commit 4d8973e20b32f1ca083cf64a5701e601b4669d01 Author: Eyck Jentzsch Date: Fri Jun 28 23:08:36 2019 +0200 Initial version diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Also_See_More_FreeRTOS+TCP_and_FreeRTOS_FAT_in_the_lab.url b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Also_See_More_FreeRTOS+TCP_and_FreeRTOS_FAT_in_the_lab.url new file mode 100644 index 0000000..dd4e342 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Also_See_More_FreeRTOS+TCP_and_FreeRTOS_FAT_in_the_lab.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 +[InternetShortcut] +URL=http://www.freertos.org/labs +IDList= diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/Common/FreeRTOS_TCP_server.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/Common/FreeRTOS_TCP_server.c new file mode 100644 index 0000000..3b9f8fb --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/Common/FreeRTOS_TCP_server.c @@ -0,0 +1,353 @@ +/* + * FreeRTOS+TCP V2.0.3 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + + +/* Standard includes. */ +#include +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_TCP_server.h" +#include "FreeRTOS_server_private.h" + +/* Remove the entire file if TCP is not being used. */ +#if( ipconfigUSE_TCP == 1 ) && ( ( ipconfigUSE_HTTP == 1 ) || ( ipconfigUSE_FTP == 1 ) ) + +#if !defined( ARRAY_SIZE ) + #define ARRAY_SIZE(x) ( BaseType_t ) (sizeof( x ) / sizeof( x )[ 0 ] ) +#endif + + +static void prvReceiveNewClient( TCPServer_t *pxServer, BaseType_t xIndex, Socket_t xNexSocket ); +static char *strnew( const char *pcString ); +/* Remove slashes at the end of a path. */ +static void prvRemoveSlash( char *pcDir ); + +TCPServer_t *FreeRTOS_CreateTCPServer( const struct xSERVER_CONFIG *pxConfigs, BaseType_t xCount ) +{ +TCPServer_t *pxServer; +SocketSet_t xSocketSet; + + /* Create a new server. + xPort / xPortAlt : Make the service available on 1 or 2 public port numbers. */ + xSocketSet = FreeRTOS_CreateSocketSet(); + + if( xSocketSet != NULL ) + { + BaseType_t xSize; + + xSize = sizeof( *pxServer ) - sizeof( pxServer->xServers ) + xCount * sizeof( pxServer->xServers[ 0 ] ); + + pxServer = ( TCPServer_t * ) pvPortMallocLarge( xSize ); + if( pxServer != NULL ) + { + struct freertos_sockaddr xAddress; + BaseType_t xNoTimeout = 0; + BaseType_t xIndex; + + memset( pxServer, '\0', xSize ); + pxServer->xServerCount = xCount; + pxServer->xSocketSet = xSocketSet; + + for( xIndex = 0; xIndex < xCount; xIndex++ ) + { + BaseType_t xPortNumber = pxConfigs[ xIndex ].xPortNumber; + + if( xPortNumber > 0 ) + { + Socket_t xSocket; + + xSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_STREAM, FREERTOS_IPPROTO_TCP ); + FreeRTOS_printf( ( "TCP socket on port %d\n", ( int )xPortNumber ) ); + + if( xSocket != FREERTOS_NO_SOCKET ) + { + xAddress.sin_addr = FreeRTOS_GetIPAddress(); // Single NIC, currently not used + xAddress.sin_port = FreeRTOS_htons( xPortNumber ); + + FreeRTOS_bind( xSocket, &xAddress, sizeof( xAddress ) ); + FreeRTOS_listen( xSocket, pxConfigs[ xIndex ].xBackLog ); + + FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_RCVTIMEO, ( void * ) &xNoTimeout, sizeof( BaseType_t ) ); + FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_SNDTIMEO, ( void * ) &xNoTimeout, sizeof( BaseType_t ) ); + + #if( ipconfigHTTP_RX_BUFSIZE > 0 ) + { + if( pxConfigs[ xIndex ].eType == eSERVER_HTTP ) + { + WinProperties_t xWinProps; + + memset( &xWinProps, '\0', sizeof( xWinProps ) ); + /* The parent socket itself won't get connected. The properties below + will be inherited by each new child socket. */ + xWinProps.lTxBufSize = ipconfigHTTP_TX_BUFSIZE; + xWinProps.lTxWinSize = ipconfigHTTP_TX_WINSIZE; + xWinProps.lRxBufSize = ipconfigHTTP_RX_BUFSIZE; + xWinProps.lRxWinSize = ipconfigHTTP_RX_WINSIZE; + + /* Set the window and buffer sizes. */ + FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_WIN_PROPERTIES, ( void * ) &xWinProps, sizeof( xWinProps ) ); + } + } + #endif + + FreeRTOS_FD_SET( xSocket, xSocketSet, eSELECT_READ|eSELECT_EXCEPT ); + pxServer->xServers[ xIndex ].xSocket = xSocket; + pxServer->xServers[ xIndex ].eType = pxConfigs[ xIndex ].eType; + pxServer->xServers[ xIndex ].pcRootDir = strnew( pxConfigs[ xIndex ].pcRootDir ); + prvRemoveSlash( ( char * ) pxServer->xServers[ xIndex ].pcRootDir ); + } + } + } + } + else + { + /* Could not allocate the server, delete the socket set */ + FreeRTOS_DeleteSocketSet( xSocketSet ); + } + } + else + { + /* Could not create a socket set, return NULL */ + pxServer = NULL; + } + + return pxServer; +} +/*-----------------------------------------------------------*/ + +static void prvReceiveNewClient( TCPServer_t *pxServer, BaseType_t xIndex, Socket_t xNexSocket ) +{ +TCPClient_t *pxClient = NULL; +BaseType_t xSize = 0; +FTCPWorkFunction fWorkFunc = NULL; +FTCPDeleteFunction fDeleteFunc = NULL; +const char *pcType = "Unknown"; + + /*_RB_ Can the work and delete functions be part of the xSERVER_CONFIG structure + becomes generic, with no pre-processing required? */ + #if( ipconfigUSE_HTTP != 0 ) + { + if( pxServer->xServers[ xIndex ].eType == eSERVER_HTTP ) + { + xSize = sizeof( HTTPClient_t ); + fWorkFunc = xHTTPClientWork; + fDeleteFunc = vHTTPClientDelete; + pcType = "HTTP"; + } + } + #endif /* ipconfigUSE_HTTP != 0 */ + + #if( ipconfigUSE_FTP != 0 ) + { + if( pxServer->xServers[ xIndex ].eType == eSERVER_FTP ) + { + xSize = sizeof( FTPClient_t ); + fWorkFunc = xFTPClientWork; + fDeleteFunc = vFTPClientDelete; + pcType = "FTP"; + } + } + #endif /* ipconfigUSE_FTP != 0 */ + + /* Malloc enough space for a new HTTP-client */ + if( xSize ) + { + pxClient = ( TCPClient_t* ) pvPortMallocLarge( xSize ); + } + + if( pxClient != NULL ) + { + memset( pxClient, '\0', xSize ); + + /* Put the new client in front of the list. */ + pxClient->eType = pxServer->xServers[ xIndex ].eType; + pxClient->pcRootDir = pxServer->xServers[ xIndex ].pcRootDir; + pxClient->pxParent = pxServer; + pxClient->xSocket = xNexSocket; + pxClient->pxNextClient = pxServer->pxClients; + pxClient->fWorkFunction = fWorkFunc; + pxClient->fDeleteFunction = fDeleteFunc; + pxServer->pxClients = pxClient; + + FreeRTOS_FD_SET( xNexSocket, pxServer->xSocketSet, eSELECT_READ|eSELECT_EXCEPT ); + } + else + { + pcType = "closed"; + FreeRTOS_closesocket( xNexSocket ); + } + { + struct freertos_sockaddr xRemoteAddress; + FreeRTOS_GetRemoteAddress( pxClient->xSocket, &xRemoteAddress ); + FreeRTOS_printf( ( "TPC-server: new %s client %xip\n", pcType, (unsigned)FreeRTOS_ntohl( xRemoteAddress.sin_addr ) ) ); + } + + /* Remove compiler warnings in case FreeRTOS_printf() is not used. */ + ( void ) pcType; +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_TCPServerWork( TCPServer_t *pxServer, TickType_t xBlockingTime ) +{ +TCPClient_t **ppxClient; +BaseType_t xIndex; +BaseType_t xRc; + + /* Let the server do one working cycle */ + xRc = FreeRTOS_select( pxServer->xSocketSet, xBlockingTime ); + + if( xRc != 0 ) + { + for( xIndex = 0; xIndex < pxServer->xServerCount; xIndex++ ) + { + struct freertos_sockaddr xAddress; + Socket_t xNexSocket; + socklen_t xSocketLength; + + if( pxServer->xServers[ xIndex ].xSocket == FREERTOS_NO_SOCKET ) + { + continue; + } + + xSocketLength = sizeof( xAddress ); + xNexSocket = FreeRTOS_accept( pxServer->xServers[ xIndex ].xSocket, &xAddress, &xSocketLength); + + if( ( xNexSocket != FREERTOS_NO_SOCKET ) && ( xNexSocket != FREERTOS_INVALID_SOCKET ) ) + { + prvReceiveNewClient( pxServer, xIndex, xNexSocket ); + } + } + } + + ppxClient = &pxServer->pxClients; + + while( ( * ppxClient ) != NULL ) + { + TCPClient_t *pxThis = *ppxClient; + + /* Almost C++ */ + xRc = pxThis->fWorkFunction( pxThis ); + + if (xRc < 0 ) + { + *ppxClient = pxThis->pxNextClient; + /* Close handles, resources */ + pxThis->fDeleteFunction( pxThis ); + /* Free the space */ + vPortFreeLarge( pxThis ); + } + else + { + ppxClient = &( pxThis->pxNextClient ); + } + } +} +/*-----------------------------------------------------------*/ + +static char *strnew( const char *pcString ) +{ +BaseType_t xLength; +char *pxBuffer; + + xLength = strlen( pcString ) + 1; + pxBuffer = ( char * ) pvPortMalloc( xLength ); + if( pxBuffer != NULL ) + { + memcpy( pxBuffer, pcString, xLength ); + } + + return pxBuffer; +} +/*-----------------------------------------------------------*/ + +static void prvRemoveSlash( char *pcDir ) +{ +BaseType_t xLength = strlen( pcDir ); + + while( ( xLength > 0 ) && ( pcDir[ xLength - 1 ] == '/' ) ) + { + pcDir[ --xLength ] = '\0'; + } +} +/*-----------------------------------------------------------*/ + +#if( ipconfigSUPPORT_SIGNALS != 0 ) + + /* FreeRTOS_TCPServerWork() calls select(). + The two functions below provide a possibility to interrupt + the call to select(). After the interruption, resume + by calling FreeRTOS_TCPServerWork() again. */ + BaseType_t FreeRTOS_TCPServerSignal( TCPServer_t *pxServer ) + { + BaseType_t xIndex; + BaseType_t xResult = pdFALSE; + for( xIndex = 0; xIndex < pxServer->xServerCount; xIndex++ ) + { + if( pxServer->xServers[ xIndex ].xSocket != FREERTOS_NO_SOCKET ) + { + FreeRTOS_SignalSocket( pxServer->xServers[ xIndex ].xSocket ); + xResult = pdTRUE; + break; + } + } + + return xResult; + } + +#endif /* ipconfigSUPPORT_SIGNALS */ +/*-----------------------------------------------------------*/ + +#if( ipconfigSUPPORT_SIGNALS != 0 ) + + /* Same as above: this function may be called from an ISR, + for instance a GPIO interrupt. */ + BaseType_t FreeRTOS_TCPServerSignalFromISR( TCPServer_t *pxServer, BaseType_t *pxHigherPriorityTaskWoken ) + { + BaseType_t xIndex; + BaseType_t xResult = pdFALSE; + for( xIndex = 0; xIndex < pxServer->xServerCount; xIndex++ ) + { + if( pxServer->xServers[ xIndex ].xSocket != FREERTOS_NO_SOCKET ) + { + FreeRTOS_SignalSocketFromISR( pxServer->xServers[ xIndex ].xSocket, pxHigherPriorityTaskWoken ); + xResult = pdTRUE; + break; + } + } + + return xResult; + } +#endif /* ipconfigSUPPORT_SIGNALS */ +/*-----------------------------------------------------------*/ + +#endif /* ( ipconfigUSE_TCP == 1 ) && ( ( ipconfigUSE_HTTP == 1 ) || ( ipconfigUSE_FTP == 1 ) ) */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/FTP/FreeRTOS_FTP_commands.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/FTP/FreeRTOS_FTP_commands.c new file mode 100644 index 0000000..b399f36 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/FTP/FreeRTOS_FTP_commands.c @@ -0,0 +1,74 @@ +/* + * FreeRTOS+TCP V2.0.3 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_FTP_commands.h" + +const FTPCommand_t xFTPCommands[ FTP_CMD_COUNT ] = +{ +/* cmdLen cmdName[7] cmdType checkLogin checkNullArg */ + { 4, "USER", ECMD_USER, pdFALSE, pdFALSE }, + { 4, "PASS", ECMD_PASS, pdFALSE, pdFALSE }, + { 4, "ACCT", ECMD_ACCT, pdTRUE, pdFALSE }, + { 3, "CWD", ECMD_CWD, pdTRUE, pdTRUE }, + { 4, "CDUP", ECMD_CDUP, pdTRUE, pdFALSE }, + { 4, "SMNT", ECMD_SMNT, pdTRUE, pdFALSE }, + { 4, "QUIT", ECMD_QUIT, pdTRUE, pdFALSE }, + { 4, "REIN", ECMD_REIN, pdTRUE, pdFALSE }, + { 4, "PORT", ECMD_PORT, pdTRUE, pdFALSE }, + { 4, "PASV", ECMD_PASV, pdTRUE, pdFALSE }, + { 4, "TYPE", ECMD_TYPE, pdTRUE, pdFALSE }, + { 4, "STRU", ECMD_STRU, pdTRUE, pdFALSE }, + { 4, "MODE", ECMD_MODE, pdTRUE, pdFALSE }, + { 4, "RETR", ECMD_RETR, pdTRUE, pdTRUE }, + { 4, "STOR", ECMD_STOR, pdTRUE, pdTRUE }, + { 4, "STOU", ECMD_STOU, pdTRUE, pdFALSE }, + { 4, "APPE", ECMD_APPE, pdTRUE, pdFALSE }, + { 4, "ALLO", ECMD_ALLO, pdTRUE, pdFALSE }, + { 4, "REST", ECMD_REST, pdTRUE, pdFALSE }, + { 4, "RNFR", ECMD_RNFR, pdTRUE, pdTRUE }, + { 4, "RNTO", ECMD_RNTO, pdTRUE, pdTRUE }, + { 4, "ABOR", ECMD_ABOR, pdTRUE, pdFALSE }, + { 4, "SIZE", ECMD_SIZE, pdTRUE, pdTRUE }, + { 4, "MDTM", ECMD_MDTM, pdTRUE, pdTRUE }, + { 4, "DELE", ECMD_DELE, pdTRUE, pdTRUE }, + { 3, "RMD", ECMD_RMD, pdTRUE, pdTRUE }, + { 3, "MKD", ECMD_MKD, pdTRUE, pdTRUE }, + { 3, "PWD", ECMD_PWD, pdTRUE, pdFALSE }, + { 4, "LIST", ECMD_LIST, pdTRUE, pdFALSE }, + { 4, "NLST", ECMD_NLST, pdTRUE, pdFALSE }, + { 4, "SITE", ECMD_SITE, pdTRUE, pdFALSE }, + { 4, "SYST", ECMD_SYST, pdFALSE, pdFALSE }, + { 4, "FEAT", ECMD_FEAT, pdFALSE, pdFALSE }, + { 4, "STAT", ECMD_STAT, pdTRUE, pdFALSE }, + { 4, "HELP", ECMD_HELP, pdFALSE, pdFALSE }, + { 4, "NOOP", ECMD_NOOP, pdFALSE, pdFALSE }, + { 4, "EMPT", ECMD_EMPTY, pdFALSE, pdFALSE }, + { 4, "CLOS", ECMD_CLOSE, pdTRUE, pdFALSE }, + { 4, "UNKN", ECMD_UNKNOWN, pdFALSE, pdFALSE }, +}; diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/FTP/FreeRTOS_FTP_server.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/FTP/FreeRTOS_FTP_server.c new file mode 100644 index 0000000..a2a6ba1 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/FTP/FreeRTOS_FTP_server.c @@ -0,0 +1,2637 @@ +/* + * FreeRTOS+TCP V2.0.3 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +/* Standard includes. */ +#include +#include +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "portmacro.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_TCP_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_Stream_Buffer.h" + +/* FreeRTOS Protocol includes. */ +#include "FreeRTOS_FTP_commands.h" +#include "FreeRTOS_TCP_server.h" +#include "FreeRTOS_server_private.h" + +/* Remove the whole file if FTP is not supported. */ +#if( ipconfigUSE_FTP == 1 ) + +#ifndef HTTP_SERVER_BACKLOG + #define HTTP_SERVER_BACKLOG ( 12 ) +#endif + +#if !defined( ARRAY_SIZE ) + #define ARRAY_SIZE( x ) ( BaseType_t ) (sizeof( x ) / sizeof( x )[ 0 ] ) +#endif + +#if defined(__WIN32__) && !defined(ipconfigFTP_FS_USES_BACKSLAH) + #define ipconfigFTP_FS_USES_BACKSLAH 1 +#endif + +/* Some defines to make the code more readbale */ +#define pcCOMMAND_BUFFER pxClient->pxParent->pcCommandBuffer +#define pcNEW_DIR pxClient->pxParent->pcNewDir +#define pcFILE_BUFFER pxClient->pxParent->pcFileBuffer + +/* This FTP server will only do binary transfers */ +#define TMODE_BINARY 1 +#define TMODE_ASCII 2 +#define TMODE_7BITS 3 +#define TMODE_8BITS 4 + +/* Ascii character definitions. */ +#define ftpASCII_CR 13 +#define ftpASCII_LF 10 + +#if defined( FTP_WRITES_ALIGNED ) || defined( ipconfigFTP_WRITES_ALIGNED ) + #error Name change : please rename the define to the new name 'ipconfigFTP_ZERO_COPY_ALIGNED_WRITES' +#endif + +/* + * ipconfigFTP_ZERO_COPY_ALIGNED_WRITES : experimental optimisation option. + * If non-zero, receiving data will be done with the zero-copy method and also + * writes to disk will be done with sector-alignment as much as possible. + */ +#ifndef ipconfigFTP_ZERO_COPY_ALIGNED_WRITES + #define ipconfigFTP_ZERO_COPY_ALIGNED_WRITES 0 +#endif + +/* + * This module only has 2 public functions: + */ +BaseType_t xFTPClientWork( TCPClient_t *pxClient ); +void vFTPClientDelete( TCPClient_t *pxClient ); + +/* + * Process a single command. + */ +static BaseType_t prvProcessCommand( FTPClient_t *pxClient, BaseType_t xIndex, char *pcRestCommand ); + +/* + * Create a socket for a data connection to the FTP client. + */ +static BaseType_t prvTransferConnect( FTPClient_t *pxClient, BaseType_t xDoListen ); + +/* + * Either call listen() or connect() to start the transfer connection. + */ +static BaseType_t prvTransferStart( FTPClient_t *pxClient ); + +/* + * See if the socket has got connected or disconnected. Close the socket if + * necessary. + */ +static void prvTransferCheck( FTPClient_t *pxClient ); + +/* + * Close the data socket and issue some informative logging. + */ +static void prvTransferCloseSocket( FTPClient_t *pxClient ); + +/* + * Close the file handle (pxReadHandle or pxWriteHandle). + */ +static void prvTransferCloseFile( FTPClient_t *pxClient ); + +/* + * Close a directory (-handle). + */ +static void prvTransferCloseDir( FTPClient_t *pxClient ); + +/* + * Translate a string (indicating a transfer type) to a number. + */ +static BaseType_t prvGetTransferType( const char *pcType ); + +#if( ipconfigHAS_PRINTF != 0 ) + /* + * For nice logging: write an amount (number of bytes), e.g. 3512200 as + * "3.45 MB" + */ + static const char *pcMkSize( uint32_t ulAmount, char *pcBuffer, BaseType_t xBufferSize ); +#endif + +#if( ipconfigHAS_PRINTF != 0 ) + /* + * Calculate the average as bytes-per-second, when amount and milliseconds + * are known. + */ + static uint32_t ulGetAverage( uint32_t ulAmount, TickType_t xDeltaMs ); +#endif + +/* + * A port command looks like: PORT h1,h2,h3,h4,p1,p2. Parse it and translate it + * to an IP-address and a port number. + */ +static UBaseType_t prvParsePortData( const char *pcCommand, uint32_t *pulIPAddress ); + +/* + * CWD: Change current working directory. + */ + +static BaseType_t prvChangeDir( FTPClient_t *pxClient, char *pcDirectory ); + +/* + * RNFR: Rename from ... + */ +static BaseType_t prvRenameFrom( FTPClient_t *pxClient, const char *pcFileName ); + +/* + * RNTO: Rename to ... + */ +static BaseType_t prvRenameTo( FTPClient_t *pxClient, const char *pcFileName ); + +/* + * SITE: Change file permissions. + */ +static BaseType_t prvSiteCmd( FTPClient_t *pxClient, char *pcRestCommand ); + +/* + * DELE: Delete a file. + */ +static BaseType_t prvDeleteFile( FTPClient_t *pxClient, char *pcFileName ); + +/* + * SIZE: get the size of a file (xSendDate = 0). + * MDTM: get data and time properties (xSendDate = 1). + */ +static BaseType_t prvSizeDateFile( FTPClient_t *pxClient, char *pcFileName, BaseType_t xSendDate ); + +/* + * MKD: Make / create a directory (xDoRemove = 0). + * RMD: Remove a directory (xDoRemove = 1). + */ +static BaseType_t prvMakeRemoveDir( FTPClient_t *pxClient, const char *pcDirectory, BaseType_t xDoRemove ); + +/* + * The next three commands: LIST, RETR and STOR all require a data socket. + * The data connection is either started with a 'PORT' or a 'PASV' command. + * Each of the commands has a prepare- (Prep) and a working- (Work) function. + * The Work function should be called as long as the data socket is open, and + * there is data to be transmitted. + */ + +/* + * LIST: Send a directory listing in Unix style. + */ +static BaseType_t prvListSendPrep( FTPClient_t *pxClient ); +static BaseType_t prvListSendWork( FTPClient_t *pxClient ); + +/* + * RETR: Send a file to the FTP client. + */ +static BaseType_t prvRetrieveFilePrep( FTPClient_t *pxClient, char *pcFileName ); +static BaseType_t prvRetrieveFileWork( FTPClient_t *pxClient ); + +/* + * STOR: Receive a file from the FTP client and store it. + */ +static BaseType_t prvStoreFilePrep( FTPClient_t *pxClient, char *pcFileName ); +static BaseType_t prvStoreFileWork( FTPClient_t *pxClient ); + +/* + * Print/format a single directory entry in Unix style. + */ +static BaseType_t prvGetFileInfoStat( FF_DirEnt_t *pxEntry, char *pcLine, BaseType_t xMaxLength ); + +/* + * Send a reply to a socket, either the command- or the data-socket. + */ +static BaseType_t prvSendReply( Socket_t xSocket, const char *pcBuffer, BaseType_t xLength ); + +/* + * Prepend the root directory (if any), plus the current working directory + * (always), to get an absolute path. + */ +BaseType_t xMakeAbsolute( FTPClient_t *pxClient, char *pcBuffer, BaseType_t xBufferLength, const char *pcPath ); + +/* + +####### ##### ###### # # ## + # ## # # # # # # # # + # # # # # # # + # # # # # # # #### ### ## # # + ##### # ##### # # # # # # # # # # + # # # # # # # # # ## # #### + # # # ## ## # # # # # + # # # ## ## # # # # # +#### #### #### ## ## #### #### ## ## + + * xFTPClientWork() + * will be called by FreeRTOS_TCPServerWork(), after select has expired(). + * FD_ISSET will not be used. This work function will always be called at + * regular intervals, and also after a select() event has occurred. + */ +BaseType_t xFTPClientWork( TCPClient_t *pxTCPClient ) +{ +FTPClient_t *pxClient = ( FTPClient_t * ) pxTCPClient; +BaseType_t xRc; + + if( pxClient->bits.bHelloSent == pdFALSE_UNSIGNED ) + { + BaseType_t xLength; + + pxClient->bits.bHelloSent = pdTRUE_UNSIGNED; + + xLength = snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), + "220 Welcome to the FreeRTOS+TCP FTP server\r\n" ); + prvSendReply( pxClient->xSocket, pcCOMMAND_BUFFER, xLength ); + } + + /* Call recv() in a non-blocking way, to see if there is an FTP command + sent to this server. */ + xRc = FreeRTOS_recv( pxClient->xSocket, ( void * )pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), 0 ); + + if( xRc > 0 ) + { + BaseType_t xIndex; + const FTPCommand_t *pxCommand; + char *pcRestCommand; + + if( xRc < ( BaseType_t ) sizeof( pcCOMMAND_BUFFER ) ) + { + pcCOMMAND_BUFFER[ xRc ] = '\0'; + } + + while( xRc && ( ( pcCOMMAND_BUFFER[ xRc - 1 ] == ftpASCII_CR ) || ( pcCOMMAND_BUFFER[ xRc - 1 ] == ftpASCII_LF ) ) ) + { + pcCOMMAND_BUFFER[ --xRc ] = '\0'; + } + + /* Now iterate through a list of FTP commands, and look for a match. */ + pxCommand = xFTPCommands; + pcRestCommand = pcCOMMAND_BUFFER; + for( xIndex = 0; xIndex < FTP_CMD_COUNT - 1; xIndex++, pxCommand++ ) + { + BaseType_t xLength; + + /* The length of each command is stored as well, just to be a bit + quicker here. */ + xLength = pxCommand->xCommandLength; + + if( ( xRc >= xLength ) && ( memcmp( ( const void * ) pxCommand->pcCommandName, ( const void * ) pcCOMMAND_BUFFER, xLength ) == 0 ) ) + { + /* A match with an existing command is found. Skip any + whitespace to get the first parameter. */ + pcRestCommand += xLength; + while( ( *pcRestCommand == ' ' ) || ( *pcRestCommand == '\t' ) ) + { + pcRestCommand++; + } + break; + } + } + + /* If the command received was not recognised, xIndex will point to a + fake entry called 'ECMD_UNKNOWN'. */ + prvProcessCommand( pxClient, xIndex, pcRestCommand ); + } + else if( xRc < 0 ) + { + /* The connection will be closed and the client will be deleted. */ + FreeRTOS_printf( ( "xFTPClientWork: xRc = %ld\n", xRc ) ); + } + + /* Does it have an open data connection? */ + if( pxClient->xTransferSocket != FREERTOS_NO_SOCKET ) + { + /* See if the connection has changed. */ + prvTransferCheck( pxClient ); + + /* "pcConnectionAck" contains a string like: + "Response: 150 Accepted data connection from 192.168.2.3:6789" + The socket can only be used once this acknowledgement has been sent. */ + if( ( pxClient->xTransferSocket != FREERTOS_NO_SOCKET ) && ( pxClient->pcConnectionAck[ 0 ] == '\0' ) ) + { + BaseType_t xClientRc = 0; + + if( pxClient->bits1.bDirHasEntry ) + { + /* Still listing a directory. */ + xClientRc = prvListSendWork( pxClient ); + } + else if( pxClient->pxReadHandle != NULL ) + { + /* Sending a file. */ + xClientRc = prvRetrieveFileWork( pxClient ); + } + else if( pxClient->pxWriteHandle != NULL ) + { + /* Receiving a file. */ + xClientRc = prvStoreFileWork( pxClient ); + } + + if( xClientRc < 0 ) + { + prvTransferCloseSocket( pxClient ); + prvTransferCloseFile( pxClient ); + } + } + } + + return xRc; +} +/*-----------------------------------------------------------*/ + +static void prvTransferCloseDir( FTPClient_t *pxClient ) +{ + /* Nothing to close for +FAT. */ + ( void ) pxClient; +} +/*-----------------------------------------------------------*/ + +void vFTPClientDelete( TCPClient_t *pxTCPClient ) +{ +FTPClient_t *pxClient = ( FTPClient_t * ) pxTCPClient; + + /* Close any directory-listing-handles (not used by +FAT ). */ + prvTransferCloseDir( pxClient ); + /* Close the data-socket. */ + prvTransferCloseSocket( pxClient ); + /* Close any open file handle. */ + prvTransferCloseFile( pxClient ); + + /* Close the FTP command socket */ + if( pxClient->xSocket != FREERTOS_NO_SOCKET ) + { + FreeRTOS_FD_CLR( pxClient->xSocket, pxClient->pxParent->xSocketSet, eSELECT_ALL ); + FreeRTOS_closesocket( pxClient->xSocket ); + pxClient->xSocket = FREERTOS_NO_SOCKET; + } +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvProcessCommand( FTPClient_t *pxClient, BaseType_t xIndex, char *pcRestCommand ) +{ +const FTPCommand_t *pxFTPCommand = &( xFTPCommands[ xIndex ] ); +const char *pcMyReply = NULL; +BaseType_t xResult = 0; + + if( ( pxFTPCommand->ucCommandType != ECMD_PASS ) && ( pxFTPCommand->ucCommandType != ECMD_PORT ) ) + { + FreeRTOS_printf( ( " %s %s\n", pxFTPCommand->pcCommandName, pcRestCommand ) ); + } + + if( ( pxFTPCommand->checkLogin != pdFALSE ) && ( pxClient->bits.bLoggedIn == pdFALSE_UNSIGNED ) ) + { + pcMyReply = REPL_530; /* Please first log in. */ + } + else if( ( pxFTPCommand->checkNullArg != pdFALSE ) && ( ( pcRestCommand == NULL ) || ( pcRestCommand[ 0 ] == '\0' ) ) ) + { + pcMyReply = REPL_501; /* Command needs a parameter. */ + } + + if( pcMyReply == NULL ) + { + switch( pxFTPCommand->ucCommandType ) + { + case ECMD_USER: /* User. */ + /* User name has been entered, expect password. */ + pxClient->bits.bStatusUser = pdTRUE_UNSIGNED; + + #if( ipconfigFTP_HAS_USER_PASSWORD_HOOK != 0 )/*_RB_ Needs defaulting and adding to the web documentation. */ + { + /* Save the user name in 'pcFileName'. */ + snprintf( pxClient->pcFileName, sizeof( pxClient->pcFileName ), "%s", pcRestCommand ); + + /* The USER name is presented to the application. The function + may return a const string like "331 Please enter your + password\r\n". */ + pcMyReply = pcApplicationFTPUserHook( pxClient->pcFileName ); + if( pcMyReply == NULL ) + { + pcMyReply = REPL_331_ANON; + } + } + #else + { + /* No password checks, any password will be accepted. */ + pcMyReply = REPL_331_ANON; + } + #endif /* ipconfigFTP_HAS_USER_PASSWORD_HOOK != 0 */ + + #if( ipconfigFTP_HAS_USER_PROPERTIES_HOOK != 0 )/*_RB_ Needs defaulting and adding to the web documentation. */ + { + FTPUserProperties_t xProperties; + + xProperties.pcRootDir = pxClient->pcRootDir; + xProperties.xReadOnly = pdFALSE; + xProperties.usPortNumber = pxClient->usClientPort; + vApplicationFTPUserPropertiesHook( pxClient->pcFileName, &( xProperties ) ); + + if( xProperties.pcRootDir != NULL ) + { + pxClient->pcRootDir = xProperties.pcRootDir; + } + pxClient->bits.bReadOnly = ( xProperties.xReadOnly != pdFALSE_UNSIGNED ); + } + #endif /* ipconfigFTP_HAS_USER_PROPERTIES_HOOK */ + break; + + case ECMD_PASS: /* Password. */ + pxClient->ulRestartOffset = 0; + if( pxClient->bits.bStatusUser == pdFALSE_UNSIGNED ) + { + pcMyReply = REPL_503; /* "503 Bad sequence of commands.\r\n". */ + } + else + { + BaseType_t xAllow; + + pxClient->bits.bStatusUser = pdFALSE_UNSIGNED; + #if( ipconfigFTP_HAS_USER_PASSWORD_HOOK != 0 ) + { + xAllow = xApplicationFTPPasswordHook( pxClient->pcFileName, pcRestCommand ); + } + #else + { + xAllow = 1; + } + #endif /* ipconfigFTP_HAS_USER_PASSWORD_HOOK */ + + if( xAllow > 0 ) + { + pxClient->bits.bLoggedIn = pdTRUE_UNSIGNED; /* Client has now logged in. */ + pcMyReply = "230 OK. Current directory is /\r\n"; + } + else + { + pcMyReply = "530 Login incorrect\r\n"; /* 530 Login incorrect. */ + } + + strcpy( pxClient->pcCurrentDir, ( const char * ) "/" ); + } + break; + + case ECMD_SYST: /* System. */ + snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), "215 UNIX Type: L8\r\n" ); + pcMyReply = pcCOMMAND_BUFFER; + break; + + case ECMD_PWD: /* Get working directory. */ + xMakeRelative( pxClient, pcFILE_BUFFER, sizeof( pcFILE_BUFFER ), pxClient->pcCurrentDir ); + snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), REPL_257_PWD, pcFILE_BUFFER ); + pcMyReply = pcCOMMAND_BUFFER; + break; + + case ECMD_REST: + if( pxClient->bits.bReadOnly != pdFALSE_UNSIGNED ) + { + pcMyReply = REPL_553_READ_ONLY; + } + else + { + const char *pcPtr = pcRestCommand; + + while( *pcPtr == ' ' ) + { + pcPtr++; + } + + if( ( *pcPtr >= '0' ) && ( *pcPtr <= '9' ) ) + { + sscanf( pcPtr, "%lu", &pxClient->ulRestartOffset ); + snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), + "350 Restarting at %lu. Send STORE or RETRIEVE\r\n", pxClient->ulRestartOffset ); + pcMyReply = pcCOMMAND_BUFFER; + } + else + { + pcMyReply = REPL_500; /* 500 Syntax error, command unrecognised. */ + } + } + break; + + case ECMD_NOOP: /* NOP operation */ + if( pxClient->xTransferSocket != FREERTOS_NO_SOCKET ) + { + pcMyReply = REPL_200_PROGRESS; + } + else + { + pcMyReply = REPL_200; + } + break; + + case ECMD_TYPE: /* Ask or set transfer type. */ + { + /* e.g. "TYPE I" for Images (binary). */ + BaseType_t xType = prvGetTransferType( pcRestCommand ); + + if( xType < 0 ) + { + /* TYPE not recognised. */ + pcMyReply = REPL_500; + } + else + { + pxClient->xTransType = xType; + pcMyReply = REPL_200; + } + } + break; + + case ECMD_PASV: /* Enter passive mode. */ + /* Connect passive: Server will listen() and wait for a connection. + Start up a new data connection with 'xDoListen' set to true. */ + if( prvTransferConnect( pxClient, pdTRUE ) == pdFALSE ) + { + pcMyReply = REPL_502; + } + else + { + uint32_t ulIP; + uint16_t ulPort; + struct freertos_sockaddr xLocalAddress; + struct freertos_sockaddr xRemoteAddress; + + FreeRTOS_GetLocalAddress( pxClient->xTransferSocket, &xLocalAddress ); + FreeRTOS_GetRemoteAddress( pxClient->xSocket, &xRemoteAddress ); + + ulIP = FreeRTOS_ntohl( xLocalAddress.sin_addr ); + pxClient->ulClientIP = FreeRTOS_ntohl( xRemoteAddress.sin_addr ); + ulPort = FreeRTOS_ntohs( xLocalAddress.sin_port ); + + pxClient->usClientPort = FreeRTOS_ntohs( xRemoteAddress.sin_port ); + + /* REPL_227_D "227 Entering Passive Mode (%d,%d,%d,%d,%d,%d). */ + snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), REPL_227_D, + ( unsigned )ulIP >> 24, + ( unsigned )( ulIP >> 16 ) & 0xFF, + ( unsigned )( ulIP >> 8 ) & 0xFF, + ( unsigned )ulIP & 0xFF, + ( unsigned )ulPort >> 8, + ( unsigned )ulPort & 0xFF ); + + pcMyReply = pcCOMMAND_BUFFER; + } + break; + + case ECMD_PORT: /* Active connection to the client. */ + /* The client uses this command to tell the server to what + client-side port the server should contact; use of this command + indicates an active data transfer. e.g. PORT 192,168,1,2,4,19. */ + { + uint32_t ulIPAddress = 0; + UBaseType_t uxPort; + + uxPort = prvParsePortData( pcRestCommand, &ulIPAddress ); + FreeRTOS_printf( (" PORT %lxip:%ld\n", ulIPAddress, uxPort ) ); + + if( uxPort == 0u ) + { + pcMyReply = REPL_501; + } + else if( prvTransferConnect( pxClient, pdFALSE ) == pdFALSE ) + { + /* Call prvTransferConnect() with 'xDoListen' = false for an + active connect(). */ + pcMyReply = REPL_501; + } + else + { + pxClient->usClientPort = ( uint16_t ) uxPort; + pxClient->ulClientIP = ulIPAddress; + FreeRTOS_printf( ("Client address %lxip:%lu\n", ulIPAddress, uxPort ) ); + pcMyReply = REPL_200; + } + } + break; + + case ECMD_CWD: /* Change current working directory. */ + prvChangeDir( pxClient, pcRestCommand ); + break; + + case ECMD_RNFR: + if( pxClient->bits.bReadOnly != pdFALSE_UNSIGNED ) + { + pcMyReply = REPL_553_READ_ONLY; + } + else + { + prvRenameFrom( pxClient, pcRestCommand ); + } + break; + + case ECMD_RNTO: + if( pxClient->bits.bInRename == pdFALSE_UNSIGNED ) + { + pcMyReply = REPL_503; /* "503 Bad sequence of commands. */ + } + else + { + prvRenameTo( pxClient, pcRestCommand ); + } + break; + + case ECMD_SITE: /* Set file permissions */ + if( pxClient->bits.bReadOnly != pdFALSE_UNSIGNED ) + { + pcMyReply = REPL_553_READ_ONLY; + } + else if( prvSiteCmd( pxClient, pcRestCommand ) == pdFALSE ) + { + pcMyReply = REPL_202; + } + break; + + case ECMD_DELE: + if( pxClient->bits.bReadOnly != pdFALSE_UNSIGNED ) + { + pcMyReply = REPL_553_READ_ONLY; + } + else + { + prvDeleteFile( pxClient, pcRestCommand ); + } + break; + + case ECMD_MDTM: + prvSizeDateFile( pxClient, pcRestCommand, pdTRUE ); + break; + + case ECMD_SIZE: + if( pxClient->pxWriteHandle != NULL ) + { + /* This SIZE query is probably about a file which is now being + received. If so, return the value of pxClient->ulRecvBytes, + pcRestCommand points to 'pcCommandBuffer', make it free by + copying it to pcNewDir. */ + + xMakeAbsolute( pxClient, pcNEW_DIR, sizeof( pcNEW_DIR ), pcRestCommand ); + + if( strcmp( pcNEW_DIR, pcRestCommand ) == 0 ) + { + BaseType_t xCount; + for( xCount = 0; xCount < 3 && pxClient->pxWriteHandle; xCount++ ) + { + prvStoreFileWork( pxClient ); + } + if( pxClient->pxWriteHandle != NULL ) + { + /* File being queried is still open, return number of + bytes received until now. */ + snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), "213 %lu\r\n", pxClient->ulRecvBytes ); + pcMyReply = pcCOMMAND_BUFFER; + } /* otherwise, do a normal stat(). */ + } + strcpy( pcRestCommand, pcNEW_DIR ); + } + if( pcMyReply == NULL ) + { + prvSizeDateFile( pxClient, pcRestCommand, pdFALSE ); + } + break; + case ECMD_MKD: + case ECMD_RMD: + if( pxClient->bits.bReadOnly != pdFALSE_UNSIGNED ) + { + pcMyReply = REPL_553_READ_ONLY; + } + else + { + prvMakeRemoveDir( pxClient, pcRestCommand, pxFTPCommand->ucCommandType == ECMD_RMD ); + } + break; + case ECMD_CDUP: + prvChangeDir( pxClient, ".." ); + break; + + case ECMD_QUIT: + prvSendReply( pxClient->xSocket, REPL_221, 0 ); + pxClient->bits.bLoggedIn = pdFALSE_UNSIGNED; + break; + case ECMD_LIST: + case ECMD_RETR: + case ECMD_STOR: + if( ( pxClient->xTransferSocket == FREERTOS_NO_SOCKET ) && + ( ( pxFTPCommand->ucCommandType != ECMD_STOR ) || + ( pxClient->bits1.bEmptyFile == pdFALSE_UNSIGNED ) ) ) + { + /* Sending "425 Can't open data connection." : + Before receiving any of these commands, there must have been a + PORT or PASV command, which causes the creation of a data socket. */ + /* There is one exception: a STOR command is received while the + data connection has already been closed. This is tested with the + 'bEmptyFile' flag. */ + pcMyReply = REPL_425; + } + else + { + /* In case an empty file was received ( bits1.bEmptyFile ), the + transfer socket never delivered any data. Check if the transfer + socket is still open: */ + if( pxClient->xTransferSocket != FREERTOS_NO_SOCKET ) + { + prvTransferCheck( pxClient ); + } + switch( pxFTPCommand->ucCommandType ) + { + case ECMD_LIST: + prvListSendPrep( pxClient ); + break; + case ECMD_RETR: + prvRetrieveFilePrep( pxClient, pcRestCommand ); + break; + case ECMD_STOR: + if( pxClient->bits.bReadOnly != pdFALSE_UNSIGNED ) + { + pcMyReply = REPL_553_READ_ONLY; + } + else + { + prvStoreFilePrep( pxClient, pcRestCommand ); + if( pxClient->bits1.bEmptyFile != pdFALSE_UNSIGNED ) + { + /* Although the 'xTransferSocket' is closed already, + call this function just for the logging. */ + prvTransferCloseSocket( pxClient ); + + /* Close an empty file. */ + prvTransferCloseFile( pxClient ); + } + } + break; + } + } + break; + + case ECMD_FEAT: + { + static const char pcFeatAnswer[] = + "211-Features:\x0a" + /* The MDTM command is only allowed when + there is support for date&time. */ + #if( ffconfigTIME_SUPPORT != 0 ) + " MDTM\x0a" + #endif + " REST STREAM\x0a" + " SIZE\x0d\x0a" + "211 End\x0d\x0a"; + pcMyReply = pcFeatAnswer; + } + break; + + case ECMD_UNKNOWN: + FreeRTOS_printf( ("ftp::processCmd: Cmd %s unknown\n", pcRestCommand ) ); + pcMyReply = REPL_500; + break; + } + } + if( pxFTPCommand->ucCommandType != ECMD_RNFR ) + { + pxClient->bits.bInRename = pdFALSE_UNSIGNED; + } + + if( pcMyReply != NULL ) + { + xResult = prvSendReply( pxClient->xSocket, pcMyReply, strlen( pcMyReply ) ); + } + + return xResult; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTransferConnect( FTPClient_t *pxClient, BaseType_t xDoListen ) +{ +Socket_t xSocket; +BaseType_t xResult; + + /* Open a socket for a data connection with the FTP client. + Happens after a PORT or a PASV command. */ + + /* Make sure the previous socket is deleted and flags reset */ + prvTransferCloseSocket( pxClient ); + + pxClient->bits1.bEmptyFile = pdFALSE_UNSIGNED; + + xSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_STREAM, FREERTOS_IPPROTO_TCP ); + + if( ( xSocket != FREERTOS_NO_SOCKET ) && ( xSocket != FREERTOS_INVALID_SOCKET ) ) + { + BaseType_t xSmallTimeout = pdMS_TO_TICKS( 100 ); + struct freertos_sockaddr xAddress; + + #if( ipconfigFTP_TX_BUFSIZE > 0 ) + WinProperties_t xWinProps; + #endif + xAddress.sin_addr = FreeRTOS_GetIPAddress( ); /* Single NIC, currently not used */ + xAddress.sin_port = FreeRTOS_htons( 0 ); /* Bind to any available port number */ + + FreeRTOS_bind( xSocket, &xAddress, sizeof( xAddress ) ); + + #if( ipconfigFTP_TX_BUFSIZE > 0 ) + { + /* Fill in the buffer and window sizes that will be used by the + socket. */ + xWinProps.lTxBufSize = ipconfigFTP_TX_BUFSIZE; + xWinProps.lTxWinSize = ipconfigFTP_TX_WINSIZE; + xWinProps.lRxBufSize = ipconfigFTP_RX_BUFSIZE; + xWinProps.lRxWinSize = ipconfigFTP_RX_WINSIZE; + + /* Set the window and buffer sizes. */ + FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_WIN_PROPERTIES, ( void * ) &xWinProps, sizeof( xWinProps ) ); + } + #endif + + FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_RCVTIMEO, ( void * ) &xSmallTimeout, sizeof( BaseType_t ) ); + FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_SNDTIMEO, ( void * ) &xSmallTimeout, sizeof( BaseType_t ) ); + + /* The same instance of the socket will be used for the connection and + data transport. */ + if( xDoListen != pdFALSE ) + { + BaseType_t xTrueValue = pdTRUE; + FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_REUSE_LISTEN_SOCKET, ( void * ) &xTrueValue, sizeof( xTrueValue ) ); + } + pxClient->bits1.bIsListen = xDoListen; + pxClient->xTransferSocket = xSocket; + + if( xDoListen != pdFALSE ) + { + FreeRTOS_FD_SET( xSocket, pxClient->pxParent->xSocketSet, eSELECT_EXCEPT | eSELECT_READ ); + /* Calling FreeRTOS_listen( ) */ + xResult = prvTransferStart( pxClient ); + if( xResult >= 0 ) + { + xResult = pdTRUE; + } + } + else + { + FreeRTOS_FD_SET( xSocket, pxClient->pxParent->xSocketSet, eSELECT_EXCEPT | eSELECT_READ | eSELECT_WRITE ); + xResult = pdTRUE; + } + } + else + { + FreeRTOS_printf( ( "FreeRTOS_socket() failed\n" ) ); + xResult = -pdFREERTOS_ERRNO_ENOMEM; + } + + /* An active socket (PORT) should connect() later. */ + return xResult; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTransferStart( FTPClient_t *pxClient ) +{ +BaseType_t xResult; + + /* A transfer socket has been opened, now either call listen() for 'PASV' + or connect() for the 'PORT' command. */ + if( pxClient->bits1.bIsListen != pdFALSE_UNSIGNED ) + { + xResult = FreeRTOS_listen( pxClient->xTransferSocket, 1 ); + } + else + { + struct freertos_sockaddr xAddress; + + xAddress.sin_addr = FreeRTOS_htonl( pxClient->ulClientIP ); + xAddress.sin_port = FreeRTOS_htons( pxClient->usClientPort ); + /* Start an active connection for this data socket */ + xResult = FreeRTOS_connect( pxClient->xTransferSocket, &xAddress, sizeof( xAddress ) ); + } + + return xResult; +} +/*-----------------------------------------------------------*/ + +static void prvTransferCheck( FTPClient_t *pxClient ) +{ +BaseType_t xRxSize; + + /* A data transfer is busy. Check if there are changes in connectedness. */ + xRxSize = FreeRTOS_rx_size( pxClient->xTransferSocket ); + + if( pxClient->bits1.bClientConnected == pdFALSE_UNSIGNED ) + { + /* The time to receive a small file can be so short, that we don't even + see that the socket gets connected and disconnected. Therefore, check + the sizeof of the RX buffer. */ + { + struct freertos_sockaddr xAddress; + Socket_t xNexSocket; + socklen_t xSocketLength = sizeof( xAddress ); + + if( pxClient->bits1.bIsListen != pdFALSE_UNSIGNED ) + { + xNexSocket = FreeRTOS_accept( pxClient->xTransferSocket, &xAddress, &xSocketLength); + if( ( ( xNexSocket != FREERTOS_NO_SOCKET ) && ( xNexSocket != FREERTOS_INVALID_SOCKET ) ) || + xRxSize > 0 ) + { + pxClient->bits1.bClientConnected = pdTRUE_UNSIGNED; + } + } + else + { + if( FreeRTOS_issocketconnected( pxClient->xTransferSocket ) > 0 || + xRxSize > 0 ) + { + pxClient->bits1.bClientConnected = pdTRUE_UNSIGNED; + } + } + if( pxClient->bits1.bClientConnected != pdFALSE_UNSIGNED ) + { + pxClient->bits1.bEmptyFile = pdFALSE_UNSIGNED; + #if( ipconfigHAS_PRINTF != 0 ) + { + struct freertos_sockaddr xRemoteAddress, xLocalAddress; + FreeRTOS_GetRemoteAddress( pxClient->xTransferSocket, &xRemoteAddress ); + FreeRTOS_GetLocalAddress( pxClient->xTransferSocket, &xLocalAddress ); + FreeRTOS_printf( ( "%s Connected from %u to %u\n", + pxClient->bits1.bIsListen != pdFALSE_UNSIGNED ? "PASV" : "PORT", + ( unsigned ) FreeRTOS_ntohs( xLocalAddress.sin_port ), + ( unsigned ) FreeRTOS_ntohs( xRemoteAddress.sin_port ) ) ); + } + #endif /* ipconfigHAS_PRINTF */ + FreeRTOS_FD_CLR( pxClient->xTransferSocket, pxClient->pxParent->xSocketSet, eSELECT_WRITE ); + FreeRTOS_FD_SET( pxClient->xTransferSocket, pxClient->pxParent->xSocketSet, eSELECT_READ|eSELECT_EXCEPT ); + } + } + } + + if ( pxClient->bits1.bClientConnected != pdFALSE_UNSIGNED ) + { + if( pxClient->pcConnectionAck[ 0 ] != '\0' ) + { + BaseType_t xLength; + BaseType_t xRemotePort; + struct freertos_sockaddr xRemoteAddress; + + FreeRTOS_GetRemoteAddress( pxClient->xTransferSocket, &xRemoteAddress ); + xRemotePort = FreeRTOS_ntohs( xRemoteAddress.sin_port ); + + /* Tell on the command port 21 we have a data connection */ + xLength = snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), + pxClient->pcConnectionAck, pxClient->ulClientIP, xRemotePort ); + + prvSendReply( pxClient->xSocket, pcCOMMAND_BUFFER, xLength ); + pxClient->pcConnectionAck[ 0 ] = '\0'; + } + + if( ( FreeRTOS_issocketconnected( pxClient->xTransferSocket ) == pdFALSE ) && FreeRTOS_rx_size( pxClient->xTransferSocket ) == 0 ) + { + prvTransferCloseSocket( pxClient ); + prvTransferCloseFile( pxClient ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvTransferCloseSocket( FTPClient_t *pxClient ) +{ + if( pxClient->xTransferSocket != FREERTOS_NO_SOCKET ) + { + /* DEBUGGING ONLY */ + BaseType_t xRxSize = FreeRTOS_rx_size( pxClient->xTransferSocket ); + if( xRxSize > 0 ) + { + BaseType_t xRxSize2; + BaseType_t xStatus; + prvStoreFileWork( pxClient ); + xStatus = FreeRTOS_connstatus( pxClient->xTransferSocket ); + xRxSize2 = FreeRTOS_rx_size( pxClient->xTransferSocket ); + FreeRTOS_printf( ( "FTP: WARNING: %s: RX size = %ld -> %ld (%s)\n", + FreeRTOS_GetTCPStateName( xStatus ), + xRxSize, xRxSize2, pxClient->pcFileName ) ); + if( xRxSize2 > 1 ) + { + return; + } + + /* Remove compiler warnings in case FreeRTOS_printf() is not + defined. */ + ( void ) xStatus; + } + } + + if( ( pxClient->pxWriteHandle != NULL ) || ( pxClient->pxReadHandle != NULL ) ) + { + BaseType_t xLength; + char pcStrBuf[ 32 ]; + + if( pxClient->bits1.bHadError == pdFALSE_UNSIGNED ) + { + xLength = snprintf( pxClient->pcClientAck, sizeof( pxClient->pcClientAck ), + "226 Closing connection %d bytes transmitted\r\n", ( int ) pxClient->ulRecvBytes ); + } + else + { + xLength = snprintf( pxClient->pcClientAck, sizeof( pxClient->pcClientAck ), + "451 Requested action aborted after %d bytes\r\n", ( int ) pxClient->ulRecvBytes ); + } + + /* Tell on the command socket the data connection is now closed. */ + prvSendReply( pxClient->xSocket, pxClient->pcClientAck, xLength ); + + #if( ipconfigHAS_PRINTF != 0 ) + { + TickType_t xDelta; + uint32_t ulAverage; + xDelta = xTaskGetTickCount( ) - pxClient->xStartTime; + ulAverage = ulGetAverage( pxClient->ulRecvBytes, xDelta ); + + FreeRTOS_printf( ("FTP: %s: '%s' %lu Bytes (%s/sec)\n", + pxClient->pxReadHandle ? "sent" : "recv", + pxClient->pcFileName, + pxClient->ulRecvBytes, + pcMkSize( ulAverage, pcStrBuf, sizeof( pcStrBuf ) ) ) ); + } + #endif + } + + if( pxClient->xTransferSocket != FREERTOS_NO_SOCKET ) + { + FreeRTOS_FD_CLR( pxClient->xTransferSocket, pxClient->pxParent->xSocketSet, eSELECT_ALL ); + FreeRTOS_closesocket( pxClient->xTransferSocket ); + pxClient->xTransferSocket = FREERTOS_NO_SOCKET; + if( pxClient->ulRecvBytes == 0ul ) + { + /* Received zero bytes: an empty file */ + pxClient->bits1.bEmptyFile = pdTRUE_UNSIGNED; + } + else + { + pxClient->bits1.bEmptyFile = pdFALSE_UNSIGNED; + } + } + pxClient->bits1.bIsListen = pdFALSE_UNSIGNED; + pxClient->bits1.bDirHasEntry = pdFALSE_UNSIGNED; + pxClient->bits1.bClientConnected = pdFALSE_UNSIGNED; + pxClient->bits1.bHadError = pdFALSE_UNSIGNED; +} +/*-----------------------------------------------------------*/ + +static void prvTransferCloseFile( FTPClient_t *pxClient ) +{ + if( pxClient->pxWriteHandle != NULL ) + { + ff_fclose( pxClient->pxWriteHandle ); + pxClient->pxWriteHandle = NULL; + #if( ipconfigFTP_HAS_RECEIVED_HOOK != 0 ) + { + vApplicationFTPReceivedHook( pxClient->pcFileName, pxClient->ulRecvBytes, pxClient ); + } + #endif + + } + if( pxClient->pxReadHandle != NULL ) + { + ff_fclose( pxClient->pxReadHandle ); + pxClient->pxReadHandle = NULL; + } + /* These two field are only used for logging / file-statistics */ + pxClient->ulRecvBytes = 0ul; + pxClient->xStartTime = 0ul; +} +/*-----------------------------------------------------------*/ + +/** + * Guess the transfer type, given the client requested type. + * Actually in unix there is no difference between binary and + * ascii mode when we work with file descriptors. + * If #type is not recognized as a valid client request, -1 is returned. + */ +static BaseType_t prvGetTransferType( const char *pcType ) +{ +BaseType_t xResult = -1; + + if( pcType != NULL ) + { + BaseType_t xLength = strlen( pcType ); + if( xLength == 0 ) + { + return -1; + } + switch( pcType[ 0 ] ) { + case 'I': + xResult = TMODE_BINARY; + break; + case 'A': + xResult = TMODE_ASCII; + break; + case 'L': + if( xLength >= 3 ) + { + if( pcType[ 2 ] == '7' ) + { + xResult = TMODE_7BITS; + } + else if( pcType[ 2 ] == '8' ) + { + xResult = TMODE_7BITS; + } + } + break; + } + } + return xResult; +} +/*-----------------------------------------------------------*/ + +#if( ipconfigHAS_PRINTF != 0 ) + #define SIZE_1_GB ( 1024ul * 1024ul * 1024ul ) + #define SIZE_1_MB ( 1024ul * 1024ul ) + #define SIZE_1_KB ( 1024ul ) + + static const char *pcMkSize( uint32_t ulAmount, char *pcBuffer, BaseType_t xBufferSize ) + { + uint32_t ulGB, ulMB, ulKB, ulByte; + + ulGB = ( ulAmount / SIZE_1_GB ); + ulAmount -= ( ulGB * SIZE_1_GB ); + ulMB = ( ulAmount / SIZE_1_MB ); + ulAmount -= ( ulMB * SIZE_1_MB ); + ulKB = ( ulAmount / SIZE_1_KB ); + ulAmount -= ( ulKB * SIZE_1_KB ); + ulByte = ( ulAmount ); + + if (ulGB != 0ul ) + { + snprintf( pcBuffer, xBufferSize, "%lu.%02lu GB", ulGB, (100 * ulMB) / SIZE_1_KB ); + } + else if( ulMB != 0ul ) + { + snprintf( pcBuffer, xBufferSize, "%lu.%02lu MB", ulMB, (100 * ulKB) / SIZE_1_KB ); + } + else if( ulKB != 0ul ) + { + snprintf(pcBuffer, xBufferSize, "%lu.%02lu KB", ulKB, (100 * ulByte) / SIZE_1_KB ); + } + else + { + snprintf( pcBuffer, xBufferSize, "%lu bytes", ulByte ); + } + + return pcBuffer; + } + /*-----------------------------------------------------------*/ +#endif /* ipconfigHAS_PRINTF != 0 */ + +#if( ipconfigHAS_PRINTF != 0 ) + static uint32_t ulGetAverage( uint32_t ulAmount, TickType_t xDeltaMs ) + { + uint32_t ulAverage; + + /* Get the average amount of bytes per seconds. Ideally this is + calculated by Multiplying with 1000 and dividing by milliseconds: + ulAverage = ( 1000ul * ulAmount ) / xDeltaMs; + Now get a maximum precision, while avoiding an arithmetic overflow: + */ + if( xDeltaMs == 0ul ) + { + /* Time is zero, there is no average */ + ulAverage = 0ul; + } + else if( ulAmount >= ( ~0ul / 10ul ) ) + { + /* More than 409 MB has been transferred, do not multiply. */ + ulAverage = ( ulAmount / ( xDeltaMs / 1000ul ) ); + } + else if( ulAmount >= ( ~0ul / 100ul ) ) + { + /* Between 409 and 41 MB has been transferred, can multiply by 10. */ + ulAverage = ( ( ulAmount * 10ul ) / ( xDeltaMs / 100ul ) ); + } + else if( ulAmount >= ( ~0ul / 1000ul ) ) + { + /* Between 4.1 MB and 41 has been transferred, can multiply by 100. */ + ulAverage = ( ( ulAmount * 100ul ) / ( xDeltaMs / 10ul ) ); + } + else + { + /* Less than 4.1 MB: can multiply by 1000. */ + ulAverage = ( ( ulAmount * 1000ul ) / xDeltaMs ); + } + + return ulAverage; + } + /*-----------------------------------------------------------*/ +#endif /* ipconfigHAS_PRINTF != 0 */ + +static UBaseType_t prvParsePortData( const char *pcCommand, uint32_t *pulIPAddress ) +{ +/*_HT_ Using 'unsigned' here because when sscanf() sees '%u', it expects a pointer to 'unsigned'. +Not sure about the sscanf() format for UBaseType_t ? */ +unsigned h1, h2, h3, h4, p1, p2; +char sep; +UBaseType_t uxResult; + + /* Expect PORT h1,h2,h3,h4,p1,p2 */ + if (sscanf (pcCommand, "%u%c%u%c%u%c%u%c%u%c%u", &h1, &sep, &h2, &sep, &h3, &sep, &h4, &sep, &p1, &sep, &p2) != 11) + { + uxResult= 0u; + } + else + { + /* Put in network byte order. */ + *pulIPAddress = + ( ( uint32_t ) h1 << 24 ) | + ( ( uint32_t ) h2 << 16 ) | + ( ( uint32_t ) h3 << 8 ) | + ( ( uint32_t ) h4 ); + uxResult = ( p1 << 8 ) | p2; + } + return uxResult; +} +/*-----------------------------------------------------------*/ + +/* + + #### ####### # ### +# # # # ## # # +# # # # # # +# ###### #### ### ## #### # # ### # #### + ## # # # # # # # # ##### # # # # + ## # # # ## # ###### # # # # ###### +# # # # # # # # # # # +# # # ## # # # # ## # # # # ## + #### ## #### #### #### #### ##### ##### #### + +*/ + +static BaseType_t prvStoreFilePrep( FTPClient_t *pxClient, char *pcFileName ) +{ +BaseType_t xResult; +FF_FILE *pxNewHandle; +size_t uxFileSize = 0ul; +int iErrorNo; + + /* Close previous handle (if any) and reset file transfer parameters. */ + prvTransferCloseFile( pxClient ); + + xMakeAbsolute( pxClient, pxClient->pcFileName, sizeof( pxClient->pcFileName ), pcFileName ); + + pxNewHandle = NULL; + + if( pxClient->ulRestartOffset != 0 ) + { + size_t uxOffset = pxClient->ulRestartOffset; + int32_t lRc; + + pxClient->ulRestartOffset = 0ul; /* Only use 1 time. */ + pxNewHandle = ff_fopen( pxClient->pcFileName, "ab" ); + + if( pxNewHandle != NULL ) + { + uxFileSize = pxNewHandle->ulFileSize; + + if( uxOffset <= uxFileSize ) + { + lRc = ff_fseek( pxNewHandle, uxOffset, FF_SEEK_SET ); + } + else + { + /* Won't even try to seek after EOF */ + lRc = -pdFREERTOS_ERRNO_EINVAL; + } + if( lRc != 0 ) + { + BaseType_t xLength; + + xLength = snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), + "450 Seek invalid %u length %u\r\n", + ( unsigned ) uxOffset, ( unsigned ) uxFileSize ); + + /* "Requested file action not taken". */ + prvSendReply( pxClient->xSocket, pcCOMMAND_BUFFER, xLength ); + + FreeRTOS_printf( ( "ftp::storeFile: create %s: Seek %u length %u\n", + pxClient->pcFileName, ( unsigned ) uxOffset, ( unsigned ) uxFileSize ) ); + + ff_fclose( pxNewHandle ); + pxNewHandle = NULL; + } + } + } + else + { + pxNewHandle = ff_fopen( pxClient->pcFileName, "wb" ); + } + + if( pxNewHandle == NULL ) + { + iErrorNo = stdioGET_ERRNO(); + if( iErrorNo == pdFREERTOS_ERRNO_ENOSPC ) + { + prvSendReply( pxClient->xSocket, REPL_552, 0 ); + } + else + { + /* "Requested file action not taken". */ + prvSendReply( pxClient->xSocket, REPL_450, 0 ); + } + FreeRTOS_printf( ( "ftp::storeFile: create %s: %s (errno %d)\n", + pxClient->pcFileName, + ( const char* ) strerror( iErrorNo ), iErrorNo ) ); + + xResult = pdFALSE; + } + else + { + if( pxClient->bits1.bIsListen ) + { + /* True if PASV is used. */ + snprintf( pxClient->pcConnectionAck, sizeof( pxClient->pcConnectionAck ), + "150 Accepted data connection from %%xip:%%u\r\n" ); + prvTransferCheck( pxClient ); + } + else + { + BaseType_t xLength; + + xLength = snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), "150 Opening BIN connection to store file\r\n" ); + prvSendReply( pxClient->xSocket, pcCOMMAND_BUFFER, xLength ); + pxClient->pcConnectionAck[ 0 ] = '\0'; + prvTransferStart( pxClient ); /* Now active connect. */ + } + + pxClient->pxWriteHandle = pxNewHandle; + + /* To get some statistics about the performance. */ + pxClient->xStartTime = xTaskGetTickCount( ); + + xResult = pdTRUE; + } + + return xResult; +} +/*-----------------------------------------------------------*/ + +#if( ipconfigFTP_ZERO_COPY_ALIGNED_WRITES == 0 ) + + static BaseType_t prvStoreFileWork( FTPClient_t *pxClient ) + { + BaseType_t xRc, xWritten; + + /* Read from the data socket until all has been read or until a negative value + is returned. */ + for( ; ; ) + { + char *pcBuffer; + + /* The "zero-copy" method: */ + xRc = FreeRTOS_recv( pxClient->xTransferSocket, ( void * ) &pcBuffer, + 0x20000u, FREERTOS_ZERO_COPY | FREERTOS_MSG_DONTWAIT ); + if( xRc <= 0 ) + { + break; + } + pxClient->ulRecvBytes += xRc; + xWritten = ff_fwrite( pcBuffer, 1, xRc, pxClient->pxWriteHandle ); + FreeRTOS_recv( pxClient->xTransferSocket, ( void * ) NULL, xRc, 0 ); + if( xWritten != xRc ) + { + xRc = -1; + /* bHadError: a transfer got aborted because of an error. */ + pxClient->bits1.bHadError = pdTRUE_UNSIGNED; + break; + } + } + return xRc; + } + +#else /* ipconfigFTP_ZERO_COPY_ALIGNED_WRITES != 0 */ + + #if !defined( ipconfigFTP_PREFERRED_WRITE_SIZE ) + /* If you store data on flash, it may be profitable to give 'ipconfigFTP_PREFERRED_WRITE_SIZE' + the same size as the size of the flash' erase blocks, e.g. 4KB */ + #define ipconfigFTP_PREFERRED_WRITE_SIZE 512ul + #endif + + static BaseType_t prvStoreFileWork( FTPClient_t *pxClient ) + { + BaseType_t xRc, xWritten; + + /* Read from the data socket until all has been read or until a negative + value is returned. */ + for( ; ; ) + { + char *pcBuffer; + UBaseType_t xStatus; + + /* The "zero-copy" method: */ + xRc = FreeRTOS_recv( pxClient->xTransferSocket, ( void * ) &pcBuffer, + 0x20000u, FREERTOS_ZERO_COPY | FREERTOS_MSG_DONTWAIT ); + + if( xRc <= 0 ) + { + /* There are no data or the connection is closed. */ + break; + } + xStatus = FreeRTOS_connstatus( pxClient->xTransferSocket ); + if( xStatus != eESTABLISHED ) + { + /* The connection is not established (any more), therefore + accept any amount of bytes, probably the last few bytes. */ + } + else + { + if( xRc >= ipconfigFTP_PREFERRED_WRITE_SIZE ) + { + /* More than a sector to write, round down to a multiple of + PREFERRED_WRITE_SIZE bytes. */ + xRc = ( xRc / ipconfigFTP_PREFERRED_WRITE_SIZE ) * ipconfigFTP_PREFERRED_WRITE_SIZE; + } + else + { + const StreamBuffer_t *pxBuffer = FreeRTOS_get_rx_buf( pxClient->xTransferSocket ); + size_t uxSpace = pxBuffer->LENGTH - pxBuffer->uxTail; + + if( uxSpace >= ipconfigFTP_PREFERRED_WRITE_SIZE ) + { + /* At this moment there are les than PREFERRED_WRITE_SIZE bytes in the RX + buffer, but there is space for more. Just return and + wait for more. */ + xRc = 0; + } + else + { + /* Now reading beyond the end of the circular buffer, + use a normal read. */ + pcBuffer = pcFILE_BUFFER; + xRc = FreeRTOS_recvcount( pxClient->xTransferSocket ); + xRc = ( xRc / ipconfigFTP_PREFERRED_WRITE_SIZE ) * ipconfigFTP_PREFERRED_WRITE_SIZE; + if( xRc > 0 ) + { + xRc = FreeRTOS_recv( pxClient->xTransferSocket, ( void * ) pcBuffer, + sizeof( pcFILE_BUFFER ), FREERTOS_MSG_DONTWAIT ); + } + } + } + } + if( xRc == 0 ) + { + break; + } + pxClient->ulRecvBytes += xRc; + + xWritten = ff_fwrite( pcBuffer, 1, xRc, pxClient->pxWriteHandle ); + if( pcBuffer != pcFILE_BUFFER ) + { + FreeRTOS_recv( pxClient->xTransferSocket, ( void * ) NULL, xRc, 0 ); + } + if( xWritten != xRc ) + { + xRc = -1; + /* bHadError: a transfer got aborted because of an error. */ + pxClient->bits1.bHadError = pdTRUE_UNSIGNED; + break; + } + } + return xRc; + } + +#endif /* ipconfigFTP_ZERO_COPY_ALIGNED_WRITES */ +/*-----------------------------------------------------------*/ + +/* +###### # ####### # ### + # # # # # ## # # + # # # # # # + # # #### ###### ### ## ### #### # # #### # # ### # #### + ###### # # # # # # # # # # # # # ##### # # # # + # ## ###### # ## # # ###### # # ###### # # # # ###### + # # # # # # # # # # # # # # + # # # ## # ## # # # ## # # # ## # # # # ## +### ## #### ## #### ##### #### ## #### #### ##### ##### #### +*/ +static BaseType_t prvRetrieveFilePrep( FTPClient_t *pxClient, char *pcFileName ) +{ +BaseType_t xResult = pdTRUE; +size_t uxFileSize; + + /* Close previous handle (if any) and reset file transfer parameters */ + prvTransferCloseFile( pxClient ); + + xMakeAbsolute( pxClient, pxClient->pcFileName, sizeof( pxClient->pcFileName ), pcFileName ); + + pxClient->pxReadHandle = ff_fopen( pxClient->pcFileName, "rb" ); + if( pxClient->pxReadHandle == NULL ) + { + int iErrno = stdioGET_ERRNO(); + /* "Requested file action not taken". */ + prvSendReply( pxClient->xSocket, REPL_450, 0 ); + FreeRTOS_printf( ("prvRetrieveFilePrep: open '%s': errno %d: %s\n", + pxClient->pcFileName, iErrno, ( const char * ) strerror( iErrno ) ) ); + uxFileSize = 0ul; + xResult = pdFALSE; + } + else + { + uxFileSize = pxClient->pxReadHandle->ulFileSize; + pxClient->uxBytesLeft = uxFileSize; + if( pxClient->ulRestartOffset != 0ul ) + { + size_t uxOffset = pxClient->ulRestartOffset; + int32_t iRc; + + /* Only use 1 time. */ + pxClient->ulRestartOffset = 0; + + if( uxOffset < uxFileSize ) + { + iRc = ff_fseek( pxClient->pxReadHandle, uxOffset, FF_SEEK_SET ); + } + else + { + iRc = -pdFREERTOS_ERRNO_EINVAL; + } + if( iRc != 0 ) + { + BaseType_t xLength; + + xLength = snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), + "450 Seek invalid %u length %u\r\n", ( unsigned ) uxOffset, ( unsigned ) uxFileSize ); + + /* "Requested file action not taken". */ + prvSendReply( pxClient->xSocket, pcCOMMAND_BUFFER, xLength ); + + FreeRTOS_printf( ( "prvRetrieveFilePrep: create %s: Seek %u length %u\n", + pxClient->pcFileName, ( unsigned ) uxOffset, ( unsigned ) uxFileSize ) ); + + ff_fclose( pxClient->pxReadHandle ); + pxClient->pxReadHandle = NULL; + xResult = pdFALSE; + } + else + { + pxClient->uxBytesLeft = uxFileSize - pxClient->ulRestartOffset; + } + } + } + if( xResult != pdFALSE ) + { + if( pxClient->bits1.bIsListen != pdFALSE_UNSIGNED ) + { + /* True if PASV is used. */ + snprintf( pxClient->pcConnectionAck, sizeof( pxClient->pcConnectionAck ), + "150%cAccepted data connection from %%xip:%%u\r\n%s", + pxClient->xTransType == TMODE_ASCII ? '-' : ' ', + pxClient->xTransType == TMODE_ASCII ? "150 NOTE: ASCII mode requested, but binary mode used\r\n" : "" ); + } else { + BaseType_t xLength; + + xLength = snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), "150%cOpening data connection to %lxip:%u\r\n%s", + pxClient->xTransType == TMODE_ASCII ? '-' : ' ', + pxClient->ulClientIP, + pxClient->usClientPort, + pxClient->xTransType == TMODE_ASCII ? "150 NOTE: ASCII mode requested, but binary mode used\r\n" : "" ); + prvSendReply( pxClient->xSocket, pcCOMMAND_BUFFER, xLength ); + pxClient->pcConnectionAck[ 0 ] = '\0'; + prvTransferStart( pxClient ); + } + + /* Prepare the ACK which will be sent when all data has been sent. */ + snprintf( pxClient->pcClientAck, sizeof( pxClient->pcClientAck ), "%s", REPL_226 ); + + /* To get some statistics about the performance. */ + pxClient->xStartTime = xTaskGetTickCount( ); + if( uxFileSize == 0ul ) + { + FreeRTOS_shutdown( pxClient->xTransferSocket, FREERTOS_SHUT_RDWR ); + } + } + + return xResult; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvRetrieveFileWork( FTPClient_t *pxClient ) +{ +size_t uxSpace; +size_t uxCount, uxItemsRead; +BaseType_t xRc = 0; +BaseType_t xSetEvent = pdFALSE; + + do + { + #if( ipconfigFTP_TX_ZERO_COPY != 0 ) + char *pcBuffer; + BaseType_t xBufferLength; + #endif /* ipconfigFTP_TX_ZERO_COPY */ + + /* Take the lesser of the two: tx_space (number of bytes that can be + queued for transmission) and uxBytesLeft (the number of bytes left to + read from the file) */ + uxSpace = FreeRTOS_tx_space( pxClient->xTransferSocket ); + + if( uxSpace == 0 ) + { + FreeRTOS_FD_SET( pxClient->xTransferSocket, pxClient->pxParent->xSocketSet, eSELECT_WRITE | eSELECT_EXCEPT ); + xRc = FreeRTOS_select( pxClient->pxParent->xSocketSet, 200 ); + uxSpace = FreeRTOS_tx_space( pxClient->xTransferSocket ); + } + + uxCount = FreeRTOS_min_uint32( pxClient->uxBytesLeft, uxSpace ); + + if( uxCount == 0 ) + { + break; + } + + #if( ipconfigFTP_TX_ZERO_COPY == 0 ) + { + if( uxCount > sizeof( pcFILE_BUFFER ) ) + { + uxCount = sizeof( pcFILE_BUFFER ); + } + uxItemsRead = ff_fread( pcFILE_BUFFER, 1, uxCount, pxClient->pxReadHandle ); + if( uxItemsRead != uxCount ) + { + FreeRTOS_printf( ( "prvRetrieveFileWork: Got %u Expected %u\n", ( unsigned )uxItemsRead, ( unsigned ) uxCount ) ); + xRc = FreeRTOS_shutdown( pxClient->xTransferSocket, FREERTOS_SHUT_RDWR ); + pxClient->uxBytesLeft = 0u; + break; + } + pxClient->uxBytesLeft -= uxCount; + + if( pxClient->uxBytesLeft == 0u ) + { + BaseType_t xTrueValue = 1; + + FreeRTOS_setsockopt( pxClient->xTransferSocket, 0, FREERTOS_SO_CLOSE_AFTER_SEND, ( void * ) &xTrueValue, sizeof( xTrueValue ) ); + } + + xRc = FreeRTOS_send( pxClient->xTransferSocket, pcFILE_BUFFER, uxCount, 0 ); + } + #else /* ipconfigFTP_TX_ZERO_COPY != 0 */ + { + /* Use zero-copy transmission: + FreeRTOS_get_tx_head() returns a direct pointer to the TX stream and + set xBufferLength to know how much space there is left. */ + pcBuffer = ( char * )FreeRTOS_get_tx_head( pxClient->xTransferSocket, &xBufferLength ); + if( ( pcBuffer != NULL ) && ( xBufferLength >= 512 ) ) + { + /* Will read disk data directly to the TX stream of the socket. */ + uxCount = FreeRTOS_min_uint32( uxCount, ( uint32_t )xBufferLength ); + if( uxCount > ( size_t ) 0x40000u ) + { + uxCount = ( size_t ) 0x40000u; + } + } + else + { + /* Use the normal file i/o buffer. */ + pcBuffer = pcFILE_BUFFER; + if( uxCount > sizeof( pcFILE_BUFFER ) ) + { + uxCount = sizeof( pcFILE_BUFFER ); + } + } + + if ( pxClient->uxBytesLeft >= 1024u ) + { + uxCount &= ~( ( size_t ) 512u - 1u ); + } + + if( uxCount <= 0u ) + { + /* Nothing to send after rounding down to a multiple of a sector size. */ + break; + } + + uxItemsRead = ff_fread( pcBuffer, 1, uxCount, pxClient->pxReadHandle ); + + if( uxCount != uxItemsRead ) + { + FreeRTOS_printf( ( "prvRetrieveFileWork: Got %u Expected %u\n", ( unsigned )uxItemsRead, ( unsigned )uxCount ) ); + xRc = FreeRTOS_shutdown( pxClient->xTransferSocket, FREERTOS_SHUT_RDWR ); + pxClient->uxBytesLeft = 0u; + break; + } + pxClient->uxBytesLeft -= uxCount; + + if( pxClient->uxBytesLeft == 0u ) + { + BaseType_t xTrueValue = 1; + + FreeRTOS_setsockopt( pxClient->xTransferSocket, 0, FREERTOS_SO_CLOSE_AFTER_SEND, ( void * ) &xTrueValue, sizeof( xTrueValue ) ); + } + if( pcBuffer != pcFILE_BUFFER ) + { + pcBuffer = NULL; + } + xRc = FreeRTOS_send( pxClient->xTransferSocket, pcBuffer, uxCount, 0 ); + } + #endif /* ipconfigFTP_TX_ZERO_COPY */ + + if( xRc < 0 ) + { + break; + } + + pxClient->ulRecvBytes += xRc; + if( pxClient->uxBytesLeft == 0u ) + { + break; + } + } while( uxCount > 0u ); + + if( xRc < 0 ) + { + FreeRTOS_printf( ( "prvRetrieveFileWork: already disconnected\n" ) ); + } + else if( pxClient->uxBytesLeft <= 0u ) + { + BaseType_t x; + + for( x = 0; x < 5; x++ ) + { + xRc = FreeRTOS_recv( pxClient->xTransferSocket, pcFILE_BUFFER, sizeof( pcFILE_BUFFER ), 0 ); + if( xRc < 0 ) + { + break; + } + } +// FreeRTOS_printf( ( "prvRetrieveFileWork: %s all sent: xRc %ld\n", pxClient->pcFileName, xRc ) ); + } + else + { + FreeRTOS_FD_SET( pxClient->xTransferSocket, pxClient->pxParent->xSocketSet, eSELECT_WRITE ); + xSetEvent = pdTRUE; + } + if( xSetEvent == pdFALSE ) + { + FreeRTOS_FD_CLR( pxClient->xTransferSocket, pxClient->pxParent->xSocketSet, eSELECT_WRITE ); + } + return xRc; +} +/*-----------------------------------------------------------*/ + +/* +### ##### #### ##### + # # # # # # # + # # # # # + # # # # + # # ## # + # # # ## # + # # # # # # + # # # # # # +####### ##### #### #### +*/ +/* Prepare sending a directory LIST */ +static BaseType_t prvListSendPrep( FTPClient_t *pxClient ) +{ +BaseType_t xFindResult; +int iErrorNo; + + if( pxClient->bits1.bIsListen != pdFALSE_UNSIGNED ) + { + /* True if PASV is used */ + snprintf( pxClient->pcConnectionAck, sizeof( pxClient->pcConnectionAck ), + "150 Accepted data connection from %%xip:%%u\r\n" ); + } + else + { + BaseType_t xLength; + + /* Here the FTP server is supposed to connect() */ + xLength = snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), + "150 Opening ASCII mode data connection to for /bin/ls \r\n" ); + + prvSendReply( pxClient->xSocket, pcCOMMAND_BUFFER, xLength ); + /* Clear the current connection acknowledge message */ + pxClient->pcConnectionAck[ 0 ] = '\0'; + prvTransferStart( pxClient ); + } + + pxClient->xDirCount = 0; + xMakeAbsolute( pxClient, pcNEW_DIR, sizeof( pcNEW_DIR ), pxClient->pcCurrentDir ); + + xFindResult = ff_findfirst( pcNEW_DIR, &pxClient->xFindData ); + + pxClient->bits1.bDirHasEntry = ( xFindResult >= 0 ); + + iErrorNo = stdioGET_ERRNO(); + if( ( xFindResult < 0 ) && ( iErrorNo == pdFREERTOS_ERRNO_ENMFILE ) ) + { + FreeRTOS_printf( ("prvListSendPrep: Empty directory? (%s)\n", pxClient->pcCurrentDir ) ); + prvSendReply( pxClient->xTransferSocket, "total 0\r\n", 0 ); + pxClient->xDirCount++; + } + else if( xFindResult < 0 ) + { + FreeRTOS_printf( ( "prvListSendPrep: rc = %ld iErrorNo = %d\n", xFindResult, iErrorNo ) ); + prvSendReply( pxClient->xSocket, REPL_451, 0 ); + } + pxClient->pcClientAck[ 0 ] = '\0'; + + return pxClient->xDirCount; +} +/*-----------------------------------------------------------*/ + +#define MAX_DIR_LIST_ENTRY_SIZE 256 + +static BaseType_t prvListSendWork( FTPClient_t *pxClient ) +{ +BaseType_t xTxSpace; + + while( pxClient->bits1.bClientConnected != pdFALSE_UNSIGNED ) + { + char *pcWritePtr = pcCOMMAND_BUFFER; + BaseType_t xWriteLength; + + xTxSpace = FreeRTOS_tx_space( pxClient->xTransferSocket ); + + if( xTxSpace > ( BaseType_t ) sizeof( pcCOMMAND_BUFFER ) ) + { + xTxSpace = sizeof( pcCOMMAND_BUFFER ); + } + + while( ( xTxSpace >= MAX_DIR_LIST_ENTRY_SIZE ) && ( pxClient->bits1.bDirHasEntry != pdFALSE_UNSIGNED ) ) + { + BaseType_t xLength, xEndOfDir; + int32_t iRc; + int iErrorNo; + + xLength = prvGetFileInfoStat( &( pxClient->xFindData.xDirectoryEntry ), pcWritePtr, xTxSpace ); + + pxClient->xDirCount++; + pcWritePtr += xLength; + xTxSpace -= xLength; + + iRc = ff_findnext( &pxClient->xFindData ); + iErrorNo = stdioGET_ERRNO(); + + xEndOfDir = ( iRc < 0 ) && ( iErrorNo == pdFREERTOS_ERRNO_ENMFILE ); + + pxClient->bits1.bDirHasEntry = ( xEndOfDir == pdFALSE ) && ( iRc >= 0 ); + + if( ( iRc < 0 ) && ( xEndOfDir == pdFALSE ) ) + { + FreeRTOS_printf( ("prvListSendWork: %s (rc %08x)\n", + ( const char * ) strerror( iErrorNo ), + ( unsigned )iRc ) ); + } + } + xWriteLength = ( BaseType_t ) ( pcWritePtr - pcCOMMAND_BUFFER ); + + if( xWriteLength == 0 ) + { + break; + } + + if( pxClient->bits1.bDirHasEntry == pdFALSE_UNSIGNED ) + { + uint32_t ulTotalCount; + uint32_t ulFreeCount; + uint32_t ulPercentage; + + ulTotalCount = 1; + ulFreeCount = ff_diskfree( pxClient->pcCurrentDir, &ulTotalCount ); + ulPercentage = ( uint32_t ) ( ( 100ULL * ulFreeCount + ulTotalCount / 2 ) / ulTotalCount ); + + /* Prepare the ACK which will be sent when all data has been sent. */ + snprintf( pxClient->pcClientAck, sizeof( pxClient->pcClientAck ), + "226-Options: -l\r\n" + "226-%ld matches total\r\n" + "226 Total %lu KB (%lu %% free)\r\n", + pxClient->xDirCount, ulTotalCount /1024, ulPercentage ); + } + + if( xWriteLength ) + { + if( pxClient->bits1.bDirHasEntry == pdFALSE_UNSIGNED ) + { + BaseType_t xTrueValue = 1; + + FreeRTOS_setsockopt( pxClient->xTransferSocket, 0, FREERTOS_SO_CLOSE_AFTER_SEND, ( void * ) &xTrueValue, sizeof( xTrueValue ) ); + } + + prvSendReply( pxClient->xTransferSocket, pcCOMMAND_BUFFER, xWriteLength ); + } + + if( pxClient->bits1.bDirHasEntry == pdFALSE_UNSIGNED ) + { + prvSendReply( pxClient->xSocket, pxClient->pcClientAck, 0 ); + break; + } + + } /* while( pxClient->bits1.bClientConnected ) */ + + return 0; +} +/*-----------------------------------------------------------*/ + +static const char *pcMonthAbbrev( BaseType_t xMonth ) +{ +static const char pcMonthList[] = "JanFebMarAprMayJunJulAugSepOctNovDec"; + + if( xMonth < 1 || xMonth > 12 ) + xMonth = 12; + + return pcMonthList + 3 * ( xMonth - 1 ); +}; +/*-----------------------------------------------------------*/ + +static BaseType_t prvGetFileInfoStat( FF_DirEnt_t *pxEntry, char *pcLine, BaseType_t xMaxLength ) +{ + char date[ 16 ]; + char mode[ 11 ] = "----------"; + BaseType_t st_nlink = 1; + const char user[ 9 ] = "freertos"; + const char group[ 8 ] = "plusfat"; + +/* + * Creates a unix-style listing, understood by most FTP clients: + * + * -rw-rw-r-- 1 freertos FreeRTOS+FAT 10564588 Sep 01 00:17 03. Metaharmoniks - Star (Instrumental).mp3 + * -rw-rw-r-- 1 freertos FreeRTOS+FAT 19087839 Sep 01 00:17 04. Simon Le Grec - Dimitri (Wherever U Are) (Cosmos Mix).mp3 + * -rw-rw-r-- 1 freertos FreeRTOS+FAT 11100621 Sep 01 00:16 05. D-Chill - Mistake (feat. Katy Blue).mp3 + */ + + #if ( ffconfigTIME_SUPPORT == 1 ) + const FF_SystemTime_t *pxCreateTime = &( pxEntry->xCreateTime ); + #else + #warning Do not use this. + FF_SystemTime_t xCreateTime; + const FF_SystemTime_t *pxCreateTime = &xCreateTime; + #endif + size_t ulSize = ( size_t )pxEntry->ulFileSize; + const char *pcFileName = pxEntry->pcFileName; + + mode[ 0 ] = ( ( pxEntry->ucAttrib & FF_FAT_ATTR_DIR ) != 0 ) ? 'd' : '-'; + #if( ffconfigDEV_SUPPORT != 0 ) + { + if( ( pxEntry->ucAttrib & FF_FAT_ATTR_DIR ) == 0 ) + { + switch( pxEntry->ucIsDeviceDir ) + { + case FF_DEV_CHAR_DEV: + mode[ 0 ] = 'c'; + break; + case FF_DEV_BLOCK_DEV: + mode[ 0 ] = 'b'; + break; + } + } + } + #endif /* ffconfigDEV_SUPPORT != 0 */ + + mode[ 1 ] = 'r'; /* Owner. */ + mode[ 2 ] = ( ( pxEntry->ucAttrib & FF_FAT_ATTR_READONLY ) != 0 ) ? '-' : 'w'; + mode[ 3 ] = '-'; /* x for executable. */ + + mode[ 4 ] = 'r'; /* group. */ + mode[ 5 ] = ( ( pxEntry->ucAttrib & FF_FAT_ATTR_READONLY ) != 0 ) ? '-' : 'w'; + mode[ 6 ] = '-'; /* x for executable. */ + + mode[ 7 ] = 'r'; /* world. */ + mode[ 8 ] = '-'; + mode[ 9 ] = '-'; /* x for executable. */ + + if( pxCreateTime->Month && pxCreateTime->Day ) + { + snprintf( date, sizeof( date ), "%-3.3s %02d %02d:%02d", + pcMonthAbbrev( pxCreateTime->Month ), + pxCreateTime->Day, + pxCreateTime->Hour, + pxCreateTime->Minute ); + } + else + { + snprintf (date, sizeof( date ), "Jan 01 1970"); + } + return snprintf( pcLine, xMaxLength, "%s %3ld %-4s %-4s %8d %12s %s\r\n", + mode, st_nlink, user, group, ( int ) ulSize, date, pcFileName ); +} +/*-----------------------------------------------------------*/ + +/* + #### # # ##### + # # # # # # +# # # # # # +# # # # # # +# # # # # # +# # # # # # +# # ## ## # # + # # ## ## # # + #### ## ## ##### +*/ +static BaseType_t prvChangeDir( FTPClient_t *pxClient, char *pcDirectory ) +{ +BaseType_t xResult; +BaseType_t xIsRootDir, xLength, xValid; +BaseType_t xIsDotDir = 0; + + if( pcDirectory[ 0 ] == '.' ) + { + if( ( pcDirectory[ 1 ] == '.' ) && + ( pcDirectory[ 2 ] == '\0' ) ) + { + xIsDotDir = 2; + } + else if( pcDirectory[ 1 ] == '\0' ) + { + xIsDotDir = 1; + } + } + + if( xIsDotDir != 0 ) + { + strcpy( pcFILE_BUFFER, pxClient->pcCurrentDir ); + + if( pcDirectory[ 1 ] == '.' ) + { + char *p = strrchr( pcFILE_BUFFER, '/' ); + if( p != NULL ) + { + if( p == pcFILE_BUFFER ) + { + p[ 1 ] = '\0'; + } + else + { + p[ 0 ] = '\0'; + } + } + } + } + else + { + if(pcDirectory[ 0 ] != '/' ) + { + BaseType_t xCurLength; + + xCurLength = strlen( pxClient->pcCurrentDir ); + snprintf( pcFILE_BUFFER, sizeof( pcFILE_BUFFER ), "%s%s%s", + pxClient->pcCurrentDir, + pxClient->pcCurrentDir[ xCurLength - 1 ] == '/' ? "" : "/", + pcDirectory ); + } + else + { + snprintf( pcFILE_BUFFER, sizeof( pcFILE_BUFFER ), "%s", pcDirectory ); + } + } + + xIsRootDir = ( pcFILE_BUFFER[ 0 ] == '/' ) && ( pcFILE_BUFFER[ 1 ] == '\0' ); + xMakeAbsolute( pxClient, pcNEW_DIR, sizeof( pcNEW_DIR ), pcFILE_BUFFER ); + + if( ( ( xIsRootDir == pdFALSE ) || ( FF_FS_Count() == 0 ) ) && ( ff_finddir( pcNEW_DIR ) == pdFALSE ) ) + { + xValid = pdFALSE; + } + else + { + xValid = pdTRUE; + } + + if( xValid == pdFALSE ) + { + /* Get the directory cluster, if it exists. */ + FreeRTOS_printf( ("FTP: chdir \"%s\": No such dir\n", pcNEW_DIR ) ); + //#define REPL_550 "550 Requested action not taken.\r\n" + //550 /home/hein/arch/h8300: No such file or directory + xLength = snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), + "550 %s: No such file or directory\r\n", + pcNEW_DIR ); + prvSendReply( pxClient->xSocket, pcCOMMAND_BUFFER, xLength ); + xResult = pdFALSE; + } + else + { + memcpy( pxClient->pcCurrentDir, pcNEW_DIR, sizeof( pxClient->pcCurrentDir ) ); + + xLength = snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), "250 Changed to %s\r\n", pcNEW_DIR ); + prvSendReply( pxClient->xSocket, pcCOMMAND_BUFFER, xLength ); + xResult = pdTRUE; + } + + return xResult; +} +/*-----------------------------------------------------------*/ + +/* +###### ## # ####### ###### + # # ## # # ## # # + # # ## # # # # # + # # ### # # # # # + ###### # ## # ##### ###### + # ## # ## # # # # ## + # # # ### # # # + # # # ## # # # +### ## # ## #### ### ## +*/ +static BaseType_t prvRenameFrom( FTPClient_t *pxClient, const char *pcFileName ) +{ +const char *myReply; +FF_FILE *fh; + + xMakeAbsolute( pxClient, pxClient->pcFileName, sizeof( pxClient->pcFileName ), pcFileName ); + + myReply = NULL; + + fh = ff_fopen( pxClient->pcFileName, "rb" ); + + if( fh != NULL ) + { + ff_fclose( fh ); + /* REPL_350; "350 Requested file action pending further information." */ + snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), + "350 Rename '%s' ...\r\n", pxClient->pcFileName ); + myReply = pcCOMMAND_BUFFER; + pxClient->bits.bInRename = pdTRUE_UNSIGNED; + } + else if( stdioGET_ERRNO() == pdFREERTOS_ERRNO_EISDIR ) + { + snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), + "350 Rename directory '%s' ...\r\n", pxClient->pcFileName ); + myReply = pcCOMMAND_BUFFER; + pxClient->bits.bInRename = pdTRUE_UNSIGNED; + } + else + { + FreeRTOS_printf( ("ftp::renameFrom[%s]\n%s\n", pxClient->pcFileName, strerror( stdioGET_ERRNO() ) ) ); + myReply = REPL_451; /* "451 Requested action aborted. Local error in processing." */ + } + if( myReply ) + { + prvSendReply( pxClient->xSocket, myReply, 0 ); + } + + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +/* +###### ## # ##### ### + # # ## # # # # ## ## + # # ## # # ## ## + # # ### # # # # + ###### # ## # # # # + # ## # ## # # # # + # # # ### # ## ## + # # # ## # ## ## +### ## # ## #### ### +*/ +static BaseType_t prvRenameTo( FTPClient_t *pxClient, const char *pcFileName ) +{ +const char *myReply = NULL; +int iResult; + + xMakeAbsolute( pxClient, pcNEW_DIR, sizeof( pcNEW_DIR ), pcFileName ); + + /* FreeRTOS+FAT rename has an extra parameter: "remove target if already + exists". */ + iResult = ff_rename( pxClient->pcFileName, pcNEW_DIR, pdFALSE ); + + if( iResult < 0 ) + { + iResult = stdioGET_ERRNO(); + } + else + { + iResult = 0; + } + + switch( iResult ) + { + case 0: + FreeRTOS_printf( ( "ftp::renameTo[%s,%s]: Ok\n", pxClient->pcFileName, pcNEW_DIR ) ); + snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), + "250 Rename successful to '%s'\r\n", pcNEW_DIR ); + myReply = pcCOMMAND_BUFFER; + break; + case pdFREERTOS_ERRNO_EEXIST: + /* the destination file already exists. + "450 Requested file action not taken.\r\n"*/ + snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), + "450 Already exists '%s'\r\n", pcNEW_DIR ); + myReply = pcCOMMAND_BUFFER; + break; + case pdFREERTOS_ERRNO_EIO: /* FF_ERR_FILE_COULD_NOT_CREATE_DIRENT */ + /* if dirent creation failed (fatal error!). + "553 Requested action not taken.\r\n" */ + FreeRTOS_printf( ("ftp::renameTo[%s,%s]: Error creating DirEnt\n", + pxClient->pcFileName, pcNEW_DIR ) ); + myReply = REPL_553; + break; + case pdFREERTOS_ERRNO_ENXIO: + case pdFREERTOS_ERRNO_ENOENT: + /* if the source file was not found. + "450 Requested file action not taken.\r\n" */ + snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), + "450 No such file '%s'\r\n", pxClient->pcFileName ); + myReply = pcCOMMAND_BUFFER; + break; + default: + FreeRTOS_printf( ("ftp::renameTo[%s,%s]: %s\n", pxClient->pcFileName, pcNEW_DIR, + (const char*)strerror( stdioGET_ERRNO() ) ) ); + myReply = REPL_451; /* "451 Requested action aborted. Local error in processing." */ + break; + } + prvSendReply( pxClient->xSocket, myReply, 0 ); + + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +/* + #### # +# # # # +# # # +# ### ###### #### + ## # # # # + ## # # ###### +# # # # # +# # # # ## # ## + #### ##### ## #### +*/ +static BaseType_t prvSiteCmd( FTPClient_t *pxClient, char *pcRestCommand ) +{ + ( void ) pxClient; + ( void ) pcRestCommand; + + return 0; +} +/*-----------------------------------------------------------*/ + +/* +##### ### + # # # # + # # # # + # # #### # #### ###### #### + # # # # # # # # # # + # # ###### # ###### # ###### + # # # # # # # + # # # ## # # ## # ## # ## +##### #### ##### #### ## #### +*/ +static BaseType_t prvDeleteFile( FTPClient_t *pxClient, char *pcFileName ) +{ +BaseType_t xResult, xLength; +int32_t iRc; +int iErrorNo; + + /* DELE: Delete a file. */ + xMakeAbsolute( pxClient, pxClient->pcFileName, sizeof( pxClient->pcFileName ), pcFileName ); + + iRc = ff_remove( pxClient->pcFileName ); + + if (iRc >= 0 ) + { + xLength = snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), + "250 File \"%s\" removed\r\n", pxClient->pcFileName ); + xResult = pdTRUE; + } + else + { + const char *errMsg = "other error"; + + iErrorNo = stdioGET_ERRNO(); + switch( iErrorNo ) + { /*_RB_ What do these negative numbers relate to? */ + case pdFREERTOS_ERRNO_ENOENT: errMsg = "No such file"; break; /* -31 File was not found. */ + case pdFREERTOS_ERRNO_EALREADY: errMsg = "File still open"; break; /* -30 File is in use. */ + case pdFREERTOS_ERRNO_EISDIR: errMsg = "Is a dir"; break; /* -32 Tried to FF_Open() a Directory. */ + case pdFREERTOS_ERRNO_EROFS: errMsg = "Read-only"; break; /* -33 Tried to FF_Open() a file marked read only. */ + case pdFREERTOS_ERRNO_ENOTDIR: errMsg = "Invalid path"; break; /* -34 The path of the file was not found. */ + } + FreeRTOS_printf( ( "ftp::delFile: '%s' because %s\n", + pxClient->pcFileName, strerror( iErrorNo ) ) ); + + xLength = snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), + "521-\"%s\" %s;\r\n" + "521 taking no action\r\n", + pxClient->pcFileName, errMsg ); + + xResult = pdFALSE; + } + + prvSendReply( pxClient->xSocket, pcCOMMAND_BUFFER, xLength ); + + return xResult; +} +/*-----------------------------------------------------------*/ + +/* + #### # ##### +# # # # # # +# # # # # +# ### ###### #### # # #### ###### #### + ## # # # # # # # # # # # + ## # # ###### # # ##### # ###### +# # # # # # # # # # # +# # # # # ## # # # # # ## # ## + #### ##### ###### #### ##### ### ## ## #### +*/ +static BaseType_t prvSizeDateFile( FTPClient_t *pxClient, char *pcFileName, BaseType_t xSendDate ) +{ +BaseType_t xResult = pdFALSE; +char *pcPtr; + + /* SIZE: get the size of a file (xSendDate = 0) + MDTM: get data and time properties (xSendDate = 1) */ + xMakeAbsolute( pxClient, pxClient->pcFileName, sizeof( pxClient->pcFileName ), pcFileName ); + + pcPtr = strrchr( pxClient->pcFileName, '/' ); + + if( ( pcPtr != NULL ) && ( pcPtr[ 1 ] != '\0' ) ) + { + FF_Stat_t xStatBuf; + int32_t iRc = ff_stat( pxClient->pcFileName, &xStatBuf ); + if (iRc < 0 ) + FreeRTOS_printf( ("In %s: %s\n", pxClient->pcFileName, + ( const char* )strerror( stdioGET_ERRNO() ) ) ); + + if( iRc == 0 ) + { + BaseType_t xLength; + /* "YYYYMMDDhhmmss" */ + if( xSendDate != pdFALSE ) + { + #if( ffconfigTIME_SUPPORT != 0 ) + { + FF_TimeStruct_t tmStruct; + time_t secs = xStatBuf.st_mtime; + FreeRTOS_gmtime_r( &secs, &tmStruct ); + + xLength = snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), "213 %04u%02u%02u%02u%02u%02u\r\n", + tmStruct.tm_year + 1900, + tmStruct.tm_mon+1, + tmStruct.tm_mday, + tmStruct.tm_hour, + tmStruct.tm_min, + tmStruct.tm_sec ); + } + #else + { + xLength = snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), "213 19700101000000\r\n", + } + #endif + } + else + { + xLength = snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), "213 %lu\r\n", xStatBuf.st_size ); + } + prvSendReply( pxClient->xSocket, pcCOMMAND_BUFFER, xLength ); + xResult = pdTRUE; + } + else + { + FreeRTOS_printf( ("ftp::sizeDateFile: No such file %s\n", pxClient->pcFileName ) ); + } + } else { + FreeRTOS_printf( ("ftp::sizeDateFile: Invalid file name: %s ?\n", pxClient->pcFileName ) ); + } + if( xResult == pdFALSE ) + { + prvSendReply( pxClient->xSocket, REPL_450, 0 ); /* "Requested file action not taken". */ + } + + return xResult; +} +/*-----------------------------------------------------------*/ + +/* +## ## ## ## ##### ###### ## ## ##### +### ### # # # # # # ### ### # # +# ### # # # # # # # # ### # # # +# # # # # # # # # # # # # # +# # # #### # # ###### # # # # # +# # # # # # # ## # # # # +# # # # # # # # # # # # +# # # # # # # # # # # # +# # ### ## ##### ### ## # # ##### +*/ +static BaseType_t prvMakeRemoveDir( FTPClient_t *pxClient, const char *pcDirectory, BaseType_t xDoRemove ) +{ +BaseType_t xResult; +BaseType_t xLength; +int32_t iRc; +int iErrorNo; + + /* MKD: Make / create a directory (xDoRemove = 0) + RMD: Remove a directory (xDoRemove = 1) */ + xMakeAbsolute( pxClient, pxClient->pcFileName, sizeof( pxClient->pcFileName ), pcDirectory ); + + if( xDoRemove ) + { + iRc = ff_rmdir( pxClient->pcFileName ); + } + else + { + #if( ffconfigMKDIR_RECURSIVE != 0 ) + { + iRc = ff_mkdir( pxClient->pcFileName, pdFALSE ); + } + #else + { + iRc = ff_mkdir( pxClient->pcFileName ); + } + #endif /* ffconfigMKDIR_RECURSIVE */ + } + xResult = pdTRUE; + + if( iRc >= 0 ) + { + xLength = snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), "257 \"%s\" directory %s\r\n", + pxClient->pcFileName, xDoRemove ? "removed" : "created" ); + } + else + { + const char *errMsg = "other error"; + BaseType_t xFTPCode = 521; + + xResult = pdFALSE; + iErrorNo = stdioGET_ERRNO(); + switch( iErrorNo ) + { + case pdFREERTOS_ERRNO_EEXIST: errMsg = "Directory already exists"; break; + case pdFREERTOS_ERRNO_ENOTDIR: errMsg = "Invalid path"; break; /* -34 The path of the file was not found. *//*_RB_ As before, what do these negative numbers relate to? */ + case pdFREERTOS_ERRNO_ENOTEMPTY:errMsg = "Dir not empty"; break; + case pdFREERTOS_ERRNO_EROFS: errMsg = "Read-only"; break; /* -33 Tried to FF_Open() a file marked read only. */ + default: errMsg = strerror( iErrorNo ); break; + } + if( iErrorNo == pdFREERTOS_ERRNO_ENOSPC ) + { + xFTPCode = 552; + } + xLength = snprintf( pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), + "%ld-\"%s\" %s;\r\n" + "%ld taking no action\r\n", + xFTPCode, pxClient->pcFileName, errMsg, xFTPCode ); + FreeRTOS_printf( ( "%sdir '%s': %s\n", xDoRemove ? "rm" : "mk", pxClient->pcFileName, errMsg ) ); + } + prvSendReply( pxClient->xSocket, pcCOMMAND_BUFFER, xLength ); + + return xResult; +} +/*-----------------------------------------------------------*/ + +static portINLINE BaseType_t IsDigit( char cChar ) +{ +BaseType_t xResult; + + if( cChar >= '0' && cChar <= '9' ) + { + xResult = pdTRUE; + } + else + { + xResult = pdFALSE; + } + return xResult; +} + +static BaseType_t prvSendReply( Socket_t xSocket, const char *pcBuffer, BaseType_t xLength ) +{ +BaseType_t xResult; + + if( xLength == 0 ) + { + xLength = strlen( pcBuffer ); + } + xResult = FreeRTOS_send( xSocket, ( const void * )pcBuffer, ( size_t ) xLength, 0 ); + if( IsDigit( ( int ) pcBuffer[ 0 ] ) && + IsDigit( ( int ) pcBuffer[ 1 ] ) && + IsDigit( ( int ) pcBuffer[ 2 ] ) && + IsDigit( ( int ) pcBuffer[ 3 ] ) ) + { + const char *last = pcBuffer + strlen( pcBuffer ); + int iLength; + while( ( last > pcBuffer ) && ( ( last[ -1 ] == ftpASCII_CR ) || ( last[ -1 ] == ftpASCII_LF ) ) ) + { + last--; + } + iLength = ( int )( last - pcBuffer ); + FF_PRINTF( " %-*.*s", iLength, iLength, pcBuffer ); + } + return xResult; +} +/*-----------------------------------------------------------*/ + +#if( ipconfigFTP_HAS_RECEIVED_HOOK != 0 ) + + /* + * The following function is called for every file received: + * void vApplicationFTPReceivedHook( pcFileName, ulSize, pxFTPClient ); + * This callback function may do a callback to vFTPReplyMessage() to send messages + * to the FTP client like: + * 200-Please wait: Received new firmware + * 200-Please wait: Please wait a few seconds for reboot + */ + void vFTPReplyMessage( struct xFTP_CLIENT *pxFTPClient, const char *pcMessage ) + { + if( ( pxFTPClient != NULL ) && ( pxFTPClient->xSocket != NULL ) ) + { + prvSendReply( pxFTPClient->xSocket, pcMessage, 0 ); + } + } + /*-----------------------------------------------------------*/ + +#endif /* ipconfigFTP_HAS_RECEIVED_HOOK != 0 */ + +/* + * Some explanation: + * The FTP client may send: "DELE readme.txt" + * Here the complete path is constructed consisting of 3 parts: + * + * pxClient->pcRootDir + pxClient->pcCurrentDir + pcFileName + * + * 'pcCurrentDir' will not be applied for an absolute path like in "DELE /.htaccess" + */ +BaseType_t xMakeAbsolute( FTPClient_t *pxClient, char *pcBuffer, BaseType_t xBufferLength, const char *pcFileName ) +{ +BaseType_t xLength = strlen( pxClient->pcRootDir ); + + if( pcFileName[ 0 ] != '/' ) + { + char *pcNewDirBuffer = pcNEW_DIR; + BaseType_t xCurLength; + + xCurLength = strlen( pxClient->pcCurrentDir ); + if( pcBuffer == pcNEW_DIR ) + { + /* In one call, the result already goes into pcNEW_DIR. + Use pcFILE_BUFFER in that case */ + pcNewDirBuffer = pcFILE_BUFFER; + } + snprintf( pcNewDirBuffer, sizeof( pcNEW_DIR ), "%s%s%s", + pxClient->pcCurrentDir, + pxClient->pcCurrentDir[ xCurLength - 1 ] == '/' ? "" : "/", + pcFileName ); + pcFileName = pcNewDirBuffer; + } + if( strncasecmp( pxClient->pcRootDir, pcFileName, xLength ) == 0 ) + { + xLength = snprintf( pcBuffer, xBufferLength, "%s", pcFileName ); + } + else + { + xLength = snprintf( pcBuffer, xBufferLength, "%s/%s", + pxClient->pcRootDir, + pcFileName[ 0 ] == '/' ? ( pcFileName + 1 ) : pcFileName ); + } + + #if( ipconfigFTP_FS_USES_BACKSLAH == 1 ) + for( pcPtr = pcBuffer; *pcPtr; pcPtr++ ) + { + if( pcPtr[ 0 ] == '/' ) + { + pcPtr[ 0 ] = '\\'; + } + } + #endif + + return xLength; +} +/*-----------------------------------------------------------*/ + +BaseType_t xMakeRelative( FTPClient_t *pxClient, char *pcBuffer, BaseType_t xBufferLength, const char *pcFileName ) +{ +BaseType_t xLength = strlen( pxClient->pcRootDir ); + + if( strncasecmp ( pxClient->pcRootDir, pcFileName, xLength ) == 0 ) + { + xLength = snprintf( pcBuffer, xBufferLength, "%s", pcFileName + xLength ); + } + else + { + xLength = snprintf( pcBuffer, xBufferLength, "%s", pcFileName ); + } + + return xLength; +} +/*-----------------------------------------------------------*/ + +#endif /* ipconfigUSE_FTP */ + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/HTTP/FreeRTOS_HTTP_commands.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/HTTP/FreeRTOS_HTTP_commands.c new file mode 100644 index 0000000..f8b5ac2 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/HTTP/FreeRTOS_HTTP_commands.c @@ -0,0 +1,71 @@ +/* + * FreeRTOS+TCP V2.0.3 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + + +/* Standard includes. */ +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" + +#include "FreeRTOS_HTTP_commands.h" + +const struct xWEB_COMMAND xWebCommands[ WEB_CMD_COUNT ] = +{ + { 3, "GET", ECMD_GET }, + { 4, "HEAD", ECMD_HEAD }, + { 4, "POST", ECMD_POST }, + { 3, "PUT", ECMD_PUT }, + { 6, "DELETE", ECMD_DELETE }, + { 5, "TRACE", ECMD_TRACE }, + { 7, "OPTIONS", ECMD_OPTIONS }, + { 7, "CONNECT", ECMD_CONNECT }, + { 5, "PATCH", ECMD_PATCH }, + { 4, "UNKN", ECMD_UNK }, +}; + +const char *webCodename (int aCode) +{ + switch (aCode) { + case WEB_REPLY_OK: // = 200, + return "OK"; + case WEB_NO_CONTENT: // 204 + return "No content"; + case WEB_BAD_REQUEST: // = 400, + return "Bad request"; + case WEB_UNAUTHORIZED: // = 401, + return "Authorization Required"; + case WEB_NOT_FOUND: // = 404, + return "Not Found"; + case WEB_GONE: // = 410, + return "Done"; + case WEB_PRECONDITION_FAILED: // = 412, + return "Precondition Failed"; + case WEB_INTERNAL_SERVER_ERROR: // = 500, + return "Internal Server Error"; + } + return "Unknown"; +} diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/HTTP/FreeRTOS_HTTP_server.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/HTTP/FreeRTOS_HTTP_server.c new file mode 100644 index 0000000..ee69fd1 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/HTTP/FreeRTOS_HTTP_server.c @@ -0,0 +1,428 @@ +/* + * FreeRTOS+TCP V2.0.3 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +/* Standard includes. */ +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" + +/* FreeRTOS Protocol includes. */ +#include "FreeRTOS_HTTP_commands.h" +#include "FreeRTOS_TCP_server.h" +#include "FreeRTOS_server_private.h" + +/* Remove the whole file if HTTP is not supported. */ +#if( ipconfigUSE_HTTP == 1 ) + +/* FreeRTOS+FAT includes. */ +#include "ff_stdio.h" + +#ifndef HTTP_SERVER_BACKLOG + #define HTTP_SERVER_BACKLOG ( 12 ) +#endif + +#ifndef USE_HTML_CHUNKS + #define USE_HTML_CHUNKS ( 0 ) +#endif + +#if !defined( ARRAY_SIZE ) + #define ARRAY_SIZE(x) ( BaseType_t ) (sizeof( x ) / sizeof( x )[ 0 ] ) +#endif + +/* Some defines to make the code more readbale */ +#define pcCOMMAND_BUFFER pxClient->pxParent->pcCommandBuffer +#define pcNEW_DIR pxClient->pxParent->pcNewDir +#define pcFILE_BUFFER pxClient->pxParent->pcFileBuffer + +#ifndef ipconfigHTTP_REQUEST_CHARACTER + #define ipconfigHTTP_REQUEST_CHARACTER '?' +#endif + +/*_RB_ Need comment block, although fairly self evident. */ +static void prvFileClose( HTTPClient_t *pxClient ); +static BaseType_t prvProcessCmd( HTTPClient_t *pxClient, BaseType_t xIndex ); +static const char *pcGetContentsType( const char *apFname ); +static BaseType_t prvOpenURL( HTTPClient_t *pxClient ); +static BaseType_t prvSendFile( HTTPClient_t *pxClient ); +static BaseType_t prvSendReply( HTTPClient_t *pxClient, BaseType_t xCode ); + +static const char pcEmptyString[1] = { '\0' }; + +typedef struct xTYPE_COUPLE +{ + const char *pcExtension; + const char *pcType; +} TypeCouple_t; + +static TypeCouple_t pxTypeCouples[ ] = +{ + { "html", "text/html" }, + { "css", "text/css" }, + { "js", "text/javascript" }, + { "png", "image/png" }, + { "jpg", "image/jpeg" }, + { "gif", "image/gif" }, + { "txt", "text/plain" }, + { "mp3", "audio/mpeg3" }, + { "wav", "audio/wav" }, + { "flac", "audio/ogg" }, + { "pdf", "application/pdf" }, + { "ttf", "application/x-font-ttf" }, + { "ttc", "application/x-font-ttf" } +}; + +void vHTTPClientDelete( TCPClient_t *pxTCPClient ) +{ +HTTPClient_t *pxClient = ( HTTPClient_t * ) pxTCPClient; + + /* This HTTP client stops, close / release all resources. */ + if( pxClient->xSocket != FREERTOS_NO_SOCKET ) + { + FreeRTOS_FD_CLR( pxClient->xSocket, pxClient->pxParent->xSocketSet, eSELECT_ALL ); + FreeRTOS_closesocket( pxClient->xSocket ); + pxClient->xSocket = FREERTOS_NO_SOCKET; + } + prvFileClose( pxClient ); +} +/*-----------------------------------------------------------*/ + +static void prvFileClose( HTTPClient_t *pxClient ) +{ + if( pxClient->pxFileHandle != NULL ) + { + FreeRTOS_printf( ( "Closing file: %s\n", pxClient->pcCurrentFilename ) ); + ff_fclose( pxClient->pxFileHandle ); + pxClient->pxFileHandle = NULL; + } +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvSendReply( HTTPClient_t *pxClient, BaseType_t xCode ) +{ +struct xTCP_SERVER *pxParent = pxClient->pxParent; +BaseType_t xRc; + + /* A normal command reply on the main socket (port 21). */ + char *pcBuffer = pxParent->pcFileBuffer; + + xRc = snprintf( pcBuffer, sizeof( pxParent->pcFileBuffer ), + "HTTP/1.1 %d %s\r\n" +#if USE_HTML_CHUNKS + "Transfer-Encoding: chunked\r\n" +#endif + "Content-Type: %s\r\n" + "Connection: keep-alive\r\n" + "%s\r\n", + ( int ) xCode, + webCodename (xCode), + pxParent->pcContentsType[0] ? pxParent->pcContentsType : "text/html", + pxParent->pcExtraContents ); + + pxParent->pcContentsType[0] = '\0'; + pxParent->pcExtraContents[0] = '\0'; + + xRc = FreeRTOS_send( pxClient->xSocket, ( const void * ) pcBuffer, xRc, 0 ); + pxClient->bits.bReplySent = pdTRUE_UNSIGNED; + + return xRc; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvSendFile( HTTPClient_t *pxClient ) +{ +size_t uxSpace; +size_t uxCount; +BaseType_t xRc = 0; + + if( pxClient->bits.bReplySent == pdFALSE_UNSIGNED ) + { + pxClient->bits.bReplySent = pdTRUE_UNSIGNED; + + strcpy( pxClient->pxParent->pcContentsType, pcGetContentsType( pxClient->pcCurrentFilename ) ); + snprintf( pxClient->pxParent->pcExtraContents, sizeof( pxClient->pxParent->pcExtraContents ), + "Content-Length: %d\r\n", ( int ) pxClient->uxBytesLeft ); + + /* "Requested file action OK". */ + xRc = prvSendReply( pxClient, WEB_REPLY_OK ); + } + + if( xRc >= 0 ) do + { + uxSpace = FreeRTOS_tx_space( pxClient->xSocket ); + + if( pxClient->uxBytesLeft < uxSpace ) + { + uxCount = pxClient->uxBytesLeft; + } + else + { + uxCount = uxSpace; + } + + if( uxCount > 0u ) + { + if( uxCount > sizeof( pxClient->pxParent->pcFileBuffer ) ) + { + uxCount = sizeof( pxClient->pxParent->pcFileBuffer ); + } + ff_fread( pxClient->pxParent->pcFileBuffer, 1, uxCount, pxClient->pxFileHandle ); + pxClient->uxBytesLeft -= uxCount; + + xRc = FreeRTOS_send( pxClient->xSocket, pxClient->pxParent->pcFileBuffer, uxCount, 0 ); + if( xRc < 0 ) + { + break; + } + } + } while( uxCount > 0u ); + + if( pxClient->uxBytesLeft == 0u ) + { + /* Writing is ready, no need for further 'eSELECT_WRITE' events. */ + FreeRTOS_FD_CLR( pxClient->xSocket, pxClient->pxParent->xSocketSet, eSELECT_WRITE ); + prvFileClose( pxClient ); + } + else + { + /* Wake up the TCP task as soon as this socket may be written to. */ + FreeRTOS_FD_SET( pxClient->xSocket, pxClient->pxParent->xSocketSet, eSELECT_WRITE ); + } + + return xRc; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvOpenURL( HTTPClient_t *pxClient ) +{ +BaseType_t xRc; +char pcSlash[ 2 ]; + + pxClient->bits.ulFlags = 0; + + #if( ipconfigHTTP_HAS_HANDLE_REQUEST_HOOK != 0 ) + { + if( strchr( pxClient->pcUrlData, ipconfigHTTP_REQUEST_CHARACTER ) != NULL ) + { + size_t xResult; + + xResult = uxApplicationHTTPHandleRequestHook( pxClient->pcUrlData, pxClient->pcCurrentFilename, sizeof( pxClient->pcCurrentFilename ) ); + if( xResult > 0 ) + { + strcpy( pxClient->pxParent->pcContentsType, "text/html" ); + snprintf( pxClient->pxParent->pcExtraContents, sizeof( pxClient->pxParent->pcExtraContents ), + "Content-Length: %d\r\n", ( int ) xResult ); + xRc = prvSendReply( pxClient, WEB_REPLY_OK ); /* "Requested file action OK" */ + if( xRc > 0 ) + { + xRc = FreeRTOS_send( pxClient->xSocket, pxClient->pcCurrentFilename, xResult, 0 ); + } + /* Although against the coding standard of FreeRTOS, a return is + done here to simplify this conditional code. */ + return xRc; + } + } + } + #endif /* ipconfigHTTP_HAS_HANDLE_REQUEST_HOOK */ + + if( pxClient->pcUrlData[ 0 ] != '/' ) + { + /* Insert a slash before the file name. */ + pcSlash[ 0 ] = '/'; + pcSlash[ 1 ] = '\0'; + } + else + { + /* The browser provided a starting '/' already. */ + pcSlash[ 0 ] = '\0'; + } + snprintf( pxClient->pcCurrentFilename, sizeof( pxClient->pcCurrentFilename ), "%s%s%s", + pxClient->pcRootDir, + pcSlash, + pxClient->pcUrlData); + + pxClient->pxFileHandle = ff_fopen( pxClient->pcCurrentFilename, "rb" ); + + FreeRTOS_printf( ( "Open file '%s': %s\n", pxClient->pcCurrentFilename, + pxClient->pxFileHandle != NULL ? "Ok" : strerror( stdioGET_ERRNO() ) ) ); + + if( pxClient->pxFileHandle == NULL ) + { + /* "404 File not found". */ + xRc = prvSendReply( pxClient, WEB_NOT_FOUND ); + } + else + { + pxClient->uxBytesLeft = ( size_t ) pxClient->pxFileHandle->ulFileSize; + xRc = prvSendFile( pxClient ); + } + + return xRc; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvProcessCmd( HTTPClient_t *pxClient, BaseType_t xIndex ) +{ +BaseType_t xResult = 0; + + /* A new command has been received. Process it. */ + switch( xIndex ) + { + case ECMD_GET: + xResult = prvOpenURL( pxClient ); + break; + + case ECMD_HEAD: + case ECMD_POST: + case ECMD_PUT: + case ECMD_DELETE: + case ECMD_TRACE: + case ECMD_OPTIONS: + case ECMD_CONNECT: + case ECMD_PATCH: + case ECMD_UNK: + { + FreeRTOS_printf( ( "prvProcessCmd: Not implemented: %s\n", + xWebCommands[xIndex].pcCommandName ) ); + } + break; + } + + return xResult; +} +/*-----------------------------------------------------------*/ + +BaseType_t xHTTPClientWork( TCPClient_t *pxTCPClient ) +{ +BaseType_t xRc; +HTTPClient_t *pxClient = ( HTTPClient_t * ) pxTCPClient; + + if( pxClient->pxFileHandle != NULL ) + { + prvSendFile( pxClient ); + } + + xRc = FreeRTOS_recv( pxClient->xSocket, ( void * )pcCOMMAND_BUFFER, sizeof( pcCOMMAND_BUFFER ), 0 ); + + if( xRc > 0 ) + { + BaseType_t xIndex; + const char *pcEndOfCmd; + const struct xWEB_COMMAND *curCmd; + char *pcBuffer = pcCOMMAND_BUFFER; + + if( xRc < ( BaseType_t ) sizeof( pcCOMMAND_BUFFER ) ) + { + pcBuffer[ xRc ] = '\0'; + } + while( xRc && ( pcBuffer[ xRc - 1 ] == 13 || pcBuffer[ xRc - 1 ] == 10 ) ) + { + pcBuffer[ --xRc ] = '\0'; + } + pcEndOfCmd = pcBuffer + xRc; + + curCmd = xWebCommands; + + /* Pointing to "/index.html HTTP/1.1". */ + pxClient->pcUrlData = pcBuffer; + + /* Pointing to "HTTP/1.1". */ + pxClient->pcRestData = pcEmptyString; + + /* Last entry is "ECMD_UNK". */ + for( xIndex = 0; xIndex < WEB_CMD_COUNT - 1; xIndex++, curCmd++ ) + { + BaseType_t xLength; + + xLength = curCmd->xCommandLength; + if( ( xRc >= xLength ) && ( memcmp( curCmd->pcCommandName, pcBuffer, xLength ) == 0 ) ) + { + char *pcLastPtr; + + pxClient->pcUrlData += xLength + 1; + for( pcLastPtr = (char *)pxClient->pcUrlData; pcLastPtr < pcEndOfCmd; pcLastPtr++ ) + { + char ch = *pcLastPtr; + if( ( ch == '\0' ) || ( strchr( "\n\r \t", ch ) != NULL ) ) + { + *pcLastPtr = '\0'; + pxClient->pcRestData = pcLastPtr + 1; + break; + } + } + break; + } + } + + if( xIndex < ( WEB_CMD_COUNT - 1 ) ) + { + xRc = prvProcessCmd( pxClient, xIndex ); + } + } + else if( xRc < 0 ) + { + /* The connection will be closed and the client will be deleted. */ + FreeRTOS_printf( ( "xHTTPClientWork: rc = %ld\n", xRc ) ); + } + return xRc; +} +/*-----------------------------------------------------------*/ + +static const char *pcGetContentsType (const char *apFname) +{ + const char *slash = NULL; + const char *dot = NULL; + const char *ptr; + const char *pcResult = "text/html"; + BaseType_t x; + + for( ptr = apFname; *ptr; ptr++ ) + { + if (*ptr == '.') dot = ptr; + if (*ptr == '/') slash = ptr; + } + if( dot > slash ) + { + dot++; + for( x = 0; x < ARRAY_SIZE( pxTypeCouples ); x++ ) + { + if( strcasecmp( dot, pxTypeCouples[ x ].pcExtension ) == 0 ) + { + pcResult = pxTypeCouples[ x ].pcType; + break; + } + } + } + return pcResult; +} + +#endif /* ipconfigUSE_HTTP */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/NTP/NTPDemo.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/NTP/NTPDemo.c new file mode 100644 index 0000000..7795c41 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/NTP/NTPDemo.c @@ -0,0 +1,440 @@ +/* + * FreeRTOS+TCP V2.0.3 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +/* + * NTPDemo.c + * + * An example of how to lookup a domain using DNS + * And also how to send and receive UDP messages to get the NTP time + * + */ + +/* Standard includes. */ +#include +#include +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_DNS.h" +#include "FreeRTOS_Stream_Buffer.h" + +/* Use the date & time functions from +FAT. */ +#include "ff_time.h" + +#include "NTPDemo.h" +#include "ntpClient.h" + +#include "date_and_time.h" + +enum EStatus { + EStatusLookup, + EStatusAsking, + EStatusPause, + EStatusFailed, +}; + +static struct SNtpPacket xNTPPacket; + +#if( ipconfigUSE_CALLBACKS == 0 ) + static char cRecvBuffer[ sizeof( struct SNtpPacket ) + 64 ]; +#endif + +static enum EStatus xStatus = EStatusLookup; + +static const char *pcTimeServers[] = { + "0.asia.pool.ntp.org", + "0.europe.pool.ntp.org", + "0.id.pool.ntp.org", + "0.south-america.pool.ntp.org", + "0.oceania.pool.ntp.org", + "0.north-america.pool.ntp.org" +}; + +static SemaphoreHandle_t xNTPWakeupSem = NULL; +static uint32_t ulIPAddressFound; +static Socket_t xUDPSocket = NULL; +static TaskHandle_t xNTPTaskhandle = NULL; +static TickType_t uxSendTime; + +static void prvNTPTask( void *pvParameters ); + +static void vSignalTask( void ) +{ + #if( ipconfigUSE_CALLBACKS == 0 ) + if( xUDPSocket != NULL ) + { + /* Send a signal to the socket so that the + FreeRTOS_recvfrom will get interrupted. */ + FreeRTOS_SignalSocket( xUDPSocket ); + } + else + #endif + if( xNTPWakeupSem != NULL ) + { + xSemaphoreGive( xNTPWakeupSem ); + } +} + +void vStartNTPTask( uint16_t usTaskStackSize, UBaseType_t uxTaskPriority ) +{ + /* The only public function in this module: start a task to contact + some NTP server. */ + + if( xNTPTaskhandle != NULL ) + { + switch( xStatus ) + { + case EStatusPause: + xStatus = EStatusAsking; + vSignalTask(); + break; + case EStatusLookup: + FreeRTOS_printf( ( "NTP looking up server\n" ) ); + break; + case EStatusAsking: + FreeRTOS_printf( ( "NTP still asking\n" ) ); + break; + case EStatusFailed: + FreeRTOS_printf( ( "NTP failed somehow\n" ) ); + ulIPAddressFound = 0ul; + xStatus = EStatusLookup; + vSignalTask(); + break; + } + } + else + { + xUDPSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP ); + if( xUDPSocket != NULL ) + { + struct freertos_sockaddr xAddress; + #if( ipconfigUSE_CALLBACKS != 0 ) + BaseType_t xReceiveTimeOut = pdMS_TO_TICKS( 0 ); + #else + BaseType_t xReceiveTimeOut = pdMS_TO_TICKS( 5000 ); + #endif + + xAddress.sin_addr = 0ul; + xAddress.sin_port = FreeRTOS_htons( NTP_PORT ); + + FreeRTOS_bind( xUDPSocket, &xAddress, sizeof( xAddress ) ); + FreeRTOS_setsockopt( xUDPSocket, 0, FREERTOS_SO_RCVTIMEO, &xReceiveTimeOut, sizeof( xReceiveTimeOut ) ); + xTaskCreate( prvNTPTask, /* The function that implements the task. */ + ( const char * ) "NTP client", /* Just a text name for the task to aid debugging. */ + usTaskStackSize, /* The stack size is defined in FreeRTOSIPConfig.h. */ + NULL, /* The task parameter, not used in this case. */ + uxTaskPriority, /* The priority assigned to the task is defined in FreeRTOSConfig.h. */ + &xNTPTaskhandle ); /* The task handle. */ + } + else + { + FreeRTOS_printf( ( "Creating socket failed\n" ) ); + } + } +} +/*-----------------------------------------------------------*/ + +static void vDNS_callback( const char *pcName, void *pvSearchID, uint32_t ulIPAddress ) +{ +char pcBuf[16]; + + /* The DNS lookup has a result, or it has reached the time-out. */ + FreeRTOS_inet_ntoa( ulIPAddress, pcBuf ); + FreeRTOS_printf( ( "IP address of %s found: %s\n", pcName, pcBuf ) ); + if( ulIPAddressFound == 0ul ) + { + ulIPAddressFound = ulIPAddress; + } + /* For testing: in case DNS doen't respond, still try some NTP server + with a known IP-address. */ + if( ulIPAddressFound == 0ul ) + { + ulIPAddressFound = FreeRTOS_inet_addr_quick( 184, 105, 182, 7 ); +/* ulIPAddressFound = FreeRTOS_inet_addr_quick( 103, 242, 70, 4 ); */ + } + xStatus = EStatusAsking; + + vSignalTask(); +} +/*-----------------------------------------------------------*/ + +static void prvSwapFields( struct SNtpPacket *pxPacket) +{ + /* NTP messages are big-endian */ + pxPacket->rootDelay = FreeRTOS_htonl( pxPacket->rootDelay ); + pxPacket->rootDispersion = FreeRTOS_htonl( pxPacket->rootDispersion ); + + pxPacket->referenceTimestamp.seconds = FreeRTOS_htonl( pxPacket->referenceTimestamp.seconds ); + pxPacket->referenceTimestamp.fraction = FreeRTOS_htonl( pxPacket->referenceTimestamp.fraction ); + + pxPacket->originateTimestamp.seconds = FreeRTOS_htonl( pxPacket->originateTimestamp.seconds ); + pxPacket->originateTimestamp.fraction = FreeRTOS_htonl( pxPacket->originateTimestamp.fraction ); + + pxPacket->receiveTimestamp.seconds = FreeRTOS_htonl( pxPacket->receiveTimestamp.seconds ); + pxPacket->receiveTimestamp.fraction = FreeRTOS_htonl( pxPacket->receiveTimestamp.fraction ); + + pxPacket->transmitTimestamp.seconds = FreeRTOS_htonl( pxPacket->transmitTimestamp.seconds ); + pxPacket->transmitTimestamp.fraction = FreeRTOS_htonl( pxPacket->transmitTimestamp.fraction ); +} +/*-----------------------------------------------------------*/ + +static void prvNTPPacketInit( ) +{ + memset (&xNTPPacket, '\0', sizeof( xNTPPacket ) ); + + xNTPPacket.flags = 0xDB; /* value 0xDB : mode 3 (client), version 3, leap indicator unknown 3 */ + xNTPPacket.poll = 10; /* 10 means 1 << 10 = 1024 seconds */ + xNTPPacket.precision = 0xFA; /* = 250 = 0.015625 seconds */ + xNTPPacket.rootDelay = 0x5D2E; /* 0x5D2E = 23854 or (23854/65535)= 0.3640 sec */ + xNTPPacket.rootDispersion = 0x0008CAC8; /* 0x0008CAC8 = 8.7912 seconds */ + + /* use the recorded NTP time */ + time_t uxSecs = FreeRTOS_time( NULL );/* apTime may be NULL, returns seconds */ + + xNTPPacket.referenceTimestamp.seconds = uxSecs; /* Current time */ + xNTPPacket.transmitTimestamp.seconds = uxSecs + 3; + + /* Transform the contents of the fields from native to big endian. */ + prvSwapFields( &xNTPPacket ); +} +/*-----------------------------------------------------------*/ + +static void prvReadTime( struct SNtpPacket * pxPacket ) +{ + FF_TimeStruct_t xTimeStruct; + time_t uxPreviousSeconds; + time_t uxPreviousMS; + + time_t uxCurrentSeconds; + time_t uxCurrentMS; + + const char *pcTimeUnit; + int32_t ilDiff; + TickType_t uxTravelTime; + + uxTravelTime = xTaskGetTickCount() - uxSendTime; + + /* Transform the contents of the fields from big to native endian. */ + prvSwapFields( pxPacket ); + + uxCurrentSeconds = pxPacket->receiveTimestamp.seconds - TIME1970; + uxCurrentMS = pxPacket->receiveTimestamp.fraction / 4294967; + uxCurrentSeconds += uxCurrentMS / 1000; + uxCurrentMS = uxCurrentMS % 1000; + + // Get the last time recorded + uxPreviousSeconds = FreeRTOS_get_secs_msec( &uxPreviousMS ); + + // Set the new time with precision in msec. */ + FreeRTOS_set_secs_msec( &uxCurrentSeconds, &uxCurrentMS ); + + if( uxCurrentSeconds >= uxPreviousSeconds ) + { + ilDiff = ( int32_t ) ( uxCurrentSeconds - uxPreviousSeconds ); + } + else + { + ilDiff = 0 - ( int32_t ) ( uxPreviousSeconds - uxCurrentSeconds ); + } + + if( ( ilDiff < -5 ) || ( ilDiff > 5 ) ) + { + /* More than 5 seconds difference. */ + pcTimeUnit = "sec"; + } + else + { + /* Less than or equal to 5 second difference. */ + pcTimeUnit = "ms"; + uint32_t ulLowest = ( uxCurrentSeconds <= uxPreviousSeconds ) ? uxCurrentSeconds : uxPreviousSeconds; + int32_t iCurMS = 1000 * ( uxCurrentSeconds - ulLowest ) + uxCurrentMS; + int32_t iPrevMS = 1000 * ( uxPreviousSeconds - ulLowest ) + uxPreviousMS; + ilDiff = iCurMS - iPrevMS; + } + uxCurrentSeconds -= iTimeZone; + + FreeRTOS_gmtime_r( &uxCurrentSeconds, &xTimeStruct ); + + /* + 378.067 [NTP client] NTP time: 9/11/2015 16:11:19.559 Diff -20 ms (289 ms) + 379.441 [NTP client] NTP time: 9/11/2015 16:11:20.933 Diff 0 ms (263 ms) + */ + + FreeRTOS_printf( ("NTP time: %d/%d/%02d %2d:%02d:%02d.%03u Diff %d %s (%lu ms)\n", + xTimeStruct.tm_mday, + xTimeStruct.tm_mon + 1, + xTimeStruct.tm_year + 1900, + xTimeStruct.tm_hour, + xTimeStruct.tm_min, + xTimeStruct.tm_sec, + ( unsigned )uxCurrentMS, + ( unsigned )ilDiff, + pcTimeUnit, + uxTravelTime ) ); + + /* Remove compiler warnings in case FreeRTOS_printf() is not used. */ + ( void ) pcTimeUnit; + ( void ) uxTravelTime; +} +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_CALLBACKS != 0 ) + + static BaseType_t xOnUDPReceive( Socket_t xSocket, void * pvData, size_t xLength, + const struct freertos_sockaddr *pxFrom, const struct freertos_sockaddr *pxDest ) + { + if( xLength >= sizeof( xNTPPacket ) ) + { + prvReadTime( ( struct SNtpPacket *)pvData ); + if( xStatus != EStatusPause ) + { + xStatus = EStatusPause; + } + } + vSignalTask(); + /* Tell the driver not to store the RX data */ + return 1; + } + /*-----------------------------------------------------------*/ + +#endif /* ipconfigUSE_CALLBACKS != 0 */ + +static void prvNTPTask( void *pvParameters ) +{ +BaseType_t xServerIndex = 3; +struct freertos_sockaddr xAddress; +#if( ipconfigUSE_CALLBACKS != 0 ) + F_TCP_UDP_Handler_t xHandler; +#endif /* ipconfigUSE_CALLBACKS != 0 */ + + xStatus = EStatusLookup; + #if( ipconfigSOCKET_HAS_USER_SEMAPHORE != 0 ) || ( ipconfigUSE_CALLBACKS != 0 ) + { + xNTPWakeupSem = xSemaphoreCreateBinary(); + } + #endif + + #if( ipconfigUSE_CALLBACKS != 0 ) + { + memset( &xHandler, '\0', sizeof( xHandler ) ); + xHandler.pxOnUDPReceive = xOnUDPReceive; + FreeRTOS_setsockopt( xUDPSocket, 0, FREERTOS_SO_UDP_RECV_HANDLER, ( void * ) &xHandler, sizeof( xHandler ) ); + } + #endif + #if( ipconfigSOCKET_HAS_USER_SEMAPHORE != 0 ) + { + FreeRTOS_setsockopt( xUDPSocket, 0, FREERTOS_SO_SET_SEMAPHORE, ( void * ) &xNTPWakeupSem, sizeof( xNTPWakeupSem ) ); + } + #endif + for( ; ; ) + { + switch( xStatus ) + { + case EStatusLookup: + if( ( ulIPAddressFound == 0ul ) || ( ulIPAddressFound == ~0ul ) ) + { + if( ++xServerIndex == sizeof( pcTimeServers ) / sizeof( pcTimeServers[ 0 ] ) ) + { + xServerIndex = 0; + } + FreeRTOS_printf( ( "Looking up server '%s'\n", pcTimeServers[ xServerIndex ] ) ); + FreeRTOS_gethostbyname_a( pcTimeServers[ xServerIndex ], vDNS_callback, (void *)NULL, 1200 ); + } + else + { + xStatus = EStatusAsking; + } + break; + + case EStatusAsking: + { + char pcBuf[16]; + + prvNTPPacketInit( ); + xAddress.sin_addr = ulIPAddressFound; + xAddress.sin_port = FreeRTOS_htons( NTP_PORT ); + + FreeRTOS_inet_ntoa( xAddress.sin_addr, pcBuf ); + FreeRTOS_printf( ( "Sending UDP message to %s:%u\n", + pcBuf, + FreeRTOS_ntohs( xAddress.sin_port ) ) ); + + uxSendTime = xTaskGetTickCount( ); + FreeRTOS_sendto( xUDPSocket, ( void * )&xNTPPacket, sizeof( xNTPPacket ), 0, &xAddress, sizeof( xAddress ) ); + } + break; + + case EStatusPause: + break; + + case EStatusFailed: + break; + } + + #if( ipconfigUSE_CALLBACKS != 0 ) + { + xSemaphoreTake( xNTPWakeupSem, 5000 ); + } + #else + { + uint32_t xAddressSize; + BaseType_t xReturned; + + xAddressSize = sizeof( xAddress ); + xReturned = FreeRTOS_recvfrom( xUDPSocket, ( void * ) cRecvBuffer, sizeof( cRecvBuffer ), 0, &xAddress, &xAddressSize ); + switch( xReturned ) + { + case 0: + case -pdFREERTOS_ERRNO_EAGAIN: + case -pdFREERTOS_ERRNO_EINTR: + break; + default: + if( xReturned < sizeof( xNTPPacket ) ) + { + FreeRTOS_printf( ( "FreeRTOS_recvfrom: returns %ld\n", xReturned ) ); + } + else + { + prvReadTime( ( struct SNtpPacket *)cRecvBuffer ); + if( xStatus != EStatusPause ) + { + xStatus = EStatusPause; + } + } + break; + } + } + #endif + } +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/include/FreeRTOS_FTP_commands.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/include/FreeRTOS_FTP_commands.h new file mode 100644 index 0000000..6ae2384 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/include/FreeRTOS_FTP_commands.h @@ -0,0 +1,133 @@ +/* + * FreeRTOS+TCP V2.0.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +#ifndef __FTPCMD_H__ + +#define __FTPCMD_H__ + +#define REPL_110 "110 Restart marker reply.\r\n" +#define REPL_120 "120 Try again in 2 minutes.\r\n" +#define REPL_125 "125 Data connection already open; transfer starting.\r\n" +#define REPL_150 "150 File status okay; about to open data connection.\r\n" +#define REPL_200 "200 NOOP command successful.\r\n" +#define REPL_200_PROGRESS "200 NOOP: data transfer in progress.\r\n" +#define REPL_202 "202 Command not implemented, superfluous at this site.\r\n" +#define REPL_211 "221 System status, or system help reply.\r\n" +#define REPL_211_STATUS "221-status of %s.\r\n" +#define REPL_211_END "221 End of status.\r\n" +#define REPL_212 "212 Directory status.\r\n" +#define REPL_213 "213 File status.\r\n" +#define REPL_214 "214 Help message.\r\n" +#define REPL_214_END "214 End Help message.\r\n" +#define REPL_215 "215 %s system type.\r\n" +#define REPL_220 "220 Service ready for new user.\r\n" +#define REPL_221 "221 Service closing control connection.\r\n" +#define REPL_225 "225 Data connection open; no transfer in progress.\r\n" +#define REPL_226 "226 Closing data connection.\r\n" +#define REPL_227 "227 Entering Passive Mode (%s,%s,%s,%s,%s,%s).\r\n" +#define REPL_227_D "227 Entering Passive Mode (%u,%u,%u,%u,%u,%u).\r\n" +#define REPL_230 "230 User logged in, proceed.\r\n" +#define REPL_250 "250 Requested file action okay, completed.\r\n" +#define REPL_257 "257 %s created.\r\n" +// #define REPL_257_PWD "257 \"%s\" is current working dir.\r\n" +#define REPL_257_PWD "257 \"%s\"\r\n" +#define REPL_331 "331 Only anonymous user is accepted.\r\n" +#define REPL_331_ANON "331 Anonymous login okay\r\n" +#define REPL_332 "332 Need account for login.\r\n" +#define REPL_350 "350 Requested file action pending further information.\r\n" +#define REPL_421 "421 Service not available, closing control connection.\r\n" +#define REPL_425 "425 Can't open data connection.\r\n" +#define REPL_426 "426 Connection closed; transfer aborted.\r\n" +#define REPL_450 "450 Requested file action not taken.\r\n" +#define REPL_451 "451 Requested action aborted. Local error in processing.\r\n" +#define REPL_452 "452 Requested action not taken.\r\n" +#define REPL_500 "500 Syntax error, command unrecognized.\r\n" +#define REPL_501 "501 Syntax error in parameters or arguments.\r\n" +#define REPL_502 "502 Command not implemented.\r\n" +#define REPL_503 "503 Bad sequence of commands.\r\n" +#define REPL_504 "504 Command not implemented for that parameter.\r\n" +#define REPL_530 "530 Not logged in.\r\n" +#define REPL_532 "532 Need account for storing files.\r\n" +#define REPL_550 "550 Requested action not taken.\r\n" +#define REPL_551 "551 Requested action aborted. Page type unknown.\r\n" +#define REPL_552 "552 Requested file action aborted.\r\n" +#define REPL_553 "553 Requested action not taken.\r\n" +#define REPL_553_READ_ONLY "553 Read-only file-system.\r\n" + +enum EFTPCommand { + ECMD_USER, + ECMD_PASS, + ECMD_ACCT, + ECMD_CWD, + ECMD_CDUP, + ECMD_SMNT, + ECMD_QUIT, + ECMD_REIN, + ECMD_PORT, + ECMD_PASV, + ECMD_TYPE, + ECMD_STRU, + ECMD_MODE, + ECMD_RETR, + ECMD_STOR, + ECMD_STOU, + ECMD_APPE, + ECMD_ALLO, + ECMD_REST, + ECMD_RNFR, + ECMD_RNTO, + ECMD_ABOR, + ECMD_SIZE, + ECMD_MDTM, + ECMD_DELE, + ECMD_RMD, + ECMD_MKD, + ECMD_PWD, + ECMD_LIST, + ECMD_NLST, + ECMD_SITE, + ECMD_SYST, + ECMD_FEAT, + ECMD_STAT, + ECMD_HELP, + ECMD_NOOP, + ECMD_EMPTY, + ECMD_CLOSE, + ECMD_UNKNOWN, +}; + +typedef struct xFTP_COMMAND { + BaseType_t xCommandLength; + const char pcCommandName[7]; + const unsigned char ucCommandType; + const unsigned char checkLogin; + const unsigned char checkNullArg; +} FTPCommand_t; + +#define FTP_CMD_COUNT (ECMD_UNKNOWN+1) + +extern const FTPCommand_t xFTPCommands[ FTP_CMD_COUNT ]; + +#endif // __FTPCMD_H__ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/include/FreeRTOS_HTTP_commands.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/include/FreeRTOS_HTTP_commands.h new file mode 100644 index 0000000..75eaf5d --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/include/FreeRTOS_HTTP_commands.h @@ -0,0 +1,67 @@ +/* + * FreeRTOS+TCP V2.0.3 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ +#ifndef FREERTOS_HTTP_COMMANDS_H +#define FREERTOS_HTTP_COMMANDS_H + +enum { + WEB_REPLY_OK = 200, + WEB_NO_CONTENT = 204, + WEB_BAD_REQUEST = 400, + WEB_UNAUTHORIZED = 401, + WEB_NOT_FOUND = 404, + WEB_GONE = 410, + WEB_PRECONDITION_FAILED = 412, + WEB_INTERNAL_SERVER_ERROR = 500, +}; + +enum EWebCommand { + ECMD_GET, + ECMD_HEAD, + ECMD_POST, + ECMD_PUT, + ECMD_DELETE, + ECMD_TRACE, + ECMD_OPTIONS, + ECMD_CONNECT, + ECMD_PATCH, + ECMD_UNK, +}; + +struct xWEB_COMMAND +{ + BaseType_t xCommandLength; + const char *pcCommandName; + const unsigned char ucCommandType; +}; + +#define WEB_CMD_COUNT (ECMD_UNK+1) + +extern const struct xWEB_COMMAND xWebCommands[WEB_CMD_COUNT]; + +extern const char *webCodename (int aCode); + +#endif /* FREERTOS_HTTP_COMMANDS_H */ + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/include/FreeRTOS_TCP_server.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/include/FreeRTOS_TCP_server.h new file mode 100644 index 0000000..d8140ce --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/include/FreeRTOS_TCP_server.h @@ -0,0 +1,125 @@ +/* + * FreeRTOS+TCP V2.0.3 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +/* + Some code which is common to TCP servers like HTTP en FTP +*/ + +#ifndef FREERTOS_TCP_SERVER_H +#define FREERTOS_TCP_SERVER_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef FTP_SERVER_USES_RELATIVE_DIRECTORY + #define FTP_SERVER_USES_RELATIVE_DIRECTORY 0 +#endif + +enum eSERVER_TYPE +{ + eSERVER_NONE, + eSERVER_HTTP, + eSERVER_FTP, +}; + +struct xFTP_CLIENT; + +#if( ipconfigFTP_HAS_RECEIVED_HOOK != 0 ) + extern void vApplicationFTPReceivedHook( const char *pcFileName, uint32_t ulSize, struct xFTP_CLIENT *pxFTPClient ); + extern void vFTPReplyMessage( struct xFTP_CLIENT *pxFTPClient, const char *pcMessage ); +#endif /* ipconfigFTP_HAS_RECEIVED_HOOK != 0 */ + +#if( ipconfigFTP_HAS_USER_PASSWORD_HOOK != 0 ) + /* + * Function is called when a user name has been submitted. + * The function may return a string such as: "331 Please enter your password" + * or return NULL to use the default reply. + */ + extern const char *pcApplicationFTPUserHook( const char *pcUserName ); +#endif /* ipconfigFTP_HAS_USER_PASSWORD_HOOK */ + +#if( ipconfigFTP_HAS_USER_PASSWORD_HOOK != 0 ) + /* + * Function is called when a password was received. + * Return positive value to allow the user + */ + extern BaseType_t xApplicationFTPPasswordHook( const char *pcUserName, const char *pcPassword ); +#endif /* ipconfigFTP_HAS_USER_PASSWORD_HOOK */ + +#if( ipconfigFTP_HAS_USER_PROPERTIES_HOOK != 0 ) + /* + * The FTP server is asking for user-specific properties + */ + typedef struct + { + uint16_t usPortNumber; /* For reference only. Host-endian. */ + const char *pcRootDir; + BaseType_t xReadOnly; + } + FTPUserProperties_t; + extern void vApplicationFTPUserPropertiesHook( const char *pcUserName, FTPUserProperties_t *pxProperties ); +#endif /* ipconfigFTP_HAS_USER_PASSWORD_HOOK */ + +#if( ipconfigHTTP_HAS_HANDLE_REQUEST_HOOK != 0 ) + /* + * A GET request is received containing a special character, + * usually a question mark. + * const char *pcURLData; // A request, e.g. "/request?limit=75" + * char *pcBuffer; // Here the answer can be written + * size_t uxBufferLength; // Size of the buffer + * + */ + extern size_t uxApplicationHTTPHandleRequestHook( const char *pcURLData, char *pcBuffer, size_t uxBufferLength ); +#endif /* ipconfigHTTP_HAS_HANDLE_REQUEST_HOOK */ + +struct xSERVER_CONFIG +{ + enum eSERVER_TYPE eType; /* eSERVER_HTTP | eSERVER_FTP */ + BaseType_t xPortNumber; /* e.g. 80, 8080, 21 */ + BaseType_t xBackLog; /* e.g. 10, maximum number of connected TCP clients */ + const char * const pcRootDir; /* Treat this directory as the root directory */ +}; + +struct xTCP_SERVER; +typedef struct xTCP_SERVER TCPServer_t; + +TCPServer_t *FreeRTOS_CreateTCPServer( const struct xSERVER_CONFIG *pxConfigs, BaseType_t xCount ); +void FreeRTOS_TCPServerWork( TCPServer_t *pxServer, TickType_t xBlockingTime ); + +#if( ipconfigSUPPORT_SIGNALS != 0 ) + /* FreeRTOS_TCPServerWork() calls select(). + The two functions below provide a possibility to interrupt + the call to select(). After the interruption, resume + by calling FreeRTOS_TCPServerWork() again. */ + BaseType_t FreeRTOS_TCPServerSignal( TCPServer_t *pxServer ); + BaseType_t FreeRTOS_TCPServerSignalFromISR( TCPServer_t *pxServer, BaseType_t *pxHigherPriorityTaskWoken ); +#endif + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* FREERTOS_TCP_SERVER_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/include/FreeRTOS_server_private.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/include/FreeRTOS_server_private.h new file mode 100644 index 0000000..7376804 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/include/FreeRTOS_server_private.h @@ -0,0 +1,185 @@ +/* + * FreeRTOS+TCP V2.0.3 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + + /* + Some code which is common to TCP servers like HTTP and FTP +*/ + +#ifndef FREERTOS_SERVER_PRIVATE_H +#define FREERTOS_SERVER_PRIVATE_H + +#define FREERTOS_NO_SOCKET NULL + +/* FreeRTOS+FAT */ +#include "ff_stdio.h" + +/* Each HTTP server has 1, at most 2 sockets */ +#define HTTP_SOCKET_COUNT 2 + +/* + * ipconfigTCP_COMMAND_BUFFER_SIZE sets the size of: + * pcCommandBuffer': a buffer to receive and send TCP commands + * + * ipconfigTCP_FILE_BUFFER_SIZE sets the size of: + * pcFileBuffer' : a buffer to access the file system: read or write data. + * + * The buffers are both used for FTP as well as HTTP. + */ + +#ifndef ipconfigTCP_COMMAND_BUFFER_SIZE + #define ipconfigTCP_COMMAND_BUFFER_SIZE ( 2048 ) +#endif + +#ifndef ipconfigTCP_FILE_BUFFER_SIZE + #define ipconfigTCP_FILE_BUFFER_SIZE ( 2048 ) +#endif + +struct xTCP_CLIENT; + +typedef BaseType_t ( * FTCPWorkFunction ) ( struct xTCP_CLIENT * /* pxClient */ ); +typedef void ( * FTCPDeleteFunction ) ( struct xTCP_CLIENT * /* pxClient */ ); + +#define TCP_CLIENT_FIELDS \ + enum eSERVER_TYPE eType; \ + struct xTCP_SERVER *pxParent; \ + Socket_t xSocket; \ + const char *pcRootDir; \ + FTCPWorkFunction fWorkFunction; \ + FTCPDeleteFunction fDeleteFunction; \ + struct xTCP_CLIENT *pxNextClient + +typedef struct xTCP_CLIENT +{ + /* This define contains fields which must come first within each of the client structs */ + TCP_CLIENT_FIELDS; + /* --- Keep at the top --- */ + +} TCPClient_t; + +struct xHTTP_CLIENT +{ + /* This define contains fields which must come first within each of the client structs */ + TCP_CLIENT_FIELDS; + /* --- Keep at the top --- */ + + const char *pcUrlData; + const char *pcRestData; + char pcCurrentFilename[ ffconfigMAX_FILENAME ]; + size_t uxBytesLeft; + FF_FILE *pxFileHandle; + union { + struct { + uint32_t + bReplySent : 1; + }; + uint32_t ulFlags; + } bits; +}; + +typedef struct xHTTP_CLIENT HTTPClient_t; + +struct xFTP_CLIENT +{ + /* This define contains fields which must come first within each of the client structs */ + TCP_CLIENT_FIELDS; + /* --- Keep at the top --- */ + + uint32_t ulRestartOffset; + uint32_t ulRecvBytes; + size_t uxBytesLeft; /* Bytes left to send */ + uint32_t ulClientIP; + TickType_t xStartTime; + uint16_t usClientPort; + Socket_t xTransferSocket; + BaseType_t xTransType; + BaseType_t xDirCount; + FF_FindData_t xFindData; + FF_FILE *pxReadHandle; + FF_FILE *pxWriteHandle; + char pcCurrentDir[ ffconfigMAX_FILENAME ]; + char pcFileName[ ffconfigMAX_FILENAME ]; + char pcConnectionAck[ 128 ]; + char pcClientAck[ 128 ]; + union { + struct { + uint32_t + bHelloSent : 1, + bLoggedIn : 1, + bStatusUser : 1, + bInRename : 1, + bReadOnly : 1; + }; + uint32_t ulFTPFlags; + } bits; + union { + struct { + uint32_t + bIsListen : 1, /* pdTRUE for passive data connections (using list()). */ + bDirHasEntry : 1, /* pdTRUE if ff_findfirst() was successful. */ + bClientConnected : 1, /* pdTRUE after connect() or accept() has succeeded. */ + bEmptyFile : 1, /* pdTRUE if a connection-without-data was received. */ + bHadError : 1; /* pdTRUE if a transfer got aborted because of an error. */ + }; + uint32_t ulConnFlags; + } bits1; +}; + +typedef struct xFTP_CLIENT FTPClient_t; + +BaseType_t xHTTPClientWork( TCPClient_t *pxClient ); +BaseType_t xFTPClientWork( TCPClient_t *pxClient ); + +void vHTTPClientDelete( TCPClient_t *pxClient ); +void vFTPClientDelete( TCPClient_t *pxClient ); + +BaseType_t xMakeAbsolute( struct xFTP_CLIENT *pxClient, char *pcBuffer, BaseType_t xBufferLength, const char *pcFileName ); +BaseType_t xMakeRelative( FTPClient_t *pxClient, char *pcBuffer, BaseType_t xBufferLength, const char *pcFileName ); + +struct xTCP_SERVER +{ + SocketSet_t xSocketSet; + /* A buffer to receive and send TCP commands, either HTTP of FTP. */ + char pcCommandBuffer[ ipconfigTCP_COMMAND_BUFFER_SIZE ]; + /* A buffer to access the file system: read or write data. */ + char pcFileBuffer[ ipconfigTCP_FILE_BUFFER_SIZE ]; + + #if( ipconfigUSE_FTP != 0 ) + char pcNewDir[ ffconfigMAX_FILENAME ]; + #endif + #if( ipconfigUSE_HTTP != 0 ) + char pcContentsType[40]; /* Space for the msg: "text/javascript" */ + char pcExtraContents[40]; /* Space for the msg: "Content-Length: 346500" */ + #endif + BaseType_t xServerCount; + TCPClient_t *pxClients; + struct xSERVER + { + enum eSERVER_TYPE eType; /* eSERVER_HTTP | eSERVER_FTP */ + const char *pcRootDir; + Socket_t xSocket; + } xServers[ 1 ]; +}; + +#endif /* FREERTOS_SERVER_PRIVATE_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/include/NTPClient.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/include/NTPClient.h new file mode 100644 index 0000000..813539e --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/include/NTPClient.h @@ -0,0 +1,71 @@ +// +// ntpClient.h +// + +#ifndef __NTPCLIENT_H__ + +#define __NTPCLIENT_H__ + +#define NTP_PORT 123 + +typedef uint32_t quint32; +typedef int32_t qint32; +typedef uint8_t quint8; +typedef int8_t qint8; + +typedef union _SNtpFlags SNtpFlags; + +/** + * 64-bit NTP timestamp. + */ +struct __attribute__ ((__packed__)) _SNtpTimestamp { + /** Number of seconds passed since Jan 1 1900, in big-endian format. */ + quint32 seconds; + + /** Fractional time part, in 1/0xFFFFFFFFs of a second. */ + quint32 fraction; +}; + +typedef struct _SNtpTimestamp SNtpTimestamp; +/** + * Mandatory part of an NTP packet + */ +struct SNtpPacket { + /** Flags. */ + unsigned char flags; // value 0xDB : mode 3 (client), version 3, leap indicator unknown 3 + + /** Stratum of the clock. */ + quint8 stratum; // value 0 : unspecified + + /** Maximum interval between successive messages, in log2 seconds. Note that the value is signed. */ + qint8 poll; // 10 means 1 << 10 = 1024 seconds + + /** Precision of the clock, in log2 seconds. Note that the value is signed. */ + qint8 precision; // 0xFA = 250 = 0.015625 seconds + + /** Round trip time to the primary reference source, in NTP short format. */ + qint32 rootDelay; // 0x5D2E = 23854 or (23854/65535)= 0.3640 sec + + /** Nominal error relative to the primary reference source. */ + qint32 rootDispersion; // 0x0008 CAC8 = 8.7912 seconds + + /** Reference identifier (either a 4 character string or an IP address). */ + qint8 referenceID[4]; // or just 0000 + + /** The time at which the clock was last set or corrected. */ + SNtpTimestamp referenceTimestamp; // Current time + + /** The time at which the request departed the client for the server. */ + SNtpTimestamp originateTimestamp; // Keep 0 + + /** The time at which the request arrived at the server. */ + SNtpTimestamp receiveTimestamp; // Keep 0 + + /** The time at which the reply departed the server for client. */ + SNtpTimestamp transmitTimestamp; +}; + +/* Add this number to get secs since 1-1-1900 */ +#define TIME1970 2208988800UL + +#endif // __NTPCLIENT_H__ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/include/NTPDemo.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/include/NTPDemo.h new file mode 100644 index 0000000..e75fb76 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/Demo_IP_Protocols/include/NTPDemo.h @@ -0,0 +1,11 @@ +/* + * A simple demo for NTP using FreeRTOS+TCP + */ + +#ifndef NTPDEMO_H + +#define NTPDEMO_H + +void vStartNTPTask( uint16_t usTaskStackSize, UBaseType_t uxTaskPriority ); + +#endif \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/File-Related-CLI-commands.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/File-Related-CLI-commands.c new file mode 100644 index 0000000..e973cef --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/File-Related-CLI-commands.c @@ -0,0 +1,530 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Standard includes. */ +#include +#include +#include +#include + +/* FreeRTOS+CLI includes. */ +#include "FreeRTOS_CLI.h" + +/* File system includes. */ +#include "fat_sl.h" +#include "api_mdriver_ram.h" + +#ifdef _WINDOWS_ + #define snprintf _snprintf +#endif + +#define cliNEW_LINE "\r\n" + +/******************************************************************************* + * See the URL in the comments within main.c for the location of the online + * documentation. + ******************************************************************************/ + +/* + * Print out information on a single file. + */ +static void prvCreateFileInfoString( char *pcBuffer, F_FIND *pxFindStruct ); + +/* + * Copies an existing file into a newly created file. + */ +static BaseType_t prvPerformCopy( const char *pcSourceFile, + int32_t lSourceFileLength, + const char *pcDestinationFile, + char *pxWriteBuffer, + size_t xWriteBufferLen ); + +/* + * Implements the DIR command. + */ +static BaseType_t prvDIRCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the CD command. + */ +static BaseType_t prvCDCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the DEL command. + */ +static BaseType_t prvDELCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the TYPE command. + */ +static BaseType_t prvTYPECommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the COPY command. + */ +static BaseType_t prvCOPYCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* Structure that defines the DIR command line command, which lists all the +files in the current directory. */ +static const CLI_Command_Definition_t xDIR = +{ + "dir", /* The command string to type. */ + "\r\ndir:\r\n Lists the files in the current directory\r\n", + prvDIRCommand, /* The function to run. */ + 0 /* No parameters are expected. */ +}; + +/* Structure that defines the CD command line command, which changes the +working directory. */ +static const CLI_Command_Definition_t xCD = +{ + "cd", /* The command string to type. */ + "\r\ncd :\r\n Changes the working directory\r\n", + prvCDCommand, /* The function to run. */ + 1 /* One parameter is expected. */ +}; + +/* Structure that defines the TYPE command line command, which prints the +contents of a file to the console. */ +static const CLI_Command_Definition_t xTYPE = +{ + "type", /* The command string to type. */ + "\r\ntype :\r\n Prints file contents to the terminal\r\n", + prvTYPECommand, /* The function to run. */ + 1 /* One parameter is expected. */ +}; + +/* Structure that defines the DEL command line command, which deletes a file. */ +static const CLI_Command_Definition_t xDEL = +{ + "del", /* The command string to type. */ + "\r\ndel :\r\n deletes a file or directory\r\n", + prvDELCommand, /* The function to run. */ + 1 /* One parameter is expected. */ +}; + +/* Structure that defines the COPY command line command, which deletes a file. */ +static const CLI_Command_Definition_t xCOPY = +{ + "copy", /* The command string to type. */ + "\r\ncopy :\r\n Copies to \r\n", + prvCOPYCommand, /* The function to run. */ + 2 /* Two parameters are expected. */ +}; + + +/*-----------------------------------------------------------*/ + +void vRegisterFileSystemCLICommands( void ) +{ + /* Register all the command line commands defined immediately above. */ + FreeRTOS_CLIRegisterCommand( &xDIR ); + FreeRTOS_CLIRegisterCommand( &xCD ); + FreeRTOS_CLIRegisterCommand( &xTYPE ); + FreeRTOS_CLIRegisterCommand( &xDEL ); + FreeRTOS_CLIRegisterCommand( &xCOPY ); +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTYPECommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *pcParameter; +BaseType_t xParameterStringLength, xReturn = pdTRUE; +static F_FILE *pxFile = NULL; +int iChar; +size_t xByte; +size_t xColumns = 50U; + + /* Ensure there is always a null terminator after each character written. */ + memset( pcWriteBuffer, 0x00, xWriteBufferLen ); + + /* Ensure the buffer leaves space for the \r\n. */ + configASSERT( xWriteBufferLen > ( strlen( cliNEW_LINE ) * 2 ) ); + xWriteBufferLen -= strlen( cliNEW_LINE ); + + if( xWriteBufferLen < xColumns ) + { + /* Ensure the loop that uses xColumns as an end condition does not + write off the end of the buffer. */ + xColumns = xWriteBufferLen; + } + + if( pxFile == NULL ) + { + /* The file has not been opened yet. Find the file name. */ + pcParameter = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 1, /* Return the first parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcParameter ); + + /* Attempt to open the requested file. */ + pxFile = f_open( pcParameter, "r" ); + } + + if( pxFile != NULL ) + { + /* Read the next chunk of data from the file. */ + for( xByte = 0; xByte < xColumns; xByte++ ) + { + iChar = f_getc( pxFile ); + + if( iChar == -1 ) + { + /* No more characters to return. */ + f_close( pxFile ); + pxFile = NULL; + break; + } + else + { + pcWriteBuffer[ xByte ] = ( char ) iChar; + } + } + } + + if( pxFile == NULL ) + { + /* Either the file was not opened, or all the data from the file has + been returned and the file is now closed. */ + xReturn = pdFALSE; + } + + strcat( pcWriteBuffer, cliNEW_LINE ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvCDCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *pcParameter; +BaseType_t xParameterStringLength; +unsigned char ucReturned; +size_t xStringLength; + + /* Obtain the parameter string. */ + pcParameter = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 1, /* Return the first parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcParameter ); + + /* Attempt to move to the requested directory. */ + ucReturned = f_chdir( pcParameter ); + + if( ucReturned == F_NO_ERROR ) + { + sprintf( pcWriteBuffer, "In: " ); + xStringLength = strlen( pcWriteBuffer ); + f_getcwd( &( pcWriteBuffer[ xStringLength ] ), ( unsigned char ) ( xWriteBufferLen - xStringLength ) ); + } + else + { + sprintf( pcWriteBuffer, "Error" ); + } + + strcat( pcWriteBuffer, cliNEW_LINE ); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvDIRCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +static F_FIND *pxFindStruct = NULL; +unsigned char ucReturned; +BaseType_t xReturn = pdFALSE; + + /* This assumes pcWriteBuffer is long enough. */ + ( void ) pcCommandString; + + /* Ensure the buffer leaves space for the \r\n. */ + configASSERT( xWriteBufferLen > ( strlen( cliNEW_LINE ) * 2 ) ); + xWriteBufferLen -= strlen( cliNEW_LINE ); + + if( pxFindStruct == NULL ) + { + /* This is the first time this function has been executed since the Dir + command was run. Create the find structure. */ + pxFindStruct = ( F_FIND * ) pvPortMalloc( sizeof( F_FIND ) ); + + if( pxFindStruct != NULL ) + { + ucReturned = f_findfirst( "*.*", pxFindStruct ); + + if( ucReturned == F_NO_ERROR ) + { + prvCreateFileInfoString( pcWriteBuffer, pxFindStruct ); + xReturn = pdPASS; + } + else + { + snprintf( pcWriteBuffer, xWriteBufferLen, "Error: f_findfirst() failed." ); + } + } + else + { + snprintf( pcWriteBuffer, xWriteBufferLen, "Failed to allocate RAM (using heap_4.c will prevent fragmentation)." ); + } + } + else + { + /* The find struct has already been created. Find the next file in + the directory. */ + ucReturned = f_findnext( pxFindStruct ); + + if( ucReturned == F_NO_ERROR ) + { + prvCreateFileInfoString( pcWriteBuffer, pxFindStruct ); + xReturn = pdPASS; + } + else + { + /* There are no more files. Free the find structure. */ + vPortFree( pxFindStruct ); + pxFindStruct = NULL; + + /* No string to return. */ + pcWriteBuffer[ 0 ] = 0x00; + } + } + + strcat( pcWriteBuffer, cliNEW_LINE ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvDELCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *pcParameter; +BaseType_t xParameterStringLength; +unsigned char ucReturned; + + /* This function assumes xWriteBufferLen is large enough! */ + ( void ) xWriteBufferLen; + + /* Obtain the parameter string. */ + pcParameter = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 1, /* Return the first parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcParameter ); + + /* Attempt to delete the file. */ + ucReturned = f_delete( pcParameter ); + + if( ucReturned == F_NO_ERROR ) + { + sprintf( pcWriteBuffer, "%s was deleted", pcParameter ); + } + else + { + sprintf( pcWriteBuffer, "Error" ); + } + + strcat( pcWriteBuffer, cliNEW_LINE ); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvCOPYCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +char *pcSourceFile, *pcDestinationFile; +BaseType_t xParameterStringLength; +long lSourceLength, lDestinationLength = 0; + + /* Obtain the name of the destination file. */ + pcDestinationFile = ( char * ) FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 2, /* Return the second parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcDestinationFile ); + + /* Obtain the name of the source file. */ + pcSourceFile = ( char * ) FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 1, /* Return the first parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcSourceFile ); + + /* Terminate the string. */ + pcSourceFile[ xParameterStringLength ] = 0x00; + + /* See if the source file exists, obtain its length if it does. */ + lSourceLength = f_filelength( pcSourceFile ); + + if( lSourceLength == 0 ) + { + sprintf( pcWriteBuffer, "Source file does not exist" ); + } + else + { + /* See if the destination file exists. */ + lDestinationLength = f_filelength( pcDestinationFile ); + + if( lDestinationLength != 0 ) + { + sprintf( pcWriteBuffer, "Error: Destination file already exists" ); + } + } + + /* Continue only if the source file exists and the destination file does + not exist. */ + if( ( lSourceLength != 0 ) && ( lDestinationLength == 0 ) ) + { + if( prvPerformCopy( pcSourceFile, lSourceLength, pcDestinationFile, pcWriteBuffer, xWriteBufferLen ) == pdPASS ) + { + sprintf( pcWriteBuffer, "Copy made" ); + } + else + { + sprintf( pcWriteBuffer, "Error during copy" ); + } + } + + strcat( pcWriteBuffer, cliNEW_LINE ); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvPerformCopy( const char *pcSourceFile, + int32_t lSourceFileLength, + const char *pcDestinationFile, + char *pxWriteBuffer, + size_t xWriteBufferLen ) +{ +int32_t lBytesRead = 0, lBytesToRead, lBytesRemaining; +F_FILE *pxFile; +BaseType_t xReturn = pdPASS; + + /* NOTE: Error handling has been omitted for clarity. */ + + while( lBytesRead < lSourceFileLength ) + { + /* How many bytes are left? */ + lBytesRemaining = lSourceFileLength - lBytesRead; + + /* How many bytes should be read this time around the loop. Can't + read more bytes than will fit into the buffer. */ + if( lBytesRemaining > ( long ) xWriteBufferLen ) + { + lBytesToRead = ( long ) xWriteBufferLen; + } + else + { + lBytesToRead = lBytesRemaining; + } + + /* Open the source file, seek past the data that has already been + read from the file, read the next block of data, then close the + file again so the destination file can be opened. */ + pxFile = f_open( pcSourceFile, "r" ); + if( pxFile != NULL ) + { + f_seek( pxFile, lBytesRead, F_SEEK_SET ); + f_read( pxWriteBuffer, lBytesToRead, 1, pxFile ); + f_close( pxFile ); + } + else + { + xReturn = pdFAIL; + break; + } + + /* Open the destination file and write the block of data to the end of + the file. */ + pxFile = f_open( pcDestinationFile, "a" ); + if( pxFile != NULL ) + { + f_write( pxWriteBuffer, lBytesToRead, 1, pxFile ); + f_close( pxFile ); + } + else + { + xReturn = pdFAIL; + break; + } + + lBytesRead += lBytesToRead; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static void prvCreateFileInfoString( char *pcBuffer, F_FIND *pxFindStruct ) +{ +const char *pcWritableFile = "writable file", *pcReadOnlyFile = "read only file", *pcDirectory = "directory"; +const char * pcAttrib; + + /* Point pcAttrib to a string that describes the file. */ + if( ( pxFindStruct->attr & F_ATTR_DIR ) != 0 ) + { + pcAttrib = pcDirectory; + } + else if( pxFindStruct->attr & F_ATTR_READONLY ) + { + pcAttrib = pcReadOnlyFile; + } + else + { + pcAttrib = pcWritableFile; + } + + /* Create a string that includes the file name, the file size and the + attributes string. */ + sprintf( pcBuffer, "%s [%s] [size=%d]", pxFindStruct->filename, pcAttrib, ( int ) pxFindStruct->filesize ); +} diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/Sample-CLI-commands.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/Sample-CLI-commands.c new file mode 100644 index 0000000..fd54884 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/Sample-CLI-commands.c @@ -0,0 +1,480 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + + /****************************************************************************** + * + * http://www.FreeRTOS.org/cli + * + ******************************************************************************/ + + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Standard includes. */ +#include +#include +#include +#include + +/* FreeRTOS+CLI includes. */ +#include "FreeRTOS_CLI.h" + +#ifndef configINCLUDE_TRACE_RELATED_CLI_COMMANDS + #define configINCLUDE_TRACE_RELATED_CLI_COMMANDS 0 +#endif + +#ifndef configINCLUDE_QUERY_HEAP_COMMAND + #define configINCLUDE_QUERY_HEAP_COMMAND 0 +#endif + +/* + * The function that registers the commands that are defined within this file. + */ +void vRegisterSampleCLICommands( void ); + +/* + * Implements the task-stats command. + */ +static BaseType_t prvTaskStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the run-time-stats command. + */ +#if( configGENERATE_RUN_TIME_STATS == 1 ) + static BaseType_t prvRunTimeStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); +#endif /* configGENERATE_RUN_TIME_STATS */ + +/* + * Implements the echo-three-parameters command. + */ +static BaseType_t prvThreeParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the echo-parameters command. + */ +static BaseType_t prvParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the "query heap" command. + */ +#if( configINCLUDE_QUERY_HEAP_COMMAND == 1 ) + static BaseType_t prvQueryHeapCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); +#endif + +/* + * Implements the "trace start" and "trace stop" commands; + */ +#if( configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 ) + static BaseType_t prvStartStopTraceCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); +#endif + +/* Structure that defines the "task-stats" command line command. This generates +a table that gives information on each task in the system. */ +static const CLI_Command_Definition_t xTaskStats = +{ + "task-stats", /* The command string to type. */ + "\r\ntask-stats:\r\n Displays a table showing the state of each FreeRTOS task\r\n", + prvTaskStatsCommand, /* The function to run. */ + 0 /* No parameters are expected. */ +}; + +/* Structure that defines the "echo_3_parameters" command line command. This +takes exactly three parameters that the command simply echos back one at a +time. */ +static const CLI_Command_Definition_t xThreeParameterEcho = +{ + "echo-3-parameters", + "\r\necho-3-parameters :\r\n Expects three parameters, echos each in turn\r\n", + prvThreeParameterEchoCommand, /* The function to run. */ + 3 /* Three parameters are expected, which can take any value. */ +}; + +/* Structure that defines the "echo_parameters" command line command. This +takes a variable number of parameters that the command simply echos back one at +a time. */ +static const CLI_Command_Definition_t xParameterEcho = +{ + "echo-parameters", + "\r\necho-parameters <...>:\r\n Take variable number of parameters, echos each in turn\r\n", + prvParameterEchoCommand, /* The function to run. */ + -1 /* The user can enter any number of commands. */ +}; + +#if( configGENERATE_RUN_TIME_STATS == 1 ) + /* Structure that defines the "run-time-stats" command line command. This + generates a table that shows how much run time each task has */ + static const CLI_Command_Definition_t xRunTimeStats = + { + "run-time-stats", /* The command string to type. */ + "\r\nrun-time-stats:\r\n Displays a table showing how much processing time each FreeRTOS task has used\r\n", + prvRunTimeStatsCommand, /* The function to run. */ + 0 /* No parameters are expected. */ + }; +#endif /* configGENERATE_RUN_TIME_STATS */ + +#if( configINCLUDE_QUERY_HEAP_COMMAND == 1 ) + /* Structure that defines the "query_heap" command line command. */ + static const CLI_Command_Definition_t xQueryHeap = + { + "query-heap", + "\r\nquery-heap:\r\n Displays the free heap space, and minimum ever free heap space.\r\n", + prvQueryHeapCommand, /* The function to run. */ + 0 /* The user can enter any number of commands. */ + }; +#endif /* configQUERY_HEAP_COMMAND */ + +#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 + /* Structure that defines the "trace" command line command. This takes a single + parameter, which can be either "start" or "stop". */ + static const CLI_Command_Definition_t xStartStopTrace = + { + "trace", + "\r\ntrace [start | stop]:\r\n Starts or stops a trace recording for viewing in FreeRTOS+Trace\r\n", + prvStartStopTraceCommand, /* The function to run. */ + 1 /* One parameter is expected. Valid values are "start" and "stop". */ + }; +#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */ + +/*-----------------------------------------------------------*/ + +void vRegisterSampleCLICommands( void ) +{ + /* Register all the command line commands defined immediately above. */ + FreeRTOS_CLIRegisterCommand( &xTaskStats ); + FreeRTOS_CLIRegisterCommand( &xThreeParameterEcho ); + FreeRTOS_CLIRegisterCommand( &xParameterEcho ); + + #if( configGENERATE_RUN_TIME_STATS == 1 ) + { + FreeRTOS_CLIRegisterCommand( &xRunTimeStats ); + } + #endif + + #if( configINCLUDE_QUERY_HEAP_COMMAND == 1 ) + { + FreeRTOS_CLIRegisterCommand( &xQueryHeap ); + } + #endif + + #if( configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 ) + { + FreeRTOS_CLIRegisterCommand( &xStartStopTrace ); + } + #endif +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTaskStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *const pcHeader = " State Priority Stack #\r\n************************************************\r\n"; +BaseType_t xSpacePadding; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + /* Generate a table of task stats. */ + strcpy( pcWriteBuffer, "Task" ); + pcWriteBuffer += strlen( pcWriteBuffer ); + + /* Minus three for the null terminator and half the number of characters in + "Task" so the column lines up with the centre of the heading. */ + configASSERT( configMAX_TASK_NAME_LEN > 3 ); + for( xSpacePadding = strlen( "Task" ); xSpacePadding < ( configMAX_TASK_NAME_LEN - 3 ); xSpacePadding++ ) + { + /* Add a space to align columns after the task's name. */ + *pcWriteBuffer = ' '; + pcWriteBuffer++; + + /* Ensure always terminated. */ + *pcWriteBuffer = 0x00; + } + strcpy( pcWriteBuffer, pcHeader ); + vTaskList( pcWriteBuffer + strlen( pcHeader ) ); + + /* There is no more data to return after this single string, so return + pdFALSE. */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +#if( configINCLUDE_QUERY_HEAP_COMMAND == 1 ) + + static BaseType_t prvQueryHeapCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) + { + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + sprintf( pcWriteBuffer, "Current free heap %d bytes, minimum ever free heap %d bytes\r\n", ( int ) xPortGetFreeHeapSize(), ( int ) xPortGetMinimumEverFreeHeapSize() ); + + /* There is no more data to return after this single string, so return + pdFALSE. */ + return pdFALSE; + } + +#endif /* configINCLUDE_QUERY_HEAP */ +/*-----------------------------------------------------------*/ + +#if( configGENERATE_RUN_TIME_STATS == 1 ) + + static BaseType_t prvRunTimeStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) + { + const char * const pcHeader = " Abs Time % Time\r\n****************************************\r\n"; + BaseType_t xSpacePadding; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + /* Generate a table of task stats. */ + strcpy( pcWriteBuffer, "Task" ); + pcWriteBuffer += strlen( pcWriteBuffer ); + + /* Pad the string "task" with however many bytes necessary to make it the + length of a task name. Minus three for the null terminator and half the + number of characters in "Task" so the column lines up with the centre of + the heading. */ + for( xSpacePadding = strlen( "Task" ); xSpacePadding < ( configMAX_TASK_NAME_LEN - 3 ); xSpacePadding++ ) + { + /* Add a space to align columns after the task's name. */ + *pcWriteBuffer = ' '; + pcWriteBuffer++; + + /* Ensure always terminated. */ + *pcWriteBuffer = 0x00; + } + + strcpy( pcWriteBuffer, pcHeader ); + vTaskGetRunTimeStats( pcWriteBuffer + strlen( pcHeader ) ); + + /* There is no more data to return after this single string, so return + pdFALSE. */ + return pdFALSE; + } + +#endif /* configGENERATE_RUN_TIME_STATS */ +/*-----------------------------------------------------------*/ + +static BaseType_t prvThreeParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *pcParameter; +BaseType_t xParameterStringLength, xReturn; +static UBaseType_t uxParameterNumber = 0; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + if( uxParameterNumber == 0 ) + { + /* The first time the function is called after the command has been + entered just a header string is returned. */ + sprintf( pcWriteBuffer, "The three parameters were:\r\n" ); + + /* Next time the function is called the first parameter will be echoed + back. */ + uxParameterNumber = 1U; + + /* There is more data to be returned as no parameters have been echoed + back yet. */ + xReturn = pdPASS; + } + else + { + /* Obtain the parameter string. */ + pcParameter = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + uxParameterNumber, /* Return the next parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcParameter ); + + /* Return the parameter string. */ + memset( pcWriteBuffer, 0x00, xWriteBufferLen ); + sprintf( pcWriteBuffer, "%d: ", ( int ) uxParameterNumber ); + strncat( pcWriteBuffer, pcParameter, ( size_t ) xParameterStringLength ); + strncat( pcWriteBuffer, "\r\n", strlen( "\r\n" ) ); + + /* If this is the last of the three parameters then there are no more + strings to return after this one. */ + if( uxParameterNumber == 3U ) + { + /* If this is the last of the three parameters then there are no more + strings to return after this one. */ + xReturn = pdFALSE; + uxParameterNumber = 0; + } + else + { + /* There are more parameters to return after this one. */ + xReturn = pdTRUE; + uxParameterNumber++; + } + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *pcParameter; +BaseType_t xParameterStringLength, xReturn; +static UBaseType_t uxParameterNumber = 0; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + if( uxParameterNumber == 0 ) + { + /* The first time the function is called after the command has been + entered just a header string is returned. */ + sprintf( pcWriteBuffer, "The parameters were:\r\n" ); + + /* Next time the function is called the first parameter will be echoed + back. */ + uxParameterNumber = 1U; + + /* There is more data to be returned as no parameters have been echoed + back yet. */ + xReturn = pdPASS; + } + else + { + /* Obtain the parameter string. */ + pcParameter = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + uxParameterNumber, /* Return the next parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + if( pcParameter != NULL ) + { + /* Return the parameter string. */ + memset( pcWriteBuffer, 0x00, xWriteBufferLen ); + sprintf( pcWriteBuffer, "%d: ", ( int ) uxParameterNumber ); + strncat( pcWriteBuffer, ( char * ) pcParameter, ( size_t ) xParameterStringLength ); + strncat( pcWriteBuffer, "\r\n", strlen( "\r\n" ) ); + + /* There might be more parameters to return after this one. */ + xReturn = pdTRUE; + uxParameterNumber++; + } + else + { + /* No more parameters were found. Make sure the write buffer does + not contain a valid string. */ + pcWriteBuffer[ 0 ] = 0x00; + + /* No more data to return. */ + xReturn = pdFALSE; + + /* Start over the next time this command is executed. */ + uxParameterNumber = 0; + } + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 + + static BaseType_t prvStartStopTraceCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) + { + const char *pcParameter; + BaseType_t lParameterStringLength; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + /* Obtain the parameter string. */ + pcParameter = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 1, /* Return the first parameter. */ + &lParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcParameter ); + + /* There are only two valid parameter values. */ + if( strncmp( pcParameter, "start", strlen( "start" ) ) == 0 ) + { + /* Start or restart the trace. */ + vTraceStop(); + vTraceClear(); + vTraceStart(); + + sprintf( pcWriteBuffer, "Trace recording (re)started.\r\n" ); + } + else if( strncmp( pcParameter, "stop", strlen( "stop" ) ) == 0 ) + { + /* End the trace, if one is running. */ + vTraceStop(); + sprintf( pcWriteBuffer, "Stopping trace recording.\r\n" ); + } + else + { + sprintf( pcWriteBuffer, "Valid parameters are 'start' and 'stop'.\r\n" ); + } + + /* There is no more data to return after this single string, so return + pdFALSE. */ + return pdFALSE; + } + +#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/UARTCommandConsole.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/UARTCommandConsole.c new file mode 100644 index 0000000..ba3a43e --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/UARTCommandConsole.c @@ -0,0 +1,226 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * NOTE: This file uses a third party USB CDC driver. + */ + +/* Standard includes. */ +#include "string.h" +#include "stdio.h" + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Example includes. */ +#include "FreeRTOS_CLI.h" + +/* Demo application includes. */ +#include "serial.h" + +/* Dimensions the buffer into which input characters are placed. */ +#define cmdMAX_INPUT_SIZE 50 + +/* Dimentions a buffer to be used by the UART driver, if the UART driver uses a +buffer at all. */ +#define cmdQUEUE_LENGTH 25 + +/* DEL acts as a backspace. */ +#define cmdASCII_DEL ( 0x7F ) + +/* The maximum time to wait for the mutex that guards the UART to become +available. */ +#define cmdMAX_MUTEX_WAIT pdMS_TO_TICKS( 300 ) + +#ifndef configCLI_BAUD_RATE + #define configCLI_BAUD_RATE 115200 +#endif + +/*-----------------------------------------------------------*/ + +/* + * The task that implements the command console processing. + */ +static void prvUARTCommandConsoleTask( void *pvParameters ); +void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority ); + +/*-----------------------------------------------------------*/ + +/* Const messages output by the command console. */ +static const char * const pcWelcomeMessage = "FreeRTOS command server.\r\nType Help to view a list of registered commands.\r\n\r\n>"; +static const char * const pcEndOfOutputMessage = "\r\n[Press ENTER to execute the previous command again]\r\n>"; +static const char * const pcNewLine = "\r\n"; + +/* Used to guard access to the UART in case messages are sent to the UART from +more than one task. */ +static SemaphoreHandle_t xTxMutex = NULL; + +/* The handle to the UART port, which is not used by all ports. */ +static xComPortHandle xPort = 0; + +/*-----------------------------------------------------------*/ + +void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority ) +{ + /* Create the semaphore used to access the UART Tx. */ + xTxMutex = xSemaphoreCreateMutex(); + configASSERT( xTxMutex ); + + /* Create that task that handles the console itself. */ + xTaskCreate( prvUARTCommandConsoleTask, /* The task that implements the command console. */ + "CLI", /* Text name assigned to the task. This is just to assist debugging. The kernel does not use this name itself. */ + usStackSize, /* The size of the stack allocated to the task. */ + NULL, /* The parameter is not used, so NULL is passed. */ + uxPriority, /* The priority allocated to the task. */ + NULL ); /* A handle is not required, so just pass NULL. */ +} +/*-----------------------------------------------------------*/ + +static void prvUARTCommandConsoleTask( void *pvParameters ) +{ +signed char cRxedChar; +uint8_t ucInputIndex = 0; +char *pcOutputString; +static char cInputString[ cmdMAX_INPUT_SIZE ], cLastInputString[ cmdMAX_INPUT_SIZE ]; +BaseType_t xReturned; +xComPortHandle xPort; + + ( void ) pvParameters; + + /* Obtain the address of the output buffer. Note there is no mutual + exclusion on this buffer as it is assumed only one command console interface + will be used at any one time. */ + pcOutputString = FreeRTOS_CLIGetOutputBuffer(); + + /* Initialise the UART. */ + xPort = xSerialPortInitMinimal( configCLI_BAUD_RATE, cmdQUEUE_LENGTH ); + + /* Send the welcome message. */ + vSerialPutString( xPort, ( signed char * ) pcWelcomeMessage, ( unsigned short ) strlen( pcWelcomeMessage ) ); + + for( ;; ) + { + /* Wait for the next character. The while loop is used in case + INCLUDE_vTaskSuspend is not set to 1 - in which case portMAX_DELAY will + be a genuine block time rather than an infinite block time. */ + while( xSerialGetChar( xPort, &cRxedChar, portMAX_DELAY ) != pdPASS ); + + /* Ensure exclusive access to the UART Tx. */ + if( xSemaphoreTake( xTxMutex, cmdMAX_MUTEX_WAIT ) == pdPASS ) + { + /* Echo the character back. */ + xSerialPutChar( xPort, cRxedChar, portMAX_DELAY ); + + /* Was it the end of the line? */ + if( cRxedChar == '\n' || cRxedChar == '\r' ) + { + /* Just to space the output from the input. */ + vSerialPutString( xPort, ( signed char * ) pcNewLine, ( unsigned short ) strlen( pcNewLine ) ); + + /* See if the command is empty, indicating that the last command + is to be executed again. */ + if( ucInputIndex == 0 ) + { + /* Copy the last command back into the input string. */ + strcpy( cInputString, cLastInputString ); + } + + /* Pass the received command to the command interpreter. The + command interpreter is called repeatedly until it returns + pdFALSE (indicating there is no more output) as it might + generate more than one string. */ + do + { + /* Get the next output string from the command interpreter. */ + xReturned = FreeRTOS_CLIProcessCommand( cInputString, pcOutputString, configCOMMAND_INT_MAX_OUTPUT_SIZE ); + + /* Write the generated string to the UART. */ + vSerialPutString( xPort, ( signed char * ) pcOutputString, ( unsigned short ) strlen( pcOutputString ) ); + + } while( xReturned != pdFALSE ); + + /* All the strings generated by the input command have been + sent. Clear the input string ready to receive the next command. + Remember the command that was just processed first in case it is + to be processed again. */ + strcpy( cLastInputString, cInputString ); + ucInputIndex = 0; + memset( cInputString, 0x00, cmdMAX_INPUT_SIZE ); + + vSerialPutString( xPort, ( signed char * ) pcEndOfOutputMessage, ( unsigned short ) strlen( pcEndOfOutputMessage ) ); + } + else + { + if( cRxedChar == '\r' ) + { + /* Ignore the character. */ + } + else if( ( cRxedChar == '\b' ) || ( cRxedChar == cmdASCII_DEL ) ) + { + /* Backspace was pressed. Erase the last character in the + string - if any. */ + if( ucInputIndex > 0 ) + { + ucInputIndex--; + cInputString[ ucInputIndex ] = '\0'; + } + } + else + { + /* A character was entered. Add it to the string entered so + far. When a \n is entered the complete string will be + passed to the command interpreter. */ + if( ( cRxedChar >= ' ' ) && ( cRxedChar <= '~' ) ) + { + if( ucInputIndex < cmdMAX_INPUT_SIZE ) + { + cInputString[ ucInputIndex ] = cRxedChar; + ucInputIndex++; + } + } + } + } + + /* Must ensure to give the mutex back. */ + xSemaphoreGive( xTxMutex ); + } + } +} +/*-----------------------------------------------------------*/ + +void vOutputString( const char * const pcMessage ) +{ + if( xSemaphoreTake( xTxMutex, cmdMAX_MUTEX_WAIT ) == pdPASS ) + { + vSerialPutString( xPort, ( signed char * ) pcMessage, ( unsigned short ) strlen( pcMessage ) ); + xSemaphoreGive( xTxMutex ); + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/UDP-Related-CLI-commands.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/UDP-Related-CLI-commands.c new file mode 100644 index 0000000..bac9b7a --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/UDP-Related-CLI-commands.c @@ -0,0 +1,313 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + /****************************************************************************** + * + * See the following URL for information on the commands defined in this file: + * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Ethernet_Related_CLI_Commands.shtml + * + ******************************************************************************/ + + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Standard includes. */ +#include +#include +#include + +/* FreeRTOS+CLI includes. */ +#include "FreeRTOS_CLI.h" + +/* FreeRTOS+UDP includes, just to make the stats available to the CLI +commands. */ +#include "FreeRTOS_UDP_IP.h" +#include "FreeRTOS_Sockets.h" + +/* + * Defines a command that prints out IP address information. + */ +static BaseType_t prvDisplayIPConfig( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Defines a command that prints out the gathered demo debug stats. + */ +static BaseType_t prvDisplayIPDebugStats( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Defines a command that sends an ICMP ping request to an IP address. + */ +static BaseType_t prvPingCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* Structure that defines the "ip-config" command line command. */ +static const CLI_Command_Definition_t xIPConfig = +{ + "ip-config", + "ip-config:\r\n Displays IP address configuration\r\n\r\n", + prvDisplayIPConfig, + 0 +}; + +#if configINCLUDE_DEMO_DEBUG_STATS != 0 + /* Structure that defines the "ip-debug-stats" command line command. */ + static const CLI_Command_Definition_t xIPDebugStats = + { + "ip-debug-stats", /* The command string to type. */ + "ip-debug-stats:\r\n Shows some IP stack stats useful for debug - an example only.\r\n\r\n", + prvDisplayIPDebugStats, /* The function to run. */ + 0 /* No parameters are expected. */ + }; +#endif /* configINCLUDE_DEMO_DEBUG_STATS */ + +#if ipconfigSUPPORT_OUTGOING_PINGS == 1 + + /* Structure that defines the "ping" command line command. This takes an IP + address or host name and (optionally) the number of bytes to ping as + parameters. */ + static const CLI_Command_Definition_t xPing = + { + "ping", + "ping :\r\n for example, ping 192.168.0.3 8, or ping www.example.com\r\n\r\n", + prvPingCommand, /* The function to run. */ + -1 /* Ping can take either one or two parameter, so the number of parameters has to be determined by the ping command implementation. */ + }; + +#endif /* ipconfigSUPPORT_OUTGOING_PINGS */ + + +/*-----------------------------------------------------------*/ + +void vRegisterUDPCLICommands( void ) +{ + /* Register all the command line commands defined immediately above. */ + FreeRTOS_CLIRegisterCommand( &xIPConfig ); + + #if configINCLUDE_DEMO_DEBUG_STATS == 1 + { + FreeRTOS_CLIRegisterCommand( &xIPDebugStats ); + } + #endif /* configINCLUDE_DEMO_DEBUG_STATS */ + + #if ipconfigSUPPORT_OUTGOING_PINGS == 1 + { + FreeRTOS_CLIRegisterCommand( &xPing ); + } + #endif /* ipconfigSUPPORT_OUTGOING_PINGS */ +} +/*-----------------------------------------------------------*/ + +#if ipconfigSUPPORT_OUTGOING_PINGS == 1 + + static BaseType_t prvPingCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) + { + char * pcParameter; + BaseType_t lParameterStringLength, xReturn; + uint32_t ulIPAddress, ulBytesToPing; + const uint32_t ulDefaultBytesToPing = 8UL; + char cBuffer[ 16 ]; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + /* Start with an empty string. */ + pcWriteBuffer[ 0 ] = 0x00; + + /* Obtain the number of bytes to ping. */ + pcParameter = ( char * ) FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 2, /* Return the second parameter. */ + &lParameterStringLength /* Store the parameter string length. */ + ); + + if( pcParameter == NULL ) + { + /* The number of bytes was not specified, so default it. */ + ulBytesToPing = ulDefaultBytesToPing; + } + else + { + ulBytesToPing = atol( pcParameter ); + } + + /* Obtain the IP address string. */ + pcParameter = ( char * ) FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 1, /* Return the first parameter. */ + &lParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcParameter ); + + /* Attempt to obtain the IP address. If the first character is not a + digit, assume the host name has been passed in. */ + if( ( *pcParameter >= '0' ) && ( *pcParameter <= '9' ) ) + { + ulIPAddress = FreeRTOS_inet_addr( pcParameter ); + } + else + { + /* Terminate the host name. */ + pcParameter[ lParameterStringLength ] = 0x00; + + /* Attempt to resolve host. */ + ulIPAddress = FreeRTOS_gethostbyname( pcParameter ); + } + + /* Convert IP address, which may have come from a DNS lookup, to string. */ + FreeRTOS_inet_ntoa( ulIPAddress, cBuffer ); + + if( ulIPAddress != 0 ) + { + xReturn = FreeRTOS_SendPingRequest( ulIPAddress, ( uint16_t ) ulBytesToPing, portMAX_DELAY ); + } + else + { + xReturn = pdFALSE; + } + + if( xReturn == pdFALSE ) + { + sprintf( pcWriteBuffer, "%s", "Could not send ping request\r\n" ); + } + else + { + sprintf( pcWriteBuffer, "Ping sent to %s with identifier %d\r\n", cBuffer, ( int ) xReturn ); + } + + return pdFALSE; + } + /*-----------------------------------------------------------*/ + +#endif /* ipconfigSUPPORT_OUTGOING_PINGS */ + +#if configINCLUDE_DEMO_DEBUG_STATS != 0 + + static BaseType_t prvDisplayIPDebugStats( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) + { + static BaseType_t xIndex = -1; + extern xExampleDebugStatEntry_t xIPTraceValues[]; + BaseType_t xReturn; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + xIndex++; + + if( xIndex < xExampleDebugStatEntries() ) + { + sprintf( pcWriteBuffer, "%s %d\r\n", ( char * ) xIPTraceValues[ xIndex ].pucDescription, ( int ) xIPTraceValues[ xIndex ].ulData ); + xReturn = pdPASS; + } + else + { + /* Reset the index for the next time it is called. */ + xIndex = -1; + + /* Ensure nothing remains in the write buffer. */ + pcWriteBuffer[ 0 ] = 0x00; + xReturn = pdFALSE; + } + + return xReturn; + } + /*-----------------------------------------------------------*/ + +#endif /* configINCLUDE_DEMO_DEBUG_STATS */ + +static BaseType_t prvDisplayIPConfig( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +static BaseType_t xIndex = 0; +BaseType_t xReturn; +uint32_t ulAddress; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + switch( xIndex ) + { + case 0 : + FreeRTOS_GetAddressConfiguration( &ulAddress, NULL, NULL, NULL ); + sprintf( pcWriteBuffer, "\r\nIP address " ); + xReturn = pdTRUE; + xIndex++; + break; + + case 1 : + FreeRTOS_GetAddressConfiguration( NULL, &ulAddress, NULL, NULL ); + sprintf( pcWriteBuffer, "\r\nNet mask " ); + xReturn = pdTRUE; + xIndex++; + break; + + case 2 : + FreeRTOS_GetAddressConfiguration( NULL, NULL, &ulAddress, NULL ); + sprintf( pcWriteBuffer, "\r\nGateway address " ); + xReturn = pdTRUE; + xIndex++; + break; + + case 3 : + FreeRTOS_GetAddressConfiguration( NULL, NULL, NULL, &ulAddress ); + sprintf( pcWriteBuffer, "\r\nDNS server address " ); + xReturn = pdTRUE; + xIndex++; + break; + + default : + ulAddress = 0; + sprintf( pcWriteBuffer, "\r\n\r\n" ); + xReturn = pdFALSE; + xIndex = 0; + break; + } + + if( ulAddress != 0 ) + { + FreeRTOS_inet_ntoa( ulAddress, ( &( pcWriteBuffer[ strlen( pcWriteBuffer ) ] ) ) ); + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_FAT_SL_Demos/CreateExampleFiles/File-system-demo.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_FAT_SL_Demos/CreateExampleFiles/File-system-demo.c new file mode 100644 index 0000000..1574635 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_FAT_SL_Demos/CreateExampleFiles/File-system-demo.c @@ -0,0 +1,321 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/******************************************************************************* + * See the URL in the comments within main.c for the location of the online + * documentation. + ******************************************************************************/ + +/* Standard includes. */ +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" + +/* File system includes. */ +#include "fat_sl.h" +#include "api_mdriver_ram.h" + +/* 8.3 format, plus null terminator. */ +#define fsMAX_FILE_NAME_LEN 13 + +/* The number of bytes read/written to the example files at a time. */ +#define fsRAM_BUFFER_SIZE 200 + +/* The number of bytes written to the file that uses f_putc() and f_getc(). */ +#define fsPUTC_FILE_SIZE 100 + +/*-----------------------------------------------------------*/ + +/* + * Creates and verifies different files on the volume, demonstrating the use of + * various different API functions. + */ +void vCreateAndVerifySampleFiles( void ); + +/* + * Create a set of example files in the root directory of the volume using + * f_write(). + */ +static void prvCreateDemoFilesUsing_f_write( void ); + +/* + * Use f_read() to read back and verify the files that were created by + * prvCreateDemoFilesUsing_f_write(). + */ +static void prvVerifyDemoFileUsing_f_read( void ); + +/* + * Create an example file in a sub-directory using f_putc(). + */ +static void prvCreateDemoFileUsing_f_putc( void ); + +/* + * Use f_getc() to read back and verify the file that was created by + * prvCreateDemoFileUsing_f_putc(). + */ +static void prvVerifyDemoFileUsing_f_getc( void ); + +/*-----------------------------------------------------------*/ + +/* A buffer used to both create content to write to disk, and read content back +from a disk. Note there is no mutual exclusion on this buffer. */ +static char cRAMBuffer[ fsRAM_BUFFER_SIZE ]; + +/* Names of directories that are created. */ +static const char *pcRoot = "/", *pcDirectory1 = "SUB1", *pcDirectory2 = "SUB2", *pcFullPath = "/SUB1/SUB2"; + +/*-----------------------------------------------------------*/ + +void vCreateAndVerifySampleFiles( void ) +{ +unsigned char ucStatus; + + /* First create the volume. */ + ucStatus = f_initvolume( ram_initfunc ); + + /* It is expected that the volume is not formatted. */ + if( ucStatus == F_ERR_NOTFORMATTED ) + { + /* Format the created volume. */ + ucStatus = f_format( F_FAT12_MEDIA ); + } + + if( ucStatus == F_NO_ERROR ) + { + /* Create a set of files using f_write(). */ + prvCreateDemoFilesUsing_f_write(); + + /* Read back and verify the files that were created using f_write(). */ + prvVerifyDemoFileUsing_f_read(); + + /* Create sub directories two deep then create a file using putc. */ + prvCreateDemoFileUsing_f_putc(); + + /* Read back and verify the file created by + prvCreateDemoFileUsing_f_putc(). */ + prvVerifyDemoFileUsing_f_getc(); + } +} +/*-----------------------------------------------------------*/ + +static void prvCreateDemoFilesUsing_f_write( void ) +{ +BaseType_t xFileNumber, xWriteNumber; +char cFileName[ fsMAX_FILE_NAME_LEN ]; +const BaseType_t xMaxFiles = 5; +long lItemsWritten; +F_FILE *pxFile; + + /* Create xMaxFiles files. Each created file will be + ( xFileNumber * fsRAM_BUFFER_SIZE ) bytes in length, and filled + with a different repeating character. */ + for( xFileNumber = 1; xFileNumber <= xMaxFiles; xFileNumber++ ) + { + /* Generate a file name. */ + sprintf( cFileName, "root%03d.txt", ( int ) xFileNumber ); + + /* Obtain the current working directory and print out the file name and + the directory into which the file is being written. */ + f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE ); + + /* Open the file, creating the file if it does not already exist. */ + pxFile = f_open( cFileName, "w" ); + configASSERT( pxFile ); + + /* Fill the RAM buffer with data that will be written to the file. This + is just a repeating ascii character that indicates the file number. */ + memset( cRAMBuffer, ( int ) ( '0' + xFileNumber ), fsRAM_BUFFER_SIZE ); + + /* Write the RAM buffer to the opened file a number of times. The + number of times the RAM buffer is written to the file depends on the + file number, so the length of each created file will be different. */ + for( xWriteNumber = 0; xWriteNumber < xFileNumber; xWriteNumber++ ) + { + lItemsWritten = f_write( cRAMBuffer, fsRAM_BUFFER_SIZE, 1, pxFile ); + configASSERT( lItemsWritten == 1 ); + } + + /* Close the file so another file can be created. */ + f_close( pxFile ); + } +} +/*-----------------------------------------------------------*/ + +static void prvVerifyDemoFileUsing_f_read( void ) +{ +BaseType_t xFileNumber, xReadNumber; +char cFileName[ fsMAX_FILE_NAME_LEN ]; +const BaseType_t xMaxFiles = 5; +long lItemsRead, lChar; +F_FILE *pxFile; + + /* Read back the files that were created by + prvCreateDemoFilesUsing_f_write(). */ + for( xFileNumber = 1; xFileNumber <= xMaxFiles; xFileNumber++ ) + { + /* Generate the file name. */ + sprintf( cFileName, "root%03d.txt", ( int ) xFileNumber ); + + /* Obtain the current working directory and print out the file name and + the directory from which the file is being read. */ + f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE ); + + /* Open the file for reading. */ + pxFile = f_open( cFileName, "r" ); + configASSERT( pxFile ); + + /* Read the file into the RAM buffer, checking the file contents are as + expected. The size of the file depends on the file number. */ + for( xReadNumber = 0; xReadNumber < xFileNumber; xReadNumber++ ) + { + /* Start with the RAM buffer clear. */ + memset( cRAMBuffer, 0x00, fsRAM_BUFFER_SIZE ); + + lItemsRead = f_read( cRAMBuffer, fsRAM_BUFFER_SIZE, 1, pxFile ); + configASSERT( lItemsRead == 1 ); + + /* Check the RAM buffer is filled with the expected data. Each + file contains a different repeating ascii character that indicates + the number of the file. */ + for( lChar = 0; lChar < fsRAM_BUFFER_SIZE; lChar++ ) + { + configASSERT( cRAMBuffer[ lChar ] == ( '0' + ( char ) xFileNumber ) ); + } + } + + /* Close the file. */ + f_close( pxFile ); + } +} +/*-----------------------------------------------------------*/ + +static void prvCreateDemoFileUsing_f_putc( void ) +{ +unsigned char ucReturn; +int iByte, iReturned; +F_FILE *pxFile; +char cFileName[ fsMAX_FILE_NAME_LEN ]; + + /* Obtain and print out the working directory. */ + f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE ); + + /* Create a sub directory. */ + ucReturn = f_mkdir( pcDirectory1 ); + configASSERT( ucReturn == F_NO_ERROR ); + + /* Move into the created sub-directory. */ + ucReturn = f_chdir( pcDirectory1 ); + configASSERT( ucReturn == F_NO_ERROR ); + + /* Obtain and print out the working directory. */ + f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE ); + + /* Create a subdirectory in the new directory. */ + ucReturn = f_mkdir( pcDirectory2 ); + configASSERT( ucReturn == F_NO_ERROR ); + + /* Move into the directory just created - now two directories down from + the root. */ + ucReturn = f_chdir( pcDirectory2 ); + configASSERT( ucReturn == F_NO_ERROR ); + + /* Obtain and print out the working directory. */ + f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE ); + configASSERT( strcmp( cRAMBuffer, pcFullPath ) == 0 ); + + /* Generate the file name. */ + sprintf( cFileName, "%s.txt", pcDirectory2 ); + + /* Print out the file name and the directory into which the file is being + written. */ + pxFile = f_open( cFileName, "w" ); + + /* Create a file 1 byte at a time. The file is filled with incrementing + ascii characters starting from '0'. */ + for( iByte = 0; iByte < fsPUTC_FILE_SIZE; iByte++ ) + { + iReturned = f_putc( ( ( int ) '0' + iByte ), pxFile ); + configASSERT( iReturned == ( ( int ) '0' + iByte ) ); + } + + /* Finished so close the file. */ + f_close( pxFile ); + + /* Move back to the root directory. */ + ucReturn = f_chdir( "../.." ); + configASSERT( ucReturn == F_NO_ERROR ); + + /* Obtain and print out the working directory. */ + f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE ); + configASSERT( strcmp( cRAMBuffer, pcRoot ) == 0 ); +} +/*-----------------------------------------------------------*/ + +static void prvVerifyDemoFileUsing_f_getc( void ) +{ +unsigned char ucReturn; +int iByte, iReturned; +F_FILE *pxFile; +char cFileName[ fsMAX_FILE_NAME_LEN ]; + + /* Move into the directory in which the file was created. */ + ucReturn = f_chdir( pcFullPath ); + configASSERT( ucReturn == F_NO_ERROR ); + + /* Obtain and print out the working directory. */ + f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE ); + configASSERT( strcmp( cRAMBuffer, pcFullPath ) == 0 ); + + /* Generate the file name. */ + sprintf( cFileName, "%s.txt", pcDirectory2 ); + + /* This time the file is opened for reading. */ + pxFile = f_open( cFileName, "r" ); + + /* Read the file 1 byte at a time. */ + for( iByte = 0; iByte < fsPUTC_FILE_SIZE; iByte++ ) + { + iReturned = f_getc( pxFile ); + configASSERT( iReturned == ( ( int ) '0' + iByte ) ); + } + + /* Finished so close the file. */ + f_close( pxFile ); + + /* Move back to the root directory. */ + ucReturn = f_chdir( "../.." ); + configASSERT( ucReturn == F_NO_ERROR ); + + /* Obtain and print out the working directory. */ + f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE ); +} + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/CLICommands/CLI-commands.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/CLICommands/CLI-commands.c new file mode 100644 index 0000000..a432648 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/CLICommands/CLI-commands.c @@ -0,0 +1,664 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + /****************************************************************************** + * + * See the following URL for information on the commands defined in this file: + * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Ethernet_Related_CLI_Commands.shtml + * + ******************************************************************************/ + + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Standard includes. */ +#include +#include +#include + +/* FreeRTOS+CLI includes. */ +#include "FreeRTOS_CLI.h" + +/* FreeRTOS+UDP includes, just to make the stats available to the CLI +commands. */ +#include "FreeRTOS_UDP_IP.h" +#include "FreeRTOS_Sockets.h" + +#ifndef configINCLUDE_TRACE_RELATED_CLI_COMMANDS + #define configINCLUDE_TRACE_RELATED_CLI_COMMANDS 0 +#endif + + +/* + * Implements the run-time-stats command. + */ +static BaseType_t prvTaskStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the task-stats command. + */ +static BaseType_t prvRunTimeStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the echo-three-parameters command. + */ +static BaseType_t prvThreeParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the echo-parameters command. + */ +static BaseType_t prvParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Defines a command that prints out IP address information. + */ +static BaseType_t prvDisplayIPConfig( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Defines a command that prints out the gathered demo debug stats. + */ +static BaseType_t prvDisplayIPDebugStats( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Defines a command that sends an ICMP ping request to an IP address. + */ +static BaseType_t prvPingCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the "trace start" and "trace stop" commands; + */ +#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 + static BaseType_t prvStartStopTraceCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); +#endif + +/* Structure that defines the "ip-config" command line command. */ +static const CLI_Command_Definition_t xIPConfig = +{ + "ip-config", + "ip-config:\r\n Displays IP address configuration\r\n\r\n", + prvDisplayIPConfig, + 0 +}; + +#if configINCLUDE_DEMO_DEBUG_STATS != 0 + /* Structure that defines the "ip-debug-stats" command line command. */ + static const CLI_Command_Definition_t xIPDebugStats = + { + "ip-debug-stats", /* The command string to type. */ + "ip-debug-stats:\r\n Shows some IP stack stats useful for debug - an example only.\r\n\r\n", + prvDisplayIPDebugStats, /* The function to run. */ + 0 /* No parameters are expected. */ + }; +#endif /* configINCLUDE_DEMO_DEBUG_STATS */ + +/* Structure that defines the "run-time-stats" command line command. This +generates a table that shows how much run time each task has */ +static const CLI_Command_Definition_t xRunTimeStats = +{ + "run-time-stats", /* The command string to type. */ + "run-time-stats:\r\n Displays a table showing how much processing time each FreeRTOS task has used\r\n\r\n", + prvRunTimeStatsCommand, /* The function to run. */ + 0 /* No parameters are expected. */ +}; + +/* Structure that defines the "task-stats" command line command. This generates +a table that gives information on each task in the system. */ +static const CLI_Command_Definition_t xTaskStats = +{ + "task-stats", /* The command string to type. */ + "task-stats:\r\n Displays a table showing the state of each FreeRTOS task\r\n\r\n", + prvTaskStatsCommand, /* The function to run. */ + 0 /* No parameters are expected. */ +}; + +/* Structure that defines the "echo_3_parameters" command line command. This +takes exactly three parameters that the command simply echos back one at a +time. */ +static const CLI_Command_Definition_t xThreeParameterEcho = +{ + "echo-3-parameters", + "echo-3-parameters :\r\n Expects three parameters, echos each in turn\r\n\r\n", + prvThreeParameterEchoCommand, /* The function to run. */ + 3 /* Three parameters are expected, which can take any value. */ +}; + +/* Structure that defines the "echo_parameters" command line command. This +takes a variable number of parameters that the command simply echos back one at +a time. */ +static const CLI_Command_Definition_t xParameterEcho = +{ + "echo-parameters", + "echo-parameters <...>:\r\n Take variable number of parameters, echos each in turn\r\n\r\n", + prvParameterEchoCommand, /* The function to run. */ + -1 /* The user can enter any number of commands. */ +}; + +#if ipconfigSUPPORT_OUTGOING_PINGS == 1 + + /* Structure that defines the "ping" command line command. This takes an IP + address or host name and (optionally) the number of bytes to ping as + parameters. */ + static const CLI_Command_Definition_t xPing = + { + "ping", + "ping :\r\n for example, ping 192.168.0.3 8, or ping www.example.com\r\n\r\n", + prvPingCommand, /* The function to run. */ + -1 /* Ping can take either one or two parameter, so the number of parameters has to be determined by the ping command implementation. */ + }; + +#endif /* ipconfigSUPPORT_OUTGOING_PINGS */ + +#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 + /* Structure that defines the "trace" command line command. This takes a single + parameter, which can be either "start" or "stop". */ + static const CLI_Command_Definition_t xStartStopTrace = + { + "trace", + "trace [start | stop]:\r\n Starts or stops a trace recording for viewing in FreeRTOS+Trace\r\n\r\n", + prvStartStopTraceCommand, /* The function to run. */ + 1 /* One parameter is expected. Valid values are "start" and "stop". */ + }; +#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */ + +/*-----------------------------------------------------------*/ + +void vRegisterCLICommands( void ) +{ + /* Register all the command line commands defined immediately above. */ + FreeRTOS_CLIRegisterCommand( &xTaskStats ); + FreeRTOS_CLIRegisterCommand( &xRunTimeStats ); + FreeRTOS_CLIRegisterCommand( &xThreeParameterEcho ); + FreeRTOS_CLIRegisterCommand( &xParameterEcho ); + FreeRTOS_CLIRegisterCommand( &xIPDebugStats ); + FreeRTOS_CLIRegisterCommand( &xIPConfig ); + + #if ipconfigSUPPORT_OUTGOING_PINGS == 1 + { + FreeRTOS_CLIRegisterCommand( &xPing ); + } + #endif /* ipconfigSUPPORT_OUTGOING_PINGS */ + + #if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 + FreeRTOS_CLIRegisterCommand( & xStartStopTrace ); + #endif +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTaskStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *const pcHeader = " State\tPriority\tStack\t#\r\n************************************************\r\n"; +BaseType_t xSpacePadding; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + /* Generate a table of task stats. */ + strcpy( pcWriteBuffer, "Task" ); + pcWriteBuffer += strlen( pcWriteBuffer ); + + /* Pad the string "task" with however many bytes necessary to make it the + length of a task name. Minus three for the null terminator and half the + number of characters in "Task" so the column lines up with the centre of + the heading. */ + for( xSpacePadding = strlen( "Task" ); xSpacePadding < ( configMAX_TASK_NAME_LEN - 3 ); xSpacePadding++ ) + { + /* Add a space to align columns after the task's name. */ + *pcWriteBuffer = ' '; + pcWriteBuffer++; + + /* Ensure always terminated. */ + *pcWriteBuffer = 0x00; + } + strcpy( pcWriteBuffer, pcHeader ); + vTaskList( pcWriteBuffer + strlen( pcHeader ) ); + + /* There is no more data to return after this single string, so return + pdFALSE. */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvRunTimeStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char * const pcHeader = " Abs Time % Time\r\n****************************************\r\n"; +BaseType_t xSpacePadding; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + /* Generate a table of task stats. */ + strcpy( pcWriteBuffer, "Task" ); + pcWriteBuffer += strlen( pcWriteBuffer ); + + /* Pad the string "task" with however many bytes necessary to make it the + length of a task name. Minus three for the null terminator and half the + number of characters in "Task" so the column lines up with the centre of + the heading. */ + for( xSpacePadding = strlen( "Task" ); xSpacePadding < ( configMAX_TASK_NAME_LEN - 3 ); xSpacePadding++ ) + { + /* Add a space to align columns after the task's name. */ + *pcWriteBuffer = ' '; + pcWriteBuffer++; + + /* Ensure always terminated. */ + *pcWriteBuffer = 0x00; + } + + strcpy( pcWriteBuffer, pcHeader ); + vTaskGetRunTimeStats( pcWriteBuffer + strlen( pcHeader ) ); + + /* There is no more data to return after this single string, so return + pdFALSE. */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvThreeParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *pcParameter; +BaseType_t xParameterStringLength, xReturn; +static BaseType_t lParameterNumber = 0; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + if( lParameterNumber == 0 ) + { + /* The first time the function is called after the command has been + entered just a header string is returned. */ + sprintf( pcWriteBuffer, "The three parameters were:\r\n" ); + + /* Next time the function is called the first parameter will be echoed + back. */ + lParameterNumber = 1L; + + /* There is more data to be returned as no parameters have been echoed + back yet. */ + xReturn = pdPASS; + } + else + { + /* Obtain the parameter string. */ + pcParameter = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + lParameterNumber, /* Return the next parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcParameter ); + + /* Return the parameter string. */ + memset( pcWriteBuffer, 0x00, xWriteBufferLen ); + sprintf( pcWriteBuffer, "%d: ", ( int ) lParameterNumber ); + strncat( pcWriteBuffer, pcParameter, xParameterStringLength ); + strncat( pcWriteBuffer, "\r\n", strlen( "\r\n" ) ); + + /* If this is the last of the three parameters then there are no more + strings to return after this one. */ + if( lParameterNumber == 3L ) + { + /* If this is the last of the three parameters then there are no more + strings to return after this one. */ + xReturn = pdFALSE; + lParameterNumber = 0L; + } + else + { + /* There are more parameters to return after this one. */ + xReturn = pdTRUE; + lParameterNumber++; + } + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *pcParameter; +BaseType_t xParameterStringLength, xReturn; +static BaseType_t lParameterNumber = 0; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + if( lParameterNumber == 0 ) + { + /* The first time the function is called after the command has been + entered just a header string is returned. */ + sprintf( pcWriteBuffer, "The parameters were:\r\n" ); + + /* Next time the function is called the first parameter will be echoed + back. */ + lParameterNumber = 1L; + + /* There is more data to be returned as no parameters have been echoed + back yet. */ + xReturn = pdPASS; + } + else + { + /* Obtain the parameter string. */ + pcParameter = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + lParameterNumber, /* Return the next parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + if( pcParameter != NULL ) + { + /* Return the parameter string. */ + memset( pcWriteBuffer, 0x00, xWriteBufferLen ); + sprintf( pcWriteBuffer, "%d: ", ( int ) lParameterNumber ); + strncat( pcWriteBuffer, pcParameter, xParameterStringLength ); + strncat( pcWriteBuffer, "\r\n", strlen( "\r\n" ) ); + + /* There might be more parameters to return after this one. */ + xReturn = pdTRUE; + lParameterNumber++; + } + else + { + /* No more parameters were found. Make sure the write buffer does + not contain a valid string. */ + pcWriteBuffer[ 0 ] = 0x00; + + /* No more data to return. */ + xReturn = pdFALSE; + + /* Start over the next time this command is executed. */ + lParameterNumber = 0; + } + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ipconfigSUPPORT_OUTGOING_PINGS == 1 + + static BaseType_t prvPingCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) + { + char * pcParameter; + BaseType_t lParameterStringLength, xReturn; + uint32_t ulIPAddress, ulBytesToPing; + const uint32_t ulDefaultBytesToPing = 8UL; + char cBuffer[ 16 ]; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + /* Start with an empty string. */ + pcWriteBuffer[ 0 ] = 0x00; + + /* Obtain the number of bytes to ping. */ + pcParameter = ( char * ) FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 2, /* Return the second parameter. */ + &lParameterStringLength /* Store the parameter string length. */ + ); + + if( pcParameter == NULL ) + { + /* The number of bytes was not specified, so default it. */ + ulBytesToPing = ulDefaultBytesToPing; + } + else + { + ulBytesToPing = atol( pcParameter ); + } + + /* Obtain the IP address string. */ + pcParameter = ( char * ) FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 1, /* Return the first parameter. */ + &lParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcParameter ); + + /* Attempt to obtain the IP address. If the first character is not a + digit, assume the host name has been passed in. */ + if( ( *pcParameter >= '0' ) && ( *pcParameter <= '9' ) ) + { + ulIPAddress = FreeRTOS_inet_addr( pcParameter ); + } + else + { + /* Terminate the host name. */ + pcParameter[ lParameterStringLength ] = 0x00; + + /* Attempt to resolve host. */ + ulIPAddress = FreeRTOS_gethostbyname( pcParameter ); + } + + /* Convert IP address, which may have come from a DNS lookup, to string. */ + FreeRTOS_inet_ntoa( ulIPAddress, cBuffer ); + + if( ulIPAddress != 0 ) + { + xReturn = FreeRTOS_SendPingRequest( ulIPAddress, ( uint16_t ) ulBytesToPing, portMAX_DELAY ); + } + else + { + xReturn = pdFALSE; + } + + if( xReturn == pdFALSE ) + { + sprintf( pcWriteBuffer, "%s", "Could not send ping request\r\n" ); + } + else + { + sprintf( pcWriteBuffer, "Ping sent to %s with identifier %d\r\n", cBuffer, xReturn ); + } + + return pdFALSE; + } + /*-----------------------------------------------------------*/ + +#endif /* ipconfigSUPPORT_OUTGOING_PINGS */ + +#if configINCLUDE_DEMO_DEBUG_STATS != 0 + + static BaseType_t prvDisplayIPDebugStats( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) + { + static BaseType_t xIndex = -1; + extern xExampleDebugStatEntry_t xIPTraceValues[]; + BaseType_t xReturn; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + xIndex++; + + if( xIndex < xExampleDebugStatEntries() ) + { + sprintf( pcWriteBuffer, "%s %d\r\n", xIPTraceValues[ xIndex ].pucDescription, ( int ) xIPTraceValues[ xIndex ].ulData ); + xReturn = pdPASS; + } + else + { + /* Reset the index for the next time it is called. */ + xIndex = -1; + + /* Ensure nothing remains in the write buffer. */ + pcWriteBuffer[ 0 ] = 0x00; + xReturn = pdFALSE; + } + + return xReturn; + } + /*-----------------------------------------------------------*/ + +#endif /* configINCLUDE_DEMO_DEBUG_STATS */ + +static BaseType_t prvDisplayIPConfig( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +static BaseType_t xIndex = 0; +BaseType_t xReturn; +uint32_t ulAddress; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + switch( xIndex ) + { + case 0 : + FreeRTOS_GetAddressConfiguration( &ulAddress, NULL, NULL, NULL ); + sprintf( pcWriteBuffer, "\r\nIP address " ); + xReturn = pdTRUE; + xIndex++; + break; + + case 1 : + FreeRTOS_GetAddressConfiguration( NULL, &ulAddress, NULL, NULL ); + sprintf( pcWriteBuffer, "\r\nNet mask " ); + xReturn = pdTRUE; + xIndex++; + break; + + case 2 : + FreeRTOS_GetAddressConfiguration( NULL, NULL, &ulAddress, NULL ); + sprintf( pcWriteBuffer, "\r\nGateway address " ); + xReturn = pdTRUE; + xIndex++; + break; + + case 3 : + FreeRTOS_GetAddressConfiguration( NULL, NULL, NULL, &ulAddress ); + sprintf( pcWriteBuffer, "\r\nDNS server address " ); + xReturn = pdTRUE; + xIndex++; + break; + + default : + ulAddress = 0; + sprintf( pcWriteBuffer, "\r\n\r\n" ); + xReturn = pdFALSE; + xIndex = 0; + break; + } + + if( ulAddress != 0 ) + { + FreeRTOS_inet_ntoa( ulAddress, &( pcWriteBuffer[ strlen( pcWriteBuffer ) ] ) ); + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 + + static BaseType_t prvStartStopTraceCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) + { + const char *pcParameter; + BaseType_t lParameterStringLength; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + /* Obtain the parameter string. */ + pcParameter = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 1, /* Return the first parameter. */ + &lParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcParameter ); + + /* There are only two valid parameter values. */ + if( strncmp( pcParameter, "start", strlen( "start" ) ) == 0 ) + { + /* Start or restart the trace. */ + vTraceStop(); + vTraceClear(); + vTraceStart(); + + sprintf( pcWriteBuffer, "Trace recording (re)started.\r\n" ); + } + else if( strncmp( pcParameter, "stop", strlen( "stop" ) ) == 0 ) + { + /* End the trace, if one is running. */ + vTraceStop(); + sprintf( pcWriteBuffer, "Stopping trace recording.\r\n" ); + } + else + { + sprintf( pcWriteBuffer, "Valid parameters are 'start' and 'stop'.\r\n" ); + } + + /* There is no more data to return after this single string, so return + pdFALSE. */ + return pdFALSE; + } + +#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/CLICommands/UDPCommandInterpreter.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/CLICommands/UDPCommandInterpreter.h new file mode 100644 index 0000000..69dda29 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/CLICommands/UDPCommandInterpreter.h @@ -0,0 +1,33 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef UDP_COMMAND_INTERPRETER_H +#define UDP_COMMAND_INTERPRETER_H + +void vStartUDPCommandInterpreterTask( uint16_t usStackSize, uint32_t ulPort, UBaseType_t uxPriority ); + +#endif /* UDP_COMMAND_INTERPRETER_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/CLICommands/UDPCommandServer.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/CLICommands/UDPCommandServer.c new file mode 100644 index 0000000..eb0d078 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/CLICommands/UDPCommandServer.c @@ -0,0 +1,206 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Standard includes. */ +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* FreeRTOS+CLI includes. */ +#include "FreeRTOS_CLI.h" + +/* FreeRTOS+UDP includes. */ +#include "FreeRTOS_UDP_IP.h" +#include "FreeRTOS_Sockets.h" + +/* Demo app includes. */ +#include "UDPCommandInterpreter.h" + +/* Dimensions the buffer into which input characters are placed. */ +#define cmdMAX_INPUT_SIZE 60 + +/* Dimensions the buffer into which string outputs can be placed. */ +#define cmdMAX_OUTPUT_SIZE 1250 + +/* Dimensions the buffer passed to the recvfrom() call. */ +#define cmdSOCKET_INPUT_BUFFER_SIZE 60 + +/* + * The task that runs FreeRTOS+CLI. + */ +void vUDPCommandInterpreterTask( void *pvParameters ); + +/* + * Open and configure the UDP socket. + */ +static xSocket_t prvOpenUDPServerSocket( uint16_t usPort ); + +/*-----------------------------------------------------------*/ + +void vStartUDPCommandInterpreterTask( uint16_t usStackSize, uint32_t ulPort, UBaseType_t uxPriority ) +{ + xTaskCreate( vUDPCommandInterpreterTask, "CLI", usStackSize, ( void * ) ulPort, uxPriority, NULL ); +} +/*-----------------------------------------------------------*/ + +/* + * Task that provides the input and output for the FreeRTOS+CLI command + * interpreter. In this case a UDP port is used. See the URL in the comments + * within main.c for the location of the online documentation. + */ +void vUDPCommandInterpreterTask( void *pvParameters ) +{ +long lBytes, lByte; +signed char cInChar, cInputIndex = 0; +static char cInputString[ cmdMAX_INPUT_SIZE ], cOutputString[ cmdMAX_OUTPUT_SIZE ], cLocalBuffer[ cmdSOCKET_INPUT_BUFFER_SIZE ]; +BaseType_t xMoreDataToFollow; +struct freertos_sockaddr xClient; +socklen_t xClientAddressLength = 0; /* This is required as a parameter to maintain the sendto() Berkeley sockets API - but it is not actually used so can take any value. */ +xSocket_t xSocket; + + /* Just to prevent compiler warnings. */ + ( void ) pvParameters; + + /* Attempt to open the socket. The port number is passed in the task + parameter. The strange casting is to remove compiler warnings on 32-bit + machines. */ + xSocket = prvOpenUDPServerSocket( ( uint16_t ) ( ( uint32_t ) pvParameters ) & 0xffffUL ); + + if( xSocket != FREERTOS_INVALID_SOCKET ) + { + for( ;; ) + { + /* Wait for incoming data on the opened socket. */ + lBytes = FreeRTOS_recvfrom( xSocket, ( void * ) cLocalBuffer, sizeof( cLocalBuffer ), 0, &xClient, &xClientAddressLength ); + + if( lBytes != FREERTOS_SOCKET_ERROR ) + { + /* Process each received byte in turn. */ + lByte = 0; + while( lByte < lBytes ) + { + /* The next character in the input buffer. */ + cInChar = cLocalBuffer[ lByte ]; + lByte++; + + /* Newline characters are taken as the end of the command + string. */ + if( cInChar == '\n' ) + { + /* Process the input string received prior to the + newline. */ + do + { + /* Pass the string to FreeRTOS+CLI. */ + xMoreDataToFollow = FreeRTOS_CLIProcessCommand( cInputString, cOutputString, cmdMAX_OUTPUT_SIZE ); + + /* Send the output generated by the command's + implementation. */ + FreeRTOS_sendto( xSocket, cOutputString, strlen( cOutputString ), 0, &xClient, xClientAddressLength ); + + } while( xMoreDataToFollow != pdFALSE ); /* Until the command does not generate any more output. */ + + /* All the strings generated by the command processing + have been sent. Clear the input string ready to receive + the next command. */ + cInputIndex = 0; + memset( cInputString, 0x00, cmdMAX_INPUT_SIZE ); + + /* Transmit a spacer, just to make the command console + easier to read. */ + FreeRTOS_sendto( xSocket, "\r\n", strlen( "\r\n" ), 0, &xClient, xClientAddressLength ); + } + else + { + if( cInChar == '\r' ) + { + /* Ignore the character. Newlines are used to + detect the end of the input string. */ + } + else if( cInChar == '\b' ) + { + /* Backspace was pressed. Erase the last character + in the string - if any. */ + if( cInputIndex > 0 ) + { + cInputIndex--; + cInputString[ cInputIndex ] = '\0'; + } + } + else + { + /* A character was entered. Add it to the string + entered so far. When a \n is entered the complete + string will be passed to the command interpreter. */ + if( cInputIndex < cmdMAX_INPUT_SIZE ) + { + cInputString[ cInputIndex ] = cInChar; + cInputIndex++; + } + } + } + } + } + } + } + else + { + /* The socket could not be opened. */ + vTaskDelete( NULL ); + } +} +/*-----------------------------------------------------------*/ + +static xSocket_t prvOpenUDPServerSocket( uint16_t usPort ) +{ +struct freertos_sockaddr xServer; +xSocket_t xSocket = FREERTOS_INVALID_SOCKET; + + xSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP ); + if( xSocket != FREERTOS_INVALID_SOCKET) + { + /* Zero out the server structure. */ + memset( ( void * ) &xServer, 0x00, sizeof( xServer ) ); + + /* Set family and port. */ + xServer.sin_port = FreeRTOS_htons( usPort ); + + /* Bind the address to the socket. */ + if( FreeRTOS_bind( xSocket, &xServer, sizeof( xServer ) ) == -1 ) + { + FreeRTOS_closesocket( xSocket ); + xSocket = FREERTOS_INVALID_SOCKET; + } + } + + return xSocket; +} + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/EchoClients/TwoEchoClients.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/EchoClients/TwoEchoClients.c new file mode 100644 index 0000000..cc18728 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/EchoClients/TwoEchoClients.c @@ -0,0 +1,359 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +/****************************************************************************** + * + * See the following web page for essential TwoEchoClient.c usage and + * configuration details: + * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Common_Echo_Clients.shtml + * + ******************************************************************************/ + + +/* Standard includes. */ +#include +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* FreeRTOS+UDP includes. */ +#include "FreeRTOS_UDP_IP.h" +#include "FreeRTOS_Sockets.h" + +/* Small delay used between attempts to obtain a zero copy buffer. */ +#define echoTINY_DELAY ( ( TickType_t ) 2 ) + +/* The echo tasks create a socket, send out a number of echo requests +(listening for each echo reply), then close the socket again before +starting over. This delay is used between each iteration to ensure the +network does not get too congested. */ +#define echoLOOP_DELAY ( ( TickType_t ) 250 / portTICK_RATE_MS ) + +#if ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS == 1 + /* When the trace recorder code is included user events are generated to + mark the sending and receiving of the echoed data (only in the zero copy + task. */ + #define echoMARK_SEND_IN_TRACE_BUFFER( x ) vTraceUserEvent( x ) + traceLabel xZeroCopySendEvent, xZeroCopyReceiveEvent; + +#else + /* When the trace recorder code is not included just #define away the call + to post the user event. */ + #define echoMARK_SEND_IN_TRACE_BUFFER( x ) + #define xZeroCopySendEvent 0 + #define xZeroCopyReceiveEvent 0 +#endif + +/* The echo server is assumed to be on port 7, which is the standard echo +protocol port. */ +#define echoECHO_PORT ( 7 ) + +/* + * Uses a socket to send data to, then receive data from, the standard echo + * port number 7. prvEchoClientTask() uses the standard interface. + * prvZeroCopyEchoClientTask() uses the zero copy interface. + */ +static void prvEchoClientTask( void *pvParameters ); +static void prvZeroCopyEchoClientTask( void *pvParameters ); + +/* The receive timeout is set shorter when the windows simulator is used +because simulated time is slower than real time. */ +#ifdef _WINDOWS_ + const TickType_t xReceiveTimeOut = 50 / portTICK_RATE_MS; +#else + const TickType_t xReceiveTimeOut = 500 / portTICK_RATE_MS; +#endif + +/*-----------------------------------------------------------*/ + +void vStartEchoClientTasks( uint16_t usTaskStackSize, UBaseType_t uxTaskPriority ) +{ + /* Create the echo client task that does not use the zero copy interface. */ + xTaskCreate( prvEchoClientTask, /* The function that implements the task. */ + "Echo0", /* Just a text name for the task to aid debugging. */ + usTaskStackSize, /* The stack size is defined in FreeRTOSIPConfig.h. */ + NULL, /* The task parameter, not used in this case. */ + uxTaskPriority, /* The priority assigned to the task is defined in FreeRTOSConfig.h. */ + NULL ); /* The task handle is not used. */ + + /* Create the echo client task that does use the zero copy interface. */ + xTaskCreate( prvZeroCopyEchoClientTask, /* The function that implements the task. */ + "Echo1", /* Just a text name for the task to aid debugging. */ + usTaskStackSize, /* The stack size is defined in FreeRTOSIPConfig.h. */ + NULL, /* The task parameter, not used in this case. */ + uxTaskPriority, /* The priority assigned to the task is defined in FreeRTOSConfig.h. */ + NULL ); /* The task handle is not used. */ +} +/*-----------------------------------------------------------*/ + +static void prvEchoClientTask( void *pvParameters ) +{ +xSocket_t xSocket; +struct freertos_sockaddr xEchoServerAddress; +char cTxString[ 25 ], cRxString[ 25 ]; /* Make sure the stack is large enough to hold these. Turn on stack overflow checking during debug to be sure. */ +int32_t lLoopCount = 0UL; +const int32_t lMaxLoopCount = 50; +volatile uint32_t ulRxCount = 0UL, ulTxCount = 0UL; +uint32_t xAddressLength = sizeof( xEchoServerAddress ); + + /* Remove compiler warning about unused parameters. */ + ( void ) pvParameters; + + /* Echo requests are sent to the echo server. The address of the echo + server is configured by the constants configECHO_SERVER_ADDR0 to + configECHO_SERVER_ADDR3 in FreeRTOSConfig.h. */ + xEchoServerAddress.sin_port = FreeRTOS_htons( echoECHO_PORT ); + xEchoServerAddress.sin_addr = FreeRTOS_inet_addr_quick( configECHO_SERVER_ADDR0, + configECHO_SERVER_ADDR1, + configECHO_SERVER_ADDR2, + configECHO_SERVER_ADDR3 ); + + for( ;; ) + { + /* Create a socket. */ + xSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP ); + configASSERT( xSocket != FREERTOS_INVALID_SOCKET ); + + /* Set a time out so a missing reply does not cause the task to block + indefinitely. */ + FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_RCVTIMEO, &xReceiveTimeOut, sizeof( xReceiveTimeOut ) ); + + /* Send a number of echo requests. */ + for( lLoopCount = 0; lLoopCount < lMaxLoopCount; lLoopCount++ ) + { + /* Create the string that is sent to the echo server. */ + sprintf( cTxString, "Message number %u\r\n", ( unsigned int ) ulTxCount ); + + /* Send the string to the socket. ulFlags is set to 0, so the zero + copy interface is not used. That means the data from cTxString is + copied into a network buffer inside FreeRTOS_sendto(), and cTxString + can be reused as soon as FreeRTOS_sendto() has returned. 1 is added + to ensure the NULL string terminator is sent as part of the message. */ + FreeRTOS_sendto( xSocket, /* The socket being sent to. */ + ( void * ) cTxString, /* The data being sent. */ + strlen( cTxString ) + 1,/* The length of the data being sent. */ + 0, /* ulFlags with the FREERTOS_ZERO_COPY bit clear. */ + &xEchoServerAddress, /* The destination address. */ + sizeof( xEchoServerAddress ) ); + + /* Keep a count of how many echo requests have been transmitted so + it can be compared to the number of echo replies received. It would + be expected to loose at least one to an ARP message the first time + the connection is created. */ + ulTxCount++; + + /* Receive data echoed back to the socket. ulFlags is zero, so the + zero copy option is not being used and the received data will be + copied into the buffer pointed to by cRxString. xAddressLength is + not actually used (at the time of writing this comment, anyway) by + FreeRTOS_recvfrom(), but is set appropriately in case future + versions do use it. */ + memset( ( void * ) cRxString, 0x00, sizeof( cRxString ) ); + FreeRTOS_recvfrom( xSocket, /* The socket being received from. */ + cRxString, /* The buffer into which the received data will be written. */ + sizeof( cRxString ), /* The size of the buffer provided to receive the data. */ + 0, /* ulFlags with the FREERTOS_ZERO_COPY bit clear. */ + &xEchoServerAddress, /* The address from where the data was sent (the source address). */ + &xAddressLength ); + + /* Compare the transmitted string to the received string. */ + if( strcmp( cRxString, cTxString ) == 0 ) + { + /* The echo reply was received without error. */ + ulRxCount++; + } + }; + + /* Pause for a short while to ensure the network is not too + congested. */ + vTaskDelay( echoLOOP_DELAY ); + + /* Close this socket before looping back to create another. */ + FreeRTOS_closesocket( xSocket ); + } +} +/*-----------------------------------------------------------*/ + +static void prvZeroCopyEchoClientTask( void *pvParameters ) +{ +xSocket_t xSocket; +struct freertos_sockaddr xEchoServerAddress; +static char cTxString[ 40 ]; +int32_t lLoopCount = 0UL; +volatile uint32_t ulRxCount = 0UL, ulTxCount = 0UL; +uint32_t xAddressLength = sizeof( xEchoServerAddress ); +int32_t lReturned; +uint8_t *pucUDPPayloadBuffer; + +const int32_t lMaxLoopCount = 50; +const char * const pcStringToSend = "Zero copy message number"; +/* The buffer is large enough to hold the string, a number, and the string terminator. */ +const size_t xBufferLength = strlen( pcStringToSend ) + 15; + + #if ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS == 1 + { + /* When the trace recorder code is included user events are generated to + mark the sending and receiving of the echoed data (only in the zero copy + task). */ + xZeroCopySendEvent = xTraceOpenLabel( "ZeroCopyTx" ); + xZeroCopyReceiveEvent = xTraceOpenLabel( "ZeroCopyRx" ); + } + #endif /* ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS */ + + /* Remove compiler warning about unused parameters. */ + ( void ) pvParameters; + + /* Delay for a little while to ensure the task is out of synch with the + other echo task implemented above. */ + vTaskDelay( echoLOOP_DELAY >> 1 ); + + /* Echo requests are sent to the echo server. The address of the echo + server is configured by the constants configECHO_SERVER_ADDR0 to + configECHO_SERVER_ADDR3 in FreeRTOSConfig.h. */ + xEchoServerAddress.sin_port = FreeRTOS_htons( echoECHO_PORT ); + xEchoServerAddress.sin_addr = FreeRTOS_inet_addr_quick( configECHO_SERVER_ADDR0, + configECHO_SERVER_ADDR1, + configECHO_SERVER_ADDR2, + configECHO_SERVER_ADDR3 ); + + for( ;; ) + { + /* Create a socket. */ + xSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP ); + configASSERT( xSocket != FREERTOS_INVALID_SOCKET ); + + /* Set a time out so a missing reply does not cause the task to block + indefinitely. */ + FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_RCVTIMEO, &xReceiveTimeOut, sizeof( xReceiveTimeOut ) ); + + /* Send a number of echo requests. */ + for( lLoopCount = 0; lLoopCount < lMaxLoopCount; lLoopCount++ ) + { + /* This task is going to send using the zero copy interface. The + data being sent is therefore written directly into a buffer that is + passed by reference into the FreeRTOS_sendto() function. First + obtain a buffer of adequate size from the IP stack. Although a max + delay is used, the actual delay will be capped to + ipconfigMAX_SEND_BLOCK_TIME_TICKS, hence the test to ensure a buffer + was actually obtained. */ + pucUDPPayloadBuffer = ( uint8_t * ) FreeRTOS_GetUDPPayloadBuffer( xBufferLength, portMAX_DELAY ); + + if( pucUDPPayloadBuffer != NULL ) + { + /* A buffer was successfully obtained. Create the string that is + sent to the echo server. Note the string is written directly + into the buffer obtained from the IP stack. */ + sprintf( ( char * ) pucUDPPayloadBuffer, "%s %u\r\n", "Zero copy message number", ( unsigned int ) ulTxCount ); + + /* Also copy the string into a local buffer so it can be compared + with the string that is later received back from the echo server. */ + strcpy( cTxString, ( char * ) pucUDPPayloadBuffer ); + + /* Pass the buffer into the send function. ulFlags has the + FREERTOS_ZERO_COPY bit set so the IP stack will take control of + the buffer, rather than copy data out of the buffer. */ + echoMARK_SEND_IN_TRACE_BUFFER( xZeroCopySendEvent ); + lReturned = FreeRTOS_sendto( xSocket, /* The socket being sent to. */ + ( void * ) pucUDPPayloadBuffer, /* The buffer being passed into the IP stack. */ + strlen( cTxString ) + 1, /* The length of the data being sent. Plus 1 to ensure the null terminator is part of the data. */ + FREERTOS_ZERO_COPY, /* ulFlags with the zero copy bit is set. */ + &xEchoServerAddress, /* Where the data is being sent. */ + sizeof( xEchoServerAddress ) ); + + if( lReturned == 0 ) + { + /* The send operation failed, so this task is still + responsible for the buffer obtained from the IP stack. To + ensure the buffer is not lost it must either be used again, + or, as in this case, returned to the IP stack using + FreeRTOS_ReleaseUDPPayloadBuffer(). pucUDPPayloadBuffer can + be safely re-used to receive from the socket below once the + buffer has been returned to the stack. */ + FreeRTOS_ReleaseUDPPayloadBuffer( ( void * ) pucUDPPayloadBuffer ); + } + else + { + /* The send was successful so the IP stack is now managing + the buffer pointed to by pucUDPPayloadBuffer, and the IP + stack will return the buffer once it has been sent. + pucUDPPayloadBuffer can be safely re-used to receive from + the socket below. */ + } + + /* Keep a count of how many echo requests have been transmitted + so it can be compared to the number of echo replies received. + It would be expected to loose at least one to an ARP message the + first time the connection is created. */ + ulTxCount++; + + /* Receive data on the socket. ulFlags has the zero copy bit set + (FREERTOS_ZERO_COPY) indicating to the stack that a reference to + the received data should be passed out to this task using the + second parameter to the FreeRTOS_recvfrom() call. When this is + done the IP stack is no longer responsible for releasing the + buffer, and the task *must* return the buffer to the stack when + it is no longer needed. By default the receive block time is + portMAX_DELAY. */ + echoMARK_SEND_IN_TRACE_BUFFER( xZeroCopyReceiveEvent ); + lReturned = FreeRTOS_recvfrom( xSocket, /* The socket to receive from. */ + ( void * ) &pucUDPPayloadBuffer, /* pucUDPPayloadBuffer will be set to point to the buffer that already contains the received data. */ + 0, /* Ignored because the zero copy interface is being used. */ + FREERTOS_ZERO_COPY, /* ulFlags with the FREERTOS_ZERO_COPY bit set. */ + &xEchoServerAddress, /* The address from which the data was sent. */ + &xAddressLength ); + + if( lReturned > 0 ) + { + /* Compare the string sent to the echo server with the string + received back from the echo server. */ + if( strcmp( ( char * ) pucUDPPayloadBuffer, cTxString ) == 0 ) + { + /* The strings matched. */ + ulRxCount++; + } + + /* The buffer that contains the data passed out of the stack + *must* be returned to the stack. */ + FreeRTOS_ReleaseUDPPayloadBuffer( pucUDPPayloadBuffer ); + } + } + } + + /* Pause for a short while to ensure the network is not too + congested. */ + vTaskDelay( echoLOOP_DELAY ); + + /* Close this socket before looping back to create another. */ + FreeRTOS_closesocket( xSocket ); + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/EchoClients/TwoEchoClients.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/EchoClients/TwoEchoClients.h new file mode 100644 index 0000000..3f1f6ef --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/EchoClients/TwoEchoClients.h @@ -0,0 +1,38 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef TWO_ECHO_CLIENTS_H +#define TWO_ECHO_CLIENTS_H + +/* + * Create the two UDP echo client tasks. One task uses the standard interface + * to send to and receive from an echo server. The other task uses the zero + * copy interface to send to and receive from an echo server. + */ +void vStartEchoClientTasks( uint16_t usTaskStackSize, UBaseType_t uxTaskPriority ); + +#endif /* TWO_ECHO_CLIENTS_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/TraceMacros/Example1/DemoIPTrace.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/TraceMacros/Example1/DemoIPTrace.c new file mode 100644 index 0000000..b241fd3 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/TraceMacros/Example1/DemoIPTrace.c @@ -0,0 +1,150 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * This file, along with DemoIPTrace.h, provides a basic example use of the + * FreeRTOS+UDP trace macros. The statistics gathered here can be viewed in + * the command line interface. + * See http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/UDP_IP_Trace.shtml + */ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* FreeRTOS+UDP includes. */ +#include "FreeRTOS_UDP_IP.h" +#include "DemoIPTrace.h" + +/* It is possible to remove the trace macros using the +configINCLUDE_DEMO_DEBUG_STATS setting in FreeRTOSIPConfig.h. */ +#if configINCLUDE_DEMO_DEBUG_STATS == 1 + +/* + * Each row in the xIPTraceValues[] table contains a pointer to a function that + * updates the value for that row. Rows that latch the lowest value point to + * this function (for example, this function can be used to latch the lowest + * number of network buffers that were available during the execution of the + * stack). + */ +static void prvStoreLowest( uint32_t *pulCurrentValue, uint32_t ulCount ); + +/* + * Each row in the xIPTraceValues[] table contains a pointer to a function that + * updates the value for that row. Rows that simply increment an event count + * point to this function. + */ +static void prvIncrementEventCount( uint32_t *pulCurrentValue, uint32_t ulCount ); + + +xExampleDebugStatEntry_t xIPTraceValues[] = +{ + /* Comment out array entries to remove individual trace items. */ + + { iptraceID_NETWORK_INTERFACE_RECEIVE, ( const uint8_t * const ) "Packets received by the network interface", prvIncrementEventCount, 0 }, + { iptraceID_NETWORK_INTERFACE_TRANSMIT, ( const uint8_t * const ) "Count of transmitted packets", prvIncrementEventCount, 0 }, + { iptraceID_PACKET_DROPPED_TO_GENERATE_ARP, ( const uint8_t * const ) "Count of packets dropped to generate ARP", prvIncrementEventCount, 0 }, + { iptraceID_NETWORK_BUFFER_OBTAINED, ( const uint8_t * const ) "Lowest ever available network buffers", prvStoreLowest, 0xffffUL }, + { iptraceID_NETWORK_EVENT_RECEIVED, ( const uint8_t * const ) "Lowest ever free space in network event queue", prvStoreLowest, 0xffffUL }, + { iptraceID_FAILED_TO_OBTAIN_NETWORK_BUFFER, ( const uint8_t * const ) "Count of failed attempts to obtain a network buffer",prvIncrementEventCount, 0 }, + { iptraceID_ARP_TABLE_ENTRY_EXPIRED, ( const uint8_t * const ) "Count of expired ARP entries", prvIncrementEventCount, 0 }, + { iptraceID_FAILED_TO_CREATE_SOCKET, ( const uint8_t * const ) "Count of failures to create a socket", prvIncrementEventCount, 0 }, + { iptraceID_RECVFROM_DISCARDING_BYTES, ( const uint8_t * const ) "Count of times recvfrom() has discarding bytes", prvIncrementEventCount, 0 }, + { iptraceID_ETHERNET_RX_EVENT_LOST, ( const uint8_t * const ) "Count of lost Ethenret Rx events (event queue full?)",prvIncrementEventCount, 0 }, + { iptraceID_STACK_TX_EVENT_LOST, ( const uint8_t * const ) "Count of lost IP stack events (event queue full?)", prvIncrementEventCount, 0 }, + { ipconfigID_BIND_FAILED, ( const uint8_t * const ) "Count of failed calls to bind()", prvIncrementEventCount, 0 }, + { iptraceID_RECVFROM_TIMEOUT, ( const uint8_t * const ) "Count of receive timeouts", prvIncrementEventCount, 0 }, + { iptraceID_SENDTO_DATA_TOO_LONG, ( const uint8_t * const ) "Count of failed sends due to oversized payload", prvIncrementEventCount, 0 }, + { iptraceID_SENDTO_SOCKET_NOT_BOUND, ( const uint8_t * const ) "Count of failed sends due to unbound socket", prvIncrementEventCount, 0 }, + { iptraceID_NO_BUFFER_FOR_SENDTO, ( const uint8_t * const ) "Count of failed transmits due to timeout", prvIncrementEventCount, 0 }, + { iptraceID_WAIT_FOR_TX_DMA_DESCRIPTOR, ( const uint8_t * const ) "Number of times task had to wait to obtain a DMA Tx descriptor", prvIncrementEventCount, 0 }, + { iptraceID_FAILED_TO_NOTIFY_SELECT_GROUP, ( const uint8_t * const ) "Failed to notify select group", prvIncrementEventCount, 0 } +}; + +/*-----------------------------------------------------------*/ + +BaseType_t xExampleDebugStatEntries( void ) +{ + /* Return the number of entries in the xIPTraceValues[] table. */ + return ( BaseType_t ) ( sizeof( xIPTraceValues ) / sizeof( xExampleDebugStatEntry_t ) ); +} +/*-----------------------------------------------------------*/ + +void vExampleDebugStatUpdate( uint8_t ucIdentifier, uint32_t ulValue ) +{ +BaseType_t xIndex; +const BaseType_t xEntries = sizeof( xIPTraceValues ) / sizeof( xExampleDebugStatEntry_t ); + + /* Update an entry in the xIPTraceValues[] table. Each row in the table + includes a pointer to a function that performs the actual update. This + function just executes the update function from that table row. */ + for( xIndex = 0; xIndex < xEntries; xIndex++ ) + { + if( xIPTraceValues[ xIndex ].ucIdentifier == ucIdentifier ) + { + xIPTraceValues[ xIndex ].vPerformAction( &( xIPTraceValues[ xIndex ].ulData ), ulValue ); + break; + } + } + + configASSERT( xIndex != xEntries ); +} +/*-----------------------------------------------------------*/ + +static void prvIncrementEventCount( uint32_t *pulCurrentValue, uint32_t ulCount ) +{ + /* Each row in the xIPTraceValues[] table contains a pointer to a function + that updates the value for that row. Rows that simply increment an event + count point to this function. */ + ( void ) ulCount; + ( *pulCurrentValue )++; +} +/*-----------------------------------------------------------*/ + +static void prvStoreLowest( uint32_t *pulCurrentValue, uint32_t ulCount ) +{ + /* Each row in the xIPTraceValues[] table contains a pointer to a function + that updates the value for that row. Rows that latch the lowest value + point to this function (for example, this function can be used to latch + the lowest number of network buffers that were available during the + execution of the stack). */ + if( ulCount < *pulCurrentValue ) + { + *pulCurrentValue = ulCount; + } +} +/*-----------------------------------------------------------*/ + + +#endif /* configINCLUDE_DEMO_DEBUG_STATS == 1 */ + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/TraceMacros/Example1/DemoIPTrace.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/TraceMacros/Example1/DemoIPTrace.h new file mode 100644 index 0000000..1a73f1c --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/TraceMacros/Example1/DemoIPTrace.h @@ -0,0 +1,121 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * This file, along with DemoIPTrace.h, provides a basic example use of the + * FreeRTOS+UDP trace macros. The statistics gathered here can be viewed in + * the command line interface. + * See http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/UDP_IP_Trace.shtml + */ + +#ifndef DEMO_IP_TRACE_MACROS_H +#define DEMO_IP_TRACE_MACROS_H + +typedef void ( *vTraceAction_t )( uint32_t *, uint32_t ); + +/* Type that defines each statistic being gathered. */ +typedef struct ExampleDebugStatEntry +{ + uint8_t ucIdentifier; /* Unique identifier for statistic. */ + const uint8_t * const pucDescription; /* Text description for the statistic. */ + vTraceAction_t vPerformAction; /* Action to perform when the statistic is updated (increment counter, store minimum value, store maximum value, etc. */ + uint32_t ulData; /* The meaning of this data is dependent on the trace macro ID. */ +} xExampleDebugStatEntry_t; + +/* Unique identifiers used to locate the entry for each trace macro in the +xIPTraceValues[] table defined in DemoIPTrace.c. */ +#define iptraceID_NETWORK_INTERFACE_RECEIVE 0 +#define iptraceID_NETWORK_INTERFACE_TRANSMIT 1 +#define iptraceID_PACKET_DROPPED_TO_GENERATE_ARP 2 +/* Do not change IDs above this line as the ID is shared with a FreeRTOS+Nabto +demo. */ +#define iptraceID_NETWORK_BUFFER_OBTAINED 3 +#define iptraceID_NETWORK_BUFFER_OBTAINED_FROM_ISR 4 +#define iptraceID_NETWORK_EVENT_RECEIVED 5 +#define iptraceID_FAILED_TO_OBTAIN_NETWORK_BUFFER 6 +#define iptraceID_ARP_TABLE_ENTRY_EXPIRED 7 +#define iptraceID_FAILED_TO_CREATE_SOCKET 8 +#define iptraceID_RECVFROM_DISCARDING_BYTES 9 +#define iptraceID_ETHERNET_RX_EVENT_LOST 10 +#define iptraceID_STACK_TX_EVENT_LOST 11 +#define ipconfigID_BIND_FAILED 12 +#define iptraceID_RECVFROM_TIMEOUT 13 +#define iptraceID_SENDTO_DATA_TOO_LONG 14 +#define iptraceID_SENDTO_SOCKET_NOT_BOUND 15 +#define iptraceID_NO_BUFFER_FOR_SENDTO 16 +#define iptraceID_WAIT_FOR_TX_DMA_DESCRIPTOR 17 +#define iptraceID_FAILED_TO_NOTIFY_SELECT_GROUP 18 + +/* It is possible to remove the trace macros using the +configINCLUDE_DEMO_DEBUG_STATS setting in FreeRTOSIPConfig.h. */ +#if configINCLUDE_DEMO_DEBUG_STATS == 1 + + /* The trace macro definitions themselves. Any trace macros left undefined + will default to be empty macros. */ + #define iptraceNETWORK_BUFFER_OBTAINED( pxBufferAddress ) vExampleDebugStatUpdate( iptraceID_NETWORK_BUFFER_OBTAINED, uxQueueMessagesWaiting( ( xQueueHandle ) xNetworkBufferSemaphore ) ) + #define iptraceNETWORK_BUFFER_OBTAINED_FROM_ISR( pxBufferAddress ) vExampleDebugStatUpdate( iptraceID_NETWORK_BUFFER_OBTAINED, uxQueueMessagesWaiting( ( xQueueHandle ) xNetworkBufferSemaphore ) ) + + #define iptraceNETWORK_EVENT_RECEIVED( eEvent ) { \ + uint16_t usSpace; \ + usSpace = ( uint16_t ) uxQueueMessagesWaiting( xNetworkEventQueue ); \ + /* Minus one as an event was removed before the space was queried. */ \ + usSpace = ( ipconfigEVENT_QUEUE_LENGTH - usSpace ) - 1; \ + vExampleDebugStatUpdate( iptraceID_NETWORK_EVENT_RECEIVED, usSpace ); \ + } + + #define iptraceFAILED_TO_OBTAIN_NETWORK_BUFFER() vExampleDebugStatUpdate( iptraceID_FAILED_TO_OBTAIN_NETWORK_BUFFER, 0 ) + #define iptraceARP_TABLE_ENTRY_EXPIRED( ulIPAddress ) vExampleDebugStatUpdate( iptraceID_ARP_TABLE_ENTRY_EXPIRED, 0 ) + #define iptracePACKET_DROPPED_TO_GENERATE_ARP( ulIPAddress ) vExampleDebugStatUpdate( iptraceID_PACKET_DROPPED_TO_GENERATE_ARP, 0 ) + #define iptraceFAILED_TO_CREATE_SOCKET() vExampleDebugStatUpdate( iptraceID_FAILED_TO_CREATE_SOCKET, 0 ) + #define iptraceRECVFROM_DISCARDING_BYTES( xNumberOfBytesDiscarded ) vExampleDebugStatUpdate( iptraceID_RECVFROM_DISCARDING_BYTES, 0 ) + #define iptraceETHERNET_RX_EVENT_LOST() vExampleDebugStatUpdate( iptraceID_ETHERNET_RX_EVENT_LOST, 0 ) + #define iptraceSTACK_TX_EVENT_LOST( xEvent ) vExampleDebugStatUpdate( iptraceID_STACK_TX_EVENT_LOST, 0 ) + #define iptraceBIND_FAILED( xSocket, usPort ) vExampleDebugStatUpdate( ipconfigID_BIND_FAILED, 0 ) + #define iptraceNETWORK_INTERFACE_TRANSMIT() vExampleDebugStatUpdate( iptraceID_NETWORK_INTERFACE_TRANSMIT, 0 ) + #define iptraceRECVFROM_TIMEOUT() vExampleDebugStatUpdate( iptraceID_RECVFROM_TIMEOUT, 0 ) + #define iptraceSENDTO_DATA_TOO_LONG() vExampleDebugStatUpdate( iptraceID_SENDTO_DATA_TOO_LONG, 0 ) + #define iptraceSENDTO_SOCKET_NOT_BOUND() vExampleDebugStatUpdate( iptraceID_SENDTO_SOCKET_NOT_BOUND, 0 ) + #define iptraceNO_BUFFER_FOR_SENDTO() vExampleDebugStatUpdate( iptraceID_NO_BUFFER_FOR_SENDTO, 0 ) + #define iptraceWAITING_FOR_TX_DMA_DESCRIPTOR() vExampleDebugStatUpdate( iptraceID_WAIT_FOR_TX_DMA_DESCRIPTOR, 0 ) + #define iptraceFAILED_TO_NOTIFY_SELECT_GROUP( xSocket ) vExampleDebugStatUpdate( iptraceID_FAILED_TO_NOTIFY_SELECT_GROUP, 0 ) + #define iptraceNETWORK_INTERFACE_RECEIVE() vExampleDebugStatUpdate( iptraceID_NETWORK_INTERFACE_RECEIVE, 0 ) + + /* + * The function that updates a line in the xIPTraceValues table. + */ + void vExampleDebugStatUpdate( uint8_t ucIdentifier, uint32_t ulValue ); + + /* + * Returns the number of entries in the xIPTraceValues table. + */ + BaseType_t xExampleDebugStatEntries( void ); + +#endif /* configINCLUDE_DEMO_DEBUG_STATS == 1 */ + + +#endif /* DEMO_IP_TRACE_MACROS_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/CLI-commands.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/CLI-commands.c new file mode 100644 index 0000000..5f4fa3d --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/CLI-commands.c @@ -0,0 +1,378 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* FreeRTOS+CLI includes. */ +#include "FreeRTOS_CLI.h" + +/* + * Writes trace data to a disk file when the trace recording is stopped. + * This function will simply overwrite any trace files that already exist. + */ +static void prvSaveTraceFile( void ); + +/* + * Defines a command that returns a table showing the state of each task at the + * time the command is called. + */ +static BaseType_t prvTaskStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Defines a command that returns a table showing how much time each task has + * spent in the Running state. + */ +static BaseType_t prvRunTimeStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Defines a command that expects exactly three parameters. Each of the three + * parameter are echoed back one at a time. + */ +static BaseType_t prvThreeParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Defines a command that can take a variable number of parameters. Each + * parameter is echoes back one at a time. + */ +static BaseType_t prvParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Defines a command that starts/stops events being recorded for offline viewing + * in FreeRTOS+Trace. + */ +static BaseType_t prvStartStopTraceCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* Structure that defines the "run-time-stats" command line command. */ +static const CLI_Command_Definition_t xRunTimeStats = +{ + "run-time-stats", /* The command string to type. */ + "\r\nrun-time-stats:\r\n Displays a table showing how much processing time each FreeRTOS task has used\r\n\r\n", + prvRunTimeStatsCommand, /* The function to run. */ + 0 /* No parameters are expected. */ +}; + +/* Structure that defines the "task-stats" command line command. */ +static const CLI_Command_Definition_t xTaskStats = +{ + "task-stats", /* The command string to type. */ + "\r\ntask-stats:\r\n Displays a table showing the state of each FreeRTOS task\r\n\r\n", + prvTaskStatsCommand, /* The function to run. */ + 0 /* No parameters are expected. */ +}; + +/* Structure that defines the "echo_3_parameters" command line command. This +takes exactly three parameters that the command simply echos back one at a +time. */ +static const CLI_Command_Definition_t xThreeParameterEcho = +{ + "echo_3_parameters", + "\r\necho_3_parameters :\r\n Expects three parameters, echos each in turn\r\n\r\n", + prvThreeParameterEchoCommand, /* The function to run. */ + 3 /* Three parameters are expected, which can take any value. */ +}; + +/* Structure that defines the "echo_parameters" command line command. This +takes a variable number of parameters that the command simply echos back one at +a time. */ +static const CLI_Command_Definition_t xParameterEcho = +{ + "echo_parameters", + "\r\necho_parameters <...>:\r\n Take variable number of parameters, echos each in turn\r\n\r\n", + prvParameterEchoCommand, /* The function to run. */ + -1 /* The user can enter any number of commands. */ +}; + +/* Structure that defines the "trace" command line command. This takes a single +parameter, which can be either "start" or "stop". */ +static const CLI_Command_Definition_t xStartTrace = +{ + "trace", + "\r\ntrace [start | stop]:\r\n Starts or stops a trace recording for viewing in FreeRTOS+Trace\r\n\r\n", + prvStartStopTraceCommand, /* The function to run. */ + 1 /* One parameter is expected. Valid values are "start" and "stop". */ +}; + +/*-----------------------------------------------------------*/ + +void vRegisterCLICommands( void ) +{ + /* Register all the command line commands defined immediately above. */ + FreeRTOS_CLIRegisterCommand( &xTaskStats ); + FreeRTOS_CLIRegisterCommand( &xRunTimeStats ); + FreeRTOS_CLIRegisterCommand( &xThreeParameterEcho ); + FreeRTOS_CLIRegisterCommand( &xParameterEcho ); + FreeRTOS_CLIRegisterCommand( &xStartTrace ); +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTaskStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *const pcHeader = "Task State Priority Stack #\r\n************************************************\r\n"; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + /* Generate a table of task stats. */ + strcpy( pcWriteBuffer, pcHeader ); + vTaskList( pcWriteBuffer + strlen( pcHeader ) ); + + /* There is no more data to return after this single string, so return + pdFALSE. */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvRunTimeStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char * const pcHeader = "Task Abs Time % Time\r\n****************************************\r\n"; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + /* Generate a table of task stats. */ + strcpy( pcWriteBuffer, pcHeader ); + vTaskGetRunTimeStats( pcWriteBuffer + strlen( pcHeader ) ); + + /* There is no more data to return after this single string, so return + pdFALSE. */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvThreeParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *pcParameter; +BaseType_t lParameterStringLength, xReturn; +static BaseType_t lParameterNumber = 0; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + if( lParameterNumber == 0 ) + { + /* The first time the function is called after the command has been + entered just a header string is returned. */ + sprintf( pcWriteBuffer, "The three parameters were:\r\n" ); + + /* Next time the function is called the first parameter will be echoed + back. */ + lParameterNumber = 1L; + + /* There is more data to be returned as no parameters have been echoed + back yet. */ + xReturn = pdPASS; + } + else + { + /* Obtain the parameter string. */ + pcParameter = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + lParameterNumber, /* Return the next parameter. */ + &lParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcParameter ); + + /* Return the parameter string. */ + memset( pcWriteBuffer, 0x00, xWriteBufferLen ); + sprintf( pcWriteBuffer, "%d: ", lParameterNumber ); + strncat( pcWriteBuffer, pcParameter, lParameterStringLength ); + strncat( pcWriteBuffer, "\r\n", strlen( "\r\n" ) ); + + /* If this is the last of the three parameters then there are no more + strings to return after this one. */ + if( lParameterNumber == 3L ) + { + /* If this is the last of the three parameters then there are no more + strings to return after this one. */ + xReturn = pdFALSE; + lParameterNumber = 0L; + } + else + { + /* There are more parameters to return after this one. */ + xReturn = pdTRUE; + lParameterNumber++; + } + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *pcParameter; +BaseType_t lParameterStringLength, xReturn; +static BaseType_t lParameterNumber = 0; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + if( lParameterNumber == 0 ) + { + /* The first time the function is called after the command has been + entered just a header string is returned. */ + sprintf( pcWriteBuffer, "The parameters were:\r\n" ); + + /* Next time the function is called the first parameter will be echoed + back. */ + lParameterNumber = 1L; + + /* There is more data to be returned as no parameters have been echoed + back yet. */ + xReturn = pdPASS; + } + else + { + /* Obtain the parameter string. */ + pcParameter = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + lParameterNumber, /* Return the next parameter. */ + &lParameterStringLength /* Store the parameter string length. */ + ); + + if( pcParameter != NULL ) + { + /* Return the parameter string. */ + memset( pcWriteBuffer, 0x00, xWriteBufferLen ); + sprintf( pcWriteBuffer, "%d: ", lParameterNumber ); + strncat( pcWriteBuffer, pcParameter, lParameterStringLength ); + strncat( pcWriteBuffer, "\r\n", strlen( "\r\n" ) ); + + /* There might be more parameters to return after this one. */ + xReturn = pdTRUE; + lParameterNumber++; + } + else + { + /* No more parameters were found. Make sure the write buffer does + not contain a valid string. */ + pcWriteBuffer[ 0 ] = 0x00; + + /* No more data to return. */ + xReturn = pdFALSE; + + /* Start over the next time this command is executed. */ + lParameterNumber = 0; + } + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvStartStopTraceCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *pcParameter; +BaseType_t lParameterStringLength; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + /* Obtain the parameter string. */ + pcParameter = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 1, /* Return the first parameter. */ + &lParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcParameter ); + + /* There are only two valid parameter values. */ + if( strncmp( pcParameter, "start", strlen( "start" ) ) == 0 ) + { + /* Start or restart the trace. */ + vTraceStop(); + vTraceClear(); + uiTraceStart(); + + sprintf( pcWriteBuffer, "Trace recording (re)started.\r\n" ); + } + else if( strncmp( pcParameter, "stop", strlen( "stop" ) ) == 0 ) + { + /* End the trace, if one is running. */ + vTraceStop(); + sprintf( pcWriteBuffer, "Stopping trace recording and dumping log to disk.\r\n" ); + prvSaveTraceFile(); + } + else + { + sprintf( pcWriteBuffer, "Valid parameters are 'start' and 'stop'.\r\n" ); + } + + /* There is no more data to return after this single string, so return + pdFALSE. */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static void prvSaveTraceFile( void ) +{ +FILE* pxOutputFile; + + fopen_s( &pxOutputFile, "Trace.dump", "wb"); + + if( pxOutputFile != NULL ) + { + fwrite( RecorderDataPtr, sizeof( RecorderDataType ), 1, pxOutputFile ); + fclose( pxOutputFile ); + printf( "\r\nTrace output saved to Trace.dump\r\n" ); + } + else + { + printf( "\r\nFailed to create trace dump file\r\n" ); + } +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/FreeRTOSConfig.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/FreeRTOSConfig.h new file mode 100644 index 0000000..f73e0f3 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/FreeRTOSConfig.h @@ -0,0 +1,124 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configTICK_RATE_HZ ( 1000 ) /* In this non-real time simulated environment the tick frequency has to be at least a multiple of the Win32 tick frequency, and therefore very slow. */ +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 60 ) /* In this simulated case, the stack only has to hold one small structure as the real stack is part of the Win32 thread. */ +#define configTOTAL_HEAP_SIZE ( ( size_t ) 0 ) /* This parameter has no effect when heap_3.c is included in the project. */ +#define configMAX_TASK_NAME_LEN ( 7 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configCHECK_FOR_STACK_OVERFLOW 0 /* Not applicable to the Win32 port. */ +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 + +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY 2 +#define configTIMER_QUEUE_LENGTH 20 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + +#define configMAX_PRIORITIES ( 7 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 1 + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + +/* Run time stats gathering definitions. */ +unsigned long ulGetRunTimeCounterValue( void ); +void vConfigureTimerForRunTimeStats( void ); +#define configGENERATE_RUN_TIME_STATS 1 +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vConfigureTimerForRunTimeStats() +#define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue() + +extern void vAssertCalled( void ); +#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled() + +/* The UDP port to use for incoming command inputs. The outgoing port is +set to ( configUDP_CLI_PORT_NUMBER + 1 ). */ +#define configUDP_CLI_PORT_NUMBER 5001 + +/* The size of the global output buffer that is available for use when there +are multiple command interpreters running at once (for example, one on a UART +and one on TCP/IP). This is done to prevent an output buffer being defined by +each implementation - which would waste RAM. In this case, there is only one +command interpreter running, and it has its own local output buffer, so the +global buffer is just set to be one byte long as it is not used and should not +take up unnecessary RAM. */ +#define configCOMMAND_INT_MAX_OUTPUT_SIZE 1 + + +/* Include the FreeRTOS+Trace FreeRTOS trace macro definitions. */ +#include "trcRecorder.h" + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/FreeRTOS_Plus_CLI_with_Trace.sln b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/FreeRTOS_Plus_CLI_with_Trace.sln new file mode 100644 index 0000000..6334f86 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/FreeRTOS_Plus_CLI_with_Trace.sln @@ -0,0 +1,22 @@ + +Microsoft Visual Studio Solution File, Format Version 12.00 +# Visual Studio 14 +VisualStudioVersion = 14.0.25420.1 +MinimumVisualStudioVersion = 10.0.40219.1 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "RTOSDemo", "WIN32.vcxproj", "{C686325E-3261-42F7-AEB1-DDE5280E1CEB}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Win32 = Debug|Win32 + Release|Win32 = Release|Win32 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.ActiveCfg = Debug|Win32 + {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.Build.0 = Debug|Win32 + {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.ActiveCfg = Release|Win32 + {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.Build.0 = Release|Win32 + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/READ_ME.url b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/READ_ME.url new file mode 100644 index 0000000..8ee5a95 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/READ_ME.url @@ -0,0 +1,5 @@ +[InternetShortcut] +URL=http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_Trace/Free_RTOS_Plus_Trace_CLI_Example.shtml +IDList= +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/Run-time-stats-utils.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/Run-time-stats-utils.c new file mode 100644 index 0000000..37204d1 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/Run-time-stats-utils.c @@ -0,0 +1,100 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * Utility functions required to gather run time statistics. See: + * http://www.freertos.org/rtos-run-time-stats.html + * + * Note that this is a simulated port, where simulated time is a lot slower than + * real time, therefore the run time counter values have no real meaningful + * units. + * + * Also note that it is assumed this demo is going to be used for short periods + * of time only, and therefore timer overflows are not handled. +*/ + +/* FreeRTOS includes. */ +#include + +/* Variables used in the creation of the run time stats time base. Run time +stats record how much time each task spends in the Running state. */ +static long long llInitialRunTimeCounterValue = 0LL, llTicksPerHundedthMillisecond = 0LL; + +/*-----------------------------------------------------------*/ + +void vConfigureTimerForRunTimeStats( void ) +{ +LARGE_INTEGER liPerformanceCounterFrequency, liInitialRunTimeValue; + + /* Initialise the variables used to create the run time stats time base. + Run time stats record how much time each task spends in the Running + state. */ + + if( QueryPerformanceFrequency( &liPerformanceCounterFrequency ) == 0 ) + { + llTicksPerHundedthMillisecond = 1; + } + else + { + /* How many times does the performance counter increment in 1/100th + millisecond. */ + llTicksPerHundedthMillisecond = liPerformanceCounterFrequency.QuadPart / 100000LL; + + /* What is the performance counter value now, this will be subtracted + from readings taken at run time. */ + QueryPerformanceCounter( &liInitialRunTimeValue ); + llInitialRunTimeCounterValue = liInitialRunTimeValue.QuadPart; + } +} +/*-----------------------------------------------------------*/ + +unsigned long ulGetRunTimeCounterValue( void ) +{ +LARGE_INTEGER liCurrentCount; +unsigned long ulReturn; + + /* What is the performance counter value now? */ + QueryPerformanceCounter( &liCurrentCount ); + + /* Subtract the performance counter value reading taken when the + application started to get a count from that reference point, then + scale to (simulated) 1/100ths of a millisecond. */ + if( llTicksPerHundedthMillisecond == 0 ) + { + /* The trace macros can call this function before the kernel has been + started, in which case llTicksPerHundedthMillisecond will not have been + initialised. */ + ulReturn = 0; + } + else + { + ulReturn = ( unsigned long ) ( ( liCurrentCount.QuadPart - llInitialRunTimeCounterValue ) / llTicksPerHundedthMillisecond ); + } + + return ulReturn; +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/Trace_Recorder_Configuration/trcConfig.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/Trace_Recorder_Configuration/trcConfig.h new file mode 100644 index 0000000..3a6fab8 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/Trace_Recorder_Configuration/trcConfig.h @@ -0,0 +1,300 @@ +/******************************************************************************* + * Trace Recorder Library for Tracealyzer v4.1.4 + * Percepio AB, www.percepio.com + * + * trcConfig.h + * + * Main configuration parameters for the trace recorder library. + * More settings can be found in trcStreamingConfig.h and trcSnapshotConfig.h. + * + * Read more at http://percepio.com/2016/10/05/rtos-tracing/ + * + * Terms of Use + * This file is part of the trace recorder library (RECORDER), which is the + * intellectual property of Percepio AB (PERCEPIO) and provided under a + * license as follows. + * The RECORDER may be used free of charge for the purpose of recording data + * intended for analysis in PERCEPIO products. It may not be used or modified + * for other purposes without explicit permission from PERCEPIO. + * You may distribute the RECORDER in its original source code form, assuming + * this text (terms of use, disclaimer, copyright notice) is unchanged. You are + * allowed to distribute the RECORDER with minor modifications intended for + * configuration or porting of the RECORDER, e.g., to allow using it on a + * specific processor, processor family or with a specific communication + * interface. Any such modifications should be documented directly below + * this comment block. + * + * Disclaimer + * The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty + * as to its use or performance. PERCEPIO does not and cannot warrant the + * performance or results you may obtain by using the RECORDER or documentation. + * PERCEPIO make no warranties, express or implied, as to noninfringement of + * third party rights, merchantability, or fitness for any particular purpose. + * In no event will PERCEPIO, its technology partners, or distributors be liable + * to you for any consequential, incidental or special damages, including any + * lost profits or lost savings, even if a representative of PERCEPIO has been + * advised of the possibility of such damages, or for any claim by any third + * party. Some jurisdictions do not allow the exclusion or limitation of + * incidental, consequential or special damages, or the exclusion of implied + * warranties or limitations on how long an implied warranty may last, so the + * above limitations may not apply to you. + * + * Tabs are used for indent in this file (1 tab = 4 spaces) + * + * Copyright Percepio AB, 2018. + * www.percepio.com + ******************************************************************************/ + +#ifndef TRC_CONFIG_H +#define TRC_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "trcPortDefines.h" + +/****************************************************************************** + * Include of processor header file + * + * Here you may need to include the header file for your processor. This is + * required at least for the ARM Cortex-M port, that uses the ARM CMSIS API. + * Try that in case of build problems. Otherwise, remove the #error line below. + *****************************************************************************/ +//#error "Trace Recorder: Please include your processor's header file here and remove this line." + +/******************************************************************************* + * Configuration Macro: TRC_CFG_HARDWARE_PORT + * + * Specify what hardware port to use (i.e., the "timestamping driver"). + * + * All ARM Cortex-M MCUs are supported by "TRC_HARDWARE_PORT_ARM_Cortex_M". + * This port uses the DWT cycle counter for Cortex-M3/M4/M7 devices, which is + * available on most such devices. In case your device don't have DWT support, + * you will get an error message opening the trace. In that case, you may + * force the recorder to use SysTick timestamping instead, using this define: + * + * #define TRC_CFG_ARM_CM_USE_SYSTICK + * + * For ARM Cortex-M0/M0+ devices, SysTick mode is used automatically. + * + * See trcHardwarePort.h for available ports and information on how to + * define your own port, if not already present. + ******************************************************************************/ +#define TRC_CFG_HARDWARE_PORT TRC_HARDWARE_PORT_Win32 + +/******************************************************************************* + * Configuration Macro: TRC_CFG_RECORDER_MODE + * + * Specify what recording mode to use. Snapshot means that the data is saved in + * an internal RAM buffer, for later upload. Streaming means that the data is + * transferred continuously to the host PC. + * + * For more information, see http://percepio.com/2016/10/05/rtos-tracing/ + * and the Tracealyzer User Manual. + * + * Values: + * TRC_RECORDER_MODE_SNAPSHOT + * TRC_RECORDER_MODE_STREAMING + ******************************************************************************/ +#define TRC_CFG_RECORDER_MODE TRC_RECORDER_MODE_SNAPSHOT +/****************************************************************************** + * TRC_CFG_FREERTOS_VERSION + * + * Specify what version of FreeRTOS that is used (don't change unless using the + * trace recorder library with an older version of FreeRTOS). + * + * TRC_FREERTOS_VERSION_7_3 If using FreeRTOS v7.3.x + * TRC_FREERTOS_VERSION_7_4 If using FreeRTOS v7.4.x + * TRC_FREERTOS_VERSION_7_5_OR_7_6 If using FreeRTOS v7.5.0 - v7.6.0 + * TRC_FREERTOS_VERSION_8_X If using FreeRTOS v8.X.X + * TRC_FREERTOS_VERSION_9_0_0 If using FreeRTOS v9.0.0 + * TRC_FREERTOS_VERSION_9_0_1 If using FreeRTOS v9.0.1 + * TRC_FREERTOS_VERSION_9_0_2 If using FreeRTOS v9.0.2 + * TRC_FREERTOS_VERSION_10_0_0 If using FreeRTOS v10.0.0 or later + *****************************************************************************/ +#define TRC_CFG_FREERTOS_VERSION TRC_FREERTOS_VERSION_10_0_0 + +/******************************************************************************* + * TRC_CFG_SCHEDULING_ONLY + * + * Macro which should be defined as an integer value. + * + * If this setting is enabled (= 1), only scheduling events are recorded. + * If disabled (= 0), all events are recorded (unless filtered in other ways). + * + * Default value is 0 (= include additional events). + ******************************************************************************/ +#define TRC_CFG_SCHEDULING_ONLY 0 + + /****************************************************************************** + * TRC_CFG_INCLUDE_MEMMANG_EVENTS + * + * Macro which should be defined as either zero (0) or one (1). + * + * This controls if malloc and free calls should be traced. Set this to zero (0) + * to exclude malloc/free calls, or one (1) to include such events in the trace. + * + * Default value is 1. + *****************************************************************************/ +#define TRC_CFG_INCLUDE_MEMMANG_EVENTS 1 + + /****************************************************************************** + * TRC_CFG_INCLUDE_USER_EVENTS + * + * Macro which should be defined as either zero (0) or one (1). + * + * If this is zero (0), all code related to User Events is excluded in order + * to reduce code size. Any attempts of storing User Events are then silently + * ignored. + * + * User Events are application-generated events, like "printf" but for the + * trace log, generated using vTracePrint and vTracePrintF. + * The formatting is done on host-side, by Tracealyzer. User Events are + * therefore much faster than a console printf and can often be used + * in timing critical code without problems. + * + * Note: In streaming mode, User Events are used to provide error messages + * and warnings from the recorder (in case of incorrect configuration) for + * display in Tracealyzer. Disabling user events will also disable these + * warnings. You can however still catch them by calling xTraceGetLastError + * or by putting breakpoints in prvTraceError and prvTraceWarning. + * + * Default value is 1. + *****************************************************************************/ +#define TRC_CFG_INCLUDE_USER_EVENTS 1 + + /***************************************************************************** + * TRC_CFG_INCLUDE_ISR_TRACING + * + * Macro which should be defined as either zero (0) or one (1). + * + * If this is zero (0), the code for recording Interrupt Service Routines is + * excluded, in order to reduce code size. + * + * Default value is 1. + * + * Note: tracing ISRs requires that you insert calls to vTraceStoreISRBegin + * and vTraceStoreISREnd in your interrupt handlers. + *****************************************************************************/ +#define TRC_CFG_INCLUDE_ISR_TRACING 1 + + /***************************************************************************** + * TRC_CFG_INCLUDE_READY_EVENTS + * + * Macro which should be defined as either zero (0) or one (1). + * + * If one (1), events are recorded when tasks enter scheduling state "ready". + * This allows Tracealyzer to show the initial pending time before tasks enter + * the execution state, and present accurate response times. + * If zero (0), "ready events" are not created, which allows for recording + * longer traces in the same amount of RAM. + * + * Default value is 1. + *****************************************************************************/ +#define TRC_CFG_INCLUDE_READY_EVENTS 1 + + /***************************************************************************** + * TRC_CFG_INCLUDE_OSTICK_EVENTS + * + * Macro which should be defined as either zero (0) or one (1). + * + * If this is one (1), events will be generated whenever the OS clock is + * increased. If zero (0), OS tick events are not generated, which allows for + * recording longer traces in the same amount of RAM. + * + * Default value is 1. + *****************************************************************************/ +#define TRC_CFG_INCLUDE_OSTICK_EVENTS 1 + + /***************************************************************************** + * TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS + * + * Macro which should be defined as either zero (0) or one (1). + * + * If this is zero (0), the trace will exclude any "event group" events. + * + * Default value is 0 (excluded) since dependent on event_groups.c + *****************************************************************************/ +#define TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS 0 + + /***************************************************************************** + * TRC_CFG_INCLUDE_TIMER_EVENTS + * + * Macro which should be defined as either zero (0) or one (1). + * + * If this is zero (0), the trace will exclude any Timer events. + * + * Default value is 0 since dependent on timers.c + *****************************************************************************/ +#define TRC_CFG_INCLUDE_TIMER_EVENTS 1 + + /***************************************************************************** + * TRC_CFG_INCLUDE_PEND_FUNC_CALL_EVENTS + * + * Macro which should be defined as either zero (0) or one (1). + * + * If this is zero (0), the trace will exclude any "pending function call" + * events, such as xTimerPendFunctionCall(). + * + * Default value is 0 since dependent on timers.c + *****************************************************************************/ +#define TRC_CFG_INCLUDE_PEND_FUNC_CALL_EVENTS 1 + +/******************************************************************************* + * Configuration Macro: TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS + * + * Macro which should be defined as either zero (0) or one (1). + * + * If this is zero (0), the trace will exclude any stream buffer or message + * buffer events. + * + * Default value is 0 since dependent on stream_buffer.c (new in FreeRTOS v10) + ******************************************************************************/ +#define TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS 0 + +/******************************************************************************* + * Configuration Macro: TRC_CFG_RECORDER_BUFFER_ALLOCATION + * + * Specifies how the recorder buffer is allocated (also in case of streaming, in + * port using the recorder's internal temporary buffer) + * + * Values: + * TRC_RECORDER_BUFFER_ALLOCATION_STATIC - Static allocation (internal) + * TRC_RECORDER_BUFFER_ALLOCATION_DYNAMIC - Malloc in vTraceEnable + * TRC_RECORDER_BUFFER_ALLOCATION_CUSTOM - Use vTraceSetRecorderDataBuffer + * + * Static and dynamic mode does the allocation for you, either in compile time + * (static) or in runtime (malloc). + * The custom mode allows you to control how and where the allocation is made, + * for details see TRC_ALLOC_CUSTOM_BUFFER and vTraceSetRecorderDataBuffer(). + ******************************************************************************/ +#define TRC_CFG_RECORDER_BUFFER_ALLOCATION TRC_RECORDER_BUFFER_ALLOCATION_STATIC + +/****************************************************************************** + * TRC_CFG_MAX_ISR_NESTING + * + * Defines how many levels of interrupt nesting the recorder can handle, in + * case multiple ISRs are traced and ISR nesting is possible. If this + * is exceeded, the particular ISR will not be traced and the recorder then + * logs an error message. This setting is used to allocate an internal stack + * for keeping track of the previous execution context (4 byte per entry). + * + * This value must be a non-zero positive constant, at least 1. + * + * Default value: 8 + *****************************************************************************/ +#define TRC_CFG_MAX_ISR_NESTING 8 + +/* Specific configuration, depending on Streaming/Snapshot mode */ +#if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_SNAPSHOT) +#include "trcSnapshotConfig.h" +#elif (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING) +#include "trcStreamingConfig.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _TRC_CONFIG_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/Trace_Recorder_Configuration/trcSnapshotConfig.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/Trace_Recorder_Configuration/trcSnapshotConfig.h new file mode 100644 index 0000000..aa22293 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/Trace_Recorder_Configuration/trcSnapshotConfig.h @@ -0,0 +1,378 @@ +/******************************************************************************* + * Trace Recorder Library for Tracealyzer v4.1.4 + * Percepio AB, www.percepio.com + * + * trcSnapshotConfig.h + * + * Configuration parameters for trace recorder library in snapshot mode. + * Read more at http://percepio.com/2016/10/05/rtos-tracing/ + * + * Terms of Use + * This file is part of the trace recorder library (RECORDER), which is the + * intellectual property of Percepio AB (PERCEPIO) and provided under a + * license as follows. + * The RECORDER may be used free of charge for the purpose of recording data + * intended for analysis in PERCEPIO products. It may not be used or modified + * for other purposes without explicit permission from PERCEPIO. + * You may distribute the RECORDER in its original source code form, assuming + * this text (terms of use, disclaimer, copyright notice) is unchanged. You are + * allowed to distribute the RECORDER with minor modifications intended for + * configuration or porting of the RECORDER, e.g., to allow using it on a + * specific processor, processor family or with a specific communication + * interface. Any such modifications should be documented directly below + * this comment block. + * + * Disclaimer + * The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty + * as to its use or performance. PERCEPIO does not and cannot warrant the + * performance or results you may obtain by using the RECORDER or documentation. + * PERCEPIO make no warranties, express or implied, as to noninfringement of + * third party rights, merchantability, or fitness for any particular purpose. + * In no event will PERCEPIO, its technology partners, or distributors be liable + * to you for any consequential, incidental or special damages, including any + * lost profits or lost savings, even if a representative of PERCEPIO has been + * advised of the possibility of such damages, or for any claim by any third + * party. Some jurisdictions do not allow the exclusion or limitation of + * incidental, consequential or special damages, or the exclusion of implied + * warranties or limitations on how long an implied warranty may last, so the + * above limitations may not apply to you. + * + * Tabs are used for indent in this file (1 tab = 4 spaces) + * + * Copyright Percepio AB, 2018. + * www.percepio.com + ******************************************************************************/ + +#ifndef TRC_SNAPSHOT_CONFIG_H +#define TRC_SNAPSHOT_CONFIG_H + +#define TRC_SNAPSHOT_MODE_RING_BUFFER (0x01) +#define TRC_SNAPSHOT_MODE_STOP_WHEN_FULL (0x02) + +/****************************************************************************** + * TRC_CFG_SNAPSHOT_MODE + * + * Macro which should be defined as one of: + * - TRC_SNAPSHOT_MODE_RING_BUFFER + * - TRC_SNAPSHOT_MODE_STOP_WHEN_FULL + * Default is TRC_SNAPSHOT_MODE_RING_BUFFER. + * + * With TRC_CFG_SNAPSHOT_MODE set to TRC_SNAPSHOT_MODE_RING_BUFFER, the + * events are stored in a ring buffer, i.e., where the oldest events are + * overwritten when the buffer becomes full. This allows you to get the last + * events leading up to an interesting state, e.g., an error, without having + * to store the whole run since startup. + * + * When TRC_CFG_SNAPSHOT_MODE is TRC_SNAPSHOT_MODE_STOP_WHEN_FULL, the + * recording is stopped when the buffer becomes full. This is useful for + * recording events following a specific state, e.g., the startup sequence. + *****************************************************************************/ +#define TRC_CFG_SNAPSHOT_MODE TRC_SNAPSHOT_MODE_RING_BUFFER + +/******************************************************************************* + * TRC_CFG_EVENT_BUFFER_SIZE + * + * Macro which should be defined as an integer value. + * + * This defines the capacity of the event buffer, i.e., the number of records + * it may store. Most events use one record (4 byte), although some events + * require multiple 4-byte records. You should adjust this to the amount of RAM + * available in the target system. + * + * Default value is 1000, which means that 4000 bytes is allocated for the + * event buffer. + ******************************************************************************/ +#define TRC_CFG_EVENT_BUFFER_SIZE 15000 + +/******************************************************************************* + * TRC_CFG_NTASK, TRC_CFG_NISR, TRC_CFG_NQUEUE, TRC_CFG_NSEMAPHORE... + * + * A group of macros which should be defined as integer values, zero or larger. + * + * These define the capacity of the Object Property Table, i.e., the maximum + * number of objects active at any given point, within each object class (e.g., + * task, queue, semaphore, ...). + * + * If tasks or other objects are deleted in your system, this + * setting does not limit the total amount of objects created, only the number + * of objects that have been successfully created but not yet deleted. + * + * Using too small values will cause vTraceError to be called, which stores an + * error message in the trace that is shown when opening the trace file. The + * error message can also be retrieved using xTraceGetLastError. + * + * It can be wise to start with large values for these constants, + * unless you are very confident on these numbers. Then do a recording and + * check the actual usage by selecting View menu -> Trace Details -> + * Resource Usage -> Object Table. + ******************************************************************************/ +#define TRC_CFG_NTASK 150 +#define TRC_CFG_NISR 90 +#define TRC_CFG_NQUEUE 90 +#define TRC_CFG_NSEMAPHORE 90 +#define TRC_CFG_NMUTEX 90 +#define TRC_CFG_NTIMER 250 +#define TRC_CFG_NEVENTGROUP 90 +#define TRC_CFG_NSTREAMBUFFER 50 +#define TRC_CFG_NMESSAGEBUFFER 50 + + +/****************************************************************************** + * TRC_CFG_INCLUDE_FLOAT_SUPPORT + * + * Macro which should be defined as either zero (0) or one (1). + * + * If this is zero (0), the support for logging floating point values in + * vTracePrintF is stripped out, in case floating point values are not used or + * supported by the platform used. + * + * Floating point values are only used in vTracePrintF and its subroutines, to + * allow for storing float (%f) or double (%lf) arguments. + * + * vTracePrintF can be used with integer and string arguments in either case. + * + * Default value is 0. + *****************************************************************************/ +#define TRC_CFG_INCLUDE_FLOAT_SUPPORT 0 + +/******************************************************************************* + * TRC_CFG_SYMBOL_TABLE_SIZE + * + * Macro which should be defined as an integer value. + * + * This defines the capacity of the symbol table, in bytes. This symbol table + * stores User Events labels and names of deleted tasks, queues, or other kernel + * objects. If you don't use User Events or delete any kernel + * objects you set this to a very low value. The minimum recommended value is 4. + * A size of zero (0) is not allowed since a zero-sized array may result in a + * 32-bit pointer, i.e., using 4 bytes rather than 0. + * + * Default value is 800. + ******************************************************************************/ +#define TRC_CFG_SYMBOL_TABLE_SIZE 5000 + +#if (TRC_CFG_SYMBOL_TABLE_SIZE == 0) +#error "TRC_CFG_SYMBOL_TABLE_SIZE may not be zero!" +#endif + +/****************************************************************************** + * TRC_CFG_NAME_LEN_TASK, TRC_CFG_NAME_LEN_QUEUE, ... + * + * Macros that specify the maximum lengths (number of characters) for names of + * kernel objects, such as tasks and queues. If longer names are used, they will + * be truncated when stored in the recorder. + *****************************************************************************/ +#define TRC_CFG_NAME_LEN_TASK 15 +#define TRC_CFG_NAME_LEN_ISR 15 +#define TRC_CFG_NAME_LEN_QUEUE 15 +#define TRC_CFG_NAME_LEN_SEMAPHORE 15 +#define TRC_CFG_NAME_LEN_MUTEX 15 +#define TRC_CFG_NAME_LEN_TIMER 15 +#define TRC_CFG_NAME_LEN_EVENTGROUP 15 +#define TRC_CFG_NAME_LEN_STREAMBUFFER 15 +#define TRC_CFG_NAME_LEN_MESSAGEBUFFER 15 + +/****************************************************************************** + *** ADVANCED SETTINGS ******************************************************** + ****************************************************************************** + * The remaining settings are not necessary to modify but allows for optimizing + * the recorder setup for your specific needs, e.g., to exclude events that you + * are not interested in, in order to get longer traces. + *****************************************************************************/ + +/****************************************************************************** +* TRC_CFG_HEAP_SIZE_BELOW_16M +* +* An integer constant that can be used to reduce the buffer usage of memory +* allocation events (malloc/free). This value should be 1 if the heap size is +* below 16 MB (2^24 byte), and you can live with reported addresses showing the +* lower 24 bits only. If 0, you get the full 32-bit addresses. +* +* Default value is 0. +******************************************************************************/ +#define TRC_CFG_HEAP_SIZE_BELOW_16M 0 + +/****************************************************************************** + * TRC_CFG_USE_IMPLICIT_IFE_RULES + * + * Macro which should be defined as either zero (0) or one (1). + * Default is 1. + * + * Tracealyzer groups the events into "instances" based on Instance Finish + * Events (IFEs), produced either by default rules or calls to the recorder + * functions vTraceInstanceFinishedNow and vTraceInstanceFinishedNext. + * + * If TRC_CFG_USE_IMPLICIT_IFE_RULES is one (1), the default IFE rules is + * used, resulting in a "typical" grouping of events into instances. + * If these rules don't give appropriate instances in your case, you can + * override the default rules using vTraceInstanceFinishedNow/Next for one + * or several tasks. The default IFE rules are then disabled for those tasks. + * + * If TRC_CFG_USE_IMPLICIT_IFE_RULES is zero (0), the implicit IFE rules are + * disabled globally. You must then call vTraceInstanceFinishedNow or + * vTraceInstanceFinishedNext to manually group the events into instances, + * otherwise the tasks will appear a single long instance. + * + * The default IFE rules count the following events as "instance finished": + * - Task delay, delay until + * - Task suspend + * - Blocking on "input" operations, i.e., when the task is waiting for the + * next a message/signal/event. But only if this event is blocking. + * + * For details, see trcSnapshotKernelPort.h and look for references to the + * macro trcKERNEL_HOOKS_SET_TASK_INSTANCE_FINISHED. + *****************************************************************************/ +#define TRC_CFG_USE_IMPLICIT_IFE_RULES 1 + +/****************************************************************************** + * TRC_CFG_USE_16BIT_OBJECT_HANDLES + * + * Macro which should be defined as either zero (0) or one (1). + * + * If set to 0 (zero), the recorder uses 8-bit handles to identify kernel + * objects such as tasks and queues. This limits the supported number of + * concurrently active objects to 255 of each type (tasks, queues, mutexes, + * etc.) Note: 255, not 256, since handle 0 is reserved. + * + * If set to 1 (one), the recorder uses 16-bit handles to identify kernel + * objects such as tasks and queues. This limits the supported number of + * concurrent objects to 65535 of each type (object class). However, since the + * object property table is limited to 64 KB, the practical limit is about + * 3000 objects in total. + * + * Default is 0 (8-bit handles) + * + * NOTE: An object with handle above 255 will use an extra 4-byte record in + * the event buffer whenever the object is referenced. Moreover, some internal + * tables in the recorder gets slightly larger when using 16-bit handles. + *****************************************************************************/ +#define TRC_CFG_USE_16BIT_OBJECT_HANDLES 0 + +/****************************************************************************** + * TRC_CFG_USE_TRACE_ASSERT + * + * Macro which should be defined as either zero (0) or one (1). + * Default is 1. + * + * If this is one (1), the TRACE_ASSERT macro (used at various locations in the + * trace recorder) will verify that a relevant condition is true. + * If the condition is false, prvTraceError() will be called, which stops the + * recording and stores an error message that is displayed when opening the + * trace in Tracealyzer. + * + * This is used on several places in the recorder code for sanity checks on + * parameters. Can be switched off to reduce the footprint of the tracing, but + * we recommend to have it enabled initially. + *****************************************************************************/ +#define TRC_CFG_USE_TRACE_ASSERT 1 + +/******************************************************************************* + * TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER + * + * Macro which should be defined as an integer value. + * + * Set TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER to 1 to enable the + * separate user event buffer (UB). + * In this mode, user events are stored separately from other events, + * e.g., RTOS events. Thereby you can get a much longer history of + * user events as they don't need to share the buffer space with more + * frequent events. + * + * The UB is typically used with the snapshot ring-buffer mode, so the + * recording can continue when the main buffer gets full. And since the + * main buffer then overwrites the earliest events, Tracealyzer displays + * "Unknown Actor" instead of task scheduling for periods with UB data only. + * + * In UB mode, user events are structured as UB channels, which contains + * a channel name and a default format string. Register a UB channel using + * xTraceRegisterUBChannel. + * + * Events and data arguments are written using vTraceUBEvent and + * vTraceUBData. They are designed to provide efficient logging of + * repeating events, using the same format string within each channel. + * + * Examples: + * + * traceString chn1 = xTraceRegisterString("Channel 1"); + * traceString fmt1 = xTraceRegisterString("Event!"); + * traceUBChannel UBCh1 = xTraceRegisterUBChannel(chn1, fmt1); + * + * traceString chn2 = xTraceRegisterString("Channel 2"); + * traceString fmt2 = xTraceRegisterString("X: %d, Y: %d"); + * traceUBChannel UBCh2 = xTraceRegisterUBChannel(chn2, fmt2); + * + * // Result in "[Channel 1] Event!" + * vTraceUBEvent(UBCh1); + * + * // Result in "[Channel 2] X: 23, Y: 19" + * vTraceUBData(UBCh2, 23, 19); + * + * You can also use the other user event functions, like vTracePrintF. + * as they are then rerouted to the UB instead of the main event buffer. + * vTracePrintF then looks up the correct UB channel based on the + * provided channel name and format string, or creates a new UB channel + * if no match is found. The format string should therefore not contain + * "random" messages but mainly format specifiers. Random strings should + * be stored using %s and with the string as an argument. + * + * // Creates a new UB channel ("Channel 2", "%Z: %d") + * vTracePrintF(chn2, "%Z: %d", value1); + * + * // Finds the existing UB channel + * vTracePrintF(chn2, "%Z: %d", value2); + + ******************************************************************************/ +#define TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER 0 + +/******************************************************************************* + * TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE + * + * Macro which should be defined as an integer value. + * + * This defines the capacity of the user event buffer (UB), in number of slots. + * A single user event can use multiple slots, depending on the arguments. + * + * Only applicable if TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER is 1. + ******************************************************************************/ +#define TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE 200 + +/******************************************************************************* + * TRC_CFG_UB_CHANNELS + * + * Macro which should be defined as an integer value. + * + * This defines the number of User Event Buffer Channels (UB channels). + * These are used to structure the events when using the separate user + * event buffer, and contains both a User Event Channel (the name) and + * a default format string for the channel. + * + * Only applicable if TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER is 1. + ******************************************************************************/ +#define TRC_CFG_UB_CHANNELS 32 + +/******************************************************************************* + * TRC_CFG_ISR_TAILCHAINING_THRESHOLD + * + * Macro which should be defined as an integer value. + * + * If tracing multiple ISRs, this setting allows for accurate display of the + * context-switching also in cases when the ISRs execute in direct sequence. + * + * vTraceStoreISREnd normally assumes that the ISR returns to the previous + * context, i.e., a task or a preempted ISR. But if another traced ISR + * executes in direct sequence, Tracealyzer may incorrectly display a minimal + * fragment of the previous context in between the ISRs. + * + * By using TRC_CFG_ISR_TAILCHAINING_THRESHOLD you can avoid this. This is + * however a threshold value that must be measured for your specific setup. + * See http://percepio.com/2014/03/21/isr_tailchaining_threshold/ + * + * The default setting is 0, meaning "disabled" and that you may get an + * extra fragments of the previous context in between tail-chained ISRs. + * + * Note: This setting has separate definitions in trcSnapshotConfig.h and + * trcStreamingConfig.h, since it is affected by the recorder mode. + ******************************************************************************/ +#define TRC_CFG_ISR_TAILCHAINING_THRESHOLD 0 + +#endif /*TRC_SNAPSHOT_CONFIG_H*/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/UDPCommandServer.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/UDPCommandServer.c new file mode 100644 index 0000000..d155d87 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/UDPCommandServer.c @@ -0,0 +1,221 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#pragma comment( lib, "ws2_32.lib" ) + +/* Win32 includes. */ +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* FreeRTOS+CLI includes. */ +#include "FreeRTOS_CLI.h" + +/* Dimensions the buffer into which input characters are placed. */ +#define cmdMAX_INPUT_SIZE 60 + +/* Dimensions the buffer into which string outputs can be placed. */ +#define cmdMAX_OUTPUT_SIZE 1024 + +/* Dimensions the buffer passed to the recvfrom() call. */ +#define cmdSOCKET_INPUT_BUFFER_SIZE 60 + +/* + * Open and configure the UDP socket. + */ +static SOCKET prvOpenUDPSocket( void ); + +/*-----------------------------------------------------------*/ + +/* + * Task that provides the input and output for the FreeRTOS+CLI command + * interpreter. In this case a UDP port is used. See the URL in the comments + * within main.c for the location of the online documentation. + */ +void vUDPCommandInterpreterTask( void *pvParameters ) +{ +long lBytes, lByte; +signed char cInChar, cInputIndex = 0; +static signed char cInputString[ cmdMAX_INPUT_SIZE ], cOutputString[ cmdMAX_OUTPUT_SIZE ], cLocalBuffer[ cmdSOCKET_INPUT_BUFFER_SIZE ]; +BaseType_t xMoreDataToFollow; +volatile int iErrorCode = 0; +struct sockaddr_in xClient; +int xClientAddressLength = sizeof( struct sockaddr_in ); +SOCKET xSocket; + + /* Just to prevent compiler warnings. */ + ( void ) pvParameters; + + /* Attempt to open the socket. */ + xSocket = prvOpenUDPSocket(); + + if( xSocket != INVALID_SOCKET ) + { + for( ;; ) + { + /* Wait for incoming data on the opened socket. */ + lBytes = recvfrom( xSocket, cLocalBuffer, sizeof( cLocalBuffer ), 0, ( struct sockaddr * ) &xClient, &xClientAddressLength ); + + if( lBytes == SOCKET_ERROR ) + { + /* Something went wrong, but it is not handled by this simple + example. */ + iErrorCode = WSAGetLastError(); + } + else + { + /* Process each received byte in turn. */ + lByte = 0; + while( lByte < lBytes ) + { + /* The next character in the input buffer. */ + cInChar = cLocalBuffer[ lByte ]; + lByte++; + + /* Newline characters are taken as the end of the command + string. */ + if( cInChar == '\n' ) + { + /* Process the input string received prior to the + newline. */ + do + { + /* Pass the string to FreeRTOS+CLI. */ + xMoreDataToFollow = FreeRTOS_CLIProcessCommand( cInputString, cOutputString, cmdMAX_OUTPUT_SIZE ); + + /* Send the output generated by the command's + implementation. */ + sendto( xSocket, cOutputString, strlen( cOutputString ), 0, ( SOCKADDR * ) &xClient, xClientAddressLength ); + + } while( xMoreDataToFollow != pdFALSE ); /* Until the command does not generate any more output. */ + + /* All the strings generated by the command processing + have been sent. Clear the input string ready to receive + the next command. */ + cInputIndex = 0; + memset( cInputString, 0x00, cmdMAX_INPUT_SIZE ); + + /* Transmit a spacer, just to make the command console + easier to read. */ + sendto( xSocket, "\r\n", strlen( "\r\n" ), 0, ( SOCKADDR * ) &xClient, xClientAddressLength ); + } + else + { + if( cInChar == '\r' ) + { + /* Ignore the character. Newlines are used to + detect the end of the input string. */ + } + else if( cInChar == '\b' ) + { + /* Backspace was pressed. Erase the last character + in the string - if any. */ + if( cInputIndex > 0 ) + { + cInputIndex--; + cInputString[ cInputIndex ] = '\0'; + } + } + else + { + /* A character was entered. Add it to the string + entered so far. When a \n is entered the complete + string will be passed to the command interpreter. */ + if( cInputIndex < cmdMAX_INPUT_SIZE ) + { + cInputString[ cInputIndex ] = cInChar; + cInputIndex++; + } + } + } + } + } + } + } + else + { + /* The socket could not be opened. */ + vTaskDelete( NULL ); + } +} +/*-----------------------------------------------------------*/ + +static SOCKET prvOpenUDPSocket( void ) +{ +WSADATA xWSAData; +WORD wVersionRequested; +struct sockaddr_in xServer; +SOCKET xSocket = INVALID_SOCKET; + + wVersionRequested = MAKEWORD( 2, 2 ); + + /* Prepare to use WinSock. */ + if( WSAStartup( wVersionRequested, &xWSAData ) != 0 ) + { + fprintf( stderr, "Could not open Windows connection.\n" ); + } + else + { + xSocket = socket( AF_INET, SOCK_DGRAM, 0 ); + if( xSocket == INVALID_SOCKET) + { + fprintf( stderr, "Could not create socket.\n" ); + WSACleanup(); + } + else + { + /* Zero out the server structure. */ + memset( ( void * ) &xServer, 0x00, sizeof( struct sockaddr_in ) ); + + /* Set family and port. */ + xServer.sin_family = AF_INET; + xServer.sin_port = htons( configUDP_CLI_PORT_NUMBER ); + + /* Assign the loopback address */ + xServer.sin_addr.S_un.S_un_b.s_b1 = 127; + xServer.sin_addr.S_un.S_un_b.s_b2 = 0; + xServer.sin_addr.S_un.S_un_b.s_b3 = 0; + xServer.sin_addr.S_un.S_un_b.s_b4 = 1; + + /* Bind the address to the socket. */ + if( bind( xSocket, ( struct sockaddr * ) &xServer, sizeof( struct sockaddr_in ) ) == -1 ) + { + fprintf( stderr, "Could not socket to port %d.\n", configUDP_CLI_PORT_NUMBER ); + closesocket( xSocket ); + xSocket = INVALID_SOCKET; + WSACleanup(); + } + } + } + + return xSocket; +} + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/WIN32.vcxproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/WIN32.vcxproj new file mode 100644 index 0000000..29a2fba --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/WIN32.vcxproj @@ -0,0 +1,160 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + + {C686325E-3261-42F7-AEB1-DDE5280E1CEB} + RTOSDemo + + + + Application + false + MultiByte + v140 + + + Application + false + MultiByte + v140 + + + + + + + + + + + + + + + <_ProjectFileVersion>10.0.30319.1 + .\Debug\ + .\Debug\ + true + .\Release\ + .\Release\ + false + + + + .\Debug/WIN32.tlb + + + + + Disabled + ..\..\Source\FreeRTOS-Plus-Trace\Include;..\..\..\FreeRTOS\Source\include;..\..\..\FreeRTOS\Source\portable\MSVC-MingW;..\..\Source\FreeRTOS-Plus-CLI;.\Trace_Recorder_Configuration;.;%(AdditionalIncludeDirectories) + WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) + true + EnableFastChecks + MultiThreadedDebug + .\Debug/WIN32.pch + .\Debug/ + .\Debug/ + .\Debug/ + Level4 + true + false + EditAndContinue + + + _DEBUG;%(PreprocessorDefinitions) + 0x0c09 + + + .\Debug/RTOSDemo.exe + true + true + .\Debug/WIN32.pdb + Console + MachineX86 + %(AdditionalDependencies) + + + + + true + .\Debug/WIN32.bsc + + + + + .\Release/WIN32.tlb + + + + + MaxSpeed + OnlyExplicitInline + _WINSOCKAPI_;WIN32;NDEBUG;_CONSOLE;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) + true + MultiThreaded + true + .\Release/WIN32.pch + .\Release/ + .\Release/ + .\Release/ + Level3 + true + ..\Common\Utils;..\Common\ethernet\lwip-1.4.0\ports\win32\WinPCap;..\Common\ethernet\lwip-1.4.0\src\include\ipv4;..\Common\ethernet\lwip-1.4.0\src\include;..\..\Source\include;..\..\Source\portable\MSVC-MingW;..\Common\ethernet\lwip-1.4.0\ports\win32\include;..\Common\Include;.\lwIP_Apps;.;%(AdditionalIncludeDirectories) + + + NDEBUG;%(PreprocessorDefinitions) + 0x0c09 + + + .\Release/RTOSDemo.exe + true + .\Release/WIN32.pdb + Console + MachineX86 + ..\Common\ethernet\lwip-1.4.0\ports\win32\WinPCap + wpcap.lib;%(AdditionalDependencies) + + + true + .\Release/WIN32.bsc + + + + + + + + + + + + + + + + %(AdditionalIncludeDirectories) + %(PreprocessorDefinitions) + %(PreprocessorDefinitions) + + + + + + + + + + + + + \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/WIN32.vcxproj.filters b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/WIN32.vcxproj.filters new file mode 100644 index 0000000..d112c99 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/WIN32.vcxproj.filters @@ -0,0 +1,95 @@ + + + + + {38712199-cebf-4124-bf15-398f7c3419ea} + ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe + + + {34567deb-d5ab-4a56-8640-0aaec609521a} + cpp;c;cxx;rc;def;r;odl;idl;hpj;bat + + + {af3445a1-4908-4170-89ed-39345d90d30c} + + + {f32be356-4763-4cae-9020-974a2638cb08} + *.c + + + {88f409e6-d396-4ac5-94bd-7a99c914be46} + + + {e5ad4ec7-23dc-4295-8add-2acaee488f5a} + + + {629e761f-e8a8-430e-b44e-f38d83292b54} + + + {19ff1a34-36de-4c48-9d10-3fb1fa0d1fa4} + + + + + {fd43c0ed-fdbc-437f-a5a3-c50399690bd7} + + + {91dffc7b-279b-44f6-a2b2-f5d2e132a85d} + + + + + Demo App Source + + + FreeRTOS\Source\Portable + + + FreeRTOS\Source\Portable + + + FreeRTOS\Source + + + FreeRTOS\Source + + + FreeRTOS\Source + + + FreeRTOS\Source + + + Demo App Source + + + Demo App Source + + + Demo App Source + + + FreeRTOS+\FreeRTOS+CLI + + + FreeRTOS+\FreeRTOS+Trace + + + FreeRTOS+\FreeRTOS+Trace + + + FreeRTOS+\FreeRTOS+Trace + + + + + FreeRTOS\Configuration Files + + + Demo App Source\Trace Recorder Configuration + + + Demo App Source\Trace Recorder Configuration + + + \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/WIN32.vcxproj.user b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/WIN32.vcxproj.user new file mode 100644 index 0000000..695b5c7 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/WIN32.vcxproj.user @@ -0,0 +1,3 @@ + + + \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/main.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/main.c new file mode 100644 index 0000000..a8e293d --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/main.c @@ -0,0 +1,246 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + ****************************************************************************** + * -NOTE- The Win32 port is a simulation (or is that emulation?) only! Do not + * expect to get real time behaviour from the Win32 port or this demo + * application. It is provided as a convenient development and demonstration + * test bed only. This was tested using Windows XP on a dual core laptop. + * + * Windows will not be running the FreeRTOS simulator threads continuously, so + * the timing information in the FreeRTOS+Trace logs have no meaningful units. + * See the documentation page for the Windows simulator for an explanation of + * the slow timing: + * http://www.freertos.org/FreeRTOS-Windows-Simulator-Emulator-for-Visual-Studio-and-Eclipse-MingW.html + * - READ THE WEB DOCUMENTATION FOR THIS PORT FOR MORE INFORMATION ON USING IT - + * + * Documentation for this demo can be found on: + * http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_Trace/Free_RTOS_Plus_Trace_CLI_Example.shtml + ****************************************************************************** + * + * This is a simple FreeRTOS Windows simulator project that makes it easy to + * evaluate FreeRTOS+CLI and FreeRTOS+Trace on a standard desktop PC, without + * any external hardware or interfaces being required. + * + * To keep everything as simple as possible, the command line interface is + * accessed through a UDP socket on the default Windows loopback IP address of + * 127.0.0.1. Full instructions are provided on the documentation page + * referenced above. + * + * Commands are provided to both start and stop a FreeRTOS+Trace recording. + * Stopping a recording will result in the recorded data being saved to the + * hard disk, ready for viewing in the FreeRTOS+Trace graphical user interface. + * Again, full instructions are provided on the documentation page referenced + * above. + * + * A queue send task and a queue receive task are defined in this file. The + * queue receive task spends most of its time blocked on the queue waiting for + * messages to arrive. The queue send task periodically sends a message to the + * queue, causing the queue receive task to exit the Blocked state. The + * priority of the queue receive task is above that of the queue send task, so + * it pre-empts the queue send task as soon as it leaves the Blocked state. It + * then consumes the message from the queue and prints "message received" to + * the screen before returning to block on the queue once again. This + * sequencing is clearly visible in the recorded FreeRTOS+Trace data. + * + */ + +/* Standard includes. */ +#include +#include + +/* FreeRTOS includes. */ +#include +#include "task.h" +#include "queue.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainUDP_CLI_TASK_PRIORITY ( tskIDLE_PRIORITY ) + +/* The rate at which data is sent to the queue. The (simulated) 250ms value is +converted to ticks using the portTICK_RATE_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 250 / portTICK_RATE_MS ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/*-----------------------------------------------------------*/ + +/* + * The queue send and receive tasks as described in the comments at the top of + * this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/* + * The task that implements the UDP command interpreter using FreeRTOS+CLI. + */ +extern void vUDPCommandInterpreterTask( void *pvParameters ); + +/* + * Register commands that can be used with FreeRTOS+CLI through the UDP socket. + * The commands are defined in CLI-commands.c. + */ +extern void vRegisterCLICommands( void ); + +/* The queue used by both tasks. */ +static xQueueHandle xQueue = NULL; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ +const uint32_t ulLongTime_ms = 250UL; + + /* Initialise the trace recorder and create the label used to post user + events to the trace recording on each tick interrupt. */ + vTraceEnable( TRC_START ); + + /* Create the queue used to pass messages from the queue send task to the + queue receive task. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); + + /* Give the queue a name for the FreeRTOS+Trace log. */ + vTraceSetQueueName( xQueue, "DemoQ" ); + + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. Not actually used as a stack in the Win32 simulator port. */ + NULL, /* The parameter passed to the task - not used in this example. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Create the task that handles the CLI on a UDP port. The port number + is set using the configUDP_CLI_PORT_NUMBER setting in FreeRTOSConfig.h. */ + xTaskCreate( vUDPCommandInterpreterTask, "CLI", configMINIMAL_STACK_SIZE, NULL, mainUDP_CLI_TASK_PRIORITY, NULL ); + + /* Register commands with the FreeRTOS+CLI command interpreter. */ + vRegisterCLICommands(); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was insufficient FreeRTOS heap memory available for the idle and/or + timer tasks to be created. See the memory management section on the + FreeRTOS web site for more details (this is standard text that is not + really applicable to the Win32 simulator port). */ + for( ;; ) + { + Sleep( ulLongTime_ms ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +TickType_t xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Remove warning about unused parameters. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. + While in the Blocked state this task will not consume any CPU time. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + write a message to the display. 0 is used as the block time so the + sending operation will not block - it shouldn't need to block as the + queue should always be empty at this point in the code, and it is an + error if it is not. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; + + /* Remove warning about unused parameters. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, write the message to the + display before looping back to block on the queue again. */ + if( ulReceivedValue == 100UL ) + { + printf( "Message received!\r\n" ); + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +const unsigned long ulMSToSleep = 5; + + /* This function is called on each cycle of the idle task if + configUSE_IDLE_HOOK is set to 1 in FreeRTOSConfig.h. Sleep to reduce CPU + load. */ + Sleep( ulMSToSleep ); +} +/*-----------------------------------------------------------*/ + +void vAssertCalled( void ) +{ +const unsigned long ulLongSleep = 1000UL; + + taskDISABLE_INTERRUPTS(); + for( ;; ) + { + Sleep( ulLongSleep ); + } +} +/*-----------------------------------------------------------*/ + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/readme.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/readme.txt new file mode 100644 index 0000000..1a0cbcf --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/readme.txt @@ -0,0 +1,7 @@ +Directories: + ++ FreeRTOS-Plus/Demo_Projects_Using_FreeRTOS_Simulator/FreeRTOS_Plus_CLI_with_Trace + contains a FreeRTOS windows simulator demo project for both FreeRTOS+CLI and + FreeRTOS+Trace. See http://www.FreeRTOS.org/trace for information on using + the project. + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/ReadMe.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/ReadMe.txt new file mode 100644 index 0000000..7561001 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/ReadMe.txt @@ -0,0 +1,7 @@ +This demo was removed in FreeRTOS V10.0.0 as FreeRTOS+FAT SL was not distributed +in that release. The full FreeRTOS+FAT product (as opposed to the 'SL' Super +Lean product) is still available. Previous versions of FreeRTOS can be +downloaded from http://sourceforge.net/projects/freertos/files/FreeRTOS/ + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/ConfigurationFiles/FreeRTOSConfig.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/ConfigurationFiles/FreeRTOSConfig.h new file mode 100644 index 0000000..347140a --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/ConfigurationFiles/FreeRTOSConfig.h @@ -0,0 +1,131 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * http://www.freertos.org/a00110.html + * + * The bottom of this file contains some constants specific to running the UDP + * stack in this demo. Constants specific to FreeRTOS+UDP itself (rather than + * the demo) are contained in FreeRTOSIPConfig.h. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configMAX_PRIORITIES ( 7 ) +#define configTICK_RATE_HZ ( 1000 ) /* In this non-real time simulated environment the tick frequency has to be at least a multiple of the Win32 tick frequency, and therefore very slow. */ +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 60 ) /* In this simulated case, the stack only has to hold one small structure as the real stack is part of the Win32 thread. */ +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32U * 1024U ) ) +#define configMAX_TASK_NAME_LEN ( 7 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 0 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 + +/* Hook function related definitions. */ +#define configUSE_TICK_HOOK 0 +#define configUSE_IDLE_HOOK 1 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configCHECK_FOR_STACK_OVERFLOW 0 /* Not applicable to the Win32 port. */ + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + +/* Run time stats gathering definitions. */ +unsigned long ulGetRunTimeCounterValue( void ); +void vConfigureTimerForRunTimeStats( void ); +#define configGENERATE_RUN_TIME_STATS 1 +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vConfigureTimerForRunTimeStats() +#define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue() + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTimerGetTimerTaskHandle 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xQueueGetMutexHolder 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + +/* Assert call defined for debug builds. */ +#ifdef _DEBUG + extern void vAssertCalled( const char *pcFile, unsigned long ulLine ); + #define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ ) +#endif /* _DEBUG */ + + + +/* Application specific definitions follow. **********************************/ + +/* The UDP port to use for incoming command inputs. The outgoing port is +set to ( configUDP_CLI_PORT_NUMBER + 1 ). */ +#define configUDP_CLI_PORT_NUMBER 5001 + +/* The size of the global output buffer that is available for use when there +are multiple command interpreters running at once (for example, one on a UART +and one on TCP/IP). This is done to prevent an output buffer being defined by +each implementation - which would waste RAM. In this case, there is only one +command interpreter running, and it has its own local output buffer, so the +global buffer is just set to be one byte long as it is not used and should not +take up unnecessary RAM. */ +#define configCOMMAND_INT_MAX_OUTPUT_SIZE 1 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/ConfigurationFiles/redconf.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/ConfigurationFiles/redconf.c new file mode 100644 index 0000000..129697f --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/ConfigurationFiles/redconf.c @@ -0,0 +1,17 @@ +/* THIS FILE WAS GENERATED BY THE DATALIGHT RELIANCE EDGE CONFIGURATION + UTILITY. DO NOT MODIFY. + + Generated by configuration utility version 2.0 +*/ +/** @file +*/ +#include +#include +#include +#include + + +const VOLCONF gaRedVolConf[REDCONF_VOLUME_COUNT] = +{ + { 512U, 65536U, false, 256U, 0U, "" } +}; diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/ConfigurationFiles/redconf.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/ConfigurationFiles/redconf.h new file mode 100644 index 0000000..c0d2f2a --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/ConfigurationFiles/redconf.h @@ -0,0 +1,112 @@ +/* THIS FILE WAS GENERATED BY THE DATALIGHT RELIANCE EDGE CONFIGURATION + UTILITY. DO NOT MODIFY. + + Generated by configuration utility version 2.0 +*/ +/** @file +*/ +#ifndef REDCONF_H +#define REDCONF_H + + +#include + +#define REDCONF_READ_ONLY 0 + +#define REDCONF_API_POSIX 1 + +#define REDCONF_API_FSE 0 + +#define REDCONF_API_POSIX_FORMAT 1 + +#define REDCONF_API_POSIX_LINK 1 + +#define REDCONF_API_POSIX_UNLINK 1 + +#define REDCONF_API_POSIX_MKDIR 1 + +#define REDCONF_API_POSIX_RMDIR 1 + +#define REDCONF_API_POSIX_RENAME 1 + +#define REDCONF_RENAME_ATOMIC 1 + +#define REDCONF_API_POSIX_FTRUNCATE 1 + +#define REDCONF_API_POSIX_READDIR 1 + +#define REDCONF_NAME_MAX 28U + +#define REDCONF_PATH_SEPARATOR '/' + +#define REDCONF_TASK_COUNT 10U + +#define REDCONF_HANDLE_COUNT 10U + +#define REDCONF_API_FSE_FORMAT 0 + +#define REDCONF_API_FSE_TRUNCATE 0 + +#define REDCONF_API_FSE_TRANSMASKGET 0 + +#define REDCONF_API_FSE_TRANSMASKSET 0 + +#define REDCONF_OUTPUT 1 + +#define REDCONF_ASSERTS 1 + +#define REDCONF_BLOCK_SIZE 512U + +#define REDCONF_VOLUME_COUNT 1U + +#define REDCONF_ENDIAN_BIG 0 + +#define REDCONF_ALIGNMENT_SIZE 4U + +#define REDCONF_CRC_ALGORITHM CRC_SLICEBY8 + +#define REDCONF_INODE_BLOCKS 1 + +#define REDCONF_INODE_TIMESTAMPS 1 + +#define REDCONF_ATIME 0 + +#define REDCONF_DIRECT_POINTERS 4U + +#define REDCONF_INDIRECT_POINTERS 32U + +#define REDCONF_BUFFER_COUNT 12U + +#define RedMemCpyUnchecked memcpy + +#define RedMemMoveUnchecked memmove + +#define RedMemSetUnchecked memset + +#define RedMemCmpUnchecked memcmp + +#define RedStrLenUnchecked strlen + +#define RedStrCmpUnchecked strcmp + +#define RedStrNCmpUnchecked strncmp + +#define RedStrNCpyUnchecked strncpy + +#define REDCONF_TRANSACT_DEFAULT (( RED_TRANSACT_CREAT | RED_TRANSACT_MKDIR | RED_TRANSACT_RENAME | RED_TRANSACT_LINK | RED_TRANSACT_UNLINK | RED_TRANSACT_FSYNC | RED_TRANSACT_CLOSE | RED_TRANSACT_VOLFULL | RED_TRANSACT_UMOUNT ) & RED_TRANSACT_MASK) + +#define REDCONF_IMAP_INLINE 0 + +#define REDCONF_IMAP_EXTERNAL 1 + +#define REDCONF_DISCARDS 0 + +#define REDCONF_IMAGE_BUILDER 0 + +#define REDCONF_CHECKER 0 + +#define RED_CONFIG_UTILITY_VERSION 0x2000000U + +#define RED_CONFIG_MINCOMPAT_VER 0x1000200U + +#endif diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/ConfigurationFiles/redtypes.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/ConfigurationFiles/redtypes.h new file mode 100644 index 0000000..8c896db --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/ConfigurationFiles/redtypes.h @@ -0,0 +1,110 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Defines basic types used by Reliance Edge. + + The following types *must* be defined by this header, either directly (using + typedef) or indirectly (by including other headers, such as the C99 headers + stdint.h and stdbool.h): + + - bool: Boolean type, capable of storing true (1) or false (0) + - uint8_t: Unsigned 8-bit integer + - int8_t: Signed 8-bit integer + - uint16_t: Unsigned 16-bit integer + - int16_t: Signed 16-bit integer + - uint32_t: Unsigned 32-bit integer + - int32_t: Signed 32-bit integer + - uint64_t: Unsigned 64-bit integer + - int64_t: Signed 64-bit integer + - uintptr_t: Unsigned integer capable of storing a pointer, preferably the + same size as pointers themselves. + + These types deliberately use the same names as the standard C99 types, so + that if the C99 headers stdint.h and stdbool.h are available, they may be + included here. + + If the user application defines similar types, those may be reused. For + example, suppose there is an application header apptypes.h which defines + types with a similar purpose but different names. That header could be + reused to define the types Reliance Edge needs: + + ~~~{.c} + #include + + typedef BOOL bool; + typedef BYTE uint8_t; + typedef INT8 int8_t; + // And so on... + ~~~ + + If there are neither C99 headers nor suitable types in application headers, + this header should be populated with typedefs that define the required types + in terms of the standard C types. This requires knowledge of the size of + the C types on the target hardware (e.g., how big is an "int" or a pointer). + Below is an example which assumes the target has 8-bit chars, 16-bit shorts, + 32-bit ints, 32-bit pointers, and 64-bit long longs: + + ~~~{.c} + typedef int bool; + typedef unsigned char uint8_t; + typedef signed char int8_t; + typedef unsigned short uint16_t; + typedef short int16_t; + typedef unsigned int uint32_t; + typedef int int32_t; + typedef unsigned long long uint64_t; + typedef long long int64_t; + typedef uint32_t uintptr_t; + ~~~ +*/ +#ifndef REDTYPES_H +#define REDTYPES_H + + +typedef int bool; /**< @brief Boolean type; either true or false. */ + +typedef unsigned __int8 uint8_t; /**< @brief Unsigned 8-bit integer. */ +typedef __int8 int8_t; /**< @brief Signed 8-bit integer. */ + +typedef unsigned __int16 uint16_t; /**< @brief Unsigned 16-bit integer. */ +typedef __int16 int16_t; /**< @brief Signed 16-bit integer. */ + +typedef unsigned __int32 uint32_t; /**< @brief Unsigned 32-bit integer. */ +typedef __int32 int32_t; /**< @brief Signed 32-bit integer. */ + +typedef unsigned __int64 uint64_t; /**< @brief Unsigned 64-bit integer. */ +typedef __int64 int64_t; /**< @brief Signed 64-bit integer. */ + +/** @brief Unsigned integer capable of storing a pointer. +*/ +#ifdef _WIN64 +typedef uint64_t uintptr_t; +#else +typedef uint32_t uintptr_t; +#endif + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/File-Related-CLI-commands.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/File-Related-CLI-commands.c new file mode 100644 index 0000000..523fc8b --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/File-Related-CLI-commands.c @@ -0,0 +1,1525 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Standard includes. */ +#include +#include +#include + +/* FreeRTOS+CLI includes. */ +#include "FreeRTOS_CLI.h" + +/* File system includes. */ +#include +#include + +#ifdef _WINDOWS_ + #define snprintf _snprintf +#endif + +#define cliNEW_LINE "\r\n" + +/******************************************************************************* + * See the URL in the comments within main.c for the location of the online + * documentation. + ******************************************************************************/ + +/* + * Print out information on a single file. + */ +static void prvCreateFileInfoString( char *pcBuffer, REDDIRENT *pxDirent ); + +/* + * Copies an existing file into a newly created file. + */ +static BaseType_t prvPerformCopy( int32_t lSourceFildes, + int32_t lDestinationFiledes, + char *pxWriteBuffer, + size_t xWriteBufferLen ); + +/* + * Implements the DIR command. + */ +static BaseType_t prvDIRCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the DEL command. + */ +static BaseType_t prvDELCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the TYPE command. + */ +static BaseType_t prvTYPECommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the APPEND command. + */ +static BaseType_t prvAPPENDCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the COPY command. + */ +static BaseType_t prvCOPYCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the CREATE command. + */ +static BaseType_t prvCREATECommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the MKDIR command. + */ +static BaseType_t prvMKDIRCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the RENAME command. + */ +static BaseType_t prvRENAMECommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the LINK command. + */ +static BaseType_t prvLINKCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the STAT command. + */ +static BaseType_t prvSTATCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the STATFS command. + */ +static BaseType_t prvSTATFSCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the FORMAT command. + */ +static BaseType_t prvFORMATCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the TRANSACT command. + */ +static BaseType_t prvTRANSACTCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the TRANSMASKGET command. + */ +static BaseType_t prvTRANSMASKGETCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the TRANSMASKSET command. + */ +static BaseType_t prvTRANSMASKSETCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the ABORT command. + */ +static BaseType_t prvABORTCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the TEST command. + */ +static BaseType_t prvTESTFSCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + + +/* Structure that defines the DIR command line command, which lists all the +files in the current directory. */ +static const CLI_Command_Definition_t xDIR = +{ + "dir", /* The command string to type. */ + "\r\ndir :\r\n Lists the files in the named directory\r\n", + prvDIRCommand, /* The function to run. */ + 1 /* One parameter is expected. */ +}; + +/* Structure that defines the TYPE command line command, which prints the +contents of a file to the console. */ +static const CLI_Command_Definition_t xTYPE = +{ + "type", /* The command string to type. */ + "\r\ntype :\r\n Prints file contents to the terminal\r\n", + prvTYPECommand, /* The function to run. */ + 1 /* One parameter is expected. */ +}; + +/* Structure that defines the APPEND command line command, which appends data +to a file. */ +static const CLI_Command_Definition_t xAPPEND = +{ + "append", /* The command string to type. */ + "\r\nappend :\r\n Appends data to a file (created if it does not exist)\r\n", + prvAPPENDCommand, /* The function to run. */ + 3 /* Three parameters are expected. */ +}; + +/* Structure that defines the DEL command line command, which deletes a file. */ +static const CLI_Command_Definition_t xDEL = +{ + "del", /* The command string to type. */ + "\r\ndel :\r\n deletes a file or directory\r\n", + prvDELCommand, /* The function to run. */ + 1 /* One parameter is expected. */ +}; + +/* Structure that defines the COPY command line command, which copies a file. */ +static const CLI_Command_Definition_t xCOPY = +{ + "copy", /* The command string to type. */ + "\r\ncopy :\r\n Copies to \r\n", + prvCOPYCommand, /* The function to run. */ + 2 /* Two parameters are expected. */ +}; + +/* Structure that defines the CREATE command line command, which creates an +empty file. */ +static const CLI_Command_Definition_t xCREATE = +{ + "create", /* The command string to type. */ + "\r\ncreate :\r\n Creates an empty file\r\n", + prvCREATECommand, /* The function to run. */ + 1 /* One parameter is expected. */ +}; + +/* Structure that defines the MKDIR command line command, which creates an +empty directory. */ +static const CLI_Command_Definition_t xMKDIR = +{ + "mkdir", /* The command string to type. */ + "\r\nmkdir :\r\n Creates an empty directory\r\n", + prvMKDIRCommand, /* The function to run. */ + 1 /* One parameter is expected. */ +}; + +/* Structure that defines the RENAME command line command, which renames a file. */ +static const CLI_Command_Definition_t xRENAME = +{ + "rename", /* The command string to type. */ + "\r\nrename :\r\n Rename to \r\n", + prvRENAMECommand, /* The function to run. */ + 2 /* Two parameters are expected. */ +}; + +/* Structure that defines the LINK command line command, which creates a hard +link. */ +static const CLI_Command_Definition_t xLINK = +{ + "link", /* The command string to type. */ + "\r\nlink :\r\n Create hard link pointing at \r\n", + prvLINKCommand, /* The function to run. */ + 2 /* Two parameters are expected. */ +}; + +/* Structure that defines the STAT command line command, which shows various +information about a file. */ +static const CLI_Command_Definition_t xSTAT = +{ + "stat", /* The command string to type. */ + "\r\nstat :\r\n Show file information\r\n", + prvSTATCommand, /* The function to run. */ + 1 /* One parameter is expected. */ +}; + +/* Structure that defines the STATFS command line command, which shows various +file system information. */ +static const CLI_Command_Definition_t xSTATFS = +{ + "statfs", /* The command string to type. */ + "\r\nstatfs:\r\n Show file system information.\r\n", + prvSTATFSCommand, /* The function to run. */ + 0 /* No parameters are expected. */ +}; + +/* Structure that defines the FORMAT command line command, which re-formats the +file system. */ +static const CLI_Command_Definition_t xFORMAT = +{ + "format", /* The command string to type. */ + "\r\nformat:\r\n Re-formats the file system volume. ALL FILES WILL BE DELETED!\r\n", + prvFORMATCommand, /* The function to run. */ + 0 /* No parameters are expected. */ +}; + +/* Structure that defines the TRANSACT command line command, which commits a +transaction point. */ +static const CLI_Command_Definition_t xTRANSACT = +{ + "transact", /* The command string to type. */ + "\r\ntransact:\r\n Commit a Reliance Edge transaction point\r\n", + prvTRANSACTCommand, /* The function to run. */ + 0 /* No parameters are expected. */ +}; + +/* Structure that defines the TRANSMASKGET command line command, which retrieves +the current automatic transaction event mask. */ +static const CLI_Command_Definition_t xTRANSMASKGET = +{ + "transmaskget", /* The command string to type. */ + "\r\ntransmaskget:\r\n Retrieve the Reliance Edge automatic transaction mask\r\n", + prvTRANSMASKGETCommand, /* The function to run. */ + 0 /* No parameters are expected. */ +}; + +/* Structure that defines the TRANSMASKSET command line command, which sets the +automatic transaction event mask. */ +static const CLI_Command_Definition_t xTRANSMASKSET = +{ + "transmaskset", /* The command string to type. */ + "\r\ntransmaskset :\r\n Set the Reliance Edge automatic transaction mask\r\n", + prvTRANSMASKSETCommand, /* The function to run. */ + 1 /* One parameter is expected. */ +}; + +/* Structure that defines the ABORT command line command, which rolls back +changes which have not been transacted. */ +static const CLI_Command_Definition_t xABORT = +{ + "abort", /* The command string to type. */ + "\r\nabort:\r\n Roll back all changes not part of the last transaction point\r\n", + prvABORTCommand, /* The function to run. */ + 0 /* No parameters are expected. */ +}; + +/* Structure that defines the TEST-FS command line command, which executes some +file system driver tests. */ +static const CLI_Command_Definition_t xTEST_FS = +{ + "test-fs", /* The command string to type. */ + "\r\ntest-fs:\r\n Executes file system tests. ALL FILES WILL BE DELETED!\r\n", + prvTESTFSCommand, /* The function to run. */ + 0 /* No parameters are expected. */ +}; + +/*-----------------------------------------------------------*/ + +void vRegisterFileSystemCLICommands( void ) +{ + /* Register all the command line commands defined immediately above. */ + FreeRTOS_CLIRegisterCommand( &xDIR ); + FreeRTOS_CLIRegisterCommand( &xTYPE ); + FreeRTOS_CLIRegisterCommand( &xAPPEND ); + FreeRTOS_CLIRegisterCommand( &xDEL ); + FreeRTOS_CLIRegisterCommand( &xCOPY ); + FreeRTOS_CLIRegisterCommand( &xCREATE ); + FreeRTOS_CLIRegisterCommand( &xMKDIR ); + FreeRTOS_CLIRegisterCommand( &xRENAME ); + FreeRTOS_CLIRegisterCommand( &xLINK ); + FreeRTOS_CLIRegisterCommand( &xSTAT ); + FreeRTOS_CLIRegisterCommand( &xSTATFS ); + FreeRTOS_CLIRegisterCommand( &xFORMAT ); + FreeRTOS_CLIRegisterCommand( &xTRANSACT ); + FreeRTOS_CLIRegisterCommand( &xTRANSMASKGET ); + FreeRTOS_CLIRegisterCommand( &xTRANSMASKSET ); + FreeRTOS_CLIRegisterCommand( &xABORT ); + FreeRTOS_CLIRegisterCommand( &xTEST_FS ); +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvDIRCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +static REDDIR *pxDir = NULL; +REDDIRENT *pxDirent; +const char *pcParameter; +BaseType_t xParameterStringLength, xReturn = pdFALSE; + + /* This assumes pcWriteBuffer is long enough. */ + ( void ) pcCommandString; + + /* Ensure the buffer leaves space for the \r\n. */ + configASSERT( xWriteBufferLen > ( strlen( cliNEW_LINE ) * 2 ) ); + xWriteBufferLen -= strlen( cliNEW_LINE ); + + if( pxDir == NULL ) + { + /* Retrieve the directory to DIR. */ + pcParameter = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 1, /* Return the first parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcParameter ); + + /* This is the first time this function has been executed since the Dir + command was run. Open the directory. */ + pxDir = red_opendir( pcParameter ); + } + + if( pxDir ) + { + /* red_readdir() returns NULL either on error or upon reaching the + end of the directory. Clear errno so these conditions can be + distinguished. */ + red_errno = 0; + pxDirent = red_readdir( pxDir ); + + if( pxDirent ) + { + prvCreateFileInfoString( pcWriteBuffer, pxDirent ); + xReturn = pdPASS; + } + else if( red_errno == 0 ) + { + /* There are no more files. Close the directory. */ + red_closedir( pxDir ); + pxDir = NULL; + + /* No string to return. */ + pcWriteBuffer[ 0 ] = 0x00; + } + else + { + snprintf( pcWriteBuffer, xWriteBufferLen, "Error %d reading directory.", ( int ) red_errno ); + } + } + else + { + /* User-friendly messages for common errors. */ + switch( red_errno ) + { + case RED_ENOENT : + snprintf( pcWriteBuffer, xWriteBufferLen, "Directory not found." ); + break; + + case RED_ENOTDIR : + snprintf( pcWriteBuffer, xWriteBufferLen, "Directory not found or not a directory." ); + break; + + default : + snprintf( pcWriteBuffer, xWriteBufferLen, "Error %d opening directory.", ( int ) red_errno ); + break; + } + } + + strcat( pcWriteBuffer, cliNEW_LINE ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTYPECommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *pcParameter; +BaseType_t xParameterStringLength, xReturn = pdTRUE; +static int32_t lFildes = -1; +REDSTAT finfo; +int32_t lStatus, lBytesRead; +size_t xColumns = 50U; + + /* Ensure there is always a null terminator after each character written. */ + memset( pcWriteBuffer, 0x00, xWriteBufferLen ); + + /* Ensure the buffer leaves space for the \r\n. */ + configASSERT( xWriteBufferLen > ( strlen( cliNEW_LINE ) * 2 ) ); + xWriteBufferLen -= strlen( cliNEW_LINE ); + + if( xWriteBufferLen < xColumns ) + { + /* Ensure the loop that uses xColumns as an end condition does not + write off the end of the buffer. */ + xColumns = xWriteBufferLen; + } + + if( lFildes == -1 ) + { + /* The file has not been opened yet. Find the file name. */ + pcParameter = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 1, /* Return the first parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcParameter ); + + /* Attempt to open the requested file. */ + lFildes = red_open( pcParameter, RED_O_RDONLY ); + if( lFildes == -1 ) + { + /* User-friendly messages for common errors. */ + switch( red_errno ) + { + case RED_ENOENT : + case RED_ENOTDIR : + snprintf( pcWriteBuffer, xWriteBufferLen, "File not found." ); + break; + + default : + snprintf( pcWriteBuffer, xWriteBufferLen, "Error %d opening file.", ( int ) red_errno ); + break; + } + } + else + { + /* Make sure this is a file, not a directory. */ + lStatus = red_fstat( lFildes, &finfo ); + if( lStatus == 0 ) + { + if( RED_S_ISDIR( finfo.st_mode ) ) + { + snprintf( pcWriteBuffer, xWriteBufferLen, "Cannot TYPE a directory." ); + red_close( lFildes ); + lFildes = -1; + } + } + else + { + snprintf( pcWriteBuffer, xWriteBufferLen, "Error %d querying file.", ( int ) red_errno ); + red_close( lFildes ); + lFildes = -1; + } + } + } + + if( lFildes != -1 ) + { + /* Read the next chunk of data from the file. */ + lBytesRead = red_read( lFildes, pcWriteBuffer, xColumns ); + + if( lBytesRead < ( int32_t ) xColumns ) + { + /* Error or no more characters to return. */ + red_close( lFildes ); + lFildes = -1; + } + } + + if( lFildes == -1 ) + { + /* Either the file was not opened, or all the data from the file has + been returned and the file is now closed. */ + xReturn = pdFALSE; + } + + strcat( pcWriteBuffer, cliNEW_LINE ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvAPPENDCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +char *pcFileName = NULL; +const char *pcCharacter = NULL, *pcLength; +BaseType_t xParameterStringLength, xGoodParameters = pdTRUE; +int32_t lFildes, lAppendLength = -1, lThisWrite, lTotalWritten, lBytesWritten; + + /* This function assumes xWriteBufferLen is large enough! */ + ( void ) xWriteBufferLen; + + /* Find the length to write. */ + pcLength = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 3, /* Return the third parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + configASSERT( pcLength ); + + /* Convert the string into a number. */ + lAppendLength = RedAtoI( pcLength ); + if( lAppendLength < 0 ) + { + strcpy( pcWriteBuffer, "Third parameter cannot be a negative number." ); + xGoodParameters = pdFALSE; + } + + if( xGoodParameters ) + { + /* Find the character to write. */ + pcCharacter = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 2, /* Return the second parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + configASSERT( pcCharacter ); + + if( xParameterStringLength != 1 ) + { + strcpy( pcWriteBuffer, "Second parameter must be a single character." ); + xGoodParameters = pdFALSE; + } + } + + if( xGoodParameters ) + { + /* Find the file name. */ + pcFileName = ( char * ) FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 1, /* Return the first parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + configASSERT( pcFileName ); + + /* Terminate the string. */ + pcFileName[ xParameterStringLength ] = 0x00; + } + + if( xGoodParameters ) + { + /* Attempt to open the requested file. */ + lFildes = red_open( pcFileName, RED_O_WRONLY|RED_O_APPEND|RED_O_CREAT ); + + if( lFildes == -1 ) + { + /* User-friendly messages for common errors. */ + switch( red_errno ) + { + case RED_ENOENT : + case RED_ENOTDIR : + strcpy( pcWriteBuffer, "Bad file path." ); + break; + + case RED_EISDIR : + strcpy( pcWriteBuffer, "Cannot append to a directory." ); + break; + + default : + sprintf( pcWriteBuffer, "Error %d opening file.", ( int ) red_errno ); + break; + } + } + else + { + /* Put the requested character into the buffer. */ + memset( pcWriteBuffer, pcCharacter[0], xWriteBufferLen ); + + /* Append the data. */ + for( lTotalWritten = 0; lTotalWritten < lAppendLength; lTotalWritten += lThisWrite ) + { + lThisWrite = lAppendLength - lTotalWritten; + if( lThisWrite > ( int32_t ) xWriteBufferLen ) + { + lThisWrite = ( int32_t ) xWriteBufferLen; + } + + lBytesWritten = red_write( lFildes, pcWriteBuffer, lThisWrite ); + if( lBytesWritten == -1 ) + { + /* User-friendly messages for common errors. */ + switch( red_errno ) + { + case RED_ENOSPC : + strcpy( pcWriteBuffer, "Out of disk space." ); + break; + + default : + sprintf( pcWriteBuffer, "Error %d writing to file.", ( int ) red_errno ); + break; + } + + break; + } + else if( lBytesWritten != lThisWrite ) + { + /* Some data was written, but not all of it. This only + happens when the disk is full or the file reached its + maximum size. That latter is unlikely in this demo. */ + strcpy( pcWriteBuffer, "Out of disk space." ); + break; + } + } + + if( lTotalWritten == lAppendLength ) + { + strcpy( pcWriteBuffer, "Append successful." ); + } + + red_close( lFildes ); + } + } + + strcat( pcWriteBuffer, cliNEW_LINE ); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvDELCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *pcParameter; +BaseType_t xParameterStringLength; +int32_t lStatus; + + /* This function assumes xWriteBufferLen is large enough! */ + ( void ) xWriteBufferLen; + + /* Obtain the parameter string. */ + pcParameter = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 1, /* Return the first parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcParameter ); + + /* Attempt to delete the file or directory. */ + lStatus = red_unlink( pcParameter ); + + if( lStatus == 0 ) + { + sprintf( pcWriteBuffer, "%s was deleted", pcParameter ); + } + else + { + /* User-friendly messages for common errors. */ + switch( red_errno ) + { + case RED_ENOTDIR : + case RED_ENOENT : + sprintf( pcWriteBuffer, "File not found." ); + break; + + case RED_ENOTEMPTY : + sprintf( pcWriteBuffer, "Cannot remove directory: not empty." ); + break; + + default : + sprintf( pcWriteBuffer, "Error %d deleting file.", ( int ) red_errno ); + break; + } + } + + strcat( pcWriteBuffer, cliNEW_LINE ); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvCOPYCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +char *pcSourceFile; +const char *pcDestinationFile; +BaseType_t xParameterStringLength; +int32_t lSourceFildes, lDestinationFildes; + + /* Obtain the name of the destination file. */ + pcDestinationFile = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 2, /* Return the second parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcDestinationFile ); + + /* Obtain the name of the source file. */ + pcSourceFile = ( char * ) FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 1, /* Return the first parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcSourceFile ); + + /* Terminate the string. */ + pcSourceFile[ xParameterStringLength ] = 0x00; + + /* See if the source file exists, openm it if it does. */ + lSourceFildes = red_open( pcSourceFile, RED_O_RDONLY ); + + if( lSourceFildes == -1 ) + { + sprintf( pcWriteBuffer, "Source file does not exist" ); + } + else + { + /* Create the destination file, error if it already exists. */ + lDestinationFildes = red_open( pcDestinationFile, RED_O_CREAT|RED_O_EXCL|RED_O_WRONLY ); + + if( lDestinationFildes == -1 ) + { + sprintf( pcWriteBuffer, "Error: Destination file already exists" ); + } + else + { + if( prvPerformCopy( lSourceFildes, lDestinationFildes, pcWriteBuffer, xWriteBufferLen ) == pdPASS ) + { + sprintf( pcWriteBuffer, "Copy made" ); + } + else + { + sprintf( pcWriteBuffer, "Error during copy" ); + } + + red_close( lDestinationFildes ); + } + + red_close( lSourceFildes ); + } + + strcat( pcWriteBuffer, cliNEW_LINE ); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvCREATECommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *pcParameter; +BaseType_t xParameterStringLength; +int32_t lFildes; + + /* This function assumes xWriteBufferLen is large enough! */ + ( void ) xWriteBufferLen; + + /* Obtain the parameter string. */ + pcParameter = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 1, /* Return the first parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcParameter ); + + /* Attempt to create the file. */ + lFildes = red_open( pcParameter, RED_O_CREAT|RED_O_EXCL|RED_O_RDWR ); + + if( lFildes != -1 ) + { + sprintf( pcWriteBuffer, "%s was created", pcParameter ); + red_close( lFildes ); + } + else + { + /* User-friendly messages for common errors. */ + switch( red_errno ) + { + case RED_ENOTDIR : + case RED_ENOENT : + sprintf( pcWriteBuffer, "Bad file path." ); + break; + + case RED_EEXIST : + sprintf( pcWriteBuffer, "File already exists." ); + break; + + default : + sprintf( pcWriteBuffer, "Error %d creating file.", ( int ) red_errno ); + break; + } + } + + strcat( pcWriteBuffer, cliNEW_LINE ); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvMKDIRCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *pcParameter; +BaseType_t xParameterStringLength; +int32_t lStatus; + + /* This function assumes xWriteBufferLen is large enough! */ + ( void ) xWriteBufferLen; + + /* Obtain the parameter string. */ + pcParameter = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 1, /* Return the first parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcParameter ); + + /* Attempt to create the file. */ + lStatus = red_mkdir( pcParameter ); + + if( lStatus == 0 ) + { + sprintf( pcWriteBuffer, "%s was created", pcParameter ); + } + else + { + /* User-friendly messages for common errors. */ + switch( red_errno ) + { + case RED_ENOTDIR : + case RED_ENOENT : + sprintf( pcWriteBuffer, "Bad file path." ); + break; + + case RED_EEXIST : + sprintf( pcWriteBuffer, "Directory already exists." ); + break; + + default : + sprintf( pcWriteBuffer, "Error %d creating directory.", ( int ) red_errno ); + break; + } + } + + strcat( pcWriteBuffer, cliNEW_LINE ); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvRENAMECommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *pcDestinationFile; +char *pcSourceFile; +BaseType_t xParameterStringLength; +int32_t lStatus; + + /* This function assumes xWriteBufferLen is large enough! */ + ( void ) xWriteBufferLen; + + /* Obtain the name of the destination file. */ + pcDestinationFile = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 2, /* Return the second parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcDestinationFile ); + + /* Obtain the name of the source file. */ + pcSourceFile = ( char * ) FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 1, /* Return the first parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcSourceFile ); + + /* Terminate the string. */ + pcSourceFile[ xParameterStringLength ] = 0x00; + + /* Attempt to rename the file. */ + lStatus = red_rename( pcSourceFile, pcDestinationFile ); + + if( lStatus == 0 ) + { + sprintf( pcWriteBuffer, "%s was renamed to %s", pcSourceFile, pcDestinationFile ); + } + else + { + /* User-friendly messages for common errors. */ + switch( red_errno ) + { + case RED_ENOTDIR : + case RED_ENOENT : + case RED_EISDIR : + sprintf( pcWriteBuffer, "Bad file path." ); + break; + + /* This will only be seen if POSIX rename is disabled. */ + case RED_EEXIST : + sprintf( pcWriteBuffer, "Destination already exists." ); + break; + + default : + sprintf( pcWriteBuffer, "Error %d renaming file.", ( int ) red_errno ); + break; + } + } + + strcat( pcWriteBuffer, cliNEW_LINE ); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvLINKCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *pcDestinationFile; +char *pcSourceFile; +BaseType_t xParameterStringLength; +int32_t lStatus; + + /* This function assumes xWriteBufferLen is large enough! */ + ( void ) xWriteBufferLen; + + /* Obtain the name of the destination file. */ + pcDestinationFile = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 2, /* Return the second parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcDestinationFile ); + + /* Obtain the name of the source file. */ + pcSourceFile = ( char * ) FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 1, /* Return the first parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcSourceFile ); + + /* Terminate the string. */ + pcSourceFile[ xParameterStringLength ] = 0x00; + + /* Attempt to create the hard link. */ + lStatus = red_link( pcSourceFile, pcDestinationFile ); + + if( lStatus == 0 ) + { + sprintf( pcWriteBuffer, "%s was linked to %s", pcDestinationFile, pcSourceFile ); + } + else + { + /* User-friendly messages for common errors. */ + switch( red_errno ) + { + case RED_ENOTDIR : + case RED_ENOENT : + sprintf( pcWriteBuffer, "Bad file path." ); + break; + + case RED_EPERM : + sprintf( pcWriteBuffer, "Cannot link a directory." ); + break; + + case RED_EMLINK : + sprintf( pcWriteBuffer, "Too many hard links." ); + break; + + default : + sprintf( pcWriteBuffer, "Error %d linking file.", ( int ) red_errno ); + break; + } + } + + strcat( pcWriteBuffer, cliNEW_LINE ); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvSTATCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *pcParameter, *pcModeString; +BaseType_t xParameterStringLength; +REDSTAT finfo; +int32_t lFildes, lStatus; + + /* Ensure the buffer leaves space for the \r\n. */ + configASSERT( xWriteBufferLen > ( strlen( cliNEW_LINE ) * 2 ) ); + xWriteBufferLen -= strlen( cliNEW_LINE ); + + /* Find the file name. */ + pcParameter = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 1, /* Return the first parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcParameter ); + + /* Attempt to open the requested file. */ + lFildes = red_open( pcParameter, RED_O_RDONLY ); + if( lFildes == -1 ) + { + /* User-friendly messages for common errors. */ + switch( red_errno ) + { + case RED_ENOENT : + case RED_ENOTDIR : + snprintf( pcWriteBuffer, xWriteBufferLen, "File not found." ); + break; + + default : + snprintf( pcWriteBuffer, xWriteBufferLen, "Error %d opening file.", ( int ) red_errno ); + break; + } + } + else + { + lStatus = red_fstat( lFildes, &finfo ); + if( lStatus == 0 ) + { + if( RED_S_ISDIR( finfo.st_mode ) ) + { + pcModeString = "dir"; + } + else + { + pcModeString = "file"; + } + + snprintf( pcWriteBuffer, xWriteBufferLen, "ino=%lu mode=0x%04x(%s) nlink=%x size=%lu blocks=%lu", + ( unsigned long ) finfo.st_ino, ( unsigned ) finfo.st_mode, pcModeString, + ( unsigned ) finfo.st_nlink, (unsigned long) finfo.st_size, (unsigned long) finfo.st_blocks ); + } + else + { + snprintf( pcWriteBuffer, xWriteBufferLen, "Error %d querying file.", ( int ) red_errno ); + } + + red_close( lFildes ); + } + + strcat( pcWriteBuffer, cliNEW_LINE ); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvSTATFSCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +REDSTATFS fsinfo; +int32_t lStatus; + + /* Avoid compiler warnings. */ + ( void ) pcCommandString; + + /* Ensure the buffer leaves space for the \r\n. */ + configASSERT( xWriteBufferLen > ( strlen( cliNEW_LINE ) * 2 ) ); + xWriteBufferLen -= strlen( cliNEW_LINE ); + + lStatus = red_statvfs( "", &fsinfo ); + + if( lStatus == -1 ) + { + snprintf( pcWriteBuffer, xWriteBufferLen, "Error %d querying file system.", ( int ) red_errno ); + } + else + { + snprintf( pcWriteBuffer, xWriteBufferLen, + "Block size: %lu\r\n" + "Block count: %lu\r\n" + "Free blocks: %lu\r\n" + "Inode count: %lu\r\n" + "Free inodes: %lu\r\n", + ( unsigned long ) fsinfo.f_bsize, ( unsigned long ) fsinfo.f_blocks, + ( unsigned long ) fsinfo.f_bfree, ( unsigned long ) fsinfo.f_files, + ( unsigned long ) fsinfo.f_ffree ); + } + + strcat( pcWriteBuffer, cliNEW_LINE ); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvFORMATCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +int32_t lStatus; + + /* Avoid compiler warnings. */ + ( void ) pcCommandString; + + /* This function assumes xWriteBufferLen is large enough! */ + ( void ) xWriteBufferLen; + + /* File system volumes cannot be formatted while mounted. */ + lStatus = red_umount( "" ); + if( lStatus == -1 ) + { + sprintf( pcWriteBuffer, "Error %d during unmount.", ( int ) red_errno ); + } + else + { + /* Re-format the file system volume. */ + lStatus = red_format( "" ); + + if( lStatus == -1 ) + { + sprintf( pcWriteBuffer, "Error %d during format.", ( int ) red_errno ); + } + else + { + /* Mount again so that other commands will work properly. */ + lStatus = red_mount( "" ); + + if( lStatus == -1 ) + { + sprintf( pcWriteBuffer, "Error %d during mount.", ( int ) red_errno ); + } + else + { + strcpy( pcWriteBuffer, "Format successful." ); + } + } + } + + strcat( pcWriteBuffer, cliNEW_LINE ); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTRANSACTCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +int32_t lStatus; + + /* Avoid compiler warnings. */ + ( void ) pcCommandString; + + /* This function assumes xWriteBufferLen is large enough! */ + ( void ) xWriteBufferLen; + + /* Save the original transaction mask settings. */ + lStatus = red_transact( "" ); + + if( lStatus == -1 ) + { + sprintf( pcWriteBuffer, "Error %d during transaction point.", ( int ) red_errno ); + } + else + { + strcpy( pcWriteBuffer, "Transaction point successful." ); + } + + strcat( pcWriteBuffer, cliNEW_LINE ); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTRANSMASKGETCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +uint32_t ulEventMask; +int32_t lStatus; + + /* Avoid compiler warnings. */ + ( void ) pcCommandString; + + /* Ensure the buffer leaves space for the \r\n. */ + configASSERT( xWriteBufferLen > ( strlen( cliNEW_LINE ) * 2 ) ); + xWriteBufferLen -= strlen( cliNEW_LINE ); + + lStatus = red_gettransmask( "", &ulEventMask ); + if( lStatus == -1 ) + { + snprintf( pcWriteBuffer, xWriteBufferLen, "Error %d retrieving automatic transaction event mask.", ( int ) red_errno ); + } + else + { + snprintf( pcWriteBuffer, xWriteBufferLen, + "Current automatic transaction event mask: 0x%04lx\r\n" + "RED_TRANSACT_UMOUNT (0x0001): %s\r\n" + "RED_TRANSACT_CREAT (0x0002): %s\r\n" + "RED_TRANSACT_UNLINK (0x0004): %s\r\n" + "RED_TRANSACT_MKDIR (0x0008): %s\r\n" + "RED_TRANSACT_RENAME (0x0010): %s\r\n" + "RED_TRANSACT_LINK (0x0020): %s\r\n" + "RED_TRANSACT_CLOSE (0x0040): %s\r\n" + "RED_TRANSACT_WRITE (0x0080): %s\r\n" + "RED_TRANSACT_FSYNC (0x0100): %s\r\n" + "RED_TRANSACT_TRUNCATE (0x0200): %s\r\n" + "RED_TRANSACT_VOLFULL (0x0400): %s\r\n", + ( unsigned long ) ulEventMask, + ( ulEventMask & RED_TRANSACT_UMOUNT ) ? "Enabled" : "Disabled", + ( ulEventMask & RED_TRANSACT_CREAT ) ? "Enabled" : "Disabled", + ( ulEventMask & RED_TRANSACT_UNLINK ) ? "Enabled" : "Disabled", + ( ulEventMask & RED_TRANSACT_MKDIR ) ? "Enabled" : "Disabled", + ( ulEventMask & RED_TRANSACT_RENAME ) ? "Enabled" : "Disabled", + ( ulEventMask & RED_TRANSACT_LINK ) ? "Enabled" : "Disabled", + ( ulEventMask & RED_TRANSACT_CLOSE ) ? "Enabled" : "Disabled", + ( ulEventMask & RED_TRANSACT_WRITE ) ? "Enabled" : "Disabled", + ( ulEventMask & RED_TRANSACT_FSYNC ) ? "Enabled" : "Disabled", + ( ulEventMask & RED_TRANSACT_TRUNCATE ) ? "Enabled" : "Disabled", + ( ulEventMask & RED_TRANSACT_VOLFULL ) ? "Enabled" : "Disabled" ); + } + + strcat( pcWriteBuffer, cliNEW_LINE ); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTRANSMASKSETCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *pcParameter; +BaseType_t xParameterStringLength; +uint32_t ulEventMask; +int32_t lStatus; + + /* Ensure the buffer leaves space for the \r\n. */ + configASSERT( xWriteBufferLen > ( strlen( cliNEW_LINE ) * 2 ) ); + xWriteBufferLen -= strlen( cliNEW_LINE ); + + /* Obtain the parameter string. */ + pcParameter = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 1, /* Return the first parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcParameter ); + + if( ( pcParameter[0] == '0' ) && ( ( pcParameter[1] == 'x' ) || ( pcParameter[1] == 'X' ) ) ) + { + pcParameter += 2; + } + + /* Convert the argument into a value. */ + RedHtoUL( pcParameter, &ulEventMask ); + + /* Set the new transaction mask. */ + lStatus = red_settransmask( "", ulEventMask ); + if( lStatus == -1 ) + { + /* User-friendly messages for common errors. */ + switch( red_errno ) + { + case RED_EINVAL: + snprintf( pcWriteBuffer, xWriteBufferLen, "Invalid bits in transaction mask." ); + break; + + default : + snprintf( pcWriteBuffer, xWriteBufferLen, "Error %d setting transaction mask.", ( int ) red_errno ); + break; + } + } + else + { + snprintf( pcWriteBuffer, xWriteBufferLen, + "Successfully set automatic transaction mask. Enabled events:\r\n" + "RED_TRANSACT_UMOUNT (0x0001): %s\r\n" + "RED_TRANSACT_CREAT (0x0002): %s\r\n" + "RED_TRANSACT_UNLINK (0x0004): %s\r\n" + "RED_TRANSACT_MKDIR (0x0008): %s\r\n" + "RED_TRANSACT_RENAME (0x0010): %s\r\n" + "RED_TRANSACT_LINK (0x0020): %s\r\n" + "RED_TRANSACT_CLOSE (0x0040): %s\r\n" + "RED_TRANSACT_WRITE (0x0080): %s\r\n" + "RED_TRANSACT_FSYNC (0x0100): %s\r\n" + "RED_TRANSACT_TRUNCATE (0x0200): %s\r\n" + "RED_TRANSACT_VOLFULL (0x0400): %s\r\n", + ( ulEventMask & RED_TRANSACT_UMOUNT ) ? "Enabled" : "Disabled", + ( ulEventMask & RED_TRANSACT_CREAT ) ? "Enabled" : "Disabled", + ( ulEventMask & RED_TRANSACT_UNLINK ) ? "Enabled" : "Disabled", + ( ulEventMask & RED_TRANSACT_MKDIR ) ? "Enabled" : "Disabled", + ( ulEventMask & RED_TRANSACT_RENAME ) ? "Enabled" : "Disabled", + ( ulEventMask & RED_TRANSACT_LINK ) ? "Enabled" : "Disabled", + ( ulEventMask & RED_TRANSACT_CLOSE ) ? "Enabled" : "Disabled", + ( ulEventMask & RED_TRANSACT_WRITE ) ? "Enabled" : "Disabled", + ( ulEventMask & RED_TRANSACT_FSYNC ) ? "Enabled" : "Disabled", + ( ulEventMask & RED_TRANSACT_TRUNCATE ) ? "Enabled" : "Disabled", + ( ulEventMask & RED_TRANSACT_VOLFULL ) ? "Enabled" : "Disabled" ); + } + + strcat( pcWriteBuffer, cliNEW_LINE ); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvABORTCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +uint32_t ulEventMask; +int32_t lStatus; + + /* Avoid compiler warnings. */ + ( void ) pcCommandString; + + /* This function assumes xWriteBufferLen is large enough! */ + ( void ) xWriteBufferLen; + + /* Save the original transaction mask settings. */ + lStatus = red_gettransmask( "", &ulEventMask ); + + if( lStatus == -1 ) + { + sprintf( pcWriteBuffer, "Error %d querying transaction mask.", ( int ) red_errno ); + } + else + { + /* Make it so that red_umount() will not automatically commit a new + transaction point. */ + lStatus = red_settransmask( "", ulEventMask & ~( ( uint32_t ) RED_TRANSACT_UMOUNT ) ); + + if( lStatus == -1 ) + { + sprintf( pcWriteBuffer, "Error %d setting transaction mask.", ( int ) red_errno ); + } + else + { + /* Unmount. Since red_umount() will not transact, all changes which + were not already transacted are rolled back. */ + lStatus = red_umount( "" ); + + if( lStatus == -1 ) + { + sprintf( pcWriteBuffer, "Error %d during unmount.", ( int ) red_errno ); + } + else + { + /* Mount. Mount always starts from the last transaction point. */ + lStatus = red_mount( "" ); + + if( lStatus == -1 ) + { + sprintf( pcWriteBuffer, "Error %d during mount.", ( int ) red_errno ); + } + else + { + strcpy( pcWriteBuffer, "Working state changes succesfully aborted." ); + } + } + + /* Restore the original transaction mask settings. */ + red_settransmask( "", ulEventMask ); + } + } + + strcat( pcWriteBuffer, cliNEW_LINE ); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTESTFSCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +UBaseType_t uxOriginalPriority; +FSSTRESSPARAM param; + + /* Avoid compiler warnings. */ + ( void ) xWriteBufferLen; + ( void ) pcCommandString; + + /* Limitations in the interaction with the Windows TCP/IP stack require + the command console to run at the idle priority. Raise the priority for + the duration of the tests to ensure there are not multiple switches to the + idle task as in the simulated environment the idle task hook function may + include a (relatively) long delay. */ + uxOriginalPriority = uxTaskPriorityGet( NULL ); + vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 ); + + /* Delete all files to avoid inteferring with the test. */ + red_umount( "" ); + red_format( "" ); + red_mount( "" ); + + FsstressDefaultParams(¶m); + param.fVerbose = pdTRUE; + param.ulNops = 10000; + param.ulSeed = 1; + FsstressStart(¶m); + + /* Clean up after the test. */ + red_umount( "" ); + red_format( "" ); + red_mount( "" ); + + /* Reset back to the original priority. */ + vTaskPrioritySet( NULL, uxOriginalPriority ); + + sprintf( pcWriteBuffer, "%s", "Test results were sent to Windows console" ); + strcat( pcWriteBuffer, cliNEW_LINE ); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvPerformCopy( int32_t lSourceFildes, + int32_t lDestinationFiledes, + char *pxWriteBuffer, + size_t xWriteBufferLen ) +{ +int32_t lBytesRead; +BaseType_t xReturn = pdPASS; + + /* Assuming both files are at offset zero. */ + + for( ;; ) + { + /* Read the next block of data. */ + lBytesRead = red_read( lSourceFildes, pxWriteBuffer, xWriteBufferLen ); + if( lBytesRead <= 0 ) + { + if( lBytesRead == -1) + { + /* Error reading from file. */ + xReturn = pdFAIL; + } + else + { + /* No error: reached end of file, time to stop. */ + } + + break; + } + + /* Write the block of data to the end of the file. */ + if( red_write( lDestinationFiledes, pxWriteBuffer, lBytesRead ) != lBytesRead ) + { + xReturn = pdFAIL; + break; + } + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static void prvCreateFileInfoString( char *pcBuffer, REDDIRENT *pxDirent ) +{ +const char *pcFile = "file", *pcDirectory = "directory"; +const char *pcAttrib; + + /* Point pcAttrib to a string that describes the file. */ + if( RED_S_ISDIR(pxDirent->d_stat.st_mode) ) + { + pcAttrib = pcDirectory; + } + else + { + pcAttrib = pcFile; + } + + /* Create a string that includes the file name, the file size and the + attributes string. */ + sprintf( pcBuffer, "%s [%s] [size=%lld]", pxDirent->d_name, pcAttrib, pxDirent->d_stat.st_size ); +} diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/File-system-demo.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/File-system-demo.c new file mode 100644 index 0000000..04a8a65 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/File-system-demo.c @@ -0,0 +1,289 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/******************************************************************************* + * See the URL in the comments within main.c for the location of the online + * documentation. + ******************************************************************************/ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" + +/* File system includes. */ +#include + +/* The number of bytes read/written to the example files at a time. */ +#define fsRAM_BUFFER_SIZE 200 + +/* The volume prefix is an empty string, for convenience since there is only one +volume in this demo. +*/ +#define fsVOLUME_NAME "" + +/*-----------------------------------------------------------*/ + +/* + * Creates and verifies different files on the volume, demonstrating the use of + * various different API functions. + */ +void vCreateAndVerifySampleFiles( void ); + +/* + * Create a set of example files in the root directory of the volume using + * f_write(). + */ +static void prvCreateDemoFiles( void ); + +/* + * Use f_read() to read back and verify the files that were created by + * prvCreateDemoFiles(). + */ +static void prvVerifyDemoFiles( void ); + +/*-----------------------------------------------------------*/ + +/* A buffer used to both create content to write to disk, and read content back +from a disk. Note there is no mutual exclusion on this buffer. */ +static char cRAMBuffer[ fsRAM_BUFFER_SIZE ]; + +/* Names of directories that are created. */ +static const char *pcDirectory1 = "/SUB1", *pcDirectory2 = "/SUB1/SUB2"; + +/*-----------------------------------------------------------*/ + +void vCreateAndVerifySampleFiles( void ) +{ +int32_t lStatus; + + /* First initialize the Reliance Edge driver. */ + lStatus = red_init(); + + /* Format the volume. */ + if( lStatus == 0 ) + { + lStatus = red_format( fsVOLUME_NAME ); + } + + /* Mount the volume. */ + if( lStatus == 0 ) + { + lStatus = red_mount( fsVOLUME_NAME ); + } + + if( lStatus == 0 ) + { + /* Create a set of files using red_write(). */ + prvCreateDemoFiles(); + + /* Read back and verify the files that were created using red_write(). */ + prvVerifyDemoFiles(); + } +} +/*-----------------------------------------------------------*/ + +static void prvCreateDemoFiles( void ) +{ +BaseType_t xFileNumber, xWriteNumber; +char cFilePath[ 64 ]; +const BaseType_t xMaxFiles = 5; +uint32_t ulEventMask; +int32_t lBytesWritten, lFildes, lStatus; +int iByte; + + /* Save the current transaction point settings. */ + lStatus = red_gettransmask( fsVOLUME_NAME, &ulEventMask ); + configASSERT( lStatus == 0 ); + + /* Disable automatic transaction points so that all of the files can be + created in one atomic operation. */ + lStatus = red_settransmask( fsVOLUME_NAME, RED_TRANSACT_MANUAL ); + configASSERT( lStatus == 0 ); + + /* Create xMaxFiles files. Each created file will be + ( xFileNumber * fsRAM_BUFFER_SIZE ) bytes in length, and filled + with a different repeating character. */ + for( xFileNumber = 1; xFileNumber <= xMaxFiles; xFileNumber++ ) + { + /* Generate a file name. */ + sprintf( cFilePath, "/root%03d.txt", xFileNumber ); + + /* Print out the file name and the directory into which the file is + being written. */ + printf( "Creating file %s\r\n", cFilePath ); + + /* Open the file, creating the file if it does not already exist. */ + lFildes = red_open( cFilePath, RED_O_CREAT|RED_O_TRUNC|RED_O_WRONLY ); + configASSERT( lFildes != -1 ); + + /* Fill the RAM buffer with data that will be written to the file. This + is just a repeating ascii character that indicates the file number. */ + memset( cRAMBuffer, ( int ) ( '0' + xFileNumber ), fsRAM_BUFFER_SIZE ); + + /* Write the RAM buffer to the opened file a number of times. The + number of times the RAM buffer is written to the file depends on the + file number, so the length of each created file will be different. */ + for( xWriteNumber = 0; xWriteNumber < xFileNumber; xWriteNumber++ ) + { + lBytesWritten = red_write( lFildes, cRAMBuffer, fsRAM_BUFFER_SIZE ); + configASSERT( lBytesWritten == fsRAM_BUFFER_SIZE ); + } + + /* Close the file so another file can be created. */ + lStatus = red_close( lFildes ); + configASSERT( lStatus == 0 ); + } + + /* Commit a transaction point, atomically adding the set of files to the + transacted state. */ + lStatus = red_transact( fsVOLUME_NAME ); + configASSERT( lStatus == 0 ); + + /* Create a sub directory. */ + printf( "Creating directory %s\r\n", pcDirectory1 ); + + lStatus = red_mkdir( pcDirectory1 ); + configASSERT( lStatus == 0 ); + + /* Create a subdirectory in the new directory. */ + printf( "Creating directory %s\r\n", pcDirectory2 ); + + lStatus = red_mkdir( pcDirectory2 ); + configASSERT( lStatus == 0 ); + + /* Generate the file name. */ + sprintf( cFilePath, "%s/file.txt", pcDirectory2 ); + + /* Print out the file name and the directory into which the file is being + written. */ + printf( "Writing file %s\r\n", cFilePath ); + + lFildes = red_open( cFilePath, RED_O_CREAT|RED_O_TRUNC|RED_O_WRONLY ); + + /* Write the file. It is filled with incrementing ascii characters starting + from '0'. */ + for( iByte = 0; iByte < fsRAM_BUFFER_SIZE; iByte++ ) + { + cRAMBuffer[ iByte ] = ( char ) ( ( int ) '0' + iByte ); + } + + lBytesWritten = red_write( lFildes, cRAMBuffer, fsRAM_BUFFER_SIZE ); + configASSERT( lBytesWritten == fsRAM_BUFFER_SIZE ); + + /* Finished so close the file. */ + lStatus = red_close( lFildes ); + configASSERT( lStatus == 0 ); + + /* Commit a transaction point, atomically adding the set of files and + directories to the transacted state. */ + lStatus = red_transact( fsVOLUME_NAME ); + configASSERT( lStatus == 0 ); + + /* Restore previous transaction point settings. */ + lStatus = red_settransmask( fsVOLUME_NAME, ulEventMask ); + configASSERT( lStatus == 0 ); +} +/*-----------------------------------------------------------*/ + +static void prvVerifyDemoFiles( void ) +{ +BaseType_t xFileNumber, xReadNumber; +char cFilePath[ 64 ]; +const BaseType_t xMaxFiles = 5; +long lChar; +int32_t lBytesRead, lFildes, lStatus; +int iByte; + + /* Read back the files that were created by prvCreateDemoFiles(). */ + for( xFileNumber = 1; xFileNumber <= xMaxFiles; xFileNumber++ ) + { + /* Generate the file name. */ + sprintf( cFilePath, "/root%03d.txt", xFileNumber ); + + /* Print out the file name and the directory from which the file is + being read. */ + printf( "Reading file %s\r\n", cFilePath ); + + /* Open the file for reading. */ + lFildes = red_open( cFilePath, RED_O_RDONLY ); + configASSERT( lFildes != -1 ); + + /* Read the file into the RAM buffer, checking the file contents are as + expected. The size of the file depends on the file number. */ + for( xReadNumber = 0; xReadNumber < xFileNumber; xReadNumber++ ) + { + /* Start with the RAM buffer clear. */ + memset( cRAMBuffer, 0x00, fsRAM_BUFFER_SIZE ); + + lBytesRead = red_read( lFildes, cRAMBuffer, fsRAM_BUFFER_SIZE ); + configASSERT( lBytesRead == fsRAM_BUFFER_SIZE ); + + /* Check the RAM buffer is filled with the expected data. Each + file contains a different repeating ascii character that indicates + the number of the file. */ + for( lChar = 0; lChar < fsRAM_BUFFER_SIZE; lChar++ ) + { + configASSERT( cRAMBuffer[ lChar ] == ( '0' + ( char ) xFileNumber ) ); + } + } + + /* Close the file. */ + lStatus = red_close( lFildes ); + configASSERT( lStatus == 0 ); + } + + /* Generate the file name. */ + sprintf( cFilePath, "%s/file.txt", pcDirectory2 ); + + /* Print out the file name and the directory from which the file is being + read. */ + printf( "Reading file %s\r\n", cFilePath ); + + /* This time the file is opened for reading. */ + lFildes = red_open( cFilePath, RED_O_RDONLY ); + configASSERT( lFildes != -1 ); + + /* Read the file. */ + lBytesRead = red_read( lFildes, cRAMBuffer, fsRAM_BUFFER_SIZE ); + configASSERT( lBytesRead == fsRAM_BUFFER_SIZE ); + + /* Verify the file 1 byte at a time. */ + for( iByte = 0; iByte < fsRAM_BUFFER_SIZE; iByte++ ) + { + configASSERT( cRAMBuffer[ iByte ] == ( char ) ( ( int ) '0' + iByte ) ); + } + + /* Finished so close the file. */ + lStatus = red_close( lFildes ); + configASSERT( lStatus == 0 ); +} + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/FreeRTOS_Plus_Reliance_Edge_with_CLI.sln b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/FreeRTOS_Plus_Reliance_Edge_with_CLI.sln new file mode 100644 index 0000000..3f819af --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/FreeRTOS_Plus_Reliance_Edge_with_CLI.sln @@ -0,0 +1,20 @@ + +Microsoft Visual Studio Solution File, Format Version 11.00 +# Visual C++ Express 2010 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "WIN32", "WIN32.vcxproj", "{C686325E-3261-42F7-AEB1-DDE5280E1CEB}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Win32 = Debug|Win32 + Release|Win32 = Release|Win32 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.ActiveCfg = Debug|Win32 + {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.Build.0 = Debug|Win32 + {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.ActiveCfg = Release|Win32 + {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.Build.0 = Release|Win32 + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/Instructions_ReadMe.url b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/Instructions_ReadMe.url new file mode 100644 index 0000000..9aca2c6 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/Instructions_ReadMe.url @@ -0,0 +1,6 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 +[InternetShortcut] +URL=http://www.freertos.org/FreeRTOS-Plus/Fail_Safe_File_System/Fail_Safe_Embedded_File_System_demo.shtml +IDList= +HotKey=0 diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/Run-time-stats-utils.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/Run-time-stats-utils.c new file mode 100644 index 0000000..72ed5a4 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/Run-time-stats-utils.c @@ -0,0 +1,90 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * Utility functions required to gather run time statistics. See: + * http://www.freertos.org/rtos-run-time-stats.html + * + * Note that this is a simulated port, where simulated time is a lot slower than + * real time, therefore the run time counter values have no real meaningful + * units. + * + * Also note that it is assumed this demo is going to be used for short periods + * of time only, and therefore timer overflows are not handled. +*/ + +/* FreeRTOS includes. */ +#include + +/* Variables used in the creation of the run time stats time base. Run time +stats record how much time each task spends in the Running state. */ +static long long llInitialRunTimeCounterValue = 0LL, llTicksPerHundedthMillisecond = 0LL; + +/*-----------------------------------------------------------*/ + +void vConfigureTimerForRunTimeStats( void ) +{ +LARGE_INTEGER liPerformanceCounterFrequency, liInitialRunTimeValue; + + /* Initialise the variables used to create the run time stats time base. + Run time stats record how much time each task spends in the Running + state. */ + + if( QueryPerformanceFrequency( &liPerformanceCounterFrequency ) == 0 ) + { + llTicksPerHundedthMillisecond = 1; + } + else + { + /* How many times does the performance counter increment in 1/100th + millisecond. */ + llTicksPerHundedthMillisecond = liPerformanceCounterFrequency.QuadPart / 100000LL; + + /* What is the performance counter value now, this will be subtracted + from readings taken at run time. */ + QueryPerformanceCounter( &liInitialRunTimeValue ); + llInitialRunTimeCounterValue = liInitialRunTimeValue.QuadPart; + } +} +/*-----------------------------------------------------------*/ + +unsigned long ulGetRunTimeCounterValue( void ) +{ +LARGE_INTEGER liCurrentCount; +unsigned long ulReturn; + + /* What is the performance counter value now? */ + QueryPerformanceCounter( &liCurrentCount ); + + /* Subtract the performance counter value reading taken when the + application started to get a count from that reference point, then + scale to (simulated) 1/100ths of a millisecond. */ + ulReturn = ( unsigned long ) ( ( liCurrentCount.QuadPart - llInitialRunTimeCounterValue ) / llTicksPerHundedthMillisecond ); + + return ulReturn; +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/Sample-CLI-commands.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/Sample-CLI-commands.c new file mode 100644 index 0000000..42e7cc4 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/Sample-CLI-commands.c @@ -0,0 +1,379 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + /****************************************************************************** + * + * See the following URL for information on the commands defined in this file: + * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Ethernet_Related_CLI_Commands.shtml + * + ******************************************************************************/ + + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Standard includes. */ +#include +#include +#include + +/* FreeRTOS+CLI includes. */ +#include "FreeRTOS_CLI.h" + +#ifndef configINCLUDE_TRACE_RELATED_CLI_COMMANDS + #define configINCLUDE_TRACE_RELATED_CLI_COMMANDS 0 +#endif + + +/* + * Implements the run-time-stats command. + */ +static BaseType_t prvTaskStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the task-stats command. + */ +static BaseType_t prvRunTimeStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the echo-three-parameters command. + */ +static BaseType_t prvThreeParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the echo-parameters command. + */ +static BaseType_t prvParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Implements the "trace start" and "trace stop" commands; + */ +#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 + static BaseType_t prvStartStopTraceCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); +#endif + +/* Structure that defines the "run-time-stats" command line command. This +generates a table that shows how much run time each task has */ +static const CLI_Command_Definition_t xRunTimeStats = +{ + "run-time-stats", /* The command string to type. */ + "\r\nrun-time-stats:\r\n Displays a table showing how much processing time each FreeRTOS task has used\r\n", + prvRunTimeStatsCommand, /* The function to run. */ + 0 /* No parameters are expected. */ +}; + +/* Structure that defines the "task-stats" command line command. This generates +a table that gives information on each task in the system. */ +static const CLI_Command_Definition_t xTaskStats = +{ + "task-stats", /* The command string to type. */ + "\r\ntask-stats:\r\n Displays a table showing the state of each FreeRTOS task\r\n", + prvTaskStatsCommand, /* The function to run. */ + 0 /* No parameters are expected. */ +}; + +/* Structure that defines the "echo_3_parameters" command line command. This +takes exactly three parameters that the command simply echos back one at a +time. */ +static const CLI_Command_Definition_t xThreeParameterEcho = +{ + "echo-3-parameters", + "\r\necho-3-parameters :\r\n Expects three parameters, echos each in turn\r\n", + prvThreeParameterEchoCommand, /* The function to run. */ + 3 /* Three parameters are expected, which can take any value. */ +}; + +/* Structure that defines the "echo_parameters" command line command. This +takes a variable number of parameters that the command simply echos back one at +a time. */ +static const CLI_Command_Definition_t xParameterEcho = +{ + "echo-parameters", + "\r\necho-parameters <...>:\r\n Take variable number of parameters, echos each in turn\r\n", + prvParameterEchoCommand, /* The function to run. */ + -1 /* The user can enter any number of commands. */ +}; + +#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 + /* Structure that defines the "trace" command line command. This takes a single + parameter, which can be either "start" or "stop". */ + static const CLI_Command_Definition_t xStartStopTrace = + { + "trace", + "\r\ntrace [start | stop]:\r\n Starts or stops a trace recording for viewing in FreeRTOS+Trace\r\n", + prvStartStopTraceCommand, /* The function to run. */ + 1 /* One parameter is expected. Valid values are "start" and "stop". */ + }; +#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */ + +/*-----------------------------------------------------------*/ + +void vRegisterSampleCLICommands( void ) +{ + /* Register all the command line commands defined immediately above. */ + FreeRTOS_CLIRegisterCommand( &xTaskStats ); + FreeRTOS_CLIRegisterCommand( &xRunTimeStats ); + FreeRTOS_CLIRegisterCommand( &xThreeParameterEcho ); + FreeRTOS_CLIRegisterCommand( &xParameterEcho ); + + #if( configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 ) + { + FreeRTOS_CLIRegisterCommand( & xStartStopTrace ); + } + #endif +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTaskStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *const pcHeader = "Task State Priority Stack #\r\n************************************************\r\n"; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + /* Generate a table of task stats. */ + strcpy( pcWriteBuffer, pcHeader ); + vTaskList( pcWriteBuffer + strlen( pcHeader ) ); + + /* There is no more data to return after this single string, so return + pdFALSE. */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvRunTimeStatsCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char * const pcHeader = "Task Abs Time % Time\r\n****************************************\r\n"; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + /* Generate a table of task stats. */ + strcpy( pcWriteBuffer, pcHeader ); + vTaskGetRunTimeStats( pcWriteBuffer + strlen( pcHeader ) ); + + /* There is no more data to return after this single string, so return + pdFALSE. */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvThreeParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *pcParameter; +BaseType_t xParameterStringLength, xReturn; +static BaseType_t lParameterNumber = 0; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + if( lParameterNumber == 0 ) + { + /* The first time the function is called after the command has been + entered just a header string is returned. */ + sprintf( pcWriteBuffer, "The three parameters were:\r\n" ); + + /* Next time the function is called the first parameter will be echoed + back. */ + lParameterNumber = 1L; + + /* There is more data to be returned as no parameters have been echoed + back yet. */ + xReturn = pdPASS; + } + else + { + /* Obtain the parameter string. */ + pcParameter = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + lParameterNumber, /* Return the next parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcParameter ); + + /* Return the parameter string. */ + memset( pcWriteBuffer, 0x00, xWriteBufferLen ); + sprintf( pcWriteBuffer, "%d: ", ( int ) lParameterNumber ); + strncat( pcWriteBuffer, pcParameter, xParameterStringLength ); + strncat( pcWriteBuffer, "\r\n", strlen( "\r\n" ) ); + + /* If this is the last of the three parameters then there are no more + strings to return after this one. */ + if( lParameterNumber == 3L ) + { + /* If this is the last of the three parameters then there are no more + strings to return after this one. */ + xReturn = pdFALSE; + lParameterNumber = 0L; + } + else + { + /* There are more parameters to return after this one. */ + xReturn = pdTRUE; + lParameterNumber++; + } + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvParameterEchoCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +const char *pcParameter; +BaseType_t xParameterStringLength, xReturn; +static BaseType_t lParameterNumber = 0; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + if( lParameterNumber == 0 ) + { + /* The first time the function is called after the command has been + entered just a header string is returned. */ + sprintf( pcWriteBuffer, "The parameters were:\r\n" ); + + /* Next time the function is called the first parameter will be echoed + back. */ + lParameterNumber = 1L; + + /* There is more data to be returned as no parameters have been echoed + back yet. */ + xReturn = pdPASS; + } + else + { + /* Obtain the parameter string. */ + pcParameter = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + lParameterNumber, /* Return the next parameter. */ + &xParameterStringLength /* Store the parameter string length. */ + ); + + if( pcParameter != NULL ) + { + /* Return the parameter string. */ + memset( pcWriteBuffer, 0x00, xWriteBufferLen ); + sprintf( pcWriteBuffer, "%d: ", ( int ) lParameterNumber ); + strncat( pcWriteBuffer, pcParameter, xParameterStringLength ); + strncat( pcWriteBuffer, "\r\n", strlen( "\r\n" ) ); + + /* There might be more parameters to return after this one. */ + xReturn = pdTRUE; + lParameterNumber++; + } + else + { + /* No more parameters were found. Make sure the write buffer does + not contain a valid string. */ + pcWriteBuffer[ 0 ] = 0x00; + + /* No more data to return. */ + xReturn = pdFALSE; + + /* Start over the next time this command is executed. */ + lParameterNumber = 0; + } + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 + + static BaseType_t prvStartStopTraceCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) + { + const char *pcParameter; + BaseType_t lParameterStringLength; + + /* Remove compile time warnings about unused parameters, and check the + write buffer is not NULL. NOTE - for simplicity, this example assumes the + write buffer length is adequate, so does not check for buffer overflows. */ + ( void ) pcCommandString; + ( void ) xWriteBufferLen; + configASSERT( pcWriteBuffer ); + + /* Obtain the parameter string. */ + pcParameter = FreeRTOS_CLIGetParameter + ( + pcCommandString, /* The command string itself. */ + 1, /* Return the first parameter. */ + &lParameterStringLength /* Store the parameter string length. */ + ); + + /* Sanity check something was returned. */ + configASSERT( pcParameter ); + + /* There are only two valid parameter values. */ + if( strncmp( pcParameter, "start", strlen( "start" ) ) == 0 ) + { + /* Start or restart the trace. */ + vTraceStop(); + vTraceClear(); + vTraceStart(); + + sprintf( pcWriteBuffer, "Trace recording (re)started.\r\n" ); + } + else if( strncmp( pcParameter, "stop", strlen( "stop" ) ) == 0 ) + { + /* End the trace, if one is running. */ + vTraceStop(); + sprintf( pcWriteBuffer, "Stopping trace recording.\r\n" ); + } + else + { + sprintf( pcWriteBuffer, "Valid parameters are 'start' and 'stop'.\r\n" ); + } + + /* There is no more data to return after this single string, so return + pdFALSE. */ + return pdFALSE; + } + +#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/UDPCommandServer.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/UDPCommandServer.c new file mode 100644 index 0000000..5659823 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/UDPCommandServer.c @@ -0,0 +1,229 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#pragma comment( lib, "ws2_32.lib" ) + +/* Win32 includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Standard includes. */ +#include +#include + +/* FreeRTOS+CLI includes. */ +#include "FreeRTOS_CLI.h" + +/* Dimensions the buffer into which input characters are placed. */ +#define cmdMAX_INPUT_SIZE 60 + +/* Dimensions the buffer into which string outputs can be placed. */ +#define cmdMAX_OUTPUT_SIZE 1024 + +/* Dimensions the buffer passed to the recvfrom() call. */ +#define cmdSOCKET_INPUT_BUFFER_SIZE 60 + +/* DEL acts as a backspace. */ +#define cmdASCII_DEL ( 0x7F ) + +/* + * Open and configure the UDP socket. + */ +static SOCKET prvOpenUDPSocket( void ); + +/*-----------------------------------------------------------*/ + +/* + * Task that provides the input and output for the FreeRTOS+CLI command + * interpreter. In this case a WinSock UDP port is used for convenience as this + * demo runs in a simulated environment on a Windows PC. See the URL in the + * comments within main.c for the location of the online documentation. + */ +void vUDPCommandInterpreterTask( void *pvParameters ) +{ +long lBytes, lByte; +signed char cInChar, cInputIndex = 0; +static signed char cInputString[ cmdMAX_INPUT_SIZE ], cOutputString[ cmdMAX_OUTPUT_SIZE ], cLocalBuffer[ cmdSOCKET_INPUT_BUFFER_SIZE ]; +BaseType_t xMoreDataToFollow; +volatile int iErrorCode = 0; +struct sockaddr_in xClient; +int xClientAddressLength = sizeof( struct sockaddr_in ); +SOCKET xSocket; + + /* Just to prevent compiler warnings. */ + ( void ) pvParameters; + + /* Attempt to open the socket. */ + xSocket = prvOpenUDPSocket(); + + if( xSocket != INVALID_SOCKET ) + { + for( ;; ) + { + /* Wait for incoming data on the opened socket. */ + lBytes = recvfrom( xSocket, cLocalBuffer, sizeof( cLocalBuffer ), 0, ( struct sockaddr * ) &xClient, &xClientAddressLength ); + + if( lBytes == SOCKET_ERROR ) + { + /* Something went wrong, but it is not handled by this simple + example. */ + iErrorCode = WSAGetLastError(); + } + else + { + /* Process each received byte in turn. */ + lByte = 0; + while( lByte < lBytes ) + { + /* The next character in the input buffer. */ + cInChar = cLocalBuffer[ lByte ]; + lByte++; + + /* Newline characters are taken as the end of the command + string. */ + if( cInChar == '\n' ) + { + /* Process the input string received prior to the + newline. */ + do + { + /* Pass the string to FreeRTOS+CLI. */ + xMoreDataToFollow = FreeRTOS_CLIProcessCommand( cInputString, cOutputString, cmdMAX_OUTPUT_SIZE ); + + /* Send the output generated by the command's + implementation. */ + sendto( xSocket, cOutputString, strlen( cOutputString ), 0, ( SOCKADDR * ) &xClient, xClientAddressLength ); + + } while( xMoreDataToFollow != pdFALSE ); /* Until the command does not generate any more output. */ + + /* All the strings generated by the command processing + have been sent. Clear the input string ready to receive + the next command. */ + cInputIndex = 0; + memset( cInputString, 0x00, cmdMAX_INPUT_SIZE ); + + /* Transmit a spacer, just to make the command console + easier to read. */ + sendto( xSocket, "\r\n", strlen( "\r\n" ), 0, ( SOCKADDR * ) &xClient, xClientAddressLength ); + } + else + { + if( cInChar == '\r' ) + { + /* Ignore the character. Newlines are used to + detect the end of the input string. */ + } + else if( ( cInChar == '\b' ) || ( cInChar == cmdASCII_DEL ) ) + { + /* Backspace was pressed. Erase the last character + in the string - if any. */ + if( cInputIndex > 0 ) + { + cInputIndex--; + cInputString[ cInputIndex ] = '\0'; + } + } + else + { + /* A character was entered. Add it to the string + entered so far. When a \n is entered the complete + string will be passed to the command interpreter. */ + if( cInputIndex < cmdMAX_INPUT_SIZE ) + { + cInputString[ cInputIndex ] = cInChar; + cInputIndex++; + } + } + } + } + } + } + } + else + { + /* The socket could not be opened. */ + vTaskDelete( NULL ); + } +} +/*-----------------------------------------------------------*/ + +static SOCKET prvOpenUDPSocket( void ) +{ +WSADATA xWSAData; +WORD wVersionRequested; +struct sockaddr_in xServer; +SOCKET xSocket = INVALID_SOCKET; + + wVersionRequested = MAKEWORD( 2, 2 ); + + /* Prepare to use WinSock. */ + if( WSAStartup( wVersionRequested, &xWSAData ) != 0 ) + { + fprintf( stderr, "Could not open Windows connection.\n" ); + } + else + { + xSocket = socket( AF_INET, SOCK_DGRAM, 0 ); + if( xSocket == INVALID_SOCKET) + { + fprintf( stderr, "Could not create socket.\n" ); + WSACleanup(); + } + else + { + /* Zero out the server structure. */ + memset( ( void * ) &xServer, 0x00, sizeof( struct sockaddr_in ) ); + + /* Set family and port. */ + xServer.sin_family = AF_INET; + xServer.sin_port = htons( configUDP_CLI_PORT_NUMBER ); + + /* Assign the loopback address */ + xServer.sin_addr.S_un.S_un_b.s_b1 = 127; + xServer.sin_addr.S_un.S_un_b.s_b2 = 0; + xServer.sin_addr.S_un.S_un_b.s_b3 = 0; + xServer.sin_addr.S_un.S_un_b.s_b4 = 1; + + /* Bind the address to the socket. */ + if( bind( xSocket, ( struct sockaddr * ) &xServer, sizeof( struct sockaddr_in ) ) == -1 ) + { + fprintf( stderr, "Could not socket to port %d.\n", configUDP_CLI_PORT_NUMBER ); + closesocket( xSocket ); + xSocket = INVALID_SOCKET; + WSACleanup(); + } + } + } + + return xSocket; +} + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/WIN32.vcxproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/WIN32.vcxproj new file mode 100644 index 0000000..6d377dc --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/WIN32.vcxproj @@ -0,0 +1,199 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + + {C686325E-3261-42F7-AEB1-DDE5280E1CEB} + RTOSDemo + + + + Application + false + MultiByte + + + Application + false + MultiByte + + + + + + + + + + + + + + + <_ProjectFileVersion>10.0.30319.1 + .\Debug\ + .\Debug\ + true + .\Release\ + .\Release\ + false + + + + .\Debug/WIN32.tlb + + + + + Disabled + ..\..\Source\Reliance-Edge\os\freertos\include;..\..\Source\Reliance-Edge\projects\freertos\win32-demo;..\..\Source\Reliance-Edge\core\include;..\..\Source\Reliance-Edge\include;..\..\..\FreeRTOS\Source\include;..\..\..\FreeRTOS\Source\portable\MSVC-MingW;..\..\Source\FreeRTOS-Plus-CLI;.;.\ConfigurationFiles;%(AdditionalIncludeDirectories) + WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) + true + EnableFastChecks + MultiThreadedDebug + .\Debug/WIN32.pch + .\Debug/ + .\Debug/ + .\Debug/ + Level4 + true + false + EditAndContinue + + + _DEBUG;%(PreprocessorDefinitions) + 0x0c09 + + + .\Debug/RTOSDemo.exe + true + true + .\Debug/WIN32.pdb + Console + MachineX86 + %(AdditionalDependencies) + .\WinPCap + + + true + .\Debug/WIN32.bsc + + + + + .\Release/WIN32.tlb + + + + + MaxSpeed + OnlyExplicitInline + _WINSOCKAPI_;WIN32;NDEBUG;_CONSOLE;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) + true + MultiThreaded + true + .\Release/WIN32.pch + .\Release/ + .\Release/ + .\Release/ + Level3 + true + ..\Common\Utils;..\Common\ethernet\lwip-1.4.0\ports\win32\WinPCap;..\Common\ethernet\lwip-1.4.0\src\include\ipv4;..\Common\ethernet\lwip-1.4.0\src\include;..\..\Source\include;..\..\Source\portable\MSVC-MingW;..\Common\ethernet\lwip-1.4.0\ports\win32\include;..\Common\Include;.\lwIP_Apps;.;%(AdditionalIncludeDirectories) + + + NDEBUG;%(PreprocessorDefinitions) + 0x0c09 + + + .\Release/RTOSDemo.exe + true + .\Release/WIN32.pdb + Console + MachineX86 + ..\Common\ethernet\lwip-1.4.0\ports\win32\WinPCap + wpcap.lib;%(AdditionalDependencies) + + + true + .\Release/WIN32.bsc + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + %(AdditionalIncludeDirectories) + %(PreprocessorDefinitions) + %(PreprocessorDefinitions) + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/WIN32.vcxproj.filters b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/WIN32.vcxproj.filters new file mode 100644 index 0000000..7d355d1 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/WIN32.vcxproj.filters @@ -0,0 +1,219 @@ + + + + + {38712199-cebf-4124-bf15-398f7c3419ea} + ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe + + + {af3445a1-4908-4170-89ed-39345d90d30c} + + + {f32be356-4763-4cae-9020-974a2638cb08} + *.c + + + {88f409e6-d396-4ac5-94bd-7a99c914be46} + + + {e5ad4ec7-23dc-4295-8add-2acaee488f5a} + + + {fd43c0ed-fdbc-437f-a5a3-c50399690bd7} + + + {c5889fe2-af0f-4cea-927f-6a6935ec5e14} + + + {19ff1a34-36de-4c48-9d10-3fb1fa0d1fa4} + h;hpp;hxx;hm;inl + + + {ab23827c-126c-4e5a-bc99-8efa44d8a8bd} + + + {9c9c3b2d-6958-407d-b742-23fbf73678ed} + + + {e47b8f1d-1582-4e56-9c2f-ca2cdbea1b86} + + + {9ecfe142-5bd2-472b-9568-243fa6169874} + + + {28ee3d7e-231b-4094-8a10-ad89fc82f705} + + + {a955d01e-1f95-4c34-9558-14c52b75576f} + + + + + FreeRTOS\Source\Portable + + + FreeRTOS\Source + + + FreeRTOS\Source + + + FreeRTOS\Source + + + FreeRTOS\Source + + + FreeRTOS\Source\Portable + + + FreeRTOS+\FreeRTOS+CLI + + + + + + + + FreeRTOS+\FreeRTOS+Reliance Edge\test + + + FreeRTOS+\FreeRTOS+Reliance Edge\test + + + FreeRTOS+\FreeRTOS+Reliance Edge\test + + + FreeRTOS+\FreeRTOS+Reliance Edge\port + + + FreeRTOS+\FreeRTOS+Reliance Edge\port + + + FreeRTOS+\FreeRTOS+Reliance Edge\port + + + FreeRTOS+\FreeRTOS+Reliance Edge\port + + + FreeRTOS+\FreeRTOS+Reliance Edge\port + + + FreeRTOS+\FreeRTOS+Reliance Edge\port + + + FreeRTOS+\FreeRTOS+Reliance Edge\port + + + FreeRTOS+\FreeRTOS+Reliance Edge\driver + + + FreeRTOS+\FreeRTOS+Reliance Edge\driver + + + FreeRTOS+\FreeRTOS+Reliance Edge\driver + + + FreeRTOS+\FreeRTOS+Reliance Edge\driver + + + FreeRTOS+\FreeRTOS+Reliance Edge\driver + + + FreeRTOS+\FreeRTOS+Reliance Edge\driver + + + FreeRTOS+\FreeRTOS+Reliance Edge\driver + + + FreeRTOS+\FreeRTOS+Reliance Edge\driver + + + FreeRTOS+\FreeRTOS+Reliance Edge\driver + + + FreeRTOS+\FreeRTOS+Reliance Edge\driver + + + FreeRTOS+\FreeRTOS+Reliance Edge\driver + + + FreeRTOS+\FreeRTOS+Reliance Edge\driver + + + FreeRTOS+\FreeRTOS+Reliance Edge\driver + + + FreeRTOS+\FreeRTOS+Reliance Edge\driver + + + FreeRTOS+\FreeRTOS+Reliance Edge\util + + + FreeRTOS+\FreeRTOS+Reliance Edge\util + + + FreeRTOS+\FreeRTOS+Reliance Edge\util + + + FreeRTOS+\FreeRTOS+Reliance Edge\util + + + FreeRTOS+\FreeRTOS+Reliance Edge\util + + + FreeRTOS+\FreeRTOS+Reliance Edge\util + + + FreeRTOS+\FreeRTOS+Reliance Edge\util + + + + Configuration Files + + + FreeRTOS+\FreeRTOS+Reliance Edge\test + + + FreeRTOS+\FreeRTOS+Reliance Edge\test + + + FreeRTOS+\FreeRTOS+Reliance Edge\test + + + FreeRTOS+\FreeRTOS+Reliance Edge\test + + + + + FreeRTOS+\FreeRTOS+CLI\include + + + FreeRTOS\Source\include + + + FreeRTOS\Source\include + + + FreeRTOS\Source\include + + + FreeRTOS\Source\include + + + FreeRTOS\Source\include + + + FreeRTOS\Source\include + + + Configuration Files + + + Configuration Files + + + Configuration Files + + + \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/WIN32.vcxproj.user b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/WIN32.vcxproj.user new file mode 100644 index 0000000..695b5c7 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/WIN32.vcxproj.user @@ -0,0 +1,3 @@ + + + \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/main.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/main.c new file mode 100644 index 0000000..f5bf167 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_Reliance_Edge_and_CLI_Windows_Simulator/main.c @@ -0,0 +1,165 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/****************************************************************************** + * + * This demo is described on the following web page: + * TODO: This link describes the FAT version of this demo. + * http://www.freertos.org/FreeRTOS-Plus/Fail_Safe_File_System/Fail_Safe_Embedded_File_System_demo.shtml + * + ******************************************************************************/ + +/* Standard includes. */ +#include +#include + +/* FreeRTOS includes. */ +#include +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Priorities at which the tasks are created. */ +#define mainUDP_CLI_TASK_PRIORITY ( tskIDLE_PRIORITY ) + +/*-----------------------------------------------------------*/ + +/* + * Register the generic commands that can be used with FreeRTOS+CLI. + */ +extern void vRegisterSampleCLICommands( void ); + +/* + * Register the file system commands that can be used with FreeRTOS+CLI. + */ +extern void vRegisterFileSystemCLICommands( void ); + +/* + * The task that implements the UDP command interpreter using FreeRTOS+CLI. + */ +extern void vUDPCommandInterpreterTask( void *pvParameters ); + +/* + * Creates and verifies different files on the volume, demonstrating the use of + * various different API functions. + */ +extern void vCreateAndVerifySampleFiles( void ); + +/*-----------------------------------------------------------*/ + +/* See http://www.freertos.org/FreeRTOS-Plus/Fail_Safe_File_System/Fail_Safe_Embedded_File_System_demo.shtml +for instructions. */ + +int main( void ) +{ +const uint32_t ulLongTime_ms = 250UL; + + /* Initialise the drive and file system, then create a few example + files. The output from this function just goes to the stdout window, + allowing the output to be viewed when the UDP command console is not + connected. */ + vCreateAndVerifySampleFiles(); + + /* Register generic commands with the FreeRTOS+CLI command interpreter. */ + vRegisterSampleCLICommands(); + + /* Register file system related commands with the FreeRTOS+CLI command + interpreter. */ + vRegisterFileSystemCLICommands(); + + /* Create the task that handles the CLI on a UDP port. The port number + is set using the configUDP_CLI_PORT_NUMBER setting in FreeRTOSConfig.h. */ + xTaskCreate( vUDPCommandInterpreterTask, /* The function that implements the command interpreter IO handling. */ + "CLI", /* The name of the task - just to assist debugging. */ + configMINIMAL_STACK_SIZE, NULL, /* The size of the stack allocated to the task. */ + mainUDP_CLI_TASK_PRIORITY, /* The priority at which the task will run. */ + NULL ); /* A handle to the task is not required, so NULL is passed. */ + + /* Start the RTOS scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was insufficient FreeRTOS heap memory available for the idle and/or + timer tasks to be created. See the memory management section on the + FreeRTOS web site for more details (this is standard text that is not + really applicable to the Win32 simulator port). */ + for( ;; ) + { + Sleep( ulLongTime_ms ); + } +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +const unsigned long ulMSToSleep = 5; + + /* This function is called on each cycle of the idle task if + configUSE_IDLE_HOOK is set to 1 in FreeRTOSConfig.h. Sleep to reduce CPU + load. */ + Sleep( ulMSToSleep ); +} +/*-----------------------------------------------------------*/ + +void vAssertCalled( const char *pcFile, unsigned long ulLine ) +{ +volatile uint32_t ulSetToNonZeroToExitLoop = 0; + + printf( "ASSERT FAILED: File %s, line %u\r\n", pcFile, ulLine ); + + taskENTER_CRITICAL(); + { + while( ulSetToNonZeroToExitLoop == 0 ) + { + /* Do not leave the assert function unless the debugger is used to + set ulSetToNonZeroToExitLoop to a non-zero value. */ + } + } + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* vApplicationMallocFailedHook() will only be called if + configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + function that will get called if a call to pvPortMalloc() fails. + pvPortMalloc() is called internally by the kernel whenever a task, queue, + timer or semaphore is created. It is also called by various parts of the + demo application. If heap_1.c, heap_2.c or heap_4.c are used, then the + size of the heap available to pvPortMalloc() is defined by + configTOTAL_HEAP_SIZE in FreeRTOSConfig.h, and the xPortGetFreeHeapSize() + API function can be used to query the size of free heap space that remains + (although it does not provide information on how the remaining heap might + be fragmented). */ + taskDISABLE_INTERRUPTS(); + for( ;; ); +} + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/DemoTasks/SimpleTCPEchoServer.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/DemoTasks/SimpleTCPEchoServer.c new file mode 100644 index 0000000..2a2c704 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/DemoTasks/SimpleTCPEchoServer.c @@ -0,0 +1,288 @@ +/* + FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * FreeRTOS tasks are used with FreeRTOS+TCP to create a TCP echo server on the + * standard echo port number (7). + * + * See the following web page for essential demo usage and configuration + * details: + * http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/TCP_Echo_Server.html + */ + +/* Standard includes. */ +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" + +/* Remove the whole file if FreeRTOSIPConfig.h is set to exclude TCP. */ +#if( ipconfigUSE_TCP == 1 ) + +/* The maximum time to wait for a closing socket to close. */ +#define tcpechoSHUTDOWN_DELAY ( pdMS_TO_TICKS( 5000 ) ) + +/* The standard echo port number. */ +#define tcpechoPORT_NUMBER 7 + +/* If ipconfigUSE_TCP_WIN is 1 then the Tx sockets will use a buffer size set by +ipconfigTCP_TX_BUFFER_LENGTH, and the Tx window size will be +configECHO_SERVER_TX_WINDOW_SIZE times the buffer size. Note +ipconfigTCP_TX_BUFFER_LENGTH is set in FreeRTOSIPConfig.h as it is a standard TCP/IP +stack constant, whereas configECHO_SERVER_TX_WINDOW_SIZE is set in +FreeRTOSConfig.h as it is a demo application constant. */ +#ifndef configECHO_SERVER_TX_WINDOW_SIZE + #define configECHO_SERVER_TX_WINDOW_SIZE 2 +#endif + +/* If ipconfigUSE_TCP_WIN is 1 then the Rx sockets will use a buffer size set by +ipconfigTCP_RX_BUFFER_LENGTH, and the Rx window size will be +configECHO_SERVER_RX_WINDOW_SIZE times the buffer size. Note +ipconfigTCP_RX_BUFFER_LENGTH is set in FreeRTOSIPConfig.h as it is a standard TCP/IP +stack constant, whereas configECHO_SERVER_RX_WINDOW_SIZE is set in +FreeRTOSConfig.h as it is a demo application constant. */ +#ifndef configECHO_SERVER_RX_WINDOW_SIZE + #define configECHO_SERVER_RX_WINDOW_SIZE 2 +#endif + +/*-----------------------------------------------------------*/ + +/* + * Uses FreeRTOS+TCP to listen for incoming echo connections, creating a task + * to handle each connection. + */ +static void prvConnectionListeningTask( void *pvParameters ); + +/* + * Created by the connection listening task to handle a single connection. + */ +static void prvServerConnectionInstance( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* Stores the stack size passed into vStartSimpleTCPServerTasks() so it can be +reused when the server listening task creates tasks to handle connections. */ +static uint16_t usUsedStackSize = 0; + +/*-----------------------------------------------------------*/ + +void vStartSimpleTCPServerTasks( uint16_t usStackSize, UBaseType_t uxPriority ) +{ + /* Create the TCP echo server. */ + xTaskCreate( prvConnectionListeningTask, "ServerListener", usStackSize, NULL, uxPriority + 1, NULL ); + + /* Remember the requested stack size so it can be re-used by the server + listening task when it creates tasks to handle connections. */ + usUsedStackSize = usStackSize; +} +/*-----------------------------------------------------------*/ + +static void prvConnectionListeningTask( void *pvParameters ) +{ +struct freertos_sockaddr xClient, xBindAddress; +Socket_t xListeningSocket, xConnectedSocket; +socklen_t xSize = sizeof( xClient ); +static const TickType_t xReceiveTimeOut = portMAX_DELAY; +const BaseType_t xBacklog = 20; + +#if( ipconfigUSE_TCP_WIN == 1 ) + WinProperties_t xWinProps; + + /* Fill in the buffer and window sizes that will be used by the socket. */ + xWinProps.lTxBufSize = ipconfigTCP_TX_BUFFER_LENGTH; + xWinProps.lTxWinSize = configECHO_SERVER_TX_WINDOW_SIZE; + xWinProps.lRxBufSize = ipconfigTCP_RX_BUFFER_LENGTH; + xWinProps.lRxWinSize = configECHO_SERVER_RX_WINDOW_SIZE; +#endif /* ipconfigUSE_TCP_WIN */ + + /* Just to prevent compiler warnings. */ + ( void ) pvParameters; + + /* Attempt to open the socket. */ + xListeningSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_STREAM, FREERTOS_IPPROTO_TCP ); + configASSERT( xListeningSocket != FREERTOS_INVALID_SOCKET ); + + /* Set a time out so accept() will just wait for a connection. */ + FreeRTOS_setsockopt( xListeningSocket, 0, FREERTOS_SO_RCVTIMEO, &xReceiveTimeOut, sizeof( xReceiveTimeOut ) ); + + /* Set the window and buffer sizes. */ + #if( ipconfigUSE_TCP_WIN == 1 ) + { + FreeRTOS_setsockopt( xListeningSocket, 0, FREERTOS_SO_WIN_PROPERTIES, ( void * ) &xWinProps, sizeof( xWinProps ) ); + } + #endif /* ipconfigUSE_TCP_WIN */ + + /* Bind the socket to the port that the client task will send to, then + listen for incoming connections. */ + xBindAddress.sin_port = tcpechoPORT_NUMBER; + xBindAddress.sin_port = FreeRTOS_htons( xBindAddress.sin_port ); + FreeRTOS_bind( xListeningSocket, &xBindAddress, sizeof( xBindAddress ) ); + FreeRTOS_listen( xListeningSocket, xBacklog ); + + for( ;; ) + { + /* Wait for a client to connect. */ + xConnectedSocket = FreeRTOS_accept( xListeningSocket, &xClient, &xSize ); + configASSERT( xConnectedSocket != FREERTOS_INVALID_SOCKET ); + + /* Spawn a task to handle the connection. */ + xTaskCreate( prvServerConnectionInstance, "EchoServer", usUsedStackSize, ( void * ) xConnectedSocket, tskIDLE_PRIORITY, NULL ); + } +} +/*-----------------------------------------------------------*/ + +static void prvServerConnectionInstance( void *pvParameters ) +{ +int32_t lBytes, lSent, lTotalSent; +Socket_t xConnectedSocket; +static const TickType_t xReceiveTimeOut = pdMS_TO_TICKS( 5000 ); +static const TickType_t xSendTimeOut = pdMS_TO_TICKS( 5000 ); +TickType_t xTimeOnShutdown; +uint8_t *pucRxBuffer; + + xConnectedSocket = ( Socket_t ) pvParameters; + + /* Attempt to create the buffer used to receive the string to be echoed + back. This could be avoided using a zero copy interface that just returned + the same buffer. */ + pucRxBuffer = ( uint8_t * ) pvPortMalloc( ipconfigTCP_MSS ); + + if( pucRxBuffer != NULL ) + { + FreeRTOS_setsockopt( xConnectedSocket, 0, FREERTOS_SO_RCVTIMEO, &xReceiveTimeOut, sizeof( xReceiveTimeOut ) ); + FreeRTOS_setsockopt( xConnectedSocket, 0, FREERTOS_SO_SNDTIMEO, &xSendTimeOut, sizeof( xReceiveTimeOut ) ); + + for( ;; ) + { + /* Zero out the receive array so there is NULL at the end of the string + when it is printed out. */ + memset( pucRxBuffer, 0x00, ipconfigTCP_MSS ); + + /* Receive data on the socket. */ + lBytes = FreeRTOS_recv( xConnectedSocket, pucRxBuffer, ipconfigTCP_MSS, 0 ); + + /* If data was received, echo it back. */ + if( lBytes >= 0 ) + { + lSent = 0; + lTotalSent = 0; + + /* Call send() until all the data has been sent. */ + while( ( lSent >= 0 ) && ( lTotalSent < lBytes ) ) + { + lSent = FreeRTOS_send( xConnectedSocket, pucRxBuffer, lBytes - lTotalSent, 0 ); + lTotalSent += lSent; + } + + if( lSent < 0 ) + { + /* Socket closed? */ + break; + } + } + else + { + /* Socket closed? */ + break; + } + } + } + + /* Initiate a shutdown in case it has not already been initiated. */ + FreeRTOS_shutdown( xConnectedSocket, FREERTOS_SHUT_RDWR ); + + /* Wait for the shutdown to take effect, indicated by FreeRTOS_recv() + returning an error. */ + xTimeOnShutdown = xTaskGetTickCount(); + do + { + if( FreeRTOS_recv( xConnectedSocket, pucRxBuffer, ipconfigTCP_MSS, 0 ) < 0 ) + { + break; + } + } while( ( xTaskGetTickCount() - xTimeOnShutdown ) < tcpechoSHUTDOWN_DELAY ); + + /* Finished with the socket, buffer, the task. */ + vPortFree( pucRxBuffer ); + FreeRTOS_closesocket( xConnectedSocket ); + + vTaskDelete( NULL ); +} +/*-----------------------------------------------------------*/ + +/* The whole file is excluded if TCP is not compiled in. */ +#endif /* ipconfigUSE_TCP */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/DemoTasks/SimpleUDPClientAndServer.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/DemoTasks/SimpleUDPClientAndServer.c new file mode 100644 index 0000000..0c6ffa2 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/DemoTasks/SimpleUDPClientAndServer.c @@ -0,0 +1,355 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * Creates two transmitting tasks and two receiving tasks. The transmitting + * tasks send values that are received by the receiving tasks. One set of tasks + * uses the standard API. The other set of tasks uses the zero copy API. + * + * See the following web page for essential demo usage and configuration + * details: + * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/examples_FreeRTOS_simulator.html + */ + +/* Standard includes. */ +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" + +#define simpTINY_DELAY ( ( TickType_t ) 2 ) + +/* + * Uses a socket to send data without using the zero copy option. + * prvSimpleServerTask() will receive the data. + */ +static void prvSimpleClientTask( void *pvParameters ); + +/* + * Uses a socket to receive the data sent by the prvSimpleClientTask() task. + * Does not use the zero copy option. + */ +static void prvSimpleServerTask( void *pvParameters ); + +/* + * Uses a socket to send data using the zero copy option. + * prvSimpleZeroCopyServerTask() will receive the data. + */ +static void prvSimpleZeroCopyUDPClientTask( void *pvParameters ); + +/* + * Uses a socket to receive the data sent by the prvSimpleZeroCopyUDPClientTask() + * task. Uses the zero copy option. + */ +static void prvSimpleZeroCopyServerTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +void vStartSimpleUDPClientServerTasks( uint16_t usStackSize, uint32_t ulPort, UBaseType_t uxPriority ) +{ + /* Create the client and server tasks that do not use the zero copy + interface. */ + xTaskCreate( prvSimpleClientTask, "SimpCpyClnt", usStackSize, ( void * ) ulPort, uxPriority, NULL ); + xTaskCreate( prvSimpleServerTask, "SimpCpySrv", usStackSize, ( void * ) ulPort, uxPriority + 1, NULL ); + + /* Create the client and server tasks that do use the zero copy interface. */ + xTaskCreate( prvSimpleZeroCopyUDPClientTask, "SimpZCpyClnt", usStackSize, ( void * ) ( ulPort + 1 ), uxPriority, NULL ); + xTaskCreate( prvSimpleZeroCopyServerTask, "SimpZCpySrv", usStackSize, ( void * ) ( ulPort + 1 ), uxPriority + 1, NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvSimpleClientTask( void *pvParameters ) +{ +Socket_t xClientSocket; +struct freertos_sockaddr xDestinationAddress; +uint8_t cString[ 50 ]; +BaseType_t lReturned; +uint32_t ulCount = 0UL, ulIPAddress; +const uint32_t ulLoopsPerSocket = 10UL; +const TickType_t x150ms = 150UL / portTICK_PERIOD_MS; + + /* Remove compiler warning about unused parameters. */ + ( void ) pvParameters; + + /* It is assumed that this task is not created until the network is up, + so the IP address can be obtained immediately. store the IP address being + used in ulIPAddress. This is done so the socket can send to a different + port on the same IP address. */ + FreeRTOS_GetAddressConfiguration( &ulIPAddress, NULL, NULL, NULL ); + + /* This test sends to itself, so data sent from here is received by a server + socket on the same IP address. Setup the freertos_sockaddr structure with + this nodes IP address, and the port number being sent to. The strange + casting is to try and remove compiler warnings on 32 bit machines. */ + xDestinationAddress.sin_addr = ulIPAddress; + xDestinationAddress.sin_port = ( uint16_t ) ( ( uint32_t ) pvParameters ) & 0xffffUL; + xDestinationAddress.sin_port = FreeRTOS_htons( xDestinationAddress.sin_port ); + + for( ;; ) + { + /* Create the socket. */ + xClientSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP ); + configASSERT( xClientSocket != FREERTOS_INVALID_SOCKET ); + + /* The count is used to differentiate between different messages sent to + the server, and to break out of the do while loop below. */ + ulCount = 0UL; + + do + { + /* Create the string that is sent to the server. */ + sprintf( ( char * ) cString, "Server received (not zero copy): Message number %lu\r\n", ulCount ); + + /* Send the string to the socket. ulFlags is set to 0, so the zero + copy option is not selected. That means the data from cString[] is + copied into a network buffer inside FreeRTOS_sendto(), and cString[] + can be reused as soon as FreeRTOS_sendto() has returned. */ + lReturned = FreeRTOS_sendto( xClientSocket, ( void * ) cString, strlen( ( const char * ) cString ), 0, &xDestinationAddress, sizeof( xDestinationAddress ) ); + + ulCount++; + + } while( ( lReturned != FREERTOS_SOCKET_ERROR ) && ( ulCount < ulLoopsPerSocket ) ); + + FreeRTOS_closesocket( xClientSocket ); + + /* A short delay to prevent the messages printed by the server task + scrolling off the screen too quickly, and to prevent reduce the network + loading. */ + vTaskDelay( x150ms ); + } +} +/*-----------------------------------------------------------*/ + +static void prvSimpleServerTask( void *pvParameters ) +{ +int32_t lBytes; +uint8_t cReceivedString[ 60 ]; +struct freertos_sockaddr xClient, xBindAddress; +uint32_t xClientLength = sizeof( xClient ); +Socket_t xListeningSocket; + + /* Just to prevent compiler warnings. */ + ( void ) pvParameters; + + /* Attempt to open the socket. */ + xListeningSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP ); + configASSERT( xListeningSocket != FREERTOS_INVALID_SOCKET ); + + /* This test receives data sent from a different port on the same IP + address. Configure the freertos_sockaddr structure with the address being + bound to. The strange casting is to try and remove compiler warnings on 32 + bit machines. Note that this task is only created after the network is up, + so the IP address is valid here. */ + xBindAddress.sin_port = ( uint16_t ) ( ( uint32_t ) pvParameters ) & 0xffffUL; + xBindAddress.sin_port = FreeRTOS_htons( xBindAddress.sin_port ); + + /* Bind the socket to the port that the client task will send to. */ + FreeRTOS_bind( xListeningSocket, &xBindAddress, sizeof( xBindAddress ) ); + + for( ;; ) + { + /* Zero out the receive array so there is NULL at the end of the string + when it is printed out. */ + memset( cReceivedString, 0x00, sizeof( cReceivedString ) ); + + /* Receive data on the socket. ulFlags is zero, so the zero copy option + is not set and the received data is copied into the buffer pointed to by + cReceivedString. By default the block time is portMAX_DELAY. + xClientLength is not actually used by FreeRTOS_recvfrom(), but is set + appropriately in case future versions do use it. */ + lBytes = FreeRTOS_recvfrom( xListeningSocket, cReceivedString, sizeof( cReceivedString ), 0, &xClient, &xClientLength ); + + /* Error check. */ + configASSERT( lBytes == ( BaseType_t ) strlen( ( const char * ) cReceivedString ) ); + } +} +/*-----------------------------------------------------------*/ + +static void prvSimpleZeroCopyUDPClientTask( void *pvParameters ) +{ +Socket_t xClientSocket; +uint8_t *pucUDPPayloadBuffer; +struct freertos_sockaddr xDestinationAddress; +BaseType_t lReturned; +uint32_t ulCount = 0UL, ulIPAddress; +const uint32_t ulLoopsPerSocket = 10UL; +const char *pcStringToSend = "Server received (using zero copy): Message number "; +const TickType_t x150ms = 150UL / portTICK_PERIOD_MS; +/* 15 is added to ensure the number, \r\n and terminating zero fit. */ +const size_t xStringLength = strlen( pcStringToSend ) + 15; + + /* Remove compiler warning about unused parameters. */ + ( void ) pvParameters; + + /* It is assumed that this task is not created until the network is up, + so the IP address can be obtained immediately. store the IP address being + used in ulIPAddress. This is done so the socket can send to a different + port on the same IP address. */ + FreeRTOS_GetAddressConfiguration( &ulIPAddress, NULL, NULL, NULL ); + + /* This test sends to itself, so data sent from here is received by a server + socket on the same IP address. Setup the freertos_sockaddr structure with + this nodes IP address, and the port number being sent to. The strange + casting is to try and remove compiler warnings on 32 bit machines. */ + xDestinationAddress.sin_addr = ulIPAddress; + xDestinationAddress.sin_port = ( uint16_t ) ( ( uint32_t ) pvParameters ) & 0xffffUL; + xDestinationAddress.sin_port = FreeRTOS_htons( xDestinationAddress.sin_port ); + + for( ;; ) + { + /* Create the socket. */ + xClientSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP ); + configASSERT( xClientSocket != FREERTOS_INVALID_SOCKET ); + + /* The count is used to differentiate between different messages sent to + the server, and to break out of the do while loop below. */ + ulCount = 0UL; + + do + { + /* This task is going to send using the zero copy interface. The + data being sent is therefore written directly into a buffer that is + passed into, rather than copied into, the FreeRTOS_sendto() + function. + + First obtain a buffer of adequate length from the IP stack into which + the string will be written. Although a max delay is used, the actual + delay will be capped to ipconfigMAX_SEND_BLOCK_TIME_TICKS, hence + the do while loop is used to ensure a buffer is obtained. */ + do + { + } while( ( pucUDPPayloadBuffer = ( uint8_t * ) FreeRTOS_GetUDPPayloadBuffer( xStringLength, portMAX_DELAY ) ) == NULL ); + + /* A buffer was successfully obtained. Create the string that is + sent to the server. First the string is filled with zeros as this will + effectively be the null terminator when the string is received at the other + end. Note that the string is being written directly into the buffer + obtained from the IP stack above. */ + memset( ( void * ) pucUDPPayloadBuffer, 0x00, xStringLength ); + sprintf( ( char * ) pucUDPPayloadBuffer, "%s%lu\r\n", pcStringToSend, ulCount ); + + /* Pass the buffer into the send function. ulFlags has the + FREERTOS_ZERO_COPY bit set so the IP stack will take control of the + buffer rather than copy data out of the buffer. */ + lReturned = FreeRTOS_sendto( xClientSocket, /* The socket being sent to. */ + ( void * ) pucUDPPayloadBuffer, /* A pointer to the the data being sent. */ + strlen( ( const char * ) pucUDPPayloadBuffer ) + 1, /* The length of the data being sent - including the string's null terminator. */ + FREERTOS_ZERO_COPY, /* ulFlags with the FREERTOS_ZERO_COPY bit set. */ + &xDestinationAddress, /* Where the data is being sent. */ + sizeof( xDestinationAddress ) ); + + if( lReturned == 0 ) + { + /* The send operation failed, so this task is still responsible + for the buffer obtained from the IP stack. To ensure the buffer + is not lost it must either be used again, or, as in this case, + returned to the IP stack using FreeRTOS_ReleaseUDPPayloadBuffer(). + pucUDPPayloadBuffer can be safely re-used after this call. */ + FreeRTOS_ReleaseUDPPayloadBuffer( ( void * ) pucUDPPayloadBuffer ); + } + else + { + /* The send was successful so the IP stack is now managing the + buffer pointed to by pucUDPPayloadBuffer, and the IP stack will + return the buffer once it has been sent. pucUDPPayloadBuffer can + be safely re-used. */ + } + + ulCount++; + + } while( ( lReturned != FREERTOS_SOCKET_ERROR ) && ( ulCount < ulLoopsPerSocket ) ); + + FreeRTOS_closesocket( xClientSocket ); + + /* A short delay to prevent the messages scrolling off the screen too + quickly. */ + vTaskDelay( x150ms ); + } +} +/*-----------------------------------------------------------*/ + +static void prvSimpleZeroCopyServerTask( void *pvParameters ) +{ +int32_t lBytes; +uint8_t *pucUDPPayloadBuffer; +struct freertos_sockaddr xClient, xBindAddress; +uint32_t xClientLength = sizeof( xClient ), ulIPAddress; +Socket_t xListeningSocket; + + /* Just to prevent compiler warnings. */ + ( void ) pvParameters; + + /* Attempt to open the socket. */ + xListeningSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP ); + configASSERT( xListeningSocket != FREERTOS_INVALID_SOCKET ); + + /* This test receives data sent from a different port on the same IP address. + Obtain the nodes IP address. Configure the freertos_sockaddr structure with + the address being bound to. The strange casting is to try and remove + compiler warnings on 32 bit machines. Note that this task is only created + after the network is up, so the IP address is valid here. */ + FreeRTOS_GetAddressConfiguration( &ulIPAddress, NULL, NULL, NULL ); + xBindAddress.sin_addr = ulIPAddress; + xBindAddress.sin_port = ( uint16_t ) ( ( uint32_t ) pvParameters ) & 0xffffUL; + xBindAddress.sin_port = FreeRTOS_htons( xBindAddress.sin_port ); + + /* Bind the socket to the port that the client task will send to. */ + FreeRTOS_bind( xListeningSocket, &xBindAddress, sizeof( xBindAddress ) ); + + for( ;; ) + { + /* Receive data on the socket. ulFlags has the zero copy bit set + (FREERTOS_ZERO_COPY) indicating to the stack that a reference to the + received data should be passed out to this task using the second + parameter to the FreeRTOS_recvfrom() call. When this is done the + IP stack is no longer responsible for releasing the buffer, and + the task *must* return the buffer to the stack when it is no longer + needed. By default the block time is portMAX_DELAY. */ + lBytes = FreeRTOS_recvfrom( xListeningSocket, ( void * ) &pucUDPPayloadBuffer, 0, FREERTOS_ZERO_COPY, &xClient, &xClientLength ); + + /* Print the received characters. */ + if( lBytes > 0 ) + { + /* It is expected to receive one more byte than the string length as + the NULL terminator is also transmitted. */ + configASSERT( lBytes == ( ( BaseType_t ) strlen( ( const char * ) pucUDPPayloadBuffer ) + 1 ) ); + } + + if( lBytes >= 0 ) + { + /* The buffer *must* be freed once it is no longer needed. */ + FreeRTOS_ReleaseUDPPayloadBuffer( pucUDPPayloadBuffer ); + } + } +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/DemoTasks/TCPEchoClient_SingleTasks.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/DemoTasks/TCPEchoClient_SingleTasks.c new file mode 100644 index 0000000..e89d369 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/DemoTasks/TCPEchoClient_SingleTasks.c @@ -0,0 +1,358 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * A set of tasks are created that send TCP echo requests to the standard echo + * port (port 7) on the IP address set by the configECHO_SERVER_ADDR0 to + * configECHO_SERVER_ADDR3 constants, then wait for and verify the reply + * (another demo is avilable that demonstrates the reception being performed in + * a task other than that from with the request was made). + * + * See the following web page for essential demo usage and configuration + * details: + * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/examples_FreeRTOS_simulator.html + */ + +/* Standard includes. */ +#include +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" + +/* Exclude the whole file if FreeRTOSIPConfig.h is configured to use UDP only. */ +#if( ipconfigUSE_TCP == 1 ) + +/* The echo tasks create a socket, send out a number of echo requests, listen +for the echo reply, then close the socket again before starting over. This +delay is used between each iteration to ensure the network does not get too +congested. */ +#define echoLOOP_DELAY ( ( TickType_t ) 150 / portTICK_PERIOD_MS ) + +/* The echo server is assumed to be on port 7, which is the standard echo +protocol port. */ +#define echoECHO_PORT ( 7 ) + +/* The size of the buffers is a multiple of the MSS - the length of the data +sent is a pseudo random size between 20 and echoBUFFER_SIZES. */ +#define echoBUFFER_SIZE_MULTIPLIER ( 3 ) +#define echoBUFFER_SIZES ( ipconfigTCP_MSS * echoBUFFER_SIZE_MULTIPLIER ) + +/* The number of instances of the echo client task to create. */ +#define echoNUM_ECHO_CLIENTS ( 5 ) + +/*-----------------------------------------------------------*/ + +/* + * Uses a socket to send data to, then receive data from, the standard echo + * port number 7. + */ +static void prvEchoClientTask( void *pvParameters ); + +/* + * Creates a pseudo random sized buffer of data to send to the echo server. + */ +static BaseType_t prvCreateTxData( char *ucBuffer, uint32_t ulBufferLength ); + +/*-----------------------------------------------------------*/ + +/* Rx and Tx time outs are used to ensure the sockets do not wait too long for +missing data. */ +static const TickType_t xReceiveTimeOut = pdMS_TO_TICKS( 4000 ); +static const TickType_t xSendTimeOut = pdMS_TO_TICKS( 2000 ); + +/* Counters for each created task - for inspection only. */ +static uint32_t ulTxRxCycles[ echoNUM_ECHO_CLIENTS ] = { 0 }, + ulTxRxFailures[ echoNUM_ECHO_CLIENTS ] = { 0 }, + ulConnections[ echoNUM_ECHO_CLIENTS ] = { 0 }; + +/* Rx and Tx buffers for each created task. */ +static char cTxBuffers[ echoNUM_ECHO_CLIENTS ][ echoBUFFER_SIZES ], + cRxBuffers[ echoNUM_ECHO_CLIENTS ][ echoBUFFER_SIZES ]; + +/*-----------------------------------------------------------*/ + +void vStartTCPEchoClientTasks_SingleTasks( uint16_t usTaskStackSize, UBaseType_t uxTaskPriority ) +{ +BaseType_t x; + + /* Create the echo client tasks. */ + for( x = 0; x < echoNUM_ECHO_CLIENTS; x++ ) + { + xTaskCreate( prvEchoClientTask, /* The function that implements the task. */ + "Echo0", /* Just a text name for the task to aid debugging. */ + usTaskStackSize, /* The stack size is defined in FreeRTOSIPConfig.h. */ + ( void * ) x, /* The task parameter, not used in this case. */ + uxTaskPriority, /* The priority assigned to the task is defined in FreeRTOSConfig.h. */ + NULL ); /* The task handle is not used. */ + } +} +/*-----------------------------------------------------------*/ + +static void prvEchoClientTask( void *pvParameters ) +{ +Socket_t xSocket; +struct freertos_sockaddr xEchoServerAddress; +int32_t lLoopCount = 0UL; +const int32_t lMaxLoopCount = 1; +volatile uint32_t ulTxCount = 0UL; +BaseType_t xReceivedBytes, xReturned, xInstance; +BaseType_t lTransmitted, lStringLength; +char *pcTransmittedString, *pcReceivedString; +WinProperties_t xWinProps; +TickType_t xTimeOnEntering; + + /* Fill in the buffer and window sizes that will be used by the socket. */ + xWinProps.lTxBufSize = 6 * ipconfigTCP_MSS; + xWinProps.lTxWinSize = 3; + xWinProps.lRxBufSize = 6 * ipconfigTCP_MSS; + xWinProps.lRxWinSize = 3; + + /* This task can be created a number of times. Each instance is numbered + to enable each instance to use a different Rx and Tx buffer. The number is + passed in as the task's parameter. */ + xInstance = ( BaseType_t ) pvParameters; + + /* Point to the buffers to be used by this instance of this task. */ + pcTransmittedString = &( cTxBuffers[ xInstance ][ 0 ] ); + pcReceivedString = &( cRxBuffers[ xInstance ][ 0 ] ); + + /* Echo requests are sent to the echo server. The address of the echo + server is configured by the constants configECHO_SERVER_ADDR0 to + configECHO_SERVER_ADDR3 in FreeRTOSConfig.h. */ + xEchoServerAddress.sin_port = FreeRTOS_htons( echoECHO_PORT ); + xEchoServerAddress.sin_addr = FreeRTOS_inet_addr_quick( configECHO_SERVER_ADDR0, + configECHO_SERVER_ADDR1, + configECHO_SERVER_ADDR2, + configECHO_SERVER_ADDR3 ); + + for( ;; ) + { + /* Create a TCP socket. */ + xSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_STREAM, FREERTOS_IPPROTO_TCP ); + configASSERT( xSocket != FREERTOS_INVALID_SOCKET ); + + /* Set a time out so a missing reply does not cause the task to block + indefinitely. */ + FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_RCVTIMEO, &xReceiveTimeOut, sizeof( xReceiveTimeOut ) ); + FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_SNDTIMEO, &xSendTimeOut, sizeof( xSendTimeOut ) ); + + /* Set the window and buffer sizes. */ + FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_WIN_PROPERTIES, ( void * ) &xWinProps, sizeof( xWinProps ) ); + + /* Connect to the echo server. */ + if( FreeRTOS_connect( xSocket, &xEchoServerAddress, sizeof( xEchoServerAddress ) ) == 0 ) + { + ulConnections[ xInstance ]++; + + /* Send a number of echo requests. */ + for( lLoopCount = 0; lLoopCount < lMaxLoopCount; lLoopCount++ ) + { + /* Create the string that is sent to the echo server. */ + lStringLength = prvCreateTxData( pcTransmittedString, echoBUFFER_SIZES ); + + /* Add in some unique text at the front of the string. */ + sprintf( pcTransmittedString, "TxRx message number %u", ulTxCount ); + ulTxCount++; + + /* Send the string to the socket. */ + lTransmitted = FreeRTOS_send( xSocket, /* The socket being sent to. */ + ( void * ) pcTransmittedString, /* The data being sent. */ + lStringLength, /* The length of the data being sent. */ + 0 ); /* No flags. */ + + if( lTransmitted < 0 ) + { + /* Error? */ + break; + } + + /* Clear the buffer into which the echoed string will be + placed. */ + memset( ( void * ) pcReceivedString, 0x00, echoBUFFER_SIZES ); + xReceivedBytes = 0; + + /* Receive data echoed back to the socket. */ + while( xReceivedBytes < lTransmitted ) + { + xReturned = FreeRTOS_recv( xSocket, /* The socket being received from. */ + &( pcReceivedString[ xReceivedBytes ] ),/* The buffer into which the received data will be written. */ + lStringLength - xReceivedBytes, /* The size of the buffer provided to receive the data. */ + 0 ); /* No flags. */ + + if( xReturned < 0 ) + { + /* Error occurred. Latch it so it can be detected + below. */ + xReceivedBytes = xReturned; + break; + } + else if( xReturned == 0 ) + { + /* Timed out. */ + break; + } + else + { + /* Keep a count of the bytes received so far. */ + xReceivedBytes += xReturned; + } + } + + /* If an error occurred it will be latched in xReceivedBytes, + otherwise xReceived bytes will be just that - the number of + bytes received from the echo server. */ + if( xReceivedBytes > 0 ) + { + /* Compare the transmitted string to the received string. */ + configASSERT( strncmp( pcReceivedString, pcTransmittedString, lTransmitted ) == 0 ); + if( strncmp( pcReceivedString, pcTransmittedString, lTransmitted ) == 0 ) + { + /* The echo reply was received without error. */ + ulTxRxCycles[ xInstance ]++; + } + else + { + /* The received string did not match the transmitted + string. */ + ulTxRxFailures[ xInstance ]++; + break; + } + } + else if( xReceivedBytes < 0 ) + { + /* FreeRTOS_recv() returned an error. */ + break; + } + else + { + /* Timed out without receiving anything? */ + break; + } + } + + /* Finished using the connected socket, initiate a graceful close: + FIN, FIN+ACK, ACK. */ + FreeRTOS_shutdown( xSocket, FREERTOS_SHUT_RDWR ); + + /* Expect FreeRTOS_recv() to return an error once the shutdown is + complete. */ + xTimeOnEntering = xTaskGetTickCount(); + do + { + xReturned = FreeRTOS_recv( xSocket, /* The socket being received from. */ + &( pcReceivedString[ 0 ] ), /* The buffer into which the received data will be written. */ + echoBUFFER_SIZES, /* The size of the buffer provided to receive the data. */ + 0 ); + + if( xReturned < 0 ) + { + break; + } + + } while( ( xTaskGetTickCount() - xTimeOnEntering ) < xReceiveTimeOut ); + } + + /* Close this socket before looping back to create another. */ + FreeRTOS_closesocket( xSocket ); + + /* Pause for a short while to ensure the network is not too + congested. */ + vTaskDelay( echoLOOP_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvCreateTxData( char *cBuffer, uint32_t ulBufferLength ) +{ +BaseType_t lCharactersToAdd, lCharacter; +char cChar = '0'; +const BaseType_t lMinimumLength = 60; + + /* Randomise the number of characters that will be sent in the echo + request. */ + do + { + lCharactersToAdd = ipconfigRAND32() % ( ulBufferLength - 20UL ); + } while ( ( lCharactersToAdd == 0 ) || ( lCharactersToAdd < lMinimumLength ) ); /* Must be at least enough to add the unique text to the start of the string later. */ + + /* Fill the buffer. */ + for( lCharacter = 0; lCharacter < lCharactersToAdd; lCharacter++ ) + { + cBuffer[ lCharacter ] = cChar; + cChar++; + + if( cChar > '~' ) + { + cChar = '0'; + } + } + + return lCharactersToAdd; +} +/*-----------------------------------------------------------*/ + +BaseType_t xAreSingleTaskTCPEchoClientsStillRunning( void ) +{ +static uint32_t ulLastEchoSocketCount[ echoNUM_ECHO_CLIENTS ] = { 0 }, ulLastConnections[ echoNUM_ECHO_CLIENTS ] = { 0 }; +BaseType_t xReturn = pdPASS, x; + + /* Return fail is the number of cycles does not increment between + consecutive calls. */ + for( x = 0; x < echoNUM_ECHO_CLIENTS; x++ ) + { + if( ulTxRxCycles[ x ] == ulLastEchoSocketCount[ x ] ) + { + xReturn = pdFAIL; + } + else + { + ulLastEchoSocketCount[ x ] = ulTxRxCycles[ x ]; + } + + if( ulConnections[ x ] == ulLastConnections[ x ] ) + { + xReturn = pdFAIL; + } + else + { + ulConnections[ x ] = ulLastConnections[ x ]; + } + } + + return xReturn; +} + +#endif /* ipconfigUSE_TCP */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/DemoTasks/include/SimpleTCPEchoServer.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/DemoTasks/include/SimpleTCPEchoServer.h new file mode 100644 index 0000000..7409e67 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/DemoTasks/include/SimpleTCPEchoServer.h @@ -0,0 +1,76 @@ +/* + FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef SIMPLE_TCP_ECHO_SERVER_H +#define SIMPLE_TCP_ECHO_SERVER_H + +void vStartSimpleTCPServerTasks( uint16_t usStackSize, BaseType_t uxPriority ); +BaseType_t xAreTCPEchoServersStillRunning( void ); + +#endif /* SIMPLE_TCP_ECHO_SERVER_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/DemoTasks/include/SimpleUDPClientAndServer.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/DemoTasks/include/SimpleUDPClientAndServer.h new file mode 100644 index 0000000..342ab12 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/DemoTasks/include/SimpleUDPClientAndServer.h @@ -0,0 +1,33 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef SIMPLE_UDP_CLIENT_AND_SERVER_H +#define SIMPLE_UDPCLIENT_AND_SERVER_H + +void vStartSimpleUDPClientServerTasks( uint16_t usStackSize, uint32_t ulsPort, UBaseType_t uxPriority ); + +#endif /* SIMPLE_UDPCLIENT_AND_SERVER_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/DemoTasks/include/TCPEchoClient_SingleTasks.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/DemoTasks/include/TCPEchoClient_SingleTasks.h new file mode 100644 index 0000000..0f4676f --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/DemoTasks/include/TCPEchoClient_SingleTasks.h @@ -0,0 +1,40 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef SINGLE_TASK_TCP_ECHO_CLIENTS_H +#define SINGLE_TASK_TCP_ECHO_CLIENTS_H + +/* + * Create the TCP echo client tasks. This is the version where an echo request + * is made from the same task that listens for the echo reply. + */ +void vStartTCPEchoClientTasks_SingleTasks( uint16_t usTaskStackSize, UBaseType_t uxTaskPriority ); +BaseType_t xAreSingleTaskTCPEchoClientsStillRunning( void ); + +#endif /* SINGLE_TASK_TCP_ECHO_CLIENTS_H */ + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/FreeRTOSConfig.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/FreeRTOSConfig.h new file mode 100644 index 0000000..7fdff10 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/FreeRTOSConfig.h @@ -0,0 +1,219 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * http://www.freertos.org/a00110.html + * + * The bottom of this file contains some constants specific to running the UDP + * stack in this demo. Constants specific to FreeRTOS+TCP itself (rather than + * the demo) are contained in FreeRTOSIPConfig.h. + *----------------------------------------------------------*/ +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#define configMAX_PRIORITIES ( 7 ) +#define configTICK_RATE_HZ ( 1000 ) /* In this non-real time simulated environment the tick frequency has to be at least a multiple of the Win32 tick frequency, and therefore very slow. */ +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 60 ) /* In this simulated case, the stack only has to hold one small structure as the real stack is part of the Win32 thread. */ +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 2048U * 1024U ) ) +#define configMAX_TASK_NAME_LEN ( 15 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 0 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 3 /* FreeRTOS+FAT requires 2 pointers if a CWD is supported. */ + +/* Hook function related definitions. */ +#define configUSE_TICK_HOOK 0 +#define configUSE_IDLE_HOOK 1 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configCHECK_FOR_STACK_OVERFLOW 0 /* Not applicable to the Win32 port. */ + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + +/* Event group related definitions. */ +#define configUSE_EVENT_GROUPS 1 + +/* Run time stats gathering definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTimerGetTimerTaskHandle 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xQueueGetMutexHolder 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xEventGroupSetBitsFromISR 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_pcTaskGetTaskName 1 + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. configUSE_STATS_FORMATTING_FUNCTIONS +is set to 2 so the formatting functions are included without the stdio.h being +included in tasks.c. That is because this project defines its own sprintf() +functions. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + +/* Assert call defined for debug builds. */ +#ifdef _DEBUG + extern void vAssertCalled( const char *pcFile, uint32_t ulLine ); + #define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ ) +#endif /* _DEBUG */ + + + +/* Application specific definitions follow. **********************************/ + +/* If configINCLUDE_DEMO_DEBUG_STATS is set to one, then a few basic IP trace +macros are defined to gather some UDP stack statistics that can then be viewed +through the CLI interface. */ +#define configINCLUDE_DEMO_DEBUG_STATS 1 + +/* The size of the global output buffer that is available for use when there +are multiple command interpreters running at once (for example, one on a UART +and one on TCP/IP). This is done to prevent an output buffer being defined by +each implementation - which would waste RAM. In this case, there is only one +command interpreter running, and it has its own local output buffer, so the +global buffer is just set to be one byte long as it is not used and should not +take up unnecessary RAM. */ +#define configCOMMAND_INT_MAX_OUTPUT_SIZE 1 + +/* Only used when running in the FreeRTOS Windows simulator. Defines the +priority of the task used to simulate Ethernet interrupts. */ +#define configMAC_ISR_SIMULATOR_PRIORITY ( configMAX_PRIORITIES - 1 ) + +/* This demo creates a virtual network connection by accessing the raw Ethernet +or WiFi data to and from a real network connection. Many computers have more +than one real network port, and configNETWORK_INTERFACE_TO_USE is used to tell +the demo which real port should be used to create the virtual port. The ports +available are displayed on the console when the application is executed. For +example, on my development laptop setting configNETWORK_INTERFACE_TO_USE to 4 +results in the wired network being used, while setting +configNETWORK_INTERFACE_TO_USE to 2 results in the wireless network being +used. */ +#define configNETWORK_INTERFACE_TO_USE 2L + +/* The address of an echo server that will be used by the two demo echo client +tasks. +http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/TCP_Echo_Clients.html +http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/UDP_Echo_Clients.html */ +#define configECHO_SERVER_ADDR0 192 +#define configECHO_SERVER_ADDR1 168 +#define configECHO_SERVER_ADDR2 0 +#define configECHO_SERVER_ADDR3 11 + +/* Default MAC address configuration. The demo creates a virtual network +connection that uses this MAC address by accessing the raw Ethernet/WiFi data +to and from a real network connection on the host PC. See the +configNETWORK_INTERFACE_TO_USE definition above for information on how to +configure the real network connection to use. */ +#define configMAC_ADDR0 0x00 +#define configMAC_ADDR1 0x11 +#define configMAC_ADDR2 0x22 +#define configMAC_ADDR3 0x33 +#define configMAC_ADDR4 0x44 +#define configMAC_ADDR5 0x41 + +/* Default IP address configuration. Used in ipconfigUSE_DNS is set to 0, or +ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */ +#define configIP_ADDR0 10 +#define configIP_ADDR1 10 +#define configIP_ADDR2 10 +#define configIP_ADDR3 200 + +/* Default gateway IP address configuration. Used in ipconfigUSE_DNS is set to +0, or ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */ +#define configGATEWAY_ADDR0 10 +#define configGATEWAY_ADDR1 10 +#define configGATEWAY_ADDR2 10 +#define configGATEWAY_ADDR3 1 + +/* Default DNS server configuration. OpenDNS addresses are 208.67.222.222 and +208.67.220.220. Used in ipconfigUSE_DNS is set to 0, or ipconfigUSE_DNS is set +to 1 but a DNS server cannot be contacted.*/ +#define configDNS_SERVER_ADDR0 208 +#define configDNS_SERVER_ADDR1 67 +#define configDNS_SERVER_ADDR2 222 +#define configDNS_SERVER_ADDR3 222 + +/* Default netmask configuration. Used in ipconfigUSE_DNS is set to 0, or +ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */ +#define configNET_MASK0 255 +#define configNET_MASK1 0 +#define configNET_MASK2 0 +#define configNET_MASK3 0 + +/* The UDP port to which print messages are sent. */ +#define configPRINT_PORT ( 15000 ) + +#if( defined( _MSC_VER ) && ( _MSC_VER <= 1600 ) && !defined( snprintf ) ) + /* Map to Windows names. */ + #define snprintf _snprintf + #define vsnprintf _vsnprintf +#endif + +/* Visual studio does not have an implementation of strcasecmp(). */ +#define strcasecmp _stricmp +#define strncasecmp _strnicmp +#define strcmpi _strcmpi + +#endif /* FREERTOS_CONFIG_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/FreeRTOSIPConfig.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/FreeRTOSIPConfig.h new file mode 100644 index 0000000..4aa549e --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/FreeRTOSIPConfig.h @@ -0,0 +1,307 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +/***************************************************************************** + * + * See the following URL for configuration information. + * http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/TCP_IP_Configuration.html + * + *****************************************************************************/ + +#ifndef FREERTOS_IP_CONFIG_H +#define FREERTOS_IP_CONFIG_H + +/* Prototype for the function used to print out. In this case it prints to the +console before the network is connected then a UDP port after the network has +connected. */ +extern void vLoggingPrintf( const char *pcFormatString, ... ); + +/* Set to 1 to print out debug messages. If ipconfigHAS_DEBUG_PRINTF is set to +1 then FreeRTOS_debug_printf should be defined to the function used to print +out the debugging messages. */ +#define ipconfigHAS_DEBUG_PRINTF 0 +#if( ipconfigHAS_DEBUG_PRINTF == 1 ) + #define FreeRTOS_debug_printf(X) vLoggingPrintf X +#endif + +/* Set to 1 to print out non debugging messages, for example the output of the +FreeRTOS_netstat() command, and ping replies. If ipconfigHAS_PRINTF is set to 1 +then FreeRTOS_printf should be set to the function used to print out the +messages. */ +#define ipconfigHAS_PRINTF 1 +#if( ipconfigHAS_PRINTF == 1 ) + #define FreeRTOS_printf(X) vLoggingPrintf X +#endif + +/* Define the byte order of the target MCU (the MCU FreeRTOS+TCP is executing +on). Valid options are pdFREERTOS_BIG_ENDIAN and pdFREERTOS_LITTLE_ENDIAN. */ +#define ipconfigBYTE_ORDER pdFREERTOS_LITTLE_ENDIAN + +/* If the network card/driver includes checksum offloading (IP/TCP/UDP checksums) +then set ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM to 1 to prevent the software +stack repeating the checksum calculations. */ +#define ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM 1 + +/* Several API's will block until the result is known, or the action has been +performed, for example FreeRTOS_send() and FreeRTOS_recv(). The timeouts can be +set per socket, using setsockopt(). If not set, the times below will be +used as defaults. */ +#define ipconfigSOCK_DEFAULT_RECEIVE_BLOCK_TIME ( 5000 ) +#define ipconfigSOCK_DEFAULT_SEND_BLOCK_TIME ( 5000 ) + +/* Include support for LLMNR: Link-local Multicast Name Resolution +(non-Microsoft) */ +#define ipconfigUSE_LLMNR ( 1 ) + +/* Include support for NBNS: NetBIOS Name Service (Microsoft) */ +#define ipconfigUSE_NBNS ( 1 ) + +/* Include support for DNS caching. For TCP, having a small DNS cache is very +useful. When a cache is present, ipconfigDNS_REQUEST_ATTEMPTS can be kept low +and also DNS may use small timeouts. If a DNS reply comes in after the DNS +socket has been destroyed, the result will be stored into the cache. The next +call to FreeRTOS_gethostbyname() will return immediately, without even creating +a socket. */ +#define ipconfigUSE_DNS_CACHE ( 1 ) +#define ipconfigDNS_CACHE_NAME_LENGTH ( 16 ) +#define ipconfigDNS_CACHE_ENTRIES ( 4 ) +#define ipconfigDNS_REQUEST_ATTEMPTS ( 2 ) + +/* The IP stack executes it its own task (although any application task can make +use of its services through the published sockets API). ipconfigUDP_TASK_PRIORITY +sets the priority of the task that executes the IP stack. The priority is a +standard FreeRTOS task priority so can take any value from 0 (the lowest +priority) to (configMAX_PRIORITIES - 1) (the highest priority). +configMAX_PRIORITIES is a standard FreeRTOS configuration parameter defined in +FreeRTOSConfig.h, not FreeRTOSIPConfig.h. Consideration needs to be given as to +the priority assigned to the task executing the IP stack relative to the +priority assigned to tasks that use the IP stack. */ +#define ipconfigIP_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) + +/* The size, in words (not bytes), of the stack allocated to the FreeRTOS+TCP +task. This setting is less important when the FreeRTOS Win32 simulator is used +as the Win32 simulator only stores a fixed amount of information on the task +stack. FreeRTOS includes optional stack overflow detection, see: +http://www.freertos.org/Stacks-and-stack-overflow-checking.html */ +#define ipconfigIP_TASK_STACK_SIZE_WORDS ( configMINIMAL_STACK_SIZE * 5 ) + +/* ipconfigRAND32() is called by the IP stack to generate random numbers for +things such as a DHCP transaction number or initial sequence number. Random +number generation is performed via this macro to allow applications to use their +own random number generation method. For example, it might be possible to +generate a random number by sampling noise on an analogue input. */ +extern UBaseType_t uxRand(); +#define ipconfigRAND32() uxRand() + +/* If ipconfigUSE_NETWORK_EVENT_HOOK is set to 1 then FreeRTOS+TCP will call the +network event hook at the appropriate times. If ipconfigUSE_NETWORK_EVENT_HOOK +is not set to 1 then the network event hook will never be called. See +http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/API/vApplicationIPNetworkEventHook.shtml +*/ +#define ipconfigUSE_NETWORK_EVENT_HOOK 1 + +/* Sockets have a send block time attribute. If FreeRTOS_sendto() is called but +a network buffer cannot be obtained then the calling task is held in the Blocked +state (so other tasks can continue to executed) until either a network buffer +becomes available or the send block time expires. If the send block time expires +then the send operation is aborted. The maximum allowable send block time is +capped to the value set by ipconfigMAX_SEND_BLOCK_TIME_TICKS. Capping the +maximum allowable send block time prevents prevents a deadlock occurring when +all the network buffers are in use and the tasks that process (and subsequently +free) the network buffers are themselves blocked waiting for a network buffer. +ipconfigMAX_SEND_BLOCK_TIME_TICKS is specified in RTOS ticks. A time in +milliseconds can be converted to a time in ticks by dividing the time in +milliseconds by portTICK_PERIOD_MS. */ +#define ipconfigUDP_MAX_SEND_BLOCK_TIME_TICKS ( 5000 / portTICK_PERIOD_MS ) + +/* If ipconfigUSE_DHCP is 1 then FreeRTOS+TCP will attempt to retrieve an IP +address, netmask, DNS server address and gateway address from a DHCP server. If +ipconfigUSE_DHCP is 0 then FreeRTOS+TCP will use a static IP address. The +stack will revert to using the static IP address even when ipconfigUSE_DHCP is +set to 1 if a valid configuration cannot be obtained from a DHCP server for any +reason. The static configuration used is that passed into the stack by the +FreeRTOS_IPInit() function call. */ +#define ipconfigUSE_DHCP 1 + +/* When ipconfigUSE_DHCP is set to 1, DHCP requests will be sent out at +increasing time intervals until either a reply is received from a DHCP server +and accepted, or the interval between transmissions reaches +ipconfigMAXIMUM_DISCOVER_TX_PERIOD. The IP stack will revert to using the +static IP address passed as a parameter to FreeRTOS_IPInit() if the +re-transmission time interval reaches ipconfigMAXIMUM_DISCOVER_TX_PERIOD without +a DHCP reply being received. */ +#define ipconfigMAXIMUM_DISCOVER_TX_PERIOD ( 120000 / portTICK_PERIOD_MS ) + +/* The ARP cache is a table that maps IP addresses to MAC addresses. The IP +stack can only send a UDP message to a remove IP address if it knowns the MAC +address associated with the IP address, or the MAC address of the router used to +contact the remote IP address. When a UDP message is received from a remote IP +address the MAC address and IP address are added to the ARP cache. When a UDP +message is sent to a remote IP address that does not already appear in the ARP +cache then the UDP message is replaced by a ARP message that solicits the +required MAC address information. ipconfigARP_CACHE_ENTRIES defines the maximum +number of entries that can exist in the ARP table at any one time. */ +#define ipconfigARP_CACHE_ENTRIES 6 + +/* ARP requests that do not result in an ARP response will be re-transmitted a +maximum of ipconfigMAX_ARP_RETRANSMISSIONS times before the ARP request is +aborted. */ +#define ipconfigMAX_ARP_RETRANSMISSIONS ( 5 ) + +/* ipconfigMAX_ARP_AGE defines the maximum time between an entry in the ARP +table being created or refreshed and the entry being removed because it is stale. +New ARP requests are sent for ARP cache entries that are nearing their maximum +age. ipconfigMAX_ARP_AGE is specified in tens of seconds, so a value of 150 is +equal to 1500 seconds (or 25 minutes). */ +#define ipconfigMAX_ARP_AGE 150 + +/* Implementing FreeRTOS_inet_addr() necessitates the use of string handling +routines, which are relatively large. To save code space the full +FreeRTOS_inet_addr() implementation is made optional, and a smaller and faster +alternative called FreeRTOS_inet_addr_quick() is provided. FreeRTOS_inet_addr() +takes an IP in decimal dot format (for example, "192.168.0.1") as its parameter. +FreeRTOS_inet_addr_quick() takes an IP address as four separate numerical octets +(for example, 192, 168, 0, 1) as its parameters. If +ipconfigINCLUDE_FULL_INET_ADDR is set to 1 then both FreeRTOS_inet_addr() and +FreeRTOS_indet_addr_quick() are available. If ipconfigINCLUDE_FULL_INET_ADDR is +not set to 1 then only FreeRTOS_indet_addr_quick() is available. */ +#define ipconfigINCLUDE_FULL_INET_ADDR 1 + +/* ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS defines the total number of network buffer that +are available to the IP stack. The total number of network buffers is limited +to ensure the total amount of RAM that can be consumed by the IP stack is capped +to a pre-determinable value. */ +#define ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS 60 + +/* A FreeRTOS queue is used to send events from application tasks to the IP +stack. ipconfigEVENT_QUEUE_LENGTH sets the maximum number of events that can +be queued for processing at any one time. The event queue must be a minimum of +5 greater than the total number of network buffers. */ +#define ipconfigEVENT_QUEUE_LENGTH ( ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS + 5 ) + +/* The address of a socket is the combination of its IP address and its port +number. FreeRTOS_bind() is used to manually allocate a port number to a socket +(to 'bind' the socket to a port), but manual binding is not normally necessary +for client sockets (those sockets that initiate outgoing connections rather than +wait for incoming connections on a known port number). If +ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND is set to 1 then calling +FreeRTOS_sendto() on a socket that has not yet been bound will result in the IP +stack automatically binding the socket to a port number from the range +socketAUTO_PORT_ALLOCATION_START_NUMBER to 0xffff. If +ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND is set to 0 then calling FreeRTOS_sendto() +on a socket that has not yet been bound will result in the send operation being +aborted. */ +#define ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND 1 + +/* Defines the Time To Live (TTL) values used in outgoing UDP packets. */ +#define ipconfigUDP_TIME_TO_LIVE 128 +#define ipconfigTCP_TIME_TO_LIVE 128 /* also defined in FreeRTOSIPConfigDefaults.h */ + +/* USE_TCP: Use TCP and all its features */ +#define ipconfigUSE_TCP ( 1 ) + +/* USE_WIN: Let TCP use windowing mechanism. */ +#define ipconfigUSE_TCP_WIN ( 1 ) + +/* The MTU is the maximum number of bytes the payload of a network frame can +contain. For normal Ethernet V2 frames the maximum MTU is 1500. Setting a +lower value can save RAM, depending on the buffer management scheme used. If +ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is 1 then (ipconfigNETWORK_MTU - 28) must +be divisible by 8. */ +#define ipconfigNETWORK_MTU 1200 + +/* Set ipconfigUSE_DNS to 1 to include a basic DNS client/resolver. DNS is used +through the FreeRTOS_gethostbyname() API function. */ +#define ipconfigUSE_DNS 1 + +/* If ipconfigREPLY_TO_INCOMING_PINGS is set to 1 then the IP stack will +generate replies to incoming ICMP echo (ping) requests. */ +#define ipconfigREPLY_TO_INCOMING_PINGS 1 + +/* If ipconfigSUPPORT_OUTGOING_PINGS is set to 1 then the +FreeRTOS_SendPingRequest() API function is available. */ +#define ipconfigSUPPORT_OUTGOING_PINGS 0 + +/* If ipconfigSUPPORT_SELECT_FUNCTION is set to 1 then the FreeRTOS_select() +(and associated) API function is available. */ +#define ipconfigSUPPORT_SELECT_FUNCTION 1 + +/* If ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES is set to 1 then Ethernet frames +that are not in Ethernet II format will be dropped. This option is included for +potential future IP stack developments. */ +#define ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES 1 + +/* If ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES is set to 1 then it is the +responsibility of the Ethernet interface to filter out packets that are of no +interest. If the Ethernet interface does not implement this functionality, then +set ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES to 0 to have the IP stack +perform the filtering instead (it is much less efficient for the stack to do it +because the packet will already have been passed into the stack). If the +Ethernet driver does all the necessary filtering in hardware then software +filtering can be removed by using a value other than 1 or 0. */ +#define ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES 1 + +/* The windows simulator cannot really simulate MAC interrupts, and needs to +block occasionally to allow other tasks to run. */ +#define configWINDOWS_MAC_INTERRUPT_SIMULATOR_DELAY ( 20 / portTICK_PERIOD_MS ) + +/* Advanced only: in order to access 32-bit fields in the IP packets with +32-bit memory instructions, all packets will be stored 32-bit-aligned, plus 16-bits. +This has to do with the contents of the IP-packets: all 32-bit fields are +32-bit-aligned, plus 16-bit(!) */ +#define ipconfigPACKET_FILLER_SIZE 2 + +/* Define the size of the pool of TCP window descriptors. On the average, each +TCP socket will use up to 2 x 6 descriptors, meaning that it can have 2 x 6 +outstanding packets (for Rx and Tx). When using up to 10 TP sockets +simultaneously, one could define TCP_WIN_SEG_COUNT as 120. */ +#define ipconfigTCP_WIN_SEG_COUNT 240 + +/* Each TCP socket has a circular buffers for Rx and Tx, which have a fixed +maximum size. Define the size of Rx buffer for TCP sockets. */ +#define ipconfigTCP_RX_BUFFER_LENGTH ( 1000 ) + +/* Define the size of Tx buffer for TCP sockets. */ +#define ipconfigTCP_TX_BUFFER_LENGTH ( 1000 ) + +/* When using call-back handlers, the driver may check if the handler points to +real program memory (RAM or flash) or just has a random non-zero value. */ +#define ipconfigIS_VALID_PROG_ADDRESS(x) ( (x) != NULL ) + +/* Include support for TCP hang protection. All sockets in a connecting or +disconnecting stage will timeout after a period of non-activity. */ +#define ipconfigTCP_HANG_PROTECTION ( 1 ) +#define ipconfigTCP_HANG_PROTECTION_TIME ( 30 ) + +/* Include support for TCP keep-alive messages. */ +#define ipconfigTCP_KEEP_ALIVE ( 1 ) +#define ipconfigTCP_KEEP_ALIVE_INTERVAL ( 20 ) /* in seconds */ + +#define portINLINE __inline + +#endif /* FREERTOS_IP_CONFIG_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/FreeRTOS_Plus_TCP_Minimal.sln b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/FreeRTOS_Plus_TCP_Minimal.sln new file mode 100644 index 0000000..b362f36 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/FreeRTOS_Plus_TCP_Minimal.sln @@ -0,0 +1,23 @@ + +Microsoft Visual Studio Solution File, Format Version 11.00 +# Visual Studio 2010 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "RTOSDemo", "WIN32.vcxproj", "{C686325E-3261-42F7-AEB1-DDE5280E1CEB}" +EndProject +Global + GlobalSection(TestCaseManagementSettings) = postSolution + CategoryFile = FreeRTOS_Plus_TCP_Minimal.vsmdi + EndGlobalSection + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Win32 = Debug|Win32 + Release|Win32 = Release|Win32 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.ActiveCfg = Debug|Win32 + {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.Build.0 = Debug|Win32 + {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.ActiveCfg = Release|Win32 + {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.Build.0 = Release|Win32 + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/FreeRTOS_Plus_TCP_Minimal.suo b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/FreeRTOS_Plus_TCP_Minimal.suo new file mode 100644 index 0000000..6a1e0eb Binary files /dev/null and b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/FreeRTOS_Plus_TCP_Minimal.suo differ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/ReadMe.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/ReadMe.txt new file mode 100644 index 0000000..682a18c --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/ReadMe.txt @@ -0,0 +1,34 @@ +The FreeRTOS+TCP source code and example projects are currently provided in +their own .zip file download, but using the directory structure of the official +FreeRTOS .zip file download. This allow the projects to be seamlessly moved +from one download to the other, but can seem strange when the files are viewed +in isolation. + +The minimal FreeRTOS+TCP Visual Studio project file is in the following directory: +FreeRTOS-Plus\Demo\FreeRTOS_Plus_TCP_Minimal_Windows_Simulator + +The minimal project is a cut down version of the full Windows demo that only +includes examples of simple TCP and UDP clients. The instructions for the full +Windows demo are still relevant though as they describe how to set up the +WinPCap development environment, how to set the IP address, and other such +items. Note that, as delivered, configUSE_DHCP is set to 0, so a static IP +address is used. The instructions are provided on the following URL: +http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/examples_FreeRTOS_simulator.html + +The UDP client example included in the minimal project is described on the +following URL: +http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/UDP_client_server.html + +The TCP client example included in the minimal project is described on the +following URL: +http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/TCP_Echo_Clients.html + +A description of the FreeRTOS+TCP source code directory is provided on the +following URL: +http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/TCP_Networking_Tutorial_Source_Code_Organisation.html + +A description of the way the main FreeRTOS .zip file download source code is +organised is provided on the following URL: +http://www.freertos.org/a00017.html + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/Read_Me_Build_Instructions.url b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/Read_Me_Build_Instructions.url new file mode 100644 index 0000000..3ceab76 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/Read_Me_Build_Instructions.url @@ -0,0 +1,6 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 +[InternetShortcut] +URL=http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/examples_FreeRTOS_simulator.html +IDList= +HotKey=0 diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WIN32.vcxproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WIN32.vcxproj new file mode 100644 index 0000000..a550436 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WIN32.vcxproj @@ -0,0 +1,197 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + + {C686325E-3261-42F7-AEB1-DDE5280E1CEB} + RTOSDemo + + + + Application + false + MultiByte + v140 + + + Application + false + MultiByte + v140 + + + + + + + + + + + + + + + <_ProjectFileVersion>10.0.30319.1 + .\Debug\ + .\Debug\ + true + .\Release\ + .\Release\ + false + AllRules.ruleset + + + + .\Debug/WIN32.tlb + + + + + Disabled + ..\..\Source\FreeRTOS-Plus-FAT\include;..\..\Source\FreeRTOS-Plus-FAT\portable\common;..\..\Source\FreeRTOS-Plus-TCP\protocols\include;..\..\Source\FreeRTOS-Plus-TCP\portable\BufferManagement;.\DemoTasks\include;..\..\Source\FreeRTOS-Plus-TCP\portable\Compiler\MSVC;.\WinPCap;..\..\..\FreeRTOS\Source\include;..\..\..\FreeRTOS\Source\portable\MSVC-MingW;..\..\Source\FreeRTOS-Plus-CLI;.\TraceMacros\Example1;..\..\Source\FreeRTOS-Plus-TCP\include;.;%(AdditionalIncludeDirectories) + WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) + true + EnableFastChecks + MultiThreadedDLL + .\Debug/WIN32.pch + .\Debug/ + .\Debug/ + .\Debug/ + Level4 + true + false + EditAndContinue + /wd4210 /wd4127 /wd4214 /wd4201 /wd4244 /wd4310 %(AdditionalOptions) + true + NotUsing + false + CompileAsC + + + _DEBUG;%(PreprocessorDefinitions) + 0x0c09 + + + .\Debug/RTOSDemo.exe + true + true + .\Debug/WIN32.pdb + Console + MachineX86 + wpcap.lib;%(AdditionalDependencies) + .\WinPCap + false + + + true + .\Debug/WIN32.bsc + + + + + .\Release/WIN32.tlb + + + + + MaxSpeed + OnlyExplicitInline + _WINSOCKAPI_;WIN32;NDEBUG;_CONSOLE;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) + true + MultiThreaded + true + .\Release/WIN32.pch + .\Release/ + .\Release/ + .\Release/ + Level3 + true + ..\Common\Utils;..\Common\ethernet\lwip-1.4.0\ports\win32\WinPCap;..\Common\ethernet\lwip-1.4.0\src\include\ipv4;..\Common\ethernet\lwip-1.4.0\src\include;..\..\Source\include;..\..\Source\portable\MSVC-MingW;..\Common\ethernet\lwip-1.4.0\ports\win32\include;..\Common\Include;.\lwIP_Apps;.;%(AdditionalIncludeDirectories) + + + NDEBUG;%(PreprocessorDefinitions) + 0x0c09 + + + .\Release/RTOSDemo.exe + true + .\Release/WIN32.pdb + Console + MachineX86 + ..\Common\ethernet\lwip-1.4.0\ports\win32\WinPCap + wpcap.lib;%(AdditionalDependencies) + + + true + .\Release/WIN32.bsc + + + + + + + + + + + + + + + + + + + + + + + + + + + %(AdditionalIncludeDirectories) + %(PreprocessorDefinitions) + %(PreprocessorDefinitions) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WIN32.vcxproj.filters b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WIN32.vcxproj.filters new file mode 100644 index 0000000..de00fc8 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WIN32.vcxproj.filters @@ -0,0 +1,177 @@ + + + + + {38712199-cebf-4124-bf15-398f7c3419ea} + ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe + + + {af3445a1-4908-4170-89ed-39345d90d30c} + + + {f32be356-4763-4cae-9020-974a2638cb08} + *.c + + + {88f409e6-d396-4ac5-94bd-7a99c914be46} + + + {e5ad4ec7-23dc-4295-8add-2acaee488f5a} + + + {d2dcd641-8d91-492b-852f-5563ffadaec6} + + + {8672fa26-b119-481f-8b8d-086419c01a3e} + + + {4570be11-ec96-4b55-ac58-24b50ada980a} + + + {5d93ed51-023a-41ad-9243-8d230165d34b} + + + {b71e974a-9f28-4815-972b-d930ba8a34d0} + + + + + FreeRTOS\Source\Portable + + + FreeRTOS\Source + + + FreeRTOS\Source + + + FreeRTOS\Source + + + FreeRTOS\Source + + + DemoTasks + + + FreeRTOS+\FreeRTOS+TCP + + + FreeRTOS+\FreeRTOS+TCP + + + FreeRTOS+\FreeRTOS+TCP + + + FreeRTOS+\FreeRTOS+TCP + + + FreeRTOS+\FreeRTOS+TCP\portable + + + FreeRTOS+\FreeRTOS+TCP\portable + + + FreeRTOS+\FreeRTOS+TCP + + + FreeRTOS+\FreeRTOS+TCP + + + FreeRTOS+\FreeRTOS+TCP + + + FreeRTOS+\FreeRTOS+TCP + + + FreeRTOS\Source + + + FreeRTOS\Source\Portable + + + + DemoTasks + + + FreeRTOS+\FreeRTOS+TCP + + + + DemoTasks + + + + + FreeRTOS+\FreeRTOS+TCP\include + + + FreeRTOS+\FreeRTOS+TCP\include + + + FreeRTOS+\FreeRTOS+TCP\include + + + FreeRTOS+\FreeRTOS+TCP\include + + + FreeRTOS\Source\include + + + FreeRTOS\Source\include + + + FreeRTOS\Source\include + + + FreeRTOS\Source\include + + + FreeRTOS\Source\include + + + FreeRTOS\Source\include + + + FreeRTOS\Source\include + + + FreeRTOS+\FreeRTOS+TCP\include + + + FreeRTOS+\FreeRTOS+TCP\include + + + FreeRTOS+\FreeRTOS+TCP\include + + + FreeRTOS+\FreeRTOS+TCP\include + + + FreeRTOS+\FreeRTOS+TCP\include + + + FreeRTOS+\FreeRTOS+TCP\include + + + FreeRTOS+\FreeRTOS+TCP\include + + + FreeRTOS+\FreeRTOS+TCP\include + + + FreeRTOS+\FreeRTOS+TCP\include + + + + + FreeRTOS+\FreeRTOS+TCP\include + + + FreeRTOS\Source\include + + + FreeRTOS\Source\include + + + \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/Packet32.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/Packet32.h new file mode 100644 index 0000000..1e0eacd --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/Packet32.h @@ -0,0 +1,359 @@ +/* + * Copyright (c) 1999 - 2005 NetGroup, Politecnico di Torino (Italy) + * Copyright (c) 2005 - 2007 CACE Technologies, Davis (California) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Politecnico di Torino, CACE Technologies + * nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/** @ingroup packetapi + * @{ + */ + +/** @defgroup packet32h Packet.dll definitions and data structures + * Packet32.h contains the data structures and the definitions used by packet.dll. + * The file is used both by the Win9x and the WinNTx versions of packet.dll, and can be included + * by the applications that use the functions of this library + * @{ + */ + +#ifndef __PACKET32 +#define __PACKET32 + +#include + +#ifdef HAVE_AIRPCAP_API +#include +#else +#if !defined(AIRPCAP_HANDLE__EAE405F5_0171_9592_B3C2_C19EC426AD34__DEFINED_) +#define AIRPCAP_HANDLE__EAE405F5_0171_9592_B3C2_C19EC426AD34__DEFINED_ +typedef struct _AirpcapHandle *PAirpcapHandle; +#endif /* AIRPCAP_HANDLE__EAE405F5_0171_9592_B3C2_C19EC426AD34__DEFINED_ */ +#endif /* HAVE_AIRPCAP_API */ + +#ifdef HAVE_DAG_API +#include +#endif /* HAVE_DAG_API */ + +// Working modes +#define PACKET_MODE_CAPT 0x0 ///< Capture mode +#define PACKET_MODE_STAT 0x1 ///< Statistical mode +#define PACKET_MODE_MON 0x2 ///< Monitoring mode +#define PACKET_MODE_DUMP 0x10 ///< Dump mode +#define PACKET_MODE_STAT_DUMP MODE_DUMP | MODE_STAT ///< Statistical dump Mode + + +/// Alignment macro. Defines the alignment size. +#define Packet_ALIGNMENT sizeof(int) +/// Alignment macro. Rounds up to the next even multiple of Packet_ALIGNMENT. +#define Packet_WORDALIGN(x) (((x)+(Packet_ALIGNMENT-1))&~(Packet_ALIGNMENT-1)) + +#define NdisMediumNull -1 ///< Custom linktype: NDIS doesn't provide an equivalent +#define NdisMediumCHDLC -2 ///< Custom linktype: NDIS doesn't provide an equivalent +#define NdisMediumPPPSerial -3 ///< Custom linktype: NDIS doesn't provide an equivalent +#define NdisMediumBare80211 -4 ///< Custom linktype: NDIS doesn't provide an equivalent +#define NdisMediumRadio80211 -5 ///< Custom linktype: NDIS doesn't provide an equivalent +#define NdisMediumPpi -6 ///< Custom linktype: NDIS doesn't provide an equivalent + +// Loopback behaviour definitions +#define NPF_DISABLE_LOOPBACK 1 ///< Drop the packets sent by the NPF driver +#define NPF_ENABLE_LOOPBACK 2 ///< Capture the packets sent by the NPF driver + +/*! + \brief Network type structure. + + This structure is used by the PacketGetNetType() function to return information on the current adapter's type and speed. +*/ +typedef struct NetType +{ + UINT LinkType; ///< The MAC of the current network adapter (see function PacketGetNetType() for more information) + ULONGLONG LinkSpeed; ///< The speed of the network in bits per second +}NetType; + + +//some definitions stolen from libpcap + +#ifndef BPF_MAJOR_VERSION + +/*! + \brief A BPF pseudo-assembly program. + + The program will be injected in the kernel by the PacketSetBPF() function and applied to every incoming packet. +*/ +struct bpf_program +{ + UINT bf_len; ///< Indicates the number of instructions of the program, i.e. the number of struct bpf_insn that will follow. + struct bpf_insn *bf_insns; ///< A pointer to the first instruction of the program. +}; + +/*! + \brief A single BPF pseudo-instruction. + + bpf_insn contains a single instruction for the BPF register-machine. It is used to send a filter program to the driver. +*/ +struct bpf_insn +{ + USHORT code; ///< Instruction type and addressing mode. + UCHAR jt; ///< Jump if true + UCHAR jf; ///< Jump if false + int k; ///< Generic field used for various purposes. +}; + +/*! + \brief Structure that contains a couple of statistics values on the current capture. + + It is used by packet.dll to return statistics about a capture session. +*/ +struct bpf_stat +{ + UINT bs_recv; ///< Number of packets that the driver received from the network adapter + ///< from the beginning of the current capture. This value includes the packets + ///< lost by the driver. + UINT bs_drop; ///< number of packets that the driver lost from the beginning of a capture. + ///< Basically, a packet is lost when the the buffer of the driver is full. + ///< In this situation the packet cannot be stored and the driver rejects it. + UINT ps_ifdrop; ///< drops by interface. XXX not yet supported + UINT bs_capt; ///< number of packets that pass the filter, find place in the kernel buffer and + ///< thus reach the application. +}; + +/*! + \brief Packet header. + + This structure defines the header associated with every packet delivered to the application. +*/ +struct bpf_hdr +{ + struct timeval bh_tstamp; ///< The timestamp associated with the captured packet. + ///< It is stored in a TimeVal structure. + UINT bh_caplen; ///< Length of captured portion. The captured portion can be different + ///< from the original packet, because it is possible (with a proper filter) + ///< to instruct the driver to capture only a portion of the packets. + UINT bh_datalen; ///< Original length of packet + USHORT bh_hdrlen; ///< Length of bpf header (this struct plus alignment padding). In some cases, + ///< a padding could be added between the end of this structure and the packet + ///< data for performance reasons. This filed can be used to retrieve the actual data + ///< of the packet. +}; + +/*! + \brief Dump packet header. + + This structure defines the header associated with the packets in a buffer to be used with PacketSendPackets(). + It is simpler than the bpf_hdr, because it corresponds to the header associated by WinPcap and libpcap to a + packet in a dump file. This makes straightforward sending WinPcap dump files to the network. +*/ +struct dump_bpf_hdr{ + struct timeval ts; ///< Time stamp of the packet + UINT caplen; ///< Length of captured portion. The captured portion can smaller than the + ///< the original packet, because it is possible (with a proper filter) to + ///< instruct the driver to capture only a portion of the packets. + UINT len; ///< Length of the original packet (off wire). +}; + + +#endif + +struct bpf_stat; + +#define DOSNAMEPREFIX TEXT("Packet_") ///< Prefix added to the adapters device names to create the WinPcap devices +#define MAX_LINK_NAME_LENGTH 64 //< Maximum length of the devices symbolic links +#define NMAX_PACKET 65535 + +/*! + \brief Addresses of a network adapter. + + This structure is used by the PacketGetNetInfoEx() function to return the IP addresses associated with + an adapter. +*/ +typedef struct npf_if_addr { + struct sockaddr_storage IPAddress; ///< IP address. + struct sockaddr_storage SubnetMask; ///< Netmask for that address. + struct sockaddr_storage Broadcast; ///< Broadcast address. +}npf_if_addr; + + +#define ADAPTER_NAME_LENGTH 256 + 12 ///< Maximum length for the name of an adapter. The value is the same used by the IP Helper API. +#define ADAPTER_DESC_LENGTH 128 ///< Maximum length for the description of an adapter. The value is the same used by the IP Helper API. +#define MAX_MAC_ADDR_LENGTH 8 ///< Maximum length for the link layer address of an adapter. The value is the same used by the IP Helper API. +#define MAX_NETWORK_ADDRESSES 16 ///< Maximum length for the link layer address of an adapter. The value is the same used by the IP Helper API. + + +typedef struct WAN_ADAPTER_INT WAN_ADAPTER; ///< Describes an opened wan (dialup, VPN...) network adapter using the NetMon API +typedef WAN_ADAPTER *PWAN_ADAPTER; ///< Describes an opened wan (dialup, VPN...) network adapter using the NetMon API + +#define INFO_FLAG_NDIS_ADAPTER 0 ///< Flag for ADAPTER_INFO: this is a traditional ndis adapter +#define INFO_FLAG_NDISWAN_ADAPTER 1 ///< Flag for ADAPTER_INFO: this is a NdisWan adapter, and it's managed by WANPACKET +#define INFO_FLAG_DAG_CARD 2 ///< Flag for ADAPTER_INFO: this is a DAG card +#define INFO_FLAG_DAG_FILE 6 ///< Flag for ADAPTER_INFO: this is a DAG file +#define INFO_FLAG_DONT_EXPORT 8 ///< Flag for ADAPTER_INFO: when this flag is set, the adapter will not be listed or openend by winpcap. This allows to prevent exporting broken network adapters, like for example FireWire ones. +#define INFO_FLAG_AIRPCAP_CARD 16 ///< Flag for ADAPTER_INFO: this is an airpcap card +#define INFO_FLAG_NPFIM_DEVICE 32 + +/*! + \brief Describes an opened network adapter. + + This structure is the most important for the functioning of packet.dll, but the great part of its fields + should be ignored by the user, since the library offers functions that avoid to cope with low-level parameters +*/ +typedef struct _ADAPTER { + HANDLE hFile; ///< \internal Handle to an open instance of the NPF driver. + CHAR SymbolicLink[MAX_LINK_NAME_LENGTH]; ///< \internal A string containing the name of the network adapter currently opened. + int NumWrites; ///< \internal Number of times a packets written on this adapter will be repeated + ///< on the wire. + HANDLE ReadEvent; ///< A notification event associated with the read calls on the adapter. + ///< It can be passed to standard Win32 functions (like WaitForSingleObject + ///< or WaitForMultipleObjects) to wait until the driver's buffer contains some + ///< data. It is particularly useful in GUI applications that need to wait + ///< concurrently on several events. In Windows NT/2000 the PacketSetMinToCopy() + ///< function can be used to define the minimum amount of data in the kernel buffer + ///< that will cause the event to be signalled. + + UINT ReadTimeOut; ///< \internal The amount of time after which a read on the driver will be released and + ///< ReadEvent will be signaled, also if no packets were captured + CHAR Name[ADAPTER_NAME_LENGTH]; + PWAN_ADAPTER pWanAdapter; + UINT Flags; ///< Adapter's flags. Tell if this adapter must be treated in a different way, using the Netmon API or the dagc API. + +#ifdef HAVE_AIRPCAP_API + PAirpcapHandle AirpcapAd; +#endif // HAVE_AIRPCAP_API + +#ifdef HAVE_NPFIM_API + void* NpfImHandle; +#endif // HAVE_NPFIM_API + +#ifdef HAVE_DAG_API + dagc_t *pDagCard; ///< Pointer to the dagc API adapter descriptor for this adapter + PCHAR DagBuffer; ///< Pointer to the buffer with the packets that is received from the DAG card + struct timeval DagReadTimeout; ///< Read timeout. The dagc API requires a timeval structure + unsigned DagFcsLen; ///< Length of the frame check sequence attached to any packet by the card. Obtained from the registry + DWORD DagFastProcess; ///< True if the user requests fast capture processing on this card. Higher level applications can use this value to provide a faster but possibly unprecise capture (for example, libpcap doesn't convert the timestamps). +#endif // HAVE_DAG_API +} ADAPTER, *LPADAPTER; + +/*! + \brief Structure that contains a group of packets coming from the driver. + + This structure defines the header associated with every packet delivered to the application. +*/ +typedef struct _PACKET { + HANDLE hEvent; ///< \deprecated Still present for compatibility with old applications. + OVERLAPPED OverLapped; ///< \deprecated Still present for compatibility with old applications. + PVOID Buffer; ///< Buffer with containing the packets. See the PacketReceivePacket() for + ///< details about the organization of the data in this buffer + UINT Length; ///< Length of the buffer + DWORD ulBytesReceived; ///< Number of valid bytes present in the buffer, i.e. amount of data + ///< received by the last call to PacketReceivePacket() + BOOLEAN bIoComplete; ///< \deprecated Still present for compatibility with old applications. +} PACKET, *LPPACKET; + +/*! + \brief Structure containing an OID request. + + It is used by the PacketRequest() function to send an OID to the interface card driver. + It can be used, for example, to retrieve the status of the error counters on the adapter, its MAC address, + the list of the multicast groups defined on it, and so on. +*/ +struct _PACKET_OID_DATA { + ULONG Oid; ///< OID code. See the Microsoft DDK documentation or the file ntddndis.h + ///< for a complete list of valid codes. + ULONG Length; ///< Length of the data field + UCHAR Data[1]; ///< variable-lenght field that contains the information passed to or received + ///< from the adapter. +}; +typedef struct _PACKET_OID_DATA PACKET_OID_DATA, *PPACKET_OID_DATA; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @} + */ + +/* +BOOLEAN QueryWinPcapRegistryStringA(CHAR *SubKeyName, + CHAR *Value, + UINT *pValueLen, + CHAR *DefaultVal); + +BOOLEAN QueryWinPcapRegistryStringW(WCHAR *SubKeyName, + WCHAR *Value, + UINT *pValueLen, + WCHAR *DefaultVal); +*/ + +//--------------------------------------------------------------------------- +// EXPORTED FUNCTIONS +//--------------------------------------------------------------------------- + +PCHAR PacketGetVersion(); +PCHAR PacketGetDriverVersion(); +BOOLEAN PacketSetMinToCopy(LPADAPTER AdapterObject,int nbytes); +BOOLEAN PacketSetNumWrites(LPADAPTER AdapterObject,int nwrites); +BOOLEAN PacketSetMode(LPADAPTER AdapterObject,int mode); +BOOLEAN PacketSetReadTimeout(LPADAPTER AdapterObject,int timeout); +BOOLEAN PacketSetBpf(LPADAPTER AdapterObject,struct bpf_program *fp); +BOOLEAN PacketSetLoopbackBehavior(LPADAPTER AdapterObject, UINT LoopbackBehavior); +INT PacketSetSnapLen(LPADAPTER AdapterObject,int snaplen); +BOOLEAN PacketGetStats(LPADAPTER AdapterObject,struct bpf_stat *s); +BOOLEAN PacketGetStatsEx(LPADAPTER AdapterObject,struct bpf_stat *s); +BOOLEAN PacketSetBuff(LPADAPTER AdapterObject,int dim); +BOOLEAN PacketGetNetType (LPADAPTER AdapterObject,NetType *type); +LPADAPTER PacketOpenAdapter(PCHAR AdapterName); +BOOLEAN PacketSendPacket(LPADAPTER AdapterObject,LPPACKET pPacket,BOOLEAN Sync); +INT PacketSendPackets(LPADAPTER AdapterObject,PVOID PacketBuff,ULONG Size, BOOLEAN Sync); +LPPACKET PacketAllocatePacket(void); +VOID PacketInitPacket(LPPACKET lpPacket,PVOID Buffer,UINT Length); +VOID PacketFreePacket(LPPACKET lpPacket); +BOOLEAN PacketReceivePacket(LPADAPTER AdapterObject,LPPACKET lpPacket,BOOLEAN Sync); +BOOLEAN PacketSetHwFilter(LPADAPTER AdapterObject,ULONG Filter); +BOOLEAN PacketGetAdapterNames(PTSTR pStr,PULONG BufferSize); +BOOLEAN PacketGetNetInfoEx(PCHAR AdapterName, npf_if_addr* buffer, PLONG NEntries); +BOOLEAN PacketRequest(LPADAPTER AdapterObject,BOOLEAN Set,PPACKET_OID_DATA OidData); +HANDLE PacketGetReadEvent(LPADAPTER AdapterObject); +BOOLEAN PacketSetDumpName(LPADAPTER AdapterObject, void *name, int len); +BOOLEAN PacketSetDumpLimits(LPADAPTER AdapterObject, UINT maxfilesize, UINT maxnpacks); +BOOLEAN PacketIsDumpEnded(LPADAPTER AdapterObject, BOOLEAN sync); +BOOL PacketStopDriver(); +VOID PacketCloseAdapter(LPADAPTER lpAdapter); +BOOLEAN PacketStartOem(PCHAR errorString, UINT errorStringLength); +BOOLEAN PacketStartOemEx(PCHAR errorString, UINT errorStringLength, ULONG flags); +PAirpcapHandle PacketGetAirPcapHandle(LPADAPTER AdapterObject); + +// +// Used by PacketStartOemEx +// +#define PACKET_START_OEM_NO_NETMON 0x00000001 + +#ifdef __cplusplus +} +#endif + +#endif //__PACKET32 diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/PacketData.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/PacketData.h new file mode 100644 index 0000000..8124db6 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/PacketData.h @@ -0,0 +1,267 @@ +char pkt1[] = { +0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, +0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, +0x00, 0x30, 0x09, 0x9c, 0x40, 0x00, 0x80, 0x06, +0x6f, 0x07, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, +0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, +0xc7, 0x35, 0x00, 0x00, 0x00, 0x00, 0x70, 0x02, +0x40, 0x00, 0xdf, 0xab, 0x00, 0x00, 0x02, 0x04, +0x05, 0xb4, 0x01, 0x01, 0x04, 0x02 }; + +char pkt2[] = { +0x00, 0x14, 0x22, 0xcb, 0x18, 0x2d, 0x00, 0x01, +0x02, 0x45, 0x09, 0x11, 0x08, 0x00, 0x45, 0x00, +0x00, 0x2c, 0x00, 0x01, 0x00, 0x00, 0x40, 0x06, +0xf8, 0xa6, 0xc0, 0xa8, 0x00, 0x0c, 0xc0, 0xa8, +0x00, 0xc8, 0x00, 0x50, 0x0f, 0xe2, 0x00, 0x00, +0x06, 0x68, 0x09, 0xe7, 0xc7, 0x36, 0x60, 0x12, +0x05, 0x92, 0x28, 0xca, 0x00, 0x00, 0x02, 0x04, +0x05, 0x92 }; + +char pkt3[] = { +0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, +0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, +0x00, 0x28, 0x09, 0x9e, 0x40, 0x00, 0x80, 0x06, +0x6f, 0x0d, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, +0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, +0xc7, 0x36, 0x00, 0x00, 0x06, 0x69, 0x50, 0x10, +0x42, 0xd8, 0x82, 0x3f, 0x00, 0x00 }; + +char pkt4[] = { +0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, +0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, +0x02, 0x27, 0x09, 0x9f, 0x40, 0x00, 0x80, 0x06, +0x6d, 0x0d, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, +0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, +0xc7, 0x36, 0x00, 0x00, 0x06, 0x69, 0x50, 0x18, +0x42, 0xd8, 0x84, 0x3e, 0x00, 0x00, 0x47, 0x45, +0x54, 0x20, 0x2f, 0x20, 0x48, 0x54, 0x54, 0x50, +0x2f, 0x31, 0x2e, 0x31, 0x0d, 0x0a, 0x41, 0x63, +0x63, 0x65, 0x70, 0x74, 0x3a, 0x20, 0x69, 0x6d, +0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0x2c, +0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x78, +0x2d, 0x78, 0x62, 0x69, 0x74, 0x6d, 0x61, 0x70, +0x2c, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, +0x6a, 0x70, 0x65, 0x67, 0x2c, 0x20, 0x69, 0x6d, +0x61, 0x67, 0x65, 0x2f, 0x70, 0x6a, 0x70, 0x65, +0x67, 0x2c, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, +0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x76, +0x6e, 0x64, 0x2e, 0x6d, 0x73, 0x2d, 0x65, 0x78, +0x63, 0x65, 0x6c, 0x2c, 0x20, 0x61, 0x70, 0x70, +0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, +0x2f, 0x6d, 0x73, 0x77, 0x6f, 0x72, 0x64, 0x2c, +0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, +0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x76, 0x6e, 0x64, +0x2e, 0x6d, 0x73, 0x2d, 0x70, 0x6f, 0x77, 0x65, +0x72, 0x70, 0x6f, 0x69, 0x6e, 0x74, 0x2c, 0x20, +0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, +0x69, 0x6f, 0x6e, 0x2f, 0x78, 0x2d, 0x6d, 0x73, +0x2d, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, +0x74, 0x69, 0x6f, 0x6e, 0x2c, 0x20, 0x61, 0x70, +0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, +0x6e, 0x2f, 0x78, 0x2d, 0x6d, 0x73, 0x2d, 0x78, +0x62, 0x61, 0x70, 0x2c, 0x20, 0x61, 0x70, 0x70, +0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, +0x2f, 0x76, 0x6e, 0x64, 0x2e, 0x6d, 0x73, 0x2d, +0x78, 0x70, 0x73, 0x64, 0x6f, 0x63, 0x75, 0x6d, +0x65, 0x6e, 0x74, 0x2c, 0x20, 0x61, 0x70, 0x70, +0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, +0x2f, 0x78, 0x61, 0x6d, 0x6c, 0x2b, 0x78, 0x6d, +0x6c, 0x2c, 0x20, 0x2a, 0x2f, 0x2a, 0x0d, 0x0a, +0x41, 0x63, 0x63, 0x65, 0x70, 0x74, 0x2d, 0x4c, +0x61, 0x6e, 0x67, 0x75, 0x61, 0x67, 0x65, 0x3a, +0x20, 0x65, 0x6e, 0x2d, 0x67, 0x62, 0x0d, 0x0a, +0x41, 0x63, 0x63, 0x65, 0x70, 0x74, 0x2d, 0x45, +0x6e, 0x63, 0x6f, 0x64, 0x69, 0x6e, 0x67, 0x3a, +0x20, 0x67, 0x7a, 0x69, 0x70, 0x2c, 0x20, 0x64, +0x65, 0x66, 0x6c, 0x61, 0x74, 0x65, 0x0d, 0x0a, +0x55, 0x73, 0x65, 0x72, 0x2d, 0x41, 0x67, 0x65, +0x6e, 0x74, 0x3a, 0x20, 0x4d, 0x6f, 0x7a, 0x69, +0x6c, 0x6c, 0x61, 0x2f, 0x34, 0x2e, 0x30, 0x20, +0x28, 0x63, 0x6f, 0x6d, 0x70, 0x61, 0x74, 0x69, +0x62, 0x6c, 0x65, 0x3b, 0x20, 0x4d, 0x53, 0x49, +0x45, 0x20, 0x36, 0x2e, 0x30, 0x3b, 0x20, 0x57, +0x69, 0x6e, 0x64, 0x6f, 0x77, 0x73, 0x20, 0x4e, +0x54, 0x20, 0x35, 0x2e, 0x31, 0x3b, 0x20, 0x53, +0x56, 0x31, 0x3b, 0x20, 0x47, 0x6f, 0x6f, 0x67, +0x6c, 0x65, 0x54, 0x35, 0x3b, 0x20, 0x2e, 0x4e, +0x45, 0x54, 0x20, 0x43, 0x4c, 0x52, 0x20, 0x32, +0x2e, 0x30, 0x2e, 0x35, 0x30, 0x37, 0x32, 0x37, +0x3b, 0x20, 0x2e, 0x4e, 0x45, 0x54, 0x20, 0x43, +0x4c, 0x52, 0x20, 0x33, 0x2e, 0x30, 0x2e, 0x30, +0x34, 0x35, 0x30, 0x36, 0x2e, 0x36, 0x34, 0x38, +0x3b, 0x20, 0x2e, 0x4e, 0x45, 0x54, 0x20, 0x43, +0x4c, 0x52, 0x20, 0x33, 0x2e, 0x35, 0x2e, 0x32, +0x31, 0x30, 0x32, 0x32, 0x29, 0x0d, 0x0a, 0x48, +0x6f, 0x73, 0x74, 0x3a, 0x20, 0x31, 0x39, 0x32, +0x2e, 0x31, 0x36, 0x38, 0x2e, 0x30, 0x2e, 0x31, +0x32, 0x0d, 0x0a, 0x43, 0x6f, 0x6e, 0x6e, 0x65, +0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x4b, +0x65, 0x65, 0x70, 0x2d, 0x41, 0x6c, 0x69, 0x76, +0x65, 0x0d, 0x0a, 0x0d, 0x0a }; + +char pkt5[] = { +0x00, 0x14, 0x22, 0xcb, 0x18, 0x2d, 0x00, 0x01, +0x02, 0x45, 0x09, 0x11, 0x08, 0x00, 0x45, 0x00, +0x00, 0x2c, 0x00, 0x02, 0x00, 0x00, 0x40, 0x06, +0xf8, 0xa5, 0xc0, 0xa8, 0x00, 0x0c, 0xc0, 0xa8, +0x00, 0xc8, 0x00, 0x50, 0x0f, 0xe2, 0x00, 0x00, +0x06, 0x68, 0x09, 0xe7, 0xc7, 0x36, 0x60, 0x12, +0x05, 0x92, 0x28, 0xca, 0x00, 0x00, 0x02, 0x04, +0x05, 0x92 }; + +char pkt6[] = { +0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, +0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, +0x00, 0x28, 0x09, 0xa1, 0x40, 0x00, 0x80, 0x06, +0x6f, 0x0a, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, +0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, +0xc9, 0x35, 0x00, 0x00, 0x06, 0x69, 0x50, 0x10, +0x42, 0xd8, 0x82, 0x3f, 0x00, 0x00 }; + +char pkt7[] = { +0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, +0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, +0x02, 0x27, 0x09, 0xa2, 0x40, 0x00, 0x80, 0x06, +0x6d, 0x0a, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, +0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, +0xc7, 0x36, 0x00, 0x00, 0x06, 0x69, 0x50, 0x18, +0x42, 0xd8, 0x84, 0x3e, 0x00, 0x00, 0x47, 0x45, +0x54, 0x20, 0x2f, 0x20, 0x48, 0x54, 0x54, 0x50, +0x2f, 0x31, 0x2e, 0x31, 0x0d, 0x0a, 0x41, 0x63, +0x63, 0x65, 0x70, 0x74, 0x3a, 0x20, 0x69, 0x6d, +0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0x2c, +0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x78, +0x2d, 0x78, 0x62, 0x69, 0x74, 0x6d, 0x61, 0x70, +0x2c, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, +0x6a, 0x70, 0x65, 0x67, 0x2c, 0x20, 0x69, 0x6d, +0x61, 0x67, 0x65, 0x2f, 0x70, 0x6a, 0x70, 0x65, +0x67, 0x2c, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, +0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x76, +0x6e, 0x64, 0x2e, 0x6d, 0x73, 0x2d, 0x65, 0x78, +0x63, 0x65, 0x6c, 0x2c, 0x20, 0x61, 0x70, 0x70, +0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, +0x2f, 0x6d, 0x73, 0x77, 0x6f, 0x72, 0x64, 0x2c, +0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, +0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x76, 0x6e, 0x64, +0x2e, 0x6d, 0x73, 0x2d, 0x70, 0x6f, 0x77, 0x65, +0x72, 0x70, 0x6f, 0x69, 0x6e, 0x74, 0x2c, 0x20, +0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, +0x69, 0x6f, 0x6e, 0x2f, 0x78, 0x2d, 0x6d, 0x73, +0x2d, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, +0x74, 0x69, 0x6f, 0x6e, 0x2c, 0x20, 0x61, 0x70, +0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, +0x6e, 0x2f, 0x78, 0x2d, 0x6d, 0x73, 0x2d, 0x78, +0x62, 0x61, 0x70, 0x2c, 0x20, 0x61, 0x70, 0x70, +0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, +0x2f, 0x76, 0x6e, 0x64, 0x2e, 0x6d, 0x73, 0x2d, +0x78, 0x70, 0x73, 0x64, 0x6f, 0x63, 0x75, 0x6d, +0x65, 0x6e, 0x74, 0x2c, 0x20, 0x61, 0x70, 0x70, +0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, +0x2f, 0x78, 0x61, 0x6d, 0x6c, 0x2b, 0x78, 0x6d, +0x6c, 0x2c, 0x20, 0x2a, 0x2f, 0x2a, 0x0d, 0x0a, +0x41, 0x63, 0x63, 0x65, 0x70, 0x74, 0x2d, 0x4c, +0x61, 0x6e, 0x67, 0x75, 0x61, 0x67, 0x65, 0x3a, +0x20, 0x65, 0x6e, 0x2d, 0x67, 0x62, 0x0d, 0x0a, +0x41, 0x63, 0x63, 0x65, 0x70, 0x74, 0x2d, 0x45, +0x6e, 0x63, 0x6f, 0x64, 0x69, 0x6e, 0x67, 0x3a, +0x20, 0x67, 0x7a, 0x69, 0x70, 0x2c, 0x20, 0x64, +0x65, 0x66, 0x6c, 0x61, 0x74, 0x65, 0x0d, 0x0a, +0x55, 0x73, 0x65, 0x72, 0x2d, 0x41, 0x67, 0x65, +0x6e, 0x74, 0x3a, 0x20, 0x4d, 0x6f, 0x7a, 0x69, +0x6c, 0x6c, 0x61, 0x2f, 0x34, 0x2e, 0x30, 0x20, +0x28, 0x63, 0x6f, 0x6d, 0x70, 0x61, 0x74, 0x69, +0x62, 0x6c, 0x65, 0x3b, 0x20, 0x4d, 0x53, 0x49, +0x45, 0x20, 0x36, 0x2e, 0x30, 0x3b, 0x20, 0x57, +0x69, 0x6e, 0x64, 0x6f, 0x77, 0x73, 0x20, 0x4e, +0x54, 0x20, 0x35, 0x2e, 0x31, 0x3b, 0x20, 0x53, +0x56, 0x31, 0x3b, 0x20, 0x47, 0x6f, 0x6f, 0x67, +0x6c, 0x65, 0x54, 0x35, 0x3b, 0x20, 0x2e, 0x4e, +0x45, 0x54, 0x20, 0x43, 0x4c, 0x52, 0x20, 0x32, +0x2e, 0x30, 0x2e, 0x35, 0x30, 0x37, 0x32, 0x37, +0x3b, 0x20, 0x2e, 0x4e, 0x45, 0x54, 0x20, 0x43, +0x4c, 0x52, 0x20, 0x33, 0x2e, 0x30, 0x2e, 0x30, +0x34, 0x35, 0x30, 0x36, 0x2e, 0x36, 0x34, 0x38, +0x3b, 0x20, 0x2e, 0x4e, 0x45, 0x54, 0x20, 0x43, +0x4c, 0x52, 0x20, 0x33, 0x2e, 0x35, 0x2e, 0x32, +0x31, 0x30, 0x32, 0x32, 0x29, 0x0d, 0x0a, 0x48, +0x6f, 0x73, 0x74, 0x3a, 0x20, 0x31, 0x39, 0x32, +0x2e, 0x31, 0x36, 0x38, 0x2e, 0x30, 0x2e, 0x31, +0x32, 0x0d, 0x0a, 0x43, 0x6f, 0x6e, 0x6e, 0x65, +0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x4b, +0x65, 0x65, 0x70, 0x2d, 0x41, 0x6c, 0x69, 0x76, +0x65, 0x0d, 0x0a, 0x0d, 0x0a }; + +char pkt8[] = { +0x00, 0x14, 0x22, 0xcb, 0x18, 0x2d, 0x00, 0x01, +0x02, 0x45, 0x09, 0x11, 0x08, 0x00, 0x45, 0x00, +0x00, 0x2c, 0x00, 0x03, 0x00, 0x00, 0x40, 0x06, +0xf8, 0xa4, 0xc0, 0xa8, 0x00, 0x0c, 0xc0, 0xa8, +0x00, 0xc8, 0x00, 0x50, 0x0f, 0xe2, 0x00, 0x00, +0x06, 0x68, 0x09, 0xe7, 0xc7, 0x36, 0x60, 0x12, +0x05, 0x92, 0x28, 0xca, 0x00, 0x00, 0x02, 0x04, +0x05, 0x92 }; + +char pkt9[] = { +0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, +0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, +0x00, 0x28, 0x09, 0xa3, 0x40, 0x00, 0x80, 0x06, +0x6f, 0x08, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, +0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, +0xc9, 0x35, 0x00, 0x00, 0x06, 0x69, 0x50, 0x10, +0x42, 0xd8, 0x82, 0x3f, 0x00, 0x00 }; + +char pkt10[] = { +0x00, 0x14, 0x22, 0xcb, 0x18, 0x2d, 0x00, 0x01, +0x02, 0x45, 0x09, 0x11, 0x08, 0x00, 0x45, 0x00, +0x00, 0x2c, 0x00, 0x04, 0x00, 0x00, 0x40, 0x06, +0xf8, 0xa3, 0xc0, 0xa8, 0x00, 0x0c, 0xc0, 0xa8, +0x00, 0xc8, 0x00, 0x50, 0x0f, 0xe2, 0x00, 0x00, +0x06, 0x68, 0x09, 0xe7, 0xc7, 0x36, 0x60, 0x12, +0x05, 0x92, 0x28, 0xca, 0x00, 0x00, 0x02, 0x04, +0x05, 0x92 }; + +char pkt11[] = { +0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, +0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, +0x00, 0x28, 0x09, 0xa6, 0x40, 0x00, 0x80, 0x06, +0x6f, 0x05, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, +0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, +0xc9, 0x35, 0x00, 0x00, 0x06, 0x69, 0x50, 0x10, +0x42, 0xd8, 0x82, 0x3f, 0x00, 0x00 }; + +char pkt12[] = { +0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14, +0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00, +0x00, 0x28, 0x09, 0xa7, 0x40, 0x00, 0x80, 0x06, +0x6f, 0x04, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8, +0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7, +0xc9, 0x35, 0x00, 0x00, 0x06, 0x69, 0x50, 0x14, +0x00, 0x00, 0x43, 0xf4, 0x00, 0x00 }; + + +typedef struct +{ + char *pcData; + int iDataLen; +} xPacketData; + +xPacketData xAllPackets[] = +{ + { pkt1, sizeof( pkt1 ) }, +// { pkt2, sizeof( pkt2 ) }, + { pkt3, sizeof( pkt3 ) }, + { pkt4, sizeof( pkt4 ) }, +// { pkt5, sizeof( pkt5 ) }, + { pkt6, sizeof( pkt6 ) }, + { pkt7, sizeof( pkt7 ) }, + { pkt8, sizeof( pkt8 ) }, + { pkt9, sizeof( pkt9 ) }, + { pkt10, sizeof( pkt10 ) }, +// { pkt11, sizeof( pkt11 ) }, +// { pkt12, sizeof( pkt12 ) }, +// { pkt13, sizeof( pkt13 ) }, +// { pkt14, sizeof( pkt14 ) }, +// { pkt15, sizeof( pkt15 ) }, +// { pkt16, sizeof( pkt16 ) }, +}; diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/Win32-Extensions.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/Win32-Extensions.h new file mode 100644 index 0000000..be71c85 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/Win32-Extensions.h @@ -0,0 +1,114 @@ +/* + * Copyright (c) 1999 - 2005 NetGroup, Politecnico di Torino (Italy) + * Copyright (c) 2005 - 2006 CACE Technologies, Davis (California) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Politecnico di Torino, CACE Technologies + * nor the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __WIN32_EXTENSIONS_H__ +#define __WIN32_EXTENSIONS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Definitions */ + +/*! + \brief A queue of raw packets that will be sent to the network with pcap_sendqueue_transmit(). +*/ +struct pcap_send_queue +{ + u_int maxlen; ///< Maximum size of the the queue, in bytes. This variable contains the size of the buffer field. + u_int len; ///< Current size of the queue, in bytes. + char *buffer; ///< Buffer containing the packets to be sent. +}; + +typedef struct pcap_send_queue pcap_send_queue; + +/*! + \brief This typedef is a support for the pcap_get_airpcap_handle() function +*/ +#if !defined(AIRPCAP_HANDLE__EAE405F5_0171_9592_B3C2_C19EC426AD34__DEFINED_) +#define AIRPCAP_HANDLE__EAE405F5_0171_9592_B3C2_C19EC426AD34__DEFINED_ +typedef struct _AirpcapHandle *PAirpcapHandle; +#endif + +#define BPF_MEM_EX_IMM 0xc0 +#define BPF_MEM_EX_IND 0xe0 + +/*used for ST*/ +#define BPF_MEM_EX 0xc0 +#define BPF_TME 0x08 + +#define BPF_LOOKUP 0x90 +#define BPF_EXECUTE 0xa0 +#define BPF_INIT 0xb0 +#define BPF_VALIDATE 0xc0 +#define BPF_SET_ACTIVE 0xd0 +#define BPF_RESET 0xe0 +#define BPF_SET_MEMORY 0x80 +#define BPF_GET_REGISTER_VALUE 0x70 +#define BPF_SET_REGISTER_VALUE 0x60 +#define BPF_SET_WORKING 0x50 +#define BPF_SET_ACTIVE_READ 0x40 +#define BPF_SET_AUTODELETION 0x30 +#define BPF_SEPARATION 0xff + +/* Prototypes */ +pcap_send_queue* pcap_sendqueue_alloc(u_int memsize); + +void pcap_sendqueue_destroy(pcap_send_queue* queue); + +int pcap_sendqueue_queue(pcap_send_queue* queue, const struct pcap_pkthdr *pkt_header, const u_char *pkt_data); + +u_int pcap_sendqueue_transmit(pcap_t *p, pcap_send_queue* queue, int sync); + +HANDLE pcap_getevent(pcap_t *p); + +struct pcap_stat *pcap_stats_ex(pcap_t *p, int *pcap_stat_size); + +int pcap_setuserbuffer(pcap_t *p, int size); + +int pcap_live_dump(pcap_t *p, char *filename, int maxsize, int maxpacks); + +int pcap_live_dump_ended(pcap_t *p, int sync); + +int pcap_offline_filter(struct bpf_program *prog, const struct pcap_pkthdr *header, const u_char *pkt_data); + +int pcap_start_oem(char* err_str, int flags); + +PAirpcapHandle pcap_get_airpcap_handle(pcap_t *p); + +#ifdef __cplusplus +} +#endif + +#endif //__WIN32_EXTENSIONS_H__ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/arch.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/arch.c new file mode 100644 index 0000000..d704da8 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/arch.c @@ -0,0 +1,336 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* WinPCap includes. */ +#include "pcap.h" +#include "remote-ext.h" + +/* uIP includes. */ +#include "net/uip.h" +#include "net/uip_arp.h" +#include "net/clock-arch.h" + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* + * Query the computer the simulation is being executed on to find the network + * interfaces it has installed. + */ +static pcap_if_t * prvPrintAvailableNetworkInterfaces( void ); + +/* + * Open the network interface. The number of the interface to be opened is set + * by the configNETWORK_INTERFACE_TO_USE constant in FreeRTOSConfig.h. + */ +static void prvOpenSelectedNetworkInterface( pcap_if_t *pxAllNetworkInterfaces ); + +/* + * Configure the capture filter to allow blocking reads, and to filter out + * packets that are not of interest to this demo. + */ +static void prvConfigureCaptureBehaviour( void ); + +pcap_t *pxOpenedInterfaceHandle = NULL; +LARGE_INTEGER freq, sys_start_time; + +#define archNUM_BUFFERS 5 +#define archNUM_BUFFER_POINTERS ( archNUM_BUFFERS - 1 ) + +static void prvInterruptSimulator( void *pvParameters ); + +static unsigned char ucEthernetBuffer[ archNUM_BUFFERS ][ UIP_CONF_BUFFER_SIZE ]; +static unsigned char *pucEthernetBufferPointers[ archNUM_BUFFER_POINTERS ]; + +static long lLengthOfDataInBuffer[ archNUM_BUFFER_POINTERS ] = { 0 }; +static unsigned char ucNextBufferToFill = 0U, ucNextBufferToProcess = 0U; + +unsigned char *uip_buf = NULL; +char cErrorBuffer[PCAP_ERRBUF_SIZE]; + +void vNetifTx( void ) +{ + pcap_sendpacket( pxOpenedInterfaceHandle, uip_buf, uip_len ); + pcap_sendpacket( pxOpenedInterfaceHandle, uip_buf, uip_len ); +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxNetifRx( void ) +{ +UBaseType_t xDataLen; +unsigned char *pucTemp; + + /* Check there is really data available. */ + xDataLen = lLengthOfDataInBuffer[ ucNextBufferToProcess ]; + if( xDataLen != 0L ) + { + + /* The buffer pointed to by uip_buf is going to change. Remember which + buffer uip_buf is currently pointing to. */ + pucTemp = uip_buf; + + /* Point uip_buf at the next buffer that contains data. */ + uip_buf = pucEthernetBufferPointers[ ucNextBufferToProcess ]; + + /* The buffer pointed to by + pucEthernetBufferPointeres[ ucNextBufferToProcess ] is now in use by + uip_buf, but the buffer uip_buf was pointing to on entry to this + function is free. Set + pucEthernetBufferPointeres[ ucNextBufferToProcess ] to the free + buffer. */ + pucEthernetBufferPointers[ ucNextBufferToProcess ] = pucTemp; + lLengthOfDataInBuffer[ ucNextBufferToProcess ] = 0L; + + ucNextBufferToProcess++; + if( ucNextBufferToProcess >= archNUM_BUFFER_POINTERS ) + { + ucNextBufferToProcess = 0L; + } + } + + return xDataLen; +} +/*-----------------------------------------------------------*/ + +BaseType_t xNetifInit( void ) +{ +BaseType_t x; +pcap_if_t *pxAllNetworkInterfaces; + + /* Allocate a free buffer to each buffer pointer. */ + for( x = 0; x < sizeof( pucEthernetBufferPointers ) / sizeof( unsigned char * ); x++ ) + { + pucEthernetBufferPointers[ x ] = &( ucEthernetBuffer[ x ][ 0 ] ); + } + + /* Start with uip_buf pointing to a buffer that is not referenced from the + pucEthernetBufferPointers[] array. */ + uip_buf = &( ucEthernetBuffer[ archNUM_BUFFERS - 1 ][ 0 ] ); + + /* Query the computer the simulation is being executed on to find the + network interfaces it has installed. */ + pxAllNetworkInterfaces = prvPrintAvailableNetworkInterfaces(); + + /* Open the network interface. The number of the interface to be opened is + set by the configNETWORK_INTERFACE_TO_USE constant in FreeRTOSConfig.h. + Calling this function will set the pxOpenedInterfaceHandle variable. If, + after calling this function, pxOpenedInterfaceHandle is equal to NULL, then + the interface could not be opened. */ + if( pxAllNetworkInterfaces != NULL ) + { + prvOpenSelectedNetworkInterface( pxAllNetworkInterfaces ); + } + + + return x; +} +/*-----------------------------------------------------------*/ + +static pcap_if_t * prvPrintAvailableNetworkInterfaces( void ) +{ +pcap_if_t * pxAllNetworkInterfaces = NULL, *xInterface; +long lInterfaceNumber = 1; + + if( pcap_findalldevs_ex( PCAP_SRC_IF_STRING, NULL, &pxAllNetworkInterfaces, cErrorBuffer ) == -1 ) + { + printf( "\r\nCould not obtain a list of network interfaces\r\n%s\r\n", cErrorBuffer ); + pxAllNetworkInterfaces = NULL; + } + + if( pxAllNetworkInterfaces != NULL ) + { + /* Print out the list of network interfaces. The first in the list + is interface '1', not interface '0'. */ + for( xInterface = pxAllNetworkInterfaces; xInterface != NULL; xInterface = xInterface->next ) + { + printf( "%d. %s", lInterfaceNumber, xInterface->name ); + + if( xInterface->description != NULL ) + { + printf( " (%s)\r\n", xInterface->description ); + } + else + { + printf( " (No description available)\r\n") ; + } + + lInterfaceNumber++; + } + } + + if( lInterfaceNumber == 1 ) + { + /* The interface number was never incremented, so the above for() loop + did not execute meaning no interfaces were found. */ + printf( " \r\nNo network interfaces were found.\r\n" ); + pxAllNetworkInterfaces = NULL; + } + + printf( "\r\nThe interface that will be opened is set by configNETWORK_INTERFACE_TO_USE which should be defined in FreeRTOSConfig.h\r\n" ); + printf( "Attempting to open interface number %d.\r\n", configNETWORK_INTERFACE_TO_USE ); + + if( ( configNETWORK_INTERFACE_TO_USE < 1L ) || ( configNETWORK_INTERFACE_TO_USE > lInterfaceNumber ) ) + { + printf("\r\nconfigNETWORK_INTERFACE_TO_USE is not in the valid range.\r\n" ); + + if( pxAllNetworkInterfaces != NULL ) + { + /* Free the device list, as no devices are going to be opened. */ + pcap_freealldevs( pxAllNetworkInterfaces ); + pxAllNetworkInterfaces = NULL; + } + } + + return pxAllNetworkInterfaces; +} +/*-----------------------------------------------------------*/ + +static void prvOpenSelectedNetworkInterface( pcap_if_t *pxAllNetworkInterfaces ) +{ +pcap_if_t *xInterface; +long x; + + /* Walk the list of devices until the selected device is located. */ + xInterface = pxAllNetworkInterfaces; + for( x = 0L; x < ( configNETWORK_INTERFACE_TO_USE - 1L ); x++ ) + { + xInterface = xInterface->next; + } + + /* Open the selected interface. */ + pxOpenedInterfaceHandle = pcap_open( xInterface->name, /* The name of the selected interface. */ + UIP_CONF_BUFFER_SIZE, /* The size of the packet to capture. */ + PCAP_OPENFLAG_PROMISCUOUS, /* Open in promiscious mode as the MAC and + IP address is going to be "simulated", and + not be the real MAC and IP address. This allows + trafic to the simulated IP address to be routed + to uIP, and trafic to the real IP address to be + routed to the Windows TCP/IP stack. */ + 0xfffffffL, /* The read time out. This is going to block + until data is available. */ + NULL, /* No authentication is required as this is + not a remote capture session. */ + cErrorBuffer + ); + + if ( pxOpenedInterfaceHandle == NULL ) + { + printf( "\r\n%s is not supported by WinPcap and cannot be opened\r\n", xInterface->name ); + } + else + { + /* Configure the capture filter to allow blocking reads, and to filter + out packets that are not of interest to this demo. */ + prvConfigureCaptureBehaviour(); + } + + /* The device list is no longer required. */ + pcap_freealldevs( pxAllNetworkInterfaces ); +} +/*-----------------------------------------------------------*/ + +static void prvConfigureCaptureBehaviour( void ) +{ +struct bpf_program xFilterCode; +const long lMinBytesToCopy = 10L, lBlocking = 0L; +unsigned long ulNetMask; + + /* Unblock a read as soon as anything is received. */ + pcap_setmintocopy( pxOpenedInterfaceHandle, lMinBytesToCopy ); + + /* Allow blocking. */ + pcap_setnonblock( pxOpenedInterfaceHandle, lBlocking, cErrorBuffer ); + + /* Set up a filter so only the packets of interest are passed to the uIP + stack. cErrorBuffer is used for convenience to create the string. Don't + confuse this with an error message. */ + sprintf( cErrorBuffer, "broadcast or multicast or host %d.%d.%d.%d", configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 ); + + ulNetMask = ( configNET_MASK3 << 24UL ) | ( configNET_MASK2 << 16UL ) | ( configNET_MASK1 << 8L ) | configNET_MASK0; + + if( pcap_compile(pxOpenedInterfaceHandle, &xFilterCode, cErrorBuffer, 1, ulNetMask ) < 0 ) + { + printf("\r\nThe packet filter string is invalid\r\n" ); + } + else + { + if( pcap_setfilter( pxOpenedInterfaceHandle, &xFilterCode ) < 0 ) + { + printf( "\r\nAn error occurred setting the packet filter.\r\n" ); + } + } + + /* Create a task that simulates an interrupt in a real system. This will + block waiting for packets, then send a message to the uIP task when data + is available. */ + xTaskCreate( prvInterruptSimulator, ( signed char * ) "MAC_ISR", configMINIMAL_STACK_SIZE, NULL, ( configuIP_TASK_PRIORITY - 1 ), NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvInterruptSimulator( void *pvParameters ) +{ +static struct pcap_pkthdr *pxHeader; +const unsigned char *pucPacketData; +extern QueueHandle_t xEMACEventQueue; +const unsigned long ulRxEvent = uipETHERNET_RX_EVENT; +long lResult; + + /* Just to kill the compiler warning. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Get the next packet. */ + lResult = pcap_next_ex( pxOpenedInterfaceHandle, &pxHeader, &pucPacketData ); + if( lResult ) + { + /* Is the next buffer into which data should be placed free? */ + if( lLengthOfDataInBuffer[ ucNextBufferToFill ] == 0L ) + { + /* Copy the data from the captured packet into the buffer. */ + memcpy( pucEthernetBufferPointers[ ucNextBufferToFill ], pucPacketData, pxHeader->len ); + + /* Note the amount of data that was copied. */ + lLengthOfDataInBuffer[ ucNextBufferToFill ] = pxHeader->len; + + /* Move onto the next buffer, wrapping around if necessary. */ + ucNextBufferToFill++; + if( ucNextBufferToFill >= archNUM_BUFFER_POINTERS ) + { + ucNextBufferToFill = 0U; + } + + /* Data was received and stored. Send a message to the uIP task + to let it know. */ + xQueueSendToBack( xEMACEventQueue, &ulRxEvent, portMAX_DELAY ); + } + } + } +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/bittypes.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/bittypes.h new file mode 100644 index 0000000..f55fcec --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/bittypes.h @@ -0,0 +1,137 @@ +/* + * Copyright (C) 1999 WIDE Project. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the project nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#ifndef _BITTYPES_H +#define _BITTYPES_H + +#ifndef HAVE_U_INT8_T + +#if SIZEOF_CHAR == 1 +typedef unsigned char u_int8_t; +typedef signed char _int8_t; +#elif SIZEOF_INT == 1 +typedef unsigned int u_int8_t; +typedef signed int int8_t; +#else /* XXX */ +#error "there's no appropriate type for u_int8_t" +#endif +#define HAVE_U_INT8_T 1 +#define HAVE_INT8_T 1 + +#endif /* HAVE_U_INT8_T */ + +#ifndef HAVE_U_INT16_T + +#if SIZEOF_SHORT == 2 +typedef unsigned short u_int16_t; +typedef signed short _int16_t; +#elif SIZEOF_INT == 2 +typedef unsigned int u_int16_t; +typedef signed int int16_t; +#elif SIZEOF_CHAR == 2 +typedef unsigned char u_int16_t; +typedef signed char int16_t; +#else /* XXX */ +#error "there's no appropriate type for u_int16_t" +#endif +#define HAVE_U_INT16_T 1 +#define HAVE_INT16_T 1 + +#endif /* HAVE_U_INT16_T */ + +#ifndef HAVE_U_INT32_T + +#if SIZEOF_INT == 4 +typedef unsigned int u_int32_t; +typedef signed int _int32_t; +#elif SIZEOF_LONG == 4 +typedef unsigned long u_int32_t; +typedef signed long int32_t; +#elif SIZEOF_SHORT == 4 +typedef unsigned short u_int32_t; +typedef signed short int32_t; +#else /* XXX */ +#error "there's no appropriate type for u_int32_t" +#endif +#define HAVE_U_INT32_T 1 +#define HAVE_INT32_T 1 + +#endif /* HAVE_U_INT32_T */ + +#ifndef HAVE_U_INT64_T +#if SIZEOF_LONG_LONG == 8 +typedef unsigned long long u_int64_t; +typedef long long int64_t; +#elif defined(_MSC_EXTENSIONS) +typedef unsigned _int64 u_int64_t; +typedef _int64 int64_t; +#elif SIZEOF_INT == 8 +typedef unsigned int u_int64_t; +#elif SIZEOF_LONG == 8 +typedef unsigned long u_int64_t; +#elif SIZEOF_SHORT == 8 +typedef unsigned short u_int64_t; +#else /* XXX */ +#error "there's no appropriate type for u_int64_t" +#endif + +#endif /* HAVE_U_INT64_T */ + +#ifndef PRId64 +#ifdef _MSC_EXTENSIONS +#define PRId64 "I64d" +#else /* _MSC_EXTENSIONS */ +#define PRId64 "lld" +#endif /* _MSC_EXTENSIONS */ +#endif /* PRId64 */ + +#ifndef PRIo64 +#ifdef _MSC_EXTENSIONS +#define PRIo64 "I64o" +#else /* _MSC_EXTENSIONS */ +#define PRIo64 "llo" +#endif /* _MSC_EXTENSIONS */ +#endif /* PRIo64 */ + +#ifndef PRIx64 +#ifdef _MSC_EXTENSIONS +#define PRIx64 "I64x" +#else /* _MSC_EXTENSIONS */ +#define PRIx64 "llx" +#endif /* _MSC_EXTENSIONS */ +#endif /* PRIx64 */ + +#ifndef PRIu64 +#ifdef _MSC_EXTENSIONS +#define PRIu64 "I64u" +#else /* _MSC_EXTENSIONS */ +#define PRIu64 "llu" +#endif /* _MSC_EXTENSIONS */ +#endif /* PRIu64 */ + +#endif /* _BITTYPES_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/ip6_misc.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/ip6_misc.h new file mode 100644 index 0000000..562fa61 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/ip6_misc.h @@ -0,0 +1,163 @@ +/* + * Copyright (c) 1993, 1994, 1997 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that: (1) source code distributions + * retain the above copyright notice and this paragraph in its entirety, (2) + * distributions including binary code include the above copyright notice and + * this paragraph in its entirety in the documentation or other materials + * provided with the distribution, and (3) all advertising materials mentioning + * features or use of this software display the following acknowledgement: + * ``This product includes software developed by the University of California, + * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of + * the University nor the names of its contributors may be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * @(#) $Header: /tcpdump/master/libpcap/Win32/Include/ip6_misc.h,v 1.5 2006-01-22 18:02:18 gianluca Exp $ (LBL) + */ + +/* + * This file contains a collage of declarations for IPv6 from FreeBSD not present in Windows + */ + +#include + +#include + +#ifndef __MINGW32__ +#define IN_MULTICAST(a) IN_CLASSD(a) +#endif + +#define IN_EXPERIMENTAL(a) ((((u_int32_t) (a)) & 0xf0000000) == 0xf0000000) + +#define IN_LOOPBACKNET 127 + +#if defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF) +/* IPv6 address */ +struct in6_addr + { + union + { + u_int8_t u6_addr8[16]; + u_int16_t u6_addr16[8]; + u_int32_t u6_addr32[4]; + } in6_u; +#define s6_addr in6_u.u6_addr8 +#define s6_addr16 in6_u.u6_addr16 +#define s6_addr32 in6_u.u6_addr32 +#define s6_addr64 in6_u.u6_addr64 + }; + +#define IN6ADDR_ANY_INIT { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } +#define IN6ADDR_LOOPBACK_INIT { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1 } +#endif /* __MINGW32__ */ + + +#if (defined _MSC_VER) || (defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF)) +typedef unsigned short sa_family_t; +#endif + + +#if defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF) + +#define __SOCKADDR_COMMON(sa_prefix) \ + sa_family_t sa_prefix##family + +/* Ditto, for IPv6. */ +struct sockaddr_in6 + { + __SOCKADDR_COMMON (sin6_); + u_int16_t sin6_port; /* Transport layer port # */ + u_int32_t sin6_flowinfo; /* IPv6 flow information */ + struct in6_addr sin6_addr; /* IPv6 address */ + }; + +#define IN6_IS_ADDR_V4MAPPED(a) \ + ((((u_int32_t *) (a))[0] == 0) && (((u_int32_t *) (a))[1] == 0) && \ + (((u_int32_t *) (a))[2] == htonl (0xffff))) + +#define IN6_IS_ADDR_MULTICAST(a) (((u_int8_t *) (a))[0] == 0xff) + +#define IN6_IS_ADDR_LINKLOCAL(a) \ + ((((u_int32_t *) (a))[0] & htonl (0xffc00000)) == htonl (0xfe800000)) + +#define IN6_IS_ADDR_LOOPBACK(a) \ + (((u_int32_t *) (a))[0] == 0 && ((u_int32_t *) (a))[1] == 0 && \ + ((u_int32_t *) (a))[2] == 0 && ((u_int32_t *) (a))[3] == htonl (1)) +#endif /* __MINGW32__ */ + +#define ip6_vfc ip6_ctlun.ip6_un2_vfc +#define ip6_flow ip6_ctlun.ip6_un1.ip6_un1_flow +#define ip6_plen ip6_ctlun.ip6_un1.ip6_un1_plen +#define ip6_nxt ip6_ctlun.ip6_un1.ip6_un1_nxt +#define ip6_hlim ip6_ctlun.ip6_un1.ip6_un1_hlim +#define ip6_hops ip6_ctlun.ip6_un1.ip6_un1_hlim + +#define nd_rd_type nd_rd_hdr.icmp6_type +#define nd_rd_code nd_rd_hdr.icmp6_code +#define nd_rd_cksum nd_rd_hdr.icmp6_cksum +#define nd_rd_reserved nd_rd_hdr.icmp6_data32[0] + +/* + * IPV6 extension headers + */ +#define IPPROTO_HOPOPTS 0 /* IPv6 hop-by-hop options */ +#define IPPROTO_IPV6 41 /* IPv6 header. */ +#define IPPROTO_ROUTING 43 /* IPv6 routing header */ +#define IPPROTO_FRAGMENT 44 /* IPv6 fragmentation header */ +#define IPPROTO_ESP 50 /* encapsulating security payload */ +#define IPPROTO_AH 51 /* authentication header */ +#define IPPROTO_ICMPV6 58 /* ICMPv6 */ +#define IPPROTO_NONE 59 /* IPv6 no next header */ +#define IPPROTO_DSTOPTS 60 /* IPv6 destination options */ +#define IPPROTO_PIM 103 /* Protocol Independent Multicast. */ + +#define IPV6_RTHDR_TYPE_0 0 + +/* Option types and related macros */ +#define IP6OPT_PAD1 0x00 /* 00 0 00000 */ +#define IP6OPT_PADN 0x01 /* 00 0 00001 */ +#define IP6OPT_JUMBO 0xC2 /* 11 0 00010 = 194 */ +#define IP6OPT_JUMBO_LEN 6 +#define IP6OPT_ROUTER_ALERT 0x05 /* 00 0 00101 */ + +#define IP6OPT_RTALERT_LEN 4 +#define IP6OPT_RTALERT_MLD 0 /* Datagram contains an MLD message */ +#define IP6OPT_RTALERT_RSVP 1 /* Datagram contains an RSVP message */ +#define IP6OPT_RTALERT_ACTNET 2 /* contains an Active Networks msg */ +#define IP6OPT_MINLEN 2 + +#define IP6OPT_BINDING_UPDATE 0xc6 /* 11 0 00110 */ +#define IP6OPT_BINDING_ACK 0x07 /* 00 0 00111 */ +#define IP6OPT_BINDING_REQ 0x08 /* 00 0 01000 */ +#define IP6OPT_HOME_ADDRESS 0xc9 /* 11 0 01001 */ +#define IP6OPT_EID 0x8a /* 10 0 01010 */ + +#define IP6OPT_TYPE(o) ((o) & 0xC0) +#define IP6OPT_TYPE_SKIP 0x00 +#define IP6OPT_TYPE_DISCARD 0x40 +#define IP6OPT_TYPE_FORCEICMP 0x80 +#define IP6OPT_TYPE_ICMP 0xC0 + +#define IP6OPT_MUTABLE 0x20 + + +#if defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF) +#ifndef EAI_ADDRFAMILY +struct addrinfo { + int ai_flags; /* AI_PASSIVE, AI_CANONNAME */ + int ai_family; /* PF_xxx */ + int ai_socktype; /* SOCK_xxx */ + int ai_protocol; /* 0 or IPPROTO_xxx for IPv4 and IPv6 */ + size_t ai_addrlen; /* length of ai_addr */ + char *ai_canonname; /* canonical name for hostname */ + struct sockaddr *ai_addr; /* binary address */ + struct addrinfo *ai_next; /* next structure in linked list */ +}; +#endif +#endif /* __MINGW32__ */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/netif.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/netif.h new file mode 100644 index 0000000..8fe5393 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/netif.h @@ -0,0 +1,52 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef NET_IF_H +#define NET_IF_H + +/* + * Send uip_len bytes from uip_buf to the network interface selected by the + * configNETWORK_INTERFACE_TO_USE constant (defined in FreeRTOSConfig.h). + */ +void vNetifTx( void ); + +/* + * Receive bytes from the network interface selected by the + * configNETWORK_INTERFACE_TO_USE constant (defined in FreeRTOSConfig.h). The + * bytes are placed in uip_buf. The number of bytes copied into uip_buf is + * returned. + */ +UBaseType_t uxNetifRx( void ); + +/* + * Prepare a packet capture session. This will print out all the network + * interfaces available, and the one actually used is set by the + * configNETWORK_INTERFACE_TO_USE constant that is defined in + * FreeRTOSConfig.h. */ +BaseType_t xNetifInit( void ); + +#endif /* NET_IF_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap-bpf.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap-bpf.h new file mode 100644 index 0000000..5fe129d --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap-bpf.h @@ -0,0 +1,47 @@ +/*- + * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from the Stanford/CMU enet packet filter, + * (net/enet.c) distributed as part of 4.3BSD, and code contributed + * to Berkeley by Steven McCanne and Van Jacobson both of Lawrence + * Berkeley Laboratory. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#) $Header: /tcpdump/master/libpcap/pcap-bpf.h,v 1.50 2007/04/01 21:43:55 guy Exp $ (LBL) + */ + +/* + * For backwards compatibility. + * + * Note to OS vendors: do NOT get rid of this file! Some applications + * might expect to be able to include . + */ +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap-namedb.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap-namedb.h new file mode 100644 index 0000000..80a2f00 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap-namedb.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 1994, 1996 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the Computer Systems + * Engineering Group at Lawrence Berkeley Laboratory. + * 4. Neither the name of the University nor of the Laboratory may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#) $Header: /tcpdump/master/libpcap/pcap-namedb.h,v 1.13 2006/10/04 18:13:32 guy Exp $ (LBL) + */ + +/* + * For backwards compatibility. + * + * Note to OS vendors: do NOT get rid of this file! Some applications + * might expect to be able to include . + */ +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap-stdinc.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap-stdinc.h new file mode 100644 index 0000000..cbd62d1 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap-stdinc.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2002 - 2005 NetGroup, Politecnico di Torino (Italy) + * Copyright (c) 2005 - 2009 CACE Technologies, Inc. Davis (California) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Politecnico di Torino nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @(#) $Header: /tcpdump/master/libpcap/pcap-stdinc.h,v 1.10.2.1 2008-10-06 15:38:39 gianluca Exp $ (LBL) + */ + +#define SIZEOF_CHAR 1 +#define SIZEOF_SHORT 2 +#define SIZEOF_INT 4 +#ifndef _MSC_EXTENSIONS +#define SIZEOF_LONG_LONG 8 +#endif + +/* + * Avoids a compiler warning in case this was already defined + * (someone defined _WINSOCKAPI_ when including 'windows.h', in order + * to prevent it from including 'winsock.h') + */ +#ifdef _WINSOCKAPI_ +#undef _WINSOCKAPI_ +#endif +#include + +#include + +#include "bittypes.h" +#include +#include + +#ifndef __MINGW32__ +#include "IP6_misc.h" +#endif + +#define caddr_t char* + +#if _MSC_VER < 1500 +#define snprintf _snprintf +#define vsnprintf _vsnprintf +#define strdup _strdup +#endif + +#define inline __inline + +#ifdef __MINGW32__ +#include +#else /*__MINGW32__*/ +/* MSVC compiler */ +#ifndef _UINTPTR_T_DEFINED +#ifdef _WIN64 +typedef unsigned __int64 uintptr_t; +#else +typedef _W64 unsigned int uintptr_t; +#endif +#define _UINTPTR_T_DEFINED +#endif + +#ifndef _INTPTR_T_DEFINED +#ifdef _WIN64 +typedef __int64 intptr_t; +#else +typedef _W64 int intptr_t; +#endif +#define _INTPTR_T_DEFINED +#endif + +#endif /*__MINGW32__*/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap.h new file mode 100644 index 0000000..935f949 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 1993, 1994, 1995, 1996, 1997 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the Computer Systems + * Engineering Group at Lawrence Berkeley Laboratory. + * 4. Neither the name of the University nor of the Laboratory may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#) $Header: /tcpdump/master/libpcap/pcap.h,v 1.59 2006/10/04 18:09:22 guy Exp $ (LBL) + */ + +/* + * For backwards compatibility. + * + * Note to OS vendors: do NOT get rid of this file! Many applications + * expect to be able to include , and at least some of them + * go through contortions in their configure scripts to try to detect + * OSes that have "helpfully" moved pcap.h to without + * leaving behind a file. + */ +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap/bluetooth.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap/bluetooth.h new file mode 100644 index 0000000..7bf65df --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap/bluetooth.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006 Paolo Abeni (Italy) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * bluetooth data struct + * By Paolo Abeni + * + * @(#) $Header: /tcpdump/master/libpcap/pcap/bluetooth.h,v 1.1 2007/09/22 02:10:17 guy Exp $ + */ + +#ifndef _PCAP_BLUETOOTH_STRUCTS_H__ +#define _PCAP_BLUETOOTH_STRUCTS_H__ + +/* + * Header prepended libpcap to each bluetooth h:4 frame. + * fields are in network byte order + */ +typedef struct _pcap_bluetooth_h4_header { + u_int32_t direction; /* if first bit is set direction is incoming */ +} pcap_bluetooth_h4_header; + + +#endif diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap/bpf.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap/bpf.h new file mode 100644 index 0000000..9f4ca33 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap/bpf.h @@ -0,0 +1,934 @@ +/*- + * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from the Stanford/CMU enet packet filter, + * (net/enet.c) distributed as part of 4.3BSD, and code contributed + * to Berkeley by Steven McCanne and Van Jacobson both of Lawrence + * Berkeley Laboratory. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)bpf.h 7.1 (Berkeley) 5/7/91 + * + * @(#) $Header: /tcpdump/master/libpcap/pcap/bpf.h,v 1.19.2.8 2008-09-22 20:16:01 guy Exp $ (LBL) + */ + +/* + * This is libpcap's cut-down version of bpf.h; it includes only + * the stuff needed for the code generator and the userland BPF + * interpreter, and the libpcap APIs for setting filters, etc.. + * + * "pcap-bpf.c" will include the native OS version, as it deals with + * the OS's BPF implementation. + * + * XXX - should this all just be moved to "pcap.h"? + */ + +#ifndef BPF_MAJOR_VERSION + +#ifdef __cplusplus +extern "C" { +#endif + +/* BSD style release date */ +#define BPF_RELEASE 199606 + +#ifdef MSDOS /* must be 32-bit */ +typedef long bpf_int32; +typedef unsigned long bpf_u_int32; +#else +typedef int bpf_int32; +typedef u_int bpf_u_int32; +#endif + +/* + * Alignment macros. BPF_WORDALIGN rounds up to the next + * even multiple of BPF_ALIGNMENT. + */ +#ifndef __NetBSD__ +#define BPF_ALIGNMENT sizeof(bpf_int32) +#else +#define BPF_ALIGNMENT sizeof(long) +#endif +#define BPF_WORDALIGN(x) (((x)+(BPF_ALIGNMENT-1))&~(BPF_ALIGNMENT-1)) + +#define BPF_MAXBUFSIZE 0x8000 +#define BPF_MINBUFSIZE 32 + +/* + * Structure for "pcap_compile()", "pcap_setfilter()", etc.. + */ +struct bpf_program { + u_int bf_len; + struct bpf_insn *bf_insns; +}; + +/* + * Struct return by BIOCVERSION. This represents the version number of + * the filter language described by the instruction encodings below. + * bpf understands a program iff kernel_major == filter_major && + * kernel_minor >= filter_minor, that is, if the value returned by the + * running kernel has the same major number and a minor number equal + * equal to or less than the filter being downloaded. Otherwise, the + * results are undefined, meaning an error may be returned or packets + * may be accepted haphazardly. + * It has nothing to do with the source code version. + */ +struct bpf_version { + u_short bv_major; + u_short bv_minor; +}; +/* Current version number of filter architecture. */ +#define BPF_MAJOR_VERSION 1 +#define BPF_MINOR_VERSION 1 + +/* + * Data-link level type codes. + * + * Do *NOT* add new values to this list without asking + * "tcpdump-workers@lists.tcpdump.org" for a value. Otherwise, you run + * the risk of using a value that's already being used for some other + * purpose, and of having tools that read libpcap-format captures not + * being able to handle captures with your new DLT_ value, with no hope + * that they will ever be changed to do so (as that would destroy their + * ability to read captures using that value for that other purpose). + */ + +/* + * These are the types that are the same on all platforms, and that + * have been defined by for ages. + */ +#define DLT_NULL 0 /* BSD loopback encapsulation */ +#define DLT_EN10MB 1 /* Ethernet (10Mb) */ +#define DLT_EN3MB 2 /* Experimental Ethernet (3Mb) */ +#define DLT_AX25 3 /* Amateur Radio AX.25 */ +#define DLT_PRONET 4 /* Proteon ProNET Token Ring */ +#define DLT_CHAOS 5 /* Chaos */ +#define DLT_IEEE802 6 /* 802.5 Token Ring */ +#define DLT_ARCNET 7 /* ARCNET, with BSD-style header */ +#define DLT_SLIP 8 /* Serial Line IP */ +#define DLT_PPP 9 /* Point-to-point Protocol */ +#define DLT_FDDI 10 /* FDDI */ + +/* + * These are types that are different on some platforms, and that + * have been defined by for ages. We use #ifdefs to + * detect the BSDs that define them differently from the traditional + * libpcap + * + * XXX - DLT_ATM_RFC1483 is 13 in BSD/OS, and DLT_RAW is 14 in BSD/OS, + * but I don't know what the right #define is for BSD/OS. + */ +#define DLT_ATM_RFC1483 11 /* LLC-encapsulated ATM */ + +#ifdef __OpenBSD__ +#define DLT_RAW 14 /* raw IP */ +#else +#define DLT_RAW 12 /* raw IP */ +#endif + +/* + * Given that the only OS that currently generates BSD/OS SLIP or PPP + * is, well, BSD/OS, arguably everybody should have chosen its values + * for DLT_SLIP_BSDOS and DLT_PPP_BSDOS, which are 15 and 16, but they + * didn't. So it goes. + */ +#if defined(__NetBSD__) || defined(__FreeBSD__) +#ifndef DLT_SLIP_BSDOS +#define DLT_SLIP_BSDOS 13 /* BSD/OS Serial Line IP */ +#define DLT_PPP_BSDOS 14 /* BSD/OS Point-to-point Protocol */ +#endif +#else +#define DLT_SLIP_BSDOS 15 /* BSD/OS Serial Line IP */ +#define DLT_PPP_BSDOS 16 /* BSD/OS Point-to-point Protocol */ +#endif + +/* + * 17 is used for DLT_OLD_PFLOG in OpenBSD; + * OBSOLETE: DLT_PFLOG is 117 in OpenBSD now as well. See below. + * 18 is used for DLT_PFSYNC in OpenBSD; don't use it for anything else. + */ + +#define DLT_ATM_CLIP 19 /* Linux Classical-IP over ATM */ + +/* + * Apparently Redback uses this for its SmartEdge 400/800. I hope + * nobody else decided to use it, too. + */ +#define DLT_REDBACK_SMARTEDGE 32 + +/* + * These values are defined by NetBSD; other platforms should refrain from + * using them for other purposes, so that NetBSD savefiles with link + * types of 50 or 51 can be read as this type on all platforms. + */ +#define DLT_PPP_SERIAL 50 /* PPP over serial with HDLC encapsulation */ +#define DLT_PPP_ETHER 51 /* PPP over Ethernet */ + +/* + * The Axent Raptor firewall - now the Symantec Enterprise Firewall - uses + * a link-layer type of 99 for the tcpdump it supplies. The link-layer + * header has 6 bytes of unknown data, something that appears to be an + * Ethernet type, and 36 bytes that appear to be 0 in at least one capture + * I've seen. + */ +#define DLT_SYMANTEC_FIREWALL 99 + +/* + * Values between 100 and 103 are used in capture file headers as + * link-layer types corresponding to DLT_ types that differ + * between platforms; don't use those values for new DLT_ new types. + */ + +/* + * This value was defined by libpcap 0.5; platforms that have defined + * it with a different value should define it here with that value - + * a link type of 104 in a save file will be mapped to DLT_C_HDLC, + * whatever value that happens to be, so programs will correctly + * handle files with that link type regardless of the value of + * DLT_C_HDLC. + * + * The name DLT_C_HDLC was used by BSD/OS; we use that name for source + * compatibility with programs written for BSD/OS. + * + * libpcap 0.5 defined it as DLT_CHDLC; we define DLT_CHDLC as well, + * for source compatibility with programs written for libpcap 0.5. + */ +#define DLT_C_HDLC 104 /* Cisco HDLC */ +#define DLT_CHDLC DLT_C_HDLC + +#define DLT_IEEE802_11 105 /* IEEE 802.11 wireless */ + +/* + * 106 is reserved for Linux Classical IP over ATM; it's like DLT_RAW, + * except when it isn't. (I.e., sometimes it's just raw IP, and + * sometimes it isn't.) We currently handle it as DLT_LINUX_SLL, + * so that we don't have to worry about the link-layer header.) + */ + +/* + * Frame Relay; BSD/OS has a DLT_FR with a value of 11, but that collides + * with other values. + * DLT_FR and DLT_FRELAY packets start with the Q.922 Frame Relay header + * (DLCI, etc.). + */ +#define DLT_FRELAY 107 + +/* + * OpenBSD DLT_LOOP, for loopback devices; it's like DLT_NULL, except + * that the AF_ type in the link-layer header is in network byte order. + * + * DLT_LOOP is 12 in OpenBSD, but that's DLT_RAW in other OSes, so + * we don't use 12 for it in OSes other than OpenBSD. + */ +#ifdef __OpenBSD__ +#define DLT_LOOP 12 +#else +#define DLT_LOOP 108 +#endif + +/* + * Encapsulated packets for IPsec; DLT_ENC is 13 in OpenBSD, but that's + * DLT_SLIP_BSDOS in NetBSD, so we don't use 13 for it in OSes other + * than OpenBSD. + */ +#ifdef __OpenBSD__ +#define DLT_ENC 13 +#else +#define DLT_ENC 109 +#endif + +/* + * Values between 110 and 112 are reserved for use in capture file headers + * as link-layer types corresponding to DLT_ types that might differ + * between platforms; don't use those values for new DLT_ types + * other than the corresponding DLT_ types. + */ + +/* + * This is for Linux cooked sockets. + */ +#define DLT_LINUX_SLL 113 + +/* + * Apple LocalTalk hardware. + */ +#define DLT_LTALK 114 + +/* + * Acorn Econet. + */ +#define DLT_ECONET 115 + +/* + * Reserved for use with OpenBSD ipfilter. + */ +#define DLT_IPFILTER 116 + +/* + * OpenBSD DLT_PFLOG; DLT_PFLOG is 17 in OpenBSD, but that's DLT_LANE8023 + * in SuSE 6.3, so we can't use 17 for it in capture-file headers. + * + * XXX: is there a conflict with DLT_PFSYNC 18 as well? + */ +#ifdef __OpenBSD__ +#define DLT_OLD_PFLOG 17 +#define DLT_PFSYNC 18 +#endif +#define DLT_PFLOG 117 + +/* + * Registered for Cisco-internal use. + */ +#define DLT_CISCO_IOS 118 + +/* + * For 802.11 cards using the Prism II chips, with a link-layer + * header including Prism monitor mode information plus an 802.11 + * header. + */ +#define DLT_PRISM_HEADER 119 + +/* + * Reserved for Aironet 802.11 cards, with an Aironet link-layer header + * (see Doug Ambrisko's FreeBSD patches). + */ +#define DLT_AIRONET_HEADER 120 + +/* + * Reserved for Siemens HiPath HDLC. + */ +#define DLT_HHDLC 121 + +/* + * This is for RFC 2625 IP-over-Fibre Channel. + * + * This is not for use with raw Fibre Channel, where the link-layer + * header starts with a Fibre Channel frame header; it's for IP-over-FC, + * where the link-layer header starts with an RFC 2625 Network_Header + * field. + */ +#define DLT_IP_OVER_FC 122 + +/* + * This is for Full Frontal ATM on Solaris with SunATM, with a + * pseudo-header followed by an AALn PDU. + * + * There may be other forms of Full Frontal ATM on other OSes, + * with different pseudo-headers. + * + * If ATM software returns a pseudo-header with VPI/VCI information + * (and, ideally, packet type information, e.g. signalling, ILMI, + * LANE, LLC-multiplexed traffic, etc.), it should not use + * DLT_ATM_RFC1483, but should get a new DLT_ value, so tcpdump + * and the like don't have to infer the presence or absence of a + * pseudo-header and the form of the pseudo-header. + */ +#define DLT_SUNATM 123 /* Solaris+SunATM */ + +/* + * Reserved as per request from Kent Dahlgren + * for private use. + */ +#define DLT_RIO 124 /* RapidIO */ +#define DLT_PCI_EXP 125 /* PCI Express */ +#define DLT_AURORA 126 /* Xilinx Aurora link layer */ + +/* + * Header for 802.11 plus a number of bits of link-layer information + * including radio information, used by some recent BSD drivers as + * well as the madwifi Atheros driver for Linux. + */ +#define DLT_IEEE802_11_RADIO 127 /* 802.11 plus radiotap radio header */ + +/* + * Reserved for the TZSP encapsulation, as per request from + * Chris Waters + * TZSP is a generic encapsulation for any other link type, + * which includes a means to include meta-information + * with the packet, e.g. signal strength and channel + * for 802.11 packets. + */ +#define DLT_TZSP 128 /* Tazmen Sniffer Protocol */ + +/* + * BSD's ARCNET headers have the source host, destination host, + * and type at the beginning of the packet; that's what's handed + * up to userland via BPF. + * + * Linux's ARCNET headers, however, have a 2-byte offset field + * between the host IDs and the type; that's what's handed up + * to userland via PF_PACKET sockets. + * + * We therefore have to have separate DLT_ values for them. + */ +#define DLT_ARCNET_LINUX 129 /* ARCNET */ + +/* + * Juniper-private data link types, as per request from + * Hannes Gredler . The DLT_s are used + * for passing on chassis-internal metainformation such as + * QOS profiles, etc.. + */ +#define DLT_JUNIPER_MLPPP 130 +#define DLT_JUNIPER_MLFR 131 +#define DLT_JUNIPER_ES 132 +#define DLT_JUNIPER_GGSN 133 +#define DLT_JUNIPER_MFR 134 +#define DLT_JUNIPER_ATM2 135 +#define DLT_JUNIPER_SERVICES 136 +#define DLT_JUNIPER_ATM1 137 + +/* + * Apple IP-over-IEEE 1394, as per a request from Dieter Siegmund + * . The header that's presented is an Ethernet-like + * header: + * + * #define FIREWIRE_EUI64_LEN 8 + * struct firewire_header { + * u_char firewire_dhost[FIREWIRE_EUI64_LEN]; + * u_char firewire_shost[FIREWIRE_EUI64_LEN]; + * u_short firewire_type; + * }; + * + * with "firewire_type" being an Ethernet type value, rather than, + * for example, raw GASP frames being handed up. + */ +#define DLT_APPLE_IP_OVER_IEEE1394 138 + +/* + * Various SS7 encapsulations, as per a request from Jeff Morriss + * and subsequent discussions. + */ +#define DLT_MTP2_WITH_PHDR 139 /* pseudo-header with various info, followed by MTP2 */ +#define DLT_MTP2 140 /* MTP2, without pseudo-header */ +#define DLT_MTP3 141 /* MTP3, without pseudo-header or MTP2 */ +#define DLT_SCCP 142 /* SCCP, without pseudo-header or MTP2 or MTP3 */ + +/* + * DOCSIS MAC frames. + */ +#define DLT_DOCSIS 143 + +/* + * Linux-IrDA packets. Protocol defined at http://www.irda.org. + * Those packets include IrLAP headers and above (IrLMP...), but + * don't include Phy framing (SOF/EOF/CRC & byte stuffing), because Phy + * framing can be handled by the hardware and depend on the bitrate. + * This is exactly the format you would get capturing on a Linux-IrDA + * interface (irdaX), but not on a raw serial port. + * Note the capture is done in "Linux-cooked" mode, so each packet include + * a fake packet header (struct sll_header). This is because IrDA packet + * decoding is dependant on the direction of the packet (incomming or + * outgoing). + * When/if other platform implement IrDA capture, we may revisit the + * issue and define a real DLT_IRDA... + * Jean II + */ +#define DLT_LINUX_IRDA 144 + +/* + * Reserved for IBM SP switch and IBM Next Federation switch. + */ +#define DLT_IBM_SP 145 +#define DLT_IBM_SN 146 + +/* + * Reserved for private use. If you have some link-layer header type + * that you want to use within your organization, with the capture files + * using that link-layer header type not ever be sent outside your + * organization, you can use these values. + * + * No libpcap release will use these for any purpose, nor will any + * tcpdump release use them, either. + * + * Do *NOT* use these in capture files that you expect anybody not using + * your private versions of capture-file-reading tools to read; in + * particular, do *NOT* use them in products, otherwise you may find that + * people won't be able to use tcpdump, or snort, or Ethereal, or... to + * read capture files from your firewall/intrusion detection/traffic + * monitoring/etc. appliance, or whatever product uses that DLT_ value, + * and you may also find that the developers of those applications will + * not accept patches to let them read those files. + * + * Also, do not use them if somebody might send you a capture using them + * for *their* private type and tools using them for *your* private type + * would have to read them. + * + * Instead, ask "tcpdump-workers@lists.tcpdump.org" for a new DLT_ value, + * as per the comment above, and use the type you're given. + */ +#define DLT_USER0 147 +#define DLT_USER1 148 +#define DLT_USER2 149 +#define DLT_USER3 150 +#define DLT_USER4 151 +#define DLT_USER5 152 +#define DLT_USER6 153 +#define DLT_USER7 154 +#define DLT_USER8 155 +#define DLT_USER9 156 +#define DLT_USER10 157 +#define DLT_USER11 158 +#define DLT_USER12 159 +#define DLT_USER13 160 +#define DLT_USER14 161 +#define DLT_USER15 162 + +/* + * For future use with 802.11 captures - defined by AbsoluteValue + * Systems to store a number of bits of link-layer information + * including radio information: + * + * http://www.shaftnet.org/~pizza/software/capturefrm.txt + * + * but it might be used by some non-AVS drivers now or in the + * future. + */ +#define DLT_IEEE802_11_RADIO_AVS 163 /* 802.11 plus AVS radio header */ + +/* + * Juniper-private data link type, as per request from + * Hannes Gredler . The DLT_s are used + * for passing on chassis-internal metainformation such as + * QOS profiles, etc.. + */ +#define DLT_JUNIPER_MONITOR 164 + +/* + * Reserved for BACnet MS/TP. + */ +#define DLT_BACNET_MS_TP 165 + +/* + * Another PPP variant as per request from Karsten Keil . + * + * This is used in some OSes to allow a kernel socket filter to distinguish + * between incoming and outgoing packets, on a socket intended to + * supply pppd with outgoing packets so it can do dial-on-demand and + * hangup-on-lack-of-demand; incoming packets are filtered out so they + * don't cause pppd to hold the connection up (you don't want random + * input packets such as port scans, packets from old lost connections, + * etc. to force the connection to stay up). + * + * The first byte of the PPP header (0xff03) is modified to accomodate + * the direction - 0x00 = IN, 0x01 = OUT. + */ +#define DLT_PPP_PPPD 166 + +/* + * Names for backwards compatibility with older versions of some PPP + * software; new software should use DLT_PPP_PPPD. + */ +#define DLT_PPP_WITH_DIRECTION DLT_PPP_PPPD +#define DLT_LINUX_PPP_WITHDIRECTION DLT_PPP_PPPD + +/* + * Juniper-private data link type, as per request from + * Hannes Gredler . The DLT_s are used + * for passing on chassis-internal metainformation such as + * QOS profiles, cookies, etc.. + */ +#define DLT_JUNIPER_PPPOE 167 +#define DLT_JUNIPER_PPPOE_ATM 168 + +#define DLT_GPRS_LLC 169 /* GPRS LLC */ +#define DLT_GPF_T 170 /* GPF-T (ITU-T G.7041/Y.1303) */ +#define DLT_GPF_F 171 /* GPF-F (ITU-T G.7041/Y.1303) */ + +/* + * Requested by Oolan Zimmer for use in Gcom's T1/E1 line + * monitoring equipment. + */ +#define DLT_GCOM_T1E1 172 +#define DLT_GCOM_SERIAL 173 + +/* + * Juniper-private data link type, as per request from + * Hannes Gredler . The DLT_ is used + * for internal communication to Physical Interface Cards (PIC) + */ +#define DLT_JUNIPER_PIC_PEER 174 + +/* + * Link types requested by Gregor Maier of Endace + * Measurement Systems. They add an ERF header (see + * http://www.endace.com/support/EndaceRecordFormat.pdf) in front of + * the link-layer header. + */ +#define DLT_ERF_ETH 175 /* Ethernet */ +#define DLT_ERF_POS 176 /* Packet-over-SONET */ + +/* + * Requested by Daniele Orlandi for raw LAPD + * for vISDN (http://www.orlandi.com/visdn/). Its link-layer header + * includes additional information before the LAPD header, so it's + * not necessarily a generic LAPD header. + */ +#define DLT_LINUX_LAPD 177 + +/* + * Juniper-private data link type, as per request from + * Hannes Gredler . + * The DLT_ are used for prepending meta-information + * like interface index, interface name + * before standard Ethernet, PPP, Frelay & C-HDLC Frames + */ +#define DLT_JUNIPER_ETHER 178 +#define DLT_JUNIPER_PPP 179 +#define DLT_JUNIPER_FRELAY 180 +#define DLT_JUNIPER_CHDLC 181 + +/* + * Multi Link Frame Relay (FRF.16) + */ +#define DLT_MFR 182 + +/* + * Juniper-private data link type, as per request from + * Hannes Gredler . + * The DLT_ is used for internal communication with a + * voice Adapter Card (PIC) + */ +#define DLT_JUNIPER_VP 183 + +/* + * Arinc 429 frames. + * DLT_ requested by Gianluca Varenni . + * Every frame contains a 32bit A429 label. + * More documentation on Arinc 429 can be found at + * http://www.condoreng.com/support/downloads/tutorials/ARINCTutorial.pdf + */ +#define DLT_A429 184 + +/* + * Arinc 653 Interpartition Communication messages. + * DLT_ requested by Gianluca Varenni . + * Please refer to the A653-1 standard for more information. + */ +#define DLT_A653_ICM 185 + +/* + * USB packets, beginning with a USB setup header; requested by + * Paolo Abeni . + */ +#define DLT_USB 186 + +/* + * Bluetooth HCI UART transport layer (part H:4); requested by + * Paolo Abeni. + */ +#define DLT_BLUETOOTH_HCI_H4 187 + +/* + * IEEE 802.16 MAC Common Part Sublayer; requested by Maria Cruz + * . + */ +#define DLT_IEEE802_16_MAC_CPS 188 + +/* + * USB packets, beginning with a Linux USB header; requested by + * Paolo Abeni . + */ +#define DLT_USB_LINUX 189 + +/* + * Controller Area Network (CAN) v. 2.0B packets. + * DLT_ requested by Gianluca Varenni . + * Used to dump CAN packets coming from a CAN Vector board. + * More documentation on the CAN v2.0B frames can be found at + * http://www.can-cia.org/downloads/?269 + */ +#define DLT_CAN20B 190 + +/* + * IEEE 802.15.4, with address fields padded, as is done by Linux + * drivers; requested by Juergen Schimmer. + */ +#define DLT_IEEE802_15_4_LINUX 191 + +/* + * Per Packet Information encapsulated packets. + * DLT_ requested by Gianluca Varenni . + */ +#define DLT_PPI 192 + +/* + * Header for 802.16 MAC Common Part Sublayer plus a radiotap radio header; + * requested by Charles Clancy. + */ +#define DLT_IEEE802_16_MAC_CPS_RADIO 193 + +/* + * Juniper-private data link type, as per request from + * Hannes Gredler . + * The DLT_ is used for internal communication with a + * integrated service module (ISM). + */ +#define DLT_JUNIPER_ISM 194 + +/* + * IEEE 802.15.4, exactly as it appears in the spec (no padding, no + * nothing); requested by Mikko Saarnivala . + */ +#define DLT_IEEE802_15_4 195 + +/* + * Various link-layer types, with a pseudo-header, for SITA + * (http://www.sita.aero/); requested by Fulko Hew (fulko.hew@gmail.com). + */ +#define DLT_SITA 196 + +/* + * Various link-layer types, with a pseudo-header, for Endace DAG cards; + * encapsulates Endace ERF records. Requested by Stephen Donnelly + * . + */ +#define DLT_ERF 197 + +/* + * Special header prepended to Ethernet packets when capturing from a + * u10 Networks board. Requested by Phil Mulholland + * . + */ +#define DLT_RAIF1 198 + +/* + * IPMB packet for IPMI, beginning with the I2C slave address, followed + * by the netFn and LUN, etc.. Requested by Chanthy Toeung + * . + */ +#define DLT_IPMB 199 + +/* + * Juniper-private data link type, as per request from + * Hannes Gredler . + * The DLT_ is used for capturing data on a secure tunnel interface. + */ +#define DLT_JUNIPER_ST 200 + +/* + * Bluetooth HCI UART transport layer (part H:4), with pseudo-header + * that includes direction information; requested by Paolo Abeni. + */ +#define DLT_BLUETOOTH_HCI_H4_WITH_PHDR 201 + +/* + * AX.25 packet with a 1-byte KISS header; see + * + * http://www.ax25.net/kiss.htm + * + * as per Richard Stearn . + */ +#define DLT_AX25_KISS 202 + +/* + * LAPD packets from an ISDN channel, starting with the address field, + * with no pseudo-header. + * Requested by Varuna De Silva . + */ +#define DLT_LAPD 203 + +/* + * Variants of various link-layer headers, with a one-byte direction + * pseudo-header prepended - zero means "received by this host", + * non-zero (any non-zero value) means "sent by this host" - as per + * Will Barker . + */ +#define DLT_PPP_WITH_DIR 204 /* PPP - don't confuse with DLT_PPP_WITH_DIRECTION */ +#define DLT_C_HDLC_WITH_DIR 205 /* Cisco HDLC */ +#define DLT_FRELAY_WITH_DIR 206 /* Frame Relay */ +#define DLT_LAPB_WITH_DIR 207 /* LAPB */ + +/* + * 208 is reserved for an as-yet-unspecified proprietary link-layer + * type, as requested by Will Barker. + */ + +/* + * IPMB with a Linux-specific pseudo-header; as requested by Alexey Neyman + * . + */ +#define DLT_IPMB_LINUX 209 + +/* + * FlexRay automotive bus - http://www.flexray.com/ - as requested + * by Hannes Kaelber . + */ +#define DLT_FLEXRAY 210 + +/* + * Media Oriented Systems Transport (MOST) bus for multimedia + * transport - http://www.mostcooperation.com/ - as requested + * by Hannes Kaelber . + */ +#define DLT_MOST 211 + +/* + * Local Interconnect Network (LIN) bus for vehicle networks - + * http://www.lin-subbus.org/ - as requested by Hannes Kaelber + * . + */ +#define DLT_LIN 212 + +/* + * X2E-private data link type used for serial line capture, + * as requested by Hannes Kaelber . + */ +#define DLT_X2E_SERIAL 213 + +/* + * X2E-private data link type used for the Xoraya data logger + * family, as requested by Hannes Kaelber . + */ +#define DLT_X2E_XORAYA 214 + +/* + * IEEE 802.15.4, exactly as it appears in the spec (no padding, no + * nothing), but with the PHY-level data for non-ASK PHYs (4 octets + * of 0 as preamble, one octet of SFD, one octet of frame length+ + * reserved bit, and then the MAC-layer data, starting with the + * frame control field). + * + * Requested by Max Filippov . + */ +#define DLT_IEEE802_15_4_NONASK_PHY 215 + + +/* + * DLT and savefile link type values are split into a class and + * a member of that class. A class value of 0 indicates a regular + * DLT_/LINKTYPE_ value. + */ +#define DLT_CLASS(x) ((x) & 0x03ff0000) + +/* + * NetBSD-specific generic "raw" link type. The class value indicates + * that this is the generic raw type, and the lower 16 bits are the + * address family we're dealing with. Those values are NetBSD-specific; + * do not assume that they correspond to AF_ values for your operating + * system. + */ +#define DLT_CLASS_NETBSD_RAWAF 0x02240000 +#define DLT_NETBSD_RAWAF(af) (DLT_CLASS_NETBSD_RAWAF | (af)) +#define DLT_NETBSD_RAWAF_AF(x) ((x) & 0x0000ffff) +#define DLT_IS_NETBSD_RAWAF(x) (DLT_CLASS(x) == DLT_CLASS_NETBSD_RAWAF) + + +/* + * The instruction encodings. + */ +/* instruction classes */ +#define BPF_CLASS(code) ((code) & 0x07) +#define BPF_LD 0x00 +#define BPF_LDX 0x01 +#define BPF_ST 0x02 +#define BPF_STX 0x03 +#define BPF_ALU 0x04 +#define BPF_JMP 0x05 +#define BPF_RET 0x06 +#define BPF_MISC 0x07 + +/* ld/ldx fields */ +#define BPF_SIZE(code) ((code) & 0x18) +#define BPF_W 0x00 +#define BPF_H 0x08 +#define BPF_B 0x10 +#define BPF_MODE(code) ((code) & 0xe0) +#define BPF_IMM 0x00 +#define BPF_ABS 0x20 +#define BPF_IND 0x40 +#define BPF_MEM 0x60 +#define BPF_LEN 0x80 +#define BPF_MSH 0xa0 + +/* alu/jmp fields */ +#define BPF_OP(code) ((code) & 0xf0) +#define BPF_ADD 0x00 +#define BPF_SUB 0x10 +#define BPF_MUL 0x20 +#define BPF_DIV 0x30 +#define BPF_OR 0x40 +#define BPF_AND 0x50 +#define BPF_LSH 0x60 +#define BPF_RSH 0x70 +#define BPF_NEG 0x80 +#define BPF_JA 0x00 +#define BPF_JEQ 0x10 +#define BPF_JGT 0x20 +#define BPF_JGE 0x30 +#define BPF_JSET 0x40 +#define BPF_SRC(code) ((code) & 0x08) +#define BPF_K 0x00 +#define BPF_X 0x08 + +/* ret - BPF_K and BPF_X also apply */ +#define BPF_RVAL(code) ((code) & 0x18) +#define BPF_A 0x10 + +/* misc */ +#define BPF_MISCOP(code) ((code) & 0xf8) +#define BPF_TAX 0x00 +#define BPF_TXA 0x80 + +/* + * The instruction data structure. + */ +struct bpf_insn { + u_short code; + u_char jt; + u_char jf; + bpf_u_int32 k; +}; + +/* + * Macros for insn array initializers. + */ +#define BPF_STMT(code, k) { (u_short)(code), 0, 0, k } +#define BPF_JUMP(code, k, jt, jf) { (u_short)(code), jt, jf, k } + +#if __STDC__ || defined(__cplusplus) +extern int bpf_validate(const struct bpf_insn *, int); +extern u_int bpf_filter(const struct bpf_insn *, const u_char *, u_int, u_int); +#else +extern int bpf_validate(); +extern u_int bpf_filter(); +#endif + +/* + * Number of scratch memory words (for BPF_LD|BPF_MEM and BPF_ST). + */ +#define BPF_MEMWORDS 16 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap/namedb.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap/namedb.h new file mode 100644 index 0000000..9002c75 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap/namedb.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 1994, 1996 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the Computer Systems + * Engineering Group at Lawrence Berkeley Laboratory. + * 4. Neither the name of the University nor of the Laboratory may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#) $Header: /tcpdump/master/libpcap/pcap/namedb.h,v 1.1 2006/10/04 18:09:22 guy Exp $ (LBL) + */ + +#ifndef lib_pcap_namedb_h +#define lib_pcap_namedb_h + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * As returned by the pcap_next_etherent() + * XXX this stuff doesn't belong in this interface, but this + * library already must do name to address translation, so + * on systems that don't have support for /etc/ethers, we + * export these hooks since they'll + */ +struct pcap_etherent { + u_char addr[6]; + char name[122]; +}; +#ifndef PCAP_ETHERS_FILE +#define PCAP_ETHERS_FILE "/etc/ethers" +#endif +struct pcap_etherent *pcap_next_etherent(FILE *); +u_char *pcap_ether_hostton(const char*); +u_char *pcap_ether_aton(const char *); + +bpf_u_int32 **pcap_nametoaddr(const char *); +#ifdef INET6 +struct addrinfo *pcap_nametoaddrinfo(const char *); +#endif +bpf_u_int32 pcap_nametonetaddr(const char *); + +int pcap_nametoport(const char *, int *, int *); +int pcap_nametoportrange(const char *, int *, int *, int *); +int pcap_nametoproto(const char *); +int pcap_nametoeproto(const char *); +int pcap_nametollc(const char *); +/* + * If a protocol is unknown, PROTO_UNDEF is returned. + * Also, pcap_nametoport() returns the protocol along with the port number. + * If there are ambiguous entried in /etc/services (i.e. domain + * can be either tcp or udp) PROTO_UNDEF is returned. + */ +#define PROTO_UNDEF -1 + +/* XXX move these to pcap-int.h? */ +int __pcap_atodn(const char *, bpf_u_int32 *); +int __pcap_atoin(const char *, bpf_u_int32 *); +u_short __pcap_nametodnaddr(const char *); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap/pcap.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap/pcap.h new file mode 100644 index 0000000..ad8fc40 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap/pcap.h @@ -0,0 +1,407 @@ +/* -*- Mode: c; tab-width: 8; indent-tabs-mode: 1; c-basic-offset: 8; -*- */ +/* + * Copyright (c) 1993, 1994, 1995, 1996, 1997 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the Computer Systems + * Engineering Group at Lawrence Berkeley Laboratory. + * 4. Neither the name of the University nor of the Laboratory may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#) $Header: /tcpdump/master/libpcap/pcap/pcap.h,v 1.4.2.11 2008-10-06 15:38:39 gianluca Exp $ (LBL) + */ + +#ifndef lib_pcap_pcap_h +#define lib_pcap_pcap_h + +#if defined(WIN32) + #include +#elif defined(MSDOS) + #include + #include /* u_int, u_char etc. */ +#else /* UN*X */ + #include + #include +#endif /* WIN32/MSDOS/UN*X */ + +#ifndef PCAP_DONT_INCLUDE_PCAP_BPF_H +#include +#endif + +#include + +#ifdef HAVE_REMOTE + // We have to define the SOCKET here, although it has been defined in sockutils.h + // This is to avoid the distribution of the 'sockutils.h' file around + // (for example in the WinPcap developer's pack) + #ifndef SOCKET + #ifdef WIN32 + #define SOCKET unsigned int + #else + #define SOCKET int + #endif + #endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define PCAP_VERSION_MAJOR 2 +#define PCAP_VERSION_MINOR 4 + +#define PCAP_ERRBUF_SIZE 256 + +/* + * Compatibility for systems that have a bpf.h that + * predates the bpf typedefs for 64-bit support. + */ +#if BPF_RELEASE - 0 < 199406 +typedef int bpf_int32; +typedef u_int bpf_u_int32; +#endif + +typedef struct pcap pcap_t; +typedef struct pcap_dumper pcap_dumper_t; +typedef struct pcap_if pcap_if_t; +typedef struct pcap_addr pcap_addr_t; + +/* + * The first record in the file contains saved values for some + * of the flags used in the printout phases of tcpdump. + * Many fields here are 32 bit ints so compilers won't insert unwanted + * padding; these files need to be interchangeable across architectures. + * + * Do not change the layout of this structure, in any way (this includes + * changes that only affect the length of fields in this structure). + * + * Also, do not change the interpretation of any of the members of this + * structure, in any way (this includes using values other than + * LINKTYPE_ values, as defined in "savefile.c", in the "linktype" + * field). + * + * Instead: + * + * introduce a new structure for the new format, if the layout + * of the structure changed; + * + * send mail to "tcpdump-workers@lists.tcpdump.org", requesting + * a new magic number for your new capture file format, and, when + * you get the new magic number, put it in "savefile.c"; + * + * use that magic number for save files with the changed file + * header; + * + * make the code in "savefile.c" capable of reading files with + * the old file header as well as files with the new file header + * (using the magic number to determine the header format). + * + * Then supply the changes as a patch at + * + * http://sourceforge.net/projects/libpcap/ + * + * so that future versions of libpcap and programs that use it (such as + * tcpdump) will be able to read your new capture file format. + */ +struct pcap_file_header { + bpf_u_int32 magic; + u_short version_major; + u_short version_minor; + bpf_int32 thiszone; /* gmt to local correction */ + bpf_u_int32 sigfigs; /* accuracy of timestamps */ + bpf_u_int32 snaplen; /* max length saved portion of each pkt */ + bpf_u_int32 linktype; /* data link type (LINKTYPE_*) */ +}; + +/* + * Macros for the value returned by pcap_datalink_ext(). + * + * If LT_FCS_LENGTH_PRESENT(x) is true, the LT_FCS_LENGTH(x) macro + * gives the FCS length of packets in the capture. + */ +#define LT_FCS_LENGTH_PRESENT(x) ((x) & 0x04000000) +#define LT_FCS_LENGTH(x) (((x) & 0xF0000000) >> 28) +#define LT_FCS_DATALINK_EXT(x) ((((x) & 0xF) << 28) | 0x04000000) + +typedef enum { + PCAP_D_INOUT = 0, + PCAP_D_IN, + PCAP_D_OUT +} pcap_direction_t; + +/* + * Generic per-packet information, as supplied by libpcap. + * + * The time stamp can and should be a "struct timeval", regardless of + * whether your system supports 32-bit tv_sec in "struct timeval", + * 64-bit tv_sec in "struct timeval", or both if it supports both 32-bit + * and 64-bit applications. The on-disk format of savefiles uses 32-bit + * tv_sec (and tv_usec); this structure is irrelevant to that. 32-bit + * and 64-bit versions of libpcap, even if they're on the same platform, + * should supply the appropriate version of "struct timeval", even if + * that's not what the underlying packet capture mechanism supplies. + */ +struct pcap_pkthdr { + struct timeval ts; /* time stamp */ + bpf_u_int32 caplen; /* length of portion present */ + bpf_u_int32 len; /* length this packet (off wire) */ +}; + +/* + * As returned by the pcap_stats() + */ +struct pcap_stat { + u_int ps_recv; /* number of packets received */ + u_int ps_drop; /* number of packets dropped */ + u_int ps_ifdrop; /* drops by interface XXX not yet supported */ +#ifdef HAVE_REMOTE + u_int ps_capt; /* number of packets that are received by the application; please get rid off the Win32 ifdef */ + u_int ps_sent; /* number of packets sent by the server on the network */ + u_int ps_netdrop; /* number of packets lost on the network */ +#endif /* HAVE_REMOTE */ +}; + +#ifdef MSDOS +/* + * As returned by the pcap_stats_ex() + */ +struct pcap_stat_ex { + u_long rx_packets; /* total packets received */ + u_long tx_packets; /* total packets transmitted */ + u_long rx_bytes; /* total bytes received */ + u_long tx_bytes; /* total bytes transmitted */ + u_long rx_errors; /* bad packets received */ + u_long tx_errors; /* packet transmit problems */ + u_long rx_dropped; /* no space in Rx buffers */ + u_long tx_dropped; /* no space available for Tx */ + u_long multicast; /* multicast packets received */ + u_long collisions; + + /* detailed rx_errors: */ + u_long rx_length_errors; + u_long rx_over_errors; /* receiver ring buff overflow */ + u_long rx_crc_errors; /* recv'd pkt with crc error */ + u_long rx_frame_errors; /* recv'd frame alignment error */ + u_long rx_fifo_errors; /* recv'r fifo overrun */ + u_long rx_missed_errors; /* recv'r missed packet */ + + /* detailed tx_errors */ + u_long tx_aborted_errors; + u_long tx_carrier_errors; + u_long tx_fifo_errors; + u_long tx_heartbeat_errors; + u_long tx_window_errors; + }; +#endif + +/* + * Item in a list of interfaces. + */ +struct pcap_if { + struct pcap_if *next; + char *name; /* name to hand to "pcap_open_live()" */ + char *description; /* textual description of interface, or NULL */ + struct pcap_addr *addresses; + bpf_u_int32 flags; /* PCAP_IF_ interface flags */ +}; + +#define PCAP_IF_LOOPBACK 0x00000001 /* interface is loopback */ + +/* + * Representation of an interface address. + */ +struct pcap_addr { + struct pcap_addr *next; + struct sockaddr *addr; /* address */ + struct sockaddr *netmask; /* netmask for that address */ + struct sockaddr *broadaddr; /* broadcast address for that address */ + struct sockaddr *dstaddr; /* P2P destination address for that address */ +}; + +typedef void (*pcap_handler)(u_char *, const struct pcap_pkthdr *, + const u_char *); + +/* + * Error codes for the pcap API. + * These will all be negative, so you can check for the success or + * failure of a call that returns these codes by checking for a + * negative value. + */ +#define PCAP_ERROR -1 /* generic error code */ +#define PCAP_ERROR_BREAK -2 /* loop terminated by pcap_breakloop */ +#define PCAP_ERROR_NOT_ACTIVATED -3 /* the capture needs to be activated */ +#define PCAP_ERROR_ACTIVATED -4 /* the operation can't be performed on already activated captures */ +#define PCAP_ERROR_NO_SUCH_DEVICE -5 /* no such device exists */ +#define PCAP_ERROR_RFMON_NOTSUP -6 /* this device doesn't support rfmon (monitor) mode */ +#define PCAP_ERROR_NOT_RFMON -7 /* operation supported only in monitor mode */ +#define PCAP_ERROR_PERM_DENIED -8 /* no permission to open the device */ +#define PCAP_ERROR_IFACE_NOT_UP -9 /* interface isn't up */ + +/* + * Warning codes for the pcap API. + * These will all be positive and non-zero, so they won't look like + * errors. + */ +#define PCAP_WARNING 1 /* generic warning code */ +#define PCAP_WARNING_PROMISC_NOTSUP 2 /* this device doesn't support promiscuous mode */ + +char *pcap_lookupdev(char *); +int pcap_lookupnet(const char *, bpf_u_int32 *, bpf_u_int32 *, char *); + +pcap_t *pcap_create(const char *, char *); +int pcap_set_snaplen(pcap_t *, int); +int pcap_set_promisc(pcap_t *, int); +int pcap_can_set_rfmon(pcap_t *); +int pcap_set_rfmon(pcap_t *, int); +int pcap_set_timeout(pcap_t *, int); +int pcap_set_buffer_size(pcap_t *, int); +int pcap_activate(pcap_t *); + +pcap_t *pcap_open_live(const char *, int, int, int, char *); +pcap_t *pcap_open_dead(int, int); +pcap_t *pcap_open_offline(const char *, char *); +#if defined(WIN32) +pcap_t *pcap_hopen_offline(intptr_t, char *); +#if !defined(LIBPCAP_EXPORTS) +#define pcap_fopen_offline(f,b) \ + pcap_hopen_offline(_get_osfhandle(_fileno(f)), b) +#else /*LIBPCAP_EXPORTS*/ +static pcap_t *pcap_fopen_offline(FILE *, char *); +#endif +#else /*WIN32*/ +pcap_t *pcap_fopen_offline(FILE *, char *); +#endif /*WIN32*/ + +void pcap_close(pcap_t *); +int pcap_loop(pcap_t *, int, pcap_handler, u_char *); +int pcap_dispatch(pcap_t *, int, pcap_handler, u_char *); +const u_char* + pcap_next(pcap_t *, struct pcap_pkthdr *); +int pcap_next_ex(pcap_t *, struct pcap_pkthdr **, const u_char **); +void pcap_breakloop(pcap_t *); +int pcap_stats(pcap_t *, struct pcap_stat *); +int pcap_setfilter(pcap_t *, struct bpf_program *); +int pcap_setdirection(pcap_t *, pcap_direction_t); +int pcap_getnonblock(pcap_t *, char *); +int pcap_setnonblock(pcap_t *, int, char *); +int pcap_inject(pcap_t *, const void *, size_t); +int pcap_sendpacket(pcap_t *, const u_char *, int); +const char *pcap_statustostr(int); +const char *pcap_strerror(int); +char *pcap_geterr(pcap_t *); +void pcap_perror(pcap_t *, char *); +int pcap_compile(pcap_t *, struct bpf_program *, const char *, int, + bpf_u_int32); +int pcap_compile_nopcap(int, int, struct bpf_program *, + const char *, int, bpf_u_int32); +void pcap_freecode(struct bpf_program *); +int pcap_offline_filter(struct bpf_program *, const struct pcap_pkthdr *, + const u_char *); +int pcap_datalink(pcap_t *); +int pcap_datalink_ext(pcap_t *); +int pcap_list_datalinks(pcap_t *, int **); +int pcap_set_datalink(pcap_t *, int); +void pcap_free_datalinks(int *); +int pcap_datalink_name_to_val(const char *); +const char *pcap_datalink_val_to_name(int); +const char *pcap_datalink_val_to_description(int); +int pcap_snapshot(pcap_t *); +int pcap_is_swapped(pcap_t *); +int pcap_major_version(pcap_t *); +int pcap_minor_version(pcap_t *); + +/* XXX */ +FILE *pcap_file(pcap_t *); +int pcap_fileno(pcap_t *); + +pcap_dumper_t *pcap_dump_open(pcap_t *, const char *); +pcap_dumper_t *pcap_dump_fopen(pcap_t *, FILE *fp); +FILE *pcap_dump_file(pcap_dumper_t *); +long pcap_dump_ftell(pcap_dumper_t *); +int pcap_dump_flush(pcap_dumper_t *); +void pcap_dump_close(pcap_dumper_t *); +void pcap_dump(u_char *, const struct pcap_pkthdr *, const u_char *); + +int pcap_findalldevs(pcap_if_t **, char *); +void pcap_freealldevs(pcap_if_t *); + +const char *pcap_lib_version(void); + +/* XXX this guy lives in the bpf tree */ +u_int bpf_filter(const struct bpf_insn *, const u_char *, u_int, u_int); +int bpf_validate(const struct bpf_insn *f, int len); +char *bpf_image(const struct bpf_insn *, int); +void bpf_dump(const struct bpf_program *, int); + +#if defined(WIN32) + +/* + * Win32 definitions + */ + +int pcap_setbuff(pcap_t *p, int dim); +int pcap_setmode(pcap_t *p, int mode); +int pcap_setmintocopy(pcap_t *p, int size); + +#ifdef WPCAP +/* Include file with the wpcap-specific extensions */ +#include +#endif /* WPCAP */ + +#define MODE_CAPT 0 +#define MODE_STAT 1 +#define MODE_MON 2 + +#elif defined(MSDOS) + +/* + * MS-DOS definitions + */ + +int pcap_stats_ex (pcap_t *, struct pcap_stat_ex *); +void pcap_set_wait (pcap_t *p, void (*yield)(void), int wait); +u_long pcap_mac_packets (void); + +#else /* UN*X */ + +/* + * UN*X definitions + */ + +int pcap_get_selectable_fd(pcap_t *); + +#endif /* WIN32/MSDOS/UN*X */ + +#ifdef HAVE_REMOTE +/* Includes most of the public stuff that is needed for the remote capture */ +#include +#endif /* HAVE_REMOTE */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap/sll.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap/sll.h new file mode 100644 index 0000000..e9d5452 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap/sll.h @@ -0,0 +1,129 @@ +/*- + * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from the Stanford/CMU enet packet filter, + * (net/enet.c) distributed as part of 4.3BSD, and code contributed + * to Berkeley by Steven McCanne and Van Jacobson both of Lawrence + * Berkeley Laboratory. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#) $Header: /tcpdump/master/libpcap/pcap/sll.h,v 1.2.2.1 2008-05-30 01:36:06 guy Exp $ (LBL) + */ + +/* + * For captures on Linux cooked sockets, we construct a fake header + * that includes: + * + * a 2-byte "packet type" which is one of: + * + * LINUX_SLL_HOST packet was sent to us + * LINUX_SLL_BROADCAST packet was broadcast + * LINUX_SLL_MULTICAST packet was multicast + * LINUX_SLL_OTHERHOST packet was sent to somebody else + * LINUX_SLL_OUTGOING packet was sent *by* us; + * + * a 2-byte Ethernet protocol field; + * + * a 2-byte link-layer type; + * + * a 2-byte link-layer address length; + * + * an 8-byte source link-layer address, whose actual length is + * specified by the previous value. + * + * All fields except for the link-layer address are in network byte order. + * + * DO NOT change the layout of this structure, or change any of the + * LINUX_SLL_ values below. If you must change the link-layer header + * for a "cooked" Linux capture, introduce a new DLT_ type (ask + * "tcpdump-workers@lists.tcpdump.org" for one, so that you don't give it + * a value that collides with a value already being used), and use the + * new header in captures of that type, so that programs that can + * handle DLT_LINUX_SLL captures will continue to handle them correctly + * without any change, and so that capture files with different headers + * can be told apart and programs that read them can dissect the + * packets in them. + */ + +#ifndef lib_pcap_sll_h +#define lib_pcap_sll_h + +/* + * A DLT_LINUX_SLL fake link-layer header. + */ +#define SLL_HDR_LEN 16 /* total header length */ +#define SLL_ADDRLEN 8 /* length of address field */ + +struct sll_header { + u_int16_t sll_pkttype; /* packet type */ + u_int16_t sll_hatype; /* link-layer address type */ + u_int16_t sll_halen; /* link-layer address length */ + u_int8_t sll_addr[SLL_ADDRLEN]; /* link-layer address */ + u_int16_t sll_protocol; /* protocol */ +}; + +/* + * The LINUX_SLL_ values for "sll_pkttype"; these correspond to the + * PACKET_ values on Linux, but are defined here so that they're + * available even on systems other than Linux, and so that they + * don't change even if the PACKET_ values change. + */ +#define LINUX_SLL_HOST 0 +#define LINUX_SLL_BROADCAST 1 +#define LINUX_SLL_MULTICAST 2 +#define LINUX_SLL_OTHERHOST 3 +#define LINUX_SLL_OUTGOING 4 + +/* + * The LINUX_SLL_ values for "sll_protocol"; these correspond to the + * ETH_P_ values on Linux, but are defined here so that they're + * available even on systems other than Linux. We assume, for now, + * that the ETH_P_ values won't change in Linux; if they do, then: + * + * if we don't translate them in "pcap-linux.c", capture files + * won't necessarily be readable if captured on a system that + * defines ETH_P_ values that don't match these values; + * + * if we do translate them in "pcap-linux.c", that makes life + * unpleasant for the BPF code generator, as the values you test + * for in the kernel aren't the values that you test for when + * reading a capture file, so the fixup code run on BPF programs + * handed to the kernel ends up having to do more work. + * + * Add other values here as necessary, for handling packet types that + * might show up on non-Ethernet, non-802.x networks. (Not all the ones + * in the Linux "if_ether.h" will, I suspect, actually show up in + * captures.) + */ +#define LINUX_SLL_P_802_3 0x0001 /* Novell 802.3 frames without 802.2 LLC header */ +#define LINUX_SLL_P_802_2 0x0004 /* 802.2 frames (not D/I/X Ethernet) */ + +#endif diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap/usb.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap/usb.h new file mode 100644 index 0000000..adcd19c --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap/usb.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2006 Paolo Abeni (Italy) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Basic USB data struct + * By Paolo Abeni + * + * @(#) $Header: /tcpdump/master/libpcap/pcap/usb.h,v 1.6 2007/09/22 02:06:08 guy Exp $ + */ + +#ifndef _PCAP_USB_STRUCTS_H__ +#define _PCAP_USB_STRUCTS_H__ + +/* + * possible transfer mode + */ +#define URB_TRANSFER_IN 0x80 +#define URB_ISOCHRONOUS 0x0 +#define URB_INTERRUPT 0x1 +#define URB_CONTROL 0x2 +#define URB_BULK 0x3 + +/* + * possible event type + */ +#define URB_SUBMIT 'S' +#define URB_COMPLETE 'C' +#define URB_ERROR 'E' + +/* + * USB setup header as defined in USB specification. + * Appears at the front of each packet in DLT_USB captures. + */ +typedef struct _usb_setup { + u_int8_t bmRequestType; + u_int8_t bRequest; + u_int16_t wValue; + u_int16_t wIndex; + u_int16_t wLength; +} pcap_usb_setup; + + +/* + * Header prepended by linux kernel to each event. + * Appears at the front of each packet in DLT_USB_LINUX captures. + */ +typedef struct _usb_header { + u_int64_t id; + u_int8_t event_type; + u_int8_t transfer_type; + u_int8_t endpoint_number; + u_int8_t device_address; + u_int16_t bus_id; + char setup_flag;/*if !=0 the urb setup header is not present*/ + char data_flag; /*if !=0 no urb data is present*/ + int64_t ts_sec; + int32_t ts_usec; + int32_t status; + u_int32_t urb_len; + u_int32_t data_len; /* amount of urb data really present in this event*/ + pcap_usb_setup setup; +} pcap_usb_header; + + +#endif diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap/vlan.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap/vlan.h new file mode 100644 index 0000000..b0cb794 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/pcap/vlan.h @@ -0,0 +1,46 @@ +/*- + * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#) $Header: /tcpdump/master/libpcap/pcap/vlan.h,v 1.1.2.2 2008-08-06 07:45:59 guy Exp $ + */ + +#ifndef lib_pcap_vlan_h +#define lib_pcap_vlan_h + +struct vlan_tag { + u_int16_t vlan_tpid; /* ETH_P_8021Q */ + u_int16_t vlan_tci; /* VLAN TCI */ +}; + +#define VLAN_TAG_LEN 4 + +#endif diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/remote-ext.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/remote-ext.h new file mode 100644 index 0000000..9f54d69 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/remote-ext.h @@ -0,0 +1,444 @@ +/* + * Copyright (c) 2002 - 2003 + * NetGroup, Politecnico di Torino (Italy) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Politecnico di Torino nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef __REMOTE_EXT_H__ +#define __REMOTE_EXT_H__ + + +#ifndef HAVE_REMOTE +#error Please do not include this file directly. Just define HAVE_REMOTE and then include pcap.h +#endif + +// Definition for Microsoft Visual Studio +#if _MSC_VER > 1000 +#pragma once +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + \file remote-ext.h + + The goal of this file it to include most of the new definitions that should be + placed into the pcap.h file. + + It includes all new definitions (structures and functions like pcap_open(). + Some of the functions are not really a remote feature, but, right now, + they are placed here. +*/ + + + +// All this stuff is public +/*! \addtogroup remote_struct + \{ +*/ + + + + +/*! + \brief Defines the maximum buffer size in which address, port, interface names are kept. + + In case the adapter name or such is larger than this value, it is truncated. + This is not used by the user; however it must be aware that an hostname / interface + name longer than this value will be truncated. +*/ +#define PCAP_BUF_SIZE 1024 + + +/*! \addtogroup remote_source_ID + \{ +*/ + + +/*! + \brief Internal representation of the type of source in use (file, + remote/local interface). + + This indicates a file, i.e. the user want to open a capture from a local file. +*/ +#define PCAP_SRC_FILE 2 +/*! + \brief Internal representation of the type of source in use (file, + remote/local interface). + + This indicates a local interface, i.e. the user want to open a capture from + a local interface. This does not involve the RPCAP protocol. +*/ +#define PCAP_SRC_IFLOCAL 3 +/*! + \brief Internal representation of the type of source in use (file, + remote/local interface). + + This indicates a remote interface, i.e. the user want to open a capture from + an interface on a remote host. This does involve the RPCAP protocol. +*/ +#define PCAP_SRC_IFREMOTE 4 + +/*! + \} +*/ + + + +/*! \addtogroup remote_source_string + + The formats allowed by the pcap_open() are the following: + - file://path_and_filename [opens a local file] + - rpcap://devicename [opens the selected device devices available on the local host, without using the RPCAP protocol] + - rpcap://host/devicename [opens the selected device available on a remote host] + - rpcap://host:port/devicename [opens the selected device available on a remote host, using a non-standard port for RPCAP] + - adaptername [to open a local adapter; kept for compability, but it is strongly discouraged] + - (NULL) [to open the first local adapter; kept for compability, but it is strongly discouraged] + + The formats allowed by the pcap_findalldevs_ex() are the following: + - file://folder/ [lists all the files in the given folder] + - rpcap:// [lists all local adapters] + - rpcap://host:port/ [lists the devices available on a remote host] + + Referring to the 'host' and 'port' paramters, they can be either numeric or literal. Since + IPv6 is fully supported, these are the allowed formats: + + - host (literal): e.g. host.foo.bar + - host (numeric IPv4): e.g. 10.11.12.13 + - host (numeric IPv4, IPv6 style): e.g. [10.11.12.13] + - host (numeric IPv6): e.g. [1:2:3::4] + - port: can be either numeric (e.g. '80') or literal (e.g. 'http') + + Here you find some allowed examples: + - rpcap://host.foo.bar/devicename [everything literal, no port number] + - rpcap://host.foo.bar:1234/devicename [everything literal, with port number] + - rpcap://10.11.12.13/devicename [IPv4 numeric, no port number] + - rpcap://10.11.12.13:1234/devicename [IPv4 numeric, with port number] + - rpcap://[10.11.12.13]:1234/devicename [IPv4 numeric with IPv6 format, with port number] + - rpcap://[1:2:3::4]/devicename [IPv6 numeric, no port number] + - rpcap://[1:2:3::4]:1234/devicename [IPv6 numeric, with port number] + - rpcap://[1:2:3::4]:http/devicename [IPv6 numeric, with literal port number] + + \{ +*/ + + +/*! + \brief String that will be used to determine the type of source in use (file, + remote/local interface). + + This string will be prepended to the interface name in order to create a string + that contains all the information required to open the source. + + This string indicates that the user wants to open a capture from a local file. +*/ +#define PCAP_SRC_FILE_STRING "file://" +/*! + \brief String that will be used to determine the type of source in use (file, + remote/local interface). + + This string will be prepended to the interface name in order to create a string + that contains all the information required to open the source. + + This string indicates that the user wants to open a capture from a network interface. + This string does not necessarily involve the use of the RPCAP protocol. If the + interface required resides on the local host, the RPCAP protocol is not involved + and the local functions are used. +*/ +#define PCAP_SRC_IF_STRING "rpcap://" + +/*! + \} +*/ + + + + + +/*! + \addtogroup remote_open_flags + \{ +*/ + +/*! + \brief Defines if the adapter has to go in promiscuous mode. + + It is '1' if you have to open the adapter in promiscuous mode, '0' otherwise. + Note that even if this parameter is false, the interface could well be in promiscuous + mode for some other reason (for example because another capture process with + promiscuous mode enabled is currently using that interface). + On on Linux systems with 2.2 or later kernels (that have the "any" device), this + flag does not work on the "any" device; if an argument of "any" is supplied, + the 'promisc' flag is ignored. +*/ +#define PCAP_OPENFLAG_PROMISCUOUS 1 + +/*! + \brief Defines if the data trasfer (in case of a remote + capture) has to be done with UDP protocol. + + If it is '1' if you want a UDP data connection, '0' if you want + a TCP data connection; control connection is always TCP-based. + A UDP connection is much lighter, but it does not guarantee that all + the captured packets arrive to the client workstation. Moreover, + it could be harmful in case of network congestion. + This flag is meaningless if the source is not a remote interface. + In that case, it is simply ignored. +*/ +#define PCAP_OPENFLAG_DATATX_UDP 2 + + +/*! + \brief Defines if the remote probe will capture its own generated traffic. + + In case the remote probe uses the same interface to capture traffic and to send + data back to the caller, the captured traffic includes the RPCAP traffic as well. + If this flag is turned on, the RPCAP traffic is excluded from the capture, so that + the trace returned back to the collector is does not include this traffic. +*/ +#define PCAP_OPENFLAG_NOCAPTURE_RPCAP 4 + +/*! + \brief Defines if the local adapter will capture its own generated traffic. + + This flag tells the underlying capture driver to drop the packets that were sent by itself. + This is usefult when building applications like bridges, that should ignore the traffic + they just sent. +*/ +#define PCAP_OPENFLAG_NOCAPTURE_LOCAL 8 + +/*! + \brief This flag configures the adapter for maximum responsiveness. + + In presence of a large value for nbytes, WinPcap waits for the arrival of several packets before + copying the data to the user. This guarantees a low number of system calls, i.e. lower processor usage, + i.e. better performance, which is good for applications like sniffers. If the user sets the + PCAP_OPENFLAG_MAX_RESPONSIVENESS flag, the capture driver will copy the packets as soon as the application + is ready to receive them. This is suggested for real time applications (like, for example, a bridge) + that need the best responsiveness.*/ +#define PCAP_OPENFLAG_MAX_RESPONSIVENESS 16 + +/*! + \} +*/ + + +/*! + \addtogroup remote_samp_methods + \{ +*/ + +/*! + \brief No sampling has to be done on the current capture. + + In this case, no sampling algorithms are applied to the current capture. +*/ +#define PCAP_SAMP_NOSAMP 0 + +/*! + \brief It defines that only 1 out of N packets must be returned to the user. + + In this case, the 'value' field of the 'pcap_samp' structure indicates the + number of packets (minus 1) that must be discarded before one packet got accepted. + In other words, if 'value = 10', the first packet is returned to the caller, while + the following 9 are discarded. +*/ +#define PCAP_SAMP_1_EVERY_N 1 + +/*! + \brief It defines that we have to return 1 packet every N milliseconds. + + In this case, the 'value' field of the 'pcap_samp' structure indicates the 'waiting + time' in milliseconds before one packet got accepted. + In other words, if 'value = 10', the first packet is returned to the caller; the next + returned one will be the first packet that arrives when 10ms have elapsed. +*/ +#define PCAP_SAMP_FIRST_AFTER_N_MS 2 + +/*! + \} +*/ + + +/*! + \addtogroup remote_auth_methods + \{ +*/ + +/*! + \brief It defines the NULL authentication. + + This value has to be used within the 'type' member of the pcap_rmtauth structure. + The 'NULL' authentication has to be equal to 'zero', so that old applications + can just put every field of struct pcap_rmtauth to zero, and it does work. +*/ +#define RPCAP_RMTAUTH_NULL 0 +/*! + \brief It defines the username/password authentication. + + With this type of authentication, the RPCAP protocol will use the username/ + password provided to authenticate the user on the remote machine. If the + authentication is successful (and the user has the right to open network devices) + the RPCAP connection will continue; otherwise it will be dropped. + + This value has to be used within the 'type' member of the pcap_rmtauth structure. +*/ +#define RPCAP_RMTAUTH_PWD 1 + +/*! + \} +*/ + + + + +/*! + + \brief This structure keeps the information needed to autheticate + the user on a remote machine. + + The remote machine can either grant or refuse the access according + to the information provided. + In case the NULL authentication is required, both 'username' and + 'password' can be NULL pointers. + + This structure is meaningless if the source is not a remote interface; + in that case, the functions which requires such a structure can accept + a NULL pointer as well. +*/ +struct pcap_rmtauth +{ + /*! + \brief Type of the authentication required. + + In order to provide maximum flexibility, we can support different types + of authentication based on the value of this 'type' variable. The currently + supported authentication methods are defined into the + \link remote_auth_methods Remote Authentication Methods Section\endlink. + + */ + int type; + /*! + \brief Zero-terminated string containing the username that has to be + used on the remote machine for authentication. + + This field is meaningless in case of the RPCAP_RMTAUTH_NULL authentication + and it can be NULL. + */ + char *username; + /*! + \brief Zero-terminated string containing the password that has to be + used on the remote machine for authentication. + + This field is meaningless in case of the RPCAP_RMTAUTH_NULL authentication + and it can be NULL. + */ + char *password; +}; + + +/*! + \brief This structure defines the information related to sampling. + + In case the sampling is requested, the capturing device should read + only a subset of the packets coming from the source. The returned packets depend + on the sampling parameters. + + \warning The sampling process is applied after the filtering process. + In other words, packets are filtered first, then the sampling process selects a + subset of the 'filtered' packets and it returns them to the caller. +*/ +struct pcap_samp +{ + /*! + Method used for sampling. Currently, the supported methods are listed in the + \link remote_samp_methods Sampling Methods Section\endlink. + */ + int method; + + /*! + This value depends on the sampling method defined. For its meaning, please check + at the \link remote_samp_methods Sampling Methods Section\endlink. + */ + int value; +}; + + + + +//! Maximum lenght of an host name (needed for the RPCAP active mode) +#define RPCAP_HOSTLIST_SIZE 1024 + + +/*! + \} +*/ // end of public documentation + + +// Exported functions + + + +/** \name New WinPcap functions + + This section lists the new functions that are able to help considerably in writing + WinPcap programs because of their easiness of use. + */ +//\{ +pcap_t *pcap_open(const char *source, int snaplen, int flags, int read_timeout, struct pcap_rmtauth *auth, char *errbuf); +int pcap_createsrcstr(char *source, int type, const char *host, const char *port, const char *name, char *errbuf); +int pcap_parsesrcstr(const char *source, int *type, char *host, char *port, char *name, char *errbuf); +int pcap_findalldevs_ex(char *source, struct pcap_rmtauth *auth, pcap_if_t **alldevs, char *errbuf); +struct pcap_samp *pcap_setsampling(pcap_t *p); + +//\} +// End of new winpcap functions + + + +/** \name Remote Capture functions + */ +//\{ +SOCKET pcap_remoteact_accept(const char *address, const char *port, const char *hostlist, char *connectinghost, struct pcap_rmtauth *auth, char *errbuf); +int pcap_remoteact_list(char *hostlist, char sep, int size, char *errbuf); +int pcap_remoteact_close(const char *host, char *errbuf); +void pcap_remoteact_cleanup(); +//\} +// End of remote capture functions + +#ifdef __cplusplus +} +#endif + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/wpcap.lib b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/wpcap.lib new file mode 100644 index 0000000..f832e04 Binary files /dev/null and b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/WinPCap/wpcap.lib differ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/demo_logging.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/demo_logging.c new file mode 100644 index 0000000..d6a1d25 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/demo_logging.c @@ -0,0 +1,526 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * Logging utility that allows FreeRTOS tasks to log to a UDP port, stdout, and + * disk file without making any Win32 system calls themselves. + * + * Messages logged to a UDP port are sent directly (using FreeRTOS+TCP), but as + * FreeRTOS tasks cannot make Win32 system calls messages sent to stdout or a + * disk file are sent via a stream buffer to a Win32 thread which then performs + * the actual output. + */ + +/* Standard includes. */ +#include +#include +#include +#include +#include + +/* FreeRTOS includes. */ +#include +#include "task.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_Stream_Buffer.h" + +/* Demo includes. */ +#include "demo_logging.h" + +/*-----------------------------------------------------------*/ + +/* The maximum size to which the log file may grow, before being renamed +to .ful. */ +#define dlLOGGING_FILE_SIZE ( 40ul * 1024ul * 1024ul ) + +/* Dimensions the arrays into which print messages are created. */ +#define dlMAX_PRINT_STRING_LENGTH 255 + +/* The size of the stream buffer used to pass messages from FreeRTOS tasks to +the Win32 thread that is responsible for making any Win32 system calls that are +necessary for the selected logging method. */ +#define dlLOGGING_STREAM_BUFFER_SIZE 32768 + +/* A block time of zero simply means don't block. */ +#define dlDONT_BLOCK 0 + +/*-----------------------------------------------------------*/ + +/* + * Called from vLoggingInit() to start a new disk log file. + */ +static void prvFileLoggingInit( void ); + +/* + * Attempt to write a message to the file. + */ +static void prvLogToFile( const char *pcMessage, size_t xLength ); + +/* + * Simply close the logging file, if it is open. + */ +static void prvFileClose( void ); + +/* + * Before the scheduler is started this function is called directly. After the + * scheduler has started it is called from the Windows thread dedicated to + * outputting log messages. Only the windows thread actually performs the + * writing so as not to disrupt the simulation by making Windows system calls + * from FreeRTOS tasks. + */ +static void prvLoggingFlushBuffer( void ); + +/* + * The windows thread that performs the actual writing of messages that require + * Win32 system calls. Only the windows thread can make system calls so as not + * to disrupt the simulation by making Windows calls from FreeRTOS tasks. + */ +static DWORD WINAPI prvWin32LoggingThread( void *pvParam ); + +/* + * Creates the socket to which UDP messages are sent. This function is not + * called directly to prevent the print socket being created from within the IP + * task - which could result in a deadlock. Instead the function call is + * deferred to run in the RTOS daemon task - hence it prototype. + */ +static void prvCreatePrintSocket( void *pvParameter1, uint32_t ulParameter2 ); + +/*-----------------------------------------------------------*/ + +/* Windows event used to wake the Win32 thread which performs any logging that +needs Win32 system calls. */ +static void *pvLoggingThreadEvent = NULL; + +/* Stores the selected logging targets passed in as parameters to the +vLoggingInit() function. */ +BaseType_t xStdoutLoggingUsed = pdFALSE, xDiskFileLoggingUsed = pdFALSE, xUDPLoggingUsed = pdFALSE; + +/* Circular buffer used to pass messages from the FreeRTOS tasks to the Win32 +thread that is responsible for making Win32 calls (when stdout or a disk log is +used). */ +static StreamBuffer_t *xLogStreamBuffer = NULL; + +/* Handle to the file used for logging. This is left open while there are +messages waiting to be logged, then closed again in between logs. */ +static FILE *pxLoggingFileHandle = NULL; + +/* When true prints are performed directly. After start up xDirectPrint is set +to pdFALSE - at which time prints that require Win32 system calls are done by +the Win32 thread responsible for logging. */ +BaseType_t xDirectPrint = pdTRUE; + +/* File names for the in use and complete (full) log files. */ +static const char *pcLogFileName = "RTOSDemo.log"; +static const char *pcFullLogFileName = "RTOSDemo.ful"; + +/* Keep the current file size in a variable, as an optimisation. */ +static size_t ulSizeOfLoggingFile = 0ul; + +/* The UDP socket and address on/to which print messages are sent. */ +Socket_t xPrintSocket = FREERTOS_INVALID_SOCKET; +struct freertos_sockaddr xPrintUDPAddress; + +/*-----------------------------------------------------------*/ + +void vLoggingInit( BaseType_t xLogToStdout, BaseType_t xLogToFile, BaseType_t xLogToUDP, uint32_t ulRemoteIPAddress, uint16_t usRemotePort ) +{ + /* Can only be called before the scheduler has started. */ + configASSERT( xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED ); + + #if( ( ipconfigHAS_DEBUG_PRINTF == 1 ) || ( ipconfigHAS_PRINTF == 1 ) ) + { + HANDLE Win32Thread; + + /* Record which output methods are to be used. */ + xStdoutLoggingUsed = xLogToStdout; + xDiskFileLoggingUsed = xLogToFile; + xUDPLoggingUsed = xLogToUDP; + + /* If a disk file is used then initialise it now. */ + if( xDiskFileLoggingUsed != pdFALSE ) + { + prvFileLoggingInit(); + } + + /* If UDP logging is used then store the address to which the log data + will be sent - but don't create the socket yet because the network is + not initialised. */ + if( xUDPLoggingUsed != pdFALSE ) + { + /* Set the address to which the print messages are sent. */ + xPrintUDPAddress.sin_port = FreeRTOS_htons( usRemotePort ); + xPrintUDPAddress.sin_addr = ulRemoteIPAddress; + } + + /* If a disk file or stdout are to be used then Win32 system calls will + have to be made. Such system calls cannot be made from FreeRTOS tasks + so create a stream buffer to pass the messages to a Win32 thread, then + create the thread itself, along with a Win32 event that can be used to + unblock the thread. */ + if( ( xStdoutLoggingUsed != pdFALSE ) || ( xDiskFileLoggingUsed != pdFALSE ) ) + { + /* Create the buffer. */ + xLogStreamBuffer = ( StreamBuffer_t * ) malloc( sizeof( *xLogStreamBuffer ) - sizeof( xLogStreamBuffer->ucArray ) + dlLOGGING_STREAM_BUFFER_SIZE + 1 ); + configASSERT( xLogStreamBuffer ); + memset( xLogStreamBuffer, '\0', sizeof( *xLogStreamBuffer ) - sizeof( xLogStreamBuffer->ucArray ) ); + xLogStreamBuffer->LENGTH = dlLOGGING_STREAM_BUFFER_SIZE + 1; + + /* Create the Windows event. */ + pvLoggingThreadEvent = CreateEvent( NULL, FALSE, TRUE, "StdoutLoggingEvent" ); + + /* Create the thread itself. */ + Win32Thread = CreateThread( + NULL, /* Pointer to thread security attributes. */ + 0, /* Initial thread stack size, in bytes. */ + prvWin32LoggingThread, /* Pointer to thread function. */ + NULL, /* Argument for new thread. */ + 0, /* Creation flags. */ + NULL ); + + /* Use the cores that are not used by the FreeRTOS tasks. */ + SetThreadAffinityMask( Win32Thread, ~0x01u ); + SetThreadPriorityBoost( Win32Thread, TRUE ); + SetThreadPriority( Win32Thread, THREAD_PRIORITY_IDLE ); + } + } + #else + { + /* FreeRTOSIPConfig is set such that no print messages will be output. + Avoid compiler warnings about unused parameters. */ + ( void ) xLogToStdout; + ( void ) xLogToFile; + ( void ) xLogToUDP; + ( void ) usRemotePort; + ( void ) ulRemoteIPAddress; + } + #endif /* ( ipconfigHAS_DEBUG_PRINTF == 1 ) || ( ipconfigHAS_PRINTF == 1 ) */ +} +/*-----------------------------------------------------------*/ + +static void prvCreatePrintSocket( void *pvParameter1, uint32_t ulParameter2 ) +{ +static const TickType_t xSendTimeOut = pdMS_TO_TICKS( 0 ); +Socket_t xSocket; + + /* The function prototype is that of a deferred function, but the parameters + are not actually used. */ + ( void ) pvParameter1; + ( void ) ulParameter2; + + xSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP ); + + if( xSocket != FREERTOS_INVALID_SOCKET ) + { + /* FreeRTOS+TCP decides which port to bind to. */ + FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_SNDTIMEO, &xSendTimeOut, sizeof( xSendTimeOut ) ); + FreeRTOS_bind( xSocket, NULL, 0 ); + + /* Now the socket is bound it can be assigned to the print socket. */ + xPrintSocket = xSocket; + } +} +/*-----------------------------------------------------------*/ + +void vLoggingPrintf( const char *pcFormat, ... ) +{ +char cPrintString[ dlMAX_PRINT_STRING_LENGTH ]; +char cOutputString[ dlMAX_PRINT_STRING_LENGTH ]; +char *pcSource, *pcTarget, *pcBegin; +size_t xLength, xLength2, rc; +static BaseType_t xMessageNumber = 0; +va_list args; +uint32_t ulIPAddress; +const char *pcTaskName; +const char *pcNoTask = "None"; +int iOriginalPriority; +HANDLE xCurrentTask; + + + if( ( xStdoutLoggingUsed != pdFALSE ) || ( xDiskFileLoggingUsed != pdFALSE ) || ( xUDPLoggingUsed != pdFALSE ) ) + { + /* There are a variable number of parameters. */ + va_start( args, pcFormat ); + + /* Additional info to place at the start of the log. */ + if( xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED ) + { + pcTaskName = pcTaskGetName( NULL ); + } + else + { + pcTaskName = pcNoTask; + } + + if( strcmp( pcFormat, "\n" ) != 0 ) + { + xLength = snprintf( cPrintString, dlMAX_PRINT_STRING_LENGTH, "%lu %lu [%s] ", + xMessageNumber++, + ( unsigned long ) xTaskGetTickCount(), + pcTaskName ); + } + else + { + xLength = 0; + memset( cPrintString, 0x00, dlMAX_PRINT_STRING_LENGTH ); + } + + xLength2 = vsnprintf( cPrintString + xLength, dlMAX_PRINT_STRING_LENGTH - xLength, pcFormat, args ); + + if( xLength2 < 0 ) + { + /* Clean up. */ + xLength2 = dlMAX_PRINT_STRING_LENGTH - 1 - xLength; + cPrintString[ dlMAX_PRINT_STRING_LENGTH - 1 ] = '\0'; + } + + xLength += xLength2; + va_end( args ); + + /* For ease of viewing, copy the string into another buffer, converting + IP addresses to dot notation on the way. */ + pcSource = cPrintString; + pcTarget = cOutputString; + + while( ( *pcSource ) != '\0' ) + { + *pcTarget = *pcSource; + pcTarget++; + pcSource++; + + /* Look forward for an IP address denoted by 'ip'. */ + if( ( isxdigit( pcSource[ 0 ] ) != pdFALSE ) && ( pcSource[ 1 ] == 'i' ) && ( pcSource[ 2 ] == 'p' ) ) + { + *pcTarget = *pcSource; + pcTarget++; + *pcTarget = '\0'; + pcBegin = pcTarget - 8; + + while( ( pcTarget > pcBegin ) && ( isxdigit( pcTarget[ -1 ] ) != pdFALSE ) ) + { + pcTarget--; + } + + sscanf( pcTarget, "%8X", &ulIPAddress ); + rc = sprintf( pcTarget, "%lu.%lu.%lu.%lu", + ( unsigned long ) ( ulIPAddress >> 24UL ), + ( unsigned long ) ( (ulIPAddress >> 16UL) & 0xffUL ), + ( unsigned long ) ( (ulIPAddress >> 8UL) & 0xffUL ), + ( unsigned long ) ( ulIPAddress & 0xffUL ) ); + pcTarget += rc; + pcSource += 3; /* skip "ip" */ + } + } + + /* How far through the buffer was written? */ + xLength = ( BaseType_t ) ( pcTarget - cOutputString ); + + /* If the message is to be logged to a UDP port then it can be sent directly + because it only uses FreeRTOS function (not Win32 functions). */ + if( xUDPLoggingUsed != pdFALSE ) + { + if( ( xPrintSocket == FREERTOS_INVALID_SOCKET ) && ( FreeRTOS_IsNetworkUp() != pdFALSE ) ) + { + /* Create and bind the socket to which print messages are sent. The + xTimerPendFunctionCall() function is used even though this is + not an interrupt because this function is called from the IP task + and the IP task cannot itself wait for a socket to bind. The + parameters to prvCreatePrintSocket() are not required so set to + NULL or 0. */ + xTimerPendFunctionCall( prvCreatePrintSocket, NULL, 0, dlDONT_BLOCK ); + } + + if( xPrintSocket != FREERTOS_INVALID_SOCKET ) + { + FreeRTOS_sendto( xPrintSocket, cOutputString, xLength, 0, &xPrintUDPAddress, sizeof( xPrintUDPAddress ) ); + + /* Just because the UDP data logger I'm using is dumb. */ + FreeRTOS_sendto( xPrintSocket, "\r", sizeof( char ), 0, &xPrintUDPAddress, sizeof( xPrintUDPAddress ) ); + } + } + + /* If logging is also to go to either stdout or a disk file then it cannot + be output here - so instead write the message to the stream buffer and wake + the Win32 thread which will read it from the stream buffer and perform the + actual output. */ + if( ( xStdoutLoggingUsed != pdFALSE ) || ( xDiskFileLoggingUsed != pdFALSE ) ) + { + configASSERT( xLogStreamBuffer ); + + /* How much space is in the buffer? */ + xLength2 = uxStreamBufferGetSpace( xLogStreamBuffer ); + + /* There must be enough space to write both the string and the length of + the string. */ + if( xLength2 >= ( xLength + sizeof( xLength ) ) ) + { + /* First write in the length of the data, then write in the data + itself. Raising the thread priority is used as a critical section + as there are potentially multiple writers. The stream buffer is + only thread safe when there is a single writer (likewise for + reading from the buffer). */ + xCurrentTask = GetCurrentThread(); + iOriginalPriority = GetThreadPriority( xCurrentTask ); + SetThreadPriority( GetCurrentThread(), THREAD_PRIORITY_TIME_CRITICAL ); + uxStreamBufferAdd( xLogStreamBuffer, 0, ( const uint8_t * ) &( xLength ), sizeof( xLength ) ); + uxStreamBufferAdd( xLogStreamBuffer, 0, ( const uint8_t * ) cOutputString, xLength ); + SetThreadPriority( GetCurrentThread(), iOriginalPriority ); + } + + /* xDirectPrint is initialised to pdTRUE, and while it remains true the + logging output function is called directly. When the system is running + the output function cannot be called directly because it would get + called from both FreeRTOS tasks and Win32 threads - so instead wake the + Win32 thread responsible for the actual output. */ + if( xDirectPrint != pdFALSE ) + { + /* While starting up, the thread which calls prvWin32LoggingThread() + is not running yet and xDirectPrint will be pdTRUE. */ + prvLoggingFlushBuffer(); + } + else if( pvLoggingThreadEvent != NULL ) + { + /* While running, wake up prvWin32LoggingThread() to send the + logging data. */ + SetEvent( pvLoggingThreadEvent ); + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvLoggingFlushBuffer( void ) +{ +size_t xLength; +char cPrintString[ dlMAX_PRINT_STRING_LENGTH ]; + + /* Is there more than the length value stored in the circular buffer + used to pass data from the FreeRTOS simulator into this Win32 thread? */ + while( uxStreamBufferGetSize( xLogStreamBuffer ) > sizeof( xLength ) ) + { + memset( cPrintString, 0x00, dlMAX_PRINT_STRING_LENGTH ); + uxStreamBufferGet( xLogStreamBuffer, 0, ( uint8_t * ) &xLength, sizeof( xLength ), pdFALSE ); + uxStreamBufferGet( xLogStreamBuffer, 0, ( uint8_t * ) cPrintString, xLength, pdFALSE ); + + /* Write the message to standard out if requested to do so when + vLoggingInit() was called, or if the network is not yet up. */ + if( ( xStdoutLoggingUsed != pdFALSE ) || ( FreeRTOS_IsNetworkUp() == pdFALSE ) ) + { + /* Write the message to stdout. */ + printf( "%s", cPrintString ); /*_RB_ Replace with _write(). */ + } + + /* Write the message to a file if requested to do so when + vLoggingInit() was called. */ + if( xDiskFileLoggingUsed != pdFALSE ) + { + prvLogToFile( cPrintString, xLength ); + } + } + + prvFileClose(); +} +/*-----------------------------------------------------------*/ + +static DWORD WINAPI prvWin32LoggingThread( void *pvParameter ) +{ +const DWORD xMaxWait = 1000; + + ( void ) pvParameter; + + /* From now on, prvLoggingFlushBuffer() will only be called from this + Windows thread */ + xDirectPrint = pdFALSE; + + for( ;; ) + { + /* Wait to be told there are message waiting to be logged. */ + WaitForSingleObject( pvLoggingThreadEvent, xMaxWait ); + + /* Write out all waiting messages. */ + prvLoggingFlushBuffer(); + } +} +/*-----------------------------------------------------------*/ + +static void prvFileLoggingInit( void ) +{ +FILE *pxHandle = fopen( pcLogFileName, "a" ); + + if( pxHandle != NULL ) + { + fseek( pxHandle, SEEK_END, 0ul ); + ulSizeOfLoggingFile = ftell( pxHandle ); + fclose( pxHandle ); + } + else + { + ulSizeOfLoggingFile = 0ul; + } +} +/*-----------------------------------------------------------*/ + +static void prvFileClose( void ) +{ + if( pxLoggingFileHandle != NULL ) + { + fclose( pxLoggingFileHandle ); + pxLoggingFileHandle = NULL; + } +} +/*-----------------------------------------------------------*/ + +static void prvLogToFile( const char *pcMessage, size_t xLength ) +{ + if( pxLoggingFileHandle == NULL ) + { + pxLoggingFileHandle = fopen( pcLogFileName, "a" ); + } + + if( pxLoggingFileHandle != NULL ) + { + fwrite( pcMessage, 1, xLength, pxLoggingFileHandle ); + ulSizeOfLoggingFile += xLength; + + /* If the file has grown to its maximum permissible size then close and + rename it - then start with a new file. */ + if( ulSizeOfLoggingFile > ( size_t ) dlLOGGING_FILE_SIZE ) + { + prvFileClose(); + if( _access( pcFullLogFileName, 00 ) == 0 ) + { + remove( pcFullLogFileName ); + } + rename( pcLogFileName, pcFullLogFileName ); + ulSizeOfLoggingFile = 0; + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/demo_logging.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/demo_logging.h new file mode 100644 index 0000000..62ae46a --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/demo_logging.h @@ -0,0 +1,48 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef DEMO_LOGGING_H +#define DEMO_LOGGING_H + +/* + * Initialise a logging system that can be used from FreeRTOS tasks and Win32 + * threads. Do not call printf() directly while the scheduler is running. + * + * Set xLogToStdout, xLogToFile and xLogToUDP to either pdTRUE or pdFALSE to + * lot to stdout, a disk file and a UDP port respectively. + * + * If xLogToUDP is pdTRUE then ulRemoteIPAddress and usRemotePort must be set + * to the IP address and port number to which UDP log messages will be sent. + */ +void vLoggingInit( BaseType_t xLogToStdout, + BaseType_t xLogToFile, + BaseType_t xLogToUDP, + uint32_t ulRemoteIPAddress, + uint16_t usRemotePort ); + +#endif /* DEMO_LOGGING_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/main.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/main.c new file mode 100644 index 0000000..f5ae5eb --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/main.c @@ -0,0 +1,373 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * This project is a cut down version of the project described on the following + * link. Only the simple UDP client and server and the TCP echo clients are + * included in the build: + * http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/examples_FreeRTOS_simulator.html + */ + +/* Standard includes. */ +#include +#include + +/* FreeRTOS includes. */ +#include +#include "task.h" + +/* Demo application includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "SimpleUDPClientAndServer.h" +#include "SimpleTCPEchoServer.h" +#include "TCPEchoClient_SingleTasks.h" +#include "demo_logging.h" + +/* Simple UDP client and server task parameters. */ +#define mainSIMPLE_UDP_CLIENT_SERVER_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainSIMPLE_UDP_CLIENT_SERVER_PORT ( 5005UL ) + +/* Echo client task parameters - used for both TCP and UDP echo clients. */ +#define mainECHO_CLIENT_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 ) /* Not used in the Windows port. */ +#define mainECHO_CLIENT_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* Echo server task parameters. */ +#define mainECHO_SERVER_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 ) /* Not used in the Windows port. */ +#define mainECHO_SERVER_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* Define a name that will be used for LLMNR and NBNS searches. */ +#define mainHOST_NAME "RTOSDemo" +#define mainDEVICE_NICK_NAME "windows_demo" + +/* Set the following constants to 1 or 0 to define which tasks to include and +exclude: + +mainCREATE_SIMPLE_UDP_CLIENT_SERVER_TASKS: When set to 1 two UDP client tasks +and two UDP server tasks are created. The clients talk to the servers. One set +of tasks use the standard sockets interface, and the other the zero copy sockets +interface. These tasks are self checking and will trigger a configASSERT() if +they detect a difference in the data that is received from that which was sent. +As these tasks use UDP, and can therefore loose packets, they will cause +configASSERT() to be called when they are run in a less than perfect networking +environment. + +mainCREATE_TCP_ECHO_TASKS_SINGLE: When set to 1 a set of tasks are created that +send TCP echo requests to the standard echo port (port 7), then wait for and +verify the echo reply, from within the same task (Tx and Rx are performed in the +same RTOS task). The IP address of the echo server must be configured using the +configECHO_SERVER_ADDR0 to configECHO_SERVER_ADDR3 constants in +FreeRTOSConfig.h. + +mainCREATE_TCP_ECHO_SERVER_TASK: When set to 1 a task is created that accepts +connections on the standard echo port (port 7), then echos back any data +received on that connection. +*/ +#define mainCREATE_SIMPLE_UDP_CLIENT_SERVER_TASKS 1 +#define mainCREATE_TCP_ECHO_TASKS_SINGLE 1 +#define mainCREATE_TCP_ECHO_SERVER_TASK 0 +/*-----------------------------------------------------------*/ + +/* + * Just seeds the simple pseudo random number generator. + */ +static void prvSRand( UBaseType_t ulSeed ); + +/* + * Miscellaneous initialisation including preparing the logging and seeding the + * random number generator. + */ +static void prvMiscInitialisation( void ); + +/* The default IP and MAC address used by the demo. The address configuration +defined here will be used if ipconfigUSE_DHCP is 0, or if ipconfigUSE_DHCP is +1 but a DHCP server could not be contacted. See the online documentation for +more information. */ +static const uint8_t ucIPAddress[ 4 ] = { configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 }; +static const uint8_t ucNetMask[ 4 ] = { configNET_MASK0, configNET_MASK1, configNET_MASK2, configNET_MASK3 }; +static const uint8_t ucGatewayAddress[ 4 ] = { configGATEWAY_ADDR0, configGATEWAY_ADDR1, configGATEWAY_ADDR2, configGATEWAY_ADDR3 }; +static const uint8_t ucDNSServerAddress[ 4 ] = { configDNS_SERVER_ADDR0, configDNS_SERVER_ADDR1, configDNS_SERVER_ADDR2, configDNS_SERVER_ADDR3 }; + +/* Set the following constant to pdTRUE to log using the method indicated by the +name of the constant, or pdFALSE to not log using the method indicated by the +name of the constant. Options include to standard out (xLogToStdout), to a disk +file (xLogToFile), and to a UDP port (xLogToUDP). If xLogToUDP is set to pdTRUE +then UDP messages are sent to the IP address configured as the echo server +address (see the configECHO_SERVER_ADDR0 definitions in FreeRTOSConfig.h) and +the port number set by configPRINT_PORT in FreeRTOSConfig.h. */ +const BaseType_t xLogToStdout = pdTRUE, xLogToFile = pdFALSE, xLogToUDP = pdFALSE; + +/* Default MAC address configuration. The demo creates a virtual network +connection that uses this MAC address by accessing the raw Ethernet data +to and from a real network connection on the host PC. See the +configNETWORK_INTERFACE_TO_USE definition for information on how to configure +the real network connection to use. */ +const uint8_t ucMACAddress[ 6 ] = { configMAC_ADDR0, configMAC_ADDR1, configMAC_ADDR2, configMAC_ADDR3, configMAC_ADDR4, configMAC_ADDR5 }; + +/* Use by the pseudo random number generator. */ +static UBaseType_t ulNextRand; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ +const uint32_t ulLongTime_ms = pdMS_TO_TICKS( 1000UL ); + + /* + * Instructions for using this project are provided on: + * http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/examples_FreeRTOS_simulator.html + */ + + /* Miscellaneous initialisation including preparing the logging and seeding + the random number generator. */ + prvMiscInitialisation(); + + /* Initialise the network interface. + + ***NOTE*** Tasks that use the network are created in the network event hook + when the network is connected and ready for use (see the definition of + vApplicationIPNetworkEventHook() below). The address values passed in here + are used if ipconfigUSE_DHCP is set to 0, or if ipconfigUSE_DHCP is set to 1 + but a DHCP server cannot be contacted. */ + FreeRTOS_debug_printf( ( "FreeRTOS_IPInit\n" ) ); + FreeRTOS_IPInit( ucIPAddress, ucNetMask, ucGatewayAddress, ucDNSServerAddress, ucMACAddress ); + + /* Start the RTOS scheduler. */ + FreeRTOS_debug_printf( ("vTaskStartScheduler\n") ); + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was insufficient FreeRTOS heap memory available for the idle and/or + timer tasks to be created. See the memory management section on the + FreeRTOS web site for more details (this is standard text that is not not + really applicable to the Win32 simulator port). */ + for( ;; ) + { + Sleep( ulLongTime_ms ); + } +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +const uint32_t ulMSToSleep = 1; + + /* This is just a trivial example of an idle hook. It is called on each + cycle of the idle task if configUSE_IDLE_HOOK is set to 1 in + FreeRTOSConfig.h. It must *NOT* attempt to block. In this case the + idle task just sleeps to lower the CPU usage. */ + Sleep( ulMSToSleep ); +} +/*-----------------------------------------------------------*/ + +void vAssertCalled( const char *pcFile, uint32_t ulLine ) +{ +const uint32_t ulLongSleep = 1000UL; +volatile uint32_t ulBlockVariable = 0UL; +volatile char *pcFileName = ( volatile char * ) pcFile; +volatile uint32_t ulLineNumber = ulLine; + + ( void ) pcFileName; + ( void ) ulLineNumber; + + FreeRTOS_debug_printf( ( "vAssertCalled( %s, %ld\n", pcFile, ulLine ) ); + + /* Setting ulBlockVariable to a non-zero value in the debugger will allow + this function to be exited. */ + taskDISABLE_INTERRUPTS(); + { + while( ulBlockVariable == 0UL ) + { + Sleep( ulLongSleep ); + } + } + taskENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +/* Called by FreeRTOS+TCP when the network connects or disconnects. Disconnect +events are only received if implemented in the MAC driver. */ +void vApplicationIPNetworkEventHook( eIPCallbackEvent_t eNetworkEvent ) +{ +uint32_t ulIPAddress, ulNetMask, ulGatewayAddress, ulDNSServerAddress; +char cBuffer[ 16 ]; +static BaseType_t xTasksAlreadyCreated = pdFALSE; + + /* If the network has just come up...*/ + if( eNetworkEvent == eNetworkUp ) + { + /* Create the tasks that use the IP stack if they have not already been + created. */ + if( xTasksAlreadyCreated == pdFALSE ) + { + /* See the comments above the definitions of these pre-processor + macros at the top of this file for a description of the individual + demo tasks. */ + #if( mainCREATE_SIMPLE_UDP_CLIENT_SERVER_TASKS == 1 ) + { + vStartSimpleUDPClientServerTasks( configMINIMAL_STACK_SIZE, mainSIMPLE_UDP_CLIENT_SERVER_PORT, mainSIMPLE_UDP_CLIENT_SERVER_TASK_PRIORITY ); + } + #endif /* mainCREATE_SIMPLE_UDP_CLIENT_SERVER_TASKS */ + + #if( mainCREATE_TCP_ECHO_TASKS_SINGLE == 1 ) + { + vStartTCPEchoClientTasks_SingleTasks( mainECHO_CLIENT_TASK_STACK_SIZE, mainECHO_CLIENT_TASK_PRIORITY ); + } + #endif /* mainCREATE_TCP_ECHO_TASKS_SINGLE */ + + #if( mainCREATE_TCP_ECHO_SERVER_TASK == 1 ) + { + vStartSimpleTCPServerTasks( mainECHO_SERVER_TASK_STACK_SIZE, mainECHO_SERVER_TASK_PRIORITY ); + } + #endif + + xTasksAlreadyCreated = pdTRUE; + } + + /* Print out the network configuration, which may have come from a DHCP + server. */ + FreeRTOS_GetAddressConfiguration( &ulIPAddress, &ulNetMask, &ulGatewayAddress, &ulDNSServerAddress ); + FreeRTOS_inet_ntoa( ulIPAddress, cBuffer ); + FreeRTOS_printf( ( "\r\n\r\nIP Address: %s\r\n", cBuffer ) ); + + FreeRTOS_inet_ntoa( ulNetMask, cBuffer ); + FreeRTOS_printf( ( "Subnet Mask: %s\r\n", cBuffer ) ); + + FreeRTOS_inet_ntoa( ulGatewayAddress, cBuffer ); + FreeRTOS_printf( ( "Gateway Address: %s\r\n", cBuffer ) ); + + FreeRTOS_inet_ntoa( ulDNSServerAddress, cBuffer ); + FreeRTOS_printf( ( "DNS Server Address: %s\r\n\r\n\r\n", cBuffer ) ); + } +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + vAssertCalled( __FILE__, __LINE__ ); +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxRand( void ) +{ +const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL; + + /* Utility function to generate a pseudo random number. */ + + ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement; + return( ( int ) ( ulNextRand >> 16UL ) & 0x7fffUL ); +} +/*-----------------------------------------------------------*/ + +static void prvSRand( UBaseType_t ulSeed ) +{ + /* Utility function to seed the pseudo random number generator. */ + ulNextRand = ulSeed; +} +/*-----------------------------------------------------------*/ + +static void prvMiscInitialisation( void ) +{ +time_t xTimeNow; +uint32_t ulLoggingIPAddress; + + ulLoggingIPAddress = FreeRTOS_inet_addr_quick( configECHO_SERVER_ADDR0, configECHO_SERVER_ADDR1, configECHO_SERVER_ADDR2, configECHO_SERVER_ADDR3 ); + vLoggingInit( xLogToStdout, xLogToFile, xLogToUDP, ulLoggingIPAddress, configPRINT_PORT ); + + /* Seed the random number generator. */ + time( &xTimeNow ); + FreeRTOS_debug_printf( ( "Seed for randomiser: %lu\n", xTimeNow ) ); + prvSRand( ( uint32_t ) xTimeNow ); + FreeRTOS_debug_printf( ( "Random numbers: %08X %08X %08X %08X\n", ipconfigRAND32(), ipconfigRAND32(), ipconfigRAND32(), ipconfigRAND32() ) ); +} +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_LLMNR != 0 ) || ( ipconfigUSE_NBNS != 0 ) || ( ipconfigDHCP_REGISTER_HOSTNAME == 1 ) + + const char *pcApplicationHostnameHook( void ) + { + /* Assign the name "FreeRTOS" to this network node. This function will + be called during the DHCP: the machine will be registered with an IP + address plus this name. */ + return mainHOST_NAME; + } + +#endif +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_LLMNR != 0 ) || ( ipconfigUSE_NBNS != 0 ) + + BaseType_t xApplicationDNSQueryHook( const char *pcName ) + { + BaseType_t xReturn; + + /* Determine if a name lookup is for this node. Two names are given + to this node: that returned by pcApplicationHostnameHook() and that set + by mainDEVICE_NICK_NAME. */ + if( _stricmp( pcName, pcApplicationHostnameHook() ) == 0 ) + { + xReturn = pdPASS; + } + else if( _stricmp( pcName, mainDEVICE_NICK_NAME ) == 0 ) + { + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + + return xReturn; + } + +#endif + +/* + * Callback that provides the inputs necessary to generate a randomized TCP + * Initial Sequence Number per RFC 6528. THIS IS ONLY A DUMMY IMPLEMENTATION + * THAT RETURNS A PSEUDO RANDOM NUMBER SO IS NOT INTENDED FOR USE IN PRODUCTION + * SYSTEMS. + */ +extern uint32_t ulApplicationGetNextSequenceNumber( uint32_t ulSourceAddress, + uint16_t usSourcePort, + uint32_t ulDestinationAddress, + uint16_t usDestinationPort ) +{ + ( void ) ulSourceAddress; + ( void ) usSourcePort; + ( void ) ulDestinationAddress; + ( void ) usDestinationPort; + + return uxRand(); +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/printf-stdarg.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/printf-stdarg.c new file mode 100644 index 0000000..5505535 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/printf-stdarg.c @@ -0,0 +1,667 @@ +/* + Copyright 2001, 2002 Georges Menie (www.menie.org) + stdarg version contributed by Christian Ettinger + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + Changes for the FreeRTOS ports: + + - The dot in "%-8.8s" + - The specifiers 'l' (long) and 'L' (long long) + - The specifier 'u' for unsigned + - Dot notation for IP addresses: + sprintf("IP = %xip\n", 0xC0A80164); + will produce "IP = 192.168.1.100\n" +*/ + +#include +#include +#include +#include + +#include "FreeRTOS.h" + +#define PAD_RIGHT 1 +#define PAD_ZERO 2 + +/* + * Return 1 for readable, 2 for writeable, 3 for both. + * Function must be provided by the application. + */ +extern BaseType_t xApplicationMemoryPermissions( uint32_t aAddress ); + +extern void vOutputChar( const char cChar, const TickType_t xTicksToWait ); +static const TickType_t xTicksToWait = pdMS_TO_TICKS( 20 ); + +struct xPrintFlags +{ + int base; + int width; + int printLimit; + unsigned + pad : 8, + letBase : 8, + isSigned : 1, + isNumber : 1, + long32 : 1, + long64 : 1; +}; + +struct SStringBuf +{ + char *str; + const char *orgStr; + const char *nulPos; + int curLen; + struct xPrintFlags flags; +}; + +static void strbuf_init( struct SStringBuf *apStr, char *apBuf, const char *apMaxStr ) +{ + apStr->str = apBuf; + apStr->orgStr = apBuf; + apStr->nulPos = apMaxStr-1; + apStr->curLen = 0; + + memset( &apStr->flags, '\0', sizeof( apStr->flags ) ); +} +/*-----------------------------------------------------------*/ + +static BaseType_t strbuf_printchar( struct SStringBuf *apStr, int c ) +{ + if( apStr->str == NULL ) + { + vOutputChar( ( char ) c, xTicksToWait ); + apStr->curLen++; + return pdTRUE; + } + if( apStr->str < apStr->nulPos ) + { + *( apStr->str++ ) = c; + apStr->curLen++; + return pdTRUE; + } + if( apStr->str == apStr->nulPos ) + { + *( apStr->str++ ) = '\0'; + } + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static portINLINE BaseType_t strbuf_printchar_inline( struct SStringBuf *apStr, int c ) +{ + if( apStr->str == NULL ) + { + vOutputChar( ( char ) c, xTicksToWait ); + if( c == 0 ) + { + return pdFALSE; + } + apStr->curLen++; + return pdTRUE; + } + if( apStr->str < apStr->nulPos ) + { + *(apStr->str++) = c; + if( c == 0 ) + { + return pdFALSE; + } + apStr->curLen++; + return pdTRUE; + } + if( apStr->str == apStr->nulPos ) + { + *( apStr->str++ ) = '\0'; + } + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static portINLINE int i2hex( int aCh ) +{ +int iResult; + + if( aCh < 10 ) + { + iResult = '0' + aCh; + } + else + { + iResult = 'A' + aCh - 10; + } + + return iResult; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prints(struct SStringBuf *apBuf, const char *apString ) +{ + register int padchar = ' '; + int i,len; + + if( xApplicationMemoryPermissions( ( uint32_t )apString ) == 0 ) + { + /* The user has probably made a mistake with the parameter + for '%s', the memory is not readbale. */ + apString = "INV_MEM"; + } + + if( apBuf->flags.width > 0 ) + { + register int len = 0; + register const char *ptr; + for( ptr = apString; *ptr; ++ptr ) + { + ++len; + } + + if( len >= apBuf->flags.width ) + { + apBuf->flags.width = 0; + } + else + { + apBuf->flags.width -= len; + } + + if( apBuf->flags.pad & PAD_ZERO ) + { + padchar = '0'; + } + } + if( ( apBuf->flags.pad & PAD_RIGHT ) == 0 ) + { + for( ; apBuf->flags.width > 0; --apBuf->flags.width ) + { + if( strbuf_printchar( apBuf, padchar ) == 0 ) + { + return pdFALSE; + } + } + } + if( ( apBuf->flags.isNumber == pdTRUE ) && ( apBuf->flags.pad == pdTRUE ) ) + { + /* The string to print represents an integer number. + * In this case, printLimit is the min number of digits to print + * If the length of the number to print is less than the min nb of i + * digits to display, we add 0 before printing the number + */ + len = strlen( apString ); + + if( len < apBuf->flags.printLimit ) + { + i = apBuf->flags.printLimit - len; + for( ; i; i-- ) + { + if( strbuf_printchar( apBuf, '0' ) == 0 ) + { + return pdFALSE; + } + } + } + } + /* The string to print is not the result of a number conversion to ascii. + * For a string, printLimit is the max number of characters to display + */ + for( ; apBuf->flags.printLimit && *apString ; ++apString, --apBuf->flags.printLimit ) + { + if( !strbuf_printchar( apBuf, *apString ) ) + { + return pdFALSE; + } + } + + for( ; apBuf->flags.width > 0; --apBuf->flags.width ) + { + if( !strbuf_printchar( apBuf, padchar ) ) + { + return pdFALSE; + } + } + + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +/* the following should be enough for 32 bit int */ +#define PRINT_BUF_LEN 12 /* to print 4294967296 */ + +#if SPRINTF_LONG_LONG +#warning 64-bit libraries will be included as well +static BaseType_t printll( struct SStringBuf *apBuf, long long i ) +{ + char print_buf[ 2 * PRINT_BUF_LEN ]; + register char *s; + register int t, neg = 0; + register unsigned long long u = i; + lldiv_t lldiv_result; + +/* typedef struct + * { + * long long int quot; // quotient + * long long int rem; // remainder + * } lldiv_t; + */ + + apBuf->flags.isNumber = pdTRUE; /* Parameter for prints */ + if( i == 0LL ) + { + print_buf[ 0 ] = '0'; + print_buf[ 1 ] = '\0'; + return prints( apBuf, print_buf ); + } + + if( ( apBuf->flags.isSigned == pdTRUE ) && ( apBuf->flags.base == 10 ) && ( i < 0LL ) ) + { + neg = 1; + u = -i; + } + + s = print_buf + sizeof( print_buf ) - 1; + + *s = '\0'; + /* 18446744073709551616 */ + while( u != 0 ) + { + lldiv_result = lldiv( u, ( unsigned long long ) apBuf->flags.base ); + t = lldiv_result.rem; + if( t >= 10 ) + { + t += apBuf->flags.letBase - '0' - 10; + } + *( --s ) = t + '0'; + u = lldiv_result.quot; + } + + if( neg != 0 ) + { + if( ( apBuf->flags.width != 0 ) && ( apBuf->flags.pad & PAD_ZERO ) ) + { + if( !strbuf_printchar( apBuf, '-' ) ) + { + return pdFALSE; + } + --apBuf->flags.width; + } + else + { + *( --s ) = '-'; + } + } + + return prints( apBuf, s ); +} +#endif /* SPRINTF_LONG_LONG */ +/*-----------------------------------------------------------*/ + +static BaseType_t printi( struct SStringBuf *apBuf, int i ) +{ + char print_buf[ PRINT_BUF_LEN ]; + register char *s; + register int t, neg = 0; + register unsigned int u = i; + register unsigned base = apBuf->flags.base; + + apBuf->flags.isNumber = pdTRUE; /* Parameter for prints */ + + if( i == 0 ) + { + print_buf[ 0 ] = '0'; + print_buf[ 1 ] = '\0'; + return prints( apBuf, print_buf ); + } + + if( ( apBuf->flags.isSigned == pdTRUE ) && ( base == 10 ) && ( i < 0 ) ) + { + neg = 1; + u = -i; + } + + s = print_buf + sizeof( print_buf ) - 1; + + *s = '\0'; + switch( base ) + { + case 16: + while( u != 0 ) + { + t = u & 0xF; + if( t >= 10 ) + { + t += apBuf->flags.letBase - '0' - 10; + } + *( --s ) = t + '0'; + u >>= 4; + } + break; + + case 8: + case 10: + /* GCC compiles very efficient */ + while( u ) + { + t = u % base; + *( --s ) = t + '0'; + u /= base; + } + break; +/* + // The generic case, not yet in use + default: + while( u ) + { + t = u % base; + if( t >= 10) + { + t += apBuf->flags.letBase - '0' - 10; + } + *( --s ) = t + '0'; + u /= base; + } + break; +*/ + } + + if( neg != 0 ) + { + if( apBuf->flags.width && (apBuf->flags.pad & PAD_ZERO ) ) + { + if( strbuf_printchar( apBuf, '-' ) == 0 ) + { + return pdFALSE; + } + --apBuf->flags.width; + } + else + { + *( --s ) = '-'; + } + } + + return prints( apBuf, s ); +} +/*-----------------------------------------------------------*/ + +static BaseType_t printIp(struct SStringBuf *apBuf, unsigned i ) +{ + char print_buf[16]; + + sprintf( print_buf, "%u.%u.%u.%u", + i >> 24, + ( i >> 16 ) & 0xff, + ( i >> 8 ) & 0xff, + i & 0xff ); + apBuf->flags.isNumber = pdTRUE; /* Parameter for prints */ + prints( apBuf, print_buf ); + + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +static void tiny_print( struct SStringBuf *apBuf, const char *format, va_list args ) +{ + char scr[2]; + + for( ; ; ) + { + int ch = *( format++ ); + + if( ch != '%' ) + { + do + { + /* Put the most like flow in a small loop */ + if( strbuf_printchar_inline( apBuf, ch ) == 0 ) + { + return; + } + ch = *( format++ ); + } while( ch != '%' ); + } + ch = *( format++ ); + /* Now ch has character after '%', format pointing to next */ + + if( ch == '\0' ) + { + break; + } + if( ch == '%' ) + { + if( strbuf_printchar( apBuf, ch ) == 0 ) + { + return; + } + continue; + } + memset( &apBuf->flags, '\0', sizeof( apBuf->flags ) ); + + if( ch == '-' ) + { + ch = *( format++ ); + apBuf->flags.pad = PAD_RIGHT; + } + while( ch == '0' ) + { + ch = *( format++ ); + apBuf->flags.pad |= PAD_ZERO; + } + if( ch == '*' ) + { + ch = *( format++ ); + apBuf->flags.width = va_arg( args, int ); + } + else + { + while( ch >= '0' && ch <= '9' ) + { + apBuf->flags.width *= 10; + apBuf->flags.width += ch - '0'; + ch = *( format++ ); + } + } + if( ch == '.' ) + { + ch = *( format++ ); + if( ch == '*' ) + { + apBuf->flags.printLimit = va_arg( args, int ); + ch = *( format++ ); + } + else + { + while( ch >= '0' && ch <= '9' ) + { + apBuf->flags.printLimit *= 10; + apBuf->flags.printLimit += ch - '0'; + ch = *( format++ ); + } + } + } + if( apBuf->flags.printLimit == 0 ) + { + apBuf->flags.printLimit--; /* -1: make it unlimited */ + } + if( ch == 's' ) + { + register char *s = ( char * )va_arg( args, int ); + if( prints( apBuf, s ? s : "(null)" ) == 0 ) + { + break; + } + continue; + } + if( ch == 'c' ) + { + /* char are converted to int then pushed on the stack */ + scr[0] = ( char ) va_arg( args, int ); + + if( strbuf_printchar( apBuf, scr[0] ) == 0 ) + { + return; + } + + continue; + } + if( ch == 'l' ) + { + ch = *( format++ ); + apBuf->flags.long32 = 1; + /* Makes not difference as u32 == long */ + } + if( ch == 'L' ) + { + ch = *( format++ ); + apBuf->flags.long64 = 1; + /* Does make a difference */ + } + apBuf->flags.base = 10; + apBuf->flags.letBase = 'a'; + + if( ch == 'd' || ch == 'u' ) + { + apBuf->flags.isSigned = ( ch == 'd' ); +#if SPRINTF_LONG_LONG + if( apBuf->flags.long64 != pdFALSE ) + { + if( printll( apBuf, va_arg( args, long long ) ) == 0 ) + { + break; + } + } else +#endif /* SPRINTF_LONG_LONG */ + if( printi( apBuf, va_arg( args, int ) ) == 0 ) + { + break; + } + continue; + } + + apBuf->flags.base = 16; /* From here all hexadecimal */ + + if( ch == 'x' && format[0] == 'i' && format[1] == 'p' ) + { + format += 2; /* eat the "xi" of "xip" */ + /* Will use base 10 again */ + if( printIp( apBuf, va_arg( args, int ) ) == 0 ) + { + break; + } + continue; + } + if( ch == 'x' || ch == 'X' || ch == 'p' || ch == 'o' ) + { + if( ch == 'X' ) + { + apBuf->flags.letBase = 'A'; + } + else if( ch == 'o' ) + { + apBuf->flags.base = 8; + } +#if SPRINTF_LONG_LONG + if( apBuf->flags.long64 != pdFALSE ) + { + if( printll( apBuf, va_arg( args, long long ) ) == 0 ) + { + break; + } + } else +#endif /* SPRINTF_LONG_LONG */ + if( printi( apBuf, va_arg( args, int ) ) == 0 ) + { + break; + } + continue; + } + } + strbuf_printchar( apBuf, '\0' ); +} +/*-----------------------------------------------------------*/ + +int vsnprintf( char *apBuf, size_t aMaxLen, const char *apFmt, va_list args ) +{ + struct SStringBuf strBuf; + strbuf_init( &strBuf, apBuf, ( const char* )apBuf + aMaxLen ); + tiny_print( &strBuf, apFmt, args ); + + return strBuf.curLen; +} +/*-----------------------------------------------------------*/ + +int snprintf( char *apBuf, size_t aMaxLen, const char *apFmt, ... ) +{ + va_list args; + + va_start( args, apFmt ); + struct SStringBuf strBuf; + strbuf_init( &strBuf, apBuf, ( const char* )apBuf + aMaxLen ); + tiny_print( &strBuf, apFmt, args ); + va_end( args ); + + return strBuf.curLen; +} +/*-----------------------------------------------------------*/ + +int sprintf( char *apBuf, const char *apFmt, ... ) +{ + va_list args; + + va_start( args, apFmt ); + struct SStringBuf strBuf; + strbuf_init( &strBuf, apBuf, ( const char * )apBuf + 1024 ); + tiny_print( &strBuf, apFmt, args ); + va_end( args ); + + return strBuf.curLen; +} +/*-----------------------------------------------------------*/ + +int vsprintf( char *apBuf, const char *apFmt, va_list args ) +{ + struct SStringBuf strBuf; + strbuf_init( &strBuf, apBuf, ( const char* ) apBuf + 1024 ); + tiny_print( &strBuf, apFmt, args ); + + return strBuf.curLen; +} +/*-----------------------------------------------------------*/ + +const char *mkSize (unsigned long long aSize, char *apBuf, int aLen) +{ +static char retString[33]; +size_t gb, mb, kb, sb; + + if (apBuf == NULL) { + apBuf = retString; + aLen = sizeof( retString ); + } + gb = aSize / (1024*1024*1024); + aSize -= gb * (1024*1024*1024); + mb = aSize / (1024*1024); + aSize -= mb * (1024*1024); + kb = aSize / (1024); + aSize -= kb * (1024); + sb = aSize; + if( gb ) + { + snprintf (apBuf, aLen, "%u.%02u GB", ( unsigned ) gb, ( unsigned ) ( ( 100 * mb ) / 1024ul ) ); + } + else if( mb ) + { + snprintf (apBuf, aLen, "%u.%02u MB", ( unsigned ) mb, ( unsigned ) ( ( 100 * kb) / 1024ul ) ); + } + else if( kb != 0ul ) + { + snprintf (apBuf, aLen, "%u.%02u KB", ( unsigned ) kb, ( unsigned ) ( ( 100 * sb) / 1024ul ) ); + } + else + { + snprintf (apBuf, aLen, "%u bytes", ( unsigned ) sb); + } + return apBuf; +} diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_CLI_FAT_SL_SAM4E_Atmel_Studio/ReadMe.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_CLI_FAT_SL_SAM4E_Atmel_Studio/ReadMe.txt new file mode 100644 index 0000000..24bb546 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_CLI_FAT_SL_SAM4E_Atmel_Studio/ReadMe.txt @@ -0,0 +1,4 @@ +FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by FreeRTOS+TCP, +which was brought into the main download in FreeRTOS V10.0.0. FreeRTOS+TCP can +be configured as a UDP only stack, and FreeRTOS+UDP does not contain the patches +applied to FreeRTOS+TCP. \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_CLI_FAT_SL_SAM4E_Atmel_Studio/See also FreeRTOS+TCP.url b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_CLI_FAT_SL_SAM4E_Atmel_Studio/See also FreeRTOS+TCP.url new file mode 100644 index 0000000..2da199c --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_CLI_FAT_SL_SAM4E_Atmel_Studio/See also FreeRTOS+TCP.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 +[InternetShortcut] +URL=http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/index.html +IDList= diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ReadMe.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ReadMe.txt new file mode 100644 index 0000000..24bb546 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ReadMe.txt @@ -0,0 +1,4 @@ +FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by FreeRTOS+TCP, +which was brought into the main download in FreeRTOS V10.0.0. FreeRTOS+TCP can +be configured as a UDP only stack, and FreeRTOS+UDP does not contain the patches +applied to FreeRTOS+TCP. \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/See also FreeRTOS+TCP.url b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/See also FreeRTOS+TCP.url new file mode 100644 index 0000000..2da199c --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/See also FreeRTOS+TCP.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 +[InternetShortcut] +URL=http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/index.html +IDList= diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/ReadMe.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/ReadMe.txt new file mode 100644 index 0000000..24bb546 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/ReadMe.txt @@ -0,0 +1,4 @@ +FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by FreeRTOS+TCP, +which was brought into the main download in FreeRTOS V10.0.0. FreeRTOS+TCP can +be configured as a UDP only stack, and FreeRTOS+UDP does not contain the patches +applied to FreeRTOS+TCP. \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/See also FreeRTOS+TCP.url b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/See also FreeRTOS+TCP.url new file mode 100644 index 0000000..2da199c --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_Windows_Simulator/See also FreeRTOS+TCP.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 +[InternetShortcut] +URL=http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/index.html +IDList= diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/FreeRTOSConfig.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/FreeRTOSConfig.h new file mode 100644 index 0000000..e031afb --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/FreeRTOSConfig.h @@ -0,0 +1,97 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configTICK_RATE_HZ ( 1000 ) /* In this non-real time simulated environment the tick frequency has to be at least a multiple of the Win32 tick frequency, and therefore very slow. */ +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 60 ) /* In this simulated case, the stack only has to hold one small structure as the real stack is part of the Win32 thread. */ +#define configTOTAL_HEAP_SIZE ( ( size_t ) 0 ) /* This parameter has no effect when heap_3.c is included in the project. */ +#define configMAX_TASK_NAME_LEN ( 7 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configCHECK_FOR_STACK_OVERFLOW 0 /* Not applicable to the Win32 port. */ +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 + +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY 2 +#define configTIMER_QUEUE_LENGTH 20 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + +#define configMAX_PRIORITIES ( 7 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 1 + +/* Run time stats gathering definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 + +extern void vAssertCalled( void ); +#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled() + +/* The TCP port used by both the secure client and the secure server. */ +#define configTCP_PORT_NUMBER 5001 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/FreeRTOS_Plus_WolfSSL.sln b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/FreeRTOS_Plus_WolfSSL.sln new file mode 100644 index 0000000..3f819af --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/FreeRTOS_Plus_WolfSSL.sln @@ -0,0 +1,20 @@ + +Microsoft Visual Studio Solution File, Format Version 11.00 +# Visual C++ Express 2010 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "WIN32", "WIN32.vcxproj", "{C686325E-3261-42F7-AEB1-DDE5280E1CEB}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Win32 = Debug|Win32 + Release|Win32 = Release|Win32 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.ActiveCfg = Debug|Win32 + {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.Build.0 = Debug|Win32 + {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.ActiveCfg = Release|Win32 + {C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.Build.0 = Release|Win32 + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/READ_ME.url b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/READ_ME.url new file mode 100644 index 0000000..4b773e3 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/READ_ME.url @@ -0,0 +1,5 @@ +[InternetShortcut] +URL=http://www.freertos.org/FreeRTOS-Plus/WolfSSL/FreeRTOS_WolfSSL_Example.shtml +IDList= +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/SecureTCPClientTask.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/SecureTCPClientTask.c new file mode 100644 index 0000000..ad8d22c --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/SecureTCPClientTask.c @@ -0,0 +1,136 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#pragma comment( lib, "ws2_32.lib" ) + +/* Win32 includes. */ +#include + +/* wolfSSL includes. */ +#include "wolfssl/ssl.h" + +/* Standard includes. */ +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*-----------------------------------------------------------*/ + +/* The wolfSSL context for the client. */ +static WOLFSSL_CTX* xWolfSSL_ClientContext = NULL; + +/*-----------------------------------------------------------*/ + +/* See the comments at the top of main.c. */ +void vSecureTCPClientTask( void *pvParameters ) +{ +SOCKET xClientSocket; +struct sockaddr_in xConnection; +WOLFSSL* xWolfSSL_Object; +WORD wVersionRequested; +WSADATA xWSAData; +char cString[ 50 ]; +BaseType_t lReturned; +uint32_t ulCount = 0UL; + + /* Remove compiler warning about unused parameters. */ + ( void ) pvParameters; + + /* Prepare to use WinSock. */ + wVersionRequested = MAKEWORD( 2, 2 ); + configASSERT( WSAStartup( wVersionRequested, &xWSAData ) == 0 ); + + /* Set family and port for client socket. */ + memset( ( void * ) &xConnection, 0x00, sizeof( struct sockaddr_in ) ); + xConnection.sin_family = AF_INET; + xConnection.sin_addr.s_addr = inet_addr("127.0.0.1"); + xConnection.sin_port = htons( configTCP_PORT_NUMBER ); + + /* Attempt to create a context that uses the TLS 1.2 server protocol. */ + xWolfSSL_ClientContext = wolfSSL_CTX_new( wolfTLSv1_2_client_method() ); + configASSERT( xWolfSSL_ClientContext ); + + /* Load the CA certificate. */ + lReturned = wolfSSL_CTX_load_verify_locations( xWolfSSL_ClientContext, "ca-cert.pem", 0 ); + configASSERT( lReturned == SSL_SUCCESS ); + + for( ;; ) + { + /* Create the socket. */ + xClientSocket = socket( AF_INET, SOCK_STREAM, 0 ); + configASSERT( xClientSocket != INVALID_SOCKET ); + + /* Connect to the secure server. */ + if( connect( xClientSocket, ( SOCKADDR * ) &xConnection, sizeof( xConnection ) ) == 0 ) + { + /* The connect was successful. Create a wolfSSL object to associate + with this connection. */ + xWolfSSL_Object = wolfSSL_new( xWolfSSL_ClientContext ); + + if( xWolfSSL_Object != NULL ) + { + /* Associate the created wolfSSL object with the connected + socket. */ + lReturned = wolfSSL_set_fd( xWolfSSL_Object, xClientSocket ); + configASSERT( lReturned == SSL_SUCCESS ); + + /* The count is used to differentiate between messages sent to + the server, and to break out of the do while loop below. */ + ulCount = 0UL; + + do + { + /* Create the string that is sent to the secure server. */ + sprintf( cString, "Message number %lu\r\n", ulCount ); + + /* The next line is the secure equivalent of the standard + sockets call: + lReturned = send( xClientSocket, cString, strlen( cString ) + 1, 0 ); */ + lReturned = wolfSSL_write( xWolfSSL_Object, cString, strlen( cString ) + 1 ); + + + /* Short delay to prevent the messages streaming up the + console too quickly. */ + vTaskDelay( 50 ); + ulCount++; + + } while( ( lReturned != SOCKET_ERROR ) && ( ulCount < 10UL ) ); + } + + wolfSSL_free( xWolfSSL_Object ); + closesocket( xClientSocket ); + + /* Delay for a short time before starting over. */ + vTaskDelay( 250 ); + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/SecureTCPServerTask.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/SecureTCPServerTask.c new file mode 100644 index 0000000..ba678b9 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/SecureTCPServerTask.c @@ -0,0 +1,245 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#pragma comment( lib, "ws2_32.lib" ) + +/* Win32 includes. */ +#include + +/* wolfSSL includes. */ +#include "wolfssl/ssl.h" + +/* Standard includes. */ +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* This application is using the FreeRTOS Windows simulator, which uses the +FreeRTOS scheduler to schedule FreeRTOS task within the Windows environment. +The Windows envrionment must not be allowed to block any Windows threads that +are running FreeRTOS tasks, unless the FreeRTOS task is running at the FreeRTOS +idle priority. For simplicity, this demo uses the Windows TCP/IP stack, the +API for which can cause Windows threads to block. Therefore, any FreeRTOS task +that makes calls to the Windows TCP/IP stack must be assigned the idle prioity. +Note this is only a restriction of the simulated Windows environment - real +FreeRTOS ports do not have this restriction. */ +#define sstSECURE_CLIENT_TASK_PRIORITY ( tskIDLE_PRIORITY ) + +/*-----------------------------------------------------------*/ + +/* + * Open, configures and binds the server's TCP socket. + */ +static SOCKET prvOpenServerSocket( void ); + +/* + * Prepare the wolfSSL library for use. + */ +static void prvInitialiseWolfSSL( void ); + +/* + * The task that implements the client side of the connection. + */ +extern void vSecureTCPClientTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The wolfSSL context for the server. */ +static WOLFSSL_CTX* xWolfSSL_ServerContext = NULL; + +/*-----------------------------------------------------------*/ + +/* See the comments at the top of main.c. */ +void vSecureTCPServerTask( void *pvParameters ) +{ +BaseType_t xReturned; +long lBytes; +uint8_t cReceivedString[ 60 ]; +struct sockaddr_in xClient; +int xClientAddressLength = sizeof( struct sockaddr_in ); +SOCKET xListeningSocket, xConnectedSocket; +WOLFSSL* xWolfSSL_Object; /* Only one connection is accepted at a time, so only one object is needed at a time. */ + + /* Just to prevent compiler warnings. */ + ( void ) pvParameters; + + /* Perform the initialisation necessary before wolfSSL can be used. */ + prvInitialiseWolfSSL(); + configASSERT( xWolfSSL_ServerContext ); + + /* Attempt to open the socket. */ + xListeningSocket = prvOpenServerSocket(); + + /* Now the server socket has been created and the wolfSSL library has been + initialised, the task that implements the client side can be created. */ + xTaskCreate( vSecureTCPClientTask, "Client", configMINIMAL_STACK_SIZE, NULL, sstSECURE_CLIENT_TASK_PRIORITY, NULL ); + + if( xListeningSocket != INVALID_SOCKET ) + { + for( ;; ) + { + /* Wait until the client connects. */ + printf( "Waiting for new connection\r\n" ); + xConnectedSocket = accept( xListeningSocket, ( struct sockaddr * ) &xClient, &xClientAddressLength ); + + if( xConnectedSocket != INVALID_SOCKET ) + { + printf( "Connection established\r\n" ); + + /* A connection has been accepted by the server. Create a + wolfSSL object for use with the newly connected socket. */ + xWolfSSL_Object = NULL; + xWolfSSL_Object = wolfSSL_new( xWolfSSL_ServerContext ); + + if( xWolfSSL_Object != NULL ) + { + /* Associate the created wolfSSL object with the connected + socket. */ + xReturned = wolfSSL_set_fd( xWolfSSL_Object, xConnectedSocket ); + configASSERT( xReturned == SSL_SUCCESS ); + + do + { + /* The next line is the secure equivalent to the + standard sockets call: + lBytes = recv( xConnectedSocket, cReceivedString, 50, 0 ); */ + lBytes = wolfSSL_read( xWolfSSL_Object, cReceivedString, sizeof( cReceivedString ) ); + + /* Print the received characters. */ + if( lBytes > 0 ) + { + printf( "Received by the secure server: %s\r\n", cReceivedString ); + } + + } while ( lBytes > 0 ); + + /* The connection was closed, close the socket and free the + wolfSSL object. */ + closesocket( xConnectedSocket ); + wolfSSL_free( xWolfSSL_Object ); + printf( "Connection closed, back to start\r\n\r\n" ); + } + } + } + } + else + { + /* The socket could not be opened. */ + vTaskDelete( NULL ); + } +} +/*-----------------------------------------------------------*/ + +static SOCKET prvOpenServerSocket( void ) +{ +WSADATA xWSAData; +WORD wVersionRequested; +struct sockaddr_in xConnection; +SOCKET xSocket = INVALID_SOCKET; + + wVersionRequested = MAKEWORD( 2, 2 ); + + /* Prepare to use WinSock. */ + if( WSAStartup( wVersionRequested, &xWSAData ) != 0 ) + { + fprintf( stderr, "Could not open Windows connection.\n" ); + } + else + { + xSocket = socket( AF_INET, SOCK_STREAM, 0 ); + if( xSocket == INVALID_SOCKET) + { + fprintf( stderr, "Could not create socket.\n" ); + WSACleanup(); + } + else + { + /* Zero out the server structure. */ + memset( ( void * ) &xConnection, 0x00, sizeof( struct sockaddr_in ) ); + + xConnection.sin_family = AF_INET; + xConnection.sin_addr.s_addr = inet_addr("127.0.0.1"); + xConnection.sin_port = htons( configTCP_PORT_NUMBER ); + + /* Bind the address to the socket. */ + if( bind( xSocket, ( struct sockaddr * ) &xConnection, sizeof( struct sockaddr_in ) ) == -1 ) + { + fprintf( stderr, "Could not socket to port %d.\n", configTCP_PORT_NUMBER ); + closesocket( xSocket ); + xSocket = INVALID_SOCKET; + WSACleanup(); + } + + if( listen( xSocket, 20 ) != 0 ) + { + closesocket( xSocket ); + xSocket = INVALID_SOCKET; + WSACleanup(); + } + } + } + + return xSocket; +} +/*-----------------------------------------------------------*/ + +static void prvInitialiseWolfSSL( void ) +{ +int32_t iReturn; + + #ifdef DEBUG_WOLFSSL + { + wolfSSL_Debugging_ON(); + } + #endif + + /* Initialise wolfSSL. This must be done before any other wolfSSL functions + are called. */ + wolfSSL_Init(); + + /* Attempt to create a context that uses the TLS 1.2 server protocol. */ + xWolfSSL_ServerContext = wolfSSL_CTX_new( wolfTLSv1_2_server_method() ); + + if( xWolfSSL_ServerContext != NULL ) + { + /* Load the CA certificate. Real applications should ensure that + wolfSSL_CTX_load_verify_locations() returns SSL_SUCCESS before + proceeding. */ + iReturn = wolfSSL_CTX_load_verify_locations( xWolfSSL_ServerContext, "ca-cert.pem", 0 ); + configASSERT( iReturn == SSL_SUCCESS ); + + iReturn = wolfSSL_CTX_use_certificate_file( xWolfSSL_ServerContext, "server-cert.pem", SSL_FILETYPE_PEM ); + configASSERT( iReturn == SSL_SUCCESS ); + + iReturn = wolfSSL_CTX_use_PrivateKey_file( xWolfSSL_ServerContext, "server-key.pem", SSL_FILETYPE_PEM ); + configASSERT( iReturn == SSL_SUCCESS ); + } +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/WIN32.vcxproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/WIN32.vcxproj new file mode 100644 index 0000000..09a0648 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/WIN32.vcxproj @@ -0,0 +1,200 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + + {C686325E-3261-42F7-AEB1-DDE5280E1CEB} + RTOSDemo + + + + Application + false + MultiByte + + + Application + false + MultiByte + + + + + + + + + + + + + + + <_ProjectFileVersion>10.0.30319.1 + .\Debug\ + .\Debug\ + true + .\Release\ + .\Release\ + false + + + + .\Debug/WIN32.tlb + + + + + Disabled + ..\..\Source\wolfSSL;..\..\..\FreeRTOS\Source\include;..\..\..\FreeRTOS\Source\portable\MSVC-MingW;.;%(AdditionalIncludeDirectories) + WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS;SIZEOF_LONG_LONG=8;%(PreprocessorDefinitions) + true + EnableFastChecks + MultiThreadedDebug + .\Debug/WIN32.pch + .\Debug/ + .\Debug/ + .\Debug/ + Level4 + true + false + EditAndContinue + 4206;4214;%(DisableSpecificWarnings) + + + _DEBUG;%(PreprocessorDefinitions) + 0x0c09 + + + .\Debug/RTOSDemo.exe + true + true + .\Debug/WIN32.pdb + Console + MachineX86 + %(AdditionalDependencies) + + + + + true + .\Debug/WIN32.bsc + + + + + .\Release/WIN32.tlb + + + + + MaxSpeed + OnlyExplicitInline + _WINSOCKAPI_;WIN32;NDEBUG;_CONSOLE;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) + true + MultiThreaded + true + .\Release/WIN32.pch + .\Release/ + .\Release/ + .\Release/ + Level3 + true + ..\..\Source\include;..\..\Source\portable\MSVC-MingW;..\Common\Include;.;%(AdditionalIncludeDirectories) + + + NDEBUG;%(PreprocessorDefinitions) + 0x0c09 + + + .\Release/RTOSDemo.exe + true + .\Release/WIN32.pdb + Console + MachineX86 + ..\Common\ethernet\lwip-1.4.0\ports\win32\WinPCap + wpcap.lib;%(AdditionalDependencies) + + + true + .\Release/WIN32.bsc + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + %(AdditionalIncludeDirectories) + %(PreprocessorDefinitions) + %(PreprocessorDefinitions) + + + + + + + + + + + \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/WIN32.vcxproj.filters b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/WIN32.vcxproj.filters new file mode 100644 index 0000000..de5048f --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/WIN32.vcxproj.filters @@ -0,0 +1,210 @@ + + + + + {38712199-cebf-4124-bf15-398f7c3419ea} + ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe + + + {34567deb-d5ab-4a56-8640-0aaec609521a} + cpp;c;cxx;rc;def;r;odl;idl;hpj;bat + + + {af3445a1-4908-4170-89ed-39345d90d30c} + + + {f32be356-4763-4cae-9020-974a2638cb08} + *.c + + + {88f409e6-d396-4ac5-94bd-7a99c914be46} + + + {e5ad4ec7-23dc-4295-8add-2acaee488f5a} + + + {8b481200-a9e5-48a4-98ad-49d2783cd652} + + + {738eaad9-4e49-4309-9074-c3d9e102fb4a} + + + + + Demo App Source + + + FreeRTOS\Source\Portable + + + FreeRTOS\Source\Portable + + + FreeRTOS\Source + + + FreeRTOS\Source + + + FreeRTOS\Source + + + FreeRTOS\Source + + + FreeRTOS+\wolfSSL + + + FreeRTOS+\wolfSSL + + + FreeRTOS+\wolfSSL + + + FreeRTOS+\wolfSSL + + + FreeRTOS+\wolfSSL + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + Demo App Source + + + Demo App Source + + + FreeRTOS+\wolfSSL\wolfcrypt + + + FreeRTOS+\wolfSSL\wolfcrypt + + + + + Demo App Source + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/WIN32.vcxproj.user b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/WIN32.vcxproj.user new file mode 100644 index 0000000..695b5c7 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/WIN32.vcxproj.user @@ -0,0 +1,3 @@ + + + \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/ca-cert.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/ca-cert.pem new file mode 100644 index 0000000..6eacbeb --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/ca-cert.pem @@ -0,0 +1,86 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 15672591315981621815 (0xd9803ac3d2f4da37) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C=US, ST=Montana, L=Bozeman, O=Sawtooth, OU=Consulting, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Validity + Not Before: May 7 18:21:01 2015 GMT + Not After : Jan 31 18:21:01 2018 GMT + Subject: C=US, ST=Montana, L=Bozeman, O=Sawtooth, OU=Consulting, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:bf:0c:ca:2d:14:b2:1e:84:42:5b:cd:38:1f:4a: + f2:4d:75:10:f1:b6:35:9f:df:ca:7d:03:98:d3:ac: + de:03:66:ee:2a:f1:d8:b0:7d:6e:07:54:0b:10:98: + 21:4d:80:cb:12:20:e7:cc:4f:de:45:7d:c9:72:77: + 32:ea:ca:90:bb:69:52:10:03:2f:a8:f3:95:c5:f1: + 8b:62:56:1b:ef:67:6f:a4:10:41:95:ad:0a:9b:e3: + a5:c0:b0:d2:70:76:50:30:5b:a8:e8:08:2c:7c:ed: + a7:a2:7a:8d:38:29:1c:ac:c7:ed:f2:7c:95:b0:95: + 82:7d:49:5c:38:cd:77:25:ef:bd:80:75:53:94:3c: + 3d:ca:63:5b:9f:15:b5:d3:1d:13:2f:19:d1:3c:db: + 76:3a:cc:b8:7d:c9:e5:c2:d7:da:40:6f:d8:21:dc: + 73:1b:42:2d:53:9c:fe:1a:fc:7d:ab:7a:36:3f:98: + de:84:7c:05:67:ce:6a:14:38:87:a9:f1:8c:b5:68: + cb:68:7f:71:20:2b:f5:a0:63:f5:56:2f:a3:26:d2: + b7:6f:b1:5a:17:d7:38:99:08:fe:93:58:6f:fe:c3: + 13:49:08:16:0b:a7:4d:67:00:52:31:67:23:4e:98: + ed:51:45:1d:b9:04:d9:0b:ec:d8:28:b3:4b:bd:ed: + 36:79 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Subject Key Identifier: + 27:8E:67:11:74:C3:26:1D:3F:ED:33:63:B3:A4:D8:1D:30:E5:E8:D5 + X509v3 Authority Key Identifier: + keyid:27:8E:67:11:74:C3:26:1D:3F:ED:33:63:B3:A4:D8:1D:30:E5:E8:D5 + DirName:/C=US/ST=Montana/L=Bozeman/O=Sawtooth/OU=Consulting/CN=www.wolfssl.com/emailAddress=info@wolfssl.com + serial:D9:80:3A:C3:D2:F4:DA:37 + + X509v3 Basic Constraints: + CA:TRUE + Signature Algorithm: sha256WithRSAEncryption + 7a:af:44:3b:aa:6f:53:42:b2:33:aa:43:5f:56:30:d3:b9:96: + 0b:9a:55:5a:39:2a:0b:4e:e4:2e:f1:95:66:c9:86:36:82:8d: + 63:7c:4d:a2:ee:48:ba:03:c7:90:d7:a7:c6:74:60:48:5f:31: + a2:f9:5e:3e:c3:82:e1:e5:2f:41:81:83:29:25:79:d1:53:00: + 69:3c:ed:0a:30:3b:41:1d:92:a1:2c:a8:9d:2c:e3:23:87:79: + e0:55:6e:91:a8:50:da:46:2f:c2:20:50:3e:2b:47:97:14:b0: + 7d:04:ba:45:51:d0:6e:e1:5a:a2:4b:84:9c:4d:cd:85:04:f9: + 28:31:82:93:bc:c7:59:49:91:03:e8:df:6a:e4:56:ad:6a:cb: + 1f:0d:37:e4:5e:bd:e7:9f:d5:ec:9d:3c:18:25:9b:f1:2f:50: + 7d:eb:31:cb:f1:63:22:9d:57:fc:f3:84:20:1a:c6:07:87:92: + 26:9e:15:18:59:33:06:dc:fb:b0:b6:76:5d:f1:c1:2f:c8:2f: + 62:9c:c0:d6:de:eb:65:77:f3:5c:a6:c3:88:27:96:75:b4:f4: + 54:cd:ff:2d:21:2e:96:f0:07:73:4b:e9:93:92:90:de:62:d9: + a3:3b:ac:6e:24:5f:27:4a:b3:94:70:ff:30:17:e7:7e:32:8f: + 65:b7:75:58 +-----BEGIN CERTIFICATE----- +MIIEqjCCA5KgAwIBAgIJANmAOsPS9No3MA0GCSqGSIb3DQEBCwUAMIGUMQswCQYD +VQQGEwJVUzEQMA4GA1UECAwHTW9udGFuYTEQMA4GA1UEBwwHQm96ZW1hbjERMA8G +A1UECgwIU2F3dG9vdGgxEzARBgNVBAsMCkNvbnN1bHRpbmcxGDAWBgNVBAMMD3d3 +dy53b2xmc3NsLmNvbTEfMB0GCSqGSIb3DQEJARYQaW5mb0B3b2xmc3NsLmNvbTAe +Fw0xNTA1MDcxODIxMDFaFw0xODAxMzExODIxMDFaMIGUMQswCQYDVQQGEwJVUzEQ +MA4GA1UECAwHTW9udGFuYTEQMA4GA1UEBwwHQm96ZW1hbjERMA8GA1UECgwIU2F3 +dG9vdGgxEzARBgNVBAsMCkNvbnN1bHRpbmcxGDAWBgNVBAMMD3d3dy53b2xmc3Ns +LmNvbTEfMB0GCSqGSIb3DQEJARYQaW5mb0B3b2xmc3NsLmNvbTCCASIwDQYJKoZI +hvcNAQEBBQADggEPADCCAQoCggEBAL8Myi0Ush6EQlvNOB9K8k11EPG2NZ/fyn0D +mNOs3gNm7irx2LB9bgdUCxCYIU2AyxIg58xP3kV9yXJ3MurKkLtpUhADL6jzlcXx +i2JWG+9nb6QQQZWtCpvjpcCw0nB2UDBbqOgILHztp6J6jTgpHKzH7fJ8lbCVgn1J +XDjNdyXvvYB1U5Q8PcpjW58VtdMdEy8Z0TzbdjrMuH3J5cLX2kBv2CHccxtCLVOc +/hr8fat6Nj+Y3oR8BWfOahQ4h6nxjLVoy2h/cSAr9aBj9VYvoybSt2+xWhfXOJkI +/pNYb/7DE0kIFgunTWcAUjFnI06Y7VFFHbkE2Qvs2CizS73tNnkCAwEAAaOB/DCB ++TAdBgNVHQ4EFgQUJ45nEXTDJh0/7TNjs6TYHTDl6NUwgckGA1UdIwSBwTCBvoAU +J45nEXTDJh0/7TNjs6TYHTDl6NWhgZqkgZcwgZQxCzAJBgNVBAYTAlVTMRAwDgYD +VQQIDAdNb250YW5hMRAwDgYDVQQHDAdCb3plbWFuMREwDwYDVQQKDAhTYXd0b290 +aDETMBEGA1UECwwKQ29uc3VsdGluZzEYMBYGA1UEAwwPd3d3LndvbGZzc2wuY29t +MR8wHQYJKoZIhvcNAQkBFhBpbmZvQHdvbGZzc2wuY29tggkA2YA6w9L02jcwDAYD +VR0TBAUwAwEB/zANBgkqhkiG9w0BAQsFAAOCAQEAeq9EO6pvU0KyM6pDX1Yw07mW +C5pVWjkqC07kLvGVZsmGNoKNY3xNou5IugPHkNenxnRgSF8xovlePsOC4eUvQYGD +KSV50VMAaTztCjA7QR2SoSyonSzjI4d54FVukahQ2kYvwiBQPitHlxSwfQS6RVHQ +buFaokuEnE3NhQT5KDGCk7zHWUmRA+jfauRWrWrLHw035F6955/V7J08GCWb8S9Q +fesxy/FjIp1X/POEIBrGB4eSJp4VGFkzBtz7sLZ2XfHBL8gvYpzA1t7rZXfzXKbD +iCeWdbT0VM3/LSEulvAHc0vpk5KQ3mLZozusbiRfJ0qzlHD/MBfnfjKPZbd1WA== +-----END CERTIFICATE----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/main.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/main.c new file mode 100644 index 0000000..0558704 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/main.c @@ -0,0 +1,103 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Standard includes. */ +#include +#include + +/* FreeRTOS includes. */ +#include +#include "task.h" + +/* This application is using the FreeRTOS Windows simulator, which uses the +FreeRTOS scheduler to schedule FreeRTOS task within the Windows environment. +The Windows environment must not be allowed to block any Windows threads that +are running FreeRTOS tasks, unless the FreeRTOS task is running at the FreeRTOS +idle priority. For simplicity, this demo uses the Windows TCP/IP stack, the +API for which can cause Windows threads to block. Therefore, any FreeRTOS task +that makes calls to the Windows TCP/IP stack must be assigned the idle priority. +Note this is only a restriction of the simulated Windows environment - real +FreeRTOS ports do not have this restriction. */ +#define mainSECURE_SERVER_TASK_PRIORITY ( tskIDLE_PRIORITY ) + + +/*-----------------------------------------------------------*/ + +/* + * The task that implements the server side. + */ +extern void vSecureTCPServerTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +int main( void ) +{ +const uint32_t ulLongTime_ms = 250UL; + + /* Create the TCP server task. This will itself create the client task + once it has completed the wolfSSL initialisation. */ + xTaskCreate( vSecureTCPServerTask, "Server", configMINIMAL_STACK_SIZE, NULL, mainSECURE_SERVER_TASK_PRIORITY, NULL ); + + /* Start the task running. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was insufficient FreeRTOS heap memory available for the idle and/or + timer tasks to be created. See the memory management section on the + FreeRTOS web site for more details (this is standard text that is not + really applicable to the Win32 simulator port). */ + for( ;; ) + { + Sleep( ulLongTime_ms ); + } +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +const unsigned long ulMSToSleep = 5; + + /* This function is called on each cycle of the idle task if + configUSE_IDLE_HOOK is set to 1 in FreeRTOSConfig.h. Sleep to reduce CPU + load. */ + Sleep( ulMSToSleep ); +} +/*-----------------------------------------------------------*/ + +void vAssertCalled( void ) +{ +const unsigned long ulLongSleep = 1000UL; + + taskDISABLE_INTERRUPTS(); + for( ;; ) + { + Sleep( ulLongSleep ); + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/server-cert.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/server-cert.pem new file mode 100644 index 0000000..95df724 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/server-cert.pem @@ -0,0 +1,172 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 1 (0x1) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C=US, ST=Montana, L=Bozeman, O=Sawtooth, OU=Consulting, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Validity + Not Before: May 7 18:21:01 2015 GMT + Not After : Jan 31 18:21:01 2018 GMT + Subject: C=US, ST=Montana, L=Bozeman, O=wolfSSL, OU=Support, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:c0:95:08:e1:57:41:f2:71:6d:b7:d2:45:41:27: + 01:65:c6:45:ae:f2:bc:24:30:b8:95:ce:2f:4e:d6: + f6:1c:88:bc:7c:9f:fb:a8:67:7f:fe:5c:9c:51:75: + f7:8a:ca:07:e7:35:2f:8f:e1:bd:7b:c0:2f:7c:ab: + 64:a8:17:fc:ca:5d:7b:ba:e0:21:e5:72:2e:6f:2e: + 86:d8:95:73:da:ac:1b:53:b9:5f:3f:d7:19:0d:25: + 4f:e1:63:63:51:8b:0b:64:3f:ad:43:b8:a5:1c:5c: + 34:b3:ae:00:a0:63:c5:f6:7f:0b:59:68:78:73:a6: + 8c:18:a9:02:6d:af:c3:19:01:2e:b8:10:e3:c6:cc: + 40:b4:69:a3:46:33:69:87:6e:c4:bb:17:a6:f3:e8: + dd:ad:73:bc:7b:2f:21:b5:fd:66:51:0c:bd:54:b3: + e1:6d:5f:1c:bc:23:73:d1:09:03:89:14:d2:10:b9: + 64:c3:2a:d0:a1:96:4a:bc:e1:d4:1a:5b:c7:a0:c0: + c1:63:78:0f:44:37:30:32:96:80:32:23:95:a1:77: + ba:13:d2:97:73:e2:5d:25:c9:6a:0d:c3:39:60:a4: + b4:b0:69:42:42:09:e9:d8:08:bc:33:20:b3:58:22: + a7:aa:eb:c4:e1:e6:61:83:c5:d2:96:df:d9:d0:4f: + ad:d7 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Subject Key Identifier: + B3:11:32:C9:92:98:84:E2:C9:F8:D0:3B:6E:03:42:CA:1F:0E:8E:3C + X509v3 Authority Key Identifier: + keyid:27:8E:67:11:74:C3:26:1D:3F:ED:33:63:B3:A4:D8:1D:30:E5:E8:D5 + DirName:/C=US/ST=Montana/L=Bozeman/O=Sawtooth/OU=Consulting/CN=www.wolfssl.com/emailAddress=info@wolfssl.com + serial:D9:80:3A:C3:D2:F4:DA:37 + + X509v3 Basic Constraints: + CA:TRUE + Signature Algorithm: sha256WithRSAEncryption + 67:c0:2c:a9:43:47:e7:11:14:77:ae:cc:d8:e0:6b:23:82:91: + 63:e8:a8:0d:21:c5:c8:47:97:2f:d5:f3:86:fb:6c:ce:25:f9: + 7c:78:c8:3a:22:68:f2:16:1e:d2:d2:3f:24:04:87:f2:b7:c1: + 62:63:ba:c5:fa:ae:d2:20:81:1a:d2:0c:ae:26:6b:1b:2b:10: + d3:e1:9a:4e:64:6c:97:db:36:a8:8f:f8:05:63:bf:ba:0d:88: + 0b:87:46:c9:e4:64:e3:d7:bd:b8:2d:d5:c1:c3:c4:db:55:68: + dc:a3:7a:40:b9:a9:f6:04:4a:22:cf:98:76:1c:e4:a3:ff:79: + 19:96:57:63:07:6f:f6:32:77:16:50:9b:e3:34:18:d4:eb:be: + fd:b6:6f:e3:c7:f6:85:bf:ac:32:ad:98:57:be:13:92:44:10: + a5:f3:ae:e2:66:da:44:a9:94:71:3f:d0:2f:20:59:87:e4:5a: + 40:ee:d2:e4:0c:ce:25:94:dc:0f:fe:38:e0:41:52:34:5c:bb: + c3:db:c1:5f:76:c3:5d:0e:32:69:2b:9d:01:ed:50:1b:4f:77: + a9:a9:d8:71:30:cb:2e:2c:70:00:ab:78:4b:d7:15:d9:17:f8: + 64:b2:f7:3a:da:e1:0b:8b:0a:e1:4e:b1:03:46:14:ca:94:e3: + 44:77:d7:59 +-----BEGIN CERTIFICATE----- +MIIEnjCCA4agAwIBAgIBATANBgkqhkiG9w0BAQsFADCBlDELMAkGA1UEBhMCVVMx +EDAOBgNVBAgMB01vbnRhbmExEDAOBgNVBAcMB0JvemVtYW4xETAPBgNVBAoMCFNh +d3Rvb3RoMRMwEQYDVQQLDApDb25zdWx0aW5nMRgwFgYDVQQDDA93d3cud29sZnNz +bC5jb20xHzAdBgkqhkiG9w0BCQEWEGluZm9Ad29sZnNzbC5jb20wHhcNMTUwNTA3 +MTgyMTAxWhcNMTgwMTMxMTgyMTAxWjCBkDELMAkGA1UEBhMCVVMxEDAOBgNVBAgM +B01vbnRhbmExEDAOBgNVBAcMB0JvemVtYW4xEDAOBgNVBAoMB3dvbGZTU0wxEDAO +BgNVBAsMB1N1cHBvcnQxGDAWBgNVBAMMD3d3dy53b2xmc3NsLmNvbTEfMB0GCSqG +SIb3DQEJARYQaW5mb0B3b2xmc3NsLmNvbTCCASIwDQYJKoZIhvcNAQEBBQADggEP +ADCCAQoCggEBAMCVCOFXQfJxbbfSRUEnAWXGRa7yvCQwuJXOL07W9hyIvHyf+6hn +f/5cnFF194rKB+c1L4/hvXvAL3yrZKgX/Mpde7rgIeVyLm8uhtiVc9qsG1O5Xz/X +GQ0lT+FjY1GLC2Q/rUO4pRxcNLOuAKBjxfZ/C1loeHOmjBipAm2vwxkBLrgQ48bM +QLRpo0YzaYduxLsXpvPo3a1zvHsvIbX9ZlEMvVSz4W1fHLwjc9EJA4kU0hC5ZMMq +0KGWSrzh1Bpbx6DAwWN4D0Q3MDKWgDIjlaF3uhPSl3PiXSXJag3DOWCktLBpQkIJ +6dgIvDMgs1gip6rrxOHmYYPF0pbf2dBPrdcCAwEAAaOB/DCB+TAdBgNVHQ4EFgQU +sxEyyZKYhOLJ+NA7bgNCyh8OjjwwgckGA1UdIwSBwTCBvoAUJ45nEXTDJh0/7TNj +s6TYHTDl6NWhgZqkgZcwgZQxCzAJBgNVBAYTAlVTMRAwDgYDVQQIDAdNb250YW5h +MRAwDgYDVQQHDAdCb3plbWFuMREwDwYDVQQKDAhTYXd0b290aDETMBEGA1UECwwK +Q29uc3VsdGluZzEYMBYGA1UEAwwPd3d3LndvbGZzc2wuY29tMR8wHQYJKoZIhvcN +AQkBFhBpbmZvQHdvbGZzc2wuY29tggkA2YA6w9L02jcwDAYDVR0TBAUwAwEB/zAN +BgkqhkiG9w0BAQsFAAOCAQEAZ8AsqUNH5xEUd67M2OBrI4KRY+ioDSHFyEeXL9Xz +hvtsziX5fHjIOiJo8hYe0tI/JASH8rfBYmO6xfqu0iCBGtIMriZrGysQ0+GaTmRs +l9s2qI/4BWO/ug2IC4dGyeRk49e9uC3VwcPE21Vo3KN6QLmp9gRKIs+Ydhzko/95 +GZZXYwdv9jJ3FlCb4zQY1Ou+/bZv48f2hb+sMq2YV74TkkQQpfOu4mbaRKmUcT/Q +LyBZh+RaQO7S5AzOJZTcD/444EFSNFy7w9vBX3bDXQ4yaSudAe1QG093qanYcTDL +LixwAKt4S9cV2Rf4ZLL3OtrhC4sK4U6xA0YUypTjRHfXWQ== +-----END CERTIFICATE----- +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 15672591315981621815 (0xd9803ac3d2f4da37) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C=US, ST=Montana, L=Bozeman, O=Sawtooth, OU=Consulting, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Validity + Not Before: May 7 18:21:01 2015 GMT + Not After : Jan 31 18:21:01 2018 GMT + Subject: C=US, ST=Montana, L=Bozeman, O=Sawtooth, OU=Consulting, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:bf:0c:ca:2d:14:b2:1e:84:42:5b:cd:38:1f:4a: + f2:4d:75:10:f1:b6:35:9f:df:ca:7d:03:98:d3:ac: + de:03:66:ee:2a:f1:d8:b0:7d:6e:07:54:0b:10:98: + 21:4d:80:cb:12:20:e7:cc:4f:de:45:7d:c9:72:77: + 32:ea:ca:90:bb:69:52:10:03:2f:a8:f3:95:c5:f1: + 8b:62:56:1b:ef:67:6f:a4:10:41:95:ad:0a:9b:e3: + a5:c0:b0:d2:70:76:50:30:5b:a8:e8:08:2c:7c:ed: + a7:a2:7a:8d:38:29:1c:ac:c7:ed:f2:7c:95:b0:95: + 82:7d:49:5c:38:cd:77:25:ef:bd:80:75:53:94:3c: + 3d:ca:63:5b:9f:15:b5:d3:1d:13:2f:19:d1:3c:db: + 76:3a:cc:b8:7d:c9:e5:c2:d7:da:40:6f:d8:21:dc: + 73:1b:42:2d:53:9c:fe:1a:fc:7d:ab:7a:36:3f:98: + de:84:7c:05:67:ce:6a:14:38:87:a9:f1:8c:b5:68: + cb:68:7f:71:20:2b:f5:a0:63:f5:56:2f:a3:26:d2: + b7:6f:b1:5a:17:d7:38:99:08:fe:93:58:6f:fe:c3: + 13:49:08:16:0b:a7:4d:67:00:52:31:67:23:4e:98: + ed:51:45:1d:b9:04:d9:0b:ec:d8:28:b3:4b:bd:ed: + 36:79 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Subject Key Identifier: + 27:8E:67:11:74:C3:26:1D:3F:ED:33:63:B3:A4:D8:1D:30:E5:E8:D5 + X509v3 Authority Key Identifier: + keyid:27:8E:67:11:74:C3:26:1D:3F:ED:33:63:B3:A4:D8:1D:30:E5:E8:D5 + DirName:/C=US/ST=Montana/L=Bozeman/O=Sawtooth/OU=Consulting/CN=www.wolfssl.com/emailAddress=info@wolfssl.com + serial:D9:80:3A:C3:D2:F4:DA:37 + + X509v3 Basic Constraints: + CA:TRUE + Signature Algorithm: sha256WithRSAEncryption + 7a:af:44:3b:aa:6f:53:42:b2:33:aa:43:5f:56:30:d3:b9:96: + 0b:9a:55:5a:39:2a:0b:4e:e4:2e:f1:95:66:c9:86:36:82:8d: + 63:7c:4d:a2:ee:48:ba:03:c7:90:d7:a7:c6:74:60:48:5f:31: + a2:f9:5e:3e:c3:82:e1:e5:2f:41:81:83:29:25:79:d1:53:00: + 69:3c:ed:0a:30:3b:41:1d:92:a1:2c:a8:9d:2c:e3:23:87:79: + e0:55:6e:91:a8:50:da:46:2f:c2:20:50:3e:2b:47:97:14:b0: + 7d:04:ba:45:51:d0:6e:e1:5a:a2:4b:84:9c:4d:cd:85:04:f9: + 28:31:82:93:bc:c7:59:49:91:03:e8:df:6a:e4:56:ad:6a:cb: + 1f:0d:37:e4:5e:bd:e7:9f:d5:ec:9d:3c:18:25:9b:f1:2f:50: + 7d:eb:31:cb:f1:63:22:9d:57:fc:f3:84:20:1a:c6:07:87:92: + 26:9e:15:18:59:33:06:dc:fb:b0:b6:76:5d:f1:c1:2f:c8:2f: + 62:9c:c0:d6:de:eb:65:77:f3:5c:a6:c3:88:27:96:75:b4:f4: + 54:cd:ff:2d:21:2e:96:f0:07:73:4b:e9:93:92:90:de:62:d9: + a3:3b:ac:6e:24:5f:27:4a:b3:94:70:ff:30:17:e7:7e:32:8f: + 65:b7:75:58 +-----BEGIN CERTIFICATE----- +MIIEqjCCA5KgAwIBAgIJANmAOsPS9No3MA0GCSqGSIb3DQEBCwUAMIGUMQswCQYD +VQQGEwJVUzEQMA4GA1UECAwHTW9udGFuYTEQMA4GA1UEBwwHQm96ZW1hbjERMA8G +A1UECgwIU2F3dG9vdGgxEzARBgNVBAsMCkNvbnN1bHRpbmcxGDAWBgNVBAMMD3d3 +dy53b2xmc3NsLmNvbTEfMB0GCSqGSIb3DQEJARYQaW5mb0B3b2xmc3NsLmNvbTAe +Fw0xNTA1MDcxODIxMDFaFw0xODAxMzExODIxMDFaMIGUMQswCQYDVQQGEwJVUzEQ +MA4GA1UECAwHTW9udGFuYTEQMA4GA1UEBwwHQm96ZW1hbjERMA8GA1UECgwIU2F3 +dG9vdGgxEzARBgNVBAsMCkNvbnN1bHRpbmcxGDAWBgNVBAMMD3d3dy53b2xmc3Ns +LmNvbTEfMB0GCSqGSIb3DQEJARYQaW5mb0B3b2xmc3NsLmNvbTCCASIwDQYJKoZI +hvcNAQEBBQADggEPADCCAQoCggEBAL8Myi0Ush6EQlvNOB9K8k11EPG2NZ/fyn0D +mNOs3gNm7irx2LB9bgdUCxCYIU2AyxIg58xP3kV9yXJ3MurKkLtpUhADL6jzlcXx +i2JWG+9nb6QQQZWtCpvjpcCw0nB2UDBbqOgILHztp6J6jTgpHKzH7fJ8lbCVgn1J +XDjNdyXvvYB1U5Q8PcpjW58VtdMdEy8Z0TzbdjrMuH3J5cLX2kBv2CHccxtCLVOc +/hr8fat6Nj+Y3oR8BWfOahQ4h6nxjLVoy2h/cSAr9aBj9VYvoybSt2+xWhfXOJkI +/pNYb/7DE0kIFgunTWcAUjFnI06Y7VFFHbkE2Qvs2CizS73tNnkCAwEAAaOB/DCB ++TAdBgNVHQ4EFgQUJ45nEXTDJh0/7TNjs6TYHTDl6NUwgckGA1UdIwSBwTCBvoAU +J45nEXTDJh0/7TNjs6TYHTDl6NWhgZqkgZcwgZQxCzAJBgNVBAYTAlVTMRAwDgYD +VQQIDAdNb250YW5hMRAwDgYDVQQHDAdCb3plbWFuMREwDwYDVQQKDAhTYXd0b290 +aDETMBEGA1UECwwKQ29uc3VsdGluZzEYMBYGA1UEAwwPd3d3LndvbGZzc2wuY29t +MR8wHQYJKoZIhvcNAQkBFhBpbmZvQHdvbGZzc2wuY29tggkA2YA6w9L02jcwDAYD +VR0TBAUwAwEB/zANBgkqhkiG9w0BAQsFAAOCAQEAeq9EO6pvU0KyM6pDX1Yw07mW +C5pVWjkqC07kLvGVZsmGNoKNY3xNou5IugPHkNenxnRgSF8xovlePsOC4eUvQYGD +KSV50VMAaTztCjA7QR2SoSyonSzjI4d54FVukahQ2kYvwiBQPitHlxSwfQS6RVHQ +buFaokuEnE3NhQT5KDGCk7zHWUmRA+jfauRWrWrLHw035F6955/V7J08GCWb8S9Q +fesxy/FjIp1X/POEIBrGB4eSJp4VGFkzBtz7sLZ2XfHBL8gvYpzA1t7rZXfzXKbD +iCeWdbT0VM3/LSEulvAHc0vpk5KQ3mLZozusbiRfJ0qzlHD/MBfnfjKPZbd1WA== +-----END CERTIFICATE----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/server-key.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/server-key.pem new file mode 100644 index 0000000..d1627f4 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/FreeRTOS_Plus_WolfSSL_Windows_Simulator/server-key.pem @@ -0,0 +1,27 @@ +-----BEGIN RSA PRIVATE KEY----- +MIIEpQIBAAKCAQEAwJUI4VdB8nFtt9JFQScBZcZFrvK8JDC4lc4vTtb2HIi8fJ/7 +qGd//lycUXX3isoH5zUvj+G9e8AvfKtkqBf8yl17uuAh5XIuby6G2JVz2qwbU7lf +P9cZDSVP4WNjUYsLZD+tQ7ilHFw0s64AoGPF9n8LWWh4c6aMGKkCba/DGQEuuBDj +xsxAtGmjRjNph27Euxem8+jdrXO8ey8htf1mUQy9VLPhbV8cvCNz0QkDiRTSELlk +wyrQoZZKvOHUGlvHoMDBY3gPRDcwMpaAMiOVoXe6E9KXc+JdJclqDcM5YKS0sGlC +Qgnp2Ai8MyCzWCKnquvE4eZhg8XSlt/Z0E+t1wIDAQABAoIBAQCa0DQPUmIFUAHv +n+1kbsLE2hryhNeSEEiSxOlq64t1bMZ5OPLJckqGZFSVd8vDmp231B2kAMieTuTd +x7pnFsF0vKnWlI8rMBr77d8hBSPZSjm9mGtlmrjcxH3upkMVLj2+HSJgKnMw1T7Y +oqyGQy7E9WReP4l1DxHYUSVOn9iqo85gs+KK2X4b8GTKmlsFC1uqy+XjP24yIgXz +0PrvdFKB4l90073/MYNFdfpjepcu1rYZxpIm5CgGUFAOeC6peA0Ul7QS2DFAq6EB +QcIw+AdfFuRhd9Jg8p+N6PS662PeKpeB70xs5lU0USsoNPRTHMRYCj+7r7X3SoVD +LTzxWFiBAoGBAPIsVHY5I2PJEDK3k62vvhl1loFk5rW4iUJB0W3QHBv4G6xpyzY8 +ZH3c9Bm4w2CxV0hfUk9ZOlV/MsAZQ1A/rs5vF/MOn0DKTq0VO8l56cBZOHNwnAp8 +yTpIMqfYSXUKhcLC/RVz2pkJKmmanwpxv7AEpox6Wm9IWlQ7xrFTF9/nAoGBAMuT +3ncVXbdcXHzYkKmYLdZpDmOzo9ymzItqpKISjI57SCyySzfcBhh96v52odSh6T8N +zRtfr1+elltbD6F8r7ObkNtXczrtsCNErkFPHwdCEyNMy/r0FKTV9542fFufqDzB +hV900jkt/9CE3/uzIHoumxeu5roLrl9TpFLtG8SRAoGBAOyY2rvV/vlSSn0CVUlv +VW5SL4SjK7OGYrNU0mNS2uOIdqDvixWl0xgUcndex6MEH54ZYrUbG57D8rUy+UzB +qusMJn3UX0pRXKRFBnBEp1bA1CIUdp7YY1CJkNPiv4GVkjFBhzkaQwsYpVMfORpf +H0O8h2rfbtMiAP4imHBOGhkpAoGBAIpBVihRnl/Ungs7mKNU8mxW1KrpaTOFJAza +1AwtxL9PAmk4fNTm3Ezt1xYRwz4A58MmwFEC3rt1nG9WnHrzju/PisUr0toGakTJ +c/5umYf4W77xfOZltU9s8MnF/xbKixsX4lg9ojerAby/QM5TjI7t7+5ZneBj5nxe +9Y5L8TvBAoGATUX5QIzFW/QqGoq08hysa+kMVja3TnKW1eWK0uL/8fEYEz2GCbjY +dqfJHHFSlDBD4PF4dP1hG0wJzOZoKnGtHN9DvFbbpaS+NXCkXs9P/ABVmTo9I89n +WvUi+LUp0EQR6zUuRr79jhiyX6i/GTKh9dwD5nyaHwx8qbAOITc78bA= +-----END RSA PRIVATE KEY----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/readme.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/readme.txt new file mode 100644 index 0000000..c64f142 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Demo/readme.txt @@ -0,0 +1,9 @@ +Directories: + ++ The FreeRTOS-Plus/Demo directory contains a demo application for every most of + the FreeRTOS+ components. Lots of the demo applications use the FreeRTOS + Windows simulator for easy evaluation. Be aware that FreeRTOS is much slower + and not deterministic when executed in a simulated environment. + ++ See http://www.freertos.org/plus + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI/FreeRTOS_CLI.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI/FreeRTOS_CLI.c new file mode 100644 index 0000000..a977015 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI/FreeRTOS_CLI.c @@ -0,0 +1,351 @@ +/* + * FreeRTOS+CLI V1.0.4 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Standard includes. */ +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Utils includes. */ +#include "FreeRTOS_CLI.h" + +/* If the application writer needs to place the buffer used by the CLI at a +fixed address then set configAPPLICATION_PROVIDES_cOutputBuffer to 1 in +FreeRTOSConfig.h, then declare an array with the following name and size in +one of the application files: + char cOutputBuffer[ configCOMMAND_INT_MAX_OUTPUT_SIZE ]; +*/ +#ifndef configAPPLICATION_PROVIDES_cOutputBuffer + #define configAPPLICATION_PROVIDES_cOutputBuffer 0 +#endif + +typedef struct xCOMMAND_INPUT_LIST +{ + const CLI_Command_Definition_t *pxCommandLineDefinition; + struct xCOMMAND_INPUT_LIST *pxNext; +} CLI_Definition_List_Item_t; + +/* + * The callback function that is executed when "help" is entered. This is the + * only default command that is always present. + */ +static BaseType_t prvHelpCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* + * Return the number of parameters that follow the command name. + */ +static int8_t prvGetNumberOfParameters( const char *pcCommandString ); + +/* The definition of the "help" command. This command is always at the front +of the list of registered commands. */ +static const CLI_Command_Definition_t xHelpCommand = +{ + "help", + "\r\nhelp:\r\n Lists all the registered commands\r\n\r\n", + prvHelpCommand, + 0 +}; + +/* The definition of the list of commands. Commands that are registered are +added to this list. */ +static CLI_Definition_List_Item_t xRegisteredCommands = +{ + &xHelpCommand, /* The first command in the list is always the help command, defined in this file. */ + NULL /* The next pointer is initialised to NULL, as there are no other registered commands yet. */ +}; + +/* A buffer into which command outputs can be written is declared here, rather +than in the command console implementation, to allow multiple command consoles +to share the same buffer. For example, an application may allow access to the +command interpreter by UART and by Ethernet. Sharing a buffer is done purely +to save RAM. Note, however, that the command console itself is not re-entrant, +so only one command interpreter interface can be used at any one time. For that +reason, no attempt at providing mutual exclusion to the cOutputBuffer array is +attempted. + +configAPPLICATION_PROVIDES_cOutputBuffer is provided to allow the application +writer to provide their own cOutputBuffer declaration in cases where the +buffer needs to be placed at a fixed address (rather than by the linker). */ +#if( configAPPLICATION_PROVIDES_cOutputBuffer == 0 ) + static char cOutputBuffer[ configCOMMAND_INT_MAX_OUTPUT_SIZE ]; +#else + extern char cOutputBuffer[ configCOMMAND_INT_MAX_OUTPUT_SIZE ]; +#endif + + +/*-----------------------------------------------------------*/ + +BaseType_t FreeRTOS_CLIRegisterCommand( const CLI_Command_Definition_t * const pxCommandToRegister ) +{ +static CLI_Definition_List_Item_t *pxLastCommandInList = &xRegisteredCommands; +CLI_Definition_List_Item_t *pxNewListItem; +BaseType_t xReturn = pdFAIL; + + /* Check the parameter is not NULL. */ + configASSERT( pxCommandToRegister ); + + /* Create a new list item that will reference the command being registered. */ + pxNewListItem = ( CLI_Definition_List_Item_t * ) pvPortMalloc( sizeof( CLI_Definition_List_Item_t ) ); + configASSERT( pxNewListItem ); + + if( pxNewListItem != NULL ) + { + taskENTER_CRITICAL(); + { + /* Reference the command being registered from the newly created + list item. */ + pxNewListItem->pxCommandLineDefinition = pxCommandToRegister; + + /* The new list item will get added to the end of the list, so + pxNext has nowhere to point. */ + pxNewListItem->pxNext = NULL; + + /* Add the newly created list item to the end of the already existing + list. */ + pxLastCommandInList->pxNext = pxNewListItem; + + /* Set the end of list marker to the new list item. */ + pxLastCommandInList = pxNewListItem; + } + taskEXIT_CRITICAL(); + + xReturn = pdPASS; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t FreeRTOS_CLIProcessCommand( const char * const pcCommandInput, char * pcWriteBuffer, size_t xWriteBufferLen ) +{ +static const CLI_Definition_List_Item_t *pxCommand = NULL; +BaseType_t xReturn = pdTRUE; +const char *pcRegisteredCommandString; +size_t xCommandStringLength; + + /* Note: This function is not re-entrant. It must not be called from more + thank one task. */ + + if( pxCommand == NULL ) + { + /* Search for the command string in the list of registered commands. */ + for( pxCommand = &xRegisteredCommands; pxCommand != NULL; pxCommand = pxCommand->pxNext ) + { + pcRegisteredCommandString = pxCommand->pxCommandLineDefinition->pcCommand; + xCommandStringLength = strlen( pcRegisteredCommandString ); + + /* To ensure the string lengths match exactly, so as not to pick up + a sub-string of a longer command, check the byte after the expected + end of the string is either the end of the string or a space before + a parameter. */ + if( ( pcCommandInput[ xCommandStringLength ] == ' ' ) || ( pcCommandInput[ xCommandStringLength ] == 0x00 ) ) + { + if( strncmp( pcCommandInput, pcRegisteredCommandString, xCommandStringLength ) == 0 ) + { + /* The command has been found. Check it has the expected + number of parameters. If cExpectedNumberOfParameters is -1, + then there could be a variable number of parameters and no + check is made. */ + if( pxCommand->pxCommandLineDefinition->cExpectedNumberOfParameters >= 0 ) + { + if( prvGetNumberOfParameters( pcCommandInput ) != pxCommand->pxCommandLineDefinition->cExpectedNumberOfParameters ) + { + xReturn = pdFALSE; + } + } + + break; + } + } + } + } + + if( ( pxCommand != NULL ) && ( xReturn == pdFALSE ) ) + { + /* The command was found, but the number of parameters with the command + was incorrect. */ + strncpy( pcWriteBuffer, "Incorrect command parameter(s). Enter \"help\" to view a list of available commands.\r\n\r\n", xWriteBufferLen ); + pxCommand = NULL; + } + else if( pxCommand != NULL ) + { + /* Call the callback function that is registered to this command. */ + xReturn = pxCommand->pxCommandLineDefinition->pxCommandInterpreter( pcWriteBuffer, xWriteBufferLen, pcCommandInput ); + + /* If xReturn is pdFALSE, then no further strings will be returned + after this one, and pxCommand can be reset to NULL ready to search + for the next entered command. */ + if( xReturn == pdFALSE ) + { + pxCommand = NULL; + } + } + else + { + /* pxCommand was NULL, the command was not found. */ + strncpy( pcWriteBuffer, "Command not recognised. Enter 'help' to view a list of available commands.\r\n\r\n", xWriteBufferLen ); + xReturn = pdFALSE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +char *FreeRTOS_CLIGetOutputBuffer( void ) +{ + return cOutputBuffer; +} +/*-----------------------------------------------------------*/ + +const char *FreeRTOS_CLIGetParameter( const char *pcCommandString, UBaseType_t uxWantedParameter, BaseType_t *pxParameterStringLength ) +{ +UBaseType_t uxParametersFound = 0; +const char *pcReturn = NULL; + + *pxParameterStringLength = 0; + + while( uxParametersFound < uxWantedParameter ) + { + /* Index the character pointer past the current word. If this is the start + of the command string then the first word is the command itself. */ + while( ( ( *pcCommandString ) != 0x00 ) && ( ( *pcCommandString ) != ' ' ) ) + { + pcCommandString++; + } + + /* Find the start of the next string. */ + while( ( ( *pcCommandString ) != 0x00 ) && ( ( *pcCommandString ) == ' ' ) ) + { + pcCommandString++; + } + + /* Was a string found? */ + if( *pcCommandString != 0x00 ) + { + /* Is this the start of the required parameter? */ + uxParametersFound++; + + if( uxParametersFound == uxWantedParameter ) + { + /* How long is the parameter? */ + pcReturn = pcCommandString; + while( ( ( *pcCommandString ) != 0x00 ) && ( ( *pcCommandString ) != ' ' ) ) + { + ( *pxParameterStringLength )++; + pcCommandString++; + } + + if( *pxParameterStringLength == 0 ) + { + pcReturn = NULL; + } + + break; + } + } + else + { + break; + } + } + + return pcReturn; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvHelpCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ) +{ +static const CLI_Definition_List_Item_t * pxCommand = NULL; +BaseType_t xReturn; + + ( void ) pcCommandString; + + if( pxCommand == NULL ) + { + /* Reset the pxCommand pointer back to the start of the list. */ + pxCommand = &xRegisteredCommands; + } + + /* Return the next command help string, before moving the pointer on to + the next command in the list. */ + strncpy( pcWriteBuffer, pxCommand->pxCommandLineDefinition->pcHelpString, xWriteBufferLen ); + pxCommand = pxCommand->pxNext; + + if( pxCommand == NULL ) + { + /* There are no more commands in the list, so there will be no more + strings to return after this one and pdFALSE should be returned. */ + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static int8_t prvGetNumberOfParameters( const char *pcCommandString ) +{ +int8_t cParameters = 0; +BaseType_t xLastCharacterWasSpace = pdFALSE; + + /* Count the number of space delimited words in pcCommandString. */ + while( *pcCommandString != 0x00 ) + { + if( ( *pcCommandString ) == ' ' ) + { + if( xLastCharacterWasSpace != pdTRUE ) + { + cParameters++; + xLastCharacterWasSpace = pdTRUE; + } + } + else + { + xLastCharacterWasSpace = pdFALSE; + } + + pcCommandString++; + } + + /* If the command string ended with spaces, then there will have been too + many parameters counted. */ + if( xLastCharacterWasSpace == pdTRUE ) + { + cParameters--; + } + + /* The value returned is one less than the number of space delimited words, + as the first word should be the command itself. */ + return cParameters; +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI/FreeRTOS_CLI.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI/FreeRTOS_CLI.h new file mode 100644 index 0000000..12fdd70 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI/FreeRTOS_CLI.h @@ -0,0 +1,105 @@ +/* + * FreeRTOS+CLI V1.0.4 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef COMMAND_INTERPRETER_H +#define COMMAND_INTERPRETER_H + +/* The prototype to which callback functions used to process command line +commands must comply. pcWriteBuffer is a buffer into which the output from +executing the command can be written, xWriteBufferLen is the length, in bytes of +the pcWriteBuffer buffer, and pcCommandString is the entire string as input by +the user (from which parameters can be extracted).*/ +typedef BaseType_t (*pdCOMMAND_LINE_CALLBACK)( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString ); + +/* The structure that defines command line commands. A command line command +should be defined by declaring a const structure of this type. */ +typedef struct xCOMMAND_LINE_INPUT +{ + const char * const pcCommand; /* The command that causes pxCommandInterpreter to be executed. For example "help". Must be all lower case. */ + const char * const pcHelpString; /* String that describes how to use the command. Should start with the command itself, and end with "\r\n". For example "help: Returns a list of all the commands\r\n". */ + const pdCOMMAND_LINE_CALLBACK pxCommandInterpreter; /* A pointer to the callback function that will return the output generated by the command. */ + int8_t cExpectedNumberOfParameters; /* Commands expect a fixed number of parameters, which may be zero. */ +} CLI_Command_Definition_t; + +/* For backward compatibility. */ +#define xCommandLineInput CLI_Command_Definition_t + +/* + * Register the command passed in using the pxCommandToRegister parameter. + * Registering a command adds the command to the list of commands that are + * handled by the command interpreter. Once a command has been registered it + * can be executed from the command line. + */ +BaseType_t FreeRTOS_CLIRegisterCommand( const CLI_Command_Definition_t * const pxCommandToRegister ); + +/* + * Runs the command interpreter for the command string "pcCommandInput". Any + * output generated by running the command will be placed into pcWriteBuffer. + * xWriteBufferLen must indicate the size, in bytes, of the buffer pointed to + * by pcWriteBuffer. + * + * FreeRTOS_CLIProcessCommand should be called repeatedly until it returns pdFALSE. + * + * pcCmdIntProcessCommand is not reentrant. It must not be called from more + * than one task - or at least - by more than one task at a time. + */ +BaseType_t FreeRTOS_CLIProcessCommand( const char * const pcCommandInput, char * pcWriteBuffer, size_t xWriteBufferLen ); + +/*-----------------------------------------------------------*/ + +/* + * A buffer into which command outputs can be written is declared in the + * main command interpreter, rather than in the command console implementation, + * to allow application that provide access to the command console via multiple + * interfaces to share a buffer, and therefore save RAM. Note, however, that + * the command interpreter itself is not re-entrant, so only one command + * console interface can be used at any one time. For that reason, no attempt + * is made to provide any mutual exclusion mechanism on the output buffer. + * + * FreeRTOS_CLIGetOutputBuffer() returns the address of the output buffer. + */ +char *FreeRTOS_CLIGetOutputBuffer( void ); + +/* + * Return a pointer to the xParameterNumber'th word in pcCommandString. + */ +const char *FreeRTOS_CLIGetParameter( const char *pcCommandString, UBaseType_t uxWantedParameter, BaseType_t *pxParameterStringLength ); + +#endif /* COMMAND_INTERPRETER_H */ + + + + + + + + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI/History.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI/History.txt new file mode 100644 index 0000000..8c62cf9 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI/History.txt @@ -0,0 +1,32 @@ +Changes between V1.0.3 and V1.0.4 released + + + Update to use stdint and the FreeRTOS specific typedefs that were + introduced in FreeRTOS V8.0.0. + +Changes between V1.0.2 and V1.0.3 released + + + Previously, and in line with good software engineering practice, the + FreeRTOS coding standard did not permit the use of char types that were + not explicitly qualified as either signed or unsigned. As a result char + pointers used to reference strings required casts, as did the use of any + standard string handling functions. The casts ensured compiler warnings + were not generated by compilers that defaulted unqualified char types to + be signed or compilers that defaulted unqualified char types to be + unsigned. As it has in later MISRA standards, this rule has now been + relaxed, and unqualified char types are now permitted, but only when: + 1) The char is used to point to a human readable text string. + 2) The char is used to hold a single ASCII character. + +Changes between V1.0.1 and V1.0.2 released 14/10/2013 + + + Changed double quotes (") to single quotes (') in the help string to + allow the strings to be used with JSON in FreeRTOS+Nabto. + +Changes between V1.0.0 and V1.0.1 released 05/07/2012 + + + Change the name of the structure used to map a function that implements + a CLI command to the string used to call the command from + xCommandLineInput to CLI_Command_Definition_t, as it was always intended + to be. A #define was added to map the old name to the new name for + reasons of backward compatibility. + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI/LICENSE_INFORMATION.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI/LICENSE_INFORMATION.txt new file mode 100644 index 0000000..6812e27 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI/LICENSE_INFORMATION.txt @@ -0,0 +1,19 @@ +FreeRTOS+CLI is released under the following MIT license. + +Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI/ReadMe.url b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI/ReadMe.url new file mode 100644 index 0000000..3a76266 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI/ReadMe.url @@ -0,0 +1,5 @@ +[InternetShortcut] +URL=http://www.freertos.org/cli +IDList= +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI/readme.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI/readme.txt new file mode 100644 index 0000000..0f61b02 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI/readme.txt @@ -0,0 +1,4 @@ +Contains source and header files that implement FreeRTOS+CLI. See +http://www.FreeRTOS.org/cli for documentation and license information. + + \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-IO/LinkToDemo.url b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-IO/LinkToDemo.url new file mode 100644 index 0000000..e803bf2 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-IO/LinkToDemo.url @@ -0,0 +1,5 @@ +[InternetShortcut] +URL=http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_IO/Demo_Applications/LPCXpresso_LPC1769/NXP_LPC1769_Demo_Description.shtml +IDList= +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-IO/readme.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-IO/readme.txt new file mode 100644 index 0000000..f5c8d2f --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-IO/readme.txt @@ -0,0 +1,7 @@ +It is not possible to create an example FreeRTOS+IO project for the Windows +simulator. FreeRTOS+IO information can be found on http://www.FreeRTOS.org/IO. + +A featured demo that includes telnet like functionality, a web server, +a command line interface (using FreeRTOS+CLI) and a FAT file system is +described on +http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_IO/Demo_Applications/LPCXpresso_LPC1769/NXP_LPC1769_Demo_Description.shtml \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_ARP.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_ARP.c new file mode 100644 index 0000000..ed34d9a --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_ARP.c @@ -0,0 +1,653 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +/* Standard includes. */ +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_IP_Private.h" +#include "FreeRTOS_ARP.h" +#include "FreeRTOS_UDP_IP.h" +#include "FreeRTOS_DHCP.h" +#if( ipconfigUSE_LLMNR == 1 ) + #include "FreeRTOS_DNS.h" +#endif /* ipconfigUSE_LLMNR */ +#include "NetworkInterface.h" +#include "NetworkBufferManagement.h" + + +/* When the age of an entry in the ARP table reaches this value (it counts down +to zero, so this is an old entry) an ARP request will be sent to see if the +entry is still valid and can therefore be refreshed. */ +#define arpMAX_ARP_AGE_BEFORE_NEW_ARP_REQUEST ( 3 ) + +/* The time between gratuitous ARPs. */ +#ifndef arpGRATUITOUS_ARP_PERIOD + #define arpGRATUITOUS_ARP_PERIOD ( pdMS_TO_TICKS( 20000 ) ) +#endif + +/*-----------------------------------------------------------*/ + +/* + * Lookup an MAC address in the ARP cache from the IP address. + */ +static eARPLookupResult_t prvCacheLookup( uint32_t ulAddressToLookup, MACAddress_t * const pxMACAddress ); + +/*-----------------------------------------------------------*/ + +/* The ARP cache. */ +static ARPCacheRow_t xARPCache[ ipconfigARP_CACHE_ENTRIES ]; + +/* The time at which the last gratuitous ARP was sent. Gratuitous ARPs are used +to ensure ARP tables are up to date and to detect IP address conflicts. */ +static TickType_t xLastGratuitousARPTime = ( TickType_t ) 0; + +/* + * IP-clash detection is currently only used internally. When DHCP doesn't respond, the + * driver can try out a random LinkLayer IP address (169.254.x.x). It will send out a + * gratuitos ARP message and, after a period of time, check the variables here below: + */ +#if( ipconfigARP_USE_CLASH_DETECTION != 0 ) + /* Becomes non-zero if another device responded to a gratuitos ARP message. */ + BaseType_t xARPHadIPClash; + /* MAC-address of the other device containing the same IP-address. */ + MACAddress_t xARPClashMacAddress; +#endif /* ipconfigARP_USE_CLASH_DETECTION */ + +/* Part of the Ethernet and ARP headers are always constant when sending an IPv4 +ARP packet. This array defines the constant parts, allowing this part of the +packet to be filled in using a simple memcpy() instead of individual writes. */ +static const uint8_t xDefaultPartARPPacketHeader[] = +{ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* Ethernet destination address. */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* Ethernet source address. */ + 0x08, 0x06, /* Ethernet frame type (ipARP_FRAME_TYPE). */ + 0x00, 0x01, /* usHardwareType (ipARP_HARDWARE_TYPE_ETHERNET). */ + 0x08, 0x00, /* usProtocolType. */ + ipMAC_ADDRESS_LENGTH_BYTES, /* ucHardwareAddressLength. */ + ipIP_ADDRESS_LENGTH_BYTES, /* ucProtocolAddressLength. */ + 0x00, 0x01, /* usOperation (ipARP_REQUEST). */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* xSenderHardwareAddress. */ + 0x00, 0x00, 0x00, 0x00, /* ulSenderProtocolAddress. */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* xTargetHardwareAddress. */ +}; + +/*-----------------------------------------------------------*/ + +eFrameProcessingResult_t eARPProcessPacket( ARPPacket_t * const pxARPFrame ) +{ +eFrameProcessingResult_t eReturn = eReleaseBuffer; +ARPHeader_t *pxARPHeader; +uint32_t ulTargetProtocolAddress, ulSenderProtocolAddress; + + pxARPHeader = &( pxARPFrame->xARPHeader ); + + /* The field ulSenderProtocolAddress is badly aligned, copy byte-by-byte. */ + memcpy( ( void *)&( ulSenderProtocolAddress ), ( void * )pxARPHeader->ucSenderProtocolAddress, sizeof( ulSenderProtocolAddress ) ); + /* The field ulTargetProtocolAddress is well-aligned, a 32-bits copy. */ + ulTargetProtocolAddress = pxARPHeader->ulTargetProtocolAddress; + + traceARP_PACKET_RECEIVED(); + + /* Don't do anything if the local IP address is zero because + that means a DHCP request has not completed. */ + if( *ipLOCAL_IP_ADDRESS_POINTER != 0UL ) + { + switch( pxARPHeader->usOperation ) + { + case ipARP_REQUEST : + /* The packet contained an ARP request. Was it for the IP + address of the node running this code? */ + if( ulTargetProtocolAddress == *ipLOCAL_IP_ADDRESS_POINTER ) + { + iptraceSENDING_ARP_REPLY( ulSenderProtocolAddress ); + + /* The request is for the address of this node. Add the + entry into the ARP cache, or refresh the entry if it + already exists. */ + vARPRefreshCacheEntry( &( pxARPHeader->xSenderHardwareAddress ), ulSenderProtocolAddress ); + + /* Generate a reply payload in the same buffer. */ + pxARPHeader->usOperation = ( uint16_t ) ipARP_REPLY; + if( ulTargetProtocolAddress == ulSenderProtocolAddress ) + { + /* A double IP address is detected! */ + /* Give the sources MAC address the value of the broadcast address, will be swapped later */ + memcpy( pxARPFrame->xEthernetHeader.xSourceAddress.ucBytes, xBroadcastMACAddress.ucBytes, sizeof( xBroadcastMACAddress ) ); + memset( pxARPHeader->xTargetHardwareAddress.ucBytes, '\0', sizeof( MACAddress_t ) ); + pxARPHeader->ulTargetProtocolAddress = 0UL; + } + else + { + memcpy( pxARPHeader->xTargetHardwareAddress.ucBytes, pxARPHeader->xSenderHardwareAddress.ucBytes, sizeof( MACAddress_t ) ); + pxARPHeader->ulTargetProtocolAddress = ulSenderProtocolAddress; + } + memcpy( pxARPHeader->xSenderHardwareAddress.ucBytes, ( void * ) ipLOCAL_MAC_ADDRESS, sizeof( MACAddress_t ) ); + memcpy( ( void* )pxARPHeader->ucSenderProtocolAddress, ( void* )ipLOCAL_IP_ADDRESS_POINTER, sizeof( pxARPHeader->ucSenderProtocolAddress ) ); + + eReturn = eReturnEthernetFrame; + } + break; + + case ipARP_REPLY : + iptracePROCESSING_RECEIVED_ARP_REPLY( ulTargetProtocolAddress ); + vARPRefreshCacheEntry( &( pxARPHeader->xSenderHardwareAddress ), ulSenderProtocolAddress ); + /* Process received ARP frame to see if there is a clash. */ + #if( ipconfigARP_USE_CLASH_DETECTION != 0 ) + { + if( ulSenderProtocolAddress == *ipLOCAL_IP_ADDRESS_POINTER ) + { + xARPHadIPClash = pdTRUE; + memcpy( xARPClashMacAddress.ucBytes, pxARPHeader->xSenderHardwareAddress.ucBytes, sizeof( xARPClashMacAddress.ucBytes ) ); + } + } + #endif /* ipconfigARP_USE_CLASH_DETECTION */ + break; + + default : + /* Invalid. */ + break; + } + } + + return eReturn; +} +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_ARP_REMOVE_ENTRY != 0 ) + + uint32_t ulARPRemoveCacheEntryByMac( const MACAddress_t * pxMACAddress ) + { + BaseType_t x; + uint32_t lResult = 0; + + /* For each entry in the ARP cache table. */ + for( x = 0; x < ipconfigARP_CACHE_ENTRIES; x++ ) + { + if( ( memcmp( xARPCache[ x ].xMACAddress.ucBytes, pxMACAddress->ucBytes, sizeof( pxMACAddress->ucBytes ) ) == 0 ) ) + { + lResult = xARPCache[ x ].ulIPAddress; + memset( &xARPCache[ x ], '\0', sizeof( xARPCache[ x ] ) ); + break; + } + } + + return lResult; + } + +#endif /* ipconfigUSE_ARP_REMOVE_ENTRY != 0 */ +/*-----------------------------------------------------------*/ + +void vARPRefreshCacheEntry( const MACAddress_t * pxMACAddress, const uint32_t ulIPAddress ) +{ +BaseType_t x = 0; +BaseType_t xIpEntry = -1; +BaseType_t xMacEntry = -1; +BaseType_t xUseEntry = 0; +uint8_t ucMinAgeFound = 0U; + + #if( ipconfigARP_STORES_REMOTE_ADDRESSES == 0 ) + /* Only process the IP address if it is on the local network. + Unless: when '*ipLOCAL_IP_ADDRESS_POINTER' equals zero, the IP-address + and netmask are still unknown. */ + if( ( ( ulIPAddress & xNetworkAddressing.ulNetMask ) == ( ( *ipLOCAL_IP_ADDRESS_POINTER ) & xNetworkAddressing.ulNetMask ) ) || + ( *ipLOCAL_IP_ADDRESS_POINTER == 0ul ) ) + #else + /* If ipconfigARP_STORES_REMOTE_ADDRESSES is non-zero, IP addresses with + a different netmask will also be stored. After when replying to a UDP + message from a different netmask, the IP address can be looped up and a + reply sent. This option is useful for systems with multiple gateways, + the reply will surely arrive. If ipconfigARP_STORES_REMOTE_ADDRESSES is + zero the the gateway address is the only option. */ + if( pdTRUE ) + #endif + { + /* Start with the maximum possible number. */ + ucMinAgeFound--; + + /* For each entry in the ARP cache table. */ + for( x = 0; x < ipconfigARP_CACHE_ENTRIES; x++ ) + { + /* Does this line in the cache table hold an entry for the IP + address being queried? */ + if( xARPCache[ x ].ulIPAddress == ulIPAddress ) + { + if( pxMACAddress == NULL ) + { + /* In case the parameter pxMACAddress is NULL, an entry will be reserved to + indicate that there is an outstanding ARP request, This entry will have + "ucValid == pdFALSE". */ + xIpEntry = x; + break; + } + + /* See if the MAC-address also matches. */ + if( memcmp( xARPCache[ x ].xMACAddress.ucBytes, pxMACAddress->ucBytes, sizeof( pxMACAddress->ucBytes ) ) == 0 ) + { + /* This function will be called for each received packet + As this is by far the most common path the coding standard + is relaxed in this case and a return is permitted as an + optimisation. */ + xARPCache[ x ].ucAge = ( uint8_t ) ipconfigMAX_ARP_AGE; + xARPCache[ x ].ucValid = ( uint8_t ) pdTRUE; + return; + } + + /* Found an entry containing ulIPAddress, but the MAC address + doesn't match. Might be an entry with ucValid=pdFALSE, waiting + for an ARP reply. Still want to see if there is match with the + given MAC address.ucBytes. If found, either of the two entries + must be cleared. */ + xIpEntry = x; + } + else if( ( pxMACAddress != NULL ) && ( memcmp( xARPCache[ x ].xMACAddress.ucBytes, pxMACAddress->ucBytes, sizeof( pxMACAddress->ucBytes ) ) == 0 ) ) + { + /* Found an entry with the given MAC-address, but the IP-address + is different. Continue looping to find a possible match with + ulIPAddress. */ + #if( ipconfigARP_STORES_REMOTE_ADDRESSES != 0 ) + /* If ARP stores the MAC address of IP addresses outside the + network, than the MAC address of the gateway should not be + overwritten. */ + BaseType_t bIsLocal[ 2 ]; + bIsLocal[ 0 ] = ( ( xARPCache[ x ].ulIPAddress & xNetworkAddressing.ulNetMask ) == ( ( *ipLOCAL_IP_ADDRESS_POINTER ) & xNetworkAddressing.ulNetMask ) ); + bIsLocal[ 1 ] = ( ( ulIPAddress & xNetworkAddressing.ulNetMask ) == ( ( *ipLOCAL_IP_ADDRESS_POINTER ) & xNetworkAddressing.ulNetMask ) ); + if( bIsLocal[ 0 ] == bIsLocal[ 1 ] ) + { + xMacEntry = x; + } + #else + xMacEntry = x; + #endif + } + /* _HT_ + Shouldn't we test for xARPCache[ x ].ucValid == pdFALSE here ? */ + else if( xARPCache[ x ].ucAge < ucMinAgeFound ) + { + /* As the table is traversed, remember the table row that + contains the oldest entry (the lowest age count, as ages are + decremented to zero) so the row can be re-used if this function + needs to add an entry that does not already exist. */ + ucMinAgeFound = xARPCache[ x ].ucAge; + xUseEntry = x; + } + } + + if( xMacEntry >= 0 ) + { + xUseEntry = xMacEntry; + + if( xIpEntry >= 0 ) + { + /* Both the MAC address as well as the IP address were found in + different locations: clear the entry which matches the + IP-address */ + memset( &xARPCache[ xIpEntry ], '\0', sizeof( xARPCache[ xIpEntry ] ) ); + } + } + else if( xIpEntry >= 0 ) + { + /* An entry containing the IP-address was found, but it had a different MAC address */ + xUseEntry = xIpEntry; + } + + /* If the entry was not found, we use the oldest entry and set the IPaddress */ + xARPCache[ xUseEntry ].ulIPAddress = ulIPAddress; + + if( pxMACAddress != NULL ) + { + memcpy( xARPCache[ xUseEntry ].xMACAddress.ucBytes, pxMACAddress->ucBytes, sizeof( pxMACAddress->ucBytes ) ); + + iptraceARP_TABLE_ENTRY_CREATED( ulIPAddress, (*pxMACAddress) ); + /* And this entry does not need immediate attention */ + xARPCache[ xUseEntry ].ucAge = ( uint8_t ) ipconfigMAX_ARP_AGE; + xARPCache[ xUseEntry ].ucValid = ( uint8_t ) pdTRUE; + } + else if( xIpEntry < 0 ) + { + xARPCache[ xUseEntry ].ucAge = ( uint8_t ) ipconfigMAX_ARP_RETRANSMISSIONS; + xARPCache[ xUseEntry ].ucValid = ( uint8_t ) pdFALSE; + } + } +} +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_ARP_REVERSED_LOOKUP == 1 ) + eARPLookupResult_t eARPGetCacheEntryByMac( MACAddress_t * const pxMACAddress, uint32_t *pulIPAddress ) + { + BaseType_t x; + eARPLookupResult_t eReturn = eARPCacheMiss; + + /* Loop through each entry in the ARP cache. */ + for( x = 0; x < ipconfigARP_CACHE_ENTRIES; x++ ) + { + /* Does this row in the ARP cache table hold an entry for the MAC + address being searched? */ + if( memcmp( pxMACAddress->ucBytes, xARPCache[ x ].xMACAddress.ucBytes, sizeof( MACAddress_t ) ) == 0 ) + { + *pulIPAddress = xARPCache[ x ].ulIPAddress; + eReturn = eARPCacheHit; + break; + } + } + + return eReturn; + } +#endif /* ipconfigUSE_ARP_REVERSED_LOOKUP */ + +/*-----------------------------------------------------------*/ + +eARPLookupResult_t eARPGetCacheEntry( uint32_t *pulIPAddress, MACAddress_t * const pxMACAddress ) +{ +eARPLookupResult_t eReturn; +uint32_t ulAddressToLookup; + +#if( ipconfigUSE_LLMNR == 1 ) + if( *pulIPAddress == ipLLMNR_IP_ADDR ) /* Is in network byte order. */ + { + /* The LLMNR IP-address has a fixed virtual MAC address. */ + memcpy( pxMACAddress->ucBytes, xLLMNR_MacAdress.ucBytes, sizeof( MACAddress_t ) ); + eReturn = eARPCacheHit; + } + else +#endif + if( ( *pulIPAddress == ipBROADCAST_IP_ADDRESS ) || /* Is it the general broadcast address 255.255.255.255? */ + ( *pulIPAddress == xNetworkAddressing.ulBroadcastAddress ) )/* Or a local broadcast address, eg 192.168.1.255? */ + { + /* This is a broadcast so uses the broadcast MAC address. */ + memcpy( pxMACAddress->ucBytes, xBroadcastMACAddress.ucBytes, sizeof( MACAddress_t ) ); + eReturn = eARPCacheHit; + } + else if( *ipLOCAL_IP_ADDRESS_POINTER == 0UL ) + { + /* The IP address has not yet been assigned, so there is nothing that + can be done. */ + eReturn = eCantSendPacket; + } + else + { + eReturn = eARPCacheMiss; + + if( ( *pulIPAddress & xNetworkAddressing.ulNetMask ) != ( ( *ipLOCAL_IP_ADDRESS_POINTER ) & xNetworkAddressing.ulNetMask ) ) + { +#if( ipconfigARP_STORES_REMOTE_ADDRESSES == 1 ) + eReturn = prvCacheLookup( *pulIPAddress, pxMACAddress ); + + if( eReturn == eARPCacheHit ) + { + /* The stack is configured to store 'remote IP addresses', i.e. addresses + belonging to a different the netmask. prvCacheLookup() returned a hit, so + the MAC address is known */ + } + else +#endif + { + /* The IP address is off the local network, so look up the + hardware address of the router, if any. */ + if( xNetworkAddressing.ulGatewayAddress != ( uint32_t )0u ) + { + ulAddressToLookup = xNetworkAddressing.ulGatewayAddress; + } + else + { + ulAddressToLookup = *pulIPAddress; + } + } + } + else + { + /* The IP address is on the local network, so lookup the requested + IP address directly. */ + ulAddressToLookup = *pulIPAddress; + } + + if( eReturn == eARPCacheMiss ) + { + if( ulAddressToLookup == 0UL ) + { + /* The address is not on the local network, and there is not a + router. */ + eReturn = eCantSendPacket; + } + else + { + eReturn = prvCacheLookup( ulAddressToLookup, pxMACAddress ); + + if( eReturn == eARPCacheMiss ) + { + /* It might be that the ARP has to go to the gateway. */ + *pulIPAddress = ulAddressToLookup; + } + } + } + } + + return eReturn; +} + +/*-----------------------------------------------------------*/ + +static eARPLookupResult_t prvCacheLookup( uint32_t ulAddressToLookup, MACAddress_t * const pxMACAddress ) +{ +BaseType_t x; +eARPLookupResult_t eReturn = eARPCacheMiss; + + /* Loop through each entry in the ARP cache. */ + for( x = 0; x < ipconfigARP_CACHE_ENTRIES; x++ ) + { + /* Does this row in the ARP cache table hold an entry for the IP address + being queried? */ + if( xARPCache[ x ].ulIPAddress == ulAddressToLookup ) + { + /* A matching valid entry was found. */ + if( xARPCache[ x ].ucValid == ( uint8_t ) pdFALSE ) + { + /* This entry is waiting an ARP reply, so is not valid. */ + eReturn = eCantSendPacket; + } + else + { + /* A valid entry was found. */ + memcpy( pxMACAddress->ucBytes, xARPCache[ x ].xMACAddress.ucBytes, sizeof( MACAddress_t ) ); + eReturn = eARPCacheHit; + } + break; + } + } + + return eReturn; +} +/*-----------------------------------------------------------*/ + +void vARPAgeCache( void ) +{ +BaseType_t x; +TickType_t xTimeNow; + + /* Loop through each entry in the ARP cache. */ + for( x = 0; x < ipconfigARP_CACHE_ENTRIES; x++ ) + { + /* If the entry is valid (its age is greater than zero). */ + if( xARPCache[ x ].ucAge > 0U ) + { + /* Decrement the age value of the entry in this ARP cache table row. + When the age reaches zero it is no longer considered valid. */ + ( xARPCache[ x ].ucAge )--; + + /* If the entry is not yet valid, then it is waiting an ARP + reply, and the ARP request should be retransmitted. */ + if( xARPCache[ x ].ucValid == ( uint8_t ) pdFALSE ) + { + FreeRTOS_OutputARPRequest( xARPCache[ x ].ulIPAddress ); + } + else if( xARPCache[ x ].ucAge <= ( uint8_t ) arpMAX_ARP_AGE_BEFORE_NEW_ARP_REQUEST ) + { + /* This entry will get removed soon. See if the MAC address is + still valid to prevent this happening. */ + iptraceARP_TABLE_ENTRY_WILL_EXPIRE( xARPCache[ x ].ulIPAddress ); + FreeRTOS_OutputARPRequest( xARPCache[ x ].ulIPAddress ); + } + else + { + /* The age has just ticked down, with nothing to do. */ + } + + if( xARPCache[ x ].ucAge == 0u ) + { + /* The entry is no longer valid. Wipe it out. */ + iptraceARP_TABLE_ENTRY_EXPIRED( xARPCache[ x ].ulIPAddress ); + xARPCache[ x ].ulIPAddress = 0UL; + } + } + } + + xTimeNow = xTaskGetTickCount (); + + if( ( xLastGratuitousARPTime == ( TickType_t ) 0 ) || ( ( xTimeNow - xLastGratuitousARPTime ) > ( TickType_t ) arpGRATUITOUS_ARP_PERIOD ) ) + { + FreeRTOS_OutputARPRequest( *ipLOCAL_IP_ADDRESS_POINTER ); + xLastGratuitousARPTime = xTimeNow; + } +} +/*-----------------------------------------------------------*/ + +void vARPSendGratuitous( void ) +{ + /* Setting xLastGratuitousARPTime to 0 will force a gratuitous ARP the next + time vARPAgeCache() is called. */ + xLastGratuitousARPTime = ( TickType_t ) 0; + + /* Let the IP-task call vARPAgeCache(). */ + xSendEventToIPTask( eARPTimerEvent ); +} + +/*-----------------------------------------------------------*/ +void FreeRTOS_OutputARPRequest( uint32_t ulIPAddress ) +{ +NetworkBufferDescriptor_t *pxNetworkBuffer; + + /* This is called from the context of the IP event task, so a block time + must not be used. */ + pxNetworkBuffer = pxGetNetworkBufferWithDescriptor( sizeof( ARPPacket_t ), ( TickType_t ) 0 ); + + if( pxNetworkBuffer != NULL ) + { + pxNetworkBuffer->ulIPAddress = ulIPAddress; + vARPGenerateRequestPacket( pxNetworkBuffer ); + + #if defined( ipconfigETHERNET_MINIMUM_PACKET_BYTES ) + { + if( pxNetworkBuffer->xDataLength < ( size_t ) ipconfigETHERNET_MINIMUM_PACKET_BYTES ) + { + BaseType_t xIndex; + + for( xIndex = ( BaseType_t ) pxNetworkBuffer->xDataLength; xIndex < ( BaseType_t ) ipconfigETHERNET_MINIMUM_PACKET_BYTES; xIndex++ ) + { + pxNetworkBuffer->pucEthernetBuffer[ xIndex ] = 0u; + } + pxNetworkBuffer->xDataLength = ( size_t ) ipconfigETHERNET_MINIMUM_PACKET_BYTES; + } + } + #endif + + xNetworkInterfaceOutput( pxNetworkBuffer, pdTRUE ); + } +} + +void vARPGenerateRequestPacket( NetworkBufferDescriptor_t * const pxNetworkBuffer ) +{ +ARPPacket_t *pxARPPacket; + + pxARPPacket = ( ARPPacket_t * ) pxNetworkBuffer->pucEthernetBuffer; + + /* memcpy the const part of the header information into the correct + location in the packet. This copies: + xEthernetHeader.ulDestinationAddress + xEthernetHeader.usFrameType; + xARPHeader.usHardwareType; + xARPHeader.usProtocolType; + xARPHeader.ucHardwareAddressLength; + xARPHeader.ucProtocolAddressLength; + xARPHeader.usOperation; + xARPHeader.xTargetHardwareAddress; + */ + memcpy( ( void * ) pxARPPacket, ( void * ) xDefaultPartARPPacketHeader, sizeof( xDefaultPartARPPacketHeader ) ); + memcpy( ( void * ) pxARPPacket->xEthernetHeader.xSourceAddress.ucBytes , ( void * ) ipLOCAL_MAC_ADDRESS, ( size_t ) ipMAC_ADDRESS_LENGTH_BYTES ); + memcpy( ( void * ) pxARPPacket->xARPHeader.xSenderHardwareAddress.ucBytes, ( void * ) ipLOCAL_MAC_ADDRESS, ( size_t ) ipMAC_ADDRESS_LENGTH_BYTES ); + + memcpy( ( void* )pxARPPacket->xARPHeader.ucSenderProtocolAddress, ( void* )ipLOCAL_IP_ADDRESS_POINTER, sizeof( pxARPPacket->xARPHeader.ucSenderProtocolAddress ) ); + pxARPPacket->xARPHeader.ulTargetProtocolAddress = pxNetworkBuffer->ulIPAddress; + + pxNetworkBuffer->xDataLength = sizeof( ARPPacket_t ); + + iptraceCREATING_ARP_REQUEST( pxNetworkBuffer->ulIPAddress ); +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_ClearARP( void ) +{ + memset( xARPCache, '\0', sizeof( xARPCache ) ); +} +/*-----------------------------------------------------------*/ + +#if( ipconfigHAS_PRINTF != 0 ) || ( ipconfigHAS_DEBUG_PRINTF != 0 ) + + void FreeRTOS_PrintARPCache( void ) + { + BaseType_t x, xCount = 0; + + /* Loop through each entry in the ARP cache. */ + for( x = 0; x < ipconfigARP_CACHE_ENTRIES; x++ ) + { + if( ( xARPCache[ x ].ulIPAddress != 0ul ) && ( xARPCache[ x ].ucAge > 0U ) ) + { + /* See if the MAC-address also matches, and we're all happy */ + FreeRTOS_printf( ( "Arp %2ld: %3u - %16lxip : %02x:%02x:%02x : %02x:%02x:%02x\n", + x, + xARPCache[ x ].ucAge, + xARPCache[ x ].ulIPAddress, + xARPCache[ x ].xMACAddress.ucBytes[0], + xARPCache[ x ].xMACAddress.ucBytes[1], + xARPCache[ x ].xMACAddress.ucBytes[2], + xARPCache[ x ].xMACAddress.ucBytes[3], + xARPCache[ x ].xMACAddress.ucBytes[4], + xARPCache[ x ].xMACAddress.ucBytes[5] ) ); + xCount++; + } + } + + FreeRTOS_printf( ( "Arp has %ld entries\n", xCount ) ); + } + +#endif /* ( ipconfigHAS_PRINTF != 0 ) || ( ipconfigHAS_DEBUG_PRINTF != 0 ) */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_DHCP.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_DHCP.c new file mode 100644 index 0000000..62cfd87 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_DHCP.c @@ -0,0 +1,1011 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_IP_Private.h" +#include "FreeRTOS_UDP_IP.h" +#include "FreeRTOS_TCP_IP.h" +#include "FreeRTOS_DHCP.h" +#include "FreeRTOS_ARP.h" +#include "NetworkInterface.h" +#include "NetworkBufferManagement.h" + +/* Exclude the entire file if DHCP is not enabled. */ +#if( ipconfigUSE_DHCP != 0 ) + +#if ( ipconfigUSE_DHCP != 0 ) && ( ipconfigNETWORK_MTU < 586u ) + /* DHCP must be able to receive an options field of 312 bytes, the fixed + part of the DHCP packet is 240 bytes, and the IP/UDP headers take 28 bytes. */ + #error ipconfigNETWORK_MTU needs to be at least 586 to use DHCP +#endif + +/* Parameter widths in the DHCP packet. */ +#define dhcpCLIENT_HARDWARE_ADDRESS_LENGTH 16 +#define dhcpSERVER_HOST_NAME_LENGTH 64 +#define dhcpBOOT_FILE_NAME_LENGTH 128 + +/* Timer parameters */ +#ifndef dhcpINITIAL_DHCP_TX_PERIOD + #define dhcpINITIAL_TIMER_PERIOD ( pdMS_TO_TICKS( 250 ) ) + #define dhcpINITIAL_DHCP_TX_PERIOD ( pdMS_TO_TICKS( 5000 ) ) +#endif + +/* Codes of interest found in the DHCP options field. */ +#define dhcpZERO_PAD_OPTION_CODE ( 0u ) +#define dhcpSUBNET_MASK_OPTION_CODE ( 1u ) +#define dhcpGATEWAY_OPTION_CODE ( 3u ) +#define dhcpDNS_SERVER_OPTIONS_CODE ( 6u ) +#define dhcpDNS_HOSTNAME_OPTIONS_CODE ( 12u ) +#define dhcpREQUEST_IP_ADDRESS_OPTION_CODE ( 50u ) +#define dhcpLEASE_TIME_OPTION_CODE ( 51u ) +#define dhcpMESSAGE_TYPE_OPTION_CODE ( 53u ) +#define dhcpSERVER_IP_ADDRESS_OPTION_CODE ( 54u ) +#define dhcpPARAMETER_REQUEST_OPTION_CODE ( 55u ) +#define dhcpCLIENT_IDENTIFIER_OPTION_CODE ( 61u ) + +/* The four DHCP message types of interest. */ +#define dhcpMESSAGE_TYPE_DISCOVER ( 1 ) +#define dhcpMESSAGE_TYPE_OFFER ( 2 ) +#define dhcpMESSAGE_TYPE_REQUEST ( 3 ) +#define dhcpMESSAGE_TYPE_ACK ( 5 ) +#define dhcpMESSAGE_TYPE_NACK ( 6 ) + +/* Offsets into the transmitted DHCP options fields at which various parameters +are located. */ +#define dhcpCLIENT_IDENTIFIER_OFFSET ( 5 ) +#define dhcpREQUESTED_IP_ADDRESS_OFFSET ( 13 ) +#define dhcpDHCP_SERVER_IP_ADDRESS_OFFSET ( 19 ) + +/* Values used in the DHCP packets. */ +#define dhcpREQUEST_OPCODE ( 1 ) +#define dhcpREPLY_OPCODE ( 2 ) +#define dhcpADDRESS_TYPE_ETHERNET ( 1 ) +#define dhcpETHERNET_ADDRESS_LENGTH ( 6 ) + +/* If a lease time is not received, use the default of two days. */ +/* 48 hours in ticks. Can not use pdMS_TO_TICKS() as integer overflow can occur. */ +#define dhcpDEFAULT_LEASE_TIME ( ( 48UL * 60UL * 60UL ) * configTICK_RATE_HZ ) + +/* Don't allow the lease time to be too short. */ +#define dhcpMINIMUM_LEASE_TIME ( pdMS_TO_TICKS( 60000UL ) ) /* 60 seconds in ticks. */ + +/* Marks the end of the variable length options field in the DHCP packet. */ +#define dhcpOPTION_END_BYTE 0xffu + +/* Offset into a DHCP message at which the first byte of the options is +located. */ +#define dhcpFIRST_OPTION_BYTE_OFFSET ( 0xf0 ) + +/* When walking the variable length options field, the following value is used +to ensure the walk has not gone past the end of the valid options. 2 bytes is +made up of the length byte, and minimum one byte value. */ +#define dhcpMAX_OPTION_LENGTH_OF_INTEREST ( 2L ) + +/* Standard DHCP port numbers and magic cookie value. */ +#if( ipconfigBYTE_ORDER == pdFREERTOS_LITTLE_ENDIAN ) + #define dhcpCLIENT_PORT 0x4400u + #define dhcpSERVER_PORT 0x4300u + #define dhcpCOOKIE 0x63538263ul + #define dhcpBROADCAST 0x0080u +#else + #define dhcpCLIENT_PORT 0x0044u + #define dhcpSERVER_PORT 0x0043u + #define dhcpCOOKIE 0x63825363ul + #define dhcpBROADCAST 0x8000u +#endif /* ipconfigBYTE_ORDER */ + +#include "pack_struct_start.h" +struct xDHCPMessage +{ + uint8_t ucOpcode; + uint8_t ucAddressType; + uint8_t ucAddressLength; + uint8_t ucHops; + uint32_t ulTransactionID; + uint16_t usElapsedTime; + uint16_t usFlags; + uint32_t ulClientIPAddress_ciaddr; + uint32_t ulYourIPAddress_yiaddr; + uint32_t ulServerIPAddress_siaddr; + uint32_t ulRelayAgentIPAddress_giaddr; + uint8_t ucClientHardwareAddress[ dhcpCLIENT_HARDWARE_ADDRESS_LENGTH ]; + uint8_t ucServerHostName[ dhcpSERVER_HOST_NAME_LENGTH ]; + uint8_t ucBootFileName[ dhcpBOOT_FILE_NAME_LENGTH ]; + uint32_t ulDHCPCookie; + uint8_t ucFirstOptionByte; +} +#include "pack_struct_end.h" +typedef struct xDHCPMessage DHCPMessage_t; + +/* DHCP state machine states. */ +typedef enum +{ + eWaitingSendFirstDiscover = 0, /* Initial state. Send a discover the first time it is called, and reset all timers. */ + eWaitingOffer, /* Either resend the discover, or, if the offer is forthcoming, send a request. */ + eWaitingAcknowledge, /* Either resend the request. */ + #if( ipconfigDHCP_FALL_BACK_AUTO_IP != 0 ) + eGetLinkLayerAddress, /* When DHCP didn't respond, try to obtain a LinkLayer address 168.254.x.x. */ + #endif + eLeasedAddress, /* Resend the request at the appropriate time to renew the lease. */ + eNotUsingLeasedAddress /* DHCP failed, and a default IP address is being used. */ +} eDHCPState_t; + +/* Hold information in between steps in the DHCP state machine. */ +struct xDHCP_DATA +{ + uint32_t ulTransactionId; + uint32_t ulOfferedIPAddress; + uint32_t ulDHCPServerAddress; + uint32_t ulLeaseTime; + /* Hold information on the current timer state. */ + TickType_t xDHCPTxTime; + TickType_t xDHCPTxPeriod; + /* Try both without and with the broadcast flag */ + BaseType_t xUseBroadcast; + /* Maintains the DHCP state machine state. */ + eDHCPState_t eDHCPState; + /* The UDP socket used for all incoming and outgoing DHCP traffic. */ + Socket_t xDHCPSocket; +}; + +typedef struct xDHCP_DATA DHCPData_t; + +#if( ipconfigDHCP_FALL_BACK_AUTO_IP != 0 ) + /* Define the Link Layer IP address: 169.254.x.x */ + #define LINK_LAYER_ADDRESS_0 169 + #define LINK_LAYER_ADDRESS_1 254 + + /* Define the netmask used: 255.255.0.0 */ + #define LINK_LAYER_NETMASK_0 255 + #define LINK_LAYER_NETMASK_1 255 + #define LINK_LAYER_NETMASK_2 0 + #define LINK_LAYER_NETMASK_3 0 +#endif + + +/* + * Generate a DHCP discover message and send it on the DHCP socket. + */ +static void prvSendDHCPDiscover( void ); + +/* + * Interpret message received on the DHCP socket. + */ +static BaseType_t prvProcessDHCPReplies( BaseType_t xExpectedMessageType ); + +/* + * Generate a DHCP request packet, and send it on the DHCP socket. + */ +static void prvSendDHCPRequest( void ); + +/* + * Prepare to start a DHCP transaction. This initialises some state variables + * and creates the DHCP socket if necessary. + */ +static void prvInitialiseDHCP( void ); + +/* + * Creates the part of outgoing DHCP messages that are common to all outgoing + * DHCP messages. + */ +static uint8_t *prvCreatePartDHCPMessage( struct freertos_sockaddr *pxAddress, BaseType_t xOpcode, const uint8_t * const pucOptionsArray, size_t *pxOptionsArraySize ); + +/* + * Create the DHCP socket, if it has not been created already. + */ +static void prvCreateDHCPSocket( void ); + +/* + * After DHCP has failed to answer, prepare everything to start searching + * for (trying-out) LinkLayer IP-addresses, using the random method: Send + * a gratuitous ARP request and wait if another device responds to it. + */ +#if( ipconfigDHCP_FALL_BACK_AUTO_IP != 0 ) + static void prvPrepareLinkLayerIPLookUp( void ); +#endif + +/*-----------------------------------------------------------*/ + +/* The next DHCP transaction Id to be used. */ +static DHCPData_t xDHCPData; + +/*-----------------------------------------------------------*/ + +BaseType_t xIsDHCPSocket( Socket_t xSocket ) +{ +BaseType_t xReturn; + + if( xDHCPData.xDHCPSocket == xSocket ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vDHCPProcess( BaseType_t xReset ) +{ +BaseType_t xGivingUp = pdFALSE; +#if( ipconfigUSE_DHCP_HOOK != 0 ) + eDHCPCallbackAnswer_t eAnswer; +#endif /* ipconfigUSE_DHCP_HOOK */ + + /* Is DHCP starting over? */ + if( xReset != pdFALSE ) + { + xDHCPData.eDHCPState = eWaitingSendFirstDiscover; + } + + switch( xDHCPData.eDHCPState ) + { + case eWaitingSendFirstDiscover : + /* Ask the user if a DHCP discovery is required. */ + #if( ipconfigUSE_DHCP_HOOK != 0 ) + eAnswer = xApplicationDHCPHook( eDHCPPhasePreDiscover, xNetworkAddressing.ulDefaultIPAddress ); + if( eAnswer == eDHCPContinue ) + #endif /* ipconfigUSE_DHCP_HOOK */ + { + /* Initial state. Create the DHCP socket, timer, etc. if they + have not already been created. */ + prvInitialiseDHCP(); + + /* See if prvInitialiseDHCP() has creates a socket. */ + if( xDHCPData.xDHCPSocket == NULL ) + { + xGivingUp = pdTRUE; + break; + } + + *ipLOCAL_IP_ADDRESS_POINTER = 0UL; + + /* Send the first discover request. */ + if( xDHCPData.xDHCPSocket != NULL ) + { + xDHCPData.xDHCPTxTime = xTaskGetTickCount(); + prvSendDHCPDiscover( ); + xDHCPData.eDHCPState = eWaitingOffer; + } + } + #if( ipconfigUSE_DHCP_HOOK != 0 ) + else + { + if( eAnswer == eDHCPUseDefaults ) + { + memcpy( &xNetworkAddressing, &xDefaultAddressing, sizeof( xNetworkAddressing ) ); + } + + /* The user indicates that the DHCP process does not continue. */ + xGivingUp = pdTRUE; + } + #endif /* ipconfigUSE_DHCP_HOOK */ + break; + + case eWaitingOffer : + + xGivingUp = pdFALSE; + + /* Look for offers coming in. */ + if( prvProcessDHCPReplies( dhcpMESSAGE_TYPE_OFFER ) == pdPASS ) + { + #if( ipconfigUSE_DHCP_HOOK != 0 ) + /* Ask the user if a DHCP request is required. */ + eAnswer = xApplicationDHCPHook( eDHCPPhasePreRequest, xDHCPData.ulOfferedIPAddress ); + + if( eAnswer == eDHCPContinue ) + #endif /* ipconfigUSE_DHCP_HOOK */ + { + /* An offer has been made, the user wants to continue, + generate the request. */ + xDHCPData.xDHCPTxTime = xTaskGetTickCount(); + xDHCPData.xDHCPTxPeriod = dhcpINITIAL_DHCP_TX_PERIOD; + prvSendDHCPRequest( ); + xDHCPData.eDHCPState = eWaitingAcknowledge; + break; + } + + #if( ipconfigUSE_DHCP_HOOK != 0 ) + if( eAnswer == eDHCPUseDefaults ) + { + memcpy( &xNetworkAddressing, &xDefaultAddressing, sizeof( xNetworkAddressing ) ); + } + + /* The user indicates that the DHCP process does not continue. */ + xGivingUp = pdTRUE; + #endif /* ipconfigUSE_DHCP_HOOK */ + } + else if( ( xTaskGetTickCount() - xDHCPData.xDHCPTxTime ) > xDHCPData.xDHCPTxPeriod ) + { + /* It is time to send another Discover. Increase the time + period, and if it has not got to the point of giving up - send + another discovery. */ + xDHCPData.xDHCPTxPeriod <<= 1; + + if( xDHCPData.xDHCPTxPeriod <= ipconfigMAXIMUM_DISCOVER_TX_PERIOD ) + { + xDHCPData.ulTransactionId = ipconfigRAND32( ); + + if( 0 != xDHCPData.ulTransactionId ) + { + xDHCPData.xDHCPTxTime = xTaskGetTickCount( ); + xDHCPData.xUseBroadcast = !xDHCPData.xUseBroadcast; + prvSendDHCPDiscover( ); + FreeRTOS_debug_printf( ( "vDHCPProcess: timeout %lu ticks\n", xDHCPData.xDHCPTxPeriod ) ); + } + else + { + FreeRTOS_debug_printf( ( "vDHCPProcess: failed to generate a random Transaction ID\n" ) ); + } + } + else + { + FreeRTOS_debug_printf( ( "vDHCPProcess: giving up %lu > %lu ticks\n", xDHCPData.xDHCPTxPeriod, ipconfigMAXIMUM_DISCOVER_TX_PERIOD ) ); + + #if( ipconfigDHCP_FALL_BACK_AUTO_IP != 0 ) + { + /* Only use a fake Ack if the default IP address == 0x00 + and the link local addressing is used. Start searching + a free LinkLayer IP-address. Next state will be + 'eGetLinkLayerAddress'. */ + prvPrepareLinkLayerIPLookUp(); + + /* Setting an IP address manually so set to not using + leased address mode. */ + xDHCPData.eDHCPState = eGetLinkLayerAddress; + } + #else + { + xGivingUp = pdTRUE; + } + #endif /* ipconfigDHCP_FALL_BACK_AUTO_IP */ + } + } + break; + + case eWaitingAcknowledge : + + /* Look for acks coming in. */ + if( prvProcessDHCPReplies( dhcpMESSAGE_TYPE_ACK ) == pdPASS ) + { + FreeRTOS_debug_printf( ( "vDHCPProcess: acked %lxip\n", FreeRTOS_ntohl( xDHCPData.ulOfferedIPAddress ) ) ); + + /* DHCP completed. The IP address can now be used, and the + timer set to the lease timeout time. */ + *ipLOCAL_IP_ADDRESS_POINTER = xDHCPData.ulOfferedIPAddress; + + /* Setting the 'local' broadcast address, something like + '192.168.1.255'. */ + xNetworkAddressing.ulBroadcastAddress = ( xDHCPData.ulOfferedIPAddress & xNetworkAddressing.ulNetMask ) | ~xNetworkAddressing.ulNetMask; + xDHCPData.eDHCPState = eLeasedAddress; + + iptraceDHCP_SUCCEDEED( xDHCPData.ulOfferedIPAddress ); + + /* DHCP failed, the default configured IP-address will be used + Now call vIPNetworkUpCalls() to send the network-up event and + start the ARP timer. */ + vIPNetworkUpCalls( ); + + /* Close socket to ensure packets don't queue on it. */ + vSocketClose( xDHCPData.xDHCPSocket ); + xDHCPData.xDHCPSocket = NULL; + + if( xDHCPData.ulLeaseTime == 0UL ) + { + xDHCPData.ulLeaseTime = dhcpDEFAULT_LEASE_TIME; + } + else if( xDHCPData.ulLeaseTime < dhcpMINIMUM_LEASE_TIME ) + { + xDHCPData.ulLeaseTime = dhcpMINIMUM_LEASE_TIME; + } + else + { + /* The lease time is already valid. */ + } + + /* Check for clashes. */ + vARPSendGratuitous(); + vIPReloadDHCPTimer( xDHCPData.ulLeaseTime ); + } + else + { + /* Is it time to send another Discover? */ + if( ( xTaskGetTickCount() - xDHCPData.xDHCPTxTime ) > xDHCPData.xDHCPTxPeriod ) + { + /* Increase the time period, and if it has not got to the + point of giving up - send another request. */ + xDHCPData.xDHCPTxPeriod <<= 1; + + if( xDHCPData.xDHCPTxPeriod <= ipconfigMAXIMUM_DISCOVER_TX_PERIOD ) + { + xDHCPData.xDHCPTxTime = xTaskGetTickCount(); + prvSendDHCPRequest( ); + } + else + { + /* Give up, start again. */ + xDHCPData.eDHCPState = eWaitingSendFirstDiscover; + } + } + } + break; + + #if( ipconfigDHCP_FALL_BACK_AUTO_IP != 0 ) + case eGetLinkLayerAddress: + if( ( xTaskGetTickCount() - xDHCPData.xDHCPTxTime ) > xDHCPData.xDHCPTxPeriod ) + { + if( xARPHadIPClash == pdFALSE ) + { + /* ARP OK. proceed. */ + iptraceDHCP_SUCCEDEED( xDHCPData.ulOfferedIPAddress ); + + /* Auto-IP succeeded, the default configured IP-address will + be used. Now call vIPNetworkUpCalls() to send the + network-up event and start the ARP timer. */ + vIPNetworkUpCalls( ); + xDHCPData.eDHCPState = eNotUsingLeasedAddress; + } + else + { + /* ARP clashed - try another IP address. */ + prvPrepareLinkLayerIPLookUp(); + + /* Setting an IP address manually so set to not using leased + address mode. */ + xDHCPData.eDHCPState = eGetLinkLayerAddress; + } + } + break; + #endif /* ipconfigDHCP_FALL_BACK_AUTO_IP */ + + case eLeasedAddress : + + /* Resend the request at the appropriate time to renew the lease. */ + prvCreateDHCPSocket(); + + if( xDHCPData.xDHCPSocket != NULL ) + { + xDHCPData.xDHCPTxTime = xTaskGetTickCount(); + xDHCPData.xDHCPTxPeriod = dhcpINITIAL_DHCP_TX_PERIOD; + prvSendDHCPRequest( ); + xDHCPData.eDHCPState = eWaitingAcknowledge; + + /* From now on, we should be called more often */ + vIPReloadDHCPTimer( dhcpINITIAL_TIMER_PERIOD ); + } + break; + + case eNotUsingLeasedAddress: + + vIPSetDHCPTimerEnableState( pdFALSE ); + break; + + default: + break; + } + + if( xGivingUp != pdFALSE ) + { + /* xGivingUp became true either because of a time-out, or because + xApplicationDHCPHook() returned another value than 'eDHCPContinue', + meaning that the conversion is canceled from here. */ + + /* Revert to static IP address. */ + taskENTER_CRITICAL(); + { + *ipLOCAL_IP_ADDRESS_POINTER = xNetworkAddressing.ulDefaultIPAddress; + iptraceDHCP_REQUESTS_FAILED_USING_DEFAULT_IP_ADDRESS( xNetworkAddressing.ulDefaultIPAddress ); + } + taskEXIT_CRITICAL(); + + xDHCPData.eDHCPState = eNotUsingLeasedAddress; + vIPSetDHCPTimerEnableState( pdFALSE ); + + /* DHCP failed, the default configured IP-address will be used. Now + call vIPNetworkUpCalls() to send the network-up event and start the ARP + timer. */ + vIPNetworkUpCalls( ); + + /* Test if socket was indeed created. */ + if( xDHCPData.xDHCPSocket != NULL ) + { + /* Close socket to ensure packets don't queue on it. */ + vSocketClose( xDHCPData.xDHCPSocket ); + xDHCPData.xDHCPSocket = NULL; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvCreateDHCPSocket( void ) +{ +struct freertos_sockaddr xAddress; +BaseType_t xReturn; +TickType_t xTimeoutTime = ( TickType_t ) 0; + + /* Create the socket, if it has not already been created. */ + if( xDHCPData.xDHCPSocket == NULL ) + { + xDHCPData.xDHCPSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP ); + if( xDHCPData.xDHCPSocket != FREERTOS_INVALID_SOCKET ) + { + + /* Ensure the Rx and Tx timeouts are zero as the DHCP executes in the + context of the IP task. */ + FreeRTOS_setsockopt( xDHCPData.xDHCPSocket, 0, FREERTOS_SO_RCVTIMEO, ( void * ) &xTimeoutTime, sizeof( TickType_t ) ); + FreeRTOS_setsockopt( xDHCPData.xDHCPSocket, 0, FREERTOS_SO_SNDTIMEO, ( void * ) &xTimeoutTime, sizeof( TickType_t ) ); + + /* Bind to the standard DHCP client port. */ + xAddress.sin_port = ( uint16_t ) dhcpCLIENT_PORT; + xReturn = vSocketBind( xDHCPData.xDHCPSocket, &xAddress, sizeof( xAddress ), pdFALSE ); + if( xReturn != 0 ) + { + /* Binding failed, close the socket again. */ + vSocketClose( xDHCPData.xDHCPSocket ); + xDHCPData.xDHCPSocket = NULL; + } + } + else + { + /* Change to NULL for easier testing. */ + xDHCPData.xDHCPSocket = NULL; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvInitialiseDHCP( void ) +{ + /* Initialise the parameters that will be set by the DHCP process. Per + https://www.ietf.org/rfc/rfc2131.txt, Transaction ID should be a random + value chosen by the client. */ + xDHCPData.ulTransactionId = ipconfigRAND32(); + + /* Check for random number generator API failure. */ + if( 0 != xDHCPData.ulTransactionId ) + { + xDHCPData.xUseBroadcast = 0; + xDHCPData.ulOfferedIPAddress = 0UL; + xDHCPData.ulDHCPServerAddress = 0UL; + xDHCPData.xDHCPTxPeriod = dhcpINITIAL_DHCP_TX_PERIOD; + + /* Create the DHCP socket if it has not already been created. */ + prvCreateDHCPSocket(); + FreeRTOS_debug_printf( ( "prvInitialiseDHCP: start after %lu ticks\n", dhcpINITIAL_TIMER_PERIOD ) ); + vIPReloadDHCPTimer( dhcpINITIAL_TIMER_PERIOD ); + } +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvProcessDHCPReplies( BaseType_t xExpectedMessageType ) +{ +uint8_t *pucUDPPayload, *pucLastByte; +struct freertos_sockaddr xClient; +uint32_t xClientLength = sizeof( xClient ); +int32_t lBytes; +DHCPMessage_t *pxDHCPMessage; +uint8_t *pucByte, ucOptionCode, ucLength; +uint32_t ulProcessed, ulParameter; +BaseType_t xReturn = pdFALSE; +const uint32_t ulMandatoryOptions = 2ul; /* DHCP server address, and the correct DHCP message type must be present in the options. */ + + lBytes = FreeRTOS_recvfrom( xDHCPData.xDHCPSocket, ( void * ) &pucUDPPayload, 0ul, FREERTOS_ZERO_COPY, &xClient, &xClientLength ); + + if( lBytes > 0 ) + { + /* Map a DHCP structure onto the received data. */ + pxDHCPMessage = ( DHCPMessage_t * ) ( pucUDPPayload ); + + /* Sanity check. */ + if( ( lBytes >= sizeof( DHCPMessage_t ) ) && + ( pxDHCPMessage->ulDHCPCookie == ( uint32_t ) dhcpCOOKIE ) && + ( pxDHCPMessage->ucOpcode == ( uint8_t ) dhcpREPLY_OPCODE ) && + ( pxDHCPMessage->ulTransactionID == FreeRTOS_htonl( xDHCPData.ulTransactionId ) ) ) + { + if( memcmp( ( void * ) &( pxDHCPMessage->ucClientHardwareAddress ), + ( void * ) ipLOCAL_MAC_ADDRESS, + sizeof( MACAddress_t ) ) == 0 ) + { + /* None of the essential options have been processed yet. */ + ulProcessed = 0ul; + + /* Walk through the options until the dhcpOPTION_END_BYTE byte + is found, taking care not to walk off the end of the options. */ + pucByte = &( pxDHCPMessage->ucFirstOptionByte ); + pucLastByte = &( pucUDPPayload[ lBytes - dhcpMAX_OPTION_LENGTH_OF_INTEREST ] ); + + while( pucByte < pucLastByte ) + { + ucOptionCode = pucByte[ 0 ]; + if( ucOptionCode == dhcpOPTION_END_BYTE ) + { + /* Ready, the last byte has been seen. */ + break; + } + if( ucOptionCode == dhcpZERO_PAD_OPTION_CODE ) + { + /* The value zero is used as a pad byte, + it is not followed by a length byte. */ + pucByte += 1; + continue; + } + + /* Stop if the response is malformed. */ + if( pucByte < pucLastByte - 1 ) + { + ucLength = pucByte[ 1 ]; + pucByte += 2; + + if( pucByte >= pucLastByte - ucLength ) + { + break; + } + } + else + { + break; + } + + /* In most cases, a 4-byte network-endian parameter follows, + just get it once here and use later. */ + if( ucLength >= sizeof( ulParameter ) ) + { + memcpy( ( void * ) &( ulParameter ), + ( void * ) pucByte, + ( size_t ) sizeof( ulParameter ) ); + } + else + { + ulParameter = 0; + } + + /* Option-specific handling. */ + switch( ucOptionCode ) + { + case dhcpMESSAGE_TYPE_OPTION_CODE : + + if( *pucByte == ( uint8_t ) xExpectedMessageType ) + { + /* The message type is the message type the + state machine is expecting. */ + ulProcessed++; + } + else if( *pucByte == ( uint8_t ) dhcpMESSAGE_TYPE_NACK ) + { + if( xExpectedMessageType == ( BaseType_t ) dhcpMESSAGE_TYPE_ACK ) + { + /* Start again. */ + xDHCPData.eDHCPState = eWaitingSendFirstDiscover; + } + } + else + { + /* Don't process other message types. */ + } + break; + + case dhcpSUBNET_MASK_OPTION_CODE : + + if( ucLength == sizeof( uint32_t ) ) + { + xNetworkAddressing.ulNetMask = ulParameter; + } + break; + + case dhcpGATEWAY_OPTION_CODE : + + if( ucLength == sizeof( uint32_t ) ) + { + /* ulProcessed is not incremented in this case + because the gateway is not essential. */ + xNetworkAddressing.ulGatewayAddress = ulParameter; + } + break; + + case dhcpDNS_SERVER_OPTIONS_CODE : + + /* ulProcessed is not incremented in this case + because the DNS server is not essential. Only the + first DNS server address is taken. */ + xNetworkAddressing.ulDNSServerAddress = ulParameter; + break; + + case dhcpSERVER_IP_ADDRESS_OPTION_CODE : + + if( ucLength == sizeof( uint32_t ) ) + { + if( xExpectedMessageType == ( BaseType_t ) dhcpMESSAGE_TYPE_OFFER ) + { + /* Offers state the replying server. */ + ulProcessed++; + xDHCPData.ulDHCPServerAddress = ulParameter; + } + else + { + /* The ack must come from the expected server. */ + if( xDHCPData.ulDHCPServerAddress == ulParameter ) + { + ulProcessed++; + } + } + } + break; + + case dhcpLEASE_TIME_OPTION_CODE : + + if( ucLength == sizeof( xDHCPData.ulLeaseTime ) ) + { + /* ulProcessed is not incremented in this case + because the lease time is not essential. */ + /* The DHCP parameter is in seconds, convert + to host-endian format. */ + xDHCPData.ulLeaseTime = FreeRTOS_ntohl( ulParameter ); + + /* Divide the lease time by two to ensure a + renew request is sent before the lease actually + expires. */ + xDHCPData.ulLeaseTime >>= 1UL; + + /* Multiply with configTICK_RATE_HZ to get clock + ticks. */ + xDHCPData.ulLeaseTime = configTICK_RATE_HZ * xDHCPData.ulLeaseTime; + } + break; + + default : + + /* Not interested in this field. */ + + break; + } + + /* Jump over the data to find the next option code. */ + if( ucLength == 0u ) + { + break; + } + else + { + pucByte += ucLength; + } + } + + /* Were all the mandatory options received? */ + if( ulProcessed >= ulMandatoryOptions ) + { + /* HT:endian: used to be network order */ + xDHCPData.ulOfferedIPAddress = pxDHCPMessage->ulYourIPAddress_yiaddr; + FreeRTOS_printf( ( "vDHCPProcess: offer %lxip\n", FreeRTOS_ntohl( xDHCPData.ulOfferedIPAddress ) ) ); + xReturn = pdPASS; + } + } + } + + FreeRTOS_ReleaseUDPPayloadBuffer( ( void * ) pucUDPPayload ); + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static uint8_t *prvCreatePartDHCPMessage( struct freertos_sockaddr *pxAddress, BaseType_t xOpcode, const uint8_t * const pucOptionsArray, size_t *pxOptionsArraySize ) +{ +DHCPMessage_t *pxDHCPMessage; +size_t xRequiredBufferSize = sizeof( DHCPMessage_t ) + *pxOptionsArraySize; +uint8_t *pucUDPPayloadBuffer; + +#if( ipconfigDHCP_REGISTER_HOSTNAME == 1 ) + const char *pucHostName = pcApplicationHostnameHook (); + size_t xNameLength = strlen( pucHostName ); + uint8_t *pucPtr; + + xRequiredBufferSize += ( 2 + xNameLength ); +#endif + + /* Get a buffer. This uses a maximum delay, but the delay will be capped + to ipconfigUDP_MAX_SEND_BLOCK_TIME_TICKS so the return value still needs to + be test. */ + do + { + } while( ( pucUDPPayloadBuffer = ( uint8_t * ) FreeRTOS_GetUDPPayloadBuffer( xRequiredBufferSize, portMAX_DELAY ) ) == NULL ); + + pxDHCPMessage = ( DHCPMessage_t * ) pucUDPPayloadBuffer; + + /* Most fields need to be zero. */ + memset( ( void * ) pxDHCPMessage, 0x00, sizeof( DHCPMessage_t ) ); + + /* Create the message. */ + pxDHCPMessage->ucOpcode = ( uint8_t ) xOpcode; + pxDHCPMessage->ucAddressType = ( uint8_t ) dhcpADDRESS_TYPE_ETHERNET; + pxDHCPMessage->ucAddressLength = ( uint8_t ) dhcpETHERNET_ADDRESS_LENGTH; + pxDHCPMessage->ulTransactionID = FreeRTOS_htonl( xDHCPData.ulTransactionId ); + pxDHCPMessage->ulDHCPCookie = ( uint32_t ) dhcpCOOKIE; + if( xDHCPData.xUseBroadcast != pdFALSE ) + { + pxDHCPMessage->usFlags = ( uint16_t ) dhcpBROADCAST; + } + else + { + pxDHCPMessage->usFlags = 0u; + } + + memcpy( ( void * ) &( pxDHCPMessage->ucClientHardwareAddress[ 0 ] ), ( void * ) ipLOCAL_MAC_ADDRESS, sizeof( MACAddress_t ) ); + + /* Copy in the const part of the options options. */ + memcpy( ( void * ) &( pucUDPPayloadBuffer[ dhcpFIRST_OPTION_BYTE_OFFSET ] ), ( void * ) pucOptionsArray, *pxOptionsArraySize ); + + #if( ipconfigDHCP_REGISTER_HOSTNAME == 1 ) + { + /* With this option, the hostname can be registered as well which makes + it easier to lookup a device in a router's list of DHCP clients. */ + + /* Point to where the OPTION_END was stored to add data. */ + pucPtr = &( pucUDPPayloadBuffer[ dhcpFIRST_OPTION_BYTE_OFFSET + ( *pxOptionsArraySize - 1 ) ] ); + pucPtr[ 0 ] = dhcpDNS_HOSTNAME_OPTIONS_CODE; + pucPtr[ 1 ] = ( uint8_t ) xNameLength; + memcpy( ( void *) ( pucPtr + 2 ), pucHostName, xNameLength ); + pucPtr[ 2 + xNameLength ] = dhcpOPTION_END_BYTE; + *pxOptionsArraySize += ( 2 + xNameLength ); + } + #endif + + /* Map in the client identifier. */ + memcpy( ( void * ) &( pucUDPPayloadBuffer[ dhcpFIRST_OPTION_BYTE_OFFSET + dhcpCLIENT_IDENTIFIER_OFFSET ] ), + ( void * ) ipLOCAL_MAC_ADDRESS, sizeof( MACAddress_t ) ); + + /* Set the addressing. */ + pxAddress->sin_addr = ipBROADCAST_IP_ADDRESS; + pxAddress->sin_port = ( uint16_t ) dhcpSERVER_PORT; + + return pucUDPPayloadBuffer; +} +/*-----------------------------------------------------------*/ + +static void prvSendDHCPRequest( void ) +{ +uint8_t *pucUDPPayloadBuffer; +struct freertos_sockaddr xAddress; +static const uint8_t ucDHCPRequestOptions[] = +{ + /* Do not change the ordering without also changing + dhcpCLIENT_IDENTIFIER_OFFSET, dhcpREQUESTED_IP_ADDRESS_OFFSET and + dhcpDHCP_SERVER_IP_ADDRESS_OFFSET. */ + dhcpMESSAGE_TYPE_OPTION_CODE, 1, dhcpMESSAGE_TYPE_REQUEST, /* Message type option. */ + dhcpCLIENT_IDENTIFIER_OPTION_CODE, 6, 0, 0, 0, 0, 0, 0, /* Client identifier. */ + dhcpREQUEST_IP_ADDRESS_OPTION_CODE, 4, 0, 0, 0, 0, /* The IP address being requested. */ + dhcpSERVER_IP_ADDRESS_OPTION_CODE, 4, 0, 0, 0, 0, /* The IP address of the DHCP server. */ + dhcpOPTION_END_BYTE +}; +size_t xOptionsLength = sizeof( ucDHCPRequestOptions ); + + pucUDPPayloadBuffer = prvCreatePartDHCPMessage( &xAddress, dhcpREQUEST_OPCODE, ucDHCPRequestOptions, &xOptionsLength ); + + /* Copy in the IP address being requested. */ + memcpy( ( void * ) &( pucUDPPayloadBuffer[ dhcpFIRST_OPTION_BYTE_OFFSET + dhcpREQUESTED_IP_ADDRESS_OFFSET ] ), + ( void * ) &( xDHCPData.ulOfferedIPAddress ), sizeof( xDHCPData.ulOfferedIPAddress ) ); + + /* Copy in the address of the DHCP server being used. */ + memcpy( ( void * ) &( pucUDPPayloadBuffer[ dhcpFIRST_OPTION_BYTE_OFFSET + dhcpDHCP_SERVER_IP_ADDRESS_OFFSET ] ), + ( void * ) &( xDHCPData.ulDHCPServerAddress ), sizeof( xDHCPData.ulDHCPServerAddress ) ); + + FreeRTOS_debug_printf( ( "vDHCPProcess: reply %lxip\n", FreeRTOS_ntohl( xDHCPData.ulOfferedIPAddress ) ) ); + iptraceSENDING_DHCP_REQUEST(); + + if( FreeRTOS_sendto( xDHCPData.xDHCPSocket, pucUDPPayloadBuffer, ( sizeof( DHCPMessage_t ) + xOptionsLength ), FREERTOS_ZERO_COPY, &xAddress, sizeof( xAddress ) ) == 0 ) + { + /* The packet was not successfully queued for sending and must be + returned to the stack. */ + FreeRTOS_ReleaseUDPPayloadBuffer( pucUDPPayloadBuffer ); + } +} +/*-----------------------------------------------------------*/ + +static void prvSendDHCPDiscover( void ) +{ +uint8_t *pucUDPPayloadBuffer; +struct freertos_sockaddr xAddress; +static const uint8_t ucDHCPDiscoverOptions[] = +{ + /* Do not change the ordering without also changing dhcpCLIENT_IDENTIFIER_OFFSET. */ + dhcpMESSAGE_TYPE_OPTION_CODE, 1, dhcpMESSAGE_TYPE_DISCOVER, /* Message type option. */ + dhcpCLIENT_IDENTIFIER_OPTION_CODE, 6, 0, 0, 0, 0, 0, 0, /* Client identifier. */ + dhcpPARAMETER_REQUEST_OPTION_CODE, 3, dhcpSUBNET_MASK_OPTION_CODE, dhcpGATEWAY_OPTION_CODE, dhcpDNS_SERVER_OPTIONS_CODE, /* Parameter request option. */ + dhcpOPTION_END_BYTE +}; +size_t xOptionsLength = sizeof( ucDHCPDiscoverOptions ); + + pucUDPPayloadBuffer = prvCreatePartDHCPMessage( &xAddress, dhcpREQUEST_OPCODE, ucDHCPDiscoverOptions, &xOptionsLength ); + + FreeRTOS_debug_printf( ( "vDHCPProcess: discover\n" ) ); + iptraceSENDING_DHCP_DISCOVER(); + + if( FreeRTOS_sendto( xDHCPData.xDHCPSocket, pucUDPPayloadBuffer, ( sizeof( DHCPMessage_t ) + xOptionsLength ), FREERTOS_ZERO_COPY, &xAddress, sizeof( xAddress ) ) == 0 ) + { + /* The packet was not successfully queued for sending and must be + returned to the stack. */ + FreeRTOS_ReleaseUDPPayloadBuffer( pucUDPPayloadBuffer ); + } +} +/*-----------------------------------------------------------*/ + +#if( ipconfigDHCP_FALL_BACK_AUTO_IP != 0 ) + + static void prvPrepareLinkLayerIPLookUp( void ) + { + uint8_t ucLinkLayerIPAddress[ 2 ]; + + /* After DHCP has failed to answer, prepare everything to start + trying-out LinkLayer IP-addresses, using the random method. */ + xDHCPData.xDHCPTxTime = xTaskGetTickCount(); + + ucLinkLayerIPAddress[ 0 ] = ( uint8_t )1 + ( uint8_t )( ipconfigRAND32() % 0xFDu ); /* get value 1..254 for IP-address 3rd byte of IP address to try. */ + ucLinkLayerIPAddress[ 1 ] = ( uint8_t )1 + ( uint8_t )( ipconfigRAND32() % 0xFDu ); /* get value 1..254 for IP-address 4th byte of IP address to try. */ + + xNetworkAddressing.ulGatewayAddress = FreeRTOS_htonl( 0xA9FE0203 ); + + /* prepare xDHCPData with data to test. */ + xDHCPData.ulOfferedIPAddress = + FreeRTOS_inet_addr_quick( LINK_LAYER_ADDRESS_0, LINK_LAYER_ADDRESS_1, ucLinkLayerIPAddress[ 0 ], ucLinkLayerIPAddress[ 1 ] ); + + xDHCPData.ulLeaseTime = dhcpDEFAULT_LEASE_TIME; /* don't care about lease time. just put anything. */ + + xNetworkAddressing.ulNetMask = + FreeRTOS_inet_addr_quick( LINK_LAYER_NETMASK_0, LINK_LAYER_NETMASK_1, LINK_LAYER_NETMASK_2, LINK_LAYER_NETMASK_3 ); + + /* DHCP completed. The IP address can now be used, and the + timer set to the lease timeout time. */ + *ipLOCAL_IP_ADDRESS_POINTER = xDHCPData.ulOfferedIPAddress; + + /* Setting the 'local' broadcast address, something like 192.168.1.255' */ + xNetworkAddressing.ulBroadcastAddress = ( xDHCPData.ulOfferedIPAddress & xNetworkAddressing.ulNetMask ) | ~xNetworkAddressing.ulNetMask; + + /* Close socket to ensure packets don't queue on it. not needed anymore as DHCP failed. but still need timer for ARP testing. */ + vSocketClose( xDHCPData.xDHCPSocket ); + xDHCPData.xDHCPSocket = NULL; + xDHCPData.xDHCPTxPeriod = pdMS_TO_TICKS( 3000ul + ( ipconfigRAND32() & 0x3fful ) ); /* do ARP test every (3 + 0-1024mS) seconds. */ + + xARPHadIPClash = pdFALSE; /* reset flag that shows if have ARP clash. */ + vARPSendGratuitous(); + } + +#endif /* ipconfigDHCP_FALL_BACK_AUTO_IP */ +/*-----------------------------------------------------------*/ + +#endif /* ipconfigUSE_DHCP != 0 */ + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_DNS.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_DNS.c new file mode 100644 index 0000000..925cec9 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_DNS.c @@ -0,0 +1,1424 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "list.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_IP_Private.h" +#include "FreeRTOS_UDP_IP.h" +#include "FreeRTOS_DNS.h" +#include "NetworkBufferManagement.h" +#include "NetworkInterface.h" +#include "IPTraceMacroDefaults.h" + +/* Exclude the entire file if DNS is not enabled. */ +#if( ipconfigUSE_DNS != 0 ) + +#if( ipconfigBYTE_ORDER == pdFREERTOS_LITTLE_ENDIAN ) + #define dnsDNS_PORT 0x3500 + #define dnsONE_QUESTION 0x0100 + #define dnsOUTGOING_FLAGS 0x0001 /* Standard query. */ + #define dnsRX_FLAGS_MASK 0x0f80 /* The bits of interest in the flags field of incoming DNS messages. */ + #define dnsEXPECTED_RX_FLAGS 0x0080 /* Should be a response, without any errors. */ +#else + #define dnsDNS_PORT 0x0035 + #define dnsONE_QUESTION 0x0001 + #define dnsOUTGOING_FLAGS 0x0100 /* Standard query. */ + #define dnsRX_FLAGS_MASK 0x800f /* The bits of interest in the flags field of incoming DNS messages. */ + #define dnsEXPECTED_RX_FLAGS 0x8000 /* Should be a response, without any errors. */ + +#endif /* ipconfigBYTE_ORDER */ + +/* The maximum number of times a DNS request should be sent out if a response +is not received, before giving up. */ +#ifndef ipconfigDNS_REQUEST_ATTEMPTS + #define ipconfigDNS_REQUEST_ATTEMPTS 5 +#endif + +/* If the top two bits in the first character of a name field are set then the +name field is an offset to the string, rather than the string itself. */ +#define dnsNAME_IS_OFFSET ( ( uint8_t ) 0xc0 ) + +/* NBNS flags. */ +#define dnsNBNS_FLAGS_RESPONSE 0x8000 +#define dnsNBNS_FLAGS_OPCODE_MASK 0x7800 +#define dnsNBNS_FLAGS_OPCODE_QUERY 0x0000 +#define dnsNBNS_FLAGS_OPCODE_REGISTRATION 0x2800 + +/* Host types. */ +#define dnsTYPE_A_HOST 0x01 +#define dnsCLASS_IN 0x01 + +/* LLMNR constants. */ +#define dnsLLMNR_TTL_VALUE 300000 +#define dnsLLMNR_FLAGS_IS_REPONSE 0x8000 + +/* NBNS constants. */ +#define dnsNBNS_TTL_VALUE 3600 /* 1 hour valid */ +#define dnsNBNS_TYPE_NET_BIOS 0x0020 +#define dnsNBNS_CLASS_IN 0x01 +#define dnsNBNS_NAME_FLAGS 0x6000 +#define dnsNBNS_ENCODED_NAME_LENGTH 32 + +/* If the queried NBNS name matches with the device's name, +the query will be responded to with these flags: */ +#define dnsNBNS_QUERY_RESPONSE_FLAGS ( 0x8500 ) + +/* Flag DNS parsing errors in situations where an IPv4 address is the return +type. */ +#define dnsPARSE_ERROR 0UL + +/* + * Create a socket and bind it to the standard DNS port number. Return the + * the created socket - or NULL if the socket could not be created or bound. + */ +static Socket_t prvCreateDNSSocket( void ); + +/* + * Create the DNS message in the zero copy buffer passed in the first parameter. + */ +static size_t prvCreateDNSMessage( uint8_t *pucUDPPayloadBuffer, const char *pcHostName, TickType_t xIdentifier ); + +/* + * Simple routine that jumps over the NAME field of a resource record. + */ +static uint8_t *prvSkipNameField( uint8_t *pucByte, size_t xSourceLen ); + +/* + * Process a response packet from a DNS server. + */ +static uint32_t prvParseDNSReply( uint8_t *pucUDPPayloadBuffer, size_t xBufferLength, TickType_t xIdentifier ); + +/* + * Prepare and send a message to a DNS server. 'xReadTimeOut_ms' will be passed as + * zero, in case the user has supplied a call-back function. + */ +static uint32_t prvGetHostByName( const char *pcHostName, TickType_t xIdentifier, TickType_t xReadTimeOut_ms ); + +/* + * The NBNS and the LLMNR protocol share this reply function. + */ +#if( ( ipconfigUSE_NBNS == 1 ) || ( ipconfigUSE_LLMNR == 1 ) ) + static void prvReplyDNSMessage( NetworkBufferDescriptor_t *pxNetworkBuffer, BaseType_t lNetLength ); +#endif + +#if( ipconfigUSE_NBNS == 1 ) + static portINLINE void prvTreatNBNS( uint8_t *pucUDPPayloadBuffer, size_t xBufferLength, uint32_t ulIPAddress ); +#endif /* ipconfigUSE_NBNS */ + +#if( ipconfigUSE_DNS_CACHE == 1 ) + static uint8_t *prvReadNameField( uint8_t *pucByte, size_t xSourceLen, char *pcName, size_t xLen ); + static void prvProcessDNSCache( const char *pcName, uint32_t *pulIP, uint32_t ulTTL, BaseType_t xLookUp ); + + typedef struct xDNS_CACHE_TABLE_ROW + { + uint32_t ulIPAddress; /* The IP address of an ARP cache entry. */ + char pcName[ ipconfigDNS_CACHE_NAME_LENGTH ]; /* The name of the host */ + uint32_t ulTTL; /* Time-to-Live (in seconds) from the DNS server. */ + uint32_t ulTimeWhenAddedInSeconds; + } DNSCacheRow_t; + + static DNSCacheRow_t xDNSCache[ ipconfigDNS_CACHE_ENTRIES ]; +#endif /* ipconfigUSE_DNS_CACHE == 1 */ + +#if( ipconfigUSE_LLMNR == 1 ) + const MACAddress_t xLLMNR_MacAdress = { { 0x01, 0x00, 0x5e, 0x00, 0x00, 0xfc } }; +#endif /* ipconfigUSE_LLMNR == 1 */ + +/*-----------------------------------------------------------*/ + +#include "pack_struct_start.h" +struct xDNSMessage +{ + uint16_t usIdentifier; + uint16_t usFlags; + uint16_t usQuestions; + uint16_t usAnswers; + uint16_t usAuthorityRRs; + uint16_t usAdditionalRRs; +} +#include "pack_struct_end.h" +typedef struct xDNSMessage DNSMessage_t; + +/* A DNS query consists of a header, as described in 'struct xDNSMessage' +It is followed by 1 or more queries, each one consisting of a name and a tail, +with two fields: type and class +*/ +#include "pack_struct_start.h" +struct xDNSTail +{ + uint16_t usType; + uint16_t usClass; +} +#include "pack_struct_end.h" +typedef struct xDNSTail DNSTail_t; + +/* DNS answer record header. */ +#include "pack_struct_start.h" +struct xDNSAnswerRecord +{ + uint16_t usType; + uint16_t usClass; + uint32_t ulTTL; + uint16_t usDataLength; +} +#include "pack_struct_end.h" +typedef struct xDNSAnswerRecord DNSAnswerRecord_t; + +#if( ipconfigUSE_LLMNR == 1 ) + + #include "pack_struct_start.h" + struct xLLMNRAnswer + { + uint8_t ucNameCode; + uint8_t ucNameOffset; /* The name is not repeated in the answer, only the offset is given with "0xc0 " */ + uint16_t usType; + uint16_t usClass; + uint32_t ulTTL; + uint16_t usDataLength; + uint32_t ulIPAddress; + } + #include "pack_struct_end.h" + typedef struct xLLMNRAnswer LLMNRAnswer_t; + +#endif /* ipconfigUSE_LLMNR == 1 */ + +#if( ipconfigUSE_NBNS == 1 ) + + #include "pack_struct_start.h" + struct xNBNSRequest + { + uint16_t usRequestId; + uint16_t usFlags; + uint16_t ulRequestCount; + uint16_t usAnswerRSS; + uint16_t usAuthRSS; + uint16_t usAdditionalRSS; + uint8_t ucNameSpace; + uint8_t ucName[ dnsNBNS_ENCODED_NAME_LENGTH ]; + uint8_t ucNameZero; + uint16_t usType; + uint16_t usClass; + } + #include "pack_struct_end.h" + typedef struct xNBNSRequest NBNSRequest_t; + + #include "pack_struct_start.h" + struct xNBNSAnswer + { + uint16_t usType; + uint16_t usClass; + uint32_t ulTTL; + uint16_t usDataLength; + uint16_t usNbFlags; /* NetBIOS flags 0x6000 : IP-address, big-endian */ + uint32_t ulIPAddress; + } + #include "pack_struct_end.h" + typedef struct xNBNSAnswer NBNSAnswer_t; + +#endif /* ipconfigUSE_NBNS == 1 */ + +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_DNS_CACHE == 1 ) + uint32_t FreeRTOS_dnslookup( const char *pcHostName ) + { + uint32_t ulIPAddress = 0UL; + prvProcessDNSCache( pcHostName, &ulIPAddress, 0, pdTRUE ); + return ulIPAddress; + } +#endif /* ipconfigUSE_DNS_CACHE == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigDNS_USE_CALLBACKS != 0 ) + + typedef struct xDNS_Callback { + TickType_t xRemaningTime; /* Timeout in ms */ + FOnDNSEvent pCallbackFunction; /* Function to be called when the address has been found or when a timeout has beeen reached */ + TimeOut_t xTimeoutState; + void *pvSearchID; + struct xLIST_ITEM xListItem; + char pcName[ 1 ]; + } DNSCallback_t; + + static List_t xCallbackList; + + /* Define FreeRTOS_gethostbyname() as a normal blocking call. */ + uint32_t FreeRTOS_gethostbyname( const char *pcHostName ) + { + return FreeRTOS_gethostbyname_a( pcHostName, ( FOnDNSEvent ) NULL, ( void* )NULL, 0 ); + } + /*-----------------------------------------------------------*/ + + /* Initialise the list of call-back structures. */ + void vDNSInitialise( void ); + void vDNSInitialise( void ) + { + vListInitialise( &xCallbackList ); + } + /*-----------------------------------------------------------*/ + + /* Iterate through the list of call-back structures and remove + old entries which have reached a timeout. + As soon as the list hase become empty, the DNS timer will be stopped + In case pvSearchID is supplied, the user wants to cancel a DNS request + */ + void vDNSCheckCallBack( void *pvSearchID ); + void vDNSCheckCallBack( void *pvSearchID ) + { + const ListItem_t *pxIterator; + const MiniListItem_t* xEnd = ( const MiniListItem_t* )listGET_END_MARKER( &xCallbackList ); + + vTaskSuspendAll(); + { + for( pxIterator = ( const ListItem_t * ) listGET_NEXT( xEnd ); + pxIterator != ( const ListItem_t * ) xEnd; + ) + { + DNSCallback_t *pxCallback = ( DNSCallback_t * ) listGET_LIST_ITEM_OWNER( pxIterator ); + /* Move to the next item because we might remove this item */ + pxIterator = ( const ListItem_t * ) listGET_NEXT( pxIterator ); + if( ( pvSearchID != NULL ) && ( pvSearchID == pxCallback->pvSearchID ) ) + { + uxListRemove( &pxCallback->xListItem ); + vPortFree( pxCallback ); + } + else if( xTaskCheckForTimeOut( &pxCallback->xTimeoutState, &pxCallback->xRemaningTime ) != pdFALSE ) + { + pxCallback->pCallbackFunction( pxCallback->pcName, pxCallback->pvSearchID, 0 ); + uxListRemove( &pxCallback->xListItem ); + vPortFree( ( void * ) pxCallback ); + } + } + } + xTaskResumeAll(); + + if( listLIST_IS_EMPTY( &xCallbackList ) ) + { + vIPSetDnsTimerEnableState( pdFALSE ); + } + } + /*-----------------------------------------------------------*/ + + void FreeRTOS_gethostbyname_cancel( void *pvSearchID ) + { + /* _HT_ Should better become a new API call to have the IP-task remove the callback */ + vDNSCheckCallBack( pvSearchID ); + } + /*-----------------------------------------------------------*/ + + /* FreeRTOS_gethostbyname_a() was called along with callback parameters. + Store them in a list for later reference. */ + static void vDNSSetCallBack( const char *pcHostName, void *pvSearchID, FOnDNSEvent pCallbackFunction, TickType_t xTimeout, TickType_t xIdentifier ); + static void vDNSSetCallBack( const char *pcHostName, void *pvSearchID, FOnDNSEvent pCallbackFunction, TickType_t xTimeout, TickType_t xIdentifier ) + { + size_t lLength = strlen( pcHostName ); + DNSCallback_t *pxCallback = ( DNSCallback_t * )pvPortMalloc( sizeof( *pxCallback ) + lLength ); + + /* Translate from ms to number of clock ticks. */ + xTimeout /= portTICK_PERIOD_MS; + if( pxCallback != NULL ) + { + if( listLIST_IS_EMPTY( &xCallbackList ) ) + { + /* This is the first one, start the DNS timer to check for timeouts */ + vIPReloadDNSTimer( FreeRTOS_min_uint32( 1000U, xTimeout ) ); + } + strcpy( pxCallback->pcName, pcHostName ); + pxCallback->pCallbackFunction = pCallbackFunction; + pxCallback->pvSearchID = pvSearchID; + pxCallback->xRemaningTime = xTimeout; + vTaskSetTimeOutState( &pxCallback->xTimeoutState ); + listSET_LIST_ITEM_OWNER( &( pxCallback->xListItem ), ( void* ) pxCallback ); + listSET_LIST_ITEM_VALUE( &( pxCallback->xListItem ), xIdentifier ); + vTaskSuspendAll(); + { + vListInsertEnd( &xCallbackList, &pxCallback->xListItem ); + } + xTaskResumeAll(); + } + } + /*-----------------------------------------------------------*/ + + /* A DNS reply was received, see if there is any matching entry and + call the handler. */ + static void vDNSDoCallback( TickType_t xIdentifier, const char *pcName, uint32_t ulIPAddress ); + static void vDNSDoCallback( TickType_t xIdentifier, const char *pcName, uint32_t ulIPAddress ) + { + const ListItem_t *pxIterator; + const MiniListItem_t* xEnd = ( const MiniListItem_t* )listGET_END_MARKER( &xCallbackList ); + + vTaskSuspendAll(); + { + for( pxIterator = ( const ListItem_t * ) listGET_NEXT( xEnd ); + pxIterator != ( const ListItem_t * ) xEnd; + pxIterator = ( const ListItem_t * ) listGET_NEXT( pxIterator ) ) + { + if( listGET_LIST_ITEM_VALUE( pxIterator ) == xIdentifier ) + { + DNSCallback_t *pxCallback = ( DNSCallback_t * ) listGET_LIST_ITEM_OWNER( pxIterator ); + pxCallback->pCallbackFunction( pcName, pxCallback->pvSearchID, ulIPAddress ); + uxListRemove( &pxCallback->xListItem ); + vPortFree( pxCallback ); + if( listLIST_IS_EMPTY( &xCallbackList ) ) + { + vIPSetDnsTimerEnableState( pdFALSE ); + } + break; + } + } + } + xTaskResumeAll(); + } + +#endif /* ipconfigDNS_USE_CALLBACKS != 0 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigDNS_USE_CALLBACKS == 0 ) +uint32_t FreeRTOS_gethostbyname( const char *pcHostName ) +#else +uint32_t FreeRTOS_gethostbyname_a( const char *pcHostName, FOnDNSEvent pCallback, void *pvSearchID, TickType_t xTimeout ) +#endif +{ +uint32_t ulIPAddress = 0UL; +TickType_t xReadTimeOut_ms = ipconfigSOCK_DEFAULT_RECEIVE_BLOCK_TIME; +TickType_t xIdentifier = 0; + + /* If the supplied hostname is IP address, convert it to uint32_t + and return. */ + #if( ipconfigINCLUDE_FULL_INET_ADDR == 1 ) + { + ulIPAddress = FreeRTOS_inet_addr( pcHostName ); + } + #endif /* ipconfigINCLUDE_FULL_INET_ADDR == 1 */ + + /* If a DNS cache is used then check the cache before issuing another DNS + request. */ + #if( ipconfigUSE_DNS_CACHE == 1 ) + { + if( ulIPAddress == 0UL ) + { + ulIPAddress = FreeRTOS_dnslookup( pcHostName ); + if( ulIPAddress != 0 ) + { + FreeRTOS_debug_printf( ( "FreeRTOS_gethostbyname: found '%s' in cache: %lxip\n", pcHostName, ulIPAddress ) ); + } + else + { + /* prvGetHostByName will be called to start a DNS lookup */ + } + } + } + #endif /* ipconfigUSE_DNS_CACHE == 1 */ + + /* Generate a unique identifier. */ + if( 0 == ulIPAddress ) + { + xIdentifier = ( TickType_t )ipconfigRAND32( ); + } + + #if( ipconfigDNS_USE_CALLBACKS != 0 ) + { + if( pCallback != NULL ) + { + if( ulIPAddress == 0UL ) + { + /* The user has provided a callback function, so do not block on recvfrom() */ + if( 0 != xIdentifier ) + { + xReadTimeOut_ms = 0; + vDNSSetCallBack( pcHostName, pvSearchID, pCallback, xTimeout, ( TickType_t )xIdentifier ); + } + } + else + { + /* The IP address is known, do the call-back now. */ + pCallback( pcHostName, pvSearchID, ulIPAddress ); + } + } + } + #endif + + if( ( ulIPAddress == 0UL ) && ( 0 != xIdentifier ) ) + { + ulIPAddress = prvGetHostByName( pcHostName, xIdentifier, xReadTimeOut_ms ); + } + + return ulIPAddress; +} +/*-----------------------------------------------------------*/ + +static uint32_t prvGetHostByName( const char *pcHostName, TickType_t xIdentifier, TickType_t xReadTimeOut_ms ) +{ +struct freertos_sockaddr xAddress; +Socket_t xDNSSocket; +uint32_t ulIPAddress = 0UL; +uint8_t *pucUDPPayloadBuffer; +uint32_t ulAddressLength = sizeof( struct freertos_sockaddr ); +BaseType_t xAttempt; +int32_t lBytes; +size_t xPayloadLength, xExpectedPayloadLength; +TickType_t xWriteTimeOut_ms = ipconfigSOCK_DEFAULT_SEND_BLOCK_TIME; + +#if( ipconfigUSE_LLMNR == 1 ) + BaseType_t bHasDot = pdFALSE; +#endif /* ipconfigUSE_LLMNR == 1 */ + + /* If LLMNR is being used then determine if the host name includes a '.' - + if not then LLMNR can be used as the lookup method. */ + #if( ipconfigUSE_LLMNR == 1 ) + { + const char *pucPtr; + for( pucPtr = pcHostName; *pucPtr; pucPtr++ ) + { + if( *pucPtr == '.' ) + { + bHasDot = pdTRUE; + break; + } + } + } + #endif /* ipconfigUSE_LLMNR == 1 */ + + /* Two is added at the end for the count of characters in the first + subdomain part and the string end byte. */ + xExpectedPayloadLength = sizeof( DNSMessage_t ) + strlen( pcHostName ) + sizeof( uint16_t ) + sizeof( uint16_t ) + 2u; + + xDNSSocket = prvCreateDNSSocket(); + + if( xDNSSocket != NULL ) + { + FreeRTOS_setsockopt( xDNSSocket, 0, FREERTOS_SO_SNDTIMEO, ( void * ) &xWriteTimeOut_ms, sizeof( TickType_t ) ); + FreeRTOS_setsockopt( xDNSSocket, 0, FREERTOS_SO_RCVTIMEO, ( void * ) &xReadTimeOut_ms, sizeof( TickType_t ) ); + + for( xAttempt = 0; xAttempt < ipconfigDNS_REQUEST_ATTEMPTS; xAttempt++ ) + { + /* Get a buffer. This uses a maximum delay, but the delay will be + capped to ipconfigUDP_MAX_SEND_BLOCK_TIME_TICKS so the return value + still needs to be tested. */ + pucUDPPayloadBuffer = ( uint8_t * ) FreeRTOS_GetUDPPayloadBuffer( xExpectedPayloadLength, portMAX_DELAY ); + + if( pucUDPPayloadBuffer != NULL ) + { + /* Create the message in the obtained buffer. */ + xPayloadLength = prvCreateDNSMessage( pucUDPPayloadBuffer, pcHostName, xIdentifier ); + + iptraceSENDING_DNS_REQUEST(); + + /* Obtain the DNS server address. */ + FreeRTOS_GetAddressConfiguration( NULL, NULL, NULL, &ulIPAddress ); + + /* Send the DNS message. */ +#if( ipconfigUSE_LLMNR == 1 ) + if( bHasDot == pdFALSE ) + { + /* Use LLMNR addressing. */ + ( ( DNSMessage_t * ) pucUDPPayloadBuffer) -> usFlags = 0; + xAddress.sin_addr = ipLLMNR_IP_ADDR; /* Is in network byte order. */ + xAddress.sin_port = FreeRTOS_ntohs( ipLLMNR_PORT ); + } + else +#endif + { + /* Use DNS server. */ + xAddress.sin_addr = ulIPAddress; + xAddress.sin_port = dnsDNS_PORT; + } + + ulIPAddress = 0UL; + + if( FreeRTOS_sendto( xDNSSocket, pucUDPPayloadBuffer, xPayloadLength, FREERTOS_ZERO_COPY, &xAddress, sizeof( xAddress ) ) != 0 ) + { + /* Wait for the reply. */ + lBytes = FreeRTOS_recvfrom( xDNSSocket, &pucUDPPayloadBuffer, 0, FREERTOS_ZERO_COPY, &xAddress, &ulAddressLength ); + + if( lBytes > 0 ) + { + /* The reply was received. Process it. */ + ulIPAddress = prvParseDNSReply( pucUDPPayloadBuffer, lBytes, xIdentifier ); + + /* Finished with the buffer. The zero copy interface + is being used, so the buffer must be freed by the + task. */ + FreeRTOS_ReleaseUDPPayloadBuffer( ( void * ) pucUDPPayloadBuffer ); + + if( ulIPAddress != 0UL ) + { + /* All done. */ + break; + } + } + } + else + { + /* The message was not sent so the stack will not be + releasing the zero copy - it must be released here. */ + FreeRTOS_ReleaseUDPPayloadBuffer( ( void * ) pucUDPPayloadBuffer ); + } + } + } + + /* Finished with the socket. */ + FreeRTOS_closesocket( xDNSSocket ); + } + + return ulIPAddress; +} +/*-----------------------------------------------------------*/ + +static size_t prvCreateDNSMessage( uint8_t *pucUDPPayloadBuffer, const char *pcHostName, TickType_t xIdentifier ) +{ +DNSMessage_t *pxDNSMessageHeader; +uint8_t *pucStart, *pucByte; +DNSTail_t *pxTail; +static const DNSMessage_t xDefaultPartDNSHeader = +{ + 0, /* The identifier will be overwritten. */ + dnsOUTGOING_FLAGS, /* Flags set for standard query. */ + dnsONE_QUESTION, /* One question is being asked. */ + 0, /* No replies are included. */ + 0, /* No authorities. */ + 0 /* No additional authorities. */ +}; + + /* Copy in the const part of the header. */ + memcpy( ( void * ) pucUDPPayloadBuffer, ( void * ) &xDefaultPartDNSHeader, sizeof( xDefaultPartDNSHeader ) ); + + /* Write in a unique identifier. */ + pxDNSMessageHeader = ( DNSMessage_t * ) pucUDPPayloadBuffer; + pxDNSMessageHeader->usIdentifier = ( uint16_t ) xIdentifier; + + /* Create the resource record at the end of the header. First + find the end of the header. */ + pucStart = pucUDPPayloadBuffer + sizeof( xDefaultPartDNSHeader ); + + /* Leave a gap for the first length bytes. */ + pucByte = pucStart + 1; + + /* Copy in the host name. */ + strcpy( ( char * ) pucByte, pcHostName ); + + /* Mark the end of the string. */ + pucByte += strlen( pcHostName ); + *pucByte = 0x00u; + + /* Walk the string to replace the '.' characters with byte counts. + pucStart holds the address of the byte count. Walking the string + starts after the byte count position. */ + pucByte = pucStart; + + do + { + pucByte++; + + while( ( *pucByte != 0x00 ) && ( *pucByte != '.' ) ) + { + pucByte++; + } + + /* Fill in the byte count, then move the pucStart pointer up to + the found byte position. */ + *pucStart = ( uint8_t ) ( ( uint32_t ) pucByte - ( uint32_t ) pucStart ); + ( *pucStart )--; + + pucStart = pucByte; + + } while( *pucByte != 0x00 ); + + /* Finish off the record. */ + + pxTail = (DNSTail_t *)( pucByte + 1 ); + + vSetField16( pxTail, DNSTail_t, usType, dnsTYPE_A_HOST ); /* Type A: host */ + vSetField16( pxTail, DNSTail_t, usClass, dnsCLASS_IN ); /* 1: Class IN */ + + /* Return the total size of the generated message, which is the space from + the last written byte to the beginning of the buffer. */ + return ( ( uint32_t ) pucByte - ( uint32_t ) pucUDPPayloadBuffer + 1 ) + sizeof( *pxTail ); +} +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_DNS_CACHE == 1 ) + + static uint8_t *prvReadNameField( uint8_t *pucByte, size_t xSourceLen, char *pcName, size_t xDestLen ) + { + size_t xNameLen = 0; + BaseType_t xCount; + + if( 0 == xSourceLen ) + { + return NULL; + } + + /* Determine if the name is the fully coded name, or an offset to the name + elsewhere in the message. */ + if( ( *pucByte & dnsNAME_IS_OFFSET ) == dnsNAME_IS_OFFSET ) + { + /* Jump over the two byte offset. */ + if( xSourceLen > sizeof( uint16_t ) ) + { + pucByte += sizeof( uint16_t ); + } + else + { + pucByte = NULL; + } + } + else + { + /* pucByte points to the full name. Walk over the string. */ + while( ( NULL != pucByte ) && ( *pucByte != 0x00 ) && ( xSourceLen > 1 ) ) + { + /* If this is not the first time through the loop, then add a + separator in the output. */ + if( ( xNameLen > 0 ) && ( xNameLen < ( xDestLen - 1 ) ) ) + { + pcName[ xNameLen++ ] = '.'; + } + + /* Process the first/next sub-string. */ + for( xCount = *(pucByte++), xSourceLen--; + xCount-- && xSourceLen > 1; + pucByte++, xSourceLen-- ) + { + if( xNameLen < xDestLen - 1 ) + { + pcName[ xNameLen++ ] = *( ( char * )pucByte ); + } + else + { + /* DNS name is too big for the provided buffer. */ + pucByte = NULL; + break; + } + } + } + + /* Confirm that a fully formed name was found. */ + if( NULL != pucByte ) + { + if( 0x00 == *pucByte ) + { + pucByte++; + xSourceLen--; + pcName[ xNameLen++ ] = '\0'; + } + else + { + pucByte = NULL; + } + } + } + + return pucByte; + } +#endif /* ipconfigUSE_DNS_CACHE == 1 */ +/*-----------------------------------------------------------*/ + +static uint8_t *prvSkipNameField( uint8_t *pucByte, size_t xSourceLen ) +{ + size_t xChunkLength; + + if( 0 == xSourceLen ) + { + return NULL; + } + + /* Determine if the name is the fully coded name, or an offset to the name + elsewhere in the message. */ + if( ( *pucByte & dnsNAME_IS_OFFSET ) == dnsNAME_IS_OFFSET ) + { + /* Jump over the two byte offset. */ + if( xSourceLen > sizeof( uint16_t ) ) + { + pucByte += sizeof( uint16_t ); + } + else + { + pucByte = NULL; + } + } + else + { + /* pucByte points to the full name. Walk over the string. */ + while( ( *pucByte != 0x00 ) && ( xSourceLen > 1 ) ) + { + xChunkLength = *pucByte + 1; + + if( xSourceLen > xChunkLength ) + { + xSourceLen -= xChunkLength; + pucByte += xChunkLength; + } + else + { + pucByte = NULL; + break; + } + } + + /* Confirm that a fully formed name was found. */ + if( NULL != pucByte ) + { + if( 0x00 == *pucByte ) + { + pucByte++; + } + else + { + pucByte = NULL; + } + } + } + + return pucByte; +} +/*-----------------------------------------------------------*/ + +uint32_t ulDNSHandlePacket( NetworkBufferDescriptor_t *pxNetworkBuffer ) +{ +uint8_t *pucUDPPayloadBuffer; +size_t xPlayloadBufferLength; +DNSMessage_t *pxDNSMessageHeader; + + xPlayloadBufferLength = pxNetworkBuffer->xDataLength - sizeof( UDPPacket_t ); + if ( xPlayloadBufferLength < sizeof( DNSMessage_t ) ) + { + return pdFAIL; + } + + pucUDPPayloadBuffer = pxNetworkBuffer->pucEthernetBuffer + sizeof( UDPPacket_t ); + pxDNSMessageHeader = ( DNSMessage_t * ) pucUDPPayloadBuffer; + + if( pxNetworkBuffer->xDataLength > sizeof( UDPPacket_t ) ) + { + prvParseDNSReply( pucUDPPayloadBuffer, + xPlayloadBufferLength, + ( uint32_t )pxDNSMessageHeader->usIdentifier ); + } + + /* The packet was not consumed. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_NBNS == 1 ) + + uint32_t ulNBNSHandlePacket (NetworkBufferDescriptor_t *pxNetworkBuffer ) + { + UDPPacket_t *pxUDPPacket = ( UDPPacket_t * ) pxNetworkBuffer->pucEthernetBuffer; + uint8_t *pucUDPPayloadBuffer = pxNetworkBuffer->pucEthernetBuffer + sizeof( UDPPacket_t ); + + if( pxNetworkBuffer->xDataLength > sizeof( UDPPacket_t) ) + { + prvTreatNBNS( pucUDPPayloadBuffer, + pxNetworkBuffer->xDataLength - sizeof( UDPPacket_t ), + pxUDPPacket->xIPHeader.ulSourceIPAddress ); + } + + /* The packet was not consumed. */ + return pdFAIL; + } + +#endif /* ipconfigUSE_NBNS */ +/*-----------------------------------------------------------*/ + +static uint32_t prvParseDNSReply( uint8_t *pucUDPPayloadBuffer, size_t xBufferLength, TickType_t xIdentifier ) +{ +DNSMessage_t *pxDNSMessageHeader; +DNSAnswerRecord_t *pxDNSAnswerRecord; +uint32_t ulIPAddress = 0UL; +#if( ipconfigUSE_LLMNR == 1 ) + char *pcRequestedName = NULL; +#endif +uint8_t *pucByte; +size_t xSourceBytesRemaining; +uint16_t x, usDataLength, usQuestions; +#if( ipconfigUSE_LLMNR == 1 ) + uint16_t usType = 0, usClass = 0; +#endif +#if( ipconfigUSE_DNS_CACHE == 1 ) + char pcName[ ipconfigDNS_CACHE_NAME_LENGTH ] = ""; +#endif + + /* Ensure that the buffer is of at least minimal DNS message length. */ + if( xBufferLength < sizeof( DNSMessage_t ) ) + { + return dnsPARSE_ERROR; + } + else + { + xSourceBytesRemaining = xBufferLength; + } + + /* Parse the DNS message header. */ + pxDNSMessageHeader = ( DNSMessage_t * ) pucUDPPayloadBuffer; + + if( pxDNSMessageHeader->usIdentifier == ( uint16_t ) xIdentifier ) + { + /* Start at the first byte after the header. */ + pucByte = pucUDPPayloadBuffer + sizeof( DNSMessage_t ); + xSourceBytesRemaining -= sizeof( DNSMessage_t ); + + /* Skip any question records. */ + usQuestions = FreeRTOS_ntohs( pxDNSMessageHeader->usQuestions ); + for( x = 0; x < usQuestions; x++ ) + { + #if( ipconfigUSE_LLMNR == 1 ) + { + if( x == 0 ) + { + pcRequestedName = ( char * ) pucByte; + } + } + #endif + +#if( ipconfigUSE_DNS_CACHE == 1 ) + if( x == 0 ) + { + pucByte = prvReadNameField( pucByte, + xSourceBytesRemaining, + pcName, + sizeof( pcName ) ); + + /* Check for a malformed response. */ + if( NULL == pucByte ) + { + return dnsPARSE_ERROR; + } + else + { + xSourceBytesRemaining = ( pucUDPPayloadBuffer + xBufferLength ) - pucByte; + } + } + else +#endif /* ipconfigUSE_DNS_CACHE */ + { + /* Skip the variable length pcName field. */ + pucByte = prvSkipNameField( pucByte, + xSourceBytesRemaining ); + + /* Check for a malformed response. */ + if( NULL == pucByte ) + { + return dnsPARSE_ERROR; + } + else + { + xSourceBytesRemaining = pucUDPPayloadBuffer + xBufferLength - pucByte; + } + } + + /* Check the remaining buffer size. */ + if( xSourceBytesRemaining >= sizeof( uint32_t ) ) + { + #if( ipconfigUSE_LLMNR == 1 ) + { + /* usChar2u16 returns value in host endianness */ + usType = usChar2u16( pucByte ); + usClass = usChar2u16( pucByte + 2 ); + } + #endif /* ipconfigUSE_LLMNR */ + + /* Skip the type and class fields. */ + pucByte += sizeof( uint32_t ); + xSourceBytesRemaining -= sizeof( uint32_t ); + } + else + { + /* Malformed response. */ + return dnsPARSE_ERROR; + } + } + + /* Search through the answer records. */ + pxDNSMessageHeader->usAnswers = FreeRTOS_ntohs( pxDNSMessageHeader->usAnswers ); + + if( ( pxDNSMessageHeader->usFlags & dnsRX_FLAGS_MASK ) == dnsEXPECTED_RX_FLAGS ) + { + for( x = 0; x < pxDNSMessageHeader->usAnswers; x++ ) + { + pucByte = prvSkipNameField( pucByte, + xSourceBytesRemaining ); + + /* Check for a malformed response. */ + if( NULL == pucByte ) + { + return dnsPARSE_ERROR; + } + else + { + xSourceBytesRemaining = pucUDPPayloadBuffer + xBufferLength - pucByte; + } + + /* Is there enough data for an IPv4 A record answer and, if so, + is this an A record? */ + if( xSourceBytesRemaining >= sizeof( DNSAnswerRecord_t ) + sizeof( uint32_t ) && + usChar2u16( pucByte ) == dnsTYPE_A_HOST ) + { + /* This is the required record type and is of sufficient size. */ + pxDNSAnswerRecord = ( DNSAnswerRecord_t * )pucByte; + + /* Sanity check the data length of an IPv4 answer. */ + if( FreeRTOS_ntohs( pxDNSAnswerRecord->usDataLength ) == sizeof( uint32_t ) ) + { + /* Copy the IP address out of the record. */ + memcpy( &ulIPAddress, + pucByte + sizeof( DNSAnswerRecord_t ), + sizeof( uint32_t ) ); + + #if( ipconfigUSE_DNS_CACHE == 1 ) + { + prvProcessDNSCache( pcName, &ulIPAddress, pxDNSAnswerRecord->ulTTL, pdFALSE ); + } + #endif /* ipconfigUSE_DNS_CACHE */ + #if( ipconfigDNS_USE_CALLBACKS != 0 ) + { + /* See if any asynchronous call was made to FreeRTOS_gethostbyname_a() */ + vDNSDoCallback( ( TickType_t ) pxDNSMessageHeader->usIdentifier, pcName, ulIPAddress ); + } + #endif /* ipconfigDNS_USE_CALLBACKS != 0 */ + } + + pucByte += sizeof( DNSAnswerRecord_t ) + sizeof( uint32_t ); + xSourceBytesRemaining -= ( sizeof( DNSAnswerRecord_t ) + sizeof( uint32_t ) ); + break; + } + else if( xSourceBytesRemaining >= sizeof( DNSAnswerRecord_t ) ) + { + /* It's not an A record, so skip it. Get the header location + and then jump over the header. */ + pxDNSAnswerRecord = ( DNSAnswerRecord_t * )pucByte; + pucByte += sizeof( DNSAnswerRecord_t ); + xSourceBytesRemaining -= sizeof( DNSAnswerRecord_t ); + + /* Determine the length of the answer data from the header. */ + usDataLength = FreeRTOS_ntohs( pxDNSAnswerRecord->usDataLength ); + + /* Jump over the answer. */ + if( xSourceBytesRemaining >= usDataLength ) + { + pucByte += usDataLength; + xSourceBytesRemaining -= usDataLength; + } + else + { + /* Malformed response. */ + return dnsPARSE_ERROR; + } + } + } + } +#if( ipconfigUSE_LLMNR == 1 ) + else if( usQuestions && ( usType == dnsTYPE_A_HOST ) && ( usClass == dnsCLASS_IN ) ) + { + /* If this is not a reply to our DNS request, it might an LLMNR + request. */ + if( xApplicationDNSQueryHook ( ( pcRequestedName + 1 ) ) ) + { + int16_t usLength; + NetworkBufferDescriptor_t *pxNewBuffer = NULL; + NetworkBufferDescriptor_t *pxNetworkBuffer = pxUDPPayloadBuffer_to_NetworkBuffer( pucUDPPayloadBuffer ); + LLMNRAnswer_t *pxAnswer; + + if( ( xBufferAllocFixedSize == pdFALSE ) && ( pxNetworkBuffer != NULL ) ) + { + BaseType_t xDataLength = xBufferLength + sizeof( UDPHeader_t ) + sizeof( EthernetHeader_t ) + sizeof( IPHeader_t ); + + /* The field xDataLength was set to the length of the UDP payload. + The answer (reply) will be longer than the request, so the packet + must be duplicaed into a bigger buffer */ + pxNetworkBuffer->xDataLength = xDataLength; + pxNewBuffer = pxDuplicateNetworkBufferWithDescriptor( pxNetworkBuffer, xDataLength + 16 ); + if( pxNewBuffer != NULL ) + { + BaseType_t xOffset1, xOffset2; + + xOffset1 = ( BaseType_t ) ( pucByte - pucUDPPayloadBuffer ); + xOffset2 = ( BaseType_t ) ( ( ( uint8_t * ) pcRequestedName ) - pucUDPPayloadBuffer ); + + pxNetworkBuffer = pxNewBuffer; + pucUDPPayloadBuffer = pxNetworkBuffer->pucEthernetBuffer + ipUDP_PAYLOAD_OFFSET_IPv4; + + pucByte = pucUDPPayloadBuffer + xOffset1; + pcRequestedName = ( char * ) ( pucUDPPayloadBuffer + xOffset2 ); + pxDNSMessageHeader = ( DNSMessage_t * ) pucUDPPayloadBuffer; + + } + else + { + /* Just to indicate that the message may not be answered. */ + pxNetworkBuffer = NULL; + } + } + if( pxNetworkBuffer != NULL ) + { + pxAnswer = (LLMNRAnswer_t *)pucByte; + + /* We leave 'usIdentifier' and 'usQuestions' untouched */ + vSetField16( pxDNSMessageHeader, DNSMessage_t, usFlags, dnsLLMNR_FLAGS_IS_REPONSE ); /* Set the response flag */ + vSetField16( pxDNSMessageHeader, DNSMessage_t, usAnswers, 1 ); /* Provide a single answer */ + vSetField16( pxDNSMessageHeader, DNSMessage_t, usAuthorityRRs, 0 ); /* No authority */ + vSetField16( pxDNSMessageHeader, DNSMessage_t, usAdditionalRRs, 0 ); /* No additional info */ + + pxAnswer->ucNameCode = dnsNAME_IS_OFFSET; + pxAnswer->ucNameOffset = ( uint8_t )( pcRequestedName - ( char * ) pucUDPPayloadBuffer ); + + vSetField16( pxAnswer, LLMNRAnswer_t, usType, dnsTYPE_A_HOST ); /* Type A: host */ + vSetField16( pxAnswer, LLMNRAnswer_t, usClass, dnsCLASS_IN ); /* 1: Class IN */ + vSetField32( pxAnswer, LLMNRAnswer_t, ulTTL, dnsLLMNR_TTL_VALUE ); + vSetField16( pxAnswer, LLMNRAnswer_t, usDataLength, 4 ); + vSetField32( pxAnswer, LLMNRAnswer_t, ulIPAddress, FreeRTOS_ntohl( *ipLOCAL_IP_ADDRESS_POINTER ) ); + + usLength = ( int16_t ) ( sizeof( *pxAnswer ) + ( size_t ) ( pucByte - pucUDPPayloadBuffer ) ); + + prvReplyDNSMessage( pxNetworkBuffer, usLength ); + + if( pxNewBuffer != NULL ) + { + vReleaseNetworkBufferAndDescriptor( pxNewBuffer ); + } + } + } + } +#endif /* ipconfigUSE_LLMNR == 1 */ + } + + return ulIPAddress; +} +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_NBNS == 1 ) + + static void prvTreatNBNS( uint8_t *pucUDPPayloadBuffer, size_t xBufferLength, uint32_t ulIPAddress ) + { + uint16_t usFlags, usType, usClass; + uint8_t *pucSource, *pucTarget; + uint8_t ucByte; + uint8_t ucNBNSName[ 17 ]; + + /* Check for minimum buffer size. */ + if( xBufferLength < sizeof( NBNSRequest_t ) ) + { + return; + } + + /* Read the request flags in host endianness. */ + usFlags = usChar2u16( pucUDPPayloadBuffer + offsetof( NBNSRequest_t, usFlags ) ); + + if( ( usFlags & dnsNBNS_FLAGS_OPCODE_MASK ) == dnsNBNS_FLAGS_OPCODE_QUERY ) + { + usType = usChar2u16( pucUDPPayloadBuffer + offsetof( NBNSRequest_t, usType ) ); + usClass = usChar2u16( pucUDPPayloadBuffer + offsetof( NBNSRequest_t, usClass ) ); + + /* Not used for now */ + ( void )usClass; + /* For NBNS a name is 16 bytes long, written with capitals only. + Make sure that the copy is terminated with a zero. */ + pucTarget = ucNBNSName + sizeof(ucNBNSName ) - 2; + pucTarget[ 1 ] = '\0'; + + /* Start with decoding the last 2 bytes. */ + pucSource = pucUDPPayloadBuffer + ( offsetof( NBNSRequest_t, ucName ) + ( dnsNBNS_ENCODED_NAME_LENGTH - 2 ) ); + + for( ;; ) + { + ucByte = ( uint8_t ) ( ( ( pucSource[ 0 ] - 0x41 ) << 4 ) | ( pucSource[ 1 ] - 0x41 ) ); + + /* Make sure there are no trailing spaces in the name. */ + if( ( ucByte == ' ' ) && ( pucTarget[ 1 ] == '\0' ) ) + { + ucByte = '\0'; + } + + *pucTarget = ucByte; + + if( pucTarget == ucNBNSName ) + { + break; + } + + pucTarget -= 1; + pucSource -= 2; + } + + #if( ipconfigUSE_DNS_CACHE == 1 ) + { + if( ( usFlags & dnsNBNS_FLAGS_RESPONSE ) != 0 ) + { + /* If this is a response from another device, + add the name to the DNS cache */ + prvProcessDNSCache( ( char * ) ucNBNSName, &ulIPAddress, 0, pdFALSE ); + } + } + #else + { + /* Avoid compiler warnings. */ + ( void ) ulIPAddress; + } + #endif /* ipconfigUSE_DNS_CACHE */ + + if( ( ( usFlags & dnsNBNS_FLAGS_RESPONSE ) == 0 ) && + ( usType == dnsNBNS_TYPE_NET_BIOS ) && + ( xApplicationDNSQueryHook( ( const char * ) ucNBNSName ) != pdFALSE ) ) + { + uint16_t usLength; + DNSMessage_t *pxMessage; + NBNSAnswer_t *pxAnswer; + + /* Someone is looking for a device with ucNBNSName, + prepare a positive reply. */ + NetworkBufferDescriptor_t *pxNetworkBuffer = pxUDPPayloadBuffer_to_NetworkBuffer( pucUDPPayloadBuffer ); + + if( ( xBufferAllocFixedSize == pdFALSE ) && ( pxNetworkBuffer != NULL ) ) + { + NetworkBufferDescriptor_t *pxNewBuffer; + BaseType_t xDataLength = pxNetworkBuffer->xDataLength + sizeof( UDPHeader_t ) + + sizeof( EthernetHeader_t ) + sizeof( IPHeader_t ); + + /* The field xDataLength was set to the length of the UDP payload. + The answer (reply) will be longer than the request, so the packet + must be duplicated into a bigger buffer */ + pxNetworkBuffer->xDataLength = xDataLength; + pxNewBuffer = pxDuplicateNetworkBufferWithDescriptor( pxNetworkBuffer, xDataLength + 16 ); + if( pxNewBuffer != NULL ) + { + pucUDPPayloadBuffer = pxNewBuffer->pucEthernetBuffer + sizeof( UDPPacket_t ); + pxNetworkBuffer = pxNewBuffer; + } + else + { + /* Just prevent that a reply will be sent */ + pxNetworkBuffer = NULL; + } + } + + /* Should not occur: pucUDPPayloadBuffer is part of a xNetworkBufferDescriptor */ + if( pxNetworkBuffer != NULL ) + { + pxMessage = (DNSMessage_t *)pucUDPPayloadBuffer; + + /* As the fields in the structures are not word-aligned, we have to + copy the values byte-by-byte using macro's vSetField16() and vSetField32() */ + vSetField16( pxMessage, DNSMessage_t, usFlags, dnsNBNS_QUERY_RESPONSE_FLAGS ); /* 0x8500 */ + vSetField16( pxMessage, DNSMessage_t, usQuestions, 0 ); + vSetField16( pxMessage, DNSMessage_t, usAnswers, 1 ); + vSetField16( pxMessage, DNSMessage_t, usAuthorityRRs, 0 ); + vSetField16( pxMessage, DNSMessage_t, usAdditionalRRs, 0 ); + + pxAnswer = (NBNSAnswer_t *)( pucUDPPayloadBuffer + offsetof( NBNSRequest_t, usType ) ); + + vSetField16( pxAnswer, NBNSAnswer_t, usType, usType ); /* Type */ + vSetField16( pxAnswer, NBNSAnswer_t, usClass, dnsNBNS_CLASS_IN ); /* Class */ + vSetField32( pxAnswer, NBNSAnswer_t, ulTTL, dnsNBNS_TTL_VALUE ); + vSetField16( pxAnswer, NBNSAnswer_t, usDataLength, 6 ); /* 6 bytes including the length field */ + vSetField16( pxAnswer, NBNSAnswer_t, usNbFlags, dnsNBNS_NAME_FLAGS ); + vSetField32( pxAnswer, NBNSAnswer_t, ulIPAddress, FreeRTOS_ntohl( *ipLOCAL_IP_ADDRESS_POINTER ) ); + + usLength = ( uint16_t ) ( offsetof( NBNSRequest_t, usType ) + sizeof( NBNSAnswer_t ) ); + + prvReplyDNSMessage( pxNetworkBuffer, usLength ); + } + } + } + } + +#endif /* ipconfigUSE_NBNS */ +/*-----------------------------------------------------------*/ + +static Socket_t prvCreateDNSSocket( void ) +{ +Socket_t xSocket = NULL; +struct freertos_sockaddr xAddress; +BaseType_t xReturn; +TickType_t xTimeoutTime = pdMS_TO_TICKS( 200 ); + + /* This must be the first time this function has been called. Create + the socket. */ + xSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP ); + + /* Auto bind the port. */ + xAddress.sin_port = 0u; + xReturn = FreeRTOS_bind( xSocket, &xAddress, sizeof( xAddress ) ); + + /* Check the bind was successful, and clean up if not. */ + if( xReturn != 0 ) + { + FreeRTOS_closesocket( xSocket ); + xSocket = NULL; + } + else + { + /* Set the send and receive timeouts. */ + FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_RCVTIMEO, ( void * ) &xTimeoutTime, sizeof( TickType_t ) ); + FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_SNDTIMEO, ( void * ) &xTimeoutTime, sizeof( TickType_t ) ); + } + + return xSocket; +} +/*-----------------------------------------------------------*/ + +#if( ( ipconfigUSE_NBNS == 1 ) || ( ipconfigUSE_LLMNR == 1 ) ) + + static void prvReplyDNSMessage( NetworkBufferDescriptor_t *pxNetworkBuffer, BaseType_t lNetLength ) + { + UDPPacket_t *pxUDPPacket; + IPHeader_t *pxIPHeader; + UDPHeader_t *pxUDPHeader; + + pxUDPPacket = (UDPPacket_t *) pxNetworkBuffer->pucEthernetBuffer; + pxIPHeader = &pxUDPPacket->xIPHeader; + pxUDPHeader = &pxUDPPacket->xUDPHeader; + /* HT: started using defines like 'ipSIZE_OF_xxx' */ + pxIPHeader->usLength = FreeRTOS_htons( lNetLength + ipSIZE_OF_IPv4_HEADER + ipSIZE_OF_UDP_HEADER ); + /* HT:endian: should not be translated, copying from packet to packet */ + pxIPHeader->ulDestinationIPAddress = pxIPHeader->ulSourceIPAddress; + pxIPHeader->ulSourceIPAddress = *ipLOCAL_IP_ADDRESS_POINTER; + pxIPHeader->ucTimeToLive = ipconfigUDP_TIME_TO_LIVE; + pxIPHeader->usIdentification = FreeRTOS_htons( usPacketIdentifier ); + usPacketIdentifier++; + pxUDPHeader->usLength = FreeRTOS_htons( lNetLength + ipSIZE_OF_UDP_HEADER ); + vFlip_16( pxUDPPacket->xUDPHeader.usSourcePort, pxUDPPacket->xUDPHeader.usDestinationPort ); + + #if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM == 0 ) + { + /* calculate the IP header checksum */ + pxIPHeader->usHeaderChecksum = 0x00; + pxIPHeader->usHeaderChecksum = usGenerateChecksum( 0UL, ( uint8_t * ) &( pxIPHeader->ucVersionHeaderLength ), ipSIZE_OF_IPv4_HEADER ); + pxIPHeader->usHeaderChecksum = ~FreeRTOS_htons( pxIPHeader->usHeaderChecksum ); + + /* calculate the UDP checksum for outgoing package */ + usGenerateProtocolChecksum( ( uint8_t* ) pxUDPPacket, lNetLength, pdTRUE ); + } + #endif + + /* Important: tell NIC driver how many bytes must be sent */ + pxNetworkBuffer->xDataLength = ( size_t ) ( lNetLength + ipSIZE_OF_IPv4_HEADER + ipSIZE_OF_UDP_HEADER + ipSIZE_OF_ETH_HEADER ); + + /* This function will fill in the eth addresses and send the packet */ + vReturnEthernetFrame( pxNetworkBuffer, pdFALSE ); + } + +#endif /* ipconfigUSE_NBNS == 1 || ipconfigUSE_LLMNR == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_DNS_CACHE == 1 ) + + static void prvProcessDNSCache( const char *pcName, uint32_t *pulIP, uint32_t ulTTL, BaseType_t xLookUp ) + { + BaseType_t x; + BaseType_t xFound = pdFALSE; + uint32_t ulCurrentTimeSeconds = ( xTaskGetTickCount() / portTICK_PERIOD_MS ) / 1000; + static BaseType_t xFreeEntry = 0; + + /* For each entry in the DNS cache table. */ + for( x = 0; x < ipconfigDNS_CACHE_ENTRIES; x++ ) + { + if( xDNSCache[ x ].pcName[ 0 ] == 0 ) + { + break; + } + + if( 0 == strcmp( xDNSCache[ x ].pcName, pcName ) ) + { + /* Is this function called for a lookup or to add/update an IP address? */ + if( xLookUp != pdFALSE ) + { + /* Confirm that the record is still fresh. */ + if( ulCurrentTimeSeconds < ( xDNSCache[ x ].ulTimeWhenAddedInSeconds + FreeRTOS_ntohl( xDNSCache[ x ].ulTTL ) ) ) + { + *pulIP = xDNSCache[ x ].ulIPAddress; + } + else + { + /* Age out the old cached record. */ + xDNSCache[ x ].pcName[ 0 ] = 0; + } + } + else + { + xDNSCache[ x ].ulIPAddress = *pulIP; + xDNSCache[ x ].ulTTL = ulTTL; + xDNSCache[ x ].ulTimeWhenAddedInSeconds = ulCurrentTimeSeconds; + } + + xFound = pdTRUE; + break; + } + } + + if( xFound == pdFALSE ) + { + if( xLookUp != pdFALSE ) + { + *pulIP = 0; + } + else + { + /* Add or update the item. */ + if( strlen( pcName ) < ipconfigDNS_CACHE_NAME_LENGTH ) + { + strcpy( xDNSCache[ xFreeEntry ].pcName, pcName ); + + xDNSCache[ xFreeEntry ].ulIPAddress = *pulIP; + xDNSCache[ xFreeEntry ].ulTTL = ulTTL; + xDNSCache[ xFreeEntry ].ulTimeWhenAddedInSeconds = ulCurrentTimeSeconds; + + xFreeEntry++; + if( xFreeEntry == ipconfigDNS_CACHE_ENTRIES ) + { + xFreeEntry = 0; + } + } + } + } + + if( ( xLookUp == 0 ) || ( *pulIP != 0 ) ) + { + FreeRTOS_debug_printf( ( "prvProcessDNSCache: %s: '%s' @ %lxip\n", xLookUp ? "look-up" : "add", pcName, FreeRTOS_ntohl( *pulIP ) ) ); + } + } + +#endif /* ipconfigUSE_DNS_CACHE */ + +#endif /* ipconfigUSE_DNS != 0 */ + +/*-----------------------------------------------------------*/ + +/* Provide access to private members for testing. */ +#ifdef AMAZON_FREERTOS_ENABLE_UNIT_TESTS + #include "aws_freertos_tcp_test_access_dns_define.h" +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_IP.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_IP.c new file mode 100644 index 0000000..325a69a --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_IP.c @@ -0,0 +1,2318 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +/* Standard includes. */ +#include +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_IP_Private.h" +#include "FreeRTOS_ARP.h" +#include "FreeRTOS_UDP_IP.h" +#include "FreeRTOS_TCP_IP.h" +#include "FreeRTOS_DHCP.h" +#include "NetworkInterface.h" +#include "NetworkBufferManagement.h" +#include "FreeRTOS_DNS.h" + + +/* Used to ensure the structure packing is having the desired effect. The +'volatile' is used to prevent compiler warnings about comparing a constant with +a constant. */ +#define ipEXPECTED_EthernetHeader_t_SIZE ( ( size_t ) 14 ) +#define ipEXPECTED_ARPHeader_t_SIZE ( ( size_t ) 28 ) +#define ipEXPECTED_IPHeader_t_SIZE ( ( size_t ) 20 ) +#define ipEXPECTED_IGMPHeader__SIZE ( ( size_t ) 8 ) +#define ipEXPECTED_ICMPHeader_t_SIZE ( ( size_t ) 8 ) +#define ipEXPECTED_UDPHeader_t_SIZE ( ( size_t ) 8 ) +#define ipEXPECTED_TCPHeader_t_SIZE ( ( size_t ) 20 ) + + +/* ICMP protocol definitions. */ +#define ipICMP_ECHO_REQUEST ( ( uint8_t ) 8 ) +#define ipICMP_ECHO_REPLY ( ( uint8_t ) 0 ) + + +/* Time delay between repeated attempts to initialise the network hardware. */ +#define ipINITIALISATION_RETRY_DELAY ( pdMS_TO_TICKS( 3000 ) ) + +/* Defines how often the ARP timer callback function is executed. The time is +shorted in the Windows simulator as simulated time is not real time. */ +#ifndef ipARP_TIMER_PERIOD_MS + #ifdef _WINDOWS_ + #define ipARP_TIMER_PERIOD_MS ( 500 ) /* For windows simulator builds. */ + #else + #define ipARP_TIMER_PERIOD_MS ( 10000 ) + #endif +#endif + +#ifndef iptraceIP_TASK_STARTING + #define iptraceIP_TASK_STARTING() do {} while( 0 ) +#endif + +#if( ( ipconfigUSE_TCP == 1 ) && !defined( ipTCP_TIMER_PERIOD_MS ) ) + /* When initialising the TCP timer, + give it an initial time-out of 1 second. */ + #define ipTCP_TIMER_PERIOD_MS ( 1000 ) +#endif + +/* If ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES is set to 1, then the Ethernet +driver will filter incoming packets and only pass the stack those packets it +considers need processing. In this case ipCONSIDER_FRAME_FOR_PROCESSING() can +be #defined away. If ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES is set to 0 +then the Ethernet driver will pass all received packets to the stack, and the +stack must do the filtering itself. In this case ipCONSIDER_FRAME_FOR_PROCESSING +needs to call eConsiderFrameForProcessing. */ +#if ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES == 0 + #define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eConsiderFrameForProcessing( ( pucEthernetBuffer ) ) +#else + #define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eProcessBuffer +#endif + +/* The character used to fill ICMP echo requests, and therefore also the +character expected to fill ICMP echo replies. */ +#define ipECHO_DATA_FILL_BYTE 'x' + +#if( ipconfigBYTE_ORDER == pdFREERTOS_LITTLE_ENDIAN ) + /* The bits in the two byte IP header field that make up the fragment offset value. */ + #define ipFRAGMENT_OFFSET_BIT_MASK ( ( uint16_t ) 0xff0f ) +#else + /* The bits in the two byte IP header field that make up the fragment offset value. */ + #define ipFRAGMENT_OFFSET_BIT_MASK ( ( uint16_t ) 0x0fff ) +#endif /* ipconfigBYTE_ORDER */ + +/* The maximum time the IP task is allowed to remain in the Blocked state if no +events are posted to the network event queue. */ +#ifndef ipconfigMAX_IP_TASK_SLEEP_TIME + #define ipconfigMAX_IP_TASK_SLEEP_TIME ( pdMS_TO_TICKS( 10000UL ) ) +#endif + +/* When a new TCP connection is established, the value of +'ulNextInitialSequenceNumber' will be used as the initial sequence number. It +is very important that at start-up, 'ulNextInitialSequenceNumber' contains a +random value. Also its value must be increased continuously in time, to prevent +a third party guessing the next sequence number and take-over a TCP connection. +It is advised to increment it by 1 ever 4us, which makes about 256 times +per ms: */ +#define ipINITIAL_SEQUENCE_NUMBER_FACTOR 256UL + +/* Returned as the (invalid) checksum when the protocol being checked is not +handled. The value is chosen simply to be easy to spot when debugging. */ +#define ipUNHANDLED_PROTOCOL 0x4321u + +/* Returned to indicate a valid checksum when the checksum does not need to be +calculated. */ +#define ipCORRECT_CRC 0xffffu + +/* Returned as the (invalid) checksum when the length of the data being checked +had an invalid length. */ +#define ipINVALID_LENGTH 0x1234u + +/*-----------------------------------------------------------*/ + +typedef struct xIP_TIMER +{ + uint32_t + bActive : 1, /* This timer is running and must be processed. */ + bExpired : 1; /* Timer has expired and a task must be processed. */ + TimeOut_t xTimeOut; + TickType_t ulRemainingTime; + TickType_t ulReloadTime; +} IPTimer_t; + +/* Used in checksum calculation. */ +typedef union _xUnion32 +{ + uint32_t u32; + uint16_t u16[ 2 ]; + uint8_t u8[ 4 ]; +} xUnion32; + +/* Used in checksum calculation. */ +typedef union _xUnionPtr +{ + uint32_t *u32ptr; + uint16_t *u16ptr; + uint8_t *u8ptr; +} xUnionPtr; + +/*-----------------------------------------------------------*/ + +/* + * The main TCP/IP stack processing task. This task receives commands/events + * from the network hardware drivers and tasks that are using sockets. It also + * maintains a set of protocol timers. + */ +static void prvIPTask( void *pvParameters ); + +/* + * Called when new data is available from the network interface. + */ +static void prvProcessEthernetPacket( NetworkBufferDescriptor_t * const pxNetworkBuffer ); + +/* + * Process incoming IP packets. + */ +static eFrameProcessingResult_t prvProcessIPPacket( IPPacket_t * const pxIPPacket, NetworkBufferDescriptor_t * const pxNetworkBuffer ); + +#if ( ipconfigREPLY_TO_INCOMING_PINGS == 1 ) || ( ipconfigSUPPORT_OUTGOING_PINGS == 1 ) + /* + * Process incoming ICMP packets. + */ + static eFrameProcessingResult_t prvProcessICMPPacket( ICMPPacket_t * const pxICMPPacket ); +#endif /* ( ipconfigREPLY_TO_INCOMING_PINGS == 1 ) || ( ipconfigSUPPORT_OUTGOING_PINGS == 1 ) */ + +/* + * Turns around an incoming ping request to convert it into a ping reply. + */ +#if ( ipconfigREPLY_TO_INCOMING_PINGS == 1 ) + static eFrameProcessingResult_t prvProcessICMPEchoRequest( ICMPPacket_t * const pxICMPPacket ); +#endif /* ipconfigREPLY_TO_INCOMING_PINGS */ + +/* + * Processes incoming ping replies. The application callback function + * vApplicationPingReplyHook() is called with the results. + */ +#if ( ipconfigSUPPORT_OUTGOING_PINGS == 1 ) + static void prvProcessICMPEchoReply( ICMPPacket_t * const pxICMPPacket ); +#endif /* ipconfigSUPPORT_OUTGOING_PINGS */ + +/* + * Called to create a network connection when the stack is first started, or + * when the network connection is lost. + */ +static void prvProcessNetworkDownEvent( void ); + +/* + * Checks the ARP, DHCP and TCP timers to see if any periodic or timeout + * processing is required. + */ +static void prvCheckNetworkTimers( void ); + +/* + * Determine how long the IP task can sleep for, which depends on when the next + * periodic or timeout processing must be performed. + */ +static TickType_t prvCalculateSleepTime( void ); + +/* + * The network card driver has received a packet. In the case that it is part + * of a linked packet chain, walk through it to handle every message. + */ +static void prvHandleEthernetPacket( NetworkBufferDescriptor_t *pxBuffer ); + +/* + * Utility functions for the light weight IP timers. + */ +static void prvIPTimerStart( IPTimer_t *pxTimer, TickType_t xTime ); +static BaseType_t prvIPTimerCheck( IPTimer_t *pxTimer ); +static void prvIPTimerReload( IPTimer_t *pxTimer, TickType_t xTime ); + +static eFrameProcessingResult_t prvAllowIPPacket( const IPPacket_t * const pxIPPacket, + NetworkBufferDescriptor_t * const pxNetworkBuffer, UBaseType_t uxHeaderLength ); + +/*-----------------------------------------------------------*/ + +/* The queue used to pass events into the IP-task for processing. */ +QueueHandle_t xNetworkEventQueue = NULL; + +/*_RB_ Requires comment. */ +uint16_t usPacketIdentifier = 0U; + +/* For convenience, a MAC address of all 0xffs is defined const for quick +reference. */ +const MACAddress_t xBroadcastMACAddress = { { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff } }; + +/* Structure that stores the netmask, gateway address and DNS server addresses. */ +NetworkAddressingParameters_t xNetworkAddressing = { 0, 0, 0, 0, 0 }; + +/* Default values for the above struct in case DHCP +does not lead to a confirmed request. */ +NetworkAddressingParameters_t xDefaultAddressing = { 0, 0, 0, 0, 0 }; + +/* Used to ensure network down events cannot be missed when they cannot be +posted to the network event queue because the network event queue is already +full. */ +static BaseType_t xNetworkDownEventPending = pdFALSE; + +/* Stores the handle of the task that handles the stack. The handle is used +(indirectly) by some utility function to determine if the utility function is +being called by a task (in which case it is ok to block) or by the IP task +itself (in which case it is not ok to block). */ +static TaskHandle_t xIPTaskHandle = NULL; + +#if( ipconfigUSE_TCP != 0 ) + /* Set to a non-zero value if one or more TCP message have been processed + within the last round. */ + static BaseType_t xProcessedTCPMessage; +#endif + +/* Simple set to pdTRUE or pdFALSE depending on whether the network is up or +down (connected, not connected) respectively. */ +static BaseType_t xNetworkUp = pdFALSE; + +/* +A timer for each of the following processes, all of which need attention on a +regular basis: + 1. ARP, to check its table entries + 2. DPHC, to send requests and to renew a reservation + 3. TCP, to check for timeouts, resends + 4. DNS, to check for timeouts when looking-up a domain. + */ +static IPTimer_t xARPTimer; +#if( ipconfigUSE_DHCP != 0 ) + static IPTimer_t xDHCPTimer; +#endif +#if( ipconfigUSE_TCP != 0 ) + static IPTimer_t xTCPTimer; +#endif +#if( ipconfigDNS_USE_CALLBACKS != 0 ) + static IPTimer_t xDNSTimer; +#endif + +/* Set to pdTRUE when the IP task is ready to start processing packets. */ +static BaseType_t xIPTaskInitialised = pdFALSE; + +#if( ipconfigCHECK_IP_QUEUE_SPACE != 0 ) + /* Keep track of the lowest amount of space in 'xNetworkEventQueue'. */ + static UBaseType_t uxQueueMinimumSpace = ipconfigEVENT_QUEUE_LENGTH; +#endif + +/*-----------------------------------------------------------*/ + +static void prvIPTask( void *pvParameters ) +{ +IPStackEvent_t xReceivedEvent; +TickType_t xNextIPSleep; +FreeRTOS_Socket_t *pxSocket; +struct freertos_sockaddr xAddress; + + /* Just to prevent compiler warnings about unused parameters. */ + ( void ) pvParameters; + + /* A possibility to set some additional task properties. */ + iptraceIP_TASK_STARTING(); + + /* Generate a dummy message to say that the network connection has gone + down. This will cause this task to initialise the network interface. After + this it is the responsibility of the network interface hardware driver to + send this message if a previously connected network is disconnected. */ + FreeRTOS_NetworkDown(); + + #if( ipconfigUSE_TCP == 1 ) + { + /* Initialise the TCP timer. */ + prvIPTimerReload( &xTCPTimer, pdMS_TO_TICKS( ipTCP_TIMER_PERIOD_MS ) ); + } + #endif + + /* Initialisation is complete and events can now be processed. */ + xIPTaskInitialised = pdTRUE; + + FreeRTOS_debug_printf( ( "prvIPTask started\n" ) ); + + /* Loop, processing IP events. */ + for( ;; ) + { + ipconfigWATCHDOG_TIMER(); + + /* Check the ARP, DHCP and TCP timers to see if there is any periodic + or timeout processing to perform. */ + prvCheckNetworkTimers(); + + /* Calculate the acceptable maximum sleep time. */ + xNextIPSleep = prvCalculateSleepTime(); + + /* Wait until there is something to do. If the following call exits + * due to a time out rather than a message being received, set a + * 'NoEvent' value. */ + if ( xQueueReceive( xNetworkEventQueue, ( void * ) &xReceivedEvent, xNextIPSleep ) == pdFALSE ) + { + xReceivedEvent.eEventType = eNoEvent; + } + + #if( ipconfigCHECK_IP_QUEUE_SPACE != 0 ) + { + if( xReceivedEvent.eEventType != eNoEvent ) + { + UBaseType_t uxCount; + + uxCount = uxQueueSpacesAvailable( xNetworkEventQueue ); + if( uxQueueMinimumSpace > uxCount ) + { + uxQueueMinimumSpace = uxCount; + } + } + } + #endif /* ipconfigCHECK_IP_QUEUE_SPACE */ + + iptraceNETWORK_EVENT_RECEIVED( xReceivedEvent.eEventType ); + + switch( xReceivedEvent.eEventType ) + { + case eNetworkDownEvent : + /* Attempt to establish a connection. */ + xNetworkUp = pdFALSE; + prvProcessNetworkDownEvent(); + break; + + case eNetworkRxEvent: + /* The network hardware driver has received a new packet. A + pointer to the received buffer is located in the pvData member + of the received event structure. */ + prvHandleEthernetPacket( ( NetworkBufferDescriptor_t * ) ( xReceivedEvent.pvData ) ); + break; + + case eARPTimerEvent : + /* The ARP timer has expired, process the ARP cache. */ + vARPAgeCache(); + break; + + case eSocketBindEvent: + /* FreeRTOS_bind (a user API) wants the IP-task to bind a socket + to a port. The port number is communicated in the socket field + usLocalPort. vSocketBind() will actually bind the socket and the + API will unblock as soon as the eSOCKET_BOUND event is + triggered. */ + pxSocket = ( FreeRTOS_Socket_t * ) ( xReceivedEvent.pvData ); + xAddress.sin_addr = 0u; /* For the moment. */ + xAddress.sin_port = FreeRTOS_ntohs( pxSocket->usLocalPort ); + pxSocket->usLocalPort = 0u; + vSocketBind( pxSocket, &xAddress, sizeof( xAddress ), pdFALSE ); + + /* Before 'eSocketBindEvent' was sent it was tested that + ( xEventGroup != NULL ) so it can be used now to wake up the + user. */ + pxSocket->xEventBits |= eSOCKET_BOUND; + vSocketWakeUpUser( pxSocket ); + break; + + case eSocketCloseEvent : + /* The user API FreeRTOS_closesocket() has sent a message to the + IP-task to actually close a socket. This is handled in + vSocketClose(). As the socket gets closed, there is no way to + report back to the API, so the API won't wait for the result */ + vSocketClose( ( FreeRTOS_Socket_t * ) ( xReceivedEvent.pvData ) ); + break; + + case eStackTxEvent : + /* The network stack has generated a packet to send. A + pointer to the generated buffer is located in the pvData + member of the received event structure. */ + vProcessGeneratedUDPPacket( ( NetworkBufferDescriptor_t * ) ( xReceivedEvent.pvData ) ); + break; + + case eDHCPEvent: + /* The DHCP state machine needs processing. */ + #if( ipconfigUSE_DHCP == 1 ) + { + vDHCPProcess( pdFALSE ); + } + #endif /* ipconfigUSE_DHCP */ + break; + + case eSocketSelectEvent : + /* FreeRTOS_select() has got unblocked by a socket event, + vSocketSelect() will check which sockets actually have an event + and update the socket field xSocketBits. */ + #if( ipconfigSUPPORT_SELECT_FUNCTION == 1 ) + { + vSocketSelect( ( SocketSelect_t * ) ( xReceivedEvent.pvData ) ); + } + #endif /* ipconfigSUPPORT_SELECT_FUNCTION == 1 */ + break; + + case eSocketSignalEvent : + #if( ipconfigSUPPORT_SIGNALS != 0 ) + { + /* Some task wants to signal the user of this socket in + order to interrupt a call to recv() or a call to select(). */ + FreeRTOS_SignalSocket( ( Socket_t ) xReceivedEvent.pvData ); + } + #endif /* ipconfigSUPPORT_SIGNALS */ + break; + + case eTCPTimerEvent : + #if( ipconfigUSE_TCP == 1 ) + { + /* Simply mark the TCP timer as expired so it gets processed + the next time prvCheckNetworkTimers() is called. */ + xTCPTimer.bExpired = pdTRUE_UNSIGNED; + } + #endif /* ipconfigUSE_TCP */ + break; + + case eTCPAcceptEvent: + /* The API FreeRTOS_accept() was called, the IP-task will now + check if the listening socket (communicated in pvData) actually + received a new connection. */ + #if( ipconfigUSE_TCP == 1 ) + { + pxSocket = ( FreeRTOS_Socket_t * ) ( xReceivedEvent.pvData ); + + if( xTCPCheckNewClient( pxSocket ) != pdFALSE ) + { + pxSocket->xEventBits |= eSOCKET_ACCEPT; + vSocketWakeUpUser( pxSocket ); + } + } + #endif /* ipconfigUSE_TCP */ + break; + + case eTCPNetStat: + /* FreeRTOS_netstat() was called to have the IP-task print an + overview of all sockets and their connections */ + #if( ( ipconfigUSE_TCP == 1 ) && ( ipconfigHAS_PRINTF == 1 ) ) + { + vTCPNetStat(); + } + #endif /* ipconfigUSE_TCP */ + break; + + default : + /* Should not get here. */ + break; + } + + if( xNetworkDownEventPending != pdFALSE ) + { + /* A network down event could not be posted to the network event + queue because the queue was full. Try posting again. */ + FreeRTOS_NetworkDown(); + } + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xIsCallingFromIPTask( void ) +{ +BaseType_t xReturn; + + if( xTaskGetCurrentTaskHandle() == xIPTaskHandle ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static void prvHandleEthernetPacket( NetworkBufferDescriptor_t *pxBuffer ) +{ + #if( ipconfigUSE_LINKED_RX_MESSAGES == 0 ) + { + /* When ipconfigUSE_LINKED_RX_MESSAGES is not set to 0 then only one + buffer will be sent at a time. This is the default way for +TCP to pass + messages from the MAC to the TCP/IP stack. */ + prvProcessEthernetPacket( pxBuffer ); + } + #else /* ipconfigUSE_LINKED_RX_MESSAGES */ + { + NetworkBufferDescriptor_t *pxNextBuffer; + + /* An optimisation that is useful when there is high network traffic. + Instead of passing received packets into the IP task one at a time the + network interface can chain received packets together and pass them into + the IP task in one go. The packets are chained using the pxNextBuffer + member. The loop below walks through the chain processing each packet + in the chain in turn. */ + do + { + /* Store a pointer to the buffer after pxBuffer for use later on. */ + pxNextBuffer = pxBuffer->pxNextBuffer; + + /* Make it NULL to avoid using it later on. */ + pxBuffer->pxNextBuffer = NULL; + + prvProcessEthernetPacket( pxBuffer ); + pxBuffer = pxNextBuffer; + + /* While there is another packet in the chain. */ + } while( pxBuffer != NULL ); + } + #endif /* ipconfigUSE_LINKED_RX_MESSAGES */ +} +/*-----------------------------------------------------------*/ + +static TickType_t prvCalculateSleepTime( void ) +{ +TickType_t xMaximumSleepTime; + + /* Start with the maximum sleep time, then check this against the remaining + time in any other timers that are active. */ + xMaximumSleepTime = ipconfigMAX_IP_TASK_SLEEP_TIME; + + if( xARPTimer.bActive != pdFALSE_UNSIGNED ) + { + if( xARPTimer.ulRemainingTime < xMaximumSleepTime ) + { + xMaximumSleepTime = xARPTimer.ulReloadTime; + } + } + + #if( ipconfigUSE_DHCP == 1 ) + { + if( xDHCPTimer.bActive != pdFALSE_UNSIGNED ) + { + if( xDHCPTimer.ulRemainingTime < xMaximumSleepTime ) + { + xMaximumSleepTime = xDHCPTimer.ulRemainingTime; + } + } + } + #endif /* ipconfigUSE_DHCP */ + + #if( ipconfigUSE_TCP == 1 ) + { + if( xTCPTimer.ulRemainingTime < xMaximumSleepTime ) + { + xMaximumSleepTime = xTCPTimer.ulRemainingTime; + } + } + #endif + + #if( ipconfigDNS_USE_CALLBACKS != 0 ) + { + if( xDNSTimer.bActive != pdFALSE ) + { + if( xDNSTimer.ulRemainingTime < xMaximumSleepTime ) + { + xMaximumSleepTime = xDNSTimer.ulRemainingTime; + } + } + } + #endif + + return xMaximumSleepTime; +} +/*-----------------------------------------------------------*/ + +static void prvCheckNetworkTimers( void ) +{ + /* Is it time for ARP processing? */ + if( prvIPTimerCheck( &xARPTimer ) != pdFALSE ) + { + xSendEventToIPTask( eARPTimerEvent ); + } + + #if( ipconfigUSE_DHCP == 1 ) + { + /* Is it time for DHCP processing? */ + if( prvIPTimerCheck( &xDHCPTimer ) != pdFALSE ) + { + xSendEventToIPTask( eDHCPEvent ); + } + } + #endif /* ipconfigUSE_DHCP */ + + #if( ipconfigDNS_USE_CALLBACKS != 0 ) + { + extern void vDNSCheckCallBack( void *pvSearchID ); + + /* Is it time for DNS processing? */ + if( prvIPTimerCheck( &xDNSTimer ) != pdFALSE ) + { + vDNSCheckCallBack( NULL ); + } + } + #endif /* ipconfigDNS_USE_CALLBACKS */ + + #if( ipconfigUSE_TCP == 1 ) + { + BaseType_t xWillSleep; + TickType_t xNextTime; + BaseType_t xCheckTCPSockets; + + if( uxQueueMessagesWaiting( xNetworkEventQueue ) == 0u ) + { + xWillSleep = pdTRUE; + } + else + { + xWillSleep = pdFALSE; + } + + /* Sockets need to be checked if the TCP timer has expired. */ + xCheckTCPSockets = prvIPTimerCheck( &xTCPTimer ); + + /* Sockets will also be checked if there are TCP messages but the + message queue is empty (indicated by xWillSleep being true). */ + if( ( xProcessedTCPMessage != pdFALSE ) && ( xWillSleep != pdFALSE ) ) + { + xCheckTCPSockets = pdTRUE; + } + + if( xCheckTCPSockets != pdFALSE ) + { + /* Attend to the sockets, returning the period after which the + check must be repeated. */ + xNextTime = xTCPTimerCheck( xWillSleep ); + prvIPTimerStart( &xTCPTimer, xNextTime ); + xProcessedTCPMessage = 0; + } + } + #endif /* ipconfigUSE_TCP == 1 */ +} +/*-----------------------------------------------------------*/ + +static void prvIPTimerStart( IPTimer_t *pxTimer, TickType_t xTime ) +{ + vTaskSetTimeOutState( &pxTimer->xTimeOut ); + pxTimer->ulRemainingTime = xTime; + + if( xTime == ( TickType_t ) 0 ) + { + pxTimer->bExpired = pdTRUE_UNSIGNED; + } + else + { + pxTimer->bExpired = pdFALSE_UNSIGNED; + } + + pxTimer->bActive = pdTRUE_UNSIGNED; +} +/*-----------------------------------------------------------*/ + +static void prvIPTimerReload( IPTimer_t *pxTimer, TickType_t xTime ) +{ + pxTimer->ulReloadTime = xTime; + prvIPTimerStart( pxTimer, xTime ); +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvIPTimerCheck( IPTimer_t *pxTimer ) +{ +BaseType_t xReturn; + + if( pxTimer->bActive == pdFALSE_UNSIGNED ) + { + /* The timer is not enabled. */ + xReturn = pdFALSE; + } + else + { + /* The timer might have set the bExpired flag already, if not, check the + value of xTimeOut against ulRemainingTime. */ + if( ( pxTimer->bExpired != pdFALSE_UNSIGNED ) || + ( xTaskCheckForTimeOut( &( pxTimer->xTimeOut ), &( pxTimer->ulRemainingTime ) ) != pdFALSE ) ) + { + prvIPTimerStart( pxTimer, pxTimer->ulReloadTime ); + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_NetworkDown( void ) +{ +static const IPStackEvent_t xNetworkDownEvent = { eNetworkDownEvent, NULL }; +const TickType_t xDontBlock = ( TickType_t ) 0; + + /* Simply send the network task the appropriate event. */ + if( xSendEventStructToIPTask( &xNetworkDownEvent, xDontBlock ) != pdPASS ) + { + /* Could not send the message, so it is still pending. */ + xNetworkDownEventPending = pdTRUE; + } + else + { + /* Message was sent so it is not pending. */ + xNetworkDownEventPending = pdFALSE; + } + + iptraceNETWORK_DOWN(); +} +/*-----------------------------------------------------------*/ + +BaseType_t FreeRTOS_NetworkDownFromISR( void ) +{ +static const IPStackEvent_t xNetworkDownEvent = { eNetworkDownEvent, NULL }; +BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + /* Simply send the network task the appropriate event. */ + if( xQueueSendToBackFromISR( xNetworkEventQueue, &xNetworkDownEvent, &xHigherPriorityTaskWoken ) != pdPASS ) + { + xNetworkDownEventPending = pdTRUE; + } + else + { + xNetworkDownEventPending = pdFALSE; + } + + iptraceNETWORK_DOWN(); + + return xHigherPriorityTaskWoken; +} +/*-----------------------------------------------------------*/ + +void *FreeRTOS_GetUDPPayloadBuffer( size_t xRequestedSizeBytes, TickType_t xBlockTimeTicks ) +{ +NetworkBufferDescriptor_t *pxNetworkBuffer; +void *pvReturn; + + /* Cap the block time. The reason for this is explained where + ipconfigUDP_MAX_SEND_BLOCK_TIME_TICKS is defined (assuming an official + FreeRTOSIPConfig.h header file is being used). */ + if( xBlockTimeTicks > ipconfigUDP_MAX_SEND_BLOCK_TIME_TICKS ) + { + xBlockTimeTicks = ipconfigUDP_MAX_SEND_BLOCK_TIME_TICKS; + } + + /* Obtain a network buffer with the required amount of storage. */ + pxNetworkBuffer = pxGetNetworkBufferWithDescriptor( sizeof( UDPPacket_t ) + xRequestedSizeBytes, xBlockTimeTicks ); + + if( pxNetworkBuffer != NULL ) + { + /* Set the actual packet size in case a bigger buffer was returned. */ + pxNetworkBuffer->xDataLength = sizeof( UDPPacket_t ) + xRequestedSizeBytes; + + /* Leave space for the UPD header. */ + pvReturn = ( void * ) &( pxNetworkBuffer->pucEthernetBuffer[ ipUDP_PAYLOAD_OFFSET_IPv4 ] ); + } + else + { + pvReturn = NULL; + } + + return ( void * ) pvReturn; +} +/*-----------------------------------------------------------*/ + +NetworkBufferDescriptor_t *pxDuplicateNetworkBufferWithDescriptor( NetworkBufferDescriptor_t * const pxNetworkBuffer, + BaseType_t xNewLength ) +{ +NetworkBufferDescriptor_t * pxNewBuffer; + + /* This function is only used when 'ipconfigZERO_COPY_TX_DRIVER' is set to 1. + The transmit routine wants to have ownership of the network buffer + descriptor, because it will pass the buffer straight to DMA. */ + pxNewBuffer = pxGetNetworkBufferWithDescriptor( ( size_t ) xNewLength, ( TickType_t ) 0 ); + + if( pxNewBuffer != NULL ) + { + /* Set the actual packet size in case a bigger buffer than requested + was returned. */ + pxNewBuffer->xDataLength = xNewLength; + + /* Copy the original packet information. */ + pxNewBuffer->ulIPAddress = pxNetworkBuffer->ulIPAddress; + pxNewBuffer->usPort = pxNetworkBuffer->usPort; + pxNewBuffer->usBoundPort = pxNetworkBuffer->usBoundPort; + memcpy( pxNewBuffer->pucEthernetBuffer, pxNetworkBuffer->pucEthernetBuffer, pxNetworkBuffer->xDataLength ); + } + + return pxNewBuffer; +} +/*-----------------------------------------------------------*/ + +#if( ipconfigZERO_COPY_TX_DRIVER != 0 ) || ( ipconfigZERO_COPY_RX_DRIVER != 0 ) + + NetworkBufferDescriptor_t *pxPacketBuffer_to_NetworkBuffer( const void *pvBuffer ) + { + uint8_t *pucBuffer; + NetworkBufferDescriptor_t *pxResult; + + if( pvBuffer == NULL ) + { + pxResult = NULL; + } + else + { + /* Obtain the network buffer from the zero copy pointer. */ + pucBuffer = ( uint8_t * ) pvBuffer; + + /* The input here is a pointer to a payload buffer. Subtract the + size of the header in the network buffer, usually 8 + 2 bytes. */ + pucBuffer -= ipBUFFER_PADDING; + + /* Here a pointer was placed to the network descriptor. As a + pointer is dereferenced, make sure it is well aligned. */ + if( ( ( ( uint32_t ) pucBuffer ) & ( sizeof( pucBuffer ) - ( size_t ) 1 ) ) == ( uint32_t ) 0 ) + { + pxResult = * ( ( NetworkBufferDescriptor_t ** ) pucBuffer ); + } + else + { + pxResult = NULL; + } + } + + return pxResult; + } + +#endif /* ipconfigZERO_COPY_TX_DRIVER != 0 */ +/*-----------------------------------------------------------*/ + +NetworkBufferDescriptor_t *pxUDPPayloadBuffer_to_NetworkBuffer( void *pvBuffer ) +{ +uint8_t *pucBuffer; +NetworkBufferDescriptor_t *pxResult; + + if( pvBuffer == NULL ) + { + pxResult = NULL; + } + else + { + /* Obtain the network buffer from the zero copy pointer. */ + pucBuffer = ( uint8_t * ) pvBuffer; + + /* The input here is a pointer to a payload buffer. Subtract + the total size of a UDP/IP header plus the size of the header in + the network buffer, usually 8 + 2 bytes. */ + pucBuffer -= ( sizeof( UDPPacket_t ) + ipBUFFER_PADDING ); + + /* Here a pointer was placed to the network descriptor, + As a pointer is dereferenced, make sure it is well aligned */ + if( ( ( ( uint32_t ) pucBuffer ) & ( sizeof( pucBuffer ) - 1 ) ) == 0 ) + { + /* The following statement may trigger a: + warning: cast increases required alignment of target type [-Wcast-align]. + It has been confirmed though that the alignment is suitable. */ + pxResult = * ( ( NetworkBufferDescriptor_t ** ) pucBuffer ); + } + else + { + pxResult = NULL; + } + } + + return pxResult; +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_ReleaseUDPPayloadBuffer( void *pvBuffer ) +{ + vReleaseNetworkBufferAndDescriptor( pxUDPPayloadBuffer_to_NetworkBuffer( pvBuffer ) ); +} +/*-----------------------------------------------------------*/ + +/*_RB_ Should we add an error or assert if the task priorities are set such that the servers won't function as expected? */ +/*_HT_ There was a bug in FreeRTOS_TCP_IP.c that only occurred when the applications' priority was too high. + As that bug has been repaired, there is not an urgent reason to warn. + It is better though to use the advised priority scheme. */ +BaseType_t FreeRTOS_IPInit( const uint8_t ucIPAddress[ ipIP_ADDRESS_LENGTH_BYTES ], const uint8_t ucNetMask[ ipIP_ADDRESS_LENGTH_BYTES ], const uint8_t ucGatewayAddress[ ipIP_ADDRESS_LENGTH_BYTES ], const uint8_t ucDNSServerAddress[ ipIP_ADDRESS_LENGTH_BYTES ], const uint8_t ucMACAddress[ ipMAC_ADDRESS_LENGTH_BYTES ] ) +{ +BaseType_t xReturn = pdFALSE; + + /* This function should only be called once. */ + configASSERT( xIPIsNetworkTaskReady() == pdFALSE ); + configASSERT( xNetworkEventQueue == NULL ); + configASSERT( xIPTaskHandle == NULL ); + + /* Check structure packing is correct. */ + configASSERT( sizeof( EthernetHeader_t ) == ipEXPECTED_EthernetHeader_t_SIZE ); + configASSERT( sizeof( ARPHeader_t ) == ipEXPECTED_ARPHeader_t_SIZE ); + configASSERT( sizeof( IPHeader_t ) == ipEXPECTED_IPHeader_t_SIZE ); + configASSERT( sizeof( ICMPHeader_t ) == ipEXPECTED_ICMPHeader_t_SIZE ); + configASSERT( sizeof( UDPHeader_t ) == ipEXPECTED_UDPHeader_t_SIZE ); + + /* Attempt to create the queue used to communicate with the IP task. */ + xNetworkEventQueue = xQueueCreate( ( UBaseType_t ) ipconfigEVENT_QUEUE_LENGTH, ( UBaseType_t ) sizeof( IPStackEvent_t ) ); + configASSERT( xNetworkEventQueue ); + + if( xNetworkEventQueue != NULL ) + { + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + { + /* A queue registry is normally used to assist a kernel aware + debugger. If one is in use then it will be helpful for the debugger + to show information about the network event queue. */ + vQueueAddToRegistry( xNetworkEventQueue, "NetEvnt" ); + } + #endif /* configQUEUE_REGISTRY_SIZE */ + + if( xNetworkBuffersInitialise() == pdPASS ) + { + /* Store the local IP and MAC address. */ + xNetworkAddressing.ulDefaultIPAddress = FreeRTOS_inet_addr_quick( ucIPAddress[ 0 ], ucIPAddress[ 1 ], ucIPAddress[ 2 ], ucIPAddress[ 3 ] ); + xNetworkAddressing.ulNetMask = FreeRTOS_inet_addr_quick( ucNetMask[ 0 ], ucNetMask[ 1 ], ucNetMask[ 2 ], ucNetMask[ 3 ] ); + xNetworkAddressing.ulGatewayAddress = FreeRTOS_inet_addr_quick( ucGatewayAddress[ 0 ], ucGatewayAddress[ 1 ], ucGatewayAddress[ 2 ], ucGatewayAddress[ 3 ] ); + xNetworkAddressing.ulDNSServerAddress = FreeRTOS_inet_addr_quick( ucDNSServerAddress[ 0 ], ucDNSServerAddress[ 1 ], ucDNSServerAddress[ 2 ], ucDNSServerAddress[ 3 ] ); + xNetworkAddressing.ulBroadcastAddress = ( xNetworkAddressing.ulDefaultIPAddress & xNetworkAddressing.ulNetMask ) | ~xNetworkAddressing.ulNetMask; + + memcpy( &xDefaultAddressing, &xNetworkAddressing, sizeof( xDefaultAddressing ) ); + + #if ipconfigUSE_DHCP == 1 + { + /* The IP address is not set until DHCP completes. */ + *ipLOCAL_IP_ADDRESS_POINTER = 0x00UL; + } + #else + { + /* The IP address is set from the value passed in. */ + *ipLOCAL_IP_ADDRESS_POINTER = xNetworkAddressing.ulDefaultIPAddress; + + /* Added to prevent ARP flood to gateway. Ensure the + gateway is on the same subnet as the IP address. */ + configASSERT( ( ( *ipLOCAL_IP_ADDRESS_POINTER ) & xNetworkAddressing.ulNetMask ) == ( xNetworkAddressing.ulGatewayAddress & xNetworkAddressing.ulNetMask ) ); + } + #endif /* ipconfigUSE_DHCP == 1 */ + + /* The MAC address is stored in the start of the default packet + header fragment, which is used when sending UDP packets. */ + memcpy( ( void * ) ipLOCAL_MAC_ADDRESS, ( void * ) ucMACAddress, ( size_t ) ipMAC_ADDRESS_LENGTH_BYTES ); + + /* Prepare the sockets interface. */ + xReturn = vNetworkSocketsInit(); + + if( pdTRUE == xReturn ) + { + /* Create the task that processes Ethernet and stack events. */ + xReturn = xTaskCreate( prvIPTask, "IP-task", ( uint16_t )ipconfigIP_TASK_STACK_SIZE_WORDS, NULL, ( UBaseType_t )ipconfigIP_TASK_PRIORITY, &xIPTaskHandle ); + } + } + else + { + FreeRTOS_debug_printf( ( "FreeRTOS_IPInit: xNetworkBuffersInitialise() failed\n") ); + + /* Clean up. */ + vQueueDelete( xNetworkEventQueue ); + xNetworkEventQueue = NULL; + } + } + else + { + FreeRTOS_debug_printf( ( "FreeRTOS_IPInit: Network event queue could not be created\n") ); + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_GetAddressConfiguration( uint32_t *pulIPAddress, uint32_t *pulNetMask, uint32_t *pulGatewayAddress, uint32_t *pulDNSServerAddress ) +{ + /* Return the address configuration to the caller. */ + + if( pulIPAddress != NULL ) + { + *pulIPAddress = *ipLOCAL_IP_ADDRESS_POINTER; + } + + if( pulNetMask != NULL ) + { + *pulNetMask = xNetworkAddressing.ulNetMask; + } + + if( pulGatewayAddress != NULL ) + { + *pulGatewayAddress = xNetworkAddressing.ulGatewayAddress; + } + + if( pulDNSServerAddress != NULL ) + { + *pulDNSServerAddress = xNetworkAddressing.ulDNSServerAddress; + } +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_SetAddressConfiguration( const uint32_t *pulIPAddress, const uint32_t *pulNetMask, const uint32_t *pulGatewayAddress, const uint32_t *pulDNSServerAddress ) +{ + /* Update the address configuration. */ + + if( pulIPAddress != NULL ) + { + *ipLOCAL_IP_ADDRESS_POINTER = *pulIPAddress; + } + + if( pulNetMask != NULL ) + { + xNetworkAddressing.ulNetMask = *pulNetMask; + } + + if( pulGatewayAddress != NULL ) + { + xNetworkAddressing.ulGatewayAddress = *pulGatewayAddress; + } + + if( pulDNSServerAddress != NULL ) + { + xNetworkAddressing.ulDNSServerAddress = *pulDNSServerAddress; + } +} +/*-----------------------------------------------------------*/ + +#if ( ipconfigSUPPORT_OUTGOING_PINGS == 1 ) + + BaseType_t FreeRTOS_SendPingRequest( uint32_t ulIPAddress, size_t xNumberOfBytesToSend, TickType_t xBlockTimeTicks ) + { + NetworkBufferDescriptor_t *pxNetworkBuffer; + ICMPHeader_t *pxICMPHeader; + BaseType_t xReturn = pdFAIL; + static uint16_t usSequenceNumber = 0; + uint8_t *pucChar; + IPStackEvent_t xStackTxEvent = { eStackTxEvent, NULL }; + + if( (xNumberOfBytesToSend >= 1 ) && ( xNumberOfBytesToSend < ( ( ipconfigNETWORK_MTU - sizeof( IPHeader_t ) ) - sizeof( ICMPHeader_t ) ) ) && ( uxGetNumberOfFreeNetworkBuffers() >= 3 ) ) + { + pxNetworkBuffer = pxGetNetworkBufferWithDescriptor( xNumberOfBytesToSend + sizeof( ICMPPacket_t ), xBlockTimeTicks ); + + if( pxNetworkBuffer != NULL ) + { + pxICMPHeader = ( ICMPHeader_t * ) &( pxNetworkBuffer->pucEthernetBuffer[ ipIP_PAYLOAD_OFFSET ] ); + usSequenceNumber++; + + /* Fill in the basic header information. */ + pxICMPHeader->ucTypeOfMessage = ipICMP_ECHO_REQUEST; + pxICMPHeader->ucTypeOfService = 0; + pxICMPHeader->usIdentifier = usSequenceNumber; + pxICMPHeader->usSequenceNumber = usSequenceNumber; + + /* Find the start of the data. */ + pucChar = ( uint8_t * ) pxICMPHeader; + pucChar += sizeof( ICMPHeader_t ); + + /* Just memset the data to a fixed value. */ + memset( ( void * ) pucChar, ( int ) ipECHO_DATA_FILL_BYTE, xNumberOfBytesToSend ); + + /* The message is complete, IP and checksum's are handled by + vProcessGeneratedUDPPacket */ + pxNetworkBuffer->pucEthernetBuffer[ ipSOCKET_OPTIONS_OFFSET ] = FREERTOS_SO_UDPCKSUM_OUT; + pxNetworkBuffer->ulIPAddress = ulIPAddress; + pxNetworkBuffer->usPort = ipPACKET_CONTAINS_ICMP_DATA; + pxNetworkBuffer->xDataLength = xNumberOfBytesToSend + sizeof( ICMPHeader_t ); + + /* Send to the stack. */ + xStackTxEvent.pvData = pxNetworkBuffer; + + if( xSendEventStructToIPTask( &xStackTxEvent, xBlockTimeTicks) != pdPASS ) + { + vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ); + iptraceSTACK_TX_EVENT_LOST( ipSTACK_TX_EVENT ); + } + else + { + xReturn = usSequenceNumber; + } + } + } + else + { + /* The requested number of bytes will not fit in the available space + in the network buffer. */ + } + + return xReturn; + } + +#endif /* ipconfigSUPPORT_OUTGOING_PINGS == 1 */ +/*-----------------------------------------------------------*/ + +BaseType_t xSendEventToIPTask( eIPEvent_t eEvent ) +{ +IPStackEvent_t xEventMessage; +const TickType_t xDontBlock = ( TickType_t ) 0; + + xEventMessage.eEventType = eEvent; + xEventMessage.pvData = ( void* )NULL; + + return xSendEventStructToIPTask( &xEventMessage, xDontBlock ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xSendEventStructToIPTask( const IPStackEvent_t *pxEvent, TickType_t xTimeout ) +{ +BaseType_t xReturn, xSendMessage; + + if( ( xIPIsNetworkTaskReady() == pdFALSE ) && ( pxEvent->eEventType != eNetworkDownEvent ) ) + { + /* Only allow eNetworkDownEvent events if the IP task is not ready + yet. Not going to attempt to send the message so the send failed. */ + xReturn = pdFAIL; + } + else + { + xSendMessage = pdTRUE; + + #if( ipconfigUSE_TCP == 1 ) + { + if( pxEvent->eEventType == eTCPTimerEvent ) + { + /* TCP timer events are sent to wake the timer task when + xTCPTimer has expired, but there is no point sending them if the + IP task is already awake processing other message. */ + xTCPTimer.bExpired = pdTRUE_UNSIGNED; + + if( uxQueueMessagesWaiting( xNetworkEventQueue ) != 0u ) + { + /* Not actually going to send the message but this is not a + failure as the message didn't need to be sent. */ + xSendMessage = pdFALSE; + } + } + } + #endif /* ipconfigUSE_TCP */ + + if( xSendMessage != pdFALSE ) + { + /* The IP task cannot block itself while waiting for itself to + respond. */ + if( ( xIsCallingFromIPTask() == pdTRUE ) && ( xTimeout > ( TickType_t ) 0 ) ) + { + xTimeout = ( TickType_t ) 0; + } + + xReturn = xQueueSendToBack( xNetworkEventQueue, pxEvent, xTimeout ); + + if( xReturn == pdFAIL ) + { + /* A message should have been sent to the IP task, but wasn't. */ + FreeRTOS_debug_printf( ( "xSendEventStructToIPTask: CAN NOT ADD %d\n", pxEvent->eEventType ) ); + iptraceSTACK_TX_EVENT_LOST( pxEvent->eEventType ); + } + } + else + { + /* It was not necessary to send the message to process the event so + even though the message was not sent the call was successful. */ + xReturn = pdPASS; + } + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +eFrameProcessingResult_t eConsiderFrameForProcessing( const uint8_t * const pucEthernetBuffer ) +{ +eFrameProcessingResult_t eReturn; +const EthernetHeader_t *pxEthernetHeader; + + pxEthernetHeader = ( const EthernetHeader_t * ) pucEthernetBuffer; + + if( memcmp( ( void * ) ipLOCAL_MAC_ADDRESS, ( void * ) &( pxEthernetHeader->xDestinationAddress ), sizeof( MACAddress_t ) ) == 0 ) + { + /* The packet was directed to this node directly - process it. */ + eReturn = eProcessBuffer; + } + else if( memcmp( ( void * ) xBroadcastMACAddress.ucBytes, ( void * ) pxEthernetHeader->xDestinationAddress.ucBytes, sizeof( MACAddress_t ) ) == 0 ) + { + /* The packet was a broadcast - process it. */ + eReturn = eProcessBuffer; + } + else +#if( ipconfigUSE_LLMNR == 1 ) + if( memcmp( ( void * ) xLLMNR_MacAdress.ucBytes, ( void * ) pxEthernetHeader->xDestinationAddress.ucBytes, sizeof( MACAddress_t ) ) == 0 ) + { + /* The packet is a request for LLMNR - process it. */ + eReturn = eProcessBuffer; + } + else +#endif /* ipconfigUSE_LLMNR */ + { + /* The packet was not a broadcast, or for this node, just release + the buffer without taking any other action. */ + eReturn = eReleaseBuffer; + } + + #if( ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES == 1 ) + { + uint16_t usFrameType; + + if( eReturn == eProcessBuffer ) + { + usFrameType = pxEthernetHeader->usFrameType; + usFrameType = FreeRTOS_ntohs( usFrameType ); + + if( usFrameType <= 0x600U ) + { + /* Not an Ethernet II frame. */ + eReturn = eReleaseBuffer; + } + } + } + #endif /* ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES == 1 */ + + return eReturn; +} +/*-----------------------------------------------------------*/ + +static void prvProcessNetworkDownEvent( void ) +{ + /* Stop the ARP timer while there is no network. */ + xARPTimer.bActive = pdFALSE_UNSIGNED; + + #if ipconfigUSE_NETWORK_EVENT_HOOK == 1 + { + static BaseType_t xCallEventHook = pdFALSE; + + /* The first network down event is generated by the IP stack itself to + initialise the network hardware, so do not call the network down event + the first time through. */ + if( xCallEventHook == pdTRUE ) + { + vApplicationIPNetworkEventHook( eNetworkDown ); + } + xCallEventHook = pdTRUE; + } + #endif + + /* Per the ARP Cache Validation section of https://tools.ietf.org/html/rfc1122, + treat network down as a "delivery problem" and flush the ARP cache for this + interface. */ + FreeRTOS_ClearARP( ); + + /* The network has been disconnected (or is being initialised for the first + time). Perform whatever hardware processing is necessary to bring it up + again, or wait for it to be available again. This is hardware dependent. */ + if( xNetworkInterfaceInitialise() != pdPASS ) + { + /* Ideally the network interface initialisation function will only + return when the network is available. In case this is not the case, + wait a while before retrying the initialisation. */ + vTaskDelay( ipINITIALISATION_RETRY_DELAY ); + FreeRTOS_NetworkDown(); + } + else + { + /* Set remaining time to 0 so it will become active immediately. */ + #if ipconfigUSE_DHCP == 1 + { + /* The network is not up until DHCP has completed. */ + vDHCPProcess( pdTRUE ); + xSendEventToIPTask( eDHCPEvent ); + } + #else + { + /* Perform any necessary 'network up' processing. */ + vIPNetworkUpCalls(); + } + #endif + } +} +/*-----------------------------------------------------------*/ + +void vIPNetworkUpCalls( void ) +{ + xNetworkUp = pdTRUE; + + #if( ipconfigUSE_NETWORK_EVENT_HOOK == 1 ) + { + vApplicationIPNetworkEventHook( eNetworkUp ); + } + #endif /* ipconfigUSE_NETWORK_EVENT_HOOK */ + + #if( ipconfigDNS_USE_CALLBACKS != 0 ) + { + /* The following function is declared in FreeRTOS_DNS.c and 'private' to + this library */ + extern void vDNSInitialise( void ); + vDNSInitialise(); + } + #endif /* ipconfigDNS_USE_CALLBACKS != 0 */ + + /* Set remaining time to 0 so it will become active immediately. */ + prvIPTimerReload( &xARPTimer, pdMS_TO_TICKS( ipARP_TIMER_PERIOD_MS ) ); +} +/*-----------------------------------------------------------*/ + +static void prvProcessEthernetPacket( NetworkBufferDescriptor_t * const pxNetworkBuffer ) +{ +EthernetHeader_t *pxEthernetHeader; +eFrameProcessingResult_t eReturned = eReleaseBuffer; + + configASSERT( pxNetworkBuffer ); + + /* Interpret the Ethernet frame. */ + if( pxNetworkBuffer->xDataLength >= sizeof( EthernetHeader_t ) ) + { + eReturned = ipCONSIDER_FRAME_FOR_PROCESSING( pxNetworkBuffer->pucEthernetBuffer ); + pxEthernetHeader = ( EthernetHeader_t * )( pxNetworkBuffer->pucEthernetBuffer ); + + if( eReturned == eProcessBuffer ) + { + /* Interpret the received Ethernet packet. */ + switch( pxEthernetHeader->usFrameType ) + { + case ipARP_FRAME_TYPE: + /* The Ethernet frame contains an ARP packet. */ + if( pxNetworkBuffer->xDataLength >= sizeof( ARPPacket_t ) ) + { + eReturned = eARPProcessPacket( ( ARPPacket_t * )pxNetworkBuffer->pucEthernetBuffer ); + } + else + { + eReturned = eReleaseBuffer; + } + break; + + case ipIPv4_FRAME_TYPE: + /* The Ethernet frame contains an IP packet. */ + if( pxNetworkBuffer->xDataLength >= sizeof( IPPacket_t ) ) + { + eReturned = prvProcessIPPacket( ( IPPacket_t * )pxNetworkBuffer->pucEthernetBuffer, pxNetworkBuffer ); + } + else + { + eReturned = eReleaseBuffer; + } + break; + + default: + /* No other packet types are handled. Nothing to do. */ + eReturned = eReleaseBuffer; + break; + } + } + } + + /* Perform any actions that resulted from processing the Ethernet frame. */ + switch( eReturned ) + { + case eReturnEthernetFrame : + /* The Ethernet frame will have been updated (maybe it was + an ARP request or a PING request?) and should be sent back to + its source. */ + vReturnEthernetFrame( pxNetworkBuffer, pdTRUE ); + /* parameter pdTRUE: the buffer must be released once + the frame has been transmitted */ + break; + + case eFrameConsumed : + /* The frame is in use somewhere, don't release the buffer + yet. */ + break; + + default : + /* The frame is not being used anywhere, and the + NetworkBufferDescriptor_t structure containing the frame should + just be released back to the list of free buffers. */ + vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ); + break; + } +} +/*-----------------------------------------------------------*/ + +static eFrameProcessingResult_t prvAllowIPPacket( const IPPacket_t * const pxIPPacket, + NetworkBufferDescriptor_t * const pxNetworkBuffer, UBaseType_t uxHeaderLength ) +{ +eFrameProcessingResult_t eReturn = eProcessBuffer; + +#if( ( ipconfigETHERNET_DRIVER_FILTERS_PACKETS == 0 ) || ( ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM == 0 ) ) + const IPHeader_t * pxIPHeader = &( pxIPPacket->xIPHeader ); +#else + /* or else, the parameter won't be used and the function will be optimised + away */ + ( void ) pxIPPacket; +#endif + + #if( ipconfigETHERNET_DRIVER_FILTERS_PACKETS == 0 ) + { + /* In systems with a very small amount of RAM, it might be advantageous + to have incoming messages checked earlier, by the network card driver. + This method may decrease the usage of sparse network buffers. */ + uint32_t ulDestinationIPAddress = pxIPHeader->ulDestinationIPAddress; + + /* Ensure that the incoming packet is not fragmented (only outgoing + packets can be fragmented) as these are the only handled IP frames + currently. */ + if( ( pxIPHeader->usFragmentOffset & ipFRAGMENT_OFFSET_BIT_MASK ) != 0U ) + { + /* Can not handle, fragmented packet. */ + eReturn = eReleaseBuffer; + } + /* 0x45 means: IPv4 with an IP header of 5 x 4 = 20 bytes + * 0x47 means: IPv4 with an IP header of 7 x 4 = 28 bytes */ + else if( ( pxIPHeader->ucVersionHeaderLength < 0x45u ) || ( pxIPHeader->ucVersionHeaderLength > 0x4Fu ) ) + { + /* Can not handle, unknown or invalid header version. */ + eReturn = eReleaseBuffer; + } + /* Is the packet for this IP address? */ + else if( ( ulDestinationIPAddress != *ipLOCAL_IP_ADDRESS_POINTER ) && + /* Is it the global broadcast address 255.255.255.255 ? */ + ( ulDestinationIPAddress != ipBROADCAST_IP_ADDRESS ) && + /* Is it a specific broadcast address 192.168.1.255 ? */ + ( ulDestinationIPAddress != xNetworkAddressing.ulBroadcastAddress ) && + #if( ipconfigUSE_LLMNR == 1 ) + /* Is it the LLMNR multicast address? */ + ( ulDestinationIPAddress != ipLLMNR_IP_ADDR ) && + #endif + /* Or (during DHCP negotiation) we have no IP-address yet? */ + ( *ipLOCAL_IP_ADDRESS_POINTER != 0UL ) ) + { + /* Packet is not for this node, release it */ + eReturn = eReleaseBuffer; + } + } + #endif /* ipconfigETHERNET_DRIVER_FILTERS_PACKETS */ + + #if( ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM == 0 ) + { + /* Some drivers of NIC's with checksum-offloading will enable the above + define, so that the checksum won't be checked again here */ + if (eReturn == eProcessBuffer ) + { + /* Is the IP header checksum correct? */ + if( ( pxIPHeader->ucProtocol != ( uint8_t ) ipPROTOCOL_ICMP ) && + ( usGenerateChecksum( 0UL, ( uint8_t * ) &( pxIPHeader->ucVersionHeaderLength ), ( size_t ) uxHeaderLength ) != ipCORRECT_CRC ) ) + { + /* Check sum in IP-header not correct. */ + eReturn = eReleaseBuffer; + } + /* Is the upper-layer checksum (TCP/UDP/ICMP) correct? */ + else if( usGenerateProtocolChecksum( ( uint8_t * )( pxNetworkBuffer->pucEthernetBuffer ), pxNetworkBuffer->xDataLength, pdFALSE ) != ipCORRECT_CRC ) + { + /* Protocol checksum not accepted. */ + eReturn = eReleaseBuffer; + } + } + } + #else + { + /* to avoid warning unused parameters */ + ( void ) pxNetworkBuffer; + ( void ) uxHeaderLength; + } + #endif /* ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM == 0 */ + + return eReturn; +} +/*-----------------------------------------------------------*/ + +static eFrameProcessingResult_t prvProcessIPPacket( IPPacket_t * const pxIPPacket, NetworkBufferDescriptor_t * const pxNetworkBuffer ) +{ +eFrameProcessingResult_t eReturn; +IPHeader_t * pxIPHeader = &( pxIPPacket->xIPHeader ); +UBaseType_t uxHeaderLength = ( UBaseType_t ) ( ( pxIPHeader->ucVersionHeaderLength & 0x0Fu ) << 2 ); +uint8_t ucProtocol; + + /* Bound the calculated header length: take away the Ethernet header size, + then check if the IP header is claiming to be longer than the remaining + total packet size. Also check for minimal header field length. */ + if( ( uxHeaderLength > ( pxNetworkBuffer->xDataLength - ipSIZE_OF_ETH_HEADER ) ) || + ( uxHeaderLength < ipSIZE_OF_IPv4_HEADER ) ) + { + return eReleaseBuffer; + } + + ucProtocol = pxIPPacket->xIPHeader.ucProtocol; + /* Check if the IP headers are acceptable and if it has our destination. */ + eReturn = prvAllowIPPacket( pxIPPacket, pxNetworkBuffer, uxHeaderLength ); + + if( eReturn == eProcessBuffer ) + { + if( uxHeaderLength > ipSIZE_OF_IPv4_HEADER ) + { + /* All structs of headers expect a IP header size of 20 bytes + * IP header options were included, we'll ignore them and cut them out + * Note: IP options are mostly use in Multi-cast protocols */ + const size_t optlen = ( ( size_t ) uxHeaderLength ) - ipSIZE_OF_IPv4_HEADER; + /* From: the previous start of UDP/ICMP/TCP data */ + uint8_t *pucSource = ( uint8_t* )(pxNetworkBuffer->pucEthernetBuffer + sizeof( EthernetHeader_t ) + uxHeaderLength); + /* To: the usual start of UDP/ICMP/TCP data at offset 20 from IP header */ + uint8_t *pucTarget = ( uint8_t* )(pxNetworkBuffer->pucEthernetBuffer + sizeof( EthernetHeader_t ) + ipSIZE_OF_IPv4_HEADER); + /* How many: total length minus the options and the lower headers */ + const size_t xMoveLen = pxNetworkBuffer->xDataLength - optlen - ipSIZE_OF_IPv4_HEADER - ipSIZE_OF_ETH_HEADER; + + memmove( pucTarget, pucSource, xMoveLen ); + pxNetworkBuffer->xDataLength -= optlen; + + /* Fix-up new version/header length field in IP packet. */ + pxIPHeader->ucVersionHeaderLength = ( pxIPHeader->ucVersionHeaderLength & 0xF0 ) | /* High nibble is the version. */ + ( ( ipSIZE_OF_IPv4_HEADER >> 2 ) & 0x0F ); /* Low nibble is the header size, in bytes, divided by four. */ + } + + /* Add the IP and MAC addresses to the ARP table if they are not + already there - otherwise refresh the age of the existing + entry. */ + if( ucProtocol != ( uint8_t ) ipPROTOCOL_UDP ) + { + /* Refresh the ARP cache with the IP/MAC-address of the received packet + * For UDP packets, this will be done later in xProcessReceivedUDPPacket() + * as soon as know that the message will be handled by someone + * This will prevent that the ARP cache will get overwritten + * with the IP-address of useless broadcast packets + */ + vARPRefreshCacheEntry( &( pxIPPacket->xEthernetHeader.xSourceAddress ), pxIPHeader->ulSourceIPAddress ); + } + switch( ucProtocol ) + { + case ipPROTOCOL_ICMP : + /* The IP packet contained an ICMP frame. Don't bother + checking the ICMP checksum, as if it is wrong then the + wrong data will also be returned, and the source of the + ping will know something went wrong because it will not + be able to validate what it receives. */ + #if ( ipconfigREPLY_TO_INCOMING_PINGS == 1 ) || ( ipconfigSUPPORT_OUTGOING_PINGS == 1 ) + { + if( pxNetworkBuffer->xDataLength >= sizeof( ICMPPacket_t ) ) + { + ICMPPacket_t *pxICMPPacket = ( ICMPPacket_t * )( pxNetworkBuffer->pucEthernetBuffer ); + if( pxIPHeader->ulDestinationIPAddress == *ipLOCAL_IP_ADDRESS_POINTER ) + { + eReturn = prvProcessICMPPacket( pxICMPPacket ); + } + } + else + { + eReturn = eReleaseBuffer; + } + } + #endif /* ( ipconfigREPLY_TO_INCOMING_PINGS == 1 ) || ( ipconfigSUPPORT_OUTGOING_PINGS == 1 ) */ + break; + + case ipPROTOCOL_UDP : + { + /* The IP packet contained a UDP frame. */ + UDPPacket_t *pxUDPPacket = ( UDPPacket_t * ) ( pxNetworkBuffer->pucEthernetBuffer ); + + /* Only proceed if the payload length indicated in the header + appears to be valid. */ + if ( pxNetworkBuffer->xDataLength >= sizeof( UDPPacket_t ) ) + { + /* Ensure that downstream UDP packet handling has the lesser + * of: the actual network buffer Ethernet frame length, or + * the sender's UDP packet header payload length, minus the + * size of the UDP header. + * + * The size of the UDP packet structure in this implementation + * includes the size of the Ethernet header, the size of + * the IP header, and the size of the UDP header. + */ + + pxNetworkBuffer->xDataLength -= sizeof( UDPPacket_t ); + if( ( FreeRTOS_ntohs( pxUDPPacket->xUDPHeader.usLength ) - sizeof( UDPHeader_t ) ) < + pxNetworkBuffer->xDataLength ) + { + pxNetworkBuffer->xDataLength = FreeRTOS_ntohs( pxUDPPacket->xUDPHeader.usLength ) - sizeof( UDPHeader_t ); + } + + /* Fields in pxNetworkBuffer (usPort, ulIPAddress) are network order. */ + pxNetworkBuffer->usPort = pxUDPPacket->xUDPHeader.usSourcePort; + pxNetworkBuffer->ulIPAddress = pxUDPPacket->xIPHeader.ulSourceIPAddress; + + /* ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM: + * In some cases, the upper-layer checksum has been calculated + * by the NIC driver. + * + * Pass the packet payload to the UDP sockets implementation. */ + if( xProcessReceivedUDPPacket( pxNetworkBuffer, + pxUDPPacket->xUDPHeader.usDestinationPort ) == pdPASS ) + { + eReturn = eFrameConsumed; + } + } + else + { + eReturn = eReleaseBuffer; + } + } + break; + +#if ipconfigUSE_TCP == 1 + case ipPROTOCOL_TCP : + { + + if( xProcessReceivedTCPPacket( pxNetworkBuffer ) == pdPASS ) + { + eReturn = eFrameConsumed; + } + + /* Setting this variable will cause xTCPTimerCheck() + to be called just before the IP-task blocks. */ + xProcessedTCPMessage++; + } + break; +#endif + default : + /* Not a supported frame type. */ + break; + } + } + + return eReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ipconfigSUPPORT_OUTGOING_PINGS == 1 ) + + static void prvProcessICMPEchoReply( ICMPPacket_t * const pxICMPPacket ) + { + ePingReplyStatus_t eStatus = eSuccess; + uint16_t usDataLength, usCount; + uint8_t *pucByte; + + /* Find the total length of the IP packet. */ + usDataLength = pxICMPPacket->xIPHeader.usLength; + usDataLength = FreeRTOS_ntohs( usDataLength ); + + /* Remove the length of the IP headers to obtain the length of the ICMP + message itself. */ + usDataLength = ( uint16_t ) ( ( ( uint32_t ) usDataLength ) - ipSIZE_OF_IPv4_HEADER ); + + /* Remove the length of the ICMP header, to obtain the length of + data contained in the ping. */ + usDataLength = ( uint16_t ) ( ( ( uint32_t ) usDataLength ) - ipSIZE_OF_ICMP_HEADER ); + + /* Checksum has already been checked before in prvProcessIPPacket */ + + /* Find the first byte of the data within the ICMP packet. */ + pucByte = ( uint8_t * ) pxICMPPacket; + pucByte += sizeof( ICMPPacket_t ); + + /* Check each byte. */ + for( usCount = 0; usCount < usDataLength; usCount++ ) + { + if( *pucByte != ipECHO_DATA_FILL_BYTE ) + { + eStatus = eInvalidData; + break; + } + + pucByte++; + } + + /* Call back into the application to pass it the result. */ + vApplicationPingReplyHook( eStatus, pxICMPPacket->xICMPHeader.usIdentifier ); + } + +#endif +/*-----------------------------------------------------------*/ + +#if ( ipconfigREPLY_TO_INCOMING_PINGS == 1 ) + + static eFrameProcessingResult_t prvProcessICMPEchoRequest( ICMPPacket_t * const pxICMPPacket ) + { + ICMPHeader_t *pxICMPHeader; + IPHeader_t *pxIPHeader; + uint16_t usRequest; + + pxICMPHeader = &( pxICMPPacket->xICMPHeader ); + pxIPHeader = &( pxICMPPacket->xIPHeader ); + + /* HT:endian: changed back */ + iptraceSENDING_PING_REPLY( pxIPHeader->ulSourceIPAddress ); + + /* The checksum can be checked here - but a ping reply should be + returned even if the checksum is incorrect so the other end can + tell that the ping was received - even if the ping reply contains + invalid data. */ + pxICMPHeader->ucTypeOfMessage = ( uint8_t ) ipICMP_ECHO_REPLY; + pxIPHeader->ulDestinationIPAddress = pxIPHeader->ulSourceIPAddress; + pxIPHeader->ulSourceIPAddress = *ipLOCAL_IP_ADDRESS_POINTER; + + /* Update the checksum because the ucTypeOfMessage member in the header + has been changed to ipICMP_ECHO_REPLY. This is faster than calling + usGenerateChecksum(). */ + + /* due to compiler warning "integer operation result is out of range" */ + + usRequest = ( uint16_t ) ( ( uint16_t )ipICMP_ECHO_REQUEST << 8 ); + + if( pxICMPHeader->usChecksum >= FreeRTOS_htons( 0xFFFFu - usRequest ) ) + { + pxICMPHeader->usChecksum = ( uint16_t ) + ( ( ( uint32_t ) pxICMPHeader->usChecksum ) + + FreeRTOS_htons( usRequest + 1UL ) ); + } + else + { + pxICMPHeader->usChecksum = ( uint16_t ) + ( ( ( uint32_t ) pxICMPHeader->usChecksum ) + + FreeRTOS_htons( usRequest ) ); + } + return eReturnEthernetFrame; + } + +#endif /* ipconfigREPLY_TO_INCOMING_PINGS == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ipconfigREPLY_TO_INCOMING_PINGS == 1 ) || ( ipconfigSUPPORT_OUTGOING_PINGS == 1 ) + + static eFrameProcessingResult_t prvProcessICMPPacket( ICMPPacket_t * const pxICMPPacket ) + { + eFrameProcessingResult_t eReturn = eReleaseBuffer; + + iptraceICMP_PACKET_RECEIVED(); + switch( pxICMPPacket->xICMPHeader.ucTypeOfMessage ) + { + case ipICMP_ECHO_REQUEST : + #if ( ipconfigREPLY_TO_INCOMING_PINGS == 1 ) + { + eReturn = prvProcessICMPEchoRequest( pxICMPPacket ); + } + #endif /* ( ipconfigREPLY_TO_INCOMING_PINGS == 1 ) */ + break; + + case ipICMP_ECHO_REPLY : + #if ( ipconfigSUPPORT_OUTGOING_PINGS == 1 ) + { + prvProcessICMPEchoReply( pxICMPPacket ); + } + #endif /* ipconfigSUPPORT_OUTGOING_PINGS */ + break; + + default : + break; + } + + return eReturn; + } + +#endif /* ( ipconfigREPLY_TO_INCOMING_PINGS == 1 ) || ( ipconfigSUPPORT_OUTGOING_PINGS == 1 ) */ +/*-----------------------------------------------------------*/ + +uint16_t usGenerateProtocolChecksum( const uint8_t * const pucEthernetBuffer, size_t uxBufferLength, BaseType_t xOutgoingPacket ) +{ +uint32_t ulLength; +uint16_t usChecksum, *pusChecksum; +const IPPacket_t * pxIPPacket; +UBaseType_t uxIPHeaderLength; +ProtocolPacket_t *pxProtPack; +uint8_t ucProtocol; +#if( ipconfigHAS_DEBUG_PRINTF != 0 ) + const char *pcType; +#endif + + /* Check for minimum packet size. */ + if( uxBufferLength < sizeof( IPPacket_t ) ) + { + return ipINVALID_LENGTH; + } + + /* Parse the packet length. */ + pxIPPacket = ( const IPPacket_t * ) pucEthernetBuffer; + + /* Per https://tools.ietf.org/html/rfc791, the four-bit Internet Header + Length field contains the length of the internet header in 32-bit words. */ + uxIPHeaderLength = ( UBaseType_t ) ( sizeof( uint32_t ) * ( pxIPPacket->xIPHeader.ucVersionHeaderLength & 0x0Fu ) ); + + /* Check for minimum packet size. */ + if( uxBufferLength < sizeof( IPPacket_t ) + uxIPHeaderLength - ipSIZE_OF_IPv4_HEADER ) + { + return ipINVALID_LENGTH; + } + if( uxBufferLength < FreeRTOS_ntohs( pxIPPacket->xIPHeader.usLength ) ) + { + return ipINVALID_LENGTH; + } + + /* Identify the next protocol. */ + ucProtocol = pxIPPacket->xIPHeader.ucProtocol; + + /* N.B., if this IP packet header includes Options, then the following + assignment results in a pointer into the protocol packet with the Ethernet + and IP headers incorrectly aligned. However, either way, the "third" + protocol (Layer 3 or 4) header will be aligned, which is the convenience + of this calculation. */ + pxProtPack = ( ProtocolPacket_t * ) ( pucEthernetBuffer + ( uxIPHeaderLength - ipSIZE_OF_IPv4_HEADER ) ); + + /* Switch on the Layer 3/4 protocol. */ + if( ucProtocol == ( uint8_t ) ipPROTOCOL_UDP ) + { + if( uxBufferLength < ( uxIPHeaderLength + ipSIZE_OF_ETH_HEADER + ipSIZE_OF_UDP_HEADER ) ) + { + return ipINVALID_LENGTH; + } + + pusChecksum = ( uint16_t * ) ( &( pxProtPack->xUDPPacket.xUDPHeader.usChecksum ) ); + #if( ipconfigHAS_DEBUG_PRINTF != 0 ) + { + pcType = "UDP"; + } + #endif /* ipconfigHAS_DEBUG_PRINTF != 0 */ + } + else if( ucProtocol == ( uint8_t ) ipPROTOCOL_TCP ) + { + if( uxBufferLength < ( uxIPHeaderLength + ipSIZE_OF_ETH_HEADER + ipSIZE_OF_TCP_HEADER ) ) + { + return ipINVALID_LENGTH; + } + + pusChecksum = ( uint16_t * ) ( &( pxProtPack->xTCPPacket.xTCPHeader.usChecksum ) ); + #if( ipconfigHAS_DEBUG_PRINTF != 0 ) + { + pcType = "TCP"; + } + #endif /* ipconfigHAS_DEBUG_PRINTF != 0 */ + } + else if( ( ucProtocol == ( uint8_t ) ipPROTOCOL_ICMP ) || + ( ucProtocol == ( uint8_t ) ipPROTOCOL_IGMP ) ) + { + if( uxBufferLength < ( uxIPHeaderLength + ipSIZE_OF_ETH_HEADER + ipSIZE_OF_ICMP_HEADER ) ) + { + return ipINVALID_LENGTH; + } + + pusChecksum = ( uint16_t * ) ( &( pxProtPack->xICMPPacket.xICMPHeader.usChecksum ) ); + #if( ipconfigHAS_DEBUG_PRINTF != 0 ) + { + if( ucProtocol == ( uint8_t ) ipPROTOCOL_ICMP ) + { + pcType = "ICMP"; + } + else + { + pcType = "IGMP"; + } + } + #endif /* ipconfigHAS_DEBUG_PRINTF != 0 */ + } + else + { + /* Unhandled protocol, other than ICMP, IGMP, UDP, or TCP. */ + return ipUNHANDLED_PROTOCOL; + } + + /* The protocol and checksum field have been identified. Check the direction + of the packet. */ + if( xOutgoingPacket != pdFALSE ) + { + /* This is an outgoing packet. Before calculating the checksum, set it + to zero. */ + *( pusChecksum ) = 0u; + } + else if( ( *pusChecksum == 0u ) && ( ucProtocol == ( uint8_t ) ipPROTOCOL_UDP ) ) + { + /* Sender hasn't set the checksum, no use to calculate it. */ + return ipCORRECT_CRC; + } + + ulLength = ( uint32_t ) + ( FreeRTOS_ntohs( pxIPPacket->xIPHeader.usLength ) - ( ( uint16_t ) uxIPHeaderLength ) ); /* normally minus 20 */ + + if( ( ulLength < sizeof( pxProtPack->xUDPPacket.xUDPHeader ) ) || + ( ulLength > ( uint32_t )( ipconfigNETWORK_MTU - uxIPHeaderLength ) ) ) + { + #if( ipconfigHAS_DEBUG_PRINTF != 0 ) + { + FreeRTOS_debug_printf( ( "usGenerateProtocolChecksum[%s]: len invalid: %lu\n", pcType, ulLength ) ); + } + #endif /* ipconfigHAS_DEBUG_PRINTF != 0 */ + + /* Again, in a 16-bit return value there is no space to indicate an + error. For incoming packets, 0x1234 will cause dropping of the packet. + For outgoing packets, there is a serious problem with the + format/length */ + return ipINVALID_LENGTH; + } + if( ucProtocol <= ( uint8_t ) ipPROTOCOL_IGMP ) + { + /* ICMP/IGMP do not have a pseudo header for CRC-calculation. */ + usChecksum = ( uint16_t ) + ( ~usGenerateChecksum( 0UL, + ( uint8_t * ) &( pxProtPack->xTCPPacket.xTCPHeader ), ( size_t ) ulLength ) ); + } + else + { + /* For UDP and TCP, sum the pseudo header, i.e. IP protocol + length + fields */ + usChecksum = ( uint16_t ) ( ulLength + ( ( uint16_t ) ucProtocol ) ); + + /* And then continue at the IPv4 source and destination addresses. */ + usChecksum = ( uint16_t ) + ( ~usGenerateChecksum( ( uint32_t ) usChecksum, ( uint8_t * )&( pxIPPacket->xIPHeader.ulSourceIPAddress ), + ( 2u * sizeof( pxIPPacket->xIPHeader.ulSourceIPAddress ) + ulLength ) ) ); + + /* Sum TCP header and data. */ + } + + if( xOutgoingPacket == pdFALSE ) + { + /* This is in incoming packet. If the CRC is correct, it should be zero. */ + if( usChecksum == 0u ) + { + usChecksum = ( uint16_t )ipCORRECT_CRC; + } + } + else + { + if( ( usChecksum == 0u ) && ( ucProtocol == ( uint8_t ) ipPROTOCOL_UDP ) ) + { + /* In case of UDP, a calculated checksum of 0x0000 is transmitted + as 0xffff. A value of zero would mean that the checksum is not used. */ + #if( ipconfigHAS_DEBUG_PRINTF != 0 ) + { + if( xOutgoingPacket != pdFALSE ) + { + FreeRTOS_debug_printf( ( "usGenerateProtocolChecksum[%s]: crc swap: %04X\n", pcType, usChecksum ) ); + } + } + #endif /* ipconfigHAS_DEBUG_PRINTF != 0 */ + + usChecksum = ( uint16_t )0xffffu; + } + } + usChecksum = FreeRTOS_htons( usChecksum ); + + if( xOutgoingPacket != pdFALSE ) + { + *( pusChecksum ) = usChecksum; + } + #if( ipconfigHAS_DEBUG_PRINTF != 0 ) + else if( ( xOutgoingPacket == pdFALSE ) && ( usChecksum != ipCORRECT_CRC ) ) + { + FreeRTOS_debug_printf( ( "usGenerateProtocolChecksum[%s]: ID %04X: from %lxip to %lxip bad crc: %04X\n", + pcType, + FreeRTOS_ntohs( pxIPPacket->xIPHeader.usIdentification ), + FreeRTOS_ntohl( pxIPPacket->xIPHeader.ulSourceIPAddress ), + FreeRTOS_ntohl( pxIPPacket->xIPHeader.ulDestinationIPAddress ), + FreeRTOS_ntohs( *pusChecksum ) ) ); + } + #endif /* ipconfigHAS_DEBUG_PRINTF != 0 */ + + return usChecksum; +} +/*-----------------------------------------------------------*/ + +/** + * This method generates a checksum for a given IPv4 header, per RFC791 (page 14). + * The checksum algorithm is decribed as: + * "[T]he 16 bit one's complement of the one's complement sum of all 16 bit words in the + * header. For purposes of computing the checksum, the value of the checksum field is zero." + * + * In a nutshell, that means that each 16-bit 'word' must be summed, after which + * the number of 'carries' (overflows) is added to the result. If that addition + * produces an overflow, that 'carry' must also be added to the final result. The final checksum + * should be the bitwise 'not' (ones-complement) of the result if the packet is + * meant to be transmitted, but this method simply returns the raw value, probably + * because when a packet is received, the checksum is verified by checking that + * ((received & calculated) == 0) without applying a bitwise 'not' to the 'calculated' checksum. + * + * This logic is optimized for microcontrollers which have limited resources, so the logic looks odd. + * It iterates over the full range of 16-bit words, but it does so by processing several 32-bit + * words at once whenever possible. Its first step is to align the memory pointer to a 32-bit boundary, + * after which it runs a fast loop to process multiple 32-bit words at once and adding their 'carries'. + * Finally, it finishes up by processing any remaining 16-bit words, and adding up all of the 'carries'. + * With 32-bit arithmetic, the number of 16-bit 'carries' produced by sequential additions can be found + * by looking at the 16 most-significant bits of the 32-bit integer, since a 32-bit int will continue + * counting up instead of overflowing after 16 bits. That is why the actual checksum calculations look like: + * union.u32 = ( uint32_t ) union.u16[ 0 ] + union.u16[ 1 ]; + * + * Arguments: + * ulSum: This argument provides a value to initialize the progressive summation + * of the header's values to. It is often 0, but protocols like TCP or UDP + * can have pseudo-header fields which need to be included in the checksum. + * pucNextData: This argument contains the address of the first byte which this + * method should process. The method's memory iterator is initialized to this value. + * uxDataLengthBytes: This argument contains the number of bytes that this method + * should process. + */ +uint16_t usGenerateChecksum( uint32_t ulSum, const uint8_t * pucNextData, size_t uxDataLengthBytes ) +{ +xUnion32 xSum2, xSum, xTerm; +xUnionPtr xSource; /* Points to first byte */ +xUnionPtr xLastSource; /* Points to last byte plus one */ +uint32_t ulAlignBits, ulCarry = 0ul; + + /* Small MCUs often spend up to 30% of the time doing checksum calculations + This function is optimised for 32-bit CPUs; Each time it will try to fetch + 32-bits, sums it with an accumulator and counts the number of carries. */ + + /* Swap the input (little endian platform only). */ + xSum.u32 = FreeRTOS_ntohs( ulSum ); + xTerm.u32 = 0ul; + + xSource.u8ptr = ( uint8_t * ) pucNextData; + ulAlignBits = ( ( ( uint32_t ) pucNextData ) & 0x03u ); /* gives 0, 1, 2, or 3 */ + + /* If byte (8-bit) aligned... */ + if( ( ( ulAlignBits & 1ul ) != 0ul ) && ( uxDataLengthBytes >= ( size_t ) 1 ) ) + { + xTerm.u8[ 1 ] = *( xSource.u8ptr ); + ( xSource.u8ptr )++; + uxDataLengthBytes--; + /* Now xSource is word (16-bit) aligned. */ + } + + /* If half-word (16-bit) aligned... */ + if( ( ( ulAlignBits == 1u ) || ( ulAlignBits == 2u ) ) && ( uxDataLengthBytes >= 2u ) ) + { + xSum.u32 += *(xSource.u16ptr); + ( xSource.u16ptr )++; + uxDataLengthBytes -= 2u; + /* Now xSource is word (32-bit) aligned. */ + } + + /* Word (32-bit) aligned, do the most part. */ + xLastSource.u32ptr = ( xSource.u32ptr + ( uxDataLengthBytes / 4u ) ) - 3u; + + /* In this loop, four 32-bit additions will be done, in total 16 bytes. + Indexing with constants (0,1,2,3) gives faster code than using + post-increments. */ + while( xSource.u32ptr < xLastSource.u32ptr ) + { + /* Use a secondary Sum2, just to see if the addition produced an + overflow. */ + xSum2.u32 = xSum.u32 + xSource.u32ptr[ 0 ]; + if( xSum2.u32 < xSum.u32 ) + { + ulCarry++; + } + + /* Now add the secondary sum to the major sum, and remember if there was + a carry. */ + xSum.u32 = xSum2.u32 + xSource.u32ptr[ 1 ]; + if( xSum2.u32 > xSum.u32 ) + { + ulCarry++; + } + + /* And do the same trick once again for indexes 2 and 3 */ + xSum2.u32 = xSum.u32 + xSource.u32ptr[ 2 ]; + if( xSum2.u32 < xSum.u32 ) + { + ulCarry++; + } + + xSum.u32 = xSum2.u32 + xSource.u32ptr[ 3 ]; + + if( xSum2.u32 > xSum.u32 ) + { + ulCarry++; + } + + /* And finally advance the pointer 4 * 4 = 16 bytes. */ + xSource.u32ptr += 4; + } + + /* Now add all carries. */ + xSum.u32 = ( uint32_t )xSum.u16[ 0 ] + xSum.u16[ 1 ] + ulCarry; + + uxDataLengthBytes %= 16u; + xLastSource.u8ptr = ( uint8_t * ) ( xSource.u8ptr + ( uxDataLengthBytes & ~( ( size_t ) 1 ) ) ); + + /* Half-word aligned. */ + while( xSource.u16ptr < xLastSource.u16ptr ) + { + /* At least one more short. */ + xSum.u32 += xSource.u16ptr[ 0 ]; + xSource.u16ptr++; + } + + if( ( uxDataLengthBytes & ( size_t ) 1 ) != 0u ) /* Maybe one more ? */ + { + xTerm.u8[ 0 ] = xSource.u8ptr[ 0 ]; + } + xSum.u32 += xTerm.u32; + + /* Now add all carries again. */ + xSum.u32 = ( uint32_t ) xSum.u16[ 0 ] + xSum.u16[ 1 ]; + + /* The previous summation might have given a 16-bit carry. */ + xSum.u32 = ( uint32_t ) xSum.u16[ 0 ] + xSum.u16[ 1 ]; + + if( ( ulAlignBits & 1u ) != 0u ) + { + /* Quite unlikely, but pucNextData might be non-aligned, which would + mean that a checksum is calculated starting at an odd position. */ + xSum.u32 = ( ( xSum.u32 & 0xffu ) << 8 ) | ( ( xSum.u32 & 0xff00u ) >> 8 ); + } + + /* swap the output (little endian platform only). */ + return FreeRTOS_htons( ( (uint16_t) xSum.u32 ) ); +} +/*-----------------------------------------------------------*/ + +void vReturnEthernetFrame( NetworkBufferDescriptor_t * pxNetworkBuffer, BaseType_t xReleaseAfterSend ) +{ +EthernetHeader_t *pxEthernetHeader; + +#if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + NetworkBufferDescriptor_t *pxNewBuffer; +#endif + + #if defined( ipconfigETHERNET_MINIMUM_PACKET_BYTES ) + { + if( pxNetworkBuffer->xDataLength < ( size_t ) ipconfigETHERNET_MINIMUM_PACKET_BYTES ) + { + BaseType_t xIndex; + + FreeRTOS_printf( ( "vReturnEthernetFrame: length %lu\n", ( uint32_t )pxNetworkBuffer->xDataLength ) ); + for( xIndex = ( BaseType_t ) pxNetworkBuffer->xDataLength; xIndex < ( BaseType_t ) ipconfigETHERNET_MINIMUM_PACKET_BYTES; xIndex++ ) + { + pxNetworkBuffer->pucEthernetBuffer[ xIndex ] = 0u; + } + pxNetworkBuffer->xDataLength = ( size_t ) ipconfigETHERNET_MINIMUM_PACKET_BYTES; + } + } + #endif + +#if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + + if( xReleaseAfterSend == pdFALSE ) + { + pxNewBuffer = pxDuplicateNetworkBufferWithDescriptor( pxNetworkBuffer, ( BaseType_t ) pxNetworkBuffer->xDataLength ); + xReleaseAfterSend = pdTRUE; + pxNetworkBuffer = pxNewBuffer; + } + + if( pxNetworkBuffer != NULL ) +#endif + { + pxEthernetHeader = ( EthernetHeader_t * ) ( pxNetworkBuffer->pucEthernetBuffer ); + + /* Swap source and destination MAC addresses. */ + memcpy( ( void * ) &( pxEthernetHeader->xDestinationAddress ), ( void * ) &( pxEthernetHeader->xSourceAddress ), sizeof( pxEthernetHeader->xDestinationAddress ) ); + memcpy( ( void * ) &( pxEthernetHeader->xSourceAddress) , ( void * ) ipLOCAL_MAC_ADDRESS, ( size_t ) ipMAC_ADDRESS_LENGTH_BYTES ); + + /* Send! */ + xNetworkInterfaceOutput( pxNetworkBuffer, xReleaseAfterSend ); + } +} +/*-----------------------------------------------------------*/ + +uint32_t FreeRTOS_GetIPAddress( void ) +{ + /* Returns the IP address of the NIC. */ + return *ipLOCAL_IP_ADDRESS_POINTER; +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_SetIPAddress( uint32_t ulIPAddress ) +{ + /* Sets the IP address of the NIC. */ + *ipLOCAL_IP_ADDRESS_POINTER = ulIPAddress; +} +/*-----------------------------------------------------------*/ + +uint32_t FreeRTOS_GetGatewayAddress( void ) +{ + return xNetworkAddressing.ulGatewayAddress; +} +/*-----------------------------------------------------------*/ + +uint32_t FreeRTOS_GetDNSServerAddress( void ) +{ + return xNetworkAddressing.ulDNSServerAddress; +} +/*-----------------------------------------------------------*/ + +uint32_t FreeRTOS_GetNetmask( void ) +{ + return xNetworkAddressing.ulNetMask; +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_UpdateMACAddress( const uint8_t ucMACAddress[ipMAC_ADDRESS_LENGTH_BYTES] ) +{ + /* Copy the MAC address at the start of the default packet header fragment. */ + memcpy( ( void * )ipLOCAL_MAC_ADDRESS, ( void * )ucMACAddress, ( size_t )ipMAC_ADDRESS_LENGTH_BYTES ); +} +/*-----------------------------------------------------------*/ + +const uint8_t * FreeRTOS_GetMACAddress( void ) +{ + return ipLOCAL_MAC_ADDRESS; +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_SetNetmask ( uint32_t ulNetmask ) +{ + xNetworkAddressing.ulNetMask = ulNetmask; +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_SetGatewayAddress ( uint32_t ulGatewayAddress ) +{ + xNetworkAddressing.ulGatewayAddress = ulGatewayAddress; +} +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_DHCP == 1 ) + void vIPSetDHCPTimerEnableState( BaseType_t xEnableState ) + { + if( xEnableState != pdFALSE ) + { + xDHCPTimer.bActive = pdTRUE_UNSIGNED; + } + else + { + xDHCPTimer.bActive = pdFALSE_UNSIGNED; + } + } +#endif /* ipconfigUSE_DHCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_DHCP == 1 ) + void vIPReloadDHCPTimer( uint32_t ulLeaseTime ) + { + prvIPTimerReload( &xDHCPTimer, ulLeaseTime ); + } +#endif /* ipconfigUSE_DHCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigDNS_USE_CALLBACKS == 1 ) + void vIPSetDnsTimerEnableState( BaseType_t xEnableState ) + { + if( xEnableState != 0 ) + { + xDNSTimer.bActive = pdTRUE; + } + else + { + xDNSTimer.bActive = pdFALSE; + } + } +#endif /* ipconfigUSE_DHCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigDNS_USE_CALLBACKS != 0 ) + void vIPReloadDNSTimer( uint32_t ulCheckTime ) + { + prvIPTimerReload( &xDNSTimer, ulCheckTime ); + } +#endif /* ipconfigDNS_USE_CALLBACKS != 0 */ +/*-----------------------------------------------------------*/ + +BaseType_t xIPIsNetworkTaskReady( void ) +{ + return xIPTaskInitialised; +} +/*-----------------------------------------------------------*/ + +BaseType_t FreeRTOS_IsNetworkUp( void ) +{ + return xNetworkUp; +} +/*-----------------------------------------------------------*/ + +#if( ipconfigCHECK_IP_QUEUE_SPACE != 0 ) + UBaseType_t uxGetMinimumIPQueueSpace( void ) + { + return uxQueueMinimumSpace; + } +#endif +/*-----------------------------------------------------------*/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_Sockets.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_Sockets.c new file mode 100644 index 0000000..ce03f61 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_Sockets.c @@ -0,0 +1,3632 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +/* Standard includes. */ +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_UDP_IP.h" +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_IP_Private.h" +#include "FreeRTOS_DNS.h" +#include "NetworkBufferManagement.h" + +/* The ItemValue of the sockets xBoundSocketListItem member holds the socket's +port number. */ +#define socketSET_SOCKET_PORT( pxSocket, usPort ) listSET_LIST_ITEM_VALUE( ( &( ( pxSocket )->xBoundSocketListItem ) ), ( usPort ) ) +#define socketGET_SOCKET_PORT( pxSocket ) listGET_LIST_ITEM_VALUE( ( &( ( pxSocket )->xBoundSocketListItem ) ) ) + +/* Test if a socket it bound which means it is either included in +xBoundUDPSocketsList or xBoundTCPSocketsList */ +#define socketSOCKET_IS_BOUND( pxSocket ) ( listLIST_ITEM_CONTAINER( & ( pxSocket )->xBoundSocketListItem ) != NULL ) + +/* If FreeRTOS_sendto() is called on a socket that is not bound to a port +number then, depending on the FreeRTOSIPConfig.h settings, it might be that a +port number is automatically generated for the socket. Automatically generated +port numbers will be between socketAUTO_PORT_ALLOCATION_START_NUMBER and +0xffff. + +Per https://tools.ietf.org/html/rfc6056, "the dynamic ports consist of the range +49152-65535. However, ephemeral port selection algorithms should use the whole +range 1024-65535" excluding those already in use (inbound or outbound). */ +#if !defined( socketAUTO_PORT_ALLOCATION_START_NUMBER ) + #define socketAUTO_PORT_ALLOCATION_START_NUMBER ( ( uint16_t ) 0x0400 ) +#endif + +#define socketAUTO_PORT_ALLOCATION_MAX_NUMBER ( ( uint16_t ) 0xffff ) + +/* The number of octets that make up an IP address. */ +#define socketMAX_IP_ADDRESS_OCTETS 4u + +/* A block time of 0 simply means "don't block". */ +#define socketDONT_BLOCK ( ( TickType_t ) 0 ) + +#if( ( ipconfigUSE_TCP == 1 ) && !defined( ipTCP_TIMER_PERIOD_MS ) ) + #define ipTCP_TIMER_PERIOD_MS ( 1000 ) +#endif + +/* The next private port number to use when binding a client socket is stored in +the usNextPortToUse[] array - which has either 1 or two indexes depending on +whether TCP is being supported. */ +#if( ipconfigUSE_TCP == 1 ) + #define socketPROTOCOL_COUNT 2 +#else + #define socketPROTOCOL_COUNT 1 +#endif + +/* Indexes into the usNextPortToUse[] array for UDP and TCP sockets +respectively. */ +#define socketNEXT_UDP_PORT_NUMBER_INDEX 0 +#define socketNEXT_TCP_PORT_NUMBER_INDEX 1 + + +/*-----------------------------------------------------------*/ + +/* + * Allocate the next port number from the private allocation range. + * TCP and UDP each have their own series of port numbers + * ulProtocol is either ipPROTOCOL_UDP or ipPROTOCOL_TCP + */ +static uint16_t prvGetPrivatePortNumber( BaseType_t xProtocol ); + +/* + * Return the list item from within pxList that has an item value of + * xWantedItemValue. If there is no such list item return NULL. + */ +static const ListItem_t * pxListFindListItemWithValue( const List_t *pxList, TickType_t xWantedItemValue ); + +/* + * Return pdTRUE only if pxSocket is valid and bound, as far as can be + * determined. + */ +static BaseType_t prvValidSocket( FreeRTOS_Socket_t *pxSocket, BaseType_t xProtocol, BaseType_t xIsBound ); + +/* + * Before creating a socket, check the validity of the parameters used + * and find the size of the socket space, which is different for UDP and TCP + */ +static BaseType_t prvDetermineSocketSize( BaseType_t xDomain, BaseType_t xType, BaseType_t xProtocol, size_t *pxSocketSize ); + +#if( ipconfigUSE_TCP == 1 ) + /* + * Create a txStream or a rxStream, depending on the parameter 'xIsInputStream' + */ + static StreamBuffer_t *prvTCPCreateStream (FreeRTOS_Socket_t *pxSocket, BaseType_t xIsInputStream ); +#endif /* ipconfigUSE_TCP == 1 */ + +#if( ipconfigUSE_TCP == 1 ) + /* + * Called from FreeRTOS_send(): some checks which will be done before + * sending a TCP packed. + */ + static int32_t prvTCPSendCheck( FreeRTOS_Socket_t *pxSocket, size_t xDataLength ); +#endif /* ipconfigUSE_TCP */ + +#if( ipconfigUSE_TCP == 1 ) + /* + * When a child socket gets closed, make sure to update the child-count of the parent + */ + static void prvTCPSetSocketCount( FreeRTOS_Socket_t *pxSocketToDelete ); +#endif /* ipconfigUSE_TCP == 1 */ + +#if( ipconfigUSE_TCP == 1 ) + /* + * Called from FreeRTOS_connect(): make some checks and if allowed, send a + * message to the IP-task to start connecting to a remote socket + */ + static BaseType_t prvTCPConnectStart( FreeRTOS_Socket_t *pxSocket, struct freertos_sockaddr *pxAddress ); +#endif /* ipconfigUSE_TCP */ + +#if( ipconfigSUPPORT_SELECT_FUNCTION == 1 ) + + /* Executed by the IP-task, it will check all sockets belonging to a set */ + static FreeRTOS_Socket_t *prvFindSelectedSocket( SocketSelect_t *pxSocketSet ); + +#endif /* ipconfigSUPPORT_SELECT_FUNCTION == 1 */ +/*-----------------------------------------------------------*/ + +/* The list that contains mappings between sockets and port numbers. Accesses +to this list must be protected by critical sections of one kind or another. */ +List_t xBoundUDPSocketsList; + +#if ipconfigUSE_TCP == 1 + List_t xBoundTCPSocketsList; +#endif /* ipconfigUSE_TCP == 1 */ + +/*-----------------------------------------------------------*/ + +static BaseType_t prvValidSocket( FreeRTOS_Socket_t *pxSocket, BaseType_t xProtocol, BaseType_t xIsBound ) +{ +BaseType_t xReturn = pdTRUE; + + if( ( pxSocket == NULL ) || ( pxSocket == FREERTOS_INVALID_SOCKET ) ) + { + xReturn = pdFALSE; + } + else if( ( xIsBound != pdFALSE ) && ( socketSOCKET_IS_BOUND( pxSocket ) == pdFALSE ) ) + { + /* The caller expects the socket to be bound, but it isn't. */ + xReturn = pdFALSE; + } + else if( pxSocket->ucProtocol != ( uint8_t ) xProtocol ) + { + /* Socket has a wrong type (UDP != TCP). */ + xReturn = pdFALSE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t vNetworkSocketsInit( void ) +{ + vListInitialise( &xBoundUDPSocketsList ); + + #if( ipconfigUSE_TCP == 1 ) + { + vListInitialise( &xBoundTCPSocketsList ); + } + #endif /* ipconfigUSE_TCP == 1 */ + + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvDetermineSocketSize( BaseType_t xDomain, BaseType_t xType, BaseType_t xProtocol, size_t *pxSocketSize ) +{ +BaseType_t xReturn = pdPASS; +FreeRTOS_Socket_t *pxSocket; + + /* Asserts must not appear before it has been determined that the network + task is ready - otherwise the asserts will fail. */ + if( xIPIsNetworkTaskReady() == pdFALSE ) + { + xReturn = pdFAIL; + } + else + { + /* Only Ethernet is currently supported. */ + configASSERT( xDomain == FREERTOS_AF_INET ); + + /* Check if the UDP socket-list has been initialised. */ + configASSERT( listLIST_IS_INITIALISED( &xBoundUDPSocketsList ) ); + #if( ipconfigUSE_TCP == 1 ) + { + /* Check if the TCP socket-list has been initialised. */ + configASSERT( listLIST_IS_INITIALISED( &xBoundTCPSocketsList ) ); + } + #endif /* ipconfigUSE_TCP == 1 */ + + if( xProtocol == FREERTOS_IPPROTO_UDP ) + { + if( xType != FREERTOS_SOCK_DGRAM ) + { + xReturn = pdFAIL; + configASSERT( xReturn ); + } + /* In case a UDP socket is created, do not allocate space for TCP data. */ + *pxSocketSize = ( sizeof( *pxSocket ) - sizeof( pxSocket->u ) ) + sizeof( pxSocket->u.xUDP ); + } +#if( ipconfigUSE_TCP == 1 ) + else if( xProtocol == FREERTOS_IPPROTO_TCP ) + { + if( xType != FREERTOS_SOCK_STREAM ) + { + xReturn = pdFAIL; + configASSERT( xReturn ); + } + + *pxSocketSize = ( sizeof( *pxSocket ) - sizeof( pxSocket->u ) ) + sizeof( pxSocket->u.xTCP ); + } +#endif /* ipconfigUSE_TCP == 1 */ + else + { + xReturn = pdFAIL; + configASSERT( xReturn ); + } + } + /* In case configASSERT() is not used */ + ( void )xDomain; + return xReturn; +} +/*-----------------------------------------------------------*/ + +/* FreeRTOS_socket() allocates and initiates a socket */ +Socket_t FreeRTOS_socket( BaseType_t xDomain, BaseType_t xType, BaseType_t xProtocol ) +{ +FreeRTOS_Socket_t *pxSocket; +size_t uxSocketSize; +EventGroupHandle_t xEventGroup; +Socket_t xReturn; + + if( prvDetermineSocketSize( xDomain, xType, xProtocol, &uxSocketSize ) == pdFAIL ) + { + xReturn = FREERTOS_INVALID_SOCKET; + } + else + { + /* Allocate the structure that will hold the socket information. The + size depends on the type of socket: UDP sockets need less space. A + define 'pvPortMallocSocket' will used to allocate the necessary space. + By default it points to the FreeRTOS function 'pvPortMalloc()'. */ + pxSocket = ( FreeRTOS_Socket_t * ) pvPortMallocSocket( uxSocketSize ); + + if( pxSocket == NULL ) + { + pxSocket = ( FreeRTOS_Socket_t * ) FREERTOS_INVALID_SOCKET; + iptraceFAILED_TO_CREATE_SOCKET(); + } + else if( ( xEventGroup = xEventGroupCreate() ) == NULL ) + { + vPortFreeSocket( pxSocket ); + pxSocket = ( FreeRTOS_Socket_t * ) FREERTOS_INVALID_SOCKET; + iptraceFAILED_TO_CREATE_EVENT_GROUP(); + } + else + { + /* Clear the entire space to avoid nulling individual entries */ + memset( pxSocket, '\0', uxSocketSize ); + + pxSocket->xEventGroup = xEventGroup; + + /* Initialise the socket's members. The semaphore will be created + if the socket is bound to an address, for now the pointer to the + semaphore is just set to NULL to show it has not been created. */ + if( xProtocol == FREERTOS_IPPROTO_UDP ) + { + vListInitialise( &( pxSocket->u.xUDP.xWaitingPacketsList ) ); + + #if( ipconfigUDP_MAX_RX_PACKETS > 0 ) + { + pxSocket->u.xUDP.uxMaxPackets = ( UBaseType_t ) ipconfigUDP_MAX_RX_PACKETS; + } + #endif /* ipconfigUDP_MAX_RX_PACKETS > 0 */ + } + + vListInitialiseItem( &( pxSocket->xBoundSocketListItem ) ); + listSET_LIST_ITEM_OWNER( &( pxSocket->xBoundSocketListItem ), ( void * ) pxSocket ); + + pxSocket->xReceiveBlockTime = ipconfigSOCK_DEFAULT_RECEIVE_BLOCK_TIME; + pxSocket->xSendBlockTime = ipconfigSOCK_DEFAULT_SEND_BLOCK_TIME; + pxSocket->ucSocketOptions = ( uint8_t ) FREERTOS_SO_UDPCKSUM_OUT; + pxSocket->ucProtocol = ( uint8_t ) xProtocol; /* protocol: UDP or TCP */ + + #if( ipconfigUSE_TCP == 1 ) + { + if( xProtocol == FREERTOS_IPPROTO_TCP ) + { + /* StreamSize is expressed in number of bytes */ + /* Round up buffer sizes to nearest multiple of MSS */ + pxSocket->u.xTCP.usInitMSS = pxSocket->u.xTCP.usCurMSS = ipconfigTCP_MSS; + pxSocket->u.xTCP.uxRxStreamSize = ( size_t ) ipconfigTCP_RX_BUFFER_LENGTH; + pxSocket->u.xTCP.uxTxStreamSize = ( size_t ) FreeRTOS_round_up( ipconfigTCP_TX_BUFFER_LENGTH, ipconfigTCP_MSS ); + /* Use half of the buffer size of the TCP windows */ + #if ( ipconfigUSE_TCP_WIN == 1 ) + { + pxSocket->u.xTCP.uxRxWinSize = FreeRTOS_max_uint32( 1UL, ( uint32_t ) ( pxSocket->u.xTCP.uxRxStreamSize / 2 ) / ipconfigTCP_MSS ); + pxSocket->u.xTCP.uxTxWinSize = FreeRTOS_max_uint32( 1UL, ( uint32_t ) ( pxSocket->u.xTCP.uxTxStreamSize / 2 ) / ipconfigTCP_MSS ); + } + #else + { + pxSocket->u.xTCP.uxRxWinSize = 1u; + pxSocket->u.xTCP.uxTxWinSize = 1u; + } + #endif + /* The above values are just defaults, and can be overridden by + calling FreeRTOS_setsockopt(). No buffers will be allocated until a + socket is connected and data is exchanged. */ + } + } + #endif /* ipconfigUSE_TCP == 1 */ + } + + xReturn = ( Socket_t ) pxSocket; + } + + /* Remove compiler warnings in the case the configASSERT() is not defined. */ + ( void ) xDomain; + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if( ipconfigSUPPORT_SELECT_FUNCTION == 1 ) + + SocketSet_t FreeRTOS_CreateSocketSet( void ) + { + SocketSelect_t *pxSocketSet; + + pxSocketSet = ( SocketSelect_t * ) pvPortMalloc( sizeof( *pxSocketSet ) ); + + if( pxSocketSet != NULL ) + { + memset( pxSocketSet, '\0', sizeof( *pxSocketSet ) ); + pxSocketSet->xSelectGroup = xEventGroupCreate(); + + if( pxSocketSet->xSelectGroup == NULL ) + { + vPortFree( ( void* ) pxSocketSet ); + pxSocketSet = NULL; + } + } + + return ( SocketSet_t * ) pxSocketSet; + } + +#endif /* ipconfigSUPPORT_SELECT_FUNCTION == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigSUPPORT_SELECT_FUNCTION == 1 ) + + void FreeRTOS_DeleteSocketSet( SocketSet_t xSocketSet ) + { + SocketSelect_t *pxSocketSet = ( SocketSelect_t*) xSocketSet; + + vEventGroupDelete( pxSocketSet->xSelectGroup ); + vPortFree( ( void* ) pxSocketSet ); + } + +#endif /* ipconfigSUPPORT_SELECT_FUNCTION == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigSUPPORT_SELECT_FUNCTION == 1 ) + + /* Add a socket to a set */ + void FreeRTOS_FD_SET( Socket_t xSocket, SocketSet_t xSocketSet, EventBits_t xSelectBits ) + { + FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) xSocket; + SocketSelect_t *pxSocketSet = ( SocketSelect_t * ) xSocketSet; + + configASSERT( pxSocket != NULL ); + configASSERT( xSocketSet != NULL ); + + /* Make sure we're not adding bits which are reserved for internal use, + such as eSELECT_CALL_IP */ + pxSocket->xSelectBits |= ( xSelectBits & eSELECT_ALL ); + + if( ( pxSocket->xSelectBits & eSELECT_ALL ) != 0 ) + { + /* Adding a socket to a socket set. */ + pxSocket->pxSocketSet = ( SocketSelect_t * ) xSocketSet; + + /* Now have the IP-task call vSocketSelect() to see if the set contains + any sockets which are 'ready' and set the proper bits. + By setting 'bApiCalled = false', vSocketSelect() knows that it was + not called from a user API */ + pxSocketSet->bApiCalled = pdFALSE; + prvFindSelectedSocket( pxSocketSet ); + } + } + +#endif /* ipconfigSUPPORT_SELECT_FUNCTION == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigSUPPORT_SELECT_FUNCTION == 1 ) + /* Clear select bits for a socket + If the mask becomes 0, remove the socket from the set */ + void FreeRTOS_FD_CLR( Socket_t xSocket, SocketSet_t xSocketSet, EventBits_t xSelectBits ) + { + FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) xSocket; + + configASSERT( pxSocket != NULL ); + configASSERT( xSocketSet != NULL ); + + pxSocket->xSelectBits &= ~( xSelectBits & eSELECT_ALL ); + if( ( pxSocket->xSelectBits & eSELECT_ALL ) != 0 ) + { + pxSocket->pxSocketSet = ( SocketSelect_t *)xSocketSet; + } + else + { + /* disconnect it from the socket set */ + pxSocket->pxSocketSet = ( SocketSelect_t *)NULL; + } + } + +#endif /* ipconfigSUPPORT_SELECT_FUNCTION == 1 */ +/*-----------------------------------------------------------*/ + + +#if( ipconfigSUPPORT_SELECT_FUNCTION == 1 ) + + /* Test if a socket belongs to a socket-set */ + EventBits_t FreeRTOS_FD_ISSET( Socket_t xSocket, SocketSet_t xSocketSet ) + { + EventBits_t xReturn; + FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) xSocket; + + configASSERT( pxSocket != NULL ); + configASSERT( xSocketSet != NULL ); + + if( xSocketSet == ( SocketSet_t ) pxSocket->pxSocketSet ) + { + /* Make sure we're not adding bits which are reserved for internal + use. */ + xReturn = pxSocket->xSocketBits & eSELECT_ALL; + } + else + { + xReturn = 0; + } + + return xReturn; + } + +#endif /* ipconfigSUPPORT_SELECT_FUNCTION == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigSUPPORT_SELECT_FUNCTION == 1 ) + + /* The select() statement: wait for an event to occur on any of the sockets + included in a socket set */ + BaseType_t FreeRTOS_select( SocketSet_t xSocketSet, TickType_t xBlockTimeTicks ) + { + TimeOut_t xTimeOut; + TickType_t xRemainingTime; + SocketSelect_t *pxSocketSet = ( SocketSelect_t*) xSocketSet; + BaseType_t xResult; + + configASSERT( xSocketSet != NULL ); + + /* Only in the first round, check for non-blocking */ + xRemainingTime = xBlockTimeTicks; + + /* Fetch the current time */ + vTaskSetTimeOutState( &xTimeOut ); + + for( ;; ) + { + /* Find a socket which might have triggered the bit + This function might return immediately or block for a limited time */ + xResult = ( BaseType_t ) xEventGroupWaitBits( pxSocketSet->xSelectGroup, eSELECT_ALL, pdFALSE, pdFALSE, xRemainingTime ); + + #if( ipconfigSUPPORT_SIGNALS != 0 ) + { + if( ( xResult & eSELECT_INTR ) != 0u ) + { + xEventGroupClearBits( pxSocketSet->xSelectGroup, eSELECT_INTR ); + FreeRTOS_debug_printf( ( "FreeRTOS_select: interrupted\n" ) ); + break; + } + } + #endif /* ipconfigSUPPORT_SIGNALS */ + + /* Have the IP-task find the socket which had an event */ + pxSocketSet->bApiCalled = pdTRUE; + prvFindSelectedSocket( pxSocketSet ); + + xResult = ( BaseType_t ) xEventGroupGetBits( pxSocketSet->xSelectGroup ); + + if( xResult != 0 ) + { + break; + } + + /* Has the timeout been reached? */ + if( xTaskCheckForTimeOut( &xTimeOut, &xRemainingTime ) != pdFALSE ) + { + break; + } + } + + return xResult; + } + +#endif /* ipconfigSUPPORT_SELECT_FUNCTION */ +/*-----------------------------------------------------------*/ + +#if( ipconfigSUPPORT_SELECT_FUNCTION == 1 ) + + /* Send a message to the IP-task to have it check all sockets belonging to + 'pxSocketSet' */ + static FreeRTOS_Socket_t *prvFindSelectedSocket( SocketSelect_t *pxSocketSet ) + { + IPStackEvent_t xSelectEvent; + FreeRTOS_Socket_t *xReturn; + + xSelectEvent.eEventType = eSocketSelectEvent; + xSelectEvent.pvData = ( void * ) pxSocketSet; + + /* while the IP-task works on the request, the API will block on + 'eSELECT_CALL_IP'. So clear it first. */ + xEventGroupClearBits( pxSocketSet->xSelectGroup, eSELECT_CALL_IP ); + + /* Now send the socket select event */ + if( xSendEventStructToIPTask( &xSelectEvent, ( TickType_t ) portMAX_DELAY ) == pdFAIL ) + { + /* Oops, we failed to wake-up the IP task. No use to wait for it. */ + FreeRTOS_debug_printf( ( "prvFindSelectedSocket: failed\n" ) ); + xReturn = NULL; + } + else + { + /* As soon as the IP-task is ready, it will set 'eSELECT_CALL_IP' to + wakeup the calling API */ + xEventGroupWaitBits( pxSocketSet->xSelectGroup, eSELECT_CALL_IP, pdTRUE, pdFALSE, portMAX_DELAY ); + + /* Return 'pxSocket' which is set by the IP-task */ + xReturn = pxSocketSet->pxSocket; + } + + return xReturn; + } + +#endif /* ipconfigSUPPORT_SELECT_FUNCTION == 1 */ +/*-----------------------------------------------------------*/ + +/* + * FreeRTOS_recvfrom: receive data from a bound socket + * In this library, the function can only be used with connectionsless sockets + * (UDP) + */ +int32_t FreeRTOS_recvfrom( Socket_t xSocket, void *pvBuffer, size_t xBufferLength, BaseType_t xFlags, struct freertos_sockaddr *pxSourceAddress, socklen_t *pxSourceAddressLength ) +{ +BaseType_t lPacketCount = 0; +NetworkBufferDescriptor_t *pxNetworkBuffer; +FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) xSocket; +TickType_t xRemainingTime = ( TickType_t ) 0; /* Obsolete assignment, but some compilers output a warning if its not done. */ +BaseType_t xTimed = pdFALSE; +TimeOut_t xTimeOut; +int32_t lReturn; +EventBits_t xEventBits = ( EventBits_t ) 0; + + if( prvValidSocket( pxSocket, FREERTOS_IPPROTO_UDP, pdTRUE ) == pdFALSE ) + { + return -pdFREERTOS_ERRNO_EINVAL; + } + + lPacketCount = ( BaseType_t ) listCURRENT_LIST_LENGTH( &( pxSocket->u.xUDP.xWaitingPacketsList ) ); + + /* The function prototype is designed to maintain the expected Berkeley + sockets standard, but this implementation does not use all the parameters. */ + ( void ) pxSourceAddressLength; + + while( lPacketCount == 0 ) + { + if( xTimed == pdFALSE ) + { + /* Check to see if the socket is non blocking on the first + iteration. */ + xRemainingTime = pxSocket->xReceiveBlockTime; + + if( xRemainingTime == ( TickType_t ) 0 ) + { + #if( ipconfigSUPPORT_SIGNALS != 0 ) + { + /* Just check for the interrupt flag. */ + xEventBits = xEventGroupWaitBits( pxSocket->xEventGroup, eSOCKET_INTR, + pdTRUE /*xClearOnExit*/, pdFALSE /*xWaitAllBits*/, socketDONT_BLOCK ); + } + #endif /* ipconfigSUPPORT_SIGNALS */ + break; + } + + if( ( xFlags & FREERTOS_MSG_DONTWAIT ) != 0 ) + { + break; + } + + /* To ensure this part only executes once. */ + xTimed = pdTRUE; + + /* Fetch the current time. */ + vTaskSetTimeOutState( &xTimeOut ); + } + + /* Wait for arrival of data. While waiting, the IP-task may set the + 'eSOCKET_RECEIVE' bit in 'xEventGroup', if it receives data for this + socket, thus unblocking this API call. */ + xEventBits = xEventGroupWaitBits( pxSocket->xEventGroup, eSOCKET_RECEIVE | eSOCKET_INTR, + pdTRUE /*xClearOnExit*/, pdFALSE /*xWaitAllBits*/, xRemainingTime ); + + #if( ipconfigSUPPORT_SIGNALS != 0 ) + { + if( ( xEventBits & eSOCKET_INTR ) != 0 ) + { + if( ( xEventBits & eSOCKET_RECEIVE ) != 0 ) + { + /* Shouldn't have cleared the eSOCKET_RECEIVE flag. */ + xEventGroupSetBits( pxSocket->xEventGroup, eSOCKET_RECEIVE ); + } + break; + } + } + #else + { + ( void ) xEventBits; + } + #endif /* ipconfigSUPPORT_SIGNALS */ + + lPacketCount = ( BaseType_t ) listCURRENT_LIST_LENGTH( &( pxSocket->u.xUDP.xWaitingPacketsList ) ); + + if( lPacketCount != 0 ) + { + break; + } + + /* Has the timeout been reached ? */ + if( xTaskCheckForTimeOut( &xTimeOut, &xRemainingTime ) ) + { + break; + } + } /* while( lPacketCount == 0 ) */ + + if( lPacketCount != 0 ) + { + taskENTER_CRITICAL(); + { + /* The owner of the list item is the network buffer. */ + pxNetworkBuffer = ( NetworkBufferDescriptor_t * ) listGET_OWNER_OF_HEAD_ENTRY( &( pxSocket->u.xUDP.xWaitingPacketsList ) ); + + if( ( xFlags & FREERTOS_MSG_PEEK ) == 0 ) + { + /* Remove the network buffer from the list of buffers waiting to + be processed by the socket. */ + uxListRemove( &( pxNetworkBuffer->xBufferListItem ) ); + } + } + taskEXIT_CRITICAL(); + + /* The returned value is the data length, which may have been capped to + the receive buffer size. */ + lReturn = ( int32_t ) pxNetworkBuffer->xDataLength; + + if( pxSourceAddress != NULL ) + { + pxSourceAddress->sin_port = pxNetworkBuffer->usPort; + pxSourceAddress->sin_addr = pxNetworkBuffer->ulIPAddress; + } + + if( ( xFlags & FREERTOS_ZERO_COPY ) == 0 ) + { + /* The zero copy flag is not set. Truncate the length if it won't + fit in the provided buffer. */ + if( lReturn > ( int32_t ) xBufferLength ) + { + iptraceRECVFROM_DISCARDING_BYTES( ( xBufferLength - lReturn ) ); + lReturn = ( int32_t )xBufferLength; + } + + /* Copy the received data into the provided buffer, then release the + network buffer. */ + memcpy( pvBuffer, ( void * ) &( pxNetworkBuffer->pucEthernetBuffer[ ipUDP_PAYLOAD_OFFSET_IPv4 ] ), ( size_t )lReturn ); + + if( ( xFlags & FREERTOS_MSG_PEEK ) == 0 ) + { + vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ); + } + } + else + { + /* The zero copy flag was set. pvBuffer is not a buffer into which + the received data can be copied, but a pointer that must be set to + point to the buffer in which the received data has already been + placed. */ + *( ( void** ) pvBuffer ) = ( void * ) ( &( pxNetworkBuffer->pucEthernetBuffer[ ipUDP_PAYLOAD_OFFSET_IPv4 ] ) ); + } + + } +#if( ipconfigSUPPORT_SIGNALS != 0 ) + else if( ( xEventBits & eSOCKET_INTR ) != 0 ) + { + lReturn = -pdFREERTOS_ERRNO_EINTR; + iptraceRECVFROM_INTERRUPTED(); + } +#endif /* ipconfigSUPPORT_SIGNALS */ + else + { + lReturn = -pdFREERTOS_ERRNO_EWOULDBLOCK; + iptraceRECVFROM_TIMEOUT(); + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + +int32_t FreeRTOS_sendto( Socket_t xSocket, const void *pvBuffer, size_t xTotalDataLength, BaseType_t xFlags, const struct freertos_sockaddr *pxDestinationAddress, socklen_t xDestinationAddressLength ) +{ +NetworkBufferDescriptor_t *pxNetworkBuffer; +IPStackEvent_t xStackTxEvent = { eStackTxEvent, NULL }; +TimeOut_t xTimeOut; +TickType_t xTicksToWait; +int32_t lReturn = 0; +FreeRTOS_Socket_t *pxSocket; + + pxSocket = ( FreeRTOS_Socket_t * ) xSocket; + + /* The function prototype is designed to maintain the expected Berkeley + sockets standard, but this implementation does not use all the + parameters. */ + ( void ) xDestinationAddressLength; + configASSERT( pvBuffer ); + + if( xTotalDataLength <= ( size_t ) ipMAX_UDP_PAYLOAD_LENGTH ) + { + /* If the socket is not already bound to an address, bind it now. + Passing NULL as the address parameter tells FreeRTOS_bind() to select + the address to bind to. */ + if( ( socketSOCKET_IS_BOUND( pxSocket ) != pdFALSE ) || + ( FreeRTOS_bind( xSocket, NULL, 0u ) == 0 ) ) + { + xTicksToWait = pxSocket->xSendBlockTime; + + #if( ipconfigUSE_CALLBACKS != 0 ) + { + if( xIsCallingFromIPTask() != pdFALSE ) + { + /* If this send function is called from within a call-back + handler it may not block, otherwise chances would be big to + get a deadlock: the IP-task waiting for itself. */ + xTicksToWait = ( TickType_t )0; + } + } + #endif /* ipconfigUSE_CALLBACKS */ + + if( ( xFlags & FREERTOS_MSG_DONTWAIT ) != 0 ) + { + xTicksToWait = ( TickType_t ) 0; + } + + if( ( xFlags & FREERTOS_ZERO_COPY ) == 0 ) + { + /* Zero copy is not set, so obtain a network buffer into + which the payload will be copied. */ + vTaskSetTimeOutState( &xTimeOut ); + + /* Block until a buffer becomes available, or until a + timeout has been reached */ + pxNetworkBuffer = pxGetNetworkBufferWithDescriptor( xTotalDataLength + sizeof( UDPPacket_t ), xTicksToWait ); + + if( pxNetworkBuffer != NULL ) + { + memcpy( ( void * ) &( pxNetworkBuffer->pucEthernetBuffer[ ipUDP_PAYLOAD_OFFSET_IPv4 ] ), ( void * ) pvBuffer, xTotalDataLength ); + + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdTRUE ) + { + /* The entire block time has been used up. */ + xTicksToWait = ( TickType_t ) 0; + } + } + } + else + { + /* When zero copy is used, pvBuffer is a pointer to the + payload of a buffer that has already been obtained from the + stack. Obtain the network buffer pointer from the buffer. */ + pxNetworkBuffer = pxUDPPayloadBuffer_to_NetworkBuffer( (void*)pvBuffer ); + } + + if( pxNetworkBuffer != NULL ) + { + pxNetworkBuffer->xDataLength = xTotalDataLength; + pxNetworkBuffer->usPort = pxDestinationAddress->sin_port; + pxNetworkBuffer->usBoundPort = ( uint16_t ) socketGET_SOCKET_PORT( pxSocket ); + pxNetworkBuffer->ulIPAddress = pxDestinationAddress->sin_addr; + + /* The socket options are passed to the IP layer in the + space that will eventually get used by the Ethernet header. */ + pxNetworkBuffer->pucEthernetBuffer[ ipSOCKET_OPTIONS_OFFSET ] = pxSocket->ucSocketOptions; + + /* Tell the networking task that the packet needs sending. */ + xStackTxEvent.pvData = pxNetworkBuffer; + + /* Ask the IP-task to send this packet */ + if( xSendEventStructToIPTask( &xStackTxEvent, xTicksToWait ) == pdPASS ) + { + /* The packet was successfully sent to the IP task. */ + lReturn = ( int32_t ) xTotalDataLength; + #if( ipconfigUSE_CALLBACKS == 1 ) + { + if( ipconfigIS_VALID_PROG_ADDRESS( pxSocket->u.xUDP.pxHandleSent ) ) + { + pxSocket->u.xUDP.pxHandleSent( (Socket_t *)pxSocket, xTotalDataLength ); + } + } + #endif /* ipconfigUSE_CALLBACKS */ + } + else + { + /* If the buffer was allocated in this function, release + it. */ + if( ( xFlags & FREERTOS_ZERO_COPY ) == 0 ) + { + vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ); + } + iptraceSTACK_TX_EVENT_LOST( ipSTACK_TX_EVENT ); + } + } + else + { + /* If errno was available, errno would be set to + FREERTOS_ENOPKTS. As it is, the function must return the + number of transmitted bytes, so the calling function knows + how much data was actually sent. */ + iptraceNO_BUFFER_FOR_SENDTO(); + } + } + else + { + iptraceSENDTO_SOCKET_NOT_BOUND(); + } + } + else + { + /* The data is longer than the available buffer space. */ + iptraceSENDTO_DATA_TOO_LONG(); + } + + return lReturn; +} /* Tested */ +/*-----------------------------------------------------------*/ + +/* + * FreeRTOS_bind() : binds a sockt to a local port number. If port 0 is + * provided, a system provided port number will be assigned. This function can + * be used for both UDP and TCP sockets. The actual binding will be performed + * by the IP-task to avoid mutual access to the bound-socket-lists + * (xBoundUDPSocketsList or xBoundTCPSocketsList). + */ +BaseType_t FreeRTOS_bind( Socket_t xSocket, struct freertos_sockaddr * pxAddress, socklen_t xAddressLength ) +{ +IPStackEvent_t xBindEvent; +FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) xSocket; +BaseType_t xReturn = 0; + + ( void ) xAddressLength; + + if( ( pxSocket == NULL ) || ( pxSocket == FREERTOS_INVALID_SOCKET ) ) + { + xReturn = -pdFREERTOS_ERRNO_EINVAL; + } + /* Once a socket is bound to a port, it can not be bound to a different + port number */ + else if( socketSOCKET_IS_BOUND( pxSocket) != pdFALSE ) + { + /* The socket is already bound. */ + FreeRTOS_debug_printf( ( "vSocketBind: Socket already bound to %d\n", pxSocket->usLocalPort ) ); + xReturn = -pdFREERTOS_ERRNO_EINVAL; + } + else + { + /* Prepare a messages to the IP-task in order to perform the binding. + The desired port number will be passed in usLocalPort. */ + xBindEvent.eEventType = eSocketBindEvent; + xBindEvent.pvData = ( void * ) xSocket; + if( pxAddress != NULL ) + { + pxSocket->usLocalPort = FreeRTOS_ntohs( pxAddress->sin_port ); + } + else + { + /* Caller wants to bind to a random port number. */ + pxSocket->usLocalPort = 0u; + } + + /* portMAX_DELAY is used as a the time-out parameter, as binding *must* + succeed before the socket can be used. _RB_ The use of an infinite + block time needs be changed as it could result in the task hanging. */ + if( xSendEventStructToIPTask( &xBindEvent, ( TickType_t ) portMAX_DELAY ) == pdFAIL ) + { + /* Failed to wake-up the IP-task, no use to wait for it */ + FreeRTOS_debug_printf( ( "FreeRTOS_bind: send event failed\n" ) ); + xReturn = -pdFREERTOS_ERRNO_ECANCELED; + } + else + { + /* The IP-task will set the 'eSOCKET_BOUND' bit when it has done its + job. */ + xEventGroupWaitBits( pxSocket->xEventGroup, eSOCKET_BOUND, pdTRUE /*xClearOnExit*/, pdFALSE /*xWaitAllBits*/, portMAX_DELAY ); + if( socketSOCKET_IS_BOUND( pxSocket ) == pdFALSE ) + { + xReturn = -pdFREERTOS_ERRNO_EINVAL; + } + } + } + + return xReturn; +} + +/* + * vSocketBind(): internal version of bind() that should not be called directly. + * 'xInternal' is used for TCP sockets only: it allows to have several + * (connected) child sockets bound to the same server port. + */ +BaseType_t vSocketBind( FreeRTOS_Socket_t *pxSocket, struct freertos_sockaddr * pxAddress, size_t uxAddressLength, BaseType_t xInternal ) +{ +BaseType_t xReturn = 0; /* In Berkeley sockets, 0 means pass for bind(). */ +List_t *pxSocketList; +#if( ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND == 1 ) + struct freertos_sockaddr xAddress; +#endif /* ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND */ + +#if( ipconfigUSE_TCP == 1 ) + if( pxSocket->ucProtocol == ( uint8_t ) FREERTOS_IPPROTO_TCP ) + { + pxSocketList = &xBoundTCPSocketsList; + } + else +#endif /* ipconfigUSE_TCP == 1 */ + { + pxSocketList = &xBoundUDPSocketsList; + } + + /* The function prototype is designed to maintain the expected Berkeley + sockets standard, but this implementation does not use all the parameters. */ + ( void ) uxAddressLength; + + configASSERT( pxSocket ); + configASSERT( pxSocket != FREERTOS_INVALID_SOCKET ); + + #if( ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND == 1 ) + { + /* pxAddress will be NULL if sendto() was called on a socket without the + socket being bound to an address. In this case, automatically allocate + an address and port to the socket. */ + if( pxAddress == NULL ) + { + pxAddress = &xAddress; + /* Put the port to zero to be assigned later. */ + pxAddress->sin_port = 0u; + } + } + #endif /* ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND == 1 */ + + /* Sockets must be bound before calling FreeRTOS_sendto() if + ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND is not set to 1. */ + configASSERT( pxAddress ); + + if( pxAddress != NULL ) + { + if( pxAddress->sin_port == 0u ) + { + pxAddress->sin_port = prvGetPrivatePortNumber( ( BaseType_t )pxSocket->ucProtocol ); + if( 0 == pxAddress->sin_port ) + { + return -pdFREERTOS_ERRNO_EADDRNOTAVAIL; + } + } + + /* If vSocketBind() is called from the API FreeRTOS_bind() it has been + confirmed that the socket was not yet bound to a port. If it is called + from the IP-task, no such check is necessary. */ + + /* Check to ensure the port is not already in use. If the bind is + called internally, a port MAY be used by more than one socket. */ + if( ( ( xInternal == pdFALSE ) || ( pxSocket->ucProtocol != ( uint8_t ) FREERTOS_IPPROTO_TCP ) ) && + ( pxListFindListItemWithValue( pxSocketList, ( TickType_t ) pxAddress->sin_port ) != NULL ) ) + { + FreeRTOS_debug_printf( ( "vSocketBind: %sP port %d in use\n", + pxSocket->ucProtocol == ( uint8_t ) FREERTOS_IPPROTO_TCP ? "TC" : "UD", + FreeRTOS_ntohs( pxAddress->sin_port ) ) ); + xReturn = -pdFREERTOS_ERRNO_EADDRINUSE; + } + else + { + /* Allocate the port number to the socket. + This macro will set 'xBoundSocketListItem->xItemValue' */ + socketSET_SOCKET_PORT( pxSocket, pxAddress->sin_port ); + + /* And also store it in a socket field 'usLocalPort' in host-byte-order, + mostly used for logging and debugging purposes */ + pxSocket->usLocalPort = FreeRTOS_ntohs( pxAddress->sin_port ); + + /* Add the socket to the list of bound ports. */ + { + /* If the network driver can iterate through 'xBoundUDPSocketsList', + by calling xPortHasUDPSocket() then the IP-task must temporarily + suspend the scheduler to keep the list in a consistent state. */ + #if( ipconfigETHERNET_DRIVER_FILTERS_PACKETS == 1 ) + { + vTaskSuspendAll(); + } + #endif /* ipconfigETHERNET_DRIVER_FILTERS_PACKETS */ + + /* Add the socket to 'xBoundUDPSocketsList' or 'xBoundTCPSocketsList' */ + vListInsertEnd( pxSocketList, &( pxSocket->xBoundSocketListItem ) ); + + #if( ipconfigETHERNET_DRIVER_FILTERS_PACKETS == 1 ) + { + xTaskResumeAll(); + } + #endif /* ipconfigETHERNET_DRIVER_FILTERS_PACKETS */ + } + } + } + else + { + xReturn = -pdFREERTOS_ERRNO_EADDRNOTAVAIL; + FreeRTOS_debug_printf( ( "vSocketBind: Socket no addr\n" ) ); + } + + if( xReturn != 0 ) + { + iptraceBIND_FAILED( xSocket, ( FreeRTOS_ntohs( pxAddress->sin_port ) ) ); + } + + return xReturn; +} /* Tested */ +/*-----------------------------------------------------------*/ + +/* + * Close a socket and free the allocated space + * In case of a TCP socket: the connection will not be closed automatically + * Subsequent messages for the closed socket will be responded to with a RST + * The IP-task will actually close the socket, after receiving a 'eSocketCloseEvent' message + */ +BaseType_t FreeRTOS_closesocket( Socket_t xSocket ) +{ +BaseType_t xResult; +#if( ipconfigUSE_TCP == 1 ) && ( ipconfigUSE_CALLBACKS == 1 ) + FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * )xSocket; +#endif +IPStackEvent_t xCloseEvent; +xCloseEvent.eEventType = eSocketCloseEvent; +xCloseEvent.pvData = ( void * ) xSocket; + + if( ( xSocket == NULL ) || ( xSocket == FREERTOS_INVALID_SOCKET ) ) + { + xResult = 0; + } + else + { + #if( ( ipconfigUSE_TCP == 1 ) && ( ipconfigUSE_CALLBACKS == 1 ) ) + { + if( pxSocket->ucProtocol == ( uint8_t ) FREERTOS_IPPROTO_TCP ) + { + /* Make sure that IP-task won't call the user callback's anymore */ + pxSocket->u.xTCP.pxHandleConnected = NULL; + pxSocket->u.xTCP.pxHandleReceive = NULL; + pxSocket->u.xTCP.pxHandleSent = NULL; + } + } + #endif /* ( ( ipconfigUSE_TCP == 1 ) && ( ipconfigUSE_CALLBACKS == 1 ) ) */ + + /* Let the IP task close the socket to keep it synchronised with the + packet handling. */ + + /* Note when changing the time-out value below, it must be checked who is calling + this function. If it is called by the IP-task, a deadlock could occur. + The IP-task would only call it in case of a user call-back */ + if( xSendEventStructToIPTask( &xCloseEvent, ( TickType_t ) 0 ) == pdFAIL ) + { + FreeRTOS_debug_printf( ( "FreeRTOS_closesocket: failed\n" ) ); + xResult = -1; + } + else + { + xResult = 1; + } + } + + return xResult; +} + +/* This is the internal version of FreeRTOS_closesocket() + * It will be called by the IPtask only to avoid problems with synchronicity + */ +void *vSocketClose( FreeRTOS_Socket_t *pxSocket ) +{ +NetworkBufferDescriptor_t *pxNetworkBuffer; + + #if( ipconfigUSE_TCP == 1 ) + { + /* For TCP: clean up a little more. */ + if( pxSocket->ucProtocol == ( uint8_t ) FREERTOS_IPPROTO_TCP ) + { + #if( ipconfigUSE_TCP_WIN == 1 ) + { + if( pxSocket->u.xTCP.pxAckMessage != NULL ) + { + vReleaseNetworkBufferAndDescriptor( pxSocket->u.xTCP.pxAckMessage ); + } + /* Free the resources which were claimed by the tcpWin member */ + vTCPWindowDestroy( &pxSocket->u.xTCP.xTCPWindow ); + } + #endif /* ipconfigUSE_TCP_WIN */ + + /* Free the input and output streams */ + if( pxSocket->u.xTCP.rxStream != NULL ) + { + vPortFreeLarge( pxSocket->u.xTCP.rxStream ); + } + + if( pxSocket->u.xTCP.txStream != NULL ) + { + vPortFreeLarge( pxSocket->u.xTCP.txStream ); + } + + /* In case this is a child socket, make sure the child-count of the + parent socket is decreased. */ + prvTCPSetSocketCount( pxSocket ); + } + } + #endif /* ipconfigUSE_TCP == 1 */ + + /* Socket must be unbound first, to ensure no more packets are queued on + it. */ + if( socketSOCKET_IS_BOUND( pxSocket ) != pdFALSE ) + { + /* If the network driver can iterate through 'xBoundUDPSocketsList', + by calling xPortHasUDPSocket(), then the IP-task must temporarily + suspend the scheduler to keep the list in a consistent state. */ + #if( ipconfigETHERNET_DRIVER_FILTERS_PACKETS == 1 ) + { + vTaskSuspendAll(); + } + #endif /* ipconfigETHERNET_DRIVER_FILTERS_PACKETS */ + + uxListRemove( &( pxSocket->xBoundSocketListItem ) ); + + #if( ipconfigETHERNET_DRIVER_FILTERS_PACKETS == 1 ) + { + xTaskResumeAll(); + } + #endif /* ipconfigETHERNET_DRIVER_FILTERS_PACKETS */ + } + + /* Now the socket is not bound the list of waiting packets can be + drained. */ + if( pxSocket->ucProtocol == ( uint8_t ) FREERTOS_IPPROTO_UDP ) + { + while( listCURRENT_LIST_LENGTH( &( pxSocket->u.xUDP.xWaitingPacketsList ) ) > 0U ) + { + pxNetworkBuffer = ( NetworkBufferDescriptor_t * ) listGET_OWNER_OF_HEAD_ENTRY( &( pxSocket->u.xUDP.xWaitingPacketsList ) ); + uxListRemove( &( pxNetworkBuffer->xBufferListItem ) ); + vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ); + } + } + + if( pxSocket->xEventGroup ) + { + vEventGroupDelete( pxSocket->xEventGroup ); + } + + #if( ipconfigUSE_TCP == 1 ) && ( ipconfigHAS_DEBUG_PRINTF != 0 ) + { + if( pxSocket->ucProtocol == ( uint8_t ) FREERTOS_IPPROTO_TCP ) + { + FreeRTOS_debug_printf( ( "FreeRTOS_closesocket[%u to %lxip:%u]: buffers %lu socks %lu\n", + pxSocket->usLocalPort, + pxSocket->u.xTCP.ulRemoteIP, + pxSocket->u.xTCP.usRemotePort, + uxGetNumberOfFreeNetworkBuffers(), + listCURRENT_LIST_LENGTH( &xBoundTCPSocketsList ) ) ); + } + } + #endif /* ( ipconfigUSE_TCP == 1 ) && ( ipconfigHAS_DEBUG_PRINTF != 0 ) */ + + /* Anf finally, after all resources have been freed, free the socket space */ + vPortFreeSocket( pxSocket ); + + return 0; +} /* Tested */ + +/*-----------------------------------------------------------*/ + +#if ipconfigUSE_TCP == 1 + + /* + * When a child socket gets closed, make sure to update the child-count of the + * parent. When a listening parent socket is closed, make sure no child-sockets + * keep a pointer to it. + */ + static void prvTCPSetSocketCount( FreeRTOS_Socket_t *pxSocketToDelete ) + { + const ListItem_t *pxIterator; + const MiniListItem_t *pxEnd = ( const MiniListItem_t* )listGET_END_MARKER( &xBoundTCPSocketsList ); + FreeRTOS_Socket_t *pxOtherSocket; + uint16_t usLocalPort = pxSocketToDelete->usLocalPort; + + for( pxIterator = ( const ListItem_t * ) listGET_NEXT( pxEnd ); + pxIterator != ( const ListItem_t * ) pxEnd; + pxIterator = ( const ListItem_t * ) listGET_NEXT( pxIterator ) ) + { + pxOtherSocket = ( FreeRTOS_Socket_t * ) listGET_LIST_ITEM_OWNER( pxIterator ); + if( ( pxOtherSocket->u.xTCP.ucTCPState == eTCP_LISTEN ) && + ( pxOtherSocket->usLocalPort == usLocalPort ) && + ( pxOtherSocket->u.xTCP.usChildCount ) ) + { + pxOtherSocket->u.xTCP.usChildCount--; + FreeRTOS_debug_printf( ( "Lost: Socket %u now has %u / %u child%s\n", + pxOtherSocket->usLocalPort, + pxOtherSocket->u.xTCP.usChildCount, + pxOtherSocket->u.xTCP.usBacklog, + pxOtherSocket->u.xTCP.usChildCount == 1u ? "" : "ren" ) ); + break; + } + } + } + +#endif /* ipconfigUSE_TCP == 1 */ + +/*-----------------------------------------------------------*/ + +BaseType_t FreeRTOS_setsockopt( Socket_t xSocket, int32_t lLevel, int32_t lOptionName, const void *pvOptionValue, size_t xOptionLength ) +{ +/* The standard Berkeley function returns 0 for success. */ +BaseType_t xReturn = -pdFREERTOS_ERRNO_EINVAL; +BaseType_t lOptionValue; +FreeRTOS_Socket_t *pxSocket; + + pxSocket = ( FreeRTOS_Socket_t * ) xSocket; + + /* The function prototype is designed to maintain the expected Berkeley + sockets standard, but this implementation does not use all the parameters. */ + ( void ) lLevel; + ( void ) xOptionLength; + + configASSERT( xSocket ); + + switch( lOptionName ) + { + case FREERTOS_SO_RCVTIMEO : + /* Receive time out. */ + pxSocket->xReceiveBlockTime = *( ( TickType_t * ) pvOptionValue ); + xReturn = 0; + break; + + case FREERTOS_SO_SNDTIMEO : + pxSocket->xSendBlockTime = *( ( TickType_t * ) pvOptionValue ); + if( pxSocket->ucProtocol == ( uint8_t ) FREERTOS_IPPROTO_UDP ) + { + /* The send time out is capped for the reason stated in the + comments where ipconfigUDP_MAX_SEND_BLOCK_TIME_TICKS is defined + in FreeRTOSIPConfig.h (assuming an official configuration file + is being used. */ + if( pxSocket->xSendBlockTime > ipconfigUDP_MAX_SEND_BLOCK_TIME_TICKS ) + { + pxSocket->xSendBlockTime = ipconfigUDP_MAX_SEND_BLOCK_TIME_TICKS; + } + } + else + { + /* For TCP socket, it isn't necessary to limit the blocking time + because the FreeRTOS_send() function does not wait for a network + buffer to become available. */ + } + xReturn = 0; + break; + #if( ipconfigUDP_MAX_RX_PACKETS > 0 ) + case FREERTOS_SO_UDP_MAX_RX_PACKETS: + if( pxSocket->ucProtocol != ( uint8_t ) FREERTOS_IPPROTO_UDP ) + { + break; /* will return -pdFREERTOS_ERRNO_EINVAL */ + } + pxSocket->u.xUDP.uxMaxPackets = *( ( UBaseType_t * ) pvOptionValue ); + xReturn = 0; + break; + #endif /* ipconfigUDP_MAX_RX_PACKETS */ + + case FREERTOS_SO_UDPCKSUM_OUT : + /* Turn calculating of the UDP checksum on/off for this socket. */ + lOptionValue = ( BaseType_t ) pvOptionValue; + + if( lOptionValue == 0 ) + { + pxSocket->ucSocketOptions &= ( uint8_t ) ~FREERTOS_SO_UDPCKSUM_OUT; + } + else + { + pxSocket->ucSocketOptions |= ( uint8_t ) FREERTOS_SO_UDPCKSUM_OUT; + } + xReturn = 0; + break; + + #if( ipconfigUSE_CALLBACKS == 1 ) + #if( ipconfigUSE_TCP == 1 ) + case FREERTOS_SO_TCP_CONN_HANDLER: /* Set a callback for (dis)connection events */ + case FREERTOS_SO_TCP_RECV_HANDLER: /* Install a callback for receiving TCP data. Supply pointer to 'F_TCP_UDP_Handler_t' (see below) */ + case FREERTOS_SO_TCP_SENT_HANDLER: /* Install a callback for sending TCP data. Supply pointer to 'F_TCP_UDP_Handler_t' (see below) */ + #endif /* ipconfigUSE_TCP */ + case FREERTOS_SO_UDP_RECV_HANDLER: /* Install a callback for receiving UDP data. Supply pointer to 'F_TCP_UDP_Handler_t' (see below) */ + case FREERTOS_SO_UDP_SENT_HANDLER: /* Install a callback for sending UDP data. Supply pointer to 'F_TCP_UDP_Handler_t' (see below) */ + { + #if( ipconfigUSE_TCP == 1 ) + { + UBaseType_t uxProtocol; + if( ( lOptionName == FREERTOS_SO_UDP_RECV_HANDLER ) || + ( lOptionName == FREERTOS_SO_UDP_SENT_HANDLER ) ) + { + uxProtocol = ( UBaseType_t ) FREERTOS_IPPROTO_UDP; + } + else + { + uxProtocol = ( UBaseType_t ) FREERTOS_IPPROTO_TCP; + } + + if( pxSocket->ucProtocol != ( uint8_t ) uxProtocol ) + { + break; /* will return -pdFREERTOS_ERRNO_EINVAL */ + } + } + #else + { + /* No need to check if the socket has the right + protocol, because only UDP socket can be created. */ + } + #endif /* ipconfigUSE_TCP */ + + switch( lOptionName ) + { + #if ipconfigUSE_TCP == 1 + case FREERTOS_SO_TCP_CONN_HANDLER: + pxSocket->u.xTCP.pxHandleConnected = ((F_TCP_UDP_Handler_t *)pvOptionValue)->pxOnTCPConnected; + break; + case FREERTOS_SO_TCP_RECV_HANDLER: + pxSocket->u.xTCP.pxHandleReceive = ((F_TCP_UDP_Handler_t *)pvOptionValue)->pxOnTCPReceive; + break; + case FREERTOS_SO_TCP_SENT_HANDLER: + pxSocket->u.xTCP.pxHandleSent = ((F_TCP_UDP_Handler_t *)pvOptionValue)->pxOnTCPSent; + break; + #endif /* ipconfigUSE_TCP */ + case FREERTOS_SO_UDP_RECV_HANDLER: + pxSocket->u.xUDP.pxHandleReceive = ((F_TCP_UDP_Handler_t *)pvOptionValue)->pxOnUDPReceive; + break; + case FREERTOS_SO_UDP_SENT_HANDLER: + pxSocket->u.xUDP.pxHandleSent = ((F_TCP_UDP_Handler_t *)pvOptionValue)->pxOnUDPSent; + break; + default: + break; + } + } + + xReturn = 0; + break; + #endif /* ipconfigUSE_CALLBACKS */ + + #if( ipconfigUSE_TCP != 0 ) + #if( ipconfigSOCKET_HAS_USER_SEMAPHORE != 0 ) + /* Each socket has a semaphore on which the using task normally + sleeps. */ + case FREERTOS_SO_SET_SEMAPHORE: + { + pxSocket->pxUserSemaphore = *( ( SemaphoreHandle_t * ) pvOptionValue ); + xReturn = 0; + } + break; + #endif /* ipconfigSOCKET_HAS_USER_SEMAPHORE */ + + #if( ipconfigSOCKET_HAS_USER_WAKE_CALLBACK != 0 ) + case FREERTOS_SO_WAKEUP_CALLBACK: + { + /* Each socket can have a callback function that is executed + when there is an event the socket's owner might want to + process. */ + pxSocket->pxUserWakeCallback = ( SocketWakeupCallback_t ) pvOptionValue; + xReturn = 0; + } + break; + #endif /* ipconfigSOCKET_HAS_USER_WAKE_CALLBACK */ + + case FREERTOS_SO_SNDBUF: /* Set the size of the send buffer, in units of MSS (TCP only) */ + case FREERTOS_SO_RCVBUF: /* Set the size of the receive buffer, in units of MSS (TCP only) */ + { + uint32_t ulNewValue; + + if( pxSocket->ucProtocol != ( uint8_t ) FREERTOS_IPPROTO_TCP ) + { + FreeRTOS_debug_printf( ( "Set SO_%sBUF: wrong socket type\n", + ( lOptionName == FREERTOS_SO_SNDBUF ) ? "SND" : "RCV" ) ); + break; /* will return -pdFREERTOS_ERRNO_EINVAL */ + } + + if( ( ( lOptionName == FREERTOS_SO_SNDBUF ) && ( pxSocket->u.xTCP.txStream != NULL ) ) || + ( ( lOptionName == FREERTOS_SO_RCVBUF ) && ( pxSocket->u.xTCP.rxStream != NULL ) ) ) + { + FreeRTOS_debug_printf( ( "Set SO_%sBUF: buffer already created\n", + ( lOptionName == FREERTOS_SO_SNDBUF ) ? "SND" : "RCV" ) ); + break; /* will return -pdFREERTOS_ERRNO_EINVAL */ + } + + ulNewValue = *( ( uint32_t * ) pvOptionValue ); + + if( lOptionName == FREERTOS_SO_SNDBUF ) + { + /* Round up to nearest MSS size */ + ulNewValue = FreeRTOS_round_up( ulNewValue, ( uint32_t ) pxSocket->u.xTCP.usInitMSS ); + pxSocket->u.xTCP.uxTxStreamSize = ulNewValue; + } + else + { + pxSocket->u.xTCP.uxRxStreamSize = ulNewValue; + } + } + xReturn = 0; + break; + + case FREERTOS_SO_WIN_PROPERTIES: /* Set all buffer and window properties in one call, parameter is pointer to WinProperties_t */ + { + WinProperties_t* pxProps; + + if( pxSocket->ucProtocol != ( uint8_t ) FREERTOS_IPPROTO_TCP ) + { + FreeRTOS_debug_printf( ( "Set SO_WIN_PROP: wrong socket type\n" ) ); + break; /* will return -pdFREERTOS_ERRNO_EINVAL */ + } + + if( ( pxSocket->u.xTCP.txStream != NULL ) || ( pxSocket->u.xTCP.rxStream != NULL ) ) + { + FreeRTOS_debug_printf( ( "Set SO_WIN_PROP: buffer already created\n" ) ); + break; /* will return -pdFREERTOS_ERRNO_EINVAL */ + } + + pxProps = ( ( WinProperties_t * ) pvOptionValue ); + FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_SNDBUF, &( pxProps->lTxBufSize ), sizeof( pxProps->lTxBufSize ) ); + FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_RCVBUF, &( pxProps->lRxBufSize ), sizeof( pxProps->lRxBufSize ) ); + #if( ipconfigUSE_TCP_WIN == 1 ) + { + pxSocket->u.xTCP.uxRxWinSize = ( uint32_t )pxProps->lRxWinSize; /* Fixed value: size of the TCP reception window */ + pxSocket->u.xTCP.uxTxWinSize = ( uint32_t )pxProps->lTxWinSize; /* Fixed value: size of the TCP transmit window */ + } + #else + { + pxSocket->u.xTCP.uxRxWinSize = 1u; + pxSocket->u.xTCP.uxTxWinSize = 1u; + } + #endif + + /* In case the socket has already initialised its tcpWin, + adapt the window size parameters */ + if( pxSocket->u.xTCP.xTCPWindow.u.bits.bHasInit != pdFALSE_UNSIGNED ) + { + pxSocket->u.xTCP.xTCPWindow.xSize.ulRxWindowLength = pxSocket->u.xTCP.uxRxWinSize * pxSocket->u.xTCP.usInitMSS; + pxSocket->u.xTCP.xTCPWindow.xSize.ulTxWindowLength = pxSocket->u.xTCP.uxTxWinSize * pxSocket->u.xTCP.usInitMSS; + } + } + + xReturn = 0; + break; + + case FREERTOS_SO_REUSE_LISTEN_SOCKET: /* If true, the server-socket will turn into a connected socket */ + { + if( pxSocket->ucProtocol != ( uint8_t ) FREERTOS_IPPROTO_TCP ) + { + break; /* will return -pdFREERTOS_ERRNO_EINVAL */ + } + if( *( ( BaseType_t * ) pvOptionValue ) != 0 ) + { + pxSocket->u.xTCP.bits.bReuseSocket = pdTRUE_UNSIGNED; + } + else + { + pxSocket->u.xTCP.bits.bReuseSocket = pdFALSE_UNSIGNED; + } + } + xReturn = 0; + break; + + case FREERTOS_SO_CLOSE_AFTER_SEND: /* As soon as the last byte has been transmitted, finalise the connection */ + { + if( pxSocket->ucProtocol != ( uint8_t ) FREERTOS_IPPROTO_TCP ) + { + break; /* will return -pdFREERTOS_ERRNO_EINVAL */ + } + + if( *( ( BaseType_t * ) pvOptionValue ) != 0 ) + { + pxSocket->u.xTCP.bits.bCloseAfterSend = pdTRUE_UNSIGNED; + } + else + { + pxSocket->u.xTCP.bits.bCloseAfterSend = pdFALSE_UNSIGNED; + } + } + xReturn = 0; + break; + + case FREERTOS_SO_SET_FULL_SIZE: /* Refuse to send packets smaller than MSS */ + { + if( pxSocket->ucProtocol != ( uint8_t ) FREERTOS_IPPROTO_TCP ) + { + break; /* will return -pdFREERTOS_ERRNO_EINVAL */ + } + + if( *( ( BaseType_t * ) pvOptionValue ) != 0 ) + { + pxSocket->u.xTCP.xTCPWindow.u.bits.bSendFullSize = pdTRUE_UNSIGNED; + } + else + { + pxSocket->u.xTCP.xTCPWindow.u.bits.bSendFullSize = pdFALSE_UNSIGNED; + } + + if( ( pxSocket->u.xTCP.xTCPWindow.u.bits.bSendFullSize == pdFALSE_UNSIGNED ) && + ( pxSocket->u.xTCP.ucTCPState >= eESTABLISHED ) && + ( FreeRTOS_outstanding( pxSocket ) != 0 ) ) + { + pxSocket->u.xTCP.usTimeout = 1u; /* to set/clear bSendFullSize */ + xSendEventToIPTask( eTCPTimerEvent ); + } + } + xReturn = 0; + break; + + case FREERTOS_SO_STOP_RX: /* Refuse to receive more packts */ + { + if( pxSocket->ucProtocol != ( uint8_t ) FREERTOS_IPPROTO_TCP ) + { + break; /* will return -pdFREERTOS_ERRNO_EINVAL */ + } + + if( *( ( BaseType_t * ) pvOptionValue ) != 0 ) + { + pxSocket->u.xTCP.bits.bRxStopped = pdTRUE_UNSIGNED; + } + else + { + pxSocket->u.xTCP.bits.bRxStopped = pdFALSE_UNSIGNED; + } + + pxSocket->u.xTCP.bits.bWinChange = pdTRUE_UNSIGNED; + pxSocket->u.xTCP.usTimeout = 1u; /* to set/clear bRxStopped */ + xSendEventToIPTask( eTCPTimerEvent ); + } + xReturn = 0; + break; + + #endif /* ipconfigUSE_TCP == 1 */ + + default : + /* No other options are handled. */ + xReturn = -pdFREERTOS_ERRNO_ENOPROTOOPT; + break; + } + + return xReturn; +} /* Tested */ + +/*-----------------------------------------------------------*/ + +/* Find an available port number per https://tools.ietf.org/html/rfc6056. */ +static uint16_t prvGetPrivatePortNumber( BaseType_t xProtocol ) +{ +const uint16_t usEphemeralPortCount = + socketAUTO_PORT_ALLOCATION_MAX_NUMBER - socketAUTO_PORT_ALLOCATION_START_NUMBER + 1; +uint16_t usIterations = usEphemeralPortCount; +uint32_t ulRandomSeed = 0; +uint16_t usResult = 0; +BaseType_t xGotZeroOnce = pdFALSE; +const List_t *pxList; + +#if ipconfigUSE_TCP == 1 + if( xProtocol == ( BaseType_t ) FREERTOS_IPPROTO_TCP ) + { + pxList = &xBoundTCPSocketsList; + } + else +#endif + { + pxList = &xBoundUDPSocketsList; + } + + /* Avoid compiler warnings if ipconfigUSE_TCP is not defined. */ + ( void ) xProtocol; + + /* Find the next available port using the random seed as a starting + point. */ + do + { + /* Generate a random seed. */ + ulRandomSeed = ipconfigRAND32( ); + + /* Only proceed if the random number generator succeeded. */ + if( 0 == ulRandomSeed ) + { + if( pdFALSE == xGotZeroOnce ) + { + xGotZeroOnce = pdTRUE; + continue; + } + else + { + break; + } + } + + /* Map the random to a candidate port. */ + usResult = + socketAUTO_PORT_ALLOCATION_START_NUMBER + + ( ( ( uint16_t )ulRandomSeed ) % usEphemeralPortCount ); + + /* Check if there's already an open socket with the same protocol + and port. */ + if( NULL == pxListFindListItemWithValue( + pxList, + ( TickType_t )FreeRTOS_htons( usResult ) ) ) + { + usResult = FreeRTOS_htons( usResult ); + break; + } + else + { + usResult = 0; + } + + usIterations--; + } + while( usIterations > 0 ); + + return usResult; +} +/*-----------------------------------------------------------*/ + +/* pxListFindListItemWithValue: find a list item in a bound socket list +'xWantedItemValue' refers to a port number */ +static const ListItem_t * pxListFindListItemWithValue( const List_t *pxList, TickType_t xWantedItemValue ) +{ +const ListItem_t * pxResult = NULL; + + if( ( xIPIsNetworkTaskReady() != pdFALSE ) && ( pxList != NULL ) ) + { + const ListItem_t *pxIterator; + const MiniListItem_t *pxEnd = ( const MiniListItem_t* )listGET_END_MARKER( pxList ); + for( pxIterator = ( const ListItem_t * ) listGET_NEXT( pxEnd ); + pxIterator != ( const ListItem_t * ) pxEnd; + pxIterator = ( const ListItem_t * ) listGET_NEXT( pxIterator ) ) + { + if( listGET_LIST_ITEM_VALUE( pxIterator ) == xWantedItemValue ) + { + pxResult = pxIterator; + break; + } + } + } + + return pxResult; +} /* Tested */ + +/*-----------------------------------------------------------*/ + +FreeRTOS_Socket_t *pxUDPSocketLookup( UBaseType_t uxLocalPort ) +{ +const ListItem_t *pxListItem; +FreeRTOS_Socket_t *pxSocket = NULL; + + /* Looking up a socket is quite simple, find a match with the local port. + + See if there is a list item associated with the port number on the + list of bound sockets. */ + pxListItem = pxListFindListItemWithValue( &xBoundUDPSocketsList, ( TickType_t ) uxLocalPort ); + + if( pxListItem != NULL ) + { + /* The owner of the list item is the socket itself. */ + pxSocket = ( FreeRTOS_Socket_t * ) listGET_LIST_ITEM_OWNER( pxListItem ); + configASSERT( pxSocket != NULL ); + } + return pxSocket; +} + +/*-----------------------------------------------------------*/ + +#if ipconfigINCLUDE_FULL_INET_ADDR == 1 + + uint32_t FreeRTOS_inet_addr( const char * pcIPAddress ) + { + const uint32_t ulDecimalBase = 10u; + uint8_t ucOctet[ socketMAX_IP_ADDRESS_OCTETS ]; + const char *pcPointerOnEntering; + uint32_t ulReturn = 0UL, ulValue; + UBaseType_t uxOctetNumber; + BaseType_t xResult = pdPASS; + + for( uxOctetNumber = 0u; uxOctetNumber < socketMAX_IP_ADDRESS_OCTETS; uxOctetNumber++ ) + { + ulValue = 0ul; + pcPointerOnEntering = pcIPAddress; + + while( ( *pcIPAddress >= '0' ) && ( *pcIPAddress <= '9' ) ) + { + /* Move previous read characters into the next decimal + position. */ + ulValue *= ulDecimalBase; + + /* Add the binary value of the ascii character. */ + ulValue += ( ( uint32_t ) ( *pcIPAddress ) - ( uint32_t ) '0' ); + + /* Move to next character in the string. */ + pcIPAddress++; + } + + /* Check characters were read. */ + if( pcIPAddress == pcPointerOnEntering ) + { + xResult = pdFAIL; + } + + /* Check the value fits in an 8-bit number. */ + if( ulValue > 0xffUL ) + { + xResult = pdFAIL; + } + else + { + ucOctet[ uxOctetNumber ] = ( uint8_t ) ulValue; + + /* Check the next character is as expected. */ + if( uxOctetNumber < ( socketMAX_IP_ADDRESS_OCTETS - 1u ) ) + { + if( *pcIPAddress != '.' ) + { + xResult = pdFAIL; + } + else + { + /* Move past the dot. */ + pcIPAddress++; + } + } + } + + if( xResult == pdFAIL ) + { + /* No point going on. */ + break; + } + } + + if( *pcIPAddress != ( char ) 0 ) + { + /* Expected the end of the string. */ + xResult = pdFAIL; + } + + if( uxOctetNumber != socketMAX_IP_ADDRESS_OCTETS ) + { + /* Didn't read enough octets. */ + xResult = pdFAIL; + } + + if( xResult == pdPASS ) + { + ulReturn = FreeRTOS_inet_addr_quick( ucOctet[ 0 ], ucOctet[ 1 ], ucOctet[ 2 ], ucOctet[ 3 ] ); + } + + return ulReturn; + } + +#endif /* ipconfigINCLUDE_FULL_INET_ADDR */ + +/*-----------------------------------------------------------*/ + +/* Function to get the local address and IP port */ +size_t FreeRTOS_GetLocalAddress( Socket_t xSocket, struct freertos_sockaddr *pxAddress ) +{ +FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) xSocket; + + /* IP address of local machine. */ + pxAddress->sin_addr = *ipLOCAL_IP_ADDRESS_POINTER; + + /* Local port on this machine. */ + pxAddress->sin_port = FreeRTOS_htons( pxSocket->usLocalPort ); + + return sizeof( *pxAddress ); +} + +/*-----------------------------------------------------------*/ + +void vSocketWakeUpUser( FreeRTOS_Socket_t *pxSocket ) +{ +/* _HT_ must work this out, now vSocketWakeUpUser will be called for any important + * event or transition */ + #if( ipconfigSOCKET_HAS_USER_SEMAPHORE == 1 ) + { + if( pxSocket->pxUserSemaphore != NULL ) + { + xSemaphoreGive( pxSocket->pxUserSemaphore ); + } + } + #endif /* ipconfigSOCKET_HAS_USER_SEMAPHORE */ + + #if( ipconfigSOCKET_HAS_USER_WAKE_CALLBACK == 1 ) + { + if( pxSocket->pxUserWakeCallback != NULL ) + { + pxSocket->pxUserWakeCallback( pxSocket ); + } + } + #endif /* ipconfigSOCKET_HAS_USER_SEMAPHORE */ + + #if( ipconfigSUPPORT_SELECT_FUNCTION == 1 ) + { + if( pxSocket->pxSocketSet != NULL ) + { + EventBits_t xSelectBits = ( pxSocket->xEventBits >> SOCKET_EVENT_BIT_COUNT ) & eSELECT_ALL; + if( xSelectBits != 0ul ) + { + pxSocket->xSocketBits |= xSelectBits; + xEventGroupSetBits( pxSocket->pxSocketSet->xSelectGroup, xSelectBits ); + } + } + + pxSocket->xEventBits &= eSOCKET_ALL; + } + #endif /* ipconfigSUPPORT_SELECT_FUNCTION */ + + if( ( pxSocket->xEventGroup != NULL ) && ( pxSocket->xEventBits != 0u ) ) + { + xEventGroupSetBits( pxSocket->xEventGroup, pxSocket->xEventBits ); + } + + pxSocket->xEventBits = 0ul; +} + +/*-----------------------------------------------------------*/ + +#if( ipconfigETHERNET_DRIVER_FILTERS_PACKETS == 1 ) + + /* This define makes it possible for network-card drivers to inspect + * UDP message and see if there is any UDP socket bound to a given port + * number. + * This is probably only usefull in systems with a minimum of RAM and + * when lots of anonymous broadcast messages come in + */ + BaseType_t xPortHasUDPSocket( uint16_t usPortNr ) + { + BaseType_t xFound = pdFALSE; + + vTaskSuspendAll(); + { + if( ( pxListFindListItemWithValue( &xBoundUDPSocketsList, ( TickType_t ) usPortNr ) != NULL ) ) + { + xFound = pdTRUE; + } + } + xTaskResumeAll(); + + return xFound; + } + +#endif /* ipconfigETHERNET_DRIVER_FILTERS_PACKETS */ + +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP == 1 ) + + static BaseType_t bMayConnect( FreeRTOS_Socket_t *pxSocket ); + static BaseType_t bMayConnect( FreeRTOS_Socket_t *pxSocket ) + { + switch( pxSocket->u.xTCP.ucTCPState ) + { + case eCLOSED: + case eCLOSE_WAIT: return 0; + case eCONNECT_SYN: return -pdFREERTOS_ERRNO_EINPROGRESS; + default: return -pdFREERTOS_ERRNO_EAGAIN; + } + } + +#endif /* ipconfigUSE_TCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP == 1 ) + + static BaseType_t prvTCPConnectStart( FreeRTOS_Socket_t *pxSocket, struct freertos_sockaddr *pxAddress ) + { + BaseType_t xResult = 0; + + if( prvValidSocket( pxSocket, FREERTOS_IPPROTO_TCP, pdFALSE ) == pdFALSE ) + { + /* Not a valid socket or wrong type */ + xResult = -pdFREERTOS_ERRNO_EBADF; + } + else if( FreeRTOS_issocketconnected( pxSocket ) > 0 ) + { + /* The socket is already connected. */ + xResult = -pdFREERTOS_ERRNO_EISCONN; + } + else if( socketSOCKET_IS_BOUND( pxSocket ) == pdFALSE ) + { + /* Bind the socket to the port that the client task will send from. + Non-standard, so the error returned is that returned by bind(). */ + xResult = FreeRTOS_bind( ( Socket_t ) pxSocket, NULL, 0u ); + } + + if( xResult == 0 ) + { + /* Check if it makes any sense to wait for a connect event, this condition + might change while sleeping, so it must be checked within each loop */ + xResult = bMayConnect( pxSocket ); /* -EINPROGRESS, -EAGAIN, or 0 for OK */ + + /* Start the connect procedure, kernel will start working on it */ + if( xResult == 0 ) + { + pxSocket->u.xTCP.bits.bConnPrepared = pdFALSE_UNSIGNED; + pxSocket->u.xTCP.ucRepCount = 0u; + + FreeRTOS_debug_printf( ( "FreeRTOS_connect: %u to %lxip:%u\n", + pxSocket->usLocalPort, FreeRTOS_ntohl( pxAddress->sin_addr ), FreeRTOS_ntohs( pxAddress->sin_port ) ) ); + + /* Port on remote machine. */ + pxSocket->u.xTCP.usRemotePort = FreeRTOS_ntohs( pxAddress->sin_port ); + + /* IP address of remote machine. */ + pxSocket->u.xTCP.ulRemoteIP = FreeRTOS_ntohl( pxAddress->sin_addr ); + + /* (client) internal state: socket wants to send a connect. */ + vTCPStateChange( pxSocket, eCONNECT_SYN ); + + /* To start an active connect. */ + pxSocket->u.xTCP.usTimeout = 1u; + + if( xSendEventToIPTask( eTCPTimerEvent ) != pdPASS ) + { + xResult = -pdFREERTOS_ERRNO_ECANCELED; + } + } + } + + return xResult; + } + +#endif /* ipconfigUSE_TCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP == 1 ) + + /* + * FreeRTOS_connect: socket wants to connect to a remote port + */ + BaseType_t FreeRTOS_connect( Socket_t xClientSocket, struct freertos_sockaddr *pxAddress, socklen_t xAddressLength ) + { + FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t* ) xClientSocket; + TickType_t xRemainingTime; + BaseType_t xTimed = pdFALSE; + BaseType_t xResult; + TimeOut_t xTimeOut; + + ( void ) xAddressLength; + + xResult = prvTCPConnectStart( pxSocket, pxAddress ); + + if( xResult == 0 ) + { + /* And wait for the result */ + for( ;; ) + { + if( xTimed == pdFALSE ) + { + /* Only in the first round, check for non-blocking */ + xRemainingTime = pxSocket->xReceiveBlockTime; + if( xRemainingTime == ( TickType_t )0 ) + { + /* Not yet connected, correct state, non-blocking. */ + xResult = -pdFREERTOS_ERRNO_EWOULDBLOCK; + break; + } + + /* Don't get here a second time. */ + xTimed = pdTRUE; + + /* Fetch the current time */ + vTaskSetTimeOutState( &xTimeOut ); + } + + /* Did it get connected while sleeping ? */ + xResult = FreeRTOS_issocketconnected( pxSocket ); + + /* Returns positive when connected, negative means an error */ + if( xResult < 0 ) + { + /* Return the error */ + break; + } + + if( xResult > 0 ) + { + /* Socket now connected, return a zero */ + xResult = 0; + break; + } + + /* Is it allowed to sleep more? */ + if( xTaskCheckForTimeOut( &xTimeOut, &xRemainingTime ) ) + { + xResult = -pdFREERTOS_ERRNO_ETIMEDOUT; + break; + } + + /* Go sleeping until we get any down-stream event */ + xEventGroupWaitBits( pxSocket->xEventGroup, eSOCKET_CONNECT, pdTRUE /*xClearOnExit*/, pdFALSE /*xWaitAllBits*/, xRemainingTime ); + } + } + + return xResult; + } +#endif /* ipconfigUSE_TCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP == 1 ) + + /* + * FreeRTOS_accept: can return a new connected socket + * if the server socket is in listen mode and receives a connection request + * The new socket will be bound already to the same port number as the listing + * socket. + */ + Socket_t FreeRTOS_accept( Socket_t xServerSocket, struct freertos_sockaddr *pxAddress, socklen_t *pxAddressLength ) + { + FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) xServerSocket; + FreeRTOS_Socket_t *pxClientSocket = NULL; + TickType_t xRemainingTime; + BaseType_t xTimed = pdFALSE, xAsk = pdFALSE; + TimeOut_t xTimeOut; + IPStackEvent_t xAskEvent; + + if( prvValidSocket( pxSocket, FREERTOS_IPPROTO_TCP, pdTRUE ) == pdFALSE ) + { + /* Not a valid socket or wrong type */ + pxClientSocket = ( FreeRTOS_Socket_t * ) FREERTOS_INVALID_SOCKET; + } + else if( ( pxSocket->u.xTCP.bits.bReuseSocket == pdFALSE_UNSIGNED ) && + ( pxSocket->u.xTCP.ucTCPState != eTCP_LISTEN ) ) + { + /* Parent socket is not in listening mode */ + pxClientSocket = ( FreeRTOS_Socket_t * ) FREERTOS_INVALID_SOCKET; + } + else + { + /* Loop will stop with breaks. */ + for( ; ; ) + { + /* Is there a new client? */ + vTaskSuspendAll(); + { + if( pxSocket->u.xTCP.bits.bReuseSocket == pdFALSE_UNSIGNED ) + { + pxClientSocket = pxSocket->u.xTCP.pxPeerSocket; + } + else + { + pxClientSocket = pxSocket; + } + if( pxClientSocket != NULL ) + { + pxSocket->u.xTCP.pxPeerSocket = NULL; + + /* Is it still not taken ? */ + if( pxClientSocket->u.xTCP.bits.bPassAccept != pdFALSE_UNSIGNED ) + { + pxClientSocket->u.xTCP.bits.bPassAccept = pdFALSE_UNSIGNED; + } + else + { + pxClientSocket = NULL; + } + } + } + xTaskResumeAll(); + + if( pxClientSocket != NULL ) + { + if( pxAddress != NULL ) + { + /* IP address of remote machine. */ + pxAddress->sin_addr = FreeRTOS_ntohl( pxClientSocket->u.xTCP.ulRemoteIP ); + + /* Port on remote machine. */ + pxAddress->sin_port = FreeRTOS_ntohs( pxClientSocket->u.xTCP.usRemotePort ); + } + if( pxAddressLength != NULL ) + { + *pxAddressLength = sizeof( *pxAddress ); + } + + if( pxSocket->u.xTCP.bits.bReuseSocket == pdFALSE_UNSIGNED ) + { + xAsk = pdTRUE; + } + } + + if( xAsk != pdFALSE ) + { + /* Ask to set an event in 'xEventGroup' as soon as a new + client gets connected for this listening socket. */ + xAskEvent.eEventType = eTCPAcceptEvent; + xAskEvent.pvData = ( void * ) pxSocket; + xSendEventStructToIPTask( &xAskEvent, portMAX_DELAY ); + } + + if( pxClientSocket != NULL ) + { + break; + } + + if( xTimed == pdFALSE ) + { + /* Only in the first round, check for non-blocking */ + xRemainingTime = pxSocket->xReceiveBlockTime; + if( xRemainingTime == ( TickType_t ) 0 ) + { + break; + } + + /* Don't get here a second time */ + xTimed = pdTRUE; + + /* Fetch the current time */ + vTaskSetTimeOutState( &xTimeOut ); + } + + /* Has the timeout been reached? */ + if( xTaskCheckForTimeOut( &xTimeOut, &xRemainingTime ) != pdFALSE ) + { + break; + } + + /* Go sleeping until we get any down-stream event */ + xEventGroupWaitBits( pxSocket->xEventGroup, eSOCKET_ACCEPT, pdTRUE /*xClearOnExit*/, pdFALSE /*xWaitAllBits*/, xRemainingTime ); + } + } + + return ( Socket_t ) pxClientSocket; + } +#endif /* ipconfigUSE_TCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP == 1 ) + + /* + * Read incoming data from a TCP socket + * Only after the last byte has been read, a close error might be returned + */ + BaseType_t FreeRTOS_recv( Socket_t xSocket, void *pvBuffer, size_t xBufferLength, BaseType_t xFlags ) + { + BaseType_t xByteCount; + FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) xSocket; + TickType_t xRemainingTime; + BaseType_t xTimed = pdFALSE; + TimeOut_t xTimeOut; + EventBits_t xEventBits = ( EventBits_t ) 0; + + /* Check if the socket is valid, has type TCP and if it is bound to a + port. */ + if( prvValidSocket( pxSocket, FREERTOS_IPPROTO_TCP, pdTRUE ) == pdFALSE ) + { + xByteCount = -pdFREERTOS_ERRNO_EINVAL; + } + else + { + if( pxSocket->u.xTCP.rxStream != NULL ) + { + xByteCount = ( BaseType_t )uxStreamBufferGetSize ( pxSocket->u.xTCP.rxStream ); + } + else + { + xByteCount = 0; + } + + while( xByteCount == 0 ) + { + switch( pxSocket->u.xTCP.ucTCPState ) + { + case eCLOSED: + case eCLOSE_WAIT: /* (server + client) waiting for a connection termination request from the local user. */ + case eCLOSING: /* (server + client) waiting for a connection termination request acknowledgement from the remote TCP. */ + if( pxSocket->u.xTCP.bits.bMallocError != pdFALSE_UNSIGNED ) + { + /* The no-memory error has priority above the non-connected error. + Both are fatal and will elad to closing the socket. */ + xByteCount = -pdFREERTOS_ERRNO_ENOMEM; + } + else + { + xByteCount = -pdFREERTOS_ERRNO_ENOTCONN; + } + /* Call continue to break out of the switch and also the while + loop. */ + continue; + default: + break; + } + + if( xTimed == pdFALSE ) + { + /* Only in the first round, check for non-blocking. */ + xRemainingTime = pxSocket->xReceiveBlockTime; + + if( xRemainingTime == ( TickType_t ) 0 ) + { + #if( ipconfigSUPPORT_SIGNALS != 0 ) + { + /* Just check for the interrupt flag. */ + xEventBits = xEventGroupWaitBits( pxSocket->xEventGroup, eSOCKET_INTR, + pdTRUE /*xClearOnExit*/, pdFALSE /*xWaitAllBits*/, socketDONT_BLOCK ); + } + #endif /* ipconfigSUPPORT_SIGNALS */ + break; + } + + if( ( xFlags & FREERTOS_MSG_DONTWAIT ) != 0 ) + { + break; + } + + /* Don't get here a second time. */ + xTimed = pdTRUE; + + /* Fetch the current time. */ + vTaskSetTimeOutState( &xTimeOut ); + } + + /* Has the timeout been reached? */ + if( xTaskCheckForTimeOut( &xTimeOut, &xRemainingTime ) != pdFALSE ) + { + break; + } + + /* Block until there is a down-stream event. */ + xEventBits = xEventGroupWaitBits( pxSocket->xEventGroup, + eSOCKET_RECEIVE | eSOCKET_CLOSED | eSOCKET_INTR, + pdTRUE /*xClearOnExit*/, pdFALSE /*xWaitAllBits*/, xRemainingTime ); + #if( ipconfigSUPPORT_SIGNALS != 0 ) + { + if( ( xEventBits & eSOCKET_INTR ) != 0u ) + { + break; + } + } + #else + { + ( void ) xEventBits; + } + #endif /* ipconfigSUPPORT_SIGNALS */ + + if( pxSocket->u.xTCP.rxStream != NULL ) + { + xByteCount = ( BaseType_t ) uxStreamBufferGetSize ( pxSocket->u.xTCP.rxStream ); + } + else + { + xByteCount = 0; + } + } + + #if( ipconfigSUPPORT_SIGNALS != 0 ) + if( ( xEventBits & eSOCKET_INTR ) != 0 ) + { + if( ( xEventBits & ( eSOCKET_RECEIVE | eSOCKET_CLOSED ) ) != 0 ) + { + /* Shouldn't have cleared other flags. */ + xEventBits &= ~eSOCKET_INTR; + xEventGroupSetBits( pxSocket->xEventGroup, xEventBits ); + } + xByteCount = -pdFREERTOS_ERRNO_EINTR; + } + else + #endif /* ipconfigSUPPORT_SIGNALS */ + if( xByteCount > 0 ) + { + if( ( xFlags & FREERTOS_ZERO_COPY ) == 0 ) + { + xByteCount = ( BaseType_t ) uxStreamBufferGet( pxSocket->u.xTCP.rxStream, 0ul, ( uint8_t * ) pvBuffer, ( size_t ) xBufferLength, ( xFlags & FREERTOS_MSG_PEEK ) != 0 ); + if( pxSocket->u.xTCP.bits.bLowWater != pdFALSE_UNSIGNED ) + { + /* We had reached the low-water mark, now see if the flag + can be cleared */ + size_t uxFrontSpace = uxStreamBufferFrontSpace( pxSocket->u.xTCP.rxStream ); + + if( uxFrontSpace >= pxSocket->u.xTCP.uxEnoughSpace ) + { + pxSocket->u.xTCP.bits.bLowWater = pdFALSE_UNSIGNED; + pxSocket->u.xTCP.bits.bWinChange = pdTRUE_UNSIGNED; + pxSocket->u.xTCP.usTimeout = 1u; /* because bLowWater is cleared. */ + xSendEventToIPTask( eTCPTimerEvent ); + } + } + } + else + { + /* Zero-copy reception of data: pvBuffer is a pointer to a pointer. */ + xByteCount = ( BaseType_t ) uxStreamBufferGetPtr( pxSocket->u.xTCP.rxStream, (uint8_t **)pvBuffer ); + } + } + } /* prvValidSocket() */ + + return xByteCount; + } + +#endif /* ipconfigUSE_TCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP == 1 ) + + static int32_t prvTCPSendCheck( FreeRTOS_Socket_t *pxSocket, size_t xDataLength ) + { + int32_t xResult = 1; + + /* Is this a socket of type TCP and is it already bound to a port number ? */ + if( prvValidSocket( pxSocket, FREERTOS_IPPROTO_TCP, pdTRUE ) == pdFALSE ) + { + xResult = -pdFREERTOS_ERRNO_EINVAL; + } + else if( pxSocket->u.xTCP.bits.bMallocError != pdFALSE_UNSIGNED ) + { + xResult = -pdFREERTOS_ERRNO_ENOMEM; + } + else if( pxSocket->u.xTCP.ucTCPState == eCLOSED ) + { + xResult = -pdFREERTOS_ERRNO_ENOTCONN; + } + else if( pxSocket->u.xTCP.bits.bFinSent != pdFALSE_UNSIGNED ) + { + /* This TCP connection is closing already, the FIN flag has been sent. + Maybe it is still delivering or receiving data. + Return OK in order not to get closed/deleted too quickly */ + xResult = 0; + } + else if( xDataLength == 0ul ) + { + /* send() is being called to send zero bytes */ + xResult = 0; + } + else if( pxSocket->u.xTCP.txStream == NULL ) + { + /* Create the outgoing stream only when it is needed */ + prvTCPCreateStream( pxSocket, pdFALSE ); + + if( pxSocket->u.xTCP.txStream == NULL ) + { + xResult = -pdFREERTOS_ERRNO_ENOMEM; + } + } + + return xResult; + } + +#endif /* ipconfigUSE_TCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP == 1 ) + + /* Get a direct pointer to the circular transmit buffer. + '*pxLength' will contain the number of bytes that may be written. */ + uint8_t *FreeRTOS_get_tx_head( Socket_t xSocket, BaseType_t *pxLength ) + { + uint8_t *pucReturn; + FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) xSocket; + StreamBuffer_t *pxBuffer = pxSocket->u.xTCP.txStream; + + if( pxBuffer != NULL ) + { + BaseType_t xSpace = ( BaseType_t ) uxStreamBufferGetSpace( pxBuffer ); + BaseType_t xRemain = ( BaseType_t ) ( pxBuffer->LENGTH - pxBuffer->uxHead ); + + *pxLength = FreeRTOS_min_BaseType( xSpace, xRemain ); + pucReturn = pxBuffer->ucArray + pxBuffer->uxHead; + } + else + { + *pxLength = 0; + pucReturn = NULL; + } + + return pucReturn; + } +#endif /* ipconfigUSE_TCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP == 1 ) + /* + * Send data using a TCP socket. It is not necessary to have the socket + * connected already. Outgoing data will be stored and delivered as soon as + * the socket gets connected. + */ + BaseType_t FreeRTOS_send( Socket_t xSocket, const void *pvBuffer, size_t uxDataLength, BaseType_t xFlags ) + { + BaseType_t xByteCount; + BaseType_t xBytesLeft; + FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) xSocket; + TickType_t xRemainingTime; + BaseType_t xTimed = pdFALSE; + TimeOut_t xTimeOut; + BaseType_t xCloseAfterSend; + + /* Prevent compiler warnings about unused parameters. The parameter + may be used in future versions. */ + ( void ) xFlags; + + xByteCount = ( BaseType_t ) prvTCPSendCheck( pxSocket, uxDataLength ); + + if( xByteCount > 0 ) + { + /* xBytesLeft is number of bytes to send, will count to zero. */ + xBytesLeft = ( BaseType_t ) uxDataLength; + + /* xByteCount is number of bytes that can be sent now. */ + xByteCount = ( BaseType_t ) uxStreamBufferGetSpace( pxSocket->u.xTCP.txStream ); + + /* While there are still bytes to be sent. */ + while( xBytesLeft > 0 ) + { + /* If txStream has space. */ + if( xByteCount > 0 ) + { + /* Don't send more than necessary. */ + if( xByteCount > xBytesLeft ) + { + xByteCount = xBytesLeft; + } + + /* Is the close-after-send flag set and is this really the + last transmission? */ + if( ( pxSocket->u.xTCP.bits.bCloseAfterSend != pdFALSE_UNSIGNED ) && ( xByteCount == xBytesLeft ) ) + { + xCloseAfterSend = pdTRUE; + } + else + { + xCloseAfterSend = pdFALSE; + } + + /* The flag 'bCloseAfterSend' can be set before sending data + using setsockopt() + + When the last data packet is being sent out, a FIN flag will + be included to let the peer know that no more data is to be + expected. The use of 'bCloseAfterSend' is not mandatory, it + is just a faster way of transferring files (e.g. when using + FTP). */ + if( xCloseAfterSend != pdFALSE ) + { + /* Now suspend the scheduler: sending the last data and + setting bCloseRequested must be done together */ + vTaskSuspendAll(); + pxSocket->u.xTCP.bits.bCloseRequested = pdTRUE_UNSIGNED; + } + + xByteCount = ( BaseType_t ) uxStreamBufferAdd( pxSocket->u.xTCP.txStream, 0ul, ( const uint8_t * ) pvBuffer, ( size_t ) xByteCount ); + + if( xCloseAfterSend != pdFALSE ) + { + /* Now when the IP-task transmits the data, it will also + see that bCloseRequested is true and include the FIN + flag to start closure of the connection. */ + xTaskResumeAll(); + } + + /* Send a message to the IP-task so it can work on this + socket. Data is sent, let the IP-task work on it. */ + pxSocket->u.xTCP.usTimeout = 1u; + + if( xIsCallingFromIPTask() == pdFALSE ) + { + /* Only send a TCP timer event when not called from the + IP-task. */ + xSendEventToIPTask( eTCPTimerEvent ); + } + + xBytesLeft -= xByteCount; + + if( xBytesLeft == 0 ) + { + break; + } + + /* As there are still bytes left to be sent, increase the + data pointer. */ + pvBuffer = ( void * ) ( ( ( const uint8_t * ) pvBuffer) + xByteCount ); + } + + /* Not all bytes have been sent. In case the socket is marked as + blocking sleep for a while. */ + if( xTimed == pdFALSE ) + { + /* Only in the first round, check for non-blocking. */ + xRemainingTime = pxSocket->xSendBlockTime; + + #if( ipconfigUSE_CALLBACKS != 0 ) + { + if( xIsCallingFromIPTask() != pdFALSE ) + { + /* If this send function is called from within a + call-back handler it may not block, otherwise + chances would be big to get a deadlock: the IP-task + waiting for itself. */ + xRemainingTime = ( TickType_t ) 0; + } + } + #endif /* ipconfigUSE_CALLBACKS */ + + if( xRemainingTime == ( TickType_t ) 0 ) + { + break; + } + + if( ( xFlags & FREERTOS_MSG_DONTWAIT ) != 0 ) + { + break; + } + + /* Don't get here a second time. */ + xTimed = pdTRUE; + + /* Fetch the current time. */ + vTaskSetTimeOutState( &xTimeOut ); + } + else + { + /* Has the timeout been reached? */ + if( xTaskCheckForTimeOut( &xTimeOut, &xRemainingTime ) != pdFALSE ) + { + break; + } + } + + /* Go sleeping until down-stream events are received. */ + xEventGroupWaitBits( pxSocket->xEventGroup, eSOCKET_SEND | eSOCKET_CLOSED, + pdTRUE /*xClearOnExit*/, pdFALSE /*xWaitAllBits*/, xRemainingTime ); + + xByteCount = ( BaseType_t ) uxStreamBufferGetSpace( pxSocket->u.xTCP.txStream ); + } + + /* How much was actually sent? */ + xByteCount = ( ( BaseType_t ) uxDataLength ) - xBytesLeft; + + if( xByteCount == 0 ) + { + if( pxSocket->u.xTCP.ucTCPState > eESTABLISHED ) + { + xByteCount = ( BaseType_t ) -pdFREERTOS_ERRNO_ENOTCONN; + } + else + { + if( ipconfigTCP_MAY_LOG_PORT( pxSocket->usLocalPort ) != pdFALSE ) + { + FreeRTOS_debug_printf( ( "FreeRTOS_send: %u -> %lxip:%d: no space\n", + pxSocket->usLocalPort, + pxSocket->u.xTCP.ulRemoteIP, + pxSocket->u.xTCP.usRemotePort ) ); + } + + xByteCount = ( BaseType_t ) -pdFREERTOS_ERRNO_ENOSPC; + } + } + } + + return xByteCount; + } + +#endif /* ipconfigUSE_TCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP == 1 ) + + /* + * Request to put a socket in listen mode + */ + BaseType_t FreeRTOS_listen( Socket_t xSocket, BaseType_t xBacklog ) + { + FreeRTOS_Socket_t *pxSocket; + BaseType_t xResult = 0; + + pxSocket = ( FreeRTOS_Socket_t * ) xSocket; + + /* listen() is allowed for a valid TCP socket in Closed state and already + bound. */ + if( prvValidSocket( pxSocket, FREERTOS_IPPROTO_TCP, pdTRUE ) == pdFALSE ) + { + xResult = -pdFREERTOS_ERRNO_EOPNOTSUPP; + } + else if( ( pxSocket->u.xTCP.ucTCPState != eCLOSED ) && ( pxSocket->u.xTCP.ucTCPState != eCLOSE_WAIT ) ) + { + /* Socket is in a wrong state. */ + xResult = -pdFREERTOS_ERRNO_EOPNOTSUPP; + } + else + { + /* Backlog is interpreted here as "the maximum number of child + sockets. */ + pxSocket->u.xTCP.usBacklog = ( uint16_t )FreeRTOS_min_int32( ( int32_t ) 0xffff, ( int32_t ) xBacklog ); + + /* This cleaning is necessary only if a listening socket is being + reused as it might have had a previous connection. */ + if( pxSocket->u.xTCP.bits.bReuseSocket ) + { + if( pxSocket->u.xTCP.rxStream != NULL ) + { + vStreamBufferClear( pxSocket->u.xTCP.rxStream ); + } + + if( pxSocket->u.xTCP.txStream != NULL ) + { + vStreamBufferClear( pxSocket->u.xTCP.txStream ); + } + + memset( pxSocket->u.xTCP.xPacket.u.ucLastPacket, '\0', sizeof( pxSocket->u.xTCP.xPacket.u.ucLastPacket ) ); + memset( &pxSocket->u.xTCP.xTCPWindow, '\0', sizeof( pxSocket->u.xTCP.xTCPWindow ) ); + memset( &pxSocket->u.xTCP.bits, '\0', sizeof( pxSocket->u.xTCP.bits ) ); + + /* Now set the bReuseSocket flag again, because the bits have + just been cleared. */ + pxSocket->u.xTCP.bits.bReuseSocket = pdTRUE_UNSIGNED; + } + + vTCPStateChange( pxSocket, eTCP_LISTEN ); + } + + return xResult; + } + +#endif /* ipconfigUSE_TCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP == 1 ) + + /* shutdown - shut down part of a full-duplex connection */ + BaseType_t FreeRTOS_shutdown( Socket_t xSocket, BaseType_t xHow ) + { + FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) xSocket; + BaseType_t xResult; + + if( prvValidSocket( pxSocket, FREERTOS_IPPROTO_TCP, pdTRUE ) == pdFALSE ) + { + /*_RB_ Is this comment correct? The socket is not of a type that + supports the listen() operation. */ + xResult = -pdFREERTOS_ERRNO_EOPNOTSUPP; + } + else if ( pxSocket->u.xTCP.ucTCPState != eESTABLISHED ) + { + /*_RB_ Is this comment correct? The socket is not of a type that + supports the listen() operation. */ + xResult = -pdFREERTOS_ERRNO_EOPNOTSUPP; + } + else + { + pxSocket->u.xTCP.bits.bUserShutdown = pdTRUE_UNSIGNED; + + /* Let the IP-task perform the shutdown of the connection. */ + pxSocket->u.xTCP.usTimeout = 1u; + xSendEventToIPTask( eTCPTimerEvent ); + xResult = 0; + } + (void) xHow; + + return xResult; + } + +#endif /* ipconfigUSE_TCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP == 1 ) + + /* + * A TCP timer has expired, now check all TCP sockets for: + * - Active connect + * - Send a delayed ACK + * - Send new data + * - Send a keep-alive packet + * - Check for timeout (in non-connected states only) + */ + TickType_t xTCPTimerCheck( BaseType_t xWillSleep ) + { + FreeRTOS_Socket_t *pxSocket; + TickType_t xShortest = pdMS_TO_TICKS( ( TickType_t ) ipTCP_TIMER_PERIOD_MS ); + TickType_t xNow = xTaskGetTickCount(); + static TickType_t xLastTime = 0u; + TickType_t xDelta = xNow - xLastTime; + ListItem_t* pxEnd = ( ListItem_t * ) listGET_END_MARKER( &xBoundTCPSocketsList ); + ListItem_t *pxIterator = ( ListItem_t * ) listGET_HEAD_ENTRY( &xBoundTCPSocketsList ); + + xLastTime = xNow; + + if( xDelta == 0u ) + { + xDelta = 1u; + } + + while( pxIterator != pxEnd ) + { + pxSocket = ( FreeRTOS_Socket_t * )listGET_LIST_ITEM_OWNER( pxIterator ); + pxIterator = ( ListItem_t * ) listGET_NEXT( pxIterator ); + + /* Sockets with 'tmout == 0' do not need any regular attention. */ + if( pxSocket->u.xTCP.usTimeout == 0u ) + { + continue; + } + + if( xDelta < ( TickType_t ) pxSocket->u.xTCP.usTimeout ) + { + pxSocket->u.xTCP.usTimeout = ( uint16_t ) ( ( ( TickType_t ) pxSocket->u.xTCP.usTimeout ) - xDelta ); + } + else + { + int rc ; + pxSocket->u.xTCP.usTimeout = 0u; + rc = xTCPSocketCheck( pxSocket ); + + /* Within this function, the socket might want to send a delayed + ack or send out data or whatever it needs to do. */ + if( rc < 0 ) + { + /* Continue because the socket was deleted. */ + continue; + } + } + + /* In xEventBits the driver may indicate that the socket has + important events for the user. These are only done just before the + IP-task goes to sleep. */ + if( pxSocket->xEventBits != 0u ) + { + if( xWillSleep != pdFALSE ) + { + /* The IP-task is about to go to sleep, so messages can be + sent to the socket owners. */ + vSocketWakeUpUser( pxSocket ); + } + else + { + /* Or else make sure this will be called again to wake-up + the sockets' owner. */ + xShortest = ( TickType_t ) 0; + } + } + + if( ( pxSocket->u.xTCP.usTimeout != 0u ) && ( xShortest > ( TickType_t ) pxSocket->u.xTCP.usTimeout ) ) + { + xShortest = ( TickType_t ) pxSocket->u.xTCP.usTimeout; + } + } + + return xShortest; + } + +#endif /* ipconfigUSE_TCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP == 1 ) + + /* + * TCP: as multiple sockets may be bound to the same local port number + * looking up a socket is a little more complex: + * Both a local port, and a remote port and IP address are being used + * For a socket in listening mode, the remote port and IP address are both 0 + */ + FreeRTOS_Socket_t *pxTCPSocketLookup( uint32_t ulLocalIP, UBaseType_t uxLocalPort, uint32_t ulRemoteIP, UBaseType_t uxRemotePort ) + { + ListItem_t *pxIterator; + FreeRTOS_Socket_t *pxResult = NULL, *pxListenSocket = NULL; + MiniListItem_t *pxEnd = ( MiniListItem_t* )listGET_END_MARKER( &xBoundTCPSocketsList ); + + /* Parameter not yet supported. */ + ( void ) ulLocalIP; + + for( pxIterator = ( ListItem_t * ) listGET_NEXT( pxEnd ); + pxIterator != ( ListItem_t * ) pxEnd; + pxIterator = ( ListItem_t * ) listGET_NEXT( pxIterator ) ) + { + FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) listGET_LIST_ITEM_OWNER( pxIterator ); + + if( pxSocket->usLocalPort == ( uint16_t ) uxLocalPort ) + { + if( pxSocket->u.xTCP.ucTCPState == eTCP_LISTEN ) + { + /* If this is a socket listening to uxLocalPort, remember it + in case there is no perfect match. */ + pxListenSocket = pxSocket; + } + else if( ( pxSocket->u.xTCP.usRemotePort == ( uint16_t ) uxRemotePort ) && ( pxSocket->u.xTCP.ulRemoteIP == ulRemoteIP ) ) + { + /* For sockets not in listening mode, find a match with + xLocalPort, ulRemoteIP AND xRemotePort. */ + pxResult = pxSocket; + break; + } + } + } + if( pxResult == NULL ) + { + /* An exact match was not found, maybe a listening socket was + found. */ + pxResult = pxListenSocket; + } + + return pxResult; + } + +#endif /* ipconfigUSE_TCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP == 1 ) + + const struct xSTREAM_BUFFER *FreeRTOS_get_rx_buf( Socket_t xSocket ) + { + FreeRTOS_Socket_t *pxSocket = (FreeRTOS_Socket_t *)xSocket; + + return pxSocket->u.xTCP.rxStream; + } + +#endif /* ipconfigUSE_TCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP == 1 ) + + static StreamBuffer_t *prvTCPCreateStream ( FreeRTOS_Socket_t *pxSocket, BaseType_t xIsInputStream ) + { + StreamBuffer_t *pxBuffer; + size_t uxLength; + size_t uxSize; + + /* Now that a stream is created, the maximum size is fixed before + creation, it could still be changed with setsockopt(). */ + if( xIsInputStream != pdFALSE ) + { + uxLength = pxSocket->u.xTCP.uxRxStreamSize; + + if( pxSocket->u.xTCP.uxLittleSpace == 0ul ) + { + pxSocket->u.xTCP.uxLittleSpace = ( 1ul * pxSocket->u.xTCP.uxRxStreamSize ) / 5u; /*_RB_ Why divide by 5? Can this be changed to a #define? */ + } + + if( pxSocket->u.xTCP.uxEnoughSpace == 0ul ) + { + pxSocket->u.xTCP.uxEnoughSpace = ( 4ul * pxSocket->u.xTCP.uxRxStreamSize ) / 5u; /*_RB_ Why multiply by 4? Maybe sock80_PERCENT?*/ + } + } + else + { + uxLength = pxSocket->u.xTCP.uxTxStreamSize; + } + + /* Add an extra 4 (or 8) bytes. */ + uxLength += sizeof( size_t ); + + /* And make the length a multiple of sizeof( size_t ). */ + uxLength &= ~( sizeof( size_t ) - 1u ); + + uxSize = sizeof( *pxBuffer ) - sizeof( pxBuffer->ucArray ) + uxLength; + + pxBuffer = ( StreamBuffer_t * )pvPortMallocLarge( uxSize ); + + if( pxBuffer == NULL ) + { + FreeRTOS_debug_printf( ( "prvTCPCreateStream: malloc failed\n" ) ); + pxSocket->u.xTCP.bits.bMallocError = pdTRUE_UNSIGNED; + vTCPStateChange( pxSocket, eCLOSE_WAIT ); + } + else + { + /* Clear the markers of the stream */ + memset( pxBuffer, '\0', sizeof( *pxBuffer ) - sizeof( pxBuffer->ucArray ) ); + pxBuffer->LENGTH = ( size_t ) uxLength ; + + if( xTCPWindowLoggingLevel != 0 ) + { + FreeRTOS_debug_printf( ( "prvTCPCreateStream: %cxStream created %lu bytes (total %lu)\n", xIsInputStream ? 'R' : 'T', uxLength, uxSize ) ); + } + + if( xIsInputStream != 0 ) + { + pxSocket->u.xTCP.rxStream = pxBuffer; + } + else + { + pxSocket->u.xTCP.txStream = pxBuffer; + } + } + + return pxBuffer; + } + +#endif /* ipconfigUSE_TCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP == 1 ) + + /* + * Add data to the RxStream. When uxOffset > 0, data has come in out-of-order + * and will be put in front of the head so it can not be popped by the user. + */ + int32_t lTCPAddRxdata( FreeRTOS_Socket_t *pxSocket, size_t uxOffset, const uint8_t *pcData, uint32_t ulByteCount ) + { + StreamBuffer_t *pxStream = pxSocket->u.xTCP.rxStream; + int32_t xResult; + #if( ipconfigUSE_CALLBACKS == 1 ) + BaseType_t bHasHandler = ipconfigIS_VALID_PROG_ADDRESS( pxSocket->u.xTCP.pxHandleReceive ); + const uint8_t *pucBuffer = NULL; + #endif /* ipconfigUSE_CALLBACKS */ + + /* int32_t uxStreamBufferAdd( pxBuffer, uxOffset, pucData, aCount ) + if( pucData != NULL ) copy data the the buffer + if( pucData == NULL ) no copying, just advance rxHead + if( uxOffset != 0 ) Just store data which has come out-of-order + if( uxOffset == 0 ) Also advance rxHead */ + if( pxStream == NULL ) + { + pxStream = prvTCPCreateStream( pxSocket, pdTRUE ); + if( pxStream == NULL ) + { + return -1; + } + } + + #if( ipconfigUSE_CALLBACKS == 1 ) + { + if( ( bHasHandler != pdFALSE ) && ( uxStreamBufferGetSize( pxStream ) == 0u ) && ( uxOffset == 0ul ) && ( pcData != NULL ) ) + { + /* Data can be passed directly to the user */ + pucBuffer = pcData; + + /* Zero-copy for call-back: no need to add the bytes to the + stream, only the pointer will be advanced by uxStreamBufferAdd(). */ + pcData = NULL; + } + } + #endif /* ipconfigUSE_CALLBACKS */ + + xResult = ( int32_t ) uxStreamBufferAdd( pxStream, uxOffset, pcData, ( size_t ) ulByteCount ); + + #if( ipconfigHAS_DEBUG_PRINTF != 0 ) + { + if( xResult != ( int32_t ) ulByteCount ) + { + FreeRTOS_debug_printf( ( "lTCPAddRxdata: at %ld: %ld/%lu bytes (tail %lu head %lu space %lu front %lu)\n", + uxOffset, xResult, ulByteCount, + pxStream->uxTail, + pxStream->uxHead, + uxStreamBufferFrontSpace( pxStream ), + pxStream->uxFront ) ); + } + } + #endif /* ipconfigHAS_DEBUG_PRINTF */ + + if( uxOffset == 0u ) + { + /* Data is being added to rxStream at the head (offs = 0) */ + #if( ipconfigUSE_CALLBACKS == 1 ) + if( bHasHandler != pdFALSE ) + { + /* The socket owner has installed an OnReceive handler. Pass the + Rx data, without copying from the rxStream, to the user. */ + for (;;) + { + uint8_t *ucReadPtr = NULL; + uint32_t ulCount; + if( pucBuffer != NULL ) + { + ucReadPtr = ( uint8_t * )pucBuffer; + ulCount = ulByteCount; + pucBuffer = NULL; + } + else + { + ulCount = ( uint32_t ) uxStreamBufferGetPtr( pxStream, &( ucReadPtr ) ); + } + + if( ulCount == 0ul ) + { + break; + } + + pxSocket->u.xTCP.pxHandleReceive( (Socket_t *)pxSocket, ( void* )ucReadPtr, ( size_t ) ulCount ); + uxStreamBufferGet( pxStream, 0ul, NULL, ( size_t ) ulCount, pdFALSE ); + } + } else + #endif /* ipconfigUSE_CALLBACKS */ + { + /* See if running out of space. */ + if( pxSocket->u.xTCP.bits.bLowWater == pdFALSE_UNSIGNED ) + { + size_t uxFrontSpace = uxStreamBufferFrontSpace( pxSocket->u.xTCP.rxStream ); + if( uxFrontSpace <= pxSocket->u.xTCP.uxLittleSpace ) + { + pxSocket->u.xTCP.bits.bLowWater = pdTRUE_UNSIGNED; + pxSocket->u.xTCP.bits.bWinChange = pdTRUE_UNSIGNED; + + /* bLowWater was reached, send the changed window size. */ + pxSocket->u.xTCP.usTimeout = 1u; + xSendEventToIPTask( eTCPTimerEvent ); + } + } + + /* New incoming data is available, wake up the user. User's + semaphores will be set just before the IP-task goes asleep. */ + pxSocket->xEventBits |= eSOCKET_RECEIVE; + + #if ipconfigSUPPORT_SELECT_FUNCTION == 1 + { + if( ( pxSocket->xSelectBits & eSELECT_READ ) != 0 ) + { + pxSocket->xEventBits |= ( eSELECT_READ << SOCKET_EVENT_BIT_COUNT ); + } + } + #endif + } + } + + return xResult; + } + +#endif /* ipconfigUSE_TCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP == 1 ) + + /* Function to get the remote address and IP port */ + BaseType_t FreeRTOS_GetRemoteAddress( Socket_t xSocket, struct freertos_sockaddr *pxAddress ) + { + FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) xSocket; + BaseType_t xResult; + + if( pxSocket->ucProtocol != ( uint8_t ) FREERTOS_IPPROTO_TCP ) + { + xResult = -pdFREERTOS_ERRNO_EINVAL; + } + else + { + /* BSD style sockets communicate IP and port addresses in network + byte order. + + IP address of remote machine. */ + pxAddress->sin_addr = FreeRTOS_htonl ( pxSocket->u.xTCP.ulRemoteIP ); + + /* Port on remote machine. */ + pxAddress->sin_port = FreeRTOS_htons ( pxSocket->u.xTCP.usRemotePort ); + + xResult = ( BaseType_t ) sizeof( ( *pxAddress ) ); + } + + return xResult; + } + +#endif /* ipconfigUSE_TCP */ + +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP == 1 ) + + /* Returns the number of bytes that may be added to txStream */ + BaseType_t FreeRTOS_maywrite( Socket_t xSocket ) + { + FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) xSocket; + BaseType_t xResult; + + if( pxSocket->ucProtocol != ( uint8_t ) FREERTOS_IPPROTO_TCP ) + { + xResult = -pdFREERTOS_ERRNO_EINVAL; + } + else if( pxSocket->u.xTCP.ucTCPState != eESTABLISHED ) + { + if( ( pxSocket->u.xTCP.ucTCPState < eCONNECT_SYN ) || ( pxSocket->u.xTCP.ucTCPState > eESTABLISHED ) ) + { + xResult = -1; + } + else + { + xResult = 0; + } + } + else if( pxSocket->u.xTCP.txStream == NULL ) + { + xResult = ( BaseType_t ) pxSocket->u.xTCP.uxTxStreamSize; + } + else + { + xResult = ( BaseType_t ) uxStreamBufferGetSpace( pxSocket->u.xTCP.txStream ); + } + + return xResult; + } + +#endif /* ipconfigUSE_TCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP ==1 ) + + BaseType_t FreeRTOS_tx_space( Socket_t xSocket ) + { + FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) xSocket; + BaseType_t xReturn; + + if( pxSocket->ucProtocol != ( uint8_t ) FREERTOS_IPPROTO_TCP ) + { + xReturn = -pdFREERTOS_ERRNO_EINVAL; + } + else + { + if( pxSocket->u.xTCP.txStream != NULL ) + { + xReturn = ( BaseType_t ) uxStreamBufferGetSpace ( pxSocket->u.xTCP.txStream ); + } + else + { + xReturn = ( BaseType_t ) pxSocket->u.xTCP.uxTxStreamSize; + } + } + + return xReturn; + } + +#endif /* ipconfigUSE_TCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP == 1 ) + + BaseType_t FreeRTOS_tx_size( Socket_t xSocket ) + { + FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) xSocket; + BaseType_t xReturn; + + if( pxSocket->ucProtocol != ( uint8_t ) FREERTOS_IPPROTO_TCP ) + { + xReturn = -pdFREERTOS_ERRNO_EINVAL; + } + else + { + if( pxSocket->u.xTCP.txStream != NULL ) + { + xReturn = ( BaseType_t ) uxStreamBufferGetSize ( pxSocket->u.xTCP.txStream ); + } + else + { + xReturn = 0; + } + } + + return xReturn; + } + +#endif /* ipconfigUSE_TCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP == 1 ) + + /* Returns pdTRUE if TCP socket is connected. */ + BaseType_t FreeRTOS_issocketconnected( Socket_t xSocket ) + { + FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) xSocket; + BaseType_t xReturn = pdFALSE; + + if( pxSocket->ucProtocol != ( uint8_t ) FREERTOS_IPPROTO_TCP ) + { + xReturn = -pdFREERTOS_ERRNO_EINVAL; + } + else + { + if( pxSocket->u.xTCP.ucTCPState >= eESTABLISHED ) + { + if( pxSocket->u.xTCP.ucTCPState < eCLOSE_WAIT ) + { + xReturn = pdTRUE; + } + } + } + + return xReturn; + } + +#endif /* ipconfigUSE_TCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP == 1 ) + + /* returns the actual size of MSS being used */ + BaseType_t FreeRTOS_mss( Socket_t xSocket ) + { + FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) xSocket; + BaseType_t xReturn; + + if( pxSocket->ucProtocol != ( uint8_t ) FREERTOS_IPPROTO_TCP ) + { + xReturn = -pdFREERTOS_ERRNO_EINVAL; + } + else + { + /* usCurMSS is declared as uint16_t to save space. FreeRTOS_mss() + will often be used in signed native-size expressions cast it to + BaseType_t. */ + xReturn = ( BaseType_t ) ( pxSocket->u.xTCP.usCurMSS ); + } + + return xReturn; + } + +#endif /* ipconfigUSE_TCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP == 1 ) + + /* HT: for internal use only: return the connection status */ + BaseType_t FreeRTOS_connstatus( Socket_t xSocket ) + { + FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) xSocket; + BaseType_t xReturn; + + if( pxSocket->ucProtocol != ( uint8_t ) FREERTOS_IPPROTO_TCP ) + { + xReturn = -pdFREERTOS_ERRNO_EINVAL; + } + else + { + /* Cast it to BaseType_t */ + xReturn = ( BaseType_t ) ( pxSocket->u.xTCP.ucTCPState ); + } + + return xReturn; + } + +#endif /* ipconfigUSE_TCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP == 1 ) + + /* + * Returns the number of bytes which can be read. + */ + BaseType_t FreeRTOS_rx_size( Socket_t xSocket ) + { + FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) xSocket; + BaseType_t xReturn; + + if( pxSocket->ucProtocol != ( uint8_t ) FREERTOS_IPPROTO_TCP ) + { + xReturn = -pdFREERTOS_ERRNO_EINVAL; + } + else if( pxSocket->u.xTCP.rxStream != NULL ) + { + xReturn = ( BaseType_t ) uxStreamBufferGetSize( pxSocket->u.xTCP.rxStream ); + } + else + { + xReturn = 0; + } + + return xReturn; + } + +#endif /* ipconfigUSE_TCP */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP == 1 ) + + void FreeRTOS_netstat( void ) + { + IPStackEvent_t xAskEvent; + + /* Ask the IP-task to call vTCPNetStat() + * to avoid accessing xBoundTCPSocketsList + */ + xAskEvent.eEventType = eTCPNetStat; + xAskEvent.pvData = ( void * ) NULL; + xSendEventStructToIPTask( &xAskEvent, 1000u ); + } + +#endif /* ipconfigUSE_TCP */ +/*-----------------------------------------------------------*/ + +#if( ( ipconfigHAS_PRINTF != 0 ) && ( ipconfigUSE_TCP == 1 ) ) + + void vTCPNetStat( void ) + { + /* Show a simple listing of all created sockets and their connections */ + ListItem_t *pxIterator; + BaseType_t count = 0; + + if( listLIST_IS_INITIALISED( &xBoundTCPSocketsList ) == pdFALSE ) + { + FreeRTOS_printf( ( "PLUS-TCP not initialized\n" ) ); + } + else + { + FreeRTOS_printf( ( "Prot Port IP-Remote : Port R/T Status Alive tmout Child\n" ) ); + for( pxIterator = ( ListItem_t * ) listGET_HEAD_ENTRY( &xBoundTCPSocketsList ); + pxIterator != ( ListItem_t * ) listGET_END_MARKER( &xBoundTCPSocketsList ); + pxIterator = ( ListItem_t * ) listGET_NEXT( pxIterator ) ) + { + FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) listGET_LIST_ITEM_OWNER( pxIterator ); + #if( ipconfigTCP_KEEP_ALIVE == 1 ) + TickType_t age = xTaskGetTickCount() - pxSocket->u.xTCP.xLastAliveTime; + #else + TickType_t age = 0u; + #endif + #if( ipconfigUSE_CALLBACKS == 1 ) + void *pxHandleReceive = (void*)pxSocket->u.xTCP.pxHandleReceive; + #else + void *pxHandleReceive = (void*)NULL; + #endif + char ucChildText[16] = ""; + if (pxSocket->u.xTCP.ucTCPState == eTCP_LISTEN) + { + const int32_t copied_len = snprintf( ucChildText, sizeof( ucChildText ), " %d/%d", + ( int ) pxSocket->u.xTCP.usChildCount, + ( int ) pxSocket->u.xTCP.usBacklog); + /* These should never evaluate to false since the buffers are both shorter than 5-6 characters (<=65535) */ + configASSERT( copied_len >= 0 ); + configASSERT( copied_len < sizeof( ucChildText ) ); + } + FreeRTOS_printf( ( "TCP %5d %-16lxip:%5d %d/%d %-13.13s %6lu %6u%s\n", + pxSocket->usLocalPort, /* Local port on this machine */ + pxSocket->u.xTCP.ulRemoteIP, /* IP address of remote machine */ + pxSocket->u.xTCP.usRemotePort, /* Port on remote machine */ + pxSocket->u.xTCP.rxStream != NULL, + pxSocket->u.xTCP.txStream != NULL, + FreeRTOS_GetTCPStateName( pxSocket->u.xTCP.ucTCPState ), + (age > 999999 ? 999999 : age), /* Format 'age' for printing */ + pxSocket->u.xTCP.usTimeout, + ucChildText ) ); + /* Remove compiler warnings if FreeRTOS_debug_printf() is not defined. */ + ( void ) pxHandleReceive; + count++; + } + + for( pxIterator = ( ListItem_t * ) listGET_HEAD_ENTRY( &xBoundUDPSocketsList ); + pxIterator != ( ListItem_t * ) listGET_END_MARKER( &xBoundUDPSocketsList ); + pxIterator = ( ListItem_t * ) listGET_NEXT( pxIterator ) ) + { + /* Local port on this machine */ + FreeRTOS_printf( ( "UDP Port %5u\n", + FreeRTOS_ntohs( listGET_LIST_ITEM_VALUE( pxIterator ) ) ) ); + count++; + } + + FreeRTOS_printf( ( "FreeRTOS_netstat: %lu sockets %lu < %lu < %d buffers free\n", + count, + uxGetMinimumFreeNetworkBuffers( ), + uxGetNumberOfFreeNetworkBuffers( ), + ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ) ); + } + } + +#endif /* ( ( ipconfigHAS_PRINTF != 0 ) && ( ipconfigUSE_TCP == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if( ipconfigSUPPORT_SELECT_FUNCTION == 1 ) + + void vSocketSelect( SocketSelect_t *pxSocketSet ) + { + BaseType_t xRound; + EventBits_t xSocketBits, xBitsToClear; + #if ipconfigUSE_TCP == 1 + BaseType_t xLastRound = 1; + #else + BaseType_t xLastRound = 0; + #endif + + /* These flags will be switched on after checking the socket status. */ + EventBits_t xGroupBits = 0; + pxSocketSet->pxSocket = NULL; + + for( xRound = 0; xRound <= xLastRound; xRound++ ) + { + const ListItem_t *pxIterator; + const MiniListItem_t *pxEnd; + if( xRound == 0 ) + { + pxEnd = ( const MiniListItem_t* )listGET_END_MARKER( &xBoundUDPSocketsList ); + } + #if ipconfigUSE_TCP == 1 + else + { + pxEnd = ( const MiniListItem_t* )listGET_END_MARKER( &xBoundTCPSocketsList ); + } + #endif /* ipconfigUSE_TCP == 1 */ + for( pxIterator = ( const ListItem_t * ) ( listGET_NEXT( pxEnd ) ); + pxIterator != ( const ListItem_t * ) pxEnd; + pxIterator = ( const ListItem_t * ) listGET_NEXT( pxIterator ) ) + { + FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) listGET_LIST_ITEM_OWNER( pxIterator ); + if( pxSocket->pxSocketSet != pxSocketSet ) + { + /* Socket does not belong to this select group. */ + continue; + } + xSocketBits = 0; + + #if( ipconfigUSE_TCP == 1 ) + if( pxSocket->ucProtocol == FREERTOS_IPPROTO_TCP ) + { + /* Check if the socket has already been accepted by the + owner. If not, it is useless to return it from a + select(). */ + BaseType_t bAccepted = pdFALSE; + + if( pxSocket->u.xTCP.bits.bPassQueued == pdFALSE_UNSIGNED ) + { + if( pxSocket->u.xTCP.bits.bPassAccept == pdFALSE_UNSIGNED ) + { + bAccepted = pdTRUE; + } + } + + /* Is the set owner interested in READ events? */ + if( ( pxSocket->xSelectBits & eSELECT_READ ) != 0 ) + { + if( pxSocket->u.xTCP.ucTCPState == eTCP_LISTEN ) + { + if( ( pxSocket->u.xTCP.pxPeerSocket != NULL ) && ( pxSocket->u.xTCP.pxPeerSocket->u.xTCP.bits.bPassAccept != 0 ) ) + { + xSocketBits |= eSELECT_READ; + } + } + else if( ( pxSocket->u.xTCP.bits.bReuseSocket != pdFALSE_UNSIGNED ) && ( pxSocket->u.xTCP.bits.bPassAccept != pdFALSE_UNSIGNED ) ) + { + /* This socket has the re-use flag. After connecting it turns into + aconnected socket. Set the READ event, so that accept() will be called. */ + xSocketBits |= eSELECT_READ; + } + else if( ( bAccepted != 0 ) && ( FreeRTOS_recvcount( pxSocket ) > 0 ) ) + { + xSocketBits |= eSELECT_READ; + } + } + /* Is the set owner interested in EXCEPTION events? */ + if( ( pxSocket->xSelectBits & eSELECT_EXCEPT ) != 0 ) + { + if( ( pxSocket->u.xTCP.ucTCPState == eCLOSE_WAIT ) || ( pxSocket->u.xTCP.ucTCPState == eCLOSED ) ) + { + xSocketBits |= eSELECT_EXCEPT; + } + } + + /* Is the set owner interested in WRITE events? */ + if( ( pxSocket->xSelectBits & eSELECT_WRITE ) != 0 ) + { + BaseType_t bMatch = pdFALSE; + + if( bAccepted != 0 ) + { + if( FreeRTOS_tx_space( pxSocket ) > 0 ) + { + bMatch = pdTRUE; + } + } + + if( bMatch == pdFALSE ) + { + if( ( pxSocket->u.xTCP.bits.bConnPrepared != pdFALSE_UNSIGNED ) && + ( pxSocket->u.xTCP.ucTCPState >= eESTABLISHED ) && + ( pxSocket->u.xTCP.bits.bConnPassed == pdFALSE_UNSIGNED ) ) + { + pxSocket->u.xTCP.bits.bConnPassed = pdTRUE_UNSIGNED; + bMatch = pdTRUE; + } + } + + if( bMatch != pdFALSE ) + { + xSocketBits |= eSELECT_WRITE; + } + } + } + else + #endif /* ipconfigUSE_TCP == 1 */ + { + /* Select events for UDP are simpler. */ + if( ( ( pxSocket->xSelectBits & eSELECT_READ ) != 0 ) && + ( listCURRENT_LIST_LENGTH( &( pxSocket->u.xUDP.xWaitingPacketsList ) ) > 0U ) ) + { + xSocketBits |= eSELECT_READ; + } + /* The WRITE and EXCEPT bits are not used for UDP */ + } /* if( pxSocket->ucProtocol == FREERTOS_IPPROTO_TCP ) */ + + /* Each socket keeps its own event flags, which are looked-up + by FreeRTOS_FD_ISSSET() */ + pxSocket->xSocketBits = xSocketBits; + + /* The ORed value will be used to set the bits in the event + group. */ + xGroupBits |= xSocketBits; + + } /* for( pxIterator ... ) */ + } /* for( xRound = 0; xRound <= xLastRound; xRound++ ) */ + + xBitsToClear = xEventGroupGetBits( pxSocketSet->xSelectGroup ); + + /* Now set the necessary bits. */ + xBitsToClear = ( xBitsToClear & ~xGroupBits ) & eSELECT_ALL; + + #if( ipconfigSUPPORT_SIGNALS != 0 ) + { + /* Maybe the socketset was signalled, but don't + clear the 'eSELECT_INTR' bit here, as it will be used + and cleared in FreeRTOS_select(). */ + xBitsToClear &= ( EventBits_t ) ~eSELECT_INTR; + } + #endif /* ipconfigSUPPORT_SIGNALS */ + + if( xBitsToClear != 0 ) + { + xEventGroupClearBits( pxSocketSet->xSelectGroup, xBitsToClear ); + } + + /* Now include eSELECT_CALL_IP to wakeup the caller. */ + xEventGroupSetBits( pxSocketSet->xSelectGroup, xGroupBits | eSELECT_CALL_IP ); + } + +#endif /* ipconfigSUPPORT_SELECT_FUNCTION == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigSUPPORT_SIGNALS != 0 ) + + /* Send a signal to the task which reads from this socket. */ + BaseType_t FreeRTOS_SignalSocket( Socket_t xSocket ) + { + FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) xSocket; + BaseType_t xReturn; + + if( pxSocket == NULL ) + { + xReturn = -pdFREERTOS_ERRNO_EINVAL; + } + else + #if( ipconfigSUPPORT_SELECT_FUNCTION == 1 ) + if( ( pxSocket->pxSocketSet != NULL ) && ( pxSocket->pxSocketSet->xSelectGroup != NULL ) ) + { + xEventGroupSetBits( pxSocket->pxSocketSet->xSelectGroup, eSELECT_INTR ); + xReturn = 0; + } + else + #endif /* ipconfigSUPPORT_SELECT_FUNCTION */ + if( pxSocket->xEventGroup != NULL ) + { + xEventGroupSetBits( pxSocket->xEventGroup, eSOCKET_INTR ); + xReturn = 0; + } + else + { + xReturn = -pdFREERTOS_ERRNO_EINVAL; + } + + return xReturn; + } + +#endif /* ipconfigSUPPORT_SIGNALS */ +/*-----------------------------------------------------------*/ + +#if( ipconfigSUPPORT_SIGNALS != 0 ) + + /* Send a signal to the task which reads from this socket (FromISR version). */ + BaseType_t FreeRTOS_SignalSocketFromISR( Socket_t xSocket, BaseType_t *pxHigherPriorityTaskWoken ) + { + FreeRTOS_Socket_t *pxSocket = ( FreeRTOS_Socket_t * ) xSocket; + BaseType_t xReturn; + IPStackEvent_t xEvent; + extern QueueHandle_t xNetworkEventQueue; + + configASSERT( pxSocket != NULL ); + configASSERT( pxSocket->ucProtocol == FREERTOS_IPPROTO_TCP ); + configASSERT( pxSocket->xEventGroup ); + + xEvent.eEventType = eSocketSignalEvent; + xEvent.pvData = ( void * )pxSocket; + + /* The IP-task will call FreeRTOS_SignalSocket for this socket. */ + xReturn = xQueueSendToBackFromISR( xNetworkEventQueue, &xEvent, pxHigherPriorityTaskWoken ); + + return xReturn; + } + +#endif /* ipconfigSUPPORT_SIGNALS */ +/*-----------------------------------------------------------*/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_Stream_Buffer.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_Stream_Buffer.c new file mode 100644 index 0000000..f903fad --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_Stream_Buffer.c @@ -0,0 +1,199 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_UDP_IP.h" +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_IP_Private.h" + +/* + * uxStreamBufferAdd( ) + * Adds data to a stream buffer. If uxOffset > 0, data will be written at + * an offset from uxHead while uxHead will not be moved yet. This possibility + * will be used when TCP data is received while earlier data is still missing. + * If 'pucData' equals NULL, the function is called to advance 'uxHead' only. + */ +size_t uxStreamBufferAdd( StreamBuffer_t *pxBuffer, size_t uxOffset, const uint8_t *pucData, size_t uxCount ) +{ +size_t uxSpace, uxNextHead, uxFirst; + + uxSpace = uxStreamBufferGetSpace( pxBuffer ); + + /* If uxOffset > 0, items can be placed in front of uxHead */ + if( uxSpace > uxOffset ) + { + uxSpace -= uxOffset; + } + else + { + uxSpace = 0u; + } + + /* The number of bytes that can be written is the minimum of the number of + bytes requested and the number available. */ + uxCount = FreeRTOS_min_uint32( uxSpace, uxCount ); + + if( uxCount != 0u ) + { + uxNextHead = pxBuffer->uxHead; + + if( uxOffset != 0u ) + { + /* ( uxOffset > 0 ) means: write in front if the uxHead marker */ + uxNextHead += uxOffset; + if( uxNextHead >= pxBuffer->LENGTH ) + { + uxNextHead -= pxBuffer->LENGTH; + } + } + + if( pucData != NULL ) + { + /* Calculate the number of bytes that can be added in the first + write - which may be less than the total number of bytes that need + to be added if the buffer will wrap back to the beginning. */ + uxFirst = FreeRTOS_min_uint32( pxBuffer->LENGTH - uxNextHead, uxCount ); + + /* Write as many bytes as can be written in the first write. */ + memcpy( ( void* ) ( pxBuffer->ucArray + uxNextHead ), pucData, uxFirst ); + + /* If the number of bytes written was less than the number that + could be written in the first write... */ + if( uxCount > uxFirst ) + { + /* ...then write the remaining bytes to the start of the + buffer. */ + memcpy( ( void * )pxBuffer->ucArray, pucData + uxFirst, uxCount - uxFirst ); + } + } + + if( uxOffset == 0u ) + { + /* ( uxOffset == 0 ) means: write at uxHead position */ + uxNextHead += uxCount; + if( uxNextHead >= pxBuffer->LENGTH ) + { + uxNextHead -= pxBuffer->LENGTH; + } + pxBuffer->uxHead = uxNextHead; + } + + if( xStreamBufferLessThenEqual( pxBuffer, pxBuffer->uxFront, uxNextHead ) != pdFALSE ) + { + /* Advance the front pointer */ + pxBuffer->uxFront = uxNextHead; + } + } + + return uxCount; +} +/*-----------------------------------------------------------*/ + +/* + * uxStreamBufferGet( ) + * 'uxOffset' can be used to read data located at a certain offset from 'lTail'. + * If 'pucData' equals NULL, the function is called to advance 'lTail' only. + * if 'xPeek' is pdTRUE, or if 'uxOffset' is non-zero, the 'lTail' pointer will + * not be advanced. + */ +size_t uxStreamBufferGet( StreamBuffer_t *pxBuffer, size_t uxOffset, uint8_t *pucData, size_t uxMaxCount, BaseType_t xPeek ) +{ +size_t uxSize, uxCount, uxFirst, uxNextTail; + + /* How much data is available? */ + uxSize = uxStreamBufferGetSize( pxBuffer ); + + if( uxSize > uxOffset ) + { + uxSize -= uxOffset; + } + else + { + uxSize = 0u; + } + + /* Use the minimum of the wanted bytes and the available bytes. */ + uxCount = FreeRTOS_min_uint32( uxSize, uxMaxCount ); + + if( uxCount > 0u ) + { + uxNextTail = pxBuffer->uxTail; + + if( uxOffset != 0u ) + { + uxNextTail += uxOffset; + if( uxNextTail >= pxBuffer->LENGTH ) + { + uxNextTail -= pxBuffer->LENGTH; + } + } + + if( pucData != NULL ) + { + /* Calculate the number of bytes that can be read - which may be + less than the number wanted if the data wraps around to the start of + the buffer. */ + uxFirst = FreeRTOS_min_uint32( pxBuffer->LENGTH - uxNextTail, uxCount ); + + /* Obtain the number of bytes it is possible to obtain in the first + read. */ + memcpy( pucData, pxBuffer->ucArray + uxNextTail, uxFirst ); + + /* If the total number of wanted bytes is greater than the number + that could be read in the first read... */ + if( uxCount > uxFirst ) + { + /*...then read the remaining bytes from the start of the buffer. */ + memcpy( pucData + uxFirst, pxBuffer->ucArray, uxCount - uxFirst ); + } + } + + if( ( xPeek == pdFALSE ) && ( uxOffset == 0UL ) ) + { + /* Move the tail pointer to effecively remove the data read from + the buffer. */ + uxNextTail += uxCount; + + if( uxNextTail >= pxBuffer->LENGTH ) + { + uxNextTail -= pxBuffer->LENGTH; + } + + pxBuffer->uxTail = uxNextTail; + } + } + + return uxCount; +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_TCP_IP.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_TCP_IP.c new file mode 100644 index 0000000..7ec0733 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_TCP_IP.c @@ -0,0 +1,3309 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +/* + * FreeRTOS_TCP_IP.c + * Module which handles the TCP connections for FreeRTOS+TCP. + * It depends on FreeRTOS_TCP_WIN.c, which handles the TCP windowing + * schemes. + * + * Endianness: in this module all ports and IP addresses are stored in + * host byte-order, except fields in the IP-packets + */ + +/* Standard includes. */ +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_IP_Private.h" +#include "FreeRTOS_UDP_IP.h" +#include "FreeRTOS_TCP_IP.h" +#include "FreeRTOS_DHCP.h" +#include "NetworkInterface.h" +#include "NetworkBufferManagement.h" +#include "FreeRTOS_ARP.h" +#include "FreeRTOS_TCP_WIN.h" + + +/* Just make sure the contents doesn't get compiled if TCP is not enabled. */ +#if ipconfigUSE_TCP == 1 + +/* This compile-time test was moved to here because some macro's +were unknown within 'FreeRTOSIPConfigDefaults.h'. It tests whether +the defined MTU size can contain at least a complete TCP packet. */ + +#if ( ( ipconfigTCP_MSS + ipSIZE_OF_IPv4_HEADER + ipSIZE_OF_TCP_HEADER ) > ipconfigNETWORK_MTU ) + #error The ipconfigTCP_MSS setting in FreeRTOSIPConfig.h is too large. +#endif + +/* + * The meaning of the TCP flags: + */ +#define ipTCP_FLAG_FIN 0x0001u /* No more data from sender */ +#define ipTCP_FLAG_SYN 0x0002u /* Synchronize sequence numbers */ +#define ipTCP_FLAG_RST 0x0004u /* Reset the connection */ +#define ipTCP_FLAG_PSH 0x0008u /* Push function: please push buffered data to the recv application */ +#define ipTCP_FLAG_ACK 0x0010u /* Acknowledgment field is significant */ +#define ipTCP_FLAG_URG 0x0020u /* Urgent pointer field is significant */ +#define ipTCP_FLAG_ECN 0x0040u /* ECN-Echo */ +#define ipTCP_FLAG_CWR 0x0080u /* Congestion Window Reduced */ +#define ipTCP_FLAG_NS 0x0100u /* ECN-nonce concealment protection */ +#define ipTCP_FLAG_RSV 0x0E00u /* Reserved, keep 0 */ + +/* A mask to filter all protocol flags. */ +#define ipTCP_FLAG_CTRL 0x001Fu + +/* + * A few values of the TCP options: + */ +#define TCP_OPT_END 0u /* End of TCP options list */ +#define TCP_OPT_NOOP 1u /* "No-operation" TCP option */ +#define TCP_OPT_MSS 2u /* Maximum segment size TCP option */ +#define TCP_OPT_WSOPT 3u /* TCP Window Scale Option (3-byte long) */ +#define TCP_OPT_SACK_P 4u /* Advertize that SACK is permitted */ +#define TCP_OPT_SACK_A 5u /* SACK option with first/last */ +#define TCP_OPT_TIMESTAMP 8u /* Time-stamp option */ + +#define TCP_OPT_MSS_LEN 4u /* Length of TCP MSS option. */ +#define TCP_OPT_WSOPT_LEN 3u /* Length of TCP WSOPT option. */ + +#define TCP_OPT_TIMESTAMP_LEN 10 /* fixed length of the time-stamp option */ + +#ifndef ipconfigTCP_ACK_EARLIER_PACKET + #define ipconfigTCP_ACK_EARLIER_PACKET 1 +#endif + +/* + * The macro NOW_CONNECTED() is use to determine if the connection makes a + * transition from connected to non-connected and vice versa. + * NOW_CONNECTED() returns true when the status has one of these values: + * eESTABLISHED, eFIN_WAIT_1, eFIN_WAIT_2, eCLOSING, eLAST_ACK, eTIME_WAIT + * Technically the connection status is closed earlier, but the library wants + * to prevent that the socket will be deleted before the last ACK has been + * and thus causing a 'RST' packet on either side. + */ +#define NOW_CONNECTED( status )\ + ( ( status >= eESTABLISHED ) && ( status != eCLOSE_WAIT ) ) + +/* + * The highest 4 bits in the TCP offset byte indicate the total length of the + * TCP header, divided by 4. + */ +#define VALID_BITS_IN_TCP_OFFSET_BYTE ( 0xF0u ) + +/* + * Acknowledgements to TCP data packets may be delayed as long as more is being expected. + * A normal delay would be 200ms. Here a much shorter delay of 20 ms is being used to + * gain performance. + */ +#define DELAYED_ACK_SHORT_DELAY_MS ( 2 ) +#define DELAYED_ACK_LONGER_DELAY_MS ( 20 ) + +/* + * The MSS (Maximum Segment Size) will be taken as large as possible. However, packets with + * an MSS of 1460 bytes won't be transported through the internet. The MSS will be reduced + * to 1400 bytes. + */ +#define REDUCED_MSS_THROUGH_INTERNET ( 1400 ) + +/* + * When there are no TCP options, the TCP offset equals 20 bytes, which is stored as + * the number 5 (words) in the higher niblle of the TCP-offset byte. + */ +#define TCP_OFFSET_LENGTH_BITS ( 0xf0u ) +#define TCP_OFFSET_STANDARD_LENGTH ( 0x50u ) + +/* + * Each TCP socket is checked regularly to see if it can send data packets. + * By default, the maximum number of packets sent during one check is limited to 8. + * This amount may be further limited by setting the socket's TX window size. + */ +#if( !defined( SEND_REPEATED_COUNT ) ) + #define SEND_REPEATED_COUNT ( 8 ) +#endif /* !defined( SEND_REPEATED_COUNT ) */ + +/* + * Define a maximum perdiod of time (ms) to leave a TCP-socket unattended. + * When a TCP timer expires, retries and keep-alive messages will be checked. + */ +#ifndef tcpMAXIMUM_TCP_WAKEUP_TIME_MS + #define tcpMAXIMUM_TCP_WAKEUP_TIME_MS 20000u +#endif + +/* + * The names of the different TCP states may be useful in logging. + */ +#if( ( ipconfigHAS_DEBUG_PRINTF != 0 ) || ( ipconfigHAS_PRINTF != 0 ) ) + static const char *pcStateNames[] = { + "eCLOSED", + "eTCP_LISTEN", + "eCONNECT_SYN", + "eSYN_FIRST", + "eSYN_RECEIVED", + "eESTABLISHED", + "eFIN_WAIT_1", + "eFIN_WAIT_2", + "eCLOSE_WAIT", + "eCLOSING", + "eLAST_ACK", + "eTIME_WAIT", + "eUNKNOWN", +}; +#endif /* ( ipconfigHAS_DEBUG_PRINTF != 0 ) || ( ipconfigHAS_PRINTF != 0 ) */ + +/* + * Returns true if the socket must be checked. Non-active sockets are waiting + * for user action, either connect() or close(). + */ +static BaseType_t prvTCPSocketIsActive( UBaseType_t uxStatus ); + +/* + * Either sends a SYN or calls prvTCPSendRepeated (for regular messages). + */ +static int32_t prvTCPSendPacket( FreeRTOS_Socket_t *pxSocket ); + +/* + * Try to send a series of messages. + */ +static int32_t prvTCPSendRepeated( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t **ppxNetworkBuffer ); + +/* + * Return or send a packet to the other party. + */ +static void prvTCPReturnPacket( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t *pxNetworkBuffer, + uint32_t ulLen, BaseType_t xReleaseAfterSend ); + +/* + * Initialise the data structures which keep track of the TCP windowing system. + */ +static void prvTCPCreateWindow( FreeRTOS_Socket_t *pxSocket ); + +/* + * Let ARP look-up the MAC-address of the peer and initialise the first SYN + * packet. + */ +static BaseType_t prvTCPPrepareConnect( FreeRTOS_Socket_t *pxSocket ); + +#if( ipconfigHAS_DEBUG_PRINTF != 0 ) + /* + * For logging and debugging: make a string showing the TCP flags. + */ + static const char *prvTCPFlagMeaning( UBaseType_t xFlags); +#endif /* ipconfigHAS_DEBUG_PRINTF != 0 */ + +/* + * Parse the TCP option(s) received, if present. + */ +static void prvCheckOptions( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t *pxNetworkBuffer ); + +/* + * Set the initial properties in the options fields, like the preferred + * value of MSS and whether SACK allowed. Will be transmitted in the state + * 'eCONNECT_SYN'. + */ +static UBaseType_t prvSetSynAckOptions( FreeRTOS_Socket_t *pxSocket, TCPPacket_t * pxTCPPacket ); + +/* + * For anti-hang protection and TCP keep-alive messages. Called in two places: + * after receiving a packet and after a state change. The socket's alive timer + * may be reset. + */ +static void prvTCPTouchSocket( FreeRTOS_Socket_t *pxSocket ); + +/* + * Prepare an outgoing message, if anything has to be sent. + */ +static int32_t prvTCPPrepareSend( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t **ppxNetworkBuffer, UBaseType_t uxOptionsLength ); + +/* + * Calculate when this socket needs to be checked to do (re-)transmissions. + */ +static TickType_t prvTCPNextTimeout( FreeRTOS_Socket_t *pxSocket ); + +/* + * The API FreeRTOS_send() adds data to the TX stream. Add + * this data to the windowing system to it can be transmitted. + */ +static void prvTCPAddTxData( FreeRTOS_Socket_t *pxSocket ); + +/* + * Called to handle the closure of a TCP connection. + */ +static BaseType_t prvTCPHandleFin( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t *pxNetworkBuffer ); + +/* + * Called from prvTCPHandleState(). Find the TCP payload data and check and + * return its length. + */ +static BaseType_t prvCheckRxData( NetworkBufferDescriptor_t *pxNetworkBuffer, uint8_t **ppucRecvData ); + +/* + * Called from prvTCPHandleState(). Check if the payload data may be accepted. + * If so, it will be added to the socket's reception queue. + */ +static BaseType_t prvStoreRxData( FreeRTOS_Socket_t *pxSocket, uint8_t *pucRecvData, + NetworkBufferDescriptor_t *pxNetworkBuffer, uint32_t ulReceiveLength ); + +/* + * Set the TCP options (if any) for the outgoing packet. + */ +static UBaseType_t prvSetOptions( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t *pxNetworkBuffer ); + +/* + * Called from prvTCPHandleState() as long as the TCP status is eSYN_RECEIVED to + * eCONNECT_SYN. + */ +static BaseType_t prvHandleSynReceived( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t **ppxNetworkBuffer, + uint32_t ulReceiveLength, UBaseType_t uxOptionsLength ); + +/* + * Called from prvTCPHandleState() as long as the TCP status is eESTABLISHED. + */ +static BaseType_t prvHandleEstablished( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t **ppxNetworkBuffer, + uint32_t ulReceiveLength, UBaseType_t uxOptionsLength ); + +/* + * Called from prvTCPHandleState(). There is data to be sent. + * If ipconfigUSE_TCP_WIN is defined, and if only an ACK must be sent, it will + * be checked if it would better be postponed for efficiency. + */ +static BaseType_t prvSendData( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t **ppxNetworkBuffer, + uint32_t ulReceiveLength, BaseType_t xSendLength ); + +/* + * The heart of all: check incoming packet for valid data and acks and do what + * is necessary in each state. + */ +static BaseType_t prvTCPHandleState( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t **ppxNetworkBuffer ); + +/* + * Reply to a peer with the RST flag on, in case a packet can not be handled. + */ +static BaseType_t prvTCPSendReset( NetworkBufferDescriptor_t *pxNetworkBuffer ); + +/* + * Set the initial value for MSS (Maximum Segment Size) to be used. + */ +static void prvSocketSetMSS( FreeRTOS_Socket_t *pxSocket ); + +/* + * Return either a newly created socket, or the current socket in a connected + * state (depends on the 'bReuseSocket' flag). + */ +static FreeRTOS_Socket_t *prvHandleListen( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t *pxNetworkBuffer ); + +/* + * After a listening socket receives a new connection, it may duplicate itself. + * The copying takes place in prvTCPSocketCopy. + */ +static BaseType_t prvTCPSocketCopy( FreeRTOS_Socket_t *pxNewSocket, FreeRTOS_Socket_t *pxSocket ); + +/* + * prvTCPStatusAgeCheck() will see if the socket has been in a non-connected + * state for too long. If so, the socket will be closed, and -1 will be + * returned. + */ +#if( ipconfigTCP_HANG_PROTECTION == 1 ) + static BaseType_t prvTCPStatusAgeCheck( FreeRTOS_Socket_t *pxSocket ); +#endif + +static NetworkBufferDescriptor_t *prvTCPBufferResize( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t *pxNetworkBuffer, + int32_t lDataLen, UBaseType_t uxOptionsLength ); + +#if( ( ipconfigHAS_DEBUG_PRINTF != 0 ) || ( ipconfigHAS_PRINTF != 0 ) ) + const char *FreeRTOS_GetTCPStateName( UBaseType_t ulState ); +#endif + +#if( ipconfigUSE_TCP_WIN != 0 ) + static uint8_t prvWinScaleFactor( FreeRTOS_Socket_t *pxSocket ); +#endif + +/* + * Generate a randomized TCP Initial Sequence Number per RFC. + */ +extern uint32_t ulApplicationGetNextSequenceNumber( uint32_t ulSourceAddress, + uint16_t usSourcePort, + uint32_t ulDestinationAddress, + uint16_t usDestinationPort ); + +/*-----------------------------------------------------------*/ + +/* prvTCPSocketIsActive() returns true if the socket must be checked. + * Non-active sockets are waiting for user action, either connect() + * or close(). */ +static BaseType_t prvTCPSocketIsActive( UBaseType_t uxStatus ) +{ + switch( uxStatus ) + { + case eCLOSED: + case eCLOSE_WAIT: + case eFIN_WAIT_2: + case eCLOSING: + case eTIME_WAIT: + return pdFALSE; + default: + return pdTRUE; + } +} +/*-----------------------------------------------------------*/ + +#if( ipconfigTCP_HANG_PROTECTION == 1 ) + + static BaseType_t prvTCPStatusAgeCheck( FreeRTOS_Socket_t *pxSocket ) + { + BaseType_t xResult; + switch( pxSocket->u.xTCP.ucTCPState ) + { + case eESTABLISHED: + /* If the 'ipconfigTCP_KEEP_ALIVE' option is enabled, sockets in + state ESTABLISHED can be protected using keep-alive messages. */ + xResult = pdFALSE; + break; + case eCLOSED: + case eTCP_LISTEN: + case eCLOSE_WAIT: + /* These 3 states may last for ever, up to the owner. */ + xResult = pdFALSE; + break; + default: + /* All other (non-connected) states will get anti-hanging + protection. */ + xResult = pdTRUE; + break; + } + if( xResult != pdFALSE ) + { + /* How much time has past since the last active moment which is + defined as A) a state change or B) a packet has arrived. */ + TickType_t xAge = xTaskGetTickCount( ) - pxSocket->u.xTCP.xLastActTime; + + /* ipconfigTCP_HANG_PROTECTION_TIME is in units of seconds. */ + if( xAge > ( ipconfigTCP_HANG_PROTECTION_TIME * configTICK_RATE_HZ ) ) + { + #if( ipconfigHAS_DEBUG_PRINTF == 1 ) + { + FreeRTOS_debug_printf( ( "Inactive socket closed: port %u rem %lxip:%u status %s\n", + pxSocket->usLocalPort, + pxSocket->u.xTCP.ulRemoteIP, + pxSocket->u.xTCP.usRemotePort, + FreeRTOS_GetTCPStateName( ( UBaseType_t ) pxSocket->u.xTCP.ucTCPState ) ) ); + } + #endif /* ipconfigHAS_DEBUG_PRINTF */ + + /* Move to eCLOSE_WAIT, user may close the socket. */ + vTCPStateChange( pxSocket, eCLOSE_WAIT ); + + /* When 'bPassQueued' true, this socket is an orphan until it + gets connected. */ + if( pxSocket->u.xTCP.bits.bPassQueued != pdFALSE_UNSIGNED ) + { + if( pxSocket->u.xTCP.bits.bReuseSocket == pdFALSE_UNSIGNED ) + { + /* As it did not get connected, and the user can never + accept() it anymore, it will be deleted now. Called from + the IP-task, so it's safe to call the internal Close + function: vSocketClose(). */ + vSocketClose( pxSocket ); + } + /* Return a negative value to tell to inform the caller + xTCPTimerCheck() + that the socket got closed and may not be accessed anymore. */ + xResult = -1; + } + } + } + return xResult; + } + /*-----------------------------------------------------------*/ + +#endif + +/* + * As soon as a TCP socket timer expires, this function xTCPSocketCheck + * will be called (from xTCPTimerCheck) + * It can send a delayed ACK or new data + * Sequence of calling (normally) : + * IP-Task: + * xTCPTimerCheck() // Check all sockets ( declared in FreeRTOS_Sockets.c ) + * xTCPSocketCheck() // Either send a delayed ACK or call prvTCPSendPacket() + * prvTCPSendPacket() // Either send a SYN or call prvTCPSendRepeated ( regular messages ) + * prvTCPSendRepeated() // Send at most 8 messages on a row + * prvTCPReturnPacket() // Prepare for returning + * xNetworkInterfaceOutput() // Sends data to the NIC ( declared in portable/NetworkInterface/xxx ) + */ +BaseType_t xTCPSocketCheck( FreeRTOS_Socket_t *pxSocket ) +{ +BaseType_t xResult = 0; +BaseType_t xReady = pdFALSE; + + if( ( pxSocket->u.xTCP.ucTCPState >= eESTABLISHED ) && ( pxSocket->u.xTCP.txStream != NULL ) ) + { + /* The API FreeRTOS_send() might have added data to the TX stream. Add + this data to the windowing system to it can be transmitted. */ + prvTCPAddTxData( pxSocket ); + } + + #if ipconfigUSE_TCP_WIN == 1 + { + if( pxSocket->u.xTCP.pxAckMessage != NULL ) + { + /* The first task of this regular socket check is to send-out delayed + ACK's. */ + if( pxSocket->u.xTCP.bits.bUserShutdown == pdFALSE_UNSIGNED ) + { + /* Earlier data was received but not yet acknowledged. This + function is called when the TCP timer for the socket expires, the + ACK may be sent now. */ + if( pxSocket->u.xTCP.ucTCPState != eCLOSED ) + { + if( xTCPWindowLoggingLevel > 1 && ipconfigTCP_MAY_LOG_PORT( pxSocket->usLocalPort ) ) + { + FreeRTOS_debug_printf( ( "Send[%u->%u] del ACK %lu SEQ %lu (len %u)\n", + pxSocket->usLocalPort, + pxSocket->u.xTCP.usRemotePort, + pxSocket->u.xTCP.xTCPWindow.rx.ulCurrentSequenceNumber - pxSocket->u.xTCP.xTCPWindow.rx.ulFirstSequenceNumber, + pxSocket->u.xTCP.xTCPWindow.ulOurSequenceNumber - pxSocket->u.xTCP.xTCPWindow.tx.ulFirstSequenceNumber, + ipSIZE_OF_IPv4_HEADER + ipSIZE_OF_TCP_HEADER ) ); + } + + prvTCPReturnPacket( pxSocket, pxSocket->u.xTCP.pxAckMessage, ipSIZE_OF_IPv4_HEADER + ipSIZE_OF_TCP_HEADER, ipconfigZERO_COPY_TX_DRIVER ); + + #if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + { + /* The ownership has been passed to the SEND routine, + clear the pointer to it. */ + pxSocket->u.xTCP.pxAckMessage = NULL; + } + #endif /* ipconfigZERO_COPY_TX_DRIVER */ + } + if( prvTCPNextTimeout( pxSocket ) > 1 ) + { + /* Tell the code below that this function is ready. */ + xReady = pdTRUE; + } + } + else + { + /* The user wants to perform an active shutdown(), skip sending + the delayed ACK. The function prvTCPSendPacket() will send the + FIN along with the ACK's. */ + } + + if( pxSocket->u.xTCP.pxAckMessage != NULL ) + { + vReleaseNetworkBufferAndDescriptor( pxSocket->u.xTCP.pxAckMessage ); + pxSocket->u.xTCP.pxAckMessage = NULL; + } + } + } + #endif /* ipconfigUSE_TCP_WIN */ + + if( xReady == pdFALSE ) + { + /* The second task of this regular socket check is sending out data. */ + if( ( pxSocket->u.xTCP.ucTCPState >= eESTABLISHED ) || + ( pxSocket->u.xTCP.ucTCPState == eCONNECT_SYN ) ) + { + prvTCPSendPacket( pxSocket ); + } + + /* Set the time-out for the next wakeup for this socket. */ + prvTCPNextTimeout( pxSocket ); + + #if( ipconfigTCP_HANG_PROTECTION == 1 ) + { + /* In all (non-connected) states in which keep-alive messages can not be sent + the anti-hang protocol will close sockets that are 'hanging'. */ + xResult = prvTCPStatusAgeCheck( pxSocket ); + } + #endif + } + + return xResult; +} +/*-----------------------------------------------------------*/ + +/* + * prvTCPSendPacket() will be called when the socket time-out has been reached. + * It is only called by xTCPSocketCheck(). + */ +static int32_t prvTCPSendPacket( FreeRTOS_Socket_t *pxSocket ) +{ +int32_t lResult = 0; +UBaseType_t uxOptionsLength; +TCPPacket_t *pxTCPPacket; +NetworkBufferDescriptor_t *pxNetworkBuffer; + + if( pxSocket->u.xTCP.ucTCPState != eCONNECT_SYN ) + { + /* The connection is in s state other than SYN. */ + pxNetworkBuffer = NULL; + + /* prvTCPSendRepeated() will only create a network buffer if necessary, + i.e. when data must be sent to the peer. */ + lResult = prvTCPSendRepeated( pxSocket, &pxNetworkBuffer ); + + if( pxNetworkBuffer != NULL ) + { + vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ); + } + } + else + { + if( pxSocket->u.xTCP.ucRepCount >= 3u ) + { + /* The connection is in the SYN status. The packet will be repeated + to most 3 times. When there is no response, the socket get the + status 'eCLOSE_WAIT'. */ + FreeRTOS_debug_printf( ( "Connect: giving up %lxip:%u\n", + pxSocket->u.xTCP.ulRemoteIP, /* IP address of remote machine. */ + pxSocket->u.xTCP.usRemotePort ) ); /* Port on remote machine. */ + vTCPStateChange( pxSocket, eCLOSE_WAIT ); + } + else if( ( pxSocket->u.xTCP.bits.bConnPrepared != pdFALSE_UNSIGNED ) || ( prvTCPPrepareConnect( pxSocket ) == pdTRUE ) ) + { + /* Or else, if the connection has been prepared, or can be prepared + now, proceed to send the packet with the SYN flag. + prvTCPPrepareConnect() prepares 'xPacket' and returns pdTRUE if + the Ethernet address of the peer or the gateway is found. */ + pxTCPPacket = ( TCPPacket_t * )pxSocket->u.xTCP.xPacket.u.ucLastPacket; + + /* About to send a SYN packet. Call prvSetSynAckOptions() to set + the proper options: The size of MSS and whether SACK's are + allowed. */ + uxOptionsLength = prvSetSynAckOptions( pxSocket, pxTCPPacket ); + + /* Return the number of bytes to be sent. */ + lResult = ( BaseType_t ) ( ipSIZE_OF_IPv4_HEADER + ipSIZE_OF_TCP_HEADER + uxOptionsLength ); + + /* Set the TCP offset field: ipSIZE_OF_TCP_HEADER equals 20 and + uxOptionsLength is always a multiple of 4. The complete expression + would be: + ucTCPOffset = ( ( ipSIZE_OF_TCP_HEADER + uxOptionsLength ) / 4 ) << 4 */ + pxTCPPacket->xTCPHeader.ucTCPOffset = ( uint8_t )( ( ipSIZE_OF_TCP_HEADER + uxOptionsLength ) << 2 ); + + /* Repeat Count is used for a connecting socket, to limit the number + of tries. */ + pxSocket->u.xTCP.ucRepCount++; + + /* Send the SYN message to make a connection. The messages is + stored in the socket field 'xPacket'. It will be wrapped in a + pseudo network buffer descriptor before it will be sent. */ + prvTCPReturnPacket( pxSocket, NULL, ( uint32_t ) lResult, pdFALSE ); + } + } + + /* Return the total number of bytes sent. */ + return lResult; +} +/*-----------------------------------------------------------*/ + +/* + * prvTCPSendRepeated will try to send a series of messages, as long as there is + * data to be sent and as long as the transmit window isn't full. + */ +static int32_t prvTCPSendRepeated( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t **ppxNetworkBuffer ) +{ +UBaseType_t uxIndex; +int32_t lResult = 0; +UBaseType_t uxOptionsLength = 0u; +int32_t xSendLength; + + for( uxIndex = 0u; uxIndex < ( UBaseType_t ) SEND_REPEATED_COUNT; uxIndex++ ) + { + /* prvTCPPrepareSend() might allocate a network buffer if there is data + to be sent. */ + xSendLength = prvTCPPrepareSend( pxSocket, ppxNetworkBuffer, uxOptionsLength ); + if( xSendLength <= 0 ) + { + break; + } + + /* And return the packet to the peer. */ + prvTCPReturnPacket( pxSocket, *ppxNetworkBuffer, ( uint32_t ) xSendLength, ipconfigZERO_COPY_TX_DRIVER ); + + #if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + { + *ppxNetworkBuffer = NULL; + } + #endif /* ipconfigZERO_COPY_TX_DRIVER */ + + lResult += xSendLength; + } + + /* Return the total number of bytes sent. */ + return lResult; +} +/*-----------------------------------------------------------*/ + +/* + * Return (or send) a packet the the peer. The data is stored in pxBuffer, + * which may either point to a real network buffer or to a TCP socket field + * called 'xTCP.xPacket'. A temporary xNetworkBuffer will be used to pass + * the data to the NIC. + */ +static void prvTCPReturnPacket( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t *pxNetworkBuffer, uint32_t ulLen, BaseType_t xReleaseAfterSend ) +{ +TCPPacket_t * pxTCPPacket; +IPHeader_t *pxIPHeader; +EthernetHeader_t *pxEthernetHeader; +uint32_t ulFrontSpace, ulSpace, ulSourceAddress, ulWinSize; +TCPWindow_t *pxTCPWindow; +NetworkBufferDescriptor_t xTempBuffer; +/* For sending, a pseudo network buffer will be used, as explained above. */ + + if( pxNetworkBuffer == NULL ) + { + pxNetworkBuffer = &xTempBuffer; + + #if( ipconfigUSE_LINKED_RX_MESSAGES != 0 ) + { + xTempBuffer.pxNextBuffer = NULL; + } + #endif + xTempBuffer.pucEthernetBuffer = pxSocket->u.xTCP.xPacket.u.ucLastPacket; + xTempBuffer.xDataLength = sizeof( pxSocket->u.xTCP.xPacket.u.ucLastPacket ); + xReleaseAfterSend = pdFALSE; + } + + #if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + { + if( xReleaseAfterSend == pdFALSE ) + { + pxNetworkBuffer = pxDuplicateNetworkBufferWithDescriptor( pxNetworkBuffer, ( BaseType_t ) pxNetworkBuffer->xDataLength ); + if( pxNetworkBuffer == NULL ) + { + FreeRTOS_debug_printf( ( "prvTCPReturnPacket: duplicate failed\n" ) ); + } + xReleaseAfterSend = pdTRUE; + } + } + #endif /* ipconfigZERO_COPY_TX_DRIVER */ + + if( pxNetworkBuffer != NULL ) + { + pxTCPPacket = ( TCPPacket_t * ) ( pxNetworkBuffer->pucEthernetBuffer ); + pxIPHeader = &pxTCPPacket->xIPHeader; + pxEthernetHeader = &pxTCPPacket->xEthernetHeader; + + /* Fill the packet, using hton translations. */ + if( pxSocket != NULL ) + { + /* Calculate the space in the RX buffer in order to advertise the + size of this socket's reception window. */ + pxTCPWindow = &( pxSocket->u.xTCP.xTCPWindow ); + + if( pxSocket->u.xTCP.rxStream != NULL ) + { + /* An RX stream was created already, see how much space is + available. */ + ulFrontSpace = ( uint32_t ) uxStreamBufferFrontSpace( pxSocket->u.xTCP.rxStream ); + } + else + { + /* No RX stream has been created, the full stream size is + available. */ + ulFrontSpace = ( uint32_t ) pxSocket->u.xTCP.uxRxStreamSize; + } + + /* Take the minimum of the RX buffer space and the RX window size. */ + ulSpace = FreeRTOS_min_uint32( pxSocket->u.xTCP.ulRxCurWinSize, pxTCPWindow->xSize.ulRxWindowLength ); + + if( ( pxSocket->u.xTCP.bits.bLowWater != pdFALSE_UNSIGNED ) || ( pxSocket->u.xTCP.bits.bRxStopped != pdFALSE_UNSIGNED ) ) + { + /* The low-water mark was reached, meaning there was little + space left. The socket will wait until the application has read + or flushed the incoming data, and 'zero-window' will be + advertised. */ + ulSpace = 0u; + } + + /* If possible, advertise an RX window size of at least 1 MSS, otherwise + the peer might start 'zero window probing', i.e. sending small packets + (1, 2, 4, 8... bytes). */ + if( ( ulSpace < pxSocket->u.xTCP.usCurMSS ) && ( ulFrontSpace >= pxSocket->u.xTCP.usCurMSS ) ) + { + ulSpace = pxSocket->u.xTCP.usCurMSS; + } + + /* Avoid overflow of the 16-bit win field. */ + #if( ipconfigUSE_TCP_WIN != 0 ) + { + ulWinSize = ( ulSpace >> pxSocket->u.xTCP.ucMyWinScaleFactor ); + } + #else + { + ulWinSize = ulSpace; + } + #endif + if( ulWinSize > 0xfffcUL ) + { + ulWinSize = 0xfffcUL; + } + + pxTCPPacket->xTCPHeader.usWindow = FreeRTOS_htons( ( uint16_t ) ulWinSize ); + + #if( ipconfigHAS_DEBUG_PRINTF != 0 ) + { + if( ipconfigTCP_MAY_LOG_PORT( pxSocket->usLocalPort ) != pdFALSE ) + { + if( ( xTCPWindowLoggingLevel != 0 ) && ( pxSocket->u.xTCP.bits.bWinChange != pdFALSE_UNSIGNED ) ) + { + size_t uxFrontSpace; + + if(pxSocket->u.xTCP.rxStream != NULL) + { + uxFrontSpace = uxStreamBufferFrontSpace( pxSocket->u.xTCP.rxStream ) ; + } + else + { + uxFrontSpace = 0u; + } + + FreeRTOS_debug_printf( ( "%s: %lxip:%u: [%lu < %lu] winSize %ld\n", + pxSocket->u.xTCP.bits.bLowWater ? "STOP" : "GO ", + pxSocket->u.xTCP.ulRemoteIP, + pxSocket->u.xTCP.usRemotePort, + pxSocket->u.xTCP.bits.bLowWater ? pxSocket->u.xTCP.uxLittleSpace : uxFrontSpace, pxSocket->u.xTCP.uxEnoughSpace, + (int32_t) ( pxTCPWindow->rx.ulHighestSequenceNumber - pxTCPWindow->rx.ulCurrentSequenceNumber ) ) ); + } + } + } + #endif /* ipconfigHAS_DEBUG_PRINTF != 0 */ + + /* The new window size has been advertised, switch off the flag. */ + pxSocket->u.xTCP.bits.bWinChange = pdFALSE_UNSIGNED; + + /* Later on, when deciding to delay an ACK, a precise estimate is needed + of the free RX space. At this moment, 'ulHighestRxAllowed' would be the + highest sequence number minus 1 that the socket will accept. */ + pxSocket->u.xTCP.ulHighestRxAllowed = pxTCPWindow->rx.ulCurrentSequenceNumber + ulSpace; + + #if( ipconfigTCP_KEEP_ALIVE == 1 ) + if( pxSocket->u.xTCP.bits.bSendKeepAlive != pdFALSE_UNSIGNED ) + { + /* Sending a keep-alive packet, send the current sequence number + minus 1, which will be recognised as a keep-alive packet an + responded to by acknowledging the last byte. */ + pxSocket->u.xTCP.bits.bSendKeepAlive = pdFALSE_UNSIGNED; + pxSocket->u.xTCP.bits.bWaitKeepAlive = pdTRUE_UNSIGNED; + + pxTCPPacket->xTCPHeader.ulSequenceNumber = pxSocket->u.xTCP.xTCPWindow.ulOurSequenceNumber - 1UL; + pxTCPPacket->xTCPHeader.ulSequenceNumber = FreeRTOS_htonl( pxTCPPacket->xTCPHeader.ulSequenceNumber ); + } + else + #endif + { + pxTCPPacket->xTCPHeader.ulSequenceNumber = FreeRTOS_htonl( pxSocket->u.xTCP.xTCPWindow.ulOurSequenceNumber ); + + if( ( pxTCPPacket->xTCPHeader.ucTCPFlags & ( uint8_t ) ipTCP_FLAG_FIN ) != 0u ) + { + /* Suppress FIN in case this packet carries earlier data to be + retransmitted. */ + uint32_t ulDataLen = ( uint32_t ) ( ulLen - ( ipSIZE_OF_TCP_HEADER + ipSIZE_OF_IPv4_HEADER ) ); + if( ( pxTCPWindow->ulOurSequenceNumber + ulDataLen ) != pxTCPWindow->tx.ulFINSequenceNumber ) + { + pxTCPPacket->xTCPHeader.ucTCPFlags &= ( ( uint8_t ) ~ipTCP_FLAG_FIN ); + FreeRTOS_debug_printf( ( "Suppress FIN for %lu + %lu < %lu\n", + pxTCPWindow->ulOurSequenceNumber - pxTCPWindow->tx.ulFirstSequenceNumber, + ulDataLen, + pxTCPWindow->tx.ulFINSequenceNumber - pxTCPWindow->tx.ulFirstSequenceNumber ) ); + } + } + } + + /* Tell which sequence number is expected next time */ + pxTCPPacket->xTCPHeader.ulAckNr = FreeRTOS_htonl( pxTCPWindow->rx.ulCurrentSequenceNumber ); + } + else + { + /* Sending data without a socket, probably replying with a RST flag + Just swap the two sequence numbers. */ + vFlip_32( pxTCPPacket->xTCPHeader.ulSequenceNumber, pxTCPPacket->xTCPHeader.ulAckNr ); + } + + pxIPHeader->ucTimeToLive = ( uint8_t ) ipconfigTCP_TIME_TO_LIVE; + pxIPHeader->usLength = FreeRTOS_htons( ulLen ); + if( ( pxSocket == NULL ) || ( *ipLOCAL_IP_ADDRESS_POINTER == 0ul ) ) + { + /* When pxSocket is NULL, this function is called by prvTCPSendReset() + and the IP-addresses must be swapped. + Also swap the IP-addresses in case the IP-tack doesn't have an + IP-address yet, i.e. when ( *ipLOCAL_IP_ADDRESS_POINTER == 0ul ). */ + ulSourceAddress = pxIPHeader->ulDestinationIPAddress; + } + else + { + ulSourceAddress = *ipLOCAL_IP_ADDRESS_POINTER; + } + pxIPHeader->ulDestinationIPAddress = pxIPHeader->ulSourceIPAddress; + pxIPHeader->ulSourceIPAddress = ulSourceAddress; + vFlip_16( pxTCPPacket->xTCPHeader.usSourcePort, pxTCPPacket->xTCPHeader.usDestinationPort ); + + /* Just an increasing number. */ + pxIPHeader->usIdentification = FreeRTOS_htons( usPacketIdentifier ); + usPacketIdentifier++; + pxIPHeader->usFragmentOffset = 0u; + + #if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM == 0 ) + { + /* calculate the IP header checksum, in case the driver won't do that. */ + pxIPHeader->usHeaderChecksum = 0x00u; + pxIPHeader->usHeaderChecksum = usGenerateChecksum( 0UL, ( uint8_t * ) &( pxIPHeader->ucVersionHeaderLength ), ipSIZE_OF_IPv4_HEADER ); + pxIPHeader->usHeaderChecksum = ~FreeRTOS_htons( pxIPHeader->usHeaderChecksum ); + + /* calculate the TCP checksum for an outgoing packet. */ + usGenerateProtocolChecksum( (uint8_t*)pxTCPPacket, pxNetworkBuffer->xDataLength, pdTRUE ); + + /* A calculated checksum of 0 must be inverted as 0 means the checksum + is disabled. */ + if( pxTCPPacket->xTCPHeader.usChecksum == 0x00u ) + { + pxTCPPacket->xTCPHeader.usChecksum = 0xffffU; + } + } + #endif + + #if( ipconfigUSE_LINKED_RX_MESSAGES != 0 ) + pxNetworkBuffer->pxNextBuffer = NULL; + #endif + + /* Important: tell NIC driver how many bytes must be sent. */ + pxNetworkBuffer->xDataLength = ulLen + ipSIZE_OF_ETH_HEADER; + + /* Fill in the destination MAC addresses. */ + memcpy( ( void * ) &( pxEthernetHeader->xDestinationAddress ), ( void * ) &( pxEthernetHeader->xSourceAddress ), + sizeof( pxEthernetHeader->xDestinationAddress ) ); + + /* The source MAC addresses is fixed to 'ipLOCAL_MAC_ADDRESS'. */ + memcpy( ( void * ) &( pxEthernetHeader->xSourceAddress) , ( void * ) ipLOCAL_MAC_ADDRESS, ( size_t ) ipMAC_ADDRESS_LENGTH_BYTES ); + + #if defined( ipconfigETHERNET_MINIMUM_PACKET_BYTES ) + { + if( pxNetworkBuffer->xDataLength < ( size_t ) ipconfigETHERNET_MINIMUM_PACKET_BYTES ) + { + BaseType_t xIndex; + + for( xIndex = ( BaseType_t ) pxNetworkBuffer->xDataLength; xIndex < ( BaseType_t ) ipconfigETHERNET_MINIMUM_PACKET_BYTES; xIndex++ ) + { + pxNetworkBuffer->pucEthernetBuffer[ xIndex ] = 0u; + } + pxNetworkBuffer->xDataLength = ( size_t ) ipconfigETHERNET_MINIMUM_PACKET_BYTES; + } + } + #endif + + /* Send! */ + xNetworkInterfaceOutput( pxNetworkBuffer, xReleaseAfterSend ); + + if( xReleaseAfterSend == pdFALSE ) + { + /* Swap-back some fields, as pxBuffer probably points to a socket field + containing the packet header. */ + vFlip_16( pxTCPPacket->xTCPHeader.usSourcePort, pxTCPPacket->xTCPHeader.usDestinationPort); + pxTCPPacket->xIPHeader.ulSourceIPAddress = pxTCPPacket->xIPHeader.ulDestinationIPAddress; + memcpy( pxEthernetHeader->xSourceAddress.ucBytes, pxEthernetHeader->xDestinationAddress.ucBytes, ( size_t ) ipMAC_ADDRESS_LENGTH_BYTES ); + } + else + { + /* Nothing to do: the buffer has been passed to DMA and will be released after use */ + } + } /* if( pxNetworkBuffer != NULL ) */ +} +/*-----------------------------------------------------------*/ + +/* + * The SYN event is very important: the sequence numbers, which have a kind of + * random starting value, are being synchronised. The sliding window manager + * (in FreeRTOS_TCP_WIN.c) needs to know them, along with the Maximum Segment + * Size (MSS) in use. + */ +static void prvTCPCreateWindow( FreeRTOS_Socket_t *pxSocket ) +{ + if( xTCPWindowLoggingLevel ) + FreeRTOS_debug_printf( ( "Limits (using): TCP Win size %lu Water %lu <= %lu <= %lu\n", + pxSocket->u.xTCP.uxRxWinSize * ipconfigTCP_MSS, + pxSocket->u.xTCP.uxLittleSpace , + pxSocket->u.xTCP.uxEnoughSpace, + pxSocket->u.xTCP.uxRxStreamSize ) ); + vTCPWindowCreate( + &pxSocket->u.xTCP.xTCPWindow, + ipconfigTCP_MSS * pxSocket->u.xTCP.uxRxWinSize, + ipconfigTCP_MSS * pxSocket->u.xTCP.uxTxWinSize, + pxSocket->u.xTCP.xTCPWindow.rx.ulCurrentSequenceNumber, + pxSocket->u.xTCP.xTCPWindow.ulOurSequenceNumber, + ( uint32_t ) pxSocket->u.xTCP.usInitMSS ); +} +/*-----------------------------------------------------------*/ + +/* + * Connecting sockets have a special state: eCONNECT_SYN. In this phase, + * the Ethernet address of the target will be found using ARP. In case the + * target IP address is not within the netmask, the hardware address of the + * gateway will be used. + */ +static BaseType_t prvTCPPrepareConnect( FreeRTOS_Socket_t *pxSocket ) +{ +TCPPacket_t *pxTCPPacket; +IPHeader_t *pxIPHeader; +eARPLookupResult_t eReturned; +uint32_t ulRemoteIP; +MACAddress_t xEthAddress; +BaseType_t xReturn = pdTRUE; +uint32_t ulInitialSequenceNumber = 0; + + #if( ipconfigHAS_PRINTF != 0 ) + { + /* Only necessary for nicer logging. */ + memset( xEthAddress.ucBytes, '\0', sizeof( xEthAddress.ucBytes ) ); + } + #endif /* ipconfigHAS_PRINTF != 0 */ + + ulRemoteIP = FreeRTOS_htonl( pxSocket->u.xTCP.ulRemoteIP ); + + /* Determine the ARP cache status for the requested IP address. */ + eReturned = eARPGetCacheEntry( &( ulRemoteIP ), &( xEthAddress ) ); + + switch( eReturned ) + { + case eARPCacheHit: /* An ARP table lookup found a valid entry. */ + break; /* We can now prepare the SYN packet. */ + case eARPCacheMiss: /* An ARP table lookup did not find a valid entry. */ + case eCantSendPacket: /* There is no IP address, or an ARP is still in progress. */ + default: + /* Count the number of times it couldn't find the ARP address. */ + pxSocket->u.xTCP.ucRepCount++; + + FreeRTOS_debug_printf( ( "ARP for %lxip (using %lxip): rc=%d %02X:%02X:%02X %02X:%02X:%02X\n", + pxSocket->u.xTCP.ulRemoteIP, + FreeRTOS_htonl( ulRemoteIP ), + eReturned, + xEthAddress.ucBytes[ 0 ], + xEthAddress.ucBytes[ 1 ], + xEthAddress.ucBytes[ 2 ], + xEthAddress.ucBytes[ 3 ], + xEthAddress.ucBytes[ 4 ], + xEthAddress.ucBytes[ 5 ] ) ); + + /* And issue a (new) ARP request */ + FreeRTOS_OutputARPRequest( ulRemoteIP ); + + xReturn = pdFALSE; + } + + if( xReturn != pdFALSE ) + { + /* Get a difficult-to-predict initial sequence number for this 4-tuple. */ + ulInitialSequenceNumber = ulApplicationGetNextSequenceNumber( *ipLOCAL_IP_ADDRESS_POINTER, + pxSocket->usLocalPort, + pxSocket->u.xTCP.ulRemoteIP, + pxSocket->u.xTCP.usRemotePort ); + + /* Check for a random number generation error. */ + if( 0 == ulInitialSequenceNumber ) + { + xReturn = pdFALSE; + } + } + + if( xReturn != pdFALSE ) + { + /* The MAC-address of the peer (or gateway) has been found, + now prepare the initial TCP packet and some fields in the socket. */ + pxTCPPacket = ( TCPPacket_t * )pxSocket->u.xTCP.xPacket.u.ucLastPacket; + pxIPHeader = &pxTCPPacket->xIPHeader; + + /* reset the retry counter to zero. */ + pxSocket->u.xTCP.ucRepCount = 0u; + + /* And remember that the connect/SYN data are prepared. */ + pxSocket->u.xTCP.bits.bConnPrepared = pdTRUE_UNSIGNED; + + /* Now that the Ethernet address is known, the initial packet can be + prepared. */ + memset( pxSocket->u.xTCP.xPacket.u.ucLastPacket, '\0', sizeof( pxSocket->u.xTCP.xPacket.u.ucLastPacket ) ); + + /* Write the Ethernet address in Source, because it will be swapped by + prvTCPReturnPacket(). */ + memcpy( &pxTCPPacket->xEthernetHeader.xSourceAddress, &xEthAddress, sizeof( xEthAddress ) ); + + /* 'ipIPv4_FRAME_TYPE' is already in network-byte-order. */ + pxTCPPacket->xEthernetHeader.usFrameType = ipIPv4_FRAME_TYPE; + + pxIPHeader->ucVersionHeaderLength = 0x45u; + pxIPHeader->usLength = FreeRTOS_htons( sizeof( TCPPacket_t ) - sizeof( pxTCPPacket->xEthernetHeader ) ); + pxIPHeader->ucTimeToLive = ( uint8_t ) ipconfigTCP_TIME_TO_LIVE; + + pxIPHeader->ucProtocol = ( uint8_t ) ipPROTOCOL_TCP; + + /* Addresses and ports will be stored swapped because prvTCPReturnPacket + will swap them back while replying. */ + pxIPHeader->ulDestinationIPAddress = *ipLOCAL_IP_ADDRESS_POINTER; + pxIPHeader->ulSourceIPAddress = FreeRTOS_htonl( pxSocket->u.xTCP.ulRemoteIP ); + + pxTCPPacket->xTCPHeader.usSourcePort = FreeRTOS_htons( pxSocket->u.xTCP.usRemotePort ); + pxTCPPacket->xTCPHeader.usDestinationPort = FreeRTOS_htons( pxSocket->usLocalPort ); + + /* We are actively connecting, so the peer's Initial Sequence Number (ISN) + isn't known yet. */ + pxSocket->u.xTCP.xTCPWindow.rx.ulCurrentSequenceNumber = 0ul; + + /* Start with ISN (Initial Sequence Number). */ + pxSocket->u.xTCP.xTCPWindow.ulOurSequenceNumber = ulInitialSequenceNumber; + + /* The TCP header size is 20 bytes, divided by 4 equals 5, which is put in + the high nibble of the TCP offset field. */ + pxTCPPacket->xTCPHeader.ucTCPOffset = 0x50u; + + /* Only set the SYN flag. */ + pxTCPPacket->xTCPHeader.ucTCPFlags = ipTCP_FLAG_SYN; + + /* Set the values of usInitMSS / usCurMSS for this socket. */ + prvSocketSetMSS( pxSocket ); + + /* For now this is also the advertised window size. */ + pxSocket->u.xTCP.ulRxCurWinSize = pxSocket->u.xTCP.usInitMSS; + + /* The initial sequence numbers at our side are known. Later + vTCPWindowInit() will be called to fill in the peer's sequence numbers, but + first wait for a SYN+ACK reply. */ + prvTCPCreateWindow( pxSocket ); + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +/* For logging and debugging: make a string showing the TCP flags +*/ +#if( ipconfigHAS_DEBUG_PRINTF != 0 ) + + static const char *prvTCPFlagMeaning( UBaseType_t xFlags) + { + static char retString[10]; + snprintf(retString, sizeof( retString ), "%c%c%c%c%c%c%c%c%c", + ( xFlags & ipTCP_FLAG_FIN ) ? 'F' : '.', /* 0x0001: No more data from sender */ + ( xFlags & ipTCP_FLAG_SYN ) ? 'S' : '.', /* 0x0002: Synchronize sequence numbers */ + ( xFlags & ipTCP_FLAG_RST ) ? 'R' : '.', /* 0x0004: Reset the connection */ + ( xFlags & ipTCP_FLAG_PSH ) ? 'P' : '.', /* 0x0008: Push function: please push buffered data to the recv application */ + ( xFlags & ipTCP_FLAG_ACK ) ? 'A' : '.', /* 0x0010: Acknowledgment field is significant */ + ( xFlags & ipTCP_FLAG_URG ) ? 'U' : '.', /* 0x0020: Urgent pointer field is significant */ + ( xFlags & ipTCP_FLAG_ECN ) ? 'E' : '.', /* 0x0040: ECN-Echo */ + ( xFlags & ipTCP_FLAG_CWR ) ? 'C' : '.', /* 0x0080: Congestion Window Reduced */ + ( xFlags & ipTCP_FLAG_NS ) ? 'N' : '.'); /* 0x0100: ECN-nonce concealment protection */ + return retString; + } + /*-----------------------------------------------------------*/ + +#endif /* ipconfigHAS_DEBUG_PRINTF */ + +/* + * Parse the TCP option(s) received, if present. It has already been verified + * that: ((pxTCPHeader->ucTCPOffset & 0xf0) > 0x50), meaning that the TP header + * is longer than the usual 20 (5 x 4) bytes. + */ +static void prvCheckOptions( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t *pxNetworkBuffer ) +{ +TCPPacket_t * pxTCPPacket; +TCPHeader_t * pxTCPHeader; +const unsigned char *pucPtr; +const unsigned char *pucLast; +TCPWindow_t *pxTCPWindow; +UBaseType_t uxNewMSS; + + pxTCPPacket = ( TCPPacket_t * ) ( pxNetworkBuffer->pucEthernetBuffer ); + pxTCPHeader = &pxTCPPacket->xTCPHeader; + + /* A character pointer to iterate through the option data */ + pucPtr = pxTCPHeader->ucOptdata; + pucLast = pucPtr + (((pxTCPHeader->ucTCPOffset >> 4) - 5) << 2); + pxTCPWindow = &pxSocket->u.xTCP.xTCPWindow; + + /* Validate options size calculation. */ + if( pucLast > ( pxNetworkBuffer->pucEthernetBuffer + pxNetworkBuffer->xDataLength ) ) + { + return; + } + + /* The comparison with pucLast is only necessary in case the option data are + corrupted, we don't like to run into invalid memory and crash. */ + while( pucPtr < pucLast ) + { + UBaseType_t xRemainingOptionsBytes = pucLast - pucPtr; + + if( pucPtr[ 0 ] == TCP_OPT_END ) + { + /* End of options. */ + break; + } + if( pucPtr[ 0 ] == TCP_OPT_NOOP) + { + /* NOP option, inserted to make the length a multiple of 4. */ + pucPtr++; + continue; + } + + /* Any other well-formed option must be at least two bytes: the option + type byte followed by a length byte. */ + if( xRemainingOptionsBytes < 2 ) + { + break; + } +#if( ipconfigUSE_TCP_WIN != 0 ) + else if( pucPtr[ 0 ] == TCP_OPT_WSOPT ) + { + /* Confirm that the option fits in the remaining buffer space. */ + if( ( xRemainingOptionsBytes < TCP_OPT_WSOPT_LEN ) || ( pucPtr[ 1 ] != TCP_OPT_WSOPT_LEN ) ) + { + break; + } + + pxSocket->u.xTCP.ucPeerWinScaleFactor = pucPtr[ 2 ]; + pxSocket->u.xTCP.bits.bWinScaling = pdTRUE_UNSIGNED; + pucPtr += TCP_OPT_WSOPT_LEN; + } +#endif /* ipconfigUSE_TCP_WIN */ + else if( pucPtr[ 0 ] == TCP_OPT_MSS ) + { + /* Confirm that the option fits in the remaining buffer space. */ + if( ( xRemainingOptionsBytes < TCP_OPT_MSS_LEN )|| ( pucPtr[ 1 ] != TCP_OPT_MSS_LEN ) ) + { + break; + } + + /* An MSS option with the correct option length. FreeRTOS_htons() + is not needed here because usChar2u16() already returns a host + endian number. */ + uxNewMSS = usChar2u16( pucPtr + 2 ); + + if( pxSocket->u.xTCP.usInitMSS != uxNewMSS ) + { + /* Perform a basic check on the the new MSS. */ + if( uxNewMSS == 0 ) + { + break; + } + + FreeRTOS_debug_printf( ( "MSS change %u -> %lu\n", pxSocket->u.xTCP.usInitMSS, uxNewMSS ) ); + } + + if( pxSocket->u.xTCP.usInitMSS > uxNewMSS ) + { + /* our MSS was bigger than the MSS of the other party: adapt it. */ + pxSocket->u.xTCP.bits.bMssChange = pdTRUE_UNSIGNED; + if( ( pxTCPWindow != NULL ) && ( pxSocket->u.xTCP.usCurMSS > uxNewMSS ) ) + { + /* The peer advertises a smaller MSS than this socket was + using. Use that as well. */ + FreeRTOS_debug_printf( ( "Change mss %d => %lu\n", pxSocket->u.xTCP.usCurMSS, uxNewMSS ) ); + pxSocket->u.xTCP.usCurMSS = ( uint16_t ) uxNewMSS; + } + pxTCPWindow->xSize.ulRxWindowLength = ( ( uint32_t ) uxNewMSS ) * ( pxTCPWindow->xSize.ulRxWindowLength / ( ( uint32_t ) uxNewMSS ) ); + pxTCPWindow->usMSSInit = ( uint16_t ) uxNewMSS; + pxTCPWindow->usMSS = ( uint16_t ) uxNewMSS; + pxSocket->u.xTCP.usInitMSS = ( uint16_t ) uxNewMSS; + pxSocket->u.xTCP.usCurMSS = ( uint16_t ) uxNewMSS; + } + + #if( ipconfigUSE_TCP_WIN != 1 ) + /* Without scaled windows, MSS is the only interesting option. */ + break; + #else + /* Or else we continue to check another option: selective ACK. */ + pucPtr += TCP_OPT_MSS_LEN; + #endif /* ipconfigUSE_TCP_WIN != 1 */ + } + else + { + /* All other options have a length field, so that we easily + can skip past them. */ + unsigned char len = pucPtr[ 1 ]; + if( ( len < 2 ) || ( len > xRemainingOptionsBytes ) ) + { + /* If the length field is too small or too big, the options are malformed. + Don't process them further. */ + break; + } + + #if( ipconfigUSE_TCP_WIN == 1 ) + { + /* Selective ACK: the peer has received a packet but it is missing earlier + packets. At least this packet does not need retransmission anymore + ulTCPWindowTxSack( ) takes care of this administration. */ + if( pucPtr[0] == TCP_OPT_SACK_A ) + { + len -= 2; + pucPtr += 2; + + while( len >= 8 ) + { + uint32_t ulFirst = ulChar2u32( pucPtr ); + uint32_t ulLast = ulChar2u32( pucPtr + 4 ); + uint32_t ulCount = ulTCPWindowTxSack( &pxSocket->u.xTCP.xTCPWindow, ulFirst, ulLast ); + /* ulTCPWindowTxSack( ) returns the number of bytes which have been acked + starting from the head position. + Advance the tail pointer in txStream. */ + if( ( pxSocket->u.xTCP.txStream != NULL ) && ( ulCount > 0 ) ) + { + /* Just advancing the tail index, 'ulCount' bytes have been confirmed. */ + uxStreamBufferGet( pxSocket->u.xTCP.txStream, 0, NULL, ( size_t ) ulCount, pdFALSE ); + pxSocket->xEventBits |= eSOCKET_SEND; + + #if ipconfigSUPPORT_SELECT_FUNCTION == 1 + { + if( pxSocket->xSelectBits & eSELECT_WRITE ) + { + /* The field 'xEventBits' is used to store regular socket events (at most 8), + as well as 'select events', which will be left-shifted */ + pxSocket->xEventBits |= ( eSELECT_WRITE << SOCKET_EVENT_BIT_COUNT ); + } + } + #endif + + /* In case the socket owner has installed an OnSent handler, + call it now. */ + #if( ipconfigUSE_CALLBACKS == 1 ) + { + if( ipconfigIS_VALID_PROG_ADDRESS( pxSocket->u.xTCP.pxHandleSent ) ) + { + pxSocket->u.xTCP.pxHandleSent( (Socket_t *)pxSocket, ulCount ); + } + } + #endif /* ipconfigUSE_CALLBACKS == 1 */ + } + pucPtr += 8; + len -= 8; + } + /* len should be 0 by now. */ + } + } + #endif /* ipconfigUSE_TCP_WIN == 1 */ + + pucPtr += len; + } + } +} +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN != 0 ) + + static uint8_t prvWinScaleFactor( FreeRTOS_Socket_t *pxSocket ) + { + size_t uxWinSize; + uint8_t ucFactor; + + /* 'xTCP.uxRxWinSize' is the size of the reception window in units of MSS. */ + uxWinSize = pxSocket->u.xTCP.uxRxWinSize * ( size_t ) pxSocket->u.xTCP.usInitMSS; + ucFactor = 0u; + while( uxWinSize > 0xfffful ) + { + /* Divide by two and increase the binary factor by 1. */ + uxWinSize >>= 1; + ucFactor++; + } + + FreeRTOS_debug_printf( ( "prvWinScaleFactor: uxRxWinSize %lu MSS %lu Factor %u\n", + pxSocket->u.xTCP.uxRxWinSize, + pxSocket->u.xTCP.usInitMSS, + ucFactor ) ); + + return ucFactor; + } + +#endif +/*-----------------------------------------------------------*/ + +/* + * When opening a TCP connection, while SYN's are being sent, the parties may + * communicate what MSS (Maximum Segment Size) they intend to use. MSS is the + * nett size of the payload, always smaller than MTU. +*/ +static UBaseType_t prvSetSynAckOptions( FreeRTOS_Socket_t *pxSocket, TCPPacket_t * pxTCPPacket ) +{ +TCPHeader_t *pxTCPHeader = &pxTCPPacket->xTCPHeader; +uint16_t usMSS = pxSocket->u.xTCP.usInitMSS; +UBaseType_t uxOptionsLength; + + /* We send out the TCP Maximum Segment Size option with our SYN[+ACK]. */ + + pxTCPHeader->ucOptdata[ 0 ] = ( uint8_t ) TCP_OPT_MSS; + pxTCPHeader->ucOptdata[ 1 ] = ( uint8_t ) TCP_OPT_MSS_LEN; + pxTCPHeader->ucOptdata[ 2 ] = ( uint8_t ) ( usMSS >> 8 ); + pxTCPHeader->ucOptdata[ 3 ] = ( uint8_t ) ( usMSS & 0xffu ); + + #if( ipconfigUSE_TCP_WIN != 0 ) + { + pxSocket->u.xTCP.ucMyWinScaleFactor = prvWinScaleFactor( pxSocket ); + + pxTCPHeader->ucOptdata[ 4 ] = TCP_OPT_NOOP; + pxTCPHeader->ucOptdata[ 5 ] = ( uint8_t ) ( TCP_OPT_WSOPT ); + pxTCPHeader->ucOptdata[ 6 ] = ( uint8_t ) ( TCP_OPT_WSOPT_LEN ); + pxTCPHeader->ucOptdata[ 7 ] = ( uint8_t ) pxSocket->u.xTCP.ucMyWinScaleFactor; + uxOptionsLength = 8u; + } + #else + { + uxOptionsLength = 4u; + } + #endif + + #if( ipconfigUSE_TCP_WIN == 0 ) + { + return uxOptionsLength; + } + #else + { + pxTCPHeader->ucOptdata[ uxOptionsLength + 0 ] = TCP_OPT_NOOP; + pxTCPHeader->ucOptdata[ uxOptionsLength + 1 ] = TCP_OPT_NOOP; + pxTCPHeader->ucOptdata[ uxOptionsLength + 2 ] = TCP_OPT_SACK_P; /* 4: Sack-Permitted Option. */ + pxTCPHeader->ucOptdata[ uxOptionsLength + 3 ] = 2; /* 2: length of this option. */ + uxOptionsLength += 4u; + + return uxOptionsLength; /* bytes, not words. */ + } + #endif /* ipconfigUSE_TCP_WIN == 0 */ +} + +/* + * For anti-hanging protection and TCP keep-alive messages. Called in two + * places: after receiving a packet and after a state change. The socket's + * alive timer may be reset. + */ +static void prvTCPTouchSocket( FreeRTOS_Socket_t *pxSocket ) +{ + #if( ipconfigTCP_HANG_PROTECTION == 1 ) + { + pxSocket->u.xTCP.xLastActTime = xTaskGetTickCount( ); + } + #endif + + #if( ipconfigTCP_KEEP_ALIVE == 1 ) + { + pxSocket->u.xTCP.bits.bWaitKeepAlive = pdFALSE_UNSIGNED; + pxSocket->u.xTCP.bits.bSendKeepAlive = pdFALSE_UNSIGNED; + pxSocket->u.xTCP.ucKeepRepCount = 0u; + pxSocket->u.xTCP.xLastAliveTime = xTaskGetTickCount(); + } + #endif + + ( void ) pxSocket; +} +/*-----------------------------------------------------------*/ + +/* + * Changing to a new state. Centralised here to do specific actions such as + * resetting the alive timer, calling the user's OnConnect handler to notify + * that a socket has got (dis)connected, and setting bit to unblock a call to + * FreeRTOS_select() + */ +void vTCPStateChange( FreeRTOS_Socket_t *pxSocket, enum eTCP_STATE eTCPState ) +{ +FreeRTOS_Socket_t *xParent = NULL; +BaseType_t bBefore = ( BaseType_t ) NOW_CONNECTED( pxSocket->u.xTCP.ucTCPState ); /* Was it connected ? */ +BaseType_t bAfter = ( BaseType_t ) NOW_CONNECTED( eTCPState ); /* Is it connected now ? */ +#if( ipconfigHAS_DEBUG_PRINTF != 0 ) + BaseType_t xPreviousState = ( BaseType_t ) pxSocket->u.xTCP.ucTCPState; +#endif +#if( ipconfigUSE_CALLBACKS == 1 ) + FreeRTOS_Socket_t *xConnected = NULL; +#endif + + /* Has the connected status changed? */ + if( bBefore != bAfter ) + { + /* Is the socket connected now ? */ + if( bAfter != pdFALSE ) + { + /* if bPassQueued is true, this socket is an orphan until it gets connected. */ + if( pxSocket->u.xTCP.bits.bPassQueued != pdFALSE_UNSIGNED ) + { + /* Now that it is connected, find it's parent. */ + if( pxSocket->u.xTCP.bits.bReuseSocket != pdFALSE_UNSIGNED ) + { + xParent = pxSocket; + } + else + { + xParent = pxSocket->u.xTCP.pxPeerSocket; + configASSERT( xParent != NULL ); + } + if( xParent != NULL ) + { + if( xParent->u.xTCP.pxPeerSocket == NULL ) + { + xParent->u.xTCP.pxPeerSocket = pxSocket; + } + + xParent->xEventBits |= eSOCKET_ACCEPT; + + #if( ipconfigSUPPORT_SELECT_FUNCTION == 1 ) + { + /* Library support FreeRTOS_select(). Receiving a new + connection is being translated as a READ event. */ + if( ( xParent->xSelectBits & eSELECT_READ ) != 0 ) + { + xParent->xEventBits |= ( eSELECT_READ << SOCKET_EVENT_BIT_COUNT ); + } + } + #endif + + #if( ipconfigUSE_CALLBACKS == 1 ) + { + if( ( ipconfigIS_VALID_PROG_ADDRESS( xParent->u.xTCP.pxHandleConnected ) != pdFALSE ) && + ( xParent->u.xTCP.bits.bReuseSocket == pdFALSE_UNSIGNED ) ) + { + /* The listening socket does not become connected itself, in stead + a child socket is created. + Postpone a call the OnConnect event until the end of this function. */ + xConnected = xParent; + } + } + #endif + } + + /* Don't need to access the parent socket anymore, so the + reference 'pxPeerSocket' may be cleared. */ + pxSocket->u.xTCP.pxPeerSocket = NULL; + pxSocket->u.xTCP.bits.bPassQueued = pdFALSE_UNSIGNED; + + /* When true, this socket may be returned in a call to accept(). */ + pxSocket->u.xTCP.bits.bPassAccept = pdTRUE_UNSIGNED; + } + else + { + pxSocket->xEventBits |= eSOCKET_CONNECT; + + #if( ipconfigSUPPORT_SELECT_FUNCTION == 1 ) + { + if( pxSocket->xSelectBits & eSELECT_WRITE ) + { + pxSocket->xEventBits |= ( eSELECT_WRITE << SOCKET_EVENT_BIT_COUNT ); + } + } + #endif + } + } + else /* bAfter == pdFALSE, connection is closed. */ + { + /* Notify/wake-up the socket-owner by setting a semaphore. */ + pxSocket->xEventBits |= eSOCKET_CLOSED; + + #if( ipconfigSUPPORT_SELECT_FUNCTION == 1 ) + { + if( ( pxSocket->xSelectBits & eSELECT_EXCEPT ) != 0 ) + { + pxSocket->xEventBits |= ( eSELECT_EXCEPT << SOCKET_EVENT_BIT_COUNT ); + } + } + #endif + } + #if( ipconfigUSE_CALLBACKS == 1 ) + { + if( ( ipconfigIS_VALID_PROG_ADDRESS( pxSocket->u.xTCP.pxHandleConnected ) != pdFALSE ) && ( xConnected == NULL ) ) + { + /* The 'connected' state has changed, call the user handler. */ + xConnected = pxSocket; + } + } + #endif /* ipconfigUSE_CALLBACKS */ + + if( prvTCPSocketIsActive( ( UBaseType_t ) pxSocket->u.xTCP.ucTCPState ) == pdFALSE ) + { + /* Now the socket isn't in an active state anymore so it + won't need further attention of the IP-task. + Setting time-out to zero means that the socket won't get checked during + timer events. */ + pxSocket->u.xTCP.usTimeout = 0u; + } + } + else + { + if( eTCPState == eCLOSED ) + { + /* Socket goes to status eCLOSED because of a RST. + When nobody owns the socket yet, delete it. */ + if( ( pxSocket->u.xTCP.bits.bPassQueued != pdFALSE_UNSIGNED ) || + ( pxSocket->u.xTCP.bits.bPassAccept != pdFALSE_UNSIGNED ) ) + { + FreeRTOS_debug_printf( ( "vTCPStateChange: Closing socket\n" ) ); + if( pxSocket->u.xTCP.bits.bReuseSocket == pdFALSE_UNSIGNED ) + { + FreeRTOS_closesocket( pxSocket ); + } + } + } + } + + /* Fill in the new state. */ + pxSocket->u.xTCP.ucTCPState = ( uint8_t ) eTCPState; + + /* touch the alive timers because moving to another state. */ + prvTCPTouchSocket( pxSocket ); + + #if( ipconfigHAS_DEBUG_PRINTF == 1 ) + { + if( ( xTCPWindowLoggingLevel >= 0 ) && ( ipconfigTCP_MAY_LOG_PORT( pxSocket->usLocalPort ) != pdFALSE ) ) + FreeRTOS_debug_printf( ( "Socket %d -> %lxip:%u State %s->%s\n", + pxSocket->usLocalPort, + pxSocket->u.xTCP.ulRemoteIP, + pxSocket->u.xTCP.usRemotePort, + FreeRTOS_GetTCPStateName( ( UBaseType_t ) xPreviousState ), + FreeRTOS_GetTCPStateName( ( UBaseType_t ) eTCPState ) ) ); + } + #endif /* ipconfigHAS_DEBUG_PRINTF */ + + #if( ipconfigUSE_CALLBACKS == 1 ) + { + if( xConnected != NULL ) + { + /* The 'connected' state has changed, call the OnConnect handler of the parent. */ + xConnected->u.xTCP.pxHandleConnected( ( Socket_t * ) xConnected, bAfter ); + } + } + #endif + if( xParent != NULL ) + { + vSocketWakeUpUser( xParent ); + } +} +/*-----------------------------------------------------------*/ + +static NetworkBufferDescriptor_t *prvTCPBufferResize( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t *pxNetworkBuffer, + int32_t lDataLen, UBaseType_t uxOptionsLength ) +{ +NetworkBufferDescriptor_t *pxReturn; +int32_t lNeeded; +BaseType_t xResize; + + if( xBufferAllocFixedSize != pdFALSE ) + { + /* Network buffers are created with a fixed size and can hold the largest + MTU. */ + lNeeded = ( int32_t ) ipTOTAL_ETHERNET_FRAME_SIZE; + /* and therefore, the buffer won't be too small. + Only ask for a new network buffer in case none was supplied. */ + xResize = ( pxNetworkBuffer == NULL ); + } + else + { + /* Network buffers are created with a variable size. See if it must + grow. */ + lNeeded = FreeRTOS_max_int32( ( int32_t ) sizeof( pxSocket->u.xTCP.xPacket.u.ucLastPacket ), + ( int32_t ) ( ipSIZE_OF_ETH_HEADER + ipSIZE_OF_IPv4_HEADER + ipSIZE_OF_TCP_HEADER + uxOptionsLength ) + lDataLen ); + /* In case we were called from a TCP timer event, a buffer must be + created. Otherwise, test 'xDataLength' of the provided buffer. */ + xResize = ( pxNetworkBuffer == NULL ) || ( pxNetworkBuffer->xDataLength < (size_t)lNeeded ); + } + + if( xResize != pdFALSE ) + { + /* The caller didn't provide a network buffer or the provided buffer is + too small. As we must send-out a data packet, a buffer will be created + here. */ + pxReturn = pxGetNetworkBufferWithDescriptor( ( uint32_t ) lNeeded, 0u ); + + if( pxReturn != NULL ) + { + /* Set the actual packet size, in case the returned buffer is larger. */ + pxReturn->xDataLength = lNeeded; + + /* Copy the existing data to the new created buffer. */ + if( pxNetworkBuffer ) + { + /* Either from the previous buffer... */ + memcpy( pxReturn->pucEthernetBuffer, pxNetworkBuffer->pucEthernetBuffer, pxNetworkBuffer->xDataLength ); + + /* ...and release it. */ + vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ); + } + else + { + /* Or from the socket field 'xTCP.xPacket'. */ + memcpy( pxReturn->pucEthernetBuffer, pxSocket->u.xTCP.xPacket.u.ucLastPacket, sizeof( pxSocket->u.xTCP.xPacket.u.ucLastPacket ) ); + } + } + } + else + { + /* xResize is false, the network buffer provided was big enough. */ + pxReturn = pxNetworkBuffer; + + /* Thanks to Andrey Ivanov from swissEmbedded for reporting that the + xDataLength member must get the correct length too! */ + pxNetworkBuffer->xDataLength = ( size_t ) ( ipSIZE_OF_ETH_HEADER + ipSIZE_OF_IPv4_HEADER + ipSIZE_OF_TCP_HEADER + uxOptionsLength ) + ( size_t ) lDataLen; + } + + return pxReturn; +} +/*-----------------------------------------------------------*/ + +/* + * Prepare an outgoing message, in case anything has to be sent. + */ +static int32_t prvTCPPrepareSend( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t **ppxNetworkBuffer, UBaseType_t uxOptionsLength ) +{ +int32_t lDataLen; +uint8_t *pucEthernetBuffer, *pucSendData; +TCPPacket_t *pxTCPPacket; +size_t uxOffset; +uint32_t ulDataGot, ulDistance; +TCPWindow_t *pxTCPWindow; +NetworkBufferDescriptor_t *pxNewBuffer; +int32_t lStreamPos; + + if( ( *ppxNetworkBuffer ) != NULL ) + { + /* A network buffer descriptor was already supplied */ + pucEthernetBuffer = ( *ppxNetworkBuffer )->pucEthernetBuffer; + } + else + { + /* For now let it point to the last packet header */ + pucEthernetBuffer = pxSocket->u.xTCP.xPacket.u.ucLastPacket; + } + + pxTCPPacket = ( TCPPacket_t * ) ( pucEthernetBuffer ); + pxTCPWindow = &pxSocket->u.xTCP.xTCPWindow; + lDataLen = 0; + lStreamPos = 0; + pxTCPPacket->xTCPHeader.ucTCPFlags |= ipTCP_FLAG_ACK; + + if( pxSocket->u.xTCP.txStream != NULL ) + { + /* ulTCPWindowTxGet will return the amount of data which may be sent + along with the position in the txStream. + Why check for MSS > 1 ? + Because some TCP-stacks (like uIP) use it for flow-control. */ + if( pxSocket->u.xTCP.usCurMSS > 1u ) + { + lDataLen = ( int32_t ) ulTCPWindowTxGet( pxTCPWindow, pxSocket->u.xTCP.ulWindowSize, &lStreamPos ); + } + + if( lDataLen > 0 ) + { + /* Check if the current network buffer is big enough, if not, + resize it. */ + pxNewBuffer = prvTCPBufferResize( pxSocket, *ppxNetworkBuffer, lDataLen, uxOptionsLength ); + + if( pxNewBuffer != NULL ) + { + *ppxNetworkBuffer = pxNewBuffer; + pucEthernetBuffer = pxNewBuffer->pucEthernetBuffer; + pxTCPPacket = ( TCPPacket_t * ) ( pucEthernetBuffer ); + + pucSendData = pucEthernetBuffer + ipSIZE_OF_ETH_HEADER + ipSIZE_OF_IPv4_HEADER + ipSIZE_OF_TCP_HEADER + uxOptionsLength; + + /* Translate the position in txStream to an offset from the tail + marker. */ + uxOffset = uxStreamBufferDistance( pxSocket->u.xTCP.txStream, pxSocket->u.xTCP.txStream->uxTail, ( size_t ) lStreamPos ); + + /* Here data is copied from the txStream in 'peek' mode. Only + when the packets are acked, the tail marker will be updated. */ + ulDataGot = ( uint32_t ) uxStreamBufferGet( pxSocket->u.xTCP.txStream, uxOffset, pucSendData, ( size_t ) lDataLen, pdTRUE ); + + #if( ipconfigHAS_DEBUG_PRINTF != 0 ) + { + if( ulDataGot != ( uint32_t ) lDataLen ) + { + FreeRTOS_debug_printf( ( "uxStreamBufferGet: pos %lu offs %lu only %lu != %lu\n", + lStreamPos, uxOffset, ulDataGot, lDataLen ) ); + } + } + #endif + + /* If the owner of the socket requests a closure, add the FIN + flag to the last packet. */ + if( ( pxSocket->u.xTCP.bits.bCloseRequested != pdFALSE_UNSIGNED ) && ( pxSocket->u.xTCP.bits.bFinSent == pdFALSE_UNSIGNED ) ) + { + ulDistance = ( uint32_t ) uxStreamBufferDistance( pxSocket->u.xTCP.txStream, ( size_t ) lStreamPos, pxSocket->u.xTCP.txStream->uxHead ); + + if( ulDistance == ulDataGot ) + { + #if (ipconfigHAS_DEBUG_PRINTF == 1) + { + /* the order of volatile accesses is undefined + so such workaround */ + size_t uxHead = pxSocket->u.xTCP.txStream->uxHead; + size_t uxMid = pxSocket->u.xTCP.txStream->uxMid; + size_t uxTail = pxSocket->u.xTCP.txStream->uxTail; + + FreeRTOS_debug_printf( ( "CheckClose %lu <= %lu (%lu <= %lu <= %lu)\n", ulDataGot, ulDistance, + uxTail, uxMid, uxHead ) ); + } + #endif + /* Although the socket sends a FIN, it will stay in + ESTABLISHED until all current data has been received or + delivered. */ + pxTCPPacket->xTCPHeader.ucTCPFlags |= ipTCP_FLAG_FIN; + pxTCPWindow->tx.ulFINSequenceNumber = pxTCPWindow->ulOurSequenceNumber + ( uint32_t ) lDataLen; + pxSocket->u.xTCP.bits.bFinSent = pdTRUE_UNSIGNED; + } + } + } + else + { + lDataLen = -1; + } + } + } + + if( ( lDataLen >= 0 ) && ( pxSocket->u.xTCP.ucTCPState == eESTABLISHED ) ) + { + /* See if the socket owner wants to shutdown this connection. */ + if( ( pxSocket->u.xTCP.bits.bUserShutdown != pdFALSE_UNSIGNED ) && + ( xTCPWindowTxDone( pxTCPWindow ) != pdFALSE ) ) + { + pxSocket->u.xTCP.bits.bUserShutdown = pdFALSE_UNSIGNED; + pxTCPPacket->xTCPHeader.ucTCPFlags |= ipTCP_FLAG_FIN; + pxSocket->u.xTCP.bits.bFinSent = pdTRUE_UNSIGNED; + pxSocket->u.xTCP.bits.bWinChange = pdTRUE_UNSIGNED; + pxTCPWindow->tx.ulFINSequenceNumber = pxTCPWindow->tx.ulCurrentSequenceNumber; + vTCPStateChange( pxSocket, eFIN_WAIT_1 ); + } + + #if( ipconfigTCP_KEEP_ALIVE != 0 ) + { + if( pxSocket->u.xTCP.ucKeepRepCount > 3u ) + { + FreeRTOS_debug_printf( ( "keep-alive: giving up %lxip:%u\n", + pxSocket->u.xTCP.ulRemoteIP, /* IP address of remote machine. */ + pxSocket->u.xTCP.usRemotePort ) ); /* Port on remote machine. */ + vTCPStateChange( pxSocket, eCLOSE_WAIT ); + lDataLen = -1; + } + if( ( lDataLen == 0 ) && ( pxSocket->u.xTCP.bits.bWinChange == pdFALSE_UNSIGNED ) ) + { + /* If there is no data to be sent, and no window-update message, + we might want to send a keep-alive message. */ + TickType_t xAge = xTaskGetTickCount( ) - pxSocket->u.xTCP.xLastAliveTime; + TickType_t xMax; + xMax = ( ( TickType_t ) ipconfigTCP_KEEP_ALIVE_INTERVAL * configTICK_RATE_HZ ); + if( pxSocket->u.xTCP.ucKeepRepCount ) + { + xMax = ( 3u * configTICK_RATE_HZ ); + } + if( xAge > xMax ) + { + pxSocket->u.xTCP.xLastAliveTime = xTaskGetTickCount( ); + if( xTCPWindowLoggingLevel ) + FreeRTOS_debug_printf( ( "keep-alive: %lxip:%u count %u\n", + pxSocket->u.xTCP.ulRemoteIP, + pxSocket->u.xTCP.usRemotePort, + pxSocket->u.xTCP.ucKeepRepCount ) ); + pxSocket->u.xTCP.bits.bSendKeepAlive = pdTRUE_UNSIGNED; + pxSocket->u.xTCP.usTimeout = ( ( uint16_t ) pdMS_TO_TICKS( 2500 ) ); + pxSocket->u.xTCP.ucKeepRepCount++; + } + } + } + #endif /* ipconfigTCP_KEEP_ALIVE */ + } + + /* Anything to send, a change of the advertised window size, or maybe send a + keep-alive message? */ + if( ( lDataLen > 0 ) || + ( pxSocket->u.xTCP.bits.bWinChange != pdFALSE_UNSIGNED ) || + ( pxSocket->u.xTCP.bits.bSendKeepAlive != pdFALSE_UNSIGNED ) ) + { + pxTCPPacket->xTCPHeader.ucTCPFlags &= ( ( uint8_t ) ~ipTCP_FLAG_PSH ); + pxTCPPacket->xTCPHeader.ucTCPOffset = ( uint8_t )( ( ipSIZE_OF_TCP_HEADER + uxOptionsLength ) << 2 ); + + pxTCPPacket->xTCPHeader.ucTCPFlags |= ( uint8_t ) ipTCP_FLAG_ACK; + + if( lDataLen != 0l ) + { + pxTCPPacket->xTCPHeader.ucTCPFlags |= ( uint8_t ) ipTCP_FLAG_PSH; + } + + lDataLen += ( int32_t ) ( ipSIZE_OF_IPv4_HEADER + ipSIZE_OF_TCP_HEADER + uxOptionsLength ); + } + + return lDataLen; +} +/*-----------------------------------------------------------*/ + +/* + * Calculate after how much time this socket needs to be checked again. + */ +static TickType_t prvTCPNextTimeout ( FreeRTOS_Socket_t *pxSocket ) +{ +TickType_t ulDelayMs = ( TickType_t ) tcpMAXIMUM_TCP_WAKEUP_TIME_MS; + + if( pxSocket->u.xTCP.ucTCPState == eCONNECT_SYN ) + { + /* The socket is actively connecting to a peer. */ + if( pxSocket->u.xTCP.bits.bConnPrepared ) + { + /* Ethernet address has been found, use progressive timeout for + active connect(). */ + if( pxSocket->u.xTCP.ucRepCount < 3u ) + { + ulDelayMs = ( 3000UL << ( pxSocket->u.xTCP.ucRepCount - 1u ) ); + } + else + { + ulDelayMs = 11000UL; + } + } + else + { + /* Still in the ARP phase: check every half second. */ + ulDelayMs = 500UL; + } + + FreeRTOS_debug_printf( ( "Connect[%lxip:%u]: next timeout %u: %lu ms\n", + pxSocket->u.xTCP.ulRemoteIP, pxSocket->u.xTCP.usRemotePort, + pxSocket->u.xTCP.ucRepCount, ulDelayMs ) ); + pxSocket->u.xTCP.usTimeout = ( uint16_t )pdMS_TO_MIN_TICKS( ulDelayMs ); + } + else if( pxSocket->u.xTCP.usTimeout == 0u ) + { + /* Let the sliding window mechanism decide what time-out is appropriate. */ + BaseType_t xResult = xTCPWindowTxHasData( &pxSocket->u.xTCP.xTCPWindow, pxSocket->u.xTCP.ulWindowSize, &ulDelayMs ); + if( ulDelayMs == 0u ) + { + if( xResult != ( BaseType_t )0 ) + { + ulDelayMs = 1UL; + } + else + { + ulDelayMs = tcpMAXIMUM_TCP_WAKEUP_TIME_MS; + } + } + else + { + /* ulDelayMs contains the time to wait before a re-transmission. */ + } + pxSocket->u.xTCP.usTimeout = ( uint16_t )pdMS_TO_MIN_TICKS( ulDelayMs ); + } + else + { + /* field '.usTimeout' has already been set (by the + keep-alive/delayed-ACK mechanism). */ + } + + /* Return the number of clock ticks before the timer expires. */ + return ( TickType_t ) pxSocket->u.xTCP.usTimeout; +} +/*-----------------------------------------------------------*/ + +static void prvTCPAddTxData( FreeRTOS_Socket_t *pxSocket ) +{ +int32_t lCount, lLength; + + /* A txStream has been created already, see if the socket has new data for + the sliding window. + + uxStreamBufferMidSpace() returns the distance between rxHead and rxMid. It contains new + Tx data which has not been passed to the sliding window yet. The oldest + data not-yet-confirmed can be found at rxTail. */ + lLength = ( int32_t ) uxStreamBufferMidSpace( pxSocket->u.xTCP.txStream ); + + if( lLength > 0 ) + { + /* All data between txMid and rxHead will now be passed to the sliding + window manager, so it can start transmitting them. + + Hand over the new data to the sliding window handler. It will be + split-up in chunks of 1460 bytes each (or less, depending on + ipconfigTCP_MSS). */ + lCount = lTCPWindowTxAdd( &pxSocket->u.xTCP.xTCPWindow, + ( uint32_t ) lLength, + ( int32_t ) pxSocket->u.xTCP.txStream->uxMid, + ( int32_t ) pxSocket->u.xTCP.txStream->LENGTH ); + + /* Move the rxMid pointer forward up to rxHead. */ + if( lCount > 0 ) + { + vStreamBufferMoveMid( pxSocket->u.xTCP.txStream, ( size_t ) lCount ); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * prvTCPHandleFin() will be called to handle socket closure + * The Closure starts when either a FIN has been received and accepted, + * Or when the socket has sent a FIN flag to the peer + * Before being called, it has been checked that both reception and transmission + * are complete. + */ +static BaseType_t prvTCPHandleFin( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t *pxNetworkBuffer ) +{ +TCPPacket_t *pxTCPPacket = ( TCPPacket_t * ) ( pxNetworkBuffer->pucEthernetBuffer ); +TCPHeader_t *pxTCPHeader = &pxTCPPacket->xTCPHeader; +uint8_t ucTCPFlags = pxTCPHeader->ucTCPFlags; +TCPWindow_t *pxTCPWindow = &pxSocket->u.xTCP.xTCPWindow; +BaseType_t xSendLength = 0; +uint32_t ulAckNr = FreeRTOS_ntohl( pxTCPHeader->ulAckNr ); + + if( ( ucTCPFlags & ipTCP_FLAG_FIN ) != 0u ) + { + pxTCPWindow->rx.ulCurrentSequenceNumber = pxTCPWindow->rx.ulFINSequenceNumber + 1u; + } + if( pxSocket->u.xTCP.bits.bFinSent == pdFALSE_UNSIGNED ) + { + /* We haven't yet replied with a FIN, do so now. */ + pxTCPWindow->tx.ulFINSequenceNumber = pxTCPWindow->tx.ulCurrentSequenceNumber; + pxSocket->u.xTCP.bits.bFinSent = pdTRUE_UNSIGNED; + } + else + { + /* We did send a FIN already, see if it's ACK'd. */ + if( ulAckNr == pxTCPWindow->tx.ulFINSequenceNumber + 1u ) + { + pxSocket->u.xTCP.bits.bFinAcked = pdTRUE_UNSIGNED; + } + } + + if( pxSocket->u.xTCP.bits.bFinAcked == pdFALSE_UNSIGNED ) + { + pxTCPWindow->tx.ulCurrentSequenceNumber = pxTCPWindow->tx.ulFINSequenceNumber; + pxTCPHeader->ucTCPFlags = ipTCP_FLAG_ACK | ipTCP_FLAG_FIN; + + /* And wait for the final ACK. */ + vTCPStateChange( pxSocket, eLAST_ACK ); + } + else + { + /* Our FIN has been ACK'd, the outgoing sequence number is now fixed. */ + pxTCPWindow->tx.ulCurrentSequenceNumber = pxTCPWindow->tx.ulFINSequenceNumber + 1u; + if( pxSocket->u.xTCP.bits.bFinRecv == pdFALSE_UNSIGNED ) + { + /* We have sent out a FIN but the peer hasn't replied with a FIN + yet. Do nothing for the moment. */ + pxTCPHeader->ucTCPFlags = 0u; + } + else + { + if( pxSocket->u.xTCP.bits.bFinLast == pdFALSE_UNSIGNED ) + { + /* This is the third of the three-way hand shake: the last + ACK. */ + pxTCPHeader->ucTCPFlags = ipTCP_FLAG_ACK; + } + else + { + /* The other party started the closure, so we just wait for the + last ACK. */ + pxTCPHeader->ucTCPFlags = 0u; + } + + /* And wait for the user to close this socket. */ + vTCPStateChange( pxSocket, eCLOSE_WAIT ); + } + } + + pxTCPWindow->ulOurSequenceNumber = pxTCPWindow->tx.ulCurrentSequenceNumber; + + if( pxTCPHeader->ucTCPFlags != 0u ) + { + xSendLength = ( BaseType_t ) ( ipSIZE_OF_IPv4_HEADER + ipSIZE_OF_TCP_HEADER + pxTCPWindow->ucOptionLength ); + } + + pxTCPHeader->ucTCPOffset = ( uint8_t ) ( ( ipSIZE_OF_TCP_HEADER + pxTCPWindow->ucOptionLength ) << 2 ); + + if( xTCPWindowLoggingLevel != 0 ) + { + FreeRTOS_debug_printf( ( "TCP: send FIN+ACK (ack %lu, cur/nxt %lu/%lu) ourSeqNr %lu | Rx %lu\n", + ulAckNr - pxTCPWindow->tx.ulFirstSequenceNumber, + pxTCPWindow->tx.ulCurrentSequenceNumber - pxTCPWindow->tx.ulFirstSequenceNumber, + pxTCPWindow->ulNextTxSequenceNumber - pxTCPWindow->tx.ulFirstSequenceNumber, + pxTCPWindow->ulOurSequenceNumber - pxTCPWindow->tx.ulFirstSequenceNumber, + pxTCPWindow->rx.ulCurrentSequenceNumber - pxTCPWindow->rx.ulFirstSequenceNumber ) ); + } + + return xSendLength; +} +/*-----------------------------------------------------------*/ + +/* + * prvCheckRxData(): called from prvTCPHandleState() + * + * The first thing that will be done is find the TCP payload data + * and check the length of this data. + */ +static BaseType_t prvCheckRxData( NetworkBufferDescriptor_t *pxNetworkBuffer, uint8_t **ppucRecvData ) +{ +TCPPacket_t *pxTCPPacket = ( TCPPacket_t * ) ( pxNetworkBuffer->pucEthernetBuffer ); +TCPHeader_t *pxTCPHeader = &( pxTCPPacket->xTCPHeader ); +int32_t lLength, lTCPHeaderLength, lReceiveLength, lUrgentLength; + + /* Determine the length and the offset of the user-data sent to this + node. + + The size of the TCP header is given in a multiple of 4-byte words (single + byte, needs no ntoh() translation). A shift-right 2: is the same as + (offset >> 4) * 4. */ + lTCPHeaderLength = ( BaseType_t ) ( ( pxTCPHeader->ucTCPOffset & VALID_BITS_IN_TCP_OFFSET_BYTE ) >> 2 ); + + /* Let pucRecvData point to the first byte received. */ + *ppucRecvData = pxNetworkBuffer->pucEthernetBuffer + ipSIZE_OF_ETH_HEADER + ipSIZE_OF_IPv4_HEADER + lTCPHeaderLength; + + /* Calculate lReceiveLength - the length of the TCP data received. This is + equal to the total packet length minus: + ( LinkLayer length (14) + IP header length (20) + size of TCP header(20 +) ).*/ + lReceiveLength = ( ( int32_t ) pxNetworkBuffer->xDataLength ) - ( int32_t ) ipSIZE_OF_ETH_HEADER; + lLength = ( int32_t )FreeRTOS_htons( pxTCPPacket->xIPHeader.usLength ); + + if( lReceiveLength > lLength ) + { + /* More bytes were received than the reported length, often because of + padding bytes at the end. */ + lReceiveLength = lLength; + } + + /* Subtract the size of the TCP and IP headers and the actual data size is + known. */ + if( lReceiveLength > ( lTCPHeaderLength + ( int32_t ) ipSIZE_OF_IPv4_HEADER ) ) + { + lReceiveLength -= ( lTCPHeaderLength + ( int32_t ) ipSIZE_OF_IPv4_HEADER ); + } + else + { + lReceiveLength = 0; + } + + /* Urgent Pointer: + This field communicates the current value of the urgent pointer as a + positive offset from the sequence number in this segment. The urgent + pointer points to the sequence number of the octet following the urgent + data. This field is only be interpreted in segments with the URG control + bit set. */ + if( ( pxTCPHeader->ucTCPFlags & ipTCP_FLAG_URG ) != 0u ) + { + /* Although we ignore the urgent data, we have to skip it. */ + lUrgentLength = ( int32_t ) FreeRTOS_htons( pxTCPHeader->usUrgent ); + *ppucRecvData += lUrgentLength; + lReceiveLength -= FreeRTOS_min_int32( lReceiveLength, lUrgentLength ); + } + + return ( BaseType_t ) lReceiveLength; +} +/*-----------------------------------------------------------*/ + +/* + * prvStoreRxData(): called from prvTCPHandleState() + * + * The second thing is to do is check if the payload data may be accepted + * If so, they will be added to the reception queue. + */ +static BaseType_t prvStoreRxData( FreeRTOS_Socket_t *pxSocket, uint8_t *pucRecvData, + NetworkBufferDescriptor_t *pxNetworkBuffer, uint32_t ulReceiveLength ) +{ +TCPPacket_t *pxTCPPacket = ( TCPPacket_t * ) ( pxNetworkBuffer->pucEthernetBuffer ); +TCPHeader_t *pxTCPHeader = &pxTCPPacket->xTCPHeader; +TCPWindow_t *pxTCPWindow = &pxSocket->u.xTCP.xTCPWindow; +uint32_t ulSequenceNumber, ulSpace; +int32_t lOffset, lStored; +BaseType_t xResult = 0; + + ulSequenceNumber = FreeRTOS_ntohl( pxTCPHeader->ulSequenceNumber ); + + if( ( ulReceiveLength > 0u ) && ( pxSocket->u.xTCP.ucTCPState >= eSYN_RECEIVED ) ) + { + /* See if way may accept the data contents and forward it to the socket + owner. + + If it can't be "accept"ed it may have to be stored and send a selective + ack (SACK) option to confirm it. In that case, xTCPWindowRxStore() will be + called later to store an out-of-order packet (in case lOffset is + negative). */ + if ( pxSocket->u.xTCP.rxStream ) + { + ulSpace = ( uint32_t )uxStreamBufferGetSpace ( pxSocket->u.xTCP.rxStream ); + } + else + { + ulSpace = ( uint32_t )pxSocket->u.xTCP.uxRxStreamSize; + } + + lOffset = lTCPWindowRxCheck( pxTCPWindow, ulSequenceNumber, ulReceiveLength, ulSpace ); + + if( lOffset >= 0 ) + { + /* New data has arrived and may be made available to the user. See + if the head marker in rxStream may be advanced, only if lOffset == 0. + In case the low-water mark is reached, bLowWater will be set + "low-water" here stands for "little space". */ + lStored = lTCPAddRxdata( pxSocket, ( uint32_t ) lOffset, pucRecvData, ulReceiveLength ); + + if( lStored != ( int32_t ) ulReceiveLength ) + { + FreeRTOS_debug_printf( ( "lTCPAddRxdata: stored %ld / %lu bytes??\n", lStored, ulReceiveLength ) ); + + /* Received data could not be stored. The socket's flag + bMallocError has been set. The socket now has the status + eCLOSE_WAIT and a RST packet will be sent back. */ + prvTCPSendReset( pxNetworkBuffer ); + xResult = -1; + } + } + + /* After a missing packet has come in, higher packets may be passed to + the user. */ + #if( ipconfigUSE_TCP_WIN == 1 ) + { + /* Now lTCPAddRxdata() will move the rxHead pointer forward + so data becomes available to the user immediately + In case the low-water mark is reached, bLowWater will be set. */ + if( ( xResult == 0 ) && ( pxTCPWindow->ulUserDataLength > 0 ) ) + { + lTCPAddRxdata( pxSocket, 0ul, NULL, pxTCPWindow->ulUserDataLength ); + pxTCPWindow->ulUserDataLength = 0; + } + } + #endif /* ipconfigUSE_TCP_WIN */ + } + else + { + pxTCPWindow->ucOptionLength = 0u; + } + + return xResult; +} +/*-----------------------------------------------------------*/ + +/* Set the TCP options (if any) for the outgoing packet. */ +static UBaseType_t prvSetOptions( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t *pxNetworkBuffer ) +{ +TCPPacket_t *pxTCPPacket = ( TCPPacket_t * ) ( pxNetworkBuffer->pucEthernetBuffer ); +TCPHeader_t *pxTCPHeader = &pxTCPPacket->xTCPHeader; +TCPWindow_t *pxTCPWindow = &pxSocket->u.xTCP.xTCPWindow; +UBaseType_t uxOptionsLength = pxTCPWindow->ucOptionLength; + + #if( ipconfigUSE_TCP_WIN == 1 ) + if( uxOptionsLength != 0u ) + { + /* TCP options must be sent because a packet which is out-of-order + was received. */ + if( xTCPWindowLoggingLevel >= 0 ) + FreeRTOS_debug_printf( ( "SACK[%d,%d]: optlen %lu sending %lu - %lu\n", + pxSocket->usLocalPort, + pxSocket->u.xTCP.usRemotePort, + uxOptionsLength, + FreeRTOS_ntohl( pxTCPWindow->ulOptionsData[ 1 ] ) - pxSocket->u.xTCP.xTCPWindow.rx.ulFirstSequenceNumber, + FreeRTOS_ntohl( pxTCPWindow->ulOptionsData[ 2 ] ) - pxSocket->u.xTCP.xTCPWindow.rx.ulFirstSequenceNumber ) ); + memcpy( pxTCPHeader->ucOptdata, pxTCPWindow->ulOptionsData, ( size_t ) uxOptionsLength ); + + /* The header length divided by 4, goes into the higher nibble, + effectively a shift-left 2. */ + pxTCPHeader->ucTCPOffset = ( uint8_t )( ( ipSIZE_OF_TCP_HEADER + uxOptionsLength ) << 2 ); + } + else + #endif /* ipconfigUSE_TCP_WIN */ + if( ( pxSocket->u.xTCP.ucTCPState >= eESTABLISHED ) && ( pxSocket->u.xTCP.bits.bMssChange != pdFALSE_UNSIGNED ) ) + { + /* TCP options must be sent because the MSS has changed. */ + pxSocket->u.xTCP.bits.bMssChange = pdFALSE_UNSIGNED; + if( xTCPWindowLoggingLevel >= 0 ) + { + FreeRTOS_debug_printf( ( "MSS: sending %d\n", pxSocket->u.xTCP.usCurMSS ) ); + } + + pxTCPHeader->ucOptdata[ 0 ] = TCP_OPT_MSS; + pxTCPHeader->ucOptdata[ 1 ] = TCP_OPT_MSS_LEN; + pxTCPHeader->ucOptdata[ 2 ] = ( uint8_t ) ( ( pxSocket->u.xTCP.usCurMSS ) >> 8 ); + pxTCPHeader->ucOptdata[ 3 ] = ( uint8_t ) ( ( pxSocket->u.xTCP.usCurMSS ) & 0xffu ); + uxOptionsLength = 4u; + pxTCPHeader->ucTCPOffset = ( uint8_t )( ( ipSIZE_OF_TCP_HEADER + uxOptionsLength ) << 2 ); + } + + return uxOptionsLength; +} +/*-----------------------------------------------------------*/ + +/* + * prvHandleSynReceived(): called from prvTCPHandleState() + * + * Called from the states: eSYN_RECEIVED and eCONNECT_SYN + * If the flags received are correct, the socket will move to eESTABLISHED. + */ +static BaseType_t prvHandleSynReceived( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t **ppxNetworkBuffer, + uint32_t ulReceiveLength, UBaseType_t uxOptionsLength ) +{ +TCPPacket_t *pxTCPPacket = ( TCPPacket_t * ) ( (*ppxNetworkBuffer)->pucEthernetBuffer ); +TCPHeader_t *pxTCPHeader = &pxTCPPacket->xTCPHeader; +TCPWindow_t *pxTCPWindow = &pxSocket->u.xTCP.xTCPWindow; +uint8_t ucTCPFlags = pxTCPHeader->ucTCPFlags; +uint32_t ulSequenceNumber = FreeRTOS_ntohl( pxTCPHeader->ulSequenceNumber ); +BaseType_t xSendLength = 0; + + /* Either expect a ACK or a SYN+ACK. */ + uint16_t usExpect = ( uint16_t ) ipTCP_FLAG_ACK; + if( pxSocket->u.xTCP.ucTCPState == eCONNECT_SYN ) + { + usExpect |= ( uint16_t ) ipTCP_FLAG_SYN; + } + + if( ( ucTCPFlags & 0x17u ) != usExpect ) + { + /* eSYN_RECEIVED: flags 0010 expected, not 0002. */ + /* eSYN_RECEIVED: flags ACK expected, not SYN. */ + FreeRTOS_debug_printf( ( "%s: flags %04X expected, not %04X\n", + pxSocket->u.xTCP.ucTCPState == eSYN_RECEIVED ? "eSYN_RECEIVED" : "eCONNECT_SYN", + usExpect, ucTCPFlags ) ); + vTCPStateChange( pxSocket, eCLOSE_WAIT ); + pxTCPHeader->ucTCPFlags |= ipTCP_FLAG_RST; + xSendLength = ( BaseType_t ) ( ipSIZE_OF_IPv4_HEADER + ipSIZE_OF_TCP_HEADER + uxOptionsLength ); + pxTCPHeader->ucTCPOffset = ( uint8_t )( ( ipSIZE_OF_TCP_HEADER + uxOptionsLength ) << 2 ); + } + else + { + pxTCPWindow->usPeerPortNumber = pxSocket->u.xTCP.usRemotePort; + pxTCPWindow->usOurPortNumber = pxSocket->usLocalPort; + + if( pxSocket->u.xTCP.ucTCPState == eCONNECT_SYN ) + { + TCPPacket_t *pxLastTCPPacket = ( TCPPacket_t * ) ( pxSocket->u.xTCP.xPacket.u.ucLastPacket ); + + /* Clear the SYN flag in lastPacket. */ + pxLastTCPPacket->xTCPHeader.ucTCPFlags = ipTCP_FLAG_ACK; + + /* This socket was the one connecting actively so now perofmr the + synchronisation. */ + vTCPWindowInit( &pxSocket->u.xTCP.xTCPWindow, + ulSequenceNumber, pxSocket->u.xTCP.xTCPWindow.ulOurSequenceNumber, ( uint32_t ) pxSocket->u.xTCP.usCurMSS ); + pxTCPWindow->rx.ulCurrentSequenceNumber = pxTCPWindow->rx.ulHighestSequenceNumber = ulSequenceNumber + 1u; + pxTCPWindow->tx.ulCurrentSequenceNumber++; /* because we send a TCP_SYN [ | TCP_ACK ]; */ + pxTCPWindow->ulNextTxSequenceNumber++; + } + else if( ulReceiveLength == 0u ) + { + pxTCPWindow->rx.ulCurrentSequenceNumber = ulSequenceNumber; + } + + /* The SYN+ACK has been confirmed, increase the next sequence number by + 1. */ + pxTCPWindow->ulOurSequenceNumber = pxTCPWindow->tx.ulFirstSequenceNumber + 1u; + + #if( ipconfigUSE_TCP_WIN == 1 ) + { + FreeRTOS_debug_printf( ( "TCP: %s %d => %lxip:%d set ESTAB (scaling %u)\n", + pxSocket->u.xTCP.ucTCPState == eCONNECT_SYN ? "active" : "passive", + pxSocket->usLocalPort, + pxSocket->u.xTCP.ulRemoteIP, + pxSocket->u.xTCP.usRemotePort, + ( unsigned ) pxSocket->u.xTCP.bits.bWinScaling ) ); + } + #endif /* ipconfigUSE_TCP_WIN */ + + if( ( pxSocket->u.xTCP.ucTCPState == eCONNECT_SYN ) || ( ulReceiveLength != 0u ) ) + { + pxTCPHeader->ucTCPFlags = ipTCP_FLAG_ACK; + xSendLength = ( BaseType_t ) ( ipSIZE_OF_IPv4_HEADER + ipSIZE_OF_TCP_HEADER + uxOptionsLength ); + pxTCPHeader->ucTCPOffset = ( uint8_t ) ( ( ipSIZE_OF_TCP_HEADER + uxOptionsLength ) << 2 ); + } + #if( ipconfigUSE_TCP_WIN != 0 ) + { + if( pxSocket->u.xTCP.bits.bWinScaling == pdFALSE_UNSIGNED ) + { + /* The other party did not send a scaling factor. + A shifting factor in this side must be canceled. */ + pxSocket->u.xTCP.ucMyWinScaleFactor = 0; + pxSocket->u.xTCP.ucPeerWinScaleFactor = 0; + } + } + #endif /* ipconfigUSE_TCP_WIN */ + /* This was the third step of connecting: SYN, SYN+ACK, ACK so now the + connection is established. */ + vTCPStateChange( pxSocket, eESTABLISHED ); + } + + return xSendLength; +} +/*-----------------------------------------------------------*/ + +/* + * prvHandleEstablished(): called from prvTCPHandleState() + * + * Called if the status is eESTABLISHED. Data reception has been handled + * earlier. Here the ACK's from peer will be checked, and if a FIN is received, + * the code will check if it may be accepted, i.e. if all expected data has been + * completely received. + */ +static BaseType_t prvHandleEstablished( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t **ppxNetworkBuffer, + uint32_t ulReceiveLength, UBaseType_t uxOptionsLength ) +{ +TCPPacket_t *pxTCPPacket = ( TCPPacket_t * ) ( (*ppxNetworkBuffer)->pucEthernetBuffer ); +TCPHeader_t *pxTCPHeader = &pxTCPPacket->xTCPHeader; +TCPWindow_t *pxTCPWindow = &pxSocket->u.xTCP.xTCPWindow; +uint8_t ucTCPFlags = pxTCPHeader->ucTCPFlags; +uint32_t ulSequenceNumber = FreeRTOS_ntohl( pxTCPHeader->ulSequenceNumber ), ulCount; +BaseType_t xSendLength = 0, xMayClose = pdFALSE, bRxComplete, bTxDone; +int32_t lDistance, lSendResult; + + /* Remember the window size the peer is advertising. */ + pxSocket->u.xTCP.ulWindowSize = FreeRTOS_ntohs( pxTCPHeader->usWindow ); + #if( ipconfigUSE_TCP_WIN != 0 ) + { + pxSocket->u.xTCP.ulWindowSize = + ( pxSocket->u.xTCP.ulWindowSize << pxSocket->u.xTCP.ucPeerWinScaleFactor ); + } + #endif + + if( ( ucTCPFlags & ( uint8_t ) ipTCP_FLAG_ACK ) != 0u ) + { + ulCount = ulTCPWindowTxAck( pxTCPWindow, FreeRTOS_ntohl( pxTCPPacket->xTCPHeader.ulAckNr ) ); + + /* ulTCPWindowTxAck() returns the number of bytes which have been acked, + starting at 'tx.ulCurrentSequenceNumber'. Advance the tail pointer in + txStream. */ + if( ( pxSocket->u.xTCP.txStream != NULL ) && ( ulCount > 0u ) ) + { + /* Just advancing the tail index, 'ulCount' bytes have been + confirmed, and because there is new space in the txStream, the + user/owner should be woken up. */ + /* _HT_ : only in case the socket's waiting? */ + if( uxStreamBufferGet( pxSocket->u.xTCP.txStream, 0u, NULL, ( size_t ) ulCount, pdFALSE ) != 0u ) + { + pxSocket->xEventBits |= eSOCKET_SEND; + + #if ipconfigSUPPORT_SELECT_FUNCTION == 1 + { + if( ( pxSocket->xSelectBits & eSELECT_WRITE ) != 0 ) + { + pxSocket->xEventBits |= ( eSELECT_WRITE << SOCKET_EVENT_BIT_COUNT ); + } + } + #endif + /* In case the socket owner has installed an OnSent handler, + call it now. */ + #if( ipconfigUSE_CALLBACKS == 1 ) + { + if( ipconfigIS_VALID_PROG_ADDRESS( pxSocket->u.xTCP.pxHandleSent ) ) + { + pxSocket->u.xTCP.pxHandleSent( (Socket_t *)pxSocket, ulCount ); + } + } + #endif /* ipconfigUSE_CALLBACKS == 1 */ + } + } + } + + /* If this socket has a stream for transmission, add the data to the + outgoing segment(s). */ + if( pxSocket->u.xTCP.txStream != NULL ) + { + prvTCPAddTxData( pxSocket ); + } + + pxSocket->u.xTCP.xTCPWindow.ulOurSequenceNumber = pxTCPWindow->tx.ulCurrentSequenceNumber; + + if( ( pxSocket->u.xTCP.bits.bFinAccepted != pdFALSE_UNSIGNED ) || ( ( ucTCPFlags & ( uint8_t ) ipTCP_FLAG_FIN ) != 0u ) ) + { + /* Peer is requesting to stop, see if we're really finished. */ + xMayClose = pdTRUE; + + /* Checks are only necessary if we haven't sent a FIN yet. */ + if( pxSocket->u.xTCP.bits.bFinSent == pdFALSE_UNSIGNED ) + { + /* xTCPWindowTxDone returns true when all Tx queues are empty. */ + bRxComplete = xTCPWindowRxEmpty( pxTCPWindow ); + bTxDone = xTCPWindowTxDone( pxTCPWindow ); + + if( ( bRxComplete == 0 ) || ( bTxDone == 0 ) ) + { + /* Refusing FIN: Rx incomp 1 optlen 4 tx done 1. */ + FreeRTOS_debug_printf( ( "Refusing FIN[%u,%u]: RxCompl %lu tx done %ld\n", + pxSocket->usLocalPort, + pxSocket->u.xTCP.usRemotePort, + bRxComplete, bTxDone ) ); + xMayClose = pdFALSE; + } + else + { + lDistance = ( int32_t ) ( ulSequenceNumber + ulReceiveLength - pxTCPWindow->rx.ulCurrentSequenceNumber ); + + if( lDistance > 1 ) + { + FreeRTOS_debug_printf( ( "Refusing FIN: Rx not complete %ld (cur %lu high %lu)\n", + lDistance, pxTCPWindow->rx.ulCurrentSequenceNumber - pxTCPWindow->rx.ulFirstSequenceNumber, + pxTCPWindow->rx.ulHighestSequenceNumber - pxTCPWindow->rx.ulFirstSequenceNumber ) ); + + xMayClose = pdFALSE; + } + } + } + + if( xTCPWindowLoggingLevel > 0 ) + { + FreeRTOS_debug_printf( ( "TCP: FIN received, mayClose = %ld (Rx %lu Len %ld, Tx %lu)\n", + xMayClose, ulSequenceNumber - pxSocket->u.xTCP.xTCPWindow.rx.ulFirstSequenceNumber, ulReceiveLength, + pxTCPWindow->tx.ulCurrentSequenceNumber - pxSocket->u.xTCP.xTCPWindow.tx.ulFirstSequenceNumber ) ); + } + + if( xMayClose != pdFALSE ) + { + pxSocket->u.xTCP.bits.bFinAccepted = pdTRUE_UNSIGNED; + xSendLength = prvTCPHandleFin( pxSocket, *ppxNetworkBuffer ); + } + } + + if( xMayClose == pdFALSE ) + { + pxTCPHeader->ucTCPFlags = ipTCP_FLAG_ACK; + + if( ulReceiveLength != 0u ) + { + xSendLength = ( BaseType_t ) ( ipSIZE_OF_IPv4_HEADER + ipSIZE_OF_TCP_HEADER + uxOptionsLength ); + /* TCP-offsett equals '( ( length / 4 ) << 4 )', resulting in a shift-left 2 */ + pxTCPHeader->ucTCPOffset = ( uint8_t )( ( ipSIZE_OF_TCP_HEADER + uxOptionsLength ) << 2 ); + + if( pxSocket->u.xTCP.bits.bFinSent != pdFALSE_UNSIGNED ) + { + pxTCPWindow->tx.ulCurrentSequenceNumber = pxTCPWindow->tx.ulFINSequenceNumber; + } + } + + /* Now get data to be transmitted. */ + /* _HT_ patch: since the MTU has be fixed at 1500 in stead of 1526, TCP + can not send-out both TCP options and also a full packet. Sending + options (SACK) is always more urgent than sending data, which can be + sent later. */ + if( uxOptionsLength == 0u ) + { + /* prvTCPPrepareSend might allocate a bigger network buffer, if + necessary. */ + lSendResult = prvTCPPrepareSend( pxSocket, ppxNetworkBuffer, uxOptionsLength ); + if( lSendResult > 0 ) + { + xSendLength = ( BaseType_t ) lSendResult; + } + } + } + + return xSendLength; +} +/*-----------------------------------------------------------*/ + +/* + * Called from prvTCPHandleState(). There is data to be sent. If + * ipconfigUSE_TCP_WIN is defined, and if only an ACK must be sent, it will be + * checked if it would better be postponed for efficiency. + */ +static BaseType_t prvSendData( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t **ppxNetworkBuffer, + uint32_t ulReceiveLength, BaseType_t xSendLength ) +{ +TCPPacket_t *pxTCPPacket = ( TCPPacket_t * ) ( (*ppxNetworkBuffer)->pucEthernetBuffer ); +TCPHeader_t *pxTCPHeader = &pxTCPPacket->xTCPHeader; +TCPWindow_t *pxTCPWindow = &pxSocket->u.xTCP.xTCPWindow; +/* Find out what window size we may advertised. */ +uint32_t ulFrontSpace; +int32_t lRxSpace; +#if( ipconfigUSE_TCP_WIN == 1 ) + #if( ipconfigTCP_ACK_EARLIER_PACKET == 0 ) + const int32_t lMinLength = 0; + #else + int32_t lMinLength; + #endif +#endif + pxSocket->u.xTCP.ulRxCurWinSize = pxTCPWindow->xSize.ulRxWindowLength - + ( pxTCPWindow->rx.ulHighestSequenceNumber - pxTCPWindow->rx.ulCurrentSequenceNumber ); + + /* Free space in rxStream. */ + if( pxSocket->u.xTCP.rxStream != NULL ) + { + ulFrontSpace = ( uint32_t ) uxStreamBufferFrontSpace( pxSocket->u.xTCP.rxStream ); + } + else + { + ulFrontSpace = ( uint32_t ) pxSocket->u.xTCP.uxRxStreamSize; + } + + pxSocket->u.xTCP.ulRxCurWinSize = FreeRTOS_min_uint32( ulFrontSpace, pxSocket->u.xTCP.ulRxCurWinSize ); + + /* Set the time-out field, so that we'll be called by the IP-task in case no + next message will be received. */ + lRxSpace = (int32_t)( pxSocket->u.xTCP.ulHighestRxAllowed - pxTCPWindow->rx.ulCurrentSequenceNumber ); + #if ipconfigUSE_TCP_WIN == 1 + { + + #if( ipconfigTCP_ACK_EARLIER_PACKET != 0 ) + { + lMinLength = ( ( int32_t ) 2 ) * ( ( int32_t ) pxSocket->u.xTCP.usCurMSS ); + } + #endif /* ipconfigTCP_ACK_EARLIER_PACKET */ + + /* In case we're receiving data continuously, we might postpone sending + an ACK to gain performance. */ + if( ( ulReceiveLength > 0 ) && /* Data was sent to this socket. */ + ( lRxSpace >= lMinLength ) && /* There is Rx space for more data. */ + ( pxSocket->u.xTCP.bits.bFinSent == pdFALSE_UNSIGNED ) && /* Not in a closure phase. */ + ( xSendLength == ( ipSIZE_OF_IPv4_HEADER + ipSIZE_OF_TCP_HEADER ) ) && /* No Tx data or options to be sent. */ + ( pxSocket->u.xTCP.ucTCPState == eESTABLISHED ) && /* Connection established. */ + ( pxTCPHeader->ucTCPFlags == ipTCP_FLAG_ACK ) ) /* There are no other flags than an ACK. */ + { + if( pxSocket->u.xTCP.pxAckMessage != *ppxNetworkBuffer ) + { + /* There was still a delayed in queue, delete it. */ + if( pxSocket->u.xTCP.pxAckMessage != 0 ) + { + vReleaseNetworkBufferAndDescriptor( pxSocket->u.xTCP.pxAckMessage ); + } + + pxSocket->u.xTCP.pxAckMessage = *ppxNetworkBuffer; + } + if( ( ulReceiveLength < ( uint32_t ) pxSocket->u.xTCP.usCurMSS ) || /* Received a small message. */ + ( lRxSpace < ( int32_t ) ( 2U * pxSocket->u.xTCP.usCurMSS ) ) ) /* There are less than 2 x MSS space in the Rx buffer. */ + { + pxSocket->u.xTCP.usTimeout = ( uint16_t ) pdMS_TO_MIN_TICKS( DELAYED_ACK_SHORT_DELAY_MS ); + } + else + { + /* Normally a delayed ACK should wait 200 ms for a next incoming + packet. Only wait 20 ms here to gain performance. A slow ACK + for full-size message. */ + pxSocket->u.xTCP.usTimeout = ( uint16_t ) pdMS_TO_MIN_TICKS( DELAYED_ACK_LONGER_DELAY_MS ); + } + + if( ( xTCPWindowLoggingLevel > 1 ) && ( ipconfigTCP_MAY_LOG_PORT( pxSocket->usLocalPort ) != pdFALSE ) ) + { + FreeRTOS_debug_printf( ( "Send[%u->%u] del ACK %lu SEQ %lu (len %lu) tmout %u d %lu\n", + pxSocket->usLocalPort, + pxSocket->u.xTCP.usRemotePort, + pxTCPWindow->rx.ulCurrentSequenceNumber - pxTCPWindow->rx.ulFirstSequenceNumber, + pxSocket->u.xTCP.xTCPWindow.ulOurSequenceNumber - pxTCPWindow->tx.ulFirstSequenceNumber, + xSendLength, + pxSocket->u.xTCP.usTimeout, lRxSpace ) ); + } + + *ppxNetworkBuffer = NULL; + xSendLength = 0; + } + else if( pxSocket->u.xTCP.pxAckMessage != NULL ) + { + /* As an ACK is not being delayed, remove any earlier delayed ACK + message. */ + if( pxSocket->u.xTCP.pxAckMessage != *ppxNetworkBuffer ) + { + vReleaseNetworkBufferAndDescriptor( pxSocket->u.xTCP.pxAckMessage ); + } + + pxSocket->u.xTCP.pxAckMessage = NULL; + } + } + #else + { + /* Remove compiler warnings. */ + ( void ) ulReceiveLength; + ( void ) pxTCPHeader; + ( void ) lRxSpace; + } + #endif /* ipconfigUSE_TCP_WIN */ + + if( xSendLength != 0 ) + { + if( ( xTCPWindowLoggingLevel > 1 ) && ( ipconfigTCP_MAY_LOG_PORT( pxSocket->usLocalPort ) != pdFALSE ) ) + { + FreeRTOS_debug_printf( ( "Send[%u->%u] imm ACK %lu SEQ %lu (len %lu)\n", + pxSocket->usLocalPort, + pxSocket->u.xTCP.usRemotePort, + pxTCPWindow->rx.ulCurrentSequenceNumber - pxTCPWindow->rx.ulFirstSequenceNumber, + pxTCPWindow->ulOurSequenceNumber - pxTCPWindow->tx.ulFirstSequenceNumber, + xSendLength ) ); + } + + /* Set the parameter 'xReleaseAfterSend' to the value of + ipconfigZERO_COPY_TX_DRIVER. */ + prvTCPReturnPacket( pxSocket, *ppxNetworkBuffer, ( uint32_t ) xSendLength, ipconfigZERO_COPY_TX_DRIVER ); + #if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + { + /* The driver has taken ownership of the Network Buffer. */ + *ppxNetworkBuffer = NULL; + } + #endif + } + + return xSendLength; +} +/*-----------------------------------------------------------*/ + +/* + * prvTCPHandleState() + * is the most important function of this TCP stack + * We've tried to keep it (relatively short) by putting a lot of code in + * the static functions above: + * + * prvCheckRxData() + * prvStoreRxData() + * prvSetOptions() + * prvHandleSynReceived() + * prvHandleEstablished() + * prvSendData() + * + * As these functions are declared static, and they're called from one location + * only, most compilers will inline them, thus avoiding a call and return. + */ +static BaseType_t prvTCPHandleState( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t **ppxNetworkBuffer ) +{ +TCPPacket_t *pxTCPPacket = ( TCPPacket_t * ) ( (*ppxNetworkBuffer)->pucEthernetBuffer ); +TCPHeader_t *pxTCPHeader = &( pxTCPPacket->xTCPHeader ); +BaseType_t xSendLength = 0; +uint32_t ulReceiveLength; /* Number of bytes contained in the TCP message. */ +uint8_t *pucRecvData; +uint32_t ulSequenceNumber = FreeRTOS_ntohl (pxTCPHeader->ulSequenceNumber); + + /* uxOptionsLength: the size of the options to be sent (always a multiple of + 4 bytes) + 1. in the SYN phase, we shall communicate the MSS + 2. in case of a SACK, Selective ACK, ack a segment which comes in + out-of-order. */ +UBaseType_t uxOptionsLength = 0u; +uint8_t ucTCPFlags = pxTCPHeader->ucTCPFlags; +TCPWindow_t *pxTCPWindow = &( pxSocket->u.xTCP.xTCPWindow ); + + /* First get the length and the position of the received data, if any. + pucRecvData will point to the first byte of the TCP payload. */ + ulReceiveLength = ( uint32_t ) prvCheckRxData( *ppxNetworkBuffer, &pucRecvData ); + + if( pxSocket->u.xTCP.ucTCPState >= eESTABLISHED ) + { + if ( pxTCPWindow->rx.ulCurrentSequenceNumber == ulSequenceNumber + 1u ) + { + /* This is most probably a keep-alive message from peer. Setting + 'bWinChange' doesn't cause a window-size-change, the flag is used + here to force sending an immediate ACK. */ + pxSocket->u.xTCP.bits.bWinChange = pdTRUE_UNSIGNED; + } + } + + /* Keep track of the highest sequence number that might be expected within + this connection. */ + if( ( ( int32_t ) ( ulSequenceNumber + ulReceiveLength - pxTCPWindow->rx.ulHighestSequenceNumber ) ) > 0 ) + { + pxTCPWindow->rx.ulHighestSequenceNumber = ulSequenceNumber + ulReceiveLength; + } + + /* Storing data may result in a fatal error if malloc() fails. */ + if( prvStoreRxData( pxSocket, pucRecvData, *ppxNetworkBuffer, ulReceiveLength ) < 0 ) + { + xSendLength = -1; + } + else + { + uxOptionsLength = prvSetOptions( pxSocket, *ppxNetworkBuffer ); + + if( ( pxSocket->u.xTCP.ucTCPState == eSYN_RECEIVED ) && ( ( ucTCPFlags & ipTCP_FLAG_CTRL ) == ipTCP_FLAG_SYN ) ) + { + FreeRTOS_debug_printf( ( "eSYN_RECEIVED: ACK expected, not SYN: peer missed our SYN+ACK\n" ) ); + + /* In eSYN_RECEIVED a simple ACK is expected, but apparently the + 'SYN+ACK' didn't arrive. Step back to the previous state in which + a first incoming SYN is handled. The SYN was counted already so + decrease it first. */ + vTCPStateChange( pxSocket, eSYN_FIRST ); + } + + if( ( ( ucTCPFlags & ipTCP_FLAG_FIN ) != 0u ) && ( pxSocket->u.xTCP.bits.bFinRecv == pdFALSE_UNSIGNED ) ) + { + /* It's the first time a FIN has been received, remember its + sequence number. */ + pxTCPWindow->rx.ulFINSequenceNumber = ulSequenceNumber + ulReceiveLength; + pxSocket->u.xTCP.bits.bFinRecv = pdTRUE_UNSIGNED; + + /* Was peer the first one to send a FIN? */ + if( pxSocket->u.xTCP.bits.bFinSent == pdFALSE_UNSIGNED ) + { + /* If so, don't send the-last-ACK. */ + pxSocket->u.xTCP.bits.bFinLast = pdTRUE_UNSIGNED; + } + } + + switch (pxSocket->u.xTCP.ucTCPState) + { + case eCLOSED: /* (server + client) no connection state at all. */ + /* Nothing to do for a closed socket, except waiting for the + owner. */ + break; + + case eTCP_LISTEN: /* (server) waiting for a connection request from + any remote TCP and port. */ + /* The listen state was handled in xProcessReceivedTCPPacket(). + Should not come here. */ + break; + + case eSYN_FIRST: /* (server) Just received a SYN request for a server + socket. */ + { + /* A new socket has been created, reply with a SYN+ACK. + Acknowledge with seq+1 because the SYN is seen as pseudo data + with len = 1. */ + uxOptionsLength = prvSetSynAckOptions( pxSocket, pxTCPPacket ); + pxTCPHeader->ucTCPFlags = ipTCP_FLAG_SYN | ipTCP_FLAG_ACK; + + xSendLength = ( BaseType_t ) ( ipSIZE_OF_IPv4_HEADER + ipSIZE_OF_TCP_HEADER + uxOptionsLength ); + + /* Set the TCP offset field: ipSIZE_OF_TCP_HEADER equals 20 and + uxOptionsLength is a multiple of 4. The complete expression is: + ucTCPOffset = ( ( ipSIZE_OF_TCP_HEADER + uxOptionsLength ) / 4 ) << 4 */ + pxTCPHeader->ucTCPOffset = ( uint8_t )( ( ipSIZE_OF_TCP_HEADER + uxOptionsLength ) << 2 ); + vTCPStateChange( pxSocket, eSYN_RECEIVED ); + + pxTCPWindow->rx.ulCurrentSequenceNumber = pxTCPWindow->rx.ulHighestSequenceNumber = ulSequenceNumber + 1u; + pxTCPWindow->tx.ulCurrentSequenceNumber = pxTCPWindow->ulNextTxSequenceNumber = pxTCPWindow->tx.ulFirstSequenceNumber + 1u; /* because we send a TCP_SYN. */ + } + break; + + case eCONNECT_SYN: /* (client) also called SYN_SENT: we've just send a + SYN, expect a SYN+ACK and send a ACK now. */ + /* Fall through */ + case eSYN_RECEIVED: /* (server) we've had a SYN, replied with SYN+SCK + expect a ACK and do nothing. */ + xSendLength = prvHandleSynReceived( pxSocket, ppxNetworkBuffer, ulReceiveLength, uxOptionsLength ); + break; + + case eESTABLISHED: /* (server + client) an open connection, data + received can be delivered to the user. The normal + state for the data transfer phase of the connection + The closing states are also handled here with the + use of some flags. */ + xSendLength = prvHandleEstablished( pxSocket, ppxNetworkBuffer, ulReceiveLength, uxOptionsLength ); + break; + + case eLAST_ACK: /* (server + client) waiting for an acknowledgement + of the connection termination request previously + sent to the remote TCP (which includes an + acknowledgement of its connection termination + request). */ + /* Fall through */ + case eFIN_WAIT_1: /* (server + client) waiting for a connection termination request from the remote TCP, + * or an acknowledgement of the connection termination request previously sent. */ + /* Fall through */ + case eFIN_WAIT_2: /* (server + client) waiting for a connection termination request from the remote TCP. */ + xSendLength = prvTCPHandleFin( pxSocket, *ppxNetworkBuffer ); + break; + + case eCLOSE_WAIT: /* (server + client) waiting for a connection + termination request from the local user. Nothing to + do, connection is closed, wait for owner to close + this socket. */ + break; + + case eCLOSING: /* (server + client) waiting for a connection + termination request acknowledgement from the remote + TCP. */ + break; + + case eTIME_WAIT: /* (either server or client) waiting for enough time + to pass to be sure the remote TCP received the + acknowledgement of its connection termination + request. [According to RFC 793 a connection can stay + in TIME-WAIT for a maximum of four minutes known as + a MSL (maximum segment lifetime).] These states are + implemented implicitly by settings flags like + 'bFinSent', 'bFinRecv', and 'bFinAcked'. */ + break; + default: + break; + } + } + + if( xSendLength > 0 ) + { + xSendLength = prvSendData( pxSocket, ppxNetworkBuffer, ulReceiveLength, xSendLength ); + } + + return xSendLength; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTCPSendReset( NetworkBufferDescriptor_t *pxNetworkBuffer ) +{ + #if( ipconfigIGNORE_UNKNOWN_PACKETS == 0 ) + { + TCPPacket_t *pxTCPPacket = ( TCPPacket_t * ) ( pxNetworkBuffer->pucEthernetBuffer ); + const BaseType_t xSendLength = ( BaseType_t ) ( ipSIZE_OF_IPv4_HEADER + ipSIZE_OF_TCP_HEADER + 0u ); /* Plus 0 options. */ + + pxTCPPacket->xTCPHeader.ucTCPFlags = ipTCP_FLAG_ACK | ipTCP_FLAG_RST; + pxTCPPacket->xTCPHeader.ucTCPOffset = ( ipSIZE_OF_TCP_HEADER + 0u ) << 2; + + prvTCPReturnPacket( NULL, pxNetworkBuffer, ( uint32_t ) xSendLength, pdFALSE ); + } + #endif /* !ipconfigIGNORE_UNKNOWN_PACKETS */ + + /* Remove compiler warnings if ipconfigIGNORE_UNKNOWN_PACKETS == 1. */ + ( void ) pxNetworkBuffer; + + /* The packet was not consumed. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +static void prvSocketSetMSS( FreeRTOS_Socket_t *pxSocket ) +{ +uint32_t ulMSS = ipconfigTCP_MSS; + + if( ( ( FreeRTOS_ntohl( pxSocket->u.xTCP.ulRemoteIP ) ^ *ipLOCAL_IP_ADDRESS_POINTER ) & xNetworkAddressing.ulNetMask ) != 0ul ) + { + /* Data for this peer will pass through a router, and maybe through + the internet. Limit the MSS to 1400 bytes or less. */ + ulMSS = FreeRTOS_min_uint32( ( uint32_t ) REDUCED_MSS_THROUGH_INTERNET, ulMSS ); + } + + FreeRTOS_debug_printf( ( "prvSocketSetMSS: %lu bytes for %lxip:%u\n", ulMSS, pxSocket->u.xTCP.ulRemoteIP, pxSocket->u.xTCP.usRemotePort ) ); + + pxSocket->u.xTCP.usInitMSS = pxSocket->u.xTCP.usCurMSS = ( uint16_t ) ulMSS; +} +/*-----------------------------------------------------------*/ + +/* + * FreeRTOS_TCP_IP has only 2 public functions, this is the second one: + * xProcessReceivedTCPPacket() + * prvTCPHandleState() + * prvTCPPrepareSend() + * prvTCPReturnPacket() + * xNetworkInterfaceOutput() // Sends data to the NIC + * prvTCPSendRepeated() + * prvTCPReturnPacket() // Prepare for returning + * xNetworkInterfaceOutput() // Sends data to the NIC +*/ +BaseType_t xProcessReceivedTCPPacket( NetworkBufferDescriptor_t *pxNetworkBuffer ) +{ +FreeRTOS_Socket_t *pxSocket; +TCPPacket_t * pxTCPPacket = ( TCPPacket_t * ) ( pxNetworkBuffer->pucEthernetBuffer ); +uint16_t ucTCPFlags; +uint32_t ulLocalIP; +uint16_t xLocalPort; +uint32_t ulRemoteIP; +uint16_t xRemotePort; +BaseType_t xResult = pdPASS; + + /* Check for a minimum packet size. */ + if( pxNetworkBuffer->xDataLength >= ( ipSIZE_OF_ETH_HEADER + ipSIZE_OF_IPv4_HEADER + ipSIZE_OF_TCP_HEADER ) ) + { + ucTCPFlags = pxTCPPacket->xTCPHeader.ucTCPFlags; + ulLocalIP = FreeRTOS_htonl( pxTCPPacket->xIPHeader.ulDestinationIPAddress ); + xLocalPort = FreeRTOS_htons( pxTCPPacket->xTCPHeader.usDestinationPort ); + ulRemoteIP = FreeRTOS_htonl( pxTCPPacket->xIPHeader.ulSourceIPAddress ); + xRemotePort = FreeRTOS_htons( pxTCPPacket->xTCPHeader.usSourcePort ); + + /* Find the destination socket, and if not found: return a socket listing to + the destination PORT. */ + pxSocket = ( FreeRTOS_Socket_t * )pxTCPSocketLookup( ulLocalIP, xLocalPort, ulRemoteIP, xRemotePort ); + } + else + { + return pdFAIL; + } + + if( ( pxSocket == NULL ) || ( prvTCPSocketIsActive( ( UBaseType_t ) pxSocket->u.xTCP.ucTCPState ) == pdFALSE ) ) + { + /* A TCP messages is received but either there is no socket with the + given port number or the there is a socket, but it is in one of these + non-active states: eCLOSED, eCLOSE_WAIT, eFIN_WAIT_2, eCLOSING, or + eTIME_WAIT. */ + + FreeRTOS_debug_printf( ( "TCP: No active socket on port %d (%lxip:%d)\n", xLocalPort, ulRemoteIP, xRemotePort ) ); + + /* Send a RST to all packets that can not be handled. As a result + the other party will get a ECONN error. There are two exceptions: + 1) A packet that already has the RST flag set. + 2) A packet that only has the ACK flag set. + A packet with only the ACK flag set might be the last ACK in + a three-way hand-shake that closes a connection. */ + if( ( ( ucTCPFlags & ipTCP_FLAG_CTRL ) != ipTCP_FLAG_ACK ) && + ( ( ucTCPFlags & ipTCP_FLAG_RST ) == 0u ) ) + { + prvTCPSendReset( pxNetworkBuffer ); + } + + /* The packet can't be handled. */ + xResult = pdFAIL; + } + else + { + pxSocket->u.xTCP.ucRepCount = 0u; + + if( pxSocket->u.xTCP.ucTCPState == eTCP_LISTEN ) + { + /* The matching socket is in a listening state. Test if the peer + has set the SYN flag. */ + if( ( ucTCPFlags & ipTCP_FLAG_CTRL ) != ipTCP_FLAG_SYN ) + { + /* What happens: maybe after a reboot, a client doesn't know the + connection had gone. Send a RST in order to get a new connect + request. */ + #if( ipconfigHAS_DEBUG_PRINTF == 1 ) + { + FreeRTOS_debug_printf( ( "TCP: Server can't handle flags: %s from %lxip:%u to port %u\n", + prvTCPFlagMeaning( ( UBaseType_t ) ucTCPFlags ), ulRemoteIP, xRemotePort, xLocalPort ) ); + } + #endif /* ipconfigHAS_DEBUG_PRINTF */ + + if( ( ucTCPFlags & ipTCP_FLAG_RST ) == 0u ) + { + prvTCPSendReset( pxNetworkBuffer ); + } + xResult = pdFAIL; + } + else + { + /* prvHandleListen() will either return a newly created socket + (if bReuseSocket is false), otherwise it returns the current + socket which will later get connected. */ + pxSocket = prvHandleListen( pxSocket, pxNetworkBuffer ); + + if( pxSocket == NULL ) + { + xResult = pdFAIL; + } + } + } /* if( pxSocket->u.xTCP.ucTCPState == eTCP_LISTEN ). */ + else + { + /* This is not a socket in listening mode. Check for the RST + flag. */ + if( ( ucTCPFlags & ipTCP_FLAG_RST ) != 0u ) + { + /* The target socket is not in a listening state, any RST packet + will cause the socket to be closed. */ + FreeRTOS_debug_printf( ( "TCP: RST received from %lxip:%u for %u\n", ulRemoteIP, xRemotePort, xLocalPort ) ); + /* _HT_: should indicate that 'ECONNRESET' must be returned to the used during next API. */ + vTCPStateChange( pxSocket, eCLOSED ); + + /* The packet cannot be handled. */ + xResult = pdFAIL; + } + else if( ( ( ucTCPFlags & ipTCP_FLAG_CTRL ) == ipTCP_FLAG_SYN ) && ( pxSocket->u.xTCP.ucTCPState >= eESTABLISHED ) ) + { + /* SYN flag while this socket is already connected. */ + FreeRTOS_debug_printf( ( "TCP: SYN unexpected from %lxip:%u\n", ulRemoteIP, xRemotePort ) ); + + /* The packet cannot be handled. */ + xResult = pdFAIL; + } + else + { + /* Update the copy of the TCP header only (skipping eth and IP + headers). It might be used later on, whenever data must be sent + to the peer. */ + const BaseType_t lOffset = ( BaseType_t ) ( ipSIZE_OF_ETH_HEADER + ipSIZE_OF_IPv4_HEADER ); + memcpy( pxSocket->u.xTCP.xPacket.u.ucLastPacket + lOffset, pxNetworkBuffer->pucEthernetBuffer + lOffset, ipSIZE_OF_TCP_HEADER ); + } + } + } + + if( xResult != pdFAIL ) + { + /* Touch the alive timers because we received a message for this + socket. */ + prvTCPTouchSocket( pxSocket ); + + /* Parse the TCP option(s), if present. */ + /* _HT_ : if we're in the SYN phase, and peer does not send a MSS option, + then we MUST assume an MSS size of 536 bytes for backward compatibility. */ + + /* When there are no TCP options, the TCP offset equals 20 bytes, which is stored as + the number 5 (words) in the higher niblle of the TCP-offset byte. */ + if( ( pxTCPPacket->xTCPHeader.ucTCPOffset & TCP_OFFSET_LENGTH_BITS ) > TCP_OFFSET_STANDARD_LENGTH ) + { + prvCheckOptions( pxSocket, pxNetworkBuffer ); + } + + + #if( ipconfigUSE_TCP_WIN == 1 ) + { + pxSocket->u.xTCP.ulWindowSize = FreeRTOS_ntohs( pxTCPPacket->xTCPHeader.usWindow ); + pxSocket->u.xTCP.ulWindowSize = + ( pxSocket->u.xTCP.ulWindowSize << pxSocket->u.xTCP.ucPeerWinScaleFactor ); + } + #endif + + /* In prvTCPHandleState() the incoming messages will be handled + depending on the current state of the connection. */ + if( prvTCPHandleState( pxSocket, &pxNetworkBuffer ) > 0 ) + { + /* prvTCPHandleState() has sent a message, see if there are more to + be transmitted. */ + #if( ipconfigUSE_TCP_WIN == 1 ) + { + prvTCPSendRepeated( pxSocket, &pxNetworkBuffer ); + } + #endif /* ipconfigUSE_TCP_WIN */ + } + + if( pxNetworkBuffer != NULL ) + { + /* We must check if the buffer is unequal to NULL, because the + socket might keep a reference to it in case a delayed ACK must be + sent. */ + vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ); + pxNetworkBuffer = NULL; + } + + /* And finally, calculate when this socket wants to be woken up. */ + prvTCPNextTimeout ( pxSocket ); + /* Return pdPASS to tell that the network buffer is 'consumed'. */ + xResult = pdPASS; + } + + /* pdPASS being returned means the buffer has been consumed. */ + return xResult; +} +/*-----------------------------------------------------------*/ + +static FreeRTOS_Socket_t *prvHandleListen( FreeRTOS_Socket_t *pxSocket, NetworkBufferDescriptor_t *pxNetworkBuffer ) +{ +TCPPacket_t * pxTCPPacket = ( TCPPacket_t * ) ( pxNetworkBuffer->pucEthernetBuffer ); +FreeRTOS_Socket_t *pxReturn = NULL; +uint32_t ulInitialSequenceNumber; + + /* Assume that a new Initial Sequence Number will be required. Request + it now in order to fail out if necessary. */ + ulInitialSequenceNumber = ulApplicationGetNextSequenceNumber( *ipLOCAL_IP_ADDRESS_POINTER, + pxSocket->usLocalPort, + pxTCPPacket->xIPHeader.ulSourceIPAddress, + pxTCPPacket->xTCPHeader.usSourcePort ); + + /* A pure SYN (without ACK) has come in, create a new socket to answer + it. */ + if( 0 != ulInitialSequenceNumber ) + { + if( pxSocket->u.xTCP.bits.bReuseSocket != pdFALSE_UNSIGNED ) + { + /* The flag bReuseSocket indicates that the same instance of the + listening socket should be used for the connection. */ + pxReturn = pxSocket; + pxSocket->u.xTCP.bits.bPassQueued = pdTRUE_UNSIGNED; + pxSocket->u.xTCP.pxPeerSocket = pxSocket; + } + else + { + /* The socket does not have the bReuseSocket flag set meaning create a + new socket when a connection comes in. */ + pxReturn = NULL; + + if( pxSocket->u.xTCP.usChildCount >= pxSocket->u.xTCP.usBacklog ) + { + FreeRTOS_printf( ( "Check: Socket %u already has %u / %u child%s\n", + pxSocket->usLocalPort, + pxSocket->u.xTCP.usChildCount, + pxSocket->u.xTCP.usBacklog, + pxSocket->u.xTCP.usChildCount == 1 ? "" : "ren" ) ); + prvTCPSendReset( pxNetworkBuffer ); + } + else + { + FreeRTOS_Socket_t *pxNewSocket = ( FreeRTOS_Socket_t * ) + FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_STREAM, FREERTOS_IPPROTO_TCP ); + + if( ( pxNewSocket == NULL ) || ( pxNewSocket == FREERTOS_INVALID_SOCKET ) ) + { + FreeRTOS_debug_printf( ( "TCP: Listen: new socket failed\n" ) ); + prvTCPSendReset( pxNetworkBuffer ); + } + else if( prvTCPSocketCopy( pxNewSocket, pxSocket ) != pdFALSE ) + { + /* The socket will be connected immediately, no time for the + owner to setsockopt's, therefore copy properties of the server + socket to the new socket. Only the binding might fail (due to + lack of resources). */ + pxReturn = pxNewSocket; + } + } + } + } + + if( ( 0 != ulInitialSequenceNumber ) && ( pxReturn != NULL ) ) + { + pxReturn->u.xTCP.usRemotePort = FreeRTOS_htons( pxTCPPacket->xTCPHeader.usSourcePort ); + pxReturn->u.xTCP.ulRemoteIP = FreeRTOS_htonl( pxTCPPacket->xIPHeader.ulSourceIPAddress ); + pxReturn->u.xTCP.xTCPWindow.ulOurSequenceNumber = ulInitialSequenceNumber; + + /* Here is the SYN action. */ + pxReturn->u.xTCP.xTCPWindow.rx.ulCurrentSequenceNumber = FreeRTOS_ntohl( pxTCPPacket->xTCPHeader.ulSequenceNumber ); + prvSocketSetMSS( pxReturn ); + + prvTCPCreateWindow( pxReturn ); + + vTCPStateChange( pxReturn, eSYN_FIRST ); + + /* Make a copy of the header up to the TCP header. It is needed later + on, whenever data must be sent to the peer. */ + memcpy( pxReturn->u.xTCP.xPacket.u.ucLastPacket, pxNetworkBuffer->pucEthernetBuffer, sizeof( pxReturn->u.xTCP.xPacket.u.ucLastPacket ) ); + } + return pxReturn; +} +/*-----------------------------------------------------------*/ + +/* + * Duplicates a socket after a listening socket receives a connection. + */ +static BaseType_t prvTCPSocketCopy( FreeRTOS_Socket_t *pxNewSocket, FreeRTOS_Socket_t *pxSocket ) +{ +struct freertos_sockaddr xAddress; + + pxNewSocket->xReceiveBlockTime = pxSocket->xReceiveBlockTime; + pxNewSocket->xSendBlockTime = pxSocket->xSendBlockTime; + pxNewSocket->ucSocketOptions = pxSocket->ucSocketOptions; + pxNewSocket->u.xTCP.uxRxStreamSize = pxSocket->u.xTCP.uxRxStreamSize; + pxNewSocket->u.xTCP.uxTxStreamSize = pxSocket->u.xTCP.uxTxStreamSize; + pxNewSocket->u.xTCP.uxLittleSpace = pxSocket->u.xTCP.uxLittleSpace; + pxNewSocket->u.xTCP.uxEnoughSpace = pxSocket->u.xTCP.uxEnoughSpace; + pxNewSocket->u.xTCP.uxRxWinSize = pxSocket->u.xTCP.uxRxWinSize; + pxNewSocket->u.xTCP.uxTxWinSize = pxSocket->u.xTCP.uxTxWinSize; + + #if( ipconfigSOCKET_HAS_USER_SEMAPHORE == 1 ) + { + pxNewSocket->pxUserSemaphore = pxSocket->pxUserSemaphore; + } + #endif /* ipconfigSOCKET_HAS_USER_SEMAPHORE */ + + #if( ipconfigUSE_CALLBACKS == 1 ) + { + /* In case call-backs are used, copy them from parent to child. */ + pxNewSocket->u.xTCP.pxHandleConnected = pxSocket->u.xTCP.pxHandleConnected; + pxNewSocket->u.xTCP.pxHandleReceive = pxSocket->u.xTCP.pxHandleReceive; + pxNewSocket->u.xTCP.pxHandleSent = pxSocket->u.xTCP.pxHandleSent; + } + #endif /* ipconfigUSE_CALLBACKS */ + + #if( ipconfigSUPPORT_SELECT_FUNCTION == 1 ) + { + /* Child socket of listening sockets will inherit the Socket Set + Otherwise the owner has no chance of including it into the set. */ + if( pxSocket->pxSocketSet ) + { + pxNewSocket->pxSocketSet = pxSocket->pxSocketSet; + pxNewSocket->xSelectBits = pxSocket->xSelectBits | eSELECT_READ | eSELECT_EXCEPT; + } + } + #endif /* ipconfigSUPPORT_SELECT_FUNCTION */ + + /* And bind it to the same local port as its parent. */ + xAddress.sin_addr = *ipLOCAL_IP_ADDRESS_POINTER; + xAddress.sin_port = FreeRTOS_htons( pxSocket->usLocalPort ); + + #if( ipconfigTCP_HANG_PROTECTION == 1 ) + { + /* Only when there is anti-hanging protection, a socket may become an + orphan temporarily. Once this socket is really connected, the owner of + the server socket will be notified. */ + + /* When bPassQueued is true, the socket is an orphan until it gets + connected. */ + pxNewSocket->u.xTCP.bits.bPassQueued = pdTRUE_UNSIGNED; + pxNewSocket->u.xTCP.pxPeerSocket = pxSocket; + } + #else + { + /* A reference to the new socket may be stored and the socket is marked + as 'passable'. */ + + /* When bPassAccept is pdTRUE_UNSIGNED this socket may be returned in a call to + accept(). */ + pxNewSocket->u.xTCP.bits.bPassAccept = pdTRUE_UNSIGNED; + if(pxSocket->u.xTCP.pxPeerSocket == NULL ) + { + pxSocket->u.xTCP.pxPeerSocket = pxNewSocket; + } + } + #endif + + pxSocket->u.xTCP.usChildCount++; + + FreeRTOS_debug_printf( ( "Gain: Socket %u now has %u / %u child%s\n", + pxSocket->usLocalPort, + pxSocket->u.xTCP.usChildCount, + pxSocket->u.xTCP.usBacklog, + pxSocket->u.xTCP.usChildCount == 1u ? "" : "ren" ) ); + + /* Now bind the child socket to the same port as the listening socket. */ + if( vSocketBind ( pxNewSocket, &xAddress, sizeof( xAddress ), pdTRUE ) != 0 ) + { + FreeRTOS_debug_printf( ( "TCP: Listen: new socket bind error\n" ) ); + vSocketClose( pxNewSocket ); + return pdFALSE; + } + + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +#if( ( ipconfigHAS_DEBUG_PRINTF != 0 ) || ( ipconfigHAS_PRINTF != 0 ) ) + + const char *FreeRTOS_GetTCPStateName( UBaseType_t ulState ) + { + if( ulState >= ( UBaseType_t ) ARRAY_SIZE( pcStateNames ) ) + { + ulState = ( UBaseType_t ) ARRAY_SIZE( pcStateNames ) - 1u; + } + return pcStateNames[ ulState ]; + } + +#endif /* ( ( ipconfigHAS_DEBUG_PRINTF != 0 ) || ( ipconfigHAS_PRINTF != 0 ) ) */ +/*-----------------------------------------------------------*/ + +/* + * In the API accept(), the user asks is there is a new client? As API's can + * not walk through the xBoundTCPSocketsList the IP-task will do this. + */ +BaseType_t xTCPCheckNewClient( FreeRTOS_Socket_t *pxSocket ) +{ +TickType_t xLocalPort = FreeRTOS_htons( pxSocket->usLocalPort ); +ListItem_t *pxIterator; +FreeRTOS_Socket_t *pxFound; +BaseType_t xResult = pdFALSE; + + /* Here xBoundTCPSocketsList can be accessed safely IP-task is the only one + who has access. */ + for( pxIterator = ( ListItem_t * ) listGET_HEAD_ENTRY( &xBoundTCPSocketsList ); + pxIterator != ( ListItem_t * ) listGET_END_MARKER( &xBoundTCPSocketsList ); + pxIterator = ( ListItem_t * ) listGET_NEXT( pxIterator ) ) + { + if( listGET_LIST_ITEM_VALUE( pxIterator ) == xLocalPort ) + { + pxFound = ( FreeRTOS_Socket_t * ) listGET_LIST_ITEM_OWNER( pxIterator ); + if( ( pxFound->ucProtocol == FREERTOS_IPPROTO_TCP ) && ( pxFound->u.xTCP.bits.bPassAccept != pdFALSE_UNSIGNED ) ) + { + pxSocket->u.xTCP.pxPeerSocket = pxFound; + FreeRTOS_debug_printf( ( "xTCPCheckNewClient[0]: client on port %u\n", pxSocket->usLocalPort ) ); + xResult = pdTRUE; + break; + } + } + } + return xResult; +} +/*-----------------------------------------------------------*/ + +#endif /* ipconfigUSE_TCP == 1 */ + +/* Provide access to private members for testing. */ +#ifdef AMAZON_FREERTOS_ENABLE_UNIT_TESTS + #include "aws_freertos_tcp_test_access_tcp_define.h" +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_TCP_WIN.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_TCP_WIN.c new file mode 100644 index 0000000..93fde95 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_TCP_WIN.c @@ -0,0 +1,1998 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +/* + * FreeRTOS_TCP_WIN.c + * Module which handles the TCP windowing schemes for FreeRTOS+TCP. Many + * functions have two versions - one for FreeRTOS+TCP (full) and one for + * FreeRTOS+TCP (lite). + * + * In this module all ports and IP addresses and sequence numbers are + * being stored in host byte-order. + */ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_UDP_IP.h" +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_IP_Private.h" +#include "NetworkBufferManagement.h" +#include "FreeRTOS_TCP_WIN.h" + +/* Constants used for Smoothed Round Trip Time (SRTT). */ +#define winSRTT_INCREMENT_NEW 2 +#define winSRTT_INCREMENT_CURRENT 6 +#define winSRTT_DECREMENT_NEW 1 +#define winSRTT_DECREMENT_CURRENT 7 +#define winSRTT_CAP_mS 50 + +#if( ipconfigUSE_TCP_WIN == 1 ) + + #define xTCPWindowRxNew( pxWindow, ulSequenceNumber, lCount ) xTCPWindowNew( pxWindow, ulSequenceNumber, lCount, pdTRUE ) + + #define xTCPWindowTxNew( pxWindow, ulSequenceNumber, lCount ) xTCPWindowNew( pxWindow, ulSequenceNumber, lCount, pdFALSE ) + + /* The code to send a single Selective ACK (SACK): + * NOP (0x01), NOP (0x01), SACK (0x05), LEN (0x0a), + * followed by a lower and a higher sequence number, + * where LEN is 2 + 2*4 = 10 bytes. */ + #if( ipconfigBYTE_ORDER == pdFREERTOS_BIG_ENDIAN ) + #define OPTION_CODE_SINGLE_SACK ( 0x0101050aUL ) + #else + #define OPTION_CODE_SINGLE_SACK ( 0x0a050101UL ) + #endif + + /* Normal retransmission: + * A packet will be retransmitted after a Retransmit Time-Out (RTO). + * Fast retransmission: + * When 3 packets with a higher sequence number have been acknowledged + * by the peer, it is very unlikely a current packet will ever arrive. + * It will be retransmitted far before the RTO. + */ + #define DUPLICATE_ACKS_BEFORE_FAST_RETRANSMIT ( 3u ) + + /* If there have been several retransmissions (4), decrease the + * size of the transmission window to at most 2 times MSS. + */ + #define MAX_TRANSMIT_COUNT_USING_LARGE_WINDOW ( 4u ) + +#endif /* configUSE_TCP_WIN */ +/*-----------------------------------------------------------*/ + +extern void vListInsertGeneric( List_t * const pxList, ListItem_t * const pxNewListItem, MiniListItem_t * const pxWhere ); + +/* + * All TCP sockets share a pool of segment descriptors (TCPSegment_t) + * Available descriptors are stored in the 'xSegmentList' + * When a socket owns a descriptor, it will either be stored in + * 'xTxSegments' or 'xRxSegments' + * As soon as a package has been confirmed, the descriptor will be returned + * to the segment pool + */ +#if( ipconfigUSE_TCP_WIN == 1 ) + static BaseType_t prvCreateSectors( void ); +#endif /* ipconfigUSE_TCP_WIN == 1 */ + +/* + * Find a segment with a given sequence number in the list of received + * segments: 'pxWindow->xRxSegments'. + */ +#if( ipconfigUSE_TCP_WIN == 1 ) + static TCPSegment_t *xTCPWindowRxFind( TCPWindow_t *pxWindow, uint32_t ulSequenceNumber ); +#endif /* ipconfigUSE_TCP_WIN == 1 */ + +/* + * Allocate a new segment + * The socket will borrow all segments from a common pool: 'xSegmentList', + * which is a list of 'TCPSegment_t' + */ +#if( ipconfigUSE_TCP_WIN == 1 ) + static TCPSegment_t *xTCPWindowNew( TCPWindow_t *pxWindow, uint32_t ulSequenceNumber, int32_t lCount, BaseType_t xIsForRx ); +#endif /* ipconfigUSE_TCP_WIN == 1 */ + +/* When the peer has a close request (FIN flag), the driver will check if + * there are missing packets in the Rx-queue + * It will accept the closure of the connection if both conditions are true: + * - the Rx-queue is empty + * - we've ACK'd the highest Rx sequence number seen + */ +#if( ipconfigUSE_TCP_WIN == 1 ) + BaseType_t xTCPWindowRxEmpty( TCPWindow_t *pxWindow ); +#endif /* ipconfigUSE_TCP_WIN == 1 */ + +/* + * Detaches and returns the head of a queue + */ +#if( ipconfigUSE_TCP_WIN == 1 ) + static TCPSegment_t *xTCPWindowGetHead( List_t *pxList ); +#endif /* ipconfigUSE_TCP_WIN == 1 */ + +/* + * Returns the head of a queue but it won't be detached + */ +#if( ipconfigUSE_TCP_WIN == 1 ) + static TCPSegment_t *xTCPWindowPeekHead( List_t *pxList ); +#endif /* ipconfigUSE_TCP_WIN == 1 */ + +/* + * Free entry pxSegment because it's not used anymore + * The ownership will be passed back to the segment pool + */ +#if( ipconfigUSE_TCP_WIN == 1 ) + static void vTCPWindowFree( TCPSegment_t *pxSegment ); +#endif /* ipconfigUSE_TCP_WIN == 1 */ + +/* + * A segment has been received with sequence number 'ulSequenceNumber', where + * 'ulCurrentSequenceNumber == ulSequenceNumber', which means that exactly this + * segment was expected. xTCPWindowRxConfirm() will check if there is already + * another segment with a sequence number between (ulSequenceNumber) and + * (ulSequenceNumber+xLength). Normally none will be found, because the next Rx + * segment should have a sequence number equal to '(ulSequenceNumber+xLength)'. + */ +#if( ipconfigUSE_TCP_WIN == 1 ) + static TCPSegment_t *xTCPWindowRxConfirm( TCPWindow_t *pxWindow, uint32_t ulSequenceNumber, uint32_t ulLength ); +#endif /* ipconfigUSE_TCP_WIN == 1 */ + +/* + * FreeRTOS+TCP stores data in circular buffers. Calculate the next position to + * store. + */ +#if( ipconfigUSE_TCP_WIN == 1 ) + static int32_t lTCPIncrementTxPosition( int32_t lPosition, int32_t lMax, int32_t lCount ); +#endif /* ipconfigUSE_TCP_WIN == 1 */ + +/* + * This function will look if there is new transmission data. It will return + * true if there is data to be sent. + */ +#if( ipconfigUSE_TCP_WIN == 1 ) + static BaseType_t prvTCPWindowTxHasSpace( TCPWindow_t *pxWindow, uint32_t ulWindowSize ); +#endif /* ipconfigUSE_TCP_WIN == 1 */ + +/* + * An acknowledge was received. See if some outstanding data may be removed + * from the transmission queue(s). + */ +#if( ipconfigUSE_TCP_WIN == 1 ) + static uint32_t prvTCPWindowTxCheckAck( TCPWindow_t *pxWindow, uint32_t ulFirst, uint32_t ulLast ); +#endif /* ipconfigUSE_TCP_WIN == 1 */ + +/* + * A higher Tx block has been acknowledged. Now iterate through the xWaitQueue + * to find a possible condition for a FAST retransmission. + */ +#if( ipconfigUSE_TCP_WIN == 1 ) + static uint32_t prvTCPWindowFastRetransmit( TCPWindow_t *pxWindow, uint32_t ulFirst ); +#endif /* ipconfigUSE_TCP_WIN == 1 */ + +/*-----------------------------------------------------------*/ + +/* TCP segment pool. */ +#if( ipconfigUSE_TCP_WIN == 1 ) + static TCPSegment_t *xTCPSegments = NULL; +#endif /* ipconfigUSE_TCP_WIN == 1 */ + +/* List of free TCP segments. */ +#if( ipconfigUSE_TCP_WIN == 1 ) + static List_t xSegmentList; +#endif + +/* Logging verbosity level. */ +BaseType_t xTCPWindowLoggingLevel = 0; + +#if( ipconfigUSE_TCP_WIN == 1 ) + /* Some 32-bit arithmetic: comparing sequence numbers */ + static portINLINE BaseType_t xSequenceLessThanOrEqual( uint32_t a, uint32_t b ); + static portINLINE BaseType_t xSequenceLessThanOrEqual( uint32_t a, uint32_t b ) + { + /* Test if a <= b + Return true if the unsigned subtraction of (b-a) doesn't generate an + arithmetic overflow. */ + return ( ( b - a ) & 0x80000000UL ) == 0UL; + } +#endif /* ipconfigUSE_TCP_WIN */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + static portINLINE BaseType_t xSequenceLessThan( uint32_t a, uint32_t b ); + static portINLINE BaseType_t xSequenceLessThan( uint32_t a, uint32_t b ) + { + /* Test if a < b */ + return ( ( b - a - 1UL ) & 0x80000000UL ) == 0UL; + } +#endif /* ipconfigUSE_TCP_WIN */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + static portINLINE BaseType_t xSequenceGreaterThan( uint32_t a, uint32_t b ); + static portINLINE BaseType_t xSequenceGreaterThan( uint32_t a, uint32_t b ) + { + /* Test if a > b */ + return ( ( a - b - 1UL ) & 0x80000000UL ) == 0UL; + } +#endif /* ipconfigUSE_TCP_WIN */ + +/*-----------------------------------------------------------*/ +static portINLINE BaseType_t xSequenceGreaterThanOrEqual( uint32_t a, uint32_t b ); +static portINLINE BaseType_t xSequenceGreaterThanOrEqual( uint32_t a, uint32_t b ) +{ + /* Test if a >= b */ + return ( ( a - b ) & 0x80000000UL ) == 0UL; +} +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + static portINLINE void vListInsertFifo( List_t * const pxList, ListItem_t * const pxNewListItem ); + static portINLINE void vListInsertFifo( List_t * const pxList, ListItem_t * const pxNewListItem ) + { + vListInsertGeneric( pxList, pxNewListItem, &pxList->xListEnd ); + } +#endif +/*-----------------------------------------------------------*/ + +static portINLINE void vTCPTimerSet( TCPTimer_t *pxTimer ); +static portINLINE void vTCPTimerSet( TCPTimer_t *pxTimer ) +{ + pxTimer->ulBorn = xTaskGetTickCount ( ); +} +/*-----------------------------------------------------------*/ + +static portINLINE uint32_t ulTimerGetAge( TCPTimer_t *pxTimer ); +static portINLINE uint32_t ulTimerGetAge( TCPTimer_t *pxTimer ) +{ + return ( ( xTaskGetTickCount() - pxTimer->ulBorn ) * portTICK_PERIOD_MS ); +} +/*-----------------------------------------------------------*/ + +/* _HT_ GCC (using the settings that I'm using) checks for every public function if it is +preceded by a prototype. Later this prototype will be located in list.h? */ + +extern void vListInsertGeneric( List_t * const pxList, ListItem_t * const pxNewListItem, MiniListItem_t * const pxWhere ); + +void vListInsertGeneric( List_t * const pxList, ListItem_t * const pxNewListItem, MiniListItem_t * const pxWhere ) +{ + /* Insert a new list item into pxList, it does not sort the list, + but it puts the item just before xListEnd, so it will be the last item + returned by listGET_HEAD_ENTRY() */ + pxNewListItem->pxNext = (struct xLIST_ITEM * configLIST_VOLATILE)pxWhere; + pxNewListItem->pxPrevious = pxWhere->pxPrevious; + pxWhere->pxPrevious->pxNext = pxNewListItem; + pxWhere->pxPrevious = pxNewListItem; + + /* Remember which list the item is in. */ + pxNewListItem->pvContainer = ( void * ) pxList; /* If this line fails to build then ensure configENABLE_BACKWARD_COMPATIBILITY is set to 1 in FreeRTOSConfig.h. */ + + ( pxList->uxNumberOfItems )++; +} +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + + static BaseType_t prvCreateSectors( void ) + { + BaseType_t xIndex, xReturn; + + /* Allocate space for 'xTCPSegments' and store them in 'xSegmentList'. */ + + vListInitialise( &xSegmentList ); + xTCPSegments = ( TCPSegment_t * ) pvPortMallocLarge( ipconfigTCP_WIN_SEG_COUNT * sizeof( xTCPSegments[ 0 ] ) ); + + if( xTCPSegments == NULL ) + { + FreeRTOS_debug_printf( ( "prvCreateSectors: malloc %lu failed\n", + ipconfigTCP_WIN_SEG_COUNT * sizeof( xTCPSegments[ 0 ] ) ) ); + + xReturn = pdFAIL; + } + else + { + /* Clear the allocated space. */ + memset( xTCPSegments, '\0', ipconfigTCP_WIN_SEG_COUNT * sizeof( xTCPSegments[ 0 ] ) ); + + for( xIndex = 0; xIndex < ipconfigTCP_WIN_SEG_COUNT; xIndex++ ) + { + /* Could call vListInitialiseItem here but all data has been + nulled already. Set the owner to a segment descriptor. */ + listSET_LIST_ITEM_OWNER( &( xTCPSegments[ xIndex ].xListItem ), ( void* ) &( xTCPSegments[ xIndex ] ) ); + listSET_LIST_ITEM_OWNER( &( xTCPSegments[ xIndex ].xQueueItem ), ( void* ) &( xTCPSegments[ xIndex ] ) ); + + /* And add it to the pool of available segments */ + vListInsertFifo( &xSegmentList, &( xTCPSegments[xIndex].xListItem ) ); + } + + xReturn = pdPASS; + } + + return xReturn; + } + +#endif /* ipconfigUSE_TCP_WIN == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + + static TCPSegment_t *xTCPWindowRxFind( TCPWindow_t *pxWindow, uint32_t ulSequenceNumber ) + { + const ListItem_t *pxIterator; + const MiniListItem_t* pxEnd; + TCPSegment_t *pxSegment, *pxReturn = NULL; + + /* Find a segment with a given sequence number in the list of received + segments. */ + + pxEnd = ( const MiniListItem_t* )listGET_END_MARKER( &pxWindow->xRxSegments ); + + for( pxIterator = ( const ListItem_t * ) listGET_NEXT( pxEnd ); + pxIterator != ( const ListItem_t * ) pxEnd; + pxIterator = ( const ListItem_t * ) listGET_NEXT( pxIterator ) ) + { + pxSegment = ( TCPSegment_t * ) listGET_LIST_ITEM_OWNER( pxIterator ); + + if( pxSegment->ulSequenceNumber == ulSequenceNumber ) + { + pxReturn = pxSegment; + break; + } + } + + return pxReturn; + } + +#endif /* ipconfigUSE_TCP_WIN == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + + static TCPSegment_t *xTCPWindowNew( TCPWindow_t *pxWindow, uint32_t ulSequenceNumber, int32_t lCount, BaseType_t xIsForRx ) + { + TCPSegment_t *pxSegment; + ListItem_t * pxItem; + + /* Allocate a new segment. The socket will borrow all segments from a + common pool: 'xSegmentList', which is a list of 'TCPSegment_t' */ + if( listLIST_IS_EMPTY( &xSegmentList ) != pdFALSE ) + { + /* If the TCP-stack runs out of segments, you might consider + increasing 'ipconfigTCP_WIN_SEG_COUNT'. */ + FreeRTOS_debug_printf( ( "xTCPWindow%cxNew: Error: all segments occupied\n", xIsForRx ? 'R' : 'T' ) ); + pxSegment = NULL; + } + else + { + /* Pop the item at the head of the list. Semaphore protection is + not required as only the IP task will call these functions. */ + pxItem = ( ListItem_t * ) listGET_HEAD_ENTRY( &xSegmentList ); + pxSegment = ( TCPSegment_t * ) listGET_LIST_ITEM_OWNER( pxItem ); + + configASSERT( pxItem != NULL ); + configASSERT( pxSegment != NULL ); + + /* Remove the item from xSegmentList. */ + uxListRemove( pxItem ); + + /* Add it to either the connections' Rx or Tx queue. */ + vListInsertFifo( xIsForRx ? &pxWindow->xRxSegments : &pxWindow->xTxSegments, pxItem ); + + /* And set the segment's timer to zero */ + vTCPTimerSet( &pxSegment->xTransmitTimer ); + + pxSegment->u.ulFlags = 0; + pxSegment->u.bits.bIsForRx = ( xIsForRx != 0 ); + pxSegment->lMaxLength = lCount; + pxSegment->lDataLength = lCount; + pxSegment->ulSequenceNumber = ulSequenceNumber; + #if( ipconfigHAS_DEBUG_PRINTF != 0 ) + { + static UBaseType_t xLowestLength = ipconfigTCP_WIN_SEG_COUNT; + UBaseType_t xLength = listCURRENT_LIST_LENGTH( &xSegmentList ); + + if( xLowestLength > xLength ) + { + xLowestLength = xLength; + } + } + #endif /* ipconfigHAS_DEBUG_PRINTF */ + } + + return pxSegment; + } + +#endif /* ipconfigUSE_TCP_WIN == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + + BaseType_t xTCPWindowRxEmpty( TCPWindow_t *pxWindow ) + { + BaseType_t xReturn; + + /* When the peer has a close request (FIN flag), the driver will check + if there are missing packets in the Rx-queue. It will accept the + closure of the connection if both conditions are true: + - the Rx-queue is empty + - the highest Rx sequence number has been ACK'ed */ + if( listLIST_IS_EMPTY( ( &pxWindow->xRxSegments ) ) == pdFALSE ) + { + /* Rx data has been stored while earlier packets were missing. */ + xReturn = pdFALSE; + } + else if( xSequenceGreaterThanOrEqual( pxWindow->rx.ulCurrentSequenceNumber, pxWindow->rx.ulHighestSequenceNumber ) != pdFALSE ) + { + /* No Rx packets are being stored and the highest sequence number + that has been received has been ACKed. */ + xReturn = pdTRUE; + } + else + { + FreeRTOS_debug_printf( ( "xTCPWindowRxEmpty: cur %lu highest %lu (empty)\n", + ( pxWindow->rx.ulCurrentSequenceNumber - pxWindow->rx.ulFirstSequenceNumber ), + ( pxWindow->rx.ulHighestSequenceNumber - pxWindow->rx.ulFirstSequenceNumber ) ) ); + xReturn = pdFALSE; + } + + return xReturn; + } + +#endif /* ipconfigUSE_TCP_WIN == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + + static TCPSegment_t *xTCPWindowGetHead( List_t *pxList ) + { + TCPSegment_t *pxSegment; + ListItem_t * pxItem; + + /* Detaches and returns the head of a queue. */ + if( listLIST_IS_EMPTY( pxList ) != pdFALSE ) + { + pxSegment = NULL; + } + else + { + pxItem = ( ListItem_t * ) listGET_HEAD_ENTRY( pxList ); + pxSegment = ( TCPSegment_t * ) listGET_LIST_ITEM_OWNER( pxItem ); + + uxListRemove( pxItem ); + } + + return pxSegment; + } + +#endif /* ipconfigUSE_TCP_WIN == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + + static TCPSegment_t *xTCPWindowPeekHead( List_t *pxList ) + { + ListItem_t *pxItem; + TCPSegment_t *pxReturn; + + /* Returns the head of a queue but it won't be detached. */ + if( listLIST_IS_EMPTY( pxList ) != pdFALSE ) + { + pxReturn = NULL; + } + else + { + pxItem = ( ListItem_t * ) listGET_HEAD_ENTRY( pxList ); + pxReturn = ( TCPSegment_t * ) listGET_LIST_ITEM_OWNER( pxItem ); + } + + return pxReturn; + } + +#endif /* ipconfigUSE_TCP_WIN == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + + static void vTCPWindowFree( TCPSegment_t *pxSegment ) + { + /* Free entry pxSegment because it's not used any more. The ownership + will be passed back to the segment pool. + + Unlink it from one of the queues, if any. */ + if( listLIST_ITEM_CONTAINER( &( pxSegment->xQueueItem ) ) != NULL ) + { + uxListRemove( &( pxSegment->xQueueItem ) ); + } + + pxSegment->ulSequenceNumber = 0u; + pxSegment->lDataLength = 0l; + pxSegment->u.ulFlags = 0u; + + /* Take it out of xRxSegments/xTxSegments */ + if( listLIST_ITEM_CONTAINER( &( pxSegment->xListItem ) ) != NULL ) + { + uxListRemove( &( pxSegment->xListItem ) ); + } + + /* Return it to xSegmentList */ + vListInsertFifo( &xSegmentList, &( pxSegment->xListItem ) ); + } + +#endif /* ipconfigUSE_TCP_WIN == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + + void vTCPWindowDestroy( TCPWindow_t *pxWindow ) + { + List_t * pxSegments; + BaseType_t xRound; + TCPSegment_t *pxSegment; + + /* Destroy a window. A TCP window doesn't serve any more. Return all + owned segments to the pool. In order to save code, it will make 2 rounds, + one to remove the segments from xRxSegments, and a second round to clear + xTxSegments*/ + for( xRound = 0; xRound < 2; xRound++ ) + { + if( xRound != 0 ) + { + pxSegments = &( pxWindow->xRxSegments ); + } + else + { + pxSegments = &( pxWindow->xTxSegments ); + } + + if( listLIST_IS_INITIALISED( pxSegments ) != pdFALSE ) + { + while( listCURRENT_LIST_LENGTH( pxSegments ) > 0U ) + { + pxSegment = ( TCPSegment_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxSegments ); + vTCPWindowFree( pxSegment ); + } + } + } + } + +#endif /* ipconfigUSE_TCP_WIN == 1 */ +/*-----------------------------------------------------------*/ + +void vTCPWindowCreate( TCPWindow_t *pxWindow, uint32_t ulRxWindowLength, + uint32_t ulTxWindowLength, uint32_t ulAckNumber, uint32_t ulSequenceNumber, uint32_t ulMSS ) +{ + /* Create and initialize a window. */ + + #if( ipconfigUSE_TCP_WIN == 1 ) + { + if( xTCPSegments == NULL ) + { + prvCreateSectors(); + } + + vListInitialise( &pxWindow->xTxSegments ); + vListInitialise( &pxWindow->xRxSegments ); + + vListInitialise( &pxWindow->xPriorityQueue ); /* Priority queue: segments which must be sent immediately */ + vListInitialise( &pxWindow->xTxQueue ); /* Transmit queue: segments queued for transmission */ + vListInitialise( &pxWindow->xWaitQueue ); /* Waiting queue: outstanding segments */ + } + #endif /* ipconfigUSE_TCP_WIN == 1 */ + + if( xTCPWindowLoggingLevel != 0 ) + { + FreeRTOS_debug_printf( ( "vTCPWindowCreate: for WinLen = Rx/Tx: %lu/%lu\n", + ulRxWindowLength, ulTxWindowLength ) ); + } + + pxWindow->xSize.ulRxWindowLength = ulRxWindowLength; + pxWindow->xSize.ulTxWindowLength = ulTxWindowLength; + + vTCPWindowInit( pxWindow, ulAckNumber, ulSequenceNumber, ulMSS ); +} +/*-----------------------------------------------------------*/ + +void vTCPWindowInit( TCPWindow_t *pxWindow, uint32_t ulAckNumber, uint32_t ulSequenceNumber, uint32_t ulMSS ) +{ +const int32_t l500ms = 500; + + pxWindow->u.ulFlags = 0ul; + pxWindow->u.bits.bHasInit = pdTRUE_UNSIGNED; + + if( ulMSS != 0ul ) + { + if( pxWindow->usMSSInit != 0u ) + { + pxWindow->usMSSInit = ( uint16_t ) ulMSS; + } + + if( ( ulMSS < ( uint32_t ) pxWindow->usMSS ) || ( pxWindow->usMSS == 0u ) ) + { + pxWindow->xSize.ulRxWindowLength = ( pxWindow->xSize.ulRxWindowLength / ulMSS ) * ulMSS; + pxWindow->usMSS = ( uint16_t ) ulMSS; + } + } + + #if( ipconfigUSE_TCP_WIN == 0 ) + { + pxWindow->xTxSegment.lMaxLength = ( int32_t ) pxWindow->usMSS; + } + #endif /* ipconfigUSE_TCP_WIN == 1 */ + + /*Start with a timeout of 2 * 500 ms (1 sec). */ + pxWindow->lSRTT = l500ms; + + /* Just for logging, to print relative sequence numbers. */ + pxWindow->rx.ulFirstSequenceNumber = ulAckNumber; + + /* The segment asked for in the next transmission. */ + pxWindow->rx.ulCurrentSequenceNumber = ulAckNumber; + + /* The right-hand side of the receive window. */ + pxWindow->rx.ulHighestSequenceNumber = ulAckNumber; + + pxWindow->tx.ulFirstSequenceNumber = ulSequenceNumber; + + /* The segment asked for in next transmission. */ + pxWindow->tx.ulCurrentSequenceNumber = ulSequenceNumber; + + /* The sequence number given to the next outgoing byte to be added is + maintained by lTCPWindowTxAdd(). */ + pxWindow->ulNextTxSequenceNumber = ulSequenceNumber; + + /* The right-hand side of the transmit window. */ + pxWindow->tx.ulHighestSequenceNumber = ulSequenceNumber; + pxWindow->ulOurSequenceNumber = ulSequenceNumber; +} +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + + void vTCPSegmentCleanup( void ) + { + /* Free and clear the TCP segments pointer. This function should only be called + * once FreeRTOS+TCP will no longer be used. No thread-safety is provided for this + * function. */ + if( xTCPSegments != NULL ) + { + vPortFreeLarge( xTCPSegments ); + xTCPSegments = NULL; + } + } + +#endif /* ipconfgiUSE_TCP_WIN == 1 */ +/*-----------------------------------------------------------*/ + +/*============================================================================= + * + * ###### # # + * # # # # + * # # # # + * # # #### + * ###### ## + * # ## #### + * # # # # + * # # # # + * ### ## # # + * Rx functions + * + *=============================================================================*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + + static TCPSegment_t *xTCPWindowRxConfirm( TCPWindow_t *pxWindow, uint32_t ulSequenceNumber, uint32_t ulLength ) + { + TCPSegment_t *pxBest = NULL; + const ListItem_t *pxIterator; + uint32_t ulNextSequenceNumber = ulSequenceNumber + ulLength; + const MiniListItem_t* pxEnd = ( const MiniListItem_t* ) listGET_END_MARKER( &pxWindow->xRxSegments ); + TCPSegment_t *pxSegment; + + /* A segment has been received with sequence number 'ulSequenceNumber', + where 'ulCurrentSequenceNumber == ulSequenceNumber', which means that + exactly this segment was expected. xTCPWindowRxConfirm() will check if + there is already another segment with a sequence number between (ulSequenceNumber) + and (ulSequenceNumber+ulLength). Normally none will be found, because + the next RX segment should have a sequence number equal to + '(ulSequenceNumber+ulLength)'. */ + + /* Iterate through all RX segments that are stored: */ + for( pxIterator = ( const ListItem_t * ) listGET_NEXT( pxEnd ); + pxIterator != ( const ListItem_t * ) pxEnd; + pxIterator = ( const ListItem_t * ) listGET_NEXT( pxIterator ) ) + { + pxSegment = ( TCPSegment_t * ) listGET_LIST_ITEM_OWNER( pxIterator ); + /* And see if there is a segment for which: + 'ulSequenceNumber' <= 'pxSegment->ulSequenceNumber' < 'ulNextSequenceNumber' + If there are more matching segments, the one with the lowest sequence number + shall be taken */ + if( ( xSequenceGreaterThanOrEqual( pxSegment->ulSequenceNumber, ulSequenceNumber ) != 0 ) && + ( xSequenceLessThan( pxSegment->ulSequenceNumber, ulNextSequenceNumber ) != 0 ) ) + { + if( ( pxBest == NULL ) || ( xSequenceLessThan( pxSegment->ulSequenceNumber, pxBest->ulSequenceNumber ) != 0 ) ) + { + pxBest = pxSegment; + } + } + } + + if( ( pxBest != NULL ) && + ( ( pxBest->ulSequenceNumber != ulSequenceNumber ) || ( pxBest->lDataLength != ( int32_t ) ulLength ) ) ) + { + FreeRTOS_flush_logging(); + FreeRTOS_debug_printf( ( "xTCPWindowRxConfirm[%u]: search %lu (+%ld=%lu) found %lu (+%ld=%lu)\n", + pxWindow->usPeerPortNumber, + ulSequenceNumber - pxWindow->rx.ulFirstSequenceNumber, + ulLength, + ulSequenceNumber + ulLength - pxWindow->rx.ulFirstSequenceNumber, + pxBest->ulSequenceNumber - pxWindow->rx.ulFirstSequenceNumber, + pxBest->lDataLength, + pxBest->ulSequenceNumber + ( ( uint32_t ) pxBest->lDataLength ) - pxWindow->rx.ulFirstSequenceNumber ) ); + } + + return pxBest; + } + +#endif /* ipconfgiUSE_TCP_WIN == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + + int32_t lTCPWindowRxCheck( TCPWindow_t *pxWindow, uint32_t ulSequenceNumber, uint32_t ulLength, uint32_t ulSpace ) + { + uint32_t ulCurrentSequenceNumber, ulLast, ulSavedSequenceNumber; + int32_t lReturn, lDistance; + TCPSegment_t *pxFound; + + /* If lTCPWindowRxCheck( ) returns == 0, the packet will be passed + directly to user (segment is expected). If it returns a positive + number, an earlier packet is missing, but this packet may be stored. + If negative, the packet has already been stored, or it is out-of-order, + or there is not enough space. + + As a side-effect, pxWindow->ulUserDataLength will get set to non-zero, + if more Rx data may be passed to the user after this packet. */ + + ulCurrentSequenceNumber = pxWindow->rx.ulCurrentSequenceNumber; + + /* For Selective Ack (SACK), used when out-of-sequence data come in. */ + pxWindow->ucOptionLength = 0u; + + /* Non-zero if TCP-windows contains data which must be popped. */ + pxWindow->ulUserDataLength = 0ul; + + if( ulCurrentSequenceNumber == ulSequenceNumber ) + { + /* This is the packet with the lowest sequence number we're waiting + for. It can be passed directly to the rx stream. */ + if( ulLength > ulSpace ) + { + FreeRTOS_debug_printf( ( "lTCPWindowRxCheck: Refuse %lu bytes, due to lack of space (%lu)\n", ulLength, ulSpace ) ); + lReturn = -1; + } + else + { + ulCurrentSequenceNumber += ulLength; + + if( listCURRENT_LIST_LENGTH( &( pxWindow->xRxSegments ) ) != 0 ) + { + ulSavedSequenceNumber = ulCurrentSequenceNumber; + + /* Clean up all sequence received between ulSequenceNumber and ulSequenceNumber + ulLength since they are duplicated. + If the server is forced to retransmit packets several time in a row it might send a batch of concatenated packet for speed. + So we cannot rely on the packets between ulSequenceNumber and ulSequenceNumber + ulLength to be sequential and it is better to just + clean them out. */ + do + { + pxFound = xTCPWindowRxConfirm( pxWindow, ulSequenceNumber, ulLength ); + + if ( pxFound != NULL ) + { + /* Remove it because it will be passed to user directly. */ + vTCPWindowFree( pxFound ); + } + } while ( pxFound ); + + /* Check for following segments that are already in the + queue and increment ulCurrentSequenceNumber. */ + while( ( pxFound = xTCPWindowRxFind( pxWindow, ulCurrentSequenceNumber ) ) != NULL ) + { + ulCurrentSequenceNumber += ( uint32_t ) pxFound->lDataLength; + + /* As all packet below this one have been passed to the + user it can be discarded. */ + vTCPWindowFree( pxFound ); + } + + if( ulSavedSequenceNumber != ulCurrentSequenceNumber ) + { + /* After the current data-package, there is more data + to be popped. */ + pxWindow->ulUserDataLength = ulCurrentSequenceNumber - ulSavedSequenceNumber; + + if( xTCPWindowLoggingLevel >= 1 ) + { + FreeRTOS_debug_printf( ( "lTCPWindowRxCheck[%d,%d]: retran %lu (Found %lu bytes at %lu cnt %ld)\n", + pxWindow->usPeerPortNumber, pxWindow->usOurPortNumber, + ulSequenceNumber - pxWindow->rx.ulFirstSequenceNumber, + pxWindow->ulUserDataLength, + ulSavedSequenceNumber - pxWindow->rx.ulFirstSequenceNumber, + listCURRENT_LIST_LENGTH( &pxWindow->xRxSegments ) ) ); + } + } + } + + pxWindow->rx.ulCurrentSequenceNumber = ulCurrentSequenceNumber; + + /* Packet was expected, may be passed directly to the socket + buffer or application. Store the packet at offset 0. */ + lReturn = 0; + } + } + else if( ulCurrentSequenceNumber == ( ulSequenceNumber + 1UL ) ) + { + /* Looks like a TCP keep-alive message. Do not accept/store Rx data + ulUserDataLength = 0. Not packet out-of-sync. Just reply to it. */ + lReturn = -1; + } + else + { + /* The packet is not the one expected. See if it falls within the Rx + window so it can be stored. */ + + /* An "out-of-sequence" segment was received, must have missed one. + Prepare a SACK (Selective ACK). */ + ulLast = ulSequenceNumber + ulLength; + lDistance = ( int32_t ) ( ulLast - ulCurrentSequenceNumber ); + + if( lDistance <= 0 ) + { + /* An earlier has been received, must be a retransmission of a + packet that has been accepted already. No need to send out a + Selective ACK (SACK). */ + lReturn = -1; + } + else if( lDistance > ( int32_t ) ulSpace ) + { + /* The new segment is ahead of rx.ulCurrentSequenceNumber. The + sequence number of this packet is too far ahead, ignore it. */ + FreeRTOS_debug_printf( ( "lTCPWindowRxCheck: Refuse %lu+%lu bytes, due to lack of space (%lu)\n", lDistance, ulLength, ulSpace ) ); + lReturn = -1; + } + else + { + /* See if there is more data in a contiguous block to make the + SACK describe a longer range of data. */ + + /* TODO: SACK's may also be delayed for a short period + * This is useful because subsequent packets will be SACK'd with + * single one message + */ + while( ( pxFound = xTCPWindowRxFind( pxWindow, ulLast ) ) != NULL ) + { + ulLast += ( uint32_t ) pxFound->lDataLength; + } + + if( xTCPWindowLoggingLevel >= 1 ) + { + FreeRTOS_debug_printf( ( "lTCPWindowRxCheck[%d,%d]: seqnr %lu exp %lu (dist %ld) SACK to %lu\n", + pxWindow->usPeerPortNumber, pxWindow->usOurPortNumber, + ulSequenceNumber - pxWindow->rx.ulFirstSequenceNumber, + ulCurrentSequenceNumber - pxWindow->rx.ulFirstSequenceNumber, + ( BaseType_t ) ( ulSequenceNumber - ulCurrentSequenceNumber ), /* want this signed */ + ulLast - pxWindow->rx.ulFirstSequenceNumber ) ); + } + + /* Now prepare the SACK message. + Code OPTION_CODE_SINGLE_SACK already in network byte order. */ + pxWindow->ulOptionsData[0] = OPTION_CODE_SINGLE_SACK; + + /* First sequence number that we received. */ + pxWindow->ulOptionsData[1] = FreeRTOS_htonl( ulSequenceNumber ); + + /* Last + 1 */ + pxWindow->ulOptionsData[2] = FreeRTOS_htonl( ulLast ); + + /* Which make 12 (3*4) option bytes. */ + pxWindow->ucOptionLength = 3 * sizeof( pxWindow->ulOptionsData[ 0 ] ); + + pxFound = xTCPWindowRxFind( pxWindow, ulSequenceNumber ); + + if( pxFound != NULL ) + { + /* This out-of-sequence packet has been received for a + second time. It is already stored but do send a SACK + again. */ + lReturn = -1; + } + else + { + pxFound = xTCPWindowRxNew( pxWindow, ulSequenceNumber, ( int32_t ) ulLength ); + + if( pxFound == NULL ) + { + /* Can not send a SACK, because the segment cannot be + stored. */ + pxWindow->ucOptionLength = 0u; + + /* Needs to be stored but there is no segment + available. */ + lReturn = -1; + } + else + { + if( xTCPWindowLoggingLevel != 0 ) + { + FreeRTOS_debug_printf( ( "lTCPWindowRxCheck[%u,%u]: seqnr %lu (cnt %lu)\n", + pxWindow->usPeerPortNumber, pxWindow->usOurPortNumber, ulSequenceNumber - pxWindow->rx.ulFirstSequenceNumber, + listCURRENT_LIST_LENGTH( &pxWindow->xRxSegments ) ) ); + FreeRTOS_flush_logging( ); + } + + /* Return a positive value. The packet may be accepted + and stored but an earlier packet is still missing. */ + lReturn = ( int32_t ) ( ulSequenceNumber - ulCurrentSequenceNumber ); + } + } + } + } + + return lReturn; + } + +#endif /* ipconfgiUSE_TCP_WIN == 1 */ +/*-----------------------------------------------------------*/ + +/*============================================================================= + * + * ######### # # + * # # # # # + * # # # + * # #### + * # ## + * # #### + * # # # + * # # # + * ##### # # + * + * Tx functions + * + *=============================================================================*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + + static int32_t lTCPIncrementTxPosition( int32_t lPosition, int32_t lMax, int32_t lCount ) + { + /* +TCP stores data in circular buffers. Calculate the next position to + store. */ + lPosition += lCount; + if( lPosition >= lMax ) + { + lPosition -= lMax; + } + + return lPosition; + } + +#endif /* ipconfigUSE_TCP_WIN == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + + int32_t lTCPWindowTxAdd( TCPWindow_t *pxWindow, uint32_t ulLength, int32_t lPosition, int32_t lMax ) + { + int32_t lBytesLeft = ( int32_t ) ulLength, lToWrite; + int32_t lDone = 0; + TCPSegment_t *pxSegment = pxWindow->pxHeadSegment; + + /* Puts a message in the Tx-window (after buffer size has been + verified). */ + if( pxSegment != NULL ) + { + if( pxSegment->lDataLength < pxSegment->lMaxLength ) + { + if( ( pxSegment->u.bits.bOutstanding == pdFALSE_UNSIGNED ) && ( pxSegment->lDataLength != 0 ) ) + { + /* Adding data to a segment that was already in the TX queue. It + will be filled-up to a maximum of MSS (maximum segment size). */ + lToWrite = FreeRTOS_min_int32( lBytesLeft, pxSegment->lMaxLength - pxSegment->lDataLength ); + + pxSegment->lDataLength += lToWrite; + + if( pxSegment->lDataLength >= pxSegment->lMaxLength ) + { + /* This segment is full, don't add more bytes. */ + pxWindow->pxHeadSegment = NULL; + } + + lBytesLeft -= lToWrite; + + /* ulNextTxSequenceNumber is the sequence number of the next byte to + be stored for transmission. */ + pxWindow->ulNextTxSequenceNumber += ( uint32_t ) lToWrite; + + /* Increased the return value. */ + lDone += lToWrite; + + /* Some detailed logging, for those who're interested. */ + if( ( xTCPWindowLoggingLevel >= 2 ) && ( ipconfigTCP_MAY_LOG_PORT( pxWindow->usOurPortNumber ) != 0 ) ) + { + FreeRTOS_debug_printf( ( "lTCPWindowTxAdd: Add %4lu bytes for seqNr %lu len %4lu (nxt %lu) pos %lu\n", + ulLength, + pxSegment->ulSequenceNumber - pxWindow->tx.ulFirstSequenceNumber, + pxSegment->lDataLength, + pxWindow->ulNextTxSequenceNumber - pxWindow->tx.ulFirstSequenceNumber, + pxSegment->lStreamPos ) ); + FreeRTOS_flush_logging( ); + } + + /* Calculate the next position in the circular data buffer, knowing + its maximum length 'lMax'. */ + lPosition = lTCPIncrementTxPosition( lPosition, lMax, lToWrite ); + } + } + } + + while( lBytesLeft > 0 ) + { + /* The current transmission segment is full, create new segments as + needed. */ + pxSegment = xTCPWindowTxNew( pxWindow, pxWindow->ulNextTxSequenceNumber, pxWindow->usMSS ); + + if( pxSegment != NULL ) + { + /* Store as many as needed, but no more than the maximum + (MSS). */ + lToWrite = FreeRTOS_min_int32( lBytesLeft, pxSegment->lMaxLength ); + + pxSegment->lDataLength = lToWrite; + pxSegment->lStreamPos = lPosition; + lBytesLeft -= lToWrite; + lPosition = lTCPIncrementTxPosition( lPosition, lMax, lToWrite ); + pxWindow->ulNextTxSequenceNumber += ( uint32_t ) lToWrite; + lDone += lToWrite; + + /* Link this segment in the Tx-Queue. */ + vListInsertFifo( &( pxWindow->xTxQueue ), &( pxSegment->xQueueItem ) ); + + /* Let 'pxHeadSegment' point to this segment if there is still + space. */ + if( pxSegment->lDataLength < pxSegment->lMaxLength ) + { + pxWindow->pxHeadSegment = pxSegment; + } + else + { + pxWindow->pxHeadSegment = NULL; + } + + if( ipconfigTCP_MAY_LOG_PORT( pxWindow->usOurPortNumber ) != 0 ) + { + if( ( xTCPWindowLoggingLevel >= 3 ) || + ( ( xTCPWindowLoggingLevel >= 2 ) && ( pxWindow->pxHeadSegment != NULL ) ) ) + { + FreeRTOS_debug_printf( ( "lTCPWindowTxAdd: New %4ld bytes for seqNr %lu len %4lu (nxt %lu) pos %lu\n", + ulLength, + pxSegment->ulSequenceNumber - pxWindow->tx.ulFirstSequenceNumber, + pxSegment->lDataLength, + pxWindow->ulNextTxSequenceNumber - pxWindow->tx.ulFirstSequenceNumber, + pxSegment->lStreamPos ) ); + FreeRTOS_flush_logging( ); + } + } + } + else + { + /* A sever situation: running out of segments for transmission. + No more data can be sent at the moment. */ + if( lDone != 0 ) + { + FreeRTOS_debug_printf( ( "lTCPWindowTxAdd: Sorry all buffers full (cancel %ld bytes)\n", lBytesLeft ) ); + } + break; + } + } + + return lDone; + } + +#endif /* ipconfigUSE_TCP_WIN == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + + BaseType_t xTCPWindowTxDone( TCPWindow_t *pxWindow ) + { + return listLIST_IS_EMPTY( ( &pxWindow->xTxSegments) ); + } + +#endif /* ipconfigUSE_TCP_WIN == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + + static BaseType_t prvTCPWindowTxHasSpace( TCPWindow_t *pxWindow, uint32_t ulWindowSize ) + { + uint32_t ulTxOutstanding; + BaseType_t xHasSpace; + TCPSegment_t *pxSegment; + + /* This function will look if there is new transmission data. It will + return true if there is data to be sent. */ + + pxSegment = xTCPWindowPeekHead( &( pxWindow->xTxQueue ) ); + + if( pxSegment == NULL ) + { + xHasSpace = pdFALSE; + } + else + { + /* How much data is outstanding, i.e. how much data has been sent + but not yet acknowledged ? */ + if( pxWindow->tx.ulHighestSequenceNumber >= pxWindow->tx.ulCurrentSequenceNumber ) + { + ulTxOutstanding = pxWindow->tx.ulHighestSequenceNumber - pxWindow->tx.ulCurrentSequenceNumber; + } + else + { + ulTxOutstanding = 0UL; + } + + /* Subtract this from the peer's space. */ + ulWindowSize -= FreeRTOS_min_uint32( ulWindowSize, ulTxOutstanding ); + + /* See if the next segment may be sent. */ + if( ulWindowSize >= ( uint32_t ) pxSegment->lDataLength ) + { + xHasSpace = pdTRUE; + } + else + { + xHasSpace = pdFALSE; + } + + /* If 'xHasSpace', it looks like the peer has at least space for 1 + more new segment of size MSS. xSize.ulTxWindowLength is the self-imposed + limitation of the transmission window (in case of many resends it + may be decreased). */ + if( ( ulTxOutstanding != 0UL ) && ( pxWindow->xSize.ulTxWindowLength < ulTxOutstanding + ( ( uint32_t ) pxSegment->lDataLength ) ) ) + { + xHasSpace = pdFALSE; + } + } + + return xHasSpace; + } + +#endif /* ipconfigUSE_TCP_WIN == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + + BaseType_t xTCPWindowTxHasData( TCPWindow_t *pxWindow, uint32_t ulWindowSize, TickType_t *pulDelay ) + { + TCPSegment_t *pxSegment; + BaseType_t xReturn; + TickType_t ulAge, ulMaxAge; + + *pulDelay = 0u; + + if( listLIST_IS_EMPTY( &pxWindow->xPriorityQueue ) == pdFALSE ) + { + /* No need to look at retransmissions or new transmission as long as + there are priority segments. *pulDelay equals zero, meaning it must + be sent out immediately. */ + xReturn = pdTRUE; + } + else + { + pxSegment = xTCPWindowPeekHead( &( pxWindow->xWaitQueue ) ); + + if( pxSegment != NULL ) + { + /* There is an outstanding segment, see if it is time to resend + it. */ + ulAge = ulTimerGetAge( &pxSegment->xTransmitTimer ); + + /* After a packet has been sent for the first time, it will wait + '1 * lSRTT' ms for an ACK. A second time it will wait '2 * lSRTT' ms, + each time doubling the time-out */ + ulMaxAge = ( 1u << pxSegment->u.bits.ucTransmitCount ) * ( ( uint32_t ) pxWindow->lSRTT ); + + if( ulMaxAge > ulAge ) + { + /* A segment must be sent after this amount of msecs */ + *pulDelay = ulMaxAge - ulAge; + } + + xReturn = pdTRUE; + } + else + { + /* No priority segment, no outstanding data, see if there is new + transmission data. */ + pxSegment = xTCPWindowPeekHead( &pxWindow->xTxQueue ); + + /* See if it fits in the peer's reception window. */ + if( pxSegment == NULL ) + { + xReturn = pdFALSE; + } + else if( prvTCPWindowTxHasSpace( pxWindow, ulWindowSize ) == pdFALSE ) + { + /* Too many outstanding messages. */ + xReturn = pdFALSE; + } + else if( ( pxWindow->u.bits.bSendFullSize != pdFALSE_UNSIGNED ) && ( pxSegment->lDataLength < pxSegment->lMaxLength ) ) + { + /* 'bSendFullSize' is a special optimisation. If true, the + driver will only sent completely filled packets (of MSS + bytes). */ + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + } + } + + return xReturn; + } + +#endif /* ipconfigUSE_TCP_WIN == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + + uint32_t ulTCPWindowTxGet( TCPWindow_t *pxWindow, uint32_t ulWindowSize, int32_t *plPosition ) + { + TCPSegment_t *pxSegment; + uint32_t ulMaxTime; + uint32_t ulReturn = ~0UL; + + + /* Fetches data to be sent-out now. + + Priority messages: segments with a resend need no check current sliding + window size. */ + pxSegment = xTCPWindowGetHead( &( pxWindow->xPriorityQueue ) ); + pxWindow->ulOurSequenceNumber = pxWindow->tx.ulHighestSequenceNumber; + + if( pxSegment == NULL ) + { + /* Waiting messages: outstanding messages with a running timer + neither check peer's reception window size because these packets + have been sent earlier. */ + pxSegment = xTCPWindowPeekHead( &( pxWindow->xWaitQueue ) ); + + if( pxSegment != NULL ) + { + /* Do check the timing. */ + ulMaxTime = ( 1u << pxSegment->u.bits.ucTransmitCount ) * ( ( uint32_t ) pxWindow->lSRTT ); + + if( ulTimerGetAge( &pxSegment->xTransmitTimer ) > ulMaxTime ) + { + /* A normal (non-fast) retransmission. Move it from the + head of the waiting queue. */ + pxSegment = xTCPWindowGetHead( &( pxWindow->xWaitQueue ) ); + pxSegment->u.bits.ucDupAckCount = pdFALSE_UNSIGNED; + + /* Some detailed logging. */ + if( ( xTCPWindowLoggingLevel != 0 ) && ( ipconfigTCP_MAY_LOG_PORT( pxWindow->usOurPortNumber ) != 0 ) ) + { + FreeRTOS_debug_printf( ( "ulTCPWindowTxGet[%u,%u]: WaitQueue %ld bytes for sequence number %lu (%lX)\n", + pxWindow->usPeerPortNumber, + pxWindow->usOurPortNumber, + pxSegment->lDataLength, + pxSegment->ulSequenceNumber - pxWindow->tx.ulFirstSequenceNumber, + pxSegment->ulSequenceNumber ) ); + FreeRTOS_flush_logging( ); + } + } + else + { + pxSegment = NULL; + } + } + + if( pxSegment == NULL ) + { + /* New messages: sent-out for the first time. Check current + sliding window size of peer. */ + pxSegment = xTCPWindowPeekHead( &( pxWindow->xTxQueue ) ); + + if( pxSegment == NULL ) + { + /* No segments queued. */ + ulReturn = 0UL; + } + else if( ( pxWindow->u.bits.bSendFullSize != pdFALSE_UNSIGNED ) && ( pxSegment->lDataLength < pxSegment->lMaxLength ) ) + { + /* A segment has been queued but the driver waits until it + has a full size of MSS. */ + ulReturn = 0; + } + else if( prvTCPWindowTxHasSpace( pxWindow, ulWindowSize ) == pdFALSE ) + { + /* Peer has no more space at this moment. */ + ulReturn = 0; + } + else + { + /* Move it out of the Tx queue. */ + pxSegment = xTCPWindowGetHead( &( pxWindow->xTxQueue ) ); + + /* Don't let pxHeadSegment point to this segment any more, + so no more data will be added. */ + if( pxWindow->pxHeadSegment == pxSegment ) + { + pxWindow->pxHeadSegment = NULL; + } + + /* pxWindow->tx.highest registers the highest sequence + number in our transmission window. */ + pxWindow->tx.ulHighestSequenceNumber = pxSegment->ulSequenceNumber + ( ( uint32_t ) pxSegment->lDataLength ); + + /* ...and more detailed logging */ + if( ( xTCPWindowLoggingLevel >= 2 ) && ( ipconfigTCP_MAY_LOG_PORT( pxWindow->usOurPortNumber ) != pdFALSE ) ) + { + FreeRTOS_debug_printf( ( "ulTCPWindowTxGet[%u,%u]: XmitQueue %ld bytes for sequence number %lu (ws %lu)\n", + pxWindow->usPeerPortNumber, + pxWindow->usOurPortNumber, + pxSegment->lDataLength, + pxSegment->ulSequenceNumber - pxWindow->tx.ulFirstSequenceNumber, + ulWindowSize ) ); + FreeRTOS_flush_logging( ); + } + } + } + } + else + { + /* There is a priority segment. It doesn't need any checking for + space or timeouts. */ + if( xTCPWindowLoggingLevel != 0 ) + { + FreeRTOS_debug_printf( ( "ulTCPWindowTxGet[%u,%u]: PrioQueue %ld bytes for sequence number %lu (ws %lu)\n", + pxWindow->usPeerPortNumber, + pxWindow->usOurPortNumber, + pxSegment->lDataLength, + pxSegment->ulSequenceNumber - pxWindow->tx.ulFirstSequenceNumber, + ulWindowSize ) ); + FreeRTOS_flush_logging( ); + } + } + + /* See if it has already been determined to return 0. */ + if( ulReturn != 0UL ) + { + configASSERT( listLIST_ITEM_CONTAINER( &(pxSegment->xQueueItem ) ) == NULL ); + + /* Now that the segment will be transmitted, add it to the tail of + the waiting queue. */ + vListInsertFifo( &pxWindow->xWaitQueue, &pxSegment->xQueueItem ); + + /* And mark it as outstanding. */ + pxSegment->u.bits.bOutstanding = pdTRUE_UNSIGNED; + + /* Administer the transmit count, needed for fast + retransmissions. */ + ( pxSegment->u.bits.ucTransmitCount )++; + + /* If there have been several retransmissions (4), decrease the + size of the transmission window to at most 2 times MSS. */ + if( pxSegment->u.bits.ucTransmitCount == MAX_TRANSMIT_COUNT_USING_LARGE_WINDOW ) + { + if( pxWindow->xSize.ulTxWindowLength > ( 2U * pxWindow->usMSS ) ) + { + FreeRTOS_debug_printf( ( "ulTCPWindowTxGet[%u - %d]: Change Tx window: %lu -> %u\n", + pxWindow->usPeerPortNumber, pxWindow->usOurPortNumber, + pxWindow->xSize.ulTxWindowLength, 2 * pxWindow->usMSS ) ); + pxWindow->xSize.ulTxWindowLength = ( 2UL * pxWindow->usMSS ); + } + } + + /* Clear the transmit timer. */ + vTCPTimerSet( &( pxSegment->xTransmitTimer ) ); + + pxWindow->ulOurSequenceNumber = pxSegment->ulSequenceNumber; + + /* Inform the caller where to find the data within the queue. */ + *plPosition = pxSegment->lStreamPos; + + /* And return the length of the data segment */ + ulReturn = ( uint32_t ) pxSegment->lDataLength; + } + + return ulReturn; + } + +#endif /* ipconfigUSE_TCP_WIN == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + + static uint32_t prvTCPWindowTxCheckAck( TCPWindow_t *pxWindow, uint32_t ulFirst, uint32_t ulLast ) + { + uint32_t ulBytesConfirmed = 0u; + uint32_t ulSequenceNumber = ulFirst, ulDataLength; + const ListItem_t *pxIterator; + const MiniListItem_t *pxEnd = ( const MiniListItem_t* )listGET_END_MARKER( &pxWindow->xTxSegments ); + BaseType_t xDoUnlink; + TCPSegment_t *pxSegment; + /* An acknowledgement or a selective ACK (SACK) was received. See if some outstanding data + may be removed from the transmission queue(s). + All TX segments for which + ( ( ulSequenceNumber >= ulFirst ) && ( ulSequenceNumber < ulLast ) in a + contiguous block. Note that the segments are stored in xTxSegments in a + strict sequential order. */ + + /* SRTT[i] = (1-a) * SRTT[i-1] + a * RTT + + 0 < a < 1; usually a = 1/8 + + RTO = 2 * SRTT + + where: + RTT is Round Trip Time + SRTT is Smoothed RTT + RTO is Retransmit timeout + + A Smoothed RTT will increase quickly, but it is conservative when + becoming smaller. */ + + for( + pxIterator = ( const ListItem_t * ) listGET_NEXT( pxEnd ); + ( pxIterator != ( const ListItem_t * ) pxEnd ) && ( xSequenceLessThan( ulSequenceNumber, ulLast ) != 0 ); + ) + { + xDoUnlink = pdFALSE; + pxSegment = ( TCPSegment_t * ) listGET_LIST_ITEM_OWNER( pxIterator ); + + /* Move to the next item because the current item might get + removed. */ + pxIterator = ( const ListItem_t * ) listGET_NEXT( pxIterator ); + + /* Continue if this segment does not fall within the ACK'd range. */ + if( xSequenceGreaterThan( ulSequenceNumber, pxSegment->ulSequenceNumber ) != pdFALSE ) + { + continue; + } + + /* Is it ready? */ + if( ulSequenceNumber != pxSegment->ulSequenceNumber ) + { + break; + } + + ulDataLength = ( uint32_t ) pxSegment->lDataLength; + + if( pxSegment->u.bits.bAcked == pdFALSE_UNSIGNED ) + { + if( xSequenceGreaterThan( pxSegment->ulSequenceNumber + ( uint32_t )ulDataLength, ulLast ) != pdFALSE ) + { + /* What happens? Only part of this segment was accepted, + probably due to WND limits + + AAAAAAA BBBBBBB << acked + aaaaaaa aaaa << sent */ + #if( ipconfigHAS_DEBUG_PRINTF != 0 ) + { + uint32_t ulFirstSeq = pxSegment->ulSequenceNumber - pxWindow->tx.ulFirstSequenceNumber; + FreeRTOS_debug_printf( ( "prvTCPWindowTxCheckAck[%u.%u]: %lu - %lu Partial sequence number %lu - %lu\n", + pxWindow->usPeerPortNumber, + pxWindow->usOurPortNumber, + ulFirstSeq - pxWindow->tx.ulFirstSequenceNumber, + ulLast - pxWindow->tx.ulFirstSequenceNumber, + ulFirstSeq, ulFirstSeq + ulDataLength ) ); + } + #endif /* ipconfigHAS_DEBUG_PRINTF */ + break; + } + + /* This segment is fully ACK'd, set the flag. */ + pxSegment->u.bits.bAcked = pdTRUE_UNSIGNED; + + /* Calculate the RTT only if the segment was sent-out for the + first time and if this is the last ACK'd segment in a range. */ + if( ( pxSegment->u.bits.ucTransmitCount == 1 ) && ( ( pxSegment->ulSequenceNumber + ulDataLength ) == ulLast ) ) + { + int32_t mS = ( int32_t ) ulTimerGetAge( &( pxSegment->xTransmitTimer ) ); + + if( pxWindow->lSRTT >= mS ) + { + /* RTT becomes smaller: adapt slowly. */ + pxWindow->lSRTT = ( ( winSRTT_DECREMENT_NEW * mS ) + ( winSRTT_DECREMENT_CURRENT * pxWindow->lSRTT ) ) / ( winSRTT_DECREMENT_NEW + winSRTT_DECREMENT_CURRENT ); + } + else + { + /* RTT becomes larger: adapt quicker */ + pxWindow->lSRTT = ( ( winSRTT_INCREMENT_NEW * mS ) + ( winSRTT_INCREMENT_CURRENT * pxWindow->lSRTT ) ) / ( winSRTT_INCREMENT_NEW + winSRTT_INCREMENT_CURRENT ); + } + + /* Cap to the minimum of 50ms. */ + if( pxWindow->lSRTT < winSRTT_CAP_mS ) + { + pxWindow->lSRTT = winSRTT_CAP_mS; + } + } + + /* Unlink it from the 3 queues, but do not destroy it (yet). */ + xDoUnlink = pdTRUE; + } + + /* pxSegment->u.bits.bAcked is now true. Is it located at the left + side of the transmission queue? If so, it may be freed. */ + if( ulSequenceNumber == pxWindow->tx.ulCurrentSequenceNumber ) + { + if( ( xTCPWindowLoggingLevel >= 2 ) && ( ipconfigTCP_MAY_LOG_PORT( pxWindow->usOurPortNumber ) != pdFALSE ) ) + { + FreeRTOS_debug_printf( ( "prvTCPWindowTxCheckAck: %lu - %lu Ready sequence number %lu\n", + ulFirst - pxWindow->tx.ulFirstSequenceNumber, + ulLast - pxWindow->tx.ulFirstSequenceNumber, + pxSegment->ulSequenceNumber - pxWindow->tx.ulFirstSequenceNumber ) ); + } + + /* Increase the left-hand value of the transmission window. */ + pxWindow->tx.ulCurrentSequenceNumber += ulDataLength; + + /* This function will return the number of bytes that the tail + of txStream may be advanced. */ + ulBytesConfirmed += ulDataLength; + + /* All segments below tx.ulCurrentSequenceNumber may be freed. */ + vTCPWindowFree( pxSegment ); + + /* No need to unlink it any more. */ + xDoUnlink = pdFALSE; + } + + if( ( xDoUnlink != pdFALSE ) && ( listLIST_ITEM_CONTAINER( &( pxSegment->xQueueItem ) ) != NULL ) ) + { + /* Remove item from its queues. */ + uxListRemove( &pxSegment->xQueueItem ); + } + + ulSequenceNumber += ulDataLength; + } + + return ulBytesConfirmed; + } +#endif /* ipconfigUSE_TCP_WIN == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + + static uint32_t prvTCPWindowFastRetransmit( TCPWindow_t *pxWindow, uint32_t ulFirst ) + { + const ListItem_t *pxIterator; + const MiniListItem_t* pxEnd; + TCPSegment_t *pxSegment; + uint32_t ulCount = 0UL; + + /* A higher Tx block has been acknowledged. Now iterate through the + xWaitQueue to find a possible condition for a FAST retransmission. */ + + pxEnd = ( const MiniListItem_t* ) listGET_END_MARKER( &( pxWindow->xWaitQueue ) ); + + for( pxIterator = ( const ListItem_t * ) listGET_NEXT( pxEnd ); + pxIterator != ( const ListItem_t * ) pxEnd; ) + { + /* Get the owner, which is a TCP segment. */ + pxSegment = ( TCPSegment_t * ) listGET_LIST_ITEM_OWNER( pxIterator ); + + /* Hop to the next item before the current gets unlinked. */ + pxIterator = ( const ListItem_t * ) listGET_NEXT( pxIterator ); + + /* Fast retransmission: + When 3 packets with a higher sequence number have been acknowledged + by the peer, it is very unlikely a current packet will ever arrive. + It will be retransmitted far before the RTO. */ + if( ( pxSegment->u.bits.bAcked == pdFALSE_UNSIGNED ) && + ( xSequenceLessThan( pxSegment->ulSequenceNumber, ulFirst ) != pdFALSE ) && + ( ++( pxSegment->u.bits.ucDupAckCount ) == DUPLICATE_ACKS_BEFORE_FAST_RETRANSMIT ) ) + { + pxSegment->u.bits.ucTransmitCount = pdFALSE_UNSIGNED; + + /* Not clearing 'ucDupAckCount' yet as more SACK's might come in + which might lead to a second fast rexmit. */ + if( ( xTCPWindowLoggingLevel >= 0 ) && ( ipconfigTCP_MAY_LOG_PORT( pxWindow->usOurPortNumber ) != pdFALSE ) ) + { + FreeRTOS_debug_printf( ( "prvTCPWindowFastRetransmit: Requeue sequence number %lu < %lu\n", + pxSegment->ulSequenceNumber - pxWindow->tx.ulFirstSequenceNumber, + ulFirst - pxWindow->tx.ulFirstSequenceNumber ) ); + FreeRTOS_flush_logging( ); + } + + /* Remove it from xWaitQueue. */ + uxListRemove( &pxSegment->xQueueItem ); + + /* Add this segment to the priority queue so it gets + retransmitted immediately. */ + vListInsertFifo( &( pxWindow->xPriorityQueue ), &( pxSegment->xQueueItem ) ); + ulCount++; + } + } + + return ulCount; + } +#endif /* ipconfigUSE_TCP_WIN == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + + uint32_t ulTCPWindowTxAck( TCPWindow_t *pxWindow, uint32_t ulSequenceNumber ) + { + uint32_t ulFirstSequence, ulReturn; + + /* Receive a normal ACK. */ + + ulFirstSequence = pxWindow->tx.ulCurrentSequenceNumber; + + if( xSequenceLessThanOrEqual( ulSequenceNumber, ulFirstSequence ) != pdFALSE ) + { + ulReturn = 0UL; + } + else + { + ulReturn = prvTCPWindowTxCheckAck( pxWindow, ulFirstSequence, ulSequenceNumber ); + } + + return ulReturn; + } + +#endif /* ipconfigUSE_TCP_WIN == 1 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 1 ) + + uint32_t ulTCPWindowTxSack( TCPWindow_t *pxWindow, uint32_t ulFirst, uint32_t ulLast ) + { + uint32_t ulAckCount = 0UL; + uint32_t ulCurrentSequenceNumber = pxWindow->tx.ulCurrentSequenceNumber; + + /* Receive a SACK option. */ + ulAckCount = prvTCPWindowTxCheckAck( pxWindow, ulFirst, ulLast ); + prvTCPWindowFastRetransmit( pxWindow, ulFirst ); + + if( ( xTCPWindowLoggingLevel >= 1 ) && ( xSequenceGreaterThan( ulFirst, ulCurrentSequenceNumber ) != pdFALSE ) ) + { + FreeRTOS_debug_printf( ( "ulTCPWindowTxSack[%u,%u]: from %lu to %lu (ack = %lu)\n", + pxWindow->usPeerPortNumber, + pxWindow->usOurPortNumber, + ulFirst - pxWindow->tx.ulFirstSequenceNumber, + ulLast - pxWindow->tx.ulFirstSequenceNumber, + pxWindow->tx.ulCurrentSequenceNumber - pxWindow->tx.ulFirstSequenceNumber ) ); + FreeRTOS_flush_logging( ); + } + + return ulAckCount; + } + +#endif /* ipconfigUSE_TCP_WIN == 1 */ +/*-----------------------------------------------------------*/ + +/* +##### # ##### #### ###### +# # # # # # # # # # # + # # # # # # + # ### ##### # # # # # # + # # # # # # # # ##### + # # # # # # #### # # # + # # # # # # # # # # + # # # # #### # # # # + #### ##### # # # #### #### #### + # + ### +*/ +#if( ipconfigUSE_TCP_WIN == 0 ) + + int32_t lTCPWindowRxCheck( TCPWindow_t *pxWindow, uint32_t ulSequenceNumber, uint32_t ulLength, uint32_t ulSpace ) + { + int32_t iReturn; + + /* Data was received at 'ulSequenceNumber'. See if it was expected + and if there is enough space to store the new data. */ + if( ( pxWindow->rx.ulCurrentSequenceNumber != ulSequenceNumber ) || ( ulSpace < ulLength ) ) + { + iReturn = -1; + } + else + { + pxWindow->rx.ulCurrentSequenceNumber += ( uint32_t ) ulLength; + iReturn = 0; + } + + return iReturn; + } + +#endif /* ipconfigUSE_TCP_WIN == 0 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 0 ) + + int32_t lTCPWindowTxAdd( TCPWindow_t *pxWindow, uint32_t ulLength, int32_t lPosition, int32_t lMax ) + { + TCPSegment_t *pxSegment = &( pxWindow->xTxSegment ); + int32_t lResult; + + /* Data is being scheduled for transmission. */ + + /* lMax would indicate the size of the txStream. */ + ( void ) lMax; + /* This is tiny TCP: there is only 1 segment for outgoing data. + As long as 'lDataLength' is unequal to zero, the segment is still occupied. */ + if( pxSegment->lDataLength > 0 ) + { + lResult = 0L; + } + else + { + if( ulLength > ( uint32_t ) pxSegment->lMaxLength ) + { + if( ( xTCPWindowLoggingLevel != 0 ) && ( ipconfigTCP_MAY_LOG_PORT( pxWindow->usOurPortNumber ) != pdFALSE ) ) + { + FreeRTOS_debug_printf( ( "lTCPWindowTxAdd: can only store %ld / %ld bytes\n", ulLength, pxSegment->lMaxLength ) ); + } + + ulLength = ( uint32_t ) pxSegment->lMaxLength; + } + + if( ( xTCPWindowLoggingLevel != 0 ) && ( ipconfigTCP_MAY_LOG_PORT( pxWindow->usOurPortNumber ) != pdFALSE ) ) + { + FreeRTOS_debug_printf( ( "lTCPWindowTxAdd: SeqNr %ld (%ld) Len %ld\n", + pxWindow->ulNextTxSequenceNumber - pxWindow->tx.ulFirstSequenceNumber, + pxWindow->tx.ulCurrentSequenceNumber - pxWindow->tx.ulFirstSequenceNumber, + ulLength ) ); + } + + /* The sequence number of the first byte in this packet. */ + pxSegment->ulSequenceNumber = pxWindow->ulNextTxSequenceNumber; + pxSegment->lDataLength = ( int32_t ) ulLength; + pxSegment->lStreamPos = lPosition; + pxSegment->u.ulFlags = 0UL; + vTCPTimerSet( &( pxSegment->xTransmitTimer ) ); + + /* Increase the sequence number of the next data to be stored for + transmission. */ + pxWindow->ulNextTxSequenceNumber += ulLength; + lResult = ( int32_t )ulLength; + } + + return lResult; + } + +#endif /* ipconfigUSE_TCP_WIN == 0 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 0 ) + + uint32_t ulTCPWindowTxGet( TCPWindow_t *pxWindow, uint32_t ulWindowSize, int32_t *plPosition ) + { + TCPSegment_t *pxSegment = &( pxWindow->xTxSegment ); + uint32_t ulLength = ( uint32_t ) pxSegment->lDataLength; + uint32_t ulMaxTime; + + if( ulLength != 0UL ) + { + /* _HT_ Still under investigation */ + ( void ) ulWindowSize; + + if( pxSegment->u.bits.bOutstanding != pdFALSE_UNSIGNED ) + { + /* As 'ucTransmitCount' has a minimum of 1, take 2 * RTT */ + ulMaxTime = ( ( uint32_t ) 1u << pxSegment->u.bits.ucTransmitCount ) * ( ( uint32_t ) pxWindow->lSRTT ); + + if( ulTimerGetAge( &( pxSegment->xTransmitTimer ) ) < ulMaxTime ) + { + ulLength = 0ul; + } + } + + if( ulLength != 0ul ) + { + pxSegment->u.bits.bOutstanding = pdTRUE_UNSIGNED; + pxSegment->u.bits.ucTransmitCount++; + vTCPTimerSet (&pxSegment->xTransmitTimer); + pxWindow->ulOurSequenceNumber = pxSegment->ulSequenceNumber; + *plPosition = pxSegment->lStreamPos; + } + } + + return ulLength; + } + +#endif /* ipconfigUSE_TCP_WIN == 0 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 0 ) + + BaseType_t xTCPWindowTxDone( TCPWindow_t *pxWindow ) + { + BaseType_t xReturn; + + /* Has the outstanding data been sent because user wants to shutdown? */ + if( pxWindow->xTxSegment.lDataLength == 0 ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; + } + +#endif /* ipconfigUSE_TCP_WIN == 0 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 0 ) + + static BaseType_t prvTCPWindowTxHasSpace( TCPWindow_t *pxWindow, uint32_t ulWindowSize ); + static BaseType_t prvTCPWindowTxHasSpace( TCPWindow_t *pxWindow, uint32_t ulWindowSize ) + { + BaseType_t xReturn; + + if( ulWindowSize >= pxWindow->usMSSInit ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; + } + +#endif /* ipconfigUSE_TCP_WIN == 0 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 0 ) + + BaseType_t xTCPWindowTxHasData( TCPWindow_t *pxWindow, uint32_t ulWindowSize, TickType_t *pulDelay ) + { + TCPSegment_t *pxSegment = &( pxWindow->xTxSegment ); + BaseType_t xReturn; + TickType_t ulAge, ulMaxAge; + + /* Check data to be sent. */ + *pulDelay = ( TickType_t ) 0; + if( pxSegment->lDataLength == 0 ) + { + /* Got nothing to send right now. */ + xReturn = pdFALSE; + } + else + { + if( pxSegment->u.bits.bOutstanding != pdFALSE_UNSIGNED ) + { + ulAge = ulTimerGetAge ( &pxSegment->xTransmitTimer ); + ulMaxAge = ( ( TickType_t ) 1u << pxSegment->u.bits.ucTransmitCount ) * ( ( uint32_t ) pxWindow->lSRTT ); + + if( ulMaxAge > ulAge ) + { + *pulDelay = ulMaxAge - ulAge; + } + + xReturn = pdTRUE; + } + else if( prvTCPWindowTxHasSpace( pxWindow, ulWindowSize ) == pdFALSE ) + { + /* Too many outstanding messages. */ + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + } + + return xReturn; + } + +#endif /* ipconfigUSE_TCP_WIN == 0 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 0 ) + + uint32_t ulTCPWindowTxAck( TCPWindow_t *pxWindow, uint32_t ulSequenceNumber ) + { + TCPSegment_t *pxSegment = &( pxWindow->xTxSegment ); + uint32_t ulDataLength = ( uint32_t ) pxSegment->lDataLength; + + /* Receive a normal ACK */ + + if( ulDataLength != 0ul ) + { + if( ulSequenceNumber < ( pxWindow->tx.ulCurrentSequenceNumber + ulDataLength ) ) + { + if( ipconfigTCP_MAY_LOG_PORT( pxWindow->usOurPortNumber ) != pdFALSE ) + { + FreeRTOS_debug_printf( ( "win_tx_ack: acked %ld expc %ld len %ld\n", + ulSequenceNumber - pxWindow->tx.ulFirstSequenceNumber, + pxWindow->tx.ulCurrentSequenceNumber - pxWindow->tx.ulFirstSequenceNumber, + ulDataLength ) ); + } + + /* Nothing to send right now. */ + ulDataLength = 0ul; + } + else + { + pxWindow->tx.ulCurrentSequenceNumber += ulDataLength; + + if( ( xTCPWindowLoggingLevel != 0 ) && ( ipconfigTCP_MAY_LOG_PORT( pxWindow->usOurPortNumber ) != pdFALSE ) ) + { + FreeRTOS_debug_printf( ( "win_tx_ack: acked seqnr %ld len %ld\n", + ulSequenceNumber - pxWindow->tx.ulFirstSequenceNumber, + ulDataLength ) ); + } + + pxSegment->lDataLength = 0; + } + } + + return ulDataLength; + } + +#endif /* ipconfigUSE_TCP_WIN == 0 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 0 ) + + BaseType_t xTCPWindowRxEmpty( TCPWindow_t *pxWindow ) + { + /* Return true if 'ulCurrentSequenceNumber >= ulHighestSequenceNumber' + 'ulCurrentSequenceNumber' is the highest sequence number stored, + 'ulHighestSequenceNumber' is the highest sequence number seen. */ + return xSequenceGreaterThanOrEqual( pxWindow->rx.ulCurrentSequenceNumber, pxWindow->rx.ulHighestSequenceNumber ); + } + +#endif /* ipconfigUSE_TCP_WIN == 0 */ +/*-----------------------------------------------------------*/ + +#if( ipconfigUSE_TCP_WIN == 0 ) + + /* Destroy a window (always returns NULL) */ + void vTCPWindowDestroy( TCPWindow_t *pxWindow ) + { + /* As in tiny TCP there are no shared segments descriptors, there is + nothing to release. */ + ( void ) pxWindow; + } + +#endif /* ipconfigUSE_TCP_WIN == 0 */ +/*-----------------------------------------------------------*/ + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_UDP_IP.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_UDP_IP.c new file mode 100644 index 0000000..87d60fc --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_UDP_IP.c @@ -0,0 +1,378 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +/* Standard includes. */ +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_IP_Private.h" +#include "FreeRTOS_UDP_IP.h" +#include "FreeRTOS_ARP.h" +#include "FreeRTOS_DHCP.h" +#include "NetworkInterface.h" +#include "NetworkBufferManagement.h" + +#if( ipconfigUSE_DNS == 1 ) + #include "FreeRTOS_DNS.h" +#endif + +/* The expected IP version and header length coded into the IP header itself. */ +#define ipIP_VERSION_AND_HEADER_LENGTH_BYTE ( ( uint8_t ) 0x45 ) + +/* Part of the Ethernet and IP headers are always constant when sending an IPv4 +UDP packet. This array defines the constant parts, allowing this part of the +packet to be filled in using a simple memcpy() instead of individual writes. */ +UDPPacketHeader_t xDefaultPartUDPPacketHeader = +{ + /* .ucBytes : */ + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* Ethernet source MAC address. */ + 0x08, 0x00, /* Ethernet frame type. */ + ipIP_VERSION_AND_HEADER_LENGTH_BYTE, /* ucVersionHeaderLength. */ + 0x00, /* ucDifferentiatedServicesCode. */ + 0x00, 0x00, /* usLength. */ + 0x00, 0x00, /* usIdentification. */ + 0x00, 0x00, /* usFragmentOffset. */ + ipconfigUDP_TIME_TO_LIVE, /* ucTimeToLive */ + ipPROTOCOL_UDP, /* ucProtocol. */ + 0x00, 0x00, /* usHeaderChecksum. */ + 0x00, 0x00, 0x00, 0x00 /* Source IP address. */ + } +}; +/*-----------------------------------------------------------*/ + +void vProcessGeneratedUDPPacket( NetworkBufferDescriptor_t * const pxNetworkBuffer ) +{ +UDPPacket_t *pxUDPPacket; +IPHeader_t *pxIPHeader; +eARPLookupResult_t eReturned; +uint32_t ulIPAddress = pxNetworkBuffer->ulIPAddress; + + /* Map the UDP packet onto the start of the frame. */ + pxUDPPacket = ( UDPPacket_t * ) pxNetworkBuffer->pucEthernetBuffer; + + /* Determine the ARP cache status for the requested IP address. */ + eReturned = eARPGetCacheEntry( &( ulIPAddress ), &( pxUDPPacket->xEthernetHeader.xDestinationAddress ) ); + + if( eReturned != eCantSendPacket ) + { + if( eReturned == eARPCacheHit ) + { + #if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM == 0 ) + uint8_t ucSocketOptions; + #endif + iptraceSENDING_UDP_PACKET( pxNetworkBuffer->ulIPAddress ); + + /* Create short cuts to the data within the packet. */ + pxIPHeader = &( pxUDPPacket->xIPHeader ); + + #if ( ipconfigSUPPORT_OUTGOING_PINGS == 1 ) + /* Is it possible that the packet is not actually a UDP packet + after all, but an ICMP packet. */ + if( pxNetworkBuffer->usPort != ipPACKET_CONTAINS_ICMP_DATA ) + #endif /* ipconfigSUPPORT_OUTGOING_PINGS */ + { + UDPHeader_t *pxUDPHeader; + + pxUDPHeader = &( pxUDPPacket->xUDPHeader ); + + pxUDPHeader->usDestinationPort = pxNetworkBuffer->usPort; + pxUDPHeader->usSourcePort = pxNetworkBuffer->usBoundPort; + pxUDPHeader->usLength = ( uint16_t ) ( pxNetworkBuffer->xDataLength + sizeof( UDPHeader_t ) ); + pxUDPHeader->usLength = FreeRTOS_htons( pxUDPHeader->usLength ); + pxUDPHeader->usChecksum = 0u; + } + + /* memcpy() the constant parts of the header information into + the correct location within the packet. This fills in: + xEthernetHeader.xSourceAddress + xEthernetHeader.usFrameType + xIPHeader.ucVersionHeaderLength + xIPHeader.ucDifferentiatedServicesCode + xIPHeader.usLength + xIPHeader.usIdentification + xIPHeader.usFragmentOffset + xIPHeader.ucTimeToLive + xIPHeader.ucProtocol + and + xIPHeader.usHeaderChecksum + */ + /* Save options now, as they will be overwritten by memcpy */ + #if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM == 0 ) + ucSocketOptions = pxNetworkBuffer->pucEthernetBuffer[ ipSOCKET_OPTIONS_OFFSET ]; + #endif + /* + * Offset the memcpy by the size of a MAC address to start at the packet's + * Ethernet header 'source' MAC address; the preceding 'destination' should not be altered. + */ + char *pxUdpSrcAddrOffset = ( char *) pxUDPPacket + sizeof( MACAddress_t ); + memcpy( pxUdpSrcAddrOffset, xDefaultPartUDPPacketHeader.ucBytes, sizeof( xDefaultPartUDPPacketHeader ) ); + + #if ipconfigSUPPORT_OUTGOING_PINGS == 1 + if( pxNetworkBuffer->usPort == ipPACKET_CONTAINS_ICMP_DATA ) + { + pxIPHeader->ucProtocol = ipPROTOCOL_ICMP; + pxIPHeader->usLength = ( uint16_t ) ( pxNetworkBuffer->xDataLength + sizeof( IPHeader_t ) ); + } + else + #endif /* ipconfigSUPPORT_OUTGOING_PINGS */ + { + pxIPHeader->usLength = ( uint16_t ) ( pxNetworkBuffer->xDataLength + sizeof( IPHeader_t ) + sizeof( UDPHeader_t ) ); + } + + /* The total transmit size adds on the Ethernet header. */ + pxNetworkBuffer->xDataLength = pxIPHeader->usLength + sizeof( EthernetHeader_t ); + pxIPHeader->usLength = FreeRTOS_htons( pxIPHeader->usLength ); + /* HT:endian: changed back to network endian */ + pxIPHeader->ulDestinationIPAddress = pxNetworkBuffer->ulIPAddress; + + #if( ipconfigUSE_LLMNR == 1 ) + { + /* LLMNR messages are typically used on a LAN and they're + * not supposed to cross routers */ + if( pxNetworkBuffer->ulIPAddress == ipLLMNR_IP_ADDR ) + { + pxIPHeader->ucTimeToLive = 0x01; + } + } + #endif + + #if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM == 0 ) + { + pxIPHeader->usHeaderChecksum = 0u; + pxIPHeader->usHeaderChecksum = usGenerateChecksum( 0UL, ( uint8_t * ) &( pxIPHeader->ucVersionHeaderLength ), ipSIZE_OF_IPv4_HEADER ); + pxIPHeader->usHeaderChecksum = ~FreeRTOS_htons( pxIPHeader->usHeaderChecksum ); + + if( ( ucSocketOptions & ( uint8_t ) FREERTOS_SO_UDPCKSUM_OUT ) != 0u ) + { + usGenerateProtocolChecksum( (uint8_t*)pxUDPPacket, pxNetworkBuffer->xDataLength, pdTRUE ); + } + else + { + pxUDPPacket->xUDPHeader.usChecksum = 0u; + } + } + #endif + } + else if( eReturned == eARPCacheMiss ) + { + /* Add an entry to the ARP table with a null hardware address. + This allows the ARP timer to know that an ARP reply is + outstanding, and perform retransmissions if necessary. */ + vARPRefreshCacheEntry( NULL, ulIPAddress ); + + /* Generate an ARP for the required IP address. */ + iptracePACKET_DROPPED_TO_GENERATE_ARP( pxNetworkBuffer->ulIPAddress ); + pxNetworkBuffer->ulIPAddress = ulIPAddress; + vARPGenerateRequestPacket( pxNetworkBuffer ); + } + else + { + /* The lookup indicated that an ARP request has already been + sent out for the queried IP address. */ + eReturned = eCantSendPacket; + } + } + + if( eReturned != eCantSendPacket ) + { + /* The network driver is responsible for freeing the network buffer + after the packet has been sent. */ + + #if defined( ipconfigETHERNET_MINIMUM_PACKET_BYTES ) + { + if( pxNetworkBuffer->xDataLength < ( size_t ) ipconfigETHERNET_MINIMUM_PACKET_BYTES ) + { + BaseType_t xIndex; + + for( xIndex = ( BaseType_t ) pxNetworkBuffer->xDataLength; xIndex < ( BaseType_t ) ipconfigETHERNET_MINIMUM_PACKET_BYTES; xIndex++ ) + { + pxNetworkBuffer->pucEthernetBuffer[ xIndex ] = 0u; + } + pxNetworkBuffer->xDataLength = ( size_t ) ipconfigETHERNET_MINIMUM_PACKET_BYTES; + } + } + #endif + + xNetworkInterfaceOutput( pxNetworkBuffer, pdTRUE ); + } + else + { + /* The packet can't be sent (DHCP not completed?). Just drop the + packet. */ + vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ); + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xProcessReceivedUDPPacket( NetworkBufferDescriptor_t *pxNetworkBuffer, uint16_t usPort ) +{ +BaseType_t xReturn = pdPASS; +FreeRTOS_Socket_t *pxSocket; + +UDPPacket_t *pxUDPPacket = (UDPPacket_t *) pxNetworkBuffer->pucEthernetBuffer; + + /* Caller must check for minimum packet size. */ + pxSocket = pxUDPSocketLookup( usPort ); + + if( pxSocket ) + { + + /* When refreshing the ARP cache with received UDP packets we must be + careful; hundreds of broadcast messages may pass and if we're not + handling them, no use to fill the ARP cache with those IP addresses. */ + vARPRefreshCacheEntry( &( pxUDPPacket->xEthernetHeader.xSourceAddress ), pxUDPPacket->xIPHeader.ulSourceIPAddress ); + + #if( ipconfigUSE_CALLBACKS == 1 ) + { + /* Did the owner of this socket register a reception handler ? */ + if( ipconfigIS_VALID_PROG_ADDRESS( pxSocket->u.xUDP.pxHandleReceive ) ) + { + struct freertos_sockaddr xSourceAddress, destinationAddress; + void *pcData = ( void * ) &( pxNetworkBuffer->pucEthernetBuffer[ ipUDP_PAYLOAD_OFFSET_IPv4 ] ); + FOnUDPReceive_t xHandler = ( FOnUDPReceive_t ) pxSocket->u.xUDP.pxHandleReceive; + xSourceAddress.sin_port = pxNetworkBuffer->usPort; + xSourceAddress.sin_addr = pxNetworkBuffer->ulIPAddress; + destinationAddress.sin_port = usPort; + destinationAddress.sin_addr = pxUDPPacket->xIPHeader.ulDestinationIPAddress; + + if( xHandler( ( Socket_t * ) pxSocket, ( void* ) pcData, ( size_t ) pxNetworkBuffer->xDataLength, + &xSourceAddress, &destinationAddress ) ) + { + xReturn = pdFAIL; /* FAIL means that we did not consume or release the buffer */ + } + } + } + #endif /* ipconfigUSE_CALLBACKS */ + + #if( ipconfigUDP_MAX_RX_PACKETS > 0 ) + { + if( xReturn == pdPASS ) + { + if ( listCURRENT_LIST_LENGTH( &( pxSocket->u.xUDP.xWaitingPacketsList ) ) >= pxSocket->u.xUDP.uxMaxPackets ) + { + FreeRTOS_debug_printf( ( "xProcessReceivedUDPPacket: buffer full %ld >= %ld port %u\n", + listCURRENT_LIST_LENGTH( &( pxSocket->u.xUDP.xWaitingPacketsList ) ), + pxSocket->u.xUDP.uxMaxPackets, pxSocket->usLocalPort ) ); + xReturn = pdFAIL; /* we did not consume or release the buffer */ + } + } + } + #endif + + if( xReturn == pdPASS ) + { + vTaskSuspendAll(); + { + if( xReturn == pdPASS ) + { + taskENTER_CRITICAL(); + { + /* Add the network packet to the list of packets to be + processed by the socket. */ + vListInsertEnd( &( pxSocket->u.xUDP.xWaitingPacketsList ), &( pxNetworkBuffer->xBufferListItem ) ); + } + taskEXIT_CRITICAL(); + } + } + xTaskResumeAll(); + + /* Set the socket's receive event */ + if( pxSocket->xEventGroup != NULL ) + { + xEventGroupSetBits( pxSocket->xEventGroup, eSOCKET_RECEIVE ); + } + + #if( ipconfigSUPPORT_SELECT_FUNCTION == 1 ) + { + if( ( pxSocket->pxSocketSet != NULL ) && ( ( pxSocket->xSelectBits & eSELECT_READ ) != 0 ) ) + { + xEventGroupSetBits( pxSocket->pxSocketSet->xSelectGroup, eSELECT_READ ); + } + } + #endif + + #if( ipconfigSOCKET_HAS_USER_SEMAPHORE == 1 ) + { + if( pxSocket->pxUserSemaphore != NULL ) + { + xSemaphoreGive( pxSocket->pxUserSemaphore ); + } + } + #endif + + #if( ipconfigUSE_DHCP == 1 ) + { + if( xIsDHCPSocket( pxSocket ) ) + { + xSendEventToIPTask( eDHCPEvent ); + } + } + #endif + } + } + else + { + /* There is no socket listening to the target port, but still it might + be for this node. */ + + #if( ipconfigUSE_LLMNR == 1 ) + /* a LLMNR request, check for the destination port. */ + if( ( usPort == FreeRTOS_ntohs( ipLLMNR_PORT ) ) || + ( pxUDPPacket->xUDPHeader.usSourcePort == FreeRTOS_ntohs( ipLLMNR_PORT ) ) ) + { + vARPRefreshCacheEntry( &( pxUDPPacket->xEthernetHeader.xSourceAddress ), pxUDPPacket->xIPHeader.ulSourceIPAddress ); + xReturn = ( BaseType_t )ulDNSHandlePacket( pxNetworkBuffer ); + } + else + #endif /* ipconfigUSE_LLMNR */ + + #if( ipconfigUSE_NBNS == 1 ) + /* a NetBIOS request, check for the destination port */ + if( ( usPort == FreeRTOS_ntohs( ipNBNS_PORT ) ) || + ( pxUDPPacket->xUDPHeader.usSourcePort == FreeRTOS_ntohs( ipNBNS_PORT ) ) ) + { + vARPRefreshCacheEntry( &( pxUDPPacket->xEthernetHeader.xSourceAddress ), pxUDPPacket->xIPHeader.ulSourceIPAddress ); + xReturn = ( BaseType_t )ulNBNSHandlePacket( pxNetworkBuffer ); + } + else + #endif /* ipconfigUSE_NBNS */ + { + xReturn = pdFAIL; + } + } + + return xReturn; +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/History.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/History.txt new file mode 100644 index 0000000..07ad698 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/History.txt @@ -0,0 +1,191 @@ +Changes in V2.0.11 + + + Updates some drivers in the portable layer. + +Changes between 160919 and 180821 releases: + + + Multiple security improvements and fixes in packet parsing routines, DNS + caching, and TCP sequence number and ID generation. + + Disable NBNS and LLMNR by default. + + Add TCP hang protection by default. + + We thank Ori Karliner of Zimperium zLabs Team for reporting these issues. + + + Update FreeRTOS_gethostbyname() to allow an IP address to be passed in - + in which case it is just returned as a uint32_t. + + Introduce ipconfigSOCKET_HAS_USER_WAKE_CALLBACK to FreeRTOS_Sockets.c to + allow a user supposed callback function to be executed when socket events + occur in the same way that the socket semaphore is currently used. + + Update xNetworkBuffersInitialise() to ensure the semaphore created by the + function is not accessed until after the NULL check. + + Improve print messages output by the Win32 port layer version of + prvPrintAvailableNetworkInterfaces(). + +Changes between 160908 and 160919 releases: + + + Add a NULL check before attempting to close the DHCP socket. [Prior to + 160823 the IP task closed the DHCP socket by calling a public API function + - which checked for the socket being NULL. This was changed to call a + local private function, which did not have a NULL check, in place of the + public API function.] + + Various [internal only] naming changes to better comply with the FreeRTOS + naming conventions. + + Improvements to the Zynq network driver. DMA transmission buffers now use + a counting semaphore. When all TX-buffers are in-use, the IP-task will + block momentarily until a TX-buffer becomes available. + + Experimental implementation of the TCP window scaling protocol. The + scaling option will always be offered, at least with a factor 1. If the + TCP sliding window size becomes more than 64KB, the factor will increase + automatically. + + ipconfigETHERNET_MINIMUM_PACKET_BYTES is now applied for every protocol: + TCP, UDP, and ARP. + + Updated the Zynq project to use BufferAllocation_1.c rather than + BufferAllocation_2.c - which is a requirement with its current + configuration (due to the alignment requirements on the combined cache and + DMA configuration). + +Changes between 160823 and 160908 releases: + + + Use ipconfigZERO_COPY_TX_DRIVER as the xReleaseAfterSend() parameter where + prvTCPReturnPacket() is called in prvSendData() to prevent unnecessary + copying of data. + + Remove the use of the uxGetRxEventCount variable, which was used to give + priority to incoming messages, but could result in the IP task starving + application tasks of processing time. + +Changes between 160112 and 160823 releases + + NOTE: The 160908 release is a maintenance release for the 160112 single + interface labs release - not a release of the current development branch. + + + Various minor stability enhancements, including the ability to work with + configTICK_RATE_HZ set to less than 1KHz, closing DHCP sockets directly + rather than via FreeRTOS_closesocket(), and better handling of unknown + TCP packets before an IP address has been assigned. + + ipBUFFER_PADDING is now configurable through the ipconfigBUFFER_PADDING + constant to improve network buffer alignment handling capabilities (expert + users/driver writers only). + + Multiple improvements to the FTP server, including to how read only and + zero length files are handled. + + ipconfigFTP_HAS_USER_PROPERTIES_HOOK (to allow each user to have a + different root directory and access rights) and + ipconfigHTTP_HAS_HANDLE_REQUEST_HOOK (to handle AJAX style data) + introduced, although these are not yet fully tested and the constant names + are likely to change. + + Introduce ipconfigHAS_TX_CRC_OFFLOADING. + + ipconfigUSE_DHCP_HOOK is now called ipconfigUSE_DHCP_HOOK, and the name + of the callback function has also changed. See the web documentation for + details. + + ipconfigTCP_RX_BUF_LEN is now ipconfigTCP_RX_BUFFER_LENGTH, and + ipconfigTCP_TX_BUF_LEN is now ipconfigTCP_TX_BUFFER_LENGTH, which is + actually how they have always been documented. + + Added example TFTP server capable of receiving (not sending) files. + Intended for bootloader type functionality. + + Various variable name changes for consistency (mainly ensuring UDP, TCP, + DNS, etc. always use the same case letters, and type prefixes are correct). + + Various minor edits to improve types used by internal variables. + + Simplified mapping of standard library functions to their Visual Studio + equivalents. + + Improve robustness of network drivers. + + Introduce pxResizeNetworkBufferWithDescriptor(). + + Removed obsolete FreeRTOSIPConfig.h constants from + FreeRTOSIPConfigDefaults.h. + + Added additional asserts() - predominantly to catch incorrect structure + packing. + +Changes between 160112 and 160111 releases + + + Updated the STM32 network driver so checksums are calculated by the + hardware. + + Implemented a simple "quit" command in the TCP command console. + +Changes between 150825 and 160111 releases + + + New device support: Demo applications and example drivers are provided + for Atmel SAM4E and ST STM32F4 microcontrollers. + + Various updates to improve compliance with the FreeRTOS coding standard. + + Added a command console example that uses TCP/IP for input and output (the + pre-existing command console example uses UDP/IP). + + Updated the UDP logging example so it will send log messages to the local + UDP broadcast address if a specific IP address is not provided. This + simplifies configuration, but note not all switches and routers will pass + broadcast messages. + + Add TCP echo client and TCP echo server examples to the Zynq demo. + + Minor updates to the Zynq network driver. + + Update the Zynq project to use version 2015.4 of the Xilinx SDK. + + Introduce FreeRTOS_SignalSocket(), which can be used to interrupt a task + that is blocked while reading from a socket ( FreeRTOS_recv[from] ). + + Make use of FreeRTOS_SignalSocket() in the FTP and HTTP servers. + + Major updates to the NTP client, although this is not included in any of + the pre-configured demo applications yet. + + Added support for DHCP zero pad option. + + Added uxGetMinimumIPQueueSpace(), a function to monitor the minimum amount + of space on the message queue. + + Better handling of zero length files in the FTP server. + + Fixed a bug reported by Andrey Ivanov from swissEmbedded that affects + users of 'ipconfigZERO_COPY_TX_DRIVER'. + + +Changes between 150825 150825 (?) + + + Added xApplicationDHCPUserHook() so a user defined hook will be + called at certain points in the DHCP process if + ipconfigDHCP_USES_USER_HOOK is set to 1. + + Added FreeRTOS_get_tx_head() to improve TCP zero copy behaviour - for + expert use only. + + RST is no longer sent if only the ACK flag is set. + + Previously, an immediate ACK was only sent when buffer space was + exhausted. Now, to improve performance, it is possible to send an + immediate ACK earlier - dependent on the ipconfigTCP_ACK_EARLIER_PACKET + setting. + + LLMNR and NBNS requests can now be sent to locate other devices - + previously these protocols would only be replied to, not generated. + + Added Auto-IP functionality (still in test) in case DHCP fails. Dependent + on the ipconfigDHCP_FALL_BACK_LINK_LAYER_ADDRESS and + ipconfigARP_USE_CLASH_DETECTION settings. + + Added NTP code and demo. + + FTP can now STOR and RETR zero-length files. + + Added LLMNR demo to Win32 demo - so now the Win32 responds to + "ping RTOSDemo". + +Changes between 141019 and 150825 + + + Added FTP server, which uses the new FreeRTOS+FAT component. + + Added basic HTTP server, which uses the new FreeRTOS+FAT component. + + Multiple definitions that are now common with FreeRTOS+FAT have been moved + into FreeRTOS's ProjDefs.h header file, and so prefixed with 'pd'. + + Introduced ipconfigZERO_COPY_TX_DRIVER, which defines who is responsible + for freeing a buffer sent to to the MAC driver for transmission, and + facilitates the development of zero copy drivers. + + Introduced the FREERTOS_MSG_DONTWAIT flag. The flag can be used as a + simpler and faster alternative to using FreeRTOS_setsockopt() to set the + send or receive timeout to 0. + + A few functions that were previously all lower case are now mixed case, as + lower case function names are only used when they are equivalent to a + a Berkeley sockets API function of the same name. + + Introduced uxGetMinimumFreeNetworkBuffers() to return the minimum number + of network buffers that have ever existed since the application started + executing. + + Introduce ipconfigETHERNET_MINIMUM_PACKET_BYTES to allow the application + writer to set their own minimum buffer size should the hardware not be + capable of padding under-sized Ethernet frames. + + vNetworkBufferRelease() renamed vReleaseNetworkBuffer() - just for + consistency with the names of other functions in the same file. + + Grouped DHCP status data into a structure. + + DHCP is now tried both with and without the broadcast flag. + + Replaced occurrences of configASSERT_VOID() with configASSERT(). + + ipconfigDNS_USE_CALLBACKS introduced to allow FreeRTOS_gethostbyname() to + be used without blocking. + + Fix: LLMNR and NBNS behaviour when the reply is in a larger buffer than the + request, and BufferAllocation_2 was used. + + Introduced ipMAX_IP_TASK_SLEEP_TIME to allow the application writer to + override the default value of 10 seconds. + + Fix: Correct error in *pxUDPPayloadBuffer_to_NetworkBuffer(). + + FreeRTOS_recv() now recognises the FREERTOS_ZERO_COPY flag, which, when + set, the void *pvBuffer parameter is interpreted as void **pvBuffer. + + FreeRTOS_listen() now returns an error code. Previously it always + returned 0. + + Fix: Previously if a listening socket was reused, and a connection + failed, the TCP/IP stack closed the socket, now the socket is correctly + left unclosed as it is owned by the application. + + Various other formatting and minor fix alterations. \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/LICENSE_INFORMATION.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/LICENSE_INFORMATION.txt new file mode 100644 index 0000000..24a8f88 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/LICENSE_INFORMATION.txt @@ -0,0 +1,19 @@ +FreeRTOS+TCP is released under the following MIT license. + +Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/ReadMe.url b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/ReadMe.url new file mode 100644 index 0000000..8a8017f --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/ReadMe.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 +[InternetShortcut] +URL=http://www.freertos.org/tcp +IDList= diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOSIPConfigDefaults.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOSIPConfigDefaults.h new file mode 100644 index 0000000..ebe531e --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOSIPConfigDefaults.h @@ -0,0 +1,560 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef FREERTOS_DEFAULT_IP_CONFIG_H +#define FREERTOS_DEFAULT_IP_CONFIG_H + +/* The error numbers defined in this file will be moved to the core FreeRTOS +code in future versions of FreeRTOS - at which time the following header file +will be removed. */ +#include "FreeRTOS_errno_TCP.h" + +/* This file provides default values for configuration options that are missing +from the FreeRTOSIPConfig.h configuration header file. */ + + +/* Ensure defined configuration constants are using the most up to date naming. */ +#ifdef tcpconfigIP_TIME_TO_LIVE + #error now called: ipconfigTCP_TIME_TO_LIVE +#endif + +#ifdef updconfigIP_TIME_TO_LIVE + #error now called: ipconfigUDP_TIME_TO_LIVE +#endif + +#ifdef ipFILLER_SIZE + #error now called: ipconfigPACKET_FILLER_SIZE +#endif + +#ifdef dnsMAX_REQUEST_ATTEMPTS + #error now called: ipconfigDNS_REQUEST_ATTEMPTS +#endif + +#ifdef ipconfigUDP_TASK_PRIORITY + #error now called: ipconfigIP_TASK_PRIORITY +#endif + +#ifdef ipconfigUDP_TASK_STACK_SIZE_WORDS + #error now called: ipconfigIP_TASK_STACK_SIZE_WORDS +#endif + +#ifdef ipconfigDRIVER_INCLUDED_RX_IP_FILTERING + #error now called: ipconfigETHERNET_DRIVER_FILTERS_PACKETS +#endif + +#ifdef ipconfigMAX_SEND_BLOCK_TIME_TICKS + #error now called: ipconfigUDP_MAX_SEND_BLOCK_TIME_TICKS +#endif + +#ifdef ipconfigUSE_RECEIVE_CONNECT_CALLBACKS + #error now called: ipconfigUSE_CALLBACKS +#endif + +#ifdef ipconfigNUM_NETWORK_BUFFERS + #error now called: ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS +#endif + +#ifdef ipconfigTCP_HANG_PROT + #error now called: ipconfigTCP_HANG_PROTECTION +#endif + +#ifdef ipconfigTCP_HANG_PROT_TIME + #error now called: ipconfigTCP_HANG_PROTECTION_TIME +#endif + +#ifdef FreeRTOS_lprintf + #error now called: FreeRTOS_debug_printf +#endif + +#if ( ipconfigEVENT_QUEUE_LENGTH < ( ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS + 5 ) ) + #error The ipconfigEVENT_QUEUE_LENGTH parameter must be at least ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS + 5 +#endif + +#if ( ipconfigNETWORK_MTU < 46 ) + #error ipconfigNETWORK_MTU must be at least 46. +#endif + +#ifdef ipconfigBUFFER_ALLOC_FIXED_SIZE + #error ipconfigBUFFER_ALLOC_FIXED_SIZE was dropped and replaced by a const value, declared in BufferAllocation[12].c +#endif + +#ifdef ipconfigNIC_SEND_PASSES_DMA + #error now called: ipconfigZERO_COPY_TX_DRIVER +#endif + +#ifdef HAS_TX_CRC_OFFLOADING + /* _HT_ As these macro names have changed, throw an error + if they're still defined. */ + #error now called: ipconfigHAS_TX_CRC_OFFLOADING +#endif + +#ifdef HAS_RX_CRC_OFFLOADING + #error now called: ipconfigHAS_RX_CRC_OFFLOADING +#endif + +#ifdef ipconfigTCP_RX_BUF_LEN + #error ipconfigTCP_RX_BUF_LEN is now called ipconfigTCP_RX_BUFFER_LENGTH +#endif + +#ifdef ipconfigTCP_TX_BUF_LEN + #error ipconfigTCP_TX_BUF_LEN is now called ipconfigTCP_TX_BUFFER_LENGTH +#endif + +#ifdef ipconfigDHCP_USES_USER_HOOK + #error ipconfigDHCP_USES_USER_HOOK and its associated callback have been superceeded - see http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/TCP_IP_Configuration.html#ipconfigUSE_DHCP_HOOK +#endif + +#ifndef ipconfigUSE_TCP + #define ipconfigUSE_TCP ( 1 ) +#endif + +#if ipconfigUSE_TCP + + /* Include support for TCP scaling windows */ + #ifndef ipconfigUSE_TCP_WIN + #define ipconfigUSE_TCP_WIN ( 1 ) + #endif + + #ifndef ipconfigTCP_WIN_SEG_COUNT + #define ipconfigTCP_WIN_SEG_COUNT ( 256 ) + #endif + + #ifndef ipconfigIGNORE_UNKNOWN_PACKETS + /* When non-zero, TCP will not send RST packets in reply to + TCP packets which are unknown, or out-of-order. */ + #define ipconfigIGNORE_UNKNOWN_PACKETS ( 0 ) + #endif +#endif + +/* + * For debuging/logging: check if the port number is used for telnet + * Some events will not be logged for telnet connections + * because it would produce logging about the transmission of the logging... + * This macro will only be used if FreeRTOS_debug_printf() is defined for logging + */ +#ifndef ipconfigTCP_MAY_LOG_PORT + #define ipconfigTCP_MAY_LOG_PORT(xPort) ( ( xPort ) != 23u ) +#endif + + +#ifndef ipconfigSOCK_DEFAULT_RECEIVE_BLOCK_TIME + #define ipconfigSOCK_DEFAULT_RECEIVE_BLOCK_TIME portMAX_DELAY +#endif + +#ifndef ipconfigSOCK_DEFAULT_SEND_BLOCK_TIME + #define ipconfigSOCK_DEFAULT_SEND_BLOCK_TIME portMAX_DELAY +#endif + +/* + * FreeRTOS debug logging routine (proposal) + * The macro will be called in the printf() style. Users can define + * their own logging routine as: + * + * #define FreeRTOS_debug_printf( MSG ) my_printf MSG + * + * The FreeRTOS_debug_printf() must be thread-safe but does not have to be + * interrupt-safe. + */ +#ifdef ipconfigHAS_DEBUG_PRINTF + #if( ipconfigHAS_DEBUG_PRINTF == 0 ) + #ifdef FreeRTOS_debug_printf + #error Do not define FreeRTOS_debug_print if ipconfigHAS_DEBUG_PRINTF is set to 0 + #endif /* ifdef FreeRTOS_debug_printf */ + #endif /* ( ipconfigHAS_DEBUG_PRINTF == 0 ) */ +#endif /* ifdef ipconfigHAS_DEBUG_PRINTF */ + +#ifndef FreeRTOS_debug_printf + #define FreeRTOS_debug_printf( MSG ) do{} while(0) + #define ipconfigHAS_DEBUG_PRINTF 0 +#endif + +/* + * FreeRTOS general logging routine (proposal) + * Used in some utility functions such as FreeRTOS_netstat() and FreeRTOS_PrintARPCache() + * + * #define FreeRTOS_printf( MSG ) my_printf MSG + * + * The FreeRTOS_printf() must be thread-safe but does not have to be interrupt-safe + */ +#ifdef ipconfigHAS_PRINTF + #if( ipconfigHAS_PRINTF == 0 ) + #ifdef FreeRTOS_printf + #error Do not define FreeRTOS_print if ipconfigHAS_PRINTF is set to 0 + #endif /* ifdef FreeRTOS_debug_printf */ + #endif /* ( ipconfigHAS_PRINTF == 0 ) */ +#endif /* ifdef ipconfigHAS_PRINTF */ + +#ifndef FreeRTOS_printf + #define FreeRTOS_printf( MSG ) do{} while(0) + #define ipconfigHAS_PRINTF 0 +#endif + +/* + * In cases where a lot of logging is produced, FreeRTOS_flush_logging( ) + * will be called to give the logging module a chance to flush the data + * An example of this is the netstat command, which produces many lines of logging + */ +#ifndef FreeRTOS_flush_logging + #define FreeRTOS_flush_logging( ) do{} while(0) +#endif + +/* Malloc functions. Within most applications of FreeRTOS, the couple + * pvPortMalloc()/vPortFree() will be used. + * If there is also SDRAM, the user may decide to use a different memory + * allocator: + * MallocLarge is used to allocate large TCP buffers (for Rx/Tx) + * MallocSocket is used to allocate the space for the sockets + */ +#ifndef pvPortMallocLarge + #define pvPortMallocLarge( x ) pvPortMalloc( x ) +#endif + +#ifndef vPortFreeLarge + #define vPortFreeLarge(ptr) vPortFree(ptr) +#endif + +#ifndef pvPortMallocSocket + #define pvPortMallocSocket( x ) pvPortMalloc( x ) +#endif + +#ifndef vPortFreeSocket + #define vPortFreeSocket(ptr) vPortFree(ptr) +#endif + +/* + * At several places within the library, random numbers are needed: + * - DHCP: For creating a DHCP transaction number + * - TCP: Set the Initial Sequence Number: this is the value of the first outgoing + * sequence number being used when connecting to a peer. + * Having a well randomised ISN is important to avoid spoofing + * - UDP/TCP: for setting the first port number to be used, in case a socket + * uses a 'random' or anonymous port number + */ +#ifndef ipconfigRAND32 + #define ipconfigRAND32() rand() +#endif +/* -------------------------------------------------------- + * End of: HT Added some macro defaults for the PLUS-UDP project + * -------------------------------------------------------- */ + +#ifndef ipconfigUSE_NETWORK_EVENT_HOOK + #define ipconfigUSE_NETWORK_EVENT_HOOK 0 +#endif + +#ifndef ipconfigUDP_MAX_SEND_BLOCK_TIME_TICKS + #define ipconfigUDP_MAX_SEND_BLOCK_TIME_TICKS ( pdMS_TO_TICKS( 20 ) ) +#endif + +#ifndef ipconfigARP_CACHE_ENTRIES + #define ipconfigARP_CACHE_ENTRIES 10 +#endif + +#ifndef ipconfigMAX_ARP_RETRANSMISSIONS + #define ipconfigMAX_ARP_RETRANSMISSIONS ( 5u ) +#endif + +#ifndef ipconfigMAX_ARP_AGE + #define ipconfigMAX_ARP_AGE 150u +#endif + +#ifndef ipconfigUSE_ARP_REVERSED_LOOKUP + #define ipconfigUSE_ARP_REVERSED_LOOKUP 0 +#endif + +#ifndef ipconfigUSE_ARP_REMOVE_ENTRY + #define ipconfigUSE_ARP_REMOVE_ENTRY 0 +#endif + +#ifndef ipconfigINCLUDE_FULL_INET_ADDR + #define ipconfigINCLUDE_FULL_INET_ADDR 1 +#endif + +#ifndef ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS + #define ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS 45 +#endif + +#ifndef ipconfigEVENT_QUEUE_LENGTH + #define ipconfigEVENT_QUEUE_LENGTH ( ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS + 5 ) +#endif + +#ifndef ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND + #define ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND 1 +#endif + +#ifndef ipconfigUDP_TIME_TO_LIVE + #define ipconfigUDP_TIME_TO_LIVE 128 +#endif + +#ifndef ipconfigTCP_TIME_TO_LIVE + #define ipconfigTCP_TIME_TO_LIVE 128 +#endif + +#ifndef ipconfigUDP_MAX_RX_PACKETS + /* Make postive to define the maximum number of packets which will be buffered + * for each UDP socket. + * Can be overridden with the socket option FREERTOS_SO_UDP_MAX_RX_PACKETS + */ + #define ipconfigUDP_MAX_RX_PACKETS 0u +#endif + +#ifndef ipconfigUSE_DHCP + #define ipconfigUSE_DHCP 1 +#endif + +#ifndef ipconfigUSE_DHCP_HOOK + #define ipconfigUSE_DHCP_HOOK 0 +#endif + +#ifndef ipconfigDHCP_FALL_BACK_AUTO_IP + /* + * Only applicable when DHCP is in use: + * If no DHCP server responds, use "Auto-IP" : the + * device will allocate a random LinkLayer IP address. + */ + #define ipconfigDHCP_FALL_BACK_AUTO_IP ( 0 ) +#endif + +#if( ipconfigDHCP_FALL_BACK_AUTO_IP != 0 ) + #define ipconfigARP_USE_CLASH_DETECTION 1 +#endif + +#ifndef ipconfigARP_USE_CLASH_DETECTION + #define ipconfigARP_USE_CLASH_DETECTION 0 +#endif + +#ifndef ipconfigNETWORK_MTU + #define ipconfigNETWORK_MTU 1500 +#endif + +#ifndef ipconfigTCP_MSS + #define ipconfigTCP_MSS ( ipconfigNETWORK_MTU - ipSIZE_OF_IPv4_HEADER - ipSIZE_OF_TCP_HEADER ) +#endif + +/* Each TCP socket has circular stream buffers for Rx and Tx, which + * have a fixed maximum size. + * The defaults for these size are defined here, although + * they can be overridden at runtime by using the setsockopt() call */ +#ifndef ipconfigTCP_RX_BUFFER_LENGTH + #define ipconfigTCP_RX_BUFFER_LENGTH ( 4u * ipconfigTCP_MSS ) /* defaults to 5840 bytes */ +#endif + +/* Define the size of Tx stream buffer for TCP sockets */ +#ifndef ipconfigTCP_TX_BUFFER_LENGTH +# define ipconfigTCP_TX_BUFFER_LENGTH ( 4u * ipconfigTCP_MSS ) /* defaults to 5840 bytes */ +#endif + +#ifndef ipconfigMAXIMUM_DISCOVER_TX_PERIOD + #ifdef _WINDOWS_ + #define ipconfigMAXIMUM_DISCOVER_TX_PERIOD ( pdMS_TO_TICKS( 999 ) ) + #else + #define ipconfigMAXIMUM_DISCOVER_TX_PERIOD ( pdMS_TO_TICKS( 30000 ) ) + #endif /* _WINDOWS_ */ +#endif /* ipconfigMAXIMUM_DISCOVER_TX_PERIOD */ + +#ifndef ipconfigUSE_DNS + #define ipconfigUSE_DNS 1 +#endif + +#ifndef ipconfigDNS_REQUEST_ATTEMPTS + #define ipconfigDNS_REQUEST_ATTEMPTS 5 +#endif + +#ifndef ipconfigUSE_DNS_CACHE + #define ipconfigUSE_DNS_CACHE 0 +#endif + +#if( ipconfigUSE_DNS_CACHE != 0 ) + #ifndef ipconfigDNS_CACHE_NAME_LENGTH + /* Per https://tools.ietf.org/html/rfc1035, 253 is the maximum string length + of a DNS name. The following default accounts for a null terminator. */ + #define ipconfigDNS_CACHE_NAME_LENGTH 254 + #endif + + #ifndef ipconfigDNS_CACHE_ENTRIES + #define ipconfigDNS_CACHE_ENTRIES 1 + #endif +#endif /* ipconfigUSE_DNS_CACHE != 0 */ + +#ifndef ipconfigCHECK_IP_QUEUE_SPACE + #define ipconfigCHECK_IP_QUEUE_SPACE 0 +#endif + +#ifndef ipconfigUSE_LLMNR + /* Include support for LLMNR: Link-local Multicast Name Resolution (non-Microsoft) */ + #define ipconfigUSE_LLMNR ( 0 ) +#endif + +#if( !defined( ipconfigUSE_DNS ) ) + #if( ( ipconfigUSE_LLMNR != 0 ) || ( ipconfigUSE_NBNS != 0 ) ) + /* LLMNR and NBNS depend on DNS because those protocols share a lot of code. */ + #error When either LLMNR or NBNS is used, ipconfigUSE_DNS must be defined + #endif +#endif + +#ifndef ipconfigREPLY_TO_INCOMING_PINGS + #define ipconfigREPLY_TO_INCOMING_PINGS 1 +#endif + +#ifndef ipconfigSUPPORT_OUTGOING_PINGS + #define ipconfigSUPPORT_OUTGOING_PINGS 0 +#endif + +#ifndef ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES + #define ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES 1 +#endif + +#ifndef ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES + #define ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES 1 +#endif + +#ifndef configINCLUDE_TRACE_RELATED_CLI_COMMANDS + #define ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS 0 +#else + #define ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS configINCLUDE_TRACE_RELATED_CLI_COMMANDS +#endif + +#ifndef ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM + #define ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM ( 0 ) +#endif + +#ifndef ipconfigETHERNET_DRIVER_FILTERS_PACKETS + #define ipconfigETHERNET_DRIVER_FILTERS_PACKETS ( 0 ) +#endif + +#ifndef ipconfigWATCHDOG_TIMER + /* This macro will be called in every loop the IP-task makes. It may be + replaced by user-code that triggers a watchdog */ + #define ipconfigWATCHDOG_TIMER() +#endif + +#ifndef ipconfigUSE_CALLBACKS + #define ipconfigUSE_CALLBACKS ( 0 ) +#endif + +#if( ipconfigUSE_CALLBACKS != 0 ) + #ifndef ipconfigIS_VALID_PROG_ADDRESS + /* Replace this macro with a test returning non-zero if the memory pointer to by x + * is valid memory which can contain executable code + * In fact this is an extra safety measure: if a handler points to invalid memory, + * it will not be called + */ + #define ipconfigIS_VALID_PROG_ADDRESS(x) ( ( x ) != NULL ) + #endif +#endif + +#ifndef ipconfigHAS_INLINE_FUNCTIONS + #define ipconfigHAS_INLINE_FUNCTIONS ( 1 ) +#endif + +#ifndef portINLINE + #define portINLINE inline +#endif + +#ifndef ipconfigZERO_COPY_TX_DRIVER + /* When non-zero, the buffers passed to the SEND routine may be passed + to DMA. As soon as sending is ready, the buffers must be released by + calling vReleaseNetworkBufferAndDescriptor(), */ + #define ipconfigZERO_COPY_TX_DRIVER ( 0 ) +#endif + +#ifndef ipconfigZERO_COPY_RX_DRIVER + /* This define doesn't mean much to the driver, except that it makes + sure that pxPacketBuffer_to_NetworkBuffer() will be included. */ + #define ipconfigZERO_COPY_RX_DRIVER ( 0 ) +#endif + +#ifndef ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM + #define ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM 0 +#endif + +#ifndef ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM + #define ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM 0 +#endif + +#ifndef ipconfigDHCP_REGISTER_HOSTNAME + #define ipconfigDHCP_REGISTER_HOSTNAME 0 +#endif + +#ifndef ipconfigSOCKET_HAS_USER_SEMAPHORE + #define ipconfigSOCKET_HAS_USER_SEMAPHORE 0 +#endif + +#ifndef ipconfigSOCKET_HAS_USER_WAKE_CALLBACK + #define ipconfigSOCKET_HAS_USER_WAKE_CALLBACK 0 +#endif + +#ifndef ipconfigSUPPORT_SELECT_FUNCTION + #define ipconfigSUPPORT_SELECT_FUNCTION 0 +#endif + +#ifndef ipconfigTCP_KEEP_ALIVE + #define ipconfigTCP_KEEP_ALIVE 0 +#endif + +#ifndef ipconfigDNS_USE_CALLBACKS + #define ipconfigDNS_USE_CALLBACKS 0 +#endif + +#ifndef ipconfigSUPPORT_SIGNALS + #define ipconfigSUPPORT_SIGNALS 0 +#endif + +#ifndef ipconfigUSE_NBNS + #define ipconfigUSE_NBNS 0 +#endif + +/* As an attack surface reduction for ports that listen for inbound +connections, hang protection can help reduce the impact of SYN floods. */ +#ifndef ipconfigTCP_HANG_PROTECTION + #define ipconfigTCP_HANG_PROTECTION 1 +#endif + +/* Non-activity timeout is expressed in seconds. */ +#ifndef ipconfigTCP_HANG_PROTECTION_TIME + #define ipconfigTCP_HANG_PROTECTION_TIME 30 +#endif + +#ifndef ipconfigTCP_IP_SANITY + #define ipconfigTCP_IP_SANITY 0 +#endif + +#ifndef ipconfigARP_STORES_REMOTE_ADDRESSES + #define ipconfigARP_STORES_REMOTE_ADDRESSES 0 +#endif + +#ifndef ipconfigBUFFER_PADDING + /* Expert option: define a value for 'ipBUFFER_PADDING'. + When 'ipconfigBUFFER_PADDING' equals 0, + 'ipBUFFER_PADDING' will get a default value of 8 + 2 bytes. */ + #define ipconfigBUFFER_PADDING 0 +#endif + +#ifndef ipconfigPACKET_FILLER_SIZE + #define ipconfigPACKET_FILLER_SIZE 2 +#endif + +#endif /* FREERTOS_DEFAULT_IP_CONFIG_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_ARP.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_ARP.h new file mode 100644 index 0000000..b9974b4 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_ARP.h @@ -0,0 +1,141 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +#ifndef FREERTOS_ARP_H +#define FREERTOS_ARP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Application level configuration options. */ +#include "FreeRTOSIPConfig.h" +#include "FreeRTOSIPConfigDefaults.h" +#include "IPTraceMacroDefaults.h" + +/*-----------------------------------------------------------*/ +/* Miscellaneous structure and definitions. */ +/*-----------------------------------------------------------*/ + +typedef struct xARP_CACHE_TABLE_ROW +{ + uint32_t ulIPAddress; /* The IP address of an ARP cache entry. */ + MACAddress_t xMACAddress; /* The MAC address of an ARP cache entry. */ + uint8_t ucAge; /* A value that is periodically decremented but can also be refreshed by active communication. The ARP cache entry is removed if the value reaches zero. */ + uint8_t ucValid; /* pdTRUE: xMACAddress is valid, pdFALSE: waiting for ARP reply */ +} ARPCacheRow_t; + +typedef enum +{ + eARPCacheMiss = 0, /* 0 An ARP table lookup did not find a valid entry. */ + eARPCacheHit, /* 1 An ARP table lookup found a valid entry. */ + eCantSendPacket /* 2 There is no IP address, or an ARP is still in progress, so the packet cannot be sent. */ +} eARPLookupResult_t; + +typedef enum +{ + eNotFragment = 0, /* The IP packet being sent is not part of a fragment. */ + eFirstFragment, /* The IP packet being sent is the first in a set of fragmented packets. */ + eFollowingFragment /* The IP packet being sent is part of a set of fragmented packets. */ +} eIPFragmentStatus_t; + +/* + * If ulIPAddress is already in the ARP cache table then reset the age of the + * entry back to its maximum value. If ulIPAddress is not already in the ARP + * cache table then add it - replacing the oldest current entry if there is not + * a free space available. + */ +void vARPRefreshCacheEntry( const MACAddress_t * pxMACAddress, const uint32_t ulIPAddress ); + +#if( ipconfigARP_USE_CLASH_DETECTION != 0 ) + /* Becomes non-zero if another device responded to a gratuitos ARP message. */ + extern BaseType_t xARPHadIPClash; + /* MAC-address of the other device containing the same IP-address. */ + extern MACAddress_t xARPClashMacAddress; +#endif /* ipconfigARP_USE_CLASH_DETECTION */ + +#if( ipconfigUSE_ARP_REMOVE_ENTRY != 0 ) + + /* + * In some rare cases, it might be useful to remove a ARP cache entry of a + * known MAC address to make sure it gets refreshed. + */ + uint32_t ulARPRemoveCacheEntryByMac( const MACAddress_t * pxMACAddress ); + +#endif /* ipconfigUSE_ARP_REMOVE_ENTRY != 0 */ + +/* + * Look for ulIPAddress in the ARP cache. If the IP address exists, copy the + * associated MAC address into pxMACAddress, refresh the ARP cache entry's + * age, and return eARPCacheHit. If the IP address does not exist in the ARP + * cache return eARPCacheMiss. If the packet cannot be sent for any reason + * (maybe DHCP is still in process, or the addressing needs a gateway but there + * isn't a gateway defined) then return eCantSendPacket. + */ +eARPLookupResult_t eARPGetCacheEntry( uint32_t *pulIPAddress, MACAddress_t * const pxMACAddress ); + +#if( ipconfigUSE_ARP_REVERSED_LOOKUP != 0 ) + + /* Lookup an IP-address if only the MAC-address is known */ + eARPLookupResult_t eARPGetCacheEntryByMac( MACAddress_t * const pxMACAddress, uint32_t *pulIPAddress ); + +#endif +/* + * Reduce the age count in each entry within the ARP cache. An entry is no + * longer considered valid and is deleted if its age reaches zero. + */ +void vARPAgeCache( void ); + +/* + * Send out an ARP request for the IP address contained in pxNetworkBuffer, and + * add an entry into the ARP table that indicates that an ARP reply is + * outstanding so re-transmissions can be generated. + */ +void vARPGenerateRequestPacket( NetworkBufferDescriptor_t * const pxNetworkBuffer ); + +/* + * After DHCP is ready and when changing IP address, force a quick send of our new IP + * address + */ +void vARPSendGratuitous( void ); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif /* FREERTOS_ARP_H */ + + + + + + + + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_DHCP.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_DHCP.h new file mode 100644 index 0000000..64421e5 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_DHCP.h @@ -0,0 +1,87 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +#ifndef FREERTOS_DHCP_H +#define FREERTOS_DHCP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Application level configuration options. */ +#include "FreeRTOSIPConfig.h" +#include "IPTraceMacroDefaults.h" + +/* Used in the DHCP callback if ipconfigUSE_DHCP_HOOK is set to 1. */ +typedef enum eDHCP_PHASE +{ + eDHCPPhasePreDiscover, /* Driver is about to send a DHCP discovery. */ + eDHCPPhasePreRequest, /* Driver is about to request DHCP an IP address. */ +#if( ipconfigDHCP_SEND_DISCOVER_AFTER_AUTO_IP != 0 ) + eDHCPPhasePreLLA, /* Driver is about to try get an LLA address */ +#endif /* ipconfigDHCP_SEND_DISCOVER_AFTER_AUTO_IP */ +} eDHCPCallbackPhase_t; + +/* Used in the DHCP callback if ipconfigUSE_DHCP_HOOK is set to 1. */ +typedef enum eDHCP_ANSWERS +{ + eDHCPContinue, /* Continue the DHCP process */ + eDHCPUseDefaults, /* Stop DHCP and use the static defaults. */ + eDHCPStopNoChanges, /* Stop DHCP and continue with current settings. */ +} eDHCPCallbackAnswer_t; + +/* + * NOT A PUBLIC API FUNCTION. + */ +void vDHCPProcess( BaseType_t xReset ); + +/* Internal call: returns true if socket is the current DHCP socket */ +BaseType_t xIsDHCPSocket( Socket_t xSocket ); + +/* Prototype of the hook (or callback) function that must be provided by the +application if ipconfigUSE_DHCP_HOOK is set to 1. See the following URL for +usage information: +http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/TCP_IP_Configuration.html#ipconfigUSE_DHCP_HOOK +*/ +eDHCPCallbackAnswer_t xApplicationDHCPHook( eDHCPCallbackPhase_t eDHCPPhase, uint32_t ulIPAddress ); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* FREERTOS_DHCP_H */ + + + + + + + + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_DNS.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_DNS.h new file mode 100644 index 0000000..cf59577 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_DNS.h @@ -0,0 +1,133 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +#ifndef FREERTOS_DNS_H +#define FREERTOS_DNS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Application level configuration options. */ +#include "FreeRTOSIPConfig.h" +#include "IPTraceMacroDefaults.h" + + +/* The Link-local Multicast Name Resolution (LLMNR) + * is included. + * Note that a special MAC address is required in addition to the NIC's actual + * MAC address: 01:00:5E:00:00:FC + * + * The target IP address will be 224.0.0.252 + */ +#if( ipconfigBYTE_ORDER == pdFREERTOS_BIG_ENDIAN ) + #define ipLLMNR_IP_ADDR 0xE00000FC +#else + #define ipLLMNR_IP_ADDR 0xFC0000E0 +#endif /* ipconfigBYTE_ORDER == pdFREERTOS_BIG_ENDIAN */ + +#define ipLLMNR_PORT 5355 /* Standard LLMNR port. */ +#define ipDNS_PORT 53 /* Standard DNS port. */ +#define ipDHCP_CLIENT 67 +#define ipDHCP_SERVER 68 +#define ipNBNS_PORT 137 /* NetBIOS Name Service. */ +#define ipNBDGM_PORT 138 /* Datagram Service, not included. */ + +/* + * The following function should be provided by the user and return true if it + * matches the domain name. + */ +extern BaseType_t xApplicationDNSQueryHook( const char *pcName ); + +/* + * LLMNR is very similar to DNS, so is handled by the DNS routines. + */ +uint32_t ulDNSHandlePacket( NetworkBufferDescriptor_t *pxNetworkBuffer ); + +#if( ipconfigUSE_LLMNR == 1 ) + extern const MACAddress_t xLLMNR_MacAdress; +#endif /* ipconfigUSE_LLMNR */ + +#if( ipconfigUSE_NBNS != 0 ) + + /* + * Inspect a NetBIOS Names-Service message. If the name matches with ours + * (xApplicationDNSQueryHook returns true) an answer will be sent back. + * Note that LLMNR is a better protocol for name services on a LAN as it is + * less polluted + */ + uint32_t ulNBNSHandlePacket (NetworkBufferDescriptor_t *pxNetworkBuffer ); + +#endif /* ipconfigUSE_NBNS */ + +#if( ipconfigUSE_DNS_CACHE != 0 ) + + uint32_t FreeRTOS_dnslookup( const char *pcHostName ); + +#endif /* ipconfigUSE_DNS_CACHE != 0 */ + +#if( ipconfigDNS_USE_CALLBACKS != 0 ) + + /* + * Users may define this type of function as a callback. + * It will be called when a DNS reply is received or when a timeout has been reached. + */ + typedef void (* FOnDNSEvent ) ( const char * /* pcName */, void * /* pvSearchID */, uint32_t /* ulIPAddress */ ); + + /* + * Asynchronous version of gethostbyname() + * xTimeout is in units of ms. + */ + uint32_t FreeRTOS_gethostbyname_a( const char *pcHostName, FOnDNSEvent pCallback, void *pvSearchID, TickType_t xTimeout ); + void FreeRTOS_gethostbyname_cancel( void *pvSearchID ); + +#endif + +/* + * FULL, UP-TO-DATE AND MAINTAINED REFERENCE DOCUMENTATION FOR ALL THESE + * FUNCTIONS IS AVAILABLE ON THE FOLLOWING URL: + * _TBD_ Add URL + */ +uint32_t FreeRTOS_gethostbyname( const char *pcHostName ); + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* FREERTOS_DNS_H */ + + + + + + + + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_IP.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_IP.h new file mode 100644 index 0000000..1ac4ed7 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_IP.h @@ -0,0 +1,328 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +#ifndef FREERTOS_IP_H +#define FREERTOS_IP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Application level configuration options. */ +#include "FreeRTOSIPConfig.h" +#include "FreeRTOSIPConfigDefaults.h" +#include "IPTraceMacroDefaults.h" + +/* Some constants defining the sizes of several parts of a packet */ +#define ipSIZE_OF_ETH_HEADER 14u +#define ipSIZE_OF_IPv4_HEADER 20u +#define ipSIZE_OF_IGMP_HEADER 8u +#define ipSIZE_OF_ICMP_HEADER 8u +#define ipSIZE_OF_UDP_HEADER 8u +#define ipSIZE_OF_TCP_HEADER 20u + + +/* The number of octets in the MAC and IP addresses respectively. */ +#define ipMAC_ADDRESS_LENGTH_BYTES ( 6 ) +#define ipIP_ADDRESS_LENGTH_BYTES ( 4 ) + +/* IP protocol definitions. */ +#define ipPROTOCOL_ICMP ( 1 ) +#define ipPROTOCOL_IGMP ( 2 ) +#define ipPROTOCOL_TCP ( 6 ) +#define ipPROTOCOL_UDP ( 17 ) + +/* Dimensions the buffers that are filled by received Ethernet frames. */ +#define ipSIZE_OF_ETH_CRC_BYTES ( 4UL ) +#define ipSIZE_OF_ETH_OPTIONAL_802_1Q_TAG_BYTES ( 4UL ) +#define ipTOTAL_ETHERNET_FRAME_SIZE ( ( ( uint32_t ) ipconfigNETWORK_MTU ) + ( ( uint32_t ) ipSIZE_OF_ETH_HEADER ) + ipSIZE_OF_ETH_CRC_BYTES + ipSIZE_OF_ETH_OPTIONAL_802_1Q_TAG_BYTES ) + +/*_RB_ Comment may need updating. */ +/* Space left at the beginning of a network buffer storage area to store a +pointer back to the network buffer. Should be a multiple of 8 to ensure 8 byte +alignment is maintained on architectures that require it. + +In order to get a 32-bit alignment of network packets, an offset of 2 bytes +would be desirable, as defined by ipconfigPACKET_FILLER_SIZE. So the malloc'd +buffer will have the following contents: + uint32_t pointer; // word-aligned + uchar_8 filler[6]; + << ETH-header >> // half-word-aligned + uchar_8 dest[6]; // start of pucEthernetBuffer + uchar_8 dest[6]; + uchar16_t type; + << IP-header >> // word-aligned + uint8_t ucVersionHeaderLength; + etc + */ +#if( ipconfigBUFFER_PADDING != 0 ) + #define ipBUFFER_PADDING ipconfigBUFFER_PADDING +#else + #define ipBUFFER_PADDING ( 8u + ipconfigPACKET_FILLER_SIZE ) +#endif + +/* The structure used to store buffers and pass them around the network stack. +Buffers can be in use by the stack, in use by the network interface hardware +driver, or free (not in use). */ +typedef struct xNETWORK_BUFFER +{ + ListItem_t xBufferListItem; /* Used to reference the buffer form the free buffer list or a socket. */ + uint32_t ulIPAddress; /* Source or destination IP address, depending on usage scenario. */ + uint8_t *pucEthernetBuffer; /* Pointer to the start of the Ethernet frame. */ + size_t xDataLength; /* Starts by holding the total Ethernet frame length, then the UDP/TCP payload length. */ + uint16_t usPort; /* Source or destination port, depending on usage scenario. */ + uint16_t usBoundPort; /* The port to which a transmitting socket is bound. */ + #if( ipconfigUSE_LINKED_RX_MESSAGES != 0 ) + struct xNETWORK_BUFFER *pxNextBuffer; /* Possible optimisation for expert users - requires network driver support. */ + #endif +} NetworkBufferDescriptor_t; + +#include "pack_struct_start.h" +struct xMAC_ADDRESS +{ + uint8_t ucBytes[ ipMAC_ADDRESS_LENGTH_BYTES ]; +} +#include "pack_struct_end.h" + +typedef struct xMAC_ADDRESS MACAddress_t; + +typedef enum eNETWORK_EVENTS +{ + eNetworkUp, /* The network is configured. */ + eNetworkDown /* The network connection has been lost. */ +} eIPCallbackEvent_t; + +typedef enum ePING_REPLY_STATUS +{ + eSuccess = 0, /* A correct reply has been received for an outgoing ping. */ + eInvalidChecksum, /* A reply was received for an outgoing ping but the checksum of the reply was incorrect. */ + eInvalidData /* A reply was received to an outgoing ping but the payload of the reply was not correct. */ +} ePingReplyStatus_t; + +typedef enum eNETWORK_ADDRESS_TYPE +{ + eNetWorkAddressTypeIPV4, + eNetWorkAddressTypeIPV6, + eNetWorkAddressTypeHostName +} eNetWorkAddressType_t; + +/* Endian related definitions. */ +#if( ipconfigBYTE_ORDER == pdFREERTOS_LITTLE_ENDIAN ) + + /* FreeRTOS_htons / FreeRTOS_htonl: some platforms might have built-in versions + using a single instruction so allow these versions to be overridden. */ + #ifndef FreeRTOS_htons + #define FreeRTOS_htons( usIn ) ( (uint16_t) ( ( ( usIn ) << 8U ) | ( ( usIn ) >> 8U ) ) ) + #endif + + #ifndef FreeRTOS_htonl + #define FreeRTOS_htonl( ulIn ) \ + ( \ + ( uint32_t ) \ + ( \ + ( ( ( ( uint32_t ) ( ulIn ) ) ) << 24 ) | \ + ( ( ( ( uint32_t ) ( ulIn ) ) & 0x0000ff00UL ) << 8 ) | \ + ( ( ( ( uint32_t ) ( ulIn ) ) & 0x00ff0000UL ) >> 8 ) | \ + ( ( ( ( uint32_t ) ( ulIn ) ) ) >> 24 ) \ + ) \ + ) + #endif + +#else /* ipconfigBYTE_ORDER */ + + #define FreeRTOS_htons( x ) ( ( uint16_t ) ( x ) ) + #define FreeRTOS_htonl( x ) ( ( uint32_t ) ( x ) ) + +#endif /* ipconfigBYTE_ORDER == pdFREERTOS_LITTLE_ENDIAN */ + +#define FreeRTOS_ntohs( x ) FreeRTOS_htons( x ) +#define FreeRTOS_ntohl( x ) FreeRTOS_htonl( x ) + +#if( ipconfigHAS_INLINE_FUNCTIONS == 1 ) + + static portINLINE int32_t FreeRTOS_max_int32 (int32_t a, int32_t b); + static portINLINE uint32_t FreeRTOS_max_uint32 (uint32_t a, uint32_t b); + static portINLINE int32_t FreeRTOS_min_int32 (int32_t a, int32_t b); + static portINLINE uint32_t FreeRTOS_min_uint32 (uint32_t a, uint32_t b); + static portINLINE uint32_t FreeRTOS_round_up (uint32_t a, uint32_t d); + static portINLINE uint32_t FreeRTOS_round_down (uint32_t a, uint32_t d); + static portINLINE BaseType_t FreeRTOS_min_BaseType (BaseType_t a, BaseType_t b); + static portINLINE BaseType_t FreeRTOS_max_BaseType (BaseType_t a, BaseType_t b); + static portINLINE UBaseType_t FreeRTOS_max_UBaseType (UBaseType_t a, UBaseType_t b); + static portINLINE UBaseType_t FreeRTOS_min_UBaseType (UBaseType_t a, UBaseType_t b); + + + static portINLINE int32_t FreeRTOS_max_int32 (int32_t a, int32_t b) { return a >= b ? a : b; } + static portINLINE uint32_t FreeRTOS_max_uint32 (uint32_t a, uint32_t b) { return a >= b ? a : b; } + static portINLINE int32_t FreeRTOS_min_int32 (int32_t a, int32_t b) { return a <= b ? a : b; } + static portINLINE uint32_t FreeRTOS_min_uint32 (uint32_t a, uint32_t b) { return a <= b ? a : b; } + static portINLINE uint32_t FreeRTOS_round_up (uint32_t a, uint32_t d) { return d * ( ( a + d - 1u ) / d ); } + static portINLINE uint32_t FreeRTOS_round_down (uint32_t a, uint32_t d) { return d * ( a / d ); } + + static portINLINE BaseType_t FreeRTOS_max_BaseType (BaseType_t a, BaseType_t b) { return a >= b ? a : b; } + static portINLINE UBaseType_t FreeRTOS_max_UBaseType (UBaseType_t a, UBaseType_t b) { return a >= b ? a : b; } + static portINLINE BaseType_t FreeRTOS_min_BaseType (BaseType_t a, BaseType_t b) { return a <= b ? a : b; } + static portINLINE UBaseType_t FreeRTOS_min_UBaseType (UBaseType_t a, UBaseType_t b) { return a <= b ? a : b; } + +#else + + #define FreeRTOS_max_int32(a,b) ( ( ( int32_t ) ( a ) ) >= ( ( int32_t ) ( b ) ) ? ( ( int32_t ) ( a ) ) : ( ( int32_t ) ( b ) ) ) + #define FreeRTOS_max_uint32(a,b) ( ( ( uint32_t ) ( a ) ) >= ( ( uint32_t ) ( b ) ) ? ( ( uint32_t ) ( a ) ) : ( ( uint32_t ) ( b ) ) ) + + #define FreeRTOS_min_int32(a,b) ( ( ( int32_t ) a ) <= ( ( int32_t ) b ) ? ( ( int32_t ) a ) : ( ( int32_t ) b ) ) + #define FreeRTOS_min_uint32(a,b) ( ( ( uint32_t ) a ) <= ( ( uint32_t ) b ) ? ( ( uint32_t ) a ) : ( ( uint32_t ) b ) ) + + /* Round-up: a = d * ( ( a + d - 1 ) / d ) */ + #define FreeRTOS_round_up(a,d) ( ( ( uint32_t ) ( d ) ) * ( ( ( ( uint32_t ) ( a ) ) + ( ( uint32_t ) ( d ) ) - 1UL ) / ( ( uint32_t ) ( d ) ) ) ) + #define FreeRTOS_round_down(a,d) ( ( ( uint32_t ) ( d ) ) * ( ( ( uint32_t ) ( a ) ) / ( ( uint32_t ) ( d ) ) ) ) + + #define FreeRTOS_ms_to_tick(ms) ( ( ms * configTICK_RATE_HZ + 500 ) / 1000 ) + + #define FreeRTOS_max_BaseType(a, b) ( ( ( BaseType_t ) ( a ) ) >= ( ( BaseType_t ) ( b ) ) ? ( ( BaseType_t ) ( a ) ) : ( ( BaseType_t ) ( b ) ) ) + #define FreeRTOS_max_UBaseType(a, b) ( ( ( UBaseType_t ) ( a ) ) >= ( ( UBaseType_t ) ( b ) ) ? ( ( UBaseType_t ) ( a ) ) : ( ( UBaseType_t ) ( b ) ) ) + #define FreeRTOS_min_BaseType(a, b) ( ( ( BaseType_t ) ( a ) ) <= ( ( BaseType_t ) ( b ) ) ? ( ( BaseType_t ) ( a ) ) : ( ( BaseType_t ) ( b ) ) ) + #define FreeRTOS_min_UBaseType(a, b) ( ( ( UBaseType_t ) ( a ) ) <= ( ( UBaseType_t ) ( b ) ) ? ( ( UBaseType_t ) ( a ) ) : ( ( UBaseType_t ) ( b ) ) ) + +#endif /* ipconfigHAS_INLINE_FUNCTIONS */ + +#define pdMS_TO_MIN_TICKS( xTimeInMs ) ( pdMS_TO_TICKS( ( xTimeInMs ) ) < ( ( TickType_t ) 1 ) ? ( ( TickType_t ) 1 ) : pdMS_TO_TICKS( ( xTimeInMs ) ) ) + +#ifndef pdTRUE_SIGNED + /* Temporary solution: eventually the defines below will appear in 'Source\include\projdefs.h' */ + #define pdTRUE_SIGNED pdTRUE + #define pdFALSE_SIGNED pdFALSE + #define pdTRUE_UNSIGNED ( ( UBaseType_t ) 1u ) + #define pdFALSE_UNSIGNED ( ( UBaseType_t ) 0u ) +#endif + +/* + * FULL, UP-TO-DATE AND MAINTAINED REFERENCE DOCUMENTATION FOR ALL THESE + * FUNCTIONS IS AVAILABLE ON THE FOLLOWING URL: + * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/FreeRTOS_TCP_API_Functions.html + */ +BaseType_t FreeRTOS_IPInit( const uint8_t ucIPAddress[ ipIP_ADDRESS_LENGTH_BYTES ], + const uint8_t ucNetMask[ ipIP_ADDRESS_LENGTH_BYTES ], + const uint8_t ucGatewayAddress[ ipIP_ADDRESS_LENGTH_BYTES ], + const uint8_t ucDNSServerAddress[ ipIP_ADDRESS_LENGTH_BYTES ], + const uint8_t ucMACAddress[ ipMAC_ADDRESS_LENGTH_BYTES ] ); + +void * FreeRTOS_GetUDPPayloadBuffer( size_t xRequestedSizeBytes, TickType_t xBlockTimeTicks ); +void FreeRTOS_GetAddressConfiguration( uint32_t *pulIPAddress, uint32_t *pulNetMask, uint32_t *pulGatewayAddress, uint32_t *pulDNSServerAddress ); +void FreeRTOS_SetAddressConfiguration( const uint32_t *pulIPAddress, const uint32_t *pulNetMask, const uint32_t *pulGatewayAddress, const uint32_t *pulDNSServerAddress ); +BaseType_t FreeRTOS_SendPingRequest( uint32_t ulIPAddress, size_t xNumberOfBytesToSend, TickType_t xBlockTimeTicks ); +void FreeRTOS_ReleaseUDPPayloadBuffer( void *pvBuffer ); +const uint8_t * FreeRTOS_GetMACAddress( void ); +void FreeRTOS_UpdateMACAddress( const uint8_t ucMACAddress[ipMAC_ADDRESS_LENGTH_BYTES] ); +void vApplicationIPNetworkEventHook( eIPCallbackEvent_t eNetworkEvent ); +void vApplicationPingReplyHook( ePingReplyStatus_t eStatus, uint16_t usIdentifier ); +uint32_t FreeRTOS_GetIPAddress( void ); +void FreeRTOS_SetIPAddress( uint32_t ulIPAddress ); +void FreeRTOS_SetNetmask( uint32_t ulNetmask ); +void FreeRTOS_SetGatewayAddress( uint32_t ulGatewayAddress ); +uint32_t FreeRTOS_GetGatewayAddress( void ); +uint32_t FreeRTOS_GetDNSServerAddress( void ); +uint32_t FreeRTOS_GetNetmask( void ); +void FreeRTOS_OutputARPRequest( uint32_t ulIPAddress ); +BaseType_t FreeRTOS_IsNetworkUp( void ); + +#if( ipconfigCHECK_IP_QUEUE_SPACE != 0 ) + UBaseType_t uxGetMinimumIPQueueSpace( void ); +#endif + +/* + * Defined in FreeRTOS_Sockets.c + * //_RB_ Don't think this comment is correct. If this is for internal use only it should appear after all the public API functions and not start with FreeRTOS_. + * Socket has had activity, reset the timer so it will not be closed + * because of inactivity + */ +const char *FreeRTOS_GetTCPStateName( UBaseType_t ulState); + +/* _HT_ Temporary: show all valid ARP entries + */ +void FreeRTOS_PrintARPCache( void ); +void FreeRTOS_ClearARP( void ); + +#if( ipconfigDHCP_REGISTER_HOSTNAME == 1 ) + + /* DHCP has an option for clients to register their hostname. It doesn't + have much use, except that a device can be found in a router along with its + name. If this option is used the callback below must be provided by the + application writer to return a const string, denoting the device's name. */ + const char *pcApplicationHostnameHook( void ); + +#endif /* ipconfigDHCP_REGISTER_HOSTNAME */ + + +/* For backward compatibility define old structure names to the newer equivalent +structure name. */ +#ifndef ipconfigENABLE_BACKWARD_COMPATIBILITY + #define ipconfigENABLE_BACKWARD_COMPATIBILITY 1 +#endif + +#if( ipconfigENABLE_BACKWARD_COMPATIBILITY == 1 ) + #define xIPStackEvent_t IPStackEvent_t + #define xNetworkBufferDescriptor_t NetworkBufferDescriptor_t + #define xMACAddress_t MACAddress_t + #define xWinProperties_t WinProperties_t + #define xSocket_t Socket_t + #define xSocketSet_t SocketSet_t + #define ipSIZE_OF_IP_HEADER ipSIZE_OF_IPv4_HEADER + + /* Since August 2016, the public types and fields below have changed name: + abbreviations TCP/UDP are now written in capitals, and type names now end with "_t". */ + #define FOnConnected FOnConnected_t + #define FOnTcpReceive FOnTCPReceive_t + #define FOnTcpSent FOnTCPSent_t + #define FOnUdpReceive FOnUDPReceive_t + #define FOnUdpSent FOnUDPSent_t + + #define pOnTcpConnected pxOnTCPConnected + #define pOnTcpReceive pxOnTCPReceive + #define pOnTcpSent pxOnTCPSent + #define pOnUdpReceive pxOnUDPReceive + #define pOnUdpSent pxOnUDPSent + + #define FOnUdpSent FOnUDPSent_t + #define FOnTcpSent FOnTCPSent_t +#endif /* ipconfigENABLE_BACKWARD_COMPATIBILITY */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* FREERTOS_IP_H */ + + + + + + + + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_IP_Private.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_IP_Private.h new file mode 100644 index 0000000..d6784cf --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_IP_Private.h @@ -0,0 +1,827 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +#ifndef FREERTOS_IP_PRIVATE_H +#define FREERTOS_IP_PRIVATE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Application level configuration options. */ +#include "FreeRTOSIPConfig.h" +#include "FreeRTOSIPConfigDefaults.h" +#include "FreeRTOS_Sockets.h" +#include "IPTraceMacroDefaults.h" +#include "FreeRTOS_Stream_Buffer.h" +#if( ipconfigUSE_TCP == 1 ) + #include "FreeRTOS_TCP_WIN.h" + #include "FreeRTOS_TCP_IP.h" +#endif + +#include "event_groups.h" + +typedef struct xNetworkAddressingParameters +{ + uint32_t ulDefaultIPAddress; + uint32_t ulNetMask; + uint32_t ulGatewayAddress; + uint32_t ulDNSServerAddress; + uint32_t ulBroadcastAddress; +} NetworkAddressingParameters_t; + +extern BaseType_t xTCPWindowLoggingLevel; + +/*-----------------------------------------------------------*/ +/* Protocol headers. */ +/*-----------------------------------------------------------*/ + +#include "pack_struct_start.h" +struct xETH_HEADER +{ + MACAddress_t xDestinationAddress; /* 0 + 6 = 6 */ + MACAddress_t xSourceAddress; /* 6 + 6 = 12 */ + uint16_t usFrameType; /* 12 + 2 = 14 */ +} +#include "pack_struct_end.h" +typedef struct xETH_HEADER EthernetHeader_t; + +#include "pack_struct_start.h" +struct xARP_HEADER +{ + uint16_t usHardwareType; /* 0 + 2 = 2 */ + uint16_t usProtocolType; /* 2 + 2 = 4 */ + uint8_t ucHardwareAddressLength; /* 4 + 1 = 5 */ + uint8_t ucProtocolAddressLength; /* 5 + 1 = 6 */ + uint16_t usOperation; /* 6 + 2 = 8 */ + MACAddress_t xSenderHardwareAddress; /* 8 + 6 = 14 */ + uint8_t ucSenderProtocolAddress[ 4 ]; /* 14 + 4 = 18 */ + MACAddress_t xTargetHardwareAddress; /* 18 + 6 = 24 */ + uint32_t ulTargetProtocolAddress; /* 24 + 4 = 28 */ +} +#include "pack_struct_end.h" +typedef struct xARP_HEADER ARPHeader_t; + +#include "pack_struct_start.h" +struct xIP_HEADER +{ + uint8_t ucVersionHeaderLength; /* 0 + 1 = 1 */ + uint8_t ucDifferentiatedServicesCode; /* 1 + 1 = 2 */ + uint16_t usLength; /* 2 + 2 = 4 */ + uint16_t usIdentification; /* 4 + 2 = 6 */ + uint16_t usFragmentOffset; /* 6 + 2 = 8 */ + uint8_t ucTimeToLive; /* 8 + 1 = 9 */ + uint8_t ucProtocol; /* 9 + 1 = 10 */ + uint16_t usHeaderChecksum; /* 10 + 2 = 12 */ + uint32_t ulSourceIPAddress; /* 12 + 4 = 16 */ + uint32_t ulDestinationIPAddress; /* 16 + 4 = 20 */ +} +#include "pack_struct_end.h" +typedef struct xIP_HEADER IPHeader_t; + +#include "pack_struct_start.h" +struct xIGMP_HEADER +{ + uint8_t ucVersionType; /* 0 + 1 = 1 */ + uint8_t ucMaxResponseTime; /* 1 + 1 = 2 */ + uint16_t usChecksum; /* 2 + 2 = 4 */ + uint32_t usGroupAddress; /* 4 + 4 = 8 */ +} +#include "pack_struct_end.h" +typedef struct xIGMP_HEADER IGMPHeader_t; + +#include "pack_struct_start.h" +struct xICMP_HEADER +{ + uint8_t ucTypeOfMessage; /* 0 + 1 = 1 */ + uint8_t ucTypeOfService; /* 1 + 1 = 2 */ + uint16_t usChecksum; /* 2 + 2 = 4 */ + uint16_t usIdentifier; /* 4 + 2 = 6 */ + uint16_t usSequenceNumber; /* 6 + 2 = 8 */ +} +#include "pack_struct_end.h" +typedef struct xICMP_HEADER ICMPHeader_t; + +#include "pack_struct_start.h" +struct xUDP_HEADER +{ + uint16_t usSourcePort; /* 0 + 2 = 2 */ + uint16_t usDestinationPort; /* 2 + 2 = 4 */ + uint16_t usLength; /* 4 + 2 = 6 */ + uint16_t usChecksum; /* 6 + 2 = 8 */ +} +#include "pack_struct_end.h" +typedef struct xUDP_HEADER UDPHeader_t; + +#include "pack_struct_start.h" +struct xTCP_HEADER +{ + uint16_t usSourcePort; /* + 2 = 2 */ + uint16_t usDestinationPort; /* + 2 = 4 */ + uint32_t ulSequenceNumber; /* + 4 = 8 */ + uint32_t ulAckNr; /* + 4 = 12 */ + uint8_t ucTCPOffset; /* + 1 = 13 */ + uint8_t ucTCPFlags; /* + 1 = 14 */ + uint16_t usWindow; /* + 2 = 15 */ + uint16_t usChecksum; /* + 2 = 18 */ + uint16_t usUrgent; /* + 2 = 20 */ +#if ipconfigUSE_TCP == 1 + /* the option data is not a part of the TCP header */ + uint8_t ucOptdata[ipSIZE_TCP_OPTIONS]; /* + 12 = 32 */ +#endif +} +#include "pack_struct_end.h" +typedef struct xTCP_HEADER TCPHeader_t; + +#include "pack_struct_start.h" +struct xPSEUDO_HEADER +{ + uint32_t ulSourceAddress; + uint32_t ulDestinationAddress; + uint8_t ucZeros; + uint8_t ucProtocol; + uint16_t usUDPLength; +} +#include "pack_struct_end.h" +typedef struct xPSEUDO_HEADER PseudoHeader_t; + +/*-----------------------------------------------------------*/ +/* Nested protocol packets. */ +/*-----------------------------------------------------------*/ + +#include "pack_struct_start.h" +struct xARP_PACKET +{ + EthernetHeader_t xEthernetHeader; /* 0 + 14 = 14 */ + ARPHeader_t xARPHeader; /* 14 + 28 = 42 */ +} +#include "pack_struct_end.h" +typedef struct xARP_PACKET ARPPacket_t; + +#include "pack_struct_start.h" +struct xIP_PACKET +{ + EthernetHeader_t xEthernetHeader; + IPHeader_t xIPHeader; +} +#include "pack_struct_end.h" +typedef struct xIP_PACKET IPPacket_t; + +#include "pack_struct_start.h" +struct xICMP_PACKET +{ + EthernetHeader_t xEthernetHeader; + IPHeader_t xIPHeader; + ICMPHeader_t xICMPHeader; +} +#include "pack_struct_end.h" +typedef struct xICMP_PACKET ICMPPacket_t; + +#include "pack_struct_start.h" +struct xUDP_PACKET +{ + EthernetHeader_t xEthernetHeader; /* 0 + 14 = 14 */ + IPHeader_t xIPHeader; /* 14 + 20 = 34 */ + UDPHeader_t xUDPHeader; /* 34 + 8 = 42 */ +} +#include "pack_struct_end.h" +typedef struct xUDP_PACKET UDPPacket_t; + +#include "pack_struct_start.h" +struct xTCP_PACKET +{ + EthernetHeader_t xEthernetHeader; /* 0 + 14 = 14 */ + IPHeader_t xIPHeader; /* 14 + 20 = 34 */ + TCPHeader_t xTCPHeader; /* 34 + 32 = 66 */ +} +#include "pack_struct_end.h" +typedef struct xTCP_PACKET TCPPacket_t; + +typedef union XPROT_PACKET +{ + ARPPacket_t xARPPacket; + TCPPacket_t xTCPPacket; + UDPPacket_t xUDPPacket; + ICMPPacket_t xICMPPacket; +} ProtocolPacket_t; + + +/* The maximum UDP payload length. */ +#define ipMAX_UDP_PAYLOAD_LENGTH ( ( ipconfigNETWORK_MTU - ipSIZE_OF_IPv4_HEADER ) - ipSIZE_OF_UDP_HEADER ) + +typedef enum +{ + eReleaseBuffer = 0, /* Processing the frame did not find anything to do - just release the buffer. */ + eProcessBuffer, /* An Ethernet frame has a valid address - continue process its contents. */ + eReturnEthernetFrame, /* The Ethernet frame contains an ARP or ICMP packet that can be returned to its source. */ + eFrameConsumed /* Processing the Ethernet packet contents resulted in the payload being sent to the stack. */ +} eFrameProcessingResult_t; + +typedef enum +{ + eNoEvent = -1, + eNetworkDownEvent, /* 0: The network interface has been lost and/or needs [re]connecting. */ + eNetworkRxEvent, /* 1: The network interface has queued a received Ethernet frame. */ + eARPTimerEvent, /* 2: The ARP timer expired. */ + eStackTxEvent, /* 3: The software stack has queued a packet to transmit. */ + eDHCPEvent, /* 4: Process the DHCP state machine. */ + eTCPTimerEvent, /* 5: See if any TCP socket needs attention. */ + eTCPAcceptEvent, /* 6: Client API FreeRTOS_accept() waiting for client connections. */ + eTCPNetStat, /* 7: IP-task is asked to produce a netstat listing. */ + eSocketBindEvent, /* 8: Send a message to the IP-task to bind a socket to a port. */ + eSocketCloseEvent, /* 9: Send a message to the IP-task to close a socket. */ + eSocketSelectEvent, /*10: Send a message to the IP-task for select(). */ + eSocketSignalEvent, /*11: A socket must be signalled. */ +} eIPEvent_t; + +typedef struct IP_TASK_COMMANDS +{ + eIPEvent_t eEventType; + void *pvData; +} IPStackEvent_t; + +#define ipBROADCAST_IP_ADDRESS 0xffffffffUL + +/* Offset into the Ethernet frame that is used to temporarily store information +on the fragmentation status of the packet being sent. The value is important, +as it is past the location into which the destination address will get placed. */ +#define ipFRAGMENTATION_PARAMETERS_OFFSET ( 6 ) +#define ipSOCKET_OPTIONS_OFFSET ( 6 ) + +/* Only used when outgoing fragmentation is being used (FreeRTOSIPConfig.h +setting. */ +#define ipGET_UDP_PAYLOAD_OFFSET_FOR_FRAGMENT( usFragmentOffset ) ( ( ( usFragmentOffset ) == 0 ) ? ipUDP_PAYLOAD_OFFSET_IPv4 : ipIP_PAYLOAD_OFFSET ) + +/* The offset into a UDP packet at which the UDP data (payload) starts. */ +#define ipUDP_PAYLOAD_OFFSET_IPv4 ( sizeof( UDPPacket_t ) ) + +/* The offset into an IP packet into which the IP data (payload) starts. */ +#define ipIP_PAYLOAD_OFFSET ( sizeof( IPPacket_t ) ) + +#include "pack_struct_start.h" +struct xUDP_IP_FRAGMENT_PARAMETERS +{ + uint8_t ucSocketOptions; + uint8_t ucPadFor16BitAlignment; + uint16_t usFragmentedPacketOffset; + uint16_t usFragmentLength; + uint16_t usPayloadChecksum; +} +#include "pack_struct_end.h" +typedef struct xUDP_IP_FRAGMENT_PARAMETERS IPFragmentParameters_t; + +#if( ipconfigBYTE_ORDER == pdFREERTOS_LITTLE_ENDIAN ) + + /* Ethernet frame types. */ + #define ipARP_FRAME_TYPE ( 0x0608U ) + #define ipIPv4_FRAME_TYPE ( 0x0008U ) + + /* ARP related definitions. */ + #define ipARP_PROTOCOL_TYPE ( 0x0008U ) + #define ipARP_HARDWARE_TYPE_ETHERNET ( 0x0100U ) + #define ipARP_REQUEST ( 0x0100U ) + #define ipARP_REPLY ( 0x0200U ) + +#else + + /* Ethernet frame types. */ + #define ipARP_FRAME_TYPE ( 0x0806U ) + #define ipIPv4_FRAME_TYPE ( 0x0800U ) + + /* ARP related definitions. */ + #define ipARP_PROTOCOL_TYPE ( 0x0800U ) + #define ipARP_HARDWARE_TYPE_ETHERNET ( 0x0001U ) + #define ipARP_REQUEST ( 0x0001 ) + #define ipARP_REPLY ( 0x0002 ) + +#endif /* ipconfigBYTE_ORDER == pdFREERTOS_LITTLE_ENDIAN */ + + +/* For convenience, a MAC address of all zeros and another of all 0xffs are +defined const for quick reference. */ +extern const MACAddress_t xBroadcastMACAddress; /* all 0xff's */ +extern uint16_t usPacketIdentifier; + +/* Define a default UDP packet header (declared in FreeRTOS_UDP_IP.c) */ +typedef union xUDPPacketHeader +{ + uint8_t ucBytes[24]; + uint32_t ulWords[6]; +} UDPPacketHeader_t; +extern UDPPacketHeader_t xDefaultPartUDPPacketHeader; + +/* Structure that stores the netmask, gateway address and DNS server addresses. */ +extern NetworkAddressingParameters_t xNetworkAddressing; + +/* Structure that stores the defaults for netmask, gateway address and DNS. +These values will be copied to 'xNetworkAddressing' in case DHCP is not used, +and also in case DHCP does not lead to a confirmed request. */ +extern NetworkAddressingParameters_t xDefaultAddressing; + +/* True when BufferAllocation_1.c was included, false for BufferAllocation_2.c */ +extern const BaseType_t xBufferAllocFixedSize; + +/* Defined in FreeRTOS_Sockets.c */ +#if ( ipconfigUSE_TCP == 1 ) + extern List_t xBoundTCPSocketsList; +#endif + +/* The local IP address is accessed from within xDefaultPartUDPPacketHeader, +rather than duplicated in its own variable. */ +#define ipLOCAL_IP_ADDRESS_POINTER ( ( uint32_t * ) &( xDefaultPartUDPPacketHeader.ulWords[ 20u / sizeof(uint32_t) ] ) ) + +/* The local MAC address is accessed from within xDefaultPartUDPPacketHeader, +rather than duplicated in its own variable. */ +#define ipLOCAL_MAC_ADDRESS ( &xDefaultPartUDPPacketHeader.ucBytes[0] ) + +/* ICMP packets are sent using the same function as UDP packets. The port +number is used to distinguish between the two, as 0 is an invalid UDP port. */ +#define ipPACKET_CONTAINS_ICMP_DATA ( 0 ) + +/* For now, the lower 8 bits in 'xEventBits' will be reserved for the above +socket events. */ +#define SOCKET_EVENT_BIT_COUNT 8 + +#define vSetField16( pxBase, xType, xField, usValue ) \ +{ \ + ( ( uint8_t* )( pxBase ) ) [ offsetof( xType, xField ) + 0 ] = ( uint8_t ) ( ( usValue ) >> 8 ); \ + ( ( uint8_t* )( pxBase ) ) [ offsetof( xType, xField ) + 1 ] = ( uint8_t ) ( ( usValue ) & 0xff ); \ +} + +#define vSetField32( pxBase, xType, xField, ulValue ) \ +{ \ + ( (uint8_t*)( pxBase ) ) [ offsetof( xType, xField ) + 0 ] = ( uint8_t ) ( ( ulValue ) >> 24 ); \ + ( (uint8_t*)( pxBase ) ) [ offsetof( xType, xField ) + 1 ] = ( uint8_t ) ( ( ( ulValue ) >> 16 ) & 0xff ); \ + ( (uint8_t*)( pxBase ) ) [ offsetof( xType, xField ) + 2 ] = ( uint8_t ) ( ( ( ulValue ) >> 8 ) & 0xff ); \ + ( (uint8_t*)( pxBase ) ) [ offsetof( xType, xField ) + 3 ] = ( uint8_t ) ( ( ulValue ) & 0xff ); \ +} + +#define vFlip_16( left, right ) \ + do { \ + uint16_t tmp = (left); \ + (left) = (right); \ + (right) = tmp; \ + } while (0) + +#define vFlip_32( left, right ) \ + do { \ + uint32_t tmp = (left); \ + (left) = (right); \ + (right) = tmp; \ + } while (0) + +#ifndef ARRAY_SIZE + #define ARRAY_SIZE(x) (BaseType_t)(sizeof(x)/sizeof(x)[0]) +#endif + +/* + * A version of FreeRTOS_GetReleaseNetworkBuffer() that can be called from an + * interrupt. If a non zero value is returned, then the calling ISR should + * perform a context switch before exiting the ISR. + */ +BaseType_t FreeRTOS_ReleaseFreeNetworkBufferFromISR( void ); + +/* + * Create a message that contains a command to initialise the network interface. + * This is used during initialisation, and at any time the network interface + * goes down thereafter. The network interface hardware driver is responsible + * for sending the message that contains the network interface down command/ + * event. + * + * Only use the FreeRTOS_NetworkDownFromISR() version if the function is to be + * called from an interrupt service routine. If FreeRTOS_NetworkDownFromISR() + * returns a non-zero value then a context switch should be performed ebfore + * the interrupt is exited. + */ +void FreeRTOS_NetworkDown( void ); +BaseType_t FreeRTOS_NetworkDownFromISR( void ); + +/* + * Processes incoming ARP packets. + */ +eFrameProcessingResult_t eARPProcessPacket( ARPPacket_t * const pxARPFrame ); + +/* + * Inspect an Ethernet frame to see if it contains data that the stack needs to + * process. eProcessBuffer is returned if the frame should be processed by the + * stack. eReleaseBuffer is returned if the frame should be discarded. + */ +eFrameProcessingResult_t eConsiderFrameForProcessing( const uint8_t * const pucEthernetBuffer ); + +/* + * Return the checksum generated over xDataLengthBytes from pucNextData. + */ +uint16_t usGenerateChecksum( uint32_t ulSum, const uint8_t * pucNextData, size_t uxDataLengthBytes ); + +/* Socket related private functions. */ + +/* + * The caller must ensure that pxNetworkBuffer->xDataLength is the UDP packet + * payload size (excluding packet headers) and that the packet in pucEthernetBuffer + * is at least the size of UDPPacket_t. + */ +BaseType_t xProcessReceivedUDPPacket( NetworkBufferDescriptor_t *pxNetworkBuffer, uint16_t usPort ); + +/* + * Initialize the socket list data structures for TCP and UDP. + */ +BaseType_t vNetworkSocketsInit( void ); + +/* + * Returns pdTRUE if the IP task has been created and is initialised. Otherwise + * returns pdFALSE. + */ +BaseType_t xIPIsNetworkTaskReady( void ); + +#if( ipconfigSOCKET_HAS_USER_WAKE_CALLBACK == 1 ) + struct XSOCKET; + typedef void (*SocketWakeupCallback_t)( struct XSOCKET * pxSocket ); +#endif + +#if( ipconfigUSE_TCP == 1 ) + + /* + * Actually a user thing, but because xBoundTCPSocketsList, let it do by the + * IP-task + */ + void vTCPNetStat( void ); + + /* + * At least one socket needs to check for timeouts + */ + TickType_t xTCPTimerCheck( BaseType_t xWillSleep ); + + /* Every TCP socket has a buffer space just big enough to store + the last TCP header received. + As a reference of this field may be passed to DMA, force the + alignment to 8 bytes. */ + typedef union + { + struct + { + /* Increase the alignment of this union by adding a 64-bit variable. */ + uint64_t ullAlignmentWord; + } a; + struct + { + /* The next field only serves to give 'ucLastPacket' a correct + alignment of 8 + 2. See comments in FreeRTOS_IP.h */ + uint8_t ucFillPacket[ ipconfigPACKET_FILLER_SIZE ]; + uint8_t ucLastPacket[ sizeof( TCPPacket_t ) ]; + } u; + } LastTCPPacket_t; + + /* + * Note that the values of all short and long integers in these structs + * are being stored in the native-endian way + * Translation should take place when accessing any structure which defines + * network packets, such as IPHeader_t and TCPHeader_t + */ + typedef struct TCPSOCKET + { + uint32_t ulRemoteIP; /* IP address of remote machine */ + uint16_t usRemotePort; /* Port on remote machine */ + struct { + /* Most compilers do like bit-flags */ + uint32_t + bMssChange : 1, /* This socket has seen a change in MSS */ + bPassAccept : 1, /* when true, this socket may be returned in a call to accept() */ + bPassQueued : 1, /* when true, this socket is an orphan until it gets connected + * Why an orphan? Because it may not be returned in a accept() call until it + * gets the state eESTABLISHED */ + bReuseSocket : 1, /* When a listening socket gets a connection, do not create a new instance but keep on using it */ + bCloseAfterSend : 1,/* As soon as the last byte has been transmitted, finalise the connection + * Useful in e.g. FTP connections, where the last data bytes are sent along with the FIN flag */ + bUserShutdown : 1, /* User requesting a graceful shutdown */ + bCloseRequested : 1,/* Request to finalise the connection */ + bLowWater : 1, /* high-water level has been reached. Cleared as soon as 'rx-count < lo-water' */ + bWinChange : 1, /* The value of bLowWater has changed, must send a window update */ + bSendKeepAlive : 1, /* When this flag is true, a TCP keep-alive message must be send */ + bWaitKeepAlive : 1, /* When this flag is true, a TCP keep-alive reply is expected */ + bConnPrepared : 1, /* Connecting socket: Message has been prepared */ + #if( ipconfigSUPPORT_SELECT_FUNCTION == 1 ) + bConnPassed : 1, /* Connecting socket: Socket has been passed in a successful select() */ + #endif /* ipconfigSUPPORT_SELECT_FUNCTION */ + bFinAccepted : 1, /* This socket has received (or sent) a FIN and accepted it */ + bFinSent : 1, /* We've sent out a FIN */ + bFinRecv : 1, /* We've received a FIN from our peer */ + bFinAcked : 1, /* Our FIN packet has been acked */ + bFinLast : 1, /* The last ACK (after FIN and FIN+ACK) has been sent or will be sent by the peer */ + bRxStopped : 1, /* Application asked to temporarily stop reception */ + bMallocError : 1, /* There was an error allocating a stream */ + bWinScaling : 1; /* A TCP-Window Scaling option was offered and accepted in the SYN phase. */ + } bits; + uint32_t ulHighestRxAllowed; + /* The highest sequence number that we can receive at any moment */ + uint16_t usTimeout; /* Time (in ticks) after which this socket needs attention */ + uint16_t usCurMSS; /* Current Maximum Segment Size */ + uint16_t usInitMSS; /* Initial maximum segment Size */ + uint16_t usChildCount; /* In case of a listening socket: number of connections on this port number */ + uint16_t usBacklog; /* In case of a listening socket: maximum number of concurrent connections on this port number */ + uint8_t ucRepCount; /* Send repeat count, for retransmissions + * This counter is separate from the xmitCount in the + * TCP win segments */ + uint8_t ucTCPState; /* TCP state: see eTCP_STATE */ + struct XSOCKET *pxPeerSocket; /* for server socket: child, for child socket: parent */ + #if( ipconfigTCP_KEEP_ALIVE == 1 ) + uint8_t ucKeepRepCount; + TickType_t xLastAliveTime; + #endif /* ipconfigTCP_KEEP_ALIVE */ + #if( ipconfigTCP_HANG_PROTECTION == 1 ) + TickType_t xLastActTime; + #endif /* ipconfigTCP_HANG_PROTECTION */ + size_t uxLittleSpace; + size_t uxEnoughSpace; + size_t uxRxStreamSize; + size_t uxTxStreamSize; + StreamBuffer_t *rxStream; + StreamBuffer_t *txStream; + #if( ipconfigUSE_TCP_WIN == 1 ) + NetworkBufferDescriptor_t *pxAckMessage; + #endif /* ipconfigUSE_TCP_WIN */ + /* Buffer space to store the last TCP header received. */ + LastTCPPacket_t xPacket; + uint8_t tcpflags; /* TCP flags */ + #if( ipconfigUSE_TCP_WIN != 0 ) + uint8_t ucMyWinScaleFactor; + uint8_t ucPeerWinScaleFactor; + #endif + #if( ipconfigUSE_CALLBACKS == 1 ) + FOnTCPReceive_t pxHandleReceive; /* + * In case of a TCP socket: + * typedef void (* FOnTCPReceive_t) (Socket_t xSocket, void *pData, size_t xLength ); + */ + FOnTCPSent_t pxHandleSent; + FOnConnected_t pxHandleConnected; /* Actually type: typedef void (* FOnConnected_t) (Socket_t xSocket, BaseType_t ulConnected ); */ + #endif /* ipconfigUSE_CALLBACKS */ + uint32_t ulWindowSize; /* Current Window size advertised by peer */ + uint32_t ulRxCurWinSize; /* Constantly changing: this is the current size available for data reception */ + size_t uxRxWinSize; /* Fixed value: size of the TCP reception window */ + size_t uxTxWinSize; /* Fixed value: size of the TCP transmit window */ + + TCPWindow_t xTCPWindow; + } IPTCPSocket_t; + +#endif /* ipconfigUSE_TCP */ + +typedef struct UDPSOCKET +{ + List_t xWaitingPacketsList; /* Incoming packets */ + #if( ipconfigUDP_MAX_RX_PACKETS > 0 ) + UBaseType_t uxMaxPackets; /* Protection: limits the number of packets buffered per socket */ + #endif /* ipconfigUDP_MAX_RX_PACKETS */ + #if( ipconfigUSE_CALLBACKS == 1 ) + FOnUDPReceive_t pxHandleReceive; /* + * In case of a UDP socket: + * typedef void (* FOnUDPReceive_t) (Socket_t xSocket, void *pData, size_t xLength, struct freertos_sockaddr *pxAddr ); + */ + FOnUDPSent_t pxHandleSent; + #endif /* ipconfigUSE_CALLBACKS */ +} IPUDPSocket_t; + +typedef enum eSOCKET_EVENT { + eSOCKET_RECEIVE = 0x0001, + eSOCKET_SEND = 0x0002, + eSOCKET_ACCEPT = 0x0004, + eSOCKET_CONNECT = 0x0008, + eSOCKET_BOUND = 0x0010, + eSOCKET_CLOSED = 0x0020, + eSOCKET_INTR = 0x0040, + eSOCKET_ALL = 0x007F, +} eSocketEvent_t; + +typedef struct XSOCKET +{ + EventBits_t xEventBits; + EventGroupHandle_t xEventGroup; + + ListItem_t xBoundSocketListItem; /* Used to reference the socket from a bound sockets list. */ + TickType_t xReceiveBlockTime; /* if recv[to] is called while no data is available, wait this amount of time. Unit in clock-ticks */ + TickType_t xSendBlockTime; /* if send[to] is called while there is not enough space to send, wait this amount of time. Unit in clock-ticks */ + + uint16_t usLocalPort; /* Local port on this machine */ + uint8_t ucSocketOptions; + uint8_t ucProtocol; /* choice of FREERTOS_IPPROTO_UDP/TCP */ + #if( ipconfigSOCKET_HAS_USER_SEMAPHORE == 1 ) + SemaphoreHandle_t pxUserSemaphore; + #endif /* ipconfigSOCKET_HAS_USER_SEMAPHORE */ + #if( ipconfigSOCKET_HAS_USER_WAKE_CALLBACK == 1 ) + SocketWakeupCallback_t pxUserWakeCallback; + #endif /* ipconfigSOCKET_HAS_USER_WAKE_CALLBACK */ + + #if( ipconfigSUPPORT_SELECT_FUNCTION == 1 ) + struct xSOCKET_SET *pxSocketSet; + /* User may indicate which bits are interesting for this socket. */ + EventBits_t xSelectBits; + /* These bits indicate the events which have actually occurred. + They are maintained by the IP-task */ + EventBits_t xSocketBits; + #endif /* ipconfigSUPPORT_SELECT_FUNCTION */ + /* TCP/UDP specific fields: */ + /* Before accessing any member of this structure, it should be confirmed */ + /* that the protocol corresponds with the type of structure */ + + union + { + IPUDPSocket_t xUDP; + #if( ipconfigUSE_TCP == 1 ) + IPTCPSocket_t xTCP; + /* Make sure that xTCP is 8-bytes aligned by + declaring a 64-bit variable in the same union */ + uint64_t ullTCPAlignment; + #endif /* ipconfigUSE_TCP */ + } u; +} FreeRTOS_Socket_t; + +#if( ipconfigUSE_TCP == 1 ) + /* + * Lookup a TCP socket, using a multiple matching: both port numbers and + * return IP address. + */ + FreeRTOS_Socket_t *pxTCPSocketLookup( uint32_t ulLocalIP, UBaseType_t uxLocalPort, uint32_t ulRemoteIP, UBaseType_t uxRemotePort ); + +#endif /* ipconfigUSE_TCP */ + +/* + * Look up a local socket by finding a match with the local port. + */ +FreeRTOS_Socket_t *pxUDPSocketLookup( UBaseType_t uxLocalPort ); + +/* + * Called when the application has generated a UDP packet to send. + */ +void vProcessGeneratedUDPPacket( NetworkBufferDescriptor_t * const pxNetworkBuffer ); + +/* + * Calculate the upper-layer checksum + * Works both for UDP, ICMP and TCP packages + * bOut = true: checksum will be set in outgoing packets + * bOut = false: checksum will be calculated for incoming packets + * returning 0xffff means: checksum was correct + */ +uint16_t usGenerateProtocolChecksum( const uint8_t * const pucEthernetBuffer, size_t uxBufferLength, BaseType_t xOutgoingPacket ); + +/* + * An Ethernet frame has been updated (maybe it was an ARP request or a PING + * request?) and is to be sent back to its source. + */ +void vReturnEthernetFrame( NetworkBufferDescriptor_t * pxNetworkBuffer, BaseType_t xReleaseAfterSend ); + +/* + * The internal version of bind() + * If 'ulInternal' is true, it is called by the driver + * The TCP driver needs to bind a socket at the moment a listening socket + * creates a new connected socket + */ +BaseType_t vSocketBind( FreeRTOS_Socket_t *pxSocket, struct freertos_sockaddr * pxAddress, size_t uxAddressLength, BaseType_t xInternal ); + +/* + * Internal function to add streaming data to a TCP socket. If ulIn == true, + * data will be added to the rxStream, otherwise to the tXStream. Normally data + * will be written with ulOffset == 0, meaning: at the end of the FIFO. When + * packet come in out-of-order, an offset will be used to put it in front and + * the head will not change yet. + */ +int32_t lTCPAddRxdata(FreeRTOS_Socket_t *pxSocket, size_t uxOffset, const uint8_t *pcData, uint32_t ulByteCount); + +/* + * Currently called for any important event. + */ +void vSocketWakeUpUser( FreeRTOS_Socket_t *pxSocket ); + +/* + * Some helping function, their meaning should be clear + */ +static portINLINE uint32_t ulChar2u32 (const uint8_t *apChr); +static portINLINE uint32_t ulChar2u32 (const uint8_t *apChr) +{ + return ( ( ( uint32_t )apChr[0] ) << 24) | + ( ( ( uint32_t )apChr[1] ) << 16) | + ( ( ( uint32_t )apChr[2] ) << 8) | + ( ( ( uint32_t )apChr[3] ) ); +} + +static portINLINE uint16_t usChar2u16 (const uint8_t *apChr); +static portINLINE uint16_t usChar2u16 (const uint8_t *apChr) +{ + return ( uint16_t ) + ( ( ( ( uint32_t )apChr[0] ) << 8) | + ( ( ( uint32_t )apChr[1] ) ) ); +} + +/* Check a single socket for retransmissions and timeouts */ +BaseType_t xTCPSocketCheck( FreeRTOS_Socket_t *pxSocket ); + +BaseType_t xTCPCheckNewClient( FreeRTOS_Socket_t *pxSocket ); + +/* Defined in FreeRTOS_Sockets.c + * Close a socket + */ +void *vSocketClose( FreeRTOS_Socket_t *pxSocket ); + +/* + * Send the event eEvent to the IP task event queue, using a block time of + * zero. Return pdPASS if the message was sent successfully, otherwise return + * pdFALSE. +*/ +BaseType_t xSendEventToIPTask( eIPEvent_t eEvent ); + +/* + * The same as above, but a struct as a parameter, containing: + * eIPEvent_t eEventType; + * void *pvData; + */ +BaseType_t xSendEventStructToIPTask( const IPStackEvent_t *pxEvent, TickType_t xTimeout ); + +/* + * Returns a pointer to the original NetworkBuffer from a pointer to a UDP + * payload buffer. + */ +NetworkBufferDescriptor_t *pxUDPPayloadBuffer_to_NetworkBuffer( void *pvBuffer ); + +#if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + /* + * For the case where the network driver passes a buffer directly to a DMA + * descriptor, this function can be used to translate a 'network buffer' to + * a 'network buffer descriptor'. + */ + NetworkBufferDescriptor_t *pxPacketBuffer_to_NetworkBuffer( const void *pvBuffer ); +#endif + +/* + * Internal: Sets a new state for a TCP socket and performs the necessary + * actions like calling a OnConnected handler to notify the socket owner. + */ +#if( ipconfigUSE_TCP == 1 ) + void vTCPStateChange( FreeRTOS_Socket_t *pxSocket, enum eTCP_STATE eTCPState ); +#endif /* ipconfigUSE_TCP */ + +/*_RB_ Should this be part of the public API? */ +void FreeRTOS_netstat( void ); + +/* Returns pdTRUE is this function is called from the IP-task */ +BaseType_t xIsCallingFromIPTask( void ); + +#if( ipconfigSUPPORT_SELECT_FUNCTION == 1 ) + +typedef struct xSOCKET_SET +{ + EventGroupHandle_t xSelectGroup; + BaseType_t bApiCalled; /* True if the API was calling the private vSocketSelect */ + FreeRTOS_Socket_t *pxSocket; +} SocketSelect_t; + +extern void vSocketSelect( SocketSelect_t *pxSocketSelect ); + +#endif /* ipconfigSUPPORT_SELECT_FUNCTION */ + +void vIPSetDHCPTimerEnableState( BaseType_t xEnableState ); +void vIPReloadDHCPTimer( uint32_t ulLeaseTime ); +#if( ipconfigDNS_USE_CALLBACKS != 0 ) + void vIPReloadDNSTimer( uint32_t ulCheckTime ); + void vIPSetDnsTimerEnableState( BaseType_t xEnableState ); +#endif + +/* Send the network-up event and start the ARP timer. */ +void vIPNetworkUpCalls( void ); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* FREERTOS_IP_PRIVATE_H */ + + + + + + + + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_Sockets.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_Sockets.h new file mode 100644 index 0000000..630e681 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_Sockets.h @@ -0,0 +1,393 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +#ifndef FREERTOS_SOCKETS_H +#define FREERTOS_SOCKETS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Standard includes. */ +#include + +/* Application level configuration options. */ +#include "FreeRTOSIPConfig.h" + +#ifndef FREERTOS_IP_CONFIG_H + #error FreeRTOSIPConfig.h has not been included yet +#endif + +/* Event bit definitions are required by the select functions. */ +#include "event_groups.h" + +#ifndef INC_FREERTOS_H + #error FreeRTOS.h must be included before FreeRTOS_Sockets.h. +#endif + +#ifndef INC_TASK_H + #ifndef TASK_H /* For compatibility with older FreeRTOS versions. */ + #error The FreeRTOS header file task.h must be included before FreeRTOS_Sockets.h. + #endif +#endif + +/* Assigned to an Socket_t variable when the socket is not valid, probably +because it could not be created. */ +#define FREERTOS_INVALID_SOCKET ( ( void * ) ~0U ) + +/* API function error values. As errno is supported, the FreeRTOS sockets +functions return error codes rather than just a pass or fail indication. */ +/* HT: Extended the number of error codes, gave them positive values and if possible +the corresponding found in errno.h +In case of an error, API's will still return negative numbers, e.g. + return -pdFREERTOS_ERRNO_EWOULDBLOCK; +in case an operation would block */ + +/* The following defines are obsolete, please use -pdFREERTOS_ERRNO_Exxx */ + +#define FREERTOS_SOCKET_ERROR ( -1 ) +#define FREERTOS_EWOULDBLOCK ( - pdFREERTOS_ERRNO_EWOULDBLOCK ) +#define FREERTOS_EINVAL ( - pdFREERTOS_ERRNO_EINVAL ) +#define FREERTOS_EADDRNOTAVAIL ( - pdFREERTOS_ERRNO_EADDRNOTAVAIL ) +#define FREERTOS_EADDRINUSE ( - pdFREERTOS_ERRNO_EADDRINUSE ) +#define FREERTOS_ENOBUFS ( - pdFREERTOS_ERRNO_ENOBUFS ) +#define FREERTOS_ENOPROTOOPT ( - pdFREERTOS_ERRNO_ENOPROTOOPT ) +#define FREERTOS_ECLOSED ( - pdFREERTOS_ERRNO_ENOTCONN ) + +/* Values for the parameters to FreeRTOS_socket(), inline with the Berkeley +standard. See the documentation of FreeRTOS_socket() for more information. */ +#define FREERTOS_AF_INET ( 2 ) +#define FREERTOS_AF_INET6 ( 10 ) +#define FREERTOS_SOCK_DGRAM ( 2 ) +#define FREERTOS_IPPROTO_UDP ( 17 ) + +#define FREERTOS_SOCK_STREAM ( 1 ) +#define FREERTOS_IPPROTO_TCP ( 6 ) +/* IP packet of type "Any local network" + * can be used in stead of TCP for testing with sockets in raw mode + */ +#define FREERTOS_IPPROTO_USR_LAN ( 63 ) + +/* A bit value that can be passed into the FreeRTOS_sendto() function as part of +the flags parameter. Setting the FREERTOS_ZERO_COPY in the flags parameter +indicates that the zero copy interface is being used. See the documentation for +FreeRTOS_sockets() for more information. */ +#define FREERTOS_ZERO_COPY ( 1 ) + +/* Values that can be passed in the option name parameter of calls to +FreeRTOS_setsockopt(). */ +#define FREERTOS_SO_RCVTIMEO ( 0 ) /* Used to set the receive time out. */ +#define FREERTOS_SO_SNDTIMEO ( 1 ) /* Used to set the send time out. */ +#define FREERTOS_SO_UDPCKSUM_OUT ( 2 ) /* Used to turn the use of the UDP checksum by a socket on or off. This also doubles as part of an 8-bit bitwise socket option. */ +#if( ipconfigSOCKET_HAS_USER_SEMAPHORE == 1 ) + #define FREERTOS_SO_SET_SEMAPHORE ( 3 ) /* Used to set a user's semaphore */ +#endif +#define FREERTOS_SO_SNDBUF ( 4 ) /* Set the size of the send buffer (TCP only) */ +#define FREERTOS_SO_RCVBUF ( 5 ) /* Set the size of the receive buffer (TCP only) */ + +#if ipconfigUSE_CALLBACKS == 1 + #define FREERTOS_SO_TCP_CONN_HANDLER ( 6 ) /* Install a callback for (dis) connection events. Supply pointer to 'F_TCP_UDP_Handler_t' (see below) */ + #define FREERTOS_SO_TCP_RECV_HANDLER ( 7 ) /* Install a callback for receiving TCP data. Supply pointer to 'F_TCP_UDP_Handler_t' (see below) */ + #define FREERTOS_SO_TCP_SENT_HANDLER ( 8 ) /* Install a callback for sending TCP data. Supply pointer to 'F_TCP_UDP_Handler_t' (see below) */ + #define FREERTOS_SO_UDP_RECV_HANDLER ( 9 ) /* Install a callback for receiving UDP data. Supply pointer to 'F_TCP_UDP_Handler_t' (see below) */ + #define FREERTOS_SO_UDP_SENT_HANDLER ( 10 ) /* Install a callback for sending UDP data. Supply pointer to 'F_TCP_UDP_Handler_t' (see below) */ +#endif /* ipconfigUSE_CALLBACKS */ + +#define FREERTOS_SO_REUSE_LISTEN_SOCKET ( 11 ) /* When a listening socket gets connected, do not create a new one but re-use it */ +#define FREERTOS_SO_CLOSE_AFTER_SEND ( 12 ) /* As soon as the last byte has been transmitted, finalise the connection */ +#define FREERTOS_SO_WIN_PROPERTIES ( 13 ) /* Set all buffer and window properties in one call, parameter is pointer to WinProperties_t */ +#define FREERTOS_SO_SET_FULL_SIZE ( 14 ) /* Refuse to send packets smaller than MSS */ + +#define FREERTOS_SO_STOP_RX ( 15 ) /* Temporarily hold up reception, used by streaming client */ + +#if( ipconfigUDP_MAX_RX_PACKETS > 0 ) + #define FREERTOS_SO_UDP_MAX_RX_PACKETS ( 16 ) /* This option helps to limit the maximum number of packets a UDP socket will buffer */ +#endif + +#if( ipconfigSOCKET_HAS_USER_WAKE_CALLBACK == 1 ) + #define FREERTOS_SO_WAKEUP_CALLBACK ( 17 ) +#endif + + +#define FREERTOS_NOT_LAST_IN_FRAGMENTED_PACKET ( 0x80 ) /* For internal use only, but also part of an 8-bit bitwise value. */ +#define FREERTOS_FRAGMENTED_PACKET ( 0x40 ) /* For internal use only, but also part of an 8-bit bitwise value. */ + +/* Values for flag for FreeRTOS_shutdown(). */ +#define FREERTOS_SHUT_RD ( 0 ) /* Not really at this moment, just for compatibility of the interface */ +#define FREERTOS_SHUT_WR ( 1 ) +#define FREERTOS_SHUT_RDWR ( 2 ) + +/* Values for flag for FreeRTOS_recv(). */ +#define FREERTOS_MSG_OOB ( 2 ) /* process out-of-band data */ +#define FREERTOS_MSG_PEEK ( 4 ) /* peek at incoming message */ +#define FREERTOS_MSG_DONTROUTE ( 8 ) /* send without using routing tables */ +#define FREERTOS_MSG_DONTWAIT ( 16 ) /* Can be used with recvfrom(), sendto(), recv(), and send(). */ + +typedef struct xWIN_PROPS { + /* Properties of the Tx buffer and Tx window */ + int32_t lTxBufSize; /* Unit: bytes */ + int32_t lTxWinSize; /* Unit: MSS */ + + /* Properties of the Rx buffer and Rx window */ + int32_t lRxBufSize; /* Unit: bytes */ + int32_t lRxWinSize; /* Unit: MSS */ +} WinProperties_t; + +/* For compatibility with the expected Berkeley sockets naming. */ +#define socklen_t uint32_t + +/* For this limited implementation, only two members are required in the +Berkeley style sockaddr structure. */ +struct freertos_sockaddr +{ + /* _HT_ On 32- and 64-bit architectures, the addition of the two uint8_t + fields doesn't make the structure bigger, due to alignment. + The fields are inserted as a preparation for IPv6. */ + + /* sin_len and sin_family not used in the IPv4-only release. */ + uint8_t sin_len; /* length of this structure. */ + uint8_t sin_family; /* FREERTOS_AF_INET. */ + uint16_t sin_port; + uint32_t sin_addr; +}; + +#if ipconfigBYTE_ORDER == pdFREERTOS_LITTLE_ENDIAN + + #define FreeRTOS_inet_addr_quick( ucOctet0, ucOctet1, ucOctet2, ucOctet3 ) \ + ( ( ( ( uint32_t ) ( ucOctet3 ) ) << 24UL ) | \ + ( ( ( uint32_t ) ( ucOctet2 ) ) << 16UL ) | \ + ( ( ( uint32_t ) ( ucOctet1 ) ) << 8UL ) | \ + ( ( uint32_t ) ( ucOctet0 ) ) ) + + #define FreeRTOS_inet_ntoa( ulIPAddress, pucBuffer ) \ + sprintf( ( char * ) ( pucBuffer ), "%u.%u.%u.%u", \ + ( ( unsigned ) ( ( ulIPAddress ) & 0xffUL ) ), \ + ( ( unsigned ) ( ( ( ulIPAddress ) >> 8 ) & 0xffUL ) ), \ + ( ( unsigned ) ( ( ( ulIPAddress ) >> 16 ) & 0xffUL ) ),\ + ( ( unsigned ) ( ( ulIPAddress ) >> 24 ) ) ) + +#else /* ipconfigBYTE_ORDER */ + + #define FreeRTOS_inet_addr_quick( ucOctet0, ucOctet1, ucOctet2, ucOctet3 ) \ + ( ( ( ( uint32_t ) ( ucOctet0 ) ) << 24UL ) | \ + ( ( ( uint32_t ) ( ucOctet1 ) ) << 16UL ) | \ + ( ( ( uint32_t ) ( ucOctet2 ) ) << 8UL ) | \ + ( ( uint32_t ) ( ucOctet3 ) ) ) + + #define FreeRTOS_inet_ntoa( ulIPAddress, pucBuffer ) \ + sprintf( ( char * ) ( pucBuffer ), "%u.%u.%u.%u", \ + ( ( unsigned ) ( ( ulIPAddress ) >> 24 ) ), \ + ( ( unsigned ) ( ( ( ulIPAddress ) >> 16 ) & 0xffUL ) ),\ + ( ( unsigned ) ( ( ( ulIPAddress ) >> 8 ) & 0xffUL ) ), \ + ( ( unsigned ) ( ( ulIPAddress ) & 0xffUL ) ) ) + +#endif /* ipconfigBYTE_ORDER */ + +/* The socket type itself. */ +typedef void *Socket_t; + +/* The SocketSet_t type is the equivalent to the fd_set type used by the +Berkeley API. */ +typedef void *SocketSet_t; + +/** + * FULL, UP-TO-DATE AND MAINTAINED REFERENCE DOCUMENTATION FOR ALL THESE + * FUNCTIONS IS AVAILABLE ON THE FOLLOWING URL: + * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/FreeRTOS_TCP_API_Functions.html + */ +Socket_t FreeRTOS_socket( BaseType_t xDomain, BaseType_t xType, BaseType_t xProtocol ); +int32_t FreeRTOS_recvfrom( Socket_t xSocket, void *pvBuffer, size_t xBufferLength, BaseType_t xFlags, struct freertos_sockaddr *pxSourceAddress, socklen_t *pxSourceAddressLength ); +int32_t FreeRTOS_sendto( Socket_t xSocket, const void *pvBuffer, size_t xTotalDataLength, BaseType_t xFlags, const struct freertos_sockaddr *pxDestinationAddress, socklen_t xDestinationAddressLength ); +BaseType_t FreeRTOS_bind( Socket_t xSocket, struct freertos_sockaddr *pxAddress, socklen_t xAddressLength ); + +/* function to get the local address and IP port */ +size_t FreeRTOS_GetLocalAddress( Socket_t xSocket, struct freertos_sockaddr *pxAddress ); + +/* Made available when ipconfigETHERNET_DRIVER_FILTERS_PACKETS is set to 1. */ +BaseType_t xPortHasUDPSocket( uint16_t usPortNr ); + +#if ipconfigUSE_TCP == 1 + +BaseType_t FreeRTOS_connect( Socket_t xClientSocket, struct freertos_sockaddr *pxAddress, socklen_t xAddressLength ); +BaseType_t FreeRTOS_listen( Socket_t xSocket, BaseType_t xBacklog ); +BaseType_t FreeRTOS_recv( Socket_t xSocket, void *pvBuffer, size_t xBufferLength, BaseType_t xFlags ); +BaseType_t FreeRTOS_send( Socket_t xSocket, const void *pvBuffer, size_t uxDataLength, BaseType_t xFlags ); +Socket_t FreeRTOS_accept( Socket_t xServerSocket, struct freertos_sockaddr *pxAddress, socklen_t *pxAddressLength ); +BaseType_t FreeRTOS_shutdown (Socket_t xSocket, BaseType_t xHow); + +#if( ipconfigSUPPORT_SIGNALS != 0 ) + /* Send a signal to the task which is waiting for a given socket. */ + BaseType_t FreeRTOS_SignalSocket( Socket_t xSocket ); + + /* Send a signal to the task which reads from this socket (FromISR + version). */ + BaseType_t FreeRTOS_SignalSocketFromISR( Socket_t xSocket, BaseType_t *pxHigherPriorityTaskWoken ); +#endif /* ipconfigSUPPORT_SIGNALS */ + +/* Return the remote address and IP port. */ +BaseType_t FreeRTOS_GetRemoteAddress( Socket_t xSocket, struct freertos_sockaddr *pxAddress ); + +/* returns pdTRUE if TCP socket is connected */ +BaseType_t FreeRTOS_issocketconnected( Socket_t xSocket ); + +/* returns the actual size of MSS being used */ +BaseType_t FreeRTOS_mss( Socket_t xSocket ); + +/* for internal use only: return the connection status */ +BaseType_t FreeRTOS_connstatus( Socket_t xSocket ); + +/* Returns the number of bytes that may be added to txStream */ +BaseType_t FreeRTOS_maywrite( Socket_t xSocket ); + +/* + * Two helper functions, mostly for testing + * rx_size returns the number of bytes available in the Rx buffer + * tx_space returns the free space in the Tx buffer + */ +BaseType_t FreeRTOS_rx_size( Socket_t xSocket ); +BaseType_t FreeRTOS_tx_space( Socket_t xSocket ); +BaseType_t FreeRTOS_tx_size( Socket_t xSocket ); + +/* Returns the number of outstanding bytes in txStream. */ +/* The function FreeRTOS_outstanding() was already implemented +FreeRTOS_tx_size(). */ +#define FreeRTOS_outstanding( xSocket ) FreeRTOS_tx_size( xSocket ) + +/* Returns the number of bytes in the socket's rxStream. */ +/* The function FreeRTOS_recvcount() was already implemented +FreeRTOS_rx_size(). */ +#define FreeRTOS_recvcount( xSocket ) FreeRTOS_rx_size( xSocket ) + +/* + * For advanced applications only: + * Get a direct pointer to the circular transmit buffer. + * '*pxLength' will contain the number of bytes that may be written. + */ +uint8_t *FreeRTOS_get_tx_head( Socket_t xSocket, BaseType_t *pxLength ); + +#endif /* ipconfigUSE_TCP */ + +/* + * Connect / disconnect handler for a TCP socket + * For example: + * static void vMyConnectHandler (Socket_t xSocket, BaseType_t ulConnected) + * { + * } + * F_TCP_UDP_Handler_t xHnd = { vMyConnectHandler }; + * FreeRTOS_setsockopt( sock, 0, FREERTOS_SO_TCP_CONN_HANDLER, ( void * ) &xHnd, sizeof( xHnd ) ); + */ + +typedef void (* FOnConnected_t )( Socket_t /* xSocket */, BaseType_t /* ulConnected */ ); + +/* + * Reception handler for a TCP socket + * A user-proved function will be called on reception of a message + * If the handler returns a positive number, the messages will not be stored + * For example: + * static BaseType_t xOnTCPReceive( Socket_t xSocket, void * pData, size_t xLength ) + * { + * // handle the message + * return 1; + * } + * F_TCP_UDP_Handler_t xHand = { xOnTCPReceive }; + * FreeRTOS_setsockopt( sock, 0, FREERTOS_SO_TCP_RECV_HANDLER, ( void * ) &xHand, sizeof( xHand ) ); + */ +typedef BaseType_t (* FOnTCPReceive_t )( Socket_t /* xSocket */, void * /* pData */, size_t /* xLength */ ); +typedef void (* FOnTCPSent_t )( Socket_t /* xSocket */, size_t /* xLength */ ); + +/* + * Reception handler for a UDP socket + * A user-proved function will be called on reception of a message + * If the handler returns a positive number, the messages will not be stored + */ +typedef BaseType_t (* FOnUDPReceive_t ) (Socket_t /* xSocket */, void * /* pData */, size_t /* xLength */, + const struct freertos_sockaddr * /* pxFrom */, const struct freertos_sockaddr * /* pxDest */ ); +typedef void (* FOnUDPSent_t )( Socket_t /* xSocket */, size_t /* xLength */ ); + + +typedef union xTCP_UDP_HANDLER +{ + FOnConnected_t pxOnTCPConnected; /* FREERTOS_SO_TCP_CONN_HANDLER */ + FOnTCPReceive_t pxOnTCPReceive; /* FREERTOS_SO_TCP_RECV_HANDLER */ + FOnTCPSent_t pxOnTCPSent; /* FREERTOS_SO_TCP_SENT_HANDLER */ + FOnUDPReceive_t pxOnUDPReceive; /* FREERTOS_SO_UDP_RECV_HANDLER */ + FOnUDPSent_t pxOnUDPSent; /* FREERTOS_SO_UDP_SENT_HANDLER */ +} F_TCP_UDP_Handler_t; + +BaseType_t FreeRTOS_setsockopt( Socket_t xSocket, int32_t lLevel, int32_t lOptionName, const void *pvOptionValue, size_t xOptionLength ); +BaseType_t FreeRTOS_closesocket( Socket_t xSocket ); +uint32_t FreeRTOS_gethostbyname( const char *pcHostName ); +uint32_t FreeRTOS_inet_addr( const char * pcIPAddress ); + +/* + * For the web server: borrow the circular Rx buffer for inspection + * HTML driver wants to see if a sequence of 13/10/13/10 is available + */ +const struct xSTREAM_BUFFER *FreeRTOS_get_rx_buf( Socket_t xSocket ); + +void FreeRTOS_netstat( void ); + +#if ipconfigSUPPORT_SELECT_FUNCTION == 1 + + /* For FD_SET and FD_CLR, a combination of the following bits can be used: */ + + typedef enum eSELECT_EVENT { + eSELECT_READ = 0x0001, + eSELECT_WRITE = 0x0002, + eSELECT_EXCEPT = 0x0004, + eSELECT_INTR = 0x0008, + eSELECT_ALL = 0x000F, + /* Reserved for internal use: */ + eSELECT_CALL_IP = 0x0010, + /* end */ + } eSelectEvent_t; + + SocketSet_t FreeRTOS_CreateSocketSet( void ); + void FreeRTOS_DeleteSocketSet( SocketSet_t xSocketSet ); + void FreeRTOS_FD_SET( Socket_t xSocket, SocketSet_t xSocketSet, EventBits_t xBitsToSet ); + void FreeRTOS_FD_CLR( Socket_t xSocket, SocketSet_t xSocketSet, EventBits_t xBitsToClear ); + EventBits_t FreeRTOS_FD_ISSET( Socket_t xSocket, SocketSet_t xSocketSet ); + BaseType_t FreeRTOS_select( SocketSet_t xSocketSet, TickType_t xBlockTimeTicks ); + +#endif /* ipconfigSUPPORT_SELECT_FUNCTION */ + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif /* FREERTOS_SOCKETS_H */ + + + + + + + + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_Stream_Buffer.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_Stream_Buffer.h new file mode 100644 index 0000000..1ebb86d --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_Stream_Buffer.h @@ -0,0 +1,256 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +/* + * FreeRTOS_Stream_Buffer.h + * + * A cicular character buffer + * An implementation of a circular buffer without a length field + * If LENGTH defines the size of the buffer, a maximum of (LENGT-1) bytes can be stored + * In order to add or read data from the buffer, memcpy() will be called at most 2 times + */ + +#ifndef FREERTOS_STREAM_BUFFER_H +#define FREERTOS_STREAM_BUFFER_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct xSTREAM_BUFFER { + volatile size_t uxTail; /* next item to read */ + volatile size_t uxMid; /* iterator within the valid items */ + volatile size_t uxHead; /* next position store a new item */ + volatile size_t uxFront; /* iterator within the free space */ + size_t LENGTH; /* const value: number of reserved elements */ + uint8_t ucArray[ sizeof( size_t ) ]; +} StreamBuffer_t; + +static portINLINE void vStreamBufferClear( StreamBuffer_t *pxBuffer ); +static portINLINE void vStreamBufferClear( StreamBuffer_t *pxBuffer ) +{ + /* Make the circular buffer empty */ + pxBuffer->uxHead = 0u; + pxBuffer->uxTail = 0u; + pxBuffer->uxFront = 0u; + pxBuffer->uxMid = 0u; +} +/*-----------------------------------------------------------*/ + +static portINLINE size_t uxStreamBufferSpace( const StreamBuffer_t *pxBuffer, const size_t uxLower, const size_t uxUpper ); +static portINLINE size_t uxStreamBufferSpace( const StreamBuffer_t *pxBuffer, const size_t uxLower, const size_t uxUpper ) +{ +/* Returns the space between uxLower and uxUpper, which equals to the distance minus 1 */ +size_t uxCount; + + uxCount = pxBuffer->LENGTH + uxUpper - uxLower - 1u; + if( uxCount >= pxBuffer->LENGTH ) + { + uxCount -= pxBuffer->LENGTH; + } + + return uxCount; +} +/*-----------------------------------------------------------*/ + +static portINLINE size_t uxStreamBufferDistance( const StreamBuffer_t *pxBuffer, const size_t uxLower, const size_t uxUpper ); +static portINLINE size_t uxStreamBufferDistance( const StreamBuffer_t *pxBuffer, const size_t uxLower, const size_t uxUpper ) +{ +/* Returns the distance between uxLower and uxUpper */ +size_t uxCount; + + uxCount = pxBuffer->LENGTH + uxUpper - uxLower; + if ( uxCount >= pxBuffer->LENGTH ) + { + uxCount -= pxBuffer->LENGTH; + } + + return uxCount; +} +/*-----------------------------------------------------------*/ + +static portINLINE size_t uxStreamBufferGetSpace( const StreamBuffer_t *pxBuffer ); +static portINLINE size_t uxStreamBufferGetSpace( const StreamBuffer_t *pxBuffer ) +{ +/* Returns the number of items which can still be added to uxHead +before hitting on uxTail */ +size_t uxHead = pxBuffer->uxHead; +size_t uxTail = pxBuffer->uxTail; + + return uxStreamBufferSpace( pxBuffer, uxHead, uxTail ); +} +/*-----------------------------------------------------------*/ + +static portINLINE size_t uxStreamBufferFrontSpace( const StreamBuffer_t *pxBuffer ); +static portINLINE size_t uxStreamBufferFrontSpace( const StreamBuffer_t *pxBuffer ) +{ +/* Distance between uxFront and uxTail +or the number of items which can still be added to uxFront, +before hitting on uxTail */ + +size_t uxFront = pxBuffer->uxFront; +size_t uxTail = pxBuffer->uxTail; + + return uxStreamBufferSpace( pxBuffer, uxFront, uxTail ); +} +/*-----------------------------------------------------------*/ + +static portINLINE size_t uxStreamBufferGetSize( const StreamBuffer_t *pxBuffer ); +static portINLINE size_t uxStreamBufferGetSize( const StreamBuffer_t *pxBuffer ) +{ +/* Returns the number of items which can be read from uxTail +before reaching uxHead */ +size_t uxHead = pxBuffer->uxHead; +size_t uxTail = pxBuffer->uxTail; + + return uxStreamBufferDistance( pxBuffer, uxTail, uxHead ); +} +/*-----------------------------------------------------------*/ + +static portINLINE size_t uxStreamBufferMidSpace( const StreamBuffer_t *pxBuffer ); +static portINLINE size_t uxStreamBufferMidSpace( const StreamBuffer_t *pxBuffer ) +{ +/* Returns the distance between uxHead and uxMid */ +size_t uxHead = pxBuffer->uxHead; +size_t uxMid = pxBuffer->uxMid; + + return uxStreamBufferDistance( pxBuffer, uxMid, uxHead ); +} +/*-----------------------------------------------------------*/ + +static portINLINE void vStreamBufferMoveMid( StreamBuffer_t *pxBuffer, size_t uxCount ); +static portINLINE void vStreamBufferMoveMid( StreamBuffer_t *pxBuffer, size_t uxCount ) +{ +/* Increment uxMid, but no further than uxHead */ +size_t uxSize = uxStreamBufferMidSpace( pxBuffer ); + + if( uxCount > uxSize ) + { + uxCount = uxSize; + } + pxBuffer->uxMid += uxCount; + if( pxBuffer->uxMid >= pxBuffer->LENGTH ) + { + pxBuffer->uxMid -= pxBuffer->LENGTH; + } +} +/*-----------------------------------------------------------*/ +static portINLINE BaseType_t xStreamBufferIsEmpty( const StreamBuffer_t *pxBuffer ); +static portINLINE BaseType_t xStreamBufferIsEmpty( const StreamBuffer_t *pxBuffer ) +{ +BaseType_t xReturn; + + /* True if no item is available */ + if( pxBuffer->uxHead == pxBuffer->uxTail ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + return xReturn; +} +/*-----------------------------------------------------------*/ + +static portINLINE BaseType_t xStreamBufferIsFull( const StreamBuffer_t *pxBuffer ); +static portINLINE BaseType_t xStreamBufferIsFull( const StreamBuffer_t *pxBuffer ) +{ + /* True if the available space equals zero. */ + return ( BaseType_t ) ( uxStreamBufferGetSpace( pxBuffer ) == 0u ); +} +/*-----------------------------------------------------------*/ + +static portINLINE BaseType_t xStreamBufferLessThenEqual( const StreamBuffer_t *pxBuffer, const size_t uxLeft, const size_t uxRight ); +static portINLINE BaseType_t xStreamBufferLessThenEqual( const StreamBuffer_t *pxBuffer, const size_t uxLeft, const size_t uxRight ) +{ +BaseType_t xReturn; +size_t uxTail = pxBuffer->uxTail; + + /* Returns true if ( uxLeft < uxRight ) */ + if( ( uxLeft < uxTail ) ^ ( uxRight < uxTail ) ) + { + if( uxRight < uxTail ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + else + { + if( uxLeft <= uxRight ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + return xReturn; +} +/*-----------------------------------------------------------*/ + +static portINLINE size_t uxStreamBufferGetPtr( StreamBuffer_t *pxBuffer, uint8_t **ppucData ); +static portINLINE size_t uxStreamBufferGetPtr( StreamBuffer_t *pxBuffer, uint8_t **ppucData ) +{ +size_t uxNextTail = pxBuffer->uxTail; +size_t uxSize = uxStreamBufferGetSize( pxBuffer ); + + *ppucData = pxBuffer->ucArray + uxNextTail; + + return FreeRTOS_min_uint32( uxSize, pxBuffer->LENGTH - uxNextTail ); +} + +/* + * Add bytes to a stream buffer. + * + * pxBuffer - The buffer to which the bytes will be added. + * uxOffset - If uxOffset > 0, data will be written at an offset from uxHead + * while uxHead will not be moved yet. + * pucData - A pointer to the data to be added. + * uxCount - The number of bytes to add. + */ +size_t uxStreamBufferAdd( StreamBuffer_t *pxBuffer, size_t uxOffset, const uint8_t *pucData, size_t uxCount ); + +/* + * Read bytes from a stream buffer. + * + * pxBuffer - The buffer from which the bytes will be read. + * uxOffset - Can be used to read data located at a certain offset from 'uxTail'. + * pucData - A pointer to the buffer into which data will be read. + * uxMaxCount - The number of bytes to read. + * xPeek - If set to pdTRUE the data will remain in the buffer. + */ +size_t uxStreamBufferGet( StreamBuffer_t *pxBuffer, size_t uxOffset, uint8_t *pucData, size_t uxMaxCount, BaseType_t xPeek ); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* !defined( FREERTOS_STREAM_BUFFER_H ) */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_TCP_IP.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_TCP_IP.h new file mode 100644 index 0000000..503fa10 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_TCP_IP.h @@ -0,0 +1,80 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +#ifndef FREERTOS_TCP_IP_H +#define FREERTOS_TCP_IP_H + +#ifdef __cplusplus +extern "C" { +#endif + +BaseType_t xProcessReceivedTCPPacket( NetworkBufferDescriptor_t *pxNetworkBuffer ); + +typedef enum eTCP_STATE { + /* Comments about the TCP states are borrowed from the very useful + * Wiki page: + * http://en.wikipedia.org/wiki/Transmission_Control_Protocol */ + eCLOSED = 0u, /* 0 (server + client) no connection state at all. */ + eTCP_LISTEN, /* 1 (server) waiting for a connection request + from any remote TCP and port. */ + eCONNECT_SYN, /* 2 (client) internal state: socket wants to send + a connect */ + eSYN_FIRST, /* 3 (server) Just created, must ACK the SYN request. */ + eSYN_RECEIVED, /* 4 (server) waiting for a confirming connection request + acknowledgement after having both received and sent a connection request. */ + eESTABLISHED, /* 5 (server + client) an open connection, data received can be + delivered to the user. The normal state for the data transfer phase of the connection. */ + eFIN_WAIT_1, /* 6 (server + client) waiting for a connection termination request from the remote TCP, + or an acknowledgement of the connection termination request previously sent. */ + eFIN_WAIT_2, /* 7 (server + client) waiting for a connection termination request from the remote TCP. */ + eCLOSE_WAIT, /* 8 (server + client) waiting for a connection termination request from the local user. */ + eCLOSING, /* (server + client) waiting for a connection termination request acknowledgement from the remote TCP. */ + eLAST_ACK, /* 9 (server + client) waiting for an acknowledgement of the connection termination request + previously sent to the remote TCP + (which includes an acknowledgement of its connection termination request). */ + eTIME_WAIT, /* 10 (either server or client) waiting for enough time to pass to be sure the remote TCP received the + acknowledgement of its connection termination request. [According to RFC 793 a connection can + stay in TIME-WAIT for a maximum of four minutes known as a MSL (maximum segment lifetime).] */ +} eIPTCPState_t; + + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif /* FREERTOS_TCP_IP_H */ + + + + + + + + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_TCP_WIN.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_TCP_WIN.h new file mode 100644 index 0000000..6913322 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_TCP_WIN.h @@ -0,0 +1,213 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +/* + * FreeRTOS_TCP_WIN.c + * Module which handles the TCP windowing schemes for FreeRTOS-PLUS-TCP + */ + +#ifndef FREERTOS_TCP_WIN_H +#define FREERTOS_TCP_WIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern BaseType_t xTCPWindowLoggingLevel; + +typedef struct xTCPTimer +{ + uint32_t ulBorn; +} TCPTimer_t; + +typedef struct xTCP_SEGMENT +{ + uint32_t ulSequenceNumber; /* The sequence number of the first byte in this packet */ + int32_t lMaxLength; /* Maximum space, number of bytes which can be stored in this segment */ + int32_t lDataLength; /* Actual number of bytes */ + int32_t lStreamPos; /* reference to the [t|r]xStream of the socket */ + TCPTimer_t xTransmitTimer; /* saves a timestamp at the moment this segment gets transmitted (TX only) */ + union + { + struct + { + uint32_t + ucTransmitCount : 8,/* Number of times the segment has been transmitted, used to calculate the RTT */ + ucDupAckCount : 8, /* Counts the number of times that a higher segment was ACK'd. After 3 times a Fast Retransmission takes place */ + bOutstanding : 1, /* It the peer's turn, we're just waiting for an ACK */ + bAcked : 1, /* This segment has been acknowledged */ + bIsForRx : 1; /* pdTRUE if segment is used for reception */ + } bits; + uint32_t ulFlags; + } u; +#if( ipconfigUSE_TCP_WIN != 0 ) + struct xLIST_ITEM xQueueItem; /* TX only: segments can be linked in one of three queues: xPriorityQueue, xTxQueue, and xWaitQueue */ + struct xLIST_ITEM xListItem; /* With this item the segment can be connected to a list, depending on who is owning it */ +#endif +} TCPSegment_t; + +typedef struct xTCP_WINSIZE +{ + uint32_t ulRxWindowLength; + uint32_t ulTxWindowLength; +} TCPWinSize_t; + +/* + * If TCP time-stamps are being used, they will occupy 12 bytes in + * each packet, and thus the message space will become smaller + */ +/* Keep this as a multiple of 4 */ +#if( ipconfigUSE_TCP_WIN == 1 ) + #define ipSIZE_TCP_OPTIONS 16u +#else + #define ipSIZE_TCP_OPTIONS 12u +#endif + +/* + * Every TCP connection owns a TCP window for the administration of all packets + * It owns two sets of segment descriptors, incoming and outgoing + */ +typedef struct xTCP_WINDOW +{ + union + { + struct + { + uint32_t + bHasInit : 1, /* The window structure has been initialised */ + bSendFullSize : 1, /* May only send packets with a size equal to MSS (for optimisation) */ + bTimeStamps : 1; /* Socket is supposed to use TCP time-stamps. This depends on the */ + } bits; /* party which opens the connection */ + uint32_t ulFlags; + } u; + TCPWinSize_t xSize; + struct + { + uint32_t ulFirstSequenceNumber; /* Logging & debug: the first segment received/sent in this connection + * for Tx: initial send sequence number (ISS) + * for Rx: initial receive sequence number (IRS) */ + uint32_t ulCurrentSequenceNumber;/* Tx/Rx: the oldest sequence number not yet confirmed, also SND.UNA / RCV.NXT + * In other words: the sequence number of the left side of the sliding window */ + uint32_t ulFINSequenceNumber; /* The sequence number which carried the FIN flag */ + uint32_t ulHighestSequenceNumber;/* Sequence number of the right-most byte + 1 */ + } rx, tx; + uint32_t ulOurSequenceNumber; /* The SEQ number we're sending out */ + uint32_t ulUserDataLength; /* Number of bytes in Rx buffer which may be passed to the user, after having received a 'missing packet' */ + uint32_t ulNextTxSequenceNumber; /* The sequence number given to the next byte to be added for transmission */ + int32_t lSRTT; /* Smoothed Round Trip Time, it may increment quickly and it decrements slower */ + uint8_t ucOptionLength; /* Number of valid bytes in ulOptionsData[] */ +#if( ipconfigUSE_TCP_WIN == 1 ) + List_t xPriorityQueue; /* Priority queue: segments which must be sent immediately */ + List_t xTxQueue; /* Transmit queue: segments queued for transmission */ + List_t xWaitQueue; /* Waiting queue: outstanding segments */ + TCPSegment_t *pxHeadSegment; /* points to a segment which has not been transmitted and it's size is still growing (user data being added) */ + uint32_t ulOptionsData[ipSIZE_TCP_OPTIONS/sizeof(uint32_t)]; /* Contains the options we send out */ + List_t xTxSegments; /* A linked list of all transmission segments, sorted on sequence number */ + List_t xRxSegments; /* A linked list of reception segments, order depends on sequence of arrival */ +#else + /* For tiny TCP, there is only 1 outstanding TX segment */ + TCPSegment_t xTxSegment; /* Priority queue */ +#endif + uint16_t usOurPortNumber; /* Mostly for debugging/logging: our TCP port number */ + uint16_t usPeerPortNumber; /* debugging/logging: the peer's TCP port number */ + uint16_t usMSS; /* Current accepted MSS */ + uint16_t usMSSInit; /* MSS as configured by the socket owner */ +} TCPWindow_t; + + +/*============================================================================= + * + * Creation and destruction + * + *=============================================================================*/ + +/* Create and initialize a window */ +void vTCPWindowCreate( TCPWindow_t *pxWindow, uint32_t ulRxWindowLength, + uint32_t ulTxWindowLength, uint32_t ulAckNumber, uint32_t ulSequenceNumber, uint32_t ulMSS ); + +/* Destroy a window (always returns NULL) + * It will free some resources: a collection of segments */ +void vTCPWindowDestroy( TCPWindow_t *pxWindow ); + +/* Initialize a window */ +void vTCPWindowInit( TCPWindow_t *pxWindow, uint32_t ulAckNumber, uint32_t ulSequenceNumber, uint32_t ulMSS ); + +/* Clean up allocated segments. Should only be called when FreeRTOS+TCP will no longer be used. */ +void vTCPSegmentCleanup( void ); + +/*============================================================================= + * + * Rx functions + * + *=============================================================================*/ + +/* if true may be passed directly to user (segment expected and window is empty) + * But pxWindow->ackno should always be used to set "BUF->ackno" */ +int32_t lTCPWindowRxCheck( TCPWindow_t *pxWindow, uint32_t ulSequenceNumber, uint32_t ulLength, uint32_t ulSpace ); + +/* When lTCPWindowRxCheck returned false, please call store for this unexpected data */ +BaseType_t xTCPWindowRxStore( TCPWindow_t *pxWindow, uint32_t ulSequenceNumber, uint32_t ulLength ); + +/* This function will be called as soon as a FIN is received. It will return true + * if there are no 'open' reception segments */ +BaseType_t xTCPWindowRxEmpty( TCPWindow_t *pxWindow ); + +/* _HT_ Temporary function for testing/debugging + * Not used at this moment */ +void vTCPWinShowSegments( TCPWindow_t *pxWindow, BaseType_t bForRx ); + +/*============================================================================= + * + * Tx functions + * + *=============================================================================*/ + +/* Adds data to the Tx-window */ +int32_t lTCPWindowTxAdd( TCPWindow_t *pxWindow, uint32_t ulLength, int32_t lPosition, int32_t lMax ); + +/* Check data to be sent and calculate the time period we may sleep */ +BaseType_t xTCPWindowTxHasData( TCPWindow_t *pxWindow, uint32_t ulWindowSize, TickType_t *pulDelay ); + +/* See if anything is left to be sent + * Function will be called when a FIN has been received. Only when the TX window is clean, + * it will return pdTRUE */ +BaseType_t xTCPWindowTxDone( TCPWindow_t *pxWindow ); + +/* Fetches data to be sent. + * apPos will point to a location with the circular data buffer: txStream */ +uint32_t ulTCPWindowTxGet( TCPWindow_t *pxWindow, uint32_t ulWindowSize, int32_t *plPosition ); + +/* Receive a normal ACK */ +uint32_t ulTCPWindowTxAck( TCPWindow_t *pxWindow, uint32_t ulSequenceNumber ); + +/* Receive a SACK option */ +uint32_t ulTCPWindowTxSack( TCPWindow_t *pxWindow, uint32_t ulFirst, uint32_t ulLast ); + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* FREERTOS_TCP_WIN_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_UDP_IP.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_UDP_IP.h new file mode 100644 index 0000000..9915952 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_UDP_IP.h @@ -0,0 +1,56 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +#ifndef FREERTOS_UDP_IP_H +#define FREERTOS_UDP_IP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Application level configuration options. */ +#include "FreeRTOSIPConfig.h" +#include "FreeRTOSIPConfigDefaults.h" +#include "IPTraceMacroDefaults.h" + + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif /* FREERTOS_UDP_IP_H */ + + + + + + + + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_errno_TCP.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_errno_TCP.h new file mode 100644 index 0000000..fffe22d --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/FreeRTOS_errno_TCP.h @@ -0,0 +1,90 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +#ifndef FREERTOS_ERRNO_TCP +#define FREERTOS_ERRNO_TCP + +/* The following definitions will be included in the core FreeRTOS code in +future versions of FreeRTOS - hence the 'pd' (ProjDefs) prefix - at which time +this file will be removed. */ + +/* The following errno values are used by FreeRTOS+ components, not FreeRTOS +itself. */ + +/* For future compatibility (see comment above), check the definitions have not +already been made. */ +#ifndef pdFREERTOS_ERRNO_NONE + #define pdFREERTOS_ERRNO_NONE 0 /* No errors */ + #define pdFREERTOS_ERRNO_ENOENT 2 /* No such file or directory */ + #define pdFREERTOS_ERRNO_EINTR 4 /* Interrupted system call */ + #define pdFREERTOS_ERRNO_EIO 5 /* I/O error */ + #define pdFREERTOS_ERRNO_ENXIO 6 /* No such device or address */ + #define pdFREERTOS_ERRNO_EBADF 9 /* Bad file number */ + #define pdFREERTOS_ERRNO_EAGAIN 11 /* No more processes */ + #define pdFREERTOS_ERRNO_EWOULDBLOCK 11 /* Operation would block */ + #define pdFREERTOS_ERRNO_ENOMEM 12 /* Not enough memory */ + #define pdFREERTOS_ERRNO_EACCES 13 /* Permission denied */ + #define pdFREERTOS_ERRNO_EFAULT 14 /* Bad address */ + #define pdFREERTOS_ERRNO_EBUSY 16 /* Mount device busy */ + #define pdFREERTOS_ERRNO_EEXIST 17 /* File exists */ + #define pdFREERTOS_ERRNO_EXDEV 18 /* Cross-device link */ + #define pdFREERTOS_ERRNO_ENODEV 19 /* No such device */ + #define pdFREERTOS_ERRNO_ENOTDIR 20 /* Not a directory */ + #define pdFREERTOS_ERRNO_EISDIR 21 /* Is a directory */ + #define pdFREERTOS_ERRNO_EINVAL 22 /* Invalid argument */ + #define pdFREERTOS_ERRNO_ENOSPC 28 /* No space left on device */ + #define pdFREERTOS_ERRNO_ESPIPE 29 /* Illegal seek */ + #define pdFREERTOS_ERRNO_EROFS 30 /* Read only file system */ + #define pdFREERTOS_ERRNO_EUNATCH 42 /* Protocol driver not attached */ + #define pdFREERTOS_ERRNO_EBADE 50 /* Invalid exchange */ + #define pdFREERTOS_ERRNO_EFTYPE 79 /* Inappropriate file type or format */ + #define pdFREERTOS_ERRNO_ENMFILE 89 /* No more files */ + #define pdFREERTOS_ERRNO_ENOTEMPTY 90 /* Directory not empty */ + #define pdFREERTOS_ERRNO_ENAMETOOLONG 91 /* File or path name too long */ + #define pdFREERTOS_ERRNO_EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ + #define pdFREERTOS_ERRNO_ENOBUFS 105 /* No buffer space available */ + #define pdFREERTOS_ERRNO_ENOPROTOOPT 109 /* Protocol not available */ + #define pdFREERTOS_ERRNO_EADDRINUSE 112 /* Address already in use */ + #define pdFREERTOS_ERRNO_ETIMEDOUT 116 /* Connection timed out */ + #define pdFREERTOS_ERRNO_EINPROGRESS 119 /* Connection already in progress */ + #define pdFREERTOS_ERRNO_EALREADY 120 /* Socket already connected */ + #define pdFREERTOS_ERRNO_EADDRNOTAVAIL 125 /* Address not available */ + #define pdFREERTOS_ERRNO_EISCONN 127 /* Socket is already connected */ + #define pdFREERTOS_ERRNO_ENOTCONN 128 /* Socket is not connected */ + #define pdFREERTOS_ERRNO_ENOMEDIUM 135 /* No medium inserted */ + #define pdFREERTOS_ERRNO_EILSEQ 138 /* An invalid UTF-16 sequence was encountered. */ + #define pdFREERTOS_ERRNO_ECANCELED 140 /* Operation canceled. */ + + /* The following endian values are used by FreeRTOS+ components, not FreeRTOS + itself. */ + #define pdFREERTOS_LITTLE_ENDIAN 0 + #define pdFREERTOS_BIG_ENDIAN 1 + +#endif /* pdFREERTOS_ERRNO_NONE */ + +#endif /* FREERTOS_ERRNO_TCP */ + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/IPTraceMacroDefaults.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/IPTraceMacroDefaults.h new file mode 100644 index 0000000..3fa8eab --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/IPTraceMacroDefaults.h @@ -0,0 +1,193 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +/* This file provides default (empty) implementations for any IP trace macros +that are not defined by the user. See +http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/TCP_IP_Trace.html */ + +#ifndef UDP_TRACE_MACRO_DEFAULTS_H +#define UDP_TRACE_MACRO_DEFAULTS_H + +#ifndef iptraceNETWORK_DOWN + #define iptraceNETWORK_DOWN() +#endif + +#ifndef iptraceNETWORK_BUFFER_RELEASED + #define iptraceNETWORK_BUFFER_RELEASED( pxBufferAddress ) +#endif + +#ifndef iptraceNETWORK_BUFFER_OBTAINED + #define iptraceNETWORK_BUFFER_OBTAINED( pxBufferAddress ) +#endif + +#ifndef iptraceNETWORK_BUFFER_OBTAINED_FROM_ISR + #define iptraceNETWORK_BUFFER_OBTAINED_FROM_ISR( pxBufferAddress ) +#endif + +#ifndef iptraceFAILED_TO_OBTAIN_NETWORK_BUFFER + #define iptraceFAILED_TO_OBTAIN_NETWORK_BUFFER() +#endif + +#ifndef iptraceFAILED_TO_OBTAIN_NETWORK_BUFFER_FROM_ISR + #define iptraceFAILED_TO_OBTAIN_NETWORK_BUFFER_FROM_ISR() +#endif + +#ifndef iptraceCREATING_ARP_REQUEST + #define iptraceCREATING_ARP_REQUEST( ulIPAddress ) +#endif + +#ifndef iptraceARP_TABLE_ENTRY_WILL_EXPIRE + #define iptraceARP_TABLE_ENTRY_WILL_EXPIRE( ulIPAddress ) +#endif + +#ifndef iptraceARP_TABLE_ENTRY_EXPIRED + #define iptraceARP_TABLE_ENTRY_EXPIRED( ulIPAddress ) +#endif + +#ifndef iptraceARP_TABLE_ENTRY_CREATED + #define iptraceARP_TABLE_ENTRY_CREATED( ulIPAddress, ucMACAddress ) +#endif + +#ifndef iptraceSENDING_UDP_PACKET + #define iptraceSENDING_UDP_PACKET( ulIPAddress ) +#endif + +#ifndef iptracePACKET_DROPPED_TO_GENERATE_ARP + #define iptracePACKET_DROPPED_TO_GENERATE_ARP( ulIPAddress ) +#endif + +#ifndef iptraceICMP_PACKET_RECEIVED + #define iptraceICMP_PACKET_RECEIVED() +#endif + +#ifndef iptraceSENDING_PING_REPLY + #define iptraceSENDING_PING_REPLY( ulIPAddress ) +#endif + +#ifndef traceARP_PACKET_RECEIVED + #define traceARP_PACKET_RECEIVED() +#endif + +#ifndef iptracePROCESSING_RECEIVED_ARP_REPLY + #define iptracePROCESSING_RECEIVED_ARP_REPLY( ulIPAddress ) +#endif + +#ifndef iptraceSENDING_ARP_REPLY + #define iptraceSENDING_ARP_REPLY( ulIPAddress ) +#endif + +#ifndef iptraceFAILED_TO_CREATE_SOCKET + #define iptraceFAILED_TO_CREATE_SOCKET() +#endif + +#ifndef iptraceFAILED_TO_CREATE_EVENT_GROUP + #define iptraceFAILED_TO_CREATE_EVENT_GROUP() +#endif + +#ifndef iptraceRECVFROM_DISCARDING_BYTES + #define iptraceRECVFROM_DISCARDING_BYTES( xNumberOfBytesDiscarded ) +#endif + +#ifndef iptraceETHERNET_RX_EVENT_LOST + #define iptraceETHERNET_RX_EVENT_LOST() +#endif + +#ifndef iptraceSTACK_TX_EVENT_LOST + #define iptraceSTACK_TX_EVENT_LOST( xEvent ) +#endif + +#ifndef iptraceNETWORK_EVENT_RECEIVED + #define iptraceNETWORK_EVENT_RECEIVED( eEvent ) +#endif + +#ifndef iptraceBIND_FAILED + #define iptraceBIND_FAILED( xSocket, usPort ) +#endif + +#ifndef iptraceDHCP_REQUESTS_FAILED_USING_DEFAULT_IP_ADDRESS + #define iptraceDHCP_REQUESTS_FAILED_USING_DEFAULT_IP_ADDRESS( ulIPAddress ) +#endif + +#ifndef iptraceSENDING_DHCP_DISCOVER + #define iptraceSENDING_DHCP_DISCOVER() +#endif + +#ifndef iptraceSENDING_DHCP_REQUEST + #define iptraceSENDING_DHCP_REQUEST() +#endif + +#ifndef iptraceDHCP_SUCCEDEED + #define iptraceDHCP_SUCCEDEED( address ) +#endif + +#ifndef iptraceNETWORK_INTERFACE_TRANSMIT + #define iptraceNETWORK_INTERFACE_TRANSMIT() +#endif + +#ifndef iptraceNETWORK_INTERFACE_RECEIVE + #define iptraceNETWORK_INTERFACE_RECEIVE() +#endif + +#ifndef iptraceSENDING_DNS_REQUEST + #define iptraceSENDING_DNS_REQUEST() +#endif + +#ifndef iptraceWAITING_FOR_TX_DMA_DESCRIPTOR + #define iptraceWAITING_FOR_TX_DMA_DESCRIPTOR() +#endif + +#ifndef ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS + #define ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS 0 +#endif + +#ifndef iptraceFAILED_TO_NOTIFY_SELECT_GROUP + #define iptraceFAILED_TO_NOTIFY_SELECT_GROUP( xSocket ) +#endif + +#ifndef pvPortMallocSocket + #define pvPortMallocSocket(xSize) pvPortMalloc( ( xSize ) ) +#endif + +#ifndef iptraceRECVFROM_TIMEOUT + #define iptraceRECVFROM_TIMEOUT() +#endif + +#ifndef iptraceRECVFROM_INTERRUPTED + #define iptraceRECVFROM_INTERRUPTED() +#endif + +#ifndef iptraceNO_BUFFER_FOR_SENDTO + #define iptraceNO_BUFFER_FOR_SENDTO() +#endif + +#ifndef iptraceSENDTO_SOCKET_NOT_BOUND + #define iptraceSENDTO_SOCKET_NOT_BOUND() +#endif + +#ifndef iptraceSENDTO_DATA_TOO_LONG + #define iptraceSENDTO_DATA_TOO_LONG() +#endif + +#endif /* UDP_TRACE_MACRO_DEFAULTS_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/NetworkBufferManagement.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/NetworkBufferManagement.h new file mode 100644 index 0000000..8e4f903 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/NetworkBufferManagement.h @@ -0,0 +1,70 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +#ifndef NETWORK_BUFFER_MANAGEMENT_H +#define NETWORK_BUFFER_MANAGEMENT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* NOTE PUBLIC API FUNCTIONS. */ +BaseType_t xNetworkBuffersInitialise( void ); +NetworkBufferDescriptor_t *pxGetNetworkBufferWithDescriptor( size_t xRequestedSizeBytes, TickType_t xBlockTimeTicks ); +NetworkBufferDescriptor_t *pxNetworkBufferGetFromISR( size_t xRequestedSizeBytes ); +void vReleaseNetworkBufferAndDescriptor( NetworkBufferDescriptor_t * const pxNetworkBuffer ); +BaseType_t vNetworkBufferReleaseFromISR( NetworkBufferDescriptor_t * const pxNetworkBuffer ); +uint8_t *pucGetNetworkBuffer( size_t *pxRequestedSizeBytes ); +void vReleaseNetworkBuffer( uint8_t *pucEthernetBuffer ); + +/* Get the current number of free network buffers. */ +UBaseType_t uxGetNumberOfFreeNetworkBuffers( void ); + +/* Get the lowest number of free network buffers. */ +UBaseType_t uxGetMinimumFreeNetworkBuffers( void ); + +/* Copy a network buffer into a bigger buffer. */ +NetworkBufferDescriptor_t *pxDuplicateNetworkBufferWithDescriptor( NetworkBufferDescriptor_t * const pxNetworkBuffer, + BaseType_t xNewLength); + +/* Increase the size of a Network Buffer. +In case BufferAllocation_2.c is used, the new space must be allocated. */ +NetworkBufferDescriptor_t *pxResizeNetworkBufferWithDescriptor( NetworkBufferDescriptor_t * pxNetworkBuffer, + size_t xNewSizeBytes ); + +#if ipconfigTCP_IP_SANITY + /* + * Check if an address is a valid pointer to a network descriptor + * by looking it up in the array of network descriptors + */ + UBaseType_t bIsValidNetworkDescriptor (const NetworkBufferDescriptor_t * pxDesc); + BaseType_t prvIsFreeBuffer( const NetworkBufferDescriptor_t *pxDescr ); +#endif + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif /* NETWORK_BUFFER_MANAGEMENT_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/NetworkInterface.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/NetworkInterface.h new file mode 100644 index 0000000..2924b79 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include/NetworkInterface.h @@ -0,0 +1,44 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + +#ifndef NETWORK_INTERFACE_H +#define NETWORK_INTERFACE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* NOTE PUBLIC API FUNCTIONS. */ +BaseType_t xNetworkInterfaceInitialise( void ); +BaseType_t xNetworkInterfaceOutput( NetworkBufferDescriptor_t * const pxNetworkBuffer, BaseType_t xReleaseAfterSend ); +void vNetworkInterfaceAllocateRAMToBuffers( NetworkBufferDescriptor_t pxNetworkBuffers[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ] ); +BaseType_t xGetPhyLinkStatus( void ); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif /* NETWORK_INTERFACE_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/BufferManagement/BufferAllocation_1.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/BufferManagement/BufferAllocation_1.c new file mode 100644 index 0000000..3540b15 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/BufferManagement/BufferAllocation_1.c @@ -0,0 +1,423 @@ +/* +FreeRTOS+TCP V2.0.11 +Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + http://aws.amazon.com/freertos + http://www.FreeRTOS.org +*/ + +/****************************************************************************** + * + * See the following web page for essential buffer allocation scheme usage and + * configuration details: + * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/Embedded_Ethernet_Buffer_Management.html + * + ******************************************************************************/ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_IP_Private.h" +#include "NetworkInterface.h" +#include "NetworkBufferManagement.h" + +/* For an Ethernet interrupt to be able to obtain a network buffer there must +be at least this number of buffers available. */ +#define baINTERRUPT_BUFFER_GET_THRESHOLD ( 3 ) + +/* A list of free (available) NetworkBufferDescriptor_t structures. */ +static List_t xFreeBuffersList; + +/* Some statistics about the use of buffers. */ +static UBaseType_t uxMinimumFreeNetworkBuffers = 0u; + +/* Declares the pool of NetworkBufferDescriptor_t structures that are available +to the system. All the network buffers referenced from xFreeBuffersList exist +in this array. The array is not accessed directly except during initialisation, +when the xFreeBuffersList is filled (as all the buffers are free when the system +is booted). */ +static NetworkBufferDescriptor_t xNetworkBuffers[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ]; + +/* This constant is defined as true to let FreeRTOS_TCP_IP.c know that the +network buffers have constant size, large enough to hold the biggest Ethernet +packet. No resizing will be done. */ +const BaseType_t xBufferAllocFixedSize = pdTRUE; + +/* The semaphore used to obtain network buffers. */ +static SemaphoreHandle_t xNetworkBufferSemaphore = NULL; + +#if( ipconfigTCP_IP_SANITY != 0 ) + static char cIsLow = pdFALSE; + UBaseType_t bIsValidNetworkDescriptor( const NetworkBufferDescriptor_t * pxDesc ); +#else + static UBaseType_t bIsValidNetworkDescriptor( const NetworkBufferDescriptor_t * pxDesc ); +#endif /* ipconfigTCP_IP_SANITY */ + +static void prvShowWarnings( void ); + +/* The user can define their own ipconfigBUFFER_ALLOC_LOCK() and +ipconfigBUFFER_ALLOC_UNLOCK() macros, especially for use form an ISR. If these +are not defined then default them to call the normal enter/exit critical +section macros. */ +#if !defined( ipconfigBUFFER_ALLOC_LOCK ) + + #define ipconfigBUFFER_ALLOC_INIT( ) do {} while (0) + #define ipconfigBUFFER_ALLOC_LOCK_FROM_ISR() \ + UBaseType_t uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR(); \ + { + + #define ipconfigBUFFER_ALLOC_UNLOCK_FROM_ISR() \ + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); \ + } + + #define ipconfigBUFFER_ALLOC_LOCK() taskENTER_CRITICAL() + #define ipconfigBUFFER_ALLOC_UNLOCK() taskEXIT_CRITICAL() + +#endif /* ipconfigBUFFER_ALLOC_LOCK */ + +/*-----------------------------------------------------------*/ + +#if( ipconfigTCP_IP_SANITY != 0 ) + + /* HT: SANITY code will be removed as soon as the library is stable + * and and ready to become public + * Function below gives information about the use of buffers */ + #define WARN_LOW ( 2 ) + #define WARN_HIGH ( ( 5 * ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ) / 10 ) + +#endif /* ipconfigTCP_IP_SANITY */ + +/*-----------------------------------------------------------*/ + +#if( ipconfigTCP_IP_SANITY != 0 ) + + BaseType_t prvIsFreeBuffer( const NetworkBufferDescriptor_t *pxDescr ) + { + return ( bIsValidNetworkDescriptor( pxDescr ) != 0 ) && + ( listIS_CONTAINED_WITHIN( &xFreeBuffersList, &( pxDescr->xBufferListItem ) ) != 0 ); + } + /*-----------------------------------------------------------*/ + + static void prvShowWarnings( void ) + { + UBaseType_t uxCount = uxGetNumberOfFreeNetworkBuffers( ); + if( ( ( cIsLow == 0 ) && ( uxCount <= WARN_LOW ) ) || ( ( cIsLow != 0 ) && ( uxCount >= WARN_HIGH ) ) ) + { + cIsLow = !cIsLow; + FreeRTOS_debug_printf( ( "*** Warning *** %s %lu buffers left\n", cIsLow ? "only" : "now", uxCount ) ); + } + } + /*-----------------------------------------------------------*/ + + UBaseType_t bIsValidNetworkDescriptor( const NetworkBufferDescriptor_t * pxDesc ) + { + uint32_t offset = ( uint32_t ) ( ((const char *)pxDesc) - ((const char *)xNetworkBuffers) ); + if( ( offset >= sizeof( xNetworkBuffers ) ) || + ( ( offset % sizeof( xNetworkBuffers[0] ) ) != 0 ) ) + return pdFALSE; + return (UBaseType_t) (pxDesc - xNetworkBuffers) + 1; + } + /*-----------------------------------------------------------*/ + +#else + static UBaseType_t bIsValidNetworkDescriptor (const NetworkBufferDescriptor_t * pxDesc) + { + ( void ) pxDesc; + return ( UBaseType_t ) pdTRUE; + } + /*-----------------------------------------------------------*/ + + static void prvShowWarnings( void ) + { + } + /*-----------------------------------------------------------*/ + +#endif /* ipconfigTCP_IP_SANITY */ + +BaseType_t xNetworkBuffersInitialise( void ) +{ +BaseType_t xReturn, x; + + /* Only initialise the buffers and their associated kernel objects if they + have not been initialised before. */ + if( xNetworkBufferSemaphore == NULL ) + { + /* In case alternative locking is used, the mutexes can be initialised + here */ + ipconfigBUFFER_ALLOC_INIT(); + + xNetworkBufferSemaphore = xSemaphoreCreateCounting( ( UBaseType_t ) ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS, ( UBaseType_t ) ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ); + configASSERT( xNetworkBufferSemaphore ); + + if( xNetworkBufferSemaphore != NULL ) + { + vListInitialise( &xFreeBuffersList ); + + /* Initialise all the network buffers. The buffer storage comes + from the network interface, and different hardware has different + requirements. */ + vNetworkInterfaceAllocateRAMToBuffers( xNetworkBuffers ); + for( x = 0; x < ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS; x++ ) + { + /* Initialise and set the owner of the buffer list items. */ + vListInitialiseItem( &( xNetworkBuffers[ x ].xBufferListItem ) ); + listSET_LIST_ITEM_OWNER( &( xNetworkBuffers[ x ].xBufferListItem ), &xNetworkBuffers[ x ] ); + + /* Currently, all buffers are available for use. */ + vListInsert( &xFreeBuffersList, &( xNetworkBuffers[ x ].xBufferListItem ) ); + } + + uxMinimumFreeNetworkBuffers = ( UBaseType_t ) ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS; + } + } + + if( xNetworkBufferSemaphore == NULL ) + { + xReturn = pdFAIL; + } + else + { + xReturn = pdPASS; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +NetworkBufferDescriptor_t *pxGetNetworkBufferWithDescriptor( size_t xRequestedSizeBytes, TickType_t xBlockTimeTicks ) +{ +NetworkBufferDescriptor_t *pxReturn = NULL; +BaseType_t xInvalid = pdFALSE; +UBaseType_t uxCount; + + /* The current implementation only has a single size memory block, so + the requested size parameter is not used (yet). */ + ( void ) xRequestedSizeBytes; + + if( xNetworkBufferSemaphore != NULL ) + { + /* If there is a semaphore available, there is a network buffer + available. */ + if( xSemaphoreTake( xNetworkBufferSemaphore, xBlockTimeTicks ) == pdPASS ) + { + /* Protect the structure as they are accessed from tasks and + interrupts. */ + ipconfigBUFFER_ALLOC_LOCK(); + { + pxReturn = ( NetworkBufferDescriptor_t * ) listGET_OWNER_OF_HEAD_ENTRY( &xFreeBuffersList ); + + if( ( bIsValidNetworkDescriptor( pxReturn ) != pdFALSE_UNSIGNED ) && + listIS_CONTAINED_WITHIN( &xFreeBuffersList, &( pxReturn->xBufferListItem ) ) ) + { + uxListRemove( &( pxReturn->xBufferListItem ) ); + } + else + { + xInvalid = pdTRUE; + } + } + ipconfigBUFFER_ALLOC_UNLOCK(); + + if( xInvalid == pdTRUE ) + { + /* _RB_ Can printf() be called from an interrupt? (comment + above says this can be called from an interrupt too) */ + /* _HT_ The function shall not be called from an ISR. Comment + was indeed misleading. Hopefully clear now? + So the printf()is OK here. */ + FreeRTOS_debug_printf( ( "pxGetNetworkBufferWithDescriptor: INVALID BUFFER: %p (valid %lu)\n", + pxReturn, bIsValidNetworkDescriptor( pxReturn ) ) ); + pxReturn = NULL; + } + else + { + /* Reading UBaseType_t, no critical section needed. */ + uxCount = listCURRENT_LIST_LENGTH( &xFreeBuffersList ); + + /* For stats, latch the lowest number of network buffers since + booting. */ + if( uxMinimumFreeNetworkBuffers > uxCount ) + { + uxMinimumFreeNetworkBuffers = uxCount; + } + + pxReturn->xDataLength = xRequestedSizeBytes; + + #if( ipconfigTCP_IP_SANITY != 0 ) + { + prvShowWarnings(); + } + #endif /* ipconfigTCP_IP_SANITY */ + + #if( ipconfigUSE_LINKED_RX_MESSAGES != 0 ) + { + /* make sure the buffer is not linked */ + pxReturn->pxNextBuffer = NULL; + } + #endif /* ipconfigUSE_LINKED_RX_MESSAGES */ + + if( xTCPWindowLoggingLevel > 3 ) + { + FreeRTOS_debug_printf( ( "BUF_GET[%ld]: %p (%p)\n", + bIsValidNetworkDescriptor( pxReturn ), + pxReturn, pxReturn->pucEthernetBuffer ) ); + } + } + iptraceNETWORK_BUFFER_OBTAINED( pxReturn ); + } + else + { + iptraceFAILED_TO_OBTAIN_NETWORK_BUFFER(); + } + } + + return pxReturn; +} +/*-----------------------------------------------------------*/ + +NetworkBufferDescriptor_t *pxNetworkBufferGetFromISR( size_t xRequestedSizeBytes ) +{ +NetworkBufferDescriptor_t *pxReturn = NULL; + + /* The current implementation only has a single size memory block, so + the requested size parameter is not used (yet). */ + ( void ) xRequestedSizeBytes; + + /* If there is a semaphore available then there is a buffer available, but, + as this is called from an interrupt, only take a buffer if there are at + least baINTERRUPT_BUFFER_GET_THRESHOLD buffers remaining. This prevents, + to a certain degree at least, a rapidly executing interrupt exhausting + buffer and in so doing preventing tasks from continuing. */ + if( uxQueueMessagesWaitingFromISR( ( QueueHandle_t ) xNetworkBufferSemaphore ) > ( UBaseType_t ) baINTERRUPT_BUFFER_GET_THRESHOLD ) + { + if( xSemaphoreTakeFromISR( xNetworkBufferSemaphore, NULL ) == pdPASS ) + { + /* Protect the structure as it is accessed from tasks and interrupts. */ + ipconfigBUFFER_ALLOC_LOCK_FROM_ISR(); + { + pxReturn = ( NetworkBufferDescriptor_t * ) listGET_OWNER_OF_HEAD_ENTRY( &xFreeBuffersList ); + uxListRemove( &( pxReturn->xBufferListItem ) ); + } + ipconfigBUFFER_ALLOC_UNLOCK_FROM_ISR(); + + iptraceNETWORK_BUFFER_OBTAINED_FROM_ISR( pxReturn ); + } + } + + if( pxReturn == NULL ) + { + iptraceFAILED_TO_OBTAIN_NETWORK_BUFFER_FROM_ISR(); + } + + return pxReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t vNetworkBufferReleaseFromISR( NetworkBufferDescriptor_t * const pxNetworkBuffer ) +{ +BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + /* Ensure the buffer is returned to the list of free buffers before the + counting semaphore is 'given' to say a buffer is available. */ + ipconfigBUFFER_ALLOC_LOCK_FROM_ISR(); + { + vListInsertEnd( &xFreeBuffersList, &( pxNetworkBuffer->xBufferListItem ) ); + } + ipconfigBUFFER_ALLOC_UNLOCK_FROM_ISR(); + + xSemaphoreGiveFromISR( xNetworkBufferSemaphore, &xHigherPriorityTaskWoken ); + iptraceNETWORK_BUFFER_RELEASED( pxNetworkBuffer ); + + return xHigherPriorityTaskWoken; +} +/*-----------------------------------------------------------*/ + +void vReleaseNetworkBufferAndDescriptor( NetworkBufferDescriptor_t * const pxNetworkBuffer ) +{ +BaseType_t xListItemAlreadyInFreeList; + + if( bIsValidNetworkDescriptor( pxNetworkBuffer ) == pdFALSE_UNSIGNED ) + { + FreeRTOS_debug_printf( ( "vReleaseNetworkBufferAndDescriptor: Invalid buffer %p\n", pxNetworkBuffer ) ); + return ; + } + /* Ensure the buffer is returned to the list of free buffers before the + counting semaphore is 'given' to say a buffer is available. */ + ipconfigBUFFER_ALLOC_LOCK(); + { + { + xListItemAlreadyInFreeList = listIS_CONTAINED_WITHIN( &xFreeBuffersList, &( pxNetworkBuffer->xBufferListItem ) ); + + if( xListItemAlreadyInFreeList == pdFALSE ) + { + vListInsertEnd( &xFreeBuffersList, &( pxNetworkBuffer->xBufferListItem ) ); + } + } + } + ipconfigBUFFER_ALLOC_UNLOCK(); + + if( xListItemAlreadyInFreeList ) + { + FreeRTOS_debug_printf( ( "vReleaseNetworkBufferAndDescriptor: %p ALREADY RELEASED (now %lu)\n", + pxNetworkBuffer, uxGetNumberOfFreeNetworkBuffers( ) ) ); + } + if( xListItemAlreadyInFreeList == pdFALSE ) + { + xSemaphoreGive( xNetworkBufferSemaphore ); + prvShowWarnings(); + if( xTCPWindowLoggingLevel > 3 ) + FreeRTOS_debug_printf( ( "BUF_PUT[%ld]: %p (%p) (now %lu)\n", + bIsValidNetworkDescriptor( pxNetworkBuffer ), + pxNetworkBuffer, pxNetworkBuffer->pucEthernetBuffer, + uxGetNumberOfFreeNetworkBuffers( ) ) ); + } + iptraceNETWORK_BUFFER_RELEASED( pxNetworkBuffer ); +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxGetMinimumFreeNetworkBuffers( void ) +{ + return uxMinimumFreeNetworkBuffers; +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxGetNumberOfFreeNetworkBuffers( void ) +{ + return listCURRENT_LIST_LENGTH( &xFreeBuffersList ); +} + +NetworkBufferDescriptor_t *pxResizeNetworkBufferWithDescriptor( NetworkBufferDescriptor_t * pxNetworkBuffer, size_t xNewSizeBytes ) +{ + /* In BufferAllocation_1.c all network buffer are allocated with a + maximum size of 'ipTOTAL_ETHERNET_FRAME_SIZE'.No need to resize the + network buffer. */ + ( void ) xNewSizeBytes; + return pxNetworkBuffer; +} + +/*#endif */ /* ipconfigINCLUDE_TEST_CODE */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/BufferManagement/BufferAllocation_2.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/BufferManagement/BufferAllocation_2.c new file mode 100644 index 0000000..5647ac6 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/BufferManagement/BufferAllocation_2.c @@ -0,0 +1,390 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/****************************************************************************** + * + * See the following web page for essential buffer allocation scheme usage and + * configuration details: + * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/Embedded_Ethernet_Buffer_Management.html + * + ******************************************************************************/ + +/* THIS FILE SHOULD NOT BE USED IF THE PROJECT INCLUDES A MEMORY ALLOCATOR +THAT WILL FRAGMENT THE HEAP MEMORY. For example, heap_2 must not be used, +heap_4 can be used. */ + + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_UDP_IP.h" +#include "FreeRTOS_IP_Private.h" +#include "NetworkInterface.h" +#include "NetworkBufferManagement.h" + +/* The obtained network buffer must be large enough to hold a packet that might +replace the packet that was requested to be sent. */ +#if ipconfigUSE_TCP == 1 + #define baMINIMAL_BUFFER_SIZE sizeof( TCPPacket_t ) +#else + #define baMINIMAL_BUFFER_SIZE sizeof( ARPPacket_t ) +#endif /* ipconfigUSE_TCP == 1 */ + +/*_RB_ This is too complex not to have an explanation. */ +#if defined( ipconfigETHERNET_MINIMUM_PACKET_BYTES ) + #define ASSERT_CONCAT_(a, b) a##b + #define ASSERT_CONCAT(a, b) ASSERT_CONCAT_(a, b) + #define STATIC_ASSERT(e) \ + ;enum { ASSERT_CONCAT(assert_line_, __LINE__) = 1/(!!(e)) } + + STATIC_ASSERT( ipconfigETHERNET_MINIMUM_PACKET_BYTES <= baMINIMAL_BUFFER_SIZE ); +#endif + +/* A list of free (available) NetworkBufferDescriptor_t structures. */ +static List_t xFreeBuffersList; + +/* Some statistics about the use of buffers. */ +static size_t uxMinimumFreeNetworkBuffers; + +/* Declares the pool of NetworkBufferDescriptor_t structures that are available +to the system. All the network buffers referenced from xFreeBuffersList exist +in this array. The array is not accessed directly except during initialisation, +when the xFreeBuffersList is filled (as all the buffers are free when the system +is booted). */ +static NetworkBufferDescriptor_t xNetworkBufferDescriptors[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ]; + +/* This constant is defined as false to let FreeRTOS_TCP_IP.c know that the +network buffers have a variable size: resizing may be necessary */ +const BaseType_t xBufferAllocFixedSize = pdFALSE; + +/* The semaphore used to obtain network buffers. */ +static SemaphoreHandle_t xNetworkBufferSemaphore = NULL; + +/*-----------------------------------------------------------*/ + +BaseType_t xNetworkBuffersInitialise( void ) +{ +BaseType_t xReturn, x; + + /* Only initialise the buffers and their associated kernel objects if they + have not been initialised before. */ + if( xNetworkBufferSemaphore == NULL ) + { + xNetworkBufferSemaphore = xSemaphoreCreateCounting( ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS, ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ); + configASSERT( xNetworkBufferSemaphore ); + + if( xNetworkBufferSemaphore != NULL ) + { + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + { + vQueueAddToRegistry( xNetworkBufferSemaphore, "NetBufSem" ); + } + #endif /* configQUEUE_REGISTRY_SIZE */ + + /* If the trace recorder code is included name the semaphore for viewing + in FreeRTOS+Trace. */ + #if( ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS == 1 ) + { + extern QueueHandle_t xNetworkEventQueue; + vTraceSetQueueName( xNetworkEventQueue, "IPStackEvent" ); + vTraceSetQueueName( xNetworkBufferSemaphore, "NetworkBufferCount" ); + } + #endif /* ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS == 1 */ + + vListInitialise( &xFreeBuffersList ); + + /* Initialise all the network buffers. No storage is allocated to + the buffers yet. */ + for( x = 0; x < ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS; x++ ) + { + /* Initialise and set the owner of the buffer list items. */ + xNetworkBufferDescriptors[ x ].pucEthernetBuffer = NULL; + vListInitialiseItem( &( xNetworkBufferDescriptors[ x ].xBufferListItem ) ); + listSET_LIST_ITEM_OWNER( &( xNetworkBufferDescriptors[ x ].xBufferListItem ), &xNetworkBufferDescriptors[ x ] ); + + /* Currently, all buffers are available for use. */ + vListInsert( &xFreeBuffersList, &( xNetworkBufferDescriptors[ x ].xBufferListItem ) ); + } + + uxMinimumFreeNetworkBuffers = ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS; + } + } + + if( xNetworkBufferSemaphore == NULL ) + { + xReturn = pdFAIL; + } + else + { + xReturn = pdPASS; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +uint8_t *pucGetNetworkBuffer( size_t *pxRequestedSizeBytes ) +{ +uint8_t *pucEthernetBuffer; +size_t xSize = *pxRequestedSizeBytes; + + if( xSize < baMINIMAL_BUFFER_SIZE ) + { + /* Buffers must be at least large enough to hold a TCP-packet with + headers, or an ARP packet, in case TCP is not included. */ + xSize = baMINIMAL_BUFFER_SIZE; + } + + /* Round up xSize to the nearest multiple of N bytes, + where N equals 'sizeof( size_t )'. */ + if( ( xSize & ( sizeof( size_t ) - 1u ) ) != 0u ) + { + xSize = ( xSize | ( sizeof( size_t ) - 1u ) ) + 1u; + } + *pxRequestedSizeBytes = xSize; + + /* Allocate a buffer large enough to store the requested Ethernet frame size + and a pointer to a network buffer structure (hence the addition of + ipBUFFER_PADDING bytes). */ + pucEthernetBuffer = ( uint8_t * ) pvPortMalloc( xSize + ipBUFFER_PADDING ); + configASSERT( pucEthernetBuffer ); + + if( pucEthernetBuffer != NULL ) + { + /* Enough space is left at the start of the buffer to place a pointer to + the network buffer structure that references this Ethernet buffer. + Return a pointer to the start of the Ethernet buffer itself. */ + pucEthernetBuffer += ipBUFFER_PADDING; + } + + return pucEthernetBuffer; +} +/*-----------------------------------------------------------*/ + +void vReleaseNetworkBuffer( uint8_t *pucEthernetBuffer ) +{ + /* There is space before the Ethernet buffer in which a pointer to the + network buffer that references this Ethernet buffer is stored. Remove the + space before freeing the buffer. */ + if( pucEthernetBuffer != NULL ) + { + pucEthernetBuffer -= ipBUFFER_PADDING; + vPortFree( ( void * ) pucEthernetBuffer ); + } +} +/*-----------------------------------------------------------*/ + +NetworkBufferDescriptor_t *pxGetNetworkBufferWithDescriptor( size_t xRequestedSizeBytes, TickType_t xBlockTimeTicks ) +{ +NetworkBufferDescriptor_t *pxReturn = NULL; +size_t uxCount; + + if( ( xRequestedSizeBytes != 0u ) && ( xRequestedSizeBytes < ( size_t ) baMINIMAL_BUFFER_SIZE ) ) + { + /* ARP packets can replace application packets, so the storage must be + at least large enough to hold an ARP. */ + xRequestedSizeBytes = baMINIMAL_BUFFER_SIZE; + } + + /* Add 2 bytes to xRequestedSizeBytes and round up xRequestedSizeBytes + to the nearest multiple of N bytes, where N equals 'sizeof( size_t )'. */ + xRequestedSizeBytes += 2u; + if( ( xRequestedSizeBytes & ( sizeof( size_t ) - 1u ) ) != 0u ) + { + xRequestedSizeBytes = ( xRequestedSizeBytes | ( sizeof( size_t ) - 1u ) ) + 1u; + } + + /* If there is a semaphore available, there is a network buffer available. */ + if( xSemaphoreTake( xNetworkBufferSemaphore, xBlockTimeTicks ) == pdPASS ) + { + /* Protect the structure as it is accessed from tasks and interrupts. */ + taskENTER_CRITICAL(); + { + pxReturn = ( NetworkBufferDescriptor_t * ) listGET_OWNER_OF_HEAD_ENTRY( &xFreeBuffersList ); + uxListRemove( &( pxReturn->xBufferListItem ) ); + } + taskEXIT_CRITICAL(); + + /* Reading UBaseType_t, no critical section needed. */ + uxCount = listCURRENT_LIST_LENGTH( &xFreeBuffersList ); + + if( uxMinimumFreeNetworkBuffers > uxCount ) + { + uxMinimumFreeNetworkBuffers = uxCount; + } + + /* Allocate storage of exactly the requested size to the buffer. */ + configASSERT( pxReturn->pucEthernetBuffer == NULL ); + if( xRequestedSizeBytes > 0 ) + { + /* Extra space is obtained so a pointer to the network buffer can + be stored at the beginning of the buffer. */ + pxReturn->pucEthernetBuffer = ( uint8_t * ) pvPortMalloc( xRequestedSizeBytes + ipBUFFER_PADDING ); + + if( pxReturn->pucEthernetBuffer == NULL ) + { + /* The attempt to allocate storage for the buffer payload failed, + so the network buffer structure cannot be used and must be + released. */ + vReleaseNetworkBufferAndDescriptor( pxReturn ); + pxReturn = NULL; + } + else + { + /* Store a pointer to the network buffer structure in the + buffer storage area, then move the buffer pointer on past the + stored pointer so the pointer value is not overwritten by the + application when the buffer is used. */ + *( ( NetworkBufferDescriptor_t ** ) ( pxReturn->pucEthernetBuffer ) ) = pxReturn; + pxReturn->pucEthernetBuffer += ipBUFFER_PADDING; + + /* Store the actual size of the allocated buffer, which may be + greater than the original requested size. */ + pxReturn->xDataLength = xRequestedSizeBytes; + + #if( ipconfigUSE_LINKED_RX_MESSAGES != 0 ) + { + /* make sure the buffer is not linked */ + pxReturn->pxNextBuffer = NULL; + } + #endif /* ipconfigUSE_LINKED_RX_MESSAGES */ + } + } + else + { + /* A descriptor is being returned without an associated buffer being + allocated. */ + } + } + + if( pxReturn == NULL ) + { + iptraceFAILED_TO_OBTAIN_NETWORK_BUFFER(); + } + else + { + iptraceNETWORK_BUFFER_OBTAINED( pxReturn ); + } + + return pxReturn; +} +/*-----------------------------------------------------------*/ + +void vReleaseNetworkBufferAndDescriptor( NetworkBufferDescriptor_t * const pxNetworkBuffer ) +{ +BaseType_t xListItemAlreadyInFreeList; + + /* Ensure the buffer is returned to the list of free buffers before the + counting semaphore is 'given' to say a buffer is available. Release the + storage allocated to the buffer payload. THIS FILE SHOULD NOT BE USED + IF THE PROJECT INCLUDES A MEMORY ALLOCATOR THAT WILL FRAGMENT THE HEAP + MEMORY. For example, heap_2 must not be used, heap_4 can be used. */ + vReleaseNetworkBuffer( pxNetworkBuffer->pucEthernetBuffer ); + pxNetworkBuffer->pucEthernetBuffer = NULL; + + taskENTER_CRITICAL(); + { + xListItemAlreadyInFreeList = listIS_CONTAINED_WITHIN( &xFreeBuffersList, &( pxNetworkBuffer->xBufferListItem ) ); + + if( xListItemAlreadyInFreeList == pdFALSE ) + { + vListInsertEnd( &xFreeBuffersList, &( pxNetworkBuffer->xBufferListItem ) ); + } + } + taskEXIT_CRITICAL(); + + /* + * Update the network state machine, unless the program fails to release its 'xNetworkBufferSemaphore'. + * The program should only try to release its semaphore if 'xListItemAlreadyInFreeList' is false. + */ + if( xListItemAlreadyInFreeList == pdFALSE ) + { + if ( xSemaphoreGive( xNetworkBufferSemaphore ) == pdTRUE ) + { + iptraceNETWORK_BUFFER_RELEASED( pxNetworkBuffer ); + } + } + else + { + iptraceNETWORK_BUFFER_RELEASED( pxNetworkBuffer ); + } +} +/*-----------------------------------------------------------*/ + +/* + * Returns the number of free network buffers + */ +UBaseType_t uxGetNumberOfFreeNetworkBuffers( void ) +{ + return listCURRENT_LIST_LENGTH( &xFreeBuffersList ); +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxGetMinimumFreeNetworkBuffers( void ) +{ + return uxMinimumFreeNetworkBuffers; +} +/*-----------------------------------------------------------*/ + +NetworkBufferDescriptor_t *pxResizeNetworkBufferWithDescriptor( NetworkBufferDescriptor_t * pxNetworkBuffer, size_t xNewSizeBytes ) +{ +size_t xOriginalLength; +uint8_t *pucBuffer; + + xOriginalLength = pxNetworkBuffer->xDataLength + ipBUFFER_PADDING; + xNewSizeBytes = xNewSizeBytes + ipBUFFER_PADDING; + + pucBuffer = pucGetNetworkBuffer( &( xNewSizeBytes ) ); + + if( pucBuffer == NULL ) + { + /* In case the allocation fails, return NULL. */ + pxNetworkBuffer = NULL; + } + else + { + pxNetworkBuffer->xDataLength = xNewSizeBytes; + if( xNewSizeBytes > xOriginalLength ) + { + xNewSizeBytes = xOriginalLength; + } + + memcpy( pucBuffer - ipBUFFER_PADDING, pxNetworkBuffer->pucEthernetBuffer - ipBUFFER_PADDING, xNewSizeBytes ); + vReleaseNetworkBuffer( pxNetworkBuffer->pucEthernetBuffer ); + pxNetworkBuffer->pucEthernetBuffer = pucBuffer; + } + + return pxNetworkBuffer; +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/GCC/pack_struct_end.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/GCC/pack_struct_end.h new file mode 100644 index 0000000..d61b8d0 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/GCC/pack_struct_end.h @@ -0,0 +1,46 @@ +/* +FreeRTOS+TCP V2.0.11 +Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + http://aws.amazon.com/freertos + http://www.FreeRTOS.org +*/ + +/***************************************************************************** + * + * See the following URL for an explanation of this file: + * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/Embedded_Compiler_Porting.html + * + *****************************************************************************/ +__attribute__( (packed) ); + + + + + + + + + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/GCC/pack_struct_start.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/GCC/pack_struct_start.h new file mode 100644 index 0000000..5a88f78 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/GCC/pack_struct_start.h @@ -0,0 +1,48 @@ +/* +FreeRTOS+TCP V2.0.11 +Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + http://aws.amazon.com/freertos + http://www.FreeRTOS.org +*/ + +/***************************************************************************** + * + * See the following URL for an explanation of this file: + * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/Embedded_Compiler_Porting.html + * + *****************************************************************************/ + +/* Nothing to do here. */ + + + + + + + + + + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/IAR/pack_struct_end.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/IAR/pack_struct_end.h new file mode 100644 index 0000000..85e6708 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/IAR/pack_struct_end.h @@ -0,0 +1,47 @@ +/* +FreeRTOS+TCP V2.0.11 +Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + http://aws.amazon.com/freertos + http://www.FreeRTOS.org +*/ + +/***************************************************************************** + * + * See the following URL for an explanation of this file: + * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/Embedded_Compiler_Porting.html + * + *****************************************************************************/ + +; + + + + + + + + + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/IAR/pack_struct_start.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/IAR/pack_struct_start.h new file mode 100644 index 0000000..15e6eb6 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/IAR/pack_struct_start.h @@ -0,0 +1,49 @@ +/* +FreeRTOS+TCP V2.0.11 +Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + http://aws.amazon.com/freertos + http://www.FreeRTOS.org +*/ + +/***************************************************************************** + * + * See the following URL for an explanation of this file: + * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/Embedded_Compiler_Porting.html + * + *****************************************************************************/ + +__packed + + + + + + + + + + + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/MSVC/pack_struct_end.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/MSVC/pack_struct_end.h new file mode 100644 index 0000000..19a0f39 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/MSVC/pack_struct_end.h @@ -0,0 +1,48 @@ +/* +FreeRTOS+TCP V2.0.11 +Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + http://aws.amazon.com/freertos + http://www.FreeRTOS.org +*/ + +/***************************************************************************** + * + * See the following URL for an explanation of this file: + * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/Embedded_Compiler_Porting.html + * + *****************************************************************************/ + +; +#pragma pack( pop ) + + + + + + + + + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/MSVC/pack_struct_start.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/MSVC/pack_struct_start.h new file mode 100644 index 0000000..54a3e68 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/MSVC/pack_struct_start.h @@ -0,0 +1,47 @@ +/* +FreeRTOS+TCP V2.0.11 +Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + http://aws.amazon.com/freertos + http://www.FreeRTOS.org +*/ + +/***************************************************************************** + * + * See the following URL for an explanation of this file: + * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/Embedded_Compiler_Porting.html + * + *****************************************************************************/ + +#pragma pack( push, 1 ) + + + + + + + + + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/Renesas/pack_struct_end.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/Renesas/pack_struct_end.h new file mode 100644 index 0000000..c8de043 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/Renesas/pack_struct_end.h @@ -0,0 +1,54 @@ +/* +FreeRTOS+TCP V2.0.11 +Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + http://aws.amazon.com/freertos + http://www.FreeRTOS.org +*/ + +/***************************************************************************** + * + * See the following URL for an explanation of this file: + * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/Embedded_Compiler_Porting.html + * + *****************************************************************************/ + + +#ifdef _SH + #ifdef __RENESAS__ + ; + #pragma unpack + #endif +#endif + + + + + + + + + + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/Renesas/pack_struct_start.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/Renesas/pack_struct_start.h new file mode 100644 index 0000000..55b2fd5 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/Renesas/pack_struct_start.h @@ -0,0 +1,53 @@ +/* +FreeRTOS+TCP V2.0.11 +Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + http://aws.amazon.com/freertos + http://www.FreeRTOS.org +*/ + +/***************************************************************************** + * + * See the following URL for an explanation of this file: + * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/Embedded_Compiler_Porting.html + * + *****************************************************************************/ + + +#ifdef _SH + #ifdef __RENESAS__ + #pragma pack 1 + #endif +#endif + + + + + + + + + + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/NetworkInterface.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/NetworkInterface.c new file mode 100644 index 0000000..7d83e07 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/NetworkInterface.c @@ -0,0 +1,649 @@ +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + + +/* Standard includes. */ +#include +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_IP_Private.h" +#include "NetworkBufferManagement.h" +#include "NetworkInterface.h" + +/* Some files from the Atmel Software Framework */ +/*_RB_ The SAM4E portable layer has three different header files called gmac.h! */ +#include "instance/gmac.h" +#include +#include + +#ifndef BMSR_LINK_STATUS + #define BMSR_LINK_STATUS 0x0004 //!< Link status +#endif + +#ifndef PHY_LS_HIGH_CHECK_TIME_MS + /* Check if the LinkSStatus in the PHY is still high after 15 seconds of not + receiving packets. */ + #define PHY_LS_HIGH_CHECK_TIME_MS 15000 +#endif + +#ifndef PHY_LS_LOW_CHECK_TIME_MS + /* Check if the LinkSStatus in the PHY is still low every second. */ + #define PHY_LS_LOW_CHECK_TIME_MS 1000 +#endif + +/* Interrupt events to process. Currently only the Rx event is processed +although code for other events is included to allow for possible future +expansion. */ +#define EMAC_IF_RX_EVENT 1UL +#define EMAC_IF_TX_EVENT 2UL +#define EMAC_IF_ERR_EVENT 4UL +#define EMAC_IF_ALL_EVENT ( EMAC_IF_RX_EVENT | EMAC_IF_TX_EVENT | EMAC_IF_ERR_EVENT ) + +#define ETHERNET_CONF_PHY_ADDR BOARD_GMAC_PHY_ADDR + +#define HZ_PER_MHZ ( 1000000UL ) + +#ifndef EMAC_MAX_BLOCK_TIME_MS + #define EMAC_MAX_BLOCK_TIME_MS 100ul +#endif + +#if !defined( GMAC_USES_TX_CALLBACK ) || ( GMAC_USES_TX_CALLBACK != 1 ) + #error Please define GMAC_USES_TX_CALLBACK as 1 +#endif + +#if( ipconfigZERO_COPY_RX_DRIVER != 0 ) + #warning The EMAC of SAM4E has fixed-size RX buffers so ZERO_COPY_RX is not possible +#endif + +/* Default the size of the stack used by the EMAC deferred handler task to 4x +the size of the stack used by the idle task - but allow this to be overridden in +FreeRTOSConfig.h as configMINIMAL_STACK_SIZE is a user definable constant. */ +#ifndef configEMAC_TASK_STACK_SIZE + #define configEMAC_TASK_STACK_SIZE ( 4 * configMINIMAL_STACK_SIZE ) +#endif + +/*-----------------------------------------------------------*/ + +/* + * Wait a fixed time for the link status to indicate the network is up. + */ +static BaseType_t xGMACWaitLS( TickType_t xMaxTime ); + +#if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM == 1 ) && ( ipconfigHAS_TX_CRC_OFFLOADING == 0 ) + void vGMACGenerateChecksum( uint8_t *apBuffer ); +#endif + +/* + * Called from the ASF GMAC driver. + */ +static void prvRxCallback( uint32_t ulStatus ); +static void prvTxCallback( uint32_t ulStatus, uint8_t *puc_buffer ); + +/* + * A deferred interrupt handler task that processes GMAC interrupts. + */ +static void prvEMACHandlerTask( void *pvParameters ); + +/* + * Initialise the ASF GMAC driver. + */ +static BaseType_t prvGMACInit( void ); + +/* + * Try to obtain an Rx packet from the hardware. + */ +static uint32_t prvEMACRxPoll( void ); + +/*-----------------------------------------------------------*/ + +/* Bit map of outstanding ETH interrupt events for processing. Currently only +the Rx interrupt is handled, although code is included for other events to +enable future expansion. */ +static volatile uint32_t ulISREvents; + +/* A copy of PHY register 1: 'PHY_REG_01_BMSR' */ +static uint32_t ulPHYLinkStatus = 0; +static volatile BaseType_t xGMACSwitchRequired; + +/* ethernet_phy_addr: the address of the PHY in use. +Atmel was a bit ambiguous about it so the address will be stored +in this variable, see ethernet_phy.c */ +extern int ethernet_phy_addr; + +/* LLMNR multicast address. */ +static const uint8_t llmnr_mac_address[] = { 0x01, 0x00, 0x5E, 0x00, 0x00, 0xFC }; + +/* The GMAC object as defined by the ASF drivers. */ +static gmac_device_t gs_gmac_dev; + +/* MAC address to use. */ +extern const uint8_t ucMACAddress[ 6 ]; + +/* Holds the handle of the task used as a deferred interrupt processor. The +handle is used so direct notifications can be sent to the task for all EMAC/DMA +related interrupts. */ +TaskHandle_t xEMACTaskHandle = NULL; + +static QueueHandle_t xTxBufferQueue; +int tx_release_count[ 4 ]; + +/* xTXDescriptorSemaphore is a counting semaphore with +a maximum count of GMAC_TX_BUFFERS, which is the number of +DMA TX descriptors. */ +static SemaphoreHandle_t xTXDescriptorSemaphore = NULL; + +/*-----------------------------------------------------------*/ + +/* + * GMAC interrupt handler. + */ +void GMAC_Handler(void) +{ + xGMACSwitchRequired = pdFALSE; + + /* gmac_handler() may call prvRxCallback() which may change + the value of xGMACSwitchRequired. */ + gmac_handler( &gs_gmac_dev ); + + if( xGMACSwitchRequired != pdFALSE ) + { + portEND_SWITCHING_ISR( xGMACSwitchRequired ); + } +} +/*-----------------------------------------------------------*/ + +static void prvRxCallback( uint32_t ulStatus ) +{ + if( ( ( ulStatus & GMAC_RSR_REC ) != 0 ) && ( xEMACTaskHandle != NULL ) ) + { + /* let the prvEMACHandlerTask know that there was an RX event. */ + ulISREvents |= EMAC_IF_RX_EVENT; + /* Only an RX interrupt can wakeup prvEMACHandlerTask. */ + vTaskNotifyGiveFromISR( xEMACTaskHandle, ( BaseType_t * ) &xGMACSwitchRequired ); + } +} +/*-----------------------------------------------------------*/ + +static void prvTxCallback( uint32_t ulStatus, uint8_t *puc_buffer ) +{ + if( ( xTxBufferQueue != NULL ) && ( xEMACTaskHandle != NULL ) ) + { + /* let the prvEMACHandlerTask know that there was an RX event. */ + ulISREvents |= EMAC_IF_TX_EVENT; + + vTaskNotifyGiveFromISR( xEMACTaskHandle, ( BaseType_t * ) &xGMACSwitchRequired ); + xQueueSendFromISR( xTxBufferQueue, &puc_buffer, ( BaseType_t * ) &xGMACSwitchRequired ); + tx_release_count[ 2 ]++; + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xNetworkInterfaceInitialise( void ) +{ +const TickType_t x5_Seconds = 5000UL; + + if( xEMACTaskHandle == NULL ) + { + prvGMACInit(); + + /* Wait at most 5 seconds for a Link Status in the PHY. */ + xGMACWaitLS( pdMS_TO_TICKS( x5_Seconds ) ); + + /* The handler task is created at the highest possible priority to + ensure the interrupt handler can return directly to it. */ + xTaskCreate( prvEMACHandlerTask, "EMAC", configEMAC_TASK_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, &xEMACTaskHandle ); + configASSERT( xEMACTaskHandle ); + } + + if( xTxBufferQueue == NULL ) + { + xTxBufferQueue = xQueueCreate( GMAC_TX_BUFFERS, sizeof( void * ) ); + configASSERT( xTxBufferQueue ); + } + + if( xTXDescriptorSemaphore == NULL ) + { + xTXDescriptorSemaphore = xSemaphoreCreateCounting( ( UBaseType_t ) GMAC_TX_BUFFERS, ( UBaseType_t ) GMAC_TX_BUFFERS ); + configASSERT( xTXDescriptorSemaphore ); + } + /* When returning non-zero, the stack will become active and + start DHCP (in configured) */ + return ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != 0; +} +/*-----------------------------------------------------------*/ + +BaseType_t xGetPhyLinkStatus( void ) +{ +BaseType_t xResult; + + /* This function returns true if the Link Status in the PHY is high. */ + if( ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != 0 ) + { + xResult = pdTRUE; + } + else + { + xResult = pdFALSE; + } + + return xResult; +} +/*-----------------------------------------------------------*/ + +BaseType_t xNetworkInterfaceOutput( NetworkBufferDescriptor_t * const pxDescriptor, BaseType_t bReleaseAfterSend ) +{ +/* Do not wait too long for a free TX DMA buffer. */ +const TickType_t xBlockTimeTicks = pdMS_TO_TICKS( 50u ); + + do { + if( ( ulPHYLinkStatus & BMSR_LINK_STATUS ) == 0 ) + { + /* Do not attempt to send packets as long as the Link Status is low. */ + break; + } + if( xTXDescriptorSemaphore == NULL ) + { + /* Semaphore has not been created yet? */ + break; + } + if( xSemaphoreTake( xTXDescriptorSemaphore, xBlockTimeTicks ) != pdPASS ) + { + /* Time-out waiting for a free TX descriptor. */ + tx_release_count[ 3 ]++; + break; + } + #if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + { + /* Confirm that the pxDescriptor may be kept by the driver. */ + configASSERT( bReleaseAfterSend != pdFALSE ); + } + #endif /* ipconfigZERO_COPY_TX_DRIVER */ + + gmac_dev_write( &gs_gmac_dev, (void *)pxDescriptor->pucEthernetBuffer, pxDescriptor->xDataLength, prvTxCallback ); + + #if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + { + /* Confirm that the pxDescriptor may be kept by the driver. */ + bReleaseAfterSend = pdFALSE; + } + #endif /* ipconfigZERO_COPY_TX_DRIVER */ + /* Not interested in a call-back after TX. */ + iptraceNETWORK_INTERFACE_TRANSMIT(); + } while( 0 ); + + if( bReleaseAfterSend != pdFALSE ) + { + vReleaseNetworkBufferAndDescriptor( pxDescriptor ); + } + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvGMACInit( void ) +{ +uint32_t ncfgr; + + gmac_options_t gmac_option; + + memset( &gmac_option, '\0', sizeof( gmac_option ) ); + gmac_option.uc_copy_all_frame = 0; + gmac_option.uc_no_boardcast = 0; + memcpy( gmac_option.uc_mac_addr, ucMACAddress, sizeof( gmac_option.uc_mac_addr ) ); + + gs_gmac_dev.p_hw = GMAC; + gmac_dev_init( GMAC, &gs_gmac_dev, &gmac_option ); + + NVIC_SetPriority( GMAC_IRQn, configMAC_INTERRUPT_PRIORITY ); + NVIC_EnableIRQ( GMAC_IRQn ); + + /* Contact the Ethernet PHY and store it's address in 'ethernet_phy_addr' */ + ethernet_phy_init( GMAC, ETHERNET_CONF_PHY_ADDR, sysclk_get_cpu_hz() ); + + ethernet_phy_auto_negotiate( GMAC, ethernet_phy_addr ); + ethernet_phy_set_link( GMAC, ethernet_phy_addr, 1 ); + + /* The GMAC driver will call a hook prvRxCallback(), which + in turn will wake-up the task by calling vTaskNotifyGiveFromISR() */ + gmac_dev_set_rx_callback( &gs_gmac_dev, prvRxCallback ); + gmac_set_address( GMAC, 1, (uint8_t*)llmnr_mac_address ); + + ncfgr = GMAC_NCFGR_SPD | GMAC_NCFGR_FD; + + GMAC->GMAC_NCFGR = ( GMAC->GMAC_NCFGR & ~( GMAC_NCFGR_SPD | GMAC_NCFGR_FD ) ) | ncfgr; + + return 1; +} +/*-----------------------------------------------------------*/ + +static inline unsigned long ulReadMDIO( unsigned /*short*/ usAddress ) +{ +uint32_t ulValue, ulReturn; +int rc; + + gmac_enable_management( GMAC, 1 ); + rc = gmac_phy_read( GMAC, ethernet_phy_addr, usAddress, &ulValue ); + gmac_enable_management( GMAC, 0 ); + if( rc == GMAC_OK ) + { + ulReturn = ulValue; + } + else + { + ulReturn = 0UL; + } + + return ulReturn; +} +/*-----------------------------------------------------------*/ + +static BaseType_t xGMACWaitLS( TickType_t xMaxTime ) +{ +TickType_t xStartTime = xTaskGetTickCount(); +TickType_t xEndTime; +BaseType_t xReturn; +const TickType_t xShortTime = pdMS_TO_TICKS( 100UL ); + + for( ;; ) + { + xEndTime = xTaskGetTickCount(); + + if( ( xEndTime - xStartTime ) > xMaxTime ) + { + /* Wated more than xMaxTime, return. */ + xReturn = pdFALSE; + break; + } + + /* Check the link status again. */ + ulPHYLinkStatus = ulReadMDIO( PHY_REG_01_BMSR ); + + if( ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != 0 ) + { + /* Link is up - return. */ + xReturn = pdTRUE; + break; + } + + /* Link is down - wait in the Blocked state for a short while (to allow + other tasks to execute) before checking again. */ + vTaskDelay( xShortTime ); + } + + FreeRTOS_printf( ( "xGMACWaitLS: %ld (PHY %d) freq %lu Mz\n", + xReturn, + ethernet_phy_addr, + sysclk_get_cpu_hz() / HZ_PER_MHZ ) ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +//#if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM == 1 ) && ( ipconfigHAS_TX_CRC_OFFLOADING == 0 ) + + void vGMACGenerateChecksum( uint8_t *apBuffer ) + { + ProtocolPacket_t *xProtPacket = (ProtocolPacket_t *)apBuffer; + + if ( xProtPacket->xTCPPacket.xEthernetHeader.usFrameType == ipIPv4_FRAME_TYPE ) + { + IPHeader_t *pxIPHeader = &( xProtPacket->xTCPPacket.xIPHeader ); + + /* Calculate the IP header checksum. */ + pxIPHeader->usHeaderChecksum = 0x00; + pxIPHeader->usHeaderChecksum = usGenerateChecksum( 0u, ( uint8_t * ) &( pxIPHeader->ucVersionHeaderLength ), ipSIZE_OF_IPv4_HEADER ); + pxIPHeader->usHeaderChecksum = ~FreeRTOS_htons( pxIPHeader->usHeaderChecksum ); + + /* Calculate the TCP checksum for an outgoing packet. */ + usGenerateProtocolChecksum( ( uint8_t * ) apBuffer, pdTRUE ); + } + } + +//#endif +/*-----------------------------------------------------------*/ + +static uint32_t prvEMACRxPoll( void ) +{ +unsigned char *pucUseBuffer; +uint32_t ulReceiveCount, ulResult, ulReturnValue = 0; +static NetworkBufferDescriptor_t *pxNextNetworkBufferDescriptor = NULL; +const UBaseType_t xMinDescriptorsToLeave = 2UL; +const TickType_t xBlockTime = pdMS_TO_TICKS( 100UL ); +static IPStackEvent_t xRxEvent = { eNetworkRxEvent, NULL }; + + for( ;; ) + { + /* If pxNextNetworkBufferDescriptor was not left pointing at a valid + descriptor then allocate one now. */ + if( ( pxNextNetworkBufferDescriptor == NULL ) && ( uxGetNumberOfFreeNetworkBuffers() > xMinDescriptorsToLeave ) ) + { + pxNextNetworkBufferDescriptor = pxGetNetworkBufferWithDescriptor( ipTOTAL_ETHERNET_FRAME_SIZE, xBlockTime ); + } + + if( pxNextNetworkBufferDescriptor != NULL ) + { + /* Point pucUseBuffer to the buffer pointed to by the descriptor. */ + pucUseBuffer = ( unsigned char* ) ( pxNextNetworkBufferDescriptor->pucEthernetBuffer - ipconfigPACKET_FILLER_SIZE ); + } + else + { + /* As long as pxNextNetworkBufferDescriptor is NULL, the incoming + messages will be flushed and ignored. */ + pucUseBuffer = NULL; + } + + /* Read the next packet from the hardware into pucUseBuffer. */ + ulResult = gmac_dev_read( &gs_gmac_dev, pucUseBuffer, ipTOTAL_ETHERNET_FRAME_SIZE, &ulReceiveCount ); + + if( ( ulResult != GMAC_OK ) || ( ulReceiveCount == 0 ) ) + { + /* No data from the hardware. */ + break; + } + + if( pxNextNetworkBufferDescriptor == NULL ) + { + /* Data was read from the hardware, but no descriptor was available + for it, so it will be dropped. */ + iptraceETHERNET_RX_EVENT_LOST(); + continue; + } + + iptraceNETWORK_INTERFACE_RECEIVE(); + pxNextNetworkBufferDescriptor->xDataLength = ( size_t ) ulReceiveCount; + xRxEvent.pvData = ( void * ) pxNextNetworkBufferDescriptor; + + /* Send the descriptor to the IP task for processing. */ + if( xSendEventStructToIPTask( &xRxEvent, xBlockTime ) != pdTRUE ) + { + /* The buffer could not be sent to the stack so must be released + again. */ + vReleaseNetworkBufferAndDescriptor( pxNextNetworkBufferDescriptor ); + iptraceETHERNET_RX_EVENT_LOST(); + FreeRTOS_printf( ( "prvEMACRxPoll: Can not queue return packet!\n" ) ); + } + + /* Now the buffer has either been passed to the IP-task, + or it has been released in the code above. */ + pxNextNetworkBufferDescriptor = NULL; + ulReturnValue++; + } + + return ulReturnValue; +} +/*-----------------------------------------------------------*/ + +void vCheckBuffersAndQueue( void ) +{ +static UBaseType_t uxLastMinBufferCount = 0; +#if( ipconfigCHECK_IP_QUEUE_SPACE != 0 ) + static UBaseType_t uxLastMinQueueSpace; +#endif +static UBaseType_t uxCurrentCount; + + #if( ipconfigCHECK_IP_QUEUE_SPACE != 0 ) + { + uxCurrentCount = uxGetMinimumIPQueueSpace(); + if( uxLastMinQueueSpace != uxCurrentCount ) + { + /* The logging produced below may be helpful + while tuning +TCP: see how many buffers are in use. */ + uxLastMinQueueSpace = uxCurrentCount; + FreeRTOS_printf( ( "Queue space: lowest %lu\n", uxCurrentCount ) ); + } + } + #endif /* ipconfigCHECK_IP_QUEUE_SPACE */ + uxCurrentCount = uxGetMinimumFreeNetworkBuffers(); + if( uxLastMinBufferCount != uxCurrentCount ) + { + /* The logging produced below may be helpful + while tuning +TCP: see how many buffers are in use. */ + uxLastMinBufferCount = uxCurrentCount; + FreeRTOS_printf( ( "Network buffers: %lu lowest %lu\n", + uxGetNumberOfFreeNetworkBuffers(), uxCurrentCount ) ); + } + +} + +static void prvEMACHandlerTask( void *pvParameters ) +{ +TimeOut_t xPhyTime; +TickType_t xPhyRemTime; +UBaseType_t uxCount; +#if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + NetworkBufferDescriptor_t *pxBuffer; +#endif +uint8_t *pucBuffer; +BaseType_t xResult = 0; +uint32_t xStatus; +const TickType_t ulMaxBlockTime = pdMS_TO_TICKS( EMAC_MAX_BLOCK_TIME_MS ); + + /* Remove compiler warnings about unused parameters. */ + ( void ) pvParameters; + + configASSERT( xEMACTaskHandle ); + + vTaskSetTimeOutState( &xPhyTime ); + xPhyRemTime = pdMS_TO_TICKS( PHY_LS_LOW_CHECK_TIME_MS ); + + for( ;; ) + { + vCheckBuffersAndQueue(); + + if( ( ulISREvents & EMAC_IF_ALL_EVENT ) == 0 ) + { + /* No events to process now, wait for the next. */ + ulTaskNotifyTake( pdFALSE, ulMaxBlockTime ); + } + + if( ( ulISREvents & EMAC_IF_RX_EVENT ) != 0 ) + { + ulISREvents &= ~EMAC_IF_RX_EVENT; + + /* Wait for the EMAC interrupt to indicate that another packet has been + received. */ + xResult = prvEMACRxPoll(); + } + + if( ( ulISREvents & EMAC_IF_TX_EVENT ) != 0 ) + { + /* Future extension: code to release TX buffers if zero-copy is used. */ + ulISREvents &= ~EMAC_IF_TX_EVENT; + while( xQueueReceive( xTxBufferQueue, &pucBuffer, 0 ) != pdFALSE ) + { + #if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + { + pxBuffer = pxPacketBuffer_to_NetworkBuffer( pucBuffer ); + if( pxBuffer != NULL ) + { + vReleaseNetworkBufferAndDescriptor( pxBuffer ); + tx_release_count[ 0 ]++; + } + else + { + tx_release_count[ 1 ]++; + } + } + #else + { + tx_release_count[ 0 ]++; + } + #endif + uxCount = uxQueueMessagesWaiting( ( QueueHandle_t ) xTXDescriptorSemaphore ); + if( uxCount < GMAC_TX_BUFFERS ) + { + /* Tell the counting semaphore that one more TX descriptor is available. */ + xSemaphoreGive( xTXDescriptorSemaphore ); + } + } + } + + if( ( ulISREvents & EMAC_IF_ERR_EVENT ) != 0 ) + { + /* Future extension: logging about errors that occurred. */ + ulISREvents &= ~EMAC_IF_ERR_EVENT; + } + + if( xResult > 0 ) + { + /* A packet was received. No need to check for the PHY status now, + but set a timer to check it later on. */ + vTaskSetTimeOutState( &xPhyTime ); + xPhyRemTime = pdMS_TO_TICKS( PHY_LS_HIGH_CHECK_TIME_MS ); + xResult = 0; + } + else if( xTaskCheckForTimeOut( &xPhyTime, &xPhyRemTime ) != pdFALSE ) + { + /* Check the link status again. */ + xStatus = ulReadMDIO( PHY_REG_01_BMSR ); + + if( ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != ( xStatus & BMSR_LINK_STATUS ) ) + { + ulPHYLinkStatus = xStatus; + FreeRTOS_printf( ( "prvEMACHandlerTask: PHY LS now %d\n", ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != 0 ) ); + } + + vTaskSetTimeOutState( &xPhyTime ); + if( ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != 0 ) + { + xPhyRemTime = pdMS_TO_TICKS( PHY_LS_HIGH_CHECK_TIME_MS ); + } + else + { + xPhyRemTime = pdMS_TO_TICKS( PHY_LS_LOW_CHECK_TIME_MS ); + } + } + } +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/component/gmac.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/component/gmac.h new file mode 100644 index 0000000..6eb069f --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/component/gmac.h @@ -0,0 +1,746 @@ +/** + * \file + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM4E_GMAC_COMPONENT_ +#define _SAM4E_GMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Gigabit Ethernet MAC */ +/* ============================================================================= */ +/** \addtogroup SAM4E_GMAC Gigabit Ethernet MAC */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief GmacSa hardware registers */ +typedef struct { + RwReg GMAC_SAB; /**< \brief (GmacSa Offset: 0x0) Specific Address 1 Bottom [31:0] Register */ + RwReg GMAC_SAT; /**< \brief (GmacSa Offset: 0x4) Specific Address 1 Top [47:32] Register */ +} GmacSa; +/** \brief Gmac hardware registers */ +#define GMACSA_NUMBER 4 +typedef struct { + RwReg GMAC_NCR; /**< \brief (Gmac Offset: 0x000) Network Control Register */ + RwReg GMAC_NCFGR; /**< \brief (Gmac Offset: 0x004) Network Configuration Register */ + RoReg GMAC_NSR; /**< \brief (Gmac Offset: 0x008) Network Status Register */ + RwReg GMAC_UR; /**< \brief (Gmac Offset: 0x00C) User Register */ + RwReg GMAC_DCFGR; /**< \brief (Gmac Offset: 0x010) DMA Configuration Register */ + RwReg GMAC_TSR; /**< \brief (Gmac Offset: 0x014) Transmit Status Register */ + RwReg GMAC_RBQB; /**< \brief (Gmac Offset: 0x018) Receive Buffer Queue Base Address */ + RwReg GMAC_TBQB; /**< \brief (Gmac Offset: 0x01C) Transmit Buffer Queue Base Address */ + RwReg GMAC_RSR; /**< \brief (Gmac Offset: 0x020) Receive Status Register */ + RoReg GMAC_ISR; /**< \brief (Gmac Offset: 0x024) Interrupt Status Register */ + WoReg GMAC_IER; /**< \brief (Gmac Offset: 0x028) Interrupt Enable Register */ + WoReg GMAC_IDR; /**< \brief (Gmac Offset: 0x02C) Interrupt Disable Register */ + RoReg GMAC_IMR; /**< \brief (Gmac Offset: 0x030) Interrupt Mask Register */ + RwReg GMAC_MAN; /**< \brief (Gmac Offset: 0x034) PHY Maintenance Register */ + RoReg GMAC_RPQ; /**< \brief (Gmac Offset: 0x038) Received Pause Quantum Register */ + RwReg GMAC_TPQ; /**< \brief (Gmac Offset: 0x03C) Transmit Pause Quantum Register */ + RwReg GMAC_TPSF; /**< \brief (Gmac Offset: 0x040) TX Partial Store and Forward Register */ + RwReg GMAC_RPSF; /**< \brief (Gmac Offset: 0x044) RX Partial Store and Forward Register */ + RoReg Reserved1[14]; + RwReg GMAC_HRB; /**< \brief (Gmac Offset: 0x080) Hash Register Bottom [31:0] */ + RwReg GMAC_HRT; /**< \brief (Gmac Offset: 0x084) Hash Register Top [63:32] */ + GmacSa GMAC_SA[GMACSA_NUMBER]; /**< \brief (Gmac Offset: 0x088) 1 .. 4 */ + RwReg GMAC_TIDM[4]; /**< \brief (Gmac Offset: 0x0A8) Type ID Match 1 Register */ + RwReg GMAC_WOL; /**< \brief (Gmac Offset: 0x0B8) Wake on LAN Register */ + RwReg GMAC_IPGS; /**< \brief (Gmac Offset: 0x0BC) IPG Stretch Register */ + RwReg GMAC_SVLAN; /**< \brief (Gmac Offset: 0x0C0) Stacked VLAN Register */ + RwReg GMAC_TPFCP; /**< \brief (Gmac Offset: 0x0C4) Transmit PFC Pause Register */ + RwReg GMAC_SAMB1; /**< \brief (Gmac Offset: 0x0C8) Specific Address 1 Mask Bottom [31:0] Register */ + RwReg GMAC_SAMT1; /**< \brief (Gmac Offset: 0x0CC) Specific Address 1 Mask Top [47:32] Register */ + RoReg Reserved2[12]; + RoReg GMAC_OTLO; /**< \brief (Gmac Offset: 0x100) Octets Transmitted [31:0] Register */ + RoReg GMAC_OTHI; /**< \brief (Gmac Offset: 0x104) Octets Transmitted [47:32] Register */ + RoReg GMAC_FT; /**< \brief (Gmac Offset: 0x108) Frames Transmitted Register */ + RoReg GMAC_BCFT; /**< \brief (Gmac Offset: 0x10C) Broadcast Frames Transmitted Register */ + RoReg GMAC_MFT; /**< \brief (Gmac Offset: 0x110) Multicast Frames Transmitted Register */ + RoReg GMAC_PFT; /**< \brief (Gmac Offset: 0x114) Pause Frames Transmitted Register */ + RoReg GMAC_BFT64; /**< \brief (Gmac Offset: 0x118) 64 Byte Frames Transmitted Register */ + RoReg GMAC_TBFT127; /**< \brief (Gmac Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register */ + RoReg GMAC_TBFT255; /**< \brief (Gmac Offset: 0x120) 128 to 255 Byte Frames Transmitted Register */ + RoReg GMAC_TBFT511; /**< \brief (Gmac Offset: 0x124) 256 to 511 Byte Frames Transmitted Register */ + RoReg GMAC_TBFT1023; /**< \brief (Gmac Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register */ + RoReg GMAC_TBFT1518; /**< \brief (Gmac Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register */ + RoReg GMAC_GTBFT1518; /**< \brief (Gmac Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register */ + RoReg GMAC_TUR; /**< \brief (Gmac Offset: 0x134) Transmit Under Runs Register */ + RoReg GMAC_SCF; /**< \brief (Gmac Offset: 0x138) Single Collision Frames Register */ + RoReg GMAC_MCF; /**< \brief (Gmac Offset: 0x13C) Multiple Collision Frames Register */ + RoReg GMAC_EC; /**< \brief (Gmac Offset: 0x140) Excessive Collisions Register */ + RoReg GMAC_LC; /**< \brief (Gmac Offset: 0x144) Late Collisions Register */ + RoReg GMAC_DTF; /**< \brief (Gmac Offset: 0x148) Deferred Transmission Frames Register */ + RoReg GMAC_CSE; /**< \brief (Gmac Offset: 0x14C) Carrier Sense Errors Register */ + RoReg GMAC_ORLO; /**< \brief (Gmac Offset: 0x150) Octets Received [31:0] Received */ + RoReg GMAC_ORHI; /**< \brief (Gmac Offset: 0x154) Octets Received [47:32] Received */ + RoReg GMAC_FR; /**< \brief (Gmac Offset: 0x158) Frames Received Register */ + RoReg GMAC_BCFR; /**< \brief (Gmac Offset: 0x15C) Broadcast Frames Received Register */ + RoReg GMAC_MFR; /**< \brief (Gmac Offset: 0x160) Multicast Frames Received Register */ + RoReg GMAC_PFR; /**< \brief (Gmac Offset: 0x164) Pause Frames Received Register */ + RoReg GMAC_BFR64; /**< \brief (Gmac Offset: 0x168) 64 Byte Frames Received Register */ + RoReg GMAC_TBFR127; /**< \brief (Gmac Offset: 0x16C) 65 to 127 Byte Frames Received Register */ + RoReg GMAC_TBFR255; /**< \brief (Gmac Offset: 0x170) 128 to 255 Byte Frames Received Register */ + RoReg GMAC_TBFR511; /**< \brief (Gmac Offset: 0x174) 256 to 511Byte Frames Received Register */ + RoReg GMAC_TBFR1023; /**< \brief (Gmac Offset: 0x178) 512 to 1023 Byte Frames Received Register */ + RoReg GMAC_TBFR1518; /**< \brief (Gmac Offset: 0x17C) 1024 to 1518 Byte Frames Received Register */ + RoReg GMAC_TMXBFR; /**< \brief (Gmac Offset: 0x180) 1519 to Maximum Byte Frames Received Register */ + RoReg GMAC_UFR; /**< \brief (Gmac Offset: 0x184) Undersize Frames Received Register */ + RoReg GMAC_OFR; /**< \brief (Gmac Offset: 0x188) Oversize Frames Received Register */ + RoReg GMAC_JR; /**< \brief (Gmac Offset: 0x18C) Jabbers Received Register */ + RoReg GMAC_FCSE; /**< \brief (Gmac Offset: 0x190) Frame Check Sequence Errors Register */ + RoReg GMAC_LFFE; /**< \brief (Gmac Offset: 0x194) Length Field Frame Errors Register */ + RoReg GMAC_RSE; /**< \brief (Gmac Offset: 0x198) Receive Symbol Errors Register */ + RoReg GMAC_AE; /**< \brief (Gmac Offset: 0x19C) Alignment Errors Register */ + RoReg GMAC_RRE; /**< \brief (Gmac Offset: 0x1A0) Receive Resource Errors Register */ + RoReg GMAC_ROE; /**< \brief (Gmac Offset: 0x1A4) Receive Overrun Register */ + RoReg GMAC_IHCE; /**< \brief (Gmac Offset: 0x1A8) IP Header Checksum Errors Register */ + RoReg GMAC_TCE; /**< \brief (Gmac Offset: 0x1AC) TCP Checksum Errors Register */ + RoReg GMAC_UCE; /**< \brief (Gmac Offset: 0x1B0) UDP Checksum Errors Register */ + RoReg Reserved3[5]; + RwReg GMAC_TSSS; /**< \brief (Gmac Offset: 0x1C8) 1588 Timer Sync Strobe Seconds Register */ + RwReg GMAC_TSSN; /**< \brief (Gmac Offset: 0x1CC) 1588 Timer Sync Strobe Nanoseconds Register */ + RwReg GMAC_TS; /**< \brief (Gmac Offset: 0x1D0) 1588 Timer Seconds Register */ + RwReg GMAC_TN; /**< \brief (Gmac Offset: 0x1D4) 1588 Timer Nanoseconds Register */ + WoReg GMAC_TA; /**< \brief (Gmac Offset: 0x1D8) 1588 Timer Adjust Register */ + RwReg GMAC_TI; /**< \brief (Gmac Offset: 0x1DC) 1588 Timer Increment Register */ + RoReg GMAC_EFTS; /**< \brief (Gmac Offset: 0x1E0) PTP Event Frame Transmitted Seconds */ + RoReg GMAC_EFTN; /**< \brief (Gmac Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds */ + RoReg GMAC_EFRS; /**< \brief (Gmac Offset: 0x1E8) PTP Event Frame Received Seconds */ + RoReg GMAC_EFRN; /**< \brief (Gmac Offset: 0x1EC) PTP Event Frame Received Nanoseconds */ + RoReg GMAC_PEFTS; /**< \brief (Gmac Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds */ + RoReg GMAC_PEFTN; /**< \brief (Gmac Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds */ + RoReg GMAC_PEFRS; /**< \brief (Gmac Offset: 0x1F8) PTP Peer Event Frame Received Seconds */ + RoReg GMAC_PEFRN; /**< \brief (Gmac Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds */ + RoReg Reserved4[128]; + RoReg GMAC_ISRPQ[7]; /**< \brief (Gmac Offset: 0x400) Interrupt Status Register Priority Queue */ + RoReg Reserved5[9]; + RwReg GMAC_TBQBAPQ[7]; /**< \brief (Gmac Offset: 0x440) Transmit Buffer Queue Base Address Priority Queue */ + RoReg Reserved6[9]; + RwReg GMAC_RBQBAPQ[7]; /**< \brief (Gmac Offset: 0x480) Receive Buffer Queue Base Address Priority Queue */ + RoReg Reserved7[1]; + RwReg GMAC_RBSRPQ[7]; /**< \brief (Gmac Offset: 0x4A0) Receive Buffer Size Register Priority Queue */ + RoReg Reserved8[17]; + RwReg GMAC_ST1RPQ[16]; /**< \brief (Gmac Offset: 0x500) Screening Type1 Register Priority Queue */ + RwReg GMAC_ST2RPQ[16]; /**< \brief (Gmac Offset: 0x540) Screening Type2 Register Priority Queue */ + RoReg Reserved9[32]; + WoReg GMAC_IERPQ[7]; /**< \brief (Gmac Offset: 0x600) Interrupt Enable Register Priority Queue */ + RoReg Reserved10[1]; + WoReg GMAC_IDRPQ[7]; /**< \brief (Gmac Offset: 0x620) Interrupt Disable Register Priority Queue */ + RoReg Reserved11[1]; + RwReg GMAC_IMRPQ[7]; /**< \brief (Gmac Offset: 0x640) Interrupt Mask Register Priority Queue */ +} Gmac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- GMAC_NCR : (GMAC Offset: 0x000) Network Control Register -------- */ +#define GMAC_NCR_LB (0x1u << 0) /**< \brief (GMAC_NCR) Loop Back */ +#define GMAC_NCR_LBL (0x1u << 1) /**< \brief (GMAC_NCR) Loop Back Local */ +#define GMAC_NCR_RXEN (0x1u << 2) /**< \brief (GMAC_NCR) Receive Enable */ +#define GMAC_NCR_TXEN (0x1u << 3) /**< \brief (GMAC_NCR) Transmit Enable */ +#define GMAC_NCR_MPE (0x1u << 4) /**< \brief (GMAC_NCR) Management Port Enable */ +#define GMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (GMAC_NCR) Clear Statistics Registers */ +#define GMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (GMAC_NCR) Increment Statistics Registers */ +#define GMAC_NCR_WESTAT (0x1u << 7) /**< \brief (GMAC_NCR) Write Enable for Statistics Registers */ +#define GMAC_NCR_BP (0x1u << 8) /**< \brief (GMAC_NCR) Back pressure */ +#define GMAC_NCR_TSTART (0x1u << 9) /**< \brief (GMAC_NCR) Start Transmission */ +#define GMAC_NCR_THALT (0x1u << 10) /**< \brief (GMAC_NCR) Transmit Halt */ +#define GMAC_NCR_TXPF (0x1u << 11) /**< \brief (GMAC_NCR) Transmit Pause Frame */ +#define GMAC_NCR_TXZQPF (0x1u << 12) /**< \brief (GMAC_NCR) Transmit Zero Quantum Pause Frame */ +#define GMAC_NCR_RDS (0x1u << 14) /**< \brief (GMAC_NCR) Read Snapshot */ +#define GMAC_NCR_SRTSM (0x1u << 15) /**< \brief (GMAC_NCR) Store Receive Time Stamp to Memory */ +#define GMAC_NCR_ENPBPR (0x1u << 16) /**< \brief (GMAC_NCR) Enable PFC Priority-based Pause Reception */ +#define GMAC_NCR_TXPBPF (0x1u << 17) /**< \brief (GMAC_NCR) Transmit PFC Priority-based Pause Frame */ +#define GMAC_NCR_FNP (0x1u << 18) /**< \brief (GMAC_NCR) Flush Next Packet */ +/* -------- GMAC_NCFGR : (GMAC Offset: 0x004) Network Configuration Register -------- */ +#define GMAC_NCFGR_SPD (0x1u << 0) /**< \brief (GMAC_NCFGR) Speed */ +#define GMAC_NCFGR_FD (0x1u << 1) /**< \brief (GMAC_NCFGR) Full Duplex */ +#define GMAC_NCFGR_DNVLAN (0x1u << 2) /**< \brief (GMAC_NCFGR) Discard Non-VLAN FRAMES */ +#define GMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (GMAC_NCFGR) Jumbo Frame Size */ +#define GMAC_NCFGR_CAF (0x1u << 4) /**< \brief (GMAC_NCFGR) Copy All Frames */ +#define GMAC_NCFGR_NBC (0x1u << 5) /**< \brief (GMAC_NCFGR) No Broadcast */ +#define GMAC_NCFGR_MTIHEN (0x1u << 6) /**< \brief (GMAC_NCFGR) Multicast Hash Enable */ +#define GMAC_NCFGR_UNIHEN (0x1u << 7) /**< \brief (GMAC_NCFGR) Unicast Hash Enable */ +#define GMAC_NCFGR_MAXFS (0x1u << 8) /**< \brief (GMAC_NCFGR) 1536 Maximum Frame Size */ +#define GMAC_NCFGR_GBE (0x1u << 10) /**< \brief (GMAC_NCFGR) Gigabit Mode Enable */ +#define GMAC_NCFGR_PIS (0x1u << 11) /**< \brief (GMAC_NCFGR) Physical Interface Select */ +#define GMAC_NCFGR_RTY (0x1u << 12) /**< \brief (GMAC_NCFGR) Retry Test */ +#define GMAC_NCFGR_PEN (0x1u << 13) /**< \brief (GMAC_NCFGR) Pause Enable */ +#define GMAC_NCFGR_RXBUFO_Pos 14 +#define GMAC_NCFGR_RXBUFO_Msk (0x3u << GMAC_NCFGR_RXBUFO_Pos) /**< \brief (GMAC_NCFGR) Receive Buffer Offset */ +#define GMAC_NCFGR_RXBUFO(value) ((GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos))) +#define GMAC_NCFGR_LFERD (0x1u << 16) /**< \brief (GMAC_NCFGR) Length Field Error Frame Discard */ +#define GMAC_NCFGR_RFCS (0x1u << 17) /**< \brief (GMAC_NCFGR) Remove FCS */ +#define GMAC_NCFGR_CLK_Pos 18 +#define GMAC_NCFGR_CLK_Msk (0x7u << GMAC_NCFGR_CLK_Pos) /**< \brief (GMAC_NCFGR) MDC CLock Division */ +#define GMAC_NCFGR_CLK_MCK_8 (0x0u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) */ +#define GMAC_NCFGR_CLK_MCK_16 (0x1u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) */ +#define GMAC_NCFGR_CLK_MCK_32 (0x2u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) */ +#define GMAC_NCFGR_CLK_MCK_48 (0x3u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 48 (MCK up to 120MHz) */ +#define GMAC_NCFGR_CLK_MCK_64 (0x4u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) */ +#define GMAC_NCFGR_CLK_MCK_96 (0x5u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) */ +#define GMAC_NCFGR_CLK_MCK_128 (0x6u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 128 (MCK up to 320 MHz) */ +#define GMAC_NCFGR_CLK_MCK_224 (0x7u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 224 (MCK up to 540 MHz) */ +#define GMAC_NCFGR_DBW_Pos 21 +#define GMAC_NCFGR_DBW_Msk (0x3u << GMAC_NCFGR_DBW_Pos) /**< \brief (GMAC_NCFGR) Data Bus Width */ +#define GMAC_NCFGR_DBW_DBW32 (0x0u << 21) /**< \brief (GMAC_NCFGR) 32-bit data bus width */ +#define GMAC_NCFGR_DBW_DBW64 (0x1u << 21) /**< \brief (GMAC_NCFGR) 64-bit data bus width */ +#define GMAC_NCFGR_DCPF (0x1u << 23) /**< \brief (GMAC_NCFGR) Disable Copy of Pause Frames */ +#define GMAC_NCFGR_RXCOEN (0x1u << 24) /**< \brief (GMAC_NCFGR) Receive Checksum Offload Enable */ +#define GMAC_NCFGR_EFRHD (0x1u << 25) /**< \brief (GMAC_NCFGR) Enable Frames Received in Half Duplex */ +#define GMAC_NCFGR_IRXFCS (0x1u << 26) /**< \brief (GMAC_NCFGR) Ignore RX FCS */ +#define GMAC_NCFGR_IPGSEN (0x1u << 28) /**< \brief (GMAC_NCFGR) IP Stretch Enable */ +#define GMAC_NCFGR_RXBP (0x1u << 29) /**< \brief (GMAC_NCFGR) Receive Bad Preamble */ +#define GMAC_NCFGR_IRXER (0x1u << 30) /**< \brief (GMAC_NCFGR) Ignore IPG rx_er */ +/* -------- GMAC_NSR : (GMAC Offset: 0x008) Network Status Register -------- */ +#define GMAC_NSR_MDIO (0x1u << 1) /**< \brief (GMAC_NSR) MDIO Input Status */ +#define GMAC_NSR_IDLE (0x1u << 2) /**< \brief (GMAC_NSR) PHY Management Logic Idle */ +/* -------- GMAC_UR : (GMAC Offset: 0x00C) User Register -------- */ +#define GMAC_UR_RGMII (0x1u << 0) /**< \brief (GMAC_UR) RGMII Mode */ +#define GMAC_UR_HDFC (0x1u << 6) /**< \brief (GMAC_UR) Half Duplex Flow Control */ +#define GMAC_UR_BPDG (0x1u << 7) /**< \brief (GMAC_UR) BPDG Bypass Deglitchers */ +/* -------- GMAC_DCFGR : (GMAC Offset: 0x010) DMA Configuration Register -------- */ +#define GMAC_DCFGR_FBLDO_Pos 0 +#define GMAC_DCFGR_FBLDO_Msk (0x1fu << GMAC_DCFGR_FBLDO_Pos) /**< \brief (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: */ +#define GMAC_DCFGR_FBLDO_SINGLE (0x1u << 0) /**< \brief (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR4 (0x4u << 0) /**< \brief (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) */ +#define GMAC_DCFGR_FBLDO_INCR8 (0x8u << 0) /**< \brief (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR16 (0x10u << 0) /**< \brief (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts */ +#define GMAC_DCFGR_ESMA (0x1u << 6) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses */ +#define GMAC_DCFGR_ESPA (0x1u << 7) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses */ +#define GMAC_DCFGR_RXBMS_Pos 8 +#define GMAC_DCFGR_RXBMS_Msk (0x3u << GMAC_DCFGR_RXBMS_Pos) /**< \brief (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select */ +#define GMAC_DCFGR_RXBMS_EIGHTH (0x0u << 8) /**< \brief (GMAC_DCFGR) 1 Kbyte Memory Size */ +#define GMAC_DCFGR_RXBMS_QUARTER (0x1u << 8) /**< \brief (GMAC_DCFGR) 2 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_HALF (0x2u << 8) /**< \brief (GMAC_DCFGR) 4 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_FULL (0x3u << 8) /**< \brief (GMAC_DCFGR) 8 Kbytes Memory Size */ +#define GMAC_DCFGR_TXPBMS (0x1u << 10) /**< \brief (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select */ +#define GMAC_DCFGR_TXCOEN (0x1u << 11) /**< \brief (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable */ +#define GMAC_DCFGR_DRBS_Pos 16 +#define GMAC_DCFGR_DRBS_Msk (0xffu << GMAC_DCFGR_DRBS_Pos) /**< \brief (GMAC_DCFGR) DMA Receive Buffer Size */ +#define GMAC_DCFGR_DRBS(value) ((GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos))) +#define GMAC_DCFGR_DDRP (0x1u << 24) /**< \brief (GMAC_DCFGR) DMA Discard Receive Packets */ +/* -------- GMAC_TSR : (GMAC Offset: 0x014) Transmit Status Register -------- */ +#define GMAC_TSR_UBR (0x1u << 0) /**< \brief (GMAC_TSR) Used Bit Read */ +#define GMAC_TSR_COL (0x1u << 1) /**< \brief (GMAC_TSR) Collision Occurred */ +#define GMAC_TSR_RLE (0x1u << 2) /**< \brief (GMAC_TSR) Retry Limit Exceeded */ +#define GMAC_TSR_TXGO (0x1u << 3) /**< \brief (GMAC_TSR) Transmit Go */ +#define GMAC_TSR_TFC (0x1u << 4) /**< \brief (GMAC_TSR) Transmit Frame Corruption due to AHB error */ +#define GMAC_TSR_TXCOMP (0x1u << 5) /**< \brief (GMAC_TSR) Transmit Complete */ +#define GMAC_TSR_UND (0x1u << 6) /**< \brief (GMAC_TSR) Transmit Under Run */ +#define GMAC_TSR_LCO (0x1u << 7) /**< \brief (GMAC_TSR) Late Collision Occurred */ +#define GMAC_TSR_HRESP (0x1u << 8) /**< \brief (GMAC_TSR) HRESP Not OK */ +/* -------- GMAC_RBQB : (GMAC Offset: 0x018) Receive Buffer Queue Base Address -------- */ +#define GMAC_RBQB_ADDR_Pos 2 +#define GMAC_RBQB_ADDR_Msk (0x3fffffffu << GMAC_RBQB_ADDR_Pos) /**< \brief (GMAC_RBQB) Receive buffer queue base address */ +#define GMAC_RBQB_ADDR(value) ((GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos))) +/* -------- GMAC_TBQB : (GMAC Offset: 0x01C) Transmit Buffer Queue Base Address -------- */ +#define GMAC_TBQB_ADDR_Pos 2 +#define GMAC_TBQB_ADDR_Msk (0x3fffffffu << GMAC_TBQB_ADDR_Pos) /**< \brief (GMAC_TBQB) Transmit Buffer Queue Base Address */ +#define GMAC_TBQB_ADDR(value) ((GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos))) +/* -------- GMAC_RSR : (GMAC Offset: 0x020) Receive Status Register -------- */ +#define GMAC_RSR_BNA (0x1u << 0) /**< \brief (GMAC_RSR) Buffer Not Available */ +#define GMAC_RSR_REC (0x1u << 1) /**< \brief (GMAC_RSR) Frame Received */ +#define GMAC_RSR_RXOVR (0x1u << 2) /**< \brief (GMAC_RSR) Receive Overrun */ +#define GMAC_RSR_HNO (0x1u << 3) /**< \brief (GMAC_RSR) HRESP Not OK */ +/* -------- GMAC_ISR : (GMAC Offset: 0x024) Interrupt Status Register -------- */ +#define GMAC_ISR_MFS (0x1u << 0) /**< \brief (GMAC_ISR) Management Frame Sent */ +#define GMAC_ISR_RCOMP (0x1u << 1) /**< \brief (GMAC_ISR) Receive Complete */ +#define GMAC_ISR_RXUBR (0x1u << 2) /**< \brief (GMAC_ISR) RX Used Bit Read */ +#define GMAC_ISR_TXUBR (0x1u << 3) /**< \brief (GMAC_ISR) TX Used Bit Read */ +#define GMAC_ISR_TUR (0x1u << 4) /**< \brief (GMAC_ISR) Transmit Under Run */ +#define GMAC_ISR_RLEX (0x1u << 5) /**< \brief (GMAC_ISR) Retry Limit Exceeded or Late Collision */ +#define GMAC_ISR_TFC (0x1u << 6) /**< \brief (GMAC_ISR) Transmit Frame Corruption due to AHB error */ +#define GMAC_ISR_TCOMP (0x1u << 7) /**< \brief (GMAC_ISR) Transmit Complete */ +#define GMAC_ISR_ROVR (0x1u << 10) /**< \brief (GMAC_ISR) Receive Overrun */ +#define GMAC_ISR_HRESP (0x1u << 11) /**< \brief (GMAC_ISR) HRESP Not OK */ +#define GMAC_ISR_PFNZ (0x1u << 12) /**< \brief (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_ISR_PTZ (0x1u << 13) /**< \brief (GMAC_ISR) Pause Time Zero */ +#define GMAC_ISR_PFTR (0x1u << 14) /**< \brief (GMAC_ISR) Pause Frame Transmitted */ +#define GMAC_ISR_EXINT (0x1u << 15) /**< \brief (GMAC_ISR) External Interrupt */ +#define GMAC_ISR_DRQFR (0x1u << 18) /**< \brief (GMAC_ISR) PTP Delay Request Frame Received */ +#define GMAC_ISR_SFR (0x1u << 19) /**< \brief (GMAC_ISR) PTP Sync Frame Received */ +#define GMAC_ISR_DRQFT (0x1u << 20) /**< \brief (GMAC_ISR) PTP Delay Request Frame Transmitted */ +#define GMAC_ISR_SFT (0x1u << 21) /**< \brief (GMAC_ISR) PTP Sync Frame Transmitted */ +#define GMAC_ISR_PDRQFR (0x1u << 22) /**< \brief (GMAC_ISR) PDelay Request Frame Received */ +#define GMAC_ISR_PDRSFR (0x1u << 23) /**< \brief (GMAC_ISR) PDelay Response Frame Received */ +#define GMAC_ISR_PDRQFT (0x1u << 24) /**< \brief (GMAC_ISR) PDelay Request Frame Transmitted */ +#define GMAC_ISR_PDRSFT (0x1u << 25) /**< \brief (GMAC_ISR) PDelay Response Frame Transmitted */ +#define GMAC_ISR_SRI (0x1u << 26) /**< \brief (GMAC_ISR) TSU Seconds Register Increment */ +#define GMAC_ISR_WOL (0x1u << 28) /**< \brief (GMAC_ISR) Wake On LAN */ +/* -------- GMAC_IER : (GMAC Offset: 0x028) Interrupt Enable Register -------- */ +#define GMAC_IER_MFS (0x1u << 0) /**< \brief (GMAC_IER) Management Frame Sent */ +#define GMAC_IER_RCOMP (0x1u << 1) /**< \brief (GMAC_IER) Receive Complete */ +#define GMAC_IER_RXUBR (0x1u << 2) /**< \brief (GMAC_IER) RX Used Bit Read */ +#define GMAC_IER_TXUBR (0x1u << 3) /**< \brief (GMAC_IER) TX Used Bit Read */ +#define GMAC_IER_TUR (0x1u << 4) /**< \brief (GMAC_IER) Transmit Under Run */ +#define GMAC_IER_RLEX (0x1u << 5) /**< \brief (GMAC_IER) Retry Limit Exceeded or Late Collision */ +#define GMAC_IER_TFC (0x1u << 6) /**< \brief (GMAC_IER) Transmit Frame Corruption due to AHB error */ +#define GMAC_IER_TCOMP (0x1u << 7) /**< \brief (GMAC_IER) Transmit Complete */ +#define GMAC_IER_ROVR (0x1u << 10) /**< \brief (GMAC_IER) Receive Overrun */ +#define GMAC_IER_HRESP (0x1u << 11) /**< \brief (GMAC_IER) HRESP Not OK */ +#define GMAC_IER_PFNZ (0x1u << 12) /**< \brief (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IER_PTZ (0x1u << 13) /**< \brief (GMAC_IER) Pause Time Zero */ +#define GMAC_IER_PFTR (0x1u << 14) /**< \brief (GMAC_IER) Pause Frame Transmitted */ +#define GMAC_IER_EXINT (0x1u << 15) /**< \brief (GMAC_IER) External Interrupt */ +#define GMAC_IER_DRQFR (0x1u << 18) /**< \brief (GMAC_IER) PTP Delay Request Frame Received */ +#define GMAC_IER_SFR (0x1u << 19) /**< \brief (GMAC_IER) PTP Sync Frame Received */ +#define GMAC_IER_DRQFT (0x1u << 20) /**< \brief (GMAC_IER) PTP Delay Request Frame Transmitted */ +#define GMAC_IER_SFT (0x1u << 21) /**< \brief (GMAC_IER) PTP Sync Frame Transmitted */ +#define GMAC_IER_PDRQFR (0x1u << 22) /**< \brief (GMAC_IER) PDelay Request Frame Received */ +#define GMAC_IER_PDRSFR (0x1u << 23) /**< \brief (GMAC_IER) PDelay Response Frame Received */ +#define GMAC_IER_PDRQFT (0x1u << 24) /**< \brief (GMAC_IER) PDelay Request Frame Transmitted */ +#define GMAC_IER_PDRSFT (0x1u << 25) /**< \brief (GMAC_IER) PDelay Response Frame Transmitted */ +#define GMAC_IER_SRI (0x1u << 26) /**< \brief (GMAC_IER) TSU Seconds Register Increment */ +#define GMAC_IER_WOL (0x1u << 28) /**< \brief (GMAC_IER) Wake On LAN */ +/* -------- GMAC_IDR : (GMAC Offset: 0x02C) Interrupt Disable Register -------- */ +#define GMAC_IDR_MFS (0x1u << 0) /**< \brief (GMAC_IDR) Management Frame Sent */ +#define GMAC_IDR_RCOMP (0x1u << 1) /**< \brief (GMAC_IDR) Receive Complete */ +#define GMAC_IDR_RXUBR (0x1u << 2) /**< \brief (GMAC_IDR) RX Used Bit Read */ +#define GMAC_IDR_TXUBR (0x1u << 3) /**< \brief (GMAC_IDR) TX Used Bit Read */ +#define GMAC_IDR_TUR (0x1u << 4) /**< \brief (GMAC_IDR) Transmit Under Run */ +#define GMAC_IDR_RLEX (0x1u << 5) /**< \brief (GMAC_IDR) Retry Limit Exceeded or Late Collision */ +#define GMAC_IDR_TFC (0x1u << 6) /**< \brief (GMAC_IDR) Transmit Frame Corruption due to AHB error */ +#define GMAC_IDR_TCOMP (0x1u << 7) /**< \brief (GMAC_IDR) Transmit Complete */ +#define GMAC_IDR_ROVR (0x1u << 10) /**< \brief (GMAC_IDR) Receive Overrun */ +#define GMAC_IDR_HRESP (0x1u << 11) /**< \brief (GMAC_IDR) HRESP Not OK */ +#define GMAC_IDR_PFNZ (0x1u << 12) /**< \brief (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IDR_PTZ (0x1u << 13) /**< \brief (GMAC_IDR) Pause Time Zero */ +#define GMAC_IDR_PFTR (0x1u << 14) /**< \brief (GMAC_IDR) Pause Frame Transmitted */ +#define GMAC_IDR_EXINT (0x1u << 15) /**< \brief (GMAC_IDR) External Interrupt */ +#define GMAC_IDR_DRQFR (0x1u << 18) /**< \brief (GMAC_IDR) PTP Delay Request Frame Received */ +#define GMAC_IDR_SFR (0x1u << 19) /**< \brief (GMAC_IDR) PTP Sync Frame Received */ +#define GMAC_IDR_DRQFT (0x1u << 20) /**< \brief (GMAC_IDR) PTP Delay Request Frame Transmitted */ +#define GMAC_IDR_SFT (0x1u << 21) /**< \brief (GMAC_IDR) PTP Sync Frame Transmitted */ +#define GMAC_IDR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IDR) PDelay Request Frame Received */ +#define GMAC_IDR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IDR) PDelay Response Frame Received */ +#define GMAC_IDR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IDR) PDelay Request Frame Transmitted */ +#define GMAC_IDR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IDR) PDelay Response Frame Transmitted */ +#define GMAC_IDR_SRI (0x1u << 26) /**< \brief (GMAC_IDR) TSU Seconds Register Increment */ +#define GMAC_IDR_WOL (0x1u << 28) /**< \brief (GMAC_IDR) Wake On LAN */ +/* -------- GMAC_IMR : (GMAC Offset: 0x030) Interrupt Mask Register -------- */ +#define GMAC_IMR_MFS (0x1u << 0) /**< \brief (GMAC_IMR) Management Frame Sent */ +#define GMAC_IMR_RCOMP (0x1u << 1) /**< \brief (GMAC_IMR) Receive Complete */ +#define GMAC_IMR_RXUBR (0x1u << 2) /**< \brief (GMAC_IMR) RX Used Bit Read */ +#define GMAC_IMR_TXUBR (0x1u << 3) /**< \brief (GMAC_IMR) TX Used Bit Read */ +#define GMAC_IMR_TUR (0x1u << 4) /**< \brief (GMAC_IMR) Transmit Under Run */ +#define GMAC_IMR_RLEX (0x1u << 5) /**< \brief (GMAC_IMR) Retry Limit Exceeded or Late Collision */ +#define GMAC_IMR_TFC (0x1u << 6) /**< \brief (GMAC_IMR) Transmit Frame Corruption due to AHB error */ +#define GMAC_IMR_TCOMP (0x1u << 7) /**< \brief (GMAC_IMR) Transmit Complete */ +#define GMAC_IMR_ROVR (0x1u << 10) /**< \brief (GMAC_IMR) Receive Overrun */ +#define GMAC_IMR_HRESP (0x1u << 11) /**< \brief (GMAC_IMR) HRESP Not OK */ +#define GMAC_IMR_PFNZ (0x1u << 12) /**< \brief (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IMR_PTZ (0x1u << 13) /**< \brief (GMAC_IMR) Pause Time Zero */ +#define GMAC_IMR_PFTR (0x1u << 14) /**< \brief (GMAC_IMR) Pause Frame Transmitted */ +#define GMAC_IMR_EXINT (0x1u << 15) /**< \brief (GMAC_IMR) External Interrupt */ +#define GMAC_IMR_DRQFR (0x1u << 18) /**< \brief (GMAC_IMR) PTP Delay Request Frame Received */ +#define GMAC_IMR_SFR (0x1u << 19) /**< \brief (GMAC_IMR) PTP Sync Frame Received */ +#define GMAC_IMR_DRQFT (0x1u << 20) /**< \brief (GMAC_IMR) PTP Delay Request Frame Transmitted */ +#define GMAC_IMR_SFT (0x1u << 21) /**< \brief (GMAC_IMR) PTP Sync Frame Transmitted */ +#define GMAC_IMR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IMR) PDelay Request Frame Received */ +#define GMAC_IMR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IMR) PDelay Response Frame Received */ +#define GMAC_IMR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IMR) PDelay Request Frame Transmitted */ +#define GMAC_IMR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IMR) PDelay Response Frame Transmitted */ +/* -------- GMAC_MAN : (GMAC Offset: 0x034) PHY Maintenance Register -------- */ +#define GMAC_MAN_DATA_Pos 0 +#define GMAC_MAN_DATA_Msk (0xffffu << GMAC_MAN_DATA_Pos) /**< \brief (GMAC_MAN) PHY Data */ +#define GMAC_MAN_DATA(value) ((GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos))) +#define GMAC_MAN_WTN_Pos 16 +#define GMAC_MAN_WTN_Msk (0x3u << GMAC_MAN_WTN_Pos) /**< \brief (GMAC_MAN) Write Ten */ +#define GMAC_MAN_WTN(value) ((GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos))) +#define GMAC_MAN_REGA_Pos 18 +#define GMAC_MAN_REGA_Msk (0x1fu << GMAC_MAN_REGA_Pos) /**< \brief (GMAC_MAN) Register Address */ +#define GMAC_MAN_REGA(value) ((GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos))) +#define GMAC_MAN_PHYA_Pos 23 +#define GMAC_MAN_PHYA_Msk (0x1fu << GMAC_MAN_PHYA_Pos) /**< \brief (GMAC_MAN) PHY Address */ +#define GMAC_MAN_PHYA(value) ((GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos))) +#define GMAC_MAN_OP_Pos 28 +#define GMAC_MAN_OP_Msk (0x3u << GMAC_MAN_OP_Pos) /**< \brief (GMAC_MAN) Operation */ +#define GMAC_MAN_OP(value) ((GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos))) +#define GMAC_MAN_CLTTO (0x1u << 30) /**< \brief (GMAC_MAN) Clause 22 Operation */ +#define GMAC_MAN_WZO (0x1u << 31) /**< \brief (GMAC_MAN) Write ZERO */ +/* -------- GMAC_RPQ : (GMAC Offset: 0x038) Received Pause Quantum Register -------- */ +#define GMAC_RPQ_RPQ_Pos 0 +#define GMAC_RPQ_RPQ_Msk (0xffffu << GMAC_RPQ_RPQ_Pos) /**< \brief (GMAC_RPQ) Received Pause Quantum */ +/* -------- GMAC_TPQ : (GMAC Offset: 0x03C) Transmit Pause Quantum Register -------- */ +#define GMAC_TPQ_TPQ_Pos 0 +#define GMAC_TPQ_TPQ_Msk (0xffffu << GMAC_TPQ_TPQ_Pos) /**< \brief (GMAC_TPQ) Transmit Pause Quantum */ +#define GMAC_TPQ_TPQ(value) ((GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos))) +/* -------- GMAC_TPSF : (GMAC Offset: 0x040) TX Partial Store and Forward Register -------- */ +#define GMAC_TPSF_TPB1ADR_Pos 0 +#define GMAC_TPSF_TPB1ADR_Msk (0xfffu << GMAC_TPSF_TPB1ADR_Pos) /**< \brief (GMAC_TPSF) tx_pbuf_addr-1:0 */ +#define GMAC_TPSF_TPB1ADR(value) ((GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos))) +#define GMAC_TPSF_ENTXP (0x1u << 31) /**< \brief (GMAC_TPSF) Enable TX Partial Store and Forward Operation */ +/* -------- GMAC_RPSF : (GMAC Offset: 0x044) RX Partial Store and Forward Register -------- */ +#define GMAC_RPSF_RPB1ADR_Pos 0 +#define GMAC_RPSF_RPB1ADR_Msk (0xfffu << GMAC_RPSF_RPB1ADR_Pos) /**< \brief (GMAC_RPSF) rx_pbuf_addr-1:0 */ +#define GMAC_RPSF_RPB1ADR(value) ((GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos))) +#define GMAC_RPSF_ENRXP (0x1u << 31) /**< \brief (GMAC_RPSF) Enable RX Partial Store and Forward Operation */ +/* -------- GMAC_HRB : (GMAC Offset: 0x080) Hash Register Bottom [31:0] -------- */ +#define GMAC_HRB_ADDR_Pos 0 +#define GMAC_HRB_ADDR_Msk (0xffffffffu << GMAC_HRB_ADDR_Pos) /**< \brief (GMAC_HRB) Hash Address */ +#define GMAC_HRB_ADDR(value) ((GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos))) +/* -------- GMAC_HRT : (GMAC Offset: 0x084) Hash Register Top [63:32] -------- */ +#define GMAC_HRT_ADDR_Pos 0 +#define GMAC_HRT_ADDR_Msk (0xffffffffu << GMAC_HRT_ADDR_Pos) /**< \brief (GMAC_HRT) Hash Address */ +#define GMAC_HRT_ADDR(value) ((GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos))) +/* -------- GMAC_SAB1 : (GMAC Offset: 0x088) Specific Address 1 Bottom [31:0] Register -------- */ +#define GMAC_SAB1_ADDR_Pos 0 +#define GMAC_SAB1_ADDR_Msk (0xffffffffu << GMAC_SAB1_ADDR_Pos) /**< \brief (GMAC_SAB1) Specific Address 1 */ +#define GMAC_SAB1_ADDR(value) ((GMAC_SAB1_ADDR_Msk & ((value) << GMAC_SAB1_ADDR_Pos))) +/* -------- GMAC_SAT1 : (GMAC Offset: 0x08C) Specific Address 1 Top [47:32] Register -------- */ +#define GMAC_SAT1_ADDR_Pos 0 +#define GMAC_SAT1_ADDR_Msk (0xffffu << GMAC_SAT1_ADDR_Pos) /**< \brief (GMAC_SAT1) Specific Address 1 */ +#define GMAC_SAT1_ADDR(value) ((GMAC_SAT1_ADDR_Msk & ((value) << GMAC_SAT1_ADDR_Pos))) +/* -------- GMAC_SAB2 : (GMAC Offset: 0x090) Specific Address 2 Bottom [31:0] Register -------- */ +#define GMAC_SAB2_ADDR_Pos 0 +#define GMAC_SAB2_ADDR_Msk (0xffffffffu << GMAC_SAB2_ADDR_Pos) /**< \brief (GMAC_SAB2) Specific Address 2 */ +#define GMAC_SAB2_ADDR(value) ((GMAC_SAB2_ADDR_Msk & ((value) << GMAC_SAB2_ADDR_Pos))) +/* -------- GMAC_SAT2 : (GMAC Offset: 0x094) Specific Address 2 Top [47:32] Register -------- */ +#define GMAC_SAT2_ADDR_Pos 0 +#define GMAC_SAT2_ADDR_Msk (0xffffu << GMAC_SAT2_ADDR_Pos) /**< \brief (GMAC_SAT2) Specific Address 2 */ +#define GMAC_SAT2_ADDR(value) ((GMAC_SAT2_ADDR_Msk & ((value) << GMAC_SAT2_ADDR_Pos))) +/* -------- GMAC_SAB3 : (GMAC Offset: 0x098) Specific Address 3 Bottom [31:0] Register -------- */ +#define GMAC_SAB3_ADDR_Pos 0 +#define GMAC_SAB3_ADDR_Msk (0xffffffffu << GMAC_SAB3_ADDR_Pos) /**< \brief (GMAC_SAB3) Specific Address 3 */ +#define GMAC_SAB3_ADDR(value) ((GMAC_SAB3_ADDR_Msk & ((value) << GMAC_SAB3_ADDR_Pos))) +/* -------- GMAC_SAT3 : (GMAC Offset: 0x09C) Specific Address 3 Top [47:32] Register -------- */ +#define GMAC_SAT3_ADDR_Pos 0 +#define GMAC_SAT3_ADDR_Msk (0xffffu << GMAC_SAT3_ADDR_Pos) /**< \brief (GMAC_SAT3) Specific Address 3 */ +#define GMAC_SAT3_ADDR(value) ((GMAC_SAT3_ADDR_Msk & ((value) << GMAC_SAT3_ADDR_Pos))) +/* -------- GMAC_SAB4 : (GMAC Offset: 0x0A0) Specific Address 4 Bottom [31:0] Register -------- */ +#define GMAC_SAB4_ADDR_Pos 0 +#define GMAC_SAB4_ADDR_Msk (0xffffffffu << GMAC_SAB4_ADDR_Pos) /**< \brief (GMAC_SAB4) Specific Address 4 */ +#define GMAC_SAB4_ADDR(value) ((GMAC_SAB4_ADDR_Msk & ((value) << GMAC_SAB4_ADDR_Pos))) +/* -------- GMAC_SAT4 : (GMAC Offset: 0x0A4) Specific Address 4 Top [47:32] Register -------- */ +#define GMAC_SAT4_ADDR_Pos 0 +#define GMAC_SAT4_ADDR_Msk (0xffffu << GMAC_SAT4_ADDR_Pos) /**< \brief (GMAC_SAT4) Specific Address 4 */ +#define GMAC_SAT4_ADDR(value) ((GMAC_SAT4_ADDR_Msk & ((value) << GMAC_SAT4_ADDR_Pos))) +/* -------- GMAC_TIDM[4] : (GMAC Offset: 0x0A8) Type ID Match 1 Register -------- */ +#define GMAC_TIDM_TID_Pos 0 +#define GMAC_TIDM_TID_Msk (0xffffu << GMAC_TIDM_TID_Pos) /**< \brief (GMAC_TIDM[4]) Type ID Match 1 */ +#define GMAC_TIDM_TID(value) ((GMAC_TIDM_TID_Msk & ((value) << GMAC_TIDM_TID_Pos))) +/* -------- GMAC_WOL : (GMAC Offset: 0x0B8) Wake on LAN Register -------- */ +#define GMAC_WOL_IP_Pos 0 +#define GMAC_WOL_IP_Msk (0xffffu << GMAC_WOL_IP_Pos) /**< \brief (GMAC_WOL) ARP Request IP Address */ +#define GMAC_WOL_IP(value) ((GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos))) +#define GMAC_WOL_MAG (0x1u << 16) /**< \brief (GMAC_WOL) Magic Packet Event Enable */ +#define GMAC_WOL_ARP (0x1u << 17) /**< \brief (GMAC_WOL) ARP Request IP Address */ +#define GMAC_WOL_SA1 (0x1u << 18) /**< \brief (GMAC_WOL) Specific Address Register 1 Event Enable */ +#define GMAC_WOL_MTI (0x1u << 19) /**< \brief (GMAC_WOL) Multicast Hash Event Enable */ +/* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) IPG Stretch Register -------- */ +#define GMAC_IPGS_FL_Pos 0 +#define GMAC_IPGS_FL_Msk (0xffffu << GMAC_IPGS_FL_Pos) /**< \brief (GMAC_IPGS) Frame Length */ +#define GMAC_IPGS_FL(value) ((GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos))) +/* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) Stacked VLAN Register -------- */ +#define GMAC_SVLAN_VLAN_TYPE_Pos 0 +#define GMAC_SVLAN_VLAN_TYPE_Msk (0xffffu << GMAC_SVLAN_VLAN_TYPE_Pos) /**< \brief (GMAC_SVLAN) User Defined VLAN_TYPE Field */ +#define GMAC_SVLAN_VLAN_TYPE(value) ((GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos))) +#define GMAC_SVLAN_ESVLAN (0x1u << 31) /**< \brief (GMAC_SVLAN) Enable Stacked VLAN Processing Mode */ +/* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) Transmit PFC Pause Register -------- */ +#define GMAC_TPFCP_PEV_Pos 0 +#define GMAC_TPFCP_PEV_Msk (0xffu << GMAC_TPFCP_PEV_Pos) /**< \brief (GMAC_TPFCP) Priority Enable Vector */ +#define GMAC_TPFCP_PEV(value) ((GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos))) +#define GMAC_TPFCP_PQ_Pos 8 +#define GMAC_TPFCP_PQ_Msk (0xffu << GMAC_TPFCP_PQ_Pos) /**< \brief (GMAC_TPFCP) Pause Quantum */ +#define GMAC_TPFCP_PQ(value) ((GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos))) +/* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) Specific Address 1 Mask Bottom [31:0] Register -------- */ +#define GMAC_SAMB1_ADDR_Pos 0 +#define GMAC_SAMB1_ADDR_Msk (0xffffffffu << GMAC_SAMB1_ADDR_Pos) /**< \brief (GMAC_SAMB1) Specific Address 1 Mask */ +#define GMAC_SAMB1_ADDR(value) ((GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos))) +/* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) Specific Address 1 Mask Top [47:32] Register -------- */ +#define GMAC_SAMT1_ADDR_Pos 0 +#define GMAC_SAMT1_ADDR_Msk (0xffffu << GMAC_SAMT1_ADDR_Pos) /**< \brief (GMAC_SAMT1) Specific Address 1 Mask */ +#define GMAC_SAMT1_ADDR(value) ((GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos))) +/* -------- GMAC_OTLO : (GMAC Offset: 0x100) Octets Transmitted [31:0] Register -------- */ +#define GMAC_OTLO_TXO_Pos 0 +#define GMAC_OTLO_TXO_Msk (0xffffffffu << GMAC_OTLO_TXO_Pos) /**< \brief (GMAC_OTLO) Transmitted Octets */ +/* -------- GMAC_OTHI : (GMAC Offset: 0x104) Octets Transmitted [47:32] Register -------- */ +#define GMAC_OTHI_TXO_Pos 0 +#define GMAC_OTHI_TXO_Msk (0xffffu << GMAC_OTHI_TXO_Pos) /**< \brief (GMAC_OTHI) Transmitted Octets */ +/* -------- GMAC_FT : (GMAC Offset: 0x108) Frames Transmitted Register -------- */ +#define GMAC_FT_FTX_Pos 0 +#define GMAC_FT_FTX_Msk (0xffffffffu << GMAC_FT_FTX_Pos) /**< \brief (GMAC_FT) Frames Transmitted without Error */ +/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) Broadcast Frames Transmitted Register -------- */ +#define GMAC_BCFT_BFTX_Pos 0 +#define GMAC_BCFT_BFTX_Msk (0xffffffffu << GMAC_BCFT_BFTX_Pos) /**< \brief (GMAC_BCFT) Broadcast Frames Transmitted without Error */ +/* -------- GMAC_MFT : (GMAC Offset: 0x110) Multicast Frames Transmitted Register -------- */ +#define GMAC_MFT_MFTX_Pos 0 +#define GMAC_MFT_MFTX_Msk (0xffffffffu << GMAC_MFT_MFTX_Pos) /**< \brief (GMAC_MFT) Multicast Frames Transmitted without Error */ +/* -------- GMAC_PFT : (GMAC Offset: 0x114) Pause Frames Transmitted Register -------- */ +#define GMAC_PFT_PFTX_Pos 0 +#define GMAC_PFT_PFTX_Msk (0xffffu << GMAC_PFT_PFTX_Pos) /**< \brief (GMAC_PFT) Pause Frames Transmitted Register */ +/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) 64 Byte Frames Transmitted Register -------- */ +#define GMAC_BFT64_NFTX_Pos 0 +#define GMAC_BFT64_NFTX_Msk (0xffffffffu << GMAC_BFT64_NFTX_Pos) /**< \brief (GMAC_BFT64) 64 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT127_NFTX_Pos 0 +#define GMAC_TBFT127_NFTX_Msk (0xffffffffu << GMAC_TBFT127_NFTX_Pos) /**< \brief (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) 128 to 255 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT255_NFTX_Pos 0 +#define GMAC_TBFT255_NFTX_Msk (0xffffffffu << GMAC_TBFT255_NFTX_Pos) /**< \brief (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) 256 to 511 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT511_NFTX_Pos 0 +#define GMAC_TBFT511_NFTX_Msk (0xffffffffu << GMAC_TBFT511_NFTX_Pos) /**< \brief (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1023_NFTX_Pos 0 +#define GMAC_TBFT1023_NFTX_Msk (0xffffffffu << GMAC_TBFT1023_NFTX_Pos) /**< \brief (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1518_NFTX_Pos 0 +#define GMAC_TBFT1518_NFTX_Msk (0xffffffffu << GMAC_TBFT1518_NFTX_Pos) /**< \brief (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error */ +/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_GTBFT1518_NFTX_Pos 0 +#define GMAC_GTBFT1518_NFTX_Msk (0xffffffffu << GMAC_GTBFT1518_NFTX_Pos) /**< \brief (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error */ +/* -------- GMAC_TUR : (GMAC Offset: 0x134) Transmit Under Runs Register -------- */ +#define GMAC_TUR_TXUNR_Pos 0 +#define GMAC_TUR_TXUNR_Msk (0x3ffu << GMAC_TUR_TXUNR_Pos) /**< \brief (GMAC_TUR) Transmit Under Runs */ +/* -------- GMAC_SCF : (GMAC Offset: 0x138) Single Collision Frames Register -------- */ +#define GMAC_SCF_SCOL_Pos 0 +#define GMAC_SCF_SCOL_Msk (0x3ffffu << GMAC_SCF_SCOL_Pos) /**< \brief (GMAC_SCF) Single Collision */ +/* -------- GMAC_MCF : (GMAC Offset: 0x13C) Multiple Collision Frames Register -------- */ +#define GMAC_MCF_MCOL_Pos 0 +#define GMAC_MCF_MCOL_Msk (0x3ffffu << GMAC_MCF_MCOL_Pos) /**< \brief (GMAC_MCF) Multiple Collision */ +/* -------- GMAC_EC : (GMAC Offset: 0x140) Excessive Collisions Register -------- */ +#define GMAC_EC_XCOL_Pos 0 +#define GMAC_EC_XCOL_Msk (0x3ffu << GMAC_EC_XCOL_Pos) /**< \brief (GMAC_EC) Excessive Collisions */ +/* -------- GMAC_LC : (GMAC Offset: 0x144) Late Collisions Register -------- */ +#define GMAC_LC_LCOL_Pos 0 +#define GMAC_LC_LCOL_Msk (0x3ffu << GMAC_LC_LCOL_Pos) /**< \brief (GMAC_LC) Late Collisions */ +/* -------- GMAC_DTF : (GMAC Offset: 0x148) Deferred Transmission Frames Register -------- */ +#define GMAC_DTF_DEFT_Pos 0 +#define GMAC_DTF_DEFT_Msk (0x3ffffu << GMAC_DTF_DEFT_Pos) /**< \brief (GMAC_DTF) Deferred Transmission */ +/* -------- GMAC_CSE : (GMAC Offset: 0x14C) Carrier Sense Errors Register -------- */ +#define GMAC_CSE_CSR_Pos 0 +#define GMAC_CSE_CSR_Msk (0x3ffu << GMAC_CSE_CSR_Pos) /**< \brief (GMAC_CSE) Carrier Sense Error */ +/* -------- GMAC_ORLO : (GMAC Offset: 0x150) Octets Received [31:0] Received -------- */ +#define GMAC_ORLO_RXO_Pos 0 +#define GMAC_ORLO_RXO_Msk (0xffffffffu << GMAC_ORLO_RXO_Pos) /**< \brief (GMAC_ORLO) Received Octets */ +/* -------- GMAC_ORHI : (GMAC Offset: 0x154) Octets Received [47:32] Received -------- */ +#define GMAC_ORHI_RXO_Pos 0 +#define GMAC_ORHI_RXO_Msk (0xffffu << GMAC_ORHI_RXO_Pos) /**< \brief (GMAC_ORHI) Received Octets */ +/* -------- GMAC_FR : (GMAC Offset: 0x158) Frames Received Register -------- */ +#define GMAC_FR_FRX_Pos 0 +#define GMAC_FR_FRX_Msk (0xffffffffu << GMAC_FR_FRX_Pos) /**< \brief (GMAC_FR) Frames Received without Error */ +/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) Broadcast Frames Received Register -------- */ +#define GMAC_BCFR_BFRX_Pos 0 +#define GMAC_BCFR_BFRX_Msk (0xffffffffu << GMAC_BCFR_BFRX_Pos) /**< \brief (GMAC_BCFR) Broadcast Frames Received without Error */ +/* -------- GMAC_MFR : (GMAC Offset: 0x160) Multicast Frames Received Register -------- */ +#define GMAC_MFR_MFRX_Pos 0 +#define GMAC_MFR_MFRX_Msk (0xffffffffu << GMAC_MFR_MFRX_Pos) /**< \brief (GMAC_MFR) Multicast Frames Received without Error */ +/* -------- GMAC_PFR : (GMAC Offset: 0x164) Pause Frames Received Register -------- */ +#define GMAC_PFR_PFRX_Pos 0 +#define GMAC_PFR_PFRX_Msk (0xffffu << GMAC_PFR_PFRX_Pos) /**< \brief (GMAC_PFR) Pause Frames Received Register */ +/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) 64 Byte Frames Received Register -------- */ +#define GMAC_BFR64_NFRX_Pos 0 +#define GMAC_BFR64_NFRX_Msk (0xffffffffu << GMAC_BFR64_NFRX_Pos) /**< \brief (GMAC_BFR64) 64 Byte Frames Received without Error */ +/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) 65 to 127 Byte Frames Received Register -------- */ +#define GMAC_TBFR127_NFRX_Pos 0 +#define GMAC_TBFR127_NFRX_Msk (0xffffffffu << GMAC_TBFR127_NFRX_Pos) /**< \brief (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error */ +/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) 128 to 255 Byte Frames Received Register -------- */ +#define GMAC_TBFR255_NFRX_Pos 0 +#define GMAC_TBFR255_NFRX_Msk (0xffffffffu << GMAC_TBFR255_NFRX_Pos) /**< \brief (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error */ +/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) 256 to 511Byte Frames Received Register -------- */ +#define GMAC_TBFR511_NFRX_Pos 0 +#define GMAC_TBFR511_NFRX_Msk (0xffffffffu << GMAC_TBFR511_NFRX_Pos) /**< \brief (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error */ +/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) 512 to 1023 Byte Frames Received Register -------- */ +#define GMAC_TBFR1023_NFRX_Pos 0 +#define GMAC_TBFR1023_NFRX_Msk (0xffffffffu << GMAC_TBFR1023_NFRX_Pos) /**< \brief (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error */ +/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) 1024 to 1518 Byte Frames Received Register -------- */ +#define GMAC_TBFR1518_NFRX_Pos 0 +#define GMAC_TBFR1518_NFRX_Msk (0xffffffffu << GMAC_TBFR1518_NFRX_Pos) /**< \brief (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error */ +/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) 1519 to Maximum Byte Frames Received Register -------- */ +#define GMAC_TMXBFR_NFRX_Pos 0 +#define GMAC_TMXBFR_NFRX_Msk (0xffffffffu << GMAC_TMXBFR_NFRX_Pos) /**< \brief (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error */ +/* -------- GMAC_UFR : (GMAC Offset: 0x184) Undersize Frames Received Register -------- */ +#define GMAC_UFR_UFRX_Pos 0 +#define GMAC_UFR_UFRX_Msk (0x3ffu << GMAC_UFR_UFRX_Pos) /**< \brief (GMAC_UFR) Undersize Frames Received */ +/* -------- GMAC_OFR : (GMAC Offset: 0x188) Oversize Frames Received Register -------- */ +#define GMAC_OFR_OFRX_Pos 0 +#define GMAC_OFR_OFRX_Msk (0x3ffu << GMAC_OFR_OFRX_Pos) /**< \brief (GMAC_OFR) Oversized Frames Received */ +/* -------- GMAC_JR : (GMAC Offset: 0x18C) Jabbers Received Register -------- */ +#define GMAC_JR_JRX_Pos 0 +#define GMAC_JR_JRX_Msk (0x3ffu << GMAC_JR_JRX_Pos) /**< \brief (GMAC_JR) Jabbers Received */ +/* -------- GMAC_FCSE : (GMAC Offset: 0x190) Frame Check Sequence Errors Register -------- */ +#define GMAC_FCSE_FCKR_Pos 0 +#define GMAC_FCSE_FCKR_Msk (0x3ffu << GMAC_FCSE_FCKR_Pos) /**< \brief (GMAC_FCSE) Frame Check Sequence Errors */ +/* -------- GMAC_LFFE : (GMAC Offset: 0x194) Length Field Frame Errors Register -------- */ +#define GMAC_LFFE_LFER_Pos 0 +#define GMAC_LFFE_LFER_Msk (0x3ffu << GMAC_LFFE_LFER_Pos) /**< \brief (GMAC_LFFE) Length Field Frame Errors */ +/* -------- GMAC_RSE : (GMAC Offset: 0x198) Receive Symbol Errors Register -------- */ +#define GMAC_RSE_RXSE_Pos 0 +#define GMAC_RSE_RXSE_Msk (0x3ffu << GMAC_RSE_RXSE_Pos) /**< \brief (GMAC_RSE) Receive Symbol Errors */ +/* -------- GMAC_AE : (GMAC Offset: 0x19C) Alignment Errors Register -------- */ +#define GMAC_AE_AER_Pos 0 +#define GMAC_AE_AER_Msk (0x3ffu << GMAC_AE_AER_Pos) /**< \brief (GMAC_AE) Alignment Errors */ +/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) Receive Resource Errors Register -------- */ +#define GMAC_RRE_RXRER_Pos 0 +#define GMAC_RRE_RXRER_Msk (0x3ffffu << GMAC_RRE_RXRER_Pos) /**< \brief (GMAC_RRE) Receive Resource Errors */ +/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) Receive Overrun Register -------- */ +#define GMAC_ROE_RXOVR_Pos 0 +#define GMAC_ROE_RXOVR_Msk (0x3ffu << GMAC_ROE_RXOVR_Pos) /**< \brief (GMAC_ROE) Receive Overruns */ +/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) IP Header Checksum Errors Register -------- */ +#define GMAC_IHCE_HCKER_Pos 0 +#define GMAC_IHCE_HCKER_Msk (0xffu << GMAC_IHCE_HCKER_Pos) /**< \brief (GMAC_IHCE) IP Header Checksum Errors */ +/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) TCP Checksum Errors Register -------- */ +#define GMAC_TCE_TCKER_Pos 0 +#define GMAC_TCE_TCKER_Msk (0xffu << GMAC_TCE_TCKER_Pos) /**< \brief (GMAC_TCE) TCP Checksum Errors */ +/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) UDP Checksum Errors Register -------- */ +#define GMAC_UCE_UCKER_Pos 0 +#define GMAC_UCE_UCKER_Msk (0xffu << GMAC_UCE_UCKER_Pos) /**< \brief (GMAC_UCE) UDP Checksum Errors */ +/* -------- GMAC_TSSS : (GMAC Offset: 0x1C8) 1588 Timer Sync Strobe Seconds Register -------- */ +#define GMAC_TSSS_VTS_Pos 0 +#define GMAC_TSSS_VTS_Msk (0xffffffffu << GMAC_TSSS_VTS_Pos) /**< \brief (GMAC_TSSS) Value of Timer Seconds Register Capture */ +#define GMAC_TSSS_VTS(value) ((GMAC_TSSS_VTS_Msk & ((value) << GMAC_TSSS_VTS_Pos))) +/* -------- GMAC_TSSN : (GMAC Offset: 0x1CC) 1588 Timer Sync Strobe Nanoseconds Register -------- */ +#define GMAC_TSSN_VTN_Pos 0 +#define GMAC_TSSN_VTN_Msk (0x3fffffffu << GMAC_TSSN_VTN_Pos) /**< \brief (GMAC_TSSN) Value Timer Nanoseconds Register Capture */ +#define GMAC_TSSN_VTN(value) ((GMAC_TSSN_VTN_Msk & ((value) << GMAC_TSSN_VTN_Pos))) +/* -------- GMAC_TS : (GMAC Offset: 0x1D0) 1588 Timer Seconds Register -------- */ +#define GMAC_TS_TCS_Pos 0 +#define GMAC_TS_TCS_Msk (0xffffffffu << GMAC_TS_TCS_Pos) /**< \brief (GMAC_TS) Timer Count in Seconds */ +#define GMAC_TS_TCS(value) ((GMAC_TS_TCS_Msk & ((value) << GMAC_TS_TCS_Pos))) +/* -------- GMAC_TN : (GMAC Offset: 0x1D4) 1588 Timer Nanoseconds Register -------- */ +#define GMAC_TN_TNS_Pos 0 +#define GMAC_TN_TNS_Msk (0x3fffffffu << GMAC_TN_TNS_Pos) /**< \brief (GMAC_TN) Timer Count in Nanoseconds */ +#define GMAC_TN_TNS(value) ((GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos))) +/* -------- GMAC_TA : (GMAC Offset: 0x1D8) 1588 Timer Adjust Register -------- */ +#define GMAC_TA_ITDT_Pos 0 +#define GMAC_TA_ITDT_Msk (0x3fffffffu << GMAC_TA_ITDT_Pos) /**< \brief (GMAC_TA) Increment/Decrement */ +#define GMAC_TA_ITDT(value) ((GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos))) +#define GMAC_TA_ADJ (0x1u << 31) /**< \brief (GMAC_TA) Adjust 1588 Timer */ +/* -------- GMAC_TI : (GMAC Offset: 0x1DC) 1588 Timer Increment Register -------- */ +#define GMAC_TI_CNS_Pos 0 +#define GMAC_TI_CNS_Msk (0xffu << GMAC_TI_CNS_Pos) /**< \brief (GMAC_TI) Count Nanoseconds */ +#define GMAC_TI_CNS(value) ((GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos))) +#define GMAC_TI_ACNS_Pos 8 +#define GMAC_TI_ACNS_Msk (0xffu << GMAC_TI_ACNS_Pos) /**< \brief (GMAC_TI) Alternative Count Nanoseconds */ +#define GMAC_TI_ACNS(value) ((GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos))) +#define GMAC_TI_NIT_Pos 16 +#define GMAC_TI_NIT_Msk (0xffu << GMAC_TI_NIT_Pos) /**< \brief (GMAC_TI) Number of Increments */ +#define GMAC_TI_NIT(value) ((GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos))) +/* -------- GMAC_EFTS : (GMAC Offset: 0x1E0) PTP Event Frame Transmitted Seconds -------- */ +#define GMAC_EFTS_RUD_Pos 0 +#define GMAC_EFTS_RUD_Msk (0xffffffffu << GMAC_EFTS_RUD_Pos) /**< \brief (GMAC_EFTS) Register Update */ +/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds -------- */ +#define GMAC_EFTN_RUD_Pos 0 +#define GMAC_EFTN_RUD_Msk (0x3fffffffu << GMAC_EFTN_RUD_Pos) /**< \brief (GMAC_EFTN) Register Update */ +/* -------- GMAC_EFRS : (GMAC Offset: 0x1E8) PTP Event Frame Received Seconds -------- */ +#define GMAC_EFRS_RUD_Pos 0 +#define GMAC_EFRS_RUD_Msk (0xffffffffu << GMAC_EFRS_RUD_Pos) /**< \brief (GMAC_EFRS) Register Update */ +/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) PTP Event Frame Received Nanoseconds -------- */ +#define GMAC_EFRN_RUD_Pos 0 +#define GMAC_EFRN_RUD_Msk (0x3fffffffu << GMAC_EFRN_RUD_Pos) /**< \brief (GMAC_EFRN) Register Update */ +/* -------- GMAC_PEFTS : (GMAC Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds -------- */ +#define GMAC_PEFTS_RUD_Pos 0 +#define GMAC_PEFTS_RUD_Msk (0xffffffffu << GMAC_PEFTS_RUD_Pos) /**< \brief (GMAC_PEFTS) Register Update */ +/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds -------- */ +#define GMAC_PEFTN_RUD_Pos 0 +#define GMAC_PEFTN_RUD_Msk (0x3fffffffu << GMAC_PEFTN_RUD_Pos) /**< \brief (GMAC_PEFTN) Register Update */ +/* -------- GMAC_PEFRS : (GMAC Offset: 0x1F8) PTP Peer Event Frame Received Seconds -------- */ +#define GMAC_PEFRS_RUD_Pos 0 +#define GMAC_PEFRS_RUD_Msk (0xffffffffu << GMAC_PEFRS_RUD_Pos) /**< \brief (GMAC_PEFRS) Register Update */ +/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds -------- */ +#define GMAC_PEFRN_RUD_Pos 0 +#define GMAC_PEFRN_RUD_Msk (0x3fffffffu << GMAC_PEFRN_RUD_Pos) /**< \brief (GMAC_PEFRN) Register Update */ +/* -------- GMAC_ISRPQ[7] : (GMAC Offset: 0x400) Interrupt Status Register Priority Queue -------- */ +#define GMAC_ISRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_ISRPQ[7]) Receive Complete */ +#define GMAC_ISRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_ISRPQ[7]) RX Used Bit Read */ +#define GMAC_ISRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_ISRPQ[7]) Retry Limit Exceeded or Late Collision */ +#define GMAC_ISRPQ_TFC (0x1u << 6) /**< \brief (GMAC_ISRPQ[7]) Transmit Frame Corruption due to AHB error */ +#define GMAC_ISRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_ISRPQ[7]) Transmit Complete */ +#define GMAC_ISRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_ISRPQ[7]) Receive Overrun */ +#define GMAC_ISRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_ISRPQ[7]) HRESP Not OK */ +/* -------- GMAC_TBQBAPQ[7] : (GMAC Offset: 0x440) Transmit Buffer Queue Base Address Priority Queue -------- */ +#define GMAC_TBQBAPQ_TXBQBA_Pos 2 +#define GMAC_TBQBAPQ_TXBQBA_Msk (0x3fu << GMAC_TBQBAPQ_TXBQBA_Pos) /**< \brief (GMAC_TBQBAPQ[7]) Transmit Buffer Queue Base Address */ +#define GMAC_TBQBAPQ_TXBQBA(value) ((GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos))) +/* -------- GMAC_RBQBAPQ[7] : (GMAC Offset: 0x480) Receive Buffer Queue Base Address Priority Queue -------- */ +#define GMAC_RBQBAPQ_RXBQBA_Pos 2 +#define GMAC_RBQBAPQ_RXBQBA_Msk (0x3fu << GMAC_RBQBAPQ_RXBQBA_Pos) /**< \brief (GMAC_RBQBAPQ[7]) Receive Buffer Queue Base Address */ +#define GMAC_RBQBAPQ_RXBQBA(value) ((GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos))) +/* -------- GMAC_RBSRPQ[7] : (GMAC Offset: 0x4A0) Receive Buffer Size Register Priority Queue -------- */ +#define GMAC_RBSRPQ_RBS_Pos 0 +#define GMAC_RBSRPQ_RBS_Msk (0xffffu << GMAC_RBSRPQ_RBS_Pos) /**< \brief (GMAC_RBSRPQ[7]) Receive Buffer Size */ +#define GMAC_RBSRPQ_RBS(value) ((GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos))) +/* -------- GMAC_ST1RPQ[16] : (GMAC Offset: 0x500) Screening Type1 Register Priority Queue -------- */ +#define GMAC_ST1RPQ_QNB_Pos 0 +#define GMAC_ST1RPQ_QNB_Msk (0xfu << GMAC_ST1RPQ_QNB_Pos) /**< \brief (GMAC_ST1RPQ[16]) Que Number (0->7) */ +#define GMAC_ST1RPQ_QNB(value) ((GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos))) +#define GMAC_ST1RPQ_DSTCM_Pos 4 +#define GMAC_ST1RPQ_DSTCM_Msk (0xffu << GMAC_ST1RPQ_DSTCM_Pos) /**< \brief (GMAC_ST1RPQ[16]) Differentiated Services or Traffic Class Match */ +#define GMAC_ST1RPQ_DSTCM(value) ((GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos))) +#define GMAC_ST1RPQ_UDPM_Pos 12 +#define GMAC_ST1RPQ_UDPM_Msk (0xffffu << GMAC_ST1RPQ_UDPM_Pos) /**< \brief (GMAC_ST1RPQ[16]) UDP Port Match */ +#define GMAC_ST1RPQ_UDPM(value) ((GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos))) +#define GMAC_ST1RPQ_DSTCE (0x1u << 28) /**< \brief (GMAC_ST1RPQ[16]) Differentiated Services or Traffic Class Match Enable */ +#define GMAC_ST1RPQ_UDPE (0x1u << 29) /**< \brief (GMAC_ST1RPQ[16]) UDP Port Match Enable */ +/* -------- GMAC_ST2RPQ[16] : (GMAC Offset: 0x540) Screening Type2 Register Priority Queue -------- */ +#define GMAC_ST2RPQ_QNB_Pos 0 +#define GMAC_ST2RPQ_QNB_Msk (0xfu << GMAC_ST2RPQ_QNB_Pos) /**< \brief (GMAC_ST2RPQ[16]) Que Number (0->7) */ +#define GMAC_ST2RPQ_QNB(value) ((GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos))) +#define GMAC_ST2RPQ_VLANP_Pos 4 +#define GMAC_ST2RPQ_VLANP_Msk (0xfu << GMAC_ST2RPQ_VLANP_Pos) /**< \brief (GMAC_ST2RPQ[16]) VLAN Priority */ +#define GMAC_ST2RPQ_VLANP(value) ((GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos))) +#define GMAC_ST2RPQ_VLANE (0x1u << 8) /**< \brief (GMAC_ST2RPQ[16]) VLAN Enable */ +/* -------- GMAC_IERPQ[7] : (GMAC Offset: 0x600) Interrupt Enable Register Priority Queue -------- */ +#define GMAC_IERPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IERPQ[7]) Receive Complete */ +#define GMAC_IERPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IERPQ[7]) RX Used Bit Read */ +#define GMAC_IERPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IERPQ[7]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IERPQ_TFC (0x1u << 6) /**< \brief (GMAC_IERPQ[7]) Transmit Frame Corruption due to AHB error */ +#define GMAC_IERPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IERPQ[7]) Transmit Complete */ +#define GMAC_IERPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IERPQ[7]) Receive Overrun */ +#define GMAC_IERPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IERPQ[7]) HRESP Not OK */ +/* -------- GMAC_IDRPQ[7] : (GMAC Offset: 0x620) Interrupt Disable Register Priority Queue -------- */ +#define GMAC_IDRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IDRPQ[7]) Receive Complete */ +#define GMAC_IDRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IDRPQ[7]) RX Used Bit Read */ +#define GMAC_IDRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IDRPQ[7]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IDRPQ_TFC (0x1u << 6) /**< \brief (GMAC_IDRPQ[7]) Transmit Frame Corruption due to AHB error */ +#define GMAC_IDRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IDRPQ[7]) Transmit Complete */ +#define GMAC_IDRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IDRPQ[7]) Receive Overrun */ +#define GMAC_IDRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IDRPQ[7]) HRESP Not OK */ +/* -------- GMAC_IMRPQ[7] : (GMAC Offset: 0x640) Interrupt Mask Register Priority Queue -------- */ +#define GMAC_IMRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IMRPQ[7]) Receive Complete */ +#define GMAC_IMRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IMRPQ[7]) RX Used Bit Read */ +#define GMAC_IMRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IMRPQ[7]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IMRPQ_AHB (0x1u << 6) /**< \brief (GMAC_IMRPQ[7]) AHB Error */ +#define GMAC_IMRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IMRPQ[7]) Transmit Complete */ +#define GMAC_IMRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IMRPQ[7]) Receive Overrun */ +#define GMAC_IMRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IMRPQ[7]) HRESP Not OK */ + +/*@}*/ + + +#endif /* _SAM4E_GMAC_COMPONENT_ */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/ethernet_phy.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/ethernet_phy.c new file mode 100644 index 0000000..fe9e296 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/ethernet_phy.c @@ -0,0 +1,454 @@ + /** + * \file + * + * \brief API driver for KSZ8051MNL PHY component. + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/* Standard includes. */ +#include +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "FreeRTOSIPConfig.h" + +#include "ethernet_phy.h" +#include "instance/gmac.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup ksz8051mnl_ethernet_phy_group PHY component (KSZ8051MNL) + * + * Driver for the ksz8051mnl component. This driver provides access to the main + * features of the PHY. + * + * \section dependencies Dependencies + * This driver depends on the following modules: + * - \ref gmac_group Ethernet Media Access Controller (GMAC) module. + * + * @{ + */ + +SPhyProps phyProps; + +/* Max PHY number */ +#define ETH_PHY_MAX_ADDR 31 + +/* Ethernet PHY operation max retry count */ +#define ETH_PHY_RETRY_MAX 1000000 + +/* Ethernet PHY operation timeout */ +#define ETH_PHY_TIMEOUT 10 + +/** + * \brief Find a valid PHY Address ( from addrStart to 31 ). + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_phy_addr PHY address. + * \param uc_start_addr Start address of the PHY to be searched. + * + * \return 0xFF when no valid PHY address is found. + */ +int ethernet_phy_addr = 0; +static uint8_t ethernet_phy_find_valid(Gmac *p_gmac, uint8_t uc_phy_addr, + uint8_t uc_start_addr) +{ + uint32_t ul_value = 0; + uint8_t uc_cnt; + uint8_t uc_phy_address = uc_phy_addr; + + gmac_enable_management(p_gmac, true); +/* +#define GMII_OUI_MSB 0x0022 +#define GMII_OUI_LSB 0x05 + +PHYID1 = 0x0022 +PHYID2 = 0x1550 +0001_0101_0101_0000 = 0x1550 <= mask should be 0xFFF0 +*/ + /* Check the current PHY address */ + gmac_phy_read(p_gmac, uc_phy_addr, GMII_PHYID1, &ul_value); + + /* Find another one */ + if (ul_value != GMII_OUI_MSB) { + ethernet_phy_addr = 0xFF; + for (uc_cnt = uc_start_addr; uc_cnt <= ETH_PHY_MAX_ADDR; uc_cnt++) { + uc_phy_address = (uc_phy_address + 1) & 0x1F; + ul_value = 0; + gmac_phy_read(p_gmac, uc_phy_address, GMII_PHYID1, &ul_value); + if (ul_value == GMII_OUI_MSB) { + ethernet_phy_addr = uc_phy_address; + break; + } + } + } + + gmac_enable_management(p_gmac, false); + + if (ethernet_phy_addr != 0xFF) { + gmac_phy_read(p_gmac, uc_phy_address, GMII_BMSR, &ul_value); + } + return ethernet_phy_addr; +} + + +/** + * \brief Perform a HW initialization to the PHY and set up clocks. + * + * This should be called only once to initialize the PHY pre-settings. + * The PHY address is the reset status of CRS, RXD[3:0] (the emacPins' pullups). + * The COL pin is used to select MII mode on reset (pulled up for Reduced MII). + * The RXDV pin is used to select test mode on reset (pulled up for test mode). + * The above pins should be predefined for corresponding settings in resetPins. + * The GMAC peripheral pins are configured after the reset is done. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_phy_addr PHY address. + * \param ul_mck GMAC MCK. + * + * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout. + */ +uint8_t ethernet_phy_init(Gmac *p_gmac, uint8_t uc_phy_addr, uint32_t mck) +{ + uint8_t uc_rc = GMAC_TIMEOUT; + uint8_t uc_phy; + + ethernet_phy_reset(GMAC,uc_phy_addr); + + /* Configure GMAC runtime clock */ + uc_rc = gmac_set_mdc_clock(p_gmac, mck); + if (uc_rc != GMAC_OK) { + return 0; + } + + /* Check PHY Address */ + uc_phy = ethernet_phy_find_valid(p_gmac, uc_phy_addr, 0); + if (uc_phy == 0xFF) { + return 0; + } + if (uc_phy != uc_phy_addr) { + ethernet_phy_reset(p_gmac, uc_phy_addr); + } + phy_props.phy_chn = uc_phy; + return uc_phy; +} + + +/** + * \brief Get the Link & speed settings, and automatically set up the GMAC with the + * settings. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_phy_addr PHY address. + * \param uc_apply_setting_flag Set to 0 to not apply the PHY configurations, else to apply. + * + * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout. + */ +uint8_t ethernet_phy_set_link(Gmac *p_gmac, uint8_t uc_phy_addr, + uint8_t uc_apply_setting_flag) +{ + uint32_t ul_stat1; + uint32_t ul_stat2; + uint8_t uc_phy_address, uc_speed = true, uc_fd = true; + uint8_t uc_rc = GMAC_TIMEOUT; + + gmac_enable_management(p_gmac, true); + + uc_phy_address = uc_phy_addr; + + uc_rc = gmac_phy_read(p_gmac, uc_phy_address, GMII_BMSR, &ul_stat1); + if (uc_rc != GMAC_OK) { + /* Disable PHY management and start the GMAC transfer */ + gmac_enable_management(p_gmac, false); + + return uc_rc; + } + if ((ul_stat1 & GMII_LINK_STATUS) == 0) { + /* Disable PHY management and start the GMAC transfer */ + gmac_enable_management(p_gmac, false); + + return GMAC_INVALID; + } + + if (uc_apply_setting_flag == 0) { + /* Disable PHY management and start the GMAC transfer */ + gmac_enable_management(p_gmac, false); + + return uc_rc; + } + + /* Read advertisement */ + uc_rc = gmac_phy_read(p_gmac, uc_phy_address, GMII_ANAR, &ul_stat2); +phy_props.phy_stat1 = ul_stat1; +phy_props.phy_stat2 = ul_stat2; + if (uc_rc != GMAC_OK) { + /* Disable PHY management and start the GMAC transfer */ + gmac_enable_management(p_gmac, false); + + return uc_rc; + } + + if ((ul_stat1 & GMII_100BASE_TX_FD) && (ul_stat2 & GMII_100TX_FDX)) { + /* Set GMAC for 100BaseTX and Full Duplex */ + uc_speed = true; + uc_fd = true; + } else + if ((ul_stat1 & GMII_100BASE_T4_HD) && (ul_stat2 & GMII_100TX_HDX)) { + /* Set MII for 100BaseTX and Half Duplex */ + uc_speed = true; + uc_fd = false; + } else + if ((ul_stat1 & GMII_10BASE_T_FD) && (ul_stat2 & GMII_10_FDX)) { + /* Set MII for 10BaseT and Full Duplex */ + uc_speed = false; + uc_fd = true; + } else + if ((ul_stat1 & GMII_10BASE_T_HD) && (ul_stat2 & GMII_10_HDX)) { + /* Set MII for 10BaseT and Half Duplex */ + uc_speed = false; + uc_fd = false; + } + + gmac_set_speed(p_gmac, uc_speed); + gmac_enable_full_duplex(p_gmac, uc_fd); + + /* Start the GMAC transfers */ + gmac_enable_management(p_gmac, false); + return uc_rc; +} + +PhyProps_t phy_props; + +/** + * \brief Issue an auto negotiation of the PHY. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_phy_addr PHY address. + * + * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout. + */ +uint8_t ethernet_phy_auto_negotiate(Gmac *p_gmac, uint8_t uc_phy_addr) +{ + uint32_t ul_retry_max = ETH_PHY_RETRY_MAX; + uint32_t ul_value; + uint32_t ul_phy_anar; + uint32_t ul_retry_count = 0; + uint8_t uc_speed = 0; + uint8_t uc_fd=0; + uint8_t uc_rc = GMAC_TIMEOUT; + + gmac_enable_management(p_gmac, true); + + /* Set up control register */ + uc_rc = gmac_phy_read(p_gmac, uc_phy_addr, GMII_BMCR, &ul_value); + if (uc_rc != GMAC_OK) { + gmac_enable_management(p_gmac, false); +phy_props.phy_result = -1; + return uc_rc; + } + + ul_value &= ~(uint32_t)GMII_AUTONEG; /* Remove auto-negotiation enable */ + ul_value &= ~(uint32_t)(GMII_LOOPBACK | GMII_POWER_DOWN); + ul_value |= (uint32_t)GMII_ISOLATE; /* Electrically isolate PHY */ + uc_rc = gmac_phy_write(p_gmac, uc_phy_addr, GMII_BMCR, ul_value); + if (uc_rc != GMAC_OK) { + gmac_enable_management(p_gmac, false); +phy_props.phy_result = -2; + return uc_rc; + } + + /* + * Set the Auto_negotiation Advertisement Register. + * MII advertising for Next page. + * 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3. + */ + ul_phy_anar = GMII_100TX_FDX | GMII_100TX_HDX | GMII_10_FDX | GMII_10_HDX | + GMII_AN_IEEE_802_3; + uc_rc = gmac_phy_write(p_gmac, uc_phy_addr, GMII_ANAR, ul_phy_anar); + if (uc_rc != GMAC_OK) { + gmac_enable_management(p_gmac, false); +phy_props.phy_result = -3; + return uc_rc; + } + + /* Read & modify control register */ + uc_rc = gmac_phy_read(p_gmac, uc_phy_addr, GMII_BMCR, &ul_value); + if (uc_rc != GMAC_OK) { + gmac_enable_management(p_gmac, false); +phy_props.phy_result = -4; + return uc_rc; + } + + ul_value |= GMII_SPEED_SELECT | GMII_AUTONEG | GMII_DUPLEX_MODE; + uc_rc = gmac_phy_write(p_gmac, uc_phy_addr, GMII_BMCR, ul_value); + if (uc_rc != GMAC_OK) { + gmac_enable_management(p_gmac, false); +phy_props.phy_result = -5; + return uc_rc; + } + + /* Restart auto negotiation */ + ul_value |= (uint32_t)GMII_RESTART_AUTONEG; + ul_value &= ~(uint32_t)GMII_ISOLATE; + uc_rc = gmac_phy_write(p_gmac, uc_phy_addr, GMII_BMCR, ul_value); + if (uc_rc != GMAC_OK) { + gmac_enable_management(p_gmac, false); +phy_props.phy_result = -6; + return uc_rc; + } + + /* Check if auto negotiation is completed */ + while (1) { + uc_rc = gmac_phy_read(p_gmac, uc_phy_addr, GMII_BMSR, &ul_value); + if (uc_rc != GMAC_OK) { + gmac_enable_management(p_gmac, false); +phy_props.phy_result = -7; + return uc_rc; + } + /* Done successfully */ + if (ul_value & GMII_AUTONEG_COMP) { + break; + } + + /* Timeout check */ + if (ul_retry_max) { + if (++ul_retry_count >= ul_retry_max) { + gmac_enable_management(p_gmac, false); +phy_props.phy_result = -8; + return GMAC_TIMEOUT; + } + } + } + + /* Get the auto negotiate link partner base page */ + uc_rc = gmac_phy_read(p_gmac, uc_phy_addr, GMII_PCR1, &phy_props.phy_params); + if (uc_rc != GMAC_OK) { + gmac_enable_management(p_gmac, false); +phy_props.phy_result = -9; + return uc_rc; + } + + + /* Set up the GMAC link speed */ + if ((ul_phy_anar & phy_props.phy_params) & GMII_100TX_FDX) { + /* Set MII for 100BaseTX and Full Duplex */ + uc_speed = true; + uc_fd = true; + } else if ((ul_phy_anar & phy_props.phy_params) & GMII_10_FDX) { + /* Set MII for 10BaseT and Full Duplex */ + uc_speed = false; + uc_fd = true; + } else if ((ul_phy_anar & phy_props.phy_params) & GMII_100TX_HDX) { + /* Set MII for 100BaseTX and half Duplex */ + uc_speed = true; + uc_fd = false; + } else if ((ul_phy_anar & phy_props.phy_params) & GMII_10_HDX) { + /* Set MII for 10BaseT and half Duplex */ + uc_speed = false; + uc_fd = false; + } + + gmac_set_speed(p_gmac, uc_speed); + gmac_enable_full_duplex(p_gmac, uc_fd); + + /* Select Media Independent Interface type */ + gmac_select_mii_mode(p_gmac, ETH_PHY_MODE); + + gmac_enable_transmit(GMAC, true); + gmac_enable_receive(GMAC, true); + + gmac_enable_management(p_gmac, false); +phy_props.phy_result = 1; + return uc_rc; +} + +/** + * \brief Issue a SW reset to reset all registers of the PHY. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_phy_addr PHY address. + * + * \Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout. + */ +uint8_t ethernet_phy_reset(Gmac *p_gmac, uint8_t uc_phy_addr) +{ + uint32_t ul_bmcr = GMII_RESET; + uint8_t uc_phy_address = uc_phy_addr; + uint32_t ul_timeout = ETH_PHY_TIMEOUT; + uint8_t uc_rc = GMAC_TIMEOUT; + + gmac_enable_management(p_gmac, true); + + ul_bmcr = GMII_RESET; + gmac_phy_write(p_gmac, uc_phy_address, GMII_BMCR, ul_bmcr); + + do { + gmac_phy_read(p_gmac, uc_phy_address, GMII_BMCR, &ul_bmcr); + ul_timeout--; + } while ((ul_bmcr & GMII_RESET) && ul_timeout); + + gmac_enable_management(p_gmac, false); + + if (!ul_timeout) { + uc_rc = GMAC_OK; + } + + return (uc_rc); +} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \} + */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/ethernet_phy.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/ethernet_phy.h new file mode 100644 index 0000000..8ea5fa0 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/ethernet_phy.h @@ -0,0 +1,281 @@ +/** + * \file + * + * \brief KSZ8051MNL (Ethernet PHY) driver for SAM. + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef ETHERNET_PHY_H_INCLUDED +#define ETHERNET_PHY_H_INCLUDED + +#include "compiler.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// IEEE defined Registers +#define GMII_BMCR 0x00 // Basic Control +#define GMII_BMSR 0x01 // Basic Status +#define GMII_PHYID1 0x02 // PHY Idendifier 1 +#define GMII_PHYID2 0x03 // PHY Idendifier 2 +#define GMII_ANAR 0x04 // Auto_Negotiation Advertisement +#define GMII_ANLPAR 0x05 // Auto_negotiation Link Partner Ability +#define GMII_ANER 0x06 // Auto-negotiation Expansion +#define GMII_ANNPR 0x07 // Auto-negotiation Next Page +#define GMII_ANLPNPAR 0x08 // Link Partner Next Page Ability +//#define GMII_1000BTCR 9 // 1000Base-T Control // Reserved +//#define GMII_1000BTSR 10 // 1000Base-T Status // Reserved +#define GMII_AFECR1 0x11 // AFE Control 1 +//#define GMII_ERDWR 12 // Extend Register - Data Write Register +//#define GMII_ERDRR 13 // Extend Register - Data Read Register +//14 reserved +#define GMII_RXERCR 0x15 // RXER Counter + + #define PHY_REG_01_BMSR 0x01 // Basic mode status register + #define PHY_REG_02_PHYSID1 0x02 // PHYS ID 1 + #define PHY_REG_03_PHYSID2 0x03 // PHYS ID 2 + #define PHY_REG_04_ADVERTISE 0x04 // Advertisement control reg + #define PHY_REG_05_LPA 0x05 // Link partner ability reg + #define PHY_REG_06_ANER 0x06 // 6 RW Auto-Negotiation Expansion Register + #define PHY_REG_07_ANNPTR 0x07 // 7 RW Auto-Negotiation Next Page TX + #define PHY_REG_08_RESERVED0 0x08 // 0x08..0x0Fh 8-15 RW RESERVED + + #define PHY_REG_10_PHYSTS 0x10 // 16 RO PHY Status Register + #define PHY_REG_11_MICR 0x11 // 17 RW MII Interrupt Control Register + #define PHY_REG_12_MISR 0x12 // 18 RO MII Interrupt Status Register + #define PHY_REG_13_RESERVED1 0x13 // 19 RW RESERVED + #define PHY_REG_14_FCSCR 0x14 // 20 RO False Carrier Sense Counter Register + #define PHY_REG_15_RECR 0x15 // 21 RO Receive Error Counter Register + #define PHY_REG_16_PCSR 0x16 // 22 RW PCS Sub-Layer Configuration and Status Register + #define PHY_REG_17_RBR 0x17 // 23 RW RMII and Bypass Register + #define PHY_REG_18_LEDCR 0x18 // 24 RW LED Direct Control Register + #define PHY_REG_19_PHYCR 0x19 // 25 RW PHY Control Register + #define PHY_REG_1A_10BTSCR 0x1A // 26 RW 10Base-T Status/Control Register + #define PHY_REG_1B_CDCTRL1 0x1B // 27 RW CD Test Control Register and BIST Extensions Register + #define PHY_REG_1B_INT_CTRL 0x1B // 27 RW KSZ8041NL interrupt control + #define PHY_REG_1C_RESERVED2 0x1C // 28 RW RESERVED + #define PHY_REG_1D_EDCR 0x1D // 29 RW Energy Detect Control Register + #define PHY_REG_1E_RESERVED3 0x1E // + #define PHY_REG_1F_RESERVED4 0x1F // 30-31 RW RESERVED + + #define PHY_REG_1E_PHYCR_1 0x1E // + #define PHY_REG_1F_PHYCR_2 0x1F // + + #define PHY_SPEED_10 1 + #define PHY_SPEED_100 2 + #define PHY_SPEED_AUTO (PHY_SPEED_10|PHY_SPEED_100) + + #define PHY_MDIX_DIRECT 1 + #define PHY_MDIX_CROSSED 2 + #define PHY_MDIX_AUTO (PHY_MDIX_CROSSED|PHY_MDIX_DIRECT) + + #define PHY_DUPLEX_HALF 1 + #define PHY_DUPLEX_FULL 2 + #define PHY_DUPLEX_AUTO (PHY_DUPLEX_FULL|PHY_DUPLEX_HALF) + + typedef struct _SPhyProps { + unsigned char speed; + unsigned char mdix; + unsigned char duplex; + unsigned char spare; + } SPhyProps; + + const char *phyPrintable (const SPhyProps *apProps); + + extern SPhyProps phyProps; + +#define GMII_OMSOR 0x16 // Operation Mode Strap Override +#define GMII_OMSSR 0x17 // Operation Mode Strap Status +#define GMII_ECR 0x18 // Expanded Control +//#define GMII_DPPSR 19 // Digital PMA/PCS Status +//20 reserved +//#define GMII_RXERCR 21 // RXER Counter Register +//22-26 reserved +#define GMII_ICSR 0x1B // Interrupt Control/Status +//#define GMII_DDC1R 28 // Digital Debug Control 1 Register +#define GMII_LCSR 0x1D // LinkMD Control/Status + +//29-30 reserved +#define GMII_PCR1 0x1E // PHY Control 1 +#define GMII_PCR2 0x1F // PHY Control 2 + +/* +//Extend Registers +#define GMII_CCR 256 // Common Control Register +#define GMII_SSR 257 // Strap Status Register +#define GMII_OMSOR 258 // Operation Mode Strap Override Register +#define GMII_OMSSR 259 // Operation Mode Strap Status Register +#define GMII_RCCPSR 260 // RGMII Clock and Control Pad Skew Register +#define GMII_RRDPSR 261 // RGMII RX Data Pad Skew Register +#define GMII_ATR 263 // Analog Test Register +*/ + + +// Bit definitions: GMII_BMCR 0x00 Basic Control +#define GMII_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation +#define GMII_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation +#define GMII_SPEED_SELECT (1 << 13) // 1=100Mbps; 0=10Mbps +#define GMII_AUTONEG (1 << 12) // Auto-negotiation Enable +#define GMII_POWER_DOWN (1 << 11) // 1=Power down 0=Normal operation +#define GMII_ISOLATE (1 << 10) // 1 = Isolates 0 = Normal operation +#define GMII_RESTART_AUTONEG (1 << 9) // 1 = Restart auto-negotiation 0 = Normal operation +#define GMII_DUPLEX_MODE (1 << 8) // 1 = Full duplex operation 0 = Normal operation +#define GMII_COLLISION_TEST (1 << 7) // 1 = Enable COL test; 0 = Disable COL test +//#define GMII_SPEED_SELECT_MSB (1 << 6) // Reserved +// Reserved 6 to 0 // Read as 0, ignore on write + +// Bit definitions: GMII_BMSR 0x01 Basic Status +#define GMII_100BASE_T4 (1 << 15) // 100BASE-T4 Capable +#define GMII_100BASE_TX_FD (1 << 14) // 100BASE-TX Full Duplex Capable +#define GMII_100BASE_T4_HD (1 << 13) // 100BASE-TX Half Duplex Capable +#define GMII_10BASE_T_FD (1 << 12) // 10BASE-T Full Duplex Capable +#define GMII_10BASE_T_HD (1 << 11) // 10BASE-T Half Duplex Capable +// Reserved 10 to79 // Read as 0, ignore on write +//#define GMII_EXTEND_STATUS (1 << 8) // 1 = Extend Status Information In Reg 15 +// Reserved 7 +#define GMII_MF_PREAMB_SUPPR (1 << 6) // MII Frame Preamble Suppression +#define GMII_AUTONEG_COMP (1 << 5) // Auto-negotiation Complete +#define GMII_REMOTE_FAULT (1 << 4) // Remote Fault +#define GMII_AUTONEG_ABILITY (1 << 3) // Auto Configuration Ability +#define GMII_LINK_STATUS (1 << 2) // Link Status +#define GMII_JABBER_DETECT (1 << 1) // Jabber Detect +#define GMII_EXTEND_CAPAB (1 << 0) // Extended Capability + + +// Bit definitions: GMII_PHYID1 0x02 PHY Idendifier 1 +// Bit definitions: GMII_PHYID2 0x03 PHY Idendifier 2 +#define GMII_LSB_MASK 0x3F +#define GMII_OUI_MSB 0x0022 +#define GMII_OUI_LSB 0x05 + + +// Bit definitions: GMII_ANAR 0x04 Auto_Negotiation Advertisement +// Bit definitions: GMII_ANLPAR 0x05 Auto_negotiation Link Partner Ability +#define GMII_NP (1 << 15) // Next page Indication +// Reserved 7 +#define GMII_RF (1 << 13) // Remote Fault +// Reserved 12 // Write as 0, ignore on read +#define GMII_PAUSE_MASK (3 << 11) // 0,0 = No Pause 1,0 = Asymmetric Pause(link partner) + // 0,1 = Symmetric Pause 1,1 = Symmetric&Asymmetric Pause(local device) +#define GMII_100T4 (1 << 9) // 100BASE-T4 Support +#define GMII_100TX_FDX (1 << 8) // 100BASE-TX Full Duplex Support +#define GMII_100TX_HDX (1 << 7) // 100BASE-TX Support +#define GMII_10_FDX (1 << 6) // 10BASE-T Full Duplex Support +#define GMII_10_HDX (1 << 5) // 10BASE-T Support +// Selector 4 to 0 // Protocol Selection Bits +#define GMII_AN_IEEE_802_3 0x0001 // [00001] = IEEE 802.3 + + +// Bit definitions: GMII_ANER 0x06 Auto-negotiation Expansion +// Reserved 15 to 5 // Read as 0, ignore on write +#define GMII_PDF (1 << 4) // Local Device Parallel Detection Fault +#define GMII_LP_NP_ABLE (1 << 3) // Link Partner Next Page Able +#define GMII_NP_ABLE (1 << 2) // Local Device Next Page Able +#define GMII_PAGE_RX (1 << 1) // New Page Received +#define GMII_LP_AN_ABLE (1 << 0) // Link Partner Auto-negotiation Able + +/** + * \brief Perform a HW initialization to the PHY and set up clocks. + * + * This should be called only once to initialize the PHY pre-settings. + * The PHY address is the reset status of CRS, RXD[3:0] (the GmacPins' pullups). + * The COL pin is used to select MII mode on reset (pulled up for Reduced MII). + * The RXDV pin is used to select test mode on reset (pulled up for test mode). + * The above pins should be predefined for corresponding settings in resetPins. + * The GMAC peripheral pins are configured after the reset is done. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_phy_addr PHY address. + * \param ul_mck GMAC MCK. + * + * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout. + */ +uint8_t ethernet_phy_init(Gmac *p_gmac, uint8_t uc_phy_addr, uint32_t ul_mck); + + +/** + * \brief Get the Link & speed settings, and automatically set up the GMAC with the + * settings. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_phy_addr PHY address. + * \param uc_apply_setting_flag Set to 0 to not apply the PHY configurations, else to apply. + * + * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout. + */ +uint8_t ethernet_phy_set_link(Gmac *p_gmac, uint8_t uc_phy_addr, + uint8_t uc_apply_setting_flag); + + +/** + * \brief Issue an auto negotiation of the PHY. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_phy_addr PHY address. + * + * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout. + */ +uint8_t ethernet_phy_auto_negotiate(Gmac *p_gmac, uint8_t uc_phy_addr); + +/** + * \brief Issue a SW reset to reset all registers of the PHY. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_phy_addr PHY address. + * + * \Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout. + */ +uint8_t ethernet_phy_reset(Gmac *p_gmac, uint8_t uc_phy_addr); + +typedef struct xPHY_PROPS { + signed char phy_result; + uint32_t phy_params; + uint32_t phy_stat1; + uint32_t phy_stat2; + unsigned char phy_chn; +} PhyProps_t; +extern PhyProps_t phy_props; + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /* #ifndef ETHERNET_PHY_H_INCLUDED */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/gmac.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/gmac.c new file mode 100644 index 0000000..fe73a73 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/gmac.c @@ -0,0 +1,945 @@ + /** + * \file + * + * \brief GMAC (Ethernet MAC) driver for SAM. + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/* Standard includes. */ +#include +#include +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#include "FreeRTOSIPConfig.h" + +#include "compiler.h" +#include "instance/gmac.h" +#include "ethernet_phy.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (int)( sizeof(x) / sizeof(x)[0] ) +#endif +/** + * \defgroup gmac_group Ethernet Media Access Controller + * + * See \ref gmac_quickstart. + * + * Driver for the GMAC (Ethernet Media Access Controller). + * This file contains basic functions for the GMAC, with support for all modes, settings + * and clock speeds. + * + * \section dependencies Dependencies + * This driver does not depend on other modules. + * + * @{ + */ + +/** TX descriptor lists */ +COMPILER_ALIGNED(8) +static gmac_tx_descriptor_t gs_tx_desc[ GMAC_TX_BUFFERS ]; +#if( GMAC_USES_TX_CALLBACK != 0 ) +/** TX callback lists */ +static gmac_dev_tx_cb_t gs_tx_callback[ GMAC_TX_BUFFERS ]; +#endif +/** RX descriptors lists */ +COMPILER_ALIGNED(8) +static gmac_rx_descriptor_t gs_rx_desc[ GMAC_RX_BUFFERS ]; + +#if( ipconfigZERO_COPY_TX_DRIVER == 0 ) + /** Send Buffer. Section 3.6 of AMBA 2.0 spec states that burst should not cross the + * 1K Boundaries. Receive buffer manager write operations are burst of 2 words => 3 lsb bits + * of the address shall be set to 0. + */ + COMPILER_ALIGNED(8) + static uint8_t gs_uc_tx_buffer[ GMAC_TX_BUFFERS * GMAC_TX_UNITSIZE ]; +#endif /* ipconfigZERO_COPY_TX_DRIVER */ + +/** Receive Buffer */ +COMPILER_ALIGNED(8) +static uint8_t gs_uc_rx_buffer[ GMAC_RX_BUFFERS * GMAC_RX_UNITSIZE ]; + +/** + * GMAC device memory management struct. + */ +typedef struct gmac_dev_mem { + /* Pointer to allocated buffer for RX. The address should be 8-byte aligned + and the size should be GMAC_RX_UNITSIZE * wRxSize. */ + uint8_t *p_rx_buffer; + /* Pointer to allocated RX descriptor list. */ + gmac_rx_descriptor_t *p_rx_dscr; + /* RX size, in number of registered units (RX descriptors). */ + /* Increased size from 16- to 32-bits, because it's more efficient */ + uint32_t us_rx_size; + /* Pointer to allocated buffer for TX. The address should be 8-byte aligned + and the size should be GMAC_TX_UNITSIZE * wTxSize. */ + uint8_t *p_tx_buffer; + /* Pointer to allocated TX descriptor list. */ + gmac_tx_descriptor_t *p_tx_dscr; + /* TX size, in number of registered units (TX descriptors). */ + uint32_t us_tx_size; +} gmac_dev_mem_t; + +/** Return count in buffer */ +#define CIRC_CNT( head, tail, size ) ( ( ( head ) - ( tail ) ) % ( size ) ) + +/* + * Return space available, from 0 to size-1. + * Always leave one free char as a completely full buffer that has (head == tail), + * which is the same as empty. + */ +#define CIRC_SPACE( head, tail, size ) CIRC_CNT( ( tail ), ( ( head ) + 1 ), ( size ) ) + +/** Circular buffer is empty ? */ +#define CIRC_EMPTY( head, tail ) ( head == tail ) +/** Clear circular buffer */ +#define CIRC_CLEAR( head, tail ) do { ( head ) = 0; ( tail ) = 0; } while( 0 ) + +/** Increment head or tail */ +static __inline void circ_inc32( int32_t *lHeadOrTail, uint32_t ulSize ) +{ + ( *lHeadOrTail ) ++; + if( ( *lHeadOrTail ) >= ( int32_t )ulSize ) + { + ( *lHeadOrTail ) = 0; + } +} + +/** + * \brief Wait PHY operation to be completed. + * + * \param p_gmac HW controller address. + * \param ul_retry The retry times, 0 to wait forever until completeness. + * + * Return GMAC_OK if the operation is completed successfully. + */ +static uint8_t gmac_wait_phy(Gmac* p_gmac, const uint32_t ul_retry) +{ + volatile uint32_t ul_retry_count = 0; + const uint32_t xPHYPollDelay = pdMS_TO_TICKS( 1ul ); + + while (!gmac_is_phy_idle(p_gmac)) { + if (ul_retry == 0) { + continue; + } + + ul_retry_count++; + + if (ul_retry_count >= ul_retry) { + return GMAC_TIMEOUT; + } + + /* Block the task to allow other tasks to execute while the PHY + is not connected. */ + vTaskDelay( xPHYPollDelay ); + } + return GMAC_OK; +} + +/** + * \brief Disable transfer, reset registers and descriptor lists. + * + * \param p_dev Pointer to GMAC driver instance. + * + */ +static void gmac_reset_tx_mem(gmac_device_t* p_dev) +{ + Gmac *p_hw = p_dev->p_hw; + uint8_t *p_tx_buff = p_dev->p_tx_buffer; + gmac_tx_descriptor_t *p_td = p_dev->p_tx_dscr; + + uint32_t ul_index; + uint32_t ul_address; + + /* Disable TX */ + gmac_enable_transmit(p_hw, 0); + + /* Set up the TX descriptors */ + CIRC_CLEAR(p_dev->l_tx_head, p_dev->l_tx_tail); + for( ul_index = 0; ul_index < p_dev->ul_tx_list_size; ul_index++ ) + { + #if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + { + ul_address = (uint32_t) 0u; + } + #else + { + ul_address = (uint32_t) (&(p_tx_buff[ul_index * GMAC_TX_UNITSIZE])); + } + #endif /* ipconfigZERO_COPY_TX_DRIVER */ + p_td[ul_index].addr = ul_address; + p_td[ul_index].status.val = GMAC_TXD_USED; + } + p_td[p_dev->ul_tx_list_size - 1].status.val = + GMAC_TXD_USED | GMAC_TXD_WRAP; + + /* Set transmit buffer queue */ + gmac_set_tx_queue(p_hw, (uint32_t) p_td); +} + +/** + * \brief Disable receiver, reset registers and descriptor list. + * + * \param p_drv Pointer to GMAC Driver instance. + */ +static void gmac_reset_rx_mem(gmac_device_t* p_dev) +{ + Gmac *p_hw = p_dev->p_hw; + uint8_t *p_rx_buff = p_dev->p_rx_buffer; + gmac_rx_descriptor_t *pRd = p_dev->p_rx_dscr; + + uint32_t ul_index; + uint32_t ul_address; + + /* Disable RX */ + gmac_enable_receive(p_hw, 0); + + /* Set up the RX descriptors */ + p_dev->ul_rx_idx = 0; + for( ul_index = 0; ul_index < p_dev->ul_rx_list_size; ul_index++ ) + { + ul_address = (uint32_t) (&(p_rx_buff[ul_index * GMAC_RX_UNITSIZE])); + pRd[ul_index].addr.val = ul_address & GMAC_RXD_ADDR_MASK; + pRd[ul_index].status.val = 0; + } + pRd[p_dev->ul_rx_list_size - 1].addr.val |= GMAC_RXD_WRAP; + + /* Set receive buffer queue */ + gmac_set_rx_queue(p_hw, (uint32_t) pRd); +} + + +/** + * \brief Initialize the allocated buffer lists for GMAC driver to transfer data. + * Must be invoked after gmac_dev_init() but before RX/TX starts. + * + * \note If input address is not 8-byte aligned, the address is automatically + * adjusted and the list size is reduced by one. + * + * \param p_gmac Pointer to GMAC instance. + * \param p_gmac_dev Pointer to GMAC device instance. + * \param p_dev_mm Pointer to the GMAC memory management control block. + * \param p_tx_cb Pointer to allocated TX callback list. + * + * \return GMAC_OK or GMAC_PARAM. + */ +static uint8_t gmac_init_mem(Gmac* p_gmac, gmac_device_t* p_gmac_dev, + gmac_dev_mem_t* p_dev_mm +#if( GMAC_USES_TX_CALLBACK != 0 ) + , gmac_dev_tx_cb_t* p_tx_cb +#endif + ) +{ + if (p_dev_mm->us_rx_size <= 1 || p_dev_mm->us_tx_size <= 1 +#if( GMAC_USES_TX_CALLBACK != 0 ) + || p_tx_cb == NULL +#endif + ) { + return GMAC_PARAM; + } + + /* Assign RX buffers */ + if (((uint32_t) p_dev_mm->p_rx_buffer & 0x7) + || ((uint32_t) p_dev_mm->p_rx_dscr & 0x7)) { + p_dev_mm->us_rx_size--; + } + p_gmac_dev->p_rx_buffer = + (uint8_t *) ((uint32_t) p_dev_mm->p_rx_buffer & 0xFFFFFFF8); + p_gmac_dev->p_rx_dscr = + (gmac_rx_descriptor_t *) ((uint32_t) p_dev_mm->p_rx_dscr + & 0xFFFFFFF8); + p_gmac_dev->ul_rx_list_size = p_dev_mm->us_rx_size; + + /* Assign TX buffers */ + if (((uint32_t) p_dev_mm->p_tx_buffer & 0x7) + || ((uint32_t) p_dev_mm->p_tx_dscr & 0x7)) { + p_dev_mm->us_tx_size--; + } + p_gmac_dev->p_tx_buffer = + (uint8_t *) ((uint32_t) p_dev_mm->p_tx_buffer & 0xFFFFFFF8); + p_gmac_dev->p_tx_dscr = + (gmac_tx_descriptor_t *) ((uint32_t) p_dev_mm->p_tx_dscr + & 0xFFFFFFF8); + p_gmac_dev->ul_tx_list_size = p_dev_mm->us_tx_size; +#if( GMAC_USES_TX_CALLBACK != 0 ) + p_gmac_dev->func_tx_cb_list = p_tx_cb; +#endif + /* Reset TX & RX */ + gmac_reset_rx_mem(p_gmac_dev); + gmac_reset_tx_mem(p_gmac_dev); + + /* Enable Rx and Tx, plus the statistics register */ + gmac_enable_transmit(p_gmac, true); + gmac_enable_receive(p_gmac, true); + gmac_enable_statistics_write(p_gmac, true); + + /* Set up the interrupts for transmission and errors */ + gmac_enable_interrupt(p_gmac, + GMAC_IER_RXUBR | /* Enable receive used bit read interrupt. */ + GMAC_IER_TUR | /* Enable transmit underrun interrupt. */ + GMAC_IER_RLEX | /* Enable retry limit exceeded interrupt. */ + GMAC_IER_TFC | /* Enable transmit buffers exhausted in mid-frame interrupt. */ + GMAC_IER_TCOMP | /* Enable transmit complete interrupt. */ + GMAC_IER_ROVR | /* Enable receive overrun interrupt. */ + GMAC_IER_HRESP | /* Enable Hresp not OK interrupt. */ + GMAC_IER_PFNZ | /* Enable pause frame received interrupt. */ + GMAC_IER_PTZ); /* Enable pause time zero interrupt. */ + + return GMAC_OK; +} + +/** + * \brief Read the PHY register. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_phy_address PHY address. + * \param uc_address Register address. + * \param p_value Pointer to a 32-bit location to store read data. + * + * \Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout. + */ +uint8_t gmac_phy_read(Gmac* p_gmac, uint8_t uc_phy_address, uint8_t uc_address, + uint32_t* p_value) +{ + gmac_maintain_phy(p_gmac, uc_phy_address, uc_address, 1, 0); + + if (gmac_wait_phy(p_gmac, MAC_PHY_RETRY_MAX) == GMAC_TIMEOUT) { + return GMAC_TIMEOUT; + } + *p_value = gmac_get_phy_data(p_gmac); + return GMAC_OK; +} + +/** + * \brief Write the PHY register. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_phy_address PHY Address. + * \param uc_address Register Address. + * \param ul_value Data to write, actually 16-bit data. + * + * \Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout. + */ +uint8_t gmac_phy_write(Gmac* p_gmac, uint8_t uc_phy_address, + uint8_t uc_address, uint32_t ul_value) +{ + gmac_maintain_phy(p_gmac, uc_phy_address, uc_address, 0, ul_value); + + if (gmac_wait_phy(p_gmac, MAC_PHY_RETRY_MAX) == GMAC_TIMEOUT) { + return GMAC_TIMEOUT; + } + return GMAC_OK; +} + +/** + * \brief Initialize the GMAC driver. + * + * \param p_gmac Pointer to the GMAC instance. + * \param p_gmac_dev Pointer to the GMAC device instance. + * \param p_opt GMAC configure options. + */ +void gmac_dev_init(Gmac* p_gmac, gmac_device_t* p_gmac_dev, + gmac_options_t* p_opt) +{ + gmac_dev_mem_t gmac_dev_mm; + + /* Disable TX & RX and more */ + gmac_network_control(p_gmac, 0); + gmac_disable_interrupt(p_gmac, ~0u); + + + gmac_clear_statistics(p_gmac); + + /* Clear all status bits in the receive status register. */ + gmac_clear_rx_status(p_gmac, GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA); + + /* Clear all status bits in the transmit status register */ + gmac_clear_tx_status(p_gmac, GMAC_TSR_UBR | GMAC_TSR_COL | GMAC_TSR_RLE + | GMAC_TSR_TFC | GMAC_TSR_TXCOMP | GMAC_TSR_UND); + + /* Clear interrupts */ + gmac_get_interrupt_status(p_gmac); +#if !defined(ETHERNET_CONF_DATA_OFFSET) + /* Receive Buffer Offset + * Indicates the number of bytes by which the received data + * is offset from the start of the receive buffer + * which can be handy for alignment reasons */ + /* Note: FreeRTOS+TCP wants to have this offset set to 2 bytes */ + #error ETHERNET_CONF_DATA_OFFSET not defined, assuming 0 +#endif + /* Enable the copy of data into the buffers + ignore broadcasts, and not copy FCS. */ + + gmac_set_configure(p_gmac, + ( gmac_get_configure(p_gmac) & ~GMAC_NCFGR_RXBUFO_Msk ) | + GMAC_NCFGR_RFCS | /* Remove FCS, frame check sequence (last 4 bytes) */ + GMAC_NCFGR_PEN | /* Pause Enable */ + GMAC_NCFGR_RXBUFO( ETHERNET_CONF_DATA_OFFSET ) | + GMAC_RXD_RXCOEN ); + + /* + * GMAC_DCFGR_TXCOEN: (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable. + * Note: tha SAM4E does have RX checksum offloading + * but TX checksum offloading has NOT been implemented. + * http://community.atmel.com/forum/sam4e-gmac-transmit-checksum-offload-enablesolved + */ + + gmac_set_dma(p_gmac, + gmac_get_dma(p_gmac) | GMAC_DCFGR_TXCOEN ); + + gmac_enable_copy_all(p_gmac, p_opt->uc_copy_all_frame); + gmac_disable_broadcast(p_gmac, p_opt->uc_no_boardcast); + + /* Fill in GMAC device memory management */ + gmac_dev_mm.p_rx_buffer = gs_uc_rx_buffer; + gmac_dev_mm.p_rx_dscr = gs_rx_desc; + gmac_dev_mm.us_rx_size = GMAC_RX_BUFFERS; + + #if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + { + gmac_dev_mm.p_tx_buffer = NULL; + } + #else + { + gmac_dev_mm.p_tx_buffer = gs_uc_tx_buffer; + } + #endif + gmac_dev_mm.p_tx_dscr = gs_tx_desc; + gmac_dev_mm.us_tx_size = GMAC_TX_BUFFERS; + + gmac_init_mem(p_gmac, p_gmac_dev, &gmac_dev_mm +#if( GMAC_USES_TX_CALLBACK != 0 ) + , gs_tx_callback +#endif + ); + + gmac_set_address(p_gmac, 0, p_opt->uc_mac_addr); +} + +/** + * \brief Frames can be read from the GMAC in multiple sections. + * + * Returns > 0 if a complete frame is available + * It also it cleans up incomplete older frames + */ + +static uint32_t gmac_dev_poll(gmac_device_t* p_gmac_dev) +{ + uint32_t ulReturn = 0; + int32_t ulIndex = p_gmac_dev->ul_rx_idx; + gmac_rx_descriptor_t *pxHead = &p_gmac_dev->p_rx_dscr[ulIndex]; + + /* Discard any incomplete frames */ + while ((pxHead->addr.val & GMAC_RXD_OWNERSHIP) && + (pxHead->status.val & GMAC_RXD_SOF) == 0) { + pxHead->addr.val &= ~(GMAC_RXD_OWNERSHIP); + circ_inc32 (&ulIndex, p_gmac_dev->ul_rx_list_size); + pxHead = &p_gmac_dev->p_rx_dscr[ulIndex]; + p_gmac_dev->ul_rx_idx = ulIndex; + #if( GMAC_STATS != 0 ) + { + gmacStats.incompCount++; + } + #endif + } + + while ((pxHead->addr.val & GMAC_RXD_OWNERSHIP) != 0) { + if ((pxHead->status.val & GMAC_RXD_EOF) != 0) { + /* Here a complete frame has been seen with SOF and EOF */ + ulReturn = pxHead->status.bm.len; + break; + } + circ_inc32 (&ulIndex, p_gmac_dev->ul_rx_list_size); + pxHead = &p_gmac_dev->p_rx_dscr[ulIndex]; + if ((pxHead->addr.val & GMAC_RXD_OWNERSHIP) == 0) { + /* CPU is not the owner (yet) */ + break; + } + if ((pxHead->status.val & GMAC_RXD_SOF) != 0) { + /* Strange, we found a new Start Of Frame + * discard previous segments */ + int32_t ulPrev = p_gmac_dev->ul_rx_idx; + pxHead = &p_gmac_dev->p_rx_dscr[ulPrev]; + do { + pxHead->addr.val &= ~(GMAC_RXD_OWNERSHIP); + circ_inc32 (&ulPrev, p_gmac_dev->ul_rx_list_size); + pxHead = &p_gmac_dev->p_rx_dscr[ulPrev]; + #if( GMAC_STATS != 0 ) + { + gmacStats.truncCount++; + } + #endif + } while (ulPrev != ulIndex); + p_gmac_dev->ul_rx_idx = ulIndex; + } + } + return ulReturn; +} + +/** + * \brief Frames can be read from the GMAC in multiple sections. + * Read ul_frame_size bytes from the GMAC receive buffers to pcTo. + * p_rcv_size is the size of the entire frame. Generally gmac_read + * will be repeatedly called until the sum of all the ul_frame_size equals + * the value of p_rcv_size. + * + * \param p_gmac_dev Pointer to the GMAC device instance. + * \param p_frame Address of the frame buffer. + * \param ul_frame_size Length of the frame. + * \param p_rcv_size Received frame size. + * + * \return GMAC_OK if receiving frame successfully, otherwise failed. + */ +uint32_t gmac_dev_read(gmac_device_t* p_gmac_dev, uint8_t* p_frame, + uint32_t ul_frame_size, uint32_t* p_rcv_size) +{ + int32_t nextIdx; /* A copy of the Rx-index 'ul_rx_idx' */ + int32_t bytesLeft = gmac_dev_poll (p_gmac_dev); + gmac_rx_descriptor_t *pxHead; + + if (bytesLeft == 0 ) + { + return GMAC_RX_NULL; + } + + /* gmac_dev_poll has confirmed that there is a complete frame at + * the current position 'ul_rx_idx' + */ + nextIdx = p_gmac_dev->ul_rx_idx; + + /* Read +2 bytes because buffers are aligned at -2 bytes */ + bytesLeft = min( bytesLeft + 2, ( int32_t )ul_frame_size ); + + /* The frame will be copied in 1 or 2 memcpy's */ + if( ( p_frame != NULL ) && ( bytesLeft != 0 ) ) + { + const uint8_t *source; + int32_t left; + int32_t toCopy; + + source = p_gmac_dev->p_rx_buffer + nextIdx * GMAC_RX_UNITSIZE; + left = bytesLeft; + toCopy = ( p_gmac_dev->ul_rx_list_size - nextIdx ) * GMAC_RX_UNITSIZE; + if(toCopy > left ) + { + toCopy = left; + } + memcpy (p_frame, source, toCopy); + left -= toCopy; + + if( left != 0ul ) + { + memcpy (p_frame + toCopy, (void*)p_gmac_dev->p_rx_buffer, left); + } + } + + do + { + pxHead = &p_gmac_dev->p_rx_dscr[nextIdx]; + pxHead->addr.val &= ~(GMAC_RXD_OWNERSHIP); + circ_inc32 (&nextIdx, p_gmac_dev->ul_rx_list_size); + } while ((pxHead->status.val & GMAC_RXD_EOF) == 0); + + p_gmac_dev->ul_rx_idx = nextIdx; + + *p_rcv_size = bytesLeft; + + return GMAC_OK; +} + + +extern void vGMACGenerateChecksum( uint8_t *apBuffer ); + +/** + * \brief Send ulLength bytes from pcFrom. This copies the buffer to one of the + * GMAC Tx buffers, and then indicates to the GMAC that the buffer is ready. + * If lEndOfFrame is true then the data being copied is the end of the frame + * and the frame can be transmitted. + * + * \param p_gmac_dev Pointer to the GMAC device instance. + * \param p_buffer Pointer to the data buffer. + * \param ul_size Length of the frame. + * \param func_tx_cb Transmit callback function. + * + * \return Length sent. + */ +uint32_t gmac_dev_write(gmac_device_t* p_gmac_dev, void *p_buffer, + uint32_t ul_size, gmac_dev_tx_cb_t func_tx_cb) +{ + + volatile gmac_tx_descriptor_t *p_tx_td; +#if( GMAC_USES_TX_CALLBACK != 0 ) + volatile gmac_dev_tx_cb_t *p_func_tx_cb; +#endif + + Gmac *p_hw = p_gmac_dev->p_hw; + +#if( GMAC_USES_TX_CALLBACK == 0 ) + ( void )func_tx_cb; +#endif + + /* Check parameter */ + if (ul_size > GMAC_TX_UNITSIZE) { + return GMAC_PARAM; + } + + /* Pointers to the current transmit descriptor */ + p_tx_td = &p_gmac_dev->p_tx_dscr[p_gmac_dev->l_tx_head]; + + /* If no free TxTd, buffer can't be sent, schedule the wakeup callback */ +// if (CIRC_SPACE(p_gmac_dev->l_tx_head, p_gmac_dev->l_tx_tail, +// p_gmac_dev->ul_tx_list_size) == 0) + { + if ((p_tx_td->status.val & GMAC_TXD_USED) == 0) + return GMAC_TX_BUSY; + } +#if( GMAC_USES_TX_CALLBACK != 0 ) + /* Pointers to the current Tx callback */ + p_func_tx_cb = &p_gmac_dev->func_tx_cb_list[p_gmac_dev->l_tx_head]; +#endif + + /* Set up/copy data to transmission buffer */ + if (p_buffer && ul_size) { + /* Driver manages the ring buffer */ + /* Calculating the checksum here is faster than calculating it from the GMAC buffer + * because withing p_buffer, it is well aligned */ + #if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + { + /* Zero-copy... */ + p_tx_td->addr = ( uint32_t ) p_buffer; + } + #else + { + /* Or memcopy... */ + memcpy((void *)p_tx_td->addr, p_buffer, ul_size); + } + #endif /* ipconfigZERO_COPY_TX_DRIVER */ + vGMACGenerateChecksum( ( uint8_t * ) p_tx_td->addr ); + } + +#if( GMAC_USES_TX_CALLBACK != 0 ) + /* Tx callback */ + *p_func_tx_cb = func_tx_cb; +#endif + + /* Update transmit descriptor status */ + + /* The buffer size defined is the length of ethernet frame, + so it's always the last buffer of the frame. */ + if( p_gmac_dev->l_tx_head == ( int32_t )( p_gmac_dev->ul_tx_list_size - 1 ) ) + { + /* No need to 'and' with GMAC_TXD_LEN_MASK because ul_size has been checked */ + p_tx_td->status.val = + ul_size | GMAC_TXD_LAST | GMAC_TXD_WRAP; + } else { + p_tx_td->status.val = + ul_size | GMAC_TXD_LAST; + } + + circ_inc32( &p_gmac_dev->l_tx_head, p_gmac_dev->ul_tx_list_size ); + + /* Now start to transmit if it is still not done */ + gmac_start_transmission(p_hw); + + return GMAC_OK; +} + +/** + * \brief Get current load of transmit. + * + * \param p_gmac_dev Pointer to the GMAC device instance. + * + * \return Current load of transmit. + */ +#if( GMAC_USES_TX_CALLBACK != 0 ) +/* Without defining GMAC_USES_TX_CALLBACK, l_tx_tail won't be updated */ +uint32_t gmac_dev_get_tx_load(gmac_device_t* p_gmac_dev) +{ + uint16_t us_head = p_gmac_dev->l_tx_head; + uint16_t us_tail = p_gmac_dev->l_tx_tail; + return CIRC_CNT(us_head, us_tail, p_gmac_dev->ul_tx_list_size); +} +#endif + +/** + * \brief Register/Clear RX callback. Callback will be invoked after the next received + * frame. + * + * When gmac_dev_read() returns GMAC_RX_NULL, the application task calls + * gmac_dev_set_rx_callback() to register func_rx_cb() callback and enters suspend state. + * The callback is in charge to resume the task once a new frame has been + * received. The next time gmac_dev_read() is called, it will be successful. + * + * This function is usually invoked from the RX callback itself with NULL + * callback, to unregister. Once the callback has resumed the application task, + * there is no need to invoke the callback again. + * + * \param p_gmac_dev Pointer to the GMAC device instance. + * \param func_tx_cb Receive callback function. + */ +void gmac_dev_set_rx_callback(gmac_device_t* p_gmac_dev, + gmac_dev_rx_cb_t func_rx_cb) +{ + Gmac *p_hw = p_gmac_dev->p_hw; + + if (func_rx_cb == NULL) { + gmac_disable_interrupt(p_hw, GMAC_IDR_RCOMP); + p_gmac_dev->func_rx_cb = NULL; + } else { + p_gmac_dev->func_rx_cb = func_rx_cb; + gmac_enable_interrupt(p_hw, GMAC_IER_RCOMP); + } +} + +/** + * \brief Register/Clear TX wakeup callback. + * + * When gmac_dev_write() returns GMAC_TX_BUSY (all transmit descriptor busy), the application + * task calls gmac_dev_set_tx_wakeup_callback() to register func_wakeup() callback and + * enters suspend state. The callback is in charge to resume the task once + * several transmit descriptors have been released. The next time gmac_dev_write() will be called, + * it shall be successful. + * + * This function is usually invoked with NULL callback from the TX wakeup + * callback itself, to unregister. Once the callback has resumed the + * application task, there is no need to invoke the callback again. + * + * \param p_gmac_dev Pointer to GMAC device instance. + * \param func_wakeup Pointer to wakeup callback function. + * \param uc_threshold Number of free transmit descriptor before wakeup callback invoked. + * + * \return GMAC_OK, GMAC_PARAM on parameter error. + */ +#if( GMAC_USES_WAKEUP_CALLBACK ) +uint8_t gmac_dev_set_tx_wakeup_callback(gmac_device_t* p_gmac_dev, + gmac_dev_wakeup_cb_t func_wakeup_cb, uint8_t uc_threshold) +{ + if (func_wakeup_cb == NULL) { + p_gmac_dev->func_wakeup_cb = NULL; + } else { + if (uc_threshold <= p_gmac_dev->ul_tx_list_size) { + p_gmac_dev->func_wakeup_cb = func_wakeup_cb; + p_gmac_dev->uc_wakeup_threshold = uc_threshold; + } else { + return GMAC_PARAM; + } + } + + return GMAC_OK; +} +#endif /* GMAC_USES_WAKEUP_CALLBACK */ + +/** + * \brief Reset TX & RX queue & statistics. + * + * \param p_gmac_dev Pointer to GMAC device instance. + */ +void gmac_dev_reset(gmac_device_t* p_gmac_dev) +{ + Gmac *p_hw = p_gmac_dev->p_hw; + + gmac_reset_rx_mem(p_gmac_dev); + gmac_reset_tx_mem(p_gmac_dev); + gmac_network_control(p_hw, GMAC_NCR_TXEN | GMAC_NCR_RXEN + | GMAC_NCR_WESTAT | GMAC_NCR_CLRSTAT); +} + +void gmac_dev_halt(Gmac* p_gmac); + +void gmac_dev_halt(Gmac* p_gmac) +{ + gmac_network_control(p_gmac, GMAC_NCR_WESTAT | GMAC_NCR_CLRSTAT); + gmac_disable_interrupt(p_gmac, ~0u); +} + + +/** + * \brief GMAC Interrupt handler. + * + * \param p_gmac_dev Pointer to GMAC device instance. + */ + +#if( GMAC_STATS != 0 ) + extern int logPrintf( const char *pcFormat, ... ); + + void gmac_show_irq_counts () + { + int index; + for (index = 0; index < ARRAY_SIZE(intPairs); index++) { + if (gmacStats.intStatus[intPairs[index].index]) { + logPrintf("%s : %6u\n", intPairs[index].name, gmacStats.intStatus[intPairs[index].index]); + } + } + } +#endif + +void gmac_handler(gmac_device_t* p_gmac_dev) +{ + Gmac *p_hw = p_gmac_dev->p_hw; + +#if( GMAC_USES_TX_CALLBACK != 0 ) + gmac_tx_descriptor_t *p_tx_td; + gmac_dev_tx_cb_t *p_tx_cb = NULL; + uint32_t ul_tx_status_flag; +#endif +#if( GMAC_STATS != 0 ) + int index; +#endif + + /* volatile */ uint32_t ul_isr; + /* volatile */ uint32_t ul_rsr; + /* volatile */ uint32_t ul_tsr; + + ul_isr = gmac_get_interrupt_status(p_hw); + ul_rsr = gmac_get_rx_status(p_hw); + ul_tsr = gmac_get_tx_status(p_hw); + +/* Why clear bits that are ignored anyway ? */ +/* ul_isr &= ~(gmac_get_interrupt_mask(p_hw) | 0xF8030300); */ + #if( GMAC_STATS != 0 ) + { + for (index = 0; index < ARRAY_SIZE(intPairs); index++) { + if (ul_isr & intPairs[index].mask) + gmacStats.intStatus[intPairs[index].index]++; + } + } + #endif /* GMAC_STATS != 0 */ + + /* RX packet */ + if ((ul_isr & GMAC_ISR_RCOMP) || (ul_rsr & (GMAC_RSR_REC|GMAC_RSR_RXOVR|GMAC_RSR_BNA))) { + /* Clear status */ + gmac_clear_rx_status(p_hw, ul_rsr); + + if (ul_isr & GMAC_ISR_RCOMP) + ul_rsr |= GMAC_RSR_REC; + /* Invoke callbacks which can be useful to wake op a task */ + if (p_gmac_dev->func_rx_cb) { + p_gmac_dev->func_rx_cb(ul_rsr); + } + } + + /* TX packet */ + if ((ul_isr & GMAC_ISR_TCOMP) || (ul_tsr & (GMAC_TSR_TXCOMP|GMAC_TSR_COL|GMAC_TSR_RLE|GMAC_TSR_UND))) { + +#if( GMAC_USES_TX_CALLBACK != 0 ) + ul_tx_status_flag = GMAC_TSR_TXCOMP; +#endif + /* A frame transmitted */ + + /* Check RLE */ + if (ul_tsr & GMAC_TSR_RLE) { + /* Status RLE & Number of discarded buffers */ +#if( GMAC_USES_TX_CALLBACK != 0 ) + ul_tx_status_flag = GMAC_TSR_RLE | CIRC_CNT(p_gmac_dev->l_tx_head, + p_gmac_dev->l_tx_tail, p_gmac_dev->ul_tx_list_size); + p_tx_cb = &p_gmac_dev->func_tx_cb_list[p_gmac_dev->l_tx_tail]; +#endif + gmac_reset_tx_mem(p_gmac_dev); + gmac_enable_transmit(p_hw, 1); + } + /* Clear status */ + gmac_clear_tx_status(p_hw, ul_tsr); + +#if( GMAC_USES_TX_CALLBACK != 0 ) + if (!CIRC_EMPTY(p_gmac_dev->l_tx_head, p_gmac_dev->l_tx_tail)) { + /* Check the buffers */ + do { + p_tx_td = &p_gmac_dev->p_tx_dscr[p_gmac_dev->l_tx_tail]; + p_tx_cb = &p_gmac_dev->func_tx_cb_list[p_gmac_dev->l_tx_tail]; + /* Any error? Exit if buffer has not been sent yet */ + if ((p_tx_td->status.val & GMAC_TXD_USED) == 0) { + break; + } + + /* Notify upper layer that a packet has been sent */ + if (*p_tx_cb) { + (*p_tx_cb) (ul_tx_status_flag, (void*)p_tx_td->addr); + #if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + { + p_tx_td->addr = 0ul; + } + #endif /* ipconfigZERO_COPY_TX_DRIVER */ + } + + circ_inc32(&p_gmac_dev->l_tx_tail, p_gmac_dev->ul_tx_list_size); + } while (CIRC_CNT(p_gmac_dev->l_tx_head, p_gmac_dev->l_tx_tail, + p_gmac_dev->ul_tx_list_size)); + } + + if (ul_tsr & GMAC_TSR_RLE) { + /* Notify upper layer RLE */ + if (*p_tx_cb) { + (*p_tx_cb) (ul_tx_status_flag, NULL); + } + } +#endif /* GMAC_USES_TX_CALLBACK */ + +#if( GMAC_USES_WAKEUP_CALLBACK ) + /* If a wakeup has been scheduled, notify upper layer that it can + send other packets, and the sending will be successful. */ + if ((CIRC_SPACE(p_gmac_dev->l_tx_head, p_gmac_dev->l_tx_tail, + p_gmac_dev->ul_tx_list_size) >= p_gmac_dev->uc_wakeup_threshold) + && p_gmac_dev->func_wakeup_cb) { + p_gmac_dev->func_wakeup_cb(); + } +#endif + } +} + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/gmac.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/gmac.h new file mode 100644 index 0000000..fca3ece --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/gmac.h @@ -0,0 +1,1346 @@ + /** + * \file + * + * \brief GMAC (Ethernet MAC) driver for SAM. + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef GMAC_H_INCLUDED +#define GMAC_H_INCLUDED + +#include "compiler.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** The buffer addresses written into the descriptors must be aligned, so the + last few bits are zero. These bits have special meaning for the GMAC + peripheral and cannot be used as part of the address. */ +#define GMAC_RXD_ADDR_MASK 0xFFFFFFFC +#define GMAC_RXD_WRAP (1ul << 1) /**< Wrap bit */ +#define GMAC_RXD_OWNERSHIP (1ul << 0) /**< Ownership bit */ + +#define GMAC_RXD_BROADCAST (1ul << 31) /**< Broadcast detected */ +#define GMAC_RXD_MULTIHASH (1ul << 30) /**< Multicast hash match */ +#define GMAC_RXD_UNIHASH (1ul << 29) /**< Unicast hash match */ +#define GMAC_RXD_ADDR_FOUND (1ul << 27) /**< Specific address match found */ +#define GMAC_RXD_ADDR (3ul << 25) /**< Address match */ +#define GMAC_RXD_RXCOEN (1ul << 24) /**< RXCOEN related function */ +#define GMAC_RXD_TYPE (3ul << 22) /**< Type ID match */ +#define GMAC_RXD_VLAN (1ul << 21) /**< VLAN tag detected */ +#define GMAC_RXD_PRIORITY (1ul << 20) /**< Priority tag detected */ +#define GMAC_RXD_PRIORITY_MASK (3ul << 17) /**< VLAN priority */ +#define GMAC_RXD_CFI (1ul << 16) /**< Concatenation Format Indicator only if bit 21 is set */ +#define GMAC_RXD_EOF (1ul << 15) /**< End of frame */ +#define GMAC_RXD_SOF (1ul << 14) /**< Start of frame */ +#define GMAC_RXD_FCS (1ul << 13) /**< Frame check sequence */ +#define GMAC_RXD_OFFSET_MASK /**< Receive buffer offset */ +#define GMAC_RXD_LEN_MASK (0xFFF) /**< Length of frame including FCS (if selected) */ +#define GMAC_RXD_LENJUMBO_MASK (0x3FFF) /**< Jumbo frame length */ + +#define GMAC_TXD_USED (1ul << 31) /**< Frame is transmitted */ +#define GMAC_TXD_WRAP (1ul << 30) /**< Last descriptor */ +#define GMAC_TXD_ERROR (1ul << 29) /**< Retry limit exceeded, error */ +#define GMAC_TXD_UNDERRUN (1ul << 28) /**< Transmit underrun */ +#define GMAC_TXD_EXHAUSTED (1ul << 27) /**< Buffer exhausted */ +#define GMAC_TXD_LATE (1ul << 26) /**< Late collision,transmit error */ +#define GMAC_TXD_CHECKSUM_ERROR (7ul << 20) /**< Checksum error */ +#define GMAC_TXD_NOCRC (1ul << 16) /**< No CRC */ +#define GMAC_TXD_LAST (1ul << 15) /**< Last buffer in frame */ +#define GMAC_TXD_LEN_MASK (0x1FFF) /**< Length of buffer */ + +/** The MAC can support frame lengths up to 1536 bytes */ +#define GMAC_FRAME_LENTGH_MAX 1536 + +#define GMAC_RX_UNITSIZE 128 /**< Fixed size for RX buffer */ +#define GMAC_TX_UNITSIZE 1518 /**< Size for ETH frame length */ + +/** GMAC clock speed */ +#define GMAC_MCK_SPEED_240MHZ (240*1000*1000) +#define GMAC_MCK_SPEED_160MHZ (160*1000*1000) +#define GMAC_MCK_SPEED_120MHZ (120*1000*1000) +#define GMAC_MCK_SPEED_80MHZ (80*1000*1000) +#define GMAC_MCK_SPEED_40MHZ (40*1000*1000) +#define GMAC_MCK_SPEED_20MHZ (20*1000*1000) + +/** GMAC maintain code default value*/ +#define GMAC_MAN_CODE_VALUE (10) + +/** GMAC maintain start of frame default value*/ +#define GMAC_MAN_SOF_VALUE (1) + +/** GMAC maintain read/write*/ +#define GMAC_MAN_RW_TYPE (2) + +/** GMAC maintain read only*/ +#define GMAC_MAN_READ_ONLY (1) + +/** GMAC address length */ +#define GMAC_ADDR_LENGTH (6) + + +#define GMAC_DUPLEX_HALF 0 +#define GMAC_DUPLEX_FULL 1 + +#define GMAC_SPEED_10M 0 +#define GMAC_SPEED_100M 1 + +/** + * \brief Return codes for GMAC APIs. + */ +typedef enum { + GMAC_OK = 0, /** 0 Operation OK */ + GMAC_TIMEOUT = 1, /** 1 GMAC operation timeout */ + GMAC_TX_BUSY, /** 2 TX in progress */ + GMAC_RX_NULL, /** 3 No data received */ + GMAC_SIZE_TOO_SMALL, /** 4 Buffer size not enough */ + GMAC_PARAM, /** 5 Parameter error, TX packet invalid or RX size too small */ + GMAC_INVALID = 0xFF, /* Invalid */ +} gmac_status_t; + +/** + * \brief Media Independent Interface (MII) type. + */ +typedef enum { + GMAC_PHY_MII = 0, /** MII mode */ + GMAC_PHY_RMII = 1, /** Reduced MII mode */ + GMAC_PHY_INVALID = 0xFF, /* Invalid mode*/ +} gmac_mii_mode_t; + +/** Receive buffer descriptor struct */ +COMPILER_PACK_SET(8) +typedef struct gmac_rx_descriptor { + union gmac_rx_addr { + uint32_t val; + struct gmac_rx_addr_bm { + uint32_t b_ownership:1, /**< User clear, GMAC sets this to 1 once it has successfully written a frame to memory */ + b_wrap:1, /**< Marks last descriptor in receive buffer */ + addr_dw:30; /**< Address in number of DW */ + } bm; + } addr; /**< Address, Wrap & Ownership */ + union gmac_rx_status { + uint32_t val; + struct gmac_rx_status_bm { + uint32_t len:13, /** 0..12 Length of frame including FCS */ + b_fcs:1, /** 13 Receive buffer offset, bits 13:12 of frame length for jumbo frame */ + b_sof:1, /** 14 Start of frame */ + b_eof:1, /** 15 End of frame */ + b_cfi:1, /** 16 Concatenation Format Indicator */ + vlan_priority:3, /** 17..19 VLAN priority (if VLAN detected) */ + b_priority_detected:1, /** 20 Priority tag detected */ + b_vlan_detected:1, /** 21 VLAN tag detected */ + b_type_id_match:2, /** 22..23 Type ID match */ + b_checksumoffload:1, /** 24 Checksum offload specific function */ + b_addrmatch:2, /** 25..26 Address register match */ + b_ext_addr_match:1, /** 27 External address match found */ + reserved:1, /** 28 */ + b_uni_hash_match:1, /** 29 Unicast hash match */ + b_multi_hash_match:1, /** 30 Multicast hash match */ + b_boardcast_detect:1; /** 31 Global broadcast address detected */ + } bm; + } status; +} gmac_rx_descriptor_t; + +/** Transmit buffer descriptor struct */ +COMPILER_PACK_SET(8) +typedef struct gmac_tx_descriptor { + uint32_t addr; + union gmac_tx_status { + uint32_t val; + struct gmac_tx_status_bm { + uint32_t len:14, /** 0..13 Length of buffer */ + reserved:1, /** 14 */ + b_last_buffer:1, /** 15 Last buffer (in the current frame) */ + b_no_crc:1, /** 16 No CRC */ + reserved1:3, /** 17..19 */ + b_checksumoffload:3, /** 20..22 Transmit checksum generation offload errors */ + reserved2:3, /** 23..25 */ + b_lco:1, /** 26 Late collision, transmit error detected */ + b_exhausted:1, /** 27 Buffer exhausted in mid frame */ + b_underrun:1, /** 28 Transmit underrun */ + b_error:1, /** 29 Retry limit exceeded, error detected */ + b_wrap:1, /** 30 Marks last descriptor in TD list */ + b_used:1; /** 31 User clear, GMAC sets this to 1 once a frame has been successfully transmitted */ + } bm; + } status; +} gmac_tx_descriptor_t; + +COMPILER_PACK_RESET() + +/** + * \brief Input parameters when initializing the gmac module mode. + */ +typedef struct gmac_options { + /* Enable/Disable CopyAllFrame */ + uint8_t uc_copy_all_frame; + /* Enable/Disable NoBroadCast */ + uint8_t uc_no_boardcast; + /* MAC address */ + uint8_t uc_mac_addr[GMAC_ADDR_LENGTH]; +} gmac_options_t; + +/** RX callback */ +typedef void (*gmac_dev_tx_cb_t) (uint32_t ul_status); +/** Wakeup callback */ +typedef void (*gmac_dev_wakeup_cb_t) (void); + +/** + * GMAC driver structure. + */ +typedef struct gmac_device { + + /** Pointer to HW register base */ + Gmac *p_hw; + /** + * Pointer to allocated TX buffer. + * Section 3.6 of AMBA 2.0 spec states that burst should not cross + * 1K Boundaries. + * Receive buffer manager writes are burst of 2 words => 3 lsb bits + * of the address shall be set to 0. + */ + uint8_t *p_tx_buffer; + /** Pointer to allocated RX buffer */ + uint8_t *p_rx_buffer; + /** Pointer to Rx TDs (must be 8-byte aligned) */ + gmac_rx_descriptor_t *p_rx_dscr; + /** Pointer to Tx TDs (must be 8-byte aligned) */ + gmac_tx_descriptor_t *p_tx_dscr; + /** Optional callback to be invoked once a frame has been received */ + gmac_dev_tx_cb_t func_rx_cb; +#if( GMAC_USES_WAKEUP_CALLBACK ) + /** Optional callback to be invoked once several TDs have been released */ + gmac_dev_wakeup_cb_t func_wakeup_cb; +#endif +#if( GMAC_USES_TX_CALLBACK != 0 ) + /** Optional callback list to be invoked once TD has been processed */ + gmac_dev_tx_cb_t *func_tx_cb_list; +#endif + /** RX TD list size */ + uint32_t ul_rx_list_size; + /** RX index for current processing TD */ + uint32_t ul_rx_idx; + /** TX TD list size */ + uint32_t ul_tx_list_size; + /** Circular buffer head pointer by upper layer (buffer to be sent) */ + int32_t l_tx_head; + /** Circular buffer tail pointer incremented by handlers (buffer sent) */ + int32_t l_tx_tail; + + /** Number of free TD before wakeup callback is invoked */ + uint32_t uc_wakeup_threshold; +} gmac_device_t; + +/** + * \brief Write network control value. + * + * \param p_gmac Pointer to the GMAC instance. + * \param ul_ncr Network control value. + */ +static inline void gmac_network_control(Gmac* p_gmac, uint32_t ul_ncr) +{ + p_gmac->GMAC_NCR = ul_ncr; +} + +/** + * \brief Get network control value. + * + * \param p_gmac Pointer to the GMAC instance. + */ + +static inline uint32_t gmac_get_network_control(Gmac* p_gmac) +{ + return p_gmac->GMAC_NCR; +} + +/** + * \brief Enable/Disable GMAC receive. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable GMAC receiver, else to enable it. + */ +static inline void gmac_enable_receive(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCR |= GMAC_NCR_RXEN; + } else { + p_gmac->GMAC_NCR &= ~GMAC_NCR_RXEN; + } +} + +/** + * \brief Enable/Disable GMAC transmit. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable GMAC transmit, else to enable it. + */ +static inline void gmac_enable_transmit(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCR |= GMAC_NCR_TXEN; + } else { + p_gmac->GMAC_NCR &= ~GMAC_NCR_TXEN; + } +} + +/** + * \brief Enable/Disable GMAC management. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable GMAC management, else to enable it. + */ +static inline void gmac_enable_management(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCR |= GMAC_NCR_MPE; + } else { + p_gmac->GMAC_NCR &= ~GMAC_NCR_MPE; + } +} + +/** + * \brief Clear all statistics registers. + * + * \param p_gmac Pointer to the GMAC instance. + */ +static inline void gmac_clear_statistics(Gmac* p_gmac) +{ + p_gmac->GMAC_NCR |= GMAC_NCR_CLRSTAT; +} + +/** + * \brief Increase all statistics registers. + * + * \param p_gmac Pointer to the GMAC instance. + */ +static inline void gmac_increase_statistics(Gmac* p_gmac) +{ + p_gmac->GMAC_NCR |= GMAC_NCR_INCSTAT; +} + +/** + * \brief Enable/Disable statistics registers writing. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable the statistics registers writing, else to enable it. + */ +static inline void gmac_enable_statistics_write(Gmac* p_gmac, + uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCR |= GMAC_NCR_WESTAT; + } else { + p_gmac->GMAC_NCR &= ~GMAC_NCR_WESTAT; + } +} + +/** + * \brief In half-duplex mode, forces collisions on all received frames. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable the back pressure, else to enable it. + */ +static inline void gmac_enable_back_pressure(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCR |= GMAC_NCR_BP; + } else { + p_gmac->GMAC_NCR &= ~GMAC_NCR_BP; + } +} + +/** + * \brief Start transmission. + * + * \param p_gmac Pointer to the GMAC instance. + */ +static inline void gmac_start_transmission(Gmac* p_gmac) +{ + p_gmac->GMAC_NCR |= GMAC_NCR_TSTART; +} + +/** + * \brief Halt transmission. + * + * \param p_gmac Pointer to the GMAC instance. + */ +static inline void gmac_halt_transmission(Gmac* p_gmac) +{ + p_gmac->GMAC_NCR |= GMAC_NCR_THALT; +} + +/** + * \brief Transmit pause frame. + * + * \param p_gmac Pointer to the GMAC instance. + */ +static inline void gmac_tx_pause_frame(Gmac* p_gmac) +{ + p_gmac->GMAC_NCR |= GMAC_NCR_TXPF; +} + +/** + * \brief Transmit zero quantum pause frame. + * + * \param p_gmac Pointer to the GMAC instance. + */ +static inline void gmac_tx_pause_zero_quantum_frame(Gmac* p_gmac) +{ + p_gmac->GMAC_NCR |= GMAC_NCR_TXZQPF; +} + +/** + * \brief Read snapshot. + * + * \param p_gmac Pointer to the GMAC instance. + */ +static inline void gmac_read_snapshot(Gmac* p_gmac) +{ + p_gmac->GMAC_NCR |= GMAC_NCR_RDS; +} + +/** + * \brief Store receivetime stamp to memory. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to normal operation, else to enable the store. + */ +static inline void gmac_store_rx_time_stamp(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCR |= GMAC_NCR_SRTSM; + } else { + p_gmac->GMAC_NCR &= ~GMAC_NCR_SRTSM; + } +} + +/** + * \brief Enable PFC priority-based pause reception. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 1 to set the reception, 0 to disable. + */ +static inline void gmac_enable_pfc_pause_frame(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCR |= GMAC_NCR_ENPBPR; + } else { + p_gmac->GMAC_NCR &= ~GMAC_NCR_ENPBPR; + } +} + +/** + * \brief Transmit PFC priority-based pause reception. + * + * \param p_gmac Pointer to the GMAC instance. + */ +static inline void gmac_transmit_pfc_pause_frame(Gmac* p_gmac) +{ + p_gmac->GMAC_NCR |= GMAC_NCR_TXPBPF; +} + +/** + * \brief Flush next packet. + * + * \param p_gmac Pointer to the GMAC instance. + */ +static inline void gmac_flush_next_packet(Gmac* p_gmac) +{ + p_gmac->GMAC_NCR |= GMAC_NCR_FNP; +} + +/** + * \brief Set up network configuration register. + * + * \param p_gmac Pointer to the GMAC instance. + * \param ul_cfg Network configuration value. + */ +static inline void gmac_set_configure(Gmac* p_gmac, uint32_t ul_cfg) +{ + p_gmac->GMAC_NCFGR = ul_cfg; +} + +/** + * \brief Get network configuration. + * + * \param p_gmac Pointer to the GMAC instance. + * + * \return Network configuration. + */ +static inline uint32_t gmac_get_configure(Gmac* p_gmac) +{ + return p_gmac->GMAC_NCFGR; +} + + +/* Get and set DMA Configuration Register */ +static inline void gmac_set_dma(Gmac* p_gmac, uint32_t ul_cfg) +{ + p_gmac->GMAC_DCFGR = ul_cfg; +} + +static inline uint32_t gmac_get_dma(Gmac* p_gmac) +{ + return p_gmac->GMAC_DCFGR; +} + +/** + * \brief Set speed. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_speed 1 to indicate 100Mbps, 0 to 10Mbps. + */ +static inline void gmac_set_speed(Gmac* p_gmac, uint8_t uc_speed) +{ + if (uc_speed) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_SPD; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_SPD; + } +} + +/** + * \brief Enable/Disable Full-Duplex mode. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable the Full-Duplex mode, else to enable it. + */ +static inline void gmac_enable_full_duplex(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_FD; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_FD; + } +} + +/** + * \brief Enable/Disable Copy(Receive) All Valid Frames. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable copying all valid frames, else to enable it. + */ +static inline void gmac_enable_copy_all(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_CAF; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_CAF; + } +} + +/** + * \brief Enable/Disable jumbo frames (up to 10240 bytes). + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable the jumbo frames, else to enable it. + */ +static inline void gmac_enable_jumbo_frames(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_JFRAME; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_JFRAME; + } +} + +/** + * \brief Disable/Enable broadcast receiving. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 1 to disable the broadcast, else to enable it. + */ +static inline void gmac_disable_broadcast(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_NBC; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_NBC; + } +} + +/** + * \brief Enable/Disable multicast hash. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable the multicast hash, else to enable it. + */ +static inline void gmac_enable_multicast_hash(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_UNIHEN; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_UNIHEN; + } +} + +/** + * \brief Enable/Disable big frames (over 1518, up to 1536). + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable big frames else to enable it. + */ +static inline void gmac_enable_big_frame(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_MAXFS; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_MAXFS; + } +} + +/** + * \brief Set MDC clock divider. + * + * \param p_gmac Pointer to the GMAC instance. + * \param ul_mck GMAC MCK. + * + * \return GMAC_OK if successfully. + */ +static inline uint8_t gmac_set_mdc_clock(Gmac* p_gmac, uint32_t ul_mck) +{ + uint32_t ul_clk; + + if (ul_mck > GMAC_MCK_SPEED_240MHZ) { + return GMAC_INVALID; + } else if (ul_mck > GMAC_MCK_SPEED_160MHZ) { + ul_clk = GMAC_NCFGR_CLK_MCK_96; + } else if (ul_mck > GMAC_MCK_SPEED_120MHZ) { + ul_clk = GMAC_NCFGR_CLK_MCK_64; + } else if (ul_mck > GMAC_MCK_SPEED_80MHZ) { + ul_clk = GMAC_NCFGR_CLK_MCK_48; + } else if (ul_mck > GMAC_MCK_SPEED_40MHZ) { + ul_clk = GMAC_NCFGR_CLK_MCK_32; + } else if (ul_mck > GMAC_MCK_SPEED_20MHZ) { + ul_clk = GMAC_NCFGR_CLK_MCK_16; + } else { + ul_clk = GMAC_NCFGR_CLK_MCK_8; + } + ; + p_gmac->GMAC_NCFGR = (p_gmac->GMAC_NCFGR & ~GMAC_NCFGR_CLK_Msk) | ul_clk; + return GMAC_OK; +} + +/** + * \brief Enable/Disable retry test. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable the GMAC receiver, else to enable it. + */ +static inline void gmac_enable_retry_test(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_RTY; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_RTY; + } +} + +/** + * \brief Enable/Disable pause (when a valid pause frame is received). + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable pause frame, else to enable it. + */ +static inline void gmac_enable_pause_frame(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_PEN; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_PEN; + } +} + +/** + * \brief Set receive buffer offset to 0 ~ 3. + * + * \param p_gmac Pointer to the GMAC instance. + */ +static inline void gmac_set_rx_buffer_offset(Gmac* p_gmac, uint8_t uc_offset) +{ + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_RXBUFO_Msk; + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_RXBUFO(uc_offset); +} + +/** + * \brief Enable/Disable receive length field checking. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable receive length field checking, else to enable it. + */ +static inline void gmac_enable_rx_length_check(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_LFERD; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_LFERD; + } +} + +/** + * \brief Enable/Disable discarding FCS field of received frames. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable discarding FCS field of received frames, else to enable it. + */ +static inline void gmac_enable_discard_fcs(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_RFCS; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_RFCS; + } +} + + +/** + * \brief Enable/Disable frames to be received in half-duplex mode + * while transmitting. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable the received in half-duplex mode, else to enable it. + */ +static inline void gmac_enable_efrhd(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_EFRHD; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_EFRHD; + } +} + +/** + * \brief Enable/Disable ignore RX FCS. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable ignore RX FCS, else to enable it. + */ +static inline void gmac_enable_ignore_rx_fcs(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_IRXFCS; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_IRXFCS; + } +} + +/** + * \brief Get Network Status. + * + * \param p_gmac Pointer to the GMAC instance. + * + * \return Network status. + */ +static inline uint32_t gmac_get_status(Gmac* p_gmac) +{ + return p_gmac->GMAC_NSR; +} + +/** + * \brief Get MDIO IN pin status. + * + * \param p_gmac Pointer to the GMAC instance. + * + * \return MDIO IN pin status. + */ +static inline uint8_t gmac_get_MDIO(Gmac* p_gmac) +{ + return ((p_gmac->GMAC_NSR & GMAC_NSR_MDIO) > 0); +} + +/** + * \brief Check if PHY is idle. + * + * \param p_gmac Pointer to the GMAC instance. + * + * \return 1 if PHY is idle. + */ +static inline uint8_t gmac_is_phy_idle(Gmac* p_gmac) +{ + return ((p_gmac->GMAC_NSR & GMAC_NSR_IDLE) > 0); +} + +/** + * \brief Return transmit status. + * + * \param p_gmac Pointer to the GMAC instance. + * + * \return Transmit status. + */ +static inline uint32_t gmac_get_tx_status(Gmac* p_gmac) +{ + return p_gmac->GMAC_TSR; +} + +/** + * \brief Clear transmit status. + * + * \param p_gmac Pointer to the GMAC instance. + * \param ul_status Transmit status. + */ +static inline void gmac_clear_tx_status(Gmac* p_gmac, uint32_t ul_status) +{ + p_gmac->GMAC_TSR = ul_status; +} + +/** + * \brief Return receive status. + * + * \param p_gmac Pointer to the GMAC instance. + */ +static inline uint32_t gmac_get_rx_status(Gmac* p_gmac) +{ + return p_gmac->GMAC_RSR; +} + +/** + * \brief Clear receive status. + * + * \param p_gmac Pointer to the GMAC instance. + * \param ul_status Receive status. + */ +static inline void gmac_clear_rx_status(Gmac* p_gmac, uint32_t ul_status) +{ + p_gmac->GMAC_RSR = ul_status; +} + +/** + * \brief Set Rx Queue. + * + * \param p_gmac Pointer to the GMAC instance. + * \param ul_addr Rx queue address. + */ +static inline void gmac_set_rx_queue(Gmac* p_gmac, uint32_t ul_addr) +{ + p_gmac->GMAC_RBQB = GMAC_RBQB_ADDR_Msk & ul_addr; +} + +/** + * \brief Get Rx Queue Address. + * + * \param p_gmac Pointer to the GMAC instance. + * + * \return Rx queue address. + */ +static inline uint32_t gmac_get_rx_queue(Gmac* p_gmac) +{ + return p_gmac->GMAC_RBQB; +} + +/** + * \brief Set Tx Queue. + * + * \param p_gmac Pointer to the GMAC instance. + * \param ul_addr Tx queue address. + */ +static inline void gmac_set_tx_queue(Gmac* p_gmac, uint32_t ul_addr) +{ + p_gmac->GMAC_TBQB = GMAC_TBQB_ADDR_Msk & ul_addr; +} + +/** + * \brief Get Tx Queue. + * + * \param p_gmac Pointer to the GMAC instance. + * + * \return Rx queue address. + */ +static inline uint32_t gmac_get_tx_queue(Gmac* p_gmac) +{ + return p_gmac->GMAC_TBQB; +} + +/** + * \brief Enable interrupt(s). + * + * \param p_gmac Pointer to the GMAC instance. + * \param ul_source Interrupt source(s) to be enabled. + */ +static inline void gmac_enable_interrupt(Gmac* p_gmac, uint32_t ul_source) +{ + p_gmac->GMAC_IER = ul_source; +} + +/** + * \brief Disable interrupt(s). + * + * \param p_gmac Pointer to the GMAC instance. + * \param ul_source Interrupt source(s) to be disabled. + */ +static inline void gmac_disable_interrupt(Gmac* p_gmac, uint32_t ul_source) +{ + p_gmac->GMAC_IDR = ul_source; +} + +/** + * \brief Return interrupt status. + * + * \param p_gmac Pointer to the GMAC instance. + * + * \return Interrupt status. + */ +static inline uint32_t gmac_get_interrupt_status(Gmac* p_gmac) +{ + return p_gmac->GMAC_ISR; +} + +/** + * \brief Return interrupt mask. + * + * \param p_gmac Pointer to the GMAC instance. + * + * \return Interrupt mask. + */ +static inline uint32_t gmac_get_interrupt_mask(Gmac* p_gmac) +{ + return p_gmac->GMAC_IMR; +} + +/** + * \brief Execute PHY maintenance command. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_phy_addr PHY address. + * \param uc_reg_addr Register address. + * \param uc_rw 1 to Read, 0 to write. + * \param us_data Data to be performed, write only. + */ +static inline void gmac_maintain_phy(Gmac* p_gmac, + uint8_t uc_phy_addr, uint8_t uc_reg_addr, uint8_t uc_rw, + uint16_t us_data) +{ + /* Wait until bus idle */ + while ((p_gmac->GMAC_NSR & GMAC_NSR_IDLE) == 0); + /* Write maintain register */ + p_gmac->GMAC_MAN = GMAC_MAN_WTN(GMAC_MAN_CODE_VALUE) + | GMAC_MAN_CLTTO + | GMAC_MAN_PHYA(uc_phy_addr) + | GMAC_MAN_REGA(uc_reg_addr) + | GMAC_MAN_OP((uc_rw ? GMAC_MAN_RW_TYPE : GMAC_MAN_READ_ONLY)) + | GMAC_MAN_DATA(us_data); +} + +/** + * \brief Get PHY maintenance data returned. + * + * \param p_gmac Pointer to the GMAC instance. + * + * \return Get PHY data. + */ +static inline uint16_t gmac_get_phy_data(Gmac* p_gmac) +{ + /* Wait until bus idle */ + while ((p_gmac->GMAC_NSR & GMAC_NSR_IDLE) == 0); + /* Return data */ + return (uint16_t) (p_gmac->GMAC_MAN & GMAC_MAN_DATA_Msk); +} + +/** + * \brief Set Hash. + * + * \param p_gmac Pointer to the GMAC instance. + * \param ul_hash_top Hash top. + * \param ul_hash_bottom Hash bottom. + */ +static inline void gmac_set_hash(Gmac* p_gmac, uint32_t ul_hash_top, + uint32_t ul_hash_bottom) +{ + p_gmac->GMAC_HRB = ul_hash_bottom; + p_gmac->GMAC_HRT = ul_hash_top; +} + +/** + * \brief Set 64 bits Hash. + * + * \param p_gmac Pointer to the GMAC instance. + * \param ull_hash 64 bits hash value. + */ +static inline void gmac_set_hash64(Gmac* p_gmac, uint64_t ull_hash) +{ + p_gmac->GMAC_HRB = (uint32_t) ull_hash; + p_gmac->GMAC_HRT = (uint32_t) (ull_hash >> 32); +} + +/** + * \brief Set MAC Address. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_index GMAC specific address register index. + * \param p_mac_addr GMAC address. + */ +static inline void gmac_set_address(Gmac* p_gmac, uint8_t uc_index, + uint8_t* p_mac_addr) +{ + p_gmac->GMAC_SA[uc_index].GMAC_SAB = (p_mac_addr[3] << 24) + | (p_mac_addr[2] << 16) + | (p_mac_addr[1] << 8) + | (p_mac_addr[0]); + p_gmac->GMAC_SA[uc_index].GMAC_SAT = (p_mac_addr[5] << 8) + | (p_mac_addr[4]); +} + +/** + * \brief Set MAC Address via 2 dword. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_index GMAC specific address register index. + * \param ul_mac_top GMAC top address. + * \param ul_mac_bottom GMAC bottom address. + */ +static inline void gmac_set_address32(Gmac* p_gmac, uint8_t uc_index, + uint32_t ul_mac_top, uint32_t ul_mac_bottom) +{ + p_gmac->GMAC_SA[uc_index].GMAC_SAB = ul_mac_bottom; + p_gmac->GMAC_SA[uc_index].GMAC_SAT = ul_mac_top; +} + +/** + * \brief Set MAC Address via int64. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_index GMAC specific address register index. + * \param ull_mac 64-bit GMAC address. + */ +static inline void gmac_set_address64(Gmac* p_gmac, uint8_t uc_index, + uint64_t ull_mac) +{ + p_gmac->GMAC_SA[uc_index].GMAC_SAB = (uint32_t) ull_mac; + p_gmac->GMAC_SA[uc_index].GMAC_SAT = (uint32_t) (ull_mac >> 32); +} + +/** + * \brief Select media independent interface mode. + * + * \param p_gmac Pointer to the GMAC instance. + * \param mode Media independent interface mode. + */ +static inline void gmac_select_mii_mode(Gmac* p_gmac, gmac_mii_mode_t mode) +{ + switch (mode) { + case GMAC_PHY_MII: + case GMAC_PHY_RMII: + p_gmac->GMAC_UR |= GMAC_UR_RMIIMII; + break; + + default: + p_gmac->GMAC_UR &= ~GMAC_UR_RMIIMII; + break; + } +} + +uint8_t gmac_phy_read(Gmac* p_gmac, uint8_t uc_phy_address, uint8_t uc_address, + uint32_t* p_value); +uint8_t gmac_phy_write(Gmac* p_gmac, uint8_t uc_phy_address, + uint8_t uc_address, uint32_t ul_value); +void gmac_dev_init(Gmac* p_gmac, gmac_device_t* p_gmac_dev, + gmac_options_t* p_opt); +uint32_t gmac_dev_read(gmac_device_t* p_gmac_dev, uint8_t* p_frame, + uint32_t ul_frame_size, uint32_t* p_rcv_size); +uint32_t gmac_dev_write(gmac_device_t* p_gmac_dev, void *p_buffer, + uint32_t ul_size, gmac_dev_tx_cb_t func_tx_cb); +uint32_t gmac_dev_get_tx_load(gmac_device_t* p_gmac_dev); +void gmac_dev_set_rx_callback(gmac_device_t* p_gmac_dev, + gmac_dev_tx_cb_t func_rx_cb); +uint8_t gmac_dev_set_tx_wakeup_callback(gmac_device_t* p_gmac_dev, + gmac_dev_wakeup_cb_t func_wakeup, uint8_t uc_threshold); +void gmac_dev_reset(gmac_device_t* p_gmac_dev); +void gmac_handler(gmac_device_t* p_gmac_dev); + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \page gmac_quickstart Quickstart guide for GMAC driver. + * + * This is the quickstart guide for the \ref gmac_group "Ethernet MAC", + * with step-by-step instructions on how to configure and use the driver in a + * selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * \section gmac_basic_use_case Basic use case + * In the basic use case, the GMAC driver are configured for: + * - PHY component KSZ8051MNL is used + * - GMAC uses MII mode + * - The number of receive buffer is 16 + * - The number of transfer buffer is 8 + * - MAC address is set to 00-04-25-1c-a0-02 + * - IP address is set to 192.168.0.2 + * - IP address is set to 192.168.0.2 + * - Gateway is set to 192.168.0.1 + * - Network mask is 255.255.255.0 + * - PHY operation max retry count is 1000000 + * - GMAC is configured to not support copy all frame and support broadcast + * - The data will be read from the ethernet + * + * \section gmac_basic_use_case_setup Setup steps + * + * \subsection gmac_basic_use_case_setup_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (sysclock)" + * -# \ref pmc_group "Power Management Controller (pmc)" + * -# \ref ksz8051mnl_ethernet_phy_group "PHY component (KSZ8051MNL)" + * + * \subsection gmac_basic_use_case_setup_code Example code + * Content of conf_eth.h + * \code + * #define GMAC_RX_BUFFERS 16 + * #define GMAC_TX_BUFFERS 8 + * #define MAC_PHY_RETRY_MAX 1000000 + * #define ETHERNET_CONF_ETHADDR0 0x00 + * #define ETHERNET_CONF_ETHADDR0 0x00 + * #define ETHERNET_CONF_ETHADDR1 0x04 + * #define ETHERNET_CONF_ETHADDR2 0x25 + * #define ETHERNET_CONF_ETHADDR3 0x1C + * #define ETHERNET_CONF_ETHADDR4 0xA0 + * #define ETHERNET_CONF_ETHADDR5 0x02 + * #define ETHERNET_CONF_IPADDR0 192 + * #define ETHERNET_CONF_IPADDR1 168 + * #define ETHERNET_CONF_IPADDR2 0 + * #define ETHERNET_CONF_IPADDR3 2 + * #define ETHERNET_CONF_GATEWAY_ADDR0 192 + * #define ETHERNET_CONF_GATEWAY_ADDR1 168 + * #define ETHERNET_CONF_GATEWAY_ADDR2 0 + * #define ETHERNET_CONF_GATEWAY_ADDR3 1 + * #define ETHERNET_CONF_NET_MASK0 255 + * #define ETHERNET_CONF_NET_MASK1 255 + * #define ETHERNET_CONF_NET_MASK2 255 + * #define ETHERNET_CONF_NET_MASK3 0 + * #define ETH_PHY_MODE ETH_PHY_MODE + * \endcode + * + * A specific gmac device and the receive data buffer must be defined; another ul_frm_size should be defined + * to trace the actual size of the data received. + * \code + * static gmac_device_t gs_gmac_dev; + * static volatile uint8_t gs_uc_eth_buffer[GMAC_FRAME_LENTGH_MAX]; + * + * uint32_t ul_frm_size; + * \endcode + * + * Add to application C-file: + * \code + * void gmac_init(void) + * { + * sysclk_init(); + * + * board_init(); + * + * pmc_enable_periph_clk(ID_GMAC); + * + * gmac_option.uc_copy_all_frame = 0; + * gmac_option.uc_no_boardcast = 0; + * memcpy(gmac_option.uc_mac_addr, gs_uc_mac_address, sizeof(gs_uc_mac_address)); + * gs_gmac_dev.p_hw = GMAC; + * + * gmac_dev_init(GMAC, &gs_gmac_dev, &gmac_option); + * + * NVIC_EnableIRQ(GMAC_IRQn); + * + * ethernet_phy_init(GMAC, BOARD_GMAC_PHY_ADDR, sysclk_get_cpu_hz()); + * + * ethernet_phy_auto_negotiate(GMAC, BOARD_GMAC_PHY_ADDR); + * + * ethernet_phy_set_link(GMAC, BOARD_GMAC_PHY_ADDR, 1); + * \endcode + * + * \subsection gmac_basic_use_case_setup_flow Workflow + * - Ensure that conf_eth.h is present and contains the + * following configuration symbol. This configuration file is used + * by the driver and should not be included by the application. + * -# Define the receiving buffer size used in the internal GMAC driver. + * The buffer size used for RX is GMAC_RX_BUFFERS * 128. + * If it was supposed receiving a large number of frame, the + * GMAC_RX_BUFFERS should be set higher. E.g., the application wants to accept + * a ping echo test of 2048, the GMAC_RX_BUFFERS should be set at least + * (2048/128)=16, and as there are additional frames coming, a preferred + * number is 24 depending on a normal Ethernet throughput. + * - \code + * #define GMAC_RX_BUFFERS 16 + * \endcode + * -# Define the transmitting buffer size used in the internal GMAC driver. + * The buffer size used for TX is GMAC_TX_BUFFERS * 1518. + * - \code + * #define GMAC_TX_BUFFERS 8 + * \endcode + * -# Define maximum retry time for a PHY read/write operation. + * - \code + * #define MAC_PHY_RETRY_MAX 1000000 + * \endcode + * -# Define the MAC address. 00:04:25:1C:A0:02 is the address reserved + * for ATMEL, application should always change this address to its' own. + * - \code + * #define ETHERNET_CONF_ETHADDR0 0x00 + * #define ETHERNET_CONF_ETHADDR1 0x04 + * #define ETHERNET_CONF_ETHADDR2 0x25 + * #define ETHERNET_CONF_ETHADDR3 0x1C + * #define ETHERNET_CONF_ETHADDR4 0xA0 + * #define ETHERNET_CONF_ETHADDR5 0x02 + * \endcode + * -# Define the IP address configration used in the application. When DHCP + * is enabled, this configuration is not effected. + * - \code + * #define ETHERNET_CONF_IPADDR0 192 + * #define ETHERNET_CONF_IPADDR1 168 + * #define ETHERNET_CONF_IPADDR2 0 + * #define ETHERNET_CONF_IPADDR3 2 + * #define ETHERNET_CONF_GATEWAY_ADDR0 192 + * #define ETHERNET_CONF_GATEWAY_ADDR1 168 + * #define ETHERNET_CONF_GATEWAY_ADDR2 0 + * #define ETHERNET_CONF_GATEWAY_ADDR3 1 + * #define ETHERNET_CONF_NET_MASK0 255 + * #define ETHERNET_CONF_NET_MASK1 255 + * #define ETHERNET_CONF_NET_MASK2 255 + * #define ETHERNET_CONF_NET_MASK3 0 + * \endcode + * -# Configure the PHY maintainance interface. + * - \code + * #define ETH_PHY_MODE GMAC_PHY_MII + * \endcode + * -# Enable the system clock: + * - \code sysclk_init(); \endcode + * -# Enable PIO configurations for GMAC: + * - \code board_init(); \endcode + * -# Enable PMC clock for GMAC: + * - \code pmc_enable_periph_clk(ID_GMAC); \endcode + * -# Set the GMAC options; it's set to copy all frame and support broadcast: + * - \code + * gmac_option.uc_copy_all_frame = 0; + * gmac_option.uc_no_boardcast = 0; + * memcpy(gmac_option.uc_mac_addr, gs_uc_mac_address, sizeof(gs_uc_mac_address)); + * gs_gmac_dev.p_hw = GMAC; + * \endcode + * -# Initialize GMAC device with the filled option: + * - \code + * gmac_dev_init(GMAC, &gs_gmac_dev, &gmac_option); + * \endcode + * -# Enable the interrupt service for GMAC: + * - \code + * NVIC_EnableIRQ(GMAC_IRQn); + * \endcode + * -# Initialize the PHY component: + * - \code + * ethernet_phy_init(GMAC, BOARD_GMAC_PHY_ADDR, sysclk_get_cpu_hz()); + * \endcode + * -# The link will be established based on auto negotiation. + * - \code + * ethernet_phy_auto_negotiate(GMAC, BOARD_GMAC_PHY_ADDR); + * \endcode + * -# Establish the ethernet link; the network can be worked from now on: + * - \code + * ethernet_phy_set_link(GMAC, BOARD_GMAC_PHY_ADDR, 1); + * \endcode + * + * \section gmac_basic_use_case_usage Usage steps + * \subsection gmac_basic_use_case_usage_code Example code + * Add to, e.g., main loop in application C-file: + * \code + * gmac_dev_read(&gs_gmac_dev, (uint8_t *) gs_uc_eth_buffer, sizeof(gs_uc_eth_buffer), &ul_frm_size)); + * \endcode + * + * \subsection gmac_basic_use_case_usage_flow Workflow + * -# Start reading the data from the ethernet: + * - \code gmac_dev_read(&gs_gmac_dev, (uint8_t *) gs_uc_eth_buffer, sizeof(gs_uc_eth_buffer), &ul_frm_size)); \endcode + */ + +# define GMAC_STATS 0 + +#if( GMAC_STATS != 0 ) + + /* Here below some code to study the types and + frequencies of GMAC interrupts. */ + #define GMAC_IDX_RXUBR 0 + #define GMAC_IDX_TUR 1 + #define GMAC_IDX_RLEX 2 + #define GMAC_IDX_TFC 3 + #define GMAC_IDX_RCOMP 4 + #define GMAC_IDX_TCOMP 5 + #define GMAC_IDX_ROVR 6 + #define GMAC_IDX_HRESP 7 + #define GMAC_IDX_PFNZ 8 + #define GMAC_IDX_PTZ 9 + + struct SGmacStats { + unsigned recvCount; + unsigned rovrCount; + unsigned bnaCount; + unsigned sendCount; + unsigned sovrCount; + unsigned incompCount; + unsigned truncCount; + + unsigned intStatus[10]; + }; + extern struct SGmacStats gmacStats; + + struct SIntPair { + const char *name; + unsigned mask; + int index; + }; + + #define MK_PAIR( NAME ) #NAME, GMAC_IER_##NAME, GMAC_IDX_##NAME + static const struct SIntPair intPairs[] = { + { MK_PAIR( RXUBR ) }, /* Enable receive used bit read interrupt. */ + { MK_PAIR( TUR ) }, /* Enable transmit underrun interrupt. */ + { MK_PAIR( RLEX ) }, /* Enable retry limit exceeded interrupt. */ + { MK_PAIR( TFC ) }, /* Enable transmit buffers exhausted in mid-frame interrupt. */ + { MK_PAIR( RCOMP ) }, /* Receive complete */ + { MK_PAIR( TCOMP ) }, /* Enable transmit complete interrupt. */ + { MK_PAIR( ROVR ) }, /* Enable receive overrun interrupt. */ + { MK_PAIR( HRESP ) }, /* Enable Hresp not OK interrupt. */ + { MK_PAIR( PFNZ ) }, /* Enable pause frame received interrupt. */ + { MK_PAIR( PTZ ) } /* Enable pause time zero interrupt. */ + }; + + void gmac_show_irq_counts (); + +#endif + +#endif /* GMAC_H_INCLUDED */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/instance/gmac.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/instance/gmac.h new file mode 100644 index 0000000..24d806d --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ATSAM4E/instance/gmac.h @@ -0,0 +1,1349 @@ + /** + * \file + * + * \brief GMAC (Ethernet MAC) driver for SAM. + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef GMAC_H_INCLUDED +#define GMAC_H_INCLUDED + +#include "compiler.h" +#include "component/gmac.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** The buffer addresses written into the descriptors must be aligned, so the + last few bits are zero. These bits have special meaning for the GMAC + peripheral and cannot be used as part of the address. */ +#define GMAC_RXD_ADDR_MASK 0xFFFFFFFC +#define GMAC_RXD_WRAP (1ul << 1) /**< Wrap bit */ +#define GMAC_RXD_OWNERSHIP (1ul << 0) /**< Ownership bit */ + +#define GMAC_RXD_BROADCAST (1ul << 31) /**< Broadcast detected */ +#define GMAC_RXD_MULTIHASH (1ul << 30) /**< Multicast hash match */ +#define GMAC_RXD_UNIHASH (1ul << 29) /**< Unicast hash match */ +#define GMAC_RXD_ADDR_FOUND (1ul << 27) /**< Specific address match found */ +#define GMAC_RXD_ADDR (3ul << 25) /**< Address match */ +#define GMAC_RXD_RXCOEN (1ul << 24) /**< RXCOEN related function */ +#define GMAC_RXD_TYPE (3ul << 22) /**< Type ID match */ +#define GMAC_RXD_VLAN (1ul << 21) /**< VLAN tag detected */ +#define GMAC_RXD_PRIORITY (1ul << 20) /**< Priority tag detected */ +#define GMAC_RXD_PRIORITY_MASK (3ul << 17) /**< VLAN priority */ +#define GMAC_RXD_CFI (1ul << 16) /**< Concatenation Format Indicator only if bit 21 is set */ +#define GMAC_RXD_EOF (1ul << 15) /**< End of frame */ +#define GMAC_RXD_SOF (1ul << 14) /**< Start of frame */ +#define GMAC_RXD_FCS (1ul << 13) /**< Frame check sequence */ +#define GMAC_RXD_OFFSET_MASK /**< Receive buffer offset */ +#define GMAC_RXD_LEN_MASK (0xFFF) /**< Length of frame including FCS (if selected) */ +#define GMAC_RXD_LENJUMBO_MASK (0x3FFF) /**< Jumbo frame length */ + +#define GMAC_TXD_USED (1ul << 31) /**< Frame is transmitted */ +#define GMAC_TXD_WRAP (1ul << 30) /**< Last descriptor */ +#define GMAC_TXD_ERROR (1ul << 29) /**< Retry limit exceeded, error */ +#define GMAC_TXD_UNDERRUN (1ul << 28) /**< Transmit underrun */ +#define GMAC_TXD_EXHAUSTED (1ul << 27) /**< Buffer exhausted */ +#define GMAC_TXD_LATE (1ul << 26) /**< Late collision,transmit error */ +#define GMAC_TXD_CHECKSUM_ERROR (7ul << 20) /**< Checksum error */ +#define GMAC_TXD_NOCRC (1ul << 16) /**< No CRC */ +#define GMAC_TXD_LAST (1ul << 15) /**< Last buffer in frame */ +#define GMAC_TXD_LEN_MASK (0x1FFF) /**< Length of buffer */ + +/** The MAC can support frame lengths up to 1536 bytes */ +#define GMAC_FRAME_LENTGH_MAX 1536 + +#define GMAC_RX_UNITSIZE 128 /**< Fixed size for RX buffer */ +#define GMAC_TX_UNITSIZE 1518 /**< Size for ETH frame length */ + +/** GMAC clock speed */ +#define GMAC_MCK_SPEED_240MHZ (240*1000*1000) +#define GMAC_MCK_SPEED_160MHZ (160*1000*1000) +#define GMAC_MCK_SPEED_120MHZ (120*1000*1000) +#define GMAC_MCK_SPEED_80MHZ (80*1000*1000) +#define GMAC_MCK_SPEED_40MHZ (40*1000*1000) +#define GMAC_MCK_SPEED_20MHZ (20*1000*1000) + +/** GMAC maintain code default value*/ +#define GMAC_MAN_CODE_VALUE (10) + +/** GMAC maintain start of frame default value*/ +#define GMAC_MAN_SOF_VALUE (1) + +/** GMAC maintain read/write*/ +#define GMAC_MAN_RW_TYPE (2) + +/** GMAC maintain read only*/ +#define GMAC_MAN_READ_ONLY (1) + +/** GMAC address length */ +#define GMAC_ADDR_LENGTH (6) + + +#define GMAC_DUPLEX_HALF 0 +#define GMAC_DUPLEX_FULL 1 + +#define GMAC_SPEED_10M 0 +#define GMAC_SPEED_100M 1 + +/** + * \brief Return codes for GMAC APIs. + */ +typedef enum { + GMAC_OK = 0, /** 0 Operation OK */ + GMAC_TIMEOUT = 1, /** 1 GMAC operation timeout */ + GMAC_TX_BUSY, /** 2 TX in progress */ + GMAC_RX_NULL, /** 3 No data received */ + GMAC_SIZE_TOO_SMALL, /** 4 Buffer size not enough */ + GMAC_PARAM, /** 5 Parameter error, TX packet invalid or RX size too small */ + GMAC_INVALID = 0xFF, /* Invalid */ +} gmac_status_t; + +/** + * \brief Media Independent Interface (MII) type. + */ +typedef enum { + GMAC_PHY_MII = 0, /** MII mode */ + GMAC_PHY_RMII = 1, /** Reduced MII mode */ + GMAC_PHY_INVALID = 0xFF, /* Invalid mode*/ +} gmac_mii_mode_t; + +/** Receive buffer descriptor struct */ +COMPILER_PACK_SET(8) +typedef struct gmac_rx_descriptor { + union gmac_rx_addr { + uint32_t val; + struct gmac_rx_addr_bm { + uint32_t b_ownership:1, /**< User clear, GMAC sets this to 1 once it has successfully written a frame to memory */ + b_wrap:1, /**< Marks last descriptor in receive buffer */ + addr_dw:30; /**< Address in number of DW */ + } bm; + } addr; /**< Address, Wrap & Ownership */ + union gmac_rx_status { + uint32_t val; + struct gmac_rx_status_bm { + uint32_t len:13, /** 0..12 Length of frame including FCS */ + b_fcs:1, /** 13 Receive buffer offset, bits 13:12 of frame length for jumbo frame */ + b_sof:1, /** 14 Start of frame */ + b_eof:1, /** 15 End of frame */ + b_cfi:1, /** 16 Concatenation Format Indicator */ + vlan_priority:3, /** 17..19 VLAN priority (if VLAN detected) */ + b_priority_detected:1, /** 20 Priority tag detected */ + b_vlan_detected:1, /** 21 VLAN tag detected */ + b_type_id_match:2, /** 22..23 Type ID match */ + b_checksumoffload:1, /** 24 Checksum offload specific function */ + b_addrmatch:2, /** 25..26 Address register match */ + b_ext_addr_match:1, /** 27 External address match found */ + reserved:1, /** 28 */ + b_uni_hash_match:1, /** 29 Unicast hash match */ + b_multi_hash_match:1, /** 30 Multicast hash match */ + b_boardcast_detect:1; /** 31 Global broadcast address detected */ + } bm; + } status; +} gmac_rx_descriptor_t; + +/** Transmit buffer descriptor struct */ +COMPILER_PACK_SET(8) +typedef struct gmac_tx_descriptor { + uint32_t addr; + union gmac_tx_status { + uint32_t val; + struct gmac_tx_status_bm { + uint32_t len:14, /** 0..13 Length of buffer */ + reserved:1, /** 14 */ + b_last_buffer:1, /** 15 Last buffer (in the current frame) */ + b_no_crc:1, /** 16 No CRC */ + reserved1:3, /** 17..19 */ + b_checksumoffload:3, /** 20..22 Transmit checksum generation offload errors */ + reserved2:3, /** 23..25 */ + b_lco:1, /** 26 Late collision, transmit error detected */ + b_exhausted:1, /** 27 Buffer exhausted in mid frame */ + b_underrun:1, /** 28 Transmit underrun */ + b_error:1, /** 29 Retry limit exceeded, error detected */ + b_wrap:1, /** 30 Marks last descriptor in TD list */ + b_used:1; /** 31 User clear, GMAC sets this to 1 once a frame has been successfully transmitted */ + } bm; + } status; +} gmac_tx_descriptor_t; + +COMPILER_PACK_RESET() + +/** + * \brief Input parameters when initializing the gmac module mode. + */ +typedef struct gmac_options { + /* Enable/Disable CopyAllFrame */ + uint8_t uc_copy_all_frame; + /* Enable/Disable NoBroadCast */ + uint8_t uc_no_boardcast; + /* MAC address */ + uint8_t uc_mac_addr[GMAC_ADDR_LENGTH]; +} gmac_options_t; + +/** TX callback */ +typedef void (*gmac_dev_tx_cb_t) (uint32_t ul_status, uint8_t *puc_buffer); +/** RX callback */ +typedef void (*gmac_dev_rx_cb_t) (uint32_t ul_status); +/** Wakeup callback */ +typedef void (*gmac_dev_wakeup_cb_t) (void); + +/** + * GMAC driver structure. + */ +typedef struct gmac_device { + + /** Pointer to HW register base */ + Gmac *p_hw; + /** + * Pointer to allocated TX buffer. + * Section 3.6 of AMBA 2.0 spec states that burst should not cross + * 1K Boundaries. + * Receive buffer manager writes are burst of 2 words => 3 lsb bits + * of the address shall be set to 0. + */ + uint8_t *p_tx_buffer; + /** Pointer to allocated RX buffer */ + uint8_t *p_rx_buffer; + /** Pointer to Rx TDs (must be 8-byte aligned) */ + gmac_rx_descriptor_t *p_rx_dscr; + /** Pointer to Tx TDs (must be 8-byte aligned) */ + gmac_tx_descriptor_t *p_tx_dscr; + /** Optional callback to be invoked once a frame has been received */ + gmac_dev_rx_cb_t func_rx_cb; +#if( GMAC_USES_WAKEUP_CALLBACK ) + /** Optional callback to be invoked once several TDs have been released */ + gmac_dev_wakeup_cb_t func_wakeup_cb; +#endif +#if( GMAC_USES_TX_CALLBACK != 0 ) + /** Optional callback list to be invoked once TD has been processed */ + gmac_dev_tx_cb_t *func_tx_cb_list; +#endif + /** RX TD list size */ + uint32_t ul_rx_list_size; + /** RX index for current processing TD */ + uint32_t ul_rx_idx; + /** TX TD list size */ + uint32_t ul_tx_list_size; + /** Circular buffer head pointer by upper layer (buffer to be sent) */ + int32_t l_tx_head; + /** Circular buffer tail pointer incremented by handlers (buffer sent) */ + int32_t l_tx_tail; + + /** Number of free TD before wakeup callback is invoked */ + uint32_t uc_wakeup_threshold; +} gmac_device_t; + +/** + * \brief Write network control value. + * + * \param p_gmac Pointer to the GMAC instance. + * \param ul_ncr Network control value. + */ +static inline void gmac_network_control(Gmac* p_gmac, uint32_t ul_ncr) +{ + p_gmac->GMAC_NCR = ul_ncr; +} + +/** + * \brief Get network control value. + * + * \param p_gmac Pointer to the GMAC instance. + */ + +static inline uint32_t gmac_get_network_control(Gmac* p_gmac) +{ + return p_gmac->GMAC_NCR; +} + +/** + * \brief Enable/Disable GMAC receive. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable GMAC receiver, else to enable it. + */ +static inline void gmac_enable_receive(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCR |= GMAC_NCR_RXEN; + } else { + p_gmac->GMAC_NCR &= ~GMAC_NCR_RXEN; + } +} + +/** + * \brief Enable/Disable GMAC transmit. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable GMAC transmit, else to enable it. + */ +static inline void gmac_enable_transmit(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCR |= GMAC_NCR_TXEN; + } else { + p_gmac->GMAC_NCR &= ~GMAC_NCR_TXEN; + } +} + +/** + * \brief Enable/Disable GMAC management. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable GMAC management, else to enable it. + */ +static inline void gmac_enable_management(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCR |= GMAC_NCR_MPE; + } else { + p_gmac->GMAC_NCR &= ~GMAC_NCR_MPE; + } +} + +/** + * \brief Clear all statistics registers. + * + * \param p_gmac Pointer to the GMAC instance. + */ +static inline void gmac_clear_statistics(Gmac* p_gmac) +{ + p_gmac->GMAC_NCR |= GMAC_NCR_CLRSTAT; +} + +/** + * \brief Increase all statistics registers. + * + * \param p_gmac Pointer to the GMAC instance. + */ +static inline void gmac_increase_statistics(Gmac* p_gmac) +{ + p_gmac->GMAC_NCR |= GMAC_NCR_INCSTAT; +} + +/** + * \brief Enable/Disable statistics registers writing. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable the statistics registers writing, else to enable it. + */ +static inline void gmac_enable_statistics_write(Gmac* p_gmac, + uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCR |= GMAC_NCR_WESTAT; + } else { + p_gmac->GMAC_NCR &= ~GMAC_NCR_WESTAT; + } +} + +/** + * \brief In half-duplex mode, forces collisions on all received frames. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable the back pressure, else to enable it. + */ +static inline void gmac_enable_back_pressure(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCR |= GMAC_NCR_BP; + } else { + p_gmac->GMAC_NCR &= ~GMAC_NCR_BP; + } +} + +/** + * \brief Start transmission. + * + * \param p_gmac Pointer to the GMAC instance. + */ +static inline void gmac_start_transmission(Gmac* p_gmac) +{ + p_gmac->GMAC_NCR |= GMAC_NCR_TSTART; +} + +/** + * \brief Halt transmission. + * + * \param p_gmac Pointer to the GMAC instance. + */ +static inline void gmac_halt_transmission(Gmac* p_gmac) +{ + p_gmac->GMAC_NCR |= GMAC_NCR_THALT; +} + +/** + * \brief Transmit pause frame. + * + * \param p_gmac Pointer to the GMAC instance. + */ +static inline void gmac_tx_pause_frame(Gmac* p_gmac) +{ + p_gmac->GMAC_NCR |= GMAC_NCR_TXPF; +} + +/** + * \brief Transmit zero quantum pause frame. + * + * \param p_gmac Pointer to the GMAC instance. + */ +static inline void gmac_tx_pause_zero_quantum_frame(Gmac* p_gmac) +{ + p_gmac->GMAC_NCR |= GMAC_NCR_TXZQPF; +} + +/** + * \brief Read snapshot. + * + * \param p_gmac Pointer to the GMAC instance. + */ +static inline void gmac_read_snapshot(Gmac* p_gmac) +{ + p_gmac->GMAC_NCR |= GMAC_NCR_RDS; +} + +/** + * \brief Store receivetime stamp to memory. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to normal operation, else to enable the store. + */ +static inline void gmac_store_rx_time_stamp(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCR |= GMAC_NCR_SRTSM; + } else { + p_gmac->GMAC_NCR &= ~GMAC_NCR_SRTSM; + } +} + +/** + * \brief Enable PFC priority-based pause reception. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 1 to set the reception, 0 to disable. + */ +static inline void gmac_enable_pfc_pause_frame(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCR |= GMAC_NCR_ENPBPR; + } else { + p_gmac->GMAC_NCR &= ~GMAC_NCR_ENPBPR; + } +} + +/** + * \brief Transmit PFC priority-based pause reception. + * + * \param p_gmac Pointer to the GMAC instance. + */ +static inline void gmac_transmit_pfc_pause_frame(Gmac* p_gmac) +{ + p_gmac->GMAC_NCR |= GMAC_NCR_TXPBPF; +} + +/** + * \brief Flush next packet. + * + * \param p_gmac Pointer to the GMAC instance. + */ +static inline void gmac_flush_next_packet(Gmac* p_gmac) +{ + p_gmac->GMAC_NCR |= GMAC_NCR_FNP; +} + +/** + * \brief Set up network configuration register. + * + * \param p_gmac Pointer to the GMAC instance. + * \param ul_cfg Network configuration value. + */ +static inline void gmac_set_configure(Gmac* p_gmac, uint32_t ul_cfg) +{ + p_gmac->GMAC_NCFGR = ul_cfg; +} + +/** + * \brief Get network configuration. + * + * \param p_gmac Pointer to the GMAC instance. + * + * \return Network configuration. + */ +static inline uint32_t gmac_get_configure(Gmac* p_gmac) +{ + return p_gmac->GMAC_NCFGR; +} + + +/* Get and set DMA Configuration Register */ +static inline void gmac_set_dma(Gmac* p_gmac, uint32_t ul_cfg) +{ + p_gmac->GMAC_DCFGR = ul_cfg; +} + +static inline uint32_t gmac_get_dma(Gmac* p_gmac) +{ + return p_gmac->GMAC_DCFGR; +} + +/** + * \brief Set speed. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_speed 1 to indicate 100Mbps, 0 to 10Mbps. + */ +static inline void gmac_set_speed(Gmac* p_gmac, uint8_t uc_speed) +{ + if (uc_speed) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_SPD; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_SPD; + } +} + +/** + * \brief Enable/Disable Full-Duplex mode. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable the Full-Duplex mode, else to enable it. + */ +static inline void gmac_enable_full_duplex(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_FD; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_FD; + } +} + +/** + * \brief Enable/Disable Copy(Receive) All Valid Frames. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable copying all valid frames, else to enable it. + */ +static inline void gmac_enable_copy_all(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_CAF; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_CAF; + } +} + +/** + * \brief Enable/Disable jumbo frames (up to 10240 bytes). + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable the jumbo frames, else to enable it. + */ +static inline void gmac_enable_jumbo_frames(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_JFRAME; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_JFRAME; + } +} + +/** + * \brief Disable/Enable broadcast receiving. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 1 to disable the broadcast, else to enable it. + */ +static inline void gmac_disable_broadcast(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_NBC; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_NBC; + } +} + +/** + * \brief Enable/Disable multicast hash. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable the multicast hash, else to enable it. + */ +static inline void gmac_enable_multicast_hash(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_UNIHEN; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_UNIHEN; + } +} + +/** + * \brief Enable/Disable big frames (over 1518, up to 1536). + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable big frames else to enable it. + */ +static inline void gmac_enable_big_frame(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_MAXFS; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_MAXFS; + } +} + +/** + * \brief Set MDC clock divider. + * + * \param p_gmac Pointer to the GMAC instance. + * \param ul_mck GMAC MCK. + * + * \return GMAC_OK if successfully. + */ +static inline uint8_t gmac_set_mdc_clock(Gmac* p_gmac, uint32_t ul_mck) +{ + uint32_t ul_clk; + + if (ul_mck > GMAC_MCK_SPEED_240MHZ) { + return GMAC_INVALID; + } else if (ul_mck > GMAC_MCK_SPEED_160MHZ) { + ul_clk = GMAC_NCFGR_CLK_MCK_96; + } else if (ul_mck > GMAC_MCK_SPEED_120MHZ) { + ul_clk = GMAC_NCFGR_CLK_MCK_64; + } else if (ul_mck > GMAC_MCK_SPEED_80MHZ) { + ul_clk = GMAC_NCFGR_CLK_MCK_48; + } else if (ul_mck > GMAC_MCK_SPEED_40MHZ) { + ul_clk = GMAC_NCFGR_CLK_MCK_32; + } else if (ul_mck > GMAC_MCK_SPEED_20MHZ) { + ul_clk = GMAC_NCFGR_CLK_MCK_16; + } else { + ul_clk = GMAC_NCFGR_CLK_MCK_8; + } + ; + p_gmac->GMAC_NCFGR = (p_gmac->GMAC_NCFGR & ~GMAC_NCFGR_CLK_Msk) | ul_clk; + return GMAC_OK; +} + +/** + * \brief Enable/Disable retry test. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable the GMAC receiver, else to enable it. + */ +static inline void gmac_enable_retry_test(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_RTY; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_RTY; + } +} + +/** + * \brief Enable/Disable pause (when a valid pause frame is received). + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable pause frame, else to enable it. + */ +static inline void gmac_enable_pause_frame(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_PEN; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_PEN; + } +} + +/** + * \brief Set receive buffer offset to 0 ~ 3. + * + * \param p_gmac Pointer to the GMAC instance. + */ +static inline void gmac_set_rx_buffer_offset(Gmac* p_gmac, uint8_t uc_offset) +{ + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_RXBUFO_Msk; + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_RXBUFO(uc_offset); +} + +/** + * \brief Enable/Disable receive length field checking. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable receive length field checking, else to enable it. + */ +static inline void gmac_enable_rx_length_check(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_LFERD; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_LFERD; + } +} + +/** + * \brief Enable/Disable discarding FCS field of received frames. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable discarding FCS field of received frames, else to enable it. + */ +static inline void gmac_enable_discard_fcs(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_RFCS; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_RFCS; + } +} + + +/** + * \brief Enable/Disable frames to be received in half-duplex mode + * while transmitting. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable the received in half-duplex mode, else to enable it. + */ +static inline void gmac_enable_efrhd(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_EFRHD; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_EFRHD; + } +} + +/** + * \brief Enable/Disable ignore RX FCS. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_enable 0 to disable ignore RX FCS, else to enable it. + */ +static inline void gmac_enable_ignore_rx_fcs(Gmac* p_gmac, uint8_t uc_enable) +{ + if (uc_enable) { + p_gmac->GMAC_NCFGR |= GMAC_NCFGR_IRXFCS; + } else { + p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_IRXFCS; + } +} + +/** + * \brief Get Network Status. + * + * \param p_gmac Pointer to the GMAC instance. + * + * \return Network status. + */ +static inline uint32_t gmac_get_status(Gmac* p_gmac) +{ + return p_gmac->GMAC_NSR; +} + +/** + * \brief Get MDIO IN pin status. + * + * \param p_gmac Pointer to the GMAC instance. + * + * \return MDIO IN pin status. + */ +static inline uint8_t gmac_get_MDIO(Gmac* p_gmac) +{ + return ((p_gmac->GMAC_NSR & GMAC_NSR_MDIO) > 0); +} + +/** + * \brief Check if PHY is idle. + * + * \param p_gmac Pointer to the GMAC instance. + * + * \return 1 if PHY is idle. + */ +static inline uint8_t gmac_is_phy_idle(Gmac* p_gmac) +{ + return ((p_gmac->GMAC_NSR & GMAC_NSR_IDLE) > 0); +} + +/** + * \brief Return transmit status. + * + * \param p_gmac Pointer to the GMAC instance. + * + * \return Transmit status. + */ +static inline uint32_t gmac_get_tx_status(Gmac* p_gmac) +{ + return p_gmac->GMAC_TSR; +} + +/** + * \brief Clear transmit status. + * + * \param p_gmac Pointer to the GMAC instance. + * \param ul_status Transmit status. + */ +static inline void gmac_clear_tx_status(Gmac* p_gmac, uint32_t ul_status) +{ + p_gmac->GMAC_TSR = ul_status; +} + +/** + * \brief Return receive status. + * + * \param p_gmac Pointer to the GMAC instance. + */ +static inline uint32_t gmac_get_rx_status(Gmac* p_gmac) +{ + return p_gmac->GMAC_RSR; +} + +/** + * \brief Clear receive status. + * + * \param p_gmac Pointer to the GMAC instance. + * \param ul_status Receive status. + */ +static inline void gmac_clear_rx_status(Gmac* p_gmac, uint32_t ul_status) +{ + p_gmac->GMAC_RSR = ul_status; +} + +/** + * \brief Set Rx Queue. + * + * \param p_gmac Pointer to the GMAC instance. + * \param ul_addr Rx queue address. + */ +static inline void gmac_set_rx_queue(Gmac* p_gmac, uint32_t ul_addr) +{ + p_gmac->GMAC_RBQB = GMAC_RBQB_ADDR_Msk & ul_addr; +} + +/** + * \brief Get Rx Queue Address. + * + * \param p_gmac Pointer to the GMAC instance. + * + * \return Rx queue address. + */ +static inline uint32_t gmac_get_rx_queue(Gmac* p_gmac) +{ + return p_gmac->GMAC_RBQB; +} + +/** + * \brief Set Tx Queue. + * + * \param p_gmac Pointer to the GMAC instance. + * \param ul_addr Tx queue address. + */ +static inline void gmac_set_tx_queue(Gmac* p_gmac, uint32_t ul_addr) +{ + p_gmac->GMAC_TBQB = GMAC_TBQB_ADDR_Msk & ul_addr; +} + +/** + * \brief Get Tx Queue. + * + * \param p_gmac Pointer to the GMAC instance. + * + * \return Rx queue address. + */ +static inline uint32_t gmac_get_tx_queue(Gmac* p_gmac) +{ + return p_gmac->GMAC_TBQB; +} + +/** + * \brief Enable interrupt(s). + * + * \param p_gmac Pointer to the GMAC instance. + * \param ul_source Interrupt source(s) to be enabled. + */ +static inline void gmac_enable_interrupt(Gmac* p_gmac, uint32_t ul_source) +{ + p_gmac->GMAC_IER = ul_source; +} + +/** + * \brief Disable interrupt(s). + * + * \param p_gmac Pointer to the GMAC instance. + * \param ul_source Interrupt source(s) to be disabled. + */ +static inline void gmac_disable_interrupt(Gmac* p_gmac, uint32_t ul_source) +{ + p_gmac->GMAC_IDR = ul_source; +} + +/** + * \brief Return interrupt status. + * + * \param p_gmac Pointer to the GMAC instance. + * + * \return Interrupt status. + */ +static inline uint32_t gmac_get_interrupt_status(Gmac* p_gmac) +{ + return p_gmac->GMAC_ISR; +} + +/** + * \brief Return interrupt mask. + * + * \param p_gmac Pointer to the GMAC instance. + * + * \return Interrupt mask. + */ +static inline uint32_t gmac_get_interrupt_mask(Gmac* p_gmac) +{ + return p_gmac->GMAC_IMR; +} + +/** + * \brief Execute PHY maintenance command. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_phy_addr PHY address. + * \param uc_reg_addr Register address. + * \param uc_rw 1 to Read, 0 to write. + * \param us_data Data to be performed, write only. + */ +static inline void gmac_maintain_phy(Gmac* p_gmac, + uint8_t uc_phy_addr, uint8_t uc_reg_addr, uint8_t uc_rw, + uint16_t us_data) +{ + /* Wait until bus idle */ + while ((p_gmac->GMAC_NSR & GMAC_NSR_IDLE) == 0); + /* Write maintain register */ + p_gmac->GMAC_MAN = GMAC_MAN_WTN(GMAC_MAN_CODE_VALUE) + | GMAC_MAN_CLTTO + | GMAC_MAN_PHYA(uc_phy_addr) + | GMAC_MAN_REGA(uc_reg_addr) + | GMAC_MAN_OP((uc_rw ? GMAC_MAN_RW_TYPE : GMAC_MAN_READ_ONLY)) + | GMAC_MAN_DATA(us_data); +} + +/** + * \brief Get PHY maintenance data returned. + * + * \param p_gmac Pointer to the GMAC instance. + * + * \return Get PHY data. + */ +static inline uint16_t gmac_get_phy_data(Gmac* p_gmac) +{ + /* Wait until bus idle */ + while ((p_gmac->GMAC_NSR & GMAC_NSR_IDLE) == 0); + /* Return data */ + return (uint16_t) (p_gmac->GMAC_MAN & GMAC_MAN_DATA_Msk); +} + +/** + * \brief Set Hash. + * + * \param p_gmac Pointer to the GMAC instance. + * \param ul_hash_top Hash top. + * \param ul_hash_bottom Hash bottom. + */ +static inline void gmac_set_hash(Gmac* p_gmac, uint32_t ul_hash_top, + uint32_t ul_hash_bottom) +{ + p_gmac->GMAC_HRB = ul_hash_bottom; + p_gmac->GMAC_HRT = ul_hash_top; +} + +/** + * \brief Set 64 bits Hash. + * + * \param p_gmac Pointer to the GMAC instance. + * \param ull_hash 64 bits hash value. + */ +static inline void gmac_set_hash64(Gmac* p_gmac, uint64_t ull_hash) +{ + p_gmac->GMAC_HRB = (uint32_t) ull_hash; + p_gmac->GMAC_HRT = (uint32_t) (ull_hash >> 32); +} + +/** + * \brief Set MAC Address. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_index GMAC specific address register index. + * \param p_mac_addr GMAC address. + */ +static inline void gmac_set_address(Gmac* p_gmac, uint8_t uc_index, + uint8_t* p_mac_addr) +{ + p_gmac->GMAC_SA[uc_index].GMAC_SAB = (p_mac_addr[3] << 24) + | (p_mac_addr[2] << 16) + | (p_mac_addr[1] << 8) + | (p_mac_addr[0]); + p_gmac->GMAC_SA[uc_index].GMAC_SAT = (p_mac_addr[5] << 8) + | (p_mac_addr[4]); +} + +/** + * \brief Set MAC Address via 2 dword. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_index GMAC specific address register index. + * \param ul_mac_top GMAC top address. + * \param ul_mac_bottom GMAC bottom address. + */ +static inline void gmac_set_address32(Gmac* p_gmac, uint8_t uc_index, + uint32_t ul_mac_top, uint32_t ul_mac_bottom) +{ + p_gmac->GMAC_SA[uc_index].GMAC_SAB = ul_mac_bottom; + p_gmac->GMAC_SA[uc_index].GMAC_SAT = ul_mac_top; +} + +/** + * \brief Set MAC Address via int64. + * + * \param p_gmac Pointer to the GMAC instance. + * \param uc_index GMAC specific address register index. + * \param ull_mac 64-bit GMAC address. + */ +static inline void gmac_set_address64(Gmac* p_gmac, uint8_t uc_index, + uint64_t ull_mac) +{ + p_gmac->GMAC_SA[uc_index].GMAC_SAB = (uint32_t) ull_mac; + p_gmac->GMAC_SA[uc_index].GMAC_SAT = (uint32_t) (ull_mac >> 32); +} + +/** + * \brief Select media independent interface mode. + * + * \param p_gmac Pointer to the GMAC instance. + * \param mode Media independent interface mode. + */ +static inline void gmac_select_mii_mode(Gmac* p_gmac, gmac_mii_mode_t mode) +{ + switch (mode) { + case GMAC_PHY_MII: + case GMAC_PHY_RMII: + p_gmac->GMAC_UR |= GMAC_UR_RMIIMII; + break; + + default: + p_gmac->GMAC_UR &= ~GMAC_UR_RMIIMII; + break; + } +} + +uint8_t gmac_phy_read(Gmac* p_gmac, uint8_t uc_phy_address, uint8_t uc_address, + uint32_t* p_value); +uint8_t gmac_phy_write(Gmac* p_gmac, uint8_t uc_phy_address, + uint8_t uc_address, uint32_t ul_value); +void gmac_dev_init(Gmac* p_gmac, gmac_device_t* p_gmac_dev, + gmac_options_t* p_opt); +uint32_t gmac_dev_read(gmac_device_t* p_gmac_dev, uint8_t* p_frame, + uint32_t ul_frame_size, uint32_t* p_rcv_size); +uint32_t gmac_dev_write(gmac_device_t* p_gmac_dev, void *p_buffer, + uint32_t ul_size, gmac_dev_tx_cb_t func_tx_cb); +uint32_t gmac_dev_get_tx_load(gmac_device_t* p_gmac_dev); +void gmac_dev_set_rx_callback(gmac_device_t* p_gmac_dev, + gmac_dev_rx_cb_t func_rx_cb); +uint8_t gmac_dev_set_tx_wakeup_callback(gmac_device_t* p_gmac_dev, + gmac_dev_wakeup_cb_t func_wakeup, uint8_t uc_threshold); +void gmac_dev_reset(gmac_device_t* p_gmac_dev); +void gmac_handler(gmac_device_t* p_gmac_dev); + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \page gmac_quickstart Quickstart guide for GMAC driver. + * + * This is the quickstart guide for the \ref gmac_group "Ethernet MAC", + * with step-by-step instructions on how to configure and use the driver in a + * selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * \section gmac_basic_use_case Basic use case + * In the basic use case, the GMAC driver are configured for: + * - PHY component KSZ8051MNL is used + * - GMAC uses MII mode + * - The number of receive buffer is 16 + * - The number of transfer buffer is 8 + * - MAC address is set to 00-04-25-1c-a0-02 + * - IP address is set to 192.168.0.2 + * - IP address is set to 192.168.0.2 + * - Gateway is set to 192.168.0.1 + * - Network mask is 255.255.255.0 + * - PHY operation max retry count is 1000000 + * - GMAC is configured to not support copy all frame and support broadcast + * - The data will be read from the ethernet + * + * \section gmac_basic_use_case_setup Setup steps + * + * \subsection gmac_basic_use_case_setup_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (sysclock)" + * -# \ref pmc_group "Power Management Controller (pmc)" + * -# \ref ksz8051mnl_ethernet_phy_group "PHY component (KSZ8051MNL)" + * + * \subsection gmac_basic_use_case_setup_code Example code + * Content of conf_eth.h + * \code + * #define GMAC_RX_BUFFERS 16 + * #define GMAC_TX_BUFFERS 8 + * #define MAC_PHY_RETRY_MAX 1000000 + * #define ETHERNET_CONF_ETHADDR0 0x00 + * #define ETHERNET_CONF_ETHADDR0 0x00 + * #define ETHERNET_CONF_ETHADDR1 0x04 + * #define ETHERNET_CONF_ETHADDR2 0x25 + * #define ETHERNET_CONF_ETHADDR3 0x1C + * #define ETHERNET_CONF_ETHADDR4 0xA0 + * #define ETHERNET_CONF_ETHADDR5 0x02 + * #define ETHERNET_CONF_IPADDR0 192 + * #define ETHERNET_CONF_IPADDR1 168 + * #define ETHERNET_CONF_IPADDR2 0 + * #define ETHERNET_CONF_IPADDR3 2 + * #define ETHERNET_CONF_GATEWAY_ADDR0 192 + * #define ETHERNET_CONF_GATEWAY_ADDR1 168 + * #define ETHERNET_CONF_GATEWAY_ADDR2 0 + * #define ETHERNET_CONF_GATEWAY_ADDR3 1 + * #define ETHERNET_CONF_NET_MASK0 255 + * #define ETHERNET_CONF_NET_MASK1 255 + * #define ETHERNET_CONF_NET_MASK2 255 + * #define ETHERNET_CONF_NET_MASK3 0 + * #define ETH_PHY_MODE ETH_PHY_MODE + * \endcode + * + * A specific gmac device and the receive data buffer must be defined; another ul_frm_size should be defined + * to trace the actual size of the data received. + * \code + * static gmac_device_t gs_gmac_dev; + * static volatile uint8_t gs_uc_eth_buffer[GMAC_FRAME_LENTGH_MAX]; + * + * uint32_t ul_frm_size; + * \endcode + * + * Add to application C-file: + * \code + * void gmac_init(void) + * { + * sysclk_init(); + * + * board_init(); + * + * pmc_enable_periph_clk(ID_GMAC); + * + * gmac_option.uc_copy_all_frame = 0; + * gmac_option.uc_no_boardcast = 0; + * memcpy(gmac_option.uc_mac_addr, gs_uc_mac_address, sizeof(gs_uc_mac_address)); + * gs_gmac_dev.p_hw = GMAC; + * + * gmac_dev_init(GMAC, &gs_gmac_dev, &gmac_option); + * + * NVIC_EnableIRQ(GMAC_IRQn); + * + * ethernet_phy_init(GMAC, BOARD_GMAC_PHY_ADDR, sysclk_get_cpu_hz()); + * + * ethernet_phy_auto_negotiate(GMAC, BOARD_GMAC_PHY_ADDR); + * + * ethernet_phy_set_link(GMAC, BOARD_GMAC_PHY_ADDR, 1); + * \endcode + * + * \subsection gmac_basic_use_case_setup_flow Workflow + * - Ensure that conf_eth.h is present and contains the + * following configuration symbol. This configuration file is used + * by the driver and should not be included by the application. + * -# Define the receiving buffer size used in the internal GMAC driver. + * The buffer size used for RX is GMAC_RX_BUFFERS * 128. + * If it was supposed receiving a large number of frame, the + * GMAC_RX_BUFFERS should be set higher. E.g., the application wants to accept + * a ping echo test of 2048, the GMAC_RX_BUFFERS should be set at least + * (2048/128)=16, and as there are additional frames coming, a preferred + * number is 24 depending on a normal Ethernet throughput. + * - \code + * #define GMAC_RX_BUFFERS 16 + * \endcode + * -# Define the transmitting buffer size used in the internal GMAC driver. + * The buffer size used for TX is GMAC_TX_BUFFERS * 1518. + * - \code + * #define GMAC_TX_BUFFERS 8 + * \endcode + * -# Define maximum retry time for a PHY read/write operation. + * - \code + * #define MAC_PHY_RETRY_MAX 1000000 + * \endcode + * -# Define the MAC address. 00:04:25:1C:A0:02 is the address reserved + * for ATMEL, application should always change this address to its' own. + * - \code + * #define ETHERNET_CONF_ETHADDR0 0x00 + * #define ETHERNET_CONF_ETHADDR1 0x04 + * #define ETHERNET_CONF_ETHADDR2 0x25 + * #define ETHERNET_CONF_ETHADDR3 0x1C + * #define ETHERNET_CONF_ETHADDR4 0xA0 + * #define ETHERNET_CONF_ETHADDR5 0x02 + * \endcode + * -# Define the IP address configration used in the application. When DHCP + * is enabled, this configuration is not effected. + * - \code + * #define ETHERNET_CONF_IPADDR0 192 + * #define ETHERNET_CONF_IPADDR1 168 + * #define ETHERNET_CONF_IPADDR2 0 + * #define ETHERNET_CONF_IPADDR3 2 + * #define ETHERNET_CONF_GATEWAY_ADDR0 192 + * #define ETHERNET_CONF_GATEWAY_ADDR1 168 + * #define ETHERNET_CONF_GATEWAY_ADDR2 0 + * #define ETHERNET_CONF_GATEWAY_ADDR3 1 + * #define ETHERNET_CONF_NET_MASK0 255 + * #define ETHERNET_CONF_NET_MASK1 255 + * #define ETHERNET_CONF_NET_MASK2 255 + * #define ETHERNET_CONF_NET_MASK3 0 + * \endcode + * -# Configure the PHY maintainance interface. + * - \code + * #define ETH_PHY_MODE GMAC_PHY_MII + * \endcode + * -# Enable the system clock: + * - \code sysclk_init(); \endcode + * -# Enable PIO configurations for GMAC: + * - \code board_init(); \endcode + * -# Enable PMC clock for GMAC: + * - \code pmc_enable_periph_clk(ID_GMAC); \endcode + * -# Set the GMAC options; it's set to copy all frame and support broadcast: + * - \code + * gmac_option.uc_copy_all_frame = 0; + * gmac_option.uc_no_boardcast = 0; + * memcpy(gmac_option.uc_mac_addr, gs_uc_mac_address, sizeof(gs_uc_mac_address)); + * gs_gmac_dev.p_hw = GMAC; + * \endcode + * -# Initialize GMAC device with the filled option: + * - \code + * gmac_dev_init(GMAC, &gs_gmac_dev, &gmac_option); + * \endcode + * -# Enable the interrupt service for GMAC: + * - \code + * NVIC_EnableIRQ(GMAC_IRQn); + * \endcode + * -# Initialize the PHY component: + * - \code + * ethernet_phy_init(GMAC, BOARD_GMAC_PHY_ADDR, sysclk_get_cpu_hz()); + * \endcode + * -# The link will be established based on auto negotiation. + * - \code + * ethernet_phy_auto_negotiate(GMAC, BOARD_GMAC_PHY_ADDR); + * \endcode + * -# Establish the ethernet link; the network can be worked from now on: + * - \code + * ethernet_phy_set_link(GMAC, BOARD_GMAC_PHY_ADDR, 1); + * \endcode + * + * \section gmac_basic_use_case_usage Usage steps + * \subsection gmac_basic_use_case_usage_code Example code + * Add to, e.g., main loop in application C-file: + * \code + * gmac_dev_read(&gs_gmac_dev, (uint8_t *) gs_uc_eth_buffer, sizeof(gs_uc_eth_buffer), &ul_frm_size)); + * \endcode + * + * \subsection gmac_basic_use_case_usage_flow Workflow + * -# Start reading the data from the ethernet: + * - \code gmac_dev_read(&gs_gmac_dev, (uint8_t *) gs_uc_eth_buffer, sizeof(gs_uc_eth_buffer), &ul_frm_size)); \endcode + */ + +# define GMAC_STATS 0 + +#if( GMAC_STATS != 0 ) + + /* Here below some code to study the types and + frequencies of GMAC interrupts. */ + #define GMAC_IDX_RXUBR 0 + #define GMAC_IDX_TUR 1 + #define GMAC_IDX_RLEX 2 + #define GMAC_IDX_TFC 3 + #define GMAC_IDX_RCOMP 4 + #define GMAC_IDX_TCOMP 5 + #define GMAC_IDX_ROVR 6 + #define GMAC_IDX_HRESP 7 + #define GMAC_IDX_PFNZ 8 + #define GMAC_IDX_PTZ 9 + + struct SGmacStats { + unsigned recvCount; + unsigned rovrCount; + unsigned bnaCount; + unsigned sendCount; + unsigned sovrCount; + unsigned incompCount; + unsigned truncCount; + + unsigned intStatus[10]; + }; + extern struct SGmacStats gmacStats; + + struct SIntPair { + const char *name; + unsigned mask; + int index; + }; + + #define MK_PAIR( NAME ) #NAME, GMAC_IER_##NAME, GMAC_IDX_##NAME + static const struct SIntPair intPairs[] = { + { MK_PAIR( RXUBR ) }, /* Enable receive used bit read interrupt. */ + { MK_PAIR( TUR ) }, /* Enable transmit underrun interrupt. */ + { MK_PAIR( RLEX ) }, /* Enable retry limit exceeded interrupt. */ + { MK_PAIR( TFC ) }, /* Enable transmit buffers exhausted in mid-frame interrupt. */ + { MK_PAIR( RCOMP ) }, /* Receive complete */ + { MK_PAIR( TCOMP ) }, /* Enable transmit complete interrupt. */ + { MK_PAIR( ROVR ) }, /* Enable receive overrun interrupt. */ + { MK_PAIR( HRESP ) }, /* Enable Hresp not OK interrupt. */ + { MK_PAIR( PFNZ ) }, /* Enable pause frame received interrupt. */ + { MK_PAIR( PTZ ) } /* Enable pause time zero interrupt. */ + }; + + void gmac_show_irq_counts (); + +#endif + +#endif /* GMAC_H_INCLUDED */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Common/phyHandling.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Common/phyHandling.c new file mode 100644 index 0000000..9b222c2 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Common/phyHandling.c @@ -0,0 +1,664 @@ +/* + * Handling of Ethernet PHY's + * PHY's communicate with an EMAC either through + * a Media-Independent Interface (MII), or a Reduced Media-Independent Interface (RMII). + * The EMAC can poll for PHY ports on 32 different addresses. Each of the PHY ports + * shall be treated independently. + * + */ + +/* Standard includes. */ +#include +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" + +#include "phyHandling.h" + +#include "eventLogging.h" + +#define phyMIN_PHY_ADDRESS 0 +#define phyMAX_PHY_ADDRESS 31 + +#if defined( PHY_LS_HIGH_CHECK_TIME_MS ) || defined( PHY_LS_LOW_CHECK_TIME_MS ) + #warning please use the new defines with 'ipconfig' prefix +#endif + +#ifndef ipconfigPHY_LS_HIGH_CHECK_TIME_MS + /* Check if the LinkSStatus in the PHY is still high after 15 seconds of not + receiving packets. */ + #define ipconfigPHY_LS_HIGH_CHECK_TIME_MS 15000 +#endif + +#ifndef ipconfigPHY_LS_LOW_CHECK_TIME_MS + /* Check if the LinkSStatus in the PHY is still low every second. */ + #define ipconfigPHY_LS_LOW_CHECK_TIME_MS 1000 +#endif + +/* Naming and numbering of basic PHY registers. */ +#define phyREG_00_BMCR 0x00u /* Basic Mode Control Register. */ +#define phyREG_01_BMSR 0x01u /* Basic Mode Status Register. */ +#define phyREG_02_PHYSID1 0x02u /* PHYS ID 1 */ +#define phyREG_03_PHYSID2 0x03u /* PHYS ID 2 */ +#define phyREG_04_ADVERTISE 0x04u /* Advertisement control reg */ + +/* Naming and numbering of extended PHY registers. */ +#define PHYREG_10_PHYSTS 0x10u /* 16 PHY status register Offset */ +#define phyREG_19_PHYCR 0x19u /* 25 RW PHY Control Register */ +#define phyREG_1F_PHYSPCS 0x1Fu /* 31 RW PHY Special Control Status */ + +/* Bit fields for 'phyREG_00_BMCR', the 'Basic Mode Control Register'. */ +#define phyBMCR_FULL_DUPLEX 0x0100u /* Full duplex. */ +#define phyBMCR_AN_RESTART 0x0200u /* Auto negotiation restart. */ +#define phyBMCR_AN_ENABLE 0x1000u /* Enable auto negotiation. */ +#define phyBMCR_SPEED_100 0x2000u /* Select 100Mbps. */ +#define phyBMCR_RESET 0x8000u /* Reset the PHY. */ + +/* Bit fields for 'phyREG_19_PHYCR', the 'PHY Control Register'. */ +#define PHYCR_MDIX_EN 0x8000u /* Enable Auto MDIX. */ +#define PHYCR_MDIX_FORCE 0x4000u /* Force MDIX crossed. */ + +#define phyBMSR_AN_COMPLETE 0x0020u /* Auto-Negotiation process completed */ + +#define phyBMSR_LINK_STATUS 0x0004u + +#define phyPHYSTS_LINK_STATUS 0x0001u /* PHY Link mask */ +#define phyPHYSTS_SPEED_STATUS 0x0002u /* PHY Speed mask */ +#define phyPHYSTS_DUPLEX_STATUS 0x0004u /* PHY Duplex mask */ + +/* Bit fields for 'phyREG_1F_PHYSPCS + 001 = 10BASE-T half-duplex + 101 = 10BASE-T full-duplex + 010 = 100BASE-TX half-duplex + 110 = 100BASE-TX full-duplex +*/ +#define phyPHYSPCS_SPEED_MASK 0x000Cu +#define phyPHYSPCS_SPEED_10 0x0004u +#define phyPHYSPCS_FULL_DUPLEX 0x0010u + +/* + * Description of all capabilities that can be advertised to + * the peer (usually a switch or router). + */ +#define phyADVERTISE_CSMA 0x0001u /* Only selector supported. */ +#define phyADVERTISE_10HALF 0x0020u /* Try for 10mbps half-duplex. */ +#define phyADVERTISE_10FULL 0x0040u /* Try for 10mbps full-duplex. */ +#define phyADVERTISE_100HALF 0x0080u /* Try for 100mbps half-duplex. */ +#define phyADVERTISE_100FULL 0x0100u /* Try for 100mbps full-duplex. */ + +#define phyADVERTISE_ALL ( phyADVERTISE_10HALF | phyADVERTISE_10FULL | \ + phyADVERTISE_100HALF | phyADVERTISE_100FULL ) + +/* Send a reset commando to a set of PHY-ports. */ +static uint32_t xPhyReset( EthernetPhy_t *pxPhyObject, uint32_t ulPhyMask ); + +static BaseType_t xHas_1F_PHYSPCS( uint32_t ulPhyID ) +{ +BaseType_t xResult; + + switch( ulPhyID ) + { + case PHY_ID_LAN8720: + case PHY_ID_LAN8742A: + case PHY_ID_KSZ8041: +/* + case PHY_ID_KSZ8051: // same ID as 8041 + case PHY_ID_KSZ8081: // same ID as 8041 +*/ + case PHY_ID_KSZ8863: + default: + /* Most PHY's have a 1F_PHYSPCS */ + xResult = pdTRUE; + break; + case PHY_ID_DP83848I: + xResult = pdFALSE; + break; + } + return xResult; +} +/*-----------------------------------------------------------*/ + +static BaseType_t xHas_19_PHYCR( uint32_t ulPhyID ) +{ +BaseType_t xResult; + + switch( ulPhyID ) + { + case PHY_ID_LAN8742A: + case PHY_ID_DP83848I: + xResult = pdTRUE; + break; + default: + /* Most PHY's do not have a 19_PHYCR */ + xResult = pdFALSE; + break; + } + return xResult; +} +/*-----------------------------------------------------------*/ + +/* Initialise the struct and assign a PHY-read and -write function. */ +void vPhyInitialise( EthernetPhy_t *pxPhyObject, xApplicationPhyReadHook_t fnPhyRead, xApplicationPhyWriteHook_t fnPhyWrite ) +{ + memset( ( void * )pxPhyObject, '\0', sizeof( *pxPhyObject ) ); + + pxPhyObject->fnPhyRead = fnPhyRead; + pxPhyObject->fnPhyWrite = fnPhyWrite; +} +/*-----------------------------------------------------------*/ + +/* Discover all PHY's connected by polling 32 indexes ( zero-based ) */ +BaseType_t xPhyDiscover( EthernetPhy_t *pxPhyObject ) +{ +BaseType_t xPhyAddress; + + pxPhyObject->xPortCount = 0; + + for( xPhyAddress = phyMIN_PHY_ADDRESS; xPhyAddress <= phyMAX_PHY_ADDRESS; xPhyAddress++ ) + { + uint32_t ulLowerID; + + pxPhyObject->fnPhyRead( xPhyAddress, phyREG_03_PHYSID2, &ulLowerID ); + /* A valid PHY id can not be all zeros or all ones. */ + if( ( ulLowerID != ( uint16_t )~0u ) && ( ulLowerID != ( uint16_t )0u ) ) + { + uint32_t ulUpperID; + uint32_t ulPhyID; + + pxPhyObject->fnPhyRead( xPhyAddress, phyREG_02_PHYSID1, &ulUpperID ); + ulPhyID = ( ( ( uint32_t ) ulUpperID ) << 16 ) | ( ulLowerID & 0xFFF0 ); + + pxPhyObject->ucPhyIndexes[ pxPhyObject->xPortCount ] = xPhyAddress; + pxPhyObject->ulPhyIDs[ pxPhyObject->xPortCount ] = ulPhyID; + + pxPhyObject->xPortCount++; + + /* See if there is more storage space. */ + if( pxPhyObject->xPortCount == ipconfigPHY_MAX_PORTS ) + { + break; + } + } + } + if( pxPhyObject->xPortCount > 0 ) + { + FreeRTOS_printf( ( "PHY ID %lX\n", pxPhyObject->ulPhyIDs[ 0 ] ) ); + eventLogAdd( "PHY ID 0x%lX", pxPhyObject->ulPhyIDs[ 0 ] ); + } + + return pxPhyObject->xPortCount; +} +/*-----------------------------------------------------------*/ + +/* Send a reset commando to a set of PHY-ports. */ +static uint32_t xPhyReset( EthernetPhy_t *pxPhyObject, uint32_t ulPhyMask ) +{ +uint32_t ulDoneMask, ulConfig; +TickType_t xRemainingTime; +TimeOut_t xTimer; +BaseType_t xPhyIndex; + + /* A bit-mask ofPHY ports that are ready. */ + ulDoneMask = 0ul; + + /* Set the RESET bits high. */ + for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++ ) + { + BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ]; + + /* Read Control register. */ + pxPhyObject->fnPhyRead( xPhyAddress, phyREG_00_BMCR, &ulConfig ); + pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_00_BMCR, ulConfig | phyBMCR_RESET ); + } + + xRemainingTime = ( TickType_t ) pdMS_TO_TICKS( 1000UL ); + vTaskSetTimeOutState( &xTimer ); + + /* The reset should last less than a second. */ + for( ;; ) + { + for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++ ) + { + BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ]; + + pxPhyObject->fnPhyRead( xPhyAddress, phyREG_00_BMCR, &ulConfig ); + if( ( ulConfig & phyBMCR_RESET ) == 0 ) + { + FreeRTOS_printf( ( "xPhyReset: phyBMCR_RESET %d ready\n", (int)xPhyIndex ) ); + ulDoneMask |= ( 1ul << xPhyIndex ); + } + } + if( ulDoneMask == ulPhyMask ) + { + break; + } + if( xTaskCheckForTimeOut( &xTimer, &xRemainingTime ) != pdFALSE ) + { + FreeRTOS_printf( ( "xPhyReset: phyBMCR_RESET timed out ( done 0x%02lX )\n", ulDoneMask ) ); + break; + } + } + + /* Clear the reset bits. */ + for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++ ) + { + BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ]; + + pxPhyObject->fnPhyRead( xPhyAddress, phyREG_00_BMCR, &ulConfig ); + pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_00_BMCR, ulConfig & ~phyBMCR_RESET ); + } + + vTaskDelay( pdMS_TO_TICKS( 50ul ) ); + eventLogAdd( "PHY reset %d ports", (int)pxPhyObject->xPortCount ); + return ulDoneMask; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPhyConfigure( EthernetPhy_t *pxPhyObject, const PhyProperties_t *pxPhyProperties ) +{ +uint32_t ulConfig, ulAdvertise; +BaseType_t xPhyIndex; + + if( pxPhyObject->xPortCount < 1 ) + { + FreeRTOS_printf( ( "xPhyResetAll: No PHY's detected.\n" ) ); + return -1; + } + + /* The expected ID for the 'LAN8742A' is 0x0007c130. */ + /* The expected ID for the 'LAN8720' is 0x0007c0f0. */ + /* The expected ID for the 'DP83848I' is 0x20005C90. */ + + /* Set advertise register. */ + if( ( pxPhyProperties->ucSpeed == ( uint8_t )PHY_SPEED_AUTO ) && ( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_AUTO ) ) + { + ulAdvertise = phyADVERTISE_CSMA | phyADVERTISE_ALL; + /* Reset auto-negotiation capability. */ + } + else + { + ulAdvertise = phyADVERTISE_CSMA; + + if( pxPhyProperties->ucSpeed == ( uint8_t )PHY_SPEED_AUTO ) + { + if( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_FULL ) + { + ulAdvertise |= phyADVERTISE_10FULL | phyADVERTISE_100FULL; + } + else + { + ulAdvertise |= phyADVERTISE_10HALF | phyADVERTISE_100HALF; + } + } + else if( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_AUTO ) + { + if( pxPhyProperties->ucSpeed == ( uint8_t )PHY_SPEED_10 ) + { + ulAdvertise |= phyADVERTISE_10FULL | phyADVERTISE_10HALF; + } + else + { + ulAdvertise |= phyADVERTISE_100FULL | phyADVERTISE_100HALF; + } + } + else if( pxPhyProperties->ucSpeed == ( uint8_t )PHY_SPEED_100 ) + { + if( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_FULL ) + { + ulAdvertise |= phyADVERTISE_100FULL; + } + else + { + ulAdvertise |= phyADVERTISE_100HALF; + } + } + else + { + if( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_FULL ) + { + ulAdvertise |= phyADVERTISE_10FULL; + } + else + { + ulAdvertise |= phyADVERTISE_10HALF; + } + } + } + + /* Send a reset commando to a set of PHY-ports. */ + xPhyReset( pxPhyObject, xPhyGetMask( pxPhyObject ) ); + + for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++ ) + { + BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ]; + uint32_t ulPhyID = pxPhyObject->ulPhyIDs[ xPhyIndex ]; + + /* Write advertise register. */ + pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_04_ADVERTISE, ulAdvertise ); + + /* + AN_EN AN1 AN0 Forced Mode + 0 0 0 10BASE-T, Half-Duplex + 0 0 1 10BASE-T, Full-Duplex + 0 1 0 100BASE-TX, Half-Duplex + 0 1 1 100BASE-TX, Full-Duplex + AN_EN AN1 AN0 Advertised Mode + 1 0 0 10BASE-T, Half/Full-Duplex + 1 0 1 100BASE-TX, Half/Full-Duplex + 1 1 0 10BASE-T Half-Duplex + 100BASE-TX, Half-Duplex + 1 1 1 10BASE-T, Half/Full-Duplex + 100BASE-TX, Half/Full-Duplex + */ + + /* Read Control register. */ + pxPhyObject->fnPhyRead( xPhyAddress, phyREG_00_BMCR, &ulConfig ); + + ulConfig &= ~( phyBMCR_SPEED_100 | phyBMCR_FULL_DUPLEX ); + + ulConfig |= phyBMCR_AN_ENABLE; + + if( pxPhyProperties->ucSpeed == ( uint8_t )PHY_SPEED_100 ) + { + ulConfig |= phyBMCR_SPEED_100; + } + else if( pxPhyProperties->ucSpeed == ( uint8_t )PHY_SPEED_10 ) + { + ulConfig &= ~phyBMCR_SPEED_100; + } + + if( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_FULL ) + { + ulConfig |= phyBMCR_FULL_DUPLEX; + } + else if( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_HALF ) + { + ulConfig &= ~phyBMCR_FULL_DUPLEX; + } + + if( xHas_19_PHYCR( ulPhyID ) ) + { + uint32_t ulPhyControl; + /* Read PHY Control register. */ + pxPhyObject->fnPhyRead( xPhyAddress, phyREG_19_PHYCR, &ulPhyControl ); + + /* Clear bits which might get set: */ + ulPhyControl &= ~( PHYCR_MDIX_EN|PHYCR_MDIX_FORCE ); + + if( pxPhyProperties->ucMDI_X == PHY_MDIX_AUTO ) + { + ulPhyControl |= PHYCR_MDIX_EN; + } + else if( pxPhyProperties->ucMDI_X == PHY_MDIX_CROSSED ) + { + /* Force direct link = Use crossed RJ45 cable. */ + ulPhyControl &= ~PHYCR_MDIX_FORCE; + } + else + { + /* Force crossed link = Use direct RJ45 cable. */ + ulPhyControl |= PHYCR_MDIX_FORCE; + } + /* update PHY Control Register. */ + pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_19_PHYCR, ulPhyControl ); + } + + FreeRTOS_printf( ( "+TCP: advertise: %04lX config %04lX\n", ulAdvertise, ulConfig ) ); + eventLogAdd( "adv: %04lX config %04lX", ulAdvertise, ulConfig ); + } + + /* Keep these values for later use. */ + pxPhyObject->ulBCRValue = ulConfig; + pxPhyObject->ulACRValue = ulAdvertise; + + return 0; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPhyFixedValue( EthernetPhy_t *pxPhyObject, uint32_t ulPhyMask ) +{ +BaseType_t xPhyIndex; +uint32_t ulValue, ulBitMask = ( uint32_t )1u; + + ulValue = ( uint32_t )0u; + + if( pxPhyObject->xPhyPreferences.ucDuplex == PHY_DUPLEX_FULL ) + { + ulValue |= phyBMCR_FULL_DUPLEX; + } + if( pxPhyObject->xPhyPreferences.ucSpeed == PHY_SPEED_100 ) + { + ulValue |= phyBMCR_SPEED_100; + } + + for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++, ulBitMask <<= 1 ) + { + if( ( ulPhyMask & ulBitMask ) != 0lu ) + { + BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ]; + + /* Enable Auto-Negotiation. */ + pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_00_BMCR, ulValue ); + } + } + return 0; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPhyStartAutoNegotiation( EthernetPhy_t *pxPhyObject, uint32_t ulPhyMask ) +{ +uint32_t xPhyIndex, ulDoneMask, ulBitMask; +uint32_t ulPHYLinkStatus, ulRegValue; +TickType_t xRemainingTime; +TimeOut_t xTimer; + + if( ulPhyMask == ( uint32_t )0u ) + { + return 0; + } + for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++ ) + { + if( ( ulPhyMask & ( 1lu << xPhyIndex ) ) != 0lu ) + { + BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ]; + + /* Enable Auto-Negotiation. */ + pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_04_ADVERTISE, pxPhyObject->ulACRValue); + pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_00_BMCR, pxPhyObject->ulBCRValue | phyBMCR_AN_RESTART ); + } + } +eventLogAdd( "AN start" ); + xRemainingTime = ( TickType_t ) pdMS_TO_TICKS( 3000UL ); + vTaskSetTimeOutState( &xTimer ); + ulDoneMask = 0; + /* Wait until the auto-negotiation will be completed */ + for( ;; ) + { + ulBitMask = ( uint32_t )1u; + for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++, ulBitMask <<= 1 ) + { + if( ( ulPhyMask & ulBitMask ) != 0lu ) + { + if( ( ulDoneMask & ulBitMask ) == 0lu ) + { + BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ]; + + pxPhyObject->fnPhyRead( xPhyAddress, phyREG_01_BMSR, &ulRegValue ); + if( ( ulRegValue & phyBMSR_AN_COMPLETE ) != 0 ) + { + ulDoneMask |= ulBitMask; + } + } + } + } + if( ulPhyMask == ulDoneMask ) + { + break; + } + if( xTaskCheckForTimeOut( &xTimer, &xRemainingTime ) != pdFALSE ) + { + FreeRTOS_printf( ( "xPhyReset: phyBMCR_RESET timed out ( done 0x%02lX )\n", ulDoneMask ) ); + eventLogAdd( "ANtimed out"); + break; + } + } +eventLogAdd( "AN done %02lX / %02lX", ulDoneMask, ulPhyMask ); + + if( ulDoneMask != ( uint32_t)0u ) + { + ulBitMask = ( uint32_t )1u; + pxPhyObject->ulLinkStatusMask &= ~( ulDoneMask ); + for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++, ulBitMask <<= 1 ) + { + BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ]; + uint32_t ulPhyID = pxPhyObject->ulPhyIDs[ xPhyIndex ]; + + if( ( ulDoneMask & ulBitMask ) == ( uint32_t )0u ) + { + continue; + } + + /* Clear the 'phyBMCR_AN_RESTART' bit. */ + pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_00_BMCR, pxPhyObject->ulBCRValue ); + + pxPhyObject->fnPhyRead( xPhyAddress, phyREG_01_BMSR, &ulRegValue); + if( ( ulRegValue & phyBMSR_LINK_STATUS ) != 0 ) + { + ulPHYLinkStatus |= phyBMSR_LINK_STATUS; + pxPhyObject->ulLinkStatusMask |= ulBitMask; + } + else + { + ulPHYLinkStatus &= ~( phyBMSR_LINK_STATUS ); + } + + if( xHas_1F_PHYSPCS( ulPhyID ) ) + { + /* 31 RW PHY Special Control Status */ + uint32_t ulControlStatus; + + pxPhyObject->fnPhyRead( xPhyAddress, phyREG_1F_PHYSPCS, &ulControlStatus); + ulRegValue = 0; + if( ( ulControlStatus & phyPHYSPCS_FULL_DUPLEX ) != 0 ) + { + ulRegValue |= phyPHYSTS_DUPLEX_STATUS; + } + if( ( ulControlStatus & phyPHYSPCS_SPEED_MASK ) == phyPHYSPCS_SPEED_10 ) + { + ulRegValue |= phyPHYSTS_SPEED_STATUS; + } + + } + else + { + /* Read the result of the auto-negotiation. */ + pxPhyObject->fnPhyRead( xPhyAddress, PHYREG_10_PHYSTS, &ulRegValue); + } + + FreeRTOS_printf( ( ">> Autonego ready: %08lx: %s duplex %u mbit %s status\n", + ulRegValue, + ( ulRegValue & phyPHYSTS_DUPLEX_STATUS ) ? "full" : "half", + ( ulRegValue & phyPHYSTS_SPEED_STATUS ) ? 10 : 100, + ( ( ulPHYLinkStatus |= phyBMSR_LINK_STATUS ) != 0) ? "high" : "low" ) ); + eventLogAdd( "%s duplex %u mbit %s st", + ( ulRegValue & phyPHYSTS_DUPLEX_STATUS ) ? "full" : "half", + ( ulRegValue & phyPHYSTS_SPEED_STATUS ) ? 10 : 100, + ( ( ulPHYLinkStatus |= phyBMSR_LINK_STATUS ) != 0) ? "high" : "low" ); +{ + uint32_t regs[4]; + int i,j; + int address = 0x10; + for (i = 0; i < 4; i++) + { + for (j = 0; j < 4; j++) + { + pxPhyObject->fnPhyRead( xPhyAddress, address, regs + j ); + address++; + } + eventLogAdd("%04lX %04lX %04lX %04lX", + regs[0], regs[1], regs[2], regs[3]); + } +} + if( ( ulRegValue & phyPHYSTS_DUPLEX_STATUS ) != ( uint32_t )0u ) + { + pxPhyObject->xPhyProperties.ucDuplex = PHY_DUPLEX_FULL; + } + else + { + pxPhyObject->xPhyProperties.ucDuplex = PHY_DUPLEX_HALF; + } + + if( ( ulRegValue & phyPHYSTS_SPEED_STATUS ) != 0 ) + { + pxPhyObject->xPhyProperties.ucSpeed = PHY_SPEED_10; + } + else + { + pxPhyObject->xPhyProperties.ucSpeed = PHY_SPEED_100; + } + } + } /* if( ulDoneMask != ( uint32_t)0u ) */ + + return 0; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPhyCheckLinkStatus( EthernetPhy_t *pxPhyObject, BaseType_t xHadReception ) +{ +uint32_t ulStatus, ulBitMask = 1u; +BaseType_t xPhyIndex; +BaseType_t xNeedCheck = pdFALSE; + + if( xHadReception > 0 ) + { + /* A packet was received. No need to check for the PHY status now, + but set a timer to check it later on. */ + vTaskSetTimeOutState( &( pxPhyObject->xLinkStatusTimer ) ); + pxPhyObject->xLinkStatusRemaining = pdMS_TO_TICKS( ipconfigPHY_LS_HIGH_CHECK_TIME_MS ); + } + else if( xTaskCheckForTimeOut( &( pxPhyObject->xLinkStatusTimer ), &( pxPhyObject->xLinkStatusRemaining ) ) != pdFALSE ) + { + for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++, ulBitMask <<= 1 ) + { + BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ]; + + if( pxPhyObject->fnPhyRead( xPhyAddress, phyREG_01_BMSR, &ulStatus ) == 0 ) + { + if( !!( pxPhyObject->ulLinkStatusMask & ulBitMask ) != !!( ulStatus & phyBMSR_LINK_STATUS ) ) + { + if( ( ulStatus & phyBMSR_LINK_STATUS ) != 0 ) + { + pxPhyObject->ulLinkStatusMask |= ulBitMask; + } + else + { + pxPhyObject->ulLinkStatusMask &= ~( ulBitMask ); + } + FreeRTOS_printf( ( "xPhyCheckLinkStatus: PHY LS now %02lX\n", pxPhyObject->ulLinkStatusMask ) ); + eventLogAdd( "PHY LS now %02lX", pxPhyObject->ulLinkStatusMask ); + xNeedCheck = pdTRUE; + } + } + } + vTaskSetTimeOutState( &( pxPhyObject->xLinkStatusTimer ) ); + if( ( pxPhyObject->ulLinkStatusMask & phyBMSR_LINK_STATUS ) != 0 ) + { + pxPhyObject->xLinkStatusRemaining = pdMS_TO_TICKS( ipconfigPHY_LS_HIGH_CHECK_TIME_MS ); + } + else + { + pxPhyObject->xLinkStatusRemaining = pdMS_TO_TICKS( ipconfigPHY_LS_LOW_CHECK_TIME_MS ); + } + } + return xNeedCheck; +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/LPC17xx/NetworkInterface.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/LPC17xx/NetworkInterface.c new file mode 100644 index 0000000..e0d04e4 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/LPC17xx/NetworkInterface.c @@ -0,0 +1,267 @@ +/* +FreeRTOS+TCP V2.0.11 +Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + http://aws.amazon.com/freertos + http://www.FreeRTOS.org +*/ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Hardware abstraction. */ +#include "FreeRTOS_IO.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_UDP_IP.h" +#include "FreeRTOS_Sockets.h" +#include "NetworkBufferManagement.h" + +/* Driver includes. */ +#include "lpc17xx_emac.h" +#include "lpc17xx_pinsel.h" + +/* Demo includes. */ +#include "NetworkInterface.h" + +#if ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES != 1 + #define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eProcessBuffer +#else + #define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eConsiderFrameForProcessing( ( pucEthernetBuffer ) ) +#endif + +/* When a packet is ready to be sent, if it cannot be sent immediately then the +task performing the transmit will block for niTX_BUFFER_FREE_WAIT +milliseconds. It will do this a maximum of niMAX_TX_ATTEMPTS before giving +up. */ +#define niTX_BUFFER_FREE_WAIT ( pdMS_TO_TICKS( 2UL ) ) +#define niMAX_TX_ATTEMPTS ( 5 ) + +/* The length of the queue used to send interrupt status words from the +interrupt handler to the deferred handler task. */ +#define niINTERRUPT_QUEUE_LENGTH ( 10 ) + +/*-----------------------------------------------------------*/ + +/* + * A deferred interrupt handler task that processes + */ +static void prvEMACHandlerTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used to communicate Ethernet events with the IP task. */ +extern QueueHandle_t xNetworkEventQueue; + +/* The semaphore used to wake the deferred interrupt handler task when an Rx +interrupt is received. */ +static SemaphoreHandle_t xEMACRxEventSemaphore = NULL; +/*-----------------------------------------------------------*/ + +BaseType_t xNetworkInterfaceInitialise( void ) +{ +EMAC_CFG_Type Emac_Config; +PINSEL_CFG_Type xPinConfig; +BaseType_t xStatus, xReturn; +extern uint8_t ucMACAddress[ 6 ]; + + /* Enable Ethernet Pins */ + boardCONFIGURE_ENET_PINS( xPinConfig ); + + Emac_Config.Mode = EMAC_MODE_AUTO; + Emac_Config.pbEMAC_Addr = ucMACAddress; + xStatus = EMAC_Init( &Emac_Config ); + + LPC_EMAC->IntEnable &= ~( EMAC_INT_TX_DONE ); + + if( xStatus != ERROR ) + { + vSemaphoreCreateBinary( xEMACRxEventSemaphore ); + configASSERT( xEMACRxEventSemaphore ); + + /* The handler task is created at the highest possible priority to + ensure the interrupt handler can return directly to it. */ + xTaskCreate( prvEMACHandlerTask, "EMAC", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); + + /* Enable the interrupt and set its priority to the minimum + interrupt priority. */ + NVIC_SetPriority( ENET_IRQn, configMAC_INTERRUPT_PRIORITY ); + NVIC_EnableIRQ( ENET_IRQn ); + + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + + configASSERT( xStatus != ERROR ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xNetworkInterfaceOutput( NetworkBufferDescriptor_t * const pxNetworkBuffer ) +{ +BaseType_t xReturn = pdFAIL; +int32_t x; +extern void EMAC_StartTransmitNextBuffer( uint32_t ulLength ); +extern void EMAC_SetNextPacketToSend( uint8_t * pucBuffer ); + + + /* Attempt to obtain access to a Tx buffer. */ + for( x = 0; x < niMAX_TX_ATTEMPTS; x++ ) + { + if( EMAC_CheckTransmitIndex() == TRUE ) + { + /* Will the data fit in the Tx buffer? */ + if( pxNetworkBuffer->xDataLength < EMAC_ETH_MAX_FLEN ) /*_RB_ The size needs to come from FreeRTOSIPConfig.h. */ + { + /* Assign the buffer to the Tx descriptor that is now known to + be free. */ + EMAC_SetNextPacketToSend( pxNetworkBuffer->pucBuffer ); + + /* The EMAC now owns the buffer. */ + pxNetworkBuffer->pucBuffer = NULL; + + /* Initiate the Tx. */ + EMAC_StartTransmitNextBuffer( pxNetworkBuffer->xDataLength ); + iptraceNETWORK_INTERFACE_TRANSMIT(); + + /* The Tx has been initiated. */ + xReturn = pdPASS; + } + break; + } + else + { + vTaskDelay( niTX_BUFFER_FREE_WAIT ); + } + } + + /* Finished with the network buffer. */ + vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void ENET_IRQHandler( void ) +{ +uint32_t ulInterruptCause; + + while( ( ulInterruptCause = LPC_EMAC->IntStatus ) != 0 ) + { + /* Clear the interrupt. */ + LPC_EMAC->IntClear = ulInterruptCause; + + /* Clear fatal error conditions. NOTE: The driver does not clear all + errors, only those actually experienced. For future reference, range + errors are not actually errors so can be ignored. */ + if( ( ulInterruptCause & EMAC_INT_TX_UNDERRUN ) != 0U ) + { + LPC_EMAC->Command |= EMAC_CR_TX_RES; + } + + /* Unblock the deferred interrupt handler task if the event was an + Rx. */ + if( ( ulInterruptCause & EMAC_INT_RX_DONE ) != 0UL ) + { + xSemaphoreGiveFromISR( xEMACRxEventSemaphore, NULL ); + } + } + + /* ulInterruptCause is used for convenience here. A context switch is + wanted, but coding portEND_SWITCHING_ISR( 1 ) would likely result in a + compiler warning. */ + portEND_SWITCHING_ISR( ulInterruptCause ); +} +/*-----------------------------------------------------------*/ + +static void prvEMACHandlerTask( void *pvParameters ) +{ +size_t xDataLength; +const uint16_t usCRCLength = 4; +NetworkBufferDescriptor_t *pxNetworkBuffer; +IPStackEvent_t xRxEvent = { eNetworkRxEvent, NULL }; + +/* This is not included in the header file for some reason. */ +extern uint8_t *EMAC_NextPacketToRead( void ); + + ( void ) pvParameters; + configASSERT( xEMACRxEventSemaphore ); + + for( ;; ) + { + /* Wait for the EMAC interrupt to indicate that another packet has been + received. The while() loop is only needed if INCLUDE_vTaskSuspend is + set to 0 in FreeRTOSConfig.h. */ + while( xSemaphoreTake( xEMACRxEventSemaphore, portMAX_DELAY ) == pdFALSE ); + + /* At least one packet has been received. */ + while( EMAC_CheckReceiveIndex() != FALSE ) + { + /* Obtain the length, minus the CRC. The CRC is four bytes + but the length is already minus 1. */ + xDataLength = ( size_t ) EMAC_GetReceiveDataSize() - ( usCRCLength - 1U ); + + if( xDataLength > 0U ) + { + /* Obtain a network buffer to pass this data into the + stack. No storage is required as the network buffer + will point directly to the buffer that already holds + the received data. */ + pxNetworkBuffer = pxGetNetworkBufferWithDescriptor( 0, ( TickType_t ) 0 ); + + if( pxNetworkBuffer != NULL ) + { + pxNetworkBuffer->pucBuffer = EMAC_NextPacketToRead(); + pxNetworkBuffer->xDataLength = xDataLength; + xRxEvent.pvData = ( void * ) pxNetworkBuffer; + + /* Data was received and stored. Send a message to the IP + task to let it know. */ + if( xSendEventStructToIPTask( &xRxEvent, ( TickType_t ) 0 ) == pdFAIL ) + { + vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ); + iptraceETHERNET_RX_EVENT_LOST(); + } + } + else + { + iptraceETHERNET_RX_EVENT_LOST(); + } + + iptraceNETWORK_INTERFACE_RECEIVE(); + } + + /* Release the frame. */ + EMAC_UpdateRxConsumeIndex(); + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/LPC18xx/NetworkInterface.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/LPC18xx/NetworkInterface.c new file mode 100644 index 0000000..ac01d41 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/LPC18xx/NetworkInterface.c @@ -0,0 +1,1068 @@ +/* +FreeRTOS+TCP V2.0.11 +Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + http://aws.amazon.com/freertos + http://www.FreeRTOS.org +*/ + +/* Standard includes. */ +#include +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_IP_Private.h" +#include "NetworkBufferManagement.h" +#include "NetworkInterface.h" + +/* LPCOpen includes. */ +#include "chip.h" +#include "lpc_phy.h" + +/* The size of the stack allocated to the task that handles Rx packets. */ +#define nwRX_TASK_STACK_SIZE 140 + +#ifndef PHY_LS_HIGH_CHECK_TIME_MS + /* Check if the LinkSStatus in the PHY is still high after 15 seconds of not + receiving packets. */ + #define PHY_LS_HIGH_CHECK_TIME_MS 15000 +#endif + +#ifndef PHY_LS_LOW_CHECK_TIME_MS + /* Check if the LinkSStatus in the PHY is still low every second. */ + #define PHY_LS_LOW_CHECK_TIME_MS 1000 +#endif + +#ifndef configUSE_RMII + #define configUSE_RMII 1 +#endif + +#ifndef configNUM_RX_DESCRIPTORS + #error please define configNUM_RX_DESCRIPTORS in your FreeRTOSIPConfig.h +#endif + +#ifndef configNUM_TX_DESCRIPTORS + #error please define configNUM_TX_DESCRIPTORS in your FreeRTOSIPConfig.h +#endif + +#ifndef NETWORK_IRQHandler + #error NETWORK_IRQHandler must be defined to the name of the function that is installed in the interrupt vector table to handle Ethernet interrupts. +#endif + +#if !defined( MAC_FF_HMC ) + /* Hash for multicast. */ + #define MAC_FF_HMC ( 1UL << 2UL ) +#endif + +#ifndef iptraceEMAC_TASK_STARTING + #define iptraceEMAC_TASK_STARTING() do { } while( 0 ) +#endif + +/* Define the bits of .STATUS that indicate a reception error. */ +#define nwRX_STATUS_ERROR_BITS \ + ( RDES_CE /* CRC Error */ | \ + RDES_RE /* Receive Error */ | \ + RDES_DE /* Descriptor Error */ | \ + RDES_RWT /* Receive Watchdog Timeout */ | \ + RDES_LC /* Late Collision */ | \ + RDES_OE /* Overflow Error */ | \ + RDES_SAF /* Source Address Filter Fail */ | \ + RDES_AFM /* Destination Address Filter Fail */ | \ + RDES_LE /* Length Error */ ) + +/* Define the EMAC status bits that should trigger an interrupt. */ +#define nwDMA_INTERRUPT_MASK \ + ( DMA_IE_TIE /* Transmit interrupt enable */ | \ + DMA_IE_TSE /* Transmit stopped enable */ | \ + DMA_IE_OVE /* Overflow interrupt enable */ | \ + DMA_IE_RIE /* Receive interrupt enable */ | \ + DMA_IE_NIE /* Normal interrupt summary enable */ | \ + DMA_IE_AIE /* Abnormal interrupt summary enable */ | \ + DMA_IE_RUE /* Receive buffer unavailable enable */ | \ + DMA_IE_UNE /* Underflow interrupt enable. */ | \ + DMA_IE_TJE /* Transmit jabber timeout enable */ | \ + DMA_IE_RSE /* Received stopped enable */ | \ + DMA_IE_RWE /* Receive watchdog timeout enable */ | \ + DMA_IE_FBE )/* Fatal bus error enable */ + +/* Interrupt events to process. Currently only the RX/TX events are processed +although code for other events is included to allow for possible future +expansion. */ +#define EMAC_IF_RX_EVENT 1UL +#define EMAC_IF_TX_EVENT 2UL +#define EMAC_IF_ERR_EVENT 4UL +#define EMAC_IF_ALL_EVENT ( EMAC_IF_RX_EVENT | EMAC_IF_TX_EVENT | EMAC_IF_ERR_EVENT ) + + /* If ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES is set to 1, then the Ethernet + driver will filter incoming packets and only pass the stack those packets it + considers need processing. */ + #if( ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES == 0 ) + #define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eProcessBuffer + #else + #define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eConsiderFrameForProcessing( ( pucEthernetBuffer ) ) + #endif + +#if( ipconfigZERO_COPY_RX_DRIVER == 0 ) || ( ipconfigZERO_COPY_TX_DRIVER == 0 ) + #warning It is adviced to enable both macros +#endif + +#ifndef configPLACE_IN_SECTION_RAM + #define configPLACE_IN_SECTION_RAM +/* + #define configPLACE_IN_SECTION_RAM __attribute__ ((section(".ramfunc"))) +*/ +#endif + +/*-----------------------------------------------------------*/ + +/* + * Delay function passed into the library. The implementation uses FreeRTOS + * calls so the scheduler must be started before the driver can be used. + */ +static void prvDelay( uint32_t ulMilliSeconds ); + +/* + * Initialises the Tx and Rx descriptors respectively. + */ +static void prvSetupTxDescriptors( void ); +static void prvSetupRxDescriptors( void ); + +/* + * A task that processes received frames. + */ +static void prvEMACHandlerTask( void *pvParameters ); + +/* + * Sets up the MAC with the results of an auto-negotiation. + */ +static BaseType_t prvSetLinkSpeed( void ); + +/* + * Generates a CRC for a MAC address that is then used to generate a hash index. + */ +static uint32_t prvGenerateCRC32( const uint8_t *ucAddress ); + +/* + * Generates a hash index when setting a filter to permit a MAC address. + */ +static uint32_t prvGetHashIndex( const uint8_t *ucAddress ); + +/* + * Update the hash table to allow a MAC address. + */ +static void prvAddMACAddress( const uint8_t* ucMacAddress ); + +/* + * Sometimes the DMA will report received data as being longer than the actual + * received from length. This function checks the reported length and corrects + * if if necessary. + */ +static void prvRemoveTrailingBytes( NetworkBufferDescriptor_t *pxDescriptor ); + +/*-----------------------------------------------------------*/ + +/* Bit map of outstanding ETH interrupt events for processing. Currently only +the Rx and Tx interrupt is handled, although code is included for other events +to enable future expansion. */ +static volatile uint32_t ulISREvents; + +/* A copy of PHY register 1: 'PHY_REG_01_BMSR' */ +static uint32_t ulPHYLinkStatus = 0; + +/* Tx descriptors and index. */ +static ENET_ENHTXDESC_T xDMATxDescriptors[ configNUM_TX_DESCRIPTORS ]; + +/* ulNextFreeTxDescriptor is declared volatile, because it is accessed from +to different tasks. */ +static volatile uint32_t ulNextFreeTxDescriptor; +static uint32_t ulTxDescriptorToClear; + +/* Rx descriptors and index. */ +static ENET_ENHRXDESC_T xDMARxDescriptors[ configNUM_RX_DESCRIPTORS ]; +static uint32_t ulNextRxDescriptorToProcess; + +/* Must be defined externally - the demo applications define this in main.c. */ +extern uint8_t ucMACAddress[ 6 ]; + +/* The handle of the task that processes Rx packets. The handle is required so +the task can be notified when new packets arrive. */ +static TaskHandle_t xRxHanderTask = NULL; + +#if( ipconfigUSE_LLMNR == 1 ) + static const uint8_t xLLMNR_MACAddress[] = { '\x01', '\x00', '\x5E', '\x00', '\x00', '\xFC' }; +#endif /* ipconfigUSE_LLMNR == 1 */ + +/* xTXDescriptorSemaphore is a counting semaphore with +a maximum count of ETH_TXBUFNB, which is the number of +DMA TX descriptors. */ +static SemaphoreHandle_t xTXDescriptorSemaphore = NULL; + +/*-----------------------------------------------------------*/ + + +BaseType_t xNetworkInterfaceInitialise( void ) +{ +BaseType_t xReturn = pdPASS; + + /* The interrupt will be turned on when a link is established. */ + NVIC_DisableIRQ( ETHERNET_IRQn ); + + /* Disable receive and transmit DMA processes. */ + LPC_ETHERNET->DMA_OP_MODE &= ~( DMA_OM_ST | DMA_OM_SR ); + + /* Disable packet reception. */ + LPC_ETHERNET->MAC_CONFIG &= ~( MAC_CFG_RE | MAC_CFG_TE ); + + /* Call the LPCOpen function to initialise the hardware. */ + Chip_ENET_Init( LPC_ETHERNET ); + + /* Save MAC address. */ + Chip_ENET_SetADDR( LPC_ETHERNET, ucMACAddress ); + + /* Clear all MAC address hash entries. */ + LPC_ETHERNET->MAC_HASHTABLE_HIGH = 0; + LPC_ETHERNET->MAC_HASHTABLE_LOW = 0; + + #if( ipconfigUSE_LLMNR == 1 ) + { + prvAddMACAddress( xLLMNR_MACAddress ); + } + #endif /* ipconfigUSE_LLMNR == 1 */ + + /* Promiscuous flag (PR) and Receive All flag (RA) set to zero. The + registers MAC_HASHTABLE_[LOW|HIGH] will be loaded to allow certain + multi-cast addresses. */ + LPC_ETHERNET->MAC_FRAME_FILTER = MAC_FF_HMC; + + #if( configUSE_RMII == 1 ) + { + if( lpc_phy_init( pdTRUE, prvDelay ) != SUCCESS ) + { + xReturn = pdFAIL; + } + } + #else + { + #warning This path has not been tested. + if( lpc_phy_init( pdFALSE, prvDelay ) != SUCCESS ) + { + xReturn = pdFAIL; + } + } + #endif + + if( xReturn == pdPASS ) + { + /* Guard against the task being created more than once and the + descriptors being initialised more than once. */ + if( xRxHanderTask == NULL ) + { + xReturn = xTaskCreate( prvEMACHandlerTask, "EMAC", nwRX_TASK_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, &xRxHanderTask ); + configASSERT( xReturn ); + } + + if( xTXDescriptorSemaphore == NULL ) + { + /* Create a counting semaphore, with a value of 'configNUM_TX_DESCRIPTORS' + and a maximum of 'configNUM_TX_DESCRIPTORS'. */ + xTXDescriptorSemaphore = xSemaphoreCreateCounting( ( UBaseType_t ) configNUM_TX_DESCRIPTORS, ( UBaseType_t ) configNUM_TX_DESCRIPTORS ); + configASSERT( xTXDescriptorSemaphore ); + } + + /* Enable MAC interrupts. */ + LPC_ETHERNET->DMA_INT_EN = nwDMA_INTERRUPT_MASK; + } + + if( xReturn != pdFAIL ) + { + /* Auto-negotiate was already started. Wait for it to complete. */ + xReturn = prvSetLinkSpeed(); + + if( xReturn == pdPASS ) + { + /* Initialise the descriptors. */ + prvSetupTxDescriptors(); + prvSetupRxDescriptors(); + + /* Clear all interrupts. */ + LPC_ETHERNET->DMA_STAT = DMA_ST_ALL; + + /* Enable receive and transmit DMA processes. */ + LPC_ETHERNET->DMA_OP_MODE |= DMA_OM_ST | DMA_OM_SR; + + /* Set Receiver / Transmitter Enable. */ + LPC_ETHERNET->MAC_CONFIG |= MAC_CFG_RE | MAC_CFG_TE; + + /* Start receive polling. */ + LPC_ETHERNET->DMA_REC_POLL_DEMAND = 1; + + /* Enable interrupts in the NVIC. */ + NVIC_SetPriority( ETHERNET_IRQn, configMAC_INTERRUPT_PRIORITY ); + NVIC_EnableIRQ( ETHERNET_IRQn ); + } + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#define niBUFFER_1_PACKET_SIZE 1536 + +static __attribute__ ((section("._ramAHB32"))) uint8_t ucNetworkPackets[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS * niBUFFER_1_PACKET_SIZE ] __attribute__ ( ( aligned( 32 ) ) ); + +void vNetworkInterfaceAllocateRAMToBuffers( NetworkBufferDescriptor_t pxNetworkBuffers[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ] ) +{ + +uint8_t *ucRAMBuffer = ucNetworkPackets; +uint32_t ul; + + for( ul = 0; ul < ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS; ul++ ) + { + pxNetworkBuffers[ ul ].pucEthernetBuffer = ucRAMBuffer + ipBUFFER_PADDING; + *( ( unsigned * ) ucRAMBuffer ) = ( unsigned ) ( &( pxNetworkBuffers[ ul ] ) ); + ucRAMBuffer += niBUFFER_1_PACKET_SIZE; + } +} +/*-----------------------------------------------------------*/ + +configPLACE_IN_SECTION_RAM +static void vClearTXBuffers() +{ +uint32_t ulLastDescriptor = ulNextFreeTxDescriptor; +size_t uxCount = ( ( size_t ) configNUM_TX_DESCRIPTORS ) - uxSemaphoreGetCount( xTXDescriptorSemaphore ); +#if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + NetworkBufferDescriptor_t *pxNetworkBuffer; + uint8_t *ucPayLoad; +#endif + + /* This function is called after a TX-completion interrupt. + It will release each Network Buffer used in xNetworkInterfaceOutput(). + 'uxCount' represents the number of descriptors given to DMA for transmission. + After sending a packet, the DMA will clear the 'TDES_OWN' bit. */ + while( ( uxCount > ( size_t ) 0u ) && ( ( xDMATxDescriptors[ ulTxDescriptorToClear ].CTRLSTAT & TDES_OWN ) == 0 ) ) + { + if( ( ulTxDescriptorToClear == ulLastDescriptor ) && ( uxCount != ( size_t ) configNUM_TX_DESCRIPTORS ) ) + { + break; + } + + + #if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + { + ucPayLoad = ( uint8_t * )xDMATxDescriptors[ ulTxDescriptorToClear ].B1ADD; + if( ucPayLoad != NULL ) + { + /* B1ADD points to a pucEthernetBuffer of a Network Buffer descriptor. */ + pxNetworkBuffer = pxPacketBuffer_to_NetworkBuffer( ucPayLoad ); + + configASSERT( pxNetworkBuffer != NULL ); + + vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ) ; + xDMATxDescriptors[ ulTxDescriptorToClear ].B1ADD = ( uint32_t )0u; + } + } + #endif /* ipconfigZERO_COPY_TX_DRIVER */ + + /* Move onto the next descriptor, wrapping if necessary. */ + ulTxDescriptorToClear++; + if( ulTxDescriptorToClear >= configNUM_TX_DESCRIPTORS ) + { + ulTxDescriptorToClear = 0; + } + + uxCount--; + /* Tell the counting semaphore that one more TX descriptor is available. */ + xSemaphoreGive( xTXDescriptorSemaphore ); + } +} + +/*-----------------------------------------------------------*/ + +configPLACE_IN_SECTION_RAM +BaseType_t xNetworkInterfaceOutput( NetworkBufferDescriptor_t * const pxDescriptor, BaseType_t bReleaseAfterSend ) +{ +BaseType_t xReturn = pdFAIL; +const TickType_t xBlockTimeTicks = pdMS_TO_TICKS( 50 ); + + /* Attempt to obtain access to a Tx descriptor. */ + do + { + if( xTXDescriptorSemaphore == NULL ) + { + break; + } + if( xSemaphoreTake( xTXDescriptorSemaphore, xBlockTimeTicks ) != pdPASS ) + { + /* Time-out waiting for a free TX descriptor. */ + break; + } + + /* If the descriptor is still owned by the DMA it can't be used. */ + if( ( xDMATxDescriptors[ ulNextFreeTxDescriptor ].CTRLSTAT & TDES_OWN ) != 0 ) + { + /* The semaphore was taken, the TX DMA-descriptor is still not available. + Actually that should not occur, the 'TDES_OWN' was already confirmed low in vClearTXBuffers(). */ + xSemaphoreGive( xTXDescriptorSemaphore ); + } + else + { + #if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + { + /* bReleaseAfterSend should always be set when using the zero + copy driver. */ + configASSERT( bReleaseAfterSend != pdFALSE ); + + /* The DMA's descriptor to point directly to the data in the + network buffer descriptor. The data is not copied. */ + xDMATxDescriptors[ ulNextFreeTxDescriptor ].B1ADD = ( uint32_t ) pxDescriptor->pucEthernetBuffer; + + /* The DMA descriptor will 'own' this Network Buffer, + until it has been sent. So don't release it now. */ + bReleaseAfterSend = false; + } + #else + { + /* The data is copied from the network buffer descriptor into + the DMA's descriptor. */ + memcpy( ( void * ) xDMATxDescriptors[ ulNextFreeTxDescriptor ].B1ADD, ( void * ) pxDescriptor->pucEthernetBuffer, pxDescriptor->xDataLength ); + } + #endif + + xDMATxDescriptors[ ulNextFreeTxDescriptor ].BSIZE = ( uint32_t ) TDES_ENH_BS1( pxDescriptor->xDataLength ); + + /* This descriptor is given back to the DMA. */ + xDMATxDescriptors[ ulNextFreeTxDescriptor ].CTRLSTAT |= TDES_OWN; + + /* Ensure the DMA is polling Tx descriptors. */ + LPC_ETHERNET->DMA_TRANS_POLL_DEMAND = 1; + + iptraceNETWORK_INTERFACE_TRANSMIT(); + + /* Move onto the next descriptor, wrapping if necessary. */ + ulNextFreeTxDescriptor++; + if( ulNextFreeTxDescriptor >= configNUM_TX_DESCRIPTORS ) + { + ulNextFreeTxDescriptor = 0; + } + + /* The Tx has been initiated. */ + xReturn = pdPASS; + } + } while( 0 ); + + /* The buffer has been sent so can be released. */ + if( bReleaseAfterSend != pdFALSE ) + { + vReleaseNetworkBufferAndDescriptor( pxDescriptor ); + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static void prvDelay( uint32_t ulMilliSeconds ) +{ + /* Ensure the scheduler was started before attempting to use the scheduler to + create a delay. */ + configASSERT( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ); + + vTaskDelay( pdMS_TO_TICKS( ulMilliSeconds ) ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupTxDescriptors( void ) +{ +BaseType_t x; + + /* Start with Tx descriptors clear. */ + memset( ( void * ) xDMATxDescriptors, 0, sizeof( xDMATxDescriptors ) ); + + /* Index to the next Tx descriptor to use. */ + ulNextFreeTxDescriptor = 0ul; + + /* Index to the next Tx descriptor to clear ( after transmission ). */ + ulTxDescriptorToClear = 0ul; + + for( x = 0; x < configNUM_TX_DESCRIPTORS; x++ ) + { + #if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + { + /* Nothing to do, B1ADD will be set when data is ready to transmit. + Currently the memset above will have set it to NULL. */ + } + #else + { + /* Allocate a buffer to the Tx descriptor. This is the most basic + way of creating a driver as the data is then copied into the + buffer. */ + xDMATxDescriptors[ x ].B1ADD = ( uint32_t ) pvPortMalloc( ipTOTAL_ETHERNET_FRAME_SIZE ); + + /* Use an assert to check the allocation as +TCP applications will + often not use a malloc() failed hook as the TCP stack will recover + from allocation failures. */ + configASSERT( xDMATxDescriptors[ x ].B1ADD ); + } + #endif + + /* Buffers hold an entire frame so all buffers are both the start and + end of a frame. */ + /* TDES_ENH_TCH Second Address Chained. */ + /* TDES_ENH_CIC(n) Checksum Insertion Control, tried but it does not work for the LPC18xx... */ + /* TDES_ENH_FS First Segment. */ + /* TDES_ENH_LS Last Segment. */ + /* TDES_ENH_IC Interrupt on Completion. */ + xDMATxDescriptors[ x ].CTRLSTAT = TDES_ENH_TCH | TDES_ENH_CIC( 3 ) | TDES_ENH_FS | TDES_ENH_LS | TDES_ENH_IC; + xDMATxDescriptors[ x ].B2ADD = ( uint32_t ) &xDMATxDescriptors[ x + 1 ]; + } + + xDMATxDescriptors[ configNUM_TX_DESCRIPTORS - 1 ].CTRLSTAT |= TDES_ENH_TER; + xDMATxDescriptors[ configNUM_TX_DESCRIPTORS - 1 ].B2ADD = ( uint32_t ) &xDMATxDescriptors[ 0 ]; + + /* Point the DMA to the base of the descriptor list. */ + LPC_ETHERNET->DMA_TRANS_DES_ADDR = ( uint32_t ) xDMATxDescriptors; +} +/*-----------------------------------------------------------*/ + +static void prvSetupRxDescriptors( void ) +{ +BaseType_t x; +#if( ipconfigZERO_COPY_RX_DRIVER != 0 ) + NetworkBufferDescriptor_t *pxNetworkBuffer; +#endif + + /* Index to the next Rx descriptor to use. */ + ulNextRxDescriptorToProcess = 0; + + /* Clear RX descriptor list. */ + memset( ( void * ) xDMARxDescriptors, 0, sizeof( xDMARxDescriptors ) ); + + for( x = 0; x < configNUM_RX_DESCRIPTORS; x++ ) + { + /* Allocate a buffer of the largest possible frame size as it is not + known what size received frames will be. */ + + #if( ipconfigZERO_COPY_RX_DRIVER != 0 ) + { + pxNetworkBuffer = pxGetNetworkBufferWithDescriptor( ipTOTAL_ETHERNET_FRAME_SIZE, 0 ); + + /* During start-up there should be enough Network Buffers available, + so it is safe to use configASSERT(). + In case this assert fails, please check: configNUM_RX_DESCRIPTORS, + ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS, and in case BufferAllocation_2.c + is included, check the amount of available heap. */ + configASSERT( pxNetworkBuffer != NULL ); + + /* Pass the actual buffer to DMA. */ + xDMARxDescriptors[ x ].B1ADD = ( uint32_t ) pxNetworkBuffer->pucEthernetBuffer; + } + #else + { + /* All DMA descriptors are populated with permanent memory blocks. + Their contents will be copy to Network Buffers. */ + xDMARxDescriptors[ x ].B1ADD = ( uint32_t ) pvPortMalloc( ipTOTAL_ETHERNET_FRAME_SIZE ); + } + #endif /* ipconfigZERO_COPY_RX_DRIVER */ + + /* Use an assert to check the allocation as +TCP applications will often + not use a malloc failed hook as the TCP stack will recover from + allocation failures. */ + configASSERT( xDMARxDescriptors[ x ].B1ADD ); + + xDMARxDescriptors[ x ].B2ADD = ( uint32_t ) &( xDMARxDescriptors[ x + 1 ] ); + xDMARxDescriptors[ x ].CTRL = ( uint32_t ) RDES_ENH_BS1( ipTOTAL_ETHERNET_FRAME_SIZE ) | RDES_ENH_RCH; + + /* The descriptor is available for use by the DMA. */ + xDMARxDescriptors[ x ].STATUS = RDES_OWN; + } + + /* RDES_ENH_RER Receive End of Ring. */ + xDMARxDescriptors[ ( configNUM_RX_DESCRIPTORS - 1 ) ].CTRL |= RDES_ENH_RER; + xDMARxDescriptors[ configNUM_RX_DESCRIPTORS - 1 ].B2ADD = ( uint32_t ) &( xDMARxDescriptors[ 0 ] ); + + /* Point the DMA to the base of the descriptor list. */ + LPC_ETHERNET->DMA_REC_DES_ADDR = ( uint32_t ) xDMARxDescriptors; +} +/*-----------------------------------------------------------*/ +configPLACE_IN_SECTION_RAM +static void prvRemoveTrailingBytes( NetworkBufferDescriptor_t *pxDescriptor ) +{ +size_t xExpectedLength; +IPPacket_t *pxIPPacket; + + pxIPPacket = ( IPPacket_t * ) pxDescriptor->pucEthernetBuffer; + /* Look at the actual length of the packet, translate it to a host-endial notation. */ + xExpectedLength = sizeof( EthernetHeader_t ) + ( size_t ) FreeRTOS_htons( pxIPPacket->xIPHeader.usLength ); + + if( xExpectedLength == ( pxDescriptor->xDataLength + 4 ) ) + { + pxDescriptor->xDataLength -= 4; + } + else + { + if( pxDescriptor->xDataLength > xExpectedLength ) + { + pxDescriptor->xDataLength = ( size_t ) xExpectedLength; + } + } +} +/*-----------------------------------------------------------*/ +configPLACE_IN_SECTION_RAM +BaseType_t xGetPhyLinkStatus( void ) +{ +BaseType_t xReturn; + + if( ( ulPHYLinkStatus & PHY_LINK_CONNECTED ) == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +uint32_t ulDataAvailable; + +configPLACE_IN_SECTION_RAM +static BaseType_t prvNetworkInterfaceInput() +{ +BaseType_t xResult = pdFALSE; +uint32_t ulStatus; +eFrameProcessingResult_t eResult; +const TickType_t xDescriptorWaitTime = pdMS_TO_TICKS( 250 ); +const UBaseType_t uxMinimumBuffersRemaining = 3UL; +uint16_t usLength; +NetworkBufferDescriptor_t *pxDescriptor; +#if( ipconfigZERO_COPY_RX_DRIVER != 0 ) + NetworkBufferDescriptor_t *pxNewDescriptor; +#endif /* ipconfigZERO_COPY_RX_DRIVER */ +#if( ipconfigUSE_LINKED_RX_MESSAGES == 0 ) + IPStackEvent_t xRxEvent = { eNetworkRxEvent, NULL }; +#endif + + /* Process each descriptor that is not still in use by the DMA. */ + ulStatus = xDMARxDescriptors[ ulNextRxDescriptorToProcess ].STATUS; + if( ( ulStatus & RDES_OWN ) == 0 ) + { + /* Check packet for errors */ + if( ( ulStatus & nwRX_STATUS_ERROR_BITS ) != 0 ) + { + /* There is some reception error. */ + intCount[ 3 ]++; + /* Clear error bits. */ + ulStatus &= ~( ( uint32_t )nwRX_STATUS_ERROR_BITS ); + } + else + { + xResult++; + + eResult = ipCONSIDER_FRAME_FOR_PROCESSING( ( const uint8_t * const ) ( xDMARxDescriptors[ ulNextRxDescriptorToProcess ].B1ADD ) ); + if( eResult == eProcessBuffer ) + { + if( ( ulPHYLinkStatus & PHY_LINK_CONNECTED ) == 0 ) + { + ulPHYLinkStatus |= PHY_LINK_CONNECTED; + FreeRTOS_printf( ( "prvEMACHandlerTask: PHY LS now %d (message received)\n", ( ulPHYLinkStatus & PHY_LINK_CONNECTED ) != 0 ) ); + } + + #if( ipconfigZERO_COPY_RX_DRIVER != 0 ) + if( uxGetNumberOfFreeNetworkBuffers() > uxMinimumBuffersRemaining ) + { + pxNewDescriptor = pxGetNetworkBufferWithDescriptor( ipTOTAL_ETHERNET_FRAME_SIZE, xDescriptorWaitTime ); + } + else + { + /* Too risky to allocate a new Network Buffer. */ + pxNewDescriptor = NULL; + } + if( pxNewDescriptor != NULL ) + #else + if( uxGetNumberOfFreeNetworkBuffers() > uxMinimumBuffersRemaining ) + #endif /* ipconfigZERO_COPY_RX_DRIVER */ + { + #if( ipconfigZERO_COPY_RX_DRIVER != 0 ) + const uint8_t *pucBuffer; + #endif + + /* Get the actual length. */ + usLength = RDES_FLMSK( ulStatus ); + + #if( ipconfigZERO_COPY_RX_DRIVER != 0 ) + { + /* Replace the character buffer 'B1ADD'. */ + pucBuffer = ( const uint8_t * const ) ( xDMARxDescriptors[ ulNextRxDescriptorToProcess ].B1ADD ); + xDMARxDescriptors[ ulNextRxDescriptorToProcess ].B1ADD = ( uint32_t ) pxNewDescriptor->pucEthernetBuffer; + + /* 'B1ADD' contained the address of a 'pucEthernetBuffer' that + belongs to a Network Buffer. Find the original Network Buffer. */ + pxDescriptor = pxPacketBuffer_to_NetworkBuffer( pucBuffer ); + /* This zero-copy driver makes sure that every 'xDMARxDescriptors' contains + a reference to a Network Buffer at any time. + In case it runs out of Network Buffers, a DMA buffer won't be replaced, + and the received messages is dropped. */ + configASSERT( pxDescriptor != NULL ); + } + #else + { + /* Create a buffer of exactly the required length. */ + pxDescriptor = pxGetNetworkBufferWithDescriptor( usLength, xDescriptorWaitTime ); + } + #endif /* ipconfigZERO_COPY_RX_DRIVER */ + + if( pxDescriptor != NULL ) + { + pxDescriptor->xDataLength = ( size_t ) usLength; + #if( ipconfigZERO_COPY_RX_DRIVER == 0 ) + { + /* Copy the data into the allocated buffer. */ + memcpy( ( void * ) pxDescriptor->pucEthernetBuffer, ( void * ) xDMARxDescriptors[ ulNextRxDescriptorToProcess ].B1ADD, usLength ); + } + #endif /* ipconfigZERO_COPY_RX_DRIVER */ + /* It is possible that more data was copied than + actually makes up the frame. If this is the case + adjust the length to remove any trailing bytes. */ + prvRemoveTrailingBytes( pxDescriptor ); + + /* Pass the data to the TCP/IP task for processing. */ + xRxEvent.pvData = ( void * ) pxDescriptor; + if( xSendEventStructToIPTask( &xRxEvent, xDescriptorWaitTime ) == pdFALSE ) + { + /* Could not send the descriptor into the TCP/IP + stack, it must be released. */ + vReleaseNetworkBufferAndDescriptor( pxDescriptor ); + } + else + { + iptraceNETWORK_INTERFACE_RECEIVE(); + + /* The data that was available at the top of this + loop has been sent, so is no longer available. */ + ulDataAvailable = pdFALSE; + } + } + } + } + else + { + /* The packet is discarded as uninteresting. */ + ulDataAvailable = pdFALSE; + } + /* Got here because received data was sent to the IP task or the + data contained an error and was discarded. Give the descriptor + back to the DMA. */ + xDMARxDescriptors[ ulNextRxDescriptorToProcess ].STATUS = ulStatus | RDES_OWN; + + /* Move onto the next descriptor. */ + ulNextRxDescriptorToProcess++; + if( ulNextRxDescriptorToProcess >= configNUM_RX_DESCRIPTORS ) + { + ulNextRxDescriptorToProcess = 0; + } + + ulStatus = xDMARxDescriptors[ ulNextRxDescriptorToProcess ].STATUS; + } /* if( ( ulStatus & nwRX_STATUS_ERROR_BITS ) != 0 ) */ + } /* if( ( ulStatus & RDES_OWN ) == 0 ) */ + + /* Restart receive polling. */ + LPC_ETHERNET->DMA_REC_POLL_DEMAND = 1; + + return xResult; +} +/*-----------------------------------------------------------*/ + +configPLACE_IN_SECTION_RAM +void NETWORK_IRQHandler( void ) +{ +BaseType_t xHigherPriorityTaskWoken = pdFALSE; +uint32_t ulDMAStatus; +const uint32_t ulRxInterruptMask = + DMA_ST_RI | /* Receive interrupt */ + DMA_ST_RU; /* Receive buffer unavailable */ +const uint32_t ulTxInterruptMask = + DMA_ST_TI | /* Transmit interrupt */ + DMA_ST_TPS; /* Transmit process stopped */ + + configASSERT( xRxHanderTask ); + + /* Get pending interrupts. */ + ulDMAStatus = LPC_ETHERNET->DMA_STAT; + + /* RX group interrupt(s). */ + if( ( ulDMAStatus & ulRxInterruptMask ) != 0x00 ) + { + /* Remember that an RX event has happened. */ + ulISREvents |= EMAC_IF_RX_EVENT; + vTaskNotifyGiveFromISR( xRxHanderTask, &xHigherPriorityTaskWoken ); + intCount[ 0 ]++; + } + + /* TX group interrupt(s). */ + if( ( ulDMAStatus & ulTxInterruptMask ) != 0x00 ) + { + /* Remember that a TX event has happened. */ + ulISREvents |= EMAC_IF_TX_EVENT; + vTaskNotifyGiveFromISR( xRxHanderTask, &xHigherPriorityTaskWoken ); + intCount[ 1 ]++; + } + + /* Test for 'Abnormal interrupt summary'. */ + if( ( ulDMAStatus & DMA_ST_AIE ) != 0x00 ) + { + /* The trace macro must be written such that it can be called from + an interrupt. */ + iptraceETHERNET_RX_EVENT_LOST(); + } + + /* Clear pending interrupts */ + LPC_ETHERNET->DMA_STAT = ulDMAStatus; + + /* Context switch needed? */ + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvSetLinkSpeed( void ) +{ +BaseType_t xReturn = pdFAIL; +TickType_t xTimeOnEntering; +uint32_t ulPhyStatus; +const TickType_t xAutoNegotiateDelay = pdMS_TO_TICKS( 5000UL ); + + /* Ensure polling does not starve lower priority tasks by temporarily + setting the priority of this task to that of the idle task. */ + vTaskPrioritySet( NULL, tskIDLE_PRIORITY ); + + xTimeOnEntering = xTaskGetTickCount(); + do + { + ulPhyStatus = lpcPHYStsPoll(); + if( ( ulPhyStatus & PHY_LINK_CONNECTED ) != 0x00 ) + { + /* Set interface speed and duplex. */ + if( ( ulPhyStatus & PHY_LINK_SPEED100 ) != 0x00 ) + { + Chip_ENET_SetSpeed( LPC_ETHERNET, 1 ); + } + else + { + Chip_ENET_SetSpeed( LPC_ETHERNET, 0 ); + } + + if( ( ulPhyStatus & PHY_LINK_FULLDUPLX ) != 0x00 ) + { + Chip_ENET_SetDuplex( LPC_ETHERNET, true ); + } + else + { + Chip_ENET_SetDuplex( LPC_ETHERNET, false ); + } + + xReturn = pdPASS; + break; + } + } while( ( xTaskGetTickCount() - xTimeOnEntering ) < xAutoNegotiateDelay ); + + /* Reset the priority of this task back to its original value. */ + vTaskPrioritySet( NULL, ipconfigIP_TASK_PRIORITY ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static uint32_t prvGenerateCRC32( const uint8_t *ucAddress ) +{ +unsigned int j; +const uint32_t Polynomial = 0xEDB88320; +uint32_t crc = ~0ul; +const uint8_t *pucCurrent = ( const uint8_t * ) ucAddress; +const uint8_t *pucLast = pucCurrent + 6; + + /* Calculate normal CRC32 */ + while( pucCurrent < pucLast ) + { + crc ^= *( pucCurrent++ ); + for( j = 0; j < 8; j++ ) + { + if( ( crc & 1 ) != 0 ) + { + crc = (crc >> 1) ^ Polynomial; + } + else + { + crc >>= 1; + } + } + } + return ~crc; +} +/*-----------------------------------------------------------*/ + +static uint32_t prvGetHashIndex( const uint8_t *ucAddress ) +{ +uint32_t ulCrc = prvGenerateCRC32( ucAddress ); +uint32_t ulIndex = 0ul; +BaseType_t xCount = 6; + + /* Take the lowest 6 bits of the CRC32 and reverse them */ + while( xCount-- ) + { + ulIndex <<= 1; + ulIndex |= ( ulCrc & 1 ); + ulCrc >>= 1; + } + + /* This is the has value of 'ucAddress' */ + return ulIndex; +} +/*-----------------------------------------------------------*/ + +static void prvAddMACAddress( const uint8_t* ucMacAddress ) +{ +BaseType_t xIndex; + + xIndex = prvGetHashIndex( ucMacAddress ); + if( xIndex >= 32 ) + { + LPC_ETHERNET->MAC_HASHTABLE_HIGH |= ( 1u << ( xIndex - 32 ) ); + } + else + { + LPC_ETHERNET->MAC_HASHTABLE_LOW |= ( 1u << xIndex ); + } +} +/*-----------------------------------------------------------*/ + +configPLACE_IN_SECTION_RAM +static void prvEMACHandlerTask( void *pvParameters ) +{ +TimeOut_t xPhyTime; +TickType_t xPhyRemTime; +UBaseType_t uxLastMinBufferCount = 0; +UBaseType_t uxCurrentCount; +BaseType_t xResult = 0; +uint32_t ulStatus; +const TickType_t xBlockTime = pdMS_TO_TICKS( 5000ul ); + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + /* A possibility to set some additional task properties. */ + iptraceEMAC_TASK_STARTING(); + + vTaskSetTimeOutState( &xPhyTime ); + xPhyRemTime = pdMS_TO_TICKS( PHY_LS_LOW_CHECK_TIME_MS ); + + for( ;; ) + { + uxCurrentCount = uxGetMinimumFreeNetworkBuffers(); + if( uxLastMinBufferCount != uxCurrentCount ) + { + /* The logging produced below may be helpful + while tuning +TCP: see how many buffers are in use. */ + uxLastMinBufferCount = uxCurrentCount; + FreeRTOS_printf( ( "Network buffers: %lu lowest %lu\n", + uxGetNumberOfFreeNetworkBuffers(), uxCurrentCount ) ); + } + + #if( ipconfigCHECK_IP_QUEUE_SPACE != 0 ) + { + static UBaseType_t uxLastMinQueueSpace = 0; + + uxCurrentCount = uxGetMinimumIPQueueSpace(); + if( uxLastMinQueueSpace != uxCurrentCount ) + { + /* The logging produced below may be helpful + while tuning +TCP: see how many buffers are in use. */ + uxLastMinQueueSpace = uxCurrentCount; + FreeRTOS_printf( ( "Queue space: lowest %lu\n", uxCurrentCount ) ); + } + } + #endif /* ipconfigCHECK_IP_QUEUE_SPACE */ + + ulTaskNotifyTake( pdTRUE, xBlockTime ); + + xResult = ( BaseType_t ) 0; + + if( ( ulISREvents & EMAC_IF_TX_EVENT ) != 0 ) + { + /* Code to release TX buffers if zero-copy is used. */ + ulISREvents &= ~EMAC_IF_TX_EVENT; + { + /* Check if DMA packets have been delivered. */ + vClearTXBuffers(); + } + } + + if( ( ulISREvents & EMAC_IF_RX_EVENT ) != 0 ) + { + ulISREvents &= ~EMAC_IF_RX_EVENT; + + xResult = prvNetworkInterfaceInput(); + if( xResult > 0 ) + { + while( prvNetworkInterfaceInput() > 0 ) + { + } + } + } + + if( xResult > 0 ) + { + /* A packet was received. No need to check for the PHY status now, + but set a timer to check it later on. */ + vTaskSetTimeOutState( &xPhyTime ); + xPhyRemTime = pdMS_TO_TICKS( PHY_LS_HIGH_CHECK_TIME_MS ); + xResult = 0; + } + else if( xTaskCheckForTimeOut( &xPhyTime, &xPhyRemTime ) != pdFALSE ) + { + ulStatus = lpcPHYStsPoll(); + + if( ( ulPHYLinkStatus & PHY_LINK_CONNECTED ) != ( ulStatus & PHY_LINK_CONNECTED ) ) + { + ulPHYLinkStatus = ulStatus; + FreeRTOS_printf( ( "prvEMACHandlerTask: PHY LS now %d (polled PHY)\n", ( ulPHYLinkStatus & PHY_LINK_CONNECTED ) != 0 ) ); + } + + vTaskSetTimeOutState( &xPhyTime ); + if( ( ulPHYLinkStatus & PHY_LINK_CONNECTED ) != 0 ) + { + xPhyRemTime = pdMS_TO_TICKS( PHY_LS_HIGH_CHECK_TIME_MS ); + } + else + { + xPhyRemTime = pdMS_TO_TICKS( PHY_LS_LOW_CHECK_TIME_MS ); + } + } + } +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/LPC18xx/ReadMe.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/LPC18xx/ReadMe.txt new file mode 100644 index 0000000..86a7f91 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/LPC18xx/ReadMe.txt @@ -0,0 +1,3 @@ +NetworkInterface.c: +Requires NXP's LPCOpen library and was developed on an LPC1830 and LPC1835 Xplorer +boards from NGX. \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/README_DRIVER_DISCLAIMER.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/README_DRIVER_DISCLAIMER.txt new file mode 100644 index 0000000..347bb11 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/README_DRIVER_DISCLAIMER.txt @@ -0,0 +1,10 @@ +Network drivers are provided as examples only, and do not form part of the +FreeRTOS+TCP stack itself. They: + + + May be based on driver code provided by the chip vendors, + + May not have been tested in all possible configurations, + + Will not necessarily be optimised. + + May have a dependency on a particular PHY part number. + + May not necessarily comply with any particular coding standard. + + May have dependencies on chip company libraries. + + May include other hardware board dependencies. diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/SH2A/NetworkInterface.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/SH2A/NetworkInterface.c new file mode 100644 index 0000000..44d19f3 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/SH2A/NetworkInterface.c @@ -0,0 +1,118 @@ +/* +FreeRTOS+TCP V2.0.11 +Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + http://aws.amazon.com/freertos + http://www.FreeRTOS.org +*/ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_UDP_IP.h" +#include "FreeRTOS_Sockets.h" +#include "NetworkBufferManagement.h" + +/* Hardware includes. */ +#include "hwEthernet.h" + +/* Demo includes. */ +#include "NetworkInterface.h" + +#if ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES != 1 + #define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eProcessBuffer +#else + #define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eConsiderFrameForProcessing( ( pucEthernetBuffer ) ) +#endif + +/* When a packet is ready to be sent, if it cannot be sent immediately then the +task performing the transmit will block for niTX_BUFFER_FREE_WAIT +milliseconds. It will do this a maximum of niMAX_TX_ATTEMPTS before giving +up. */ +#define niTX_BUFFER_FREE_WAIT ( ( TickType_t ) 2UL / portTICK_PERIOD_MS ) +#define niMAX_TX_ATTEMPTS ( 5 ) + +/* The length of the queue used to send interrupt status words from the +interrupt handler to the deferred handler task. */ +#define niINTERRUPT_QUEUE_LENGTH ( 10 ) + +/*-----------------------------------------------------------*/ + +/* + * A deferred interrupt handler task that processes + */ +extern void vEMACHandlerTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used to communicate Ethernet events with the IP task. */ +extern QueueHandle_t xNetworkEventQueue; + +/* The semaphore used to wake the deferred interrupt handler task when an Rx +interrupt is received. */ +SemaphoreHandle_t xEMACRxEventSemaphore = NULL; +/*-----------------------------------------------------------*/ + +BaseType_t xNetworkInterfaceInitialise( void ) +{ +BaseType_t xStatus, xReturn; +extern uint8_t ucMACAddress[ 6 ]; + + /* Initialise the MAC. */ + vInitEmac(); + + while( lEMACWaitForLink() != pdPASS ) + { + vTaskDelay( 20 ); + } + + vSemaphoreCreateBinary( xEMACRxEventSemaphore ); + configASSERT( xEMACRxEventSemaphore ); + + /* The handler task is created at the highest possible priority to + ensure the interrupt handler can return directly to it. */ + xTaskCreate( vEMACHandlerTask, "EMAC", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); + xReturn = pdPASS; + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xNetworkInterfaceOutput( NetworkBufferDescriptor_t * const pxNetworkBuffer ) +{ +extern void vEMACCopyWrite( uint8_t * pucBuffer, uint16_t usLength ); + + vEMACCopyWrite( pxNetworkBuffer->pucBuffer, pxNetworkBuffer->xDataLength ); + + /* Finished with the network buffer. */ + vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ); + + return pdTRUE; +} +/*-----------------------------------------------------------*/ + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32F7xx/NetworkInterface.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32F7xx/NetworkInterface.c new file mode 100644 index 0000000..7de2902 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32F7xx/NetworkInterface.c @@ -0,0 +1,1193 @@ +/* + * Some constants, hardware definitions and comments taken from ST's HAL driver + * library, COPYRIGHT(c) 2015 STMicroelectronics. + */ + +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Standard includes. */ +#include +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_IP_Private.h" +#include "FreeRTOS_DNS.h" +#include "NetworkBufferManagement.h" +#include "NetworkInterface.h" + +#include "phyHandling.h" + +/* ST includes. */ +#ifdef STM32F7xx + #include "stm32f7xx_hal.h" +#else + #include "stm32f4xx_hal.h" +#endif + +/* Interrupt events to process. Currently only the Rx event is processed +although code for other events is included to allow for possible future +expansion. */ +#define EMAC_IF_RX_EVENT 1UL +#define EMAC_IF_TX_EVENT 2UL +#define EMAC_IF_ERR_EVENT 4UL +#define EMAC_IF_ALL_EVENT ( EMAC_IF_RX_EVENT | EMAC_IF_TX_EVENT | EMAC_IF_ERR_EVENT ) + +#define ETH_DMA_ALL_INTS \ + ( ETH_DMA_IT_TST | ETH_DMA_IT_PMT | ETH_DMA_IT_MMC | ETH_DMA_IT_NIS | ETH_DMA_IT_ER | \ + ETH_DMA_IT_FBE | ETH_DMA_IT_RWT | ETH_DMA_IT_RPS | ETH_DMA_IT_RBU | ETH_DMA_IT_R | \ + ETH_DMA_IT_TU | ETH_DMA_IT_RO | ETH_DMA_IT_TJT | ETH_DMA_IT_TPS | ETH_DMA_IT_T ) + + + +#define ipFRAGMENT_OFFSET_BIT_MASK ( ( uint16_t ) 0x0fff ) /* The bits in the two byte IP header field that make up the fragment offset value. */ + +/* + * Most users will want a PHY that negotiates about + * the connection properties: speed, dmix and duplex. + * On some rare cases, you want to select what is being + * advertised, properties like MDIX and duplex. + */ + +#if !defined( ipconfigETHERNET_AN_ENABLE ) + /* Enable auto-negotiation */ + #define ipconfigETHERNET_AN_ENABLE 1 +#endif + +#if !defined( ipconfigETHERNET_AUTO_CROSS_ENABLE ) + #define ipconfigETHERNET_AUTO_CROSS_ENABLE 1 +#endif + +#if( ipconfigETHERNET_AN_ENABLE == 0 ) + /* + * The following three defines are only used in case there + * is no auto-negotiation. + */ + #if !defined( ipconfigETHERNET_CROSSED_LINK ) + #define ipconfigETHERNET_CROSSED_LINK 1 + #endif + + #if !defined( ipconfigETHERNET_USE_100MB ) + #define ipconfigETHERNET_USE_100MB 1 + #endif + + #if !defined( ipconfigETHERNET_USE_FULL_DUPLEX ) + #define ipconfigETHERNET_USE_FULL_DUPLEX 1 + #endif +#endif /* ipconfigETHERNET_AN_ENABLE == 0 */ + +/* Default the size of the stack used by the EMAC deferred handler task to twice +the size of the stack used by the idle task - but allow this to be overridden in +FreeRTOSConfig.h as configMINIMAL_STACK_SIZE is a user definable constant. */ +#ifndef configEMAC_TASK_STACK_SIZE + #define configEMAC_TASK_STACK_SIZE ( 2 * configMINIMAL_STACK_SIZE ) +#endif + +/* Two choices must be made: RMII versus MII, +and the index of the PHY in use ( between 0 and 31 ). */ +#ifndef ipconfigUSE_RMII + #ifdef STM32F7xx + #define ipconfigUSE_RMII 1 + #else + #define ipconfigUSE_RMII 0 + #endif /* STM32F7xx */ +#endif /* ipconfigUSE_RMII */ + +#ifndef ipconfigPHY_INDEX + #ifdef STM32F7xx + #define ipconfigPHY_INDEX 0 + #else + #define ipconfigPHY_INDEX 1 + #endif /* STM32F7xx */ +#endif /* ipconfigPHY_INDEX */ + + +/*-----------------------------------------------------------*/ + +/* + * A deferred interrupt handler task that processes + */ +static void prvEMACHandlerTask( void *pvParameters ); + +/* + * Force a negotiation with the Switch or Router and wait for LS. + */ +static void prvEthernetUpdateConfig( BaseType_t xForce ); + +/* + * See if there is a new packet and forward it to the IP-task. + */ +static BaseType_t prvNetworkInterfaceInput( void ); + +#if( ipconfigUSE_LLMNR != 0 ) + /* + * For LLMNR, an extra MAC-address must be configured to + * be able to receive the multicast messages. + */ + static void prvMACAddressConfig(ETH_HandleTypeDef *heth, uint32_t ulIndex, uint8_t *Addr); +#endif + +/* + * Check if a given packet should be accepted. + */ +static BaseType_t xMayAcceptPacket( uint8_t *pcBuffer ); + +/* + * Initialise the TX descriptors. + */ +static void prvDMATxDescListInit( void ); + +/* + * Initialise the RX descriptors. + */ +static void prvDMARxDescListInit( void ); + +/* After packets have been sent, the network +buffers will be released. */ +static void vClearTXBuffers( void ); + +/*-----------------------------------------------------------*/ + +/* Bit map of outstanding ETH interrupt events for processing. Currently only +the Rx interrupt is handled, although code is included for other events to +enable future expansion. */ +static volatile uint32_t ulISREvents; + +#if( ipconfigUSE_LLMNR == 1 ) + static const uint8_t xLLMNR_MACAddress[] = { 0x01, 0x00, 0x5E, 0x00, 0x00, 0xFC }; +#endif + +static EthernetPhy_t xPhyObject; + +/* Ethernet handle. */ +static ETH_HandleTypeDef xETH; + +/* xTXDescriptorSemaphore is a counting semaphore with +a maximum count of ETH_TXBUFNB, which is the number of +DMA TX descriptors. */ +static SemaphoreHandle_t xTXDescriptorSemaphore = NULL; + +/* + * Note: it is adviced to define both + * + * #define ipconfigZERO_COPY_RX_DRIVER 1 + * #define ipconfigZERO_COPY_TX_DRIVER 1 + * + * The method using memcpy is slower and probaly uses more RAM memory. + * The possibility is left in the code just for comparison. + * + * It is adviced to define ETH_TXBUFNB at least 4. Note that no + * TX buffers are allocated in a zero-copy driver. + */ +/* MAC buffers: ---------------------------------------------------------*/ + +/* Put the DMA descriptors in '.first_data'. +This is important for STM32F7, which has an L1 data cache. +The first 64KB of the SRAM is not cached. */ + +/* Ethernet Rx MA Descriptor */ +__attribute__ ((aligned (32))) +__attribute__ ((section(".first_data"))) + ETH_DMADescTypeDef DMARxDscrTab[ ETH_RXBUFNB ]; + +#if( ipconfigZERO_COPY_RX_DRIVER == 0 ) + /* Ethernet Receive Buffer */ + __ALIGN_BEGIN uint8_t Rx_Buff[ ETH_RXBUFNB ][ ETH_RX_BUF_SIZE ] __ALIGN_END; +#endif + +/* Ethernet Tx DMA Descriptor */ +__attribute__ ((aligned (32))) +__attribute__ ((section(".first_data"))) + ETH_DMADescTypeDef DMATxDscrTab[ ETH_TXBUFNB ]; + +#if( ipconfigZERO_COPY_TX_DRIVER == 0 ) + /* Ethernet Transmit Buffer */ + __ALIGN_BEGIN uint8_t Tx_Buff[ ETH_TXBUFNB ][ ETH_TX_BUF_SIZE ] __ALIGN_END; +#endif + +#if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + /* DMATxDescToClear points to the next TX DMA descriptor + that must be cleared by vClearTXBuffers(). */ + static __IO ETH_DMADescTypeDef *DMATxDescToClear; +#endif + +/* ucMACAddress as it appears in main.c */ +extern const uint8_t ucMACAddress[ 6 ]; + +/* Holds the handle of the task used as a deferred interrupt processor. The +handle is used so direct notifications can be sent to the task for all EMAC/DMA +related interrupts. */ +static TaskHandle_t xEMACTaskHandle = NULL; + +/* For local use only: describe the PHY's properties: */ +const PhyProperties_t xPHYProperties = +{ + #if( ipconfigETHERNET_AN_ENABLE != 0 ) + .ucSpeed = PHY_SPEED_AUTO, + .ucDuplex = PHY_DUPLEX_AUTO, + #else + #if( ipconfigETHERNET_USE_100MB != 0 ) + .ucSpeed = PHY_SPEED_100, + #else + .ucSpeed = PHY_SPEED_10, + #endif + + #if( ipconfigETHERNET_USE_FULL_DUPLEX != 0 ) + .duplex = PHY_DUPLEX_FULL, + #else + .duplex = PHY_DUPLEX_HALF, + #endif + #endif + + #if( ipconfigETHERNET_AN_ENABLE != 0 ) && ( ipconfigETHERNET_AUTO_CROSS_ENABLE != 0 ) + .ucMDI_X = PHY_MDIX_AUTO, + #elif( ipconfigETHERNET_CROSSED_LINK != 0 ) + .ucMDI_X = PHY_MDIX_CROSSED, + #else + .ucMDI_X = PHY_MDIX_DIRECT, + #endif +}; + +/*-----------------------------------------------------------*/ + +void HAL_ETH_RxCpltCallback( ETH_HandleTypeDef *heth ) +{ +BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + /* Ethernet RX-Complete callback function, elsewhere declared as weak. */ + ulISREvents |= EMAC_IF_RX_EVENT; + /* Wakeup the prvEMACHandlerTask. */ + if( xEMACTaskHandle != NULL ) + { + vTaskNotifyGiveFromISR( xEMACTaskHandle, &xHigherPriorityTaskWoken ); + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + } +} +/*-----------------------------------------------------------*/ + +void HAL_ETH_TxCpltCallback( ETH_HandleTypeDef *heth ) +{ +BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + /* This call-back is only useful in case packets are being sent + zero-copy. Once they're sent, the buffers will be released + by the function vClearTXBuffers(). */ + ulISREvents |= EMAC_IF_TX_EVENT; + /* Wakeup the prvEMACHandlerTask. */ + if( xEMACTaskHandle != NULL ) + { + vTaskNotifyGiveFromISR( xEMACTaskHandle, &xHigherPriorityTaskWoken ); + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + } + +} +/*-----------------------------------------------------------*/ + +static void vClearTXBuffers() +{ +__IO ETH_DMADescTypeDef *txLastDescriptor = xETH.TxDesc; +size_t uxCount = ( ( UBaseType_t ) ETH_TXBUFNB ) - uxSemaphoreGetCount( xTXDescriptorSemaphore ); +#if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + NetworkBufferDescriptor_t *pxNetworkBuffer; + uint8_t *ucPayLoad; +#endif + + /* This function is called after a TX-completion interrupt. + It will release each Network Buffer used in xNetworkInterfaceOutput(). + 'uxCount' represents the number of descriptors given to DMA for transmission. + After sending a packet, the DMA will clear the 'ETH_DMATXDESC_OWN' bit. */ + while( ( uxCount > 0 ) && ( ( DMATxDescToClear->Status & ETH_DMATXDESC_OWN ) == 0 ) ) + { + if( ( DMATxDescToClear == txLastDescriptor ) && ( uxCount != ETH_TXBUFNB ) ) + { + break; + } + #if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + { + ucPayLoad = ( uint8_t * )DMATxDescToClear->Buffer1Addr; + + if( ucPayLoad != NULL ) + { + pxNetworkBuffer = pxPacketBuffer_to_NetworkBuffer( ucPayLoad ); + if( pxNetworkBuffer != NULL ) + { + vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ) ; + } + DMATxDescToClear->Buffer1Addr = ( uint32_t )0u; + } + } + #endif /* ipconfigZERO_COPY_TX_DRIVER */ + + DMATxDescToClear = ( ETH_DMADescTypeDef * )( DMATxDescToClear->Buffer2NextDescAddr ); + + uxCount--; + /* Tell the counting semaphore that one more TX descriptor is available. */ + xSemaphoreGive( xTXDescriptorSemaphore ); + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xNetworkInterfaceInitialise( void ) +{ +HAL_StatusTypeDef hal_eth_init_status; +BaseType_t xResult; + + if( xEMACTaskHandle == NULL ) + { + if( xTXDescriptorSemaphore == NULL ) + { + xTXDescriptorSemaphore = xSemaphoreCreateCounting( ( UBaseType_t ) ETH_TXBUFNB, ( UBaseType_t ) ETH_TXBUFNB ); + configASSERT( xTXDescriptorSemaphore ); + } + + /* Initialise ETH */ + + xETH.Instance = ETH; +//#warning Enable auto-nego again + xETH.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE; +// xETH.Init.AutoNegotiation = ETH_AUTONEGOTIATION_DISABLE; + xETH.Init.Speed = ETH_SPEED_100M; + xETH.Init.DuplexMode = ETH_MODE_FULLDUPLEX; + xETH.Init.PhyAddress = ipconfigPHY_INDEX; + + xETH.Init.MACAddr = ( uint8_t *) ucMACAddress; + xETH.Init.RxMode = ETH_RXINTERRUPT_MODE; + + /* using the ETH_CHECKSUM_BY_HARDWARE option: + both the IP and the protocol checksums will be calculated + by the peripheral. */ + xETH.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE; + + #if( ipconfigUSE_RMII != 0 ) + { + xETH.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII; + } + #else + { + xETH.Init.MediaInterface = ETH_MEDIA_INTERFACE_MII; + } + #endif /* ipconfigUSE_RMII */ + + hal_eth_init_status = HAL_ETH_Init( &xETH ); + + /* Only for inspection by debugger. */ + ( void ) hal_eth_init_status; + + /* Set the TxDesc and RxDesc pointers. */ + xETH.TxDesc = DMATxDscrTab; + xETH.RxDesc = DMARxDscrTab; + + /* Make sure that all unused fields are cleared. */ + memset( &DMATxDscrTab, '\0', sizeof( DMATxDscrTab ) ); + memset( &DMARxDscrTab, '\0', sizeof( DMARxDscrTab ) ); + + /* Initialize Tx Descriptors list: Chain Mode */ + DMATxDescToClear = DMATxDscrTab; + + /* Initialise TX-descriptors. */ + prvDMATxDescListInit(); + + /* Initialise RX-descriptors. */ + prvDMARxDescListInit(); + + #if( ipconfigUSE_LLMNR != 0 ) + { + /* Program the LLMNR address at index 1. */ + prvMACAddressConfig( &xETH, ETH_MAC_ADDRESS1, ( uint8_t *) xLLMNR_MACAddress ); + } + #endif + + /* Force a negotiation with the Switch or Router and wait for LS. */ + prvEthernetUpdateConfig( pdTRUE ); + + /* The deferred interrupt handler task is created at the highest + possible priority to ensure the interrupt handler can return directly + to it. The task's handle is stored in xEMACTaskHandle so interrupts can + notify the task when there is something to process. */ + xTaskCreate( prvEMACHandlerTask, "EMAC", configEMAC_TASK_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, &xEMACTaskHandle ); + } /* if( xEMACTaskHandle == NULL ) */ + + if( xPhyObject.ulLinkStatusMask != 0 ) + { + xETH.Instance->DMAIER |= ETH_DMA_ALL_INTS; + xResult = pdPASS; + FreeRTOS_printf( ( "Link Status is high\n" ) ) ; + } + else + { + /* For now pdFAIL will be returned. But prvEMACHandlerTask() is running + and it will keep on checking the PHY and set 'ulLinkStatusMask' when necessary. */ + xResult = pdFAIL; + FreeRTOS_printf( ( "Link Status still low\n" ) ) ; + } + /* When returning non-zero, the stack will become active and + start DHCP (in configured) */ + return xResult; +} +/*-----------------------------------------------------------*/ + +static void prvDMATxDescListInit() +{ +ETH_DMADescTypeDef *pxDMADescriptor; +BaseType_t xIndex; + + /* Get the pointer on the first member of the descriptor list */ + pxDMADescriptor = DMATxDscrTab; + + /* Fill each DMA descriptor with the right values */ + for( xIndex = 0; xIndex < ETH_TXBUFNB; xIndex++, pxDMADescriptor++ ) + { + /* Set Second Address Chained bit */ + pxDMADescriptor->Status = ETH_DMATXDESC_TCH; + + #if( ipconfigZERO_COPY_TX_DRIVER == 0 ) + { + /* Set Buffer1 address pointer */ + pxDMADescriptor->Buffer1Addr = ( uint32_t )( Tx_Buff[ xIndex ] ); + } + #endif + + if( xETH.Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE ) + { + /* Set the DMA Tx descriptors checksum insertion for TCP, UDP, and ICMP */ + pxDMADescriptor->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL; + } + + /* Initialize the next descriptor with the Next Descriptor Polling Enable */ + if( xIndex < ETH_TXBUFNB - 1 ) + { + /* Set next descriptor address register with next descriptor base address */ + pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) ( pxDMADescriptor + 1 ); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) DMATxDscrTab; + } + } + + /* Set Transmit Descriptor List Address Register */ + xETH.Instance->DMATDLAR = ( uint32_t ) DMATxDscrTab; +} +/*-----------------------------------------------------------*/ + +static void prvDMARxDescListInit() +{ +ETH_DMADescTypeDef *pxDMADescriptor; +BaseType_t xIndex; + /* + * RX-descriptors. + */ + + /* Get the pointer on the first member of the descriptor list */ + pxDMADescriptor = DMARxDscrTab; + + /* Fill each DMA descriptor with the right values */ + for( xIndex = 0; xIndex < ETH_RXBUFNB; xIndex++, pxDMADescriptor++ ) + { + + /* Set Buffer1 size and Second Address Chained bit */ + pxDMADescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | (uint32_t)ETH_RX_BUF_SIZE; + + #if( ipconfigZERO_COPY_RX_DRIVER != 0 ) + { + /* Set Buffer1 address pointer */ + NetworkBufferDescriptor_t *pxBuffer; + + pxBuffer = pxGetNetworkBufferWithDescriptor( ETH_RX_BUF_SIZE, 100ul ); + /* If the assert below fails, make sure that there are at least 'ETH_RXBUFNB' + Network Buffers available during start-up ( ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ) */ + configASSERT( pxBuffer != NULL ); + if( pxBuffer != NULL ) + { + pxDMADescriptor->Buffer1Addr = (uint32_t)pxBuffer->pucEthernetBuffer; + pxDMADescriptor->Status = ETH_DMARXDESC_OWN; + } + } + #else + { + /* Set Buffer1 address pointer */ + pxDMADescriptor->Buffer1Addr = ( uint32_t )( Rx_Buff[ xIndex ] ); + /* Set Own bit of the Rx descriptor Status */ + pxDMADescriptor->Status = ETH_DMARXDESC_OWN; + } + #endif + + /* Initialize the next descriptor with the Next Descriptor Polling Enable */ + if( xIndex < ETH_RXBUFNB - 1 ) + { + /* Set next descriptor address register with next descriptor base address */ + pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t )( pxDMADescriptor + 1 ); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) DMARxDscrTab; + } + + } + /* Set Receive Descriptor List Address Register */ + xETH.Instance->DMARDLAR = ( uint32_t ) DMARxDscrTab; +} +/*-----------------------------------------------------------*/ + +static void prvMACAddressConfig(ETH_HandleTypeDef *heth, uint32_t ulIndex, uint8_t *Addr) +{ +uint32_t ulTempReg; + + /* Calculate the selected MAC address high register. */ + ulTempReg = 0x80000000ul | ( ( uint32_t ) Addr[ 5 ] << 8 ) | ( uint32_t ) Addr[ 4 ]; + + /* Load the selected MAC address high register. */ + ( *(__IO uint32_t *)( ( uint32_t ) ( ETH_MAC_ADDR_HBASE + ulIndex ) ) ) = ulTempReg; + + /* Calculate the selected MAC address low register. */ + ulTempReg = ( ( uint32_t ) Addr[ 3 ] << 24 ) | ( ( uint32_t ) Addr[ 2 ] << 16 ) | ( ( uint32_t ) Addr[ 1 ] << 8 ) | Addr[ 0 ]; + + /* Load the selected MAC address low register */ + ( *(__IO uint32_t *) ( ( uint32_t ) ( ETH_MAC_ADDR_LBASE + ulIndex ) ) ) = ulTempReg; +} +/*-----------------------------------------------------------*/ + +BaseType_t xNetworkInterfaceOutput( NetworkBufferDescriptor_t * const pxDescriptor, BaseType_t bReleaseAfterSend ) +{ +BaseType_t xReturn = pdFAIL; +uint32_t ulTransmitSize = 0; +__IO ETH_DMADescTypeDef *pxDmaTxDesc; +/* Do not wait too long for a free TX DMA buffer. */ +const TickType_t xBlockTimeTicks = pdMS_TO_TICKS( 50u ); + + #if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM != 0 ) + { + ProtocolPacket_t *pxPacket; + + #if( ipconfigZERO_COPY_RX_DRIVER != 0 ) + { + configASSERT( bReleaseAfterSend != 0 ); + } + #endif /* ipconfigZERO_COPY_RX_DRIVER */ + + /* If the peripheral must calculate the checksum, it wants + the protocol checksum to have a value of zero. */ + pxPacket = ( ProtocolPacket_t * ) ( pxDescriptor->pucEthernetBuffer ); + + if( pxPacket->xICMPPacket.xIPHeader.ucProtocol == ipPROTOCOL_ICMP ) + { + pxPacket->xICMPPacket.xICMPHeader.usChecksum = ( uint16_t )0u; + } + } + #endif + + /* Open a do {} while ( 0 ) loop to be able to call break. */ + do + { + if( xPhyObject.ulLinkStatusMask != 0 ) + { + if( xSemaphoreTake( xTXDescriptorSemaphore, xBlockTimeTicks ) != pdPASS ) + { + /* Time-out waiting for a free TX descriptor. */ + break; + } + + /* This function does the actual transmission of the packet. The packet is + contained in 'pxDescriptor' that is passed to the function. */ + pxDmaTxDesc = xETH.TxDesc; + + /* Is this buffer available? */ + configASSERT ( ( pxDmaTxDesc->Status & ETH_DMATXDESC_OWN ) == 0 ); + + { + /* Is this buffer available? */ + /* Get bytes in current buffer. */ + ulTransmitSize = pxDescriptor->xDataLength; + + if( ulTransmitSize > ETH_TX_BUF_SIZE ) + { + ulTransmitSize = ETH_TX_BUF_SIZE; + } + + #if( ipconfigZERO_COPY_TX_DRIVER == 0 ) + { + /* Copy the bytes. */ + memcpy( ( void * ) pxDmaTxDesc->Buffer1Addr, pxDescriptor->pucEthernetBuffer, ulTransmitSize ); + } + #else + { + /* Move the buffer. */ + pxDmaTxDesc->Buffer1Addr = ( uint32_t )pxDescriptor->pucEthernetBuffer; + /* The Network Buffer has been passed to DMA, no need to release it. */ + bReleaseAfterSend = pdFALSE_UNSIGNED; + } + #endif /* ipconfigZERO_COPY_TX_DRIVER */ + + /* Ask to set the IPv4 checksum. + Also need an Interrupt on Completion so that 'vClearTXBuffers()' will be called.. */ + pxDmaTxDesc->Status |= ETH_DMATXDESC_CIC_TCPUDPICMP_FULL | ETH_DMATXDESC_IC; + + /* Prepare transmit descriptors to give to DMA. */ + + /* Set LAST and FIRST segment */ + pxDmaTxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS; + /* Set frame size */ + pxDmaTxDesc->ControlBufferSize = ( ulTransmitSize & ETH_DMATXDESC_TBS1 ); + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + pxDmaTxDesc->Status |= ETH_DMATXDESC_OWN; + + /* Point to next descriptor */ + xETH.TxDesc = ( ETH_DMADescTypeDef * ) ( xETH.TxDesc->Buffer2NextDescAddr ); + /* Ensure completion of memory access */ + __DSB(); + /* Resume DMA transmission*/ + xETH.Instance->DMATPDR = 0; + iptraceNETWORK_INTERFACE_TRANSMIT(); + xReturn = pdPASS; + } + } + else + { + /* The PHY has no Link Status, packet shall be dropped. */ + } + } while( 0 ); + /* The buffer has been sent so can be released. */ + if( bReleaseAfterSend != pdFALSE ) + { + vReleaseNetworkBufferAndDescriptor( pxDescriptor ); + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static BaseType_t xMayAcceptPacket( uint8_t *pcBuffer ) +{ +const ProtocolPacket_t *pxProtPacket = ( const ProtocolPacket_t * )pcBuffer; + + switch( pxProtPacket->xTCPPacket.xEthernetHeader.usFrameType ) + { + case ipARP_FRAME_TYPE: + /* Check it later. */ + return pdTRUE; + case ipIPv4_FRAME_TYPE: + /* Check it here. */ + break; + default: + /* Refuse the packet. */ + return pdFALSE; + } + + #if( ipconfigETHERNET_DRIVER_FILTERS_PACKETS == 1 ) + { + const IPHeader_t *pxIPHeader = &(pxProtPacket->xTCPPacket.xIPHeader); + uint32_t ulDestinationIPAddress; + + /* Ensure that the incoming packet is not fragmented (only outgoing packets + * can be fragmented) as these are the only handled IP frames currently. */ + if( ( pxIPHeader->usFragmentOffset & FreeRTOS_ntohs( ipFRAGMENT_OFFSET_BIT_MASK ) ) != 0U ) + { + return pdFALSE; + } + /* HT: Might want to make the following configurable because + * most IP messages have a standard length of 20 bytes */ + + /* 0x45 means: IPv4 with an IP header of 5 x 4 = 20 bytes + * 0x47 means: IPv4 with an IP header of 7 x 4 = 28 bytes */ + if( pxIPHeader->ucVersionHeaderLength < 0x45 || pxIPHeader->ucVersionHeaderLength > 0x4F ) + { + return pdFALSE; + } + + ulDestinationIPAddress = pxIPHeader->ulDestinationIPAddress; + /* Is the packet for this node? */ + if( ( ulDestinationIPAddress != *ipLOCAL_IP_ADDRESS_POINTER ) && + /* Is it a broadcast address x.x.x.255 ? */ + ( ( FreeRTOS_ntohl( ulDestinationIPAddress ) & 0xff ) != 0xff ) && + #if( ipconfigUSE_LLMNR == 1 ) + ( ulDestinationIPAddress != ipLLMNR_IP_ADDR ) && + #endif + ( *ipLOCAL_IP_ADDRESS_POINTER != 0 ) ) { + FreeRTOS_printf( ( "Drop IP %lxip\n", FreeRTOS_ntohl( ulDestinationIPAddress ) ) ); + return pdFALSE; + } + + if( pxIPHeader->ucProtocol == ipPROTOCOL_UDP ) + { + uint16_t port = pxProtPacket->xUDPPacket.xUDPHeader.usDestinationPort; + + if( ( xPortHasUDPSocket( port ) == pdFALSE ) + #if ipconfigUSE_LLMNR == 1 + && ( port != FreeRTOS_ntohs( ipLLMNR_PORT ) ) + #endif + #if ipconfigUSE_NBNS == 1 + && ( port != FreeRTOS_ntohs( ipNBNS_PORT ) ) + #endif + #if ipconfigUSE_DNS == 1 + && ( pxProtPacket->xUDPPacket.xUDPHeader.usSourcePort != FreeRTOS_ntohs( ipDNS_PORT ) ) + #endif + ) { + /* Drop this packet, not for this device. */ + return pdFALSE; + } + } + } + #endif /* ipconfigETHERNET_DRIVER_FILTERS_PACKETS */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvNetworkInterfaceInput( void ) +{ +NetworkBufferDescriptor_t *pxCurDescriptor; +NetworkBufferDescriptor_t *pxNewDescriptor = NULL; +BaseType_t xReceivedLength, xAccepted; +__IO ETH_DMADescTypeDef *pxDMARxDescriptor; +xIPStackEvent_t xRxEvent = { eNetworkRxEvent, NULL }; +const TickType_t xDescriptorWaitTime = pdMS_TO_TICKS( 250 ); +uint8_t *pucBuffer; + + pxDMARxDescriptor = xETH.RxDesc; + + if( ( pxDMARxDescriptor->Status & ETH_DMARXDESC_OWN) == 0 ) + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + xReceivedLength = ( ( pxDMARxDescriptor->Status & ETH_DMARXDESC_FL ) >> ETH_DMARXDESC_FRAMELENGTHSHIFT ) - 4; + + pucBuffer = (uint8_t *) pxDMARxDescriptor->Buffer1Addr; + + /* Update the ETHERNET DMA global Rx descriptor with next Rx descriptor */ + /* Chained Mode */ + /* Selects the next DMA Rx descriptor list for next buffer to read */ + xETH.RxDesc = ( ETH_DMADescTypeDef* )pxDMARxDescriptor->Buffer2NextDescAddr; + } + else + { + xReceivedLength = 0; + } + + /* Obtain the size of the packet and put it into the "usReceivedLength" variable. */ + + /* get received frame */ + if( xReceivedLength > 0ul ) + { + /* In order to make the code easier and faster, only packets in a single buffer + will be accepted. This can be done by making the buffers large enough to + hold a complete Ethernet packet (1536 bytes). + Therefore, two sanity checks: */ + configASSERT( xReceivedLength <= ETH_RX_BUF_SIZE ); + + if( ( pxDMARxDescriptor->Status & ( ETH_DMARXDESC_CE | ETH_DMARXDESC_IPV4HCE | ETH_DMARXDESC_FT ) ) != ETH_DMARXDESC_FT ) + { + /* Not an Ethernet frame-type or a checmsum error. */ + xAccepted = pdFALSE; + } + else + { + /* See if this packet must be handled. */ + xAccepted = xMayAcceptPacket( pucBuffer ); + } + + if( xAccepted != pdFALSE ) + { + /* The packet wil be accepted, but check first if a new Network Buffer can + be obtained. If not, the packet will still be dropped. */ + pxNewDescriptor = pxGetNetworkBufferWithDescriptor( ETH_RX_BUF_SIZE, xDescriptorWaitTime ); + + if( pxNewDescriptor == NULL ) + { + /* A new descriptor can not be allocated now. This packet will be dropped. */ + xAccepted = pdFALSE; + } + } + #if( ipconfigZERO_COPY_RX_DRIVER != 0 ) + { + /* Find out which Network Buffer was originally passed to the descriptor. */ + pxCurDescriptor = pxPacketBuffer_to_NetworkBuffer( pucBuffer ); + configASSERT( pxCurDescriptor != NULL ); + } + #else + { + /* In this mode, the two descriptors are the same. */ + pxCurDescriptor = pxNewDescriptor; + if( pxNewDescriptor != NULL ) + { + /* The packet is acepted and a new Network Buffer was created, + copy data to the Network Bufffer. */ + memcpy( pxNewDescriptor->pucEthernetBuffer, pucBuffer, xReceivedLength ); + } + } + #endif + + if( xAccepted != pdFALSE ) + { + pxCurDescriptor->xDataLength = xReceivedLength; + xRxEvent.pvData = ( void * ) pxCurDescriptor; + + /* Pass the data to the TCP/IP task for processing. */ + if( xSendEventStructToIPTask( &xRxEvent, xDescriptorWaitTime ) == pdFALSE ) + { + /* Could not send the descriptor into the TCP/IP stack, it + must be released. */ + vReleaseNetworkBufferAndDescriptor( pxCurDescriptor ); + iptraceETHERNET_RX_EVENT_LOST(); + } + else + { + iptraceNETWORK_INTERFACE_RECEIVE(); + } + } + + /* Release descriptors to DMA */ + #if( ipconfigZERO_COPY_RX_DRIVER != 0 ) + { + /* Set Buffer1 address pointer */ + if( pxNewDescriptor != NULL ) + { + pxDMARxDescriptor->Buffer1Addr = (uint32_t)pxNewDescriptor->pucEthernetBuffer; + } + else + { + /* The packet was dropped and the same Network + Buffer will be used to receive a new packet. */ + } + } + #endif /* ipconfigZERO_COPY_RX_DRIVER */ + + /* Set Buffer1 size and Second Address Chained bit */ + pxDMARxDescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | (uint32_t)ETH_RX_BUF_SIZE; + pxDMARxDescriptor->Status = ETH_DMARXDESC_OWN; + + /* Ensure completion of memory access */ + __DSB(); + /* When Rx Buffer unavailable flag is set clear it and resume + reception. */ + if( ( xETH.Instance->DMASR & ETH_DMASR_RBUS ) != 0 ) + { + /* Clear RBUS ETHERNET DMA flag. */ + xETH.Instance->DMASR = ETH_DMASR_RBUS; + + /* Resume DMA reception. */ + xETH.Instance->DMARPDR = 0; + } + } + + return ( xReceivedLength > 0 ); +} +/*-----------------------------------------------------------*/ + + +BaseType_t xSTM32_PhyRead( BaseType_t xAddress, BaseType_t xRegister, uint32_t *pulValue ) +{ +uint16_t usPrevAddress = xETH.Init.PhyAddress; +BaseType_t xResult; +HAL_StatusTypeDef xHALResult; + + xETH.Init.PhyAddress = xAddress; + xHALResult = HAL_ETH_ReadPHYRegister( &xETH, ( uint16_t )xRegister, pulValue ); + xETH.Init.PhyAddress = usPrevAddress; + + if( xHALResult == HAL_OK ) + { + xResult = 0; + } + else + { + xResult = -1; + } + return xResult; +} +/*-----------------------------------------------------------*/ + +BaseType_t xSTM32_PhyWrite( BaseType_t xAddress, BaseType_t xRegister, uint32_t ulValue ) +{ +uint16_t usPrevAddress = xETH.Init.PhyAddress; +BaseType_t xResult; +HAL_StatusTypeDef xHALResult; + + xETH.Init.PhyAddress = xAddress; + xHALResult = HAL_ETH_WritePHYRegister( &xETH, ( uint16_t )xRegister, ulValue ); + xETH.Init.PhyAddress = usPrevAddress; + + if( xHALResult == HAL_OK ) + { + xResult = 0; + } + else + { + xResult = -1; + } + return xResult; +} +/*-----------------------------------------------------------*/ + +void phy_test() +{ +BaseType_t xPhyCount; +BaseType_t xPhyIndex; + + vPhyInitialise( &xPhyObject, xSTM32_PhyRead, xSTM32_PhyWrite ); + xPhyCount = xPhyDiscover( &xPhyObject ); + FreeRTOS_printf( ( "PHY count %ld\n", xPhyCount ) ); + for( xPhyIndex = 0; xPhyIndex < xPhyCount; xPhyIndex++ ) + { + FreeRTOS_printf( ( "PHY[%d] at address %d ( 0x%08X )\n", + xPhyIndex, + xPhyObject.ucPhyIndexes[ xPhyIndex ], + xPhyObject.ulPhyIDs[ xPhyIndex ] ) ); + + } + +} + +void vMACBProbePhy( void ) +{ + vPhyInitialise( &xPhyObject, xSTM32_PhyRead, xSTM32_PhyWrite ); + xPhyDiscover( &xPhyObject ); + xPhyConfigure( &xPhyObject, &xPHYProperties ); +} +/*-----------------------------------------------------------*/ + +static void prvEthernetUpdateConfig( BaseType_t xForce ) +{ + FreeRTOS_printf( ( "prvEthernetUpdateConfig: LS mask %02X Force %d\n", + xPhyObject.ulLinkStatusMask, + ( int )xForce ) ); + + if( ( xForce != pdFALSE ) || ( xPhyObject.ulLinkStatusMask != 0 ) ) + { + /* Restart the auto-negotiation. */ + if( xETH.Init.AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE ) + { + xPhyStartAutoNegotiation( &xPhyObject, xPhyGetMask( &xPhyObject ) ); + + /* Configure the MAC with the Duplex Mode fixed by the + auto-negotiation process. */ + if( xPhyObject.xPhyProperties.ucDuplex == PHY_DUPLEX_FULL ) + { + xETH.Init.DuplexMode = ETH_MODE_FULLDUPLEX; + } + else + { + xETH.Init.DuplexMode = ETH_MODE_HALFDUPLEX; + } + + /* Configure the MAC with the speed fixed by the + auto-negotiation process. */ + if( xPhyObject.xPhyProperties.ucSpeed == PHY_SPEED_10 ) + { + xETH.Init.Speed = ETH_SPEED_10M; + } + else + { + xETH.Init.Speed = ETH_SPEED_100M; + } + } + else /* AutoNegotiation Disable */ + { + /* Check parameters */ + assert_param( IS_ETH_SPEED( xETH.Init.Speed ) ); + assert_param( IS_ETH_DUPLEX_MODE( xETH.Init.DuplexMode ) ); + + if( xETH.Init.DuplexMode == ETH_MODE_FULLDUPLEX ) + { + xPhyObject.xPhyPreferences.ucDuplex = PHY_DUPLEX_HALF; + } + else + { + xPhyObject.xPhyPreferences.ucDuplex = PHY_DUPLEX_FULL; + } + + if( xETH.Init.Speed == ETH_SPEED_10M ) + { + xPhyObject.xPhyPreferences.ucSpeed = PHY_SPEED_10; + } + else + { + xPhyObject.xPhyPreferences.ucSpeed = PHY_SPEED_100; + } + + xPhyObject.xPhyPreferences.ucMDI_X = PHY_MDIX_AUTO; + + /* Use predefined (fixed) configuration. */ + xPhyFixedValue( &xPhyObject, xPhyGetMask( &xPhyObject ) ); + } + + /* ETHERNET MAC Re-Configuration */ + HAL_ETH_ConfigMAC( &xETH, (ETH_MACInitTypeDef *) NULL); + + /* Restart MAC interface */ + HAL_ETH_Start( &xETH); + } + else + { + /* Stop MAC interface */ + HAL_ETH_Stop( &xETH ); + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xGetPhyLinkStatus( void ) +{ +BaseType_t xReturn; + + if( xPhyObject.ulLinkStatusMask != 0 ) + { + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#define niBUFFER_1_PACKET_SIZE 1536 + +static __attribute__ ((section(".first_data"))) uint8_t ucNetworkPackets[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS * niBUFFER_1_PACKET_SIZE ] __attribute__ ( ( aligned( 32 ) ) ); + +void vNetworkInterfaceAllocateRAMToBuffers( NetworkBufferDescriptor_t pxNetworkBuffers[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ] ) +{ + +uint8_t *ucRAMBuffer = ucNetworkPackets; +uint32_t ul; + + for( ul = 0; ul < ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS; ul++ ) + { + pxNetworkBuffers[ ul ].pucEthernetBuffer = ucRAMBuffer + ipBUFFER_PADDING; + *( ( unsigned * ) ucRAMBuffer ) = ( unsigned ) ( &( pxNetworkBuffers[ ul ] ) ); + ucRAMBuffer += niBUFFER_1_PACKET_SIZE; + } +} +/*-----------------------------------------------------------*/ + +static void prvEMACHandlerTask( void *pvParameters ) +{ +UBaseType_t uxLastMinBufferCount = 0; +#if( ipconfigCHECK_IP_QUEUE_SPACE != 0 ) +UBaseType_t uxLastMinQueueSpace = 0; +#endif +UBaseType_t uxCurrentCount; +BaseType_t xResult; +const TickType_t ulMaxBlockTime = pdMS_TO_TICKS( 100UL ); + + /* Remove compiler warnings about unused parameters. */ + ( void ) pvParameters; + + for( ;; ) + { + xResult = 0; + uxCurrentCount = uxGetMinimumFreeNetworkBuffers(); + if( uxLastMinBufferCount != uxCurrentCount ) + { + /* The logging produced below may be helpful + while tuning +TCP: see how many buffers are in use. */ + uxLastMinBufferCount = uxCurrentCount; + FreeRTOS_printf( ( "Network buffers: %lu lowest %lu\n", + uxGetNumberOfFreeNetworkBuffers(), uxCurrentCount ) ); + } + + if( xTXDescriptorSemaphore != NULL ) + { + static UBaseType_t uxLowestSemCount = ( UBaseType_t ) ETH_TXBUFNB - 1; + + uxCurrentCount = uxSemaphoreGetCount( xTXDescriptorSemaphore ); + if( uxLowestSemCount > uxCurrentCount ) + { + uxLowestSemCount = uxCurrentCount; + FreeRTOS_printf( ( "TX DMA buffers: lowest %lu\n", uxLowestSemCount ) ); + } + + } + + #if( ipconfigCHECK_IP_QUEUE_SPACE != 0 ) + { + uxCurrentCount = uxGetMinimumIPQueueSpace(); + if( uxLastMinQueueSpace != uxCurrentCount ) + { + /* The logging produced below may be helpful + while tuning +TCP: see how many buffers are in use. */ + uxLastMinQueueSpace = uxCurrentCount; + FreeRTOS_printf( ( "Queue space: lowest %lu\n", uxCurrentCount ) ); + } + } + #endif /* ipconfigCHECK_IP_QUEUE_SPACE */ + + if( ( ulISREvents & EMAC_IF_ALL_EVENT ) == 0 ) + { + /* No events to process now, wait for the next. */ + ulTaskNotifyTake( pdFALSE, ulMaxBlockTime ); + } + + if( ( ulISREvents & EMAC_IF_RX_EVENT ) != 0 ) + { + ulISREvents &= ~EMAC_IF_RX_EVENT; + + xResult = prvNetworkInterfaceInput(); + if( xResult > 0 ) + { + while( prvNetworkInterfaceInput() > 0 ) + { + } + } + } + + if( ( ulISREvents & EMAC_IF_TX_EVENT ) != 0 ) + { + /* Code to release TX buffers if zero-copy is used. */ + ulISREvents &= ~EMAC_IF_TX_EVENT; + /* Check if DMA packets have been delivered. */ + vClearTXBuffers(); + } + + if( ( ulISREvents & EMAC_IF_ERR_EVENT ) != 0 ) + { + /* Future extension: logging about errors that occurred. */ + ulISREvents &= ~EMAC_IF_ERR_EVENT; + } + if( xPhyCheckLinkStatus( &xPhyObject, xResult ) != 0 ) + { + /* Something has changed to a Link Status, need re-check. */ + prvEthernetUpdateConfig( pdFALSE ); + } + } +} +/*-----------------------------------------------------------*/ + +void ETH_IRQHandler( void ) +{ + HAL_ETH_IRQHandler( &xETH ); +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32F7xx/stm32f7xx_hal_eth.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32F7xx/stm32f7xx_hal_eth.c new file mode 100644 index 0000000..6f335c5 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32F7xx/stm32f7xx_hal_eth.c @@ -0,0 +1,1835 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_eth.c + * @author MCD Application Team + * @version V1.3.2 + * @date 26-June-2015 + * @brief ETH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Ethernet (ETH) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#)Declare a ETH_HandleTypeDef handle structure, for example: + ETH_HandleTypeDef heth; + + (#)Fill parameters of Init structure in heth handle + + (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) + + (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API: + (##) Enable the Ethernet interface clock using + (+++) __HAL_RCC_ETHMAC_CLK_ENABLE(); + (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE(); + (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE(); + + (##) Initialize the related GPIO clocks + (##) Configure Ethernet pin-out + (##) Configure Ethernet NVIC interrupt (IT mode) + + (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers: + (##) HAL_ETH_DMATxDescListInit(); for Transmission process + (##) HAL_ETH_DMARxDescListInit(); for Reception process + + (#)Enable MAC and DMA transmission and reception: + (##) HAL_ETH_Start(); + + (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer + the frame to MAC TX FIFO: + (##) HAL_ETH_TransmitFrame(); + + (#)Poll for a received frame in ETH RX DMA Descriptors and get received + frame parameters + (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop) + + (#) Get a received frame when an ETH RX interrupt occurs: + (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only) + + (#) Communicate with external PHY device: + (##) Read a specific register from the PHY + HAL_ETH_ReadPHYRegister(); + (##) Write data to a specific RHY register: + HAL_ETH_WritePHYRegister(); + + (#) Configure the Ethernet MAC after ETH peripheral initialization + HAL_ETH_ConfigMAC(); all MAC parameters should be filled. + + (#) Configure the Ethernet DMA after ETH peripheral initialization + HAL_ETH_ConfigDMA(); all DMA parameters should be filled. + + -@- The PTP protocol and the DMA descriptors ring mode are not supported + in this driver + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + + +int lUDPLoggingPrintf( const char *pcFormatString, ... ); + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup ETH ETH + * @brief ETH HAL module driver + * @{ + */ + +#if !defined( ARRAY_SIZE ) + #define ARRAY_SIZE( x ) ( sizeof ( x ) / sizeof ( x )[ 0 ] ) +#endif + +#ifdef HAL_ETH_MODULE_ENABLED + +#if defined(STM32F7xx) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup ETH_Private_Constants ETH Private Constants + * @{ + */ +#define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */ +#define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */ + +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup ETH_Private_Functions ETH Private Functions + * @{ + */ +static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err); +static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr); +static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth); +static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth); +static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth); +static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth); +static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth); +static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth); +static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth); +static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth); +static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth); + +/** + * @} + */ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup ETH_Exported_Functions ETH Exported Functions + * @{ + */ + +/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the Ethernet peripheral + (+) De-initialize the Ethernet peripheral + + @endverbatim + * @{ + */ +extern void vMACBProbePhy ( void ); + +/** + * @brief Initializes the Ethernet MAC and DMA according to default + * parameters. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) +{ + uint32_t tmpreg = 0; + uint32_t hclk = 60000000; + uint32_t err = ETH_SUCCESS; + + /* Check the ETH peripheral state */ + if( heth == NULL ) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation)); + assert_param(IS_ETH_RX_MODE(heth->Init.RxMode)); + assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode)); + assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface)); + + if( heth->State == HAL_ETH_STATE_RESET ) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC. */ + HAL_ETH_MspInit( heth ); + } + + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Select MII or RMII Mode*/ + SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL); + SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface; + + /* Ethernet Software reset */ + /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ + /* After reset all the registers holds their respective reset values */ + /* Also enable EDFE: Enhanced descriptor format enable. */ +// heth->Instance->DMABMR |= ETH_DMABMR_SR | ETH_DMABMR_EDE; + heth->Instance->DMABMR |= ETH_DMABMR_SR; + + /* Wait for software reset */ + while ((heth->Instance->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) + { + } + + /*-------------------------------- MAC Initialization ----------------------*/ + /* Get the ETHERNET MACMIIAR value */ + tmpreg = heth->Instance->MACMIIAR; + /* Clear CSR Clock Range CR[2:0] bits */ + tmpreg &= ETH_MACMIIAR_CR_MASK; + + /* Get hclk frequency value (168,000,000) */ + hclk = HAL_RCC_GetHCLKFreq(); + + /* Set CR bits depending on hclk value */ + if( ( hclk >= 20000000 ) && ( hclk < 35000000 ) ) + { + /* CSR Clock Range between 20-35 MHz */ + tmpreg |= (uint32_t) ETH_MACMIIAR_CR_Div16; + } + else if( ( hclk >= 35000000 ) && ( hclk < 60000000 ) ) + { + /* CSR Clock Range between 35-60 MHz */ + tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div26; + } + else if((hclk >= 60000000 ) && ( hclk < 100000000 ) ) + { + /* CSR Clock Range between 60-100 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; + } + else if((hclk >= 100000000 ) && ( hclk < 150000000)) + { + /* CSR Clock Range between 100-150 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62; + } + else /* ((hclk >= 150000000 ) && ( hclk <= 168000000)) */ + { + /* CSR Clock Range between 150-168 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102; + } + + /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ + heth->Instance->MACMIIAR = (uint32_t)tmpreg; + + /* Initialise the MACB and set all PHY properties */ + vMACBProbePhy(); + + /* Config MAC and DMA */ + ETH_MACDMAConfig(heth, err); + + /* Set ETH HAL State to Ready */ + heth->State= HAL_ETH_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief De-Initializes the ETH peripheral. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) +{ + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */ + HAL_ETH_MspDeInit( heth ); + + /* Set ETH HAL state to Disabled */ + heth->State= HAL_ETH_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK( heth ); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the DMA Tx descriptors in chain mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param DMATxDescTab: Pointer to the first Tx desc list + * @param TxBuff: Pointer to the first TxBuffer list + * @param TxBuffCount: Number of the used Tx desc in the list + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *pxDMATable, uint8_t *ucDataBuffer, uint32_t ulBufferCount) +{ + uint32_t i = 0; + ETH_DMADescTypeDef *pxDMADescriptor; + + /* Process Locked */ + __HAL_LOCK( heth ); + + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* Set the TxDesc pointer with the first one of the pxDMATable list */ + heth->TxDesc = pxDMATable; + + /* Fill each DMA descriptor with the right values */ + for( i=0; i < ulBufferCount; i++ ) + { + /* Get the pointer on the ith member of the descriptor list */ + pxDMADescriptor = pxDMATable + i; + + /* Set Second Address Chained bit */ + pxDMADescriptor->Status = ETH_DMATXDESC_TCH; + + pxDMADescriptor->ControlBufferSize = 0; + + /* Set Buffer1 address pointer */ + if( ucDataBuffer != NULL ) + { + pxDMADescriptor->Buffer1Addr = ( uint32_t )( &ucDataBuffer[ i * ETH_TX_BUF_SIZE ] ); + } + else + { + /* Buffer space is not provided because it uses zero-copy transmissions. */ + pxDMADescriptor->Buffer1Addr = ( uint32_t )0u; + } + + if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) + { + /* Set the DMA Tx descriptors checksum insertion for TCP, UDP, and ICMP */ + pxDMADescriptor->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL; + } + + /* Initialize the next descriptor with the Next Descriptor Polling Enable */ + if(i < ( ulBufferCount - 1 ) ) + { + /* Set next descriptor address register with next descriptor base address */ + pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) ( pxDMATable + i + 1 ); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) pxDMATable; + } + } + + /* Set Transmit Descriptor List Address Register */ + heth->Instance->DMATDLAR = ( uint32_t ) pxDMATable; + + /* Set ETH HAL State to Ready */ + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the DMA Rx descriptors in chain mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param DMARxDescTab: Pointer to the first Rx desc list + * @param RxBuff: Pointer to the first RxBuffer list + * @param RxBuffCount: Number of the used Rx desc in the list + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *pxDMATable, uint8_t *ucDataBuffer, uint32_t ulBufferCount) +{ + uint32_t i = 0; + ETH_DMADescTypeDef *pxDMADescriptor; + + /* Process Locked */ + __HAL_LOCK( heth ); + + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* Set the RxDesc pointer with the first one of the pxDMATable list */ + heth->RxDesc = pxDMATable; + + /* Fill each DMA descriptor with the right values */ + for(i=0; i < ulBufferCount; i++) + { + /* Get the pointer on the ith member of the descriptor list */ + pxDMADescriptor = pxDMATable+i; + + /* Set Own bit of the Rx descriptor Status */ + pxDMADescriptor->Status = ETH_DMARXDESC_OWN; + + /* Set Buffer1 size and Second Address Chained bit */ + pxDMADescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE; + + /* Set Buffer1 address pointer */ + if( ucDataBuffer != NULL ) + { + pxDMADescriptor->Buffer1Addr = ( uint32_t )( &ucDataBuffer[ i * ETH_RX_BUF_SIZE ] ); + } + else + { + /* Buffer space is not provided because it uses zero-copy reception. */ + pxDMADescriptor->Buffer1Addr = ( uint32_t )0u; + } + + if( heth->Init.RxMode == ETH_RXINTERRUPT_MODE ) + { + /* Enable Ethernet DMA Rx Descriptor interrupt */ + pxDMADescriptor->ControlBufferSize &= ~ETH_DMARXDESC_DIC; + } + + /* Initialize the next descriptor with the Next Descriptor Polling Enable */ + if(i < (ulBufferCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + pxDMADescriptor->Buffer2NextDescAddr = (uint32_t)(pxDMATable+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) pxDMATable; + } + } + + /* Set Receive Descriptor List Address Register */ + heth->Instance->DMARDLAR = ( uint32_t ) pxDMATable; + + /* Set ETH HAL State to Ready */ + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the ETH MSP. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes ETH MSP. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * + @verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Transmit a frame + HAL_ETH_TransmitFrame(); + (+) Receive a frame + HAL_ETH_GetReceivedFrame(); + HAL_ETH_GetReceivedFrame_IT(); + (+) Read from an External PHY register + HAL_ETH_ReadPHYRegister(); + (+) Write to an External PHY register + HAL_ETH_WritePHYRegister(); + + @endverbatim + + * @{ + */ + +/** + * @brief Sends an Ethernet frame. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param FrameLength: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength) +{ + uint32_t bufcount = 0, size = 0, i = 0; + __IO ETH_DMADescTypeDef *pxDmaTxDesc = heth->TxDesc; + /* Process Locked */ + __HAL_LOCK( heth ); + + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + if( FrameLength == 0 ) + { + /* Set ETH HAL state to READY */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + + return HAL_ERROR; + } + + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if( ( pxDmaTxDesc->Status & ETH_DMATXDESC_OWN ) != ( uint32_t ) RESET ) + { + /* OWN bit set */ + heth->State = HAL_ETH_STATE_BUSY_TX; + + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + + return HAL_ERROR; + } + + /* Get the number of needed Tx buffers for the current frame, rounding up. */ + bufcount = ( FrameLength + ETH_TX_BUF_SIZE - 1 ) / ETH_TX_BUF_SIZE; + + if (bufcount == 1) + { + /* Set LAST and FIRST segment */ + pxDmaTxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS; + /* Set frame size */ + pxDmaTxDesc->ControlBufferSize = ( FrameLength & ETH_DMATXDESC_TBS1 ); + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + pxDmaTxDesc->Status |= ETH_DMATXDESC_OWN; + /* Point to next descriptor */ + heth->TxDesc = ( ETH_DMADescTypeDef * ) ( heth->TxDesc->Buffer2NextDescAddr ); + } + else + { + for( i = 0; i < bufcount; i++ ) + { + /* Clear FIRST and LAST segment bits */ + uint32_t ulStatus = heth->TxDesc->Status & ~( ETH_DMATXDESC_FS | ETH_DMATXDESC_LS ); + + if( i == 0 ) + { + /* Setting the first segment bit */ + heth->TxDesc->Status = ulStatus | ETH_DMATXDESC_FS; + } + + /* Program size */ + if (i < (bufcount-1)) + { + heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1); + } + else + { + /* Setting the last segment bit */ + heth->TxDesc->Status = ulStatus | ETH_DMATXDESC_LS; + size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE; + heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1); + } + + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + heth->TxDesc->Status |= ETH_DMATXDESC_OWN; + /* point to next descriptor */ + heth->TxDesc = (ETH_DMADescTypeDef *)( heth->TxDesc->Buffer2NextDescAddr ); + } + } + + __DSB(); + + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if( ( heth->Instance->DMASR & ETH_DMASR_TBUS ) != ( uint32_t )RESET ) + { + heth->Instance->DMACHTDR = ( uint32_t )pxDmaTxDesc; + + /* Clear TBUS ETHERNET DMA flag */ + heth->Instance->DMASR = ETH_DMASR_TBUS; + /* Resume DMA transmission*/ + heth->Instance->DMATPDR = 0; + } + + /* Set ETH HAL State to Ready */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Checks for received frames. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT( ETH_HandleTypeDef *heth ) +{ + return HAL_ETH_GetReceivedFrame( heth ); +} + +HAL_StatusTypeDef HAL_ETH_GetReceivedFrame( ETH_HandleTypeDef *heth ) +{ +uint32_t ulCounter = 0; +ETH_DMADescTypeDef *pxDescriptor = heth->RxDesc; +HAL_StatusTypeDef xResult = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK( heth ); + + /* Check the ETH state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* Scan descriptors owned by CPU */ + while( ( ( pxDescriptor->Status & ETH_DMARXDESC_OWN ) == 0ul ) && ( ulCounter < ETH_RXBUFNB ) ) + { + uint32_t ulStatus = pxDescriptor->Status; + + /* Just for security. */ + ulCounter++; + + if( ( ulStatus & ( ETH_DMARXDESC_FS | ETH_DMARXDESC_LS ) ) == ( uint32_t )ETH_DMARXDESC_FS ) + { + /* First segment in frame, but not the last. */ + heth->RxFrameInfos.FSRxDesc = pxDescriptor; + heth->RxFrameInfos.LSRxDesc = ( ETH_DMADescTypeDef *)NULL; + heth->RxFrameInfos.SegCount = 1; + /* Point to next descriptor. */ + pxDescriptor = (ETH_DMADescTypeDef*) (pxDescriptor->Buffer2NextDescAddr); + heth->RxDesc = pxDescriptor; + } + else if( ( ulStatus & ( ETH_DMARXDESC_LS | ETH_DMARXDESC_FS ) ) == 0ul ) + { + /* This is an intermediate segment, not first, not last. */ + /* Increment segment count. */ + heth->RxFrameInfos.SegCount++; + /* Move to the next descriptor. */ + pxDescriptor = ( ETH_DMADescTypeDef * ) ( pxDescriptor->Buffer2NextDescAddr ); + heth->RxDesc = pxDescriptor; + } + /* Must be a last segment */ + else + { + /* This is the last segment. */ + /* Check if last segment is first segment: one segment contains the frame */ + if( heth->RxFrameInfos.SegCount == 0 ) + { + /* Remember the first segment. */ + heth->RxFrameInfos.FSRxDesc = pxDescriptor; + } + + /* Increment segment count */ + heth->RxFrameInfos.SegCount++; + + /* Remember the last segment. */ + heth->RxFrameInfos.LSRxDesc = pxDescriptor; + + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + heth->RxFrameInfos.length = + ( ( ulStatus & ETH_DMARXDESC_FL ) >> ETH_DMARXDESC_FRAMELENGTHSHIFT ) - 4; + + /* Get the address of the buffer start address */ + heth->RxFrameInfos.buffer = heth->RxFrameInfos.FSRxDesc->Buffer1Addr; + + /* Point to next descriptor */ + heth->RxDesc = ( ETH_DMADescTypeDef * ) pxDescriptor->Buffer2NextDescAddr; + + /* Return OK status: a packet was received. */ + xResult = HAL_OK; + break; + } + } + + /* Set ETH HAL State to Ready */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + + /* Return function status */ + return xResult; +} + +#if( STM32_ETHERNET_STATS != 0 ) + + volatile int rx_count, tx_count, int_count; + /** + * @brief This function handles ETH interrupt request. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ + volatile int int_counts[32]; + volatile int tx_status[8]; + volatile unsigned sr_history[32]; + volatile int sr_head; + #define STM32_STAT_INC( x ) do { ( x )++; } while( 0 ) + +#else + #define STM32_STAT_INC( x ) do { } while( 0 ) +#endif /* STM32_ETHERNET_STATS */ + +#define ETH_DMA_ALL_INTS \ + ( ETH_DMA_IT_TST | ETH_DMA_IT_PMT | ETH_DMA_IT_MMC | ETH_DMA_IT_NIS | ETH_DMA_IT_AIS | ETH_DMA_IT_ER | \ + ETH_DMA_IT_FBE | ETH_DMA_IT_ET | ETH_DMA_IT_RWT | ETH_DMA_IT_RPS | ETH_DMA_IT_RBU | ETH_DMA_IT_R | \ + ETH_DMA_IT_TU | ETH_DMA_IT_RO | ETH_DMA_IT_TJT | ETH_DMA_IT_TPS | ETH_DMA_IT_T ) + +//#define ETH_DMA_ALL_INTS ETH_DMA_IT_RBU | ETH_DMA_FLAG_T | ETH_DMA_FLAG_AIS + +#define INT_MASK ( ( uint32_t ) ~ ( ETH_DMA_IT_TBU ) ) +void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) +{ + uint32_t dmasr; + + STM32_STAT_INC( int_count ); + + dmasr = heth->Instance->DMASR & ETH_DMA_ALL_INTS; + heth->Instance->DMASR = dmasr; + +#if( STM32_ETHERNET_STATS != 0 ) + if( sr_head < ARRAY_SIZE( sr_history ) ) + { + sr_history[ sr_head++ ] = dmasr; + } + + { + int i; + for (i = 0; i < 32; i++) { + if (dmasr & (1u << i)) { + int_counts[i]++; + } + } + tx_status[ ( dmasr >> 20 ) & 0x07 ]++; + } +#endif + + /* Frame received */ + if( ( dmasr & ( ETH_DMA_FLAG_R | ETH_DMA_IT_RBU ) ) != 0 ) + { + /* Receive complete callback */ + HAL_ETH_RxCpltCallback( heth ); + STM32_STAT_INC( rx_count ); + } + /* Frame transmitted */ + if( ( dmasr & ( ETH_DMA_FLAG_T ) ) != 0 ) + { + /* Transfer complete callback */ + HAL_ETH_TxCpltCallback( heth ); + STM32_STAT_INC( tx_count ); + } + + /* ETH DMA Error */ + if( ( dmasr & ( ETH_DMA_FLAG_AIS ) ) != 0 ) + { + /* Ethernet Error callback */ + HAL_ETH_ErrorCallback( heth ); + } +} + +/** + * @brief Tx Transfer completed callbacks. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Ethernet transfer error callbacks + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Reads a PHY register + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. + * This parameter can be one of the following values: + * PHY_BCR: Transceiver Basic Control Register, + * PHY_BSR: Transceiver Basic Status Register. + * More PHY register could be read depending on the used PHY + * @param RegValue: PHY register value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue) +{ +uint32_t tmpreg = 0; +uint32_t tickstart = 0; +HAL_StatusTypeDef xResult; + + /* Check parameters */ + assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); + + /* Check the ETH peripheral state */ + if( heth->State == HAL_ETH_STATE_BUSY_RD ) + { + xResult = HAL_BUSY; + } + else + { + __HAL_LOCK( heth ); + + /* Set ETH HAL State to BUSY_RD */ + heth->State = HAL_ETH_STATE_BUSY_RD; + + /* Get the ETHERNET MACMIIAR value */ + tmpreg = heth->Instance->MACMIIAR; + + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg &= ~ETH_MACMIIAR_CR_MASK; + + /* Prepare the MII address register value */ + tmpreg |= ( ( ( uint32_t )heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA ); /* Set the PHY device address */ + tmpreg |= ( ( ( uint32_t )PHYReg << 6 ) & ETH_MACMIIAR_MR ); /* Set the PHY register address */ + tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */ + tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + + /* Write the result value into the MII Address register */ + heth->Instance->MACMIIAR = tmpreg; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check for the Busy flag */ + while( 1 ) + { + tmpreg = heth->Instance->MACMIIAR; + + if( ( tmpreg & ETH_MACMIIAR_MB ) == 0ul ) + { + /* Get MACMIIDR value */ + *RegValue = ( uint32_t ) heth->Instance->MACMIIDR; + xResult = HAL_OK; + break; + } + /* Check for the Timeout */ + if( ( HAL_GetTick( ) - tickstart ) > PHY_READ_TO ) + { + xResult = HAL_TIMEOUT; + break; + } + + } + + /* Set ETH HAL State to READY */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + } + + if( xResult != HAL_OK ) + { + lUDPLoggingPrintf( "ReadPHY: %d\n", xResult ); + } + /* Return function status */ + return xResult; +} + +/** + * @brief Writes to a PHY register. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. + * This parameter can be one of the following values: + * PHY_BCR: Transceiver Control Register. + * More PHY register could be written depending on the used PHY + * @param RegValue: the value to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue) +{ +uint32_t tmpreg = 0; +uint32_t tickstart = 0; +HAL_StatusTypeDef xResult; + + /* Check parameters */ + assert_param( IS_ETH_PHY_ADDRESS( heth->Init.PhyAddress ) ); + + /* Check the ETH peripheral state */ + if( heth->State == HAL_ETH_STATE_BUSY_WR ) + { + xResult = HAL_BUSY; + } + else + { + __HAL_LOCK( heth ); + + /* Set ETH HAL State to BUSY_WR */ + heth->State = HAL_ETH_STATE_BUSY_WR; + + /* Get the ETHERNET MACMIIAR value */ + tmpreg = heth->Instance->MACMIIAR; + + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg &= ~ETH_MACMIIAR_CR_MASK; + + /* Prepare the MII register address value */ + tmpreg |= ( ( ( uint32_t ) heth->Init.PhyAddress << 11 ) & ETH_MACMIIAR_PA ); /* Set the PHY device address */ + tmpreg |= ( ( ( uint32_t ) PHYReg << 6 ) & ETH_MACMIIAR_MR ); /* Set the PHY register address */ + tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */ + tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + + /* Give the value to the MII data register */ + heth->Instance->MACMIIDR = ( uint16_t ) RegValue; + + /* Write the result value into the MII Address register */ + heth->Instance->MACMIIAR = tmpreg; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check for the Busy flag */ + while( 1 ) + { + tmpreg = heth->Instance->MACMIIAR; + + if( ( tmpreg & ETH_MACMIIAR_MB ) == 0ul ) + { + xResult = HAL_OK; + break; + } + /* Check for the Timeout */ + if( ( HAL_GetTick( ) - tickstart ) > PHY_WRITE_TO ) + { + xResult = HAL_TIMEOUT; + break; + } + } + + /* Set ETH HAL State to READY */ + heth->State = HAL_ETH_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + } + + if( xResult != HAL_OK ) + { + lUDPLoggingPrintf( "WritePHY: %d\n", xResult ); + } + /* Return function status */ + return xResult; +} + +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Enable MAC and DMA transmission and reception. + HAL_ETH_Start(); + (+) Disable MAC and DMA transmission and reception. + HAL_ETH_Stop(); + (+) Set the MAC configuration in runtime mode + HAL_ETH_ConfigMAC(); + (+) Set the DMA configuration in runtime mode + HAL_ETH_ConfigDMA(); + +@endverbatim + * @{ + */ + + /** + * @brief Enables Ethernet MAC and DMA reception/transmission + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Start( ETH_HandleTypeDef *heth ) +{ + /* Process Locked */ + __HAL_LOCK( heth ); + + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* Enable transmit state machine of the MAC for transmission on the MII */ + ETH_MACTransmissionEnable( heth ); + + /* Enable receive state machine of the MAC for reception from the MII */ + ETH_MACReceptionEnable( heth ); + + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO( heth ); + + /* Start DMA transmission */ + ETH_DMATransmissionEnable( heth ); + + /* Start DMA reception */ + ETH_DMAReceptionEnable( heth ); + + /* Set the ETH state to READY*/ + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop Ethernet MAC and DMA reception/transmission + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) +{ + /* Process Locked */ + __HAL_LOCK( heth ); + + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* Stop DMA transmission */ + ETH_DMATransmissionDisable( heth ); + + /* Stop DMA reception */ + ETH_DMAReceptionDisable( heth ); + + /* Disable receive state machine of the MAC for reception from the MII */ + ETH_MACReceptionDisable( heth ); + + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO( heth ); + + /* Disable transmit state machine of the MAC for transmission on the MII */ + ETH_MACTransmissionDisable( heth ); + + /* Set the ETH state*/ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + + /* Return function status */ + return HAL_OK; +} + +static void prvWriteMACFCR( ETH_HandleTypeDef *heth, uint32_t ulValue) +{ + /* Enable the MAC transmission */ + heth->Instance->MACFCR = ulValue; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles. + Read it back, wait a ms and */ + ( void ) heth->Instance->MACFCR; + + HAL_Delay( ETH_REG_WRITE_DELAY ); + + heth->Instance->MACFCR = ulValue; +} + +static void prvWriteDMAOMR( ETH_HandleTypeDef *heth, uint32_t ulValue) +{ + /* Enable the MAC transmission */ + heth->Instance->DMAOMR = ulValue; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles. + Read it back, wait a ms and */ + ( void ) heth->Instance->DMAOMR; + + HAL_Delay( ETH_REG_WRITE_DELAY ); + + heth->Instance->DMAOMR = ulValue; +} + +static void prvWriteMACCR( ETH_HandleTypeDef *heth, uint32_t ulValue) +{ + /* Enable the MAC transmission */ + heth->Instance->MACCR = ulValue; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles. + Read it back, wait a ms and */ + ( void ) heth->Instance->MACCR; + + HAL_Delay( ETH_REG_WRITE_DELAY ); + + heth->Instance->MACCR = ulValue; +} + +/** + * @brief Set ETH MAC Configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param macconf: MAC Configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf) +{ + uint32_t tmpreg = 0; + + /* Process Locked */ + __HAL_LOCK( heth ); + + /* Set the ETH peripheral state to BUSY */ + heth->State= HAL_ETH_STATE_BUSY; + + assert_param(IS_ETH_SPEED(heth->Init.Speed)); + assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); + + if (macconf != NULL) + { + /* Check the parameters */ + assert_param(IS_ETH_WATCHDOG(macconf->Watchdog)); + assert_param(IS_ETH_JABBER(macconf->Jabber)); + assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap)); + assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense)); + assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn)); + assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode)); + assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload)); + assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission)); + assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip)); + assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit)); + assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck)); + assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll)); + assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter)); + assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames)); + assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception)); + assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter)); + assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode)); + assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter)); + assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter)); + assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime)); + assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause)); + assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold)); + assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect)); + assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl)); + assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl)); + assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison)); + assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier)); + + /*------------------------ ETHERNET MACCR Configuration --------------------*/ + /* Get the ETHERNET MACCR value */ + tmpreg = heth->Instance->MACCR; + /* Clear WD, PCE, PS, TE and RE bits */ + tmpreg &= ETH_MACCR_CLEAR_MASK; + + tmpreg |= (uint32_t)( + macconf->Watchdog | + macconf->Jabber | + macconf->InterFrameGap | + macconf->CarrierSense | + heth->Init.Speed | + macconf->ReceiveOwn | + macconf->LoopbackMode | + heth->Init.DuplexMode | + macconf->ChecksumOffload | + macconf->RetryTransmission | + macconf->AutomaticPadCRCStrip | + macconf->BackOffLimit | + macconf->DeferralCheck); + + /* Write to ETHERNET MACCR */ + prvWriteMACCR( heth, tmpreg ); + + /*----------------------- ETHERNET MACFFR Configuration --------------------*/ + /* Write to ETHERNET MACFFR */ + heth->Instance->MACFFR = (uint32_t)( + macconf->ReceiveAll | + macconf->SourceAddrFilter | + macconf->PassControlFrames | + macconf->BroadcastFramesReception | + macconf->DestinationAddrFilter | + macconf->PromiscuousMode | + macconf->MulticastFramesFilter | + macconf->UnicastFramesFilter); + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg = heth->Instance->MACFFR; + HAL_Delay(ETH_REG_WRITE_DELAY); + heth->Instance->MACFFR = tmpreg; + + /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ + /* Write to ETHERNET MACHTHR */ + heth->Instance->MACHTHR = (uint32_t)macconf->HashTableHigh; + + /* Write to ETHERNET MACHTLR */ + heth->Instance->MACHTLR = (uint32_t)macconf->HashTableLow; + /*----------------------- ETHERNET MACFCR Configuration --------------------*/ + + /* Get the ETHERNET MACFCR value */ + tmpreg = heth->Instance->MACFCR; + /* Clear xx bits */ + tmpreg &= ETH_MACFCR_CLEAR_MASK; + + tmpreg |= (uint32_t)(( + macconf->PauseTime << 16) | + macconf->ZeroQuantaPause | + macconf->PauseLowThreshold | + macconf->UnicastPauseFrameDetect | + macconf->ReceiveFlowControl | + macconf->TransmitFlowControl); + + /* Write to ETHERNET MACFCR */ + prvWriteMACFCR( heth, tmpreg ); + + /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ + heth->Instance->MACVLANTR = (uint32_t)(macconf->VLANTagComparison | + macconf->VLANTagIdentifier); + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg = heth->Instance->MACVLANTR; + HAL_Delay(ETH_REG_WRITE_DELAY); + heth->Instance->MACVLANTR = tmpreg; + } + else /* macconf == NULL : here we just configure Speed and Duplex mode */ + { + /*------------------------ ETHERNET MACCR Configuration --------------------*/ + /* Get the ETHERNET MACCR value */ + tmpreg = heth->Instance->MACCR; + + /* Clear FES and DM bits */ + tmpreg &= ~((uint32_t)0x00004800); + + tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode); + + /* Write to ETHERNET MACCR */ + prvWriteMACCR( heth, tmpreg ); + } + + /* Set the ETH state to Ready */ + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Sets ETH DMA Configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param dmaconf: DMA Configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf) +{ + uint32_t tmpreg = 0; + + /* Process Locked */ + __HAL_LOCK( heth ); + + /* Set the ETH peripheral state to BUSY */ + heth->State= HAL_ETH_STATE_BUSY; + + /* Check parameters */ + assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame)); + assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward)); + assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame)); + assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward)); + assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl)); + assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames)); + assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames)); + assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl)); + assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate)); + assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats)); + assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst)); + assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength)); + assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength)); + assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat)); + assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength)); + assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration)); + + /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ + /* Get the ETHERNET DMAOMR value */ + tmpreg = heth->Instance->DMAOMR; + /* Clear xx bits */ + tmpreg &= ETH_DMAOMR_CLEAR_MASK; + + tmpreg |= (uint32_t)( + dmaconf->DropTCPIPChecksumErrorFrame | + dmaconf->ReceiveStoreForward | + dmaconf->FlushReceivedFrame | + dmaconf->TransmitStoreForward | + dmaconf->TransmitThresholdControl | + dmaconf->ForwardErrorFrames | + dmaconf->ForwardUndersizedGoodFrames | + dmaconf->ReceiveThresholdControl | + dmaconf->SecondFrameOperate); + + /* Write to ETHERNET DMAOMR */ + prvWriteDMAOMR( heth, tmpreg ); + + /*----------------------- ETHERNET DMABMR Configuration --------------------*/ + heth->Instance->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats | + dmaconf->FixedBurst | + dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ + dmaconf->TxDMABurstLength | + dmaconf->EnhancedDescriptorFormat | + (dmaconf->DescriptorSkipLength << 2) | + dmaconf->DMAArbitration | + ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg = heth->Instance->DMABMR; + HAL_Delay(ETH_REG_WRITE_DELAY); + heth->Instance->DMABMR = tmpreg; + + /* Set the ETH state to Ready */ + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * + @verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + (+) Get the ETH handle state: + HAL_ETH_GetState(); + + + @endverbatim + * @{ + */ + +/** + * @brief Return the ETH HAL state + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL state + */ +HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) +{ + /* Return ETH state */ + return heth->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup ETH_Private_Functions + * @{ + */ + +/** + * @brief Configures Ethernet MAC and DMA with default parameters. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param err: Ethernet Init error + * @retval HAL status + */ +static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) +{ + ETH_MACInitTypeDef macinit; + ETH_DMAInitTypeDef dmainit; + uint32_t tmpreg = 0; + + if (err != ETH_SUCCESS) /* Auto-negotiation failed */ + { + /* Set Ethernet duplex mode to Full-duplex */ + heth->Init.DuplexMode = ETH_MODE_FULLDUPLEX; + + /* Set Ethernet speed to 100M */ + heth->Init.Speed = ETH_SPEED_100M; + } + + /* Ethernet MAC default initialization **************************************/ + macinit.Watchdog = ETH_WATCHDOG_ENABLE; + macinit.Jabber = ETH_JABBER_ENABLE; + macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT; + macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE; + macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE; + macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE; + if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) + { + macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; + } + else + { + macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE; + } + macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE; + macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE; + macinit.BackOffLimit = ETH_BACKOFFLIMIT_10; + macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE; + macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE; + macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE; + macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL; + macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE; + macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL; + macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE; + macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT; + macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT; + macinit.HashTableHigh = 0x0; + macinit.HashTableLow = 0x0; + macinit.PauseTime = 0x0; + macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE; + macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4; + macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE; + macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE; + macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE; + macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT; + macinit.VLANTagIdentifier = 0x0; + + /*------------------------ ETHERNET MACCR Configuration --------------------*/ + /* Get the ETHERNET MACCR value */ + tmpreg = heth->Instance->MACCR; + /* Clear WD, PCE, PS, TE and RE bits */ + tmpreg &= ETH_MACCR_CLEAR_MASK; + /* Set the WD bit according to ETH Watchdog value */ + /* Set the JD: bit according to ETH Jabber value */ + /* Set the IFG bit according to ETH InterFrameGap value */ + /* Set the DCRS bit according to ETH CarrierSense value */ + /* Set the FES bit according to ETH Speed value */ + /* Set the DO bit according to ETH ReceiveOwn value */ + /* Set the LM bit according to ETH LoopbackMode value */ + /* Set the DM bit according to ETH Mode value */ + /* Set the IPCO bit according to ETH ChecksumOffload value */ + /* Set the DR bit according to ETH RetryTransmission value */ + /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */ + /* Set the BL bit according to ETH BackOffLimit value */ + /* Set the DC bit according to ETH DeferralCheck value */ + tmpreg |= (uint32_t)(macinit.Watchdog | + macinit.Jabber | + macinit.InterFrameGap | + macinit.CarrierSense | + heth->Init.Speed | + macinit.ReceiveOwn | + macinit.LoopbackMode | + heth->Init.DuplexMode | + macinit.ChecksumOffload | + macinit.RetryTransmission | + macinit.AutomaticPadCRCStrip | + macinit.BackOffLimit | + macinit.DeferralCheck); + + /* Write to ETHERNET MACCR */ + prvWriteMACCR( heth, tmpreg ); + + /*----------------------- ETHERNET MACFFR Configuration --------------------*/ + /* Set the RA bit according to ETH ReceiveAll value */ + /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */ + /* Set the PCF bit according to ETH PassControlFrames value */ + /* Set the DBF bit according to ETH BroadcastFramesReception value */ + /* Set the DAIF bit according to ETH DestinationAddrFilter value */ + /* Set the PR bit according to ETH PromiscuousMode value */ + /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */ + /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */ + /* Write to ETHERNET MACFFR */ + heth->Instance->MACFFR = (uint32_t)(macinit.ReceiveAll | + macinit.SourceAddrFilter | + macinit.PassControlFrames | + macinit.BroadcastFramesReception | + macinit.DestinationAddrFilter | + macinit.PromiscuousMode | + macinit.MulticastFramesFilter | + macinit.UnicastFramesFilter); + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg = heth->Instance->MACFFR; + HAL_Delay(ETH_REG_WRITE_DELAY); + heth->Instance->MACFFR = tmpreg; + + /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/ + /* Write to ETHERNET MACHTHR */ + heth->Instance->MACHTHR = (uint32_t)macinit.HashTableHigh; + + /* Write to ETHERNET MACHTLR */ + heth->Instance->MACHTLR = (uint32_t)macinit.HashTableLow; + /*----------------------- ETHERNET MACFCR Configuration -------------------*/ + + /* Get the ETHERNET MACFCR value */ + tmpreg = heth->Instance->MACFCR; + /* Clear xx bits */ + tmpreg &= ETH_MACFCR_CLEAR_MASK; + + /* Set the PT bit according to ETH PauseTime value */ + /* Set the DZPQ bit according to ETH ZeroQuantaPause value */ + /* Set the PLT bit according to ETH PauseLowThreshold value */ + /* Set the UP bit according to ETH UnicastPauseFrameDetect value */ + /* Set the RFE bit according to ETH ReceiveFlowControl value */ + /* Set the TFE bit according to ETH TransmitFlowControl value */ + tmpreg |= (uint32_t)((macinit.PauseTime << 16) | + macinit.ZeroQuantaPause | + macinit.PauseLowThreshold | + macinit.UnicastPauseFrameDetect | + macinit.ReceiveFlowControl | + macinit.TransmitFlowControl); + + /* Write to ETHERNET MACFCR */ + prvWriteMACFCR( heth, tmpreg ); + + /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/ + /* Set the ETV bit according to ETH VLANTagComparison value */ + /* Set the VL bit according to ETH VLANTagIdentifier value */ + heth->Instance->MACVLANTR = (uint32_t)(macinit.VLANTagComparison | + macinit.VLANTagIdentifier); + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg = heth->Instance->MACVLANTR; + HAL_Delay(ETH_REG_WRITE_DELAY); + heth->Instance->MACVLANTR = tmpreg; + + /* Ethernet DMA default initialization ************************************/ + dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE; + dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE; + dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE; + dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE; + dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES; + dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE; + dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE; + dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES; + dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE; + dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE; + dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE; + dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; + dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; + dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE; + dmainit.DescriptorSkipLength = 0x0; + dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; + + /* Get the ETHERNET DMAOMR value */ + tmpreg = heth->Instance->DMAOMR; + /* Clear xx bits */ + tmpreg &= ETH_DMAOMR_CLEAR_MASK; + + /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */ + /* Set the RSF bit according to ETH ReceiveStoreForward value */ + /* Set the DFF bit according to ETH FlushReceivedFrame value */ + /* Set the TSF bit according to ETH TransmitStoreForward value */ + /* Set the TTC bit according to ETH TransmitThresholdControl value */ + /* Set the FEF bit according to ETH ForwardErrorFrames value */ + /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */ + /* Set the RTC bit according to ETH ReceiveThresholdControl value */ + /* Set the OSF bit according to ETH SecondFrameOperate value */ + tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | + dmainit.ReceiveStoreForward | + dmainit.FlushReceivedFrame | + dmainit.TransmitStoreForward | + dmainit.TransmitThresholdControl | + dmainit.ForwardErrorFrames | + dmainit.ForwardUndersizedGoodFrames | + dmainit.ReceiveThresholdControl | + dmainit.SecondFrameOperate); + + /* Write to ETHERNET DMAOMR */ + prvWriteDMAOMR( heth, tmpreg ); + + /*----------------------- ETHERNET DMABMR Configuration ------------------*/ + /* Set the AAL bit according to ETH AddressAlignedBeats value */ + /* Set the FB bit according to ETH FixedBurst value */ + /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */ + /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */ + /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/ + /* Set the DSL bit according to ETH DesciptorSkipLength value */ + /* Set the PR and DA bits according to ETH DMAArbitration value */ + heth->Instance->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats | + dmainit.FixedBurst | + dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ + dmainit.TxDMABurstLength | + dmainit.EnhancedDescriptorFormat | + (dmainit.DescriptorSkipLength << 2) | + dmainit.DMAArbitration | + ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg = heth->Instance->DMABMR; + HAL_Delay(ETH_REG_WRITE_DELAY); + heth->Instance->DMABMR = tmpreg; + + if(heth->Init.RxMode == ETH_RXINTERRUPT_MODE) + { + /* Enable the Ethernet Rx Interrupt */ + __HAL_ETH_DMA_ENABLE_IT(( heth ), ETH_DMA_IT_NIS | ETH_DMA_IT_R); + } + + /* Initialize MAC address in ethernet MAC */ + ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr); +} + +/** + * @brief Configures the selected MAC address. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param MacAddr: The MAC address to configure + * This parameter can be one of the following values: + * @arg ETH_MAC_Address0: MAC Address0 + * @arg ETH_MAC_Address1: MAC Address1 + * @arg ETH_MAC_Address2: MAC Address2 + * @arg ETH_MAC_Address3: MAC Address3 + * @param Addr: Pointer to MAC address buffer data (6 bytes) + * @retval HAL status + */ +static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param( IS_ETH_MAC_ADDRESS0123( MacAddr ) ); + + /* Calculate the selected MAC address high register */ + tmpreg = 0x80000000ul | ( ( uint32_t )Addr[ 5 ] << 8) | (uint32_t)Addr[ 4 ]; + /* Load the selected MAC address high register */ + ( * ( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_HBASE + MacAddr ) ) ) = tmpreg; + /* Calculate the selected MAC address low register */ + tmpreg = ( ( uint32_t )Addr[ 3 ] << 24 ) | ( ( uint32_t )Addr[ 2 ] << 16 ) | ( ( uint32_t )Addr[ 1 ] << 8 ) | Addr[ 0 ]; + + /* Load the selected MAC address low register */ + ( * ( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_LBASE + MacAddr ) ) ) = tmpreg; +} + +/** + * @brief Enables the MAC transmission. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth) +{ + uint32_t tmpreg = heth->Instance->MACCR | ETH_MACCR_TE; + + prvWriteMACCR( heth, tmpreg ); +} + +/** + * @brief Disables the MAC transmission. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth) +{ + uint32_t tmpreg = heth->Instance->MACCR & ~( ETH_MACCR_TE ); + + prvWriteMACCR( heth, tmpreg ); +} + +/** + * @brief Enables the MAC reception. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth) +{ + __IO uint32_t tmpreg = heth->Instance->MACCR | ETH_MACCR_RE; + + prvWriteMACCR( heth, tmpreg ); +} + +/** + * @brief Disables the MAC reception. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth) +{ + __IO uint32_t tmpreg = heth->Instance->MACCR & ~( ETH_MACCR_RE ); + + prvWriteMACCR( heth, tmpreg ); +} + +/** + * @brief Enables the DMA transmission. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth) +{ + /* Enable the DMA transmission */ + __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_ST; + + prvWriteDMAOMR( heth, tmpreg ); +} + +/** + * @brief Disables the DMA transmission. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth) +{ + /* Disable the DMA transmission */ + __IO uint32_t tmpreg = heth->Instance->DMAOMR & ~( ETH_DMAOMR_ST ); + + prvWriteDMAOMR( heth, tmpreg ); +} + +/** + * @brief Enables the DMA reception. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth) +{ + /* Enable the DMA reception */ + __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_SR; + + prvWriteDMAOMR( heth, tmpreg ); +} + +/** + * @brief Disables the DMA reception. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth) +{ + /* Disable the DMA reception */ + __IO uint32_t tmpreg = heth->Instance->DMAOMR & ~( ETH_DMAOMR_SR ); + + prvWriteDMAOMR( heth, tmpreg ); +} + +/** + * @brief Clears the ETHERNET transmit FIFO. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth) +{ + /* Set the Flush Transmit FIFO bit */ + __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_FTF; + + prvWriteDMAOMR( heth, tmpreg ); +} + +/** + * @} + */ + +#endif /* STM32F7xx */ +#endif /* HAL_ETH_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32F7xx/stm32f7xx_hal_eth.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32F7xx/stm32f7xx_hal_eth.h new file mode 100644 index 0000000..0c40193 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32F7xx/stm32f7xx_hal_eth.h @@ -0,0 +1,2214 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_eth.h + * @author MCD Application Team + * @version V1.2.2 + * @date 14-April-2017 + * @brief Header file of ETH HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_ETH_H +#define __STM32F7xx_HAL_ETH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup ETH + * @{ + */ + +/** @addtogroup ETH_Private_Macros + * @{ + */ +#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20) +#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \ + ((CMD) == ETH_AUTONEGOTIATION_DISABLE)) +#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ + ((SPEED) == ETH_SPEED_100M)) +#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \ + ((MODE) == ETH_MODE_HALFDUPLEX)) +#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ + ((MODE) == ETH_RXINTERRUPT_MODE)) +#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \ + ((MODE) == ETH_CHECKSUM_BY_SOFTWARE)) +#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \ + ((MODE) == ETH_MEDIA_INTERFACE_RMII)) +#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \ + ((CMD) == ETH_WATCHDOG_DISABLE)) +#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \ + ((CMD) == ETH_JABBER_DISABLE)) +#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \ + ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \ + ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \ + ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \ + ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \ + ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \ + ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \ + ((GAP) == ETH_INTERFRAMEGAP_40BIT)) +#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \ + ((CMD) == ETH_CARRIERSENCE_DISABLE)) +#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \ + ((CMD) == ETH_RECEIVEOWN_DISABLE)) +#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \ + ((CMD) == ETH_LOOPBACKMODE_DISABLE)) +#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \ + ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE)) +#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \ + ((CMD) == ETH_RETRYTRANSMISSION_DISABLE)) +#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \ + ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE)) +#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \ + ((LIMIT) == ETH_BACKOFFLIMIT_8) || \ + ((LIMIT) == ETH_BACKOFFLIMIT_4) || \ + ((LIMIT) == ETH_BACKOFFLIMIT_1)) +#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \ + ((CMD) == ETH_DEFFERRALCHECK_DISABLE)) +#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \ + ((CMD) == ETH_RECEIVEAll_DISABLE)) +#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \ + ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \ + ((CMD) == ETH_SOURCEADDRFILTER_DISABLE)) +#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \ + ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \ + ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER)) +#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \ + ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE)) +#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \ + ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE)) +#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \ + ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE)) +#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \ + ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \ + ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \ + ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE)) +#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \ + ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \ + ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT)) +#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF) +#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \ + ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE)) +#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \ + ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \ + ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \ + ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256)) +#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \ + ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE)) +#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \ + ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE)) +#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \ + ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE)) +#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \ + ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT)) +#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF) +#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \ + ((ADDRESS) == ETH_MAC_ADDRESS1) || \ + ((ADDRESS) == ETH_MAC_ADDRESS2) || \ + ((ADDRESS) == ETH_MAC_ADDRESS3)) +#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \ + ((ADDRESS) == ETH_MAC_ADDRESS2) || \ + ((ADDRESS) == ETH_MAC_ADDRESS3)) +#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \ + ((FILTER) == ETH_MAC_ADDRESSFILTER_DA)) +#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \ + ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \ + ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \ + ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \ + ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \ + ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1)) +#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \ + ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE)) +#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \ + ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE)) +#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \ + ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE)) +#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \ + ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE)) +#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \ + ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \ + ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \ + ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \ + ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \ + ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \ + ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \ + ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES)) +#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \ + ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE)) +#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \ + ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE)) +#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \ + ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \ + ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \ + ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES)) +#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \ + ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE)) +#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \ + ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE)) +#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \ + ((CMD) == ETH_FIXEDBURST_DISABLE)) +#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT)) +#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT)) +#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F) +#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \ + ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \ + ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \ + ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \ + ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX)) +#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \ + ((FLAG) == ETH_DMATXDESC_IC) || \ + ((FLAG) == ETH_DMATXDESC_LS) || \ + ((FLAG) == ETH_DMATXDESC_FS) || \ + ((FLAG) == ETH_DMATXDESC_DC) || \ + ((FLAG) == ETH_DMATXDESC_DP) || \ + ((FLAG) == ETH_DMATXDESC_TTSE) || \ + ((FLAG) == ETH_DMATXDESC_TER) || \ + ((FLAG) == ETH_DMATXDESC_TCH) || \ + ((FLAG) == ETH_DMATXDESC_TTSS) || \ + ((FLAG) == ETH_DMATXDESC_IHE) || \ + ((FLAG) == ETH_DMATXDESC_ES) || \ + ((FLAG) == ETH_DMATXDESC_JT) || \ + ((FLAG) == ETH_DMATXDESC_FF) || \ + ((FLAG) == ETH_DMATXDESC_PCE) || \ + ((FLAG) == ETH_DMATXDESC_LCA) || \ + ((FLAG) == ETH_DMATXDESC_NC) || \ + ((FLAG) == ETH_DMATXDESC_LCO) || \ + ((FLAG) == ETH_DMATXDESC_EC) || \ + ((FLAG) == ETH_DMATXDESC_VF) || \ + ((FLAG) == ETH_DMATXDESC_CC) || \ + ((FLAG) == ETH_DMATXDESC_ED) || \ + ((FLAG) == ETH_DMATXDESC_UF) || \ + ((FLAG) == ETH_DMATXDESC_DB)) +#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \ + ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT)) +#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \ + ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \ + ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \ + ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL)) +#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF) +#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \ + ((FLAG) == ETH_DMARXDESC_AFM) || \ + ((FLAG) == ETH_DMARXDESC_ES) || \ + ((FLAG) == ETH_DMARXDESC_DE) || \ + ((FLAG) == ETH_DMARXDESC_SAF) || \ + ((FLAG) == ETH_DMARXDESC_LE) || \ + ((FLAG) == ETH_DMARXDESC_OE) || \ + ((FLAG) == ETH_DMARXDESC_VLAN) || \ + ((FLAG) == ETH_DMARXDESC_FS) || \ + ((FLAG) == ETH_DMARXDESC_LS) || \ + ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \ + ((FLAG) == ETH_DMARXDESC_LC) || \ + ((FLAG) == ETH_DMARXDESC_FT) || \ + ((FLAG) == ETH_DMARXDESC_RWT) || \ + ((FLAG) == ETH_DMARXDESC_RE) || \ + ((FLAG) == ETH_DMARXDESC_DBE) || \ + ((FLAG) == ETH_DMARXDESC_CE) || \ + ((FLAG) == ETH_DMARXDESC_MAMPCE)) +#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \ + ((BUFFER) == ETH_DMARXDESC_BUFFER2)) +#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ + ((FLAG) == ETH_PMT_FLAG_MPR)) +#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00)) +#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ + ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \ + ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \ + ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ + ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ + ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ + ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ + ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ + ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ + ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ + ((FLAG) == ETH_DMA_FLAG_T)) +#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00)) +#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ + ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ + ((IT) == ETH_MAC_IT_PMT)) +#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ + ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ + ((FLAG) == ETH_MAC_FLAG_PMT)) +#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00)) +#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ + ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ + ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ + ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ + ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ + ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ + ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ + ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ + ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) +#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \ + ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER)) +#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \ + ((IT) != 0x00)) +#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ + ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ + ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) +#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \ + ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE)) + + +/** + * @} + */ + +/** @addtogroup ETH_Private_Defines + * @{ + */ +/* Delay to wait when writing to some Ethernet registers */ +#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001U) + +/* Ethernet Errors */ +#define ETH_SUCCESS ((uint32_t)0U) +#define ETH_ERROR ((uint32_t)1U) + +/* Ethernet DMA Tx descriptors Collision Count Shift */ +#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3U) + +/* Ethernet DMA Tx descriptors Buffer2 Size Shift */ +#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U) + +/* Ethernet DMA Rx descriptors Frame Length Shift */ +#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16U) + +/* Ethernet DMA Rx descriptors Buffer2 Size Shift */ +#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U) + +/* Ethernet DMA Rx descriptors Frame length Shift */ +#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16) + +/* Ethernet MAC address offsets */ +#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40U) /* Ethernet MAC address high offset */ +#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44U) /* Ethernet MAC address low offset */ + +/* Ethernet MACMIIAR register Mask */ +#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3U) + +/* Ethernet MACCR register Mask */ +#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810FU) + +/* Ethernet MACFCR register Mask */ +#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41U) + +/* Ethernet DMAOMR register Mask */ +#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23U) + +/* Ethernet Remote Wake-up frame register length */ +#define ETH_WAKEUP_REGISTER_LENGTH 8U + +/* Ethernet Missed frames counter Shift */ +#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U + /** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ETH_Exported_Types ETH Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ + HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ + HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ + HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */ + HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */ + HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +}HAL_ETH_StateTypeDef; + +/** + * @brief ETH Init Structure definition + */ + +typedef struct +{ + uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY + The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) + and the mode (half/full-duplex). + This parameter can be a value of @ref ETH_AutoNegotiation */ + + uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. + This parameter can be a value of @ref ETH_Speed */ + + uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode + This parameter can be a value of @ref ETH_Duplex_Mode */ + + uint16_t PhyAddress; /*!< Ethernet PHY address. + This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ + + uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ + + uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode. + This parameter can be a value of @ref ETH_Rx_Mode */ + + uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software. + This parameter can be a value of @ref ETH_Checksum_Mode */ + + uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface. + This parameter can be a value of @ref ETH_Media_Interface */ + +} ETH_InitTypeDef; + + + /** + * @brief ETH MAC Configuration Structure definition + */ + +typedef struct +{ + uint32_t Watchdog; /*!< Selects or not the Watchdog timer + When enabled, the MAC allows no more then 2048 bytes to be received. + When disabled, the MAC can receive up to 16384 bytes. + This parameter can be a value of @ref ETH_Watchdog */ + + uint32_t Jabber; /*!< Selects or not Jabber timer + When enabled, the MAC allows no more then 2048 bytes to be sent. + When disabled, the MAC can send up to 16384 bytes. + This parameter can be a value of @ref ETH_Jabber */ + + uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission. + This parameter can be a value of @ref ETH_Inter_Frame_Gap */ + + uint32_t CarrierSense; /*!< Selects or not the Carrier Sense. + This parameter can be a value of @ref ETH_Carrier_Sense */ + + uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn, + ReceiveOwn allows the reception of frames when the TX_EN signal is asserted + in Half-Duplex mode. + This parameter can be a value of @ref ETH_Receive_Own */ + + uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode. + This parameter can be a value of @ref ETH_Loop_Back_Mode */ + + uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. + This parameter can be a value of @ref ETH_Checksum_Offload */ + + uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, + when a collision occurs (Half-Duplex mode). + This parameter can be a value of @ref ETH_Retry_Transmission */ + + uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping. + This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ + + uint32_t BackOffLimit; /*!< Selects the BackOff limit value. + This parameter can be a value of @ref ETH_Back_Off_Limit */ + + uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode). + This parameter can be a value of @ref ETH_Deferral_Check */ + + uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering). + This parameter can be a value of @ref ETH_Receive_All */ + + uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. + This parameter can be a value of @ref ETH_Source_Addr_Filter */ + + uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) + This parameter can be a value of @ref ETH_Pass_Control_Frames */ + + uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames. + This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ + + uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames. + This parameter can be a value of @ref ETH_Destination_Addr_Filter */ + + uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode + This parameter can be a value of @ref ETH_Promiscuous_Mode */ + + uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter. + This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ + + uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter. + This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ + + uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ + + uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ + + uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ + + uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames. + This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ + + uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for + automatic retransmission of PAUSE Frame. + This parameter can be a value of @ref ETH_Pause_Low_Threshold */ + + uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 + unicast address and unique multicast address). + This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ + + uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and + disable its transmitter for a specified time (Pause Time) + This parameter can be a value of @ref ETH_Receive_Flow_Control */ + + uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) + or the MAC back-pressure operation (Half-Duplex mode) + This parameter can be a value of @ref ETH_Transmit_Flow_Control */ + + uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for + comparison and filtering. + This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ + + uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ + +} ETH_MACInitTypeDef; + + +/** + * @brief ETH DMA Configuration Structure definition + */ + +typedef struct +{ + uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames. + This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ + + uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode. + This parameter can be a value of @ref ETH_Receive_Store_Forward */ + + uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames. + This parameter can be a value of @ref ETH_Flush_Received_Frame */ + + uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode. + This parameter can be a value of @ref ETH_Transmit_Store_Forward */ + + uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control. + This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ + + uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames. + This parameter can be a value of @ref ETH_Forward_Error_Frames */ + + uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error + and length less than 64 bytes) including pad-bytes and CRC) + This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ + + uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO. + This parameter can be a value of @ref ETH_Receive_Threshold_Control */ + + uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second + frame of Transmit data even before obtaining the status for the first frame. + This parameter can be a value of @ref ETH_Second_Frame_Operate */ + + uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats. + This parameter can be a value of @ref ETH_Address_Aligned_Beats */ + + uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers. + This parameter can be a value of @ref ETH_Fixed_Burst */ + + uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. + This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ + + uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. + This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ + + uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format. + This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */ + + uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) + This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ + + uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration. + This parameter can be a value of @ref ETH_DMA_Arbitration */ +} ETH_DMAInitTypeDef; + + +/** + * @brief ETH DMA Descriptors data structure definition + */ + +typedef struct +{ + __IO uint32_t Status; /*!< Status */ + + uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ + + uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ + + uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ + + /*!< Enhanced Ethernet DMA PTP Descriptors */ + uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */ + + uint32_t Reserved1; /*!< Reserved */ + + uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */ + + uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */ + +} ETH_DMADescTypeDef; + + +/** + * @brief Received Frame Informations structure definition + */ +typedef struct +{ + ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */ + + ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */ + + uint32_t SegCount; /*!< Segment count */ + + uint32_t length; /*!< Frame length */ + + uint32_t buffer; /*!< Frame buffer */ + +} ETH_DMARxFrameInfos; + + +/** + * @brief ETH Handle Structure definition + */ + +typedef struct +{ + ETH_TypeDef *Instance; /*!< Register base address */ + + ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ + + uint32_t LinkStatus; /*!< Ethernet link status */ + + ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */ + + ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */ + + ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */ + + __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */ + + HAL_LockTypeDef Lock; /*!< ETH Lock */ + +} ETH_HandleTypeDef; + + /** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ETH_Exported_Constants ETH Exported Constants + * @{ + */ + +/** @defgroup ETH_Buffers_setting ETH Buffers setting + * @{ + */ +#define ETH_MAX_PACKET_SIZE ((uint32_t)1524U) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC ((uint32_t)4U) /*!< Ethernet CRC */ +#define ETH_EXTRA ((uint32_t)2U) /*!< Extra bytes in some cases */ +#define ETH_VLAN_TAG ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */ +#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46U) /*!< Minimum Ethernet payload size */ +#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500U) /*!< Maximum Ethernet payload size */ +#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U) /*!< Jumbo frame payload size */ + + /* Ethernet driver receive buffers are organized in a chained linked-list, when + an Ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO + to the driver receive buffers memory. + + Depending on the size of the received Ethernet packet and the size of + each Ethernet driver receive buffer, the received packet can take one or more + Ethernet driver receive buffer. + + In below are defined the size of one Ethernet driver receive buffer ETH_RX_BUF_SIZE + and the total count of the driver receive buffers ETH_RXBUFNB. + + The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as + example, they can be reconfigured in the application layer to fit the application + needs */ + +/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet + packet */ +#ifndef ETH_RX_BUF_SIZE + #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE +#endif + +/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ +#ifndef ETH_RXBUFNB + #define ETH_RXBUFNB ((uint32_t)5U) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ +#endif + + + /* Ethernet driver transmit buffers are organized in a chained linked-list, when + an Ethernet packet is transmitted, Tx-DMA will transfer the packet from the + driver transmit buffers memory to the TxFIFO. + + Depending on the size of the Ethernet packet to be transmitted and the size of + each Ethernet driver transmit buffer, the packet to be transmitted can take + one or more Ethernet driver transmit buffer. + + In below are defined the size of one Ethernet driver transmit buffer ETH_TX_BUF_SIZE + and the total count of the driver transmit buffers ETH_TXBUFNB. + + The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as + example, they can be reconfigured in the application layer to fit the application + needs */ + +/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet + packet */ +#ifndef ETH_TX_BUF_SIZE + #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE +#endif + +/* 5 Ethernet driver transmit buffers are used (in a chained linked list)*/ +#ifndef ETH_TXBUFNB + #define ETH_TXBUFNB ((uint32_t)5U) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ +#endif + + /** + * @} + */ + +/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor + * @{ + */ + +/* + DMA Tx Descriptor + ----------------------------------------------------------------------------------------------- + TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | + ----------------------------------------------------------------------------------------------- + TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | + ----------------------------------------------------------------------------------------------- + TDES2 | Buffer1 Address [31:0] | + ----------------------------------------------------------------------------------------------- + TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | + ----------------------------------------------------------------------------------------------- +*/ + +/** + * @brief Bit definition of TDES0 register: DMA Tx descriptor status register + */ +#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATXDESC_IC ((uint32_t)0x40000000U) /*!< Interrupt on Completion */ +#define ETH_DMATXDESC_LS ((uint32_t)0x20000000U) /*!< Last Segment */ +#define ETH_DMATXDESC_FS ((uint32_t)0x10000000U) /*!< First Segment */ +#define ETH_DMATXDESC_DC ((uint32_t)0x08000000U) /*!< Disable CRC */ +#define ETH_DMATXDESC_DP ((uint32_t)0x04000000U) /*!< Disable Padding */ +#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000U) /*!< Transmit Time Stamp Enable */ +#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000U) /*!< Checksum Insertion Control: 4 cases */ +#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000U) /*!< Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000U) /*!< IPV4 header Checksum Insertion */ +#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000U) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000U) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATXDESC_TER ((uint32_t)0x00200000U) /*!< Transmit End of Ring */ +#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000U) /*!< Second Address Chained */ +#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000U) /*!< Tx Time Stamp Status */ +#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000U) /*!< IP Header Error */ +#define ETH_DMATXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ +#define ETH_DMATXDESC_JT ((uint32_t)0x00004000U) /*!< Jabber Timeout */ +#define ETH_DMATXDESC_FF ((uint32_t)0x00002000U) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000U) /*!< Payload Checksum Error */ +#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800U) /*!< Loss of Carrier: carrier lost during transmission */ +#define ETH_DMATXDESC_NC ((uint32_t)0x00000400U) /*!< No Carrier: no carrier signal from the transceiver */ +#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200U) /*!< Late Collision: transmission aborted due to collision */ +#define ETH_DMATXDESC_EC ((uint32_t)0x00000100U) /*!< Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATXDESC_VF ((uint32_t)0x00000080U) /*!< VLAN Frame */ +#define ETH_DMATXDESC_CC ((uint32_t)0x00000078U) /*!< Collision Count */ +#define ETH_DMATXDESC_ED ((uint32_t)0x00000004U) /*!< Excessive Deferral */ +#define ETH_DMATXDESC_UF ((uint32_t)0x00000002U) /*!< Underflow Error: late data arrival from the memory */ +#define ETH_DMATXDESC_DB ((uint32_t)0x00000001U) /*!< Deferred Bit */ + +/** + * @brief Bit definition of TDES1 register + */ +#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000U) /*!< Transmit Buffer2 Size */ +#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFFU) /*!< Transmit Buffer1 Size */ + +/** + * @brief Bit definition of TDES2 register + */ +#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of TDES3 register + */ +#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */ + + /*--------------------------------------------------------------------------------------------- + TDES6 | Transmit Time Stamp Low [31:0] | + ----------------------------------------------------------------------------------------------- + TDES7 | Transmit Time Stamp High [31:0] | + ----------------------------------------------------------------------------------------------*/ + +/* Bit definition of TDES6 register */ + #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp Low */ + +/* Bit definition of TDES7 register */ + #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp High */ + +/** + * @} + */ +/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor + * @{ + */ + +/* + DMA Rx Descriptor + -------------------------------------------------------------------------------------------------------------------- + RDES0 | OWN(31) | Status [30:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES2 | Buffer1 Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- +*/ + +/** + * @brief Bit definition of RDES0 register: DMA Rx descriptor status register + */ +#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000U) /*!< DA Filter Fail for the rx frame */ +#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000U) /*!< Receive descriptor frame length */ +#define ETH_DMARXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMARXDESC_DE ((uint32_t)0x00004000U) /*!< Descriptor error: no more descriptors for receive frame */ +#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000U) /*!< SA Filter Fail for the received frame */ +#define ETH_DMARXDESC_LE ((uint32_t)0x00001000U) /*!< Frame size not matching with length field */ +#define ETH_DMARXDESC_OE ((uint32_t)0x00000800U) /*!< Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400U) /*!< VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARXDESC_FS ((uint32_t)0x00000200U) /*!< First descriptor of the frame */ +#define ETH_DMARXDESC_LS ((uint32_t)0x00000100U) /*!< Last descriptor of the frame */ +#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080U) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ +#define ETH_DMARXDESC_LC ((uint32_t)0x00000040U) /*!< Late collision occurred during reception */ +#define ETH_DMARXDESC_FT ((uint32_t)0x00000020U) /*!< Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010U) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMARXDESC_RE ((uint32_t)0x00000008U) /*!< Receive error: error reported by MII interface */ +#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004U) /*!< Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARXDESC_CE ((uint32_t)0x00000002U) /*!< CRC error */ +#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001U) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ + +/** + * @brief Bit definition of RDES1 register + */ +#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000U) /*!< Disable Interrupt on Completion */ +#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000U) /*!< Receive Buffer2 Size */ +#define ETH_DMARXDESC_RER ((uint32_t)0x00008000U) /*!< Receive End of Ring */ +#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000U) /*!< Second Address Chained */ +#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFFU) /*!< Receive Buffer1 Size */ + +/** + * @brief Bit definition of RDES2 register + */ +#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of RDES3 register + */ +#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */ + +/*--------------------------------------------------------------------------------------------------------------------- + RDES4 | Reserved[31:15] | Extended Status [14:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES5 | Reserved[31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES6 | Receive Time Stamp Low [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES7 | Receive Time Stamp High [31:0] | + --------------------------------------------------------------------------------------------------------------------*/ + +/* Bit definition of RDES4 register */ +#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000U) /* PTP Version */ +#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000U) /* PTP Frame Type */ +#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00U) /* PTP Message Type */ +#define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100U) /* SYNC message (all clock types) */ +#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200U) /* FollowUp message (all clock types) */ +#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300U) /* DelayReq message (all clock types) */ +#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400U) /* DelayResp message (all clock types) */ +#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500U) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ +#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600U) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ +#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700U) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ +#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080U) /* IPv6 Packet Received */ +#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040U) /* IPv4 Packet Received */ +#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020U) /* IP Checksum Bypassed */ +#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010U) /* IP Payload Error */ +#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008U) /* IP Header Error */ +#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007U) /* IP Payload Type */ +#define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001U) /* UDP payload encapsulated in the IP datagram */ +#define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002U) /* TCP payload encapsulated in the IP datagram */ +#define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003U) /* ICMP payload encapsulated in the IP datagram */ + +/* Bit definition of RDES6 register */ +#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp Low */ + +/* Bit definition of RDES7 register */ +#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp High */ +/** + * @} + */ + /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation + * @{ + */ +#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001U) +#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000U) + +/** + * @} + */ +/** @defgroup ETH_Speed ETH Speed + * @{ + */ +#define ETH_SPEED_10M ((uint32_t)0x00000000U) +#define ETH_SPEED_100M ((uint32_t)0x00004000U) + +/** + * @} + */ +/** @defgroup ETH_Duplex_Mode ETH Duplex Mode + * @{ + */ +#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800U) +#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000U) +/** + * @} + */ +/** @defgroup ETH_Rx_Mode ETH Rx Mode + * @{ + */ +#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000U) +#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001U) +/** + * @} + */ + +/** @defgroup ETH_Checksum_Mode ETH Checksum Mode + * @{ + */ +#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000U) +#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001U) +/** + * @} + */ + +/** @defgroup ETH_Media_Interface ETH Media Interface + * @{ + */ +#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000U) +#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL) +/** + * @} + */ + +/** @defgroup ETH_Watchdog ETH Watchdog + * @{ + */ +#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000U) +#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000U) +/** + * @} + */ + +/** @defgroup ETH_Jabber ETH Jabber + * @{ + */ +#define ETH_JABBER_ENABLE ((uint32_t)0x00000000U) +#define ETH_JABBER_DISABLE ((uint32_t)0x00400000U) +/** + * @} + */ + +/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap + * @{ + */ +#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000U) /*!< minimum IFG between frames during transmission is 96Bit */ +#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000U) /*!< minimum IFG between frames during transmission is 88Bit */ +#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000U) /*!< minimum IFG between frames during transmission is 80Bit */ +#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000U) /*!< minimum IFG between frames during transmission is 72Bit */ +#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000U) /*!< minimum IFG between frames during transmission is 64Bit */ +#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000U) /*!< minimum IFG between frames during transmission is 56Bit */ +#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000U) /*!< minimum IFG between frames during transmission is 48Bit */ +#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000U) /*!< minimum IFG between frames during transmission is 40Bit */ +/** + * @} + */ + +/** @defgroup ETH_Carrier_Sense ETH Carrier Sense + * @{ + */ +#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000U) +#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000U) +/** + * @} + */ + +/** @defgroup ETH_Receive_Own ETH Receive Own + * @{ + */ +#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U) +#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000U) +/** + * @} + */ + +/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode + * @{ + */ +#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000U) +#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup ETH_Checksum_Offload ETH Checksum Offload + * @{ + */ +#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400U) +#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup ETH_Retry_Transmission ETH Retry Transmission + * @{ + */ +#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U) +#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200U) +/** + * @} + */ + +/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip + * @{ + */ +#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080U) +#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit + * @{ + */ +#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000U) +#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020U) +#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040U) +#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060U) +/** + * @} + */ + +/** @defgroup ETH_Deferral_Check ETH Deferral Check + * @{ + */ +#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010U) +#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup ETH_Receive_All ETH Receive All + * @{ + */ +#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000U) +#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter + * @{ + */ +#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200U) +#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300U) +#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames + * @{ + */ +#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040U) /*!< MAC filters all control frames from reaching the application */ +#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080U) /*!< MAC forwards all control frames to application even if they fail the Address Filter */ +#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0U) /*!< MAC forwards control frames that pass the Address Filter. */ +/** + * @} + */ + +/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception + * @{ + */ +#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000U) +#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020U) +/** + * @} + */ + +/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter + * @{ + */ +#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000U) +#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008U) +/** + * @} + */ + +/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode + * @{ + */ +#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001U) +#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter + * @{ + */ +#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404U) +#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004U) +#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U) +#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010U) +/** + * @} + */ + +/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter + * @{ + */ +#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402U) +#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002U) +#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause + * @{ + */ +#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000U) +#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080U) +/** + * @} + */ + +/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold + * @{ + */ +#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000U) /*!< Pause time minus 4 slot times */ +#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010U) /*!< Pause time minus 28 slot times */ +#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020U) /*!< Pause time minus 144 slot times */ +#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030U) /*!< Pause time minus 256 slot times */ +/** + * @} + */ + +/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect + * @{ + */ +#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008U) +#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control + * @{ + */ +#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004U) +#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control + * @{ + */ +#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002U) +#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison + * @{ + */ +#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000U) +#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses ETH MAC addresses + * @{ + */ +#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U) +#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U) +#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U) +#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U) +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA + * @{ + */ +#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000U) +#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008U) +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes + * @{ + */ +#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000U) /*!< Mask MAC Address high reg bits [15:8] */ +#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000U) /*!< Mask MAC Address high reg bits [7:0] */ +#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000U) /*!< Mask MAC Address low reg bits [31:24] */ +#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000U) /*!< Mask MAC Address low reg bits [23:16] */ +#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000U) /*!< Mask MAC Address low reg bits [15:8] */ +#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000U) /*!< Mask MAC Address low reg bits [70] */ +/** + * @} + */ + +/** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags + * @{ + */ +#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */ +#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */ +/** + * @} + */ + +/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame + * @{ + */ +#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000U) +#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000U) +/** + * @} + */ + +/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward + * @{ + */ +#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000U) +#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame + * @{ + */ +#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000U) +#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000U) +/** + * @} + */ + +/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward + * @{ + */ +#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000U) +#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control + * @{ + */ +#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000U) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000U) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000U) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000U) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000U) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000U) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000U) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ +/** + * @} + */ + +/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames + * @{ + */ +#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080U) +#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames + * @{ + */ +#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040U) +#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control + * @{ + */ +#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ +#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008U) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ +#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010U) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ +#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018U) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ +/** + * @} + */ + +/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate + * @{ + */ +#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004U) +#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats + * @{ + */ +#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000U) +#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup ETH_Fixed_Burst ETH Fixed Burst + * @{ + */ +#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000U) +#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length + * @{ + */ +#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ +/** + * @} + */ + +/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length + * @{ + */ +#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +/** + * @} + */ + +/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format + * @{ + */ +#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080U) +#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration + * @{ + */ +#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000U) +#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000U) +#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000U) +#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000U) +#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002U) +/** + * @} + */ + +/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment + * @{ + */ +#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000U) /*!< Last Segment */ +#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000U) /*!< First Segment */ +/** + * @} + */ + +/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control + * @{ + */ +#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000U) /*!< Checksum engine bypass */ +#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000U) /*!< IPv4 header checksum insertion */ +#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000U) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ +#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000U) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ +/** + * @} + */ + +/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers + * @{ + */ +#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000U) /*!< DMA Rx Desc Buffer1 */ +#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001U) /*!< DMA Rx Desc Buffer2 */ +/** + * @} + */ + +/** @defgroup ETH_PMT_Flags ETH PMT Flags + * @{ + */ +#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000U) /*!< Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040U) /*!< Wake-Up Frame Received */ +#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020U) /*!< Magic Packet Received */ +/** + * @} + */ + +/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts + * @{ + */ +#define ETH_MMC_IT_TGF ((uint32_t)0x00200000U) /*!< When Tx good frame counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000U) /*!< When Tx good multi col counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000U) /*!< When Tx good single col counter reaches half the maximum value */ +/** + * @} + */ + +/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts + * @{ + */ +#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000U) /*!< When Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040U) /*!< When Rx alignment error counter reaches half the maximum value */ +#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020U) /*!< When Rx crc error counter reaches half the maximum value */ +/** + * @} + */ + +/** @defgroup ETH_MAC_Flags ETH MAC Flags + * @{ + */ +#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200U) /*!< Time stamp trigger flag (on MAC) */ +#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040U) /*!< MMC transmit flag */ +#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020U) /*!< MMC receive flag */ +#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010U) /*!< MMC flag (on MAC) */ +#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008U) /*!< PMT flag (on MAC) */ +/** + * @} + */ + +/** @defgroup ETH_DMA_Flags ETH DMA Flags + * @{ + */ +#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000U) /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000U) /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000U) /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000U) /*!< Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000U) /*!< Error bits 0-write transfer, 1-read transfer */ +#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000U) /*!< Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000U) /*!< Normal interrupt summary flag */ +#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000U) /*!< Abnormal interrupt summary flag */ +#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000U) /*!< Early receive flag */ +#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000U) /*!< Fatal bus error flag */ +#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400U) /*!< Early transmit flag */ +#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200U) /*!< Receive watchdog timeout flag */ +#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100U) /*!< Receive process stopped flag */ +#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080U) /*!< Receive buffer unavailable flag */ +#define ETH_DMA_FLAG_R ((uint32_t)0x00000040U) /*!< Receive flag */ +#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020U) /*!< Underflow flag */ +#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010U) /*!< Overflow flag */ +#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008U) /*!< Transmit jabber timeout flag */ +#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004U) /*!< Transmit buffer unavailable flag */ +#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002U) /*!< Transmit process stopped flag */ +#define ETH_DMA_FLAG_T ((uint32_t)0x00000001U) /*!< Transmit flag */ +/** + * @} + */ + +/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts + * @{ + */ +#define ETH_MAC_IT_TST ((uint32_t)0x00000200U) /*!< Time stamp trigger interrupt (on MAC) */ +#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040U) /*!< MMC transmit interrupt */ +#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020U) /*!< MMC receive interrupt */ +#define ETH_MAC_IT_MMC ((uint32_t)0x00000010U) /*!< MMC interrupt (on MAC) */ +#define ETH_MAC_IT_PMT ((uint32_t)0x00000008U) /*!< PMT interrupt (on MAC) */ +/** + * @} + */ + +/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts + * @{ + */ +#define ETH_DMA_IT_TST ((uint32_t)0x20000000U) /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_IT_PMT ((uint32_t)0x10000000U) /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_IT_MMC ((uint32_t)0x08000000U) /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_IT_NIS ((uint32_t)0x00010000U) /*!< Normal interrupt summary */ +#define ETH_DMA_IT_AIS ((uint32_t)0x00008000U) /*!< Abnormal interrupt summary */ +#define ETH_DMA_IT_ER ((uint32_t)0x00004000U) /*!< Early receive interrupt */ +#define ETH_DMA_IT_FBE ((uint32_t)0x00002000U) /*!< Fatal bus error interrupt */ +#define ETH_DMA_IT_ET ((uint32_t)0x00000400U) /*!< Early transmit interrupt */ +#define ETH_DMA_IT_RWT ((uint32_t)0x00000200U) /*!< Receive watchdog timeout interrupt */ +#define ETH_DMA_IT_RPS ((uint32_t)0x00000100U) /*!< Receive process stopped interrupt */ +#define ETH_DMA_IT_RBU ((uint32_t)0x00000080U) /*!< Receive buffer unavailable interrupt */ +#define ETH_DMA_IT_R ((uint32_t)0x00000040U) /*!< Receive interrupt */ +#define ETH_DMA_IT_TU ((uint32_t)0x00000020U) /*!< Underflow interrupt */ +#define ETH_DMA_IT_RO ((uint32_t)0x00000010U) /*!< Overflow interrupt */ +#define ETH_DMA_IT_TJT ((uint32_t)0x00000008U) /*!< Transmit jabber timeout interrupt */ +#define ETH_DMA_IT_TBU ((uint32_t)0x00000004U) /*!< Transmit buffer unavailable interrupt */ +#define ETH_DMA_IT_TPS ((uint32_t)0x00000002U) /*!< Transmit process stopped interrupt */ +#define ETH_DMA_IT_T ((uint32_t)0x00000001U) /*!< Transmit interrupt */ +/** + * @} + */ + +/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state + * @{ + */ +#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000U) /*!< Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000U) /*!< Running - fetching the Tx descriptor */ +#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000U) /*!< Running - waiting for status */ +#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000U) /*!< Running - reading the data from host memory */ +#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000U) /*!< Suspended - Tx Descriptor unavailable */ +#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000U) /*!< Running - closing Rx descriptor */ + +/** + * @} + */ + + +/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state + * @{ + */ +#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000U) /*!< Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000U) /*!< Running - fetching the Rx descriptor */ +#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000U) /*!< Running - waiting for packet */ +#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000U) /*!< Suspended - Rx Descriptor unavailable */ +#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000U) /*!< Running - closing descriptor */ +#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000U) /*!< Running - queuing the receive frame into host memory */ + +/** + * @} + */ + +/** @defgroup ETH_DMA_overflow ETH DMA overflow + * @{ + */ +#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000U) /*!< Overflow bit for FIFO overflow counter */ +#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000U) /*!< Overflow bit for missed frame counter */ +/** + * @} + */ + +/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP + * @{ + */ +#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000U) /*!< External interrupt line 19 Connected to the ETH EXTI Line */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup ETH_Exported_Macros ETH Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ + +/** @brief Reset ETH handle state + * @param __HANDLE__: specifies the ETH handle. + * @retval None + */ +#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) + +/** + * @brief Checks whether the specified Ethernet DMA Tx Desc flag is set or not. + * @param __HANDLE__: ETH Handle + * @param __FLAG__: specifies the flag of TDES0 to check. + * @retval the ETH_DMATxDescFlag (SET or RESET). + */ +#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) + +/** + * @brief Checks whether the specified Ethernet DMA Rx Desc flag is set or not. + * @param __HANDLE__: ETH Handle + * @param __FLAG__: specifies the flag of RDES0 to check. + * @retval the ETH_DMATxDescFlag (SET or RESET). + */ +#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__)) + +/** + * @brief Enables the specified DMA Rx Desc receive interrupt. + * @param __HANDLE__: ETH Handle + * @retval None + */ +#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC)) + +/** + * @brief Disables the specified DMA Rx Desc receive interrupt. + * @param __HANDLE__: ETH Handle + * @retval None + */ +#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC) + +/** + * @brief Set the specified DMA Rx Desc Own bit. + * @param __HANDLE__: ETH Handle + * @retval None + */ +#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) + +/** + * @brief Returns the specified Ethernet DMA Tx Desc collision count. + * @param __HANDLE__: ETH Handle + * @retval The Transmit descriptor collision counter value. + */ +#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) + +/** + * @brief Set the specified DMA Tx Desc Own bit. + * @param __HANDLE__: ETH Handle + * @retval None + */ +#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN) + +/** + * @brief Enables the specified DMA Tx Desc Transmit interrupt. + * @param __HANDLE__: ETH Handle + * @retval None + */ +#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC) + +/** + * @brief Disables the specified DMA Tx Desc Transmit interrupt. + * @param __HANDLE__: ETH Handle + * @retval None + */ +#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) + +/** + * @brief Selects the specified Ethernet DMA Tx Desc Checksum Insertion. + * @param __HANDLE__: ETH Handle + * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion. + * This parameter can be one of the following values: + * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass + * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum + * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present + * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header + * @retval None + */ +#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__)) + +/** + * @brief Enables the DMA Tx Desc CRC. + * @param __HANDLE__: ETH Handle + * @retval None + */ +#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC) + +/** + * @brief Disables the DMA Tx Desc CRC. + * @param __HANDLE__: ETH Handle + * @retval None + */ +#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC) + +/** + * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes. + * @param __HANDLE__: ETH Handle + * @retval None + */ +#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP) + +/** + * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes. + * @param __HANDLE__: ETH Handle + * @retval None + */ +#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) + +/** + * @brief Enables the specified Ethernet MAC interrupts. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the Ethernet MAC interrupt sources to be + * enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_IT_PMT : PMT interrupt + * @retval None + */ +#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__)) + +/** + * @brief Disables the specified Ethernet MAC interrupts. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the Ethernet MAC interrupt sources to be + * enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_IT_PMT : PMT interrupt + * @retval None + */ +#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__)) + +/** + * @brief Initiate a Pause Control Frame (Full-duplex only). + * @param __HANDLE__: ETH Handle + * @retval None + */ +#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) + +/** + * @brief Checks whether the Ethernet flow control busy bit is set or not. + * @param __HANDLE__: ETH Handle + * @retval The new state of flow control busy status bit (SET or RESET). + */ +#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA) + +/** + * @brief Enables the MAC Back Pressure operation activation (Half-duplex only). + * @param __HANDLE__: ETH Handle + * @retval None + */ +#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) + +/** + * @brief Disables the MAC BackPressure operation activation (Half-duplex only). + * @param __HANDLE__: ETH Handle + * @retval None + */ +#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) + +/** + * @brief Checks whether the specified Ethernet MAC flag is set or not. + * @param __HANDLE__: ETH Handle + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag + * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag + * @arg ETH_MAC_FLAG_MMCR : MMC receive flag + * @arg ETH_MAC_FLAG_MMC : MMC flag + * @arg ETH_MAC_FLAG_PMT : PMT flag + * @retval The state of Ethernet MAC flag. + */ +#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) + +/** + * @brief Enables the specified Ethernet DMA interrupts. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the Ethernet DMA interrupt sources to be + * enabled @ref ETH_DMA_Interrupts + * @retval None + */ +#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified Ethernet DMA interrupts. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the Ethernet DMA interrupt sources to be + * disabled. @ref ETH_DMA_Interrupts + * @retval None + */ +#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__)) + +/** + * @brief Clears the Ethernet DMA IT pending bit. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts + * @retval None + */ +#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) + +/** + * @brief Checks whether the specified Ethernet DMA flag is set or not. +* @param __HANDLE__: ETH Handle + * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags + * @retval The new state of ETH_DMA_FLAG (SET or RESET). + */ +#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) + +/** + * @brief Checks whether the specified Ethernet DMA flag is set or not. + * @param __HANDLE__: ETH Handle + * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags + * @retval The new state of ETH_DMA_FLAG (SET or RESET). + */ +#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) + +/** + * @brief Checks whether the specified Ethernet DMA overflow flag is set or not. + * @param __HANDLE__: ETH Handle + * @param __OVERFLOW__: specifies the DMA overflow flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter + * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter + * @retval The state of Ethernet DMA overflow Flag (SET or RESET). + */ +#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__)) + +/** + * @brief Set the DMA Receive status watchdog timer register value + * @param __HANDLE__: ETH Handle + * @param __VALUE__: DMA Receive status watchdog timer register value + * @retval None + */ +#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__)) + +/** + * @brief Enables any unicast packet filtered by the MAC address + * recognition to be a wake-up frame. + * @param __HANDLE__: ETH Handle. + * @retval None + */ +#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU) + +/** + * @brief Disables any unicast packet filtered by the MAC address + * recognition to be a wake-up frame. + * @param __HANDLE__: ETH Handle. + * @retval None + */ +#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU) + +/** + * @brief Enables the MAC Wake-Up Frame Detection. + * @param __HANDLE__: ETH Handle. + * @retval None + */ +#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE) + +/** + * @brief Disables the MAC Wake-Up Frame Detection. + * @param __HANDLE__: ETH Handle. + * @retval None + */ +#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) + +/** + * @brief Enables the MAC Magic Packet Detection. + * @param __HANDLE__: ETH Handle. + * @retval None + */ +#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE) + +/** + * @brief Disables the MAC Magic Packet Detection. + * @param __HANDLE__: ETH Handle. + * @retval None + */ +#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) + +/** + * @brief Enables the MAC Power Down. + * @param __HANDLE__: ETH Handle + * @retval None + */ +#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD) + +/** + * @brief Disables the MAC Power Down. + * @param __HANDLE__: ETH Handle + * @retval None + */ +#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) + +/** + * @brief Checks whether the specified Ethernet PMT flag is set or not. + * @param __HANDLE__: ETH Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset + * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received + * @arg ETH_PMT_FLAG_MPR : Magic Packet Received + * @retval The new state of Ethernet PMT Flag (SET or RESET). + */ +#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__)) + +/** + * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) + * @param __HANDLE__: ETH Handle. + * @retval None + */ +#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP)) + +/** + * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) + * @param __HANDLE__: ETH Handle. + * @retval None + */ +#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\ + (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0) + +/** + * @brief Enables the MMC Counter Freeze. + * @param __HANDLE__: ETH Handle. + * @retval None + */ +#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF) + +/** + * @brief Disables the MMC Counter Freeze. + * @param __HANDLE__: ETH Handle. + * @retval None + */ +#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF) + +/** + * @brief Enables the MMC Reset On Read. + * @param __HANDLE__: ETH Handle. + * @retval None + */ +#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR) + +/** + * @brief Disables the MMC Reset On Read. + * @param __HANDLE__: ETH Handle. + * @retval None + */ +#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR) + +/** + * @brief Enables the MMC Counter Stop Rollover. + * @param __HANDLE__: ETH Handle. + * @retval None + */ +#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR) + +/** + * @brief Disables the MMC Counter Stop Rollover. + * @param __HANDLE__: ETH Handle. + * @retval None + */ +#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR) + +/** + * @brief Resets the MMC Counters. + * @param __HANDLE__: ETH Handle. + * @retval None + */ +#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) + +/** + * @brief Enables the specified Ethernet MMC Rx interrupts. + * @param __HANDLE__: ETH Handle. + * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value + * @retval None + */ +#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF) +/** + * @brief Disables the specified Ethernet MMC Rx interrupts. + * @param __HANDLE__: ETH Handle. + * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value + * @retval None + */ +#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF) +/** + * @brief Enables the specified Ethernet MMC Tx interrupts. + * @param __HANDLE__: ETH Handle. + * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value + * @retval None + */ +#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__)) + +/** + * @brief Disables the specified Ethernet MMC Tx interrupts. + * @param __HANDLE__: ETH Handle. + * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value + * @retval None + */ +#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__)) + +/** + * @brief Enables the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Disables the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Enable event on ETH External event line. + * @retval None. + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Disable event on ETH External event line + * @retval None. + */ +#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Get flag of the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Clear flag of the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Enables rising edge trigger to the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP + +/** + * @brief Disables the rising edge trigger to the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Enables falling edge trigger to the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Disables falling edge trigger to the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Enables rising/falling edge trigger to the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ + EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP + +/** + * @brief Disables rising/falling edge trigger to the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ + EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None. + */ +#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP + +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup ETH_Exported_Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ + +/** @addtogroup ETH_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); +void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); +void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); +HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); + +/** + * @} + */ +/* IO operation functions ****************************************************/ + +/** @addtogroup ETH_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength); +HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth); +/* Communication with PHY functions*/ +HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue); +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth); +void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); +/* Callback in non blocking modes (Interrupt) */ +void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ + +/** @addtogroup ETH_Exported_Functions_Group3 + * @{ + */ + +HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf); +HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ + +/** @addtogroup ETH_Exported_Functions_Group4 + * @{ + */ +HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_ETH_H */ + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32Fxx/NetworkInterface.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32Fxx/NetworkInterface.c new file mode 100644 index 0000000..ab17be2 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32Fxx/NetworkInterface.c @@ -0,0 +1,1190 @@ +/* + * Some constants, hardware definitions and comments taken from ST's HAL driver + * library, COPYRIGHT(c) 2015 STMicroelectronics. + */ + +/* + * FreeRTOS+TCP V2.0.11 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org +*/ + +/* Standard includes. */ +#include +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_IP_Private.h" +#include "FreeRTOS_DNS.h" +#include "NetworkBufferManagement.h" +#include "NetworkInterface.h" +#include "phyHandling.h" + +#define __STM32_HAL_LEGACY 1 + +/* ST includes. */ +#if defined( STM32F7xx ) + #include "stm32f7xx_hal.h" +#elif defined( STM32F4xx ) + #include "stm32f4xx_hal.h" +#elif defined( STM32F2xx ) + #include "stm32f2xx_hal.h" +#else + #error What part? +#endif + +#include "stm32fxx_hal_eth.h" + +/* Interrupt events to process. Currently only the Rx event is processed +although code for other events is included to allow for possible future +expansion. */ +#define EMAC_IF_RX_EVENT 1UL +#define EMAC_IF_TX_EVENT 2UL +#define EMAC_IF_ERR_EVENT 4UL +#define EMAC_IF_ALL_EVENT ( EMAC_IF_RX_EVENT | EMAC_IF_TX_EVENT | EMAC_IF_ERR_EVENT ) + +#define ETH_DMA_ALL_INTS \ + ( ETH_DMA_IT_TST | ETH_DMA_IT_PMT | ETH_DMA_IT_MMC | ETH_DMA_IT_NIS | ETH_DMA_IT_ER | \ + ETH_DMA_IT_FBE | ETH_DMA_IT_RWT | ETH_DMA_IT_RPS | ETH_DMA_IT_RBU | ETH_DMA_IT_R | \ + ETH_DMA_IT_TU | ETH_DMA_IT_RO | ETH_DMA_IT_TJT | ETH_DMA_IT_TPS | ETH_DMA_IT_T ) + +#ifndef niEMAC_HANDLER_TASK_PRIORITY + #define niEMAC_HANDLER_TASK_PRIORITY configMAX_PRIORITIES - 1 +#endif + +#define ipFRAGMENT_OFFSET_BIT_MASK ( ( uint16_t ) 0x0fff ) /* The bits in the two byte IP header field that make up the fragment offset value. */ + +/* + * Most users will want a PHY that negotiates about + * the connection properties: speed, dmix and duplex. + * On some rare cases, you want to select what is being + * advertised, properties like MDIX and duplex. + */ + +#if !defined( ipconfigETHERNET_AN_ENABLE ) + /* Enable auto-negotiation */ + #define ipconfigETHERNET_AN_ENABLE 1 +#endif + +#if !defined( ipconfigETHERNET_AUTO_CROSS_ENABLE ) + #define ipconfigETHERNET_AUTO_CROSS_ENABLE 1 +#endif + +#if( ipconfigETHERNET_AN_ENABLE == 0 ) + /* + * The following three defines are only used in case there + * is no auto-negotiation. + */ + #if !defined( ipconfigETHERNET_CROSSED_LINK ) + #define ipconfigETHERNET_CROSSED_LINK 1 + #endif + + #if !defined( ipconfigETHERNET_USE_100MB ) + #define ipconfigETHERNET_USE_100MB 1 + #endif + + #if !defined( ipconfigETHERNET_USE_FULL_DUPLEX ) + #define ipconfigETHERNET_USE_FULL_DUPLEX 1 + #endif +#endif /* ipconfigETHERNET_AN_ENABLE == 0 */ + +/* Default the size of the stack used by the EMAC deferred handler task to twice +the size of the stack used by the idle task - but allow this to be overridden in +FreeRTOSConfig.h as configMINIMAL_STACK_SIZE is a user definable constant. */ +#ifndef configEMAC_TASK_STACK_SIZE + #define configEMAC_TASK_STACK_SIZE ( 2 * configMINIMAL_STACK_SIZE ) +#endif + +/* Two choices must be made: RMII versus MII, +and the index of the PHY in use ( between 0 and 31 ). */ +#ifndef ipconfigUSE_RMII + #ifdef STM32F7xx + #define ipconfigUSE_RMII 1 + #else + #define ipconfigUSE_RMII 0 + #endif /* STM32F7xx */ +#endif /* ipconfigUSE_RMII */ + +#if( ipconfigUSE_RMII != 0 ) + #warning Using RMII, make sure if this is correct +#else + #warning Using MII, make sure if this is correct +#endif + +/*-----------------------------------------------------------*/ + +/* + * A deferred interrupt handler task that processes + */ +static void prvEMACHandlerTask( void *pvParameters ); + +/* + * Force a negotiation with the Switch or Router and wait for LS. + */ +static void prvEthernetUpdateConfig( BaseType_t xForce ); + +/* + * See if there is a new packet and forward it to the IP-task. + */ +static BaseType_t prvNetworkInterfaceInput( void ); + +#if( ipconfigUSE_LLMNR != 0 ) + /* + * For LLMNR, an extra MAC-address must be configured to + * be able to receive the multicast messages. + */ + static void prvMACAddressConfig(ETH_HandleTypeDef *heth, uint32_t ulIndex, uint8_t *Addr); +#endif + +/* + * Check if a given packet should be accepted. + */ +static BaseType_t xMayAcceptPacket( uint8_t *pcBuffer ); + +/* + * Initialise the TX descriptors. + */ +static void prvDMATxDescListInit( void ); + +/* + * Initialise the RX descriptors. + */ +static void prvDMARxDescListInit( void ); + + /* After packets have been sent, the network + buffers will be released. */ + static void vClearTXBuffers( void ); + +/*-----------------------------------------------------------*/ + +/* Bit map of outstanding ETH interrupt events for processing. Currently only +the Rx interrupt is handled, although code is included for other events to +enable future expansion. */ +static volatile uint32_t ulISREvents; + +#if( ipconfigUSE_LLMNR == 1 ) + static const uint8_t xLLMNR_MACAddress[] = { 0x01, 0x00, 0x5E, 0x00, 0x00, 0xFC }; +#endif + +static EthernetPhy_t xPhyObject; + +/* Ethernet handle. */ +static ETH_HandleTypeDef xETH; + + /* xTXDescriptorSemaphore is a counting semaphore with + a maximum count of ETH_TXBUFNB, which is the number of + DMA TX descriptors. */ + static SemaphoreHandle_t xTXDescriptorSemaphore = NULL; + +/* + * Note: it is adviced to define both + * + * #define ipconfigZERO_COPY_RX_DRIVER 1 + * #define ipconfigZERO_COPY_TX_DRIVER 1 + * + * The method using memcpy is slower and probaly uses more RAM memory. + * The possibility is left in the code just for comparison. + * + * It is adviced to define ETH_TXBUFNB at least 4. Note that no + * TX buffers are allocated in a zero-copy driver. + */ +/* MAC buffers: ---------------------------------------------------------*/ + +/* Put the DMA descriptors in '.first_data'. +This is important for STM32F7, which has an L1 data cache. +The first 64KB of the SRAM is not cached. */ + +/* Ethernet Rx MA Descriptor */ +__attribute__ ((aligned (32))) +__attribute__ ((section(".first_data"))) + ETH_DMADescTypeDef DMARxDscrTab[ ETH_RXBUFNB ]; + +#if( ipconfigZERO_COPY_RX_DRIVER == 0 ) + /* Ethernet Receive Buffer */ + __ALIGN_BEGIN uint8_t Rx_Buff[ ETH_RXBUFNB ][ ETH_RX_BUF_SIZE ] __ALIGN_END; +#endif + +/* Ethernet Tx DMA Descriptor */ +__attribute__ ((aligned (32))) +__attribute__ ((section(".first_data"))) + ETH_DMADescTypeDef DMATxDscrTab[ ETH_TXBUFNB ]; + +#if( ipconfigZERO_COPY_TX_DRIVER == 0 ) + /* Ethernet Transmit Buffer */ + __ALIGN_BEGIN uint8_t Tx_Buff[ ETH_TXBUFNB ][ ETH_TX_BUF_SIZE ] __ALIGN_END; +#endif + +#if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + /* DMATxDescToClear points to the next TX DMA descriptor + that must be cleared by vClearTXBuffers(). */ + static __IO ETH_DMADescTypeDef *DMATxDescToClear; +#endif + +/* Holds the handle of the task used as a deferred interrupt processor. The +handle is used so direct notifications can be sent to the task for all EMAC/DMA +related interrupts. */ +static TaskHandle_t xEMACTaskHandle = NULL; + +/* For local use only: describe the PHY's properties: */ +const PhyProperties_t xPHYProperties = +{ + #if( ipconfigETHERNET_AN_ENABLE != 0 ) + .ucSpeed = PHY_SPEED_AUTO, + .ucDuplex = PHY_DUPLEX_AUTO, + #else + #if( ipconfigETHERNET_USE_100MB != 0 ) + .ucSpeed = PHY_SPEED_100, + #else + .ucSpeed = PHY_SPEED_10, + #endif + + #if( ipconfigETHERNET_USE_FULL_DUPLEX != 0 ) + .duplex = PHY_DUPLEX_FULL, + #else + .duplex = PHY_DUPLEX_HALF, + #endif + #endif + + #if( ipconfigETHERNET_AN_ENABLE != 0 ) && ( ipconfigETHERNET_AUTO_CROSS_ENABLE != 0 ) + .ucMDI_X = PHY_MDIX_AUTO, + #elif( ipconfigETHERNET_CROSSED_LINK != 0 ) + .ucMDI_X = PHY_MDIX_CROSSED, + #else + .ucMDI_X = PHY_MDIX_DIRECT, + #endif +}; + +/*-----------------------------------------------------------*/ + +void HAL_ETH_RxCpltCallback( ETH_HandleTypeDef *heth ) +{ +BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + /* Ethernet RX-Complete callback function, elsewhere declared as weak. */ + ulISREvents |= EMAC_IF_RX_EVENT; + /* Wakeup the prvEMACHandlerTask. */ + if( xEMACTaskHandle != NULL ) + { + vTaskNotifyGiveFromISR( xEMACTaskHandle, &xHigherPriorityTaskWoken ); + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + } +} +/*-----------------------------------------------------------*/ + + void HAL_ETH_TxCpltCallback( ETH_HandleTypeDef *heth ) + { + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + /* This call-back is only useful in case packets are being sent + zero-copy. Once they're sent, the buffers will be released + by the function vClearTXBuffers(). */ + ulISREvents |= EMAC_IF_TX_EVENT; + /* Wakeup the prvEMACHandlerTask. */ + if( xEMACTaskHandle != NULL ) + { + vTaskNotifyGiveFromISR( xEMACTaskHandle, &xHigherPriorityTaskWoken ); + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + } + + } +/*-----------------------------------------------------------*/ + + static void vClearTXBuffers() + { + __IO ETH_DMADescTypeDef *txLastDescriptor = xETH.TxDesc; +size_t uxCount = ( ( UBaseType_t ) ETH_TXBUFNB ) - uxSemaphoreGetCount( xTXDescriptorSemaphore ); +#if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + NetworkBufferDescriptor_t *pxNetworkBuffer; + uint8_t *ucPayLoad; +#endif + + /* This function is called after a TX-completion interrupt. + It will release each Network Buffer used in xNetworkInterfaceOutput(). + 'uxCount' represents the number of descriptors given to DMA for transmission. + After sending a packet, the DMA will clear the 'ETH_DMATXDESC_OWN' bit. */ + while( ( uxCount > 0 ) && ( ( DMATxDescToClear->Status & ETH_DMATXDESC_OWN ) == 0 ) ) + { + if( ( DMATxDescToClear == txLastDescriptor ) && ( uxCount != ETH_TXBUFNB ) ) + { + break; + } + #if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + { + ucPayLoad = ( uint8_t * )DMATxDescToClear->Buffer1Addr; + + if( ucPayLoad != NULL ) + { + pxNetworkBuffer = pxPacketBuffer_to_NetworkBuffer( ucPayLoad ); + if( pxNetworkBuffer != NULL ) + { + vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ) ; + } + DMATxDescToClear->Buffer1Addr = ( uint32_t )0u; + } + } + #endif /* ipconfigZERO_COPY_TX_DRIVER */ + + DMATxDescToClear = ( ETH_DMADescTypeDef * )( DMATxDescToClear->Buffer2NextDescAddr ); + + uxCount--; + /* Tell the counting semaphore that one more TX descriptor is available. */ + xSemaphoreGive( xTXDescriptorSemaphore ); + } + } +/*-----------------------------------------------------------*/ + +BaseType_t xNetworkInterfaceInitialise( void ) +{ +HAL_StatusTypeDef hal_eth_init_status; +BaseType_t xResult; + + if( xEMACTaskHandle == NULL ) + { + if( xTXDescriptorSemaphore == NULL ) + { + xTXDescriptorSemaphore = xSemaphoreCreateCounting( ( UBaseType_t ) ETH_TXBUFNB, ( UBaseType_t ) ETH_TXBUFNB ); + configASSERT( xTXDescriptorSemaphore ); + } + + /* Initialise ETH */ + + xETH.Instance = ETH; + xETH.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE; + xETH.Init.Speed = ETH_SPEED_100M; + xETH.Init.DuplexMode = ETH_MODE_FULLDUPLEX; + /* Value of PhyAddress doesn't matter, will be probed for. */ + xETH.Init.PhyAddress = 0; + + xETH.Init.MACAddr = ( uint8_t *)FreeRTOS_GetMACAddress(); + xETH.Init.RxMode = ETH_RXINTERRUPT_MODE; + + /* using the ETH_CHECKSUM_BY_HARDWARE option: + both the IP and the protocol checksums will be calculated + by the peripheral. */ + xETH.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE; + + #if( ipconfigUSE_RMII != 0 ) + { + xETH.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII; + } + #else + { + xETH.Init.MediaInterface = ETH_MEDIA_INTERFACE_MII; + } + #endif /* ipconfigUSE_RMII */ + + hal_eth_init_status = HAL_ETH_Init( &xETH ); + + /* Only for inspection by debugger. */ + ( void ) hal_eth_init_status; + + /* Set the TxDesc and RxDesc pointers. */ + xETH.TxDesc = DMATxDscrTab; + xETH.RxDesc = DMARxDscrTab; + + /* Make sure that all unused fields are cleared. */ + memset( &DMATxDscrTab, '\0', sizeof( DMATxDscrTab ) ); + memset( &DMARxDscrTab, '\0', sizeof( DMARxDscrTab ) ); + + /* Initialize Tx Descriptors list: Chain Mode */ + DMATxDescToClear = DMATxDscrTab; + + /* Initialise TX-descriptors. */ + prvDMATxDescListInit(); + + /* Initialise RX-descriptors. */ + prvDMARxDescListInit(); + + #if( ipconfigUSE_LLMNR != 0 ) + { + /* Program the LLMNR address at index 1. */ + prvMACAddressConfig( &xETH, ETH_MAC_ADDRESS1, ( uint8_t *) xLLMNR_MACAddress ); + } + #endif + + /* Force a negotiation with the Switch or Router and wait for LS. */ + prvEthernetUpdateConfig( pdTRUE ); + + /* The deferred interrupt handler task is created at the highest + possible priority to ensure the interrupt handler can return directly + to it. The task's handle is stored in xEMACTaskHandle so interrupts can + notify the task when there is something to process. */ + xTaskCreate( prvEMACHandlerTask, "EMAC", configEMAC_TASK_STACK_SIZE, NULL, niEMAC_HANDLER_TASK_PRIORITY, &xEMACTaskHandle ); + } /* if( xEMACTaskHandle == NULL ) */ + + if( xPhyObject.ulLinkStatusMask != 0 ) + { + xETH.Instance->DMAIER |= ETH_DMA_ALL_INTS; + xResult = pdPASS; + FreeRTOS_printf( ( "Link Status is high\n" ) ) ; + } + else + { + /* For now pdFAIL will be returned. But prvEMACHandlerTask() is running + and it will keep on checking the PHY and set 'ulLinkStatusMask' when necessary. */ + xResult = pdFAIL; + FreeRTOS_printf( ( "Link Status still low\n" ) ) ; + } + /* When returning non-zero, the stack will become active and + start DHCP (in configured) */ + return xResult; +} +/*-----------------------------------------------------------*/ + +static void prvDMATxDescListInit() +{ +ETH_DMADescTypeDef *pxDMADescriptor; +BaseType_t xIndex; + + /* Get the pointer on the first member of the descriptor list */ + pxDMADescriptor = DMATxDscrTab; + + /* Fill each DMA descriptor with the right values */ + for( xIndex = 0; xIndex < ETH_TXBUFNB; xIndex++, pxDMADescriptor++ ) + { + /* Set Second Address Chained bit */ + pxDMADescriptor->Status = ETH_DMATXDESC_TCH; + + #if( ipconfigZERO_COPY_TX_DRIVER == 0 ) + { + /* Set Buffer1 address pointer */ + pxDMADescriptor->Buffer1Addr = ( uint32_t )( Tx_Buff[ xIndex ] ); + } + #endif + + if( xETH.Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE ) + { + /* Set the DMA Tx descriptors checksum insertion for TCP, UDP, and ICMP */ + pxDMADescriptor->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL; + } + + /* Initialize the next descriptor with the Next Descriptor Polling Enable */ + if( xIndex < ETH_TXBUFNB - 1 ) + { + /* Set next descriptor address register with next descriptor base address */ + pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) ( pxDMADescriptor + 1 ); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) DMATxDscrTab; + } + } + + /* Set Transmit Descriptor List Address Register */ + xETH.Instance->DMATDLAR = ( uint32_t ) DMATxDscrTab; +} +/*-----------------------------------------------------------*/ + +static void prvDMARxDescListInit() +{ +ETH_DMADescTypeDef *pxDMADescriptor; +BaseType_t xIndex; + /* + * RX-descriptors. + */ + + /* Get the pointer on the first member of the descriptor list */ + pxDMADescriptor = DMARxDscrTab; + + /* Fill each DMA descriptor with the right values */ + for( xIndex = 0; xIndex < ETH_RXBUFNB; xIndex++, pxDMADescriptor++ ) + { + + /* Set Buffer1 size and Second Address Chained bit */ + pxDMADescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | (uint32_t)ETH_RX_BUF_SIZE; + + #if( ipconfigZERO_COPY_RX_DRIVER != 0 ) + { + /* Set Buffer1 address pointer */ + NetworkBufferDescriptor_t *pxBuffer; + + pxBuffer = pxGetNetworkBufferWithDescriptor( ETH_RX_BUF_SIZE, 100ul ); + /* If the assert below fails, make sure that there are at least 'ETH_RXBUFNB' + Network Buffers available during start-up ( ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ) */ + configASSERT( pxBuffer != NULL ); + if( pxBuffer != NULL ) + { + pxDMADescriptor->Buffer1Addr = (uint32_t)pxBuffer->pucEthernetBuffer; + pxDMADescriptor->Status = ETH_DMARXDESC_OWN; + } + } + #else + { + /* Set Buffer1 address pointer */ + pxDMADescriptor->Buffer1Addr = ( uint32_t )( Rx_Buff[ xIndex ] ); + /* Set Own bit of the Rx descriptor Status */ + pxDMADescriptor->Status = ETH_DMARXDESC_OWN; + } + #endif + + /* Initialize the next descriptor with the Next Descriptor Polling Enable */ + if( xIndex < ETH_RXBUFNB - 1 ) + { + /* Set next descriptor address register with next descriptor base address */ + pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t )( pxDMADescriptor + 1 ); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) DMARxDscrTab; + } + + } + /* Set Receive Descriptor List Address Register */ + xETH.Instance->DMARDLAR = ( uint32_t ) DMARxDscrTab; +} +/*-----------------------------------------------------------*/ + +static void prvMACAddressConfig(ETH_HandleTypeDef *heth, uint32_t ulIndex, uint8_t *Addr) +{ +uint32_t ulTempReg; + + /* Calculate the selected MAC address high register. */ + ulTempReg = 0x80000000ul | ( ( uint32_t ) Addr[ 5 ] << 8 ) | ( uint32_t ) Addr[ 4 ]; + + /* Load the selected MAC address high register. */ + ( *(__IO uint32_t *)( ( uint32_t ) ( ETH_MAC_ADDR_HBASE + ulIndex ) ) ) = ulTempReg; + + /* Calculate the selected MAC address low register. */ + ulTempReg = ( ( uint32_t ) Addr[ 3 ] << 24 ) | ( ( uint32_t ) Addr[ 2 ] << 16 ) | ( ( uint32_t ) Addr[ 1 ] << 8 ) | Addr[ 0 ]; + + /* Load the selected MAC address low register */ + ( *(__IO uint32_t *) ( ( uint32_t ) ( ETH_MAC_ADDR_LBASE + ulIndex ) ) ) = ulTempReg; +} +/*-----------------------------------------------------------*/ + +BaseType_t xNetworkInterfaceOutput( NetworkBufferDescriptor_t * const pxDescriptor, BaseType_t bReleaseAfterSend ) +{ +BaseType_t xReturn = pdFAIL; +uint32_t ulTransmitSize = 0; +__IO ETH_DMADescTypeDef *pxDmaTxDesc; +/* Do not wait too long for a free TX DMA buffer. */ +const TickType_t xBlockTimeTicks = pdMS_TO_TICKS( 50u ); + + /* Open a do {} while ( 0 ) loop to be able to call break. */ + do + { + if( xCheckLoopback( pxDescriptor, bReleaseAfterSend ) != 0 ) + { + /* The packet has been sent back to the IP-task. + The IP-task will further handle it. + Do not release the descriptor. */ + bReleaseAfterSend = pdFALSE; + break; + } + #if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM != 0 ) + { + ProtocolPacket_t *pxPacket; + + #if( ipconfigZERO_COPY_RX_DRIVER != 0 ) + { + configASSERT( bReleaseAfterSend != 0 ); + } + #endif /* ipconfigZERO_COPY_RX_DRIVER */ + + /* If the peripheral must calculate the checksum, it wants + the protocol checksum to have a value of zero. */ + pxPacket = ( ProtocolPacket_t * ) ( pxDescriptor->pucEthernetBuffer ); + + if( pxPacket->xICMPPacket.xIPHeader.ucProtocol == ipPROTOCOL_ICMP ) + { + pxPacket->xICMPPacket.xICMPHeader.usChecksum = ( uint16_t )0u; + } + } + #endif /* ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM */ + if( xPhyObject.ulLinkStatusMask != 0 ) + { + if( xSemaphoreTake( xTXDescriptorSemaphore, xBlockTimeTicks ) != pdPASS ) + { + /* Time-out waiting for a free TX descriptor. */ + break; + } + + /* This function does the actual transmission of the packet. The packet is + contained in 'pxDescriptor' that is passed to the function. */ + pxDmaTxDesc = xETH.TxDesc; + + /* Is this buffer available? */ + configASSERT ( ( pxDmaTxDesc->Status & ETH_DMATXDESC_OWN ) == 0 ); + + { + /* Is this buffer available? */ + /* Get bytes in current buffer. */ + ulTransmitSize = pxDescriptor->xDataLength; + + if( ulTransmitSize > ETH_TX_BUF_SIZE ) + { + ulTransmitSize = ETH_TX_BUF_SIZE; + } + + #if( ipconfigZERO_COPY_TX_DRIVER == 0 ) + { + /* Copy the bytes. */ + memcpy( ( void * ) pxDmaTxDesc->Buffer1Addr, pxDescriptor->pucEthernetBuffer, ulTransmitSize ); + } + #else + { + /* Move the buffer. */ + pxDmaTxDesc->Buffer1Addr = ( uint32_t )pxDescriptor->pucEthernetBuffer; + /* The Network Buffer has been passed to DMA, no need to release it. */ + bReleaseAfterSend = pdFALSE_UNSIGNED; + } + #endif /* ipconfigZERO_COPY_TX_DRIVER */ + + /* Ask to set the IPv4 checksum. + Also need an Interrupt on Completion so that 'vClearTXBuffers()' will be called.. */ + pxDmaTxDesc->Status |= ETH_DMATXDESC_CIC_TCPUDPICMP_FULL | ETH_DMATXDESC_IC; + + /* Prepare transmit descriptors to give to DMA. */ + + /* Set LAST and FIRST segment */ + pxDmaTxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS; + /* Set frame size */ + pxDmaTxDesc->ControlBufferSize = ( ulTransmitSize & ETH_DMATXDESC_TBS1 ); + + #if( NETWORK_BUFFERS_CACHED != 0 ) + { + BaseType_t xlength = CACHE_LINE_SIZE * ( ( ulTransmitSize + NETWORK_BUFFER_HEADER_SIZE + CACHE_LINE_SIZE - 1 ) / CACHE_LINE_SIZE ); + uint32_t *pulBuffer = ( uint32_t )( pxDescriptor->pucEthernetBuffer - NETWORK_BUFFER_HEADER_SIZE ); + cache_clean_invalidate_by_addr( pulBuffer, xlength ); + } + #endif + + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + pxDmaTxDesc->Status |= ETH_DMATXDESC_OWN; + + /* Point to next descriptor */ + xETH.TxDesc = ( ETH_DMADescTypeDef * ) ( xETH.TxDesc->Buffer2NextDescAddr ); + /* Ensure completion of memory access */ + __DSB(); + /* Resume DMA transmission*/ + xETH.Instance->DMATPDR = 0; + iptraceNETWORK_INTERFACE_TRANSMIT(); + xReturn = pdPASS; + } + } + else + { + /* The PHY has no Link Status, packet shall be dropped. */ + } + } while( 0 ); + /* The buffer has been sent so can be released. */ + if( bReleaseAfterSend != pdFALSE ) + { + vReleaseNetworkBufferAndDescriptor( pxDescriptor ); + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static BaseType_t xMayAcceptPacket( uint8_t *pcBuffer ) +{ +const ProtocolPacket_t *pxProtPacket = ( const ProtocolPacket_t * )pcBuffer; + + switch( pxProtPacket->xTCPPacket.xEthernetHeader.usFrameType ) + { + case ipARP_FRAME_TYPE: + /* Check it later. */ + return pdTRUE; + case ipIPv4_FRAME_TYPE: + /* Check it here. */ + break; + default: + /* Refuse the packet. */ + return pdFALSE; + } + + #if( ipconfigETHERNET_DRIVER_FILTERS_PACKETS == 1 ) + { + const IPHeader_t *pxIPHeader = &(pxProtPacket->xTCPPacket.xIPHeader); + uint32_t ulDestinationIPAddress; + + /* Ensure that the incoming packet is not fragmented (only outgoing packets + * can be fragmented) as these are the only handled IP frames currently. */ + if( ( pxIPHeader->usFragmentOffset & FreeRTOS_ntohs( ipFRAGMENT_OFFSET_BIT_MASK ) ) != 0U ) + { + return pdFALSE; + } + /* HT: Might want to make the following configurable because + * most IP messages have a standard length of 20 bytes */ + + /* 0x45 means: IPv4 with an IP header of 5 x 4 = 20 bytes + * 0x47 means: IPv4 with an IP header of 7 x 4 = 28 bytes */ + if( pxIPHeader->ucVersionHeaderLength < 0x45 || pxIPHeader->ucVersionHeaderLength > 0x4F ) + { + return pdFALSE; + } + + ulDestinationIPAddress = pxIPHeader->ulDestinationIPAddress; + /* Is the packet for this node? */ + if( ( ulDestinationIPAddress != *ipLOCAL_IP_ADDRESS_POINTER ) && + /* Is it a broadcast address x.x.x.255 ? */ + ( ( FreeRTOS_ntohl( ulDestinationIPAddress ) & 0xff ) != 0xff ) && + #if( ipconfigUSE_LLMNR == 1 ) + ( ulDestinationIPAddress != ipLLMNR_IP_ADDR ) && + #endif + ( *ipLOCAL_IP_ADDRESS_POINTER != 0 ) ) { + FreeRTOS_printf( ( "Drop IP %lxip\n", FreeRTOS_ntohl( ulDestinationIPAddress ) ) ); + return pdFALSE; + } + + if( pxIPHeader->ucProtocol == ipPROTOCOL_UDP ) + { + uint16_t port = pxProtPacket->xUDPPacket.xUDPHeader.usDestinationPort; + + if( ( xPortHasUDPSocket( port ) == pdFALSE ) + #if ipconfigUSE_LLMNR == 1 + && ( port != FreeRTOS_ntohs( ipLLMNR_PORT ) ) + #endif + #if ipconfigUSE_NBNS == 1 + && ( port != FreeRTOS_ntohs( ipNBNS_PORT ) ) + #endif + #if ipconfigUSE_DNS == 1 + && ( pxProtPacket->xUDPPacket.xUDPHeader.usSourcePort != FreeRTOS_ntohs( ipDNS_PORT ) ) + #endif + ) { + /* Drop this packet, not for this device. */ + return pdFALSE; + } + } + } + #endif /* ipconfigETHERNET_DRIVER_FILTERS_PACKETS */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvNetworkInterfaceInput( void ) +{ +NetworkBufferDescriptor_t *pxCurDescriptor; +NetworkBufferDescriptor_t *pxNewDescriptor = NULL; +BaseType_t xReceivedLength, xAccepted; +__IO ETH_DMADescTypeDef *pxDMARxDescriptor; +xIPStackEvent_t xRxEvent = { eNetworkRxEvent, NULL }; +const TickType_t xDescriptorWaitTime = pdMS_TO_TICKS( 250 ); +uint8_t *pucBuffer; + + pxDMARxDescriptor = xETH.RxDesc; + + if( ( pxDMARxDescriptor->Status & ETH_DMARXDESC_OWN) == 0 ) + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + xReceivedLength = ( ( pxDMARxDescriptor->Status & ETH_DMARXDESC_FL ) >> ETH_DMARXDESC_FRAMELENGTHSHIFT ) - 4; + + pucBuffer = (uint8_t *) pxDMARxDescriptor->Buffer1Addr; + + /* Update the ETHERNET DMA global Rx descriptor with next Rx descriptor */ + /* Chained Mode */ + /* Selects the next DMA Rx descriptor list for next buffer to read */ + xETH.RxDesc = ( ETH_DMADescTypeDef* )pxDMARxDescriptor->Buffer2NextDescAddr; + } + else + { + xReceivedLength = 0; + } + + /* Obtain the size of the packet and put it into the "usReceivedLength" variable. */ + + /* get received frame */ + if( xReceivedLength > 0ul ) + { + /* In order to make the code easier and faster, only packets in a single buffer + will be accepted. This can be done by making the buffers large enough to + hold a complete Ethernet packet (1536 bytes). + Therefore, two sanity checks: */ + configASSERT( xReceivedLength <= ETH_RX_BUF_SIZE ); + + if( ( pxDMARxDescriptor->Status & ( ETH_DMARXDESC_CE | ETH_DMARXDESC_IPV4HCE | ETH_DMARXDESC_FT ) ) != ETH_DMARXDESC_FT ) + { + /* Not an Ethernet frame-type or a checmsum error. */ + xAccepted = pdFALSE; + } + else + { + /* See if this packet must be handled. */ + xAccepted = xMayAcceptPacket( pucBuffer ); + } + + if( xAccepted != pdFALSE ) + { + /* The packet wil be accepted, but check first if a new Network Buffer can + be obtained. If not, the packet will still be dropped. */ + pxNewDescriptor = pxGetNetworkBufferWithDescriptor( ETH_RX_BUF_SIZE, xDescriptorWaitTime ); + + if( pxNewDescriptor == NULL ) + { + /* A new descriptor can not be allocated now. This packet will be dropped. */ + xAccepted = pdFALSE; + } + } + #if( ipconfigZERO_COPY_RX_DRIVER != 0 ) + { + /* Find out which Network Buffer was originally passed to the descriptor. */ + pxCurDescriptor = pxPacketBuffer_to_NetworkBuffer( pucBuffer ); + configASSERT( pxCurDescriptor != NULL ); + } + #else + { + /* In this mode, the two descriptors are the same. */ + pxCurDescriptor = pxNewDescriptor; + if( pxNewDescriptor != NULL ) + { + /* The packet is acepted and a new Network Buffer was created, + copy data to the Network Bufffer. */ + memcpy( pxNewDescriptor->pucEthernetBuffer, pucBuffer, xReceivedLength ); + } + } + #endif + + if( xAccepted != pdFALSE ) + { + pxCurDescriptor->xDataLength = xReceivedLength; + xRxEvent.pvData = ( void * ) pxCurDescriptor; + + /* Pass the data to the TCP/IP task for processing. */ + if( xSendEventStructToIPTask( &xRxEvent, xDescriptorWaitTime ) == pdFALSE ) + { + /* Could not send the descriptor into the TCP/IP stack, it + must be released. */ + vReleaseNetworkBufferAndDescriptor( pxCurDescriptor ); + iptraceETHERNET_RX_EVENT_LOST(); + } + else + { + iptraceNETWORK_INTERFACE_RECEIVE(); + } + } + + /* Release descriptors to DMA */ + #if( ipconfigZERO_COPY_RX_DRIVER != 0 ) + { + /* Set Buffer1 address pointer */ + if( pxNewDescriptor != NULL ) + { + pxDMARxDescriptor->Buffer1Addr = (uint32_t)pxNewDescriptor->pucEthernetBuffer; + } + else + { + /* The packet was dropped and the same Network + Buffer will be used to receive a new packet. */ + } + } + #endif /* ipconfigZERO_COPY_RX_DRIVER */ + + /* Set Buffer1 size and Second Address Chained bit */ + pxDMARxDescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | (uint32_t)ETH_RX_BUF_SIZE; + pxDMARxDescriptor->Status = ETH_DMARXDESC_OWN; + + /* Ensure completion of memory access */ + __DSB(); + /* When Rx Buffer unavailable flag is set clear it and resume + reception. */ + if( ( xETH.Instance->DMASR & ETH_DMASR_RBUS ) != 0 ) + { + /* Clear RBUS ETHERNET DMA flag. */ + xETH.Instance->DMASR = ETH_DMASR_RBUS; + + /* Resume DMA reception. */ + xETH.Instance->DMARPDR = 0; + } + } + + return ( xReceivedLength > 0 ); +} +/*-----------------------------------------------------------*/ + + +BaseType_t xSTM32_PhyRead( BaseType_t xAddress, BaseType_t xRegister, uint32_t *pulValue ) + { +uint16_t usPrevAddress = xETH.Init.PhyAddress; +BaseType_t xResult; +HAL_StatusTypeDef xHALResult; + + xETH.Init.PhyAddress = xAddress; + xHALResult = HAL_ETH_ReadPHYRegister( &xETH, ( uint16_t )xRegister, pulValue ); + xETH.Init.PhyAddress = usPrevAddress; + + if( xHALResult == HAL_OK ) + { + xResult = 0; + } + else + { + xResult = -1; + } + return xResult; + } +/*-----------------------------------------------------------*/ + +BaseType_t xSTM32_PhyWrite( BaseType_t xAddress, BaseType_t xRegister, uint32_t ulValue ) + { +uint16_t usPrevAddress = xETH.Init.PhyAddress; +BaseType_t xResult; +HAL_StatusTypeDef xHALResult; + + xETH.Init.PhyAddress = xAddress; + xHALResult = HAL_ETH_WritePHYRegister( &xETH, ( uint16_t )xRegister, ulValue ); + xETH.Init.PhyAddress = usPrevAddress; + + if( xHALResult == HAL_OK ) + { + xResult = 0; + } + else + { + xResult = -1; + } + return xResult; + } +/*-----------------------------------------------------------*/ + +void vMACBProbePhy( void ) +{ + vPhyInitialise( &xPhyObject, xSTM32_PhyRead, xSTM32_PhyWrite ); + xPhyDiscover( &xPhyObject ); + xPhyConfigure( &xPhyObject, &xPHYProperties ); +} +/*-----------------------------------------------------------*/ + +static void prvEthernetUpdateConfig( BaseType_t xForce ) +{ + FreeRTOS_printf( ( "prvEthernetUpdateConfig: LS mask %02lX Force %d\n", + xPhyObject.ulLinkStatusMask, + ( int )xForce ) ); + + if( ( xForce != pdFALSE ) || ( xPhyObject.ulLinkStatusMask != 0 ) ) + { + /* Restart the auto-negotiation. */ + if( xETH.Init.AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE ) + { + xPhyStartAutoNegotiation( &xPhyObject, xPhyGetMask( &xPhyObject ) ); + + /* Configure the MAC with the Duplex Mode fixed by the + auto-negotiation process. */ + if( xPhyObject.xPhyProperties.ucDuplex == PHY_DUPLEX_FULL ) + { + xETH.Init.DuplexMode = ETH_MODE_FULLDUPLEX; + } + else + { + xETH.Init.DuplexMode = ETH_MODE_HALFDUPLEX; + } + + /* Configure the MAC with the speed fixed by the + auto-negotiation process. */ + if( xPhyObject.xPhyProperties.ucSpeed == PHY_SPEED_10 ) + { + xETH.Init.Speed = ETH_SPEED_10M; + } + else + { + xETH.Init.Speed = ETH_SPEED_100M; + } + } + else /* AutoNegotiation Disable */ + { + /* Check parameters */ + assert_param( IS_ETH_SPEED( xETH.Init.Speed ) ); + assert_param( IS_ETH_DUPLEX_MODE( xETH.Init.DuplexMode ) ); + + if( xETH.Init.DuplexMode == ETH_MODE_FULLDUPLEX ) + { + xPhyObject.xPhyPreferences.ucDuplex = PHY_DUPLEX_HALF; + } + else + { + xPhyObject.xPhyPreferences.ucDuplex = PHY_DUPLEX_FULL; + } + + if( xETH.Init.Speed == ETH_SPEED_10M ) + { + xPhyObject.xPhyPreferences.ucSpeed = PHY_SPEED_10; + } + else + { + xPhyObject.xPhyPreferences.ucSpeed = PHY_SPEED_100; + } + + xPhyObject.xPhyPreferences.ucMDI_X = PHY_MDIX_AUTO; + + /* Use predefined (fixed) configuration. */ + xPhyFixedValue( &xPhyObject, xPhyGetMask( &xPhyObject ) ); + } + + /* ETHERNET MAC Re-Configuration */ + HAL_ETH_ConfigMAC( &xETH, (ETH_MACInitTypeDef *) NULL); + + /* Restart MAC interface */ + HAL_ETH_Start( &xETH); + } + else + { + /* Stop MAC interface */ + HAL_ETH_Stop( &xETH ); + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xGetPhyLinkStatus( void ) +{ +BaseType_t xReturn; + + if( xPhyObject.ulLinkStatusMask != 0 ) + { + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +/* Uncomment this in case BufferAllocation_1.c is used. */ + +#define niBUFFER_1_PACKET_SIZE 1536 + +void vNetworkInterfaceAllocateRAMToBuffers( NetworkBufferDescriptor_t pxNetworkBuffers[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ] ) +{ +static __attribute__ ((section(".first_data"))) uint8_t ucNetworkPackets[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS * niBUFFER_1_PACKET_SIZE ] __attribute__ ( ( aligned( 32 ) ) ); +uint8_t *ucRAMBuffer = ucNetworkPackets; +uint32_t ul; + + for( ul = 0; ul < ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS; ul++ ) + { + pxNetworkBuffers[ ul ].pucEthernetBuffer = ucRAMBuffer + ipBUFFER_PADDING; + *( ( unsigned * ) ucRAMBuffer ) = ( unsigned ) ( &( pxNetworkBuffers[ ul ] ) ); + ucRAMBuffer += niBUFFER_1_PACKET_SIZE; + } +} +/*-----------------------------------------------------------*/ + +static void prvEMACHandlerTask( void *pvParameters ) +{ +UBaseType_t uxLastMinBufferCount = 0; +#if( ipconfigCHECK_IP_QUEUE_SPACE != 0 ) +UBaseType_t uxLastMinQueueSpace = 0; +#endif +UBaseType_t uxCurrentCount; +BaseType_t xResult; +const TickType_t ulMaxBlockTime = pdMS_TO_TICKS( 100UL ); + + /* Remove compiler warnings about unused parameters. */ + ( void ) pvParameters; + + for( ;; ) + { + xResult = 0; + uxCurrentCount = uxGetMinimumFreeNetworkBuffers(); + if( uxLastMinBufferCount != uxCurrentCount ) + { + /* The logging produced below may be helpful + while tuning +TCP: see how many buffers are in use. */ + uxLastMinBufferCount = uxCurrentCount; + FreeRTOS_printf( ( "Network buffers: %lu lowest %lu\n", + uxGetNumberOfFreeNetworkBuffers(), uxCurrentCount ) ); + } + + if( xTXDescriptorSemaphore != NULL ) + { + static UBaseType_t uxLowestSemCount = ( UBaseType_t ) ETH_TXBUFNB - 1; + + uxCurrentCount = uxSemaphoreGetCount( xTXDescriptorSemaphore ); + if( uxLowestSemCount > uxCurrentCount ) + { + uxLowestSemCount = uxCurrentCount; + FreeRTOS_printf( ( "TX DMA buffers: lowest %lu\n", uxLowestSemCount ) ); + } + + } + + #if( ipconfigCHECK_IP_QUEUE_SPACE != 0 ) + { + uxCurrentCount = uxGetMinimumIPQueueSpace(); + if( uxLastMinQueueSpace != uxCurrentCount ) + { + /* The logging produced below may be helpful + while tuning +TCP: see how many buffers are in use. */ + uxLastMinQueueSpace = uxCurrentCount; + FreeRTOS_printf( ( "Queue space: lowest %lu\n", uxCurrentCount ) ); + } + } + #endif /* ipconfigCHECK_IP_QUEUE_SPACE */ + + if( ( ulISREvents & EMAC_IF_ALL_EVENT ) == 0 ) + { + /* No events to process now, wait for the next. */ + ulTaskNotifyTake( pdFALSE, ulMaxBlockTime ); + } + + if( ( ulISREvents & EMAC_IF_RX_EVENT ) != 0 ) + { + ulISREvents &= ~EMAC_IF_RX_EVENT; + + xResult = prvNetworkInterfaceInput(); + if( xResult > 0 ) + { + while( prvNetworkInterfaceInput() > 0 ) + { + } + } + } + + if( ( ulISREvents & EMAC_IF_TX_EVENT ) != 0 ) + { + /* Code to release TX buffers if zero-copy is used. */ + ulISREvents &= ~EMAC_IF_TX_EVENT; + /* Check if DMA packets have been delivered. */ + vClearTXBuffers(); + } + + if( ( ulISREvents & EMAC_IF_ERR_EVENT ) != 0 ) + { + /* Future extension: logging about errors that occurred. */ + ulISREvents &= ~EMAC_IF_ERR_EVENT; + } + if( xPhyCheckLinkStatus( &xPhyObject, xResult ) != 0 ) + { + /* Something has changed to a Link Status, need re-check. */ + prvEthernetUpdateConfig( pdFALSE ); + } + } +} +/*-----------------------------------------------------------*/ + +void ETH_IRQHandler( void ) +{ + HAL_ETH_IRQHandler( &xETH ); +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32Fxx/stm32f4xx_hal_eth.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32Fxx/stm32f4xx_hal_eth.c new file mode 100644 index 0000000..4388d12 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32Fxx/stm32f4xx_hal_eth.c @@ -0,0 +1,1833 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_eth.c + * @author MCD Application Team + * @version V1.3.2 + * @date 26-June-2015 + * @brief ETH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Ethernet (ETH) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#)Declare a ETH_HandleTypeDef handle structure, for example: + ETH_HandleTypeDef heth; + + (#)Fill parameters of Init structure in heth handle + + (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) + + (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API: + (##) Enable the Ethernet interface clock using + (+++) __HAL_RCC_ETHMAC_CLK_ENABLE(); + (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE(); + (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE(); + + (##) Initialize the related GPIO clocks + (##) Configure Ethernet pin-out + (##) Configure Ethernet NVIC interrupt (IT mode) + + (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers: + (##) HAL_ETH_DMATxDescListInit(); for Transmission process + (##) HAL_ETH_DMARxDescListInit(); for Reception process + + (#)Enable MAC and DMA transmission and reception: + (##) HAL_ETH_Start(); + + (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer + the frame to MAC TX FIFO: + (##) HAL_ETH_TransmitFrame(); + + (#)Poll for a received frame in ETH RX DMA Descriptors and get received + frame parameters + (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop) + + (#) Get a received frame when an ETH RX interrupt occurs: + (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only) + + (#) Communicate with external PHY device: + (##) Read a specific register from the PHY + HAL_ETH_ReadPHYRegister(); + (##) Write data to a specific RHY register: + HAL_ETH_WritePHYRegister(); + + (#) Configure the Ethernet MAC after ETH peripheral initialization + HAL_ETH_ConfigMAC(); all MAC parameters should be filled. + + (#) Configure the Ethernet DMA after ETH peripheral initialization + HAL_ETH_ConfigDMA(); all DMA parameters should be filled. + + -@- The PTP protocol and the DMA descriptors ring mode are not supported + in this driver + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +int lUDPLoggingPrintf( const char *pcFormatString, ... ); + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup ETH ETH + * @brief ETH HAL module driver + * @{ + */ + +#if !defined( ARRAY_SIZE ) + #define ARRAY_SIZE( x ) ( sizeof ( x ) / sizeof ( x )[ 0 ] ) +#endif + +#ifdef HAL_ETH_MODULE_ENABLED + +#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup ETH_Private_Constants ETH Private Constants + * @{ + */ +#define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */ +#define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */ + +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup ETH_Private_Functions ETH Private Functions + * @{ + */ +static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err); +static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr); +static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth); +static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth); +static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth); +static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth); +static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth); +static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth); +static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth); +static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth); +static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth); + +/** + * @} + */ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup ETH_Exported_Functions ETH Exported Functions + * @{ + */ + +/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the Ethernet peripheral + (+) De-initialize the Ethernet peripheral + + @endverbatim + * @{ + */ +extern void vMACBProbePhy ( void ); + +/** + * @brief Initializes the Ethernet MAC and DMA according to default + * parameters. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) +{ + uint32_t tmpreg = 0; + uint32_t hclk = 60000000; + uint32_t err = ETH_SUCCESS; + + /* Check the ETH peripheral state */ + if( heth == NULL ) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation)); + assert_param(IS_ETH_RX_MODE(heth->Init.RxMode)); + assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode)); + assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface)); + + if( heth->State == HAL_ETH_STATE_RESET ) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC. */ + HAL_ETH_MspInit( heth ); + } + + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Select MII or RMII Mode*/ + SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL); + SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface; + + /* Ethernet Software reset */ + /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ + /* After reset all the registers holds their respective reset values */ + /* Also enable EDFE: Enhanced descriptor format enable. */ + heth->Instance->DMABMR |= ETH_DMABMR_SR | ETH_DMABMR_EDE; + + /* Wait for software reset */ + while ((heth->Instance->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) + { + } + + /*-------------------------------- MAC Initialization ----------------------*/ + /* Get the ETHERNET MACMIIAR value */ + tmpreg = heth->Instance->MACMIIAR; + /* Clear CSR Clock Range CR[2:0] bits */ + tmpreg &= ETH_MACMIIAR_CR_MASK; + + /* Get hclk frequency value (168,000,000) */ + hclk = HAL_RCC_GetHCLKFreq(); + + /* Set CR bits depending on hclk value */ + if( ( hclk >= 20000000 ) && ( hclk < 35000000 ) ) + { + /* CSR Clock Range between 20-35 MHz */ + tmpreg |= (uint32_t) ETH_MACMIIAR_CR_Div16; + } + else if( ( hclk >= 35000000 ) && ( hclk < 60000000 ) ) + { + /* CSR Clock Range between 35-60 MHz */ + tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div26; + } + else if((hclk >= 60000000 ) && ( hclk < 100000000 ) ) + { + /* CSR Clock Range between 60-100 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; + } + else if((hclk >= 100000000 ) && ( hclk < 150000000)) + { + /* CSR Clock Range between 100-150 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62; + } + else /* ((hclk >= 150000000 ) && ( hclk <= 168000000)) */ + { + /* CSR Clock Range between 150-168 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102; + } + + /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ + heth->Instance->MACMIIAR = (uint32_t)tmpreg; + + /* Initialise the MACB and set all PHY properties */ + vMACBProbePhy(); + + /* Config MAC and DMA */ + ETH_MACDMAConfig(heth, err); + + /* Set ETH HAL State to Ready */ + heth->State= HAL_ETH_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief De-Initializes the ETH peripheral. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) +{ + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */ + HAL_ETH_MspDeInit( heth ); + + /* Set ETH HAL state to Disabled */ + heth->State= HAL_ETH_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK( heth ); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the DMA Tx descriptors in chain mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param DMATxDescTab: Pointer to the first Tx desc list + * @param TxBuff: Pointer to the first TxBuffer list + * @param TxBuffCount: Number of the used Tx desc in the list + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *pxDMATable, uint8_t *ucDataBuffer, uint32_t ulBufferCount) +{ + uint32_t i = 0; + ETH_DMADescTypeDef *pxDMADescriptor; + + /* Process Locked */ + __HAL_LOCK( heth ); + + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* Set the TxDesc pointer with the first one of the pxDMATable list */ + heth->TxDesc = pxDMATable; + + /* Fill each DMA descriptor with the right values */ + for( i=0; i < ulBufferCount; i++ ) + { + /* Get the pointer on the ith member of the descriptor list */ + pxDMADescriptor = pxDMATable + i; + + /* Set Second Address Chained bit */ + pxDMADescriptor->Status = ETH_DMATXDESC_TCH; + + pxDMADescriptor->ControlBufferSize = 0; + + /* Set Buffer1 address pointer */ + if( ucDataBuffer != NULL ) + { + pxDMADescriptor->Buffer1Addr = ( uint32_t )( &ucDataBuffer[ i * ETH_TX_BUF_SIZE ] ); + } + else + { + /* Buffer space is not provided because it uses zero-copy transmissions. */ + pxDMADescriptor->Buffer1Addr = ( uint32_t )0u; + } + + if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) + { + /* Set the DMA Tx descriptors checksum insertion for TCP, UDP, and ICMP */ + pxDMADescriptor->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL; + } + + /* Initialize the next descriptor with the Next Descriptor Polling Enable */ + if(i < ( ulBufferCount - 1 ) ) + { + /* Set next descriptor address register with next descriptor base address */ + pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) ( pxDMATable + i + 1 ); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) pxDMATable; + } + } + + /* Set Transmit Descriptor List Address Register */ + heth->Instance->DMATDLAR = ( uint32_t ) pxDMATable; + + /* Set ETH HAL State to Ready */ + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the DMA Rx descriptors in chain mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param DMARxDescTab: Pointer to the first Rx desc list + * @param RxBuff: Pointer to the first RxBuffer list + * @param RxBuffCount: Number of the used Rx desc in the list + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *pxDMATable, uint8_t *ucDataBuffer, uint32_t ulBufferCount) +{ + uint32_t i = 0; + ETH_DMADescTypeDef *pxDMADescriptor; + + /* Process Locked */ + __HAL_LOCK( heth ); + + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* Set the RxDesc pointer with the first one of the pxDMATable list */ + heth->RxDesc = pxDMATable; + + /* Fill each DMA descriptor with the right values */ + for(i=0; i < ulBufferCount; i++) + { + /* Get the pointer on the ith member of the descriptor list */ + pxDMADescriptor = pxDMATable+i; + + /* Set Own bit of the Rx descriptor Status */ + pxDMADescriptor->Status = ETH_DMARXDESC_OWN; + + /* Set Buffer1 size and Second Address Chained bit */ + pxDMADescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE; + + /* Set Buffer1 address pointer */ + if( ucDataBuffer != NULL ) + { + pxDMADescriptor->Buffer1Addr = ( uint32_t )( &ucDataBuffer[ i * ETH_RX_BUF_SIZE ] ); + } + else + { + /* Buffer space is not provided because it uses zero-copy reception. */ + pxDMADescriptor->Buffer1Addr = ( uint32_t )0u; + } + + if( heth->Init.RxMode == ETH_RXINTERRUPT_MODE ) + { + /* Enable Ethernet DMA Rx Descriptor interrupt */ + pxDMADescriptor->ControlBufferSize &= ~ETH_DMARXDESC_DIC; + } + + /* Initialize the next descriptor with the Next Descriptor Polling Enable */ + if(i < (ulBufferCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + pxDMADescriptor->Buffer2NextDescAddr = (uint32_t)(pxDMATable+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) pxDMATable; + } + } + + /* Set Receive Descriptor List Address Register */ + heth->Instance->DMARDLAR = ( uint32_t ) pxDMATable; + + /* Set ETH HAL State to Ready */ + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the ETH MSP. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes ETH MSP. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * + @verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Transmit a frame + HAL_ETH_TransmitFrame(); + (+) Receive a frame + HAL_ETH_GetReceivedFrame(); + HAL_ETH_GetReceivedFrame_IT(); + (+) Read from an External PHY register + HAL_ETH_ReadPHYRegister(); + (+) Write to an External PHY register + HAL_ETH_WritePHYRegister(); + + @endverbatim + + * @{ + */ + +/** + * @brief Sends an Ethernet frame. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param FrameLength: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength) +{ + uint32_t bufcount = 0, size = 0, i = 0; + __IO ETH_DMADescTypeDef *pxDmaTxDesc = heth->TxDesc; + /* Process Locked */ + __HAL_LOCK( heth ); + + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + if( FrameLength == 0 ) + { + /* Set ETH HAL state to READY */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + + return HAL_ERROR; + } + + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if( ( pxDmaTxDesc->Status & ETH_DMATXDESC_OWN ) != ( uint32_t ) RESET ) + { + /* OWN bit set */ + heth->State = HAL_ETH_STATE_BUSY_TX; + + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + + return HAL_ERROR; + } + + /* Get the number of needed Tx buffers for the current frame, rounding up. */ + bufcount = ( FrameLength + ETH_TX_BUF_SIZE - 1 ) / ETH_TX_BUF_SIZE; + + if (bufcount == 1) + { + /* Set LAST and FIRST segment */ + pxDmaTxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS; + /* Set frame size */ + pxDmaTxDesc->ControlBufferSize = ( FrameLength & ETH_DMATXDESC_TBS1 ); + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + pxDmaTxDesc->Status |= ETH_DMATXDESC_OWN; + /* Point to next descriptor */ + heth->TxDesc = ( ETH_DMADescTypeDef * ) ( heth->TxDesc->Buffer2NextDescAddr ); + } + else + { + for( i = 0; i < bufcount; i++ ) + { + /* Clear FIRST and LAST segment bits */ + uint32_t ulStatus = heth->TxDesc->Status & ~( ETH_DMATXDESC_FS | ETH_DMATXDESC_LS ); + + if( i == 0 ) + { + /* Setting the first segment bit */ + heth->TxDesc->Status = ulStatus | ETH_DMATXDESC_FS; + } + + /* Program size */ + if (i < (bufcount-1)) + { + heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1); + } + else + { + /* Setting the last segment bit */ + heth->TxDesc->Status = ulStatus | ETH_DMATXDESC_LS; + size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE; + heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1); + } + + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + heth->TxDesc->Status |= ETH_DMATXDESC_OWN; + /* point to next descriptor */ + heth->TxDesc = (ETH_DMADescTypeDef *)( heth->TxDesc->Buffer2NextDescAddr ); + } + } + + __DSB(); + + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if( ( heth->Instance->DMASR & ETH_DMASR_TBUS ) != ( uint32_t )RESET ) + { + heth->Instance->DMACHTDR = ( uint32_t )pxDmaTxDesc; + + /* Clear TBUS ETHERNET DMA flag */ + heth->Instance->DMASR = ETH_DMASR_TBUS; + /* Resume DMA transmission*/ + heth->Instance->DMATPDR = 0; + } + + /* Set ETH HAL State to Ready */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Checks for received frames. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT( ETH_HandleTypeDef *heth ) +{ + return HAL_ETH_GetReceivedFrame( heth ); +} + +HAL_StatusTypeDef HAL_ETH_GetReceivedFrame( ETH_HandleTypeDef *heth ) +{ +uint32_t ulCounter = 0; +ETH_DMADescTypeDef *pxDescriptor = heth->RxDesc; +HAL_StatusTypeDef xResult = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK( heth ); + + /* Check the ETH state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* Scan descriptors owned by CPU */ + while( ( ( pxDescriptor->Status & ETH_DMARXDESC_OWN ) == 0ul ) && ( ulCounter < ETH_RXBUFNB ) ) + { + uint32_t ulStatus = pxDescriptor->Status; + + /* Just for security. */ + ulCounter++; + + if( ( ulStatus & ( ETH_DMARXDESC_FS | ETH_DMARXDESC_LS ) ) == ( uint32_t )ETH_DMARXDESC_FS ) + { + /* First segment in frame, but not the last. */ + heth->RxFrameInfos.FSRxDesc = pxDescriptor; + heth->RxFrameInfos.LSRxDesc = ( ETH_DMADescTypeDef *)NULL; + heth->RxFrameInfos.SegCount = 1; + /* Point to next descriptor. */ + pxDescriptor = (ETH_DMADescTypeDef*) (pxDescriptor->Buffer2NextDescAddr); + heth->RxDesc = pxDescriptor; + } + else if( ( ulStatus & ( ETH_DMARXDESC_LS | ETH_DMARXDESC_FS ) ) == 0ul ) + { + /* This is an intermediate segment, not first, not last. */ + /* Increment segment count. */ + heth->RxFrameInfos.SegCount++; + /* Move to the next descriptor. */ + pxDescriptor = ( ETH_DMADescTypeDef * ) ( pxDescriptor->Buffer2NextDescAddr ); + heth->RxDesc = pxDescriptor; + } + /* Must be a last segment */ + else + { + /* This is the last segment. */ + /* Check if last segment is first segment: one segment contains the frame */ + if( heth->RxFrameInfos.SegCount == 0 ) + { + /* Remember the first segment. */ + heth->RxFrameInfos.FSRxDesc = pxDescriptor; + } + + /* Increment segment count */ + heth->RxFrameInfos.SegCount++; + + /* Remember the last segment. */ + heth->RxFrameInfos.LSRxDesc = pxDescriptor; + + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + heth->RxFrameInfos.length = + ( ( ulStatus & ETH_DMARXDESC_FL ) >> ETH_DMARXDESC_FRAMELENGTHSHIFT ) - 4; + + /* Get the address of the buffer start address */ + heth->RxFrameInfos.buffer = heth->RxFrameInfos.FSRxDesc->Buffer1Addr; + + /* Point to next descriptor */ + heth->RxDesc = ( ETH_DMADescTypeDef * ) pxDescriptor->Buffer2NextDescAddr; + + /* Return OK status: a packet was received. */ + xResult = HAL_OK; + break; + } + } + + /* Set ETH HAL State to Ready */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + + /* Return function status */ + return xResult; +} + +#if( STM32_ETHERNET_STATS != 0 ) + + volatile int rx_count, tx_count, int_count; + /** + * @brief This function handles ETH interrupt request. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ + volatile int int_counts[32]; + volatile int tx_status[8]; + volatile unsigned sr_history[32]; + volatile int sr_head; + #define STM32_STAT_INC( x ) do { ( x )++; } while( 0 ) + +#else + #define STM32_STAT_INC( x ) do { } while( 0 ) +#endif /* STM32_ETHERNET_STATS */ + +#define ETH_DMA_ALL_INTS \ + ( ETH_DMA_IT_TST | ETH_DMA_IT_PMT | ETH_DMA_IT_MMC | ETH_DMA_IT_NIS | ETH_DMA_IT_AIS | ETH_DMA_IT_ER | \ + ETH_DMA_IT_FBE | ETH_DMA_IT_ET | ETH_DMA_IT_RWT | ETH_DMA_IT_RPS | ETH_DMA_IT_RBU | ETH_DMA_IT_R | \ + ETH_DMA_IT_TU | ETH_DMA_IT_RO | ETH_DMA_IT_TJT | ETH_DMA_IT_TPS | ETH_DMA_IT_T ) + +//#define ETH_DMA_ALL_INTS ETH_DMA_IT_RBU | ETH_DMA_FLAG_T | ETH_DMA_FLAG_AIS + +#define INT_MASK ( ( uint32_t ) ~ ( ETH_DMA_IT_TBU ) ) +void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) +{ + uint32_t dmasr; + + STM32_STAT_INC( int_count ); + + dmasr = heth->Instance->DMASR & ETH_DMA_ALL_INTS; + heth->Instance->DMASR = dmasr; + +#if( STM32_ETHERNET_STATS != 0 ) + if( sr_head < ARRAY_SIZE( sr_history ) ) + { + sr_history[ sr_head++ ] = dmasr; + } + + { + int i; + for (i = 0; i < 32; i++) { + if (dmasr & (1u << i)) { + int_counts[i]++; + } + } + tx_status[ ( dmasr >> 20 ) & 0x07 ]++; + } +#endif + + /* Frame received */ + if( ( dmasr & ( ETH_DMA_FLAG_R | ETH_DMA_IT_RBU ) ) != 0 ) + { + /* Receive complete callback */ + HAL_ETH_RxCpltCallback( heth ); + STM32_STAT_INC( rx_count ); + } + /* Frame transmitted */ + if( ( dmasr & ( ETH_DMA_FLAG_T ) ) != 0 ) + { + /* Transfer complete callback */ + HAL_ETH_TxCpltCallback( heth ); + STM32_STAT_INC( tx_count ); + } + + /* ETH DMA Error */ + if( ( dmasr & ( ETH_DMA_FLAG_AIS ) ) != 0 ) + { + /* Ethernet Error callback */ + HAL_ETH_ErrorCallback( heth ); + } +} + +/** + * @brief Tx Transfer completed callbacks. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Ethernet transfer error callbacks + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Reads a PHY register + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. + * This parameter can be one of the following values: + * PHY_BCR: Transceiver Basic Control Register, + * PHY_BSR: Transceiver Basic Status Register. + * More PHY register could be read depending on the used PHY + * @param RegValue: PHY register value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue) +{ +uint32_t tmpreg = 0; +uint32_t tickstart = 0; +HAL_StatusTypeDef xResult; + + /* Check parameters */ + assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); + + /* Check the ETH peripheral state */ + if( heth->State == HAL_ETH_STATE_BUSY_RD ) + { + xResult = HAL_BUSY; + } + else + { + __HAL_LOCK( heth ); + + /* Set ETH HAL State to BUSY_RD */ + heth->State = HAL_ETH_STATE_BUSY_RD; + + /* Get the ETHERNET MACMIIAR value */ + tmpreg = heth->Instance->MACMIIAR; + + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg &= ~ETH_MACMIIAR_CR_MASK; + + /* Prepare the MII address register value */ + tmpreg |= ( ( ( uint32_t )heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA ); /* Set the PHY device address */ + tmpreg |= ( ( ( uint32_t )PHYReg << 6 ) & ETH_MACMIIAR_MR ); /* Set the PHY register address */ + tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */ + tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + + /* Write the result value into the MII Address register */ + heth->Instance->MACMIIAR = tmpreg; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check for the Busy flag */ + while( 1 ) + { + tmpreg = heth->Instance->MACMIIAR; + + if( ( tmpreg & ETH_MACMIIAR_MB ) == 0ul ) + { + /* Get MACMIIDR value */ + *RegValue = ( uint32_t ) heth->Instance->MACMIIDR; + xResult = HAL_OK; + break; + } + /* Check for the Timeout */ + if( ( HAL_GetTick( ) - tickstart ) > PHY_READ_TO ) + { + xResult = HAL_TIMEOUT; + break; + } + + } + + /* Set ETH HAL State to READY */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + } + + if( xResult != HAL_OK ) + { + lUDPLoggingPrintf( "ReadPHY: %d\n", xResult ); + } + /* Return function status */ + return xResult; +} + +/** + * @brief Writes to a PHY register. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. + * This parameter can be one of the following values: + * PHY_BCR: Transceiver Control Register. + * More PHY register could be written depending on the used PHY + * @param RegValue: the value to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue) +{ +uint32_t tmpreg = 0; +uint32_t tickstart = 0; +HAL_StatusTypeDef xResult; + + /* Check parameters */ + assert_param( IS_ETH_PHY_ADDRESS( heth->Init.PhyAddress ) ); + + /* Check the ETH peripheral state */ + if( heth->State == HAL_ETH_STATE_BUSY_WR ) + { + xResult = HAL_BUSY; + } + else + { + __HAL_LOCK( heth ); + + /* Set ETH HAL State to BUSY_WR */ + heth->State = HAL_ETH_STATE_BUSY_WR; + + /* Get the ETHERNET MACMIIAR value */ + tmpreg = heth->Instance->MACMIIAR; + + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg &= ~ETH_MACMIIAR_CR_MASK; + + /* Prepare the MII register address value */ + tmpreg |= ( ( ( uint32_t ) heth->Init.PhyAddress << 11 ) & ETH_MACMIIAR_PA ); /* Set the PHY device address */ + tmpreg |= ( ( ( uint32_t ) PHYReg << 6 ) & ETH_MACMIIAR_MR ); /* Set the PHY register address */ + tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */ + tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + + /* Give the value to the MII data register */ + heth->Instance->MACMIIDR = ( uint16_t ) RegValue; + + /* Write the result value into the MII Address register */ + heth->Instance->MACMIIAR = tmpreg; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check for the Busy flag */ + while( 1 ) + { + tmpreg = heth->Instance->MACMIIAR; + + if( ( tmpreg & ETH_MACMIIAR_MB ) == 0ul ) + { + xResult = HAL_OK; + break; + } + /* Check for the Timeout */ + if( ( HAL_GetTick( ) - tickstart ) > PHY_WRITE_TO ) + { + xResult = HAL_TIMEOUT; + break; + } + } + + /* Set ETH HAL State to READY */ + heth->State = HAL_ETH_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + } + + if( xResult != HAL_OK ) + { + lUDPLoggingPrintf( "WritePHY: %d\n", xResult ); + } + /* Return function status */ + return xResult; +} + +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Enable MAC and DMA transmission and reception. + HAL_ETH_Start(); + (+) Disable MAC and DMA transmission and reception. + HAL_ETH_Stop(); + (+) Set the MAC configuration in runtime mode + HAL_ETH_ConfigMAC(); + (+) Set the DMA configuration in runtime mode + HAL_ETH_ConfigDMA(); + +@endverbatim + * @{ + */ + + /** + * @brief Enables Ethernet MAC and DMA reception/transmission + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Start( ETH_HandleTypeDef *heth ) +{ + /* Process Locked */ + __HAL_LOCK( heth ); + + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* Enable transmit state machine of the MAC for transmission on the MII */ + ETH_MACTransmissionEnable( heth ); + + /* Enable receive state machine of the MAC for reception from the MII */ + ETH_MACReceptionEnable( heth ); + + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO( heth ); + + /* Start DMA transmission */ + ETH_DMATransmissionEnable( heth ); + + /* Start DMA reception */ + ETH_DMAReceptionEnable( heth ); + + /* Set the ETH state to READY*/ + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop Ethernet MAC and DMA reception/transmission + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) +{ + /* Process Locked */ + __HAL_LOCK( heth ); + + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* Stop DMA transmission */ + ETH_DMATransmissionDisable( heth ); + + /* Stop DMA reception */ + ETH_DMAReceptionDisable( heth ); + + /* Disable receive state machine of the MAC for reception from the MII */ + ETH_MACReceptionDisable( heth ); + + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO( heth ); + + /* Disable transmit state machine of the MAC for transmission on the MII */ + ETH_MACTransmissionDisable( heth ); + + /* Set the ETH state*/ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + + /* Return function status */ + return HAL_OK; +} + +static void prvWriteMACFCR( ETH_HandleTypeDef *heth, uint32_t ulValue) +{ + /* Enable the MAC transmission */ + heth->Instance->MACFCR = ulValue; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles. + Read it back, wait a ms and */ + ( void ) heth->Instance->MACFCR; + + HAL_Delay( ETH_REG_WRITE_DELAY ); + + heth->Instance->MACFCR = ulValue; +} + +static void prvWriteDMAOMR( ETH_HandleTypeDef *heth, uint32_t ulValue) +{ + /* Enable the MAC transmission */ + heth->Instance->DMAOMR = ulValue; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles. + Read it back, wait a ms and */ + ( void ) heth->Instance->DMAOMR; + + HAL_Delay( ETH_REG_WRITE_DELAY ); + + heth->Instance->DMAOMR = ulValue; +} + +static void prvWriteMACCR( ETH_HandleTypeDef *heth, uint32_t ulValue) +{ + /* Enable the MAC transmission */ + heth->Instance->MACCR = ulValue; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles. + Read it back, wait a ms and */ + ( void ) heth->Instance->MACCR; + + HAL_Delay( ETH_REG_WRITE_DELAY ); + + heth->Instance->MACCR = ulValue; +} + +/** + * @brief Set ETH MAC Configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param macconf: MAC Configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf) +{ + uint32_t tmpreg = 0; + + /* Process Locked */ + __HAL_LOCK( heth ); + + /* Set the ETH peripheral state to BUSY */ + heth->State= HAL_ETH_STATE_BUSY; + + assert_param(IS_ETH_SPEED(heth->Init.Speed)); + assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); + + if (macconf != NULL) + { + /* Check the parameters */ + assert_param(IS_ETH_WATCHDOG(macconf->Watchdog)); + assert_param(IS_ETH_JABBER(macconf->Jabber)); + assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap)); + assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense)); + assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn)); + assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode)); + assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload)); + assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission)); + assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip)); + assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit)); + assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck)); + assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll)); + assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter)); + assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames)); + assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception)); + assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter)); + assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode)); + assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter)); + assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter)); + assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime)); + assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause)); + assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold)); + assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect)); + assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl)); + assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl)); + assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison)); + assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier)); + + /*------------------------ ETHERNET MACCR Configuration --------------------*/ + /* Get the ETHERNET MACCR value */ + tmpreg = heth->Instance->MACCR; + /* Clear WD, PCE, PS, TE and RE bits */ + tmpreg &= ETH_MACCR_CLEAR_MASK; + + tmpreg |= (uint32_t)( + macconf->Watchdog | + macconf->Jabber | + macconf->InterFrameGap | + macconf->CarrierSense | + heth->Init.Speed | + macconf->ReceiveOwn | + macconf->LoopbackMode | + heth->Init.DuplexMode | + macconf->ChecksumOffload | + macconf->RetryTransmission | + macconf->AutomaticPadCRCStrip | + macconf->BackOffLimit | + macconf->DeferralCheck); + + /* Write to ETHERNET MACCR */ + prvWriteMACCR( heth, tmpreg ); + + /*----------------------- ETHERNET MACFFR Configuration --------------------*/ + /* Write to ETHERNET MACFFR */ + heth->Instance->MACFFR = (uint32_t)( + macconf->ReceiveAll | + macconf->SourceAddrFilter | + macconf->PassControlFrames | + macconf->BroadcastFramesReception | + macconf->DestinationAddrFilter | + macconf->PromiscuousMode | + macconf->MulticastFramesFilter | + macconf->UnicastFramesFilter); + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg = heth->Instance->MACFFR; + HAL_Delay(ETH_REG_WRITE_DELAY); + heth->Instance->MACFFR = tmpreg; + + /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ + /* Write to ETHERNET MACHTHR */ + heth->Instance->MACHTHR = (uint32_t)macconf->HashTableHigh; + + /* Write to ETHERNET MACHTLR */ + heth->Instance->MACHTLR = (uint32_t)macconf->HashTableLow; + /*----------------------- ETHERNET MACFCR Configuration --------------------*/ + + /* Get the ETHERNET MACFCR value */ + tmpreg = heth->Instance->MACFCR; + /* Clear xx bits */ + tmpreg &= ETH_MACFCR_CLEAR_MASK; + + tmpreg |= (uint32_t)(( + macconf->PauseTime << 16) | + macconf->ZeroQuantaPause | + macconf->PauseLowThreshold | + macconf->UnicastPauseFrameDetect | + macconf->ReceiveFlowControl | + macconf->TransmitFlowControl); + + /* Write to ETHERNET MACFCR */ + prvWriteMACFCR( heth, tmpreg ); + + /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ + heth->Instance->MACVLANTR = (uint32_t)(macconf->VLANTagComparison | + macconf->VLANTagIdentifier); + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg = heth->Instance->MACVLANTR; + HAL_Delay(ETH_REG_WRITE_DELAY); + heth->Instance->MACVLANTR = tmpreg; + } + else /* macconf == NULL : here we just configure Speed and Duplex mode */ + { + /*------------------------ ETHERNET MACCR Configuration --------------------*/ + /* Get the ETHERNET MACCR value */ + tmpreg = heth->Instance->MACCR; + + /* Clear FES and DM bits */ + tmpreg &= ~((uint32_t)0x00004800); + + tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode); + + /* Write to ETHERNET MACCR */ + prvWriteMACCR( heth, tmpreg ); + } + + /* Set the ETH state to Ready */ + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Sets ETH DMA Configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param dmaconf: DMA Configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf) +{ + uint32_t tmpreg = 0; + + /* Process Locked */ + __HAL_LOCK( heth ); + + /* Set the ETH peripheral state to BUSY */ + heth->State= HAL_ETH_STATE_BUSY; + + /* Check parameters */ + assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame)); + assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward)); + assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame)); + assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward)); + assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl)); + assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames)); + assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames)); + assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl)); + assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate)); + assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats)); + assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst)); + assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength)); + assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength)); + assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat)); + assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength)); + assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration)); + + /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ + /* Get the ETHERNET DMAOMR value */ + tmpreg = heth->Instance->DMAOMR; + /* Clear xx bits */ + tmpreg &= ETH_DMAOMR_CLEAR_MASK; + + tmpreg |= (uint32_t)( + dmaconf->DropTCPIPChecksumErrorFrame | + dmaconf->ReceiveStoreForward | + dmaconf->FlushReceivedFrame | + dmaconf->TransmitStoreForward | + dmaconf->TransmitThresholdControl | + dmaconf->ForwardErrorFrames | + dmaconf->ForwardUndersizedGoodFrames | + dmaconf->ReceiveThresholdControl | + dmaconf->SecondFrameOperate); + + /* Write to ETHERNET DMAOMR */ + prvWriteDMAOMR( heth, tmpreg ); + + /*----------------------- ETHERNET DMABMR Configuration --------------------*/ + heth->Instance->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats | + dmaconf->FixedBurst | + dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ + dmaconf->TxDMABurstLength | + dmaconf->EnhancedDescriptorFormat | + (dmaconf->DescriptorSkipLength << 2) | + dmaconf->DMAArbitration | + ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg = heth->Instance->DMABMR; + HAL_Delay(ETH_REG_WRITE_DELAY); + heth->Instance->DMABMR = tmpreg; + + /* Set the ETH state to Ready */ + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK( heth ); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * + @verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + (+) Get the ETH handle state: + HAL_ETH_GetState(); + + + @endverbatim + * @{ + */ + +/** + * @brief Return the ETH HAL state + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL state + */ +HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) +{ + /* Return ETH state */ + return heth->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup ETH_Private_Functions + * @{ + */ + +/** + * @brief Configures Ethernet MAC and DMA with default parameters. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param err: Ethernet Init error + * @retval HAL status + */ +static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) +{ + ETH_MACInitTypeDef macinit; + ETH_DMAInitTypeDef dmainit; + uint32_t tmpreg = 0; + + if (err != ETH_SUCCESS) /* Auto-negotiation failed */ + { + /* Set Ethernet duplex mode to Full-duplex */ + heth->Init.DuplexMode = ETH_MODE_FULLDUPLEX; + + /* Set Ethernet speed to 100M */ + heth->Init.Speed = ETH_SPEED_100M; + } + + /* Ethernet MAC default initialization **************************************/ + macinit.Watchdog = ETH_WATCHDOG_ENABLE; + macinit.Jabber = ETH_JABBER_ENABLE; + macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT; + macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE; + macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE; + macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE; + if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) + { + macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; + } + else + { + macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE; + } + macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE; + macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE; + macinit.BackOffLimit = ETH_BACKOFFLIMIT_10; + macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE; + macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE; + macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE; + macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL; + macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE; + macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL; + macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE; + macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT; + macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT; + macinit.HashTableHigh = 0x0; + macinit.HashTableLow = 0x0; + macinit.PauseTime = 0x0; + macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE; + macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4; + macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE; + macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE; + macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE; + macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT; + macinit.VLANTagIdentifier = 0x0; + + /*------------------------ ETHERNET MACCR Configuration --------------------*/ + /* Get the ETHERNET MACCR value */ + tmpreg = heth->Instance->MACCR; + /* Clear WD, PCE, PS, TE and RE bits */ + tmpreg &= ETH_MACCR_CLEAR_MASK; + /* Set the WD bit according to ETH Watchdog value */ + /* Set the JD: bit according to ETH Jabber value */ + /* Set the IFG bit according to ETH InterFrameGap value */ + /* Set the DCRS bit according to ETH CarrierSense value */ + /* Set the FES bit according to ETH Speed value */ + /* Set the DO bit according to ETH ReceiveOwn value */ + /* Set the LM bit according to ETH LoopbackMode value */ + /* Set the DM bit according to ETH Mode value */ + /* Set the IPCO bit according to ETH ChecksumOffload value */ + /* Set the DR bit according to ETH RetryTransmission value */ + /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */ + /* Set the BL bit according to ETH BackOffLimit value */ + /* Set the DC bit according to ETH DeferralCheck value */ + tmpreg |= (uint32_t)(macinit.Watchdog | + macinit.Jabber | + macinit.InterFrameGap | + macinit.CarrierSense | + heth->Init.Speed | + macinit.ReceiveOwn | + macinit.LoopbackMode | + heth->Init.DuplexMode | + macinit.ChecksumOffload | + macinit.RetryTransmission | + macinit.AutomaticPadCRCStrip | + macinit.BackOffLimit | + macinit.DeferralCheck); + + /* Write to ETHERNET MACCR */ + prvWriteMACCR( heth, tmpreg ); + + /*----------------------- ETHERNET MACFFR Configuration --------------------*/ + /* Set the RA bit according to ETH ReceiveAll value */ + /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */ + /* Set the PCF bit according to ETH PassControlFrames value */ + /* Set the DBF bit according to ETH BroadcastFramesReception value */ + /* Set the DAIF bit according to ETH DestinationAddrFilter value */ + /* Set the PR bit according to ETH PromiscuousMode value */ + /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */ + /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */ + /* Write to ETHERNET MACFFR */ + heth->Instance->MACFFR = (uint32_t)(macinit.ReceiveAll | + macinit.SourceAddrFilter | + macinit.PassControlFrames | + macinit.BroadcastFramesReception | + macinit.DestinationAddrFilter | + macinit.PromiscuousMode | + macinit.MulticastFramesFilter | + macinit.UnicastFramesFilter); + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg = heth->Instance->MACFFR; + HAL_Delay(ETH_REG_WRITE_DELAY); + heth->Instance->MACFFR = tmpreg; + + /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/ + /* Write to ETHERNET MACHTHR */ + heth->Instance->MACHTHR = (uint32_t)macinit.HashTableHigh; + + /* Write to ETHERNET MACHTLR */ + heth->Instance->MACHTLR = (uint32_t)macinit.HashTableLow; + /*----------------------- ETHERNET MACFCR Configuration -------------------*/ + + /* Get the ETHERNET MACFCR value */ + tmpreg = heth->Instance->MACFCR; + /* Clear xx bits */ + tmpreg &= ETH_MACFCR_CLEAR_MASK; + + /* Set the PT bit according to ETH PauseTime value */ + /* Set the DZPQ bit according to ETH ZeroQuantaPause value */ + /* Set the PLT bit according to ETH PauseLowThreshold value */ + /* Set the UP bit according to ETH UnicastPauseFrameDetect value */ + /* Set the RFE bit according to ETH ReceiveFlowControl value */ + /* Set the TFE bit according to ETH TransmitFlowControl value */ + tmpreg |= (uint32_t)((macinit.PauseTime << 16) | + macinit.ZeroQuantaPause | + macinit.PauseLowThreshold | + macinit.UnicastPauseFrameDetect | + macinit.ReceiveFlowControl | + macinit.TransmitFlowControl); + + /* Write to ETHERNET MACFCR */ + prvWriteMACFCR( heth, tmpreg ); + + /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/ + /* Set the ETV bit according to ETH VLANTagComparison value */ + /* Set the VL bit according to ETH VLANTagIdentifier value */ + heth->Instance->MACVLANTR = (uint32_t)(macinit.VLANTagComparison | + macinit.VLANTagIdentifier); + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg = heth->Instance->MACVLANTR; + HAL_Delay(ETH_REG_WRITE_DELAY); + heth->Instance->MACVLANTR = tmpreg; + + /* Ethernet DMA default initialization ************************************/ + dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE; + dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE; + dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE; + dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE; + dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES; + dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE; + dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE; + dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES; + dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE; + dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE; + dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE; + dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; + dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; + dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE; + dmainit.DescriptorSkipLength = 0x0; + dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; + + /* Get the ETHERNET DMAOMR value */ + tmpreg = heth->Instance->DMAOMR; + /* Clear xx bits */ + tmpreg &= ETH_DMAOMR_CLEAR_MASK; + + /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */ + /* Set the RSF bit according to ETH ReceiveStoreForward value */ + /* Set the DFF bit according to ETH FlushReceivedFrame value */ + /* Set the TSF bit according to ETH TransmitStoreForward value */ + /* Set the TTC bit according to ETH TransmitThresholdControl value */ + /* Set the FEF bit according to ETH ForwardErrorFrames value */ + /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */ + /* Set the RTC bit according to ETH ReceiveThresholdControl value */ + /* Set the OSF bit according to ETH SecondFrameOperate value */ + tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | + dmainit.ReceiveStoreForward | + dmainit.FlushReceivedFrame | + dmainit.TransmitStoreForward | + dmainit.TransmitThresholdControl | + dmainit.ForwardErrorFrames | + dmainit.ForwardUndersizedGoodFrames | + dmainit.ReceiveThresholdControl | + dmainit.SecondFrameOperate); + + /* Write to ETHERNET DMAOMR */ + prvWriteDMAOMR( heth, tmpreg ); + + /*----------------------- ETHERNET DMABMR Configuration ------------------*/ + /* Set the AAL bit according to ETH AddressAlignedBeats value */ + /* Set the FB bit according to ETH FixedBurst value */ + /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */ + /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */ + /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/ + /* Set the DSL bit according to ETH DesciptorSkipLength value */ + /* Set the PR and DA bits according to ETH DMAArbitration value */ + heth->Instance->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats | + dmainit.FixedBurst | + dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ + dmainit.TxDMABurstLength | + dmainit.EnhancedDescriptorFormat | + (dmainit.DescriptorSkipLength << 2) | + dmainit.DMAArbitration | + ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg = heth->Instance->DMABMR; + HAL_Delay(ETH_REG_WRITE_DELAY); + heth->Instance->DMABMR = tmpreg; + + if(heth->Init.RxMode == ETH_RXINTERRUPT_MODE) + { + /* Enable the Ethernet Rx Interrupt */ + __HAL_ETH_DMA_ENABLE_IT(( heth ), ETH_DMA_IT_NIS | ETH_DMA_IT_R); + } + + /* Initialize MAC address in ethernet MAC */ + ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr); +} + +/** + * @brief Configures the selected MAC address. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param MacAddr: The MAC address to configure + * This parameter can be one of the following values: + * @arg ETH_MAC_Address0: MAC Address0 + * @arg ETH_MAC_Address1: MAC Address1 + * @arg ETH_MAC_Address2: MAC Address2 + * @arg ETH_MAC_Address3: MAC Address3 + * @param Addr: Pointer to MAC address buffer data (6 bytes) + * @retval HAL status + */ +static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param( IS_ETH_MAC_ADDRESS0123( MacAddr ) ); + + /* Calculate the selected MAC address high register */ + tmpreg = 0x80000000ul | ( ( uint32_t )Addr[ 5 ] << 8) | (uint32_t)Addr[ 4 ]; + /* Load the selected MAC address high register */ + ( * ( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_HBASE + MacAddr ) ) ) = tmpreg; + /* Calculate the selected MAC address low register */ + tmpreg = ( ( uint32_t )Addr[ 3 ] << 24 ) | ( ( uint32_t )Addr[ 2 ] << 16 ) | ( ( uint32_t )Addr[ 1 ] << 8 ) | Addr[ 0 ]; + + /* Load the selected MAC address low register */ + ( * ( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_LBASE + MacAddr ) ) ) = tmpreg; +} + +/** + * @brief Enables the MAC transmission. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth) +{ + uint32_t tmpreg = heth->Instance->MACCR | ETH_MACCR_TE; + + prvWriteMACCR( heth, tmpreg ); +} + +/** + * @brief Disables the MAC transmission. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth) +{ + uint32_t tmpreg = heth->Instance->MACCR & ~( ETH_MACCR_TE ); + + prvWriteMACCR( heth, tmpreg ); +} + +/** + * @brief Enables the MAC reception. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth) +{ + __IO uint32_t tmpreg = heth->Instance->MACCR | ETH_MACCR_RE; + + prvWriteMACCR( heth, tmpreg ); +} + +/** + * @brief Disables the MAC reception. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth) +{ + __IO uint32_t tmpreg = heth->Instance->MACCR & ~( ETH_MACCR_RE ); + + prvWriteMACCR( heth, tmpreg ); +} + +/** + * @brief Enables the DMA transmission. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth) +{ + /* Enable the DMA transmission */ + __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_ST; + + prvWriteDMAOMR( heth, tmpreg ); +} + +/** + * @brief Disables the DMA transmission. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth) +{ + /* Disable the DMA transmission */ + __IO uint32_t tmpreg = heth->Instance->DMAOMR & ~( ETH_DMAOMR_ST ); + + prvWriteDMAOMR( heth, tmpreg ); +} + +/** + * @brief Enables the DMA reception. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth) +{ + /* Enable the DMA reception */ + __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_SR; + + prvWriteDMAOMR( heth, tmpreg ); +} + +/** + * @brief Disables the DMA reception. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth) +{ + /* Disable the DMA reception */ + __IO uint32_t tmpreg = heth->Instance->DMAOMR & ~( ETH_DMAOMR_SR ); + + prvWriteDMAOMR( heth, tmpreg ); +} + +/** + * @brief Clears the ETHERNET transmit FIFO. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth) +{ + /* Set the Flush Transmit FIFO bit */ + __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_FTF; + + prvWriteDMAOMR( heth, tmpreg ); +} + +/** + * @} + */ + +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* HAL_ETH_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32Fxx/stm32f4xx_hal_eth.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32Fxx/stm32f4xx_hal_eth.h new file mode 100644 index 0000000..93b9caf --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/STM32Fxx/stm32f4xx_hal_eth.h @@ -0,0 +1,6 @@ +/* + * The Ethernet header files for STM32F2, STM32F4 and STM32F7 have been merged to + * a single module that works for both parts: "stm32fxx_hal_eth" + */ + +#include "stm32fxx_hal_eth.h" diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/WinPCap/FaultInjection.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/WinPCap/FaultInjection.c new file mode 100644 index 0000000..e100a4e --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/WinPCap/FaultInjection.c @@ -0,0 +1,173 @@ +#define xBUFFER_CACHE_SIZE 10 +#define xMAX_FAULT_INJECTION_RATE 15 +#define xMIN_FAULT_INJECTION_RATE 3 +#define xNUM_FAULT_TYPES 1 + +static NetworkBufferDescriptor_t *xNetworkBufferCache[ xBUFFER_CACHE_SIZE ] = { 0 }; + +#define xFAULT_LOG_SIZE 2048 +uint32_t ulInjectedFault[ xFAULT_LOG_SIZE ]; +uint32_t ulFaultLogIndex = 0; + +static BaseType_t prvCachePacket( NetworkBufferDescriptor_t *pxNetworkBufferIn ) +{ +BaseType_t x, xReturn = pdFALSE; + + for( x = 0; x < xBUFFER_CACHE_SIZE; x++ ) + { + if( xNetworkBufferCache[ x ] == NULL ) + { + xNetworkBufferCache[ x ] = pxNetworkBufferIn; + xReturn = pdTRUE; + break; + } + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static NetworkBufferDescriptor_t *prvGetCachedPacket( void ) +{ +BaseType_t x; +NetworkBufferDescriptor_t *pxReturn = NULL; + + for( x = ( xBUFFER_CACHE_SIZE - 1 ); x >= 0; x-- ) + { + if( xNetworkBufferCache[ x ] != NULL ) + { + pxReturn = xNetworkBufferCache[ x ]; + xNetworkBufferCache[ x ] = NULL; + break; + } + } + + return pxReturn; +} +/*-----------------------------------------------------------*/ + +static NetworkBufferDescriptor_t *prvDuplicatePacket( NetworkBufferDescriptor_t * pxOriginalPacket, const uint8_t *pucPacketData ) +{ +NetworkBufferDescriptor_t *pxReturn; + + /* Obtain a new descriptor. */ + pxReturn = pxGetNetworkBufferWithDescriptor( pxOriginalPacket->xDataLength, 0 ); + + if( pxReturn != NULL ) + { + /* Copy in the packet data. */ + pxReturn->xDataLength = pxOriginalPacket->xDataLength; + memcpy( pxReturn->pucEthernetBuffer, pucPacketData, pxOriginalPacket->xDataLength ); + } + + return pxReturn; +} +/*-----------------------------------------------------------*/ + +static NetworkBufferDescriptor_t *prvRxFaultInjection( NetworkBufferDescriptor_t *pxNetworkBufferIn, const uint8_t *pucPacketData ) +{ +static uint32_t ulCallCount = 0, ulNextFaultCallCount = 0; +NetworkBufferDescriptor_t *pxReturn = pxNetworkBufferIn; +IPStackEvent_t xRxEvent = { eNetworkRxEvent, NULL }; +uint32_t ulFault; + +return pxNetworkBufferIn; + + ulCallCount++; + + if( ulCallCount > ulNextFaultCallCount ) + { + ulNextFaultCallCount = ipconfigRAND32() % xMAX_FAULT_INJECTION_RATE; + if( ulNextFaultCallCount < xMIN_FAULT_INJECTION_RATE ) + { + ulNextFaultCallCount = xMIN_FAULT_INJECTION_RATE; + } + + ulCallCount = 0; + + ulFault = ipconfigRAND32() % xNUM_FAULT_TYPES; + + if( ulFaultLogIndex < xFAULT_LOG_SIZE ) + { + ulInjectedFault[ ulFaultLogIndex ] = ulFault; + ulFaultLogIndex++; + } + + switch( ulFault ) + { + case 0: + /* Just drop the packet. */ + vReleaseNetworkBufferAndDescriptor( pxNetworkBufferIn ); + pxReturn = NULL; + break; + + case 1: + /* Store the packet in the cache for later. */ + if( prvCachePacket( pxNetworkBufferIn ) == pdTRUE ) + { + /* The packet may get sent later, it is not being sent + now. */ + pxReturn = NULL; + } + break; + + case 2: + /* Send a cached packet. */ + pxReturn = prvGetCachedPacket(); + if( pxReturn != NULL ) + { + /* A cached packet was obtained so drop the original + packet. */ + vReleaseNetworkBufferAndDescriptor( pxNetworkBufferIn ); + } + else + { + /* Could not obtain a packet from the cache so just return + the packet that was passed in. */ + pxReturn = pxNetworkBufferIn; + } + break; + + case 4: + + /* Send a duplicate of the packet right away. */ + pxReturn = prvDuplicatePacket( pxNetworkBufferIn, pucPacketData ); + + /* Send the original packet to the stack. */ + xRxEvent.pvData = ( void * ) pxNetworkBufferIn; + if( xSendEventStructToIPTask( &xRxEvent, ( TickType_t ) 0 ) == pdFAIL ) + { + vReleaseNetworkBufferAndDescriptor( pxNetworkBufferIn ); + } + break; + + case 5: + + /* Send both a cached packet and the current packet. */ + xRxEvent.pvData = ( void * ) prvGetCachedPacket(); + if( xRxEvent.pvData != NULL ) + { + if( xSendEventStructToIPTask( &xRxEvent, ( TickType_t ) 0 ) == pdFAIL ) + { + vReleaseNetworkBufferAndDescriptor( pxNetworkBufferIn ); + } + } + break; + + case 6: + case 7: + case 8: + /* Store the packet in the cache for later. */ + if( prvCachePacket( pxNetworkBufferIn ) == pdTRUE ) + { + /* The packet may get sent later, it is not being sent + now. */ + pxReturn = NULL; + } + break; + } + } + + return pxReturn; +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/WinPCap/NetworkInterface.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/WinPCap/NetworkInterface.c new file mode 100644 index 0000000..78b3bdf --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/WinPCap/NetworkInterface.c @@ -0,0 +1,636 @@ +/* +FreeRTOS+TCP V2.0.11 +Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + http://aws.amazon.com/freertos + http://www.FreeRTOS.org +*/ + +/* WinPCap includes. */ +#define HAVE_REMOTE +#include "pcap.h" + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_IP_Private.h" +#include "NetworkBufferManagement.h" + +/* Thread-safe circular buffers are being used to pass data to and from the PCAP +access functions. */ +#include "Win32-Extensions.h" +#include "FreeRTOS_Stream_Buffer.h" + +/* Sizes of the thread safe circular buffers used to pass data to and from the +WinPCAP Windows threads. */ +#define xSEND_BUFFER_SIZE 32768 +#define xRECV_BUFFER_SIZE 32768 + +/* If ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES is set to 1, then the Ethernet +driver will filter incoming packets and only pass the stack those packets it +considers need processing. */ +#if( ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES == 0 ) + #define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eProcessBuffer +#else + #define ipCONSIDER_FRAME_FOR_PROCESSING( pucEthernetBuffer ) eConsiderFrameForProcessing( ( pucEthernetBuffer ) ) +#endif + +/* Used to insert test code only. */ +#define niDISRUPT_PACKETS 0 + +/*-----------------------------------------------------------*/ + +/* + * Windows threads that are outside of the control of the FreeRTOS simulator are + * used to interface with the WinPCAP libraries. + */ +DWORD WINAPI prvWinPcapRecvThread( void *pvParam ); +DWORD WINAPI prvWinPcapSendThread( void *pvParam ); + +/* + * Print out a numbered list of network interfaces that are available on the + * host computer. + */ +static pcap_if_t * prvPrintAvailableNetworkInterfaces( void ); + +/* + * Open the network interface. The number of the interface to be opened is set + * by the configNETWORK_INTERFACE_TO_USE constant in FreeRTOSConfig.h. + */ +static void prvOpenSelectedNetworkInterface( pcap_if_t *pxAllNetworkInterfaces ); +static int prvOpenInterface( const char *pucName ); + +/* + * Configure the capture filter to allow blocking reads, and to filter out + * packets that are not of interest to this demo. + */ +static void prvConfigureCaptureBehaviour( void ); + +/* + * A function that simulates Ethernet interrupts by periodically polling the + * WinPCap interface for new data. + */ +static void prvInterruptSimulatorTask( void *pvParameters ); + +/* + * Create the buffers that are used to pass data between the FreeRTOS simulator + * and the Win32 threads that manage WinPCAP. + */ +static void prvCreateThreadSafeBuffers( void ); + +/* + * Utility function used to format print messages only. + */ +static const char *prvRemoveSpaces( char *pcBuffer, int aBuflen, const char *pcMessage ); + +/*-----------------------------------------------------------*/ + +/* Required by the WinPCap library. */ +static char cErrorBuffer[ PCAP_ERRBUF_SIZE ]; + +/* An event used to wake up the Win32 thread that sends data through the WinPCAP +library. */ +static void *pvSendEvent = NULL; + +/* _HT_ made the PCAP interface number configurable through the program's +parameters in order to test in different machines. */ +static BaseType_t xConfigNextworkInterfaceToUse = configNETWORK_INTERFACE_TO_USE; + +/* Handles to the Windows threads that handle the PCAP IO. */ +static HANDLE vWinPcapRecvThreadHandle = NULL; +static HANDLE vWinPcapSendThreadHandle = NULL;; + +/* The interface being used by WinPCap. */ +static pcap_t *pxOpenedInterfaceHandle = NULL; + +/* Circular buffers used by the PCAP Win32 threads. */ +static StreamBuffer_t *xSendBuffer = NULL; +static StreamBuffer_t *xRecvBuffer = NULL; + +/* The MAC address initially set to the constants defined in FreeRTOSConfig.h. */ +extern uint8_t ucMACAddress[ 6 ]; + +/* Logs the number of WinPCAP send failures, for viewing in the debugger only. */ +static volatile uint32_t ulWinPCAPSendFailures = 0; + +/*-----------------------------------------------------------*/ + +BaseType_t xNetworkInterfaceInitialise( void ) +{ +BaseType_t xReturn = pdFALSE; +pcap_if_t *pxAllNetworkInterfaces; + + /* Query the computer the simulation is being executed on to find the + network interfaces it has installed. */ + pxAllNetworkInterfaces = prvPrintAvailableNetworkInterfaces(); + + /* Open the network interface. The number of the interface to be opened is + set by the configNETWORK_INTERFACE_TO_USE constant in FreeRTOSConfig.h. + Calling this function will set the pxOpenedInterfaceHandle variable. If, + after calling this function, pxOpenedInterfaceHandle is equal to NULL, then + the interface could not be opened. */ + if( pxAllNetworkInterfaces != NULL ) + { + prvOpenSelectedNetworkInterface( pxAllNetworkInterfaces ); + } + + if( pxOpenedInterfaceHandle != NULL ) + { + xReturn = pdPASS; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static void prvCreateThreadSafeBuffers( void ) +{ + /* The buffer used to pass data to be transmitted from a FreeRTOS task to + the Win32 thread that sends via the WinPCAP library. */ + if( xSendBuffer == NULL) + { + xSendBuffer = ( StreamBuffer_t * ) malloc( sizeof( *xSendBuffer ) - sizeof( xSendBuffer->ucArray ) + xSEND_BUFFER_SIZE + 1 ); + configASSERT( xSendBuffer ); + memset( xSendBuffer, '\0', sizeof( *xSendBuffer ) - sizeof( xSendBuffer->ucArray ) ); + xSendBuffer->LENGTH = xSEND_BUFFER_SIZE + 1; + } + + /* The buffer used to pass received data from the Win32 thread that receives + via the WinPCAP library to the FreeRTOS task. */ + if( xRecvBuffer == NULL) + { + xRecvBuffer = ( StreamBuffer_t * ) malloc( sizeof( *xRecvBuffer ) - sizeof( xRecvBuffer->ucArray ) + xRECV_BUFFER_SIZE + 1 ); + configASSERT( xRecvBuffer ); + memset( xRecvBuffer, '\0', sizeof( *xRecvBuffer ) - sizeof( xRecvBuffer->ucArray ) ); + xRecvBuffer->LENGTH = xRECV_BUFFER_SIZE + 1; + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xNetworkInterfaceOutput( NetworkBufferDescriptor_t * const pxNetworkBuffer, BaseType_t bReleaseAfterSend ) +{ +size_t xSpace; + + iptraceNETWORK_INTERFACE_TRANSMIT(); + configASSERT( xIsCallingFromIPTask() == pdTRUE ); + + /* Both the length of the data being sent and the actual data being sent + are placed in the thread safe buffer used to pass data between the FreeRTOS + tasks and the Win32 thread that sends data via the WinPCAP library. Drop + the packet if there is insufficient space in the buffer to hold both. */ + xSpace = uxStreamBufferGetSpace( xSendBuffer ); + + if( ( pxNetworkBuffer->xDataLength <= ( ipconfigNETWORK_MTU + ipSIZE_OF_ETH_HEADER ) ) && + ( xSpace >= ( pxNetworkBuffer->xDataLength + sizeof( pxNetworkBuffer->xDataLength ) ) ) ) + { + /* First write in the length of the data, then write in the data + itself. */ + uxStreamBufferAdd( xSendBuffer, 0, ( const uint8_t * ) &( pxNetworkBuffer->xDataLength ), sizeof( pxNetworkBuffer->xDataLength ) ); + uxStreamBufferAdd( xSendBuffer, 0, ( const uint8_t * ) pxNetworkBuffer->pucEthernetBuffer, pxNetworkBuffer->xDataLength ); + } + else + { + FreeRTOS_debug_printf( ( "xNetworkInterfaceOutput: send buffers full to store %lu\n", pxNetworkBuffer->xDataLength ) ); + } + + /* Kick the Tx task in either case in case it doesn't know the buffer is + full. */ + SetEvent( pvSendEvent ); + + /* The buffer has been sent so can be released. */ + if( bReleaseAfterSend != pdFALSE ) + { + vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ); + } + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +static pcap_if_t * prvPrintAvailableNetworkInterfaces( void ) +{ +pcap_if_t * pxAllNetworkInterfaces = NULL, *xInterface; +int32_t lInterfaceNumber = 1; +char cBuffer[ 512 ]; +static BaseType_t xInvalidInterfaceDetected = pdFALSE; + + if( xInvalidInterfaceDetected == pdFALSE ) + { + if( pcap_findalldevs_ex( PCAP_SRC_IF_STRING, NULL, &pxAllNetworkInterfaces, cErrorBuffer ) == -1 ) + { + printf( "Could not obtain a list of network interfaces\n%s\n", cErrorBuffer ); + pxAllNetworkInterfaces = NULL; + } + else + { + printf( "\r\n\r\nThe following network interfaces are available:\r\n\r\n" ); + } + + if( pxAllNetworkInterfaces != NULL ) + { + /* Print out the list of network interfaces. The first in the list + is interface '1', not interface '0'. */ + for( xInterface = pxAllNetworkInterfaces; xInterface != NULL; xInterface = xInterface->next ) + { + /* The descriptions of the devices can be full of spaces, clean them + a little. printf() can only be used here because the network is not + up yet - so no other network tasks will be running. */ + printf( "Interface %d - %s\n", lInterfaceNumber, prvRemoveSpaces( cBuffer, sizeof( cBuffer ), xInterface->name ) ); + printf( " (%s)\n", prvRemoveSpaces(cBuffer, sizeof( cBuffer ), xInterface->description ? xInterface->description : "No description" ) ); + printf( "\n" ); + lInterfaceNumber++; + } + } + + if( lInterfaceNumber == 1 ) + { + /* The interface number was never incremented, so the above for() loop + did not execute meaning no interfaces were found. */ + printf( " \nNo network interfaces were found.\n" ); + pxAllNetworkInterfaces = NULL; + } + + printf( "\r\nThe interface that will be opened is set by " ); + printf( "\"configNETWORK_INTERFACE_TO_USE\", which\r\nshould be defined in FreeRTOSConfig.h\r\n" ); + + if( ( xConfigNextworkInterfaceToUse < 0L ) || ( xConfigNextworkInterfaceToUse >= lInterfaceNumber ) ) + { + printf( "\r\nERROR: configNETWORK_INTERFACE_TO_USE is set to %d, which is an invalid value.\r\n", xConfigNextworkInterfaceToUse ); + printf( "Please set configNETWORK_INTERFACE_TO_USE to one of the interface numbers listed above,\r\n" ); + printf( "then re-compile and re-start the application. Only Ethernet (as opposed to WiFi)\r\n" ); + printf( "interfaces are supported.\r\n\r\nHALTING\r\n\r\n\r\n" ); + xInvalidInterfaceDetected = pdTRUE; + + if( pxAllNetworkInterfaces != NULL ) + { + /* Free the device list, as no devices are going to be opened. */ + pcap_freealldevs( pxAllNetworkInterfaces ); + pxAllNetworkInterfaces = NULL; + } + } + else + { + printf( "Attempting to open interface number %d.\n", xConfigNextworkInterfaceToUse ); + } + } + + return pxAllNetworkInterfaces; +} +/*-----------------------------------------------------------*/ + +static int prvOpenInterface( const char *pucName ) +{ +static char pucInterfaceName[ 256 ]; + + if( pucName != NULL ) + { + strncpy( pucInterfaceName, pucName, sizeof( pucInterfaceName ) ); + } + + pxOpenedInterfaceHandle = pcap_open( pucInterfaceName, /* The name of the selected interface. */ + ipTOTAL_ETHERNET_FRAME_SIZE, /* The size of the packet to capture. */ + PCAP_OPENFLAG_PROMISCUOUS, /* Open in promiscuous mode as the MAC and + IP address is going to be "simulated", and + not be the real MAC and IP address. This allows + traffic to the simulated IP address to be routed + to uIP, and traffic to the real IP address to be + routed to the Windows TCP/IP stack. */ + 100, + NULL, /* No authentication is required as this is + not a remote capture session. */ + cErrorBuffer + ); + + if ( pxOpenedInterfaceHandle == NULL ) + { + printf( "\n%s is not supported by WinPcap and cannot be opened\n", pucInterfaceName ); + return 1; + } + else + { + /* Configure the capture filter to allow blocking reads, and to filter + out packets that are not of interest to this demo. */ + prvConfigureCaptureBehaviour(); + } + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvOpenSelectedNetworkInterface( pcap_if_t *pxAllNetworkInterfaces ) +{ +pcap_if_t *xInterface; +int32_t x; + + /* Walk the list of devices until the selected device is located. */ + xInterface = pxAllNetworkInterfaces; + if (0 == xConfigNextworkInterfaceToUse) { + while (NULL != xInterface) { + xInterface = xInterface->next; + if (0 == prvOpenInterface(xInterface->name)) { + break; + } + } + } + else { + for (x = 1L; x < xConfigNextworkInterfaceToUse; x++) + { + xInterface = xInterface->next; + } + /* Open the selected interface. */ + (void) prvOpenInterface(xInterface->name); + } + + /* The device list is no longer required. */ + pcap_freealldevs( pxAllNetworkInterfaces ); +} +/*-----------------------------------------------------------*/ + +static void prvConfigureCaptureBehaviour( void ) +{ +struct bpf_program xFilterCode; +uint32_t ulNetMask; + + /* Set up a filter so only the packets of interest are passed to the IP + stack. cErrorBuffer is used for convenience to create the string. Don't + confuse this with an error message. */ + sprintf( cErrorBuffer, "broadcast or multicast or ether host %x:%x:%x:%x:%x:%x", + ucMACAddress[0], ucMACAddress[1], ucMACAddress[2], ucMACAddress[3], ucMACAddress[4], ucMACAddress[5] ); + + ulNetMask = ( configNET_MASK3 << 24UL ) | ( configNET_MASK2 << 16UL ) | ( configNET_MASK1 << 8L ) | configNET_MASK0; + + if( pcap_compile( pxOpenedInterfaceHandle, &xFilterCode, cErrorBuffer, 1, ulNetMask ) < 0 ) + { + printf( "\nThe packet filter string is invalid\n" ); + } + else + { + if( pcap_setfilter( pxOpenedInterfaceHandle, &xFilterCode ) < 0 ) + { + printf( "\nAn error occurred setting the packet filter.\n" ); + } + + pcap_freecode( &xFilterCode ); + } + + /* Create the buffers used to pass packets between the FreeRTOS simulator + and the Win32 threads that are handling WinPCAP. */ + prvCreateThreadSafeBuffers(); + + if( pvSendEvent == NULL ) + { + /* Create event used to signal the Win32 WinPCAP Tx thread. */ + pvSendEvent = CreateEvent( NULL, FALSE, TRUE, NULL ); + + /* Create the Win32 thread that handles WinPCAP Rx. */ + vWinPcapRecvThreadHandle = CreateThread( + NULL, /* Pointer to thread security attributes. */ + 0, /* Initial thread stack size, in bytes. */ + prvWinPcapRecvThread, /* Pointer to thread function. */ + NULL, /* Argument for new thread. */ + 0, /* Creation flags. */ + NULL ); + + /* Use the cores that are not used by the FreeRTOS tasks. */ + SetThreadAffinityMask( vWinPcapRecvThreadHandle, ~0x01u ); + + /* Create the Win32 thread that handlers WinPCAP Tx. */ + vWinPcapSendThreadHandle = CreateThread( + NULL, /* Pointer to thread security attributes. */ + 0, /* initial thread stack size, in bytes. */ + prvWinPcapSendThread, /* Pointer to thread function. */ + NULL, /* Argument for new thread. */ + 0, /* Creation flags. */ + NULL ); + + /* Use the cores that are not used by the FreeRTOS tasks. */ + SetThreadAffinityMask( vWinPcapSendThreadHandle, ~0x01u ); + + /* Create a task that simulates an interrupt in a real system. This will + block waiting for packets, then send a message to the IP task when data + is available. */ + xTaskCreate( prvInterruptSimulatorTask, "MAC_ISR", configMINIMAL_STACK_SIZE, NULL, configMAC_ISR_SIMULATOR_PRIORITY, NULL ); + } +} +/*-----------------------------------------------------------*/ + +/* WinPCAP function. */ +void pcap_callback( u_char *user, const struct pcap_pkthdr *pkt_header, const u_char *pkt_data ) +{ + (void)user; + + /* THIS IS CALLED FROM A WINDOWS THREAD - DO NOT ATTEMPT ANY FREERTOS CALLS + OR TO PRINT OUT MESSAGES HERE. */ + + /* Pass data to the FreeRTOS simulator on a thread safe circular buffer. */ + if( ( pkt_header->caplen <= ( ipconfigNETWORK_MTU + ipSIZE_OF_ETH_HEADER ) ) && + ( uxStreamBufferGetSpace( xRecvBuffer ) >= ( ( ( size_t ) pkt_header->caplen ) + sizeof( *pkt_header ) ) ) ) + { + uxStreamBufferAdd( xRecvBuffer, 0, ( const uint8_t* ) pkt_header, sizeof( *pkt_header ) ); + uxStreamBufferAdd( xRecvBuffer, 0, ( const uint8_t* ) pkt_data, ( size_t ) pkt_header->caplen ); + } +} +/*-----------------------------------------------------------*/ + +DWORD WINAPI prvWinPcapRecvThread ( void *pvParam ) +{ + ( void ) pvParam; + + /* THIS IS A WINDOWS THREAD - DO NOT ATTEMPT ANY FREERTOS CALLS OR TO PRINT + OUT MESSAGES HERE. */ + + for( ;; ) + { + pcap_dispatch( pxOpenedInterfaceHandle, 1, pcap_callback, ( u_char * ) "mydata" ); + } +} +/*-----------------------------------------------------------*/ + +DWORD WINAPI prvWinPcapSendThread( void *pvParam ) +{ +size_t xLength; +uint8_t ucBuffer[ ipconfigNETWORK_MTU + ipSIZE_OF_ETH_HEADER ]; +static char cErrorMessage[ 1024 ]; +const DWORD xMaxMSToWait = 1000; + + /* THIS IS A WINDOWS THREAD - DO NOT ATTEMPT ANY FREERTOS CALLS OR TO PRINT + OUT MESSAGES HERE. */ + + /* Remove compiler warnings about unused parameters. */ + ( void ) pvParam; + + for( ;; ) + { + /* Wait until notified of something to send. */ + WaitForSingleObject( pvSendEvent, xMaxMSToWait ); + + /* Is there more than the length value stored in the circular buffer + used to pass data from the FreeRTOS simulator into this Win32 thread? */ + while( uxStreamBufferGetSize( xSendBuffer ) > sizeof( xLength ) ) + { + uxStreamBufferGet( xSendBuffer, 0, ( uint8_t * ) &xLength, sizeof( xLength ), pdFALSE ); + uxStreamBufferGet( xSendBuffer, 0, ( uint8_t* ) ucBuffer, xLength, pdFALSE ); + if( pcap_sendpacket( pxOpenedInterfaceHandle, ucBuffer, xLength ) != 0 ) + { + ulWinPCAPSendFailures++; + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvInterruptSimulatorTask( void *pvParameters ) +{ +struct pcap_pkthdr xHeader; +static struct pcap_pkthdr *pxHeader; +const uint8_t *pucPacketData; +uint8_t ucRecvBuffer[ ipconfigNETWORK_MTU + ipSIZE_OF_ETH_HEADER ]; +NetworkBufferDescriptor_t *pxNetworkBuffer; +IPStackEvent_t xRxEvent = { eNetworkRxEvent, NULL }; +eFrameProcessingResult_t eResult; + + /* Remove compiler warnings about unused parameters. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Does the circular buffer used to pass data from the Win32 thread that + handles WinPCAP Rx into the FreeRTOS simulator contain another packet? */ + if( uxStreamBufferGetSize( xRecvBuffer ) > sizeof( xHeader ) ) + { + /* Get the next packet. */ + uxStreamBufferGet( xRecvBuffer, 0, (uint8_t*)&xHeader, sizeof( xHeader ), pdFALSE ); + uxStreamBufferGet( xRecvBuffer, 0, (uint8_t*)ucRecvBuffer, ( size_t ) xHeader.len, pdFALSE ); + pucPacketData = ucRecvBuffer; + pxHeader = &xHeader; + + iptraceNETWORK_INTERFACE_RECEIVE(); + + /* Check for minimal size. */ + if( pxHeader->len >= sizeof( EthernetHeader_t ) ) + { + eResult = ipCONSIDER_FRAME_FOR_PROCESSING( pucPacketData ); + } + else + { + eResult = eReleaseBuffer; + } + + if( eResult == eProcessBuffer ) + { + /* Will the data fit into the frame buffer? */ + if( pxHeader->len <= ipTOTAL_ETHERNET_FRAME_SIZE ) + { + /* Obtain a buffer into which the data can be placed. This + is only an interrupt simulator, not a real interrupt, so it + is ok to call the task level function here, but note that + some buffer implementations cannot be called from a real + interrupt. */ + pxNetworkBuffer = pxGetNetworkBufferWithDescriptor( pxHeader->len, 0 ); + + if( pxNetworkBuffer != NULL ) + { + memcpy( pxNetworkBuffer->pucEthernetBuffer, pucPacketData, pxHeader->len ); + pxNetworkBuffer->xDataLength = ( size_t ) pxHeader->len; + + #if( niDISRUPT_PACKETS == 1 ) + { + pxNetworkBuffer = vRxFaultInjection( pxNetworkBuffer, pucPacketData ); + } + #endif /* niDISRUPT_PACKETS */ + + if( pxNetworkBuffer != NULL ) + { + xRxEvent.pvData = ( void * ) pxNetworkBuffer; + + /* Data was received and stored. Send a message to + the IP task to let it know. */ + if( xSendEventStructToIPTask( &xRxEvent, ( TickType_t ) 0 ) == pdFAIL ) + { + /* The buffer could not be sent to the stack so + must be released again. This is only an + interrupt simulator, not a real interrupt, so it + is ok to use the task level function here, but + note no all buffer implementations will allow + this function to be executed from a real + interrupt. */ + vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ); + iptraceETHERNET_RX_EVENT_LOST(); + } + } + else + { + /* The packet was already released or stored inside + vRxFaultInjection(). Don't release it here. */ + } + } + else + { + iptraceETHERNET_RX_EVENT_LOST(); + } + } + else + { + /* Log that a packet was dropped because it would have + overflowed the buffer, but there may be more buffers to + process. */ + } + } + } + else + { + /* There is no real way of simulating an interrupt. Make sure + other tasks can run. */ + vTaskDelay( configWINDOWS_MAC_INTERRUPT_SIMULATOR_DELAY ); + } + } +} +/*-----------------------------------------------------------*/ + +static const char *prvRemoveSpaces( char *pcBuffer, int aBuflen, const char *pcMessage ) +{ + char *pcTarget = pcBuffer; + + /* Utility function used to formap messages being printed only. */ + while( ( *pcMessage != 0 ) && ( pcTarget < ( pcBuffer + aBuflen - 1 ) ) ) + { + *( pcTarget++ ) = *pcMessage; + + if( isspace( *pcMessage ) != pdFALSE ) + { + while( isspace( *pcMessage ) != pdFALSE ) + { + pcMessage++; + } + } + else + { + pcMessage++; + } + } + + *pcTarget = '\0'; + + return pcBuffer; +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/NetworkInterface.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/NetworkInterface.c new file mode 100644 index 0000000..ad07177 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/NetworkInterface.c @@ -0,0 +1,432 @@ +/* +FreeRTOS+TCP V2.0.11 +Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + http://aws.amazon.com/freertos + http://www.FreeRTOS.org + */ + +/* Standard includes. */ +#include +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_IP_Private.h" +#include "FreeRTOS_ARP.h" +#include "NetworkBufferManagement.h" +#include "NetworkInterface.h" + +/* Xilinx library files. */ +#include +#include "Zynq/x_topology.h" +#include "Zynq/x_emacpsif.h" +#include "Zynq/x_emacpsif_hw.h" + +/* Provided memory configured as uncached. */ +#include "uncached_memory.h" + +#ifndef niEMAC_HANDLER_TASK_PRIORITY + #define niEMAC_HANDLER_TASK_PRIORITY configMAX_PRIORITIES - 1 +#endif + +#define niBMSR_LINK_STATUS 0x0004UL +#define niBMSR_AN_COMPLETE 0x0020u /* Auto-Negotiation process completed */ + +#ifndef PHY_LS_HIGH_CHECK_TIME_MS + /* Check if the LinkSStatus in the PHY is still high after 15 seconds of not + receiving packets. */ + #define PHY_LS_HIGH_CHECK_TIME_MS 15000 +#endif + +#ifndef PHY_LS_LOW_CHECK_TIME_MS + /* Check if the LinkSStatus in the PHY is still low every second. */ + #define PHY_LS_LOW_CHECK_TIME_MS 1000 +#endif + +/* The size of each buffer when BufferAllocation_1 is used: +http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/Embedded_Ethernet_Buffer_Management.html */ +#define niBUFFER_1_PACKET_SIZE 1536 + +/* Naming and numbering of PHY registers. */ +#define PHY_REG_01_BMSR 0x01 /* Basic mode status register */ + +#ifndef iptraceEMAC_TASK_STARTING + #define iptraceEMAC_TASK_STARTING() do { } while( 0 ) +#endif + +/* Default the size of the stack used by the EMAC deferred handler task to twice +the size of the stack used by the idle task - but allow this to be overridden in +FreeRTOSConfig.h as configMINIMAL_STACK_SIZE is a user definable constant. */ +#ifndef configEMAC_TASK_STACK_SIZE + #define configEMAC_TASK_STACK_SIZE ( 2 * configMINIMAL_STACK_SIZE ) +#endif + +/*-----------------------------------------------------------*/ + +/* + * Look for the link to be up every few milliseconds until either xMaxTime time + * has passed or a link is found. + */ +static BaseType_t prvGMACWaitLS( TickType_t xMaxTime ); + +/* + * A deferred interrupt handler for all MAC/DMA interrupt sources. + */ +static void prvEMACHandlerTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* EMAC data/descriptions. */ +static xemacpsif_s xEMACpsif; +struct xtopology_t xXTopology = +{ + .emac_baseaddr = XPAR_PS7_ETHERNET_0_BASEADDR, + .emac_type = xemac_type_emacps, + .intc_baseaddr = 0x0, + .intc_emac_intr = 0x0, + .scugic_baseaddr = XPAR_PS7_SCUGIC_0_BASEADDR, + .scugic_emac_intr = 0x36, +}; + +XEmacPs_Config mac_config = +{ + .DeviceId = XPAR_PS7_ETHERNET_0_DEVICE_ID, /**< Unique ID of device */ + .BaseAddress = XPAR_PS7_ETHERNET_0_BASEADDR /**< Physical base address of IPIF registers */ +}; + +extern int phy_detected; + +/* A copy of PHY register 1: 'PHY_REG_01_BMSR' */ +static uint32_t ulPHYLinkStatus = 0; + +#if( ipconfigUSE_LLMNR == 1 ) + static const uint8_t xLLMNR_MACAddress[] = { 0x01, 0x00, 0x5E, 0x00, 0x00, 0xFC }; +#endif + +/* ucMACAddress as it appears in main.c */ +extern const uint8_t ucMACAddress[ 6 ]; + +/* Holds the handle of the task used as a deferred interrupt processor. The +handle is used so direct notifications can be sent to the task for all EMAC/DMA +related interrupts. */ +TaskHandle_t xEMACTaskHandle = NULL; + +/*-----------------------------------------------------------*/ + +BaseType_t xNetworkInterfaceInitialise( void ) +{ +uint32_t ulLinkSpeed, ulDMAReg; +BaseType_t xStatus, xLinkStatus; +XEmacPs *pxEMAC_PS; +const TickType_t xWaitLinkDelay = pdMS_TO_TICKS( 7000UL ), xWaitRelinkDelay = pdMS_TO_TICKS( 1000UL ); + + /* Guard against the init function being called more than once. */ + if( xEMACTaskHandle == NULL ) + { + pxEMAC_PS = &( xEMACpsif.emacps ); + memset( &xEMACpsif, '\0', sizeof( xEMACpsif ) ); + + xStatus = XEmacPs_CfgInitialize( pxEMAC_PS, &mac_config, mac_config.BaseAddress); + if( xStatus != XST_SUCCESS ) + { + FreeRTOS_printf( ( "xEMACInit: EmacPs Configuration Failed....\n" ) ); + } + + /* Initialize the mac and set the MAC address. */ + XEmacPs_SetMacAddress( pxEMAC_PS, ( void * ) ucMACAddress, 1 ); + + #if( ipconfigUSE_LLMNR == 1 ) + { + /* Also add LLMNR multicast MAC address. */ + XEmacPs_SetMacAddress( pxEMAC_PS, ( void * )xLLMNR_MACAddress, 2 ); + } + #endif /* ipconfigUSE_LLMNR == 1 */ + + XEmacPs_SetMdioDivisor( pxEMAC_PS, MDC_DIV_224 ); + ulLinkSpeed = Phy_Setup( pxEMAC_PS ); + XEmacPs_SetOperatingSpeed( pxEMAC_PS, ulLinkSpeed); + + /* Setting the operating speed of the MAC needs a delay. */ + vTaskDelay( pdMS_TO_TICKS( 25UL ) ); + + ulDMAReg = XEmacPs_ReadReg( pxEMAC_PS->Config.BaseAddress, XEMACPS_DMACR_OFFSET); + + /* DISC_WHEN_NO_AHB: when set, the GEM DMA will automatically discard receive + packets from the receiver packet buffer memory when no AHB resource is available. */ + XEmacPs_WriteReg( pxEMAC_PS->Config.BaseAddress, XEMACPS_DMACR_OFFSET, + ulDMAReg | XEMACPS_DMACR_DISC_WHEN_NO_AHB_MASK); + + setup_isr( &xEMACpsif ); + init_dma( &xEMACpsif ); + start_emacps( &xEMACpsif ); + + prvGMACWaitLS( xWaitLinkDelay ); + + /* The deferred interrupt handler task is created at the highest + possible priority to ensure the interrupt handler can return directly + to it. The task's handle is stored in xEMACTaskHandle so interrupts can + notify the task when there is something to process. */ + xTaskCreate( prvEMACHandlerTask, "EMAC", configEMAC_TASK_STACK_SIZE, NULL, niEMAC_HANDLER_TASK_PRIORITY, &xEMACTaskHandle ); + } + else + { + /* Initialisation was already performed, just wait for the link. */ + prvGMACWaitLS( xWaitRelinkDelay ); + } + + /* Only return pdTRUE when the Link Status of the PHY is high, otherwise the + DHCP process and all other communication will fail. */ + xLinkStatus = xGetPhyLinkStatus(); + + return ( xLinkStatus != pdFALSE ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xNetworkInterfaceOutput( NetworkBufferDescriptor_t * const pxBuffer, BaseType_t bReleaseAfterSend ) +{ + if( xCheckLoopback( pxBuffer, bReleaseAfterSend ) != 0 ) + { + /* The packet has been sent back to the IP-task. + The IP-task will further handle it. + Do not release the descriptor. */ + return pdTRUE; + } + #if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM != 0 ) + { + ProtocolPacket_t *pxPacket; + + /* If the peripheral must calculate the checksum, it wants + the protocol checksum to have a value of zero. */ + pxPacket = ( ProtocolPacket_t * ) ( pxBuffer->pucEthernetBuffer ); + if( pxPacket->xICMPPacket.xIPHeader.ucProtocol == ipPROTOCOL_ICMP ) + { + IPHeader_t *pxIPHeader = &( pxPacket->xUDPPacket.xIPHeader ); + + pxPacket->xICMPPacket.xICMPHeader.usChecksum = ( uint16_t )0u; + pxIPHeader->usHeaderChecksum = 0u; + pxIPHeader->usHeaderChecksum = usGenerateChecksum( 0UL, ( uint8_t * ) &( pxIPHeader->ucVersionHeaderLength ), ipSIZE_OF_IPv4_HEADER ); + pxIPHeader->usHeaderChecksum = ~FreeRTOS_htons( pxIPHeader->usHeaderChecksum ); + + usGenerateProtocolChecksum( (uint8_t*)&( pxPacket->xUDPPacket ), pxBuffer->xDataLength, pdTRUE ); + } + } + #endif /* ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM */ + if( ( ulPHYLinkStatus & niBMSR_LINK_STATUS ) != 0 ) + { + iptraceNETWORK_INTERFACE_TRANSMIT(); + emacps_send_message( &xEMACpsif, pxBuffer, bReleaseAfterSend ); + } + else if( bReleaseAfterSend != pdFALSE ) + { + /* No link. */ + vReleaseNetworkBufferAndDescriptor( pxBuffer ); + } + + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +static inline unsigned long ulReadMDIO( unsigned ulRegister ) +{ +uint16_t usValue; + + XEmacPs_PhyRead( &( xEMACpsif.emacps ), phy_detected, ulRegister, &usValue ); + return usValue; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvGMACWaitLS( TickType_t xMaxTime ) +{ +TickType_t xStartTime, xEndTime; +const TickType_t xShortDelay = pdMS_TO_TICKS( 20UL ); +BaseType_t xReturn; + + xStartTime = xTaskGetTickCount(); + + for( ;; ) + { + xEndTime = xTaskGetTickCount(); + + if( xEndTime - xStartTime > xMaxTime ) + { + xReturn = pdFALSE; + break; + } + ulPHYLinkStatus = ulReadMDIO( PHY_REG_01_BMSR ); + + if( ( ulPHYLinkStatus & niBMSR_LINK_STATUS ) != 0 ) + { + xReturn = pdTRUE; + break; + } + + vTaskDelay( xShortDelay ); + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vNetworkInterfaceAllocateRAMToBuffers( NetworkBufferDescriptor_t pxNetworkBuffers[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ] ) +{ +static uint8_t ucNetworkPackets[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS * niBUFFER_1_PACKET_SIZE ] __attribute__ ( ( aligned( 32 ) ) ); +uint8_t *ucRAMBuffer = ucNetworkPackets; +uint32_t ul; + + for( ul = 0; ul < ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS; ul++ ) + { + pxNetworkBuffers[ ul ].pucEthernetBuffer = ucRAMBuffer + ipBUFFER_PADDING; + *( ( unsigned * ) ucRAMBuffer ) = ( unsigned ) ( &( pxNetworkBuffers[ ul ] ) ); + ucRAMBuffer += niBUFFER_1_PACKET_SIZE; + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xGetPhyLinkStatus( void ) +{ +BaseType_t xReturn; + + if( ( ulPHYLinkStatus & niBMSR_LINK_STATUS ) == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static void prvEMACHandlerTask( void *pvParameters ) +{ +TimeOut_t xPhyTime; +TickType_t xPhyRemTime; +UBaseType_t uxCurrentCount; +BaseType_t xResult = 0; +uint32_t xStatus; +const TickType_t ulMaxBlockTime = pdMS_TO_TICKS( 100UL ); +UBaseType_t uxLastMinBufferCount = 0; +UBaseType_t uxCurrentBufferCount = 0; + + /* Remove compiler warnings about unused parameters. */ + ( void ) pvParameters; + + /* A possibility to set some additional task properties like calling + portTASK_USES_FLOATING_POINT() */ + iptraceEMAC_TASK_STARTING(); + + vTaskSetTimeOutState( &xPhyTime ); + xPhyRemTime = pdMS_TO_TICKS( PHY_LS_LOW_CHECK_TIME_MS ); + + for( ;; ) + { + uxCurrentBufferCount = uxGetMinimumFreeNetworkBuffers(); + if( uxLastMinBufferCount != uxCurrentBufferCount ) + { + /* The logging produced below may be helpful + while tuning +TCP: see how many buffers are in use. */ + uxLastMinBufferCount = uxCurrentBufferCount; + FreeRTOS_printf( ( "Network buffers: %lu lowest %lu\n", + uxGetNumberOfFreeNetworkBuffers(), uxCurrentBufferCount ) ); + } + + #if( ipconfigCHECK_IP_QUEUE_SPACE != 0 ) + { + static UBaseType_t uxLastMinQueueSpace = 0; + + uxCurrentCount = uxGetMinimumIPQueueSpace(); + if( uxLastMinQueueSpace != uxCurrentCount ) + { + /* The logging produced below may be helpful + while tuning +TCP: see how many buffers are in use. */ + uxLastMinQueueSpace = uxCurrentCount; + FreeRTOS_printf( ( "Queue space: lowest %lu\n", uxCurrentCount ) ); + } + } + #endif /* ipconfigCHECK_IP_QUEUE_SPACE */ + + if( ( xEMACpsif.isr_events & EMAC_IF_ALL_EVENT ) == 0 ) + { + /* No events to process now, wait for the next. */ + ulTaskNotifyTake( pdFALSE, ulMaxBlockTime ); + } + + if( ( xEMACpsif.isr_events & EMAC_IF_RX_EVENT ) != 0 ) + { + xEMACpsif.isr_events &= ~EMAC_IF_RX_EVENT; + xResult = emacps_check_rx( &xEMACpsif ); + } + + if( ( xEMACpsif.isr_events & EMAC_IF_TX_EVENT ) != 0 ) + { + xEMACpsif.isr_events &= ~EMAC_IF_TX_EVENT; + emacps_check_tx( &xEMACpsif ); + } + + if( ( xEMACpsif.isr_events & EMAC_IF_ERR_EVENT ) != 0 ) + { + xEMACpsif.isr_events &= ~EMAC_IF_ERR_EVENT; + emacps_check_errors( &xEMACpsif ); + } + if( xResult > 0 ) + { + /* A packet was received. No need to check for the PHY status now, + but set a timer to check it later on. */ + vTaskSetTimeOutState( &xPhyTime ); + xPhyRemTime = pdMS_TO_TICKS( PHY_LS_HIGH_CHECK_TIME_MS ); + xResult = 0; + /* Indicate that the Link Status is high, so that + xNetworkInterfaceOutput() can send packets. */ + ulPHYLinkStatus |= niBMSR_LINK_STATUS; + } + else if( xTaskCheckForTimeOut( &xPhyTime, &xPhyRemTime ) != pdFALSE ) + { + xStatus = ulReadMDIO( PHY_REG_01_BMSR ); + + if( ( ulPHYLinkStatus & niBMSR_LINK_STATUS ) != ( xStatus & niBMSR_LINK_STATUS ) ) + { + ulPHYLinkStatus = xStatus; + FreeRTOS_printf( ( "prvEMACHandlerTask: PHY LS now %d\n", ( ulPHYLinkStatus & niBMSR_LINK_STATUS ) != 0 ) ); + } + + vTaskSetTimeOutState( &xPhyTime ); + if( ( ulPHYLinkStatus & niBMSR_LINK_STATUS ) != 0 ) + { + xPhyRemTime = pdMS_TO_TICKS( PHY_LS_HIGH_CHECK_TIME_MS ); + } + else + { + xPhyRemTime = pdMS_TO_TICKS( PHY_LS_LOW_CHECK_TIME_MS ); + } + } + } +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/README.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/README.txt new file mode 100644 index 0000000..74b241d --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/README.txt @@ -0,0 +1,25 @@ + + +NetworkInterface for Xilinx' Zynq + +Please include the following source files: + + $(PLUS_TCP_PATH)/portable/NetworkInterface/Zynq/NetworkInterface.c + $(PLUS_TCP_PATH)/portable/NetworkInterface/Zynq/x_emacpsif_dma.c + $(PLUS_TCP_PATH)/portable/NetworkInterface/Zynq/x_emacpsif_physpeed.c + $(PLUS_TCP_PATH)/portable/NetworkInterface/Zynq/x_emacpsif_hw.c + +And include the following source files from the Xilinx library: + + $(CPU_PATH)/$(PROCESSOR)/libsrc/emacps_v2_0/src/xemacps.c + $(CPU_PATH)/$(PROCESSOR)/libsrc/emacps_v2_0/src/xemacps_control.c + $(CPU_PATH)/$(PROCESSOR)/libsrc/emacps_v2_0/src/xemacps_g.c + $(CPU_PATH)/$(PROCESSOR)/libsrc/emacps_v2_0/src/xemacps_intr.c + + E.g. ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_intr.c + +The following source files are NOT used for the FreeRTOS+TCP interface: + + $(CPU_PATH)/$(PROCESSOR)/libsrc/emacps_v2_0/src/xemacps_bdring.c + $(CPU_PATH)/$(PROCESSOR)/libsrc/emacps_v2_0/src/xemacps_hw.c + $(CPU_PATH)/$(PROCESSOR)/libsrc/emacps_v2_0/src/xemacps_sinit.c diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/uncached_memory.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/uncached_memory.c new file mode 100644 index 0000000..b43e50e --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/uncached_memory.c @@ -0,0 +1,132 @@ +/* + * uncached_memory.c + * + * This module will declare 1 MB of memory and switch off the caching for it. + * + * pucGetUncachedMemory( ulSize ) returns a trunc of this memory with a length + * rounded up to a multiple of 4 KB + * + * ucIsCachedMemory( pucBuffer ) returns non-zero if a given pointer is NOT + * within the range of the 1 MB non-cached memory. + * + */ + +/* + * After "_end", 1 MB of uncached memory will be allocated for DMA transfers. + * Both the DMA descriptors as well as all EMAC TX-buffers will be allocated in + * uncached memory. + */ + +/* Standard includes. */ +#include +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_IP_Private.h" + +#include "Zynq/x_emacpsif.h" +#include "Zynq/x_topology.h" +#include "xstatus.h" + +#include "xparameters.h" +#include "xparameters_ps.h" +#include "xil_exception.h" +#include "xil_mmu.h" + +#include "uncached_memory.h" + +#define UNCACHED_MEMORY_SIZE 0x100000ul + +#define DDR_MEMORY_END (XPAR_PS7_DDR_0_S_AXI_HIGHADDR+1) + +static void vInitialiseUncachedMemory( void ); + +static uint8_t *pucHeadOfMemory; +static uint32_t ulMemorySize; +static uint8_t *pucStartOfMemory = NULL; + +uint8_t ucIsCachedMemory( const uint8_t *pucBuffer ) +{ +uint8_t ucReturn; + + if( ( pucStartOfMemory != NULL ) && + ( pucBuffer >= pucStartOfMemory ) && + ( pucBuffer < ( pucStartOfMemory + UNCACHED_MEMORY_SIZE ) ) ) + { + ucReturn = pdFALSE; + } + else + { + ucReturn = pdTRUE; + } + + return ucReturn; +} + +uint8_t *pucGetUncachedMemory( uint32_t ulSize ) +{ +uint8_t *pucReturn; + + if( pucStartOfMemory == NULL ) + { + vInitialiseUncachedMemory( ); + } + if( ( pucStartOfMemory == NULL ) || ( ulSize > ulMemorySize ) ) + { + pucReturn = NULL; + } + else + { + uint32_t ulSkipSize; + + pucReturn = pucHeadOfMemory; + ulSkipSize = ( ulSize + 0x1000ul ) & ~0xffful; + pucHeadOfMemory += ulSkipSize; + ulMemorySize -= ulSkipSize; + } + + return pucReturn; +} + +extern u8 _end; + +static void vInitialiseUncachedMemory( ) +{ + /* At the end of program's space... */ + pucStartOfMemory = (uint8_t *) &_end; + /* + * Align the start address to 1 MB boundary. + */ + pucStartOfMemory = (uint8_t *)( ( ( uint32_t )pucStartOfMemory + UNCACHED_MEMORY_SIZE ) & ( ~( UNCACHED_MEMORY_SIZE - 1 ) ) ); + + if( ( ( u32 )pucStartOfMemory ) + UNCACHED_MEMORY_SIZE > DDR_MEMORY_END ) + { +// vLoggingPrintf("vInitialiseUncachedMemory: Can not allocate uncached memory\n" ); + } + else + { + /* + * Some objects want to be stored in uncached memory. Hence the 1 MB + * address range that starts after "_end" is made uncached + * by setting appropriate attributes in the translation table. + */ + /* FIXME claudio rossi. Modified to prevent data abort exception (misaligned access) + * when application is compiled with -O1 or more optimization flag. + */ +/* Xil_SetTlbAttributes( ( uint32_t )pucStartOfMemory, 0xc02 ); // addr, attr */ + Xil_SetTlbAttributes( ( uint32_t )pucStartOfMemory, 0x1c02 ); // addr, attr + + /* For experiments in the SDIO driver, make the remaining uncached memory public */ + pucHeadOfMemory = pucStartOfMemory; + ulMemorySize = UNCACHED_MEMORY_SIZE; + memset( pucStartOfMemory, '\0', UNCACHED_MEMORY_SIZE ); + } +} diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/uncached_memory.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/uncached_memory.h new file mode 100644 index 0000000..5a8e5f3 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/uncached_memory.h @@ -0,0 +1,23 @@ +/* + * uncached_memory.h + * + * This module will declare 1 MB of memory and switch off the caching for it. + * + * pucGetUncachedMemory( ulSize ) returns a trunc of this memory with a length + * rounded up to a multiple of 4 KB + * + * ucIsCachedMemory( pucBuffer ) returns non-zero if a given pointer is NOT + * within the range of the 1 MB non-cached memory. + * + */ + +#ifndef UNCACHEMEMORY_H + +#define UNCACHEMEMORY_H + +uint8_t *pucGetUncachedMemory( uint32_t ulSize ); + +uint8_t ucIsCachedMemory( const uint8_t *pucBuffer ); + +#endif /* UNCACHEMEMORY_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif.h new file mode 100644 index 0000000..823dee0 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2010-2013 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#ifndef __NETIF_XEMACPSIF_H__ +#define __NETIF_XEMACPSIF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#include "xstatus.h" +#include "sleep.h" +#include "xparameters.h" +#include "xparameters_ps.h" /* defines XPAR values */ +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "xil_exception.h" +#include "xpseudo_asm.h" +#include "xil_cache.h" +#include "xil_printf.h" +#include "xuartps.h" +#include "xscugic.h" +#include "xemacps.h" /* defines XEmacPs API */ + +//#include "netif/xpqueue.h" +//#include "xlwipconfig.h" + +void xemacpsif_setmac(uint32_t index, uint8_t *addr); +uint8_t* xemacpsif_getmac(uint32_t index); +//int xemacpsif_init(struct netif *netif); +//int xemacpsif_input(struct netif *netif); +#ifdef NOTNOW_BHILL +unsigned get_IEEE_phy_speed(XLlTemac *xlltemacp); +#endif + +/* xaxiemacif_hw.c */ +void xemacps_error_handler(XEmacPs * Temac); + +struct xBD_TYPE { + uint32_t address; + uint32_t flags; +}; + +/* + * Missing declaration in 'src/xemacps_hw.h' : + * When set, the GEM DMA will automatically + * discard receive packets from the receiver packet + * buffer memory when no AHB resource is + * available. + * When low, then received packets will remain to be + * stored in the SRAM based packet buffer until + * AHB buffer resource next becomes available. + */ +#define XEMACPS_DMACR_DISC_WHEN_NO_AHB_MASK 0x01000000 + +#define EMAC_IF_RX_EVENT 1 +#define EMAC_IF_TX_EVENT 2 +#define EMAC_IF_ERR_EVENT 4 +#define EMAC_IF_ALL_EVENT 7 + +/* structure within each netif, encapsulating all information required for + * using a particular temac instance + */ +typedef struct { + XEmacPs emacps; + + /* pointers to memory holding buffer descriptors (used only with SDMA) */ + struct xBD_TYPE *rxSegments; + struct xBD_TYPE *txSegments; + + unsigned char *tx_space; + unsigned uTxUnitSize; + + char *remain_mem; + unsigned remain_siz; + + volatile int rxHead, rxTail; + volatile int txHead, txTail; + + volatile int txBusy; + + volatile uint32_t isr_events; + + unsigned int last_rx_frms_cntr; + +} xemacpsif_s; + +//extern xemacpsif_s xemacpsif; + +int is_tx_space_available(xemacpsif_s *emac); + +/* xaxiemacif_dma.c */ + +struct xNETWORK_BUFFER; + +int emacps_check_rx( xemacpsif_s *xemacpsif ); +void emacps_check_tx( xemacpsif_s *xemacpsif ); +int emacps_check_errors( xemacpsif_s *xemacps ); +void emacps_set_rx_buffers( xemacpsif_s *xemacpsif, u32 ulCount ); + +extern XStatus emacps_send_message(xemacpsif_s *xemacpsif, struct xNETWORK_BUFFER *pxBuffer, int iReleaseAfterSend ); +extern unsigned Phy_Setup( XEmacPs *xemacpsp ); +extern void setup_isr( xemacpsif_s *xemacpsif ); +extern XStatus init_dma( xemacpsif_s *xemacpsif ); +extern void start_emacps( xemacpsif_s *xemacpsif ); + +void EmacEnableIntr(void); +void EmacDisableIntr(void); + +XStatus init_axi_dma(xemacpsif_s *xemacpsif); +void process_sent_bds( xemacpsif_s *xemacpsif ); + +void emacps_send_handler(void *arg); +void emacps_recv_handler(void *arg); +void emacps_error_handler(void *arg,u8 Direction, u32 ErrorWord); +void HandleTxErrors(xemacpsif_s *xemacpsif); +XEmacPs_Config *xemacps_lookup_config(unsigned mac_base); + +void clean_dma_txdescs(xemacpsif_s *xemacpsif); +void resetrx_on_no_rxdata(xemacpsif_s *xemacpsif); + +#ifdef __cplusplus +} +#endif + +#endif /* __NETIF_XAXIEMACIF_H__ */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_dma.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_dma.c new file mode 100644 index 0000000..895564c --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_dma.c @@ -0,0 +1,663 @@ +/* +FreeRTOS+TCP V2.0.11 +Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + http://aws.amazon.com/freertos + http://www.FreeRTOS.org + */ + +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_IP_Private.h" +#include "NetworkBufferManagement.h" + +#include "Zynq/x_emacpsif.h" +#include "Zynq/x_topology.h" +#include "xstatus.h" + +#include "xparameters.h" +#include "xparameters_ps.h" +#include "xil_exception.h" +#include "xil_mmu.h" + +#include "uncached_memory.h" + +/* Two defines used to set or clear the EMAC interrupt */ +#define INTC_BASE_ADDR XPAR_SCUGIC_CPU_BASEADDR +#define INTC_DIST_BASE_ADDR XPAR_SCUGIC_DIST_BASEADDR + + + +#if( ipconfigPACKET_FILLER_SIZE != 2 ) + #error Please define ipconfigPACKET_FILLER_SIZE as the value '2' +#endif +#define TX_OFFSET ipconfigPACKET_FILLER_SIZE + +/* Defined in NetworkInterface.c */ +extern TaskHandle_t xEMACTaskHandle; + +/* + pxDMA_tx_buffers: these are character arrays, each one is big enough to hold 1 MTU. + The actual TX buffers are located in uncached RAM. +*/ +static unsigned char *pxDMA_tx_buffers[ ipconfigNIC_N_TX_DESC ] = { NULL }; + +/* + pxDMA_rx_buffers: these are pointers to 'NetworkBufferDescriptor_t'. + Once a message has been received by the EMAC, the descriptor can be passed + immediately to the IP-task. +*/ +static NetworkBufferDescriptor_t *pxDMA_rx_buffers[ ipconfigNIC_N_RX_DESC ] = { NULL }; + +/* + The FreeRTOS+TCP port is using a fixed 'topology', which is declared in + ./portable/NetworkInterface/Zynq/NetworkInterface.c +*/ +extern struct xtopology_t xXTopology; + +static SemaphoreHandle_t xTXDescriptorSemaphore = NULL; + +/* + The FreeRTOS+TCP port does not make use of "src/xemacps_bdring.c". + In stead 'struct xemacpsif_s' has a "head" and a "tail" index. + "head" is the next index to be written, used. + "tail" is the next index to be read, freed. +*/ + +int is_tx_space_available( xemacpsif_s *xemacpsif ) +{ +size_t uxCount; + + if( xTXDescriptorSemaphore != NULL ) + { + uxCount = ( ( UBaseType_t ) ipconfigNIC_N_TX_DESC ) - uxSemaphoreGetCount( xTXDescriptorSemaphore ); + } + else + { + uxCount = ( UBaseType_t ) 0u; + } + + return uxCount; +} + +void emacps_check_tx( xemacpsif_s *xemacpsif ) +{ +int tail = xemacpsif->txTail; +int head = xemacpsif->txHead; +size_t uxCount = ( ( UBaseType_t ) ipconfigNIC_N_TX_DESC ) - uxSemaphoreGetCount( xTXDescriptorSemaphore ); + + /* uxCount is the number of TX descriptors that are in use by the DMA. */ + /* When done, "TXBUF_USED" will be set. */ + + while( ( uxCount > 0 ) && ( ( xemacpsif->txSegments[ tail ].flags & XEMACPS_TXBUF_USED_MASK ) != 0 ) ) + { + if( ( tail == head ) && ( uxCount != ipconfigNIC_N_TX_DESC ) ) + { + break; + } +#if( ipconfigZERO_COPY_TX_DRIVER != 0 ) +#warning ipconfigZERO_COPY_TX_DRIVER is defined + { + void *pvBuffer = pxDMA_tx_buffers[ tail ]; + NetworkBufferDescriptor_t *pxBuffer; + + if( pvBuffer != NULL ) + { + pxDMA_tx_buffers[ tail ] = NULL; + pxBuffer = pxPacketBuffer_to_NetworkBuffer( pvBuffer ); + if( pxBuffer != NULL ) + { + vReleaseNetworkBufferAndDescriptor( pxBuffer ); + } + else + { + FreeRTOS_printf( ( "emacps_check_tx: Can not find network buffer\n" ) ); + } + } + } +#endif + /* Clear all but the "used" and "wrap" bits. */ + if( tail < ipconfigNIC_N_TX_DESC - 1 ) + { + xemacpsif->txSegments[ tail ].flags = XEMACPS_TXBUF_USED_MASK; + } + else + { + xemacpsif->txSegments[ tail ].flags = XEMACPS_TXBUF_USED_MASK | XEMACPS_TXBUF_WRAP_MASK; + } + uxCount--; + /* Tell the counting semaphore that one more TX descriptor is available. */ + xSemaphoreGive( xTXDescriptorSemaphore ); + if( ++tail == ipconfigNIC_N_TX_DESC ) + { + tail = 0; + } + xemacpsif->txTail = tail; + } + + return; +} + +void emacps_send_handler(void *arg) +{ +xemacpsif_s *xemacpsif; +BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + xemacpsif = (xemacpsif_s *)(arg); + + /* In this port for FreeRTOS+TCP, the EMAC interrupts will only set a bit in + "isr_events". The task in NetworkInterface will wake-up and do the necessary work. + */ + xemacpsif->isr_events |= EMAC_IF_TX_EVENT; + xemacpsif->txBusy = pdFALSE; + + if( xEMACTaskHandle != NULL ) + { + vTaskNotifyGiveFromISR( xEMACTaskHandle, &xHigherPriorityTaskWoken ); + } + + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); +} + +static BaseType_t xValidLength( BaseType_t xLength ) +{ +BaseType_t xReturn; + + if( ( xLength >= ( BaseType_t ) sizeof( struct xARP_PACKET ) ) && ( ( ( uint32_t ) xLength ) <= ipTOTAL_ETHERNET_FRAME_SIZE ) ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} + +XStatus emacps_send_message(xemacpsif_s *xemacpsif, NetworkBufferDescriptor_t *pxBuffer, int iReleaseAfterSend ) +{ +int head = xemacpsif->txHead; +//int tail = xemacpsif->txTail; +int iHasSent = 0; +uint32_t ulBaseAddress = xemacpsif->emacps.Config.BaseAddress; +TickType_t xBlockTimeTicks = pdMS_TO_TICKS( 5000u ); + + #if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + { + /* This driver wants to own all network buffers which are to be transmitted. */ + configASSERT( iReleaseAfterSend != pdFALSE ); + } + #endif + + /* Open a do {} while ( 0 ) loop to be able to call break. */ + do + { + uint32_t ulFlags = 0; + + if( xValidLength( pxBuffer->xDataLength ) != pdTRUE ) + { + break; + } + + if( xTXDescriptorSemaphore == NULL ) + { + break; + } + + if( xSemaphoreTake( xTXDescriptorSemaphore, xBlockTimeTicks ) != pdPASS ) + { + FreeRTOS_printf( ( "emacps_send_message: Time-out waiting for TX buffer\n" ) ); + break; + } + +#if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + /* Pass the pointer (and its ownership) directly to DMA. */ + pxDMA_tx_buffers[ head ] = pxBuffer->pucEthernetBuffer; + if( ucIsCachedMemory( pxBuffer->pucEthernetBuffer ) != 0 ) + { + Xil_DCacheFlushRange( ( unsigned )pxBuffer->pucEthernetBuffer, pxBuffer->xDataLength ); + } + /* Buffer has been transferred, do not release it. */ + iReleaseAfterSend = pdFALSE; +#else + if( pxDMA_tx_buffers[ head ] == NULL ) + { + FreeRTOS_printf( ( "emacps_send_message: pxDMA_tx_buffers[ %d ] == NULL\n", head ) ); + break; + } + /* Copy the message to unbuffered space in RAM. */ + memcpy( pxDMA_tx_buffers[ head ], pxBuffer->pucEthernetBuffer, pxBuffer->xDataLength ); +#endif + /* Packets will be sent one-by-one, so for each packet + the TXBUF_LAST bit will be set. */ + ulFlags |= XEMACPS_TXBUF_LAST_MASK; + ulFlags |= ( pxBuffer->xDataLength & XEMACPS_TXBUF_LEN_MASK ); + if( head == ( ipconfigNIC_N_TX_DESC - 1 ) ) + { + ulFlags |= XEMACPS_TXBUF_WRAP_MASK; + } + + /* Copy the address of the buffer and set the flags. */ + xemacpsif->txSegments[ head ].address = ( uint32_t )pxDMA_tx_buffers[ head ]; + xemacpsif->txSegments[ head ].flags = ulFlags; + + iHasSent = pdTRUE; + if( ++head == ipconfigNIC_N_TX_DESC ) + { + head = 0; + } + /* Update the TX-head index. These variable are declared volatile so they will be + accessed as little as possible. */ + xemacpsif->txHead = head; + } while( pdFALSE ); + + if( iReleaseAfterSend != pdFALSE ) + { + vReleaseNetworkBufferAndDescriptor( pxBuffer ); + pxBuffer = NULL; + } + + /* Data Synchronization Barrier */ + dsb(); + + if( iHasSent != pdFALSE ) + { + /* Make STARTTX high */ + uint32_t ulValue = XEmacPs_ReadReg( ulBaseAddress, XEMACPS_NWCTRL_OFFSET); + /* Start transmit */ + xemacpsif->txBusy = pdTRUE; + XEmacPs_WriteReg( ulBaseAddress, XEMACPS_NWCTRL_OFFSET, ( ulValue | XEMACPS_NWCTRL_STARTTX_MASK ) ); + } + dsb(); + + return 0; +} + +void emacps_recv_handler(void *arg) +{ + xemacpsif_s *xemacpsif; + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + xemacpsif = (xemacpsif_s *)(arg); + xemacpsif->isr_events |= EMAC_IF_RX_EVENT; + + if( xEMACTaskHandle != NULL ) + { + vTaskNotifyGiveFromISR( xEMACTaskHandle, &xHigherPriorityTaskWoken ); + } + + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); +} + +static void passEthMessages( NetworkBufferDescriptor_t *ethMsg ) +{ +IPStackEvent_t xRxEvent; + + xRxEvent.eEventType = eNetworkRxEvent; + xRxEvent.pvData = ( void * ) ethMsg; + + if( xSendEventStructToIPTask( &xRxEvent, ( TickType_t ) 1000 ) != pdPASS ) + { + /* The buffer could not be sent to the stack so must be released again. + This is a deferred handler taskr, not a real interrupt, so it is ok to + use the task level function here. */ + do + { + NetworkBufferDescriptor_t *xNext = ethMsg->pxNextBuffer; + vReleaseNetworkBufferAndDescriptor( ethMsg ); + ethMsg = xNext; + } while( ethMsg != NULL ); + + iptraceETHERNET_RX_EVENT_LOST(); + FreeRTOS_printf( ( "passEthMessages: Can not queue return packet!\n" ) ); + } +} + +TickType_t ack_reception_delay = 10; + +int emacps_check_rx( xemacpsif_s *xemacpsif ) +{ +NetworkBufferDescriptor_t *pxBuffer, *pxNewBuffer; +int rx_bytes; +volatile int msgCount = 0; +int head = xemacpsif->rxHead; +BaseType_t bHasDataPacket = pdFALSE; +NetworkBufferDescriptor_t *ethMsg = NULL; +NetworkBufferDescriptor_t *ethLast = NULL; + + /* There seems to be an issue (SI# 692601), see comments below. */ + resetrx_on_no_rxdata(xemacpsif); + + { + static int maxcount = 0; + int count = 0; + for( ;; ) + { + if( ( ( xemacpsif->rxSegments[ head ].address & XEMACPS_RXBUF_NEW_MASK ) == 0 ) || + ( pxDMA_rx_buffers[ head ] == NULL ) ) + { + break; + } + count++; + if( ++head == ipconfigNIC_N_RX_DESC ) + { + head = 0; + } + if( head == xemacpsif->rxHead ) + { + break; + } + } + if (maxcount < count) { + maxcount = count; + FreeRTOS_printf( ( "emacps_check_rx: %d packets\n", maxcount ) ); + } + head = xemacpsif->rxHead; + } + + /* This FreeRTOS+TCP driver shall be compiled with the option + "ipconfigUSE_LINKED_RX_MESSAGES" enabled. It allows the driver to send a + chain of RX messages within one message to the IP-task. */ + for( ;; ) + { + if( ( ( xemacpsif->rxSegments[ head ].address & XEMACPS_RXBUF_NEW_MASK ) == 0 ) || + ( pxDMA_rx_buffers[ head ] == NULL ) ) + { + break; + } + + pxNewBuffer = pxGetNetworkBufferWithDescriptor( ipTOTAL_ETHERNET_FRAME_SIZE, ( TickType_t ) 0 ); + if( pxNewBuffer == NULL ) + { + /* A packet has been received, but there is no replacement for this Network Buffer. + The packet will be dropped, and it Network Buffer will stay in place. */ + FreeRTOS_printf( ("emacps_check_rx: unable to allocate a Netwrok Buffer\n" ) ); + pxNewBuffer = ( NetworkBufferDescriptor_t * )pxDMA_rx_buffers[ head ]; + } + else + { + pxBuffer = ( NetworkBufferDescriptor_t * )pxDMA_rx_buffers[ head ]; + + /* Just avoiding to use or refer to the same buffer again */ + pxDMA_rx_buffers[ head ] = pxNewBuffer; + + /* + * Adjust the buffer size to the actual number of bytes received. + */ + rx_bytes = xemacpsif->rxSegments[ head ].flags & XEMACPS_RXBUF_LEN_MASK; + + pxBuffer->xDataLength = rx_bytes; +if( rx_bytes > 60 ) +{ + bHasDataPacket = 1; +} + if( ucIsCachedMemory( pxBuffer->pucEthernetBuffer ) != 0 ) + { + Xil_DCacheInvalidateRange( ( ( uint32_t )pxBuffer->pucEthernetBuffer ) - ipconfigPACKET_FILLER_SIZE, (unsigned)rx_bytes ); + } + + /* store it in the receive queue, where it'll be processed by a + different handler. */ + iptraceNETWORK_INTERFACE_RECEIVE(); + pxBuffer->pxNextBuffer = NULL; + + if( ethMsg == NULL ) + { + // Becomes the first message + ethMsg = pxBuffer; + } + else if( ethLast != NULL ) + { + // Add to the tail + ethLast->pxNextBuffer = pxBuffer; + } + + ethLast = pxBuffer; + msgCount++; + } + { + if( ucIsCachedMemory( pxNewBuffer->pucEthernetBuffer ) != 0 ) + { + Xil_DCacheInvalidateRange( ( ( uint32_t )pxNewBuffer->pucEthernetBuffer ) - ipconfigPACKET_FILLER_SIZE, (unsigned)ipTOTAL_ETHERNET_FRAME_SIZE ); + } + { + uint32_t addr = ( ( uint32_t )pxNewBuffer->pucEthernetBuffer ) & XEMACPS_RXBUF_ADD_MASK; + if( head == ( ipconfigNIC_N_RX_DESC - 1 ) ) + { + addr |= XEMACPS_RXBUF_WRAP_MASK; + } + /* Clearing 'XEMACPS_RXBUF_NEW_MASK' 0x00000001 *< Used bit.. */ + xemacpsif->rxSegments[ head ].flags = 0; + xemacpsif->rxSegments[ head ].address = addr; + if (xemacpsif->rxSegments[ head ].address) { + // Just to read it + } + } + } + + if( ++head == ipconfigNIC_N_RX_DESC ) + { + head = 0; + } + xemacpsif->rxHead = head; + } + + if( ethMsg != NULL ) + { + if( bHasDataPacket == pdFALSE ) + { +// vTaskDelay( ack_reception_delay ); + } + passEthMessages( ethMsg ); + } + + return msgCount; +} + +void clean_dma_txdescs(xemacpsif_s *xemacpsif) +{ +int index; +unsigned char *ucTxBuffer; + + /* Clear all TX descriptors and assign uncached memory to each descriptor. + "tx_space" points to the first available TX buffer. */ + ucTxBuffer = xemacpsif->tx_space; + + for( index = 0; index < ipconfigNIC_N_TX_DESC; index++ ) + { + xemacpsif->txSegments[ index ].address = ( uint32_t )ucTxBuffer; + xemacpsif->txSegments[ index ].flags = XEMACPS_TXBUF_USED_MASK; +#if( ipconfigZERO_COPY_TX_DRIVER != 0 ) + pxDMA_tx_buffers[ index ] = ( unsigned char * )NULL; +#else + pxDMA_tx_buffers[ index ] = ( unsigned char * )( ucTxBuffer + TX_OFFSET ); +#endif + ucTxBuffer += xemacpsif->uTxUnitSize; + } + xemacpsif->txSegments[ ipconfigNIC_N_TX_DESC - 1 ].flags = + XEMACPS_TXBUF_USED_MASK | XEMACPS_TXBUF_WRAP_MASK; +} + +XStatus init_dma(xemacpsif_s *xemacpsif) +{ + NetworkBufferDescriptor_t *pxBuffer; + + int iIndex; + UBaseType_t xRxSize; + UBaseType_t xTxSize; + struct xtopology_t *xtopologyp = &xXTopology; + + xRxSize = ipconfigNIC_N_RX_DESC * sizeof( xemacpsif->rxSegments[ 0 ] ); + + xTxSize = ipconfigNIC_N_TX_DESC * sizeof( xemacpsif->txSegments[ 0 ] ); + + /* Also round-up to 4KB */ + xemacpsif->uTxUnitSize = ( ipTOTAL_ETHERNET_FRAME_SIZE + 0x1000ul ) & ~0xffful; + /* + * We allocate 65536 bytes for RX BDs which can accommodate a + * maximum of 8192 BDs which is much more than any application + * will ever need. + */ + xemacpsif->rxSegments = ( struct xBD_TYPE * )( pucGetUncachedMemory ( xRxSize ) ); + xemacpsif->txSegments = ( struct xBD_TYPE * )( pucGetUncachedMemory ( xTxSize ) ); + xemacpsif->tx_space = ( unsigned char * )( pucGetUncachedMemory ( ipconfigNIC_N_TX_DESC * xemacpsif->uTxUnitSize ) ); + + /* These variables will be used in XEmacPs_Start (see src/xemacps.c). */ + xemacpsif->emacps.RxBdRing.BaseBdAddr = ( uint32_t ) xemacpsif->rxSegments; + xemacpsif->emacps.TxBdRing.BaseBdAddr = ( uint32_t ) xemacpsif->txSegments; + + if( xTXDescriptorSemaphore == NULL ) + { + xTXDescriptorSemaphore = xSemaphoreCreateCounting( ( UBaseType_t ) ipconfigNIC_N_TX_DESC, ( UBaseType_t ) ipconfigNIC_N_TX_DESC ); + configASSERT( xTXDescriptorSemaphore ); + } + /* + * Allocate RX descriptors, 1 RxBD at a time. + */ + for( iIndex = 0; iIndex < ipconfigNIC_N_RX_DESC; iIndex++ ) + { + pxBuffer = pxDMA_rx_buffers[ iIndex ]; + if( pxBuffer == NULL ) + { + pxBuffer = pxGetNetworkBufferWithDescriptor( ipTOTAL_ETHERNET_FRAME_SIZE, ( TickType_t ) 0 ); + if( pxBuffer == NULL ) + { + FreeRTOS_printf( ("Unable to allocate a network buffer in recv_handler\n" ) ); + return -1; + } + } + + xemacpsif->rxSegments[ iIndex ].flags = 0; + xemacpsif->rxSegments[ iIndex ].address = ( ( uint32_t )pxBuffer->pucEthernetBuffer ) & XEMACPS_RXBUF_ADD_MASK; + + pxDMA_rx_buffers[ iIndex ] = pxBuffer; + /* Make sure this memory is not in cache for now. */ + if( ucIsCachedMemory( pxBuffer->pucEthernetBuffer ) != 0 ) + { + Xil_DCacheInvalidateRange( ( ( uint32_t )pxBuffer->pucEthernetBuffer ) - ipconfigPACKET_FILLER_SIZE, + (unsigned)ipTOTAL_ETHERNET_FRAME_SIZE ); + } + } + + xemacpsif->rxSegments[ ipconfigNIC_N_RX_DESC - 1 ].address |= XEMACPS_RXBUF_WRAP_MASK; + + memset( xemacpsif->tx_space, '\0', ipconfigNIC_N_TX_DESC * xemacpsif->uTxUnitSize ); + + clean_dma_txdescs( xemacpsif ); + + { + uint32_t value; + value = XEmacPs_ReadReg( xemacpsif->emacps.Config.BaseAddress, XEMACPS_DMACR_OFFSET ); + + // 1xxxx: Attempt to use INCR16 AHB bursts + value = ( value & ~( XEMACPS_DMACR_BLENGTH_MASK ) ) | XEMACPS_DMACR_INCR16_AHB_BURST; +#if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM != 0 ) + value |= XEMACPS_DMACR_TCPCKSUM_MASK; +#else +#warning Are you sure the EMAC should not calculate outgoing checksums? + value &= ~XEMACPS_DMACR_TCPCKSUM_MASK; +#endif + XEmacPs_WriteReg( xemacpsif->emacps.Config.BaseAddress, XEMACPS_DMACR_OFFSET, value ); + } + { + uint32_t value; + value = XEmacPs_ReadReg( xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCFG_OFFSET ); + + /* Network buffers are 32-bit aligned + 2 bytes (because ipconfigPACKET_FILLER_SIZE = 2 ). + Now tell the EMAC that received messages should be stored at "address + 2". */ + value = ( value & ~XEMACPS_NWCFG_RXOFFS_MASK ) | 0x8000; + +#if( ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM != 0 ) + value |= XEMACPS_NWCFG_RXCHKSUMEN_MASK; +#else +#warning Are you sure the EMAC should not calculate incoming checksums? + value &= ~XEMACPS_NWCFG_RXCHKSUMEN_MASK; +#endif + XEmacPs_WriteReg( xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCFG_OFFSET, value ); + } + + /* + * Connect the device driver handler that will be called when an + * interrupt for the device occurs, the handler defined above performs + * the specific interrupt processing for the device. + */ + XScuGic_RegisterHandler(INTC_BASE_ADDR, xtopologyp->scugic_emac_intr, + (Xil_ExceptionHandler)XEmacPs_IntrHandler, + (void *)&xemacpsif->emacps); + /* + * Enable the interrupt for emacps. + */ + EmacEnableIntr( ); + + return 0; +} + +/* + * resetrx_on_no_rxdata(): + * + * It is called at regular intervals through the API xemacpsif_resetrx_on_no_rxdata + * called by the user. + * The EmacPs has a HW bug (SI# 692601) on the Rx path for heavy Rx traffic. + * Under heavy Rx traffic because of the HW bug there are times when the Rx path + * becomes unresponsive. The workaround for it is to check for the Rx path for + * traffic (by reading the stats registers regularly). If the stats register + * does not increment for sometime (proving no Rx traffic), the function resets + * the Rx data path. + * + */ + +void resetrx_on_no_rxdata(xemacpsif_s *xemacpsif) +{ + unsigned long regctrl; + unsigned long tempcntr; + + tempcntr = XEmacPs_ReadReg( xemacpsif->emacps.Config.BaseAddress, XEMACPS_RXCNT_OFFSET ); + if ( ( tempcntr == 0 ) && ( xemacpsif->last_rx_frms_cntr == 0 ) ) + { +FreeRTOS_printf( ( "resetrx_on_no_rxdata: RESET~\n" ) ); + regctrl = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + regctrl &= (~XEMACPS_NWCTRL_RXEN_MASK); + XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, regctrl); + regctrl = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCTRL_OFFSET); + regctrl |= (XEMACPS_NWCTRL_RXEN_MASK); + XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCTRL_OFFSET, regctrl); + } + xemacpsif->last_rx_frms_cntr = tempcntr; +} + +void EmacDisableIntr(void) +{ + XScuGic_DisableIntr(INTC_DIST_BASE_ADDR, xXTopology.scugic_emac_intr); +} + +void EmacEnableIntr(void) +{ + XScuGic_EnableIntr(INTC_DIST_BASE_ADDR, xXTopology.scugic_emac_intr); +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_hw.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_hw.c new file mode 100644 index 0000000..83c504a --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_hw.c @@ -0,0 +1,239 @@ +/* + * Copyright (c) 2010-2013 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + + +/* Standard includes. */ +#include +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_IP_Private.h" +#include "NetworkBufferManagement.h" +#include "NetworkInterface.h" + +#include "Zynq/x_emacpsif.h" + +extern TaskHandle_t xEMACTaskHandle; + +/*** IMPORTANT: Define PEEP in xemacpsif.h and sys_arch_raw.c + *** to run it on a PEEP board + ***/ + +void setup_isr( xemacpsif_s *xemacpsif ) +{ + /* + * Setup callbacks + */ + XEmacPs_SetHandler(&xemacpsif->emacps, XEMACPS_HANDLER_DMASEND, + (void *) emacps_send_handler, + (void *) xemacpsif); + + XEmacPs_SetHandler(&xemacpsif->emacps, XEMACPS_HANDLER_DMARECV, + (void *) emacps_recv_handler, + (void *) xemacpsif); + + XEmacPs_SetHandler(&xemacpsif->emacps, XEMACPS_HANDLER_ERROR, + (void *) emacps_error_handler, + (void *) xemacpsif); +} + +void start_emacps (xemacpsif_s *xemacps) +{ + /* start the temac */ + XEmacPs_Start(&xemacps->emacps); +} + +extern struct xtopology_t xXTopology; + +volatile int error_msg_count = 0; +volatile const char *last_err_msg = ""; + +struct xERROR_MSG { + void *arg; + u8 Direction; + u32 ErrorWord; +}; + +static struct xERROR_MSG xErrorList[ 8 ]; +static BaseType_t xErrorHead, xErrorTail; + +void emacps_error_handler(void *arg, u8 Direction, u32 ErrorWord) +{ + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + xemacpsif_s *xemacpsif; + BaseType_t xNextHead = xErrorHead; + + xemacpsif = (xemacpsif_s *)(arg); + + if( ( Direction != XEMACPS_SEND ) || (ErrorWord != XEMACPS_TXSR_USEDREAD_MASK ) ) + { + if( ++xNextHead == ( sizeof( xErrorList ) / sizeof( xErrorList[ 0 ] ) ) ) + xNextHead = 0; + if( xNextHead != xErrorTail ) + { + + xErrorList[ xErrorHead ].arg = arg; + xErrorList[ xErrorHead ].Direction = Direction; + xErrorList[ xErrorHead ].ErrorWord = ErrorWord; + + xErrorHead = xNextHead; + + xemacpsif = (xemacpsif_s *)(arg); + xemacpsif->isr_events |= EMAC_IF_ERR_EVENT; + } + + if( xEMACTaskHandle != NULL ) + { + vTaskNotifyGiveFromISR( xEMACTaskHandle, &xHigherPriorityTaskWoken ); + } + + } + + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); +} + +static void emacps_handle_error(void *arg, u8 Direction, u32 ErrorWord); + +int emacps_check_errors( xemacpsif_s *xemacps ) +{ +int xResult; + + ( void ) xemacps; + + if( xErrorHead == xErrorTail ) + { + xResult = 0; + } + else + { + xResult = 1; + emacps_handle_error( + xErrorList[ xErrorTail ].arg, + xErrorList[ xErrorTail ].Direction, + xErrorList[ xErrorTail ].ErrorWord ); + } + + return xResult; +} + +static void emacps_handle_error(void *arg, u8 Direction, u32 ErrorWord) +{ + xemacpsif_s *xemacpsif; + struct xtopology_t *xtopologyp; + XEmacPs *xemacps; + + xemacpsif = (xemacpsif_s *)(arg); + + xtopologyp = &xXTopology; + + xemacps = &xemacpsif->emacps; + + /* Do not appear to be used. */ + ( void ) xemacps; + ( void ) xtopologyp; + + last_err_msg = NULL; + + if( ErrorWord != 0 ) + { + switch (Direction) { + case XEMACPS_RECV: + if( ( ErrorWord & XEMACPS_RXSR_HRESPNOK_MASK ) != 0 ) + { + last_err_msg = "Receive DMA error"; + xNetworkInterfaceInitialise( ); + } + if( ( ErrorWord & XEMACPS_RXSR_RXOVR_MASK ) != 0 ) + { + last_err_msg = "Receive over run"; + emacps_recv_handler(arg); + } + if( ( ErrorWord & XEMACPS_RXSR_BUFFNA_MASK ) != 0 ) + { + last_err_msg = "Receive buffer not available"; + emacps_recv_handler(arg); + } + break; + case XEMACPS_SEND: + if( ( ErrorWord & XEMACPS_TXSR_HRESPNOK_MASK ) != 0 ) + { + last_err_msg = "Transmit DMA error"; + xNetworkInterfaceInitialise( ); + } + if( ( ErrorWord & XEMACPS_TXSR_URUN_MASK ) != 0 ) + { + last_err_msg = "Transmit under run"; + HandleTxErrors( xemacpsif ); + } + if( ( ErrorWord & XEMACPS_TXSR_BUFEXH_MASK ) != 0 ) + { + last_err_msg = "Transmit buffer exhausted"; + HandleTxErrors( xemacpsif ); + } + if( ( ErrorWord & XEMACPS_TXSR_RXOVR_MASK ) != 0 ) + { + last_err_msg = "Transmit retry excessed limits"; + HandleTxErrors( xemacpsif ); + } + if( ( ErrorWord & XEMACPS_TXSR_FRAMERX_MASK ) != 0 ) + { + last_err_msg = "Transmit collision"; + emacps_check_tx( xemacpsif ); + } + break; + } + } + // Break on this statement and inspect error_msg if you like + if( last_err_msg != NULL ) + { + error_msg_count++; + FreeRTOS_printf( ( "emacps_handle_error: %s\n", last_err_msg ) ); + } +} + +extern XEmacPs_Config mac_config; + +void HandleTxErrors(xemacpsif_s *xemacpsif) +{ + u32 netctrlreg; + + //taskENTER_CRITICAL() + { + netctrlreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + netctrlreg = netctrlreg & (~XEMACPS_NWCTRL_TXEN_MASK); + XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, netctrlreg); + + clean_dma_txdescs( xemacpsif ); + netctrlreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + netctrlreg = netctrlreg | (XEMACPS_NWCTRL_TXEN_MASK); + XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, netctrlreg); + } + //taskEXIT_CRITICAL( ); +} diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_hw.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_hw.h new file mode 100644 index 0000000..f3c424a --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_hw.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2010-2013 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#ifndef __XEMACPSIF_HW_H_ +#define __XEMACPSIF_HW_H_ + +#include "Zynq/x_emacpsif.h" +//#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +XEmacPs_Config * lookup_config(unsigned mac_base); + +//void init_emacps(xemacpsif_s *xemacpsif, struct netif *netif); + +int emacps_check_errors( xemacpsif_s *xemacps ); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_physpeed.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_physpeed.c new file mode 100644 index 0000000..dd0cf0a --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_emacpsif_physpeed.c @@ -0,0 +1,581 @@ +/* + * Copyright (c) 2007-2008, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names + * of its contributors may be used to endorse or promote products + * derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Some portions copyright (c) 2010-2013 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +/* Standard includes. */ +#include +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_IP_Private.h" +#include "NetworkBufferManagement.h" + +#include "Zynq/x_emacpsif.h" +#include "xparameters_ps.h" +#include "xparameters.h" + + +int phy_detected = 0; + +/*** IMPORTANT: Define PEEP in xemacpsif.h and sys_arch_raw.c + *** to run it on a PEEP board + ***/ + +/* Advertisement control register. */ +#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ +#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ +#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ +#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ + +#define ADVERTISE_100_AND_10 (ADVERTISE_10FULL | ADVERTISE_100FULL | \ + ADVERTISE_10HALF | ADVERTISE_100HALF) +#define ADVERTISE_100 (ADVERTISE_100FULL | ADVERTISE_100HALF) +#define ADVERTISE_10 (ADVERTISE_10FULL | ADVERTISE_10HALF) + +#define ADVERTISE_1000 0x0300 + + +//#define PHY_REG_00_BMCR 0x00 // Basic mode control register +//#define PHY_REG_01_BMSR 0x01 // Basic mode status register +//#define PHY_REG_02_PHYSID1 0x02 // PHYS ID 1 +//#define PHY_REG_03_PHYSID2 0x03 // PHYS ID 2 +//#define PHY_REG_04_ADVERTISE 0x04 // Advertisement control reg + +#define IEEE_CONTROL_REG_OFFSET 0 +#define IEEE_STATUS_REG_OFFSET 1 +#define IEEE_PHYSID1_OFFSET 2 +#define IEEE_PHYSID2_OFFSET 3 +#define IEEE_AUTONEGO_ADVERTISE_REG 4 +#define IEEE_PARTNER_ABILITIES_1_REG_OFFSET 5 +#define IEEE_1000_ADVERTISE_REG_OFFSET 9 +#define IEEE_PARTNER_ABILITIES_3_REG_OFFSET 10 +#define IEEE_COPPER_SPECIFIC_CONTROL_REG 16 +#define IEEE_SPECIFIC_STATUS_REG 17 +#define IEEE_COPPER_SPECIFIC_STATUS_REG_2 19 +#define IEEE_CONTROL_REG_MAC 21 +#define IEEE_PAGE_ADDRESS_REGISTER 22 + + +#define IEEE_CTRL_1GBPS_LINKSPEED_MASK 0x2040 +#define IEEE_CTRL_LINKSPEED_MASK 0x0040 +#define IEEE_CTRL_LINKSPEED_1000M 0x0040 +#define IEEE_CTRL_LINKSPEED_100M 0x2000 +#define IEEE_CTRL_LINKSPEED_10M 0x0000 +#define IEEE_CTRL_RESET_MASK 0x8000 +#define IEEE_CTRL_AUTONEGOTIATE_ENABLE 0x1000 +#if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1 +#define IEEE_CTRL_RESET 0x9140 +#define IEEE_CTRL_ISOLATE_DISABLE 0xFBFF +#endif +#define IEEE_STAT_AUTONEGOTIATE_CAPABLE 0x0008 +#define IEEE_STAT_AUTONEGOTIATE_COMPLETE 0x0020 +#define IEEE_STAT_AUTONEGOTIATE_RESTART 0x0200 +#define IEEE_STAT_1GBPS_EXTENSIONS 0x0100 +#define IEEE_AN1_ABILITY_MASK 0x1FE0 +#define IEEE_AN3_ABILITY_MASK_1GBPS 0x0C00 +#define IEEE_AN1_ABILITY_MASK_100MBPS 0x0380 +#define IEEE_AN1_ABILITY_MASK_10MBPS 0x0060 +#define IEEE_RGMII_TXRX_CLOCK_DELAYED_MASK 0x0030 + +#define IEEE_ASYMMETRIC_PAUSE_MASK 0x0800 +#define IEEE_PAUSE_MASK 0x0400 +#define IEEE_AUTONEG_ERROR_MASK 0x8000 + +#define XEMACPS_GMII2RGMII_SPEED1000_FD 0x140 +#define XEMACPS_GMII2RGMII_SPEED100_FD 0x2100 +#define XEMACPS_GMII2RGMII_SPEED10_FD 0x100 +#define XEMACPS_GMII2RGMII_REG_NUM 0x10 + +/* Frequency setting */ +#define SLCR_LOCK_ADDR (XPS_SYS_CTRL_BASEADDR + 0x4) +#define SLCR_UNLOCK_ADDR (XPS_SYS_CTRL_BASEADDR + 0x8) +#define SLCR_GEM0_CLK_CTRL_ADDR (XPS_SYS_CTRL_BASEADDR + 0x140) +#define SLCR_GEM1_CLK_CTRL_ADDR (XPS_SYS_CTRL_BASEADDR + 0x144) +#ifdef PEEP +#define SLCR_GEM_10M_CLK_CTRL_VALUE 0x00103031 +#define SLCR_GEM_100M_CLK_CTRL_VALUE 0x00103001 +#define SLCR_GEM_1G_CLK_CTRL_VALUE 0x00103011 +#endif +#define SLCR_LOCK_KEY_VALUE 0x767B +#define SLCR_UNLOCK_KEY_VALUE 0xDF0D +#define SLCR_ADDR_GEM_RST_CTRL (XPS_SYS_CTRL_BASEADDR + 0x214) +#define EMACPS_SLCR_DIV_MASK 0xFC0FC0FF + +#define EMAC0_BASE_ADDRESS 0xE000B000 +#define EMAC1_BASE_ADDRESS 0xE000C000 + +static int detect_phy(XEmacPs *xemacpsp) +{ + u16 id_lower, id_upper; + u32 phy_addr, id; + + for (phy_addr = 0; phy_addr < 32; phy_addr++) { + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_PHYSID1_OFFSET, &id_lower); + + if ((id_lower != ( u16 )0xFFFFu) && (id_lower != ( u16 )0x0u)) { + + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_PHYSID2_OFFSET, &id_upper); + id = ( ( ( uint32_t ) id_upper ) << 16 ) | ( id_lower & 0xFFF0 ); + FreeRTOS_printf( ("XEmacPs detect_phy: %04lX at address %d.\n", id, phy_addr ) ); + phy_detected = phy_addr; + return phy_addr; + } + } + + FreeRTOS_printf( ("XEmacPs detect_phy: No PHY detected. Assuming a PHY at address 0\n" ) ); + + /* default to zero */ + return 0; +} + +#ifdef PEEP +unsigned get_IEEE_phy_speed(XEmacPs *xemacpsp) +{ + + u16 control; + u16 status; + u16 partner_capabilities; + u16 partner_capabilities_1000; + u16 phylinkspeed; + u32 phy_addr = detect_phy(xemacpsp); + + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, + ADVERTISE_1000); + /* Advertise PHY speed of 100 and 10 Mbps */ + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, + ADVERTISE_100_AND_10); + + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, + &control); + control |= (IEEE_CTRL_AUTONEGOTIATE_ENABLE | + IEEE_STAT_AUTONEGOTIATE_RESTART); + + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control); + + /* Read PHY control and status registers is successful. */ + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control); + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status); + + if ((control & IEEE_CTRL_AUTONEGOTIATE_ENABLE) && (status & + IEEE_STAT_AUTONEGOTIATE_CAPABLE)) { + + while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) { + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, + &status); + } + + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_PARTNER_ABILITIES_1_REG_OFFSET, + &partner_capabilities); + + if (status & IEEE_STAT_1GBPS_EXTENSIONS) { + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_PARTNER_ABILITIES_3_REG_OFFSET, + &partner_capabilities_1000); + if (partner_capabilities_1000 & IEEE_AN3_ABILITY_MASK_1GBPS) + return 1000; + } + + if (partner_capabilities & IEEE_AN1_ABILITY_MASK_100MBPS) + return 100; + if (partner_capabilities & IEEE_AN1_ABILITY_MASK_10MBPS) + return 10; + + xil_printf("%s: unknown PHY link speed, setting TEMAC speed to be 10 Mbps\n", + __FUNCTION__); + return 10; + + } else { + + /* Update TEMAC speed accordingly */ + if (status & IEEE_STAT_1GBPS_EXTENSIONS) { + /* Get commanded link speed */ + phylinkspeed = control & IEEE_CTRL_1GBPS_LINKSPEED_MASK; + + switch (phylinkspeed) { + case (IEEE_CTRL_LINKSPEED_1000M): + return 1000; + case (IEEE_CTRL_LINKSPEED_100M): + return 100; + case (IEEE_CTRL_LINKSPEED_10M): + return 10; + default: + xil_printf("%s: unknown PHY link speed (%d), setting TEMAC speed to be 10 Mbps\n", + __FUNCTION__, phylinkspeed); + return 10; + } + + } else { + + return (control & IEEE_CTRL_LINKSPEED_MASK) ? 100 : 10; + + } + } +} + +#else /* Zynq */ +unsigned get_IEEE_phy_speed(XEmacPs *xemacpsp) +{ + u16 temp; + u16 control; + u16 status; + u16 partner_capabilities; +#if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1 + u32 phy_addr = XPAR_PCSPMA_SGMII_PHYADDR; +#else + u32 phy_addr = detect_phy(xemacpsp); +#endif + xil_printf("Start PHY autonegotiation \n"); + +#if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1 +#else + XEmacPs_PhyWrite(xemacpsp,phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 2); + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, &control); + control |= IEEE_RGMII_TXRX_CLOCK_DELAYED_MASK; + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, control); + + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0); + + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &control); + control |= IEEE_ASYMMETRIC_PAUSE_MASK; + control |= IEEE_PAUSE_MASK; + control |= ADVERTISE_100; + control |= ADVERTISE_10; + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, control); + + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, + &control); + control |= ADVERTISE_1000; + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, + control); + + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0); + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_COPPER_SPECIFIC_CONTROL_REG, + &control); + control |= (7 << 12); /* max number of gigabit attempts */ + control |= (1 << 11); /* enable downshift */ + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_COPPER_SPECIFIC_CONTROL_REG, + control); +#endif + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control); + control |= IEEE_CTRL_AUTONEGOTIATE_ENABLE; + control |= IEEE_STAT_AUTONEGOTIATE_RESTART; +#if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1 + control &= IEEE_CTRL_ISOLATE_DISABLE; +#endif + + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control); + + +#if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1 +#else + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control); + control |= IEEE_CTRL_RESET_MASK; + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control); + + while (1) { + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control); + if (control & IEEE_CTRL_RESET_MASK) + continue; + else + break; + } +#endif + xil_printf("Waiting for PHY to complete autonegotiation.\n"); + + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status); + while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) { + sleep(1); +#if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1 +#else + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_COPPER_SPECIFIC_STATUS_REG_2, + &temp); + if (temp & IEEE_AUTONEG_ERROR_MASK) { + xil_printf("Auto negotiation error \n"); + } +#endif + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, + &status); + } + + xil_printf("autonegotiation complete \n"); + +#if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1 +#else + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_SPECIFIC_STATUS_REG, &partner_capabilities); +#endif + +#if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1 + xil_printf("Waiting for Link to be up; Polling for SGMII core Reg \n"); + XEmacPs_PhyRead(xemacpsp, phy_addr, 5, &temp); + while(!(temp & 0x8000)) { + XEmacPs_PhyRead(xemacpsp, phy_addr, 5, &temp); + } + if((temp & 0x0C00) == 0x0800) { + XEmacPs_PhyRead(xemacpsp, phy_addr, 0, &temp); + return 1000; + } + else if((temp & 0x0C00) == 0x0400) { + XEmacPs_PhyRead(xemacpsp, phy_addr, 0, &temp); + return 100; + } + else if((temp & 0x0C00) == 0x0000) { + XEmacPs_PhyRead(xemacpsp, phy_addr, 0, &temp); + return 10; + } else { + xil_printf("get_IEEE_phy_speed(): Invalid speed bit value, Deafulting to Speed = 10 Mbps\n"); + XEmacPs_PhyRead(xemacpsp, phy_addr, 0, &temp); + XEmacPs_PhyWrite(xemacpsp, phy_addr, 0, 0x0100); + return 10; + } +#else + if ( ((partner_capabilities >> 14) & 3) == 2)/* 1000Mbps */ + return 1000; + else if ( ((partner_capabilities >> 14) & 3) == 1)/* 100Mbps */ + return 100; + else /* 10Mbps */ + return 10; +#endif +} +#endif + +unsigned configure_IEEE_phy_speed(XEmacPs *xemacpsp, unsigned speed) +{ + u16 control; + u32 phy_addr = detect_phy(xemacpsp); + + XEmacPs_PhyWrite(xemacpsp,phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 2); + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, &control); + control |= IEEE_RGMII_TXRX_CLOCK_DELAYED_MASK; + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, control); + + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0); + + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &control); + control |= IEEE_ASYMMETRIC_PAUSE_MASK; + control |= IEEE_PAUSE_MASK; + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, control); + + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control); + control &= ~IEEE_CTRL_LINKSPEED_1000M; + control &= ~IEEE_CTRL_LINKSPEED_100M; + control &= ~IEEE_CTRL_LINKSPEED_10M; + + if (speed == 1000) { + control |= IEEE_CTRL_LINKSPEED_1000M; + } + + else if (speed == 100) { + control |= IEEE_CTRL_LINKSPEED_100M; + /* Dont advertise PHY speed of 1000 Mbps */ + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, 0); + /* Dont advertise PHY speed of 10 Mbps */ + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, + ADVERTISE_100); + } + + else if (speed == 10) { + control |= IEEE_CTRL_LINKSPEED_10M; + /* Dont advertise PHY speed of 1000 Mbps */ + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, + 0); + /* Dont advertise PHY speed of 100 Mbps */ + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, + ADVERTISE_10); + } + + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, + control | IEEE_CTRL_RESET_MASK); + { + volatile int wait; + for (wait=0; wait < 100000; wait++); + } + return 0; +} + +static void SetUpSLCRDivisors(int mac_baseaddr, int speed) +{ + volatile u32 slcrBaseAddress; +#ifndef PEEP + u32 SlcrDiv0; + u32 SlcrDiv1=0; + u32 SlcrTxClkCntrl; +#endif + + *(volatile unsigned int *)(SLCR_UNLOCK_ADDR) = SLCR_UNLOCK_KEY_VALUE; + + if ((unsigned long)mac_baseaddr == EMAC0_BASE_ADDRESS) { + slcrBaseAddress = SLCR_GEM0_CLK_CTRL_ADDR; + } else { + slcrBaseAddress = SLCR_GEM1_CLK_CTRL_ADDR; + } +#ifdef PEEP + if (speed == 1000) { + *(volatile unsigned int *)(slcrBaseAddress) = + SLCR_GEM_1G_CLK_CTRL_VALUE; + } else if (speed == 100) { + *(volatile unsigned int *)(slcrBaseAddress) = + SLCR_GEM_100M_CLK_CTRL_VALUE; + } else { + *(volatile unsigned int *)(slcrBaseAddress) = + SLCR_GEM_10M_CLK_CTRL_VALUE; + } +#else + if (speed == 1000) { + if ((unsigned long)mac_baseaddr == EMAC0_BASE_ADDRESS) { +#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 + SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0; + SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1; +#endif + } else { +#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0 + SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0; + SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1; +#endif + } + } else if (speed == 100) { + if ((unsigned long)mac_baseaddr == EMAC0_BASE_ADDRESS) { +#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 + SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0; + SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1; +#endif + } else { +#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0 + SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0; + SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV1; +#endif + } + } else { + if ((unsigned long)mac_baseaddr == EMAC0_BASE_ADDRESS) { +#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 + SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0; + SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1; +#endif + } else { +#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0 + SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0; + SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV1; +#endif + } + } + SlcrTxClkCntrl = *(volatile unsigned int *)(slcrBaseAddress); + SlcrTxClkCntrl &= EMACPS_SLCR_DIV_MASK; + SlcrTxClkCntrl |= (SlcrDiv1 << 20); + SlcrTxClkCntrl |= (SlcrDiv0 << 8); + *(volatile unsigned int *)(slcrBaseAddress) = SlcrTxClkCntrl; +#endif + *(volatile unsigned int *)(SLCR_LOCK_ADDR) = SLCR_LOCK_KEY_VALUE; + return; +} + + +unsigned link_speed; +unsigned Phy_Setup (XEmacPs *xemacpsp) +{ + unsigned long conv_present = 0; + unsigned long convspeeddupsetting = 0; + unsigned long convphyaddr = 0; + +#ifdef XPAR_GMII2RGMIICON_0N_ETH0_ADDR + convphyaddr = XPAR_GMII2RGMIICON_0N_ETH0_ADDR; + conv_present = 1; +#else +#ifdef XPAR_GMII2RGMIICON_0N_ETH1_ADDR + convphyaddr = XPAR_GMII2RGMIICON_0N_ETH1_ADDR; + conv_present = 1; +#endif +#endif + +#ifdef ipconfigNIC_LINKSPEED_AUTODETECT + link_speed = get_IEEE_phy_speed(xemacpsp); + if (link_speed == 1000) { + SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,1000); + convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED1000_FD; + } else if (link_speed == 100) { + SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,100); + convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED100_FD; + } else { + SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,10); + convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED10_FD; + } +#elif defined(ipconfigNIC_LINKSPEED1000) + SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,1000); + link_speed = 1000; + configure_IEEE_phy_speed(xemacpsp, link_speed); + convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED1000_FD; + sleep(1); +#elif defined(ipconfigNIC_LINKSPEED100) + SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,100); + link_speed = 100; + configure_IEEE_phy_speed(xemacpsp, link_speed); + convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED100_FD; + sleep(1); +#elif defined(ipconfigNIC_LINKSPEED10) + SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,10); + link_speed = 10; + configure_IEEE_phy_speed(xemacpsp, link_speed); + convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED10_FD; + sleep(1); +#endif + if (conv_present) { + XEmacPs_PhyWrite(xemacpsp, convphyaddr, + XEMACPS_GMII2RGMII_REG_NUM, convspeeddupsetting); + } + + xil_printf("link speed: %d\n", link_speed); + return link_speed; +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_topology.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_topology.h new file mode 100644 index 0000000..bb51783 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/Zynq/x_topology.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2007-2013 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#ifndef __XTOPOLOGY_H_ +#define __XTOPOLOGY_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum xemac_types { xemac_type_unknown = -1, xemac_type_xps_emaclite, xemac_type_xps_ll_temac, xemac_type_axi_ethernet, xemac_type_emacps }; + +struct xtopology_t { + unsigned emac_baseaddr; + enum xemac_types emac_type; + unsigned intc_baseaddr; + unsigned intc_emac_intr; /* valid only for xemac_type_xps_emaclite */ + unsigned scugic_baseaddr; /* valid only for Zynq */ + unsigned scugic_emac_intr; /* valid only for GEM */ +}; + +extern int x_topology_n_emacs; +extern struct xtopology_t x_topology[]; + +int x_topology_find_index(unsigned base); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/include/phyHandling.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/include/phyHandling.h new file mode 100644 index 0000000..4262e25 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/include/phyHandling.h @@ -0,0 +1,118 @@ +/* + * Handling of Ethernet PHY's + * PHY's communicate with an EMAC either through + * a Media-Independent Interface (MII), or a Reduced Media-Independent Interface (RMII). + * The EMAC can poll for PHY ports on 32 different addresses. Each of the PHY ports + * shall be treated independently. + * + */ + +#ifndef PHYHANDLING_H + +#define PHYHANDLING_H + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifndef ipconfigPHY_MAX_PORTS + /* There can be at most 32 PHY ports, but in most cases there are 4 or less. */ + #define ipconfigPHY_MAX_PORTS 4 +#endif + +/* A generic user-provided function that reads from the PHY-port at 'xAddress'( 0-based ). A 16-bit value shall be stored in + '*pusValue'. xRegister is the register number ( 0 .. 31 ). In fact all PHY registers are 16-bit. + Return non-zero in case the action failed. */ +typedef BaseType_t ( *xApplicationPhyReadHook_t )( BaseType_t xAddress, BaseType_t xRegister, uint32_t *pulValue ); + +/* A generic user-provided function that writes 'usValue' to the + PHY-port at 'xAddress' ( 0-based ). xRegister is the register number ( 0 .. 31 ). + Return non-zero in case the action failed. */ +typedef BaseType_t ( *xApplicationPhyWriteHook_t )( BaseType_t xAddress, BaseType_t xRegister, uint32_t ulValue ); + +typedef struct xPhyProperties +{ + uint8_t ucSpeed; + uint8_t ucMDI_X; /* MDI-X : Medium Dependent Interface - Crossover */ + uint8_t ucDuplex; + uint8_t ucSpare; +} PhyProperties_t; + +typedef struct xEthernetPhy +{ + xApplicationPhyReadHook_t fnPhyRead; + xApplicationPhyWriteHook_t fnPhyWrite; + uint32_t ulPhyIDs[ ipconfigPHY_MAX_PORTS ]; + uint8_t ucPhyIndexes[ ipconfigPHY_MAX_PORTS ]; + TimeOut_t xLinkStatusTimer; + TickType_t xLinkStatusRemaining; + BaseType_t xPortCount; + uint32_t ulBCRValue; + uint32_t ulACRValue; + uint32_t ulLinkStatusMask; + PhyProperties_t xPhyPreferences; + PhyProperties_t xPhyProperties; +} EthernetPhy_t; + +/* Some defines used internally here to indicate preferences about speed, MDIX +(wired direct or crossed), and duplex (half or full). */ + +/* Values for PhyProperties_t::ucSpeed : */ +#define PHY_SPEED_10 1 +#define PHY_SPEED_100 2 +#define PHY_SPEED_AUTO 3 + +/* Values for PhyProperties_t::ucMDI_X : */ +#define PHY_MDIX_DIRECT 1 +#define PHY_MDIX_CROSSED 2 +#define PHY_MDIX_AUTO 3 + +/* Values for PhyProperties_t::ucDuplex : */ +#define PHY_DUPLEX_HALF 1 +#define PHY_DUPLEX_FULL 2 +#define PHY_DUPLEX_AUTO 3 + +/* ID's of supported PHY's : */ +#define PHY_ID_LAN8742A 0x0007c130 +#define PHY_ID_LAN8720 0x0007c0f0 + +#define PHY_ID_KSZ8041 0x000010A1 +#define PHY_ID_KSZ8051 0x000010A1 +#define PHY_ID_KSZ8081 0x000010A1 + +#define PHY_ID_KSZ8863 0x00221430 + +#define PHY_ID_DP83848I 0x20005C90 + + +/* Initialise the struct and assign a PHY-read and -write function. */ +void vPhyInitialise( EthernetPhy_t *pxPhyObject, xApplicationPhyReadHook_t fnPhyRead, xApplicationPhyWriteHook_t fnPhyWrite ); + +/* Discover all PHY's connected by polling 32 indexes ( zero-based ) */ +BaseType_t xPhyDiscover( EthernetPhy_t *pxPhyObject ); + +/* Send a reset commando to the connected PHY ports and send configuration. */ +BaseType_t xPhyConfigure( EthernetPhy_t *pxPhyObject, const PhyProperties_t *pxPhyProperties ); + +/* Give a commando to start auto negotiation on a set of PHY port's. */ +BaseType_t xPhyStartAutoNegotiation( EthernetPhy_t *pxPhyObject, uint32_t ulPhyMask ); + +/* Do not use auto negotiation but use predefined values from 'pxPhyObject->xPhyPreferences'. */ +BaseType_t xPhyFixedValue( EthernetPhy_t *pxPhyObject, uint32_t ulPhyMask ); + +/* Check the current Link Status. +'xHadReception' : make this true if a packet has been received since the +last call to this function. */ +BaseType_t xPhyCheckLinkStatus( EthernetPhy_t *pxPhyObject, BaseType_t xHadReception ); + +static __inline uint32_t xPhyGetMask( EthernetPhy_t *pxPhyObject ) +{ + return ( ( ( uint32_t ) 1u ) << pxPhyObject-> xPortCount ) - 1; +} + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ksz8851snl/NetworkInterface.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ksz8851snl/NetworkInterface.c new file mode 100644 index 0000000..544e5ba --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ksz8851snl/NetworkInterface.c @@ -0,0 +1,1272 @@ +/* +FreeRTOS+TCP V2.0.11 +Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + http://aws.amazon.com/freertos + http://www.FreeRTOS.org +*/ + +/* Standard includes. */ +#include +#include +#include +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* FreeRTOS+TCP includes. */ +#include "FreeRTOS_IP.h" +#include "FreeRTOS_Sockets.h" +#include "FreeRTOS_IP_Private.h" +#include "NetworkBufferManagement.h" +#include "NetworkInterface.h" + +#include "sam4e_xplained_pro.h" +#include "hr_gettime.h" +#include "conf_eth.h" +#include "ksz8851snl.h" +#include "ksz8851snl_reg.h" + +/* Some files from the Atmel Software Framework */ +#include +#include +#include + +/* + Sending a packet: + + 1) Called by UP-task, add buffer to the TX-list: + xNetworkInterfaceOutput() + tx_buffers[ us_tx_head ] = pxNetworkBuffer; + tx_busy[ us_tx_head ] = pdTRUE; + us_tx_head++; + + 2) Called by EMAC-Task: start SPI transfer + ksz8851snl_update() + if( ul_spi_pdc_status == SPI_PDC_IDLE ) + { + if( ( tx_busy[ us_tx_tail ] != pdFALSE ) && + ( us_pending_frame == 0 ) && + ( ul_had_intn_interrupt == 0 ) ) + { + // disable all interrupts. + ksz8851_reg_write( REG_INT_MASK, 0 ); + Bring KSZ8851SNL_CSN_GPIO low + ksz8851_fifo_write( pxNetworkBuffer->pucEthernetBuffer, xLength, xLength ); + ul_spi_pdc_status = SPI_PDC_TX_START; + tx_cur_buffer = pxNetworkBuffer; + } + } + 3) Wait for SPI RXBUFF interrupt + SPI_Handler() + if( ul_spi_pdc_status == SPI_PDC_TX_START ) + { + if( SPI_Status & SPI_SR_RXBUFF ) + { + ul_spi_pdc_status = SPI_PDC_TX_COMPLETE; + } + } + + 4) Called by EMAC-Task: finish SPI transfer + ksz8851snl_update() + if( ul_spi_pdc_status == SPI_PDC_TX_COMPLETE ) + { + ul_spi_pdc_status = SPI_PDC_IDLE; + Bring KSZ8851SNL_CSN_GPIO high + // TX step12: disable TXQ write access. + ksz8851_reg_clrbits( REG_RXQ_CMD, RXQ_START ); + // TX step12.1: enqueue frame in TXQ. + ksz8851_reg_setbits( REG_TXQ_CMD, TXQ_ENQUEUE ); + + // RX step13: enable INT_RX flag. + ksz8851_reg_write( REG_INT_MASK, INT_RX ); + + // Buffer sent, free the corresponding buffer and mark descriptor as owned by software. + vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ); + + tx_buffers[ us_tx_tail ] = NULL; + tx_busy[ us_tx_tail ] = pdFALSE; + us_tx_tail++ + } + + Receiving a packet: + + 1) Wait for a INTN interrupt + INTN_Handler() + ul_had_intn_interrupt = 1 + vTaskNotifyGiveFromISR(); // Wake up the EMAC task + + 2) Called by EMAC-Task: check for new fragments and start SPI transfer + ksz8851snl_update() + if( ul_spi_pdc_status == SPI_PDC_IDLE ) + { + if( ( ul_had_intn_interrupt != 0 ) || ( us_pending_frame > 0 ) ) + { + if( us_pending_frame == 0 ) + { + us_pending_frame = ksz8851_reg_read(REG_RX_FRAME_CNT_THRES) >> 8; + if( us_pending_frame == 0 ) + { + break; + } + } + // RX step2: disable all interrupts. + ksz8851_reg_write( REG_INT_MASK, 0 ); + Check if there is a valid packet: REG_RX_FHR_STATUS + Read the length of the next fragment: REG_RX_FHR_BYTE_CNT + ul_spi_pdc_status = SPI_PDC_RX_START; + gpio_set_pin_low(KSZ8851SNL_CSN_GPIO); + // Start SPI data transfer + ksz8851_fifo_read( pxNetworkBuffer->pucEthernetBuffer, xReadLength ); + } + } + + 3) Wait for SPI RXBUFF interrupt + SPI_Handler() + if( ul_spi_pdc_status == SPI_PDC_RX_START: + { + if( ( ulCurrentSPIStatus & SPI_SR_RXBUFF ) != 0 ) + { + // Transfer complete, disable SPI RXBUFF interrupt. + spi_disable_interrupt( KSZ8851SNL_SPI, SPI_IDR_RXBUFF ); + + ul_spi_pdc_status = SPI_PDC_RX_COMPLETE; + } + } + } + + 4) Finish SPI transfer + ksz8851snl_update() + if( ul_spi_pdc_status == SPI_PDC_RX_COMPLETE ) + { + ul_spi_pdc_status = SPI_PDC_IDLE; + Bring KSZ8851SNL_CSN_GPIO high + // RX step21: end RXQ read access. + ksz8851_reg_clrbits(REG_RXQ_CMD, RXQ_START); + // RX step22-23: update frame count to be read. + us_pending_frame-- + // RX step24: enable INT_RX flag if transfer complete. + if( us_pending_frame == 0 ) + { + // Allow more RX interrupts. + ksz8851_reg_write( REG_INT_MASK, INT_RX ); + } + + // Mark descriptor ready to be read. + rx_ready[ rxHead ] = pdTRUE; + rxHead++ + } +*/ + +#define PHY_REG_00_BMCR 0x00 // Basic mode control register +#define PHY_REG_01_BMSR 0x01 // Basic mode status register +#define PHY_REG_02_PHYSID1 0x02 // PHYS ID 1 +#define PHY_REG_03_PHYSID2 0x03 // PHYS ID 2 +#define PHY_REG_04_ADVERTISE 0x04 // Advertisement control reg +#define PHY_REG_05_LPA 0x05 // Link partner ability reg +#define PHY_REG_06_ANER 0x06 // 6 RW Auto-Negotiation Expansion Register +#define PHY_REG_07_ANNPTR 0x07 // 7 RW Auto-Negotiation Next Page TX +#define PHY_REG_08_RESERVED0 0x08 // 0x08..0x0Fh 8-15 RW RESERVED + +#define BMSR_LINK_STATUS 0x0004 //!< Link status + +#ifndef PHY_LS_HIGH_CHECK_TIME_MS + /* Check if the LinkSStatus in the PHY is still high after 15 seconds of not + receiving packets. */ + #define PHY_LS_HIGH_CHECK_TIME_MS 15000 +#endif + +#ifndef PHY_LS_LOW_CHECK_TIME_MS + /* Check if the LinkSStatus in the PHY is still low every second. */ + #define PHY_LS_LOW_CHECK_TIME_MS 1000 +#endif + +/* Interrupt events to process. Currently only the Rx event is processed +although code for other events is included to allow for possible future +expansion. */ +#define EMAC_IF_RX_EVENT 1UL +#define EMAC_IF_TX_EVENT 2UL +#define EMAC_IF_ERR_EVENT 4UL +#define EMAC_IF_ALL_EVENT ( EMAC_IF_RX_EVENT | EMAC_IF_TX_EVENT | EMAC_IF_ERR_EVENT ) + +#define ETHERNET_CONF_PHY_ADDR BOARD_GMAC_PHY_ADDR + +#ifdef ipconfigHAS_TX_CRC_OFFLOADING + #undef ipconfigHAS_TX_CRC_OFFLOADING +#endif +/* Override this define because the KSZ8851 is programmed to set all outgoing CRC's */ +#define ipconfigHAS_TX_CRC_OFFLOADING 1 + +#ifndef EMAC_MAX_BLOCK_TIME_MS + #define EMAC_MAX_BLOCK_TIME_MS 100ul +#endif + +/* Default the size of the stack used by the EMAC deferred handler task to 4x +the size of the stack used by the idle task - but allow this to be overridden in +FreeRTOSConfig.h as configMINIMAL_STACK_SIZE is a user definable constant. */ +#ifndef configEMAC_TASK_STACK_SIZE + #define configEMAC_TASK_STACK_SIZE ( 6 * configMINIMAL_STACK_SIZE ) +#endif + +#define SPI_PDC_IDLE 0 +#define SPI_PDC_RX_START 1 +#define SPI_PDC_TX_ERROR 2 +#define SPI_PDC_RX_COMPLETE 3 +#define SPI_PDC_TX_START 4 +#define SPI_PDC_RX_ERROR 5 +#define SPI_PDC_TX_COMPLETE 6 + +/** + * ksz8851snl driver structure. + */ +typedef struct { + /** Set to 1 when owner is software (ready to read), 0 for Micrel. */ + uint32_t rx_ready[MICREL_RX_BUFFERS]; + /** Set to 1 when owner is Micrel, 0 for software. */ + uint32_t tx_busy[MICREL_TX_BUFFERS]; + /** RX NetworkBufferDescriptor_t pointer list */ + NetworkBufferDescriptor_t *rx_buffers[MICREL_RX_BUFFERS]; + /** TX NetworkBufferDescriptor_t pointer list */ + NetworkBufferDescriptor_t *tx_buffers[MICREL_TX_BUFFERS]; + NetworkBufferDescriptor_t *tx_cur_buffer; + + /** Circular buffer head pointer for packet received. */ + uint32_t us_rx_head; + /** Circular buffer tail pointer for packet to be read. */ + uint32_t us_rx_tail; + /** Circular buffer head pointer by upper layer (buffer to be sent). */ + uint32_t us_tx_head; + /** Circular buffer tail pointer incremented by handlers (buffer sent). */ + uint32_t us_tx_tail; + + uint32_t ul_total_tx; + uint32_t ul_total_rx; + uint32_t tx_space; + + /** Still experimental: hash table to allow certain multicast addresses. */ + uint16_t pusHashTable[ 4 ]; + + /* ul_spi_pdc_status has "SPI_PDC_xxx" values. */ + volatile uint32_t ul_spi_pdc_status; + + /* ul_had_intn_interrupt becomes true within the INTN interrupt. */ + volatile uint32_t ul_had_intn_interrupt; + + uint16_t us_pending_frame; +} xKSZ8851_Device_t; + +/* SPI PDC register base. +Declared in ASF\sam\components\ksz8851snl\ksz8851snl.c */ +extern Pdc *g_p_spi_pdc; + +/* Temporary buffer for PDC reception. +declared in ASF\sam\components\ksz8851snl\ksz8851snl.c */ +extern uint8_t tmpbuf[1536]; + +COMPILER_ALIGNED(8) +static xKSZ8851_Device_t xMicrelDevice; + +static TaskHandle_t xTransmitHandle; + +/*-----------------------------------------------------------*/ + +/* + * Wait a fixed time for the link status to indicate the network is up. + */ +static BaseType_t xGMACWaitLS( TickType_t xMaxTime ); + +/* + * A deferred interrupt handler task that processes GMAC interrupts. + */ +static void prvEMACHandlerTask( void *pvParameters ); + +/* + * Try to obtain an Rx packet from the hardware. + */ +static uint32_t prvEMACRxPoll( void ); + +static inline unsigned long ulReadMDIO( unsigned uAddress ); + +static void ksz8851snl_low_level_init( void ); + +static NetworkBufferDescriptor_t *ksz8851snl_low_level_input( void ); + +/*-----------------------------------------------------------*/ + +/* Bit map of outstanding ETH interrupt events for processing. Currently only +the Rx interrupt is handled, although code is included for other events to +enable future expansion. */ +static volatile uint32_t ulISREvents; + +/* A copy of PHY register 1: 'PHY_REG_01_BMSR' */ +static uint32_t ulPHYLinkStatus = 0; +static volatile BaseType_t xGMACSwitchRequired; + +static void ksz8851snl_update( void ); + +static void ksz8851snl_rx_init( void ); + +static void ksz8851snl_tx_init( void ); + +/* Holds the handle of the task used as a deferred interrupt processor. The +handle is used so direct notifications can be sent to the task for all EMAC/DMA +related interrupts. */ +TaskHandle_t xEMACTaskHandle = NULL; + + +/*-----------------------------------------------------------*/ + +BaseType_t xNetworkInterfaceInitialise( void ) +{ +const TickType_t x5_Seconds = 5000UL; + + if( xEMACTaskHandle == NULL ) + { + ksz8851snl_low_level_init(); + + /* Wait at most 5 seconds for a Link Status in the PHY. */ + xGMACWaitLS( pdMS_TO_TICKS( x5_Seconds ) ); + + /* The handler task is created at the highest possible priority to + ensure the interrupt handler can return directly to it. */ + xTaskCreate( prvEMACHandlerTask, "KSZ8851", configEMAC_TASK_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, &xEMACTaskHandle ); + configASSERT( xEMACTaskHandle ); + } + + /* When returning non-zero, the stack will become active and + start DHCP (in configured) */ + ulPHYLinkStatus = ulReadMDIO( PHY_REG_01_BMSR ); + + return ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != 0; +} +/*-----------------------------------------------------------*/ + +BaseType_t xGetPhyLinkStatus( void ) +{ +BaseType_t xResult; + + /* This function returns true if the Link Status in the PHY is high. */ + if( ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != 0 ) + { + xResult = pdTRUE; + } + else + { + xResult = pdFALSE; + } + + return xResult; +} +/*-----------------------------------------------------------*/ + +BaseType_t xNetworkInterfaceOutput( NetworkBufferDescriptor_t * const pxNetworkBuffer, BaseType_t bReleaseAfterSend ) +{ +BaseType_t xResult = pdFALSE; +int txHead = xMicrelDevice.us_tx_head; + + /* Make sure the next descriptor is free. */ + if( xMicrelDevice.tx_busy[ txHead ] != pdFALSE ) + { + /* All TX buffers busy. */ + } + else if( ( ulPHYLinkStatus & BMSR_LINK_STATUS ) == 0 ) + { + /* Output: LS low. */ + } + else + { + /* Pass the packet. */ + xMicrelDevice.tx_buffers[ txHead ] = pxNetworkBuffer; + /* The descriptor is now owned by Micrel. */ + xMicrelDevice.tx_busy[ txHead ] = pdTRUE; + + /* Move the head pointer. */ + if( ++txHead == MICREL_TX_BUFFERS ) + { + txHead = 0; + } + xMicrelDevice.us_tx_head = txHead; + if( xEMACTaskHandle != NULL ) + { + xTaskNotifyGive( xEMACTaskHandle ); + } + + #if( ipconfigZERO_COPY_TX_DRIVER != 1 ) + #warning Please ipconfigZERO_COPY_TX_DRIVER as 1 + #endif + configASSERT( bReleaseAfterSend != pdFALSE ); + xResult = pdTRUE; + } + if( ( xResult == pdFALSE ) && ( bReleaseAfterSend != pdFALSE ) ) + { + vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ); + } + return xResult; +} +/*-----------------------------------------------------------*/ + +/* This Micrel has numbered it's PHY registers in a different way. +Translate the register index. */ +static int ks8851_phy_reg( int reg ) +{ + switch (reg) { + case PHY_REG_00_BMCR: + return REG_PHY_CNTL; // P1MBCR; + case PHY_REG_01_BMSR: + return REG_PHY_STATUS; + case PHY_REG_02_PHYSID1: + return REG_PHY_ID_LOW; + case PHY_REG_03_PHYSID2: + return REG_PHY_ID_HIGH; + case PHY_REG_04_ADVERTISE: + return REG_PHY_AUTO_NEGOTIATION; + case PHY_REG_05_LPA: + return REG_PHY_REMOTE_CAPABILITY; + } + + return 0x0; +} +/*-----------------------------------------------------------*/ + +static inline unsigned long ulReadMDIO( unsigned uAddress ) +{ +uint16_t usPHYStatus; +int ks8851_reg = ks8851_phy_reg( uAddress ); + + if( ks8851_reg != 0 ) + { + usPHYStatus = ksz8851_reg_read( ks8851_reg ); + } + else + { + /* Other addresses not yet implemented. */ + usPHYStatus = 0; + } + return usPHYStatus; +} +/*-----------------------------------------------------------*/ + +static BaseType_t xGMACWaitLS( TickType_t xMaxTime ) +{ +TickType_t xStartTime = xTaskGetTickCount(); +TickType_t xEndTime; +BaseType_t xReturn; +const TickType_t xShortTime = pdMS_TO_TICKS( 100UL ); +const uint32_t ulHz_Per_MHz = 1000000UL; + + for( ;; ) + { + xEndTime = xTaskGetTickCount(); + + if( ( xEndTime - xStartTime ) > xMaxTime ) + { + /* Wated more than xMaxTime, return. */ + xReturn = pdFALSE; + break; + } + + /* Check the link status again. */ + ulPHYLinkStatus = ulReadMDIO( PHY_REG_01_BMSR ); + + if( ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != 0 ) + { + /* Link is up - return. */ + xReturn = pdTRUE; + break; + } + + /* Link is down - wait in the Blocked state for a short while (to allow + other tasks to execute) before checking again. */ + vTaskDelay( xShortTime ); + } + + FreeRTOS_printf( ( "xGMACWaitLS: %ld freq %lu Mz\n", + xReturn, + sysclk_get_cpu_hz() / ulHz_Per_MHz ) ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static void vPioSetPinHigh(uint32_t ul_pin) +{ + Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))); + // Value to be driven on the I/O line: 1. + p_pio->PIO_SODR = 1 << (ul_pin & 0x1F); +} + +/** + * \brief Handler for SPI interrupt. + */ +void SPI_Handler(void) +{ +BaseType_t xDoWakeup = pdFALSE; +BaseType_t xKSZTaskWoken = pdFALSE; +uint32_t ulCurrentSPIStatus; +uint32_t ulEnabledSPIStatus; + + ulCurrentSPIStatus = spi_read_status( KSZ8851SNL_SPI ); + ulEnabledSPIStatus = spi_read_interrupt_mask( KSZ8851SNL_SPI ); + ulCurrentSPIStatus &= ulEnabledSPIStatus; + spi_disable_interrupt( KSZ8851SNL_SPI, ulCurrentSPIStatus ); + + + switch( xMicrelDevice.ul_spi_pdc_status ) + { + case SPI_PDC_RX_START: + { + if( ( ulCurrentSPIStatus & SPI_SR_OVRES ) != 0 ) + { + pdc_disable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS); + xMicrelDevice.ul_spi_pdc_status = SPI_PDC_RX_ERROR; + xDoWakeup = pdTRUE; + } + else + { + if( ( ulCurrentSPIStatus & SPI_SR_RXBUFF ) != 0 ) + { + xMicrelDevice.ul_spi_pdc_status = SPI_PDC_RX_COMPLETE; + xDoWakeup = pdTRUE; + } + } + } + break; + + case SPI_PDC_TX_START: + { + /* Middle of TX. */ + if( ( ulCurrentSPIStatus & SPI_SR_OVRES ) != 0 ) + { + pdc_disable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS); + xMicrelDevice.ul_spi_pdc_status = SPI_PDC_TX_ERROR; + xDoWakeup = pdTRUE; + } + else + { + if( ( ulCurrentSPIStatus & SPI_SR_ENDRX ) != 0 ) + { + /* Enable RX complete interrupt. */ + spi_enable_interrupt( KSZ8851SNL_SPI, SPI_IER_RXBUFF ); + } + /* End of TX. */ + if( ( ulCurrentSPIStatus & SPI_END_OF_TX ) != 0 ) + { + xMicrelDevice.ul_spi_pdc_status = SPI_PDC_TX_COMPLETE; + xDoWakeup = pdTRUE; + } + } + } + break; + } /* switch( xMicrelDevice.ul_spi_pdc_status ) */ + + if( xDoWakeup != pdFALSE ) + { + if( xEMACTaskHandle != NULL ) + { + vTaskNotifyGiveFromISR( xEMACTaskHandle, ( BaseType_t * ) &xKSZTaskWoken ); + } + } + else + { + } + portEND_SWITCHING_ISR( xKSZTaskWoken ); +} +/*-----------------------------------------------------------*/ + +static void INTN_Handler(uint32_t id, uint32_t mask) +{ +BaseType_t xKSZTaskWoken = pdFALSE; + + if( ( id == INTN_ID ) && + ( mask == INTN_PIN_MSK ) ) + { + /* Clear the PIO interrupt flags. */ + pio_get_interrupt_status( INTN_PIO ); + + /* Set the INTN flag. */ + xMicrelDevice.ul_had_intn_interrupt++; + if( xEMACTaskHandle != NULL ) + { + vTaskNotifyGiveFromISR( xEMACTaskHandle, &( xKSZTaskWoken ) ); + } + } + portEND_SWITCHING_ISR( xKSZTaskWoken ); +} +/*-----------------------------------------------------------*/ + +/** + * \brief Populate the RX descriptor ring buffers with pbufs. + * + * \param p_ksz8851snl_dev Pointer to driver data structure. + */ +static void ksz8851snl_rx_populate_queue( void ) +{ + uint32_t ul_index = 0; + NetworkBufferDescriptor_t *pxNetworkBuffer; + + /* Set up the RX descriptors */ + for (ul_index = 0; ul_index < MICREL_RX_BUFFERS; ul_index++) { + if( xMicrelDevice.rx_buffers[ ul_index ] == NULL ) + { + /* Allocate a new NetworkBufferDescriptor_t with the maximum size. */ + pxNetworkBuffer = pxGetNetworkBufferWithDescriptor( ipconfigNETWORK_MTU + 36, 100 ); + if( pxNetworkBuffer == NULL ) + { + FreeRTOS_printf( ( "ksz8851snl_rx_populate_queue: NetworkBufferDescriptor_t allocation failure\n" ) ); + configASSERT( 1 == 2 ); + } + + /* Make sure lwIP is well configured so one NetworkBufferDescriptor_t can contain the maximum packet size. */ + //LWIP_ASSERT("ksz8851snl_rx_populate_queue: NetworkBufferDescriptor_t size too small!", pbuf_clen(pxNetworkBuffer) <= 1); + + /* Save NetworkBufferDescriptor_t pointer to be sent to lwIP upper layer. */ + xMicrelDevice.rx_buffers[ ul_index ] = pxNetworkBuffer; + /* Pass it to Micrel for reception. */ + xMicrelDevice.rx_ready[ ul_index ] = pdFALSE; + } + } +} + +unsigned tx_space, wait_tx_space, tx_status, fhr_status; +unsigned rx_debug = 0; +/** + * \brief Update Micrel state machine and perform required actions. + * + * \param netif the lwIP network interface structure for this ethernetif. + */ +static void ksz8851snl_update() +{ + uint16_t txmir = 0; + +/* Check for free PDC. */ + switch( xMicrelDevice.ul_spi_pdc_status ) + { + case SPI_PDC_TX_ERROR: + { + uint32_t ulValue; + // /* TX step11: end TX transfer. */ + gpio_set_pin_high( KSZ8851SNL_CSN_GPIO ); + + vTaskDelay( 2 ); gpio_set_pin_low( KSZ8851SNL_CSN_GPIO ); + vTaskDelay( 1 ); gpio_set_pin_high( KSZ8851SNL_CSN_GPIO ); + vTaskDelay( 1 ); + + /* Disable asynchronous transfer mode. */ + xMicrelDevice.ul_spi_pdc_status = SPI_PDC_IDLE; + + /* TX step12: disable TXQ write access. */ + ksz8851_reg_clrbits( REG_RXQ_CMD, RXQ_START ); + + ulValue = ksz8851snl_reset_tx(); + + xMicrelDevice.tx_space = ksz8851_reg_read( REG_TX_MEM_INFO ) & TX_MEM_AVAILABLE_MASK; + + FreeRTOS_printf( ("SPI_PDC_TX_ERROR %02X\n", ulValue ) ); + } + break; + + case SPI_PDC_RX_ERROR: + { + uint32_t ulValue; + /* TX step11: end TX transfer. */ + gpio_set_pin_high( KSZ8851SNL_CSN_GPIO ); + + vTaskDelay( 2 ); gpio_set_pin_low( KSZ8851SNL_CSN_GPIO ); + vTaskDelay( 1 ); gpio_set_pin_high( KSZ8851SNL_CSN_GPIO ); + vTaskDelay( 1 ); + + /* Disable asynchronous transfer mode. */ + xMicrelDevice.ul_spi_pdc_status = SPI_PDC_IDLE; + + /* TX step12: disable TXQ write access. */ + ksz8851_reg_clrbits( REG_RXQ_CMD, RXQ_START ); + + //ulValue = ksz8851snl_reset_rx(); + ulValue = ksz8851snl_reinit(); + + xGMACWaitLS( pdMS_TO_TICKS( 5000UL ) ); + + FreeRTOS_printf( ("SPI_PDC_RX_ERROR %02X\n", ulValue ) ); + } + break; + } + switch( xMicrelDevice.ul_spi_pdc_status ) + { + case SPI_PDC_IDLE: + { + int txTail = xMicrelDevice.us_tx_tail; + + /* + * ========================== Handle RX ========================== + */ + if( ( xMicrelDevice.ul_had_intn_interrupt != 0 ) || ( xMicrelDevice.us_pending_frame > 0 ) ) + { + int rxHead = xMicrelDevice.us_rx_head; + NetworkBufferDescriptor_t *pxNetworkBuffer; +#warning try + xMicrelDevice.ul_had_intn_interrupt = 0; + + if( xMicrelDevice.us_pending_frame == 0 ) + { + uint16_t int_status; + /* RX step1: read interrupt status for INT_RX flag. */ + int_status = ksz8851_reg_read( REG_INT_STATUS ); + + + /* RX step2: disable all interrupts. */ + ksz8851_reg_write( REG_INT_MASK, 0 ); + + /* RX step3: clear INT_RX flag. */ + ksz8851_reg_setbits( REG_INT_STATUS, INT_RX ); + + /* RX step4-5: check for received frames. */ + xMicrelDevice.us_pending_frame = ksz8851_reg_read(REG_RX_FRAME_CNT_THRES) >> 8; + if( xMicrelDevice.us_pending_frame == 0 ) + { + /* RX step24: enable INT_RX flag. */ + ksz8851_reg_write(REG_INT_MASK, INT_RX); + return; + } + } +#warning try + xMicrelDevice.ul_had_intn_interrupt = 0; + + /* Now xMicrelDevice.us_pending_frame != 0 */ + + /* Don't break Micrel state machine, wait for a free descriptor first! */ + if( xMicrelDevice.rx_ready[ rxHead ] != pdFALSE ) + { + FreeRTOS_printf( ( "ksz8851snl_update: out of free descriptor! [tail=%u head=%u]\n", + xMicrelDevice.us_rx_tail, rxHead ) ); + return; + } + pxNetworkBuffer = xMicrelDevice.rx_buffers[ rxHead ]; + + if( pxNetworkBuffer == NULL ) + { + ksz8851snl_rx_populate_queue(); + FreeRTOS_printf( ( "ksz8851snl_update: no buffer set [head=%u]\n", rxHead ) ); + return; + } + + /* RX step6: get RX packet status. */ + fhr_status = ksz8851_reg_read( REG_RX_FHR_STATUS ); + if( ( ( fhr_status & RX_VALID ) == 0 ) || ( ( fhr_status & RX_ERRORS ) != 0 ) ) + { + ksz8851_reg_setbits(REG_RXQ_CMD, RXQ_CMD_FREE_PACKET); + FreeRTOS_printf( ( "ksz8851snl_update: RX packet error!\n" ) ); + + /* RX step4-5: check for received frames. */ + xMicrelDevice.us_pending_frame = ksz8851_reg_read(REG_RX_FRAME_CNT_THRES) >> 8; + if( xMicrelDevice.us_pending_frame == 0 ) + { + /* RX step24: enable INT_RX flag. */ + ksz8851_reg_write(REG_INT_MASK, INT_RX); + } + ulISREvents |= EMAC_IF_ERR_EVENT; + } + else + { + size_t xLength; + /* RX step7: read frame length. */ + xLength = ksz8851_reg_read(REG_RX_FHR_BYTE_CNT) & RX_BYTE_CNT_MASK; + + /* RX step8: Drop packet if len is invalid or no descriptor available. */ + if( xLength == 0 ) + { + ksz8851_reg_setbits( REG_RXQ_CMD, RXQ_CMD_FREE_PACKET ); + FreeRTOS_printf( ( "ksz8851snl_update: RX bad len!\n" ) ); + ulISREvents |= EMAC_IF_ERR_EVENT; + } + else + { + size_t xReadLength = xLength; + + xMicrelDevice.ul_total_rx++; + /* RX step9: reset RX frame pointer. */ + ksz8851_reg_clrbits(REG_RX_ADDR_PTR, ADDR_PTR_MASK); + + /* RX step10: start RXQ read access. */ + ksz8851_reg_setbits(REG_RXQ_CMD, RXQ_START); + /* RX step11-17: start asynchronous FIFO read operation. */ + xMicrelDevice.ul_spi_pdc_status = SPI_PDC_RX_START; + gpio_set_pin_low( KSZ8851SNL_CSN_GPIO ); + if( ( xReadLength & ( sizeof( size_t ) - 1 ) ) != 0 ) + { + xReadLength = ( xReadLength | ( sizeof( size_t ) - 1 ) ) + 1; + } + + /* Pass the buffer minus 2 bytes, see ksz8851snl.c: RXQ_TWOBYTE_OFFSET. */ + ksz8851_fifo_read( pxNetworkBuffer->pucEthernetBuffer - 2, xReadLength ); + /* Remove CRC and update buffer length. */ + xLength -= 4; + pxNetworkBuffer->xDataLength = xLength; + /* Wait for SPI interrupt to set status 'SPI_PDC_RX_COMPLETE'. */ + } + } + break; + } /* ul_had_intn_interrupt || us_pending_frame */ + /* + * ========================== Handle TX ========================== + */ + + /* Fetch next packet to be sent. */ + if( ( xMicrelDevice.tx_busy[ txTail ] != pdFALSE ) && + ( xMicrelDevice.us_pending_frame == 0 ) && + ( xMicrelDevice.ul_had_intn_interrupt == 0 ) ) + { + NetworkBufferDescriptor_t *pxNetworkBuffer = xMicrelDevice.tx_buffers[ txTail ]; + size_t xLength = pxNetworkBuffer->xDataLength; + int iIndex = xLength; + + xLength = 4 * ( ( xLength + 3 ) / 4 ); + while( iIndex < ( int ) xLength ) + { + pxNetworkBuffer->pucEthernetBuffer[ iIndex ] = '\0'; + iIndex++; + } + pxNetworkBuffer->xDataLength = xLength; + + /* TX step1: check if TXQ memory size is available for transmit. */ + txmir = ksz8851_reg_read( REG_TX_MEM_INFO ); + txmir = txmir & TX_MEM_AVAILABLE_MASK; + + if( txmir < ( xLength + 8 ) ) + { + if( wait_tx_space == pdFALSE ) + { + tx_status = ksz8851_reg_read( REG_TX_STATUS ); + fhr_status = ksz8851_reg_read( REG_RX_FHR_STATUS ); + wait_tx_space = pdTRUE; + } + //return; + rx_debug = 1; + tx_space = txmir; + } + else + { + tx_space = txmir; + + /* TX step2: disable all interrupts. */ + ksz8851_reg_write( REG_INT_MASK, 0 ); + + xMicrelDevice.tx_space -= xLength; + + /* TX step3: enable TXQ write access. */ + ksz8851_reg_setbits( REG_RXQ_CMD, RXQ_START ); + /* TX step4-8: perform FIFO write operation. */ + xMicrelDevice.ul_spi_pdc_status = SPI_PDC_TX_START; + xMicrelDevice.tx_cur_buffer = pxNetworkBuffer; + /* Bring SPI SS low. */ + gpio_set_pin_low( KSZ8851SNL_CSN_GPIO ); + xMicrelDevice.ul_total_tx++; + + ksz8851_fifo_write( pxNetworkBuffer->pucEthernetBuffer, xLength, xLength ); + } + } + } + break; /* SPI_PDC_IDLE */ + + case SPI_PDC_RX_COMPLETE: + { + int rxHead = xMicrelDevice.us_rx_head; + /* RX step18-19: pad with dummy data to keep dword alignment. */ + /* Packet lengths will be rounded up to a multiple of "sizeof size_t". */ +// xLength = xMicrelDevice.rx_buffers[ rxHead ]->xDataLength & 3; +// if( xLength != 0 ) +// { +// ksz8851_fifo_dummy( 4 - xLength ); +// } + + /* RX step20: end RX transfer. */ + gpio_set_pin_high( KSZ8851SNL_CSN_GPIO ); + + /* Disable asynchronous transfer mode. */ + xMicrelDevice.ul_spi_pdc_status = SPI_PDC_IDLE; + + /* RX step21: end RXQ read access. */ + ksz8851_reg_clrbits(REG_RXQ_CMD, RXQ_START); + + /* RX step22-23: update frame count to be read. */ + xMicrelDevice.us_pending_frame -= 1; + + /* RX step24: enable INT_RX flag if transfer complete. */ + if( xMicrelDevice.us_pending_frame == 0 ) + { + ksz8851_reg_write(REG_INT_MASK, INT_RX); + } + + /* Mark descriptor ready to be read. */ + xMicrelDevice.rx_ready[ rxHead ] = pdTRUE; + if( ++rxHead == MICREL_RX_BUFFERS ) + { + rxHead = 0; + } + xMicrelDevice.us_rx_head = rxHead; + if( rx_debug != 0 ) + { + uint32_t txmir; + rx_debug = 0; + txmir = ksz8851_reg_read( REG_TX_MEM_INFO ); + txmir = txmir & TX_MEM_AVAILABLE_MASK; + } + /* Tell prvEMACHandlerTask that RX packets are available. */ + ulISREvents |= EMAC_IF_RX_EVENT; + } /* case SPI_PDC_RX_COMPLETE */ + break; + + case SPI_PDC_TX_COMPLETE: + { + int txTail = xMicrelDevice.us_tx_tail; + NetworkBufferDescriptor_t *pxNetworkBuffer = xMicrelDevice.tx_buffers[ txTail ]; + + size_t xLength; + /* TX step9-10: pad with dummy data to keep dword alignment. */ + /* Not necessary: length is already a multiple of 4. */ + xLength = pxNetworkBuffer->xDataLength & 3; + if( xLength != 0 ) + { +// ksz8851_fifo_dummy( 4 - xLength ); + } + +// /* TX step11: end TX transfer. */ + gpio_set_pin_high( KSZ8851SNL_CSN_GPIO ); + + /* Disable asynchronous transfer mode. */ + xMicrelDevice.ul_spi_pdc_status = SPI_PDC_IDLE; + + /* TX step12: disable TXQ write access. */ + ksz8851_reg_clrbits( REG_RXQ_CMD, RXQ_START ); + + xMicrelDevice.tx_space = ksz8851_reg_read( REG_TX_MEM_INFO ) & TX_MEM_AVAILABLE_MASK; + + /* TX step12.1: enqueue frame in TXQ. */ + ksz8851_reg_setbits( REG_TXQ_CMD, TXQ_ENQUEUE ); + + /* RX step13: enable INT_RX flag. */ +// ksz8851_reg_write( REG_INT_MASK, INT_RX ); + /* Buffer sent, free the corresponding buffer and mark descriptor as owned by software. */ + vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ); + + xMicrelDevice.tx_buffers[ txTail ] = NULL; + xMicrelDevice.tx_busy[ txTail ] = pdFALSE; + if( ++txTail == MICREL_TX_BUFFERS ) + { + txTail = 0; + } + + xMicrelDevice.us_tx_tail = txTail; + /* Experiment. */ + //xMicrelDevice.ul_had_intn_interrupt = 1; + if( xTransmitHandle != NULL ) + { + xTaskNotifyGive( xTransmitHandle ); + } +#warning moved downward + /* RX step13: enable INT_RX flag. */ + ksz8851_reg_write( REG_INT_MASK, INT_RX ); + /* Prevent the EMAC task from sleeping a single time. */ + ulISREvents |= EMAC_IF_TX_EVENT; + } /* case SPI_PDC_TX_COMPLETE */ + break; + } /* switch( xMicrelDevice.ul_spi_pdc_status ) */ +} + +/** + * \brief Set up the RX descriptor ring buffers. + * + * This function sets up the descriptor list used for RX packets. + * + */ +static void ksz8851snl_rx_init() +{ + uint32_t ul_index = 0; + + /* Init pointer index. */ + xMicrelDevice.us_rx_head = 0; + xMicrelDevice.us_rx_tail = 0; + + /* Set up the RX descriptors. */ + for (ul_index = 0; ul_index < MICREL_RX_BUFFERS; ul_index++) { + xMicrelDevice.rx_buffers[ul_index] = NULL; + xMicrelDevice.rx_ready[ul_index] = pdFALSE; + } + + /* Build RX buffer and descriptors. */ + ksz8851snl_rx_populate_queue(); +} + +/** + * \brief Set up the TX descriptor ring buffers. + * + * This function sets up the descriptor list used for TX packets. + * + */ +static void ksz8851snl_tx_init() +{ + uint32_t ul_index = 0; + + /* Init TX index pointer. */ + xMicrelDevice.us_tx_head = 0; + xMicrelDevice.us_tx_tail = 0; + + /* Set up the TX descriptors */ + for( ul_index = 0; ul_index < MICREL_TX_BUFFERS; ul_index++ ) + { + xMicrelDevice.tx_busy[ul_index] = pdFALSE; + } + xMicrelDevice.tx_space = 6144; +} + +/** + * \brief Initialize ksz8851snl ethernet controller. + * + * \note Called from ethernetif_init(). + * + * \param netif the lwIP network interface structure for this ethernetif. + */ +static void ksz8851snl_low_level_init( void ) +{ + ksz8851snl_rx_init(); + ksz8851snl_tx_init(); + + /* Enable NVIC interrupts. */ + NVIC_SetPriority(SPI_IRQn, INT_PRIORITY_SPI); + NVIC_EnableIRQ(SPI_IRQn); + + /* Initialize SPI link. */ + if( ksz8851snl_init() < 0 ) + { + FreeRTOS_printf( ( "ksz8851snl_low_level_init: failed to initialize the Micrel driver!\n" ) ); + configASSERT(0 == 1); + } + memset( xMicrelDevice.pusHashTable, 255, sizeof( xMicrelDevice.pusHashTable ) ); + ksz8851_reg_write( REG_MAC_HASH_0, FreeRTOS_htons( xMicrelDevice.pusHashTable[ 0 ] ) ); + ksz8851_reg_write( REG_MAC_HASH_2, FreeRTOS_htons( xMicrelDevice.pusHashTable[ 1 ] ) ); + ksz8851_reg_write( REG_MAC_HASH_4, FreeRTOS_htons( xMicrelDevice.pusHashTable[ 2 ] ) ); + ksz8851_reg_write( REG_MAC_HASH_6, FreeRTOS_htons( xMicrelDevice.pusHashTable[ 3 ] ) ); + + /* Initialize interrupt line INTN. */ + configure_intn( INTN_Handler ); +} + +/** + * \brief Use pre-allocated pbuf as DMA source and return the incoming packet. + * + * \param netif the lwIP network interface structure for this ethernetif. + * + * \return a pbuf filled with the received packet (including MAC header). + * 0 on memory error. + */ +static NetworkBufferDescriptor_t *ksz8851snl_low_level_input( void ) +{ +NetworkBufferDescriptor_t *pxNetworkBuffer = NULL; +int rxTail = xMicrelDevice.us_rx_tail; + + /* Check that descriptor is owned by software (ie packet received). */ + if( xMicrelDevice.rx_ready[ rxTail ] != pdFALSE ) + { + + /* Fetch pre-allocated buffer */ + pxNetworkBuffer = xMicrelDevice.rx_buffers[ rxTail ]; + + /* Remove this pbuf from its descriptor. */ + xMicrelDevice.rx_buffers[ rxTail ] = NULL; + + /* Clears rx_ready and sets rx_buffers. */ + ksz8851snl_rx_populate_queue(); + + if( ++rxTail == MICREL_RX_BUFFERS ) + { + rxTail = 0; + } + xMicrelDevice.us_rx_tail = rxTail; + } + + return pxNetworkBuffer; +} +/*-----------------------------------------------------------*/ + +static uint32_t prvEMACRxPoll( void ) +{ +NetworkBufferDescriptor_t *pxNetworkBuffer; +IPStackEvent_t xRxEvent = { eNetworkRxEvent, NULL }; +uint32_t ulReturnValue = 0; + + for( ;; ) + { + /* Only for logging. */ + int rxTail = xMicrelDevice.us_rx_tail; + EthernetHeader_t *pxEthernetHeader; + + pxNetworkBuffer = ksz8851snl_low_level_input(); + + if( pxNetworkBuffer == NULL ) + { + break; + } + pxEthernetHeader = ( EthernetHeader_t * ) ( pxNetworkBuffer->pucEthernetBuffer ); + + if( ( pxEthernetHeader->usFrameType != ipIPv4_FRAME_TYPE ) && + ( pxEthernetHeader->usFrameType != ipARP_FRAME_TYPE ) ) + { + FreeRTOS_printf( ( "Frame type %02X received\n", pxEthernetHeader->usFrameType ) ); + } + ulReturnValue++; + + xRxEvent.pvData = ( void * )pxNetworkBuffer; + /* Send the descriptor to the IP task for processing. */ + if( xSendEventStructToIPTask( &xRxEvent, 100UL ) != pdTRUE ) + { + vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ); + iptraceETHERNET_RX_EVENT_LOST(); + FreeRTOS_printf( ( "prvEMACRxPoll: Can not queue return packet!\n" ) ); + } + } + + return ulReturnValue; +} +/*-----------------------------------------------------------*/ + +static void prvEMACHandlerTask( void *pvParameters ) +{ +TimeOut_t xPhyTime; +TickType_t xPhyRemTime; +TickType_t xLoggingTime; +UBaseType_t uxLastMinBufferCount = 0; +UBaseType_t uxCurrentCount; +BaseType_t xResult = 0; +uint32_t xStatus; +const TickType_t ulMaxBlockTime = pdMS_TO_TICKS( EMAC_MAX_BLOCK_TIME_MS ); +#if( ipconfigCHECK_IP_QUEUE_SPACE != 0 ) + UBaseType_t uxLastMinQueueSpace = 0; +#endif + + /* Remove compiler warnings about unused parameters. */ + ( void ) pvParameters; + + configASSERT( xEMACTaskHandle ); + + vTaskSetTimeOutState( &xPhyTime ); + xPhyRemTime = pdMS_TO_TICKS( PHY_LS_LOW_CHECK_TIME_MS ); + xLoggingTime = xTaskGetTickCount(); + + for( ;; ) + { + uxCurrentCount = uxGetMinimumFreeNetworkBuffers(); + if( uxLastMinBufferCount != uxCurrentCount ) + { + /* The logging produced below may be helpful + while tuning +TCP: see how many buffers are in use. */ + uxLastMinBufferCount = uxCurrentCount; + FreeRTOS_printf( ( "Network buffers: %lu lowest %lu\n", + uxGetNumberOfFreeNetworkBuffers(), uxCurrentCount ) ); + } + + #if( ipconfigCHECK_IP_QUEUE_SPACE != 0 ) + { + uxCurrentCount = uxGetMinimumIPQueueSpace(); + if( uxLastMinQueueSpace != uxCurrentCount ) + { + /* The logging produced below may be helpful + while tuning +TCP: see how many buffers are in use. */ + uxLastMinQueueSpace = uxCurrentCount; + FreeRTOS_printf( ( "Queue space: lowest %lu\n", uxCurrentCount ) ); + } + } + #endif /* ipconfigCHECK_IP_QUEUE_SPACE */ + + /* Run the state-machine of the ksz8851 driver. */ + ksz8851snl_update(); + + if( ( ulISREvents & EMAC_IF_ALL_EVENT ) == 0 ) + { + /* No events to process now, wait for the next. */ + ulTaskNotifyTake( pdTRUE, ulMaxBlockTime ); + } + + if( ( xTaskGetTickCount() - xLoggingTime ) > 10000 ) + { + xLoggingTime += 10000; + FreeRTOS_printf( ( "Now Tx/Rx %7d /%7d\n", + xMicrelDevice.ul_total_tx, xMicrelDevice.ul_total_rx ) ); + } + + if( ( ulISREvents & EMAC_IF_RX_EVENT ) != 0 ) + { + ulISREvents &= ~EMAC_IF_RX_EVENT; + + /* Wait for the EMAC interrupt to indicate that another packet has been + received. */ + xResult = prvEMACRxPoll(); + } + + if( ( ulISREvents & EMAC_IF_TX_EVENT ) != 0 ) + { + /* Future extension: code to release TX buffers if zero-copy is used. */ + ulISREvents &= ~EMAC_IF_TX_EVENT; + } + + if( ( ulISREvents & EMAC_IF_ERR_EVENT ) != 0 ) + { + /* Future extension: logging about errors that occurred. */ + ulISREvents &= ~EMAC_IF_ERR_EVENT; + } + + if( xResult > 0 ) + { + /* As long as packets are being received, assume that + the Link Status is high. */ + ulPHYLinkStatus |= BMSR_LINK_STATUS; + /* A packet was received. No need to check for the PHY status now, + but set a timer to check it later on. */ + vTaskSetTimeOutState( &xPhyTime ); + xPhyRemTime = pdMS_TO_TICKS( PHY_LS_HIGH_CHECK_TIME_MS ); + xResult = 0; + } + else if( ( xTaskCheckForTimeOut( &xPhyTime, &xPhyRemTime ) != pdFALSE ) && + ( xMicrelDevice.ul_spi_pdc_status == SPI_PDC_IDLE ) ) + { + /* Check the link status again. */ + xStatus = ulReadMDIO( PHY_REG_01_BMSR ); + + if( ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != ( xStatus & BMSR_LINK_STATUS ) ) + { + ulPHYLinkStatus = xStatus; + FreeRTOS_printf( ( "prvEMACHandlerTask: PHY LS now %d\n", ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != 0 ) ); + } + + vTaskSetTimeOutState( &xPhyTime ); + if( ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != 0 ) + { + xPhyRemTime = pdMS_TO_TICKS( PHY_LS_HIGH_CHECK_TIME_MS ); + } + else + { + xPhyRemTime = pdMS_TO_TICKS( PHY_LS_LOW_CHECK_TIME_MS ); + } + } + } +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ksz8851snl/ksz8851snl.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ksz8851snl/ksz8851snl.c new file mode 100644 index 0000000..1579863 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ksz8851snl/ksz8851snl.c @@ -0,0 +1,610 @@ +/** + * + * \file + * + * \brief KS8851SNL driver for SAM. + * + * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#include "spi_master.h" +#include "ksz8851snl.h" +#include "ksz8851snl_reg.h" +#include "delay.h" +#include "pio.h" +#include "pio_handler.h" +#include "pdc.h" +#include "conf_eth.h" + +/* Clock polarity. */ +#define SPI_CLK_POLARITY 0 + +/* Clock phase. */ +#define SPI_CLK_PHASE 1 + +/* SPI PDC register base. */ +Pdc *g_p_spi_pdc = 0; + +int lUDPLoggingPrintf( const char *pcFormatString, ... ); + +/* Temporary buffer for PDC reception. */ +uint8_t tmpbuf[1536] __attribute__ ((aligned (16))); + +union { + uint64_t ul[2]; + uint8_t uc[16]; +} cmdBuf, respBuf; + +void dbg_add_line( const char *pcFormat, ... ); + +static void spi_clear_ovres( void ); + +/** + * \brief Read register content, set bitmask and write back to register. + * + * \param reg the register address to modify. + * \param bits_to_set bitmask to apply. + */ +void ksz8851_reg_setbits(uint16_t reg, uint16_t bits_to_set) +{ + uint16_t temp; + + temp = ksz8851_reg_read(reg); + temp |= bits_to_set; + ksz8851_reg_write(reg, temp); +} + +/** + * \brief Read register content, clear bitmask and write back to register. + * + * \param reg the register address to modify. + * \param bits_to_set bitmask to apply. + */ +void ksz8851_reg_clrbits(uint16_t reg, uint16_t bits_to_clr) +{ + uint16_t temp; + + temp = ksz8851_reg_read(reg); + temp &= ~(uint32_t) bits_to_clr; + ksz8851_reg_write(reg, temp); +} + +/** + * \brief Configure the INTN interrupt. + */ +void configure_intn(void (*p_handler) (uint32_t, uint32_t)) +{ +// gpio_configure_pin(KSZ8851SNL_INTN_GPIO, PIO_INPUT); +// pio_set_input(PIOA, PIO_PA11_IDX, PIO_PULLUP); + + /* Configure PIO clock. */ + pmc_enable_periph_clk(INTN_ID); + + /* Adjust PIO debounce filter parameters, uses 10 Hz filter. */ + pio_set_debounce_filter(INTN_PIO, INTN_PIN_MSK, 10); + + /* Initialize PIO interrupt handlers, see PIO definition in board.h. */ + pio_handler_set(INTN_PIO, INTN_ID, INTN_PIN_MSK, + INTN_ATTR, p_handler); + + /* Enable NVIC interrupts. */ + NVIC_SetPriority(INTN_IRQn, INT_PRIORITY_PIO); + NVIC_EnableIRQ((IRQn_Type)INTN_ID); + + /* Enable PIO interrupts. */ + pio_enable_interrupt(INTN_PIO, INTN_PIN_MSK); +} + +/** + * \brief Read a register value. + * + * \param reg the register address to modify. + * + * \return the register value. + */ +uint16_t ksz8851_reg_read(uint16_t reg) +{ +pdc_packet_t g_pdc_spi_tx_packet; +pdc_packet_t g_pdc_spi_rx_packet; +uint16_t cmd = 0; +uint16_t res = 0; +int iTryCount = 3; + + while( iTryCount-- > 0 ) + { + uint32_t ulStatus; + + spi_clear_ovres(); + /* Move register address to cmd bits 9-2, make 32-bit address. */ + cmd = (reg << 2) & REG_ADDR_MASK; + + /* Last 2 bits still under "don't care bits" handled with byte enable. */ + /* Select byte enable for command. */ + if (reg & 2) { + /* Odd word address writes bytes 2 and 3 */ + cmd |= (0xc << 10); + } else { + /* Even word address write bytes 0 and 1 */ + cmd |= (0x3 << 10); + } + + /* Add command read code. */ + cmd |= CMD_READ; + cmdBuf.uc[0] = cmd >> 8; + cmdBuf.uc[1] = cmd & 0xff; + cmdBuf.uc[2] = CONFIG_SPI_MASTER_DUMMY; + cmdBuf.uc[3] = CONFIG_SPI_MASTER_DUMMY; + + /* Prepare PDC transfer. */ + g_pdc_spi_tx_packet.ul_addr = (uint32_t) cmdBuf.uc; + g_pdc_spi_tx_packet.ul_size = 4; + g_pdc_spi_rx_packet.ul_addr = (uint32_t) tmpbuf; + g_pdc_spi_rx_packet.ul_size = 4; + pdc_disable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS); + pdc_tx_init(g_p_spi_pdc, &g_pdc_spi_tx_packet, NULL); + pdc_rx_init(g_p_spi_pdc, &g_pdc_spi_rx_packet, NULL); + gpio_set_pin_low(KSZ8851SNL_CSN_GPIO); + + spi_disable_interrupt( KSZ8851SNL_SPI, ~0ul ); + pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN); + for( ;; ) + { + ulStatus = spi_read_status( KSZ8851SNL_SPI ); + if( ( ulStatus & ( SPI_SR_OVRES | SPI_SR_ENDRX ) ) != 0 ) + { + break; + } + } + gpio_set_pin_high( KSZ8851SNL_CSN_GPIO ); + if( ( ulStatus & SPI_SR_OVRES ) == 0 ) + { + break; + } + pdc_disable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS); + lUDPLoggingPrintf( "ksz8851_reg_read: SPI_SR_OVRES\n" ); + } + + res = (tmpbuf[3] << 8) | tmpbuf[2]; + return res; +} + +/** + * \brief Write a register value. + * + * \param reg the register address to modify. + * \param wrdata the new register value. + */ +void ksz8851_reg_write(uint16_t reg, uint16_t wrdata) +{ +pdc_packet_t g_pdc_spi_tx_packet; +pdc_packet_t g_pdc_spi_rx_packet; +uint16_t cmd = 0; +int iTryCount = 3; + + while( iTryCount-- > 0 ) + { + uint32_t ulStatus; + + + spi_clear_ovres(); + /* Move register address to cmd bits 9-2, make 32-bit address. */ + cmd = (reg << 2) & REG_ADDR_MASK; + + /* Last 2 bits still under "don't care bits" handled with byte enable. */ + /* Select byte enable for command. */ + if (reg & 2) { + /* Odd word address writes bytes 2 and 3 */ + cmd |= (0xc << 10); + } else { + /* Even word address write bytes 0 and 1 */ + cmd |= (0x3 << 10); + } + + /* Add command write code. */ + cmd |= CMD_WRITE; + cmdBuf.uc[0] = cmd >> 8; + cmdBuf.uc[1] = cmd & 0xff; + cmdBuf.uc[2] = wrdata & 0xff; + cmdBuf.uc[3] = wrdata >> 8; + + /* Prepare PDC transfer. */ + g_pdc_spi_tx_packet.ul_addr = (uint32_t) cmdBuf.uc; + g_pdc_spi_tx_packet.ul_size = 4; + g_pdc_spi_rx_packet.ul_addr = (uint32_t) tmpbuf; + g_pdc_spi_rx_packet.ul_size = 4; + pdc_disable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS); + pdc_tx_init(g_p_spi_pdc, &g_pdc_spi_tx_packet, NULL); + pdc_rx_init(g_p_spi_pdc, &g_pdc_spi_rx_packet, NULL); + gpio_set_pin_low(KSZ8851SNL_CSN_GPIO); + + spi_disable_interrupt( KSZ8851SNL_SPI, ~0ul ); + + pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN); + for( ;; ) + { + ulStatus = spi_read_status( KSZ8851SNL_SPI ); + if( ( ulStatus & ( SPI_SR_OVRES | SPI_SR_ENDRX ) ) != 0 ) + { + break; + } + } + gpio_set_pin_high( KSZ8851SNL_CSN_GPIO ); + if( ( ulStatus & SPI_SR_OVRES ) == 0 ) + { + break; + } + pdc_disable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS); + lUDPLoggingPrintf( "ksz8851_reg_write: SPI_SR_OVRES\n" ); + } +} + +static void spi_clear_ovres( void ) +{ +volatile uint32_t rc; + rc = KSZ8851SNL_SPI->SPI_RDR; + + spi_read_status( KSZ8851SNL_SPI ); +} + +/** + * \brief Read internal fifo buffer. + * + * \param buf the buffer to store the data from the fifo buffer. + * \param len the amount of data to read. + */ +void ksz8851_fifo_read(uint8_t *buf, uint32_t len) +{ + pdc_packet_t g_pdc_spi_tx_packet; + pdc_packet_t g_pdc_spi_rx_packet; + pdc_packet_t g_pdc_spi_tx_npacket; + pdc_packet_t g_pdc_spi_rx_npacket; + + memset( cmdBuf.uc, '\0', sizeof cmdBuf ); + cmdBuf.uc[0] = FIFO_READ; + spi_clear_ovres(); + + /* Prepare PDC transfer. */ + g_pdc_spi_tx_packet.ul_addr = (uint32_t) cmdBuf.uc; + g_pdc_spi_tx_packet.ul_size = 9; + g_pdc_spi_rx_packet.ul_addr = (uint32_t) respBuf.uc; + g_pdc_spi_rx_packet.ul_size = 9; + + g_pdc_spi_tx_npacket.ul_addr = (uint32_t) buf; + g_pdc_spi_tx_npacket.ul_size = len; + g_pdc_spi_rx_npacket.ul_addr = (uint32_t) buf; + g_pdc_spi_rx_npacket.ul_size = len; + pdc_disable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS); + pdc_tx_init(g_p_spi_pdc, &g_pdc_spi_tx_packet, &g_pdc_spi_tx_npacket); + pdc_rx_init(g_p_spi_pdc, &g_pdc_spi_rx_packet, &g_pdc_spi_rx_npacket); + +spi_enable_interrupt(KSZ8851SNL_SPI, SPI_IER_RXBUFF | SPI_IER_OVRES); + + pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN); +} + +/** + * \brief Write internal fifo buffer. + * + * \param buf the buffer to send to the fifo buffer. + * \param ulActualLength the total amount of data to write. + * \param ulFIFOLength the size of the first pbuf to write from the pbuf chain. + */ +void ksz8851_fifo_write(uint8_t *buf, uint32_t ulActualLength, uint32_t ulFIFOLength) +{ + static uint8_t frameID = 0; + + pdc_packet_t g_pdc_spi_tx_packet; + pdc_packet_t g_pdc_spi_rx_packet; + pdc_packet_t g_pdc_spi_tx_npacket; + pdc_packet_t g_pdc_spi_rx_npacket; + + /* Prepare control word and byte count. */ + cmdBuf.uc[0] = FIFO_WRITE; + cmdBuf.uc[1] = frameID++ & 0x3f; + cmdBuf.uc[2] = 0; + cmdBuf.uc[3] = ulActualLength & 0xff; + cmdBuf.uc[4] = ulActualLength >> 8; + + spi_clear_ovres(); + + /* Prepare PDC transfer. */ + g_pdc_spi_tx_packet.ul_addr = (uint32_t) cmdBuf.uc; + g_pdc_spi_tx_packet.ul_size = 5; + + g_pdc_spi_rx_packet.ul_addr = (uint32_t) respBuf.uc; + g_pdc_spi_rx_packet.ul_size = 5; + + g_pdc_spi_tx_npacket.ul_addr = (uint32_t) buf; + g_pdc_spi_tx_npacket.ul_size = ulFIFOLength; + + g_pdc_spi_rx_npacket.ul_addr = (uint32_t) tmpbuf; + g_pdc_spi_rx_npacket.ul_size = ulFIFOLength; + + pdc_disable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS); + pdc_tx_init(g_p_spi_pdc, &g_pdc_spi_tx_packet, &g_pdc_spi_tx_npacket); + #if( TX_USES_RECV == 1 ) + pdc_rx_init(g_p_spi_pdc, &g_pdc_spi_rx_packet, &g_pdc_spi_rx_npacket); + spi_enable_interrupt(KSZ8851SNL_SPI, SPI_IER_ENDRX | SPI_IER_OVRES); + pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN); + #else + spi_enable_interrupt(KSZ8851SNL_SPI, SPI_SR_TXBUFE | SPI_IER_OVRES); + pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_TXTEN); + #endif +} + +/** + * \brief Write dummy data to the internal fifo buffer. + * + * \param len the amount of dummy data to write. + */ +void ksz8851_fifo_dummy(uint32_t len) +{ + pdc_packet_t g_pdc_spi_tx_packet; + pdc_packet_t g_pdc_spi_rx_packet; + + /* Prepare PDC transfer. */ + g_pdc_spi_tx_packet.ul_addr = (uint32_t) tmpbuf; + g_pdc_spi_tx_packet.ul_size = len; + g_pdc_spi_rx_packet.ul_addr = (uint32_t) tmpbuf; + g_pdc_spi_rx_packet.ul_size = len; + pdc_disable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS); + pdc_tx_init(g_p_spi_pdc, &g_pdc_spi_tx_packet, NULL); + pdc_rx_init(g_p_spi_pdc, &g_pdc_spi_rx_packet, NULL); + pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN); + + while (!(spi_read_status(KSZ8851SNL_SPI) & SPI_SR_ENDRX)) + ; +} + +void ksz8851snl_set_registers(void) +{ + /* Init step2-4: write QMU MAC address (low, middle then high). */ + ksz8851_reg_write(REG_MAC_ADDR_0, (ETHERNET_CONF_ETHADDR4 << 8) | ETHERNET_CONF_ETHADDR5); + ksz8851_reg_write(REG_MAC_ADDR_2, (ETHERNET_CONF_ETHADDR2 << 8) | ETHERNET_CONF_ETHADDR3); + ksz8851_reg_write(REG_MAC_ADDR_4, (ETHERNET_CONF_ETHADDR0 << 8) | ETHERNET_CONF_ETHADDR1); + + /* Init step5: enable QMU Transmit Frame Data Pointer Auto Increment. */ + ksz8851_reg_write(REG_TX_ADDR_PTR, ADDR_PTR_AUTO_INC); + + /* Init step6: configure QMU transmit control register. */ + ksz8851_reg_write(REG_TX_CTRL, + TX_CTRL_ICMP_CHECKSUM | + TX_CTRL_UDP_CHECKSUM | + TX_CTRL_TCP_CHECKSUM | + TX_CTRL_IP_CHECKSUM | + TX_CTRL_FLOW_ENABLE | + TX_CTRL_PAD_ENABLE | + TX_CTRL_CRC_ENABLE + ); + + /* Init step7: enable QMU Receive Frame Data Pointer Auto Increment. */ + ksz8851_reg_write(REG_RX_ADDR_PTR, ADDR_PTR_AUTO_INC); + + /* Init step8: configure QMU Receive Frame Threshold for one frame. */ + ksz8851_reg_write(REG_RX_FRAME_CNT_THRES, 1); + + /* Init step9: configure QMU receive control register1. */ + ksz8851_reg_write(REG_RX_CTRL1, + RX_CTRL_UDP_CHECKSUM | + RX_CTRL_TCP_CHECKSUM | + RX_CTRL_IP_CHECKSUM | + RX_CTRL_MAC_FILTER | + RX_CTRL_FLOW_ENABLE | + RX_CTRL_BROADCAST | + RX_CTRL_ALL_MULTICAST| + RX_CTRL_UNICAST); +// ksz8851_reg_write(REG_RX_CTRL1, +// RX_CTRL_UDP_CHECKSUM | +// RX_CTRL_TCP_CHECKSUM | +// RX_CTRL_IP_CHECKSUM | +// RX_CTRL_FLOW_ENABLE | +// RX_CTRL_PROMISCUOUS); + + ksz8851_reg_write(REG_RX_CTRL2, + RX_CTRL_IPV6_UDP_NOCHECKSUM | + RX_CTRL_UDP_LITE_CHECKSUM | + RX_CTRL_ICMP_CHECKSUM | + RX_CTRL_BURST_LEN_FRAME); + + +//#define RXQ_TWOBYTE_OFFSET (0x0200) /* Enable adding 2-byte before frame header for IP aligned with DWORD */ +#warning Remember to try the above option to get a 2-byte offset + + /* Init step11: configure QMU receive queue: trigger INT and auto-dequeue frame. */ + ksz8851_reg_write( REG_RXQ_CMD, RXQ_CMD_CNTL | RXQ_TWOBYTE_OFFSET ); + + /* Init step12: adjust SPI data output delay. */ + ksz8851_reg_write(REG_BUS_CLOCK_CTRL, BUS_CLOCK_166 | BUS_CLOCK_DIVIDEDBY_1); + + /* Init step13: restart auto-negotiation. */ + ksz8851_reg_setbits(REG_PORT_CTRL, PORT_AUTO_NEG_RESTART); + + /* Init step13.1: force link in half duplex if auto-negotiation failed. */ + if ((ksz8851_reg_read(REG_PORT_CTRL) & PORT_AUTO_NEG_RESTART) != PORT_AUTO_NEG_RESTART) + { + ksz8851_reg_clrbits(REG_PORT_CTRL, PORT_FORCE_FULL_DUPLEX); + } + + /* Init step14: clear interrupt status. */ + ksz8851_reg_write(REG_INT_STATUS, 0xFFFF); + + /* Init step15: set interrupt mask. */ + ksz8851_reg_write(REG_INT_MASK, INT_RX); + + /* Init step16: enable QMU Transmit. */ + ksz8851_reg_setbits(REG_TX_CTRL, TX_CTRL_ENABLE); + + /* Init step17: enable QMU Receive. */ + ksz8851_reg_setbits(REG_RX_CTRL1, RX_CTRL_ENABLE); +} +/** + * \brief KSZ8851SNL initialization function. + * + * \return 0 on success, 1 on communication error. + */ +uint32_t ksz8851snl_init(void) +{ +uint32_t count = 10; +uint16_t dev_id = 0; +uint8_t id_ok = 0; + + /* Configure the SPI peripheral. */ + spi_enable_clock(KSZ8851SNL_SPI); + spi_disable(KSZ8851SNL_SPI); + spi_reset(KSZ8851SNL_SPI); + spi_set_master_mode(KSZ8851SNL_SPI); + spi_disable_mode_fault_detect(KSZ8851SNL_SPI); + spi_set_peripheral_chip_select_value(KSZ8851SNL_SPI, ~(uint32_t)(1UL << KSZ8851SNL_CS_PIN)); +spi_set_fixed_peripheral_select(KSZ8851SNL_SPI); +//spi_disable_peripheral_select_decode(KSZ8851SNL_SPI); + + spi_set_clock_polarity(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, SPI_CLK_POLARITY); + spi_set_clock_phase(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, SPI_CLK_PHASE); + spi_set_bits_per_transfer(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, + SPI_CSR_BITS_8_BIT); + spi_set_baudrate_div(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, (sysclk_get_cpu_hz() / KSZ8851SNL_CLOCK_SPEED)); +// spi_set_transfer_delay(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, CONFIG_SPI_MASTER_DELAY_BS, +// CONFIG_SPI_MASTER_DELAY_BCT); + + + spi_set_transfer_delay(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, 0, 0); + + spi_enable(KSZ8851SNL_SPI); + + /* Get pointer to UART PDC register base. */ + g_p_spi_pdc = spi_get_pdc_base(KSZ8851SNL_SPI); + pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN); + + /* Control RSTN and CSN pin from the driver. */ + gpio_configure_pin(KSZ8851SNL_CSN_GPIO, KSZ8851SNL_CSN_FLAGS); + gpio_set_pin_high(KSZ8851SNL_CSN_GPIO); + gpio_configure_pin(KSZ8851SNL_RSTN_GPIO, KSZ8851SNL_RSTN_FLAGS); + + /* Reset the Micrel in a proper state. */ + while( count-- ) + { + /* Perform hardware reset with respect to the reset timing from the datasheet. */ + gpio_set_pin_low(KSZ8851SNL_RSTN_GPIO); + vTaskDelay(2); + gpio_set_pin_high(KSZ8851SNL_RSTN_GPIO); + vTaskDelay(2); + + /* Init step1: read chip ID. */ + dev_id = ksz8851_reg_read(REG_CHIP_ID); + if( ( dev_id & 0xFFF0 ) == CHIP_ID_8851_16 ) + { + id_ok = 1; + break; + } + } + if( id_ok != 0 ) + { + ksz8851snl_set_registers(); + } + + return id_ok ? 1 : -1; +} + +uint32_t ksz8851snl_reinit(void) +{ +uint32_t count = 10; +uint16_t dev_id = 0; +uint8_t id_ok = 0; + /* Reset the Micrel in a proper state. */ + while( count-- ) + { + /* Perform hardware reset with respect to the reset timing from the datasheet. */ + gpio_set_pin_low(KSZ8851SNL_RSTN_GPIO); + vTaskDelay(2); + gpio_set_pin_high(KSZ8851SNL_RSTN_GPIO); + vTaskDelay(2); + + /* Init step1: read chip ID. */ + dev_id = ksz8851_reg_read(REG_CHIP_ID); + if( ( dev_id & 0xFFF0 ) == CHIP_ID_8851_16 ) + { + id_ok = 1; + break; + } + } + if( id_ok != 0 ) + { + ksz8851snl_set_registers(); + } + + return id_ok ? 1 : -1; +} + +uint32_t ksz8851snl_reset_rx( void ) +{ +uint16_t usValue; + + usValue = ksz8851_reg_read(REG_RX_CTRL1); + + usValue &= ~( ( uint16_t ) RX_CTRL_ENABLE | RX_CTRL_FLUSH_QUEUE ); + + ksz8851_reg_write( REG_RX_CTRL1, usValue ); vTaskDelay( 2 ); + ksz8851_reg_write( REG_RX_CTRL1, usValue | RX_CTRL_FLUSH_QUEUE ); vTaskDelay( 1 ); + ksz8851_reg_write( REG_RX_CTRL1, usValue ); vTaskDelay( 1 ); + ksz8851_reg_write( REG_RX_CTRL1, usValue | RX_CTRL_ENABLE ); vTaskDelay( 1 ); + + return ( uint32_t )usValue; +} + +uint32_t ksz8851snl_reset_tx( void ) +{ +uint16_t usValue; + + usValue = ksz8851_reg_read( REG_TX_CTRL ); + + usValue &= ~( ( uint16_t ) TX_CTRL_ENABLE | TX_CTRL_FLUSH_QUEUE ); + + ksz8851_reg_write( REG_TX_CTRL, usValue ); vTaskDelay( 2 ); + ksz8851_reg_write( REG_TX_CTRL, usValue | TX_CTRL_FLUSH_QUEUE ); vTaskDelay( 1 ); + ksz8851_reg_write( REG_TX_CTRL, usValue ); vTaskDelay( 1 ); + ksz8851_reg_write( REG_TX_CTRL, usValue | TX_CTRL_ENABLE ); vTaskDelay( 1 ); + + return ( uint32_t )usValue; +} diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ksz8851snl/ksz8851snl.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ksz8851snl/ksz8851snl.h new file mode 100644 index 0000000..7952dc2 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ksz8851snl/ksz8851snl.h @@ -0,0 +1,67 @@ +/** + * + * \file + * + * \brief KS8851SNL driver for SAM. + * + * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef KSZ8851SNL_H_INCLUDED +#define KSZ8851SNL_H_INCLUDED + +#include "gpio.h" + +void configure_intn(void (*p_handler) (uint32_t, uint32_t)); +void ksz8851_reg_setbits(uint16_t reg, uint16_t bits_to_set); +void ksz8851_reg_clrbits(uint16_t reg, uint16_t bits_to_clr); +void ksz8851_fifo_read(uint8_t *buf, uint32_t len); +void ksz8851_fifo_write(uint8_t *buf, uint32_t ulActualLength, uint32_t ulFIFOLength); +void ksz8851_fifo_dummy(uint32_t len); +void ksz8851_reg_write(uint16_t reg, uint16_t wrdata); +uint16_t ksz8851_reg_read(uint16_t reg); +uint32_t ksz8851snl_init(void); +uint32_t ksz8851snl_reinit(void); + +uint32_t ksz8851snl_reset_rx( void ); +uint32_t ksz8851snl_reset_tx( void ); + +#endif /* KSZ8851SNL_H_INCLUDED */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ksz8851snl/ksz8851snl_reg.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ksz8851snl/ksz8851snl_reg.h new file mode 100644 index 0000000..3102fcc --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/NetworkInterface/ksz8851snl/ksz8851snl_reg.h @@ -0,0 +1,473 @@ +/** + * + * \file + * + * \brief KS8851SNL registers definitions. + * + * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef KSZ8851SNL_REG_H_INCLUDED +#define KSZ8851SNL_REG_H_INCLUDED + +#define REG_ADDR_MASK (0x3F0) /* Register address mask */ +#define OPCODE_MASK (3 << 14) +#define CMD_READ (0 << 14) +#define CMD_WRITE (1 << 14) +#define FIFO_READ (0x80) +#define FIFO_WRITE (0xC0) + +/* + * MAC Registers + * (Offset 0x00 - 0x25) + */ +#define REG_BUS_ERROR_STATUS (0x06) /* BESR */ +#define BUS_ERROR_IBEC (0x8000) +#define BUS_ERROR_IBECV_MASK (0x7800) /* Default IPSec clock at 166Mhz */ + +#define REG_CHIP_CFG_STATUS (0x08) /* CCFG */ +#define LITTLE_ENDIAN_BUS_MODE (0x0400) /* Bus in little endian mode */ +#define EEPROM_PRESENCE (0x0200) /* External EEPROM is used */ +#define SPI_BUS_MODE (0x0100) /* In SPI bus mode */ +#define DATA_BUS_8BIT (0x0080) /* In 8-bit bus mode operation */ +#define DATA_BUS_16BIT (0x0040) /* In 16-bit bus mode operation */ +#define DATA_BUS_32BIT (0x0020) /* In 32-bit bus mode operation */ +#define MULTIPLEX_MODE (0x0010) /* Data and address bus are shared */ +#define CHIP_PACKAGE_128PIN (0x0008) /* 128-pin package */ +#define CHIP_PACKAGE_80PIN (0x0004) /* 80-pin package */ +#define CHIP_PACKAGE_48PIN (0x0002) /* 48-pin package */ +#define CHIP_PACKAGE_32PIN (0x0001) /* 32-pin package for SPI host interface only */ + +#define REG_MAC_ADDR_0 (0x10) /* MARL */ +#define REG_MAC_ADDR_1 (0x11) /* MARL */ +#define REG_MAC_ADDR_2 (0x12) /* MARM */ +#define REG_MAC_ADDR_3 (0x13) /* MARM */ +#define REG_MAC_ADDR_4 (0x14) /* MARH */ +#define REG_MAC_ADDR_5 (0x15) /* MARH */ + +#define REG_BUS_CLOCK_CTRL (0x20) /* OBCR */ +#define BUS_CLOCK_166 (0x0004) /* 166 MHz on-chip bus clock (defaul is 125MHz) */ +#define BUS_CLOCK_DIVIDEDBY_5 (0x0003) /* Bus clock devided by 5 */ +#define BUS_CLOCK_DIVIDEDBY_3 (0x0002) /* Bus clock devided by 3 */ +#define BUS_CLOCK_DIVIDEDBY_2 (0x0001) /* Bus clock devided by 2 */ +#define BUS_CLOCK_DIVIDEDBY_1 (0x0000) /* Bus clock devided by 1 */ +#define BUS_CLOCK_DIVIDED_MASK (0x0003) /* Bus clock devider mask */ + +#define BUS_SPEED_166_MHZ (0x0004) /* Set bus speed to 166 MHz */ +#define BUS_SPEED_125_MHZ (0x0000) /* Set bus speed to 125 MHz */ +#define BUS_SPEED_83_MHZ (0x0005) /* Set bus speed to 83 MHz (166/2)*/ +#define BUS_SPEED_62_5_MHZ (0x0001) /* Set bus speed to 62.5 MHz (125/2) */ +#define BUS_SPEED_53_3_MHZ (0x0006) /* Set bus speed to 53.3 MHz (166/3) */ +#define BUS_SPEED_41_7_MHZ (0x0002) /* Set bus speed to 41.67 MHz (125/3) */ +#define BUS_SPEED_33_2_MHZ (0x0007) /* Set bus speed to 33.2 MHz (166/5) */ +#define BUS_SPEED_25_MHZ (0x0003) /* Set bus speed to 25 MHz (125/5) */ + +#define REG_EEPROM_CTRL (0x22) /* EEPCR */ +#define EEPROM_ACCESS_ENABLE (0x0010) /* Enable software to access EEPROM through bit 3 to bit 0 */ +#define EEPROM_DATA_IN (0x0008) /* Data receive from EEPROM (EEDI pin) */ +#define EEPROM_DATA_OUT (0x0004) /* Data transmit to EEPROM (EEDO pin) */ +#define EEPROM_SERIAL_CLOCK (0x0002) /* Serial clock (EESK pin) */ +#define EEPROM_CHIP_SELECT (0x0001) /* EEPROM chip select (EECS pin) */ + +#define REG_MEM_BIST_INFO (0x24) /* MBIR */ +#define TX_MEM_TEST_FINISHED (0x1000) /* TX memeory BIST test finish */ +#define TX_MEM_TEST_FAILED (0x0800) /* TX memory BIST test fail */ +#define TX_MEM_TEST_FAILED_COUNT (0x0700) /* TX memory BIST test fail count */ +#define RX_MEM_TEST_FINISHED (0x0010) /* RX memory BIST test finish */ +#define RX_MEM_TEST_FAILED (0x0008) /* RX memory BIST test fail */ +#define RX_MEM_TEST_FAILED_COUNT (0x0003) /* RX memory BIST test fail count */ + +#define REG_RESET_CTRL (0x26) /* GRR */ +#define QMU_SOFTWARE_RESET (0x0002) /* QMU soft reset (clear TxQ, RxQ) */ +#define GLOBAL_SOFTWARE_RESET (0x0001) /* Global soft reset (PHY, MAC, QMU) */ + +/* + * Wake On Lan Control Registers + * (Offset 0x2A - 0x6B) + */ +#define REG_WOL_CTRL (0x2A) /* WFCR */ +#define WOL_MAGIC_ENABLE (0x0080) /* Enable the magic packet pattern detection */ +#define WOL_FRAME3_ENABLE (0x0008) /* Enable the wake up frame 3 pattern detection */ +#define WOL_FRAME2_ENABLE (0x0004) /* Enable the wake up frame 2 pattern detection */ +#define WOL_FRAME1_ENABLE (0x0002) /* Enable the wake up frame 1 pattern detection */ +#define WOL_FRAME0_ENABLE (0x0001) /* Enable the wake up frame 0 pattern detection */ + +#define REG_WOL_FRAME0_CRC0 (0x30) /* WF0CRC0 */ +#define REG_WOL_FRAME0_CRC1 (0x32) /* WF0CRC1 */ +#define REG_WOL_FRAME0_BYTE_MASK0 (0x34) /* WF0BM0 */ +#define REG_WOL_FRAME0_BYTE_MASK1 (0x36) /* WF0BM1 */ +#define REG_WOL_FRAME0_BYTE_MASK2 (0x38) /* WF0BM2 */ +#define REG_WOL_FRAME0_BYTE_MASK3 (0x3A) /* WF0BM3 */ + +#define REG_WOL_FRAME1_CRC0 (0x40) /* WF1CRC0 */ +#define REG_WOL_FRAME1_CRC1 (0x42) /* WF1CRC1 */ +#define REG_WOL_FRAME1_BYTE_MASK0 (0x44) /* WF1BM0 */ +#define REG_WOL_FRAME1_BYTE_MASK1 (0x46) /* WF1BM1 */ +#define REG_WOL_FRAME1_BYTE_MASK2 (0x48) /* WF1BM2 */ +#define REG_WOL_FRAME1_BYTE_MASK3 (0x4A) /* WF1BM3 */ + +#define REG_WOL_FRAME2_CRC0 (0x50) /* WF2CRC0 */ +#define REG_WOL_FRAME2_CRC1 (0x52) /* WF2CRC1 */ +#define REG_WOL_FRAME2_BYTE_MASK0 (0x54) /* WF2BM0 */ +#define REG_WOL_FRAME2_BYTE_MASK1 (0x56) /* WF2BM1 */ +#define REG_WOL_FRAME2_BYTE_MASK2 (0x58) /* WF2BM2 */ +#define REG_WOL_FRAME2_BYTE_MASK3 (0x5A) /* WF2BM3 */ + +#define REG_WOL_FRAME3_CRC0 (0x60) /* WF3CRC0 */ +#define REG_WOL_FRAME3_CRC1 (0x62) /* WF3CRC1 */ +#define REG_WOL_FRAME3_BYTE_MASK0 (0x64) /* WF3BM0 */ +#define REG_WOL_FRAME3_BYTE_MASK1 (0x66) /* WF3BM1 */ +#define REG_WOL_FRAME3_BYTE_MASK2 (0x68) /* WF3BM2 */ +#define REG_WOL_FRAME3_BYTE_MASK3 (0x6A) /* WF3BM3 */ + +/* + * Transmit/Receive Control Registers + * (Offset 0x70 - 0x9F) + */ + +/* Transmit Frame Header */ +#define REG_QDR_DUMMY (0x00) /* Dummy address to access QMU RxQ, TxQ */ +#define TX_CTRL_INTERRUPT_ON (0x8000) /* Transmit Interrupt on Completion */ + +#define REG_TX_CTRL (0x70) /* TXCR */ +#define TX_CTRL_ICMP_CHECKSUM (0x0100) /* Enable ICMP frame checksum generation */ +#define TX_CTRL_UDP_CHECKSUM (0x0080) /* Enable UDP frame checksum generation */ +#define TX_CTRL_TCP_CHECKSUM (0x0040) /* Enable TCP frame checksum generation */ +#define TX_CTRL_IP_CHECKSUM (0x0020) /* Enable IP frame checksum generation */ +#define TX_CTRL_FLUSH_QUEUE (0x0010) /* Clear transmit queue, reset tx frame pointer */ +#define TX_CTRL_FLOW_ENABLE (0x0008) /* Enable transmit flow control */ +#define TX_CTRL_PAD_ENABLE (0x0004) /* Eanble adding a padding to a packet shorter than 64 bytes */ +#define TX_CTRL_CRC_ENABLE (0x0002) /* Enable adding a CRC to the end of transmit frame */ +#define TX_CTRL_ENABLE (0x0001) /* Enable tranmsit */ + +#define REG_TX_STATUS (0x72) /* TXSR */ +#define TX_STAT_LATE_COL (0x2000) /* Tranmsit late collision occurs */ +#define TX_STAT_MAX_COL (0x1000) /* Tranmsit maximum collision is reached */ +#define TX_FRAME_ID_MASK (0x003F) /* Transmit frame ID mask */ +#define TX_STAT_ERRORS ( TX_STAT_MAX_COL | TX_STAT_LATE_COL ) + +#define REG_RX_CTRL1 (0x74) /* RXCR1 */ +#define RX_CTRL_FLUSH_QUEUE (0x8000) /* Clear receive queue, reset rx frame pointer */ +#define RX_CTRL_UDP_CHECKSUM (0x4000) /* Enable UDP frame checksum verification */ +#define RX_CTRL_TCP_CHECKSUM (0x2000) /* Enable TCP frame checksum verification */ +#define RX_CTRL_IP_CHECKSUM (0x1000) /* Enable IP frame checksum verification */ +#define RX_CTRL_MAC_FILTER (0x0800) /* Receive with address that pass MAC address filtering */ +#define RX_CTRL_FLOW_ENABLE (0x0400) /* Enable receive flow control */ +#define RX_CTRL_BAD_PACKET (0x0200) /* Eanble receive CRC error frames */ +#define RX_CTRL_MULTICAST (0x0100) /* Receive multicast frames that pass the CRC hash filtering */ +#define RX_CTRL_BROADCAST (0x0080) /* Receive all the broadcast frames */ +#define RX_CTRL_ALL_MULTICAST (0x0040) /* Receive all the multicast frames (including broadcast frames) */ +#define RX_CTRL_UNICAST (0x0020) /* Receive unicast frames that match the device MAC address */ +#define RX_CTRL_PROMISCUOUS (0x0010) /* Receive all incoming frames, regardless of frame's DA */ +#define RX_CTRL_STRIP_CRC (0x0008) /* Enable strip CRC on the received frames */ +#define RX_CTRL_INVERSE_FILTER (0x0002) /* Receive with address check in inverse filtering mode */ +#define RX_CTRL_ENABLE (0x0001) /* Enable receive */ + +/* Address filtering scheme mask */ +#define RX_CTRL_FILTER_MASK ( RX_CTRL_INVERSE_FILTER | RX_CTRL_PROMISCUOUS | RX_CTRL_MULTICAST | RX_CTRL_MAC_FILTER ) + +#define REG_RX_CTRL2 (0x76) /* RXCR2 */ +#define RX_CTRL_IPV6_UDP_NOCHECKSUM (0x0010) /* No checksum generation and verification if IPv6 UDP is fragment */ +#define RX_CTRL_IPV6_UDP_CHECKSUM (0x0008) /* Receive pass IPv6 UDP frame with UDP checksum is zero */ +#define RX_CTRL_UDP_LITE_CHECKSUM (0x0004) /* Enable UDP Lite frame checksum generation and verification */ +#define RX_CTRL_ICMP_CHECKSUM (0x0002) /* Enable ICMP frame checksum verification */ +#define RX_CTRL_BLOCK_MAC (0x0001) /* Receive drop frame if the SA is same as device MAC address */ +#define RX_CTRL_BURST_LEN_MASK (0x00e0) /* SRDBL SPI Receive Data Burst Length */ +#define RX_CTRL_BURST_LEN_4 (0x0000) +#define RX_CTRL_BURST_LEN_8 (0x0020) +#define RX_CTRL_BURST_LEN_16 (0x0040) +#define RX_CTRL_BURST_LEN_32 (0x0060) +#define RX_CTRL_BURST_LEN_FRAME (0x0080) + +#define REG_TX_MEM_INFO (0x78) /* TXMIR */ +#define TX_MEM_AVAILABLE_MASK (0x1FFF) /* The amount of memory available in TXQ */ + +#define REG_RX_FHR_STATUS (0x7C) /* RXFHSR */ +#define RX_VALID (0x8000) /* Frame in the receive packet memory is valid */ +#define RX_ICMP_ERROR (0x2000) /* ICMP checksum field doesn't match */ +#define RX_IP_ERROR (0x1000) /* IP checksum field doesn't match */ +#define RX_TCP_ERROR (0x0800) /* TCP checksum field doesn't match */ +#define RX_UDP_ERROR (0x0400) /* UDP checksum field doesn't match */ +#define RX_BROADCAST (0x0080) /* Received frame is a broadcast frame */ +#define RX_MULTICAST (0x0040) /* Received frame is a multicast frame */ +#define RX_UNICAST (0x0020) /* Received frame is a unicast frame */ +#define RX_PHY_ERROR (0x0010) /* Received frame has runt error */ +#define RX_FRAME_ETHER (0x0008) /* Received frame is an Ethernet-type frame */ +#define RX_TOO_LONG (0x0004) /* Received frame length exceeds max size 0f 2048 bytes */ +#define RX_RUNT_ERROR (0x0002) /* Received frame was demaged by a collision */ +#define RX_BAD_CRC (0x0001) /* Received frame has a CRC error */ +#define RX_ERRORS ( RX_BAD_CRC | RX_TOO_LONG | RX_RUNT_ERROR | RX_PHY_ERROR | \ + RX_ICMP_ERROR | RX_IP_ERROR | RX_TCP_ERROR | RX_UDP_ERROR ) + +#define REG_RX_FHR_BYTE_CNT (0x7E) /* RXFHBCR */ +#define RX_BYTE_CNT_MASK (0x0FFF) /* Received frame byte size mask */ + +#define REG_TXQ_CMD (0x80) /* TXQCR */ +#define TXQ_AUTO_ENQUEUE (0x0004) /* Enable enqueue tx frames from tx buffer automatically */ +#define TXQ_MEM_AVAILABLE_INT (0x0002) /* Enable generate interrupt when tx memory is available */ +#define TXQ_ENQUEUE (0x0001) /* Enable enqueue tx frames one frame at a time */ + +#define REG_RXQ_CMD (0x82) /* RXQCR */ +#define RXQ_STAT_TIME_INT (0x1000) /* RX interrupt is occured by timer duration */ +#define RXQ_STAT_BYTE_CNT_INT (0x0800) /* RX interrupt is occured by byte count threshold */ +#define RXQ_STAT_FRAME_CNT_INT (0x0400) /* RX interrupt is occured by frame count threshold */ +#define RXQ_TWOBYTE_OFFSET (0x0200) /* Enable adding 2-byte before frame header for IP aligned with DWORD */ +#define RXQ_TIME_INT (0x0080) /* Enable RX interrupt by timer duration */ +#define RXQ_BYTE_CNT_INT (0x0040) /* Enable RX interrupt by byte count threshold */ +#define RXQ_FRAME_CNT_INT (0x0020) /* Enable RX interrupt by frame count threshold */ +#define RXQ_AUTO_DEQUEUE (0x0010) /* Enable release rx frames from rx buffer automatically */ +#define RXQ_START (0x0008) /* Start QMU transfer operation */ +#define RXQ_CMD_FREE_PACKET (0x0001) /* Manual dequeue (release the current frame from RxQ) */ + +#define RXQ_CMD_CNTL (RXQ_FRAME_CNT_INT|RXQ_AUTO_DEQUEUE) + +#define REG_TX_ADDR_PTR (0x84) /* TXFDPR */ +#define REG_RX_ADDR_PTR (0x86) /* RXFDPR */ +#define ADDR_PTR_AUTO_INC (0x4000) /* Enable Frame data pointer increments automatically */ +#define ADDR_PTR_MASK (0x03ff) /* Address pointer mask */ + +#define REG_RX_TIME_THRES (0x8C) /* RXDTTR */ +#define RX_TIME_THRESHOLD_MASK (0xFFFF) /* Set receive timer duration threshold */ + +#define REG_RX_BYTE_CNT_THRES (0x8E) /* RXDBCTR */ +#define RX_BYTE_THRESHOLD_MASK (0xFFFF) /* Set receive byte count threshold */ + +#define REG_INT_MASK (0x90) /* IER */ +#define INT_PHY (0x8000) /* Enable link change interrupt */ +#define INT_TX (0x4000) /* Enable transmit done interrupt */ +#define INT_RX (0x2000) /* Enable receive interrupt */ +#define INT_RX_OVERRUN (0x0800) /* Enable receive overrun interrupt */ +#define INT_TX_STOPPED (0x0200) /* Enable transmit process stopped interrupt */ +#define INT_RX_STOPPED (0x0100) /* Enable receive process stopped interrupt */ +#define INT_TX_SPACE (0x0040) /* Enable transmit space available interrupt */ +#define INT_RX_WOL_FRAME (0x0020) /* Enable WOL on receive wake-up frame detect interrupt */ +#define INT_RX_WOL_MAGIC (0x0010) /* Enable WOL on receive magic packet detect interrupt */ +#define INT_RX_WOL_LINKUP (0x0008) /* Enable WOL on link up detect interrupt */ +#define INT_RX_WOL_ENERGY (0x0004) /* Enable WOL on energy detect interrupt */ +#define INT_RX_SPI_ERROR (0x0002) /* Enable receive SPI bus error interrupt */ +#define INT_RX_WOL_DELAY_ENERGY (0x0001) /* Enable WOL on delay energy detect interrupt */ +#define INT_MASK ( INT_RX | INT_TX | INT_PHY ) + +#define REG_INT_STATUS (0x92) /* ISR */ + +#define REG_RX_FRAME_CNT_THRES (0x9C) /* RXFCTFC */ +#define RX_FRAME_CNT_MASK (0xFF00) /* Received frame count mask */ +#define RX_FRAME_THRESHOLD_MASK (0x00FF) /* Set receive frame count threshold mask */ + +#define REG_TX_TOTAL_FRAME_SIZE (0x9E) /* TXNTFSR */ +#define TX_TOTAL_FRAME_SIZE_MASK (0xFFFF) /* Set next total tx frame size mask */ + +/* + * MAC Address Hash Table Control Registers + * (Offset 0xA0 - 0xA7) + */ +#define REG_MAC_HASH_0 (0xA0) /* MAHTR0 */ +#define REG_MAC_HASH_1 (0xA1) + +#define REG_MAC_HASH_2 (0xA2) /* MAHTR1 */ +#define REG_MAC_HASH_3 (0xA3) + +#define REG_MAC_HASH_4 (0xA4) /* MAHTR2 */ +#define REG_MAC_HASH_5 (0xA5) + +#define REG_MAC_HASH_6 (0xA6) /* MAHTR3 */ +#define REG_MAC_HASH_7 (0xA7) + +/* + * QMU Receive Queue Watermark Control Registers + * (Offset 0xB0 - 0xB5) + */ +#define REG_RX_LOW_WATERMARK (0xB0) /* FCLWR */ +#define RX_LOW_WATERMARK_MASK (0x0FFF) /* Set QMU RxQ low watermark mask */ + +#define REG_RX_HIGH_WATERMARK (0xB2) /* FCHWR */ +#define RX_HIGH_WATERMARK_MASK (0x0FFF) /* Set QMU RxQ high watermark mask */ + +#define REG_RX_OVERRUN_WATERMARK (0xB4) /* FCOWR */ +#define RX_OVERRUN_WATERMARK_MASK (0x0FFF) /* Set QMU RxQ overrun watermark mask */ + +/* + * Global Control Registers + * (Offset 0xC0 - 0xD3) + */ +#define REG_CHIP_ID (0xC0) /* CIDER */ +#define CHIP_ID_MASK (0xFFF0) /* Family ID and chip ID mask */ +#define REVISION_MASK (0x000E) /* Chip revision mask */ +#define CHIP_ID_SHIFT (4) +#define REVISION_SHIFT (1) +#define CHIP_ID_8851_16 (0x8870) /* KS8851-16/32MQL chip ID */ + +#define REG_LED_CTRL (0xC6) /* CGCR */ +#define LED_CTRL_SEL1 (0x8000) /* Select LED3/LED2/LED1/LED0 indication */ +#define LED_CTRL_SEL0 (0x0200) /* Select LED3/LED2/LED1/LED0 indication */ + +#define REG_IND_IACR (0xC8) /* IACR */ +#define TABLE_READ (0x1000) /* Indirect read */ +#define TABLE_MIB (0x0C00) /* Select MIB counter table */ +#define TABLE_ENTRY_MASK (0x001F) /* Set table entry to access */ + +#define REG_IND_DATA_LOW (0xD0) /* IADLR */ +#define REG_IND_DATA_HIGH (0xD2) /* IADHR */ + +/* + * Power Management Control Registers + * (Offset 0xD4 - 0xD7) + */ +#define REG_POWER_CNTL (0xD4) /* PMECR */ +#define PME_DELAY_ENABLE (0x4000) /* Enable the PME output pin assertion delay */ +#define PME_ACTIVE_HIGHT (0x1000) /* PME output pin is active high */ +#define PME_FROM_WKFRAME (0x0800) /* PME asserted when wake-up frame is detected */ +#define PME_FROM_MAGIC (0x0400) /* PME asserted when magic packet is detected */ +#define PME_FROM_LINKUP (0x0200) /* PME asserted when link up is detected */ +#define PME_FROM_ENERGY (0x0100) /* PME asserted when energy is detected */ +#define PME_EVENT_MASK (0x0F00) /* PME asserted event mask */ +#define WAKEUP_AUTO_ENABLE (0x0080) /* Enable auto wake-up in energy mode */ +#define WAKEUP_NORMAL_AUTO_ENABLE (0x0040) /* Enable auto goto normal mode from energy detecion mode */ +#define WAKEUP_FROM_WKFRAME (0x0020) /* Wake-up from wake-up frame event detected */ +#define WAKEUP_FROM_MAGIC (0x0010) /* Wake-up from magic packet event detected */ +#define WAKEUP_FROM_LINKUP (0x0008) /* Wake-up from link up event detected */ +#define WAKEUP_FROM_ENERGY (0x0004) /* Wake-up from energy event detected */ +#define WAKEUP_EVENT_MASK (0x003C) /* Wake-up event mask */ +#define POWER_STATE_D1 (0x0003) /* Power saving mode */ +#define POWER_STATE_D3 (0x0002) /* Power down mode */ +#define POWER_STATE_D2 (0x0001) /* Power detection mode */ +#define POWER_STATE_D0 (0x0000) /* Normal operation mode (default) */ +#define POWER_STATE_MASK (0x0003) /* Power management mode mask */ + +#define REG_WAKEUP_TIME (0xD6) /* GSWUTR */ +#define WAKEUP_TIME (0xFF00) /* Min time (sec) wake-uo after detected energy */ +#define GOSLEEP_TIME (0x00FF) /* Min time (sec) before goto sleep when in energy mode */ + +/* + * PHY Control Registers + * (Offset 0xD8 - 0xF9) + */ +#define REG_PHY_RESET (0xD8) /* PHYRR */ +#define PHY_RESET (0x0001) /* Reset PHY */ + +#define REG_PHY_CNTL (0xE4) /* P1MBCR */ +#define PHY_SPEED_100MBIT (0x2000) /* Force PHY 100Mbps */ +#define PHY_AUTO_NEG_ENABLE (0x1000) /* Enable PHY auto-negotiation */ +#define PHY_POWER_DOWN (0x0800) /* Set PHY power-down */ +#define PHY_AUTO_NEG_RESTART (0x0200) /* Restart PHY auto-negotiation */ +#define PHY_FULL_DUPLEX (0x0100) /* Force PHY in full duplex mode */ +#define PHY_HP_MDIX (0x0020) /* Set PHY in HP auto MDI-X mode */ +#define PHY_FORCE_MDIX (0x0010) /* Force MDI-X */ +#define PHY_AUTO_MDIX_DISABLE (0x0008) /* Disable auto MDI-X */ +#define PHY_TRANSMIT_DISABLE (0x0002) /* Disable PHY transmit */ +#define PHY_LED_DISABLE (0x0001) /* Disable PHY LED */ + +#define REG_PHY_STATUS (0xE6) /* P1MBSR */ +#define PHY_100BT4_CAPABLE (0x8000) /* 100 BASE-T4 capable */ +#define PHY_100BTX_FD_CAPABLE (0x4000) /* 100BASE-TX full duplex capable */ +#define PHY_100BTX_CAPABLE (0x2000) /* 100BASE-TX half duplex capable */ +#define PHY_10BT_FD_CAPABLE (0x1000) /* 10BASE-TX full duplex capable */ +#define PHY_10BT_CAPABLE (0x0800) /* 10BASE-TX half duplex capable */ +#define PHY_AUTO_NEG_ACKNOWLEDGE (0x0020) /* Auto-negotiation complete */ +#define PHY_AUTO_NEG_CAPABLE (0x0008) /* Auto-negotiation capable */ +#define PHY_LINK_UP (0x0004) /* PHY link is up */ +#define PHY_EXTENDED_CAPABILITY (0x0001) /* PHY extended register capable */ + +#define REG_PHY_ID_LOW (0xE8) /* PHY1ILR */ +#define REG_PHY_ID_HIGH (0xEA) /* PHY1IHR */ + +#define REG_PHY_AUTO_NEGOTIATION (0xEC) /* P1ANAR */ +#define PHY_AUTO_NEG_SYM_PAUSE (0x0400) /* Advertise pause capability */ +#define PHY_AUTO_NEG_100BTX_FD (0x0100) /* Advertise 100 full-duplex capability */ +#define PHY_AUTO_NEG_100BTX (0x0080) /* Advertise 100 half-duplex capability */ +#define PHY_AUTO_NEG_10BT_FD (0x0040) /* Advertise 10 full-duplex capability */ +#define PHY_AUTO_NEG_10BT (0x0020) /* Advertise 10 half-duplex capability */ +#define PHY_AUTO_NEG_SELECTOR (0x001F) /* Selector field mask */ +#define PHY_AUTO_NEG_802_3 (0x0001) /* 802.3 */ + +#define REG_PHY_REMOTE_CAPABILITY (0xEE) /* P1ANLPR */ +#define PHY_REMOTE_SYM_PAUSE (0x0400) /* Link partner pause capability */ +#define PHY_REMOTE_100BTX_FD (0x0100) /* Link partner 100 full-duplex capability */ +#define PHY_REMOTE_100BTX (0x0080) /* Link partner 100 half-duplex capability */ +#define PHY_REMOTE_10BT_FD (0x0040) /* Link partner 10 full-duplex capability */ +#define PHY_REMOTE_10BT (0x0020) /* Link partner 10 half-duplex capability */ + +#define REG_PORT_LINK_MD (0xF4) /* P1SCLMD */ +#define PORT_CABLE_10M_SHORT (0x8000) /* Cable length is less than 10m short */ +#define PORT_CABLE_STAT_FAILED (0x6000) /* Cable diagnostic test fail */ +#define PORT_CABLE_STAT_SHORT (0x4000) /* Short condition detected in the cable */ +#define PORT_CABLE_STAT_OPEN (0x2000) /* Open condition detected in the cable */ +#define PORT_CABLE_STAT_NORMAL (0x0000) /* Normal condition */ +#define PORT_CABLE_DIAG_RESULT (0x6000) /* Cable diagnostic test result mask */ +#define PORT_START_CABLE_DIAG (0x1000) /* Enable cable diagnostic test */ +#define PORT_FORCE_LINK (0x0800) /* Enable force link pass */ +#define PORT_POWER_SAVING (0x0400) /* Disable power saving */ +#define PORT_REMOTE_LOOPBACK (0x0200) /* Enable remote loopback at PHY */ +#define PORT_CABLE_FAULT_COUNTER (0x01FF) /* Cable length distance to the fault */ + +#define REG_PORT_CTRL (0xF6) /* P1CR */ +#define PORT_LED_OFF (0x8000) /* Turn off all the port LEDs (LED3/LED2/LED1/LED0) */ +#define PORT_TX_DISABLE (0x4000) /* Disable port transmit */ +#define PORT_AUTO_NEG_RESTART (0x2000) /* Restart auto-negotiation */ +#define PORT_POWER_DOWN (0x0800) /* Set port power-down */ +#define PORT_AUTO_MDIX_DISABLE (0x0400) /* Disable auto MDI-X */ +#define PORT_FORCE_MDIX (0x0200) /* Force MDI-X */ +#define PORT_AUTO_NEG_ENABLE (0x0080) /* Enable auto-negotiation */ +#define PORT_FORCE_100_MBIT (0x0040) /* Force PHY 100Mbps */ +#define PORT_FORCE_FULL_DUPLEX (0x0020) /* Force PHY in full duplex mode */ +#define PORT_AUTO_NEG_SYM_PAUSE (0x0010) /* Advertise pause capability */ +#define PORT_AUTO_NEG_100BTX_FD (0x0008) /* Advertise 100 full-duplex capability */ +#define PORT_AUTO_NEG_100BTX (0x0004) /* Advertise 100 half-duplex capability */ +#define PORT_AUTO_NEG_10BT_FD (0x0002) /* Advertise 10 full-duplex capability */ +#define PORT_AUTO_NEG_10BT (0x0001) /* Advertise 10 half-duplex capability */ + +#define REG_PORT_STATUS (0xF8) /* P1SR */ +#define PORT_HP_MDIX (0x8000) /* Set PHY in HP auto MDI-X mode */ +#define PORT_REVERSED_POLARITY (0x2000) /* Polarity is reversed */ +#define PORT_RX_FLOW_CTRL (0x1000) /* Reeive flow control feature is active */ +#define PORT_TX_FLOW_CTRL (0x0800) /* Transmit flow control feature is active */ +#define PORT_STAT_SPEED_100MBIT (0x0400) /* Link is 100Mbps */ +#define PORT_STAT_FULL_DUPLEX (0x0200) /* Link is full duplex mode */ +#define PORT_MDIX_STATUS (0x0080) /* Is MDI */ +#define PORT_AUTO_NEG_COMPLETE (0x0040) /* Auto-negotiation complete */ +#define PORT_STATUS_LINK_GOOD (0x0020) /* PHY link is up */ +#define PORT_REMOTE_SYM_PAUSE (0x0010) /* Link partner pause capability */ +#define PORT_REMOTE_100BTX_FD (0x0008) /* Link partner 100 full-duplex capability */ +#define PORT_REMOTE_100BTX (0x0004) /* Link partner 100 half-duplex capability */ +#define PORT_REMOTE_10BT_FD (0x0002) /* Link partner 10 full-duplex capability */ +#define PORT_REMOTE_10BT (0x0001) /* Link partner 10 half-duplex capability */ + +#endif /* KSZ8851SNL_REG_H_INCLUDED */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/readme.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/readme.txt new file mode 100644 index 0000000..a90fb9e --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/readme.txt @@ -0,0 +1,18 @@ +Contains the files that implement FreeRTOS+TCP. + +User documentation, including an API reference is available on: +http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/ + +A description of the source code organisation is available on: +http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/TCP_Networking_Tutorial.html + +The porting guide is available on: +http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/FreeRTOS_TCP_Porting.html + +License information is available on: +http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/FreeRTOS_Plus_TCP_License.html + +At this time it is recommended to use BufferAllocation_2.c in which case it is +essential to use the heap_4.c memory allocation scheme: +http://www.FreeRTOS.org/a00111.html + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/Include/trcHardwarePort.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/Include/trcHardwarePort.h new file mode 100644 index 0000000..6bd981c --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/Include/trcHardwarePort.h @@ -0,0 +1,478 @@ +/******************************************************************************* + * Trace Recorder Library for Tracealyzer v4.1.5 + * Percepio AB, www.percepio.com + * + * trcHardwarePort.h + * + * The hardware abstraction layer for the trace recorder. + * + * Terms of Use + * This file is part of the trace recorder library (RECORDER), which is the + * intellectual property of Percepio AB (PERCEPIO) and provided under a + * license as follows. + * The RECORDER may be used free of charge for the purpose of recording data + * intended for analysis in PERCEPIO products. It may not be used or modified + * for other purposes without explicit permission from PERCEPIO. + * You may distribute the RECORDER in its original source code form, assuming + * this text (terms of use, disclaimer, copyright notice) is unchanged. You are + * allowed to distribute the RECORDER with minor modifications intended for + * configuration or porting of the RECORDER, e.g., to allow using it on a + * specific processor, processor family or with a specific communication + * interface. Any such modifications should be documented directly below + * this comment block. + * + * Disclaimer + * The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty + * as to its use or performance. PERCEPIO does not and cannot warrant the + * performance or results you may obtain by using the RECORDER or documentation. + * PERCEPIO make no warranties, express or implied, as to noninfringement of + * third party rights, merchantability, or fitness for any particular purpose. + * In no event will PERCEPIO, its technology partners, or distributors be liable + * to you for any consequential, incidental or special damages, including any + * lost profits or lost savings, even if a representative of PERCEPIO has been + * advised of the possibility of such damages, or for any claim by any third + * party. Some jurisdictions do not allow the exclusion or limitation of + * incidental, consequential or special damages, or the exclusion of implied + * warranties or limitations on how long an implied warranty may last, so the + * above limitations may not apply to you. + * + * Tabs are used for indent in this file (1 tab = 4 spaces) + * + * Copyright Percepio AB, 2018. + * www.percepio.com + ******************************************************************************/ + +#ifndef TRC_HARDWARE_PORT_H +#define TRC_HARDWARE_PORT_H + +#include "trcPortDefines.h" + + +#if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_NOT_SET) + #error "TRC_CFG_HARDWARE_PORT not selected - see trcConfig.h" +#endif + +/******************************************************************************* + * TRC_IRQ_PRIORITY_ORDER + * + * Macro which should be defined as an integer of 0 or 1. + * + * This should be 0 if lower IRQ priority values implies higher priority + * levels, such as on ARM Cortex M. If the opposite scheme is used, i.e., + * if higher IRQ priority values means higher priority, this should be 1. + * + * This setting is not critical. It is used only to sort and colorize the + * interrupts in priority order, in case you record interrupts using + * the vTraceStoreISRBegin and vTraceStoreISREnd routines. + * + ****************************************************************************** + * + * HWTC Macros + * + * These macros provides a hardware isolation layer representing the + * hardware timer/counter used for the event timestamping. + * + * TRC_HWTC_COUNT: How to read the current value of the timer/counter. + * + * TRC_HWTC_TYPE: Tells the type of timer/counter used for TRC_HWTC_COUNT: + * + * - TRC_FREE_RUNNING_32BIT_INCR: + * Free-running 32-bit timer/counter, counting upwards from 0. + * + * - TRC_FREE_RUNNING_32BIT_DECR + * Free-running 32-bit timer/counter, counting downwards from 0xFFFFFFFF. + * + * - TRC_OS_TIMER_INCR + * Periodic timer that drives the OS tick interrupt, counting upwards + * from 0 until (TRC_HWTC_PERIOD-1). + * + * - TRC_OS_TIMER_DECR + * Periodic timer that drives the OS tick interrupt, counting downwards + * from TRC_HWTC_PERIOD-1 until 0. + * + * - TRC_CUSTOM_TIMER_INCR + * A custom timer or counter independent of the OS tick, counting + * downwards from TRC_HWTC_PERIOD-1 until 0. (Currently only supported + * in streaming mode). + * + * - TRC_CUSTOM_TIMER_DECR + * A custom timer independent of the OS tick, counting downwards + * from TRC_HWTC_PERIOD-1 until 0. (Currently only supported + * in streaming mode). + * + * TRC_HWTC_PERIOD: The number of HWTC_COUNT ticks until the timer wraps + * around. If using TRC_FREE_RUNNING_32BIT_INCR/DECR, this should be 0. + * + * TRC_HWTC_FREQ_HZ: The clock rate of the TRC_HWTC_COUNT counter in Hz. If using + * TRC_OS_TIMER_INCR/DECR, this is should be TRC_HWTC_PERIOD * TRACE_TICK_RATE_HZ. + * If using a free-running timer, this is often TRACE_CPU_CLOCK_HZ (if running at + * the core clock rate). If using TRC_CUSTOM_TIMER_INCR/DECR, this should match + * the clock rate of your custom timer (i.e., TRC_HWTC_COUNT). If the default value + * of TRC_HWTC_FREQ_HZ is incorrect for your setup, you can override it by calling + * vTraceSetFrequency before calling vTraceEnable. + * + * TRC_HWTC_DIVISOR (used in snapshot mode only): + * In snapshot mode, the timestamp resolution is TRC_HWTC_FREQ_HZ/TRC_HWTC_DIVISOR. + * If the timer frequency is very high (hundreds of MHz), we recommend increasing + * the TRC_HWTC_DIVISOR prescaler, to reduce the bandwidth needed to store + * timestamps. This since extra "XTS" events are inserted if the time since the + * previous event exceeds a certain limit (255 or 65535 depending on event type). + * It is advised to keep the time between most events below 65535 native ticks + * (after division by TRC_HWTC_DIVISOR) to avoid frequent XTS events. + ******************************************************************************/ + +#if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_NOT_SET) + #error "TRC_CFG_HARDWARE_PORT not selected - see trcConfig.h" +#endif + +#if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Win32) + /* This can be used as a template for any free-running 32-bit counter */ + #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR + #define TRC_HWTC_COUNT (ulGetRunTimeCounterValue()) + #define TRC_HWTC_PERIOD 0 + #define TRC_HWTC_DIVISOR 1 + #define TRC_HWTC_FREQ_HZ 100000 + + #define TRC_IRQ_PRIORITY_ORDER 1 + + #define TRC_PORT_SPECIFIC_INIT() + +#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_HWIndependent) + /* Timestamping by OS tick only (typically 1 ms resolution) */ + #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR + #define TRC_HWTC_COUNT 0 + #define TRC_HWTC_PERIOD 1 + #define TRC_HWTC_DIVISOR 1 + #define TRC_HWTC_FREQ_HZ TRACE_TICK_RATE_HZ + + /* Set the meaning of IRQ priorities in ISR tracing - see above */ + #define TRC_IRQ_PRIORITY_ORDER NOT_SET + +#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_Cortex_M) + + #ifndef __CORTEX_M + #error "Can't find the CMSIS API. Please include your processor's header file in trcConfig.h" + #endif + + /************************************************************************** + * For Cortex-M3, M4 and M7, the DWT cycle counter is used for timestamping. + * For Cortex-M0 and M0+, the SysTick timer is used since DWT is not + * available. Systick timestamping can also be forced on Cortex-M3, M4 and + * M7 by defining the preprocessor directive TRC_CFG_ARM_CM_USE_SYSTICK, + * either directly below or in trcConfig.h. + * + * #define TRC_CFG_ARM_CM_USE_SYSTICK + **************************************************************************/ + + #if ((__CORTEX_M >= 0x03) && (! defined TRC_CFG_ARM_CM_USE_SYSTICK)) + + void prvTraceInitCortexM(void); + + #define TRC_REG_DEMCR (*(volatile uint32_t*)0xE000EDFC) + #define TRC_REG_DWT_CTRL (*(volatile uint32_t*)0xE0001000) + #define TRC_REG_DWT_CYCCNT (*(volatile uint32_t*)0xE0001004) + #define TRC_REG_DWT_EXCCNT (*(volatile uint32_t*)0xE000100C) + + #define TRC_REG_ITM_LOCKACCESS (*(volatile uint32_t*)0xE0001FB0) + #define TRC_ITM_LOCKACCESS_UNLOCK (0xC5ACCE55) + + /* Bit mask for TRCENA bit in DEMCR - Global enable for DWT and ITM */ + #define TRC_DEMCR_TRCENA (1 << 24) + + /* Bit mask for NOPRFCNT bit in DWT_CTRL. If 1, DWT_EXCCNT is not supported */ + #define TRC_DWT_CTRL_NOPRFCNT (1 << 24) + + /* Bit mask for NOCYCCNT bit in DWT_CTRL. If 1, DWT_CYCCNT is not supported */ + #define TRC_DWT_CTRL_NOCYCCNT (1 << 25) + + /* Bit mask for EXCEVTENA_ bit in DWT_CTRL. Set to 1 to enable DWT_EXCCNT */ + #define TRC_DWT_CTRL_EXCEVTENA (1 << 18) + + /* Bit mask for EXCEVTENA_ bit in DWT_CTRL. Set to 1 to enable DWT_CYCCNT */ + #define TRC_DWT_CTRL_CYCCNTENA (1) + + #define TRC_PORT_SPECIFIC_INIT() prvTraceInitCortexM() + + #define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR + #define TRC_HWTC_COUNT TRC_REG_DWT_CYCCNT + #define TRC_HWTC_PERIOD 0 + #define TRC_HWTC_DIVISOR 4 + #define TRC_HWTC_FREQ_HZ TRACE_CPU_CLOCK_HZ + #define TRC_IRQ_PRIORITY_ORDER 0 + + #else + + #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR + #define TRC_HWTC_COUNT (*((volatile uint32_t*)0xE000E018)) + #define TRC_HWTC_PERIOD ((*((volatile uint32_t*)0xE000E014)) + 1) + #define TRC_HWTC_DIVISOR 4 + #define TRC_HWTC_FREQ_HZ TRACE_CPU_CLOCK_HZ + #define TRC_IRQ_PRIORITY_ORDER 0 + + #endif + +#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Renesas_RX600) + + #include "iodefine.h" + + #if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING) + + #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR + #define TRC_HWTC_COUNT (CMT0.CMCNT) + + #elif (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_SNAPSHOT) + + /* Decreasing counters better for Tickless Idle? */ + #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR + #define TRC_HWTC_COUNT (CMT0.CMCOR - CMT0.CMCNT) + + #endif + + #define TRC_HWTC_PERIOD (CMT0.CMCOR + 1) + #define TRC_HWTC_DIVISOR 1 + #define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD) + #define TRC_IRQ_PRIORITY_ORDER 1 + +#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_MICROCHIP_PIC24_PIC32) + + #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR + #define TRC_HWTC_COUNT (TMR1) + #define TRC_HWTC_PERIOD (PR1 + 1) + #define TRC_HWTC_DIVISOR 1 + #define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD) + #define TRC_IRQ_PRIORITY_ORDER 0 + +#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_TEXAS_INSTRUMENTS_TMS570_RM48) + + #define TRC_RTIFRC0 *((uint32_t *)0xFFFFFC10) + #define TRC_RTICOMP0 *((uint32_t *)0xFFFFFC50) + #define TRC_RTIUDCP0 *((uint32_t *)0xFFFFFC54) + + #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR + #define TRC_HWTC_COUNT (TRC_RTIFRC0 - (TRC_RTICOMP0 - TRC_RTIUDCP0)) + #define TRC_HWTC_PERIOD (TRC_RTIUDCP0) + #define TRC_HWTC_DIVISOR 1 + #define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD) + #define TRC_IRQ_PRIORITY_ORDER 0 + +#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Atmel_AT91SAM7) + + /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */ + + #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR + #define TRC_HWTC_COUNT ((uint32_t)(AT91C_BASE_PITC->PITC_PIIR & 0xFFFFF)) + #define TRC_HWTC_PERIOD ((uint32_t)(AT91C_BASE_PITC->PITC_PIMR + 1)) + #define TRC_HWTC_DIVISOR 1 + #define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD) + #define TRC_IRQ_PRIORITY_ORDER 1 + +#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Atmel_UC3A0) + + /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO*/ + + /* For Atmel AVR32 (AT32UC3A) */ + + #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR + #define TRC_HWTC_COUNT ((uint32_t)sysreg_read(AVR32_COUNT)) + #define TRC_HWTC_PERIOD ((uint32_t)(sysreg_read(AVR32_COMPARE) + 1)) + #define TRC_HWTC_DIVISOR 1 + #define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD) + #define TRC_IRQ_PRIORITY_ORDER 1 + +#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_NXP_LPC210X) + + /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */ + + /* Tested with LPC2106, but should work with most LPC21XX chips. */ + + #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR + #define TRC_HWTC_COUNT *((uint32_t *)0xE0004008 ) + #define TRC_HWTC_PERIOD *((uint32_t *)0xE0004018 ) + #define TRC_HWTC_DIVISOR 1 + #define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD) + #define TRC_IRQ_PRIORITY_ORDER 0 + +#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_TEXAS_INSTRUMENTS_MSP430) + + /* UNOFFICIAL PORT - NOT YET VERIFIED */ + + #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR + #define TRC_HWTC_COUNT (TA0R) + #define TRC_HWTC_PERIOD (((uint16_t)TACCR0)+1) + #define TRC_HWTC_DIVISOR 1 + #define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD) + #define TRC_IRQ_PRIORITY_ORDER 1 + +#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_PPC405) + + /* UNOFFICIAL PORT - NOT YET VERIFIED */ + + #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR + #define TRC_HWTC_COUNT mfspr(0x3db) + #define TRC_HWTC_PERIOD (TRACE_CPU_CLOCK_HZ / TRACE_TICK_RATE_HZ) + #define TRC_HWTC_DIVISOR 1 + #define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD) + #define TRC_IRQ_PRIORITY_ORDER 0 + +#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_PPC440) + + /* UNOFFICIAL PORT */ + + /* This should work with most PowerPC chips */ + + #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR + #define TRC_HWTC_COUNT mfspr(0x016) + #define TRC_HWTC_PERIOD (TRACE_CPU_CLOCK_HZ / TRACE_TICK_RATE_HZ) + #define TRC_HWTC_DIVISOR 1 + #define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD) + #define TRC_IRQ_PRIORITY_ORDER 0 + +#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_MICROBLAZE) + + /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */ + + /* This should work with most Microblaze configurations. + * It uses the AXI Timer 0 - the tick interrupt source. + * If an AXI Timer 0 peripheral is available on your hardware platform, no modifications are required. + */ + #include "xtmrctr_l.h" + + #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR + #define TRC_HWTC_COUNT XTmrCtr_GetTimerCounterReg( XPAR_TMRCTR_0_BASEADDR, 0 ) + #define TRC_HWTC_PERIOD (XTmrCtr_mGetLoadReg( XPAR_TMRCTR_0_BASEADDR, 0) + 1) + #define TRC_HWTC_DIVISOR 16 + #define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD) + #define TRC_IRQ_PRIORITY_ORDER 0 + +#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Altera_NiosII) + + /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */ + + #include "system.h" + #include "sys/alt_timestamp.h" + + #define TRC_HWTC_TYPE TRC_OS_TIMER_INCR + #define TRC_HWTC_COUNT (uint32_t)alt_timestamp() + #define TRC_HWTC_PERIOD 0xFFFFFFFF + #define TRC_HWTC_FREQ_HZ TIMESTAMP_TIMER_FREQ + #define TRC_HWTC_DIVISOR 1 + #define TRC_IRQ_PRIORITY_ORDER 0 + +#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_CORTEX_A9) + + /* INPUT YOUR PERIPHERAL BASE ADDRESS HERE */ + #define TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS 0xSOMETHING + + #define TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET 0x0600 + #define TRC_CA9_MPCORE_PRIVCTR_PERIOD_REG (*(volatile uint32_t*)(TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x00)) + #define TRC_CA9_MPCORE_PRIVCTR_COUNTER_REG (*(volatile uint32_t*)(TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x04)) + #define TRC_CA9_MPCORE_PRIVCTR_CONTROL_REG (*(volatile uint32_t*)(TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x08)) + + #define TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK 0x0000FF00 + #define TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT 8 + #define TRC_CA9_MPCORE_PRIVCTR_PRESCALER (((TRC_CA9_MPCORE_PRIVCTR_CONTROL_REG & TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK) >> TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT) + 1) + + #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR + #define TRC_HWTC_COUNT TRC_CA9_MPCORE_PRIVCTR_COUNTER_REG + #define TRC_HWTC_PERIOD (TRC_CA9_MPCORE_PRIVCTR_PERIOD_REG + 1) + + /**************************************************************************************** + NOTE: The private timer ticks with a very high frequency (half the core-clock usually), + depending on the prescaler used. If a low prescaler is used, the number of HW ticks between + the trace events gets large, and thereby inefficient to store (sometimes extra events are + needed). To improve efficiency, you may use the TRC_HWTC_DIVISOR as an additional prescaler. + *****************************************************************************************/ + #define TRC_HWTC_DIVISOR 1 + + #define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD) + #define TRC_IRQ_PRIORITY_ORDER 0 + +#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_POWERPC_Z4) + + /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */ + + #define TRC_HWTC_TYPE TRC_OS_TIMER_DECR + //#define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING + #define TRC_HWTC_COUNT PIT.TIMER[configTICK_PIT_CHANNEL].CVAL.R // must be the PIT channel used for the systick + #define TRC_HWTC_PERIOD ((configPIT_CLOCK_HZ / configTICK_RATE_HZ) - 1U) // TODO FIXME or maybe not -1? what's the right "period" value? + #define TRC_HWTC_FREQ_HZ configPIT_CLOCK_HZ + #define TRC_HWTC_DIVISOR 1 + #define TRC_IRQ_PRIORITY_ORDER 1 // higher IRQ priority values are more significant + +#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_APPLICATION_DEFINED) + + #if !( defined (TRC_HWTC_TYPE) && defined (TRC_HWTC_COUNT) && defined (TRC_HWTC_PERIOD) && defined (TRC_HWTC_FREQ_HZ) && defined (TRC_IRQ_PRIORITY_ORDER) ) + #error "The hardware port is not completely defined!" + #endif + +#elif (TRC_CFG_HARDWARE_PORT != TRC_HARDWARE_PORT_NOT_SET) + + #error "TRC_CFG_HARDWARE_PORT had unsupported value!" + #define TRC_CFG_HARDWARE_PORT TRC_HARDWARE_PORT_NOT_SET + +#endif + +#ifndef TRC_HWTC_DIVISOR + #define TRC_HWTC_DIVISOR 1 +#endif + +#ifndef TRC_PORT_SPECIFIC_INIT + #define TRC_PORT_SPECIFIC_INIT() +#endif + +/* If Win32 port */ +#ifdef WIN32 + + #undef _WIN32_WINNT + #define _WIN32_WINNT 0x0600 + + /* Standard includes. */ + #include + #include + #include + + /*************************************************************************** + * The Win32 port by default saves the trace to file and then kills the + * program when the recorder is stopped, to facilitate quick, simple tests + * of the recorder. + ***************************************************************************/ + #define WIN32_PORT_SAVE_WHEN_STOPPED 1 + #define WIN32_PORT_EXIT_WHEN_STOPPED 1 + +#endif + +#if (TRC_CFG_HARDWARE_PORT != TRC_HARDWARE_PORT_NOT_SET) + + #ifndef TRC_HWTC_TYPE + #error "TRC_HWTC_TYPE is not set!" + #endif + + #ifndef TRC_HWTC_COUNT + #error "TRC_HWTC_COUNT is not set!" + #endif + + #ifndef TRC_HWTC_PERIOD + #error "TRC_HWTC_PERIOD is not set!" + #endif + + #ifndef TRC_HWTC_DIVISOR + #error "TRC_HWTC_DIVISOR is not set!" + #endif + + #ifndef TRC_IRQ_PRIORITY_ORDER + #error "TRC_IRQ_PRIORITY_ORDER is not set!" + #elif (TRC_IRQ_PRIORITY_ORDER != 0) && (TRC_IRQ_PRIORITY_ORDER != 1) + #error "TRC_IRQ_PRIORITY_ORDER has bad value!" + #endif + + #if (TRC_HWTC_DIVISOR < 1) + #error "TRC_HWTC_DIVISOR must be a non-zero positive value!" + #endif + + #ifndef TRC_HWTC_FREQ_HZ + #error "TRC_HWTC_FREQ_HZ not defined!" + #endif + +#endif + +#endif /*TRC_SNAPSHOT_HARDWARE_PORT_H*/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/Include/trcKernelPort.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/Include/trcKernelPort.h new file mode 100644 index 0000000..a7ba816 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/Include/trcKernelPort.h @@ -0,0 +1,2565 @@ +/******************************************************************************* + * Trace Recorder Library for Tracealyzer v4.1.5 + * Percepio AB, www.percepio.com + * + * Terms of Use + * This file is part of the trace recorder library (RECORDER), which is the + * intellectual property of Percepio AB (PERCEPIO) and provided under a + * license as follows. + * The RECORDER may be used free of charge for the purpose of recording data + * intended for analysis in PERCEPIO products. It may not be used or modified + * for other purposes without explicit permission from PERCEPIO. + * You may distribute the RECORDER in its original source code form, assuming + * this text (terms of use, disclaimer, copyright notice) is unchanged. You are + * allowed to distribute the RECORDER with minor modifications intended for + * configuration or porting of the RECORDER, e.g., to allow using it on a + * specific processor, processor family or with a specific communication + * interface. Any such modifications should be documented directly below + * this comment block. + * + * Disclaimer + * The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty + * as to its use or performance. PERCEPIO does not and cannot warrant the + * performance or results you may obtain by using the RECORDER or documentation. + * PERCEPIO make no warranties, express or implied, as to noninfringement of + * third party rights, merchantability, or fitness for any particular purpose. + * In no event will PERCEPIO, its technology partners, or distributors be liable + * to you for any consequential, incidental or special damages, including any + * lost profits or lost savings, even if a representative of PERCEPIO has been + * advised of the possibility of such damages, or for any claim by any third + * party. Some jurisdictions do not allow the exclusion or limitation of + * incidental, consequential or special damages, or the exclusion of implied + * warranties or limitations on how long an implied warranty may last, so the + * above limitations may not apply to you. + * + * FreeRTOS-specific definitions needed by the trace recorder + * + * + * + * Tabs are used for indent in this file (1 tab = 4 spaces) + * + * Copyright Percepio AB, 2018. + * www.percepio.com + ******************************************************************************/ + +#ifndef TRC_KERNEL_PORT_H +#define TRC_KERNEL_PORT_H + +#include "FreeRTOS.h" /* Defines configUSE_TRACE_FACILITY */ +#include "trcPortDefines.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define TRC_USE_TRACEALYZER_RECORDER configUSE_TRACE_FACILITY + +/*** FreeRTOS version codes **************************************************/ +#define FREERTOS_VERSION_NOT_SET 0 +#define TRC_FREERTOS_VERSION_7_3 1 /* v7.3 is earliest supported.*/ +#define TRC_FREERTOS_VERSION_7_4 2 +#define TRC_FREERTOS_VERSION_7_5_OR_7_6 3 +#define TRC_FREERTOS_VERSION_8_X 4 /* Any v8.x.x*/ +#define TRC_FREERTOS_VERSION_9_0_0 5 +#define TRC_FREERTOS_VERSION_9_0_1 6 +#define TRC_FREERTOS_VERSION_9_0_2 7 +#define TRC_FREERTOS_VERSION_10_0_0 8 /* If using FreeRTOS v10.0.0 or later version */ + +#define TRC_FREERTOS_VERSION_9_X 42 /* Not allowed anymore */ + +#if (TRC_CFG_FREERTOS_VERSION == TRC_FREERTOS_VERSION_9_X) +/* This setting for TRC_CFG_FREERTOS_VERSION is no longer allowed as v9.0.1 needs special handling. */ +#error "Please specify your exact FreeRTOS version in trcConfig.h, from the options listed above." +#endif + +#if (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) +#define prvGetStreamBufferType(x) ((( StreamBuffer_t * )x )->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER) +#else +#define prvGetStreamBufferType(x) 0 +#endif + +/* Added mainly for our internal testing. This makes it easier to create test applications that + runs on multiple FreeRTOS versions. */ +#if (TRC_CFG_FREERTOS_VERSION < TRC_FREERTOS_VERSION_8_X) + /* FreeRTOS v7.0 and later */ + #define STRING_CAST(x) ( (signed char*) x ) + #define TickType portTickType +#else + /* FreeRTOS v8.0 and later */ + #define STRING_CAST(x) x + #define TickType TickType_t +#endif + +#if (defined(TRC_USE_TRACEALYZER_RECORDER)) && (TRC_USE_TRACEALYZER_RECORDER == 1) + +/******************************************************************************* + * INCLUDE_xTaskGetCurrentTaskHandle must be set to 1 for tracing to work properly + ******************************************************************************/ +#undef INCLUDE_xTaskGetCurrentTaskHandle +#define INCLUDE_xTaskGetCurrentTaskHandle 1 + +#if (TRC_CFG_SCHEDULING_ONLY == 0) +/******************************************************************************* + * vTraceSetQueueName(void* object, const char* name) + * + * Parameter object: pointer to the Queue that shall be named + * Parameter name: the name to set (const string literal) + * + * Sets a name for Queue objects for display in Tracealyzer. + ******************************************************************************/ +void vTraceSetQueueName(void* object, const char* name); + +/******************************************************************************* + * vTraceSetSemaphoreName(void* object, const char* name) + * + * Parameter object: pointer to the Semaphore that shall be named + * Parameter name: the name to set (const string literal) + * + * Sets a name for Semaphore objects for display in Tracealyzer. + ******************************************************************************/ +void vTraceSetSemaphoreName(void* object, const char* name); + +/******************************************************************************* + * vTraceSetMutexName(void* object, const char* name) + * + * Parameter object: pointer to the Mutex that shall be named + * Parameter name: the name to set (const string literal) + * + * Sets a name for Semaphore objects for display in Tracealyzer. + ******************************************************************************/ +void vTraceSetMutexName(void* object, const char* name); + +#if (TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS == 1) +/******************************************************************************* +* vTraceSetEventGroupName(void* object, const char* name) +* +* Parameter object: pointer to the EventGroup that shall be named +* Parameter name: the name to set (const string literal) +* +* Sets a name for EventGroup objects for display in Tracealyzer. +******************************************************************************/ +void vTraceSetEventGroupName(void* object, const char* name); +#else /* (TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS == 1) */ +#define vTraceSetEventGroupName(object, name) /* Do nothing */ +#endif /* (TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS == 1) */ + +#if (TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS == 1) +/******************************************************************************* +* vTraceSetStreamBufferName(void* object, const char* name) +* +* Parameter object: pointer to the StreamBuffer that shall be named +* Parameter name: the name to set (const string literal) +* +* Sets a name for StreamBuffer objects for display in Tracealyzer. +******************************************************************************/ +void vTraceSetStreamBufferName(void* object, const char* name); +#else /* (TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS == 1) */ +#define vTraceSetStreamBufferName(object, name) /* Do nothing */ +#endif /* (TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS == 1) */ + +#if (TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS == 1) +/******************************************************************************* + * vTraceSetMessageBufferName(void* object, const char* name) + * + * Parameter object: pointer to the MessageBuffer that shall be named + * Parameter name: the name to set (const string literal) + * + * Sets a name for MessageBuffer objects for display in Tracealyzer. + ******************************************************************************/ +void vTraceSetMessageBufferName(void* object, const char* name); +#else /* (TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS == 1) */ +#define vTraceSetMessageBufferName(object, name) /* Do nothing */ +#endif /* (TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS == 1) */ + +#else /* (TRC_CFG_SCHEDULING_ONLY == 0) */ + +#define vTraceSetQueueName(object, name) /* Do nothing */ +#define vTraceSetSemaphoreName(object, name) /* Do nothing */ +#define vTraceSetMutexName(object, name) /* Do nothing */ +#define vTraceSetEventGroupName(object, name) /* Do nothing */ +#define vTraceSetStreamBufferName(object, name) /* Do nothing */ +#define vTraceSetMessageBufferName(object, name) /* Do nothing */ + +#endif /* (TRC_CFG_SCHEDULING_ONLY == 0) */ + +/******************************************************************************* + * Note: Setting names for event groups is difficult to support, this has been + * excluded intentionally. This since we don't know if event_groups.c is + * included in the build, so referencing it from the recorder may cause errors. + ******************************************************************************/ + +/* Gives the currently executing task (wrapper for RTOS-specific function) */ +void* prvTraceGetCurrentTaskHandle(void); + +#if (((TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_SNAPSHOT) && (TRC_CFG_INCLUDE_ISR_TRACING == 1)) || (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING)) +/* Tells if the scheduler currently is suspended (task-switches can't occur) */ +unsigned char prvTraceIsSchedulerSuspended(void); + +/******************************************************************************* + * INCLUDE_xTaskGetSchedulerState must be set to 1 for tracing to work properly + ******************************************************************************/ +#undef INCLUDE_xTaskGetSchedulerState +#define INCLUDE_xTaskGetSchedulerState 1 + +#endif /* (((TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_SNAPSHOT) && (TRC_CFG_INCLUDE_ISR_TRACING == 1)) || (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING)) */ + +#define TRACE_KERNEL_VERSION 0x1AA1 +#define TRACE_TICK_RATE_HZ configTICK_RATE_HZ /* Defined in "FreeRTOS.h" */ +#define TRACE_CPU_CLOCK_HZ configCPU_CLOCK_HZ /* Defined in "FreeRTOSConfig.h" */ +#define TRACE_GET_CURRENT_TASK() prvTraceGetCurrentTaskHandle() + +#define TRACE_GET_OS_TICKS() (uiTraceTickCount) /* Streaming only */ + +/* If using dynamic allocation of snapshot trace buffer... */ +#define TRACE_MALLOC(size) pvPortMalloc(size) + +#if defined(configUSE_TIMERS) +#if (configUSE_TIMERS == 1) +#undef INCLUDE_xTimerGetTimerDaemonTaskHandle +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 1 +#endif /* configUSE_TIMERS == 1*/ +#endif /* configUSE_TIMERS */ + +/* For ARM Cortex-M devices - assumes the ARM CMSIS API is available */ +#if (defined (__CORTEX_M)) + #define TRACE_ALLOC_CRITICAL_SECTION() uint32_t __irq_status; + #define TRACE_ENTER_CRITICAL_SECTION() {__irq_status = __get_PRIMASK(); __set_PRIMASK(1);} /* PRIMASK disables ALL interrupts - allows for tracing in any ISR */ + #define TRACE_EXIT_CRITICAL_SECTION() {__set_PRIMASK(__irq_status);} +#endif + +#if ((TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_CORTEX_A9) || (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Renesas_RX600) || (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_MICROCHIP_PIC24_PIC32) || (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Altera_NiosII)) + #define TRACE_ALLOC_CRITICAL_SECTION() int __irq_status; + #define TRACE_ENTER_CRITICAL_SECTION() {__irq_status = portSET_INTERRUPT_MASK_FROM_ISR();} + #define TRACE_EXIT_CRITICAL_SECTION() {portCLEAR_INTERRUPT_MASK_FROM_ISR(__irq_status);} +#endif + +#if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Win32) + /* In the Win32 port, there are no real interrupts, so we can use the normal critical sections */ + #define TRACE_ALLOC_CRITICAL_SECTION() + #define TRACE_ENTER_CRITICAL_SECTION() portENTER_CRITICAL() + #define TRACE_EXIT_CRITICAL_SECTION() portEXIT_CRITICAL() +#endif + +#if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_POWERPC_Z4) +#if (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_8_X) + /* FreeRTOS v8.0 or later */ + #define TRACE_ALLOC_CRITICAL_SECTION() UBaseType_t __irq_status; + #define TRACE_ENTER_CRITICAL_SECTION() {__irq_status = portSET_INTERRUPT_MASK_FROM_ISR();} + #define TRACE_EXIT_CRITICAL_SECTION() {portCLEAR_INTERRUPT_MASK_FROM_ISR(__irq_status);} +#else + /* FreeRTOS v7.x */ + #define TRACE_ALLOC_CRITICAL_SECTION() unsigned portBASE_TYPE __irq_status; + #define TRACE_ENTER_CRITICAL_SECTION() {__irq_status = portSET_INTERRUPT_MASK_FROM_ISR();} + #define TRACE_EXIT_CRITICAL_SECTION() {portCLEAR_INTERRUPT_MASK_FROM_ISR(__irq_status);} +#endif +#endif + +#ifndef TRACE_ENTER_CRITICAL_SECTION + #error "This hardware port has no definition for critical sections! See http://percepio.com/2014/10/27/how-to-define-critical-sections-for-the-recorder/" +#endif + + +#if (TRC_CFG_FREERTOS_VERSION == TRC_FREERTOS_VERSION_9_0_1) + /****************************************************************************** + * Fix for FreeRTOS v9.0.1 to correctly identify xQueuePeek events. + * + * In FreeRTOS v9.0.1, the below trace hooks are incorrectly used from three + * different functions. This as the earlier function xQueueGenericReceive + * has been replaced by xQueuePeek, xQueueSemaphoreTake and xQueueReceive. + * + * xQueueGenericReceive had a parameter "xJustPeeking", used by the trace hooks + * to tell between xQueuePeek events and others. This is no longer present, so + * we need another way to correctly identify peek events. Since all three + * functions call the same trace macros, the context of these macro is unknown. + * + * We therefore check the __LINE__ macro inside of the trace macros. This gives + * the line number of queue.c, where the macros are used. This can be used to + * tell if the context is xQueuePeek or another function. + * __LINE__ is a standard compiler feature since ancient times, so it should + * work on all common compilers. + * + * This might seem as a quite brittle and unusual solution, but works in this + * particular case and is only for FreeRTOS v9.0.1. + * Future versions of FreeRTOS should not need this fix, as we have submitted + * a correction of queue.c with individual trace macros for each function. + ******************************************************************************/ +#define isQueueReceiveHookActuallyPeek (__LINE__ > 1674) /* Half way between the closes trace points */ + +#elif (TRC_CFG_FREERTOS_VERSION <= TRC_FREERTOS_VERSION_9_0_0) +#define isQueueReceiveHookActuallyPeek xJustPeeking + +#elif (TRC_CFG_FREERTOS_VERSION > TRC_FREERTOS_VERSION_9_0_1) +#define isQueueReceiveHookActuallyPeek (__LINE__ < 0) /* instead of pdFALSE to fix a warning of "constant condition" */ + +#endif + +extern uint16_t CurrentFilterMask; + +extern uint16_t CurrentFilterGroup; + +uint8_t prvTraceGetQueueType(void* handle); + +uint16_t prvTraceGetTaskNumberLow16(void* handle); +uint16_t prvTraceGetTaskNumberHigh16(void* handle); +void prvTraceSetTaskNumberLow16(void* handle, uint16_t value); +void prvTraceSetTaskNumberHigh16(void* handle, uint16_t value); + +uint16_t prvTraceGetQueueNumberLow16(void* handle); +uint16_t prvTraceGetQueueNumberHigh16(void* handle); +void prvTraceSetQueueNumberLow16(void* handle, uint16_t value); +void prvTraceSetQueueNumberHigh16(void* handle, uint16_t value); + +#if (TRC_CFG_INCLUDE_TIMER_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) +uint16_t prvTraceGetTimerNumberLow16(void* handle); +uint16_t prvTraceGetTimerNumberHigh16(void* handle); +void prvTraceSetTimerNumberLow16(void* handle, uint16_t value); +void prvTraceSetTimerNumberHigh16(void* handle, uint16_t value); +#endif /* (TRC_CFG_INCLUDE_TIMER_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) */ + +#if (TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) +uint16_t prvTraceGetEventGroupNumberLow16(void* handle); +uint16_t prvTraceGetEventGroupNumberHigh16(void* handle); +void prvTraceSetEventGroupNumberLow16(void* handle, uint16_t value); +void prvTraceSetEventGroupNumberHigh16(void* handle, uint16_t value); +#endif /* (TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) */ + +#if (TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) +uint16_t prvTraceGetStreamBufferNumberLow16(void* handle); +uint16_t prvTraceGetStreamBufferNumberHigh16(void* handle); +void prvTraceSetStreamBufferNumberLow16(void* handle, uint16_t value); +void prvTraceSetStreamBufferNumberHigh16(void* handle, uint16_t value); +#endif /* (TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) */ + +#define TRACE_GET_TASK_FILTER(pxTask) prvTraceGetTaskNumberHigh16((void*)pxTask) +#define TRACE_SET_TASK_FILTER(pxTask, group) prvTraceSetTaskNumberHigh16((void*)pxTask, group) + +#define TRACE_GET_QUEUE_FILTER(pxObject) prvTraceGetQueueNumberHigh16((void*)pxObject) +#define TRACE_SET_QUEUE_FILTER(pxObject, group) prvTraceSetQueueNumberHigh16((void*)pxObject, group) + +#if (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) +#define TRACE_GET_EVENTGROUP_FILTER(pxObject) prvTraceGetEventGroupNumberHigh16((void*)pxObject) +#define TRACE_SET_EVENTGROUP_FILTER(pxObject, group) prvTraceSetEventGroupNumberHigh16((void*)pxObject, group) +#else /* (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) */ +/* FreeRTOS versions before v10.0 does not support filtering for event groups */ +#define TRACE_GET_EVENTGROUP_FILTER(pxObject) 1 +#define TRACE_SET_EVENTGROUP_FILTER(pxObject, group) +#endif /* (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) */ + +#if (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) +#define TRACE_GET_TIMER_FILTER(pxObject) prvTraceGetTimerNumberHigh16((void*)pxObject) +#define TRACE_SET_TIMER_FILTER(pxObject, group) prvTraceSetTimerNumberHigh16((void*)pxObject, group) +#else /* (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) */ +/* FreeRTOS versions before v10.0 does not support filtering for timers */ +#define TRACE_GET_TIMER_FILTER(pxObject) 1 +#define TRACE_SET_TIMER_FILTER(pxObject, group) +#endif /* (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) */ + +#define TRACE_GET_STREAMBUFFER_FILTER(pxObject) prvTraceGetStreamBufferNumberHigh16((void*)pxObject) +#define TRACE_SET_STREAMBUFFER_FILTER(pxObject, group) prvTraceSetStreamBufferNumberHigh16((void*)pxObject, group) + +/* We can only support filtering if FreeRTOS is at least v7.4 */ +#if (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_7_4) +#define TRACE_GET_OBJECT_FILTER(CLASS, pxObject) TRACE_GET_##CLASS##_FILTER(pxObject) +#define TRACE_SET_OBJECT_FILTER(CLASS, pxObject, group) TRACE_SET_##CLASS##_FILTER(pxObject, group) +#else /* (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_7_4) */ +#define TRACE_GET_OBJECT_FILTER(CLASS, pxObject) 1 +#define TRACE_SET_OBJECT_FILTER(CLASS, pxObject, group) +#endif /* (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_7_4) */ + +/******************************************************************************/ +/*** Definitions for Snapshot mode ********************************************/ +/******************************************************************************/ +#if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_SNAPSHOT) + +/*** The object classes *******************************************************/ + +#define TRACE_NCLASSES 9 +#define TRACE_CLASS_QUEUE ((traceObjectClass)0) +#define TRACE_CLASS_SEMAPHORE ((traceObjectClass)1) +#define TRACE_CLASS_MUTEX ((traceObjectClass)2) +#define TRACE_CLASS_TASK ((traceObjectClass)3) +#define TRACE_CLASS_ISR ((traceObjectClass)4) +#define TRACE_CLASS_TIMER ((traceObjectClass)5) +#define TRACE_CLASS_EVENTGROUP ((traceObjectClass)6) +#define TRACE_CLASS_STREAMBUFFER ((traceObjectClass)7) +#define TRACE_CLASS_MESSAGEBUFFER ((traceObjectClass)8) + +/*** Definitions for Object Table ********************************************/ +#define TRACE_KERNEL_OBJECT_COUNT ((TRC_CFG_NQUEUE) + (TRC_CFG_NSEMAPHORE) + (TRC_CFG_NMUTEX) + (TRC_CFG_NTASK) + (TRC_CFG_NISR) + (TRC_CFG_NTIMER) + (TRC_CFG_NEVENTGROUP) + (TRC_CFG_NSTREAMBUFFER) + (TRC_CFG_NMESSAGEBUFFER)) + +/* Queue properties (except name): current number of message in queue */ +#define PropertyTableSizeQueue ((TRC_CFG_NAME_LEN_QUEUE) + 1) + +/* Semaphore properties (except name): state (signaled = 1, cleared = 0) */ +#define PropertyTableSizeSemaphore ((TRC_CFG_NAME_LEN_SEMAPHORE) + 1) + +/* Mutex properties (except name): owner (task handle, 0 = free) */ +#define PropertyTableSizeMutex ((TRC_CFG_NAME_LEN_MUTEX) + 1) + +/* Task properties (except name): Byte 0: Current priority + Byte 1: state (if already active) + Byte 2: legacy, not used + Byte 3: legacy, not used */ +#define PropertyTableSizeTask ((TRC_CFG_NAME_LEN_TASK) + 4) + +/* ISR properties: Byte 0: priority + Byte 1: state (if already active) */ +#define PropertyTableSizeISR ((TRC_CFG_NAME_LEN_ISR) + 2) + +/* TRC_CFG_NTIMER properties: Byte 0: state (unused for now) */ +#define PropertyTableSizeTimer ((TRC_CFG_NAME_LEN_TIMER) + 1) + +/* TRC_CFG_NEVENTGROUP properties: Byte 0-3: state (unused for now)*/ +#define PropertyTableSizeEventGroup ((TRC_CFG_NAME_LEN_EVENTGROUP) + 4) + +/* TRC_CFG_NSTREAMBUFFER properties: Byte 0-3: state (unused for now)*/ +#define PropertyTableSizeStreamBuffer ((TRC_CFG_NAME_LEN_STREAMBUFFER) + 4) + +/* TRC_CFG_NMESSAGEBUFFER properties: Byte 0-3: state (unused for now)*/ +#define PropertyTableSizeMessageBuffer ((TRC_CFG_NAME_LEN_MESSAGEBUFFER) + 4) + + +/* The layout of the byte array representing the Object Property Table */ +#define StartIndexQueue (0) +#define StartIndexSemaphore (StartIndexQueue + (TRC_CFG_NQUEUE) * PropertyTableSizeQueue) +#define StartIndexMutex (StartIndexSemaphore + (TRC_CFG_NSEMAPHORE) * PropertyTableSizeSemaphore) +#define StartIndexTask (StartIndexMutex + (TRC_CFG_NMUTEX) * PropertyTableSizeMutex) +#define StartIndexISR (StartIndexTask + (TRC_CFG_NTASK) * PropertyTableSizeTask) +#define StartIndexTimer (StartIndexISR + (TRC_CFG_NISR) * PropertyTableSizeISR) +#define StartIndexEventGroup (StartIndexTimer + (TRC_CFG_NTIMER) * PropertyTableSizeTimer) +#define StartIndexStreamBuffer (StartIndexEventGroup + (TRC_CFG_NEVENTGROUP) * PropertyTableSizeEventGroup) +#define StartIndexMessageBuffer (StartIndexStreamBuffer + (TRC_CFG_NSTREAMBUFFER) * PropertyTableSizeStreamBuffer) + +/* Number of bytes used by the object table */ +#define TRACE_OBJECT_TABLE_SIZE (StartIndexMessageBuffer + (TRC_CFG_NMESSAGEBUFFER) * PropertyTableSizeMessageBuffer) + +/* Flag to tell the context of tracePEND_FUNC_CALL_FROM_ISR */ +extern int uiInEventGroupSetBitsFromISR; + +/* Initialization of the object property table */ +void vTraceInitObjectPropertyTable(void); + +/* Initialization of the handle mechanism, see e.g, prvTraceGetObjectHandle */ +void vTraceInitObjectHandleStack(void); + +/* Returns the "Not enough handles" error message for the specified object class */ +const char* pszTraceGetErrorNotEnoughHandles(traceObjectClass objectclass); + +void* prvTraceGetCurrentTaskHandle(void); + +/****************************************************************************** + * TraceQueueClassTable + * Translates a FreeRTOS QueueType into trace objects classes (TRACE_CLASS_). + * Has one entry for each QueueType, gives TRACE_CLASS ID. + ******************************************************************************/ +extern traceObjectClass TraceQueueClassTable[5]; + + +/*** Event codes for snapshot mode - must match Tracealyzer config files ******/ + +#define NULL_EVENT (0x00UL) + +/******************************************************************************* + * EVENTGROUP_DIV + * + * Miscellaneous events. + ******************************************************************************/ +#define EVENTGROUP_DIV (NULL_EVENT + 1UL) /*0x01*/ +#define DIV_XPS (EVENTGROUP_DIV + 0UL) /*0x01*/ +#define DIV_TASK_READY (EVENTGROUP_DIV + 1UL) /*0x02*/ +#define DIV_NEW_TIME (EVENTGROUP_DIV + 2UL) /*0x03*/ + +/******************************************************************************* + * EVENTGROUP_TS + * + * Events for storing task-switches and interrupts. The RESUME events are + * generated if the task/interrupt is already marked active. + ******************************************************************************/ +#define EVENTGROUP_TS (EVENTGROUP_DIV + 3UL) /*0x04*/ +#define TS_ISR_BEGIN (EVENTGROUP_TS + 0UL) /*0x04*/ +#define TS_ISR_RESUME (EVENTGROUP_TS + 1UL) /*0x05*/ +#define TS_TASK_BEGIN (EVENTGROUP_TS + 2UL) /*0x06*/ +#define TS_TASK_RESUME (EVENTGROUP_TS + 3UL) /*0x07*/ + +/******************************************************************************* + * EVENTGROUP_OBJCLOSE_NAME + * + * About Close Events + * When an object is evicted from the object property table (object close), two + * internal events are stored (EVENTGROUP_OBJCLOSE_NAME and + * EVENTGROUP_OBJCLOSE_PROP), containing the handle-name mapping and object + * properties valid up to this point. + ******************************************************************************/ +#define EVENTGROUP_OBJCLOSE_NAME_TRCSUCCESS (EVENTGROUP_TS + 4UL) /*0x08*/ + +/******************************************************************************* + * EVENTGROUP_OBJCLOSE_PROP + * + * The internal event carrying properties of deleted objects + * The handle and object class of the closed object is not stored in this event, + * but is assumed to be the same as in the preceding CLOSE event. Thus, these + * two events must be generated from within a critical section. + * When queues are closed, arg1 is the "state" property (i.e., number of + * buffered messages/signals). + * When actors are closed, arg1 is priority, arg2 is handle of the "instance + * finish" event, and arg3 is event code of the "instance finish" event. + * In this case, the lower three bits is the object class of the instance finish + * handle. The lower three bits are not used (always zero) when queues are + * closed since the queue type is given in the previous OBJCLOSE_NAME event. + ******************************************************************************/ +#define EVENTGROUP_OBJCLOSE_PROP_TRCSUCCESS (EVENTGROUP_OBJCLOSE_NAME_TRCSUCCESS + 8UL) /*0x10*/ + +/******************************************************************************* + * EVENTGROUP_CREATE + * + * The events in this group are used to log Kernel object creations. + * The lower three bits in the event code gives the object class, i.e., type of + * create operation (task, queue, semaphore, etc). + ******************************************************************************/ +#define EVENTGROUP_CREATE_OBJ_TRCSUCCESS (EVENTGROUP_OBJCLOSE_PROP_TRCSUCCESS + 8UL) /*0x18*/ + +/******************************************************************************* + * EVENTGROUP_SEND + * + * The events in this group are used to log Send/Give events on queues, + * semaphores and mutexes The lower three bits in the event code gives the + * object class, i.e., what type of object that is operated on (queue, semaphore + * or mutex). + ******************************************************************************/ +#define EVENTGROUP_SEND_TRCSUCCESS (EVENTGROUP_CREATE_OBJ_TRCSUCCESS + 8UL) /*0x20*/ + +/******************************************************************************* + * EVENTGROUP_RECEIVE + * + * The events in this group are used to log Receive/Take events on queues, + * semaphores and mutexes. The lower three bits in the event code gives the + * object class, i.e., what type of object that is operated on (queue, semaphore + * or mutex). + ******************************************************************************/ +#define EVENTGROUP_RECEIVE_TRCSUCCESS (EVENTGROUP_SEND_TRCSUCCESS + 8UL) /*0x28*/ + +/* Send/Give operations, from ISR */ +#define EVENTGROUP_SEND_FROM_ISR_TRCSUCCESS \ + (EVENTGROUP_RECEIVE_TRCSUCCESS + 8UL) /*0x30*/ + +/* Receive/Take operations, from ISR */ +#define EVENTGROUP_RECEIVE_FROM_ISR_TRCSUCCESS \ + (EVENTGROUP_SEND_FROM_ISR_TRCSUCCESS + 8UL) /*0x38*/ + +/* "Failed" event type versions of above (timeout, failed allocation, etc) */ +#define EVENTGROUP_KSE_TRCFAILED \ + (EVENTGROUP_RECEIVE_FROM_ISR_TRCSUCCESS + 8UL) /*0x40*/ + +/* Failed create calls - memory allocation failed */ +#define EVENTGROUP_CREATE_OBJ_TRCFAILED (EVENTGROUP_KSE_TRCFAILED) /*0x40*/ + +/* Failed send/give - timeout! */ +#define EVENTGROUP_SEND_TRCFAILED (EVENTGROUP_CREATE_OBJ_TRCFAILED + 8UL) /*0x48*/ + +/* Failed receive/take - timeout! */ +#define EVENTGROUP_RECEIVE_TRCFAILED (EVENTGROUP_SEND_TRCFAILED + 8UL) /*0x50*/ + +/* Failed non-blocking send/give - queue full */ +#define EVENTGROUP_SEND_FROM_ISR_TRCFAILED (EVENTGROUP_RECEIVE_TRCFAILED + 8UL) /*0x58*/ + +/* Failed non-blocking receive/take - queue empty */ +#define EVENTGROUP_RECEIVE_FROM_ISR_TRCFAILED \ + (EVENTGROUP_SEND_FROM_ISR_TRCFAILED + 8UL) /*0x60*/ + +/* Events when blocking on receive/take */ +#define EVENTGROUP_RECEIVE_TRCBLOCK \ + (EVENTGROUP_RECEIVE_FROM_ISR_TRCFAILED + 8UL) /*0x68*/ + +/* Events when blocking on send/give */ +#define EVENTGROUP_SEND_TRCBLOCK (EVENTGROUP_RECEIVE_TRCBLOCK + 8UL) /*0x70*/ + +/* Events on queue peek (receive) */ +#define EVENTGROUP_PEEK_TRCSUCCESS (EVENTGROUP_SEND_TRCBLOCK + 8UL) /*0x78*/ + +/* Events on object delete (vTaskDelete or vQueueDelete) */ +#define EVENTGROUP_DELETE_OBJ_TRCSUCCESS (EVENTGROUP_PEEK_TRCSUCCESS + 8UL) /*0x80*/ + +/* Other events - object class is implied: TASK */ +#define EVENTGROUP_OTHERS (EVENTGROUP_DELETE_OBJ_TRCSUCCESS + 8UL) /*0x88*/ +#define TASK_DELAY_UNTIL (EVENTGROUP_OTHERS + 0UL) /*0x88*/ +#define TASK_DELAY (EVENTGROUP_OTHERS + 1UL) /*0x89*/ +#define TASK_SUSPEND (EVENTGROUP_OTHERS + 2UL) /*0x8A*/ +#define TASK_RESUME (EVENTGROUP_OTHERS + 3UL) /*0x8B*/ +#define TASK_RESUME_FROM_ISR (EVENTGROUP_OTHERS + 4UL) /*0x8C*/ +#define TASK_PRIORITY_SET (EVENTGROUP_OTHERS + 5UL) /*0x8D*/ +#define TASK_PRIORITY_INHERIT (EVENTGROUP_OTHERS + 6UL) /*0x8E*/ +#define TASK_PRIORITY_DISINHERIT (EVENTGROUP_OTHERS + 7UL) /*0x8F*/ + +#define EVENTGROUP_MISC_PLACEHOLDER (EVENTGROUP_OTHERS + 8UL) /*0x90*/ +#define PEND_FUNC_CALL (EVENTGROUP_MISC_PLACEHOLDER+0UL) /*0x90*/ +#define PEND_FUNC_CALL_FROM_ISR (EVENTGROUP_MISC_PLACEHOLDER+1UL) /*0x91*/ +#define PEND_FUNC_CALL_TRCFAILED (EVENTGROUP_MISC_PLACEHOLDER+2UL) /*0x92*/ +#define PEND_FUNC_CALL_FROM_ISR_TRCFAILED (EVENTGROUP_MISC_PLACEHOLDER+3UL) /*0x93*/ +#define MEM_MALLOC_SIZE (EVENTGROUP_MISC_PLACEHOLDER+4UL) /*0x94*/ +#define MEM_MALLOC_ADDR (EVENTGROUP_MISC_PLACEHOLDER+5UL) /*0x95*/ +#define MEM_FREE_SIZE (EVENTGROUP_MISC_PLACEHOLDER+6UL) /*0x96*/ +#define MEM_FREE_ADDR (EVENTGROUP_MISC_PLACEHOLDER+7UL) /*0x97*/ + +/* User events */ +#define EVENTGROUP_USEREVENT (EVENTGROUP_MISC_PLACEHOLDER + 8UL) /*0x98*/ +#define USER_EVENT (EVENTGROUP_USEREVENT + 0UL) + +/* Allow for 0-15 arguments (the number of args is added to event code) */ +#define USER_EVENT_LAST (EVENTGROUP_USEREVENT + 15UL) /*0xA7*/ + +/******************************************************************************* + * XTS Event - eXtended TimeStamp events + * The timestamps used in the recorder are "differential timestamps" (DTS), i.e. + * the time since the last stored event. The DTS fields are either 1 or 2 bytes + * in the other events, depending on the bytes available in the event struct. + * If the time since the last event (the DTS) is larger than allowed for by + * the DTS field of the current event, an XTS event is inserted immediately + * before the original event. The XTS event contains up to 3 additional bytes + * of the DTS value - the higher bytes of the true DTS value. The lower 1-2 + * bytes are stored in the normal DTS field. + * There are two types of XTS events, XTS8 and XTS16. An XTS8 event is stored + * when there is only room for 1 byte (8 bit) DTS data in the original event, + * which means a limit of 0xFF (255UL). The XTS16 is used when the original event + * has a 16 bit DTS field and thereby can handle values up to 0xFFFF (65535UL). + * + * Using a very high frequency time base can result in many XTS events. + * Preferably, the time between two OS ticks should fit in 16 bits, i.e., + * at most 65535. If your time base has a higher frequency, you can define + * the TRACE + ******************************************************************************/ + +#define EVENTGROUP_SYS (EVENTGROUP_USEREVENT + 16UL) /*0xA8*/ +#define XTS8 (EVENTGROUP_SYS + 0UL) /*0xA8*/ +#define XTS16 (EVENTGROUP_SYS + 1UL) /*0xA9*/ +#define EVENT_BEING_WRITTEN (EVENTGROUP_SYS + 2UL) /*0xAA*/ +#define RESERVED_DUMMY_CODE (EVENTGROUP_SYS + 3UL) /*0xAB*/ +#define LOW_POWER_BEGIN (EVENTGROUP_SYS + 4UL) /*0xAC*/ +#define LOW_POWER_END (EVENTGROUP_SYS + 5UL) /*0xAD*/ +#define XID (EVENTGROUP_SYS + 6UL) /*0xAE*/ +#define XTS16L (EVENTGROUP_SYS + 7UL) /*0xAF*/ + +#define EVENTGROUP_TIMER (EVENTGROUP_SYS + 8UL) /*0xB0*/ +#define TIMER_CREATE (EVENTGROUP_TIMER + 0UL) /*0xB0*/ +#define TIMER_START (EVENTGROUP_TIMER + 1UL) /*0xB1*/ +#define TIMER_RST (EVENTGROUP_TIMER + 2UL) /*0xB2*/ +#define TIMER_STOP (EVENTGROUP_TIMER + 3UL) /*0xB3*/ +#define TIMER_CHANGE_PERIOD (EVENTGROUP_TIMER + 4UL) /*0xB4*/ +#define TIMER_DELETE_OBJ (EVENTGROUP_TIMER + 5UL) /*0xB5*/ +#define TIMER_START_FROM_ISR (EVENTGROUP_TIMER + 6UL) /*0xB6*/ +#define TIMER_RESET_FROM_ISR (EVENTGROUP_TIMER + 7UL) /*0xB7*/ +#define TIMER_STOP_FROM_ISR (EVENTGROUP_TIMER + 8UL) /*0xB8*/ + +#define TIMER_CREATE_TRCFAILED (EVENTGROUP_TIMER + 9UL) /*0xB9*/ +#define TIMER_START_TRCFAILED (EVENTGROUP_TIMER + 10UL) /*0xBA*/ +#define TIMER_RESET_TRCFAILED (EVENTGROUP_TIMER + 11UL) /*0xBB*/ +#define TIMER_STOP_TRCFAILED (EVENTGROUP_TIMER + 12UL) /*0xBC*/ +#define TIMER_CHANGE_PERIOD_TRCFAILED (EVENTGROUP_TIMER + 13UL) /*0xBD*/ +#define TIMER_DELETE_TRCFAILED (EVENTGROUP_TIMER + 14UL) /*0xBE*/ +#define TIMER_START_FROM_ISR_TRCFAILED (EVENTGROUP_TIMER + 15UL) /*0xBF*/ +#define TIMER_RESET_FROM_ISR_TRCFAILED (EVENTGROUP_TIMER + 16UL) /*0xC0*/ +#define TIMER_STOP_FROM_ISR_TRCFAILED (EVENTGROUP_TIMER + 17UL) /*0xC1*/ + +#define EVENTGROUP_EG (EVENTGROUP_TIMER + 18UL) /*0xC2*/ +#define EVENT_GROUP_CREATE (EVENTGROUP_EG + 0UL) /*0xC2*/ +#define EVENT_GROUP_CREATE_TRCFAILED (EVENTGROUP_EG + 1UL) /*0xC3*/ +#define EVENT_GROUP_SYNC_TRCBLOCK (EVENTGROUP_EG + 2UL) /*0xC4*/ +#define EVENT_GROUP_SYNC_END (EVENTGROUP_EG + 3UL) /*0xC5*/ +#define EVENT_GROUP_WAIT_BITS_TRCBLOCK (EVENTGROUP_EG + 4UL) /*0xC6*/ +#define EVENT_GROUP_WAIT_BITS_END (EVENTGROUP_EG + 5UL) /*0xC7*/ +#define EVENT_GROUP_CLEAR_BITS (EVENTGROUP_EG + 6UL) /*0xC8*/ +#define EVENT_GROUP_CLEAR_BITS_FROM_ISR (EVENTGROUP_EG + 7UL) /*0xC9*/ +#define EVENT_GROUP_SET_BITS (EVENTGROUP_EG + 8UL) /*0xCA*/ +#define EVENT_GROUP_DELETE_OBJ (EVENTGROUP_EG + 9UL) /*0xCB*/ +#define EVENT_GROUP_SYNC_END_TRCFAILED (EVENTGROUP_EG + 10UL) /*0xCC*/ +#define EVENT_GROUP_WAIT_BITS_END_TRCFAILED (EVENTGROUP_EG + 11UL) /*0xCD*/ +#define EVENT_GROUP_SET_BITS_FROM_ISR (EVENTGROUP_EG + 12UL) /*0xCE*/ +#define EVENT_GROUP_SET_BITS_FROM_ISR_TRCFAILED (EVENTGROUP_EG + 13UL) /*0xCF*/ + +#define TASK_INSTANCE_FINISHED_NEXT_KSE (EVENTGROUP_EG + 14UL) /*0xD0*/ +#define TASK_INSTANCE_FINISHED_DIRECT (EVENTGROUP_EG + 15UL) /*0xD1*/ + +#define TRACE_TASK_NOTIFY_GROUP (EVENTGROUP_EG + 16UL) /*0xD2*/ +#define TRACE_TASK_NOTIFY (TRACE_TASK_NOTIFY_GROUP + 0UL) /*0xD2*/ +#define TRACE_TASK_NOTIFY_TAKE (TRACE_TASK_NOTIFY_GROUP + 1UL) /*0xD3*/ +#define TRACE_TASK_NOTIFY_TAKE_TRCBLOCK (TRACE_TASK_NOTIFY_GROUP + 2UL) /*0xD4*/ +#define TRACE_TASK_NOTIFY_TAKE_TRCFAILED (TRACE_TASK_NOTIFY_GROUP + 3UL) /*0xD5*/ +#define TRACE_TASK_NOTIFY_WAIT (TRACE_TASK_NOTIFY_GROUP + 4UL) /*0xD6*/ +#define TRACE_TASK_NOTIFY_WAIT_TRCBLOCK (TRACE_TASK_NOTIFY_GROUP + 5UL) /*0xD7*/ +#define TRACE_TASK_NOTIFY_WAIT_TRCFAILED (TRACE_TASK_NOTIFY_GROUP + 6UL) /*0xD8*/ +#define TRACE_TASK_NOTIFY_FROM_ISR (TRACE_TASK_NOTIFY_GROUP + 7UL) /*0xD9*/ +#define TRACE_TASK_NOTIFY_GIVE_FROM_ISR (TRACE_TASK_NOTIFY_GROUP + 8UL) /*0xDA*/ + +#define TIMER_EXPIRED (TRACE_TASK_NOTIFY_GROUP + 9UL) /* 0xDB */ + + /* Events on queue peek (receive) */ +#define EVENTGROUP_PEEK_TRCBLOCK (TRACE_TASK_NOTIFY_GROUP + 10UL) /*0xDC*/ +/* peek block on queue: 0xDC */ +/* peek block on semaphore: 0xDD */ +/* peek block on mutex: 0xDE */ + +/* Events on queue peek (receive) */ +#define EVENTGROUP_PEEK_TRCFAILED (EVENTGROUP_PEEK_TRCBLOCK + 3UL) /*0xDF*/ +/* peek failed on queue: 0xDF */ +/* peek failed on semaphore: 0xE0 */ +/* peek failed on mutex: 0xE1 */ + +#define EVENTGROUP_STREAMBUFFER_DIV (EVENTGROUP_PEEK_TRCFAILED + 3UL) /*0xE2*/ +#define TRACE_STREAMBUFFER_RESET (EVENTGROUP_STREAMBUFFER_DIV + 0) /*0xE2*/ +#define TRACE_MESSAGEBUFFER_RESET (EVENTGROUP_STREAMBUFFER_DIV + 1UL) /*0xE3*/ +#define TRACE_STREAMBUFFER_OBJCLOSE_NAME_TRCSUCCESS (EVENTGROUP_STREAMBUFFER_DIV + 2UL) /*0xE4*/ +#define TRACE_MESSAGEBUFFER_OBJCLOSE_NAME_TRCSUCCESS (EVENTGROUP_STREAMBUFFER_DIV + 3UL) /*0xE5*/ +#define TRACE_STREAMBUFFER_OBJCLOSE_PROP_TRCSUCCESS (EVENTGROUP_STREAMBUFFER_DIV + 4UL) /*0xE6*/ +#define TRACE_MESSAGEBUFFER_OBJCLOSE_PROP_TRCSUCCESS (EVENTGROUP_STREAMBUFFER_DIV + 5UL) /*0xE7*/ + +/* The following are using previously "lost" event codes */ +#define TRACE_STREAMBUFFER_CREATE_OBJ_TRCSUCCESS (EVENTGROUP_CREATE_OBJ_TRCSUCCESS + 4UL) /*0x1C*/ +#define TRACE_STREAMBUFFER_CREATE_OBJ_TRCFAILED (EVENTGROUP_CREATE_OBJ_TRCFAILED + 4UL) /*0x44*/ +#define TRACE_STREAMBUFFER_DELETE_OBJ_TRCSUCCESS (EVENTGROUP_DELETE_OBJ_TRCSUCCESS + 4UL) /*0x84*/ +#define TRACE_STREAMBUFFER_SEND_TRCSUCCESS (EVENTGROUP_SEND_TRCSUCCESS + 3UL) /*0x23*/ +#define TRACE_STREAMBUFFER_SEND_TRCBLOCK (EVENTGROUP_SEND_TRCBLOCK + 3UL) /*0x73*/ +#define TRACE_STREAMBUFFER_SEND_TRCFAILED (EVENTGROUP_SEND_TRCFAILED + 3UL) /*0x4B*/ +#define TRACE_STREAMBUFFER_RECEIVE_TRCSUCCESS (EVENTGROUP_RECEIVE_TRCSUCCESS + 3UL) /*0x2B*/ +#define TRACE_STREAMBUFFER_RECEIVE_TRCBLOCK (EVENTGROUP_RECEIVE_TRCBLOCK + 3UL) /*0x6B*/ +#define TRACE_STREAMBUFFER_RECEIVE_TRCFAILED (EVENTGROUP_RECEIVE_TRCFAILED + 3UL) /*0x53*/ +#define TRACE_STREAMBUFFER_SEND_FROM_ISR_TRCSUCCESS (EVENTGROUP_SEND_FROM_ISR_TRCSUCCESS + 3UL) /*0x33*/ +#define TRACE_STREAMBUFFER_SEND_FROM_ISR_TRCFAILED (EVENTGROUP_SEND_FROM_ISR_TRCFAILED + 3UL) /*0x5B*/ +#define TRACE_STREAMBUFFER_RECEIVE_FROM_ISR_TRCSUCCESS (EVENTGROUP_RECEIVE_FROM_ISR_TRCSUCCESS + 3UL) /*0x3B*/ +#define TRACE_STREAMBUFFER_RECEIVE_FROM_ISR_TRCFAILED (EVENTGROUP_RECEIVE_FROM_ISR_TRCFAILED + 3UL) /*0x63*/ + +/* The following are using previously "lost" event codes. These macros aren't even directly referenced, instead we do (equivalent STREAMBUFFER code) + 1. */ +#define TRACE_MESSAGEBUFFER_CREATE_OBJ_TRCSUCCESS (EVENTGROUP_CREATE_OBJ_TRCSUCCESS + 5UL) /*0x1D*/ +#define TRACE_MESSAGEBUFFER_CREATE_OBJ_TRCFAILED (EVENTGROUP_CREATE_OBJ_TRCFAILED + 5UL) /*0x45*/ +#define TRACE_MESSAGEBUFFER_DELETE_OBJ_TRCSUCCESS (EVENTGROUP_DELETE_OBJ_TRCSUCCESS + 5UL) /*0x85*/ +#define TRACE_MESSAGEBUFFER_SEND_TRCSUCCESS (EVENTGROUP_SEND_TRCSUCCESS + 4UL) /*0x24*/ +#define TRACE_MESSAGEBUFFER_SEND_TRCBLOCK (EVENTGROUP_SEND_TRCBLOCK + 4UL) /*0x74*/ +#define TRACE_MESSAGEBUFFER_SEND_TRCFAILED (EVENTGROUP_SEND_TRCFAILED + 4UL) /*0x4C*/ +#define TRACE_MESSAGEBUFFER_RECEIVE_TRCSUCCESS (EVENTGROUP_RECEIVE_TRCSUCCESS + 4UL) /*0x2C*/ +#define TRACE_MESSAGEBUFFER_RECEIVE_TRCBLOCK (EVENTGROUP_RECEIVE_TRCBLOCK + 4UL) /*0x6C*/ +#define TRACE_MESSAGEBUFFER_RECEIVE_TRCFAILED (EVENTGROUP_RECEIVE_TRCFAILED + 4UL) /*0x54*/ +#define TRACE_MESSAGEBUFFER_SEND_FROM_ISR_TRCSUCCESS (EVENTGROUP_SEND_FROM_ISR_TRCSUCCESS + 4UL) /*0x34*/ +#define TRACE_MESSAGEBUFFER_SEND_FROM_ISR_TRCFAILED (EVENTGROUP_SEND_FROM_ISR_TRCFAILED + 4UL) /*0x5C*/ +#define TRACE_MESSAGEBUFFER_RECEIVE_FROM_ISR_TRCSUCCESS (EVENTGROUP_RECEIVE_FROM_ISR_TRCSUCCESS + 4UL) /*0x3C*/ +#define TRACE_MESSAGEBUFFER_RECEIVE_FROM_ISR_TRCFAILED (EVENTGROUP_RECEIVE_FROM_ISR_TRCFAILED + 4UL) /*0x64*/ + +/* LAST EVENT (0xE7) */ + +/**************************** +* MACROS TO GET TRACE CLASS * +****************************/ +#define TRACE_GET_TRACE_CLASS_FROM_TASK_CLASS(kernelClass) (TRACE_CLASS_TASK) +#define TRACE_GET_TRACE_CLASS_FROM_TASK_OBJECT(pxObject) (TRACE_CLASS_TASK) + +#define TRACE_GET_TRACE_CLASS_FROM_QUEUE_CLASS(kernelClass) TraceQueueClassTable[kernelClass] +#define TRACE_GET_TRACE_CLASS_FROM_QUEUE_OBJECT(pxObject) TRACE_GET_TRACE_CLASS_FROM_QUEUE_CLASS(prvTraceGetQueueType(pxObject)) + +#define TRACE_GET_TRACE_CLASS_FROM_TIMER_CLASS(kernelClass) (TRACE_CLASS_TIMER) +#define TRACE_GET_TRACE_CLASS_FROM_TIMER_OBJECT(pxObject) (TRACE_CLASS_TIMER) + +#define TRACE_GET_TRACE_CLASS_FROM_EVENTGROUP_CLASS(kernelClass) (TRACE_CLASS_EVENTGROUP) +#define TRACE_GET_TRACE_CLASS_FROM_EVENTGROUP_OBJECT(pxObject) (TRACE_CLASS_EVENTGROUP) + +/* TRACE_GET_TRACE_CLASS_FROM_STREAMBUFFER_CLASS can only be accessed with a parameter indicating if it is a MessageBuffer */ +#define TRACE_GET_TRACE_CLASS_FROM_STREAMBUFFER_CLASS(xIsMessageBuffer) (xIsMessageBuffer == 1 ? TRACE_CLASS_MESSAGEBUFFER : TRACE_CLASS_STREAMBUFFER) +#define TRACE_GET_TRACE_CLASS_FROM_STREAMBUFFER_OBJECT(pxObject) (prvGetStreamBufferType(pxObject) == 1 ? TRACE_CLASS_MESSAGEBUFFER : TRACE_CLASS_STREAMBUFFER) + +/* Generic versions */ +#define TRACE_GET_CLASS_TRACE_CLASS(CLASS, kernelClass) TRACE_GET_TRACE_CLASS_FROM_##CLASS##_CLASS(kernelClass) +#define TRACE_GET_OBJECT_TRACE_CLASS(CLASS, pxObject) TRACE_GET_TRACE_CLASS_FROM_##CLASS##_OBJECT(pxObject) + +/****************************** +* MACROS TO GET OBJECT NUMBER * +******************************/ +#define TRACE_GET_TASK_NUMBER(pxTCB) (traceHandle)(prvTraceGetTaskNumberLow16(pxTCB)) +#define TRACE_SET_TASK_NUMBER(pxTCB) prvTraceSetTaskNumberLow16(pxTCB, prvTraceGetObjectHandle(TRACE_GET_OBJECT_TRACE_CLASS(TASK, pxTCB))); + +#define TRACE_GET_QUEUE_NUMBER(queue) ( ( traceHandle ) prvTraceGetQueueNumberLow16(queue) ) +#define TRACE_SET_QUEUE_NUMBER(queue) prvTraceSetQueueNumberLow16(queue, (uint16_t)prvTraceGetObjectHandle(TRACE_GET_OBJECT_TRACE_CLASS(QUEUE, queue))); + +#if (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) +#define TRACE_GET_TIMER_NUMBER(tmr) ( ( traceHandle ) prvTraceGetTimerNumberLow16(tmr) ) +#define TRACE_SET_TIMER_NUMBER(tmr) prvTraceSetTimerNumberLow16(tmr, (uint16_t)prvTraceGetObjectHandle(TRACE_GET_OBJECT_TRACE_CLASS(TIMER, tmr))); +#else /* (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) */ +#define TRACE_GET_TIMER_NUMBER(tmr) ( ( traceHandle ) ((Timer_t*)tmr)->uxTimerNumber ) +#define TRACE_SET_TIMER_NUMBER(tmr) ((Timer_t*)tmr)->uxTimerNumber = prvTraceGetObjectHandle(TRACE_GET_OBJECT_TRACE_CLASS(TIMER, tmr)); +#endif /* (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) */ + +#if (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) +#define TRACE_GET_EVENTGROUP_NUMBER(eg) ( ( traceHandle ) prvTraceGetEventGroupNumberLow16(eg) ) +#define TRACE_SET_EVENTGROUP_NUMBER(eg) prvTraceSetEventGroupNumberLow16(eg, (uint16_t)prvTraceGetObjectHandle(TRACE_GET_OBJECT_TRACE_CLASS(EVENTGROUP, eg))); +#else /* (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) */ +#define TRACE_GET_EVENTGROUP_NUMBER(eg) ( ( traceHandle ) uxEventGroupGetNumber(eg) ) +#define TRACE_SET_EVENTGROUP_NUMBER(eg) ((EventGroup_t*)eg)->uxEventGroupNumber = prvTraceGetObjectHandle(TRACE_GET_OBJECT_TRACE_CLASS(EVENTGROUP, eg)); +#endif /* (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) */ + + +#define TRACE_GET_STREAMBUFFER_NUMBER(sb) ( ( traceHandle ) prvTraceGetStreamBufferNumberLow16(sb) ) +#define TRACE_SET_STREAMBUFFER_NUMBER(sb) prvTraceSetStreamBufferNumberLow16(sb, (uint16_t)prvTraceGetObjectHandle(TRACE_GET_OBJECT_TRACE_CLASS(STREAMBUFFER, sb))); + +/* Generic versions */ +#define TRACE_GET_OBJECT_NUMBER(CLASS, pxObject) TRACE_GET_##CLASS##_NUMBER(pxObject) +#define TRACE_SET_OBJECT_NUMBER(CLASS, pxObject) TRACE_SET_##CLASS##_NUMBER(pxObject) + +/****************************** +* MACROS TO GET EVENT CODES * +******************************/ +#define TRACE_GET_TASK_CLASS_EVENT_CODE(SERVICE, RESULT, kernelClass) (uint8_t)(EVENTGROUP_##SERVICE##_##RESULT + TRACE_GET_CLASS_TRACE_CLASS(TASK, kernelClass)) +#define TRACE_GET_QUEUE_CLASS_EVENT_CODE(SERVICE, RESULT, kernelClass) (uint8_t)(EVENTGROUP_##SERVICE##_##RESULT + TRACE_GET_CLASS_TRACE_CLASS(QUEUE, kernelClass)) +#define TRACE_GET_TIMER_CLASS_EVENT_CODE(SERVICE, RESULT, kernelClass) -- THIS IS NOT USED -- +#define TRACE_GET_EVENTGROUP_CLASS_EVENT_CODE(SERVICE, RESULT, kernelClass) -- THIS IS NOT USED -- +#define TRACE_GET_STREAMBUFFER_CLASS_EVENT_CODE(SERVICE, RESULT, isMessageBuffer) (uint8_t)(TRACE_STREAMBUFFER_##SERVICE##_##RESULT + (uint8_t)isMessageBuffer) + +#define TRACE_GET_TASK_OBJECT_EVENT_CODE(SERVICE, RESULT, pxTCB) (uint8_t)(EVENTGROUP_##SERVICE##_##RESULT + TRACE_CLASS_TASK) +#define TRACE_GET_QUEUE_OBJECT_EVENT_CODE(SERVICE, RESULT, pxObject) (uint8_t)(EVENTGROUP_##SERVICE##_##RESULT + TRACE_GET_OBJECT_TRACE_CLASS(QUEUE, pxObject)) +#define TRACE_GET_TIMER_OBJECT_EVENT_CODE(SERVICE, RESULT, UNUSED) -- THIS IS NOT USED -- +#define TRACE_GET_EVENTGROUP_OBJECT_EVENT_CODE(SERVICE, RESULT, UNUSED) -- THIS IS NOT USED -- +#define TRACE_GET_STREAMBUFFER_OBJECT_EVENT_CODE(SERVICE, RESULT, pxObject) (uint8_t)(TRACE_STREAMBUFFER_##SERVICE##_##RESULT + prvGetStreamBufferType(pxObject)) + +/* Generic versions */ +#define TRACE_GET_CLASS_EVENT_CODE(SERVICE, RESULT, CLASS, kernelClass) TRACE_GET_##CLASS##_CLASS_EVENT_CODE(SERVICE, RESULT, kernelClass) +#define TRACE_GET_OBJECT_EVENT_CODE(SERVICE, RESULT, CLASS, pxObject) TRACE_GET_##CLASS##_OBJECT_EVENT_CODE(SERVICE, RESULT, pxObject) + +/****************************** +* SPECIAL MACROS FOR TASKS * +******************************/ +#define TRACE_GET_TASK_PRIORITY(pxTCB) ((uint8_t)pxTCB->uxPriority) +#define TRACE_GET_TASK_NAME(pxTCB) ((char*)pxTCB->pcTaskName) + +/*** The trace macros for snapshot mode **************************************/ + +/* A macro that will update the tick count when returning from tickless idle */ +#undef traceINCREASE_TICK_COUNT +#define traceINCREASE_TICK_COUNT( xCount ) + +/* Called for each task that becomes ready */ +#undef traceMOVED_TASK_TO_READY_STATE +#define traceMOVED_TASK_TO_READY_STATE( pxTCB ) \ + trcKERNEL_HOOKS_MOVED_TASK_TO_READY_STATE(pxTCB); + +/* Called on each OS tick. Will call uiPortGetTimestamp to make sure it is called at least once every OS tick. */ +#undef traceTASK_INCREMENT_TICK + +#if (TRC_CFG_FREERTOS_VERSION <= TRC_FREERTOS_VERSION_7_4) + +#define traceTASK_INCREMENT_TICK( xTickCount ) \ + if (uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdTRUE || uxMissedTicks == 0) { trcKERNEL_HOOKS_INCREMENT_TICK(); } \ + if (uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE) { trcKERNEL_HOOKS_NEW_TIME(DIV_NEW_TIME, xTickCount + 1); } + +#else + +#define traceTASK_INCREMENT_TICK( xTickCount ) \ + if (uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdTRUE || uxPendedTicks == 0) { trcKERNEL_HOOKS_INCREMENT_TICK(); } \ + if (uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE) { trcKERNEL_HOOKS_NEW_TIME(DIV_NEW_TIME, xTickCount + 1); } + +#endif + +/* Called on each task-switch */ +#undef traceTASK_SWITCHED_IN +#define traceTASK_SWITCHED_IN() \ + trcKERNEL_HOOKS_TASK_SWITCH(TRACE_GET_CURRENT_TASK()); + +/* Called on vTaskCreate */ +#undef traceTASK_CREATE +#define traceTASK_CREATE(pxNewTCB) \ + if (pxNewTCB != NULL) \ + { \ + trcKERNEL_HOOKS_TASK_CREATE(TRACE_GET_OBJECT_EVENT_CODE(CREATE_OBJ, TRCSUCCESS, TASK, pxNewTCB), TASK, pxNewTCB); \ + } + +/* Called in vTaskCreate, if it fails (typically if the stack can not be allocated) */ +#undef traceTASK_CREATE_FAILED +#define traceTASK_CREATE_FAILED() \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_NUMERIC_PARAM_ONLY(TRACE_GET_CLASS_EVENT_CODE(CREATE_OBJ, TRCFAILED, TASK, NOT_USED), 0); + +/* Called on vTaskDelete */ +#undef traceTASK_DELETE +#define traceTASK_DELETE( pxTaskToDelete ) \ + { TRACE_ALLOC_CRITICAL_SECTION(); \ + TRACE_ENTER_CRITICAL_SECTION(); \ + trcKERNEL_HOOKS_TASK_DELETE(TRACE_GET_OBJECT_EVENT_CODE(DELETE_OBJ, TRCSUCCESS, TASK, pxTaskToDelete), TRACE_GET_OBJECT_EVENT_CODE(OBJCLOSE_NAME, TRCSUCCESS, TASK, pxTaskToDelete), TRACE_GET_OBJECT_EVENT_CODE(OBJCLOSE_PROP, TRCSUCCESS, TASK, pxTaskToDelete), pxTaskToDelete); \ + TRACE_EXIT_CRITICAL_SECTION(); } + +#if (TRC_CFG_SCHEDULING_ONLY == 0) + +#if defined(configUSE_TICKLESS_IDLE) +#if (configUSE_TICKLESS_IDLE != 0) + +#undef traceLOW_POWER_IDLE_BEGIN +#define traceLOW_POWER_IDLE_BEGIN() \ + { \ + extern uint32_t trace_disable_timestamp; \ + prvTraceStoreLowPower(0); \ + trace_disable_timestamp = 1; \ + } + +#undef traceLOW_POWER_IDLE_END +#define traceLOW_POWER_IDLE_END() \ + { \ + extern uint32_t trace_disable_timestamp; \ + trace_disable_timestamp = 0; \ + prvTraceStoreLowPower(1); \ + } + +#endif /* (configUSE_TICKLESS_IDLE != 0) */ +#endif /* defined(configUSE_TICKLESS_IDLE) */ + +/* Called on vTaskSuspend */ +#undef traceTASK_SUSPEND +#define traceTASK_SUSPEND( pxTaskToSuspend ) \ + trcKERNEL_HOOKS_TASK_SUSPEND(TASK_SUSPEND, pxTaskToSuspend); + +/* Called from special case with timer only */ +#undef traceTASK_DELAY_SUSPEND +#define traceTASK_DELAY_SUSPEND( pxTaskToSuspend ) \ + trcKERNEL_HOOKS_TASK_SUSPEND(TASK_SUSPEND, pxTaskToSuspend); \ + trcKERNEL_HOOKS_SET_TASK_INSTANCE_FINISHED(); + +/* Called on vTaskDelay - note the use of FreeRTOS variable xTicksToDelay */ +#undef traceTASK_DELAY +#define traceTASK_DELAY() \ + trcKERNEL_HOOKS_TASK_DELAY(TASK_DELAY, pxCurrentTCB, xTicksToDelay); \ + trcKERNEL_HOOKS_SET_TASK_INSTANCE_FINISHED(); + +/* Called on vTaskDelayUntil - note the use of FreeRTOS variable xTimeToWake */ +#undef traceTASK_DELAY_UNTIL +#if TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_9_0_0 +#define traceTASK_DELAY_UNTIL(xTimeToWake) \ + trcKERNEL_HOOKS_TASK_DELAY(TASK_DELAY_UNTIL, pxCurrentTCB, xTimeToWake); \ + trcKERNEL_HOOKS_SET_TASK_INSTANCE_FINISHED(); +#else /* TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_9_0_0 */ +#define traceTASK_DELAY_UNTIL() \ + trcKERNEL_HOOKS_TASK_DELAY(TASK_DELAY_UNTIL, pxCurrentTCB, xTimeToWake); \ + trcKERNEL_HOOKS_SET_TASK_INSTANCE_FINISHED(); +#endif /* TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_9_0_0 */ + +/* Called in xQueueCreate, and thereby for all other object based on queues, such as semaphores. */ +#undef traceQUEUE_CREATE +#define traceQUEUE_CREATE( pxNewQueue ) \ + trcKERNEL_HOOKS_OBJECT_CREATE(TRACE_GET_OBJECT_EVENT_CODE(CREATE_OBJ, TRCSUCCESS, QUEUE, pxNewQueue), QUEUE, pxNewQueue); + +/* Called in xQueueCreate, if the queue creation fails */ +#undef traceQUEUE_CREATE_FAILED +#define traceQUEUE_CREATE_FAILED( queueType ) \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_NUMERIC_PARAM_ONLY(TRACE_GET_CLASS_EVENT_CODE(CREATE_OBJ, TRCFAILED, QUEUE, queueType), 0); + +/* Called on vQueueDelete */ +#undef traceQUEUE_DELETE +#define traceQUEUE_DELETE( pxQueue ) \ + { TRACE_ALLOC_CRITICAL_SECTION(); \ + TRACE_ENTER_CRITICAL_SECTION(); \ + trcKERNEL_HOOKS_OBJECT_DELETE(TRACE_GET_OBJECT_EVENT_CODE(DELETE_OBJ, TRCSUCCESS, QUEUE, pxQueue), TRACE_GET_OBJECT_EVENT_CODE(OBJCLOSE_NAME, TRCSUCCESS, QUEUE, pxQueue), TRACE_GET_OBJECT_EVENT_CODE(OBJCLOSE_PROP, TRCSUCCESS, QUEUE, pxQueue), QUEUE, pxQueue); \ + TRACE_EXIT_CRITICAL_SECTION(); } + +/* This macro is not necessary as of FreeRTOS v9.0.0 */ +#if (TRC_CFG_FREERTOS_VERSION < TRC_FREERTOS_VERSION_9_0_0) +/* Called in xQueueCreateMutex, and thereby also from xSemaphoreCreateMutex and xSemaphoreCreateRecursiveMutex */ +#undef traceCREATE_MUTEX +#define traceCREATE_MUTEX( pxNewQueue ) \ + trcKERNEL_HOOKS_OBJECT_CREATE(TRACE_GET_OBJECT_EVENT_CODE(CREATE_OBJ, TRCSUCCESS, QUEUE, pxNewQueue), QUEUE, pxNewQueue); + +/* Called in xQueueCreateMutex when the operation fails (when memory allocation fails) */ +#undef traceCREATE_MUTEX_FAILED +#define traceCREATE_MUTEX_FAILED() \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_NUMERIC_PARAM_ONLY(TRACE_GET_CLASS_EVENT_CODE(CREATE_OBJ, TRCFAILED, QUEUE, queueQUEUE_TYPE_MUTEX), 0); +#endif /* (TRC_CFG_FREERTOS_VERSION < TRC_FREERTOS_VERSION_9_0_0) */ + +/* Called when the Mutex can not be given, since not holder */ +#undef traceGIVE_MUTEX_RECURSIVE_FAILED +#define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ) \ + trcKERNEL_HOOKS_KERNEL_SERVICE(TRACE_GET_OBJECT_EVENT_CODE(SEND, TRCFAILED, QUEUE, pxMutex), QUEUE, pxMutex); + +/* Called when a message is sent to a queue */ /* CS IS NEW ! */ +#undef traceQUEUE_SEND +#define traceQUEUE_SEND( pxQueue ) \ + trcKERNEL_HOOKS_KERNEL_SERVICE(TRACE_GET_OBJECT_EVENT_CODE(SEND, TRCSUCCESS, QUEUE, pxQueue), QUEUE, pxQueue); \ + trcKERNEL_HOOKS_SET_OBJECT_STATE(QUEUE, pxQueue, TRACE_GET_OBJECT_TRACE_CLASS(QUEUE, pxQueue) == TRACE_CLASS_MUTEX ? (uint8_t)0 : (uint8_t)(pxQueue->uxMessagesWaiting + 1)); + +/* Called when a message failed to be sent to a queue (timeout) */ +#undef traceQUEUE_SEND_FAILED +#define traceQUEUE_SEND_FAILED( pxQueue ) \ + trcKERNEL_HOOKS_KERNEL_SERVICE(TRACE_GET_OBJECT_EVENT_CODE(SEND, TRCFAILED, QUEUE, pxQueue), QUEUE, pxQueue); + +/* Called when the task is blocked due to a send operation on a full queue */ +#undef traceBLOCKING_ON_QUEUE_SEND +#define traceBLOCKING_ON_QUEUE_SEND( pxQueue ) \ + trcKERNEL_HOOKS_KERNEL_SERVICE(TRACE_GET_OBJECT_EVENT_CODE(SEND, TRCBLOCK, QUEUE, pxQueue), QUEUE, pxQueue); + +/* Called when a message is received from a queue */ +#undef traceQUEUE_RECEIVE +#define traceQUEUE_RECEIVE( pxQueue ) \ + if (isQueueReceiveHookActuallyPeek) \ + { \ + trcKERNEL_HOOKS_KERNEL_SERVICE(TRACE_GET_OBJECT_EVENT_CODE(PEEK, TRCSUCCESS, QUEUE, pxQueue), QUEUE, pxQueue); \ + } \ + else \ + { \ + trcKERNEL_HOOKS_KERNEL_SERVICE(TRACE_GET_OBJECT_EVENT_CODE(RECEIVE, TRCSUCCESS, QUEUE, pxQueue), QUEUE, pxQueue); \ + } \ + trcKERNEL_HOOKS_SET_OBJECT_STATE(QUEUE, pxQueue, TRACE_GET_OBJECT_TRACE_CLASS(QUEUE, pxQueue) == TRACE_CLASS_MUTEX ? (uint8_t)TRACE_GET_TASK_NUMBER(TRACE_GET_CURRENT_TASK()) : (uint8_t)(pxQueue->uxMessagesWaiting - 1)); + +/* Called when a receive operation on a queue fails (timeout) */ +#undef traceQUEUE_RECEIVE_FAILED +#define traceQUEUE_RECEIVE_FAILED( pxQueue ) \ + if (isQueueReceiveHookActuallyPeek) \ + { \ + trcKERNEL_HOOKS_KERNEL_SERVICE(TRACE_GET_OBJECT_EVENT_CODE(PEEK, TRCFAILED, QUEUE, pxQueue), QUEUE, pxQueue); \ + } \ + else \ + { \ + trcKERNEL_HOOKS_KERNEL_SERVICE(TRACE_GET_OBJECT_EVENT_CODE(RECEIVE, TRCFAILED, QUEUE, pxQueue), QUEUE, pxQueue); \ + } + +/* Called when the task is blocked due to a receive operation on an empty queue */ +#undef traceBLOCKING_ON_QUEUE_RECEIVE +#define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ) \ + if (isQueueReceiveHookActuallyPeek) \ + { \ + trcKERNEL_HOOKS_KERNEL_SERVICE(TRACE_GET_OBJECT_EVENT_CODE(PEEK, TRCBLOCK, QUEUE, pxQueue), QUEUE, pxQueue); \ + } \ + else \ + { \ + trcKERNEL_HOOKS_KERNEL_SERVICE(TRACE_GET_OBJECT_EVENT_CODE(RECEIVE, TRCBLOCK, QUEUE, pxQueue), QUEUE, pxQueue); \ + } \ + if (TRACE_GET_OBJECT_TRACE_CLASS(QUEUE, pxQueue) != TRACE_CLASS_MUTEX) \ + { \ + trcKERNEL_HOOKS_SET_TASK_INSTANCE_FINISHED(); \ + } + +/* Called on xQueuePeek */ +#undef traceQUEUE_PEEK +#define traceQUEUE_PEEK( pxQueue ) \ + trcKERNEL_HOOKS_KERNEL_SERVICE(TRACE_GET_OBJECT_EVENT_CODE(PEEK, TRCSUCCESS, QUEUE, pxQueue), QUEUE, pxQueue); + +/* Called on xQueuePeek fail/timeout (added in FreeRTOS v9.0.2) */ +#undef traceQUEUE_PEEK_FAILED +#define traceQUEUE_PEEK_FAILED( pxQueue ) \ + trcKERNEL_HOOKS_KERNEL_SERVICE(TRACE_GET_OBJECT_EVENT_CODE(PEEK, TRCFAILED, QUEUE, pxQueue), QUEUE, pxQueue); + +/* Called on xQueuePeek blocking (added in FreeRTOS v9.0.2) */ +#undef traceBLOCKING_ON_QUEUE_PEEK +#define traceBLOCKING_ON_QUEUE_PEEK( pxQueue ) \ + trcKERNEL_HOOKS_KERNEL_SERVICE(TRACE_GET_OBJECT_EVENT_CODE(PEEK, TRCBLOCK, QUEUE, pxQueue), QUEUE, pxQueue); \ + if (TRACE_GET_OBJECT_TRACE_CLASS(QUEUE, pxQueue) != TRACE_CLASS_MUTEX) \ + { \ + trcKERNEL_HOOKS_SET_TASK_INSTANCE_FINISHED(); \ + } + +/* Called when a message is sent from interrupt context, e.g., using xQueueSendFromISR */ +#undef traceQUEUE_SEND_FROM_ISR +#define traceQUEUE_SEND_FROM_ISR( pxQueue ) \ + trcKERNEL_HOOKS_KERNEL_SERVICE_FROM_ISR(TRACE_GET_OBJECT_EVENT_CODE(SEND_FROM_ISR, TRCSUCCESS, QUEUE, pxQueue), QUEUE, pxQueue); \ + trcKERNEL_HOOKS_SET_OBJECT_STATE(QUEUE, pxQueue, (uint8_t)(pxQueue->uxMessagesWaiting + 1)); + +/* Called when a message send from interrupt context fails (since the queue was full) */ +#undef traceQUEUE_SEND_FROM_ISR_FAILED +#define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ) \ + trcKERNEL_HOOKS_KERNEL_SERVICE_FROM_ISR(TRACE_GET_OBJECT_EVENT_CODE(SEND_FROM_ISR, TRCFAILED, QUEUE, pxQueue), QUEUE, pxQueue); + +/* Called when a message is received in interrupt context, e.g., using xQueueReceiveFromISR */ +#undef traceQUEUE_RECEIVE_FROM_ISR +#define traceQUEUE_RECEIVE_FROM_ISR( pxQueue ) \ + trcKERNEL_HOOKS_KERNEL_SERVICE_FROM_ISR(TRACE_GET_OBJECT_EVENT_CODE(RECEIVE_FROM_ISR, TRCSUCCESS, QUEUE, pxQueue), QUEUE, pxQueue); \ + trcKERNEL_HOOKS_SET_OBJECT_STATE(QUEUE, pxQueue, (uint8_t)(pxQueue->uxMessagesWaiting - 1)); + +/* Called when a message receive from interrupt context fails (since the queue was empty) */ +#undef traceQUEUE_RECEIVE_FROM_ISR_FAILED +#define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ) \ + trcKERNEL_HOOKS_KERNEL_SERVICE_FROM_ISR(TRACE_GET_OBJECT_EVENT_CODE(RECEIVE_FROM_ISR, TRCFAILED, QUEUE, pxQueue), QUEUE, pxQueue); + +#undef traceQUEUE_REGISTRY_ADD +#define traceQUEUE_REGISTRY_ADD(object, name) prvTraceSetObjectName(TRACE_GET_OBJECT_TRACE_CLASS(QUEUE, object), TRACE_GET_OBJECT_NUMBER(QUEUE, object), name); + +/* Called in vTaskPrioritySet */ +#undef traceTASK_PRIORITY_SET +#define traceTASK_PRIORITY_SET( pxTask, uxNewPriority ) \ + trcKERNEL_HOOKS_TASK_PRIORITY_CHANGE(TASK_PRIORITY_SET, pxTask, uxNewPriority); + +/* Called in vTaskPriorityInherit, which is called by Mutex operations */ +#undef traceTASK_PRIORITY_INHERIT +#define traceTASK_PRIORITY_INHERIT( pxTask, uxNewPriority ) \ + trcKERNEL_HOOKS_TASK_PRIORITY_CHANGE(TASK_PRIORITY_INHERIT, pxTask, uxNewPriority); + +/* Called in vTaskPriorityDisinherit, which is called by Mutex operations */ +#undef traceTASK_PRIORITY_DISINHERIT +#define traceTASK_PRIORITY_DISINHERIT( pxTask, uxNewPriority ) \ + trcKERNEL_HOOKS_TASK_PRIORITY_CHANGE(TASK_PRIORITY_DISINHERIT, pxTask, uxNewPriority); + +/* Called in vTaskResume */ +#undef traceTASK_RESUME +#define traceTASK_RESUME( pxTaskToResume ) \ + trcKERNEL_HOOKS_TASK_RESUME(TASK_RESUME, pxTaskToResume); + +/* Called in vTaskResumeFromISR */ +#undef traceTASK_RESUME_FROM_ISR +#define traceTASK_RESUME_FROM_ISR( pxTaskToResume ) \ + trcKERNEL_HOOKS_TASK_RESUME_FROM_ISR(TASK_RESUME_FROM_ISR, pxTaskToResume); + + +#if (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_8_X) + +#if (TRC_CFG_INCLUDE_MEMMANG_EVENTS == 1) + +extern void vTraceStoreMemMangEvent(uint32_t ecode, uint32_t address, int32_t size); + +/* MALLOC and FREE are always stored, no matter if they happen inside filtered task */ +#undef traceMALLOC +#define traceMALLOC( pvAddress, uiSize ) \ + if (pvAddress != 0) \ + vTraceStoreMemMangEvent(MEM_MALLOC_SIZE, ( uint32_t ) pvAddress, (int32_t)uiSize); + +#undef traceFREE +#define traceFREE( pvAddress, uiSize ) \ + vTraceStoreMemMangEvent(MEM_FREE_SIZE, ( uint32_t ) pvAddress, -((int32_t)uiSize)); + +#endif /* (TRC_CFG_INCLUDE_MEMMANG_EVENTS == 1) */ + +#if (TRC_CFG_INCLUDE_TIMER_EVENTS == 1) + +/* Called in timer.c - xTimerCreate */ +#undef traceTIMER_CREATE +#define traceTIMER_CREATE(tmr) \ + trcKERNEL_HOOKS_OBJECT_CREATE(TIMER_CREATE, TIMER, tmr); + +#undef traceTIMER_CREATE_FAILED +#define traceTIMER_CREATE_FAILED() \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_NUMERIC_PARAM_ONLY(TIMER_CREATE_TRCFAILED, 0); + +/* Note that xCommandID can never be tmrCOMMAND_EXECUTE_CALLBACK (-1) since the trace macro is not called in that case */ +#undef traceTIMER_COMMAND_SEND +#define traceTIMER_COMMAND_SEND(tmr, xCommandID, xOptionalValue, xReturn) \ + if (xCommandID > tmrCOMMAND_START_DONT_TRACE) \ + { \ + if (xCommandID == tmrCOMMAND_CHANGE_PERIOD) \ + { \ + if (xReturn == pdPASS) { \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_PARAM(TIMER_CHANGE_PERIOD, TIMER, tmr, xOptionalValue); \ + } \ + else \ + { \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_PARAM(TIMER_CHANGE_PERIOD_TRCFAILED, TIMER, tmr, xOptionalValue); \ + } \ + } \ + else if ((xCommandID == tmrCOMMAND_DELETE) && (xReturn == pdPASS)) \ + { \ + trcKERNEL_HOOKS_OBJECT_DELETE(TIMER_DELETE_OBJ, EVENTGROUP_OBJCLOSE_NAME_TRCSUCCESS + TRACE_GET_OBJECT_TRACE_CLASS(TIMER, tmr), EVENTGROUP_OBJCLOSE_PROP_TRCSUCCESS + TRACE_GET_OBJECT_TRACE_CLASS(TIMER, tmr), TIMER, tmr); \ + } \ + else \ + { \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_PARAM(EVENTGROUP_TIMER + (uint32_t)xCommandID + ((xReturn == pdPASS) ? 0 : (TIMER_CREATE_TRCFAILED - TIMER_CREATE)), TIMER, tmr, xOptionalValue); \ + }\ + } + +#undef traceTIMER_EXPIRED +#define traceTIMER_EXPIRED(tmr) \ + trcKERNEL_HOOKS_KERNEL_SERVICE(TIMER_EXPIRED, TIMER, tmr); + +#endif /* (TRC_CFG_INCLUDE_TIMER_EVENTS == 1) */ + +#if (TRC_CFG_INCLUDE_PEND_FUNC_CALL_EVENTS == 1) + +#undef tracePEND_FUNC_CALL +#define tracePEND_FUNC_CALL(func, arg1, arg2, ret) \ + if (ret == pdPASS){ \ + trcKERNEL_HOOKS_KERNEL_SERVICE(PEND_FUNC_CALL, TASK, xTimerGetTimerDaemonTaskHandle() ); \ + } \ + else \ + { \ + trcKERNEL_HOOKS_KERNEL_SERVICE(PEND_FUNC_CALL_TRCFAILED, TASK, xTimerGetTimerDaemonTaskHandle() ); \ + } + +#undef tracePEND_FUNC_CALL_FROM_ISR +#define tracePEND_FUNC_CALL_FROM_ISR(func, arg1, arg2, ret) \ + if (! uiInEventGroupSetBitsFromISR) \ + prvTraceStoreKernelCall(PEND_FUNC_CALL_FROM_ISR, TRACE_CLASS_TASK, TRACE_GET_TASK_NUMBER(xTimerGetTimerDaemonTaskHandle()) ); \ + uiInEventGroupSetBitsFromISR = 0; + +#endif /* (TRC_CFG_INCLUDE_PEND_FUNC_CALL_EVENTS == 1) */ + +#endif /* (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_8_X) */ + +#if (TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS == 1) + +#undef traceEVENT_GROUP_CREATE +#define traceEVENT_GROUP_CREATE(eg) \ + trcKERNEL_HOOKS_OBJECT_CREATE(EVENT_GROUP_CREATE, EVENTGROUP, eg); + +#undef traceEVENT_GROUP_CREATE_FAILED +#define traceEVENT_GROUP_CREATE_FAILED() \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_NUMERIC_PARAM_ONLY(EVENT_GROUP_CREATE_TRCFAILED, 0); + +#undef traceEVENT_GROUP_DELETE +#define traceEVENT_GROUP_DELETE(eg) \ + { TRACE_ALLOC_CRITICAL_SECTION(); \ + TRACE_ENTER_CRITICAL_SECTION(); \ + trcKERNEL_HOOKS_OBJECT_DELETE(EVENT_GROUP_DELETE_OBJ, EVENTGROUP_OBJCLOSE_NAME_TRCSUCCESS + TRACE_GET_OBJECT_TRACE_CLASS(EVENTGROUP, eg), EVENTGROUP_OBJCLOSE_NAME_TRCSUCCESS + TRACE_GET_OBJECT_TRACE_CLASS(EVENTGROUP, eg), EVENTGROUP, eg); \ + TRACE_EXIT_CRITICAL_SECTION(); } + +#undef traceEVENT_GROUP_SYNC_BLOCK +#define traceEVENT_GROUP_SYNC_BLOCK(eg, bitsToSet, bitsToWaitFor) \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_PARAM(EVENT_GROUP_SYNC_TRCBLOCK, EVENTGROUP, eg, bitsToWaitFor); + +#undef traceEVENT_GROUP_SYNC_END +#define traceEVENT_GROUP_SYNC_END(eg, bitsToSet, bitsToWaitFor, wasTimeout) \ + if (wasTimeout) \ + { \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_PARAM(EVENT_GROUP_SYNC_END_TRCFAILED, EVENTGROUP, eg, bitsToWaitFor); \ + } \ + else \ + { \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_PARAM(EVENT_GROUP_SYNC_END, EVENTGROUP, eg, bitsToWaitFor); \ + } + +#undef traceEVENT_GROUP_WAIT_BITS_BLOCK +#define traceEVENT_GROUP_WAIT_BITS_BLOCK(eg, bitsToWaitFor) \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_PARAM(EVENT_GROUP_WAIT_BITS_TRCBLOCK, EVENTGROUP, eg, bitsToWaitFor); \ + trcKERNEL_HOOKS_SET_TASK_INSTANCE_FINISHED(); + +#undef traceEVENT_GROUP_WAIT_BITS_END +#define traceEVENT_GROUP_WAIT_BITS_END(eg, bitsToWaitFor, wasTimeout) \ + if (wasTimeout) \ + { \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_PARAM(EVENT_GROUP_WAIT_BITS_END_TRCFAILED, EVENTGROUP, eg, bitsToWaitFor); \ + } \ + else \ + { \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_PARAM(EVENT_GROUP_WAIT_BITS_END, EVENTGROUP, eg, bitsToWaitFor); \ + } + +#undef traceEVENT_GROUP_CLEAR_BITS +#define traceEVENT_GROUP_CLEAR_BITS(eg, bitsToClear) \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_PARAM(EVENT_GROUP_CLEAR_BITS, EVENTGROUP, eg, bitsToClear); + +#undef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR +#define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR(eg, bitsToClear) \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_PARAM_FROM_ISR(EVENT_GROUP_CLEAR_BITS_FROM_ISR, EVENTGROUP, eg, bitsToClear); + +#undef traceEVENT_GROUP_SET_BITS +#define traceEVENT_GROUP_SET_BITS(eg, bitsToSet) \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_PARAM(EVENT_GROUP_SET_BITS, EVENTGROUP, eg, bitsToSet); + +#undef traceEVENT_GROUP_SET_BITS_FROM_ISR +#define traceEVENT_GROUP_SET_BITS_FROM_ISR(eg, bitsToSet) \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_PARAM_FROM_ISR(EVENT_GROUP_SET_BITS_FROM_ISR, EVENTGROUP, eg, bitsToSet); \ + uiInEventGroupSetBitsFromISR = 1; + +#endif /* (TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS == 1) */ + +#undef traceTASK_NOTIFY_TAKE +#if (TRC_CFG_FREERTOS_VERSION < TRC_FREERTOS_VERSION_9_0_0) +#define traceTASK_NOTIFY_TAKE() \ + if (pxCurrentTCB->eNotifyState == eNotified){ \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_PARAM(TRACE_TASK_NOTIFY_TAKE, TASK, pxCurrentTCB, xTicksToWait); \ + } \ + else{ \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_PARAM(TRACE_TASK_NOTIFY_TAKE_TRCFAILED, TASK, pxCurrentTCB, xTicksToWait); \ + } +#else /* TRC_CFG_FREERTOS_VERSION < TRC_FREERTOS_VERSION_9_0_0 */ +#define traceTASK_NOTIFY_TAKE() \ + if (pxCurrentTCB->ucNotifyState == taskNOTIFICATION_RECEIVED){ \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_PARAM(TRACE_TASK_NOTIFY_TAKE, TASK, pxCurrentTCB, xTicksToWait); \ + }else{ \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_PARAM(TRACE_TASK_NOTIFY_TAKE_TRCFAILED, TASK, pxCurrentTCB, xTicksToWait);} +#endif /* TRC_CFG_FREERTOS_VERSION < TRC_FREERTOS_VERSION_9_0_0 */ + +#undef traceTASK_NOTIFY_TAKE_BLOCK +#define traceTASK_NOTIFY_TAKE_BLOCK() \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_PARAM(TRACE_TASK_NOTIFY_TAKE_TRCBLOCK, TASK, pxCurrentTCB, xTicksToWait); \ + trcKERNEL_HOOKS_SET_TASK_INSTANCE_FINISHED(); + +#undef traceTASK_NOTIFY_WAIT +#if (TRC_CFG_FREERTOS_VERSION < TRC_FREERTOS_VERSION_9_0_0) +#define traceTASK_NOTIFY_WAIT() \ + if (TRACE_GET_OBJECT_FILTER(TASK, pxCurrentTCB) & CurrentFilterMask) \ + { \ + if (pxCurrentTCB->eNotifyState == eNotified) \ + prvTraceStoreKernelCallWithParam(TRACE_TASK_NOTIFY_WAIT, TRACE_CLASS_TASK, TRACE_GET_TASK_NUMBER(pxCurrentTCB), xTicksToWait); \ + else \ + prvTraceStoreKernelCallWithParam(TRACE_TASK_NOTIFY_WAIT_TRCFAILED, TRACE_CLASS_TASK, TRACE_GET_TASK_NUMBER(pxCurrentTCB), xTicksToWait); \ + } +#else /* TRC_CFG_FREERTOS_VERSION < TRC_FREERTOS_VERSION_9_0_0 */ +#define traceTASK_NOTIFY_WAIT() \ + if (TRACE_GET_OBJECT_FILTER(TASK, pxCurrentTCB) & CurrentFilterMask) \ + { \ + if (pxCurrentTCB->ucNotifyState == taskNOTIFICATION_RECEIVED) \ + prvTraceStoreKernelCallWithParam(TRACE_TASK_NOTIFY_WAIT, TRACE_CLASS_TASK, TRACE_GET_TASK_NUMBER(pxCurrentTCB), xTicksToWait); \ + else \ + prvTraceStoreKernelCallWithParam(TRACE_TASK_NOTIFY_WAIT_TRCFAILED, TRACE_CLASS_TASK, TRACE_GET_TASK_NUMBER(pxCurrentTCB), xTicksToWait); \ + } +#endif /* TRC_CFG_FREERTOS_VERSION < TRC_FREERTOS_VERSION_9_0_0 */ + +#undef traceTASK_NOTIFY_WAIT_BLOCK +#define traceTASK_NOTIFY_WAIT_BLOCK() \ + if (TRACE_GET_OBJECT_FILTER(TASK, pxCurrentTCB) & CurrentFilterMask) \ + prvTraceStoreKernelCallWithParam(TRACE_TASK_NOTIFY_WAIT_TRCBLOCK, TRACE_CLASS_TASK, TRACE_GET_TASK_NUMBER(pxCurrentTCB), xTicksToWait); \ + trcKERNEL_HOOKS_SET_TASK_INSTANCE_FINISHED(); + +#undef traceTASK_NOTIFY +#define traceTASK_NOTIFY() \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(TASK, xTaskToNotify) & CurrentFilterMask) \ + prvTraceStoreKernelCall(TRACE_TASK_NOTIFY, TRACE_CLASS_TASK, TRACE_GET_TASK_NUMBER(xTaskToNotify)); + +#undef traceTASK_NOTIFY_FROM_ISR +#define traceTASK_NOTIFY_FROM_ISR() \ + if (TRACE_GET_OBJECT_FILTER(TASK, xTaskToNotify) & CurrentFilterMask) \ + prvTraceStoreKernelCall(TRACE_TASK_NOTIFY_FROM_ISR, TRACE_CLASS_TASK, TRACE_GET_TASK_NUMBER(xTaskToNotify)); + +#undef traceTASK_NOTIFY_GIVE_FROM_ISR +#define traceTASK_NOTIFY_GIVE_FROM_ISR() \ + if (TRACE_GET_OBJECT_FILTER(TASK, xTaskToNotify) & CurrentFilterMask) \ + prvTraceStoreKernelCall(TRACE_TASK_NOTIFY_GIVE_FROM_ISR, TRACE_CLASS_TASK, TRACE_GET_TASK_NUMBER(xTaskToNotify)); + +#if (TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS == 1) + +#undef traceSTREAM_BUFFER_CREATE +#define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer ) \ + trcKERNEL_HOOKS_OBJECT_CREATE(TRACE_GET_OBJECT_EVENT_CODE(CREATE_OBJ, TRCSUCCESS, STREAMBUFFER, pxStreamBuffer), STREAMBUFFER, pxStreamBuffer); + +#undef traceSTREAM_BUFFER_CREATE_FAILED +#define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ) \ + trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_NUMERIC_PARAM_ONLY(TRACE_GET_CLASS_EVENT_CODE(CREATE_OBJ, TRCFAILED, STREAMBUFFER, xIsMessageBuffer), 0); + +#undef traceSTREAM_BUFFER_CREATE_STATIC_FAILED +#define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer ) \ + traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ) + +#undef traceSTREAM_BUFFER_DELETE +#define traceSTREAM_BUFFER_DELETE( xStreamBuffer ) \ + trcKERNEL_HOOKS_OBJECT_DELETE(TRACE_GET_OBJECT_EVENT_CODE(DELETE_OBJ, TRCSUCCESS, STREAMBUFFER, xStreamBuffer), TRACE_GET_OBJECT_EVENT_CODE(OBJCLOSE_NAME, TRCSUCCESS, STREAMBUFFER, xStreamBuffer), TRACE_GET_OBJECT_EVENT_CODE(OBJCLOSE_PROP, TRCSUCCESS, STREAMBUFFER, xStreamBuffer), STREAMBUFFER, xStreamBuffer); + +#undef traceSTREAM_BUFFER_RESET +#define traceSTREAM_BUFFER_RESET( xStreamBuffer ) \ + trcKERNEL_HOOKS_KERNEL_SERVICE(prvGetStreamBufferType(xStreamBuffer) > 0 ? TRACE_MESSAGEBUFFER_RESET : TRACE_STREAMBUFFER_RESET, STREAMBUFFER, xStreamBuffer); \ + trcKERNEL_HOOKS_SET_OBJECT_STATE(STREAMBUFFER, xStreamBuffer, 0); + +#undef traceSTREAM_BUFFER_SEND +#define traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn ) \ + trcKERNEL_HOOKS_KERNEL_SERVICE(TRACE_GET_OBJECT_EVENT_CODE(SEND, TRCSUCCESS, STREAMBUFFER, xStreamBuffer), STREAMBUFFER, xStreamBuffer); \ + trcKERNEL_HOOKS_SET_OBJECT_STATE(STREAMBUFFER, xStreamBuffer, prvBytesInBuffer(xStreamBuffer)); + +#undef traceBLOCKING_ON_STREAM_BUFFER_SEND +#define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ) \ + trcKERNEL_HOOKS_KERNEL_SERVICE(TRACE_GET_OBJECT_EVENT_CODE(SEND, TRCBLOCK, STREAMBUFFER, xStreamBuffer), STREAMBUFFER, xStreamBuffer); + +#undef traceSTREAM_BUFFER_SEND_FAILED +#define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ) \ + trcKERNEL_HOOKS_KERNEL_SERVICE(TRACE_GET_OBJECT_EVENT_CODE(SEND, TRCFAILED, STREAMBUFFER, xStreamBuffer), STREAMBUFFER, xStreamBuffer); + +#undef traceSTREAM_BUFFER_RECEIVE +#define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength ) \ + trcKERNEL_HOOKS_KERNEL_SERVICE(TRACE_GET_OBJECT_EVENT_CODE(RECEIVE, TRCSUCCESS, STREAMBUFFER, xStreamBuffer), STREAMBUFFER, xStreamBuffer); \ + trcKERNEL_HOOKS_SET_OBJECT_STATE(STREAMBUFFER, xStreamBuffer, prvBytesInBuffer(xStreamBuffer)); + + +#undef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE +#define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ) \ + trcKERNEL_HOOKS_KERNEL_SERVICE(TRACE_GET_OBJECT_EVENT_CODE(RECEIVE, TRCBLOCK, STREAMBUFFER, xStreamBuffer), STREAMBUFFER, xStreamBuffer); + +#undef traceSTREAM_BUFFER_RECEIVE_FAILED +#define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer ) \ + trcKERNEL_HOOKS_KERNEL_SERVICE(TRACE_GET_OBJECT_EVENT_CODE(RECEIVE, TRCFAILED, STREAMBUFFER, xStreamBuffer), STREAMBUFFER, xStreamBuffer); + +#undef traceSTREAM_BUFFER_SEND_FROM_ISR +#define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn ) \ + if( xReturn > ( size_t ) 0 ) \ + { \ + trcKERNEL_HOOKS_KERNEL_SERVICE_FROM_ISR(TRACE_GET_OBJECT_EVENT_CODE(SEND_FROM_ISR, TRCSUCCESS, STREAMBUFFER, xStreamBuffer), STREAMBUFFER, xStreamBuffer); \ + trcKERNEL_HOOKS_SET_OBJECT_STATE(STREAMBUFFER, xStreamBuffer, prvBytesInBuffer(xStreamBuffer)); \ + } \ + else \ + { \ + trcKERNEL_HOOKS_KERNEL_SERVICE_FROM_ISR(TRACE_GET_OBJECT_EVENT_CODE(SEND_FROM_ISR, TRCFAILED, STREAMBUFFER, xStreamBuffer), STREAMBUFFER, xStreamBuffer); \ + } + +#undef traceSTREAM_BUFFER_RECEIVE_FROM_ISR +#define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ) \ + if( xReceivedLength > ( size_t ) 0 ) \ + { \ + trcKERNEL_HOOKS_KERNEL_SERVICE_FROM_ISR(TRACE_GET_OBJECT_EVENT_CODE(RECEIVE_FROM_ISR, TRCSUCCESS, STREAMBUFFER, xStreamBuffer), STREAMBUFFER, xStreamBuffer); \ + trcKERNEL_HOOKS_SET_OBJECT_STATE(STREAMBUFFER, xStreamBuffer, prvBytesInBuffer(xStreamBuffer)); \ + } \ + else \ + { \ + trcKERNEL_HOOKS_KERNEL_SERVICE_FROM_ISR(TRACE_GET_OBJECT_EVENT_CODE(RECEIVE_FROM_ISR, TRCFAILED, STREAMBUFFER, xStreamBuffer), STREAMBUFFER, xStreamBuffer); \ + } + +#endif /* (TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS == 1) */ + +#endif /* (TRC_CFG_SCHEDULING_ONLY == 0) */ + +#endif /*#if TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_SNAPSHOT */ + +/******************************************************************************/ +/*** Definitions for Streaming mode *******************************************/ +/******************************************************************************/ +#if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING) + +/******************************************************************************* +* vTraceStoreKernelObjectName +* +* Set the name for a kernel object (defined by its address). +******************************************************************************/ +void vTraceStoreKernelObjectName(void* object, const char* name); + +/******************************************************************************* +* prvIsNewTCB +* +* Tells if this task is already executing, or if there has been a task-switch. +* Assumed to be called within a trace hook in kernel context. +*******************************************************************************/ +uint32_t prvIsNewTCB(void* pNewTCB); + +#define TRACE_GET_CURRENT_TASK() prvTraceGetCurrentTaskHandle() + +/*************************************************************************/ +/* KERNEL SPECIFIC OBJECT CONFIGURATION */ +/*************************************************************************/ + +/******************************************************************************* + * The event codes - should match the offline config file. + ******************************************************************************/ + +/*** Event codes for streaming - should match the Tracealyzer config file *****/ +#define PSF_EVENT_NULL_EVENT 0x00 + +#define PSF_EVENT_TRACE_START 0x01 +#define PSF_EVENT_TS_CONFIG 0x02 +#define PSF_EVENT_OBJ_NAME 0x03 +#define PSF_EVENT_TASK_PRIORITY 0x04 +#define PSF_EVENT_TASK_PRIO_INHERIT 0x05 +#define PSF_EVENT_TASK_PRIO_DISINHERIT 0x06 +#define PSF_EVENT_DEFINE_ISR 0x07 + +#define PSF_EVENT_TASK_CREATE 0x10 +#define PSF_EVENT_QUEUE_CREATE 0x11 +#define PSF_EVENT_SEMAPHORE_BINARY_CREATE 0x12 +#define PSF_EVENT_MUTEX_CREATE 0x13 +#define PSF_EVENT_TIMER_CREATE 0x14 +#define PSF_EVENT_EVENTGROUP_CREATE 0x15 +#define PSF_EVENT_SEMAPHORE_COUNTING_CREATE 0x16 +#define PSF_EVENT_MUTEX_RECURSIVE_CREATE 0x17 +#define PSF_EVENT_STREAMBUFFER_CREATE 0x18 +#define PSF_EVENT_MESSAGEBUFFER_CREATE 0x19 + +#define PSF_EVENT_TASK_DELETE 0x20 +#define PSF_EVENT_QUEUE_DELETE 0x21 +#define PSF_EVENT_SEMAPHORE_DELETE 0x22 +#define PSF_EVENT_MUTEX_DELETE 0x23 +#define PSF_EVENT_TIMER_DELETE 0x24 +#define PSF_EVENT_EVENTGROUP_DELETE 0x25 +#define PSF_EVENT_STREAMBUFFER_DELETE 0x28 +#define PSF_EVENT_MESSAGEBUFFER_DELETE 0x29 + +#define PSF_EVENT_TASK_READY 0x30 +#define PSF_EVENT_NEW_TIME 0x31 +#define PSF_EVENT_NEW_TIME_SCHEDULER_SUSPENDED 0x32 +#define PSF_EVENT_ISR_BEGIN 0x33 +#define PSF_EVENT_ISR_RESUME 0x34 +#define PSF_EVENT_TS_BEGIN 0x35 +#define PSF_EVENT_TS_RESUME 0x36 +#define PSF_EVENT_TASK_ACTIVATE 0x37 + +#define PSF_EVENT_MALLOC 0x38 +#define PSF_EVENT_FREE 0x39 + +#define PSF_EVENT_LOWPOWER_BEGIN 0x3A +#define PSF_EVENT_LOWPOWER_END 0x3B + +#define PSF_EVENT_IFE_NEXT 0x3C +#define PSF_EVENT_IFE_DIRECT 0x3D + +#define PSF_EVENT_TASK_CREATE_FAILED 0x40 +#define PSF_EVENT_QUEUE_CREATE_FAILED 0x41 +#define PSF_EVENT_SEMAPHORE_BINARY_CREATE_FAILED 0x42 +#define PSF_EVENT_MUTEX_CREATE_FAILED 0x43 +#define PSF_EVENT_TIMER_CREATE_FAILED 0x44 +#define PSF_EVENT_EVENTGROUP_CREATE_FAILED 0x45 +#define PSF_EVENT_SEMAPHORE_COUNTING_CREATE_FAILED 0x46 +#define PSF_EVENT_MUTEX_RECURSIVE_CREATE_FAILED 0x47 +#define PSF_EVENT_STREAMBUFFER_CREATE_FAILED 0x49 +#define PSF_EVENT_MESSAGEBUFFER_CREATE_FAILED 0x4A + +#define PSF_EVENT_TIMER_DELETE_FAILED 0x48 + +#define PSF_EVENT_QUEUE_SEND 0x50 +#define PSF_EVENT_SEMAPHORE_GIVE 0x51 +#define PSF_EVENT_MUTEX_GIVE 0x52 + +#define PSF_EVENT_QUEUE_SEND_FAILED 0x53 +#define PSF_EVENT_SEMAPHORE_GIVE_FAILED 0x54 +#define PSF_EVENT_MUTEX_GIVE_FAILED 0x55 + +#define PSF_EVENT_QUEUE_SEND_BLOCK 0x56 +#define PSF_EVENT_SEMAPHORE_GIVE_BLOCK 0x57 +#define PSF_EVENT_MUTEX_GIVE_BLOCK 0x58 + +#define PSF_EVENT_QUEUE_SEND_FROMISR 0x59 +#define PSF_EVENT_SEMAPHORE_GIVE_FROMISR 0x5A + +#define PSF_EVENT_QUEUE_SEND_FROMISR_FAILED 0x5C +#define PSF_EVENT_SEMAPHORE_GIVE_FROMISR_FAILED 0x5D + +#define PSF_EVENT_QUEUE_RECEIVE 0x60 +#define PSF_EVENT_SEMAPHORE_TAKE 0x61 +#define PSF_EVENT_MUTEX_TAKE 0x62 + +#define PSF_EVENT_QUEUE_RECEIVE_FAILED 0x63 +#define PSF_EVENT_SEMAPHORE_TAKE_FAILED 0x64 +#define PSF_EVENT_MUTEX_TAKE_FAILED 0x65 + +#define PSF_EVENT_QUEUE_RECEIVE_BLOCK 0x66 +#define PSF_EVENT_SEMAPHORE_TAKE_BLOCK 0x67 +#define PSF_EVENT_MUTEX_TAKE_BLOCK 0x68 + +#define PSF_EVENT_QUEUE_RECEIVE_FROMISR 0x69 +#define PSF_EVENT_SEMAPHORE_TAKE_FROMISR 0x6A + +#define PSF_EVENT_QUEUE_RECEIVE_FROMISR_FAILED 0x6C +#define PSF_EVENT_SEMAPHORE_TAKE_FROMISR_FAILED 0x6D + +#define PSF_EVENT_QUEUE_PEEK 0x70 +#define PSF_EVENT_SEMAPHORE_PEEK 0x71 +#define PSF_EVENT_MUTEX_PEEK 0x72 + +#define PSF_EVENT_QUEUE_PEEK_FAILED 0x73 +#define PSF_EVENT_SEMAPHORE_PEEK_FAILED 0x74 +#define PSF_EVENT_MUTEX_PEEK_FAILED 0x75 + +#define PSF_EVENT_QUEUE_PEEK_BLOCK 0x76 +#define PSF_EVENT_SEMAPHORE_PEEK_BLOCK 0x77 +#define PSF_EVENT_MUTEX_PEEK_BLOCK 0x78 + +#define PSF_EVENT_TASK_DELAY_UNTIL 0x79 +#define PSF_EVENT_TASK_DELAY 0x7A +#define PSF_EVENT_TASK_SUSPEND 0x7B +#define PSF_EVENT_TASK_RESUME 0x7C +#define PSF_EVENT_TASK_RESUME_FROMISR 0x7D + +#define PSF_EVENT_TIMER_PENDFUNCCALL 0x80 +#define PSF_EVENT_TIMER_PENDFUNCCALL_FROMISR 0x81 +#define PSF_EVENT_TIMER_PENDFUNCCALL_FAILED 0x82 +#define PSF_EVENT_TIMER_PENDFUNCCALL_FROMISR_FAILED 0x83 + +#define PSF_EVENT_USER_EVENT 0x90 + +#define PSF_EVENT_TIMER_START 0xA0 +#define PSF_EVENT_TIMER_RESET 0xA1 +#define PSF_EVENT_TIMER_STOP 0xA2 +#define PSF_EVENT_TIMER_CHANGEPERIOD 0xA3 +#define PSF_EVENT_TIMER_START_FROMISR 0xA4 +#define PSF_EVENT_TIMER_RESET_FROMISR 0xA5 +#define PSF_EVENT_TIMER_STOP_FROMISR 0xA6 +#define PSF_EVENT_TIMER_CHANGEPERIOD_FROMISR 0xA7 +#define PSF_EVENT_TIMER_START_FAILED 0xA8 +#define PSF_EVENT_TIMER_RESET_FAILED 0xA9 +#define PSF_EVENT_TIMER_STOP_FAILED 0xAA +#define PSF_EVENT_TIMER_CHANGEPERIOD_FAILED 0xAB +#define PSF_EVENT_TIMER_START_FROMISR_FAILED 0xAC +#define PSF_EVENT_TIMER_RESET_FROMISR_FAILED 0xAD +#define PSF_EVENT_TIMER_STOP_FROMISR_FAILED 0xAE +#define PSF_EVENT_TIMER_CHANGEPERIOD_FROMISR_FAILED 0xAF + +#define PSF_EVENT_EVENTGROUP_SYNC 0xB0 +#define PSF_EVENT_EVENTGROUP_WAITBITS 0xB1 +#define PSF_EVENT_EVENTGROUP_CLEARBITS 0xB2 +#define PSF_EVENT_EVENTGROUP_CLEARBITS_FROMISR 0xB3 +#define PSF_EVENT_EVENTGROUP_SETBITS 0xB4 +#define PSF_EVENT_EVENTGROUP_SETBITS_FROMISR 0xB5 +#define PSF_EVENT_EVENTGROUP_SYNC_BLOCK 0xB6 +#define PSF_EVENT_EVENTGROUP_WAITBITS_BLOCK 0xB7 +#define PSF_EVENT_EVENTGROUP_SYNC_FAILED 0xB8 +#define PSF_EVENT_EVENTGROUP_WAITBITS_FAILED 0xB9 + +#define PSF_EVENT_QUEUE_SEND_FRONT 0xC0 +#define PSF_EVENT_QUEUE_SEND_FRONT_FAILED 0xC1 +#define PSF_EVENT_QUEUE_SEND_FRONT_BLOCK 0xC2 +#define PSF_EVENT_QUEUE_SEND_FRONT_FROMISR 0xC3 +#define PSF_EVENT_QUEUE_SEND_FRONT_FROMISR_FAILED 0xC4 +#define PSF_EVENT_MUTEX_GIVE_RECURSIVE 0xC5 +#define PSF_EVENT_MUTEX_GIVE_RECURSIVE_FAILED 0xC6 +#define PSF_EVENT_MUTEX_TAKE_RECURSIVE 0xC7 +#define PSF_EVENT_MUTEX_TAKE_RECURSIVE_FAILED 0xC8 + +#define PSF_EVENT_TASK_NOTIFY 0xC9 +#define PSF_EVENT_TASK_NOTIFY_TAKE 0xCA +#define PSF_EVENT_TASK_NOTIFY_TAKE_BLOCK 0xCB +#define PSF_EVENT_TASK_NOTIFY_TAKE_FAILED 0xCC +#define PSF_EVENT_TASK_NOTIFY_WAIT 0xCD +#define PSF_EVENT_TASK_NOTIFY_WAIT_BLOCK 0xCE +#define PSF_EVENT_TASK_NOTIFY_WAIT_FAILED 0xCF +#define PSF_EVENT_TASK_NOTIFY_FROM_ISR 0xD0 +#define PSF_EVENT_TASK_NOTIFY_GIVE_FROM_ISR 0xD1 + +#define PSF_EVENT_TIMER_EXPIRED 0xD2 + +#define PSF_EVENT_STREAMBUFFER_SEND 0xD3 +#define PSF_EVENT_STREAMBUFFER_SEND_BLOCK 0xD4 +#define PSF_EVENT_STREAMBUFFER_SEND_FAILED 0xD5 +#define PSF_EVENT_STREAMBUFFER_RECEIVE 0xD6 +#define PSF_EVENT_STREAMBUFFER_RECEIVE_BLOCK 0xD7 +#define PSF_EVENT_STREAMBUFFER_RECEIVE_FAILED 0xD8 +#define PSF_EVENT_STREAMBUFFER_SEND_FROM_ISR 0xD9 +#define PSF_EVENT_STREAMBUFFER_SEND_FROM_ISR_FAILED 0xDA +#define PSF_EVENT_STREAMBUFFER_RECEIVE_FROM_ISR 0xDB +#define PSF_EVENT_STREAMBUFFER_RECEIVE_FROM_ISR_FAILED 0xDC +#define PSF_EVENT_STREAMBUFFER_RESET 0xDD + +#define PSF_EVENT_MESSAGEBUFFER_SEND 0xDE +#define PSF_EVENT_MESSAGEBUFFER_SEND_BLOCK 0xDF +#define PSF_EVENT_MESSAGEBUFFER_SEND_FAILED 0xE0 +#define PSF_EVENT_MESSAGEBUFFER_RECEIVE 0xE1 +#define PSF_EVENT_MESSAGEBUFFER_RECEIVE_BLOCK 0xE2 +#define PSF_EVENT_MESSAGEBUFFER_RECEIVE_FAILED 0xE3 +#define PSF_EVENT_MESSAGEBUFFER_SEND_FROM_ISR 0xE4 +#define PSF_EVENT_MESSAGEBUFFER_SEND_FROM_ISR_FAILED 0xE5 +#define PSF_EVENT_MESSAGEBUFFER_RECEIVE_FROM_ISR 0xE6 +#define PSF_EVENT_MESSAGEBUFFER_RECEIVE_FROM_ISR_FAILED 0xE7 +#define PSF_EVENT_MESSAGEBUFFER_RESET 0xE8 + +/*** The trace macros for streaming ******************************************/ + +/* A macro that will update the tick count when returning from tickless idle */ +#undef traceINCREASE_TICK_COUNT +/* Note: This can handle time adjustments of max 2^32 ticks, i.e., 35 seconds at 120 MHz. Thus, tick-less idle periods longer than 2^32 ticks will appear "compressed" on the time line.*/ +#define traceINCREASE_TICK_COUNT( xCount ) { extern uint32_t uiTraceTickCount; uiTraceTickCount += xCount; } + +#if (TRC_CFG_INCLUDE_OSTICK_EVENTS == 1) +#define OS_TICK_EVENT(uxSchedulerSuspended, xTickCount) if (uxSchedulerSuspended == (unsigned portBASE_TYPE) pdFALSE) { prvTraceStoreEvent1(PSF_EVENT_NEW_TIME, (uint32_t)(xTickCount + 1)); } +#else +#define OS_TICK_EVENT(uxSchedulerSuspended, xTickCount) +#endif + +/* Called on each OS tick. Will call uiPortGetTimestamp to make sure it is called at least once every OS tick. */ +#undef traceTASK_INCREMENT_TICK +#if TRC_CFG_FREERTOS_VERSION <= TRC_FREERTOS_VERSION_7_4 +#define traceTASK_INCREMENT_TICK( xTickCount ) \ + if (uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdTRUE || uxMissedTicks == 0) { extern uint32_t uiTraceTickCount; uiTraceTickCount++; } \ + OS_TICK_EVENT(uxSchedulerSuspended, xTickCount) +#else +#define traceTASK_INCREMENT_TICK( xTickCount ) \ + if (uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdTRUE || uxPendedTicks == 0) { extern uint32_t uiTraceTickCount; uiTraceTickCount++; } \ + OS_TICK_EVENT(uxSchedulerSuspended, xTickCount) +#endif /* TRC_CFG_FREERTOS_VERSION <= TRC_FREERTOS_VERSION_7_4 */ + +/* Called on each task-switch */ +#undef traceTASK_SWITCHED_IN +#define traceTASK_SWITCHED_IN() \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + { \ + if (prvIsNewTCB(pxCurrentTCB)) \ + { \ + prvTraceStoreEvent2(PSF_EVENT_TASK_ACTIVATE, (uint32_t)pxCurrentTCB, pxCurrentTCB->uxPriority); \ + } \ + } + +/* Called for each task that becomes ready */ +#if (TRC_CFG_INCLUDE_READY_EVENTS == 1) +#undef traceMOVED_TASK_TO_READY_STATE +#define traceMOVED_TASK_TO_READY_STATE( pxTCB ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, pxTCB) & CurrentFilterMask) \ + prvTraceStoreEvent1(PSF_EVENT_TASK_READY, (uint32_t)pxTCB); +#endif + +#undef traceTASK_CREATE +#if TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_9_0_0 +#define traceTASK_CREATE(pxNewTCB) \ + if (pxNewTCB != NULL) \ + { \ + prvTraceSaveSymbol(pxNewTCB, pxNewTCB->pcTaskName); \ + prvTraceSaveObjectData(pxNewTCB, pxNewTCB->uxPriority); \ + prvTraceStoreStringEvent(1, PSF_EVENT_OBJ_NAME, pxNewTCB->pcTaskName, pxNewTCB); \ + TRACE_SET_OBJECT_FILTER(TASK, pxNewTCB, CurrentFilterGroup); \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(TASK, pxNewTCB) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_TASK_CREATE, (uint32_t)pxNewTCB, pxNewTCB->uxPriority); \ + } +#else /* TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_9_0_0 */ +#define traceTASK_CREATE(pxNewTCB) \ + if (pxNewTCB != NULL) \ + { \ + prvTraceSaveSymbol(pxNewTCB, (const char*)pcName); \ + prvTraceSaveObjectData(pxNewTCB, uxPriority); \ + prvTraceStoreStringEvent(1, PSF_EVENT_OBJ_NAME, (const char*)pcName, pxNewTCB); \ + TRACE_SET_OBJECT_FILTER(TASK, pxNewTCB, CurrentFilterGroup); \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(TASK, pxNewTCB) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_TASK_CREATE, (uint32_t)pxNewTCB, uxPriority); \ + } +#endif /* TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_9_0_0 */ + +/* Called in vTaskCreate, if it fails (typically if the stack can not be allocated) */ +#undef traceTASK_CREATE_FAILED +#define traceTASK_CREATE_FAILED() \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + prvTraceStoreEvent0(PSF_EVENT_TASK_CREATE_FAILED); + +/* Called on vTaskDelete */ +#undef traceTASK_DELETE // We don't allow for filtering out "delete" events. They are important and not very frequent. Moreover, we can't exclude create events, so this should be symmetrical. +#define traceTASK_DELETE( pxTaskToDelete ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(TASK, pxTaskToDelete) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_TASK_DELETE, (uint32_t)pxTaskToDelete, (pxTaskToDelete != NULL) ? (pxTaskToDelete->uxPriority) : 0); \ + prvTraceDeleteSymbol(pxTaskToDelete); \ + prvTraceDeleteObjectData(pxTaskToDelete); + +#if (TRC_CFG_SCHEDULING_ONLY == 0) + +#if (defined(configUSE_TICKLESS_IDLE) && configUSE_TICKLESS_IDLE != 0) + +#undef traceLOW_POWER_IDLE_BEGIN +#define traceLOW_POWER_IDLE_BEGIN() \ + { \ + prvTraceStoreEvent1(PSF_EVENT_LOWPOWER_BEGIN, xExpectedIdleTime); \ + } + +#undef traceLOW_POWER_IDLE_END +#define traceLOW_POWER_IDLE_END() \ + { \ + prvTraceStoreEvent0(PSF_EVENT_LOWPOWER_END); \ + } + +#endif /* (defined(configUSE_TICKLESS_IDLE) && configUSE_TICKLESS_IDLE != 0) */ + +/* Called on vTaskSuspend */ +#undef traceTASK_SUSPEND +#define traceTASK_SUSPEND( pxTaskToSuspend ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(TASK, pxTaskToSuspend) & CurrentFilterMask) \ + prvTraceStoreEvent1(PSF_EVENT_TASK_SUSPEND, (uint32_t)pxTaskToSuspend); + +/* Called on vTaskDelay - note the use of FreeRTOS variable xTicksToDelay */ +#undef traceTASK_DELAY +#define traceTASK_DELAY() \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + prvTraceStoreEvent1(PSF_EVENT_TASK_DELAY, xTicksToDelay); + +/* Called on vTaskDelayUntil - note the use of FreeRTOS variable xTimeToWake */ +#undef traceTASK_DELAY_UNTIL +#if TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_9_0_0 +#define traceTASK_DELAY_UNTIL(xTimeToWake) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + prvTraceStoreEvent1(PSF_EVENT_TASK_DELAY_UNTIL, (uint32_t)xTimeToWake); +#else /* TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_9_0_0 */ +#define traceTASK_DELAY_UNTIL() \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + prvTraceStoreEvent1(PSF_EVENT_TASK_DELAY_UNTIL, (uint32_t)xTimeToWake); +#endif /* TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_9_0_0 */ + +#if (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_9_0_0) +#define traceQUEUE_CREATE_HELPER() \ + case queueQUEUE_TYPE_MUTEX: \ + prvTraceStoreEvent1(PSF_EVENT_MUTEX_CREATE, (uint32_t)pxNewQueue); \ + break; \ + case queueQUEUE_TYPE_RECURSIVE_MUTEX: \ + prvTraceStoreEvent1(PSF_EVENT_MUTEX_RECURSIVE_CREATE, (uint32_t)pxNewQueue); \ + break; +#else +#define traceQUEUE_CREATE_HELPER() +#endif /* (TRC_CFG_FREERTOS_VERSION < TRC_FREERTOS_VERSION_9_0_0) */ + +/* Called in xQueueCreate, and thereby for all other object based on queues, such as semaphores. */ +#undef traceQUEUE_CREATE +#define traceQUEUE_CREATE( pxNewQueue )\ + TRACE_SET_OBJECT_FILTER(QUEUE, pxNewQueue, CurrentFilterGroup); \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + { \ + if (TRACE_GET_OBJECT_FILTER(QUEUE, pxNewQueue) & CurrentFilterMask) \ + { \ + switch (pxNewQueue->ucQueueType) \ + { \ + case queueQUEUE_TYPE_BASE: \ + prvTraceStoreEvent2(PSF_EVENT_QUEUE_CREATE, (uint32_t)pxNewQueue, uxQueueLength); \ + break; \ + case queueQUEUE_TYPE_BINARY_SEMAPHORE: \ + prvTraceStoreEvent1(PSF_EVENT_SEMAPHORE_BINARY_CREATE, (uint32_t)pxNewQueue); \ + break; \ + traceQUEUE_CREATE_HELPER() \ + } \ + } \ + } + +#if (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_9_0_0) +#define traceQUEUE_CREATE_FAILED_HELPER() \ + case queueQUEUE_TYPE_MUTEX: \ + prvTraceStoreEvent1(PSF_EVENT_MUTEX_CREATE_FAILED, 0); \ + break; \ + case queueQUEUE_TYPE_RECURSIVE_MUTEX: \ + prvTraceStoreEvent1(PSF_EVENT_MUTEX_RECURSIVE_CREATE_FAILED, 0); \ + break; +#else +#define traceQUEUE_CREATE_FAILED_HELPER() +#endif /* (TRC_CFG_FREERTOS_VERSION < TRC_FREERTOS_VERSION_9_0_0) */ + +/* Called in xQueueCreate, if the queue creation fails */ +#undef traceQUEUE_CREATE_FAILED +#define traceQUEUE_CREATE_FAILED( queueType ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + { \ + switch (queueType) \ + { \ + case queueQUEUE_TYPE_BASE: \ + prvTraceStoreEvent2(PSF_EVENT_QUEUE_CREATE_FAILED, 0, uxQueueLength); \ + break; \ + case queueQUEUE_TYPE_BINARY_SEMAPHORE: \ + prvTraceStoreEvent1(PSF_EVENT_SEMAPHORE_BINARY_CREATE_FAILED, 0); \ + break; \ + traceQUEUE_CREATE_FAILED_HELPER() \ + } \ + } + +#undef traceQUEUE_DELETE // We don't allow for filtering out "delete" events. They are important and not very frequent. Moreover, we can't exclude create events, so this should be symmetrical. +#define traceQUEUE_DELETE( pxQueue ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + { \ + if (TRACE_GET_OBJECT_FILTER(QUEUE, pxQueue) & CurrentFilterMask) \ + { \ + switch (pxQueue->ucQueueType) \ + { \ + case queueQUEUE_TYPE_BASE: \ + prvTraceStoreEvent2(PSF_EVENT_QUEUE_DELETE, (uint32_t)pxQueue, (pxQueue != NULL) ? (pxQueue->uxMessagesWaiting) : 0); \ + break; \ + case queueQUEUE_TYPE_MUTEX: \ + case queueQUEUE_TYPE_RECURSIVE_MUTEX: \ + prvTraceStoreEvent2(PSF_EVENT_MUTEX_DELETE, (uint32_t)pxQueue, (pxQueue != NULL) ? (pxQueue->uxMessagesWaiting) : 0); \ + break; \ + case queueQUEUE_TYPE_COUNTING_SEMAPHORE: \ + case queueQUEUE_TYPE_BINARY_SEMAPHORE: \ + prvTraceStoreEvent2(PSF_EVENT_SEMAPHORE_DELETE, (uint32_t)pxQueue, (pxQueue != NULL) ? (pxQueue->uxMessagesWaiting) : 0); \ + break; \ + } \ + } \ + } \ + prvTraceDeleteSymbol(pxQueue); + +/* Called in xQueueCreateCountingSemaphore, if the queue creation fails */ +#undef traceCREATE_COUNTING_SEMAPHORE +#if (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_8_X) +#define traceCREATE_COUNTING_SEMAPHORE() \ + TRACE_SET_OBJECT_FILTER(QUEUE, xHandle, CurrentFilterGroup); \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(QUEUE, xHandle) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_SEMAPHORE_COUNTING_CREATE, (uint32_t)xHandle, uxMaxCount) +#elif (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_7_5_OR_7_6) +#define traceCREATE_COUNTING_SEMAPHORE() \ + TRACE_SET_OBJECT_FILTER(QUEUE, xHandle, CurrentFilterGroup); \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(QUEUE, xHandle) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_SEMAPHORE_COUNTING_CREATE, (uint32_t)xHandle, uxInitialCount); +#elif (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_7_4) +#define traceCREATE_COUNTING_SEMAPHORE() \ + TRACE_SET_OBJECT_FILTER(QUEUE, xHandle, CurrentFilterGroup); \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(QUEUE, xHandle) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_SEMAPHORE_COUNTING_CREATE, (uint32_t)xHandle, uxCountValue); +#else +#define traceCREATE_COUNTING_SEMAPHORE() \ + TRACE_SET_OBJECT_FILTER(QUEUE, pxHandle, CurrentFilterGroup); \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(QUEUE, pxHandle) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_SEMAPHORE_COUNTING_CREATE, (uint32_t)pxHandle, uxCountValue); +#endif /* TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_8_X */ + +#undef traceCREATE_COUNTING_SEMAPHORE_FAILED +#if (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_8_X) +#define traceCREATE_COUNTING_SEMAPHORE_FAILED() \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_SEMAPHORE_COUNTING_CREATE_FAILED, 0, uxMaxCount); +#elif (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_7_5_OR_7_6) +#define traceCREATE_COUNTING_SEMAPHORE_FAILED() \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_SEMAPHORE_COUNTING_CREATE_FAILED, 0, uxInitialCount); +#elif (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_7_4) +#define traceCREATE_COUNTING_SEMAPHORE_FAILED() \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_SEMAPHORE_COUNTING_CREATE_FAILED, 0, uxCountValue); +#else +#define traceCREATE_COUNTING_SEMAPHORE_FAILED() \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_SEMAPHORE_COUNTING_CREATE_FAILED, 0, uxCountValue); +#endif /* TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_8_X */ + + +/* This macro is not necessary as of FreeRTOS v9.0.0 */ +#if (TRC_CFG_FREERTOS_VERSION < TRC_FREERTOS_VERSION_9_0_0) +/* Called in xQueueCreateMutex, and thereby also from xSemaphoreCreateMutex and xSemaphoreCreateRecursiveMutex */ +#undef traceCREATE_MUTEX +#define traceCREATE_MUTEX( pxNewQueue ) \ + TRACE_SET_OBJECT_FILTER(QUEUE, pxNewQueue, CurrentFilterGroup); \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + { \ + if (TRACE_GET_OBJECT_FILTER(QUEUE, pxNewQueue) & CurrentFilterMask) \ + { \ + switch (pxNewQueue->ucQueueType) \ + { \ + case queueQUEUE_TYPE_MUTEX: \ + prvTraceStoreEvent1(PSF_EVENT_MUTEX_CREATE, (uint32_t)pxNewQueue); \ + break; \ + case queueQUEUE_TYPE_RECURSIVE_MUTEX: \ + prvTraceStoreEvent1(PSF_EVENT_MUTEX_RECURSIVE_CREATE, (uint32_t)pxNewQueue); \ + break; \ + } \ + }\ + } + +/* Called in xQueueCreateMutex when the operation fails (when memory allocation fails) */ +#undef traceCREATE_MUTEX_FAILED +#define traceCREATE_MUTEX_FAILED() \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + prvTraceStoreEvent1(PSF_EVENT_MUTEX_CREATE_FAILED, 0); +#endif /* (TRC_CFG_FREERTOS_VERSION < TRC_FREERTOS_VERSION_9_0_0) */ + +/* Called when a message is sent to a queue */ /* CS IS NEW ! */ +#undef traceQUEUE_SEND +#define traceQUEUE_SEND( pxQueue ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(QUEUE, pxQueue) & CurrentFilterMask) \ + switch (pxQueue->ucQueueType) \ + { \ + case queueQUEUE_TYPE_BASE: \ + prvTraceStoreEvent2(xCopyPosition == queueSEND_TO_BACK ? PSF_EVENT_QUEUE_SEND : PSF_EVENT_QUEUE_SEND_FRONT, (uint32_t)pxQueue, pxQueue->uxMessagesWaiting + 1); \ + break; \ + case queueQUEUE_TYPE_BINARY_SEMAPHORE: \ + case queueQUEUE_TYPE_COUNTING_SEMAPHORE: \ + prvTraceStoreEvent2(PSF_EVENT_SEMAPHORE_GIVE, (uint32_t)pxQueue, pxQueue->uxMessagesWaiting + 1); \ + break; \ + case queueQUEUE_TYPE_MUTEX: \ + case queueQUEUE_TYPE_RECURSIVE_MUTEX: \ + prvTraceStoreEvent1(PSF_EVENT_MUTEX_GIVE, (uint32_t)pxQueue); \ + break; \ + } + +/* Called when a message failed to be sent to a queue (timeout) */ +#undef traceQUEUE_SEND_FAILED +#define traceQUEUE_SEND_FAILED( pxQueue ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(QUEUE, pxQueue) & CurrentFilterMask) \ + switch (pxQueue->ucQueueType) \ + { \ + case queueQUEUE_TYPE_BASE: \ + prvTraceStoreEvent2(xCopyPosition == queueSEND_TO_BACK ? PSF_EVENT_QUEUE_SEND_FAILED : PSF_EVENT_QUEUE_SEND_FRONT_FAILED, (uint32_t)pxQueue, pxQueue->uxMessagesWaiting); \ + break; \ + case queueQUEUE_TYPE_BINARY_SEMAPHORE: \ + case queueQUEUE_TYPE_COUNTING_SEMAPHORE: \ + prvTraceStoreEvent2(PSF_EVENT_SEMAPHORE_GIVE_FAILED, (uint32_t)pxQueue, pxQueue->uxMessagesWaiting); \ + break; \ + case queueQUEUE_TYPE_MUTEX: \ + case queueQUEUE_TYPE_RECURSIVE_MUTEX: \ + prvTraceStoreEvent1(PSF_EVENT_MUTEX_GIVE_FAILED, (uint32_t)pxQueue); \ + break; \ + } + +/* Called when the task is blocked due to a send operation on a full queue */ +#undef traceBLOCKING_ON_QUEUE_SEND +#define traceBLOCKING_ON_QUEUE_SEND( pxQueue ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(QUEUE, pxQueue) & CurrentFilterMask) \ + switch (pxQueue->ucQueueType) \ + { \ + case queueQUEUE_TYPE_BASE: \ + prvTraceStoreEvent2(xCopyPosition == queueSEND_TO_BACK ? PSF_EVENT_QUEUE_SEND_BLOCK : PSF_EVENT_QUEUE_SEND_FRONT_BLOCK, (uint32_t)pxQueue, pxQueue->uxMessagesWaiting); \ + break; \ + case queueQUEUE_TYPE_BINARY_SEMAPHORE: \ + case queueQUEUE_TYPE_COUNTING_SEMAPHORE: \ + prvTraceStoreEvent2(PSF_EVENT_SEMAPHORE_GIVE_BLOCK, (uint32_t)pxQueue, pxQueue->uxMessagesWaiting); \ + break; \ + case queueQUEUE_TYPE_MUTEX: \ + case queueQUEUE_TYPE_RECURSIVE_MUTEX: \ + prvTraceStoreEvent1(PSF_EVENT_MUTEX_GIVE_BLOCK, (uint32_t)pxQueue); \ + break; \ + } + +/**************************************************************************/ +/* Makes sure xQueueGiveFromISR also has a xCopyPosition parameter */ +/**************************************************************************/ +/* Helpers needed to correctly expand names */ +#define TZ__CAT2(a,b) a ## b +#define TZ__CAT(a,b) TZ__CAT2(a, b) + +/* Expands name if this header is included... uxQueueType must be a macro that only exists in queue.c or whatever, and it must expand to nothing or to something that's valid in identifiers */ +#define xQueueGiveFromISR(a,b) TZ__CAT(xQueueGiveFromISR__, uxQueueType) (a,b) + +/* If in queue.c, the "uxQueueType" macro expands to "pcHead". queueSEND_TO_BACK is the value we need to send in */ +#define xQueueGiveFromISR__pcHead(__a, __b) MyWrapper(__a, __b, const BaseType_t xCopyPosition); \ +BaseType_t xQueueGiveFromISR(__a, __b) { return MyWrapper(xQueue, pxHigherPriorityTaskWoken, queueSEND_TO_BACK); } \ +BaseType_t MyWrapper(__a, __b, const BaseType_t xCopyPosition) + +/* If not in queue.c, "uxQueueType" isn't expanded */ +#define xQueueGiveFromISR__uxQueueType(__a, __b) xQueueGiveFromISR(__a,__b) + +/**************************************************************************/ +/* End of xQueueGiveFromISR fix */ +/**************************************************************************/ + +/* Called when a message is sent from interrupt context, e.g., using xQueueSendFromISR */ +#undef traceQUEUE_SEND_FROM_ISR +#define traceQUEUE_SEND_FROM_ISR( pxQueue ) \ + if (TRACE_GET_OBJECT_FILTER(QUEUE, pxQueue) & CurrentFilterMask) \ + switch (pxQueue->ucQueueType) \ + { \ + case queueQUEUE_TYPE_BASE: \ + prvTraceStoreEvent2(xCopyPosition == queueSEND_TO_BACK ? PSF_EVENT_QUEUE_SEND_FROMISR : PSF_EVENT_QUEUE_SEND_FRONT_FROMISR, (uint32_t)pxQueue, pxQueue->uxMessagesWaiting + 1); \ + break; \ + case queueQUEUE_TYPE_BINARY_SEMAPHORE: \ + case queueQUEUE_TYPE_COUNTING_SEMAPHORE: \ + prvTraceStoreEvent2(PSF_EVENT_SEMAPHORE_GIVE_FROMISR, (uint32_t)pxQueue, pxQueue->uxMessagesWaiting + 1); \ + break; \ + } + +/* Called when a message send from interrupt context fails (since the queue was full) */ +#undef traceQUEUE_SEND_FROM_ISR_FAILED +#define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ) \ + if (TRACE_GET_OBJECT_FILTER(QUEUE, pxQueue) & CurrentFilterMask) \ + switch (pxQueue->ucQueueType) \ + { \ + case queueQUEUE_TYPE_BASE: \ + prvTraceStoreEvent2(xCopyPosition == queueSEND_TO_BACK ? PSF_EVENT_QUEUE_SEND_FROMISR_FAILED : PSF_EVENT_QUEUE_SEND_FRONT_FROMISR_FAILED, (uint32_t)pxQueue, pxQueue->uxMessagesWaiting); \ + break; \ + case queueQUEUE_TYPE_BINARY_SEMAPHORE: \ + case queueQUEUE_TYPE_COUNTING_SEMAPHORE: \ + prvTraceStoreEvent2(PSF_EVENT_SEMAPHORE_GIVE_FROMISR_FAILED, (uint32_t)pxQueue, pxQueue->uxMessagesWaiting); \ + break; \ + } + +/* Called when a message is received from a queue */ +#undef traceQUEUE_RECEIVE +#define traceQUEUE_RECEIVE( pxQueue ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(QUEUE, pxQueue) & CurrentFilterMask) \ + switch (pxQueue->ucQueueType) \ + { \ + case queueQUEUE_TYPE_BASE: \ + if (isQueueReceiveHookActuallyPeek) \ + prvTraceStoreEvent3(PSF_EVENT_QUEUE_PEEK, (uint32_t)pxQueue, xTicksToWait, pxQueue->uxMessagesWaiting - 1); \ + else\ + prvTraceStoreEvent3(PSF_EVENT_QUEUE_RECEIVE, (uint32_t)pxQueue, xTicksToWait, pxQueue->uxMessagesWaiting - 1); \ + break; \ + case queueQUEUE_TYPE_BINARY_SEMAPHORE: \ + case queueQUEUE_TYPE_COUNTING_SEMAPHORE: \ + if (isQueueReceiveHookActuallyPeek) \ + prvTraceStoreEvent3(PSF_EVENT_SEMAPHORE_PEEK, (uint32_t)pxQueue, xTicksToWait, pxQueue->uxMessagesWaiting - 1); \ + else \ + prvTraceStoreEvent3(PSF_EVENT_SEMAPHORE_TAKE, (uint32_t)pxQueue, xTicksToWait, pxQueue->uxMessagesWaiting - 1); \ + break; \ + case queueQUEUE_TYPE_MUTEX: \ + case queueQUEUE_TYPE_RECURSIVE_MUTEX: \ + if (isQueueReceiveHookActuallyPeek) \ + prvTraceStoreEvent2(PSF_EVENT_MUTEX_PEEK, (uint32_t)pxQueue, xTicksToWait); \ + else \ + prvTraceStoreEvent2(PSF_EVENT_MUTEX_TAKE, (uint32_t)pxQueue, xTicksToWait); \ + break; \ + } + +/* Called when a receive operation on a queue fails (timeout) */ +#undef traceQUEUE_RECEIVE_FAILED +#define traceQUEUE_RECEIVE_FAILED( pxQueue ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(QUEUE, pxQueue) & CurrentFilterMask) \ + switch (pxQueue->ucQueueType) \ + { \ + case queueQUEUE_TYPE_BASE: \ + prvTraceStoreEvent3(isQueueReceiveHookActuallyPeek ? PSF_EVENT_QUEUE_PEEK_FAILED : PSF_EVENT_QUEUE_RECEIVE_FAILED, (uint32_t)pxQueue, xTicksToWait, pxQueue->uxMessagesWaiting); \ + break; \ + case queueQUEUE_TYPE_BINARY_SEMAPHORE: \ + case queueQUEUE_TYPE_COUNTING_SEMAPHORE: \ + prvTraceStoreEvent3(isQueueReceiveHookActuallyPeek ? PSF_EVENT_SEMAPHORE_PEEK_FAILED : PSF_EVENT_SEMAPHORE_TAKE_FAILED, (uint32_t)pxQueue, xTicksToWait, pxQueue->uxMessagesWaiting); \ + break; \ + case queueQUEUE_TYPE_MUTEX: \ + case queueQUEUE_TYPE_RECURSIVE_MUTEX: \ + prvTraceStoreEvent2(isQueueReceiveHookActuallyPeek ? PSF_EVENT_MUTEX_PEEK_FAILED : PSF_EVENT_MUTEX_TAKE_FAILED, (uint32_t)pxQueue, xTicksToWait); \ + break; \ + } + +/* Called when the task is blocked due to a receive operation on an empty queue */ +#undef traceBLOCKING_ON_QUEUE_RECEIVE +#define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(QUEUE, pxQueue) & CurrentFilterMask) \ + switch (pxQueue->ucQueueType) \ + { \ + case queueQUEUE_TYPE_BASE: \ + prvTraceStoreEvent3(isQueueReceiveHookActuallyPeek ? PSF_EVENT_QUEUE_PEEK_BLOCK : PSF_EVENT_QUEUE_RECEIVE_BLOCK, (uint32_t)pxQueue, xTicksToWait, pxQueue->uxMessagesWaiting); \ + break; \ + case queueQUEUE_TYPE_BINARY_SEMAPHORE: \ + case queueQUEUE_TYPE_COUNTING_SEMAPHORE: \ + prvTraceStoreEvent3(isQueueReceiveHookActuallyPeek ? PSF_EVENT_SEMAPHORE_PEEK_BLOCK : PSF_EVENT_SEMAPHORE_TAKE_BLOCK, (uint32_t)pxQueue, xTicksToWait, pxQueue->uxMessagesWaiting); \ + break; \ + case queueQUEUE_TYPE_MUTEX: \ + case queueQUEUE_TYPE_RECURSIVE_MUTEX: \ + prvTraceStoreEvent2(isQueueReceiveHookActuallyPeek ? PSF_EVENT_MUTEX_PEEK_BLOCK : PSF_EVENT_MUTEX_TAKE_BLOCK, (uint32_t)pxQueue, xTicksToWait); \ + break; \ + } + +#if (TRC_CFG_FREERTOS_VERSION > TRC_FREERTOS_VERSION_9_0_1) +/* Called when a peek operation on a queue fails (timeout) */ +#undef traceQUEUE_PEEK_FAILED +#define traceQUEUE_PEEK_FAILED( pxQueue ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(QUEUE, pxQueue) & CurrentFilterMask) \ + switch (pxQueue->ucQueueType) \ + { \ + case queueQUEUE_TYPE_BASE: \ + prvTraceStoreEvent3(PSF_EVENT_QUEUE_PEEK_FAILED, (uint32_t)pxQueue, xTicksToWait, pxQueue->uxMessagesWaiting); \ + break; \ + case queueQUEUE_TYPE_BINARY_SEMAPHORE: \ + case queueQUEUE_TYPE_COUNTING_SEMAPHORE: \ + prvTraceStoreEvent3(PSF_EVENT_SEMAPHORE_PEEK_FAILED, (uint32_t)pxQueue, xTicksToWait, pxQueue->uxMessagesWaiting); \ + break; \ + case queueQUEUE_TYPE_MUTEX: \ + case queueQUEUE_TYPE_RECURSIVE_MUTEX: \ + prvTraceStoreEvent2(PSF_EVENT_MUTEX_PEEK_FAILED, (uint32_t)pxQueue, xTicksToWait); \ + break; \ + } + +/* Called when the task is blocked due to a peek operation on an empty queue */ +#undef traceBLOCKING_ON_QUEUE_PEEK +#define traceBLOCKING_ON_QUEUE_PEEK( pxQueue ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(QUEUE, pxQueue) & CurrentFilterMask) \ + switch (pxQueue->ucQueueType) \ + { \ + case queueQUEUE_TYPE_BASE: \ + prvTraceStoreEvent3(PSF_EVENT_QUEUE_PEEK_BLOCK, (uint32_t)pxQueue, xTicksToWait, pxQueue->uxMessagesWaiting); \ + break; \ + case queueQUEUE_TYPE_BINARY_SEMAPHORE: \ + case queueQUEUE_TYPE_COUNTING_SEMAPHORE: \ + prvTraceStoreEvent3(PSF_EVENT_SEMAPHORE_PEEK_BLOCK, (uint32_t)pxQueue, xTicksToWait, pxQueue->uxMessagesWaiting); \ + break; \ + case queueQUEUE_TYPE_MUTEX: \ + case queueQUEUE_TYPE_RECURSIVE_MUTEX: \ + prvTraceStoreEvent2(PSF_EVENT_MUTEX_PEEK_BLOCK, (uint32_t)pxQueue, xTicksToWait); \ + break; \ + } + +#endif /* (TRC_CFG_FREERTOS_VERSION > TRC_FREERTOS_VERSION_9_0_1) */ + +/* Called when a message is received in interrupt context, e.g., using xQueueReceiveFromISR */ +#undef traceQUEUE_RECEIVE_FROM_ISR +#define traceQUEUE_RECEIVE_FROM_ISR( pxQueue ) \ + if (TRACE_GET_OBJECT_FILTER(QUEUE, pxQueue) & CurrentFilterMask) \ + switch (pxQueue->ucQueueType) \ + { \ + case queueQUEUE_TYPE_BASE: \ + prvTraceStoreEvent2(PSF_EVENT_QUEUE_RECEIVE_FROMISR, (uint32_t)pxQueue, pxQueue->uxMessagesWaiting - 1); \ + break; \ + case queueQUEUE_TYPE_BINARY_SEMAPHORE: \ + case queueQUEUE_TYPE_COUNTING_SEMAPHORE: \ + prvTraceStoreEvent2(PSF_EVENT_SEMAPHORE_TAKE_FROMISR, (uint32_t)pxQueue, pxQueue->uxMessagesWaiting - 1); \ + break; \ + } + +/* Called when a message receive from interrupt context fails (since the queue was empty) */ +#undef traceQUEUE_RECEIVE_FROM_ISR_FAILED +#define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ) \ + if (TRACE_GET_OBJECT_FILTER(QUEUE, pxQueue) & CurrentFilterMask) \ + switch (pxQueue->ucQueueType) \ + { \ + case queueQUEUE_TYPE_BASE: \ + prvTraceStoreEvent2(PSF_EVENT_QUEUE_RECEIVE_FROMISR_FAILED, (uint32_t)pxQueue, pxQueue->uxMessagesWaiting); \ + break; \ + case queueQUEUE_TYPE_BINARY_SEMAPHORE: \ + case queueQUEUE_TYPE_COUNTING_SEMAPHORE: \ + prvTraceStoreEvent2(PSF_EVENT_SEMAPHORE_TAKE_FROMISR_FAILED, (uint32_t)pxQueue, pxQueue->uxMessagesWaiting); \ + break; \ + } + +/* Called on xQueuePeek */ +#undef traceQUEUE_PEEK +#define traceQUEUE_PEEK( pxQueue ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(QUEUE, pxQueue) & CurrentFilterMask) \ + switch (pxQueue->ucQueueType) \ + { \ + case queueQUEUE_TYPE_BASE: \ + prvTraceStoreEvent3(PSF_EVENT_QUEUE_PEEK, (uint32_t)pxQueue, xTicksToWait, pxQueue->uxMessagesWaiting); \ + break; \ + case queueQUEUE_TYPE_BINARY_SEMAPHORE: \ + case queueQUEUE_TYPE_COUNTING_SEMAPHORE: \ + prvTraceStoreEvent3(PSF_EVENT_SEMAPHORE_PEEK, (uint32_t)pxQueue, xTicksToWait, pxQueue->uxMessagesWaiting); \ + break; \ + case queueQUEUE_TYPE_MUTEX: \ + case queueQUEUE_TYPE_RECURSIVE_MUTEX: \ + prvTraceStoreEvent1(PSF_EVENT_MUTEX_PEEK, (uint32_t)pxQueue); \ + break; \ + } + +/* Called in vTaskPrioritySet */ +#undef traceTASK_PRIORITY_SET +#define traceTASK_PRIORITY_SET( pxTask, uxNewPriority ) \ + prvTraceSaveObjectData(pxTask, uxNewPriority); \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(TASK, pxTask) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_TASK_PRIORITY, (uint32_t)pxTask, uxNewPriority); + +/* Called in vTaskPriorityInherit, which is called by Mutex operations */ +#undef traceTASK_PRIORITY_INHERIT +#define traceTASK_PRIORITY_INHERIT( pxTask, uxNewPriority ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(TASK, pxTask) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_TASK_PRIO_INHERIT, (uint32_t)pxTask, uxNewPriority); + +/* Called in vTaskPriorityDisinherit, which is called by Mutex operations */ +#undef traceTASK_PRIORITY_DISINHERIT +#define traceTASK_PRIORITY_DISINHERIT( pxTask, uxNewPriority ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(TASK, pxTask) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_TASK_PRIO_DISINHERIT, (uint32_t)pxTask, uxNewPriority); + +/* Called in vTaskResume */ +#undef traceTASK_RESUME +#define traceTASK_RESUME( pxTaskToResume ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(TASK, pxTaskToResume) & CurrentFilterMask) \ + prvTraceStoreEvent1(PSF_EVENT_TASK_RESUME, (uint32_t)pxTaskToResume); + +/* Called in vTaskResumeFromISR */ +#undef traceTASK_RESUME_FROM_ISR +#define traceTASK_RESUME_FROM_ISR( pxTaskToResume ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, pxTaskToResume) & CurrentFilterMask) \ + prvTraceStoreEvent1(PSF_EVENT_TASK_RESUME_FROMISR, (uint32_t)pxTaskToResume); + +#if (TRC_CFG_INCLUDE_MEMMANG_EVENTS == 1) + +#undef traceMALLOC +#define traceMALLOC( pvAddress, uiSize ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_MALLOC, (uint32_t)pvAddress, uiSize); + +#undef traceFREE +#define traceFREE( pvAddress, uiSize ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_FREE, (uint32_t)pvAddress, (uint32_t)(0 - uiSize)); /* "0 -" instead of just "-" to get rid of a warning... */ + +#endif /* (TRC_CFG_INCLUDE_MEMMANG_EVENTS == 1) */ + +#if (TRC_CFG_INCLUDE_TIMER_EVENTS == 1) + +/* Called in timer.c - xTimerCreate */ +#undef traceTIMER_CREATE +#define traceTIMER_CREATE(tmr) \ + TRACE_SET_OBJECT_FILTER(TIMER, tmr, CurrentFilterGroup); \ + prvTraceSaveSymbol(tmr, tmr->pcTimerName); \ + prvTraceStoreStringEvent(1, PSF_EVENT_OBJ_NAME, tmr->pcTimerName, tmr); \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(TIMER, tmr) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_TIMER_CREATE, (uint32_t)tmr, tmr->xTimerPeriodInTicks); + +#undef traceTIMER_CREATE_FAILED +#define traceTIMER_CREATE_FAILED() \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + prvTraceStoreEvent0(PSF_EVENT_TIMER_CREATE_FAILED); + +#if (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_8_X) +#define traceTIMER_COMMAND_SEND_8_0_CASES(tmr) \ + case tmrCOMMAND_RESET: \ + prvTraceStoreEvent2((xReturn == pdPASS) ? PSF_EVENT_TIMER_RESET : PSF_EVENT_TIMER_RESET_FAILED, (uint32_t)tmr, xOptionalValue); \ + break; \ + case tmrCOMMAND_START_FROM_ISR: \ + prvTraceStoreEvent2((xReturn == pdPASS) ? PSF_EVENT_TIMER_START_FROMISR : PSF_EVENT_TIMER_START_FROMISR_FAILED, (uint32_t)tmr, xOptionalValue); \ + break; \ + case tmrCOMMAND_RESET_FROM_ISR: \ + prvTraceStoreEvent2((xReturn == pdPASS) ? PSF_EVENT_TIMER_RESET_FROMISR : PSF_EVENT_TIMER_RESET_FROMISR_FAILED, (uint32_t)tmr, xOptionalValue); \ + break; \ + case tmrCOMMAND_STOP_FROM_ISR: \ + prvTraceStoreEvent2((xReturn == pdPASS) ? PSF_EVENT_TIMER_STOP_FROMISR : PSF_EVENT_TIMER_STOP_FROMISR_FAILED, (uint32_t)tmr, xOptionalValue); \ + break; \ + case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR: \ + prvTraceStoreEvent2((xReturn == pdPASS) ? PSF_EVENT_TIMER_CHANGEPERIOD_FROMISR : PSF_EVENT_TIMER_CHANGEPERIOD_FROMISR_FAILED, (uint32_t)tmr, xOptionalValue); \ + break; +#else /* TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_8_X */ +#define traceTIMER_COMMAND_SEND_8_0_CASES(tmr) +#endif /* TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_8_X */ + +/* Note that xCommandID can never be tmrCOMMAND_EXECUTE_CALLBACK (-1) since the trace macro is not called in that case */ +#undef traceTIMER_COMMAND_SEND +#define traceTIMER_COMMAND_SEND(tmr, xCommandID, xOptionalValue, xReturn) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(TIMER, tmr) & CurrentFilterMask) \ + switch(xCommandID) \ + { \ + case tmrCOMMAND_START: \ + prvTraceStoreEvent1((xReturn == pdPASS) ? PSF_EVENT_TIMER_START : PSF_EVENT_TIMER_START_FAILED, (uint32_t)tmr); \ + break; \ + case tmrCOMMAND_STOP: \ + prvTraceStoreEvent1((xReturn == pdPASS) ? PSF_EVENT_TIMER_STOP : PSF_EVENT_TIMER_STOP_FAILED, (uint32_t)tmr); \ + break; \ + case tmrCOMMAND_CHANGE_PERIOD: \ + prvTraceStoreEvent2((xReturn == pdPASS) ? PSF_EVENT_TIMER_CHANGEPERIOD : PSF_EVENT_TIMER_CHANGEPERIOD_FAILED, (uint32_t)tmr, xOptionalValue); \ + break; \ + case tmrCOMMAND_DELETE: \ + prvTraceStoreEvent1((xReturn == pdPASS) ? PSF_EVENT_TIMER_DELETE : PSF_EVENT_TIMER_DELETE_FAILED, (uint32_t)tmr); \ + break; \ + traceTIMER_COMMAND_SEND_8_0_CASES(tmr) \ + } + +#undef traceTIMER_EXPIRED +#define traceTIMER_EXPIRED(tmr) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(TIMER, tmr) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_TIMER_EXPIRED, (uint32_t)tmr->pxCallbackFunction, (uint32_t)tmr->pvTimerID); + +#endif /* #if (TRC_CFG_INCLUDE_TIMER_EVENTS == 1) */ + + +#if (TRC_CFG_INCLUDE_PEND_FUNC_CALL_EVENTS == 1) + +#undef tracePEND_FUNC_CALL +#define tracePEND_FUNC_CALL(func, arg1, arg2, ret) \ + prvTraceStoreEvent1((ret == pdPASS) ? PSF_EVENT_TIMER_PENDFUNCCALL : PSF_EVENT_TIMER_PENDFUNCCALL_FAILED, (uint32_t)func); + +#undef tracePEND_FUNC_CALL_FROM_ISR +#define tracePEND_FUNC_CALL_FROM_ISR(func, arg1, arg2, ret) \ + prvTraceStoreEvent1((ret == pdPASS) ? PSF_EVENT_TIMER_PENDFUNCCALL_FROMISR : PSF_EVENT_TIMER_PENDFUNCCALL_FROMISR_FAILED, (uint32_t)func); + +#endif /* (TRC_CFG_INCLUDE_PEND_FUNC_CALL_EVENTS == 1) */ + +#if (TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS == 1) + +#undef traceEVENT_GROUP_CREATE +#define traceEVENT_GROUP_CREATE(eg) \ + TRACE_SET_OBJECT_FILTER(EVENTGROUP, eg, CurrentFilterGroup); \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(EVENTGROUP, eg) & CurrentFilterMask) \ + prvTraceStoreEvent1(PSF_EVENT_EVENTGROUP_CREATE, (uint32_t)eg); + +#undef traceEVENT_GROUP_DELETE +#define traceEVENT_GROUP_DELETE(eg) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(EVENTGROUP, eg) & CurrentFilterMask) \ + prvTraceStoreEvent1(PSF_EVENT_EVENTGROUP_DELETE, (uint32_t)eg); \ + prvTraceDeleteSymbol(eg); + +#undef traceEVENT_GROUP_CREATE_FAILED +#define traceEVENT_GROUP_CREATE_FAILED() \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + prvTraceStoreEvent0(PSF_EVENT_EVENTGROUP_CREATE_FAILED); + +#undef traceEVENT_GROUP_SYNC_BLOCK +#define traceEVENT_GROUP_SYNC_BLOCK(eg, bitsToSet, bitsToWaitFor) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(EVENTGROUP, eg) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_EVENTGROUP_SYNC_BLOCK, (uint32_t)eg, bitsToWaitFor); + +#undef traceEVENT_GROUP_SYNC_END +#define traceEVENT_GROUP_SYNC_END(eg, bitsToSet, bitsToWaitFor, wasTimeout) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(EVENTGROUP, eg) & CurrentFilterMask) \ + prvTraceStoreEvent2((wasTimeout != pdTRUE) ? PSF_EVENT_EVENTGROUP_SYNC : PSF_EVENT_EVENTGROUP_SYNC_FAILED, (uint32_t)eg, bitsToWaitFor); + +#undef traceEVENT_GROUP_WAIT_BITS_BLOCK +#define traceEVENT_GROUP_WAIT_BITS_BLOCK(eg, bitsToWaitFor) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(EVENTGROUP, eg) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_EVENTGROUP_WAITBITS_BLOCK, (uint32_t)eg, bitsToWaitFor); + +#undef traceEVENT_GROUP_WAIT_BITS_END +#define traceEVENT_GROUP_WAIT_BITS_END(eg, bitsToWaitFor, wasTimeout) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(EVENTGROUP, eg) & CurrentFilterMask) \ + prvTraceStoreEvent2((wasTimeout != pdTRUE) ? PSF_EVENT_EVENTGROUP_WAITBITS : PSF_EVENT_EVENTGROUP_WAITBITS_FAILED, (uint32_t)eg, bitsToWaitFor); + +#undef traceEVENT_GROUP_CLEAR_BITS +#define traceEVENT_GROUP_CLEAR_BITS(eg, bitsToClear) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(EVENTGROUP, eg) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_EVENTGROUP_CLEARBITS, (uint32_t)eg, bitsToClear); + +#undef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR +#define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR(eg, bitsToClear) \ + if (TRACE_GET_OBJECT_FILTER(EVENTGROUP, eg) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_EVENTGROUP_CLEARBITS_FROMISR, (uint32_t)eg, bitsToClear); + +#undef traceEVENT_GROUP_SET_BITS +#define traceEVENT_GROUP_SET_BITS(eg, bitsToSet) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(EVENTGROUP, eg) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_EVENTGROUP_SETBITS, (uint32_t)eg, bitsToSet); + +#undef traceEVENT_GROUP_SET_BITS_FROM_ISR +#define traceEVENT_GROUP_SET_BITS_FROM_ISR(eg, bitsToSet) \ + if (TRACE_GET_OBJECT_FILTER(EVENTGROUP, eg) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_EVENTGROUP_SETBITS_FROMISR, (uint32_t)eg, bitsToSet); + +#endif /* (TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS == 1) */ + +#undef traceTASK_NOTIFY_TAKE +#if (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_9_0_0) +#define traceTASK_NOTIFY_TAKE() \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask){ \ + if (pxCurrentTCB->ucNotifyState == taskNOTIFICATION_RECEIVED) \ + prvTraceStoreEvent2(PSF_EVENT_TASK_NOTIFY_TAKE, (uint32_t)pxCurrentTCB, xTicksToWait); \ + else \ + prvTraceStoreEvent2(PSF_EVENT_TASK_NOTIFY_TAKE_FAILED, (uint32_t)pxCurrentTCB, xTicksToWait);} +#else /* TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_9_0_0 */ +#define traceTASK_NOTIFY_TAKE() \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask){ \ + if (pxCurrentTCB->eNotifyState == eNotified) \ + prvTraceStoreEvent2(PSF_EVENT_TASK_NOTIFY_TAKE, (uint32_t)pxCurrentTCB, xTicksToWait); \ + else \ + prvTraceStoreEvent2(PSF_EVENT_TASK_NOTIFY_TAKE_FAILED, (uint32_t)pxCurrentTCB, xTicksToWait);} +#endif /* TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_9_0_0 */ + +#undef traceTASK_NOTIFY_TAKE_BLOCK +#define traceTASK_NOTIFY_TAKE_BLOCK() \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_TASK_NOTIFY_TAKE_BLOCK, (uint32_t)pxCurrentTCB, xTicksToWait); + +#undef traceTASK_NOTIFY_WAIT +#if (TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_9_0_0) +#define traceTASK_NOTIFY_WAIT() \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask){ \ + if (pxCurrentTCB->ucNotifyState == taskNOTIFICATION_RECEIVED) \ + prvTraceStoreEvent2(PSF_EVENT_TASK_NOTIFY_WAIT, (uint32_t)pxCurrentTCB, xTicksToWait); \ + else \ + prvTraceStoreEvent2(PSF_EVENT_TASK_NOTIFY_WAIT_FAILED, (uint32_t)pxCurrentTCB, xTicksToWait);} +#else /* TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_9_0_0 */ +#define traceTASK_NOTIFY_WAIT() \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask){ \ + if (pxCurrentTCB->eNotifyState == eNotified) \ + prvTraceStoreEvent2(PSF_EVENT_TASK_NOTIFY_WAIT, (uint32_t)pxCurrentTCB, xTicksToWait); \ + else \ + prvTraceStoreEvent2(PSF_EVENT_TASK_NOTIFY_WAIT_FAILED, (uint32_t)pxCurrentTCB, xTicksToWait);} +#endif /* TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_9_0_0 */ + +#undef traceTASK_NOTIFY_WAIT_BLOCK +#define traceTASK_NOTIFY_WAIT_BLOCK() \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + prvTraceStoreEvent2(PSF_EVENT_TASK_NOTIFY_WAIT_BLOCK, (uint32_t)pxCurrentTCB, xTicksToWait); + +#undef traceTASK_NOTIFY +#define traceTASK_NOTIFY() \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(TASK, xTaskToNotify) & CurrentFilterMask) \ + prvTraceStoreEvent1(PSF_EVENT_TASK_NOTIFY, (uint32_t)xTaskToNotify); + +#undef traceTASK_NOTIFY_FROM_ISR +#define traceTASK_NOTIFY_FROM_ISR() \ + if (TRACE_GET_OBJECT_FILTER(TASK, xTaskToNotify) & CurrentFilterMask) \ + prvTraceStoreEvent1(PSF_EVENT_TASK_NOTIFY_FROM_ISR, (uint32_t)xTaskToNotify); + +#undef traceTASK_NOTIFY_GIVE_FROM_ISR +#define traceTASK_NOTIFY_GIVE_FROM_ISR() \ + if (TRACE_GET_OBJECT_FILTER(TASK, xTaskToNotify) & CurrentFilterMask) \ + prvTraceStoreEvent1(PSF_EVENT_TASK_NOTIFY_GIVE_FROM_ISR, (uint32_t)xTaskToNotify); + +#undef traceQUEUE_REGISTRY_ADD +#define traceQUEUE_REGISTRY_ADD(object, name) \ + prvTraceSaveSymbol(object, (const char*)name); \ + prvTraceStoreStringEvent(1, PSF_EVENT_OBJ_NAME, name, object); + +#if (TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS == 1) + +#undef traceSTREAM_BUFFER_CREATE +#define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer ) \ + TRACE_SET_OBJECT_FILTER(STREAMBUFFER, pxStreamBuffer, CurrentFilterGroup); \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(STREAMBUFFER, pxStreamBuffer) & CurrentFilterMask) \ + prvTraceStoreEvent2(xIsMessageBuffer == 1 ? PSF_EVENT_MESSAGEBUFFER_CREATE : PSF_EVENT_STREAMBUFFER_CREATE, (uint32_t)pxStreamBuffer, xBufferSizeBytes); + +#undef traceSTREAM_BUFFER_CREATE_FAILED +#define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + prvTraceStoreEvent2(xIsMessageBuffer == 1 ? PSF_EVENT_MESSAGEBUFFER_CREATE_FAILED : PSF_EVENT_STREAMBUFFER_CREATE_FAILED, 0 , xBufferSizeBytes); + +#undef traceSTREAM_BUFFER_CREATE_STATIC_FAILED +#define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer ) \ + traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ) + +#undef traceSTREAM_BUFFER_DELETE +#define traceSTREAM_BUFFER_DELETE( xStreamBuffer ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(STREAMBUFFER, pxStreamBuffer) & CurrentFilterMask) \ + prvTraceStoreEvent2(prvGetStreamBufferType(xStreamBuffer) > 0 ? PSF_EVENT_MESSAGEBUFFER_DELETE : PSF_EVENT_STREAMBUFFER_DELETE, (uint32_t)xStreamBuffer, prvBytesInBuffer(xStreamBuffer)); \ + prvTraceDeleteSymbol(xStreamBuffer); + +#undef traceSTREAM_BUFFER_RESET +#define traceSTREAM_BUFFER_RESET( xStreamBuffer ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(STREAMBUFFER, xStreamBuffer) & CurrentFilterMask) \ + prvTraceStoreEvent2(prvGetStreamBufferType(xStreamBuffer) > 0 ? PSF_EVENT_MESSAGEBUFFER_RESET : PSF_EVENT_STREAMBUFFER_RESET, (uint32_t)xStreamBuffer, 0); + +#undef traceSTREAM_BUFFER_SEND +#define traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(STREAMBUFFER, xStreamBuffer) & CurrentFilterMask) \ + prvTraceStoreEvent2(prvGetStreamBufferType(xStreamBuffer) > 0 ? PSF_EVENT_MESSAGEBUFFER_SEND : PSF_EVENT_STREAMBUFFER_SEND, (uint32_t)xStreamBuffer, prvBytesInBuffer(xStreamBuffer)); + +#undef traceBLOCKING_ON_STREAM_BUFFER_SEND +#define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(STREAMBUFFER, xStreamBuffer) & CurrentFilterMask) \ + prvTraceStoreEvent1(prvGetStreamBufferType(xStreamBuffer) > 0 ? PSF_EVENT_MESSAGEBUFFER_SEND_BLOCK : PSF_EVENT_STREAMBUFFER_SEND_BLOCK, (uint32_t)xStreamBuffer); + +#undef traceSTREAM_BUFFER_SEND_FAILED +#define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(STREAMBUFFER, xStreamBuffer) & CurrentFilterMask) \ + prvTraceStoreEvent1(prvGetStreamBufferType(xStreamBuffer) > 0 ? PSF_EVENT_MESSAGEBUFFER_SEND_FAILED : PSF_EVENT_STREAMBUFFER_SEND_FAILED, (uint32_t)xStreamBuffer); + +#undef traceSTREAM_BUFFER_RECEIVE +#define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(STREAMBUFFER, xStreamBuffer) & CurrentFilterMask) \ + prvTraceStoreEvent2(prvGetStreamBufferType(xStreamBuffer) > 0 ? PSF_EVENT_MESSAGEBUFFER_RECEIVE: PSF_EVENT_STREAMBUFFER_RECEIVE, (uint32_t)xStreamBuffer, prvBytesInBuffer(xStreamBuffer)); + +#undef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE +#define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(STREAMBUFFER, xStreamBuffer) & CurrentFilterMask) \ + prvTraceStoreEvent1(prvGetStreamBufferType(xStreamBuffer) > 0 ? PSF_EVENT_MESSAGEBUFFER_RECEIVE_BLOCK: PSF_EVENT_STREAMBUFFER_RECEIVE_BLOCK, (uint32_t)xStreamBuffer); + +#undef traceSTREAM_BUFFER_RECEIVE_FAILED +#define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(STREAMBUFFER, xStreamBuffer) & CurrentFilterMask) \ + prvTraceStoreEvent1(prvGetStreamBufferType(xStreamBuffer) > 0 ? PSF_EVENT_MESSAGEBUFFER_RECEIVE_FAILED: PSF_EVENT_STREAMBUFFER_RECEIVE_FAILED, (uint32_t)xStreamBuffer); + +#undef traceSTREAM_BUFFER_SEND_FROM_ISR +#define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn ) \ + if (TRACE_GET_OBJECT_FILTER(STREAMBUFFER, xStreamBuffer) & CurrentFilterMask) \ + { \ + if ( xReturn > ( size_t ) 0 ) \ + { \ + prvTraceStoreEvent2(prvGetStreamBufferType(xStreamBuffer) > 0 ? PSF_EVENT_MESSAGEBUFFER_SEND_FROM_ISR : PSF_EVENT_STREAMBUFFER_SEND_FROM_ISR, (uint32_t)xStreamBuffer, prvBytesInBuffer(xStreamBuffer)); \ + } \ + else \ + { \ + prvTraceStoreEvent1(prvGetStreamBufferType(xStreamBuffer) > 0 ? PSF_EVENT_MESSAGEBUFFER_SEND_FROM_ISR_FAILED : PSF_EVENT_STREAMBUFFER_SEND_FROM_ISR_FAILED, (uint32_t)xStreamBuffer); \ + } \ + } + +#undef traceSTREAM_BUFFER_RECEIVE_FROM_ISR +#define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ) \ +if (TRACE_GET_OBJECT_FILTER(STREAMBUFFER, xStreamBuffer) & CurrentFilterMask) \ + { \ + if ( xReceivedLength > ( size_t ) 0 ) \ + { \ + prvTraceStoreEvent2(prvGetStreamBufferType(xStreamBuffer) > 0 ? PSF_EVENT_MESSAGEBUFFER_RECEIVE_FROM_ISR : PSF_EVENT_STREAMBUFFER_RECEIVE_FROM_ISR, (uint32_t)xStreamBuffer, prvBytesInBuffer(xStreamBuffer)); \ + } \ + else \ + { \ + prvTraceStoreEvent1(prvGetStreamBufferType(xStreamBuffer) > 0 ? PSF_EVENT_MESSAGEBUFFER_RECEIVE_FROM_ISR_FAILED : PSF_EVENT_STREAMBUFFER_RECEIVE_FROM_ISR_FAILED, (uint32_t)xStreamBuffer); \ + } \ + } + +#endif /* (TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS == 1) */ + +#endif /* (TRC_CFG_SCHEDULING_ONLY == 0) */ + +#endif /* (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING) */ + +#else /* (TRC_USE_TRACEALYZER_RECORDER == 1) */ + +/* When recorder is disabled */ +#define vTraceSetQueueName(object, name) +#define vTraceSetSemaphoreName(object, name) +#define vTraceSetMutexName(object, name) +#define vTraceSetEventGroupName(object, name) +#define vTraceSetStreamBufferName(object, name) +#define vTraceSetMessageBufferName(object, name) + +#endif /* (TRC_USE_TRACEALYZER_RECORDER == 1) */ + +#ifdef __cplusplus +} +#endif + +#endif /* TRC_KERNEL_PORT_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/Include/trcPortDefines.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/Include/trcPortDefines.h new file mode 100644 index 0000000..258bf22 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/Include/trcPortDefines.h @@ -0,0 +1,137 @@ +/******************************************************************************* + * Trace Recorder Library for Tracealyzer v4.1.5 + * Percepio AB, www.percepio.com + * + * trcPortDefines.h + * + * Some common defines for the trace recorder. + * + * Terms of Use + * This file is part of the trace recorder library (RECORDER), which is the + * intellectual property of Percepio AB (PERCEPIO) and provided under a + * license as follows. + * The RECORDER may be used free of charge for the purpose of recording data + * intended for analysis in PERCEPIO products. It may not be used or modified + * for other purposes without explicit permission from PERCEPIO. + * You may distribute the RECORDER in its original source code form, assuming + * this text (terms of use, disclaimer, copyright notice) is unchanged. You are + * allowed to distribute the RECORDER with minor modifications intended for + * configuration or porting of the RECORDER, e.g., to allow using it on a + * specific processor, processor family or with a specific communication + * interface. Any such modifications should be documented directly below + * this comment block. + * + * Disclaimer + * The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty + * as to its use or performance. PERCEPIO does not and cannot warrant the + * performance or results you may obtain by using the RECORDER or documentation. + * PERCEPIO make no warranties, express or implied, as to noninfringement of + * third party rights, merchantability, or fitness for any particular purpose. + * In no event will PERCEPIO, its technology partners, or distributors be liable + * to you for any consequential, incidental or special damages, including any + * lost profits or lost savings, even if a representative of PERCEPIO has been + * advised of the possibility of such damages, or for any claim by any third + * party. Some jurisdictions do not allow the exclusion or limitation of + * incidental, consequential or special damages, or the exclusion of implied + * warranties or limitations on how long an implied warranty may last, so the + * above limitations may not apply to you. + * + * Tabs are used for indent in this file (1 tab = 4 spaces) + * + * Copyright Percepio AB, 2018. + * www.percepio.com + ******************************************************************************/ + +#ifndef TRC_PORTDEFINES_H +#define TRC_PORTDEFINES_H + +#define TRC_FREE_RUNNING_32BIT_INCR 1 +#define TRC_FREE_RUNNING_32BIT_DECR 2 +#define TRC_OS_TIMER_INCR 3 +#define TRC_OS_TIMER_DECR 4 +#define TRC_CUSTOM_TIMER_INCR 5 +#define TRC_CUSTOM_TIMER_DECR 6 + +/* Start options for vTraceEnable. */ +#define TRC_INIT 0 +#define TRC_START 1 +#define TRC_START_AWAIT_HOST 2 + +/* Command codes for TzCtrl task */ +#define CMD_SET_ACTIVE 1 /* Start (param1 = 1) or Stop (param1 = 0) */ + +/* The final command code, used to validate commands. */ +#define CMD_LAST_COMMAND 1 + +#define TRC_RECORDER_MODE_SNAPSHOT 0 +#define TRC_RECORDER_MODE_STREAMING 1 + +#define TRC_RECORDER_BUFFER_ALLOCATION_STATIC (0x00) +#define TRC_RECORDER_BUFFER_ALLOCATION_DYNAMIC (0x01) +#define TRC_RECORDER_BUFFER_ALLOCATION_CUSTOM (0x02) + +/* Filter Groups */ +#define FilterGroup0 (uint16_t)0x0001 +#define FilterGroup1 (uint16_t)0x0002 +#define FilterGroup2 (uint16_t)0x0004 +#define FilterGroup3 (uint16_t)0x0008 +#define FilterGroup4 (uint16_t)0x0010 +#define FilterGroup5 (uint16_t)0x0020 +#define FilterGroup6 (uint16_t)0x0040 +#define FilterGroup7 (uint16_t)0x0080 +#define FilterGroup8 (uint16_t)0x0100 +#define FilterGroup9 (uint16_t)0x0200 +#define FilterGroup10 (uint16_t)0x0400 +#define FilterGroup11 (uint16_t)0x0800 +#define FilterGroup12 (uint16_t)0x1000 +#define FilterGroup13 (uint16_t)0x2000 +#define FilterGroup14 (uint16_t)0x4000 +#define FilterGroup15 (uint16_t)0x8000 + +/****************************************************************************** + * Supported ports + * + * TRC_HARDWARE_PORT_HWIndependent + * A hardware independent fallback option for event timestamping. Provides low + * resolution timestamps based on the OS tick. + * This may be used on the Win32 port, but may also be used on embedded hardware + * platforms. All time durations will be truncated to the OS tick frequency, + * typically 1 KHz. This means that a task or ISR that executes in less than + * 1 ms get an execution time of zero. + * + * TRC_HARDWARE_PORT_APPLICATION_DEFINED + * Allows for defining the port macros in other source code files. + * + * TRC_HARDWARE_PORT_Win32 + * "Accurate" timestamping based on the Windows performance counter for Win32 + * builds. Note that this gives the host machine time, not the kernel time. + * + * Hardware specific ports + * To get accurate timestamping, a hardware timer is necessary. Below are the + * available ports. Some of these are "unofficial", meaning that + * they have not yet been verified by Percepio but have been contributed by + * external developers. They should work, otherwise let us know by emailing + * support@percepio.com. Some work on any OS platform, while other are specific + * to a certain operating system. + *****************************************************************************/ + +/****** Port Name ************************************* Code ** Official ** OS Platform *********/ +#define TRC_HARDWARE_PORT_APPLICATION_DEFINED 98 /* - - */ +#define TRC_HARDWARE_PORT_NOT_SET 99 /* - - */ +#define TRC_HARDWARE_PORT_HWIndependent 0 /* Yes Any */ +#define TRC_HARDWARE_PORT_Win32 1 /* Yes FreeRTOS on Win32 */ +#define TRC_HARDWARE_PORT_Atmel_AT91SAM7 2 /* No Any */ +#define TRC_HARDWARE_PORT_Atmel_UC3A0 3 /* No Any */ +#define TRC_HARDWARE_PORT_ARM_Cortex_M 4 /* Yes Any */ +#define TRC_HARDWARE_PORT_Renesas_RX600 6 /* Yes Any */ +#define TRC_HARDWARE_PORT_MICROCHIP_PIC24_PIC32 7 /* Yes Any */ +#define TRC_HARDWARE_PORT_TEXAS_INSTRUMENTS_TMS570_RM48 8 /* Yes Any */ +#define TRC_HARDWARE_PORT_TEXAS_INSTRUMENTS_MSP430 9 /* No Any */ +#define TRC_HARDWARE_PORT_XILINX_PPC405 11 /* No FreeRTOS */ +#define TRC_HARDWARE_PORT_XILINX_PPC440 12 /* No FreeRTOS */ +#define TRC_HARDWARE_PORT_XILINX_MICROBLAZE 13 /* No Any */ +#define TRC_HARDWARE_PORT_NXP_LPC210X 14 /* No Any */ +#define TRC_HARDWARE_PORT_ARM_CORTEX_A9 15 /* Yes Any */ +#define TRC_HARDWARE_PORT_POWERPC_Z4 16 /* No FreeRTOS */ +#define TRC_HARDWARE_PORT_Altera_NiosII 17 /* No Any */ +#endif /*TRC_PORTDEFINES_H*/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/Include/trcRecorder.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/Include/trcRecorder.h new file mode 100644 index 0000000..edcd5f0 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/Include/trcRecorder.h @@ -0,0 +1,1789 @@ +/******************************************************************************* + * Trace Recorder Library for Tracealyzer v4.1.5 + * Percepio AB, www.percepio.com + * + * trcRecorder.h + * + * The public API of the trace recorder. + * + * Terms of Use + * This file is part of the trace recorder library (RECORDER), which is the + * intellectual property of Percepio AB (PERCEPIO) and provided under a + * license as follows. + * The RECORDER may be used free of charge for the purpose of recording data + * intended for analysis in PERCEPIO products. It may not be used or modified + * for other purposes without explicit permission from PERCEPIO. + * You may distribute the RECORDER in its original source code form, assuming + * this text (terms of use, disclaimer, copyright notice) is unchanged. You are + * allowed to distribute the RECORDER with minor modifications intended for + * configuration or porting of the RECORDER, e.g., to allow using it on a + * specific processor, processor family or with a specific communication + * interface. Any such modifications should be documented directly below + * this comment block. + * + * Disclaimer + * The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty + * as to its use or performance. PERCEPIO does not and cannot warrant the + * performance or results you may obtain by using the RECORDER or documentation. + * PERCEPIO make no warranties, express or implied, as to noninfringement of + * third party rights, merchantability, or fitness for any particular purpose. + * In no event will PERCEPIO, its technology partners, or distributors be liable + * to you for any consequential, incidental or special damages, including any + * lost profits or lost savings, even if a representative of PERCEPIO has been + * advised of the possibility of such damages, or for any claim by any third + * party. Some jurisdictions do not allow the exclusion or limitation of + * incidental, consequential or special damages, or the exclusion of implied + * warranties or limitations on how long an implied warranty may last, so the + * above limitations may not apply to you. + * + * Tabs are used for indent in this file (1 tab = 4 spaces) + * + * Copyright Percepio AB, 2018. + * www.percepio.com + ******************************************************************************/ + +#ifndef TRC_RECORDER_H +#define TRC_RECORDER_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include "trcConfig.h" +#include "trcPortDefines.h" + + +#if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_SNAPSHOT) +typedef uint16_t traceString; +typedef uint8_t traceUBChannel; +typedef uint8_t traceObjectClass; + +#if (TRC_CFG_USE_16BIT_OBJECT_HANDLES == 1) +typedef uint16_t traceHandle; +#else +typedef uint8_t traceHandle; +#endif + +#include "trcHardwarePort.h" +#include "trcKernelPort.h" + +// Not available in snapshot mode +#define vTraceConsoleChannelPrintF(fmt, ...) + +#endif + +#if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING) + +typedef const char* traceString; +typedef const void* traceHandle; + +#include "trcHardwarePort.h" +#include "trcStreamingPort.h" +#include "trcKernelPort.h" + +#endif + +#if (TRC_USE_TRACEALYZER_RECORDER == 1) + +/* The user event channel for recorder warnings, must be defined in trcKernelPort.c */ +extern traceString trcWarningChannel; + +#define TRACE_GET_LOW16(value) ((uint16_t)((value) & 0x0000FFFF)) +#define TRACE_GET_HIGH16(value) ((uint16_t)(((value) >> 16) & 0x0000FFFF)) +#define TRACE_SET_LOW16(current, value) (((current) & 0xFFFF0000) | (value)) +#define TRACE_SET_HIGH16(current, value) (((current) & 0x0000FFFF) | (((uint32_t)(value)) << 16)) + +/******************************************************************************/ +/*** Common API - both Snapshot and Streaming mode ****************************/ +/******************************************************************************/ + +/****************************************************************************** +* vTraceEnable(int startOption); +* +* Initializes and optionally starts the trace, depending on the start option. +* To use the trace recorder, the startup must call vTraceEnable before any RTOS +* calls are made (including "create" calls). Three start options are provided: +* +* TRC_START: Starts the tracing directly. In snapshot mode this allows for +* starting the trace at any point in your code, assuming vTraceEnable(TRC_INIT) +* has been called in the startup. +* Can also be used for streaming without Tracealyzer control, e.g. to a local +* flash file system (assuming such a "stream port", see trcStreamingPort.h). +* +* TRC_START_AWAIT_HOST: For streaming mode only. Initializes the trace recorder +* if necessary and waits for a Start command from Tracealyzer ("Start Recording" +* button). This call is intentionally blocking! By calling vTraceEnable with +* this option from the startup code, you start tracing at this point and capture +* the early events. +* +* TRC_INIT: Initializes the trace recorder, but does not start the tracing. +* In snapshot mode, this must be followed by a vTraceEnable(TRC_START) sometime +* later. +* +* Usage examples: +* +* Snapshot trace, from startup: +* +* vTraceEnable(TRC_START); +* +* +* Snapshot trace, from a later point: +* +* vTraceEnable(TRC_INIT); +* +* ... +* vTraceEnable(TRC_START); // e.g., in task context, at some relevant event +* +* Streaming trace, from startup: +* +* vTraceEnable(TRC_START_AWAIT_HOST); // Blocks! +* +* +* Streaming trace, from a later point: +* +* vTraceEnable(TRC_INIT); +* +* +******************************************************************************/ +void vTraceEnable(int startOption); + +/****************************************************************************** + * vTracePrintF + * + * Generates "User Events", with formatted text and data, similar to a "printf". + * User Events can be used for very efficient logging from your application code. + * It is very fast since the actual string formatting is done on the host side, + * when the trace is displayed. The execution time is just some microseconds on + * a 32-bit MCU. + * + * User Events are shown as yellow labels in the main trace view of $PNAME. + * + * An advantage of User Events is that data can be plotted in the "User Event + * Signal Plot" view, visualizing any data you log as User Events, discrete + * states or control system signals (e.g. system inputs or outputs). + * + * You may group User Events into User Event Channels. The yellow User Event + * labels show the logged string, preceded by the channel name within brackets. + * + * Example: + * + * "[MyChannel] Hello World!" + * + * The User Event Channels are shown in the View Filter, which makes it easy to + * select what User Events you wish to display. User Event Channels are created + * using xTraceRegisterString(). + * + * Example: + * + * traceString adc_uechannel = xTraceRegisterString("ADC User Events"); + * ... + * vTracePrintF(adc_uechannel, + * "ADC channel %d: %d volts", + * ch, adc_reading); + * + * The following format specifiers are supported in both modes: + * %d - signed integer. + * %u - unsigned integer. + * %X - hexadecimal, uppercase. + * %x - hexadecimal, lowercase. + * %s - string (see comment below) + * + * For integer formats (%d, %u, %x, %X) you may also use width and padding. + * If using -42 as data argument, two examples are: + * "%05d" -> "-0042" + * "%5d" -> " -42". + * + * String arguments are supported in both snapshot and streaming, but in streaming + * mode you need to use xTraceRegisterString and use the returned traceString as + * the argument. In snapshot you simply provide a char* as argument. + * + * Snapshot: vTracePrintF(myChn, "my string: %s", str); + * Streaming: vTracePrintF(myChn, "my string: %s", xTraceRegisterString(str)); + * + * In snapshot mode you can specify 8-bit or 16-bit arguments to reduce RAM usage: + * %hd -> 16 bit (h) signed integer (d). + * %bu -> 8 bit (b) unsigned integer (u). + * + * However, in streaming mode all data arguments are assumed to be 32 bit wide. + * Width specifiers (e.g. %hd) are accepted but ignored (%hd treated like %d). + * + * The maximum event size also differs between the modes. In streaming this is + * limited by a maximum payload size of 52 bytes, including format string and + * data arguments. So if using one data argument, the format string is limited + * to 48 byte, etc. If this is exceeded, the format string is truncated and you + * get a warning in Tracealyzer. + * + * In snapshot mode you are limited to maximum 15 arguments, that must not exceed + * 32 bytes in total (not counting the format string). If exceeded, the recorder + * logs an internal error (displayed when opening the trace) and stops recording. + ******************************************************************************/ +#if (TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1) +void vTracePrintF(traceString chn, const char* fmt, ...); +#else +#define vTracePrintF(chn, ...) (void)chn +#endif + + /****************************************************************************** +* vTracePrint +* +* A faster version of vTracePrintF, that only allows for logging a string. +* +* Example: +* +* traceString chn = xTraceRegisterString("MyChannel"); +* ... +* vTracePrint(chn, "Hello World!"); +******************************************************************************/ +#if (TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1) +void vTracePrint(traceString chn, const char* str); +#else +#define vTracePrint(chn, ...) (void)chn +#endif + + +/******************************************************************************* +* vTraceConsoleChannelPrintF +* +* Wrapper for vTracePrint, using the default channel. Can be used as a drop-in +* replacement for printf and similar functions, e.g. in a debug logging macro. +* +* Example: +* +* // Old: #define LogString debug_console_printf +* +* // New, log to Tracealyzer instead: +* #define LogString vTraceConsoleChannelPrintF +* ... +* LogString("My value is: %d", myValue); +******************************************************************************/ +#if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING) +void vTraceConsoleChannelPrintF(const char* fmt, ...); +#endif + +/******************************************************************************* +* xTraceRegisterString +* +* Register strings in the recorder, e.g. for names of user event channels. +* +* Example: +* myEventHandle = xTraceRegisterString("MyUserEvent"); +* ... +* vTracePrintF(myEventHandle, "My value is: %d", myValue); +******************************************************************************/ +#if (TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1) +traceString xTraceRegisterString(const char* name); +#else +#define xTraceRegisterString(x) (x) +#endif + +/******************************************************************************* + * vTraceSet...Name(void* object, const char* name) + * + * Parameter object: pointer to the kernel object that shall be named + * Parameter name: the name to set + * + * Kernel-specific functions for setting names of kernel objects, for display in + * Tracealyzer. + ******************************************************************************/ +/* See trcKernelPort.h for details (kernel-specific) */ + +/******************************************************************************* + * xTraceSetISRProperties + * + * Stores a name and priority level for an Interrupt Service Routine, to allow + * for better visualization. Returns a traceHandle used by vTraceStoreISRBegin. + * + * Example: + * #define PRIO_ISR_TIMER1 3 // the hardware priority of the interrupt + * ... + * traceHandle Timer1Handle = xTraceSetISRProperties("ISRTimer1", PRIO_ISR_TIMER1); + * ... + * void ISR_handler() + * { + * vTraceStoreISRBegin(Timer1Handle); + * ... + * vTraceStoreISREnd(0); + * } + ******************************************************************************/ +traceHandle xTraceSetISRProperties(const char* name, uint8_t priority); + +/******************************************************************************* + * vTraceStoreISRBegin + * + * Registers the beginning of an Interrupt Service Routine, using a traceHandle + * provided by xTraceSetISRProperties. + * + * Example: + * #define PRIO_ISR_TIMER1 3 // the hardware priority of the interrupt + * ... + * traceHandle Timer1Handle = xTraceSetISRProperties("ISRTimer1", PRIO_ISR_TIMER1); + * ... + * void ISR_handler() + * { + * vTraceStoreISRBegin(Timer1Handle); + * ... + * vTraceStoreISREnd(0); + * } + ******************************************************************************/ +void vTraceStoreISRBegin(traceHandle handle); + +/******************************************************************************* + * vTraceStoreISREnd + * + * Registers the end of an Interrupt Service Routine. + * + * The parameter pendingISR indicates if the interrupt has requested a + * task-switch (= 1), e.g., by signaling a semaphore. Otherwise (= 0) the + * interrupt is assumed to return to the previous context. + * + * Example: + * #define PRIO_OF_ISR_TIMER1 3 // the hardware priority of the interrupt + * traceHandle traceHandleIsrTimer1 = 0; // The ID set by the recorder + * ... + * traceHandleIsrTimer1 = xTraceSetISRProperties("ISRTimer1", PRIO_OF_ISR_TIMER1); + * ... + * void ISR_handler() + * { + * vTraceStoreISRBegin(traceHandleIsrTimer1); + * ... + * vTraceStoreISREnd(0); + * } + ******************************************************************************/ +void vTraceStoreISREnd(int isTaskSwitchRequired); + +/******************************************************************************* + * vTraceInstanceFinishNow + * + * Creates an event that ends the current task instance at this very instant. + * This makes the viewer to splits the current fragment at this point and begin + * a new actor instance, even if no task-switch has occurred. + *****************************************************************************/ +void vTraceInstanceFinishedNow(void); + +/******************************************************************************* + * vTraceInstanceFinishedNext + * + * Marks the current "task instance" as finished on the next kernel call. + * + * If that kernel call is blocking, the instance ends after the blocking event + * and the corresponding return event is then the start of the next instance. + * If the kernel call is not blocking, the viewer instead splits the current + * fragment right before the kernel call, which makes this call the first event + * of the next instance. + *****************************************************************************/ +void vTraceInstanceFinishedNext(void); + +/******************************************************************************* + * xTraceGetLastError + * + * Returns the last error or warning as a string, or NULL if none. + *****************************************************************************/ +const char* xTraceGetLastError(void); + +/******************************************************************************* + * vTraceClearError + * + * Clears any errors. + *****************************************************************************/ +void vTraceClearError(void); + +/******************************************************************************* +* vTraceStop +* +* Stops the recording. Intended for snapshot mode or if streaming without +* Tracealyzer control (e.g., to a device file system). +******************************************************************************/ +void vTraceStop(void); + +/****************************************************************************** +* vTraceSetFrequency +* +* Registers the clock rate of the time source for the event timestamping. +* This is normally not required, but if the default value (TRC_HWTC_FREQ_HZ) +* should be incorrect for your setup, you can override it using this function. +* +* Must be called prior to vTraceEnable, and the time source is assumed to +* have a fixed clock frequency after the startup. +* +* Note that, in snapshot mode, the value is divided by the TRC_HWTC_DIVISOR. +* This is a software "prescaler" that is also applied on the timestamps. +*****************************************************************************/ +void vTraceSetFrequency(uint32_t frequency); + +/******************************************************************************* +* vTraceSetRecorderDataBuffer +* +* The trcConfig.h setting TRC_CFG_RECORDER_BUFFER_ALLOCATION allows for selecting +* custom allocation (TRC_RECORDER_BUFFER_ALLOCATION_CUSTOM), which allows you to +* control where the recorder trace buffer is allocated. +* +* When custom allocation is selected, use TRC_ALLOC_CUSTOM_BUFFER to make the +* allocation (in global context) and then call vTraceSetRecorderDataBuffer to +* register the allocated buffer. This supports both snapshot and streaming, +* and has no effect if using other allocation modes than CUSTOM. +* +* NOTE: vTraceSetRecorderDataBuffer must be called before vTraceEnable. +******************************************************************************/ +#if (TRC_CFG_RECORDER_BUFFER_ALLOCATION == TRC_RECORDER_BUFFER_ALLOCATION_CUSTOM) +void vTraceSetRecorderDataBuffer(void* pRecorderData); +#else +#define vTraceSetRecorderDataBuffer(pRecorderData) +#endif + + +/******************************************************************************* +* TRC_ALLOC_CUSTOM_BUFFER +* +* If using custom allocation of the trace buffer (i.e., your trcConfig.h has the +* setting TRC_RECORDER_BUFFER_ALLOCATION_CUSTOM), this macro allows you to declare +* the trace buffer in a portable way that works both in snapshot and streaming. +* +* This macro has no effect if using another allocation mode, so you can easily +* switch between different recording modes and configurations, using the same +* initialization code. +* +* This translates to a single static allocation, on which you can apply linker +* directives to place it in a particular memory region. +* +* - Snapshot mode: "RecorderDataType " +* +* - Streaming mode: "char []", +* where is defined in trcStreamingConfig.h. +* +* Example: +* +* // GCC example: place myTraceBuffer in section .tz, defined in the .ld file. +* TRC_ALLOC_CUSTOM_BUFFER(myTraceBuffer) __attribute__((section(".tz"))); +* +* int main(void) +* { +* ... +* vTraceSetRecorderDataBuffer(&myTraceBuffer); // Note the "&" +* ... +* vTraceEnable(TRC_INIT); // Initialize the data structure +******************************************************************************/ +#if (TRC_CFG_RECORDER_BUFFER_ALLOCATION == TRC_RECORDER_BUFFER_ALLOCATION_CUSTOM) + #if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_SNAPSHOT) + #define TRC_ALLOC_CUSTOM_BUFFER(bufname) RecorderDataType bufname; + #elif (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING) + #ifdef TRC_CFG_RTT_BUFFER_SIZE_UP /* J-Link RTT */ + #define TRC_ALLOC_CUSTOM_BUFFER(bufname) char bufname [TRC_CFG_RTT_BUFFER_SIZE_UP]; /* Not static in this case, since declared in user code */ + #else + #define TRC_ALLOC_CUSTOM_BUFFER(bufname) char bufname [(TRC_CFG_PAGED_EVENT_BUFFER_PAGE_COUNT) * (TRC_CFG_PAGED_EVENT_BUFFER_PAGE_SIZE)]; + #endif + #endif +#else + #define TRC_ALLOC_CUSTOM_BUFFER(bufname) +#endif + +/****************************************************************************** +* xTraceIsRecordingEnabled +* +* Returns true (1) if the recorder is enabled (i.e. is recording), otherwise 0. +******************************************************************************/ +int xTraceIsRecordingEnabled(void); + +/******************************************************************************* +* vTraceSetFilterGroup +* +* Sets the "filter group" to assign when creating RTOS objects, such as tasks, +* queues, semaphores and mutexes. This together with vTraceSetFilterMask +* allows you to control what events that are recorded, based on the +* objects they refer to. +* +* There are 16 filter groups named FilterGroup0 .. FilterGroup15. +* +* Note: We don't recommend filtering out the Idle task, so make sure to call +* vTraceSetFilterGroup just before initializing the RTOS, in order to assign +* such "default" objects to the right Filter Group (typically group 0). +* +* Example: +* +* // Assign tasks T1 to FilterGroup0 (default) +* +* +* // Assign Q1 and Q2 to FilterGroup1 +* vTraceSetFilterGroup(FilterGroup1); +* +* +* +* // Assigns Q3 to FilterGroup2 +* vTraceSetFilterGroup(FilterGroup2); +* +* +* // Only include FilterGroup0 and FilterGroup2, exclude FilterGroup1 (Q1 and Q2) from the trace +* vTraceSetFilterMask( FilterGroup0 | FilterGroup2 ); +* +* // Assign the default RTOS objects (e.g. Idle task) to FilterGroup0 +* vTraceSetFilterGroup(FilterGroup0); +* +* +* Note that you may define your own names for the filter groups using +* preprocessor definitions, to make the code easier to understand. +* +* Example: +* +* #define BASE FilterGroup0 +* #define USB_EVENTS FilterGroup1 +* #define CAN_EVENTS FilterGroup2 +* +* Note that filtering per event type (regardless of object) is also available +* in trcConfig.h. +******************************************************************************/ +void vTraceSetFilterGroup(uint16_t filterGroup); + +/****************************************************************************** +* vTraceSetFilterMask +* +* Sets the "filter mask" that is used to filter the events by object. This can +* be used to reduce the trace data rate, i.e., if your streaming interface is +* a bottleneck or if you want longer snapshot traces without increasing the +* buffer size. +* +* Note: There are two kinds of filters in the recorder. The other filter type +* excludes all events of certain kinds (e.g., OS ticks). See trcConfig.h. +* +* The filtering is based on bitwise AND with the Filter Group ID, assigned +* to RTOS objects such as tasks, queues, semaphores and mutexes. +* This together with vTraceSetFilterGroup allows you to control what +* events that are recorded, based on the objects they refer to. +* +* See example for vTraceSetFilterGroup. +******************************************************************************/ +void vTraceSetFilterMask(uint16_t filterMask); + +#if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_SNAPSHOT) + +/******************************************************************************/ +/*** Extended API for Snapshot mode *******************************************/ +/******************************************************************************/ + +/****************************************************************************** +* TRACE_STOP_HOOK - Hook Pointer Data Type +* +* Declares a data type for a call back function that will be invoked whenever +* the recorder is stopped. +* +* Snapshot mode only! +******************************************************************************/ +typedef void(*TRACE_STOP_HOOK)(void); + +/******************************************************************************* +* vTraceStopHookPtr +* +* Points to a call back function that is called from vTraceStop(). +* +* Snapshot mode only! +******************************************************************************/ +extern TRACE_STOP_HOOK vTraceStopHookPtr; + +/******************************************************************************* +* vTraceSetStopHook +* +* Sets a function to be called when the recorder is stopped. +* +* Snapshot mode only! +******************************************************************************/ +void vTraceSetStopHook(TRACE_STOP_HOOK stopHookFunction); + +/******************************************************************************* +* uiTraceStart +* +* [DEPRECATED] Use vTraceEnable instead. +* +* Starts the recorder. The recorder will not be started if an error has been +* indicated using prvTraceError, e.g. if any of the Nx constants in +* trcSnapshotConfig.h has a too small value (TRC_CFG_NTASK, TRC_CFG_NQUEUE, etc). +* +* Returns 1 if the recorder was started successfully. +* Returns 0 if the recorder start was prevented due to a previous internal +* error. In that case, check xTraceGetLastError to get the error message. +* Any error message is also presented when opening a trace file. +* +* Snapshot mode only! +******************************************************************************/ +uint32_t uiTraceStart(void); + +/******************************************************************************* +* vTraceStart +* +* [DEPRECATED] Use vTraceEnable instead. +* +* Starts the recorder. The recorder will not be started if an error has been +* indicated using prvTraceError, e.g. if any of the Nx constants in +* trcSnapshotConfig.h has a too small value (TRC_CFG_NTASK, TRC_CFG_NQUEUE, etc). +* +* Snapshot mode only! +******************************************************************************/ +void vTraceStart(void); + +/******************************************************************************* +* vTraceClear +* +* Resets the recorder. Only necessary if a restart is desired - this is not +* needed in the startup initialization. +* +* Snapshot mode only! +******************************************************************************/ +void vTraceClear(void); + + +/*****************************************************************************/ +/*** INTERNAL SNAPSHOT FUNCTIONS *********************************************/ +/*****************************************************************************/ + +#define TRC_UNUSED + +#ifndef TRC_CFG_INCLUDE_OBJECT_DELETE +#define TRC_CFG_INCLUDE_OBJECT_DELETE 0 +#endif + +#ifndef TRC_CFG_INCLUDE_READY_EVENTS +#define TRC_CFG_INCLUDE_READY_EVENTS 1 +#endif + +#ifndef TRC_CFG_INCLUDE_OSTICK_EVENTS +#define TRC_CFG_INCLUDE_OSTICK_EVENTS 0 +#endif + +/* This macro will create a task in the object table */ +#undef trcKERNEL_HOOKS_TASK_CREATE +#define trcKERNEL_HOOKS_TASK_CREATE(SERVICE, CLASS, pxTCB) \ + TRACE_SET_OBJECT_NUMBER(TASK, pxTCB); \ + TRACE_SET_OBJECT_FILTER(TASK, pxTCB, CurrentFilterGroup); \ + prvTraceSetObjectName(TRACE_CLASS_TASK, TRACE_GET_TASK_NUMBER(pxTCB), TRACE_GET_TASK_NAME(pxTCB)); \ + prvTraceSetPriorityProperty(TRACE_CLASS_TASK, TRACE_GET_TASK_NUMBER(pxTCB), TRACE_GET_TASK_PRIORITY(pxTCB)); \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(TASK, pxTCB) & CurrentFilterMask) \ + prvTraceStoreKernelCall(SERVICE, TRACE_CLASS_TASK, TRACE_GET_TASK_NUMBER(pxTCB)); + +/* This macro will remove the task and store it in the event buffer */ +#undef trcKERNEL_HOOKS_TASK_DELETE +#define trcKERNEL_HOOKS_TASK_DELETE(SERVICE, SERVICE_NAME, SERVICE_PROP, pxTCB) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(TASK, pxTCB) & CurrentFilterMask) \ + prvTraceStoreKernelCall(SERVICE, TRACE_CLASS_TASK, TRACE_GET_TASK_NUMBER(pxTCB)); \ + prvTraceStoreObjectNameOnCloseEvent(SERVICE_NAME, TRACE_GET_TASK_NUMBER(pxTCB), TRACE_CLASS_TASK); \ + prvTraceStoreObjectPropertiesOnCloseEvent(SERVICE_PROP, TRACE_GET_TASK_NUMBER(pxTCB), TRACE_CLASS_TASK); \ + prvTraceSetPriorityProperty(TRACE_CLASS_TASK, TRACE_GET_TASK_NUMBER(pxTCB), TRACE_GET_TASK_PRIORITY(pxTCB)); \ + prvTraceSetObjectState(TRACE_CLASS_TASK, TRACE_GET_TASK_NUMBER(pxTCB), TASK_STATE_INSTANCE_NOT_ACTIVE); \ + prvTraceFreeObjectHandle(TRACE_CLASS_TASK, TRACE_GET_TASK_NUMBER(pxTCB)); + + +/* This macro will setup a task in the object table */ +#undef trcKERNEL_HOOKS_OBJECT_CREATE +#define trcKERNEL_HOOKS_OBJECT_CREATE(SERVICE, CLASS, pxObject)\ + TRACE_SET_OBJECT_NUMBER(CLASS, pxObject);\ + TRACE_SET_OBJECT_FILTER(CLASS, pxObject, CurrentFilterGroup); \ + prvMarkObjectAsUsed(TRACE_GET_OBJECT_TRACE_CLASS(CLASS, pxObject), TRACE_GET_OBJECT_NUMBER(CLASS, pxObject));\ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(CLASS, pxObject) & CurrentFilterMask) \ + prvTraceStoreKernelCall(SERVICE, TRACE_GET_OBJECT_TRACE_CLASS(CLASS, pxObject), TRACE_GET_OBJECT_NUMBER(CLASS, pxObject)); \ + prvTraceSetObjectState(TRACE_GET_OBJECT_TRACE_CLASS(CLASS, pxObject), TRACE_GET_OBJECT_NUMBER(CLASS, pxObject), 0); + +/* This macro will remove the object and store it in the event buffer */ +#undef trcKERNEL_HOOKS_OBJECT_DELETE +#define trcKERNEL_HOOKS_OBJECT_DELETE(SERVICE, SERVICE_NAME, SERVICE_PROP, CLASS, pxObject) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(CLASS, pxObject) & CurrentFilterMask) \ + prvTraceStoreKernelCall(SERVICE, TRACE_GET_OBJECT_TRACE_CLASS(CLASS, pxObject), TRACE_GET_OBJECT_NUMBER(CLASS, pxObject)); \ + prvTraceStoreObjectNameOnCloseEvent(SERVICE_NAME, TRACE_GET_OBJECT_NUMBER(CLASS, pxObject), TRACE_GET_OBJECT_TRACE_CLASS(CLASS, pxObject)); \ + prvTraceStoreObjectPropertiesOnCloseEvent(SERVICE_PROP, TRACE_GET_OBJECT_NUMBER(CLASS, pxObject), TRACE_GET_OBJECT_TRACE_CLASS(CLASS, pxObject)); \ + prvTraceFreeObjectHandle(TRACE_GET_OBJECT_TRACE_CLASS(CLASS, pxObject), TRACE_GET_OBJECT_NUMBER(CLASS, pxObject)); + +/* This macro will create a call to a kernel service with a certain result, with an object as parameter */ +#undef trcKERNEL_HOOKS_KERNEL_SERVICE +#define trcKERNEL_HOOKS_KERNEL_SERVICE(SERVICE, CLASS, pxObject) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(CLASS, pxObject) & CurrentFilterMask) \ + prvTraceStoreKernelCall(SERVICE, TRACE_GET_OBJECT_TRACE_CLASS(CLASS, pxObject), TRACE_GET_OBJECT_NUMBER(CLASS, pxObject)); + +/* This macro will create a call to a kernel service with a certain result, with a null object as parameter */ +#undef trcKERNEL_HOOKS_KERNEL_SERVICE_NULL_OBJECT +#define trcKERNEL_HOOKS_KERNEL_SERVICE_NULL_OBJECT(SERVICE, TRACECLASS) \ + if (TRACE_GET_TASK_FILTER(TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + prvTraceStoreKernelCall(SERVICE, TRACECLASS, 0); + +/* This macro will create a call to a kernel service with a certain result, with an object as parameter */ +#undef trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_PARAM +#define trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_PARAM(SERVICE, CLASS, pxObject, param) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(CLASS, pxObject) & CurrentFilterMask) \ + prvTraceStoreKernelCallWithParam(SERVICE, TRACE_GET_OBJECT_TRACE_CLASS(CLASS, pxObject), TRACE_GET_OBJECT_NUMBER(CLASS, pxObject), (uint32_t)param); + +/* This macro will create a call to a kernel service with a certain result, with a null object and other value as parameter */ +#undef trcKERNEL_HOOKS_KERNEL_SERVICE_NULL_OBJECT_WITH_PARAM +#define trcKERNEL_HOOKS_KERNEL_SERVICE_NULL_OBJECT_WITH_PARAM(SERVICE, TRACECLASS, param) \ + if (TRACE_GET_TASK_FILTER(TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + prvTraceStoreKernelCallWithParam(SERVICE, TRACECLASS, 0, param); + +/* This macro will create a call to a kernel service with a certain result, with an object as parameter */ +#undef trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_NUMERIC_PARAM_ONLY +#define trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_NUMERIC_PARAM_ONLY(SERVICE, param) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + prvTraceStoreKernelCallWithNumericParamOnly(SERVICE, (uint32_t)param); + +/* This macro will create a call to a kernel service with a certain result, with an object as parameter */ +#undef trcKERNEL_HOOKS_KERNEL_SERVICE_FROM_ISR +#define trcKERNEL_HOOKS_KERNEL_SERVICE_FROM_ISR(SERVICE, CLASS, pxObject) \ + if (TRACE_GET_OBJECT_FILTER(CLASS, pxObject) & CurrentFilterMask) \ + prvTraceStoreKernelCall(SERVICE, TRACE_GET_OBJECT_TRACE_CLASS(CLASS, pxObject), TRACE_GET_OBJECT_NUMBER(CLASS, pxObject)); + +/* This macro will create a call to a kernel service with a certain result, with an object as parameter */ +#undef trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_PARAM_FROM_ISR +#define trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_PARAM_FROM_ISR(SERVICE, CLASS, pxObject, param) \ + if (TRACE_GET_OBJECT_FILTER(CLASS, pxObject) & CurrentFilterMask) \ + prvTraceStoreKernelCallWithParam(SERVICE, TRACE_GET_OBJECT_TRACE_CLASS(CLASS, pxObject), TRACE_GET_OBJECT_NUMBER(CLASS, pxObject), (uint32_t)param); + +/* This macro will create a call to a kernel service with a certain result, with an object as parameter */ +#undef trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_NUMERIC_PARAM_ONLY_FROM_ISR +#define trcKERNEL_HOOKS_KERNEL_SERVICE_WITH_NUMERIC_PARAM_ONLY_FROM_ISR(SERVICE, param) \ + prvTraceStoreKernelCallWithNumericParamOnly(SERVICE, (uint32_t)param); + +/* This macro will set the state for an object */ +#undef trcKERNEL_HOOKS_SET_OBJECT_STATE +#define trcKERNEL_HOOKS_SET_OBJECT_STATE(CLASS, pxObject, STATE) \ + prvTraceSetObjectState(TRACE_GET_OBJECT_TRACE_CLASS(CLASS, pxObject), TRACE_GET_OBJECT_NUMBER(CLASS, pxObject), (uint8_t)STATE); + +/* This macro will flag a certain task as a finished instance */ +#undef trcKERNEL_HOOKS_SET_TASK_INSTANCE_FINISHED +#define trcKERNEL_HOOKS_SET_TASK_INSTANCE_FINISHED() \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + prvTraceSetTaskInstanceFinished(TRACE_GET_TASK_NUMBER(TRACE_GET_CURRENT_TASK())); + +#if (TRC_CFG_INCLUDE_READY_EVENTS == 1) +/* This macro will create an event to indicate that a task became Ready */ +#undef trcKERNEL_HOOKS_MOVED_TASK_TO_READY_STATE +#define trcKERNEL_HOOKS_MOVED_TASK_TO_READY_STATE(pxTCB) \ + if (TRACE_GET_OBJECT_FILTER(TASK, pxTCB) & CurrentFilterMask) \ + prvTraceStoreTaskReady(TRACE_GET_TASK_NUMBER(pxTCB)); +#else /*(TRC_CFG_INCLUDE_READY_EVENTS == 1)*/ +#undef trcKERNEL_HOOKS_MOVED_TASK_TO_READY_STATE +#define trcKERNEL_HOOKS_MOVED_TASK_TO_READY_STATE(pxTCB) +#endif /*(TRC_CFG_INCLUDE_READY_EVENTS == 1)*/ + +/* This macro will update the internal tick counter and call prvTracePortGetTimeStamp(0) to update the internal counters */ +#undef trcKERNEL_HOOKS_INCREMENT_TICK +#define trcKERNEL_HOOKS_INCREMENT_TICK() \ + { \ + extern uint32_t uiTraceTickCount; \ + uiTraceTickCount++; \ + prvTracePortGetTimeStamp(0); \ + } + +#if (TRC_CFG_INCLUDE_OSTICK_EVENTS == 1) +/* This macro will create an event indicating that the OS tick count has increased */ +#undef trcKERNEL_HOOKS_NEW_TIME +#define trcKERNEL_HOOKS_NEW_TIME(SERVICE, xValue) \ + prvTraceStoreKernelCallWithNumericParamOnly(SERVICE, xValue); +#else /*(TRC_CFG_INCLUDE_OSTICK_EVENTS == 1)*/ +#undef trcKERNEL_HOOKS_NEW_TIME +#define trcKERNEL_HOOKS_NEW_TIME(SERVICE, xValue) +#endif /*(TRC_CFG_INCLUDE_OSTICK_EVENTS == 1)*/ + +/* This macro will create a task switch event to the currently executing task */ +#undef trcKERNEL_HOOKS_TASK_SWITCH +#define trcKERNEL_HOOKS_TASK_SWITCH( pxTCB ) \ + if (TRACE_GET_OBJECT_FILTER(TASK, pxTCB) & CurrentFilterMask) \ + prvTraceStoreTaskswitch(TRACE_GET_TASK_NUMBER(pxTCB)); + +/* This macro will create an event to indicate that the task has been suspended */ +#undef trcKERNEL_HOOKS_TASK_SUSPEND +#define trcKERNEL_HOOKS_TASK_SUSPEND(SERVICE, pxTCB) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(TASK, pxTCB) & CurrentFilterMask) \ + prvTraceStoreKernelCall(SERVICE, TRACE_CLASS_TASK, TRACE_GET_TASK_NUMBER(pxTCB)); \ + prvTraceSetTaskInstanceFinished((uint8_t)TRACE_GET_TASK_NUMBER(pxTCB)); + +/* This macro will create an event to indicate that a task has called a wait/delay function */ +#undef trcKERNEL_HOOKS_TASK_DELAY +#define trcKERNEL_HOOKS_TASK_DELAY(SERVICE, pxTCB, xValue) \ + if (TRACE_GET_OBJECT_FILTER(TASK, pxTCB) & CurrentFilterMask) \ + { \ + prvTraceStoreKernelCallWithNumericParamOnly(SERVICE, xValue); \ + prvTraceSetTaskInstanceFinished((uint8_t)TRACE_GET_TASK_NUMBER(pxTCB)); \ + } + +/* This macro will create an event to indicate that a task has gotten its priority changed */ +#undef trcKERNEL_HOOKS_TASK_PRIORITY_CHANGE +#define trcKERNEL_HOOKS_TASK_PRIORITY_CHANGE(SERVICE, pxTCB, uxNewPriority) \ + if (TRACE_GET_OBJECT_FILTER(TASK, pxTCB) & CurrentFilterMask) \ + { \ + prvTraceStoreKernelCallWithParam(SERVICE, TRACE_CLASS_TASK, TRACE_GET_TASK_NUMBER(pxTCB), prvTraceGetPriorityProperty(TRACE_CLASS_TASK, TRACE_GET_TASK_NUMBER(pxTCB)));\ + prvTraceSetPriorityProperty(TRACE_CLASS_TASK, TRACE_GET_TASK_NUMBER(pxTCB), (uint8_t)uxNewPriority); \ + } + +/* This macro will create an event to indicate that the task has been resumed */ +#undef trcKERNEL_HOOKS_TASK_RESUME +#define trcKERNEL_HOOKS_TASK_RESUME(SERVICE, pxTCB) \ + if (TRACE_GET_OBJECT_FILTER(TASK, TRACE_GET_CURRENT_TASK()) & CurrentFilterMask) \ + if (TRACE_GET_OBJECT_FILTER(TASK, pxTCB) & CurrentFilterMask) \ + prvTraceStoreKernelCall(SERVICE, TRACE_CLASS_TASK, TRACE_GET_TASK_NUMBER(pxTCB)); + +#undef trcKERNEL_HOOKS_TASK_RESUME_FROM_ISR +#define trcKERNEL_HOOKS_TASK_RESUME_FROM_ISR(SERVICE, pxTCB) \ + if (TRACE_GET_OBJECT_FILTER(TASK, pxTCB) & CurrentFilterMask) \ + prvTraceStoreKernelCall(SERVICE, TRACE_CLASS_TASK, TRACE_GET_TASK_NUMBER(pxTCB)); + +#if !defined TRC_CFG_INCLUDE_READY_EVENTS || TRC_CFG_INCLUDE_READY_EVENTS == 1 + void prvTraceSetReadyEventsEnabled(int status); + void prvTraceStoreTaskReady(traceHandle handle); +#else + #define prvTraceSetReadyEventsEnabled(status) +#endif + +void prvTraceStoreLowPower(uint32_t flag); + +void prvTraceStoreTaskswitch(traceHandle task_handle); + + +#if (TRC_CFG_SCHEDULING_ONLY == 0) + +void prvTraceStoreKernelCall(uint32_t eventcode, traceObjectClass objectClass, uint32_t byteParam); + +void prvTraceStoreKernelCallWithNumericParamOnly(uint32_t evtcode, uint32_t param); + +void prvTraceStoreKernelCallWithParam(uint32_t evtcode, traceObjectClass objectClass, + uint32_t objectNumber, uint32_t param); +#else + +#define prvTraceStoreKernelCall(eventcode, objectClass, byteParam) {} +#define prvTraceStoreKernelCallWithNumericParamOnly(evtcode, param) {} +#define prvTraceStoreKernelCallWithParam(evtcode, objectClass, objectNumber, param) {} + +#endif + +void prvTraceSetTaskInstanceFinished(traceHandle handle); + +void prvTraceSetPriorityProperty(uint8_t objectclass, traceHandle id, uint8_t value); + +uint8_t prvTraceGetPriorityProperty(uint8_t objectclass, traceHandle id); + +void prvTraceSetObjectState(uint8_t objectclass, traceHandle id, uint8_t value); + +void prvMarkObjectAsUsed(traceObjectClass objectclass, traceHandle handle); + +void prvTraceStoreObjectNameOnCloseEvent(uint8_t evtcode, traceHandle handle, + traceObjectClass objectclass); + +void prvTraceStoreObjectPropertiesOnCloseEvent(uint8_t evtcode, traceHandle handle, + traceObjectClass objectclass); + +/* Internal constants for task state */ +#define TASK_STATE_INSTANCE_NOT_ACTIVE 0 +#define TASK_STATE_INSTANCE_ACTIVE 1 + + +#if (TRC_CFG_INCLUDE_ISR_TRACING == 0) + +#undef vTraceSetISRProperties +#define vTraceSetISRProperties(handle, name, priority) + +#undef vTraceStoreISRBegin +#define vTraceStoreISRBegin(x) (void)x + +#undef vTraceStoreISREnd +#define vTraceStoreISREnd(x) (void)x + +#undef xTraceSetISRProperties +#define xTraceSetISRProperties(name, priority) 0 + +#endif /*(TRC_CFG_INCLUDE_ISR_TRACING == 0)*/ + +/******************************************************************************* + * xTraceGetTraceBuffer + * + * Returns a pointer to the recorder data structure. Use this together with + * uiTraceGetTraceBufferSize if you wish to implement an own store/upload + * solution, e.g., in case a debugger connection is not available for uploading + * the data. + ******************************************************************************/ +void* xTraceGetTraceBuffer(void); + +/******************************************************************************* + * uiTraceGetTraceBufferSize + * + * Gets the size of the recorder data structure. For use together with + * vTraceGetTraceBuffer if you wish to implement an own store/upload solution, + * e.g., in case a debugger connection is not available for uploading the data. + ******************************************************************************/ +uint32_t uiTraceGetTraceBufferSize(void); + +#if (TRC_CFG_SCHEDULING_ONLY == 1) +#undef TRC_CFG_INCLUDE_USER_EVENTS +#define TRC_CFG_INCLUDE_USER_EVENTS 0 +#endif /*(TRC_CFG_SCHEDULING_ONLY == 1)*/ + +#if ((TRC_CFG_INCLUDE_USER_EVENTS == 1) && (TRC_CFG_SCHEDULING_ONLY == 0)) + +#if (TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER == 1) +traceUBChannel xTraceRegisterUBChannel(traceString channel, traceString formatStr); +void vTraceUBData(traceUBChannel channel, ...); +void vTraceUBEvent(traceUBChannel channel); +#endif /*(TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER == 1)*/ + +#else /*((TRC_CFG_INCLUDE_USER_EVENTS == 1) && (TRC_CFG_SCHEDULING_ONLY == 0))*/ + +#undef vTracePrint +#define vTracePrint(chn, ...) (void)chn +#undef vTracePrintF +#define vTracePrintF(chn, ...) (void)chn +#undef xTraceRegisterString +#define xTraceRegisterString(x) 0; (void)x; +#undef xTraceRegisterChannelFormat +#define xTraceRegisterChannelFormat(eventLabel, formatStr) 0 +#undef vTraceUBData +#define vTraceUBData(label, ...) {} +#undef vTraceChannelPrint +#define vTraceChannelPrint(label) {} + +#endif /*(TRC_CFG_INCLUDE_USER_EVENTS == 1)*/ + +#define NEventCodes 0x100 + +/* Our local critical sections for the recorder */ +#define trcCRITICAL_SECTION_BEGIN() {TRACE_ENTER_CRITICAL_SECTION(); recorder_busy++;} +#define trcCRITICAL_SECTION_END() {recorder_busy--; TRACE_EXIT_CRITICAL_SECTION();} + +#if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_Cortex_M) + #define trcSR_ALLOC_CRITICAL_SECTION_ON_CORTEX_M_ONLY TRACE_ALLOC_CRITICAL_SECTION + #define trcCRITICAL_SECTION_BEGIN_ON_CORTEX_M_ONLY trcCRITICAL_SECTION_BEGIN + #define trcCRITICAL_SECTION_END_ON_CORTEX_M_ONLY trcCRITICAL_SECTION_END +#else + #define trcSR_ALLOC_CRITICAL_SECTION_ON_CORTEX_M_ONLY() {} + #define trcCRITICAL_SECTION_BEGIN_ON_CORTEX_M_ONLY() recorder_busy++; + #define trcCRITICAL_SECTION_END_ON_CORTEX_M_ONLY() recorder_busy--; +#endif + +/****************************************************************************** + * ObjectHandleStack + * This data-structure is used to provide a mechanism for 1-byte trace object + * handles. This way, only 1 byte is necessary instead of 4 bytes (a pointer) + * when storing a reference to an object. This allows for up to 255 objects of + * each object class active at any given moment. There can be more "historic" + * objects, that have been deleted - that number is only limited by the size of + * the symbol table. + * + * Note that handle zero (0) is not used, it is a code for an invalid handle. + * + * This data structure keeps track of the FREE handles, not the handles in use. + * This data structure contains one stack per object class. When a handle is + * allocated to an object, the next free handle is popped from the stack. When + * a handle is released (on object delete), it is pushed back on the stack. + * Note that there is no initialization code that pushed the free handles + * initially, that is not necessary due to the following optimization: + * + * The stack of handles (objectHandles) is initially all zeros. Since zero + * is not a valid handle, that is a signal of additional handles needed. + * If a zero is received when popping a new handle, it is replaced by the + * index of the popped handle instead. + *****************************************************************************/ +typedef struct +{ + /* For each object class, the index of the next handle to allocate */ + uint16_t indexOfNextAvailableHandle[ TRACE_NCLASSES ]; + + /* The lowest index of this class (constant) */ + uint16_t lowestIndexOfClass[ TRACE_NCLASSES ]; + + /* The highest index of this class (constant) */ + uint16_t highestIndexOfClass[ TRACE_NCLASSES ]; + + /* The highest use count for this class (for statistics) */ + uint16_t handleCountWaterMarksOfClass[ TRACE_NCLASSES ]; + + /* The free object handles - a set of stacks within this array */ + traceHandle objectHandles[ TRACE_KERNEL_OBJECT_COUNT ]; + +} objectHandleStackType; + +extern objectHandleStackType objectHandleStacks; + +/****************************************************************************** + * Object Property Table + * The Object Table contains name and other properties of the objects (tasks, + * queues, mutexes, etc). The below data structures defines the properties of + * each object class and are used to cast the byte buffer into a cleaner format. + * + * The values in the object table are continuously overwritten and always + * represent the current state. If a property is changed during runtime, the OLD + * value should be stored in the trace buffer, not the new value (since the new + * value is found in the Object Property Table). + * + * For close events this mechanism is the old names are stored in the symbol + * table), for "priority set" (the old priority is stored in the event data) + * and for "isActive", where the value decides if the task switch event type + * should be "new" or "resume". + ******************************************************************************/ + +typedef struct +{ + /* = NCLASSES */ + uint32_t NumberOfObjectClasses; + + uint32_t ObjectPropertyTableSizeInBytes; + + /* This is used to calculate the index in the dynamic object table + (handle - 1 - nofStaticObjects = index)*/ +#if (TRC_CFG_USE_16BIT_OBJECT_HANDLES == 1) + traceHandle NumberOfObjectsPerClass[2*((TRACE_NCLASSES+1)/2)]; +#else + traceHandle NumberOfObjectsPerClass[4*((TRACE_NCLASSES+3)/4)]; +#endif + + /* Allocation size rounded up to the closest multiple of 4 */ + uint8_t NameLengthPerClass[ 4*((TRACE_NCLASSES+3)/4) ]; + + uint8_t TotalPropertyBytesPerClass[ 4*((TRACE_NCLASSES+3)/4) ]; + + /* Allocation size rounded up to the closest multiple of 2 */ + uint16_t StartIndexOfClass[ 2*((TRACE_NCLASSES+1)/2) ]; + + /* The actual handles issued, should be Initiated to all zeros */ + uint8_t objbytes[ 4*((TRACE_OBJECT_TABLE_SIZE+3)/4) ]; +} ObjectPropertyTableType; + +/* Symbol table data structure */ +typedef struct +{ + /* = SYMBOL_HISTORY_TABLE_SIZE_IN_BYTES */ + uint32_t symTableSize; + + /* Entry 0 is reserved. Any reference to entry 0 implies NULL*/ + uint32_t nextFreeSymbolIndex; + + /* Size rounded up to closest multiple of 4, to avoid alignment issues*/ + uint8_t symbytes[4*(((TRC_CFG_SYMBOL_TABLE_SIZE)+3)/4)]; + + /* Used for lookups - Up to 64 linked lists within the symbol table + connecting all entries with the same 6 bit checksum. + This field holds the current list heads. Should be initiated to zeros */ + uint16_t latestEntryOfChecksum[64]; +} symbolTableType; + + +/******************************************************************************* + * The data structures of the different events, all 4 bytes long + ******************************************************************************/ + +typedef struct +{ + uint8_t type; + uint8_t objHandle; + uint16_t dts; /* differential timestamp - time since last event */ +} TSEvent, TREvent; + +typedef struct +{ + uint8_t type; + uint8_t dummy; + uint16_t dts; /* differential timestamp - time since last event */ +} LPEvent; + +typedef struct +{ + uint8_t type; + uint8_t objHandle; + uint16_t dts; /* differential timestamp - time since last event */ +} KernelCall; + +typedef struct +{ + uint8_t type; + uint8_t objHandle; + uint8_t param; + uint8_t dts; /* differential timestamp - time since last event */ +} KernelCallWithParamAndHandle; + +typedef struct +{ + uint8_t type; + uint8_t dts; /* differential timestamp - time since last event */ + uint16_t param; +} KernelCallWithParam16; + +typedef struct +{ + uint8_t type; + uint8_t objHandle; /* the handle of the closed object */ + uint16_t symbolIndex; /* the name of the closed object */ +} ObjCloseNameEvent; + +typedef struct +{ + uint8_t type; + uint8_t arg1; + uint8_t arg2; + uint8_t arg3; +} ObjClosePropEvent; + +typedef struct +{ + uint8_t type; + uint8_t unused1; + uint8_t unused2; + uint8_t dts; +} TaskInstanceStatusEvent; + +typedef struct +{ + uint8_t type; + uint8_t dts; + uint16_t payload; /* the name of the user event */ +} UserEvent; + +typedef struct +{ + uint8_t type; + + /* 8 bits extra for storing DTS, if it does not fit in ordinary event + (this one is always MSB if used) */ + uint8_t xts_8; + + /* 16 bits extra for storing DTS, if it does not fit in ordinary event. */ + uint16_t xts_16; +} XTSEvent; + +typedef struct +{ + uint8_t type; + + uint8_t xps_8; + uint16_t xps_16; +} XPSEvent; + +typedef struct{ + uint8_t type; + uint8_t dts; + uint16_t size; +} MemEventSize; + +typedef struct{ + uint8_t type; + uint8_t addr_high; + uint16_t addr_low; +} MemEventAddr; + +/******************************************************************************* + * The separate user event buffer structure. Can be enabled in trcConfig.h. + ******************************************************************************/ + +#if (TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER == 1) +typedef struct +{ + traceString name; + traceString defaultFormat; +} ChannelFormatPair; + +typedef struct +{ + uint16_t bufferID; + uint16_t version; + uint32_t wraparoundCounter; + uint32_t numberOfSlots; + uint32_t nextSlotToWrite; + uint8_t numberOfChannels; + uint8_t padding1; + uint8_t padding2; + uint8_t padding3; + ChannelFormatPair channels[(TRC_CFG_UB_CHANNELS)+1]; + uint8_t channelBuffer[((TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE) + 3) & 0xFFFFFFFC]; /* 1 byte per slot, with padding for 4 byte alignment */ + uint8_t dataBuffer[(TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE) * 4]; /* 4 bytes per slot */ + +} UserEventBuffer; +#endif + +/******************************************************************************* + * The main data structure, read by Tracealyzer from the RAM dump + ******************************************************************************/ + +typedef struct +{ + volatile uint8_t startmarker0; /* Volatile is important, see init code. */ + volatile uint8_t startmarker1; + volatile uint8_t startmarker2; + volatile uint8_t startmarker3; + volatile uint8_t startmarker4; + volatile uint8_t startmarker5; + volatile uint8_t startmarker6; + volatile uint8_t startmarker7; + volatile uint8_t startmarker8; + volatile uint8_t startmarker9; + volatile uint8_t startmarker10; + volatile uint8_t startmarker11; + + /* Used to determine Kernel and Endianess */ + uint16_t version; + + /* Currently 5 */ + uint8_t minor_version; + + /* This should be 0 if lower IRQ priority values implies higher priority + levels, such as on ARM Cortex M. If the opposite scheme is used, i.e., + if higher IRQ priority values means higher priority, this should be 1. */ + uint8_t irq_priority_order; + + /* sizeof(RecorderDataType) - just for control */ + uint32_t filesize; + + /* Current number of events recorded */ + uint32_t numEvents; + + /* The buffer size, in number of event records */ + uint32_t maxEvents; + + /* The event buffer index, where to write the next event */ + uint32_t nextFreeIndex; + + /* 1 if the buffer is full, 0 otherwise */ + uint32_t bufferIsFull; + + /* The frequency of the clock/timer/counter used as time base */ + uint32_t frequency; + + /* The absolute timestamp of the last stored event, in the native + timebase, modulo frequency! */ + uint32_t absTimeLastEvent; + + /* The number of seconds in total - lasts for 136 years */ + uint32_t absTimeLastEventSecond; + + /* 1 if the recorder has been started, 0 if not yet started or stopped. + This is a 32 bit variable due to alignment issues. */ + uint32_t recorderActive; + + /* If > 0, tells the maximum time between two traced ISRs that execute + back-to-back. If the time between vTraceStoreISREnd and a directly + following vTraceISRBegin is above isrTailchainingThreshold, we assume a + return to the previous context in between the ISRs, otherwise we assume + the have executed back-to-back and don't show any fragment of the previous + context in between. */ + uint32_t isrTailchainingThreshold; + + /* Not used, remains for compatibility and future use */ + uint8_t notused[24]; + + /* The amount of heap memory remaining at the last malloc or free event */ + uint32_t heapMemUsage; + + /* 0xF0F0F0F0 - for control only */ + int32_t debugMarker0; + + /* Set to value of TRC_CFG_USE_16BIT_OBJECT_HANDLES */ + uint32_t isUsing16bitHandles; + + /* The Object Property Table holds information about currently active + tasks, queues, and other recorded objects. This is updated on each + create call and includes object name and other properties. */ + ObjectPropertyTableType ObjectPropertyTable; + + /* 0xF1F1F1F1 - for control only */ + int32_t debugMarker1; + + /* The Symbol Table stores strings for User Events and is also used to + store names of deleted objects, which still may be in the trace but no + longer are available. */ + symbolTableType SymbolTable; + + /* For inclusion of float support, and for endian detection of floats. + The value should be (float)1 or (uint32_t)0 */ +#if (TRC_CFG_INCLUDE_FLOAT_SUPPORT == 1) + float exampleFloatEncoding; +#else + uint32_t exampleFloatEncoding; +#endif + /* This is non-zero if an internal error occurred in the recorder, e.g., if + one of the Nxxx constants was too small. The systemInfo string will then + contain an error message that is displayed when attempting to view the + trace file. */ + uint32_t internalErrorOccured; + + /* 0xF2F2F2F2 - for control only */ + int32_t debugMarker2; + + /* Error messages from the recorder. */ + char systemInfo[80]; + + /* 0xF3F3F3F3 - for control only */ + int32_t debugMarker3; + + /* The event data, in 4-byte records */ + uint8_t eventData[ (TRC_CFG_EVENT_BUFFER_SIZE) * 4 ]; + +#if (TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER == 1) + UserEventBuffer userEventBuffer; +#endif + + /* This should always be 0 */ + uint32_t endOfSecondaryBlocks; + + uint8_t endmarker0; + uint8_t endmarker1; + uint8_t endmarker2; + uint8_t endmarker3; + uint8_t endmarker4; + uint8_t endmarker5; + uint8_t endmarker6; + uint8_t endmarker7; + uint8_t endmarker8; + uint8_t endmarker9; + uint8_t endmarker10; + uint8_t endmarker11; +} RecorderDataType; + +extern RecorderDataType* RecorderDataPtr; + +/* Internal functions */ + +/* Signal an error. */ +void prvTraceError(const char* msg); + +/******************************************************************************* + * prvTracePortGetTimeStamp + * + * Returns the current time based on the HWTC macros which provide a hardware + * isolation layer towards the hardware timer/counter. + * + * The HWTC macros and prvTracePortGetTimeStamp is the main porting issue + * or the trace recorder library. Typically you should not need to change + * the code of prvTracePortGetTimeStamp if using the HWTC macros. + * + ******************************************************************************/ +void prvTracePortGetTimeStamp(uint32_t *puiTimestamp); + +traceHandle prvTraceGetObjectHandle(traceObjectClass objectclass); + +void prvTraceFreeObjectHandle(traceObjectClass objectclass, + traceHandle handle); + +/* Private function. Use the public functions in trcKernelPort.h */ +void prvTraceSetObjectName(traceObjectClass objectclass, + traceHandle handle, + const char* name); + +/* Internal macros */ + +#define TRACE_PROPERTY_NAME_GET(objectclass, objecthandle) \ +(const char*)(& RecorderDataPtr->ObjectPropertyTable.objbytes \ +[uiIndexOfObject(objecthandle, objectclass)]) + +#define TRACE_PROPERTY_OBJECT_STATE(objectclass, handle) \ +RecorderDataPtr->ObjectPropertyTable.objbytes[uiIndexOfObject(handle, objectclass) \ ++ RecorderDataPtr->ObjectPropertyTable.NameLengthPerClass[objectclass]] + +#define TRACE_PROPERTY_ACTOR_PRIORITY(objectclass, handle) \ +RecorderDataPtr->ObjectPropertyTable.objbytes[uiIndexOfObject(handle, objectclass) \ ++ RecorderDataPtr->ObjectPropertyTable.NameLengthPerClass[objectclass] + 1] + +/* DEBUG ASSERTS */ +#if defined TRC_CFG_USE_TRACE_ASSERT && TRC_CFG_USE_TRACE_ASSERT != 0 +#define TRACE_ASSERT(eval, msg, defRetVal) \ +if (!(eval)) \ +{ \ + prvTraceError("TRACE_ASSERT: " msg); \ + return defRetVal; \ +} +#else +#define TRACE_ASSERT(eval, msg, defRetVal) +#endif + +#endif /*(TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_SNAPSHOT)*/ + +#if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING) + +/****************************************************************************** + * Default values for STREAM PORT macros + * + * As a normal user, this is nothing you don't need to bother about. This is + * only important if you want to define your own custom streaming interface. + * + * You may override these in your own trcStreamingPort.h to create a custom + * stream port, and thereby stream the trace on any host-target interface. + * These default values are suitable for most cases, except the J-Link port. + ******************************************************************************/ + +/****************************************************************************** + * TRC_STREAM_PORT_USE_INTERNAL_BUFFER + * + * There are two kinds of stream ports, those that store the event to the + * internal buffer (with periodic flushing by the TzCtrl task) and those that + * write directly to the streaming interface. Most stream ports use the + * recorder's internal buffer, except for the SEGGER J-Link port (also uses a + * RAM buffer, but one defined in the SEGGER code). + * + * If the stream port (trcStreamingPort.h) defines this as zero (0), it is + * expected to transmit the data directly using TRC_STREAM_PORT_COMMIT_EVENT. + * Otherwise it is expected that the trace data is stored in the internal buffer + * and the TzCtrl task will then send the buffer pages when they become full. + ******************************************************************************/ +#ifndef TRC_STREAM_PORT_USE_INTERNAL_BUFFER +#define TRC_STREAM_PORT_USE_INTERNAL_BUFFER 1 +#endif + + /****************************************************************************** + * TRC_STREAM_PORT_ON_TRACE_BEGIN + * + * Defining any actions needed in the stream port when the recording is activated. + *******************************************************************************/ +#ifndef TRC_STREAM_PORT_ON_TRACE_BEGIN + #define TRC_STREAM_PORT_ON_TRACE_BEGIN() /* Do nothing */ +#endif + + /****************************************************************************** + * TRC_STREAM_PORT_ON_TRACE_BEGIN + * + * Defining any actions needed in the stream port when the tracing stops. + * Empty by default. + *******************************************************************************/ +#ifndef TRC_STREAM_PORT_ON_TRACE_END +#define TRC_STREAM_PORT_ON_TRACE_END() /* Do nothing */ +#endif + + /****************************************************************************** + * TRC_STREAM_PORT_ALLOCATE_EVENT + * + * This macro is used to allocate memory for each event record, just before + * assigning the record fields. + * Depending on "TRC_STREAM_PORT_USE_INTERNAL_BUFFER", this either allocates + * space in the paged event buffer, or on the local stack. In the latter case, + * the COMMIT event is used to write the data to the streaming interface. + ******************************************************************************/ +#ifndef TRC_STREAM_PORT_ALLOCATE_EVENT +#if (TRC_STREAM_PORT_USE_INTERNAL_BUFFER == 1) + #define TRC_STREAM_PORT_ALLOCATE_EVENT(_type, _ptrData, _size) _type* _ptrData; _ptrData = (_type*)prvPagedEventBufferGetWritePointer(_size); +#else + #define TRC_STREAM_PORT_ALLOCATE_EVENT(_type, _ptrData, _size) _type _tmpArray[_size / sizeof(_type)]; _type* _ptrData = _tmpArray; +#endif +#endif + + /****************************************************************************** + * TRC_STREAM_PORT_ALLOCATE_DYNAMIC_EVENT + * + * This macro is used to allocate memory for each event record, just before + * assigning the record fields. + * This has the same purpose as TRC_STREAM_PORT_ALLOCATE_EVENT and by default + * it has the same definition as TRC_STREAM_PORT_ALLOCATE_EVENT. This is used + * for events carrying variable-sized payload, such as strings. + * In the SEGGER RTT port, we need this in order to make a worst-case + * allocation on the stack. + ******************************************************************************/ +#ifndef TRC_STREAM_PORT_ALLOCATE_DYNAMIC_EVENT +#if (TRC_STREAM_PORT_USE_INTERNAL_BUFFER == 1) + #define TRC_STREAM_PORT_ALLOCATE_DYNAMIC_EVENT(_type, _ptrData, _size) TRC_STREAM_PORT_ALLOCATE_EVENT(_type, _ptrData, _size) /* We do the same thing as for non-dynamic event sizes */ +#else + #define TRC_STREAM_PORT_ALLOCATE_DYNAMIC_EVENT(_type, _ptrData, _size) _type _tmpArray[sizeof(largestEventType) / sizeof(_type)]; _type* _ptrData = _tmpArray; +#endif +#endif + + /****************************************************************************** + * TRC_STREAM_PORT_COMMIT_EVENT + * + * The COMMIT macro is used to write a single event record directly to the + * streaming inteface, without first storing the event in the internal buffer. + * This is currently only used in the SEGGER J-Link RTT port. + * + * This relies on the TRC_STREAM_PORT_WRITE_DATA macro, defined in by the + * stream port in trcStreamingPort.h. The COMMIT macro calls + * prvTraceWarning(TRC_STREAM_PORT_WRITE_DATA) if a non-zero value is returned + * from TRC_STREAM_PORT_WRITE_DATA. If zero (0) is returned, it is assumed + * that all data was successfully written. + * + * In ports using the internal buffer, this macro has no purpose as the events + * are written to the internal buffer instead. They are then flushed to the + * streaming interface in the TzCtrl task using TRC_STREAM_PORT_WRITE_DATA. + ******************************************************************************/ +#ifndef TRC_STREAM_PORT_COMMIT_EVENT +#if (TRC_STREAM_PORT_USE_INTERNAL_BUFFER == 1) + #define TRC_STREAM_PORT_COMMIT_EVENT(_ptrData, _size) /* Not used */ +#else + #define TRC_STREAM_PORT_COMMIT_EVENT(_ptrData, _size) \ + { \ + if (TRC_STREAM_PORT_WRITE_DATA(_ptrData, _size, 0) != 0)\ + prvTraceWarning(PSF_WARNING_STREAM_PORT_WRITE); \ + } +#endif +#endif + +/****************************************************************************** + * TRC_STREAM_PORT_READ_DATA (defined in trcStreamingPort.h) + * + * Defining how to read data from host (commands from Tracealyzer). + * + * If there is no direct interface to host (e.g., if streaming to a file + * system) this should be defined as 0. Instead use vTraceEnable(TRC_START) and + * vTraceStop() to control the recording from target. + * + * Parameters: + * + * - _ptrData: a pointer to a data buffer, where the received data shall be + * stored (TracealyzerCommandType*). + * + * - _size: the number of bytes to read (int). + * + * - _ptrBytesRead: a pointer to an integer (int), that should be assigned + * with the number of bytes that was received. + * + * Example: + * + * int32_t myRead(void* ptrData, uint32_t size, int32_t* ptrBytesRead); + * + * #define TRC_STREAM_PORT_READ_DATA(_ptrData, _size, _ptrBytesRead) \ + * myRead(_ptrData, _size, _ptrBytesRead) + * + * Your "myRead" function should return 0 if successful, i.e. if at least some + * bytes were received. A non-zero value should be returned if the streaming + * interface returned an error (e.g. a closed socket), which results in the + * recorder calling prvTraceWarning with the error code + * PSF_WARNING_STREAM_PORT_WRITE. + * + * If developing your own custom stream port and using the default internal + * buffer, it is important that the _ptrBytesRead parameter is assigned + * correctly by "myRead", i.e. with the number of bytes actually written. + * Otherwise the data stream may get out of sync in case the streaming interface + * can't swallow all data at once. + ******************************************************************************/ +#ifndef TRC_STREAM_PORT_READ_DATA +#error "No definition for TRC_STREAM_PORT_READ_DATA (should be in trcStreamingPort.h)" +#endif + +/****************************************************************************** + * TRC_STREAM_PORT_WRITE_DATA (defined in trcStreamingPort.h) + * + * Defining how to write trace data to the streaming interface. + * + * Parameters: + * + * - _ptrData: a pointer (void*) to the data to write. + * + * - _size: the number of bytes to write (uint32_t). + * + * - _ptrBytesWritten: a pointer to an integer (int32_t), that should be + * assigned with the number of bytes actually written. + * + * Example: + * + * int32_t myWrite(void* ptrData, uint32_t size, int32_t* ptrBytesWritten); + * + * #define TRC_STREAM_PORT_WRITE_DATA(_ptrData, _size, _ptrBytesWritten) \ + * myWrite(_ptrData, _size, _ptrBytesWritten) + * + * Your "myWrite" function should return 0 if successful, i.e. if at least some + * bytes were sent. A non-zero value should be returned if the streaming interface + * returned an error (e.g. a closed socket), which results in the recorder calling + * prvTraceWarning with the error code PSF_WARNING_STREAM_PORT_WRITE. + * + * If developing your own custom stream port and using the default internal + * buffer, it is important that the _ptrBytesWritten parameter is assigned + * correctly by "myWrite", i.e. with the number of bytes actually written. + * Otherwise the data stream may get out of sync in case the streaming interface + * can't swallow all data at once. + * + * Assuming TRC_STREAM_PORT_USE_INTERNAL_BUFFER is 1 (default), the TzCtrl task + * will use this macro to send one buffer page at a time. In case all data can't + * be written at once (if _ptrBytesWritten is less than _size), the TzCtrl task + * is smart enough to make repeated calls (with updated parameters) in order to + * send the remaining data. + * + * However, if TRC_STREAM_PORT_USE_INTERNAL_BUFFER is 0, this is used from the + * COMMIT macro, directly in the "event functions". In that case, the + * _ptrBytesWritten parameter will be NULL and should be ignored by the write + * function. In this case, it is assumed that all data can be sent in a single + * call, otherwise the write function should return a non-zero error code. + ******************************************************************************/ +#ifndef TRC_STREAM_PORT_WRITE_DATA +#error "No definition for TRC_STREAM_PORT_WRITE_DATA (should be in trcStreamingPort.h)" +#endif + +/****************************************************************************** +* Data structure declaration, depending on TRC_CFG_RECORDER_BUFFER_ALLOCATION +*******************************************************************************/ +#if (TRC_CFG_RECORDER_BUFFER_ALLOCATION == TRC_RECORDER_BUFFER_ALLOCATION_STATIC) + + /* Static allocation. */ + + /* If not defined in trcStreamingPort.h */ + #ifndef TRC_STREAM_PORT_ALLOCATE_FIELDS + #define TRC_STREAM_PORT_ALLOCATE_FIELDS() \ + char _TzTraceData[(TRC_CFG_PAGED_EVENT_BUFFER_PAGE_COUNT) * (TRC_CFG_PAGED_EVENT_BUFFER_PAGE_SIZE)]; + extern char _TzTraceData[(TRC_CFG_PAGED_EVENT_BUFFER_PAGE_COUNT) * (TRC_CFG_PAGED_EVENT_BUFFER_PAGE_SIZE)]; + #endif + + /* If not defined in trcStreamingPort.h */ + #ifndef TRC_STREAM_PORT_MALLOC + #define TRC_STREAM_PORT_MALLOC() /* Static allocation. Not used. */ + #endif +#else + /* For Dynamic or Custom Allocation mode */ + + /* If not defined in trcStreamingPort.h */ + #ifndef TRC_STREAM_PORT_ALLOCATE_FIELDS + #define TRC_STREAM_PORT_ALLOCATE_FIELDS() char* _TzTraceData = NULL; + extern char* _TzTraceData; + #endif + + /* If not defined in trcStreamingPort.h */ + #ifndef TRC_STREAM_PORT_MALLOC + #if (TRC_CFG_RECORDER_BUFFER_ALLOCATION == TRC_RECORDER_BUFFER_ALLOCATION_DYNAMIC) + #define TRC_STREAM_PORT_MALLOC() \ + _TzTraceData = TRC_PORT_MALLOC((TRC_CFG_PAGED_EVENT_BUFFER_PAGE_COUNT) * (TRC_CFG_PAGED_EVENT_BUFFER_PAGE_SIZE)); + extern char* _TzTraceData; + #else + #define TRC_STREAM_PORT_MALLOC() /* Custom allocation. Not used. */ + #endif + #endif +#endif + +#ifndef TRC_STREAM_PORT_INIT + #define TRC_STREAM_PORT_INIT() \ + TRC_STREAM_PORT_MALLOC(); /* Empty if static allocation mode */ \ + prvPagedEventBufferInit(_TzTraceData); +#endif + + +/* Signal an error. */ +void prvTraceError(int errCode); + +/* Signal an warning (does not stop the recorder). */ +void prvTraceWarning(int errCode); + +/******************************************************************************/ +/*** ERROR AND WARNING CODES (check using xTraceGetLastError) *****************/ +/******************************************************************************/ + +#define PSF_ERROR_NONE 0 +#define PSF_ERROR_EVENT_CODE_TOO_LARGE 1 +#define PSF_ERROR_ISR_NESTING_OVERFLOW 2 +#define PSF_ERROR_DWT_NOT_SUPPORTED 3 +#define PSF_ERROR_DWT_CYCCNT_NOT_SUPPORTED 4 +#define PSF_ERROR_TZCTRLTASK_NOT_CREATED 5 + +#define PSF_WARNING_SYMBOL_TABLE_SLOTS 101 +#define PSF_WARNING_SYMBOL_MAX_LENGTH 102 +#define PSF_WARNING_OBJECT_DATA_SLOTS 103 +#define PSF_WARNING_STRING_TOO_LONG 104 +#define PSF_WARNING_STREAM_PORT_READ 105 +#define PSF_WARNING_STREAM_PORT_WRITE 106 + +/******************************************************************************/ +/*** INTERNAL STREAMING FUNCTIONS *********************************************/ +/******************************************************************************/ + +/* Saves a symbol name (task name etc.) in symbol table */ +void prvTraceSaveSymbol(const void *address, const char *name); + +/* Deletes a symbol name (task name etc.) from symbol table */ +void prvTraceDeleteSymbol(void *address); + +/* Saves an object data entry (task base priority) in object data table */ +void prvTraceSaveObjectData(const void *address, uint32_t data); + +/* Removes an object data entry (task base priority) from object data table */ +void prvTraceDeleteObjectData(void *address); + +/* Store an event with zero parameters (event ID only) */ +void prvTraceStoreEvent0(uint16_t eventID); + +/* Store an event with one 32-bit parameter (pointer address or an int) */ +void prvTraceStoreEvent1(uint16_t eventID, + uint32_t param1); + +/* Store an event with two 32-bit parameters */ +void prvTraceStoreEvent2(uint16_t eventID, + uint32_t param1, + uint32_t param2); + +/* Store an event with three 32-bit parameters */ +void prvTraceStoreEvent3(uint16_t eventID, + uint32_t param1, + uint32_t param2, + uint32_t param3); + +/* Stores an event with 32-bit integer parameters */ +void prvTraceStoreEvent(int nParam, uint16_t EventID, ...); + +/* Stories an event with a string and 32-bit integer parameters */ +void prvTraceStoreStringEvent(int nArgs, uint16_t eventID, const char* str, ...); + +/* Initializes the paged event buffer used by certain stream ports */ +void prvPagedEventBufferInit(char* buffer); + +/* Retrieve a pointer to the paged event buffer */ +void* prvPagedEventBufferGetWritePointer(int sizeOfEvent); + +/* Transfer a full buffer page */ +uint32_t prvPagedEventBufferTransfer(void); + +/* The data structure for commands (a bit overkill) */ +typedef struct +{ + unsigned char cmdCode; + unsigned char param1; + unsigned char param2; + unsigned char param3; + unsigned char param4; + unsigned char param5; + unsigned char checksumLSB; + unsigned char checksumMSB; +} TracealyzerCommandType; + +/* Checks if the provided command is a valid command */ +int prvIsValidCommand(TracealyzerCommandType* cmd); + +/* Executed the received command (Start or Stop) */ +void prvProcessCommand(TracealyzerCommandType* cmd); + +#define vTraceSetStopHook(x) + +#endif /*(TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING)*/ + +#else /* when TRC_USE_TRACEALYZER_RECORDER == 0 */ + +#define vTraceEnable(x) +#define xTraceRegisterString(x) 0; (void)x; +#define vTracePrint(chn, ...) (void)chn +#define vTracePrintF(chn, ...) (void)chn +#define vTraceInstanceFinishedNow() +#define vTraceInstanceFinishedNext() +#define vTraceStoreISRBegin(x) (void)x +#define vTraceStoreISREnd(x) (void)x +#define xTraceSetISRProperties(a, b) 0 +#define vTraceStoreKernelObjectName(a, b) +#define xTraceRegisterChannelFormat(eventLabel, formatStr) 0 +#define vTraceChannelPrint(label) +#define vTraceUBData(label, ...) + +#define vTraceSetFilterGroup(x) +#define vTraceSetFilterMask(x) + +#define prvTraceSetReadyEventsEnabled(status) + +#define vTraceExcludeTask(handle) + +#define uiTraceStart() (1) +#define vTraceStart() +#define vTraceStop() + +#ifndef vTraceSetRecorderDataBuffer +#define vTraceSetRecorderDataBuffer(pRecorderData) +#endif + +#define vTraceConsoleChannelPrintF(fmt, ...) + +#ifndef TRC_ALLOC_CUSTOM_BUFFER +#define TRC_ALLOC_CUSTOM_BUFFER(bufname) +#endif + +#define xTraceIsRecordingEnabled() (0) + +#define vTraceSetStopHook(x) + +#endif /*(TRC_USE_TRACEALYZER_RECORDER == 1)*/ + +#ifdef __cplusplus +} +#endif + +#endif /* TRC_RECORDER_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/ReadMe.url b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/ReadMe.url new file mode 100644 index 0000000..251da66 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/ReadMe.url @@ -0,0 +1,5 @@ +[InternetShortcut] +URL=http://www.freertos.org/trace +IDList= +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/config/trcConfig.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/config/trcConfig.h new file mode 100644 index 0000000..dceb6d8 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/config/trcConfig.h @@ -0,0 +1,301 @@ +/******************************************************************************* + * Trace Recorder Library for Tracealyzer v4.1.4 + * Percepio AB, www.percepio.com + * + * trcConfig.h + * + * Main configuration parameters for the trace recorder library. + * More settings can be found in trcStreamingConfig.h and trcSnapshotConfig.h. + * + * Read more at http://percepio.com/2016/10/05/rtos-tracing/ + * + * Terms of Use + * This file is part of the trace recorder library (RECORDER), which is the + * intellectual property of Percepio AB (PERCEPIO) and provided under a + * license as follows. + * The RECORDER may be used free of charge for the purpose of recording data + * intended for analysis in PERCEPIO products. It may not be used or modified + * for other purposes without explicit permission from PERCEPIO. + * You may distribute the RECORDER in its original source code form, assuming + * this text (terms of use, disclaimer, copyright notice) is unchanged. You are + * allowed to distribute the RECORDER with minor modifications intended for + * configuration or porting of the RECORDER, e.g., to allow using it on a + * specific processor, processor family or with a specific communication + * interface. Any such modifications should be documented directly below + * this comment block. + * + * Disclaimer + * The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty + * as to its use or performance. PERCEPIO does not and cannot warrant the + * performance or results you may obtain by using the RECORDER or documentation. + * PERCEPIO make no warranties, express or implied, as to noninfringement of + * third party rights, merchantability, or fitness for any particular purpose. + * In no event will PERCEPIO, its technology partners, or distributors be liable + * to you for any consequential, incidental or special damages, including any + * lost profits or lost savings, even if a representative of PERCEPIO has been + * advised of the possibility of such damages, or for any claim by any third + * party. Some jurisdictions do not allow the exclusion or limitation of + * incidental, consequential or special damages, or the exclusion of implied + * warranties or limitations on how long an implied warranty may last, so the + * above limitations may not apply to you. + * + * Tabs are used for indent in this file (1 tab = 4 spaces) + * + * Copyright Percepio AB, 2018. + * www.percepio.com + ******************************************************************************/ + +#ifndef TRC_CONFIG_H +#define TRC_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "trcPortDefines.h" + +/****************************************************************************** + * Include of processor header file + * + * Here you may need to include the header file for your processor. This is + * required at least for the ARM Cortex-M port, that uses the ARM CMSIS API. + * Try that in case of build problems. Otherwise, remove the #error line below. + *****************************************************************************/ +#error "Trace Recorder: Please include your processor's header file here and remove this line." + +/******************************************************************************* + * Configuration Macro: TRC_CFG_HARDWARE_PORT + * + * Specify what hardware port to use (i.e., the "timestamping driver"). + * + * All ARM Cortex-M MCUs are supported by "TRC_HARDWARE_PORT_ARM_Cortex_M". + * This port uses the DWT cycle counter for Cortex-M3/M4/M7 devices, which is + * available on most such devices. In case your device don't have DWT support, + * you will get an error message opening the trace. In that case, you may + * force the recorder to use SysTick timestamping instead, using this define: + * + * #define TRC_CFG_ARM_CM_USE_SYSTICK + * + * For ARM Cortex-M0/M0+ devices, SysTick mode is used automatically. + * + * See trcHardwarePort.h for available ports and information on how to + * define your own port, if not already present. + ******************************************************************************/ +#define TRC_CFG_HARDWARE_PORT TRC_HARDWARE_PORT_NOT_SET + +/******************************************************************************* + * Configuration Macro: TRC_CFG_RECORDER_MODE + * + * Specify what recording mode to use. Snapshot means that the data is saved in + * an internal RAM buffer, for later upload. Streaming means that the data is + * transferred continuously to the host PC. + * + * For more information, see http://percepio.com/2016/10/05/rtos-tracing/ + * and the Tracealyzer User Manual. + * + * Values: + * TRC_RECORDER_MODE_SNAPSHOT + * TRC_RECORDER_MODE_STREAMING + ******************************************************************************/ +#define TRC_CFG_RECORDER_MODE TRC_RECORDER_MODE_SNAPSHOT + +/****************************************************************************** + * TRC_CFG_FREERTOS_VERSION + * + * Specify what version of FreeRTOS that is used (don't change unless using the + * trace recorder library with an older version of FreeRTOS). + * + * TRC_FREERTOS_VERSION_7_3 If using FreeRTOS v7.3.x + * TRC_FREERTOS_VERSION_7_4 If using FreeRTOS v7.4.x + * TRC_FREERTOS_VERSION_7_5_OR_7_6 If using FreeRTOS v7.5.0 - v7.6.0 + * TRC_FREERTOS_VERSION_8_X If using FreeRTOS v8.X.X + * TRC_FREERTOS_VERSION_9_0_0 If using FreeRTOS v9.0.0 + * TRC_FREERTOS_VERSION_9_0_1 If using FreeRTOS v9.0.1 + * TRC_FREERTOS_VERSION_9_0_2 If using FreeRTOS v9.0.2 + * TRC_FREERTOS_VERSION_10_0_0 If using FreeRTOS v10.0.0 or later + *****************************************************************************/ +#define TRC_CFG_FREERTOS_VERSION TRC_FREERTOS_VERSION_10_0_0 + +/******************************************************************************* + * TRC_CFG_SCHEDULING_ONLY + * + * Macro which should be defined as an integer value. + * + * If this setting is enabled (= 1), only scheduling events are recorded. + * If disabled (= 0), all events are recorded (unless filtered in other ways). + * + * Default value is 0 (= include additional events). + ******************************************************************************/ +#define TRC_CFG_SCHEDULING_ONLY 0 + + /****************************************************************************** + * TRC_CFG_INCLUDE_MEMMANG_EVENTS + * + * Macro which should be defined as either zero (0) or one (1). + * + * This controls if malloc and free calls should be traced. Set this to zero (0) + * to exclude malloc/free calls, or one (1) to include such events in the trace. + * + * Default value is 1. + *****************************************************************************/ +#define TRC_CFG_INCLUDE_MEMMANG_EVENTS 1 + + /****************************************************************************** + * TRC_CFG_INCLUDE_USER_EVENTS + * + * Macro which should be defined as either zero (0) or one (1). + * + * If this is zero (0), all code related to User Events is excluded in order + * to reduce code size. Any attempts of storing User Events are then silently + * ignored. + * + * User Events are application-generated events, like "printf" but for the + * trace log, generated using vTracePrint and vTracePrintF. + * The formatting is done on host-side, by Tracealyzer. User Events are + * therefore much faster than a console printf and can often be used + * in timing critical code without problems. + * + * Note: In streaming mode, User Events are used to provide error messages + * and warnings from the recorder (in case of incorrect configuration) for + * display in Tracealyzer. Disabling user events will also disable these + * warnings. You can however still catch them by calling xTraceGetLastError + * or by putting breakpoints in prvTraceError and prvTraceWarning. + * + * Default value is 1. + *****************************************************************************/ +#define TRC_CFG_INCLUDE_USER_EVENTS 1 + + /***************************************************************************** + * TRC_CFG_INCLUDE_ISR_TRACING + * + * Macro which should be defined as either zero (0) or one (1). + * + * If this is zero (0), the code for recording Interrupt Service Routines is + * excluded, in order to reduce code size. + * + * Default value is 1. + * + * Note: tracing ISRs requires that you insert calls to vTraceStoreISRBegin + * and vTraceStoreISREnd in your interrupt handlers. + *****************************************************************************/ +#define TRC_CFG_INCLUDE_ISR_TRACING 1 + + /***************************************************************************** + * TRC_CFG_INCLUDE_READY_EVENTS + * + * Macro which should be defined as either zero (0) or one (1). + * + * If one (1), events are recorded when tasks enter scheduling state "ready". + * This allows Tracealyzer to show the initial pending time before tasks enter + * the execution state, and present accurate response times. + * If zero (0), "ready events" are not created, which allows for recording + * longer traces in the same amount of RAM. + * + * Default value is 1. + *****************************************************************************/ +#define TRC_CFG_INCLUDE_READY_EVENTS 1 + + /***************************************************************************** + * TRC_CFG_INCLUDE_OSTICK_EVENTS + * + * Macro which should be defined as either zero (0) or one (1). + * + * If this is one (1), events will be generated whenever the OS clock is + * increased. If zero (0), OS tick events are not generated, which allows for + * recording longer traces in the same amount of RAM. + * + * Default value is 1. + *****************************************************************************/ +#define TRC_CFG_INCLUDE_OSTICK_EVENTS 1 + + /***************************************************************************** + * TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS + * + * Macro which should be defined as either zero (0) or one (1). + * + * If this is zero (0), the trace will exclude any "event group" events. + * + * Default value is 0 (excluded) since dependent on event_groups.c + *****************************************************************************/ +#define TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS 0 + + /***************************************************************************** + * TRC_CFG_INCLUDE_TIMER_EVENTS + * + * Macro which should be defined as either zero (0) or one (1). + * + * If this is zero (0), the trace will exclude any Timer events. + * + * Default value is 0 since dependent on timers.c + *****************************************************************************/ +#define TRC_CFG_INCLUDE_TIMER_EVENTS 0 + + /***************************************************************************** + * TRC_CFG_INCLUDE_PEND_FUNC_CALL_EVENTS + * + * Macro which should be defined as either zero (0) or one (1). + * + * If this is zero (0), the trace will exclude any "pending function call" + * events, such as xTimerPendFunctionCall(). + * + * Default value is 0 since dependent on timers.c + *****************************************************************************/ +#define TRC_CFG_INCLUDE_PEND_FUNC_CALL_EVENTS 0 + +/******************************************************************************* + * Configuration Macro: TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS + * + * Macro which should be defined as either zero (0) or one (1). + * + * If this is zero (0), the trace will exclude any stream buffer or message + * buffer events. + * + * Default value is 0 since dependent on stream_buffer.c (new in FreeRTOS v10) + ******************************************************************************/ +#define TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS 0 + +/******************************************************************************* + * Configuration Macro: TRC_CFG_RECORDER_BUFFER_ALLOCATION + * + * Specifies how the recorder buffer is allocated (also in case of streaming, in + * port using the recorder's internal temporary buffer) + * + * Values: + * TRC_RECORDER_BUFFER_ALLOCATION_STATIC - Static allocation (internal) + * TRC_RECORDER_BUFFER_ALLOCATION_DYNAMIC - Malloc in vTraceEnable + * TRC_RECORDER_BUFFER_ALLOCATION_CUSTOM - Use vTraceSetRecorderDataBuffer + * + * Static and dynamic mode does the allocation for you, either in compile time + * (static) or in runtime (malloc). + * The custom mode allows you to control how and where the allocation is made, + * for details see TRC_ALLOC_CUSTOM_BUFFER and vTraceSetRecorderDataBuffer(). + ******************************************************************************/ +#define TRC_CFG_RECORDER_BUFFER_ALLOCATION TRC_RECORDER_BUFFER_ALLOCATION_STATIC + +/****************************************************************************** + * TRC_CFG_MAX_ISR_NESTING + * + * Defines how many levels of interrupt nesting the recorder can handle, in + * case multiple ISRs are traced and ISR nesting is possible. If this + * is exceeded, the particular ISR will not be traced and the recorder then + * logs an error message. This setting is used to allocate an internal stack + * for keeping track of the previous execution context (4 byte per entry). + * + * This value must be a non-zero positive constant, at least 1. + * + * Default value: 8 + *****************************************************************************/ +#define TRC_CFG_MAX_ISR_NESTING 8 + +/* Specific configuration, depending on Streaming/Snapshot mode */ +#if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_SNAPSHOT) +#include "trcSnapshotConfig.h" +#elif (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING) +#include "trcStreamingConfig.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _TRC_CONFIG_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/config/trcSnapshotConfig.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/config/trcSnapshotConfig.h new file mode 100644 index 0000000..5ce12fc --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/config/trcSnapshotConfig.h @@ -0,0 +1,377 @@ +/******************************************************************************* + * Trace Recorder Library for Tracealyzer v4.1.4 + * Percepio AB, www.percepio.com + * + * trcSnapshotConfig.h + * + * Configuration parameters for trace recorder library in snapshot mode. + * Read more at http://percepio.com/2016/10/05/rtos-tracing/ + * + * Terms of Use + * This file is part of the trace recorder library (RECORDER), which is the + * intellectual property of Percepio AB (PERCEPIO) and provided under a + * license as follows. + * The RECORDER may be used free of charge for the purpose of recording data + * intended for analysis in PERCEPIO products. It may not be used or modified + * for other purposes without explicit permission from PERCEPIO. + * You may distribute the RECORDER in its original source code form, assuming + * this text (terms of use, disclaimer, copyright notice) is unchanged. You are + * allowed to distribute the RECORDER with minor modifications intended for + * configuration or porting of the RECORDER, e.g., to allow using it on a + * specific processor, processor family or with a specific communication + * interface. Any such modifications should be documented directly below + * this comment block. + * + * Disclaimer + * The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty + * as to its use or performance. PERCEPIO does not and cannot warrant the + * performance or results you may obtain by using the RECORDER or documentation. + * PERCEPIO make no warranties, express or implied, as to noninfringement of + * third party rights, merchantability, or fitness for any particular purpose. + * In no event will PERCEPIO, its technology partners, or distributors be liable + * to you for any consequential, incidental or special damages, including any + * lost profits or lost savings, even if a representative of PERCEPIO has been + * advised of the possibility of such damages, or for any claim by any third + * party. Some jurisdictions do not allow the exclusion or limitation of + * incidental, consequential or special damages, or the exclusion of implied + * warranties or limitations on how long an implied warranty may last, so the + * above limitations may not apply to you. + * + * Tabs are used for indent in this file (1 tab = 4 spaces) + * + * Copyright Percepio AB, 2018. + * www.percepio.com + ******************************************************************************/ + +#ifndef TRC_SNAPSHOT_CONFIG_H +#define TRC_SNAPSHOT_CONFIG_H + +#define TRC_SNAPSHOT_MODE_RING_BUFFER (0x01) +#define TRC_SNAPSHOT_MODE_STOP_WHEN_FULL (0x02) + +/****************************************************************************** + * TRC_CFG_SNAPSHOT_MODE + * + * Macro which should be defined as one of: + * - TRC_SNAPSHOT_MODE_RING_BUFFER + * - TRC_SNAPSHOT_MODE_STOP_WHEN_FULL + * Default is TRC_SNAPSHOT_MODE_RING_BUFFER. + * + * With TRC_CFG_SNAPSHOT_MODE set to TRC_SNAPSHOT_MODE_RING_BUFFER, the + * events are stored in a ring buffer, i.e., where the oldest events are + * overwritten when the buffer becomes full. This allows you to get the last + * events leading up to an interesting state, e.g., an error, without having + * to store the whole run since startup. + * + * When TRC_CFG_SNAPSHOT_MODE is TRC_SNAPSHOT_MODE_STOP_WHEN_FULL, the + * recording is stopped when the buffer becomes full. This is useful for + * recording events following a specific state, e.g., the startup sequence. + *****************************************************************************/ +#define TRC_CFG_SNAPSHOT_MODE TRC_SNAPSHOT_MODE_RING_BUFFER + +/******************************************************************************* + * TRC_CFG_EVENT_BUFFER_SIZE + * + * Macro which should be defined as an integer value. + * + * This defines the capacity of the event buffer, i.e., the number of records + * it may store. Most events use one record (4 byte), although some events + * require multiple 4-byte records. You should adjust this to the amount of RAM + * available in the target system. + * + * Default value is 1000, which means that 4000 bytes is allocated for the + * event buffer. + ******************************************************************************/ +#define TRC_CFG_EVENT_BUFFER_SIZE 1000 + +/******************************************************************************* + * TRC_CFG_NTASK, TRC_CFG_NISR, TRC_CFG_NQUEUE, TRC_CFG_NSEMAPHORE... + * + * A group of macros which should be defined as integer values, zero or larger. + * + * These define the capacity of the Object Property Table, i.e., the maximum + * number of objects active at any given point, within each object class (e.g., + * task, queue, semaphore, ...). + * + * If tasks or other objects are deleted in your system, this + * setting does not limit the total amount of objects created, only the number + * of objects that have been successfully created but not yet deleted. + * + * Using too small values will cause vTraceError to be called, which stores an + * error message in the trace that is shown when opening the trace file. The + * error message can also be retrieved using xTraceGetLastError. + * + * It can be wise to start with large values for these constants, + * unless you are very confident on these numbers. Then do a recording and + * check the actual usage by selecting View menu -> Trace Details -> + * Resource Usage -> Object Table. + ******************************************************************************/ +#define TRC_CFG_NTASK 15 +#define TRC_CFG_NISR 5 +#define TRC_CFG_NQUEUE 10 +#define TRC_CFG_NSEMAPHORE 10 +#define TRC_CFG_NMUTEX 10 +#define TRC_CFG_NTIMER 5 +#define TRC_CFG_NEVENTGROUP 5 +#define TRC_CFG_NSTREAMBUFFER 5 +#define TRC_CFG_NMESSAGEBUFFER 5 + +/****************************************************************************** + * TRC_CFG_INCLUDE_FLOAT_SUPPORT + * + * Macro which should be defined as either zero (0) or one (1). + * + * If this is zero (0), the support for logging floating point values in + * vTracePrintF is stripped out, in case floating point values are not used or + * supported by the platform used. + * + * Floating point values are only used in vTracePrintF and its subroutines, to + * allow for storing float (%f) or double (%lf) arguments. + * + * vTracePrintF can be used with integer and string arguments in either case. + * + * Default value is 0. + *****************************************************************************/ +#define TRC_CFG_INCLUDE_FLOAT_SUPPORT 0 + +/******************************************************************************* + * TRC_CFG_SYMBOL_TABLE_SIZE + * + * Macro which should be defined as an integer value. + * + * This defines the capacity of the symbol table, in bytes. This symbol table + * stores User Events labels and names of deleted tasks, queues, or other kernel + * objects. If you don't use User Events or delete any kernel + * objects you set this to a very low value. The minimum recommended value is 4. + * A size of zero (0) is not allowed since a zero-sized array may result in a + * 32-bit pointer, i.e., using 4 bytes rather than 0. + * + * Default value is 800. + ******************************************************************************/ +#define TRC_CFG_SYMBOL_TABLE_SIZE 800 + +#if (TRC_CFG_SYMBOL_TABLE_SIZE == 0) +#error "TRC_CFG_SYMBOL_TABLE_SIZE may not be zero!" +#endif + +/****************************************************************************** + * TRC_CFG_NAME_LEN_TASK, TRC_CFG_NAME_LEN_QUEUE, ... + * + * Macros that specify the maximum lengths (number of characters) for names of + * kernel objects, such as tasks and queues. If longer names are used, they will + * be truncated when stored in the recorder. + *****************************************************************************/ +#define TRC_CFG_NAME_LEN_TASK 15 +#define TRC_CFG_NAME_LEN_ISR 15 +#define TRC_CFG_NAME_LEN_QUEUE 15 +#define TRC_CFG_NAME_LEN_SEMAPHORE 15 +#define TRC_CFG_NAME_LEN_MUTEX 15 +#define TRC_CFG_NAME_LEN_TIMER 15 +#define TRC_CFG_NAME_LEN_EVENTGROUP 15 +#define TRC_CFG_NAME_LEN_STREAMBUFFER 15 +#define TRC_CFG_NAME_LEN_MESSAGEBUFFER 15 + +/****************************************************************************** + *** ADVANCED SETTINGS ******************************************************** + ****************************************************************************** + * The remaining settings are not necessary to modify but allows for optimizing + * the recorder setup for your specific needs, e.g., to exclude events that you + * are not interested in, in order to get longer traces. + *****************************************************************************/ + +/****************************************************************************** +* TRC_CFG_HEAP_SIZE_BELOW_16M +* +* An integer constant that can be used to reduce the buffer usage of memory +* allocation events (malloc/free). This value should be 1 if the heap size is +* below 16 MB (2^24 byte), and you can live with reported addresses showing the +* lower 24 bits only. If 0, you get the full 32-bit addresses. +* +* Default value is 0. +******************************************************************************/ +#define TRC_CFG_HEAP_SIZE_BELOW_16M 0 + +/****************************************************************************** + * TRC_CFG_USE_IMPLICIT_IFE_RULES + * + * Macro which should be defined as either zero (0) or one (1). + * Default is 1. + * + * Tracealyzer groups the events into "instances" based on Instance Finish + * Events (IFEs), produced either by default rules or calls to the recorder + * functions vTraceInstanceFinishedNow and vTraceInstanceFinishedNext. + * + * If TRC_CFG_USE_IMPLICIT_IFE_RULES is one (1), the default IFE rules is + * used, resulting in a "typical" grouping of events into instances. + * If these rules don't give appropriate instances in your case, you can + * override the default rules using vTraceInstanceFinishedNow/Next for one + * or several tasks. The default IFE rules are then disabled for those tasks. + * + * If TRC_CFG_USE_IMPLICIT_IFE_RULES is zero (0), the implicit IFE rules are + * disabled globally. You must then call vTraceInstanceFinishedNow or + * vTraceInstanceFinishedNext to manually group the events into instances, + * otherwise the tasks will appear a single long instance. + * + * The default IFE rules count the following events as "instance finished": + * - Task delay, delay until + * - Task suspend + * - Blocking on "input" operations, i.e., when the task is waiting for the + * next a message/signal/event. But only if this event is blocking. + * + * For details, see trcSnapshotKernelPort.h and look for references to the + * macro trcKERNEL_HOOKS_SET_TASK_INSTANCE_FINISHED. + *****************************************************************************/ +#define TRC_CFG_USE_IMPLICIT_IFE_RULES 1 + +/****************************************************************************** + * TRC_CFG_USE_16BIT_OBJECT_HANDLES + * + * Macro which should be defined as either zero (0) or one (1). + * + * If set to 0 (zero), the recorder uses 8-bit handles to identify kernel + * objects such as tasks and queues. This limits the supported number of + * concurrently active objects to 255 of each type (tasks, queues, mutexes, + * etc.) Note: 255, not 256, since handle 0 is reserved. + * + * If set to 1 (one), the recorder uses 16-bit handles to identify kernel + * objects such as tasks and queues. This limits the supported number of + * concurrent objects to 65535 of each type (object class). However, since the + * object property table is limited to 64 KB, the practical limit is about + * 3000 objects in total. + * + * Default is 0 (8-bit handles) + * + * NOTE: An object with handle above 255 will use an extra 4-byte record in + * the event buffer whenever the object is referenced. Moreover, some internal + * tables in the recorder gets slightly larger when using 16-bit handles. + *****************************************************************************/ +#define TRC_CFG_USE_16BIT_OBJECT_HANDLES 0 + +/****************************************************************************** + * TRC_CFG_USE_TRACE_ASSERT + * + * Macro which should be defined as either zero (0) or one (1). + * Default is 1. + * + * If this is one (1), the TRACE_ASSERT macro (used at various locations in the + * trace recorder) will verify that a relevant condition is true. + * If the condition is false, prvTraceError() will be called, which stops the + * recording and stores an error message that is displayed when opening the + * trace in Tracealyzer. + * + * This is used on several places in the recorder code for sanity checks on + * parameters. Can be switched off to reduce the footprint of the tracing, but + * we recommend to have it enabled initially. + *****************************************************************************/ +#define TRC_CFG_USE_TRACE_ASSERT 1 + +/******************************************************************************* + * TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER + * + * Macro which should be defined as an integer value. + * + * Set TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER to 1 to enable the + * separate user event buffer (UB). + * In this mode, user events are stored separately from other events, + * e.g., RTOS events. Thereby you can get a much longer history of + * user events as they don't need to share the buffer space with more + * frequent events. + * + * The UB is typically used with the snapshot ring-buffer mode, so the + * recording can continue when the main buffer gets full. And since the + * main buffer then overwrites the earliest events, Tracealyzer displays + * "Unknown Actor" instead of task scheduling for periods with UB data only. + * + * In UB mode, user events are structured as UB channels, which contains + * a channel name and a default format string. Register a UB channel using + * xTraceRegisterUBChannel. + * + * Events and data arguments are written using vTraceUBEvent and + * vTraceUBData. They are designed to provide efficient logging of + * repeating events, using the same format string within each channel. + * + * Examples: + * + * traceString chn1 = xTraceRegisterString("Channel 1"); + * traceString fmt1 = xTraceRegisterString("Event!"); + * traceUBChannel UBCh1 = xTraceRegisterUBChannel(chn1, fmt1); + * + * traceString chn2 = xTraceRegisterString("Channel 2"); + * traceString fmt2 = xTraceRegisterString("X: %d, Y: %d"); + * traceUBChannel UBCh2 = xTraceRegisterUBChannel(chn2, fmt2); + * + * // Result in "[Channel 1] Event!" + * vTraceUBEvent(UBCh1); + * + * // Result in "[Channel 2] X: 23, Y: 19" + * vTraceUBData(UBCh2, 23, 19); + * + * You can also use the other user event functions, like vTracePrintF. + * as they are then rerouted to the UB instead of the main event buffer. + * vTracePrintF then looks up the correct UB channel based on the + * provided channel name and format string, or creates a new UB channel + * if no match is found. The format string should therefore not contain + * "random" messages but mainly format specifiers. Random strings should + * be stored using %s and with the string as an argument. + * + * // Creates a new UB channel ("Channel 2", "%Z: %d") + * vTracePrintF(chn2, "%Z: %d", value1); + * + * // Finds the existing UB channel + * vTracePrintF(chn2, "%Z: %d", value2); + + ******************************************************************************/ +#define TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER 0 + +/******************************************************************************* + * TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE + * + * Macro which should be defined as an integer value. + * + * This defines the capacity of the user event buffer (UB), in number of slots. + * A single user event can use multiple slots, depending on the arguments. + * + * Only applicable if TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER is 1. + ******************************************************************************/ +#define TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE 200 + +/******************************************************************************* + * TRC_CFG_UB_CHANNELS + * + * Macro which should be defined as an integer value. + * + * This defines the number of User Event Buffer Channels (UB channels). + * These are used to structure the events when using the separate user + * event buffer, and contains both a User Event Channel (the name) and + * a default format string for the channel. + * + * Only applicable if TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER is 1. + ******************************************************************************/ +#define TRC_CFG_UB_CHANNELS 32 + +/******************************************************************************* + * TRC_CFG_ISR_TAILCHAINING_THRESHOLD + * + * Macro which should be defined as an integer value. + * + * If tracing multiple ISRs, this setting allows for accurate display of the + * context-switching also in cases when the ISRs execute in direct sequence. + * + * vTraceStoreISREnd normally assumes that the ISR returns to the previous + * context, i.e., a task or a preempted ISR. But if another traced ISR + * executes in direct sequence, Tracealyzer may incorrectly display a minimal + * fragment of the previous context in between the ISRs. + * + * By using TRC_CFG_ISR_TAILCHAINING_THRESHOLD you can avoid this. This is + * however a threshold value that must be measured for your specific setup. + * See http://percepio.com/2014/03/21/isr_tailchaining_threshold/ + * + * The default setting is 0, meaning "disabled" and that you may get an + * extra fragments of the previous context in between tail-chained ISRs. + * + * Note: This setting has separate definitions in trcSnapshotConfig.h and + * trcStreamingConfig.h, since it is affected by the recorder mode. + ******************************************************************************/ +#define TRC_CFG_ISR_TAILCHAINING_THRESHOLD 0 + +#endif /*TRC_SNAPSHOT_CONFIG_H*/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/config/trcStreamingConfig.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/config/trcStreamingConfig.h new file mode 100644 index 0000000..f578f10 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/config/trcStreamingConfig.h @@ -0,0 +1,170 @@ +/******************************************************************************* + * Trace Recorder Library for Tracealyzer v4.1.4 + * Percepio AB, www.percepio.com + * + * trcStreamingConfig.h + * + * Configuration parameters for the trace recorder library in streaming mode. + * Read more at http://percepio.com/2016/10/05/rtos-tracing/ + * + * Terms of Use + * This file is part of the trace recorder library (RECORDER), which is the + * intellectual property of Percepio AB (PERCEPIO) and provided under a + * license as follows. + * The RECORDER may be used free of charge for the purpose of recording data + * intended for analysis in PERCEPIO products. It may not be used or modified + * for other purposes without explicit permission from PERCEPIO. + * You may distribute the RECORDER in its original source code form, assuming + * this text (terms of use, disclaimer, copyright notice) is unchanged. You are + * allowed to distribute the RECORDER with minor modifications intended for + * configuration or porting of the RECORDER, e.g., to allow using it on a + * specific processor, processor family or with a specific communication + * interface. Any such modifications should be documented directly below + * this comment block. + * + * Disclaimer + * The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty + * as to its use or performance. PERCEPIO does not and cannot warrant the + * performance or results you may obtain by using the RECORDER or documentation. + * PERCEPIO make no warranties, express or implied, as to noninfringement of + * third party rights, merchantability, or fitness for any particular purpose. + * In no event will PERCEPIO, its technology partners, or distributors be liable + * to you for any consequential, incidental or special damages, including any + * lost profits or lost savings, even if a representative of PERCEPIO has been + * advised of the possibility of such damages, or for any claim by any third + * party. Some jurisdictions do not allow the exclusion or limitation of + * incidental, consequential or special damages, or the exclusion of implied + * warranties or limitations on how long an implied warranty may last, so the + * above limitations may not apply to you. + * + * Tabs are used for indent in this file (1 tab = 4 spaces) + * + * Copyright Percepio AB, 2018. + * www.percepio.com + ******************************************************************************/ + +#ifndef TRC_STREAMING_CONFIG_H +#define TRC_STREAMING_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Configuration Macro: TRC_CFG_SYMBOL_TABLE_SLOTS + * + * The maximum number of symbols names that can be stored. This includes: + * - Task names + * - Named ISRs (vTraceSetISRProperties) + * - Named kernel objects (vTraceStoreKernelObjectName) + * - User event channels (xTraceRegisterString) + * + * If this value is too small, not all symbol names will be stored and the + * trace display will be affected. In that case, there will be warnings + * (as User Events) from TzCtrl task, that monitors this. + ******************************************************************************/ +#define TRC_CFG_SYMBOL_TABLE_SLOTS 40 + +/******************************************************************************* + * Configuration Macro: TRC_CFG_SYMBOL_MAX_LENGTH + * + * The maximum length of symbol names, including: + * - Task names + * - Named ISRs (vTraceSetISRProperties) + * - Named kernel objects (vTraceStoreKernelObjectName) + * - User event channel names (xTraceRegisterString) + * + * If longer symbol names are used, they will be truncated by the recorder, + * which will affect the trace display. In that case, there will be warnings + * (as User Events) from TzCtrl task, that monitors this. + ******************************************************************************/ +#define TRC_CFG_SYMBOL_MAX_LENGTH 25 + +/******************************************************************************* + * Configuration Macro: TRC_CFG_OBJECT_DATA_SLOTS + * + * The maximum number of object data entries (used for task priorities) that can + * be stored at the same time. Must be sufficient for all tasks, otherwise there + * will be warnings (as User Events) from TzCtrl task, that monitors this. + ******************************************************************************/ +#define TRC_CFG_OBJECT_DATA_SLOTS 40 + +/******************************************************************************* + * Configuration Macro: TRC_CFG_CTRL_TASK_STACK_SIZE + * + * The stack size of the TzCtrl task, that receive commands. + * We are aiming to remove this extra task in future versions. + ******************************************************************************/ +#define TRC_CFG_CTRL_TASK_STACK_SIZE (configMINIMAL_STACK_SIZE * 2) + +/******************************************************************************* + * Configuration Macro: TRC_CFG_CTRL_TASK_PRIORITY + * + * The priority of the TzCtrl task, that receive commands from Tracealyzer. + * Most stream ports also rely on the TzCtrl task to transmit the data from the + * internal buffer to the stream interface (all except for the J-Link port). + * For such ports, make sure the TzCtrl priority is high enough to ensure + * reliable periodic execution and transfer of the data. + ******************************************************************************/ +#define TRC_CFG_CTRL_TASK_PRIORITY 1 + +/******************************************************************************* + * Configuration Macro: TRC_CFG_CTRL_TASK_DELAY + * + * The delay between every loop of the TzCtrl task. A high delay will reduce the + * CPU load, but may cause missed events if the TzCtrl task is performing the + * trace transfer. + ******************************************************************************/ +#define TRC_CFG_CTRL_TASK_DELAY ((10 * configTICK_RATE_HZ) / 1000) + +/******************************************************************************* + * Configuration Macro: TRC_CFG_PAGED_EVENT_BUFFER_PAGE_COUNT + * + * Specifies the number of pages used by the paged event buffer. + * This may need to be increased if there are a lot of missed events. + * + * Note: not used by the J-Link RTT stream port (see trcStreamingPort.h instead) + ******************************************************************************/ +#define TRC_CFG_PAGED_EVENT_BUFFER_PAGE_COUNT 2 + +/******************************************************************************* + * Configuration Macro: TRC_CFG_PAGED_EVENT_BUFFER_PAGE_SIZE + * + * Specifies the size of each page in the paged event buffer. This can be tuned + * to match any internal low-level buffers used by the streaming interface, like + * the Ethernet MTU (Maximum Transmission Unit). + * + * Note: not used by the J-Link RTT stream port (see trcStreamingPort.h instead) + ******************************************************************************/ +#define TRC_CFG_PAGED_EVENT_BUFFER_PAGE_SIZE 2500 + +/******************************************************************************* + * TRC_CFG_ISR_TAILCHAINING_THRESHOLD + * + * Macro which should be defined as an integer value. + * + * If tracing multiple ISRs, this setting allows for accurate display of the + * context-switching also in cases when the ISRs execute in direct sequence. + * + * vTraceStoreISREnd normally assumes that the ISR returns to the previous + * context, i.e., a task or a preempted ISR. But if another traced ISR + * executes in direct sequence, Tracealyzer may incorrectly display a minimal + * fragment of the previous context in between the ISRs. + * + * By using TRC_CFG_ISR_TAILCHAINING_THRESHOLD you can avoid this. This is + * however a threshold value that must be measured for your specific setup. + * See http://percepio.com/2014/03/21/isr_tailchaining_threshold/ + * + * The default setting is 0, meaning "disabled" and that you may get an + * extra fragments of the previous context in between tail-chained ISRs. + * + * Note: This setting has separate definitions in trcSnapshotConfig.h and + * trcStreamingConfig.h, since it is affected by the recorder mode. + ******************************************************************************/ +#define TRC_CFG_ISR_TAILCHAINING_THRESHOLD 0 + +#ifdef __cplusplus +} +#endif + +#endif /* TRC_STREAMING_CONFIG_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/readme.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/readme.txt new file mode 100644 index 0000000..79b6400 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/readme.txt @@ -0,0 +1,152 @@ +------------------------------------------------------------------------------- + Tracealyzer for FreeRTOS - Trace Recorder Library v3.1.1 +------------------------------------------------------------------------------- + +Tracealyzer for FreeRTOS is a sophisticated tool for tracing and visualization +of FreeRTOS-based systems. Tracealyzer gives an unprecedented insight into the +runtime behavior, which speeds up debugging, validation and optimization. + +To learn more about this, see + + - Getting Started (videos etc): http://percepio.com/gettingstarted/tz-freertos/ + + - User Manual (incl. Recorder API): http://percepio.com/docs/FreeRTOS/manual + + - FAQ: http://percepio.com/category/faq/ + +In case you have any questions, don't hesitate to contact support@percepio.com + +------------------------------------------------------------------------------- + +Changes, v3.1.1 -> v3.1.2 + +- Fixed two bugs related to User Events, one in vTracePrintF and other in vTracePrint. + +- Fixed a build problem related to a single reference of the old FreeRTOS type "xTaskHandle", in trcKernelPort.c. + Changed to "TaskHandle_t", unless if using an older FreeRTOS kernel or the "compatibility mode". + +- Removed traceCREATE_MUTEX hook for FreeRTOS v9 or later (no longer required) + +- Updated the User Manual regarding snapshot trace via IAR Embedded Workbench. + +- Renamed vTraceGetTraceBuffer to xTraceGetTraceBuffer, since returning a pointer. + +------------------------------------------------------------------------------- + +Changes, v3.1.0 -> v3.1.1 + +After the major changes in the v3.1.0 trace recorder library, this update +corrects a number of minor issues. Only minor functional improvements. + +- You can now use TRC_ALLOC_CUSTOM_BUFFER to declare a trace buffer on a custom + location (using linker directives). + The related function vTraceSetRecorderDataBuffer has been promoted to the + Common API (previously only supported in snapshot mode, but custom allocation + is now generally supported also in streaming mode). + +- Removed TRC_CFG_USE_LINKER_PRAGMA. No longer necessary thanks to the custom + allocation mode. + +- Added support for timestamping from custom periodic timers, required for + accurate timestamping on Cortex-M0/M0+ devices when using tickless idle. + Only for streaming mode so far. See TRC_CUSTOM_TIMER_INCR / DECR. + +- ARM Cortex-M port: Made sure the DWT unit is initialized properly, in case + the debugger doesn't handle this. + +- ARM Cortex-M port: Added possibility to use Systick timestamping also on + Cortex-M3/M4/M7 devices (that otherwise use DWT timestamping by default). + To use this option, define the macro TRC_CFG_ARM_CM_USE_SYSTICK. + +- J-Link streaming: The default RTT buffer has been changed from 0 to 1. + +- J-Link streaming: The RTT buffer settings for buffer 1 and higher, are now + found in trcStreamingPort.h. Note: These settings don't apply to buffer 0. + +- vTracePrint has been optimized for better performance in string logging. + +- Minor performance improvement related to symbol table transfer in streaming mode. + +- Timer names now registered also in streaming mode. + +- Timer start and stop event are now traced. + +- Implemented support for queue registry (traceQUEUE_REGISTRY_ADD) also for streaming. + +- Fixed a bug related to repeated calls of vTraceEnable. + +- Fixed a bug where task-switches seemed to occur even though the scheduler was disabled. + +- Renamed HARDWARE_PORT_TEXAS_INSTRUMENTS_TMS570_RM48, added prefix TRC. + +- Fixed several language issues in the comments and documentation. + +- Fixed several minor issues and warnings from different compilers + (including PowerPC/gcc) and configurations. + +------------------------------------------------------------------------------- + +Changes, v3.0.9 -> v3.1.0 + +- Merge of previously separated snapshot and streaming recorders into a single + recorder supporting both streaming and snapshot as different modes. + +- New common API for supporting both streaming and snapshot modes. + +- New integration guide, see the User Manual. + +- Major improvement of API documentation in source files and User Manual. + +- New concept of "stream ports", giving a better structure defining streaming + interfaces, and restructured the J-Link and TCP/IP streaming as stream ports. + +- Added a stream port for USB CDC connections, with STM32 as example. + Since Tracealyzer now can receive serial data on Windows COM ports, this is + really easy to use. + +- Added a warning (#error) for cases where FreeRTOS tickless idle mode is used + together with timestamping using SysTick or other periodic interrupt timers, + Tracing with tickless idle requires an independent time source to correctly + capture the length of the idle periods. + +- Major changes in the recorder API. Important examples are: + + * Some configuration macros have changed names, e.g. for "hardware port". + Make sure to remove any old "trcConfig.h" files if upgrading from an + earlier version! + + * Recorder configuration in trcConfig.h has been minimized and now only + includes the important settings that are independent of recorder mode. + Advanced settings for each mode are found in trcSnapshotConfig.h and + trcStreamingConfig.h. + + * vTraceEnable replaces Trace_Init and vTraceInitTraceData, as well as + vTraceStart and uiTraceStart. + + * vTraceStop now part of the common API and thereby available also in + streaming. And since vTraceEnable can start the streaming directly + you have the option control the tracing from target, e.g., for + streaming to a device file system. + + * vTraceStoreKernelObjectName from old streaming recorder has been replaced + by vTraceSetQueueName, vTraceSetSemaphoreName, etc. + + * vTraceSetISRProperties now returns a "traceHandle" that should be passed as + parameter to vTraceStoreISRBegin and vTraceStoreISREnd. + + * xTraceRegisterString has replaced the old functions xTraceOpenLabel and + vTraceStoreUserEventChannelName. This now returns a "traceString" for use + as "channel" parameter in vTracePrintF, and in other places where strings + are stored. + + * Removed vTraceStoreISREndManual and vTraceStoreISREndAuto, use + vTraceStoreISREnd instead. + + * Renamed the functions for saving User Events in a separate buffer: + - xTraceRegisterChannelFormat -> xTraceRegisterUBChannel + - vTraceChannelPrintF -> vTraceUBData + - vTraceChannelUserEvent -> vTraceUBEvent + + +------------------------------------------------------------------------------- +Copyright Percepio AB, 2017. \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/ARM_ITM/Keil-uVision-Tracealyzer-ITM-Exporter.ini b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/ARM_ITM/Keil-uVision-Tracealyzer-ITM-Exporter.ini new file mode 100644 index 0000000..5e2c8b9 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/ARM_ITM/Keil-uVision-Tracealyzer-ITM-Exporter.ini @@ -0,0 +1,52 @@ +/************************************************************ +* Percepio Tracealyzer - ITM Trace Exporter for Keil uVision +* Copyright (c) 2018, Percepio AB. +* https://percepio.com +************************************************************/ + +FUNC void tzSetEnable(int enable) +{ + if (enable == 1) + { + printf("Starting Tracealyzer recorder\n"); + + // Forward the ITM data to file + exec("ITMLOG 1 > .\\tracealyzer.psf"); + + // Send start command to Tracealyzer (not required if using vTraceEnable(TRC_START)) + exec("E CHAR tz_host_command_data = 1, 1, 0, 0, 0, 0, 0xFD, 0xFF"); + exec("tz_host_command_bytes_to_read = 8"); + } + else if (enable == 0) + { + printf("Stopping Tracealyzer recorder...\n"); + + // Send stop command to Tracealyzer, to stop writing ITM data. + exec("E CHAR tz_host_command_data = 1, 0, 0, 0, 0, 0, 0xFE, 0xFF"); + exec("tz_host_command_bytes_to_read = 8"); + + _sleep_(2000); // Wait a while to let all data be written the host file. + + // Stop forwarding the ITM data to file and close the file. + exec("ITMLOG 1 OFF"); + + printf("Tracealyzer recorder stopped.\n"); + + } + else printf("Usage: tzSetEnable(0 or 1), where 0 is disable (stops recorder) and 1 enable (starts recording)"); + +} + + +// The Tracealyzer ITM stream port for Keil µVision can be used in two ways. +// +// 1. Start tracing directly from startup. +// Make sure tzSetEnable(1) is called below and vTraceEnable(TRC_START) in your target startup. +// +// 2. Start the trace manually, using the "Start Recording" button in Keil µVision. +// In this case, comment out the below call to tzSetEnable and make sure you call vTraceEnable(TRC_INIT) in your target startup (not TRC_START). + +tzSetEnable(1); + +DEFINE BUTTON "Start Recording", "tzSetEnable(1)"; +DEFINE BUTTON "Stop Recording", "tzSetEnable(0)"; \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/ARM_ITM/Readme-ARM_ITM.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/ARM_ITM/Readme-ARM_ITM.txt new file mode 100644 index 0000000..0802b53 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/ARM_ITM/Readme-ARM_ITM.txt @@ -0,0 +1,28 @@ +Tracealyzer Stream Port for ARM Cortex-M ITM +-------------------------------------------- +2018-05-04 + +This directory contains a "stream port" for the Tracealyzer recorder library, +i.e., the specific code needed to use a particular interface for streaming a +Tracealyzer RTOS trace. The stream port is defined by a set of macros in +trcStreamingPort.h, found in the "include" directory. + +This particular stream port targets ARM's ITM interface, which together with +a fast debug probe such as a Keil ULINKpro or ULINKplus provides excellent +performance. This stream port does not use any RAM buffer for the trace, but +writes the data directly to the ITM registers. This is very fast. + +To setup Keil uVision for ITM tracing with a Keil ULINKpro (or ULINKplus), +see Percepio Application Note PA-021 https://percepio.com/2018/05/04/keil-itm-support/ + +Learning more: + - Tracealyzer User Manual (Help -> User Manual) + - https://percepio.com/gettingstarted + - Percepio Application Note PA-021 https://percepio.com/2018/05/04/keil-itm-support/ + - About ITM trace, https://percepio.com/2016/06/09/arm-itm/ + - About the recorder and custom streaming, http://percepio.com/2016/10/05/rtos-tracing + +For questions, please contact support@percepio.com + +Percepio AB +www.percepio.com \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/ARM_ITM/include/trcStreamingPort.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/ARM_ITM/include/trcStreamingPort.h new file mode 100644 index 0000000..ca20ae7 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/ARM_ITM/include/trcStreamingPort.h @@ -0,0 +1,91 @@ +/******************************************************************************* + * Trace Recorder Library for Tracealyzer v4.1.5 + * Percepio AB, www.percepio.com + * + * trcStreamingPort.h + * + * The interface definitions for trace streaming ("stream ports"). + * This "stream port" sets up the recorder to use ARM ITM as streaming channel. + * + * Terms of Use + * This file is part of the trace recorder library (RECORDER), which is the + * intellectual property of Percepio AB (PERCEPIO) and provided under a + * license as follows. + * The RECORDER may be used free of charge for the purpose of recording data + * intended for analysis in PERCEPIO products. It may not be used or modified + * for other purposes without explicit permission from PERCEPIO. + * You may distribute the RECORDER in its original source code form, assuming + * this text (terms of use, disclaimer, copyright notice) is unchanged. You are + * allowed to distribute the RECORDER with minor modifications intended for + * configuration or porting of the RECORDER, e.g., to allow using it on a + * specific processor, processor family or with a specific communication + * interface. Any such modifications should be documented directly below + * this comment block. + * + * Disclaimer + * The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty + * as to its use or performance. PERCEPIO does not and cannot warrant the + * performance or results you may obtain by using the RECORDER or documentation. + * PERCEPIO make no warranties, express or implied, as to noninfringement of + * third party rights, merchantability, or fitness for any particular purpose. + * In no event will PERCEPIO, its technology partners, or distributors be liable + * to you for any consequential, incidental or special damages, including any + * lost profits or lost savings, even if a representative of PERCEPIO has been + * advised of the possibility of such damages, or for any claim by any third + * party. Some jurisdictions do not allow the exclusion or limitation of + * incidental, consequential or special damages, or the exclusion of implied + * warranties or limitations on how long an implied warranty may last, so the + * above limitations may not apply to you. + * + * Tabs are used for indent in this file (1 tab = 4 spaces) + * + * Copyright Percepio AB, 2018. + * www.percepio.com + ******************************************************************************/ + +#ifndef TRC_STREAMING_PORT_H +#define TRC_STREAMING_PORT_H + +#ifdef __cplusplus +extern "C" { +#endif + + +int32_t itm_write(void* ptrData, uint32_t size, int32_t* ptrBytesWritten); +int32_t read_from_host(void* ptrData, uint32_t size, int32_t* ptrBytesRead); + +/******************************************************************************* + * TRC_CFG_ITM_PORT + * + * Possible values: 0 - 31 + * + * What ITM port to use for the ITM software events. Make sure the IDE is + * configured for the same channel. + * + * Default: 1 (0 is typically terminal output and 31 is used by Keil) + * + ******************************************************************************/ +#define TRC_CFG_ITM_PORT 1 + +#if (TRC_CFG_ITM_PORT < 0) || (TRC_CFG_ITM_PORT > 31) +#error "Bad ITM port selected." +#endif + +// Not used for ITM - no RAM buffer... +#define TRC_STREAM_PORT_ALLOCATE_FIELDS() + +// Not used for ITM - assume the IDE configures the ITM setup +#define TRC_STREAM_PORT_INIT() + +/* Important for the ITM port - no RAM buffer, direct writes. In most other ports this can be skipped (default is 1) */ +#define TRC_STREAM_PORT_USE_INTERNAL_BUFFER 0 + +#define TRC_STREAM_PORT_WRITE_DATA(_ptrData, _size, _ptrBytesWritten) itm_write(_ptrData, _size, _ptrBytesWritten) + +#define TRC_STREAM_PORT_READ_DATA(_ptrData, _size, _ptrBytesRead) read_from_host(_ptrData, _size, _ptrBytesRead) + +#ifdef __cplusplus +} +#endif + +#endif /* TRC_STREAMING_PORT_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/ARM_ITM/trcStreamingPort.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/ARM_ITM/trcStreamingPort.c new file mode 100644 index 0000000..0d36b4a --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/ARM_ITM/trcStreamingPort.c @@ -0,0 +1,71 @@ + +#include "trcRecorder.h" + +#if (TRC_USE_TRACEALYZER_RECORDER == 1) +#if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING) + +static void itm_write_32(uint32_t data); + +volatile int32_t tz_host_command_bytes_to_read = 0; // This is set by the Tracealyzer host application (to the number of bytes written), after having written to tz_host_commands. Set to zero by the read function after the message in tz_host_commands has been read. +volatile char tz_host_command_data[32]; + +/* This reads "command" data from a RAM buffer, written by a host macro in the debugger */ +int32_t read_from_host(void* ptrData, uint32_t size, int32_t* ptrBytesRead) +{ + if ( tz_host_command_bytes_to_read > 0) + { + int i; + uint8_t * bytesBuffer = (uint8_t*) ptrData; + + if (ptrBytesRead != NULL) + *ptrBytesRead = (int32_t)tz_host_command_bytes_to_read; + + if (tz_host_command_bytes_to_read != size) + { + return -1; + } + + for (i=0; i < tz_host_command_bytes_to_read; i++) + { + bytesBuffer[i] = tz_host_command_data[i]; + } + + tz_host_command_bytes_to_read = 0; + } + + return 0; +} + +static void itm_write_32(uint32_t data) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && // Trace enabled + (ITM->TCR & ITM_TCR_ITMENA_Msk) && // ITM enabled + (ITM->TER & (1UL << TRC_CFG_ITM_PORT))) // ITM port enabled + { + while (ITM->PORT[TRC_CFG_ITM_PORT].u32 == 0); // Block until room in ITM FIFO - This stream port is always in "blocking mode", since intended for high-speed ITM! + ITM->PORT[TRC_CFG_ITM_PORT].u32 = data; // Write the data + } +} + +/* This is assumed to execute from within the recorder, with interrupts disabled */ +int32_t itm_write(void* ptrData, uint32_t size, int32_t* ptrBytesWritten) +{ + uint32_t bytesWritten = 0; + uint32_t* ptr32 = (uint32_t*)ptrData; + + if (size % 4 != 0) return -2; + + while(bytesWritten < size) + { + itm_write_32(*ptr32); + ptr32++; + bytesWritten += 4; + } + + *ptrBytesWritten = bytesWritten; + + return 0; +} + +#endif +#endif diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/File/Readme-Streamport.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/File/Readme-Streamport.txt new file mode 100644 index 0000000..afc5a09 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/File/Readme-Streamport.txt @@ -0,0 +1,19 @@ +Tracealyzer Stream Port for Files +------------------------------------------------- + +This directory contains a "stream port" for the Tracealyzer recorder library, +i.e., the specific code needed to use a particular interface for streaming a +Tracealyzer RTOS trace. The stream port is defined by a set of macros in +trcStreamingPort.h, found in the "include" directory. + +This particular stream port is for streaming to a file via stdio.h (fwrite). + +To use this stream port, make sure that include/trcStreamingPort.h is found +by the compiler (i.e., add this folder to your project's include paths) and +add all included source files to your build. Make sure no other versions of +trcStreamingPort.h are included by mistake! + +See also http://percepio.com/2016/10/05/rtos-tracing. + +Percepio AB +www.percepio.com \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/File/include/trcStreamingPort.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/File/include/trcStreamingPort.h new file mode 100644 index 0000000..2897b7c --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/File/include/trcStreamingPort.h @@ -0,0 +1,87 @@ +/******************************************************************************* + * Trace Recorder Library for Tracealyzer v4.1.5 + * Percepio AB, www.percepio.com + * + * trcStreamingPort.h + * + * The interface definitions for trace streaming ("stream ports"). + * This "stream port" sets up the recorder to stream the trace to file. + * + * Terms of Use + * This file is part of the trace recorder library (RECORDER), which is the + * intellectual property of Percepio AB (PERCEPIO) and provided under a + * license as follows. + * The RECORDER may be used free of charge for the purpose of recording data + * intended for analysis in PERCEPIO products. It may not be used or modified + * for other purposes without explicit permission from PERCEPIO. + * You may distribute the RECORDER in its original source code form, assuming + * this text (terms of use, disclaimer, copyright notice) is unchanged. You are + * allowed to distribute the RECORDER with minor modifications intended for + * configuration or porting of the RECORDER, e.g., to allow using it on a + * specific processor, processor family or with a specific communication + * interface. Any such modifications should be documented directly below + * this comment block. + * + * Disclaimer + * The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty + * as to its use or performance. PERCEPIO does not and cannot warrant the + * performance or results you may obtain by using the RECORDER or documentation. + * PERCEPIO make no warranties, express or implied, as to noninfringement of + * third party rights, merchantability, or fitness for any particular purpose. + * In no event will PERCEPIO, its technology partners, or distributors be liable + * to you for any consequential, incidental or special damages, including any + * lost profits or lost savings, even if a representative of PERCEPIO has been + * advised of the possibility of such damages, or for any claim by any third + * party. Some jurisdictions do not allow the exclusion or limitation of + * incidental, consequential or special damages, or the exclusion of implied + * warranties or limitations on how long an implied warranty may last, so the + * above limitations may not apply to you. + * + * Tabs are used for indent in this file (1 tab = 4 spaces) + * + * Copyright Percepio AB, 2018. + * www.percepio.com + ******************************************************************************/ + +#ifndef TRC_STREAMING_PORT_H +#define TRC_STREAMING_PORT_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int32_t writeToFile(void* data, uint32_t size, int32_t *ptrBytesWritten); + +void closeFile(void); + +void openFile(char* fileName); + +/* This define will determine whether to use the internal PagedEventBuffer or not. +If file writing creates additional trace events (i.e. it uses semaphores or mutexes), +then the paged event buffer must be enabled to avoid infinite recursion. */ +#define TRC_STREAM_PORT_USE_INTERNAL_BUFFER 1 + +#define TRC_STREAM_PORT_READ_DATA(_ptrData, _size, _ptrBytesRead) 0 /* Does not read commands from Tz (yet) */ + +#define TRC_STREAM_PORT_WRITE_DATA(_ptrData, _size, _ptrBytesSent) writeToFile(_ptrData, _size, _ptrBytesSent) + +#if (TRC_CFG_RECORDER_BUFFER_ALLOCATION == TRC_RECORDER_BUFFER_ALLOCATION_DYNAMIC) +#define TRC_STREAM_PORT_MALLOC() \ + _TzTraceData = TRC_PORT_MALLOC((TRC_CFG_PAGED_EVENT_BUFFER_PAGE_COUNT) * (TRC_CFG_PAGED_EVENT_BUFFER_PAGE_SIZE)); +extern char* _TzTraceData; +#else +#define TRC_STREAM_PORT_MALLOC() /* Custom or static allocation. Not used. */ +#endif +#define TRC_STREAM_PORT_INIT() \ + TRC_STREAM_PORT_MALLOC(); \ + openFile("trace.psf") + +#define TRC_STREAM_PORT_ON_TRACE_END() closeFile() + +#ifdef __cplusplus +} +#endif + +#endif /* TRC_STREAMING_PORT_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/File/trcStreamingPort.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/File/trcStreamingPort.c new file mode 100644 index 0000000..a019791 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/File/trcStreamingPort.c @@ -0,0 +1,103 @@ +/******************************************************************************* + * Trace Recorder Library for Tracealyzer v4.1.5 + * Percepio AB, www.percepio.com + * + * trcStreamingPort.c + * + * Supporting functions for trace streaming, used by the "stream ports" + * for reading and writing data to the interface. + * Existing ports can easily be modified to fit another setup, e.g., a + * different TCP/IP stack, or to define your own stream port. + * + * Terms of Use + * This file is part of the trace recorder library (RECORDER), which is the + * intellectual property of Percepio AB (PERCEPIO) and provided under a + * license as follows. + * The RECORDER may be used free of charge for the purpose of recording data + * intended for analysis in PERCEPIO products. It may not be used or modified + * for other purposes without explicit permission from PERCEPIO. + * You may distribute the RECORDER in its original source code form, assuming + * this text (terms of use, disclaimer, copyright notice) is unchanged. You are + * allowed to distribute the RECORDER with minor modifications intended for + * configuration or porting of the RECORDER, e.g., to allow using it on a + * specific processor, processor family or with a specific communication + * interface. Any such modifications should be documented directly below + * this comment block. + * + * Disclaimer + * The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty + * as to its use or performance. PERCEPIO does not and cannot warrant the + * performance or results you may obtain by using the RECORDER or documentation. + * PERCEPIO make no warranties, express or implied, as to noninfringement of + * third party rights, merchantability, or fitness for any particular purpose. + * In no event will PERCEPIO, its technology partners, or distributors be liable + * to you for any consequential, incidental or special damages, including any + * lost profits or lost savings, even if a representative of PERCEPIO has been + * advised of the possibility of such damages, or for any claim by any third + * party. Some jurisdictions do not allow the exclusion or limitation of + * incidental, consequential or special damages, or the exclusion of implied + * warranties or limitations on how long an implied warranty may last, so the + * above limitations may not apply to you. + * + * Tabs are used for indent in this file (1 tab = 4 spaces) + * + * Copyright Percepio AB, 2018. + * www.percepio.com + ******************************************************************************/ + +#include "trcRecorder.h" + +#if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING) +#if (TRC_USE_TRACEALYZER_RECORDER == 1) + +FILE* traceFile = NULL; + +void openFile(char* fileName) +{ + if (traceFile == NULL) + { + errno_t err = fopen_s(&traceFile, fileName, "wb"); + if (err != 0) + { + printf("Could not open trace file, error code %d.\n", err); + exit(-1); + } + else { + printf("Trace file created.\n"); + } + } +} + +int32_t writeToFile(void* data, uint32_t size, int32_t *ptrBytesWritten) +{ + int32_t written = 0; + if (traceFile != NULL) + { + written = fwrite(data, 1, size, traceFile); + } + else + { + written = 0; + } + + if (ptrBytesWritten != 0) + *ptrBytesWritten = written; + + if ((int32_t)size == written) + return 0; + else + return -1; +} + +void closeFile(void) +{ + if (traceFile != NULL) + { + fclose(traceFile); + traceFile = NULL; + printf("Trace file closed.\n"); + } +} + +#endif /*(TRC_USE_TRACEALYZER_RECORDER == 1)*/ +#endif /*(TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING)*/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/Jlink_RTT/Readme-Streamport.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/Jlink_RTT/Readme-Streamport.txt new file mode 100644 index 0000000..cae5e8e --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/Jlink_RTT/Readme-Streamport.txt @@ -0,0 +1,22 @@ +Tracealyzer Stream Port for SEGGER J-Link +----------------------------------------- + +This directory contains a "stream port" for the Tracealyzer recorder library, +i.e., the specific code needed to use a particular interface for streaming a +Tracealyzer RTOS trace. The stream port is defined by a set of macros in +trcStreamingPort.h, found in the "include" directory. + +This particular stream port targets SEGGER J-Link debug probes, using the RTT +interface provided by SEGGER. + +To use this stream port, make sure that include/trcStreamingPort.h is found +by the compiler (i.e., add this folder to your project's include paths) and +add all included source files to your build. Make sure no other versions of +trcStreamingPort.h are included by mistake! + +Note that this stream port also contains SEGGER's RTT driver. + +See also http://percepio.com/2016/10/05/rtos-tracing. + +Percepio AB +www.percepio.com \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/Jlink_RTT/SEGGER_RTT.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/Jlink_RTT/SEGGER_RTT.c new file mode 100644 index 0000000..3ff3ba9 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/Jlink_RTT/SEGGER_RTT.c @@ -0,0 +1,1447 @@ +/********************************************************************* +* SEGGER MICROCONTROLLER GmbH & Co. KG * +* Solutions for real time microcontroller applications * +********************************************************************** +* * +* (c) 2014 - 2016 SEGGER Microcontroller GmbH & Co. KG * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* * This software may in its unmodified form be freely redistributed * +* in source, linkable, or executable form. * +* * The source code may be modified, provided the source code * +* retains the above copyright notice, this list of conditions and * +* the following disclaimer. * +* * Modified versions of this software in source, executable, or * +* linkable form may not be distributed without prior consent of * +* SEGGER. * +* * This software may only be used for communication with SEGGER * +* J-Link debug probes. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +* * +* RTT version: 6.00e * +* * +********************************************************************** +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT.c +Purpose : Implementation of SEGGER real-time transfer (RTT) which + allows real-time communication on targets which support + debugger memory accesses while the CPU is running. +Revision: $Rev: 4079 $ + +Additional information: + Type "int" is assumed to be 32-bits in size + H->T Host to target communication + T->H Target to host communication + + RTT channel 0 is always present and reserved for Terminal usage. + Name is fixed to "Terminal" + + Effective buffer size: SizeOfBuffer - 1 + + WrOff == RdOff: Buffer is empty + WrOff == (RdOff - 1): Buffer is full + WrOff > RdOff: Free space includes wrap-around + WrOff < RdOff: Used space includes wrap-around + (WrOff == (SizeOfBuffer - 1)) && (RdOff == 0): + Buffer full and wrap-around after next byte + + +---------------------------------------------------------------------- +*/ + +#include "SEGGER_RTT.h" + +#include // for memcpy + +/********************************************************************* +* +* Configuration, default values +* +********************************************************************** +*/ + +#ifndef BUFFER_SIZE_UP + #define BUFFER_SIZE_UP 1024 // Size of the buffer for terminal output of target, up to host +#endif + +#ifndef BUFFER_SIZE_DOWN + #define BUFFER_SIZE_DOWN 16 // Size of the buffer for terminal input to target from host (Usually keyboard input) +#endif + +#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS + #define SEGGER_RTT_MAX_NUM_UP_BUFFERS 2 // Number of up-buffers (T->H) available on this target +#endif + +#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS + #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS 2 // Number of down-buffers (H->T) available on this target +#endif + +#ifndef SEGGER_RTT_BUFFER_SECTION + #if defined(SEGGER_RTT_SECTION) + #define SEGGER_RTT_BUFFER_SECTION SEGGER_RTT_SECTION + #endif +#endif + +#ifndef SEGGER_RTT_ALIGNMENT + #define SEGGER_RTT_ALIGNMENT 0 +#endif + +#ifndef SEGGER_RTT_BUFFER_ALIGNMENT + #define SEGGER_RTT_BUFFER_ALIGNMENT 0 +#endif + +#ifndef SEGGER_RTT_MODE_DEFAULT + #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP +#endif + +#ifndef SEGGER_RTT_LOCK + #define SEGGER_RTT_LOCK() +#endif + +#ifndef SEGGER_RTT_UNLOCK + #define SEGGER_RTT_UNLOCK() +#endif + +#ifndef STRLEN + #define STRLEN(a) strlen((a)) +#endif + +#ifndef MEMCPY + #define MEMCPY(pDest, pSrc, NumBytes) memcpy((pDest), (pSrc), (NumBytes)) +#endif + +#ifndef MIN + #define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef MAX + #define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +// +// For some environments, NULL may not be defined until certain headers are included +// +#ifndef NULL + #define NULL 0 +#endif + +/********************************************************************* +* +* Defines, fixed +* +********************************************************************** +*/ +#if (defined __ICCARM__) || (defined __ICCRX__) + #define RTT_PRAGMA(P) _Pragma(#P) +#endif + +#if SEGGER_RTT_ALIGNMENT || SEGGER_RTT_BUFFER_ALIGNMENT + #if (defined __GNUC__) + #define SEGGER_RTT_ALIGN(Var, Alignment) Var __attribute__ ((aligned (Alignment))) + #elif (defined __ICCARM__) || (defined __ICCRX__) + #define PRAGMA(A) _Pragma(#A) +#define SEGGER_RTT_ALIGN(Var, Alignment) RTT_PRAGMA(data_alignment=Alignment) \ + Var + #elif (defined __CC_ARM__) + #define SEGGER_RTT_ALIGN(Var, Alignment) Var __attribute__ ((aligned (Alignment))) + #else + #error "Alignment not supported for this compiler." + #endif +#else + #define SEGGER_RTT_ALIGN(Var, Alignment) Var +#endif + +#if defined(SEGGER_RTT_SECTION) || defined (SEGGER_RTT_BUFFER_SECTION) + #if (defined __GNUC__) + #define SEGGER_RTT_PUT_SECTION(Var, Section) __attribute__ ((section (Section))) Var + #elif (defined __ICCARM__) || (defined __ICCRX__) +#define SEGGER_RTT_PUT_SECTION(Var, Section) RTT_PRAGMA(location=Section) \ + Var + #elif (defined __CC_ARM__) + #define SEGGER_RTT_PUT_SECTION(Var, Section) __attribute__ ((section (Section), zero_init)) Var + #else + #error "Section placement not supported for this compiler." + #endif +#else + #define SEGGER_RTT_PUT_SECTION(Var, Section) Var +#endif + + +#if SEGGER_RTT_ALIGNMENT + #define SEGGER_RTT_CB_ALIGN(Var) SEGGER_RTT_ALIGN(Var, SEGGER_RTT_ALIGNMENT) +#else + #define SEGGER_RTT_CB_ALIGN(Var) Var +#endif + +#if SEGGER_RTT_BUFFER_ALIGNMENT + #define SEGGER_RTT_BUFFER_ALIGN(Var) SEGGER_RTT_ALIGN(Var, SEGGER_RTT_BUFFER_ALIGNMENT) +#else + #define SEGGER_RTT_BUFFER_ALIGN(Var) Var +#endif + + +#if defined(SEGGER_RTT_SECTION) + #define SEGGER_RTT_PUT_CB_SECTION(Var) SEGGER_RTT_PUT_SECTION(Var, SEGGER_RTT_SECTION) +#else + #define SEGGER_RTT_PUT_CB_SECTION(Var) Var +#endif + +#if defined(SEGGER_RTT_BUFFER_SECTION) + #define SEGGER_RTT_PUT_BUFFER_SECTION(Var) SEGGER_RTT_PUT_SECTION(Var, SEGGER_RTT_BUFFER_SECTION) +#else + #define SEGGER_RTT_PUT_BUFFER_SECTION(Var) Var +#endif + +/********************************************************************* +* +* Static const data +* +********************************************************************** +*/ + +static unsigned char _aTerminalId[16] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' }; + +/********************************************************************* +* +* Static data +* +********************************************************************** +*/ +// +// RTT Control Block and allocate buffers for channel 0 +// +SEGGER_RTT_PUT_CB_SECTION(SEGGER_RTT_CB_ALIGN(SEGGER_RTT_CB _SEGGER_RTT)); + +SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acUpBuffer [BUFFER_SIZE_UP])); +SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acDownBuffer[BUFFER_SIZE_DOWN])); + +static char _ActiveTerminal; + +/********************************************************************* +* +* Static functions +* +********************************************************************** +*/ + +/********************************************************************* +* +* _DoInit() +* +* Function description +* Initializes the control block an buffers. +* May only be called via INIT() to avoid overriding settings. +* +*/ +#define INIT() do { \ + if (_SEGGER_RTT.acID[0] == '\0') { _DoInit(); } \ + } while (0) +static void _DoInit(void) { + SEGGER_RTT_CB* p; + // + // Initialize control block + // + p = &_SEGGER_RTT; + p->MaxNumUpBuffers = SEGGER_RTT_MAX_NUM_UP_BUFFERS; + p->MaxNumDownBuffers = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS; + // + // Initialize up buffer 0 + // + p->aUp[0].sName = "Terminal"; + p->aUp[0].pBuffer = _acUpBuffer; + p->aUp[0].SizeOfBuffer = sizeof(_acUpBuffer); + p->aUp[0].RdOff = 0u; + p->aUp[0].WrOff = 0u; + p->aUp[0].Flags = SEGGER_RTT_MODE_DEFAULT; + // + // Initialize down buffer 0 + // + p->aDown[0].sName = "Terminal"; + p->aDown[0].pBuffer = _acDownBuffer; + p->aDown[0].SizeOfBuffer = sizeof(_acDownBuffer); + p->aDown[0].RdOff = 0u; + p->aDown[0].WrOff = 0u; + p->aDown[0].Flags = SEGGER_RTT_MODE_DEFAULT; + // + // Finish initialization of the control block. + // Copy Id string in three steps to make sure "SEGGER RTT" is not found + // in initializer memory (usually flash) by J-Link + // + strcpy(&p->acID[7], "RTT"); + strcpy(&p->acID[0], "SEGGER"); + p->acID[6] = ' '; +} + +/********************************************************************* +* +* _WriteBlocking() +* +* Function description +* Stores a specified number of characters in SEGGER RTT ring buffer +* and updates the associated write pointer which is periodically +* read by the host. +* The caller is responsible for managing the write chunk sizes as +* _WriteBlocking() will block until all data has been posted successfully. +* +* Parameters +* pRing Ring buffer to post to. +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* >= 0 - Number of bytes written into buffer. +*/ +static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer, unsigned NumBytes) { + unsigned NumBytesToWrite; + unsigned NumBytesWritten; + unsigned RdOff; + unsigned WrOff; + // + // Write data to buffer and handle wrap-around if necessary + // + NumBytesWritten = 0u; + WrOff = pRing->WrOff; + do { + RdOff = pRing->RdOff; // May be changed by host (debug probe) in the meantime + if (RdOff > WrOff) { + NumBytesToWrite = RdOff - WrOff - 1u; + } else { + NumBytesToWrite = pRing->SizeOfBuffer - (WrOff - RdOff + 1u); + } + NumBytesToWrite = MIN(NumBytesToWrite, (pRing->SizeOfBuffer - WrOff)); // Number of bytes that can be written until buffer wrap-around + NumBytesToWrite = MIN(NumBytesToWrite, NumBytes); + memcpy(pRing->pBuffer + WrOff, pBuffer, NumBytesToWrite); + NumBytesWritten += NumBytesToWrite; + pBuffer += NumBytesToWrite; + NumBytes -= NumBytesToWrite; + WrOff += NumBytesToWrite; + if (WrOff == pRing->SizeOfBuffer) { + WrOff = 0u; + } + pRing->WrOff = WrOff; + } while (NumBytes); + // + return NumBytesWritten; +} + +/********************************************************************* +* +* _WriteNoCheck() +* +* Function description +* Stores a specified number of characters in SEGGER RTT ring buffer +* and updates the associated write pointer which is periodically +* read by the host. +* It is callers responsibility to make sure data actually fits in buffer. +* +* Parameters +* pRing Ring buffer to post to. +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Notes +* (1) If there might not be enough space in the "Up"-buffer, call _WriteBlocking +*/ +static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsigned NumBytes) { + unsigned NumBytesAtOnce; + unsigned WrOff; + unsigned Rem; + + WrOff = pRing->WrOff; + Rem = pRing->SizeOfBuffer - WrOff; + if (Rem > NumBytes) { + // + // All data fits before wrap around + // + memcpy(pRing->pBuffer + WrOff, pData, NumBytes); + pRing->WrOff = WrOff + NumBytes; + } else { + // + // We reach the end of the buffer, so need to wrap around + // + NumBytesAtOnce = Rem; + memcpy(pRing->pBuffer + WrOff, pData, NumBytesAtOnce); + NumBytesAtOnce = NumBytes - Rem; + memcpy(pRing->pBuffer, pData + Rem, NumBytesAtOnce); + pRing->WrOff = NumBytesAtOnce; + } +} + +/********************************************************************* +* +* _PostTerminalSwitch() +* +* Function description +* Switch terminal to the given terminal ID. It is the caller's +* responsibility to ensure the terminal ID is correct and there is +* enough space in the buffer for this to complete successfully. +* +* Parameters +* pRing Ring buffer to post to. +* TerminalId Terminal ID to switch to. +*/ +static void _PostTerminalSwitch(SEGGER_RTT_BUFFER_UP* pRing, unsigned char TerminalId) { + char ac[2]; + + ac[0] = 0xFFu; + ac[1] = _aTerminalId[TerminalId]; // Caller made already sure that TerminalId does not exceed our terminal limit + _WriteBlocking(pRing, ac, 2u); +} + +/********************************************************************* +* +* _GetAvailWriteSpace() +* +* Function description +* Returns the number of bytes that can be written to the ring +* buffer without blocking. +* +* Parameters +* pRing Ring buffer to check. +* +* Return value +* Number of bytes that are free in the buffer. +*/ +static unsigned _GetAvailWriteSpace(SEGGER_RTT_BUFFER_UP* pRing) { + unsigned RdOff; + unsigned WrOff; + unsigned r; + // + // Avoid warnings regarding volatile access order. It's not a problem + // in this case, but dampen compiler enthusiasm. + // + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + if (RdOff <= WrOff) { + r = pRing->SizeOfBuffer - 1u - WrOff + RdOff; + } else { + r = RdOff - WrOff - 1u; + } + return r; +} + +/********************************************************************* +* +* Public code +* +********************************************************************** +*/ +/********************************************************************* +* +* SEGGER_RTT_ReadNoLock() +* +* Function description +* Reads characters from SEGGER real-time-terminal control block +* which have been previously stored by the host. +* Do not lock against interrupts and multiple access. +* +* Parameters +* BufferIndex Index of Down-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to. +* BufferSize Size of the target application buffer. +* +* Return value +* Number of bytes that have been read. +*/ +unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned BufferSize) { + unsigned NumBytesRem; + unsigned NumBytesRead; + unsigned RdOff; + unsigned WrOff; + unsigned char* pBuffer; + SEGGER_RTT_BUFFER_DOWN* pRing; + // + INIT(); + pRing = &_SEGGER_RTT.aDown[BufferIndex]; + pBuffer = (unsigned char*)pData; + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + NumBytesRead = 0u; + // + // Read from current read position to wrap-around of buffer, first + // + if (RdOff > WrOff) { + NumBytesRem = pRing->SizeOfBuffer - RdOff; + NumBytesRem = MIN(NumBytesRem, BufferSize); + memcpy(pBuffer, pRing->pBuffer + RdOff, NumBytesRem); + NumBytesRead += NumBytesRem; + pBuffer += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; + // + // Handle wrap-around of buffer + // + if (RdOff == pRing->SizeOfBuffer) { + RdOff = 0u; + } + } + // + // Read remaining items of buffer + // + NumBytesRem = WrOff - RdOff; + NumBytesRem = MIN(NumBytesRem, BufferSize); + if (NumBytesRem > 0u) { + memcpy(pBuffer, pRing->pBuffer + RdOff, NumBytesRem); + NumBytesRead += NumBytesRem; + pBuffer += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; + } + if (NumBytesRead) { + pRing->RdOff = RdOff; + } + // + return NumBytesRead; +} + +/********************************************************************* +* +* SEGGER_RTT_Read +* +* Function description +* Reads characters from SEGGER real-time-terminal control block +* which have been previously stored by the host. +* +* Parameters +* BufferIndex Index of Down-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to. +* BufferSize Size of the target application buffer. +* +* Return value +* Number of bytes that have been read. +*/ +unsigned SEGGER_RTT_Read(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) { + unsigned NumBytesRead; + // + SEGGER_RTT_LOCK(); + // + // Call the non-locking read function + // + NumBytesRead = SEGGER_RTT_ReadNoLock(BufferIndex, pBuffer, BufferSize); + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + // + return NumBytesRead; +} + +/********************************************************************* +* +* SEGGER_RTT_WriteWithOverwriteNoLock +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block. +* SEGGER_RTT_WriteWithOverwriteNoLock does not lock the application +* and overwrites data if the data does not fit into the buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, data is overwritten. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +* (3) Do not use SEGGER_RTT_WriteWithOverwriteNoLock if a J-Link +* connection reads RTT data. +*/ +void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + const char* pData; + SEGGER_RTT_BUFFER_UP* pRing; + unsigned Avail; + + pData = (const char *)pBuffer; + // + // Get "to-host" ring buffer and copy some elements into local variables. + // + pRing = &_SEGGER_RTT.aUp[BufferIndex]; + // + // Check if we will overwrite data and need to adjust the RdOff. + // + if (pRing->WrOff == pRing->RdOff) { + Avail = pRing->SizeOfBuffer - 1u; + } else if ( pRing->WrOff < pRing->RdOff) { + Avail = pRing->RdOff - pRing->WrOff - 1u; + } else { + Avail = pRing->RdOff - pRing->WrOff - 1u + pRing->SizeOfBuffer; + } + if (NumBytes > Avail) { + pRing->RdOff += (NumBytes - Avail); + while (pRing->RdOff >= pRing->SizeOfBuffer) { + pRing->RdOff -= pRing->SizeOfBuffer; + } + } + // + // Write all data, no need to check the RdOff, but possibly handle multiple wrap-arounds + // + Avail = pRing->SizeOfBuffer - pRing->WrOff; + do { + if (Avail > NumBytes) { + // + // Last round + // +#if 1 // memcpy() is good for large amounts of data, but the overhead is too big for small amounts. Use a simple byte loop instead. + char* pDst; + pDst = pRing->pBuffer + pRing->WrOff; + pRing->WrOff += NumBytes; + do { + *pDst++ = *pData++; + } while (--NumBytes); +#else + memcpy(pRing->pBuffer + WrOff, pData, NumBytes); + pRing->WrOff += NumBytes; +#endif + break; //Alternatively: NumBytes = 0; + } else { + // + // Wrap-around necessary, write until wrap-around and reset WrOff + // + memcpy(pRing->pBuffer + pRing->WrOff, pData, Avail); + pData += Avail; + pRing->WrOff = 0; + NumBytes -= Avail; + Avail = (pRing->SizeOfBuffer - 1); + } + } while (NumBytes); +} + +/********************************************************************* +* +* SEGGER_RTT_WriteSkipNoLock +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block which is then read by the host. +* SEGGER_RTT_WriteSkipNoLock does not lock the application and +* skips all data, if the data does not fit into the buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, all data is dropped. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +*/ +unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + const char* pData; + SEGGER_RTT_BUFFER_UP* pRing; + unsigned Avail; + unsigned RdOff; + unsigned WrOff; + unsigned Rem; + + pData = (const char *)pBuffer; + // + // Get "to-host" ring buffer and copy some elements into local variables. + // + pRing = &_SEGGER_RTT.aUp[BufferIndex]; + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + // + // Handle the most common cases fastest. + // Which is: + // RdOff <= WrOff -> Space until wrap around is free. + // AND + // WrOff + NumBytes < SizeOfBuffer -> No Wrap around necessary. + // + // OR + // + // RdOff > WrOff -> Space until RdOff - 1 is free. + // AND + // WrOff + NumBytes < RdOff -> Data fits into buffer + // + if (RdOff <= WrOff) { + // + // Get space until WrOff will be at wrap around. + // + Avail = pRing->SizeOfBuffer - 1u - WrOff ; + if (Avail >= NumBytes) { +#if 1 // memcpy() is good for large amounts of data, but the overhead is too big for small amounts. Use a simple byte loop instead. + char* pDst; + pDst = pRing->pBuffer + WrOff; + WrOff += NumBytes; + do { + *pDst++ = *pData++; + } while (--NumBytes); + pRing->WrOff = WrOff + NumBytes; +#else + memcpy(pRing->pBuffer + WrOff, pData, NumBytes); + pRing->WrOff = WrOff + NumBytes; +#endif + return 1; + } + // + // If data did not fit into space until wrap around calculate complete space in buffer. + // + Avail += RdOff; + // + // If there is still no space for the whole of this output, don't bother. + // + if (Avail >= NumBytes) { + // + // OK, we have enough space in buffer. Copy in one or 2 chunks + // + Rem = pRing->SizeOfBuffer - WrOff; // Space until end of buffer + if (Rem > NumBytes) { + memcpy(pRing->pBuffer + WrOff, pData, NumBytes); + pRing->WrOff = WrOff + NumBytes; + } else { + // + // We reach the end of the buffer, so need to wrap around + // + memcpy(pRing->pBuffer + WrOff, pData, Rem); + memcpy(pRing->pBuffer, pData + Rem, NumBytes - Rem); + pRing->WrOff = NumBytes - Rem; + } + return 1; + } + } else { + Avail = RdOff - WrOff - 1u; + if (Avail >= NumBytes) { + memcpy(pRing->pBuffer + WrOff, pData, NumBytes); + pRing->WrOff = WrOff + NumBytes; + return 1; + } + } + // + // If we reach this point no data has been written + // + return 0; +} + +/********************************************************************* +* +* SEGGER_RTT_WriteNoLock +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block which is then read by the host. +* SEGGER_RTT_WriteNoLock does not lock the application. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, remaining characters of pBuffer are dropped. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +*/ +unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + unsigned Status; + unsigned Avail; + const char* pData; + SEGGER_RTT_BUFFER_UP* pRing; + + pData = (const char *)pBuffer; + // + // Get "to-host" ring buffer. + // + pRing = &_SEGGER_RTT.aUp[BufferIndex]; + // + // How we output depends upon the mode... + // + switch (pRing->Flags) { + case SEGGER_RTT_MODE_NO_BLOCK_SKIP: + // + // If we are in skip mode and there is no space for the whole + // of this output, don't bother. + // + Avail = _GetAvailWriteSpace(pRing); + if (Avail < NumBytes) { + Status = 0u; + } else { + Status = NumBytes; + _WriteNoCheck(pRing, pData, NumBytes); + } + break; + case SEGGER_RTT_MODE_NO_BLOCK_TRIM: + // + // If we are in trim mode, trim to what we can output without blocking. + // + Avail = _GetAvailWriteSpace(pRing); + Status = Avail < NumBytes ? Avail : NumBytes; + _WriteNoCheck(pRing, pData, Status); + break; + case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: + // + // If we are in blocking mode, output everything. + // + Status = _WriteBlocking(pRing, pData, NumBytes); + break; + default: + Status = 0u; + break; + } + // + // Finish up. + // + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_Write +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block which is then read by the host. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, remaining characters of pBuffer are dropped. +*/ +unsigned SEGGER_RTT_Write(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + unsigned Status; + // + INIT(); + SEGGER_RTT_LOCK(); + // + // Call the non-locking write function + // + Status = SEGGER_RTT_WriteNoLock(BufferIndex, pBuffer, NumBytes); + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + // + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_WriteString +* +* Function description +* Stores string in SEGGER RTT control block. +* This data is read by the host. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* s Pointer to string. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, depending on configuration, +* remaining characters may be dropped or RTT module waits until there is more space in the buffer. +* (2) String passed to this function has to be \0 terminated +* (3) \0 termination character is *not* stored in RTT buffer +*/ +unsigned SEGGER_RTT_WriteString(unsigned BufferIndex, const char* s) { + unsigned Len; + + Len = STRLEN(s); + return SEGGER_RTT_Write(BufferIndex, s, Len); +} + +/********************************************************************* +* +* SEGGER_RTT_GetKey +* +* Function description +* Reads one character from the SEGGER RTT buffer. +* Host has previously stored data there. +* +* Return value +* < 0 - No character available (buffer empty). +* >= 0 - Character which has been read. (Possible values: 0 - 255) +* +* Notes +* (1) This function is only specified for accesses to RTT buffer 0. +*/ +int SEGGER_RTT_GetKey(void) { + char c; + int r; + + r = (int)SEGGER_RTT_Read(0u, &c, 1u); + if (r == 1) { + r = (int)(unsigned char)c; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_WaitKey +* +* Function description +* Waits until at least one character is avaible in the SEGGER RTT buffer. +* Once a character is available, it is read and this function returns. +* +* Return value +* >=0 - Character which has been read. +* +* Notes +* (1) This function is only specified for accesses to RTT buffer 0 +* (2) This function is blocking if no character is present in RTT buffer +*/ +int SEGGER_RTT_WaitKey(void) { + int r; + + do { + r = SEGGER_RTT_GetKey(); + } while (r < 0); + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_HasKey +* +* Function description +* Checks if at least one character for reading is available in the SEGGER RTT buffer. +* +* Return value +* == 0 - No characters are available to read. +* == 1 - At least one character is available. +* +* Notes +* (1) This function is only specified for accesses to RTT buffer 0 +*/ +int SEGGER_RTT_HasKey(void) { + unsigned RdOff; + int r; + + INIT(); + RdOff = _SEGGER_RTT.aDown[0].RdOff; + if (RdOff != _SEGGER_RTT.aDown[0].WrOff) { + r = 1; + } else { + r = 0; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_HasData +* +* Function description +* Check if there is data from the host in the given buffer. +* +* Return value: +* ==0: No data +* !=0: Data in buffer +* +*/ +unsigned SEGGER_RTT_HasData(unsigned BufferIndex) { + SEGGER_RTT_BUFFER_DOWN* pRing; + unsigned v; + + pRing = &_SEGGER_RTT.aDown[BufferIndex]; + v = pRing->WrOff; + return v - pRing->RdOff; +} + +/********************************************************************* +* +* SEGGER_RTT_AllocDownBuffer +* +* Function description +* Run-time configuration of the next down-buffer (H->T). +* The next buffer, which is not used yet is configured. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* +* Return value +* >= 0 - O.K. Buffer Index +* < 0 - Error +*/ +int SEGGER_RTT_AllocDownBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int BufferIndex; + + INIT(); + SEGGER_RTT_LOCK(); + BufferIndex = 0; + do { + if (_SEGGER_RTT.aDown[BufferIndex].pBuffer == NULL) { + break; + } + BufferIndex++; + } while (BufferIndex < _SEGGER_RTT.MaxNumDownBuffers); + if (BufferIndex < _SEGGER_RTT.MaxNumDownBuffers) { + _SEGGER_RTT.aDown[BufferIndex].sName = sName; + _SEGGER_RTT.aDown[BufferIndex].pBuffer = (char*)pBuffer; + _SEGGER_RTT.aDown[BufferIndex].SizeOfBuffer = BufferSize; + _SEGGER_RTT.aDown[BufferIndex].RdOff = 0u; + _SEGGER_RTT.aDown[BufferIndex].WrOff = 0u; + _SEGGER_RTT.aDown[BufferIndex].Flags = Flags; + } else { + BufferIndex = -1; + } + SEGGER_RTT_UNLOCK(); + return BufferIndex; +} + +/********************************************************************* +* +* SEGGER_RTT_AllocUpBuffer +* +* Function description +* Run-time configuration of the next up-buffer (T->H). +* The next buffer, which is not used yet is configured. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* +* Return value +* >= 0 - O.K. Buffer Index +* < 0 - Error +*/ +int SEGGER_RTT_AllocUpBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int BufferIndex; + + INIT(); + SEGGER_RTT_LOCK(); + BufferIndex = 0; + do { + if (_SEGGER_RTT.aUp[BufferIndex].pBuffer == NULL) { + break; + } + BufferIndex++; + } while (BufferIndex < _SEGGER_RTT.MaxNumUpBuffers); + if (BufferIndex < _SEGGER_RTT.MaxNumUpBuffers) { + _SEGGER_RTT.aUp[BufferIndex].sName = sName; + _SEGGER_RTT.aUp[BufferIndex].pBuffer = (char*)pBuffer; + _SEGGER_RTT.aUp[BufferIndex].SizeOfBuffer = BufferSize; + _SEGGER_RTT.aUp[BufferIndex].RdOff = 0u; + _SEGGER_RTT.aUp[BufferIndex].WrOff = 0u; + _SEGGER_RTT.aUp[BufferIndex].Flags = Flags; + } else { + BufferIndex = -1; + } + SEGGER_RTT_UNLOCK(); + return BufferIndex; +} + +/********************************************************************* +* +* SEGGER_RTT_ConfigUpBuffer +* +* Function description +* Run-time configuration of a specific up-buffer (T->H). +* Buffer to be configured is specified by index. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* BufferIndex Index of the buffer to configure. +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* +* Return value +* >= 0 - O.K. +* < 0 - Error +* +* Additional information +* Buffer 0 is configured on compile-time. +* May only be called once per buffer. +* Buffer name and flags can be reconfigured using the appropriate functions. +*/ +int SEGGER_RTT_ConfigUpBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int r; + + INIT(); + if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumUpBuffers) { + SEGGER_RTT_LOCK(); + if (BufferIndex > 0u) { + _SEGGER_RTT.aUp[BufferIndex].sName = sName; + _SEGGER_RTT.aUp[BufferIndex].pBuffer = (char*)pBuffer; + _SEGGER_RTT.aUp[BufferIndex].SizeOfBuffer = BufferSize; + _SEGGER_RTT.aUp[BufferIndex].RdOff = 0u; + _SEGGER_RTT.aUp[BufferIndex].WrOff = 0u; + } + _SEGGER_RTT.aUp[BufferIndex].Flags = Flags; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_ConfigDownBuffer +* +* Function description +* Run-time configuration of a specific down-buffer (H->T). +* Buffer to be configured is specified by index. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* BufferIndex Index of the buffer to configure. +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* +* Return value +* >= 0 O.K. +* < 0 Error +* +* Additional information +* Buffer 0 is configured on compile-time. +* May only be called once per buffer. +* Buffer name and flags can be reconfigured using the appropriate functions. +*/ +int SEGGER_RTT_ConfigDownBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int r; + + INIT(); + if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumDownBuffers) { + SEGGER_RTT_LOCK(); + if (BufferIndex > 0u) { + _SEGGER_RTT.aDown[BufferIndex].sName = sName; + _SEGGER_RTT.aDown[BufferIndex].pBuffer = (char*)pBuffer; + _SEGGER_RTT.aDown[BufferIndex].SizeOfBuffer = BufferSize; + _SEGGER_RTT.aDown[BufferIndex].RdOff = 0u; + _SEGGER_RTT.aDown[BufferIndex].WrOff = 0u; + } + _SEGGER_RTT.aDown[BufferIndex].Flags = Flags; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_SetNameUpBuffer +* +* Function description +* Run-time configuration of a specific up-buffer name (T->H). +* Buffer to be configured is specified by index. +* +* Parameters +* BufferIndex Index of the buffer to renamed. +* sName Pointer to a constant name string. +* +* Return value +* >= 0 O.K. +* < 0 Error +*/ +int SEGGER_RTT_SetNameUpBuffer(unsigned BufferIndex, const char* sName) { + int r; + + INIT(); + if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumUpBuffers) { + SEGGER_RTT_LOCK(); + _SEGGER_RTT.aUp[BufferIndex].sName = sName; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_SetNameDownBuffer +* +* Function description +* Run-time configuration of a specific Down-buffer name (T->H). +* Buffer to be configured is specified by index. +* +* Parameters +* BufferIndex Index of the buffer to renamed. +* sName Pointer to a constant name string. +* +* Return value +* >= 0 O.K. +* < 0 Error +*/ +int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName) { + int r; + + INIT(); + if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumDownBuffers) { + SEGGER_RTT_LOCK(); + _SEGGER_RTT.aDown[BufferIndex].sName = sName; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_SetFlagsUpBuffer +* +* Function description +* Run-time configuration of specific up-buffer flags (T->H). +* Buffer to be configured is specified by index. +* +* Parameters +* BufferIndex Index of the buffer. +* Flags Flags to set for the buffer. +* +* Return value +* >= 0 O.K. +* < 0 Error +*/ +int SEGGER_RTT_SetFlagsUpBuffer(unsigned BufferIndex, unsigned Flags) { + int r; + + INIT(); + if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumUpBuffers) { + SEGGER_RTT_LOCK(); + _SEGGER_RTT.aUp[BufferIndex].Flags = Flags; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_SetFlagsDownBuffer +* +* Function description +* Run-time configuration of specific Down-buffer flags (T->H). +* Buffer to be configured is specified by index. +* +* Parameters +* BufferIndex Index of the buffer to renamed. +* Flags Flags to set for the buffer. +* +* Return value +* >= 0 O.K. +* < 0 Error +*/ +int SEGGER_RTT_SetFlagsDownBuffer(unsigned BufferIndex, unsigned Flags) { + int r; + + INIT(); + if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumDownBuffers) { + SEGGER_RTT_LOCK(); + _SEGGER_RTT.aDown[BufferIndex].Flags = Flags; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_Init +* +* Function description +* Initializes the RTT Control Block. +* Should be used in RAM targets, at start of the application. +* +*/ +void SEGGER_RTT_Init (void) { + _DoInit(); +} + +/********************************************************************* +* +* SEGGER_RTT_SetTerminal +* +* Function description +* Sets the terminal to be used for output on channel 0. +* +* Parameters +* TerminalId Index of the terminal. +* +* Return value +* >= 0 O.K. +* < 0 Error (e.g. if RTT is configured for non-blocking mode and there was no space in the buffer to set the new terminal Id) +*/ +int SEGGER_RTT_SetTerminal (char TerminalId) { + char ac[2]; + SEGGER_RTT_BUFFER_UP* pRing; + unsigned Avail; + int r; + // + INIT(); + // + r = 0; + ac[0] = 0xFFU; + if ((unsigned char)TerminalId < (unsigned char)sizeof(_aTerminalId)) { // We only support a certain number of channels + ac[1] = _aTerminalId[(unsigned char)TerminalId]; + pRing = &_SEGGER_RTT.aUp[0]; // Buffer 0 is always reserved for terminal I/O, so we can use index 0 here, fixed + SEGGER_RTT_LOCK(); // Lock to make sure that no other task is writing into buffer, while we are and number of free bytes in buffer does not change downwards after checking and before writing + if ((pRing->Flags & SEGGER_RTT_MODE_MASK) == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) { + _ActiveTerminal = TerminalId; + _WriteBlocking(pRing, ac, 2u); + } else { // Skipping mode or trim mode? => We cannot trim this command so handling is the same for both modes + Avail = _GetAvailWriteSpace(pRing); + if (Avail >= 2) { + _ActiveTerminal = TerminalId; // Only change active terminal in case of success + _WriteNoCheck(pRing, ac, 2u); + } else { + r = -1; + } + } + SEGGER_RTT_UNLOCK(); + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_TerminalOut +* +* Function description +* Writes a string to the given terminal +* without changing the terminal for channel 0. +* +* Parameters +* TerminalId Index of the terminal. +* s String to be printed on the terminal. +* +* Return value +* >= 0 - Number of bytes written. +* < 0 - Error. +* +*/ +int SEGGER_RTT_TerminalOut (char TerminalId, const char* s) { + int Status; + unsigned FragLen; + unsigned Avail; + SEGGER_RTT_BUFFER_UP* pRing; + // + INIT(); + // + // Validate terminal ID. + // + if (TerminalId < (char)sizeof(_aTerminalId)) { // We only support a certain number of channels + // + // Get "to-host" ring buffer. + // + pRing = &_SEGGER_RTT.aUp[0]; + // + // Need to be able to change terminal, write data, change back. + // Compute the fixed and variable sizes. + // + FragLen = strlen(s); + // + // How we output depends upon the mode... + // + SEGGER_RTT_LOCK(); + Avail = _GetAvailWriteSpace(pRing); + switch (pRing->Flags & SEGGER_RTT_MODE_MASK) { + case SEGGER_RTT_MODE_NO_BLOCK_SKIP: + // + // If we are in skip mode and there is no space for the whole + // of this output, don't bother switching terminals at all. + // + if (Avail < (FragLen + 4u)) { + Status = 0; + } else { + _PostTerminalSwitch(pRing, TerminalId); + Status = (int)_WriteBlocking(pRing, s, FragLen); + _PostTerminalSwitch(pRing, _ActiveTerminal); + } + break; + case SEGGER_RTT_MODE_NO_BLOCK_TRIM: + // + // If we are in trim mode and there is not enough space for everything, + // trim the output but always include the terminal switch. If no room + // for terminal switch, skip that totally. + // + if (Avail < 4u) { + Status = -1; + } else { + _PostTerminalSwitch(pRing, TerminalId); + Status = (int)_WriteBlocking(pRing, s, (FragLen < (Avail - 4u)) ? FragLen : (Avail - 4u)); + _PostTerminalSwitch(pRing, _ActiveTerminal); + } + break; + case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: + // + // If we are in blocking mode, output everything. + // + _PostTerminalSwitch(pRing, TerminalId); + Status = (int)_WriteBlocking(pRing, s, FragLen); + _PostTerminalSwitch(pRing, _ActiveTerminal); + break; + default: + Status = -1; + break; + } + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + } else { + Status = -1; + } + return Status; +} + + +/*************************** End of file ****************************/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/Jlink_RTT/include/SEGGER_RTT.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/Jlink_RTT/include/SEGGER_RTT.h new file mode 100644 index 0000000..cdd6270 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/Jlink_RTT/include/SEGGER_RTT.h @@ -0,0 +1,238 @@ +/********************************************************************* +* SEGGER MICROCONTROLLER GmbH & Co. KG * +* Solutions for real time microcontroller applications * +********************************************************************** +* * +* (c) 2014 - 2016 SEGGER Microcontroller GmbH & Co. KG * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* * This software may in its unmodified form be freely redistributed * +* in source, linkable, or executable form. * +* * The source code may be modified, provided the source code * +* retains the above copyright notice, this list of conditions and * +* the following disclaimer. * +* * Modified versions of this software in source, executable, or * +* linkable form may not be distributed without prior consent of * +* SEGGER. * +* * This software may only be used for communication with SEGGER * +* J-Link debug probes. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +* * +* RTT version: 6.00e * +* * +********************************************************************** +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT.h +Purpose : Implementation of SEGGER real-time transfer which allows + real-time communication on targets which support debugger + memory accesses while the CPU is running. +Revision: $Rev: 4079 $ +---------------------------------------------------------------------- +*/ + +#ifndef SEGGER_RTT_H +#define SEGGER_RTT_H + +#include "SEGGER_RTT_Conf.h" + +/********************************************************************* +* +* Defines, fixed +* +********************************************************************** +*/ + +/********************************************************************* +* +* Types +* +********************************************************************** +*/ + +// +// Description for a circular buffer (also called "ring buffer") +// which is used as up-buffer (T->H) +// +typedef struct { + const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" + char* pBuffer; // Pointer to start of buffer + unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. + unsigned WrOff; // Position of next item to be written by either target. + volatile unsigned RdOff; // Position of next item to be read by host. Must be volatile since it may be modified by host. + unsigned Flags; // Contains configuration flags +} SEGGER_RTT_BUFFER_UP; + +// +// Description for a circular buffer (also called "ring buffer") +// which is used as down-buffer (H->T) +// +typedef struct { + const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" + char* pBuffer; // Pointer to start of buffer + unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. + volatile unsigned WrOff; // Position of next item to be written by host. Must be volatile since it may be modified by host. + unsigned RdOff; // Position of next item to be read by target (down-buffer). + unsigned Flags; // Contains configuration flags +} SEGGER_RTT_BUFFER_DOWN; + +// +// RTT control block which describes the number of buffers available +// as well as the configuration for each buffer +// +// +typedef struct { + char acID[16]; // Initialized to "SEGGER RTT" + int MaxNumUpBuffers; // Initialized to SEGGER_RTT_MAX_NUM_UP_BUFFERS (type. 2) + int MaxNumDownBuffers; // Initialized to SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (type. 2) + SEGGER_RTT_BUFFER_UP aUp[SEGGER_RTT_MAX_NUM_UP_BUFFERS]; // Up buffers, transferring information up from target via debug probe to host + SEGGER_RTT_BUFFER_DOWN aDown[SEGGER_RTT_MAX_NUM_DOWN_BUFFERS]; // Down buffers, transferring information down from host via debug probe to target +} SEGGER_RTT_CB; + +/********************************************************************* +* +* Global data +* +********************************************************************** +*/ +extern SEGGER_RTT_CB _SEGGER_RTT; + +/********************************************************************* +* +* RTT API functions +* +********************************************************************** +*/ +#ifdef __cplusplus + extern "C" { +#endif +int SEGGER_RTT_AllocDownBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_AllocUpBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_ConfigUpBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_ConfigDownBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_GetKey (void); +unsigned SEGGER_RTT_HasData (unsigned BufferIndex); +int SEGGER_RTT_HasKey (void); +void SEGGER_RTT_Init (void); +unsigned SEGGER_RTT_Read (unsigned BufferIndex, void* pBuffer, unsigned BufferSize); +unsigned SEGGER_RTT_ReadNoLock (unsigned BufferIndex, void* pData, unsigned BufferSize); +int SEGGER_RTT_SetNameDownBuffer (unsigned BufferIndex, const char* sName); +int SEGGER_RTT_SetNameUpBuffer (unsigned BufferIndex, const char* sName); +int SEGGER_RTT_SetFlagsDownBuffer (unsigned BufferIndex, unsigned Flags); +int SEGGER_RTT_SetFlagsUpBuffer (unsigned BufferIndex, unsigned Flags); +int SEGGER_RTT_WaitKey (void); +unsigned SEGGER_RTT_Write (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteSkipNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteString (unsigned BufferIndex, const char* s); +void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +// +// Function macro for performance optimization +// +#define SEGGER_RTT_HASDATA(n) (_SEGGER_RTT.aDown[n].WrOff - _SEGGER_RTT.aDown[n].RdOff) + +/********************************************************************* +* +* RTT "Terminal" API functions +* +********************************************************************** +*/ +int SEGGER_RTT_SetTerminal (char TerminalId); +int SEGGER_RTT_TerminalOut (char TerminalId, const char* s); + +/********************************************************************* +* +* RTT printf functions (require SEGGER_RTT_printf.c) +* +********************************************************************** +*/ +int SEGGER_RTT_printf(unsigned BufferIndex, const char * sFormat, ...); +#ifdef __cplusplus + } +#endif + +/********************************************************************* +* +* Defines +* +********************************************************************** +*/ + +// +// Operating modes. Define behavior if buffer is full (not enough space for entire message) +// +#define SEGGER_RTT_MODE_NO_BLOCK_SKIP (0U) // Skip. Do not block, output nothing. (Default) +#define SEGGER_RTT_MODE_NO_BLOCK_TRIM (1U) // Trim: Do not block, output as much as fits. +#define SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL (2U) // Block: Wait until there is space in the buffer. +#define SEGGER_RTT_MODE_MASK (3U) + +// +// Control sequences, based on ANSI. +// Can be used to control color, and clear the screen +// +#define RTT_CTRL_RESET "" // Reset to default colors +#define RTT_CTRL_CLEAR "" // Clear screen, reposition cursor to top left + +#define RTT_CTRL_TEXT_BLACK "" +#define RTT_CTRL_TEXT_RED "" +#define RTT_CTRL_TEXT_GREEN "" +#define RTT_CTRL_TEXT_YELLOW "" +#define RTT_CTRL_TEXT_BLUE "" +#define RTT_CTRL_TEXT_MAGENTA "" +#define RTT_CTRL_TEXT_CYAN "" +#define RTT_CTRL_TEXT_WHITE "" + +#define RTT_CTRL_TEXT_BRIGHT_BLACK "" +#define RTT_CTRL_TEXT_BRIGHT_RED "" +#define RTT_CTRL_TEXT_BRIGHT_GREEN "" +#define RTT_CTRL_TEXT_BRIGHT_YELLOW "" +#define RTT_CTRL_TEXT_BRIGHT_BLUE "" +#define RTT_CTRL_TEXT_BRIGHT_MAGENTA "" +#define RTT_CTRL_TEXT_BRIGHT_CYAN "" +#define RTT_CTRL_TEXT_BRIGHT_WHITE "" + +#define RTT_CTRL_BG_BLACK "" +#define RTT_CTRL_BG_RED "" +#define RTT_CTRL_BG_GREEN "" +#define RTT_CTRL_BG_YELLOW "" +#define RTT_CTRL_BG_BLUE "" +#define RTT_CTRL_BG_MAGENTA "" +#define RTT_CTRL_BG_CYAN "" +#define RTT_CTRL_BG_WHITE "" + +#define RTT_CTRL_BG_BRIGHT_BLACK "" +#define RTT_CTRL_BG_BRIGHT_RED "" +#define RTT_CTRL_BG_BRIGHT_GREEN "" +#define RTT_CTRL_BG_BRIGHT_YELLOW "" +#define RTT_CTRL_BG_BRIGHT_BLUE "" +#define RTT_CTRL_BG_BRIGHT_MAGENTA "" +#define RTT_CTRL_BG_BRIGHT_CYAN "" +#define RTT_CTRL_BG_BRIGHT_WHITE "" + + +#endif + +/*************************** End of file ****************************/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/Jlink_RTT/include/SEGGER_RTT_Conf.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/Jlink_RTT/include/SEGGER_RTT_Conf.h new file mode 100644 index 0000000..4f7f4cc --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/Jlink_RTT/include/SEGGER_RTT_Conf.h @@ -0,0 +1,259 @@ +/********************************************************************* +* SEGGER MICROCONTROLLER GmbH & Co. KG * +* Solutions for real time microcontroller applications * +********************************************************************** +* * +* (c) 2014 - 2016 SEGGER Microcontroller GmbH & Co. KG * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* * This software may in its unmodified form be freely redistributed * +* in source, linkable, or executable form. * +* * The source code may be modified, provided the source code * +* retains the above copyright notice, this list of conditions and * +* the following disclaimer. * +* * Modified versions of this software in source, executable, or * +* linkable form may not be distributed without prior consent of * +* SEGGER. * +* * This software may only be used for communication with SEGGER * +* J-Link debug probes. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +* * +* RTT version: 6.00e * +* * +********************************************************************** +---------------------------------------------------------------------- +File : SEGGER_RTT_Conf.h +Purpose : Implementation of SEGGER real-time transfer (RTT) which + allows real-time communication on targets which support + debugger memory accesses while the CPU is running. +Revision: $Rev: 3892 $ +---------------------------END-OF-HEADER------------------------------ +*/ + +#ifndef SEGGER_RTT_CONF_H +#define SEGGER_RTT_CONF_H + +#ifdef __IAR_SYSTEMS_ICC__ + #include +#endif + +/********************************************************************* +* +* Defines, configurable +* +********************************************************************** +*/ + +#define SEGGER_RTT_MAX_NUM_UP_BUFFERS (3) // Max. number of up-buffers (T->H) available on this target (Default: 3) +#define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (3) // Max. number of down-buffers (H->T) available on this target (Default: 3) + +#define BUFFER_SIZE_UP (64) // Size of the buffer for terminal output of target, up to host (Default: 1k) +#define BUFFER_SIZE_DOWN (16) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) + +#define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) + +#define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0) + +// +// Target is not allowed to perform other RTT operations while string still has not been stored completely. +// Otherwise we would probably end up with a mixed string in the buffer. +// If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here. +// +// SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4. +// Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches. +// When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly. +// (Higher priority = lower priority number) +// Default value for embOS: 128u +// Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +// In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC +// or define SEGGER_RTT_LOCK() to completely disable interrupts. +// + +#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20) + +/********************************************************************* +* +* RTT lock configuration for SEGGER Embedded Studio, +* Rowley CrossStudio and GCC +*/ +#if (defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__) + #ifdef __ARM_ARCH_6M__ + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + __asm volatile ("mrs %0, primask \n\t" \ + "mov r1, $1 \n\t" \ + "msr primask, r1 \n\t" \ + : "=r" (LockState) \ + : \ + : "r1" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \ + : \ + : "r" (LockState) \ + : \ + ); \ + } + + #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + __asm volatile ("mrs %0, basepri \n\t" \ + "mov r1, %1 \n\t" \ + "msr basepri, r1 \n\t" \ + : "=r" (LockState) \ + : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ + : "r1" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \ + : \ + : "r" (LockState) \ + : \ + ); \ + } + + #elif defined(__ARM_ARCH_7A__) + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + __asm volatile ("mrs r1, CPSR \n\t" \ + "mov %0, r1 \n\t" \ + "orr r1, r1, #0xC0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : "=r" (LockState) \ + : \ + : "r1" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ + "mrs r1, CPSR \n\t" \ + "bic r1, r1, #0xC0 \n\t" \ + "and r0, r0, #0xC0 \n\t" \ + "orr r1, r1, r0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : \ + : "r" (LockState) \ + : "r0", "r1" \ + ); \ + } +#else + #define SEGGER_RTT_LOCK() + #define SEGGER_RTT_UNLOCK() + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for IAR EWARM +*/ +#ifdef __ICCARM__ + #if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + LockState = __get_PRIMASK(); \ + __set_PRIMASK(1); + + #define SEGGER_RTT_UNLOCK() __set_PRIMASK(LockState); \ + } + #elif ((defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || (defined (__ARM7M__) && (__CORE__ == __ARM7M__))) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + LockState = __get_BASEPRI(); \ + __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); + + #define SEGGER_RTT_UNLOCK() __set_BASEPRI(LockState); \ + } + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for IAR RX +*/ +#ifdef __ICCRX__ + #define SEGGER_RTT_LOCK() { \ + unsigned long LockState; \ + LockState = __get_interrupt_state(); \ + __disable_interrupt(); + + #define SEGGER_RTT_UNLOCK() __set_interrupt_state(LockState); \ + } +#endif + +/********************************************************************* +* +* RTT lock configuration for KEIL ARM +*/ +#ifdef __CC_ARM + #if (defined __TARGET_ARCH_6S_M) + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + register unsigned char PRIMASK __asm( "primask"); \ + LockState = PRIMASK; \ + PRIMASK = 1u; \ + __schedule_barrier(); + + #define SEGGER_RTT_UNLOCK() PRIMASK = LockState; \ + __schedule_barrier(); \ + } + #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + register unsigned char BASEPRI __asm( "basepri"); \ + LockState = BASEPRI; \ + BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ + __schedule_barrier(); + + #define SEGGER_RTT_UNLOCK() BASEPRI = LockState; \ + __schedule_barrier(); \ + } + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration fallback +*/ +#ifndef SEGGER_RTT_LOCK + #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) +#endif + +#ifndef SEGGER_RTT_UNLOCK + #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state) +#endif + +#endif +/*************************** End of file ****************************/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/Jlink_RTT/include/trcStreamingPort.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/Jlink_RTT/include/trcStreamingPort.h new file mode 100644 index 0000000..b1074b4 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/Jlink_RTT/include/trcStreamingPort.h @@ -0,0 +1,196 @@ +/******************************************************************************* + * Trace Recorder Library for Tracealyzer v4.1.5 + * Percepio AB, www.percepio.com + * + * trcStreamingPort.h + * + * The interface definitions for trace streaming ("stream ports"). + * This "stream port" sets up the recorder to use SEGGER RTT as streaming channel. + * + * Note that this stream port is more complex than the typical case, since + * the J-Link interface uses a separate RAM buffer in SEGGER_RTT.c, instead + * of the default buffer included in the recorder core. The other stream ports + * offer more typical examples of how to define a custom streaming interface. + * + * Terms of Use + * This file is part of the trace recorder library (RECORDER), which is the + * intellectual property of Percepio AB (PERCEPIO) and provided under a + * license as follows. + * The RECORDER may be used free of charge for the purpose of recording data + * intended for analysis in PERCEPIO products. It may not be used or modified + * for other purposes without explicit permission from PERCEPIO. + * You may distribute the RECORDER in its original source code form, assuming + * this text (terms of use, disclaimer, copyright notice) is unchanged. You are + * allowed to distribute the RECORDER with minor modifications intended for + * configuration or porting of the RECORDER, e.g., to allow using it on a + * specific processor, processor family or with a specific communication + * interface. Any such modifications should be documented directly below + * this comment block. + * + * Disclaimer + * The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty + * as to its use or performance. PERCEPIO does not and cannot warrant the + * performance or results you may obtain by using the RECORDER or documentation. + * PERCEPIO make no warranties, express or implied, as to noninfringement of + * third party rights, merchantability, or fitness for any particular purpose. + * In no event will PERCEPIO, its technology partners, or distributors be liable + * to you for any consequential, incidental or special damages, including any + * lost profits or lost savings, even if a representative of PERCEPIO has been + * advised of the possibility of such damages, or for any claim by any third + * party. Some jurisdictions do not allow the exclusion or limitation of + * incidental, consequential or special damages, or the exclusion of implied + * warranties or limitations on how long an implied warranty may last, so the + * above limitations may not apply to you. + * + * Tabs are used for indent in this file (1 tab = 4 spaces) + * + * Copyright Percepio AB, 2018. + * www.percepio.com + ******************************************************************************/ + +#ifndef TRC_STREAMING_PORT_H +#define TRC_STREAMING_PORT_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* + * Configuration Macro: TRC_CFG_RTT_BUFFER_SIZE_UP + * + * Defines the size of the "up" RTT buffer (target -> host) to use for writing + * the trace data, for RTT buffer 1 or higher. + * + * This setting is ignored for RTT buffer 0, which can't be reconfigured + * in runtime and therefore hard-coded to use the defines in SEGGER_RTT_Conf.h. + * + * Default buffer size for Tracealyzer is 5000 bytes. + * + * If you have a stand-alone J-Link probe, the can be decreased to around 1 KB. + * But integrated J-Link OB interfaces are slower and needs about 5-10 KB, + * depending on the amount of data produced. + ******************************************************************************/ +#define TRC_CFG_RTT_BUFFER_SIZE_UP 5000 + +/******************************************************************************* + * Configuration Macro: TRC_CFG_RTT_BUFFER_SIZE_DOWN + * + * Defines the size of the "down" RTT buffer (host -> target) to use for reading + * commands from Tracealyzer, for RTT buffer 1 or higher. + * + * Default buffer size for Tracealyzer is 32 bytes. + * + * This setting is ignored for RTT buffer 0, which can't be reconfigured + * in runtime and therefore hard-coded to use the defines in SEGGER_RTT_Conf.h. + ******************************************************************************/ +#define TRC_CFG_RTT_BUFFER_SIZE_DOWN 32 + +/******************************************************************************* + * Configuration Macro: TRC_CFG_RTT_UP_BUFFER_INDEX + * + * Defines the RTT buffer to use for writing the trace data. Make sure that + * the PC application has the same setting (File->Settings). + * + * Default: 1 + * + * We don't recommend using RTT buffer 0, since mainly intended for terminals. + * If you prefer to use buffer 0, it must be configured in SEGGER_RTT_Conf.h. + ******************************************************************************/ +#define TRC_CFG_RTT_UP_BUFFER_INDEX 1 + +/******************************************************************************* + * Configuration Macro: TRC_CFG_RTT_DOWN_BUFFER_INDEX + * + * Defines the RTT buffer to use for reading the trace data. Make sure that + * the PC application has the same setting (File->Settings). + * + * Default: 1 + * + * We don't recommend using RTT buffer 0, since mainly intended for terminals. + * If you prefer to use buffer 0, it must be configured in SEGGER_RTT_Conf.h. + ******************************************************************************/ +#define TRC_CFG_RTT_DOWN_BUFFER_INDEX 1 + +/******************************************************************************* + * TRC_CFG_RTT_MODE + * This stream port for J-Link streaming relies on SEGGER RTT, that contains an + * internal RAM buffer read by the J-Link probes during execution. + * + * Possible values: + * - SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL + * - SEGGER_RTT_MODE_NO_BLOCK_SKIP (default) + * + * Using SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL ensure that you get a + * complete and valid trace. This may however cause blocking if your streaming + * interface isn't fast enough, which may disturb the real-time behavior. + * + * We therefore recommend SEGGER_RTT_MODE_NO_BLOCK_SKIP. In this mode, + * Tracealyzer will report lost events if the transfer is not + * fast enough. In that case, try increasing the size of the "up buffer". + ******************************************************************************/ +#define TRC_CFG_RTT_MODE SEGGER_RTT_MODE_NO_BLOCK_SKIP + +#include "SEGGER_RTT_Conf.h" +#include "SEGGER_RTT.h" + +#if (TRC_CFG_RTT_UP_BUFFER_INDEX >= SEGGER_RTT_MAX_NUM_UP_BUFFERS) +#error "TRC_CFG_RTT_UP_BUFFER_INDEX must be smaller than SEGGER_RTT_MAX_NUM_UP_BUFFERS" +#endif + +#if (TRC_CFG_RTT_DOWN_BUFFER_INDEX >= SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) +#error "TRC_CFG_RTT_DOWN_BUFFER_INDEX must be smaller than SEGGER_RTT_MAX_NUM_DOWN_BUFFERS" +#endif + +/* If index is defined as 0, the internal RTT buffers will be used instead of this. */ +#if TRC_CFG_RTT_UP_BUFFER_INDEX == 0 +#define TRC_RTT_ALLOC_UP() static char* _TzTraceData = NULL; /* Not actually used. Ignore allocation method. */ +#define TRC_STREAM_PORT_MALLOC() /* Static allocation. Not used. */ +#else +#if TRC_CFG_RECORDER_BUFFER_ALLOCATION == TRC_RECORDER_BUFFER_ALLOCATION_STATIC +#define TRC_RTT_ALLOC_UP() char _TzTraceData[TRC_CFG_RTT_BUFFER_SIZE_UP]; /* Static allocation */ +#define TRC_STREAM_PORT_MALLOC() /* Static allocation. Not used. */ +#endif +#if TRC_CFG_RECORDER_BUFFER_ALLOCATION == TRC_RECORDER_BUFFER_ALLOCATION_DYNAMIC +#define TRC_RTT_ALLOC_UP() char* _TzTraceData = NULL; /* Dynamic allocation */ +#define TRC_STREAM_PORT_MALLOC() _TzTraceData = TRC_PORT_MALLOC(TRC_CFG_RTT_BUFFER_SIZE_UP); +#endif +#if TRC_CFG_RECORDER_BUFFER_ALLOCATION == TRC_RECORDER_BUFFER_ALLOCATION_CUSTOM +#define TRC_RTT_ALLOC_UP() char* _TzTraceData = NULL; /* Custom allocation, user needs to call vTraceSetRecorderDataBuffer before vTraceEnable, to assign this */ +#define TRC_STREAM_PORT_MALLOC() /* Not used in custom mode */ +#endif +#endif + +/* Down-buffer. If index is defined as 0, the internal RTT buffers will be used instead of this. */ \ +#if TRC_CFG_RTT_DOWN_BUFFER_INDEX == 0 +#define TRC_RTT_ALLOC_DOWN() static char* _TzCtrlData = NULL; /* Not actually used. Ignore allocation method. */ +#else +#define TRC_RTT_ALLOC_DOWN() static char _TzCtrlData[TRC_CFG_RTT_BUFFER_SIZE_DOWN]; /* Always static allocation, since usually small. */ +#endif + +#define TRC_STREAM_PORT_ALLOCATE_FIELDS() \ + TRC_RTT_ALLOC_UP() /* Macro that will result in proper UP buffer allocation */ \ + TRC_RTT_ALLOC_DOWN() /* Macro that will result in proper DOWN buffer allocation */ + +int32_t readFromRTT(void* ptrData, uint32_t size, int32_t* ptrBytesRead); + +int32_t writeToRTT(void* ptrData, uint32_t size, int32_t* ptrBytesWritten); + + +#define TRC_STREAM_PORT_INIT() \ + TRC_STREAM_PORT_MALLOC(); /*Dynamic allocation or empty if static */ \ + SEGGER_RTT_ConfigUpBuffer(TRC_CFG_RTT_UP_BUFFER_INDEX, "TzData", _TzTraceData, TRC_CFG_RTT_BUFFER_SIZE_UP, TRC_CFG_RTT_MODE ); \ + SEGGER_RTT_ConfigDownBuffer(TRC_CFG_RTT_DOWN_BUFFER_INDEX, "TzCtrl", _TzCtrlData, TRC_CFG_RTT_BUFFER_SIZE_DOWN, TRC_CFG_RTT_MODE); + +/* Important for the J-Link port, in most other ports this can be skipped (default is 1) */ +#define TRC_STREAM_PORT_USE_INTERNAL_BUFFER 0 + +#define TRC_STREAM_PORT_WRITE_DATA(_ptrData, _size, _ptrBytesWritten) writeToRTT(_ptrData, _size, _ptrBytesWritten) + +#define TRC_STREAM_PORT_READ_DATA(_ptrData, _size, _ptrBytesRead) readFromRTT(_ptrData, _size, _ptrBytesRead) + +#ifdef __cplusplus +} +#endif + +#endif /* TRC_STREAMING_PORT_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/Jlink_RTT/trcStreamingPort.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/Jlink_RTT/trcStreamingPort.c new file mode 100644 index 0000000..d279f83 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/Jlink_RTT/trcStreamingPort.c @@ -0,0 +1,44 @@ + +#include "trcRecorder.h" + +#if (TRC_USE_TRACEALYZER_RECORDER == 1) +#if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING) + +int32_t readFromRTT(void* ptrData, uint32_t size, int32_t* ptrBytesRead) +{ + uint32_t bytesRead = 0; + + if (SEGGER_RTT_HASDATA(TRC_CFG_RTT_DOWN_BUFFER_INDEX)) + { + bytesRead = SEGGER_RTT_Read((TRC_CFG_RTT_DOWN_BUFFER_INDEX), (char*)ptrData, size); + + if (ptrBytesRead != NULL) + *ptrBytesRead = (int32_t)bytesRead; + + if (bytesRead != size) + { + return -1; + } + + } + + return 0; +} + +int32_t writeToRTT(void* ptrData, uint32_t size, int32_t* ptrBytesWritten) +{ + uint32_t bytesWritten = SEGGER_RTT_Write((TRC_CFG_RTT_UP_BUFFER_INDEX), (const char*)ptrData, size); + + if (ptrBytesWritten != NULL) + *ptrBytesWritten = (int32_t)bytesWritten; + + if (bytesWritten != size) + { + return -1; + } + + return 0; +} + +#endif +#endif diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/TCPIP/Readme-Streamport.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/TCPIP/Readme-Streamport.txt new file mode 100644 index 0000000..f8f097b --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/TCPIP/Readme-Streamport.txt @@ -0,0 +1,22 @@ +Tracealyzer Stream Port for TCP/IP (lwIP example) +------------------------------------------------- + +This directory contains a "stream port" for the Tracealyzer recorder library, +i.e., the specific code needed to use a particular interface for streaming a +Tracealyzer RTOS trace. The stream port is defined by a set of macros in +trcStreamingPort.h, found in the "include" directory. + +This particular stream port targets TCP/IP. This example assumes lwIP but is +easy to modify for other TCP/IP stacks. + +To use this stream port, make sure that include/trcStreamingPort.h is found +by the compiler (i.e., add this folder to your project's include paths) and +add all included source files to your build. Make sure no other versions of +trcStreamingPort.h are included by mistake! + +Note that lwIP is not included, but assumed to exist in the project already. + +See also http://percepio.com/2016/10/05/rtos-tracing. + +Percepio AB +www.percepio.com \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/TCPIP/include/trcStreamingPort.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/TCPIP/include/trcStreamingPort.h new file mode 100644 index 0000000..51e52e8 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/TCPIP/include/trcStreamingPort.h @@ -0,0 +1,66 @@ +/******************************************************************************* + * Trace Recorder Library for Tracealyzer v4.1.5 + * Percepio AB, www.percepio.com + * + * trcStreamingPort.h + * + * The interface definitions for trace streaming ("stream ports"). + * This "stream port" sets up the recorder to use TCP/IP as streaming channel. + * The example is for lwIP. + * + * Terms of Use + * This file is part of the trace recorder library (RECORDER), which is the + * intellectual property of Percepio AB (PERCEPIO) and provided under a + * license as follows. + * The RECORDER may be used free of charge for the purpose of recording data + * intended for analysis in PERCEPIO products. It may not be used or modified + * for other purposes without explicit permission from PERCEPIO. + * You may distribute the RECORDER in its original source code form, assuming + * this text (terms of use, disclaimer, copyright notice) is unchanged. You are + * allowed to distribute the RECORDER with minor modifications intended for + * configuration or porting of the RECORDER, e.g., to allow using it on a + * specific processor, processor family or with a specific communication + * interface. Any such modifications should be documented directly below + * this comment block. + * + * Disclaimer + * The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty + * as to its use or performance. PERCEPIO does not and cannot warrant the + * performance or results you may obtain by using the RECORDER or documentation. + * PERCEPIO make no warranties, express or implied, as to noninfringement of + * third party rights, merchantability, or fitness for any particular purpose. + * In no event will PERCEPIO, its technology partners, or distributors be liable + * to you for any consequential, incidental or special damages, including any + * lost profits or lost savings, even if a representative of PERCEPIO has been + * advised of the possibility of such damages, or for any claim by any third + * party. Some jurisdictions do not allow the exclusion or limitation of + * incidental, consequential or special damages, or the exclusion of implied + * warranties or limitations on how long an implied warranty may last, so the + * above limitations may not apply to you. + * + * Tabs are used for indent in this file (1 tab = 4 spaces) + * + * Copyright Percepio AB, 2018. + * www.percepio.com + ******************************************************************************/ + +#ifndef TRC_STREAMING_PORT_H +#define TRC_STREAMING_PORT_H + +#ifdef __cplusplus +extern "C" { +#endif + +int32_t trcTcpRead(void* data, uint32_t size, int32_t *ptrBytesRead); + +int32_t trcTcpWrite(void* data, uint32_t size, int32_t *ptrBytesWritten); + +#define TRC_STREAM_PORT_READ_DATA(_ptrData, _size, _ptrBytesRead) trcTcpRead(_ptrData, _size, _ptrBytesRead) + +#define TRC_STREAM_PORT_WRITE_DATA(_ptrData, _size, _ptrBytesSent) trcTcpWrite(_ptrData, _size, _ptrBytesSent) + +#ifdef __cplusplus +} +#endif + +#endif /* TRC_STREAMING_PORT_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/TCPIP/trcStreamingPort.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/TCPIP/trcStreamingPort.c new file mode 100644 index 0000000..d420d12 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/TCPIP/trcStreamingPort.c @@ -0,0 +1,186 @@ +/******************************************************************************* + * Trace Recorder Library for Tracealyzer v4.1.5 + * Percepio AB, www.percepio.com + * + * trcStreamingPort.c + * + * Supporting functions for trace streaming, used by the "stream ports" + * for reading and writing data to the interface. + * Existing ports can easily be modified to fit another setup, e.g., a + * different TCP/IP stack, or to define your own stream port. + * + * Terms of Use + * This file is part of the trace recorder library (RECORDER), which is the + * intellectual property of Percepio AB (PERCEPIO) and provided under a + * license as follows. + * The RECORDER may be used free of charge for the purpose of recording data + * intended for analysis in PERCEPIO products. It may not be used or modified + * for other purposes without explicit permission from PERCEPIO. + * You may distribute the RECORDER in its original source code form, assuming + * this text (terms of use, disclaimer, copyright notice) is unchanged. You are + * allowed to distribute the RECORDER with minor modifications intended for + * configuration or porting of the RECORDER, e.g., to allow using it on a + * specific processor, processor family or with a specific communication + * interface. Any such modifications should be documented directly below + * this comment block. + * + * Disclaimer + * The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty + * as to its use or performance. PERCEPIO does not and cannot warrant the + * performance or results you may obtain by using the RECORDER or documentation. + * PERCEPIO make no warranties, express or implied, as to noninfringement of + * third party rights, merchantability, or fitness for any particular purpose. + * In no event will PERCEPIO, its technology partners, or distributors be liable + * to you for any consequential, incidental or special damages, including any + * lost profits or lost savings, even if a representative of PERCEPIO has been + * advised of the possibility of such damages, or for any claim by any third + * party. Some jurisdictions do not allow the exclusion or limitation of + * incidental, consequential or special damages, or the exclusion of implied + * warranties or limitations on how long an implied warranty may last, so the + * above limitations may not apply to you. + * + * Tabs are used for indent in this file (1 tab = 4 spaces) + * + * Copyright Percepio AB, 2018. + * www.percepio.com + ******************************************************************************/ + +#include "trcRecorder.h" + +#if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING) +#if (TRC_USE_TRACEALYZER_RECORDER == 1) + +/* TCP/IP includes - for lwIP in this case */ +#include "lwip/tcpip.h" +#include "lwip/sockets.h" + +int errno; + +#define TRC_TCPIP_PORT 12000 + +int sock = -1, new_sd = -1; +int flags = 0; +int remoteSize; +struct sockaddr_in address, remote; + +int32_t trcSocketSend( void* data, int32_t size, int32_t* bytesWritten ) +{ + if (new_sd < 0) + return -1; + + if (bytesWritten == NULL) + return -1; + + *bytesWritten = send( new_sd, data, size, 0 ); + if (*bytesWritten < 0) + { + /* EWOULDBLOCK may be expected when buffers are full */ + if (errno != 0 && errno != EWOULDBLOCK) + { + closesocket(new_sd); + new_sd = -1; + return -1; + } + else + *bytesWritten = 0; + } + + return 0; +} + +int32_t trcSocketReceive( void* data, int32_t size, int32_t* bytesRead ) +{ + if (new_sd < 0) + return -1; + + *bytesRead = recv( new_sd, data, size, 0 ); + if ( *bytesRead < 0 ) + { + /* EWOULDBLOCK may be expected when there is no data to receive */ + if (errno != 0 && errno != EWOULDBLOCK) + { + closesocket(new_sd); + new_sd = -1; + return -1; + } + else + *bytesRead = 0; + } + + return 0; +} + +int32_t trcSocketInitializeListener() +{ + if (sock >= 0) + return 0; + + sock = lwip_socket(AF_INET, SOCK_STREAM, 0); + + if (sock < 0) + return -1; + + address.sin_family = AF_INET; + address.sin_port = htons( TRC_TCPIP_PORT ); + address.sin_addr.s_addr = INADDR_ANY; + + if (bind(sock, (struct sockaddr *)&address, sizeof (address)) < 0) + { + closesocket(sock); + sock = -1; + return -1; + } + + if (lwip_listen(sock, 5) < 0) + { + closesocket(sock); + sock = -1; + return -1; + } + + return 0; +} + +int32_t trcSocketAccept() +{ + if (sock < 0) + return -1; + + if (new_sd >= 0) + return 0; + + remoteSize = sizeof( remote ); + new_sd = accept( sock, (struct sockaddr *)&remote, (socklen_t*)&remoteSize ); + + flags = fcntl( new_sd, F_GETFL, 0 ); + fcntl( new_sd, F_SETFL, flags | O_NONBLOCK ); + + if( new_sd < 0 ) + { + closesocket(new_sd); + new_sd = -1; + closesocket(sock); + sock = -1; + return -1; + } + + return 0; +} +/************** MODIFY THE ABOVE PART TO USE YOUR TPC/IP STACK ****************/ + +int32_t trcTcpWrite(void* data, uint32_t size, int32_t *ptrBytesWritten) +{ + return trcSocketSend(data, size, ptrBytesWritten); +} + +int32_t trcTcpRead(void* data, uint32_t size, int32_t *ptrBytesRead) +{ + trcSocketInitializeListener(); + + trcSocketAccept(); + + return trcSocketReceive(data, size, ptrBytesRead); +} + +#endif /*(TRC_USE_TRACEALYZER_RECORDER == 1)*/ +#endif /*(TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING)*/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/USB_CDC/Readme-Streamport.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/USB_CDC/Readme-Streamport.txt new file mode 100644 index 0000000..260f12a --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/USB_CDC/Readme-Streamport.txt @@ -0,0 +1,27 @@ +Tracealyzer Stream Port for USB CDC (STM32 example) +--------------------------------------------------- + +This directory contains a "stream port" for the Tracealyzer recorder library, +i.e., the specific code needed to use a particular interface for streaming a +Tracealyzer RTOS trace. The stream port is defined by a set of macros in +trcStreamingPort.h, found in the "include" directory. + +This particular stream port targets USB CDC. This is an example for the STM32 USB +stack (from the STM32CubeMX code generation tool, v1.4.1) and has been tested on +a STM32F767ZI device on a Nucleo board. See this blog post: + +http://percepio.com/2017/02/03/usb-trace-streaming-st-nucleo-f767zi-board/ + +However, it should be straight-forward to modify this for other USB stacks. + +To use this stream port, make sure that include/trcStreamingPort.h is found +by the compiler (i.e., add this folder to your project's include paths) and +add all included source files to your build. Make sure no other versions of +trcStreamingPort.h are included by mistake! + +Note that the USB stack not included, but assumed to exist in the project already. + +See also http://percepio.com/2016/10/05/rtos-tracing. + +Percepio AB +www.percepio.com \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/USB_CDC/include/trcStreamingPort.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/USB_CDC/include/trcStreamingPort.h new file mode 100644 index 0000000..6940b4d --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/USB_CDC/include/trcStreamingPort.h @@ -0,0 +1,83 @@ +/******************************************************************************* + * Trace Recorder Library for Tracealyzer v4.1.5 + * Percepio AB, www.percepio.com + * + * trcStreamingPort.h + * + * The interface definitions for trace streaming ("stream ports"). + * This "stream port" sets up the recorder to use USB CDC as streaming channel. + * The example is for STM32 using STM32Cube. + * + * Terms of Use + * This file is part of the trace recorder library (RECORDER), which is the + * intellectual property of Percepio AB (PERCEPIO) and provided under a + * license as follows. + * The RECORDER may be used free of charge for the purpose of recording data + * intended for analysis in PERCEPIO products. It may not be used or modified + * for other purposes without explicit permission from PERCEPIO. + * You may distribute the RECORDER in its original source code form, assuming + * this text (terms of use, disclaimer, copyright notice) is unchanged. You are + * allowed to distribute the RECORDER with minor modifications intended for + * configuration or porting of the RECORDER, e.g., to allow using it on a + * specific processor, processor family or with a specific communication + * interface. Any such modifications should be documented directly below + * this comment block. + * + * Disclaimer + * The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty + * as to its use or performance. PERCEPIO does not and cannot warrant the + * performance or results you may obtain by using the RECORDER or documentation. + * PERCEPIO make no warranties, express or implied, as to noninfringement of + * third party rights, merchantability, or fitness for any particular purpose. + * In no event will PERCEPIO, its technology partners, or distributors be liable + * to you for any consequential, incidental or special damages, including any + * lost profits or lost savings, even if a representative of PERCEPIO has been + * advised of the possibility of such damages, or for any claim by any third + * party. Some jurisdictions do not allow the exclusion or limitation of + * incidental, consequential or special damages, or the exclusion of implied + * warranties or limitations on how long an implied warranty may last, so the + * above limitations may not apply to you. + * + * Tabs are used for indent in this file (1 tab = 4 spaces) + * + * Copyright Percepio AB, 2018. + * www.percepio.com + ******************************************************************************/ + +#ifndef TRC_STREAMING_PORT_H +#define TRC_STREAMING_PORT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Include files as needed, in this case it is files from STM32Cube FW_F7 V1.4.1 */ +#include "usb_device.h" +#include "usbd_cdc.h" +#include "usbd_CDC_if.h" +#include "usb_device.h" + +/* Tested on STM32 devices using Keil/CMSIS USB stack */ + +extern USBD_CDC_ItfTypeDef USBD_Interface_fops_FS; + +uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len); + +int32_t trcCDCReceive(void *data, uint32_t size, int32_t* NumBytes); + +int32_t trcCDCTransmit(void* data, uint32_t size, int32_t * noOfBytesSent ); + +#define TRC_STREAM_PORT_INIT() \ + MX_USB_DEVICE_Init(); \ + TRC_STREAM_PORT_MALLOC(); /*Dynamic allocation or empty if static */ + +#define TRC_STREAM_PORT_READ_DATA(_ptrData, _size, _ptrBytesRead) trcCDCReceive(_ptrData, _size, _ptrBytesRead) + +#define TRC_STREAM_PORT_WRITE_DATA(_ptrData, _size, _ptrBytesSent) trcCDCTransmit(_ptrData, _size, _ptrBytesSent) + + +#ifdef __cplusplus +} +#endif + +#endif /* TRC_STREAMING_PORT_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/USB_CDC/trcStreamingPort.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/USB_CDC/trcStreamingPort.c new file mode 100644 index 0000000..800022a --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/streamports/USB_CDC/trcStreamingPort.c @@ -0,0 +1,246 @@ + +#include "trcRecorder.h" + +#if (TRC_USE_TRACEALYZER_RECORDER == 1) +#if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING) + +#include "stdint.h" + +/* Include files as needed, in this case it is files from STM32Cube FW_F7 V1.4.1 */ +#include "usb_device.h" +#include "usbd_cdc.h" +#include "usbd_CDC_if.h" +#include "usb_device.h" + +#define BUFSIZE 64 + +typedef struct{ + uint32_t idx; + uint8_t data[BUFSIZE]; +}recBuf; + +/* Define size for the receive and transmit buffer over CDC */ +#define APP_RX_DATA_SIZE 8 +#define APP_TX_DATA_SIZE 64 + +/* Received Data over USB are stored in this buffer */ +uint8_t UserRxBufferFS[APP_RX_DATA_SIZE]; + +/* Send Data over USB CDC are stored in this buffer */ +uint8_t UserTxBufferFS[APP_TX_DATA_SIZE]; + +extern USBD_HandleTypeDef hUsbDeviceFS; + +extern PCD_HandleTypeDef hpcd_USB_OTG_FS; + +recBuf commandBuffer; + +static int8_t CDC_Init_FS (void); +static int8_t CDC_DeInit_FS (void); +static int8_t CDC_Control_FS (uint8_t cmd, uint8_t* pbuf, uint16_t length); +static int8_t CDC_Receive_FS (uint8_t* pbuf, uint32_t *Len); + +USBD_CDC_ItfTypeDef USBD_Interface_fops_FS = +{ + CDC_Init_FS, + CDC_DeInit_FS, + CDC_Control_FS, + CDC_Receive_FS +}; + +/* Private functions ---------------------------------------------------------*/ +/** + * @brief CDC_Init_FS + * Initializes the CDC media low layer over the FS USB IP + * @param None + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_Init_FS(void) +{ + /* Set Application Buffers */ + USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0); + USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS); + return (USBD_OK); +} + +/** + * @brief CDC_DeInit_FS + * DeInitializes the CDC media low layer + * @param None + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_DeInit_FS(void) +{ + return (USBD_OK); +} + +/** + * @brief CDC_Control_FS + * Manage the CDC class requests + * @param cmd: Command code + * @param pbuf: Buffer containing command data (request parameters) + * @param length: Number of data to be sent (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_Control_FS (uint8_t cmd, uint8_t* pbuf, uint16_t length) +{ + switch (cmd) + { + case CDC_SEND_ENCAPSULATED_COMMAND: + break; + + case CDC_GET_ENCAPSULATED_RESPONSE: + break; + + case CDC_SET_COMM_FEATURE: + break; + + case CDC_GET_COMM_FEATURE: + break; + + case CDC_CLEAR_COMM_FEATURE: + break; + + /*******************************************************************************/ + /* Line Coding Structure */ + /*-----------------------------------------------------------------------------*/ + /* Offset | Field | Size | Value | Description */ + /* 0 | dwDTERate | 4 | Number |Data terminal rate, in bits per second*/ + /* 4 | bCharFormat | 1 | Number | Stop bits */ + /* 0 - 1 Stop bit */ + /* 1 - 1.5 Stop bits */ + /* 2 - 2 Stop bits */ + /* 5 | bParityType | 1 | Number | Parity */ + /* 0 - None */ + /* 1 - Odd */ + /* 2 - Even */ + /* 3 - Mark */ + /* 4 - Space */ + /* 6 | bDataBits | 1 | Number Data bits (5, 6, 7, 8 or 16). */ + /*******************************************************************************/ + case CDC_SET_LINE_CODING: + break; + + case CDC_GET_LINE_CODING: + break; + + case CDC_SET_CONTROL_LINE_STATE: + break; + + case CDC_SEND_BREAK: + break; + + default: + break; + } + return (USBD_OK); +} + +/** + * @brief CDC_Receive_FS + * Data received over USB OUT endpoint are sent over CDC interface + * through this function. + * + * @note + * This function will block any OUT packet reception on USB endpoint + * until exiting this function. If you exit this function before transfer + * is complete on CDC interface (i.e. using DMA controller) it will result + * in receiving more data while previous ones are still not sent. + * + * @param Buf: Buffer of data to be received + * @param Len: Number of data received (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_Receive_FS (uint8_t* Buf, uint32_t *Len) +{ + for( uint32_t i=0;i<* Len;i++) + { + commandBuffer.data[commandBuffer.idx]=Buf[i]; + commandBuffer.idx++; + } + USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]); + USBD_CDC_ReceivePacket(&hUsbDeviceFS); + + return (USBD_OK); +} + +/** + * @brief CDC_Transmit_FS + * Data send over USB IN endpoint are sent over CDC interface + * through this function. + * @note + * + * + * @param Buf: Buffer of data to be send + * @param Len: Number of data to be send (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY + */ +uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len) +{ + uint8_t result = USBD_OK; + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData; + if (hcdc->TxState != 0){ + return USBD_BUSY; + } + USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len); + result = USBD_CDC_TransmitPacket(&hUsbDeviceFS); + return result; +} + +/* The READ function, used in trcStreamingPort.h */ +int32_t trcCDCReceive(void *data, uint32_t size, int32_t* NumBytes) +{ + uint32_t i,diff; + + if(commandBuffer.idx>0) + { + if (size >= commandBuffer.idx) // more than what is stored, number of bytes will be .idx + { + memcpy(data,commandBuffer.data, commandBuffer.idx); + *NumBytes=commandBuffer.idx; + commandBuffer.idx=0; // Make the buffer ready for a new command + } + else //If some data in the buffer is not read + { + diff = commandBuffer.idx-size; + memcpy(data,commandBuffer.data, size); + for(i=0;i v4.1.5 + +- Fixed a bug in the ITM stream port, that required Port 0 to be enabled. +- Added missing include of stdio.h (needed by vTraceConsoleChannelPrintF). +- Moved standard includes from trcRecorder.h into the .c files needing them. + +------------------------------------------------------------------------------- + +Changes, v4.1.2 -> v4.1.4 + +- Fixed a compile error when certain FreeRTOS settings were used +- Disabled filter support for FreeRTOS v7.3 since it uses "char" for object id + +------------------------------------------------------------------------------- + +Changes, v4.1.0 -> v4.1.2 + +- Added vTraceConsoleChannelPrintF(...) + +------------------------------------------------------------------------------- + +Changes, v4.0.3 -> v4.1.0 + +- Improved performance of User Events +- Fixed handling of format strings ending with '%' +- Improved handling of creative user configuration macros + +------------------------------------------------------------------------------- + +Changes, v4.0.2 -> v4.0.3 + +- Minor fix for TCP/IP stream port. +- Corrected default RTT mode setting. + +------------------------------------------------------------------------------- + +Changes, v4.0.1 -> v4.0.2 + +- Memory allocation trace events now ignore filters. + +------------------------------------------------------------------------------- + +Changes, v4.0.0 -> v4.0.1 + +- Minor fixes to default values. + +------------------------------------------------------------------------------- + +Changes, v3.3.0 -> v4.0.0 + +- Fixed some issues with filters. + +------------------------------------------------------------------------------- + +Changes, v3.2.0 -> v3.3.0 + +- Added support for FreeRTOS v10, including the new object types Message Buffer + and Stream Buffer. + +- Improved the object-level filtering to also support Timer, Event Group, + Message Buffer and Stream Buffer objects. + +- Fixed a few remaining build problems with older FreeRTOS versions (v7.x). + +- vTraceStoreISRBegin now reports an error on invalid handles, i.e., if the + initialization of the handle (xTraceSetISRProperties) had not been made. + +------------------------------------------------------------------------------- + +Changes, v3.1.2 -> v3.2.0 + +- Added new filtering system - that works in both snapshot and streaming mode. + Filtering was previously not supported in streaming mode, but can be very + useful for slower streaming interfaces. By exluding irrelevant events, the + amount of data produced can be reduced a lot. + + * New functions vTraceSetFilterGroup and vTraceSetFilterMask allows for + excluding all events from specific objects (like a semaphore or queue). + + * Added new "generic" filters (preprocessor level) to trcConfig.h, that + exclude all events of a particular types. + - TRC_CFG_INCLUDE_NOTIFY_EVENTS + - TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS + - TRC_CFG_INCLUDE_PEND_FUNC_CALL_EVENTS + - TRC_CFG_INCLUDE_TIMER_EVENTS + + * Upgraded some previous filters from "Snapshot only" to the Common API + and thereby moved them from trcSnapshotConfig.h to trcConfig.h. + - TRC_CFG_SCHEDULING_ONLY + - TRC_CFG_INCLUDE_MEMMANG_EVENTS + - TRC_CFG_INCLUDE_USER_EVENTS + - TRC_CFG_INCLUDE_ISR_TRACING + - TRC_CFG_INCLUDE_READY_EVENTS + - TRC_CFG_INCLUDE_OSTICK_EVENTS + + * Removed the old filter system from trcSnapshotRecorder.c. + +- Improved streaming interface - Now only two (2) macros are needed to be + defined in most cases, read and write. This makes it a lot easier to make + custom stream ports. + + * Many definitions that were identical in most stream ports, have been + replaced by default definitions in the recorder core. If needed, they + can be overriden by custom definitions in trcStreamingPort.h. + + * Stream ports are now assumed to use recorder's internal event buffer. + Other stream ports that writes directly to the streaming interface + (like J-Link) should define TRC_STREAM_PORT_USE_INTERNAL_BUFFER + as zero (0) to make it work correctly. + + * Macro TRC_STREAM_PORT_PERIODIC_SEND_DATA has been replaced by + TRC_STREAM_PORT_WRITE_DATA. Together with TRC_STREAM_PORT_READ_DATA, + this is all that is necessary for a typical stream port. + + * Return values from the stream port macros READ_DATA and WRITE_DATA are + now checked. Expects 0 on success, anything else produces a warning + that can be retrived using xTraceGetLastError() and also seen in + Tracealyzer if a trace was produced. + + * Stream ports should no longer call prvPagedEventBufferInit explicitly + (e.g. in TRC_STREAM_PORT_ON_TRACE_BEGIN). This is now called + automatically if TRC_STREAM_PORT_USE_INTERNAL_BUFFER == 1. + + * Macros TRC_STREAM_PORT_ON_TRACE_BEGIN and TRC_STREAM_PORT_ON_TRACE_END + are now unused by default and don't need to be defined. + You can however use them to hook in some own function at these events. + +- Added two new stream ports + + * TCPIP-Win32: allows for testing the streaming on Windows ports of your + RTOS, using Winsock. + + * File: example of streaming to a local file system (tested on Windows, + but easy to modify). + +- Added support for FreeRTOS v9.0.1 + + * Replaced FreeRTOS version code TRC_FREERTOS_VERSION_9_X with + - TRC_FREERTOS_VERSION_9_0_0 + - TRC_FREERTOS_VERSION_9_0_1 + + * Using TRC_FREERTOS_VERSION_9_X is no longer allowed. + +- Added additional events for xQueuePeek, for blocking and timeouts events. + +- Added event for traceTIMER_EXPIRED, showing when the timer callback + function is called. + +- Improved diagnostics in streaming mode, in case of errors in the recorder. + + * Added prvTraceWarning() - registers a "warning" error code, without + stopping the recorder. Called if READ_DATA or WRITE_DATA returns a + non-zero value, and in several other cases where the recorder + configuration is incorrect (e.g., too small symbol table). + + * Added several new warning codes (PSF_WARNING_XYZ), corresponding to the + issues detected by prvCheckRecorderStatus. + + * Fixed duplicate definitions of warning messages, so the warnings reported + to Tracealyzer are the same as those provided in xTraceGetLastError(). + + * Added better explainations of warning/error messages in the body of + xTraceGetLastError (in streaming mode). + +- Added xTraceIsRecordingEnabled() to Common API. + +- Added "unofficial" hardware port for Altera Nios-II. + This is a user contribition, not yet verified by Percerpio. + +- Fixed bug in vTraceEnable - option TRC_START_AWAIT_HOST was ignored if already initialized. + +- Fixed a few remaining compiler warnings. + +- Changed order of some settings in trcConfig.h - moved advanced stuff to the + bottom. + +- Removed SEGGER_RTT_Printf.c from the J-Link stream port since not required + for Tracealyzer. + +------------------------------------------------------------------------------- + +Changes, v3.1.1 -> v3.1.2 +- Fixed two bugs related to User Events, one in vTracePrintF and other in vTracePrint. + +- Fixed a build problem related to a single reference of the old FreeRTOS type "xTaskHandle", in trcKernelPort.c. + Changed to "TaskHandle_t", unless if using an older FreeRTOS kernel or the "compatibility mode". + +- Removed traceCREATE_MUTEX hook for FreeRTOS v9 or later (no longer required) + +- Updated the User Manual regarding snapshot trace via IAR Embedded Workbench. + +- Renamed vTraceGetTraceBuffer to xTraceGetTraceBuffer, since returning a pointer. + +------------------------------------------------------------------------------- + +Changes, v3.1.0 -> v3.1.1 + +After the major changes in the v3.1.0 trace recorder library, this update +corrects a number of minor issues. Only minor functional improvements. + +- You can now use TRC_ALLOC_CUSTOM_BUFFER to declare a trace buffer on a custom + location (using linker directives). + The related function vTraceSetRecorderDataBuffer has been promoted to the + Common API (previously only supported in snapshot mode, but custom allocation + is now generally supported also in streaming mode). + +- Removed TRC_CFG_USE_LINKER_PRAGMA. No longer necessary thanks to the custom + allocation mode. + +- Added support for timestamping from custom periodic timers, required for + accurate timestamping on Cortex-M0/M0+ devices when using tickless idle. + Only for streaming mode so far. See TRC_CUSTOM_TIMER_INCR / DECR. + +- ARM Cortex-M port: Made sure the DWT unit is initialized properly, in case + the debugger doesn't handle this. + +- ARM Cortex-M port: Added possibility to use Systick timestamping also on + Cortex-M3/M4/M7 devices (that otherwise use DWT timestamping by default). + To use this option, define the macro TRC_CFG_ARM_CM_USE_SYSTICK. + +- J-Link streaming: The default RTT buffer has been changed from 0 to 1. + +- J-Link streaming: The RTT buffer settings for buffer 1 and higher, are now + found in trcStreamingPort.h. Note: These settings don't apply to buffer 0. + +- vTracePrint has been optimized for better performance in string logging. + +- Minor performance improvement related to symbol table transfer in streaming mode. + +- Timer names now registered also in streaming mode. + +- Timer start and stop event are now traced. + +- Implemented support for queue registry (traceQUEUE_REGISTRY_ADD) also for streaming. + +- Fixed a bug related to repeated calls of vTraceEnable. + +- Fixed a bug where task-switches seemed to occur even though the scheduler was disabled. + +- Renamed HARDWARE_PORT_TEXAS_INSTRUMENTS_TMS570_RM48, added prefix TRC. + +- Fixed several language issues in the comments and documentation. + +- Fixed several minor issues and warnings from different compilers + (including PowerPC/gcc) and configurations. + +------------------------------------------------------------------------------- + +Changes, v3.0.9 -> v3.1.0 + +- Merge of previously separated snapshot and streaming recorders into a single + recorder supporting both streaming and snapshot as different modes. + +- New common API for supporting both streaming and snapshot modes. + +- New integration guide, see the User Manual. + +- Major improvement of API documentation in source files and User Manual. + +- New concept of "stream ports", giving a better structure defining streaming + interfaces, and restructured the J-Link and TCP/IP streaming as stream ports. + +- Added a stream port for USB CDC connections, with STM32 as example. + Since Tracealyzer now can receive serial data on Windows COM ports, this is + really easy to use. + +- Added a warning (#error) for cases where FreeRTOS tickless idle mode is used + together with timestamping using SysTick or other periodic interrupt timers, + Tracing with tickless idle requires an independent time source to correctly + capture the length of the idle periods. + +- Major changes in the recorder API. Important examples are: + + * Some configuration macros have changed names, e.g. for "hardware port". + Make sure to remove any old "trcConfig.h" files if upgrading from an + earlier version! + + * Recorder configuration in trcConfig.h has been minimized and now only + includes the important settings that are independent of recorder mode. + Advanced settings for each mode are found in trcSnapshotConfig.h and + trcStreamingConfig.h. + + * vTraceEnable replaces Trace_Init and vTraceInitTraceData, as well as + vTraceStart and uiTraceStart. + + * vTraceStop now part of the common API and thereby available also in + streaming. And since vTraceEnable can start the streaming directly + you have the option control the tracing from target, e.g., for + streaming to a device file system. + + * vTraceStoreKernelObjectName from old streaming recorder has been replaced + by vTraceSetQueueName, vTraceSetSemaphoreName, etc. + + * vTraceSetISRProperties now returns a "traceHandle" that should be passed as + parameter to vTraceStoreISRBegin and vTraceStoreISREnd. + + * xTraceRegisterString has replaced the old functions xTraceOpenLabel and + vTraceStoreUserEventChannelName. This now returns a "traceString" for use + as "channel" parameter in vTracePrintF, and in other places where strings + are stored. + + * Removed vTraceStoreISREndManual and vTraceStoreISREndAuto, use + vTraceStoreISREnd instead. + + * Renamed the functions for saving User Events in a separate buffer: + - xTraceRegisterChannelFormat -> xTraceRegisterUBChannel + - vTraceChannelPrintF -> vTraceUBData + - vTraceChannelUserEvent -> vTraceUBEvent + + +------------------------------------------------------------------------------- +Copyright Percepio AB, 2018. \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/trcKernelPort.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/trcKernelPort.c new file mode 100644 index 0000000..d41b526 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/trcKernelPort.c @@ -0,0 +1,833 @@ +/******************************************************************************* + * Trace Recorder Library for Tracealyzer v4.1.5 + * Percepio AB, www.percepio.com + * + * trcKernelPort.c + * + * The FreeRTOS-specific parts of the trace recorder + * + * Terms of Use + * This file is part of the trace recorder library (RECORDER), which is the + * intellectual property of Percepio AB (PERCEPIO) and provided under a + * license as follows. + * The RECORDER may be used free of charge for the purpose of recording data + * intended for analysis in PERCEPIO products. It may not be used or modified + * for other purposes without explicit permission from PERCEPIO. + * You may distribute the RECORDER in its original source code form, assuming + * this text (terms of use, disclaimer, copyright notice) is unchanged. You are + * allowed to distribute the RECORDER with minor modifications intended for + * configuration or porting of the RECORDER, e.g., to allow using it on a + * specific processor, processor family or with a specific communication + * interface. Any such modifications should be documented directly below + * this comment block. + * + * Disclaimer + * The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty + * as to its use or performance. PERCEPIO does not and cannot warrant the + * performance or results you may obtain by using the RECORDER or documentation. + * PERCEPIO make no warranties, express or implied, as to noninfringement of + * third party rights, merchantability, or fitness for any particular purpose. + * In no event will PERCEPIO, its technology partners, or distributors be liable + * to you for any consequential, incidental or special damages, including any + * lost profits or lost savings, even if a representative of PERCEPIO has been + * advised of the possibility of such damages, or for any claim by any third + * party. Some jurisdictions do not allow the exclusion or limitation of + * incidental, consequential or special damages, or the exclusion of implied + * warranties or limitations on how long an implied warranty may last, so the + * above limitations may not apply to you. + * + * Tabs are used for indent in this file (1 tab = 4 spaces) + * + * Copyright Percepio AB, 2018. + * www.percepio.com + ******************************************************************************/ + +#include "FreeRTOS.h" + +#if (!defined(TRC_USE_TRACEALYZER_RECORDER) && configUSE_TRACE_FACILITY == 1) +#error Trace Recorder: You need to include trcRecorder.h at the end of your FreeRTOSConfig.h! +#endif + +#if (defined(TRC_USE_TRACEALYZER_RECORDER) && TRC_USE_TRACEALYZER_RECORDER == 1) + +#ifndef TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS + /* TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS is missing in trcConfig.h. */ +#error "TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS must be defined in trcConfig.h." +#endif + +#ifndef TRC_CFG_INCLUDE_TIMER_EVENTS + /* TRC_CFG_INCLUDE_TIMER_EVENTS is missing in trcConfig.h. */ +#error "TRC_CFG_INCLUDE_TIMER_EVENTS must be defined in trcConfig.h." +#endif + +#ifndef TRC_CFG_INCLUDE_PEND_FUNC_CALL_EVENTS + /* TRC_CFG_INCLUDE_PEND_FUNC_CALL_EVENTS is missing in trcConfig.h. */ +#error "TRC_CFG_INCLUDE_PEND_FUNC_CALL_EVENTS must be defined in trcConfig.h." +#endif + +#ifndef TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS + /* TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS is missing in trcConfig.h. Define this as 1 if using FreeRTOS v10 or later and like to trace stream buffer or message buffer events, otherwise 0. */ +#error "TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS must be defined in trcConfig.h." +#endif + +#if (configUSE_TICKLESS_IDLE != 0 && (TRC_HWTC_TYPE == TRC_OS_TIMER_INCR || TRC_HWTC_TYPE == TRC_OS_TIMER_DECR)) + /* + The below error message is to alert you on the following issue: + + The hardware port selected in trcConfig.h uses the operating system timer for the + timestamping, i.e., the periodic interrupt timer that drives the OS tick interrupt. + + When using "tickless idle" mode, the recorder needs an independent time source in + order to correctly record the durations of the idle times. Otherwise, the trace may appear + to have a different length than in reality, and the reported CPU load is also affected. + + You may override this warning by defining the TRC_CFG_ACKNOWLEDGE_TICKLESS_IDLE_WARNING + macro in your trcConfig.h file. But then the time scale may be incorrect during + tickless idle periods. + + To get this correct, override the default timestamping by setting TRC_CFG_HARDWARE_PORT + in trcConfig.h to TRC_HARDWARE_PORT_APPLICATION_DEFINED and define the HWTC macros + accordingly, using a free running counter or an independent periodic interrupt timer. + See trcHardwarePort.h for details. + + For ARM Cortex-M3, M4 and M7 MCUs this is not an issue, since the recorder uses the + DWT cycle counter for timestamping in these cases. + */ + + #ifndef TRC_CFG_ACKNOWLEDGE_TICKLESS_IDLE_WARNING + #error Trace Recorder: This timestamping mode is not recommended with Tickless Idle. + #endif +#endif /* (configUSE_TICKLESS_IDLE != 0 && (TRC_HWTC_TYPE == TRC_OS_TIMER_INCR || TRC_HWTC_TYPE == TRC_OS_TIMER_DECR)) */ + +#include "task.h" +#include "queue.h" + +#if (TRC_CFG_INCLUDE_TIMER_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_8_X) +/* If the project does not include the FreeRTOS timers, TRC_CFG_INCLUDE_TIMER_EVENTS must be set to 0 */ +#include "timers.h" +#endif /* (TRC_CFG_INCLUDE_TIMER_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_8_X) */ + +#if (TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_8_X) +/* If the project does not include the FreeRTOS event groups, TRC_CFG_INCLUDE_TIMER_EVENTS must be set to 0 */ +#include "event_groups.h" +#endif /* (TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_8_X) */ + +#if (TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) +/* If the project does not include the FreeRTOS stream buffers, TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS must be set to 0 */ +#include "stream_buffer.h" +#endif /* (TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) */ + +uint32_t prvTraceGetQueueNumber(void* handle); + +#if (TRC_CFG_FREERTOS_VERSION < TRC_FREERTOS_VERSION_8_X) + +extern unsigned char ucQueueGetQueueNumber( xQueueHandle pxQueue ); +extern void vQueueSetQueueNumber( xQueueHandle pxQueue, unsigned char ucQueueNumber ); +extern unsigned char ucQueueGetQueueType( xQueueHandle pxQueue ); + +uint32_t prvTraceGetQueueNumber(void* handle) +{ + return (uint32_t)ucQueueGetQueueNumber(handle); +} +#else +uint32_t prvTraceGetQueueNumber(void* handle) +{ + return (uint32_t)uxQueueGetQueueNumber(handle); +} +#endif /* (TRC_CFG_FREERTOS_VERSION < TRC_FREERTOS_VERSION_8_X) */ + +uint8_t prvTraceGetQueueType(void* handle) +{ + // This is either declared in header file in FreeRTOS 8 and later, or as extern above + return ucQueueGetQueueType(handle); +} + +/* Tasks */ +uint16_t prvTraceGetTaskNumberLow16(void* handle) +{ + return TRACE_GET_LOW16(uxTaskGetTaskNumber(handle)); +} + +uint16_t prvTraceGetTaskNumberHigh16(void* handle) +{ + return TRACE_GET_HIGH16(uxTaskGetTaskNumber(handle)); +} + +void prvTraceSetTaskNumberLow16(void* handle, uint16_t value) +{ + vTaskSetTaskNumber(handle, TRACE_SET_LOW16(uxTaskGetTaskNumber(handle), value)); +} + +void prvTraceSetTaskNumberHigh16(void* handle, uint16_t value) +{ + vTaskSetTaskNumber(handle, TRACE_SET_HIGH16(uxTaskGetTaskNumber(handle), value)); +} + +uint16_t prvTraceGetQueueNumberLow16(void* handle) +{ + return TRACE_GET_LOW16(prvTraceGetQueueNumber(handle)); +} + +uint16_t prvTraceGetQueueNumberHigh16(void* handle) +{ + return TRACE_GET_HIGH16(prvTraceGetQueueNumber(handle)); +} + +void prvTraceSetQueueNumberLow16(void* handle, uint16_t value) +{ + vQueueSetQueueNumber(handle, TRACE_SET_LOW16(prvTraceGetQueueNumber(handle), value)); +} + +void prvTraceSetQueueNumberHigh16(void* handle, uint16_t value) +{ + vQueueSetQueueNumber(handle, TRACE_SET_HIGH16(prvTraceGetQueueNumber(handle), value)); +} + +#if (TRC_CFG_INCLUDE_TIMER_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) + +uint16_t prvTraceGetTimerNumberLow16(void* handle) +{ + return TRACE_GET_LOW16(uxTimerGetTimerNumber(handle)); +} + +uint16_t prvTraceGetTimerNumberHigh16(void* handle) +{ + return TRACE_GET_HIGH16(uxTimerGetTimerNumber(handle)); +} + +void prvTraceSetTimerNumberLow16(void* handle, uint16_t value) +{ + vTimerSetTimerNumber(handle, TRACE_SET_LOW16(uxTimerGetTimerNumber(handle), value)); +} + +void prvTraceSetTimerNumberHigh16(void* handle, uint16_t value) +{ + vTimerSetTimerNumber(handle, TRACE_SET_HIGH16(uxTimerGetTimerNumber(handle), value)); +} +#endif /* (TRC_CFG_INCLUDE_TIMER_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) */ + +#if (TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) + +uint16_t prvTraceGetEventGroupNumberLow16(void* handle) +{ + return TRACE_GET_LOW16(uxEventGroupGetNumber(handle)); +} + +uint16_t prvTraceGetEventGroupNumberHigh16(void* handle) +{ + return TRACE_GET_HIGH16(uxEventGroupGetNumber(handle)); +} + +void prvTraceSetEventGroupNumberLow16(void* handle, uint16_t value) +{ + vEventGroupSetNumber(handle, TRACE_SET_LOW16(uxEventGroupGetNumber(handle), value)); +} + +void prvTraceSetEventGroupNumberHigh16(void* handle, uint16_t value) +{ + vEventGroupSetNumber(handle, TRACE_SET_HIGH16(uxEventGroupGetNumber(handle), value)); +} +#endif /* (TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) */ + +#if (TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) + +uint16_t prvTraceGetStreamBufferNumberLow16(void* handle) +{ + return TRACE_GET_LOW16(uxStreamBufferGetStreamBufferNumber(handle)); +} + +uint16_t prvTraceGetStreamBufferNumberHigh16(void* handle) +{ + return TRACE_GET_HIGH16(uxStreamBufferGetStreamBufferNumber(handle)); +} + +void prvTraceSetStreamBufferNumberLow16(void* handle, uint16_t value) +{ + vStreamBufferSetStreamBufferNumber(handle, TRACE_SET_LOW16(uxStreamBufferGetStreamBufferNumber(handle), value)); +} + +void prvTraceSetStreamBufferNumberHigh16(void* handle, uint16_t value) +{ + vStreamBufferSetStreamBufferNumber(handle, TRACE_SET_HIGH16(uxStreamBufferGetStreamBufferNumber(handle), value)); +} +#endif /* (TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) */ + +#if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING) + +static void* pCurrentTCB = NULL; +#if (defined(configENABLE_BACKWARD_COMPATIBILITY) && configENABLE_BACKWARD_COMPATIBILITY == 0) +/* We're explicitly not using compatibility mode */ +static TaskHandle_t HandleTzCtrl = NULL; /* TzCtrl task TCB */ +#else +/* We're using compatibility mode, or we're running an old kernel */ +static xTaskHandle HandleTzCtrl = NULL; /* TzCtrl task TCB */ +#endif + +#if defined(configSUPPORT_STATIC_ALLOCATION) +#if (configSUPPORT_STATIC_ALLOCATION == 1) +static StackType_t stackTzCtrl[TRC_CFG_CTRL_TASK_STACK_SIZE]; +static StaticTask_t tcbTzCtrl; +#endif +#endif + +/* Monitored by TzCtrl task, that give warnings as User Events */ +extern volatile uint32_t NoRoomForSymbol; +extern volatile uint32_t NoRoomForObjectData; +extern volatile uint32_t LongestSymbolName; +extern volatile uint32_t MaxBytesTruncated; + +/* Keeps track of previous values, to only react on changes. */ +static uint32_t NoRoomForSymbol_last = 0; +static uint32_t NoRoomForObjectData_last = 0; +static uint32_t LongestSymbolName_last = 0; +static uint32_t MaxBytesTruncated_last = 0; + +/* User Event Channel for giving warnings regarding NoRoomForSymbol etc. */ +traceString trcWarningChannel; + +#define TRC_PORT_MALLOC(size) pvPortMalloc(size) + +TRC_STREAM_PORT_ALLOCATE_FIELDS() + +/* Called by TzCtrl task periodically (Normally every 100 ms) */ +static void prvCheckRecorderStatus(void); + +extern void prvTraceWarning(int errCode); + +/* The TzCtrl task - receives commands from Tracealyzer (start/stop) */ +static portTASK_FUNCTION( TzCtrl, pvParameters ); + +/******************************************************************************* + * vTraceEnable + * + * Function that enables the tracing and creates the control task. It will halt + * execution until a Start command has been received if haltUntilStart is true. + * + ******************************************************************************/ +void vTraceEnable(int startOption) +{ + int32_t bytes = 0; + int32_t status; + extern uint32_t RecorderEnabled; + TracealyzerCommandType msg; + + /* Only do this first time...*/ + if (HandleTzCtrl == NULL) + { + TRC_STREAM_PORT_INIT(); + + /* Note: Requires that TRC_CFG_INCLUDE_USER_EVENTS is 1. */ + trcWarningChannel = xTraceRegisterString("Warnings from Recorder"); + + /* Creates the TzCtrl task - receives trace commands (start, stop, ...) */ + #if defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION == 1) + HandleTzCtrl = xTaskCreateStatic(TzCtrl, STRING_CAST("TzCtrl"), TRC_CFG_CTRL_TASK_STACK_SIZE, NULL, TRC_CFG_CTRL_TASK_PRIORITY, stackTzCtrl, &tcbTzCtrl); + #else + xTaskCreate( TzCtrl, STRING_CAST("TzCtrl"), TRC_CFG_CTRL_TASK_STACK_SIZE, NULL, TRC_CFG_CTRL_TASK_PRIORITY, &HandleTzCtrl ); + #endif + + if (HandleTzCtrl == NULL) + { + prvTraceError(PSF_ERROR_TZCTRLTASK_NOT_CREATED); + } + } + + if (startOption == TRC_START_AWAIT_HOST) + { + /* We keep trying to read commands until the recorder has been started */ + do + { + bytes = 0; + + status = TRC_STREAM_PORT_READ_DATA(&msg, sizeof(TracealyzerCommandType), (int32_t*)&bytes); + + if (status != 0) + { + prvTraceWarning(PSF_WARNING_STREAM_PORT_READ); + } + + if ((status == 0) && (bytes == sizeof(TracealyzerCommandType))) + { + if (prvIsValidCommand(&msg)) + { + if (msg.cmdCode == CMD_SET_ACTIVE && msg.param1 == 1) + { + /* On start, init and reset the timestamping */ + TRC_PORT_SPECIFIC_INIT(); + } + + prvProcessCommand(&msg); + } + } + } + while (RecorderEnabled == 0); + } + else if (startOption == TRC_START) + { + /* We start streaming directly - this assumes that the interface is ready! */ + TRC_PORT_SPECIFIC_INIT(); + + msg.cmdCode = CMD_SET_ACTIVE; + msg.param1 = 1; + prvProcessCommand(&msg); + } + else + { + /* On TRC_INIT */ + TRC_PORT_SPECIFIC_INIT(); + } +} + +#if (TRC_CFG_SCHEDULING_ONLY == 0) +/******************************************************************************* + * vTraceSetQueueName(void* object, const char* name) + * + * Parameter object: pointer to the Queue that shall be named + * Parameter name: the name to set (const string literal) + * + * Sets a name for Queue objects for display in Tracealyzer. + ******************************************************************************/ +void vTraceSetQueueName(void* object, const char* name) +{ + vTraceStoreKernelObjectName(object, name); +} + +/******************************************************************************* + * vTraceSetSemaphoreName(void* object, const char* name) + * + * Parameter object: pointer to the Semaphore that shall be named + * Parameter name: the name to set (const string literal) + * + * Sets a name for Semaphore objects for display in Tracealyzer. + ******************************************************************************/ +void vTraceSetSemaphoreName(void* object, const char* name) +{ + vTraceStoreKernelObjectName(object, name); +} + +/******************************************************************************* + * vTraceSetMutexName(void* object, const char* name) + * + * Parameter object: pointer to the Mutex that shall be named + * Parameter name: the name to set (const string literal) + * + * Sets a name for Mutex objects for display in Tracealyzer. + ******************************************************************************/ +void vTraceSetMutexName(void* object, const char* name) +{ + vTraceStoreKernelObjectName(object, name); +} + +#if (TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_8_X) +/******************************************************************************* +* vTraceSetEventGroupName(void* object, const char* name) +* +* Parameter object: pointer to the vTraceSetEventGroupName that shall be named +* Parameter name: the name to set (const string literal) +* +* Sets a name for EventGroup objects for display in Tracealyzer. +******************************************************************************/ +void vTraceSetEventGroupName(void* object, const char* name) +{ + vTraceStoreKernelObjectName(object, name); +} +#endif /* (TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_8_X) */ + +#if (TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) +/******************************************************************************* +* vTraceSetStreamBufferName(void* object, const char* name) +* +* Parameter object: pointer to the StreamBuffer that shall be named +* Parameter name: the name to set (const string literal) +* +* Sets a name for StreamBuffer objects for display in Tracealyzer. +******************************************************************************/ +void vTraceSetStreamBufferName(void* object, const char* name) +{ + vTraceStoreKernelObjectName(object, name); +} + +/******************************************************************************* +* vTraceSetMessageBufferName(void* object, const char* name) +* +* Parameter object: pointer to the MessageBuffer that shall be named +* Parameter name: the name to set (const string literal) +* +* Sets a name for MessageBuffer objects for display in Tracealyzer. +******************************************************************************/ +void vTraceSetMessageBufferName(void* object, const char* name) +{ + vTraceStoreKernelObjectName(object, name); +} +#endif /* (TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) */ + +#endif /* (TRC_CFG_SCHEDULING_ONLY == 0) */ + +/******************************************************************************* + * prvGetCurrentTaskHandle + * + * Function that returns the handle to the currently executing task. + * + ******************************************************************************/ +void* prvTraceGetCurrentTaskHandle(void) +{ + return xTaskGetCurrentTaskHandle(); +} + +/******************************************************************************* + * prvIsNewTCB + * + * Tells if this task is already executing, or if there has been a task-switch. + * Assumed to be called within a trace hook in kernel context. + ******************************************************************************/ +uint32_t prvIsNewTCB(void* pNewTCB) +{ + if (pCurrentTCB != pNewTCB) + { + pCurrentTCB = pNewTCB; + return 1; + } + return 0; +} + +/******************************************************************************* + * prvTraceIsSchedulerSuspended + * + * Returns true if the RTOS scheduler currently is disabled, thus preventing any + * task-switches from occurring. Only called from vTraceStoreISREnd. + ******************************************************************************/ +unsigned char prvTraceIsSchedulerSuspended(void) +{ + /* Assumed to be available in FreeRTOS. According to the FreeRTOS docs, + INCLUDE_xTaskGetSchedulerState or configUSE_TIMERS must be set to 1 in + FreeRTOSConfig.h for this function to be available. */ + + return xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED; +} + + +/******************************************************************************* + * prvCheckRecorderStatus + * + * Called by TzCtrl task periodically (every 100 ms - seems reasonable). + * Checks a number of diagnostic variables and give warnings as user events, + * in most cases including a suggested solution. + ******************************************************************************/ +static void prvCheckRecorderStatus(void) +{ + if (NoRoomForSymbol > NoRoomForSymbol_last) + { + if (NoRoomForSymbol > 0) + { + prvTraceWarning(PSF_WARNING_SYMBOL_TABLE_SLOTS); + } + NoRoomForSymbol_last = NoRoomForSymbol; + } + + if (NoRoomForObjectData > NoRoomForObjectData_last) + { + if (NoRoomForObjectData > 0) + { + prvTraceWarning(PSF_WARNING_OBJECT_DATA_SLOTS); + } + NoRoomForObjectData_last = NoRoomForObjectData; + } + + if (LongestSymbolName > LongestSymbolName_last) + { + if (LongestSymbolName > (TRC_CFG_SYMBOL_MAX_LENGTH)) + { + prvTraceWarning(PSF_WARNING_SYMBOL_MAX_LENGTH); + } + LongestSymbolName_last = LongestSymbolName; + } + + if (MaxBytesTruncated > MaxBytesTruncated_last) + { + if (MaxBytesTruncated > 0) + { + prvTraceWarning(PSF_WARNING_STRING_TOO_LONG); + } + MaxBytesTruncated_last = MaxBytesTruncated; + } +} + +/******************************************************************************* + * TzCtrl + * + * Task for sending the trace data from the internal buffer to the stream + * interface (assuming TRC_STREAM_PORT_USE_INTERNAL_BUFFER == 1) and for + * receiving commands from Tracealyzer. Also does some diagnostics. + ******************************************************************************/ +static portTASK_FUNCTION( TzCtrl, pvParameters ) +{ + TracealyzerCommandType msg; + int32_t bytes = 0; + int32_t status = 0; + (void)pvParameters; + + while (1) + { + do + { + /* Listen for new commands */ + bytes = 0; + status = TRC_STREAM_PORT_READ_DATA(&msg, sizeof(TracealyzerCommandType), (int32_t*)&bytes); + + if (status != 0) + { + prvTraceWarning(PSF_WARNING_STREAM_PORT_READ); + } + + if ((status == 0) && (bytes == sizeof(TracealyzerCommandType))) + { + if (prvIsValidCommand(&msg)) + { + prvProcessCommand(&msg); /* Start or Stop currently... */ + } + } + +/* If the internal buffer is disabled, the COMMIT macro instead sends the data directly + from the "event functions" (using TRC_STREAM_PORT_WRITE_DATA). */ +#if (TRC_STREAM_PORT_USE_INTERNAL_BUFFER == 1) + /* If there is a buffer page, this sends it to the streaming interface using TRC_STREAM_PORT_WRITE_DATA. */ + bytes = prvPagedEventBufferTransfer(); +#endif + + /* If there was data sent or received (bytes != 0), loop around and repeat, if there is more data to send or receive. + Otherwise, step out of this loop and sleep for a while. */ + + } while (bytes != 0); + + prvCheckRecorderStatus(); + + vTaskDelay(TRC_CFG_CTRL_TASK_DELAY); + } +} + +#endif /*(TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING)*/ + + +#if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_SNAPSHOT) + +/* Internal flag to tell the context of tracePEND_FUNC_CALL_FROM_ISR */ +int uiInEventGroupSetBitsFromISR = 0; + +/****************************************************************************** + * TraceQueueClassTable + * Translates a FreeRTOS QueueType into trace objects classes (TRACE_CLASS_). + * Has one entry for each QueueType, gives TRACE_CLASS ID. + ******************************************************************************/ +traceObjectClass TraceQueueClassTable[5] = { + TRACE_CLASS_QUEUE, + TRACE_CLASS_MUTEX, + TRACE_CLASS_SEMAPHORE, + TRACE_CLASS_SEMAPHORE, + TRACE_CLASS_MUTEX +}; + +#if (TRC_CFG_SCHEDULING_ONLY == 0) +/******************************************************************************* + * vTraceSetQueueName(void* object, const char* name) + * + * Parameter object: pointer to the Queue that shall be named + * Parameter name: the name to set (const string literal) + * + * Sets a name for Queue objects for display in Tracealyzer. + ******************************************************************************/ +void vTraceSetQueueName(void* object, const char* name) +{ + prvTraceSetObjectName(TRACE_CLASS_QUEUE, TRACE_GET_OBJECT_NUMBER(QUEUE, object), name); +} + +/******************************************************************************* + * vTraceSetSemaphoreName(void* object, const char* name) + * + * Parameter object: pointer to the Semaphore that shall be named + * Parameter name: the name to set (const string literal) + * + * Sets a name for Semaphore objects for display in Tracealyzer. + ******************************************************************************/ +void vTraceSetSemaphoreName(void* object, const char* name) +{ + prvTraceSetObjectName(TRACE_CLASS_SEMAPHORE, TRACE_GET_OBJECT_NUMBER(QUEUE, object), name); +} + +/******************************************************************************* + * vTraceSetMutexName(void* object, const char* name) + * + * Parameter object: pointer to the Mutex that shall be named + * Parameter name: the name to set (const string literal) + * + * Sets a name for Semaphore objects for display in Tracealyzer. + ******************************************************************************/ +void vTraceSetMutexName(void* object, const char* name) +{ + prvTraceSetObjectName(TRACE_CLASS_MUTEX, TRACE_GET_OBJECT_NUMBER(QUEUE, object), name); +} + +#if (TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_8_X) +/******************************************************************************* +* vTraceSetEventGroupName(void* object, const char* name) +* +* Parameter object: pointer to the EventGroup that shall be named +* Parameter name: the name to set (const string literal) +* +* Sets a name for EventGroup objects for display in Tracealyzer. +******************************************************************************/ +void vTraceSetEventGroupName(void* object, const char* name) +{ + prvTraceSetObjectName(TRACE_CLASS_EVENTGROUP, TRACE_GET_OBJECT_NUMBER(EVENTGROUP, object), name); +} +#endif /* (TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_8_X) */ + +#if (TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) +/******************************************************************************* +* vTraceSetStreamBufferName(void* object, const char* name) +* +* Parameter object: pointer to the StreamBuffer that shall be named +* Parameter name: the name to set (const string literal) +* +* Sets a name for StreamBuffer objects for display in Tracealyzer. +******************************************************************************/ +void vTraceSetStreamBufferName(void* object, const char* name) +{ + prvTraceSetObjectName(TRACE_CLASS_STREAMBUFFER, TRACE_GET_OBJECT_NUMBER(STREAMBUFFER, object), name); +} + +/******************************************************************************* +* vTraceSetMessageBufferName(void* object, const char* name) +* +* Parameter object: pointer to the MessageBuffer that shall be named +* Parameter name: the name to set (const string literal) +* +* Sets a name for MessageBuffer objects for display in Tracealyzer. +******************************************************************************/ +void vTraceSetMessageBufferName(void* object, const char* name) +{ + prvTraceSetObjectName(TRACE_CLASS_MESSAGEBUFFER, TRACE_GET_OBJECT_NUMBER(STREAMBUFFER, object), name); +} +#endif /* (TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS == 1 && TRC_CFG_FREERTOS_VERSION >= TRC_FREERTOS_VERSION_10_0_0) */ + +#endif /* (TRC_CFG_SCHEDULING_ONLY == 0) */ + +void* prvTraceGetCurrentTaskHandle() +{ + return xTaskGetCurrentTaskHandle(); +} + +/* Initialization of the object property table */ +void vTraceInitObjectPropertyTable() +{ + RecorderDataPtr->ObjectPropertyTable.NumberOfObjectClasses = TRACE_NCLASSES; + RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[0] = TRC_CFG_NQUEUE; + RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[1] = TRC_CFG_NSEMAPHORE; + RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[2] = TRC_CFG_NMUTEX; + RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[3] = TRC_CFG_NTASK; + RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[4] = TRC_CFG_NISR; + RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[5] = TRC_CFG_NTIMER; + RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[6] = TRC_CFG_NEVENTGROUP; + RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[7] = TRC_CFG_NSTREAMBUFFER; + RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[8] = TRC_CFG_NMESSAGEBUFFER; + RecorderDataPtr->ObjectPropertyTable.NameLengthPerClass[0] = TRC_CFG_NAME_LEN_QUEUE; + RecorderDataPtr->ObjectPropertyTable.NameLengthPerClass[1] = TRC_CFG_NAME_LEN_SEMAPHORE; + RecorderDataPtr->ObjectPropertyTable.NameLengthPerClass[2] = TRC_CFG_NAME_LEN_MUTEX; + RecorderDataPtr->ObjectPropertyTable.NameLengthPerClass[3] = TRC_CFG_NAME_LEN_TASK; + RecorderDataPtr->ObjectPropertyTable.NameLengthPerClass[4] = TRC_CFG_NAME_LEN_ISR; + RecorderDataPtr->ObjectPropertyTable.NameLengthPerClass[5] = TRC_CFG_NAME_LEN_TIMER; + RecorderDataPtr->ObjectPropertyTable.NameLengthPerClass[6] = TRC_CFG_NAME_LEN_EVENTGROUP; + RecorderDataPtr->ObjectPropertyTable.NameLengthPerClass[7] = TRC_CFG_NAME_LEN_STREAMBUFFER; + RecorderDataPtr->ObjectPropertyTable.NameLengthPerClass[8] = TRC_CFG_NAME_LEN_MESSAGEBUFFER; + RecorderDataPtr->ObjectPropertyTable.TotalPropertyBytesPerClass[0] = PropertyTableSizeQueue; + RecorderDataPtr->ObjectPropertyTable.TotalPropertyBytesPerClass[1] = PropertyTableSizeSemaphore; + RecorderDataPtr->ObjectPropertyTable.TotalPropertyBytesPerClass[2] = PropertyTableSizeMutex; + RecorderDataPtr->ObjectPropertyTable.TotalPropertyBytesPerClass[3] = PropertyTableSizeTask; + RecorderDataPtr->ObjectPropertyTable.TotalPropertyBytesPerClass[4] = PropertyTableSizeISR; + RecorderDataPtr->ObjectPropertyTable.TotalPropertyBytesPerClass[5] = PropertyTableSizeTimer; + RecorderDataPtr->ObjectPropertyTable.TotalPropertyBytesPerClass[6] = PropertyTableSizeEventGroup; + RecorderDataPtr->ObjectPropertyTable.TotalPropertyBytesPerClass[7] = PropertyTableSizeStreamBuffer; + RecorderDataPtr->ObjectPropertyTable.TotalPropertyBytesPerClass[8] = PropertyTableSizeMessageBuffer; + RecorderDataPtr->ObjectPropertyTable.StartIndexOfClass[0] = StartIndexQueue; + RecorderDataPtr->ObjectPropertyTable.StartIndexOfClass[1] = StartIndexSemaphore; + RecorderDataPtr->ObjectPropertyTable.StartIndexOfClass[2] = StartIndexMutex; + RecorderDataPtr->ObjectPropertyTable.StartIndexOfClass[3] = StartIndexTask; + RecorderDataPtr->ObjectPropertyTable.StartIndexOfClass[4] = StartIndexISR; + RecorderDataPtr->ObjectPropertyTable.StartIndexOfClass[5] = StartIndexTimer; + RecorderDataPtr->ObjectPropertyTable.StartIndexOfClass[6] = StartIndexEventGroup; + RecorderDataPtr->ObjectPropertyTable.StartIndexOfClass[7] = StartIndexStreamBuffer; + RecorderDataPtr->ObjectPropertyTable.StartIndexOfClass[8] = StartIndexMessageBuffer; + RecorderDataPtr->ObjectPropertyTable.ObjectPropertyTableSizeInBytes = TRACE_OBJECT_TABLE_SIZE; +} + +/* Initialization of the handle mechanism, see e.g, prvTraceGetObjectHandle */ +void vTraceInitObjectHandleStack() +{ + objectHandleStacks.indexOfNextAvailableHandle[0] = objectHandleStacks.lowestIndexOfClass[0] = 0; + objectHandleStacks.indexOfNextAvailableHandle[1] = objectHandleStacks.lowestIndexOfClass[1] = (TRC_CFG_NQUEUE); + objectHandleStacks.indexOfNextAvailableHandle[2] = objectHandleStacks.lowestIndexOfClass[2] = (TRC_CFG_NQUEUE) + (TRC_CFG_NSEMAPHORE); + objectHandleStacks.indexOfNextAvailableHandle[3] = objectHandleStacks.lowestIndexOfClass[3] = (TRC_CFG_NQUEUE) + (TRC_CFG_NSEMAPHORE) + (TRC_CFG_NMUTEX); + objectHandleStacks.indexOfNextAvailableHandle[4] = objectHandleStacks.lowestIndexOfClass[4] = (TRC_CFG_NQUEUE) + (TRC_CFG_NSEMAPHORE) + (TRC_CFG_NMUTEX) + (TRC_CFG_NTASK); + objectHandleStacks.indexOfNextAvailableHandle[5] = objectHandleStacks.lowestIndexOfClass[5] = (TRC_CFG_NQUEUE) + (TRC_CFG_NSEMAPHORE) + (TRC_CFG_NMUTEX) + (TRC_CFG_NTASK) + (TRC_CFG_NISR); + objectHandleStacks.indexOfNextAvailableHandle[6] = objectHandleStacks.lowestIndexOfClass[6] = (TRC_CFG_NQUEUE) + (TRC_CFG_NSEMAPHORE) + (TRC_CFG_NMUTEX) + (TRC_CFG_NTASK) + (TRC_CFG_NISR) + (TRC_CFG_NTIMER); + objectHandleStacks.indexOfNextAvailableHandle[7] = objectHandleStacks.lowestIndexOfClass[7] = (TRC_CFG_NQUEUE) + (TRC_CFG_NSEMAPHORE) + (TRC_CFG_NMUTEX) + (TRC_CFG_NTASK) + (TRC_CFG_NISR) + (TRC_CFG_NTIMER) + (TRC_CFG_NEVENTGROUP); + objectHandleStacks.indexOfNextAvailableHandle[8] = objectHandleStacks.lowestIndexOfClass[8] = (TRC_CFG_NQUEUE) + (TRC_CFG_NSEMAPHORE) + (TRC_CFG_NMUTEX) + (TRC_CFG_NTASK) + (TRC_CFG_NISR) + (TRC_CFG_NTIMER) + (TRC_CFG_NEVENTGROUP) + (TRC_CFG_NSTREAMBUFFER); + + objectHandleStacks.highestIndexOfClass[0] = (TRC_CFG_NQUEUE) - 1; + objectHandleStacks.highestIndexOfClass[1] = (TRC_CFG_NQUEUE) + (TRC_CFG_NSEMAPHORE) - 1; + objectHandleStacks.highestIndexOfClass[2] = (TRC_CFG_NQUEUE) + (TRC_CFG_NSEMAPHORE) + (TRC_CFG_NMUTEX) - 1; + objectHandleStacks.highestIndexOfClass[3] = (TRC_CFG_NQUEUE) + (TRC_CFG_NSEMAPHORE) + (TRC_CFG_NMUTEX) + (TRC_CFG_NTASK) - 1; + objectHandleStacks.highestIndexOfClass[4] = (TRC_CFG_NQUEUE) + (TRC_CFG_NSEMAPHORE) + (TRC_CFG_NMUTEX) + (TRC_CFG_NTASK) + (TRC_CFG_NISR) - 1; + objectHandleStacks.highestIndexOfClass[5] = (TRC_CFG_NQUEUE) + (TRC_CFG_NSEMAPHORE) + (TRC_CFG_NMUTEX) + (TRC_CFG_NTASK) + (TRC_CFG_NISR) + (TRC_CFG_NTIMER) - 1; + objectHandleStacks.highestIndexOfClass[6] = (TRC_CFG_NQUEUE) + (TRC_CFG_NSEMAPHORE) + (TRC_CFG_NMUTEX) + (TRC_CFG_NTASK) + (TRC_CFG_NISR) + (TRC_CFG_NTIMER) + (TRC_CFG_NEVENTGROUP) - 1; + objectHandleStacks.highestIndexOfClass[7] = (TRC_CFG_NQUEUE) + (TRC_CFG_NSEMAPHORE) + (TRC_CFG_NMUTEX) + (TRC_CFG_NTASK) + (TRC_CFG_NISR) + (TRC_CFG_NTIMER) + (TRC_CFG_NEVENTGROUP) + (TRC_CFG_NSTREAMBUFFER) - 1; + objectHandleStacks.highestIndexOfClass[8] = (TRC_CFG_NQUEUE) + (TRC_CFG_NSEMAPHORE) + (TRC_CFG_NMUTEX) + (TRC_CFG_NTASK) + (TRC_CFG_NISR) + (TRC_CFG_NTIMER) + (TRC_CFG_NEVENTGROUP) + (TRC_CFG_NSTREAMBUFFER) + (TRC_CFG_NMESSAGEBUFFER) - 1; +} + +/* Returns the "Not enough handles" error message for this object class */ +const char* pszTraceGetErrorNotEnoughHandles(traceObjectClass objectclass) +{ + switch(objectclass) + { + case TRACE_CLASS_TASK: + return "Not enough TASK handles - increase TRC_CFG_NTASK in trcSnapshotConfig.h"; + case TRACE_CLASS_ISR: + return "Not enough ISR handles - increase TRC_CFG_NISR in trcSnapshotConfig.h"; + case TRACE_CLASS_SEMAPHORE: + return "Not enough SEMAPHORE handles - increase TRC_CFG_NSEMAPHORE in trcSnapshotConfig.h"; + case TRACE_CLASS_MUTEX: + return "Not enough MUTEX handles - increase TRC_CFG_NMUTEX in trcSnapshotConfig.h"; + case TRACE_CLASS_QUEUE: + return "Not enough QUEUE handles - increase TRC_CFG_NQUEUE in trcSnapshotConfig.h"; + case TRACE_CLASS_TIMER: + return "Not enough TIMER handles - increase TRC_CFG_NTIMER in trcSnapshotConfig.h"; + case TRACE_CLASS_EVENTGROUP: + return "Not enough EVENTGROUP handles - increase TRC_CFG_NEVENTGROUP in trcSnapshotConfig.h"; + case TRACE_CLASS_STREAMBUFFER: + return "Not enough STREAMBUFFER handles - increase TRC_CFG_NSTREAMBUFFER in trcSnapshotConfig.h"; + case TRACE_CLASS_MESSAGEBUFFER: + return "Not enough MESSAGEBUFFER handles - increase TRC_CFG_NMESSAGEBUFFER in trcSnapshotConfig.h"; + default: + return "pszTraceGetErrorHandles: Invalid objectclass!"; + } +} + +/******************************************************************************* + * prvTraceIsSchedulerSuspended + * + * Returns true if the RTOS scheduler currently is disabled, thus preventing any + * task-switches from occurring. Only called from vTraceStoreISREnd. + ******************************************************************************/ +#if (TRC_CFG_INCLUDE_ISR_TRACING == 1) +unsigned char prvTraceIsSchedulerSuspended(void) +{ + /* Assumed to be available in FreeRTOS. According to the FreeRTOS docs, + INCLUDE_xTaskGetSchedulerState or configUSE_TIMERS must be set to 1 in + FreeRTOSConfig.h for this function to be available. */ + + return xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED; +} +#endif + +#endif /* Snapshot mode */ + +#endif /*(TRC_USE_TRACEALYZER_RECORDER == 1)*/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/trcSnapshotRecorder.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/trcSnapshotRecorder.c new file mode 100644 index 0000000..9eec9d2 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/trcSnapshotRecorder.c @@ -0,0 +1,3105 @@ +/******************************************************************************* + * Trace Recorder Library for Tracealyzer v4.1.5 + * Percepio AB, www.percepio.com + * + * trcSnapshotRecorder.c + * + * The generic core of the trace recorder's snapshot mode. + * + * Terms of Use + * This file is part of the trace recorder library (RECORDER), which is the + * intellectual property of Percepio AB (PERCEPIO) and provided under a + * license as follows. + * The RECORDER may be used free of charge for the purpose of recording data + * intended for analysis in PERCEPIO products. It may not be used or modified + * for other purposes without explicit permission from PERCEPIO. + * You may distribute the RECORDER in its original source code form, assuming + * this text (terms of use, disclaimer, copyright notice) is unchanged. You are + * allowed to distribute the RECORDER with minor modifications intended for + * configuration or porting of the RECORDER, e.g., to allow using it on a + * specific processor, processor family or with a specific communication + * interface. Any such modifications should be documented directly below + * this comment block. + * + * Disclaimer + * The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty + * as to its use or performance. PERCEPIO does not and cannot warrant the + * performance or results you may obtain by using the RECORDER or documentation. + * PERCEPIO make no warranties, express or implied, as to noninfringement of + * third party rights, merchantability, or fitness for any particular purpose. + * In no event will PERCEPIO, its technology partners, or distributors be liable + * to you for any consequential, incidental or special damages, including any + * lost profits or lost savings, even if a representative of PERCEPIO has been + * advised of the possibility of such damages, or for any claim by any third + * party. Some jurisdictions do not allow the exclusion or limitation of + * incidental, consequential or special damages, or the exclusion of implied + * warranties or limitations on how long an implied warranty may last, so the + * above limitations may not apply to you. + * + * Tabs are used for indent in this file (1 tab = 4 spaces) + * + * Copyright Percepio AB, 2018. + * www.percepio.com + ******************************************************************************/ + +#include "trcRecorder.h" + +#if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_SNAPSHOT) + +#if (TRC_USE_TRACEALYZER_RECORDER == 1) + +#include +#include +#include + +#if ((TRC_HWTC_TYPE == TRC_CUSTOM_TIMER_INCR) || (TRC_HWTC_TYPE == TRC_CUSTOM_TIMER_DECR)) + #error "CUSTOM timestamping mode is not (yet) supported in snapshot mode!" +#endif + +/* DO NOT CHANGE */ +#define TRACE_MINOR_VERSION 5 +#if (TRC_CFG_INCLUDE_ISR_TRACING == 1) +static traceHandle isrstack[TRC_CFG_MAX_ISR_NESTING]; +int32_t isPendingContextSwitch = 0; +#endif /* (TRC_CFG_INCLUDE_ISR_TRACING == 1) */ + +#if !defined TRC_CFG_INCLUDE_READY_EVENTS || TRC_CFG_INCLUDE_READY_EVENTS == 1 +static int readyEventsEnabled = 1; +#endif /*!defined TRC_CFG_INCLUDE_READY_EVENTS || TRC_CFG_INCLUDE_READY_EVENTS == 1*/ + +/******************************************************************************* + * uiTraceTickCount + * + * This variable is should be updated by the Kernel tick interrupt. This does + * not need to be modified when developing a new timer port. It is preferred to + * keep any timer port changes in the HWTC macro definitions, which typically + * give sufficient flexibility. + ******************************************************************************/ +uint32_t uiTraceTickCount = 0; + +uint32_t trace_disable_timestamp = 0; + +static uint32_t last_timestamp = 0; + +/* Flag that shows if inside a critical section of the recorder */ +volatile int recorder_busy = 0; + +/* Holds the value set by vTraceSetFrequency */ +uint32_t timestampFrequency = 0; + +/* The last error message of the recorder. NULL if no error message. */ +const char* traceErrorMessage = NULL; + +int8_t nISRactive = 0; + +traceHandle handle_of_last_logged_task = 0; + +/* Called when the recorder is stopped, set by vTraceSetStopHook. */ +TRACE_STOP_HOOK vTraceStopHookPtr = (TRACE_STOP_HOOK)0; + +uint16_t CurrentFilterMask = 0xFFFF; + +uint16_t CurrentFilterGroup = FilterGroup0; + +extern int8_t nISRactive; + +extern traceHandle handle_of_last_logged_task; + +/*************** Private Functions *******************************************/ +static void prvStrncpy(char* dst, const char* src, uint32_t maxLength); +static uint8_t prvTraceGetObjectState(uint8_t objectclass, traceHandle id); +static void prvTraceGetChecksum(const char *pname, uint8_t* pcrc, uint8_t* plength); +static void* prvTraceNextFreeEventBufferSlot(void); +static uint16_t prvTraceGetDTS(uint16_t param_maxDTS); +static traceString prvTraceOpenSymbol(const char* name, traceString userEventChannel); +static void prvTraceUpdateCounters(void); + +void vTraceStoreMemMangEvent(uint32_t ecode, uint32_t address, int32_t signed_size); + +#if (TRC_CFG_SNAPSHOT_MODE == TRC_SNAPSHOT_MODE_RING_BUFFER) +static void prvCheckDataToBeOverwrittenForMultiEntryEvents(uint8_t nEntries); +#endif + +static traceString prvTraceCreateSymbolTableEntry(const char* name, + uint8_t crc6, + uint8_t len, + traceString channel); + +static traceString prvTraceLookupSymbolTableEntry(const char* name, + uint8_t crc6, + uint8_t len, + traceString channel); + + +#if (TRC_CFG_INCLUDE_ISR_TRACING == 0) +/* ISR tracing is turned off */ +void prvTraceIncreaseISRActive(void); +void prvTraceDecreaseISRActive(void); +#endif /*(TRC_CFG_INCLUDE_ISR_TRACING == 0)*/ + +#if (TRC_CFG_USE_16BIT_OBJECT_HANDLES == 1) +static uint8_t prvTraceGet8BitHandle(traceHandle handle); +#else +#define prvTraceGet8BitHandle(x) ((uint8_t)x) +#endif + + +#if (TRC_CFG_INCLUDE_MEMMANG_EVENTS == 1) && (TRC_CFG_SCHEDULING_ONLY == 0) +static uint32_t heapMemUsage = 0; +#endif + +#if (TRC_CFG_SCHEDULING_ONLY == 0) +static uint32_t prvTraceGetParam(uint32_t, uint32_t); +#endif + +/******************************************************************************* + * prvTraceInitTraceData + * + * Allocates and initializes the recorder data structure, based on the constants + * in trcConfig.h. This allows for allocating the data on the heap, instead of + * using a static declaration. + ******************************************************************************/ +static void prvTraceInitTraceData(void); + +/******************************************************************************* + * prvTracePortGetTimeStamp + * + * Returns the current time based on the HWTC macros which provide a hardware + * isolation layer towards the hardware timer/counter. + * + * The HWTC macros and prvTracePortGetTimeStamp is the main porting issue + * or the trace recorder library. Typically you should not need to change + * the code of prvTracePortGetTimeStamp if using the HWTC macros. + * + ******************************************************************************/ +void prvTracePortGetTimeStamp(uint32_t *puiTimestamp); + +static void prvTraceTaskInstanceFinish(int8_t direct); + +#if ((TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1)) +static void vTracePrintF_Helper(traceString eventLabel, const char* formatStr, va_list vl); + +#if (TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER == 1) +static void vTraceUBData_Helper(traceUBChannel channelPair, va_list vl); +static void prvTraceUBHelper1(traceUBChannel channel, traceString eventLabel, traceString formatLabel, va_list vl); +static void prvTraceUBHelper2(traceUBChannel channel, uint32_t* data, uint32_t noOfSlots); +#endif /*(TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER == 1)*/ +#endif /* ((TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1)) */ + +/********* Public Functions **************************************************/ + +uint16_t uiIndexOfObject(traceHandle objecthandle, uint8_t objectclass); + +/******************************************************************************* + * prvTraceError + * + * Called by various parts in the recorder. Stops the recorder and stores a + * pointer to an error message, which is printed by the monitor task. + ******************************************************************************/ +void prvTraceError(const char* msg); + +/****************************************************************************** +* vTraceEnable(int startOption) - snapshot mode +* +* Initializes and optionally starts the trace, depending on the start option. +* To use the trace recorder, the startup must call vTraceEnable before any RTOS +* calls are made (including "create" calls). Three start options are provided: +* +* TRC_START: Starts the tracing directly. In snapshot mode this allows for +* starting the trace at any point in your code, assuming vTraceEnable(TRC_INIT) +* has been called in the startup. +* Can also be used for streaming without Tracealyzer control, e.g. to a local +* flash file system (assuming such a "stream port", see trcStreamingPort.h). +* +* TRC_INIT: Initializes the trace recorder, but does not start the tracing. +* In snapshot mode, this must be followed by a vTraceEnable(TRC_START) sometime +* later. +* +* Usage examples, in snapshot mode: +* +* Snapshot trace, from startup: +* +* vTraceEnable(TRC_START); +* +* +* Snapshot trace, from a later point: +* +* vTraceEnable(TRC_INIT); +* +* ... +* vTraceEnable(TRC_START); // e.g., in task context, at some relevant event +* +* +* Note: See other implementation of vTraceEnable in trcStreamingRecorder.c +******************************************************************************/ +void vTraceEnable(int startOption) +{ + prvTraceInitTraceData(); + + if (startOption == TRC_START) + { + vTraceStart(); + } + else if (startOption == TRC_START_AWAIT_HOST) + { + prvTraceError("vTraceEnable(TRC_START_AWAIT_HOST) not allowed in Snapshot mode"); + } + else if (startOption != TRC_INIT) + { + prvTraceError("Unexpected argument to vTraceEnable (snapshot mode)"); + } +} + +/******************************************************************************* + * vTraceSetRecorderDataBuffer + * + * If custom allocation is used, this function must be called so the recorder + * library knows where to save the trace data. + ******************************************************************************/ +#if (TRC_CFG_RECORDER_BUFFER_ALLOCATION == TRC_RECORDER_BUFFER_ALLOCATION_CUSTOM) +void vTraceSetRecorderDataBuffer(void* pRecorderData) +{ + TRACE_ASSERT(pRecorderData != NULL, "vTraceSetRecorderDataBuffer, pRecorderData == NULL", TRC_UNUSED); + RecorderDataPtr = pRecorderData; +} +#endif + +/******************************************************************************* + * vTraceSetStopHook + * + * Sets a function to be called when the recorder is stopped. This can be used + * to save the trace to a file system, if available. This is only implemented + * for snapshot mode. + ******************************************************************************/ +void vTraceSetStopHook(TRACE_STOP_HOOK stopHookFunction) +{ + vTraceStopHookPtr = stopHookFunction; +} + +/******************************************************************************* + * vTraceClear + * + * Resets the recorder. Only necessary if a restart is desired - this is not + * needed in the startup initialization. + ******************************************************************************/ +void vTraceClear(void) +{ + TRACE_ALLOC_CRITICAL_SECTION(); + trcCRITICAL_SECTION_BEGIN(); + RecorderDataPtr->absTimeLastEventSecond = 0; + RecorderDataPtr->absTimeLastEvent = 0; + RecorderDataPtr->nextFreeIndex = 0; + RecorderDataPtr->numEvents = 0; + RecorderDataPtr->bufferIsFull = 0; + traceErrorMessage = NULL; + RecorderDataPtr->internalErrorOccured = 0; + (void)memset(RecorderDataPtr->eventData, 0, RecorderDataPtr->maxEvents * 4); + handle_of_last_logged_task = 0; + trcCRITICAL_SECTION_END(); +} + +/******************************************************************************* + * uiTraceStart + * + * Starts the recorder. The recorder will not be started if an error has been + * indicated using prvTraceError, e.g. if any of the Nx constants in trcConfig.h + * has a too small value (TRC_CFG_NTASK, TRC_CFG_NQUEUE, etc). + * + * Returns 1 if the recorder was started successfully. + * Returns 0 if the recorder start was prevented due to a previous internal + * error. In that case, check xTraceGetLastError to get the error message. + * Any error message is also presented when opening a trace file. + * + * This function is obsolete, but has been saved for backwards compatibility. + * We recommend using vTraceEnable instead. + ******************************************************************************/ +uint32_t uiTraceStart(void) +{ + traceHandle handle; + TRACE_ALLOC_CRITICAL_SECTION(); + + handle = 0; + + if (RecorderDataPtr == NULL) + { + TRACE_ASSERT(RecorderDataPtr != NULL, "Recorder not initialized. Use vTraceEnable() instead!", 0); + return 0; + } + + if (RecorderDataPtr->recorderActive == 1) + return 1; /* Already running */ + + if (traceErrorMessage == NULL) + { + trcCRITICAL_SECTION_BEGIN(); + RecorderDataPtr->recorderActive = 1; + + handle = TRACE_GET_TASK_NUMBER(TRACE_GET_CURRENT_TASK()); + if (handle == 0) + { + /* This occurs if the scheduler is not yet started. + This creates a dummy "(startup)" task entry internally in the + recorder */ + handle = prvTraceGetObjectHandle(TRACE_CLASS_TASK); + prvTraceSetObjectName(TRACE_CLASS_TASK, handle, "(startup)"); + + prvTraceSetPriorityProperty(TRACE_CLASS_TASK, handle, 0); + } + + prvTraceStoreTaskswitch(handle); /* Register the currently running task */ + trcCRITICAL_SECTION_END(); + } + + return RecorderDataPtr->recorderActive; +} + +/******************************************************************************* + * vTraceStart + * + * Starts the recorder. The recorder will not be started if an error has been + * indicated using prvTraceError, e.g. if any of the Nx constants in trcConfig.h + * has a too small value (TRC_CFG_NTASK, TRC_CFG_NQUEUE, etc). + * + * This function is obsolete, but has been saved for backwards compatibility. + * We recommend using vTraceEnable instead. + ******************************************************************************/ +void vTraceStart(void) +{ + (void)uiTraceStart(); +} + +/******************************************************************************* + * vTraceStop + * + * Stops the recorder. The recording can be resumed by calling vTraceStart. + * This does not reset the recorder. Use vTraceClear if that is desired. + ******************************************************************************/ +void vTraceStop(void) +{ + if (RecorderDataPtr != NULL) + { + RecorderDataPtr->recorderActive = 0; + } + + if (vTraceStopHookPtr != (TRACE_STOP_HOOK)0) + { + (*vTraceStopHookPtr)(); /* An application call-back function. */ + } +} + +/******************************************************************************* +* xTraceIsRecordingEnabled +* Returns true (1) if the recorder is enabled (i.e. is recording), otherwise 0. +******************************************************************************/ +int xTraceIsRecordingEnabled(void) +{ + if (RecorderDataPtr != NULL) + { + return (int)RecorderDataPtr->recorderActive; + } + else + { + return 0; + } +} + +/******************************************************************************* + * xTraceGetLastError + * + * Gives the last error message, if any. NULL if no error message is stored. + * Any error message is also presented when opening a trace file. + ******************************************************************************/ +const char* xTraceGetLastError(void) +{ + return traceErrorMessage; +} + +/******************************************************************************* +* vTraceClearError +* +* Removes any previous error message generated by recorder calling prvTraceError. +* By calling this function, it may be possible to start/restart the trace +* despite errors in the recorder, but there is no guarantee that the trace +* recorder will work correctly in that case, depending on the type of error. +******************************************************************************/ +void vTraceClearError(void) +{ + traceErrorMessage = NULL; + if (RecorderDataPtr != NULL) + { + RecorderDataPtr->internalErrorOccured = 0; + } +} + +/******************************************************************************* + * xTraceGetTraceBuffer + * + * Returns a pointer to the recorder data structure. Use this together with + * uiTraceGetTraceBufferSize if you wish to implement an own store/upload + * solution, e.g., in case a debugger connection is not available for uploading + * the data. + ******************************************************************************/ +void* xTraceGetTraceBuffer(void) +{ + return RecorderDataPtr; +} + +/******************************************************************************* + * uiTraceGetTraceBufferSize + * + * Gets the size of the recorder data structure. For use together with + * vTraceGetTraceBuffer if you wish to implement an own store/upload solution, + * e.g., in case a debugger connection is not available for uploading the data. + ******************************************************************************/ +uint32_t uiTraceGetTraceBufferSize(void) +{ + return sizeof(RecorderDataType); +} + +/****************************************************************************** + * prvTraceTaskInstanceFinish + * + * Private common function for the vTraceTaskInstanceFinishXXX functions. + *****************************************************************************/ +static void prvTraceTaskInstanceFinish(int8_t direct) +{ + TaskInstanceStatusEvent* tis; + uint8_t dts45; + + TRACE_ALLOC_CRITICAL_SECTION(); + + trcCRITICAL_SECTION_BEGIN(); + if (RecorderDataPtr->recorderActive && handle_of_last_logged_task) + { + dts45 = (uint8_t)prvTraceGetDTS(0xFF); + tis = (TaskInstanceStatusEvent*) prvTraceNextFreeEventBufferSlot(); + if (tis != NULL) + { + if (direct == 0) + tis->type = TASK_INSTANCE_FINISHED_NEXT_KSE; + else + tis->type = TASK_INSTANCE_FINISHED_DIRECT; + + tis->dts = dts45; + prvTraceUpdateCounters(); + } + } + trcCRITICAL_SECTION_END(); +} + +/****************************************************************************** + * vTraceInstanceFinishedNext(void) + * + * Marks the current task instance as finished on the next kernel call. + * + * If that kernel call is blocking, the instance ends after the blocking event + * and the corresponding return event is then the start of the next instance. + * If the kernel call is not blocking, the viewer instead splits the current + * fragment right before the kernel call, which makes this call the first event + * of the next instance. + * + * See also TRC_CFG_USE_IMPLICIT_IFE_RULES in trcConfig.h + * + * Example: + * + * while(1) + * { + * xQueueReceive(CommandQueue, &command, timeoutDuration); + * processCommand(command); + * vTraceInstanceFinishedNext(); + * } + *****************************************************************************/ +void vTraceInstanceFinishedNext(void) +{ + prvTraceTaskInstanceFinish(0); +} + +/****************************************************************************** + * vTraceInstanceFinishedNow(void) + * + * Marks the current task instance as finished at this very instant. + * This makes the viewer to splits the current fragment at this point and begin + * a new actor instance. + * + * See also TRC_CFG_USE_IMPLICIT_IFE_RULES in trcConfig.h + * + * Example: + * + * This example will generate two instances for each loop iteration. + * The first instance ends at vTraceInstanceFinishedNow(), while the second + * instance ends at the next xQueueReceive call. + * + * while (1) + * { + * xQueueReceive(CommandQueue, &command, timeoutDuration); + * ProcessCommand(command); + * vTraceInstanceFinishedNow(); + * DoSometingElse(); + * vTraceInstanceFinishedNext(); + * } + *****************************************************************************/ +void vTraceInstanceFinishedNow(void) +{ + prvTraceTaskInstanceFinish(1); +} + +/******************************************************************************* + * Interrupt recording functions + ******************************************************************************/ + +#if (TRC_CFG_INCLUDE_ISR_TRACING == 1) + +/******************************************************************************* + * xTraceSetISRProperties + * + * Stores a name and priority level for an Interrupt Service Routine, to allow + * for better visualization. Returns a traceHandle used by vTraceStoreISRBegin. + * + * Example: + * #define PRIO_ISR_TIMER1 3 // the hardware priority of the interrupt + * ... + * traceHandle Timer1Handle = xTraceSetISRProperties("ISRTimer1", PRIO_ISR_TIMER1); + * ... + * void ISR_handler() + * { + * vTraceStoreISRBegin(Timer1Handle); + * ... + * vTraceStoreISREnd(0); + * } + ******************************************************************************/ + traceHandle xTraceSetISRProperties(const char* name, uint8_t priority) +{ + static traceHandle handle = 0; + TRACE_ASSERT(RecorderDataPtr != NULL, "Recorder not initialized, call vTraceEnable() first!", (traceHandle)0); + TRACE_ASSERT(handle <= RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[TRACE_CLASS_ISR], "xTraceSetISRProperties: Invalid value for handle", 0); + TRACE_ASSERT(name != NULL, "xTraceSetISRProperties: name == NULL", 0); + + handle++; + + prvTraceSetObjectName(TRACE_CLASS_ISR, handle, name); + prvTraceSetPriorityProperty(TRACE_CLASS_ISR, handle, priority); + + return handle; +} + +/******************************************************************************* + * vTraceStoreISRBegin + * + * Registers the beginning of an Interrupt Service Routine, using a traceHandle + * provided by xTraceSetISRProperties. + * + * Example: + * #define PRIO_ISR_TIMER1 3 // the hardware priority of the interrupt + * ... + * traceHandle Timer1Handle = xTraceSetISRProperties("ISRTimer1", PRIO_ISR_TIMER1); + * ... + * void ISR_handler() + * { + * vTraceStoreISRBegin(Timer1Handle); + * ... + * vTraceStoreISREnd(0); + * } + ******************************************************************************/ +void vTraceStoreISRBegin(traceHandle handle) +{ + TRACE_ALLOC_CRITICAL_SECTION(); + + if (recorder_busy) + { + /************************************************************************* + * This occurs if an ISR calls a trace function, preempting a previous + * trace call that is being processed in a different ISR or task. + * If this occurs, there is probably a problem in the definition of the + * recorder's internal critical sections (TRACE_ENTER_CRITICAL_SECTION and + * TRACE_EXIT_CRITICAL_SECTION). They must disable the RTOS tick interrupt + * and any other ISRs that calls the trace recorder directly or via + * traced kernel functions. The ARM port disables all interrupts using the + * PRIMASK register to avoid this issue. + *************************************************************************/ + prvTraceError("vTraceStoreISRBegin - recorder busy! See code comment."); + return; + } + trcCRITICAL_SECTION_BEGIN(); + + if (RecorderDataPtr->recorderActive && handle_of_last_logged_task) + { + uint16_t dts4; + + TRACE_ASSERT(handle != 0, "vTraceStoreISRBegin: Invalid ISR handle (NULL)", TRC_UNUSED); + TRACE_ASSERT(handle <= RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[TRACE_CLASS_ISR], "vTraceStoreISRBegin: Invalid ISR handle (> NISR)", TRC_UNUSED); + + dts4 = (uint16_t)prvTraceGetDTS(0xFFFF); + + if (RecorderDataPtr->recorderActive) /* Need to repeat this check! */ + { + if (nISRactive < TRC_CFG_MAX_ISR_NESTING) + { + TSEvent* ts; + uint8_t hnd8 = prvTraceGet8BitHandle(handle); + isrstack[nISRactive] = handle; + nISRactive++; + ts = (TSEvent*)prvTraceNextFreeEventBufferSlot(); + if (ts != NULL) + { + ts->type = TS_ISR_BEGIN; + ts->dts = dts4; + ts->objHandle = hnd8; + prvTraceUpdateCounters(); + } + } + else + { + /* This should not occur unless something is very wrong */ + prvTraceError("Too many nested interrupts!"); + } + } + } + trcCRITICAL_SECTION_END(); +} + +/******************************************************************************* + * vTraceStoreISREnd + * + * Registers the end of an Interrupt Service Routine. + * + * The parameter pendingISR indicates if the interrupt has requested a + * task-switch (= 1), e.g., by signaling a semaphore. Otherwise (= 0) the + * interrupt is assumed to return to the previous context. + * + * Example: + * #define PRIO_OF_ISR_TIMER1 3 // the hardware priority of the interrupt + * traceHandle traceHandleIsrTimer1 = 0; // The ID set by the recorder + * ... + * traceHandleIsrTimer1 = xTraceSetISRProperties("ISRTimer1", PRIO_OF_ISR_TIMER1); + * ... + * void ISR_handler() + * { + * vTraceStoreISRBegin(traceHandleIsrTimer1); + * ... + * vTraceStoreISREnd(0); + * } + ******************************************************************************/ +void vTraceStoreISREnd(int pendingISR) +{ + TSEvent* ts; + uint16_t dts5; + uint8_t hnd8 = 0, type = 0; + + TRACE_ALLOC_CRITICAL_SECTION(); + + if (! RecorderDataPtr->recorderActive || ! handle_of_last_logged_task) + { + return; + } + + if (recorder_busy) + { + /************************************************************************* + * This occurs if an ISR calls a trace function, preempting a previous + * trace call that is being processed in a different ISR or task. + * If this occurs, there is probably a problem in the definition of the + * recorder's internal critical sections (TRACE_ENTER_CRITICAL_SECTION and + * TRACE_EXIT_CRITICAL_SECTION). They must disable the RTOS tick interrupt + * and any other ISRs that calls the trace recorder directly or via + * traced kernel functions. The ARM port disables all interrupts using the + * PRIMASK register to avoid this issue. + *************************************************************************/ + prvTraceError("vTraceStoreISREnd - recorder busy! See code comment."); + return; + } + + if (nISRactive == 0) + { + prvTraceError("Unmatched call to vTraceStoreISREnd (nISRactive == 0, expected > 0)"); + return; + } + + trcCRITICAL_SECTION_BEGIN(); + isPendingContextSwitch |= pendingISR; /* Is there a pending context switch right now? */ + nISRactive--; + if (nISRactive > 0) + { + /* Return to another ISR */ + type = TS_ISR_RESUME; + hnd8 = prvTraceGet8BitHandle(isrstack[nISRactive - 1]); /* isrstack[nISRactive] is the handle of the ISR we're currently exiting. isrstack[nISRactive - 1] is the handle of the ISR that was executing previously. */ + } + else if ((isPendingContextSwitch == 0) || (prvTraceIsSchedulerSuspended())) + { + /* Return to interrupted task, if no context switch will occur in between. */ + type = TS_TASK_RESUME; + hnd8 = prvTraceGet8BitHandle(handle_of_last_logged_task); + } + + if (type != 0) + { + dts5 = (uint16_t)prvTraceGetDTS(0xFFFF); + ts = (TSEvent*)prvTraceNextFreeEventBufferSlot(); + if (ts != NULL) + { + ts->type = type; + ts->objHandle = hnd8; + ts->dts = dts5; + prvTraceUpdateCounters(); + } + } + + trcCRITICAL_SECTION_END(); +} + +#else + +/* ISR tracing is turned off */ +void prvTraceIncreaseISRActive(void) +{ + if (RecorderDataPtr->recorderActive && handle_of_last_logged_task) + nISRactive++; +} + +void prvTraceDecreaseISRActive(void) +{ + if (RecorderDataPtr->recorderActive && handle_of_last_logged_task) + nISRactive--; +} +#endif /* (TRC_CFG_INCLUDE_ISR_TRACING == 1)*/ + + +/********************************************************************************/ +/* User Event functions */ +/********************************************************************************/ + +#define MAX_ARG_SIZE (4+32) + +#if ((TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1)) +static uint8_t writeInt8(void * buffer, uint8_t i, uint8_t value) +{ + TRACE_ASSERT(buffer != NULL, "writeInt8: buffer == NULL", 0); + + if (i >= MAX_ARG_SIZE) + { + return 255; + } + + ((uint8_t*)buffer)[i] = value; + + if (i + 1 > MAX_ARG_SIZE) + { + return 255; + } + + return ((uint8_t) (i + 1)); +} +#endif + +#if ((TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1)) +static uint8_t writeInt16(void * buffer, uint8_t i, uint16_t value) +{ + TRACE_ASSERT(buffer != NULL, "writeInt16: buffer == NULL", 0); + + /* Align to multiple of 2 */ + while ((i % 2) != 0) + { + if (i >= MAX_ARG_SIZE) + { + return 255; + } + + ((uint8_t*)buffer)[i] = 0; + i++; + } + + if (i + 2 > MAX_ARG_SIZE) + { + return 255; + } + + ((uint16_t*)buffer)[i/2] = value; + + return ((uint8_t) (i + 2)); +} +#endif + +#if ((TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1)) +static uint8_t writeInt32(void * buffer, uint8_t i, uint32_t value) +{ + TRACE_ASSERT(buffer != NULL, "writeInt32: buffer == NULL", 0); + + /* A 32 bit value should begin at an even 4-byte address */ + while ((i % 4) != 0) + { + if (i >= MAX_ARG_SIZE) + { + return 255; + } + + ((uint8_t*)buffer)[i] = 0; + i++; + } + + if (i + 4 > MAX_ARG_SIZE) + { + return 255; + } + + ((uint32_t*)buffer)[i/4] = value; + + return ((uint8_t) (i + 4)); +} +#endif + +#if ((TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1) && (TRC_CFG_INCLUDE_FLOAT_SUPPORT)) +static uint8_t writeFloat(void * buffer, uint8_t i, float value) +{ + TRACE_ASSERT(buffer != NULL, "writeFloat: buffer == NULL", 0); + + /* A 32 bit value should begin at an even 4-byte address */ + while ((i % 4) != 0) + { + if (i >= MAX_ARG_SIZE) + { + return 255; + } + + ((uint8_t*)buffer)[i] = 0; + i++; + } + + if (i + 4 > MAX_ARG_SIZE) + { + return 255; + } + + ((float*)buffer)[i/4] = value; + + return i + 4; +} +#endif + +#if ((TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1) && (TRC_CFG_INCLUDE_FLOAT_SUPPORT)) +static uint8_t writeDouble(void * buffer, uint8_t i, double value) +{ + uint32_t * dest; + uint32_t * src = (uint32_t*)&value; + + TRACE_ASSERT(buffer != NULL, "writeDouble: buffer == NULL", 0); + + /* The double is written as two 32 bit values, and should begin at an even + 4-byte address (to avoid having to align with 8 byte) */ + while (i % 4 != 0) + { + if (i >= MAX_ARG_SIZE) + { + return 255; + } + + ((uint8_t*)buffer)[i] = 0; + i++; + } + + if (i + 8 > MAX_ARG_SIZE) + { + return 255; + } + + dest = &(((uint32_t *)buffer)[i/4]); + + dest[0] = src[0]; + dest[1] = src[1]; + + return i + 8; +} +#endif + +/******************************************************************************* + * prvTraceUserEventFormat + * + * Parses the format string and stores the arguments in the buffer. + ******************************************************************************/ +#if ((TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1)) +static uint8_t prvTraceUserEventFormat(const char* formatStr, va_list vl, uint8_t* buffer, uint8_t byteOffset) +{ + uint16_t formatStrIndex = 0; + uint8_t argCounter = 0; + uint8_t i = byteOffset; + + while (formatStr[formatStrIndex] != '\0') + { + if (formatStr[formatStrIndex] == '%') + { + argCounter++; + + if (argCounter > 15) + { + prvTraceError("vTracePrintF - Too many arguments, max 15 allowed!"); + return 0; + } + + formatStrIndex++; + + while ((formatStr[formatStrIndex] >= '0' && formatStr[formatStrIndex] <= '9') || formatStr[formatStrIndex] == '#' || formatStr[formatStrIndex] == '.') + formatStrIndex++; + + if (formatStr[formatStrIndex] != '\0') + { + switch (formatStr[formatStrIndex]) + { + case 'd': i = writeInt32( buffer, + i, + (uint32_t)va_arg(vl, uint32_t)); + break; + case 'x': + case 'X': + case 'u': i = writeInt32( buffer, + i, + (uint32_t)va_arg(vl, uint32_t)); + break; + case 's': i = writeInt16( buffer, + i, + xTraceRegisterString((char*)va_arg(vl, char*))); + break; + +#if (TRC_CFG_INCLUDE_FLOAT_SUPPORT) + /* Yes, "double" as type also in the float + case. This since "float" is promoted into "double" + by the va_arg stuff. */ + case 'f': i = writeFloat( buffer, + i, + (float)va_arg(vl, double)); + break; +#else + /* No support for floats, but attempt to store a float user event + avoid a possible crash due to float reference. Instead store the + data on uint_32 format (will not be displayed anyway). This is just + to keep va_arg and i consistent. */ + + case 'f': i = writeInt32( buffer, + i, + (uint32_t)va_arg(vl, double)); + break; +#endif + case 'l': + formatStrIndex++; + switch (formatStr[formatStrIndex]) + { +#if (TRC_CFG_INCLUDE_FLOAT_SUPPORT) + case 'f': i = writeDouble(buffer, + i, + (double)va_arg(vl, double)); + break; +#else + /* No support for floats, but attempt to store a float user event + avoid a possible crash due to float reference. Instead store the + data on uint_32 format (will not be displayed anyway). This is just + to keep va_arg and i consistent. */ + case 'f': i = writeInt32( buffer, /* In this case, the value will not be shown anyway */ + i, + (uint32_t)va_arg(vl, double)); + + i = writeInt32( buffer, /* Do it twice, to write in total 8 bytes */ + i, + (uint32_t)va_arg(vl, double)); + break; +#endif + + } + break; + case 'h': + formatStrIndex++; + switch (formatStr[formatStrIndex]) + { + case 'd': i = writeInt16( buffer, + i, + (uint16_t)va_arg(vl, uint32_t)); + break; + case 'u': i = writeInt16( buffer, + i, + (uint16_t)va_arg(vl, uint32_t)); + break; + } + break; + case 'b': + formatStrIndex++; + switch (formatStr[formatStrIndex]) + { + case 'd': i = writeInt8( buffer, + i, + (uint8_t)va_arg(vl, uint32_t)); + break; + + case 'u': i = writeInt8( buffer, + i, + (uint8_t)va_arg(vl, uint32_t)); + break; + } + break; + } + } + else + break; + } + formatStrIndex++; + if (i == 255) + { + prvTraceError("vTracePrintF - Too large arguments, max 32 byte allowed!"); + return 0; + } + } + return (uint8_t)(i+3)/4; +} +#endif + +/******************************************************************************* + * prvTraceClearChannelBuffer + * + * Clears a number of items in the channel buffer, starting from nextSlotToWrite. + ******************************************************************************/ +#if ((TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1) && (TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER == 1)) +static void prvTraceClearChannelBuffer(uint32_t count) +{ + uint32_t slots; + + TRACE_ASSERT((TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE) >= count, + "prvTraceClearChannelBuffer: TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE is too small to handle this event.", TRC_UNUSED); + + /* Check if we're close to the end of the buffer */ + if (RecorderDataPtr->userEventBuffer.nextSlotToWrite + count > (TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE)) + { + slots = (TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE) - RecorderDataPtr->userEventBuffer.nextSlotToWrite; /* Number of slots before end of buffer */ + (void)memset(&RecorderDataPtr->userEventBuffer.channelBuffer[RecorderDataPtr->userEventBuffer.nextSlotToWrite], 0, slots); + (void)memset(&RecorderDataPtr->userEventBuffer.channelBuffer[0], 0, (count - slots)); + } + else + (void)memset(&RecorderDataPtr->userEventBuffer.channelBuffer[RecorderDataPtr->userEventBuffer.nextSlotToWrite], 0, count); +} +#endif + +/******************************************************************************* + * prvTraceCopyToDataBuffer + * + * Copies a number of items to the data buffer, starting from nextSlotToWrite. + ******************************************************************************/ +#if ((TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1) && (TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER == 1)) +static void prvTraceCopyToDataBuffer(uint32_t* data, uint32_t count) +{ + uint32_t slots; + + TRACE_ASSERT(data != NULL, + "prvTraceCopyToDataBuffer: data == NULL.", TRC_UNUSED); + TRACE_ASSERT(count <= (TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE), + "prvTraceCopyToDataBuffer: TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE is too small to handle this event.", TRC_UNUSED); + /* Check if we're close to the end of the buffer */ + if (RecorderDataPtr->userEventBuffer.nextSlotToWrite + count > (TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE)) + { + slots = (TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE) - RecorderDataPtr->userEventBuffer.nextSlotToWrite; /* Number of slots before end of buffer */ + (void)memcpy(&RecorderDataPtr->userEventBuffer.dataBuffer[RecorderDataPtr->userEventBuffer.nextSlotToWrite * 4], data, slots * 4); + (void)memcpy(&RecorderDataPtr->userEventBuffer.dataBuffer[0], data + slots, (count - slots) * 4); + } + else + { + (void)memcpy(&RecorderDataPtr->userEventBuffer.dataBuffer[RecorderDataPtr->userEventBuffer.nextSlotToWrite * 4], data, count * 4); + } +} +#endif + +/******************************************************************************* + * prvTraceUBHelper1 + * + * Calls on prvTraceUserEventFormat() to do the actual formatting, then goes on + * to the next helper function. + ******************************************************************************/ +#if ((TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1) && (TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER == 1)) +static void prvTraceUBHelper1(traceUBChannel channel, traceString eventLabel, traceString formatLabel, va_list vl) +{ + uint32_t data[(3 + MAX_ARG_SIZE) / 4]; + uint8_t byteOffset = 4; /* Need room for timestamp */ + uint8_t noOfSlots; + + if (channel == 0) + { + /* We are dealing with an unknown channel format pair */ + byteOffset = (uint8_t)(byteOffset + 4); /* Also need room for channel and format */ + ((uint16_t*)data)[2] = eventLabel; + ((uint16_t*)data)[3] = formatLabel; + } + + noOfSlots = prvTraceUserEventFormat((char*)&(RecorderDataPtr->SymbolTable.symbytes[formatLabel+4]), vl, (uint8_t*)data, byteOffset); + + prvTraceUBHelper2(channel, data, noOfSlots); +} +#endif + +/******************************************************************************* + * prvTraceUBHelper2 + * + * This function simply copies the data buffer to the actual user event buffer. + ******************************************************************************/ +#if ((TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1) && (TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER == 1)) +static void prvTraceUBHelper2(traceUBChannel channel, uint32_t* data, uint32_t noOfSlots) +{ + static uint32_t old_timestamp = 0; + uint32_t old_nextSlotToWrite = 0; + + TRACE_ALLOC_CRITICAL_SECTION(); + + TRACE_ASSERT((TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE) >= noOfSlots, "prvTraceUBHelper2: TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE is too small to handle this event.", TRC_UNUSED); + + trcCRITICAL_SECTION_BEGIN(); + /* Store the timestamp */ + prvTracePortGetTimeStamp(data); + + if (*data < old_timestamp) + { + RecorderDataPtr->userEventBuffer.wraparoundCounter++; + } + + old_timestamp = *data; + + /* Start by erasing any information in the channel buffer */ + prvTraceClearChannelBuffer(noOfSlots); + + prvTraceCopyToDataBuffer(data, noOfSlots); /* Will wrap around the data if necessary */ + + old_nextSlotToWrite = RecorderDataPtr->userEventBuffer.nextSlotToWrite; /* Save the index that we want to write the channel data at when we're done */ + RecorderDataPtr->userEventBuffer.nextSlotToWrite = (RecorderDataPtr->userEventBuffer.nextSlotToWrite + noOfSlots) % (TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE); /* Make sure we never end up outside the buffer */ + + /* Write to the channel buffer to indicate that this user event is ready to be used */ + if (channel != 0) + { + RecorderDataPtr->userEventBuffer.channelBuffer[old_nextSlotToWrite] = channel; + } + else + { + /* 0xFF indicates that this is not a normal channel id */ + RecorderDataPtr->userEventBuffer.channelBuffer[old_nextSlotToWrite] = (traceUBChannel)0xFF; + } + trcCRITICAL_SECTION_END(); +} +#endif + +/******************************************************************************* + * xTraceRegisterUBChannel + * + * Registers a channel for Separated User Events, i.e., those stored in the + * separate user event buffer. + * + * Note: Only available if TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER is enabled in + * trcSnapshotConfig.h + ******************************************************************************/ +#if ((TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1) && (TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER == 1)) +traceUBChannel xTraceRegisterUBChannel(traceString channel, traceString formatStr) +{ + uint8_t i; + traceUBChannel retVal = 0; + + TRACE_ALLOC_CRITICAL_SECTION(); + + TRACE_ASSERT(formatStr != 0, "xTraceRegisterChannelFormat: formatStr == 0", (traceUBChannel)0); + + trcCRITICAL_SECTION_BEGIN(); + for (i = 1; i <= (TRC_CFG_UB_CHANNELS); i++) /* Size of the channels buffer is TRC_CFG_UB_CHANNELS + 1. Index 0 is unused. */ + { + if(RecorderDataPtr->userEventBuffer.channels[i].name == 0 && RecorderDataPtr->userEventBuffer.channels[i].defaultFormat == 0) + { + /* Found empty slot */ + RecorderDataPtr->userEventBuffer.channels[i].name = channel; + RecorderDataPtr->userEventBuffer.channels[i].defaultFormat = formatStr; + retVal = (traceUBChannel)i; + break; + } + + if (RecorderDataPtr->userEventBuffer.channels[i].name == channel && RecorderDataPtr->userEventBuffer.channels[i].defaultFormat == formatStr) + { + /* Found a match */ + retVal = (traceUBChannel)i; + break; + } + } + trcCRITICAL_SECTION_END(); + + return retVal; +} +#endif + +/****************************************************************************** + * vTraceUBData + * + * Slightly faster version of vTracePrintF() due to no lookups. + * + * Note: This is only available if TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER is + * enabled in trcSnapshotConfig.h + ******************************************************************************/ +#if ((TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1) && (TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER == 1)) +void vTraceUBData(traceUBChannel channelPair, ...) +{ + va_list vl; + + TRACE_ASSERT(channelPair != 0, "vTraceUBData: Not a valid traceUBChannel!", TRC_UNUSED); + + va_start(vl, channelPair); + vTraceUBData_Helper(channelPair, vl); + va_end(vl); +} +#endif + +/* Extracts the channel name and format string from the traceUBChannel, then calls prvTraceUBHelper1. */ +#if ((TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1) && (TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER == 1)) +void vTraceUBData_Helper(traceUBChannel channelPair, va_list vl) +{ + traceString channel; + traceString formatStr; + + TRACE_ASSERT(channelPair != 0, "vTraceUBData_Helper: channelPair == 0", TRC_UNUSED); + TRACE_ASSERT(channelPair <= (TRC_CFG_UB_CHANNELS), "vTraceUBData_Helper: ", TRC_UNUSED); + + channel = RecorderDataPtr->userEventBuffer.channels[channelPair].name; + formatStr = RecorderDataPtr->userEventBuffer.channels[channelPair].defaultFormat; + + prvTraceUBHelper1(channelPair, channel, formatStr, vl); +} +#endif + +/****************************************************************************** + * vTraceUBEvent + * + * Slightly faster version of ... due to no lookups. + ******************************************************************************/ +#if ((TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1) && (TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER == 1)) +void vTraceUBEvent(traceUBChannel channelPair) +{ + uint32_t data[(3 + MAX_ARG_SIZE) / 4]; + + TRACE_ASSERT(channelPair != 0, "vTraceUBEvent: channelPair == 0", TRC_UNUSED); + TRACE_ASSERT(channelPair <= (TRC_CFG_UB_CHANNELS), "vTraceUBEvent: ", TRC_UNUSED); + + prvTraceUBHelper2(channelPair, data, 1); /* Only need one slot for timestamp */ +} +#endif + +/****************************************************************************** + * vTracePrintF + * + * Generates User Event with formatted text and data, similar to a "printf". + * It is very fast compared to a normal "printf" since this function only + * stores the arguments. The actual formatting is done + * on the host PC when the trace is displayed in the viewer tool. + * + * User Event labels are created using xTraceRegisterString. + * Example: + * + * traceString adc_uechannel = xTraceRegisterString("ADC User Events"); + * ... + * vTracePrintF(adc_uechannel, + * "ADC channel %d: %lf volts", + * ch, (double)adc_reading/(double)scale); + * + * This can be combined into one line, if desired, but this is slower: + * + * vTracePrintF(xTraceRegisterString("ADC User Events"), + * "ADC channel %d: %lf volts", + * ch, (double)adc_reading/(double)scale); + * + * Calling xTraceRegisterString multiple times will not create duplicate entries, but + * it is of course faster to just do it once, and then keep the handle for later + * use. If you don't have any data arguments, only a text label/string, it is + * better to use vTracePrint - it is faster. + * + * Format specifiers supported: + * %d - 32 bit signed integer + * %u - 32 bit unsigned integer + * %f - 32 bit float + * %s - string (is copied to the recorder symbol table) + * %hd - 16 bit signed integer + * %hu - 16 bit unsigned integer + * %bd - 8 bit signed integer + * %bu - 8 bit unsigned integer + * %lf - double-precision float (Note! See below...) + * + * Up to 15 data arguments are allowed, with a total size of maximum 32 byte. + * In case this is exceeded, the user event is changed into an error message. + * + * The data is stored in trace buffer, and is packed to allow storing multiple + * smaller data entries in the same 4-byte record, e.g., four 8-bit values. + * A string requires two bytes, as the symbol table is limited to 64K. Storing + * a double (%lf) uses two records, so this is quite costly. Use float (%f) + * unless the higher precision is really necessary. + * + * Note that the double-precision float (%lf) assumes a 64 bit double + * representation. This does not seem to be the case on e.g. PIC24 and PIC32. + * Before using a %lf argument on a 16-bit MCU, please verify that + * "sizeof(double)" actually gives 8 as expected. If not, use %f instead. + ******************************************************************************/ +#if ((TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1)) +void vTracePrintF(traceString eventLabel, const char* formatStr, ...) +{ + va_list vl; + + va_start(vl, formatStr); + vTracePrintF_Helper(eventLabel, formatStr, vl); + va_end(vl); +} +#endif + +#if ((TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1)) +void vTracePrintF_Helper(traceString eventLabel, const char* formatStr, va_list vl) +{ +#if (TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER == 0) + uint32_t noOfSlots; + UserEvent* ue1; + uint32_t tempDataBuffer[(3 + MAX_ARG_SIZE) / 4]; + TRACE_ALLOC_CRITICAL_SECTION(); + + TRACE_ASSERT(formatStr != NULL, "vTracePrintF_Helper: formatStr == NULL", TRC_UNUSED); + + trcCRITICAL_SECTION_BEGIN(); + + if (RecorderDataPtr->recorderActive && handle_of_last_logged_task) + { + /* First, write the "primary" user event entry in the local buffer, but + let the event type be "EVENT_BEING_WRITTEN" for now...*/ + + ue1 = (UserEvent*)(&tempDataBuffer[0]); + + ue1->type = EVENT_BEING_WRITTEN; /* Update this as the last step */ + + noOfSlots = prvTraceUserEventFormat(formatStr, vl, (uint8_t*)tempDataBuffer, 4); + + /* Store the format string, with a reference to the channel symbol */ + ue1->payload = prvTraceOpenSymbol(formatStr, eventLabel); + + ue1->dts = (uint8_t)prvTraceGetDTS(0xFF); + + /* prvTraceGetDTS might stop the recorder in some cases... */ + if (RecorderDataPtr->recorderActive) + { + + /* If the data does not fit in the remaining main buffer, wrap around to + 0 if allowed, otherwise stop the recorder and quit). */ + if (RecorderDataPtr->nextFreeIndex + noOfSlots > RecorderDataPtr->maxEvents) + { + #if (TRC_CFG_SNAPSHOT_MODE == TRC_SNAPSHOT_MODE_RING_BUFFER) + (void)memset(& RecorderDataPtr->eventData[RecorderDataPtr->nextFreeIndex * 4], + 0, + (RecorderDataPtr->maxEvents - RecorderDataPtr->nextFreeIndex)*4); + RecorderDataPtr->nextFreeIndex = 0; + RecorderDataPtr->bufferIsFull = 1; + #else + + /* Stop recorder, since the event data will not fit in the + buffer and not circular buffer in this case... */ + vTraceStop(); + #endif + } + + /* Check if recorder has been stopped (i.e., vTraceStop above) */ + if (RecorderDataPtr->recorderActive) + { + /* Check that the buffer to be overwritten does not contain any user + events that would be partially overwritten. If so, they must be "killed" + by replacing the user event and following data with NULL events (i.e., + using a memset to zero).*/ + #if (TRC_CFG_SNAPSHOT_MODE == TRC_SNAPSHOT_MODE_RING_BUFFER) + prvCheckDataToBeOverwrittenForMultiEntryEvents((uint8_t)noOfSlots); + #endif + /* Copy the local buffer to the main buffer */ + (void)memcpy(& RecorderDataPtr->eventData[RecorderDataPtr->nextFreeIndex * 4], + tempDataBuffer, + noOfSlots * 4); + + /* Update the event type, i.e., number of data entries following the + main USER_EVENT entry (Note: important that this is after the memcpy, + but within the critical section!)*/ + RecorderDataPtr->eventData[RecorderDataPtr->nextFreeIndex * 4] = + (uint8_t) ( USER_EVENT + noOfSlots - 1 ); + + /* Update the main buffer event index (already checked that it fits in + the buffer, so no need to check for wrapping)*/ + + RecorderDataPtr->nextFreeIndex += noOfSlots; + RecorderDataPtr->numEvents += noOfSlots; + + if (RecorderDataPtr->nextFreeIndex >= (TRC_CFG_EVENT_BUFFER_SIZE)) + { + #if (TRC_CFG_SNAPSHOT_MODE == TRC_SNAPSHOT_MODE_RING_BUFFER) + /* We have reached the end, but this is a ring buffer. Start from the beginning again. */ + RecorderDataPtr->bufferIsFull = 1; + RecorderDataPtr->nextFreeIndex = 0; + #else + /* We have reached the end so we stop. */ + vTraceStop(); + #endif + } + } + + #if (TRC_CFG_SNAPSHOT_MODE == TRC_SNAPSHOT_MODE_RING_BUFFER) + /* Make sure the next entry is cleared correctly */ + prvCheckDataToBeOverwrittenForMultiEntryEvents(1); + #endif + + } + } + trcCRITICAL_SECTION_END(); + +#elif (TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER == 1) + /* Use the separate user event buffer */ + traceString formatLabel; + traceUBChannel channel; + + if (RecorderDataPtr->recorderActive && handle_of_last_logged_task) + { + formatLabel = xTraceRegisterString(formatStr); + + channel = xTraceRegisterUBChannel(eventLabel, formatLabel); + + prvTraceUBHelper1(channel, eventLabel, formatLabel, vl); + } +#endif +} +#endif + +/****************************************************************************** + * vTracePrint + * + * Basic user event + * + * Generates a User Event with a text label. The label is created/looked up + * in the symbol table using xTraceRegisterString. + ******************************************************************************/ +#if ((TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1)) +void vTracePrint(traceString chn, const char* str) +{ +#if (TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER == 0) + UserEvent* ue; + uint8_t dts1; + TRACE_ALLOC_CRITICAL_SECTION(); + + trcCRITICAL_SECTION_BEGIN(); + if (RecorderDataPtr->recorderActive && handle_of_last_logged_task) + { + dts1 = (uint8_t)prvTraceGetDTS(0xFF); + ue = (UserEvent*) prvTraceNextFreeEventBufferSlot(); + if (ue != NULL) + { + ue->dts = dts1; + ue->type = USER_EVENT; + ue->payload = prvTraceOpenSymbol(str, chn); + prvTraceUpdateCounters(); + } + } + trcCRITICAL_SECTION_END(); + +#elif (TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER == 1) + traceUBChannel channel; + uint32_t noOfSlots = 1; + uint32_t tempDataBuffer[(3 + MAX_ARG_SIZE) / 4]; + if (RecorderDataPtr->recorderActive && handle_of_last_logged_task) + { + traceString trcStr = prvTraceOpenSymbol(str, chn); + channel = xTraceRegisterUBChannel(chn, trcStr); + + if (channel == 0) + { + /* We are dealing with an unknown channel format pair */ + noOfSlots++; /* Also need room for channel and format */ + ((uint16_t*)tempDataBuffer)[2] = chn; + ((uint16_t*)tempDataBuffer)[3] = trcStr; + } + + prvTraceUBHelper2(channel, tempDataBuffer, noOfSlots); + } +#endif +} +#endif + +/******************************************************************************* + * xTraceRegisterString + * + * Register strings in the recorder, e.g. for names of user event channels. + * + * Example: + * myEventHandle = xTraceRegisterString("MyUserEvent"); + * ... + * vTracePrintF(myEventHandle, "My value is: %d", myValue); + ******************************************************************************/ +#if ((TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1)) +traceString xTraceRegisterString(const char* label) +{ + TRACE_ASSERT(label != NULL, "xTraceRegisterString: label == NULL", (traceString)0); + TRACE_ASSERT(RecorderDataPtr != NULL, "Recorder not initialized, call vTraceEnable() first!", (traceHandle)0); + return prvTraceOpenSymbol(label, 0); +} +#endif + + +#if ((!defined TRC_CFG_INCLUDE_READY_EVENTS) || (TRC_CFG_INCLUDE_READY_EVENTS == 1)) + +void prvTraceSetReadyEventsEnabled(int status) +{ + readyEventsEnabled = status; +} + +/******************************************************************************* + * prvTraceStoreTaskReady + * + * This function stores a ready state for the task handle sent in as parameter. + ******************************************************************************/ +void prvTraceStoreTaskReady(traceHandle handle) +{ + uint16_t dts3; + TREvent* tr; + uint8_t hnd8; + + TRACE_ALLOC_CRITICAL_SECTION(); + + if (handle == 0) + { + /* On FreeRTOS v7.3.0, this occurs when creating tasks due to a bad + placement of the trace macro. In that case, the events are ignored. */ + return; + } + + if (! readyEventsEnabled) + { + /* When creating tasks, ready events are also created. If creating + a "hidden" (not traced) task, we must therefore disable recording + of ready events to avoid an undesired ready event... */ + return; + } + + TRACE_ASSERT(handle <= (TRC_CFG_NTASK), "prvTraceStoreTaskReady: Invalid value for handle", TRC_UNUSED); + + if (recorder_busy) + { + /************************************************************************* + * This occurs if an ISR calls a trace function, preempting a previous + * trace call that is being processed in a different ISR or task. + * If this occurs, there is probably a problem in the definition of the + * recorder's internal critical sections (TRACE_ENTER_CRITICAL_SECTION and + * TRACE_EXIT_CRITICAL_SECTION). They must disable the RTOS tick interrupt + * and any other ISRs that calls the trace recorder directly or via + * traced kernel functions. The ARM port disables all interrupts using the + * PRIMASK register to avoid this issue. + *************************************************************************/ + prvTraceError("Recorder busy - high priority ISR using syscall? (1)"); + return; + } + + trcCRITICAL_SECTION_BEGIN(); + if (RecorderDataPtr->recorderActive) /* Need to repeat this check! */ + { + dts3 = (uint16_t)prvTraceGetDTS(0xFFFF); + hnd8 = prvTraceGet8BitHandle(handle); + tr = (TREvent*)prvTraceNextFreeEventBufferSlot(); + if (tr != NULL) + { + tr->type = DIV_TASK_READY; + tr->dts = dts3; + tr->objHandle = hnd8; + prvTraceUpdateCounters(); + } + } + trcCRITICAL_SECTION_END(); +} +#endif + +/******************************************************************************* + * prvTraceStoreLowPower + * + * This function stores a low power state. + ******************************************************************************/ +void prvTraceStoreLowPower(uint32_t flag) +{ + uint16_t dts; + LPEvent* lp; + TRACE_ALLOC_CRITICAL_SECTION(); + + TRACE_ASSERT(flag <= 1, "prvTraceStoreLowPower: Invalid flag value", TRC_UNUSED); + + if (recorder_busy) + { + /************************************************************************* + * This occurs if an ISR calls a trace function, preempting a previous + * trace call that is being processed in a different ISR or task. + * If this occurs, there is probably a problem in the definition of the + * recorder's internal critical sections (TRACE_ENTER_CRITICAL_SECTION and + * TRACE_EXIT_CRITICAL_SECTION). They must disable the RTOS tick interrupt + * and any other ISRs that calls the trace recorder directly or via + * traced kernel functions. The ARM port disables all interrupts using the + * PRIMASK register to avoid this issue. + *************************************************************************/ + prvTraceError("Recorder busy - high priority ISR using syscall? (1)"); + return; + } + + trcCRITICAL_SECTION_BEGIN(); + if (RecorderDataPtr->recorderActive) + { + dts = (uint16_t)prvTraceGetDTS(0xFFFF); + lp = (LPEvent*)prvTraceNextFreeEventBufferSlot(); + if (lp != NULL) + { + lp->type = (uint8_t) (LOW_POWER_BEGIN + ( uint8_t ) flag); /* BEGIN or END depending on flag */ + lp->dts = dts; + prvTraceUpdateCounters(); + } + } + trcCRITICAL_SECTION_END(); +} + +/******************************************************************************* + * vTraceStoreMemMangEvent + * + * This function stores malloc and free events. Each call requires two records, + * for size and address respectively. The event code parameter (ecode) is applied + * to the first record (size) and the following address record gets event + * code "ecode + 1", so make sure this is respected in the event code table. + * Note: On "free" calls, the signed_size parameter should be negative. + ******************************************************************************/ +#if (TRC_CFG_INCLUDE_MEMMANG_EVENTS == 1) +#if (TRC_CFG_SCHEDULING_ONLY == 0) +void vTraceStoreMemMangEvent(uint32_t ecode, uint32_t address, int32_t signed_size) +{ + uint8_t dts1; + MemEventSize * ms; + MemEventAddr * ma; + uint16_t size_low; + uint16_t addr_low; + uint8_t addr_high; + uint32_t size; + TRACE_ALLOC_CRITICAL_SECTION(); + + if (RecorderDataPtr == NULL) + { + /* Occurs in vTraceInitTraceData, if using dynamic allocation. */ + return; + } + + if (signed_size < 0) + size = (uint32_t)(- signed_size); + else + size = (uint32_t)(signed_size); + + trcCRITICAL_SECTION_BEGIN(); + + heapMemUsage = heapMemUsage + (uint32_t)signed_size; + + if (RecorderDataPtr->recorderActive) + { + dts1 = (uint8_t)prvTraceGetDTS(0xFF); + size_low = (uint16_t)prvTraceGetParam(0xFFFF, size); + ms = (MemEventSize *)prvTraceNextFreeEventBufferSlot(); + + if (ms != NULL) + { + ms->dts = dts1; + ms->type = NULL_EVENT; /* Updated when all events are written */ + ms->size = size_low; + prvTraceUpdateCounters(); + + /* Storing a second record with address (signals "failed" if null) */ + #if (TRC_CFG_HEAP_SIZE_BELOW_16M) + /* If the heap address range is within 16 MB, i.e., the upper 8 bits + of addresses are constant, this optimization avoids storing an extra + event record by ignoring the upper 8 bit of the address */ + addr_low = address & 0xFFFF; + addr_high = (address >> 16) & 0xFF; + #else + /* The whole 32 bit address is stored using a second event record + for the upper 16 bit */ + addr_low = (uint16_t)prvTraceGetParam(0xFFFF, address); + addr_high = 0; + #endif + + ma = (MemEventAddr *) prvTraceNextFreeEventBufferSlot(); + if (ma != NULL) + { + ma->addr_low = addr_low; + ma->addr_high = addr_high; + ma->type = (uint8_t) (ecode + 1); /* Note this! */ + ms->type = (uint8_t) ecode; + prvTraceUpdateCounters(); + RecorderDataPtr->heapMemUsage = heapMemUsage; + } + } + } + trcCRITICAL_SECTION_END(); +} +#endif /* TRC_CFG_SCHEDULING_ONLY */ +#endif + +/******************************************************************************* + * prvTraceStoreKernelCall + * + * This is the main integration point for storing kernel calls, and + * is called by the hooks in trcKernelHooks.h (see trcKernelPort.h for event codes). + ******************************************************************************/ +#if (TRC_CFG_SCHEDULING_ONLY == 0) +void prvTraceStoreKernelCall(uint32_t ecode, traceObjectClass objectClass, uint32_t objectNumber) +{ + KernelCall * kse; + uint16_t dts1; + uint8_t hnd8; + TRACE_ALLOC_CRITICAL_SECTION(); + + TRACE_ASSERT(ecode < 0xFF, "prvTraceStoreKernelCall: ecode >= 0xFF", TRC_UNUSED); + TRACE_ASSERT(objectClass < TRACE_NCLASSES, "prvTraceStoreKernelCall: objectClass >= TRACE_NCLASSES", TRC_UNUSED); + TRACE_ASSERT(objectNumber <= RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[objectClass], "prvTraceStoreKernelCall: Invalid value for objectNumber", TRC_UNUSED); + + if (recorder_busy) + { + /************************************************************************* + * This occurs if an ISR calls a trace function, preempting a previous + * trace call that is being processed in a different ISR or task. + * If this occurs, there is probably a problem in the definition of the + * recorder's internal critical sections (TRACE_ENTER_CRITICAL_SECTION and + * TRACE_EXIT_CRITICAL_SECTION). They must disable the RTOS tick interrupt + * and any other ISRs that calls the trace recorder directly or via + * traced kernel functions. The ARM port disables all interrupts using the + * PRIMASK register to avoid this issue. + *************************************************************************/ + prvTraceError("Recorder busy - high priority ISR using syscall? (2)"); + return; + } + + if (handle_of_last_logged_task == 0) + { + return; + } + + trcCRITICAL_SECTION_BEGIN(); + if (RecorderDataPtr->recorderActive) + { + dts1 = (uint16_t)prvTraceGetDTS(0xFFFF); + hnd8 = prvTraceGet8BitHandle((traceHandle)objectNumber); + kse = (KernelCall*) prvTraceNextFreeEventBufferSlot(); + if (kse != NULL) + { + kse->dts = dts1; + kse->type = (uint8_t)ecode; + kse->objHandle = hnd8; + prvTraceUpdateCounters(); + } + } + trcCRITICAL_SECTION_END(); +} +#endif /* TRC_CFG_SCHEDULING_ONLY */ + +/******************************************************************************* + * prvTraceStoreKernelCallWithParam + * + * Used for storing kernel calls with a handle and a numeric parameter. If the + * numeric parameter does not fit in one byte, and extra XPS event is inserted + * before the kernel call event containing the three upper bytes. + ******************************************************************************/ +#if (TRC_CFG_SCHEDULING_ONLY == 0) +void prvTraceStoreKernelCallWithParam(uint32_t evtcode, + traceObjectClass objectClass, + uint32_t objectNumber, + uint32_t param) +{ + KernelCallWithParamAndHandle * kse; + uint8_t dts2; + uint8_t hnd8; + uint8_t p8; + TRACE_ALLOC_CRITICAL_SECTION(); + + TRACE_ASSERT(evtcode < 0xFF, "prvTraceStoreKernelCallWithParam: evtcode >= 0xFF", TRC_UNUSED); + TRACE_ASSERT(objectClass < TRACE_NCLASSES, "prvTraceStoreKernelCallWithParam: objectClass >= TRACE_NCLASSES", TRC_UNUSED); + TRACE_ASSERT(objectNumber <= RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[objectClass], "prvTraceStoreKernelCallWithParam: Invalid value for objectNumber", TRC_UNUSED); + + if (recorder_busy) + { + /************************************************************************* + * This occurs if an ISR calls a trace function, preempting a previous + * trace call that is being processed in a different ISR or task. + * If this occurs, there is probably a problem in the definition of the + * recorder's internal critical sections (TRACE_ENTER_CRITICAL_SECTION and + * TRACE_EXIT_CRITICAL_SECTION). They must disable the RTOS tick interrupt + * and any other ISRs that calls the trace recorder directly or via + * traced kernel functions. The ARM port disables all interrupts using the + * PRIMASK register to avoid this issue. + *************************************************************************/ + prvTraceError("Recorder busy - high priority ISR using syscall? (3)"); + return; + } + + trcCRITICAL_SECTION_BEGIN(); + if (RecorderDataPtr->recorderActive && handle_of_last_logged_task) + { + dts2 = (uint8_t)prvTraceGetDTS(0xFF); + p8 = (uint8_t) prvTraceGetParam(0xFF, param); + hnd8 = prvTraceGet8BitHandle((traceHandle)objectNumber); + kse = (KernelCallWithParamAndHandle*) prvTraceNextFreeEventBufferSlot(); + if (kse != NULL) + { + kse->dts = dts2; + kse->type = (uint8_t)evtcode; + kse->objHandle = hnd8; + kse->param = p8; + prvTraceUpdateCounters(); + } + } + trcCRITICAL_SECTION_END(); +} +#endif /* TRC_CFG_SCHEDULING_ONLY */ + + +/******************************************************************************* + * prvTraceGetParam + * + * Used for storing extra bytes for kernel calls with numeric parameters. + * + * May only be called within a critical section! + ******************************************************************************/ +#if (TRC_CFG_SCHEDULING_ONLY == 0) +static uint32_t prvTraceGetParam(uint32_t param_max, uint32_t param) +{ + XPSEvent* xps; + + TRACE_ASSERT(param_max == 0xFF || param_max == 0xFFFF, + "prvTraceGetParam: Invalid value for param_max", param); + + if (param <= param_max) + { + return param; + } + else + { + xps = (XPSEvent*) prvTraceNextFreeEventBufferSlot(); + if (xps != NULL) + { + xps->type = DIV_XPS; + xps->xps_8 = (uint8_t)((param & (0xFF00 & ~param_max)) >> 8); + xps->xps_16 = (uint16_t)((param & (0xFFFF0000 & ~param_max)) >> 16); + prvTraceUpdateCounters(); + } + + return param & param_max; + } +} +#endif + +/******************************************************************************* + * prvTraceStoreKernelCallWithNumericParamOnly + * + * Used for storing kernel calls with numeric parameters only. This is + * only used for traceTASK_DELAY and traceDELAY_UNTIL at the moment. + ******************************************************************************/ +#if (TRC_CFG_SCHEDULING_ONLY == 0) +void prvTraceStoreKernelCallWithNumericParamOnly(uint32_t evtcode, uint32_t param) +{ + KernelCallWithParam16 * kse; + uint8_t dts6; + uint16_t restParam; + TRACE_ALLOC_CRITICAL_SECTION(); + + restParam = 0; + + TRACE_ASSERT(evtcode < 0xFF, "prvTraceStoreKernelCallWithNumericParamOnly: Invalid value for evtcode", TRC_UNUSED); + + if (recorder_busy) + { + /************************************************************************* + * This occurs if an ISR calls a trace function, preempting a previous + * trace call that is being processed in a different ISR or task. + * If this occurs, there is probably a problem in the definition of the + * recorder's internal critical sections (TRACE_ENTER_CRITICAL_SECTION and + * TRACE_EXIT_CRITICAL_SECTION). They must disable the RTOS tick interrupt + * and any other ISRs that calls the trace recorder directly or via + * traced kernel functions. The ARM port disables all interrupts using the + * PRIMASK register to avoid this issue. + *************************************************************************/ + prvTraceError("Recorder busy - high priority ISR using syscall? (4)"); + return; + } + + trcCRITICAL_SECTION_BEGIN(); + if (RecorderDataPtr->recorderActive && handle_of_last_logged_task) + { + dts6 = (uint8_t)prvTraceGetDTS(0xFF); + restParam = (uint16_t)prvTraceGetParam(0xFFFF, param); + kse = (KernelCallWithParam16*) prvTraceNextFreeEventBufferSlot(); + if (kse != NULL) + { + kse->dts = dts6; + kse->type = (uint8_t)evtcode; + kse->param = restParam; + prvTraceUpdateCounters(); + } + } + trcCRITICAL_SECTION_END(); +} +#endif /* TRC_CFG_SCHEDULING_ONLY */ + +/******************************************************************************* + * prvTraceStoreTaskswitch + * Called by the scheduler from the SWITCHED_OUT hook, and by uiTraceStart. + * At this point interrupts are assumed to be disabled! + ******************************************************************************/ +void prvTraceStoreTaskswitch(traceHandle task_handle) +{ + uint16_t dts3; + TSEvent* ts; + uint8_t hnd8; +#if (TRC_CFG_INCLUDE_ISR_TRACING == 1) + extern int32_t isPendingContextSwitch; +#endif + trcSR_ALLOC_CRITICAL_SECTION_ON_CORTEX_M_ONLY(); + + TRACE_ASSERT(task_handle <= (TRC_CFG_NTASK), + "prvTraceStoreTaskswitch: Invalid value for task_handle", TRC_UNUSED); + + trcCRITICAL_SECTION_BEGIN_ON_CORTEX_M_ONLY(); + + if ((task_handle != handle_of_last_logged_task) && (RecorderDataPtr->recorderActive)) + { +#if (TRC_CFG_INCLUDE_ISR_TRACING == 1) + isPendingContextSwitch = 0; +#endif + + dts3 = (uint16_t)prvTraceGetDTS(0xFFFF); + handle_of_last_logged_task = task_handle; + hnd8 = prvTraceGet8BitHandle(handle_of_last_logged_task); + ts = (TSEvent*)prvTraceNextFreeEventBufferSlot(); + + if (ts != NULL) + { + if (prvTraceGetObjectState(TRACE_CLASS_TASK, + handle_of_last_logged_task) == TASK_STATE_INSTANCE_ACTIVE) + { + ts->type = TS_TASK_RESUME; + } + else + { + ts->type = TS_TASK_BEGIN; + } + + ts->dts = dts3; + ts->objHandle = hnd8; + + prvTraceSetObjectState(TRACE_CLASS_TASK, + handle_of_last_logged_task, + TASK_STATE_INSTANCE_ACTIVE); + + prvTraceUpdateCounters(); + } + } + + trcCRITICAL_SECTION_END_ON_CORTEX_M_ONLY(); +} + +/******************************************************************************* + * prvTraceStoreObjectNameOnCloseEvent + * + * Updates the symbol table with the name of this object from the dynamic + * objects table and stores a "close" event, holding the mapping between handle + * and name (a symbol table handle). The stored name-handle mapping is thus the + * "old" one, valid up until this point. + ******************************************************************************/ +void prvTraceStoreObjectNameOnCloseEvent(uint8_t evtcode, traceHandle handle, + traceObjectClass objectclass) +{ + ObjCloseNameEvent * ce; + const char * name; + traceString idx; + + TRACE_ASSERT(objectclass < TRACE_NCLASSES, + "prvTraceStoreObjectNameOnCloseEvent: objectclass >= TRACE_NCLASSES", TRC_UNUSED); + TRACE_ASSERT(handle <= RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[objectclass], + "prvTraceStoreObjectNameOnCloseEvent: Invalid value for handle", TRC_UNUSED); + + if (RecorderDataPtr->recorderActive) + { + uint8_t hnd8 = prvTraceGet8BitHandle(handle); + name = TRACE_PROPERTY_NAME_GET(objectclass, handle); + idx = prvTraceOpenSymbol(name, 0); + + // Interrupt disable not necessary, already done in trcHooks.h macro + ce = (ObjCloseNameEvent*) prvTraceNextFreeEventBufferSlot(); + if (ce != NULL) + { + ce->type = (uint8_t) evtcode; + ce->objHandle = hnd8; + ce->symbolIndex = idx; + prvTraceUpdateCounters(); + } + } +} + +void prvTraceStoreObjectPropertiesOnCloseEvent(uint8_t evtcode, traceHandle handle, + traceObjectClass objectclass) +{ + ObjClosePropEvent * pe; + + TRACE_ASSERT(objectclass < TRACE_NCLASSES, + "prvTraceStoreObjectPropertiesOnCloseEvent: objectclass >= TRACE_NCLASSES", TRC_UNUSED); + TRACE_ASSERT(handle <= RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[objectclass], + "prvTraceStoreObjectPropertiesOnCloseEvent: Invalid value for handle", TRC_UNUSED); + + if (RecorderDataPtr->recorderActive) + { + // Interrupt disable not necessary, already done in trcHooks.h macro + pe = (ObjClosePropEvent*) prvTraceNextFreeEventBufferSlot(); + if (pe != NULL) + { + if (objectclass == TRACE_CLASS_TASK) + { + pe->arg1 = TRACE_PROPERTY_ACTOR_PRIORITY(objectclass, handle); + } + else + { + pe->arg1 = TRACE_PROPERTY_OBJECT_STATE(objectclass, handle); + } + pe->type = evtcode; + prvTraceUpdateCounters(); + } + } +} + +void prvTraceSetPriorityProperty(uint8_t objectclass, traceHandle id, uint8_t value) +{ + TRACE_ASSERT(objectclass < TRACE_NCLASSES, + "prvTraceSetPriorityProperty: objectclass >= TRACE_NCLASSES", TRC_UNUSED); + TRACE_ASSERT(id <= RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[objectclass], + "prvTraceSetPriorityProperty: Invalid value for id", TRC_UNUSED); + + TRACE_PROPERTY_ACTOR_PRIORITY(objectclass, id) = value; +} + +uint8_t prvTraceGetPriorityProperty(uint8_t objectclass, traceHandle id) +{ + TRACE_ASSERT(objectclass < TRACE_NCLASSES, + "prvTraceGetPriorityProperty: objectclass >= TRACE_NCLASSES", 0); + TRACE_ASSERT(id <= RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[objectclass], + "prvTraceGetPriorityProperty: Invalid value for id", 0); + + return TRACE_PROPERTY_ACTOR_PRIORITY(objectclass, id); +} + +void prvTraceSetObjectState(uint8_t objectclass, traceHandle id, uint8_t value) +{ + TRACE_ASSERT(objectclass < TRACE_NCLASSES, + "prvTraceSetObjectState: objectclass >= TRACE_NCLASSES", TRC_UNUSED); + TRACE_ASSERT(id <= RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[objectclass], + "prvTraceSetObjectState: Invalid value for id", TRC_UNUSED); + + TRACE_PROPERTY_OBJECT_STATE(objectclass, id) = value; +} + +uint8_t prvTraceGetObjectState(uint8_t objectclass, traceHandle id) +{ + TRACE_ASSERT(objectclass < TRACE_NCLASSES, + "prvTraceGetObjectState: objectclass >= TRACE_NCLASSES", 0); + TRACE_ASSERT(id <= RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[objectclass], + "prvTraceGetObjectState: Invalid value for id", 0); + + return TRACE_PROPERTY_OBJECT_STATE(objectclass, id); +} + +void prvTraceSetTaskInstanceFinished(traceHandle handle) +{ + TRACE_ASSERT(handle <= RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[TRACE_CLASS_TASK], + "prvTraceSetTaskInstanceFinished: Invalid value for handle", TRC_UNUSED); + +#if (TRC_CFG_USE_IMPLICIT_IFE_RULES == 1) + TRACE_PROPERTY_OBJECT_STATE(TRACE_CLASS_TASK, handle) = 0; +#endif +} + +/******************************************************************************* + * Static data initializations + ******************************************************************************/ + +/* A set of stacks that keeps track of available object handles for each class. +The stacks are empty initially, meaning that allocation of new handles will be +based on a counter (for each object class). Any delete operation will +return the handle to the corresponding stack, for reuse on the next allocate.*/ +objectHandleStackType objectHandleStacks = { { 0 }, { 0 }, { 0 }, { 0 }, { 0 } }; + +/* Initial TRC_HWTC_COUNT value, for detecting if the time-stamping source is +enabled. If using the OS periodic timer for time-stamping, this might not +have been configured on the earliest events during the startup. */ +uint32_t init_hwtc_count; + +/******************************************************************************* + * RecorderData + * + * The main data structure in snapshot mode, when using the default static memory + * allocation (TRC_RECORDER_BUFFER_ALLOCATION_STATIC). The recorder uses a pointer + * RecorderDataPtr to access the data, to also allow for dynamic or custom data + * allocation (see TRC_CFG_RECORDER_BUFFER_ALLOCATION). + ******************************************************************************/ +#if (TRC_CFG_RECORDER_BUFFER_ALLOCATION == TRC_RECORDER_BUFFER_ALLOCATION_STATIC) +RecorderDataType RecorderData; +#endif + +/******************************************************************************* + * RecorderDataPtr + * + * Pointer to the main data structure, when in snapshot mode. + ******************************************************************************/ +RecorderDataType* RecorderDataPtr = NULL; + +/* This version of the function dynamically allocates the trace data */ +void prvTraceInitTraceData() +{ + + if (RecorderDataPtr == NULL) + { +#if (TRC_CFG_RECORDER_BUFFER_ALLOCATION == TRC_RECORDER_BUFFER_ALLOCATION_STATIC) + RecorderDataPtr = &RecorderData; +#elif (TRC_CFG_RECORDER_BUFFER_ALLOCATION == TRC_RECORDER_BUFFER_ALLOCATION_DYNAMIC) + RecorderDataPtr = (RecorderDataType*)TRACE_MALLOC(sizeof(RecorderDataType)); + if (! RecorderDataPtr) + { + prvTraceError("Failed allocating recorder buffer!"); + return; + } +#elif (TRC_CFG_RECORDER_BUFFER_ALLOCATION == TRC_RECORDER_BUFFER_ALLOCATION_CUSTOM) + if (! RecorderDataPtr) + { + prvTraceError("Recorder data pointer not set! Use vTraceSetRecorderDataBuffer()."); + return; + } +#endif + } + else + { + if (RecorderDataPtr->startmarker0 == 1) + { + /* Already initialized */ + return; + } + } + + init_hwtc_count = TRC_HWTC_COUNT; + + (void)memset(RecorderDataPtr, 0, sizeof(RecorderDataType)); + + RecorderDataPtr->version = TRACE_KERNEL_VERSION; + RecorderDataPtr->minor_version = TRACE_MINOR_VERSION; + RecorderDataPtr->irq_priority_order = TRC_IRQ_PRIORITY_ORDER; + RecorderDataPtr->filesize = sizeof(RecorderDataType); + RecorderDataPtr->maxEvents = (TRC_CFG_EVENT_BUFFER_SIZE); + RecorderDataPtr->debugMarker0 = (int32_t) 0xF0F0F0F0; + RecorderDataPtr->isUsing16bitHandles = TRC_CFG_USE_16BIT_OBJECT_HANDLES; + RecorderDataPtr->isrTailchainingThreshold = TRC_CFG_ISR_TAILCHAINING_THRESHOLD; + + /* This function is kernel specific */ + vTraceInitObjectPropertyTable(); + + RecorderDataPtr->debugMarker1 = (int32_t)0xF1F1F1F1; + RecorderDataPtr->SymbolTable.symTableSize = (TRC_CFG_SYMBOL_TABLE_SIZE); + RecorderDataPtr->SymbolTable.nextFreeSymbolIndex = 1; +#if (TRC_CFG_INCLUDE_FLOAT_SUPPORT == 1) + RecorderDataPtr->exampleFloatEncoding = 1.0f; /* otherwise already zero */ +#endif + RecorderDataPtr->debugMarker2 = (int32_t)0xF2F2F2F2; + prvStrncpy(RecorderDataPtr->systemInfo, "Trace Recorder Demo", 80); + RecorderDataPtr->debugMarker3 = (int32_t)0xF3F3F3F3; + RecorderDataPtr->endmarker0 = 0x0A; + RecorderDataPtr->endmarker1 = 0x0B; + RecorderDataPtr->endmarker2 = 0x0C; + RecorderDataPtr->endmarker3 = 0x0D; + RecorderDataPtr->endmarker4 = 0x71; + RecorderDataPtr->endmarker5 = 0x72; + RecorderDataPtr->endmarker6 = 0x73; + RecorderDataPtr->endmarker7 = 0x74; + RecorderDataPtr->endmarker8 = 0xF1; + RecorderDataPtr->endmarker9 = 0xF2; + RecorderDataPtr->endmarker10 = 0xF3; + RecorderDataPtr->endmarker11 = 0xF4; + +#if TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER + RecorderDataPtr->userEventBuffer.bufferID = 1; + RecorderDataPtr->userEventBuffer.version = 0; + RecorderDataPtr->userEventBuffer.numberOfSlots = (TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE); + RecorderDataPtr->userEventBuffer.numberOfChannels = (TRC_CFG_UB_CHANNELS) + 1; +#endif + + /* Kernel specific initialization of the objectHandleStacks variable */ + vTraceInitObjectHandleStack(); + + + /* Finally, the 12-byte "start markers" are initialized, allowing for + Tracealyzer to find the trace data in a larger RAM dump. + + The start and end markers must be unique, but without proper precautions there + might be a risk of accidental duplicates of the start/end markers, e.g., due to + compiler optimizations. + + The below initialization of the start marker is therefore made in reverse order + and the fields are volatile to ensure this assignment order. This to avoid any + chance of accidental duplicates of this elsewhere in memory. + + Moreover, the fields are set byte-by-byte to avoid endian issues.*/ + + RecorderDataPtr->startmarker11 = 0xF4; + RecorderDataPtr->startmarker10 = 0xF3; + RecorderDataPtr->startmarker9 = 0xF2; + RecorderDataPtr->startmarker8 = 0xF1; + RecorderDataPtr->startmarker7 = 0x74; + RecorderDataPtr->startmarker6 = 0x73; + RecorderDataPtr->startmarker5 = 0x72; + RecorderDataPtr->startmarker4 = 0x71; + RecorderDataPtr->startmarker3 = 0x04; + RecorderDataPtr->startmarker2 = 0x03; + RecorderDataPtr->startmarker1 = 0x02; + RecorderDataPtr->startmarker0 = 0x01; + + if (traceErrorMessage != NULL) + { + // An error was detected before vTraceEnable was called, make sure this is stored in the trace data. + prvStrncpy(RecorderDataPtr->systemInfo, traceErrorMessage, 80); + RecorderDataPtr->internalErrorOccured = 1; + vTraceStop(); + } + + + +#ifdef TRC_PORT_SPECIFIC_INIT + TRC_PORT_SPECIFIC_INIT(); +#endif +} + + +void* prvTraceNextFreeEventBufferSlot(void) +{ + if (! RecorderDataPtr->recorderActive) + { + /* If an XTS or XPS event prior to the main event has filled the buffer + before saving the main event, and store mode is "stop when full". */ + return NULL; + } + + if (RecorderDataPtr->nextFreeIndex >= (TRC_CFG_EVENT_BUFFER_SIZE)) + { + prvTraceError("Attempt to index outside event buffer!"); + return NULL; + } + return (void*)(&RecorderDataPtr->eventData[RecorderDataPtr->nextFreeIndex*4]); +} + +uint16_t uiIndexOfObject(traceHandle objecthandle, uint8_t objectclass) +{ + TRACE_ASSERT(objectclass < TRACE_NCLASSES, + "uiIndexOfObject: Invalid value for objectclass", 0); + TRACE_ASSERT(objecthandle > 0 && objecthandle <= RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[objectclass], + "uiIndexOfObject: Invalid value for objecthandle", 0); + + if ((objectclass < TRACE_NCLASSES) && (objecthandle > 0) && + (objecthandle <= RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[objectclass])) + { + return (uint16_t)(RecorderDataPtr->ObjectPropertyTable.StartIndexOfClass[objectclass] + + (RecorderDataPtr->ObjectPropertyTable.TotalPropertyBytesPerClass[objectclass] * (objecthandle-1))); + } + + prvTraceError("Object table lookup with invalid object handle or object class!"); + return 0; +} + +traceHandle prvTraceGetObjectHandle(traceObjectClass objectclass) +{ + traceHandle handle; + static int indexOfHandle; + + TRACE_ALLOC_CRITICAL_SECTION(); + + TRACE_ASSERT(RecorderDataPtr != NULL, "Recorder not initialized, call vTraceEnable() first!", (traceHandle)0); + + TRACE_ASSERT(objectclass < TRACE_NCLASSES, + "prvTraceGetObjectHandle: Invalid value for objectclass", (traceHandle)0); + + trcCRITICAL_SECTION_BEGIN(); + indexOfHandle = objectHandleStacks.indexOfNextAvailableHandle[objectclass]; + if (objectHandleStacks.objectHandles[indexOfHandle] == 0) + { + /* Zero is used to indicate a never before used handle, i.e., + new slots in the handle stack. The handle slot needs to + be initialized here (starts at 1). */ + objectHandleStacks.objectHandles[indexOfHandle] = + (traceHandle)(1 + indexOfHandle - + objectHandleStacks.lowestIndexOfClass[objectclass]); + } + + handle = objectHandleStacks.objectHandles[indexOfHandle]; + + if (objectHandleStacks.indexOfNextAvailableHandle[objectclass] + > objectHandleStacks.highestIndexOfClass[objectclass]) + { + prvTraceError(pszTraceGetErrorNotEnoughHandles(objectclass)); + handle = 0; + } + else + { + int hndCount; + objectHandleStacks.indexOfNextAvailableHandle[objectclass]++; + + hndCount = objectHandleStacks.indexOfNextAvailableHandle[objectclass] - + objectHandleStacks.lowestIndexOfClass[objectclass]; + + if (hndCount > + objectHandleStacks.handleCountWaterMarksOfClass[objectclass]) + { + objectHandleStacks.handleCountWaterMarksOfClass[objectclass] = + (traceHandle)hndCount; + } + } + trcCRITICAL_SECTION_END(); + + return handle; +} + +void prvTraceFreeObjectHandle(traceObjectClass objectclass, traceHandle handle) +{ + int indexOfHandle; + + TRACE_ASSERT(objectclass < TRACE_NCLASSES, + "prvTraceFreeObjectHandle: Invalid value for objectclass", TRC_UNUSED); + TRACE_ASSERT(handle > 0 && handle <= RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[objectclass], + "prvTraceFreeObjectHandle: Invalid value for handle", TRC_UNUSED); + + /* Check that there is room to push the handle on the stack */ + if ((objectHandleStacks.indexOfNextAvailableHandle[objectclass] - 1) < + objectHandleStacks.lowestIndexOfClass[objectclass]) + { + /* Error */ + prvTraceError("Attempt to free more handles than allocated!"); + } + else + { + objectHandleStacks.indexOfNextAvailableHandle[objectclass]--; + indexOfHandle = objectHandleStacks.indexOfNextAvailableHandle[objectclass]; + objectHandleStacks.objectHandles[indexOfHandle] = handle; + } +} + +/******************************************************************************* + * prvMarkObjectAsUsed + * + * Sets an "is used flag" on object creation, using the first byte of the name + * field. This allows for counting the number of used Object Table slots, even + * if no names have been set. + ******************************************************************************/ +void prvMarkObjectAsUsed(traceObjectClass objectclass, traceHandle handle) +{ + uint16_t idx = uiIndexOfObject(handle, objectclass); + RecorderDataPtr->ObjectPropertyTable.objbytes[idx] = 1; +} + +/******************************************************************************* + * prvStrncpy + * + * Private string copy function, to improve portability between compilers. + ******************************************************************************/ +static void prvStrncpy(char* dst, const char* src, uint32_t maxLength) +{ + uint32_t i; + for (i = 0; i < maxLength; i++) + { + dst[i] = src[i]; + if (src[i] == 0) + break; + } +} + +/******************************************************************************* + * prvTraceSetObjectName + * + * Registers the names of queues, semaphores and other kernel objects in the + * recorder's Object Property Table, at the given handle and object class. + ******************************************************************************/ +void prvTraceSetObjectName(traceObjectClass objectclass, + traceHandle handle, + const char* name) +{ + static uint16_t idx; + + TRACE_ASSERT(name != NULL, "prvTraceSetObjectName: name == NULL", TRC_UNUSED); + + if (objectclass >= TRACE_NCLASSES) + { + prvTraceError("Illegal object class in prvTraceSetObjectName"); + return; + } + + if (handle == 0) + { + prvTraceError("Illegal handle (0) in prvTraceSetObjectName."); + return; + } + + if (handle > RecorderDataPtr->ObjectPropertyTable.NumberOfObjectsPerClass[objectclass]) + { + /* ERROR */ + prvTraceError(pszTraceGetErrorNotEnoughHandles(objectclass)); + } + else + { + idx = uiIndexOfObject(handle, objectclass); + + if (traceErrorMessage == NULL) + { + prvStrncpy((char*)&(RecorderDataPtr->ObjectPropertyTable.objbytes[idx]), + name, + RecorderDataPtr->ObjectPropertyTable.NameLengthPerClass[ objectclass ]); + } + } +} + +traceString prvTraceOpenSymbol(const char* name, traceString userEventChannel) +{ + uint16_t result; + uint8_t len; + uint8_t crc; + TRACE_ALLOC_CRITICAL_SECTION(); + + len = 0; + crc = 0; + + TRACE_ASSERT(name != NULL, "prvTraceOpenSymbol: name == NULL", (traceString)0); + + prvTraceGetChecksum(name, &crc, &len); + + trcCRITICAL_SECTION_BEGIN(); + result = prvTraceLookupSymbolTableEntry(name, crc, len, userEventChannel); + if (!result) + { + result = prvTraceCreateSymbolTableEntry(name, crc, len, userEventChannel); + } + trcCRITICAL_SECTION_END(); + + return result; +} + + +/****************************************************************************** +* vTraceSetFrequency +* +* Registers the clock rate of the time source for the event timestamping. +* This is normally not required, but if the default value (TRC_HWTC_FREQ_HZ) +* should be incorrect for your setup, you can override it using this function. +* +* Must be called prior to vTraceEnable, and the time source is assumed to +* have a fixed clock frequency after the startup. +* +* Note that, in snapshot mode, the value is divided by the TRC_HWTC_DIVISOR. +* This is a software "prescaler" that is also applied on the timestamps. +*****************************************************************************/ +void vTraceSetFrequency(uint32_t frequency) +{ + timestampFrequency = frequency; +} + +/******************************************************************************* + * Supporting functions + ******************************************************************************/ + +/******************************************************************************* + * prvTraceError + * + * Called by various parts in the recorder. Stops the recorder and stores a + * pointer to an error message, which is printed by the monitor task. + * If you are not using the monitor task, you may use xTraceGetLastError() + * from your application to check if the recorder is OK. + * + * Note: If a recorder error is registered before vTraceStart is called, the + * trace start will be aborted. This can occur if any of the Nxxxx constants + * (e.g., TRC_CFG_NTASK) in trcConfig.h is too small. + ******************************************************************************/ +void prvTraceError(const char* msg) +{ + /* Stop the recorder */ + if (RecorderDataPtr != NULL) + { + vTraceStop(); + } + + /* If first error only... */ + if (traceErrorMessage == NULL) + { + traceErrorMessage = (char*)(intptr_t) msg; + if (RecorderDataPtr != NULL) + { + prvStrncpy(RecorderDataPtr->systemInfo, traceErrorMessage, 80); + RecorderDataPtr->internalErrorOccured = 1; + } + } +} + +void vTraceSetFilterMask(uint16_t filterMask) +{ + CurrentFilterMask = filterMask; +} + +void vTraceSetFilterGroup(uint16_t filterGroup) +{ + CurrentFilterGroup = filterGroup; +} + +/****************************************************************************** + * prvCheckDataToBeOverwrittenForMultiEntryEvents + * + * This checks if the next event to be overwritten is a multi-entry user event, + * i.e., a USER_EVENT followed by data entries. + * Such data entries do not have an event code at byte 0, as other events. + * All 4 bytes are user data, so the first byte of such data events must + * not be interpreted as type field. The number of data entries following + * a USER_EVENT is given in the event code of the USER_EVENT. + * Therefore, when overwriting a USER_EVENT (when using in ring-buffer mode) + * any data entries following must be replaced with NULL events (code 0). + * + * This is assumed to execute within a critical section... + *****************************************************************************/ + +#if (TRC_CFG_SNAPSHOT_MODE == TRC_SNAPSHOT_MODE_RING_BUFFER) +void prvCheckDataToBeOverwrittenForMultiEntryEvents(uint8_t nofEntriesToCheck) +{ + /* Generic "int" type is desired - should be 16 bit variable on 16 bit HW */ + unsigned int i = 0; + unsigned int e = 0; + + TRACE_ASSERT(nofEntriesToCheck != 0, + "prvCheckDataToBeOverwrittenForMultiEntryEvents: nofEntriesToCheck == 0", TRC_UNUSED); + + while (i < nofEntriesToCheck) + { + e = RecorderDataPtr->nextFreeIndex + i; + if ((RecorderDataPtr->eventData[e*4] > USER_EVENT) && + (RecorderDataPtr->eventData[e*4] < USER_EVENT + 16)) + { + uint8_t nDataEvents = (uint8_t)(RecorderDataPtr->eventData[e*4] - USER_EVENT); + if ((e + nDataEvents) < RecorderDataPtr->maxEvents) + { + (void)memset(& RecorderDataPtr->eventData[e*4], 0, (size_t) (4 + 4 * nDataEvents)); + } + } + else if (RecorderDataPtr->eventData[e*4] == DIV_XPS) + { + if ((e + 1) < RecorderDataPtr->maxEvents) + { + /* Clear 8 bytes */ + (void)memset(& RecorderDataPtr->eventData[e*4], 0, 4 + 4); + } + else + { + /* Clear 8 bytes, 4 first and 4 last */ + (void)memset(& RecorderDataPtr->eventData[0], 0, 4); + (void)memset(& RecorderDataPtr->eventData[e*4], 0, 4); + } + } + i++; + } +} +#endif + +/******************************************************************************* + * prvTraceUpdateCounters + * + * Updates the index of the event buffer. + ******************************************************************************/ +void prvTraceUpdateCounters(void) +{ + if (RecorderDataPtr->recorderActive == 0) + { + return; + } + + RecorderDataPtr->numEvents++; + + RecorderDataPtr->nextFreeIndex++; + + if (RecorderDataPtr->nextFreeIndex >= (TRC_CFG_EVENT_BUFFER_SIZE)) + { +#if (TRC_CFG_SNAPSHOT_MODE == TRC_SNAPSHOT_MODE_RING_BUFFER) + RecorderDataPtr->bufferIsFull = 1; + RecorderDataPtr->nextFreeIndex = 0; +#else + vTraceStop(); +#endif + } + +#if (TRC_CFG_SNAPSHOT_MODE == TRC_SNAPSHOT_MODE_RING_BUFFER) + prvCheckDataToBeOverwrittenForMultiEntryEvents(1); +#endif +} + +/****************************************************************************** + * prvTraceGetDTS + * + * Returns a differential timestamp (DTS), i.e., the time since + * last event, and creates an XTS event if the DTS does not fit in the + * number of bits given. The XTS event holds the MSB bytes of the DTS. + * + * The parameter param_maxDTS should be 0xFF for 8-bit dts or 0xFFFF for + * events with 16-bit dts fields. + *****************************************************************************/ +uint16_t prvTraceGetDTS(uint16_t param_maxDTS) +{ + static uint32_t old_timestamp = 0; + XTSEvent* xts = 0; + uint32_t dts = 0; + uint32_t timestamp = 0; + + TRACE_ASSERT(param_maxDTS == 0xFF || param_maxDTS == 0xFFFF, "prvTraceGetDTS: Invalid value for param_maxDTS", 0); + + + if (RecorderDataPtr->frequency == 0) + { + if (timestampFrequency != 0) + { + /* If to override default TRC_HWTC_FREQ_HZ value with value set by vTraceSetFrequency */ + RecorderDataPtr->frequency = timestampFrequency / (TRC_HWTC_DIVISOR); + } + else if (init_hwtc_count != (TRC_HWTC_COUNT)) + { + /* If using default value and timer has been started. + Note: If the default frequency value set here would be incorrect, e.g., + if the timer has actually not been configured yet, override this + with vTraceSetFrequency. + */ + RecorderDataPtr->frequency = (TRC_HWTC_FREQ_HZ) / (TRC_HWTC_DIVISOR); + } + /* If no override (vTraceSetFrequency) and timer inactive -> no action */ + } + + /************************************************************************** + * The below statements read the timestamp from the timer port module. + * If necessary, whole seconds are extracted using division while the rest + * comes from the modulo operation. + **************************************************************************/ + + prvTracePortGetTimeStamp(×tamp); + + /*************************************************************************** + * Since dts is unsigned the result will be correct even if timestamp has + * wrapped around. + ***************************************************************************/ + dts = timestamp - old_timestamp; + old_timestamp = timestamp; + + if (RecorderDataPtr->frequency > 0) + { + /* Check if dts > 1 second */ + if (dts > RecorderDataPtr->frequency) + { + /* More than 1 second has passed */ + RecorderDataPtr->absTimeLastEventSecond += dts / RecorderDataPtr->frequency; + /* The part that is not an entire second is added to absTimeLastEvent */ + RecorderDataPtr->absTimeLastEvent += dts % RecorderDataPtr->frequency; + } + else + { + RecorderDataPtr->absTimeLastEvent += dts; + } + + /* Check if absTimeLastEvent >= 1 second */ + if (RecorderDataPtr->absTimeLastEvent >= RecorderDataPtr->frequency) + { + /* RecorderDataPtr->absTimeLastEvent is more than or equal to 1 second, but always less than 2 seconds */ + RecorderDataPtr->absTimeLastEventSecond++; + RecorderDataPtr->absTimeLastEvent -= RecorderDataPtr->frequency; + /* RecorderDataPtr->absTimeLastEvent is now less than 1 second */ + } + } + else + { + /* Special case if the recorder has not yet started (frequency may be uninitialized, i.e., zero) */ + RecorderDataPtr->absTimeLastEvent = timestamp; + } + + /* If the dts (time since last event) does not fit in event->dts (only 8 or 16 bits) */ + if (dts > param_maxDTS) + { + /* Create an XTS event (eXtended TimeStamp) containing the higher dts bits*/ + xts = (XTSEvent*) prvTraceNextFreeEventBufferSlot(); + + if (xts != NULL) + { + if (param_maxDTS == 0xFFFF) + { + xts->type = XTS16; + xts->xts_16 = (uint16_t)((dts / 0x10000) & 0xFFFF); + xts->xts_8 = 0; + } + else if (param_maxDTS == 0xFF) + { + xts->type = XTS8; + xts->xts_16 = (uint16_t)((dts / 0x100) & 0xFFFF); + xts->xts_8 = (uint8_t)((dts / 0x1000000) & 0xFF); + } + else + { + prvTraceError("Bad param_maxDTS in prvTraceGetDTS"); + } + prvTraceUpdateCounters(); + } + } + + return (uint16_t)dts & param_maxDTS; +} + +/******************************************************************************* + * prvTraceLookupSymbolTableEntry + * + * Find an entry in the symbol table, return 0 if not present. + * + * The strings are stored in a byte pool, with four bytes of "meta-data" for + * every string. + * byte 0-1: index of next entry with same checksum (for fast lookup). + * byte 2-3: reference to a symbol table entry, a label for vTracePrintF + * format strings only (the handle of the destination channel). + * byte 4..(4 + length): the string (object name or user event label), with + * zero-termination + ******************************************************************************/ +traceString prvTraceLookupSymbolTableEntry(const char* name, + uint8_t crc6, + uint8_t len, + traceString chn) +{ + uint16_t i = RecorderDataPtr->SymbolTable.latestEntryOfChecksum[ crc6 ]; + + TRACE_ASSERT(name != NULL, "prvTraceLookupSymbolTableEntry: name == NULL", (traceString)0); + TRACE_ASSERT(len != 0, "prvTraceLookupSymbolTableEntry: len == 0", (traceString)0); + + while (i != 0) + { + if (RecorderDataPtr->SymbolTable.symbytes[i + 2] == (chn & 0x00FF)) + { + if (RecorderDataPtr->SymbolTable.symbytes[i + 3] == (chn / 0x100)) + { + if (RecorderDataPtr->SymbolTable.symbytes[i + 4 + len] == '\0') + { + if (strncmp((char*)(& RecorderDataPtr->SymbolTable.symbytes[i + 4]), name, len) == 0) + { + break; /* found */ + } + } + } + } + i = (uint16_t)(RecorderDataPtr->SymbolTable.symbytes[i] + (RecorderDataPtr->SymbolTable.symbytes[i + 1] * 0x100)); + } + return i; +} + +/******************************************************************************* + * prvTraceCreateSymbolTableEntry + * + * Creates an entry in the symbol table, independent if it exists already. + * + * The strings are stored in a byte pool, with four bytes of "meta-data" for + * every string. + * byte 0-1: index of next entry with same checksum (for fast lookup). + * byte 2-3: reference to a symbol table entry, a label for vTracePrintF + * format strings only (the handle of the destination channel). + * byte 4..(4 + length): the string (object name or user event label), with + * zero-termination + ******************************************************************************/ +uint16_t prvTraceCreateSymbolTableEntry(const char* name, + uint8_t crc6, + uint8_t len, + traceString channel) +{ + uint16_t ret = 0; + + TRACE_ASSERT(name != NULL, "prvTraceCreateSymbolTableEntry: name == NULL", 0); + TRACE_ASSERT(len != 0, "prvTraceCreateSymbolTableEntry: len == 0", 0); + + if (RecorderDataPtr->SymbolTable.nextFreeSymbolIndex + len + 4 >= (TRC_CFG_SYMBOL_TABLE_SIZE)) + { + prvTraceError("Symbol table full. Increase TRC_CFG_SYMBOL_TABLE_SIZE in trcConfig.h"); + ret = 0; + } + else + { + + RecorderDataPtr->SymbolTable.symbytes + [ RecorderDataPtr->SymbolTable.nextFreeSymbolIndex] = + (uint8_t)(RecorderDataPtr->SymbolTable.latestEntryOfChecksum[ crc6 ] & 0x00FF); + + RecorderDataPtr->SymbolTable.symbytes + [ RecorderDataPtr->SymbolTable.nextFreeSymbolIndex + 1] = + (uint8_t)(RecorderDataPtr->SymbolTable.latestEntryOfChecksum[ crc6 ] / 0x100); + + RecorderDataPtr->SymbolTable.symbytes + [ RecorderDataPtr->SymbolTable.nextFreeSymbolIndex + 2] = + (uint8_t)(channel & 0x00FF); + + RecorderDataPtr->SymbolTable.symbytes + [ RecorderDataPtr->SymbolTable.nextFreeSymbolIndex + 3] = + (uint8_t)(channel / 0x100); + + /* set name (bytes 4...4+len-1) */ + prvStrncpy((char*)&(RecorderDataPtr->SymbolTable.symbytes + [ RecorderDataPtr->SymbolTable.nextFreeSymbolIndex + 4]), name, len); + + /* Set zero termination (at offset 4+len) */ + RecorderDataPtr->SymbolTable.symbytes + [RecorderDataPtr->SymbolTable.nextFreeSymbolIndex + 4 + len] = '\0'; + + /* store index of entry (for return value, and as head of LL[crc6]) */ + RecorderDataPtr->SymbolTable.latestEntryOfChecksum + [ crc6 ] = (uint16_t)RecorderDataPtr->SymbolTable.nextFreeSymbolIndex; + + RecorderDataPtr->SymbolTable.nextFreeSymbolIndex += (uint32_t) (len + 5); + + ret = (uint16_t)(RecorderDataPtr->SymbolTable.nextFreeSymbolIndex - (uint8_t)(len + 5)); + } + + return ret; +} + + +/******************************************************************************* + * prvTraceGetChecksum + * + * Calculates a simple 6-bit checksum from a string, used to index the string + * for fast symbol table lookup. + ******************************************************************************/ +void prvTraceGetChecksum(const char *pname, uint8_t* pcrc, uint8_t* plength) +{ + unsigned char c; + int length = 1; /* Should be 1 to account for '\0' */ + int crc = 0; + + TRACE_ASSERT(pname != NULL, "prvTraceGetChecksum: pname == NULL", TRC_UNUSED); + TRACE_ASSERT(pcrc != NULL, "prvTraceGetChecksum: pcrc == NULL", TRC_UNUSED); + TRACE_ASSERT(plength != NULL, "prvTraceGetChecksum: plength == NULL", TRC_UNUSED); + + if (pname != (const char *) 0) + { + for (; (c = (unsigned char) *pname++) != '\0';) + { + crc += c; + length++; + } + } + *pcrc = (uint8_t)(crc & 0x3F); + *plength = (uint8_t)length; +} + +#if (TRC_CFG_USE_16BIT_OBJECT_HANDLES == 1) + +static void prvTraceStoreXID(traceHandle handle); + +/****************************************************************************** + * prvTraceStoreXID + * + * Stores an XID (eXtended IDentifier) event. + * This is used if an object/task handle is larger than 255. + * The parameter "handle" is the full (16 bit) handle, assumed to be 256 or + * larger. Handles below 256 should not use this function. + * + * NOTE: this function MUST be called from within a critical section. + *****************************************************************************/ +static void prvTraceStoreXID(traceHandle handle) +{ + XPSEvent* xid; + + TRACE_ASSERT(handle >= 256, "prvTraceStoreXID: Handle < 256", TRC_UNUSED); + + xid = (XPSEvent*)prvTraceNextFreeEventBufferSlot(); + + if (xid != NULL) + { + xid->type = XID; + + /* This function is (only) used when traceHandle is 16 bit... */ + xid->xps_16 = handle; + + prvTraceUpdateCounters(); + } +} + +static uint8_t prvTraceGet8BitHandle(traceHandle handle) +{ + if (handle > 255) + { + prvTraceStoreXID(handle); + /* The full handle (16 bit) is stored in the XID event. + This code (255) is used instead of zero (which is an error code).*/ + return 255; + } + return (uint8_t)(handle & 0xFF); +} +#endif /*(TRC_CFG_USE_16BIT_OBJECT_HANDLES == 1)*/ + + +/* If using DWT timestamping (default on ARM Cortex-M3, M4 and M7), make sure the DWT unit is initialized. */ +#ifndef TRC_CFG_ARM_CM_USE_SYSTICK +#if ((TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_Cortex_M) && (defined (__CORTEX_M) && (__CORTEX_M >= 0x03))) +void prvTraceInitCortexM() +{ + /* Ensure that the DWT registers are unlocked and can be modified. */ + TRC_REG_ITM_LOCKACCESS = TRC_ITM_LOCKACCESS_UNLOCK; + + /* Make sure DWT is enabled, if supported */ + TRC_REG_DEMCR |= TRC_DEMCR_TRCENA; + + do{ + /* Verify that DWT is supported */ + if (TRC_REG_DEMCR == 0) + { + /* This function is called on Cortex-M3, M4 and M7 devices to initialize + the DWT unit, assumed present. The DWT cycle counter is used for timestamping. + + If the below error is produced, the DWT unit does not seem to be available. + + In that case, define the macro TRC_CFG_ARM_CM_USE_SYSTICK in your build + to use SysTick timestamping instead, or define your own timestamping by + setting TRC_CFG_HARDWARE_PORT to TRC_HARDWARE_PORT_APPLICATION_DEFINED + and make the necessary definitions, as explained in trcHardwarePort.h.*/ + + prvTraceError("DWT unit not available, see code comment."); + break; + } + + /* Verify that DWT_CYCCNT is supported */ + if (TRC_REG_DWT_CTRL & TRC_DWT_CTRL_NOCYCCNT) + { + /* This function is called on Cortex-M3, M4 and M7 devices to initialize + the DWT unit, assumed present. The DWT cycle counter is used for timestamping. + + If the below error is produced, the cycle counter does not seem to be available. + + In that case, define the macro TRC_CFG_ARM_CM_USE_SYSTICK in your build + to use SysTick timestamping instead, or define your own timestamping by + setting TRC_CFG_HARDWARE_PORT to TRC_HARDWARE_PORT_APPLICATION_DEFINED + and make the necessary definitions, as explained in trcHardwarePort.h.*/ + + prvTraceError("DWT_CYCCNT not available, see code comment."); + break; + } + + /* Reset the cycle counter */ + TRC_REG_DWT_CYCCNT = 0; + + /* Enable the cycle counter */ + TRC_REG_DWT_CTRL |= TRC_DWT_CTRL_CYCCNTENA; + + }while(0); /* breaks above jump here */ +} +#endif +#endif + +/****************************************************************************** + * prvTracePortGetTimeStamp + * + * Returns the current time based on the HWTC macros which provide a hardware + * isolation layer towards the hardware timer/counter. + * + * The HWTC macros and prvTracePortGetTimeStamp is the main porting issue + * or the trace recorder library. Typically you should not need to change + * the code of prvTracePortGetTimeStamp if using the HWTC macros. + * + ******************************************************************************/ +void prvTracePortGetTimeStamp(uint32_t *pTimestamp) +{ + static uint32_t last_hwtc_count = 0; + uint32_t hwtc_count = 0; + +#if TRC_HWTC_TYPE == TRC_OS_TIMER_INCR || TRC_HWTC_TYPE == TRC_OS_TIMER_DECR + /* systick based timer */ + static uint32_t last_traceTickCount = 0; + uint32_t traceTickCount = 0; +#else /*TRC_HWTC_TYPE == TRC_OS_TIMER_INCR || TRC_HWTC_TYPE == TRC_OS_TIMER_DECR*/ + /* Free running timer */ + static uint32_t last_hwtc_rest = 0; + uint32_t diff = 0; + uint32_t diff_scaled = 0; +#endif /*TRC_HWTC_TYPE == TRC_OS_TIMER_INCR || TRC_HWTC_TYPE == TRC_OS_TIMER_DECR*/ + + if (trace_disable_timestamp == 1) + { + if (pTimestamp) + *pTimestamp = last_timestamp; + return; + } + + /* Retrieve TRC_HWTC_COUNT only once since the same value should be used all throughout this function. */ +#if (TRC_HWTC_TYPE == TRC_OS_TIMER_INCR || TRC_HWTC_TYPE == TRC_FREE_RUNNING_32BIT_INCR) + /* Get the increasing tick count */ + hwtc_count = (TRC_HWTC_COUNT); +#elif (TRC_HWTC_TYPE == TRC_OS_TIMER_DECR || TRC_HWTC_TYPE == TRC_FREE_RUNNING_32BIT_DECR) + /* Convert decreasing tick count into increasing tick count */ + hwtc_count = (TRC_HWTC_PERIOD) - (TRC_HWTC_COUNT); +#else + #error "TRC_HWTC_TYPE has unexpected value" +#endif + +#if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Win32) + /* The Win32 port uses ulGetRunTimeCounterValue for timestamping, which in turn + uses QueryPerformanceCounter. That function is not always reliable when used over + multiple threads. We must therefore handle rare cases where the timestamp is less + than the previous. In practice, this should "never" roll over since the + performance counter is 64 bit wide. */ + + if (last_hwtc_count > hwtc_count) + { + hwtc_count = last_hwtc_count; + } +#endif + +#if (TRC_HWTC_TYPE == TRC_OS_TIMER_INCR || TRC_HWTC_TYPE == TRC_OS_TIMER_DECR) + /* Timestamping is based on a timer that wraps at TRC_HWTC_PERIOD */ + if (last_traceTickCount - uiTraceTickCount - 1 < 0x80000000) + { + /* This means last_traceTickCount is higher than uiTraceTickCount, + so we have previously compensated for a missed tick. + Therefore we use the last stored value because that is more accurate. */ + traceTickCount = last_traceTickCount; + } + else + { + /* Business as usual */ + traceTickCount = uiTraceTickCount; + } + + /* Check for overflow. May occur if the update of uiTraceTickCount has been + delayed due to disabled interrupts. */ + if (traceTickCount == last_traceTickCount && hwtc_count < last_hwtc_count) + { + /* A trace tick has occurred but not been executed by the kernel, so we compensate manually. */ + traceTickCount++; + } + + /* Check if the return address is OK, then we perform the calculation. */ + if (pTimestamp) + { + /* Get timestamp from trace ticks. Scale down the period to avoid unwanted overflows. */ + last_timestamp = traceTickCount * ((TRC_HWTC_PERIOD) / (TRC_HWTC_DIVISOR)); + /* Increase timestamp by (hwtc_count + "lost hardware ticks from scaling down period") / TRC_HWTC_DIVISOR. */ + last_timestamp += (hwtc_count + traceTickCount * ((TRC_HWTC_PERIOD) % (TRC_HWTC_DIVISOR))) / (TRC_HWTC_DIVISOR); + } + /* Store the previous value */ + last_traceTickCount = traceTickCount; + +#else /*(TRC_HWTC_TYPE == TRC_OS_TIMER_INCR || TRC_HWTC_TYPE == TRC_OS_TIMER_DECR)*/ + + /* Timestamping is based on a free running timer */ + /* This part handles free running clocks that can be scaled down to avoid too large DTS values. + Without this, the scaled timestamp will incorrectly wrap at (2^32 / TRC_HWTC_DIVISOR) ticks. + The scaled timestamp returned from this function is supposed to go from 0 -> 2^32, which in real time would represent (0 -> 2^32 * TRC_HWTC_DIVISOR) ticks. */ + + /* First we see how long time has passed since the last timestamp call, and we also add the ticks that was lost when we scaled down the last time. */ + diff = (hwtc_count - last_hwtc_count) + last_hwtc_rest; + + /* Scale down the diff */ + diff_scaled = diff / (TRC_HWTC_DIVISOR); + + /* Find out how many ticks were lost when scaling down, so we can add them the next time */ + last_hwtc_rest = diff % (TRC_HWTC_DIVISOR); + + /* We increase the scaled timestamp by the scaled amount */ + last_timestamp += diff_scaled; +#endif /*(TRC_HWTC_TYPE == TRC_OS_TIMER_INCR || TRC_HWTC_TYPE == TRC_OS_TIMER_DECR)*/ + + /* Is anyone interested in the results? */ + if (pTimestamp) + *pTimestamp = last_timestamp; + + /* Store the previous value */ + last_hwtc_count = hwtc_count; +} + +#endif /*(TRC_USE_TRACEALYZER_RECORDER == 1)*/ + +#endif /*(TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_SNAPSHOT)*/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/trcStreamingRecorder.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/trcStreamingRecorder.c new file mode 100644 index 0000000..dc1b878 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace/trcStreamingRecorder.c @@ -0,0 +1,1896 @@ +/******************************************************************************* + * Trace Recorder Library for Tracealyzer v4.1.5 + * Percepio AB, www.percepio.com + * + * trcStreamingRecorder.c + * + * The generic core of the trace recorder's streaming mode. + * + * Terms of Use + * This file is part of the trace recorder library (RECORDER), which is the + * intellectual property of Percepio AB (PERCEPIO) and provided under a + * license as follows. + * The RECORDER may be used free of charge for the purpose of recording data + * intended for analysis in PERCEPIO products. It may not be used or modified + * for other purposes without explicit permission from PERCEPIO. + * You may distribute the RECORDER in its original source code form, assuming + * this text (terms of use, disclaimer, copyright notice) is unchanged. You are + * allowed to distribute the RECORDER with minor modifications intended for + * configuration or porting of the RECORDER, e.g., to allow using it on a + * specific processor, processor family or with a specific communication + * interface. Any such modifications should be documented directly below + * this comment block. + * + * Disclaimer + * The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty + * as to its use or performance. PERCEPIO does not and cannot warrant the + * performance or results you may obtain by using the RECORDER or documentation. + * PERCEPIO make no warranties, express or implied, as to noninfringement of + * third party rights, merchantability, or fitness for any particular purpose. + * In no event will PERCEPIO, its technology partners, or distributors be liable + * to you for any consequential, incidental or special damages, including any + * lost profits or lost savings, even if a representative of PERCEPIO has been + * advised of the possibility of such damages, or for any claim by any third + * party. Some jurisdictions do not allow the exclusion or limitation of + * incidental, consequential or special damages, or the exclusion of implied + * warranties or limitations on how long an implied warranty may last, so the + * above limitations may not apply to you. + * + * Tabs are used for indent in this file (1 tab = 4 spaces) + * + * Copyright Percepio AB, 2018. + * www.percepio.com + ******************************************************************************/ + +#include "trcRecorder.h" + +#if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING) + +#if (TRC_USE_TRACEALYZER_RECORDER == 1) + +#include +#include + +typedef struct{ + uint16_t EventID; + uint16_t EventCount; + uint32_t TS; +} BaseEvent; + +typedef struct{ + BaseEvent base; + uint32_t param1; +} EventWithParam_1; + +typedef struct{ + BaseEvent base; + uint32_t param1; + uint32_t param2; +} EventWithParam_2; + +typedef struct{ + BaseEvent base; + uint32_t param1; + uint32_t param2; + uint32_t param3; +} EventWithParam_3; + +/* Used in event functions with variable number of parameters. */ +typedef struct +{ + BaseEvent base; + uint32_t data[15]; /* maximum payload size */ +} largestEventType; + +typedef struct{ + uint32_t psf; + uint16_t version; + uint16_t platform; + uint32_t options; + uint16_t symbolSize; + uint16_t symbolCount; + uint16_t objectDataSize; + uint16_t objectDataCount; +} PSFHeaderInfo; + + +/* The size of each slot in the Symbol Table */ +#define SYMBOL_TABLE_SLOT_SIZE (sizeof(uint32_t) + (((TRC_CFG_SYMBOL_MAX_LENGTH)+(sizeof(uint32_t)-1))/sizeof(uint32_t))*sizeof(uint32_t)) + +#define OBJECT_DATA_SLOT_SIZE (sizeof(uint32_t) + sizeof(uint32_t)) + +/* The total size of the Symbol Table */ +#define SYMBOL_TABLE_BUFFER_SIZE ((TRC_CFG_SYMBOL_TABLE_SLOTS) * SYMBOL_TABLE_SLOT_SIZE) + +/* The total size of the Object Data Table */ +#define OBJECT_DATA_TABLE_BUFFER_SIZE ((TRC_CFG_OBJECT_DATA_SLOTS) * OBJECT_DATA_SLOT_SIZE) + +/* The Symbol Table type - just a byte array */ +typedef struct{ + union + { + uint32_t pSymbolTableBufferUINT32[SYMBOL_TABLE_BUFFER_SIZE / sizeof(uint32_t)]; + uint8_t pSymbolTableBufferUINT8[SYMBOL_TABLE_BUFFER_SIZE]; + } SymbolTableBuffer; +} SymbolTable; + +/* The Object Data Table type - just a byte array */ +typedef struct{ + union + { + uint32_t pObjectDataTableBufferUINT32[OBJECT_DATA_TABLE_BUFFER_SIZE / sizeof(uint32_t)]; + uint8_t pObjectDataTableBufferUINT8[OBJECT_DATA_TABLE_BUFFER_SIZE]; + } ObjectDataTableBuffer; +} ObjectDataTable; + +typedef struct{ + uint16_t Status; /* 16 bit to avoid implicit padding (warnings) */ + uint16_t BytesRemaining; + char* WritePointer; +} PageType; + +/* Code used for "task address" when no task has started. (NULL = idle task) */ +#define HANDLE_NO_TASK 2 + +#define PAGE_STATUS_FREE 0 +#define PAGE_STATUS_WRITE 1 +#define PAGE_STATUS_READ 2 + +#define PSF_ASSERT(_assert, _err) if (! (_assert)){ prvTraceError(_err); return; } + +/* Part of the PSF format - encodes the number of 32-bit params in an event */ +#define PARAM_COUNT(n) ((n & 0xF) << 12) + +/* The Symbol Table instance - keeps names of tasks and other named objects. */ +static SymbolTable symbolTable = { { { 0 } } }; + +/* This points to the first unused entry in the symbol table. */ +static uint32_t firstFreeSymbolTableIndex = 0; + +/* The Object Data Table instance - keeps initial priorities of tasks. */ +static ObjectDataTable objectDataTable = { { { 0 } } }; + +/* This points to the first unused entry in the object data table. */ +static uint32_t firstFreeObjectDataTableIndex = 0; + +/* Keeps track of ISR nesting */ +static uint32_t ISR_stack[TRC_CFG_MAX_ISR_NESTING]; + +/* Keeps track of ISR nesting */ +static int8_t ISR_stack_index = -1; + +/* Any error that occurred in the recorder (also creates User Event) */ +static int errorCode = 0; + +/* Counts the number of trace sessions (not yet used) */ +static uint32_t SessionCounter = 0u; + +/* Master switch for recording (0 => Disabled, 1 => Enabled) */ +uint32_t RecorderEnabled = 0u; + +/* Used to determine endian of data (big/little) */ +static uint32_t PSFEndianessIdentifier = 0x50534600; + +/* Used to interpret the data format */ +static uint16_t FormatVersion = 0x0004; + +/* The number of events stored. Used as event sequence number. */ +static uint32_t eventCounter = 0; + +/* Remembers if an earlier ISR in a sequence of adjacent ISRs has triggered a task switch. +In that case, vTraceStoreISREnd does not store a return to the previously executing task. */ +int32_t isPendingContextSwitch = 0; + +uint32_t uiTraceTickCount = 0; +uint32_t timestampFrequency = 0; +uint32_t DroppedEventCounter = 0; +uint32_t TotalBytesRemaining_LowWaterMark = (TRC_CFG_PAGED_EVENT_BUFFER_PAGE_COUNT) * (TRC_CFG_PAGED_EVENT_BUFFER_PAGE_SIZE); +uint32_t TotalBytesRemaining = (TRC_CFG_PAGED_EVENT_BUFFER_PAGE_COUNT) * (TRC_CFG_PAGED_EVENT_BUFFER_PAGE_SIZE); + +PageType PageInfo[TRC_CFG_PAGED_EVENT_BUFFER_PAGE_COUNT]; + +char* EventBuffer = NULL; + +/******************************************************************************* + * NoRoomForSymbol + * + * Incremented on prvTraceSaveSymbol if no room for saving the symbol name. This + * is used for storing the names of: + * - Tasks + * - Named ISRs (xTraceSetISRProperties) + * - Named kernel objects (vTraceStoreKernelObjectName) + * - User event channels (xTraceRegisterString) + * + * This variable should be zero. If not, it shows the number of missing slots so + * far. In that case, increment SYMBOL_TABLE_SLOTS with (at least) this value. + ******************************************************************************/ +volatile uint32_t NoRoomForSymbol = 0; + +/******************************************************************************* + * NoRoomForObjectData + * + * Incremented on prvTraceSaveObjectData if no room for saving the object data, + * i.e., the base priorities of tasks. There must be one slot for each task. + * If not, this variable will show the difference. + * + * This variable should be zero. If not, it shows the number of missing slots so + * far. In that case, increment OBJECT_DATA_SLOTS with (at least) this value. + ******************************************************************************/ +volatile uint32_t NoRoomForObjectData = 0; + +/******************************************************************************* + * LongestSymbolName + * + * Updated in prvTraceSaveSymbol. Should not exceed TRC_CFG_SYMBOL_MAX_LENGTH, + * otherwise symbol names will be truncated. In that case, set + * TRC_CFG_SYMBOL_MAX_LENGTH to (at least) this value. + ******************************************************************************/ +volatile uint32_t LongestSymbolName = 0; + +/******************************************************************************* + * MaxBytesTruncated + * + * Set in prvTraceStoreStringEvent if the total data payload exceeds 60 bytes, + * including data arguments and the string. For user events, that is 52 bytes + * for string and data arguments. In that is exceeded, the event is truncated + * (usually only the string, unless more than 15 parameters) and this variable + * holds the maximum number of truncated bytes, from any event. + ******************************************************************************/ +volatile uint32_t MaxBytesTruncated = 0; + +uint16_t CurrentFilterMask = 0xFFFF; + +uint16_t CurrentFilterGroup = FilterGroup0; + +/* Internal common function for storing string events */ +static void prvTraceStoreStringEventHelper( int nArgs, + uint16_t eventID, + traceString userEvtChannel, + int len, + const char* str, + va_list* vl); + +/* Not static to avoid warnings from SysGCC/PPC */ +void prvTraceStoreSimpleStringEventHelper(traceString userEvtChannel, + const char* str); + + +/* Stores the header information on Start */ +static void prvTraceStoreHeader(void); + +/* Stores the symbol table on Start */ +static void prvTraceStoreSymbolTable(void); + +/* Stores the object table on Start */ +static void prvTraceStoreObjectDataTable(void); + +/* Store the Timestamp Config on Start */ +static void prvTraceStoreTSConfig(void); + +/* Store the current warnings */ +static void prvTraceStoreWarnings(void); + +/* Internal function for starting/stopping the recorder. */ +static void prvSetRecorderEnabled(uint32_t isEnabled); + +/* Mark the page read as complete. */ +static void prvPageReadComplete(int pageIndex); + +/* Retrieve a buffer page to write to. */ +static int prvAllocateBufferPage(int prevPage); + +/* Get the current buffer page index (return value) and the number +of valid bytes in the buffer page (bytesUsed). */ +static int prvGetBufferPage(int32_t* bytesUsed); + +/* Performs timestamping using definitions in trcHardwarePort.h */ +static uint32_t prvGetTimestamp32(void); + +/* Signal an error. */ +void prvTraceError(int errCode); + +/* Signal an warning (does not stop the recorder). */ +void prvTraceWarning(int errCode); + +/****************************************************************************** + * vTraceInstanceFinishedNow + * + * Creates an event that ends the current task instance at this very instant. + * This makes the viewer to splits the current fragment at this point and begin + * a new actor instance, even if no task-switch has occurred. + *****************************************************************************/ +void vTraceInstanceFinishedNow(void) +{ + prvTraceStoreEvent0(PSF_EVENT_IFE_DIRECT); +} + +/****************************************************************************** + * vTraceInstanceFinishedNext + * + * Marks the current "task instance" as finished on the next kernel call. + * + * If that kernel call is blocking, the instance ends after the blocking event + * and the corresponding return event is then the start of the next instance. + * If the kernel call is not blocking, the viewer instead splits the current + * fragment right before the kernel call, which makes this call the first event + * of the next instance. + *****************************************************************************/ +void vTraceInstanceFinishedNext(void) +{ + prvTraceStoreEvent0(PSF_EVENT_IFE_NEXT); +} + +/******************************************************************************* + * vTraceStoreKernelObjectName + * + * Parameter object: pointer to the Event Group that shall be named + * Parameter name: the name to set (const string literal) + * + * Sets a name for a kernel object for display in Tracealyzer. + ******************************************************************************/ +void vTraceStoreKernelObjectName(void* object, const char* name) +{ + /* Always save in symbol table, if the recording has not yet started */ + prvTraceSaveSymbol(object, name); + + prvTraceStoreStringEvent(1, PSF_EVENT_OBJ_NAME, name, (uint32_t)object); +} + + +/****************************************************************************** +* vTraceSetFrequency +* +* Registers the clock rate of the time source for the event timestamping. +* This is normally not required, but if the default value (TRC_HWTC_FREQ_HZ) +* should be incorrect for your setup, you can override it using this function. +* +* Must be called prior to vTraceEnable, and the time source is assumed to +* have a fixed clock frequency after the startup. +*****************************************************************************/ +void vTraceSetFrequency(uint32_t frequency) +{ + timestampFrequency = frequency; +} + +#if (TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1) + +/******************************************************************************* +* xTraceRegisterString +* +* Stores a name for a user event channel, returns the handle. +******************************************************************************/ +traceString xTraceRegisterString(const char* name) +{ + prvTraceSaveSymbol((const void*)name, name); + + /* Always save in symbol table, if the recording has not yet started */ + prvTraceStoreStringEvent(1, PSF_EVENT_OBJ_NAME, (const char*)name, (uint32_t)name); + + return (traceString)name; +} + +/****************************************************************************** + * vTracePrint + * + * Generates "User Events", with unformatted text. + * + * User Events can be used for very efficient application logging, and are shown + * as yellow labels in the main trace view. + * + * You may group User Events into User Event Channels. The yellow User Event + * labels shows the logged string, preceded by the channel name within + * brackets. For example: + * + * "[MyChannel] Hello World!" + * + * The User Event Channels are shown in the View Filter, which makes it easy to + * select what User Events you wish to display. User Event Channels are created + * using xTraceRegisterString(). + * + * Example: + * + * traceString chn = xTraceRegisterString("MyChannel"); + * ... + * vTracePrint(chn, "Hello World!"); + * + ******************************************************************************/ +void vTracePrint(traceString chn, const char* str) +{ + prvTraceStoreSimpleStringEventHelper(chn, str); +} + + +/******************************************************************************* +* vTraceConsoleChannelPrintF +* +* Wrapper for vTracePrint, using the default channel. Can be used as a drop-in +* replacement for printf and similar functions, e.g. in a debug logging macro. +* +* Example: +* +* // Old: #define LogString debug_console_printf +* +* // New, log to Tracealyzer instead: +* #define LogString vTraceConsoleChannelPrintF +* ... +* LogString("My value is: %d", myValue); +******************************************************************************/ +void vTraceConsoleChannelPrintF(const char* fmt, ...) +{ + va_list vl; + char tempBuf[60]; + static traceString consoleChannel = NULL; + + if (consoleChannel == NULL) + consoleChannel = xTraceRegisterString("Debug Console"); + + va_start(vl, fmt); + vsnprintf(tempBuf, 60, fmt, vl); + vTracePrint(consoleChannel, tempBuf); + va_end(vl); +} + +/****************************************************************************** + * vTracePrintF + * + * Generates "User Events", with formatted text and data, similar to a "printf". + * It is very fast since the actual formatting is done on the host side when the + * trace is displayed. + * + * User Events can be used for very efficient application logging, and are shown + * as yellow labels in the main trace view. + * An advantage of User Events is that data can be plotted in the "User Event + * Signal Plot" view, visualizing any data you log as User Events, discrete + * states or control system signals (e.g. system inputs or outputs). + * + * You may group User Events into User Event Channels. The yellow User Event + * labels show the logged string, preceded by the channel name within brackets. + * + * Example: + * + * "[MyChannel] Hello World!" + * + * The User Event Channels are shown in the View Filter, which makes it easy to + * select what User Events you wish to display. User Event Channels are created + * using xTraceRegisterString(). + * + * Example: + * + * traceString adc_uechannel = xTraceRegisterString("ADC User Events"); + * ... + * vTracePrintF(adc_uechannel, + * "ADC channel %d: %d volts", + * ch, adc_reading); + * + * All data arguments are assumed to be 32 bit wide. The following formats are + * supported: + * %d - signed integer. The following width and padding format is supported: "%05d" -> "-0042" and "%5d" -> " -42" + * %u - unsigned integer. The following width and padding format is supported: "%05u" -> "00042" and "%5u" -> " 42" + * %X - hexadecimal (uppercase). The following width and padding format is supported: "%04X" -> "002A" and "%4X" -> " 2A" + * %x - hexadecimal (lowercase). The following width and padding format is supported: "%04x" -> "002a" and "%4x" -> " 2a" + * %s - string (currently, this must be an earlier stored symbol name) + * + * Up to 15 data arguments are allowed, with a total size of maximum 60 byte + * including 8 byte for the base event fields and the format string. So with + * one data argument, the maximum string length is 48 chars. If this is exceeded + * the string is truncated (4 bytes at a time). + * + ******************************************************************************/ +void vTracePrintF(traceString chn, const char* fmt, ...) +{ + va_list vl; + int i = 0; + + int nArgs = 0; + + /* Count the number of arguments in the format string (e.g., %d) */ + for (i = 0; (fmt[i] != 0) && (i < 52); i++) + { + if (fmt[i] == '%') + { + if (fmt[i + 1] != 0 && fmt[i + 1] != '%') + { + nArgs++; /* Found an argument */ + } + + i++; /* Move past format specifier or non-argument '%' */ + } + } + + va_start(vl, fmt); + + if (chn != NULL) + { + prvTraceStoreStringEventHelper(nArgs, (uint16_t)(PSF_EVENT_USER_EVENT + nArgs + 1), chn, i, fmt, &vl); + } + else + { + prvTraceStoreStringEventHelper(nArgs, (uint16_t)(PSF_EVENT_USER_EVENT + nArgs), chn, i, fmt, &vl); + } + va_end(vl); +} +#endif /* (TRC_CFG_SCHEDULING_ONLY == 0) && (TRC_CFG_INCLUDE_USER_EVENTS == 1) */ + +/******************************************************************************* + * xTraceSetISRProperties + * + * Stores a name and priority level for an Interrupt Service Routine, to allow + * for better visualization. Returns a traceHandle used by vTraceStoreISRBegin. + * + * Example: + * #define PRIO_ISR_TIMER1 3 // the hardware priority of the interrupt + * ... + * traceHandle Timer1Handle = xTraceSetISRProperties("ISRTimer1", PRIO_ISR_TIMER1); + * ... + * void ISR_handler() + * { + * vTraceStoreISRBegin(Timer1Handle); + * ... + * vTraceStoreISREnd(0); + * } + * + ******************************************************************************/ +traceHandle xTraceSetISRProperties(const char* name, uint8_t priority) +{ + /* Save object data in object data table */ + prvTraceSaveObjectData((const void*)name, priority); + + /* Note: "name" is used both as a string argument, and the address as ID */ + prvTraceStoreStringEvent(2, PSF_EVENT_DEFINE_ISR, name, name, priority); + + /* Always save in symbol table, if the recording has not yet started */ + prvTraceSaveSymbol((const void*)name, name); + + return (traceHandle)name; +} + +/******************************************************************************* + * vTraceStoreISRBegin + * + * Registers the beginning of an Interrupt Service Routine, using a traceHandle + * provided by xTraceSetISRProperties. + * + * Example: + * #define PRIO_ISR_TIMER1 3 // the hardware priority of the interrupt + * ... + * traceHandle Timer1Handle = xTraceSetISRProperties("ISRTimer1", PRIO_ISR_TIMER1); + * ... + * void ISR_handler() + * { + * vTraceStoreISRBegin(Timer1Handle); + * ... + * vTraceStoreISREnd(0); + * } + * + ******************************************************************************/ +void vTraceStoreISRBegin(traceHandle handle) +{ + TRACE_ALLOC_CRITICAL_SECTION(); + + TRACE_ENTER_CRITICAL_SECTION(); + + /* We are at the start of a possible ISR chain. + No context switches should have been triggered now. */ + if (ISR_stack_index == -1) + isPendingContextSwitch = 0; + + if (ISR_stack_index < (TRC_CFG_MAX_ISR_NESTING) - 1) + { + ISR_stack_index++; + ISR_stack[ISR_stack_index] = (uint32_t)handle; +#if (TRC_CFG_INCLUDE_ISR_TRACING == 1) + prvTraceStoreEvent1(PSF_EVENT_ISR_BEGIN, (uint32_t)handle); +#endif + TRACE_EXIT_CRITICAL_SECTION(); + } + else + { + TRACE_EXIT_CRITICAL_SECTION(); + prvTraceError(PSF_ERROR_ISR_NESTING_OVERFLOW); + } +} + +/******************************************************************************* + * vTraceStoreISREnd + * + * Registers the end of an Interrupt Service Routine. + * + * The parameter pendingISR indicates if the interrupt has requested a + * task-switch (= 1), e.g., by signaling a semaphore. Otherwise (= 0) the + * interrupt is assumed to return to the previous context. + * + * Example: + * #define PRIO_OF_ISR_TIMER1 3 // the hardware priority of the interrupt + * traceHandle traceHandleIsrTimer1 = 0; // The ID set by the recorder + * ... + * traceHandleIsrTimer1 = xTraceSetISRProperties("ISRTimer1", PRIO_OF_ISR_TIMER1); + * ... + * void ISR_handler() + * { + * vTraceStoreISRBegin(traceHandleIsrTimer1); + * ... + * vTraceStoreISREnd(0); + * } + * + ******************************************************************************/ +void vTraceStoreISREnd(int isTaskSwitchRequired) +{ + TRACE_ALLOC_CRITICAL_SECTION(); + + TRACE_ENTER_CRITICAL_SECTION(); + + (void)ISR_stack; + + /* Is there a pending task-switch? (perhaps from an earlier ISR) */ + isPendingContextSwitch |= isTaskSwitchRequired; + + if (ISR_stack_index > 0) + { + ISR_stack_index--; + +#if (TRC_CFG_INCLUDE_ISR_TRACING == 1) + /* Store return to interrupted ISR (if nested ISRs)*/ + prvTraceStoreEvent1(PSF_EVENT_ISR_RESUME, (uint32_t)ISR_stack[ISR_stack_index]); +#endif + } + else + { + ISR_stack_index--; + + /* Store return to interrupted task, if no context switch will occur in between. */ + if ((isPendingContextSwitch == 0) || (prvTraceIsSchedulerSuspended())) + { +#if (TRC_CFG_INCLUDE_ISR_TRACING == 1) + prvTraceStoreEvent1(PSF_EVENT_TS_RESUME, (uint32_t)TRACE_GET_CURRENT_TASK()); +#endif + } + } + + TRACE_EXIT_CRITICAL_SECTION(); +} + + +/******************************************************************************* + * xTraceGetLastError + * + * Returns the last error or warning, as a string, or NULL if none. + *****************************************************************************/ +const char* xTraceGetLastError(void) +{ + /* Note: the error messages are short, in order to fit in a User Event. + Instead, the users can read more in the below comments.*/ + + switch (errorCode) + { + + case PSF_WARNING_SYMBOL_TABLE_SLOTS: + /* There was not enough symbol table slots for storing symbol names. + The number of missing slots is counted by NoRoomForSymbol. Inspect this + variable and increase TRC_CFG_SYMBOL_TABLE_SLOTS by at least that value. */ + + return "Exceeded SYMBOL_TABLE_SLOTS (see xTraceGetLastError)"; + + case PSF_WARNING_SYMBOL_MAX_LENGTH: + /* A symbol name exceeded TRC_CFG_SYMBOL_MAX_LENGTH in length. + Make sure the symbol names are at most TRC_CFG_SYMBOL_MAX_LENGTH, + or inspect LongestSymbolName and increase TRC_CFG_SYMBOL_MAX_LENGTH + to at least this value. */ + + return "Exceeded SYMBOL_MAX_LENGTH (see xTraceGetLastError)"; + + case PSF_WARNING_OBJECT_DATA_SLOTS: + /* There was not enough symbol object table slots for storing object + properties, such as task priorites. The number of missing slots is + counted by NoRoomForObjectData. Inspect this variable and increase + TRC_CFG_OBJECT_DATA_SLOTS by at least that value. */ + + return "Exceeded OBJECT_DATA_SLOTS (see xTraceGetLastError)"; + + case PSF_WARNING_STRING_TOO_LONG: + /* Some string argument was longer than the maximum payload size + and has been truncated by "MaxBytesTruncated" bytes. + + This may happen for the following functions: + - vTracePrint + - vTracePrintF + - vTraceStoreKernelObjectName + - xTraceRegisterString + - vTraceSetISRProperties + + A PSF event may store maximum 60 bytes payload, including data + arguments and string characters. For User Events, also the User + Event Channel (4 bytes) must be squeezed in, if a channel is + specified (can be NULL). */ + + return "String too long (see xTraceGetLastError)"; + + case PSF_WARNING_STREAM_PORT_READ: + /* TRC_STREAM_PORT_READ_DATA is expected to return 0 when completed successfully. + This means there is an error in the communication with host/Tracealyzer. */ + + return "TRC_STREAM_PORT_READ_DATA returned error (!= 0)."; + + case PSF_WARNING_STREAM_PORT_WRITE: + /* TRC_STREAM_PORT_WRITE_DATA is expected to return 0 when completed successfully. + This means there is an error in the communication with host/Tracealyzer. */ + + return "TRC_STREAM_PORT_WRITE_DATA returned error (!= 0)."; + + case PSF_ERROR_EVENT_CODE_TOO_LARGE: + /* The highest allowed event code is 4095, anything higher is an unexpected error. + Please contact support@percepio.com for assistance.*/ + + return "Invalid event code (see xTraceGetLastError)"; + + case PSF_ERROR_ISR_NESTING_OVERFLOW: + /* Nesting of ISR trace calls exceeded the limit (TRC_CFG_MAX_ISR_NESTING). + If this is unlikely, make sure that you call vTraceStoreISRExit in the end + of all ISR handlers. Or increase TRC_CFG_MAX_ISR_NESTING. */ + + return "Exceeded ISR nesting (see xTraceGetLastError)"; + + case PSF_ERROR_DWT_NOT_SUPPORTED: + /* On ARM Cortex-M only - failed to initialize DWT Cycle Counter since not supported by this chip. + DWT timestamping is selected automatically for ART Cortex-M3, M4 and higher, based on the __CORTEX_M + macro normally set by ARM's CMSIS library, since typically available. You can however select + SysTick timestamping instead by defining adding "#define TRC_CFG_ARM_CM_USE_SYSTICK".*/ + + return "DWT not supported (see xTraceGetLastError)"; + + case PSF_ERROR_DWT_CYCCNT_NOT_SUPPORTED: + /* On ARM Cortex-M only - failed to initialize DWT Cycle Counter since not supported by this chip. + DWT timestamping is selected automatically for ART Cortex-M3, M4 and higher, based on the __CORTEX_M + macro normally set by ARM's CMSIS library, since typically available. You can however select + SysTick timestamping instead by defining adding "#define TRC_CFG_ARM_CM_USE_SYSTICK".*/ + + return "DWT_CYCCNT not supported (see xTraceGetLastError)"; + + case PSF_ERROR_TZCTRLTASK_NOT_CREATED: + /* vTraceEnable failed creating the trace control task (TzCtrl) - incorrect parameters (priority?) + or insufficient heap size? */ + return "Could not create TzCtrl (see xTraceGetLastError)"; + + } + + return NULL; +} + +/******************************************************************************* + * vTraceClearError + * + * Clears any errors. + *****************************************************************************/ +void vTraceClearError(void) +{ + NoRoomForSymbol = 0; + LongestSymbolName = 0; + NoRoomForObjectData = 0; + MaxBytesTruncated = 0; + errorCode = PSF_ERROR_NONE; +} + +/******************************************************************************* + * vTraceStop + * + * Stops the tracing. + *****************************************************************************/ +void vTraceStop(void) +{ + prvSetRecorderEnabled(0); +} + +/******************************************************************************* + * vTraceSetRecorderDataBuffer + * + * If custom allocation is used, this function must be called so the recorder + * library knows where to save the trace data. + ******************************************************************************/ +#if (TRC_CFG_RECORDER_BUFFER_ALLOCATION == TRC_RECORDER_BUFFER_ALLOCATION_CUSTOM) + +extern char* _TzTraceData; + +void vTraceSetRecorderDataBuffer(void* pRecorderData) +{ + _TzTraceData = pRecorderData; +} +#endif + + +/******************************************************************************* +* xTraceIsRecordingEnabled +* Returns true (1) if the recorder is enabled (i.e. is recording), otherwise 0. +******************************************************************************/ +int xTraceIsRecordingEnabled(void) +{ + return (int)RecorderEnabled; +} + +void vTraceSetFilterMask(uint16_t filterMask) +{ + CurrentFilterMask = filterMask; +} + +void vTraceSetFilterGroup(uint16_t filterGroup) +{ + CurrentFilterGroup = filterGroup; +} + + +/******************************************************************************/ +/*** INTERNAL FUNCTIONS *******************************************************/ +/******************************************************************************/ + +/* Internal function for starting/stopping the recorder. */ +static void prvSetRecorderEnabled(uint32_t isEnabled) +{ + void* currentTask; + + TRACE_ALLOC_CRITICAL_SECTION(); + + if (RecorderEnabled == isEnabled) + { + return; + } + + currentTask = TRACE_GET_CURRENT_TASK(); + + TRACE_ENTER_CRITICAL_SECTION(); + + RecorderEnabled = isEnabled; + + if (currentTask == NULL) + { + currentTask = (void*)HANDLE_NO_TASK; + } + + if (RecorderEnabled) + { + TRC_STREAM_PORT_ON_TRACE_BEGIN(); + + #if (TRC_STREAM_PORT_USE_INTERNAL_BUFFER == 1) + prvPagedEventBufferInit(_TzTraceData); + #endif + + eventCounter = 0; + ISR_stack_index = -1; + prvTraceStoreHeader(); + prvTraceStoreSymbolTable(); + prvTraceStoreObjectDataTable(); + prvTraceStoreEvent3( PSF_EVENT_TRACE_START, + (uint32_t)TRACE_GET_OS_TICKS(), + (uint32_t)currentTask, + SessionCounter++); + prvTraceStoreTSConfig(); + prvTraceStoreWarnings(); + } + else + { + TRC_STREAM_PORT_ON_TRACE_END(); + } + + TRACE_EXIT_CRITICAL_SECTION(); +} + +/* Stores the symbol table on Start */ +static void prvTraceStoreSymbolTable(void) +{ + uint32_t i = 0; + uint32_t j = 0; + TRACE_ALLOC_CRITICAL_SECTION(); + + TRACE_ENTER_CRITICAL_SECTION(); + + if (RecorderEnabled) + { + for (i = 0; i < (sizeof(SymbolTable) / sizeof(uint32_t)); i += (SYMBOL_TABLE_SLOT_SIZE / sizeof(uint32_t))) + { + TRC_STREAM_PORT_ALLOCATE_EVENT(uint32_t, data, SYMBOL_TABLE_SLOT_SIZE); + if (data != NULL) + { + for (j = 0; j < (SYMBOL_TABLE_SLOT_SIZE / sizeof(uint32_t)); j++) + { + data[j] = symbolTable.SymbolTableBuffer.pSymbolTableBufferUINT32[i+j]; + } + TRC_STREAM_PORT_COMMIT_EVENT(data, SYMBOL_TABLE_SLOT_SIZE); + } + } + } + TRACE_EXIT_CRITICAL_SECTION(); +} + +/* Stores the object table on Start */ +static void prvTraceStoreObjectDataTable(void) +{ + uint32_t i = 0; + uint32_t j = 0; + TRACE_ALLOC_CRITICAL_SECTION(); + + TRACE_ENTER_CRITICAL_SECTION(); + + if (RecorderEnabled) + { + for (i = 0; i < (sizeof(ObjectDataTable) / sizeof(uint32_t)); i += (OBJECT_DATA_SLOT_SIZE / sizeof(uint32_t))) + { + TRC_STREAM_PORT_ALLOCATE_EVENT(uint32_t, data, OBJECT_DATA_SLOT_SIZE); + if (data != NULL) + { + for (j = 0; j < (OBJECT_DATA_SLOT_SIZE / sizeof(uint32_t)); j++) + { + data[j] = objectDataTable.ObjectDataTableBuffer.pObjectDataTableBufferUINT32[i+j]; + } + TRC_STREAM_PORT_COMMIT_EVENT(data, OBJECT_DATA_SLOT_SIZE); + } + } + } + TRACE_EXIT_CRITICAL_SECTION(); +} + +/* Stores the header information on Start */ +static void prvTraceStoreHeader(void) +{ + TRACE_ALLOC_CRITICAL_SECTION(); + + TRACE_ENTER_CRITICAL_SECTION(); + + if (RecorderEnabled) + { + TRC_STREAM_PORT_ALLOCATE_EVENT(PSFHeaderInfo, header, sizeof(PSFHeaderInfo)); + if (header != NULL) + { + header->psf = PSFEndianessIdentifier; + header->version = FormatVersion; + header->platform = TRACE_KERNEL_VERSION; + header->options = 0; + /* Lowest bit used for TRC_IRQ_PRIORITY_ORDER */ + header->options = header->options | (TRC_IRQ_PRIORITY_ORDER << 0); + header->symbolSize = SYMBOL_TABLE_SLOT_SIZE; + header->symbolCount = (TRC_CFG_SYMBOL_TABLE_SLOTS); + header->objectDataSize = 8; + header->objectDataCount = (TRC_CFG_OBJECT_DATA_SLOTS); + TRC_STREAM_PORT_COMMIT_EVENT(header, sizeof(PSFHeaderInfo)); + } + } + TRACE_EXIT_CRITICAL_SECTION(); +} + +/* Store the current warnings */ +static void prvTraceStoreWarnings(void) +{ + if (RecorderEnabled) + { + const char* errStr = xTraceGetLastError(); + + if (errStr != NULL) + { + vTracePrint(trcWarningChannel, errStr); + } + } +} + +/* Store an event with zero parameters (event ID only) */ +void prvTraceStoreEvent0(uint16_t eventID) +{ + TRACE_ALLOC_CRITICAL_SECTION(); + + PSF_ASSERT(eventID < 4096, PSF_ERROR_EVENT_CODE_TOO_LARGE); + + TRACE_ENTER_CRITICAL_SECTION(); + + if (RecorderEnabled) + { + eventCounter++; + + { + TRC_STREAM_PORT_ALLOCATE_EVENT(BaseEvent, event, sizeof(BaseEvent)); + if (event != NULL) + { + event->EventID = eventID | PARAM_COUNT(0); + event->EventCount = (uint16_t)eventCounter; + event->TS = prvGetTimestamp32(); + TRC_STREAM_PORT_COMMIT_EVENT(event, sizeof(BaseEvent)); + } + } + } + TRACE_EXIT_CRITICAL_SECTION(); +} + +/* Store an event with one 32-bit parameter (pointer address or an int) */ +void prvTraceStoreEvent1(uint16_t eventID, uint32_t param1) +{ + TRACE_ALLOC_CRITICAL_SECTION(); + + PSF_ASSERT(eventID < 4096, PSF_ERROR_EVENT_CODE_TOO_LARGE); + + TRACE_ENTER_CRITICAL_SECTION(); + + if (RecorderEnabled) + { + eventCounter++; + + { + TRC_STREAM_PORT_ALLOCATE_EVENT(EventWithParam_1, event, sizeof(EventWithParam_1)); + if (event != NULL) + { + event->base.EventID = eventID | PARAM_COUNT(1); + event->base.EventCount = (uint16_t)eventCounter; + event->base.TS = prvGetTimestamp32(); + event->param1 = (uint32_t)param1; + TRC_STREAM_PORT_COMMIT_EVENT(event, sizeof(EventWithParam_1)); + } + } + } + TRACE_EXIT_CRITICAL_SECTION(); +} + +/* Store an event with two 32-bit parameters */ +void prvTraceStoreEvent2(uint16_t eventID, uint32_t param1, uint32_t param2) +{ + TRACE_ALLOC_CRITICAL_SECTION(); + + PSF_ASSERT(eventID < 4096, PSF_ERROR_EVENT_CODE_TOO_LARGE); + + TRACE_ENTER_CRITICAL_SECTION(); + + if (RecorderEnabled) + { + eventCounter++; + + { + TRC_STREAM_PORT_ALLOCATE_EVENT(EventWithParam_2, event, sizeof(EventWithParam_2)); + if (event != NULL) + { + event->base.EventID = eventID | PARAM_COUNT(2); + event->base.EventCount = (uint16_t)eventCounter; + event->base.TS = prvGetTimestamp32(); + event->param1 = (uint32_t)param1; + event->param2 = param2; + TRC_STREAM_PORT_COMMIT_EVENT(event, sizeof(EventWithParam_2)); + } + } + } + TRACE_EXIT_CRITICAL_SECTION(); +} + +/* Store an event with three 32-bit parameters */ +void prvTraceStoreEvent3( uint16_t eventID, + uint32_t param1, + uint32_t param2, + uint32_t param3) +{ + TRACE_ALLOC_CRITICAL_SECTION(); + + PSF_ASSERT(eventID < 4096, PSF_ERROR_EVENT_CODE_TOO_LARGE); + + TRACE_ENTER_CRITICAL_SECTION(); + + if (RecorderEnabled) + { + eventCounter++; + + { + TRC_STREAM_PORT_ALLOCATE_EVENT(EventWithParam_3, event, sizeof(EventWithParam_3)); + if (event != NULL) + { + event->base.EventID = eventID | PARAM_COUNT(3); + event->base.EventCount = (uint16_t)eventCounter; + event->base.TS = prvGetTimestamp32(); + event->param1 = (uint32_t)param1; + event->param2 = param2; + event->param3 = param3; + TRC_STREAM_PORT_COMMIT_EVENT(event, sizeof(EventWithParam_3)); + } + } + } + TRACE_EXIT_CRITICAL_SECTION(); +} + +/* Stores an event with 32-bit integer parameters */ +void prvTraceStoreEvent(int nParam, uint16_t eventID, ...) +{ + va_list vl; + int i; + TRACE_ALLOC_CRITICAL_SECTION(); + + PSF_ASSERT(eventID < 4096, PSF_ERROR_EVENT_CODE_TOO_LARGE); + + TRACE_ENTER_CRITICAL_SECTION(); + + if (RecorderEnabled) + { + int eventSize = (int)sizeof(BaseEvent) + nParam * (int)sizeof(uint32_t); + + eventCounter++; + + { + TRC_STREAM_PORT_ALLOCATE_DYNAMIC_EVENT(largestEventType, event, eventSize); + if (event != NULL) + { + event->base.EventID = eventID | (uint16_t)PARAM_COUNT(nParam); + event->base.EventCount = (uint16_t)eventCounter; + event->base.TS = prvGetTimestamp32(); + + va_start(vl, eventID); + for (i = 0; i < nParam; i++) + { + uint32_t* tmp = (uint32_t*) &(event->data[i]); + *tmp = va_arg(vl, uint32_t); + } + va_end(vl); + + TRC_STREAM_PORT_COMMIT_EVENT(event, (uint32_t)eventSize); + } + } + } + TRACE_EXIT_CRITICAL_SECTION(); +} + +/* Stories an event with a string and 32-bit integer parameters */ +void prvTraceStoreStringEvent(int nArgs, uint16_t eventID, const char* str, ...) +{ + int len; + va_list vl; + + for (len = 0; (str[len] != 0) && (len < 52); len++); /* empty loop */ + + va_start(vl, str); + prvTraceStoreStringEventHelper(nArgs, eventID, NULL, len, str, &vl); + va_end(vl); +} + +/* Internal common function for storing string events */ +static void prvTraceStoreStringEventHelper(int nArgs, + uint16_t eventID, + traceString userEvtChannel, + int len, + const char* str, + va_list* vl) +{ + int nWords; + int nStrWords; + int i; + int offset = 0; + TRACE_ALLOC_CRITICAL_SECTION(); + + PSF_ASSERT(eventID < 4096, PSF_ERROR_EVENT_CODE_TOO_LARGE); + + /* The string length in multiples of 32 bit words (+1 for null character) */ + nStrWords = (len+1+3)/4; + + /* If a user event channel is specified, add in the list */ + if (userEvtChannel) + nArgs++; + + offset = nArgs * 4; + + /* The total number of 32-bit words needed for the whole payload */ + nWords = nStrWords + nArgs; + + if (nWords > 15) /* if attempting to store more than 60 byte (= max) */ + { + /* Truncate event if too large. The string characters are stored + last, so usually only the string is truncated, unless there a lot + of parameters... */ + + /* Diagnostics ... */ + uint32_t bytesTruncated = (uint32_t)(nWords - 15) * 4; + + if (bytesTruncated > MaxBytesTruncated) + { + MaxBytesTruncated = bytesTruncated; + } + + nWords = 15; + len = 15 * 4 - offset; + } + + TRACE_ENTER_CRITICAL_SECTION(); + + if (RecorderEnabled) + { + int eventSize = (int)sizeof(BaseEvent) + nWords * (int)sizeof(uint32_t); + + eventCounter++; + + { + TRC_STREAM_PORT_ALLOCATE_DYNAMIC_EVENT(largestEventType, event, eventSize); + if (event != NULL) + { + uint32_t* data32; + uint8_t* data8; + event->base.EventID = (eventID) | (uint16_t)PARAM_COUNT(nWords); + event->base.EventCount = (uint16_t)eventCounter; + event->base.TS = prvGetTimestamp32(); + + /* 32-bit write-pointer for the data argument */ + data32 = (uint32_t*) &(event->data[0]); + + for (i = 0; i < nArgs; i++) + { + if ((userEvtChannel != NULL) && (i == 0)) + { + /* First, add the User Event Channel if not NULL */ + data32[i] = (uint32_t)userEvtChannel; + } + else + { + /* Add data arguments... */ + data32[i] = va_arg(*vl, uint32_t); + } + } + data8 = (uint8_t*)&(event->data[0]); + for (i = 0; i < len; i++) + { + data8[offset + i] = str[i]; + } + + if (len < (15 * 4 - offset)) + data8[offset + len] = 0; /* Only truncate if we don't fill up the buffer completely */ + TRC_STREAM_PORT_COMMIT_EVENT(event, (uint32_t)eventSize); + } + } + } + + TRACE_EXIT_CRITICAL_SECTION(); +} + +/* Internal common function for storing string events without additional arguments */ +void prvTraceStoreSimpleStringEventHelper(traceString userEvtChannel, + const char* str) +{ + int len; + int nWords; + int nStrWords; + int i; + int nArgs = 0; + int offset = 0; + uint16_t eventID = PSF_EVENT_USER_EVENT; + TRACE_ALLOC_CRITICAL_SECTION(); + + PSF_ASSERT(eventID < 4096, PSF_ERROR_EVENT_CODE_TOO_LARGE); + + for (len = 0; (str[len] != 0) && (len < 52); len++); /* empty loop */ + + /* The string length in multiples of 32 bit words (+1 for null character) */ + nStrWords = (len+1+3)/4; + + /* If a user event channel is specified, add in the list */ + if (userEvtChannel) + { + nArgs++; + eventID++; + } + + offset = nArgs * 4; + + /* The total number of 32-bit words needed for the whole payload */ + nWords = nStrWords + nArgs; + + if (nWords > 15) /* if attempting to store more than 60 byte (= max) */ + { + /* Truncate event if too large. The string characters are stored + last, so usually only the string is truncated, unless there a lot + of parameters... */ + + /* Diagnostics ... */ + uint32_t bytesTruncated = (uint32_t)(nWords - 15) * 4; + + if (bytesTruncated > MaxBytesTruncated) + { + MaxBytesTruncated = bytesTruncated; + } + + nWords = 15; + len = 15 * 4 - offset; + } + + TRACE_ENTER_CRITICAL_SECTION(); + + if (RecorderEnabled) + { + int eventSize = (int)sizeof(BaseEvent) + nWords * (int)sizeof(uint32_t); + + eventCounter++; + + { + TRC_STREAM_PORT_ALLOCATE_DYNAMIC_EVENT(largestEventType, event, eventSize); + if (event != NULL) + { + uint32_t* data32; + uint8_t* data8; + event->base.EventID = (eventID) | (uint16_t)PARAM_COUNT(nWords); + event->base.EventCount = (uint16_t)eventCounter; + event->base.TS = prvGetTimestamp32(); + + /* 32-bit write-pointer for the data argument */ + data32 = (uint32_t*) &(event->data[0]); + + if (userEvtChannel != NULL) + { + /* First, add the User Event Channel if not NULL */ + data32[0] = (uint32_t)userEvtChannel; + } + + data8 = (uint8_t*) &(event->data[0]); + for (i = 0; i < len; i++) + { + data8[offset + i] = str[i]; + } + + if (len < (15 * 4 - offset)) + data8[offset + len] = 0; /* Only truncate if we don't fill up the buffer completely */ + TRC_STREAM_PORT_COMMIT_EVENT(event, (uint32_t)eventSize); + } + } + } + + TRACE_EXIT_CRITICAL_SECTION(); +} + +/* Saves a symbol name (task name etc.) in symbol table */ +void prvTraceSaveSymbol(const void *address, const char *name) +{ + uint32_t i; + uint32_t foundSlot; + uint32_t *ptrAddress; + uint8_t *ptrSymbol; + TRACE_ALLOC_CRITICAL_SECTION(); + + TRACE_ENTER_CRITICAL_SECTION(); + + foundSlot = firstFreeSymbolTableIndex; + + /* First look for previous entries using this address */ + for (i = 0; i < firstFreeSymbolTableIndex; i += SYMBOL_TABLE_SLOT_SIZE) + { + /* We access the symbol table via the union member pSymbolTableBufferUINT32 to avoid strict-aliasing issues */ + ptrAddress = &symbolTable.SymbolTableBuffer.pSymbolTableBufferUINT32[i / sizeof(uint32_t)]; + if (*ptrAddress == (uint32_t)address) + { + foundSlot = i; + break; + } + } + + if (foundSlot < SYMBOL_TABLE_BUFFER_SIZE) + { + /* We access the symbol table via the union member pSymbolTableBufferUINT32 to avoid strict-aliasing issues */ + symbolTable.SymbolTableBuffer.pSymbolTableBufferUINT32[foundSlot / sizeof(uint32_t)] = (uint32_t)address; + + /* We access the symbol table via the union member pSymbolTableBufferUINT8 to avoid strict-aliasing issues */ + ptrSymbol = &symbolTable.SymbolTableBuffer.pSymbolTableBufferUINT8[foundSlot + sizeof(uint32_t)]; + for (i = 0; i < (TRC_CFG_SYMBOL_MAX_LENGTH); i++) + { + ptrSymbol[i] = (uint8_t)name[i]; /* We do this first to ensure we also get the 0 termination, if there is one */ + + if (name[i] == 0) + break; + } + + /* Check the length of "name", if longer than SYMBOL_MAX_LENGTH */ + while ((name[i] != 0) && i < 128) + { + i++; + } + + /* Remember the longest symbol name, for diagnostic purposes */ + if (i > LongestSymbolName) + { + LongestSymbolName = i; + } + + /* Is this the last entry in the symbol table? */ + if (foundSlot == firstFreeSymbolTableIndex) + { + firstFreeSymbolTableIndex += SYMBOL_TABLE_SLOT_SIZE; + } + } + else + { + NoRoomForSymbol++; + } + + TRACE_EXIT_CRITICAL_SECTION(); +} + +/* Deletes a symbol name (task name etc.) from symbol table */ +void prvTraceDeleteSymbol(void *address) +{ + uint32_t i, j; + uint32_t *ptr, *lastEntryPtr; + TRACE_ALLOC_CRITICAL_SECTION(); + + TRACE_ENTER_CRITICAL_SECTION(); + + for (i = 0; i < firstFreeSymbolTableIndex; i += SYMBOL_TABLE_SLOT_SIZE) + { + /* We access the symbol table via the union member pSymbolTableBufferUINT32 to avoid strict-aliasing issues */ + ptr = &symbolTable.SymbolTableBuffer.pSymbolTableBufferUINT32[i / sizeof(uint32_t)]; + if (*ptr == (uint32_t)address) + { + /* See if we have another entry in the table, and that this isn't already the last entry */ + if (firstFreeSymbolTableIndex > SYMBOL_TABLE_SLOT_SIZE && i != (firstFreeSymbolTableIndex - SYMBOL_TABLE_SLOT_SIZE)) + { + /* Another entry is available, get pointer to the last one */ + /* We access the symbol table via the union member pSymbolTableBufferUINT32 to avoid strict-aliasing issues */ + lastEntryPtr = &symbolTable.SymbolTableBuffer.pSymbolTableBufferUINT32[(firstFreeSymbolTableIndex - SYMBOL_TABLE_SLOT_SIZE) / sizeof(uint32_t)]; + + /* Copy last entry to this position */ + for (j = 0; j < (SYMBOL_TABLE_SLOT_SIZE) / sizeof(uint32_t); j++) + { + ptr[j] = lastEntryPtr[j]; + } + + /* For good measure we also zero out the original position */ + *lastEntryPtr = 0; + } + else + *ptr = 0; /* No other entry found, or this is the last entry */ + + /* Lower index */ + firstFreeSymbolTableIndex -= SYMBOL_TABLE_SLOT_SIZE; + + break; + } + } + + TRACE_EXIT_CRITICAL_SECTION(); +} + +/* Saves an object data entry (current task priority) in object data table */ +void prvTraceSaveObjectData(const void *address, uint32_t data) +{ + uint32_t i; + uint32_t foundSlot; + uint32_t *ptr; + TRACE_ALLOC_CRITICAL_SECTION(); + + TRACE_ENTER_CRITICAL_SECTION(); + + foundSlot = firstFreeObjectDataTableIndex; + + /* First look for previous entries using this address */ + for (i = 0; i < firstFreeObjectDataTableIndex; i += OBJECT_DATA_SLOT_SIZE) + { + /* We access the data table via the union member pObjectDataTableBufferUINT32 to avoid strict-aliasing issues */ + ptr = &objectDataTable.ObjectDataTableBuffer.pObjectDataTableBufferUINT32[i / sizeof(uint32_t)]; + if (*ptr == (uint32_t)address) + { + foundSlot = i; + break; + } + } + + if (foundSlot < OBJECT_DATA_TABLE_BUFFER_SIZE) + { + /* We access the data table via the union member pObjectDataTableBufferUINT32 to avoid strict-aliasing issues */ + objectDataTable.ObjectDataTableBuffer.pObjectDataTableBufferUINT32[foundSlot / sizeof(uint32_t)] = (uint32_t)address; + objectDataTable.ObjectDataTableBuffer.pObjectDataTableBufferUINT32[foundSlot / sizeof(uint32_t) + 1] = data; + + /* Is this the last entry in the object data table? */ + if (foundSlot == firstFreeObjectDataTableIndex) + { + firstFreeObjectDataTableIndex += OBJECT_DATA_SLOT_SIZE; + } + } + else + { + NoRoomForObjectData++; + } + + TRACE_EXIT_CRITICAL_SECTION(); +} + +/* Removes an object data entry (task base priority) from object data table */ +void prvTraceDeleteObjectData(void *address) +{ + uint32_t i, j; + uint32_t *ptr, *lastEntryPtr; + TRACE_ALLOC_CRITICAL_SECTION(); + + TRACE_ENTER_CRITICAL_SECTION(); + + for (i = 0; i < firstFreeObjectDataTableIndex; i += OBJECT_DATA_SLOT_SIZE) + { + /* We access the data table via the union member pObjectDataTableBufferUINT32 to avoid strict-aliasing issues */ + ptr = &objectDataTable.ObjectDataTableBuffer.pObjectDataTableBufferUINT32[i / sizeof(uint32_t)]; + if (*ptr == (uint32_t)address) + { + /* See if we have another entry in the table, and that this isn't already the last entry */ + if (firstFreeObjectDataTableIndex > OBJECT_DATA_SLOT_SIZE && i != (firstFreeObjectDataTableIndex - OBJECT_DATA_SLOT_SIZE)) + { + /* Another entry is available, get pointer to the last one */ + /* We access the data table via the union member pObjectDataTableBufferUINT32 to avoid strict-aliasing issues */ + lastEntryPtr = &objectDataTable.ObjectDataTableBuffer.pObjectDataTableBufferUINT32[(firstFreeObjectDataTableIndex - OBJECT_DATA_SLOT_SIZE) / sizeof(uint32_t)]; + + /* Copy last entry to this position */ + for (j = 0; j < (OBJECT_DATA_SLOT_SIZE) / sizeof(uint32_t); j++) + { + ptr[j] = lastEntryPtr[j]; + } + + /* For good measure we also zero out the original position */ + *lastEntryPtr = 0; + } + else + *ptr = 0; /* No other entry found, or this is the last entry */ + + /* Lower index */ + firstFreeObjectDataTableIndex -= OBJECT_DATA_SLOT_SIZE; + + break; + } + } + + TRACE_EXIT_CRITICAL_SECTION(); +} + +/* Checks if the provided command is a valid command */ +int prvIsValidCommand(TracealyzerCommandType* cmd) +{ + uint16_t checksum = (uint16_t)(0xFFFF - ( cmd->cmdCode + + cmd->param1 + + cmd->param2 + + cmd->param3 + + cmd->param4 + + cmd->param5)); + + if (cmd->checksumMSB != (unsigned char)(checksum >> 8)) + return 0; + + if (cmd->checksumLSB != (unsigned char)(checksum & 0xFF)) + return 0; + + if (cmd->cmdCode > CMD_LAST_COMMAND) + return 0; + + return 1; +} + +/* Executed the received command (Start or Stop) */ +void prvProcessCommand(TracealyzerCommandType* cmd) +{ + switch(cmd->cmdCode) + { + case CMD_SET_ACTIVE: + prvSetRecorderEnabled(cmd->param1); + break; + default: + break; + } +} + +/* Called on warnings, when the recording can continue. */ +void prvTraceWarning(int errCode) +{ + if (!errorCode) + { + errorCode = errCode; + prvTraceStoreWarnings(); + } +} + +/* Called on critical errors in the recorder. Stops the recorder! */ +void prvTraceError(int errCode) +{ + if (! errorCode) + { + errorCode = errCode; + prvTraceStoreWarnings(); + vTracePrintF(trcWarningChannel, "Recorder stopped in prvTraceError()"); + + prvSetRecorderEnabled(0); + } +} + +/* If using DWT timestamping (default on ARM Cortex-M3, M4 and M7), make sure the DWT unit is initialized. */ +#ifndef TRC_CFG_ARM_CM_USE_SYSTICK +#if ((TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_Cortex_M) && (defined (__CORTEX_M) && (__CORTEX_M >= 0x03))) + +void prvTraceInitCortexM() +{ + /* Make sure the DWT registers are unlocked, in case the debugger doesn't do this. */ + TRC_REG_ITM_LOCKACCESS = TRC_ITM_LOCKACCESS_UNLOCK; + + /* Make sure DWT is enabled is enabled, if supported */ + TRC_REG_DEMCR |= TRC_DEMCR_TRCENA; + + do + { + /* Verify that DWT is supported */ + if (TRC_REG_DEMCR == 0) + { + /* This function is called on Cortex-M3, M4 and M7 devices to initialize + the DWT unit, assumed present. The DWT cycle counter is used for timestamping. + + If the below error is produced, the DWT unit does not seem to be available. + + In that case, define the macro TRC_CFG_ARM_CM_USE_SYSTICK in your build + to use SysTick timestamping instead, or define your own timestamping by + setting TRC_CFG_HARDWARE_PORT to TRC_HARDWARE_PORT_APPLICATION_DEFINED + and make the necessary definitions, as explained in trcHardwarePort.h.*/ + + prvTraceError(PSF_ERROR_DWT_NOT_SUPPORTED); + break; + } + + /* Verify that DWT_CYCCNT is supported */ + if (TRC_REG_DWT_CTRL & TRC_DWT_CTRL_NOCYCCNT) + { + /* This function is called on Cortex-M3, M4 and M7 devices to initialize + the DWT unit, assumed present. The DWT cycle counter is used for timestamping. + + If the below error is produced, the cycle counter does not seem to be available. + + In that case, define the macro TRC_CFG_ARM_CM_USE_SYSTICK in your build + to use SysTick timestamping instead, or define your own timestamping by + setting TRC_CFG_HARDWARE_PORT to TRC_HARDWARE_PORT_APPLICATION_DEFINED + and make the necessary definitions, as explained in trcHardwarePort.h.*/ + + prvTraceError(PSF_ERROR_DWT_CYCCNT_NOT_SUPPORTED); + break; + } + + /* Reset the cycle counter */ + TRC_REG_DWT_CYCCNT = 0; + + /* Enable the cycle counter */ + TRC_REG_DWT_CTRL |= TRC_DWT_CTRL_CYCCNTENA; + + } while(0); /* breaks above jump here */ +} +#endif +#endif + +/* Performs timestamping using definitions in trcHardwarePort.h */ +static uint32_t prvGetTimestamp32(void) +{ +#if ((TRC_HWTC_TYPE == TRC_FREE_RUNNING_32BIT_INCR) || (TRC_HWTC_TYPE == TRC_FREE_RUNNING_32BIT_DECR)) + return TRC_HWTC_COUNT; +#endif + +#if ((TRC_HWTC_TYPE == TRC_CUSTOM_TIMER_INCR) || (TRC_HWTC_TYPE == TRC_CUSTOM_TIMER_DECR)) + return TRC_HWTC_COUNT; +#endif + +#if ((TRC_HWTC_TYPE == TRC_OS_TIMER_INCR) || (TRC_HWTC_TYPE == TRC_OS_TIMER_DECR)) + uint32_t ticks = TRACE_GET_OS_TICKS(); + return ((TRC_HWTC_COUNT) & 0x00FFFFFFU) + ((ticks & 0x000000FFU) << 24); +#endif +} + +/* Store the Timestamp Config event */ +static void prvTraceStoreTSConfig(void) +{ + /* If not overridden using vTraceSetFrequency, use default value */ + if (timestampFrequency == 0) + { + timestampFrequency = TRC_HWTC_FREQ_HZ; + } + + #if (TRC_HWTC_TYPE == TRC_CUSTOM_TIMER_INCR || TRC_HWTC_TYPE == TRC_CUSTOM_TIMER_DECR) + + prvTraceStoreEvent(5, + PSF_EVENT_TS_CONFIG, + (uint32_t)timestampFrequency, + (uint32_t)(TRACE_TICK_RATE_HZ), + (uint32_t)(TRC_HWTC_TYPE), + (uint32_t)(TRC_CFG_ISR_TAILCHAINING_THRESHOLD), + (uint32_t)(TRC_HWTC_PERIOD)); + + #else + + prvTraceStoreEvent(4, + PSF_EVENT_TS_CONFIG, + (uint32_t)timestampFrequency, + (uint32_t)(TRACE_TICK_RATE_HZ), + (uint32_t)(TRC_HWTC_TYPE), + (uint32_t)(TRC_CFG_ISR_TAILCHAINING_THRESHOLD)); + #endif +} + +/* Retrieve a buffer page to write to. */ +static int prvAllocateBufferPage(int prevPage) +{ + int index; + int count = 0; + + index = (prevPage + 1) % (TRC_CFG_PAGED_EVENT_BUFFER_PAGE_COUNT); + + while((PageInfo[index].Status != PAGE_STATUS_FREE) && (count ++ < (TRC_CFG_PAGED_EVENT_BUFFER_PAGE_COUNT))) + { + index = (index + 1) % (TRC_CFG_PAGED_EVENT_BUFFER_PAGE_COUNT); + } + + if (PageInfo[index].Status == PAGE_STATUS_FREE) + { + return index; + } + + return -1; +} + +/* Mark the page read as complete. */ +static void prvPageReadComplete(int pageIndex) +{ + TRACE_ALLOC_CRITICAL_SECTION(); + + TRACE_ENTER_CRITICAL_SECTION(); + PageInfo[pageIndex].BytesRemaining = (TRC_CFG_PAGED_EVENT_BUFFER_PAGE_SIZE); + PageInfo[pageIndex].WritePointer = &EventBuffer[pageIndex * (TRC_CFG_PAGED_EVENT_BUFFER_PAGE_SIZE)]; + PageInfo[pageIndex].Status = PAGE_STATUS_FREE; + + TotalBytesRemaining += (TRC_CFG_PAGED_EVENT_BUFFER_PAGE_SIZE); + + TRACE_EXIT_CRITICAL_SECTION(); +} + +/* Get the current buffer page index and remaining number of bytes. */ +static int prvGetBufferPage(int32_t* bytesUsed) +{ + static int8_t lastPage = -1; + int count = 0; + int8_t index = (int8_t) ((lastPage + 1) % (TRC_CFG_PAGED_EVENT_BUFFER_PAGE_COUNT)); + + while((PageInfo[index].Status != PAGE_STATUS_READ) && (count++ < (TRC_CFG_PAGED_EVENT_BUFFER_PAGE_COUNT))) + { + index = (int8_t)((index + 1) % (TRC_CFG_PAGED_EVENT_BUFFER_PAGE_COUNT)); + } + + if (PageInfo[index].Status == PAGE_STATUS_READ) + { + *bytesUsed = (TRC_CFG_PAGED_EVENT_BUFFER_PAGE_SIZE) - PageInfo[index].BytesRemaining; + lastPage = index; + return index; + } + + *bytesUsed = 0; + + return -1; +} + +/******************************************************************************* + * uint32_t prvPagedEventBufferTransfer(void) + * + * Transfers one buffer page of trace data, if a full page is available, using + * the macro TRC_STREAM_PORT_WRITE_DATA as defined in trcStreamingPort.h. + * + * This function is intended to be called the periodic TzCtrl task with a suitable + * delay (e.g. 10-100 ms). + * + * Returns the number of bytes sent. If non-zero, it is good to call this + * again, in order to send any additional data waiting in the buffer. + * If zero, wait a while before calling again. + * + * In case of errors from the streaming interface, it registers a warning + * (PSF_WARNING_STREAM_PORT_WRITE) provided by xTraceGetLastError(). + * + *******************************************************************************/ +uint32_t prvPagedEventBufferTransfer(void) +{ + int8_t pageToTransfer = -1; + int32_t bytesTransferredTotal = 0; + int32_t bytesTransferredNow = 0; + int32_t bytesToTransfer; + + pageToTransfer = (int8_t)prvGetBufferPage(&bytesToTransfer); + + /* bytesToTransfer now contains the number of "valid" bytes in the buffer page, that should be transmitted. + There might be some unused junk bytes in the end, that must be ignored. */ + + if (pageToTransfer > -1) + { + while (1) /* Keep going until we have transferred all that we intended to */ + { + if (TRC_STREAM_PORT_WRITE_DATA( + &EventBuffer[pageToTransfer * (TRC_CFG_PAGED_EVENT_BUFFER_PAGE_SIZE) + bytesTransferredTotal], + (uint32_t)(bytesToTransfer - bytesTransferredTotal), + &bytesTransferredNow) == 0) + { + /* Write was successful. Update the number of transferred bytes. */ + bytesTransferredTotal += bytesTransferredNow; + + if (bytesTransferredTotal == bytesToTransfer) + { + /* All bytes have been transferred. Mark the buffer page as "Read Complete" (so it can be written to) and return OK. */ + prvPageReadComplete(pageToTransfer); + return (uint32_t)bytesTransferredTotal; + } + } + else + { + /* Some error from the streaming interface... */ + prvTraceWarning(PSF_WARNING_STREAM_PORT_WRITE); + return 0; + } + } + } + return 0; +} + +/******************************************************************************* + * void* prvPagedEventBufferGetWritePointer(int sizeOfEvent) + * + * Returns a pointer to an available location in the buffer able to store the + * requested size. + * + * Return value: The pointer. + * + * Parameters: + * - sizeOfEvent: The size of the event that is to be placed in the buffer. + * +*******************************************************************************/ +void* prvPagedEventBufferGetWritePointer(int sizeOfEvent) +{ + void* ret; + static int currentWritePage = -1; + + if (currentWritePage == -1) + { + currentWritePage = prvAllocateBufferPage(currentWritePage); + if (currentWritePage == -1) + { + DroppedEventCounter++; + return NULL; + } + } + + if (PageInfo[currentWritePage].BytesRemaining - sizeOfEvent < 0) + { + PageInfo[currentWritePage].Status = PAGE_STATUS_READ; + + TotalBytesRemaining -= PageInfo[currentWritePage].BytesRemaining; // Last trailing bytes + + if (TotalBytesRemaining < TotalBytesRemaining_LowWaterMark) + TotalBytesRemaining_LowWaterMark = TotalBytesRemaining; + + currentWritePage = prvAllocateBufferPage(currentWritePage); + if (currentWritePage == -1) + { + DroppedEventCounter++; + return NULL; + } + } + ret = PageInfo[currentWritePage].WritePointer; + PageInfo[currentWritePage].WritePointer += sizeOfEvent; + PageInfo[currentWritePage].BytesRemaining = (uint16_t)(PageInfo[currentWritePage].BytesRemaining -sizeOfEvent); + + TotalBytesRemaining = (TotalBytesRemaining-(uint16_t)sizeOfEvent); + + if (TotalBytesRemaining < TotalBytesRemaining_LowWaterMark) + TotalBytesRemaining_LowWaterMark = TotalBytesRemaining; + + return ret; +} + +/******************************************************************************* + * void prvPagedEventBufferInit(char* buffer) + * + * Assigns the buffer to use and initializes the PageInfo structure. + * + * Return value: void + * + * Parameters: + * - char* buffer: pointer to the trace data buffer, allocated by the caller. + * +*******************************************************************************/ +void prvPagedEventBufferInit(char* buffer) +{ + int i; + TRACE_ALLOC_CRITICAL_SECTION(); + + EventBuffer = buffer; + + TRACE_ENTER_CRITICAL_SECTION(); + for (i = 0; i < (TRC_CFG_PAGED_EVENT_BUFFER_PAGE_COUNT); i++) + { + PageInfo[i].BytesRemaining = (TRC_CFG_PAGED_EVENT_BUFFER_PAGE_SIZE); + PageInfo[i].WritePointer = &EventBuffer[i * (TRC_CFG_PAGED_EVENT_BUFFER_PAGE_SIZE)]; + PageInfo[i].Status = PAGE_STATUS_FREE; + } + TRACE_EXIT_CRITICAL_SECTION(); + +} + +#endif /*(TRC_USE_TRACEALYZER_RECORDER == 1)*/ + +#endif /*(TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING)*/ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/See also FreeRTOS+TCP.url b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/See also FreeRTOS+TCP.url new file mode 100644 index 0000000..2da199c --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/See also FreeRTOS+TCP.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 +[InternetShortcut] +URL=http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/index.html +IDList= diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/readme.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/readme.txt new file mode 100644 index 0000000..24bb546 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/FreeRTOS-Plus-UDP/readme.txt @@ -0,0 +1,4 @@ +FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by FreeRTOS+TCP, +which was brought into the main download in FreeRTOS V10.0.0. FreeRTOS+TCP can +be configured as a UDP only stack, and FreeRTOS+UDP does not contain the patches +applied to FreeRTOS+TCP. \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/CREDITS.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/CREDITS.txt new file mode 100644 index 0000000..7b2f608 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/CREDITS.txt @@ -0,0 +1,21 @@ +Reliance Edge Credits +===================== + +This is a list (or partial list) of people who have made non-trivial or +noteworthy contributions to the Reliance Edge project. It is sorted by name. +Entries are formatted as below: + +Real Name (githubaccount) +Short description of how Real Name contributed to Reliance Edge. + +The real name may be withheld by request and the GitHub account name might be +missing if the contributor does not use GitHub. + +Credits +------- + +Jean-Christophe Dubois (jcdubois) +Created a user-space Linux port of Reliance Edge, ported the open-source host +tools (including the formatter and image builder) to Linux, and created a FUSE +(File System in User Space) implementation for Reliance Edge. + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/LICENSE.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/LICENSE.txt new file mode 100644 index 0000000..1f963da --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/LICENSE.txt @@ -0,0 +1,340 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Lesser General Public License instead.) You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +this service if you wish), that you receive source code or can get it +if you want it, that you can change the software or use pieces of it +in new free programs; and that you know you can do these things. + + To protect your rights, we need to make restrictions that forbid +anyone to deny you these rights or to ask you to surrender the rights. +These restrictions translate to certain responsibilities for you if you +distribute copies of the software, or if you modify it. + + For example, if you distribute copies of such a program, whether +gratis or for a fee, you must give the recipients all the rights that +you have. You must make sure that they, too, receive or can get the +source code. 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To prevent this, we have made it clear that any +patent must be licensed for everyone's free use or not licensed at all. + + The precise terms and conditions for copying, distribution and +modification follow. + + GNU GENERAL PUBLIC LICENSE + TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + + 0. This License applies to any program or other work which contains +a notice placed by the copyright holder saying it may be distributed +under the terms of this General Public License. The "Program", below, +refers to any such program or work, and a "work based on the Program" +means either the Program or any derivative work under copyright law: +that is to say, a work containing the Program or a portion of it, +either verbatim or with modifications and/or translated into another +language. (Hereinafter, translation is included without limitation in +the term "modification".) Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. The act of +running the Program is not restricted, and the output from the Program +is covered only if its contents constitute a work based on the +Program (independent of having been made by running the Program). +Whether that is true depends on what the Program does. + + 1. You may copy and distribute verbatim copies of the Program's +source code as you receive it, in any medium, provided that you +conspicuously and appropriately publish on each copy an appropriate +copyright notice and disclaimer of warranty; keep intact all the +notices that refer to this License and to the absence of any warranty; +and give any other recipients of the Program a copy of this License +along with the Program. + +You may charge a fee for the physical act of transferring a copy, and +you may at your option offer warranty protection in exchange for a fee. + + 2. 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It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/README.md b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/README.md new file mode 100644 index 0000000..0c2e228 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/README.md @@ -0,0 +1,123 @@ +# Reliance Edge + +Reliance Edge is a small, portable, highly reliable power-fail safe file system +for resource-constrained embedded systems like microcontrollers. It is written +in C and provides a familiar POSIX-like file system API, making it easy to use +in your application; or an alternate minimalist API if your application has +simple storage needs. Reliance Edge is highly configurable and can be tuned to +the precise needs of your application. + +## Getting Help + +You will find this section later in our readme as well - but we wanted to tell +you up front: DATALIGHT WANTS TO HEAR FROM YOU! Whether it's just to make +comments about the product, to suggest new features, or to tell us what you +don't like - reach out! All comments and inquiries can be directed to +. + +## Documentation + +The complete documentation for Reliance Edge is distributed separately. It +includes an API reference and detailed discussions of various aspects of using +Reliance Edge, including porting, building, configuring, and testing. This +complete documentation, called the _Developer's Guide_, can be obtained for free +from here: + + + +In addition this README, see doc/release_notes.md for a list of updates +to Reliance Edge and a list of known issues. There is also a quick-start +guide in the doc/ directory that describes step-by-step how to compile +and run Reliance Edge in a simulated Windows environment. + +## Why Use Reliance Edge? + +Reliance Edge is ideal for small embedded systems with data storage +requirements, especially if there is a chance of sudden power loss or other +system failures. Compared to "raw" disk access, using a file system like +Reliance Edge removes the burden of tracking which sectors belong to which +objects, and allows data to be updated more reliably. Compared to the FAT file +system, using Reliance Edge eliminates the possibility that file system data +will be left in an inconsistent state, corrupting the disk; Reliance Edge does +not need a fsck/CHKDSK utility. Compared to journaling file systems, Reliance +Edge has less overhead and results in less storage media wear for longer device +lifetimes. + +Reliance Edge uses a unique transactional model that not only prevents file +system corruption but also allows a set of changes to be made in an atomic "all +or nothing" fashion. This is very useful for applications that make sets of +interrelated changes. By using the features of Reliance Edge, a set of changes +can be incorporated into a single atomic transaction, which is committed in its +entirety or not at all even if interrupted by power loss; this means the +application does not need code to recover from partially-finished updates. + +## Hardware + +The typical hardware for Reliance Edge is a 32-bit microcontroller, but other +targets are possible. In its typical configurations, Reliance Edge needs at +least 4 KB to 5 KB of RAM, 11 to 18 KB of code space (on the ROM or NOR flash), +and 500 to 700 bytes of stack. + +Reliance Edge is not designed for high-end embedded systems that run complicated +operating systems like Linux or Windows Embedded Compact. Embedded systems of +that variety are better served by other file systems, like Datalight's +[Reliance Nitro](http://www.datalight.com/products/embedded-file-systems/reliance-nitro). + +## Getting Reliance Edge Working + +Before you can use Reliance Edge, it must be ported and configured. At a +minimum, porting includes filling-in functions so that Reliance Edge can issue +commands to your storage medium; depending on your needs, other functions may +need to be filled in as well. These functions reside in a subdirectory in the +os/ directory; see os/stub/ for a blank set of functions. Configuring includes +creating a project directory (start by copying projects/newproj) and creating +the two configuration files (redconf.h/redconf.c) using the Reliance Edge +Configuration Utility (which can be downloaded from +). + +These topics are covered in much greater detail in the _Developer's Guide_, +linked above. + +## Using Reliance Edge + +Using Reliance Edge is a simple matter of including the primary Reliance Edge +application header in your application (either include/redposix.h or +include/redfse.h) and compiling and linking against Reliance Edge binaries. +The Reliance Edge driver must be initialized before it is used (via the +red\_init() or RedFseInit() functions) and then volumes can be mounted and file +and directory functions invoked. The Reliance Edge API is documented in the +_Developer's Guide_ (linked above) and also via comments in the source code. + +## Licensing + +Reliance Edge is an open-source project licensed under the GNU General Public +License v2 (GPLv2). Businesses and individuals that for commercial or other +reasons cannot comply with the terms of the GPLv2 license may obtain a +commercial license before incorporating Reliance Edge into proprietary software +for distribution in any form. Visit +for more information. The commercial distribution also includes extra tests and +tools not distributed with the GPLv2 version. + +See LICENSE.txt for the full license terms of this distribution of the product. + +## Getting Help + +If you need assistance using Reliance Edge, and you have already consulted the +_Developer's Guide_, contact . + +In the near future, a community forum or message board will be set up to +facilitate discussion of Reliance Edge and allow users to get help from +Datalight and from each other. In the meantime, please use the email address +given above. + +## Contributing + +Contributions to Reliance Edge are welcome. Our policy is that Datalight must +own the copyright of all code incorporated into Reliance Edge; if contributing a +significant amount of code, you will be asked to file a copyright assignment +agreement. See CONTRIBUTING.txt for further details and contribution +guidelines. + +To report bugs, please create a GitHub issue or contact +. + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/README.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/README.txt new file mode 100644 index 0000000..106d923 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/README.txt @@ -0,0 +1,140 @@ + + +RELIANCE EDGE + + +Reliance Edge is a small, portable, highly reliable power-fail safe file +system for resource-constrained embedded systems like microcontrollers. +It is written in C and provides a familiar POSIX-like file system API, +making it easy to use in your application; or an alternate minimalist +API if your application has simple storage needs. Reliance Edge is +highly configurable and can be tuned to the precise needs of your +application. + + +Getting Help + +You will find this section later in our readme as well - but we wanted +to tell you up front: DATALIGHT WANTS TO HEAR FROM YOU! Whether it's +just to make comments about the product, to suggest new features, or to +tell us what you don't like - reach out! All comments and inquiries can +be directed to RelianceEdgeSupport@datalight.com. + + +Documentation + +The complete documentation for Reliance Edge is distributed separately. +It includes an API reference and detailed discussions of various aspects +of using Reliance Edge, including porting, building, configuring, and +testing. This complete documentation, called the _Developer's Guide_, +can be obtained for free from here: + +http://www.datalight.com/reliance-edge + +In addition this README, see doc/release_notes.md for a list of updates +to Reliance Edge and a list of known issues. There is also a quick-start +guide in the doc/ directory that describes step-by-step how to compile +and run Reliance Edge in a simulated Windows environment. + + +Why Use Reliance Edge? + +Reliance Edge is ideal for small embedded systems with data storage +requirements, especially if there is a chance of sudden power loss or +other system failures. Compared to "raw" disk access, using a file +system like Reliance Edge removes the burden of tracking which sectors +belong to which objects, and allows data to be updated more reliably. +Compared to the FAT file system, using Reliance Edge eliminates the +possibility that file system data will be left in an inconsistent state, +corrupting the disk; Reliance Edge does not need a fsck/CHKDSK utility. +Compared to journaling file systems, Reliance Edge has less overhead and +results in less storage media wear for longer device lifetimes. + +Reliance Edge uses a unique transactional model that not only prevents +file system corruption but also allows a set of changes to be made in an +atomic "all or nothing" fashion. This is very useful for applications +that make sets of interrelated changes. By using the features of +Reliance Edge, a set of changes can be incorporated into a single atomic +transaction, which is committed in its entirety or not at all even if +interrupted by power loss; this means the application does not need code +to recover from partially-finished updates. + + +Hardware + +The typical hardware for Reliance Edge is a 32-bit microcontroller, but +other targets are possible. In its typical configurations, Reliance Edge +needs at least 4 KB to 5 KB of RAM, 11 to 18 KB of code space (on the +ROM or NOR flash), and 500 to 700 bytes of stack. + +Reliance Edge is not designed for high-end embedded systems that run +complicated operating systems like Linux or Windows Embedded Compact. +Embedded systems of that variety are better served by other file +systems, like Datalight's Reliance Nitro. + + +Getting Reliance Edge Working + +Before you can use Reliance Edge, it must be ported and configured. At a +minimum, porting includes filling-in functions so that Reliance Edge can +issue commands to your storage medium; depending on your needs, other +functions may need to be filled in as well. These functions reside in a +subdirectory in the os/ directory; see os/stub/ for a blank set of +functions. Configuring includes creating a project directory (start by +copying projects/newproj) and creating the two configuration files +(redconf.h/redconf.c) using the Reliance Edge Configuration Utility +(which can be downloaded from http://www.datalight.com/reliance-edge). + +These topics are covered in much greater detail in the _Developer's +Guide_, linked above. + + +Using Reliance Edge + +Using Reliance Edge is a simple matter of including the primary Reliance +Edge application header in your application (either include/redposix.h +or include/redfse.h) and compiling and linking against Reliance Edge +binaries. The Reliance Edge driver must be initialized before it is used +(via the red_init() or RedFseInit() functions) and then volumes can be +mounted and file and directory functions invoked. The Reliance Edge API +is documented in the _Developer's Guide_ (linked above) and also via +comments in the source code. + + +Licensing + +Reliance Edge is an open-source project licensed under the GNU General +Public License v2 (GPLv2). Businesses and individuals that for +commercial or other reasons cannot comply with the terms of the GPLv2 +license may obtain a commercial license before incorporating Reliance +Edge into proprietary software for distribution in any form. Visit +http://www.datalight.com/reliance-edge for more information. The +commercial distribution also includes extra tests and tools not +distributed with the GPLv2 version. + +See LICENSE.txt for the full license terms of this distribution of the +product. + + +Getting Help + +If you need assistance using Reliance Edge, and you have already +consulted the _Developer's Guide_, contact +RelianceEdgeSupport@datalight.com. + +In the near future, a community forum or message board will be set up to +facilitate discussion of Reliance Edge and allow users to get help from +Datalight and from each other. In the meantime, please use the email +address given above. + + +Contributing + +Contributions to Reliance Edge are welcome. Our policy is that Datalight +must own the copyright of all code incorporated into Reliance Edge; if +contributing a significant amount of code, you will be asked to file a +copyright assignment agreement. See CONTRIBUTING.txt for further details +and contribution guidelines. + +To report bugs, please create a GitHub issue or contact +RelianceEdgeSupport@datalight.com. diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/blockio.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/blockio.c new file mode 100644 index 0000000..897143d --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/blockio.c @@ -0,0 +1,198 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements block device I/O using logical blocks as the units. + + The OS block device implementations operate on sectors. The core does I/O + in terms of logical blocks: this module translates from logical blocks to + sectors. + + If bBlockIoRetries is greater than 0 for the current volume, then this + module will retry block device calls on failure up to the configured number + of times. This behavior caters to the type of unreliable hardware and + drivers that are sometimes found in the IoT world, where one operation may + fail but the next may still succeed. +*/ +#include +#include + + +/** @brief Read a range of logical blocks. + + @param bVolNum The volume whose block device is being read from. + @param ulBlockStart The first block to read. + @param ulBlockCount The number of blocks to read. + @param pBuffer The buffer to populate with the data read. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EINVAL Invalid parameters. +*/ +REDSTATUS RedIoRead( + uint8_t bVolNum, + uint32_t ulBlockStart, + uint32_t ulBlockCount, + void *pBuffer) +{ + REDSTATUS ret = 0; + + if( (bVolNum >= REDCONF_VOLUME_COUNT) + || (ulBlockStart >= gaRedVolume[bVolNum].ulBlockCount) + || ((gaRedVolume[bVolNum].ulBlockCount - ulBlockStart) < ulBlockCount) + || (ulBlockCount == 0U) + || (pBuffer == NULL)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + uint8_t bSectorShift = gaRedVolume[bVolNum].bBlockSectorShift; + uint64_t ullSectorStart = (uint64_t)ulBlockStart << bSectorShift; + uint32_t ulSectorCount = ulBlockCount << bSectorShift; + uint8_t bRetryIdx; + + REDASSERT(bSectorShift < 32U); + REDASSERT((ulSectorCount >> bSectorShift) == ulBlockCount); + + for(bRetryIdx = 0U; bRetryIdx <= gpRedVolConf->bBlockIoRetries; bRetryIdx++) + { + ret = RedOsBDevRead(bVolNum, ullSectorStart, ulSectorCount, pBuffer); + + if(ret == 0) + { + break; + } + } + } + + CRITICAL_ASSERT(ret == 0); + + return ret; +} + + +#if REDCONF_READ_ONLY == 0 +/** @brief Write a range of logical blocks. + + @param bVolNum The volume whose block device is being written to. + @param ulBlockStart The first block to write. + @param ulBlockCount The number of blocks to write. + @param pBuffer The buffer containing the data to write. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EINVAL Invalid parameters. +*/ +REDSTATUS RedIoWrite( + uint8_t bVolNum, + uint32_t ulBlockStart, + uint32_t ulBlockCount, + const void *pBuffer) +{ + REDSTATUS ret = 0; + + if( (bVolNum >= REDCONF_VOLUME_COUNT) + || (ulBlockStart >= gaRedVolume[bVolNum].ulBlockCount) + || ((gaRedVolume[bVolNum].ulBlockCount - ulBlockStart) < ulBlockCount) + || (ulBlockCount == 0U) + || (pBuffer == NULL)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + uint8_t bSectorShift = gaRedVolume[bVolNum].bBlockSectorShift; + uint64_t ullSectorStart = (uint64_t)ulBlockStart << bSectorShift; + uint32_t ulSectorCount = ulBlockCount << bSectorShift; + uint8_t bRetryIdx; + + REDASSERT(bSectorShift < 32U); + REDASSERT((ulSectorCount >> bSectorShift) == ulBlockCount); + + for(bRetryIdx = 0U; bRetryIdx <= gpRedVolConf->bBlockIoRetries; bRetryIdx++) + { + ret = RedOsBDevWrite(bVolNum, ullSectorStart, ulSectorCount, pBuffer); + + if(ret == 0) + { + break; + } + } + } + + CRITICAL_ASSERT(ret == 0); + + return ret; +} + + +/** @brief Flush any caches beneath the file system. + + @param bVolNum The volume number of the volume whose block device is being + flushed. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p bVolNum is an invalid volume number. + @retval -RED_EIO A disk I/O error occurred. +*/ +REDSTATUS RedIoFlush( + uint8_t bVolNum) +{ + REDSTATUS ret = 0; + + if(bVolNum >= REDCONF_VOLUME_COUNT) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + uint8_t bRetryIdx; + + for(bRetryIdx = 0U; bRetryIdx <= gpRedVolConf->bBlockIoRetries; bRetryIdx++) + { + ret = RedOsBDevFlush(bVolNum); + + if(ret == 0) + { + break; + } + } + } + + CRITICAL_ASSERT(ret == 0); + + return ret; +} +#endif /* REDCONF_READ_ONLY == 0 */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/buffer.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/buffer.c new file mode 100644 index 0000000..17717e0 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/buffer.c @@ -0,0 +1,1212 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements the block device buffering system. + + This module implements the block buffer cache. It has a number of block + sized buffers which are used to store data from a given block (identified + by both block number and volume number: this cache is shared among all + volumes). Block buffers may be either dirty or clean. Most I/O passes + through this module. When a buffer is needed for a block which is not in + the cache, a "victim" is selected via a simple LRU scheme. +*/ +#include +#include + + +#if DINDIR_POINTERS > 0U + #define INODE_META_BUFFERS 3U /* Inode, double indirect, indirect */ +#elif REDCONF_INDIRECT_POINTERS > 0U + #define INODE_META_BUFFERS 2U /* Inode, indirect */ +#elif REDCONF_DIRECT_POINTERS == INODE_ENTRIES + #define INODE_META_BUFFERS 1U /* Inode only */ +#endif + +#define INODE_BUFFERS (INODE_META_BUFFERS + 1U) /* Add data buffer */ + +#if REDCONF_IMAP_EXTERNAL == 1 + #define IMAP_BUFFERS 1U +#else + #define IMAP_BUFFERS 0U +#endif + +#if (REDCONF_READ_ONLY == 1) || (REDCONF_API_FSE == 1) + /* Read, write, truncate, lookup: One inode all the way down, plus imap. + */ + #define MINIMUM_BUFFER_COUNT (INODE_BUFFERS + IMAP_BUFFERS) +#elif REDCONF_API_POSIX == 1 + #if REDCONF_API_POSIX_RENAME == 1 + #if REDCONF_RENAME_ATOMIC == 1 + /* Two parent directories all the way down. Source and destination inode + buffer. One inode buffer for cyclic rename detection. Imap. The + parent inode buffers are released before deleting the destination + inode, so that does not increase the minimum. + */ + #define MINIMUM_BUFFER_COUNT (INODE_BUFFERS + INODE_BUFFERS + 3U + IMAP_BUFFERS) + #else + /* Two parent directories all the way down. Source inode buffer. One + inode buffer for cyclic rename detection. Imap. + */ + #define MINIMUM_BUFFER_COUNT (INODE_BUFFERS + INODE_BUFFERS + 2U + IMAP_BUFFERS) + #endif + #else + /* Link/create: Needs a parent inode all the way down, an extra inode + buffer, and an imap buffer. + + Unlink is the same, since the parent inode buffers are released before + the inode is deleted. + */ + #define MINIMUM_BUFFER_COUNT (INODE_BUFFERS + 1U + IMAP_BUFFERS) + #endif +#endif + +#if REDCONF_BUFFER_COUNT < MINIMUM_BUFFER_COUNT +#error "REDCONF_BUFFER_COUNT is too low for the configuration" +#endif + + +/* A note on the typecasts in the below macros: Operands to bitwise operators + are subject to the "usual arithmetic conversions". This means that the + flags, which have uint16_t values, are promoted to int. MISRA-C:2012 R10.1 + forbids using signed integers in bitwise operations, so we cast to uint32_t + to avoid the integer promotion, then back to uint16_t to reflect the actual + type. +*/ +#define BFLAG_META_MASK (uint16_t)((uint32_t)BFLAG_META_MASTER | BFLAG_META_IMAP | BFLAG_META_INODE | BFLAG_META_INDIR | BFLAG_META_DINDIR) +#define BFLAG_MASK (uint16_t)((uint32_t)BFLAG_DIRTY | BFLAG_NEW | BFLAG_META_MASK) + + +/* An invalid block number. Used to indicate buffers which are not currently + in use. +*/ +#define BBLK_INVALID UINT32_MAX + + +/** @brief Metadata stored for each block buffer. + + To make better use of CPU caching when searching the BUFFERHEAD array, this + structure should be kept small. +*/ +typedef struct +{ + uint32_t ulBlock; /**< Block number the buffer is associated with; BBLK_INVALID if unused. */ + uint8_t bVolNum; /**< Volume the block resides on. */ + uint8_t bRefCount; /**< Number of references. */ + uint16_t uFlags; /**< Buffer flags: mask of BFLAG_* values. */ +} BUFFERHEAD; + + +/** @brief State information for the block buffer module. +*/ +typedef struct +{ + /** Number of buffers which are referenced (have a bRefCount > 0). + */ + uint16_t uNumUsed; + + /** MRU array. Each element of the array stores a buffer index; each buffer + index appears in the array once and only once. The first element of the + array is the most-recently-used (MRU) buffer, followed by the next most + recently used, and so on, till the last element, which is the least- + recently-used (LRU) buffer. + */ + uint8_t abMRU[REDCONF_BUFFER_COUNT]; + + /** Buffer heads, storing metadata for each buffer. + */ + BUFFERHEAD aHead[REDCONF_BUFFER_COUNT]; + + /** Array of memory for the block buffers themselves. + + Force 64-bit alignment of the aabBuffer array to ensure that it is safe + to cast buffer pointers to node structure pointers. + */ + ALIGNED_2D_BYTE_ARRAY(b, aabBuffer, REDCONF_BUFFER_COUNT, REDCONF_BLOCK_SIZE); +} BUFFERCTX; + + +static bool BufferIsValid(const uint8_t *pbBuffer, uint16_t uFlags); +static bool BufferToIdx(const void *pBuffer, uint8_t *pbIdx); +#if REDCONF_READ_ONLY == 0 +static REDSTATUS BufferWrite(uint8_t bIdx); +static REDSTATUS BufferFinalize(uint8_t *pbBuffer, uint16_t uFlags); +#endif +static void BufferMakeLRU(uint8_t bIdx); +static void BufferMakeMRU(uint8_t bIdx); +static bool BufferFind(uint32_t ulBlock, uint8_t *pbIdx); + +#ifdef REDCONF_ENDIAN_SWAP +static void BufferEndianSwap(const void *pBuffer, uint16_t uFlags); +static void BufferEndianSwapHeader(NODEHEADER *pHeader); +static void BufferEndianSwapMaster(MASTERBLOCK *pMaster); +static void BufferEndianSwapMetaRoot(METAROOT *pMetaRoot); +static void BufferEndianSwapInode(INODE *pInode); +static void BufferEndianSwapIndir(INDIR *pIndir); +#endif + + +static BUFFERCTX gBufCtx; + + +/** @brief Initialize the buffers. +*/ +void RedBufferInit(void) +{ + uint8_t bIdx; + + RedMemSet(&gBufCtx, 0U, sizeof(gBufCtx)); + + for(bIdx = 0U; bIdx < REDCONF_BUFFER_COUNT; bIdx++) + { + /* When the buffers have been freshly initialized, acquire the buffers + in the order in which they appear in the array. + */ + gBufCtx.abMRU[bIdx] = (uint8_t)((REDCONF_BUFFER_COUNT - bIdx) - 1U); + gBufCtx.aHead[bIdx].ulBlock = BBLK_INVALID; + } +} + + +/** @brief Acquire a buffer. + + @param ulBlock Block number to acquire. + @param uFlags BFLAG_ values for the operation. + @param ppBuffer On success, populated with the acquired buffer. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EINVAL Invalid parameters. + @retval -RED_EBUSY All buffers are referenced. +*/ +REDSTATUS RedBufferGet( + uint32_t ulBlock, + uint16_t uFlags, + void **ppBuffer) +{ + REDSTATUS ret = 0; + uint8_t bIdx; + + if((ulBlock >= gpRedVolume->ulBlockCount) || ((uFlags & BFLAG_MASK) != uFlags) || (ppBuffer == NULL)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + if(BufferFind(ulBlock, &bIdx)) + { + /* Error if the buffer exists and BFLAG_NEW was specified, since + the new flag is used when a block is newly allocated/created, so + the block was previously free and and there should never be an + existing buffer for a free block. + + Error if the buffer exists but does not have the same type as + was requested. + */ + if( ((uFlags & BFLAG_NEW) != 0U) + || ((uFlags & BFLAG_META_MASK) != (gBufCtx.aHead[bIdx].uFlags & BFLAG_META_MASK))) + { + CRITICAL_ERROR(); + ret = -RED_EFUBAR; + } + } + else if(gBufCtx.uNumUsed == REDCONF_BUFFER_COUNT) + { + /* The MINIMUM_BUFFER_COUNT is supposed to ensure that no operation + ever runs out of buffers, so this should never happen. + */ + CRITICAL_ERROR(); + ret = -RED_EBUSY; + } + else + { + BUFFERHEAD *pHead; + + /* Search for the least recently used buffer which is not + referenced. + */ + for(bIdx = (uint8_t)(REDCONF_BUFFER_COUNT - 1U); bIdx > 0U; bIdx--) + { + if(gBufCtx.aHead[gBufCtx.abMRU[bIdx]].bRefCount == 0U) + { + break; + } + } + + bIdx = gBufCtx.abMRU[bIdx]; + pHead = &gBufCtx.aHead[bIdx]; + + if(pHead->bRefCount == 0U) + { + /* If the LRU buffer is valid and dirty, write it out before + repurposing it. + */ + if(((pHead->uFlags & BFLAG_DIRTY) != 0U) && (pHead->ulBlock != BBLK_INVALID)) + { + #if REDCONF_READ_ONLY == 1 + CRITICAL_ERROR(); + ret = -RED_EFUBAR; + #else + ret = BufferWrite(bIdx); + #endif + } + } + else + { + /* All the buffers are used, which should have been caught by + checking gBufCtx.uNumUsed. + */ + CRITICAL_ERROR(); + ret = -RED_EBUSY; + } + + if(ret == 0) + { + if((uFlags & BFLAG_NEW) == 0U) + { + /* Invalidate the LRU buffer. If the read fails, we do not + want the buffer head to continue to refer to the old + block number, since the read, even if it fails, may have + partially overwritten the buffer data (consider the case + where block size exceeds sector size, and some but not + all of the sectors are read successfully), and if the + buffer were to be used subsequently with its partially + erroneous contents, bad things could happen. + */ + pHead->ulBlock = BBLK_INVALID; + + ret = RedIoRead(gbRedVolNum, ulBlock, 1U, gBufCtx.b.aabBuffer[bIdx]); + + if((ret == 0) && ((uFlags & BFLAG_META) != 0U)) + { + if(!BufferIsValid(gBufCtx.b.aabBuffer[bIdx], uFlags)) + { + /* A corrupt metadata node is usually a critical + error. The master block is an exception since + it might be invalid because the volume is not + mounted; that condition is expected and should + not result in an assertion. + */ + CRITICAL_ASSERT((uFlags & BFLAG_META_MASTER) == BFLAG_META_MASTER); + ret = -RED_EIO; + } + } + + #ifdef REDCONF_ENDIAN_SWAP + if(ret == 0) + { + BufferEndianSwap(gBufCtx.b.aabBuffer[bIdx], uFlags); + } + #endif + } + else + { + RedMemSet(gBufCtx.b.aabBuffer[bIdx], 0U, REDCONF_BLOCK_SIZE); + } + } + + if(ret == 0) + { + pHead->bVolNum = gbRedVolNum; + pHead->ulBlock = ulBlock; + pHead->uFlags = 0U; + } + } + + /* Reference the buffer, update its flags, and promote it to MRU. This + happens both when BufferFind() found an existing buffer for the + block and when the LRU buffer was repurposed to create a buffer for + the block. + */ + if(ret == 0) + { + BUFFERHEAD *pHead = &gBufCtx.aHead[bIdx]; + + pHead->bRefCount++; + + if(pHead->bRefCount == 1U) + { + gBufCtx.uNumUsed++; + } + + /* BFLAG_NEW tells this function to zero the buffer instead of + reading it from disk; it has no meaning later on, and thus is + not saved. + */ + pHead->uFlags |= (uFlags & (~BFLAG_NEW)); + + BufferMakeMRU(bIdx); + + *ppBuffer = gBufCtx.b.aabBuffer[bIdx]; + } + } + + return ret; +} + + +/** @brief Release a buffer. + + @param pBuffer The buffer to release. + */ +void RedBufferPut( + const void *pBuffer) +{ + uint8_t bIdx; + + if(!BufferToIdx(pBuffer, &bIdx)) + { + REDERROR(); + } + else + { + REDASSERT(gBufCtx.aHead[bIdx].bRefCount > 0U); + gBufCtx.aHead[bIdx].bRefCount--; + + if(gBufCtx.aHead[bIdx].bRefCount == 0U) + { + REDASSERT(gBufCtx.uNumUsed > 0U); + gBufCtx.uNumUsed--; + } + } +} + + +#if REDCONF_READ_ONLY == 0 +/** @brief Flush all buffers for the active volume in the given range of blocks. + + @param ulBlockStart Starting block number to flush. + @param ulBlockCount Count of blocks, starting at @p ulBlockStart, to flush. + Must not be zero. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EINVAL Invalid parameters. +*/ +REDSTATUS RedBufferFlush( + uint32_t ulBlockStart, + uint32_t ulBlockCount) +{ + REDSTATUS ret = 0; + + if( (ulBlockStart >= gpRedVolume->ulBlockCount) + || ((gpRedVolume->ulBlockCount - ulBlockStart) < ulBlockCount) + || (ulBlockCount == 0U)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + uint8_t bIdx; + + for(bIdx = 0U; bIdx < REDCONF_BUFFER_COUNT; bIdx++) + { + BUFFERHEAD *pHead = &gBufCtx.aHead[bIdx]; + + if( (pHead->bVolNum == gbRedVolNum) + && (pHead->ulBlock != BBLK_INVALID) + && ((pHead->uFlags & BFLAG_DIRTY) != 0U) + && (pHead->ulBlock >= ulBlockStart) + && (pHead->ulBlock < (ulBlockStart + ulBlockCount))) + { + ret = BufferWrite(bIdx); + + if(ret == 0) + { + pHead->uFlags &= (~BFLAG_DIRTY); + } + else + { + break; + } + } + } + } + + return ret; +} + + +/** @brief Mark a buffer dirty + + @param pBuffer The buffer to mark dirty. +*/ +void RedBufferDirty( + const void *pBuffer) +{ + uint8_t bIdx; + + if(!BufferToIdx(pBuffer, &bIdx)) + { + REDERROR(); + } + else + { + REDASSERT(gBufCtx.aHead[bIdx].bRefCount > 0U); + + gBufCtx.aHead[bIdx].uFlags |= BFLAG_DIRTY; + } +} + + +/** @brief Branch a buffer, marking it dirty and assigning a new block number. + + @param pBuffer The buffer to branch. + @param ulBlockNew The new block number for the buffer. +*/ +void RedBufferBranch( + const void *pBuffer, + uint32_t ulBlockNew) +{ + uint8_t bIdx; + + if( !BufferToIdx(pBuffer, &bIdx) + || (ulBlockNew >= gpRedVolume->ulBlockCount)) + { + REDERROR(); + } + else + { + BUFFERHEAD *pHead = &gBufCtx.aHead[bIdx]; + + REDASSERT(pHead->bRefCount > 0U); + REDASSERT((pHead->uFlags & BFLAG_DIRTY) == 0U); + + pHead->uFlags |= BFLAG_DIRTY; + pHead->ulBlock = ulBlockNew; + } +} + + +#if (REDCONF_API_POSIX == 1) || FORMAT_SUPPORTED +/** @brief Discard a buffer, releasing it and marking it invalid. + + @param pBuffer The buffer to discard. +*/ +void RedBufferDiscard( + const void *pBuffer) +{ + uint8_t bIdx; + + if(!BufferToIdx(pBuffer, &bIdx)) + { + REDERROR(); + } + else + { + REDASSERT(gBufCtx.aHead[bIdx].bRefCount == 1U); + REDASSERT(gBufCtx.uNumUsed > 0U); + + gBufCtx.aHead[bIdx].bRefCount = 0U; + gBufCtx.aHead[bIdx].ulBlock = BBLK_INVALID; + + gBufCtx.uNumUsed--; + + BufferMakeLRU(bIdx); + } +} +#endif +#endif /* REDCONF_READ_ONLY == 0 */ + + +/** @brief Discard a range of buffers, marking them invalid. + + @param ulBlockStart The starting block number to discard + @param ulBlockCount The number of blocks, starting at @p ulBlockStart, to + discard. Must not be zero. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL Invalid parameters. + @retval -RED_EBUSY A block in the desired range is referenced. +*/ +REDSTATUS RedBufferDiscardRange( + uint32_t ulBlockStart, + uint32_t ulBlockCount) +{ + REDSTATUS ret = 0; + + if( (ulBlockStart >= gpRedVolume->ulBlockCount) + || ((gpRedVolume->ulBlockCount - ulBlockStart) < ulBlockCount) + || (ulBlockCount == 0U)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + uint8_t bIdx; + + for(bIdx = 0U; bIdx < REDCONF_BUFFER_COUNT; bIdx++) + { + BUFFERHEAD *pHead = &gBufCtx.aHead[bIdx]; + + if( (pHead->bVolNum == gbRedVolNum) + && (pHead->ulBlock != BBLK_INVALID) + && (pHead->ulBlock >= ulBlockStart) + && (pHead->ulBlock < (ulBlockStart + ulBlockCount))) + { + if(pHead->bRefCount == 0U) + { + pHead->ulBlock = BBLK_INVALID; + + BufferMakeLRU(bIdx); + } + else + { + /* This should never happen. There are three general cases + when this function is used: + + 1) Discarding every block, as happens during unmount + and at the end of format. There should no longer be + any referenced buffers at those points. + 2) Discarding a block which has become free. All + buffers for such blocks should be put or branched + beforehand. + 3) Discarding of blocks that were just written straight + to disk, leaving stale data in the buffer. The write + code should never reference buffers for these blocks, + since they would not be needed or used. + */ + CRITICAL_ERROR(); + ret = -RED_EBUSY; + break; + } + } + } + } + + return ret; +} + + +/** Determine whether a metadata buffer is valid. + + This includes checking its signature, CRC, and sequence number. + + @param pbBuffer Pointer to the metadata buffer to validate. + @param uFlags The buffer flags provided by the caller. Used to determine + the expected signature. + + @return Whether the metadata buffer is valid. + + @retval true The metadata buffer is valid. + @retval false The metadata buffer is invalid. +*/ +static bool BufferIsValid( + const uint8_t *pbBuffer, + uint16_t uFlags) +{ + bool fValid; + + if((pbBuffer == NULL) || ((uFlags & BFLAG_MASK) != uFlags)) + { + REDERROR(); + fValid = false; + } + else + { + NODEHEADER buf; + uint16_t uMetaFlags = uFlags & BFLAG_META_MASK; + + /* Casting pbBuffer to (NODEHEADER *) would run afoul MISRA-C:2012 + R11.3, so instead copy the fields out. + */ + RedMemCpy(&buf.ulSignature, &pbBuffer[NODEHEADER_OFFSET_SIG], sizeof(buf.ulSignature)); + RedMemCpy(&buf.ulCRC, &pbBuffer[NODEHEADER_OFFSET_CRC], sizeof(buf.ulCRC)); + RedMemCpy(&buf.ullSequence, &pbBuffer[NODEHEADER_OFFSET_SEQ], sizeof(buf.ullSequence)); + + #ifdef REDCONF_ENDIAN_SWAP + buf.ulCRC = RedRev32(buf.ulCRC); + buf.ulSignature = RedRev32(buf.ulSignature); + buf.ullSequence = RedRev64(buf.ullSequence); + #endif + + /* Make sure the signature is correct for the type of metadata block + requested by the caller. + */ + switch(buf.ulSignature) + { + case META_SIG_MASTER: + fValid = (uMetaFlags == BFLAG_META_MASTER); + break; + #if REDCONF_IMAP_EXTERNAL == 1 + case META_SIG_IMAP: + fValid = (uMetaFlags == BFLAG_META_IMAP); + break; + #endif + case META_SIG_INODE: + fValid = (uMetaFlags == BFLAG_META_INODE); + break; + #if DINDIR_POINTERS > 0U + case META_SIG_DINDIR: + fValid = (uMetaFlags == BFLAG_META_DINDIR); + break; + #endif + #if REDCONF_DIRECT_POINTERS < INODE_ENTRIES + case META_SIG_INDIR: + fValid = (uMetaFlags == BFLAG_META_INDIR); + break; + #endif + default: + fValid = false; + break; + } + + if(fValid) + { + uint32_t ulComputedCrc; + + /* Check for disk corruption by comparing the stored CRC with one + computed from the data. + + Also check the sequence number: if it is greater than the + current sequence number, the block is from a previous format + or the disk is writing blocks out of order. During mount, + before the metaroots have been read, the sequence number will + be unknown, and the check is skipped. + */ + ulComputedCrc = RedCrcNode(pbBuffer); + if(buf.ulCRC != ulComputedCrc) + { + fValid = false; + } + else if(gpRedVolume->fMounted && (buf.ullSequence >= gpRedVolume->ullSequence)) + { + fValid = false; + } + else + { + /* Buffer is valid. No action, fValid is already true. + */ + } + } + } + + return fValid; +} + + +/** @brief Derive the index of the buffer. + + @param pBuffer The buffer to derive the index of. + @param pbIdx On success, populated with the index of the buffer. + + @return Boolean indicating result. + + @retval true Success. + @retval false Failure. @p pBuffer is not a valid buffer pointer. +*/ +static bool BufferToIdx( + const void *pBuffer, + uint8_t *pbIdx) +{ + bool fRet = false; + + if((pBuffer != NULL) && (pbIdx != NULL)) + { + uint8_t bIdx; + + /* pBuffer should be a pointer to one of the block buffers. + + A good compiler should optimize this loop into a bounds check and an + alignment check, although GCC has been observed to not do so; if the + number of buffers is small, it should not make much difference. The + alternative is to use pointer comparisons, but this both deviates + from MISRA-C:2012 and involves undefined behavior. + */ + for(bIdx = 0U; bIdx < REDCONF_BUFFER_COUNT; bIdx++) + { + if(pBuffer == &gBufCtx.b.aabBuffer[bIdx][0U]) + { + break; + } + } + + if( (bIdx < REDCONF_BUFFER_COUNT) + && (gBufCtx.aHead[bIdx].ulBlock != BBLK_INVALID) + && (gBufCtx.aHead[bIdx].bVolNum == gbRedVolNum)) + { + *pbIdx = bIdx; + fRet = true; + } + } + + return fRet; +} + + +#if REDCONF_READ_ONLY == 0 +/** @brief Write out a dirty buffer. + + @param bIdx The index of the buffer to write. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EINVAL Invalid parameters. +*/ +static REDSTATUS BufferWrite( + uint8_t bIdx) +{ + REDSTATUS ret = 0; + + if(bIdx < REDCONF_BUFFER_COUNT) + { + const BUFFERHEAD *pHead = &gBufCtx.aHead[bIdx]; + + REDASSERT((pHead->uFlags & BFLAG_DIRTY) != 0U); + + if((pHead->uFlags & BFLAG_META) != 0U) + { + ret = BufferFinalize(gBufCtx.b.aabBuffer[bIdx], pHead->uFlags); + } + + if(ret == 0) + { + ret = RedIoWrite(pHead->bVolNum, pHead->ulBlock, 1U, gBufCtx.b.aabBuffer[bIdx]); + + #ifdef REDCONF_ENDIAN_SWAP + BufferEndianSwap(gBufCtx.b.aabBuffer[bIdx], pHead->uFlags); + #endif + } + } + else + { + REDERROR(); + ret = -RED_EINVAL; + } + + return ret; +} + + +/** @brief Finalize a metadata buffer. + + This updates the CRC and the sequence number. It also sets the signature, + though this is only truly needed if the buffer is new. + + @param pbBuffer Pointer to the metadata buffer to finalize. + @param uFlags The associated buffer flags. Used to determine the expected + signature. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL Invalid parameter; or maximum sequence number reached. +*/ +static REDSTATUS BufferFinalize( + uint8_t *pbBuffer, + uint16_t uFlags) +{ + REDSTATUS ret = 0; + + if((pbBuffer == NULL) || ((uFlags & BFLAG_MASK) != uFlags)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + uint32_t ulSignature; + + switch(uFlags & BFLAG_META_MASK) + { + case BFLAG_META_MASTER: + ulSignature = META_SIG_MASTER; + break; + #if REDCONF_IMAP_EXTERNAL == 1 + case BFLAG_META_IMAP: + ulSignature = META_SIG_IMAP; + break; + #endif + case BFLAG_META_INODE: + ulSignature = META_SIG_INODE; + break; + #if DINDIR_POINTERS > 0U + case BFLAG_META_DINDIR: + ulSignature = META_SIG_DINDIR; + break; + #endif + #if REDCONF_DIRECT_POINTERS < INODE_ENTRIES + case BFLAG_META_INDIR: + ulSignature = META_SIG_INDIR; + break; + #endif + default: + ulSignature = 0U; + break; + } + + if(ulSignature == 0U) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + uint64_t ullSeqNum = gpRedVolume->ullSequence; + + ret = RedVolSeqNumIncrement(); + if(ret == 0) + { + uint32_t ulCrc; + + RedMemCpy(&pbBuffer[NODEHEADER_OFFSET_SIG], &ulSignature, sizeof(ulSignature)); + RedMemCpy(&pbBuffer[NODEHEADER_OFFSET_SEQ], &ullSeqNum, sizeof(ullSeqNum)); + + #ifdef REDCONF_ENDIAN_SWAP + BufferEndianSwap(pbBuffer, uFlags); + #endif + + ulCrc = RedCrcNode(pbBuffer); + #ifdef REDCONF_ENDIAN_SWAP + ulCrc = RedRev32(ulCrc); + #endif + RedMemCpy(&pbBuffer[NODEHEADER_OFFSET_CRC], &ulCrc, sizeof(ulCrc)); + } + } + } + + return ret; +} +#endif /* REDCONF_READ_ONLY == 0 */ + + +#ifdef REDCONF_ENDIAN_SWAP +/** @brief Swap the byte order of a metadata buffer + + Does nothing if the buffer is not a metadata node. Also does nothing for + meta roots, which don't go through the buffers anyways. + + @param pBuffer Pointer to the metadata buffer to swap + @param uFlags The associated buffer flags. Used to determin the type of + metadata node. +*/ +static void BufferEndianSwap( + void *pBuffer, + uint16_t uFlags) +{ + if((pBuffer == NULL) || ((uFlags & BFLAG_MASK) != uFlags)) + { + REDERROR(); + } + else if((uFlags & BFLAG_META_MASK) != 0) + { + BufferEndianSwapHeader(pBuffer); + + switch(uFlags & BFLAG_META_MASK) + { + case BFLAG_META_MASTER: + BufferEndianSwapMaster(pBuffer); + break; + case BFLAG_META_INODE: + BufferEndianSwapInode(pBuffer); + break; + #if DINDIR_POINTERS > 0U + case BFLAG_META_DINDIR: + BufferEndianSwapIndir(pBuffer); + break; + #endif + #if REDCONF_DIRECT_POINTERS < INODE_ENTRIES + case BFLAG_META_INDIR: + BufferEndianSwapIndir(pBuffer); + break; + #endif + default: + break; + } + } + else + { + /* File data buffers do not need to be swapped. + */ + } +} + + +/** @brief Swap the byte order of a metadata node header + + @param pHeader Pointer to the metadata node header to swap +*/ +static void BufferEndianSwapHeader( + NODEHEADER *pHeader) +{ + if(pHeader == NULL) + { + REDERROR(); + } + else + { + pHeader->ulSignature = RedRev32(pHeader->ulSignature); + pHeader->ulCRC = RedRev32(pHeader->ulCRC); + pHeader->ullSequence = RedRev64(pHeader->ullSequence); + } +} + + +/** @brief Swap the byte order of a master block + + @param pMaster Pointer to the master block to swap +*/ +static void BufferEndianSwapMaster( + MASTERBLOCK *pMaster) +{ + if(pMaster == NULL) + { + REDERROR(); + } + else + { + pMaster->ulVersion = RedRev32(pMaster->ulVersion); + pMaster->ulFormatTime = RedRev32(pMaster->ulFormatTime); + pMaster->ulInodeCount = RedRev32(pMaster->ulInodeCount); + pMaster->ulBlockCount = RedRev32(pMaster->ulBlockCount); + pMaster->uMaxNameLen = RedRev16(pMaster->uMaxNameLen); + pMaster->uDirectPointers = RedRev16(pMaster->uDirectPointers); + pMaster->uIndirectPointers = RedRev16(pMaster->uIndirectPointers); + } +} + + +/** @brief Swap the byte order of an inode + + @param pInode Pointer to the inode to swap +*/ +static void BufferEndianSwapInode( + INODE *pInode) +{ + if(pInode == NULL) + { + REDERROR(); + } + else + { + uint32_t ulIdx; + + pInode->ullSize = RedRev64(pInode->ullSize); + + #if REDCONF_INODE_BLOCKS == 1 + pInode->ulBlocks = RedRev32(pInode->ulBlocks); + #endif + + #if REDCONF_INODE_TIMESTAMPS == 1 + pInode->ulATime = RedRev32(pInode->ulATime); + pInode->ulMTime = RedRev32(pInode->ulMTime); + pInode->ulCTime = RedRev32(pInode->ulCTime); + #endif + + pInode->uMode = RedRev16(pInode->uMode); + + #if (REDCONF_API_POSIX == 1) && (REDCONF_API_POSIX_LINK == 1) + pInode->uNLink = RedRev16(pInode->uNLink); + #endif + + #if REDCONF_API_POSIX == 1 + pInode->ulPInode = RedRev32(pInode->ulPInode); + #endif + + for(ulIdx = 0; ulIdx < INODE_ENTRIES; ulIdx++) + { + pInode->aulEntries[ulIdx] = RedRev32(pInode->aulEntries[ulIdx]); + } + } +} + + +#if REDCONF_DIRECT_POINTERS < INODE_ENTRIES +/** @brief Swap the byte order of an indirect or double indirect node + + @param pIndir Pointer to the node to swap +*/ +static void BufferEndianSwapIndir( + INDIR *pIndir) +{ + if(pIndir == NULL) + { + REDERROR(); + } + else + { + uint32_t ulIdx; + + pIndir->ulInode = RedRev32(pIndir->ulInode); + + for(ulIdx = 0; ulIdx < INDIR_ENTRIES; ulIdx++) + { + pIndir->aulEntries[ulIdx] = RedRev32(pIndir->aulEntries[ulIdx]); + } + } +} + +#endif /* REDCONF_DIRECT_POINTERS < INODE_ENTRIES */ +#endif /* #ifdef REDCONF_ENDIAN_SWAP */ + + +/** @brief Mark a buffer as least recently used. + + @param bIdx The index of the buffer to make LRU. +*/ +static void BufferMakeLRU( + uint8_t bIdx) +{ + if(bIdx >= REDCONF_BUFFER_COUNT) + { + REDERROR(); + } + else if(bIdx != gBufCtx.abMRU[REDCONF_BUFFER_COUNT - 1U]) + { + uint8_t bMruIdx; + + /* Find the current position of the buffer in the MRU array. We do not + need to check the last slot, since we already know from the above + check that the index is not there. + */ + for(bMruIdx = 0U; bMruIdx < (REDCONF_BUFFER_COUNT - 1U); bMruIdx++) + { + if(bIdx == gBufCtx.abMRU[bMruIdx]) + { + break; + } + } + + if(bMruIdx < (REDCONF_BUFFER_COUNT - 1U)) + { + /* Move the buffer index to the back of the MRU array, making it + the LRU buffer. + */ + RedMemMove(&gBufCtx.abMRU[bMruIdx], &gBufCtx.abMRU[bMruIdx + 1U], REDCONF_BUFFER_COUNT - ((uint32_t)bMruIdx + 1U)); + gBufCtx.abMRU[REDCONF_BUFFER_COUNT - 1U] = bIdx; + } + else + { + REDERROR(); + } + } + else + { + /* Buffer already LRU, nothing to do. + */ + } +} + + +/** @brief Mark a buffer as most recently used. + + @param bIdx The index of the buffer to make MRU. +*/ +static void BufferMakeMRU( + uint8_t bIdx) +{ + if(bIdx >= REDCONF_BUFFER_COUNT) + { + REDERROR(); + } + else if(bIdx != gBufCtx.abMRU[0U]) + { + uint8_t bMruIdx; + + /* Find the current position of the buffer in the MRU array. We do not + need to check the first slot, since we already know from the above + check that the index is not there. + */ + for(bMruIdx = 1U; bMruIdx < REDCONF_BUFFER_COUNT; bMruIdx++) + { + if(bIdx == gBufCtx.abMRU[bMruIdx]) + { + break; + } + } + + if(bMruIdx < REDCONF_BUFFER_COUNT) + { + /* Move the buffer index to the front of the MRU array, making it + the MRU buffer. + */ + RedMemMove(&gBufCtx.abMRU[1U], &gBufCtx.abMRU[0U], bMruIdx); + gBufCtx.abMRU[0U] = bIdx; + } + else + { + REDERROR(); + } + } + else + { + /* Buffer already MRU, nothing to do. + */ + } +} + + +/** @brief Find a block in the buffers. + + @param ulBlock The block number to find. + @param pbIdx If the block is buffered (true is returned), populated with + the index of the buffer. + + @return Boolean indicating whether or not the block is buffered. + + @retval true @p ulBlock is buffered, and its index has been stored in + @p pbIdx. + @retval false @p ulBlock is not buffered. +*/ +static bool BufferFind( + uint32_t ulBlock, + uint8_t *pbIdx) +{ + bool ret = false; + + if((ulBlock >= gpRedVolume->ulBlockCount) || (pbIdx == NULL)) + { + REDERROR(); + } + else + { + uint8_t bIdx; + + for(bIdx = 0U; bIdx < REDCONF_BUFFER_COUNT; bIdx++) + { + const BUFFERHEAD *pHead = &gBufCtx.aHead[bIdx]; + + if((pHead->bVolNum == gbRedVolNum) && (pHead->ulBlock == ulBlock)) + { + *pbIdx = bIdx; + ret = true; + break; + } + } + } + + return ret; +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/core.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/core.c new file mode 100644 index 0000000..06c3a23 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/core.c @@ -0,0 +1,1921 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements the entry-points to the core file system. +*/ +#include +#include +#include + + +/* Minimum number of blocks needed for metadata on any volume: the master + block (1), the two metaroots (2), and one doubly-allocated inode (2), + resulting in 1 + 2 + 2 = 5. +*/ +#define MINIMUM_METADATA_BLOCKS (5U) + + +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) +static REDSTATUS CoreCreate(uint32_t ulPInode, const char *pszName, bool fDir, uint32_t *pulInode); +#endif +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) && (REDCONF_API_POSIX_LINK == 1) +static REDSTATUS CoreLink(uint32_t ulPInode, const char *pszName, uint32_t ulInode); +#endif +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) && ((REDCONF_API_POSIX_UNLINK == 1) || (REDCONF_API_POSIX_RMDIR == 1)) +static REDSTATUS CoreUnlink(uint32_t ulPInode, const char *pszName); +#endif +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) && (REDCONF_API_POSIX_RENAME == 1) +static REDSTATUS CoreRename(uint32_t ulSrcPInode, const char *pszSrcName, uint32_t ulDstPInode, const char *pszDstName); +#endif +#if REDCONF_READ_ONLY == 0 +static REDSTATUS CoreFileWrite(uint32_t ulInode, uint64_t ullStart, uint32_t *pulLen, const void *pBuffer); +#endif +#if TRUNCATE_SUPPORTED +static REDSTATUS CoreFileTruncate(uint32_t ulInode, uint64_t ullSize); +#endif + + +VOLUME gaRedVolume[REDCONF_VOLUME_COUNT]; +static COREVOLUME gaCoreVol[REDCONF_VOLUME_COUNT]; + +const VOLCONF * CONST_IF_ONE_VOLUME gpRedVolConf = &gaRedVolConf[0U]; +VOLUME * CONST_IF_ONE_VOLUME gpRedVolume = &gaRedVolume[0U]; +COREVOLUME * CONST_IF_ONE_VOLUME gpRedCoreVol = &gaCoreVol[0U]; +METAROOT *gpRedMR = &gaCoreVol[0U].aMR[0U]; + +CONST_IF_ONE_VOLUME uint8_t gbRedVolNum = 0; + + +/** @brief Initialize the Reliance Edge file system driver. + + Prepares the Reliance Edge file system driver to be used. Must be the first + Reliance Edge function to be invoked: no volumes can be mounted until the + driver has been initialized. + + If this function is called when the Reliance Edge driver is already + initialized, the behavior is undefined. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. +*/ +REDSTATUS RedCoreInit(void) +{ + REDSTATUS ret = 0; + uint8_t bVolNum; + #if REDCONF_OUTPUT == 1 + static uint8_t bSignedOn = 0U; /* Whether the sign on has been printed. */ + + if(bSignedOn == 0U) + { + RedSignOn(); + bSignedOn = 1U; + } + #else + /* Call RedSignOn() even when output is disabled, to force the copyright + text to be referenced and pulled into the program data. + */ + RedSignOn(); + #endif + + RedMemSet(gaRedVolume, 0U, sizeof(gaRedVolume)); + RedMemSet(gaCoreVol, 0U, sizeof(gaCoreVol)); + + RedBufferInit(); + + for(bVolNum = 0U; bVolNum < REDCONF_VOLUME_COUNT; bVolNum++) + { + VOLUME *pVol = &gaRedVolume[bVolNum]; + COREVOLUME *pCoreVol = &gaCoreVol[bVolNum]; + const VOLCONF *pVolConf = &gaRedVolConf[bVolNum]; + + if( (pVolConf->ulSectorSize < SECTOR_SIZE_MIN) + || ((REDCONF_BLOCK_SIZE % pVolConf->ulSectorSize) != 0U) + || (pVolConf->ulInodeCount == 0U)) + { + ret = -RED_EINVAL; + } + #if REDCONF_API_POSIX == 1 + else if(pVolConf->pszPathPrefix == NULL) + { + ret = -RED_EINVAL; + } + else + { + #if REDCONF_VOLUME_COUNT > 1U + uint8_t bCmpVol; + + /* Ensure there are no duplicate path prefixes. Check against all + previous volumes, which are already verified. + */ + for(bCmpVol = 0U; bCmpVol < bVolNum; bCmpVol++) + { + const char *pszCmpPathPrefix = gaRedVolConf[bCmpVol].pszPathPrefix; + + if(RedStrCmp(pVolConf->pszPathPrefix, pszCmpPathPrefix) == 0) + { + ret = -RED_EINVAL; + break; + } + } + #endif + } + #endif + + if(ret == 0) + { + pVol->bBlockSectorShift = 0U; + while((pVolConf->ulSectorSize << pVol->bBlockSectorShift) < REDCONF_BLOCK_SIZE) + { + pVol->bBlockSectorShift++; + } + + /* This should always be true since the block size is confirmed to + be a power of two (checked at compile time) and above we ensured + that (REDCONF_BLOCK_SIZE % pVolConf->ulSectorSize) == 0. + */ + REDASSERT((pVolConf->ulSectorSize << pVol->bBlockSectorShift) == REDCONF_BLOCK_SIZE); + + pVol->ulBlockCount = (uint32_t)(pVolConf->ullSectorCount >> pVol->bBlockSectorShift); + + if(pVol->ulBlockCount < MINIMUM_METADATA_BLOCKS) + { + ret = -RED_EINVAL; + } + else + { + #if REDCONF_READ_ONLY == 0 + pVol->ulTransMask = REDCONF_TRANSACT_DEFAULT; + #endif + + pVol->ullMaxInodeSize = INODE_SIZE_MAX; + + /* To understand the following code, note that the fixed- + location metadata is located at the start of the disk, in + the following order: + + - Master block (1 block) + - Metaroots (2 blocks) + - External imap blocks (variable * 2 blocks) + - Inode blocks (pVolConf->ulInodeCount * 2 blocks) + */ + + /* The imap needs bits for all inode and allocable blocks. If + that bitmap will fit into the metaroot, the inline imap is + used and there are no imap nodes on disk. The minus 3 is + there since the imap does not include bits for the master + block or metaroots. + */ + pCoreVol->fImapInline = (pVol->ulBlockCount - 3U) <= METAROOT_ENTRIES; + + if(pCoreVol->fImapInline) + { + #if REDCONF_IMAP_INLINE == 1 + pCoreVol->ulInodeTableStartBN = 3U; + #else + ret = -RED_EINVAL; + #endif + } + else + { + #if REDCONF_IMAP_EXTERNAL == 1 + pCoreVol->ulImapStartBN = 3U; + + /* The imap does not include bits for itself, so add two to + the number of imap entries for the two blocks of each + imap node. This allows us to divide up the remaining + space, making sure to round up so all data blocks are + covered. + */ + pCoreVol->ulImapNodeCount = + ((pVol->ulBlockCount - 3U) + ((IMAPNODE_ENTRIES + 2U) - 1U)) / (IMAPNODE_ENTRIES + 2U); + + pCoreVol->ulInodeTableStartBN = pCoreVol->ulImapStartBN + (pCoreVol->ulImapNodeCount * 2U); + #else + ret = -RED_EINVAL; + #endif + } + } + } + + if(ret == 0) + { + pCoreVol->ulFirstAllocableBN = pCoreVol->ulInodeTableStartBN + (pVolConf->ulInodeCount * 2U); + + if(pCoreVol->ulFirstAllocableBN > pVol->ulBlockCount) + { + /* We can get here if there is not enough space for the number + of configured inodes. + */ + ret = -RED_EINVAL; + } + else + { + pVol->ulBlocksAllocable = pVol->ulBlockCount - pCoreVol->ulFirstAllocableBN; + } + } + + if(ret != 0) + { + break; + } + } + + /* Make sure the configured endianness is correct. + */ + if(ret == 0) + { + uint16_t uValue = 0xFF00U; + uint8_t abBytes[2U]; + + RedMemCpy(abBytes, &uValue, sizeof(abBytes)); + + #if REDCONF_ENDIAN_BIG == 1 + if(abBytes[0U] != 0xFFU) + #else + if(abBytes[0U] != 0x00U) + #endif + { + ret = -RED_EINVAL; + } + } + + if(ret == 0) + { + ret = RedOsClockInit(); + + #if REDCONF_TASK_COUNT > 1U + if(ret == 0) + { + ret = RedOsMutexInit(); + + if(ret != 0) + { + (void)RedOsClockUninit(); + } + } + #endif + } + + return ret; +} + + +/** @brief Uninitialize the Reliance Edge file system driver. + + Tears down the Reliance Edge file system driver. Cannot be used until all + Reliance Edge volumes are unmounted. A subsequent call to RedCoreInit() + will initialize the driver again. + + The behavior of calling this function when the core is already uninitialized + is undefined. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBUSY At least one volume is still mounted. +*/ +REDSTATUS RedCoreUninit(void) +{ + REDSTATUS ret; + + #if REDCONF_TASK_COUNT > 1U + ret = RedOsMutexUninit(); + + if(ret == 0) + #endif + { + ret = RedOsClockUninit(); + } + + return ret; +} + + +/** @brief Set the current volume. + + All core APIs operate on the current volume. This call must precede all + core accesses. + + @param bVolNum The volume number to access. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p bVolNum is an invalid volume number. +*/ +REDSTATUS RedCoreVolSetCurrent( + uint8_t bVolNum) +{ + REDSTATUS ret; + + if(bVolNum >= REDCONF_VOLUME_COUNT) + { + ret = -RED_EINVAL; + } + else + { + #if REDCONF_VOLUME_COUNT > 1U + gbRedVolNum = bVolNum; + gpRedVolConf = &gaRedVolConf[bVolNum]; + gpRedVolume = &gaRedVolume[bVolNum]; + gpRedCoreVol = &gaCoreVol[bVolNum]; + gpRedMR = &gpRedCoreVol->aMR[gpRedCoreVol->bCurMR]; + #endif + + ret = 0; + } + + return ret; +} + + +#if FORMAT_SUPPORTED +/** @brief Format a file system volume. + + Uses the statically defined volume configuration. After calling this + function, the volume needs to be mounted -- see RedCoreVolMount(). + + An error is returned if the volume is mounted. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBUSY Volume is mounted. + @retval -RED_EIO A disk I/O error occurred. +*/ +REDSTATUS RedCoreVolFormat(void) +{ + return RedVolFormat(); +} +#endif /* FORMAT_SUPPORTED */ + + +/** @brief Mount a file system volume. + + Prepares the file system volume to be accessed. Mount will fail if the + volume has never been formatted, or if the on-disk format is inconsistent + with the compile-time configuration. + + If the volume is already mounted, the behavior is undefined. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO Volume not formatted, improperly formatted, or corrupt. +*/ +REDSTATUS RedCoreVolMount(void) +{ + return RedVolMount(); +} + + +/** @brief Unmount a file system volume. + + This function discards the in-memory state for the file system and marks it + as unmounted. Subsequent attempts to access the volume will fail until the + volume is mounted again. + + If unmount automatic transaction points are enabled, this function will + commit a transaction point prior to unmounting. If unmount automatic + transaction points are disabled, this function will unmount without + transacting, effectively discarding the working state. + + If the volume is already unmounted, the behavior is undefined. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO I/O error during unmount automatic transaction point. +*/ +REDSTATUS RedCoreVolUnmount(void) +{ + REDSTATUS ret = 0; + + #if REDCONF_READ_ONLY == 0 + if(!gpRedVolume->fReadOnly && ((gpRedVolume->ulTransMask & RED_TRANSACT_UMOUNT) != 0U)) + { + ret = RedVolTransact(); + } + #endif + + if(ret == 0) + { + ret = RedBufferDiscardRange(0U, gpRedVolume->ulBlockCount); + } + + if(ret == 0) + { + ret = RedOsBDevClose(gbRedVolNum); + } + + if(ret == 0) + { + gpRedVolume->fMounted = false; + } + + return ret; +} + + +#if REDCONF_READ_ONLY == 0 +/** @brief Commit a transaction point. + + Reliance Edge is a transactional file system. All modifications, of both + metadata and filedata, are initially working state. A transaction point + is a process whereby the working state atomically becomes the committed + state, replacing the previous committed state. Whenever Reliance Edge is + mounted, including after power loss, the state of the file system after + mount is the most recent committed state. Nothing from the committed + state is ever missing, and nothing from the working state is ever included. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL The volume is not mounted. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EROFS The file system volume is read-only. +*/ +REDSTATUS RedCoreVolTransact(void) +{ + REDSTATUS ret; + + if(!gpRedVolume->fMounted) + { + ret = -RED_EINVAL; + } + else if(gpRedVolume->fReadOnly) + { + ret = -RED_EROFS; + } + else + { + ret = RedVolTransact(); + } + + return ret; +} +#endif /* REDCONF_READ_ONLY == 0 */ + + +#if REDCONF_API_POSIX == 1 +/** @brief Query file system status information. + + @param pStatFS The buffer to populate with volume information. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval -RED_EINVAL Volume is not mounted; or @p pStatFS is `NULL`. +*/ +REDSTATUS RedCoreVolStat( + REDSTATFS *pStatFS) +{ + REDSTATUS ret; + + if((pStatFS == NULL) || (!gpRedVolume->fMounted)) + { + ret = -RED_EINVAL; + } + else + { + RedMemSet(pStatFS, 0U, sizeof(*pStatFS)); + + pStatFS->f_bsize = REDCONF_BLOCK_SIZE; + pStatFS->f_frsize = REDCONF_BLOCK_SIZE; + pStatFS->f_blocks = gpRedVolume->ulBlockCount; + #if RESERVED_BLOCKS > 0U + pStatFS->f_bfree = (gpRedMR->ulFreeBlocks > RESERVED_BLOCKS) ? (gpRedMR->ulFreeBlocks - RESERVED_BLOCKS) : 0U; + #else + pStatFS->f_bfree = gpRedMR->ulFreeBlocks; + #endif + pStatFS->f_bavail = pStatFS->f_bfree; + pStatFS->f_files = gpRedVolConf->ulInodeCount; + pStatFS->f_ffree = gpRedMR->ulFreeInodes; + pStatFS->f_favail = gpRedMR->ulFreeInodes; + + pStatFS->f_flag = RED_ST_NOSUID; + #if REDCONF_READ_ONLY == 0 + if(gpRedVolume->fReadOnly) + #endif + { + pStatFS->f_flag |= RED_ST_RDONLY; + } + + pStatFS->f_namemax = REDCONF_NAME_MAX; + pStatFS->f_maxfsize = INODE_SIZE_MAX; + pStatFS->f_dev = gbRedVolNum; + + ret = 0; + } + + return ret; +} +#endif /* REDCONF_API_POSIX == 1 */ + + +#if (REDCONF_READ_ONLY == 0) && ((REDCONF_API_POSIX == 1) || (REDCONF_API_FSE_TRANSMASKSET == 1)) +/** @brief Update the transaction mask. + + The following events are available when using the FSE API: + + - #RED_TRANSACT_UMOUNT + - #RED_TRANSACT_WRITE + - #RED_TRANSACT_TRUNCATE + - #RED_TRANSACT_VOLFULL + + The following events are available when using the POSIX-like API: + + - #RED_TRANSACT_UMOUNT + - #RED_TRANSACT_CREAT + - #RED_TRANSACT_UNLINK + - #RED_TRANSACT_MKDIR + - #RED_TRANSACT_RENAME + - #RED_TRANSACT_LINK + - #RED_TRANSACT_CLOSE + - #RED_TRANSACT_WRITE + - #RED_TRANSACT_FSYNC + - #RED_TRANSACT_TRUNCATE + - #RED_TRANSACT_VOLFULL + + The #RED_TRANSACT_MANUAL macro (by itself) may be used to disable all + automatic transaction events. The #RED_TRANSACT_MASK macro is a bitmask of + all transaction flags, excluding those representing excluded functionality. + + Attempting to enable events for excluded functionality will result in an + error. + + @param ulEventMask A bitwise-OR'd mask of automatic transaction events to + be set as the current transaction mode. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL The volume is not mounted; or @p ulEventMask contains + invalid bits. + @retval -RED_EROFS The file system volume is read-only. +*/ +REDSTATUS RedCoreTransMaskSet( + uint32_t ulEventMask) +{ + REDSTATUS ret; + + if(!gpRedVolume->fMounted || ((ulEventMask & RED_TRANSACT_MASK) != ulEventMask)) + { + ret = -RED_EINVAL; + } + else if(gpRedVolume->fReadOnly) + { + ret = -RED_EROFS; + } + else + { + gpRedVolume->ulTransMask = ulEventMask; + ret = 0; + } + + return ret; +} +#endif + + +#if (REDCONF_API_POSIX == 1) || (REDCONF_API_FSE_TRANSMASKGET == 1) +/** @brief Read the transaction mask. + + If the volume is read-only, the returned event mask is always zero. + + @param pulEventMask Populated with a bitwise-OR'd mask of automatic + transaction events which represent the current + transaction mode for the volume. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL The volume is not mounted; or @p pulEventMask is `NULL`. +*/ +REDSTATUS RedCoreTransMaskGet( + uint32_t *pulEventMask) +{ + REDSTATUS ret; + + if(!gpRedVolume->fMounted || (pulEventMask == NULL)) + { + ret = -RED_EINVAL; + } + else + { + #if REDCONF_READ_ONLY == 1 + *pulEventMask = 0U; + #else + *pulEventMask = gpRedVolume->ulTransMask; + #endif + ret = 0; + } + + return ret; +} +#endif + + +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) +/** @brief Create a file or directory. + + @param ulPInode The inode number of the parent directory. + @param pszName A null-terminated name for the new inode. + @param fDir Whether to create a directory (true) or file (false). + @param pulInode On successful return, populated with the inode number of the + new file or directory. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL The volume is not mounted; or @p pszName is not + a valid name; or @p pulInode is `NULL`. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EROFS The file system volume is read-only. + @retval -RED_ENOTDIR @p ulPInode is not a directory. + @retval -RED_EBADF @p ulPInode is not a valid inode. + @retval -RED_ENOSPC There is not enough space on the volume to + createthe new directory entry; or the directory + is full. + @retval -RED_ENFILE No available inode slots. + @retval -RED_ENAMETOOLONG @p pszName is too long. + @retval -RED_EEXIST @p pszName already exists in @p ulPInode. +*/ +REDSTATUS RedCoreCreate( + uint32_t ulPInode, + const char *pszName, + bool fDir, + uint32_t *pulInode) +{ + REDSTATUS ret; + + if(!gpRedVolume->fMounted) + { + ret = -RED_EINVAL; + } + else if(gpRedVolume->fReadOnly) + { + ret = -RED_EROFS; + } + else + { + ret = CoreCreate(ulPInode, pszName, fDir, pulInode); + + if( (ret == -RED_ENOSPC) + && ((gpRedVolume->ulTransMask & RED_TRANSACT_VOLFULL) != 0U) + && (gpRedCoreVol->ulAlmostFreeBlocks > 0U)) + { + ret = RedVolTransact(); + + if(ret == 0) + { + ret = CoreCreate(ulPInode, pszName, fDir, pulInode); + } + } + + if(ret == 0) + { + if(fDir && ((gpRedVolume->ulTransMask & RED_TRANSACT_MKDIR) != 0U)) + { + ret = RedVolTransact(); + } + else if(!fDir && ((gpRedVolume->ulTransMask & RED_TRANSACT_CREAT) != 0U)) + { + ret = RedVolTransact(); + } + else + { + /* No automatic transaction for this operation. + */ + } + } + } + + return ret; +} + + +/** @brief Create a file or directory. + + @param ulPInode The inode number of the parent directory. + @param pszName A null-terminated name for the new inode. + @param fDir Whether to create a directory (true) or file (false). + @param pulInode On successful return, populated with the inode number of the + new file or directory. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EROFS The file system volume is read-only. + @retval -RED_ENOTDIR @p ulPInode is not a directory. + @retval -RED_EBADF @p ulPInode is not a valid inode. + @retval -RED_ENOSPC There is not enough space on the volume to + create the new directory entry; or the directory + is full. + @retval -RED_ENFILE No available inode slots. + @retval -RED_ENAMETOOLONG @p pszName is too long. + @retval -RED_EEXIST @p pszName already exists in @p ulPInode. +*/ +static REDSTATUS CoreCreate( + uint32_t ulPInode, + const char *pszName, + bool fDir, + uint32_t *pulInode) +{ + REDSTATUS ret; + + if(pulInode == NULL) + { + ret = -RED_EINVAL; + } + else if(gpRedVolume->fReadOnly) + { + ret = -RED_EROFS; + } + else + { + CINODE pino; + + pino.ulInode = ulPInode; + ret = RedInodeMount(&pino, FTYPE_DIR, false); + + if(ret == 0) + { + CINODE ino; + + ino.ulInode = INODE_INVALID; + ret = RedInodeCreate(&ino, ulPInode, fDir ? RED_S_IFDIR : RED_S_IFREG); + + if(ret == 0) + { + ret = RedInodeBranch(&pino); + + if(ret == 0) + { + ret = RedDirEntryCreate(&pino, pszName, ino.ulInode); + } + + if(ret == 0) + { + *pulInode = ino.ulInode; + } + else + { + REDSTATUS ret2; + + ret2 = RedInodeFree(&ino); + CRITICAL_ASSERT(ret2 == 0); + } + + RedInodePut(&ino, 0U); + } + + RedInodePut(&pino, (ret == 0) ? (uint8_t)(IPUT_UPDATE_MTIME | IPUT_UPDATE_CTIME) : 0U); + } + } + + return ret; +} +#endif /* (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) */ + + +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) && (REDCONF_API_POSIX_LINK == 1) +/** @brief Create a hard link. + + This creates an additional name (link) for @p ulInode. The new name refers + to the same file with the same contents. If a name is deleted, but the + underlying file has other names, the file continues to exist. The link + count (accessible via RedCoreStat()) indicates the number of names that a + file has. All of a file's names are on equal footing: there is nothing + special about the original name. + + If @p ulInode names a directory, the operation will fail. + + @param ulPInode The inode number of the parent directory. + @param pszName The null-terminated name for the new link. + @param ulInode The inode to create a hard link to. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBADF @p ulPInode is not a valid inode; or @p ulInode + is not a valid inode. + @retval -RED_EEXIST @p pszName resolves to an existing file. + @retval -RED_EINVAL The volume is not mounted; or @p pszName is + `NULL`. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EMLINK Creating the link would exceed the maximum link + count of @p ulInode. + @retval -RED_ENAMETOOLONG Attempting to create a link with a name that + exceeds the maximum name length. + @retval -RED_ENOSPC There is insufficient free space to expand the + directory that would contain the link. + @retval -RED_ENOTDIR @p ulPInode is not a directory. + @retval -RED_EPERM @p ulInode is a directory. + @retval -RED_EROFS The requested link requires writing in a + directory on a read-only file system. +*/ +REDSTATUS RedCoreLink( + uint32_t ulPInode, + const char *pszName, + uint32_t ulInode) +{ + REDSTATUS ret; + + if(!gpRedVolume->fMounted) + { + ret = -RED_EINVAL; + } + else if(gpRedVolume->fReadOnly) + { + ret = -RED_EROFS; + } + else + { + ret = CoreLink(ulPInode, pszName, ulInode); + + if( (ret == -RED_ENOSPC) + && ((gpRedVolume->ulTransMask & RED_TRANSACT_VOLFULL) != 0U) + && (gpRedCoreVol->ulAlmostFreeBlocks > 0U)) + { + ret = RedVolTransact(); + + if(ret == 0) + { + ret = CoreLink(ulPInode, pszName, ulInode); + } + } + + if((ret == 0) && ((gpRedVolume->ulTransMask & RED_TRANSACT_LINK) != 0U)) + { + ret = RedVolTransact(); + } + } + + return ret; +} + + +/** @brief Create a hard link. + + @param ulPInode The inode number of the parent directory. + @param pszName The null-terminated name for the new link. + @param ulInode The inode to create a hard link to. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBADF @p ulPInode is not a valid inode; or @p ulInode + is not a valid inode. + @retval -RED_EEXIST @p pszName resolves to an existing file. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EMLINK Creating the link would exceed the maximum link + count of @p ulInode. + @retval -RED_ENAMETOOLONG Attempting to create a link with a name that + exceeds the maximum name length. + @retval -RED_ENOSPC There is insufficient free space to expand the + directory that would contain the link. + @retval -RED_ENOTDIR @p ulPInode is not a directory. + @retval -RED_EPERM @p ulInode is a directory. + @retval -RED_EROFS The requested link requires writing in a + directory on a read-only file system. +*/ +static REDSTATUS CoreLink( + uint32_t ulPInode, + const char *pszName, + uint32_t ulInode) +{ + REDSTATUS ret; + + if(gpRedVolume->fReadOnly) + { + ret = -RED_EROFS; + } + else + { + CINODE pino; + + pino.ulInode = ulPInode; + ret = RedInodeMount(&pino, FTYPE_DIR, false); + + if(ret == 0) + { + CINODE ino; + + ino.ulInode = ulInode; + ret = RedInodeMount(&ino, FTYPE_FILE, false); + + /* POSIX specifies EPERM as the errno thrown when link() is given a + directory. Switch the errno returned if EISDIR was the return + value. + */ + if(ret == -RED_EISDIR) + { + ret = -RED_EPERM; + } + + if(ret == 0) + { + if(ino.pInodeBuf->uNLink == UINT16_MAX) + { + ret = -RED_EMLINK; + } + else + { + ret = RedInodeBranch(&pino); + } + + if(ret == 0) + { + ret = RedInodeBranch(&ino); + } + + if(ret == 0) + { + ret = RedDirEntryCreate(&pino, pszName, ino.ulInode); + } + + if(ret == 0) + { + ino.pInodeBuf->uNLink++; + } + + RedInodePut(&ino, (ret == 0) ? IPUT_UPDATE_CTIME : 0U); + } + + RedInodePut(&pino, (ret == 0) ? (uint8_t)(IPUT_UPDATE_MTIME | IPUT_UPDATE_CTIME) : 0U); + } + } + + return ret; +} +#endif /* (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) && (REDCONF_API_POSIX_LINK == 1) */ + + +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) && ((REDCONF_API_POSIX_UNLINK == 1) || (REDCONF_API_POSIX_RMDIR == 1)) +/** @brief Delete a file or directory. + + The given name is deleted and the link count of the corresponding inode is + decremented. If the link count falls to zero (no remaining hard links), + the inode will be deleted. + + If the path names a directory which is not empty, the unlink will fail. + + If the deletion frees data in the committed state, it will not return to + free space until after a transaction point. Similarly, if the inode was + part of the committed state, the inode slot will not be available until + after a transaction point. + + This function can fail when the disk is full. To fix this, transact and + try again: Reliance Edge guarantees that it is possible to delete at least + one file or directory after a transaction point. If disk full automatic + transactions are enabled, this will happen automatically. + + @param ulPInode The inode number of the parent directory. + @param pszName The null-terminated name of the file or directory to + delete. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBADF @p ulPInode is not a valid inode. + @retval -RED_EINVAL The volume is not mounted; or @p pszName is + `NULL`. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENAMETOOLONG @p pszName is too long. + @retval -RED_ENOENT @p pszName does not name an existing file or + directory. + @retval -RED_ENOTDIR @p ulPInode is not a directory. + @retval -RED_ENOSPC The file system does not have enough space to + modify the parent directory to perform the + deletion. + @retval -RED_ENOTEMPTY The inode refered to by @p pszName is a + directory which is not empty. +*/ +REDSTATUS RedCoreUnlink( + uint32_t ulPInode, + const char *pszName) +{ + REDSTATUS ret; + + if(!gpRedVolume->fMounted) + { + ret = -RED_EINVAL; + } + else if(gpRedVolume->fReadOnly) + { + ret = -RED_EROFS; + } + else + { + ret = CoreUnlink(ulPInode, pszName); + + if( (ret == -RED_ENOSPC) + && ((gpRedVolume->ulTransMask & RED_TRANSACT_VOLFULL) != 0U) + && (gpRedCoreVol->ulAlmostFreeBlocks > 0U)) + { + ret = RedVolTransact(); + + if(ret == 0) + { + ret = CoreUnlink(ulPInode, pszName); + } + } + + if((ret == 0) && ((gpRedVolume->ulTransMask & RED_TRANSACT_UNLINK) != 0U)) + { + ret = RedVolTransact(); + } + } + + return ret; +} + + +/** @brief Delete a file or directory. + + @param ulPInode The inode number of the parent directory. + @param pszName The null-terminated name of the file or directory to + delete. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBADF @p ulPInode is not a valid inode. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENAMETOOLONG @p pszName is too long. + @retval -RED_ENOENT @p pszName does not name an existing file or + directory. + @retval -RED_ENOTDIR @p ulPInode is not a directory. + @retval -RED_ENOSPC The file system does not have enough space to + modify the parent directory to perform the + deletion. + @retval -RED_ENOTEMPTY The inode refered to by @p pszName is a + directory which is not empty. +*/ +static REDSTATUS CoreUnlink( + uint32_t ulPInode, + const char *pszName) +{ + REDSTATUS ret; + + if(gpRedVolume->fReadOnly) + { + ret = -RED_EROFS; + } + else + { + CINODE pino; + + pino.ulInode = ulPInode; + ret = RedInodeMount(&pino, FTYPE_DIR, false); + + if(ret == 0) + { + uint32_t ulDeleteIdx; + uint32_t ulInode; + + ret = RedDirEntryLookup(&pino, pszName, &ulDeleteIdx, &ulInode); + + if(ret == 0) + { + ret = RedInodeBranch(&pino); + } + + if(ret == 0) + { + CINODE ino; + + ino.ulInode = ulInode; + ret = RedInodeMount(&ino, FTYPE_EITHER, false); + + if(ret == 0) + { + if(ino.fDirectory && (ino.pInodeBuf->ullSize > 0U)) + { + ret = -RED_ENOTEMPTY; + } + else + { + #if RESERVED_BLOCKS > 0U + gpRedCoreVol->fUseReservedBlocks = true; + #endif + + ret = RedDirEntryDelete(&pino, ulDeleteIdx); + + #if RESERVED_BLOCKS > 0U + gpRedCoreVol->fUseReservedBlocks = false; + #endif + + if(ret == 0) + { + /* If the inode is deleted, buffers are needed to + read all of the indirects and free the data + blocks. Before doing that, to reduce the + minimum number of buffers needed to complete the + unlink, release the parent directory inode + buffers which are no longer needed. + */ + RedInodePutCoord(&pino); + + ret = RedInodeLinkDec(&ino); + CRITICAL_ASSERT(ret == 0); + } + } + + RedInodePut(&ino, (ret == 0) ? IPUT_UPDATE_CTIME : 0U); + } + } + + RedInodePut(&pino, (ret == 0) ? (uint8_t)(IPUT_UPDATE_MTIME | IPUT_UPDATE_CTIME) : 0U); + } + } + + return ret; +} +#endif /* (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) && ((REDCONF_API_POSIX_UNLINK == 1) || (REDCONF_API_POSIX_RMDIR == 1)) */ + + +#if REDCONF_API_POSIX == 1 +/** @brief Look up the inode number of a file or directory. + + @param ulPInode The inode number of the parent directory. + @param pszName The null-terminated name of the file or directory to look + up. + @param pulInode On successful return, populated with the inode number named + by @p pszName. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBADF @p ulPInode is not a valid inode. + @retval -RED_EINVAL The volume is not mounted; @p pszName is `NULL`; or + @p pulInode is `NULL`. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENOENT @p pszName does not name an existing file or directory. + @retval -RED_ENOTDIR @p ulPInode is not a directory. +*/ +REDSTATUS RedCoreLookup( + uint32_t ulPInode, + const char *pszName, + uint32_t *pulInode) +{ + REDSTATUS ret; + + if((pulInode == NULL) || !gpRedVolume->fMounted) + { + ret = -RED_EINVAL; + } + else + { + CINODE ino; + + ino.ulInode = ulPInode; + ret = RedInodeMount(&ino, FTYPE_DIR, false); + + if(ret == 0) + { + ret = RedDirEntryLookup(&ino, pszName, NULL, pulInode); + + RedInodePut(&ino, 0U); + } + } + + return ret; +} +#endif /* REDCONF_API_POSIX == 1 */ + + +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) && (REDCONF_API_POSIX_RENAME == 1) +/** @brief Rename a file or directory. + + If @p pszDstName names an existing file or directory, the behavior depends + on the configuration. If #REDCONF_RENAME_ATOMIC is false, and if the + destination name exists, this function always fails with -RED_EEXIST. + + If #REDCONF_RENAME_ATOMIC is true, and if the new name exists, then in one + atomic operation, the destination name is unlinked and the source name is + renamed to the destination name. Both names must be of the same type (both + files or both directories). As with RedCoreUnlink(), if the destination + name is a directory, it must be empty. The major exception to this + behavior is that if both names are links to the same inode, then the rename + does nothing and both names continue to exist. + + If the rename deletes the old destination, it may free data in the + committed state, which will not return to free space until after a + transaction point. Similarly, if the deleted inode was part of the + committed state, the inode slot will not be available until after a + transaction point. + + @param ulSrcPInode The inode number of the parent directory of the file or + directory to rename. + @param pszSrcName The name of the file or directory to rename. + @param ulDstPInode The new parent directory inode number of the file or + directory after the rename. + @param pszDstName The new name of the file or directory after the rename. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBADF @p ulSrcPInode is not a valid inode number; or + @p ulDstPInode is not a valid inode number. + @retval -RED_EEXIST #REDCONF_RENAME_POSIX is false and the + destination name exists. + @retval -RED_EINVAL The volume is not mounted; @p pszSrcName is + `NULL`; or @p pszDstName is `NULL`. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EISDIR The destination name exists and is a directory, + and the source name is a non-directory. + @retval -RED_ENAMETOOLONG Either @p pszSrcName or @p pszDstName is longer + than #REDCONF_NAME_MAX. + @retval -RED_ENOENT The source name is not an existing entry; or + either @p pszSrcName or @p pszDstName point to + an empty string. + @retval -RED_ENOTDIR @p ulSrcPInode is not a directory; or + @p ulDstPInode is not a directory; or the source + name is a directory and the destination name is + a file. + @retval -RED_ENOTEMPTY The destination name is a directory which is not + empty. + @retval -RED_ENOSPC The file system does not have enough space to + extend the @p ulDstPInode directory. + @retval -RED_EROFS The directory to be removed resides on a + read-only file system. +*/ +REDSTATUS RedCoreRename( + uint32_t ulSrcPInode, + const char *pszSrcName, + uint32_t ulDstPInode, + const char *pszDstName) +{ + REDSTATUS ret; + + if(!gpRedVolume->fMounted) + { + ret = -RED_EINVAL; + } + else if(gpRedVolume->fReadOnly) + { + ret = -RED_EROFS; + } + else + { + ret = CoreRename(ulSrcPInode, pszSrcName, ulDstPInode, pszDstName); + + if( (ret == -RED_ENOSPC) + && ((gpRedVolume->ulTransMask & RED_TRANSACT_VOLFULL) != 0U) + && (gpRedCoreVol->ulAlmostFreeBlocks > 0U)) + { + ret = RedVolTransact(); + + if(ret == 0) + { + ret = CoreRename(ulSrcPInode, pszSrcName, ulDstPInode, pszDstName); + } + } + + if((ret == 0) && ((gpRedVolume->ulTransMask & RED_TRANSACT_RENAME) != 0U)) + { + ret = RedVolTransact(); + } + } + + return ret; +} + + +/** @brief Rename a file or directory. + + @param ulSrcPInode The inode number of the parent directory of the file or + directory to rename. + @param pszSrcName The name of the file or directory to rename. + @param ulDstPInode The new parent directory inode number of the file or + directory after the rename. + @param pszDstName The new name of the file or directory after the rename. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBADF @p ulSrcPInode is not a valid inode number; or + @p ulDstPInode is not a valid inode number. + @retval -RED_EEXIST #REDCONF_RENAME_POSIX is false and the + destination name exists. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EISDIR The destination name exists and is a directory, + and the source name is a non-directory. + @retval -RED_ENAMETOOLONG Either @p pszSrcName or @p pszDstName is longer + than #REDCONF_NAME_MAX. + @retval -RED_ENOENT The source name is not an existing entry; or + either @p pszSrcName or @p pszDstName point to + an empty string. + @retval -RED_ENOTDIR @p ulSrcPInode is not a directory; or + @p ulDstPInode is not a directory; or the source + name is a directory and the destination name is + a file. + @retval -RED_ENOTEMPTY The destination name is a directory which is not + empty. + @retval -RED_ENOSPC The file system does not have enough space to + extend the @p ulDstPInode directory. + @retval -RED_EROFS The directory to be removed resides on a + read-only file system. +*/ +static REDSTATUS CoreRename( + uint32_t ulSrcPInode, + const char *pszSrcName, + uint32_t ulDstPInode, + const char *pszDstName) +{ + REDSTATUS ret; + + if(gpRedVolume->fReadOnly) + { + ret = -RED_EROFS; + } + else + { + bool fUpdateTimestamps = false; + CINODE SrcPInode; + + SrcPInode.ulInode = ulSrcPInode; + ret = RedInodeMount(&SrcPInode, FTYPE_DIR, true); + + if(ret == 0) + { + CINODE DstPInode; + CINODE *pDstPInode; + + if(ulSrcPInode == ulDstPInode) + { + pDstPInode = &SrcPInode; + } + else + { + pDstPInode = &DstPInode; + DstPInode.ulInode = ulDstPInode; + ret = RedInodeMount(pDstPInode, FTYPE_DIR, true); + } + + if(ret == 0) + { + /* Initialize these to zero so we can unconditionally put them, + even if RedDirEntryRename() fails before mounting them. + */ + CINODE SrcInode = {0U}; + CINODE DstInode = {0U}; + + ret = RedDirEntryRename(&SrcPInode, pszSrcName, &SrcInode, pDstPInode, pszDstName, &DstInode); + + #if REDCONF_RENAME_ATOMIC == 1 + if((ret == 0) && (DstInode.ulInode != INODE_INVALID) && (DstInode.ulInode != SrcInode.ulInode)) + { + /* If the inode is deleted, buffers are needed to read all + of the indirects and free the data blocks. Before doing + that, to reduce the minimum number of buffers needed to + complete the rename, release parent directory inode + buffers which are no longer needed. + */ + RedInodePutCoord(&SrcPInode); + RedInodePutCoord(pDstPInode); + + ret = RedInodeLinkDec(&DstInode); + CRITICAL_ASSERT(ret == 0); + } + + if((ret == 0) && (DstInode.ulInode != SrcInode.ulInode)) + #else + if(ret == 0) + #endif + { + fUpdateTimestamps = true; + } + + #if REDCONF_RENAME_ATOMIC == 1 + RedInodePut(&DstInode, 0U); + #endif + + /* POSIX says updating ctime for the source inode is optional, + but searching around it looks like this is common for Linux + and other Unix file systems. + */ + RedInodePut(&SrcInode, fUpdateTimestamps ? IPUT_UPDATE_CTIME : 0U); + RedInodePut(pDstPInode, fUpdateTimestamps ? (uint8_t)(IPUT_UPDATE_MTIME | IPUT_UPDATE_CTIME) : 0U); + } + } + + RedInodePut(&SrcPInode, fUpdateTimestamps ? (uint8_t)(IPUT_UPDATE_MTIME | IPUT_UPDATE_CTIME) : 0U); + } + + return ret; +} +#endif /* (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) && (REDCONF_API_POSIX_RENAME == 1) */ + + +#if REDCONF_API_POSIX == 1 +/** @brief Get the status of a file or directory. + + See the ::REDSTAT type for the details of the information returned. + + @param ulInode The inode number of the file or directory whose information + is to be retrieved. + @param pStat Pointer to a ::REDSTAT buffer to populate. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBADF @p ulInode is not a valid inode. + @retval -RED_EINVAL The volume is not mounted; @p pStat is `NULL`. + @retval -RED_EIO A disk I/O error occurred. +*/ +REDSTATUS RedCoreStat( + uint32_t ulInode, + REDSTAT *pStat) +{ + REDSTATUS ret; + + if(!gpRedVolume->fMounted || (pStat == NULL)) + { + ret = -RED_EINVAL; + } + else + { + CINODE ino; + + ino.ulInode = ulInode; + ret = RedInodeMount(&ino, FTYPE_EITHER, false); + if(ret == 0) + { + RedMemSet(pStat, 0U, sizeof(*pStat)); + + pStat->st_dev = gbRedVolNum; + pStat->st_ino = ulInode; + pStat->st_mode = ino.pInodeBuf->uMode; + #if REDCONF_API_POSIX_LINK == 1 + pStat->st_nlink = ino.pInodeBuf->uNLink; + #else + pStat->st_nlink = 1U; + #endif + pStat->st_size = ino.pInodeBuf->ullSize; + #if REDCONF_INODE_TIMESTAMPS == 1 + pStat->st_atime = ino.pInodeBuf->ulATime; + pStat->st_mtime = ino.pInodeBuf->ulMTime; + pStat->st_ctime = ino.pInodeBuf->ulCTime; + #endif + #if REDCONF_INODE_BLOCKS == 1 + pStat->st_blocks = ino.pInodeBuf->ulBlocks; + #endif + + RedInodePut(&ino, 0U); + } + } + + return ret; +} +#endif /* REDCONF_API_POSIX == 1 */ + + +#if REDCONF_API_FSE == 1 +/** @brief Get the size of a file. + + @param ulInode The inode number of the file whose size is to be retrieved. + @param pullSize On successful exit, populated with the file size. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBADF @p ulInode is not a valid inode. + @retval -RED_EINVAL The volume is not mounted; @p pullSize is `NULL`. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EISDIR @p ulInode is a directory inode. +*/ +REDSTATUS RedCoreFileSizeGet( + uint32_t ulInode, + uint64_t *pullSize) +{ + REDSTATUS ret; + + if(!gpRedVolume->fMounted || (pullSize == NULL)) + { + ret = -RED_EINVAL; + } + else + { + CINODE ino; + + ino.ulInode = ulInode; + ret = RedInodeMount(&ino, FTYPE_FILE, false); + if(ret == 0) + { + *pullSize = ino.pInodeBuf->ullSize; + + RedInodePut(&ino, 0U); + } + } + + return ret; +} +#endif /* REDCONF_API_FSE == 1 */ + + +/** @brief Read from a file. + + Data which has not yet been written, but which is before the end-of-file + (sparse data), shall read as zeroes. A short read -- where the number of + bytes read is less than requested -- indicates that the requested read was + partially or, if zero bytes were read, entirely beyond the end-of-file. + + If @p ullStart is at or beyond the maximum file size, it is treated like + any other read entirely beyond the end-of-file: no data is read and + @p pulLen is populated with zero. + + @param ulInode The inode number of the file to read. + @param ullStart The file offset to read from. + @param pulLen On entry, contains the number of bytes to read; on + successful exit, contains the number of bytes actually + read. + @param pBuffer The buffer to populate with the data read. Must be big + enough for the read request. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBADF @p ulInode is not a valid inode number. + @retval -RED_EINVAL The volume is not mounted; or @p pBuffer is `NULL`. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EISDIR The inode is a directory inode. +*/ +REDSTATUS RedCoreFileRead( + uint32_t ulInode, + uint64_t ullStart, + uint32_t *pulLen, + void *pBuffer) +{ + REDSTATUS ret; + + if(!gpRedVolume->fMounted || (pulLen == NULL)) + { + ret = -RED_EINVAL; + } + else + { + #if (REDCONF_ATIME == 1) && (REDCONF_READ_ONLY == 0) + bool fUpdateAtime = (*pulLen > 0U) && !gpRedVolume->fReadOnly; + #else + bool fUpdateAtime = false; + #endif + CINODE ino; + + ino.ulInode = ulInode; + ret = RedInodeMount(&ino, FTYPE_FILE, fUpdateAtime); + if(ret == 0) + { + ret = RedInodeDataRead(&ino, ullStart, pulLen, pBuffer); + + #if (REDCONF_ATIME == 1) && (REDCONF_READ_ONLY == 0) + RedInodePut(&ino, ((ret == 0) && fUpdateAtime) ? IPUT_UPDATE_ATIME : 0U); + #else + RedInodePut(&ino, 0U); + #endif + } + } + + return ret; +} + + +#if REDCONF_READ_ONLY == 0 +/** @brief Write to a file. + + If the write extends beyond the end-of-file, the file size will be + increased. + + A short write -- where the number of bytes written is less than requested + -- indicates either that the file system ran out of space but was still + able to write some of the request; or that the request would have caused + the file to exceed the maximum file size, but some of the data could be + written prior to the file size limit. + + If an error is returned, either none of the data was written or a critical + error occurred (like an I/O error) and the file system volume will be + read-only. + + @param ulInode The file number of the file to write. + @param ullStart The file offset to write at. + @param pulLen On entry, the number of bytes to write; on successful exit, + the number of bytes actually written. + @param pBuffer The buffer containing the data to be written. Must big + enough for the write request. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBADF @p ulInode is not a valid file number. + @retval -RED_EFBIG No data can be written to the given file offset since + the resulting file size would exceed the maximum file + size. + @retval -RED_EINVAL The volume is not mounted; or @p pBuffer is `NULL`. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EISDIR The inode is a directory inode. + @retval -RED_ENOSPC No data can be written because there is insufficient + free space. + @retval -RED_EROFS The file system volume is read-only. +*/ +REDSTATUS RedCoreFileWrite( + uint32_t ulInode, + uint64_t ullStart, + uint32_t *pulLen, + const void *pBuffer) +{ + REDSTATUS ret; + + if(!gpRedVolume->fMounted) + { + ret = -RED_EINVAL; + } + else if(gpRedVolume->fReadOnly) + { + ret = -RED_EROFS; + } + else + { + ret = CoreFileWrite(ulInode, ullStart, pulLen, pBuffer); + + if( (ret == -RED_ENOSPC) + && ((gpRedVolume->ulTransMask & RED_TRANSACT_VOLFULL) != 0U) + && (gpRedCoreVol->ulAlmostFreeBlocks > 0U)) + { + ret = RedVolTransact(); + + if(ret == 0) + { + ret = CoreFileWrite(ulInode, ullStart, pulLen, pBuffer); + } + } + + if((ret == 0) && ((gpRedVolume->ulTransMask & RED_TRANSACT_WRITE) != 0U)) + { + ret = RedVolTransact(); + } + } + + return ret; +} + + +/** @brief Write to a file. + + @param ulInode The file number of the file to write. + @param ullStart The file offset to write at. + @param pulLen On entry, the number of bytes to write; on successful exit, + the number of bytes actually written. + @param pBuffer The buffer containing the data to be written. Must big + enough for the write request. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBADF @p ulInode is not a valid file number. + @retval -RED_EFBIG No data can be written to the given file offset since + the resulting file size would exceed the maximum file + size. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EISDIR The inode is a directory inode. + @retval -RED_ENOSPC No data can be written because there is insufficient + free space. + @retval -RED_EROFS The file system volume is read-only. +*/ +static REDSTATUS CoreFileWrite( + uint32_t ulInode, + uint64_t ullStart, + uint32_t *pulLen, + const void *pBuffer) +{ + REDSTATUS ret; + + if(gpRedVolume->fReadOnly) + { + ret = -RED_EROFS; + } + else + { + CINODE ino; + + ino.ulInode = ulInode; + ret = RedInodeMount(&ino, FTYPE_FILE, true); + if(ret == 0) + { + ret = RedInodeDataWrite(&ino, ullStart, pulLen, pBuffer); + + RedInodePut(&ino, (ret == 0) ? (uint8_t)(IPUT_UPDATE_MTIME | IPUT_UPDATE_CTIME) : 0U); + } + } + + return ret; +} +#endif /* REDCONF_READ_ONLY == 0 */ + + +#if TRUNCATE_SUPPORTED +/** @brief Set the file size. + + Allows the file size to be increased, decreased, or to remain the same. If + the file size is increased, the new area is sparse (will read as zeroes). + If the file size is decreased, the data beyond the new end-of-file will + return to free space once it is no longer part of the committed state + (either immediately or after the next transaction point). + + @param ulInode The inode of the file to truncate. + @param ullSize The new file size, in bytes. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBADF @p ulInode is not a valid inode number. + @retval -RED_EFBIG @p ullSize exceeds the maximum file size. + @retval -RED_EINVAL The volume is not mounted. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EISDIR The inode is a directory inode. + @retval -RED_ENOSPC Insufficient free space to perform the truncate. + @retval -RED_EROFS The file system volume is read-only. +*/ +REDSTATUS RedCoreFileTruncate( + uint32_t ulInode, + uint64_t ullSize) +{ + REDSTATUS ret; + + if(!gpRedVolume->fMounted) + { + ret = -RED_EINVAL; + } + else if(gpRedVolume->fReadOnly) + { + ret = -RED_EROFS; + } + else + { + ret = CoreFileTruncate(ulInode, ullSize); + + if( (ret == -RED_ENOSPC) + && ((gpRedVolume->ulTransMask & RED_TRANSACT_VOLFULL) != 0U) + && (gpRedCoreVol->ulAlmostFreeBlocks > 0U)) + { + ret = RedVolTransact(); + + if(ret == 0) + { + ret = CoreFileTruncate(ulInode, ullSize); + } + } + + if((ret == 0) && ((gpRedVolume->ulTransMask & RED_TRANSACT_TRUNCATE) != 0U)) + { + ret = RedVolTransact(); + } + } + + return ret; +} + + +/** @brief Set the file size. + + @param ulInode The inode of the file to truncate. + @param ullSize The new file size, in bytes. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBADF @p ulInode is not a valid inode number. + @retval -RED_EFBIG @p ullSize exceeds the maximum file size. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EISDIR The inode is a directory inode. + @retval -RED_ENOSPC Insufficient free space to perform the truncate. + @retval -RED_EROFS The file system volume is read-only. +*/ +static REDSTATUS CoreFileTruncate( + uint32_t ulInode, + uint64_t ullSize) +{ + REDSTATUS ret; + + if(gpRedVolume->fReadOnly) + { + ret = -RED_EROFS; + } + else + { + CINODE ino; + + ino.ulInode = ulInode; + ret = RedInodeMount(&ino, FTYPE_FILE, true); + if(ret == 0) + { + #if RESERVED_BLOCKS > 0U + gpRedCoreVol->fUseReservedBlocks = (ullSize < ino.pInodeBuf->ullSize); + #endif + + ret = RedInodeDataTruncate(&ino, ullSize); + + #if RESERVED_BLOCKS > 0U + gpRedCoreVol->fUseReservedBlocks = false; + #endif + + RedInodePut(&ino, (ret == 0) ? (uint8_t)(IPUT_UPDATE_MTIME | IPUT_UPDATE_CTIME) : 0U); + } + } + + return ret; +} +#endif /* TRUNCATE_SUPPORTED */ + + +#if (REDCONF_API_POSIX == 1) && (REDCONF_API_POSIX_READDIR == 1) +/** @brief Read from a directory. + + If files are added to the directory after it is opened, the new files may + or may not be returned by this function. If files are deleted, the deleted + files will not be returned. + + @param ulInode The directory inode to read from. + @param pulPos A token which stores the position within the directory. To + read from the beginning of the directory, populate with + zero. + @param pszName Pointer to a buffer which must be big enough to store a + maximum size name, including a null terminator. On + successful exit, populated with the name of the next + directory entry. + @param pulInode On successful return, populated with the inode number of the + next directory entry. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBADF @p ulInode is not a valid inode number. + @retval -RED_EINVAL The volume is not mounted. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENOENT There are no more entries in the directory. + @retval -RED_ENOTDIR @p ulInode refers to a file. +*/ +REDSTATUS RedCoreDirRead( + uint32_t ulInode, + uint32_t *pulPos, + char *pszName, + uint32_t *pulInode) +{ + REDSTATUS ret; + + if(!gpRedVolume->fMounted) + { + ret = -RED_EINVAL; + } + else + { + CINODE ino; + + ino.ulInode = ulInode; + ret = RedInodeMount(&ino, FTYPE_DIR, false); + + if(ret == 0) + { + ret = RedDirEntryRead(&ino, pulPos, pszName, pulInode); + + #if (REDCONF_ATIME == 1) && (REDCONF_READ_ONLY == 0) + if((ret == 0) && !gpRedVolume->fReadOnly) + { + ret = RedInodeBranch(&ino); + } + + RedInodePut(&ino, ((ret == 0) && !gpRedVolume->fReadOnly) ? IPUT_UPDATE_ATIME : 0U); + #else + RedInodePut(&ino, 0U); + #endif + } + } + + return ret; +} +#endif /* (REDCONF_API_POSIX == 1) && (REDCONF_API_POSIX_READDIR == 1) */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/dir.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/dir.c new file mode 100644 index 0000000..cfda1c1 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/dir.c @@ -0,0 +1,958 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements directory operations. +*/ +#include + +#if REDCONF_API_POSIX == 1 + +#include + + +#define DIR_INDEX_INVALID UINT32_MAX + +#if (REDCONF_NAME_MAX % 4U) != 0U +#define DIRENT_PADDING (4U - (REDCONF_NAME_MAX % 4U)) +#else +#define DIRENT_PADDING (0U) +#endif +#define DIRENT_SIZE (4U + REDCONF_NAME_MAX + DIRENT_PADDING) +#define DIRENTS_PER_BLOCK (REDCONF_BLOCK_SIZE / DIRENT_SIZE) +#define DIRENTS_MAX (uint32_t)REDMIN(UINT32_MAX, UINT64_SUFFIX(1) * INODE_DATA_BLOCKS * DIRENTS_PER_BLOCK) + + +/** @brief On-disk directory entry. +*/ +typedef struct +{ + /** The inode number that the directory entry points at. If the directory + entry is available, this holds INODE_INVALID. + */ + uint32_t ulInode; + + /** The name of the directory entry. For names shorter than + REDCONF_NAME_MAX, unused bytes in the array are zeroed. For names of + the maximum length, the string is not null terminated. + */ + char acName[REDCONF_NAME_MAX]; + + #if DIRENT_PADDING > 0U + /** Unused padding so that ulInode is always aligned on a four-byte + boundary. + */ + uint8_t abPadding[DIRENT_PADDING]; + #endif +} DIRENT; + + +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX_RENAME == 1) +static REDSTATUS DirCyclicRenameCheck(uint32_t ulSrcInode, const CINODE *pDstPInode); +#endif +#if REDCONF_READ_ONLY == 0 +static REDSTATUS DirEntryWrite(CINODE *pPInode, uint32_t ulIdx, uint32_t ulInode, const char *pszName, uint32_t ulNameLen); +static uint64_t DirEntryIndexToOffset(uint32_t ulIdx); +#endif +static uint32_t DirOffsetToEntryIndex(uint64_t ullOffset); + + +#if REDCONF_READ_ONLY == 0 +/** @brief Create a new entry in a directory. + + @param pPInode A pointer to the cached inode structure of the directory + to which the new entry will be added. + @param pszName The name to be given to the new entry, terminated by a + null or a path separator. + @param ulInode The inode number the new name will point at. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENOSPC There is not enough space on the volume to + create the new directory entry; or the directory + is full. + @retval -RED_ENOTDIR @p pPInode is not a directory. + @retval -RED_ENAMETOOLONG @p pszName is too long. + @retval -RED_EEXIST @p pszName already exists in @p ulPInode. + @retval -RED_EINVAL @p pPInode is not a mounted dirty cached inode + structure; or @p pszName is not a valid name. +*/ +REDSTATUS RedDirEntryCreate( + CINODE *pPInode, + const char *pszName, + uint32_t ulInode) +{ + REDSTATUS ret; + + if(!CINODE_IS_DIRTY(pPInode) || (pszName == NULL) || !INODE_IS_VALID(ulInode)) + { + ret = -RED_EINVAL; + } + else if(!pPInode->fDirectory) + { + ret = -RED_ENOTDIR; + } + else + { + uint32_t ulNameLen = RedNameLen(pszName); + + if(ulNameLen == 0U) + { + ret = -RED_EINVAL; + } + else if(ulNameLen > REDCONF_NAME_MAX) + { + ret = -RED_ENAMETOOLONG; + } + else + { + uint32_t ulEntryIdx; + + ret = RedDirEntryLookup(pPInode, pszName, &ulEntryIdx, NULL); + if(ret == 0) + { + ret = -RED_EEXIST; + } + else if(ret == -RED_ENOENT) + { + if(ulEntryIdx == DIR_INDEX_INVALID) + { + ret = -RED_ENOSPC; + } + else + { + ret = 0; + } + } + else + { + /* Unexpected error, no action. + */ + } + + if(ret == 0) + { + ret = DirEntryWrite(pPInode, ulEntryIdx, ulInode, pszName, ulNameLen); + } + } + } + + return ret; +} +#endif /* REDCONF_READ_ONLY == 0 */ + + +#if DELETE_SUPPORTED +/** @brief Delete an existing directory entry. + + @param pPInode A pointer to the cached inode structure of the directory + containing the entry to be deleted. + @param ulDeleteIdx Position within the directory of the entry to be + deleted. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENOSPC The file system does not have enough space to modify + the parent directory to perform the deletion. + @retval -RED_ENOTDIR @p pPInode is not a directory. + @retval -RED_EINVAL @p pPInode is not a mounted dirty cached inode + structure; or @p ulIdx is out of range. +*/ +REDSTATUS RedDirEntryDelete( + CINODE *pPInode, + uint32_t ulDeleteIdx) +{ + REDSTATUS ret = 0; + + if(!CINODE_IS_DIRTY(pPInode) || (ulDeleteIdx >= DIRENTS_MAX)) + { + ret = -RED_EINVAL; + } + else if(!pPInode->fDirectory) + { + ret = -RED_ENOTDIR; + } + else if((DirEntryIndexToOffset(ulDeleteIdx) + DIRENT_SIZE) == pPInode->pInodeBuf->ullSize) + { + /* Start searching one behind the index to be deleted. + */ + uint32_t ulTruncIdx = ulDeleteIdx - 1U; + bool fDone = false; + + /* We are deleting the last dirent in the directory, so search + backwards to find the last populated dirent, allowing us to truncate + the directory to that point. + */ + while((ret == 0) && (ulTruncIdx != UINT32_MAX) && !fDone) + { + ret = RedInodeDataSeekAndRead(pPInode, ulTruncIdx / DIRENTS_PER_BLOCK); + + if(ret == 0) + { + const DIRENT *pDirents = CAST_CONST_DIRENT_PTR(pPInode->pbData); + uint32_t ulBlockIdx = ulTruncIdx % DIRENTS_PER_BLOCK; + + do + { + if(pDirents[ulBlockIdx].ulInode != INODE_INVALID) + { + fDone = true; + break; + } + + ulTruncIdx--; + ulBlockIdx--; + } while(ulBlockIdx != UINT32_MAX); + } + else if(ret == -RED_ENODATA) + { + ret = 0; + + REDASSERT((ulTruncIdx % DIRENTS_PER_BLOCK) == 0U); + ulTruncIdx -= DIRENTS_PER_BLOCK; + } + else + { + /* Unexpected error, loop will terminate; nothing else + to be done. + */ + } + } + + /* Currently ulTruncIdx represents the last valid dirent index, or + UINT32_MAX if the directory is now empty. Increment it so that it + represents the first invalid entry, which will be truncated. + */ + ulTruncIdx++; + + /* Truncate the directory, deleting the requested entry and any empty + dirents at the end of the directory. + */ + if(ret == 0) + { + ret = RedInodeDataTruncate(pPInode, DirEntryIndexToOffset(ulTruncIdx)); + } + } + else + { + /* The dirent to delete is not the last entry in the directory, so just + zero it. + */ + ret = DirEntryWrite(pPInode, ulDeleteIdx, INODE_INVALID, "", 0U); + } + + return ret; +} +#endif /* DELETE_SUPPORTED */ + + +/** @brief Perform a case-sensitive search of a directory for a given name. + + If found, then position of the entry within the directory and the inode + number it points to are returned. As an optimization for directory entry + creation, in the case where the requested entry does not exist, the position + of the first available (unused) entry is returned. + + @param pPInode A pointer to the cached inode structure of the directory + to search. + @param pszName The name of the desired entry, terminated by either a + null or a path separator. + @param pulEntryIdx On successful return, meaning that the desired entry + exists, populated with the position of the entry. If + returning an -RED_ENOENT error, populated with the + position of the first available entry, or set to + DIR_INDEX_INVALID if the directory is full. Optional. + @param pulInode On successful return, populated with the inode number + that the name points to. Optional; may be `NULL`. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENOENT @p pszName does not name an existing file or + directory. + @retval -RED_ENOTDIR @p pPInode is not a directory. + @retval -RED_EINVAL @p pPInode is not a mounted cached inode + structure; or @p pszName is not a valid name; or + @p pulEntryIdx is `NULL`. + @retval -RED_ENAMETOOLONG @p pszName is too long. +*/ +REDSTATUS RedDirEntryLookup( + CINODE *pPInode, + const char *pszName, + uint32_t *pulEntryIdx, + uint32_t *pulInode) +{ + REDSTATUS ret = 0; + + if(!CINODE_IS_MOUNTED(pPInode) || (pszName == NULL)) + { + ret = -RED_EINVAL; + } + else if(!pPInode->fDirectory) + { + ret = -RED_ENOTDIR; + } + else + { + uint32_t ulNameLen = RedNameLen(pszName); + + if(ulNameLen == 0U) + { + ret = -RED_EINVAL; + } + else if(ulNameLen > REDCONF_NAME_MAX) + { + ret = -RED_ENAMETOOLONG; + } + else + { + uint32_t ulIdx = 0U; + uint32_t ulDirentCount = DirOffsetToEntryIndex(pPInode->pInodeBuf->ullSize); + uint32_t ulFreeIdx = DIR_INDEX_INVALID; /* Index of first free dirent. */ + + /* Loop over the directory blocks, searching each block for a + dirent that matches the given name. + */ + while((ret == 0) && (ulIdx < ulDirentCount)) + { + ret = RedInodeDataSeekAndRead(pPInode, ulIdx / DIRENTS_PER_BLOCK); + + if(ret == 0) + { + const DIRENT *pDirents = CAST_CONST_DIRENT_PTR(pPInode->pbData); + uint32_t ulBlockLastIdx = REDMIN(DIRENTS_PER_BLOCK, ulDirentCount - ulIdx); + uint32_t ulBlockIdx; + + for(ulBlockIdx = 0U; ulBlockIdx < ulBlockLastIdx; ulBlockIdx++) + { + const DIRENT *pDirent = &pDirents[ulBlockIdx]; + + if(pDirent->ulInode != INODE_INVALID) + { + /* The name in the dirent will not be null + terminated if it is of the maximum length, so + use a bounded string compare and then make sure + there is nothing more to the name. + */ + if( (RedStrNCmp(pDirent->acName, pszName, ulNameLen) == 0) + && ((ulNameLen == REDCONF_NAME_MAX) || (pDirent->acName[ulNameLen] == '\0'))) + { + /* Found a matching dirent, stop and return its + information. + */ + if(pulInode != NULL) + { + *pulInode = pDirent->ulInode; + + #ifdef REDCONF_ENDIAN_SWAP + *pulInode = RedRev32(*pulInode); + #endif + } + + ulIdx += ulBlockIdx; + break; + } + } + else if(ulFreeIdx == DIR_INDEX_INVALID) + { + ulFreeIdx = ulIdx + ulBlockIdx; + } + else + { + /* The directory entry is free, but we already found a free one, so there's + nothing to do here. + */ + } + } + + if(ulBlockIdx < ulBlockLastIdx) + { + /* If we broke out of the for loop, we found a matching + dirent and can stop the search. + */ + break; + } + + ulIdx += ulBlockLastIdx; + } + else if(ret == -RED_ENODATA) + { + if(ulFreeIdx == DIR_INDEX_INVALID) + { + ulFreeIdx = ulIdx; + } + + ret = 0; + ulIdx += DIRENTS_PER_BLOCK; + } + else + { + /* Unexpected error, let the loop terminate, no action + here. + */ + } + } + + if(ret == 0) + { + /* If we made it all the way to the end of the directory + without stopping, then the given name does not exist in the + directory. + */ + if(ulIdx == ulDirentCount) + { + /* If the directory had no sparse dirents, then the first + free dirent is beyond the end of the directory. If the + directory is already the maximum size, then there is no + free dirent. + */ + if((ulFreeIdx == DIR_INDEX_INVALID) && (ulDirentCount < DIRENTS_MAX)) + { + ulFreeIdx = ulDirentCount; + } + + ulIdx = ulFreeIdx; + + ret = -RED_ENOENT; + } + + if(pulEntryIdx != NULL) + { + *pulEntryIdx = ulIdx; + } + } + } + } + + return ret; +} + + +#if (REDCONF_API_POSIX_READDIR == 1) || (REDCONF_CHECKER == 1) +/** @brief Read the next entry from a directory, given a starting index. + + @param pPInode A pointer to the cached inode structure of the directory to + read from. + @param pulIdx On entry, the directory index to start reading from. On + successful return, populated with the directory index to use + for subsequent reads. On -RED_ENOENT return, populated with + the directory index immediately following the last valid + one. + @param pszName On successful return, populated with the name of the next + directory entry. Buffer must be at least + REDCONF_NAME_MAX + 1 in size, to store the maximum name + length plus a null terminator. + @param pulInode On successful return, populated with the inode number + pointed at by the next directory entry. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENOENT There are no more entries in the directory. + @retval -RED_ENOTDIR @p pPInode is not a directory. + @retval -RED_EINVAL @p pPInode is not a mounted cached inode structure; + or @p pszName is `NULL`; or @p pulIdx is `NULL`; or + @p pulInode is `NULL`. +*/ +REDSTATUS RedDirEntryRead( + CINODE *pPInode, + uint32_t *pulIdx, + char *pszName, + uint32_t *pulInode) +{ + REDSTATUS ret = 0; + + if(!CINODE_IS_MOUNTED(pPInode) || (pulIdx == NULL) || (pszName == NULL) || (pulInode == NULL)) + { + ret = -RED_EINVAL; + } + else if(!pPInode->fDirectory) + { + ret = -RED_ENOTDIR; + } + else + { + uint32_t ulIdx = *pulIdx; + uint32_t ulDirentCount = DirOffsetToEntryIndex(pPInode->pInodeBuf->ullSize); + + /* Starting either at the beginning of the directory or where we left + off, loop over the directory blocks, searching each block for a + non-sparse dirent to return as the next entry in the directory. + */ + while((ret == 0) && (ulIdx < ulDirentCount)) + { + uint32_t ulBlockOffset = ulIdx / DIRENTS_PER_BLOCK; + + ret = RedInodeDataSeekAndRead(pPInode, ulBlockOffset); + + if(ret == 0) + { + const DIRENT *pDirents = CAST_CONST_DIRENT_PTR(pPInode->pbData); + uint32_t ulBlockLastIdx = REDMIN(DIRENTS_PER_BLOCK, ulDirentCount - (ulBlockOffset * DIRENTS_PER_BLOCK)); + uint32_t ulBlockIdx; + + for(ulBlockIdx = ulIdx % DIRENTS_PER_BLOCK; ulBlockIdx < ulBlockLastIdx; ulBlockIdx++) + { + if(pDirents[ulBlockIdx].ulInode != INODE_INVALID) + { + *pulIdx = ulIdx + 1U; + RedStrNCpy(pszName, pDirents[ulBlockIdx].acName, REDCONF_NAME_MAX); + pszName[REDCONF_NAME_MAX] = '\0'; + + *pulInode = pDirents[ulBlockIdx].ulInode; + + #ifdef REDCONF_ENDIAN_SWAP + *pulInode = RedRev32(*pulInode); + #endif + break; + } + + ulIdx++; + } + + if(ulBlockIdx < ulBlockLastIdx) + { + REDASSERT(ulIdx <= ulDirentCount); + break; + } + } + else if(ret == -RED_ENODATA) + { + ulIdx += DIRENTS_PER_BLOCK - (ulIdx % DIRENTS_PER_BLOCK); + ret = 0; + } + else + { + /* Unexpected error, loop will terminate; nothing else to do. + */ + } + + REDASSERT(ulIdx <= ulDirentCount); + } + + if((ret == 0) && (ulIdx >= ulDirentCount)) + { + *pulIdx = ulDirentCount; + ret = -RED_ENOENT; + } + } + + return ret; +} +#endif + + +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX_RENAME == 1) +/** Rename a directory entry. + + @param pSrcPInode The inode of the directory containing @p pszSrcName. + @param pszSrcName The name of the directory entry to be renamed. + @param pSrcInode On successful return, populated with the inode of the + source entry. + @param pDstPInode The inode of the directory in which @p pszDstName will + be created or replaced. + @param pszDstName The name of the directory entry to be created or + replaced. + @param pDstInode On successful return, if the destination previously + existed, populated with the inode previously pointed to + by the destination. This may be the same as the source + inode. If the destination did not exist, populated with + INODE_INVALID. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EEXIST #REDCONF_RENAME_ATOMIC is false and the + destination name exists. + @retval -RED_EINVAL @p pSrcPInode is not a mounted dirty cached + inode structure; or @p pSrcInode is `NULL`; or + @p pszSrcName is not a valid name; or + @p pDstPInode is not a mounted dirty cached + inode structure; or @p pDstInode is `NULL`; or + @p pszDstName is not a valid name. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EISDIR The destination name exists and is a directory, + and the source name is a non-directory. + @retval -RED_ENAMETOOLONG Either @p pszSrcName or @p pszDstName is longer + than #REDCONF_NAME_MAX. + @retval -RED_ENOENT The source name is not an existing entry; or + either @p pszSrcName or @p pszDstName point to + an empty string. + @retval -RED_ENOTDIR @p pSrcPInode is not a directory; or + @p pDstPInode is not a directory; or the source + name is a directory and the destination name is + a file. + @retval -RED_ENOTEMPTY The destination name is a directory which is not + empty. + @retval -RED_ENOSPC The file system does not have enough space to + extend the @p ulDstPInode directory. + @retval -RED_EROFS The directory to be removed resides on a + read-only file system. +*/ +REDSTATUS RedDirEntryRename( + CINODE *pSrcPInode, + const char *pszSrcName, + CINODE *pSrcInode, + CINODE *pDstPInode, + const char *pszDstName, + CINODE *pDstInode) +{ + REDSTATUS ret; + + if( !CINODE_IS_DIRTY(pSrcPInode) + || (pszSrcName == NULL) + || (pSrcInode == NULL) + || !CINODE_IS_DIRTY(pDstPInode) + || (pszDstName == NULL) + || (pDstInode == NULL)) + { + ret = -RED_EINVAL; + } + else if(!pSrcPInode->fDirectory || !pDstPInode->fDirectory) + { + ret = -RED_ENOTDIR; + } + else + { + uint32_t ulDstIdx = 0U; /* Init'd to quiet warnings. */ + uint32_t ulSrcIdx; + + /* Look up the source and destination names. + */ + ret = RedDirEntryLookup(pSrcPInode, pszSrcName, &ulSrcIdx, &pSrcInode->ulInode); + + if(ret == 0) + { + ret = RedDirEntryLookup(pDstPInode, pszDstName, &ulDstIdx, &pDstInode->ulInode); + + if(ret == -RED_ENOENT) + { + if(ulDstIdx == DIR_INDEX_INVALID) + { + ret = -RED_ENOSPC; + } + else + { + #if REDCONF_RENAME_ATOMIC == 1 + pDstInode->ulInode = INODE_INVALID; + #endif + ret = 0; + } + } + #if REDCONF_RENAME_ATOMIC == 0 + else if(ret == 0) + { + ret = -RED_EEXIST; + } + else + { + /* Nothing to do here, just propagate the error. + */ + } + #endif + } + + #if REDCONF_RENAME_ATOMIC == 1 + /* If both names point to the same inode, POSIX says to do nothing to + either name. + */ + if((ret == 0) && (pSrcInode->ulInode != pDstInode->ulInode)) + #else + if(ret == 0) + #endif + { + ret = RedInodeMount(pSrcInode, FTYPE_EITHER, true); + + #if REDCONF_RENAME_ATOMIC == 1 + if((ret == 0) && (pDstInode->ulInode != INODE_INVALID)) + { + /* Source and destination must be the same type (file/dir). + */ + ret = RedInodeMount(pDstInode, pSrcInode->fDirectory ? FTYPE_DIR : FTYPE_FILE, true); + + /* If renaming directories, the destination must be empty. + */ + if((ret == 0) && pDstInode->fDirectory && (pDstInode->pInodeBuf->ullSize > 0U)) + { + ret = -RED_ENOTEMPTY; + } + } + #endif + + /* If we are renaming a directory, make sure the rename isn't + cyclic (e.g., renaming "foo" into "foo/bar"). + */ + if((ret == 0) && pSrcInode->fDirectory) + { + ret = DirCyclicRenameCheck(pSrcInode->ulInode, pDstPInode); + } + + if(ret == 0) + { + ret = DirEntryWrite(pDstPInode, ulDstIdx, pSrcInode->ulInode, pszDstName, RedNameLen(pszDstName)); + } + + if(ret == 0) + { + ret = RedDirEntryDelete(pSrcPInode, ulSrcIdx); + + if(ret == -RED_ENOSPC) + { + REDSTATUS ret2; + + /* If there was not enough space to branch the parent + directory inode and data block containin the source + entry, revert destination directory entry to its + previous state. + */ + #if REDCONF_RENAME_ATOMIC == 1 + if(pDstInode->ulInode != INODE_INVALID) + { + ret2 = DirEntryWrite(pDstPInode, ulDstIdx, pDstInode->ulInode, pszDstName, RedNameLen(pszDstName)); + } + else + #endif + { + ret2 = RedDirEntryDelete(pDstPInode, ulDstIdx); + } + + if(ret2 != 0) + { + ret = ret2; + CRITICAL_ERROR(); + } + } + } + + if(ret == 0) + { + pSrcInode->pInodeBuf->ulPInode = pDstPInode->ulInode; + } + } + } + + return ret; +} + + +/** @brief Check for a cyclic rename. + + A cyclic rename is renaming a directory into a subdirectory of itself. For + example, renaming "a" into "a/b/c/d" is cyclic. These renames must not be + allowed since they would corrupt the directory tree. + + @param ulSrcInode The inode number of the directory being renamed. + @param pDstPInode A pointer to the cached inode structure of the directory + into which the source is being renamed. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EINVAL The rename is cyclic; or invalid parameters. + @retval -RED_ENOTDIR @p pDstPInode is not a directory. +*/ +static REDSTATUS DirCyclicRenameCheck( + uint32_t ulSrcInode, + const CINODE *pDstPInode) +{ + REDSTATUS ret = 0; + + if(!INODE_IS_VALID(ulSrcInode) || !CINODE_IS_MOUNTED(pDstPInode)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else if(ulSrcInode == pDstPInode->ulInode) + { + ret = -RED_EINVAL; + } + else if(!pDstPInode->fDirectory) + { + ret = -RED_ENOTDIR; + } + else + { + CINODE NextParent; + /* Used to prevent infinite loop in case of corrupted directory + structure. + */ + uint32_t ulIteration = 0U; + + NextParent.ulInode = pDstPInode->pInodeBuf->ulPInode; + + while( (NextParent.ulInode != ulSrcInode) + && (NextParent.ulInode != INODE_ROOTDIR) + && (NextParent.ulInode != INODE_INVALID) + && (ulIteration < gpRedVolConf->ulInodeCount)) + { + ret = RedInodeMount(&NextParent, FTYPE_DIR, false); + if(ret != 0) + { + break; + } + + NextParent.ulInode = NextParent.pInodeBuf->ulPInode; + + RedInodePut(&NextParent, 0U); + + ulIteration++; + } + + if((ret == 0) && (ulIteration == gpRedVolConf->ulInodeCount)) + { + CRITICAL_ERROR(); + ret = -RED_EFUBAR; + } + + if((ret == 0) && (ulSrcInode == NextParent.ulInode)) + { + ret = -RED_EINVAL; + } + } + + return ret; +} +#endif /* (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX_RENAME == 1) */ + + +#if REDCONF_READ_ONLY == 0 +/** @brief Update the contents of a directory entry. + + @param pPInode A pointer to the cached inode structure of the directory + whose entry is being written. + @param ulIdx The index of the directory entry to write. + @param ulInode The inode number the directory entry is to point at. + @param pszName The name of the directory entry. + @param ulNameLen The length of @p pszName. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENOSPC There is not enough space on the volume to write the + directory entry. + @retval -RED_ENOTDIR @p pPInode is not a directory. + @retval -RED_EINVAL Invalid parameters. +*/ +static REDSTATUS DirEntryWrite( + CINODE *pPInode, + uint32_t ulIdx, + uint32_t ulInode, + const char *pszName, + uint32_t ulNameLen) +{ + REDSTATUS ret; + + if( !CINODE_IS_DIRTY(pPInode) + || (ulIdx >= DIRENTS_MAX) + || (!INODE_IS_VALID(ulInode) && (ulInode != INODE_INVALID)) + || (pszName == NULL) + || (ulNameLen > REDCONF_NAME_MAX) + || ((ulNameLen == 0U) != (ulInode == INODE_INVALID))) + { + REDERROR(); + ret = -RED_EINVAL; + } + else if(!pPInode->fDirectory) + { + ret = -RED_ENOTDIR; + } + else + { + uint64_t ullOffset = DirEntryIndexToOffset(ulIdx); + uint32_t ulLen = DIRENT_SIZE; + static DIRENT de; + + RedMemSet(&de, 0U, sizeof(de)); + + de.ulInode = ulInode; + + #ifdef REDCONF_ENDIAN_SWAP + de.ulInode = RedRev32(de.ulInode); + #endif + + RedStrNCpy(de.acName, pszName, ulNameLen); + + ret = RedInodeDataWrite(pPInode, ullOffset, &ulLen, &de); + } + + return ret; +} + + +/** @brief Convert a directory entry index to a byte offset. + + @param ulIdx Directory entry index. + + @return Byte offset in the directory corresponding with ulIdx. +*/ +static uint64_t DirEntryIndexToOffset( + uint32_t ulIdx) +{ + uint32_t ulBlock = ulIdx / DIRENTS_PER_BLOCK; + uint32_t ulOffsetInBlock = ulIdx % DIRENTS_PER_BLOCK; + uint64_t ullOffset; + + REDASSERT(ulIdx < DIRENTS_MAX); + + ullOffset = (uint64_t)ulBlock << BLOCK_SIZE_P2; + ullOffset += (uint64_t)ulOffsetInBlock * DIRENT_SIZE; + + return ullOffset; +} +#endif /* REDCONF_READ_ONLY == 0 */ + + +/** @brief Convert a byte offset to a directory entry index. + + @param ullOffset Byte offset in the directory. + + @return Directory entry index corresponding with @p ullOffset. +*/ +static uint32_t DirOffsetToEntryIndex( + uint64_t ullOffset) +{ + uint32_t ulIdx; + + REDASSERT(ullOffset < INODE_SIZE_MAX); + REDASSERT(((uint32_t)(ullOffset & (REDCONF_BLOCK_SIZE - 1U)) % DIRENT_SIZE) == 0U); + + /* Avoid doing any 64-bit divides. + */ + ulIdx = (uint32_t)(ullOffset >> BLOCK_SIZE_P2) * DIRENTS_PER_BLOCK; + ulIdx += (uint32_t)(ullOffset & (REDCONF_BLOCK_SIZE - 1U)) / DIRENT_SIZE; + + return ulIdx; +} + + +#endif /* REDCONF_API_POSIX == 1 */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/format.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/format.c new file mode 100644 index 0000000..8fe8f14 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/format.c @@ -0,0 +1,235 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements the Reliance Edge file system formatter. +*/ +#include +#include +#include + +#if FORMAT_SUPPORTED + + +/** @brief Format a file system volume. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBUSY Volume is mounted. + @retval -RED_EIO A disk I/O error occurred. +*/ +REDSTATUS RedVolFormat(void) +{ + REDSTATUS ret; + + if(gpRedVolume->fMounted) + { + ret = -RED_EBUSY; + } + else + { + ret = RedOsBDevOpen(gbRedVolNum, BDEV_O_RDWR); + } + + if(ret == 0) + { + MASTERBLOCK *pMB; + REDSTATUS ret2; + + /* Overwrite the master block with zeroes, so that if formatting is + interrupted, the volume will not be mountable. + */ + ret = RedBufferGet(BLOCK_NUM_MASTER, BFLAG_NEW | BFLAG_DIRTY, CAST_VOID_PTR_PTR(&pMB)); + + if(ret == 0) + { + ret = RedBufferFlush(BLOCK_NUM_MASTER, 1U); + + RedBufferDiscard(pMB); + } + + if(ret == 0) + { + ret = RedIoFlush(gbRedVolNum); + } + + #if REDCONF_IMAP_EXTERNAL == 1 + if((ret == 0) && !gpRedCoreVol->fImapInline) + { + uint32_t ulImapBlock; + uint32_t ulImapBlockLimit = gpRedCoreVol->ulImapStartBN + (gpRedCoreVol->ulImapNodeCount * 2U); + uint16_t uImapFlags = (uint16_t)((uint32_t)BFLAG_META_IMAP | BFLAG_NEW | BFLAG_DIRTY); + + /* Technically it is only necessary to create one copy of each imap + node (the copy the metaroot points at), but creating them both + avoids headaches during disk image analysis from stale imaps + left over from previous formats. + */ + for(ulImapBlock = gpRedCoreVol->ulImapStartBN; ulImapBlock < ulImapBlockLimit; ulImapBlock++) + { + IMAPNODE *pImap; + + ret = RedBufferGet(ulImapBlock, uImapFlags, CAST_VOID_PTR_PTR(&pImap)); + if(ret != 0) + { + break; + } + + RedBufferPut(pImap); + } + } + #endif + + /* Write the first metaroot. + */ + if(ret == 0) + { + RedMemSet(gpRedMR, 0U, sizeof(*gpRedMR)); + + gpRedMR->ulFreeBlocks = gpRedVolume->ulBlocksAllocable; + #if REDCONF_API_POSIX == 1 + gpRedMR->ulFreeInodes = gpRedVolConf->ulInodeCount; + #endif + gpRedMR->ulAllocNextBlock = gpRedCoreVol->ulFirstAllocableBN; + + /* The branched flag is typically set automatically when bits in + the imap change. It is set here explicitly because the imap has + only been initialized, not changed. + */ + gpRedCoreVol->fBranched = true; + + ret = RedVolTransact(); + } + + #if REDCONF_API_POSIX == 1 + /* Create the root directory. + */ + if(ret == 0) + { + CINODE rootdir; + + rootdir.ulInode = INODE_ROOTDIR; + ret = RedInodeCreate(&rootdir, INODE_INVALID, RED_S_IFDIR); + + if(ret == 0) + { + RedInodePut(&rootdir, 0U); + } + } + #endif + + #if REDCONF_API_FSE == 1 + /* The FSE API does not support creating or deletes files, so all the + inodes are created during setup. + */ + if(ret == 0) + { + uint32_t ulInodeIdx; + + for(ulInodeIdx = 0U; ulInodeIdx < gpRedVolConf->ulInodeCount; ulInodeIdx++) + { + CINODE ino; + + ino.ulInode = INODE_FIRST_FREE + ulInodeIdx; + ret = RedInodeCreate(&ino, INODE_INVALID, RED_S_IFREG); + + if(ret == 0) + { + RedInodePut(&ino, 0U); + } + } + } + #endif + + /* Write the second metaroot. + */ + if(ret == 0) + { + ret = RedVolTransact(); + } + + /* Populate and write out the master block. + */ + if(ret == 0) + { + ret = RedBufferGet(BLOCK_NUM_MASTER, (uint16_t)((uint32_t)BFLAG_META_MASTER | BFLAG_NEW | BFLAG_DIRTY), CAST_VOID_PTR_PTR(&pMB)); + } + + if(ret == 0) + { + pMB->ulVersion = RED_DISK_LAYOUT_VERSION; + RedStrNCpy(pMB->acBuildNum, RED_BUILD_NUMBER, sizeof(pMB->acBuildNum)); + pMB->ulFormatTime = RedOsClockGetTime(); + pMB->ulInodeCount = gpRedVolConf->ulInodeCount; + pMB->ulBlockCount = gpRedVolume->ulBlockCount; + pMB->uMaxNameLen = REDCONF_NAME_MAX; + pMB->uDirectPointers = REDCONF_DIRECT_POINTERS; + pMB->uIndirectPointers = REDCONF_INDIRECT_POINTERS; + pMB->bBlockSizeP2 = BLOCK_SIZE_P2; + + #if REDCONF_API_POSIX == 1 + pMB->bFlags |= MBFLAG_API_POSIX; + #endif + #if REDCONF_INODE_TIMESTAMPS == 1 + pMB->bFlags |= MBFLAG_INODE_TIMESTAMPS; + #endif + #if REDCONF_INODE_BLOCKS == 1 + pMB->bFlags |= MBFLAG_INODE_BLOCKS; + #endif + #if (REDCONF_API_POSIX == 1) && (REDCONF_API_POSIX_LINK == 1) + pMB->bFlags |= MBFLAG_INODE_NLINK; + #endif + + ret = RedBufferFlush(BLOCK_NUM_MASTER, 1U); + + RedBufferPut(pMB); + } + + if(ret == 0) + { + ret = RedIoFlush(gbRedVolNum); + } + + ret2 = RedOsBDevClose(gbRedVolNum); + if(ret == 0) + { + ret = ret2; + } + } + + /* Discard the buffers so a subsequent format will not run into blocks it + does not expect. + */ + if(ret == 0) + { + ret = RedBufferDiscardRange(0U, gpRedVolume->ulBlockCount); + } + + return ret; +} + + +#endif /* FORMAT_SUPPORTED */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/imap.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/imap.c new file mode 100644 index 0000000..87664d1 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/imap.c @@ -0,0 +1,349 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements allocation routines. + + This module implements routines for working with the imap, a bitmap which + tracks which blocks are allocated or free. Some of the functionality is + delegated to imapinline.c and imapextern.c. +*/ +#include +#include + + +/** @brief Get the allocation bit of a block from either metaroot. + + Will pass the call down either to the inline imap or to the external imap + implementation, whichever is appropriate for the current volume. + + @param bMR The metaroot index: either 0 or 1. + @param ulBlock The block number to query. + @param pfAllocated On successful return, populated with the allocation bit + of the block. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p bMR is out of range; or @p ulBlock is out of range; + or @p pfAllocated is `NULL`. + @retval -RED_EIO A disk I/O error occurred. +*/ +REDSTATUS RedImapBlockGet( + uint8_t bMR, + uint32_t ulBlock, + bool *pfAllocated) +{ + REDSTATUS ret; + + if( (bMR > 1U) + || (ulBlock < gpRedCoreVol->ulInodeTableStartBN) + || (ulBlock >= gpRedVolume->ulBlockCount) + || (pfAllocated == NULL)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + #if (REDCONF_IMAP_INLINE == 1) && (REDCONF_IMAP_EXTERNAL == 1) + if(gpRedCoreVol->fImapInline) + { + ret = RedImapIBlockGet(bMR, ulBlock, pfAllocated); + } + else + { + ret = RedImapEBlockGet(bMR, ulBlock, pfAllocated); + } + #elif REDCONF_IMAP_INLINE == 1 + ret = RedImapIBlockGet(bMR, ulBlock, pfAllocated); + #else + ret = RedImapEBlockGet(bMR, ulBlock, pfAllocated); + #endif + } + + return ret; +} + + +#if REDCONF_READ_ONLY == 0 +/** @brief Set the allocation bit of a block in the working metaroot. + + Will pass the call down either to the inline imap or to the external imap + implementation, whichever is appropriate for the current volume. + + @param ulBlock The block number to allocate or free. + @param fAllocated Whether to allocate the block (true) or free it (false). + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p ulBlock is out of range; or @p ulBlock is allocable + and @p fAllocated is 1. + @retval -RED_EIO A disk I/O error occurred. +*/ +REDSTATUS RedImapBlockSet( + uint32_t ulBlock, + bool fAllocated) +{ + REDSTATUS ret; + + if( (ulBlock < gpRedCoreVol->ulInodeTableStartBN) + || (ulBlock >= gpRedVolume->ulBlockCount)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else if( (ulBlock >= gpRedCoreVol->ulFirstAllocableBN) + && ( (fAllocated && (gpRedMR->ulFreeBlocks == 0U)) + || ((!fAllocated) && (gpRedMR->ulFreeBlocks >= gpRedVolume->ulBlocksAllocable)))) + { + /* Attempting either to free more blocks than are allocable, or + allocate a block when there are none available. This could indicate + metadata corruption. + */ + CRITICAL_ERROR(); + ret = -RED_EFUBAR; + } + else + { + #if (REDCONF_IMAP_INLINE == 1) && (REDCONF_IMAP_EXTERNAL == 1) + if(gpRedCoreVol->fImapInline) + { + ret = RedImapIBlockSet(ulBlock, fAllocated); + } + else + { + ret = RedImapEBlockSet(ulBlock, fAllocated); + } + #elif REDCONF_IMAP_INLINE == 1 + ret = RedImapIBlockSet(ulBlock, fAllocated); + #else + ret = RedImapEBlockSet(ulBlock, fAllocated); + #endif + + /* Any change to the allocation state of a block indicates that the + volume is now branched. + */ + gpRedCoreVol->fBranched = true; + } + + /* If a block was marked as no longer in use, discard it from the buffers. + */ + if((ret == 0) && (!fAllocated)) + { + ret = RedBufferDiscardRange(ulBlock, 1U); + CRITICAL_ASSERT(ret == 0); + } + + /* Adjust the free/almost free block count if the block was allocable. + Discard the block if required. + */ + if((ret == 0) && (ulBlock >= gpRedCoreVol->ulFirstAllocableBN)) + { + if(fAllocated) + { + gpRedMR->ulFreeBlocks--; + } + else + { + bool fWasAllocated; + + /* Whether the block became free or almost free depends on its + previous allocation state. If it was used, then it is now + almost free. Otherwise, it was new and is now free. + */ + ret = RedImapBlockGet(1U - gpRedCoreVol->bCurMR, ulBlock, &fWasAllocated); + CRITICAL_ASSERT(ret == 0); + + if(ret == 0) + { + if(fWasAllocated) + { + gpRedCoreVol->ulAlmostFreeBlocks++; + } + else + { + gpRedMR->ulFreeBlocks++; + } + } + } + } + + return ret; +} + + +/** @brief Allocate one block. + + @param pulBlock On successful return, populated with the allocated block + number. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p pulBlock is `NULL`. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENOSPC Insufficient free space to perform the allocation. +*/ +REDSTATUS RedImapAllocBlock( + uint32_t *pulBlock) +{ + REDSTATUS ret; + + if(pulBlock == NULL) + { + REDERROR(); + ret = -RED_EINVAL; + } + else if(gpRedMR->ulFreeBlocks == 0U) + { + ret = -RED_ENOSPC; + } + else + { + uint32_t ulStopBlock = gpRedMR->ulAllocNextBlock; + bool fAllocated = false; + + do + { + ALLOCSTATE state; + + ret = RedImapBlockState(gpRedMR->ulAllocNextBlock, &state); + CRITICAL_ASSERT(ret == 0); + + if(ret == 0) + { + if(state == ALLOCSTATE_FREE) + { + ret = RedImapBlockSet(gpRedMR->ulAllocNextBlock, true); + CRITICAL_ASSERT(ret == 0); + + *pulBlock = gpRedMR->ulAllocNextBlock; + fAllocated = true; + } + + /* Increment the next block number, wrapping it when the end of + the volume is reached. + */ + gpRedMR->ulAllocNextBlock++; + if(gpRedMR->ulAllocNextBlock == gpRedVolume->ulBlockCount) + { + gpRedMR->ulAllocNextBlock = gpRedCoreVol->ulFirstAllocableBN; + } + } + } + while((ret == 0) && !fAllocated && (gpRedMR->ulAllocNextBlock != ulStopBlock)); + + if((ret == 0) && !fAllocated) + { + /* The free block count was already determined to be non-zero, no + error occurred while looking for free blocks, but no free blocks + were found. This indicates metadata corruption. + */ + CRITICAL_ERROR(); + ret = -RED_EFUBAR; + } + } + + return ret; +} +#endif /* REDCONF_READ_ONLY == 0 */ + + +/** @brief Get the allocation state of a block. + + Takes into account the allocation bits from both metaroots, and returns one + of four possible allocation state values: + + - ::ALLOCSTATE_FREE Free and may be allocated; writeable. + - ::ALLOCSTATE_USED In-use and transacted; not writeable. + - ::ALLOCSTATE_NEW In-use but not transacted; writeable. + - ::ALLOCSTATE_AFREE Will become free after a transaction; not writeable. + + @param ulBlock The block number to query. + @param pState On successful return, populated with the state of the block. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p ulBlock is out of range; or @p pState is `NULL`. + @retval -RED_EIO A disk I/O error occurred. +*/ +REDSTATUS RedImapBlockState( + uint32_t ulBlock, + ALLOCSTATE *pState) +{ + REDSTATUS ret; + + if( (ulBlock < gpRedCoreVol->ulInodeTableStartBN) + || (ulBlock >= gpRedVolume->ulBlockCount) + || (pState == NULL)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + bool fBitCurrent; + + ret = RedImapBlockGet(gpRedCoreVol->bCurMR, ulBlock, &fBitCurrent); + + if(ret == 0) + { + bool fBitOld; + + ret = RedImapBlockGet(1U - gpRedCoreVol->bCurMR, ulBlock, &fBitOld); + + if(ret == 0) + { + if(fBitCurrent) + { + if(fBitOld) + { + *pState = ALLOCSTATE_USED; + } + else + { + *pState = ALLOCSTATE_NEW; + } + } + else + { + if(fBitOld) + { + *pState = ALLOCSTATE_AFREE; + } + else + { + *pState = ALLOCSTATE_FREE; + } + } + } + } + } + + return ret; +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/imapextern.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/imapextern.c new file mode 100644 index 0000000..67fab47 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/imapextern.c @@ -0,0 +1,316 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements routines for the external imap. + + The external imap is used on volumes that are too big for the imap bitmap + to be stored entirely in the metaroot, so instead the bitmap is stored in + imap nodes on disk, and the metaroot bitmap is used to toggle between imap + nodes. +*/ +#include + +#if REDCONF_IMAP_EXTERNAL == 1 + +#include + + +#if REDCONF_READ_ONLY == 0 +static REDSTATUS ImapNodeBranch(uint32_t ulImapNode, IMAPNODE **ppImap); +static bool ImapNodeIsBranched(uint32_t ulImapNode); +#endif + + +/** @brief Get the allocation bit of a block from the imap as it exists in + either metaroot. + + @param bMR The metaroot index: either 0 or 1. + @param ulBlock The block number to query. + @param pfAllocated On successful exit, populated with the allocation bit + of the block. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p bMR is out of range; or @p ulBlock is out of range; + or @p pfAllocated is `NULL`. + @retval -RED_EIO A disk I/O error occurred. +*/ +REDSTATUS RedImapEBlockGet( + uint8_t bMR, + uint32_t ulBlock, + bool *pfAllocated) +{ + REDSTATUS ret; + + if( gpRedCoreVol->fImapInline + || (bMR > 1U) + || (ulBlock < gpRedCoreVol->ulInodeTableStartBN) + || (ulBlock >= gpRedVolume->ulBlockCount) + || (pfAllocated == NULL)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + uint32_t ulOffset = ulBlock - gpRedCoreVol->ulInodeTableStartBN; + uint32_t ulImapNode = ulOffset / IMAPNODE_ENTRIES; + uint8_t bMRToRead = bMR; + IMAPNODE *pImap; + + #if REDCONF_READ_ONLY == 0 + /* If the imap node is not branched, then both copies of the imap are + identical. If the old metaroot copy is requested, use the current + copy instead, since it is more likely to be buffered. + */ + if(bMR == (1U - gpRedCoreVol->bCurMR)) + { + if(!ImapNodeIsBranched(ulImapNode)) + { + bMRToRead = 1U - bMR; + } + } + #endif + + ret = RedBufferGet(RedImapNodeBlock(bMRToRead, ulImapNode), BFLAG_META_IMAP, CAST_VOID_PTR_PTR(&pImap)); + + if(ret == 0) + { + *pfAllocated = RedBitGet(pImap->abEntries, ulOffset % IMAPNODE_ENTRIES); + + RedBufferPut(pImap); + } + } + + return ret; +} + + +#if REDCONF_READ_ONLY == 0 +/** @brief Set the allocation bit of a block in the working-state imap. + + @param ulBlock The block number to allocate or free. + @param fAllocated Whether to allocate the block (true) or free it (false). + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p ulBlock is out of range. + @retval -RED_EIO A disk I/O error occurred. +*/ +REDSTATUS RedImapEBlockSet( + uint32_t ulBlock, + bool fAllocated) +{ + REDSTATUS ret; + + if( gpRedCoreVol->fImapInline + || (ulBlock < gpRedCoreVol->ulInodeTableStartBN) + || (ulBlock >= gpRedVolume->ulBlockCount)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + uint32_t ulOffset = ulBlock - gpRedCoreVol->ulInodeTableStartBN; + uint32_t ulImapNode = ulOffset / IMAPNODE_ENTRIES; + IMAPNODE *pImap; + + ret = ImapNodeBranch(ulImapNode, &pImap); + + if(ret == 0) + { + uint32_t ulImapEntry = ulOffset % IMAPNODE_ENTRIES; + + if(RedBitGet(pImap->abEntries, ulImapEntry) == fAllocated) + { + /* The driver shouldn't ever set a bit in the imap to its + current value. That shouldn't ever be needed, and it + indicates that the driver is doing unnecessary I/O, or + that the imap is corrupt. + */ + CRITICAL_ERROR(); + ret = -RED_EFUBAR; + } + else if(fAllocated) + { + RedBitSet(pImap->abEntries, ulImapEntry); + } + else + { + RedBitClear(pImap->abEntries, ulImapEntry); + } + + RedBufferPut(pImap); + } + } + + return ret; +} + + +/** @brief Branch an imap node and get a buffer for it. + + If the imap node is already branched, it can be overwritten in its current + location, and this function just gets it buffered dirty. If the node is not + already branched, the metaroot must be updated to toggle the imap node to + its alternate location, thereby preserving the committed state copy of the + imap node. + + @param ulImapNode The imap node to branch and buffer. + @param ppImap On successful return, populated with the imap node + buffer, which will be marked dirty. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p ulImapNode is out of range; or @p ppImap is `NULL`. + @retval -RED_EIO A disk I/O error occurred. +*/ +static REDSTATUS ImapNodeBranch( + uint32_t ulImapNode, + IMAPNODE **ppImap) +{ + REDSTATUS ret; + + if((ulImapNode >= gpRedCoreVol->ulImapNodeCount) || (ppImap == NULL)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else if(ImapNodeIsBranched(ulImapNode)) + { + /* Imap node is already branched, so just get it buffered dirty. + */ + ret = RedBufferGet(RedImapNodeBlock(gpRedCoreVol->bCurMR, ulImapNode), BFLAG_META_IMAP | BFLAG_DIRTY, CAST_VOID_PTR_PTR(ppImap)); + } + else + { + uint32_t ulBlockCurrent; + uint32_t ulBlockOld; + + /* The metaroot currently points to the committed state imap node. + Toggle the metaroot to point at the alternate, writeable location. + */ + if(RedBitGet(gpRedMR->abEntries, ulImapNode)) + { + RedBitClear(gpRedMR->abEntries, ulImapNode); + } + else + { + RedBitSet(gpRedMR->abEntries, ulImapNode); + } + + ulBlockCurrent = RedImapNodeBlock(gpRedCoreVol->bCurMR, ulImapNode); + ulBlockOld = RedImapNodeBlock(1U - gpRedCoreVol->bCurMR, ulImapNode); + + ret = RedBufferDiscardRange(ulBlockCurrent, 1U); + + /* Buffer the committed copy then reassign the block number to the + writeable location. This also dirties the buffer. + */ + if(ret == 0) + { + ret = RedBufferGet(ulBlockOld, BFLAG_META_IMAP, CAST_VOID_PTR_PTR(ppImap)); + + if(ret == 0) + { + RedBufferBranch(*ppImap, ulBlockCurrent); + } + } + } + + return ret; +} + + +/** @brief Determine whether an imap node is branched. + + If the imap node is branched, it can be overwritten in its current location. + + @param ulImapNode The imap node to examine. + + @return Whether the imap node is branched. +*/ +static bool ImapNodeIsBranched( + uint32_t ulImapNode) +{ + bool fNodeBitSetInMetaroot0 = RedBitGet(gpRedCoreVol->aMR[0U].abEntries, ulImapNode); + bool fNodeBitSetInMetaroot1 = RedBitGet(gpRedCoreVol->aMR[1U].abEntries, ulImapNode); + + /* If the imap node is not branched, both metaroots will point to the same + copy of the node. + */ + return fNodeBitSetInMetaroot0 != fNodeBitSetInMetaroot1; +} +#endif /* REDCONF_READ_ONLY == 0 */ + + +/** @brief Calculate the block number of the imap node location indicated by the + given metaroot. + + An imap node has two locations on disk. A bit in the metaroot bitmap + indicates which location is the valid one, according to that metaroot. This + function returns the block number of the imap node which is valid in the + given metaroot. + + @param bMR Which metaroot to examine. + @param ulImapNode The imap node for which to calculate the block number. + + @return Block number of the imap node, as indicated by the given metaroot. +*/ +uint32_t RedImapNodeBlock( + uint8_t bMR, + uint32_t ulImapNode) +{ + uint32_t ulBlock; + + REDASSERT(ulImapNode < gpRedCoreVol->ulImapNodeCount); + + ulBlock = gpRedCoreVol->ulImapStartBN + (ulImapNode * 2U); + + if(bMR > 1U) + { + REDERROR(); + } + else if(RedBitGet(gpRedCoreVol->aMR[bMR].abEntries, ulImapNode)) + { + /* Bit is set, so point ulBlock at the second copy of the node. + */ + ulBlock++; + } + else + { + /* ulBlock already points at the first copy of the node. + */ + } + + return ulBlock; +} + +#endif /* REDCONF_IMAP_EXTERNAL == 1 */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/imapinline.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/imapinline.c new file mode 100644 index 0000000..0171ae7 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/imapinline.c @@ -0,0 +1,133 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements routines for the inline imap. + + The inline imap is used on volumes that are small enough for the imap bitmap + to be entirely contained within the metaroot. +*/ +#include + +#if REDCONF_IMAP_INLINE == 1 + +#include + + +/** @brief Get the allocation bit of a block from either metaroot. + + @param bMR The metaroot index: either 0 or 1. + @param ulBlock The block number to query. + @param pfAllocated On successful return, populated with the allocation bit + of the block. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p bMR is out of range; or @p ulBlock is out of range; + @p pfAllocated is `NULL`; or the current volume does not + use the inline imap. +*/ +REDSTATUS RedImapIBlockGet( + uint8_t bMR, + uint32_t ulBlock, + bool *pfAllocated) +{ + REDSTATUS ret; + + if( (!gpRedCoreVol->fImapInline) + || (bMR > 1U) + || (ulBlock < gpRedCoreVol->ulInodeTableStartBN) + || (ulBlock >= gpRedVolume->ulBlockCount) + || (pfAllocated == NULL)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + *pfAllocated = RedBitGet(gpRedCoreVol->aMR[bMR].abEntries, ulBlock - gpRedCoreVol->ulInodeTableStartBN); + ret = 0; + } + + return ret; +} + + +#if REDCONF_READ_ONLY == 0 +/** @brief Set the allocation bit of a block in the working metaroot. + + @param ulBlock The block number to allocate or free. + @param fAllocated Whether to allocate the block (true) or free it (false). + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p ulBlock is out of range; or the current volume does + not use the inline imap. +*/ +REDSTATUS RedImapIBlockSet( + uint32_t ulBlock, + bool fAllocated) +{ + REDSTATUS ret; + + if( (!gpRedCoreVol->fImapInline) + || (ulBlock < gpRedCoreVol->ulInodeTableStartBN) + || (ulBlock >= gpRedVolume->ulBlockCount)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + uint32_t ulOffset = ulBlock - gpRedCoreVol->ulInodeTableStartBN; + + if(RedBitGet(gpRedMR->abEntries, ulOffset) == fAllocated) + { + /* The driver shouldn't ever set a bit in the imap to its current + value. This is more of a problem with the external imap, but it + is checked here for consistency. + */ + CRITICAL_ERROR(); + ret = -RED_EFUBAR; + } + else if(fAllocated) + { + RedBitSet(gpRedMR->abEntries, ulOffset); + ret = 0; + } + else + { + RedBitClear(gpRedMR->abEntries, ulOffset); + ret = 0; + } + } + + return ret; +} +#endif + +#endif /* REDCONF_IMAP_INLINE == 1 */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/inode.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/inode.c new file mode 100644 index 0000000..c8c7682 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/inode.c @@ -0,0 +1,1120 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements inode functions. +*/ +#include +#include + + +#if REDCONF_READ_ONLY == 0 +static REDSTATUS InodeIsBranched(uint32_t ulInode, bool *pfIsBranched); +#endif +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) +static REDSTATUS InodeFindFree(uint32_t *pulInode); +#endif +#if REDCONF_READ_ONLY == 0 +static REDSTATUS InodeGetWriteableCopy(uint32_t ulInode, uint8_t *pbWhich); +#endif +static REDSTATUS InodeGetCurrentCopy(uint32_t ulInode, uint8_t *pbWhich); +#if REDCONF_READ_ONLY == 0 +static REDSTATUS InodeBitSet(uint32_t ulInode, uint8_t bWhich, bool fAllocated); +#endif +static uint32_t InodeBlock(uint32_t ulInode, uint8_t bWhich); + + +/** @brief Mount an existing inode. + + Will populate all fields of the cached inode structure, except those which + are populated during seek. + + @param pInode A pointer to the cached inode structure. The + pInode->ulInode field must already be initialized with the + inode number to mount. All other fields will be discarded. + @param type The expected inode type. + @param fBranch Whether to branch the inode. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL Invalid parameters. + @retval -RED_EROFS @p fBranch is true but the driver is read-only. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EBADF The inode number is free; or the inode number is not + valid. + @retval -RED_EISDIR @p type is ::FTYPE_FILE and the inode is a directory. + @retval -RED_ENOTDIR @p type is ::FTYPE_DIR and the inode is a file. +*/ +REDSTATUS RedInodeMount( + CINODE *pInode, + FTYPE type, + bool fBranch) +{ + REDSTATUS ret = 0; + + if(pInode == NULL) + { + ret = -RED_EINVAL; + } + else if(!INODE_IS_VALID(pInode->ulInode)) + { + ret = -RED_EBADF; + } + #if REDCONF_API_FSE == 1 + else if(type == FTYPE_DIR) + { + REDERROR(); + ret = -RED_EINVAL; + } + #endif + #if REDCONF_READ_ONLY == 1 + else if(fBranch) + { + REDERROR(); + ret = -RED_EROFS; + } + #endif + else + { + uint32_t ulInode = pInode->ulInode; + uint8_t bWhich = 0U; /* Init'd to quiet warnings. */ + + RedMemSet(pInode, 0U, sizeof(*pInode)); + pInode->ulInode = ulInode; + + ret = InodeGetCurrentCopy(pInode->ulInode, &bWhich); + + if(ret == 0) + { + ret = RedBufferGet(InodeBlock(pInode->ulInode, bWhich), BFLAG_META_INODE, CAST_VOID_PTR_PTR(&pInode->pInodeBuf)); + } + + #if REDCONF_READ_ONLY == 0 + if(ret == 0) + { + ret = InodeIsBranched(pInode->ulInode, &pInode->fBranched); + } + #endif + + if(ret == 0) + { + if(RED_S_ISREG(pInode->pInodeBuf->uMode)) + { + #if REDCONF_API_POSIX == 1 + pInode->fDirectory = false; + + if(type == FTYPE_DIR) + { + ret = -RED_ENOTDIR; + } + #endif + } + #if REDCONF_API_POSIX == 1 + else if(RED_S_ISDIR(pInode->pInodeBuf->uMode)) + { + pInode->fDirectory = true; + + if(type == FTYPE_FILE) + { + ret = -RED_EISDIR; + } + } + #endif + else + { + /* Missing or unsupported inode type. + */ + CRITICAL_ERROR(); + ret = -RED_EFUBAR; + } + } + + #if REDCONF_READ_ONLY == 0 + if((ret == 0) && fBranch) + { + ret = RedInodeBranch(pInode); + } + #endif + + if(ret != 0) + { + RedInodePut(pInode, 0U); + } + } + + return ret; +} + + +#if (REDCONF_READ_ONLY == 0) && ((REDCONF_API_POSIX == 1) || FORMAT_SUPPORTED) +/** @brief Create an inode. + + @param pInode Pointer to the cached inode structure. If pInode->ulInode + is #INODE_INVALID, a free inode will be found; otherwise, + pInode->ulInode will be the inode number (an error will be + returned if it is not free). + @param ulPInode The parent inode number. + @param uMode The inode mode. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBADF pInode->ulInode is an invalid inode number other than + #INODE_INVALID. + @retval -RED_EINVAL Invalid parameters. + @retval -RED_EEXIST Tried to create an inode with an inode number that is + already in use. + @retval -RED_ENFILE All inode slots are already in use. + @retval -RED_EIO A disk I/O error occurred. +*/ +REDSTATUS RedInodeCreate( + CINODE *pInode, + uint32_t ulPInode, + uint16_t uMode) +{ + REDSTATUS ret; + + #if REDCONF_API_POSIX == 1 + /* ulPInode must be a valid inode number, unless we are creating the root + directory, in which case ulPInode must be INODE_INVALID (the root + directory has no parent). + */ + if( (pInode == NULL) + || (!INODE_IS_VALID(ulPInode) && ((ulPInode != INODE_INVALID) || (pInode->ulInode != INODE_ROOTDIR)))) + #else + if(pInode == NULL) + #endif + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + uint32_t ulInode = pInode->ulInode; + + RedMemSet(pInode, 0U, sizeof(*pInode)); + + #if REDCONF_API_POSIX == 1 + if(ulInode == INODE_INVALID) + { + /* Caller requested that an inode number be allocated. Search for + an unused inode number, error if there isn't one. + */ + ret = InodeFindFree(&pInode->ulInode); + } + else + #endif + { + /* Caller requested creation of a specific inode number. Make sure + it's valid and doesn't already exist. + */ + if(INODE_IS_VALID(ulInode)) + { + bool fFree; + + ret = RedInodeIsFree(ulInode, &fFree); + if(ret == 0) + { + if(fFree) + { + pInode->ulInode = ulInode; + } + else + { + ret = -RED_EEXIST; + } + } + } + else + { + ret = -RED_EBADF; + } + } + + if(ret == 0) + { + uint8_t bWriteableWhich; + + ret = InodeGetWriteableCopy(pInode->ulInode, &bWriteableWhich); + + if(ret == 0) + { + ret = RedBufferGet(InodeBlock(pInode->ulInode, bWriteableWhich), + (uint16_t)((uint32_t)BFLAG_META_INODE | BFLAG_DIRTY | BFLAG_NEW), CAST_VOID_PTR_PTR(&pInode->pInodeBuf)); + + if(ret == 0) + { + /* Mark the inode block as allocated. + */ + ret = InodeBitSet(pInode->ulInode, bWriteableWhich, true); + + if(ret != 0) + { + RedBufferPut(pInode->pInodeBuf); + } + } + } + } + + if(ret == 0) + { + #if REDCONF_INODE_TIMESTAMPS == 1 + uint32_t ulNow = RedOsClockGetTime(); + + pInode->pInodeBuf->ulATime = ulNow; + pInode->pInodeBuf->ulMTime = ulNow; + pInode->pInodeBuf->ulCTime = ulNow; + #endif + + pInode->pInodeBuf->uMode = uMode; + + #if REDCONF_API_POSIX == 1 + #if REDCONF_API_POSIX_LINK == 1 + pInode->pInodeBuf->uNLink = 1U; + #endif + pInode->pInodeBuf->ulPInode = ulPInode; + #else + (void)ulPInode; + #endif + + pInode->fBranched = true; + pInode->fDirty = true; + + #if REDCONF_API_POSIX == 1 + gpRedMR->ulFreeInodes--; + #endif + } + } + + return ret; +} +#endif /* (REDCONF_READ_ONLY == 0) && ((REDCONF_API_POSIX == 1) || FORMAT_SUPPORTED) */ + + +#if DELETE_SUPPORTED +/** @brief Delete an inode. + + @param pInode Pointer to the cached inode structure. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBADF The inode is free. + @retval -RED_EINVAL @p pInode is `NULL`; or pInode->pBuffer is `NULL`. + @retval -RED_EIO A disk I/O error occurred. +*/ +REDSTATUS RedInodeDelete( + CINODE *pInode) +{ + REDSTATUS ret = 0; + + if(!CINODE_IS_MOUNTED(pInode)) + { + ret = -RED_EINVAL; + } + else + { + if(pInode->pInodeBuf->ullSize != 0U) + { + ret = RedInodeDataTruncate(pInode, UINT64_SUFFIX(0)); + } + + if(ret == 0) + { + ret = RedInodeFree(pInode); + } + } + + return ret; +} + + +/** @brief Decrement an inode link count and delete the inode if the link count + falls to zero. + + @param pInode A pointer to the cached inode structure. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p pInode is not a mounted cachde inode. + @retval -RED_EIO A disk I/O error occurred. +*/ +REDSTATUS RedInodeLinkDec( + CINODE *pInode) +{ + REDSTATUS ret; + + if(!CINODE_IS_MOUNTED(pInode)) + { + ret = -RED_EINVAL; + } + #if REDCONF_API_POSIX_LINK == 1 + else if(pInode->pInodeBuf->uNLink > 1U) + { + ret = RedInodeBranch(pInode); + + if(ret == 0) + { + pInode->pInodeBuf->uNLink--; + } + } + #endif + else + { + ret = RedInodeDelete(pInode); + } + + return ret; +} +#endif /* DELETE_SUPPORTED */ + + +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) +/** @brief Free an inode. + + @param pInode Pointer to the cached inode structure. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBADF The inode is free. + @retval -RED_EINVAL @p pInode is `NULL`; or pInode->pBuffer is `NULL`. + @retval -RED_EIO A disk I/O error occurred. +*/ +REDSTATUS RedInodeFree( + CINODE *pInode) +{ + REDSTATUS ret; + + if(!CINODE_IS_MOUNTED(pInode)) + { + ret = -RED_EINVAL; + } + else + { + bool fSlot0Allocated; + + RedBufferDiscard(pInode->pInodeBuf); + pInode->pInodeBuf = NULL; + + /* Determine which of the two slots for the inode is currently + allocated, and free that slot. + */ + ret = RedInodeBitGet(gpRedCoreVol->bCurMR, pInode->ulInode, 0U, &fSlot0Allocated); + + if(ret == 0) + { + bool fSlot1Allocated; + + ret = RedInodeBitGet(gpRedCoreVol->bCurMR, pInode->ulInode, 1U, &fSlot1Allocated); + + if(ret == 0) + { + if(fSlot0Allocated) + { + if(fSlot1Allocated) + { + /* Both inode slots should never be allocated at + the same time. + */ + CRITICAL_ERROR(); + ret = -RED_EFUBAR; + } + else + { + ret = InodeBitSet(pInode->ulInode, 0U, false); + } + } + else + { + if(!fSlot1Allocated) + { + /* The inode in unallocated, which should have been + caught when it was mounted. + */ + CRITICAL_ERROR(); + ret = -RED_EBADF; + } + else + { + ret = InodeBitSet(pInode->ulInode, 1U, false); + } + } + } + } + + pInode->ulInode = INODE_INVALID; + + if(ret == 0) + { + if(gpRedMR->ulFreeInodes >= gpRedVolConf->ulInodeCount) + { + CRITICAL_ERROR(); + ret = -RED_EFUBAR; + } + else + { + gpRedMR->ulFreeInodes++; + } + } + } + + return ret; +} +#endif /* (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) */ + + +/** @brief Put the cached inode structure. + + This puts all of the buffers in the ::CINODE structure. Also updates inode + timestamp fields if requested. + + @param pInode The cached inode structure. + @param bTimeFields The inode timestamp fields to update. +*/ +void RedInodePut( + CINODE *pInode, + uint8_t bTimeFields) +{ + if(pInode == NULL) + { + REDERROR(); + } + else + { + RedInodePutCoord(pInode); + + if(pInode->pInodeBuf != NULL) + { + #if (REDCONF_READ_ONLY == 0) && (REDCONF_INODE_TIMESTAMPS == 1) + if((bTimeFields & IPUT_UPDATE_MASK) != 0U) + { + if(!pInode->fBranched || !pInode->fDirty) + { + REDERROR(); + } + else + { + uint32_t ulNow = RedOsClockGetTime(); + + #if REDCONF_ATIME == 1 + if((bTimeFields & IPUT_UPDATE_ATIME) != 0U) + { + pInode->pInodeBuf->ulATime = ulNow; + } + #endif + + if((bTimeFields & IPUT_UPDATE_MTIME) != 0U) + { + pInode->pInodeBuf->ulMTime = ulNow; + } + + if((bTimeFields & IPUT_UPDATE_CTIME) != 0U) + { + pInode->pInodeBuf->ulCTime = ulNow; + } + } + } + #else + (void)bTimeFields; + #endif + + RedBufferPut(pInode->pInodeBuf); + pInode->pInodeBuf = NULL; + } + } +} + + +/** @brief Put all buffers in the cached inode structure except for the inode + node buffer. + + @param pInode A pointer to the cached inode structure. +*/ +void RedInodePutCoord( + CINODE *pInode) +{ + if(pInode == NULL) + { + REDERROR(); + } + else + { + RedInodePutData(pInode); + #if REDCONF_DIRECT_POINTERS < INODE_ENTRIES + RedInodePutIndir(pInode); + #endif + #if DINDIR_POINTERS > 0U + RedInodePutDindir(pInode); + #endif + } +} + + +#if DINDIR_POINTERS > 0U +/** @brief Put the double indirect buffer. + + @param pInode A pointer to the cached inode structure. +*/ +void RedInodePutDindir( + CINODE *pInode) +{ + if(pInode == NULL) + { + REDERROR(); + } + else if(pInode->pDindir != NULL) + { + RedBufferPut(pInode->pDindir); + pInode->pDindir = NULL; + } + else + { + /* No double indirect buffer, nothing to put. + */ + } +} +#endif + + +#if REDCONF_DIRECT_POINTERS < INODE_ENTRIES +/** @brief Put the indirect buffer. + + @param pInode A pointer to the cached inode structure. +*/ +void RedInodePutIndir( + CINODE *pInode) +{ + if(pInode == NULL) + { + REDERROR(); + } + else if(pInode->pIndir != NULL) + { + RedBufferPut(pInode->pIndir); + pInode->pIndir = NULL; + } + else + { + /* No indirect buffer, nothing to put. + */ + } +} +#endif + + +/** @brief Put the inode data buffer. + + @param pInode A pointer to the cached inode structure. +*/ +void RedInodePutData( + CINODE *pInode) +{ + if(pInode == NULL) + { + REDERROR(); + } + else if(pInode->pbData != NULL) + { + RedBufferPut(pInode->pbData); + pInode->pbData = NULL; + } + else + { + /* No data buffer, nothing to put. + */ + } +} + + +#if REDCONF_READ_ONLY == 0 +/** @brief Determine if an inode is branched. + + @param ulInode The inode number to examine. + @param pfIsBranched On successful return, populated with whether the inode + is branched. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p pInode is `NULL`; or @p ulInode is not a valid inode + number. + @retval -RED_EIO A disk I/O error occurred. +*/ +static REDSTATUS InodeIsBranched( + uint32_t ulInode, + bool *pfIsBranched) +{ + REDSTATUS ret; + + if(!INODE_IS_VALID(ulInode) || (pfIsBranched == NULL)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + ALLOCSTATE state; + + ret = RedImapBlockState(InodeBlock(ulInode, 0U), &state); + + if(ret == 0) + { + if(state == ALLOCSTATE_NEW) + { + *pfIsBranched = true; + } + else + { + ret = RedImapBlockState(InodeBlock(ulInode, 1U), &state); + + if(ret == 0) + { + if(state == ALLOCSTATE_NEW) + { + *pfIsBranched = true; + } + else + { + *pfIsBranched = false; + } + } + } + } + } + + return ret; +} + + +/** @brief Branch an inode. + + A branched inode is one in which the allocation state for one copy is free + or almost free, and the other copy is in the new state. The copy which is + in the new state is the writeable copy, which is also buffered and dirty. + + @param pInode Pointer to the cached inode structure which has already been + mounted. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL Invalid parameters. + @retval -RED_EIO A disk I/O error occurred. +*/ +REDSTATUS RedInodeBranch( + CINODE *pInode) +{ + REDSTATUS ret; + + if(!CINODE_IS_MOUNTED(pInode)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else if(!pInode->fBranched) + { + uint8_t bWhich; + + ret = InodeGetWriteableCopy(pInode->ulInode, &bWhich); + + if(ret == 0) + { + RedBufferBranch(pInode->pInodeBuf, InodeBlock(pInode->ulInode, bWhich)); + pInode->fBranched = true; + pInode->fDirty = true; + } + + /* Toggle the inode slots: the old slot block becomes almost free + (still used by the committed state) and the new slot block becomes + new. + */ + if(ret == 0) + { + ret = InodeBitSet(pInode->ulInode, 1U - bWhich, false); + } + + if(ret == 0) + { + ret = InodeBitSet(pInode->ulInode, bWhich, true); + } + + CRITICAL_ASSERT(ret == 0); + } + else + { + RedBufferDirty(pInode->pInodeBuf); + pInode->fDirty = true; + ret = 0; + } + + return ret; +} +#endif /* REDCONF_READ_ONLY == 0 */ + + +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) +/** @brief Find a free inode number. + + @param pulInode On successful return, populated with a free inode number. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p pulInode is `NULL`. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENFILE No available inode numbers. +*/ +static REDSTATUS InodeFindFree( + uint32_t *pulInode) +{ + REDSTATUS ret; + + if(pulInode == NULL) + { + REDERROR(); + ret = -RED_EINVAL; + } + else if(gpRedMR->ulFreeInodes == 0U) + { + ret = -RED_ENFILE; + } + else + { + uint32_t ulInode; + + ret = 0; + + for(ulInode = INODE_FIRST_FREE; ulInode < (INODE_FIRST_VALID + gpRedVolConf->ulInodeCount); ulInode++) + { + bool fFree; + + ret = RedInodeIsFree(ulInode, &fFree); + + if((ret != 0) || fFree) + { + break; + } + } + + if(ret == 0) + { + if(ulInode < (INODE_FIRST_VALID + gpRedVolConf->ulInodeCount)) + { + *pulInode = ulInode; + } + else + { + /* If gpRedMR->ulFreeInodes > 0, we should have found an inode. + */ + CRITICAL_ERROR(); + ret = -RED_ENFILE; + } + } + } + + return ret; +} +#endif + + +#if ((REDCONF_READ_ONLY == 0) && ((REDCONF_API_POSIX == 1) || FORMAT_SUPPORTED)) || (REDCONF_CHECKER == 1) +/** @brief Determine whether an inode number is available. + + @param ulInode The node number to examine. + @param pfFree On successful return, populated with whether the inode + number is available (true) or in use (false). + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p pfFree is `NULL`; or @p ulInode is not a valid inode + number. + @retval -RED_EIO A disk I/O error occurred. +*/ +REDSTATUS RedInodeIsFree( + uint32_t ulInode, + bool *pfFree) +{ + REDSTATUS ret; + + if(pfFree == NULL) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + bool fSlot0Allocated; + + *pfFree = false; + + ret = RedInodeBitGet(gpRedCoreVol->bCurMR, ulInode, 0U, &fSlot0Allocated); + if((ret == 0) && !fSlot0Allocated) + { + bool fSlot1Allocated; + + ret = RedInodeBitGet(gpRedCoreVol->bCurMR, ulInode, 1U, &fSlot1Allocated); + if((ret == 0) && !fSlot1Allocated) + { + *pfFree = true; + } + } + } + + return ret; +} +#endif + + +#if REDCONF_READ_ONLY == 0 +/** @brief Determine which copy of the inode is currently writeable. + + @param ulInode The inode number to examine. + @param pbWhich On successful return, populated with which copy of the inode + (either 0 or 1) is writeable. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p pbWhich is `NULL`; or ulInode is not a valid inode + number. + @retval -RED_EIO A disk I/O error occurred. +*/ +static REDSTATUS InodeGetWriteableCopy( + uint32_t ulInode, + uint8_t *pbWhich) +{ + REDSTATUS ret; + + if(pbWhich == NULL) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + bool fSlot0Allocated; + + /* The writeable inode slot is the one which is free in the committed + state, so query the committed state metaroot. + */ + ret = RedInodeBitGet(1U - gpRedCoreVol->bCurMR, ulInode, 0U, &fSlot0Allocated); + + if(ret == 0) + { + if(!fSlot0Allocated) + { + *pbWhich = 0U; + } + else + { + bool fSlot1Allocated; + + ret = RedInodeBitGet(1U - gpRedCoreVol->bCurMR, ulInode, 1U, &fSlot1Allocated); + + if(ret == 0) + { + if(!fSlot1Allocated) + { + *pbWhich = 1U; + } + else + { + /* Both inode slots were allocated, which should never + happen. + */ + CRITICAL_ERROR(); + ret = -RED_EFUBAR; + } + } + } + } + } + + return ret; +} +#endif + + +/** @brief Determine which copy of the inode is current. + + @param ulInode The inode number to examine. + @param pbWhich On successful return, populated with which copy of the inode + (either 0 or 1) is current. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBADF @p ulInode is an unallocated inode number. + @retval -RED_EINVAL @p pbWhich is `NULL`; or ulInode is not a valid inode + number. + @retval -RED_EIO A disk I/O error occurred. +*/ +static REDSTATUS InodeGetCurrentCopy( + uint32_t ulInode, + uint8_t *pbWhich) +{ + REDSTATUS ret; + + if(pbWhich == NULL) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + bool fSlot0Allocated; + + /* The current inode slot is the one which is allocated in the working + state metaroot. + */ + ret = RedInodeBitGet(gpRedCoreVol->bCurMR, ulInode, 0U, &fSlot0Allocated); + if(ret == 0) + { + if(fSlot0Allocated) + { + *pbWhich = 0U; + } + else + { + bool fSlot1Allocated; + + ret = RedInodeBitGet(gpRedCoreVol->bCurMR, ulInode, 1U, &fSlot1Allocated); + if(ret == 0) + { + if(fSlot1Allocated) + { + *pbWhich = 1U; + } + else + { + /* Neither slot for this inode was allocated, so the + inode is actually free. + */ + ret = -RED_EBADF; + } + } + } + } + } + + return ret; +} + + +/** @brief Get whether a copy of an inode is allocated. + + @param bMR The metaroot index: either 0 or 1. + @param ulInode The inode number. + @param bWhich Which copy of the inode to get. + @param pfAllocated On successful return, populated with whether the given + copy of the inode is allocated. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p bMR is not 1 or 0; @p ulInode is not a valid inode + number; or @p bWhich is not 1 or 0; or @p pfAllocated is + `NULL`. + @retval -RED_EIO A disk I/O error occurred. +*/ +REDSTATUS RedInodeBitGet( + uint8_t bMR, + uint32_t ulInode, + uint8_t bWhich, + bool *pfAllocated) +{ + REDSTATUS ret; + + if(!INODE_IS_VALID(ulInode) || (bWhich > 1U)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + ret = RedImapBlockGet(bMR, InodeBlock(ulInode, bWhich), pfAllocated); + } + + return ret; +} + + +#if REDCONF_READ_ONLY == 0 +/** @brief Set whether a copy of an inode is allocated. + + @param ulInode The inode number. + @param bWhich Which copy of the inode to set. + @param fAllocated If true, the inode is set to allocated; if false, the + inode is set to free. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p ulInode is not a valid inode number; or @p bWhich is + not 1 or 0. + @retval -RED_EIO A disk I/O error occurred. +*/ +static REDSTATUS InodeBitSet( + uint32_t ulInode, + uint8_t bWhich, + bool fAllocated) +{ + REDSTATUS ret; + + if(!INODE_IS_VALID(ulInode) || (bWhich > 1U)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + ret = RedImapBlockSet(InodeBlock(ulInode, bWhich), fAllocated); + } + + return ret; +} +#endif + + +/** @brief Determine the block number of an inode. + + @param ulInode The inode number. + @param bWhich Which copy of the inode. + + @return The block number of the inode. +*/ +static uint32_t InodeBlock( + uint32_t ulInode, + uint8_t bWhich) +{ + REDASSERT(INODE_IS_VALID(ulInode)); + REDASSERT(bWhich <= 1U); + + return gpRedCoreVol->ulInodeTableStartBN + ((ulInode - INODE_FIRST_VALID) * 2U) + bWhich; +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/inodedata.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/inodedata.c new file mode 100644 index 0000000..c311925 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/inodedata.c @@ -0,0 +1,1917 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements inode I/O functions. +*/ +#include +#include + + +/* This value is used to initialize the uIndirEntry and uDindirEntry members of + the CINODE structure. After seeking, a value of COORD_ENTRY_INVALID in + uIndirEntry indicates that there is no indirect node in the path through the + file metadata structure, and a value of COORD_ENTRY_INVALID in uDindirEntry + indicates that there is no double indirect node. +*/ +#define COORD_ENTRY_INVALID (UINT16_MAX) + +/* This enumeration is used by the BranchBlock() and BranchBlockCost() + functions to determine which blocks of the file metadata structure need to + be branched, and which to ignore. DINDIR requires requires branching the + double indirect only, INDIR requires branching the double indirect + (if present) and the indirect, and FILE_DATA requires branching the indirect + and double indirect (if present) and the file data block. +*/ +typedef enum +{ + BRANCHDEPTH_DINDIR = 0U, + BRANCHDEPTH_INDIR = 1U, + BRANCHDEPTH_FILE_DATA = 2U, + BRANCHDEPTH_MAX = BRANCHDEPTH_FILE_DATA +} BRANCHDEPTH; + + +#if REDCONF_READ_ONLY == 0 +#if DELETE_SUPPORTED || TRUNCATE_SUPPORTED +static REDSTATUS Shrink(CINODE *pInode, uint64_t ullSize); +#if DINDIR_POINTERS > 0U +static REDSTATUS TruncDindir(CINODE *pInode, bool *pfFreed); +#endif +#if REDCONF_DIRECT_POINTERS < INODE_ENTRIES +static REDSTATUS TruncIndir(CINODE *pInode, bool *pfFreed); +#endif +static REDSTATUS TruncDataBlock(const CINODE *pInode, uint32_t *pulBlock, bool fPropagate); +#endif +static REDSTATUS ExpandPrepare(CINODE *pInode); +#endif +static void SeekCoord(CINODE *pInode, uint32_t ulBlock); +static REDSTATUS ReadUnaligned(CINODE *pInode, uint64_t ullStart, uint32_t ulLen, uint8_t *pbBuffer); +static REDSTATUS ReadAligned(CINODE *pInode, uint32_t ulBlockStart, uint32_t ulBlockCount, uint8_t *pbBuffer); +#if REDCONF_READ_ONLY == 0 +static REDSTATUS WriteUnaligned(CINODE *pInode, uint64_t ullStart, uint32_t ulLen, const uint8_t *pbBuffer); +static REDSTATUS WriteAligned(CINODE *pInode, uint32_t ulBlockStart, uint32_t *pulBlockCount, const uint8_t *pbBuffer); +#endif +static REDSTATUS GetExtent(CINODE *pInode, uint32_t ulBlockStart, uint32_t *pulExtentStart, uint32_t *pulExtentLen); +#if REDCONF_READ_ONLY == 0 +static REDSTATUS BranchBlock(CINODE *pInode, BRANCHDEPTH depth, bool fBuffer); +static REDSTATUS BranchOneBlock(uint32_t *pulBlock, void **ppBuffer, uint16_t uBFlag); +static REDSTATUS BranchBlockCost(const CINODE *pInode, BRANCHDEPTH depth, uint32_t *pulCost); +static uint32_t FreeBlockCount(void); +#endif + + +/** @brief Read data from an inode. + + @param pInode A pointer to the cached inode structure of the inode from + which to read. + @param ullStart The file offset at which to read. + @param pulLen On input, the number of bytes to attempt to read. On + successful return, populated with the number of bytes + actually read. + @param pBuffer The buffer to read into. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EINVAL @p pInode is not a mounted cached inode pointer; or + @p pulLen is `NULL`; or @p pBuffer is `NULL`. +*/ +REDSTATUS RedInodeDataRead( + CINODE *pInode, + uint64_t ullStart, + uint32_t *pulLen, + void *pBuffer) +{ + REDSTATUS ret = 0; + + if(!CINODE_IS_MOUNTED(pInode) || (pulLen == NULL) || (pBuffer == NULL)) + { + ret = -RED_EINVAL; + } + else if(ullStart >= pInode->pInodeBuf->ullSize) + { + *pulLen = 0U; + } + else if(*pulLen == 0U) + { + /* Do nothing, just return success. + */ + } + else + { + uint8_t *pbBuffer = CAST_VOID_PTR_TO_UINT8_PTR(pBuffer); + uint32_t ulReadIndex = 0U; + uint32_t ulLen = *pulLen; + uint32_t ulRemaining; + + /* Reading beyond the end of the file is not allowed. If the requested + read extends beyond the end of the file, truncate the read length so + that the read stops at the end of the file. + */ + if((pInode->pInodeBuf->ullSize - ullStart) < ulLen) + { + ulLen = (uint32_t)(pInode->pInodeBuf->ullSize - ullStart); + } + + ulRemaining = ulLen; + + /* Unaligned partial block at start. + */ + if((ullStart & (REDCONF_BLOCK_SIZE - 1U)) != 0U) + { + uint32_t ulBytesInFirstBlock = REDCONF_BLOCK_SIZE - (uint32_t)(ullStart & (REDCONF_BLOCK_SIZE - 1U)); + uint32_t ulThisRead = REDMIN(ulRemaining, ulBytesInFirstBlock); + + ret = ReadUnaligned(pInode, ullStart, ulThisRead, pbBuffer); + + if(ret == 0) + { + ulReadIndex += ulThisRead; + ulRemaining -= ulThisRead; + } + } + + /* Whole blocks. + */ + if((ret == 0) && (ulRemaining >= REDCONF_BLOCK_SIZE)) + { + uint32_t ulBlockOffset = (uint32_t)((ullStart + ulReadIndex) >> BLOCK_SIZE_P2); + uint32_t ulBlockCount = ulRemaining >> BLOCK_SIZE_P2; + + REDASSERT(((ullStart + ulReadIndex) & (REDCONF_BLOCK_SIZE - 1U)) == 0U); + + ret = ReadAligned(pInode, ulBlockOffset, ulBlockCount, &pbBuffer[ulReadIndex]); + + if(ret == 0) + { + ulReadIndex += ulBlockCount << BLOCK_SIZE_P2; + ulRemaining -= ulBlockCount << BLOCK_SIZE_P2; + } + } + + /* Aligned partial block at end. + */ + if((ret == 0) && (ulRemaining > 0U)) + { + REDASSERT(ulRemaining < REDCONF_BLOCK_SIZE); + REDASSERT(((ullStart + ulReadIndex) & (REDCONF_BLOCK_SIZE - 1U)) == 0U); + + ret = ReadUnaligned(pInode, ullStart + ulReadIndex, ulRemaining, &pbBuffer[ulReadIndex]); + } + + if(ret == 0) + { + *pulLen = ulLen; + } + } + + return ret; +} + + +#if REDCONF_READ_ONLY == 0 +/** @brief Write to an inode. + + @param pInode A pointer to the cached inode structure of the inode into + which to write. + @param ullStart The file offset at which to write. + @param pulLen On input, the number of bytes to attempt to write. On + successful return, populated with the number of bytes + actually written. + @param pBuffer The buffer to write from. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EFBIG @p ullStart is greater than the maximum file size; or + @p ullStart is equal to the maximum file size and the + write length is non-zero. + @retval -RED_EINVAL @p pInode is not a mounted cached inode pointer; or + @p pulLen is `NULL`; or @p pBuffer is `NULL`. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENOSPC No data can be written because there is insufficient + free space. +*/ +REDSTATUS RedInodeDataWrite( + CINODE *pInode, + uint64_t ullStart, + uint32_t *pulLen, + const void *pBuffer) +{ + REDSTATUS ret = 0; + + if(!CINODE_IS_DIRTY(pInode) || (pulLen == NULL) || (pBuffer == NULL)) + { + ret = -RED_EINVAL; + } + else if((ullStart > INODE_SIZE_MAX) || ((ullStart == INODE_SIZE_MAX) && (*pulLen > 0U))) + { + ret = -RED_EFBIG; + } + else if(*pulLen == 0U) + { + /* Do nothing, just return success. + */ + } + else + { + const uint8_t *pbBuffer = CAST_VOID_PTR_TO_CONST_UINT8_PTR(pBuffer); + uint32_t ulWriteIndex = 0U; + uint32_t ulLen = *pulLen; + uint32_t ulRemaining; + + if((INODE_SIZE_MAX - ullStart) < ulLen) + { + ulLen = (uint32_t)(INODE_SIZE_MAX - ullStart); + } + + ulRemaining = ulLen; + + /* If the write is beyond the current end of the file, and the current + end of the file is not block-aligned, then there may be some data + that needs to be zeroed in the last block. + */ + if(ullStart > pInode->pInodeBuf->ullSize) + { + ret = ExpandPrepare(pInode); + } + + /* Partial block at start. + */ + if((ret == 0) && (((ullStart & (REDCONF_BLOCK_SIZE - 1U)) != 0U) || (ulRemaining < REDCONF_BLOCK_SIZE))) + { + uint32_t ulBytesInFirstBlock = REDCONF_BLOCK_SIZE - (uint32_t)(ullStart & (REDCONF_BLOCK_SIZE - 1U)); + uint32_t ulThisWrite = REDMIN(ulRemaining, ulBytesInFirstBlock); + + ret = WriteUnaligned(pInode, ullStart, ulThisWrite, pbBuffer); + + if(ret == 0) + { + ulWriteIndex += ulThisWrite; + ulRemaining -= ulThisWrite; + } + } + + /* Whole blocks. + */ + if((ret == 0) && (ulRemaining >= REDCONF_BLOCK_SIZE)) + { + uint32_t ulBlockOffset = (uint32_t)((ullStart + ulWriteIndex) >> BLOCK_SIZE_P2); + uint32_t ulBlockCount = ulRemaining >> BLOCK_SIZE_P2; + uint32_t ulBlocksWritten = ulBlockCount; + + REDASSERT(((ullStart + ulWriteIndex) & (REDCONF_BLOCK_SIZE - 1U)) == 0U); + + ret = WriteAligned(pInode, ulBlockOffset, &ulBlocksWritten, &pbBuffer[ulWriteIndex]); + + if((ret == -RED_ENOSPC) && (ulWriteIndex > 0U)) + { + ulBlocksWritten = 0U; + ret = 0; + } + + if(ret == 0) + { + ulWriteIndex += ulBlocksWritten << BLOCK_SIZE_P2; + ulRemaining -= ulBlocksWritten << BLOCK_SIZE_P2; + + if(ulBlocksWritten < ulBlockCount) + { + ulRemaining = 0U; + } + } + } + + /* Partial block at end. + */ + if((ret == 0) && (ulRemaining > 0U)) + { + REDASSERT(ulRemaining < REDCONF_BLOCK_SIZE); + REDASSERT(((ullStart + ulWriteIndex) & (REDCONF_BLOCK_SIZE - 1U)) == 0U); + REDASSERT(ulWriteIndex > 0U); + + ret = WriteUnaligned(pInode, ullStart + ulWriteIndex, ulRemaining, &pbBuffer[ulWriteIndex]); + + if(ret == -RED_ENOSPC) + { + ret = 0; + } + else if(ret == 0) + { + ulWriteIndex += ulRemaining; + + REDASSERT(ulWriteIndex == ulLen); + } + else + { + /* Unexpected error, return it. + */ + } + } + + if(ret == 0) + { + *pulLen = ulWriteIndex; + + if((ullStart + ulWriteIndex) > pInode->pInodeBuf->ullSize) + { + pInode->pInodeBuf->ullSize = ullStart + ulWriteIndex; + } + } + } + + return ret; +} + + +#if DELETE_SUPPORTED || TRUNCATE_SUPPORTED +/** @brief Change the size of an inode. + + @param pInode A pointer to the cached inode structure. + @praam ullSize The new file size for the inode. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EFBIG @p ullSize is greater than the maximum file size. + @retval -RED_EINVAL @p pInode is not a mounted cached inode pointer. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENOSPC Insufficient free space to perform the truncate. +*/ +REDSTATUS RedInodeDataTruncate( + CINODE *pInode, + uint64_t ullSize) +{ + REDSTATUS ret = 0; + + /* The inode does not need to be dirtied when it is being deleted, because + the inode buffer will be discarded without ever being written to disk. + Thus, we only check to see if it's mounted here. + */ + if(!CINODE_IS_MOUNTED(pInode)) + { + ret = -RED_EINVAL; + } + else if(ullSize > INODE_SIZE_MAX) + { + ret = -RED_EFBIG; + } + else + { + if(ullSize > pInode->pInodeBuf->ullSize) + { + ret = ExpandPrepare(pInode); + } + else if(ullSize < pInode->pInodeBuf->ullSize) + { + ret = Shrink(pInode, ullSize); + } + else + { + /* Size is staying the same, nothing to do. + */ + } + + if(ret == 0) + { + pInode->pInodeBuf->ullSize = ullSize; + } + } + + return ret; +} + + +/** @brief Free all file data beyond a specified point. + + @param pInode A pointer to the cached inode structure. + @param ullSize The point beyond which to free all file data. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENOSPC Insufficient free space to perform the truncate. + @retval -RED_EINVAL Invalid parameters. +*/ +static REDSTATUS Shrink( + CINODE *pInode, + uint64_t ullSize) +{ + REDSTATUS ret = 0; + + /* pInode->fDirty is checked explicitly here, instead of using the + CINODE_IS_DIRTY() macro, to avoid a duplicate mount check. + */ + if(!CINODE_IS_MOUNTED(pInode) || ((ullSize > 0U) && !pInode->fDirty)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + uint32_t ulTruncBlock = (uint32_t)((ullSize + REDCONF_BLOCK_SIZE - 1U) >> BLOCK_SIZE_P2); + + RedInodePutData(pInode); + + #if REDCONF_DIRECT_POINTERS > 0U + while(ulTruncBlock < REDCONF_DIRECT_POINTERS) + { + ret = TruncDataBlock(pInode, &pInode->pInodeBuf->aulEntries[ulTruncBlock], true); + + if(ret != 0) + { + break; + } + + ulTruncBlock++; + } + #endif + + #if REDCONF_INDIRECT_POINTERS > 0U + while((ret == 0) && (ulTruncBlock < (REDCONF_DIRECT_POINTERS + INODE_INDIR_BLOCKS))) + { + ret = RedInodeDataSeek(pInode, ulTruncBlock); + + if((ret == 0) || (ret == -RED_ENODATA)) + { + bool fFreed; + + ret = TruncIndir(pInode, &fFreed); + + if(ret == 0) + { + if(fFreed) + { + pInode->pInodeBuf->aulEntries[pInode->uInodeEntry] = BLOCK_SPARSE; + } + + /* The next seek will go to the beginning of the next + indirect. + */ + ulTruncBlock += (INDIR_ENTRIES - pInode->uIndirEntry); + } + } + } + #endif + + #if DINDIR_POINTERS > 0U + while((ret == 0) && (ulTruncBlock < INODE_DATA_BLOCKS)) + { + ret = RedInodeDataSeek(pInode, ulTruncBlock); + + if((ret == 0) || (ret == -RED_ENODATA)) + { + bool fFreed; + + /* TruncDindir() invokes seek as it goes along, which will + update the entry values (possibly all three of these); + make a copy so we can compute things correctly after. + */ + uint16_t uOrigInodeEntry = pInode->uInodeEntry; + uint16_t uOrigDindirEntry = pInode->uDindirEntry; + uint16_t uOrigIndirEntry = pInode->uIndirEntry; + + ret = TruncDindir(pInode, &fFreed); + + if(ret == 0) + { + if(fFreed) + { + pInode->pInodeBuf->aulEntries[uOrigInodeEntry] = BLOCK_SPARSE; + } + + /* The next seek will go to the beginning of the next + double indirect. + */ + ulTruncBlock += (DINDIR_DATA_BLOCKS - (uOrigDindirEntry * INDIR_ENTRIES)) - uOrigIndirEntry; + } + } + } + #endif + } + + return ret; +} + + +#if DINDIR_POINTERS > 0U +/** @brief Truncate a double indirect. + + @param pInode A pointer to the cached inode, whose coordinates indicate + the truncation boundary. + @param pfFreed On successful return, populated with whether the double + indirect node was freed. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENOSPC Insufficient free space to perform the truncate. + @retval -RED_EINVAL Invalid parameters. +*/ +static REDSTATUS TruncDindir( + CINODE *pInode, + bool *pfFreed) +{ + REDSTATUS ret = 0; + + if(!CINODE_IS_MOUNTED(pInode) || (pfFreed == NULL)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else if(pInode->pDindir == NULL) + { + *pfFreed = false; + } + else + { + bool fBranch = false; + uint16_t uEntry; + + /* The double indirect is definitely going to be branched (instead of + deleted) if any of its indirect pointers which are entirely prior to + the truncation boundary are non-sparse. + */ + for(uEntry = 0U; !fBranch && (uEntry < pInode->uDindirEntry); uEntry++) + { + fBranch = pInode->pDindir->aulEntries[uEntry] != BLOCK_SPARSE; + } + + /* Unless we already know for a fact that the double indirect is going + to be branched, examine the contents of the indirect pointer which + straddles the truncation boundary. If the indirect is going to be + deleted, we know this indirect pointer is going away, and that might + mean the double indirect is going to be deleted also. + */ + if(!fBranch && (pInode->pDindir->aulEntries[pInode->uDindirEntry] != BLOCK_SPARSE)) + { + for(uEntry = 0U; !fBranch && (uEntry < pInode->uIndirEntry); uEntry++) + { + fBranch = pInode->pIndir->aulEntries[uEntry] != BLOCK_SPARSE; + } + } + + if(fBranch) + { + ret = BranchBlock(pInode, BRANCHDEPTH_DINDIR, false); + } + + if(ret == 0) + { + uint32_t ulBlock = pInode->ulLogicalBlock; + uint16_t uStart = pInode->uDindirEntry; /* pInode->uDindirEntry will change. */ + + for(uEntry = uStart; uEntry < INDIR_ENTRIES; uEntry++) + { + /* Seek so that TruncIndir() has the correct indirect + buffer and indirect entry. + */ + ret = RedInodeDataSeek(pInode, ulBlock); + + if(ret == -RED_ENODATA) + { + ret = 0; + } + + if((ret == 0) && (pInode->ulIndirBlock != BLOCK_SPARSE)) + { + bool fIndirFreed; + + ret = TruncIndir(pInode, &fIndirFreed); + + if(ret == 0) + { + /* All of the indirects after the one which straddles + the truncation boundary should definitely end up + deleted. + */ + REDASSERT((uEntry == uStart) || fIndirFreed); + + /* If the double indirect is being freed, all of the + indirects should be freed too. + */ + REDASSERT(fIndirFreed || fBranch); + + if(fBranch && fIndirFreed) + { + pInode->pDindir->aulEntries[uEntry] = BLOCK_SPARSE; + } + } + } + + if(ret != 0) + { + break; + } + + ulBlock += (INDIR_ENTRIES - pInode->uIndirEntry); + } + + if(ret == 0) + { + *pfFreed = !fBranch; + + if(!fBranch) + { + RedInodePutDindir(pInode); + + ret = RedImapBlockSet(pInode->ulDindirBlock, false); + } + } + } + } + + return ret; +} +#endif /* DINDIR_POINTERS > 0U */ + + +#if REDCONF_DIRECT_POINTERS < INODE_ENTRIES +/** @brief Truncate a indirect. + + @param pInode A pointer to the cached inode, whose coordinates indicate + the truncation boundary. + @param pfFreed On successful return, populated with whether the indirect + node was freed. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENOSPC Insufficient free space to perform the truncate. + @retval -RED_EINVAL Invalid parameters. +*/ +static REDSTATUS TruncIndir( + CINODE *pInode, + bool *pfFreed) +{ + REDSTATUS ret = 0; + + if(!CINODE_IS_MOUNTED(pInode) || (pfFreed == NULL)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else if(pInode->pIndir == NULL) + { + *pfFreed = false; + } + else + { + bool fBranch = false; + uint16_t uEntry; + + /* Scan the range of entries which are not being truncated. If there + is anything there, then the indirect will not be empty after the + truncate, so it is branched and modified instead of deleted. + */ + for(uEntry = 0U; !fBranch && (uEntry < pInode->uIndirEntry); uEntry++) + { + fBranch = pInode->pIndir->aulEntries[uEntry] != BLOCK_SPARSE; + } + + if(fBranch) + { + ret = BranchBlock(pInode, BRANCHDEPTH_INDIR, false); + } + + if(ret == 0) + { + for(uEntry = pInode->uIndirEntry; uEntry < INDIR_ENTRIES; uEntry++) + { + ret = TruncDataBlock(pInode, &pInode->pIndir->aulEntries[uEntry], fBranch); + + if(ret != 0) + { + break; + } + } + + if(ret == 0) + { + *pfFreed = !fBranch; + + if(!fBranch) + { + RedInodePutIndir(pInode); + + ret = RedImapBlockSet(pInode->ulIndirBlock, false); + } + } + } + } + + return ret; +} +#endif /* REDCONF_DIRECT_POINTERS < INODE_ENTRIES */ + + +/** @brief Truncate a file data block. + + @param pInode A pointer to the cached inode structure. + @param pulBlock On entry, contains the block to be truncated. On + successful return, if @p fPropagate is true, populated + with BLOCK_SPARSE, otherwise unmodified. + @param fPropagate Whether the parent node is being branched. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EINVAL Invalid parameters. +*/ +static REDSTATUS TruncDataBlock( + const CINODE *pInode, + uint32_t *pulBlock, + bool fPropagate) +{ + REDSTATUS ret = 0; + + if(!CINODE_IS_MOUNTED(pInode) || (pulBlock == NULL)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else if(*pulBlock != BLOCK_SPARSE) + { + ret = RedImapBlockSet(*pulBlock, false); + + #if REDCONF_INODE_BLOCKS == 1 + if(ret == 0) + { + if(pInode->pInodeBuf->ulBlocks == 0U) + { + CRITICAL_ERROR(); + ret = -RED_EFUBAR; + } + else + { + pInode->pInodeBuf->ulBlocks--; + } + } + #endif + + if((ret == 0) && fPropagate) + { + *pulBlock = BLOCK_SPARSE; + } + } + else + { + /* Data block is sparse, nothing to truncate. + */ + } + + return ret; +} +#endif /* DELETE_SUPPORTED || TRUNCATE_SUPPORTED */ + + +/** @brief Prepare to increase the file size. + + When the inode size is increased, a sparse region is created. It is + possible that a prior shrink operation to an unaligned size left stale data + beyond the end of the file in the last data block. That data is not zeroed + while shrinking the inode in order to transfer the disk full burden from the + shrink operation to the expand operation. + + @param pInode A pointer to the cached inode structure. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENOSPC Insufficient free space to perform the truncate. + @retval -RED_EINVAL Invalid parameters. +*/ +static REDSTATUS ExpandPrepare( + CINODE *pInode) +{ + REDSTATUS ret = 0; + + if(!CINODE_IS_DIRTY(pInode)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + uint32_t ulOldSizeByteInBlock = (uint32_t)(pInode->pInodeBuf->ullSize & (REDCONF_BLOCK_SIZE - 1U)); + + if(ulOldSizeByteInBlock != 0U) + { + ret = RedInodeDataSeek(pInode, (uint32_t)(pInode->pInodeBuf->ullSize >> BLOCK_SIZE_P2)); + + if(ret == -RED_ENODATA) + { + ret = 0; + } + else if(ret == 0) + { + ret = BranchBlock(pInode, BRANCHDEPTH_FILE_DATA, true); + + if(ret == 0) + { + RedMemSet(&pInode->pbData[ulOldSizeByteInBlock], 0U, REDCONF_BLOCK_SIZE - ulOldSizeByteInBlock); + } + } + else + { + REDERROR(); + } + } + } + + return ret; +} +#endif /* REDCONF_READ_ONLY == 0 */ + + +/** @brief Seek to a given position within an inode, then buffer the data block. + + On successful return, pInode->pbData will be populated with a buffer + corresponding to the @p ulBlock block offset. + + @param pInode A pointer to the cached inode structure. + @param ulBlock The block offset to seek to and buffer. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_ENODATA The block offset is sparse. + @retval -RED_EINVAL @p ulBlock is too large. + @retval -RED_EIO A disk I/O error occurred. +*/ +REDSTATUS RedInodeDataSeekAndRead( + CINODE *pInode, + uint32_t ulBlock) +{ + REDSTATUS ret; + + ret = RedInodeDataSeek(pInode, ulBlock); + + if((ret == 0) && (pInode->pbData == NULL)) + { + REDASSERT(pInode->ulDataBlock != BLOCK_SPARSE); + + ret = RedBufferGet(pInode->ulDataBlock, 0U, CAST_VOID_PTR_PTR(&pInode->pbData)); + } + + return ret; +} + + +/** @brief Seek to a given position within an inode. + + On successful return, pInode->ulDataBlock will be populated with the + physical block number corresponding to the @p ulBlock block offset. + + Note: Callers of this function depend on its parameter checking. + + @param pInode A pointer to the cached inode structure. + @param ulBlock The block offset to seek to. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_ENODATA The block offset is sparse. + @retval -RED_EINVAL @p ulBlock is too large; or @p pInode is not a + mounted cached inode pointer. + @retval -RED_EIO A disk I/O error occurred. +*/ +REDSTATUS RedInodeDataSeek( + CINODE *pInode, + uint32_t ulBlock) +{ + REDSTATUS ret = 0; + + if(!CINODE_IS_MOUNTED(pInode) || (ulBlock >= INODE_DATA_BLOCKS)) + { + ret = -RED_EINVAL; + } + else + { + SeekCoord(pInode, ulBlock); + + #if DINDIR_POINTERS > 0U + if(pInode->uDindirEntry != COORD_ENTRY_INVALID) + { + if(pInode->ulDindirBlock == BLOCK_SPARSE) + { + /* If the double indirect is unallocated, so is the indirect. + */ + pInode->ulIndirBlock = BLOCK_SPARSE; + } + else + { + if(pInode->pDindir == NULL) + { + ret = RedBufferGet(pInode->ulDindirBlock, BFLAG_META_DINDIR, CAST_VOID_PTR_PTR(&pInode->pDindir)); + } + + if(ret == 0) + { + pInode->ulIndirBlock = pInode->pDindir->aulEntries[pInode->uDindirEntry]; + } + } + } + #endif + + #if REDCONF_DIRECT_POINTERS < INODE_ENTRIES + if((ret == 0) && (pInode->uIndirEntry != COORD_ENTRY_INVALID)) + { + if(pInode->ulIndirBlock == BLOCK_SPARSE) + { + /* If the indirect is unallocated, so is the data block. + */ + pInode->ulDataBlock = BLOCK_SPARSE; + } + else + { + if(pInode->pIndir == NULL) + { + ret = RedBufferGet(pInode->ulIndirBlock, BFLAG_META_INDIR, CAST_VOID_PTR_PTR(&pInode->pIndir)); + } + + if(ret == 0) + { + pInode->ulDataBlock = pInode->pIndir->aulEntries[pInode->uIndirEntry]; + } + } + } + #endif + + if((ret == 0) && (pInode->ulDataBlock == BLOCK_SPARSE)) + { + ret = -RED_ENODATA; + } + } + + return ret; +} + + +/** @brief Seek to the coordinates. + + Compute the new coordinates, and put any buffers which are not needed or are + no longer appropriate. + + @param pInode A pointer to the cached inode structure. + @param ulBlock The block offset to seek to. +*/ +static void SeekCoord( + CINODE *pInode, + uint32_t ulBlock) +{ + if(!CINODE_IS_MOUNTED(pInode) || (ulBlock >= INODE_DATA_BLOCKS)) + { + REDERROR(); + } + else if((pInode->ulLogicalBlock != ulBlock) || !pInode->fCoordInited) + { + RedInodePutData(pInode); + pInode->ulLogicalBlock = ulBlock; + + #if REDCONF_DIRECT_POINTERS > 0U + #if REDCONF_DIRECT_POINTERS < INODE_ENTRIES + if(ulBlock < REDCONF_DIRECT_POINTERS) + #endif + { + #if REDCONF_DIRECT_POINTERS < INODE_ENTRIES + RedInodePutCoord(pInode); + #endif + + pInode->uInodeEntry = (uint16_t)ulBlock; + pInode->ulDataBlock = pInode->pInodeBuf->aulEntries[pInode->uInodeEntry]; + + #if DINDIR_POINTERS > 0U + pInode->uDindirEntry = COORD_ENTRY_INVALID; + #endif + #if REDCONF_DIRECT_POINTERS < INODE_ENTRIES + pInode->uIndirEntry = COORD_ENTRY_INVALID; + #endif + } + #if REDCONF_DIRECT_POINTERS < INODE_ENTRIES + else + #endif + #endif + #if REDCONF_INDIRECT_POINTERS > 0U + #if REDCONF_INDIRECT_POINTERS < INODE_ENTRIES + if(ulBlock < (INODE_INDIR_BLOCKS + REDCONF_DIRECT_POINTERS)) + #endif + { + uint32_t ulIndirRangeOffset = ulBlock - REDCONF_DIRECT_POINTERS; + uint16_t uInodeEntry = (uint16_t)((ulIndirRangeOffset / INDIR_ENTRIES) + REDCONF_DIRECT_POINTERS); + uint16_t uIndirEntry = (uint16_t)(ulIndirRangeOffset % INDIR_ENTRIES); + + #if DINDIR_POINTERS > 0U + RedInodePutDindir(pInode); + #endif + + /* If the inode entry is not changing, then the previous indirect + is still the correct one. Otherwise, the old indirect will be + released and the new one will be read later. + */ + if((pInode->uInodeEntry != uInodeEntry) || !pInode->fCoordInited) + { + RedInodePutIndir(pInode); + + pInode->uInodeEntry = uInodeEntry; + + pInode->ulIndirBlock = pInode->pInodeBuf->aulEntries[pInode->uInodeEntry]; + } + + #if DINDIR_POINTERS > 0U + pInode->uDindirEntry = COORD_ENTRY_INVALID; + #endif + pInode->uIndirEntry = uIndirEntry; + + /* At this point, the following pInode members are needed but not + yet populated: + + - pIndir + - ulDataBlock + */ + } + #if DINDIR_POINTERS > 0U + else + #endif + #endif + #if DINDIR_POINTERS > 0U + { + uint32_t ulDindirRangeOffset = (ulBlock - REDCONF_DIRECT_POINTERS) - INODE_INDIR_BLOCKS; + uint16_t uInodeEntry = (uint16_t)((ulDindirRangeOffset / DINDIR_DATA_BLOCKS) + REDCONF_DIRECT_POINTERS + REDCONF_INDIRECT_POINTERS); + uint32_t ulDindirNodeOffset = ulDindirRangeOffset % DINDIR_DATA_BLOCKS; + uint16_t uDindirEntry = (uint16_t)(ulDindirNodeOffset / INDIR_ENTRIES); + uint16_t uIndirEntry = (uint16_t)(ulDindirNodeOffset % INDIR_ENTRIES); + + /* If the inode entry is not changing, then the previous double + indirect is still the correct one. Otherwise, the old double + indirect will be released and the new one will be read later. + */ + if((pInode->uInodeEntry != uInodeEntry) || !pInode->fCoordInited) + { + RedInodePutIndir(pInode); + RedInodePutDindir(pInode); + + pInode->uInodeEntry = uInodeEntry; + + pInode->ulDindirBlock = pInode->pInodeBuf->aulEntries[pInode->uInodeEntry]; + } + /* If neither the inode entry nor double indirect entry are + changing, then the previous indirect is still the correct one. + Otherwise, it old indirect will be released and the new one will + be read later. + */ + else if(pInode->uDindirEntry != uDindirEntry) + { + RedInodePutIndir(pInode); + } + else + { + /* Data buffer has already been put, nothing to do. + */ + } + + pInode->uDindirEntry = uDindirEntry; + pInode->uIndirEntry = uIndirEntry; + + /* At this point, the following pInode members are needed but not + yet populated: + + - pDindir + - pIndir + - ulIndirBlock + - ulDataBlock + */ + } + #elif (REDCONF_DIRECT_POINTERS > 0U) && (REDCONF_INDIRECT_POINTERS > 0U) + else + { + /* There are no double indirects, so the block should have been in + the direct or indirect range. + */ + REDERROR(); + } + #endif + + pInode->fCoordInited = true; + } + else + { + /* Seeking to the current position, nothing to do. + */ + } +} + + +/** @brief Read an unaligned portion of a block. + + @param pInode A pointer to the cached inode structure. + @param ullStart The file offset at which to read. + @param ulLen The number of bytes to read. + @param pbBuffer The buffer to read into. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EINVAL Invalid parameters. +*/ +static REDSTATUS ReadUnaligned( + CINODE *pInode, + uint64_t ullStart, + uint32_t ulLen, + uint8_t *pbBuffer) +{ + REDSTATUS ret; + + /* This read should not cross a block boundary. + */ + if( ((ullStart >> BLOCK_SIZE_P2) != (((ullStart + ulLen) - 1U) >> BLOCK_SIZE_P2)) + || (pbBuffer == NULL)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + ret = RedInodeDataSeekAndRead(pInode, (uint32_t)(ullStart >> BLOCK_SIZE_P2)); + + if(ret == 0) + { + RedMemCpy(pbBuffer, &pInode->pbData[ullStart & (REDCONF_BLOCK_SIZE - 1U)], ulLen); + } + else if(ret == -RED_ENODATA) + { + /* Sparse block, return zeroed data. + */ + RedMemSet(pbBuffer, 0U, ulLen); + ret = 0; + } + else + { + /* No action, just return the error. + */ + } + } + + return ret; +} + + +/** @brief Read one or more whole blocks. + + @param pInode A pointer to the cached inode structure. + @param ulBlockStart The file block offset at which to read. + @param ulBlockCount The number of blocks to read. + @param pbBuffer The buffer to read into. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EINVAL Invalid parameters. +*/ +static REDSTATUS ReadAligned( + CINODE *pInode, + uint32_t ulBlockStart, + uint32_t ulBlockCount, + uint8_t *pbBuffer) +{ + REDSTATUS ret = 0; + + if(pbBuffer == NULL) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + uint32_t ulBlockIndex = 0U; + + /* Read the data from disk one contiguous extent at a time. + */ + while((ret == 0) && (ulBlockIndex < ulBlockCount)) + { + uint32_t ulExtentStart; + uint32_t ulExtentLen = ulBlockCount - ulBlockIndex; + + ret = GetExtent(pInode, ulBlockStart + ulBlockIndex, &ulExtentStart, &ulExtentLen); + + if(ret == 0) + { + #if REDCONF_READ_ONLY == 0 + /* Before reading directly from disk, flush any dirty file data + buffers in the range to avoid reading stale data. + */ + ret = RedBufferFlush(ulExtentStart, ulExtentLen); + + if(ret == 0) + #endif + { + ret = RedIoRead(gbRedVolNum, ulExtentStart, ulExtentLen, &pbBuffer[ulBlockIndex << BLOCK_SIZE_P2]); + + if(ret == 0) + { + ulBlockIndex += ulExtentLen; + } + } + } + else if(ret == -RED_ENODATA) + { + /* Sparse block, return zeroed data. + */ + RedMemSet(&pbBuffer[ulBlockIndex << BLOCK_SIZE_P2], 0U, REDCONF_BLOCK_SIZE); + ulBlockIndex++; + ret = 0; + } + else + { + /* An unexpected error occurred; the loop will terminate. + */ + } + } + } + + return ret; +} + + +#if REDCONF_READ_ONLY == 0 +/** @brief Write an unaligned portion of a block. + + @param pInode A pointer to the cached inode structure. + @param ullStart The file offset at which to write. + @param ulLen The number of bytes to write. + @param pbBuffer The buffer to write from. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENOSPC No data can be written because there is insufficient + free space. + @retval -RED_EINVAL Invalid parameters. +*/ +static REDSTATUS WriteUnaligned( + CINODE *pInode, + uint64_t ullStart, + uint32_t ulLen, + const uint8_t *pbBuffer) +{ + REDSTATUS ret; + + /* This write should not cross a block boundary. + */ + if( ((ullStart >> BLOCK_SIZE_P2) != (((ullStart + ulLen) - 1U) >> BLOCK_SIZE_P2)) + || (pbBuffer == NULL)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + ret = RedInodeDataSeek(pInode, (uint32_t)(ullStart >> BLOCK_SIZE_P2)); + + if((ret == 0) || (ret == -RED_ENODATA)) + { + ret = BranchBlock(pInode, BRANCHDEPTH_FILE_DATA, true); + + if(ret == 0) + { + RedMemCpy(&pInode->pbData[ullStart & (REDCONF_BLOCK_SIZE - 1U)], pbBuffer, ulLen); + } + } + } + + return ret; +} + + +/** @brief Write one or more whole blocks. + + @param pInode A pointer to the cached inode structure. + @param ulBlockStart The file block offset at which to write. + @param pulBlockCount On entry, the number of blocks to attempt to write. + On successful return, the number of blocks actually + written. + @param pbBuffer The buffer to write from. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENOSPC No data can be written because there is insufficient + free space. + @retval -RED_EINVAL Invalid parameters. +*/ +static REDSTATUS WriteAligned( + CINODE *pInode, + uint32_t ulBlockStart, + uint32_t *pulBlockCount, + const uint8_t *pbBuffer) +{ + REDSTATUS ret = 0; + + if((pulBlockCount == NULL) || (pbBuffer == NULL)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + bool fFull = false; + uint32_t ulBlockCount = *pulBlockCount; + uint32_t ulBlockIndex; + + /* Branch all of the file data blocks in advance. + */ + for(ulBlockIndex = 0U; (ulBlockIndex < ulBlockCount) && !fFull; ulBlockIndex++) + { + ret = RedInodeDataSeek(pInode, ulBlockStart + ulBlockIndex); + + if((ret == 0) || (ret == -RED_ENODATA)) + { + ret = BranchBlock(pInode, BRANCHDEPTH_FILE_DATA, false); + + if(ret == -RED_ENOSPC) + { + if(ulBlockIndex > 0U) + { + ret = 0; + } + + fFull = true; + } + } + + if(ret != 0) + { + break; + } + } + + ulBlockCount = ulBlockIndex; + ulBlockIndex = 0U; + + if(fFull) + { + ulBlockCount--; + } + + /* Write the data to disk one contiguous extent at a time. + */ + while((ret == 0) && (ulBlockIndex < ulBlockCount)) + { + uint32_t ulExtentStart; + uint32_t ulExtentLen = ulBlockCount - ulBlockIndex; + + ret = GetExtent(pInode, ulBlockStart + ulBlockIndex, &ulExtentStart, &ulExtentLen); + + if(ret == 0) + { + ret = RedIoWrite(gbRedVolNum, ulExtentStart, ulExtentLen, &pbBuffer[ulBlockIndex << BLOCK_SIZE_P2]); + + if(ret == 0) + { + /* If there is any buffered file data for the extent we + just wrote, those buffers are now stale. + */ + ret = RedBufferDiscardRange(ulExtentStart, ulExtentLen); + } + + if(ret == 0) + { + ulBlockIndex += ulExtentLen; + } + } + } + + if(ret == 0) + { + *pulBlockCount = ulBlockCount; + } + } + + return ret; +} +#endif /* REDCONF_READ_ONLY == 0 */ + + +/** @brief Get the physical block number and count of contiguous blocks given a + starting logical block number. + + @param pInode A pointer to the cached inode structure. + @param ulBlockStart The file block offset for the start of the extent. + @param pulExtentStart On successful return, the starting physical block + number of the contiguous extent. + @param pulExtentLen On entry, the maximum length of the extent; on + successful return, the length of the contiguous + extent. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENODATA The block offset is sparse. + @retval -RED_EINVAL Invalid parameters. +*/ +static REDSTATUS GetExtent( + CINODE *pInode, + uint32_t ulBlockStart, + uint32_t *pulExtentStart, + uint32_t *pulExtentLen) +{ + REDSTATUS ret; + + if((pulExtentStart == NULL) || (pulExtentLen == NULL)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + ret = RedInodeDataSeek(pInode, ulBlockStart); + + if(ret == 0) + { + uint32_t ulExtentLen = *pulExtentLen; + uint32_t ulFirstBlock = pInode->ulDataBlock; + uint32_t ulRunLen = 1U; + + while((ret == 0) && (ulRunLen < ulExtentLen)) + { + ret = RedInodeDataSeek(pInode, ulBlockStart + ulRunLen); + + /* The extent ends when we find a sparse data block or when the + data block is not contiguous with the preceding data block. + */ + if((ret == -RED_ENODATA) || ((ret == 0) && (pInode->ulDataBlock != (ulFirstBlock + ulRunLen)))) + { + ret = 0; + break; + } + + ulRunLen++; + } + + if(ret == 0) + { + *pulExtentStart = ulFirstBlock; + *pulExtentLen = ulRunLen; + } + } + } + + return ret; +} + + +#if REDCONF_READ_ONLY == 0 +/** @brief Allocate or branch the file metadata path and data block if necessary. + + Optionally, can stop allocating/branching at a certain depth. + + @param pInode A pointer to the cached inode structure. + @param depth A BRANCHDEPTH_ value indicating the lowest depth to branch. + @param fBuffer Whether to buffer the data block. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENOSPC No data can be written because there is insufficient + free space. +*/ +static REDSTATUS BranchBlock( + CINODE *pInode, + BRANCHDEPTH depth, + bool fBuffer) +{ + REDSTATUS ret; + uint32_t ulCost = 0U; /* Init'd to quiet warnings. */ + + ret = BranchBlockCost(pInode, depth, &ulCost); + + if((ret == 0) && (ulCost > FreeBlockCount())) + { + ret = -RED_ENOSPC; + } + + if(ret == 0) + { + #if DINDIR_POINTERS > 0U + if(pInode->uDindirEntry != COORD_ENTRY_INVALID) + { + ret = BranchOneBlock(&pInode->ulDindirBlock, CAST_VOID_PTR_PTR(&pInode->pDindir), BFLAG_META_DINDIR); + + if(ret == 0) + { + /* In case we just created the double indirect. + */ + pInode->pDindir->ulInode = pInode->ulInode; + + pInode->pInodeBuf->aulEntries[pInode->uInodeEntry] = pInode->ulDindirBlock; + } + } + + if(ret == 0) + #endif + #if REDCONF_DIRECT_POINTERS < INODE_ENTRIES + { + if((pInode->uIndirEntry != COORD_ENTRY_INVALID) && (depth >= BRANCHDEPTH_INDIR)) + { + ret = BranchOneBlock(&pInode->ulIndirBlock, CAST_VOID_PTR_PTR(&pInode->pIndir), BFLAG_META_INDIR); + + if(ret == 0) + { + /* In case we just created the indirect. + */ + pInode->pIndir->ulInode = pInode->ulInode; + + #if DINDIR_POINTERS > 0U + if(pInode->uDindirEntry != COORD_ENTRY_INVALID) + { + pInode->pDindir->aulEntries[pInode->uDindirEntry] = pInode->ulIndirBlock; + } + else + #endif + { + pInode->pInodeBuf->aulEntries[pInode->uInodeEntry] = pInode->ulIndirBlock; + } + } + } + } + + if(ret == 0) + #endif + { + if(depth == BRANCHDEPTH_FILE_DATA) + { + #if REDCONF_INODE_BLOCKS == 1 + bool fAllocedNew = (pInode->ulDataBlock == BLOCK_SPARSE); + #endif + void **ppBufPtr = (fBuffer || (pInode->pbData != NULL)) ? CAST_VOID_PTR_PTR(&pInode->pbData) : NULL; + + ret = BranchOneBlock(&pInode->ulDataBlock, ppBufPtr, 0U); + + if(ret == 0) + { + #if REDCONF_DIRECT_POINTERS < INODE_ENTRIES + if(pInode->uIndirEntry != COORD_ENTRY_INVALID) + { + pInode->pIndir->aulEntries[pInode->uIndirEntry] = pInode->ulDataBlock; + } + else + #endif + { + pInode->pInodeBuf->aulEntries[pInode->uInodeEntry] = pInode->ulDataBlock; + } + + #if REDCONF_INODE_BLOCKS == 1 + if(fAllocedNew) + { + if(pInode->pInodeBuf->ulBlocks < INODE_DATA_BLOCKS) + { + pInode->pInodeBuf->ulBlocks++; + } + else + { + CRITICAL_ERROR(); + ret = -RED_EFUBAR; + } + } + #endif + } + } + } + + CRITICAL_ASSERT(ret == 0); + } + + return ret; +} + + +/** @brief Branch a block. + + The block can be a double indirect, indirect, or file data block. + + The caller should have already handled the disk full implications of + branching this block. + + @param pulBlock On entry, the current block number, which may be + BLOCK_SPARSE if the block is to be newly allocated. On + successful return, populated with the new block number, + which may be the same as the original block number if it + was not BLOCK_SPARSE and the block was already branched. + @param ppBuffer If NULL, indicates that the caller does not want to buffer + the branched block. If non-NULL, the caller does want the + branched block buffered, and the following is true: On + entry, the current buffer for the block, if there is one, or + NULL if there is no buffer. On successful exit, populated + with a buffer for the block, which will be dirty. If the + block number is initially BLOCK_SPARSE, there should be no + buffer for the block. + @param uBFlag The buffer type flags: BFLAG_META_DINDIR, BFLAG_META_INDIR, + or zero for file data. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EINVAL Invalid parameters. +*/ +static REDSTATUS BranchOneBlock( + uint32_t *pulBlock, + void **ppBuffer, + uint16_t uBFlag) +{ + REDSTATUS ret = 0; + + if(pulBlock == NULL) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + ALLOCSTATE state = ALLOCSTATE_FREE; + uint32_t ulPrevBlock = *pulBlock; + + if(ulPrevBlock != BLOCK_SPARSE) + { + ret = RedImapBlockState(ulPrevBlock, &state); + } + + if(ret == 0) + { + if(state == ALLOCSTATE_NEW) + { + /* Block is already branched, so simply get it buffered dirty + if requested. + */ + if(ppBuffer != NULL) + { + if(*ppBuffer != NULL) + { + RedBufferDirty(*ppBuffer); + } + else + { + ret = RedBufferGet(ulPrevBlock, uBFlag | BFLAG_DIRTY, ppBuffer); + } + } + } + else + { + /* Block does not exist or is committed state, so allocate a + new block for the branch. + */ + ret = RedImapAllocBlock(pulBlock); + + if(ret == 0) + { + if(ulPrevBlock == BLOCK_SPARSE) + { + /* Block did not exist previously, so just get it + buffered if requested. + */ + if(ppBuffer != NULL) + { + if(*ppBuffer != NULL) + { + /* How could there be an existing buffer when + the block did not exist? + */ + REDERROR(); + ret = -RED_EINVAL; + } + else + { + ret = RedBufferGet(*pulBlock, (uint16_t)((uint32_t)uBFlag | BFLAG_NEW | BFLAG_DIRTY), ppBuffer); + } + } + } + else + { + /* Branch the buffer for the committed state block to + the newly allocated location. + */ + if(ppBuffer != NULL) + { + if(*ppBuffer == NULL) + { + ret = RedBufferGet(ulPrevBlock, uBFlag, ppBuffer); + } + + if(ret == 0) + { + RedBufferBranch(*ppBuffer, *pulBlock); + } + } + + /* Mark the committed state block almost free. + */ + if(ret == 0) + { + ret = RedImapBlockSet(ulPrevBlock, false); + } + } + } + } + } + } + + return ret; +} + + +/** @brief Compute the free space cost of branching a block. + + The caller must first use RedInodeDataSeek() to the block to be branched. + + @param pInode A pointer to the cached inode structure, whose coordinates + indicate the block to be branched. + @param depth A BRANCHDEPTH_ value indicating how much of the file + metadata structure needs to be branched. + @param pulCost On successful return, populated with the number of blocks + that must be allocated from free space in order to branch + the given block. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EINVAL Invalid parameters. +*/ +static REDSTATUS BranchBlockCost( + const CINODE *pInode, + BRANCHDEPTH depth, + uint32_t *pulCost) +{ + REDSTATUS ret = 0; + + if(!CINODE_IS_MOUNTED(pInode) || !pInode->fCoordInited || (depth > BRANCHDEPTH_MAX) || (pulCost == NULL)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else + { + ALLOCSTATE state; + + /* ulCost is initialized to the maximum number of blocks that could + be branched, and decremented for every block we determine does not + need to be branched. + */ + #if DINDIR_POINTERS > 0U + uint32_t ulCost = 3U; + #elif REDCONF_DIRECT_POINTERS < INODE_ENTRIES + uint32_t ulCost = 2U; + #else + uint32_t ulCost = 1U; + #endif + + #if DINDIR_POINTERS > 0U + if(pInode->uDindirEntry != COORD_ENTRY_INVALID) + { + if(pInode->ulDindirBlock != BLOCK_SPARSE) + { + ret = RedImapBlockState(pInode->ulDindirBlock, &state); + + if((ret == 0) && (state == ALLOCSTATE_NEW)) + { + /* Double indirect already branched. + */ + ulCost--; + } + } + } + else + { + /* At this inode offset there are no double indirects. + */ + ulCost--; + } + + if(ret == 0) + #endif + #if REDCONF_DIRECT_POINTERS < INODE_ENTRIES + { + if((pInode->uIndirEntry != COORD_ENTRY_INVALID) && (depth >= BRANCHDEPTH_INDIR)) + { + if(pInode->ulIndirBlock != BLOCK_SPARSE) + { + ret = RedImapBlockState(pInode->ulIndirBlock, &state); + + if((ret == 0) && (state == ALLOCSTATE_NEW)) + { + /* Indirect already branched. + */ + ulCost--; + } + } + } + else + { + /* Either not branching this deep, or at this inode offset + there are no indirects. + */ + ulCost--; + } + } + + if(ret == 0) + #endif + { + if(depth == BRANCHDEPTH_FILE_DATA) + { + if(pInode->ulDataBlock != BLOCK_SPARSE) + { + ret = RedImapBlockState(pInode->ulDataBlock, &state); + + if((ret == 0) && (state == ALLOCSTATE_NEW)) + { + /* File data block already branched. + */ + ulCost--; + + /* If the file data block is branched, then its parent + nodes should be branched as well. + */ + REDASSERT(ulCost == 0U); + } + } + } + else + { + /* Not branching this deep. + */ + ulCost--; + } + } + + if(ret == 0) + { + *pulCost = ulCost; + } + } + + return ret; +} + + +/** @brief Yields the number of currently available free blocks. + + Accounts for reserved blocks, subtracting the number of reserved blocks if + they are unavailable. + + @return Number of currently available free blocks. +*/ +static uint32_t FreeBlockCount(void) +{ + uint32_t ulFreeBlocks = gpRedMR->ulFreeBlocks; + + #if RESERVED_BLOCKS > 0U + if(!gpRedCoreVol->fUseReservedBlocks) + { + if(ulFreeBlocks >= RESERVED_BLOCKS) + { + ulFreeBlocks -= RESERVED_BLOCKS; + } + else + { + ulFreeBlocks = 0U; + } + } + #endif + + return ulFreeBlocks; +} +#endif /* REDCONF_READ_ONLY == 0 */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/volume.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/volume.c new file mode 100644 index 0000000..976a2f0 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/driver/volume.c @@ -0,0 +1,540 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements core volume operations. +*/ +#include +#include + + +static bool MetarootIsValid(METAROOT *pMR, bool *pfSectorCRCIsValid); +#ifdef REDCONF_ENDIAN_SWAP +static void MetaRootEndianSwap(METAROOT *pMetaRoot); +#endif + + +/** @brief Mount a file system volume. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO Volume not formatted, improperly formatted, or corrupt. +*/ +REDSTATUS RedVolMount(void) +{ + REDSTATUS ret; + + #if REDCONF_READ_ONLY == 0 + ret = RedOsBDevOpen(gbRedVolNum, BDEV_O_RDWR); + #else + ret = RedOsBDevOpen(gbRedVolNum, BDEV_O_RDONLY); + #endif + + if(ret == 0) + { + ret = RedVolMountMaster(); + + if(ret == 0) + { + ret = RedVolMountMetaroot(); + } + + if(ret != 0) + { + /* If we fail to mount, invalidate the buffers to prevent any + confusion that could be caused by stale or corrupt metadata. + */ + (void)RedBufferDiscardRange(0U, gpRedVolume->ulBlockCount); + (void)RedOsBDevClose(gbRedVolNum); + } + } + + return ret; +} + + +/** @brief Mount the master block. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO Master block missing, corrupt, or inconsistent with the + compile-time driver settings. +*/ +REDSTATUS RedVolMountMaster(void) +{ + REDSTATUS ret; + MASTERBLOCK *pMB; + + /* Read the master block, to ensure that the disk was formatted with + Reliance Edge. + */ + ret = RedBufferGet(BLOCK_NUM_MASTER, BFLAG_META_MASTER, CAST_VOID_PTR_PTR(&pMB)); + + if(ret == 0) + { + /* Verify that the driver was compiled with the same settings that + the disk was formatted with. If not, the user has made a + mistake: either the driver settings are wrong, or the disk needs + to be reformatted. + */ + if( (pMB->ulVersion != RED_DISK_LAYOUT_VERSION) + || (pMB->ulInodeCount != gpRedVolConf->ulInodeCount) + || (pMB->ulBlockCount != gpRedVolume->ulBlockCount) + || (pMB->uMaxNameLen != REDCONF_NAME_MAX) + || (pMB->uDirectPointers != REDCONF_DIRECT_POINTERS) + || (pMB->uIndirectPointers != REDCONF_INDIRECT_POINTERS) + || (pMB->bBlockSizeP2 != BLOCK_SIZE_P2) + || (((pMB->bFlags & MBFLAG_API_POSIX) != 0U) != (REDCONF_API_POSIX == 1)) + || (((pMB->bFlags & MBFLAG_INODE_TIMESTAMPS) != 0U) != (REDCONF_INODE_TIMESTAMPS == 1)) + || (((pMB->bFlags & MBFLAG_INODE_BLOCKS) != 0U) != (REDCONF_INODE_BLOCKS == 1))) + { + ret = -RED_EIO; + } + #if REDCONF_API_POSIX == 1 + else if(((pMB->bFlags & MBFLAG_INODE_NLINK) != 0U) != (REDCONF_API_POSIX_LINK == 1)) + { + ret = -RED_EIO; + } + #else + else if((pMB->bFlags & MBFLAG_INODE_NLINK) != 0U) + { + ret = -RED_EIO; + } + #endif + else + { + /* Master block configuration is valid. + + Save the sequence number of the master block in the volume, + since we need it later (see RedVolMountMetaroot()) and we do + not want to re-buffer the master block. + */ + gpRedVolume->ullSequence = pMB->hdr.ullSequence; + } + + RedBufferPut(pMB); + } + + return ret; +} + + +/** @brief Mount the latest metaroot. + + This function also populates the volume contexts. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO Both metaroots are missing or corrupt. +*/ +REDSTATUS RedVolMountMetaroot(void) +{ + REDSTATUS ret; + + ret = RedIoRead(gbRedVolNum, BLOCK_NUM_FIRST_METAROOT, 1U, &gpRedCoreVol->aMR[0U]); + + if(ret == 0) + { + ret = RedIoRead(gbRedVolNum, BLOCK_NUM_FIRST_METAROOT + 1U, 1U, &gpRedCoreVol->aMR[1U]); + } + + /* Determine which metaroot is the most recent copy that was written + completely. + */ + if(ret == 0) + { + uint8_t bMR = UINT8_MAX; + bool fSectorCRCIsValid; + + if(MetarootIsValid(&gpRedCoreVol->aMR[0U], &fSectorCRCIsValid)) + { + bMR = 0U; + + #ifdef REDCONF_ENDIAN_SWAP + MetaRootEndianSwap(&gpRedCoreVol->aMR[0U]); + #endif + } + else if(gpRedVolConf->fAtomicSectorWrite && !fSectorCRCIsValid) + { + ret = -RED_EIO; + } + else + { + /* Metaroot is not valid, so it is ignored and there's nothing + to do here. + */ + } + + if(ret == 0) + { + if(MetarootIsValid(&gpRedCoreVol->aMR[1U], &fSectorCRCIsValid)) + { + #ifdef REDCONF_ENDIAN_SWAP + MetaRootEndianSwap(&gpRedCoreVol->aMR[1U]); + #endif + + if((bMR != 0U) || (gpRedCoreVol->aMR[1U].hdr.ullSequence > gpRedCoreVol->aMR[0U].hdr.ullSequence)) + { + bMR = 1U; + } + } + else if(gpRedVolConf->fAtomicSectorWrite && !fSectorCRCIsValid) + { + ret = -RED_EIO; + } + else + { + /* Metaroot is not valid, so it is ignored and there's nothing + to do here. + */ + } + } + + if(ret == 0) + { + if(bMR == UINT8_MAX) + { + /* Neither metaroot was valid. + */ + ret = -RED_EIO; + } + else + { + gpRedCoreVol->bCurMR = bMR; + gpRedMR = &gpRedCoreVol->aMR[bMR]; + } + } + } + + if(ret == 0) + { + /* Normally the metaroot contains the highest sequence number, but the + master block is the last block written during format, so on a + freshly formatted volume the master block sequence number (stored in + gpRedVolume->ullSequence) will be higher than that in the metaroot. + */ + if(gpRedMR->hdr.ullSequence > gpRedVolume->ullSequence) + { + gpRedVolume->ullSequence = gpRedMR->hdr.ullSequence; + } + + /* gpRedVolume->ullSequence stores the *next* sequence number; to avoid + giving the next node written to disk the same sequence number as the + metaroot, increment it here. + */ + ret = RedVolSeqNumIncrement(); + } + + if(ret == 0) + { + gpRedVolume->fMounted = true; + #if REDCONF_READ_ONLY == 0 + gpRedVolume->fReadOnly = false; + #endif + + #if RESERVED_BLOCKS > 0U + gpRedCoreVol->fUseReservedBlocks = false; + #endif + gpRedCoreVol->ulAlmostFreeBlocks = 0U; + + gpRedCoreVol->aMR[1U - gpRedCoreVol->bCurMR] = *gpRedMR; + gpRedCoreVol->bCurMR = 1U - gpRedCoreVol->bCurMR; + gpRedMR = &gpRedCoreVol->aMR[gpRedCoreVol->bCurMR]; + } + + return ret; +} + + +/** @brief Determine whether the metaroot is valid. + + @param pMR The metaroot buffer. + @param pfSectorCRCIsValid Populated with whether the first sector of the + metaroot buffer is valid. + + @return Whether the metaroot is valid. + + @retval true The metaroot buffer is valid. + @retval false The metaroot buffer is invalid. +*/ +static bool MetarootIsValid( + METAROOT *pMR, + bool *pfSectorCRCIsValid) +{ + bool fRet = false; + + if(pfSectorCRCIsValid == NULL) + { + REDERROR(); + } + else if(pMR == NULL) + { + REDERROR(); + *pfSectorCRCIsValid = false; + } + #ifdef REDCONF_ENDIAN_SWAP + else if(RedRev32(pMR->hdr.ulSignature) != META_SIG_METAROOT) + #else + else if(pMR->hdr.ulSignature != META_SIG_METAROOT) + #endif + { + *pfSectorCRCIsValid = false; + } + else + { + const uint8_t *pbMR = CAST_VOID_PTR_TO_CONST_UINT8_PTR(pMR); + uint32_t ulSectorCRC = pMR->ulSectorCRC; + uint32_t ulCRC; + + #ifdef REDCONF_ENDIAN_SWAP + ulSectorCRC = RedRev32(ulSectorCRC); + #endif + + /* The sector CRC was zero when the CRC was computed during the + transaction, so it must be zero here. + */ + pMR->ulSectorCRC = 0U; + + ulCRC = RedCrc32Update(0U, &pbMR[8U], gpRedVolConf->ulSectorSize - 8U); + + fRet = ulCRC == ulSectorCRC; + *pfSectorCRCIsValid = fRet; + + if(fRet) + { + if(gpRedVolConf->ulSectorSize < REDCONF_BLOCK_SIZE) + { + ulCRC = RedCrc32Update(ulCRC, &pbMR[gpRedVolConf->ulSectorSize], REDCONF_BLOCK_SIZE - gpRedVolConf->ulSectorSize); + } + + #ifdef REDCONF_ENDIAN_SWAP + ulCRC = RedRev32(ulCRC); + #endif + + fRet = ulCRC == pMR->hdr.ulCRC; + } + } + + return fRet; +} + + +#if REDCONF_READ_ONLY == 0 +/** @brief Commit a transaction point. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. +*/ +REDSTATUS RedVolTransact(void) +{ + REDSTATUS ret = 0; + + REDASSERT(!gpRedVolume->fReadOnly); /* Should be checked by caller. */ + + if(gpRedCoreVol->fBranched) + { + gpRedMR->ulFreeBlocks += gpRedCoreVol->ulAlmostFreeBlocks; + gpRedCoreVol->ulAlmostFreeBlocks = 0U; + + ret = RedBufferFlush(0U, gpRedVolume->ulBlockCount); + + if(ret == 0) + { + gpRedMR->hdr.ulSignature = META_SIG_METAROOT; + gpRedMR->hdr.ullSequence = gpRedVolume->ullSequence; + + ret = RedVolSeqNumIncrement(); + } + + if(ret == 0) + { + const uint8_t *pbMR = CAST_VOID_PTR_TO_CONST_UINT8_PTR(gpRedMR); + uint32_t ulSectorCRC; + + #ifdef REDCONF_ENDIAN_SWAP + MetaRootEndianSwap(gpRedMR); + #endif + + gpRedMR->ulSectorCRC = 0U; + + ulSectorCRC = RedCrc32Update(0U, &pbMR[8U], gpRedVolConf->ulSectorSize - 8U); + + if(gpRedVolConf->ulSectorSize < REDCONF_BLOCK_SIZE) + { + gpRedMR->hdr.ulCRC = RedCrc32Update(ulSectorCRC, &pbMR[gpRedVolConf->ulSectorSize], REDCONF_BLOCK_SIZE - gpRedVolConf->ulSectorSize); + } + else + { + gpRedMR->hdr.ulCRC = ulSectorCRC; + } + + gpRedMR->ulSectorCRC = ulSectorCRC; + + #ifdef REDCONF_ENDIAN_SWAP + gpRedMR->hdr.ulCRC = RedRev32(gpRedMR->hdr.ulCRC); + gpRedMR->ulSectorCRC = RedRev32(gpRedMR->ulSectorCRC); + #endif + + /* Flush the block device before writing the metaroot, so that all + previously written blocks are guaranteed to be on the media before + the metaroot is written. Otherwise, if the block device reorders + the writes, the metaroot could reach the media before metadata it + points at, creating a window for disk corruption if power is lost. + */ + ret = RedIoFlush(gbRedVolNum); + } + + if(ret == 0) + { + ret = RedIoWrite(gbRedVolNum, BLOCK_NUM_FIRST_METAROOT + gpRedCoreVol->bCurMR, 1U, gpRedMR); + + #ifdef REDCONF_ENDIAN_SWAP + MetaRootEndianSwap(gpRedMR); + #endif + } + + /* Flush the block device to force the metaroot write to the media. This + guarantees the transaction point is really complete before we return. + */ + if(ret == 0) + { + ret = RedIoFlush(gbRedVolNum); + } + + /* Toggle to the other metaroot buffer. The working state and committed + state metaroot buffers exchange places. + */ + if(ret == 0) + { + uint8_t bNextMR = 1U - gpRedCoreVol->bCurMR; + + gpRedCoreVol->aMR[bNextMR] = *gpRedMR; + gpRedCoreVol->bCurMR = bNextMR; + + gpRedMR = &gpRedCoreVol->aMR[gpRedCoreVol->bCurMR]; + + gpRedCoreVol->fBranched = false; + } + + CRITICAL_ASSERT(ret == 0); + } + + return ret; +} +#endif + + +#ifdef REDCONF_ENDIAN_SWAP +static void MetaRootEndianSwap( + METAROOT *pMetaRoot) +{ + if(pMetaRoot == NULL) + { + REDERROR(); + } + else + { + pMetaRoot->ulSectorCRC = RedRev32(pMetaRoot->ulSectorCRC); + pMetaRoot->ulFreeBlocks = RedRev32(pMetaRoot->ulFreeBlocks); + #if REDCONF_API_POSIX == 1 + pMetaRoot->ulFreeInodes = RedRev32(pMetaRoot->ulFreeInodes); + #endif + pMetaRoot->ulAllocNextBlock = RedRev32(pMetaRoot->ulAllocNextBlock); + } +} +#endif + + +/** @brief Process a critical file system error. + + @param pszFileName The file in which the error occurred. + @param ulLineNum The line number at which the error occurred. +*/ +void RedVolCriticalError( + const char *pszFileName, + uint32_t ulLineNum) +{ + #if REDCONF_OUTPUT == 1 + #if REDCONF_READ_ONLY == 0 + if(!gpRedVolume->fReadOnly) + { + RedOsOutputString("Critical file system error in Reliance Edge, setting volume to READONLY\n"); + } + else + #endif + { + RedOsOutputString("Critical file system error in Reliance Edge (volume already READONLY)\n"); + } + #endif + + #if REDCONF_READ_ONLY == 0 + gpRedVolume->fReadOnly = true; + #endif + + #if REDCONF_ASSERTS == 1 + RedOsAssertFail(pszFileName, ulLineNum); + #else + (void)pszFileName; + (void)ulLineNum; + #endif +} + + +/** @brief Increment the sequence number. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL Cannot increment sequence number: maximum value reached. + This should not ever happen. +*/ +REDSTATUS RedVolSeqNumIncrement(void) +{ + REDSTATUS ret; + + if(gpRedVolume->ullSequence == UINT64_MAX) + { + /* In practice this should never, ever happen; to get here, there would + need to be UINT64_MAX disk writes, which would take eons: longer + than the lifetime of any product or storage media. If this assert + fires and the current year is still written with four digits, + suspect memory corruption. + */ + CRITICAL_ERROR(); + ret = -RED_EFUBAR; + } + else + { + gpRedVolume->ullSequence++; + ret = 0; + } + + return ret; +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/include/redcore.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/include/redcore.h new file mode 100644 index 0000000..077eb93 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/include/redcore.h @@ -0,0 +1,257 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file +*/ +#ifndef REDCORE_H +#define REDCORE_H + + +#include +#include +#include "rednodes.h" +#include "redcoremacs.h" +#include "redcorevol.h" + + +#define META_SIG_MASTER (0x5453414DU) /* 'MAST' */ +#define META_SIG_METAROOT (0x4154454DU) /* 'META' */ +#define META_SIG_IMAP (0x50414D49U) /* 'IMAP' */ +#define META_SIG_INODE (0x444F4E49U) /* 'INOD' */ +#define META_SIG_DINDIR (0x494C4244U) /* 'DBLI' */ +#define META_SIG_INDIR (0x49444E49U) /* 'INDI' */ + + +REDSTATUS RedIoRead(uint8_t bVolNum, uint32_t ulBlockStart, uint32_t ulBlockCount, void *pBuffer); +#if REDCONF_READ_ONLY == 0 +REDSTATUS RedIoWrite(uint8_t bVolNum, uint32_t ulBlockStart, uint32_t ulBlockCount, const void *pBuffer); +REDSTATUS RedIoFlush(uint8_t bVolNum); +#endif + + +/** Indicates a block buffer is dirty (its contents are different than the + contents of the corresponding block on disk); or, when passed into + RedBufferGet(), indicates that the buffer should be marked dirty. +*/ +#define BFLAG_DIRTY ((uint16_t) 0x0001U) + +/** Tells RedBufferGet() that the buffer is for a newly allocated block, and its + contents should be zeroed instead of being read from disk. Always used in + combination with BFLAG_DIRTY. +*/ +#define BFLAG_NEW ((uint16_t) 0x0002U) + +/** Indicates that a block buffer is a master block (MASTERBLOCK) metadata node. +*/ +#define BFLAG_META_MASTER ((uint16_t)(0x0004U | BFLAG_META)) + +/** Indicates that a block buffer is an imap (IMAPNODE) metadata node. +*/ +#define BFLAG_META_IMAP ((uint16_t)(0x0008U | BFLAG_META)) + +/** Indicates that a block buffer is an inode (INODE) metadata node. +*/ +#define BFLAG_META_INODE ((uint16_t)(0x0010U | BFLAG_META)) + +/** Indicates that a block buffer is an indirect (INDIR) metadata node. +*/ +#define BFLAG_META_INDIR ((uint16_t)(0x0020U | BFLAG_META)) + +/** Indicates that a block buffer is a double indirect (DINDIR) metadata node. +*/ +#define BFLAG_META_DINDIR ((uint16_t)(0x0040U | BFLAG_META)) + +/** Indicates that a block buffer is a metadata node. Callers of RedBufferGet() + should not use this flag; instead, use one of the BFLAG_META_* flags. +*/ +#define BFLAG_META ((uint16_t) 0x8000U) + + +void RedBufferInit(void); +REDSTATUS RedBufferGet(uint32_t ulBlock, uint16_t uFlags, void **ppBuffer); +void RedBufferPut(const void *pBuffer); +#if REDCONF_READ_ONLY == 0 +REDSTATUS RedBufferFlush(uint32_t ulBlockStart, uint32_t ulBlockCount); +void RedBufferDirty(const void *pBuffer); +void RedBufferBranch(const void *pBuffer, uint32_t ulBlockNew); +#if (REDCONF_API_POSIX == 1) || FORMAT_SUPPORTED +void RedBufferDiscard(const void *pBuffer); +#endif +#endif +REDSTATUS RedBufferDiscardRange(uint32_t ulBlockStart, uint32_t ulBlockCount); + + +/** @brief Allocation state of a block. +*/ +typedef enum +{ + ALLOCSTATE_FREE, /**< Free and may be allocated; writeable. */ + ALLOCSTATE_USED, /**< In-use and transacted; not writeable. */ + ALLOCSTATE_NEW, /**< In-use but not transacted; writeable. */ + ALLOCSTATE_AFREE /**< Will become free after a transaction; not writeable. */ +} ALLOCSTATE; + +REDSTATUS RedImapBlockGet(uint8_t bMR, uint32_t ulBlock, bool *pfAllocated); +#if REDCONF_READ_ONLY == 0 +REDSTATUS RedImapBlockSet(uint32_t ulBlock, bool fAllocated); +REDSTATUS RedImapAllocBlock(uint32_t *pulBlock); +#endif +REDSTATUS RedImapBlockState(uint32_t ulBlock, ALLOCSTATE *pState); + +#if REDCONF_IMAP_INLINE == 1 +REDSTATUS RedImapIBlockGet(uint8_t bMR, uint32_t ulBlock, bool *pfAllocated); +REDSTATUS RedImapIBlockSet(uint32_t ulBlock, bool fAllocated); +#endif + +#if REDCONF_IMAP_EXTERNAL == 1 +REDSTATUS RedImapEBlockGet(uint8_t bMR, uint32_t ulBlock, bool *pfAllocated); +REDSTATUS RedImapEBlockSet(uint32_t ulBlock, bool fAllocated); +uint32_t RedImapNodeBlock(uint8_t bMR, uint32_t ulImapNode); +#endif + + +/** @brief Cached inode structure. +*/ +typedef struct +{ + uint32_t ulInode; /**< The inode number of the cached inode. */ + #if REDCONF_API_POSIX == 1 + bool fDirectory; /**< True if the inode is a directory. */ + #endif + #if REDCONF_READ_ONLY == 0 + bool fBranched; /**< True if the inode is branched (writeable). */ + bool fDirty; /**< True if the inode buffer is dirty. */ + #endif + bool fCoordInited; /**< True after the first seek. */ + + INODE *pInodeBuf; /**< Pointer to the inode buffer. */ + #if DINDIR_POINTERS > 0U + DINDIR *pDindir; /**< Pointer to the double indirect node buffer. */ + #endif + #if REDCONF_DIRECT_POINTERS < INODE_ENTRIES + INDIR *pIndir; /**< Pointer to the indirect node buffer. */ + #endif + uint8_t *pbData; /**< Pointer to the data block buffer. */ + + /* All the members below this point are part of the seek coordinates; see + RedInodeDataSeek(). + */ + uint32_t ulLogicalBlock; /**< Logical block offset into the inode. */ + #if DINDIR_POINTERS > 0U + uint32_t ulDindirBlock; /**< Physical block number of the double indirect node. */ + #endif + #if REDCONF_DIRECT_POINTERS < INODE_ENTRIES + uint32_t ulIndirBlock; /**< Physical block number of the indirect node. */ + #endif + uint32_t ulDataBlock; /**< Physical block number of the file data block. */ + + uint16_t uInodeEntry; /**< Which inode entry to traverse to reach ulLogicalBlock. */ + #if DINDIR_POINTERS > 0U + uint16_t uDindirEntry; /**< Which double indirect entry to traverse to reach ulLogicalBlock. */ + #endif + #if REDCONF_DIRECT_POINTERS < INODE_ENTRIES + uint16_t uIndirEntry; /**< Which indirect entry to traverse to reach ulLogicalBlock. */ + #endif +} CINODE; + +#define CINODE_IS_MOUNTED(pInode) (((pInode) != NULL) && INODE_IS_VALID((pInode)->ulInode) && ((pInode)->pInodeBuf != NULL)) +#define CINODE_IS_DIRTY(pInode) (CINODE_IS_MOUNTED(pInode) && (pInode)->fDirty) + + +#define IPUT_UPDATE_ATIME (0x01U) +#define IPUT_UPDATE_MTIME (0x02U) +#define IPUT_UPDATE_CTIME (0x04U) +#define IPUT_UPDATE_MASK (IPUT_UPDATE_ATIME|IPUT_UPDATE_MTIME|IPUT_UPDATE_CTIME) + + +REDSTATUS RedInodeMount(CINODE *pInode, FTYPE type, bool fBranch); +#if REDCONF_READ_ONLY == 0 +REDSTATUS RedInodeBranch(CINODE *pInode); +#endif +#if (REDCONF_READ_ONLY == 0) && ((REDCONF_API_POSIX == 1) || FORMAT_SUPPORTED) +REDSTATUS RedInodeCreate(CINODE *pInode, uint32_t ulPInode, uint16_t uMode); +#endif +#if DELETE_SUPPORTED +REDSTATUS RedInodeDelete(CINODE *pInode); +REDSTATUS RedInodeLinkDec(CINODE *pInode); +#endif +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) +REDSTATUS RedInodeFree(CINODE *pInode); +#endif +void RedInodePut(CINODE *pInode, uint8_t bTimeFields); +void RedInodePutCoord(CINODE *pInode); +#if DINDIR_POINTERS > 0U +void RedInodePutDindir(CINODE *pInode); +#endif +#if REDCONF_DIRECT_POINTERS < INODE_ENTRIES +void RedInodePutIndir(CINODE *pInode); +#endif +void RedInodePutData(CINODE *pInode); +#if ((REDCONF_READ_ONLY == 0) && ((REDCONF_API_POSIX == 1) || FORMAT_SUPPORTED)) || (REDCONF_CHECKER == 1) +REDSTATUS RedInodeIsFree(uint32_t ulInode, bool *pfFree); +#endif +REDSTATUS RedInodeBitGet(uint8_t bMR, uint32_t ulInode, uint8_t bWhich, bool *pfAllocated); + +REDSTATUS RedInodeDataRead(CINODE *pInode, uint64_t ullStart, uint32_t *pulLen, void *pBuffer); +#if REDCONF_READ_ONLY == 0 +REDSTATUS RedInodeDataWrite(CINODE *pInode, uint64_t ullStart, uint32_t *pulLen, const void *pBuffer); +#if DELETE_SUPPORTED || TRUNCATE_SUPPORTED +REDSTATUS RedInodeDataTruncate(CINODE *pInode, uint64_t ullSize); +#endif +#endif +REDSTATUS RedInodeDataSeekAndRead(CINODE *pInode, uint32_t ulBlock); +REDSTATUS RedInodeDataSeek(CINODE *pInode, uint32_t ulBlock); + +#if REDCONF_API_POSIX == 1 +#if REDCONF_READ_ONLY == 0 +REDSTATUS RedDirEntryCreate(CINODE *pPInode, const char *pszName, uint32_t ulInode); +#endif +#if DELETE_SUPPORTED +REDSTATUS RedDirEntryDelete(CINODE *pPInode, uint32_t ulDeleteIdx); +#endif +REDSTATUS RedDirEntryLookup(CINODE *pPInode, const char *pszName, uint32_t *pulEntryIdx, uint32_t *pulInode); +#if (REDCONF_API_POSIX_READDIR == 1) || (REDCONF_CHECKER == 1) +REDSTATUS RedDirEntryRead(CINODE *pPInode, uint32_t *pulIdx, char *pszName, uint32_t *pulInode); +#endif +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX_RENAME == 1) +REDSTATUS RedDirEntryRename(CINODE *pSrcPInode, const char *pszSrcName, CINODE *pSrcInode, CINODE *pDstPInode, const char *pszDstName, CINODE *pDstInode); +#endif +#endif + +REDSTATUS RedVolMount(void); +REDSTATUS RedVolMountMaster(void); +REDSTATUS RedVolMountMetaroot(void); +#if REDCONF_READ_ONLY == 0 +REDSTATUS RedVolTransact(void); +#endif +void RedVolCriticalError(const char *pszFileName, uint32_t ulLineNum); +REDSTATUS RedVolSeqNumIncrement(void); + +#if FORMAT_SUPPORTED +REDSTATUS RedVolFormat(void); +#endif + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/include/redcoremacs.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/include/redcoremacs.h new file mode 100644 index 0000000..221ac91 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/include/redcoremacs.h @@ -0,0 +1,92 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file +*/ +#ifndef REDCOREMACS_H +#define REDCOREMACS_H + + +#define BLOCK_NUM_MASTER (0UL) /* Block number of the master block. */ +#define BLOCK_NUM_FIRST_METAROOT (1UL) /* Block number of the first metaroot. */ + +#define BLOCK_SPARSE (0U) + +#define DINDIR_POINTERS ((INODE_ENTRIES - REDCONF_DIRECT_POINTERS) - REDCONF_INDIRECT_POINTERS) +#define DINDIR_DATA_BLOCKS (INDIR_ENTRIES * INDIR_ENTRIES) + +#define INODE_INDIR_BLOCKS (REDCONF_INDIRECT_POINTERS * INDIR_ENTRIES) +#define INODE_DINDIR_BLOCKS (DINDIR_POINTERS * DINDIR_DATA_BLOCKS) +#define INODE_DATA_BLOCKS (REDCONF_DIRECT_POINTERS + INODE_INDIR_BLOCKS + INODE_DINDIR_BLOCKS) +#define INODE_SIZE_MAX (UINT64_SUFFIX(1) * REDCONF_BLOCK_SIZE * INODE_DATA_BLOCKS) + + +/* First inode number that can be allocated. +*/ +#if REDCONF_API_POSIX == 1 +#define INODE_FIRST_FREE (INODE_FIRST_VALID + 1U) +#else +#define INODE_FIRST_FREE (INODE_FIRST_VALID) +#endif + +/** @brief Determine if an inode number is valid. +*/ +#define INODE_IS_VALID(INODENUM) (((INODENUM) >= INODE_FIRST_VALID) && ((INODENUM) < (INODE_FIRST_VALID + gpRedVolConf->ulInodeCount))) + + +/* The number of blocks reserved to allow a truncate or delete operation to + complete when the disk is otherwise full. + + The more expensive of the two operations is delete, which has to actually + write to a file data block to remove the directory entry. +*/ +#if REDCONF_READ_ONLY == 1 + #define RESERVED_BLOCKS 0U +#elif (REDCONF_API_POSIX == 1) && ((REDCONF_API_POSIX_UNLINK == 1) || (REDCONF_API_POSIX_RMDIR == 1)) + #if DINDIR_POINTERS > 0U + #define RESERVED_BLOCKS 3U + #elif REDCONF_INDIRECT_POINTERS > 0U + #define RESERVED_BLOCKS 2U + #else + #define RESERVED_BLOCKS 1U + #endif +#elif ((REDCONF_API_POSIX == 1) && (REDCONF_API_POSIX_FTRUNCATE == 1)) || ((REDCONF_API_FSE == 1) && (REDCONF_API_FSE_TRUNCATE == 1)) + #if DINDIR_POINTERS > 0U + #define RESERVED_BLOCKS 2U + #elif REDCONF_INDIRECT_POINTERS > 0U + #define RESERVED_BLOCKS 1U + #else + #define RESERVED_BLOCKS 0U + #endif +#else + #define RESERVED_BLOCKS 0U +#endif + + +#define CRITICAL_ASSERT(EXP) ((EXP) ? (void)0 : CRITICAL_ERROR()) +#define CRITICAL_ERROR() RedVolCriticalError(__FILE__, __LINE__) + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/include/redcorevol.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/include/redcorevol.h new file mode 100644 index 0000000..881cbb3 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/include/redcorevol.h @@ -0,0 +1,95 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file +*/ +#ifndef REDCOREVOL_H +#define REDCOREVOL_H + + +/** @brief Per-volume run-time data specific to the core. +*/ +typedef struct +{ + /** Whether this volume uses the inline imap (true) or external imap + (false). Computed at initialization time based on the block count. + */ + bool fImapInline; + +#if REDCONF_IMAP_EXTERNAL == 1 + /** First block number of the on-disk imap. Valid only when fImapInline + is false. + */ + uint32_t ulImapStartBN; + + /** The number of double-allocated imap nodes that make up the imap. + */ + uint32_t ulImapNodeCount; +#endif + + /** Block number where the inode table starts. + */ + uint32_t ulInodeTableStartBN; + + /** First block number that can be allocated. + */ + uint32_t ulFirstAllocableBN; + + /** The two metaroot structures, committed and working state. + */ + METAROOT aMR[2U]; + + /** The index of the current metaroot; must be 0 or 1. + */ + uint8_t bCurMR; + + /** Whether the volume has been branched or not. + */ + bool fBranched; + + /** The number of blocks which will become free after the next transaction. + */ + uint32_t ulAlmostFreeBlocks; + + #if RESERVED_BLOCKS > 0U + /** Whether to use the blocks reserved for operations that create free + space. + */ + bool fUseReservedBlocks; + #endif +} COREVOLUME; + +/* Pointer to the core volume currently being accessed; populated during + RedCoreVolSetCurrent(). +*/ +extern COREVOLUME * CONST_IF_ONE_VOLUME gpRedCoreVol; + +/* Pointer to the metaroot currently being accessed; populated during + RedCoreVolSetCurrent() and RedCoreVolTransact(). +*/ +extern METAROOT *gpRedMR; + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/include/rednodes.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/include/rednodes.h new file mode 100644 index 0000000..b333878 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/core/include/rednodes.h @@ -0,0 +1,195 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file +*/ +#ifndef REDNODES_H +#define REDNODES_H + + +#define NODEHEADER_SIZE (16U) +#define NODEHEADER_OFFSET_SIG (0U) +#define NODEHEADER_OFFSET_CRC (4U) +#define NODEHEADER_OFFSET_SEQ (8U) + +/** @brief Common header for all metadata nodes. +*/ +typedef struct +{ + uint32_t ulSignature; /**< Value which uniquely identifies the metadata node type. */ + uint32_t ulCRC; /**< CRC-32 checksum of the node contents, starting after the CRC. */ + uint64_t ullSequence; /**< Current sequence number at the time the node was written to disk. */ +} NODEHEADER; + + +/** Flag set in the master block when REDCONF_API_POSIX == 1. */ +#define MBFLAG_API_POSIX (0x01U) + +/** Flag set in the master block when REDCONF_INODE_TIMESTAMPS == 1. */ +#define MBFLAG_INODE_TIMESTAMPS (0x02U) + +/** Flag set in the master block when REDCONF_INODE_BLOCKS == 1. */ +#define MBFLAG_INODE_BLOCKS (0x04U) + +/** Flag set in the master block when (REDCONF_API_POSIX == 1) && (REDCONF_API_POSIX_LINK == 1). */ +#define MBFLAG_INODE_NLINK (0x08U) + + +/** @brief Node which identifies the volume and stores static volume information. +*/ +typedef struct +{ + NODEHEADER hdr; /**< Common node header. */ + + uint32_t ulVersion; /**< On-disk layout version number. */ + char acBuildNum[8U]; /**< Build number of the product (not null terminated). */ + uint32_t ulFormatTime; /**< Date and time the volume was formatted. */ + uint32_t ulInodeCount; /**< Compile-time configured number of inodes. */ + uint32_t ulBlockCount; /**< Compile-time configured number of logical blocks. */ + uint16_t uMaxNameLen; /**< Compile-time configured maximum file name length. */ + uint16_t uDirectPointers; /**< Compile-time configured number of direct pointers per inode. */ + uint16_t uIndirectPointers; /**< Compile-time configured number of indirect pointers per inode. */ + uint8_t bBlockSizeP2; /**< Compile-time configured block size, expressed as a power of two. */ + uint8_t bFlags; /**< Compile-time booleans which affect on-disk structures. */ +} MASTERBLOCK; + + +#if REDCONF_API_POSIX == 1 +#define METAROOT_HEADER_SIZE (NODEHEADER_SIZE + 16U) /* Size in bytes of the metaroot header fields. */ +#else +#define METAROOT_HEADER_SIZE (NODEHEADER_SIZE + 12U) /* Size in bytes of the metaroot header fields. */ +#endif +#define METAROOT_ENTRY_BYTES (REDCONF_BLOCK_SIZE - METAROOT_HEADER_SIZE) /* Number of bytes remaining in the metaroot block for entries. */ +#define METAROOT_ENTRIES (METAROOT_ENTRY_BYTES * 8U) + +/** @brief Metadata root node; each volume has two. +*/ +typedef struct +{ + NODEHEADER hdr; /**< Common node header. */ + + uint32_t ulSectorCRC; /**< CRC-32 checksum of the first sector. */ + uint32_t ulFreeBlocks; /**< Number of allocable blocks that are free. */ + #if REDCONF_API_POSIX == 1 + uint32_t ulFreeInodes; /**< Number of inode slots that are free. */ + #endif + uint32_t ulAllocNextBlock; /**< Forward allocation pointer. */ + + /** Imap bitmap. With inline imaps, this is the imap bitmap that indicates + which inode blocks are used and which allocable blocks are used. + Otherwise, this bitmap toggles nodes in the external imap between one + of two possible block locations. + */ + uint8_t abEntries[METAROOT_ENTRY_BYTES]; +} METAROOT; + + +#if REDCONF_IMAP_EXTERNAL == 1 +#define IMAPNODE_HEADER_SIZE (NODEHEADER_SIZE) /* Size in bytes of the imap node header fields. */ +#define IMAPNODE_ENTRY_BYTES (REDCONF_BLOCK_SIZE - IMAPNODE_HEADER_SIZE) /* Number of bytes remaining in the imap node for entries. */ +#define IMAPNODE_ENTRIES (IMAPNODE_ENTRY_BYTES * 8U) + +/** @brief One node of the external imap. +*/ +typedef struct +{ + NODEHEADER hdr; /**< Common node header. */ + + /** Bitmap which indicates which inode blocks are used and which allocable + blocks are used. + */ + uint8_t abEntries[IMAPNODE_ENTRY_BYTES]; +} IMAPNODE; +#endif + + +#define INODE_HEADER_SIZE (NODEHEADER_SIZE + 8U + ((REDCONF_INODE_BLOCKS == 1) ? 4U : 0U) + \ + ((REDCONF_INODE_TIMESTAMPS == 1) ? 12U : 0U) + 4U + ((REDCONF_API_POSIX == 1) ? 4U : 0U)) +#define INODE_ENTRIES ((REDCONF_BLOCK_SIZE - INODE_HEADER_SIZE) / 4U) + +#if (REDCONF_DIRECT_POINTERS < 0) || (REDCONF_DIRECT_POINTERS > (INODE_ENTRIES - REDCONF_INDIRECT_POINTERS)) + #error "Configuration error: invalid value of REDCONF_DIRECT_POINTERS" +#endif +#if (REDCONF_INDIRECT_POINTERS < 0) || (REDCONF_INDIRECT_POINTERS > (INODE_ENTRIES - REDCONF_DIRECT_POINTERS)) + #error "Configuration error: invalid value of REDCONF_INDIRECT_POINTERS" +#endif + +/** @brief Stores metadata for a file or directory. +*/ +typedef struct +{ + NODEHEADER hdr; /**< Common node header. */ + + uint64_t ullSize; /**< Size of the inode, in bytes. */ +#if REDCONF_INODE_BLOCKS == 1 + uint32_t ulBlocks; /**< Total number file data blocks allocated to the inode. */ +#endif +#if REDCONF_INODE_TIMESTAMPS == 1 + uint32_t ulATime; /**< Time of last access (seconds since January 1, 1970). */ + uint32_t ulMTime; /**< Time of last modification (seconds since January 1, 1970). */ + uint32_t ulCTime; /**< Time of last status change (seconds since January 1, 1970). */ +#endif + uint16_t uMode; /**< Inode type (file or directory) and permissions (reserved). */ +#if (REDCONF_API_POSIX == 1) && (REDCONF_API_POSIX_LINK == 1) + uint16_t uNLink; /**< Link count, number of names pointing to the inode. */ +#else + uint8_t abPadding[2]; /**< Padding to 32-bit align the next member. */ +#endif +#if REDCONF_API_POSIX == 1 + uint32_t ulPInode; /**< Parent inode number. Only guaranteed to be accurate for directories. */ +#endif + + /** Block numbers for lower levels of the file metadata structure. Some + fraction of these entries are for direct pointers (file data block + numbers), some for indirect pointers, some for double-indirect + pointers; the number allocated to each is static but user-configurable. + For all types, an array slot is zero if the range is sparse or beyond + the end of file. + */ + uint32_t aulEntries[INODE_ENTRIES]; +} INODE; + + +#define INDIR_HEADER_SIZE (NODEHEADER_SIZE + 4U) +#define INDIR_ENTRIES ((REDCONF_BLOCK_SIZE - INDIR_HEADER_SIZE) / 4U) + +/** @brief Node for storing block pointers. +*/ +typedef struct +{ + NODEHEADER hdr; /**< Common node header. */ + + uint32_t ulInode; /**< Inode which owns this indirect or double indirect. */ + + /** For indirect nodes, stores block numbers of file data. For double + indirect nodes, stores block numbers of indirect nodes. An array + slot is zero if the corresponding block or indirect range is beyond + the end of file or entirely sparse. + */ + uint32_t aulEntries[INDIR_ENTRIES]; +} INDIR, DINDIR; + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/doc/coding_style.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/doc/coding_style.txt new file mode 100644 index 0000000..1a816dd --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/doc/coding_style.txt @@ -0,0 +1,389 @@ +Datalight Coding Style +====================== + +This is a description of the Datalight Coding Style intended for third parties +who want to contribute code to Reliance Edge. This document is derived from the +DDSS Coding Guidelines, but only contains a subset of the content which is most +likely to be relevant to third party contributors. + +Reliance Edge complies with the MISRA-C:2012 coding guidelines, which includes +many rules that affect coding style. Unfortunately the MISRA-C:2012 document is +not freely available, and is much too long to be effectively summarized, but if +you are familiar with the rules, adhere to them. A few important rules of +thumb: avoid the goto and continue keywords; avoid using more than one break +in a loop; and avoid having more than one return from a function (single point +of exit); default cases in every switch statement; avoid recursion; and make +generous use of parentheses. Outside of the file system driver, in tests and +host tools, the MISRA-C rules are relaxed. + +Beyond MISRA-C, Datalight has a standard coding style. Most aspects of this +style are matters of preference, but when contributing code to Datalight an +effort should be made to use this style for the sake of consistency. + +Below is an example function, which illustrates several key points of Datalight +Coding Style: + +/** @brief One-sentence description of what this function does. + + Additional description. + + @param ulFirstParameter Description of the parameter. + @param pszPointer Description of the parameter. + + @return Describe the return value. + + @retval true Optional description of specific return value. + @retval false Optional description of specific return value. +*/ +bool ExampleFunction( + uint32_t ulFirstParameter, + char *pszPointer) +{ + bool fStatus = true; + + /* This is a single-line comment. + */ + if(ulFirstParameter > 0U) + { + /* This is a multi-line comment. Filler text: Lorem ipsum dolor sit + amet, consectetur adipiscing elit, sed do eiusmod tempor incididunt + ut labore et dolore magna aliqua. + */ + FunctionCall(); + + while(fStatus) + { + fStatus = AnotherFunction(ulFirstParameter, pszPointer); + } + } + + return fStatus; +} + +Tab Stop Conventions +-------------------- + +In all C code (.c/.h), use a tab width of four spaces, and use soft tabs (in +other words, tabs are expanded to spaces). In Makefiles, use hard tabs and a +tab width of 8. + +Naming +------ + +Datalight uses CamelCase for functions and variables. Type names are generally +UPPERCASE, except for standard types like uint32_t. Preprocessor macros are +UPPERCASE, with words separated by underscores (for example, INODE_INVALID). + +Doxygen Documentation +--------------------- + +Doxygen is used to document functions (including static functions), along with +types, structures, files, etc. For Doxygen tags, use '@' instead of a backslash +(thus "@param" not "\param"). + +Function Declarations +--------------------- + +Multi-line function declarations are preferred, as they tend to be more +readable. Use the following form: + +static bool ExampleFunctionDeclaration( + uint32_t ulFirstParameter, + char *pszPointer, + uint8_t **ppbBuffer) +{ + uint16_t uLocalVar; /* descriptive comment */ + uint8_t *pbBuffer = NULL; /* descriptive comment */ + + Function body... +} + +The following guidelines should be used: + +- Align both the data-type and the variable names, for parameters and locals, at + the same level if practical. +- For pointer types, the '*' belongs to the variable name---it's not part of the + data-type, so keep it with the variable name. +- If useful, single line comments may be used to describe local variables (not + a requirement). +- For functions with no parameters, the "void" declaration does not need to be + on a separate line. +- Generally each variable should be declared on a separate line. This promotes + readability, and facilitates having a comment for each variable. + +Function declarations should be spaced apart by two blank lines between the +closing brace which ends a function and the Doxygen comment which starts the +next. + +Curly Braces +------------ + +Datalight lines up all curly braces vertically. As per MISRA-C, curly braces +are never omitted, even if the braces contain only a single statement. + +For consistency, even structure declarations and initializations should use the +same style, with the curly braces lined up vertically. One exception is for +structure initializations where both the opening and closing curly braces can +fit on the same line. If so, do it. + +Code Comments +------------- + +Datalight uses the standard C style /* comments */. C++ style comments (//) are +never used. The Datalight standard comment style is shown below. This style +applies to all general comments within the code. + +/* This is a single-line comment. +*/ +if(ulFirstParameter > 0U) +{ + /* This is a multi-line comment. Filler text: Lorem ipsum dolor sit amet, + consectetur adipiscing elit, sed do eiusmod tempor incididunt ut labore + et dolore magna aliqua. + */ + while(fStatus) + { + } +} + +Note the characteristics: + +- The /* and */ align with the natural 4 character indentation. +- The comment text is exactly indented another 4 characters. +- The comment text starts on the same line as the opening /*. +- The terminating */ is on its own line. +- There is usually a single blank line preceding the comment, however if the + preceding line is an opening curly brace, then an extra blank line is not + necessary. +- There is usually no blank line after the comment, but rather the closing */ + "attaches" the comment to the code about which the comment refers. +- These comments should always fit with the standard 80 character margin. + +Comments where the /* and */ are on the same line may be used in a few places: + +- For variable or parameter descriptions, where the comment fits on the same + line as the declaration. +- For structure member declarations, where the comment fits on the same line as + the declaration. +- For macros or preprocessor logic, where the comment fits on the same line. + +It is OK for such comments to exceed the 80 character margin by a small amount, +if necessary, as this sometimes promotes code readability. + +Indentation Style +----------------- + +The general paradigm used in Datalight code is that curly braces line up +vertically, and everything in between them is indented. This should include all +comments, labels, and preprocessor symbols. The only things which are aligned +at the left-most columns are: + +- Symbols, variables, declarations, and preprocessor logic which are at the + module-scope (outside of a function) +- Comments which are outside of a function +- Function declarations +- Function open and closing curly braces + +Typically comments are always lined up directly with the code to which they +apply. + +Labels (when used; gotos are disallowed in driver code) are lined up two +characters to the left of the code they reside in, to make them stand out, while +as the same time, still remaining subservient to the level of curly braces in +which they reside. For example: + +bool ExampleLabelUsage(void) +{ + MutexLock(); + + Lots of complicated code... + + Unlock: + + MutexUnlock(); + + return fSuccess; +} + +Preprocessor logic, such as controlling features which are conditionally +compiled in or out, should not disrupt the flow of the code, but rather should +be indented in similar fashion to the code it controls, but positioned two +characters to the left. For example, consider the following code snippet. The +preprocessor conditions are both indented relative to the outer curly braces, +but do not disrupt the normal code flow. + +int32_t red_statvfs( + const char *pszVolume, + REDSTATFS *pStatvfs) +{ + REDSTATUS ret; + + ret = PosixEnter(); + if(ret == 0) + { + uint8_t bVolNum; + + ret = RedPathSplit(pszVolume, &bVolNum, NULL); + + #if REDCONF_VOLUME_COUNT > 1U + if(ret == 0) + { + ret = RedCoreVolSetCurrent(bVolNum); + } + #endif + + if(ret == 0) + { + ret = RedCoreVolStat(pStatvfs); + } + + PosixLeave(); + } + + return PosixReturn(ret); +} + +Note that, like anything else between curly brackets, the contents of a switch +statement are indented: + +switch(ulSignature) +{ + case META_SIG_MASTER: + fValid = (uFlags == BFLAG_META_MASTER); + break; + case META_SIG_IMAP: + fValid = (uFlags == BFLAG_META_IMAP); + break; + case META_SIG_INODE: + fValid = (uFlags == BFLAG_META_INODE); + break; + case META_SIG_DINDIR: + fValid = (uFlags == BFLAG_META_DINDIR); + break; + case META_SIG_INDIR: + fValid = (uFlags == BFLAG_META_INDIR); + break; + default: + fValid = false; + break; +} + +Maximum Line Length +------------------- + +The maximum line length for code need not be rigidly limited to the traditional +80 characters. Nevertheless the line lengths should be kept reasonable. +Anything longer than 100 to 120 characters should probably be broken up. The +most important consideration is readability---fitting on the screen is important +for readability, but equally important is facilitating an easy understanding of +the logical code flow. + +There are a few exceptions on both sides of the issue. Generally comments +should be limited to 80 characters always. Some lines of code may exceed the +120 character length by a large margin, if it makes the code more understandable +and maintainable. This is especially true when dealing with code that generates +output which needs to be lined up. + +Regardless of everything else, no lines should exceed 250 characters because +some editors cannot handle anything larger. + +Maximum Display Output Line Length +---------------------------------- + +Any code which displays TTY style output, whether on a screen or a terminal, +should be constructed so the output is readable and wraps properly on an 80 +character wide display. This primarily applies to the "standard" output from +various tests and tools as well as syntax output for those tests and tools; +debug output can violate this rule. + +Preprocessor Notation +--------------------- + +Don't use preprocessor notation where the # is separated from the keyword by one +or more white spaces. For example, don't do: + +#ifndef SYMBOL1 +# define SYMBOL1 +#endif + +Instead, do: + +#ifndef SYMBOL1 + #define SYMBOL1 +#endif + +Hexadecimal Notation +-------------------- + +Use uppercase for any alphabetic hexadecimal digits, and lower case for the +notational element. For example: + +#define HEXNUM 0x123abd /* Bad */ +#define HEXNUM 0X123ABD /* Bad */ +#define HEXNUM 0x123ABD /* Good */ + +Hungarian Notation +------------------ + +Datalight uses Hungarian notation. The following type prefixes are used: + +Type Prefix | Meaning +----------- | ------- +c | char +uc | unsigned char +i | int +n | unsigned int or size_t +b | uint8_t +u | uint16_t +ul | uint32_t +ull | uint64_t +sz | array of char that will be null-terminated +f | bool +h | A handle +fn | A function (always used with the "p" modifier) + +There is no official Hungarian for int8_t, int16_t, int32_t, or int64_t, +although some code uses unofficial variants (like "ll" for int64_t). + +The following modifiers may be used in combination with the type prefixes +defined above, or in combination with other types: + +Modifier | Meaning +-------- | ------- +a | An array +p | A pointer +g | A global variable + +Notes: + +- There is no standard Hungarian for structure declarations, however the use of + the "a" and "p" modifiers is completely appropriate (and expected). +- For those data types which do not have any standard defined Hungarian prefix, + using none is preferable to misusing another prefix which would lead to + confusion. +- The "p" pointer modifier must be used such that a variable which is a pointer + to a pointer uses multiple "p" prefixes. A general rule-of-thumb is that the + variable name should have the same number of "p" prefixes as the declaration + has asterisks. This allows pointer expressions to be easily decoded using + cancellation. + +Variable Scope +-------------- + +Declare a variable in the narrowest scope in which it is meaningful. +Unnecessarily declaring all variables at the beginning of a function, where they +may be physically far from where they are actually used, makes the code harder +to maintain. + +When multiple blocks of code share a variable, but not its value, declare the +variable separately for each code block. + +For example, if two separate blocks contain loops indexed by a variable ulIndex +declare it separately in each block rather than declaring it once in a wider +scope and using it in both places. + +Using distinct declarations in the two blocks allows the compiler to check for +failure to initialize the variable in the second block. If there is a single +declaration, the (now meaningless) value left over from the first block can be +used erroneously in the second block. + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/doc/release_notes.md b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/doc/release_notes.md new file mode 100644 index 0000000..2a3d937 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/doc/release_notes.md @@ -0,0 +1,135 @@ +# Reliance Edge Release Notes + +This file contains a list of updates made to Reliance Edge over the course of +recent releases and a list of known issues. + +## Release History and Changes + +### Reliance Edge v2.0, January 2017 + +- Added support for Linux as a host environment + - All "host" projects may now be built in either Windows or Linux using the + `make` command. The formatter and image builder are built, and the checker + and image copier are also built in the commercial kit. + - An additional host tool has been added for Linux only: `redfuse`. It is a + File System in User Space (FUSE) implementation, allowing a Reliance Edge + volume to be mounted directly on Linux for easy access. It is built from + the host project folder using the command `make redfuse`. + - The OS-specific API test (commercial kit only) is now ported to run on Linux + for the purpose of verifying the FUSE implementation. +- Fixed a bug that could leave a directory in an invalid state after removing + files. For example, an affected directory might report a non-zero length even + after all files had been deleted. +- Fixed a bug that would leave the driver in a bad state if a mount operation + failed due to missing or corrupt metaroot blocks. + +### Reliance Edge v1.1 (Beta), November 2016 + +- Added support for a discard (trim) interface in the commercial kit. While + discards are not integral to the behavior of the filesystem, they allow + certain types of Flash drivers and media to perform at optimal speed and + efficiency. The commercial version of Reliance Edge now allows the user to + implement this interface for compatible storage media. + - This change added new fields to the configuration files redconf.h and + redconf.c. The configuration utility has been updated to version 1.1 and + existing configuration files must be updated using the updated utility. +- The configuration utility now has keyboard shortcuts for opening and saving + the configuration. +- The configuration utility now adds version macros to easily identify when an + outdated configuration file is used with Reliance Edge or vice versa. + +### Reliance Edge v1.0.4, July 2016 + +- Added ARM mbed and ARM mbed OS support in the commercial kit, with an example + projects for ARM mbed OS on the NXP FRDM-K64F board. +- Some minor deficiencies in the POSIX-like API test suite have been addressed. + +### Reliance Edge v1.0.3, June 2016 + +- Added support for static memory allocation configuration in FreeRTOS + version 9. No common code changes. + +### Reliance Edge v1.0.2, February 2016 + +#### Common Code Changes +- A new per-volume configuration option has been added: users can specify a + number of times to retry a block device read, write or flush operation before + returning a failure. The configuration tool has been updated to version 1.0.2 + with this change. + - This added a new field to the volume configuration in redconf.c: existing + redconf.c files from v1.0.1 and earlier must be updated to work with v1.0.2. + Open redconf.h and redconf.c with the configuration tool, enable + "Retry block device I/O on failure" for any volumes if desired, and save the + redconf files. + +#### FreeRTOS Port Changes +- Added support for the STM32 HAL SD card driver in the FreeRTOS block device + interface. Two boards are supported out-of-the-box: the STM324xG-EVAL and the + STM32F746NG-Discovery. A sample project is included for the STM324xG-EVAL. + +#### MQX Port Changes +- Fixed a bug which prevented Reliance Edge from compiling if the File System + Essentials API was selected in the configuration. +- Fixed a bug which would have returned an uninitialized value from + `RedOsBDevFlush()` for block devices that support flushing. + +### Reliance Edge v1.0.1, October 2015 + +- Added MQX RTOS support in the commercial kit, with example projects for + the Kinetis Design Studio. +- Bug fix in the F_DRIVER implementation of the FreeRTOS block device service. + +### Reliance Edge v1.0, July 2015 + +#### Common Code Changes + +- First release of commercial kit and MISRA C:2012 Design Assurance Package. + The commercial kit includes many new tools and tests which were not previously + available. +- Overhauled parsing of command-line parameters to be consistent for all tools + and tests. Command-line tools now use Unix-style short and long options (such + as `-H` and `--help`) instead of DOS-style switches (such as `/?`). +- Renamed all os/\*/include/ostypes.h headers to os/\*/include/redostypes.h, so + that all headers use the product prefix. If you created a port using v0.9, + this header needs to be renamed and its header guard (#ifndef OSTYPES_H etc.) + should also be updated. +- Add a new header for OS-specific MISRA C:2012 deviation macros, located at + os/\*/include/redosdeviations.h. If you created a port using v0.9, copy the + template from os/stub/include/redosdeviations.h into the include directory. +- Eliminated support for sector sizes less than 256. If using a smaller sector + size (say for a RAM disk), this must now be emulated in the implementation of + the block device OS service. +- Added RedFseFormat() as an optional FSE API, allowing FSE applications to + format the volume at run-time. + - This added a new macro to redconf.h: existing redconf.h files from v0.9 must + be updated to work with v1.0. Open redconf.h with the configuration tool, + ignore the warning about the missing macro, and save it. +- Internal restructuring has renamed the macros for the string and memory + functions used in redconf.h. An existing redconf.h file from v0.9 will need + to be updated; for a file containing the old names, the new config tool will + default to using the (slow) Reliance Edge string/memory functions; to use the + C library or custom versions, this will need to be selected in the + configuration utility. +- Fix a bug which would result in an error when attempting to create a name with + one or more trailing path separators (such as `red_mkdir("/foo/bar/")`). +- Fix a bug where an open handle for an inode on one volume would prevent the + same inode number from being deleted on a different volume. + +#### FreeRTOS Port Changes + +- The implementation of the timestamp OS service no longer requires that + `configUSE_TIMERS` be set to `1`. + +### Reliance Edge v0.9 (Beta), April 2015 + +First public release. + +## Known Issues + +### Visual Studio 2005 + +The Reliance Edge Win32 port (used for the host tools and the Win32 test +project) cannot be compiled by Visual Studio 2005. This is not going to be +fixed since VS2005 is an old toolset. Newer versions of Visual Studio, starting +with Visual Studio 2008, work just fine. + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/doc/release_notes.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/doc/release_notes.txt new file mode 100644 index 0000000..341eb5d --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/doc/release_notes.txt @@ -0,0 +1,156 @@ + + +RELIANCE EDGE RELEASE NOTES + + +This file contains a list of updates made to Reliance Edge over the +course of recent releases and a list of known issues. + + +Release History and Changes + +Reliance Edge v2.0, January 2017 + +- Added support for Linux as a host environment +- All "host" projects may now be built in either Windows or Linux + using the make command. The formatter and image builder are built, + and the checker and image copier are also built in the + commercial kit. +- An additional host tool has been added for Linux only: redfuse. It + is a File System in User Space (FUSE) implementation, allowing a + Reliance Edge volume to be mounted directly on Linux for + easy access. It is built from the host project folder using the + command make redfuse. +- The OS-specific API test (commercial kit only) is now ported to run + on Linux for the purpose of verifying the FUSE implementation. +- Fixed a bug that could leave a directory in an invalid state after + removing files. For example, an affected directory might report a + non-zero length even after all files had been deleted. +- Fixed a bug that would leave the driver in a bad state if a mount + operation failed due to missing or corrupt metaroot blocks. + +Reliance Edge v1.1 (Beta), November 2016 + +- Added support for a discard (trim) interface in the commercial kit. + While discards are not integral to the behavior of the filesystem, + they allow certain types of Flash drivers and media to perform at + optimal speed and efficiency. The commercial version of Reliance + Edge now allows the user to implement this interface for compatible + storage media. +- This change added new fields to the configuration files redconf.h + and redconf.c. The configuration utility has been updated to version + 1.1 and existing configuration files must be updated using the + updated utility. +- The configuration utility now has keyboard shortcuts for opening and + saving the configuration. +- The configuration utility now adds version macros to easily identify + when an outdated configuration file is used with Reliance Edge or + vice versa. + +Reliance Edge v1.0.4, July 2016 + +- Added ARM mbed and ARM mbed OS support in the commercial kit, with + an example projects for ARM mbed OS on the NXP FRDM-K64F board. +- Some minor deficiencies in the POSIX-like API test suite have + been addressed. + +Reliance Edge v1.0.3, June 2016 + +- Added support for static memory allocation configuration in FreeRTOS + version 9. No common code changes. + +Reliance Edge v1.0.2, February 2016 + +Common Code Changes + +- A new per-volume configuration option has been added: users can + specify a number of times to retry a block device read, write or + flush operation before returning a failure. The configuration tool + has been updated to version 1.0.2 with this change. +- This added a new field to the volume configuration in redconf.c: + existing redconf.c files from v1.0.1 and earlier must be updated to + work with v1.0.2. Open redconf.h and redconf.c with the + configuration tool, enable "Retry block device I/O on failure" for + any volumes if desired, and save the redconf files. + +FreeRTOS Port Changes + +- Added support for the STM32 HAL SD card driver in the FreeRTOS block + device interface. Two boards are supported out-of-the-box: the + STM324xG-EVAL and the STM32F746NG-Discovery. A sample project is + included for the STM324xG-EVAL. + +MQX Port Changes + +- Fixed a bug which prevented Reliance Edge from compiling if the File + System Essentials API was selected in the configuration. +- Fixed a bug which would have returned an uninitialized value from + RedOsBDevFlush() for block devices that support flushing. + +Reliance Edge v1.0.1, October 2015 + +- Added MQX RTOS support in the commercial kit, with example projects + for the Kinetis Design Studio. +- Bug fix in the F_DRIVER implementation of the FreeRTOS block + device service. + +Reliance Edge v1.0, July 2015 + +Common Code Changes + +- First release of commercial kit and MISRA C:2012 Design + Assurance Package. The commercial kit includes many new tools and + tests which were not previously available. +- Overhauled parsing of command-line parameters to be consistent for + all tools and tests. Command-line tools now use Unix-style short and + long options (such as -H and --help) instead of DOS-style switches + (such as /?). +- Renamed all os/*/include/ostypes.h headers to + os/*/include/redostypes.h, so that all headers use the + product prefix. If you created a port using v0.9, this header needs + to be renamed and its header guard (#ifndef OSTYPES_H etc.) should + also be updated. +- Add a new header for OS-specific MISRA C:2012 deviation macros, + located at os/*/include/redosdeviations.h. If you created a port + using v0.9, copy the template from os/stub/include/redosdeviations.h + into the include directory. +- Eliminated support for sector sizes less than 256. If using a + smaller sector size (say for a RAM disk), this must now be emulated + in the implementation of the block device OS service. +- Added RedFseFormat() as an optional FSE API, allowing FSE + applications to format the volume at run-time. +- This added a new macro to redconf.h: existing redconf.h files from + v0.9 must be updated to work with v1.0. Open redconf.h with the + configuration tool, ignore the warning about the missing macro, and + save it. +- Internal restructuring has renamed the macros for the string and + memory functions used in redconf.h. An existing redconf.h file from + v0.9 will need to be updated; for a file containing the old names, + the new config tool will default to using the (slow) Reliance Edge + string/memory functions; to use the C library or custom versions, + this will need to be selected in the configuration utility. +- Fix a bug which would result in an error when attempting to create a + name with one or more trailing path separators (such as + red_mkdir("/foo/bar/")). +- Fix a bug where an open handle for an inode on one volume would + prevent the same inode number from being deleted on a + different volume. + +FreeRTOS Port Changes + +- The implementation of the timestamp OS service no longer requires + that configUSE_TIMERS be set to 1. + +Reliance Edge v0.9 (Beta), April 2015 + +First public release. + + +Known Issues + +Visual Studio 2005 + +The Reliance Edge Win32 port (used for the host tools and the Win32 test +project) cannot be compiled by Visual Studio 2005. This is not going to +be fixed since VS2005 is an old toolset. Newer versions of Visual +Studio, starting with Visual Studio 2008, work just fine. diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/fse/fse.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/fse/fse.c new file mode 100644 index 0000000..4ad08ef --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/fse/fse.c @@ -0,0 +1,690 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implementation of the Reliance Edge FSE API. +*/ +#include + +#if REDCONF_API_FSE == 1 + +/** @defgroup red_group_fse The File System Essentials Interface + @{ +*/ + +#include +#include +#include + + +static REDSTATUS FseEnter(uint8_t bVolNum); +static void FseLeave(void); + + +static bool gfFseInited; /* Whether driver is initialized. */ + + +/** @brief Initialize the Reliance Edge file system driver. + + Prepares the Reliance Edge file system driver to be used. Must be the first + Reliance Edge function to be invoked: no volumes can be mounted until the + driver has been initialized. + + If this function is called when the Reliance Edge driver is already + initialized, it does nothing and returns success. + + This function is not thread safe: attempting to initialize from multiple + threads could leave things in a bad state. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. +*/ +REDSTATUS RedFseInit(void) +{ + REDSTATUS ret; + + if(gfFseInited) + { + ret = 0; + } + else + { + ret = RedCoreInit(); + + if(ret == 0) + { + gfFseInited = true; + } + } + + return ret; +} + + +/** @brief Uninitialize the Reliance Edge file system driver. + + Tears down the Reliance Edge file system driver. Cannot be used until all + Reliance Edge volumes are unmounted. A subsequent call to RedFseInit() + will initialize the driver again. + + If this function is called when the Reliance Edge driver is already + uninitialized, it does nothing and returns success. + + This function is not thread safe: attempting to uninitialize from multiple + threads could leave things in a bad state. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBUSY At least one volume is still mounted. +*/ +REDSTATUS RedFseUninit(void) +{ + REDSTATUS ret = 0; + + if(!gfFseInited) + { + ret = 0; + } + else + { + uint8_t bVolNum; + + #if REDCONF_TASK_COUNT > 1U + RedOsMutexAcquire(); + #endif + + for(bVolNum = 0U; bVolNum < REDCONF_VOLUME_COUNT; bVolNum++) + { + if(gaRedVolume[bVolNum].fMounted) + { + ret = -RED_EBUSY; + break; + } + } + + if(ret == 0) + { + gfFseInited = false; + } + + #if REDCONF_TASK_COUNT > 1U + RedOsMutexRelease(); + #endif + + if(ret == 0) + { + ret = RedCoreUninit(); + } + } + + return ret; +} + + +/** @brief Mount a file system volume. + + Prepares the file system volume to be accessed. Mount will fail if the + volume has never been formatted, or if the on-disk format is inconsistent + with the compile-time configuration. + + If the volume is already mounted, this function does nothing and returns + success. + + @param bVolNum The volume number of the volume to be mounted. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p bVolNum is an invalid volume number; or the driver is + uninitialized. + @retval -RED_EIO Volume not formatted, improperly formatted, or corrupt. +*/ +REDSTATUS RedFseMount( + uint8_t bVolNum) +{ + REDSTATUS ret; + + ret = FseEnter(bVolNum); + + if(ret == 0) + { + if(!gpRedVolume->fMounted) + { + ret = RedCoreVolMount(); + } + + FseLeave(); + } + + return ret; +} + + +/** @brief Unmount a file system volume. + + This function discards the in-memory state for the file system and marks it + as unmounted. Subsequent attempts to access the volume will fail until the + volume is mounted again. + + If unmount automatic transaction points are enabled, this function will + commit a transaction point prior to unmounting. If unmount automatic + transaction points are disabled, this function will unmount without + transacting, effectively discarding the working state. + + Before unmounting, this function will wait for any active file system + thread to complete by acquiring the FS mutex. The volume will be marked as + unmounted before the FS mutex is released, so subsequent FS threads will + possibly block and then see an error when attempting to access a volume + which is unmounting or unmounted. + + If the volume is already unmounted, this function does nothing and returns + success. + + @param bVolNum The volume number of the volume to be unmounted. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p bVolNum is an invalid volume number; or the driver is + uninitialized. + @retval -RED_EIO I/O error during unmount automatic transaction point. +*/ +REDSTATUS RedFseUnmount( + uint8_t bVolNum) +{ + REDSTATUS ret; + + ret = FseEnter(bVolNum); + + if(ret == 0) + { + if(gpRedVolume->fMounted) + { + ret = RedCoreVolUnmount(); + } + + FseLeave(); + } + + return ret; +} + + +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_FSE_FORMAT == 1) +/** @brief Format a file system volume. + + Uses the statically defined volume configuration. After calling this + function, the volume needs to be mounted -- see RedFseMount(). + + An error is returned if the volume is mounted. + + @param bVolNum The volume number of the volume to be formatted. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBUSY The volume is mounted. + @retval -RED_EINVAL @p bVolNum is an invalid volume number; or the driver is + uninitialized. + @retval -RED_EIO I/O error formatting the volume. +*/ +REDSTATUS RedFseFormat( + uint8_t bVolNum) +{ + REDSTATUS ret; + + ret = FseEnter(bVolNum); + + if(ret == 0) + { + ret = RedCoreVolFormat(); + + FseLeave(); + } + + return ret; +} +#endif + + +/** @brief Read from a file. + + Data which has not yet been written, but which is before the end-of-file + (sparse data), shall read as zeroes. A short read -- where the number of + bytes read is less than requested -- indicates that the requested read was + partially or, if zero bytes were read, entirely beyond the end-of-file. + + If @p ullFileOffset is at or beyond the maximum file size, it is treated + like any other read entirely beyond the end-of-file: no data is read and + zero is returned. + + @param bVolNum The volume number of the file to read. + @param ulFileNum The file number of the file to read. + @param ullFileOffset The file offset to read from. + @param ulLength The number of bytes to read. + @param pBuffer The buffer to populate with the data read. Must be + at least ulLength bytes in size. + + @return The number of bytes read (nonnegative) or a negated ::REDSTATUS + code indicating the operation result (negative). + + @retval >=0 The number of bytes read from the file. + @retval -RED_EBADF @p ulFileNum is not a valid file number. + @retval -RED_EINVAL @p bVolNum is an invalid volume number or not mounted; + or @p pBuffer is `NULL`; or @p ulLength exceeds + INT32_MAX and cannot be returned properly. + @retval -RED_EIO A disk I/O error occurred. +*/ +int32_t RedFseRead( + uint8_t bVolNum, + uint32_t ulFileNum, + uint64_t ullFileOffset, + uint32_t ulLength, + void *pBuffer) +{ + int32_t ret; + + if(ulLength > (uint32_t)INT32_MAX) + { + ret = -RED_EINVAL; + } + else + { + ret = FseEnter(bVolNum); + } + + if(ret == 0) + { + uint32_t ulReadLen = ulLength; + + ret = RedCoreFileRead(ulFileNum, ullFileOffset, &ulReadLen, pBuffer); + + FseLeave(); + + if(ret == 0) + { + ret = (int32_t)ulReadLen; + } + } + + return ret; +} + + +#if REDCONF_READ_ONLY == 0 +/** @brief Write to a file. + + If the write extends beyond the end-of-file, the file size will be + increased. + + A short write -- where the number of bytes written is less than requested + -- indicates either that the file system ran out of space but was still + able to write some of the request; or that the request would have caused + the file to exceed the maximum file size, but some of the data could be + written prior to the file size limit. + + If an error is returned (negative return), either none of the data was + written or a critical error occurred (like an I/O error) and the file + system volume will be read-only. + + @param bVolNum The volume number of the file to write. + @param ulFileNum The file number of the file to write. + @param ullFileOffset The file offset to write at. + @param ulLength The number of bytes to write. + @param pBuffer The buffer containing the data to be written. Must + be at least ulLength bytes in size. + + @return The number of bytes written (nonnegative) or a negated ::REDSTATUS + code indicating the operation result (negative). + + @retval >0 The number of bytes written to the file. + @retval -RED_EBADF @p ulFileNum is not a valid file number. + @retval -RED_EFBIG No data can be written to the given file offset since + the resulting file size would exceed the maximum file + size. + @retval -RED_EINVAL @p bVolNum is an invalid volume number or not mounted; + or @p pBuffer is `NULL`; or @p ulLength exceeds + INT32_MAX and cannot be returned properly. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENOSPC No data can be written because there is insufficient + free space. + @retval -RED_EROFS The file system volume is read-only. +*/ +int32_t RedFseWrite( + uint8_t bVolNum, + uint32_t ulFileNum, + uint64_t ullFileOffset, + uint32_t ulLength, + const void *pBuffer) +{ + int32_t ret; + + if(ulLength > (uint32_t)INT32_MAX) + { + ret = -RED_EINVAL; + } + else + { + ret = FseEnter(bVolNum); + } + + if(ret == 0) + { + uint32_t ulWriteLen = ulLength; + + ret = RedCoreFileWrite(ulFileNum, ullFileOffset, &ulWriteLen, pBuffer); + + FseLeave(); + + if(ret == 0) + { + ret = (int32_t)ulWriteLen; + } + } + + return ret; +} +#endif + + +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_FSE_TRUNCATE == 1) +/** @brief Truncate a file (set the file size). + + Allows the file size to be increased, decreased, or to remain the same. If + the file size is increased, the new area is sparse (will read as zeroes). + If the file size is decreased, the data beyond the new end-of-file will + return to free space once it is no longer part of the committed state + (either immediately or after the next transaction point). + + This function can fail when the disk is full if @p ullNewFileSize is + non-zero. If decreasing the file size, this can be fixed by transacting and + trying again: Reliance Edge guarantees that it is possible to perform a + truncate of at least one file that decreases the file size after a + transaction point. If disk full transactions are enabled, this will happen + automatically. + + @param bVolNum The volume number of the file to truncate. + @param ulFileNum The file number of the file to truncate. + @param ullNewFileSize The new file size, in bytes. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBADF @p ulFileNum is not a valid file number. + @retval -RED_EFBIG @p ullNewFileSize exceeds the maximum file size. + @retval -RED_EINVAL @p bVolNum is an invalid volume number or not mounted. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENOSPC Insufficient free space to perform the truncate. + @retval -RED_EROFS The file system volume is read-only. +*/ +REDSTATUS RedFseTruncate( + uint8_t bVolNum, + uint32_t ulFileNum, + uint64_t ullNewFileSize) +{ + REDSTATUS ret; + + ret = FseEnter(bVolNum); + + if(ret == 0) + { + ret = RedCoreFileTruncate(ulFileNum, ullNewFileSize); + + FseLeave(); + } + + return ret; +} +#endif + + +/** @brief Retrieve the size of a file. + + @param bVolNum The volume number of the file whose size is being read. + @param ulFileNum The file number of the file whose size is being read. + + @return The size of the file (nonnegative) or a negated ::REDSTATUS code + indicating the operation result (negative). + + @retval >=0 The size of the file. + @retval -RED_EBADF @p ulFileNum is not a valid file number. + @retval -RED_EINVAL @p bVolNum is an invalid volume number or not mounted. + @retval -RED_EIO A disk I/O error occurred. +*/ +int64_t RedFseSizeGet( + uint8_t bVolNum, + uint32_t ulFileNum) +{ + int64_t ret; + + ret = FseEnter(bVolNum); + + if(ret == 0) + { + uint64_t ullSize; + + ret = RedCoreFileSizeGet(ulFileNum, &ullSize); + + FseLeave(); + + if(ret == 0) + { + /* Unless there is an on-disk format change, the maximum file size + is guaranteed to be less than INT64_MAX, and so it can be safely + returned in an int64_t. + */ + REDASSERT(ullSize < (uint64_t)INT64_MAX); + + ret = (int64_t)ullSize; + } + } + + return ret; +} + + +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_FSE_TRANSMASKSET == 1) +/** @brief Update the transaction mask. + + The following events are available: + + - #RED_TRANSACT_UMOUNT + - #RED_TRANSACT_WRITE + - #RED_TRANSACT_TRUNCATE + - #RED_TRANSACT_VOLFULL + + The #RED_TRANSACT_MANUAL macro (by itself) may be used to disable all + automatic transaction events. The #RED_TRANSACT_MASK macro is a bitmask of + all transaction flags, excluding those representing excluded functionality. + + Attempting to enable events for excluded functionality will result in an + error. + + @param bVolNum The volume number of the volume whose transaction mask + is being changed. + @param ulEventMask A bitwise-OR'd mask of automatic transaction events to + be set as the current transaction mode. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p bVolNum is an invalid volume number or not mounted; + or @p ulEventMask contains invalid bits. + @retval -RED_EROFS The file system volume is read-only. +*/ +REDSTATUS RedFseTransMaskSet( + uint8_t bVolNum, + uint32_t ulEventMask) +{ + REDSTATUS ret; + + ret = FseEnter(bVolNum); + + if(ret == 0) + { + ret = RedCoreTransMaskSet(ulEventMask); + + FseLeave(); + } + + return ret; +} +#endif + + +#if REDCONF_API_FSE_TRANSMASKGET == 1 +/** @brief Read the transaction mask. + + If the volume is read-only, the returned event mask is always zero. + + @param bVolNum The volume number of the volume whose transaction mask + is being retrieved. + @param pulEventMask Populated with a bitwise-OR'd mask of automatic + transaction events which represent the current + transaction mode for the volume. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p bVolNum is an invalid volume number or not mounted; + or @p pulEventMask is `NULL`. +*/ +REDSTATUS RedFseTransMaskGet( + uint8_t bVolNum, + uint32_t *pulEventMask) +{ + REDSTATUS ret; + + ret = FseEnter(bVolNum); + + if(ret == 0) + { + ret = RedCoreTransMaskGet(pulEventMask); + + FseLeave(); + } + + return ret; +} +#endif + + +#if REDCONF_READ_ONLY == 0 +/** @brief Commit a transaction point. + + Reliance Edge is a transactional file system. All modifications, of both + metadata and filedata, are initially working state. A transaction point + is a process whereby the working state atomically becomes the committed + state, replacing the previous committed state. Whenever Reliance Edge is + mounted, including after power loss, the state of the file system after + mount is the most recent committed state. Nothing from the committed + state is ever missing, and nothing from the working state is ever included. + + @param bVolNum The volume number of the volume to transact. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p bVolNum is an invalid volume number or not mounted. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EROFS The file system volume is read-only. +*/ +REDSTATUS RedFseTransact( + uint8_t bVolNum) +{ + REDSTATUS ret; + + ret = FseEnter(bVolNum); + + if(ret == 0) + { + ret = RedCoreVolTransact(); + + FseLeave(); + } + + return ret; +} +#endif + +/** @} */ + +/** @brief Enter the file system driver. + + @param bVolNum The volume to be accessed. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL The file system driver is uninitialized; or @p bVolNum + is not a valid volume number. +*/ +static REDSTATUS FseEnter( + uint8_t bVolNum) +{ + REDSTATUS ret; + + if(gfFseInited) + { + #if REDCONF_TASK_COUNT > 1U + RedOsMutexAcquire(); + #endif + + /* This also serves to range-check the volume number (even in single + volume configurations). + */ + ret = RedCoreVolSetCurrent(bVolNum); + + #if REDCONF_TASK_COUNT > 1U + if(ret != 0) + { + RedOsMutexRelease(); + } + #endif + } + else + { + ret = -RED_EINVAL; + } + + return ret; +} + + +/** @brief Leave the file system driver. +*/ +static void FseLeave(void) +{ + REDASSERT(gfFseInited); + + #if REDCONF_TASK_COUNT > 1U + RedOsMutexRelease(); + #endif +} + + +#endif /* REDCONF_API_FSE == 1 */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redapimacs.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redapimacs.h new file mode 100644 index 0000000..13de409 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redapimacs.h @@ -0,0 +1,112 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Defines macros used to interact with the Reliance Edge API. +*/ +#ifndef REDAPIMACS_H +#define REDAPIMACS_H + + +/** Clear all events: manual transactions only. */ +#define RED_TRANSACT_MANUAL 0x00000000U + +/** Transact prior to unmounting in red_umount() or RedFseUnmount(). */ +#define RED_TRANSACT_UMOUNT 0x00000001U + +/** Transact after a successful red_open() which created a file. */ +#define RED_TRANSACT_CREAT 0x00000002U + +/** Transact after a successful red_unlink() or red_rmdir(). */ +#define RED_TRANSACT_UNLINK 0x00000004U + +/** Transact after a successful red_mkdir(). */ +#define RED_TRANSACT_MKDIR 0x00000008U + +/** Transact after a successful red_rename(). */ +#define RED_TRANSACT_RENAME 0x00000010U + +/** Transact after a successful red_link(). */ +#define RED_TRANSACT_LINK 0x00000020U + +/** Transact after a successful red_close(). */ +#define RED_TRANSACT_CLOSE 0x00000040U + +/** Transact after a successful red_write() or RedFseWrite(). */ +#define RED_TRANSACT_WRITE 0x00000080U + +/** Transact after a successful red_fsync(). */ +#define RED_TRANSACT_FSYNC 0x00000100U + +/** Transact after a successful red_ftruncate(), RedFseTruncate(), or red_open() with RED_O_TRUNC that actually truncates. */ +#define RED_TRANSACT_TRUNCATE 0x00000200U + +/** Transact to free space in disk full situations. */ +#define RED_TRANSACT_VOLFULL 0x00000400U + +#if REDCONF_READ_ONLY == 1 + +/** Mask of all supported automatic transaction events. */ +#define RED_TRANSACT_MASK 0U + +#elif REDCONF_API_POSIX == 1 + +/** @brief Mask of all supported automatic transaction events. +*/ +#define RED_TRANSACT_MASK \ +( \ + RED_TRANSACT_UMOUNT | \ + RED_TRANSACT_CREAT | \ + ((REDCONF_API_POSIX_UNLINK == 1) ? RED_TRANSACT_UNLINK : 0U) | \ + ((REDCONF_API_POSIX_MKDIR == 1) ? RED_TRANSACT_MKDIR : 0U) | \ + ((REDCONF_API_POSIX_RENAME == 1) ? RED_TRANSACT_RENAME : 0U) | \ + ((REDCONF_API_POSIX_LINK == 1) ? RED_TRANSACT_LINK : 0U) | \ + RED_TRANSACT_CLOSE | \ + RED_TRANSACT_WRITE | \ + RED_TRANSACT_FSYNC | \ + ((REDCONF_API_POSIX_FTRUNCATE == 1) ? RED_TRANSACT_TRUNCATE : 0U) | \ + RED_TRANSACT_VOLFULL \ +) + +#else /* REDCONF_API_FSE == 1 */ + +/** @brief Mask of all supported automatic transaction events. +*/ +#define RED_TRANSACT_MASK \ +( \ + RED_TRANSACT_UMOUNT | \ + RED_TRANSACT_WRITE | \ + ((REDCONF_API_FSE_TRUNCATE == 1) ? RED_TRANSACT_TRUNCATE : 0U) | \ + RED_TRANSACT_VOLFULL \ +) + +#endif /* REDCONF_READ_ONLY */ + +#if (REDCONF_TRANSACT_DEFAULT & RED_TRANSACT_MASK) != REDCONF_TRANSACT_DEFAULT +#error "Configuration error: invalid value of REDCONF_TRANSACT_DEFAULT" +#endif + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redconfigchk.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redconfigchk.h new file mode 100644 index 0000000..8576a42 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redconfigchk.h @@ -0,0 +1,349 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Compile-time validity checks for the REDCONF macros. +*/ +#ifndef REDCONFIGCHK_H +#define REDCONFIGCHK_H + +#ifdef RED_CONFIG_MINCOMPAT_VER + #if (RED_VERSION_VAL & 0xFFFFFF00U) < (RED_CONFIG_MINCOMPAT_VER & 0xFFFFFF00U) + /* This indicates that your configuration files were generated by a + version of the Reliance Edge Configuration Utility that is designed + for a more recent version of Reliance Edge and is no longer compatible + with this version. You can update to the most recent version of + Reliance Edge or contact RelianceEdgeSupport@datalight.com to obtain + the correct legacy version of the Configuration Utility. + */ + #error "Your configuration is not compatible with this version of Reliance Edge. Please download the latest version of Reliance Edge or recreate your configuration with an older version of the Configuration Utility." + #endif +#endif + +#ifndef REDCONF_READ_ONLY + #error "Configuration error: REDCONF_READ_ONLY must be defined." +#endif +#ifndef REDCONF_API_POSIX + #error "Configuration error: REDCONF_API_POSIX must be defined." +#endif +#ifndef REDCONF_API_FSE + #error "Configuration error: REDCONF_API_FSE must be defined." +#endif + +#if REDCONF_API_POSIX == 1 + #ifndef REDCONF_API_POSIX_FORMAT + #error "Configuration error: REDCONF_API_POSIX_FORMAT must be defined." + #endif + #ifndef REDCONF_API_POSIX_UNLINK + #error "Configuration error: REDCONF_API_POSIX_UNLINK must be defined." + #endif + #ifndef REDCONF_API_POSIX_MKDIR + #error "Configuration error: REDCONF_API_POSIX_MKDIR must be defined." + #endif + #ifndef REDCONF_API_POSIX_RMDIR + #error "Configuration error: REDCONF_API_POSIX_RMDIR must be defined." + #endif + #ifndef REDCONF_API_POSIX_RENAME + #error "Configuration error: REDCONF_API_POSIX_RENAME must be defined." + #endif + #ifndef REDCONF_API_POSIX_LINK + #error "Configuration error: REDCONF_API_POSIX_LINK must be defined." + #endif + #ifndef REDCONF_API_POSIX_FTRUNCATE + #error "Configuration error: REDCONF_API_POSIX_FTRUNCATE must be defined." + #endif + #ifndef REDCONF_API_POSIX_READDIR + #error "Configuration error: REDCONF_API_POSIX_READDIR must be defined." + #endif + #ifndef REDCONF_NAME_MAX + #error "Configuration error: REDCONF_NAME_MAX must be defined." + #endif + #ifndef REDCONF_PATH_SEPARATOR + #error "Configuration error: REDCONF_PATH_SEPARATOR must be defined." + #endif + #ifndef REDCONF_RENAME_ATOMIC + #error "Configuration error: REDCONF_RENAME_ATOMIC must be defined." + #endif + #ifndef REDCONF_HANDLE_COUNT + #error "Configuration error: REDCONF_HANDLE_COUNT must be defined." + #endif +#endif +#if REDCONF_API_FSE == 1 + #ifndef REDCONF_API_FSE_FORMAT + #error "Configuration error: REDCONF_API_FSE_FORMAT must be defined." + #endif + #ifndef REDCONF_API_FSE_TRUNCATE + #error "Configuration error: REDCONF_API_FSE_TRUNCATE must be defined." + #endif + #ifndef REDCONF_API_FSE_TRANSMASKSET + #error "Configuration error: REDCONF_API_FSE_TRANSMASKSET must be defined." + #endif + #ifndef REDCONF_API_FSE_TRANSMASKGET + #error "Configuration error: REDCONF_API_FSE_TRANSMASKGET must be defined." + #endif +#endif + +#ifndef REDCONF_TASK_COUNT + #error "Configuration error: REDCONF_TASK_COUNT must be defined." +#endif +#ifndef REDCONF_ENDIAN_BIG + #error "Configuration error: REDCONF_ENDIAN_BIG must be defined." +#endif +#ifndef REDCONF_ALIGNMENT_SIZE + #error "Configuration error: REDCONF_ALIGNMENT_SIZE must be defined." +#endif +#ifndef REDCONF_CRC_ALGORITHM + #error "Configuration error: REDCONF_CRC_ALGORITHM must be defined." +#endif +#ifndef REDCONF_INODE_TIMESTAMPS + #error "Configuration error: REDCONF_INODE_TIMESTAMPS must be defined." +#endif +#ifndef REDCONF_ATIME + #error "Configuration error: REDCONF_ATIME must be defined." +#endif +#ifndef REDCONF_DIRECT_POINTERS + #error "Configuration error: REDCONF_DIRECT_POINTERS must be defined." +#endif +#ifndef REDCONF_INDIRECT_POINTERS + #error "Configuration error: REDCONF_INDIRECT_POINTERS must be defined." +#endif +#ifndef REDCONF_INODE_BLOCKS + #error "Configuration error: REDCONF_INODE_BLOCKS must be defined." +#endif +#ifndef REDCONF_IMAP_EXTERNAL + #error "Configuration error: REDCONF_IMAP_EXTERNAL must be defined." +#endif +#ifndef REDCONF_IMAP_INLINE + #error "Configuration error: REDCONF_IMAP_INLINE must be defined." +#endif +#ifndef REDCONF_OUTPUT + #error "Configuration error: REDCONF_OUTPUT must be defined." +#endif +#ifndef REDCONF_ASSERTS + #error "Configuration error: REDCONF_ASSERTS must be defined." +#endif +#ifndef REDCONF_TRANSACT_DEFAULT + #error "Configuration error: REDCONF_TRANSACT_DEFAULT must be defined." +#endif +#ifndef REDCONF_BUFFER_COUNT + #error "Configuration error: REDCONF_BUFFER_COUNT must be defined." +#endif +#ifndef REDCONF_BLOCK_SIZE + #error "Configuration error: REDCONF_BLOCK_SIZE must be defined." +#endif +#ifndef REDCONF_VOLUME_COUNT + #error "Configuration error: REDCONF_VOLUME_COUNT must be defined." +#endif +#ifndef REDCONF_DISCARDS + /* Reliance Edge 1.0.5 and below did not have REDCONF_DISCARDS. You can + fix this error by downloading the latest version of the Configuration + Utility (assuming you are using the latest version of Reliance Edge) + from http://www.datalight.com/reliance-edge, loading your redconf.c + and redconf.h files, and saving them again, replacing the original + files. + */ + #error "Configuration error: your redconf.h is not compatible. Update your redconf files with a compatible version of the configuration utility." +#endif +#ifndef REDCONF_IMAGE_BUILDER + #error "Configuration error: REDCONF_IMAGE_BUILDER must be defined." +#endif +#ifndef REDCONF_CHECKER + #error "Configuration error: REDCONF_CHECKER must be defined." +#endif + + +#if (REDCONF_READ_ONLY != 0) && (REDCONF_READ_ONLY != 1) + #error "Configuration error: REDCONF_READ_ONLY must be either 0 or 1" +#endif + +#if (REDCONF_API_POSIX != 0) && (REDCONF_API_POSIX != 1) + #error "Configuration error: REDCONF_API_POSIX must be either 0 or 1." +#endif +#if (REDCONF_API_FSE != 0) && (REDCONF_API_FSE != 1) + #error "Configuration error: REDCONF_API_FSE must be either 0 or 1." +#endif + +#if (REDCONF_API_FSE == 0) && (REDCONF_API_POSIX == 0) + #error "Configuration error: either REDCONF_API_FSE or REDCONF_API_POSIX must be set to 1." +#endif + +#if REDCONF_API_POSIX == 1 + #if REDCONF_API_FSE != 0 + #error "Configuration error: REDCONF_API_FSE must be 0 if REDCONF_API_POSIX is 1" + #endif + + #if (REDCONF_API_POSIX_FORMAT != 0) && (REDCONF_API_POSIX_FORMAT != 1) + #error "Configuration error: REDCONF_API_POSIX_FORMAT must be either 0 or 1." + #endif + + #if (REDCONF_API_POSIX_UNLINK != 0) && (REDCONF_API_POSIX_UNLINK != 1) + #error "Configuration error: REDCONF_API_POSIX_UNLINK must be either 0 or 1." + #endif + + #if (REDCONF_API_POSIX_MKDIR != 0) && (REDCONF_API_POSIX_MKDIR != 1) + #error "Configuration error: REDCONF_API_POSIX_MKDIR must be either 0 or 1." + #endif + + #if (REDCONF_API_POSIX_RMDIR != 0) && (REDCONF_API_POSIX_RMDIR != 1) + #error "Configuration error: REDCONF_API_POSIX_RMDIR must be either 0 or 1." + #endif + + #if (REDCONF_API_POSIX_RENAME != 0) && (REDCONF_API_POSIX_RENAME != 1) + #error "Configuration error: REDCONF_API_POSIX_RENAME must be either 0 or 1." + #endif + + #if (REDCONF_API_POSIX_LINK != 0) && (REDCONF_API_POSIX_LINK != 1) + #error "Configuration error: REDCONF_API_POSIX_LINK must be either 0 or 1." + #endif + + #if (REDCONF_API_POSIX_FTRUNCATE != 0) && (REDCONF_API_POSIX_FTRUNCATE != 1) + #error "Configuration error: REDCONF_API_POSIX_FTRUNCATE must be either 0 or 1." + #endif + + #if (REDCONF_API_POSIX_READDIR != 0) && (REDCONF_API_POSIX_READDIR != 1) + #error "Configuration error: REDCONF_API_POSIX_READDIR must be either 0 or 1." + #endif + + #if (REDCONF_NAME_MAX < 1U) || (REDCONF_NAME_MAX > (REDCONF_BLOCK_SIZE - 4U)) + #error "Configuration error: invalid value of REDCONF_NAME_MAX" + #endif + + #if (REDCONF_PATH_SEPARATOR < 1) || (REDCONF_PATH_SEPARATOR > 127) + #error "Configuration error: invalid value of REDCONF_PATH_SEPARATOR" + #endif + + #if (REDCONF_RENAME_ATOMIC != 0) && (REDCONF_RENAME_ATOMIC != 1) + #error "Configuration error: REDCONF_RENAME_ATOMIC must be either 0 or 1." + #endif + + #if (REDCONF_HANDLE_COUNT < 1U) || (REDCONF_HANDLE_COUNT > 4096U) + #error "Configuration error: invalid value of REDCONF_HANDLE_COUNT" + #endif +#endif +#if REDCONF_API_FSE == 1 + #if (REDCONF_API_FSE_FORMAT != 0) && (REDCONF_API_FSE_FORMAT != 1) + #error "Configuration error: REDCONF_API_FSE_FORMAT must be either 0 or 1." + #endif + + #if (REDCONF_API_FSE_TRUNCATE != 0) && (REDCONF_API_FSE_TRUNCATE != 1) + #error "Configuration error: REDCONF_API_FSE_TRUNCATE must be either 0 or 1." + #endif + + #if (REDCONF_API_FSE_TRANSMASKSET != 0) && (REDCONF_API_FSE_TRANSMASKSET != 1) + #error "Configuration error: REDCONF_API_FSE_TRANSMASKSET must be either 0 or 1." + #endif + + #if (REDCONF_API_FSE_TRANSMASKGET != 0) && (REDCONF_API_FSE_TRANSMASKGET != 1) + #error "Configuration error: REDCONF_API_FSE_TRANSMASKGET must be either 0 or 1." + #endif +#endif + +#if REDCONF_TASK_COUNT < 1U + #error "Configuration error: invalid value of REDCONF_TASK_COUNT" +#endif + +#if (REDCONF_ENDIAN_BIG != 0) && (REDCONF_ENDIAN_BIG != 1) + #error "Configuration error: REDCONF_ENDIAN_BIG must be either 0 or 1." +#endif + +#if (REDCONF_ALIGNMENT_SIZE != 1U) && (REDCONF_ALIGNMENT_SIZE != 2U) && (REDCONF_ALIGNMENT_SIZE != 4U) && (REDCONF_ALIGNMENT_SIZE != 8U) + #error "Configuration error: invalid value REDCONF_ALIGNMENT_SIZE" +#endif + +/* REDCONF_CRC_ALGORITHM checked in crc.c +*/ + +#if (REDCONF_INODE_TIMESTAMPS != 0) && (REDCONF_INODE_TIMESTAMPS != 1) + #error "Configuration error: REDCONF_INODE_TIMESTAMPS must be either 0 or 1." +#endif + +#if (REDCONF_ATIME != 0) && (REDCONF_ATIME != 1) + #error "Configuration error: REDCONF_ATIME must be either 0 or 1." +#endif + +#if (REDCONF_INODE_TIMESTAMPS == 0) && (REDCONF_ATIME == 1) + #error "Configuration error: REDCONF_ATIME must be 0 when REDCONF_INODE_TIMESTAMPS is 0." +#endif + +/* REDCONF_DIRECT_POINTERS and REDCONF_INDIRECT_POINTERS checked in rednodes.h +*/ + +#if (REDCONF_INODE_BLOCKS != 0) && (REDCONF_INODE_BLOCKS != 1) + #error "Configuration error: REDCONF_INODE_BLOCKS must be either 0 or 1." +#endif + +/* Further validity checking of imap specs done in RelCoreInit() +*/ +#if (REDCONF_IMAP_EXTERNAL != 0) && (REDCONF_IMAP_EXTERNAL != 1) + #error "Configuration error: REDCONF_IMAP_EXTERNAL must be either 0 or 1." +#endif +#if (REDCONF_IMAP_INLINE != 0) && (REDCONF_IMAP_INLINE != 1) + #error "Configuration error: REDCONF_IMAP_INLINE must be either 0 or 1." +#endif +#if (REDCONF_IMAP_INLINE == 0) && (REDCONF_IMAP_EXTERNAL == 0) + #error "Configuration error: At least one of REDCONF_IMAP_INLINE and REDCONF_IMAP_EXTERNAL must be set" +#endif + +#if (REDCONF_OUTPUT != 0) && (REDCONF_OUTPUT != 1) + #error "Configuration error: REDCONF_OUTPUT must be either 0 or 1." +#endif + +#if (REDCONF_ASSERTS != 0) && (REDCONF_ASSERTS != 1) + #error "Configuration error: REDCONF_ASSERTS must be either 0 or 1." +#endif + +/* REDCONF_BLOCK_SIZE checked in redmacs.h +*/ + +#if (REDCONF_VOLUME_COUNT < 1U) || (REDCONF_VOLUME_COUNT > 255U) + #error "REDCONF_VOLUME_COUNT must be an integer between 1 and 255" +#endif + +#if (REDCONF_DISCARDS != 0) && (REDCONF_DISCARDS != 1) + #error "Configuration error: REDCONF_DISCARDS must be either 0 or 1." +#endif + +/* REDCONF_BUFFER_COUNT lower limit checked in buffer.c +*/ +#if REDCONF_BUFFER_COUNT > 255U + #error "REDCONF_BUFFER_COUNT cannot be greater than 255" +#endif + +#if (REDCONF_IMAGE_BUILDER != 0) && (REDCONF_IMAGE_BUILDER != 1) + #error "Configuration error: REDCONF_IMAGE_BUILDER must be either 0 or 1." +#endif + +#if (REDCONF_CHECKER != 0) && (REDCONF_CHECKER != 1) + #error "Configuration error: REDCONF_CHECKER must be either 0 or 1." +#endif + + +#if (REDCONF_DISCARDS == 1) && (RED_KIT == RED_KIT_GPL) + #error "REDCONF_DISCARDS not supported in Reliance Edge under GPL. Contact sales@datalight.com to upgrade." +#endif + + +#endif + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redcoreapi.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redcoreapi.h new file mode 100644 index 0000000..20c6691 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redcoreapi.h @@ -0,0 +1,97 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file +*/ +#ifndef REDCOREAPI_H +#define REDCOREAPI_H + + +#include + + +REDSTATUS RedCoreInit(void); +REDSTATUS RedCoreUninit(void); + +REDSTATUS RedCoreVolSetCurrent(uint8_t bVolNum); + +#if FORMAT_SUPPORTED +REDSTATUS RedCoreVolFormat(void); +#endif +#if REDCONF_CHECKER == 1 +REDSTATUS RedCoreVolCheck(void); +#endif +REDSTATUS RedCoreVolMount(void); +REDSTATUS RedCoreVolUnmount(void); +#if REDCONF_READ_ONLY == 0 +REDSTATUS RedCoreVolTransact(void); +#endif +#if REDCONF_API_POSIX == 1 +REDSTATUS RedCoreVolStat(REDSTATFS *pStatFS); +#endif + +#if (REDCONF_READ_ONLY == 0) && ((REDCONF_API_POSIX == 1) || (REDCONF_API_FSE_TRANSMASKSET == 1)) +REDSTATUS RedCoreTransMaskSet(uint32_t ulEventMask); +#endif +#if (REDCONF_API_POSIX == 1) || (REDCONF_API_FSE_TRANSMASKGET == 1) +REDSTATUS RedCoreTransMaskGet(uint32_t *pulEventMask); +#endif + +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) +REDSTATUS RedCoreCreate(uint32_t ulPInode, const char *pszName, bool fDir, uint32_t *pulInode); +#endif +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) && (REDCONF_API_POSIX_LINK == 1) +REDSTATUS RedCoreLink(uint32_t ulPInode, const char *pszName, uint32_t ulInode); +#endif +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) && ((REDCONF_API_POSIX_UNLINK == 1) || (REDCONF_API_POSIX_RMDIR == 1)) +REDSTATUS RedCoreUnlink(uint32_t ulPInode, const char *pszName); +#endif +#if REDCONF_API_POSIX == 1 +REDSTATUS RedCoreLookup(uint32_t ulPInode, const char *pszName, uint32_t *pulInode); +#endif +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) && (REDCONF_API_POSIX_RENAME == 1) +REDSTATUS RedCoreRename(uint32_t ulSrcPInode, const char *pszSrcName, uint32_t ulDstPInode, const char *pszDstName); +#endif +#if REDCONF_API_POSIX == 1 +REDSTATUS RedCoreStat(uint32_t ulInode, REDSTAT *pStat); +#endif +#if REDCONF_API_FSE == 1 +REDSTATUS RedCoreFileSizeGet(uint32_t ulInode, uint64_t *pullSize); +#endif + +REDSTATUS RedCoreFileRead(uint32_t ulInode, uint64_t ullStart, uint32_t *pulLen, void *pBuffer); +#if REDCONF_READ_ONLY == 0 +REDSTATUS RedCoreFileWrite(uint32_t ulInode, uint64_t ullStart, uint32_t *pulLen, const void *pBuffer); +#endif +#if TRUNCATE_SUPPORTED +REDSTATUS RedCoreFileTruncate(uint32_t ulInode, uint64_t ullSize); +#endif + +#if (REDCONF_API_POSIX == 1) && (REDCONF_API_POSIX_READDIR == 1) +REDSTATUS RedCoreDirRead(uint32_t ulInode, uint32_t *pulPos, char *pszName, uint32_t *pulInode); +#endif + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/reddeviations.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/reddeviations.h new file mode 100644 index 0000000..302f333 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/reddeviations.h @@ -0,0 +1,224 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief This header contains macros which deviate from MISRA C:2012 +*/ +#ifndef REDDEVIATIONS_H +#define REDDEVIATIONS_H + + +/** @brief Append a suffix to a constant so that it is an unsigned 64-bit value. + + Usages of this macro deviate from MISRA C:2012 Rule 1.2 (advisory). The + rule prohibits the use of language extensions. The ULL suffix became part + of the C standard with C99. Since this code base adheres to C89, use of + this suffix is a language extension. Reliance Edge needs to deal with + 64-bit quantities, which by convention are explicitly suffixed. In at + least one case, with the INODE_SIZE_MAX macro, the code needs a way to force + a constant to be 64-bits even though its value is not so large that it would + be automatically promoted to 64-bits. Thus the need for this macro and the + deviation. In practice, the ULL suffix has proven to be a nearly universal + extension among C89 compilers. + + As rule 19.2 is advisory, a deviation record is not required. This notice + is the only record of the deviation. PC-Lint does not issue an error for + this deviation so there is no error inhibition option. + + Usages of this macro also deviate from MISRA C:2012 Rule 20.10 (advisory). + The rule prohibits use of the ## preprocessor operator. The code is not + obscure, and the operator is used only once, so this is deemed to be safe. + + As rule 20.10 is advisory, a deviation record is not required. This notice + is the only record of the deviation. + + Consistent use of this macro, even in non MISRA C code, is encouraged to + make it easier to search for 64-bit values. + +*/ +#define UINT64_SUFFIX(number) (number##ULL) + + +/** @brief Append a suffix to a constant so that it is a signed 64-bit value. + + Usages of this macro deviate from MISRA C:2012 Rule 1.2 (advisory). See the + description of UINT64_SUFFIX() for details. + + Usages of this macro deviate from MISRA C:2012 Rule 20.10 (advisory). See + the description of UINT64_SUFFIX() for details. +*/ +#define INT64_SUFFIX(number) (number##LL) + + +/** @brief Cast a pointer to a const uint8_t pointer. + + All usages of this macro deviate from MISRA C:2012 Rule 11.5 (advisory). + Because there are no alignment requirements for a uint8_t pointer, this is + safe. However, it is technically a deviation from the rule. + + As Rule 11.5 is advisory, a deviation record is not required. This notice + and the PC-Lint error inhibition option are the only records of the + deviation. +*/ +#define CAST_VOID_PTR_TO_CONST_UINT8_PTR(PTR) ((const uint8_t *)(PTR)) + + +/** @brief Cast a pointer to a uint8_t pointer. + + All usages of this macro deviate from MISRA C:2012 Rule 11.5 (advisory). + Because there are no alignment requirements for a uint8_t pointer, this is + safe. However, it is technically a deviation from the rule. + + As Rule 11.5 is advisory, a deviation record is not required. This notice + and the PC-Lint error inhibition option are the only records of the + deviation. +*/ +#define CAST_VOID_PTR_TO_UINT8_PTR(PTR) ((uint8_t *)(PTR)) + + +/** @brief Cast a pointer to a const uint32_t pointer. + + Usages of this macro may deviate from MISRA C:2012 Rule 11.5 (advisory). + It is only used in cases where the pointer is known to be aligned, and thus + it is safe to do so. + + As Rule 11.5 is advisory, a deviation record is not required. This notice + and the PC-Lint error inhibition option are the only records of the + deviation. + + Usages of this macro may deviate from MISRA C:2012 Rule 11.3 (required). + As Rule 11.3 is required, a separate deviation record is required. + + Regarding the cast to (const void *): this is there to placate some + compilers which emit warnings when a type with lower alignment requirements + (such as const uint8_t *) is cast to a type with higher alignment + requirements. In the places where this macro is used, the pointer is + checked to be of sufficient alignment. +*/ +#define CAST_CONST_UINT32_PTR(PTR) ((const uint32_t *)(const void *)(PTR)) + + +/** @brief Cast a pointer to a pointer to (void **). + + Usages of this macro deviate from MISRA C:2012 Rule 11.3 (required). + It is only used for populating a node structure pointer with a buffer + pointer. Buffer pointers are 8-byte aligned, thus it is safe to do so. + + As Rule 11.3 is required, a separate deviation record is required. +*/ +#define CAST_VOID_PTR_PTR(PTRPTR) ((void **)(PTRPTR)) + + +/** @brief Create a two-dimensional byte array which is safely aligned. + + Usages of this macro deviate from MISRA C:2012 Rule 19.2 (advisory). + A union is required to force alignment of the block buffers, which are used + to access metadata nodes, which must be safely aligned for 64-bit types. + + As rule 19.2 is advisory, a deviation record is not required. This notice + and the PC-Lint error inhibition option are the only records of the + deviation. +*/ +#define ALIGNED_2D_BYTE_ARRAY(un, nam, size1, size2) \ + union \ + { \ + uint8_t nam[size1][size2]; \ + uint64_t DummyAlign; \ + } un + + +/** @brief Determine whether RedMemMove() must copy memory in the forward + direction, instead of in the reverse. + + In order to copy between overlapping memory regions, RedMemMove() must copy + forward if the destination memory is lower, and backward if the destination + memory is higher. Failure to do so would yield incorrect results. + + The only way to make this determination without gross inefficiency is to + use pointer comparison. Pointer comparisons are undefined unless both + pointers point within the same object or array (or one element past the end + of the array); see section 6.3.8 of ANSI C89. While RedMemMove() is + normally only used when memory regions overlap, which would not result in + undefined behavior, it (like memmove()) is supposed to work even for non- + overlapping regions, which would make this function invoke undefined + behavior. Experience has shown the pointer comparisons of this sort behave + intuitively on common platforms, even though the behavior is undefined. For + those platforms where this is not the case, this implementation of memmove() + should be replaced with an alternate one. + + Usages of this macro deviate from MISRA-C:2012 Rule 18.3 (required). As + Rule 18.3 is required, a separate deviation record is required. +*/ +#define MEMMOVE_MUST_COPY_FORWARD(dest, src) ((dest) < (src)) + + +/** @brief Cast a pointer to a (const DIRENT *). + + Usages of this macro deviate from MISRA-C:2012 Rule 11.3 (required). + It is used for populating a directory entry structure pointer with a + buffer pointer. Buffer pointers are 8-byte aligned, and DIRENT only + requires 4-byte alignment, thus the typecast is safe. + + As Rule 11.3 is required, a separate deviation record is required. +*/ +#define CAST_CONST_DIRENT_PTR(PTR) ((const DIRENT *)(PTR)) + + +/** @brief Determine whether a pointer is aligned. + + A pointer is aligned if its address is an even multiple of + ::REDCONF_ALIGNMENT_SIZE. + + This is used in the slice-by-8 RedCrc32Update() function, which needs to + know whether a pointer is aligned, since the slice-by-8 algorithm needs to + access the memory in an aligned fashion, and if the pointer is not aligned, + this can result in faults or suboptimal performance (depending on platform). + + There is no way to perform this check without deviating from MISRA C rules + against casting pointers to integer types. Usage of this macro deviates + from MISRA C:2012 Rule 11.4 (advisory). The main rationale the rule cites + against converting pointers to integers is that the chosen integer type may + not be able to represent the pointer; this is a non-issue here since we use + uintptr_t. The text says the rule still applies when using uintptr_t due to + concern about unaligned pointers, but that is not an issue here since the + integer value of the pointer is not saved and not converted back into a + pointer and dereferenced. The result of casting a pointer to a sufficiently + large integer is implementation-defined, but macros similar to this one have + been used by Datalight for a long time in a wide variety of environments and + they have always worked as expected. + + As Rule 11.4 is advisory, a deviation record is not required. This notice + and the PC-Lint error inhibition option are the only records of the + deviation. + + @note PC-Lint also thinks this macro as it is used below violates Rule 11.6 + (required). This is a false positive, since Rule 11.6 only applies to + void pointers. Below, we use it on a pointer-to-object (uint8_t *), + which is covered by Rule 11.4. +*/ +#define IS_ALIGNED_PTR(ptr) (((uintptr_t)(ptr) & (REDCONF_ALIGNMENT_SIZE - 1U)) == 0U) + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/rederrno.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/rederrno.h new file mode 100644 index 0000000..9b71060 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/rederrno.h @@ -0,0 +1,114 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Error values for Reliance Edge APIs +*/ +#ifndef REDERRNO_H +#define REDERRNO_H + + +/** @brief Return type for Reliance Edge error values. +*/ +typedef int32_t REDSTATUS; + + +/* The errno numbers are the same as Linux. +*/ + +/** Operation not permitted. */ +#define RED_EPERM 1 + +/** No such file or directory. */ +#define RED_ENOENT 2 + +/** I/O error. */ +#define RED_EIO 5 + +/** Bad file number. */ +#define RED_EBADF 9 + +/** Out of memory */ +#define RED_ENOMEM 12 + +/** Device or resource busy. */ +#define RED_EBUSY 16 + +/** File exists. */ +#define RED_EEXIST 17 + +/** Cross-device link. */ +#define RED_EXDEV 18 + +/** Not a directory. */ +#define RED_ENOTDIR 20 + +/** Is a directory. */ +#define RED_EISDIR 21 + +/** Invalid argument. */ +#define RED_EINVAL 22 + +/** File table overflow. */ +#define RED_ENFILE 23 + +/** Too many open files. */ +#define RED_EMFILE 24 + +/** File too large. */ +#define RED_EFBIG 27 + +/** No space left on device. */ +#define RED_ENOSPC 28 + +/** Read-only file system. */ +#define RED_EROFS 30 + +/** Too many links. */ +#define RED_EMLINK 31 + +/** Math result not representable. */ +#define RED_ERANGE 34 + +/** File name too long. */ +#define RED_ENAMETOOLONG 36 + +/** Function not implemented. */ +#define RED_ENOSYS 38 + +/** Directory not empty. */ +#define RED_ENOTEMPTY 39 + +/** No data available. */ +#define RED_ENODATA 61 + +/** Too many users. */ +#define RED_EUSERS 87 + +/** Nothing will be okay ever again. */ +#define RED_EFUBAR RED_EINVAL + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redexclude.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redexclude.h new file mode 100644 index 0000000..01a003c --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redexclude.h @@ -0,0 +1,53 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file +*/ +#ifndef REDEXCLUDE_H +#define REDEXCLUDE_H + + +#define DELETE_SUPPORTED \ + ( \ + (REDCONF_READ_ONLY == 0) \ + && ( (REDCONF_API_POSIX == 1) \ + && ( (REDCONF_API_POSIX_RMDIR == 1) \ + || (REDCONF_API_POSIX_UNLINK == 1) \ + || ((REDCONF_API_POSIX_RENAME == 1) && (REDCONF_RENAME_ATOMIC == 1))))) + +#define TRUNCATE_SUPPORTED \ + ( \ + (REDCONF_READ_ONLY == 0) \ + && ( ((REDCONF_API_POSIX == 1) && (REDCONF_API_POSIX_FTRUNCATE == 1)) \ + || ((REDCONF_API_FSE == 1) && (REDCONF_API_FSE_TRUNCATE == 1)))) + +#define FORMAT_SUPPORTED \ + ( \ + (REDCONF_READ_ONLY == 0) \ + && ( ((REDCONF_API_POSIX == 1) && (REDCONF_API_POSIX_FORMAT == 1)) \ + || ((REDCONF_API_FSE == 1) && (REDCONF_API_FSE_FORMAT == 1)) \ + || (REDCONF_IMAGE_BUILDER == 1))) + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redfs.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redfs.h new file mode 100644 index 0000000..512d703 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redfs.h @@ -0,0 +1,46 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file +*/ +#ifndef REDFS_H +#define REDFS_H + + +#include +#include "redver.h" +#include "redconfigchk.h" +#include +#include "rederrno.h" +#include "reddeviations.h" +#include "redmacs.h" +#include "redapimacs.h" +#include "redutils.h" +#include "redosserv.h" +#include "redmisc.h" +#include "redexclude.h" + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redfse.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redfse.h new file mode 100644 index 0000000..3b0ef88 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redfse.h @@ -0,0 +1,105 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Interface for the Reliance Edge FSE API. + + The FSE (File Systems Essentials) API is a minimalist file system API + intended for simple use cases with a fixed number of statically-defined + files. It does not support creating or deleting files dynamically. Files + are referenced by a fixed file number, rather than by name; there are no + file names and no directories. There are also no file handles: files are + not opened or closed, and file offsets are given explicitly. + + If the FSE API is too limited to meet the needs of your application, + consider using the more feature-rich POSIX-like file system API instead. +*/ +#ifndef REDFSE_H +#define REDFSE_H + +/* This header is intended for application use; some applications are written + in C++. +*/ +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#if REDCONF_API_FSE == 1 + +#include +#include "redapimacs.h" +#include "rederrno.h" + + +/** @brief First valid file number. + + This macro can be used to statically define file numbers for given files, + as in the below example: + + ~~~{.c} + #define LOG_FILE (RED_FILENUM_FIRST_VALID) + #define DATABASE_FILE (RED_FILENUM_FIRST_VALID + 1U) + #define ICON1_FILE (RED_FILENUM_FIRST_VALID + 2U) + #define ICON2_FILE (RED_FILENUM_FIRST_VALID + 3U) + ~~~ +*/ +#define RED_FILENUM_FIRST_VALID (2U) + + +REDSTATUS RedFseInit(void); +REDSTATUS RedFseUninit(void); +REDSTATUS RedFseMount(uint8_t bVolNum); +REDSTATUS RedFseUnmount(uint8_t bVolNum); +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_FSE_FORMAT == 1) +REDSTATUS RedFseFormat(uint8_t bVolNum); +#endif +int32_t RedFseRead(uint8_t bVolNum, uint32_t ulFileNum, uint64_t ullFileOffset, uint32_t ulLength, void *pBuffer); +#if REDCONF_READ_ONLY == 0 +int32_t RedFseWrite(uint8_t bVolNum, uint32_t ulFileNum, uint64_t ullFileOffset, uint32_t ulLength, const void *pBuffer); +#endif +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_FSE_TRUNCATE == 1) +REDSTATUS RedFseTruncate(uint8_t bVolNum, uint32_t ulFileNum, uint64_t ullNewFileSize); +#endif +int64_t RedFseSizeGet(uint8_t bVolNum, uint32_t ulFileNum); +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_FSE_TRANSMASKSET == 1) +REDSTATUS RedFseTransMaskSet(uint8_t bVolNum, uint32_t ulEventMask); +#endif +#if REDCONF_API_FSE_TRANSMASKGET == 1 +REDSTATUS RedFseTransMaskGet(uint8_t bVolNum, uint32_t *pulEventMask); +#endif +#if REDCONF_READ_ONLY == 0 +REDSTATUS RedFseTransact(uint8_t bVolNum); +#endif + +#endif /* REDCONF_API_FSE == 1 */ + + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redgetopt.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redgetopt.h new file mode 100644 index 0000000..11c1206 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redgetopt.h @@ -0,0 +1,77 @@ +/*- + * Copyright (c) 2000 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Dieter Baron and Thomas Klausner. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +/** @file + @brief Interfaces for getopt() and getopt_long() work-alike functions. + + This code was taken from FreeBSD and slightly modified, mostly to rename + symbols with external linkage to avoid naming conflicts in systems where + there are real getopt()/getopt_long() implementations. Changed to use + fixed-width types to allow code using these interfaces to be consistent + with the rest of the product. +*/ +#ifndef REDGETOPT_H +#define REDGETOPT_H + + +#define red_no_argument 0 +#define red_required_argument 1 +#define red_optional_argument 2 + + +/** @brief Specifies a long option. +*/ +typedef struct +{ + /* name of long option */ + const char *name; + /* + * one of red_no_argument, red_required_argument, and red_optional_argument: + * whether option takes an argument + */ + int32_t has_arg; + /* if not NULL, set *flag to val when option found */ + int32_t *flag; + /* if flag not NULL, value to set *flag to; else return value */ + int32_t val; +} REDOPTION; + + +int32_t RedGetopt(int32_t nargc, char * const *nargv, const char *options); +int32_t RedGetoptLong(int32_t nargc, char * const *nargv, const char *options, const REDOPTION *long_options, int32_t *idx); + + +extern const char *red_optarg; +extern int32_t red_optind; +extern int32_t red_opterr; +extern int32_t red_optopt; +extern int32_t red_optreset; + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redmacs.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redmacs.h new file mode 100644 index 0000000..0fe8a57 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redmacs.h @@ -0,0 +1,103 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file +*/ +#ifndef REDMACS_H +#define REDMACS_H + + +#ifndef NULL +#define NULL ((void *)0) +#endif + +#ifndef UINT8_MAX +#define UINT8_MAX (0xFFU) +#endif +#ifndef UINT16_MAX +#define UINT16_MAX (0xFFFFU) +#endif +#ifndef UINT32_MAX +#define UINT32_MAX (0xFFFFFFFFU) +#endif +#ifndef UINT64_MAX +#define UINT64_MAX UINT64_SUFFIX(0xFFFFFFFFFFFFFFFF) +#endif +#ifndef INT32_MAX +#define INT32_MAX (0x7FFFFFFF) +#endif +#ifndef INT64_MAX +#define INT64_MAX INT64_SUFFIX(0x7FFFFFFFFFFFFFFF) +#endif + +#ifndef true +#define true (1) +#endif +#ifndef false +#define false (0) +#endif + +#define SECTOR_SIZE_MIN (256U) + +#if REDCONF_BLOCK_SIZE == 256U +#define BLOCK_SIZE_P2 8U +#elif REDCONF_BLOCK_SIZE == 512U +#define BLOCK_SIZE_P2 9U +#elif REDCONF_BLOCK_SIZE == 1024U +#define BLOCK_SIZE_P2 10U +#elif REDCONF_BLOCK_SIZE == 2048U +#define BLOCK_SIZE_P2 11U +#elif REDCONF_BLOCK_SIZE == 4096U +#define BLOCK_SIZE_P2 12U +#elif REDCONF_BLOCK_SIZE == 8192U +#define BLOCK_SIZE_P2 13U +#elif REDCONF_BLOCK_SIZE == 16384U +#define BLOCK_SIZE_P2 14U +#elif REDCONF_BLOCK_SIZE == 32768U +#define BLOCK_SIZE_P2 15U +#elif REDCONF_BLOCK_SIZE == 65536U +#define BLOCK_SIZE_P2 16U +#else +#error "REDCONF_BLOCK_SIZE must be a power of two value between 256 and 65536" +#endif + +#define REDMIN(a, b) (((a) < (b)) ? (a) : (b)) + +#define INODE_INVALID (0U) /* General-purpose invalid inode number (must be zero). */ +#define INODE_FIRST_VALID (2U) /* First valid inode number. */ +#define INODE_ROOTDIR (INODE_FIRST_VALID) /* Inode number of the root directory. */ + +/* Expands to a "const" qualifier when the volume count is one, otherwise + expands to nothing. This is useful for variables that never change in + single-volume configurations but do change in multi-volume configurations. +*/ +#if REDCONF_VOLUME_COUNT == 1U + #define CONST_IF_ONE_VOLUME const +#else + #define CONST_IF_ONE_VOLUME +#endif + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redmisc.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redmisc.h new file mode 100644 index 0000000..8ad8105 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redmisc.h @@ -0,0 +1,48 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file +*/ +#ifndef REDMISC_H +#define REDMISC_H + + +/** @brief Type of an inode or handle. + + Used to indicate the actual or expected type of an inode or handle. +*/ +typedef enum +{ + FTYPE_FILE, /**< Type is file. */ + FTYPE_DIR, /**< Type is directory. */ + + /** Type is either file or directory: used only to indicate an expected + type, never as an actual type. + */ + FTYPE_EITHER +} FTYPE; + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redosserv.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redosserv.h new file mode 100644 index 0000000..66c11c6 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redosserv.h @@ -0,0 +1,86 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file +*/ +#ifndef REDOSSERV_H +#define REDOSSERV_H + + +#include + + +/** @brief Type of access requested when opening a block device. +*/ +typedef enum +{ + BDEV_O_RDONLY, /**< Open block device for read access. */ + BDEV_O_WRONLY, /**< Open block device for write access. */ + BDEV_O_RDWR /**< Open block device for read and write access. */ +} BDEVOPENMODE; + +REDSTATUS RedOsBDevOpen(uint8_t bVolNum, BDEVOPENMODE mode); +REDSTATUS RedOsBDevClose(uint8_t bVolNum); +REDSTATUS RedOsBDevRead(uint8_t bVolNum, uint64_t ullSectorStart, uint32_t ulSectorCount, void *pBuffer); + +#if REDCONF_READ_ONLY == 0 +REDSTATUS RedOsBDevWrite(uint8_t bVolNum, uint64_t ullSectorStart, uint32_t ulSectorCount, const void *pBuffer); +REDSTATUS RedOsBDevFlush(uint8_t bVolNum); +#endif + +/* Non-standard API: for host machines only. +*/ +REDSTATUS RedOsBDevConfig(uint8_t bVolNum, const char *pszBDevSpec); + + +#if REDCONF_TASK_COUNT > 1U +REDSTATUS RedOsMutexInit(void); +REDSTATUS RedOsMutexUninit(void); +void RedOsMutexAcquire(void); +void RedOsMutexRelease(void); +#endif +#if (REDCONF_TASK_COUNT > 1U) && (REDCONF_API_POSIX == 1) +uint32_t RedOsTaskId(void); +#endif + +REDSTATUS RedOsClockInit(void); +REDSTATUS RedOsClockUninit(void); +uint32_t RedOsClockGetTime(void); + +REDSTATUS RedOsTimestampInit(void); +REDSTATUS RedOsTimestampUninit(void); +REDTIMESTAMP RedOsTimestamp(void); +uint64_t RedOsTimePassed(REDTIMESTAMP tsSince); + +#if REDCONF_OUTPUT == 1 +void RedOsOutputString(const char *pszString); +#endif + +#if REDCONF_ASSERTS == 1 +void RedOsAssertFail(const char *pszFileName, uint32_t ulLineNum); +#endif + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redpath.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redpath.h new file mode 100644 index 0000000..06f7c36 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redpath.h @@ -0,0 +1,38 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Interfaces of path utilities for the POSIX-like API layer. +*/ +#ifndef REDPATH_H +#define REDPATH_H + + +REDSTATUS RedPathSplit(const char *pszPath, uint8_t *pbVolNum, const char **ppszLocalPath); +REDSTATUS RedPathLookup(const char *pszLocalPath, uint32_t *pulInode); +REDSTATUS RedPathToName(const char *pszLocalPath, uint32_t *pulPInode, const char **ppszName); + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redposix.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redposix.h new file mode 100644 index 0000000..bedb008 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redposix.h @@ -0,0 +1,196 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Interface for the Reliance Edge POSIX-like API. + + The POSIX-like file system API is the primary file system API for + Reliance Edge, which supports the full functionality of the file system. + This API aims to be compatible with POSIX where reasonable, but it is + simplified considerably to meet the needs of resource-constrained embedded + systems. The API has also been extended to provide access to the unique + features of Reliance Edge, and to cover areas (like mountins and formatting) + which do not have APIs in the POSIX specification. +*/ +#ifndef REDPOSIX_H +#define REDPOSIX_H + +/* This header is intended for application use; some applications are written + in C++. +*/ +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#if REDCONF_API_POSIX == 1 + +#include +#include "redapimacs.h" +#include "rederrno.h" +#include "redstat.h" + +/** Open for reading only. */ +#define RED_O_RDONLY 0x00000001U + +/** Open for writing only. */ +#define RED_O_WRONLY 0x00000002U + +/** Open for reading and writing. */ +#define RED_O_RDWR 0x00000004U + +/** File offset for all writes is end-of-file. */ +#define RED_O_APPEND 0x00000008U + +/** Create the file. */ +#define RED_O_CREAT 0x00000010U + +/** Error if path already exists. */ +#define RED_O_EXCL 0x00000020U + +/** Truncate file to size zero. */ +#define RED_O_TRUNC 0x00000040U + + +/** @brief Last file system error (errno). + + Under normal circumstances, each task using the file system has an + independent `red_errno` value. Applications do not need to worry about + one task obliterating an error value that another task needed to read. The + value is initially zero. When one of the POSIX-like APIs return an + indication of error, `red_errno` is set to an error value. + + In some circumstances, `red_errno` will be a global errno location which + is shared by multiple tasks. If the calling task is not registered as a + file system user and all of the task slots are full, there can be no + task-specific errno, so the global errno is used. Likewise, if the file + system driver is uninitialized, there are no registered file system users + and `red_errno` always refers to the global errno. Under these + circumstances, multiple tasks manipulating `red_errno` could be + problematic. When the task count is set to one, `red_errno` always refers + to the global errno. + + Note that `red_errno` is usable as an lvalue; i.e., in addition to reading + the error value, the error value can be set: + + ~~~{.c} + red_errno = 0; + ~~~ +*/ +#define red_errno (*red_errnoptr()) + + +/** @brief Positions from which to seek within a file. +*/ +typedef enum +{ + /* 0/1/2 are the traditional values for SET/CUR/END, respectively. Prior + to the release of Unix System V in 1983, the SEEK_* symbols did not + exist and C programs hard-coded the 0/1/2 values with those meanings. + */ + RED_SEEK_SET = 0, /**< Set file offset to given offset. */ + RED_SEEK_CUR = 1, /**< Set file offset to current offset plus signed offset. */ + RED_SEEK_END = 2 /**< Set file offset to EOF plus signed offset. */ +} REDWHENCE; + + +#if REDCONF_API_POSIX_READDIR == 1 +/** @brief Opaque directory handle. +*/ +typedef struct sREDHANDLE REDDIR; + + +/** @brief Directory entry information. +*/ +typedef struct +{ + uint32_t d_ino; /**< File serial number (inode number). */ + char d_name[REDCONF_NAME_MAX+1U]; /**< Name of entry. */ + REDSTAT d_stat; /**< File information (POSIX extension). */ +} REDDIRENT; +#endif + + +int32_t red_init(void); +int32_t red_uninit(void); +int32_t red_mount(const char *pszVolume); +int32_t red_umount(const char *pszVolume); +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX_FORMAT == 1) +int32_t red_format(const char *pszVolume); +#endif +#if REDCONF_READ_ONLY == 0 +int32_t red_transact(const char *pszVolume); +#endif +#if REDCONF_READ_ONLY == 0 +int32_t red_settransmask(const char *pszVolume, uint32_t ulEventMask); +#endif +int32_t red_gettransmask(const char *pszVolume, uint32_t *pulEventMask); +int32_t red_statvfs(const char *pszVolume, REDSTATFS *pStatvfs); +int32_t red_open(const char *pszPath, uint32_t ulOpenMode); +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX_UNLINK == 1) +int32_t red_unlink(const char *pszPath); +#endif +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX_MKDIR == 1) +int32_t red_mkdir(const char *pszPath); +#endif +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX_RMDIR == 1) +int32_t red_rmdir(const char *pszPath); +#endif +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX_RENAME == 1) +int32_t red_rename(const char *pszOldPath, const char *pszNewPath); +#endif +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX_LINK == 1) +int32_t red_link(const char *pszPath, const char *pszHardLink); +#endif +int32_t red_close(int32_t iFildes); +int32_t red_read(int32_t iFildes, void *pBuffer, uint32_t ulLength); +#if REDCONF_READ_ONLY == 0 +int32_t red_write(int32_t iFildes, const void *pBuffer, uint32_t ulLength); +#endif +#if REDCONF_READ_ONLY == 0 +int32_t red_fsync(int32_t iFildes); +#endif +int64_t red_lseek(int32_t iFildes, int64_t llOffset, REDWHENCE whence); +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX_FTRUNCATE == 1) +int32_t red_ftruncate(int32_t iFildes, uint64_t ullSize); +#endif +int32_t red_fstat(int32_t iFildes, REDSTAT *pStat); +#if REDCONF_API_POSIX_READDIR == 1 +REDDIR *red_opendir(const char *pszPath); +REDDIRENT *red_readdir(REDDIR *pDirStream); +void red_rewinddir(REDDIR *pDirStream); +int32_t red_closedir(REDDIR *pDirStream); +#endif +REDSTATUS *red_errnoptr(void); + +#endif /* REDCONF_API_POSIX */ + + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redstat.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redstat.h new file mode 100644 index 0000000..bf38011 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redstat.h @@ -0,0 +1,94 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file +*/ +#ifndef REDSTAT_H +#define REDSTAT_H + + +/** Mode bit for a directory. */ +#define RED_S_IFDIR 0x4000U + +/** Mode bit for a regular file. */ +#define RED_S_IFREG 0x8000U + +/** @brief Test for a directory. +*/ +#define RED_S_ISDIR(m) (((m) & RED_S_IFDIR) != 0U) + +/** @brief Test for a regular file. +*/ +#define RED_S_ISREG(m) (((m) & RED_S_IFREG) != 0U) + + +/** File system is read-only. */ +#define RED_ST_RDONLY 0x00000001U + +/** File system ignores suid and sgid bits. */ +#define RED_ST_NOSUID 0x00000002U + + +/** @brief Status information on an inode. +*/ +typedef struct +{ + uint8_t st_dev; /**< Volume number of volume containing file. */ + uint32_t st_ino; /**< File serial number (inode number). */ + uint16_t st_mode; /**< Mode of file. */ + uint16_t st_nlink; /**< Number of hard links to the file. */ + uint64_t st_size; /**< File size in bytes. */ + #if REDCONF_INODE_TIMESTAMPS == 1 + uint32_t st_atime; /**< Time of last access (seconds since 01-01-1970). */ + uint32_t st_mtime; /**< Time of last data modification (seconds since 01-01-1970). */ + uint32_t st_ctime; /**< Time of last status change (seconds since 01-01-1970). */ + #endif + #if REDCONF_INODE_BLOCKS == 1 + uint32_t st_blocks; /**< Number of blocks allocated for this object. */ + #endif +} REDSTAT; + + +/** @brief Status information on a file system volume. +*/ +typedef struct +{ + uint32_t f_bsize; /**< File system block size. */ + uint32_t f_frsize; /**< Fundamental file system block size. */ + uint32_t f_blocks; /**< Total number of blocks on file system in units of f_frsize. */ + uint32_t f_bfree; /**< Total number of free blocks. */ + uint32_t f_bavail; /**< Number of free blocks available to non-privileged process. */ + uint32_t f_files; /**< Total number of file serial numbers. */ + uint32_t f_ffree; /**< Total number of free file serial numbers. */ + uint32_t f_favail; /**< Number of file serial numbers available to non-privileged process. */ + uint32_t f_fsid; /**< File system ID (useless, populated with zero). */ + uint32_t f_flag; /**< Bit mask of f_flag values. Includes read-only file system flag. */ + uint32_t f_namemax; /**< Maximum filename length. */ + uint64_t f_maxfsize; /**< Maximum file size (POSIX extension). */ + uint32_t f_dev; /**< Volume number (POSIX extension). */ +} REDSTATFS; + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redtests.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redtests.h new file mode 100644 index 0000000..6cd7769 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redtests.h @@ -0,0 +1,265 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Prototypes for Reliance Edge test entry points. +*/ +#ifndef REDTESTS_H +#define REDTESTS_H + +#include +#include "redtestutils.h" +#include "redver.h" + +/* This macro is only defined by the error injection project. +*/ +#ifdef REDCONF_ERROR_INJECTION +#include +#endif + +#define FSSTRESS_SUPPORTED \ + ( ((RED_KIT == RED_KIT_GPL) || (RED_KIT == RED_KIT_SANDBOX)) \ + && (REDCONF_OUTPUT == 1) && (REDCONF_READ_ONLY == 0) && (REDCONF_PATH_SEPARATOR == '/') \ + && (REDCONF_API_POSIX == 1) && (REDCONF_API_POSIX_UNLINK == 1) && (REDCONF_API_POSIX_MKDIR == 1) \ + && (REDCONF_API_POSIX_RMDIR == 1) && (REDCONF_API_POSIX_RENAME == 1) && (REDCONF_API_POSIX_LINK == 1) \ + && (REDCONF_API_POSIX_FTRUNCATE == 1) && (REDCONF_API_POSIX_READDIR == 1)) + +#define FSE_STRESS_TEST_SUPPORTED \ + ( ((RED_KIT == RED_KIT_COMMERCIAL) || (RED_KIT == RED_KIT_SANDBOX)) \ + && (REDCONF_OUTPUT == 1) && (REDCONF_READ_ONLY == 0) && (REDCONF_API_FSE == 1) \ + && (REDCONF_API_FSE_FORMAT == 1) && (REDCONF_API_FSE_TRANSMASKSET == 1) && (REDCONF_API_FSE_TRANSMASKGET == 1) \ + && (REDCONF_API_FSE_TRUNCATE == 1)) + +#define POSIX_API_TEST_SUPPORTED \ + ( ((RED_KIT == RED_KIT_COMMERCIAL) || (RED_KIT == RED_KIT_SANDBOX)) \ + && (REDCONF_OUTPUT == 1) && (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) \ + && (REDCONF_API_POSIX_FORMAT == 1) && (REDCONF_API_POSIX_UNLINK == 1)) + +#define FSE_API_TEST_SUPPORTED \ + ( ((RED_KIT == RED_KIT_COMMERCIAL) || (RED_KIT == RED_KIT_SANDBOX)) \ + && (REDCONF_OUTPUT == 1) && (REDCONF_READ_ONLY == 0) && (REDCONF_API_FSE == 1) \ + && (REDCONF_API_FSE_FORMAT == 1)) + +#define STOCH_POSIX_TEST_SUPPORTED \ + ( ((RED_KIT == RED_KIT_COMMERCIAL) || (RED_KIT == RED_KIT_SANDBOX)) \ + && (REDCONF_OUTPUT == 1) && (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) \ + && (REDCONF_API_POSIX_FORMAT == 1) && (REDCONF_API_POSIX_READDIR == 1) \ + && (REDCONF_API_POSIX_MKDIR == 1) && (REDCONF_API_POSIX_RMDIR == 1) && (REDCONF_API_POSIX_UNLINK == 1) \ + && (REDCONF_API_POSIX_RENAME == 1)) + +#define FSIOTEST_SUPPORTED \ + ( ((RED_KIT == RED_KIT_COMMERCIAL) || (RED_KIT == RED_KIT_SANDBOX)) \ + && (REDCONF_OUTPUT == 1) && (REDCONF_API_POSIX == 1)) + +#define BDEVTEST_SUPPORTED \ + ( ((RED_KIT == RED_KIT_COMMERCIAL) || (RED_KIT == RED_KIT_SANDBOX)) \ + && (REDCONF_OUTPUT == 1) && (REDCONF_READ_ONLY == 0)) + +#define DISKFULL_TEST_SUPPORTED \ + ( ((RED_KIT == RED_KIT_COMMERCIAL) || (RED_KIT == RED_KIT_SANDBOX)) \ + && (REDCONF_OUTPUT == 1) && (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX == 1) \ + && (REDCONF_API_POSIX_FORMAT == 1) && (REDCONF_API_POSIX_FTRUNCATE == 1)) + + +typedef enum +{ + PARAMSTATUS_OK, /* Parameters were good; continue. */ + PARAMSTATUS_BAD, /* Parameters were bad; stop. */ + PARAMSTATUS_HELP /* Help request; not an error, but stop. */ +} PARAMSTATUS; + + +#if FSSTRESS_SUPPORTED +typedef struct +{ + bool fNoCleanup; /**< --no-cleanup */ + uint32_t ulLoops; /**< --loops */ + uint32_t ulNops; /**< --nops */ + bool fNamePad; /**< --namepad */ + uint32_t ulSeed; /**< --seed */ + bool fVerbose; /**< --verbose */ +} FSSTRESSPARAM; + +PARAMSTATUS FsstressParseParams(int argc, char *argv[], FSSTRESSPARAM *pParam, uint8_t *pbVolNum, const char **ppszDevice); +void FsstressDefaultParams(FSSTRESSPARAM *pParam); +int FsstressStart(const FSSTRESSPARAM *pParam); +#endif + +#if STOCH_POSIX_TEST_SUPPORTED +typedef struct +{ + const char *pszVolume; /**< Volume path prefix. */ + uint32_t ulIterations; /**< --iterations */ + uint32_t ulFileListMax; /**< --files */ + uint32_t ulDirListMax; /**< --dirs */ + uint32_t ulOpenFileListMax; /**< --open-files */ + uint32_t ulOpenDirListMax; /**< --open-dirs */ + uint32_t ulRandomSeed; /**< --seed */ +} STOCHPOSIXPARAM; + +PARAMSTATUS RedStochPosixParseParams(int argc, char *argv[], STOCHPOSIXPARAM *pParam, uint8_t *pbVolNum, const char **ppszDevice); +void RedStochPosixDefaultParams(STOCHPOSIXPARAM *pParam); +int RedStochPosixStart(const STOCHPOSIXPARAM *pParam); +#endif + +#if FSE_STRESS_TEST_SUPPORTED +typedef struct +{ + uint8_t bVolNum; /**< Volume number. */ + uint32_t ulFileCount; /**< --files */ + uint32_t ulMaxFileSize; /**< --max */ + uint32_t ulMaxOpSize; /**< --buffer-size */ + uint32_t ulNops; /**< --nops */ + uint32_t ulLoops; /**< --loops */ + uint32_t ulSampleRate; /**< --sample-rate */ + uint64_t ullSeed; /**< --seed */ +} FSESTRESSPARAM; + +PARAMSTATUS FseStressParseParams(int argc, char *argv[], FSESTRESSPARAM *pParam, uint8_t *pbVolNum, const char **ppszDevice); +void FseStressDefaultParams(FSESTRESSPARAM *pParam); +int FseStressStart(const FSESTRESSPARAM *pParam); +#endif + +#if POSIX_API_TEST_SUPPORTED +typedef struct +{ + const char *pszVolume; /**< Volume path prefix. */ + bool fQuick; /**< --quick */ + bool fQuitOnFailure; /**< --quit-on-failure */ + bool fDebugErrors; /**< --debug */ +} POSIXTESTPARAM; + +PARAMSTATUS RedPosixTestParseParams(int argc, char *argv[], POSIXTESTPARAM *pParam, uint8_t *pbVolNum, const char **ppszDevice); +void RedPosixTestDefaultParams(POSIXTESTPARAM *pParam); +int RedPosixTestStart(const POSIXTESTPARAM *pParam); +#endif + + +#if POSIX_API_TEST_SUPPORTED +typedef struct +{ + const char *pszVolume; /**< Volume path prefix. */ + bool fQuick; /**< --quick */ + bool fVerbose; /**< --verbose */ + bool fQuitOnFailure; /**< --quit-on-failure */ + bool fDebugErrors; /**< --debug */ +} OSAPITESTPARAM; + +PARAMSTATUS RedOsApiTestParseParams(int argc, char *argv[], OSAPITESTPARAM *pParam, const char **ppszDevice); +void RedOsApiTestDefaultParams(OSAPITESTPARAM *pParam); +int RedOsApiTestStart(const OSAPITESTPARAM *pParam); +#endif + + +#if FSE_API_TEST_SUPPORTED +typedef struct +{ + uint8_t bVolNum; /**< Volume number. */ + bool fQuitOnFailure; /**< --quit-on-failure */ + bool fDebugErrors; /**< --debug */ +} FSETESTPARAM; + +PARAMSTATUS RedFseTestParseParams(int argc, char *argv[], FSETESTPARAM *pParam, uint8_t *pbVolNum, const char **ppszDevice); +void RedFseTestDefaultParams(FSETESTPARAM *pParam); +int RedFseTestStart(const FSETESTPARAM *pParam); +#endif + +#if FSIOTEST_SUPPORTED +typedef enum +{ + TESTFS_RELEDGE, /* Datalight Reliance Edge */ + TESTFS_FATFS, /* ChaN's FatFs */ + TESTFS_FATSL /* FreeRTOS+FAT SL */ +} TESTFS; + +typedef struct +{ + TESTFS testfs; /**< --fs */ + const char *pszVolume; /**< Volume path prefix. */ + bool fSeqRead; /**< --seq=r */ + bool fSeqWrite; /**< --seq=w */ + bool fSeqRewrite; /**< --seq=e */ + bool fRandomRead; /**< --rand=r */ + bool fRandomWrite; /**< --rand=w */ + bool fMixedWrite; /**< --mixed */ + bool fScanTest; /**< --scan */ + uint32_t ulFSBlockSize; /**< --block-size */ + uint32_t ulMaxFileSize; /**< --max */ + uint32_t ulRandomReadPasses; /**< --rand-pass=r:w (r part) */ + uint32_t ulRandomWritePasses; /**< --rand-pass=r:w (w part) */ + uint32_t ulMixedWritePasses; /**< --mixed-pass */ + int32_t iFlushOnWriteRatio; /**< --rand-fow */ + uint32_t ulBufferMin; /**< --start */ + uint32_t ulBufferSize; /**< --buffer-size */ + bool fWriteVerify; /**< --verify */ + uint32_t ulSampleRate; /**< --sample-rate */ + uint32_t ulScanCount; /**< --scan-files */ + uint64_t ullSeed; /**< --seed */ +} FSIOTESTPARAM; + +PARAMSTATUS FSIOTestParseParams(int argc, char *argv[], FSIOTESTPARAM *pParam, uint8_t *pbVolNum, const char **ppszDevice); +void FSIOTestDefaultParams(FSIOTESTPARAM *pParam); +int FSIOTestStart(const FSIOTESTPARAM *pParam); +#endif + +#if BDEVTEST_SUPPORTED +typedef struct +{ + uint8_t bDrvNum; /**< Volume number (for sector size/count). */ + bool fSeqWrite; /**< --seq:w */ + bool fSeqRead; /**< --seq:r */ + bool fRandWrite; /**< --rand:w */ + bool fRandRead; /**< --rand:r */ + uint32_t ulSampleSecs; /**< --sample-rate */ + uint32_t ulPasses; /**< --passes */ + uint32_t ulMinIOSectors; /**< --count=min[:max] (min part) */ + uint32_t ulMaxIOSectors; /**< --count=min[:max] (max part) */ + uint32_t ulMaxSizeKB; /**< --max */ + uint32_t ulTestSeconds; /**< --time */ + bool fVerify; /**< --verify */ + bool fAsyncWrites; /**< --async */ + uint64_t ullSeed; /**< --seed */ +} BDEVTESTPARAM; + +PARAMSTATUS BDevTestParseParams(int argc, char *argv[], BDEVTESTPARAM *pParam, uint8_t *pbVolNum, const char **ppszDevice); +void BDevTestDefaultParams(BDEVTESTPARAM *pParam); +int BDevTestStart(const BDEVTESTPARAM *pParam); +#endif + +#if DISKFULL_TEST_SUPPORTED +typedef struct +{ + const char *pszVolume; /**< Volume path prefix. */ + bool fQuitOnFailure; /**< --quit-on-failure */ + bool fDebugErrors; /**< --debug */ +} DISKFULLTESTPARAM; + +PARAMSTATUS DiskFullTestParseParams(int argc, char *argv[], DISKFULLTESTPARAM *pParam, uint8_t *pbVolNum, const char **ppszDevice); +void DiskFullTestDefaultParams(DISKFULLTESTPARAM *pParam); +int DiskFullTestStart(const DISKFULLTESTPARAM *pParam); +#endif + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redtestutils.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redtestutils.h new file mode 100644 index 0000000..294da5b --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redtestutils.h @@ -0,0 +1,71 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Reliance Edge utilities only needed for tests. +*/ +#ifndef REDTESTUTILS_H +#define REDTESTUTILS_H + + +#define ISDIGIT(c) (((c) >= '0') && ((c) <= '9')) + + +void RedRandSeed(uint64_t ullSeed); +uint64_t RedRand64(uint64_t *pullSeed); +uint32_t RedRand32(uint32_t *pulSeed); + +char *RedRatio(char *pBuffer, uint32_t ulBufferLen, uint64_t ullDividend, uint64_t ullDivisor, uint32_t ulDecPlaces); +uint64_t RedMulDiv64(uint64_t ullBase, uint32_t ulMultiplier, uint64_t ullDivisor); +uint64_t RedUint64DivMod32(uint64_t ullDividend, uint32_t ulDivisor, uint32_t *pulRemainder); +uint64_t RedUint64DivMod64(uint64_t ullDividend, uint64_t ullDivisor, uint64_t *pullRemainder); + +char *RedScaleBytes(uint32_t ulByteValue, char *pszBuffer, uint32_t ulBufferSize); +char *RedScaleKB(uint32_t ulKBValue, char *pszBuffer, uint32_t ulBufferSize); +uint32_t RedGetKBPerSecond(uint64_t ullKB, uint32_t ulMS); +uint32_t RedGetKBPerSecondSectors(uint32_t ulBytesPerSector, uint64_t ullSectors, uint64_t ullUS); + +int32_t RedAtoI(const char *pszNum); +const char *RedHtoUL(const char *pszNum, uint32_t *pulNum); +const char *RedHtoULL(const char *pszNum, uint64_t *pullNum); +const char *RedNtoUL(const char *pszNum, uint32_t *pulNum); +const char *RedNtoULL(const char *pszNum, uint64_t *pullNum); +const char *RedSizeToUL(const char *pszNum, uint32_t *pulResult); + +int32_t RedStrICmp(const char *pszStr1, const char *pszStr2); +int32_t RedStrNICmp(const char *pszStr1, const char *pszStr2, uint32_t ulLen); +char RedToLower(char c); + +#include + +#if REDCONF_OUTPUT == 1 +void RedPrintf(const char *pszFormat, ...); +void RedVPrintf(const char *pszFormat, va_list arglist); +#endif +int32_t RedSNPrintf(char *pcBuffer, uint32_t ulBufferLen, const char *pszFormat, ...); +int32_t RedVSNPrintf(char *pcBuffer, uint32_t ulBufferLen, const char *pszFormat, va_list arglist); + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redtoolcmn.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redtoolcmn.h new file mode 100644 index 0000000..7772552 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redtoolcmn.h @@ -0,0 +1,37 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Interfaces for common-code utilities for tools and tests. +*/ +#ifndef REDTOOLCMN_H +#define REDTOOLCMN_H + + +uint8_t RedFindVolumeNumber(const char *pszVolume); +bool RedConfirmOperation(const char *pszMessage); + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redtools.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redtools.h new file mode 100644 index 0000000..f80ffb1 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redtools.h @@ -0,0 +1,183 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +#ifndef REDTOOLS_H +#define REDTOOLS_H + + +#ifdef _WIN32 + #include + #define HOST_PATH_MAX MAX_PATH +#else + #include + #define HOST_PATH_MAX PATH_MAX +#endif + + +#if REDCONF_IMAGE_BUILDER == 1 + +#define MACRO_NAME_MAX_LEN 32 + +typedef struct +{ + uint8_t bVolNumber; + const char *pszInputDir; + const char *pszOutputFile; + #if REDCONF_API_POSIX == 1 + const char *pszVolName; + #else + const char *pszMapFile; + const char *pszDefineFile; + bool fNowarn; + #endif +} IMGBLDPARAM; + + +void ImgbldParseParams(int argc, char *argv [], IMGBLDPARAM *pParam); +int ImgbldStart(IMGBLDPARAM *pParam); + + +typedef struct +{ + #if REDCONF_API_POSIX == 1 + char asOutFilePath[HOST_PATH_MAX]; + #else + uint32_t ulOutFileIndex; + #endif + char asInFilePath[HOST_PATH_MAX]; +} FILEMAPPING; + + +extern void *gpCopyBuffer; +extern uint32_t gulCopyBufferSize; + + +/* Implemented in ibposix.c +*/ +#if REDCONF_API_POSIX == 1 +REDSTATUS IbPosixCopyDir(const char *pszVolName, const char *pszInDir); +int IbPosixCreateDir(const char *pszVolName, const char *pszFullPath, const char *pszBasePath); +int IbConvertPath(const char *pszVolName, const char *pszFullPath, const char *pszBasePath, char *szOutPath); +#endif + + +/* Implemented in ibfse.c +*/ +#if REDCONF_API_FSE == 1 +typedef struct sFILELISTENTRY FILELISTENTRY; +struct sFILELISTENTRY +{ + FILEMAPPING fileMapping; + FILELISTENTRY *pNext; +}; + + +void FreeFileList(FILELISTENTRY **ppsFileList); + +int IbFseGetFileList(const char *pszPath, const char *pszIndirPath, FILELISTENTRY **ppFileListHead); +int IbFseOutputDefines(FILELISTENTRY *pFileList, const IMGBLDPARAM *pOptions); +int IbFseCopyFiles(int volNum, const FILELISTENTRY *pFileList); +#endif + + +/* Implemented in os-specific space (ibwin.c and iblinux.c) +*/ +#if REDCONF_API_POSIX == 1 +int IbPosixCopyDirRecursive(const char *pszVolName, const char *pszInDir); +#endif +#if REDCONF_API_FSE == 1 +int IbFseBuildFileList(const char *pszDirPath, FILELISTENTRY **ppFileListHead); +#endif +#if REDCONF_API_FSE == 1 +int IbSetRelativePath(char *pszPath, const char *pszParentPath); +#endif +bool IsRegularFile(const char *pszPath); + + +/* Implemented in ibcommon.c +*/ +int IbCopyFile(int volNum, const FILEMAPPING *pFileMapping); +int IbCheckFileExists(const char *pszPath, bool *pfExists); + + +/* Implemented separately in ibfse.c and ibposix.c +*/ +int IbApiInit(void); +int IbApiUninit(void); +int IbWriteFile(int volNum, const FILEMAPPING *pFileMapping, uint64_t ullOffset, void *pData, uint32_t ulDataLen); + +#endif /* IMAGE_BUILDER */ + +/* For image copier tool +*/ + +#ifdef _WIN32 + #define HOST_PSEP '\\' + #if !__STDC__ + #define snprintf _snprintf + #define stat _stat + #define S_IFDIR _S_IFDIR + #define rmdir _rmdir + #endif +#else + #define HOST_PSEP '/' +#endif + +typedef struct +{ + uint8_t bVolNumber; + const char *pszOutputDir; + const char *pszBDevSpec; + #if REDCONF_API_POSIX == 1 + const char *pszVolName; + #endif + bool fNoWarn; +} IMGCOPYPARAM; + +typedef struct +{ + #if REDCONF_API_POSIX == 1 + const char *pszVolume; /* Volume path prefix. */ + uint32_t ulVolPrefixLen; /* strlen(COPIER::pszVolume) */ + #else + uint8_t bVolNum; /* Volume number. */ + #endif + const char *pszOutputDir; /* Output directory path. */ + bool fNoWarn; /* If true, no warning to overwrite. */ + uint8_t *pbCopyBuffer; /* Buffer for copying file data. */ +} COPIER; + + +void ImgcopyParseParams(int argc, char *argv [], IMGCOPYPARAM *pParam); +int ImgcopyStart(IMGCOPYPARAM *pParam); + +/* Implemented separately in imgcopywin.c and imgcopylinux.c. These functions + print an error message and abort on failure. +*/ +void ImgcopyMkdir(const char *pszDir); +void ImgcopyRecursiveRmdir(const char *pszDir); + + +#endif /* REDTOOLS_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redutils.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redutils.h new file mode 100644 index 0000000..f2dd663 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redutils.h @@ -0,0 +1,71 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file +*/ +#ifndef REDUTILS_H +#define REDUTILS_H + + +#if REDCONF_ASSERTS == 1 +#define REDERROR() RedOsAssertFail(__FILE__, __LINE__) +#define REDASSERT(EXP) ((EXP) ? (void)0 : REDERROR()) +#else +#define REDERROR() ((void)0) +#define REDASSERT(EXP) ((void)0) +#endif + + +void RedMemCpy(void *pDest, const void *pSrc, uint32_t ulLen); +void RedMemMove(void *pDest, const void *pSrc, uint32_t ulLen); +void RedMemSet(void *pDest, uint8_t bVal, uint32_t ulLen); +int32_t RedMemCmp(const void *pMem1, const void *pMem2, uint32_t ulLen); + +uint32_t RedStrLen(const char *pszStr); +int32_t RedStrCmp(const char *pszStr1, const char *pszStr2); +int32_t RedStrNCmp(const char *pszStr1, const char *pszStr2, uint32_t ulLen); +void RedStrNCpy(char *pszDst, const char *pszSrc, uint32_t ulLen); + +uint32_t RedCrc32Update(uint32_t ulInitCrc32, const void *pBuffer, uint32_t ulLength); +uint32_t RedCrcNode(const void *pBuffer); + +#if REDCONF_API_POSIX == 1 +uint32_t RedNameLen(const char *pszName); +#endif + +bool RedBitGet(const uint8_t *pbBitmap, uint32_t ulBit); +void RedBitSet(uint8_t *pbBitmap, uint32_t ulBit); +void RedBitClear(uint8_t *pbBitmap, uint32_t ulBit); + +#ifdef REDCONF_ENDIAN_SWAP +uint64_t RedRev64(uint64_t ullToRev); +uint32_t RedRev32(uint32_t ulToRev); +uint16_t RedRev16(uint16_t uToRev); +#endif + +void RedSignOn(void); + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redver.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redver.h new file mode 100644 index 0000000..28793a6 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redver.h @@ -0,0 +1,111 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Macros for version numbers, build number, and product information. +*/ +#ifndef REDVER_H +#define REDVER_H + + +/** @brief Consecutive number assigned to each automated build. + + +*/ +#define RED_BUILD_NUMBER "700" + +#define RED_KIT_GPL 0U /* Open source GPL kit. */ +#define RED_KIT_COMMERCIAL 1U /* Commercially-licensed kit. */ +#define RED_KIT_SANDBOX 2U /* Not a kit: developer sandbox. */ + +/** @brief Indicates the Reliance Edge kit. + + +*/ +#define RED_KIT RED_KIT_GPL + + +/** @brief Version number to display in output. +*/ +#define RED_VERSION "v2.0" + +/** @brief Version number in hex. + + The most significant byte is the major version number, etc. +*/ +#define RED_VERSION_VAL 0x02000000U + +/** @brief On-disk version number. + + This is incremented only when the on-disk layout is updated in such a way + which is incompatible with previously released versions of the file system. +*/ +#define RED_DISK_LAYOUT_VERSION 1U + + +/** @brief Base name of the file system product. +*/ +#define RED_PRODUCT_BASE_NAME "Reliance Edge" + + +/* Specifies whether the product is in alpha stage, beta stage, or neither. +*/ +#if 0 + #if 0 + #define ALPHABETA " (Alpha)" + #else + #define ALPHABETA " (Beta)" + #endif +#else + #define ALPHABETA "" +#endif + +/** @brief Full product name and version. +*/ +#define RED_PRODUCT_NAME "Datalight " RED_PRODUCT_BASE_NAME " " RED_VERSION " Build " RED_BUILD_NUMBER ALPHABETA + + +/** @brief Product copyright. +*/ +#define RED_PRODUCT_LEGAL "Copyright (c) 2014-2017 Datalight, Inc. All Rights Reserved Worldwide." + + +/** @brief Product patents. +*/ +#define RED_PRODUCT_PATENT "Patents: US#7284101." + + +/** @brief Product edition. +*/ +#if RED_KIT == RED_KIT_GPL +#define RED_PRODUCT_EDITION "Open-Source GPLv2 Edition -- Compiled " __DATE__ " at " __TIME__ +#elif RED_KIT == RED_KIT_COMMERCIAL +#define RED_PRODUCT_EDITION "Commercial Edition -- Compiled " __DATE__ " at " __TIME__ +#else +#define RED_PRODUCT_EDITION "Developer Sandbox -- Compiled " __DATE__ " at " __TIME__ +#endif + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redvolume.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redvolume.h new file mode 100644 index 0000000..266cf5e --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/include/redvolume.h @@ -0,0 +1,141 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file +*/ +#ifndef REDVOLUME_H +#define REDVOLUME_H + + +/** @brief Per-volume configuration structure. + + Contains the configuration values that may differ between volumes. Must be + declared in an array in redconf.c in the Reliance Edge project directory and + statically initialized with values representing the volume configuration of + the target system. +*/ +typedef struct +{ + /** The sector size for the block device underlying the volume: the basic + unit for reading and writing to the storage media. Commonly ranges + between 512 and 4096, but any power-of-two value not greater than the + block size will work. + */ + uint32_t ulSectorSize; + + /** The number of sectors in this file system volume. + */ + uint64_t ullSectorCount; + + /** Whether a sector write on the block device underlying the volume is + atomic. It is atomic if when the sector write is interrupted, the + contents of the sector are guaranteed to be either all of the new data, + or all of the old data. If unsure, leave as false. + */ + bool fAtomicSectorWrite; + + /** This is the maximum number of inodes (files and directories). This + number includes the root directory inode (inode 2; created during + format), but does not include inodes 0 or 1, which do not exist on + disk. The number of inodes cannot be less than 1. + */ + uint32_t ulInodeCount; + + /** This is the maximum number of times a block device I/O operation will + be retried. If a block device read, write, or flush fails, Reliance + Edge will try again up to this number of times until the operation is + successful. Set this to 0 to disable retries. + */ + uint8_t bBlockIoRetries; + + #if REDCONF_API_POSIX == 1 + /** The path prefix for the volume; for example, "VOL1:", "FlashDisk", etc. + */ + const char *pszPathPrefix; + #endif +} VOLCONF; + +extern const VOLCONF gaRedVolConf[REDCONF_VOLUME_COUNT]; +extern const VOLCONF * CONST_IF_ONE_VOLUME gpRedVolConf; + + +/** @brief Per-volume run-time data. +*/ +typedef struct +{ + /** Whether the volume is currently mounted. + */ + bool fMounted; + + #if REDCONF_READ_ONLY == 0 + /** Whether the volume is read-only. + */ + bool fReadOnly; + + /** The active automatic transaction mask. + */ + uint32_t ulTransMask; + #endif + + /** The power of 2 difference between sector size and block size. + */ + uint8_t bBlockSectorShift; + + /** The number of logical blocks in this file system volume. The unit here + is the global block size. + */ + uint32_t ulBlockCount; + + /** The total number of allocable blocks; Also the maximum count of free + blocks. + */ + uint32_t ulBlocksAllocable; + + /** The maximum number of bytes that an inode is capable of addressing. + */ + uint64_t ullMaxInodeSize; + + /** The current metadata sequence number. This value is included in all + metadata nodes and incremented every time a metadata node is written. + It is assumed to never wrap around. + */ + uint64_t ullSequence; +} VOLUME; + +/* Array of VOLUME structures, populated at during RedCoreInit(). +*/ +extern VOLUME gaRedVolume[REDCONF_VOLUME_COUNT]; + +/* Volume number currently being accessed; populated during + RedCoreVolSetCurrent(). +*/ +extern CONST_IF_ONE_VOLUME uint8_t gbRedVolNum; + +/* Pointer to the volume currently being accessed; populated during + RedCoreVolSetCurrent(). +*/ +extern VOLUME * CONST_IF_ONE_VOLUME gpRedVolume; + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/include/redosdeviations.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/include/redosdeviations.h new file mode 100644 index 0000000..cfde3a7 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/include/redosdeviations.h @@ -0,0 +1,244 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Macros to encapsulate MISRA C:2012 deviations in OS-specific code. +*/ +#ifndef REDOSDEVIATIONS_H +#define REDOSDEVIATIONS_H + + +#if REDCONF_OUTPUT == 1 +/* Needed for PRINT_ASSERT() and OUTPUT_CHARACTER(). +*/ +#include +#endif + + +#if (REDCONF_ASSERTS == 1) && (REDCONF_OUTPUT == 1) +/** Print a formatted message for an assertion. + + Usages of this macro deviate from MISRA C:2012 Rule 21.6 (required). Using + printf() is the most convenient way to output this information; and the risk + of "unspecified, undefined and implementation-defined" behavior causing + problems (as cited in the rationale for the rule) is small. The driver does + not depend on this string being outputted correctly. Furthermore, use of + printf() disappears when either asserts or output are disabled. + + As Rule 21.6 is required, a separate deviation record is required. +*/ +#define PRINT_ASSERT(file, line) \ + printf("Assertion failed in \"%s\" at line %u\n\r", ((file) == NULL) ? "" : (file), (unsigned)(line)) +#endif + + +/** Cast a value to unsigned long. + + Usages of this macro deviate from MISRA C:2012 Directive 4.6. This macro is + used in two places to cast a uint64_t value (used by the block device + abstraction for sector numbers) to unsigned long, since third-party code + which is not under the control of this project uses unsigned long for sector + numbers. The cast is guaranteed to not lose any information, since when the + disk is opened the sector count is verified to be less than or equal to an + unsigned long value. The text of the directive mentions that "it might be + desirable not to apply this guideline when interfacing with ... code outside + the project's control", which describes the situation for this deviation. + + As Directive 4.6 is advisory, a deviation record is not required. This + notice is the only record of the deviation. +*/ +#define CAST_ULONG(ull) ((unsigned long)(ull)) + + +/** Cast a const-qualified pointer to a pointer which is *not* const-qualified. + + Usages of this macro deviate from MISRA C:2012 Rule 11.8. This macro is + used in exactly one place in order to cope with a poorly designed + third-party interface. Reliance Edge, at every level of the stack, uses + const-qualified pointers for buffers used in write operations, since the + data is read from the buffer, and the buffer does not need to be modified + (consistent with Rule 8.13). One of the third-party block device interfaces + that Reliance Edge interfaces with does not follow this convention: it uses + an unqualified pointer for the buffer parameter of its sector write + function. This forces the need for the cast to avoid warnings. The + implementation of the sector write function is provided by the user, so it + is to be hoped that the buffer is not actually modified. + + As Rule 11.8 is required, a separate deviation record is required. +*/ +#define CAST_AWAY_CONST(type, ptr) ((type *)(ptr)) + + +/** Allocate zero-initialized (cleared) memory. + + All usages of this macro deviate from MISRA C:2012 Directive 4.12 (required) + and Rule 21.3 (required). In the context of the single place it is actually + used, this macro also deviates from Rule 22.1 (required). + + This macro is used in the FreeRTOS block device code in order to allocate a + RAM disk, when that implementation of the block device is selected. The + primary rationale for all these deviations is that a) the RAM disk cannot be + allocated statically (since the volume information is stored in a + structure), and b) the RAM disk is primarily intended as a temporary testing + tool for users who want to try out Reliance Edge before the real storage + media is available. In most real systems, Reliance Edge is used with + non-volatile storage like SD/MMC or eMMC, not with RAM disks. + + Rule 22.1 states that all resources which are allocated must also be + explicitly freed. The RAM disk is allocated and never freed, deviating from + that rule. This is done because the data in the RAM disk is emulating a + non-volatile storage medium, and thus needs to persist even after the block + device is closed, to allow the file system to be ormatted and then mounted, + or unmounted and remounted in the course of a test. Thus the memory will + remain allocated until the target device is rebooted. This is assumed to be + acceptable for the primary purpose of the RAM disk, which is preliminary + testing. + + As Directive 4.12, Rule 21.3, and Rule 22.1 are all required, separate + deviation records are required. +*/ +#define ALLOCATE_CLEARED_MEMORY(nelem, elsize) calloc(nelem, elsize) + + +#if REDCONF_OUTPUT == 1 +/** Output a character to a serial port or other display device. + + Usages of this macro deviate from MISRA C:2012 Rule 21.6 (required). + FreeRTOS does not include a standard method of printing characters, so + putchar() is the most convenient and portable way to accomplish the task. + The risk of "unspecified, undefined and implementation-defined" behavior + causing problems (as cited in the rationale for the rule) is small. The + driver does not depend on the character being outputted correctly. + Furthermore, use of putchar() disappears when output is disabled. + + As Rule 21.6 is required, a separate deviation record is required. +*/ +#define OUTPUT_CHARACTER(ch) (void)putchar(ch) +#endif + + +#if (REDCONF_TASK_COUNT > 1U) && (REDCONF_API_POSIX == 1) +/** Cast a TaskHandle_t (a pointer type) to uintptr_t. + + Usage of this macro deivate from MISRA-C:2012 Rule 11.4 (advisory). This + macro is used for the FreeRTOS version of RedOsTaskId(). Some RTOSes + natively use an integer for task IDs; others use pointers. RedOsTaskId() + uses integers, FreeRTOS uses pointers; to reconcile this difference, the + pointer must be cast to integer. This is fairly safe, since the resulting + integer is never cast back to a pointer; and although the integer + representation of a pointer is implementation-defined, the representation is + irrelevant provided that unique pointers are converted to unique integers. + + As Rule 11.4 is advisory, a deviation record is not required. This notice + is the only record of the deviation. +*/ +#define CAST_TASK_PTR_TO_UINTPTR(taskptr) ((uintptr_t)(taskptr)) +#endif + + +/** Ignore the return value of a function (cast to void) + + Usages of this macro deviate from MISRA C:2012 Directive 4.7, which states + that error information must be checked immediately after a function returns + potential error information. + + If asserts and output are enabled, then this macro is used to document that + the return value of printf() is ignored. A failure of printf() does not + impact the filesystem core, nor is there anything the filesystem can do to + respond to such an error (especially since it occurs within an assert). + Thus, the most reasonable action is to ignore the error. + + In the STM32 SDIO block device implementation, errors are also ignored in an + IRQ interrupt handler. This is the most reasonable action to take for two + reasons: (a) it would be dangerous to spend processor time responding to the + error inside the IRQ handler; (b) it has been verified that the same error + is propegated to the DiskRead/Write method, which does return the error to + the core. + + In the Atmel SD/MMC block device implementation, error information from + sd_mmc_read_capacity() is ignored. This is a reasonable action because all + of the possible error conditions were eliminated by a previous check. + sd_mmc_read_capacity() fails under the same conditions as + sd_mmc_test_unit_ready(), which was checked ealier in the same function. + + In the mutex module, error information returned from the mutex release + function is ignored when asserts are disabled. This is a reasonable action + because the mutex release function (xSemaphoreGive) is documented only to + fail if the mutex was not obtained correctly, which can be demonstrably + avoided. + + As Directive 4.7 is required, a separate deviation record is required. +*/ +#define IGNORE_ERRORS(fn) ((void) (fn)) + + +/** @brief Determine whether a pointer is aligned on a 32-bit boundary. + + This is used to determine whether a data buffer meets the requirements of + the underlying block device implementation. When transferring data via + DMA (Direct Memory Access) on an STM32 device, the data buffer must be cast + as a uint32 pointer, and unexpected behavior may occur if the buffer is not + aligned correctly. + + There is no way to perform this check without deviating from MISRA C rules + against casting pointers to integer types. Usage of this macro deviates + from MISRA C:2012 Rule 11.4 (advisory). The main rationale the rule cites + against converting pointers to integers is that the chosen integer type may + not be able to represent the pointer; this is a non-issue here since we use + uintptr_t. The text says the rule still applies when using uintptr_t due to + concern about unaligned pointers, but that is not an issue here since the + integer value of the pointer is not saved and not converted back into a + pointer and dereferenced. The result of casting a pointer to a sufficiently + large integer is implementation-defined, but macros similar to this one have + been used by Datalight for a long time in a wide variety of environments and + they have always worked as expected. + + This deviation only occurs when using the STM32 SDIO block device + implementation. + + As Rule 11.4 is advisory, a deviation record is not required. This notice + is the only record of deviation. +*/ +#define IS_UINT32_ALIGNED_PTR(ptr) (((uintptr_t)(ptr) & (sizeof(uint32_t) - 1U)) == 0U) + + +/** @brief Cast a 32-bit aligned void pointer to a uint32 pointer. + + Usages of this macro deviate from MISRA C:2012 Rule 11.5 (advisory). A + cast from a void pointer to an object pointer is discouraged because of + potential alignment issues. However, this macro is only used to cast + pointers that have already been tested to be 32-bit aligned, so the + operation will be safe. + + This deviation only occurs when using the STM32 SDIO block device + implementation. + + As rule 11.5 is advisory, a deviation record is not required. This notice + is the only record of the deviation. +*/ +#define CAST_UINT32_PTR(ptr) ((uint32_t *) (ptr)) + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/include/redostypes.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/include/redostypes.h new file mode 100644 index 0000000..cf0494a --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/include/redostypes.h @@ -0,0 +1,42 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Defines OS-specific types for use in common code. +*/ +#ifndef REDOSTYPES_H +#define REDOSTYPES_H + + +/** @brief Implementation-defined timestamp type. + + This can be an integer, a structure, or a pointer: anything that is + convenient for the implementation. Since the underlying type is not fixed, + common code should treat this as an opaque type. +*/ +typedef uint32_t REDTIMESTAMP; + + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/services/osassert.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/services/osassert.c new file mode 100644 index 0000000..9822caf --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/services/osassert.c @@ -0,0 +1,56 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements assertion handling. +*/ +#include + +#if REDCONF_ASSERTS == 1 + +#include + + +/** @brief Invoke the native assertion handler. + + @param pszFileName Null-terminated string containing the name of the file + where the assertion fired. + @param ulLineNum Line number in @p pszFileName where the assertion + fired. +*/ +void RedOsAssertFail( + const char *pszFileName, + uint32_t ulLineNum) +{ + #if REDCONF_OUTPUT == 1 + IGNORE_ERRORS(PRINT_ASSERT(pszFileName, ulLineNum)); + #endif + + while(true) + { + } +} + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/services/osbdev.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/services/osbdev.c new file mode 100644 index 0000000..bb42087 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/services/osbdev.c @@ -0,0 +1,1553 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements block device I/O. +*/ +#include + +#include +#include +#include + + +/*------------------------------------------------------------------------------ + Porting Note: + + Several example implementations of this module for FreeRTOS are available. + If you are lucky, you can use one of these implementations; otherwise, these + can serve as examples of how to implement this service. +------------------------------------------------------------------------------*/ + +/** @brief The F_DRIVER example implementation. + + This implementation is designed to reuse an existing block device driver + that was written for FreeRTOS+FAT SL. If you have such a driver, with + little work it can be "dropped in" and used for Reliance Edge. The only + customization required is that gpfnRedOsBDevInit needs to be defined and + pointed at the F_DRIVERINIT function. This can be done in this module or in + another C file. + + The disadantage of using the FreeRTOS F_DRIVER functions is that they only + support single-sector reads and writes. Reliance Edge will issue + multi-sector requests, and servicing these one sector at a time will + significantly slow down the file system. +*/ +#define BDEV_F_DRIVER (0U) + +/** @brief The FatFs example implementation. + + This implementation is designed to reuse an existing block device driver + that was written for FatFs. If you have such a driver, it can be linked + in and used immediately. The FatFs `diskio.h` header must be in the include + directory path. +*/ +#define BDEV_FATFS (1U) + +/** @brief The Atmel Studio Framework SD/MMC driver example implementation. + + This implementation uses a modified version of the open source SD/MMC driver + included in the Atmel Studio Framework (ASF) and will work as-is for many + varieties of Atmel hardware. This example assumes relatively minor + modifications to the ASF SD/MMC driver to make it support multi-sector read + and write requests, which greatly improves performance. The modified driver + is distributed with Reliance Edge and is included in FreeRTOS Atmel projects + (such as in projects/freertos/atmel/sam4e-ek/src/ASF). + + This example can easily be modified to work with an unmodified version of + the ASF SD/MMC driver. Simply replace sd_mmc_mem_2_ram_multi() and + sd_mmc_ram_2_mem_multi() with sd_mmc_mem_2_ram() and sd_mmc_ram_2_mem() + respectively, and add a for loop to loop over each sector in the request. + However, as described in the manual, there are considerable performance + advantages to issuing real multi-sector requests, so using the modified + driver is recommended. +*/ +#define BDEV_ATMEL_SDMMC (2U) + +/** @brief The ST Microelectronics STM32 SDIO driver example implementation. + + This implementation accesses the microSD card through the BSP utilities + provided as part of the STM32Cube package, used with the STM32 HAL drivers. + The STM3240G-EVAL and STM32F746NG-Discovery boards are currently supported. +*/ +#define BDEV_STM32_SDIO (3U) + +/** @brief The RAM disk example implementation. + + This implementation uses a RAM disk. It will allow you to compile and test + Reliance Edge even if your storage driver is not yet ready. On typical + target hardware, the amount of spare RAM will be limited so generally only + very small disks will be available. +*/ +#define BDEV_RAM_DISK (4U) + +/** @brief Pick which example implementation is compiled. + + Must be one of: + - #BDEV_F_DRIVER + - #BDEV_FATFS + - #BDEV_ATMEL_SDMMC + - #BDEV_STM32_SDIO + - #BDEV_RAM_DISK +*/ +#define BDEV_EXAMPLE_IMPLEMENTATION BDEV_RAM_DISK + + +static REDSTATUS DiskOpen(uint8_t bVolNum, BDEVOPENMODE mode); +static REDSTATUS DiskClose(uint8_t bVolNum); +static REDSTATUS DiskRead(uint8_t bVolNum, uint64_t ullSectorStart, uint32_t ulSectorCount, void *pBuffer); +#if REDCONF_READ_ONLY == 0 +static REDSTATUS DiskWrite(uint8_t bVolNum, uint64_t ullSectorStart, uint32_t ulSectorCount, const void *pBuffer); +static REDSTATUS DiskFlush(uint8_t bVolNum); +#endif + + +/** @brief Initialize a block device. + + This function is called when the file system needs access to a block + device. + + Upon successful return, the block device should be fully initialized and + ready to service read/write/flush/close requests. + + The behavior of calling this function on a block device which is already + open is undefined. + + @param bVolNum The volume number of the volume whose block device is being + initialized. + @param mode The open mode, indicating the type of access required. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p bVolNum is an invalid volume number. + @retval -RED_EIO A disk I/O error occurred. +*/ +REDSTATUS RedOsBDevOpen( + uint8_t bVolNum, + BDEVOPENMODE mode) +{ + REDSTATUS ret; + + if(bVolNum >= REDCONF_VOLUME_COUNT) + { + ret = -RED_EINVAL; + } + else + { + ret = DiskOpen(bVolNum, mode); + } + + return ret; +} + + +/** @brief Uninitialize a block device. + + This function is called when the file system no longer needs access to a + block device. If any resource were allocated by RedOsBDevOpen() to service + block device requests, they should be freed at this time. + + Upon successful return, the block device must be in such a state that it + can be opened again. + + The behavior of calling this function on a block device which is already + closed is undefined. + + @param bVolNum The volume number of the volume whose block device is being + uninitialized. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p bVolNum is an invalid volume number. +*/ +REDSTATUS RedOsBDevClose( + uint8_t bVolNum) +{ + REDSTATUS ret; + + if(bVolNum >= REDCONF_VOLUME_COUNT) + { + ret = -RED_EINVAL; + } + else + { + ret = DiskClose(bVolNum); + } + + return ret; +} + + +/** @brief Read sectors from a physical block device. + + The behavior of calling this function is undefined if the block device is + closed or if it was opened with ::BDEV_O_WRONLY. + + @param bVolNum The volume number of the volume whose block device + is being read from. + @param ullSectorStart The starting sector number. + @param ulSectorCount The number of sectors to read. + @param pBuffer The buffer into which to read the sector data. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p bVolNum is an invalid volume number, @p pBuffer is + `NULL`, or @p ullStartSector and/or @p ulSectorCount + refer to an invalid range of sectors. + @retval -RED_EIO A disk I/O error occurred. +*/ +REDSTATUS RedOsBDevRead( + uint8_t bVolNum, + uint64_t ullSectorStart, + uint32_t ulSectorCount, + void *pBuffer) +{ + REDSTATUS ret = 0; + + if( (bVolNum >= REDCONF_VOLUME_COUNT) + || (ullSectorStart >= gaRedVolConf[bVolNum].ullSectorCount) + || ((gaRedVolConf[bVolNum].ullSectorCount - ullSectorStart) < ulSectorCount) + || (pBuffer == NULL)) + { + ret = -RED_EINVAL; + } + else + { + ret = DiskRead(bVolNum, ullSectorStart, ulSectorCount, pBuffer); + } + + return ret; +} + + +#if REDCONF_READ_ONLY == 0 +/** @brief Write sectors to a physical block device. + + The behavior of calling this function is undefined if the block device is + closed or if it was opened with ::BDEV_O_RDONLY. + + @param bVolNum The volume number of the volume whose block device + is being written to. + @param ullSectorStart The starting sector number. + @param ulSectorCount The number of sectors to write. + @param pBuffer The buffer from which to write the sector data. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p bVolNum is an invalid volume number, @p pBuffer is + `NULL`, or @p ullStartSector and/or @p ulSectorCount + refer to an invalid range of sectors. + @retval -RED_EIO A disk I/O error occurred. +*/ +REDSTATUS RedOsBDevWrite( + uint8_t bVolNum, + uint64_t ullSectorStart, + uint32_t ulSectorCount, + const void *pBuffer) +{ + REDSTATUS ret = 0; + + if( (bVolNum >= REDCONF_VOLUME_COUNT) + || (ullSectorStart >= gaRedVolConf[bVolNum].ullSectorCount) + || ((gaRedVolConf[bVolNum].ullSectorCount - ullSectorStart) < ulSectorCount) + || (pBuffer == NULL)) + { + ret = -RED_EINVAL; + } + else + { + ret = DiskWrite(bVolNum, ullSectorStart, ulSectorCount, pBuffer); + } + + return ret; +} + + +/** @brief Flush any caches beneath the file system. + + This function must synchronously flush all software and hardware caches + beneath the file system, ensuring that all sectors written previously are + committed to permanent storage. + + If the environment has no caching beneath the file system, the + implementation of this function can do nothing and return success. + + The behavior of calling this function is undefined if the block device is + closed or if it was opened with ::BDEV_O_RDONLY. + + @param bVolNum The volume number of the volume whose block device is being + flushed. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p bVolNum is an invalid volume number. + @retval -RED_EIO A disk I/O error occurred. +*/ +REDSTATUS RedOsBDevFlush( + uint8_t bVolNum) +{ + REDSTATUS ret; + + if(bVolNum >= REDCONF_VOLUME_COUNT) + { + ret = -RED_EINVAL; + } + else + { + ret = DiskFlush(bVolNum); + } + + return ret; +} +#endif /* REDCONF_READ_ONLY == 0 */ + + +#if BDEV_EXAMPLE_IMPLEMENTATION == BDEV_F_DRIVER + +#include + + +/* This must be declared and initialized elsewere (e.g., in project code) to + point at the initialization function for the F_DRIVER block device. +*/ +extern const F_DRIVERINIT gpfnRedOsBDevInit; + +static F_DRIVER *gapFDriver[REDCONF_VOLUME_COUNT]; + + +/** @brief Initialize a disk. + + @param bVolNum The volume number of the volume whose block device is being + initialized. + @param mode The open mode, indicating the type of access required. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. +*/ +static REDSTATUS DiskOpen( + uint8_t bVolNum, + BDEVOPENMODE mode) +{ + REDSTATUS ret; + + (void)mode; + + if((gpfnRedOsBDevInit == NULL) || (gapFDriver[bVolNum] != NULL)) + { + ret = -RED_EINVAL; + } + else + { + F_DRIVER *pDriver; + + pDriver = gpfnRedOsBDevInit(bVolNum); + if(pDriver != NULL) + { + F_PHY geom; + int iErr; + + /* Validate that the geometry is consistent with the volume + configuration. + */ + iErr = pDriver->getphy(pDriver, &geom); + if(iErr == 0) + { + if( (geom.bytes_per_sector != gaRedVolConf[bVolNum].ulSectorSize) + || (geom.number_of_sectors < gaRedVolConf[bVolNum].ullSectorCount)) + { + ret = -RED_EINVAL; + } + else + { + gapFDriver[bVolNum] = pDriver; + ret = 0; + } + } + else + { + ret = -RED_EIO; + } + + if(ret != 0) + { + pDriver->release(pDriver); + } + } + else + { + ret = -RED_EIO; + } + } + + return ret; +} + + +/** @brief Uninitialize a disk. + + @param bVolNum The volume number of the volume whose block device is being + uninitialized. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. +*/ +static REDSTATUS DiskClose( + uint8_t bVolNum) +{ + REDSTATUS ret; + + if(gapFDriver[bVolNum] == NULL) + { + ret = -RED_EINVAL; + } + else + { + gapFDriver[bVolNum]->release(gapFDriver[bVolNum]); + gapFDriver[bVolNum] = NULL; + + ret = 0; + } + + return ret; +} + + +/** @brief Read sectors from a disk. + + @param bVolNum The volume number of the volume whose block device + is being read from. + @param ullSectorStart The starting sector number. + @param ulSectorCount The number of sectors to read. + @param pBuffer The buffer into which to read the sector data. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. +*/ +static REDSTATUS DiskRead( + uint8_t bVolNum, + uint64_t ullSectorStart, + uint32_t ulSectorCount, + void *pBuffer) +{ + REDSTATUS ret = 0; + F_DRIVER *pDriver = gapFDriver[bVolNum]; + + if(pDriver == NULL) + { + ret = -RED_EINVAL; + } + else + { + uint8_t *pbBuffer = CAST_VOID_PTR_TO_UINT8_PTR(pBuffer); + uint32_t ulSectorSize = gaRedVolConf[bVolNum].ulSectorSize; + uint32_t ulSectorIdx; + int iErr; + + for(ulSectorIdx = 0U; ulSectorIdx < ulSectorCount; ulSectorIdx++) + { + iErr = pDriver->readsector(pDriver, &pbBuffer[ulSectorIdx * ulSectorSize], + CAST_ULONG(ullSectorStart + ulSectorIdx)); + if(iErr != 0) + { + ret = -RED_EIO; + break; + } + } + } + + return ret; +} + + +#if REDCONF_READ_ONLY == 0 +/** @brief Write sectors to a disk. + + @param bVolNum The volume number of the volume whose block device + is being written to. + @param ullSectorStart The starting sector number. + @param ulSectorCount The number of sectors to write. + @param pBuffer The buffer from which to write the sector data. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL The block device is not open. + @retval -RED_EIO A disk I/O error occurred. +*/ +static REDSTATUS DiskWrite( + uint8_t bVolNum, + uint64_t ullSectorStart, + uint32_t ulSectorCount, + const void *pBuffer) +{ + REDSTATUS ret = 0; + F_DRIVER *pDriver = gapFDriver[bVolNum]; + + if(pDriver == NULL) + { + ret = -RED_EINVAL; + } + else + { + const uint8_t *pbBuffer = CAST_VOID_PTR_TO_CONST_UINT8_PTR(pBuffer); + uint32_t ulSectorSize = gaRedVolConf[bVolNum].ulSectorSize; + uint32_t ulSectorIdx; + int iErr; + + for(ulSectorIdx = 0U; ulSectorIdx < ulSectorCount; ulSectorIdx++) + { + /* We have to cast pbBuffer to non-const since the writesector + prototype is flawed, using a non-const pointer for the buffer. + */ + iErr = pDriver->writesector(pDriver, CAST_AWAY_CONST(uint8_t, &pbBuffer[ulSectorIdx * ulSectorSize]), + CAST_ULONG(ullSectorStart + ulSectorIdx)); + if(iErr != 0) + { + ret = -RED_EIO; + break; + } + } + } + + return ret; +} + + +/** @brief Flush any caches beneath the file system. + + @param bVolNum The volume number of the volume whose block device is being + flushed. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. +*/ +static REDSTATUS DiskFlush( + uint8_t bVolNum) +{ + REDSTATUS ret; + + if(gapFDriver[bVolNum] == NULL) + { + ret = -RED_EINVAL; + } + else + { + /* The F_DRIVER interface does not include a flush function, so to be + reliable the F_DRIVER implementation must use synchronous writes. + */ + ret = 0; + } + + return ret; +} +#endif /* REDCONF_READ_ONLY == 0 */ + + +#elif BDEV_EXAMPLE_IMPLEMENTATION == BDEV_FATFS + +#include +#include + +/* disk_read() and disk_write() use an unsigned 8-bit value to specify the + sector count, so no transfer can be larger than 255 sectors. +*/ +#define MAX_SECTOR_TRANSFER UINT8_MAX + + +/** @brief Initialize a disk. + + @param bVolNum The volume number of the volume whose block device is being + initialized. + @param mode The open mode, indicating the type of access required. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. +*/ +static REDSTATUS DiskOpen( + uint8_t bVolNum, + BDEVOPENMODE mode) +{ + DSTATUS status; + uint32_t ulTries; + REDSTATUS ret = 0; + + /* With some implementations of disk_initialize(), such as the one + implemented by Atmel for the ASF, the first time the disk is opened, the + SD card can take a while to get ready, in which time disk_initialize() + returns an error. Try numerous times, waiting half a second after each + failure. Empirically, this has been observed to succeed on the second + try, so trying 10x more than that provides a margin of error. + */ + for(ulTries = 0U; ulTries < 20U; ulTries++) + { + /* Assuming that the volume number is also the correct drive number. + If this is not the case in your environment, a static constant array + can be declared to map volume numbers to the correct driver number. + */ + status = disk_initialize(bVolNum); + if(status == 0) + { + break; + } + + vTaskDelay(500U / portTICK_PERIOD_MS); + } + + if(status != 0) + { + ret = -RED_EIO; + } + + /* Retrieve the sector size and sector count to ensure they are compatible + with our compile-time geometry. + */ + if(ret == 0) + { + WORD wSectorSize; + DWORD dwSectorCount; + DRESULT result; + + result = disk_ioctl(bVolNum, GET_SECTOR_SIZE, &wSectorSize); + if(result == RES_OK) + { + result = disk_ioctl(bVolNum, GET_SECTOR_COUNT, &dwSectorCount); + if(result == RES_OK) + { + if( (wSectorSize != gaRedVolConf[bVolNum].ulSectorSize) + || (dwSectorCount < gaRedVolConf[bVolNum].ullSectorCount)) + { + ret = -RED_EINVAL; + } + } + else + { + ret = -RED_EIO; + } + } + else + { + ret = -RED_EIO; + } + } + + return ret; +} + + +/** @brief Uninitialize a disk. + + @param bVolNum The volume number of the volume whose block device is being + uninitialized. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. +*/ +static REDSTATUS DiskClose( + uint8_t bVolNum) +{ + (void)bVolNum; + return 0; +} + + +/** @brief Read sectors from a disk. + + @param bVolNum The volume number of the volume whose block device + is being read from. + @param ullSectorStart The starting sector number. + @param ulSectorCount The number of sectors to read. + @param pBuffer The buffer into which to read the sector data. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. +*/ +static REDSTATUS DiskRead( + uint8_t bVolNum, + uint64_t ullSectorStart, + uint32_t ulSectorCount, + void *pBuffer) +{ + REDSTATUS ret = 0; + uint32_t ulSectorIdx = 0U; + uint32_t ulSectorSize = gaRedVolConf[bVolNum].ulSectorSize; + uint8_t *pbBuffer = CAST_VOID_PTR_TO_UINT8_PTR(pBuffer); + + while(ulSectorIdx < ulSectorCount) + { + uint32_t ulTransfer = REDMIN(ulSectorCount - ulSectorIdx, MAX_SECTOR_TRANSFER); + DRESULT result; + + result = disk_read(bVolNum, &pbBuffer[ulSectorIdx * ulSectorSize], (DWORD)(ullSectorStart + ulSectorIdx), (BYTE)ulTransfer); + if(result != RES_OK) + { + ret = -RED_EIO; + break; + } + + ulSectorIdx += ulTransfer; + } + + return ret; +} + + +#if REDCONF_READ_ONLY == 0 +/** @brief Write sectors to a disk. + + @param bVolNum The volume number of the volume whose block device + is being written to. + @param ullSectorStart The starting sector number. + @param ulSectorCount The number of sectors to write. + @param pBuffer The buffer from which to write the sector data. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. +*/ +static REDSTATUS DiskWrite( + uint8_t bVolNum, + uint64_t ullSectorStart, + uint32_t ulSectorCount, + const void *pBuffer) +{ + REDSTATUS ret = 0; + uint32_t ulSectorIdx = 0U; + uint32_t ulSectorSize = gaRedVolConf[bVolNum].ulSectorSize; + const uint8_t *pbBuffer = CAST_VOID_PTR_TO_CONST_UINT8_PTR(pBuffer); + + while(ulSectorIdx < ulSectorCount) + { + uint32_t ulTransfer = REDMIN(ulSectorCount - ulSectorIdx, MAX_SECTOR_TRANSFER); + DRESULT result; + + result = disk_write(bVolNum, &pbBuffer[ulSectorIdx * ulSectorSize], (DWORD)(ullSectorStart + ulSectorIdx), (BYTE)ulTransfer); + if(result != RES_OK) + { + ret = -RED_EIO; + break; + } + + ulSectorIdx += ulTransfer; + } + + return ret; +} + + +/** @brief Flush any caches beneath the file system. + + @param bVolNum The volume number of the volume whose block device is being + flushed. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. +*/ +static REDSTATUS DiskFlush( + uint8_t bVolNum) +{ + REDSTATUS ret; + DRESULT result; + + result = disk_ioctl(bVolNum, CTRL_SYNC, NULL); + if(result == RES_OK) + { + ret = 0; + } + else + { + ret = -RED_EIO; + } + + return ret; +} +#endif /* REDCONF_READ_ONLY == 0 */ + + +#elif BDEV_EXAMPLE_IMPLEMENTATION == BDEV_ATMEL_SDMMC + +#include + +#include +#include +#include +#include + +/* sd_mmc_mem_2_ram_multi() and sd_mmc_ram_2_mem_multi() use an unsigned + 16-bit value to specify the sector count, so no transfer can be larger + than UINT16_MAX sectors. +*/ +#define MAX_SECTOR_TRANSFER UINT16_MAX + + +/** @brief Initialize a disk. + + @param bVolNum The volume number of the volume whose block device is being + initialized. + @param mode The open mode, indicating the type of access required. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EROFS The device is read-only media and write access was + requested. +*/ +static REDSTATUS DiskOpen( + uint8_t bVolNum, + BDEVOPENMODE mode) +{ + REDSTATUS ret = 0; + uint32_t ulTries; + Ctrl_status cs; + + /* Note: Assuming the volume number is the same as the SD card slot. The + ASF SD/MMC driver supports two SD slots. This implementation will need + to be modified if multiple volumes share a single SD card. + */ + + /* The first time the disk is opened, the SD card can take a while to get + ready, in which time sd_mmc_test_unit_ready() returns either CTRL_BUSY + or CTRL_NO_PRESENT. Try numerous times, waiting half a second after + each failure. Empirically, this has been observed to succeed on the + second try, so trying 10x more than that provides a margin of error. + */ + for(ulTries = 0U; ulTries < 20U; ulTries++) + { + cs = sd_mmc_test_unit_ready(bVolNum); + if((cs != CTRL_NO_PRESENT) && (cs != CTRL_BUSY)) + { + break; + } + + vTaskDelay(500U / portTICK_PERIOD_MS); + } + + if(cs == CTRL_GOOD) + { + #if REDCONF_READ_ONLY == 0 + if(mode != BDEV_O_RDONLY) + { + if(sd_mmc_wr_protect(bVolNum)) + { + ret = -RED_EROFS; + } + } + + if(ret == 0) + #endif + { + uint32_t ulSectorLast; + + IGNORE_ERRORS(sd_mmc_read_capacity(bVolNum, &ulSectorLast)); + + /* The ASF SD/MMC driver only supports 512-byte sectors. + */ + if( (gaRedVolConf[bVolNum].ulSectorSize != 512U) + || (((uint64_t)ulSectorLast + 1U) < gaRedVolConf[bVolNum].ullSectorCount)) + { + ret = -RED_EINVAL; + } + } + } + else + { + ret = -RED_EIO; + } + + return ret; +} + + +/** @brief Uninitialize a disk. + + @param bVolNum The volume number of the volume whose block device is being + uninitialized. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. +*/ +static REDSTATUS DiskClose( + uint8_t bVolNum) +{ + (void)bVolNum; + return 0; +} + + +/** @brief Read sectors from a disk. + + @param bVolNum The volume number of the volume whose block device + is being read from. + @param ullSectorStart The starting sector number. + @param ulSectorCount The number of sectors to read. + @param pBuffer The buffer into which to read the sector data. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. +*/ +static REDSTATUS DiskRead( + uint8_t bVolNum, + uint64_t ullSectorStart, + uint32_t ulSectorCount, + void *pBuffer) +{ + REDSTATUS ret = 0; + uint32_t ulSectorIdx = 0U; + uint32_t ulSectorSize = gaRedVolConf[bVolNum].ulSectorSize; + uint8_t *pbBuffer = CAST_VOID_PTR_TO_UINT8_PTR(pBuffer); + + while(ulSectorIdx < ulSectorCount) + { + uint32_t ulTransfer = REDMIN(ulSectorCount - ulSectorIdx, MAX_SECTOR_TRANSFER); + Ctrl_status cs; + + cs = sd_mmc_mem_2_ram_multi(bVolNum, (uint32_t)(ullSectorStart + ulSectorIdx), + (uint16_t)ulTransfer, &pbBuffer[ulSectorIdx * ulSectorSize]); + if(cs != CTRL_GOOD) + { + ret = -RED_EIO; + break; + } + + ulSectorIdx += ulTransfer; + } + + return ret; +} + + +#if REDCONF_READ_ONLY == 0 +/** @brief Write sectors to a disk. + + @param bVolNum The volume number of the volume whose block device + is being written to. + @param ullSectorStart The starting sector number. + @param ulSectorCount The number of sectors to write. + @param pBuffer The buffer from which to write the sector data. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. +*/ +static REDSTATUS DiskWrite( + uint8_t bVolNum, + uint64_t ullSectorStart, + uint32_t ulSectorCount, + const void *pBuffer) +{ + REDSTATUS ret = 0; + uint32_t ulSectorIdx = 0U; + uint32_t ulSectorSize = gaRedVolConf[bVolNum].ulSectorSize; + const uint8_t *pbBuffer = CAST_VOID_PTR_TO_CONST_UINT8_PTR(pBuffer); + + while(ulSectorIdx < ulSectorCount) + { + uint32_t ulTransfer = REDMIN(ulSectorCount - ulSectorIdx, MAX_SECTOR_TRANSFER); + Ctrl_status cs; + + cs = sd_mmc_ram_2_mem_multi(bVolNum, (uint32_t)(ullSectorStart + ulSectorIdx), + (uint16_t)ulTransfer, &pbBuffer[ulSectorIdx * ulSectorSize]); + if(cs != CTRL_GOOD) + { + ret = -RED_EIO; + break; + } + + ulSectorIdx += ulTransfer; + } + + return ret; +} + + +/** @brief Flush any caches beneath the file system. + + @param bVolNum The volume number of the volume whose block device is being + flushed. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. +*/ +static REDSTATUS DiskFlush( + uint8_t bVolNum) +{ + REDSTATUS ret; + Ctrl_status cs; + + /* The ASF SD/MMC driver appears to write sectors synchronously, so it + should be fine to do nothing and return success. However, Atmel's + implementation of the FatFs diskio.c file does the equivalent of the + below when the disk is flushed. Just in case this is important for some + non-obvious reason, do the same. + */ + cs = sd_mmc_test_unit_ready(bVolNum); + if(cs == CTRL_GOOD) + { + ret = 0; + } + else + { + ret = -RED_EIO; + } + + return ret; +} +#endif /* REDCONF_READ_ONLY == 0 */ + +#elif BDEV_EXAMPLE_IMPLEMENTATION == BDEV_STM32_SDIO + +#ifdef USE_STM324xG_EVAL + #include + #include +#elif defined(USE_STM32746G_DISCO) + #include + #include +#else + /* If you are using a compatible STM32 device other than the two listed above + and you have SD card driver headers, you can try adding them to the above + list. + */ + #error "Unsupported device." +#endif + +#if REDCONF_VOLUME_COUNT > 1 + #error "The STM32 SDIO block device implementation does not support multiple volumes." +#endif + + +#ifndef USE_HAL_DRIVER + #error "The STM32 StdPeriph driver is not supported. Please use the HAL driver or modify the Reliance Edge block device interface." +#endif + + +/** @brief Number of times to call BSP_SD_GetStatus() before timing out and + returning an error. + + See ::CheckStatus(). + + NOTE: Datalight has not observed a scenario where BSP_SD_GetStatus() + returns SD_TRANSFER_BUSY after a transfer command returns successfully. + Set SD_STATUS_TIMEOUT to 0U to skip checking BSP_SD_GetStatus(). +*/ +#define SD_STATUS_TIMEOUT (100000U) + +/** @brief 4-byte aligned buffer to use for DMA transfers when passed in + an unaligned buffer. +*/ +static uint32_t gaulAlignedBuffer[512U / sizeof(uint32_t)]; + + +#if SD_STATUS_TIMEOUT > 0U +static REDSTATUS CheckStatus(void); +#endif + + +/** @brief Initialize a disk. + + @param bVolNum The volume number of the volume whose block device is being + initialized. + @param mode The open mode, indicating the type of access required. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO No SD card was found; or BSP_SD_Init() failed. + @retval -RED_EINVAL The SD card's block size is not the same as the + configured sector size; or the SD card is not large + enough for the volume; or the volume size is above + 4GiB, meaning that part of it cannot be accessed + through the STM32 SDIO driver. +*/ +static REDSTATUS DiskOpen( + uint8_t bVolNum, + BDEVOPENMODE mode) +{ + REDSTATUS ret = 0; + static bool fSdInitted = false; + + (void) mode; + + if(!fSdInitted) + { + if(BSP_SD_Init() == MSD_OK) + { + fSdInitted = true; + } + } + + if(!fSdInitted) + { + /* Above initialization attempt failed. + */ + ret = -RED_EIO; + } + else if(BSP_SD_IsDetected() == SD_NOT_PRESENT) + { + ret = -RED_EIO; + } + else + { + uint32_t ulSectorSize = gaRedVolConf[bVolNum].ulSectorSize; + HAL_SD_CardInfoTypedef sdCardInfo = {{0}}; + + BSP_SD_GetCardInfo(&sdCardInfo); + + /* Note: the actual card block size is sdCardInfo.CardBlockSize, + but the interface only supports a 512 byte block size. Further, + one card has been observed to report a 1024-byte block size, + but it worked fine with a 512-byte Reliance Edge ulSectorSize. + */ + if( (ulSectorSize != 512U) + || (sdCardInfo.CardCapacity < (gaRedVolConf[bVolNum].ullSectorCount * ulSectorSize))) + { + ret = -RED_EINVAL; + } + } + + return ret; +} + + +/** @brief Uninitialize a disk. + + @param bVolNum The volume number of the volume whose block device is being + uninitialized. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. +*/ +static REDSTATUS DiskClose( + uint8_t bVolNum) +{ + (void)bVolNum; + return 0; +} + + +/** @brief Read sectors from a disk. + + @param bVolNum The volume number of the volume whose block device + is being read from. + @param ullSectorStart The starting sector number. + @param ulSectorCount The number of sectors to read. + @param pBuffer The buffer into which to read the sector data. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. +*/ +static REDSTATUS DiskRead( + uint8_t bVolNum, + uint64_t ullSectorStart, + uint32_t ulSectorCount, + void *pBuffer) +{ + REDSTATUS redStat = 0; + uint32_t ulSectorSize = gaRedVolConf[bVolNum].ulSectorSize; + uint8_t bSdError; + + if(IS_UINT32_ALIGNED_PTR(pBuffer)) + { + bSdError = BSP_SD_ReadBlocks_DMA(CAST_UINT32_PTR(pBuffer), ullSectorStart * ulSectorSize, ulSectorSize, ulSectorCount); + + if(bSdError != MSD_OK) + { + redStat = -RED_EIO; + } + #if SD_STATUS_TIMEOUT > 0U + else + { + redStat = CheckStatus(); + } + #endif + } + else + { + uint32_t ulSectorIdx; + + for(ulSectorIdx = 0U; ulSectorIdx < ulSectorCount; ulSectorIdx++) + { + bSdError = BSP_SD_ReadBlocks_DMA(gaulAlignedBuffer, (ullSectorStart + ulSectorIdx) * ulSectorSize, ulSectorSize, 1U); + + if(bSdError != MSD_OK) + { + redStat = -RED_EIO; + } + #if SD_STATUS_TIMEOUT > 0U + else + { + redStat = CheckStatus(); + } + #endif + + if(redStat == 0) + { + uint8_t *pbBuffer = CAST_VOID_PTR_TO_UINT8_PTR(pBuffer); + + RedMemCpy(&pbBuffer[ulSectorIdx * ulSectorSize], gaulAlignedBuffer, ulSectorSize); + } + else + { + break; + } + } + } + + return redStat; +} + + +#if REDCONF_READ_ONLY == 0 +/** @brief Write sectors to a disk. + + @param bVolNum The volume number of the volume whose block device + is being written to. + @param ullSectorStart The starting sector number. + @param ulSectorCount The number of sectors to write. + @param pBuffer The buffer from which to write the sector data. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. +*/ +static REDSTATUS DiskWrite( + uint8_t bVolNum, + uint64_t ullSectorStart, + uint32_t ulSectorCount, + const void *pBuffer) +{ + REDSTATUS redStat = 0; + uint32_t ulSectorSize = gaRedVolConf[bVolNum].ulSectorSize; + uint8_t bSdError; + + if(IS_UINT32_ALIGNED_PTR(pBuffer)) + { + bSdError = BSP_SD_WriteBlocks_DMA(CAST_UINT32_PTR(CAST_AWAY_CONST(void, pBuffer)), ullSectorStart * ulSectorSize, + ulSectorSize, ulSectorCount); + + if(bSdError != MSD_OK) + { + redStat = -RED_EIO; + } + #if SD_STATUS_TIMEOUT > 0U + else + { + redStat = CheckStatus(); + } + #endif + } + else + { + uint32_t ulSectorIdx; + + for(ulSectorIdx = 0U; ulSectorIdx < ulSectorCount; ulSectorIdx++) + { + const uint8_t *pbBuffer = CAST_VOID_PTR_TO_CONST_UINT8_PTR(pBuffer); + + RedMemCpy(gaulAlignedBuffer, &pbBuffer[ulSectorIdx * ulSectorSize], ulSectorSize); + + bSdError = BSP_SD_WriteBlocks_DMA(gaulAlignedBuffer, (ullSectorStart + ulSectorIdx) * ulSectorSize, ulSectorSize, 1U); + + if(bSdError != MSD_OK) + { + redStat = -RED_EIO; + } + #if SD_STATUS_TIMEOUT > 0U + else + { + redStat = CheckStatus(); + } + #endif + + if(redStat != 0) + { + break; + } + } + } + + return redStat; +} + + +/** @brief Flush any caches beneath the file system. + + @param bVolNum The volume number of the volume whose block device is being + flushed. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. +*/ +static REDSTATUS DiskFlush( + uint8_t bVolNum) +{ + /* Disk transfer is synchronous; nothing to flush. + */ + (void) bVolNum; + return 0; +} + + +#if SD_STATUS_TIMEOUT > 0U +/** @brief Wait until BSP_SD_GetStatus returns SD_TRANSFER_OK. + + This function calls BSP_SD_GetStatus repeatedly as long as it returns + SD_TRANSFER_BUSY up to SD_STATUS_TIMEOUT times. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 SD_TRANSFER_OK was returned. + @retval -RED_EIO SD_TRANSFER_ERROR received, or timed out waiting for + SD_TRANSFER_OK. +*/ +static REDSTATUS CheckStatus(void) +{ + REDSTATUS redStat = 0; + uint32_t ulTimeout = SD_STATUS_TIMEOUT; + HAL_SD_TransferStateTypedef transferState; + + do + { + transferState = BSP_SD_GetStatus(); + ulTimeout--; + } while((transferState == SD_TRANSFER_BUSY) && (ulTimeout > 0U)); + + if(transferState != SD_TRANSFER_OK) + { + redStat = -RED_EIO; + } + + return redStat; +} +#endif + +#endif /* REDCONF_READ_ONLY == 0 */ + +#elif BDEV_EXAMPLE_IMPLEMENTATION == BDEV_RAM_DISK + +#include /* For ALLOCATE_CLEARED_MEMORY(), which expands to calloc(). */ + + +static uint8_t *gapbRamDisk[REDCONF_VOLUME_COUNT]; + + +/** @brief Initialize a disk. + + @param bVolNum The volume number of the volume whose block device is being + initialized. + @param mode The open mode, indicating the type of access required. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EIO A disk I/O error occurred. +*/ +static REDSTATUS DiskOpen( + uint8_t bVolNum, + BDEVOPENMODE mode) +{ + REDSTATUS ret = 0; + + (void)mode; + + if(gapbRamDisk[bVolNum] == NULL) + { + gapbRamDisk[bVolNum] = ALLOCATE_CLEARED_MEMORY(gaRedVolume[bVolNum].ulBlockCount, REDCONF_BLOCK_SIZE); + if(gapbRamDisk[bVolNum] == NULL) + { + ret = -RED_EIO; + } + } + + return ret; +} + + +/** @brief Uninitialize a disk. + + @param bVolNum The volume number of the volume whose block device is being + uninitialized. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. +*/ +static REDSTATUS DiskClose( + uint8_t bVolNum) +{ + REDSTATUS ret; + + if(gapbRamDisk[bVolNum] == NULL) + { + ret = -RED_EINVAL; + } + else + { + /* This implementation uses dynamically allocated memory, but must + retain previously written data after the block device is closed, and + thus the memory cannot be freed and will remain allocated until + reboot. + */ + ret = 0; + } + + return ret; +} + + +/** @brief Read sectors from a disk. + + @param bVolNum The volume number of the volume whose block device + is being read from. + @param ullSectorStart The starting sector number. + @param ulSectorCount The number of sectors to read. + @param pBuffer The buffer into which to read the sector data. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. +*/ +static REDSTATUS DiskRead( + uint8_t bVolNum, + uint64_t ullSectorStart, + uint32_t ulSectorCount, + void *pBuffer) +{ + REDSTATUS ret; + + if(gapbRamDisk[bVolNum] == NULL) + { + ret = -RED_EINVAL; + } + else + { + uint64_t ullByteOffset = ullSectorStart * gaRedVolConf[bVolNum].ulSectorSize; + uint32_t ulByteCount = ulSectorCount * gaRedVolConf[bVolNum].ulSectorSize; + + RedMemCpy(pBuffer, &gapbRamDisk[bVolNum][ullByteOffset], ulByteCount); + + ret = 0; + } + + return ret; +} + + +#if REDCONF_READ_ONLY == 0 +/** @brief Write sectors to a disk. + + @param bVolNum The volume number of the volume whose block device + is being written to. + @param ullSectorStart The starting sector number. + @param ulSectorCount The number of sectors to write. + @param pBuffer The buffer from which to write the sector data. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. +*/ +static REDSTATUS DiskWrite( + uint8_t bVolNum, + uint64_t ullSectorStart, + uint32_t ulSectorCount, + const void *pBuffer) +{ + REDSTATUS ret; + + if(gapbRamDisk[bVolNum] == NULL) + { + ret = -RED_EINVAL; + } + else + { + uint64_t ullByteOffset = ullSectorStart * gaRedVolConf[bVolNum].ulSectorSize; + uint32_t ulByteCount = ulSectorCount * gaRedVolConf[bVolNum].ulSectorSize; + + RedMemCpy(&gapbRamDisk[bVolNum][ullByteOffset], pBuffer, ulByteCount); + + ret = 0; + } + + return ret; +} + + +/** @brief Flush any caches beneath the file system. + + @param bVolNum The volume number of the volume whose block device is being + flushed. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. +*/ +static REDSTATUS DiskFlush( + uint8_t bVolNum) +{ + REDSTATUS ret; + + if(gapbRamDisk[bVolNum] == NULL) + { + ret = -RED_EINVAL; + } + else + { + ret = 0; + } + + return ret; +} +#endif /* REDCONF_READ_ONLY == 0 */ + +#else + +#error "Invalid BDEV_EXAMPLE_IMPLEMENTATION value" + +#endif /* BDEV_EXAMPLE_IMPLEMENTATION == ... */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/services/osclock.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/services/osclock.c new file mode 100644 index 0000000..cf09d17 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/services/osclock.c @@ -0,0 +1,79 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements real-time clock functions. +*/ +#include + + +/** @brief Initialize the real time clock. + + The behavior of calling this function when the RTC is already initialized + is undefined. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. +*/ +REDSTATUS RedOsClockInit(void) +{ + return 0; +} + + +/** @brief Uninitialize the real time clock. + + The behavior of calling this function when the RTC is not initialized is + undefined. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. +*/ +REDSTATUS RedOsClockUninit(void) +{ + return 0; +} + + +/** @brief Get the date/time. + + The behavior of calling this function when the RTC is not initialized is + undefined. + + @return The number of seconds since January 1, 1970 excluding leap seconds + (in other words, standard Unix time). If the resolution or epoch + of the RTC is different than this, the implementation must convert + it to the expected representation. +*/ +uint32_t RedOsClockGetTime(void) +{ + /* FreeRTOS does not provide an RTC abstraction since most of the systems + it targets have no RTC hardware. If your hardware includes an RTC that + you would like to use, this function must be customized. + */ + return 0; +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/services/osmutex.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/services/osmutex.c new file mode 100644 index 0000000..68cd0ed --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/services/osmutex.c @@ -0,0 +1,134 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements a synchronization object to provide mutual exclusion. +*/ +#include +#include + +#include +#include + +#if REDCONF_TASK_COUNT > 1U + + +static SemaphoreHandle_t xMutex; +#if defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION == 1) +static StaticSemaphore_t xMutexBuffer; +#endif + + +/** @brief Initialize the mutex. + + After initialization, the mutex is in the released state. + + The behavior of calling this function when the mutex is still initialized + is undefined. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. +*/ +REDSTATUS RedOsMutexInit(void) +{ + REDSTATUS ret = 0; + + #if defined(configSUPPORT_STATIC_ALLOCATION) && (configSUPPORT_STATIC_ALLOCATION == 1) + xMutex = xSemaphoreCreateMutexStatic(&xMutexBuffer); + + if(xMutex == NULL) + { + /* The only error case for xSemaphoreCreateMutexStatic is that the mutex + buffer parameter is NULL, which is not the case. + */ + REDERROR(); + ret = -RED_EINVAL; + } + + #else + xMutex = xSemaphoreCreateMutex(); + if(xMutex == NULL) + { + ret = -RED_ENOMEM; + } + #endif + + return ret; +} + + +/** @brief Uninitialize the mutex. + + The behavior of calling this function when the mutex is not initialized is + undefined; likewise, the behavior of uninitializing the mutex when it is + in the acquired state is undefined. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. +*/ +REDSTATUS RedOsMutexUninit(void) +{ + vSemaphoreDelete(xMutex); + xMutex = NULL; + + return 0; +} + + +/** @brief Acquire the mutex. + + The behavior of calling this function when the mutex is not initialized is + undefined; likewise, the behavior of recursively acquiring the mutex is + undefined. +*/ +void RedOsMutexAcquire(void) +{ + while(xSemaphoreTake(xMutex, portMAX_DELAY) != pdTRUE) + { + } +} + + +/** @brief Release the mutex. + + The behavior is undefined in the following cases: + + - Releasing the mutex when the mutex is not initialized. + - Releasing the mutex when it is not in the acquired state. + - Releasing the mutex from a task or thread other than the one which + acquired the mutex. +*/ +void RedOsMutexRelease(void) +{ + BaseType_t xSuccess; + + xSuccess = xSemaphoreGive(xMutex); + REDASSERT(xSuccess == pdTRUE); + IGNORE_ERRORS(xSuccess); +} + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/services/osoutput.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/services/osoutput.c new file mode 100644 index 0000000..f493890 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/services/osoutput.c @@ -0,0 +1,70 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements outputting a character string. +*/ +#include + +#if REDCONF_OUTPUT == 1 + +#include + + +/** @brief Write a string to a user-visible output location. + + Write a null-terminated string to the serial port, console, terminal, or + other display device, such that the text is visible to the user. + + @param pszString A null-terminated string. +*/ +void RedOsOutputString( + const char *pszString) +{ + if(pszString == NULL) + { + REDERROR(); + } + else + { + uint32_t ulIdx = 0U; + + while(pszString[ulIdx] != '\0') + { + OUTPUT_CHARACTER(pszString[ulIdx]); + + /* Serial output often requires a \r to print newlines correctly. + */ + if(pszString[ulIdx] == '\n') + { + OUTPUT_CHARACTER('\r'); + } + + ulIdx++; + } + } +} + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/services/ostask.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/services/ostask.c new file mode 100644 index 0000000..799c152 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/services/ostask.c @@ -0,0 +1,68 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements task functions. +*/ +#include +#include + +#include + +#if (REDCONF_TASK_COUNT > 1U) && (REDCONF_API_POSIX == 1) + +#include + +#if INCLUDE_xTaskGetCurrentTaskHandle != 1 + #error "INCLUDE_xTaskGetCurrentTaskHandle must be 1 when REDCONF_TASK_COUNT > 1 and REDCONF_API_POSIX == 1" +#endif + + +/** @brief Get the current task ID. + + This task ID must be unique for all tasks using the file system. + + @return The task ID. Must not be 0. +*/ +uint32_t RedOsTaskId(void) +{ + /* Simply casting the xTaskGetCurrentTaskHandle() return value results in + warnings from some compilers, so use variables. + */ + TaskHandle_t xTask = xTaskGetCurrentTaskHandle(); + uintptr_t taskptr = CAST_TASK_PTR_TO_UINTPTR(xTask); + uint32_t ulTaskPtr = (uint32_t)taskptr; + + /* Assert no information was lost casting from uintptr_t to uint32_t. + */ + REDASSERT(ulTaskPtr == taskptr); + + /* NULL is a valid task handle in FreeRTOS, so add one to all task IDs. + */ + REDASSERT((ulTaskPtr + 1U) != 0U); + return ulTaskPtr + 1U; +} + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/services/ostimestamp.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/services/ostimestamp.c new file mode 100644 index 0000000..d019d3a --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/os/freertos/services/ostimestamp.c @@ -0,0 +1,109 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements timestamp functions. + + The functionality implemented herein is not needed for the file system + driver, only to provide accurate results with performance tests. +*/ +#include +#include + +#include + + +/* configTICK_RATE_HZ is almost always 100, 250, 500, or 1000. If + 1000000U % configTICK_RATE_HZ != 0, then RedOsTimePassed() will be a + little inaccurate. +*/ +#define MICROSECS_PER_TICK (1000000U / configTICK_RATE_HZ) + + +/** @brief Initialize the timestamp service. + + The behavior of invoking this function when timestamps are already + initialized is undefined. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_ENOSYS The timestamp service has not been implemented. +*/ +REDSTATUS RedOsTimestampInit(void) +{ + return 0; +} + + +/** @brief Uninitialize the timestamp service. + + The behavior of invoking this function when timestamps are not initialized + is undefined. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. +*/ +REDSTATUS RedOsTimestampUninit(void) +{ + return 0; +} + + +/** @brief Retrieve a timestamp. + + The behavior of invoking this function when timestamps are not initialized + is undefined + + @return A timestamp which can later be passed to RedOsTimePassed() to + determine the amount of time which passed between the two calls. +*/ +REDTIMESTAMP RedOsTimestamp(void) +{ + return xTaskGetTickCount(); +} + + +/** @brief Determine how much time has passed since a timestamp was retrieved. + + The behavior of invoking this function when timestamps are not initialized + is undefined. + + @param tsSince A timestamp acquired earlier via RedOsTimestamp(). + + @return The number of microseconds which have passed since @p tsSince. +*/ +uint64_t RedOsTimePassed( + REDTIMESTAMP tsSince) +{ + /* This works even if the tick count has wrapped around, provided it has + only wrapped around once. + */ + uint32_t ulTicksPassed = (uint32_t)xTaskGetTickCount() - tsSince; + uint64_t ullMicrosecs = (uint64_t)ulTicksPassed * MICROSECS_PER_TICK; + + return ullMicrosecs; +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/posix/path.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/posix/path.c new file mode 100644 index 0000000..ecdf0a7 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/posix/path.c @@ -0,0 +1,448 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements path utilities for the POSIX-like API layer. +*/ +#include + +#if REDCONF_API_POSIX == 1 + +#include +#include +#include +#include + + +static bool IsRootDir(const char *pszLocalPath); +static bool PathHasMoreNames(const char *pszPathIdx); + + +/** @brief Split a path into its component parts: a volume and a volume-local + path. + + @param pszPath The path to split. + @param pbVolNum On successful return, if non-NULL, populated with + the volume number extracted from the path. + @param ppszLocalPath On successful return, populated with the + volume-local path: the path stripped of any volume + path prefixing. If this parameter is NULL, that + indicates there should be no local path, and any + characters beyond the prefix (other than path + separators) are treated as an error. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p pszPath is `NULL`. + @retval -RED_ENOENT @p pszPath could not be matched to any volume; or + @p ppszLocalPath is NULL but @p pszPath includes a local + path. +*/ +REDSTATUS RedPathSplit( + const char *pszPath, + uint8_t *pbVolNum, + const char **ppszLocalPath) +{ + REDSTATUS ret = 0; + + if(pszPath == NULL) + { + ret = -RED_EINVAL; + } + else + { + const char *pszLocalPath = pszPath; + uint8_t bMatchVol = UINT8_MAX; + uint32_t ulMatchLen = 0U; + uint8_t bDefaultVolNum = UINT8_MAX; + uint8_t bVolNum; + + for(bVolNum = 0U; bVolNum < REDCONF_VOLUME_COUNT; bVolNum++) + { + const char *pszPrefix = gaRedVolConf[bVolNum].pszPathPrefix; + uint32_t ulPrefixLen = RedStrLen(pszPrefix); + + if(ulPrefixLen == 0U) + { + /* A volume with a path prefix of an empty string is the + default volume, used when the path does not match the + prefix of any other volume. + + The default volume should only be found once. During + initialization, RedCoreInit() ensures that all volume + prefixes are unique (including empty prefixes). + */ + REDASSERT(bDefaultVolNum == UINT8_MAX); + bDefaultVolNum = bVolNum; + } + /* For a path to match, it must either be the prefix exactly, or + be followed by a path separator character. Thus, with a volume + prefix of "/foo", both "/foo" and "/foo/bar" are matches, but + "/foobar" is not. + */ + else if( (RedStrNCmp(pszPath, pszPrefix, ulPrefixLen) == 0) + && ((pszPath[ulPrefixLen] == '\0') || (pszPath[ulPrefixLen] == REDCONF_PATH_SEPARATOR))) + { + /* The length of this match should never exactly equal the + length of a previous match: that would require a duplicate + volume name, which should have been detected during init. + */ + REDASSERT(ulPrefixLen != ulMatchLen); + + /* If multiple prefixes match, the longest takes precedence. + Thus, if there are two prefixes "Flash" and "Flash/Backup", + the path "Flash/Backup/" will not be erroneously matched + with the "Flash" volume. + */ + if(ulPrefixLen > ulMatchLen) + { + bMatchVol = bVolNum; + ulMatchLen = ulPrefixLen; + } + } + else + { + /* No match, keep looking. + */ + } + } + + if(bMatchVol != UINT8_MAX) + { + /* The path matched a volume path prefix. + */ + bVolNum = bMatchVol; + pszLocalPath = &pszPath[ulMatchLen]; + } + else if(bDefaultVolNum != UINT8_MAX) + { + /* The path didn't match any of the prefixes, but one of the + volumes has a path prefix of "", so an unprefixed path is + assigned to that volume. + */ + bVolNum = bDefaultVolNum; + REDASSERT(pszLocalPath == pszPath); + } + else + { + /* The path cannot be assigned a volume. + */ + ret = -RED_ENOENT; + } + + if(ret == 0) + { + if(pbVolNum != NULL) + { + *pbVolNum = bVolNum; + } + + if(ppszLocalPath != NULL) + { + *ppszLocalPath = pszLocalPath; + } + else + { + /* If no local path is expected, then the string should either + terminate after the path prefix or the local path should name + the root directory. Allowing path separators here means that + red_mount("/data/") is OK with a path prefix of "/data". + */ + if(pszLocalPath[0U] != '\0') + { + if(!IsRootDir(pszLocalPath)) + { + ret = -RED_ENOENT; + } + } + } + } + } + + return ret; +} + + +/** @brief Lookup the inode named by the given path. + + @param pszLocalPath The path to lookup; this is a local path, without any + volume prefix. + @param pulInode On successful return, populated with the number of the + inode named by @p pszLocalPath. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p pszLocalPath is `NULL`; or @p pulInode is + `NULL`. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENOENT @p pszLocalPath is an empty string; or + @p pszLocalPath does not name an existing file + or directory. + @retval -RED_ENOTDIR A component of the path other than the last is + not a directory. + @retval -RED_ENAMETOOLONG The length of a component of @p pszLocalPath is + longer than #REDCONF_NAME_MAX. +*/ +REDSTATUS RedPathLookup( + const char *pszLocalPath, + uint32_t *pulInode) +{ + REDSTATUS ret; + + if((pszLocalPath == NULL) || (pulInode == NULL)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else if(pszLocalPath[0U] == '\0') + { + ret = -RED_ENOENT; + } + else if(IsRootDir(pszLocalPath)) + { + ret = 0; + *pulInode = INODE_ROOTDIR; + } + else + { + uint32_t ulPInode; + const char *pszName; + + ret = RedPathToName(pszLocalPath, &ulPInode, &pszName); + + if(ret == 0) + { + ret = RedCoreLookup(ulPInode, pszName, pulInode); + } + } + + return ret; +} + + +/** @brief Given a path, return the parent inode number and a pointer to the + last component in the path (the name). + + @param pszLocalPath The path to examine; this is a local path, without any + volume prefix. + @param pulPInode On successful return, populated with the inode number of + the parent directory of the last component in the path. + For example, with the path "a/b/c", populated with the + inode number of "b". + @param ppszName On successful return, populated with a pointer to the + last component in the path. For example, with the path + "a/b/c", populated with a pointer to "c". + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p pszLocalPath is `NULL`; or @p pulPInode is + `NULL`; or @p ppszName is `NULL`; or the path + names the root directory. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENOENT @p pszLocalPath is an empty string; or a + component of the path other than the last does + not exist. + @retval -RED_ENOTDIR A component of the path other than the last is + not a directory. + @retval -RED_ENAMETOOLONG The length of a component of @p pszLocalPath is + longer than #REDCONF_NAME_MAX. +*/ +REDSTATUS RedPathToName( + const char *pszLocalPath, + uint32_t *pulPInode, + const char **ppszName) +{ + REDSTATUS ret; + + if((pszLocalPath == NULL) || (pulPInode == NULL) || (ppszName == NULL)) + { + REDERROR(); + ret = -RED_EINVAL; + } + else if(IsRootDir(pszLocalPath)) + { + ret = -RED_EINVAL; + } + else if(pszLocalPath[0U] == '\0') + { + ret = -RED_ENOENT; + } + else + { + uint32_t ulInode = INODE_ROOTDIR; + uint32_t ulPInode = INODE_INVALID; + uint32_t ulPathIdx = 0U; + uint32_t ulLastNameIdx = 0U; + + ret = 0; + + do + { + uint32_t ulNameLen; + + /* Skip over path separators, to get pszLocalPath[ulPathIdx] + pointing at the next name. + */ + while(pszLocalPath[ulPathIdx] == REDCONF_PATH_SEPARATOR) + { + ulPathIdx++; + } + + if(pszLocalPath[ulPathIdx] == '\0') + { + break; + } + + /* Point ulLastNameIdx at the first character of the name; after + we exit the loop, it will point at the first character of the + last name in the path. + */ + ulLastNameIdx = ulPathIdx; + + /* Point ulPInode at the parent inode: either the root inode + (first pass) or the inode of the previous name. After we exit + the loop, this will point at the parent inode of the last name. + */ + ulPInode = ulInode; + + ulNameLen = RedNameLen(&pszLocalPath[ulPathIdx]); + + /* Lookup the inode of the name, unless we are at the last name in + the path: we don't care whether the last name exists or not. + */ + if(PathHasMoreNames(&pszLocalPath[ulPathIdx + ulNameLen])) + { + ret = RedCoreLookup(ulPInode, &pszLocalPath[ulPathIdx], &ulInode); + } + + /* Move on to the next path element. + */ + if(ret == 0) + { + ulPathIdx += ulNameLen; + } + } + while(ret == 0); + + if(ret == 0) + { + *pulPInode = ulPInode; + *ppszName = &pszLocalPath[ulLastNameIdx]; + } + } + + return ret; +} + + +/** @brief Determine whether a path names the root directory. + + @param pszLocalPath The path to examine; this is a local path, without any + volume prefix. + + @return Returns whether @p pszLocalPath names the root directory. + + @retval true @p pszLocalPath names the root directory. + @retval false @p pszLocalPath does not name the root directory. +*/ +static bool IsRootDir( + const char *pszLocalPath) +{ + bool fRet; + + if(pszLocalPath == NULL) + { + REDERROR(); + fRet = false; + } + else + { + uint32_t ulIdx = 0U; + + /* A string containing nothing but path separators (usually only one) + names the root directory. An empty string does *not* name the root + directory, since in POSIX empty strings typically elicit -RED_ENOENT + errors. + */ + while(pszLocalPath[ulIdx] == REDCONF_PATH_SEPARATOR) + { + ulIdx++; + } + + fRet = (ulIdx > 0U) && (pszLocalPath[ulIdx] == '\0'); + } + + return fRet; +} + + +/** @brief Determine whether there are more names in a path. + + Example | Result + ------- | ------ + "" false + "/" false + "//" false + "a" true + "/a" true + "//a" true + + @param pszPathIdx The path to examine, incremented to the point of + interest. + + @return Returns whether there are more names in @p pszPathIdx. + + @retval true @p pszPathIdx has more names. + @retval false @p pszPathIdx has no more names. +*/ +static bool PathHasMoreNames( + const char *pszPathIdx) +{ + bool fRet; + + if(pszPathIdx == NULL) + { + REDERROR(); + fRet = false; + } + else + { + uint32_t ulIdx = 0U; + + while(pszPathIdx[ulIdx] == REDCONF_PATH_SEPARATOR) + { + ulIdx++; + } + + fRet = pszPathIdx[ulIdx] != '\0'; + } + + return fRet; +} + +#endif /* REDCONF_API_POSIX */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/posix/posix.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/posix/posix.c new file mode 100644 index 0000000..7a21f06 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/posix/posix.c @@ -0,0 +1,3088 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implementation of the the Reliance Edge POSIX-like API. +*/ + +#include + +#if REDCONF_API_POSIX == 1 + +/** @defgroup red_group_posix The POSIX-like File System Interface + @{ +*/ + +#include +#include +#include +#include + + +/*------------------------------------------------------------------- + File Descriptors +-------------------------------------------------------------------*/ + +#define FD_GEN_BITS 11U /* File descriptor bits for mount generation. */ +#define FD_VOL_BITS 8U /* File descriptor bits for volume number. */ +#define FD_IDX_BITS 12U /* File descriptor bits for handle index. */ + +/* 31 bits available: file descriptors are int32_t, but the sign bit must + always be zero. +*/ +#if (FD_GEN_BITS + FD_VOL_BITS + FD_IDX_BITS) > 31U + #error "Internal error: too many file descriptor bits!" +#endif + +/* Maximum values for file descriptor components. +*/ +#define FD_GEN_MAX ((1UL << FD_GEN_BITS) - 1U) +#define FD_VOL_MAX ((1UL << FD_VOL_BITS) - 1U) +#define FD_IDX_MAX ((1UL << FD_IDX_BITS) - 1U) + +#if REDCONF_VOLUME_COUNT > FD_VOL_MAX + #error "Error: Too many file system volumes!" +#endif +#if REDCONF_HANDLE_COUNT > (FD_IDX_MAX + 1U) + #error "Error: Too many file system handles!" +#endif + +/* File descriptors must never be negative; and must never be zero, one, or + two, to avoid confusion with STDIN, STDOUT, and STDERR. +*/ +#define FD_MIN (3) + +/*------------------------------------------------------------------- + Handles +-------------------------------------------------------------------*/ + +/* Mask of all RED_O_* values. +*/ +#define RED_O_MASK (RED_O_RDONLY|RED_O_WRONLY|RED_O_RDWR|RED_O_APPEND|RED_O_CREAT|RED_O_EXCL|RED_O_TRUNC) + +#define HFLAG_DIRECTORY 0x01U /* Handle is for a directory. */ +#define HFLAG_READABLE 0x02U /* Handle is readable. */ +#define HFLAG_WRITEABLE 0x04U /* Handle is writeable. */ +#define HFLAG_APPENDING 0x08U /* Handle was opened in append mode. */ + +/* @brief Handle structure, used to implement file descriptors and directory + streams. +*/ +typedef struct sREDHANDLE +{ + uint32_t ulInode; /**< Inode number; 0 if handle is available. */ + uint8_t bVolNum; /**< Volume containing the inode. */ + uint8_t bFlags; /**< Handle flags (type and mode). */ + uint64_t ullOffset; /**< File or directory offset. */ + #if REDCONF_API_POSIX_READDIR == 1 + REDDIRENT dirent; /**< Dirent structure returned by red_readdir(). */ + #endif +} REDHANDLE; + +/*------------------------------------------------------------------- + Tasks +-------------------------------------------------------------------*/ + +#if REDCONF_TASK_COUNT > 1U +/* @brief Per-task information. +*/ +typedef struct +{ + uint32_t ulTaskId; /**< ID of the task which owns this slot; 0 if free. */ + REDSTATUS iErrno; /**< Last error value. */ +} TASKSLOT; +#endif + +/*------------------------------------------------------------------- + Local Prototypes +-------------------------------------------------------------------*/ + +#if (REDCONF_READ_ONLY == 0) && ((REDCONF_API_POSIX_UNLINK == 1) || (REDCONF_API_POSIX_RMDIR == 1)) +static REDSTATUS UnlinkSub(const char *pszPath, FTYPE type); +#endif +static REDSTATUS FildesOpen(const char *pszPath, uint32_t ulOpenMode, FTYPE type, int32_t *piFildes); +static REDSTATUS FildesClose(int32_t iFildes); +static REDSTATUS FildesToHandle(int32_t iFildes, FTYPE expectedType, REDHANDLE **ppHandle); +static int32_t FildesPack(uint16_t uHandleIdx, uint8_t bVolNum); +static void FildesUnpack(int32_t iFildes, uint16_t *puHandleIdx, uint8_t *pbVolNum, uint16_t *puGeneration); +#if REDCONF_API_POSIX_READDIR == 1 +static bool DirStreamIsValid(const REDDIR *pDirStream); +#endif +static REDSTATUS PosixEnter(void); +static void PosixLeave(void); +static REDSTATUS ModeTypeCheck(uint16_t uMode, FTYPE expectedType); +#if (REDCONF_READ_ONLY == 0) && ((REDCONF_API_POSIX_UNLINK == 1) || (REDCONF_API_POSIX_RMDIR == 1) || ((REDCONF_API_POSIX_RENAME == 1) && (REDCONF_RENAME_ATOMIC == 1))) +static REDSTATUS InodeUnlinkCheck(uint32_t ulInode); +#endif +#if REDCONF_TASK_COUNT > 1U +static REDSTATUS TaskRegister(uint32_t *pulTaskIdx); +#endif +static int32_t PosixReturn(REDSTATUS iError); + +/*------------------------------------------------------------------- + Globals +-------------------------------------------------------------------*/ + +static bool gfPosixInited; /* Whether driver is initialized. */ +static REDHANDLE gaHandle[REDCONF_HANDLE_COUNT]; /* Array of all handles. */ +#if REDCONF_TASK_COUNT > 1U +static TASKSLOT gaTask[REDCONF_TASK_COUNT]; /* Array of task slots. */ +#endif + +/* Array of volume mount "generations". These are incremented for a volume + each time that volume is mounted. The generation number (along with the + volume number) is incorporated into the file descriptors; a stale file + descriptor from a previous mount can be detected since it will include a + stale generation number. +*/ +static uint16_t gauGeneration[REDCONF_VOLUME_COUNT]; + + +/*------------------------------------------------------------------- + Public API +-------------------------------------------------------------------*/ + +/** @brief Initialize the Reliance Edge file system driver. + + Prepares the Reliance Edge file system driver to be used. Must be the first + Reliance Edge function to be invoked: no volumes can be mounted or formatted + until the driver has been initialized. + + If this function is called when the Reliance Edge driver is already + initialized, it does nothing and returns success. + + This function is not thread safe: attempting to initialize from multiple + threads could leave things in a bad state. + + @return On success, zero is returned. On error, -1 is returned and + #red_errno is set appropriately. + + Errno values + - #RED_EINVAL: The volume path prefix configuration is invalid. +*/ +int32_t red_init(void) +{ + REDSTATUS ret; + + if(gfPosixInited) + { + ret = 0; + } + else + { + ret = RedCoreInit(); + if(ret == 0) + { + RedMemSet(gaHandle, 0U, sizeof(gaHandle)); + + #if REDCONF_TASK_COUNT > 1U + RedMemSet(gaTask, 0U, sizeof(gaTask)); + #endif + + gfPosixInited = true; + } + } + + return PosixReturn(ret); +} + + +/** @brief Uninitialize the Reliance Edge file system driver. + + Tears down the Reliance Edge file system driver. Cannot be used until all + Reliance Edge volumes are unmounted. A subsequent call to red_init() will + initialize the driver again. + + If this function is called when the Reliance Edge driver is already + uninitialized, it does nothing and returns success. + + This function is not thread safe: attempting to uninitialize from multiple + threads could leave things in a bad state. + + @return On success, zero is returned. On error, -1 is returned and + #red_errno is set appropriately. + + Errno values + - #RED_EBUSY: At least one volume is still mounted. +*/ +int32_t red_uninit(void) +{ + REDSTATUS ret; + + if(gfPosixInited) + { + ret = PosixEnter(); + + if(ret == 0) + { + uint8_t bVolNum; + + for(bVolNum = 0U; bVolNum < REDCONF_VOLUME_COUNT; bVolNum++) + { + if(gaRedVolume[bVolNum].fMounted) + { + ret = -RED_EBUSY; + break; + } + } + + if(ret == 0) + { + /* All volumes are unmounted. Mark the driver as + uninitialized before releasing the FS mutex, to avoid any + race condition where a volume could be mounted and then the + driver uninitialized with a mounted volume. + */ + gfPosixInited = false; + } + + /* The FS mutex must be released before we uninitialize the core, + since the FS mutex needs to be in the released state when it + gets uninitialized. + + Don't use PosixLeave(), since it asserts gfPosixInited is true. + */ + #if REDCONF_TASK_COUNT > 1U + RedOsMutexRelease(); + #endif + } + + if(ret == 0) + { + ret = RedCoreUninit(); + + /* Not good if the above fails, since things might be partly, but + not entirely, torn down, and there might not be a way back to + a valid driver state. + */ + REDASSERT(ret == 0); + } + } + else + { + ret = 0; + } + + return PosixReturn(ret); +} + + +/** @brief Mount a file system volume. + + Prepares the file system volume to be accessed. Mount will fail if the + volume has never been formatted, or if the on-disk format is inconsistent + with the compile-time configuration. + + An error is returned if the volume is already mounted. + + @param pszVolume A path prefix identifying the volume to mount. + + @return On success, zero is returned. On error, -1 is returned and + #red_errno is set appropriately. + + Errno values + - #RED_EBUSY: Volume is already mounted. + - #RED_EINVAL: @p pszVolume is `NULL`; or the driver is uninitialized. + - #RED_EIO: Volume not formatted, improperly formatted, or corrupt. + - #RED_ENOENT: @p pszVolume is not a valid volume path prefix. + - #RED_EUSERS: Cannot become a file system user: too many users. +*/ +int32_t red_mount( + const char *pszVolume) +{ + REDSTATUS ret; + + ret = PosixEnter(); + + if(ret == 0) + { + uint8_t bVolNum; + + ret = RedPathSplit(pszVolume, &bVolNum, NULL); + + /* The core will return success if the volume is already mounted, so + check for that condition here to propagate the error. + */ + if((ret == 0) && gaRedVolume[bVolNum].fMounted) + { + ret = -RED_EBUSY; + } + + #if REDCONF_VOLUME_COUNT > 1U + if(ret == 0) + { + ret = RedCoreVolSetCurrent(bVolNum); + } + #endif + + if(ret == 0) + { + ret = RedCoreVolMount(); + } + + if(ret == 0) + { + /* Increment the mount generation, invalidating file descriptors + from previous mounts. Note that while the generation numbers + are stored in 16-bit values, we have less than 16-bits to store + generations in the file descriptors, so we must wrap-around + manually. + */ + gauGeneration[bVolNum]++; + if(gauGeneration[bVolNum] > FD_GEN_MAX) + { + /* Wrap-around to one, rather than zero. The generation is + stored in the top bits of the file descriptor, and doing + this means that low numbers are never valid file + descriptors. This implements the requirement that 0, 1, + and 2 are never valid file descriptors, thereby avoiding + confusion with STDIN, STDOUT, and STDERR. + */ + gauGeneration[bVolNum] = 1U; + } + } + + PosixLeave(); + } + + return PosixReturn(ret); +} + + +/** @brief Unmount a file system volume. + + This function discards the in-memory state for the file system and marks it + as unmounted. Subsequent attempts to access the volume will fail until the + volume is mounted again. + + If unmount automatic transaction points are enabled, this function will + commit a transaction point prior to unmounting. If unmount automatic + transaction points are disabled, this function will unmount without + transacting, effectively discarding the working state. + + Before unmounting, this function will wait for any active file system + thread to complete by acquiring the FS mutex. The volume will be marked as + unmounted before the FS mutex is released, so subsequent FS threads will + possibly block and then see an error when attempting to access a volume + which is unmounting or unmounted. If the volume has open handles, the + unmount will fail. + + An error is returned if the volume is already unmounted. + + @param pszVolume A path prefix identifying the volume to unmount. + + @return On success, zero is returned. On error, -1 is returned and + #red_errno is set appropriately. + + Errno values + - #RED_EBUSY: There are still open handles for this file system volume. + - #RED_EINVAL: @p pszVolume is `NULL`; or the driver is uninitialized; or + the volume is already unmounted. + - #RED_EIO: I/O error during unmount automatic transaction point. + - #RED_ENOENT: @p pszVolume is not a valid volume path prefix. + - #RED_EUSERS: Cannot become a file system user: too many users. +*/ +int32_t red_umount( + const char *pszVolume) +{ + REDSTATUS ret; + + ret = PosixEnter(); + if(ret == 0) + { + uint8_t bVolNum; + + ret = RedPathSplit(pszVolume, &bVolNum, NULL); + + /* The core will return success if the volume is already unmounted, so + check for that condition here to propagate the error. + */ + if((ret == 0) && !gaRedVolume[bVolNum].fMounted) + { + ret = -RED_EINVAL; + } + + if(ret == 0) + { + uint16_t uHandleIdx; + + /* Do not unmount the volume if it still has open handles. + */ + for(uHandleIdx = 0U; uHandleIdx < REDCONF_HANDLE_COUNT; uHandleIdx++) + { + const REDHANDLE *pHandle = &gaHandle[uHandleIdx]; + + if((pHandle->ulInode != INODE_INVALID) && (pHandle->bVolNum == bVolNum)) + { + ret = -RED_EBUSY; + break; + } + } + } + + #if REDCONF_VOLUME_COUNT > 1U + if(ret == 0) + { + ret = RedCoreVolSetCurrent(bVolNum); + } + #endif + + if(ret == 0) + { + ret = RedCoreVolUnmount(); + } + + PosixLeave(); + } + + return PosixReturn(ret); +} + + +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX_FORMAT == 1) +/** @brief Format a file system volume. + + Uses the statically defined volume configuration. After calling this + function, the volume needs to be mounted -- see red_mount(). + + An error is returned if the volume is mounted. + + @param pszVolume A path prefix identifying the volume to format. + + @return On success, zero is returned. On error, -1 is returned and + #red_errno is set appropriately. + + Errno values + - #RED_EBUSY: Volume is mounted. + - #RED_EINVAL: @p pszVolume is `NULL`; or the driver is uninitialized. + - #RED_EIO: I/O error formatting the volume. + - #RED_ENOENT: @p pszVolume is not a valid volume path prefix. + - #RED_EUSERS: Cannot become a file system user: too many users. +*/ +int32_t red_format( + const char *pszVolume) +{ + REDSTATUS ret; + + ret = PosixEnter(); + if(ret == 0) + { + uint8_t bVolNum; + + ret = RedPathSplit(pszVolume, &bVolNum, NULL); + + #if REDCONF_VOLUME_COUNT > 1U + if(ret == 0) + { + ret = RedCoreVolSetCurrent(bVolNum); + } + #endif + + if(ret == 0) + { + ret = RedCoreVolFormat(); + } + + PosixLeave(); + } + + return PosixReturn(ret); +} +#endif + + +#if REDCONF_READ_ONLY == 0 +/** @brief Commit a transaction point. + + Reliance Edge is a transactional file system. All modifications, of both + metadata and filedata, are initially working state. A transaction point + is a process whereby the working state atomically becomes the committed + state, replacing the previous committed state. Whenever Reliance Edge is + mounted, including after power loss, the state of the file system after + mount is the most recent committed state. Nothing from the committed + state is ever missing, and nothing from the working state is ever included. + + @param pszVolume A path prefix identifying the volume to transact. + + @return On success, zero is returned. On error, -1 is returned and + #red_errno is set appropriately. + + Errno values + - #RED_EINVAL: Volume is not mounted; or @p pszVolume is `NULL`. + - #RED_EIO: I/O error during the transaction point. + - #RED_ENOENT: @p pszVolume is not a valid volume path prefix. + - #RED_EUSERS: Cannot become a file system user: too many users. +*/ +int32_t red_transact( + const char *pszVolume) +{ + REDSTATUS ret; + + ret = PosixEnter(); + if(ret == 0) + { + uint8_t bVolNum; + + ret = RedPathSplit(pszVolume, &bVolNum, NULL); + + #if REDCONF_VOLUME_COUNT > 1U + if(ret == 0) + { + ret = RedCoreVolSetCurrent(bVolNum); + } + #endif + + if(ret == 0) + { + ret = RedCoreVolTransact(); + } + + PosixLeave(); + } + + return PosixReturn(ret); +} +#endif + + +#if REDCONF_READ_ONLY == 0 +/** @brief Update the transaction mask. + + The following events are available: + + - #RED_TRANSACT_UMOUNT + - #RED_TRANSACT_CREAT + - #RED_TRANSACT_UNLINK + - #RED_TRANSACT_MKDIR + - #RED_TRANSACT_RENAME + - #RED_TRANSACT_LINK + - #RED_TRANSACT_CLOSE + - #RED_TRANSACT_WRITE + - #RED_TRANSACT_FSYNC + - #RED_TRANSACT_TRUNCATE + - #RED_TRANSACT_VOLFULL + + The #RED_TRANSACT_MANUAL macro (by itself) may be used to disable all + automatic transaction events. The #RED_TRANSACT_MASK macro is a bitmask + of all transaction flags, excluding those representing excluded + functionality. + + Attempting to enable events for excluded functionality will result in an + error. + + @param pszVolume The path prefix of the volume whose transaction mask is + being changed. + @param ulEventMask A bitwise-OR'd mask of automatic transaction events to + be set as the current transaction mode. + + @return On success, zero is returned. On error, -1 is returned and + #red_errno is set appropriately. + + Errno values + - #RED_EINVAL: Volume is not mounted; or @p pszVolume is `NULL`; or + @p ulEventMask contains invalid bits. + - #RED_ENOENT: @p pszVolume is not a valid volume path prefix. + - #RED_EUSERS: Cannot become a file system user: too many users. +*/ +int32_t red_settransmask( + const char *pszVolume, + uint32_t ulEventMask) +{ + REDSTATUS ret; + + ret = PosixEnter(); + if(ret == 0) + { + uint8_t bVolNum; + + ret = RedPathSplit(pszVolume, &bVolNum, NULL); + + #if REDCONF_VOLUME_COUNT > 1U + if(ret == 0) + { + ret = RedCoreVolSetCurrent(bVolNum); + } + #endif + + if(ret == 0) + { + ret = RedCoreTransMaskSet(ulEventMask); + } + + PosixLeave(); + } + + return PosixReturn(ret); +} +#endif + + +/** @brief Read the transaction mask. + + If the volume is read-only, the returned event mask is always zero. + + @param pszVolume The path prefix of the volume whose transaction mask is + being retrieved. + @param pulEventMask Populated with a bitwise-OR'd mask of automatic + transaction events which represent the current + transaction mode for the volume. + + @return On success, zero is returned. On error, -1 is returned and + #red_errno is set appropriately. + + Errno values + - #RED_EINVAL: Volume is not mounted; or @p pszVolume is `NULL`; or + @p pulEventMask is `NULL`. + - #RED_ENOENT: @p pszVolume is not a valid volume path prefix. + - #RED_EUSERS: Cannot become a file system user: too many users. +*/ +int32_t red_gettransmask( + const char *pszVolume, + uint32_t *pulEventMask) +{ + REDSTATUS ret; + + ret = PosixEnter(); + if(ret == 0) + { + uint8_t bVolNum; + + ret = RedPathSplit(pszVolume, &bVolNum, NULL); + + #if REDCONF_VOLUME_COUNT > 1U + if(ret == 0) + { + ret = RedCoreVolSetCurrent(bVolNum); + } + #endif + + if(ret == 0) + { + ret = RedCoreTransMaskGet(pulEventMask); + } + + PosixLeave(); + } + + return PosixReturn(ret); +} + + +/** @brief Query file system status information. + + @p pszVolume should name a valid volume prefix or a valid root directory; + this differs from POSIX statvfs, where any existing file or directory is a + valid path. + + @param pszVolume The path prefix of the volume to query. + @param pStatvfs The buffer to populate with volume information. + + @return On success, zero is returned. On error, -1 is returned and + #red_errno is set appropriately. + + Errno values + - #RED_EINVAL: Volume is not mounted; or @p pszVolume is `NULL`; or + @p pStatvfs is `NULL`. + - #RED_ENOENT: @p pszVolume is not a valid volume path prefix. + - #RED_EUSERS: Cannot become a file system user: too many users. +*/ +int32_t red_statvfs( + const char *pszVolume, + REDSTATFS *pStatvfs) +{ + REDSTATUS ret; + + ret = PosixEnter(); + if(ret == 0) + { + uint8_t bVolNum; + + ret = RedPathSplit(pszVolume, &bVolNum, NULL); + + #if REDCONF_VOLUME_COUNT > 1U + if(ret == 0) + { + ret = RedCoreVolSetCurrent(bVolNum); + } + #endif + + if(ret == 0) + { + ret = RedCoreVolStat(pStatvfs); + } + + PosixLeave(); + } + + return PosixReturn(ret); +} + + +/** @brief Open a file or directory. + + Exactly one file access mode must be specified: + + - #RED_O_RDONLY: Open for reading only. + - #RED_O_WRONLY: Open for writing only. + - #RED_O_RDWR: Open for reading and writing. + + Directories can only be opened with `RED_O_RDONLY`. + + The following flags may also be used: + + - #RED_O_APPEND: Set the file offset to the end-of-file prior to each + write. + - #RED_O_CREAT: Create the named file if it does not exist. + - #RED_O_EXCL: In combination with `RED_O_CREAT`, return an error if the + path already exists. + - #RED_O_TRUNC: Truncate the opened file to size zero. Only supported when + #REDCONF_API_POSIX_FTRUNCATE is true. + + #RED_O_CREAT, #RED_O_EXCL, and #RED_O_TRUNC are invalid with #RED_O_RDONLY. + #RED_O_EXCL is invalid without #RED_O_CREAT. + + If the volume is read-only, #RED_O_RDONLY is the only valid open flag; use + of any other flag will result in an error. + + If #RED_O_TRUNC frees data which is in the committed state, it will not + return to free space until after a transaction point. + + The returned file descriptor must later be closed with red_close(). + + Unlike POSIX open, there is no optional third argument for the permissions + (which Reliance Edge does not use) and other open flags (like `O_SYNC`) are + not supported. + + @param pszPath The path to the file or directory. + @param ulOpenMode The open flags (mask of `RED_O_` values). + + @return On success, a nonnegative file descriptor is returned. On error, + -1 is returned and #red_errno is set appropriately. + + Errno values + - #RED_EEXIST: Using #RED_O_CREAT and #RED_O_EXCL, and the indicated path + already exists. + - #RED_EINVAL: @p ulOpenMode is invalid; or @p pszPath is `NULL`; or the + volume containing the path is not mounted. + - #RED_EIO: A disk I/O error occurred. + - #RED_EISDIR: The path names a directory and @p ulOpenMode includes + #RED_O_WRONLY or #RED_O_RDWR. + - #RED_EMFILE: There are no available file descriptors. + - #RED_ENAMETOOLONG: The length of a component of @p pszPath is longer than + #REDCONF_NAME_MAX. + - #RED_ENFILE: Attempting to create a file but the file system has used all + available inode slots. + - #RED_ENOENT: #RED_O_CREAT is not set and the named file does not exist; or + #RED_O_CREAT is set and the parent directory does not exist; or the + volume does not exist; or the @p pszPath argument, after removing the + volume prefix, points to an empty string. + - #RED_ENOSPC: The file does not exist and #RED_O_CREAT was specified, but + there is insufficient free space to expand the directory or to create the + new file. + - #RED_ENOTDIR: A component of the prefix in @p pszPath does not name a + directory. + - #RED_EROFS: The path resides on a read-only file system and a write + operation was requested. + - #RED_EUSERS: Cannot become a file system user: too many users. +*/ +int32_t red_open( + const char *pszPath, + uint32_t ulOpenMode) +{ + int32_t iFildes = -1; /* Init'd to quiet warnings. */ + REDSTATUS ret; + + #if REDCONF_READ_ONLY == 1 + if(ulOpenMode != RED_O_RDONLY) + { + ret = -RED_EROFS; + } + #else + if( (ulOpenMode != (ulOpenMode & RED_O_MASK)) + || ((ulOpenMode & (RED_O_RDONLY|RED_O_WRONLY|RED_O_RDWR)) == 0U) + || (((ulOpenMode & RED_O_RDONLY) != 0U) && ((ulOpenMode & (RED_O_WRONLY|RED_O_RDWR)) != 0U)) + || (((ulOpenMode & RED_O_WRONLY) != 0U) && ((ulOpenMode & (RED_O_RDONLY|RED_O_RDWR)) != 0U)) + || (((ulOpenMode & RED_O_RDWR) != 0U) && ((ulOpenMode & (RED_O_RDONLY|RED_O_WRONLY)) != 0U)) + || (((ulOpenMode & (RED_O_TRUNC|RED_O_CREAT|RED_O_EXCL)) != 0U) && ((ulOpenMode & RED_O_RDONLY) != 0U)) + || (((ulOpenMode & RED_O_EXCL) != 0U) && ((ulOpenMode & RED_O_CREAT) == 0U))) + { + ret = -RED_EINVAL; + } + #if REDCONF_API_POSIX_FTRUNCATE == 0 + else if((ulOpenMode & RED_O_TRUNC) != 0U) + { + ret = -RED_EINVAL; + } + #endif + #endif + else + { + ret = PosixEnter(); + } + + if(ret == 0) + { + ret = FildesOpen(pszPath, ulOpenMode, FTYPE_EITHER, &iFildes); + + PosixLeave(); + } + + if(ret != 0) + { + iFildes = PosixReturn(ret); + } + + return iFildes; +} + + +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX_UNLINK == 1) +/** @brief Delete a file or directory. + + The given name is deleted and the link count of the corresponding inode is + decremented. If the link count falls to zero (no remaining hard links), + the inode will be deleted. + + Unlike POSIX unlink, deleting a file or directory with open handles (file + descriptors or directory streams) will fail with an #RED_EBUSY error. This + only applies when deleting an inode with a link count of one; if a file has + multiple names (hard links), all but the last name may be deleted even if + the file is open. + + If the path names a directory which is not empty, the unlink will fail. + + If the deletion frees data in the committed state, it will not return to + free space until after a transaction point. + + Unlike POSIX unlink, this function can fail when the disk is full. To fix + this, transact and try again: Reliance Edge guarantees that it is possible + to delete at least one file or directory after a transaction point. If disk + full automatic transactions are enabled, this will happen automatically. + + @param pszPath The path of the file or directory to delete. + + @return On success, zero is returned. On error, -1 is returned and + #red_errno is set appropriately. + + Errno values + - #RED_EBUSY: @p pszPath points to an inode with open handles and a link + count of one. + - #RED_EINVAL: @p pszPath is `NULL`; or the volume containing the path is + not mounted. + - #RED_EIO: A disk I/O error occurred. + - #RED_ENAMETOOLONG: The length of a component of @p pszPath is longer than + #REDCONF_NAME_MAX. + - #RED_ENOENT: The path does not name an existing file; or the @p pszPath + argument, after removing the volume prefix, points to an empty string. + - #RED_ENOTDIR: A component of the path prefix is not a directory. + - #RED_ENOTEMPTY: The path names a directory which is not empty. + - #RED_ENOSPC: The file system does not have enough space to modify the + parent directory to perform the deletion. + - #RED_EUSERS: Cannot become a file system user: too many users. +*/ +int32_t red_unlink( + const char *pszPath) +{ + REDSTATUS ret; + + ret = PosixEnter(); + if(ret == 0) + { + ret = UnlinkSub(pszPath, FTYPE_EITHER); + + PosixLeave(); + } + + return PosixReturn(ret); +} +#endif + + +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX_MKDIR == 1) +/** @brief Create a new directory. + + Unlike POSIX mkdir, this function has no second argument for the + permissions (which Reliance Edge does not use). + + @param pszPath The name and location of the directory to create. + + @return On success, zero is returned. On error, -1 is returned and + #red_errno is set appropriately. + + Errno values + - #RED_EEXIST: @p pszPath points to an existing file or directory. + - #RED_EINVAL: @p pszPath is `NULL`; or the volume containing the path is + not mounted. + - #RED_EIO: A disk I/O error occurred. + - #RED_ENAMETOOLONG: The length of a component of @p pszPath is longer than + #REDCONF_NAME_MAX. + - #RED_ENOENT: A component of the path prefix does not name an existing + directory; or the @p pszPath argument, after removing the volume prefix, + points to an empty string. + - #RED_ENOSPC: The file system does not have enough space for the new + directory or to extend the parent directory of the new directory. + - #RED_ENOTDIR: A component of the path prefix is not a directory. + - #RED_EROFS: The parent directory resides on a read-only file system. + - #RED_EUSERS: Cannot become a file system user: too many users. +*/ +int32_t red_mkdir( + const char *pszPath) +{ + REDSTATUS ret; + + ret = PosixEnter(); + if(ret == 0) + { + const char *pszLocalPath; + uint8_t bVolNum; + + ret = RedPathSplit(pszPath, &bVolNum, &pszLocalPath); + + #if REDCONF_VOLUME_COUNT > 1U + if(ret == 0) + { + ret = RedCoreVolSetCurrent(bVolNum); + } + #endif + + if(ret == 0) + { + const char *pszName; + uint32_t ulPInode; + + ret = RedPathToName(pszLocalPath, &ulPInode, &pszName); + + if(ret == 0) + { + uint32_t ulInode; + + ret = RedCoreCreate(ulPInode, pszName, true, &ulInode); + } + } + + PosixLeave(); + } + + return PosixReturn(ret); +} +#endif + + +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX_RMDIR == 1) +/** @brief Delete a directory. + + The given directory name is deleted and the corresponding directory inode + will be deleted. + + Unlike POSIX rmdir, deleting a directory with open handles (file + descriptors or directory streams) will fail with an #RED_EBUSY error. + + If the path names a directory which is not empty, the deletion will fail. + If the path names the root directory of a file system volume, the deletion + will fail. + + If the path names a regular file, the deletion will fail. This provides + type checking and may be useful in cases where an application knows the + path to be deleted should name a directory. + + If the deletion frees data in the committed state, it will not return to + free space until after a transaction point. + + Unlike POSIX rmdir, this function can fail when the disk is full. To fix + this, transact and try again: Reliance Edge guarantees that it is possible + to delete at least one file or directory after a transaction point. If disk + full automatic transactions are enabled, this will happen automatically. + + @param pszPath The path of the directory to delete. + + @return On success, zero is returned. On error, -1 is returned and + #red_errno is set appropriately. + + Errno values + - #RED_EBUSY: @p pszPath points to a directory with open handles. + - #RED_EINVAL: @p pszPath is `NULL`; or the volume containing the path is + not mounted. + - #RED_EIO: A disk I/O error occurred. + - #RED_ENAMETOOLONG: The length of a component of @p pszPath is longer than + #REDCONF_NAME_MAX. + - #RED_ENOENT: The path does not name an existing directory; or the + @p pszPath argument, after removing the volume prefix, points to an empty + string. + - #RED_ENOTDIR: A component of the path is not a directory. + - #RED_ENOTEMPTY: The path names a directory which is not empty. + - #RED_ENOSPC: The file system does not have enough space to modify the + parent directory to perform the deletion. + - #RED_EROFS: The directory to be removed resides on a read-only file + system. + - #RED_EUSERS: Cannot become a file system user: too many users. +*/ +int32_t red_rmdir( + const char *pszPath) +{ + REDSTATUS ret; + + ret = PosixEnter(); + if(ret == 0) + { + ret = UnlinkSub(pszPath, FTYPE_DIR); + + PosixLeave(); + } + + return PosixReturn(ret); +} +#endif + + +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX_RENAME == 1) +/** @brief Rename a file or directory. + + Both paths must reside on the same file system volume. Attempting to use + this API to move a file to a different volume will result in an error. + + If @p pszNewPath names an existing file or directory, the behavior depends + on the configuration. If #REDCONF_RENAME_ATOMIC is false, and if the + destination name exists, this function always fails and sets #red_errno to + #RED_EEXIST. This behavior is contrary to POSIX. + + If #REDCONF_RENAME_ATOMIC is true, and if the new name exists, then in one + atomic operation, @p pszNewPath is unlinked and @p pszOldPath is renamed to + @p pszNewPath. Both @p pszNewPath and @p pszOldPath must be of the same + type (both files or both directories). As with red_unlink(), if + @p pszNewPath is a directory, it must be empty. The major exception to this + behavior is that if both @p pszOldPath and @p pszNewPath are links to the + same inode, then the rename does nothing and both names continue to exist. + Unlike POSIX rename, if @p pszNewPath points to an inode with a link count + of one and open handles (file descriptors or directory streams), the + rename will fail with #RED_EBUSY. + + If the rename deletes the old destination, it may free data in the + committed state, which will not return to free space until after a + transaction point. Similarly, if the deleted inode was part of the + committed state, the inode slot will not be available until after a + transaction point. + + @param pszOldPath The path of the file or directory to rename. + @param pszNewPath The new name and location after the rename. + + @return On success, zero is returned. On error, -1 is returned and + #red_errno is set appropriately. + + Errno values + - #RED_EBUSY: #REDCONF_RENAME_ATOMIC is true and @p pszNewPath points to an + inode with open handles and a link count of one. + - #RED_EEXIST: #REDCONF_RENAME_ATOMIC is false and @p pszNewPath exists. + - #RED_EINVAL: @p pszOldPath is `NULL`; or @p pszNewPath is `NULL`; or the + volume containing the path is not mounted. + - #RED_EIO: A disk I/O error occurred. + - #RED_EISDIR: The @p pszNewPath argument names a directory and the + @p pszOldPath argument names a non-directory. + - #RED_ENAMETOOLONG: The length of a component of either @p pszOldPath or + @p pszNewPath is longer than #REDCONF_NAME_MAX. + - #RED_ENOENT: The link named by @p pszOldPath does not name an existing + entry; or either @p pszOldPath or @p pszNewPath, after removing the volume + prefix, point to an empty string. + - #RED_ENOTDIR: A component of either path prefix is not a directory; or + @p pszOldPath names a directory and @p pszNewPath names a file. + - #RED_ENOTEMPTY: The path named by @p pszNewPath is a directory which is + not empty. + - #RED_ENOSPC: The file system does not have enough space to extend the + directory that would contain @p pszNewPath. + - #RED_EROFS: The directory to be removed resides on a read-only file + system. + - #RED_EUSERS: Cannot become a file system user: too many users. + - #RED_EXDEV: @p pszOldPath and @p pszNewPath are on different file system + volumes. +*/ +int32_t red_rename( + const char *pszOldPath, + const char *pszNewPath) +{ + REDSTATUS ret; + + ret = PosixEnter(); + if(ret == 0) + { + const char *pszOldLocalPath; + uint8_t bOldVolNum; + + ret = RedPathSplit(pszOldPath, &bOldVolNum, &pszOldLocalPath); + + if(ret == 0) + { + const char *pszNewLocalPath; + uint8_t bNewVolNum; + + ret = RedPathSplit(pszNewPath, &bNewVolNum, &pszNewLocalPath); + + if((ret == 0) && (bOldVolNum != bNewVolNum)) + { + ret = -RED_EXDEV; + } + + #if REDCONF_VOLUME_COUNT > 1U + if(ret == 0) + { + ret = RedCoreVolSetCurrent(bOldVolNum); + } + #endif + + if(ret == 0) + { + const char *pszOldName; + uint32_t ulOldPInode; + + ret = RedPathToName(pszOldLocalPath, &ulOldPInode, &pszOldName); + + if(ret == 0) + { + const char *pszNewName; + uint32_t ulNewPInode; + + ret = RedPathToName(pszNewLocalPath, &ulNewPInode, &pszNewName); + + #if REDCONF_RENAME_ATOMIC == 1 + if(ret == 0) + { + uint32_t ulDestInode; + + ret = RedCoreLookup(ulNewPInode, pszNewName, &ulDestInode); + if(ret == 0) + { + ret = InodeUnlinkCheck(ulDestInode); + } + else if(ret == -RED_ENOENT) + { + ret = 0; + } + else + { + /* Unexpected error, nothing to do. + */ + } + } + #endif + + if(ret == 0) + { + ret = RedCoreRename(ulOldPInode, pszOldName, ulNewPInode, pszNewName); + } + } + } + } + + PosixLeave(); + } + + return PosixReturn(ret); +} +#endif + + +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX_LINK == 1) +/** @brief Create a hard link. + + This creates an additional name (link) for the file named by @p pszPath. + The new name refers to the same file with the same contents. If a name is + deleted, but the underlying file has other names, the file continues to + exist. The link count (accessible via red_fstat()) indicates the number of + names that a file has. All of a file's names are on equal footing: there + is nothing special about the original name. + + If @p pszPath names a directory, the operation will fail. + + @param pszPath The path indicating the inode for the new link. + @param pszHardLink The name and location for the new link. + + @return On success, zero is returned. On error, -1 is returned and + #red_errno is set appropriately. + + Errno values + - #RED_EEXIST: @p pszHardLink resolves to an existing file. + - #RED_EINVAL: @p pszPath or @p pszHardLink is `NULL`; or the volume + containing the paths is not mounted. + - #RED_EIO: A disk I/O error occurred. + - #RED_EMLINK: Creating the link would exceed the maximum link count of the + inode named by @p pszPath. + - #RED_ENAMETOOLONG: The length of a component of either @p pszPath or + @p pszHardLink is longer than #REDCONF_NAME_MAX. + - #RED_ENOENT: A component of either path prefix does not exist; or the file + named by @p pszPath does not exist; or either @p pszPath or + @p pszHardLink, after removing the volume prefix, point to an empty + string. + - #RED_ENOSPC: There is insufficient free space to expand the directory that + would contain the link. + - #RED_ENOTDIR: A component of either path prefix is not a directory. + - #RED_EPERM: The @p pszPath argument names a directory. + - #RED_EROFS: The requested link requires writing in a directory on a + read-only file system. + - #RED_EUSERS: Cannot become a file system user: too many users. + - #RED_EXDEV: @p pszPath and @p pszHardLink are on different file system + volumes. +*/ +int32_t red_link( + const char *pszPath, + const char *pszHardLink) +{ + REDSTATUS ret; + + ret = PosixEnter(); + if(ret == 0) + { + const char *pszLocalPath; + uint8_t bVolNum; + + ret = RedPathSplit(pszPath, &bVolNum, &pszLocalPath); + + if(ret == 0) + { + const char *pszLinkLocalPath; + uint8_t bLinkVolNum; + + ret = RedPathSplit(pszHardLink, &bLinkVolNum, &pszLinkLocalPath); + + if((ret == 0) && (bVolNum != bLinkVolNum)) + { + ret = -RED_EXDEV; + } + + #if REDCONF_VOLUME_COUNT > 1U + if(ret == 0) + { + ret = RedCoreVolSetCurrent(bVolNum); + } + #endif + + if(ret == 0) + { + uint32_t ulInode; + + ret = RedPathLookup(pszLocalPath, &ulInode); + + if(ret == 0) + { + const char *pszLinkName; + uint32_t ulLinkPInode; + + ret = RedPathToName(pszLinkLocalPath, &ulLinkPInode, &pszLinkName); + + if(ret == 0) + { + ret = RedCoreLink(ulLinkPInode, pszLinkName, ulInode); + } + } + } + } + + PosixLeave(); + } + + return PosixReturn(ret); +} +#endif + + +/** @brief Close a file descriptor. + + @param iFildes The file descriptor to close. + + @return On success, zero is returned. On error, -1 is returned and + #red_errno is set appropriately. + + Errno values + - #RED_EBADF: @p iFildes is not a valid file descriptor. + - #RED_EIO: A disk I/O error occurred. + - #RED_EUSERS: Cannot become a file system user: too many users. +*/ +int32_t red_close( + int32_t iFildes) +{ + REDSTATUS ret; + + ret = PosixEnter(); + if(ret == 0) + { + ret = FildesClose(iFildes); + + PosixLeave(); + } + + return PosixReturn(ret); +} + + +/** @brief Read from an open file. + + The read takes place at the file offset associated with @p iFildes and + advances the file offset by the number of bytes actually read. + + Data which has not yet been written, but which is before the end-of-file + (sparse data), will read as zeroes. A short read -- where the number of + bytes read is less than requested -- indicates that the requested read was + partially or, if zero bytes were read, entirely beyond the end-of-file. + + @param iFildes The file descriptor from which to read. + @param pBuffer The buffer to populate with data read. Must be at least + @p ulLength bytes in size. + @param ulLength Number of bytes to attempt to read. + + @return On success, returns a nonnegative value indicating the number of + bytes actually read. On error, -1 is returned and #red_errno is + set appropriately. + + Errno values + - #RED_EBADF: The @p iFildes argument is not a valid file descriptor open + for reading. + - #RED_EINVAL: @p pBuffer is `NULL`; or @p ulLength exceeds INT32_MAX and + cannot be returned properly. + - #RED_EIO: A disk I/O error occurred. + - #RED_EISDIR: The @p iFildes is a file descriptor for a directory. + - #RED_EUSERS: Cannot become a file system user: too many users. +*/ +int32_t red_read( + int32_t iFildes, + void *pBuffer, + uint32_t ulLength) +{ + uint32_t ulLenRead = 0U; + REDSTATUS ret; + int32_t iReturn; + + if(ulLength > (uint32_t)INT32_MAX) + { + ret = -RED_EINVAL; + } + else + { + ret = PosixEnter(); + } + + if(ret == 0) + { + REDHANDLE *pHandle; + + ret = FildesToHandle(iFildes, FTYPE_FILE, &pHandle); + + if((ret == 0) && ((pHandle->bFlags & HFLAG_READABLE) == 0U)) + { + ret = -RED_EBADF; + } + + #if REDCONF_VOLUME_COUNT > 1U + if(ret == 0) + { + ret = RedCoreVolSetCurrent(pHandle->bVolNum); + } + #endif + + if(ret == 0) + { + ulLenRead = ulLength; + ret = RedCoreFileRead(pHandle->ulInode, pHandle->ullOffset, &ulLenRead, pBuffer); + } + + if(ret == 0) + { + REDASSERT(ulLenRead <= ulLength); + + pHandle->ullOffset += ulLenRead; + } + + PosixLeave(); + } + + if(ret == 0) + { + iReturn = (int32_t)ulLenRead; + } + else + { + iReturn = PosixReturn(ret); + } + + return iReturn; +} + + +#if REDCONF_READ_ONLY == 0 +/** @brief Write to an open file. + + The write takes place at the file offset associated with @p iFildes and + advances the file offset by the number of bytes actually written. + Alternatively, if @p iFildes was opened with #RED_O_APPEND, the file offset + is set to the end-of-file before the write begins, and likewise advances by + the number of bytes actually written. + + A short write -- where the number of bytes written is less than requested + -- indicates either that the file system ran out of space but was still + able to write some of the request; or that the request would have caused + the file to exceed the maximum file size, but some of the data could be + written prior to the file size limit. + + If an error is returned (-1), either none of the data was written or a + critical error occurred (like an I/O error) and the file system volume will + be read-only. + + @param iFildes The file descriptor to write to. + @param pBuffer The buffer containing the data to be written. Must be at + least @p ulLength bytes in size. + @param ulLength Number of bytes to attempt to write. + + @return On success, returns a nonnegative value indicating the number of + bytes actually written. On error, -1 is returned and #red_errno is + set appropriately. + + Errno values + - #RED_EBADF: The @p iFildes argument is not a valid file descriptor open + for writing. This includes the case where the file descriptor is for a + directory. + - #RED_EFBIG: No data can be written to the current file offset since the + resulting file size would exceed the maximum file size. + - #RED_EINVAL: @p pBuffer is `NULL`; or @p ulLength exceeds INT32_MAX and + cannot be returned properly. + - #RED_EIO: A disk I/O error occurred. + - #RED_ENOSPC: No data can be written because there is insufficient free + space. + - #RED_EUSERS: Cannot become a file system user: too many users. +*/ +int32_t red_write( + int32_t iFildes, + const void *pBuffer, + uint32_t ulLength) +{ + uint32_t ulLenWrote = 0U; + REDSTATUS ret; + int32_t iReturn; + + if(ulLength > (uint32_t)INT32_MAX) + { + ret = -RED_EINVAL; + } + else + { + ret = PosixEnter(); + } + + if(ret == 0) + { + REDHANDLE *pHandle; + + ret = FildesToHandle(iFildes, FTYPE_FILE, &pHandle); + if(ret == -RED_EISDIR) + { + /* POSIX says that if a file descriptor is not writable, the + errno should be -RED_EBADF. Directory file descriptors are + never writable, and unlike for read(), the spec does not + list -RED_EISDIR as an allowed errno. Therefore -RED_EBADF + takes precedence. + */ + ret = -RED_EBADF; + } + + if((ret == 0) && ((pHandle->bFlags & HFLAG_WRITEABLE) == 0U)) + { + ret = -RED_EBADF; + } + + #if REDCONF_VOLUME_COUNT > 1U + if(ret == 0) + { + ret = RedCoreVolSetCurrent(pHandle->bVolNum); + } + #endif + + if((ret == 0) && ((pHandle->bFlags & HFLAG_APPENDING) != 0U)) + { + REDSTAT s; + + ret = RedCoreStat(pHandle->ulInode, &s); + if(ret == 0) + { + pHandle->ullOffset = s.st_size; + } + } + + if(ret == 0) + { + ulLenWrote = ulLength; + ret = RedCoreFileWrite(pHandle->ulInode, pHandle->ullOffset, &ulLenWrote, pBuffer); + } + + if(ret == 0) + { + REDASSERT(ulLenWrote <= ulLength); + + pHandle->ullOffset += ulLenWrote; + } + + PosixLeave(); + } + + if(ret == 0) + { + iReturn = (int32_t)ulLenWrote; + } + else + { + iReturn = PosixReturn(ret); + } + + return iReturn; +} +#endif + + +#if REDCONF_READ_ONLY == 0 +/** @brief Synchronizes changes to a file. + + Commits all changes associated with a file or directory (including file + data, directory contents, and metadata) to permanent storage. This + function will not return until the operation is complete. + + In the current implementation, this function has global effect. All dirty + buffers are flushed and a transaction point is committed. Fsyncing one + file effectively fsyncs all files. + + If fsync automatic transactions have been disabled, this function does + nothing and returns success. In the current implementation, this is the + only real difference between this function and red_transact(): this + function can be configured to do nothing, whereas red_transact() is + unconditional. + + Applications written for portability should avoid assuming red_fsync() + effects all files, and use red_fsync() on each file that needs to be + synchronized. + + Passing read-only file descriptors to this function is permitted. + + @param iFildes The file descriptor to synchronize. + + @return On success, zero is returned. On error, -1 is returned and + #red_errno is set appropriately. + + Errno values + - #RED_EBADF: The @p iFildes argument is not a valid file descriptor. + - #RED_EIO: A disk I/O error occurred. + - #RED_EUSERS: Cannot become a file system user: too many users. +*/ +int32_t red_fsync( + int32_t iFildes) +{ + REDSTATUS ret; + + ret = PosixEnter(); + if(ret == 0) + { + REDHANDLE *pHandle; + + ret = FildesToHandle(iFildes, FTYPE_EITHER, &pHandle); + + #if REDCONF_VOLUME_COUNT > 1U + if(ret == 0) + { + ret = RedCoreVolSetCurrent(pHandle->bVolNum); + } + #endif + + /* No core event for fsync, so this transaction flag needs to be + implemented here. + */ + if(ret == 0) + { + uint32_t ulTransMask; + + ret = RedCoreTransMaskGet(&ulTransMask); + + if((ret == 0) && ((ulTransMask & RED_TRANSACT_FSYNC) != 0U)) + { + ret = RedCoreVolTransact(); + } + } + + PosixLeave(); + } + + return PosixReturn(ret); +} +#endif + + +/** @brief Move the read/write file offset. + + The file offset of the @p iFildes file descriptor is set to @p llOffset, + relative to some starting position. The available positions are: + + - ::RED_SEEK_SET Seek from the start of the file. In other words, + @p llOffset becomes the new file offset. + - ::RED_SEEK_CUR Seek from the current file offset. In other words, + @p llOffset is added to the current file offset. + - ::RED_SEEK_END Seek from the end-of-file. In other words, the new file + offset is the file size plus @p llOffset. + + Since @p llOffset is signed (can be negative), it is possible to seek + backward with ::RED_SEEK_CUR or ::RED_SEEK_END. + + It is permitted to seek beyond the end-of-file; this does not increase the + file size (a subsequent red_write() call would). + + Unlike POSIX lseek, this function cannot be used with directory file + descriptors. + + @param iFildes The file descriptor whose offset is to be updated. + @param llOffset The new file offset, relative to @p whence. + @param whence The location from which @p llOffset should be applied. + + @return On success, returns the new file position, measured in bytes from + the beginning of the file. On error, -1 is returned and #red_errno + is set appropriately. + + Errno values + - #RED_EBADF: The @p iFildes argument is not an open file descriptor. + - #RED_EINVAL: @p whence is not a valid `RED_SEEK_` value; or the resulting + file offset would be negative or beyond the maximum file size. + - #RED_EIO: A disk I/O error occurred. + - #RED_EISDIR: The @p iFildes argument is a file descriptor for a directory. + - #RED_EUSERS: Cannot become a file system user: too many users. +*/ +int64_t red_lseek( + int32_t iFildes, + int64_t llOffset, + REDWHENCE whence) +{ + REDSTATUS ret; + int64_t llReturn = -1; /* Init'd to quiet warnings. */ + + ret = PosixEnter(); + if(ret == 0) + { + int64_t llFrom = 0; /* Init'd to quiet warnings. */ + REDHANDLE *pHandle; + + /* Unlike POSIX, we disallow lseek() on directory handles. + */ + ret = FildesToHandle(iFildes, FTYPE_FILE, &pHandle); + + #if REDCONF_VOLUME_COUNT > 1U + if(ret == 0) + { + ret = RedCoreVolSetCurrent(pHandle->bVolNum); + } + #endif + + if(ret == 0) + { + switch(whence) + { + /* Seek from the beginning of the file. + */ + case RED_SEEK_SET: + llFrom = 0; + break; + + /* Seek from the current file offset. + */ + case RED_SEEK_CUR: + REDASSERT(pHandle->ullOffset <= (uint64_t)INT64_MAX); + llFrom = (int64_t)pHandle->ullOffset; + break; + + /* Seek from the end of the file. + */ + case RED_SEEK_END: + { + REDSTAT s; + + ret = RedCoreStat(pHandle->ulInode, &s); + if(ret == 0) + { + REDASSERT(s.st_size <= (uint64_t)INT64_MAX); + llFrom = (int64_t)s.st_size; + } + + break; + } + + default: + ret = -RED_EINVAL; + break; + } + } + + if(ret == 0) + { + REDASSERT(llFrom >= 0); + + /* Avoid signed integer overflow from llFrom + llOffset with large + values of llOffset and nonzero llFrom values. Underflow isn't + possible since llFrom is nonnegative. + */ + if((llOffset > 0) && (((uint64_t)llFrom + (uint64_t)llOffset) > (uint64_t)INT64_MAX)) + { + ret = -RED_EINVAL; + } + else + { + int64_t llNewOffset = llFrom + llOffset; + + if((llNewOffset < 0) || ((uint64_t)llNewOffset > gpRedVolume->ullMaxInodeSize)) + { + /* Invalid file offset. + */ + ret = -RED_EINVAL; + } + else + { + pHandle->ullOffset = (uint64_t)llNewOffset; + llReturn = llNewOffset; + } + } + } + + PosixLeave(); + } + + if(ret != 0) + { + llReturn = PosixReturn(ret); + } + + return llReturn; +} + + +#if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX_FTRUNCATE == 1) +/** @brief Truncate a file to a specified length. + + Allows the file size to be increased, decreased, or to remain the same. If + the file size is increased, the new area is sparse (will read as zeroes). + If the file size is decreased, the data beyond the new end-of-file will + return to free space once it is no longer part of the committed state + (either immediately or after the next transaction point). + + The value of the file offset is not modified by this function. + + Unlike POSIX ftruncate, this function can fail when the disk is full if + @p ullSize is non-zero. If decreasing the file size, this can be fixed by + transacting and trying again: Reliance Edge guarantees that it is possible + to perform a truncate of at least one file that decreases the file size + after a transaction point. If disk full transactions are enabled, this will + happen automatically. + + @param iFildes The file descriptor of the file to truncate. + @param ullSize The new size of the file. + + @return On success, zero is returned. On error, -1 is returned and + #red_errno is set appropriately. + + Errno values + - #RED_EBADF: The @p iFildes argument is not a valid file descriptor open + for writing. This includes the case where the file descriptor is for a + directory. + - #RED_EFBIG: @p ullSize exceeds the maximum file size. + - #RED_EIO: A disk I/O error occurred. + - #RED_ENOSPC: Insufficient free space to perform the truncate. + - #RED_EUSERS: Cannot become a file system user: too many users. +*/ +int32_t red_ftruncate( + int32_t iFildes, + uint64_t ullSize) +{ + REDSTATUS ret; + + ret = PosixEnter(); + if(ret == 0) + { + REDHANDLE *pHandle; + + ret = FildesToHandle(iFildes, FTYPE_FILE, &pHandle); + if(ret == -RED_EISDIR) + { + /* Similar to red_write() (see comment there), the RED_EBADF error + for a non-writable file descriptor takes precedence. + */ + ret = -RED_EBADF; + } + + if((ret == 0) && ((pHandle->bFlags & HFLAG_WRITEABLE) == 0U)) + { + ret = -RED_EBADF; + } + + #if REDCONF_VOLUME_COUNT > 1U + if(ret == 0) + { + ret = RedCoreVolSetCurrent(pHandle->bVolNum); + } + #endif + + if(ret == 0) + { + ret = RedCoreFileTruncate(pHandle->ulInode, ullSize); + } + + PosixLeave(); + } + + return PosixReturn(ret); +} +#endif + + +/** @brief Get the status of a file or directory. + + See the ::REDSTAT type for the details of the information returned. + + @param iFildes An open file descriptor for the file whose information is + to be retrieved. + @param pStat Pointer to a ::REDSTAT buffer to populate. + + @return On success, zero is returned. On error, -1 is returned and + #red_errno is set appropriately. + + Errno values + - #RED_EBADF: The @p iFildes argument is not a valid file descriptor. + - #RED_EINVAL: @p pStat is `NULL`. + - #RED_EIO: A disk I/O error occurred. + - #RED_EUSERS: Cannot become a file system user: too many users. +*/ +int32_t red_fstat( + int32_t iFildes, + REDSTAT *pStat) +{ + REDSTATUS ret; + + ret = PosixEnter(); + if(ret == 0) + { + REDHANDLE *pHandle; + + ret = FildesToHandle(iFildes, FTYPE_EITHER, &pHandle); + + #if REDCONF_VOLUME_COUNT > 1U + if(ret == 0) + { + ret = RedCoreVolSetCurrent(pHandle->bVolNum); + } + #endif + + if(ret == 0) + { + ret = RedCoreStat(pHandle->ulInode, pStat); + } + + PosixLeave(); + } + + return PosixReturn(ret); +} + + +#if REDCONF_API_POSIX_READDIR == 1 +/** @brief Open a directory stream for reading. + + @param pszPath The path of the directory to open. + + @return On success, returns a pointer to a ::REDDIR object that can be used + with red_readdir() and red_closedir(). On error, returns `NULL` + and #red_errno is set appropriately. + + Errno values + - #RED_EINVAL: @p pszPath is `NULL`; or the volume containing the path is + not mounted. + - #RED_EIO: A disk I/O error occurred. + - #RED_ENOENT: A component of @p pszPath does not exist; or the @p pszPath + argument, after removing the volume prefix, points to an empty string. + - #RED_ENOTDIR: A component of @p pszPath is a not a directory. + - #RED_EMFILE: There are no available file descriptors. + - #RED_EUSERS: Cannot become a file system user: too many users. +*/ +REDDIR *red_opendir( + const char *pszPath) +{ + int32_t iFildes; + REDSTATUS ret; + REDDIR *pDir = NULL; + + ret = PosixEnter(); + if(ret == 0) + { + ret = FildesOpen(pszPath, RED_O_RDONLY, FTYPE_DIR, &iFildes); + if(ret == 0) + { + uint16_t uHandleIdx; + + FildesUnpack(iFildes, &uHandleIdx, NULL, NULL); + pDir = &gaHandle[uHandleIdx]; + } + + PosixLeave(); + } + + REDASSERT((pDir == NULL) == (ret != 0)); + + if(pDir == NULL) + { + red_errno = -ret; + } + + return pDir; +} + + +/** @brief Read from a directory stream. + + The ::REDDIRENT pointer returned by this function will be overwritten by + subsequent calls on the same @p pDir. Calls with other ::REDDIR objects + will *not* modify the returned ::REDDIRENT. + + If files are added to the directory after it is opened, the new files may + or may not be returned by this function. If files are deleted, the deleted + files will not be returned. + + This function (like its POSIX equivalent) returns `NULL` in two cases: on + error and when the end of the directory is reached. To distinguish between + these two cases, the application should set #red_errno to zero before + calling this function, and if `NULL` is returned, check if #red_errno is + still zero. If it is, the end of the directory was reached; otherwise, + there was an error. + + @param pDirStream The directory stream to read from. + + @return On success, returns a pointer to a ::REDDIRENT object which is + populated with directory entry information read from the directory. + On error, returns `NULL` and #red_errno is set appropriately. If at + the end of the directory, returns `NULL` but #red_errno is not + modified. + + Errno values + - #RED_EBADF: @p pDirStream is not an open directory stream. + - #RED_EIO: A disk I/O error occurred. + - #RED_EUSERS: Cannot become a file system user: too many users. +*/ +REDDIRENT *red_readdir( + REDDIR *pDirStream) +{ + REDSTATUS ret; + REDDIRENT *pDirEnt = NULL; + + ret = PosixEnter(); + if(ret == 0) + { + if(!DirStreamIsValid(pDirStream)) + { + ret = -RED_EBADF; + } + #if REDCONF_VOLUME_COUNT > 1U + else + { + ret = RedCoreVolSetCurrent(pDirStream->bVolNum); + } + #endif + + if(ret == 0) + { + uint32_t ulDirPosition; + + /* To save memory, the directory position is stored in the same + location as the file offset. This would be a bit cleaner using + a union, but MISRA-C:2012 Rule 19.2 disallows unions. + */ + REDASSERT(pDirStream->ullOffset <= UINT32_MAX); + ulDirPosition = (uint32_t)pDirStream->ullOffset; + + ret = RedCoreDirRead(pDirStream->ulInode, &ulDirPosition, pDirStream->dirent.d_name, &pDirStream->dirent.d_ino); + + pDirStream->ullOffset = ulDirPosition; + + if(ret == 0) + { + /* POSIX extension: return stat information with the dirent. + */ + ret = RedCoreStat(pDirStream->dirent.d_ino, &pDirStream->dirent.d_stat); + if(ret == 0) + { + pDirEnt = &pDirStream->dirent; + } + } + else if(ret == -RED_ENOENT) + { + /* Reached the end of the directory; return NULL but do not set + errno. + */ + ret = 0; + } + else + { + /* Miscellaneous error; return NULL and set errno (done below). + */ + } + } + + PosixLeave(); + } + + if(ret != 0) + { + REDASSERT(pDirEnt == NULL); + + red_errno = -ret; + } + + return pDirEnt; +} + + +/** @brief Rewind a directory stream to read it from the beginning. + + Similar to closing the directory object and opening it again, but without + the need for the path. + + Since this function (like its POSIX equivalent) cannot return an error, + it takes no action in error conditions, such as when @p pDirStream is + invalid. + + @param pDirStream The directory stream to rewind. +*/ +void red_rewinddir( + REDDIR *pDirStream) +{ + if(PosixEnter() == 0) + { + if(DirStreamIsValid(pDirStream)) + { + pDirStream->ullOffset = 0U; + } + + PosixLeave(); + } +} + + +/** @brief Close a directory stream. + + After calling this function, @p pDirStream should no longer be used. + + @param pDirStream The directory stream to close. + + @return On success, zero is returned. On error, -1 is returned and + #red_errno is set appropriately. + + Errno values + - #RED_EBADF: @p pDirStream is not an open directory stream. + - #RED_EUSERS: Cannot become a file system user: too many users. +*/ +int32_t red_closedir( + REDDIR *pDirStream) +{ + REDSTATUS ret; + + ret = PosixEnter(); + if(ret == 0) + { + if(DirStreamIsValid(pDirStream)) + { + /* Mark this handle as unused. + */ + pDirStream->ulInode = INODE_INVALID; + } + else + { + ret = -RED_EBADF; + } + + PosixLeave(); + } + + return PosixReturn(ret); +} +#endif /* REDCONF_API_POSIX_READDIR */ + + +/** @brief Pointer to where the last file system error (errno) is stored. + + This function is intended to be used via the #red_errno macro, or a similar + user-defined macro, that can be used both as an lvalue (writable) and an + rvalue (readable). + + Under normal circumstances, the errno for each task is stored in a + different location. Applications do not need to worry about one task + obliterating an error value that another task needed to read. This task + errno for is initially zero. When one of the POSIX-like APIs returns an + indication of error, the location for the calling task will be populated + with the error value. + + In some circumstances, this function will return a pointer to a global + errno location which is shared by multiple tasks. If the calling task is + not registered as a file system user and all of the task slots are full, + there can be no task-specific errno, so the global pointer is returned. + Likewise, if the file system driver is uninitialized, there are no + registered file system users and this function always returns the pointer + to the global errno. Under these circumstances, multiple tasks + manipulating errno could be problematic. + + This function never returns `NULL` under any circumstances. The #red_errno + macro unconditionally dereferences the return value from this function, so + returning `NULL` could result in a fault. + + @return Pointer to where the errno value is stored for this task. +*/ +REDSTATUS *red_errnoptr(void) +{ + /* The global errno value, used in single-task configurations and when the + caller is not (and cannot become) a file system user (which includes + when the driver is uninitialized). + */ + static REDSTATUS iGlobalErrno = 0; + + #if REDCONF_TASK_COUNT == 1U + + return &iGlobalErrno; + + #else + + REDSTATUS *piErrno; + + if(gfPosixInited) + { + uint32_t ulTaskId = RedOsTaskId(); + uint32_t ulIdx; + + REDASSERT(ulTaskId != 0U); + + /* If this task has used the file system before, it will already have + a task slot, which includes the task-specific errno. + */ + RedOsMutexAcquire(); + + for(ulIdx = 0U; ulIdx < REDCONF_TASK_COUNT; ulIdx++) + { + if(gaTask[ulIdx].ulTaskId == ulTaskId) + { + break; + } + } + + RedOsMutexRelease(); + + if(ulIdx == REDCONF_TASK_COUNT) + { + REDSTATUS ret; + + /* This task is not a file system user, so try to register it as + one. This FS mutex must be held in order to register. + */ + RedOsMutexAcquire(); + + ret = TaskRegister(&ulIdx); + + RedOsMutexRelease(); + + if(ret == 0) + { + REDASSERT(gaTask[ulIdx].ulTaskId == RedOsTaskId()); + REDASSERT(gaTask[ulIdx].iErrno == 0); + + piErrno = &gaTask[ulIdx].iErrno; + } + else + { + /* Unable to register; use the global errno. + */ + piErrno = &iGlobalErrno; + } + } + else + { + piErrno = &gaTask[ulIdx].iErrno; + } + } + else + { + /* There are no registered file system tasks when the driver is + uninitialized, so use the global errno. + */ + piErrno = &iGlobalErrno; + } + + /* This function is not allowed to return NULL. + */ + REDASSERT(piErrno != NULL); + return piErrno; + + #endif +} +/** @} */ + +/*------------------------------------------------------------------- + Helper Functions +-------------------------------------------------------------------*/ + +#if (REDCONF_READ_ONLY == 0) && ((REDCONF_API_POSIX_UNLINK == 1) || (REDCONF_API_POSIX_RMDIR == 1)) + +/** @brief Remove a link to a file or directory. + + If the link count becomes zero, the file or directory is deleted. + + @param pszPath Path of the link to remove. + @param type The expected type of the path: file, directory, or either. + An error is returned if the expected type is file or + directory and does not match the path. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval -RED_EBUSY @p pszPath points to an inode with open handles + and a link count of one. + @retval -RED_EINVAL @p pszPath is `NULL`; or the volume containing + the path is not mounted. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_EISDIR @p type is ::FTYPE_FILE and the path names a + directory. + @retval -RED_ENAMETOOLONG @p pszName is too long. + @retval -RED_ENOENT The path does not name an existing file; or + @p pszPath, after removing the volume prefix, + points to an empty string. + @retval -RED_ENOTDIR @p type is ::FTYPE_DIR and the path does not + name a directory. + @retval -RED_ENOTEMPTY @p pszPath is a directory which is not empty. + @retval -RED_ENOSPC The file system does not have enough space to + modify the parent directory to perform the + deletion. +*/ +static REDSTATUS UnlinkSub( + const char *pszPath, + FTYPE type) +{ + uint8_t bVolNum; + const char *pszLocalPath; + REDSTATUS ret; + + ret = RedPathSplit(pszPath, &bVolNum, &pszLocalPath); + + #if REDCONF_VOLUME_COUNT > 1U + if(ret == 0) + { + ret = RedCoreVolSetCurrent(bVolNum); + } + #endif + + if(ret == 0) + { + const char *pszName; + uint32_t ulPInode; + + ret = RedPathToName(pszLocalPath, &ulPInode, &pszName); + + if(ret == 0) + { + uint32_t ulInode; + + ret = RedCoreLookup(ulPInode, pszName, &ulInode); + + /* ModeTypeCheck() always passes when the type is FTYPE_EITHER, so + skip stat'ing the inode in that case. + */ + if((ret == 0) && (type != FTYPE_EITHER)) + { + REDSTAT InodeStat; + + ret = RedCoreStat(ulInode, &InodeStat); + if(ret == 0) + { + ret = ModeTypeCheck(InodeStat.st_mode, type); + } + } + + if(ret == 0) + { + ret = InodeUnlinkCheck(ulInode); + } + + if(ret == 0) + { + ret = RedCoreUnlink(ulPInode, pszName); + } + } + } + + return ret; +} +#endif /* (REDCONF_API_POSIX_UNLINK == 1) || (REDCONF_API_POSIX_RMDIR == 1) */ + + +/** @brief Get a file descriptor for a path. + + @param pszPath Path to a file to open. + @param ulOpenMode The RED_O_* flags the descriptor is opened with. + @param type Indicates the expected descriptor type: file, directory, + or either. + @param piFildes On successful return, populated with the file + descriptor. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL @p piFildes is `NULL`; or @p pszPath is `NULL`; + or the volume is not mounted. + @retval -RED_EMFILE There are no available handles. + @retval -RED_EEXIST Using #RED_O_CREAT and #RED_O_EXCL, and the + indicated path already exists. + @retval -RED_EISDIR The path names a directory and @p ulOpenMode + includes #RED_O_WRONLY or #RED_O_RDWR. + @retval -RED_ENOENT #RED_O_CREAT is not set and the named file does + not exist; or #RED_O_CREAT is set and the parent + directory does not exist; or the volume does not + exist; or the @p pszPath argument, after + removing the volume prefix, points to an empty + string. + @retval -RED_EIO A disk I/O error occurred. + @retval -RED_ENAMETOOLONG The length of a component of @p pszPath is + longer than #REDCONF_NAME_MAX. + @retval -RED_ENFILE Attempting to create a file but the file system + has used all available inode slots. + @retval -RED_ENOSPC The file does not exist and #RED_O_CREAT was + specified, but there is insufficient free space + to expand the directory or to create the new + file. + @retval -RED_ENOTDIR A component of the prefix in @p pszPath does not + name a directory. + @retval -RED_EROFS The path resides on a read-only file system and + a write operation was requested. +*/ +static REDSTATUS FildesOpen( + const char *pszPath, + uint32_t ulOpenMode, + FTYPE type, + int32_t *piFildes) +{ + uint8_t bVolNum; + const char *pszLocalPath; + REDSTATUS ret; + + ret = RedPathSplit(pszPath, &bVolNum, &pszLocalPath); + + if(ret == 0) + { + if(piFildes == NULL) + { + ret = -RED_EINVAL; + } + #if REDCONF_READ_ONLY == 0 + else if(gaRedVolume[bVolNum].fReadOnly && (ulOpenMode != RED_O_RDONLY)) + { + ret = -RED_EROFS; + } + #endif + else + { + uint16_t uHandleIdx; + REDHANDLE *pHandle = NULL; + + /* Search for an unused handle. + */ + for(uHandleIdx = 0U; uHandleIdx < REDCONF_HANDLE_COUNT; uHandleIdx++) + { + if(gaHandle[uHandleIdx].ulInode == INODE_INVALID) + { + pHandle = &gaHandle[uHandleIdx]; + break; + } + } + + /* Error if all the handles are in use. + */ + if(pHandle == NULL) + { + ret = -RED_EMFILE; + } + else + { + bool fCreated = false; + uint16_t uMode = 0U; + uint32_t ulInode = 0U; /* Init'd to quiet warnings. */ + + #if REDCONF_VOLUME_COUNT > 1U + ret = RedCoreVolSetCurrent(bVolNum); + if(ret == 0) + #endif + { + #if REDCONF_READ_ONLY == 0 + if((ulOpenMode & RED_O_CREAT) != 0U) + { + uint32_t ulPInode; + const char *pszName; + + ret = RedPathToName(pszLocalPath, &ulPInode, &pszName); + if(ret == 0) + { + ret = RedCoreCreate(ulPInode, pszName, false, &ulInode); + if(ret == 0) + { + fCreated = true; + } + else if((ret == -RED_EEXIST) && ((ulOpenMode & RED_O_EXCL) == 0U)) + { + /* If the path already exists and that's OK, + lookup its inode number. + */ + ret = RedCoreLookup(ulPInode, pszName, &ulInode); + } + else + { + /* No action, just propagate the error. + */ + } + } + } + else + #endif + { + ret = RedPathLookup(pszLocalPath, &ulInode); + } + } + + /* If we created the inode, none of the below stuff is + necessary. This is important from an error handling + perspective -- we do not need code to delete the created + inode on error. + */ + if(!fCreated) + { + if(ret == 0) + { + REDSTAT s; + + ret = RedCoreStat(ulInode, &s); + if(ret == 0) + { + uMode = s.st_mode; + } + } + + /* Error if the inode is not of the expected type. + */ + if(ret == 0) + { + ret = ModeTypeCheck(uMode, type); + } + + /* Directories must always be opened with O_RDONLY. + */ + if((ret == 0) && RED_S_ISDIR(uMode) && ((ulOpenMode & RED_O_RDONLY) == 0U)) + { + ret = -RED_EISDIR; + } + + #if (REDCONF_READ_ONLY == 0) && (REDCONF_API_POSIX_FTRUNCATE == 1) + if((ret == 0) && ((ulOpenMode & RED_O_TRUNC) != 0U)) + { + ret = RedCoreFileTruncate(ulInode, UINT64_SUFFIX(0)); + } + #endif + } + + if(ret == 0) + { + int32_t iFildes; + + RedMemSet(pHandle, 0U, sizeof(*pHandle)); + + /* Populate this handle, marking it as in use. + */ + pHandle->ulInode = ulInode; + pHandle->bVolNum = bVolNum; + + if(RED_S_ISDIR(uMode)) + { + pHandle->bFlags |= HFLAG_DIRECTORY; + } + + if(((ulOpenMode & RED_O_RDONLY) != 0U) || ((ulOpenMode & RED_O_RDWR) != 0U)) + { + pHandle->bFlags |= HFLAG_READABLE; + } + + #if REDCONF_READ_ONLY == 0 + if(((ulOpenMode & RED_O_WRONLY) != 0U) || ((ulOpenMode & RED_O_RDWR) != 0U)) + { + pHandle->bFlags |= HFLAG_WRITEABLE; + } + + if((ulOpenMode & RED_O_APPEND) != 0U) + { + pHandle->bFlags |= HFLAG_APPENDING; + } + #endif + + iFildes = FildesPack(uHandleIdx, bVolNum); + if(iFildes == -1) + { + /* It should be impossible to get here, unless there + is memory corruption. + */ + REDERROR(); + ret = -RED_EFUBAR; + } + else + { + *piFildes = iFildes; + } + } + } + } + } + + return ret; +} + + +/** @brief Close a file descriptor. + + @param iFildes The file descriptor to close. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBADF @p iFildes is not a valid file descriptor. + @retval -RED_EIO A disk I/O error occurred. +*/ +static REDSTATUS FildesClose( + int32_t iFildes) +{ + REDHANDLE *pHandle; + REDSTATUS ret; + + ret = FildesToHandle(iFildes, FTYPE_EITHER, &pHandle); + + #if REDCONF_READ_ONLY == 0 + #if REDCONF_VOLUME_COUNT > 1U + if(ret == 0) + { + ret = RedCoreVolSetCurrent(pHandle->bVolNum); + } + #endif + + /* No core event for close, so this transaction flag needs to be + implemented here. + */ + if(ret == 0) + { + uint32_t ulTransMask; + + ret = RedCoreTransMaskGet(&ulTransMask); + + if((ret == 0) && ((ulTransMask & RED_TRANSACT_CLOSE) != 0U)) + { + ret = RedCoreVolTransact(); + } + } + #endif + + if(ret == 0) + { + /* Mark this handle as unused. + */ + pHandle->ulInode = INODE_INVALID; + } + + return ret; +} + + +/** @brief Convert a file descriptor into a handle pointer. + + Also validates the file descriptor. + + @param iFildes The file descriptor for which to get a handle. + @param expectedType The expected type of the file descriptor: ::FTYPE_DIR, + ::FTYPE_FILE, or ::FTYPE_EITHER. + @param ppHandle On successful return, populated with a pointer to the + handle associated with @p iFildes. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBADF @p iFildes is not a valid file descriptor. + @retval -RED_EINVAL @p ppHandle is `NULL`. + @retval -RED_EISDIR Expected a file, but the file descriptor is for a + directory. + @retval -RED_ENOTDIR Expected a directory, but the file descriptor is for + a file. +*/ +static REDSTATUS FildesToHandle( + int32_t iFildes, + FTYPE expectedType, + REDHANDLE **ppHandle) +{ + REDSTATUS ret; + + if(ppHandle == NULL) + { + REDERROR(); + ret = -RED_EINVAL; + } + else if(iFildes < FD_MIN) + { + ret = -RED_EBADF; + } + else + { + uint16_t uHandleIdx; + uint8_t bVolNum; + uint16_t uGeneration; + + FildesUnpack(iFildes, &uHandleIdx, &bVolNum, &uGeneration); + + if( (uHandleIdx >= REDCONF_HANDLE_COUNT) + || (bVolNum >= REDCONF_VOLUME_COUNT) + || (gaHandle[uHandleIdx].ulInode == INODE_INVALID) + || (gaHandle[uHandleIdx].bVolNum != bVolNum) + || (gauGeneration[bVolNum] != uGeneration)) + { + ret = -RED_EBADF; + } + else if((expectedType == FTYPE_FILE) && ((gaHandle[uHandleIdx].bFlags & HFLAG_DIRECTORY) != 0U)) + { + ret = -RED_EISDIR; + } + else if((expectedType == FTYPE_DIR) && ((gaHandle[uHandleIdx].bFlags & HFLAG_DIRECTORY) == 0U)) + { + ret = -RED_ENOTDIR; + } + else + { + *ppHandle = &gaHandle[uHandleIdx]; + ret = 0; + } + } + + return ret; +} + + +/** @brief Pack a file descriptor. + + @param uHandleIdx The index of the file handle that will be associated + with this file descriptor. + @param bVolNum The volume which contains the file or directory this + file descriptor was opened against. + + @return The packed file descriptor. +*/ +static int32_t FildesPack( + uint16_t uHandleIdx, + uint8_t bVolNum) +{ + int32_t iFildes; + + if((uHandleIdx >= REDCONF_HANDLE_COUNT) || (bVolNum >= REDCONF_VOLUME_COUNT)) + { + REDERROR(); + iFildes = -1; + } + else + { + uint32_t ulFdBits; + + REDASSERT(gauGeneration[bVolNum] <= FD_GEN_MAX); + REDASSERT(gauGeneration[bVolNum] != 0U); + + ulFdBits = gauGeneration[bVolNum]; + ulFdBits <<= FD_VOL_BITS; + ulFdBits |= bVolNum; + ulFdBits <<= FD_IDX_BITS; + ulFdBits |= uHandleIdx; + + iFildes = (int32_t)ulFdBits; + + if(iFildes < FD_MIN) + { + REDERROR(); + iFildes = -1; + } + } + + return iFildes; +} + + +/** @brief Unpack a file descriptor. + + @param iFildes The file descriptor to unpack. + @param puHandleIdx If non-NULL, populated with the handle index extracted + from the file descriptor. + @param pbVolNum If non-NULL, populated with the volume number extracted + from the file descriptor. + @param puGeneration If non-NULL, populated with the generation number + extracted from the file descriptor. +*/ +static void FildesUnpack( + int32_t iFildes, + uint16_t *puHandleIdx, + uint8_t *pbVolNum, + uint16_t *puGeneration) +{ + uint32_t ulFdBits = (uint32_t)iFildes; + + REDASSERT(iFildes >= FD_MIN); + + if(puHandleIdx != NULL) + { + *puHandleIdx = (uint16_t)(ulFdBits & FD_IDX_MAX); + } + + ulFdBits >>= FD_IDX_BITS; + + if(pbVolNum != NULL) + { + *pbVolNum = (uint8_t)(ulFdBits & FD_VOL_MAX); + } + + ulFdBits >>= FD_VOL_BITS; + + if(puGeneration != NULL) + { + *puGeneration = (uint16_t)(ulFdBits & FD_GEN_MAX); + } +} + + +#if REDCONF_API_POSIX_READDIR == 1 +/** @brief Validate a directory stream object. + + @param pDirStream The directory stream to validate. + + @return Whether the directory stream is valid. + + @retval true The directory stream object appears valid. + @retval false The directory stream object is invalid. +*/ +static bool DirStreamIsValid( + const REDDIR *pDirStream) +{ + bool fRet = true; + + if(pDirStream == NULL) + { + fRet = false; + } + else + { + uint16_t uHandleIdx; + + /* pDirStream should be a pointer to one of the handles. + + A good compiler will optimize this loop into a bounds check and an + alignment check. + */ + for(uHandleIdx = 0U; uHandleIdx < REDCONF_HANDLE_COUNT; uHandleIdx++) + { + if(pDirStream == &gaHandle[uHandleIdx]) + { + break; + } + } + + if(uHandleIdx < REDCONF_HANDLE_COUNT) + { + /* The handle must be in use, have a valid volume number, and be a + directory handle. + */ + if( (pDirStream->ulInode == INODE_INVALID) + || (pDirStream->bVolNum >= REDCONF_VOLUME_COUNT) + || ((pDirStream->bFlags & HFLAG_DIRECTORY) == 0U)) + { + fRet = false; + } + } + else + { + /* pDirStream is a non-null pointer, but it is not a pointer to one + of our handles. + */ + fRet = false; + } + } + + return fRet; +} +#endif + + +/** @brief Enter the file system driver. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EINVAL The file system driver is uninitialized. + @retval -RED_EUSERS Cannot become a file system user: too many users. +*/ +static REDSTATUS PosixEnter(void) +{ + REDSTATUS ret; + + if(gfPosixInited) + { + #if REDCONF_TASK_COUNT > 1U + RedOsMutexAcquire(); + + ret = TaskRegister(NULL); + if(ret != 0) + { + RedOsMutexRelease(); + } + #else + ret = 0; + #endif + } + else + { + ret = -RED_EINVAL; + } + + return ret; +} + + +/** @brief Leave the file system driver. +*/ +static void PosixLeave(void) +{ + /* If the driver was uninitialized, PosixEnter() should have failed and we + should not be calling PosixLeave(). + */ + REDASSERT(gfPosixInited); + + #if REDCONF_TASK_COUNT > 1U + RedOsMutexRelease(); + #endif +} + + +/** @brief Check that a mode is consistent with the given expected type. + + @param uMode An inode mode, indicating whether the inode is a file + or a directory. + @param expectedType The expected type: ::FTYPE_FILE, ::FTYPE_DIR, or + ::FTYPE_EITHER. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EISDIR Expected type is file, actual type is directory. + @retval -RED_ENOTDIR Expected type is directory, actual type is file. +*/ +static REDSTATUS ModeTypeCheck( + uint16_t uMode, + FTYPE expectedType) +{ + REDSTATUS ret; + + if((expectedType == FTYPE_FILE) && RED_S_ISDIR(uMode)) + { + /* Expected file, found directory. + */ + ret = -RED_EISDIR; + } + else if((expectedType == FTYPE_DIR) && RED_S_ISREG(uMode)) + { + /* Expected directory, found file. + */ + ret = -RED_ENOTDIR; + } + else + { + /* No expected type or found what we expected. + */ + ret = 0; + } + + return ret; +} + + +#if (REDCONF_READ_ONLY == 0) && ((REDCONF_API_POSIX_UNLINK == 1) || (REDCONF_API_POSIX_RMDIR == 1) || ((REDCONF_API_POSIX_RENAME == 1) && (REDCONF_RENAME_ATOMIC == 1))) +/** @brief Check whether an inode can be unlinked. + + If an inode has a link count of 1 (meaning unlinking another name would + result in the deletion of the inode) and open handles, it cannot be deleted + since this would break open handles. + + @param ulInode The inode whose name is to be unlinked. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EBADF @p ulInode is not a valid inode. + @retval -RED_EBUSY The inode has a link count of one and open handles. + @retval -RED_EIO A disk I/O error occurred. +*/ +static REDSTATUS InodeUnlinkCheck( + uint32_t ulInode) +{ + uint16_t uHandleIdx; + REDSTATUS ret; + + #if REDCONF_API_POSIX_LINK == 0 + ret = 0; + #else + REDSTAT InodeStat; + + ret = RedCoreStat(ulInode, &InodeStat); + + /* We only need to check for open handles if the inode is down to its last + link. If it has multiple links, the inode will continue to exist, so + deleting the name will not break the open handles. + */ + if((ret == 0) && (InodeStat.st_nlink == 1U)) + #endif + { + for(uHandleIdx = 0U; uHandleIdx < REDCONF_HANDLE_COUNT; uHandleIdx++) + { + if((gaHandle[uHandleIdx].ulInode == ulInode) && (gaHandle[uHandleIdx].bVolNum == gbRedVolNum)) + { + ret = -RED_EBUSY; + break; + } + } + } + + return ret; +} +#endif + + +#if REDCONF_TASK_COUNT > 1U +/** @brief Register a task as a file system user, if it is not already + registered as one. + + The caller must hold the FS mutex. + + @param pulTaskIdx On successful return, if non-NULL, populated with the + index of the task slot assigned to the calling task. + This is populated whether or not the task had already + been registered. + + @return A negated ::REDSTATUS code indicating the operation result. + + @retval 0 Operation was successful. + @retval -RED_EUSERS Cannot become a file system user: too many users. +*/ +static REDSTATUS TaskRegister( + uint32_t *pulTaskIdx) +{ + uint32_t ulTaskId = RedOsTaskId(); + uint32_t ulFirstFreeIdx = REDCONF_TASK_COUNT; + uint32_t ulIdx; + REDSTATUS ret; + + REDASSERT(ulTaskId != 0U); + + /* Scan the task slots to determine if the task is registered as a file + system task. + */ + for(ulIdx = 0U; ulIdx < REDCONF_TASK_COUNT; ulIdx++) + { + if(gaTask[ulIdx].ulTaskId == ulTaskId) + { + break; + } + + if((ulFirstFreeIdx == REDCONF_TASK_COUNT) && (gaTask[ulIdx].ulTaskId == 0U)) + { + ulFirstFreeIdx = ulIdx; + } + } + + if(ulIdx == REDCONF_TASK_COUNT) + { + /* Task not already registered. + */ + if(ulFirstFreeIdx == REDCONF_TASK_COUNT) + { + /* Cannot register task, no more slots. + */ + ret = -RED_EUSERS; + } + else + { + /* Registering task. + */ + ulIdx = ulFirstFreeIdx; + gaTask[ulIdx].ulTaskId = ulTaskId; + ret = 0; + } + } + else + { + /* Task already registered. + */ + ret = 0; + } + + if((ret == 0) && (pulTaskIdx != NULL)) + { + *pulTaskIdx = ulIdx; + } + + return ret; +} +#endif /* REDCONF_TASK_COUNT > 1U */ + + +/** @brief Convert an error value into a simple 0 or -1 return. + + This function is simple, but what it does is needed in many places. It + returns zero if @p iError is zero (meaning success) or it returns -1 if + @p iError is nonzero (meaning error). Also, if @p iError is nonzero, it + is saved in red_errno. + + @param iError The error value. + + @return Returns 0 if @p iError is 0; otherwise, returns -1. +*/ +static int32_t PosixReturn( + REDSTATUS iError) +{ + int32_t iReturn; + + if(iError == 0) + { + iReturn = 0; + } + else + { + iReturn = -1; + + /* The errors should be negative, and errno positive. + */ + REDASSERT(iError < 0); + red_errno = -iError; + } + + return iReturn; +} + + +#endif /* REDCONF_API_POSIX == 1 */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/tests/posix/fsstress.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/tests/posix/fsstress.c new file mode 100644 index 0000000..abc2aa9 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/tests/posix/fsstress.c @@ -0,0 +1,2050 @@ +/* + * Copyright (c) 2000 Silicon Graphics, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it would be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * Further, this software is distributed without any warranty that it is + * free of the rightful claim of any third person regarding infringement + * or the like. Any license provided herein, whether implied or + * otherwise, applies only to this software file. Patent licenses, if + * any, provided herein do not apply to combinations of this program with + * other software, or any other product whatsoever. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, + * Mountain View, CA 94043, or: + * + * http://www.sgi.com + * + * For further information regarding this notice, see: + * + * http://oss.sgi.com/projects/GenInfo/SGIGPLNoticeExplan/ + */ +/** @file + @brief File system stress test. + + This version of SGI fsstress has been modified to be single-threaded and to + work with the Reliance Edge POSIX-like API. +*/ +#include +#include +#include +#include +#include +#include + +#include +#include + +#if FSSTRESS_SUPPORTED + +#include "redposixcompat.h" + +#include +#include +#include +#include +#include +#include + +#if REDCONF_CHECKER == 1 +#include +#endif + + +/* Create POSIX types. Use #define to avoid name conflicts in those + environments where the type names already exist. +*/ +#define off_t int64_t +#define off64_t off_t +#define ino_t uint32_t +#define mode_t uint16_t +#define __int64_t int64_t + + +/** @brief Generate a random number. + + @return A nonnegative random number. +*/ +#define random() ((int)(RedRand32(NULL) & 0x7FFFFFFF)) + + +/** @brief Seed the random number generator. +*/ +#define srandom(seed) RedRandSeed(seed) + + +#define _exit(status) exit(status) +#define getpagesize() 4096U +#define getpid() 1 + + +/** @brief Determine the maximum file size. + + This is used for the MAXFSSIZE macro. +*/ +static uint64_t MaxFileSize(void) +{ + REDSTATFS info; + int32_t iStatus; + REDSTATUS errnoSave = errno; + uint64_t ullMaxFileSize; + + iStatus = red_statvfs("", &info); + if(iStatus == 0) + { + ullMaxFileSize = info.f_maxfsize; + } + else + { + /* This function does not change errno. + */ + errno = errnoSave; + + ullMaxFileSize = 0x7FFFFFFFU; + } + + return ullMaxFileSize; +} + + +/*------------------------------------------------------------------- + Simulated current working directory support +-------------------------------------------------------------------*/ + + +/* Forward declaration for red_chdir(). +*/ +static int red_stat(const char *pszPath, REDSTAT *pStat); + +/* The simulated CWD functions. +*/ +#undef chdir +#undef getcwd +#define chdir(path) red_chdir(path) +#define getcwd(buf, size) red_getcwd(buf, size) + + +/* Redefine the path-based APIs to call MakeFullPath() on their arguments + since there is no CWD support in the red_*() APIs. +*/ +#undef open +#undef unlink +#undef mkdir +#undef rmdir +#undef rename +#undef link +#undef opendir +#define open(path, oflag) red_open(MakeFullPath(path), oflag) +#define unlink(path) red_unlink(MakeFullPath(path)) +#define mkdir(path) red_mkdir(MakeFullPath(path)) +#define rmdir(path) red_rmdir(MakeFullPath(path)) +#define rename(old, new) red_rename(MakeFullPath(old), MakeFullPath(new)) +#define link(path, hardlink) red_link(MakeFullPath(path), MakeFullPath(hardlink)) +#define opendir(path) red_opendir(MakeFullPath(path)) + +#define FSSTRESS_BUF_SIZE 1024U + +/* Stores the simulated current working directory. +*/ +static char szLocalCwd[FSSTRESS_BUF_SIZE] = "/"; + + +/** @brief Change the current working directory. + + This function only supports a subset of what is possible with POSIX chdir(). + + @param pszPath The new current working directory. + + @return Upon successful completion, 0 shall be returned. Otherwise, -1 + shall be returned, and errno shall be set to indicate the error. +*/ +static int red_chdir( + const char *pszPath) +{ + uint32_t ulIdx; + int iErrno = 0; + + if(strcmp(pszPath, "..") == 0) + { + uint32_t ulLastSlashIdx = 0U; + + /* Chop off the last path separator and everything after it, so that + "/foo/bar/baz" becomes "/foo/bar", moving the CWD up one directory. + */ + for(ulIdx = 0U; szLocalCwd[ulIdx] != '\0'; ulIdx++) + { + if(szLocalCwd[ulIdx] == '/') + { + ulLastSlashIdx = ulIdx; + } + } + + if(ulLastSlashIdx != 0U) + { + szLocalCwd[ulLastSlashIdx] = '\0'; + } + } + else + { + char szOldCwd[FSSTRESS_BUF_SIZE]; + + /* chdir() must have no effect on the CWD if it fails, so save the CWD + so we can revert it if necessary. + */ + strcpy(szOldCwd, szLocalCwd); + + if(pszPath[0U] == '/') + { + if(strlen(pszPath) >= sizeof(szLocalCwd)) + { + iErrno = RED_ENAMETOOLONG; + } + else + { + strcpy(szLocalCwd, pszPath); + } + } + else + { + ulIdx = strlen(szLocalCwd); + + if((ulIdx + 1U + strlen(pszPath)) >= sizeof(szLocalCwd)) + { + iErrno = RED_ENAMETOOLONG; + } + else + { + if(szLocalCwd[1U] != '\0') + { + szLocalCwd[ulIdx] = '/'; + ulIdx++; + } + + strcpy(&szLocalCwd[ulIdx], pszPath); + } + } + + if(iErrno == 0) + { + REDSTAT s; + int iStatus; + + iStatus = red_stat(szLocalCwd, &s); + if(iStatus != 0) + { + iErrno = errno; + } + else if(!S_ISDIR(s.st_mode)) + { + iErrno = RED_ENOTDIR; + } + else + { + /* No error, new CWD checks out. + */ + } + } + + if(iErrno != 0) + { + strcpy(szLocalCwd, szOldCwd); + } + } + + if(iErrno != 0) + { + errno = iErrno; + } + + return iErrno == 0 ? 0 : -1; +} + + +/** @brief Retrieve the current working directory. + + @param pszBuf On successful return, populated with the current working + directory. If NULL, memory will be allocated for the CWD + and returned by this function. + @param nSize The size of @p pszBuf. + + @return On success, if @p pszBuf was non-NULL, returns @p pszBuf; if + @p pszBuf was NULL, returns an allocated buffer populated with the + CWD which must be freed by the caller. On failure, returns NULL + and errno will be set. +*/ +static char *red_getcwd( + char *pszBuf, + size_t nSize) +{ + char *pszRet; + + if(pszBuf == NULL) + { + pszRet = malloc(strlen(szLocalCwd) + 1U); + if(pszRet == NULL) + { + errno = RED_ENOMEM; + } + else + { + strcpy(pszRet, szLocalCwd); + } + } + else if(nSize < strlen(szLocalCwd) + 1U) + { + errno = RED_ERANGE; + pszRet = NULL; + } + else + { + strcpy(pszBuf, szLocalCwd); + pszRet = pszBuf; + } + + return pszRet; +} + + +/** @brief Make a relative path into a fully qualified path. + + @param pszName The relative path. + + @return On success, a pointer to a fully qualified path. On error, NULL. +*/ +static const char *MakeFullPath( + const char *pszName) +{ + #define MAXVOLNAME 64U /* Enough for most configs. */ + static char aszFullPath[2U][MAXVOLNAME + 1U + FSSTRESS_BUF_SIZE]; + static uint32_t ulWhich = 0U; + + char *pszFullPath = aszFullPath[ulWhich]; + const char *pszVolume = gpRedVolConf->pszPathPrefix; + int32_t iLen; + + if(pszName[0U] == '/') + { + iLen = RedSNPrintf(pszFullPath, sizeof(aszFullPath[0U]), "%s%s", pszVolume, pszName); + } + else if(strcmp(pszName, ".") == 0U) + { + iLen = RedSNPrintf(pszFullPath, sizeof(aszFullPath[0U]), "%s%s", pszVolume, szLocalCwd); + } + else if((szLocalCwd[0U] == '/') && (szLocalCwd[1U] == '\0')) + { + iLen = RedSNPrintf(pszFullPath, sizeof(aszFullPath[0U]), "%s/%s", pszVolume, pszName); + } + else + { + iLen = RedSNPrintf(pszFullPath, sizeof(aszFullPath[0U]), "%s%s/%s", pszVolume, szLocalCwd, pszName); + } + + if(iLen == -1) + { + /* Insufficient path buffer space. + */ + pszFullPath = NULL; + } + else + { + /* Toggle between two full path arrays; a kluge to make rename() and + link() work correctly. + */ + ulWhich ^= 1U; + } + + return pszFullPath; +} + + +/*------------------------------------------------------------------- + POSIX functions not implemented by the RED POSIX-like API +-------------------------------------------------------------------*/ + +#define stat(p, s) red_stat(p, s) +#define stat64(p, s) stat(p, s) +#define lstat(p, s) stat(p, s) +#define lstat64(p, s) stat(p, s) +#define truncate(p, s) red_truncate(p, s) +#define truncate64(p, s) truncate(p, s) + + +/** @brief Get the status of a file or directory. +*/ +static int red_stat( + const char *pszPath, + REDSTAT *pStat) +{ + int iFd; + int iRet; + + iFd = open(pszPath, O_RDONLY); + iRet = iFd; + if(iFd != -1) + { + iRet = fstat(iFd, pStat); + + (void)close(iFd); + } + + return iRet; +} + + +/** @brief Truncate a file to a specified length. +*/ +static int red_truncate( + const char *pszPath, + off_t llSize) +{ + int iFd; + int iRet; + + iFd = open(pszPath, O_WRONLY); + iRet = iFd; + if(iFd != -1) + { + iRet = ftruncate(iFd, llSize); + + (void)close(iFd); + } + + return iRet; +} + + +/*------------------------------------------------------------------- + Begin ported fsstress code +-------------------------------------------------------------------*/ + +/* Stuff from xfscompat.h */ + +#define MAXNAMELEN (REDCONF_NAME_MAX+1U) /* Assumed to include NUL */ + +struct dioattr { + int d_miniosz, d_maxiosz, d_mem; +}; + +#define MIN(a,b) ((a)<(b) ? (a):(b)) +#define MAX(a,b) ((a)>(b) ? (a):(b)) + +/* End xfscompat.h */ + + +typedef enum { + OP_CREAT, + OP_FDATASYNC, + OP_FSYNC, + OP_GETDENTS, + OP_LINK, + OP_MKDIR, + OP_READ, + OP_RENAME, + OP_RMDIR, + OP_STAT, + OP_TRUNCATE, + OP_UNLINK, + OP_WRITE, + #if REDCONF_CHECKER == 1 + OP_CHECK, + #endif + OP_LAST +} opty_t; + +typedef void (*opfnc_t) (int, long); + +typedef struct opdesc { + opty_t op; + const char *name; + opfnc_t func; + int freq; + int iswrite; +} opdesc_t; + +typedef struct fent { + int id; + int parent; +} fent_t; + +typedef struct flist { + int nfiles; + int nslots; + int tag; + fent_t *fents; +} flist_t; + +typedef struct pathname { + int len; + char *path; +} pathname_t; + +#define FT_DIR 0 +#define FT_DIRm (1 << FT_DIR) +#define FT_REG 1 +#define FT_REGm (1 << FT_REG) +#define FT_SYM 2 +#define FT_SYMm (1 << FT_SYM) +#define FT_DEV 3 +#define FT_DEVm (1 << FT_DEV) +#define FT_RTF 4 +#define FT_RTFm (1 << FT_RTF) +#define FT_nft 5 +#define FT_ANYm ((1 << FT_nft) - 1) +#define FT_REGFILE (FT_REGm | FT_RTFm) +#define FT_NOTDIR (FT_ANYm & ~FT_DIRm) + +#define FLIST_SLOT_INCR 16 +#define NDCACHE 64 + +#define MAXFSIZE MaxFileSize() + +static void creat_f(int opno, long r); +static void fdatasync_f(int opno, long r); +static void fsync_f(int opno, long r); +static void getdents_f(int opno, long r); +static void link_f(int opno, long r); +static void mkdir_f(int opno, long r); +static void read_f(int opno, long r); +static void rename_f(int opno, long r); +static void rmdir_f(int opno, long r); +static void stat_f(int opno, long r); +static void truncate_f(int opno, long r); +static void unlink_f(int opno, long r); +static void write_f(int opno, long r); +#if REDCONF_CHECKER == 1 +static void check_f(int opno, long r); +#endif + +static opdesc_t ops[] = { + {OP_CREAT, "creat", creat_f, 4, 1}, + {OP_FDATASYNC, "fdatasync", fdatasync_f, 1, 1}, + {OP_FSYNC, "fsync", fsync_f, 1, 1}, + {OP_GETDENTS, "getdents", getdents_f, 1, 0}, + {OP_LINK, "link", link_f, 1, 1}, + {OP_MKDIR, "mkdir", mkdir_f, 2, 1}, + {OP_READ, "read", read_f, 1, 0}, + {OP_RENAME, "rename", rename_f, 2, 1}, + {OP_RMDIR, "rmdir", rmdir_f, 1, 1}, + {OP_STAT, "stat", stat_f, 1, 0}, + {OP_TRUNCATE, "truncate", truncate_f, 2, 1}, + {OP_UNLINK, "unlink", unlink_f, 1, 1}, + {OP_WRITE, "write", write_f, 4, 1}, + #if REDCONF_CHECKER == 1 + {OP_CHECK, "check", check_f, 1, 1}, + #endif +}, *ops_end; + +static flist_t flist[FT_nft] = { + {0, 0, 'd', NULL}, + {0, 0, 'f', NULL}, + {0, 0, 'l', NULL}, + {0, 0, 'c', NULL}, + {0, 0, 'r', NULL}, +}; + +static int dcache[NDCACHE]; +static opty_t *freq_table; +static int freq_table_size; +static char *homedir; +static int *ilist; +static int ilistlen; +static off64_t maxfsize; +static int namerand; +static int nameseq; +static int nops; +static int operations = 1; +static int procid; +static int rtpct; +static unsigned long seed = 0; +static ino_t top_ino; +static int verbose = 0; + +static int delete_tree(const char *path); +static void add_to_flist(int fd, int it, int parent); +static void append_pathname(pathname_t *name, const char *str); +static void check_cwd(void); +static int creat_path(pathname_t *name, mode_t mode); +static void dcache_enter(int dirid, int slot); +static void dcache_init(void); +static fent_t *dcache_lookup(int dirid); +static void dcache_purge(int dirid); +static void del_from_flist(int ft, int slot); +static void doproc(void); +static void fent_to_name(pathname_t *name, flist_t *flp, fent_t *fep); +static void fix_parent(int oldid, int newid); +static void free_pathname(pathname_t *name); +static int generate_fname(fent_t *fep, int ft, pathname_t *name, int *idp, int *v); +static int get_fname(int which, long r, pathname_t *name, flist_t **flpp, fent_t **fepp, int *v); +static void init_pathname(pathname_t *name); +static int link_path(pathname_t *name1, pathname_t *name2); +static int lstat64_path(pathname_t *name, REDSTAT *sbuf); +static void make_freq_table(void); +static int mkdir_path(pathname_t *name, mode_t mode); +static void namerandpad(int id, char *buf, int len); +static int open_path(pathname_t *name, int oflag); +static DIR *opendir_path(pathname_t *name); +static int rename_path(pathname_t *name1, pathname_t *name2); +static int rmdir_path(pathname_t *name); +static void separate_pathname(pathname_t *name, char *buf, pathname_t *newname); +static int stat64_path(pathname_t *name, REDSTAT *sbuf); +static int truncate64_path(pathname_t *name, off64_t length); +static int unlink_path(pathname_t *name); +static void usage(const char *progname); + + +/** @brief Parse parameters for fsstress. + + @param argc The number of arguments from main(). + @param argv The vector of arguments from main(). + @param pParam Populated with the fsstress parameters. + @param pbVolNum If non-NULL, populated with the volume number. + @param ppszDevice If non-NULL, populated with the device name argument or + NULL if no device argument is provided. + + @return The result of parsing the parameters. +*/ +PARAMSTATUS FsstressParseParams( + int argc, + char *argv[], + FSSTRESSPARAM *pParam, + uint8_t *pbVolNum, + const char **ppszDevice) +{ + int c; + uint8_t bVolNum; + const REDOPTION aLongopts[] = + { + { "no-cleanup", red_no_argument, NULL, 'c' }, + { "loops", red_required_argument, NULL, 'l' }, + { "nops", red_required_argument, NULL, 'n' }, + { "namepad", red_no_argument, NULL, 'r' }, + { "seed", red_required_argument, NULL, 's' }, + { "verbose", red_no_argument, NULL, 'v' }, + { "dev", red_required_argument, NULL, 'D' }, + { "help", red_no_argument, NULL, 'H' }, + { NULL } + }; + + /* If run without parameters, treat as a help request. + */ + if(argc <= 1) + { + goto Help; + } + + /* Assume no device argument to start with. + */ + if(ppszDevice != NULL) + { + *ppszDevice = NULL; + } + + /* Set default parameters. + */ + FsstressDefaultParams(pParam); + + while((c = RedGetoptLong(argc, argv, "cl:n:rs:vD:H", aLongopts, NULL)) != -1) + { + switch(c) + { + case 'c': /* --no-cleanup */ + pParam->fNoCleanup = true; + break; + case 'l': /* --loops */ + pParam->ulLoops = RedAtoI(red_optarg); + break; + case 'n': /* --nops */ + pParam->ulNops = RedAtoI(red_optarg); + break; + case 'r': /* --namepad */ + pParam->fNamePad = true; + break; + case 's': /* --seed */ + pParam->ulSeed = RedAtoI(red_optarg); + break; + case 'v': /* --verbose */ + pParam->fVerbose = true; + break; + case 'D': /* --dev */ + if(ppszDevice != NULL) + { + *ppszDevice = red_optarg; + } + break; + case 'H': /* --help */ + goto Help; + case '?': /* Unknown or ambiguous option */ + case ':': /* Option missing required argument */ + default: + goto BadOpt; + } + } + + /* RedGetoptLong() has permuted argv to move all non-option arguments to + the end. We expect to find a volume identifier. + */ + if(red_optind >= argc) + { + RedPrintf("Missing volume argument\n"); + goto BadOpt; + } + + bVolNum = RedFindVolumeNumber(argv[red_optind]); + if(bVolNum == REDCONF_VOLUME_COUNT) + { + RedPrintf("Error: \"%s\" is not a valid volume identifier.\n", argv[red_optind]); + goto BadOpt; + } + + if(pbVolNum != NULL) + { + *pbVolNum = bVolNum; + } + + red_optind++; /* Move past volume parameter. */ + if(red_optind < argc) + { + int32_t ii; + + for(ii = red_optind; ii < argc; ii++) + { + RedPrintf("Error: Unexpected command-line argument \"%s\".\n", argv[ii]); + } + + goto BadOpt; + } + + return PARAMSTATUS_OK; + + BadOpt: + + RedPrintf("%s - invalid parameters\n", argv[0U]); + usage(argv[0U]); + return PARAMSTATUS_BAD; + + Help: + + usage(argv[0U]); + return PARAMSTATUS_HELP; +} + + +/** @brief Set default fsstress parameters. + + @param pParam Populated with the default fsstress parameters. +*/ +void FsstressDefaultParams( + FSSTRESSPARAM *pParam) +{ + RedMemSet(pParam, 0U, sizeof(*pParam)); + pParam->ulLoops = 1U; + pParam->ulNops = 10000U; +} + + +/** @brief Start fsstress. + + @param pParam fsstress parameters, either from FsstressParseParams() or + constructed programatically. + + @return Zero on success, otherwise nonzero. +*/ +int FsstressStart( + const FSSTRESSPARAM *pParam) +{ + char buf[10]; + int fd; + int i; + int cleanup; + int loops; + int loopcntr = 1; + + nops = sizeof(ops) / sizeof(ops[0]); + ops_end = &ops[nops]; + + /* Copy the already-parsed parameters into the traditional variables. + */ + cleanup = pParam->fNoCleanup ? 1 : 0; + loops = pParam->ulLoops; + operations = pParam->ulNops; + namerand = pParam->fNamePad ? 1 : 0; + seed = pParam->ulSeed; + verbose = pParam->fVerbose ? 1 : 0; + + make_freq_table(); + + while ((loopcntr <= loops) || (loops == 0)) { + RedSNPrintf(buf, sizeof(buf), "fss%x", getpid()); + fd = creat(buf, 0666); + maxfsize = (off64_t) MAXFSIZE; + dcache_init(); + if (!seed) { + seed = (unsigned long)RedOsClockGetTime(); + RedPrintf("seed = %ld\n", seed); + } + close(fd); + unlink(buf); + procid = 0; + doproc(); + if (cleanup == 0) { + delete_tree("/"); + for (i = 0; i < FT_nft; i++) { + flist[i].nslots = 0; + flist[i].nfiles = 0; + free(flist[i].fents); + flist[i].fents = NULL; + } + } + loopcntr++; + } + return 0; +} + +static int delete_tree(const char *path) +{ + REDSTAT sb; + DIR *dp; + REDDIRENT *dep; + char *childpath; + size_t len; + int e; + + e = stat(path, &sb); + if (e) + return errno; + + if (!S_ISDIR(sb.st_mode)) + return unlink(path) ? errno : 0; + + dp = opendir(path); + if (dp == NULL) + return errno; + + while((dep = readdir(dp)) != NULL) { + len = strlen(path) + 1 + strlen(dep->d_name) + 1; + childpath = malloc(len); + + strcpy(childpath, path); + if (childpath[strlen(childpath) - 1] != '/') + strcat(childpath, "/"); + strcat(childpath, dep->d_name); + + e = delete_tree(childpath); + + free(childpath); + + if (e) + break; + } + + if (e == 0 && strcmp(path, "/") != 0) { + e = rmdir(path) ? errno : 0; + } + closedir(dp); + return e; +} + +static void add_to_flist(int ft, int id, int parent) +{ + fent_t *fep; + flist_t *ftp; + + ftp = &flist[ft]; + if (ftp->nfiles == ftp->nslots) { + ftp->nslots += FLIST_SLOT_INCR; + ftp->fents = realloc(ftp->fents, ftp->nslots * sizeof(fent_t)); + } + fep = &ftp->fents[ftp->nfiles++]; + fep->id = id; + fep->parent = parent; +} + +static void append_pathname(pathname_t *name, const char *str) +{ + int len; + + len = strlen(str); +#ifdef DEBUG + if (len && *str == '/' && name->len == 0) { + RedPrintf("fsstress: append_pathname failure\n"); + chdir(homedir); + abort(); + + } +#endif + name->path = realloc(name->path, name->len + 1 + len); + strcpy(&name->path[name->len], str); + name->len += len; +} + +static void check_cwd(void) +{ +#ifdef DEBUG + REDSTAT statbuf; + + if (stat64(".", &statbuf) == 0 && statbuf.st_ino == top_ino) + return; + chdir(homedir); + RedPrintf("fsstress: check_cwd failure\n"); + abort(); + +#endif +} + +static int creat_path(pathname_t *name, mode_t mode) +{ + char buf[MAXNAMELEN]; + pathname_t newname; + int rval; + + rval = creat(name->path, mode); + if (rval >= 0 || errno != RED_ENAMETOOLONG) + return rval; + separate_pathname(name, buf, &newname); + if (chdir(buf) == 0) { + rval = creat_path(&newname, mode); + chdir(".."); + } + free_pathname(&newname); + return rval; +} + +static void dcache_enter(int dirid, int slot) +{ + dcache[dirid % NDCACHE] = slot; +} + +static void dcache_init(void) +{ + int i; + + for (i = 0; i < NDCACHE; i++) + dcache[i] = -1; +} + +static fent_t *dcache_lookup(int dirid) +{ + fent_t *fep; + int i; + + i = dcache[dirid % NDCACHE]; + if (i >= 0 && (fep = &flist[FT_DIR].fents[i])->id == dirid) + return fep; + return NULL; +} + +static void dcache_purge(int dirid) +{ + int *dcp; + + dcp = &dcache[dirid % NDCACHE]; + if (*dcp >= 0 && flist[FT_DIR].fents[*dcp].id == dirid) + *dcp = -1; +} + +static void del_from_flist(int ft, int slot) +{ + flist_t *ftp; + + ftp = &flist[ft]; + if (ft == FT_DIR) + dcache_purge(ftp->fents[slot].id); + if (slot != ftp->nfiles - 1) { + if (ft == FT_DIR) + dcache_purge(ftp->fents[ftp->nfiles - 1].id); + ftp->fents[slot] = ftp->fents[--ftp->nfiles]; + } else + ftp->nfiles--; +} + +static fent_t *dirid_to_fent(int dirid) +{ + fent_t *efep; + fent_t *fep; + flist_t *flp; + + if ((fep = dcache_lookup(dirid))) + return fep; + flp = &flist[FT_DIR]; + for (fep = flp->fents, efep = &fep[flp->nfiles]; fep < efep; fep++) { + if (fep->id == dirid) { + dcache_enter(dirid, (int)(fep - flp->fents)); + return fep; + } + } + return NULL; +} + +static void doproc(void) +{ + REDSTAT statbuf; + char buf[10]; + int opno; + opdesc_t *p; + + RedSNPrintf(buf, sizeof(buf), "p%x", procid); + (void)mkdir(buf); + if (chdir(buf) < 0 || stat64(".", &statbuf) < 0) { + perror(buf); + _exit(1); + } + top_ino = statbuf.st_ino; + homedir = getcwd(NULL, 0); + seed += procid; + srandom(seed); + if (namerand) + namerand = random(); + for (opno = 0; opno < operations; opno++) { + p = &ops[freq_table[random() % freq_table_size]]; + if ((unsigned long)p->func < 4096) + abort(); + + p->func(opno, random()); + } + free(homedir); +} + +static void fent_to_name(pathname_t *name, flist_t *flp, fent_t *fep) +{ + char buf[MAXNAMELEN]; + int i; + fent_t *pfep; + + if (fep == NULL) + return; + if (fep->parent != -1) { + pfep = dirid_to_fent(fep->parent); + fent_to_name(name, &flist[FT_DIR], pfep); + append_pathname(name, "/"); + } + i = RedSNPrintf(buf, sizeof(buf), "%c%x", flp->tag, fep->id); + namerandpad(fep->id, buf, i); + append_pathname(name, buf); +} + +static void fix_parent(int oldid, int newid) +{ + fent_t *fep; + flist_t *flp; + int i; + int j; + + for (i = 0, flp = flist; i < FT_nft; i++, flp++) { + for (j = 0, fep = flp->fents; j < flp->nfiles; j++, fep++) { + if (fep->parent == oldid) + fep->parent = newid; + } + } +} + +static void free_pathname(pathname_t *name) +{ + if (name->path) { + free(name->path); + name->path = NULL; + name->len = 0; + } +} + +static int generate_fname(fent_t *fep, int ft, pathname_t *name, int *idp, int *v) +{ + char buf[MAXNAMELEN]; + flist_t *flp; + int id; + int j; + int len; + + flp = &flist[ft]; + len = RedSNPrintf(buf, sizeof(buf), "%c%x", flp->tag, id = nameseq++); + namerandpad(id, buf, len); + if (fep) { + fent_to_name(name, &flist[FT_DIR], fep); + append_pathname(name, "/"); + } + append_pathname(name, buf); + *idp = id; + *v = verbose; + for (j = 0; !*v && j < ilistlen; j++) { + if (ilist[j] == id) { + *v = 1; + break; + } + } + return 1; +} + +static int +get_fname(int which, long r, pathname_t *name, flist_t **flpp, fent_t **fepp, int *v) +{ + int c; + fent_t *fep; + flist_t *flp; + int i; + int j; + int x; + + for (i = 0, c = 0, flp = flist; i < FT_nft; i++, flp++) { + if (which & (1 << i)) + c += flp->nfiles; + } + if (c == 0) { + if (flpp) + *flpp = NULL; + if (fepp) + *fepp = NULL; + *v = verbose; + return 0; + } + x = (int)(r % c); + for (i = 0, c = 0, flp = flist; i < FT_nft; i++, flp++) { + if (which & (1 << i)) { + if (x < c + flp->nfiles) { + fep = &flp->fents[x - c]; + if (name) + fent_to_name(name, flp, fep); + if (flpp) + *flpp = flp; + if (fepp) + *fepp = fep; + *v = verbose; + for (j = 0; !*v && j < ilistlen; j++) { + if (ilist[j] == fep->id) { + *v = 1; + break; + } + } + return 1; + } + c += flp->nfiles; + } + } +#ifdef DEBUG + RedPrintf("fsstress: get_fname failure\n"); + abort(); +#endif + return -1; + +} + +static void init_pathname(pathname_t *name) +{ + name->len = 0; + name->path = NULL; +} + +static int link_path(pathname_t *name1, pathname_t *name2) +{ + char buf1[MAXNAMELEN]; + char buf2[MAXNAMELEN]; + int down1; + pathname_t newname1; + pathname_t newname2; + int rval; + + rval = link(name1->path, name2->path); + if (rval >= 0 || errno != RED_ENAMETOOLONG) + return rval; + separate_pathname(name1, buf1, &newname1); + separate_pathname(name2, buf2, &newname2); + if (strcmp(buf1, buf2) == 0) { + if (chdir(buf1) == 0) { + rval = link_path(&newname1, &newname2); + chdir(".."); + } + } else { + if (strcmp(buf1, "..") == 0) + down1 = 0; + else if (strcmp(buf2, "..") == 0) + down1 = 1; + else if (strlen(buf1) == 0) + down1 = 0; + else if (strlen(buf2) == 0) + down1 = 1; + else + down1 = MAX(newname1.len, 3 + name2->len) <= + MAX(3 + name1->len, newname2.len); + if (down1) { + free_pathname(&newname2); + append_pathname(&newname2, "../"); + append_pathname(&newname2, name2->path); + if (chdir(buf1) == 0) { + rval = link_path(&newname1, &newname2); + chdir(".."); + } + } else { + free_pathname(&newname1); + append_pathname(&newname1, "../"); + append_pathname(&newname1, name1->path); + if (chdir(buf2) == 0) { + rval = link_path(&newname1, &newname2); + chdir(".."); + } + } + } + free_pathname(&newname1); + free_pathname(&newname2); + return rval; +} + +static int lstat64_path(pathname_t *name, REDSTAT *sbuf) +{ + char buf[MAXNAMELEN]; + pathname_t newname; + int rval; + + rval = lstat64(name->path, sbuf); + if (rval >= 0 || errno != RED_ENAMETOOLONG) + return rval; + separate_pathname(name, buf, &newname); + if (chdir(buf) == 0) { + rval = lstat64_path(&newname, sbuf); + chdir(".."); + } + free_pathname(&newname); + return rval; +} + +static void make_freq_table(void) +{ + int f; + int i; + opdesc_t *p; + + for (p = ops, f = 0; p < ops_end; p++) + f += p->freq; + freq_table = malloc(f * sizeof(*freq_table)); + freq_table_size = f; + for (p = ops, i = 0; p < ops_end; p++) { + for (f = 0; f < p->freq; f++, i++) + freq_table[i] = p->op; + } +} + +static int mkdir_path(pathname_t *name, mode_t mode) +{ + char buf[MAXNAMELEN]; + pathname_t newname; + int rval; + + rval = mkdir(name->path); + if (rval >= 0 || errno != RED_ENAMETOOLONG) + return rval; + separate_pathname(name, buf, &newname); + if (chdir(buf) == 0) { + rval = mkdir_path(&newname, mode); + chdir(".."); + } + free_pathname(&newname); + return rval; +} + +static void namerandpad(int id, char *buf, int len) +{ + int bucket; + static int buckets[8] = {0}; + static int bucket_count = 0; + int bucket_value; + int i; + int padlen; + int padmod; + + if (namerand == 0) + return; + + /* buckets[] used to be a statically initialized array with the following + initializer: { 2, 4, 8, 16, 32, 64, 128, MAXNAMELEN - 1 } + + The problem is that with Reliance Edge, the maximum name length might be + less than 128. So the below code populates buckets[] in a similar + fashion but avoids name lengths longer than the maximum. For example, + if the max name is 20, the resulting array is { 2, 4, 8, 16, 20 }. + */ + if (!bucket_count) { + bucket_count = sizeof(buckets) / sizeof(buckets[0]); + bucket_value = 2; + for (i = 0; i < bucket_count; i++) { + if (bucket_value > 128 || bucket_value >= (int)MAXNAMELEN - 1) + break; + buckets[i] = bucket_value; + bucket_value *= 2; + } + if (i < bucket_count) { + buckets[i] = MAXNAMELEN - 1; + i++; + } + bucket_count = i; + } + + bucket = (id ^ namerand) % bucket_count; + padmod = buckets[bucket] + 1 - len; + if (padmod <= 0) + return; + padlen = (id ^ namerand) % padmod; + if (padlen) { + memset(&buf[len], 'X', padlen); + buf[len + padlen] = '\0'; + } +} + +static int open_path(pathname_t *name, int oflag) +{ + char buf[MAXNAMELEN]; + pathname_t newname; + int rval; + + rval = open(name->path, oflag); + if (rval >= 0 || errno != RED_ENAMETOOLONG) + return rval; + separate_pathname(name, buf, &newname); + if (chdir(buf) == 0) { + rval = open_path(&newname, oflag); + chdir(".."); + } + free_pathname(&newname); + return rval; +} + +static DIR *opendir_path(pathname_t *name) +{ + char buf[MAXNAMELEN]; + pathname_t newname; + DIR *rval; + + rval = opendir(name->path); + if (rval || errno != RED_ENAMETOOLONG) + return rval; + separate_pathname(name, buf, &newname); + if (chdir(buf) == 0) { + rval = opendir_path(&newname); + chdir(".."); + } + free_pathname(&newname); + return rval; +} + +static int rename_path(pathname_t *name1, pathname_t *name2) +{ + char buf1[MAXNAMELEN]; + char buf2[MAXNAMELEN]; + int down1; + pathname_t newname1; + pathname_t newname2; + int rval; + + rval = rename(name1->path, name2->path); + if (rval >= 0 || errno != RED_ENAMETOOLONG) + return rval; + separate_pathname(name1, buf1, &newname1); + separate_pathname(name2, buf2, &newname2); + if (strcmp(buf1, buf2) == 0) { + if (chdir(buf1) == 0) { + rval = rename_path(&newname1, &newname2); + chdir(".."); + } + } else { + if (strcmp(buf1, "..") == 0) + down1 = 0; + else if (strcmp(buf2, "..") == 0) + down1 = 1; + else if (strlen(buf1) == 0) + down1 = 0; + else if (strlen(buf2) == 0) + down1 = 1; + else + down1 = MAX(newname1.len, 3 + name2->len) <= + MAX(3 + name1->len, newname2.len); + if (down1) { + free_pathname(&newname2); + append_pathname(&newname2, "../"); + append_pathname(&newname2, name2->path); + if (chdir(buf1) == 0) { + rval = rename_path(&newname1, &newname2); + chdir(".."); + } + } else { + free_pathname(&newname1); + append_pathname(&newname1, "../"); + append_pathname(&newname1, name1->path); + if (chdir(buf2) == 0) { + rval = rename_path(&newname1, &newname2); + chdir(".."); + } + } + } + free_pathname(&newname1); + free_pathname(&newname2); + return rval; +} + +static int rmdir_path(pathname_t *name) +{ + char buf[MAXNAMELEN]; + pathname_t newname; + int rval; + + rval = rmdir(name->path); + if (rval >= 0 || errno != RED_ENAMETOOLONG) + return rval; + separate_pathname(name, buf, &newname); + if (chdir(buf) == 0) { + rval = rmdir_path(&newname); + chdir(".."); + } + free_pathname(&newname); + return rval; +} + +static void separate_pathname(pathname_t *name, char *buf, pathname_t *newname) +{ + char *slash; + + init_pathname(newname); + slash = strchr(name->path, '/'); + if (slash == NULL) { + buf[0] = '\0'; + return; + } + *slash = '\0'; + strcpy(buf, name->path); + *slash = '/'; + append_pathname(newname, slash + 1); +} + +static int stat64_path(pathname_t *name, REDSTAT *sbuf) +{ + char buf[MAXNAMELEN]; + pathname_t newname; + int rval; + + rval = stat64(name->path, sbuf); + if (rval >= 0 || errno != RED_ENAMETOOLONG) + return rval; + separate_pathname(name, buf, &newname); + if (chdir(buf) == 0) { + rval = stat64_path(&newname, sbuf); + chdir(".."); + } + free_pathname(&newname); + return rval; +} + +static int truncate64_path(pathname_t *name, off64_t length) +{ + char buf[MAXNAMELEN]; + pathname_t newname; + int rval; + + rval = truncate64(name->path, length); + if (rval >= 0 || errno != RED_ENAMETOOLONG) + return rval; + separate_pathname(name, buf, &newname); + if (chdir(buf) == 0) { + rval = truncate64_path(&newname, length); + chdir(".."); + } + free_pathname(&newname); + return rval; +} + +static int unlink_path(pathname_t *name) +{ + char buf[MAXNAMELEN]; + pathname_t newname; + int rval; + + rval = unlink(name->path); + if (rval >= 0 || errno != RED_ENAMETOOLONG) + return rval; + separate_pathname(name, buf, &newname); + if (chdir(buf) == 0) { + rval = unlink_path(&newname); + chdir(".."); + } + free_pathname(&newname); + return rval; +} + +static void usage(const char *progname) +{ + RedPrintf("usage: %s VolumeID [Options]\n", progname); + RedPrintf("File system stress test.\n\n"); + RedPrintf("Where:\n"); + RedPrintf(" VolumeID\n"); + RedPrintf(" A volume number (e.g., 2) or a volume path prefix (e.g., VOL1: or /data)\n"); + RedPrintf(" of the volume to test.\n"); + RedPrintf("And 'Options' are any of the following:\n"); + RedPrintf(" --no-cleanup, -c\n"); + RedPrintf(" Specifies not to remove files (cleanup) after execution\n"); + RedPrintf(" --loops=count, -l count\n"); + RedPrintf(" Specifies the number of times the entire test should loop. Use 0 for\n"); + RedPrintf(" infinite. Default 1.\n"); + RedPrintf(" --nops=count, -n count\n"); + RedPrintf(" Specifies the number of operations to run (default 10000).\n"); + RedPrintf(" --namepad, -r\n"); + RedPrintf(" Specifies to use random name padding (resulting in longer names).\n"); + RedPrintf(" --seed=value, -s value\n"); + RedPrintf(" Specifies the seed for the random number generator (default timestamp).\n"); + RedPrintf(" --verbose, -v\n"); + RedPrintf(" Specifies verbose mode (without this, test is very quiet).\n"); + RedPrintf(" --dev=devname, -D devname\n"); + RedPrintf(" Specifies the device name. This is typically only meaningful when\n"); + RedPrintf(" running the test on a host machine. This can be \"ram\" to test on a RAM\n"); + RedPrintf(" disk, the path and name of a file disk (e.g., red.bin); or an OS-specific\n"); + RedPrintf(" reference to a device (on Windows, a drive letter like G: or a device name\n"); + RedPrintf(" like \\\\.\\PhysicalDrive7).\n"); + RedPrintf(" --help, -H\n"); + RedPrintf(" Prints this usage text and exits.\n\n"); + RedPrintf("Warning: This test will format the volume -- destroying all existing data.\n\n"); +} + +static void creat_f(int opno, long r) +{ + int e; + int e1; + pathname_t f; + int fd; + fent_t *fep; + int id; + int parid; + int type; + int v; + int v1; + int esz = 0; + + if (!get_fname(FT_DIRm, r, NULL, NULL, &fep, &v1)) + parid = -1; + else + parid = fep->id; + init_pathname(&f); + type = rtpct ? ((int)(random() % 100) > rtpct ? FT_REG : FT_RTF) : FT_REG; + e = generate_fname(fep, type, &f, &id, &v); + v |= v1; + if (!e) { + if (v) { + fent_to_name(&f, &flist[FT_DIR], fep); + RedPrintf("%d/%d: creat - no filename from %s\n", + procid, opno, f.path); + } + free_pathname(&f); + return; + } + fd = creat_path(&f, 0666); + e = fd < 0 ? errno : 0; + e1 = 0; + check_cwd(); + esz = 0; + if (fd >= 0) { + add_to_flist(type, id, parid); + close(fd); + } + if (v) + RedPrintf("%d/%d: creat %s x:%d %d %d\n", procid, opno, f.path, + esz, e, e1); + free_pathname(&f); +} + +static void fdatasync_f(int opno, long r) +{ + int e; + pathname_t f; + int fd; + int v; + + init_pathname(&f); + if (!get_fname(FT_REGFILE, r, &f, NULL, NULL, &v)) { + if (v) + RedPrintf("%d/%d: fdatasync - no filename\n", + procid, opno); + free_pathname(&f); + return; + } + fd = open_path(&f, O_WRONLY); + e = fd < 0 ? errno : 0; + check_cwd(); + if (fd < 0) { + if (v) + RedPrintf("%d/%d: fdatasync - open %s failed %d\n", + procid, opno, f.path, e); + free_pathname(&f); + return; + } + e = fdatasync(fd) < 0 ? errno : 0; + if (v) + RedPrintf("%d/%d: fdatasync %s %d\n", procid, opno, f.path, e); + free_pathname(&f); + close(fd); +} + +static void fsync_f(int opno, long r) +{ + int e; + pathname_t f; + int fd; + int v; + + init_pathname(&f); + if (!get_fname(FT_REGFILE, r, &f, NULL, NULL, &v)) { + if (v) + RedPrintf("%d/%d: fsync - no filename\n", procid, opno); + free_pathname(&f); + return; + } + fd = open_path(&f, O_WRONLY); + e = fd < 0 ? errno : 0; + check_cwd(); + if (fd < 0) { + if (v) + RedPrintf("%d/%d: fsync - open %s failed %d\n", + procid, opno, f.path, e); + free_pathname(&f); + return; + } + e = fsync(fd) < 0 ? errno : 0; + if (v) + RedPrintf("%d/%d: fsync %s %d\n", procid, opno, f.path, e); + free_pathname(&f); + close(fd); +} + +static void getdents_f(int opno, long r) +{ + DIR *dir; + pathname_t f; + int v; + + init_pathname(&f); + if (!get_fname(FT_DIRm, r, &f, NULL, NULL, &v)) + append_pathname(&f, "."); + dir = opendir_path(&f); + check_cwd(); + if (dir == NULL) { + if (v) + RedPrintf("%d/%d: getdents - can't open %s\n", + procid, opno, f.path); + free_pathname(&f); + return; + } + while (readdir64(dir) != NULL) + continue; + if (v) + RedPrintf("%d/%d: getdents %s 0\n", procid, opno, f.path); + free_pathname(&f); + closedir(dir); +} + +static void link_f(int opno, long r) +{ + int e; + pathname_t f; + fent_t *fep; + flist_t *flp; + int id; + pathname_t l; + int parid; + int v; + int v1; + + init_pathname(&f); + if (!get_fname(FT_NOTDIR, r, &f, &flp, NULL, &v1)) { + if (v1) + RedPrintf("%d/%d: link - no file\n", procid, opno); + free_pathname(&f); + return; + } + if (!get_fname(FT_DIRm, random(), NULL, NULL, &fep, &v)) + parid = -1; + else + parid = fep->id; + v |= v1; + init_pathname(&l); + e = generate_fname(fep, (int)(flp - flist), &l, &id, &v1); + v |= v1; + if (!e) { + if (v) { + fent_to_name(&l, &flist[FT_DIR], fep); + RedPrintf("%d/%d: link - no filename from %s\n", + procid, opno, l.path); + } + free_pathname(&l); + free_pathname(&f); + return; + } + e = link_path(&f, &l) < 0 ? errno : 0; + check_cwd(); + if (e == 0) + add_to_flist((int)(flp - flist), id, parid); + if (v) + RedPrintf("%d/%d: link %s %s %d\n", procid, opno, f.path, l.path, + e); + free_pathname(&l); + free_pathname(&f); +} + +static void mkdir_f(int opno, long r) +{ + int e; + pathname_t f; + fent_t *fep; + int id; + int parid; + int v; + int v1; + + if (!get_fname(FT_DIRm, r, NULL, NULL, &fep, &v)) + parid = -1; + else + parid = fep->id; + init_pathname(&f); + e = generate_fname(fep, FT_DIR, &f, &id, &v1); + v |= v1; + if (!e) { + if (v) { + fent_to_name(&f, &flist[FT_DIR], fep); + RedPrintf("%d/%d: mkdir - no filename from %s\n", + procid, opno, f.path); + } + free_pathname(&f); + return; + } + e = mkdir_path(&f, 0777) < 0 ? errno : 0; + check_cwd(); + if (e == 0) + add_to_flist(FT_DIR, id, parid); + if (v) + RedPrintf("%d/%d: mkdir %s %d\n", procid, opno, f.path, e); + free_pathname(&f); +} + +static void read_f(int opno, long r) +{ + char *buf; + int e; + pathname_t f; + int fd; + uint32_t len; + __int64_t lr; + off64_t off; + REDSTAT stb; + int v; + + init_pathname(&f); + if (!get_fname(FT_REGFILE, r, &f, NULL, NULL, &v)) { + if (v) + RedPrintf("%d/%d: read - no filename\n", procid, opno); + free_pathname(&f); + return; + } + fd = open_path(&f, O_RDONLY); + e = fd < 0 ? errno : 0; + check_cwd(); + if (fd < 0) { + if (v) + RedPrintf("%d/%d: read - open %s failed %d\n", + procid, opno, f.path, e); + free_pathname(&f); + return; + } + if (fstat64(fd, &stb) < 0) { + if (v) + RedPrintf("%d/%d: read - fstat64 %s failed %d\n", + procid, opno, f.path, errno); + free_pathname(&f); + close(fd); + return; + } + if (stb.st_size == 0) { + if (v) + RedPrintf("%d/%d: read - %s zero size\n", procid, opno, + f.path); + free_pathname(&f); + close(fd); + return; + } + lr = ((__int64_t) random() << 32) + random(); + off = (off64_t) (lr % stb.st_size); + lseek64(fd, off, SEEK_SET); + len = (random() % (getpagesize() * 4)) + 1; + buf = malloc(len); + e = read(fd, buf, len) < 0 ? errno : 0; + free(buf); + if (v) + RedPrintf("%d/%d: read %s [%lld,%ld] %d\n", + procid, opno, f.path, (long long)off, (long int)len, e); + free_pathname(&f); + close(fd); +} + +static void rename_f(int opno, long r) +{ + fent_t *dfep; + int e; + pathname_t f; + fent_t *fep; + flist_t *flp; + int id; + pathname_t newf; + int oldid; + int parid; + int v; + int v1; + + init_pathname(&f); + if (!get_fname(FT_ANYm, r, &f, &flp, &fep, &v1)) { + if (v1) + RedPrintf("%d/%d: rename - no filename\n", procid, opno); + free_pathname(&f); + return; + } + if (!get_fname(FT_DIRm, random(), NULL, NULL, &dfep, &v)) + parid = -1; + else + parid = dfep->id; + v |= v1; + init_pathname(&newf); + e = generate_fname(dfep, (int)(flp - flist), &newf, &id, &v1); + v |= v1; + if (!e) { + if (v) { + fent_to_name(&f, &flist[FT_DIR], dfep); + RedPrintf("%d/%d: rename - no filename from %s\n", + procid, opno, f.path); + } + free_pathname(&newf); + free_pathname(&f); + return; + } + e = rename_path(&f, &newf) < 0 ? errno : 0; + check_cwd(); + if (e == 0) { + if (flp - flist == FT_DIR) { + oldid = fep->id; + fix_parent(oldid, id); + } + del_from_flist((int)(flp - flist), (int)(fep - flp->fents)); + add_to_flist((int)(flp - flist), id, parid); + } + if (v) + RedPrintf("%d/%d: rename %s to %s %d\n", procid, opno, f.path, + newf.path, e); + free_pathname(&newf); + free_pathname(&f); +} + +static void rmdir_f(int opno, long r) +{ + int e; + pathname_t f; + fent_t *fep; + int v; + + init_pathname(&f); + if (!get_fname(FT_DIRm, r, &f, NULL, &fep, &v)) { + if (v) + RedPrintf("%d/%d: rmdir - no directory\n", procid, opno); + free_pathname(&f); + return; + } + e = rmdir_path(&f) < 0 ? errno : 0; + check_cwd(); + if (e == 0) + del_from_flist(FT_DIR, (int)(fep - flist[FT_DIR].fents)); + if (v) + RedPrintf("%d/%d: rmdir %s %d\n", procid, opno, f.path, e); + free_pathname(&f); +} + +static void stat_f(int opno, long r) +{ + int e; + pathname_t f; + REDSTAT stb; + int v; + + init_pathname(&f); + if (!get_fname(FT_ANYm, r, &f, NULL, NULL, &v)) { + if (v) + RedPrintf("%d/%d: stat - no entries\n", procid, opno); + free_pathname(&f); + return; + } + e = lstat64_path(&f, &stb) < 0 ? errno : 0; + check_cwd(); + if (v) + RedPrintf("%d/%d: stat %s %d\n", procid, opno, f.path, e); + free_pathname(&f); +} + +static void truncate_f(int opno, long r) +{ + int e; + pathname_t f; + __int64_t lr; + off64_t off; + REDSTAT stb; + int v; + + init_pathname(&f); + if (!get_fname(FT_REGFILE, r, &f, NULL, NULL, &v)) { + if (v) + RedPrintf("%d/%d: truncate - no filename\n", procid, opno); + free_pathname(&f); + return; + } + e = stat64_path(&f, &stb) < 0 ? errno : 0; + check_cwd(); + if (e > 0) { + if (v) + RedPrintf("%d/%d: truncate - stat64 %s failed %d\n", + procid, opno, f.path, e); + free_pathname(&f); + return; + } + lr = ((__int64_t) random() << 32) + random(); + off = lr % MIN(stb.st_size + (1024 * 1024), MAXFSIZE); + off %= maxfsize; + e = truncate64_path(&f, off) < 0 ? errno : 0; + check_cwd(); + if (v) + RedPrintf("%d/%d: truncate %s %lld %d\n", procid, opno, f.path, + (long long)off, e); + free_pathname(&f); +} + +static void unlink_f(int opno, long r) +{ + int e; + pathname_t f; + fent_t *fep; + flist_t *flp; + int v; + + init_pathname(&f); + if (!get_fname(FT_NOTDIR, r, &f, &flp, &fep, &v)) { + if (v) + RedPrintf("%d/%d: unlink - no file\n", procid, opno); + free_pathname(&f); + return; + } + e = unlink_path(&f) < 0 ? errno : 0; + check_cwd(); + if (e == 0) + del_from_flist((int)(flp - flist), (int)(fep - flp->fents)); + if (v) + RedPrintf("%d/%d: unlink %s %d\n", procid, opno, f.path, e); + free_pathname(&f); +} + +static void write_f(int opno, long r) +{ + char *buf; + int e; + pathname_t f; + int fd; + uint32_t len; + __int64_t lr; + off64_t off; + REDSTAT stb; + int v; + + init_pathname(&f); + if (!get_fname(FT_REGm, r, &f, NULL, NULL, &v)) { + if (v) + RedPrintf("%d/%d: write - no filename\n", procid, opno); + free_pathname(&f); + return; + } + fd = open_path(&f, O_WRONLY); + e = fd < 0 ? errno : 0; + check_cwd(); + if (fd < 0) { + if (v) + RedPrintf("%d/%d: write - open %s failed %d\n", + procid, opno, f.path, e); + free_pathname(&f); + return; + } + if (fstat64(fd, &stb) < 0) { + if (v) + RedPrintf("%d/%d: write - fstat64 %s failed %d\n", + procid, opno, f.path, errno); + free_pathname(&f); + close(fd); + return; + } + lr = ((__int64_t) random() << 32) + random(); + off = (off64_t) (lr % MIN(stb.st_size + (1024 * 1024), MAXFSIZE)); + off %= maxfsize; + lseek64(fd, off, SEEK_SET); + len = (random() % (getpagesize() * 4)) + 1; + buf = malloc(len); + memset(buf, nameseq & 0xff, len); + e = write(fd, buf, len) < 0 ? errno : 0; + free(buf); + if (v) + RedPrintf("%d/%d: write %s [%lld,%ld] %d\n", + procid, opno, f.path, (long long)off, (long int)len, e); + free_pathname(&f); + close(fd); +} + + +#if REDCONF_CHECKER == 1 +static void check_f(int opno, long r) +{ + int32_t ret; + const char *pszVolume = gpRedVolConf->pszPathPrefix; + + (void)r; + + errno = 0; + + ret = red_transact(pszVolume); + + if(ret == 0) + { + ret = red_umount(pszVolume); + + if(ret == 0) + { + int32_t ret2; + + errno = -RedCoreVolCheck(); + if(errno != 0) + { + ret = -1; + } + + ret2 = red_mount(pszVolume); + + if(ret == 0) + { + ret = ret2; + } + + if(ret2 != 0) + { + exit(1); + } + } + } + + if (verbose) + { + RedPrintf("%d/%d: check %s %d\n", procid, opno, pszVolume, errno); + } +} +#endif + + +#endif /* FSSTRESS_SUPPORTED */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/tests/posix/redposixcompat.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/tests/posix/redposixcompat.h new file mode 100644 index 0000000..6c59e93 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/tests/posix/redposixcompat.h @@ -0,0 +1,152 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Defines macros which make the Reliance Edge POSIX-like API look more + like the actual POSIX API. + + This file is intended for porting POSIX file system tests; it is not + intended for application use. +*/ +#ifndef REDPOSIXCOMPAT_H +#define REDPOSIXCOMPAT_H + + +#ifndef assert +#define assert(x) REDASSERT(x) +#endif + + +#undef O_RDONLY +#undef O_WRONLY +#undef O_RDWR +#undef O_APPEND +#undef O_CREAT +#undef O_EXCL +#undef O_TRUNC +#define O_RDONLY RED_O_RDONLY +#define O_WRONLY RED_O_WRONLY +#define O_RDWR RED_O_RDWR +#define O_APPEND RED_O_APPEND +#define O_CREAT RED_O_CREAT +#define O_EXCL RED_O_EXCL +#define O_TRUNC RED_O_TRUNC + +#undef SEEK_SET +#undef SEEK_CUR +#undef SEEK_END +#define SEEK_SET RED_SEEK_SET +#define SEEK_CUR RED_SEEK_CUR +#define SEEK_END RED_SEEK_END + +/* Old-fashioned Linux seek names. +*/ +#undef L_SET +#undef L_INCR +#undef L_XTND +#define L_SET SEEK_SET +#define L_INCR SEEK_CUR +#define L_XTND SEEK_END + +#undef S_IFDIR +#undef S_IFREG +#undef S_ISDIR +#undef S_ISREG +#define S_IFDIR RED_S_IFDIR +#define S_IFREG RED_S_IFREG +#define S_ISDIR(m) RED_S_ISDIR(m) +#define S_ISREG(m) RED_S_ISREG(m) + +#undef ST_RDONLY +#undef ST_NOSUID +#define ST_RDONLY RED_ST_RDONLY +#define ST_NOSUID RED_ST_NOSUID + +#undef open +#undef creat +#undef unlink +#undef mkdir +#undef rmdir +#undef rename +#undef link +#undef close +#undef read +#undef write +#undef fsync +#undef fdatasync +#undef lseek +#undef ftruncate +#undef fstat +#undef opendir +#undef readdir +#undef rewinddir +#undef closedir +#define open(path, oflag) red_open(path, oflag) +#define creat(path, mode) open(path, O_WRONLY|O_CREAT|O_TRUNC) +#define unlink(path) red_unlink(path) +#define mkdir(path) red_mkdir(path) +#define rmdir(path) red_rmdir(path) +#define rename(old, new) red_rename(old, new) +#define link(path, hardlink) red_link(path, hardlink) +#define close(fd) red_close(fd) +#define read(fd, buf, len) red_read(fd, buf, len) +#define write(fd, buf, len) red_write(fd, buf, len) +#define fsync(fd) red_fsync(fd) +#define fdatasync(fd) fsync(fd) +#define lseek(fd, offset, whence) red_lseek(fd, offset, whence) +#define lseek64(fd, offset, whence) lseek(fd, offset, whence) +#define ftruncate(fd, size) red_ftruncate(fd, size) +#define fstat(fd, stat) red_fstat(fd, stat) +#define fstat64(fd, stat) fstat(fd, stat) +#define opendir(path) red_opendir(path) +#define readdir(dirp) red_readdir(dirp) +#define readdir64(dirp) readdir(dirp) +#define rewinddir(dirp) red_rewinddir(dirp) +#define closedir(dirp) red_closedir(dirp) + +#undef DIR +#define DIR REDDIR + +#undef errno +#define errno (*(int *)red_errnoptr()) + +#undef memcpy +#undef memmove +#undef memset +#undef strlen +#undef strncmp +#undef strcmp +#undef strncpy +#define memcpy(d, s, l) RedMemCpy(d, s, (uint32_t)(l)) +#define memmove(d, s, l) RedMemMove(d, s, (uint32_t)(l)) +#define memset(d, c, l) RedMemSet(d, (uint8_t)(c), (uint32_t)(l)) +#define strlen(s) RedStrLen(s) +#define strncmp(s1, s2, l) RedStrNCmp(s1, s2, (uint32_t)(l)) +#define strcmp(s1, s2) RedStrCmp(s1, s2) +#define strncpy(d, s, l) RedStrNCpy(d, s, (uint32_t)(l)) + + +#endif + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/tests/util/atoi.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/tests/util/atoi.c new file mode 100644 index 0000000..ec11e0a --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/tests/util/atoi.c @@ -0,0 +1,478 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements utilities that convert strings to numbers. +*/ +#include +#include + + +#define ISHEXDIGITU(c) (((c) >= 'A') && ((c) <= 'F')) +#define ISHEXDIGITL(c) (((c) >= 'a') && ((c) <= 'f')) +#define ISHEXDIGIT(c) (ISHEXDIGITL(c) || ISHEXDIGITU(c)) + + +/** @brief Converts an ASCII number into an int32_t. + + Converts all decimal digit numbers up to the end of the string or to the + first non-numerical character. + + @note This function does *not* ignore leading white space. + + @param pszNum Pointer to a constant array of characters. + + @return The integer represented in the string. +*/ +int32_t RedAtoI( + const char *pszNum) +{ + int32_t lValue = 0; + int32_t lNegative = 1; + uint32_t ulIdx = 0U; + + if(pszNum[ulIdx] == '+') + { + ulIdx++; + } + else if(pszNum[ulIdx] == '-') + { + ulIdx++; + lNegative = -1; + } + else + { + /* No sign, implicitly positive. + */ + } + + while(ISDIGIT(pszNum[ulIdx])) + { + lValue *= 10; + lValue += pszNum[ulIdx] - '0'; + ulIdx++; + } + + lValue *= lNegative; + + return lValue; +} + + +/** @brief Convert a hexadecimal ASCII number into a uint32_t value. + + The function processes all hex digits up to a NUL-terminator, or to the + first non-hex character. Only hexadecimal digits are processed, so leading + white space, or a leading "0x" prefix are not allowed. + + If pachNum points to an empty string (points to a NUL), this function will + return NULL, and the value at *pulNum will not be modified. + + @note This function does not check for overflow. If there are more + significant digits than can be represented in a uint32_t variable, the + output is unspecified. + + @param pszNum A pointer to a constant array of hex characters. + @param pulNum A pointer to the location in which to store the uint32_t + result. Upon return, this value will be modified ONLY if + the function succeeds and the returned pointer is valid (not + NULL). + + @return A pointer to the byte following the converted number or NULL to + indicate failure. +*/ +const char *RedHtoUL( + const char *pszNum, + uint32_t *pulNum) +{ + uint64_t ullValue; + const char *pszReturn; + + pszReturn = RedHtoULL(pszNum, &ullValue); + if(pszReturn != NULL) + { + if(ullValue < UINT32_MAX) + { + *pulNum = (uint32_t)ullValue; + } + else + { + pszReturn = NULL; + } + } + + return pszReturn; +} + + +/** @brief Convert a hexadecimal ASCII number into a D_UINT64 value. + + The function processes all hex digits up to a NUL-terminator, or to the + first non-hex character. Only hexadecimal digits are processed, so leading + white space, or a leading "0x" prefix are not allowed. + + If pachNum points to an empty string (points to a NUL), this function will + return NULL, and the value at *pulNum will not be modified. + + @note This function does not check for overflow. If there are more + significant digits than can be represented in a uint64_t variable, the + output is unspecified. + + @param pszNum A pointer to a constant array of hex characters. + @param pullNum A pointer to the location in which to store the uint64_t + result. Upon return, this value will be modified ONLY if + the function succeeds and the returned pointer is valid (not + NULL). + + @return A pointer to the byte following the converted number, or NULL to + indicate failure. +*/ +const char *RedHtoULL( + const char *pszNum, + uint64_t *pullNum) +{ + uint64_t ullValue = 0U; + const char *pszReturn = NULL; + uint32_t ulIdx = 0U; + + REDASSERT(pszNum != NULL); + REDASSERT(pullNum != NULL); + + while(pszNum[ulIdx] != '\0') + { + char cDigit = pszNum[ulIdx]; + + if(ISDIGIT(cDigit)) + { + cDigit -= '0'; + } + else if(ISHEXDIGITU(cDigit)) + { + cDigit -= ('A' - 10); + } + else if(ISHEXDIGITL(cDigit)) + { + cDigit -= ('a' - 10); + } + else + { + break; + } + + REDASSERT((ullValue & UINT64_SUFFIX(0xF000000000000000)) == 0U); + + ullValue <<= 4U; + ullValue += cDigit; + + ulIdx++; + pszReturn = &pszNum[ulIdx]; + } + + /* Modify the number returned only if we found one or more valid hex + digits. + */ + if(pszReturn != NULL) + { + *pullNum = ullValue; + } + + return pszReturn; +} + + +/** @brief Convert the ASCII number to a uint32_t value. + + The number may be hex or decimal. Hex numbers must be prefixed by '0x', and + they may be upper or lower case. The conversion process will stop with the + first non hex or decimal digit. + + If the number is negative (the first character is a '-' sign), the value + will be range checked and returned as the equivalent unsigned value. + + @note This function will NOT fail for numbers which exceed the size of a + uint32_t value. + + @param pszNum A pointer to the ASCII number to convert + @param pulNum A pointer to the uint32_t location to store the result. + This value will be modified on return only if the function + succeeds and the returned pointer is valid (not NULL). + + @return A pointer to the byte following the converted number, or NULL to + indicate failure. +*/ +const char *RedNtoUL( + const char *pszNum, + uint32_t *pulNum) +{ + bool fNegative = false; + uint32_t ulIdx = 0U; + const char *pszReturn; + + REDASSERT(pszNum != NULL); + REDASSERT(pulNum != NULL); + + if(pszNum[ulIdx] == '-') + { + fNegative = true; + ulIdx++; + } + + /* Hex numbers must be prefixed with '0x'. + */ + if((pszNum[ulIdx] == '0') && ((pszNum[ulIdx + 1U] == 'x') || (pszNum[ulIdx + 1U] == 'X'))) + { + ulIdx += 2U; + + if(ISDIGIT(pszNum[ulIdx]) || ISHEXDIGIT(pszNum[ulIdx])) + { + pszReturn = RedHtoUL(&pszNum[ulIdx], pulNum); + } + else + { + pszReturn = NULL; + } + } + else if(ISDIGIT(pszNum[ulIdx])) + { + uint32_t ulTemp; + + ulTemp = RedAtoI(&pszNum[ulIdx]); + + while(ISDIGIT(pszNum[ulIdx])) + { + ulIdx++; + } + + if(fNegative) + { + /* Fail if the number is out of range. + */ + if(ulTemp > INT32_MAX) + { + pszReturn = NULL; + } + else + { + *pulNum = -((int32_t)ulTemp); + pszReturn = &pszNum[ulIdx]; + } + } + else + { + *pulNum = ulTemp; + pszReturn = &pszNum[ulIdx]; + } + } + else + { + /* Return an error if there is not at least one hex or decimal digit. + */ + pszReturn = NULL; + } + + return pszReturn; +} + + +/** @brief Convert the ASCII number pointed to by pachNum to a uint64_t value. + + The number may be hex or decimal. Hex numbers must be prefixed by '0x', and + they may be upper or lower case. The conversion process will stop with the + first non hex or decimal digit. + + If the number is negative (the first character is a '-' sign), the value + will be range checked and returned as the equivalent unsigned value. + + @param pszNum A pointer to the ASCII number to convert. + @param pullNum A pointer to the uint64_t location to store the result. + This value will be modified on return only if the function + succeeds and the returned pointer is valid (not NULL). + + @return A pointer to the byte following the converted number, or NULL to + indicate failure. +*/ +const char *RedNtoULL( + const char *pszNum, + uint64_t *pullNum) +{ + bool fNegative = false; + uint32_t ulIdx = 0U; + const char *pszReturn; + + REDASSERT(pszNum != NULL); + REDASSERT(pullNum != NULL); + + if(pszNum[ulIdx] == '-') + { + fNegative = true; + ulIdx++; + } + + /* Hex numbers must be prefixed with '0x'. + */ + if((pszNum[ulIdx] == '0') && ((pszNum[ulIdx + 1U] == 'x') || (pszNum[ulIdx + 1U] == 'X'))) + { + ulIdx += 2U; + + if(ISDIGIT(pszNum[ulIdx]) || ISHEXDIGIT(pszNum[ulIdx])) + { + pszReturn = RedHtoULL(&pszNum[ulIdx], pullNum); + } + else + { + pszReturn = NULL; + } + } + else if(ISDIGIT(pszNum[ulIdx])) + { + uint64_t ullTemp = 0U; + + while(ISDIGIT(pszNum[ulIdx])) + { + ullTemp *= 10U; + ullTemp += pszNum[ulIdx] - '0'; + ulIdx++; + } + + if(fNegative) + { + /* Fail if the number is out of range. + */ + if(ullTemp > INT64_MAX) + { + pszReturn = NULL; + } + else + { + *pullNum = (uint64_t)(-((int64_t)ullTemp)); + pszReturn = &pszNum[ulIdx]; + } + } + else + { + *pullNum = ullTemp; + pszReturn = &pszNum[ulIdx]; + } + } + else + { + /* Return an error if there is not at least one hex or decimal digit. + */ + pszReturn = NULL; + } + + return pszReturn; +} + + +/** @brief Convert an ASCII hex or decimal number, which may may have a "B", + "KB", or "MB" suffix (case insensitive), to a binary value. + + Hex numbers must be prefixed with "0x". + + @note If there is no postfix, KB is assumed! + + May fail due to bad formatting or overflow. + + @param pszNum A pointer to the ASCII number to convert. + @param pulResult A pointer to a uint32_t in which to place the result. + + @return A pointer to the byte following the string, or NULL to indicate an + error. In the event of an error, *pulResult will not be modified. +*/ +const char *RedSizeToUL( + const char *pszNum, + uint32_t *pulResult) +{ + uint32_t ulResult; + const char *pszSuffix; + const char *pszReturn; + uint32_t ulIdx = 0U; + + REDASSERT(pszNum != NULL); + REDASSERT(pulResult != NULL); + + /* Do the basic hex/decimal conversion + */ + pszSuffix = RedNtoUL(pszNum, &ulResult); + if(pszSuffix != NULL) + { + if((pszSuffix[ulIdx] == 'B') || (pszSuffix[ulIdx] == 'b')) + { + ulIdx++; + pszReturn = &pszSuffix[ulIdx]; + } + else if( ((pszSuffix[ulIdx] == 'M') || (pszSuffix[ulIdx] == 'm')) + && ((pszSuffix[ulIdx + 1U] == 'B') || (pszSuffix[ulIdx + 1U] == 'b'))) + { + ulIdx += 2U; + + if(ulResult > (UINT32_MAX / (1024U * 1024U))) + { + pszReturn = NULL; + } + else + { + ulResult *= 1024U * 1024U; + pszReturn = &pszSuffix[ulIdx]; + } + } + else + { + /* The number is either postfixed with "KB" or something + else (we don't care), but we must increment the pointer + if it is something recognize. + */ + if( ((pszSuffix[ulIdx] == 'K') || (pszSuffix[ulIdx] == 'k')) + && ((pszSuffix[ulIdx + 1U] == 'B') || (pszSuffix[ulIdx + 1U] == 'b'))) + { + ulIdx += 2U; + } + + /* "B" or "MB" were not specified, so it must be "KB" + */ + if(ulResult > (UINT32_MAX / 1024U)) + { + pszReturn = NULL; + } + else + { + ulResult *= 1024UL; + pszReturn = &pszSuffix[ulIdx]; + } + } + + if(pszReturn != NULL) + { + *pulResult = ulResult; + } + } + else + { + pszReturn = NULL; + } + + return pszReturn; +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/tests/util/math.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/tests/util/math.c new file mode 100644 index 0000000..00f6bc3 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/tests/util/math.c @@ -0,0 +1,641 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements routines for certain 64-bit math operations and simulated + floating point. + + RedUint64DivMod32() and RedUint64DivMod64() are derived from code at + http://www.hackersdelight.org. This web site states explicitly that "You + are free to use, copy, and distribute any of the code on this web site, + whether modified by you or not. You need not give attribution." +*/ +#include +#include + + +static uint32_t nlz64(uint64_t ullValue); + + +/** @brief Return a ratio value formatted as a floating point string accurate to + the specified number of decimal places. + + The function exists to provide floating point style output without using + any actual floating point types. + + This function may scale the numbers down to avoid overflow at the high end. + Likewise, potential divide-by-zero errors are internally avoided. Here are + some examples: + + Dividend | Divisor | DecPlaces | Result + -------- | ------- | --------- | ------ + 12133 | 28545 | 2 | "0.42" + 1539 | 506 | 2 | "3.04" + + To get a number formatted as a percentage, take the take the portion of the + total (normally the smaller part), multiply it by 100, and pass it to this + function as the Dividend, pass the "total" value to this function as the + Divisor, and specify the desired number of decimal places. + + For example, if you have a disk format overhead value of N blocks out of a + total of Y blocks on the disk, and you want to display the format overhead + as a percentage, you would use a function call + similar to: + + ~~~{.c} + RedRatio(szBuffer, sizeof(szBuffer), N*100U, Y, 2U); + ~~~ + + If N=145, Y=4096, and decimal places is 2, the resulting output would be + "3.54". + + The string returned will always be null-terminated, even if it means + stomping on the least significant decimal digit. + + If either the dividend or divisor values are zero, the string "0.0" will be + returned, with the prescribed number of decimal places. + + @note This function has "reasonable" limits which meet the needs of the + various supplemental utilities which use this function. Extremely + large ratios, or using many decimal places may not function as + desired. + + Parameters: + @param pBuffer A pointer to the buffer in which to store the null + terminated results. + @param ulBufferLen The length of the output buffer. + @param ullDividend The "total" value to divide. + @param ullDivisor The portion of ullDividend for which to calculate the + ratio (may be greater than ulDividend). + @param ulDecPlaces The number of decimal places to use, from 0 to 9. + + @return @p pBuffer. +*/ +char *RedRatio( + char *pBuffer, + uint32_t ulBufferLen, + uint64_t ullDividend, + uint64_t ullDivisor, + uint32_t ulDecPlaces) +{ + REDASSERT(pBuffer != NULL); + REDASSERT(ulBufferLen > 0U); + REDASSERT(ulDecPlaces <= 9U); /* arbitrary */ + + if((ullDivisor > 0U) && (ullDividend > 0U)) + { + uint32_t ii; + uint32_t ulFactor = 1U; + uint64_t ullDecimal; + uint64_t ullTemp; + + for(ii = 1U; ii <= ulDecPlaces; ii++) + { + ulFactor *= 10U; + } + + ullDecimal = RedMulDiv64(ullDividend, ulFactor, ullDivisor); + + /* Shouldn't really be calling this function in a situation where we + can overflow at this point... + */ + REDASSERT(ullDecimal != UINT64_MAX); + + if(ullDivisor <= ullDividend) + { + uint32_t ulDecimal; + + (void)RedUint64DivMod32(ullDecimal, ulFactor, &ulDecimal); + ullDecimal = ulDecimal; + } + + ullTemp = RedUint64DivMod64(ullDividend, ullDivisor, NULL); + + if(ulDecPlaces > 0U) + { + RedSNPrintf(pBuffer, ulBufferLen, "%llu.%0*llu", (unsigned long long)ullTemp, + (unsigned)ulDecPlaces, (unsigned long long)ullDecimal); + } + else + { + RedSNPrintf(pBuffer, ulBufferLen, "%llu", (unsigned long long)ullTemp); + } + } + else + { + /* If either the dividend or divisor is zero, then just output a "0.0" + string with the prescribed number of decimal places. + */ + if(ulDecPlaces > 0U) + { + RedSNPrintf(pBuffer, ulBufferLen, "0.%0*u", (unsigned)ulDecPlaces, 0U); + } + else + { + RedStrNCpy(pBuffer, "0", ulBufferLen); + } + } + + /* Ensure the returned buffer is always null-terminated + */ + pBuffer[ulBufferLen - 1U] = '\0'; + + return pBuffer; +} + + +/** @brief Multiply 64-bit and 32-bit numbers, and divide by a 64-bit number, + returning a 64-bit result. + + @note This function may return an approximate value if multiplying + @p ullBase and @p ulMultplier results in a number larger than 64-bits + _and_ this cannot be avoided by scaling. + + @param ullBase The base 64-bit number number. + @param ulMultiplier The 32-bit number by which to multiply. + @param ullDivisor The 64-bit number by which to divide. + + @return The 64-bit unsigned integer result. Always returns zero if either + @p ullBase or @p ulMultiplier are zero (regardless what + @p ullDivisor is). Returns UINT64_MAX if an overflow condition + occurred, or if @p ullDivisor is zero. +*/ +uint64_t RedMulDiv64( + uint64_t ullBase, + uint32_t ulMultiplier, + uint64_t ullDivisor) +{ + uint64_t ullTemp; + + /* Result would always be zero if either of these are zero. Specifically + test this case before looking for a zero divisor. + */ + if((ullBase == 0U) || (ulMultiplier == 0U)) + { + return 0U; + } + + if(ullDivisor == 0U) + { + return UINT64_MAX; + } + + /* Since we don't have the ability (yet) to use 128-bit numbers, we jump + through the following hoops (in order) to try to determine the proper + results without losing precision: + + 1) Shift the divisor and one of the multiplicands as many times as is + necessary to reduce the scale -- only if it can be done without + losing precision. + 2) Divide one of the multiplicands by the divisor first, but only if it + divides evenly, preserving precision. + 3) Same as #2, but try it for the other multiplicand. + 4) Last ditch, divide the larger multiplicand by the divisor first, then + do the multiply. This lose precision. + + These solutions are identified as CODE-PATHs #1-4 which are used to + identify the matching tests in dltmain.c. + + Note that execution might partially include CODE-PATH #1 up until + shifting can no longer be done without losing precision. In that case, + one of the three remaining options will be used. + */ + + ullTemp = RedUint64DivMod32(UINT64_MAX, ulMultiplier, NULL); + while(ullBase > ullTemp) + { + uint64_t ullMod; + uint64_t ullBaseTemp; + uint64_t ullWideMultiplier; + + /* CODE-PATH #1 + */ + /* So long as ulDivisor, and at least one of the other numbers, are + evenly divisible by 2, we can scale the numbers so the result does + not overflow the intermediate 64-bit value. + */ + if((ullDivisor & 1U) == 0U) + { + if((ullBase & 1U) == 0U) + { + /* CODE-PATH #1a + */ + ullDivisor >>= 1U; + ullBase >>= 1U; + continue; + } + + if(((ulMultiplier & 1U) == 0U) && ((ullTemp & UINT64_SUFFIX(0x8000000000000000)) == 0U)) + { + /* CODE-PATH #1b + */ + ullDivisor >>= 1U; + ulMultiplier >>= 1U; + ullTemp <<= 1U; + continue; + } + } + + /* If we get to this point, the above method (#1) cannot be used + because not enough of the numbers are even long enough to scale the + operands down. We'll see if either multiplicand is evenly divisble + by ulDivisor, and if so, do the divide first, then the multiply. + (Note that once we get to this point, we will never exercise the + while{} loop anymore.) + */ + + /* CODE-PATH #2 + */ + ullBaseTemp = RedUint64DivMod64(ullBase, ullDivisor, &ullMod); + if(ullMod == 0U) + { + /* Evenly divides, so check that we won't overflow, and finish up. + */ + ullBase = ullBaseTemp; + if(ullBase > ullTemp) + { + return UINT64_MAX; + } + else + { + /* We've validated that this will not overflow. + */ + ullBase *= ulMultiplier; + return ullBase; + } + } + + /* CODE-PATH #3 + */ + ullWideMultiplier = RedUint64DivMod64(ulMultiplier, ullDivisor, &ullMod); + if(ullMod == 0U) + { + /* Evenly divides, so check that we won't overflow, and finish up. + */ + + /* Must recalculate ullTemp relative to ullBase + */ + ullTemp = RedUint64DivMod64(UINT64_MAX, ullBase, NULL); + if(ullWideMultiplier > ullTemp) + { + return UINT64_MAX; + } + else + { + uint32_t ulNarrowMultiplier = (uint32_t)ullWideMultiplier; + + /* We've validated that this will not overflow. + */ + ullBase *= ulNarrowMultiplier; + return ullBase; + } + } + + /* CODE-PATH #4 + + Neither of the multipliers is evenly divisible by the divisor, so + just punt and divide the larger number first, then do the final + multiply. + + All the other attempts above would preserve precision -- this is the + only case where precision may be lost. + */ + + /* If necessary reverse the ullBase and ulMultiplier operands so that + ullBase contains the larger of the two values. + */ + if(ullBase < ulMultiplier) + { + uint32_t ulTemp = ulMultiplier; + + ulMultiplier = (uint32_t)ullBase; + ullBase = ulTemp; + } + + ullBase = RedUint64DivMod64(ullBase, ullDivisor, NULL); + ullTemp = RedUint64DivMod32(UINT64_MAX, ulMultiplier, NULL); + if(ullBase > ullTemp) + { + return UINT64_MAX; + } + else + { + ullBase *= ulMultiplier; + return ullBase; + } + } + + /* We only get to this point if either there was never any chance of + overflow, or if the pure shifting mechanism succeeded in reducing + the scale so overflow is not a problem. + */ + + ullBase *= ulMultiplier; + ullBase = RedUint64DivMod64(ullBase, ullDivisor, NULL); + + return ullBase; +} + + +/** @brief Divide a 64-bit value by a 32-bit value, returning the quotient and + the remainder. + + Essentially this function does the following: + + ~~~{.c} + if(pulRemainder != NULL) + { + *pulRemainder = (uint32_t)(ullDividend % ulDivisor); + } + return ullDividend / ulDivisor; + ~~~ + + However, it does so without ever actually dividing/modulating a 64-bit + value, since such operations are not allowed in all environments. + + @param ullDividend The value to divide. + @param ulDivisor The value to divide by. + @param pulRemainder Populated with the remainder; may be NULL. + + @return The quotient (result of the division). +*/ +uint64_t RedUint64DivMod32( + uint64_t ullDividend, + uint32_t ulDivisor, + uint32_t *pulRemainder) +{ + uint64_t ullQuotient; + uint32_t ulResultRemainder; + + /* Check for divide by zero. + */ + if(ulDivisor == 0U) + { + REDERROR(); + + /* Nonsense value if no asserts. + */ + ullQuotient = UINT64_SUFFIX(0xFFFFFFFFFFFFFBAD); + ulResultRemainder = 0xFFFFFBADU; + } + else if(ullDividend <= UINT32_MAX) + { + uint32_t ulDividend = (uint32_t)ullDividend; + + ullQuotient = ulDividend / ulDivisor; + ulResultRemainder = ulDividend % ulDivisor; + } + else + { + uint32_t ulResultHi; + uint32_t ulResultLo; + uint32_t ulRemainder; + uint8_t bIndex; + uint32_t ulThisDivision; + uint32_t ulMask; + uint8_t ucNextValue; + uint32_t ulInterimHi, ulInterimLo; + uint32_t ulLowDword = (uint32_t)ullDividend; + uint32_t ulHighDword = (uint32_t)(ullDividend >> 32U); + + /* Compute the high part and get the remainder + */ + ulResultHi = ulHighDword / ulDivisor; + ulResultLo = 0U; + ulRemainder = ulHighDword % ulDivisor; + + /* Compute the low part + */ + ulMask = 0xFF000000U; + for(bIndex = 0U; bIndex < sizeof(uint32_t); bIndex++) + { + ucNextValue = (uint8_t)((ulLowDword & ulMask) >> ((sizeof(uint32_t) - 1U - bIndex) * 8U)); + ulInterimHi = ulRemainder >> 24U; + ulInterimLo = (ulRemainder << 8U) | ucNextValue; + ulThisDivision = 0U; + while(ulInterimHi != 0U) + { + uint64_t ullInterim = ((uint64_t)ulInterimHi << 32U) + ulInterimLo; + + ullInterim -= ulDivisor; + ulThisDivision++; + + ulInterimHi = (uint32_t)(ullInterim >> 32U); + ulInterimLo = (uint32_t)ullInterim; + } + ulThisDivision += ulInterimLo / ulDivisor; + ulRemainder = ulInterimLo % ulDivisor; + ulResultLo <<= 8U; + ulResultLo += ulThisDivision; + ulMask >>= 8U; + } + + ullQuotient = ((uint64_t)ulResultHi << 32U) + ulResultLo; + ulResultRemainder = (uint32_t)(ullDividend - (ullQuotient * ulDivisor)); + } + + if(pulRemainder != NULL) + { + *pulRemainder = ulResultRemainder; + } + + return ullQuotient; +} + + +/** @brief Divide a 64-bit value by a 64-bit value, returning the quotient and + the remainder. + + Essentially this function does the following: + + ~~~{.c} + if(pullRemainder != NULL) + { + *pullRemainder = ullDividend % ullDivisor; + } + return ullDividend / ullDivisor; + ~~~ + + However, it does so without ever actually dividing/modulating a 64-bit + value, since such operations are not allowed in all environments. + + @param ullDividend The value to divide. + @param ullDivisor The value to divide by. + @param pullRemainder Populated with the remainder; may be NULL. + + @return The quotient (result of the division). +*/ +uint64_t RedUint64DivMod64( + uint64_t ullDividend, + uint64_t ullDivisor, + uint64_t *pullRemainder) +{ + /* The variables u0, u1, etc. take on only 32-bit values, but they are + declared uint64_t to avoid some compiler warning messages and to avoid + some unnecessary EXTRs that the compiler would put in, to convert + uint64_ts to ints. + */ + uint64_t u0; + uint64_t u1; + uint64_t q0; + uint64_t q1; + uint64_t ullQuotient; + + /* First the procedure takes care of the case in which the divisor is a + 32-bit quantity. There are two subcases: (1) If the left half of the + dividend is less than the divisor, one execution of RedUint64DivMod32() + is all that is required (overflow is not possible). (2) Otherwise it + does two divisions, using the grade school method. + */ + + if((ullDivisor >> 32U) == 0U) + { + if((ullDividend >> 32U) < ullDivisor) + { + /* If ullDividend/ullDivisor cannot overflow, just do one division. + */ + ullQuotient = RedUint64DivMod32(ullDividend, (uint32_t)ullDivisor, NULL); + } + else + { + uint32_t k; + + /* If ullDividend/ullDivisor would overflow: + */ + + /* Break ullDividend up into two halves. + */ + u1 = ullDividend >> 32U; + u0 = ullDividend & 0xFFFFFFFFU; + + /* First quotient digit and first remainder. + */ + q1 = RedUint64DivMod32(u1, (uint32_t)ullDivisor, &k); + + /* 2nd quot. digit. + */ + q0 = RedUint64DivMod32(((uint64_t)k << 32U) + u0, (uint32_t)ullDivisor, NULL); + + ullQuotient = (q1 << 32U) + q0; + } + } + else + { + uint64_t n; + uint64_t v1; + + n = nlz64(ullDivisor); /* 0 <= n <= 31. */ + v1 = (ullDivisor << n) >> 32U; /* Normalize the divisor so its MSB is 1. */ + u1 = ullDividend >> 1U; /* To ensure no overflow. */ + + /* Get quotient from divide unsigned insn. + */ + q1 = RedUint64DivMod32(u1, (uint32_t)v1, NULL); + + q0 = (q1 << n) >> 31U; /* Undo normalization and division of ullDividend by 2. */ + + /* Make q0 correct or too small by 1. + */ + if(q0 != 0U) + { + q0--; + } + + if((ullDividend - (q0 * ullDivisor)) >= ullDivisor) + { + q0++; /* Now q0 is correct. */ + } + + ullQuotient = q0; + } + + if(pullRemainder != NULL) + { + *pullRemainder = ullDividend - (ullQuotient * ullDivisor); + } + + return ullQuotient; +} + + +/** @brief Compute the number of leading zeroes in a 64-bit value. + + @param ullValue The value for which to compute the NLZ. + + @return The number of leading zeroes in @p ullValue. +*/ +static uint32_t nlz64( + uint64_t ullValue) +{ + uint32_t n; + + if(ullValue == 0U) + { + n = 64U; + } + else + { + uint64_t x = ullValue; + + n = 0U; + + if(x <= UINT64_SUFFIX(0x00000000FFFFFFFF)) + { + n += 32U; + x <<= 32U; + } + + if(x <= UINT64_SUFFIX(0x0000FFFFFFFFFFFF)) + { + n += 16U; + x <<= 16U; + } + + if(x <= UINT64_SUFFIX(0x00FFFFFFFFFFFFFF)) + { + n += 8U; + x <<= 8U; + } + + if(x <= UINT64_SUFFIX(0x0FFFFFFFFFFFFFFF)) + { + n += 4U; + x <<= 4U; + } + + if(x <= UINT64_SUFFIX(0x3FFFFFFFFFFFFFFF)) + { + n += 2U; + x <<= 2U; + } + + if(x <= UINT64_SUFFIX(0x7FFFFFFFFFFFFFFF)) + { + n += 1; + } + } + + return n; +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/tests/util/printf.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/tests/util/printf.c new file mode 100644 index 0000000..6df0cf4 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/tests/util/printf.c @@ -0,0 +1,1265 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements functions for printing. + + These functions are intended to be used in portable test code, which cannot + assume the standard I/O functions will be available. Similar to their ANSI + C counterparts, these functions allow formatting text strings and (if the + configuration allows it) outputing formatted text. The latter ability + relies on the RedOsOutputString() OS service function. + + Do *not* use these functions in code which can safely assume the standard + I/O functions are available (e.g., in host tools code). + + Do *not* use these functions from within the file system driver. These + functions use variable arguments and thus are not MISRA-C:2012 compliant. +*/ +#include +#include +#include +#include + + +/** @brief Maximum number of bytes of output supported by RedPrintf(). + + Typically only Datalight code uses these functions, and that could should be + written to respect this limit, so it should not normally be necessary to + adjust this value. +*/ +#define OUTPUT_BUFFER_SIZE 256U + + +typedef enum +{ + PRFMT_UNKNOWN = 0, + PRFMT_CHAR, + PRFMT_ANSISTRING, + PRFMT_SIGNED8BIT, + PRFMT_UNSIGNED8BIT, + PRFMT_SIGNED16BIT, + PRFMT_UNSIGNED16BIT, + PRFMT_SIGNED32BIT, + PRFMT_UNSIGNED32BIT, + PRFMT_SIGNED64BIT, + PRFMT_UNSIGNED64BIT, + PRFMT_HEX8BIT, + PRFMT_HEX16BIT, + PRFMT_HEX32BIT, + PRFMT_HEX64BIT, + PRFMT_POINTER, + PRFMT_DOUBLEPERCENT +} PRINTTYPE; + +typedef struct +{ + PRINTTYPE type; /* The PRFMT_* type found */ + uint32_t ulSpecifierIdx; /* Returns a pointer to the % sign */ + uint32_t ulFillLen; + char cFillChar; + bool fLeftJustified; + bool fHasIllegalType; /* TRUE if an illegal sequence was skipped over */ + bool fHasVarWidth; +} PRINTFORMAT; + + +/* Our output handlers are written for standard fixed width data types. Map + the standard ANSI C data types onto our handlers. Currently this code has + the following requirements: + + 1) shorts must be either 16 or 32 bits + 2) ints must be either 16 or 32 bits + 3) longs must be between 32 or 64 bits + 4) long longs must be 64 bits +*/ +#if (USHRT_MAX == 0xFFFFU) + #define MAPSHORT PRFMT_SIGNED16BIT + #define MAPUSHORT PRFMT_UNSIGNED16BIT + #define MAPHEXUSHORT PRFMT_HEX16BIT +#elif (USHRT_MAX == 0xFFFFFFFFU) + #define MAPSHORT PRFMT_SIGNED32BIT + #define MAPUSHORT PRFMT_UNSIGNED32BIT + #define MAPHEXUSHORT PRFMT_HEX32BIT +#else + #error "The 'short' data type does not have a 16 or 32-bit width" +#endif + +#if (UINT_MAX == 0xFFFFU) + #define MAPINT PRFMT_SIGNED16BIT + #define MAPUINT PRFMT_UNSIGNED16BIT + #define MAPHEXUINT PRFMT_HEX16BIT +#elif (UINT_MAX == 0xFFFFFFFFU) + #define MAPINT PRFMT_SIGNED32BIT + #define MAPUINT PRFMT_UNSIGNED32BIT + #define MAPHEXUINT PRFMT_HEX32BIT +#else + #error "The 'int' data type does not have a 16 or 32-bit width" +#endif + +#if (ULONG_MAX == 0xFFFFFFFFU) + #define MAPLONG PRFMT_SIGNED32BIT + #define MAPULONG PRFMT_UNSIGNED32BIT + #define MAPHEXULONG PRFMT_HEX32BIT +#elif (ULONG_MAX <= UINT64_SUFFIX(0xFFFFFFFFFFFFFFFF)) + /* We've run into unusual environments where "longs" are 40-bits wide. + In this event, map them to 64-bit types so no data is lost. + */ + #define MAPLONG PRFMT_SIGNED64BIT + #define MAPULONG PRFMT_UNSIGNED64BIT + #define MAPHEXULONG PRFMT_HEX64BIT +#else + #error "The 'long' data type is not between 32 and 64 bits wide" +#endif + +#if defined(ULLONG_MAX) && (ULLONG_MAX != UINT64_SUFFIX(0xFFFFFFFFFFFFFFFF)) + #error "The 'long long' data type is not 64 bits wide" +#else + #define MAPLONGLONG PRFMT_SIGNED64BIT + #define MAPULONGLONG PRFMT_UNSIGNED64BIT + #define MAPHEXULONGLONG PRFMT_HEX64BIT +#endif + + +static uint32_t ProcessFormatSegment(char *pcBuffer, uint32_t ulBufferLen, const char *pszFormat, PRINTFORMAT *pFormat, uint32_t *pulSpecifierLen); +static uint32_t ParseFormatSpecifier(char const *pszFormat, PRINTFORMAT *pFormatType); +static PRINTTYPE ParseFormatType(const char *pszFormat, uint32_t *pulTypeLen); +static uint32_t LtoA(char *pcBuffer, uint32_t ulBufferLen, int32_t lNum, uint32_t ulFillLen, char cFill); +static uint32_t LLtoA(char *pcBuffer, uint32_t ulBufferLen, int64_t llNum, uint32_t ulFillLen, char cFill); +static uint32_t ULtoA(char *pcBuffer, uint32_t ulBufferLen, uint32_t ulNum, bool fHex, uint32_t ulFillLen, char cFill); +static uint32_t ULLtoA(char *pcBuffer, uint32_t ulBufferLen, uint64_t ullNum, bool fHex, uint32_t ulFillLen, char cFill); +static uint32_t FinishToA(const char *pcDigits, uint32_t ulDigits, char *pcOutBuffer, uint32_t ulBufferLen, uint32_t ulFillLen, char cFill); + + +/* Digits for the *LtoA() routines. +*/ +static const char gacDigits[] = "0123456789ABCDEF"; + + +#if REDCONF_OUTPUT == 1 +/** @brief Print formatted data with a variable length argument list. + + This function provides a subset of the ANSI C printf() functionality with + several extensions to support fixed size data types. + + See RedVSNPrintf() for the list of supported types. + + @param pszFormat A pointer to the null-terminated format string. + @param ... The variable length argument list. +*/ +void RedPrintf( + const char *pszFormat, + ...) +{ + va_list arglist; + + va_start(arglist, pszFormat); + + RedVPrintf(pszFormat, arglist); + + va_end(arglist); +} + + +/** @brief Print formatted data using a pointer to a variable length argument + list. + + This function provides a subset of the ANSI C vprintf() functionality. + + See RedVSNPrintf() for the list of supported types. + + This function accommodates a maximum output length of #OUTPUT_BUFFER_SIZE. + If this function must truncate the output, and the original string was + \n terminated, the truncated output will be \n terminated as well. + + @param pszFormat A pointer to the null-terminated format string. + @param arglist The variable length argument list. +*/ +void RedVPrintf( + const char *pszFormat, + va_list arglist) +{ + char achBuffer[OUTPUT_BUFFER_SIZE]; + + if(RedVSNPrintf(achBuffer, sizeof(achBuffer), pszFormat, arglist) == -1) + { + /* Ensture the buffer is null terminated. + */ + achBuffer[sizeof(achBuffer) - 1U] = '\0'; + + /* If the original string was \n terminated and the new one is not, due to + truncation, stuff a \n into the new one. + */ + if(pszFormat[RedStrLen(pszFormat) - 1U] == '\n') + { + achBuffer[sizeof(achBuffer) - 2U] = '\n'; + } + } + + RedOsOutputString(achBuffer); +} +#endif /* #if REDCONF_OUTPUT == 1 */ + + +/** @brief Format arguments into a string using a subset of the ANSI C + vsprintf() functionality. + + This function is modeled after the Microsoft _snprint() extension to the + ANSI C sprintf() function, and allows a buffer length to be specified so + that overflow is avoided. + + See RedVSNPrintf() for the list of supported types. + + @param pcBuffer A pointer to the output buffer + @param ulBufferLen The output buffer length + @param pszFormat A pointer to the null terminated format string + @param ... Variable argument list + + @return The length output, or -1 if the buffer filled up. If -1 is + returned, the output buffer may not be null-terminated. +*/ +int32_t RedSNPrintf( + char *pcBuffer, + uint32_t ulBufferLen, + const char *pszFormat, + ...) +{ + int32_t iLen; + va_list arglist; + + va_start(arglist, pszFormat); + + iLen = RedVSNPrintf(pcBuffer, ulBufferLen, pszFormat, arglist); + + va_end(arglist); + + return iLen; +} + + +/** @brief Format arguments into a string using a subset of the ANSI C + vsprintf() functionality. + + This function is modeled after the Microsoft _vsnprint() extension to the + ANSI C vsprintf() function, and requires a buffer length to be specified so + that overflow is avoided. + + The following ANSI C standard formatting codes are supported: + + | Code | Meaning | + | ---- | ---------------------------------- | + | %c | Format a character | + | %s | Format a null-terminated C string | + | %hd | Format a signed short | + | %hu | Format an unsigned short | + | %d | Format a signed integer | + | %u | Format an unsigned integer | + | %ld | Format a signed long | + | %lu | Format an unsigned long | + | %lld | Format a signed long long | + | %llu | Format an unsigned long long | + | %hx | Format a short in hex | + | %x | Format an integer in hex | + | %lx | Format a long in hex | + | %llx | Format a long long in hex | + | %p | Format a pointer (hex value) | + + @note All formatting codes are case-sensitive. + + Fill characters and field widths are supported per the ANSI standard, as is + left justification with the '-' character. + + The only supported fill characters are '0', ' ', and '_'. + + '*' is supported to specify variable length field widths. + + Hexidecimal numbers are always displayed in upper case. Formatting codes + which specifically request upper case (e.g., "%lX") are not supported. + + Unsupported behaviors: + - Precision is not supported. + - Floating point is not supported. + + Errata: + - There is a subtle difference in the return value for this function versus + the Microsoft implementation. In the Microsoft version, if the buffer + exactly fills up, but there is no room for a null-terminator, the return + value will be the length of the buffer. In this code, -1 will be returned + when this happens. + - When using left justified strings, the only supported fill character is a + space, regardless of what may be specified. It is not clear if this is + ANSI standard or just the way the Microsoft function works, but we emulate + the Microsoft behavior. + + @param pcBuffer A pointer to the output buffer. + @param ulBufferLen The output buffer length. + @param pszFormat A pointer to the null terminated ANSI format string. + @param arglist Variable argument list. + + @return The length output, or -1 if the buffer filled up. If -1 is + returned, the output buffer may not be null-terminated. +*/ +int32_t RedVSNPrintf( + char *pcBuffer, + uint32_t ulBufferLen, + const char *pszFormat, + va_list arglist) +{ + uint32_t ulBufIdx = 0U; + uint32_t ulFmtIdx = 0U; + int32_t iLen; + + while((pszFormat[ulFmtIdx] != '\0') && (ulBufIdx < ulBufferLen)) + { + PRINTFORMAT fmt; + uint32_t ulSpecifierLen; + uint32_t ulWidth; + + /* Process the next segment of the format string, outputting + any non-format specifiers, as output buffer space allows, + and return information about the next format specifier. + */ + ulWidth = ProcessFormatSegment(&pcBuffer[ulBufIdx], ulBufferLen - ulBufIdx, &pszFormat[ulFmtIdx], &fmt, &ulSpecifierLen); + if(ulWidth) + { + REDASSERT(ulWidth <= (ulBufferLen - ulBufIdx)); + + ulBufIdx += ulWidth; + } + + /* If no specifier was found, or if the output buffer is + full, we're done -- get out. + */ + if((ulSpecifierLen == 0U) || (ulBufIdx == ulBufferLen)) + { + break; + } + + /* Otherwise, the math should add up for these things... + */ + REDASSERT(&pszFormat[fmt.ulSpecifierIdx] == &pszFormat[ulWidth]); + + /* Point past the specifier, to the next piece of the format string. + */ + ulFmtIdx = ulFmtIdx + fmt.ulSpecifierIdx + ulSpecifierLen; + + if(fmt.fHasVarWidth) + { + int iFillLen = va_arg(arglist, int); + + if(iFillLen >= 0) + { + fmt.ulFillLen = (uint32_t)iFillLen; + } + else + { + /* Bogus fill length. Ignore. + */ + fmt.ulFillLen = 0U; + } + } + + switch(fmt.type) + { + case PRFMT_DOUBLEPERCENT: + { + /* Nothing to do. A single percent has already been output, + and we just finished skipping past the second percent. + */ + break; + } + + /*-----------------> Small int handling <------------------ + * + * Values smaller than "int" will be promoted to "int" by + * the compiler, so we must retrieve them using "int" when + * calling va_arg(). Once we've done that, we immediately + * put the value into the desired data type. + *---------------------------------------------------------*/ + + case PRFMT_CHAR: + { + pcBuffer[ulBufIdx] = (char)va_arg(arglist, int); + ulBufIdx++; + break; + } + case PRFMT_SIGNED8BIT: + { + int8_t num = (int8_t)va_arg(arglist, int); + + ulBufIdx += LtoA(&pcBuffer[ulBufIdx], ulBufferLen - ulBufIdx, num, fmt.ulFillLen, fmt.cFillChar); + break; + } + case PRFMT_UNSIGNED8BIT: + { + uint8_t bNum = (uint8_t)va_arg(arglist, unsigned); + + ulBufIdx += ULtoA(&pcBuffer[ulBufIdx], ulBufferLen - ulBufIdx, bNum, false, fmt.ulFillLen, fmt.cFillChar); + break; + } + case PRFMT_HEX8BIT: + { + uint8_t bNum = (uint8_t)va_arg(arglist, unsigned); + + ulBufIdx += ULtoA(&pcBuffer[ulBufIdx], ulBufferLen - ulBufIdx, bNum, true, fmt.ulFillLen, fmt.cFillChar); + break; + } + case PRFMT_SIGNED16BIT: + { + int16_t num = (int16_t)va_arg(arglist, int); + + ulBufIdx += LtoA(&pcBuffer[ulBufIdx], ulBufferLen - ulBufIdx, num, fmt.ulFillLen, fmt.cFillChar); + break; + } + case PRFMT_UNSIGNED16BIT: + { + uint16_t uNum = (uint16_t)va_arg(arglist, unsigned); + + ulBufIdx += ULtoA(&pcBuffer[ulBufIdx], ulBufferLen - ulBufIdx, uNum, false, fmt.ulFillLen, fmt.cFillChar); + break; + } + case PRFMT_HEX16BIT: + { + uint16_t uNum = (uint16_t)va_arg(arglist, unsigned); + + ulBufIdx += ULtoA(&pcBuffer[ulBufIdx], ulBufferLen - ulBufIdx, uNum, true, fmt.ulFillLen, fmt.cFillChar); + break; + } + case PRFMT_SIGNED32BIT: + { + int32_t lNum = va_arg(arglist, int32_t); + + ulBufIdx += LtoA(&pcBuffer[ulBufIdx], ulBufferLen - ulBufIdx, lNum, fmt.ulFillLen, fmt.cFillChar); + break; + } + case PRFMT_UNSIGNED32BIT: + { + uint32_t ulNum = va_arg(arglist, uint32_t); + + ulBufIdx += ULtoA(&pcBuffer[ulBufIdx], ulBufferLen - ulBufIdx, ulNum, false, fmt.ulFillLen, fmt.cFillChar); + break; + } + case PRFMT_HEX32BIT: + { + uint32_t ulNum = va_arg(arglist, uint32_t); + + ulBufIdx += ULtoA(&pcBuffer[ulBufIdx], ulBufferLen - ulBufIdx, ulNum, true, fmt.ulFillLen, fmt.cFillChar); + break; + } + case PRFMT_SIGNED64BIT: + { + int64_t llNum = va_arg(arglist, int64_t); + + ulBufIdx += LLtoA(&pcBuffer[ulBufIdx], ulBufferLen - ulBufIdx, llNum, fmt.ulFillLen, fmt.cFillChar); + break; + } + case PRFMT_UNSIGNED64BIT: + { + uint64_t ullNum = va_arg(arglist, uint64_t); + + ulBufIdx += ULLtoA(&pcBuffer[ulBufIdx], ulBufferLen - ulBufIdx, ullNum, false, fmt.ulFillLen, fmt.cFillChar); + break; + } + case PRFMT_HEX64BIT: + { + uint64_t ullNum = va_arg(arglist, uint64_t); + + ulBufIdx += ULLtoA(&pcBuffer[ulBufIdx], ulBufferLen - ulBufIdx, ullNum, true, fmt.ulFillLen, fmt.cFillChar); + break; + } + case PRFMT_POINTER: + { + const void *ptr = va_arg(arglist, const void *); + + /* Assert our assumption. + */ + REDASSERT(sizeof(void *) <= 8U); + + /* Format as either a 64-bit or a 32-bit value. + */ + if(sizeof(void *) > 4U) + { + /* Attempt to quiet warnings. + */ + uintptr_t ptrval = (uintptr_t)ptr; + uint64_t ullPtrVal = (uint64_t)ptrval; + + ulBufIdx += ULLtoA(&pcBuffer[ulBufIdx], ulBufferLen - ulBufIdx, ullPtrVal, true, fmt.ulFillLen, fmt.cFillChar); + } + else + { + /* Attempt to quiet warnings. + */ + uintptr_t ptrval = (uintptr_t)ptr; + uint32_t ulPtrVal = (uint32_t)ptrval; + + ulBufIdx += ULtoA(&pcBuffer[ulBufIdx], ulBufferLen - ulBufIdx, ulPtrVal, true, fmt.ulFillLen, fmt.cFillChar); + } + + break; + } + case PRFMT_ANSISTRING: + { + const char *pszArg = va_arg(arglist, const char *); + uint32_t ulArgIdx = 0U; + + if(pszArg == NULL) + { + pszArg = "null"; + } + + if(fmt.ulFillLen > 0U) + { + if(!fmt.fLeftJustified) + { + uint32_t ulLen = RedStrLen(pszArg); + + /* So long as we are not left justifying, fill as many + characters as is necessary to make the string right + justified. + */ + while(((ulBufferLen - ulBufIdx) > 0U) && (fmt.ulFillLen > ulLen)) + { + pcBuffer[ulBufIdx] = fmt.cFillChar; + ulBufIdx++; + fmt.ulFillLen--; + } + } + + /* Move as many characters as we have space for into the + output buffer. + */ + while(((ulBufferLen - ulBufIdx) > 0U) && (pszArg[ulArgIdx] != '\0')) + { + pcBuffer[ulBufIdx] = pszArg[ulArgIdx]; + ulBufIdx++; + ulArgIdx++; + if(fmt.ulFillLen > 0U) + { + fmt.ulFillLen--; + } + } + + /* If there is any space left to fill, do it (the string + must have been left justified). + */ + while(((ulBufferLen - ulBufIdx) > 0U) && (fmt.ulFillLen > 0U)) + { + /* This is NOT a typo -- when using left justified + strings, spaces are the only allowed fill character. + See the errata. + */ + pcBuffer[ulBufIdx] = ' '; + ulBufIdx++; + fmt.ulFillLen--; + } + } + else + { + /* No fill characters, just move up to as many + characters as we have space for in the output + buffer. + */ + while(((ulBufferLen - ulBufIdx) > 0U) && (pszArg[ulArgIdx] != '\0')) + { + pcBuffer[ulBufIdx] = pszArg[ulArgIdx]; + ulBufIdx++; + ulArgIdx++; + } + } + break; + } + default: + { + REDERROR(); + break; + } + } + } + + /* If there is space, tack on a null and return the output length + processed, not including the null. + */ + if(ulBufIdx < ulBufferLen) + { + pcBuffer[ulBufIdx] = '\0'; + iLen = (int32_t)ulBufIdx; + } + else + { + /* Not enough space, just return -1, with no null termination + */ + iLen = -1; + } + + return iLen; +} + + +/** @brief Process the next segment of the format string, outputting any + non-format specifiers, as output buffer space allows, and return + information about the next format specifier. + + @note If the returned value is the same as the supplied @p ulBufferLen, + the output buffer will not be null-terminated. In all other cases, + the result will be null-terminated. The returned length will never + include the null in the count. + + @param pcBuffer The output buffer. + @param ulBufferLen The output buffer length. + @param pszFormat The format string to process. + @param pFormat The PRINTFORMAT structure to fill. + @param pulSpecifierLen Returns the length of any format specifier string, + or zero if no specifier was found. + + @return The count of characters from pszFormatt which were processed and + copied to pcBuffer. + - If zero is returned and *pulSpecifierLen is non-zero, then + a format specifier string was found at the start of pszFmt. + - If non-zero is returned and *pulSpecifierLen is zero, then + no format specifier string was found, and the entire pszFmt + string was copied to pBuffer (or as much as will fit). +*/ +static uint32_t ProcessFormatSegment( + char *pcBuffer, + uint32_t ulBufferLen, + const char *pszFormat, + PRINTFORMAT *pFormat, + uint32_t *pulSpecifierLen) +{ + uint32_t ulWidth = 0U; + + /* Find the next format specifier string, and information about it. + */ + *pulSpecifierLen = ParseFormatSpecifier(pszFormat, pFormat); + + if(*pulSpecifierLen == 0U) + { + /* If no specifier was found at all, then simply output the full length + of the string, or as much as will fit. + */ + ulWidth = REDMIN(ulBufferLen, RedStrLen(pszFormat)); + + RedMemCpy(pcBuffer, pszFormat, ulWidth); + } + else + { + /* If we encountered a double percent, skip past one of them so it is + copied into the output buffer. + */ + if(pFormat->type == PRFMT_DOUBLEPERCENT) + { + pFormat->ulSpecifierIdx++; + + /* A double percent specifier always has a length of two. Since + we're processing one of those percent signs, reduce the length + to one. Assert it so. + */ + REDASSERT(*pulSpecifierLen == 2U); + + (*pulSpecifierLen)--; + } + + /* So long as the specifier is not the very first thing in the format + string... + */ + if(pFormat->ulSpecifierIdx != 0U) + { + /* A specifier was found, but there is other data preceding it. + Copy as much as allowed to the output buffer. + */ + ulWidth = REDMIN(ulBufferLen, pFormat->ulSpecifierIdx); + + RedMemCpy(pcBuffer, pszFormat, ulWidth); + } + } + + /* If there is room in the output buffer, null-terminate whatever is there. + But note that the returned length never includes the null. + */ + if(ulWidth < ulBufferLen) + { + pcBuffer[ulWidth] = 0U; + } + + return ulWidth; +} + + +/** @brief Parse the specified format string for a valid RedVSNPrintf() format + sequence, and return information about it. + + @param pszFormat The format string to process. + @param pFormatType The PRINTFORMAT structure to fill. The data is only + valid if a non-zero length is returned. + + @return The length of the full format specifier string, starting at + pFormat->ulSpecifierIdx. Returns zero if a valid specifier was + not found. +*/ +static uint32_t ParseFormatSpecifier( + char const *pszFormat, + PRINTFORMAT *pFormatType) +{ + bool fContainsIllegalSequence = false; + uint32_t ulLen = 0U; + uint32_t ulIdx = 0U; + + while(pszFormat[ulIdx] != '\0') + { + uint32_t ulTypeLen; + + /* general output + */ + if(pszFormat[ulIdx] != '%') + { + ulIdx++; + } + else + { + RedMemSet(pFormatType, 0U, sizeof(*pFormatType)); + + /* Record the location of the start of the format sequence + */ + pFormatType->ulSpecifierIdx = ulIdx; + ulIdx++; + + if(pszFormat[ulIdx] == '-') + { + pFormatType->fLeftJustified = true; + ulIdx++; + } + + if((pszFormat[ulIdx] == '0') || (pszFormat[ulIdx] == '_')) + { + pFormatType->cFillChar = pszFormat[ulIdx]; + ulIdx++; + } + else + { + pFormatType->cFillChar = ' '; + } + + if(pszFormat[ulIdx] == '*') + { + pFormatType->fHasVarWidth = true; + ulIdx++; + } + else if(ISDIGIT(pszFormat[ulIdx])) + { + pFormatType->ulFillLen = (uint32_t)RedAtoI(&pszFormat[ulIdx]); + while(ISDIGIT(pszFormat[ulIdx])) + { + ulIdx++; + } + } + else + { + /* No fill length. + */ + } + + pFormatType->type = ParseFormatType(&pszFormat[ulIdx], &ulTypeLen); + if(pFormatType->type != PRFMT_UNKNOWN) + { + /* Even though we are returning successfully, keep track of + whether an illegal sequence was encountered and skipped. + */ + pFormatType->fHasIllegalType = fContainsIllegalSequence; + + ulLen = (ulIdx - pFormatType->ulSpecifierIdx) + ulTypeLen; + break; + } + + /* In the case of an unrecognized type string, simply ignore + it entirely. Reset the pointer to the position following + the percent sign, so it is not found again. + */ + fContainsIllegalSequence = false; + ulIdx = pFormatType->ulSpecifierIdx + 1U; + } + } + + return ulLen; +} + + +/** @brief Parse a RedPrintf() format type string to determine the proper data + type. + + @param pszFormat The format string to process. This must be a pointer to + the character following any width or justification + characters. + @param pulTypeLen The location in which to store the type length. The + value will be 0 if PRFMT_UNKNOWN is returned. + + @return Rhe PRFMT_* type value, or PRFMT_UNKNOWN if the type is not + recognized. +*/ +static PRINTTYPE ParseFormatType( + const char *pszFormat, + uint32_t *pulTypeLen) +{ + PRINTTYPE fmtType = PRFMT_UNKNOWN; + uint32_t ulIdx = 0U; + + switch(pszFormat[ulIdx]) + { + case '%': + fmtType = PRFMT_DOUBLEPERCENT; + break; + case 'c': + fmtType = PRFMT_CHAR; + break; + case 's': + fmtType = PRFMT_ANSISTRING; + break; + case 'p': + fmtType = PRFMT_POINTER; + break; + case 'd': + fmtType = MAPINT; + break; + case 'u': + fmtType = MAPUINT; + break; + case 'x': + fmtType = MAPHEXUINT; + break; + case 'h': + { + ulIdx++; + switch(pszFormat[ulIdx]) + { + case 'd': + fmtType = MAPSHORT; + break; + case 'u': + fmtType = MAPUSHORT; + break; + case 'x': + fmtType = MAPHEXUSHORT; + break; + default: + break; + } + break; + } + case 'l': + { + ulIdx++; + switch(pszFormat[ulIdx]) + { + case 'd': + fmtType = MAPLONG; + break; + case 'u': + fmtType = MAPULONG; + break; + case 'x': + fmtType = MAPHEXULONG; + break; + case 'l': + { + ulIdx++; + switch(pszFormat[ulIdx]) + { + case 'd': + fmtType = MAPLONGLONG; + break; + case 'u': + fmtType = MAPULONGLONG; + break; + case 'x': + case 'X': + fmtType = MAPHEXULONGLONG; + break; + default: + break; + } + break; + } + default: + break; + } + break; + } + default: + break; + } + + if(fmtType != PRFMT_UNKNOWN) + { + *pulTypeLen = ulIdx + 1U; + } + else + { + *pulTypeLen = 0U; + } + + return fmtType; +} + + +/** @brief Format a signed 32-bit integer as a base 10 ASCII string. + + @note If the output buffer length is exhausted, the result will *not* be + null-terminated. + + @note If the @p ulFillLen value is greater than or equal to the buffer + length, the result will not be null-terminated, even if the + formatted portion of the data is shorter than the buffer length. + + @param pcBuffer The output buffer + @param ulBufferLen A pointer to the output buffer length + @param lNum The 32-bit signed number to convert + @param ulFillLen The fill length, if any + @param cFill The fill character to use + + @return The length of the string. +*/ +static uint32_t LtoA( + char *pcBuffer, + uint32_t ulBufferLen, + int32_t lNum, + uint32_t ulFillLen, + char cFill) +{ + uint32_t ulLen; + + if(pcBuffer == NULL) + { + REDERROR(); + ulLen = 0U; + } + else + { + char ach[12U]; /* big enough for a int32_t in base 10 */ + uint32_t ulDigits = 0U; + uint32_t ulNum; + bool fSign; + + if(lNum < 0) + { + fSign = true; + ulNum = (uint32_t)-lNum; + } + else + { + fSign = false; + ulNum = (uint32_t)lNum; + } + + do + { + ach[ulDigits] = gacDigits[ulNum % 10U]; + ulNum = ulNum / 10U; + ulDigits++; + } + while(ulNum); + + if(fSign) + { + ach[ulDigits] = '-'; + ulDigits++; + } + + ulLen = FinishToA(ach, ulDigits, pcBuffer, ulBufferLen, ulFillLen, cFill); + } + + return ulLen; +} + + +/** @brief Format a signed 64-bit integer as a base 10 ASCII string. + + @note If the output buffer length is exhausted, the result will *not* be + null-terminated. + + @note If the @p ulFillLen value is greater than or equal to the buffer + length, the result will not be null-terminated, even if the + formatted portion of the data is shorter than the buffer length. + + @param pcBuffer The output buffer + @param ulBufferLen A pointer to the output buffer length + @param llNum The 64-bit signed number to convert + @param ulFillLen The fill length, if any + @param cFill The fill character to use + + @return The length of the string. +*/ +static uint32_t LLtoA( + char *pcBuffer, + uint32_t ulBufferLen, + int64_t llNum, + uint32_t ulFillLen, + char cFill) +{ + uint32_t ulLen; + + if(pcBuffer == NULL) + { + REDERROR(); + ulLen = 0U; + } + else + { + char ach[12U]; /* big enough for a int32_t in base 10 */ + uint32_t ulDigits = 0U; + uint64_t ullNum; + bool fSign; + + if(llNum < 0) + { + fSign = true; + ullNum = (uint64_t)-llNum; + } + else + { + fSign = false; + ullNum = (uint64_t)llNum; + } + + /* Not allowed to assume that 64-bit division is OK, so use a + software division routine. + */ + do + { + uint64_t ullQuotient; + uint32_t ulRemainder; + + /* Note: RedUint64DivMod32() is smart enough to use normal division + once ullNumericVal <= UINT32_MAX. + */ + ullQuotient = RedUint64DivMod32(ullNum, 10U, &ulRemainder); + + ach[ulDigits] = gacDigits[ulRemainder]; + ullNum = ullQuotient; + ulDigits++; + } + while(ullNum > 0U); + + if(fSign) + { + ach[ulDigits] = '-'; + ulDigits++; + } + + ulLen = FinishToA(ach, ulDigits, pcBuffer, ulBufferLen, ulFillLen, cFill); + } + + return ulLen; +} + + +/** @brief Format an unsigned 32-bit integer as an ASCII string as decimal or + hex. + + @note If the output buffer length is exhausted, the result will *not* be + null-terminated. + + @param pcBuffer The output buffer + @param ulBufferLen The output buffer length + @param ulNum The 32-bit unsigned number to convert + @param fHex If true, format as hex; if false, decimal. + @param ulFillLen The fill length, if any + @param cFill The fill character to use + + @return The length of the string. +*/ +static uint32_t ULtoA( + char *pcBuffer, + uint32_t ulBufferLen, + uint32_t ulNum, + bool fHex, + uint32_t ulFillLen, + char cFill) +{ + uint32_t ulLen; + + if(pcBuffer == NULL) + { + REDERROR(); + ulLen = 0U; + } + else + { + char ach[11U]; /* Big enough for a uint32_t in radix 10 */ + uint32_t ulDigits = 0U; + uint32_t ulNumericVal = ulNum; + uint32_t ulRadix = fHex ? 16U : 10U; + + do + { + ach[ulDigits] = gacDigits[ulNumericVal % ulRadix]; + ulNumericVal = ulNumericVal / ulRadix; + ulDigits++; + } + while(ulNumericVal > 0U); + + ulLen = FinishToA(ach, ulDigits, pcBuffer, ulBufferLen, ulFillLen, cFill); + } + + return ulLen; +} + + +/** @brief Format an unsigned 64-bit integer as an ASCII string as decimal or + hex. + + @note If the output buffer length is exhausted, the result will *not* be + null-terminated. + + @param pcBuffer The output buffer. + @param ulBufferLen The output buffer length. + @param ullNum The unsigned 64-bit number to convert. + @param fHex If true, format as hex; if false, decimal. + @param ulFillLen The fill length, if any. + @param cFill The fill character to use. + + @return The length of the string. +*/ +static uint32_t ULLtoA( + char *pcBuffer, + uint32_t ulBufferLen, + uint64_t ullNum, + bool fHex, + uint32_t ulFillLen, + char cFill) +{ + uint32_t ulLen; + + if(pcBuffer == NULL) + { + REDERROR(); + ulLen = 0U; + } + else + { + + char ach[21U]; /* Big enough for a uint64_t in radix 10 */ + uint32_t ulDigits = 0U; + uint64_t ullNumericVal = ullNum; + + if(fHex) + { + /* We can figure out the digits using bit operations. + */ + do + { + ach[ulDigits] = gacDigits[ullNumericVal & 15U]; + ullNumericVal >>= 4U; + ulDigits++; + } + while(ullNumericVal > 0U); + } + else + { + /* Not allowed to assume that 64-bit division is OK, so use a + software division routine. + */ + do + { + uint64_t ullQuotient; + uint32_t ulRemainder; + + /* Note: RedUint64DivMod32() is smart enough to use normal division + once ullNumericVal <= UINT32_MAX. + */ + ullQuotient = RedUint64DivMod32(ullNumericVal, 10U, &ulRemainder); + + ach[ulDigits] = gacDigits[ulRemainder]; + ullNumericVal = ullQuotient; + ulDigits++; + } + while(ullNumericVal > 0U); + } + + ulLen = FinishToA(ach, ulDigits, pcBuffer, ulBufferLen, ulFillLen, cFill); + } + + return ulLen; +} + + +/** @brief Finish converting a number into an ASCII string representing that + number. + + This helper function contains common logic that needs to run at the end of + all the "toA" functions. It adds the fill character and reverses the digits + string. + + @param pcDigits The digits (and sign) for the ASCII string, in reverse + order as they were computed. + @param ulDigits The number of digit characters. + @param pcOutBuffer The output buffer. + @param ulBufferLen The length of the output buffer. + @param ulFillLen The fill length. If the number string is shorter than + this, the remaining bytes are filled with @p cFill. + @param cFill The fill character. + + @return The length of @p pcOutBuffer. +*/ +static uint32_t FinishToA( + const char *pcDigits, + uint32_t ulDigits, + char *pcOutBuffer, + uint32_t ulBufferLen, + uint32_t ulFillLen, + char cFill) +{ + uint32_t ulIdx = 0U; + uint32_t ulDigitIdx = ulDigits; + + /* user may have asked for a fill char + */ + if(ulFillLen > ulDigits) + { + uint32_t ulFillRem = ulFillLen - ulDigits; + + while((ulFillRem > 0U) && (ulIdx < ulBufferLen)) + { + pcOutBuffer[ulIdx] = cFill; + ulIdx++; + ulFillRem--; + } + } + + /* reverse the string + */ + while((ulDigitIdx > 0) && (ulIdx < ulBufferLen)) + { + ulDigitIdx--; + pcOutBuffer[ulIdx] = pcDigits[ulDigitIdx]; + ulIdx++; + } + + if(ulIdx < ulBufferLen) + { + pcOutBuffer[ulIdx] = '\0'; + } + + return ulIdx; +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/tests/util/rand.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/tests/util/rand.c new file mode 100644 index 0000000..6dd4430 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/tests/util/rand.c @@ -0,0 +1,159 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements a random number generator. +*/ +#include +#include + + +/* This is the global seed used by the random number generator when the caller + has not provided a seed to either the RedRand32() or RedRand64() functions. +*/ +static uint64_t ullGlobalRandomNumberSeed; + +/* Whether the above seed has been initialized. +*/ +static bool fGlobalSeedInited; + + +/** @brief Set the global seed used by the random number generator. + + The global seed gets used when RedRand64() or RedRand32() are called with + a NULL seed argument. + + @param ullSeed The value to use as the global RNG seed. +*/ +void RedRandSeed( + uint64_t ullSeed) +{ + ullGlobalRandomNumberSeed = ullSeed; + fGlobalSeedInited = true; +} + + +/** @brief Generate a 64-bit pseudo-random number. + + The period of this random number generator is 2^64 (1.8 x 1019). These + parameters are the same as the default one-stream SPRNG lcg64 generator and + it satisfies the requirements for a maximal period. + + The tempering value is used and an AND mask and is specifically selected to + favor the distribution of lower bits. + + @param pullSeed A pointer to the seed to use. Set this value to NULL to + use the internal global seed value. + + @return A pseudo-random number in the range [0, UINT64_MAX]. +*/ +uint64_t RedRand64( + uint64_t *pullSeed) +{ + const uint64_t ullA = UINT64_SUFFIX(2862933555777941757); + const uint64_t ullC = UINT64_SUFFIX(3037000493); + const uint64_t ullT = UINT64_SUFFIX(4921441182957829599); + uint64_t ullN; + uint64_t *pullSeedPtr; + uint64_t ullLocalSeed; + + if(pullSeed != NULL) + { + ullLocalSeed = *pullSeed; + pullSeedPtr = pullSeed; + } + else + { + if(!fGlobalSeedInited) + { + /* Unfortunately, the Reliance Edge OS services don't give us much + to work with to initialize the global seed. There is no entropy + abstraction, no tick count abstraction, and the timestamp + abstraction uses an opaque type which is not guaranteed to be an + integer. The best we can do is use the RTC. + + Tests using the RNG should be supplying a seed anyway, for + reproducibility. + */ + RedRandSeed((uint64_t)RedOsClockGetTime()); + } + + ullLocalSeed = ullGlobalRandomNumberSeed; + pullSeedPtr = &ullGlobalRandomNumberSeed; + } + + ullN = (ullLocalSeed * ullA) + ullC; + + *pullSeedPtr = ullN; + + /* The linear congruential generator used above produces good psuedo-random + 64-bit number sequences, however, as with any LCG, the period of the + lower order bits is much shorter resulting in alternately odd/even pairs + in bit zero. + + The result of the LGC above is tempered below with a series of XOR and + shift operations to produce a more acceptable equidistribution of bits + throughout the 64-bit range. + */ + ullN ^= (ullN >> 21U) & ullT; + ullN ^= (ullN >> 43U) & ullT; + ullN ^= (ullN << 23U) & ~ullT; + ullN ^= (ullN << 31U) & ~ullT; + + return ullN; +} + + +/** @brief Generate a 32-bit pseudo-random number. + + @note The 32-bit random number generator internally uses the 64-bit random + number generator, returning the low 32-bits of the pseudo-random + 64-bit value. + + @param pulSeed A pointer to the seed to use. Set this value to NULL to use + the internal global seed value. + + @return A pseudo-random number in the range [0, UINT32_MAX]. +*/ +uint32_t RedRand32( + uint32_t *pulSeed) +{ + uint64_t ullN; + + if(pulSeed != NULL) + { + uint64_t ullLocalSeed; + + ullLocalSeed = *pulSeed; + ullN = RedRand64(&ullLocalSeed); + *pulSeed = (uint32_t)ullLocalSeed; + } + else + { + ullN = RedRand64(NULL); + } + + return (uint32_t)ullN; +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/toolcmn/getopt.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/toolcmn/getopt.c new file mode 100644 index 0000000..2a8f001 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/toolcmn/getopt.c @@ -0,0 +1,559 @@ +/* + * Copyright (c) 2002 Todd C. Miller + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Sponsored in part by the Defense Advanced Research Projects + * Agency (DARPA) and Air Force Research Laboratory, Air Force + * Materiel Command, USAF, under agreement number F39502-99-1-0512. + */ +/*- + * Copyright (c) 2000 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Dieter Baron and Thomas Klausner. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +/** @file + @brief Implementations of getopt() and getopt_long() work-alike functions. + + This code was taken from FreeBSD and slightly modified, mostly to rename + symbols with external linkage to avoid naming conflicts in systems where + there are real getopt()/getopt_long() implementations, and for portability. +*/ +#include +#include +#include + +#include +#include +#include +#include + + +int32_t red_opterr = 1; /* if error message should be printed */ +int32_t red_optind = 1; /* index into parent argv vector */ +int32_t red_optopt = '?'; /* character checked for validity */ +int32_t red_optreset; /* reset RedGetopt */ +const char *red_optarg; /* argument associated with option */ + +#define PRINT_ERROR ((red_opterr) && (*options != ':')) + +#define FLAG_PERMUTE 0x01 /* permute non-options to the end of argv */ +#define FLAG_ALLARGS 0x02 /* treat non-options as args to option "-1" */ +#define FLAG_LONGONLY 0x04 /* operate as RedGetoptLongOnly */ + +/* return values */ +#define BADCH (int)'?' +#define BADARG ((*options == ':') ? (int)':' : (int)'?') +#define INORDER (int)1 + +#define EMSG "" + +#define NO_PREFIX (-1) +#define D_PREFIX 0 +#define DD_PREFIX 1 +#define W_PREFIX 2 + +static int gcd(int a, int b); +static void permute_args(int panonopt_start, int panonopt_end, int opt_end, char * const *nargv); +static int parse_long_options(char * const *nargv, const char *options, const REDOPTION *long_options, int32_t *idx, int short_too, int flags); +static int getopt_internal(int nargc, char * const *nargv, const char *options, const REDOPTION *long_options, int32_t *idx, int flags); + +static const char *place = EMSG; /* option letter processing */ + +/* XXX: set red_optreset to 1 rather than these two */ +static int nonopt_start = -1; /* first non option argument (for permute) */ +static int nonopt_end = -1; /* first option after non options (for permute) */ + +/* Error messages */ +static const char recargchar[] = "option requires an argument -- %c\n"; +static const char illoptchar[] = "illegal option -- %c\n"; /* From P1003.2 */ +static int dash_prefix = NO_PREFIX; +static const char gnuoptchar[] = "invalid option -- %c\n"; + +static const char recargstring[] = "option `%s%s' requires an argument\n"; +static const char ambig[] = "option `%s%s' is ambiguous\n"; +static const char noarg[] = "option `%s%s' doesn't allow an argument\n"; +static const char illoptstring[] = "unrecognized option `%s%s'\n"; + +/* + * Compute the greatest common divisor of a and b. + */ +static int +gcd(int a, int b) +{ + int c; + + c = a % b; + while (c != 0) { + a = b; + b = c; + c = a % b; + } + + return (b); +} + +/* + * Exchange the block from nonopt_start to nonopt_end with the block + * from nonopt_end to opt_end (keeping the same order of arguments + * in each block). + */ +static void +permute_args(int panonopt_start, int panonopt_end, int opt_end, + char * const *nargv) +{ + int cstart, cyclelen, i, j, ncycle, nnonopts, nopts, pos; + char *swap; + + /* + * compute lengths of blocks and number and size of cycles + */ + nnonopts = panonopt_end - panonopt_start; + nopts = opt_end - panonopt_end; + ncycle = gcd(nnonopts, nopts); + cyclelen = (opt_end - panonopt_start) / ncycle; + + for (i = 0; i < ncycle; i++) { + cstart = panonopt_end+i; + pos = cstart; + for (j = 0; j < cyclelen; j++) { + if (pos >= panonopt_end) + pos -= nnonopts; + else + pos += nopts; + swap = nargv[pos]; + ((char **) nargv)[pos] = nargv[cstart]; + ((char **)nargv)[cstart] = swap; + } + } +} + +/* + * parse_long_options -- + * Parse long options in argc/argv argument vector. + * Returns -1 if short_too is set and the option does not match long_options. + */ +static int +parse_long_options(char * const *nargv, const char *options, + const REDOPTION *long_options, int32_t *idx, int short_too, int flags) +{ + const char *current_argv, *has_equal, *current_dash; + size_t current_argv_len; + int i, match, exact_match, second_partial_match; + + current_argv = place; + switch (dash_prefix) { + case D_PREFIX: + current_dash = "-"; + break; + case DD_PREFIX: + current_dash = "--"; + break; + case W_PREFIX: + current_dash = "-W "; + break; + default: + current_dash = ""; + break; + } + match = -1; + exact_match = 0; + second_partial_match = 0; + + red_optind++; + + if ((has_equal = strchr(current_argv, '=')) != NULL) { + /* argument found (--option=arg) */ + current_argv_len = has_equal - current_argv; + has_equal++; + } else + current_argv_len = strlen(current_argv); + + for (i = 0; long_options[i].name; i++) { + /* find matching long option */ + if (strncmp(current_argv, long_options[i].name, + current_argv_len)) + continue; + + if (strlen(long_options[i].name) == current_argv_len) { + /* exact match */ + match = i; + exact_match = 1; + break; + } + /* + * If this is a known short option, don't allow + * a partial match of a single character. + */ + if (short_too && current_argv_len == 1) + continue; + + if (match == -1) /* first partial match */ + match = i; + else if ((flags & FLAG_LONGONLY) || + long_options[i].has_arg != + long_options[match].has_arg || + long_options[i].flag != long_options[match].flag || + long_options[i].val != long_options[match].val) + second_partial_match = 1; + } + if (!exact_match && second_partial_match) { + /* ambiguous abbreviation */ + if (PRINT_ERROR) + fprintf(stderr, + ambig, + current_dash, + current_argv); + red_optopt = 0; + return (BADCH); + } + if (match != -1) { /* option found */ + if (long_options[match].has_arg == red_no_argument + && has_equal) { + if (PRINT_ERROR) + fprintf(stderr, + noarg, + current_dash, + current_argv); + /* + * XXX: GNU sets red_optopt to val regardless of flag + */ + if (long_options[match].flag == NULL) + red_optopt = long_options[match].val; + else + red_optopt = 0; + return (BADCH); + } + if (long_options[match].has_arg == red_required_argument || + long_options[match].has_arg == red_optional_argument) { + if (has_equal) + red_optarg = has_equal; + else if (long_options[match].has_arg == + red_required_argument) { + /* + * optional argument doesn't use next nargv + */ + red_optarg = nargv[red_optind++]; + } + } + if ((long_options[match].has_arg == red_required_argument) + && (red_optarg == NULL)) { + /* + * Missing argument; leading ':' indicates no error + * should be generated. + */ + if (PRINT_ERROR) + fprintf(stderr, + recargstring, + current_dash, + current_argv); + /* + * XXX: GNU sets red_optopt to val regardless of flag + */ + if (long_options[match].flag == NULL) + red_optopt = long_options[match].val; + else + red_optopt = 0; + --red_optind; + return (BADARG); + } + } else { /* unknown option */ + if (short_too) { + --red_optind; + return (-1); + } + if (PRINT_ERROR) + fprintf(stderr, + illoptstring, + current_dash, + current_argv); + red_optopt = 0; + return (BADCH); + } + if (idx) + *idx = match; + if (long_options[match].flag) { + *long_options[match].flag = long_options[match].val; + return (0); + } else + return (long_options[match].val); +} + +/* + * getopt_internal -- + * Parse argc/argv argument vector. Called by user level routines. + */ +static int +getopt_internal(int nargc, char * const *nargv, const char *options, + const REDOPTION *long_options, int32_t *idx, int flags) +{ + char *oli; /* option letter list index */ + int optchar, short_too; + + if (options == NULL) + return (-1); + + /* + * XXX Some GNU programs (like cvs) set red_optind to 0 instead of + * XXX using red_optreset. Work around this braindamage. + */ + if (red_optind == 0) + red_optind = red_optreset = 1; + + /* + * Disable GNU extensions if options string begins with a '+'. + */ + if (*options == '-') + flags |= FLAG_ALLARGS; + else if (*options == '+') + flags &= ~FLAG_PERMUTE; + if (*options == '+' || *options == '-') + options++; + + red_optarg = NULL; + if (red_optreset) + nonopt_start = nonopt_end = -1; +start: + if (red_optreset || !*place) { /* update scanning pointer */ + red_optreset = 0; + if (red_optind >= nargc) { /* end of argument vector */ + place = EMSG; + if (nonopt_end != -1) { + /* do permutation, if we have to */ + permute_args(nonopt_start, nonopt_end, + red_optind, nargv); + red_optind -= nonopt_end - nonopt_start; + } + else if (nonopt_start != -1) { + /* + * If we skipped non-options, set red_optind + * to the first of them. + */ + red_optind = nonopt_start; + } + nonopt_start = nonopt_end = -1; + return (-1); + } + if (*(place = nargv[red_optind]) != '-' || place[1] == '\0') { + place = EMSG; /* found non-option */ + if (flags & FLAG_ALLARGS) { + /* + * GNU extension: + * return non-option as argument to option 1 + */ + red_optarg = nargv[red_optind++]; + return (INORDER); + } + if (!(flags & FLAG_PERMUTE)) { + /* + * If no permutation wanted, stop parsing + * at first non-option. + */ + return (-1); + } + /* do permutation */ + if (nonopt_start == -1) + nonopt_start = red_optind; + else if (nonopt_end != -1) { + permute_args(nonopt_start, nonopt_end, + red_optind, nargv); + nonopt_start = red_optind - + (nonopt_end - nonopt_start); + nonopt_end = -1; + } + red_optind++; + /* process next argument */ + goto start; + } + if (nonopt_start != -1 && nonopt_end == -1) + nonopt_end = red_optind; + + /* + * If we have "-" do nothing, if "--" we are done. + */ + if (place[1] != '\0' && *++place == '-' && place[1] == '\0') { + red_optind++; + place = EMSG; + /* + * We found an option (--), so if we skipped + * non-options, we have to permute. + */ + if (nonopt_end != -1) { + permute_args(nonopt_start, nonopt_end, + red_optind, nargv); + red_optind -= nonopt_end - nonopt_start; + } + nonopt_start = nonopt_end = -1; + return (-1); + } + } + + /* + * Check long options if: + * 1) we were passed some + * 2) the arg is not just "-" + * 3) either the arg starts with -- we are RedGetoptLongOnly() + */ + if (long_options != NULL && place != nargv[red_optind] && + (*place == '-' || (flags & FLAG_LONGONLY))) { + short_too = 0; + dash_prefix = D_PREFIX; + if (*place == '-') { + place++; /* --foo long option */ + dash_prefix = DD_PREFIX; + } else if (*place != ':' && strchr(options, *place) != NULL) + short_too = 1; /* could be short option too */ + + optchar = parse_long_options(nargv, options, long_options, + idx, short_too, flags); + if (optchar != -1) { + place = EMSG; + return (optchar); + } + } + + if ((optchar = (int)*place++) == (int)':' || + (optchar == (int)'-' && *place != '\0') || + (oli = strchr(options, optchar)) == NULL) { + /* + * If the user specified "-" and '-' isn't listed in + * options, return -1 (non-option) as per POSIX. + * Otherwise, it is an unknown option character (or ':'). + */ + if (optchar == (int)'-' && *place == '\0') + return (-1); + if (!*place) + ++red_optind; + if (PRINT_ERROR) + fprintf(stderr, gnuoptchar, optchar); + red_optopt = optchar; + return (BADCH); + } + if (long_options != NULL && optchar == 'W' && oli[1] == ';') { + /* -W long-option */ + if (*place) /* no space */ + /* NOTHING */; + else if (++red_optind >= nargc) { /* no arg */ + place = EMSG; + if (PRINT_ERROR) + fprintf(stderr, recargchar, optchar); + red_optopt = optchar; + return (BADARG); + } else /* white space */ + place = nargv[red_optind]; + dash_prefix = W_PREFIX; + optchar = parse_long_options(nargv, options, long_options, + idx, 0, flags); + place = EMSG; + return (optchar); + } + if (*++oli != ':') { /* doesn't take argument */ + if (!*place) + ++red_optind; + } else { /* takes (optional) argument */ + red_optarg = NULL; + if (*place) /* no white space */ + red_optarg = place; + else if (oli[1] != ':') { /* arg not optional */ + if (++red_optind >= nargc) { /* no arg */ + place = EMSG; + if (PRINT_ERROR) + fprintf(stderr, recargchar, optchar); + red_optopt = optchar; + return (BADARG); + } else + red_optarg = nargv[red_optind]; + } + place = EMSG; + ++red_optind; + } + /* dump back option letter */ + return (optchar); +} + + +/** @brief Get option character from command line argument list. + + For more details, consult the getopt() man pages, since this function is + generally similar. + + @param nargc Number of arguments (argc passed into main()). + @param nargv Argument vector (argv passed into main()). + @param options String of option characters. + + @return The next known option character in @p options. If a character not + found in @p options is found or if an option is missing an argument, + it returns '?'. Returns -1 when the argument list is exhausted. +*/ +int32_t RedGetopt( + int32_t nargc, + char * const *nargv, + const char *options) +{ + return getopt_internal(nargc, nargv, options, NULL, NULL, FLAG_PERMUTE); +} + + +/** @brief Get long options from command line argument list. + + For more details, consult the getopt_long() man pages, since this function + is generally similar. + + @param nargc Number of arguments (argc passed into main()). + @param nargv Argument vector (argv passed into main()). + @param options String of option characters. + @param long_options The long options; the last element of this array must be + filled with zeroes. + @param idx If non-NULL, then populated with the index of the long + option relative to @p long_options. + + @return If the flag field in REDOPTION is NULL, returns the value specified + in the val field, which is usually just the corresponding short + option. If flag is non-NULL, returns zero and stores val in the + location pointed to by flag. Returns ':' if an option was missing + its argument, '?' for an unknown option, and -1 when the argument + list is exhausted. +*/ +int32_t RedGetoptLong( + int32_t nargc, + char * const *nargv, + const char *options, + const REDOPTION *long_options, + int32_t *idx) +{ + return getopt_internal(nargc, nargv, options, long_options, idx, FLAG_PERMUTE); +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/toolcmn/toolcmn.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/toolcmn/toolcmn.c new file mode 100644 index 0000000..0ad2b64 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/toolcmn/toolcmn.c @@ -0,0 +1,99 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements common-code utilities for tools and tests. +*/ +#include +#include +#include +#include + +#include +#include +#include +#include + + +/** @brief Convert a string into a volume number. + + In a POSIX-like configuration, @p pszVolume can either be a volume number or + a volume path prefix. In case of ambiguity, the volume number of a matching + path prefix takes precedence. + + In an FSE configuration, @p pszVolume can be a volume number. + + @param pszVolume The volume string. + + @return On success, returns the volume number; on failure, returns + #REDCONF_VOLUME_COUNT. +*/ +uint8_t RedFindVolumeNumber( + const char *pszVolume) +{ + unsigned long ulNumber; + const char *pszEndPtr; + uint8_t bVolNum = REDCONF_VOLUME_COUNT; + #if REDCONF_API_POSIX == 1 + uint8_t bIndex; + #endif + + /* Determine if pszVolume can be interpreted as a volume number. + */ + errno = 0; + ulNumber = strtoul(pszVolume, (char **)&pszEndPtr, 10); + if((errno == 0) && (ulNumber != ULONG_MAX) && (pszEndPtr[0U] == '\0') && (ulNumber < REDCONF_VOLUME_COUNT)) + { + bVolNum = (uint8_t)ulNumber; + } + + #if REDCONF_API_POSIX == 1 + /* Determine if pszVolume is a valid path prefix. + */ + for(bIndex = 0U; bIndex < REDCONF_VOLUME_COUNT; bIndex++) + { + if(strcmp(gaRedVolConf[bIndex].pszPathPrefix, pszVolume) == 0) + { + break; + } + } + + if(bIndex < REDCONF_VOLUME_COUNT) + { + /* Edge case: It is technically possible for pszVolume to be both a + valid volume number and a valid volume prefix, for different + volumes. For example, if pszVolume is "2", that would be recognized + as volume number 2 above. But if "2" is the (poorly chosen) path + prefix for volume number 4, that would also be matched. Since the + POSIX-like API is primarily name based, and the ability to use + volume numbers with this tool is just a convenience, the volume + prefix takes precedence. + */ + bVolNum = bIndex; + } + #endif + + return bVolNum; +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/util/bitmap.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/util/bitmap.c new file mode 100644 index 0000000..c09d3c9 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/util/bitmap.c @@ -0,0 +1,101 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements utilities for working with bitmaps. +*/ +#include + + +/** @brief Query the state of a bit in a bitmap. + + Bits are counted from most significant to least significant. Thus, the mask + for bit zero is 0x80 applied to the first byte in the bitmap. + + @param pbBitmap Pointer to the bitmap. + @param ulBit The bit to query. + + @retval Whether the bit is set (true) or clear (false. +*/ +bool RedBitGet( + const uint8_t *pbBitmap, + uint32_t ulBit) +{ + bool fRet; + + if(pbBitmap == NULL) + { + REDERROR(); + fRet = false; + } + else + { + fRet = (pbBitmap[ulBit >> 3U] & (0x80U >> (ulBit & 7U))) != 0U; + } + + return fRet; +} + + +/** @brief Set a bit in a bitmap to one. + + Bits are counted from most significant to least significant. Thus, the mask + for bit zero is 0x80 applied to the first byte in the bitmap. + + @param pbBitmap Pointer to the bitmap. + @param ulBit The bit to set. +*/ +void RedBitSet( + uint8_t *pbBitmap, + uint32_t ulBit) +{ + REDASSERT(pbBitmap != NULL); + + if(pbBitmap != NULL) + { + pbBitmap[ulBit >> 3U] |= (0x80U >> (ulBit & 7U)); + } +} + + +/** @brief Clear a bit in a bitmap to zero. + + Bits are counted from most significant to least significant. Thus, the mask + for bit zero is 0x80 applied to the first byte in the bitmap. + + @param pbBitmap Pointer to the bitmap. + @param ulBit The bit to clear. +*/ +void RedBitClear( + uint8_t *pbBitmap, + uint32_t ulBit) +{ + REDASSERT(pbBitmap != NULL); + + if(pbBitmap != NULL) + { + pbBitmap[ulBit >> 3U] &= ~(0x80U >> (ulBit & 7U)); + } +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/util/crc.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/util/crc.c new file mode 100644 index 0000000..7ed15cb --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/util/crc.c @@ -0,0 +1,598 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements utilities for calculating CRC-32 checksums. +*/ +#include + + +/* The CRC functions do not return errors since the only detectable error + condition is a NULL buffer pointer. If such a condition does arise, the + functions assert and return the below CRC, which, although a legal CRC, + is nonetheless suspicious and could provide a clue that something has + gone wrong. +*/ +#define SUSPICIOUS_CRC_VALUE (0xBAADC0DEU) + +#define CRC_BITWISE (0U) +#define CRC_SARWATE (1U) +#define CRC_SLICEBY8 (2U) + + +#if REDCONF_CRC_ALGORITHM == CRC_BITWISE + +/* The following is representative of the polynomial accepted by CCITT 32-bit + and in IEEE 802.3, Ethernet 2 specification. + + x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 + (reverse order) + 1110 1101 1011 1000 1000 0011 0010 0000 1 + (E) (D) (B) (8) (8) (3) (2) (0) +*/ +#define CCITT_32_POLYNOMIAL (0xEDB88320U) + + +/** @brief Compute a CRC32 for the given data buffer. + + For CCITT-32 compliance, the initial CRC must be set to 0. To CRC multiple + buffers, call this function with the previously returned CRC value. + + @param ulInitCrc32 Starting CRC value. + @param pBuffer Data buffer to calculate the CRC from. + @param ulLength Number of bytes of data in the given buffer. + + @return The updated CRC value. +*/ +uint32_t RedCrc32Update( + uint32_t ulInitCrc32, + const void *pBuffer, + uint32_t ulLength) +{ + uint32_t ulCrc32; + + if(pBuffer == NULL) + { + REDERROR(); + ulCrc32 = SUSPICIOUS_CRC_VALUE; + } + else + { + const uint8_t *pbBuffer = CAST_VOID_PTR_TO_CONST_UINT8_PTR(pBuffer); + uint32_t ulIdx; + + ulCrc32 = ~ulInitCrc32; + + for(ulIdx = 0U; ulIdx < ulLength; ++ulIdx) + { + uint32_t ulBit; + + ulCrc32 ^= pbBuffer[ulIdx]; + + /* Branchless inner loop (greatly improves performance). + */ + for(ulBit = 0U; ulBit < 8U; ulBit++) + { + ulCrc32 = ((ulCrc32 & 1U) * CCITT_32_POLYNOMIAL) ^ (ulCrc32 >> 1U); + } + } + + ulCrc32 = ~ulCrc32; + } + + return ulCrc32; +} + +#elif REDCONF_CRC_ALGORITHM == CRC_SARWATE + +/** @brief Compute a CRC32 for the given data buffer. + + For CCITT-32 compliance, the initial CRC must be set to 0. To CRC multiple + buffers, call this function with the previously returned CRC value. + + @param ulInitCrc32 Starting CRC value. + @param pBuffer Data buffer to calculate the CRC from. + @param ulLength Number of bytes of data in the given buffer. + + @return The updated CRC value. +*/ +uint32_t RedCrc32Update( + uint32_t ulInitCrc32, + const void *pBuffer, + uint32_t ulLength) +{ + static const uint32_t aulCrc32Table[] = + { + 0x00000000U, 0x77073096U, 0xEE0E612CU, 0x990951BAU, 0x076DC419U, 0x706AF48FU, 0xE963A535U, 0x9E6495A3U, + 0x0EDB8832U, 0x79DCB8A4U, 0xE0D5E91EU, 0x97D2D988U, 0x09B64C2BU, 0x7EB17CBDU, 0xE7B82D07U, 0x90BF1D91U, + 0x1DB71064U, 0x6AB020F2U, 0xF3B97148U, 0x84BE41DEU, 0x1ADAD47DU, 0x6DDDE4EBU, 0xF4D4B551U, 0x83D385C7U, + 0x136C9856U, 0x646BA8C0U, 0xFD62F97AU, 0x8A65C9ECU, 0x14015C4FU, 0x63066CD9U, 0xFA0F3D63U, 0x8D080DF5U, + 0x3B6E20C8U, 0x4C69105EU, 0xD56041E4U, 0xA2677172U, 0x3C03E4D1U, 0x4B04D447U, 0xD20D85FDU, 0xA50AB56BU, + 0x35B5A8FAU, 0x42B2986CU, 0xDBBBC9D6U, 0xACBCF940U, 0x32D86CE3U, 0x45DF5C75U, 0xDCD60DCFU, 0xABD13D59U, + 0x26D930ACU, 0x51DE003AU, 0xC8D75180U, 0xBFD06116U, 0x21B4F4B5U, 0x56B3C423U, 0xCFBA9599U, 0xB8BDA50FU, + 0x2802B89EU, 0x5F058808U, 0xC60CD9B2U, 0xB10BE924U, 0x2F6F7C87U, 0x58684C11U, 0xC1611DABU, 0xB6662D3DU, + 0x76DC4190U, 0x01DB7106U, 0x98D220BCU, 0xEFD5102AU, 0x71B18589U, 0x06B6B51FU, 0x9FBFE4A5U, 0xE8B8D433U, + 0x7807C9A2U, 0x0F00F934U, 0x9609A88EU, 0xE10E9818U, 0x7F6A0DBBU, 0x086D3D2DU, 0x91646C97U, 0xE6635C01U, + 0x6B6B51F4U, 0x1C6C6162U, 0x856530D8U, 0xF262004EU, 0x6C0695EDU, 0x1B01A57BU, 0x8208F4C1U, 0xF50FC457U, + 0x65B0D9C6U, 0x12B7E950U, 0x8BBEB8EAU, 0xFCB9887CU, 0x62DD1DDFU, 0x15DA2D49U, 0x8CD37CF3U, 0xFBD44C65U, + 0x4DB26158U, 0x3AB551CEU, 0xA3BC0074U, 0xD4BB30E2U, 0x4ADFA541U, 0x3DD895D7U, 0xA4D1C46DU, 0xD3D6F4FBU, + 0x4369E96AU, 0x346ED9FCU, 0xAD678846U, 0xDA60B8D0U, 0x44042D73U, 0x33031DE5U, 0xAA0A4C5FU, 0xDD0D7CC9U, + 0x5005713CU, 0x270241AAU, 0xBE0B1010U, 0xC90C2086U, 0x5768B525U, 0x206F85B3U, 0xB966D409U, 0xCE61E49FU, + 0x5EDEF90EU, 0x29D9C998U, 0xB0D09822U, 0xC7D7A8B4U, 0x59B33D17U, 0x2EB40D81U, 0xB7BD5C3BU, 0xC0BA6CADU, + 0xEDB88320U, 0x9ABFB3B6U, 0x03B6E20CU, 0x74B1D29AU, 0xEAD54739U, 0x9DD277AFU, 0x04DB2615U, 0x73DC1683U, + 0xE3630B12U, 0x94643B84U, 0x0D6D6A3EU, 0x7A6A5AA8U, 0xE40ECF0BU, 0x9309FF9DU, 0x0A00AE27U, 0x7D079EB1U, + 0xF00F9344U, 0x8708A3D2U, 0x1E01F268U, 0x6906C2FEU, 0xF762575DU, 0x806567CBU, 0x196C3671U, 0x6E6B06E7U, + 0xFED41B76U, 0x89D32BE0U, 0x10DA7A5AU, 0x67DD4ACCU, 0xF9B9DF6FU, 0x8EBEEFF9U, 0x17B7BE43U, 0x60B08ED5U, + 0xD6D6A3E8U, 0xA1D1937EU, 0x38D8C2C4U, 0x4FDFF252U, 0xD1BB67F1U, 0xA6BC5767U, 0x3FB506DDU, 0x48B2364BU, + 0xD80D2BDAU, 0xAF0A1B4CU, 0x36034AF6U, 0x41047A60U, 0xDF60EFC3U, 0xA867DF55U, 0x316E8EEFU, 0x4669BE79U, + 0xCB61B38CU, 0xBC66831AU, 0x256FD2A0U, 0x5268E236U, 0xCC0C7795U, 0xBB0B4703U, 0x220216B9U, 0x5505262FU, + 0xC5BA3BBEU, 0xB2BD0B28U, 0x2BB45A92U, 0x5CB36A04U, 0xC2D7FFA7U, 0xB5D0CF31U, 0x2CD99E8BU, 0x5BDEAE1DU, + 0x9B64C2B0U, 0xEC63F226U, 0x756AA39CU, 0x026D930AU, 0x9C0906A9U, 0xEB0E363FU, 0x72076785U, 0x05005713U, + 0x95BF4A82U, 0xE2B87A14U, 0x7BB12BAEU, 0x0CB61B38U, 0x92D28E9BU, 0xE5D5BE0DU, 0x7CDCEFB7U, 0x0BDBDF21U, + 0x86D3D2D4U, 0xF1D4E242U, 0x68DDB3F8U, 0x1FDA836EU, 0x81BE16CDU, 0xF6B9265BU, 0x6FB077E1U, 0x18B74777U, + 0x88085AE6U, 0xFF0F6A70U, 0x66063BCAU, 0x11010B5CU, 0x8F659EFFU, 0xF862AE69U, 0x616BFFD3U, 0x166CCF45U, + 0xA00AE278U, 0xD70DD2EEU, 0x4E048354U, 0x3903B3C2U, 0xA7672661U, 0xD06016F7U, 0x4969474DU, 0x3E6E77DBU, + 0xAED16A4AU, 0xD9D65ADCU, 0x40DF0B66U, 0x37D83BF0U, 0xA9BCAE53U, 0xDEBB9EC5U, 0x47B2CF7FU, 0x30B5FFE9U, + 0xBDBDF21CU, 0xCABAC28AU, 0x53B39330U, 0x24B4A3A6U, 0xBAD03605U, 0xCDD70693U, 0x54DE5729U, 0x23D967BFU, + 0xB3667A2EU, 0xC4614AB8U, 0x5D681B02U, 0x2A6F2B94U, 0xB40BBE37U, 0xC30C8EA1U, 0x5A05DF1BU, 0x2D02EF8DU, + }; + + uint32_t ulCrc32; + + if(pBuffer == NULL) + { + REDERROR(); + ulCrc32 = SUSPICIOUS_CRC_VALUE; + } + else + { + const uint8_t *pbBuffer = CAST_VOID_PTR_TO_CONST_UINT8_PTR(pBuffer); + uint32_t ulIdx; + + ulCrc32 = ~ulInitCrc32; + + for(ulIdx = 0U; ulIdx < ulLength; ++ulIdx) + { + ulCrc32 = (ulCrc32 >> 8U) ^ aulCrc32Table[(ulCrc32 ^ pbBuffer[ulIdx]) & 0xFFU]; + } + + ulCrc32 = ~ulCrc32; + } + + return ulCrc32; +} + +#elif REDCONF_CRC_ALGORITHM == CRC_SLICEBY8 + + +/** @brief Compute a CRC32 for the given data buffer. + + For CCITT-32 compliance, the initial CRC must be set to 0. To CRC multiple + buffers, call this function with the previously returned CRC value. + + @param ulInitCrc32 Starting CRC value. + @param pBuffer Data buffer to calculate the CRC from. + @param ulLength Number of bytes of data in the given buffer. + + @return The updated CRC value. +*/ +uint32_t RedCrc32Update( + uint32_t ulInitCrc32, + const void *pBuffer, + uint32_t ulLength) +{ + /* CRC32 XOR table, with slicing-by-8 extensions. + + This first column of the table contains the same XOR values as used in + the classic byte-at-a-time Sarwate algorithm. The other seven columns + are derived from the first, and are used in Intel's slicing-by-eight CRC + algorithm. + + The layout of this array in memory is novel and deserves explanation. + In other implementations, including Intel's example, each of the below + columns is an array. The first column is a 256-entry array, followed by + another 256-entry array for the second column, etc. Testing on both ARM + and x86 has shown the below mixed arrangement to be about 5-9% faster. + One possible explanation: With the array-per-table approach, each of the + eight table lookups is guaranteed to be in a separate 1 KB chunk of + memory. With the below array, sometimes multiple table lookups will, by + coincidence, be close together, making better use of the cache. + */ + static const uint32_t aulCrc32Table[] = + { + 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U, + 0x77073096U, 0x191B3141U, 0x01C26A37U, 0xB8BC6765U, 0x3D6029B0U, 0xCB5CD3A5U, 0xA6770BB4U, 0xCCAA009EU, + 0xEE0E612CU, 0x32366282U, 0x0384D46EU, 0xAA09C88BU, 0x7AC05360U, 0x4DC8A10BU, 0x979F1129U, 0x4225077DU, + 0x990951BAU, 0x2B2D53C3U, 0x0246BE59U, 0x12B5AFEEU, 0x47A07AD0U, 0x869472AEU, 0x31E81A9DU, 0x8E8F07E3U, + 0x076DC419U, 0x646CC504U, 0x0709A8DCU, 0x8F629757U, 0xF580A6C0U, 0x9B914216U, 0xF44F2413U, 0x844A0EFAU, + 0x706AF48FU, 0x7D77F445U, 0x06CBC2EBU, 0x37DEF032U, 0xC8E08F70U, 0x50CD91B3U, 0x52382FA7U, 0x48E00E64U, + 0xE963A535U, 0x565AA786U, 0x048D7CB2U, 0x256B5FDCU, 0x8F40F5A0U, 0xD659E31DU, 0x63D0353AU, 0xC66F0987U, + 0x9E6495A3U, 0x4F4196C7U, 0x054F1685U, 0x9DD738B9U, 0xB220DC10U, 0x1D0530B8U, 0xC5A73E8EU, 0x0AC50919U, + 0x0EDB8832U, 0xC8D98A08U, 0x0E1351B8U, 0xC5B428EFU, 0x30704BC1U, 0xEC53826DU, 0x33EF4E67U, 0xD3E51BB5U, + 0x79DCB8A4U, 0xD1C2BB49U, 0x0FD13B8FU, 0x7D084F8AU, 0x0D106271U, 0x270F51C8U, 0x959845D3U, 0x1F4F1B2BU, + 0xE0D5E91EU, 0xFAEFE88AU, 0x0D9785D6U, 0x6FBDE064U, 0x4AB018A1U, 0xA19B2366U, 0xA4705F4EU, 0x91C01CC8U, + 0x97D2D988U, 0xE3F4D9CBU, 0x0C55EFE1U, 0xD7018701U, 0x77D03111U, 0x6AC7F0C3U, 0x020754FAU, 0x5D6A1C56U, + 0x09B64C2BU, 0xACB54F0CU, 0x091AF964U, 0x4AD6BFB8U, 0xC5F0ED01U, 0x77C2C07BU, 0xC7A06A74U, 0x57AF154FU, + 0x7EB17CBDU, 0xB5AE7E4DU, 0x08D89353U, 0xF26AD8DDU, 0xF890C4B1U, 0xBC9E13DEU, 0x61D761C0U, 0x9B0515D1U, + 0xE7B82D07U, 0x9E832D8EU, 0x0A9E2D0AU, 0xE0DF7733U, 0xBF30BE61U, 0x3A0A6170U, 0x503F7B5DU, 0x158A1232U, + 0x90BF1D91U, 0x87981CCFU, 0x0B5C473DU, 0x58631056U, 0x825097D1U, 0xF156B2D5U, 0xF64870E9U, 0xD92012ACU, + 0x1DB71064U, 0x4AC21251U, 0x1C26A370U, 0x5019579FU, 0x60E09782U, 0x03D6029BU, 0x67DE9CCEU, 0x7CBB312BU, + 0x6AB020F2U, 0x53D92310U, 0x1DE4C947U, 0xE8A530FAU, 0x5D80BE32U, 0xC88AD13EU, 0xC1A9977AU, 0xB01131B5U, + 0xF3B97148U, 0x78F470D3U, 0x1FA2771EU, 0xFA109F14U, 0x1A20C4E2U, 0x4E1EA390U, 0xF0418DE7U, 0x3E9E3656U, + 0x84BE41DEU, 0x61EF4192U, 0x1E601D29U, 0x42ACF871U, 0x2740ED52U, 0x85427035U, 0x56368653U, 0xF23436C8U, + 0x1ADAD47DU, 0x2EAED755U, 0x1B2F0BACU, 0xDF7BC0C8U, 0x95603142U, 0x9847408DU, 0x9391B8DDU, 0xF8F13FD1U, + 0x6DDDE4EBU, 0x37B5E614U, 0x1AED619BU, 0x67C7A7ADU, 0xA80018F2U, 0x531B9328U, 0x35E6B369U, 0x345B3F4FU, + 0xF4D4B551U, 0x1C98B5D7U, 0x18ABDFC2U, 0x75720843U, 0xEFA06222U, 0xD58FE186U, 0x040EA9F4U, 0xBAD438ACU, + 0x83D385C7U, 0x05838496U, 0x1969B5F5U, 0xCDCE6F26U, 0xD2C04B92U, 0x1ED33223U, 0xA279A240U, 0x767E3832U, + 0x136C9856U, 0x821B9859U, 0x1235F2C8U, 0x95AD7F70U, 0x5090DC43U, 0xEF8580F6U, 0x5431D2A9U, 0xAF5E2A9EU, + 0x646BA8C0U, 0x9B00A918U, 0x13F798FFU, 0x2D111815U, 0x6DF0F5F3U, 0x24D95353U, 0xF246D91DU, 0x63F42A00U, + 0xFD62F97AU, 0xB02DFADBU, 0x11B126A6U, 0x3FA4B7FBU, 0x2A508F23U, 0xA24D21FDU, 0xC3AEC380U, 0xED7B2DE3U, + 0x8A65C9ECU, 0xA936CB9AU, 0x10734C91U, 0x8718D09EU, 0x1730A693U, 0x6911F258U, 0x65D9C834U, 0x21D12D7DU, + 0x14015C4FU, 0xE6775D5DU, 0x153C5A14U, 0x1ACFE827U, 0xA5107A83U, 0x7414C2E0U, 0xA07EF6BAU, 0x2B142464U, + 0x63066CD9U, 0xFF6C6C1CU, 0x14FE3023U, 0xA2738F42U, 0x98705333U, 0xBF481145U, 0x0609FD0EU, 0xE7BE24FAU, + 0xFA0F3D63U, 0xD4413FDFU, 0x16B88E7AU, 0xB0C620ACU, 0xDFD029E3U, 0x39DC63EBU, 0x37E1E793U, 0x69312319U, + 0x8D080DF5U, 0xCD5A0E9EU, 0x177AE44DU, 0x087A47C9U, 0xE2B00053U, 0xF280B04EU, 0x9196EC27U, 0xA59B2387U, + 0x3B6E20C8U, 0x958424A2U, 0x384D46E0U, 0xA032AF3EU, 0xC1C12F04U, 0x07AC0536U, 0xCFBD399CU, 0xF9766256U, + 0x4C69105EU, 0x8C9F15E3U, 0x398F2CD7U, 0x188EC85BU, 0xFCA106B4U, 0xCCF0D693U, 0x69CA3228U, 0x35DC62C8U, + 0xD56041E4U, 0xA7B24620U, 0x3BC9928EU, 0x0A3B67B5U, 0xBB017C64U, 0x4A64A43DU, 0x582228B5U, 0xBB53652BU, + 0xA2677172U, 0xBEA97761U, 0x3A0BF8B9U, 0xB28700D0U, 0x866155D4U, 0x81387798U, 0xFE552301U, 0x77F965B5U, + 0x3C03E4D1U, 0xF1E8E1A6U, 0x3F44EE3CU, 0x2F503869U, 0x344189C4U, 0x9C3D4720U, 0x3BF21D8FU, 0x7D3C6CACU, + 0x4B04D447U, 0xE8F3D0E7U, 0x3E86840BU, 0x97EC5F0CU, 0x0921A074U, 0x57619485U, 0x9D85163BU, 0xB1966C32U, + 0xD20D85FDU, 0xC3DE8324U, 0x3CC03A52U, 0x8559F0E2U, 0x4E81DAA4U, 0xD1F5E62BU, 0xAC6D0CA6U, 0x3F196BD1U, + 0xA50AB56BU, 0xDAC5B265U, 0x3D025065U, 0x3DE59787U, 0x73E1F314U, 0x1AA9358EU, 0x0A1A0712U, 0xF3B36B4FU, + 0x35B5A8FAU, 0x5D5DAEAAU, 0x365E1758U, 0x658687D1U, 0xF1B164C5U, 0xEBFF875BU, 0xFC5277FBU, 0x2A9379E3U, + 0x42B2986CU, 0x44469FEBU, 0x379C7D6FU, 0xDD3AE0B4U, 0xCCD14D75U, 0x20A354FEU, 0x5A257C4FU, 0xE639797DU, + 0xDBBBC9D6U, 0x6F6BCC28U, 0x35DAC336U, 0xCF8F4F5AU, 0x8B7137A5U, 0xA6372650U, 0x6BCD66D2U, 0x68B67E9EU, + 0xACBCF940U, 0x7670FD69U, 0x3418A901U, 0x7733283FU, 0xB6111E15U, 0x6D6BF5F5U, 0xCDBA6D66U, 0xA41C7E00U, + 0x32D86CE3U, 0x39316BAEU, 0x3157BF84U, 0xEAE41086U, 0x0431C205U, 0x706EC54DU, 0x081D53E8U, 0xAED97719U, + 0x45DF5C75U, 0x202A5AEFU, 0x3095D5B3U, 0x525877E3U, 0x3951EBB5U, 0xBB3216E8U, 0xAE6A585CU, 0x62737787U, + 0xDCD60DCFU, 0x0B07092CU, 0x32D36BEAU, 0x40EDD80DU, 0x7EF19165U, 0x3DA66446U, 0x9F8242C1U, 0xECFC7064U, + 0xABD13D59U, 0x121C386DU, 0x331101DDU, 0xF851BF68U, 0x4391B8D5U, 0xF6FAB7E3U, 0x39F54975U, 0x205670FAU, + 0x26D930ACU, 0xDF4636F3U, 0x246BE590U, 0xF02BF8A1U, 0xA121B886U, 0x047A07ADU, 0xA863A552U, 0x85CD537DU, + 0x51DE003AU, 0xC65D07B2U, 0x25A98FA7U, 0x48979FC4U, 0x9C419136U, 0xCF26D408U, 0x0E14AEE6U, 0x496753E3U, + 0xC8D75180U, 0xED705471U, 0x27EF31FEU, 0x5A22302AU, 0xDBE1EBE6U, 0x49B2A6A6U, 0x3FFCB47BU, 0xC7E85400U, + 0xBFD06116U, 0xF46B6530U, 0x262D5BC9U, 0xE29E574FU, 0xE681C256U, 0x82EE7503U, 0x998BBFCFU, 0x0B42549EU, + 0x21B4F4B5U, 0xBB2AF3F7U, 0x23624D4CU, 0x7F496FF6U, 0x54A11E46U, 0x9FEB45BBU, 0x5C2C8141U, 0x01875D87U, + 0x56B3C423U, 0xA231C2B6U, 0x22A0277BU, 0xC7F50893U, 0x69C137F6U, 0x54B7961EU, 0xFA5B8AF5U, 0xCD2D5D19U, + 0xCFBA9599U, 0x891C9175U, 0x20E69922U, 0xD540A77DU, 0x2E614D26U, 0xD223E4B0U, 0xCBB39068U, 0x43A25AFAU, + 0xB8BDA50FU, 0x9007A034U, 0x2124F315U, 0x6DFCC018U, 0x13016496U, 0x197F3715U, 0x6DC49BDCU, 0x8F085A64U, + 0x2802B89EU, 0x179FBCFBU, 0x2A78B428U, 0x359FD04EU, 0x9151F347U, 0xE82985C0U, 0x9B8CEB35U, 0x562848C8U, + 0x5F058808U, 0x0E848DBAU, 0x2BBADE1FU, 0x8D23B72BU, 0xAC31DAF7U, 0x23755665U, 0x3DFBE081U, 0x9A824856U, + 0xC60CD9B2U, 0x25A9DE79U, 0x29FC6046U, 0x9F9618C5U, 0xEB91A027U, 0xA5E124CBU, 0x0C13FA1CU, 0x140D4FB5U, + 0xB10BE924U, 0x3CB2EF38U, 0x283E0A71U, 0x272A7FA0U, 0xD6F18997U, 0x6EBDF76EU, 0xAA64F1A8U, 0xD8A74F2BU, + 0x2F6F7C87U, 0x73F379FFU, 0x2D711CF4U, 0xBAFD4719U, 0x64D15587U, 0x73B8C7D6U, 0x6FC3CF26U, 0xD2624632U, + 0x58684C11U, 0x6AE848BEU, 0x2CB376C3U, 0x0241207CU, 0x59B17C37U, 0xB8E41473U, 0xC9B4C492U, 0x1EC846ACU, + 0xC1611DABU, 0x41C51B7DU, 0x2EF5C89AU, 0x10F48F92U, 0x1E1106E7U, 0x3E7066DDU, 0xF85CDE0FU, 0x9047414FU, + 0xB6662D3DU, 0x58DE2A3CU, 0x2F37A2ADU, 0xA848E8F7U, 0x23712F57U, 0xF52CB578U, 0x5E2BD5BBU, 0x5CED41D1U, + 0x76DC4190U, 0xF0794F05U, 0x709A8DC0U, 0x9B14583DU, 0x58F35849U, 0x0F580A6CU, 0x440B7579U, 0x299DC2EDU, + 0x01DB7106U, 0xE9627E44U, 0x7158E7F7U, 0x23A83F58U, 0x659371F9U, 0xC404D9C9U, 0xE27C7ECDU, 0xE537C273U, + 0x98D220BCU, 0xC24F2D87U, 0x731E59AEU, 0x311D90B6U, 0x22330B29U, 0x4290AB67U, 0xD3946450U, 0x6BB8C590U, + 0xEFD5102AU, 0xDB541CC6U, 0x72DC3399U, 0x89A1F7D3U, 0x1F532299U, 0x89CC78C2U, 0x75E36FE4U, 0xA712C50EU, + 0x71B18589U, 0x94158A01U, 0x7793251CU, 0x1476CF6AU, 0xAD73FE89U, 0x94C9487AU, 0xB044516AU, 0xADD7CC17U, + 0x06B6B51FU, 0x8D0EBB40U, 0x76514F2BU, 0xACCAA80FU, 0x9013D739U, 0x5F959BDFU, 0x16335ADEU, 0x617DCC89U, + 0x9FBFE4A5U, 0xA623E883U, 0x7417F172U, 0xBE7F07E1U, 0xD7B3ADE9U, 0xD901E971U, 0x27DB4043U, 0xEFF2CB6AU, + 0xE8B8D433U, 0xBF38D9C2U, 0x75D59B45U, 0x06C36084U, 0xEAD38459U, 0x125D3AD4U, 0x81AC4BF7U, 0x2358CBF4U, + 0x7807C9A2U, 0x38A0C50DU, 0x7E89DC78U, 0x5EA070D2U, 0x68831388U, 0xE30B8801U, 0x77E43B1EU, 0xFA78D958U, + 0x0F00F934U, 0x21BBF44CU, 0x7F4BB64FU, 0xE61C17B7U, 0x55E33A38U, 0x28575BA4U, 0xD19330AAU, 0x36D2D9C6U, + 0x9609A88EU, 0x0A96A78FU, 0x7D0D0816U, 0xF4A9B859U, 0x124340E8U, 0xAEC3290AU, 0xE07B2A37U, 0xB85DDE25U, + 0xE10E9818U, 0x138D96CEU, 0x7CCF6221U, 0x4C15DF3CU, 0x2F236958U, 0x659FFAAFU, 0x460C2183U, 0x74F7DEBBU, + 0x7F6A0DBBU, 0x5CCC0009U, 0x798074A4U, 0xD1C2E785U, 0x9D03B548U, 0x789ACA17U, 0x83AB1F0DU, 0x7E32D7A2U, + 0x086D3D2DU, 0x45D73148U, 0x78421E93U, 0x697E80E0U, 0xA0639CF8U, 0xB3C619B2U, 0x25DC14B9U, 0xB298D73CU, + 0x91646C97U, 0x6EFA628BU, 0x7A04A0CAU, 0x7BCB2F0EU, 0xE7C3E628U, 0x35526B1CU, 0x14340E24U, 0x3C17D0DFU, + 0xE6635C01U, 0x77E153CAU, 0x7BC6CAFDU, 0xC377486BU, 0xDAA3CF98U, 0xFE0EB8B9U, 0xB2430590U, 0xF0BDD041U, + 0x6B6B51F4U, 0xBABB5D54U, 0x6CBC2EB0U, 0xCB0D0FA2U, 0x3813CFCBU, 0x0C8E08F7U, 0x23D5E9B7U, 0x5526F3C6U, + 0x1C6C6162U, 0xA3A06C15U, 0x6D7E4487U, 0x73B168C7U, 0x0573E67BU, 0xC7D2DB52U, 0x85A2E203U, 0x998CF358U, + 0x856530D8U, 0x888D3FD6U, 0x6F38FADEU, 0x6104C729U, 0x42D39CABU, 0x4146A9FCU, 0xB44AF89EU, 0x1703F4BBU, + 0xF262004EU, 0x91960E97U, 0x6EFA90E9U, 0xD9B8A04CU, 0x7FB3B51BU, 0x8A1A7A59U, 0x123DF32AU, 0xDBA9F425U, + 0x6C0695EDU, 0xDED79850U, 0x6BB5866CU, 0x446F98F5U, 0xCD93690BU, 0x971F4AE1U, 0xD79ACDA4U, 0xD16CFD3CU, + 0x1B01A57BU, 0xC7CCA911U, 0x6A77EC5BU, 0xFCD3FF90U, 0xF0F340BBU, 0x5C439944U, 0x71EDC610U, 0x1DC6FDA2U, + 0x8208F4C1U, 0xECE1FAD2U, 0x68315202U, 0xEE66507EU, 0xB7533A6BU, 0xDAD7EBEAU, 0x4005DC8DU, 0x9349FA41U, + 0xF50FC457U, 0xF5FACB93U, 0x69F33835U, 0x56DA371BU, 0x8A3313DBU, 0x118B384FU, 0xE672D739U, 0x5FE3FADFU, + 0x65B0D9C6U, 0x7262D75CU, 0x62AF7F08U, 0x0EB9274DU, 0x0863840AU, 0xE0DD8A9AU, 0x103AA7D0U, 0x86C3E873U, + 0x12B7E950U, 0x6B79E61DU, 0x636D153FU, 0xB6054028U, 0x3503ADBAU, 0x2B81593FU, 0xB64DAC64U, 0x4A69E8EDU, + 0x8BBEB8EAU, 0x4054B5DEU, 0x612BAB66U, 0xA4B0EFC6U, 0x72A3D76AU, 0xAD152B91U, 0x87A5B6F9U, 0xC4E6EF0EU, + 0xFCB9887CU, 0x594F849FU, 0x60E9C151U, 0x1C0C88A3U, 0x4FC3FEDAU, 0x6649F834U, 0x21D2BD4DU, 0x084CEF90U, + 0x62DD1DDFU, 0x160E1258U, 0x65A6D7D4U, 0x81DBB01AU, 0xFDE322CAU, 0x7B4CC88CU, 0xE47583C3U, 0x0289E689U, + 0x15DA2D49U, 0x0F152319U, 0x6464BDE3U, 0x3967D77FU, 0xC0830B7AU, 0xB0101B29U, 0x42028877U, 0xCE23E617U, + 0x8CD37CF3U, 0x243870DAU, 0x662203BAU, 0x2BD27891U, 0x872371AAU, 0x36846987U, 0x73EA92EAU, 0x40ACE1F4U, + 0xFBD44C65U, 0x3D23419BU, 0x67E0698DU, 0x936E1FF4U, 0xBA43581AU, 0xFDD8BA22U, 0xD59D995EU, 0x8C06E16AU, + 0x4DB26158U, 0x65FD6BA7U, 0x48D7CB20U, 0x3B26F703U, 0x9932774DU, 0x08F40F5AU, 0x8BB64CE5U, 0xD0EBA0BBU, + 0x3AB551CEU, 0x7CE65AE6U, 0x4915A117U, 0x839A9066U, 0xA4525EFDU, 0xC3A8DCFFU, 0x2DC14751U, 0x1C41A025U, + 0xA3BC0074U, 0x57CB0925U, 0x4B531F4EU, 0x912F3F88U, 0xE3F2242DU, 0x453CAE51U, 0x1C295DCCU, 0x92CEA7C6U, + 0xD4BB30E2U, 0x4ED03864U, 0x4A917579U, 0x299358EDU, 0xDE920D9DU, 0x8E607DF4U, 0xBA5E5678U, 0x5E64A758U, + 0x4ADFA541U, 0x0191AEA3U, 0x4FDE63FCU, 0xB4446054U, 0x6CB2D18DU, 0x93654D4CU, 0x7FF968F6U, 0x54A1AE41U, + 0x3DD895D7U, 0x188A9FE2U, 0x4E1C09CBU, 0x0CF80731U, 0x51D2F83DU, 0x58399EE9U, 0xD98E6342U, 0x980BAEDFU, + 0xA4D1C46DU, 0x33A7CC21U, 0x4C5AB792U, 0x1E4DA8DFU, 0x167282EDU, 0xDEADEC47U, 0xE86679DFU, 0x1684A93CU, + 0xD3D6F4FBU, 0x2ABCFD60U, 0x4D98DDA5U, 0xA6F1CFBAU, 0x2B12AB5DU, 0x15F13FE2U, 0x4E11726BU, 0xDA2EA9A2U, + 0x4369E96AU, 0xAD24E1AFU, 0x46C49A98U, 0xFE92DFECU, 0xA9423C8CU, 0xE4A78D37U, 0xB8590282U, 0x030EBB0EU, + 0x346ED9FCU, 0xB43FD0EEU, 0x4706F0AFU, 0x462EB889U, 0x9422153CU, 0x2FFB5E92U, 0x1E2E0936U, 0xCFA4BB90U, + 0xAD678846U, 0x9F12832DU, 0x45404EF6U, 0x549B1767U, 0xD3826FECU, 0xA96F2C3CU, 0x2FC613ABU, 0x412BBC73U, + 0xDA60B8D0U, 0x8609B26CU, 0x448224C1U, 0xEC277002U, 0xEEE2465CU, 0x6233FF99U, 0x89B1181FU, 0x8D81BCEDU, + 0x44042D73U, 0xC94824ABU, 0x41CD3244U, 0x71F048BBU, 0x5CC29A4CU, 0x7F36CF21U, 0x4C162691U, 0x8744B5F4U, + 0x33031DE5U, 0xD05315EAU, 0x400F5873U, 0xC94C2FDEU, 0x61A2B3FCU, 0xB46A1C84U, 0xEA612D25U, 0x4BEEB56AU, + 0xAA0A4C5FU, 0xFB7E4629U, 0x4249E62AU, 0xDBF98030U, 0x2602C92CU, 0x32FE6E2AU, 0xDB8937B8U, 0xC561B289U, + 0xDD0D7CC9U, 0xE2657768U, 0x438B8C1DU, 0x6345E755U, 0x1B62E09CU, 0xF9A2BD8FU, 0x7DFE3C0CU, 0x09CBB217U, + 0x5005713CU, 0x2F3F79F6U, 0x54F16850U, 0x6B3FA09CU, 0xF9D2E0CFU, 0x0B220DC1U, 0xEC68D02BU, 0xAC509190U, + 0x270241AAU, 0x362448B7U, 0x55330267U, 0xD383C7F9U, 0xC4B2C97FU, 0xC07EDE64U, 0x4A1FDB9FU, 0x60FA910EU, + 0xBE0B1010U, 0x1D091B74U, 0x5775BC3EU, 0xC1366817U, 0x8312B3AFU, 0x46EAACCAU, 0x7BF7C102U, 0xEE7596EDU, + 0xC90C2086U, 0x04122A35U, 0x56B7D609U, 0x798A0F72U, 0xBE729A1FU, 0x8DB67F6FU, 0xDD80CAB6U, 0x22DF9673U, + 0x5768B525U, 0x4B53BCF2U, 0x53F8C08CU, 0xE45D37CBU, 0x0C52460FU, 0x90B34FD7U, 0x1827F438U, 0x281A9F6AU, + 0x206F85B3U, 0x52488DB3U, 0x523AAABBU, 0x5CE150AEU, 0x31326FBFU, 0x5BEF9C72U, 0xBE50FF8CU, 0xE4B09FF4U, + 0xB966D409U, 0x7965DE70U, 0x507C14E2U, 0x4E54FF40U, 0x7692156FU, 0xDD7BEEDCU, 0x8FB8E511U, 0x6A3F9817U, + 0xCE61E49FU, 0x607EEF31U, 0x51BE7ED5U, 0xF6E89825U, 0x4BF23CDFU, 0x16273D79U, 0x29CFEEA5U, 0xA6959889U, + 0x5EDEF90EU, 0xE7E6F3FEU, 0x5AE239E8U, 0xAE8B8873U, 0xC9A2AB0EU, 0xE7718FACU, 0xDF879E4CU, 0x7FB58A25U, + 0x29D9C998U, 0xFEFDC2BFU, 0x5B2053DFU, 0x1637EF16U, 0xF4C282BEU, 0x2C2D5C09U, 0x79F095F8U, 0xB31F8ABBU, + 0xB0D09822U, 0xD5D0917CU, 0x5966ED86U, 0x048240F8U, 0xB362F86EU, 0xAAB92EA7U, 0x48188F65U, 0x3D908D58U, + 0xC7D7A8B4U, 0xCCCBA03DU, 0x58A487B1U, 0xBC3E279DU, 0x8E02D1DEU, 0x61E5FD02U, 0xEE6F84D1U, 0xF13A8DC6U, + 0x59B33D17U, 0x838A36FAU, 0x5DEB9134U, 0x21E91F24U, 0x3C220DCEU, 0x7CE0CDBAU, 0x2BC8BA5FU, 0xFBFF84DFU, + 0x2EB40D81U, 0x9A9107BBU, 0x5C29FB03U, 0x99557841U, 0x0142247EU, 0xB7BC1E1FU, 0x8DBFB1EBU, 0x37558441U, + 0xB7BD5C3BU, 0xB1BC5478U, 0x5E6F455AU, 0x8BE0D7AFU, 0x46E25EAEU, 0x31286CB1U, 0xBC57AB76U, 0xB9DA83A2U, + 0xC0BA6CADU, 0xA8A76539U, 0x5FAD2F6DU, 0x335CB0CAU, 0x7B82771EU, 0xFA74BF14U, 0x1A20A0C2U, 0x7570833CU, + 0xEDB88320U, 0x3B83984BU, 0xE1351B80U, 0xED59B63BU, 0xB1E6B092U, 0x1EB014D8U, 0x8816EAF2U, 0x533B85DAU, + 0x9ABFB3B6U, 0x2298A90AU, 0xE0F771B7U, 0x55E5D15EU, 0x8C869922U, 0xD5ECC77DU, 0x2E61E146U, 0x9F918544U, + 0x03B6E20CU, 0x09B5FAC9U, 0xE2B1CFEEU, 0x47507EB0U, 0xCB26E3F2U, 0x5378B5D3U, 0x1F89FBDBU, 0x111E82A7U, + 0x74B1D29AU, 0x10AECB88U, 0xE373A5D9U, 0xFFEC19D5U, 0xF646CA42U, 0x98246676U, 0xB9FEF06FU, 0xDDB48239U, + 0xEAD54739U, 0x5FEF5D4FU, 0xE63CB35CU, 0x623B216CU, 0x44661652U, 0x852156CEU, 0x7C59CEE1U, 0xD7718B20U, + 0x9DD277AFU, 0x46F46C0EU, 0xE7FED96BU, 0xDA874609U, 0x79063FE2U, 0x4E7D856BU, 0xDA2EC555U, 0x1BDB8BBEU, + 0x04DB2615U, 0x6DD93FCDU, 0xE5B86732U, 0xC832E9E7U, 0x3EA64532U, 0xC8E9F7C5U, 0xEBC6DFC8U, 0x95548C5DU, + 0x73DC1683U, 0x74C20E8CU, 0xE47A0D05U, 0x708E8E82U, 0x03C66C82U, 0x03B52460U, 0x4DB1D47CU, 0x59FE8CC3U, + 0xE3630B12U, 0xF35A1243U, 0xEF264A38U, 0x28ED9ED4U, 0x8196FB53U, 0xF2E396B5U, 0xBBF9A495U, 0x80DE9E6FU, + 0x94643B84U, 0xEA412302U, 0xEEE4200FU, 0x9051F9B1U, 0xBCF6D2E3U, 0x39BF4510U, 0x1D8EAF21U, 0x4C749EF1U, + 0x0D6D6A3EU, 0xC16C70C1U, 0xECA29E56U, 0x82E4565FU, 0xFB56A833U, 0xBF2B37BEU, 0x2C66B5BCU, 0xC2FB9912U, + 0x7A6A5AA8U, 0xD8774180U, 0xED60F461U, 0x3A58313AU, 0xC6368183U, 0x7477E41BU, 0x8A11BE08U, 0x0E51998CU, + 0xE40ECF0BU, 0x9736D747U, 0xE82FE2E4U, 0xA78F0983U, 0x74165D93U, 0x6972D4A3U, 0x4FB68086U, 0x04949095U, + 0x9309FF9DU, 0x8E2DE606U, 0xE9ED88D3U, 0x1F336EE6U, 0x49767423U, 0xA22E0706U, 0xE9C18B32U, 0xC83E900BU, + 0x0A00AE27U, 0xA500B5C5U, 0xEBAB368AU, 0x0D86C108U, 0x0ED60EF3U, 0x24BA75A8U, 0xD82991AFU, 0x46B197E8U, + 0x7D079EB1U, 0xBC1B8484U, 0xEA695CBDU, 0xB53AA66DU, 0x33B62743U, 0xEFE6A60DU, 0x7E5E9A1BU, 0x8A1B9776U, + 0xF00F9344U, 0x71418A1AU, 0xFD13B8F0U, 0xBD40E1A4U, 0xD1062710U, 0x1D661643U, 0xEFC8763CU, 0x2F80B4F1U, + 0x8708A3D2U, 0x685ABB5BU, 0xFCD1D2C7U, 0x05FC86C1U, 0xEC660EA0U, 0xD63AC5E6U, 0x49BF7D88U, 0xE32AB46FU, + 0x1E01F268U, 0x4377E898U, 0xFE976C9EU, 0x1749292FU, 0xABC67470U, 0x50AEB748U, 0x78576715U, 0x6DA5B38CU, + 0x6906C2FEU, 0x5A6CD9D9U, 0xFF5506A9U, 0xAFF54E4AU, 0x96A65DC0U, 0x9BF264EDU, 0xDE206CA1U, 0xA10FB312U, + 0xF762575DU, 0x152D4F1EU, 0xFA1A102CU, 0x322276F3U, 0x248681D0U, 0x86F75455U, 0x1B87522FU, 0xABCABA0BU, + 0x806567CBU, 0x0C367E5FU, 0xFBD87A1BU, 0x8A9E1196U, 0x19E6A860U, 0x4DAB87F0U, 0xBDF0599BU, 0x6760BA95U, + 0x196C3671U, 0x271B2D9CU, 0xF99EC442U, 0x982BBE78U, 0x5E46D2B0U, 0xCB3FF55EU, 0x8C184306U, 0xE9EFBD76U, + 0x6E6B06E7U, 0x3E001CDDU, 0xF85CAE75U, 0x2097D91DU, 0x6326FB00U, 0x006326FBU, 0x2A6F48B2U, 0x2545BDE8U, + 0xFED41B76U, 0xB9980012U, 0xF300E948U, 0x78F4C94BU, 0xE1766CD1U, 0xF135942EU, 0xDC27385BU, 0xFC65AF44U, + 0x89D32BE0U, 0xA0833153U, 0xF2C2837FU, 0xC048AE2EU, 0xDC164561U, 0x3A69478BU, 0x7A5033EFU, 0x30CFAFDAU, + 0x10DA7A5AU, 0x8BAE6290U, 0xF0843D26U, 0xD2FD01C0U, 0x9BB63FB1U, 0xBCFD3525U, 0x4BB82972U, 0xBE40A839U, + 0x67DD4ACCU, 0x92B553D1U, 0xF1465711U, 0x6A4166A5U, 0xA6D61601U, 0x77A1E680U, 0xEDCF22C6U, 0x72EAA8A7U, + 0xF9B9DF6FU, 0xDDF4C516U, 0xF4094194U, 0xF7965E1CU, 0x14F6CA11U, 0x6AA4D638U, 0x28681C48U, 0x782FA1BEU, + 0x8EBEEFF9U, 0xC4EFF457U, 0xF5CB2BA3U, 0x4F2A3979U, 0x2996E3A1U, 0xA1F8059DU, 0x8E1F17FCU, 0xB485A120U, + 0x17B7BE43U, 0xEFC2A794U, 0xF78D95FAU, 0x5D9F9697U, 0x6E369971U, 0x276C7733U, 0xBFF70D61U, 0x3A0AA6C3U, + 0x60B08ED5U, 0xF6D996D5U, 0xF64FFFCDU, 0xE523F1F2U, 0x5356B0C1U, 0xEC30A496U, 0x198006D5U, 0xF6A0A65DU, + 0xD6D6A3E8U, 0xAE07BCE9U, 0xD9785D60U, 0x4D6B1905U, 0x70279F96U, 0x191C11EEU, 0x47ABD36EU, 0xAA4DE78CU, + 0xA1D1937EU, 0xB71C8DA8U, 0xD8BA3757U, 0xF5D77E60U, 0x4D47B626U, 0xD240C24BU, 0xE1DCD8DAU, 0x66E7E712U, + 0x38D8C2C4U, 0x9C31DE6BU, 0xDAFC890EU, 0xE762D18EU, 0x0AE7CCF6U, 0x54D4B0E5U, 0xD034C247U, 0xE868E0F1U, + 0x4FDFF252U, 0x852AEF2AU, 0xDB3EE339U, 0x5FDEB6EBU, 0x3787E546U, 0x9F886340U, 0x7643C9F3U, 0x24C2E06FU, + 0xD1BB67F1U, 0xCA6B79EDU, 0xDE71F5BCU, 0xC2098E52U, 0x85A73956U, 0x828D53F8U, 0xB3E4F77DU, 0x2E07E976U, + 0xA6BC5767U, 0xD37048ACU, 0xDFB39F8BU, 0x7AB5E937U, 0xB8C710E6U, 0x49D1805DU, 0x1593FCC9U, 0xE2ADE9E8U, + 0x3FB506DDU, 0xF85D1B6FU, 0xDDF521D2U, 0x680046D9U, 0xFF676A36U, 0xCF45F2F3U, 0x247BE654U, 0x6C22EE0BU, + 0x48B2364BU, 0xE1462A2EU, 0xDC374BE5U, 0xD0BC21BCU, 0xC2074386U, 0x04192156U, 0x820CEDE0U, 0xA088EE95U, + 0xD80D2BDAU, 0x66DE36E1U, 0xD76B0CD8U, 0x88DF31EAU, 0x4057D457U, 0xF54F9383U, 0x74449D09U, 0x79A8FC39U, + 0xAF0A1B4CU, 0x7FC507A0U, 0xD6A966EFU, 0x3063568FU, 0x7D37FDE7U, 0x3E134026U, 0xD23396BDU, 0xB502FCA7U, + 0x36034AF6U, 0x54E85463U, 0xD4EFD8B6U, 0x22D6F961U, 0x3A978737U, 0xB8873288U, 0xE3DB8C20U, 0x3B8DFB44U, + 0x41047A60U, 0x4DF36522U, 0xD52DB281U, 0x9A6A9E04U, 0x07F7AE87U, 0x73DBE12DU, 0x45AC8794U, 0xF727FBDAU, + 0xDF60EFC3U, 0x02B2F3E5U, 0xD062A404U, 0x07BDA6BDU, 0xB5D77297U, 0x6EDED195U, 0x800BB91AU, 0xFDE2F2C3U, + 0xA867DF55U, 0x1BA9C2A4U, 0xD1A0CE33U, 0xBF01C1D8U, 0x88B75B27U, 0xA5820230U, 0x267CB2AEU, 0x3148F25DU, + 0x316E8EEFU, 0x30849167U, 0xD3E6706AU, 0xADB46E36U, 0xCF1721F7U, 0x2316709EU, 0x1794A833U, 0xBFC7F5BEU, + 0x4669BE79U, 0x299FA026U, 0xD2241A5DU, 0x15080953U, 0xF2770847U, 0xE84AA33BU, 0xB1E3A387U, 0x736DF520U, + 0xCB61B38CU, 0xE4C5AEB8U, 0xC55EFE10U, 0x1D724E9AU, 0x10C70814U, 0x1ACA1375U, 0x20754FA0U, 0xD6F6D6A7U, + 0xBC66831AU, 0xFDDE9FF9U, 0xC49C9427U, 0xA5CE29FFU, 0x2DA721A4U, 0xD196C0D0U, 0x86024414U, 0x1A5CD639U, + 0x256FD2A0U, 0xD6F3CC3AU, 0xC6DA2A7EU, 0xB77B8611U, 0x6A075B74U, 0x5702B27EU, 0xB7EA5E89U, 0x94D3D1DAU, + 0x5268E236U, 0xCFE8FD7BU, 0xC7184049U, 0x0FC7E174U, 0x576772C4U, 0x9C5E61DBU, 0x119D553DU, 0x5879D144U, + 0xCC0C7795U, 0x80A96BBCU, 0xC25756CCU, 0x9210D9CDU, 0xE547AED4U, 0x815B5163U, 0xD43A6BB3U, 0x52BCD85DU, + 0xBB0B4703U, 0x99B25AFDU, 0xC3953CFBU, 0x2AACBEA8U, 0xD8278764U, 0x4A0782C6U, 0x724D6007U, 0x9E16D8C3U, + 0x220216B9U, 0xB29F093EU, 0xC1D382A2U, 0x38191146U, 0x9F87FDB4U, 0xCC93F068U, 0x43A57A9AU, 0x1099DF20U, + 0x5505262FU, 0xAB84387FU, 0xC011E895U, 0x80A57623U, 0xA2E7D404U, 0x07CF23CDU, 0xE5D2712EU, 0xDC33DFBEU, + 0xC5BA3BBEU, 0x2C1C24B0U, 0xCB4DAFA8U, 0xD8C66675U, 0x20B743D5U, 0xF6999118U, 0x139A01C7U, 0x0513CD12U, + 0xB2BD0B28U, 0x350715F1U, 0xCA8FC59FU, 0x607A0110U, 0x1DD76A65U, 0x3DC542BDU, 0xB5ED0A73U, 0xC9B9CD8CU, + 0x2BB45A92U, 0x1E2A4632U, 0xC8C97BC6U, 0x72CFAEFEU, 0x5A7710B5U, 0xBB513013U, 0x840510EEU, 0x4736CA6FU, + 0x5CB36A04U, 0x07317773U, 0xC90B11F1U, 0xCA73C99BU, 0x67173905U, 0x700DE3B6U, 0x22721B5AU, 0x8B9CCAF1U, + 0xC2D7FFA7U, 0x4870E1B4U, 0xCC440774U, 0x57A4F122U, 0xD537E515U, 0x6D08D30EU, 0xE7D525D4U, 0x8159C3E8U, + 0xB5D0CF31U, 0x516BD0F5U, 0xCD866D43U, 0xEF189647U, 0xE857CCA5U, 0xA65400ABU, 0x41A22E60U, 0x4DF3C376U, + 0x2CD99E8BU, 0x7A468336U, 0xCFC0D31AU, 0xFDAD39A9U, 0xAFF7B675U, 0x20C07205U, 0x704A34FDU, 0xC37CC495U, + 0x5BDEAE1DU, 0x635DB277U, 0xCE02B92DU, 0x45115ECCU, 0x92979FC5U, 0xEB9CA1A0U, 0xD63D3F49U, 0x0FD6C40BU, + 0x9B64C2B0U, 0xCBFAD74EU, 0x91AF9640U, 0x764DEE06U, 0xE915E8DBU, 0x11E81EB4U, 0xCC1D9F8BU, 0x7AA64737U, + 0xEC63F226U, 0xD2E1E60FU, 0x906DFC77U, 0xCEF18963U, 0xD475C16BU, 0xDAB4CD11U, 0x6A6A943FU, 0xB60C47A9U, + 0x756AA39CU, 0xF9CCB5CCU, 0x922B422EU, 0xDC44268DU, 0x93D5BBBBU, 0x5C20BFBFU, 0x5B828EA2U, 0x3883404AU, + 0x026D930AU, 0xE0D7848DU, 0x93E92819U, 0x64F841E8U, 0xAEB5920BU, 0x977C6C1AU, 0xFDF58516U, 0xF42940D4U, + 0x9C0906A9U, 0xAF96124AU, 0x96A63E9CU, 0xF92F7951U, 0x1C954E1BU, 0x8A795CA2U, 0x3852BB98U, 0xFEEC49CDU, + 0xEB0E363FU, 0xB68D230BU, 0x976454ABU, 0x41931E34U, 0x21F567ABU, 0x41258F07U, 0x9E25B02CU, 0x32464953U, + 0x72076785U, 0x9DA070C8U, 0x9522EAF2U, 0x5326B1DAU, 0x66551D7BU, 0xC7B1FDA9U, 0xAFCDAAB1U, 0xBCC94EB0U, + 0x05005713U, 0x84BB4189U, 0x94E080C5U, 0xEB9AD6BFU, 0x5B3534CBU, 0x0CED2E0CU, 0x09BAA105U, 0x70634E2EU, + 0x95BF4A82U, 0x03235D46U, 0x9FBCC7F8U, 0xB3F9C6E9U, 0xD965A31AU, 0xFDBB9CD9U, 0xFFF2D1ECU, 0xA9435C82U, + 0xE2B87A14U, 0x1A386C07U, 0x9E7EADCFU, 0x0B45A18CU, 0xE4058AAAU, 0x36E74F7CU, 0x5985DA58U, 0x65E95C1CU, + 0x7BB12BAEU, 0x31153FC4U, 0x9C381396U, 0x19F00E62U, 0xA3A5F07AU, 0xB0733DD2U, 0x686DC0C5U, 0xEB665BFFU, + 0x0CB61B38U, 0x280E0E85U, 0x9DFA79A1U, 0xA14C6907U, 0x9EC5D9CAU, 0x7B2FEE77U, 0xCE1ACB71U, 0x27CC5B61U, + 0x92D28E9BU, 0x674F9842U, 0x98B56F24U, 0x3C9B51BEU, 0x2CE505DAU, 0x662ADECFU, 0x0BBDF5FFU, 0x2D095278U, + 0xE5D5BE0DU, 0x7E54A903U, 0x99770513U, 0x842736DBU, 0x11852C6AU, 0xAD760D6AU, 0xADCAFE4BU, 0xE1A352E6U, + 0x7CDCEFB7U, 0x5579FAC0U, 0x9B31BB4AU, 0x96929935U, 0x562556BAU, 0x2BE27FC4U, 0x9C22E4D6U, 0x6F2C5505U, + 0x0BDBDF21U, 0x4C62CB81U, 0x9AF3D17DU, 0x2E2EFE50U, 0x6B457F0AU, 0xE0BEAC61U, 0x3A55EF62U, 0xA386559BU, + 0x86D3D2D4U, 0x8138C51FU, 0x8D893530U, 0x2654B999U, 0x89F57F59U, 0x123E1C2FU, 0xABC30345U, 0x061D761CU, + 0xF1D4E242U, 0x9823F45EU, 0x8C4B5F07U, 0x9EE8DEFCU, 0xB49556E9U, 0xD962CF8AU, 0x0DB408F1U, 0xCAB77682U, + 0x68DDB3F8U, 0xB30EA79DU, 0x8E0DE15EU, 0x8C5D7112U, 0xF3352C39U, 0x5FF6BD24U, 0x3C5C126CU, 0x44387161U, + 0x1FDA836EU, 0xAA1596DCU, 0x8FCF8B69U, 0x34E11677U, 0xCE550589U, 0x94AA6E81U, 0x9A2B19D8U, 0x889271FFU, + 0x81BE16CDU, 0xE554001BU, 0x8A809DECU, 0xA9362ECEU, 0x7C75D999U, 0x89AF5E39U, 0x5F8C2756U, 0x825778E6U, + 0xF6B9265BU, 0xFC4F315AU, 0x8B42F7DBU, 0x118A49ABU, 0x4115F029U, 0x42F38D9CU, 0xF9FB2CE2U, 0x4EFD7878U, + 0x6FB077E1U, 0xD7626299U, 0x89044982U, 0x033FE645U, 0x06B58AF9U, 0xC467FF32U, 0xC813367FU, 0xC0727F9BU, + 0x18B74777U, 0xCE7953D8U, 0x88C623B5U, 0xBB838120U, 0x3BD5A349U, 0x0F3B2C97U, 0x6E643DCBU, 0x0CD87F05U, + 0x88085AE6U, 0x49E14F17U, 0x839A6488U, 0xE3E09176U, 0xB9853498U, 0xFE6D9E42U, 0x982C4D22U, 0xD5F86DA9U, + 0xFF0F6A70U, 0x50FA7E56U, 0x82580EBFU, 0x5B5CF613U, 0x84E51D28U, 0x35314DE7U, 0x3E5B4696U, 0x19526D37U, + 0x66063BCAU, 0x7BD72D95U, 0x801EB0E6U, 0x49E959FDU, 0xC34567F8U, 0xB3A53F49U, 0x0FB35C0BU, 0x97DD6AD4U, + 0x11010B5CU, 0x62CC1CD4U, 0x81DCDAD1U, 0xF1553E98U, 0xFE254E48U, 0x78F9ECECU, 0xA9C457BFU, 0x5B776A4AU, + 0x8F659EFFU, 0x2D8D8A13U, 0x8493CC54U, 0x6C820621U, 0x4C059258U, 0x65FCDC54U, 0x6C636931U, 0x51B26353U, + 0xF862AE69U, 0x3496BB52U, 0x8551A663U, 0xD43E6144U, 0x7165BBE8U, 0xAEA00FF1U, 0xCA146285U, 0x9D1863CDU, + 0x616BFFD3U, 0x1FBBE891U, 0x8717183AU, 0xC68BCEAAU, 0x36C5C138U, 0x28347D5FU, 0xFBFC7818U, 0x1397642EU, + 0x166CCF45U, 0x06A0D9D0U, 0x86D5720DU, 0x7E37A9CFU, 0x0BA5E888U, 0xE368AEFAU, 0x5D8B73ACU, 0xDF3D64B0U, + 0xA00AE278U, 0x5E7EF3ECU, 0xA9E2D0A0U, 0xD67F4138U, 0x28D4C7DFU, 0x16441B82U, 0x03A0A617U, 0x83D02561U, + 0xD70DD2EEU, 0x4765C2ADU, 0xA820BA97U, 0x6EC3265DU, 0x15B4EE6FU, 0xDD18C827U, 0xA5D7ADA3U, 0x4F7A25FFU, + 0x4E048354U, 0x6C48916EU, 0xAA6604CEU, 0x7C7689B3U, 0x521494BFU, 0x5B8CBA89U, 0x943FB73EU, 0xC1F5221CU, + 0x3903B3C2U, 0x7553A02FU, 0xABA46EF9U, 0xC4CAEED6U, 0x6F74BD0FU, 0x90D0692CU, 0x3248BC8AU, 0x0D5F2282U, + 0xA7672661U, 0x3A1236E8U, 0xAEEB787CU, 0x591DD66FU, 0xDD54611FU, 0x8DD55994U, 0xF7EF8204U, 0x079A2B9BU, + 0xD06016F7U, 0x230907A9U, 0xAF29124BU, 0xE1A1B10AU, 0xE03448AFU, 0x46898A31U, 0x519889B0U, 0xCB302B05U, + 0x4969474DU, 0x0824546AU, 0xAD6FAC12U, 0xF3141EE4U, 0xA794327FU, 0xC01DF89FU, 0x6070932DU, 0x45BF2CE6U, + 0x3E6E77DBU, 0x113F652BU, 0xACADC625U, 0x4BA87981U, 0x9AF41BCFU, 0x0B412B3AU, 0xC6079899U, 0x89152C78U, + 0xAED16A4AU, 0x96A779E4U, 0xA7F18118U, 0x13CB69D7U, 0x18A48C1EU, 0xFA1799EFU, 0x304FE870U, 0x50353ED4U, + 0xD9D65ADCU, 0x8FBC48A5U, 0xA633EB2FU, 0xAB770EB2U, 0x25C4A5AEU, 0x314B4A4AU, 0x9638E3C4U, 0x9C9F3E4AU, + 0x40DF0B66U, 0xA4911B66U, 0xA4755576U, 0xB9C2A15CU, 0x6264DF7EU, 0xB7DF38E4U, 0xA7D0F959U, 0x121039A9U, + 0x37D83BF0U, 0xBD8A2A27U, 0xA5B73F41U, 0x017EC639U, 0x5F04F6CEU, 0x7C83EB41U, 0x01A7F2EDU, 0xDEBA3937U, + 0xA9BCAE53U, 0xF2CBBCE0U, 0xA0F829C4U, 0x9CA9FE80U, 0xED242ADEU, 0x6186DBF9U, 0xC400CC63U, 0xD47F302EU, + 0xDEBB9EC5U, 0xEBD08DA1U, 0xA13A43F3U, 0x241599E5U, 0xD044036EU, 0xAADA085CU, 0x6277C7D7U, 0x18D530B0U, + 0x47B2CF7FU, 0xC0FDDE62U, 0xA37CFDAAU, 0x36A0360BU, 0x97E479BEU, 0x2C4E7AF2U, 0x539FDD4AU, 0x965A3753U, + 0x30B5FFE9U, 0xD9E6EF23U, 0xA2BE979DU, 0x8E1C516EU, 0xAA84500EU, 0xE712A957U, 0xF5E8D6FEU, 0x5AF037CDU, + 0xBDBDF21CU, 0x14BCE1BDU, 0xB5C473D0U, 0x866616A7U, 0x4834505DU, 0x15921919U, 0x647E3AD9U, 0xFF6B144AU, + 0xCABAC28AU, 0x0DA7D0FCU, 0xB40619E7U, 0x3EDA71C2U, 0x755479EDU, 0xDECECABCU, 0xC209316DU, 0x33C114D4U, + 0x53B39330U, 0x268A833FU, 0xB640A7BEU, 0x2C6FDE2CU, 0x32F4033DU, 0x585AB812U, 0xF3E12BF0U, 0xBD4E1337U, + 0x24B4A3A6U, 0x3F91B27EU, 0xB782CD89U, 0x94D3B949U, 0x0F942A8DU, 0x93066BB7U, 0x55962044U, 0x71E413A9U, + 0xBAD03605U, 0x70D024B9U, 0xB2CDDB0CU, 0x090481F0U, 0xBDB4F69DU, 0x8E035B0FU, 0x90311ECAU, 0x7B211AB0U, + 0xCDD70693U, 0x69CB15F8U, 0xB30FB13BU, 0xB1B8E695U, 0x80D4DF2DU, 0x455F88AAU, 0x3646157EU, 0xB78B1A2EU, + 0x54DE5729U, 0x42E6463BU, 0xB1490F62U, 0xA30D497BU, 0xC774A5FDU, 0xC3CBFA04U, 0x07AE0FE3U, 0x39041DCDU, + 0x23D967BFU, 0x5BFD777AU, 0xB08B6555U, 0x1BB12E1EU, 0xFA148C4DU, 0x089729A1U, 0xA1D90457U, 0xF5AE1D53U, + 0xB3667A2EU, 0xDC656BB5U, 0xBBD72268U, 0x43D23E48U, 0x78441B9CU, 0xF9C19B74U, 0x579174BEU, 0x2C8E0FFFU, + 0xC4614AB8U, 0xC57E5AF4U, 0xBA15485FU, 0xFB6E592DU, 0x4524322CU, 0x329D48D1U, 0xF1E67F0AU, 0xE0240F61U, + 0x5D681B02U, 0xEE530937U, 0xB853F606U, 0xE9DBF6C3U, 0x028448FCU, 0xB4093A7FU, 0xC00E6597U, 0x6EAB0882U, + 0x2A6F2B94U, 0xF7483876U, 0xB9919C31U, 0x516791A6U, 0x3FE4614CU, 0x7F55E9DAU, 0x66796E23U, 0xA201081CU, + 0xB40BBE37U, 0xB809AEB1U, 0xBCDE8AB4U, 0xCCB0A91FU, 0x8DC4BD5CU, 0x6250D962U, 0xA3DE50ADU, 0xA8C40105U, + 0xC30C8EA1U, 0xA1129FF0U, 0xBD1CE083U, 0x740CCE7AU, 0xB0A494ECU, 0xA90C0AC7U, 0x05A95B19U, 0x646E019BU, + 0x5A05DF1BU, 0x8A3FCC33U, 0xBF5A5EDAU, 0x66B96194U, 0xF704EE3CU, 0x2F987869U, 0x34414184U, 0xEAE10678U, + 0x2D02EF8DU, 0x9324FD72U, 0xBE9834EDU, 0xDE0506F1U, 0xCA64C78CU, 0xE4C4ABCCU, 0x92364A30U, 0x264B06E6U, + }; + + uint32_t ulCrc32; + + if(pBuffer == NULL) + { + REDERROR(); + ulCrc32 = SUSPICIOUS_CRC_VALUE; + } + else + { + const uint8_t *pbBuffer = CAST_VOID_PTR_TO_CONST_UINT8_PTR(pBuffer); + uint32_t ulIdx = 0U; + const uint32_t *pulXorCrc0 = &aulCrc32Table[7U]; + const uint32_t *pulXorCrc1 = &aulCrc32Table[6U]; + const uint32_t *pulXorCrc2 = &aulCrc32Table[5U]; + const uint32_t *pulXorCrc3 = &aulCrc32Table[4U]; + const uint32_t *pulXorData4 = &aulCrc32Table[3U]; + const uint32_t *pulXorData5 = &aulCrc32Table[2U]; + const uint32_t *pulXorData6 = &aulCrc32Table[1U]; + const uint32_t *pulXorData7 = &aulCrc32Table[0U]; + uint32_t ulSliceLen; + + ulCrc32 = ~ulInitCrc32; + + /* Aligned memory access is used below. To avoid suboptimal + performance and faults (depending on platform), handle the + unaligned initial bytes (if any) using the Sarwate algorithm. + */ + while((ulIdx < ulLength) && !IS_ALIGNED_PTR(&pbBuffer[ulIdx])) + { + ulCrc32 = (ulCrc32 >> 8U) ^ aulCrc32Table[((ulCrc32 ^ pbBuffer[ulIdx]) & 0xFFU) << 3U]; + + ulIdx++; + } + + /* Round down the length to the nearest multiple of eight. + */ + ulSliceLen = (((ulLength - ulIdx) >> 3U) << 3U) + ulIdx; + + /* Compute the CRC in eight byte "slices". Takes advantage of + modern processors which can load in parallel from multiple + memory locations. + */ + while(ulIdx < ulSliceLen) + { + #if REDCONF_ENDIAN_BIG == 1 + ulCrc32 ^= pbBuffer[ulIdx] | ((uint32_t)pbBuffer[ulIdx+1U] << 8U) | + ((uint32_t)pbBuffer[ulIdx+2U] << 16U) | ((uint32_t)pbBuffer[ulIdx+3U] << 24U); + #else + ulCrc32 ^= *CAST_CONST_UINT32_PTR(&pbBuffer[ulIdx]); + #endif + + ulCrc32 = + pulXorCrc3[((ulCrc32 >> 24U) & 0xFFU) << 3U] ^ + pulXorCrc2[((ulCrc32 >> 16U) & 0xFFU) << 3U] ^ + pulXorCrc1[((ulCrc32 >> 8U) & 0xFFU) << 3U] ^ + pulXorCrc0[ (ulCrc32 & 0xFFU) << 3U] ^ + pulXorData7[pbBuffer[ulIdx+7U] << 3U] ^ + pulXorData6[pbBuffer[ulIdx+6U] << 3U] ^ + pulXorData5[pbBuffer[ulIdx+5U] << 3U] ^ + pulXorData4[pbBuffer[ulIdx+4U] << 3U]; + + ulIdx += 8U; + } + + /* Compute the remaining bytes with the Sarwate algorithm. + */ + while(ulIdx < ulLength) + { + ulCrc32 = (ulCrc32 >> 8U) ^ aulCrc32Table[((ulCrc32 ^ pbBuffer[ulIdx]) & 0xFFU) << 3U]; + + ulIdx++; + } + + ulCrc32 = ~ulCrc32; + } + + return ulCrc32; +} + +#else + +#error "REDCONF_CRC_ALGORITHM must be set to CRC_BITWISE, CRC_SARWATE, or CRC_SLICEBY8" + +#endif + + +/** @brief Compute a CRC32 for a metadata node buffer. + + @param pBuffer The metadata node buffer for which to compute a CRC. Must + be a block sized buffer. + + @return The CRC of the buffer. +*/ +uint32_t RedCrcNode( + const void *pBuffer) +{ + uint32_t ulCrc; + + if(pBuffer == NULL) + { + REDERROR(); + ulCrc = SUSPICIOUS_CRC_VALUE; + } + else + { + const uint8_t *pbBuffer = CAST_VOID_PTR_TO_CONST_UINT8_PTR(pBuffer); + + /* The first eight bytes of a metadata node contain the signature and + the CRC. There is little value in CRCing the signature, and the + CRC cannot be CRC'd, so skip over that part of the buffer. + */ + ulCrc = RedCrc32Update(0U, &pbBuffer[8U], REDCONF_BLOCK_SIZE - 8U); + } + + return ulCrc; +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/util/endian.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/util/endian.c new file mode 100644 index 0000000..3cc5452 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/util/endian.c @@ -0,0 +1,82 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements utilities for performing endian swaps. +*/ +#include + + +#ifdef REDCONF_ENDIAN_SWAP + +/** @brief Reverse the byte order of a 64-bit number. + + @param ullToRev Number whose bytes will be reversed + + @retval @p ullToRev with its bytes reversed. +*/ +uint64_t RedRev64( + uint64_t ullToRev) +{ + uint64_t ullRet = ullToRev; + + ullRet = ((ullRet & UINT64_SUFFIX(0x00000000FFFFFFFF)) << 32U) | ((ullRet & UINT64_SUFFIX(0xFFFFFFFF00000000)) >> 32U); + ullRet = ((ullRet & UINT64_SUFFIX(0x0000FFFF0000FFFF)) << 16U) | ((ullRet & UINT64_SUFFIX(0xFFFF0000FFFF0000)) >> 16U); + ullRet = ((ullRet & UINT64_SUFFIX(0x00FF00FF00FF00FF)) << 8U) | ((ullRet & UINT64_SUFFIX(0xFF00FF00FF00FF00)) >> 8U); + + return ullRet; +} + + +/** @brief Reverse the byte order of a 32-bit number. + + @param ulToRev Number whose bytes will be reversed + + @retval @p ulToRev with its bytes reversed. +*/ +uint32_t RedRev32( + uint32_t ulToRev) +{ + return ((ulToRev & 0x000000FFU) << 24U) + | ((ulToRev & 0x0000FF00U) << 8U) + | ((ulToRev & 0x00FF0000U) >> 8U) + | ((ulToRev & 0xFF000000U) >> 24U); +} + + +/** @brief Reverse the byte order of a 16-bit number. + + @param uToRev Number whose bytes will be reversed + + @retval @p uToRev with its bytes reversed. +*/ +uint16_t RedRev16( + uint16_t uToRev) +{ + return ((uToRev & 0xFF00U) >> 8U) + | ((uToRev & 0x00FFU) << 8U); +} + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/util/memory.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/util/memory.c new file mode 100644 index 0000000..3c30bae --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/util/memory.c @@ -0,0 +1,301 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Default implementations of memory manipulation functions. + + These implementations are intended to be small and simple, and thus forego + all optimizations. If the C library is available, or if there are better + third-party implementations available in the system, those can be used + instead by defining the appropriate macros in redconf.h. + + These functions are not intended to be completely 100% ANSI C compatible + implementations, but rather are designed to meet the needs of Reliance Edge. + The compatibility is close enough that ANSI C compatible implementations + can be "dropped in" as replacements without difficulty. +*/ +#include + + +#ifndef RedMemCpyUnchecked +static void RedMemCpyUnchecked(void *pDest, const void *pSrc, uint32_t ulLen); +#endif +#ifndef RedMemMoveUnchecked +static void RedMemMoveUnchecked(void *pDest, const void *pSrc, uint32_t ulLen); +#endif +#ifndef RedMemSetUnchecked +static void RedMemSetUnchecked(void *pDest, uint8_t bVal, uint32_t ulLen); +#endif +#ifndef RedMemCmpUnchecked +static int32_t RedMemCmpUnchecked(const void *pMem1, const void *pMem2, uint32_t ulLen); +#endif + + +/** @brief Copy memory from one address to another. + + The source and destination memory buffers should not overlap. If the + buffers overlap, use RedMemMove() instead. + + @param pDest The destination buffer. + @param pSrc The source buffer. + @param ulLen The number of bytes to copy. +*/ +void RedMemCpy( + void *pDest, + const void *pSrc, + uint32_t ulLen) +{ + if((pDest == NULL) || (pSrc == NULL)) + { + REDERROR(); + } + else + { + RedMemCpyUnchecked(pDest, pSrc, ulLen); + } +} + + +#ifndef RedMemCpyUnchecked +/** @brief Copy memory from one address to another. + + This function should only be called from RedMemCpy(). + + @param pDest The destination buffer. + @param pSrc The source buffer. + @param ulLen The number of bytes to copy. +*/ +static void RedMemCpyUnchecked( + void *pDest, + const void *pSrc, + uint32_t ulLen) +{ + uint8_t *pbDest = CAST_VOID_PTR_TO_UINT8_PTR(pDest); + const uint8_t *pbSrc = CAST_VOID_PTR_TO_CONST_UINT8_PTR(pSrc); + uint32_t ulIdx; + + for(ulIdx = 0U; ulIdx < ulLen; ulIdx++) + { + pbDest[ulIdx] = pbSrc[ulIdx]; + } +} +#endif + + +/** @brief Move memory from one address to another. + + Supports overlapping memory regions. If memory regions do not overlap, it + is generally better to use RedMemCpy() instead. + + @param pDest The destination buffer. + @param pSrc The source buffer. + @param ulLen The number of bytes to copy. +*/ +void RedMemMove( + void *pDest, + const void *pSrc, + uint32_t ulLen) +{ + if((pDest == NULL) || (pSrc == NULL)) + { + REDERROR(); + } + else + { + RedMemMoveUnchecked(pDest, pSrc, ulLen); + } +} + + +#ifndef RedMemMoveUnchecked +/** @brief Move memory from one address to another. + + This function should only be called from RedMemMove(). + + @param pDest The destination buffer. + @param pSrc The source buffer. + @param ulLen The number of bytes to copy. +*/ +static void RedMemMoveUnchecked( + void *pDest, + const void *pSrc, + uint32_t ulLen) +{ + uint8_t *pbDest = CAST_VOID_PTR_TO_UINT8_PTR(pDest); + const uint8_t *pbSrc = CAST_VOID_PTR_TO_CONST_UINT8_PTR(pSrc); + uint32_t ulIdx; + + if(MEMMOVE_MUST_COPY_FORWARD(pbDest, pbSrc)) + { + /* If the destination is lower than the source with overlapping memory + regions, we must copy from start to end in order to copy the memory + correctly. + + Don't use RedMemCpy() to do this. It is possible that RedMemCpy() + has been replaced (even though this function has not been replaced) + with an implementation that cannot handle any kind of buffer + overlap. + */ + for(ulIdx = 0U; ulIdx < ulLen; ulIdx++) + { + pbDest[ulIdx] = pbSrc[ulIdx]; + } + } + else + { + ulIdx = ulLen; + + while(ulIdx > 0U) + { + ulIdx--; + pbDest[ulIdx] = pbSrc[ulIdx]; + } + } +} +#endif /* RedMemMoveUnchecked */ + + +/** @brief Initialize a buffer with the specified byte value. + + @param pDest The buffer to initialize. + @param bVal The byte value with which to initialize @p pDest. + @param ulLen The number of bytes to initialize. +*/ +void RedMemSet( + void *pDest, + uint8_t bVal, + uint32_t ulLen) +{ + if(pDest == NULL) + { + REDERROR(); + } + else + { + RedMemSetUnchecked(pDest, bVal, ulLen); + } +} + + +#ifndef RedMemSetUnchecked +/** @brief Initialize a buffer with the specified byte value. + + This function should only be called from RedMemSet(). + + @param pDest The buffer to initialize. + @param bVal The byte value with which to initialize @p pDest. + @param ulLen The number of bytes to initialize. +*/ +static void RedMemSetUnchecked( + void *pDest, + uint8_t bVal, + uint32_t ulLen) +{ + uint8_t *pbDest = CAST_VOID_PTR_TO_UINT8_PTR(pDest); + uint32_t ulIdx; + + for(ulIdx = 0U; ulIdx < ulLen; ulIdx++) + { + pbDest[ulIdx] = bVal; + } +} +#endif + + +/** @brief Compare the contents of two buffers. + + @param pMem1 The first buffer to compare. + @param pMem2 The second buffer to compare. + @param ulLen The length to compare. + + @return Zero if the two buffers are the same, otherwise nonzero. + + @retval 0 @p pMem1 and @p pMem2 are the same. + @retval 1 @p pMem1 is greater than @p pMem2, as determined by the + values of the first differing bytes. + @retval -1 @p pMem2 is greater than @p pMem1, as determined by the + values of the first differing bytes. +*/ +int32_t RedMemCmp( + const void *pMem1, + const void *pMem2, + uint32_t ulLen) +{ + int32_t lResult; + + if((pMem1 == NULL) || (pMem2 == NULL)) + { + REDERROR(); + lResult = 0; + } + else + { + lResult = RedMemCmpUnchecked(pMem1, pMem2, ulLen); + } + + return lResult; +} + + +#ifndef RedMemCmpUnchecked +/** @brief Compare the contents of two buffers. + + @param pMem1 The first buffer to compare. + @param pMem2 The second buffer to compare. + @param ulLen The length to compare. + + @return Zero if the two buffers are the same, otherwise nonzero. +*/ +static int32_t RedMemCmpUnchecked( + const void *pMem1, + const void *pMem2, + uint32_t ulLen) +{ + const uint8_t *pbMem1 = CAST_VOID_PTR_TO_CONST_UINT8_PTR(pMem1); + const uint8_t *pbMem2 = CAST_VOID_PTR_TO_CONST_UINT8_PTR(pMem2); + uint32_t ulIdx = 0U; + int32_t lResult; + + while((ulIdx < ulLen) && (pbMem1[ulIdx] == pbMem2[ulIdx])) + { + ulIdx++; + } + + if(ulIdx == ulLen) + { + lResult = 0; + } + else if(pbMem1[ulIdx] > pbMem2[ulIdx]) + { + lResult = 1; + } + else + { + lResult = -1; + } + + return lResult; +} +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/util/namelen.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/util/namelen.c new file mode 100644 index 0000000..abf2c73 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/util/namelen.c @@ -0,0 +1,61 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements a utility to find the length of a name. +*/ +#include + +#if REDCONF_API_POSIX == 1 + + +/** @brief Determine the length of a name, terminated either by a null or a path + separator character. + + @param pszName The name whose length is to be determined. + + @return The length of the name. +*/ +uint32_t RedNameLen( + const char *pszName) +{ + uint32_t ulIdx = 0U; + + if(pszName == NULL) + { + REDERROR(); + } + else + { + while((pszName[ulIdx] != '\0') && (pszName[ulIdx] != REDCONF_PATH_SEPARATOR)) + { + ulIdx++; + } + } + + return ulIdx; +} + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/util/sign.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/util/sign.c new file mode 100644 index 0000000..d182ab1 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/util/sign.c @@ -0,0 +1,63 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Implements a sign on message. +*/ +#include + + +/** @brief Display the Reliance Edge signon message. +*/ +void RedSignOn(void) +{ + #if REDCONF_OUTPUT == 1 + + /* Use RedOsOutputString() instead of RedPrintf() to avoid using variadic + arguments, since this function is called from the driver and cannot use + functions that violate MISRA-C:2012. + */ + RedOsOutputString(RED_PRODUCT_NAME "\n"); + RedOsOutputString(RED_PRODUCT_EDITION "\n"); + RedOsOutputString(RED_PRODUCT_LEGAL "\n"); + RedOsOutputString(RED_PRODUCT_PATENT "\n"); + + #else + + /* Always embed the copyright into the program data. Use "volatile" to try + to avoid the compiler removing the variables. + */ + static volatile const char szVersion[] = RED_PRODUCT_NAME; + static volatile const char szEdition[] = RED_PRODUCT_EDITION; + static volatile const char szCopyright[] = RED_PRODUCT_LEGAL; + static volatile const char szPatent[] = RED_PRODUCT_PATENT; + + (void)szVersion; + (void)szEdition; + (void)szCopyright; + (void)szPatent; + + #endif +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/util/string.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/util/string.c new file mode 100644 index 0000000..46119d9 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/Reliance-Edge/util/string.c @@ -0,0 +1,329 @@ +/* ----> DO NOT REMOVE THE FOLLOWING NOTICE <---- + + Copyright (c) 2014-2015 Datalight, Inc. + All Rights Reserved Worldwide. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; use version 2 of the License. + + This program is distributed in the hope that it will be useful, + but "AS-IS," WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ +/* Businesses and individuals that for commercial or other reasons cannot + comply with the terms of the GPLv2 license may obtain a commercial license + before incorporating Reliance Edge into proprietary software for + distribution in any form. Visit http://www.datalight.com/reliance-edge for + more information. +*/ +/** @file + @brief Default implementations of string manipulation functions. + + These implementations are intended to be small and simple, and thus forego + all optimizations. If the C library is available, or if there are better + third-party implementations available in the system, those can be used + instead by defining the appropriate macros in redconf.h. + + These functions are not intended to be completely 100% ANSI C compatible + implementations, but rather are designed to meet the needs of Reliance Edge. + The compatibility is close enough that ANSI C compatible implementations + can be "dropped in" as replacements without difficulty. +*/ +#include + + +#ifndef RedStrLenUnchecked +static uint32_t RedStrLenUnchecked(const char *pszStr); +#endif +#ifndef RedStrCmpUnchecked +static int32_t RedStrCmpUnchecked(const char *pszStr1, const char *pszStr2); +#endif +#ifndef RedStrNCmpUnchecked +static int32_t RedStrNCmpUnchecked(const char *pszStr1, const char *pszStr2, uint32_t ulLen); +#endif +#ifndef RedStrNCpyUnchecked +static void RedStrNCpyUnchecked(char *pszDst, const char *pszSrc, uint32_t ulLen); +#endif + + +/** @brief Determine the length (in bytes) of a null terminated string. + + The length does not include the null terminator byte. + + @param pszStr The null terminated string whose length is to be determined. + + @return The length of the @p pszStr string. +*/ +uint32_t RedStrLen( + const char *pszStr) +{ + uint32_t ulLen; + + if(pszStr == NULL) + { + REDERROR(); + ulLen = 0U; + } + else + { + /* Cast the result to uint32_t, since RedStrLenUnchecked() might be + strlen(), which returns size_t, which is possibly a 64-bit value. + */ + ulLen = (uint32_t)RedStrLenUnchecked(pszStr); + } + + return ulLen; +} + + +#ifndef RedStrLenUnchecked +/** @brief Determine the length (in bytes) of a null terminated string. + + @param pszStr The null terminated string whose length is to be determined. + + @return The length of the @p pszStr string. +*/ +static uint32_t RedStrLenUnchecked( + const char *pszStr) +{ + uint32_t ulLen = 0U; + + while(pszStr[ulLen] != '\0') + { + ulLen++; + } + + return ulLen; +} +#endif + + +/** @brief Compare two null terminated strings. + + @param pszStr1 The first string to compare. + @param pszStr2 The second string to compare. + + @return Zero if the two strings are the same, otherwise nonzero. + + @retval 0 @p pszStr1 and @p pszStr2 are the same. + @retval 1 @p pszStr1 is greater than @p pszStr2, as determined by the + values of the first differing bytes. + @retval -1 @p pszStr2 is greater than @p pszStr1, as determined by the + values of the first differing bytes. +*/ +int32_t RedStrCmp( + const char *pszStr1, + const char *pszStr2) +{ + int32_t lResult; + + if((pszStr1 == NULL) || (pszStr2 == NULL)) + { + REDERROR(); + lResult = 0; + } + else + { + lResult = RedStrCmpUnchecked(pszStr1, pszStr2); + } + + return lResult; +} + + +#ifndef RedStrCmpUnchecked +/** @brief Compare two null terminated strings. + + @param pszStr1 The first string to compare. + @param pszStr2 The second string to compare. + + @return Zero if the two strings are the same, otherwise nonzero. +*/ +static int32_t RedStrCmpUnchecked( + const char *pszStr1, + const char *pszStr2) +{ + int32_t lResult; + uint32_t ulIdx = 0U; + + while((pszStr1[ulIdx] == pszStr2[ulIdx]) && (pszStr1[ulIdx] != '\0')) + { + ulIdx++; + } + + /* "The sign of a non-zero return value is determined by the sign of the + difference between the values of the first pair of bytes (both + interpreted as type unsigned char) that differ in the strings being + compared." Use uint8_t instead of unsigned char to avoid MISRA C + deviations. + */ + if((uint8_t)pszStr1[ulIdx] > (uint8_t)pszStr2[ulIdx]) + { + lResult = 1; + } + else if((uint8_t)pszStr1[ulIdx] < (uint8_t)pszStr2[ulIdx]) + { + lResult = -1; + } + else + { + lResult = 0; + } + + return lResult; +} +#endif + + +/** @brief Compare the first @p ulLen characters of two null terminated strings. + + @param pszStr1 The first string to compare. + @param pszStr2 The second string to compare. + @param ulLen The maximum length to compare. The comparison stops when + either of the strings end or when @p ulLen bytes have been + compared. + + @return Zero if the two strings are the same, otherwise nonzero. + + @retval 0 @p pszStr1 and @p pszStr2 are the same. + @retval 1 @p pszStr1 is greater than @p pszStr2, as determined by the + values of the first differing bytes. + @retval -1 @p pszStr2 is greater than @p pszStr1, as determined by the + values of the first differing bytes. +*/ +int32_t RedStrNCmp( + const char *pszStr1, + const char *pszStr2, + uint32_t ulLen) +{ + int32_t lResult; + + if((pszStr1 == NULL) || (pszStr2 == NULL)) + { + REDERROR(); + lResult = 0; + } + else + { + lResult = RedStrNCmpUnchecked(pszStr1, pszStr2, ulLen); + } + + return lResult; +} + + +#ifndef RedStrNCmpUnchecked +/** @brief Compare the first @p ulLen characters of two null terminated strings. + + @param pszStr1 The first string to compare. + @param pszStr2 The second string to compare. + @param ulLen The maximum length to compare. The comparison stops when + either of the strings end or when @p ulLen bytes have been + compared. + + @return Zero if the two strings are the same, otherwise nonzero. +*/ +static int32_t RedStrNCmpUnchecked( + const char *pszStr1, + const char *pszStr2, + uint32_t ulLen) +{ + int32_t lResult = 0; + uint32_t ulIdx; + + for(ulIdx = 0U; ulIdx < ulLen; ulIdx++) + { + if(pszStr1[ulIdx] != pszStr2[ulIdx]) + { + /* "The sign of a non-zero return value is determined by the sign + of the difference between the values of the first pair of bytes + (both interpreted as type unsigned char) that differ in the + strings being compared." Use uint8_t instead of unsigned char + to avoid MISRA C deviations. + */ + if((uint8_t)pszStr1[ulIdx] > (uint8_t)pszStr2[ulIdx]) + { + lResult = 1; + } + else + { + lResult = -1; + } + } + + if((lResult != 0) || (pszStr1[ulIdx] == '\0')) + { + break; + } + } + + return lResult; +} +#endif + + +/** @brief Copy a string. + + Copy up to @p ulLen bytes of a null-terminated string (@p pszSrc) to a + destination buffer (@p pszDst). The result will not be null-terminated if + @p pszSrc is longer than @p ulLen - 1 bytes. + + If @p pszSrc is shorter than @p ulLen - 1 bytes, the remainder of @p pszDst + will be filled with null bytes. + + @param pszDst The destination buffer, which is at least @p ulLen bytes + in size. + @param pszSrc The null-terminated string to copy. + @param ulLen The maximum number of characters to copy. +*/ +void RedStrNCpy( + char *pszDst, + const char *pszSrc, + uint32_t ulLen) +{ + if((pszDst == NULL) || (pszSrc == NULL)) + { + REDERROR(); + } + else + { + RedStrNCpyUnchecked(pszDst, pszSrc, ulLen); + } +} + + +#ifndef RedStrNCpyUnchecked +/** @brief Copy a string. + + @param pszDst The destination buffer, which is at least @p ulLen bytes + in size. + @param pszSrc The null-terminated string to copy. + @param ulLen The maximum number of characters to copy. +*/ +static void RedStrNCpyUnchecked( + char *pszDst, + const char *pszSrc, + uint32_t ulLen) +{ + uint32_t ulIdx = 0U; + + while((ulIdx < ulLen) && (pszSrc[ulIdx] != '\0')) + { + pszDst[ulIdx] = pszSrc[ulIdx]; + ulIdx++; + } + + while(ulIdx < ulLen) + { + pszDst[ulIdx] = '\0'; + ulIdx++; + } +} +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WebDocs.url b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WebDocs.url new file mode 100644 index 0000000..be5966f --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WebDocs.url @@ -0,0 +1,5 @@ +[InternetShortcut] +URL=http://www.freertos.org/plus +IDList= +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/AUTHORS b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/AUTHORS new file mode 100644 index 0000000..e69de29 diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/COPYING b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/COPYING new file mode 100644 index 0000000..d159169 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/COPYING @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Lesser General Public License instead.) You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. 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Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. The act of +running the Program is not restricted, and the output from the Program +is covered only if its contents constitute a work based on the +Program (independent of having been made by running the Program). +Whether that is true depends on what the Program does. + + 1. You may copy and distribute verbatim copies of the Program's +source code as you receive it, in any medium, provided that you +conspicuously and appropriately publish on each copy an appropriate +copyright notice and disclaimer of warranty; keep intact all the +notices that refer to this License and to the absence of any warranty; +and give any other recipients of the Program a copy of this License +along with the Program. + +You may charge a fee for the physical act of transferring a copy, and +you may at your option offer warranty protection in exchange for a fee. + + 2. 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But when you +distribute the same sections as part of a whole which is a work based +on the Program, the distribution of the whole must be on the terms of +this License, whose permissions for other licensees extend to the +entire whole, and thus to each and every part regardless of who wrote it. + +Thus, it is not the intent of this section to claim rights or contest +your rights to work written entirely by you; rather, the intent is to +exercise the right to control the distribution of derivative or +collective works based on the Program. + +In addition, mere aggregation of another work not based on the Program +with the Program (or with a work based on the Program) on a volume of +a storage or distribution medium does not bring the other work under +the scope of this License. + + 3. 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It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ChangeLog b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ChangeLog new file mode 100644 index 0000000..e69de29 diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/INSTALL b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/INSTALL new file mode 100644 index 0000000..b9249c0 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/INSTALL @@ -0,0 +1,45 @@ +0. Building on *nix from git repository + + Run the autogen script to generate configure, you'll need the autoconf tools + installed, then proceed to step 1. + + $ ./autogen.sh + +1. Building on *nix from a release + + $ ./configure + $ make + $ make check # (optional, but highly recommended) + $ sudo make install + +2. Building on iOS + + Use on the xcode project in IDE/iOS/wolfssl.xcodeproj + There is a README in IDE/iOS with more information + +3. Building on Windows + + Use the 32bit Visual Studio Solution wolfssl.sln + For a 64bit solution please use wolfssl64.sln + +4. Building with IAR + + Please see the README in IDE/IAR-EWARM for detailed instructions + +5. Building with Keil + + Please see the Keil Projects in IDE/MDK5-ARM/Projects + +6. Building with Microchip tools + + Please see the README in mplabx + +7. Building with Freescale MQX + + Please see the README in mqx + +8. Porting to a new platform + + Please see section 2.4 in the manual: + http://www.wolfssl.com/yaSSL/Docs-cyassl-manual-2-building-cyassl.html + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/LICENSING b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/LICENSING new file mode 100644 index 0000000..e43bb9f --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/LICENSING @@ -0,0 +1,11 @@ + +CyaSSL and wolfCrypt are either licensed for use under the GPLv2 or a +standard commercial license. For our users who cannot use CyaSSL under +GPLv2, a commercial license to CyaSSL and wolfCrypt is available. +Please contact wolfSSL Inc. directly at: + +Email: licensing@wolfssl.com +Phone: +1 425 245-8247 + +More information can be found on the wolfSSL website at www.wolfssl.com. + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/Makefile.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/Makefile.am new file mode 100644 index 0000000..5918a4d --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/Makefile.am @@ -0,0 +1,164 @@ +# includes append to these: +SUFFIXES = +TESTS = +CLEANFILES = +DISTCLEANFILES = +bin_PROGRAMS = +noinst_HEADERS = +lib_LTLIBRARIES = +man_MANS = +noinst_LTLIBRARIES = +noinst_PROGRAMS = +include_HEADERS = +nobase_include_HEADERS = +check_PROGRAMS = +EXTRA_HEADERS = +BUILT_SOURCES= +EXTRA_DIST= +dist_doc_DATA= + +#includes additional rules from aminclude.am +@INC_AMINCLUDE@ +DISTCLEANFILES+= aminclude.am + +CLEANFILES+= cert.der \ + cert.pem \ + certecc.der \ + certecc.pem \ + certreq.der \ + certreq.pem \ + key.der \ + key.pem \ + ntru-cert.der \ + ntru-cert.pem \ + ntru-key.raw \ + othercert.der \ + othercert.pem \ + pkcs7cert.der \ + pkcs7envelopedData.der \ + pkcs7signedData.der + +exampledir = $(docdir)/example +dist_example_DATA= + +ACLOCAL_AMFLAGS= -I m4 + +EXTRA_DIST+= lib/dummy + +EXTRA_DIST+= cyassl-ntru.vcproj +EXTRA_DIST+= cyassl.vcproj +EXTRA_DIST+= cyassl.vcxproj +EXTRA_DIST+= cyassl-iphone.xcodeproj/project.pbxproj +EXTRA_DIST+= cyassl-ios.xcodeproj/project.pbxproj +EXTRA_DIST+= cyassl-ntru.sln +EXTRA_DIST+= cyassl.sln +EXTRA_DIST+= cyassl64.sln +EXTRA_DIST+= valgrind-error.sh +EXTRA_DIST+= gencertbuf.pl +EXTRA_DIST+= IDE + +include cyassl/include.am +include certs/include.am +include certs/1024/include.am +include certs/crl/include.am +include doc/include.am +include swig/include.am + +include src/include.am +include support/include.am +include ctaocrypt/benchmark/include.am +include ctaocrypt/src/include.am +include ctaocrypt/test/include.am +include examples/client/include.am +include examples/server/include.am +include examples/echoclient/include.am +include examples/echoserver/include.am +include testsuite/include.am +include tests/include.am +include sslSniffer/sslSnifferTest/include.am +include rpm/include.am +include mqx/ctaocrypt_test/Sources/include.am +include mqx/cyassl/include.am +include mqx/cyassl_client/Sources/include.am +include mqx/util_lib/Sources/include.am +include mplabx/include.am +include mplabx/ctaocrypt_benchmark.X/nbproject/include.am +include mplabx/ctaocrypt_test.X/nbproject/include.am +include mplabx/cyassl.X/nbproject/include.am +include mcapi/include.am +include mcapi/ctaocrypt_mcapi.X/nbproject/include.am +include mcapi/ctaocrypt_test.X/nbproject/include.am +include mcapi/cyassl.X/nbproject/include.am +include mcapi/zlib.X/nbproject/include.am + +if USE_VALGRIND +TESTS_ENVIRONMENT=./valgrind-error.sh +endif + +TEST_EXTENSIONS=.test +TESTS += $(check_PROGRAMS) +test: check +tests/unit.log: testsuite/testsuite.log + +DISTCLEANFILES+= cyassl-config +# fips files shouldn't be left after make distclean +DISTCLEANFILES+= ctaocrypt/src/fips.c +DISTCLEANFILES+= ctaocrypt/src/fips_test.c + +maintainer-clean-local: + -rm Makefile.in + -rm aclocal.m4 + -rm build-aux/compile + -rm build-aux/config.guess + -rm build-aux/config.sub + -rm build-aux/depcomp + -rm build-aux/install-sh + -rm build-aux/ltmain.sh + -rm build-aux/missing + -rm cyassl-config + -rmdir build-aux + -rm configure + -rm config.log + -rm config.status + -rm config.in + -rm m4/libtool.m4 + -rm m4/ltoptions.m4 + -rm m4/ltsugar.m4 + -rm m4/ltversion.m4 + -rm m4/lt~obsolete.m4 + -rm support/cyassl.pc + find . -type f -name '*~' -exec rm -f '{}' \; + -rm -f @PACKAGE@-*.tar.gz + -rm -f @PACKAGE@-*.rpm + +# !!!! first line of rule has to start with a hard (real) tab, not spaces +egs: + $(MAKE) examples/client/client; \ + $(MAKE) examples/echoclient/echoclient;\ + $(MAKE) examples/server/server; \ + $(MAKE) examples/echoserver/echoserver; + +ctc: + $(MAKE) ctaocrypt/test/testctaocrypt; \ + $(MAKE) ctaocrypt/benchmark/benchmark; + +install-exec-local: install-generic-config + +install-generic-config: + $(mkinstalldirs) $(DESTDIR)$(bindir) + $(INSTALL_SCRIPT) @GENERIC_CONFIG@ $(DESTDIR)$(bindir) + +uninstall-local: + -rm -f $(DESTDIR)$(bindir)/@GENERIC_CONFIG@ + +merge-clean: + @find ./ | $(GREP) \.gcda | xargs rm -f + @find ./ | $(GREP) \.gcno | xargs rm -f + @find ./ | $(GREP) \.gz | xargs rm -f + @find ./ | $(GREP) \.orig | xargs rm -f + @find ./ | $(GREP) \.rej | xargs rm -f + @find ./ | $(GREP) \.rpm | xargs rm -f + @find ./ | $(GREP) \.THIS | xargs rm -f + @find ./ | $(GREP) \.OTHER | xargs rm -f + @find ./ | $(GREP) \.BASE | xargs rm -f + @find ./ | $(GREP) \~$$ | xargs rm -f diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/Makefile.in b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/Makefile.in new file mode 100644 index 0000000..fa6cbfb --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/Makefile.in @@ -0,0 +1,3090 @@ +# Makefile.in generated by automake 1.14.1 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994-2013 Free Software Foundation, Inc. + +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + +# vim:ft=automake +# All paths should be given relative to the root +# + +# vim:ft=automake +# All paths should be given relative to the root + +# vim:ft=automake +# All paths should be given relative to the root + +# vim:ft=automake +# All paths should be given relative to the root +# + +# vim:ft=automake +# All paths should be given relative to the root +# + +# vim:ft=automake +# All paths should be given relative to the root +# + +# vim:ft=automake +# included from Top Level Makefile.am +# All paths should be given relative to the root + +# vim:ft=automake +# All paths should be given relative to the root + +# vim:ft=automake +# included from Top Level Makefile.am +# All paths should be given relative to the root + +# vim:ft=automake +# All paths should be given relative to the root +# + +# vim:ft=automake +# All paths should be given relative to the root + +# vim:ft=automake +# All paths should be given relative to the root + +# vim:ft=automake +# All paths should be given relative to the root + +# vim:ft=automake +# All paths should be given relative to the root + +# vim:ft=automake +# included from Top Level Makefile.am +# All paths should be given relative to the root + +# vim:ft=automake +# included from Top Level Makefile.am +# All paths should be given relative to the root + +# vim:ft=automake +# included from Top Level Makefile.am +# All paths should be given relative to the root + +# vim:ft=automake +# included from Top Level Makefile.am +# All paths should be given relative to the root + +# vim:ft=automake +# included from Top Level Makefile.am +# All paths should be given relative to the root + +# vim:ft=automake +# included from Top Level Makefile.am +# All paths should be given relative to the root + +# vim:ft=automake + +# vim:ft=automake +# All paths should be given relative to the root +# + +# vim:ft=automake +# All paths should be given relative to the root +# + +# vim:ft=automake +# All paths should be given relative to the root +# + +# vim:ft=automake +# All paths should be given relative to the root +# + +# vim:ft=automake +# All paths should be given relative to the root +# + +# vim:ft=automake +# All paths should be given relative to the root +# + +# vim:ft=automake +# All paths should be given relative to the root +# + +# vim:ft=automake +# All paths should be given relative to the root +# + +# vim:ft=automake +# included from Top Level Makefile.am +# All paths should be given relative to the root + +# vim:ft=automake +# All paths should be given relative to the root +# + +# vim:ft=automake +# All paths should be given relative to the root +# + +# vim:ft=automake +# All paths should be given relative to the root +# + +# vim:ft=automake +# All paths should be given relative to the root +# + + + + +VPATH = @srcdir@ +am__is_gnu_make = test -n '$(MAKEFILE_LIST)' && test -n '$(MAKELEVEL)' +am__make_running_with_option = \ + case $${target_option-} in \ + ?) ;; \ + *) echo "am__make_running_with_option: internal error: invalid" \ + "target option '$${target_option-}' specified" >&2; \ + exit 1;; \ + esac; \ + has_opt=no; \ + sane_makeflags=$$MAKEFLAGS; \ + if $(am__is_gnu_make); then \ + sane_makeflags=$$MFLAGS; \ + else \ + case $$MAKEFLAGS in \ + *\\[\ \ ]*) \ + bs=\\; \ + sane_makeflags=`printf '%s\n' "$$MAKEFLAGS" \ + | sed "s/$$bs$$bs[$$bs $$bs ]*//g"`;; \ + esac; \ + fi; \ + skip_next=no; \ + strip_trailopt () \ + { \ + flg=`printf '%s\n' "$$flg" | sed "s/$$1.*$$//"`; \ + }; \ + for flg in $$sane_makeflags; do \ + test $$skip_next = yes && { skip_next=no; continue; }; \ + case $$flg in \ + *=*|--*) continue;; \ + -*I) strip_trailopt 'I'; skip_next=yes;; \ + -*I?*) strip_trailopt 'I';; \ + -*O) strip_trailopt 'O'; skip_next=yes;; \ + -*O?*) strip_trailopt 'O';; \ + -*l) strip_trailopt 'l'; skip_next=yes;; \ + -*l?*) strip_trailopt 'l';; \ + -[dEDm]) skip_next=yes;; \ + -[JT]) skip_next=yes;; \ + esac; \ + case $$flg in \ + *$$target_option*) has_opt=yes; break;; \ + esac; \ + done; \ + test $$has_opt = yes +am__make_dryrun = (target_option=n; $(am__make_running_with_option)) +am__make_keepgoing = (target_option=k; $(am__make_running_with_option)) +pkgdatadir = $(datadir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkglibexecdir = $(libexecdir)/@PACKAGE@ +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_triplet = @build@ +host_triplet = @host@ +bin_PROGRAMS = +noinst_PROGRAMS = ctaocrypt/benchmark/benchmark$(EXEEXT) \ + ctaocrypt/test/testctaocrypt$(EXEEXT) $(am__EXEEXT_3) \ + $(am__EXEEXT_4) $(am__EXEEXT_2) +check_PROGRAMS = $(am__EXEEXT_1) $(am__EXEEXT_2) +DIST_COMMON = $(srcdir)/cyassl/include.am \ + $(srcdir)/cyassl/ctaocrypt/include.am \ + $(srcdir)/cyassl/openssl/include.am $(srcdir)/certs/include.am \ + $(srcdir)/certs/1024/include.am $(srcdir)/certs/crl/include.am \ + $(srcdir)/doc/include.am $(srcdir)/swig/include.am \ + $(srcdir)/src/include.am $(srcdir)/support/include.am \ + $(srcdir)/ctaocrypt/benchmark/include.am \ + $(srcdir)/ctaocrypt/src/include.am \ + $(srcdir)/ctaocrypt/test/include.am \ + $(srcdir)/examples/client/include.am \ + $(srcdir)/examples/server/include.am \ + $(srcdir)/examples/echoclient/include.am \ + $(srcdir)/examples/echoserver/include.am \ + $(srcdir)/testsuite/include.am $(srcdir)/tests/include.am \ + $(srcdir)/sslSniffer/sslSnifferTest/include.am \ + $(srcdir)/rpm/include.am \ + $(srcdir)/mqx/ctaocrypt_test/Sources/include.am \ + $(srcdir)/mqx/cyassl/include.am \ + $(srcdir)/mqx/cyassl_client/Sources/include.am \ + $(srcdir)/mqx/util_lib/Sources/include.am \ + $(srcdir)/mplabx/include.am \ + $(srcdir)/mplabx/ctaocrypt_benchmark.X/nbproject/include.am \ + $(srcdir)/mplabx/ctaocrypt_test.X/nbproject/include.am \ + $(srcdir)/mplabx/cyassl.X/nbproject/include.am \ + $(srcdir)/mcapi/include.am \ + $(srcdir)/mcapi/ctaocrypt_mcapi.X/nbproject/include.am \ + $(srcdir)/mcapi/ctaocrypt_test.X/nbproject/include.am \ + $(srcdir)/mcapi/cyassl.X/nbproject/include.am \ + $(srcdir)/mcapi/zlib.X/nbproject/include.am \ + $(srcdir)/Makefile.in $(srcdir)/Makefile.am \ + $(top_srcdir)/configure $(am__configure_deps) \ + $(srcdir)/config.in $(srcdir)/stamp-h.in \ + $(top_srcdir)/cyassl/version.h.in \ + $(top_srcdir)/cyassl/options.h.in \ + $(top_srcdir)/support/cyassl.pc.in $(top_srcdir)/rpm/spec.in \ + $(top_srcdir)/build-aux/depcomp $(dist_doc_DATA) \ + $(dist_example_DATA) $(include_HEADERS) \ + $(nobase_include_HEADERS) $(am__noinst_HEADERS_DIST) \ + $(top_srcdir)/build-aux/test-driver AUTHORS COPYING ChangeLog \ + NEWS README build-aux/compile build-aux/config.guess \ + build-aux/config.sub build-aux/depcomp build-aux/install-sh \ + build-aux/missing build-aux/ltmain.sh \ + $(top_srcdir)/build-aux/compile \ + $(top_srcdir)/build-aux/config.guess \ + $(top_srcdir)/build-aux/config.sub \ + $(top_srcdir)/build-aux/install-sh \ + $(top_srcdir)/build-aux/ltmain.sh \ + $(top_srcdir)/build-aux/missing +@BUILD_FIPS_TRUE@am__append_1 = ctaocrypt/src/wolfcrypt_first.c +@BUILD_MEMORY_TRUE@am__append_2 = ctaocrypt/src/memory.c +@BUILD_RSA_TRUE@am__append_3 = ctaocrypt/src/rsa.c +@BUILD_DH_TRUE@am__append_4 = ctaocrypt/src/dh.c +@BUILD_ASN_TRUE@am__append_5 = ctaocrypt/src/asn.c +@BUILD_FIPS_TRUE@am__append_6 = ctaocrypt/src/fips.c \ +@BUILD_FIPS_TRUE@ ctaocrypt/src/fips_test.c +@BUILD_CODING_TRUE@am__append_7 = ctaocrypt/src/coding.c +@BUILD_AES_TRUE@am__append_8 = ctaocrypt/src/aes.c +@BUILD_DES3_TRUE@am__append_9 = ctaocrypt/src/des3.c +@BUILD_SHA_TRUE@am__append_10 = ctaocrypt/src/sha.c +@BUILD_RC4_TRUE@am__append_11 = ctaocrypt/src/arc4.c +@BUILD_MD4_TRUE@am__append_12 = ctaocrypt/src/md4.c +@BUILD_MD5_TRUE@am__append_13 = ctaocrypt/src/md5.c +@BUILD_PWDBASED_TRUE@am__append_14 = ctaocrypt/src/pwdbased.c +@BUILD_DSA_TRUE@am__append_15 = ctaocrypt/src/dsa.c +@BUILD_AESNI_TRUE@am__append_16 = ctaocrypt/src/aes_asm.s +@BUILD_CAMELLIA_TRUE@am__append_17 = ctaocrypt/src/camellia.c +@BUILD_MD2_TRUE@am__append_18 = ctaocrypt/src/md2.c +@BUILD_RIPEMD_TRUE@am__append_19 = ctaocrypt/src/ripemd.c +@BUILD_SHA512_TRUE@am__append_20 = ctaocrypt/src/sha512.c +@BUILD_BLAKE2_TRUE@am__append_21 = ctaocrypt/src/blake2b.c +@BUILD_SNIFFER_TRUE@am__append_22 = src/sniffer.c +@BUILD_HC128_TRUE@am__append_23 = ctaocrypt/src/hc128.c +@BUILD_RABBIT_TRUE@am__append_24 = ctaocrypt/src/rabbit.c +@BUILD_INLINE_FALSE@am__append_25 = ctaocrypt/src/misc.c +@BUILD_FASTMATH_TRUE@am__append_26 = ctaocrypt/src/tfm.c +@BUILD_SLOWMATH_TRUE@am__append_27 = ctaocrypt/src/integer.c +@BUILD_ECC_TRUE@am__append_28 = ctaocrypt/src/ecc.c +@BUILD_OCSP_TRUE@am__append_29 = src/ocsp.c +@BUILD_CRL_TRUE@am__append_30 = src/crl.c +@BUILD_LIBZ_TRUE@am__append_31 = ctaocrypt/src/compress.c +@BUILD_PKCS7_TRUE@am__append_32 = ctaocrypt/src/pkcs7.c +@BUILD_FIPS_TRUE@am__append_33 = ctaocrypt/src/wolfcrypt_last.c +@BUILD_EXAMPLES_TRUE@am__append_34 = examples/client/client \ +@BUILD_EXAMPLES_TRUE@ examples/server/server \ +@BUILD_EXAMPLES_TRUE@ examples/echoclient/echoclient \ +@BUILD_EXAMPLES_TRUE@ examples/echoserver/echoserver \ +@BUILD_EXAMPLES_TRUE@ testsuite/testsuite.test tests/unit.test +@BUILD_EXAMPLES_TRUE@am__append_35 = examples/client/client.h \ +@BUILD_EXAMPLES_TRUE@ examples/server/server.h \ +@BUILD_EXAMPLES_TRUE@ examples/echoclient/echoclient.h \ +@BUILD_EXAMPLES_TRUE@ examples/echoserver/echoserver.h +@BUILD_EXAMPLES_TRUE@am__append_36 = testsuite/testsuite.test \ +@BUILD_EXAMPLES_TRUE@ tests/unit.test +@BUILD_SNIFFTEST_TRUE@am__append_37 = sslSniffer/sslSnifferTest/snifftest +@BUILD_MCAPI_TRUE@am__append_38 = mcapi/test +@BUILD_MCAPI_TRUE@am__append_39 = mcapi/test +subdir = . +ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +am__aclocal_m4_deps = $(top_srcdir)/m4/ax_add_am_macro.m4 \ + $(top_srcdir)/m4/ax_am_jobserver.m4 \ + $(top_srcdir)/m4/ax_am_macros.m4 \ + $(top_srcdir)/m4/ax_append_compile_flags.m4 \ + $(top_srcdir)/m4/ax_append_flag.m4 \ + $(top_srcdir)/m4/ax_append_to_file.m4 \ + $(top_srcdir)/m4/ax_check_compile_flag.m4 \ + $(top_srcdir)/m4/ax_check_link_flag.m4 \ + $(top_srcdir)/m4/ax_count_cpus.m4 \ + $(top_srcdir)/m4/ax_create_generic_config.m4 \ + $(top_srcdir)/m4/ax_debug.m4 \ + $(top_srcdir)/m4/ax_file_escapes.m4 \ + $(top_srcdir)/m4/ax_harden_compiler_flags.m4 \ + $(top_srcdir)/m4/ax_print_to_file.m4 \ + $(top_srcdir)/m4/ax_pthread.m4 $(top_srcdir)/m4/ax_tls.m4 \ + $(top_srcdir)/m4/ax_vcs_checkout.m4 \ + $(top_srcdir)/m4/hexversion.m4 \ + $(top_srcdir)/m4/lib_socket_nsl.m4 $(top_srcdir)/m4/libtool.m4 \ + $(top_srcdir)/m4/ltoptions.m4 $(top_srcdir)/m4/ltsugar.m4 \ + $(top_srcdir)/m4/ltversion.m4 $(top_srcdir)/m4/lt~obsolete.m4 \ + $(top_srcdir)/m4/visibility.m4 \ + $(top_srcdir)/m4/wolfssl_darwin_clang.m4 \ + $(top_srcdir)/configure.ac +am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) +am__CONFIG_DISTCLEAN_FILES = config.status config.cache config.log \ + configure.lineno config.status.lineno +mkinstalldirs = $(install_sh) -d +CONFIG_HEADER = config.h +CONFIG_CLEAN_FILES = stamp-h cyassl/version.h cyassl/options.h \ + support/cyassl.pc rpm/spec +CONFIG_CLEAN_VPATH_FILES = +am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; +am__vpath_adj = case $$p in \ + $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \ + *) f=$$p;; \ + esac; +am__strip_dir = f=`echo $$p | sed -e 's|^.*/||'`; +am__install_max = 40 +am__nobase_strip_setup = \ + srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*|]/\\\\&/g'` +am__nobase_strip = \ + for p in $$list; do echo "$$p"; done | sed -e "s|$$srcdirstrip/||" +am__nobase_list = $(am__nobase_strip_setup); \ + for p in $$list; do echo "$$p $$p"; done | \ + sed "s| $$srcdirstrip/| |;"' / .*\//!s/ .*/ ./; s,\( .*\)/[^/]*$$,\1,' | \ + $(AWK) 'BEGIN { files["."] = "" } { files[$$2] = files[$$2] " " $$1; \ + if (++n[$$2] == $(am__install_max)) \ + { print $$2, files[$$2]; n[$$2] = 0; files[$$2] = "" } } \ + END { for (dir in files) print dir, files[dir] }' +am__base_list = \ + sed '$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;s/\n/ /g' | \ + sed '$$!N;$$!N;$$!N;$$!N;s/\n/ /g' +am__uninstall_files_from_dir = { \ + test -z "$$files" \ + || { test ! -d "$$dir" && test ! -f "$$dir" && test ! -r "$$dir"; } \ + || { echo " ( cd '$$dir' && rm -f" $$files ")"; \ + $(am__cd) "$$dir" && rm -f $$files; }; \ + } +am__installdirs = "$(DESTDIR)$(libdir)" "$(DESTDIR)$(bindir)" \ + "$(DESTDIR)$(docdir)" "$(DESTDIR)$(exampledir)" \ + "$(DESTDIR)$(pkgconfigdir)" "$(DESTDIR)$(includedir)" \ + "$(DESTDIR)$(includedir)" +LTLIBRARIES = $(lib_LTLIBRARIES) $(noinst_LTLIBRARIES) +am__DEPENDENCIES_1 = +src_libcyassl_la_DEPENDENCIES = $(am__DEPENDENCIES_1) +am__src_libcyassl_la_SOURCES_DIST = ctaocrypt/src/wolfcrypt_first.c \ + src/internal.c src/io.c src/keys.c src/ssl.c src/tls.c \ + ctaocrypt/src/hmac.c ctaocrypt/src/random.c \ + ctaocrypt/src/sha256.c ctaocrypt/src/logging.c \ + ctaocrypt/src/wc_port.c ctaocrypt/src/error.c \ + ctaocrypt/src/memory.c ctaocrypt/src/rsa.c ctaocrypt/src/dh.c \ + ctaocrypt/src/asn.c ctaocrypt/src/fips.c \ + ctaocrypt/src/fips_test.c ctaocrypt/src/coding.c \ + ctaocrypt/src/aes.c ctaocrypt/src/des3.c ctaocrypt/src/sha.c \ + ctaocrypt/src/arc4.c ctaocrypt/src/md4.c ctaocrypt/src/md5.c \ + ctaocrypt/src/pwdbased.c ctaocrypt/src/dsa.c \ + ctaocrypt/src/aes_asm.s ctaocrypt/src/camellia.c \ + ctaocrypt/src/md2.c ctaocrypt/src/ripemd.c \ + ctaocrypt/src/sha512.c ctaocrypt/src/blake2b.c src/sniffer.c \ + ctaocrypt/src/hc128.c ctaocrypt/src/rabbit.c \ + ctaocrypt/src/misc.c ctaocrypt/src/tfm.c \ + ctaocrypt/src/integer.c ctaocrypt/src/ecc.c src/ocsp.c \ + src/crl.c ctaocrypt/src/compress.c ctaocrypt/src/pkcs7.c \ + ctaocrypt/src/wolfcrypt_last.c +am__dirstamp = $(am__leading_dot)dirstamp +@BUILD_FIPS_TRUE@am__objects_1 = ctaocrypt/src/src_libcyassl_la-wolfcrypt_first.lo +@BUILD_MEMORY_TRUE@am__objects_2 = \ +@BUILD_MEMORY_TRUE@ ctaocrypt/src/src_libcyassl_la-memory.lo +@BUILD_RSA_TRUE@am__objects_3 = ctaocrypt/src/src_libcyassl_la-rsa.lo +@BUILD_DH_TRUE@am__objects_4 = ctaocrypt/src/src_libcyassl_la-dh.lo +@BUILD_ASN_TRUE@am__objects_5 = ctaocrypt/src/src_libcyassl_la-asn.lo +@BUILD_FIPS_TRUE@am__objects_6 = \ +@BUILD_FIPS_TRUE@ ctaocrypt/src/src_libcyassl_la-fips.lo \ +@BUILD_FIPS_TRUE@ ctaocrypt/src/src_libcyassl_la-fips_test.lo +@BUILD_CODING_TRUE@am__objects_7 = \ +@BUILD_CODING_TRUE@ ctaocrypt/src/src_libcyassl_la-coding.lo +@BUILD_AES_TRUE@am__objects_8 = ctaocrypt/src/src_libcyassl_la-aes.lo +@BUILD_DES3_TRUE@am__objects_9 = \ +@BUILD_DES3_TRUE@ ctaocrypt/src/src_libcyassl_la-des3.lo +@BUILD_SHA_TRUE@am__objects_10 = \ +@BUILD_SHA_TRUE@ ctaocrypt/src/src_libcyassl_la-sha.lo +@BUILD_RC4_TRUE@am__objects_11 = \ +@BUILD_RC4_TRUE@ ctaocrypt/src/src_libcyassl_la-arc4.lo +@BUILD_MD4_TRUE@am__objects_12 = \ +@BUILD_MD4_TRUE@ ctaocrypt/src/src_libcyassl_la-md4.lo +@BUILD_MD5_TRUE@am__objects_13 = \ +@BUILD_MD5_TRUE@ ctaocrypt/src/src_libcyassl_la-md5.lo +@BUILD_PWDBASED_TRUE@am__objects_14 = ctaocrypt/src/src_libcyassl_la-pwdbased.lo +@BUILD_DSA_TRUE@am__objects_15 = \ +@BUILD_DSA_TRUE@ ctaocrypt/src/src_libcyassl_la-dsa.lo +@BUILD_AESNI_TRUE@am__objects_16 = ctaocrypt/src/aes_asm.lo +@BUILD_CAMELLIA_TRUE@am__objects_17 = ctaocrypt/src/src_libcyassl_la-camellia.lo +@BUILD_MD2_TRUE@am__objects_18 = \ +@BUILD_MD2_TRUE@ ctaocrypt/src/src_libcyassl_la-md2.lo +@BUILD_RIPEMD_TRUE@am__objects_19 = \ +@BUILD_RIPEMD_TRUE@ ctaocrypt/src/src_libcyassl_la-ripemd.lo +@BUILD_SHA512_TRUE@am__objects_20 = \ +@BUILD_SHA512_TRUE@ ctaocrypt/src/src_libcyassl_la-sha512.lo +@BUILD_BLAKE2_TRUE@am__objects_21 = \ +@BUILD_BLAKE2_TRUE@ ctaocrypt/src/src_libcyassl_la-blake2b.lo +@BUILD_SNIFFER_TRUE@am__objects_22 = src/src_libcyassl_la-sniffer.lo +@BUILD_HC128_TRUE@am__objects_23 = \ +@BUILD_HC128_TRUE@ ctaocrypt/src/src_libcyassl_la-hc128.lo +@BUILD_RABBIT_TRUE@am__objects_24 = \ +@BUILD_RABBIT_TRUE@ ctaocrypt/src/src_libcyassl_la-rabbit.lo +@BUILD_INLINE_FALSE@am__objects_25 = \ +@BUILD_INLINE_FALSE@ ctaocrypt/src/src_libcyassl_la-misc.lo +@BUILD_FASTMATH_TRUE@am__objects_26 = \ +@BUILD_FASTMATH_TRUE@ ctaocrypt/src/src_libcyassl_la-tfm.lo +@BUILD_SLOWMATH_TRUE@am__objects_27 = ctaocrypt/src/src_libcyassl_la-integer.lo +@BUILD_ECC_TRUE@am__objects_28 = \ +@BUILD_ECC_TRUE@ ctaocrypt/src/src_libcyassl_la-ecc.lo +@BUILD_OCSP_TRUE@am__objects_29 = src/src_libcyassl_la-ocsp.lo +@BUILD_CRL_TRUE@am__objects_30 = src/src_libcyassl_la-crl.lo +@BUILD_LIBZ_TRUE@am__objects_31 = \ +@BUILD_LIBZ_TRUE@ ctaocrypt/src/src_libcyassl_la-compress.lo +@BUILD_PKCS7_TRUE@am__objects_32 = \ +@BUILD_PKCS7_TRUE@ ctaocrypt/src/src_libcyassl_la-pkcs7.lo +@BUILD_FIPS_TRUE@am__objects_33 = ctaocrypt/src/src_libcyassl_la-wolfcrypt_last.lo +am_src_libcyassl_la_OBJECTS = $(am__objects_1) \ + src/src_libcyassl_la-internal.lo src/src_libcyassl_la-io.lo \ + src/src_libcyassl_la-keys.lo src/src_libcyassl_la-ssl.lo \ + src/src_libcyassl_la-tls.lo \ + ctaocrypt/src/src_libcyassl_la-hmac.lo \ + ctaocrypt/src/src_libcyassl_la-random.lo \ + ctaocrypt/src/src_libcyassl_la-sha256.lo \ + ctaocrypt/src/src_libcyassl_la-logging.lo \ + ctaocrypt/src/src_libcyassl_la-wc_port.lo \ + ctaocrypt/src/src_libcyassl_la-error.lo $(am__objects_2) \ + $(am__objects_3) $(am__objects_4) $(am__objects_5) \ + $(am__objects_6) $(am__objects_7) $(am__objects_8) \ + $(am__objects_9) $(am__objects_10) $(am__objects_11) \ + $(am__objects_12) $(am__objects_13) $(am__objects_14) \ + $(am__objects_15) $(am__objects_16) $(am__objects_17) \ + $(am__objects_18) $(am__objects_19) $(am__objects_20) \ + $(am__objects_21) $(am__objects_22) $(am__objects_23) \ + $(am__objects_24) $(am__objects_25) $(am__objects_26) \ + $(am__objects_27) $(am__objects_28) $(am__objects_29) \ + $(am__objects_30) $(am__objects_31) $(am__objects_32) \ + $(am__objects_33) +src_libcyassl_la_OBJECTS = $(am_src_libcyassl_la_OBJECTS) +AM_V_lt = $(am__v_lt_@AM_V@) +am__v_lt_ = $(am__v_lt_@AM_DEFAULT_V@) +am__v_lt_0 = --silent +am__v_lt_1 = +src_libcyassl_la_LINK = $(LIBTOOL) $(AM_V_lt) --tag=CC \ + $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=link $(CCLD) \ + $(src_libcyassl_la_CFLAGS) $(CFLAGS) \ + $(src_libcyassl_la_LDFLAGS) $(LDFLAGS) -o $@ +@BUILD_EXAMPLES_TRUE@am__EXEEXT_1 = testsuite/testsuite.test$(EXEEXT) \ +@BUILD_EXAMPLES_TRUE@ tests/unit.test$(EXEEXT) +@BUILD_MCAPI_TRUE@am__EXEEXT_2 = mcapi/test$(EXEEXT) +@BUILD_EXAMPLES_TRUE@am__EXEEXT_3 = examples/client/client$(EXEEXT) \ +@BUILD_EXAMPLES_TRUE@ examples/server/server$(EXEEXT) \ +@BUILD_EXAMPLES_TRUE@ examples/echoclient/echoclient$(EXEEXT) \ +@BUILD_EXAMPLES_TRUE@ examples/echoserver/echoserver$(EXEEXT) \ +@BUILD_EXAMPLES_TRUE@ testsuite/testsuite.test$(EXEEXT) \ +@BUILD_EXAMPLES_TRUE@ tests/unit.test$(EXEEXT) +@BUILD_SNIFFTEST_TRUE@am__EXEEXT_4 = sslSniffer/sslSnifferTest/snifftest$(EXEEXT) +PROGRAMS = $(bin_PROGRAMS) $(noinst_PROGRAMS) +am_ctaocrypt_benchmark_benchmark_OBJECTS = \ + ctaocrypt/benchmark/benchmark.$(OBJEXT) +ctaocrypt_benchmark_benchmark_OBJECTS = \ + $(am_ctaocrypt_benchmark_benchmark_OBJECTS) +am_ctaocrypt_test_testctaocrypt_OBJECTS = \ + ctaocrypt/test/test.$(OBJEXT) +ctaocrypt_test_testctaocrypt_OBJECTS = \ + $(am_ctaocrypt_test_testctaocrypt_OBJECTS) +am__examples_client_client_SOURCES_DIST = examples/client/client.c +@BUILD_EXAMPLES_TRUE@am_examples_client_client_OBJECTS = \ +@BUILD_EXAMPLES_TRUE@ examples/client/client.$(OBJEXT) +examples_client_client_OBJECTS = $(am_examples_client_client_OBJECTS) +am__examples_echoclient_echoclient_SOURCES_DIST = \ + examples/echoclient/echoclient.c +@BUILD_EXAMPLES_TRUE@am_examples_echoclient_echoclient_OBJECTS = \ +@BUILD_EXAMPLES_TRUE@ examples/echoclient/echoclient.$(OBJEXT) +examples_echoclient_echoclient_OBJECTS = \ + $(am_examples_echoclient_echoclient_OBJECTS) +am__examples_echoserver_echoserver_SOURCES_DIST = \ + examples/echoserver/echoserver.c +@BUILD_EXAMPLES_TRUE@am_examples_echoserver_echoserver_OBJECTS = \ +@BUILD_EXAMPLES_TRUE@ examples/echoserver/echoserver.$(OBJEXT) +examples_echoserver_echoserver_OBJECTS = \ + $(am_examples_echoserver_echoserver_OBJECTS) +am__examples_server_server_SOURCES_DIST = examples/server/server.c +@BUILD_EXAMPLES_TRUE@am_examples_server_server_OBJECTS = \ +@BUILD_EXAMPLES_TRUE@ examples/server/server.$(OBJEXT) +examples_server_server_OBJECTS = $(am_examples_server_server_OBJECTS) +am__mcapi_test_SOURCES_DIST = mcapi/crypto.c mcapi/mcapi_test.c +@BUILD_MCAPI_TRUE@am_mcapi_test_OBJECTS = mcapi/crypto.$(OBJEXT) \ +@BUILD_MCAPI_TRUE@ mcapi/mcapi_test.$(OBJEXT) +mcapi_test_OBJECTS = $(am_mcapi_test_OBJECTS) +am__sslSniffer_sslSnifferTest_snifftest_SOURCES_DIST = \ + sslSniffer/sslSnifferTest/snifftest.c +@BUILD_SNIFFTEST_TRUE@am_sslSniffer_sslSnifferTest_snifftest_OBJECTS = sslSniffer/sslSnifferTest/snifftest.$(OBJEXT) +sslSniffer_sslSnifferTest_snifftest_OBJECTS = \ + $(am_sslSniffer_sslSnifferTest_snifftest_OBJECTS) +am__tests_unit_test_SOURCES_DIST = tests/unit.c tests/api.c \ + tests/suites.c tests/hash.c examples/client/client.c \ + examples/server/server.c +@BUILD_EXAMPLES_TRUE@am_tests_unit_test_OBJECTS = \ +@BUILD_EXAMPLES_TRUE@ tests/tests_unit_test-unit.$(OBJEXT) \ +@BUILD_EXAMPLES_TRUE@ tests/tests_unit_test-api.$(OBJEXT) \ +@BUILD_EXAMPLES_TRUE@ tests/tests_unit_test-suites.$(OBJEXT) \ +@BUILD_EXAMPLES_TRUE@ tests/tests_unit_test-hash.$(OBJEXT) \ +@BUILD_EXAMPLES_TRUE@ examples/client/tests_unit_test-client.$(OBJEXT) \ +@BUILD_EXAMPLES_TRUE@ examples/server/tests_unit_test-server.$(OBJEXT) +tests_unit_test_OBJECTS = $(am_tests_unit_test_OBJECTS) +tests_unit_test_LINK = $(LIBTOOL) $(AM_V_lt) --tag=CC \ + $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=link $(CCLD) \ + $(tests_unit_test_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) \ + -o $@ +am__testsuite_testsuite_test_SOURCES_DIST = ctaocrypt/test/test.c \ + examples/client/client.c examples/echoclient/echoclient.c \ + examples/echoserver/echoserver.c examples/server/server.c \ + testsuite/testsuite.c +@BUILD_EXAMPLES_TRUE@am_testsuite_testsuite_test_OBJECTS = ctaocrypt/test/testsuite_testsuite_test-test.$(OBJEXT) \ +@BUILD_EXAMPLES_TRUE@ examples/client/testsuite_testsuite_test-client.$(OBJEXT) \ +@BUILD_EXAMPLES_TRUE@ examples/echoclient/testsuite_testsuite_test-echoclient.$(OBJEXT) \ +@BUILD_EXAMPLES_TRUE@ examples/echoserver/testsuite_testsuite_test-echoserver.$(OBJEXT) \ +@BUILD_EXAMPLES_TRUE@ examples/server/testsuite_testsuite_test-server.$(OBJEXT) \ +@BUILD_EXAMPLES_TRUE@ testsuite/testsuite_testsuite_test-testsuite.$(OBJEXT) +testsuite_testsuite_test_OBJECTS = \ + $(am_testsuite_testsuite_test_OBJECTS) +testsuite_testsuite_test_LINK = $(LIBTOOL) $(AM_V_lt) --tag=CC \ + $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=link $(CCLD) \ + $(testsuite_testsuite_test_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \ + $(LDFLAGS) -o $@ +AM_V_P = $(am__v_P_@AM_V@) +am__v_P_ = $(am__v_P_@AM_DEFAULT_V@) +am__v_P_0 = false +am__v_P_1 = : +AM_V_GEN = $(am__v_GEN_@AM_V@) +am__v_GEN_ = $(am__v_GEN_@AM_DEFAULT_V@) +am__v_GEN_0 = @echo " GEN " $@; +am__v_GEN_1 = +AM_V_at = $(am__v_at_@AM_V@) +am__v_at_ = $(am__v_at_@AM_DEFAULT_V@) +am__v_at_0 = @ +am__v_at_1 = +DEFAULT_INCLUDES = -I.@am__isrc@ +depcomp = $(SHELL) $(top_srcdir)/build-aux/depcomp +am__depfiles_maybe = depfiles +am__mv = mv -f +COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ + $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +LTCOMPILE = $(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) \ + $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) \ + $(AM_CFLAGS) $(CFLAGS) +AM_V_CC = $(am__v_CC_@AM_V@) +am__v_CC_ = $(am__v_CC_@AM_DEFAULT_V@) +am__v_CC_0 = @echo " CC " $@; +am__v_CC_1 = +CCLD = $(CC) +LINK = $(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(AM_LDFLAGS) $(LDFLAGS) -o $@ +AM_V_CCLD = $(am__v_CCLD_@AM_V@) +am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@) +am__v_CCLD_0 = @echo " CCLD " $@; +am__v_CCLD_1 = +CCASCOMPILE = $(CCAS) $(AM_CCASFLAGS) $(CCASFLAGS) +LTCCASCOMPILE = $(LIBTOOL) $(AM_V_lt) $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=compile $(CCAS) $(AM_CCASFLAGS) \ + $(CCASFLAGS) +AM_V_CCAS = $(am__v_CCAS_@AM_V@) +am__v_CCAS_ = $(am__v_CCAS_@AM_DEFAULT_V@) +am__v_CCAS_0 = @echo " CCAS " $@; +am__v_CCAS_1 = +SOURCES = $(src_libcyassl_la_SOURCES) \ + $(ctaocrypt_benchmark_benchmark_SOURCES) \ + $(ctaocrypt_test_testctaocrypt_SOURCES) \ + $(examples_client_client_SOURCES) \ + $(examples_echoclient_echoclient_SOURCES) \ + $(examples_echoserver_echoserver_SOURCES) \ + $(examples_server_server_SOURCES) $(mcapi_test_SOURCES) \ + $(sslSniffer_sslSnifferTest_snifftest_SOURCES) \ + $(tests_unit_test_SOURCES) $(testsuite_testsuite_test_SOURCES) +DIST_SOURCES = $(am__src_libcyassl_la_SOURCES_DIST) \ + $(ctaocrypt_benchmark_benchmark_SOURCES) \ + $(ctaocrypt_test_testctaocrypt_SOURCES) \ + $(am__examples_client_client_SOURCES_DIST) \ + $(am__examples_echoclient_echoclient_SOURCES_DIST) \ + $(am__examples_echoserver_echoserver_SOURCES_DIST) \ + $(am__examples_server_server_SOURCES_DIST) \ + $(am__mcapi_test_SOURCES_DIST) \ + $(am__sslSniffer_sslSnifferTest_snifftest_SOURCES_DIST) \ + $(am__tests_unit_test_SOURCES_DIST) \ + $(am__testsuite_testsuite_test_SOURCES_DIST) +am__can_run_installinfo = \ + case $$AM_UPDATE_INFO_DIR in \ + n|no|NO) false;; \ + *) (install-info --version) >/dev/null 2>&1;; \ + esac +DATA = $(dist_doc_DATA) $(dist_example_DATA) $(pkgconfig_DATA) +am__noinst_HEADERS_DIST = cyassl/internal.h ctaocrypt/test/test.h \ + examples/client/client.h examples/server/server.h \ + examples/echoclient/echoclient.h \ + examples/echoserver/echoserver.h mcapi/crypto.h +HEADERS = $(include_HEADERS) $(nobase_include_HEADERS) \ + $(noinst_HEADERS) +am__tagged_files = $(HEADERS) $(SOURCES) $(TAGS_FILES) \ + $(LISP)config.in +# Read a list of newline-separated strings from the standard input, +# and print each of them once, without duplicates. Input order is +# *not* preserved. +am__uniquify_input = $(AWK) '\ + BEGIN { nonempty = 0; } \ + { items[$$0] = 1; nonempty = 1; } \ + END { if (nonempty) { for (i in items) print i; }; } \ +' +# Make sure the list of sources is unique. This is necessary because, +# e.g., the same source file might be shared among _SOURCES variables +# for different programs/libraries. +am__define_uniq_tagged_files = \ + list='$(am__tagged_files)'; \ + unique=`for i in $$list; do \ + if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ + done | $(am__uniquify_input)` +ETAGS = etags +CTAGS = ctags +CSCOPE = cscope +AM_RECURSIVE_TARGETS = cscope check recheck +am__tty_colors_dummy = \ + mgn= red= grn= lgn= blu= brg= std=; \ + am__color_tests=no +am__tty_colors = { \ + $(am__tty_colors_dummy); \ + if test "X$(AM_COLOR_TESTS)" = Xno; then \ + am__color_tests=no; \ + elif test "X$(AM_COLOR_TESTS)" = Xalways; then \ + am__color_tests=yes; \ + elif test "X$$TERM" != Xdumb && { test -t 1; } 2>/dev/null; then \ + am__color_tests=yes; \ + fi; \ + if test $$am__color_tests = yes; then \ + red=''; \ + grn=''; \ + lgn=''; \ + blu=''; \ + mgn=''; \ + brg=''; \ + std=''; \ + fi; \ +} +am__recheck_rx = ^[ ]*:recheck:[ ]* +am__global_test_result_rx = ^[ ]*:global-test-result:[ ]* +am__copy_in_global_log_rx = ^[ ]*:copy-in-global-log:[ ]* +# A command that, given a newline-separated list of test names on the +# standard input, print the name of the tests that are to be re-run +# upon "make recheck". +am__list_recheck_tests = $(AWK) '{ \ + recheck = 1; \ + while ((rc = (getline line < ($$0 ".trs"))) != 0) \ + { \ + if (rc < 0) \ + { \ + if ((getline line2 < ($$0 ".log")) < 0) \ + recheck = 0; \ + break; \ + } \ + else if (line ~ /$(am__recheck_rx)[nN][Oo]/) \ + { \ + recheck = 0; \ + break; \ + } \ + else if (line ~ /$(am__recheck_rx)[yY][eE][sS]/) \ + { \ + break; \ + } \ + }; \ + if (recheck) \ + print $$0; \ + close ($$0 ".trs"); \ + close ($$0 ".log"); \ +}' +# A command that, given a newline-separated list of test names on the +# standard input, create the global log from their .trs and .log files. +am__create_global_log = $(AWK) ' \ +function fatal(msg) \ +{ \ + print "fatal: making $@: " msg | "cat >&2"; \ + exit 1; \ +} \ +function rst_section(header) \ +{ \ + print header; \ + len = length(header); \ + for (i = 1; i <= len; i = i + 1) \ + printf "="; \ + printf "\n\n"; \ +} \ +{ \ + copy_in_global_log = 1; \ + global_test_result = "RUN"; \ + while ((rc = (getline line < ($$0 ".trs"))) != 0) \ + { \ + if (rc < 0) \ + fatal("failed to read from " $$0 ".trs"); \ + if (line ~ /$(am__global_test_result_rx)/) \ + { \ + sub("$(am__global_test_result_rx)", "", line); \ + sub("[ ]*$$", "", line); \ + global_test_result = line; \ + } \ + else if (line ~ /$(am__copy_in_global_log_rx)[nN][oO]/) \ + copy_in_global_log = 0; \ + }; \ + if (copy_in_global_log) \ + { \ + rst_section(global_test_result ": " $$0); \ + while ((rc = (getline line < ($$0 ".log"))) != 0) \ + { \ + if (rc < 0) \ + fatal("failed to read from " $$0 ".log"); \ + print line; \ + }; \ + printf "\n"; \ + }; \ + close ($$0 ".trs"); \ + close ($$0 ".log"); \ +}' +# Restructured Text title. +am__rst_title = { sed 's/.*/ & /;h;s/./=/g;p;x;s/ *$$//;p;g' && echo; } +# Solaris 10 'make', and several other traditional 'make' implementations, +# pass "-e" to $(SHELL), and POSIX 2008 even requires this. Work around it +# by disabling -e (using the XSI extension "set +e") if it's set. +am__sh_e_setup = case $$- in *e*) set +e;; esac +# Default flags passed to test drivers. +am__common_driver_flags = \ + --color-tests "$$am__color_tests" \ + --enable-hard-errors "$$am__enable_hard_errors" \ + --expect-failure "$$am__expect_failure" +# To be inserted before the command running the test. Creates the +# directory for the log if needed. Stores in $dir the directory +# containing $f, in $tst the test, in $log the log. Executes the +# developer- defined test setup AM_TESTS_ENVIRONMENT (if any), and +# passes TESTS_ENVIRONMENT. Set up options for the wrapper that +# will run the test scripts (or their associated LOG_COMPILER, if +# thy have one). +am__check_pre = \ +$(am__sh_e_setup); \ +$(am__vpath_adj_setup) $(am__vpath_adj) \ +$(am__tty_colors); \ +srcdir=$(srcdir); export srcdir; \ +case "$@" in \ + */*) am__odir=`echo "./$@" | sed 's|/[^/]*$$||'`;; \ + *) am__odir=.;; \ +esac; \ +test "x$$am__odir" = x"." || test -d "$$am__odir" \ + || $(MKDIR_P) "$$am__odir" || exit $$?; \ +if test -f "./$$f"; then dir=./; \ +elif test -f "$$f"; then dir=; \ +else dir="$(srcdir)/"; fi; \ +tst=$$dir$$f; log='$@'; \ +if test -n '$(DISABLE_HARD_ERRORS)'; then \ + am__enable_hard_errors=no; \ +else \ + am__enable_hard_errors=yes; \ +fi; \ +case " $(XFAIL_TESTS) " in \ + *[\ \ ]$$f[\ \ ]* | *[\ \ ]$$dir$$f[\ \ ]*) \ + am__expect_failure=yes;; \ + *) \ + am__expect_failure=no;; \ +esac; \ +$(AM_TESTS_ENVIRONMENT) $(TESTS_ENVIRONMENT) +# A shell command to get the names of the tests scripts with any registered +# extension removed (i.e., equivalently, the names of the test logs, with +# the '.log' extension removed). The result is saved in the shell variable +# '$bases'. This honors runtime overriding of TESTS and TEST_LOGS. Sadly, +# we cannot use something simpler, involving e.g., "$(TEST_LOGS:.log=)", +# since that might cause problem with VPATH rewrites for suffix-less tests. +# See also 'test-harness-vpath-rewrite.sh' and 'test-trs-basic.sh'. +am__set_TESTS_bases = \ + bases='$(TEST_LOGS)'; \ + bases=`for i in $$bases; do echo $$i; done | sed 's/\.log$$//'`; \ + bases=`echo $$bases` +RECHECK_LOGS = $(TEST_LOGS) +TEST_SUITE_LOG = test-suite.log +LOG_DRIVER = $(SHELL) $(top_srcdir)/build-aux/test-driver +LOG_COMPILE = $(LOG_COMPILER) $(AM_LOG_FLAGS) $(LOG_FLAGS) +am__set_b = \ + case '$@' in \ + */*) \ + case '$*' in \ + */*) b='$*';; \ + *) b=`echo '$@' | sed 's/\.log$$//'`; \ + esac;; \ + *) \ + b='$*';; \ + esac +am__test_logs1 = $(TESTS:=.log) +am__test_logs2 = $(am__test_logs1:@EXEEXT@.log=.log) +TEST_LOGS = $(am__test_logs2:.test.log=.log) +TEST_LOG_DRIVER = $(SHELL) $(top_srcdir)/build-aux/test-driver +TEST_LOG_COMPILE = $(TEST_LOG_COMPILER) $(AM_TEST_LOG_FLAGS) \ + $(TEST_LOG_FLAGS) +DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) +distdir = $(PACKAGE)-$(VERSION) +top_distdir = $(distdir) +am__remove_distdir = \ + if test -d "$(distdir)"; then \ + find "$(distdir)" -type d ! -perm -200 -exec chmod u+w {} ';' \ + && rm -rf "$(distdir)" \ + || { sleep 5 && rm -rf "$(distdir)"; }; \ + else :; fi +am__post_remove_distdir = $(am__remove_distdir) +DIST_ARCHIVES = $(distdir).tar.gz +GZIP_ENV = --best +DIST_TARGETS = dist-gzip +distuninstallcheck_listfiles = find . -type f -print +am__distuninstallcheck_listfiles = $(distuninstallcheck_listfiles) \ + | sed 's|^\./|$(prefix)/|' | grep -v '$(infodir)/dir$$' +distcleancheck_listfiles = find . -type f -print +ACLOCAL = @ACLOCAL@ +AMINCLUDE = @AMINCLUDE@ +AMTAR = @AMTAR@ +AM_CFLAGS = @AM_CFLAGS@ +AM_CPPFLAGS = @AM_CPPFLAGS@ +AM_DEFAULT_VERBOSITY = @AM_DEFAULT_VERBOSITY@ +AM_LDFLAGS = @AM_LDFLAGS@ +AR = @AR@ +AUTOCONF = @AUTOCONF@ +AUTOHEADER = @AUTOHEADER@ +AUTOMAKE = @AUTOMAKE@ +AWK = @AWK@ +CC = @CC@ +CCAS = @CCAS@ +CCASDEPMODE = @CCASDEPMODE@ +CCASFLAGS = @CCASFLAGS@ +CCDEPMODE = @CCDEPMODE@ +CFLAGS = @CFLAGS@ +CFLAG_VISIBILITY = @CFLAG_VISIBILITY@ +CPP = @CPP@ +CPPFLAGS = @CPPFLAGS@ +CXX = @CXX@ +CXXCPP = @CXXCPP@ +CXXDEPMODE = @CXXDEPMODE@ +CXXFLAGS = @CXXFLAGS@ +CYASSL_LIBRARY_VERSION = @CYASSL_LIBRARY_VERSION@ +CYGPATH_W = @CYGPATH_W@ +DEFS = @DEFS@ +DEPDIR = @DEPDIR@ +DLLTOOL = @DLLTOOL@ +DSYMUTIL = @DSYMUTIL@ +DUMPBIN = @DUMPBIN@ +ECHO_C = @ECHO_C@ +ECHO_N = @ECHO_N@ +ECHO_T = @ECHO_T@ +EGREP = @EGREP@ +EXEEXT = @EXEEXT@ +FGREP = @FGREP@ +GENERIC_CONFIG = @GENERIC_CONFIG@ +GREP = @GREP@ +HAVE_OPENSSL_CMD = @HAVE_OPENSSL_CMD@ +HAVE_VALGRIND = @HAVE_VALGRIND@ +HAVE_VISIBILITY = @HAVE_VISIBILITY@ +HEX_VERSION = @HEX_VERSION@ +INC_AMINCLUDE = @INC_AMINCLUDE@ +INSTALL = @INSTALL@ +INSTALL_DATA = @INSTALL_DATA@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ +INSTALL_SCRIPT = @INSTALL_SCRIPT@ +INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ +LD = @LD@ +LDFLAGS = @LDFLAGS@ +LIBM = @LIBM@ +LIBOBJS = @LIBOBJS@ +LIBS = @LIBS@ +LIBTOOL = @LIBTOOL@ +LIPO = @LIPO@ +LN_S = @LN_S@ +LTLIBOBJS = @LTLIBOBJS@ +MAKEINFO = @MAKEINFO@ +MANIFEST_TOOL = @MANIFEST_TOOL@ +MCHECK = @MCHECK@ +MKDIR_P = @MKDIR_P@ +NM = @NM@ +NMEDIT = @NMEDIT@ +OBJDUMP = @OBJDUMP@ +OBJEXT = @OBJEXT@ +OTOOL = @OTOOL@ +OTOOL64 = @OTOOL64@ +PACKAGE = @PACKAGE@ +PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ +PACKAGE_NAME = @PACKAGE_NAME@ +PACKAGE_STRING = @PACKAGE_STRING@ +PACKAGE_TARNAME = @PACKAGE_TARNAME@ +PACKAGE_URL = @PACKAGE_URL@ +PACKAGE_VERSION = @PACKAGE_VERSION@ +PATH_SEPARATOR = @PATH_SEPARATOR@ +PTHREAD_CC = @PTHREAD_CC@ +PTHREAD_CFLAGS = @PTHREAD_CFLAGS@ +PTHREAD_LIBS = @PTHREAD_LIBS@ +RANLIB = @RANLIB@ +SED = @SED@ +SET_MAKE = @SET_MAKE@ +SHELL = @SHELL@ +STRIP = @STRIP@ +VERSION = @VERSION@ +abs_builddir = @abs_builddir@ +abs_srcdir = @abs_srcdir@ +abs_top_builddir = @abs_top_builddir@ +abs_top_srcdir = @abs_top_srcdir@ +ac_ct_AR = @ac_ct_AR@ +ac_ct_CC = @ac_ct_CC@ +ac_ct_CXX = @ac_ct_CXX@ +ac_ct_DUMPBIN = @ac_ct_DUMPBIN@ +am__include = @am__include@ +am__leading_dot = @am__leading_dot@ +am__quote = @am__quote@ +am__tar = @am__tar@ +am__untar = @am__untar@ +ax_pthread_config = @ax_pthread_config@ +bindir = @bindir@ +build = @build@ +build_alias = @build_alias@ +build_cpu = @build_cpu@ +build_os = @build_os@ +build_vendor = @build_vendor@ +builddir = @builddir@ +datadir = @datadir@ +datarootdir = @datarootdir@ +docdir = @docdir@ +dvidir = @dvidir@ +exec_prefix = @exec_prefix@ +host = @host@ +host_alias = @host_alias@ +host_cpu = @host_cpu@ +host_os = @host_os@ +host_vendor = @host_vendor@ +htmldir = @htmldir@ +includedir = @includedir@ +infodir = @infodir@ +install_sh = @install_sh@ +libdir = @libdir@ +libexecdir = @libexecdir@ +localedir = @localedir@ +localstatedir = @localstatedir@ +mandir = @mandir@ +mkdir_p = @mkdir_p@ +oldincludedir = @oldincludedir@ +pdfdir = @pdfdir@ +prefix = @prefix@ +program_transform_name = @program_transform_name@ +psdir = @psdir@ +sbindir = @sbindir@ +sharedstatedir = @sharedstatedir@ +srcdir = @srcdir@ +sysconfdir = @sysconfdir@ +target_alias = @target_alias@ +top_build_prefix = @top_build_prefix@ +top_builddir = @top_builddir@ +top_srcdir = @top_srcdir@ + +# includes append to these: +SUFFIXES = +TESTS = $(check_PROGRAMS) +CLEANFILES = cert.der cert.pem certecc.der certecc.pem certreq.der \ + certreq.pem key.der key.pem ntru-cert.der ntru-cert.pem \ + ntru-key.raw othercert.der othercert.pem pkcs7cert.der \ + pkcs7envelopedData.der pkcs7signedData.der +# fips files shouldn't be left after make distclean +DISTCLEANFILES = aminclude.am ctaocrypt/benchmark/.libs/benchmark \ + ctaocrypt/test/.libs/testctaocrypt \ + examples/client/.libs/client examples/server/.libs/server \ + examples/echoclient/.libs/echoclient \ + examples/echoserver/.libs/echoserver \ + testsuite/.libs/testsuite.test tests/.libs/unit.test \ + sslSniffer/sslSnifferTest/.libs/snifftest cyassl-config \ + ctaocrypt/src/fips.c ctaocrypt/src/fips_test.c +noinst_HEADERS = cyassl/internal.h ctaocrypt/test/test.h \ + $(am__append_35) mcapi/crypto.h +lib_LTLIBRARIES = src/libcyassl.la +man_MANS = +noinst_LTLIBRARIES = +include_HEADERS = +nobase_include_HEADERS = cyassl/ctaocrypt/aes.h \ + cyassl/ctaocrypt/arc4.h cyassl/ctaocrypt/asn.h \ + cyassl/ctaocrypt/asn_public.h cyassl/ctaocrypt/camellia.h \ + cyassl/ctaocrypt/coding.h cyassl/ctaocrypt/compress.h \ + cyassl/ctaocrypt/des3.h cyassl/ctaocrypt/dh.h \ + cyassl/ctaocrypt/dsa.h cyassl/ctaocrypt/ecc.h \ + cyassl/ctaocrypt/error-crypt.h cyassl/ctaocrypt/fips_test.h \ + cyassl/ctaocrypt/hc128.h cyassl/ctaocrypt/hmac.h \ + cyassl/ctaocrypt/integer.h cyassl/ctaocrypt/md2.h \ + cyassl/ctaocrypt/md4.h cyassl/ctaocrypt/md5.h \ + cyassl/ctaocrypt/misc.h cyassl/ctaocrypt/pkcs7.h \ + cyassl/ctaocrypt/wc_port.h cyassl/ctaocrypt/pwdbased.h \ + cyassl/ctaocrypt/rabbit.h cyassl/ctaocrypt/random.h \ + cyassl/ctaocrypt/ripemd.h cyassl/ctaocrypt/rsa.h \ + cyassl/ctaocrypt/settings.h cyassl/ctaocrypt/sha256.h \ + cyassl/ctaocrypt/sha512.h cyassl/ctaocrypt/sha.h \ + cyassl/ctaocrypt/blake2.h cyassl/ctaocrypt/blake2-int.h \ + cyassl/ctaocrypt/blake2-impl.h cyassl/ctaocrypt/tfm.h \ + cyassl/ctaocrypt/types.h cyassl/ctaocrypt/visibility.h \ + cyassl/ctaocrypt/logging.h cyassl/ctaocrypt/memory.h \ + cyassl/ctaocrypt/mpi_class.h cyassl/ctaocrypt/mpi_superclass.h \ + cyassl/openssl/asn1.h cyassl/openssl/bio.h cyassl/openssl/bn.h \ + cyassl/openssl/conf.h cyassl/openssl/crypto.h \ + cyassl/openssl/des.h cyassl/openssl/dh.h cyassl/openssl/dsa.h \ + cyassl/openssl/ecdsa.h cyassl/openssl/ec.h \ + cyassl/openssl/engine.h cyassl/openssl/err.h \ + cyassl/openssl/evp.h cyassl/openssl/hmac.h \ + cyassl/openssl/lhash.h cyassl/openssl/md4.h \ + cyassl/openssl/md5.h cyassl/openssl/ripemd.h \ + cyassl/openssl/ocsp.h cyassl/openssl/opensslconf.h \ + cyassl/openssl/opensslv.h cyassl/openssl/ossl_typ.h \ + cyassl/openssl/pem.h cyassl/openssl/pkcs12.h \ + cyassl/openssl/rand.h cyassl/openssl/rsa.h \ + cyassl/openssl/sha.h cyassl/openssl/ssl.h \ + cyassl/openssl/stack.h cyassl/openssl/ui.h \ + cyassl/openssl/x509.h cyassl/openssl/x509v3.h \ + cyassl/error-ssl.h cyassl/ssl.h cyassl/sniffer_error.h \ + cyassl/sniffer.h cyassl/callbacks.h cyassl/certs_test.h \ + cyassl/test.h cyassl/version.h cyassl/options.h cyassl/ocsp.h \ + cyassl/crl.h +EXTRA_HEADERS = +BUILT_SOURCES = +EXTRA_DIST = lib/dummy cyassl-ntru.vcproj cyassl.vcproj cyassl.vcxproj \ + cyassl-iphone.xcodeproj/project.pbxproj \ + cyassl-ios.xcodeproj/project.pbxproj cyassl-ntru.sln \ + cyassl.sln cyassl64.sln valgrind-error.sh gencertbuf.pl IDE \ + cyassl/sniffer_error.rc certs/ca-cert.pem certs/ca-key.pem \ + certs/client-cert.pem certs/client-keyEnc.pem \ + certs/client-key.pem certs/ecc-key.pem certs/ecc-keyPkcs8.pem \ + certs/ecc-client-key.pem certs/client-ecc-cert.pem \ + certs/ntru-cert.pem certs/dh2048.pem certs/server-cert.pem \ + certs/server-ecc.pem certs/server-ecc-rsa.pem \ + certs/server-keyEnc.pem certs/server-key.pem \ + certs/server-keyPkcs8Enc12.pem certs/server-keyPkcs8Enc2.pem \ + certs/server-keyPkcs8Enc.pem certs/server-keyPkcs8.pem \ + certs/ca-key.der certs/ca-cert.der certs/client-cert.der \ + certs/client-key.der certs/dh2048.der certs/rsa2048.der \ + certs/dsa2048.der certs/ecc-key.der certs/server-key.der \ + certs/server-cert.der certs/ntru-key.raw \ + certs/1024/client-cert.pem certs/1024/client-key.pem \ + certs/1024/dh1024.pem certs/1024/dsa1024.pem \ + certs/1024/client-cert.der certs/1024/client-key.der \ + certs/1024/dh1024.der certs/1024/dsa1024.der \ + certs/1024/rsa1024.der certs/crl/crl.pem certs/crl/cliCrl.pem \ + certs/crl/eccSrvCRL.pem certs/crl/eccCliCRL.pem \ + certs/crl/crl.revoked swig/PythonBuild.sh swig/README \ + swig/cyassl.i swig/cyassl_adds.c swig/python_cyassl.vcproj \ + swig/rsasign.py swig/runme.py support/cyassl.pc \ + ctaocrypt/benchmark/benchmark.sln \ + ctaocrypt/benchmark/benchmark.vcproj ctaocrypt/src/misc.c \ + ctaocrypt/src/asm.c ctaocrypt/src/aes_asm.asm \ + ctaocrypt/src/ecc_fp.c ctaocrypt/src/fp_mont_small.i \ + ctaocrypt/src/fp_mul_comba_12.i \ + ctaocrypt/src/fp_mul_comba_17.i \ + ctaocrypt/src/fp_mul_comba_20.i \ + ctaocrypt/src/fp_mul_comba_24.i \ + ctaocrypt/src/fp_mul_comba_28.i \ + ctaocrypt/src/fp_mul_comba_32.i ctaocrypt/src/fp_mul_comba_3.i \ + ctaocrypt/src/fp_mul_comba_48.i ctaocrypt/src/fp_mul_comba_4.i \ + ctaocrypt/src/fp_mul_comba_64.i ctaocrypt/src/fp_mul_comba_6.i \ + ctaocrypt/src/fp_mul_comba_7.i ctaocrypt/src/fp_mul_comba_8.i \ + ctaocrypt/src/fp_mul_comba_9.i \ + ctaocrypt/src/fp_mul_comba_small_set.i \ + ctaocrypt/src/fp_sqr_comba_12.i \ + ctaocrypt/src/fp_sqr_comba_17.i \ + ctaocrypt/src/fp_sqr_comba_20.i \ + ctaocrypt/src/fp_sqr_comba_24.i \ + ctaocrypt/src/fp_sqr_comba_28.i \ + ctaocrypt/src/fp_sqr_comba_32.i ctaocrypt/src/fp_sqr_comba_3.i \ + ctaocrypt/src/fp_sqr_comba_48.i ctaocrypt/src/fp_sqr_comba_4.i \ + ctaocrypt/src/fp_sqr_comba_64.i ctaocrypt/src/fp_sqr_comba_6.i \ + ctaocrypt/src/fp_sqr_comba_7.i ctaocrypt/src/fp_sqr_comba_8.i \ + ctaocrypt/src/fp_sqr_comba_9.i \ + ctaocrypt/src/fp_sqr_comba_small_set.i ctaocrypt/test/test.sln \ + ctaocrypt/test/test.vcproj examples/client/client.sln \ + examples/client/client-ntru.vcproj \ + examples/client/client.vcproj examples/client/client.vcxproj \ + examples/server/server.sln examples/server/server-ntru.vcproj \ + examples/server/server.vcproj examples/server/server.vcxproj \ + examples/echoclient/echoclient.sln \ + examples/echoclient/echoclient-ntru.vcproj \ + examples/echoclient/echoclient.vcproj \ + examples/echoclient/echoclient.vcxproj \ + examples/echoserver/echoserver.sln \ + examples/echoserver/echoserver-ntru.vcproj \ + examples/echoserver/echoserver.vcproj \ + examples/echoserver/echoserver.vcxproj testsuite/testsuite.sln \ + testsuite/testsuite-ntru.vcproj testsuite/testsuite.vcproj \ + testsuite/testsuite.vcxproj input quit tests/unit.h \ + tests/test.conf tests/test-dtls.conf \ + sslSniffer/sslSniffer.vcproj sslSniffer/sslSniffer.vcxproj \ + sslSniffer/sslSnifferTest/sslSniffTest.vcproj \ + mqx/ctaocrypt_test/.cproject mqx/ctaocrypt_test/.project \ + mqx/ctaocrypt_test/ReferencedRSESystems.xml \ + mqx/ctaocrypt_test/ctaocrypt_test_twrk70f120m_Int_Flash_SramData_Debug_PnE_U-MultiLink.launch \ + mqx/ctaocrypt_test/ctaocrypt_test_twrk70f120m_Int_Flash_SramData_Release_PnE_U-MultiLink.launch \ + mqx/ctaocrypt_test/Sources/main.c \ + mqx/ctaocrypt_test/Sources/main.h mqx/README \ + mqx/cyassl/.cproject mqx/cyassl/.project \ + mqx/cyassl_client/.cproject mqx/cyassl_client/.project \ + mqx/cyassl_client/ReferencedRSESystems.xml \ + mqx/cyassl_client/cyassl_client_twrk70f120m_Int_Flash_SramData_Debug_PnE_U-MultiLink.launch \ + mqx/cyassl_client/cyassl_client_twrk70f120m_Int_Flash_SramData_Release_PnE_U-MultiLink.launch \ + mqx/cyassl_client/Sources/main.c \ + mqx/cyassl_client/Sources/main.h mqx/util_lib/.cproject \ + mqx/util_lib/.project mqx/util_lib/Sources/util.c \ + mqx/util_lib/Sources/util.h mplabx/PIC32MZ-serial.h \ + mplabx/README mplabx/benchmark_main.c mplabx/test_main.c \ + mplabx/ctaocrypt_benchmark.X/Makefile \ + mplabx/ctaocrypt_benchmark.X/nbproject/configurations.xml \ + mplabx/ctaocrypt_benchmark.X/nbproject/project.xml \ + mplabx/ctaocrypt_test.X/Makefile \ + mplabx/ctaocrypt_test.X/nbproject/configurations.xml \ + mplabx/ctaocrypt_test.X/nbproject/project.xml \ + mplabx/cyassl.X/Makefile \ + mplabx/cyassl.X/nbproject/configurations.xml \ + mplabx/cyassl.X/nbproject/project.xml mcapi/README \ + mcapi/PIC32MZ-serial.h mcapi/ctaocrypt_mcapi.X/Makefile \ + mcapi/ctaocrypt_mcapi.X/nbproject/configurations.xml \ + mcapi/ctaocrypt_mcapi.X/nbproject/project.xml \ + mcapi/ctaocrypt_test.X/Makefile \ + mcapi/ctaocrypt_test.X/nbproject/configurations.xml \ + mcapi/ctaocrypt_test.X/nbproject/project.xml \ + mcapi/cyassl.X/Makefile \ + mcapi/cyassl.X/nbproject/configurations.xml \ + mcapi/cyassl.X/nbproject/project.xml mcapi/zlib.X/Makefile \ + mcapi/zlib.X/nbproject/configurations.xml \ + mcapi/zlib.X/nbproject/project.xml +dist_doc_DATA = certs/taoCert.txt doc/README.txt +exampledir = $(docdir)/example +dist_example_DATA = examples/client/client.c examples/server/server.c \ + examples/echoclient/echoclient.c \ + examples/echoserver/echoserver.c +ACLOCAL_AMFLAGS = -I m4 +src_libcyassl_la_SOURCES = $(am__append_1) src/internal.c src/io.c \ + src/keys.c src/ssl.c src/tls.c ctaocrypt/src/hmac.c \ + ctaocrypt/src/random.c ctaocrypt/src/sha256.c \ + ctaocrypt/src/logging.c ctaocrypt/src/wc_port.c \ + ctaocrypt/src/error.c $(am__append_2) $(am__append_3) \ + $(am__append_4) $(am__append_5) $(am__append_6) \ + $(am__append_7) $(am__append_8) $(am__append_9) \ + $(am__append_10) $(am__append_11) $(am__append_12) \ + $(am__append_13) $(am__append_14) $(am__append_15) \ + $(am__append_16) $(am__append_17) $(am__append_18) \ + $(am__append_19) $(am__append_20) $(am__append_21) \ + $(am__append_22) $(am__append_23) $(am__append_24) \ + $(am__append_25) $(am__append_26) $(am__append_27) \ + $(am__append_28) $(am__append_29) $(am__append_30) \ + $(am__append_31) $(am__append_32) $(am__append_33) +src_libcyassl_la_LDFLAGS = ${AM_LDFLAGS} -no-undefined -version-info ${CYASSL_LIBRARY_VERSION} +src_libcyassl_la_LIBADD = $(LIBM) +src_libcyassl_la_CFLAGS = -DBUILDING_CYASSL $(AM_CFLAGS) +src_libcyassl_la_CPPFLAGS = -DBUILDING_CYASSL $(AM_CPPFLAGS) +pkgconfigdir = $(libdir)/pkgconfig +pkgconfig_DATA = support/cyassl.pc +ctaocrypt_benchmark_benchmark_SOURCES = ctaocrypt/benchmark/benchmark.c +ctaocrypt_benchmark_benchmark_LDADD = src/libcyassl.la +ctaocrypt_benchmark_benchmark_DEPENDENCIES = src/libcyassl.la +ctaocrypt_test_testctaocrypt_SOURCES = ctaocrypt/test/test.c +ctaocrypt_test_testctaocrypt_LDADD = src/libcyassl.la +ctaocrypt_test_testctaocrypt_DEPENDENCIES = src/libcyassl.la +@BUILD_EXAMPLES_TRUE@examples_client_client_SOURCES = examples/client/client.c +@BUILD_EXAMPLES_TRUE@examples_client_client_LDADD = src/libcyassl.la +@BUILD_EXAMPLES_TRUE@examples_client_client_DEPENDENCIES = src/libcyassl.la +@BUILD_EXAMPLES_TRUE@examples_server_server_SOURCES = examples/server/server.c +@BUILD_EXAMPLES_TRUE@examples_server_server_LDADD = src/libcyassl.la +@BUILD_EXAMPLES_TRUE@examples_server_server_DEPENDENCIES = src/libcyassl.la +@BUILD_EXAMPLES_TRUE@examples_echoclient_echoclient_SOURCES = examples/echoclient/echoclient.c +@BUILD_EXAMPLES_TRUE@examples_echoclient_echoclient_LDADD = src/libcyassl.la +@BUILD_EXAMPLES_TRUE@examples_echoclient_echoclient_DEPENDENCIES = src/libcyassl.la +@BUILD_EXAMPLES_TRUE@examples_echoserver_echoserver_SOURCES = examples/echoserver/echoserver.c +@BUILD_EXAMPLES_TRUE@examples_echoserver_echoserver_LDADD = src/libcyassl.la +@BUILD_EXAMPLES_TRUE@examples_echoserver_echoserver_DEPENDENCIES = src/libcyassl.la +@BUILD_EXAMPLES_TRUE@testsuite_testsuite_test_SOURCES = \ +@BUILD_EXAMPLES_TRUE@ ctaocrypt/test/test.c \ +@BUILD_EXAMPLES_TRUE@ examples/client/client.c \ +@BUILD_EXAMPLES_TRUE@ examples/echoclient/echoclient.c \ +@BUILD_EXAMPLES_TRUE@ examples/echoserver/echoserver.c \ +@BUILD_EXAMPLES_TRUE@ examples/server/server.c \ +@BUILD_EXAMPLES_TRUE@ testsuite/testsuite.c + +@BUILD_EXAMPLES_TRUE@testsuite_testsuite_test_CFLAGS = -DNO_MAIN_DRIVER $(AM_CFLAGS) +@BUILD_EXAMPLES_TRUE@testsuite_testsuite_test_LDADD = src/libcyassl.la +@BUILD_EXAMPLES_TRUE@testsuite_testsuite_test_DEPENDENCIES = src/libcyassl.la +@BUILD_EXAMPLES_TRUE@tests_unit_test_SOURCES = \ +@BUILD_EXAMPLES_TRUE@ tests/unit.c \ +@BUILD_EXAMPLES_TRUE@ tests/api.c \ +@BUILD_EXAMPLES_TRUE@ tests/suites.c \ +@BUILD_EXAMPLES_TRUE@ tests/hash.c \ +@BUILD_EXAMPLES_TRUE@ examples/client/client.c \ +@BUILD_EXAMPLES_TRUE@ examples/server/server.c + +@BUILD_EXAMPLES_TRUE@tests_unit_test_CFLAGS = -DNO_MAIN_DRIVER $(AM_CFLAGS) +@BUILD_EXAMPLES_TRUE@tests_unit_test_LDADD = src/libcyassl.la +@BUILD_EXAMPLES_TRUE@tests_unit_test_DEPENDENCIES = src/libcyassl.la +@BUILD_SNIFFTEST_TRUE@sslSniffer_sslSnifferTest_snifftest_SOURCES = sslSniffer/sslSnifferTest/snifftest.c +@BUILD_SNIFFTEST_TRUE@sslSniffer_sslSnifferTest_snifftest_LDADD = src/libcyassl.la -lpcap +@BUILD_SNIFFTEST_TRUE@sslSniffer_sslSnifferTest_snifftest_DEPENDENCIES = src/libcyassl.la +@BUILD_MCAPI_TRUE@mcapi_test_SOURCES = mcapi/crypto.c \ +@BUILD_MCAPI_TRUE@ mcapi/mcapi_test.c + +@BUILD_MCAPI_TRUE@mcapi_test_LDADD = src/libcyassl.la +@BUILD_MCAPI_TRUE@mcapi_test_DEPENDENCIES = src/libcyassl.la +@USE_VALGRIND_TRUE@TESTS_ENVIRONMENT = ./valgrind-error.sh +TEST_EXTENSIONS = .test +all: $(BUILT_SOURCES) config.h + $(MAKE) $(AM_MAKEFLAGS) all-am + +.SUFFIXES: +.SUFFIXES: .c .lo .log .o .obj .s .test .test$(EXEEXT) .trs +am--refresh: Makefile + @: +$(srcdir)/Makefile.in: $(srcdir)/Makefile.am $(srcdir)/cyassl/include.am $(srcdir)/cyassl/ctaocrypt/include.am $(srcdir)/cyassl/openssl/include.am $(srcdir)/certs/include.am $(srcdir)/certs/1024/include.am $(srcdir)/certs/crl/include.am $(srcdir)/doc/include.am $(srcdir)/swig/include.am $(srcdir)/src/include.am $(srcdir)/support/include.am $(srcdir)/ctaocrypt/benchmark/include.am $(srcdir)/ctaocrypt/src/include.am $(srcdir)/ctaocrypt/test/include.am $(srcdir)/examples/client/include.am $(srcdir)/examples/server/include.am $(srcdir)/examples/echoclient/include.am $(srcdir)/examples/echoserver/include.am $(srcdir)/testsuite/include.am $(srcdir)/tests/include.am $(srcdir)/sslSniffer/sslSnifferTest/include.am $(srcdir)/rpm/include.am $(srcdir)/mqx/ctaocrypt_test/Sources/include.am $(srcdir)/mqx/cyassl/include.am $(srcdir)/mqx/cyassl_client/Sources/include.am $(srcdir)/mqx/util_lib/Sources/include.am $(srcdir)/mplabx/include.am $(srcdir)/mplabx/ctaocrypt_benchmark.X/nbproject/include.am $(srcdir)/mplabx/ctaocrypt_test.X/nbproject/include.am $(srcdir)/mplabx/cyassl.X/nbproject/include.am $(srcdir)/mcapi/include.am $(srcdir)/mcapi/ctaocrypt_mcapi.X/nbproject/include.am $(srcdir)/mcapi/ctaocrypt_test.X/nbproject/include.am $(srcdir)/mcapi/cyassl.X/nbproject/include.am $(srcdir)/mcapi/zlib.X/nbproject/include.am $(am__configure_deps) + @for dep in $?; do \ + case '$(am__configure_deps)' in \ + *$$dep*) \ + echo ' cd $(srcdir) && $(AUTOMAKE) --foreign'; \ + $(am__cd) $(srcdir) && $(AUTOMAKE) --foreign \ + && exit 0; \ + exit 1;; \ + esac; \ + done; \ + echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign Makefile'; \ + $(am__cd) $(top_srcdir) && \ + $(AUTOMAKE) --foreign Makefile +.PRECIOUS: Makefile +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + @case '$?' in \ + *config.status*) \ + echo ' $(SHELL) ./config.status'; \ + $(SHELL) ./config.status;; \ + *) \ + echo ' cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe)'; \ + cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe);; \ + esac; +$(srcdir)/cyassl/include.am $(srcdir)/cyassl/ctaocrypt/include.am $(srcdir)/cyassl/openssl/include.am $(srcdir)/certs/include.am $(srcdir)/certs/1024/include.am $(srcdir)/certs/crl/include.am $(srcdir)/doc/include.am $(srcdir)/swig/include.am $(srcdir)/src/include.am $(srcdir)/support/include.am $(srcdir)/ctaocrypt/benchmark/include.am $(srcdir)/ctaocrypt/src/include.am $(srcdir)/ctaocrypt/test/include.am $(srcdir)/examples/client/include.am $(srcdir)/examples/server/include.am $(srcdir)/examples/echoclient/include.am $(srcdir)/examples/echoserver/include.am $(srcdir)/testsuite/include.am $(srcdir)/tests/include.am $(srcdir)/sslSniffer/sslSnifferTest/include.am $(srcdir)/rpm/include.am $(srcdir)/mqx/ctaocrypt_test/Sources/include.am $(srcdir)/mqx/cyassl/include.am $(srcdir)/mqx/cyassl_client/Sources/include.am $(srcdir)/mqx/util_lib/Sources/include.am $(srcdir)/mplabx/include.am $(srcdir)/mplabx/ctaocrypt_benchmark.X/nbproject/include.am $(srcdir)/mplabx/ctaocrypt_test.X/nbproject/include.am $(srcdir)/mplabx/cyassl.X/nbproject/include.am $(srcdir)/mcapi/include.am $(srcdir)/mcapi/ctaocrypt_mcapi.X/nbproject/include.am $(srcdir)/mcapi/ctaocrypt_test.X/nbproject/include.am $(srcdir)/mcapi/cyassl.X/nbproject/include.am $(srcdir)/mcapi/zlib.X/nbproject/include.am: + +$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) + $(SHELL) ./config.status --recheck + +$(top_srcdir)/configure: $(am__configure_deps) + $(am__cd) $(srcdir) && $(AUTOCONF) +$(ACLOCAL_M4): $(am__aclocal_m4_deps) + $(am__cd) $(srcdir) && $(ACLOCAL) $(ACLOCAL_AMFLAGS) +$(am__aclocal_m4_deps): + +config.h: stamp-h1 + @test -f $@ || rm -f stamp-h1 + @test -f $@ || $(MAKE) $(AM_MAKEFLAGS) stamp-h1 + +stamp-h1: $(srcdir)/config.in $(top_builddir)/config.status + @rm -f stamp-h1 + cd $(top_builddir) && $(SHELL) ./config.status config.h +$(srcdir)/config.in: $(am__configure_deps) + ($(am__cd) $(top_srcdir) && $(AUTOHEADER)) + rm -f stamp-h1 + touch $@ + +distclean-hdr: + -rm -f config.h stamp-h1 +stamp-h: $(top_builddir)/config.status $(srcdir)/stamp-h.in + cd $(top_builddir) && $(SHELL) ./config.status $@ +cyassl/version.h: $(top_builddir)/config.status $(top_srcdir)/cyassl/version.h.in + cd $(top_builddir) && $(SHELL) ./config.status $@ +cyassl/options.h: $(top_builddir)/config.status $(top_srcdir)/cyassl/options.h.in + cd $(top_builddir) && $(SHELL) ./config.status $@ +support/cyassl.pc: $(top_builddir)/config.status $(top_srcdir)/support/cyassl.pc.in + cd $(top_builddir) && $(SHELL) ./config.status $@ +rpm/spec: $(top_builddir)/config.status $(top_srcdir)/rpm/spec.in + cd $(top_builddir) && $(SHELL) ./config.status $@ + +install-libLTLIBRARIES: $(lib_LTLIBRARIES) + @$(NORMAL_INSTALL) + @list='$(lib_LTLIBRARIES)'; test -n "$(libdir)" || list=; \ + list2=; for p in $$list; do \ + if test -f $$p; then \ + list2="$$list2 $$p"; \ + else :; fi; \ + done; \ + test -z "$$list2" || { \ + echo " $(MKDIR_P) '$(DESTDIR)$(libdir)'"; \ + $(MKDIR_P) "$(DESTDIR)$(libdir)" || exit 1; \ + echo " $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=install $(INSTALL) $(INSTALL_STRIP_FLAG) $$list2 '$(DESTDIR)$(libdir)'"; \ + $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=install $(INSTALL) $(INSTALL_STRIP_FLAG) $$list2 "$(DESTDIR)$(libdir)"; \ + } + +uninstall-libLTLIBRARIES: + @$(NORMAL_UNINSTALL) + @list='$(lib_LTLIBRARIES)'; test -n "$(libdir)" || list=; \ + for p in $$list; do \ + $(am__strip_dir) \ + echo " $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=uninstall rm -f '$(DESTDIR)$(libdir)/$$f'"; \ + $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=uninstall rm -f "$(DESTDIR)$(libdir)/$$f"; \ + done + +clean-libLTLIBRARIES: + -test -z "$(lib_LTLIBRARIES)" || rm -f $(lib_LTLIBRARIES) + @list='$(lib_LTLIBRARIES)'; \ + locs=`for p in $$list; do echo $$p; done | \ + sed 's|^[^/]*$$|.|; s|/[^/]*$$||; s|$$|/so_locations|' | \ + sort -u`; \ + test -z "$$locs" || { \ + echo rm -f $${locs}; \ + rm -f $${locs}; \ + } + +clean-noinstLTLIBRARIES: + -test -z "$(noinst_LTLIBRARIES)" || rm -f $(noinst_LTLIBRARIES) + @list='$(noinst_LTLIBRARIES)'; \ + locs=`for p in $$list; do echo $$p; done | \ + sed 's|^[^/]*$$|.|; s|/[^/]*$$||; s|$$|/so_locations|' | \ + sort -u`; \ + test -z "$$locs" || { \ + echo rm -f $${locs}; \ + rm -f $${locs}; \ + } +ctaocrypt/src/$(am__dirstamp): + @$(MKDIR_P) ctaocrypt/src + @: > ctaocrypt/src/$(am__dirstamp) +ctaocrypt/src/$(DEPDIR)/$(am__dirstamp): + @$(MKDIR_P) ctaocrypt/src/$(DEPDIR) + @: > ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-wolfcrypt_first.lo: \ + ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +src/$(am__dirstamp): + @$(MKDIR_P) src + @: > src/$(am__dirstamp) +src/$(DEPDIR)/$(am__dirstamp): + @$(MKDIR_P) src/$(DEPDIR) + @: > src/$(DEPDIR)/$(am__dirstamp) +src/src_libcyassl_la-internal.lo: src/$(am__dirstamp) \ + src/$(DEPDIR)/$(am__dirstamp) +src/src_libcyassl_la-io.lo: src/$(am__dirstamp) \ + src/$(DEPDIR)/$(am__dirstamp) +src/src_libcyassl_la-keys.lo: src/$(am__dirstamp) \ + src/$(DEPDIR)/$(am__dirstamp) +src/src_libcyassl_la-ssl.lo: src/$(am__dirstamp) \ + src/$(DEPDIR)/$(am__dirstamp) +src/src_libcyassl_la-tls.lo: src/$(am__dirstamp) \ + src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-hmac.lo: ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-random.lo: \ + ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-sha256.lo: \ + ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-logging.lo: \ + ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-wc_port.lo: \ + ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-error.lo: \ + ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-memory.lo: \ + ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-rsa.lo: ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-dh.lo: ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-asn.lo: ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-fips.lo: ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-fips_test.lo: \ + ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-coding.lo: \ + ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-aes.lo: ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-des3.lo: ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-sha.lo: ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-arc4.lo: ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-md4.lo: ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-md5.lo: ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-pwdbased.lo: \ + ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-dsa.lo: ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/aes_asm.lo: ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-camellia.lo: \ + ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-md2.lo: ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-ripemd.lo: \ + ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-sha512.lo: \ + ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-blake2b.lo: \ + ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +src/src_libcyassl_la-sniffer.lo: src/$(am__dirstamp) \ + src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-hc128.lo: \ + ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-rabbit.lo: \ + ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-misc.lo: ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-tfm.lo: ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-integer.lo: \ + ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-ecc.lo: ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +src/src_libcyassl_la-ocsp.lo: src/$(am__dirstamp) \ + src/$(DEPDIR)/$(am__dirstamp) +src/src_libcyassl_la-crl.lo: src/$(am__dirstamp) \ + src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-compress.lo: \ + ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-pkcs7.lo: \ + ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/src/src_libcyassl_la-wolfcrypt_last.lo: \ + ctaocrypt/src/$(am__dirstamp) \ + ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) + +src/libcyassl.la: $(src_libcyassl_la_OBJECTS) $(src_libcyassl_la_DEPENDENCIES) $(EXTRA_src_libcyassl_la_DEPENDENCIES) src/$(am__dirstamp) + $(AM_V_CCLD)$(src_libcyassl_la_LINK) -rpath $(libdir) $(src_libcyassl_la_OBJECTS) $(src_libcyassl_la_LIBADD) $(LIBS) +install-binPROGRAMS: $(bin_PROGRAMS) + @$(NORMAL_INSTALL) + @list='$(bin_PROGRAMS)'; test -n "$(bindir)" || list=; \ + if test -n "$$list"; then \ + echo " $(MKDIR_P) '$(DESTDIR)$(bindir)'"; \ + $(MKDIR_P) "$(DESTDIR)$(bindir)" || exit 1; \ + fi; \ + for p in $$list; do echo "$$p $$p"; done | \ + sed 's/$(EXEEXT)$$//' | \ + while read p p1; do if test -f $$p \ + || test -f $$p1 \ + ; then echo "$$p"; echo "$$p"; else :; fi; \ + done | \ + sed -e 'p;s,.*/,,;n;h' \ + -e 's|.*|.|' \ + -e 'p;x;s,.*/,,;s/$(EXEEXT)$$//;$(transform);s/$$/$(EXEEXT)/' | \ + sed 'N;N;N;s,\n, ,g' | \ + $(AWK) 'BEGIN { files["."] = ""; dirs["."] = 1 } \ + { d=$$3; if (dirs[d] != 1) { print "d", d; dirs[d] = 1 } \ + if ($$2 == $$4) files[d] = files[d] " " $$1; \ + else { print "f", $$3 "/" $$4, $$1; } } \ + END { for (d in files) print "f", d, files[d] }' | \ + while read type dir files; do \ + if test "$$dir" = .; then dir=; else dir=/$$dir; fi; \ + test -z "$$files" || { \ + echo " $(INSTALL_PROGRAM_ENV) $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=install $(INSTALL_PROGRAM) $$files '$(DESTDIR)$(bindir)$$dir'"; \ + $(INSTALL_PROGRAM_ENV) $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=install $(INSTALL_PROGRAM) $$files "$(DESTDIR)$(bindir)$$dir" || exit $$?; \ + } \ + ; done + +uninstall-binPROGRAMS: + @$(NORMAL_UNINSTALL) + @list='$(bin_PROGRAMS)'; test -n "$(bindir)" || list=; \ + files=`for p in $$list; do echo "$$p"; done | \ + sed -e 'h;s,^.*/,,;s/$(EXEEXT)$$//;$(transform)' \ + -e 's/$$/$(EXEEXT)/' \ + `; \ + test -n "$$list" || exit 0; \ + echo " ( cd '$(DESTDIR)$(bindir)' && rm -f" $$files ")"; \ + cd "$(DESTDIR)$(bindir)" && rm -f $$files + +clean-binPROGRAMS: + @list='$(bin_PROGRAMS)'; test -n "$$list" || exit 0; \ + echo " rm -f" $$list; \ + rm -f $$list || exit $$?; \ + test -n "$(EXEEXT)" || exit 0; \ + list=`for p in $$list; do echo "$$p"; done | sed 's/$(EXEEXT)$$//'`; \ + echo " rm -f" $$list; \ + rm -f $$list + +clean-checkPROGRAMS: + @list='$(check_PROGRAMS)'; test -n "$$list" || exit 0; \ + echo " rm -f" $$list; \ + rm -f $$list || exit $$?; \ + test -n "$(EXEEXT)" || exit 0; \ + list=`for p in $$list; do echo "$$p"; done | sed 's/$(EXEEXT)$$//'`; \ + echo " rm -f" $$list; \ + rm -f $$list + +clean-noinstPROGRAMS: + @list='$(noinst_PROGRAMS)'; test -n "$$list" || exit 0; \ + echo " rm -f" $$list; \ + rm -f $$list || exit $$?; \ + test -n "$(EXEEXT)" || exit 0; \ + list=`for p in $$list; do echo "$$p"; done | sed 's/$(EXEEXT)$$//'`; \ + echo " rm -f" $$list; \ + rm -f $$list +ctaocrypt/benchmark/$(am__dirstamp): + @$(MKDIR_P) ctaocrypt/benchmark + @: > ctaocrypt/benchmark/$(am__dirstamp) +ctaocrypt/benchmark/$(DEPDIR)/$(am__dirstamp): + @$(MKDIR_P) ctaocrypt/benchmark/$(DEPDIR) + @: > ctaocrypt/benchmark/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/benchmark/benchmark.$(OBJEXT): \ + ctaocrypt/benchmark/$(am__dirstamp) \ + ctaocrypt/benchmark/$(DEPDIR)/$(am__dirstamp) + +ctaocrypt/benchmark/benchmark$(EXEEXT): $(ctaocrypt_benchmark_benchmark_OBJECTS) $(ctaocrypt_benchmark_benchmark_DEPENDENCIES) $(EXTRA_ctaocrypt_benchmark_benchmark_DEPENDENCIES) ctaocrypt/benchmark/$(am__dirstamp) + @rm -f ctaocrypt/benchmark/benchmark$(EXEEXT) + $(AM_V_CCLD)$(LINK) $(ctaocrypt_benchmark_benchmark_OBJECTS) $(ctaocrypt_benchmark_benchmark_LDADD) $(LIBS) +ctaocrypt/test/$(am__dirstamp): + @$(MKDIR_P) ctaocrypt/test + @: > ctaocrypt/test/$(am__dirstamp) +ctaocrypt/test/$(DEPDIR)/$(am__dirstamp): + @$(MKDIR_P) ctaocrypt/test/$(DEPDIR) + @: > ctaocrypt/test/$(DEPDIR)/$(am__dirstamp) +ctaocrypt/test/test.$(OBJEXT): ctaocrypt/test/$(am__dirstamp) \ + ctaocrypt/test/$(DEPDIR)/$(am__dirstamp) + +ctaocrypt/test/testctaocrypt$(EXEEXT): $(ctaocrypt_test_testctaocrypt_OBJECTS) $(ctaocrypt_test_testctaocrypt_DEPENDENCIES) $(EXTRA_ctaocrypt_test_testctaocrypt_DEPENDENCIES) ctaocrypt/test/$(am__dirstamp) + @rm -f ctaocrypt/test/testctaocrypt$(EXEEXT) + $(AM_V_CCLD)$(LINK) $(ctaocrypt_test_testctaocrypt_OBJECTS) $(ctaocrypt_test_testctaocrypt_LDADD) $(LIBS) +examples/client/$(am__dirstamp): + @$(MKDIR_P) examples/client + @: > examples/client/$(am__dirstamp) +examples/client/$(DEPDIR)/$(am__dirstamp): + @$(MKDIR_P) examples/client/$(DEPDIR) + @: > examples/client/$(DEPDIR)/$(am__dirstamp) +examples/client/client.$(OBJEXT): examples/client/$(am__dirstamp) \ + examples/client/$(DEPDIR)/$(am__dirstamp) + +examples/client/client$(EXEEXT): $(examples_client_client_OBJECTS) $(examples_client_client_DEPENDENCIES) $(EXTRA_examples_client_client_DEPENDENCIES) examples/client/$(am__dirstamp) + @rm -f examples/client/client$(EXEEXT) + $(AM_V_CCLD)$(LINK) $(examples_client_client_OBJECTS) $(examples_client_client_LDADD) $(LIBS) +examples/echoclient/$(am__dirstamp): + @$(MKDIR_P) examples/echoclient + @: > examples/echoclient/$(am__dirstamp) +examples/echoclient/$(DEPDIR)/$(am__dirstamp): + @$(MKDIR_P) examples/echoclient/$(DEPDIR) + @: > examples/echoclient/$(DEPDIR)/$(am__dirstamp) +examples/echoclient/echoclient.$(OBJEXT): \ + examples/echoclient/$(am__dirstamp) \ + examples/echoclient/$(DEPDIR)/$(am__dirstamp) + +examples/echoclient/echoclient$(EXEEXT): $(examples_echoclient_echoclient_OBJECTS) $(examples_echoclient_echoclient_DEPENDENCIES) $(EXTRA_examples_echoclient_echoclient_DEPENDENCIES) examples/echoclient/$(am__dirstamp) + @rm -f examples/echoclient/echoclient$(EXEEXT) + $(AM_V_CCLD)$(LINK) $(examples_echoclient_echoclient_OBJECTS) $(examples_echoclient_echoclient_LDADD) $(LIBS) +examples/echoserver/$(am__dirstamp): + @$(MKDIR_P) examples/echoserver + @: > examples/echoserver/$(am__dirstamp) +examples/echoserver/$(DEPDIR)/$(am__dirstamp): + @$(MKDIR_P) examples/echoserver/$(DEPDIR) + @: > examples/echoserver/$(DEPDIR)/$(am__dirstamp) +examples/echoserver/echoserver.$(OBJEXT): \ + examples/echoserver/$(am__dirstamp) \ + examples/echoserver/$(DEPDIR)/$(am__dirstamp) + +examples/echoserver/echoserver$(EXEEXT): $(examples_echoserver_echoserver_OBJECTS) $(examples_echoserver_echoserver_DEPENDENCIES) $(EXTRA_examples_echoserver_echoserver_DEPENDENCIES) examples/echoserver/$(am__dirstamp) + @rm -f examples/echoserver/echoserver$(EXEEXT) + $(AM_V_CCLD)$(LINK) $(examples_echoserver_echoserver_OBJECTS) $(examples_echoserver_echoserver_LDADD) $(LIBS) +examples/server/$(am__dirstamp): + @$(MKDIR_P) examples/server + @: > examples/server/$(am__dirstamp) +examples/server/$(DEPDIR)/$(am__dirstamp): + @$(MKDIR_P) examples/server/$(DEPDIR) + @: > examples/server/$(DEPDIR)/$(am__dirstamp) +examples/server/server.$(OBJEXT): examples/server/$(am__dirstamp) \ + examples/server/$(DEPDIR)/$(am__dirstamp) + +examples/server/server$(EXEEXT): $(examples_server_server_OBJECTS) $(examples_server_server_DEPENDENCIES) $(EXTRA_examples_server_server_DEPENDENCIES) examples/server/$(am__dirstamp) + @rm -f examples/server/server$(EXEEXT) + $(AM_V_CCLD)$(LINK) $(examples_server_server_OBJECTS) $(examples_server_server_LDADD) $(LIBS) +mcapi/$(am__dirstamp): + @$(MKDIR_P) mcapi + @: > mcapi/$(am__dirstamp) +mcapi/$(DEPDIR)/$(am__dirstamp): + @$(MKDIR_P) mcapi/$(DEPDIR) + @: > mcapi/$(DEPDIR)/$(am__dirstamp) +mcapi/crypto.$(OBJEXT): mcapi/$(am__dirstamp) \ + mcapi/$(DEPDIR)/$(am__dirstamp) +mcapi/mcapi_test.$(OBJEXT): mcapi/$(am__dirstamp) \ + mcapi/$(DEPDIR)/$(am__dirstamp) + +mcapi/test$(EXEEXT): $(mcapi_test_OBJECTS) $(mcapi_test_DEPENDENCIES) $(EXTRA_mcapi_test_DEPENDENCIES) mcapi/$(am__dirstamp) + @rm -f mcapi/test$(EXEEXT) + $(AM_V_CCLD)$(LINK) $(mcapi_test_OBJECTS) $(mcapi_test_LDADD) $(LIBS) +sslSniffer/sslSnifferTest/$(am__dirstamp): + @$(MKDIR_P) sslSniffer/sslSnifferTest + @: > sslSniffer/sslSnifferTest/$(am__dirstamp) +sslSniffer/sslSnifferTest/$(DEPDIR)/$(am__dirstamp): + @$(MKDIR_P) sslSniffer/sslSnifferTest/$(DEPDIR) + @: > sslSniffer/sslSnifferTest/$(DEPDIR)/$(am__dirstamp) +sslSniffer/sslSnifferTest/snifftest.$(OBJEXT): \ + sslSniffer/sslSnifferTest/$(am__dirstamp) \ + sslSniffer/sslSnifferTest/$(DEPDIR)/$(am__dirstamp) + +sslSniffer/sslSnifferTest/snifftest$(EXEEXT): $(sslSniffer_sslSnifferTest_snifftest_OBJECTS) $(sslSniffer_sslSnifferTest_snifftest_DEPENDENCIES) $(EXTRA_sslSniffer_sslSnifferTest_snifftest_DEPENDENCIES) sslSniffer/sslSnifferTest/$(am__dirstamp) + @rm -f sslSniffer/sslSnifferTest/snifftest$(EXEEXT) + $(AM_V_CCLD)$(LINK) $(sslSniffer_sslSnifferTest_snifftest_OBJECTS) $(sslSniffer_sslSnifferTest_snifftest_LDADD) $(LIBS) +tests/$(am__dirstamp): + @$(MKDIR_P) tests + @: > tests/$(am__dirstamp) +tests/$(DEPDIR)/$(am__dirstamp): + @$(MKDIR_P) tests/$(DEPDIR) + @: > tests/$(DEPDIR)/$(am__dirstamp) +tests/tests_unit_test-unit.$(OBJEXT): tests/$(am__dirstamp) \ + tests/$(DEPDIR)/$(am__dirstamp) +tests/tests_unit_test-api.$(OBJEXT): tests/$(am__dirstamp) \ + tests/$(DEPDIR)/$(am__dirstamp) +tests/tests_unit_test-suites.$(OBJEXT): tests/$(am__dirstamp) \ + tests/$(DEPDIR)/$(am__dirstamp) +tests/tests_unit_test-hash.$(OBJEXT): tests/$(am__dirstamp) \ + tests/$(DEPDIR)/$(am__dirstamp) +examples/client/tests_unit_test-client.$(OBJEXT): \ + examples/client/$(am__dirstamp) \ + examples/client/$(DEPDIR)/$(am__dirstamp) +examples/server/tests_unit_test-server.$(OBJEXT): \ + examples/server/$(am__dirstamp) \ + examples/server/$(DEPDIR)/$(am__dirstamp) + +tests/unit.test$(EXEEXT): $(tests_unit_test_OBJECTS) $(tests_unit_test_DEPENDENCIES) $(EXTRA_tests_unit_test_DEPENDENCIES) tests/$(am__dirstamp) + @rm -f tests/unit.test$(EXEEXT) + $(AM_V_CCLD)$(tests_unit_test_LINK) $(tests_unit_test_OBJECTS) $(tests_unit_test_LDADD) $(LIBS) +ctaocrypt/test/testsuite_testsuite_test-test.$(OBJEXT): \ + ctaocrypt/test/$(am__dirstamp) \ + ctaocrypt/test/$(DEPDIR)/$(am__dirstamp) +examples/client/testsuite_testsuite_test-client.$(OBJEXT): \ + examples/client/$(am__dirstamp) \ + examples/client/$(DEPDIR)/$(am__dirstamp) +examples/echoclient/testsuite_testsuite_test-echoclient.$(OBJEXT): \ + examples/echoclient/$(am__dirstamp) \ + examples/echoclient/$(DEPDIR)/$(am__dirstamp) +examples/echoserver/testsuite_testsuite_test-echoserver.$(OBJEXT): \ + examples/echoserver/$(am__dirstamp) \ + examples/echoserver/$(DEPDIR)/$(am__dirstamp) +examples/server/testsuite_testsuite_test-server.$(OBJEXT): \ + examples/server/$(am__dirstamp) \ + examples/server/$(DEPDIR)/$(am__dirstamp) +testsuite/$(am__dirstamp): + @$(MKDIR_P) testsuite + @: > testsuite/$(am__dirstamp) +testsuite/$(DEPDIR)/$(am__dirstamp): + @$(MKDIR_P) testsuite/$(DEPDIR) + @: > testsuite/$(DEPDIR)/$(am__dirstamp) +testsuite/testsuite_testsuite_test-testsuite.$(OBJEXT): \ + testsuite/$(am__dirstamp) testsuite/$(DEPDIR)/$(am__dirstamp) + +testsuite/testsuite.test$(EXEEXT): $(testsuite_testsuite_test_OBJECTS) $(testsuite_testsuite_test_DEPENDENCIES) $(EXTRA_testsuite_testsuite_test_DEPENDENCIES) testsuite/$(am__dirstamp) + @rm -f testsuite/testsuite.test$(EXEEXT) + $(AM_V_CCLD)$(testsuite_testsuite_test_LINK) $(testsuite_testsuite_test_OBJECTS) $(testsuite_testsuite_test_LDADD) $(LIBS) + +mostlyclean-compile: + -rm -f *.$(OBJEXT) + -rm -f ctaocrypt/benchmark/*.$(OBJEXT) + -rm -f ctaocrypt/src/*.$(OBJEXT) + -rm -f ctaocrypt/src/*.lo + -rm -f ctaocrypt/test/*.$(OBJEXT) + -rm -f examples/client/*.$(OBJEXT) + -rm -f examples/echoclient/*.$(OBJEXT) + -rm -f examples/echoserver/*.$(OBJEXT) + -rm -f examples/server/*.$(OBJEXT) + -rm -f mcapi/*.$(OBJEXT) + -rm -f src/*.$(OBJEXT) + -rm -f src/*.lo + -rm -f sslSniffer/sslSnifferTest/*.$(OBJEXT) + -rm -f tests/*.$(OBJEXT) + -rm -f testsuite/*.$(OBJEXT) + +distclean-compile: + -rm -f *.tab.c + +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/benchmark/$(DEPDIR)/benchmark.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-aes.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-arc4.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-asn.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-blake2b.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-camellia.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-coding.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-compress.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-des3.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-dh.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-dsa.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-ecc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-error.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-fips.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-fips_test.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-hc128.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-hmac.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-integer.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-logging.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-md2.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-md4.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-md5.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-memory.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-misc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-pkcs7.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-pwdbased.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-rabbit.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-random.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-ripemd.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-rsa.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-sha.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-sha256.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-sha512.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-tfm.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-wc_port.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-wolfcrypt_first.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-wolfcrypt_last.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/test/$(DEPDIR)/test.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ctaocrypt/test/$(DEPDIR)/testsuite_testsuite_test-test.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@examples/client/$(DEPDIR)/client.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@examples/client/$(DEPDIR)/tests_unit_test-client.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@examples/client/$(DEPDIR)/testsuite_testsuite_test-client.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@examples/echoclient/$(DEPDIR)/echoclient.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@examples/echoclient/$(DEPDIR)/testsuite_testsuite_test-echoclient.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@examples/echoserver/$(DEPDIR)/echoserver.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@examples/echoserver/$(DEPDIR)/testsuite_testsuite_test-echoserver.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@examples/server/$(DEPDIR)/server.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@examples/server/$(DEPDIR)/tests_unit_test-server.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@examples/server/$(DEPDIR)/testsuite_testsuite_test-server.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@mcapi/$(DEPDIR)/crypto.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@mcapi/$(DEPDIR)/mcapi_test.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@src/$(DEPDIR)/src_libcyassl_la-crl.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@src/$(DEPDIR)/src_libcyassl_la-internal.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@src/$(DEPDIR)/src_libcyassl_la-io.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@src/$(DEPDIR)/src_libcyassl_la-keys.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@src/$(DEPDIR)/src_libcyassl_la-ocsp.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@src/$(DEPDIR)/src_libcyassl_la-sniffer.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@src/$(DEPDIR)/src_libcyassl_la-ssl.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@src/$(DEPDIR)/src_libcyassl_la-tls.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@sslSniffer/sslSnifferTest/$(DEPDIR)/snifftest.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@tests/$(DEPDIR)/tests_unit_test-api.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@tests/$(DEPDIR)/tests_unit_test-hash.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@tests/$(DEPDIR)/tests_unit_test-suites.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@tests/$(DEPDIR)/tests_unit_test-unit.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@testsuite/$(DEPDIR)/testsuite_testsuite_test-testsuite.Po@am__quote@ + +.c.o: +@am__fastdepCC_TRUE@ $(AM_V_CC)depbase=`echo $@ | sed 's|[^/]*$$|$(DEPDIR)/&|;s|\.o$$||'`;\ +@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $$depbase.Tpo -c -o $@ $< &&\ +@am__fastdepCC_TRUE@ $(am__mv) $$depbase.Tpo $$depbase.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='$<' object='$@' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(COMPILE) -c -o $@ $< + +.c.obj: +@am__fastdepCC_TRUE@ $(AM_V_CC)depbase=`echo $@ | sed 's|[^/]*$$|$(DEPDIR)/&|;s|\.obj$$||'`;\ +@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $$depbase.Tpo -c -o $@ `$(CYGPATH_W) '$<'` &&\ +@am__fastdepCC_TRUE@ $(am__mv) $$depbase.Tpo $$depbase.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='$<' object='$@' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(COMPILE) -c -o $@ `$(CYGPATH_W) '$<'` + +.c.lo: +@am__fastdepCC_TRUE@ $(AM_V_CC)depbase=`echo $@ | sed 's|[^/]*$$|$(DEPDIR)/&|;s|\.lo$$||'`;\ +@am__fastdepCC_TRUE@ $(LTCOMPILE) -MT $@ -MD -MP -MF $$depbase.Tpo -c -o $@ $< &&\ +@am__fastdepCC_TRUE@ $(am__mv) $$depbase.Tpo $$depbase.Plo +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='$<' object='$@' libtool=yes @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(LTCOMPILE) -c -o $@ $< + +ctaocrypt/src/src_libcyassl_la-wolfcrypt_first.lo: ctaocrypt/src/wolfcrypt_first.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -MT ctaocrypt/src/src_libcyassl_la-wolfcrypt_first.lo -MD -MP -MF ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-wolfcrypt_first.Tpo -c -o ctaocrypt/src/src_libcyassl_la-wolfcrypt_first.lo `test -f 'ctaocrypt/src/wolfcrypt_first.c' || echo '$(srcdir)/'`ctaocrypt/src/wolfcrypt_first.c +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-wolfcrypt_first.Tpo ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-wolfcrypt_first.Plo +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='ctaocrypt/src/wolfcrypt_first.c' object='ctaocrypt/src/src_libcyassl_la-wolfcrypt_first.lo' libtool=yes @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -c -o ctaocrypt/src/src_libcyassl_la-wolfcrypt_first.lo `test -f 'ctaocrypt/src/wolfcrypt_first.c' || echo '$(srcdir)/'`ctaocrypt/src/wolfcrypt_first.c + +src/src_libcyassl_la-internal.lo: src/internal.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -MT src/src_libcyassl_la-internal.lo -MD -MP -MF src/$(DEPDIR)/src_libcyassl_la-internal.Tpo -c -o src/src_libcyassl_la-internal.lo `test -f 'src/internal.c' || echo '$(srcdir)/'`src/internal.c +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) src/$(DEPDIR)/src_libcyassl_la-internal.Tpo src/$(DEPDIR)/src_libcyassl_la-internal.Plo +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='src/internal.c' object='src/src_libcyassl_la-internal.lo' libtool=yes @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -c -o src/src_libcyassl_la-internal.lo `test -f 'src/internal.c' || echo '$(srcdir)/'`src/internal.c + +src/src_libcyassl_la-io.lo: src/io.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -MT src/src_libcyassl_la-io.lo -MD -MP -MF src/$(DEPDIR)/src_libcyassl_la-io.Tpo -c -o src/src_libcyassl_la-io.lo `test -f 'src/io.c' || echo '$(srcdir)/'`src/io.c +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) src/$(DEPDIR)/src_libcyassl_la-io.Tpo src/$(DEPDIR)/src_libcyassl_la-io.Plo +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='src/io.c' object='src/src_libcyassl_la-io.lo' libtool=yes @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -c -o src/src_libcyassl_la-io.lo `test -f 'src/io.c' || echo '$(srcdir)/'`src/io.c + +src/src_libcyassl_la-keys.lo: src/keys.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -MT src/src_libcyassl_la-keys.lo -MD -MP -MF src/$(DEPDIR)/src_libcyassl_la-keys.Tpo -c -o src/src_libcyassl_la-keys.lo `test -f 'src/keys.c' || echo '$(srcdir)/'`src/keys.c +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) src/$(DEPDIR)/src_libcyassl_la-keys.Tpo src/$(DEPDIR)/src_libcyassl_la-keys.Plo +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='src/keys.c' object='src/src_libcyassl_la-keys.lo' libtool=yes @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -c -o src/src_libcyassl_la-keys.lo `test -f 'src/keys.c' || echo '$(srcdir)/'`src/keys.c + +src/src_libcyassl_la-ssl.lo: src/ssl.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -MT src/src_libcyassl_la-ssl.lo -MD -MP -MF src/$(DEPDIR)/src_libcyassl_la-ssl.Tpo -c -o src/src_libcyassl_la-ssl.lo `test -f 'src/ssl.c' || echo '$(srcdir)/'`src/ssl.c +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) src/$(DEPDIR)/src_libcyassl_la-ssl.Tpo src/$(DEPDIR)/src_libcyassl_la-ssl.Plo +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='src/ssl.c' object='src/src_libcyassl_la-ssl.lo' libtool=yes @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -c -o src/src_libcyassl_la-ssl.lo `test -f 'src/ssl.c' || echo '$(srcdir)/'`src/ssl.c + +src/src_libcyassl_la-tls.lo: src/tls.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -MT src/src_libcyassl_la-tls.lo -MD -MP -MF src/$(DEPDIR)/src_libcyassl_la-tls.Tpo -c -o src/src_libcyassl_la-tls.lo `test -f 'src/tls.c' || echo '$(srcdir)/'`src/tls.c +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) src/$(DEPDIR)/src_libcyassl_la-tls.Tpo src/$(DEPDIR)/src_libcyassl_la-tls.Plo +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='src/tls.c' object='src/src_libcyassl_la-tls.lo' libtool=yes @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -c -o src/src_libcyassl_la-tls.lo `test -f 'src/tls.c' || echo '$(srcdir)/'`src/tls.c + +ctaocrypt/src/src_libcyassl_la-hmac.lo: ctaocrypt/src/hmac.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -MT ctaocrypt/src/src_libcyassl_la-hmac.lo -MD -MP -MF ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-hmac.Tpo -c -o ctaocrypt/src/src_libcyassl_la-hmac.lo `test -f 'ctaocrypt/src/hmac.c' || echo '$(srcdir)/'`ctaocrypt/src/hmac.c +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-hmac.Tpo ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-hmac.Plo +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='ctaocrypt/src/hmac.c' object='ctaocrypt/src/src_libcyassl_la-hmac.lo' libtool=yes @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -c -o ctaocrypt/src/src_libcyassl_la-hmac.lo `test -f 'ctaocrypt/src/hmac.c' || echo '$(srcdir)/'`ctaocrypt/src/hmac.c + +ctaocrypt/src/src_libcyassl_la-random.lo: ctaocrypt/src/random.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -MT ctaocrypt/src/src_libcyassl_la-random.lo -MD -MP -MF ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-random.Tpo -c -o ctaocrypt/src/src_libcyassl_la-random.lo `test -f 'ctaocrypt/src/random.c' || echo '$(srcdir)/'`ctaocrypt/src/random.c +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-random.Tpo ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-random.Plo +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='ctaocrypt/src/random.c' object='ctaocrypt/src/src_libcyassl_la-random.lo' libtool=yes @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -c -o ctaocrypt/src/src_libcyassl_la-random.lo `test -f 'ctaocrypt/src/random.c' || echo '$(srcdir)/'`ctaocrypt/src/random.c + +ctaocrypt/src/src_libcyassl_la-sha256.lo: ctaocrypt/src/sha256.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -MT ctaocrypt/src/src_libcyassl_la-sha256.lo -MD -MP -MF ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-sha256.Tpo -c -o ctaocrypt/src/src_libcyassl_la-sha256.lo `test -f 'ctaocrypt/src/sha256.c' || echo '$(srcdir)/'`ctaocrypt/src/sha256.c +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) 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+ctaocrypt/src/src_libcyassl_la-md4.lo: ctaocrypt/src/md4.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -MT ctaocrypt/src/src_libcyassl_la-md4.lo -MD -MP -MF ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-md4.Tpo -c -o ctaocrypt/src/src_libcyassl_la-md4.lo `test -f 'ctaocrypt/src/md4.c' || echo '$(srcdir)/'`ctaocrypt/src/md4.c +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-md4.Tpo ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-md4.Plo +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='ctaocrypt/src/md4.c' object='ctaocrypt/src/src_libcyassl_la-md4.lo' libtool=yes @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) 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+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -c -o ctaocrypt/src/src_libcyassl_la-sha512.lo `test -f 'ctaocrypt/src/sha512.c' || echo '$(srcdir)/'`ctaocrypt/src/sha512.c + +ctaocrypt/src/src_libcyassl_la-blake2b.lo: ctaocrypt/src/blake2b.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -MT ctaocrypt/src/src_libcyassl_la-blake2b.lo -MD -MP -MF ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-blake2b.Tpo -c -o ctaocrypt/src/src_libcyassl_la-blake2b.lo `test -f 'ctaocrypt/src/blake2b.c' || echo '$(srcdir)/'`ctaocrypt/src/blake2b.c +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-blake2b.Tpo ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-blake2b.Plo +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='ctaocrypt/src/blake2b.c' object='ctaocrypt/src/src_libcyassl_la-blake2b.lo' libtool=yes @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -c -o ctaocrypt/src/src_libcyassl_la-blake2b.lo `test -f 'ctaocrypt/src/blake2b.c' || echo '$(srcdir)/'`ctaocrypt/src/blake2b.c + +src/src_libcyassl_la-sniffer.lo: src/sniffer.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) 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+ctaocrypt/src/src_libcyassl_la-tfm.lo: ctaocrypt/src/tfm.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -MT ctaocrypt/src/src_libcyassl_la-tfm.lo -MD -MP -MF ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-tfm.Tpo -c -o ctaocrypt/src/src_libcyassl_la-tfm.lo `test -f 'ctaocrypt/src/tfm.c' || echo '$(srcdir)/'`ctaocrypt/src/tfm.c +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-tfm.Tpo ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-tfm.Plo +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='ctaocrypt/src/tfm.c' object='ctaocrypt/src/src_libcyassl_la-tfm.lo' libtool=yes @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) 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+src/src_libcyassl_la-crl.lo: src/crl.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -MT src/src_libcyassl_la-crl.lo -MD -MP -MF src/$(DEPDIR)/src_libcyassl_la-crl.Tpo -c -o src/src_libcyassl_la-crl.lo `test -f 'src/crl.c' || echo '$(srcdir)/'`src/crl.c +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) src/$(DEPDIR)/src_libcyassl_la-crl.Tpo src/$(DEPDIR)/src_libcyassl_la-crl.Plo +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='src/crl.c' object='src/src_libcyassl_la-crl.lo' libtool=yes @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) 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+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -c -o ctaocrypt/src/src_libcyassl_la-compress.lo `test -f 'ctaocrypt/src/compress.c' || echo '$(srcdir)/'`ctaocrypt/src/compress.c + +ctaocrypt/src/src_libcyassl_la-pkcs7.lo: ctaocrypt/src/pkcs7.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(src_libcyassl_la_CPPFLAGS) $(CPPFLAGS) $(src_libcyassl_la_CFLAGS) $(CFLAGS) -MT ctaocrypt/src/src_libcyassl_la-pkcs7.lo -MD -MP -MF ctaocrypt/src/$(DEPDIR)/src_libcyassl_la-pkcs7.Tpo -c -o ctaocrypt/src/src_libcyassl_la-pkcs7.lo `test -f 'ctaocrypt/src/pkcs7.c' || echo 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+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tests_unit_test_CFLAGS) $(CFLAGS) -c -o tests/tests_unit_test-api.o `test -f 'tests/api.c' || echo '$(srcdir)/'`tests/api.c + +tests/tests_unit_test-api.obj: tests/api.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tests_unit_test_CFLAGS) $(CFLAGS) -MT tests/tests_unit_test-api.obj -MD -MP -MF tests/$(DEPDIR)/tests_unit_test-api.Tpo -c -o tests/tests_unit_test-api.obj `if test -f 'tests/api.c'; then $(CYGPATH_W) 'tests/api.c'; else $(CYGPATH_W) '$(srcdir)/tests/api.c'; fi` +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) tests/$(DEPDIR)/tests_unit_test-api.Tpo tests/$(DEPDIR)/tests_unit_test-api.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='tests/api.c' object='tests/tests_unit_test-api.obj' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) 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ctaocrypt/test/testsuite_testsuite_test-test.obj `if test -f 'ctaocrypt/test/test.c'; then $(CYGPATH_W) 'ctaocrypt/test/test.c'; else $(CYGPATH_W) '$(srcdir)/ctaocrypt/test/test.c'; fi` +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) ctaocrypt/test/$(DEPDIR)/testsuite_testsuite_test-test.Tpo ctaocrypt/test/$(DEPDIR)/testsuite_testsuite_test-test.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='ctaocrypt/test/test.c' object='ctaocrypt/test/testsuite_testsuite_test-test.obj' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(testsuite_testsuite_test_CFLAGS) $(CFLAGS) -c -o ctaocrypt/test/testsuite_testsuite_test-test.obj `if test -f 'ctaocrypt/test/test.c'; then $(CYGPATH_W) 'ctaocrypt/test/test.c'; else $(CYGPATH_W) '$(srcdir)/ctaocrypt/test/test.c'; fi` + +examples/client/testsuite_testsuite_test-client.o: examples/client/client.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(testsuite_testsuite_test_CFLAGS) $(CFLAGS) -MT examples/client/testsuite_testsuite_test-client.o -MD -MP -MF examples/client/$(DEPDIR)/testsuite_testsuite_test-client.Tpo -c -o examples/client/testsuite_testsuite_test-client.o `test -f 'examples/client/client.c' || echo '$(srcdir)/'`examples/client/client.c +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) examples/client/$(DEPDIR)/testsuite_testsuite_test-client.Tpo examples/client/$(DEPDIR)/testsuite_testsuite_test-client.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='examples/client/client.c' object='examples/client/testsuite_testsuite_test-client.o' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) 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$(AM_V_CC)source='examples/client/client.c' object='examples/client/testsuite_testsuite_test-client.obj' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(testsuite_testsuite_test_CFLAGS) $(CFLAGS) -c -o examples/client/testsuite_testsuite_test-client.obj `if test -f 'examples/client/client.c'; then $(CYGPATH_W) 'examples/client/client.c'; else $(CYGPATH_W) '$(srcdir)/examples/client/client.c'; fi` + +examples/echoclient/testsuite_testsuite_test-echoclient.o: examples/echoclient/echoclient.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(testsuite_testsuite_test_CFLAGS) $(CFLAGS) -MT examples/echoclient/testsuite_testsuite_test-echoclient.o -MD -MP -MF examples/echoclient/$(DEPDIR)/testsuite_testsuite_test-echoclient.Tpo -c -o examples/echoclient/testsuite_testsuite_test-echoclient.o `test -f 'examples/echoclient/echoclient.c' || echo '$(srcdir)/'`examples/echoclient/echoclient.c +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) examples/echoclient/$(DEPDIR)/testsuite_testsuite_test-echoclient.Tpo examples/echoclient/$(DEPDIR)/testsuite_testsuite_test-echoclient.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='examples/echoclient/echoclient.c' object='examples/echoclient/testsuite_testsuite_test-echoclient.o' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(testsuite_testsuite_test_CFLAGS) $(CFLAGS) -c -o examples/echoclient/testsuite_testsuite_test-echoclient.o `test -f 'examples/echoclient/echoclient.c' || echo '$(srcdir)/'`examples/echoclient/echoclient.c + +examples/echoclient/testsuite_testsuite_test-echoclient.obj: examples/echoclient/echoclient.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(testsuite_testsuite_test_CFLAGS) $(CFLAGS) -MT examples/echoclient/testsuite_testsuite_test-echoclient.obj -MD -MP -MF examples/echoclient/$(DEPDIR)/testsuite_testsuite_test-echoclient.Tpo -c -o examples/echoclient/testsuite_testsuite_test-echoclient.obj `if test -f 'examples/echoclient/echoclient.c'; then $(CYGPATH_W) 'examples/echoclient/echoclient.c'; else $(CYGPATH_W) '$(srcdir)/examples/echoclient/echoclient.c'; fi` +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) examples/echoclient/$(DEPDIR)/testsuite_testsuite_test-echoclient.Tpo examples/echoclient/$(DEPDIR)/testsuite_testsuite_test-echoclient.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='examples/echoclient/echoclient.c' object='examples/echoclient/testsuite_testsuite_test-echoclient.obj' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(testsuite_testsuite_test_CFLAGS) $(CFLAGS) -c -o examples/echoclient/testsuite_testsuite_test-echoclient.obj `if test -f 'examples/echoclient/echoclient.c'; then $(CYGPATH_W) 'examples/echoclient/echoclient.c'; else $(CYGPATH_W) '$(srcdir)/examples/echoclient/echoclient.c'; fi` + +examples/echoserver/testsuite_testsuite_test-echoserver.o: examples/echoserver/echoserver.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(testsuite_testsuite_test_CFLAGS) $(CFLAGS) -MT examples/echoserver/testsuite_testsuite_test-echoserver.o -MD -MP -MF examples/echoserver/$(DEPDIR)/testsuite_testsuite_test-echoserver.Tpo -c -o examples/echoserver/testsuite_testsuite_test-echoserver.o `test -f 'examples/echoserver/echoserver.c' || echo '$(srcdir)/'`examples/echoserver/echoserver.c +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) examples/echoserver/$(DEPDIR)/testsuite_testsuite_test-echoserver.Tpo examples/echoserver/$(DEPDIR)/testsuite_testsuite_test-echoserver.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='examples/echoserver/echoserver.c' object='examples/echoserver/testsuite_testsuite_test-echoserver.o' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(testsuite_testsuite_test_CFLAGS) $(CFLAGS) -c -o examples/echoserver/testsuite_testsuite_test-echoserver.o `test -f 'examples/echoserver/echoserver.c' || echo '$(srcdir)/'`examples/echoserver/echoserver.c + +examples/echoserver/testsuite_testsuite_test-echoserver.obj: examples/echoserver/echoserver.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(testsuite_testsuite_test_CFLAGS) $(CFLAGS) -MT examples/echoserver/testsuite_testsuite_test-echoserver.obj -MD -MP -MF examples/echoserver/$(DEPDIR)/testsuite_testsuite_test-echoserver.Tpo -c -o examples/echoserver/testsuite_testsuite_test-echoserver.obj `if test -f 'examples/echoserver/echoserver.c'; then $(CYGPATH_W) 'examples/echoserver/echoserver.c'; else $(CYGPATH_W) '$(srcdir)/examples/echoserver/echoserver.c'; fi` +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) examples/echoserver/$(DEPDIR)/testsuite_testsuite_test-echoserver.Tpo examples/echoserver/$(DEPDIR)/testsuite_testsuite_test-echoserver.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='examples/echoserver/echoserver.c' object='examples/echoserver/testsuite_testsuite_test-echoserver.obj' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(testsuite_testsuite_test_CFLAGS) $(CFLAGS) -c -o examples/echoserver/testsuite_testsuite_test-echoserver.obj `if test -f 'examples/echoserver/echoserver.c'; then $(CYGPATH_W) 'examples/echoserver/echoserver.c'; else $(CYGPATH_W) '$(srcdir)/examples/echoserver/echoserver.c'; fi` + +examples/server/testsuite_testsuite_test-server.o: examples/server/server.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(testsuite_testsuite_test_CFLAGS) $(CFLAGS) -MT examples/server/testsuite_testsuite_test-server.o -MD -MP -MF examples/server/$(DEPDIR)/testsuite_testsuite_test-server.Tpo -c -o examples/server/testsuite_testsuite_test-server.o `test -f 'examples/server/server.c' || echo '$(srcdir)/'`examples/server/server.c +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) examples/server/$(DEPDIR)/testsuite_testsuite_test-server.Tpo examples/server/$(DEPDIR)/testsuite_testsuite_test-server.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='examples/server/server.c' object='examples/server/testsuite_testsuite_test-server.o' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(testsuite_testsuite_test_CFLAGS) $(CFLAGS) -c -o examples/server/testsuite_testsuite_test-server.o `test -f 'examples/server/server.c' || echo '$(srcdir)/'`examples/server/server.c + +examples/server/testsuite_testsuite_test-server.obj: examples/server/server.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(testsuite_testsuite_test_CFLAGS) $(CFLAGS) -MT examples/server/testsuite_testsuite_test-server.obj -MD -MP -MF examples/server/$(DEPDIR)/testsuite_testsuite_test-server.Tpo -c -o examples/server/testsuite_testsuite_test-server.obj `if test -f 'examples/server/server.c'; then $(CYGPATH_W) 'examples/server/server.c'; else $(CYGPATH_W) '$(srcdir)/examples/server/server.c'; fi` +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) examples/server/$(DEPDIR)/testsuite_testsuite_test-server.Tpo examples/server/$(DEPDIR)/testsuite_testsuite_test-server.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='examples/server/server.c' object='examples/server/testsuite_testsuite_test-server.obj' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(testsuite_testsuite_test_CFLAGS) $(CFLAGS) -c -o examples/server/testsuite_testsuite_test-server.obj `if test -f 'examples/server/server.c'; then $(CYGPATH_W) 'examples/server/server.c'; else $(CYGPATH_W) '$(srcdir)/examples/server/server.c'; fi` + +testsuite/testsuite_testsuite_test-testsuite.o: testsuite/testsuite.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(testsuite_testsuite_test_CFLAGS) $(CFLAGS) -MT testsuite/testsuite_testsuite_test-testsuite.o -MD -MP -MF testsuite/$(DEPDIR)/testsuite_testsuite_test-testsuite.Tpo -c -o testsuite/testsuite_testsuite_test-testsuite.o `test -f 'testsuite/testsuite.c' || echo '$(srcdir)/'`testsuite/testsuite.c +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) testsuite/$(DEPDIR)/testsuite_testsuite_test-testsuite.Tpo testsuite/$(DEPDIR)/testsuite_testsuite_test-testsuite.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='testsuite/testsuite.c' object='testsuite/testsuite_testsuite_test-testsuite.o' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(testsuite_testsuite_test_CFLAGS) $(CFLAGS) -c -o testsuite/testsuite_testsuite_test-testsuite.o `test -f 'testsuite/testsuite.c' || echo '$(srcdir)/'`testsuite/testsuite.c + +testsuite/testsuite_testsuite_test-testsuite.obj: testsuite/testsuite.c +@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(testsuite_testsuite_test_CFLAGS) $(CFLAGS) -MT testsuite/testsuite_testsuite_test-testsuite.obj -MD -MP -MF testsuite/$(DEPDIR)/testsuite_testsuite_test-testsuite.Tpo -c -o testsuite/testsuite_testsuite_test-testsuite.obj `if test -f 'testsuite/testsuite.c'; then $(CYGPATH_W) 'testsuite/testsuite.c'; else $(CYGPATH_W) '$(srcdir)/testsuite/testsuite.c'; fi` +@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) testsuite/$(DEPDIR)/testsuite_testsuite_test-testsuite.Tpo testsuite/$(DEPDIR)/testsuite_testsuite_test-testsuite.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='testsuite/testsuite.c' object='testsuite/testsuite_testsuite_test-testsuite.obj' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(testsuite_testsuite_test_CFLAGS) $(CFLAGS) -c -o testsuite/testsuite_testsuite_test-testsuite.obj `if test -f 'testsuite/testsuite.c'; then $(CYGPATH_W) 'testsuite/testsuite.c'; else $(CYGPATH_W) '$(srcdir)/testsuite/testsuite.c'; fi` + +.s.o: + $(AM_V_CCAS)$(CCASCOMPILE) -c -o $@ $< + +.s.obj: + $(AM_V_CCAS)$(CCASCOMPILE) -c -o $@ `$(CYGPATH_W) '$<'` + +.s.lo: + $(AM_V_CCAS)$(LTCCASCOMPILE) -c -o $@ $< + +mostlyclean-libtool: + -rm -f *.lo + +clean-libtool: + -rm -rf .libs _libs + -rm -rf ctaocrypt/benchmark/.libs ctaocrypt/benchmark/_libs + -rm -rf ctaocrypt/src/.libs ctaocrypt/src/_libs + -rm -rf ctaocrypt/test/.libs ctaocrypt/test/_libs + -rm -rf examples/client/.libs examples/client/_libs + -rm -rf examples/echoclient/.libs examples/echoclient/_libs + -rm -rf examples/echoserver/.libs examples/echoserver/_libs + -rm -rf examples/server/.libs examples/server/_libs + -rm -rf mcapi/.libs mcapi/_libs + -rm -rf src/.libs src/_libs + -rm -rf sslSniffer/sslSnifferTest/.libs sslSniffer/sslSnifferTest/_libs + -rm -rf tests/.libs tests/_libs + -rm -rf testsuite/.libs testsuite/_libs + +distclean-libtool: + -rm -f libtool config.lt +install-dist_docDATA: $(dist_doc_DATA) + @$(NORMAL_INSTALL) + @list='$(dist_doc_DATA)'; test -n "$(docdir)" || list=; \ + if test -n "$$list"; then \ + echo " $(MKDIR_P) '$(DESTDIR)$(docdir)'"; \ + $(MKDIR_P) "$(DESTDIR)$(docdir)" || exit 1; \ + fi; \ + for p in $$list; do \ + if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \ + echo "$$d$$p"; \ + done | $(am__base_list) | \ + while read files; do \ + echo " $(INSTALL_DATA) $$files '$(DESTDIR)$(docdir)'"; \ + $(INSTALL_DATA) $$files "$(DESTDIR)$(docdir)" || exit $$?; \ + done + +uninstall-dist_docDATA: + @$(NORMAL_UNINSTALL) + @list='$(dist_doc_DATA)'; test -n "$(docdir)" || list=; \ + files=`for p in $$list; do echo $$p; done | sed -e 's|^.*/||'`; \ + dir='$(DESTDIR)$(docdir)'; $(am__uninstall_files_from_dir) +install-dist_exampleDATA: $(dist_example_DATA) + @$(NORMAL_INSTALL) + @list='$(dist_example_DATA)'; test -n "$(exampledir)" || list=; \ + if test -n "$$list"; then \ + echo " $(MKDIR_P) '$(DESTDIR)$(exampledir)'"; \ + $(MKDIR_P) "$(DESTDIR)$(exampledir)" || exit 1; \ + fi; \ + for p in $$list; do \ + if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \ + echo "$$d$$p"; \ + done | $(am__base_list) | \ + while read files; do \ + echo " $(INSTALL_DATA) $$files '$(DESTDIR)$(exampledir)'"; \ + $(INSTALL_DATA) $$files "$(DESTDIR)$(exampledir)" || exit $$?; \ + done + +uninstall-dist_exampleDATA: + @$(NORMAL_UNINSTALL) + @list='$(dist_example_DATA)'; test -n "$(exampledir)" || list=; \ + files=`for p in $$list; do echo $$p; done | sed -e 's|^.*/||'`; \ + dir='$(DESTDIR)$(exampledir)'; $(am__uninstall_files_from_dir) +install-pkgconfigDATA: $(pkgconfig_DATA) + @$(NORMAL_INSTALL) + @list='$(pkgconfig_DATA)'; test -n "$(pkgconfigdir)" || list=; \ + if test -n "$$list"; then \ + echo " $(MKDIR_P) '$(DESTDIR)$(pkgconfigdir)'"; \ + $(MKDIR_P) "$(DESTDIR)$(pkgconfigdir)" || exit 1; \ + fi; \ + for p in $$list; do \ + if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \ + echo "$$d$$p"; \ + done | $(am__base_list) | \ + while read files; do \ + echo " $(INSTALL_DATA) $$files '$(DESTDIR)$(pkgconfigdir)'"; \ + $(INSTALL_DATA) $$files "$(DESTDIR)$(pkgconfigdir)" || exit $$?; \ + done + +uninstall-pkgconfigDATA: + @$(NORMAL_UNINSTALL) + @list='$(pkgconfig_DATA)'; test -n "$(pkgconfigdir)" || list=; \ + files=`for p in $$list; do echo $$p; done | sed -e 's|^.*/||'`; \ + dir='$(DESTDIR)$(pkgconfigdir)'; $(am__uninstall_files_from_dir) +install-includeHEADERS: $(include_HEADERS) + @$(NORMAL_INSTALL) + @list='$(include_HEADERS)'; test -n "$(includedir)" || list=; \ + if test -n "$$list"; then \ + echo " $(MKDIR_P) '$(DESTDIR)$(includedir)'"; \ + $(MKDIR_P) "$(DESTDIR)$(includedir)" || exit 1; \ + fi; \ + for p in $$list; do \ + if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \ + echo "$$d$$p"; \ + done | $(am__base_list) | \ + while read files; do \ + echo " $(INSTALL_HEADER) $$files '$(DESTDIR)$(includedir)'"; \ + $(INSTALL_HEADER) $$files "$(DESTDIR)$(includedir)" || exit $$?; \ + done + +uninstall-includeHEADERS: + @$(NORMAL_UNINSTALL) + @list='$(include_HEADERS)'; test -n "$(includedir)" || list=; \ + files=`for p in $$list; do echo $$p; done | sed -e 's|^.*/||'`; \ + dir='$(DESTDIR)$(includedir)'; $(am__uninstall_files_from_dir) +install-nobase_includeHEADERS: $(nobase_include_HEADERS) + @$(NORMAL_INSTALL) + @list='$(nobase_include_HEADERS)'; test -n "$(includedir)" || list=; \ + if test -n "$$list"; then \ + echo " $(MKDIR_P) '$(DESTDIR)$(includedir)'"; \ + $(MKDIR_P) "$(DESTDIR)$(includedir)" || exit 1; \ + fi; \ + $(am__nobase_list) | while read dir files; do \ + xfiles=; for file in $$files; do \ + if test -f "$$file"; then xfiles="$$xfiles $$file"; \ + else xfiles="$$xfiles $(srcdir)/$$file"; fi; done; \ + test -z "$$xfiles" || { \ + test "x$$dir" = x. || { \ + echo " $(MKDIR_P) '$(DESTDIR)$(includedir)/$$dir'"; \ + $(MKDIR_P) "$(DESTDIR)$(includedir)/$$dir"; }; \ + echo " $(INSTALL_HEADER) $$xfiles '$(DESTDIR)$(includedir)/$$dir'"; \ + $(INSTALL_HEADER) $$xfiles "$(DESTDIR)$(includedir)/$$dir" || exit $$?; }; \ + done + +uninstall-nobase_includeHEADERS: + @$(NORMAL_UNINSTALL) + @list='$(nobase_include_HEADERS)'; test -n "$(includedir)" || list=; \ + $(am__nobase_strip_setup); files=`$(am__nobase_strip)`; \ + dir='$(DESTDIR)$(includedir)'; $(am__uninstall_files_from_dir) + +ID: $(am__tagged_files) + $(am__define_uniq_tagged_files); mkid -fID $$unique +tags: tags-am +TAGS: tags + +tags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files) + set x; \ + here=`pwd`; \ + $(am__define_uniq_tagged_files); \ + shift; \ + if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \ + test -n "$$unique" || unique=$$empty_fix; \ + if test $$# -gt 0; then \ + $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \ + "$$@" $$unique; \ + else \ + $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \ + $$unique; \ + fi; \ + fi +ctags: ctags-am + +CTAGS: ctags +ctags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files) + $(am__define_uniq_tagged_files); \ + test -z "$(CTAGS_ARGS)$$unique" \ + || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \ + $$unique + +GTAGS: + here=`$(am__cd) $(top_builddir) && pwd` \ + && $(am__cd) $(top_srcdir) \ + && gtags -i $(GTAGS_ARGS) "$$here" +cscope: cscope.files + test ! -s cscope.files \ + || $(CSCOPE) -b -q $(AM_CSCOPEFLAGS) $(CSCOPEFLAGS) -i cscope.files $(CSCOPE_ARGS) +clean-cscope: + -rm -f cscope.files +cscope.files: clean-cscope cscopelist +cscopelist: cscopelist-am + +cscopelist-am: $(am__tagged_files) + list='$(am__tagged_files)'; \ + case "$(srcdir)" in \ + [\\/]* | ?:[\\/]*) sdir="$(srcdir)" ;; \ + *) sdir=$(subdir)/$(srcdir) ;; \ + esac; \ + for i in $$list; do \ + if test -f "$$i"; then \ + echo "$(subdir)/$$i"; \ + else \ + echo "$$sdir/$$i"; \ + fi; \ + done >> $(top_builddir)/cscope.files + +distclean-tags: + -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags + -rm -f cscope.out cscope.in.out cscope.po.out cscope.files + +# Recover from deleted '.trs' file; this should ensure that +# "rm -f foo.log; make foo.trs" re-run 'foo.test', and re-create +# both 'foo.log' and 'foo.trs'. Break the recipe in two subshells +# to avoid problems with "make -n". +.log.trs: + rm -f $< $@ + $(MAKE) $(AM_MAKEFLAGS) $< + +# Leading 'am--fnord' is there to ensure the list of targets does not +# expand to empty, as could happen e.g. with make check TESTS=''. +am--fnord $(TEST_LOGS) $(TEST_LOGS:.log=.trs): $(am__force_recheck) +am--force-recheck: + @: + +$(TEST_SUITE_LOG): $(TEST_LOGS) + @$(am__set_TESTS_bases); \ + am__f_ok () { test -f "$$1" && test -r "$$1"; }; \ + redo_bases=`for i in $$bases; do \ + am__f_ok $$i.trs && am__f_ok $$i.log || echo $$i; \ + done`; \ + if test -n "$$redo_bases"; then \ + redo_logs=`for i in $$redo_bases; do echo $$i.log; done`; \ + redo_results=`for i in $$redo_bases; do echo $$i.trs; done`; \ + if $(am__make_dryrun); then :; else \ + rm -f $$redo_logs && rm -f $$redo_results || exit 1; \ + fi; \ + fi; \ + if test -n "$$am__remaking_logs"; then \ + echo "fatal: making $(TEST_SUITE_LOG): possible infinite" \ + "recursion detected" >&2; \ + else \ + am__remaking_logs=yes $(MAKE) $(AM_MAKEFLAGS) $$redo_logs; \ + fi; \ + if $(am__make_dryrun); then :; else \ + st=0; \ + errmsg="fatal: making $(TEST_SUITE_LOG): failed to create"; \ + for i in $$redo_bases; do \ + test -f $$i.trs && test -r $$i.trs \ + || { echo "$$errmsg $$i.trs" >&2; st=1; }; \ + test -f $$i.log && test -r $$i.log \ + || { echo "$$errmsg $$i.log" >&2; st=1; }; \ + done; \ + test $$st -eq 0 || exit 1; \ + fi + @$(am__sh_e_setup); $(am__tty_colors); $(am__set_TESTS_bases); \ + ws='[ ]'; \ + results=`for b in $$bases; do echo $$b.trs; done`; \ + test -n "$$results" || results=/dev/null; \ + all=` grep "^$$ws*:test-result:" $$results | wc -l`; \ + pass=` grep "^$$ws*:test-result:$$ws*PASS" $$results | wc -l`; \ + fail=` grep "^$$ws*:test-result:$$ws*FAIL" $$results | wc -l`; \ + skip=` grep "^$$ws*:test-result:$$ws*SKIP" $$results | wc -l`; \ + xfail=`grep "^$$ws*:test-result:$$ws*XFAIL" $$results | wc -l`; \ + xpass=`grep "^$$ws*:test-result:$$ws*XPASS" $$results | wc -l`; \ + error=`grep "^$$ws*:test-result:$$ws*ERROR" $$results | wc -l`; \ + if test `expr $$fail + $$xpass + $$error` -eq 0; then \ + success=true; \ + else \ + success=false; \ + fi; \ + br='==================='; br=$$br$$br$$br$$br; \ + result_count () \ + { \ + if test x"$$1" = x"--maybe-color"; then \ + maybe_colorize=yes; \ + elif test x"$$1" = x"--no-color"; then \ + maybe_colorize=no; \ + else \ + echo "$@: invalid 'result_count' usage" >&2; exit 4; \ + fi; \ + shift; \ + desc=$$1 count=$$2; \ + if test $$maybe_colorize = yes && test $$count -gt 0; then \ + color_start=$$3 color_end=$$std; \ + else \ + color_start= color_end=; \ + fi; \ + echo "$${color_start}# $$desc $$count$${color_end}"; \ + }; \ + create_testsuite_report () \ + { \ + result_count $$1 "TOTAL:" $$all "$$brg"; \ + result_count $$1 "PASS: " $$pass "$$grn"; \ + result_count $$1 "SKIP: " $$skip "$$blu"; \ + result_count $$1 "XFAIL:" $$xfail "$$lgn"; \ + result_count $$1 "FAIL: " $$fail "$$red"; \ + result_count $$1 "XPASS:" $$xpass "$$red"; \ + result_count $$1 "ERROR:" $$error "$$mgn"; \ + }; \ + { \ + echo "$(PACKAGE_STRING): $(subdir)/$(TEST_SUITE_LOG)" | \ + $(am__rst_title); \ + create_testsuite_report --no-color; \ + echo; \ + echo ".. contents:: :depth: 2"; \ + echo; \ + for b in $$bases; do echo $$b; done \ + | $(am__create_global_log); \ + } >$(TEST_SUITE_LOG).tmp || exit 1; \ + mv $(TEST_SUITE_LOG).tmp $(TEST_SUITE_LOG); \ + if $$success; then \ + col="$$grn"; \ + else \ + col="$$red"; \ + test x"$$VERBOSE" = x || cat $(TEST_SUITE_LOG); \ + fi; \ + echo "$${col}$$br$${std}"; \ + echo "$${col}Testsuite summary for $(PACKAGE_STRING)$${std}"; \ + echo "$${col}$$br$${std}"; \ + create_testsuite_report --maybe-color; \ + echo "$$col$$br$$std"; \ + if $$success; then :; else \ + echo "$${col}See $(subdir)/$(TEST_SUITE_LOG)$${std}"; \ + if test -n "$(PACKAGE_BUGREPORT)"; then \ + echo "$${col}Please report to $(PACKAGE_BUGREPORT)$${std}"; \ + fi; \ + echo "$$col$$br$$std"; \ + fi; \ + $$success || exit 1 + +check-TESTS: + @list='$(RECHECK_LOGS)'; test -z "$$list" || rm -f $$list + @list='$(RECHECK_LOGS:.log=.trs)'; test -z "$$list" || rm -f $$list + @test -z "$(TEST_SUITE_LOG)" || rm -f $(TEST_SUITE_LOG) + @set +e; $(am__set_TESTS_bases); \ + log_list=`for i in $$bases; do echo $$i.log; done`; \ + trs_list=`for i in $$bases; do echo $$i.trs; done`; \ + log_list=`echo $$log_list`; trs_list=`echo $$trs_list`; \ + $(MAKE) $(AM_MAKEFLAGS) $(TEST_SUITE_LOG) TEST_LOGS="$$log_list"; \ + exit $$?; +recheck: all $(check_PROGRAMS) + @test -z "$(TEST_SUITE_LOG)" || rm -f $(TEST_SUITE_LOG) + @set +e; $(am__set_TESTS_bases); \ + bases=`for i in $$bases; do echo $$i; done \ + | $(am__list_recheck_tests)` || exit 1; \ + log_list=`for i in $$bases; do echo $$i.log; done`; \ + log_list=`echo $$log_list`; \ + $(MAKE) $(AM_MAKEFLAGS) $(TEST_SUITE_LOG) \ + am__force_recheck=am--force-recheck \ + TEST_LOGS="$$log_list"; \ + exit $$? +mcapi/test.log: mcapi/test$(EXEEXT) + @p='mcapi/test$(EXEEXT)'; \ + b='mcapi/test'; \ + $(am__check_pre) $(LOG_DRIVER) --test-name "$$f" \ + --log-file $$b.log --trs-file $$b.trs \ + $(am__common_driver_flags) $(AM_LOG_DRIVER_FLAGS) $(LOG_DRIVER_FLAGS) -- $(LOG_COMPILE) \ + "$$tst" $(AM_TESTS_FD_REDIRECT) +.test.log: + @p='$<'; \ + $(am__set_b); \ + $(am__check_pre) $(TEST_LOG_DRIVER) --test-name "$$f" \ + --log-file $$b.log --trs-file $$b.trs \ + $(am__common_driver_flags) $(AM_TEST_LOG_DRIVER_FLAGS) $(TEST_LOG_DRIVER_FLAGS) -- $(TEST_LOG_COMPILE) \ + "$$tst" $(AM_TESTS_FD_REDIRECT) +@am__EXEEXT_TRUE@.test$(EXEEXT).log: +@am__EXEEXT_TRUE@ @p='$<'; \ +@am__EXEEXT_TRUE@ $(am__set_b); \ +@am__EXEEXT_TRUE@ $(am__check_pre) $(TEST_LOG_DRIVER) --test-name "$$f" \ +@am__EXEEXT_TRUE@ --log-file $$b.log --trs-file $$b.trs \ +@am__EXEEXT_TRUE@ $(am__common_driver_flags) $(AM_TEST_LOG_DRIVER_FLAGS) $(TEST_LOG_DRIVER_FLAGS) -- $(TEST_LOG_COMPILE) \ +@am__EXEEXT_TRUE@ "$$tst" $(AM_TESTS_FD_REDIRECT) + +distdir: $(DISTFILES) + $(am__remove_distdir) + test -d "$(distdir)" || mkdir "$(distdir)" + @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \ + topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \ + list='$(DISTFILES)'; \ + dist_files=`for file in $$list; do echo $$file; done | \ + sed -e "s|^$$srcdirstrip/||;t" \ + -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \ + case $$dist_files in \ + */*) $(MKDIR_P) `echo "$$dist_files" | \ + sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \ + sort -u` ;; \ + esac; \ + for file in $$dist_files; do \ + if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \ + if test -d $$d/$$file; then \ + dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \ + if test -d "$(distdir)/$$file"; then \ + find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \ + fi; \ + if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \ + cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \ + find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \ + fi; \ + cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \ + else \ + test -f "$(distdir)/$$file" \ + || cp -p $$d/$$file "$(distdir)/$$file" \ + || exit 1; \ + fi; \ + done + -test -n "$(am__skip_mode_fix)" \ + || find "$(distdir)" -type d ! -perm -755 \ + -exec chmod u+rwx,go+rx {} \; -o \ + ! -type d ! -perm -444 -links 1 -exec chmod a+r {} \; -o \ + ! -type d ! -perm -400 -exec chmod a+r {} \; -o \ + ! -type d ! -perm -444 -exec $(install_sh) -c -m a+r {} {} \; \ + || chmod -R a+r "$(distdir)" +dist-gzip: distdir + tardir=$(distdir) && $(am__tar) | GZIP=$(GZIP_ENV) gzip -c >$(distdir).tar.gz + $(am__post_remove_distdir) + +dist-bzip2: distdir + tardir=$(distdir) && $(am__tar) | BZIP2=$${BZIP2--9} bzip2 -c >$(distdir).tar.bz2 + $(am__post_remove_distdir) + +dist-lzip: distdir + tardir=$(distdir) && $(am__tar) | lzip -c $${LZIP_OPT--9} >$(distdir).tar.lz + $(am__post_remove_distdir) + +dist-xz: distdir + tardir=$(distdir) && $(am__tar) | XZ_OPT=$${XZ_OPT--e} xz -c >$(distdir).tar.xz + $(am__post_remove_distdir) + +dist-tarZ: distdir + @echo WARNING: "Support for shar distribution archives is" \ + "deprecated." >&2 + @echo WARNING: "It will be removed altogether in Automake 2.0" >&2 + tardir=$(distdir) && $(am__tar) | compress -c >$(distdir).tar.Z + $(am__post_remove_distdir) + +dist-shar: distdir + @echo WARNING: "Support for distribution archives compressed with" \ + "legacy program 'compress' is deprecated." >&2 + @echo WARNING: "It will be removed altogether in Automake 2.0" >&2 + shar $(distdir) | GZIP=$(GZIP_ENV) gzip -c >$(distdir).shar.gz + $(am__post_remove_distdir) + +dist-zip: distdir + -rm -f $(distdir).zip + zip -rq $(distdir).zip $(distdir) + $(am__post_remove_distdir) + +dist dist-all: + $(MAKE) $(AM_MAKEFLAGS) $(DIST_TARGETS) am__post_remove_distdir='@:' + $(am__post_remove_distdir) + +# This target untars the dist file and tries a VPATH configuration. Then +# it guarantees that the distribution is self-contained by making another +# tarfile. +distcheck: dist + case '$(DIST_ARCHIVES)' in \ + *.tar.gz*) \ + GZIP=$(GZIP_ENV) gzip -dc $(distdir).tar.gz | $(am__untar) ;;\ + *.tar.bz2*) \ + bzip2 -dc $(distdir).tar.bz2 | $(am__untar) ;;\ + *.tar.lz*) \ + lzip -dc $(distdir).tar.lz | $(am__untar) ;;\ + *.tar.xz*) \ + xz -dc $(distdir).tar.xz | $(am__untar) ;;\ + *.tar.Z*) \ + uncompress -c $(distdir).tar.Z | $(am__untar) ;;\ + *.shar.gz*) \ + GZIP=$(GZIP_ENV) gzip -dc $(distdir).shar.gz | unshar ;;\ + *.zip*) \ + unzip $(distdir).zip ;;\ + esac + chmod -R a-w $(distdir) + chmod u+w $(distdir) + mkdir $(distdir)/_build $(distdir)/_inst + chmod a-w $(distdir) + test -d $(distdir)/_build || exit 0; \ + dc_install_base=`$(am__cd) $(distdir)/_inst && pwd | sed -e 's,^[^:\\/]:[\\/],/,'` \ + && dc_destdir="$${TMPDIR-/tmp}/am-dc-$$$$/" \ + && am__cwd=`pwd` \ + && $(am__cd) $(distdir)/_build \ + && ../configure \ + $(AM_DISTCHECK_CONFIGURE_FLAGS) \ + $(DISTCHECK_CONFIGURE_FLAGS) \ + --srcdir=.. --prefix="$$dc_install_base" \ + && $(MAKE) $(AM_MAKEFLAGS) \ + && $(MAKE) $(AM_MAKEFLAGS) dvi \ + && $(MAKE) $(AM_MAKEFLAGS) check \ + && $(MAKE) $(AM_MAKEFLAGS) install \ + && $(MAKE) $(AM_MAKEFLAGS) installcheck \ + && $(MAKE) $(AM_MAKEFLAGS) uninstall \ + && $(MAKE) $(AM_MAKEFLAGS) distuninstallcheck_dir="$$dc_install_base" \ + distuninstallcheck \ + && chmod -R a-w "$$dc_install_base" \ + && ({ \ + (cd ../.. && umask 077 && mkdir "$$dc_destdir") \ + && $(MAKE) $(AM_MAKEFLAGS) DESTDIR="$$dc_destdir" install \ + && $(MAKE) $(AM_MAKEFLAGS) DESTDIR="$$dc_destdir" uninstall \ + && $(MAKE) $(AM_MAKEFLAGS) DESTDIR="$$dc_destdir" \ + distuninstallcheck_dir="$$dc_destdir" distuninstallcheck; \ + } || { rm -rf "$$dc_destdir"; exit 1; }) \ + && rm -rf "$$dc_destdir" \ + && $(MAKE) $(AM_MAKEFLAGS) dist \ + && rm -rf $(DIST_ARCHIVES) \ + && $(MAKE) $(AM_MAKEFLAGS) distcleancheck \ + && cd "$$am__cwd" \ + || exit 1 + $(am__post_remove_distdir) + @(echo "$(distdir) archives ready for distribution: "; \ + list='$(DIST_ARCHIVES)'; for i in $$list; do echo $$i; done) | \ + sed -e 1h -e 1s/./=/g -e 1p -e 1x -e '$$p' -e '$$x' +distuninstallcheck: + @test -n '$(distuninstallcheck_dir)' || { \ + echo 'ERROR: trying to run $@ with an empty' \ + '$$(distuninstallcheck_dir)' >&2; \ + exit 1; \ + }; \ + $(am__cd) '$(distuninstallcheck_dir)' || { \ + echo 'ERROR: cannot chdir into $(distuninstallcheck_dir)' >&2; \ + exit 1; \ + }; \ + test `$(am__distuninstallcheck_listfiles) | wc -l` -eq 0 \ + || { echo "ERROR: files left after uninstall:" ; \ + if test -n "$(DESTDIR)"; then \ + echo " (check DESTDIR support)"; \ + fi ; \ + $(distuninstallcheck_listfiles) ; \ + exit 1; } >&2 +distcleancheck: distclean + @if test '$(srcdir)' = . ; then \ + echo "ERROR: distcleancheck can only run from a VPATH build" ; \ + exit 1 ; \ + fi + @test `$(distcleancheck_listfiles) | wc -l` -eq 0 \ + || { echo "ERROR: files left in build directory after distclean:" ; \ + $(distcleancheck_listfiles) ; \ + exit 1; } >&2 +check-am: all-am + $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS) + $(MAKE) $(AM_MAKEFLAGS) check-TESTS +check: $(BUILT_SOURCES) + $(MAKE) $(AM_MAKEFLAGS) check-am +all-am: Makefile $(LTLIBRARIES) $(PROGRAMS) $(DATA) $(HEADERS) \ + config.h +install-binPROGRAMS: install-libLTLIBRARIES + +installdirs: + for dir in "$(DESTDIR)$(libdir)" "$(DESTDIR)$(bindir)" "$(DESTDIR)$(docdir)" "$(DESTDIR)$(exampledir)" "$(DESTDIR)$(pkgconfigdir)" "$(DESTDIR)$(includedir)" "$(DESTDIR)$(includedir)"; do \ + test -z "$$dir" || $(MKDIR_P) "$$dir"; \ + done +install: $(BUILT_SOURCES) + $(MAKE) $(AM_MAKEFLAGS) install-am +install-exec: install-exec-am +install-data: install-data-am +uninstall: uninstall-am + +install-am: all-am + @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am + +installcheck: installcheck-am +install-strip: + if test -z '$(STRIP)'; then \ + $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \ + install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \ + install; \ + else \ + $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \ + install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \ + "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'" install; \ + fi +mostlyclean-generic: + -test -z "$(TEST_LOGS)" || rm -f $(TEST_LOGS) + -test -z "$(TEST_LOGS:.log=.trs)" || rm -f $(TEST_LOGS:.log=.trs) + -test -z "$(TEST_SUITE_LOG)" || rm -f $(TEST_SUITE_LOG) + +clean-generic: + -test -z "$(CLEANFILES)" || rm -f $(CLEANFILES) + +distclean-generic: + -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES) + -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES) + -rm -f ctaocrypt/benchmark/$(DEPDIR)/$(am__dirstamp) + -rm -f ctaocrypt/benchmark/$(am__dirstamp) + -rm -f ctaocrypt/src/$(DEPDIR)/$(am__dirstamp) + -rm -f ctaocrypt/src/$(am__dirstamp) + -rm -f ctaocrypt/test/$(DEPDIR)/$(am__dirstamp) + -rm -f ctaocrypt/test/$(am__dirstamp) + -rm -f examples/client/$(DEPDIR)/$(am__dirstamp) + -rm -f examples/client/$(am__dirstamp) + -rm -f examples/echoclient/$(DEPDIR)/$(am__dirstamp) + -rm -f examples/echoclient/$(am__dirstamp) + -rm -f examples/echoserver/$(DEPDIR)/$(am__dirstamp) + -rm -f examples/echoserver/$(am__dirstamp) + -rm -f examples/server/$(DEPDIR)/$(am__dirstamp) + -rm -f examples/server/$(am__dirstamp) + -rm -f mcapi/$(DEPDIR)/$(am__dirstamp) + -rm -f mcapi/$(am__dirstamp) + -rm -f src/$(DEPDIR)/$(am__dirstamp) + -rm -f src/$(am__dirstamp) + -rm -f sslSniffer/sslSnifferTest/$(DEPDIR)/$(am__dirstamp) + -rm -f sslSniffer/sslSnifferTest/$(am__dirstamp) + -rm -f tests/$(DEPDIR)/$(am__dirstamp) + -rm -f tests/$(am__dirstamp) + -rm -f testsuite/$(DEPDIR)/$(am__dirstamp) + -rm -f testsuite/$(am__dirstamp) + -test -z "$(DISTCLEANFILES)" || rm -f $(DISTCLEANFILES) + +maintainer-clean-generic: + @echo "This command is intended for maintainers to use" + @echo "it deletes files that may require special tools to rebuild." + -test -z "$(BUILT_SOURCES)" || rm -f $(BUILT_SOURCES) +clean: clean-am + +clean-am: clean-binPROGRAMS clean-checkPROGRAMS clean-generic \ + clean-libLTLIBRARIES clean-libtool clean-noinstLTLIBRARIES \ + clean-noinstPROGRAMS mostlyclean-am + +distclean: distclean-am + -rm -f $(am__CONFIG_DISTCLEAN_FILES) + -rm -rf ctaocrypt/benchmark/$(DEPDIR) ctaocrypt/src/$(DEPDIR) ctaocrypt/test/$(DEPDIR) examples/client/$(DEPDIR) examples/echoclient/$(DEPDIR) examples/echoserver/$(DEPDIR) examples/server/$(DEPDIR) mcapi/$(DEPDIR) src/$(DEPDIR) sslSniffer/sslSnifferTest/$(DEPDIR) tests/$(DEPDIR) testsuite/$(DEPDIR) + -rm -f Makefile +distclean-am: clean-am distclean-compile distclean-generic \ + distclean-hdr distclean-libtool distclean-tags + +dvi: dvi-am + +dvi-am: + +html: html-am + +html-am: + +info: info-am + +info-am: + +install-data-am: install-dist_docDATA install-dist_exampleDATA \ + install-includeHEADERS install-nobase_includeHEADERS \ + install-pkgconfigDATA + +install-dvi: install-dvi-am + +install-dvi-am: + +install-exec-am: install-binPROGRAMS install-exec-local \ + install-libLTLIBRARIES + +install-html: install-html-am + +install-html-am: + +install-info: install-info-am + +install-info-am: + +install-man: + +install-pdf: install-pdf-am + +install-pdf-am: + +install-ps: install-ps-am + +install-ps-am: + +installcheck-am: + +maintainer-clean: maintainer-clean-am + -rm -f $(am__CONFIG_DISTCLEAN_FILES) + -rm -rf $(top_srcdir)/autom4te.cache + -rm -rf ctaocrypt/benchmark/$(DEPDIR) ctaocrypt/src/$(DEPDIR) ctaocrypt/test/$(DEPDIR) examples/client/$(DEPDIR) examples/echoclient/$(DEPDIR) examples/echoserver/$(DEPDIR) examples/server/$(DEPDIR) mcapi/$(DEPDIR) src/$(DEPDIR) sslSniffer/sslSnifferTest/$(DEPDIR) tests/$(DEPDIR) testsuite/$(DEPDIR) + -rm -f Makefile +maintainer-clean-am: distclean-am maintainer-clean-generic \ + maintainer-clean-local + +mostlyclean: mostlyclean-am + +mostlyclean-am: mostlyclean-compile mostlyclean-generic \ + mostlyclean-libtool + +pdf: pdf-am + +pdf-am: + +ps: ps-am + +ps-am: + +uninstall-am: uninstall-binPROGRAMS uninstall-dist_docDATA \ + uninstall-dist_exampleDATA uninstall-includeHEADERS \ + uninstall-libLTLIBRARIES uninstall-local \ + uninstall-nobase_includeHEADERS uninstall-pkgconfigDATA + +.MAKE: all check check-am install install-am install-strip + +.PHONY: CTAGS GTAGS TAGS all all-am am--refresh check check-TESTS \ + check-am clean clean-binPROGRAMS clean-checkPROGRAMS \ + clean-cscope clean-generic clean-libLTLIBRARIES clean-libtool \ + clean-noinstLTLIBRARIES clean-noinstPROGRAMS cscope \ + cscopelist-am ctags ctags-am dist dist-all dist-bzip2 \ + dist-gzip dist-lzip dist-shar dist-tarZ dist-xz dist-zip \ + distcheck distclean distclean-compile distclean-generic \ + distclean-hdr distclean-libtool distclean-tags distcleancheck \ + distdir distuninstallcheck dvi dvi-am html html-am info \ + info-am install install-am install-binPROGRAMS install-data \ + install-data-am install-dist_docDATA install-dist_exampleDATA \ + install-dvi install-dvi-am install-exec install-exec-am \ + install-exec-local install-html install-html-am \ + install-includeHEADERS install-info install-info-am \ + install-libLTLIBRARIES install-man \ + install-nobase_includeHEADERS install-pdf install-pdf-am \ + install-pkgconfigDATA install-ps install-ps-am install-strip \ + installcheck installcheck-am installdirs maintainer-clean \ + maintainer-clean-generic maintainer-clean-local mostlyclean \ + mostlyclean-compile mostlyclean-generic mostlyclean-libtool \ + pdf pdf-am ps ps-am recheck tags tags-am uninstall \ + uninstall-am uninstall-binPROGRAMS uninstall-dist_docDATA \ + uninstall-dist_exampleDATA uninstall-includeHEADERS \ + uninstall-libLTLIBRARIES uninstall-local \ + uninstall-nobase_includeHEADERS uninstall-pkgconfigDATA + + +#includes additional rules from aminclude.am +@INC_AMINCLUDE@ + +rpm-build: rpm/spec dist + @rm -f *.rpm + @rm -f ~/rpmbuild/RPMS/x86_64/$(PACKAGE)-$(VERSION)*.rpm + @rm -f ~/rpmbuild/SRPMS/$(PACKAGE)-$(VERSION)*.rpm + @mkdir -p ~/rpmbuild/BUILD/ + @mkdir -p ~/rpmbuild/RPMS/i386/ + @mkdir -p ~/rpmbuild/RPMS/i686/ + @mkdir -p ~/rpmbuild/RPMS/noarch/ + @mkdir -p ~/rpmbuild/RPMS/x86_64/ + @mkdir -p ~/rpmbuild/SOURCES/ + @mkdir -p ~/rpmbuild/SPECS/ + @mkdir -p ~/rpmbuild/SRPMS/ + @cp $(PACKAGE)-$(VERSION).tar.gz ~/rpmbuild/SOURCES/ + @rpmbuild -ba --clean rpm/spec + @cp ~/rpmbuild/RPMS/x86_64/$(PACKAGE)-$(VERSION)*.rpm . + @cp ~/rpmbuild/RPMS/x86_64/$(PACKAGE)-devel-$(VERSION)*.rpm . + @cp ~/rpmbuild/RPMS/x86_64/$(PACKAGE)-debuginfo-$(VERSION)*.rpm . + @cp ~/rpmbuild/SRPMS/$(PACKAGE)-$(VERSION)*.rpm . + +rpm-sign: rpm-build + @rpm --addsign *.rpm + @rpm --checksig *.rpm + +clean-rpm: + @rm -f *.tar.gz + @rm -f *.src.rpm + @rm -f *.rpm + +rpm: rpm-build + +release: rpm-sign + +auto-rpmbuild: + @auto-br-rpmbuild -ba rpm/spec +test: check +tests/unit.log: testsuite/testsuite.log + +maintainer-clean-local: + -rm Makefile.in + -rm aclocal.m4 + -rm build-aux/compile + -rm build-aux/config.guess + -rm build-aux/config.sub + -rm build-aux/depcomp + -rm build-aux/install-sh + -rm build-aux/ltmain.sh + -rm build-aux/missing + -rm cyassl-config + -rmdir build-aux + -rm configure + -rm config.log + -rm config.status + -rm config.in + -rm m4/libtool.m4 + -rm m4/ltoptions.m4 + -rm m4/ltsugar.m4 + -rm m4/ltversion.m4 + -rm m4/lt~obsolete.m4 + -rm support/cyassl.pc + find . -type f -name '*~' -exec rm -f '{}' \; + -rm -f @PACKAGE@-*.tar.gz + -rm -f @PACKAGE@-*.rpm + +# !!!! first line of rule has to start with a hard (real) tab, not spaces +egs: + $(MAKE) examples/client/client; \ + $(MAKE) examples/echoclient/echoclient;\ + $(MAKE) examples/server/server; \ + $(MAKE) examples/echoserver/echoserver; + +ctc: + $(MAKE) ctaocrypt/test/testctaocrypt; \ + $(MAKE) ctaocrypt/benchmark/benchmark; + +install-exec-local: install-generic-config + +install-generic-config: + $(mkinstalldirs) $(DESTDIR)$(bindir) + $(INSTALL_SCRIPT) @GENERIC_CONFIG@ $(DESTDIR)$(bindir) + +uninstall-local: + -rm -f $(DESTDIR)$(bindir)/@GENERIC_CONFIG@ + +merge-clean: + @find ./ | $(GREP) \.gcda | xargs rm -f + @find ./ | $(GREP) \.gcno | xargs rm -f + @find ./ | $(GREP) \.gz | xargs rm -f + @find ./ | $(GREP) \.orig | xargs rm -f + @find ./ | $(GREP) \.rej | xargs rm -f + @find ./ | $(GREP) \.rpm | xargs rm -f + @find ./ | $(GREP) \.THIS | xargs rm -f + @find ./ | $(GREP) \.OTHER | xargs rm -f + @find ./ | $(GREP) \.BASE | xargs rm -f + @find ./ | $(GREP) \~$$ | xargs rm -f + +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/NEWS b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/NEWS new file mode 100644 index 0000000..e69de29 diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/README b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/README new file mode 100644 index 0000000..e2da674 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/README @@ -0,0 +1,1044 @@ +*** Notes, Please read *** + +Note 1) +CyaSSL now needs all examples and tests to be run from the CyaSSL home +directory. This is because it finds certs and keys from ./certs/. Trying to +maintain the ability to run each program from its own directory, the testsuite +directory, the main directory (for make check/test), and for the various +different project layouts (with or without config) was becoming harder and +harder. Now to run testsuite just do: + +./testsuite/testsuite + +or + +make check (when using autoconf) + +On *nix or Windows the examples and testsuite will check to see if the current +directory is the source directory and if so, attempt to change to the CyaSSL +home directory. This should work in most setup cases, if not, just follow the +beginning of the note and specify the full path. + + +Note 2) +CyaSSL takes a different approach to certificate verification than OpenSSL does. +The default policy for the client is to verify the server, this means that if +you don't load CAs to verify the server you'll get a connect error, no signer +error to confirm failure (-188). If you want to mimic OpenSSL behavior of +having SSL_connect succeed even if verifying the server fails and reducing +security you can do this by calling: + +SSL_CTX_set_verify(ctx, SSL_VERIFY_NONE, 0); + +before calling SSL_new(); Though it's not recommended. + +*** end Notes *** + + +CyaSSL Release 3.1.0 (07/14/2014) + +Release 3.1.0 CyaSSL has bug fixes and new features including: + +- Fix for older versions of icc without 128-bit type +- Intel ASM syntax for AES-NI +- Updated NTRU support, keygen benchmark +- FIPS check for minimum required HMAC key length +- Small stack (--enable-smallstack) improvements for PKCS#7, ASN +- TLS extension support for DTLS +- Default I/O callbacks external to user +- Updated example client with bad clock test +- Ability to set optional ECC context info +- Ability to enable/disable DH separate from opensslextra +- Additional test key/cert buffers for CA and server +- Updated example certificates + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + +************ CyaSSL Release 3.0.2 (05/30/2014) + +Release 3.0.2 CyaSSL has bug fixes and new features including: + +- Added the following cipher suites: + * TLS_PSK_WITH_AES_128_GCM_SHA256 + * TLS_PSK_WITH_AES_256_GCM_SHA384 + * TLS_PSK_WITH_AES_256_CBC_SHA384 + * TLS_PSK_WITH_NULL_SHA384 + * TLS_DHE_PSK_WITH_AES_128_GCM_SHA256 + * TLS_DHE_PSK_WITH_AES_256_GCM_SHA384 + * TLS_DHE_PSK_WITH_AES_128_CBC_SHA256 + * TLS_DHE_PSK_WITH_AES_256_CBC_SHA384 + * TLS_DHE_PSK_WITH_NULL_SHA256 + * TLS_DHE_PSK_WITH_NULL_SHA384 + * TLS_DHE_PSK_WITH_AES_128_CCM + * TLS_DHE_PSK_WITH_AES_256_CCM +- Added AES-NI support for Microsoft Visual Studio builds. +- Changed small stack build to be disabled by default. +- Updated the Hash DRBG and provided a configure option to enable. + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + +************ CyaSSL Release 3.0.0 (04/29/2014) + +Release 3.0.0 CyaSSL has bug fixes and new features including: + +- FIPS release candidate +- X.509 improvements that address items reported by Suman Jana with security + researchers at UT Austin and UC Davis +- Small stack size improvements, --enable-smallstack. Offloads large local + variables to the heap. (Note this is not complete.) +- Updated AES-CCM-8 cipher suites to use approved suite numbers. + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + +************ CyaSSL Release 2.9.4 (04/09/2014) + +Release 2.9.4 CyaSSL has bug fixes and new features including: + +- Security fixes that address items reported by Ivan Fratric of the Google + Security Team +- X.509 Unknown critical extensions treated as errors, report by Suman Jana with + security researchers at UT Austin and UC Davis +- Sniffer fixes for corrupted packet length and Jumbo frames +- ARM thumb mode assembly fixes +- Xcode 5.1 support including new clang +- PIC32 MZ hardware support +- CyaSSL Object has enough room to read the Record Header now w/o allocs +- FIPS wrappers for AES, 3DES, SHA1, SHA256, SHA384, HMAC, and RSA. +- A sample I/O pool is demonstrated with --enable-iopool to overtake memory + handling and reduce memory fragmentation on I/O large sizes + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + +************ CyaSSL Release 2.9.0 (02/07/2014) + +Release 2.9.0 CyaSSL has bug fixes and new features including: +- Freescale Kinetis RNGB support +- Freescale Kinetis mmCAU support +- TLS Hello extensions + - ECC + - Secure Renegotiation (null) + - Truncated HMAC +- SCEP support + - PKCS #7 Enveloped data and signed data + - PKCS #10 Certificate Signing Request generation +- DTLS sliding window +- OCSP Improvements + - API change to integrate into Certificate Manager + - IPv4/IPv6 agnostic + - example client/server support for OCSP + - OCSP nonces are optional +- GMAC hashing +- Windows build additions +- Windows CYGWIN build fixes +- Updated test certificates +- Microchip MPLAB Harmony support +- Update autoconf scripts +- Additional X.509 inspection functions +- ECC encrypt/decrypt primitives +- ECC Certificate generation + +The Freescale Kinetis K53 RNGB documentation can be found in Chapter 33 of the +K53 Sub-Family Reference Manual: +http://cache.freescale.com/files/32bit/doc/ref_manual/K53P144M100SF2RM.pdf + +Freescale Kinetis K60 mmCAU (AES, DES, 3DES, MD5, SHA, SHA256) documentation +can be found in the "ColdFire/ColdFire+ CAU and Kinetis mmCAU Software Library +User Guide": +http://cache.freescale.com/files/32bit/doc/user_guide/CAUAPIUG.pdf + + +*****************CyaSSL Release 2.8.0 (8/30/2013) + +Release 2.8.0 CyaSSL has bug fixes and new features including: +- AES-GCM and AES-CCM use AES-NI +- NetX default IO callback handlers +- IPv6 fixes for DTLS Hello Cookies +- The ability to unload Certs/Keys after the handshake, CyaSSL_UnloadCertsKeys() +- SEP certificate extensions +- Callback getters for easier resource freeing +- External CYASSL_MAX_ERROR_SZ for correct error buffer sizing +- MacEncrypt and DecryptVerify Callbacks for User Atomic Record Layer Processing +- Public Key Callbacks for ECC and RSA +- Client now sends blank cert upon request if doesn't have one with TLS <= 1.2 + + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + +*****************CyaSSL Release 2.7.0 (6/17/2013) + +Release 2.7.0 CyaSSL has bug fixes and new features including: +- SNI support for client and server +- KEIL MDK-ARM projects +- Wildcard check to domain name match, and Subject altnames are checked too +- Better error messages for certificate verification errors +- Ability to discard session during handshake verify +- More consistent error returns across all APIs +- Ability to unload CAs at the CTX or CertManager level +- Authority subject id support for Certificate matching +- Persistent session cache functionality +- Persistent CA cache functionality +- Client session table lookups to push serverID table to library level +- Camellia support to sniffer +- User controllable settings for DTLS timeout values +- Sniffer fixes for caching long lived sessions +- DTLS reliability enhancements for the handshake +- Better ThreadX support + +When compiling with Mingw, libtool may give the following warning due to +path conversion errors: + +libtool: link: Could not determine host file name corresponding to ** +libtool: link: Continuing, but uninstalled executables may not work. + +If so, examples and testsuite will have problems when run, showing an +error while loading shared libraries. To resolve, please run "make install". + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + +************** CyaSSL Release 2.6.0 (04/15/2013) + +Release 2.6.0 CyaSSL has bug fixes and new features including: +- DTLS 1.2 support including AEAD ciphers +- SHA-3 finalist Blake2 support, it's fast and uses little resources +- SHA-384 cipher suites including ECC ones +- HMAC now supports SHA-512 +- Track memory use for example client/server with -t option +- Better IPv6 examples with --enable-ipv6, before if ipv6 examples/tests were + turned on, localhost only was used. Now link-local (with scope ids) and ipv6 + hosts can be used as well. +- Xcode v4.6 project for iOS v6.1 update +- settings.h is now checked in all *.c files for true one file setting detection +- Better alignment at SSL layer for hardware crypto alignment needs + * Note, SSL itself isn't friendly to alignment with 5 byte TLS headers and + 13 bytes DTLS headers, but every effort is now made to align with the + CYASSL_GENERAL_ALIGNMENT flag which sets desired alignment requirement +- NO_64BIT flag to turn off 64bit data type accumulators in public key code + * Note, some systems are faster with 32bit accumulators +- --enable-stacksize for example client/server stack use + * Note, modern desktop Operating Systems may add bytes to each stack frame +- Updated compression/decompression with direct crypto access +- All ./configure options are now lowercase only for consistency +- ./configure builds default to fastmath option + * Note, if on ia32 and building in shared mode this may produce a problem + with a missing register being available because of PIC, there are at least + 5 solutions to this: + 1) --disable-fastmath , don't use fastmath + 2) --disable-shared, don't build a shared library + 3) C_EXTRA_FLAGS=-DTFM_NO_ASM , turn off assembly use + 4) use clang, it just seems to work + 5) play around with no PIC options to force all registers being open +- Many new ./configure switches for option enable/disable for example + * rsa + * dh + * dsa + * md5 + * sha + * arc4 + * null (allow NULL ciphers) + * oldtls (only use TLS 1.2) + * asn (no certs or public keys allowed) +- ./configure generates cyassl/options.h which allows a header the user can + include in their app to make sure the same options are set at the app and + CyaSSL level. +- autoconf no longer needs serial-tests which lowers version requirements of + automake to 1.11 and autoconf to 2.63 + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + + +************** CyaSSL Release 2.5.0 (02/04/2013) + +Release 2.5.0 CyaSSL has bug fixes and new features including: +- Fix for TLS CBC padding timing attack identified by Nadhem Alfardan and + Kenny Paterson: http://www.isg.rhul.ac.uk/tls/ +- Microchip PIC32 (MIPS16, MIPS32) support +- Microchip MPLAB X example projects for PIC32 Ethernet Starter Kit +- Updated CTaoCrypt benchmark app for embedded systems +- 1024-bit test certs/keys and cert/key buffers +- AES-CCM-8 crypto and cipher suites +- Camellia crypto and cipher suites +- Bumped minimum autoconf version to 2.65, automake version to 1.12 +- Addition of OCSP callbacks +- STM32F2 support with hardware crypto and RNG +- Cavium NITROX support + +CTaoCrypt now has support for the Microchip PIC32 and has been tested with +the Microchip PIC32 Ethernet Starter Kit, the XC32 compiler and +MPLAB X IDE in both MIPS16 and MIPS32 instruction set modes. See the README +located under the /mplabx directory for more details. + +To add Cavium NITROX support do: + +./configure --with-cavium=/home/user/cavium/software + +pointing to your licensed cavium/software directory. Since Cavium doesn't +build a library we pull in the cavium_common.o file which gives a libtool +warning about the portability of this. Also, if you're using the github source +tree you'll need to remove the -Wredundant-decls warning from the generated +Makefile because the cavium headers don't conform to this warning. Currently +CyaSSL supports Cavium RNG, AES, 3DES, RC4, HMAC, and RSA directly at the crypto +layer. Support at the SSL level is partial and currently just does AES, 3DES, +and RC4. RSA and HMAC are slower until the Cavium calls can be utilized in non +blocking mode. The example client turns on cavium support as does the crypto +test and benchmark. Please see the HAVE_CAVIUM define. + +CyaSSL is able to use the STM32F2 hardware-based cryptography and random number +generator through the STM32F2 Standard Peripheral Library. For necessary +defines, see the CYASSL_STM32F2 define in settings.h. Documentation for the +STM32F2 Standard Peripheral Library can be found in the following document: +http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/USER_MANUAL/DM00023896.pdf + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + + +*************** CyaSSL Release 2.4.6 (12/20/2012) + +Release 2.4.6 CyaSSL has bug fixes and a few new features including: +- ECC into main version +- Lean PSK build (reduced code size, RAM usage, and stack usage) +- FreeBSD CRL monitor support +- CyaSSL_peek() +- CyaSSL_send() and CyaSSL_recv() for I/O flag setting +- CodeWarrior Support +- MQX Support +- Freescale Kinetis support including Hardware RNG +- autoconf builds use jobserver +- cyassl-config +- Sniffer memory reductions + +Thanks to Brian Aker for the improved autoconf system, make rpm, cyassl-config, +warning system, and general good ideas for improving CyaSSL! + +The Freescale Kinetis K70 RNGA documentation can be found in Chapter 37 of the +K70 Sub-Family Reference Manual: +http://cache.freescale.com/files/microcontrollers/doc/ref_manual/K70P256M150SF3RM.pdf + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + +*************** CyaSSL Release 2.4.0 (10/10/2012) + +Release 2.4.0 CyaSSL has bug fixes and a few new features including: +- DTLS reliability +- Reduced memory usage after handshake +- Updated build process + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + + +*************** CyaSSL Release 2.3.0 (8/10/2012) + +Release 2.3.0 CyaSSL has bug fixes and a few new features including: +- AES-GCM crypto and cipher suites +- make test cipher suite checks +- Subject AltName processing +- Command line support for client/server examples +- Sniffer SessionTicket support +- SHA-384 cipher suites +- Verify cipher suite validity when user overrides +- CRL dir monitoring +- DTLS Cookie support, reliability coming soon + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + + +***************CyaSSL Release 2.2.0 (5/18/2012) + +Release 2.2.0 CyaSSL has bug fixes and a few new features including: +- Initial CRL support (--enable-crl) +- Initial OCSP support (--enable-ocsp) +- Add static ECDH suites +- SHA-384 support +- ECC client certificate support +- Add medium session cache size (1055 sessions) +- Updated unit tests +- Protection against mutex reinitialization + + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + + +***************CyaSSL Release 2.0.8 (2/24/2012) + +Release 2.0.8 CyaSSL has bug fixes and a few new features including: +- A fix for malicious certificates pointed out by Remi Gacogne (thanks) + resulting in NULL pointer use. +- Respond to renegotiation attempt with no_renegoatation alert +- Add basic path support for load_verify_locations() +- Add set Temp EC-DHE key size +- Extra checks on rsa test when porting into + + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + + +************* CyaSSL Release 2.0.6 (1/27/2012) + +Release 2.0.6 CyaSSL has bug fixes and a few new features including: +- Fixes for CA basis constraint check +- CTX reference counting +- Initial unit test additions +- Lean and Mean Windows fix +- ECC benchmarking +- SSMTP build support +- Ability to group handshake messages with set_group_messages(ctx/ssl) +- CA cache addition callback +- Export Base64_Encode for general use + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + + +************* CyaSSL Release 2.0.2 (12/05/2011) + +Release 2.0.2 CyaSSL has bug fixes and a few new features including: +- CTaoCrypt Runtime library detection settings when directly using the crypto + library +- Default certificate generation now uses SHAwRSA and adds SHA256wRSA generation +- All test certificates now use 2048bit and SHA-1 for better modern browser + support +- Direct AES block access and AES-CTR (counter) mode +- Microchip pic32 support + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + + +************* CyaSSL Release 2.0.0rc3 (9/28/2011) + +Release 2.0.0rc3 for CyaSSL has bug fixes and a few new features including: +- updated autoconf support +- better make install and uninstall (uses system directories) +- make test / make check +- CyaSSL headers now in +- CTaocrypt headers now in +- OpenSSL compatibility headers now in +- examples and tests all run from home directory so can use certs in ./certs + (see note 1) + +So previous applications that used the OpenSSL compatibility header + now need to include instead, no other +changes are required. + +Special Thanks to Brian Aker for his autoconf, install, and header patches. + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + +************CyaSSL Release 2.0.0rc2 (6/6/2011) + +Release 2.0.0rc2 for CyaSSL has bug fixes and a few new features including: +- bug fixes (Alerts, DTLS with DHE) +- FreeRTOS support +- lwIP support +- Wshadow warnings removed +- asn public header +- CTaoCrypt public headers now all have ctc_ prefix (the manual is still being + updated to reflect this change) +- and more. + +This is the 2nd and perhaps final release candidate for version 2. +Please send any comments or questions to support@yassl.com. + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + +***********CyaSSL Release 2.0.0rc1 (5/2/2011) + +Release 2.0.0rc1 for CyaSSL has many new features including: +- bug fixes +- SHA-256 cipher suites +- Root Certificate Verification (instead of needing all certs in the chain) +- PKCS #8 private key encryption (supports PKCS #5 v1-v2 and PKCS #12) +- Serial number retrieval for x509 +- PBKDF2 and PKCS #12 PBKDF +- UID parsing for x509 +- SHA-256 certificate signatures +- Client and server can send chains (SSL_CTX_use_certificate_chain_file) +- CA loading can now parse multiple certificates per file +- Dynamic memory runtime hooks +- Runtime hooks for logging +- EDH on server side +- More informative error codes +- More informative logging messages +- Version downgrade more robust (use SSL_v23*) +- Shared build only by default through ./configure +- Compiler visibility is now used, internal functions not polluting namespace +- Single Makefile, no recursion, for faster and simpler building +- Turn on all warnings possible build option, warning fixes +- and more. + +Because of all the new features and the multiple OS, compiler, feature-set +options that CyaSSL allows, there may be some configuration fixes needed. +Please send any comments or questions to support@yassl.com. + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + +****************** CyaSSL Release 1.9.0 (3/2/2011) + +Release 1.9.0 for CyaSSL adds bug fixes, improved TLSv1.2 through testing and +better hash/sig algo ids, --enable-webServer for the yaSSL embedded web server, +improper AES key setup detection, user cert verify callback improvements, and +more. + +The CyaSSL manual offering is included in the doc/ directory. For build +instructions and comments about the new features please check the manual. + +Please send any comments or questions to support@yassl.com. + +****************** CyaSSL Release 1.8.0 (12/23/2010) + +Release 1.8.0 for CyaSSL adds bug fixes, x509 v3 CA signed certificate +generation, a C standard library abstraction layer, lower memory use, increased +portability through the os_settings.h file, and the ability to use NTRU cipher +suites when used in conjunction with an NTRU license and library. + +The initial CyaSSL manual offering is included in the doc/ directory. For +build instructions and comments about the new features please check the manual. + +Please send any comments or questions to support@yassl.com. + +Happy Holidays. + + +********************* CyaSSL Release 1.6.5 (9/9/2010) + +Release 1.6.5 for CyaSSL adds bug fixes and x509 v3 self signed certificate +generation. + +For general build instructions see doc/Building_CyaSSL.pdf. + +To enable certificate generation support add this option to ./configure +./configure --enable-certgen + +An example is included in ctaocrypt/test/test.c and documentation is provided +in doc/CyaSSL_Extensions_Reference.pdf item 11. + +********************** CyaSSL Release 1.6.0 (8/27/2010) + +Release 1.6.0 for CyaSSL adds bug fixes, RIPEMD-160, SHA-512, and RSA key +generation. + +For general build instructions see doc/Building_CyaSSL.pdf. + +To add RIPEMD-160 support add this option to ./configure +./configure --enable-ripemd + +To add SHA-512 support add this option to ./configure +./configure --enable-sha512 + +To add RSA key generation support add this option to ./configure +./configure --enable-keygen + +Please see ctaocrypt/test/test.c for examples and usage. + +For Windows, RIPEMD-160 and SHA-512 are enabled by default but key generation is +off by default. To turn key generation on add the define CYASSL_KEY_GEN to +CyaSSL. + + +************* CyaSSL Release 1.5.6 (7/28/2010) + +Release 1.5.6 for CyaSSL adds bug fixes, compatibility for our JSSE provider, +and a fix for GCC builds on some systems. + +For general build instructions see doc/Building_CyaSSL.pdf. + +To add AES-NI support add this option to ./configure +./configure --enable-aesni + +You'll need GCC 4.4.3 or later to make use of the assembly. + +************** CyaSSL Release 1.5.4 (7/7/2010) + +Release 1.5.4 for CyaSSL adds bug fixes, support for AES-NI, SHA1 speed +improvements from loop unrolling, and support for the Mongoose Web Server. + +For general build instructions see doc/Building_CyaSSL.pdf. + +To add AES-NI support add this option to ./configure +./configure --enable-aesni + +You'll need GCC 4.4.3 or later to make use of the assembly. + +*************** CyaSSL Release 1.5.0 (5/11/2010) + +Release 1.5.0 for CyaSSL adds bug fixes, GoAhead WebServer support, sniffer +support, and initial swig interface support. + +For general build instructions see doc/Building_CyaSSL.pdf. + +To add support for GoAhead WebServer either --enable-opensslExtra or if you +don't want all the features of opensslExtra you can just define GOAHEAD_WS +instead. GOAHEAD_WS can be added to ./configure with CFLAGS=-DGOAHEAD_WS or +you can define it yourself. + +To look at the sniffer support please see the sniffertest app in +sslSniffer/sslSnifferTest. Build with --enable-sniffer on *nix or use the +vcproj files on windows. You'll need to have pcap installed on *nix and +WinPcap on windows. + +A swig interface file is now located in the swig directory for using Python, +Java, Perl, and others with CyaSSL. This is initial support and experimental, +please send questions or comments to support@yassl.com. + +When doing load testing with CyaSSL, on the echoserver example say, the client +machine may run out of tcp ephemeral ports, they will end up in the TIME_WAIT +queue, and can't be reused by default. There are generally two ways to fix +this. 1) Reduce the length sockets remain on the TIME_WAIT queue or 2) Allow +items on the TIME_WAIT queue to be reused. + + +To reduce the TIME_WAIT length in OS X to 3 seconds (3000 milliseconds) + +sudo sysctl -w net.inet.tcp.msl=3000 + +In Linux + +sudo sysctl -w net.ipv4.tcp_tw_reuse=1 + +allows reuse of sockets in TIME_WAIT + +sudo sysctl -w net.ipv4.tcp_tw_recycle=1 + +works but seems to remove sockets from TIME_WAIT entirely? + +sudo sysctl -w net.ipv4.tcp_fin_timeout=1 + +doen't control TIME_WAIT, it controls FIN_WAIT(2) contrary to some posts + + +******************** CyaSSL Release 1.4.0 (2/18/2010) + +Release 1.3.0 for CyaSSL adds bug fixes, better multi TLS/SSL version support +through SSLv23_server_method(), and improved documentation in the doc/ folder. + +For general build instructions doc/Building_CyaSSL.pdf. + +******************** CyaSSL Release 1.3.0 (1/21/2010) + +Release 1.3.0 for CyaSSL adds bug fixes, a potential security problem fix, +better porting support, removal of assert()s, and a complete THREADX port. + +For general build instructions see rc1 below. + +******************** CyaSSL Release 1.2.0 (11/2/2009) + +Release 1.2.0 for CyaSSL adds bug fixes and session negotiation if first use is +read or write. + +For general build instructions see rc1 below. + +******************** CyaSSL Release 1.1.0 (9/2/2009) + +Release 1.1.0 for CyaSSL adds bug fixes, a check against malicious session +cache use, support for lighttpd, and TLS 1.2. + +To get TLS 1.2 support please use the client and server functions: + +SSL_METHOD *TLSv1_2_server_method(void); +SSL_METHOD *TLSv1_2_client_method(void); + +CyaSSL was tested against lighttpd 1.4.23. To build CyaSSL for use with +lighttpd use the following commands from the CyaSSL install dir : + +./configure --disable-shared --enable-opensslExtra --enable-fastmath --without-zlib + +make +make openssl-links + +Then to build lighttpd with CyaSSL use the following commands from the +lighttpd install dir: + +./configure --with-openssl --with-openssl-includes=/include --with-openssl-libs=/lib LDFLAGS=-lm + +make + +On some systems you may get a linker error about a duplicate symbol for +MD5_Init or other MD5 calls. This seems to be caused by the lighttpd src file +md5.c, which defines MD5_Init(), and is included in liblightcomp_la-md5.o. +When liblightcomp is linked with the SSL_LIBs the linker may complain about +the duplicate symbol. This can be fixed by editing the lighttpd src file md5.c +and adding this line to the beginning of the file: + +#if 0 + +and this line to the end of the file + +#endif + +Then from the lighttpd src dir do a: + +make clean +make + + +If you get link errors about undefined symbols more than likely the actual +OpenSSL libraries are found by the linker before the CyaSSL openssl-links that +point to the CyaSSL library, causing the linker confusion. This can be fixed +by editing the Makefile in the lighttpd src directory and changing the line: + +SSL_LIB = -lssl -lcrypto + +to + +SSL_LIB = -lcyassl + +Then from the lighttpd src dir do a: + +make clean +make + +This should remove any confusion the linker may be having with missing symbols. + +For any questions or concerns please contact support@yassl.com . + +For general build instructions see rc1 below. + +******************CyaSSL Release 1.0.6 (8/03/2009) + +Release 1.0.6 for CyaSSL adds bug fixes, an improved session cache, and faster +math with a huge code option. + +The session cache now defaults to a client mode, also good for embedded servers. +For servers not under heavy load (less than 200 new sessions per minute), define +BIG_SESSION_CACHE. If the server will be under heavy load, define +HUGE_SESSION_CACHE. + +There is now a fasthugemath option for configure. This enables fastmath plus +even faster math by greatly increasing the code size of the math library. Use +the benchmark utility to compare public key operations. + + +For general build instructions see rc1 below. + +******************CyaSSL Release 1.0.3 (5/10/2009) + +Release 1.0.3 for CyaSSL adds bug fixes and add increased support for OpenSSL +compatibility when building other applications. + +Release 1.0.3 includes an alpha release of DTLS for both client and servers. +This is only for testing purposes at this time. Rebroadcast and reordering +aren't fully implemented at this time but will be for the next release. + +For general build instructions see rc1 below. + +******************CyaSSL Release 1.0.2 (4/3/2009) + +Release 1.0.2 for CyaSSL adds bug fixes for a couple I/O issues. Some systems +will send a SIGPIPE on socket recv() at any time and this should be handled by +the application by turning off SIGPIPE through setsockopt() or returning from +the handler. + +Release 1.0.2 includes an alpha release of DTLS for both client and servers. +This is only for testing purposes at this time. Rebroadcast and reordering +aren't fully implemented at this time but will be for the next release. + +For general build instructions see rc1 below. + +*****************CyaSSL Release Candidiate 3 rc3-1.0.0 (2/25/2009) + + +Release Candidate 3 for CyaSSL 1.0.0 adds bug fixes and adds a project file for +iPhone development with Xcode. cyassl-iphone.xcodeproj is located in the root +directory. This release also includes a fix for supporting other +implementations that bundle multiple messages at the record layer, this was +lost when cyassl i/o was re-implemented but is now fixed. + +For general build instructions see rc1 below. + +*****************CyaSSL Release Candidiate 2 rc2-1.0.0 (1/21/2009) + + +Release Candidate 2 for CyaSSL 1.0.0 adds bug fixes and adds two new stream +ciphers along with their respective cipher suites. CyaSSL adds support for +HC-128 and RABBIT stream ciphers. The new suites are: + +TLS_RSA_WITH_HC_128_SHA +TLS_RSA_WITH_RABBIT_SHA + +And the corresponding cipher names are + +HC128-SHA +RABBIT-SHA + +CyaSSL also adds support for building with devkitPro for PPC by changing the +library proper to use libogc. The examples haven't been changed yet but if +there's interest they can be. Here's an example ./configure to build CyaSSL +for devkitPro: + +./configure --disable-shared CC=/pathTo/devkitpro/devkitPPC/bin/powerpc-gekko-gcc --host=ppc --without-zlib --enable-singleThreaded RANLIB=/pathTo/devkitpro/devkitPPC/bin/powerpc-gekko-ranlib CFLAGS="-DDEVKITPRO -DGEKKO" + +For linking purposes you'll need + +LDFLAGS="-g -mrvl -mcpu=750 -meabi -mhard-float -Wl,-Map,$(notdir $@).map" + +For general build instructions see rc1 below. + + +********************CyaSSL Release Candidiate 1 rc1-1.0.0 (12/17/2008) + + +Release Candidate 1 for CyaSSL 1.0.0 contains major internal changes. Several +areas have optimization improvements, less dynamic memory use, and the I/O +strategy has been refactored to allow alternate I/O handling or Library use. +Many thanks to Thierry Fournier for providing these ideas and most of the work. + +Because of these changes, this release is only a candidate since some problems +are probably inevitable on some platform with some I/O use. Please report any +problems and we'll try to resolve them as soon as possible. You can contact us +at support@yassl.com or todd@yassl.com. + +Using TomsFastMath by passing --enable-fastmath to ./configure now uses assembly +on some platforms. This is new so please report any problems as every compiler, +mode, OS combination hasn't been tested. On ia32 all of the registers need to +be available so be sure to pass these options to CFLAGS: + +CFLAGS="-O3 -fomit-frame-pointer" + +OS X will also need -mdynamic-no-pic added to CFLAGS + +Also if you're building in shared mode for ia32 you'll need to pass options to +LDFLAGS as well on OS X: + +LDFLAGS=-Wl,-read_only_relocs,warning + +This gives warnings for some symbols but seems to work. + + +--To build on Linux, Solaris, *BSD, Mac OS X, or Cygwin: + + ./configure + make + + from the ./testsuite/ directory run ./testsuite + +to make a debug build: + + ./configure --enable-debug --disable-shared + make + + + +--To build on Win32 + +Choose (Re)Build All from the project workspace + +Run the testsuite program + + + + + +*************************CyaSSL version 0.9.9 (7/25/2008) + +This release of CyaSSL adds bug fixes, Pre-Shared Keys, over-rideable memory +handling, and optionally TomsFastMath. Thanks to Moisés Guimarães for the +work on TomsFastMath. + +To optionally use TomsFastMath pass --enable-fastmath to ./configure +Or define USE_FAST_MATH in each project from CyaSSL for MSVC. + +Please use the benchmark routine before and after to see the performance +difference, on some platforms the gains will be little but RSA encryption +always seems to be faster. On x86-64 machines with GCC the normal math library +may outperform the fast one when using CFLAGS=-m64 because TomsFastMath can't +yet use -m64 because of GCCs inability to do 128bit division. + + **** UPDATE GCC 4.2.1 can now do 128bit division *** + +See notes below (0.2.0) for complete build instructions. + + +****************CyaSSL version 0.9.8 (5/7/2008) + +This release of CyaSSL adds bug fixes, client side Diffie-Hellman, and better +socket handling. + +See notes below (0.2.0) for complete build instructions. + + +****************CyaSSL version 0.9.6 (1/31/2008) + +This release of CyaSSL adds bug fixes, increased session management, and a fix +for gnutls. + +See notes below (0.2.0) for complete build instructions. + + +****************CyaSSL version 0.9.0 (10/15/2007) + +This release of CyaSSL adds bug fixes, MSVC 2005 support, GCC 4.2 support, +IPV6 support and test, and new test certificates. + +See notes below (0.2.0) for complete build instructions. + + +****************CyaSSL version 0.8.0 (1/10/2007) + +This release of CyaSSL adds increased socket support, for non-blocking writes, +connects, and interrupted system calls. + +See notes below (0.2.0) for complete build instructions. + + +****************CyaSSL version 0.6.3 (10/30/2006) + +This release of CyaSSL adds debug logging to stderr to aid in the debugging of +CyaSSL on systems that may not provide the best support. + +If CyaSSL is built with debugging support then you need to call +CyaSSL_Debugging_ON() to turn logging on. + +On Unix use ./configure --enable-debug + +On Windows define DEBUG_CYASSL when building CyaSSL + + +To turn logging back off call CyaSSL_Debugging_OFF() + +See notes below (0.2.0) for complete build instructions. + + +*****************CyaSSL version 0.6.2 (10/29/2006) + +This release of CyaSSL adds TLS 1.1. + +Note that CyaSSL has certificate verification on by default, unlike OpenSSL. +To emulate OpenSSL behavior, you must call SSL_CTX_set_verify() with +SSL_VERIFY_NONE. In order to have full security you should never do this, +provide CyaSSL with the proper certificates to eliminate impostors and call +CyaSSL_check_domain_name() to prevent man in the middle attacks. + +See notes below (0.2.0) for build instructions. + +*****************CyaSSL version 0.6.0 (10/25/2006) + +This release of CyaSSL adds more SSL functions, better autoconf, nonblocking +I/O for accept, connect, and read. There is now an --enable-small configure +option that turns off TLS, AES, DES3, HMAC, and ERROR_STRINGS, see configure.in +for the defines. Note that TLS requires HMAC and AES requires TLS. + +See notes below (0.2.0) for build instructions. + + +*****************CyaSSL version 0.5.5 (09/27/2006) + +This mini release of CyaSSL adds better input processing through buffered input +and big message support. Added SSL_pending() and some sanity checks on user +settings. + +See notes below (0.2.0) for build instructions. + + +*****************CyaSSL version 0.5.0 (03/27/2006) + +This release of CyaSSL adds AES support and minor bug fixes. + +See notes below (0.2.0) for build instructions. + + +*****************CyaSSL version 0.4.0 (03/15/2006) + +This release of CyaSSL adds TLSv1 client/server support and libtool. + +See notes below for build instructions. + + +*****************CyaSSL version 0.3.0 (02/26/2006) + +This release of CyaSSL adds SSLv3 server support and session resumption. + +See notes below for build instructions. + + +*****************CyaSSL version 0.2.0 (02/19/2006) + + +This is the first release of CyaSSL and its crypt brother, CTaoCrypt. CyaSSL +is written in ANSI C with the idea of a small code size, footprint, and memory +usage in mind. CTaoCrypt can be as small as 32K, and the current client +version of CyaSSL can be as small as 12K. + + +The first release of CTaoCrypt supports MD5, SHA-1, 3DES, ARC4, Big Integer +Support, RSA, ASN parsing, and basic x509 (en/de)coding. + +The first release of CyaSSL supports normal client RSA mode SSLv3 connections +with support for SHA-1 and MD5 digests. Ciphers include 3DES and RC4. + + +--To build on Linux, Solaris, *BSD, Mac OS X, or Cygwin: + + ./configure + make + + from the ./testsuite/ directory run ./testsuite + +to make a debug build: + + ./configure --enable-debug --disable-shared + make + + + +--To build on Win32 + +Choose (Re)Build All from the project workspace + +Run the testsuite program + + + +*** The next release of CyaSSL will support a server and more OpenSSL +compatibility functions. + + +Please send questions or comments to todd@yassl.com + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/README.md b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/README.md new file mode 100644 index 0000000..a490ac2 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/README.md @@ -0,0 +1,1194 @@ +# Notes - Please read + +## Note 1 +``` +wolfSSL now needs all examples and tests to be run from the wolfSSL home +directory. This is because it finds certs and keys from ./certs/. Trying to +maintain the ability to run each program from its own directory, the testsuite +directory, the main directory (for make check/test), and for the various +different project layouts (with or without config) was becoming harder and +harder. Now to run testsuite just do: + +./testsuite/testsuite + +or + +make check (when using autoconf) + +On *nix or Windows the examples and testsuite will check to see if the current +directory is the source directory and if so, attempt to change to the wolfSSL +home directory. This should work in most setup cases, if not, just follow the +beginning of the note and specify the full path. +``` + +## Note 2 +``` +wolfSSL takes a different approach to certificate verification than OpenSSL +does. The default policy for the client is to verify the server, this means +that if you don't load CAs to verify the server you'll get a connect error, +no signer error to confirm failure (-188). If you want to mimic OpenSSL +behavior of having SSL_connect succeed even if verifying the server fails and +reducing security you can do this by calling: + +wolfSSL_CTX_set_verify(ctx, SSL_VERIFY_NONE, 0); + +before calling wolfSSL_new(); Though it's not recommended. +``` + +- GNU Binutils 2.24 ld has problems with some debug builds, to fix an ld error + add -fdebug-types-section to C_EXTRA_FLAGS + +#wolfSSL (Formerly CyaSSL) Release 3.4.8 (04/06/2015) + +##Release 3.4.8 of wolfSSL has bug fixes and new features including: + +- FIPS version submitted for iOS. +- Max Strength build that only allows TLSv1.2, AEAD ciphers, and PFS. +- Improvements to usage of time code. +- Improvements to VS solution files. + +See INSTALL file for build instructions. +More info can be found on-line at //http://wolfssl.com/yaSSL/Docs.html + + +#wolfSSL (Formerly CyaSSL) Release 3.4.6 (03/30/2015) + +##Release 3.4.6 of wolfSSL has bug fixes and new features including: + +- Intel Assembly Speedups using instructions rdrand, rdseed, aesni, avx1/2, + rorx, mulx, adox, adcx . They can be enabled with --enable-intelasm. + These speedup the use of RNG, SHA2, and public key algorithms. +- Ed25519 support at the crypto level. Turn on with --enable-ed25519. Examples + in wolcrypt/test/test.c ed25519_test(). +- Post Handshake Memory reductions. wolfSSL can now hold less than 1,000 bytes + of memory per secure connection including cipher state. +- wolfSSL API and wolfCrypt API fixes, you can still include the cyassl and + ctaocrypt headers which will enable the compatibility APIs for the + foreseeable future +- INSTALL file to help direct users to build instructions for their environment +- For ECC users with the normal math library a fix that prevents a crash when + verify signature fails. Users of 3.4.0 with ECC and the normal math library + must update +- RC4 is now disabled by default in autoconf mode +- AES-GCM and ChaCha20/Poly1305 are now enabled by default to make AEAD ciphers + available without a switch +- External ChaCha-Poly AEAD API, thanks to Andrew Burks for the contribution +- DHE-PSK cipher suites can now be built without ASN or Cert support +- Fix some NO MD5 build issues with optional features +- Freescale CodeWarrior project updates +- ECC curves can be individually turned on/off at build time. +- Sniffer handles Cert Status message and other minor fixes +- SetMinVersion() at the wolfSSL Context level instead of just SSL session level + to allow minimum protocol version allowed at runtime +- RNG failure resource cleanup fix + +- No high level security fixes that requires an update though we always + recommend updating to the latest (except note 6 use case of ecc/normal math) + +See INSTALL file for build instructions. +More info can be found on-line at //http://wolfssl.com/yaSSL/Docs.html + + +#wolfSSL (Formerly CyaSSL) Release 3.4.0 (02/23/2015) + +## Release 3.4.0 wolfSSL has bug fixes and new features including: + +- wolfSSL API and wolfCrypt API, you can still include the cyassl and ctaocrypt + headers which will enable the compatibility APIs for the foreseeable future +- Example use of the wolfCrypt API can be found in wolfcrypt/test/test.c +- Example use of the wolfSSL API can be found in examples/client/client.c +- Curve25519 now supported at the wolfCrypt level, wolfSSL layer coming soon +- Improvements in the build configuration under AIX +- Microchip Pic32 MZ updates +- TIRTOS updates +- PowerPC updates +- Xcode project update +- Bidirectional shutdown examples in client/server with -w (wait for full + shutdown) option +- Cycle counts on benchmarks for x86_64, more coming soon +- ALT_ECC_SIZE for reducing ecc heap use with fastmath when also using large RSA + keys +- Various compile warnings +- Scan-build warning fixes +- Changed a memcpy to memmove in the sniffer (if using sniffer please update) +- No high level security fixes that requires an update though we always + recommend updating to the latest + + +# CyaSSL Release 3.3.0 (12/05/2014) + +- Countermeasuers for Handshake message duplicates, CHANGE CIPHER without + FINISHED, and fast forward attempts. Thanks to Karthikeyan Bhargavan from + the Prosecco team at INRIA Paris-Rocquencourt for the report. +- FIPS version submitted +- Removes SSLv2 Client Hello processing, can be enabled with OLD_HELLO_ALLOWED +- User can set mimimum downgrade version with CyaSSL_SetMinVersion() +- Small stack improvements at TLS/SSL layer +- TLS Master Secret generation and Key Expansion are now exposed +- Adds client side Secure Renegotiation, * not recommended * +- Client side session ticket support, not fully tested with Secure Renegotiation +- Allows up to 4096bit DHE at TLS Key Exchange layer +- Handles non standard SessionID sizes in Hello Messages +- PicoTCP Support +- Sniffer now supports SNI Virtual Hosts +- Sniffer now handles non HTTPS protocols using STARTTLS +- Sniffer can now parse records with multiple messages +- TI-RTOS updates +- Fix for ColdFire optimized fp_digit read only in explicit 32bit case +- ADH Cipher Suite ADH-AES128-SHA for EAP-FAST + +The CyaSSL manual is available at: +http://www.wolfssl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + +# CyaSSL Release 3.2.0 (09/10/2014) + +#### Release 3.2.0 CyaSSL has bug fixes and new features including: + +- ChaCha20 and Poly1305 crypto and suites +- Small stack improvements for OCSP, CRL, TLS, DTLS +- NTRU Encrypt and Decrypt benchmarks +- Updated Visual Studio project files +- Updated Keil MDK5 project files +- Fix for DTLS sequence numbers with GCM/CCM +- Updated HashDRBG with more secure struct declaration +- TI-RTOS support and example Code Composer Studio project files +- Ability to get enabled cipher suites, CyaSSL_get_ciphers() +- AES-GCM/CCM/Direct support for Freescale mmCAU and CAU +- Sniffer improvement checking for decrypt key setup +- Support for raw ECC key import +- Ability to convert ecc_key to DER, EccKeyToDer() +- Security fix for RSA Padding check vulnerability reported by Intel Security + Advanced Threat Research team + +The CyaSSL manual is available at: +http://www.wolfssl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + +# CyaSSL Release 3.1.0 (07/14/2014) + +#### Release 3.1.0 CyaSSL has bug fixes and new features including: + +- Fix for older versions of icc without 128-bit type +- Intel ASM syntax for AES-NI +- Updated NTRU support, keygen benchmark +- FIPS check for minimum required HMAC key length +- Small stack (--enable-smallstack) improvements for PKCS#7, ASN +- TLS extension support for DTLS +- Default I/O callbacks external to user +- Updated example client with bad clock test +- Ability to set optional ECC context info +- Ability to enable/disable DH separate from opensslextra +- Additional test key/cert buffers for CA and server +- Updated example certificates + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + +# CyaSSL Release 3.0.2 (05/30/2014) + +#### Release 3.0.2 CyaSSL has bug fixes and new features including: + +- Added the following cipher suites: + * TLS_PSK_WITH_AES_128_GCM_SHA256 + * TLS_PSK_WITH_AES_256_GCM_SHA384 + * TLS_PSK_WITH_AES_256_CBC_SHA384 + * TLS_PSK_WITH_NULL_SHA384 + * TLS_DHE_PSK_WITH_AES_128_GCM_SHA256 + * TLS_DHE_PSK_WITH_AES_256_GCM_SHA384 + * TLS_DHE_PSK_WITH_AES_128_CBC_SHA256 + * TLS_DHE_PSK_WITH_AES_256_CBC_SHA384 + * TLS_DHE_PSK_WITH_NULL_SHA256 + * TLS_DHE_PSK_WITH_NULL_SHA384 + * TLS_DHE_PSK_WITH_AES_128_CCM + * TLS_DHE_PSK_WITH_AES_256_CCM +- Added AES-NI support for Microsoft Visual Studio builds. +- Changed small stack build to be disabled by default. +- Updated the Hash DRBG and provided a configure option to enable. + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + +# CyaSSL Release 3.0.0 (04/29/2014) + +#### Release 3.0.0 CyaSSL has bug fixes and new features including: + +- FIPS release candidate +- X.509 improvements that address items reported by Suman Jana with security + researchers at UT Austin and UC Davis +- Small stack size improvements, --enable-smallstack. Offloads large local + variables to the heap. (Note this is not complete.) +- Updated AES-CCM-8 cipher suites to use approved suite numbers. + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + +# CyaSSL Release 2.9.4 (04/09/2014) + +#### Release 2.9.4 CyaSSL has bug fixes and new features including: + +- Security fixes that address items reported by Ivan Fratric of the Google + Security Team +- X.509 Unknown critical extensions treated as errors, report by Suman Jana with + security researchers at UT Austin and UC Davis +- Sniffer fixes for corrupted packet length and Jumbo frames +- ARM thumb mode assembly fixes +- Xcode 5.1 support including new clang +- PIC32 MZ hardware support +- CyaSSL Object has enough room to read the Record Header now w/o allocs +- FIPS wrappers for AES, 3DES, SHA1, SHA256, SHA384, HMAC, and RSA. +- A sample I/O pool is demonstrated with --enable-iopool to overtake memory + handling and reduce memory fragmentation on I/O large sizes + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + +# CyaSSL Release 2.9.0 (02/07/2014) + +#### Release 2.9.0 CyaSSL has bug fixes and new features including: +- Freescale Kinetis RNGB support +- Freescale Kinetis mmCAU support +- TLS Hello extensions + - ECC + - Secure Renegotiation (null) + - Truncated HMAC +- SCEP support + - PKCS #7 Enveloped data and signed data + - PKCS #10 Certificate Signing Request generation +- DTLS sliding window +- OCSP Improvements + - API change to integrate into Certificate Manager + - IPv4/IPv6 agnostic + - example client/server support for OCSP + - OCSP nonces are optional +- GMAC hashing +- Windows build additions +- Windows CYGWIN build fixes +- Updated test certificates +- Microchip MPLAB Harmony support +- Update autoconf scripts +- Additional X.509 inspection functions +- ECC encrypt/decrypt primitives +- ECC Certificate generation + +The Freescale Kinetis K53 RNGB documentation can be found in Chapter 33 of the +K53 Sub-Family Reference Manual: +http://cache.freescale.com/files/32bit/doc/ref_manual/K53P144M100SF2RM.pdf + +Freescale Kinetis K60 mmCAU (AES, DES, 3DES, MD5, SHA, SHA256) documentation +can be found in the "ColdFire/ColdFire+ CAU and Kinetis mmCAU Software Library +User Guide": +http://cache.freescale.com/files/32bit/doc/user_guide/CAUAPIUG.pdf + + +# CyaSSL Release 2.8.0 (8/30/2013) + +#### Release 2.8.0 CyaSSL has bug fixes and new features including: +- AES-GCM and AES-CCM use AES-NI +- NetX default IO callback handlers +- IPv6 fixes for DTLS Hello Cookies +- The ability to unload Certs/Keys after the handshake, CyaSSL_UnloadCertsKeys() +- SEP certificate extensions +- Callback getters for easier resource freeing +- External CYASSL_MAX_ERROR_SZ for correct error buffer sizing +- MacEncrypt and DecryptVerify Callbacks for User Atomic Record Layer Processing +- Public Key Callbacks for ECC and RSA +- Client now sends blank cert upon request if doesn't have one with TLS <= 1.2 + + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + +# CyaSSL Release 2.7.0 (6/17/2013) + +#### Release 2.7.0 CyaSSL has bug fixes and new features including: +- SNI support for client and server +- KEIL MDK-ARM projects +- Wildcard check to domain name match, and Subject altnames are checked too +- Better error messages for certificate verification errors +- Ability to discard session during handshake verify +- More consistent error returns across all APIs +- Ability to unload CAs at the CTX or CertManager level +- Authority subject id support for Certificate matching +- Persistent session cache functionality +- Persistent CA cache functionality +- Client session table lookups to push serverID table to library level +- Camellia support to sniffer +- User controllable settings for DTLS timeout values +- Sniffer fixes for caching long lived sessions +- DTLS reliability enhancements for the handshake +- Better ThreadX support + +When compiling with Mingw, libtool may give the following warning due to +path conversion errors: + +``` +libtool: link: Could not determine host file name corresponding to ** +libtool: link: Continuing, but uninstalled executables may not work. +``` + +If so, examples and testsuite will have problems when run, showing an +error while loading shared libraries. To resolve, please run "make install". + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + +# CyaSSL Release 2.6.0 (04/15/2013) + +#### Release 2.6.0 CyaSSL has bug fixes and new features including: +- DTLS 1.2 support including AEAD ciphers +- SHA-3 finalist Blake2 support, it's fast and uses little resources +- SHA-384 cipher suites including ECC ones +- HMAC now supports SHA-512 +- Track memory use for example client/server with -t option +- Better IPv6 examples with --enable-ipv6, before if ipv6 examples/tests were + turned on, localhost only was used. Now link-local (with scope ids) and ipv6 + hosts can be used as well. +- Xcode v4.6 project for iOS v6.1 update +- settings.h is now checked in all *.c files for true one file setting detection +- Better alignment at SSL layer for hardware crypto alignment needs + * Note, SSL itself isn't friendly to alignment with 5 byte TLS headers and + 13 bytes DTLS headers, but every effort is now made to align with the + CYASSL_GENERAL_ALIGNMENT flag which sets desired alignment requirement +- NO_64BIT flag to turn off 64bit data type accumulators in public key code + * Note, some systems are faster with 32bit accumulators +- --enable-stacksize for example client/server stack use + * Note, modern desktop Operating Systems may add bytes to each stack frame +- Updated compression/decompression with direct crypto access +- All ./configure options are now lowercase only for consistency +- ./configure builds default to fastmath option + * Note, if on ia32 and building in shared mode this may produce a problem + with a missing register being available because of PIC, there are at least + 5 solutions to this: + 1) --disable-fastmath , don't use fastmath + 2) --disable-shared, don't build a shared library + 3) C_EXTRA_FLAGS=-DTFM_NO_ASM , turn off assembly use + 4) use clang, it just seems to work + 5) play around with no PIC options to force all registers being open +- Many new ./configure switches for option enable/disable for example + * rsa + * dh + * dsa + * md5 + * sha + * arc4 + * null (allow NULL ciphers) + * oldtls (only use TLS 1.2) + * asn (no certs or public keys allowed) +- ./configure generates cyassl/options.h which allows a header the user can + include in their app to make sure the same options are set at the app and + CyaSSL level. +- autoconf no longer needs serial-tests which lowers version requirements of + automake to 1.11 and autoconf to 2.63 + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + + +# CyaSSL Release 2.5.0 (02/04/2013) + +#### Release 2.5.0 CyaSSL has bug fixes and new features including: +- Fix for TLS CBC padding timing attack identified by Nadhem Alfardan and + Kenny Paterson: http://www.isg.rhul.ac.uk/tls/ +- Microchip PIC32 (MIPS16, MIPS32) support +- Microchip MPLAB X example projects for PIC32 Ethernet Starter Kit +- Updated CTaoCrypt benchmark app for embedded systems +- 1024-bit test certs/keys and cert/key buffers +- AES-CCM-8 crypto and cipher suites +- Camellia crypto and cipher suites +- Bumped minimum autoconf version to 2.65, automake version to 1.12 +- Addition of OCSP callbacks +- STM32F2 support with hardware crypto and RNG +- Cavium NITROX support + +CTaoCrypt now has support for the Microchip PIC32 and has been tested with +the Microchip PIC32 Ethernet Starter Kit, the XC32 compiler and +MPLAB X IDE in both MIPS16 and MIPS32 instruction set modes. See the README +located under the /mplabx directory for more details. + +To add Cavium NITROX support do: + +./configure --with-cavium=/home/user/cavium/software + +pointing to your licensed cavium/software directory. Since Cavium doesn't +build a library we pull in the cavium_common.o file which gives a libtool +warning about the portability of this. Also, if you're using the github source +tree you'll need to remove the -Wredundant-decls warning from the generated +Makefile because the cavium headers don't conform to this warning. Currently +CyaSSL supports Cavium RNG, AES, 3DES, RC4, HMAC, and RSA directly at the crypto +layer. Support at the SSL level is partial and currently just does AES, 3DES, +and RC4. RSA and HMAC are slower until the Cavium calls can be utilized in non +blocking mode. The example client turns on cavium support as does the crypto +test and benchmark. Please see the HAVE_CAVIUM define. + +CyaSSL is able to use the STM32F2 hardware-based cryptography and random number +generator through the STM32F2 Standard Peripheral Library. For necessary +defines, see the CYASSL_STM32F2 define in settings.h. Documentation for the +STM32F2 Standard Peripheral Library can be found in the following document: +http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/USER_MANUAL/DM00023896.pdf + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + + +# CyaSSL Release 2.4.6 (12/20/2012) + +#### Release 2.4.6 CyaSSL has bug fixes and a few new features including: +- ECC into main version +- Lean PSK build (reduced code size, RAM usage, and stack usage) +- FreeBSD CRL monitor support +- CyaSSL_peek() +- CyaSSL_send() and CyaSSL_recv() for I/O flag setting +- CodeWarrior Support +- MQX Support +- Freescale Kinetis support including Hardware RNG +- autoconf builds use jobserver +- cyassl-config +- Sniffer memory reductions + +Thanks to Brian Aker for the improved autoconf system, make rpm, cyassl-config, +warning system, and general good ideas for improving CyaSSL! + +The Freescale Kinetis K70 RNGA documentation can be found in Chapter 37 of the +K70 Sub-Family Reference Manual: +http://cache.freescale.com/files/microcontrollers/doc/ref_manual/K70P256M150SF3RM.pdf + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + +# CyaSSL Release 2.4.0 (10/10/2012) + +#### Release 2.4.0 CyaSSL has bug fixes and a few new features including: +- DTLS reliability +- Reduced memory usage after handshake +- Updated build process + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + + +# CyaSSL Release 2.3.0 (8/10/2012) + +#### Release 2.3.0 CyaSSL has bug fixes and a few new features including: +- AES-GCM crypto and cipher suites +- make test cipher suite checks +- Subject AltName processing +- Command line support for client/server examples +- Sniffer SessionTicket support +- SHA-384 cipher suites +- Verify cipher suite validity when user overrides +- CRL dir monitoring +- DTLS Cookie support, reliability coming soon + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + + +# CyaSSL Release 2.2.0 (5/18/2012) + +#### Release 2.2.0 CyaSSL has bug fixes and a few new features including: +- Initial CRL support (--enable-crl) +- Initial OCSP support (--enable-ocsp) +- Add static ECDH suites +- SHA-384 support +- ECC client certificate support +- Add medium session cache size (1055 sessions) +- Updated unit tests +- Protection against mutex reinitialization + + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + + +# CyaSSL Release 2.0.8 (2/24/2012) + +#### Release 2.0.8 CyaSSL has bug fixes and a few new features including: +- A fix for malicious certificates pointed out by Remi Gacogne (thanks) + resulting in NULL pointer use. +- Respond to renegotiation attempt with no_renegoatation alert +- Add basic path support for load_verify_locations() +- Add set Temp EC-DHE key size +- Extra checks on rsa test when porting into + + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + + +# CyaSSL Release 2.0.6 (1/27/2012) + +#### Release 2.0.6 CyaSSL has bug fixes and a few new features including: +- Fixes for CA basis constraint check +- CTX reference counting +- Initial unit test additions +- Lean and Mean Windows fix +- ECC benchmarking +- SSMTP build support +- Ability to group handshake messages with set_group_messages(ctx/ssl) +- CA cache addition callback +- Export Base64_Encode for general use + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + + +# CyaSSL Release 2.0.2 (12/05/2011) + +#### Release 2.0.2 CyaSSL has bug fixes and a few new features including: +- CTaoCrypt Runtime library detection settings when directly using the crypto + library +- Default certificate generation now uses SHAwRSA and adds SHA256wRSA generation +- All test certificates now use 2048bit and SHA-1 for better modern browser + support +- Direct AES block access and AES-CTR (counter) mode +- Microchip pic32 support + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + + + +# CyaSSL Release 2.0.0rc3 (9/28/2011) + +#### Release 2.0.0rc3 for CyaSSL has bug fixes and a few new features including: +- updated autoconf support +- better make install and uninstall (uses system directories) +- make test / make check +- CyaSSL headers now in +- CTaocrypt headers now in +- OpenSSL compatibility headers now in +- examples and tests all run from home directory so can use certs in ./certs + (see note 1) + +So previous applications that used the OpenSSL compatibility header + now need to include instead, no other +changes are required. + +Special Thanks to Brian Aker for his autoconf, install, and header patches. + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + +# CyaSSL Release 2.0.0rc2 (6/6/2011) + +#### Release 2.0.0rc2 for CyaSSL has bug fixes and a few new features including: +- bug fixes (Alerts, DTLS with DHE) +- FreeRTOS support +- lwIP support +- Wshadow warnings removed +- asn public header +- CTaoCrypt public headers now all have ctc_ prefix (the manual is still being + updated to reflect this change) +- and more. + +This is the 2nd and perhaps final release candidate for version 2. +Please send any comments or questions to support@yassl.com. + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + +# CyaSSL Release 2.0.0rc1 (5/2/2011) + +#### Release 2.0.0rc1 for CyaSSL has many new features including: +- bug fixes +- SHA-256 cipher suites +- Root Certificate Verification (instead of needing all certs in the chain) +- PKCS #8 private key encryption (supports PKCS #5 v1-v2 and PKCS #12) +- Serial number retrieval for x509 +- PBKDF2 and PKCS #12 PBKDF +- UID parsing for x509 +- SHA-256 certificate signatures +- Client and server can send chains (SSL_CTX_use_certificate_chain_file) +- CA loading can now parse multiple certificates per file +- Dynamic memory runtime hooks +- Runtime hooks for logging +- EDH on server side +- More informative error codes +- More informative logging messages +- Version downgrade more robust (use SSL_v23*) +- Shared build only by default through ./configure +- Compiler visibility is now used, internal functions not polluting namespace +- Single Makefile, no recursion, for faster and simpler building +- Turn on all warnings possible build option, warning fixes +- and more. + +Because of all the new features and the multiple OS, compiler, feature-set +options that CyaSSL allows, there may be some configuration fixes needed. +Please send any comments or questions to support@yassl.com. + +The CyaSSL manual is available at: +http://www.yassl.com/documentation/CyaSSL-Manual.pdf. For build instructions +and comments about the new features please check the manual. + +# CyaSSL Release 1.9.0 (3/2/2011) + +Release 1.9.0 for CyaSSL adds bug fixes, improved TLSv1.2 through testing and +better hash/sig algo ids, --enable-webServer for the yaSSL embedded web server, +improper AES key setup detection, user cert verify callback improvements, and +more. + +The CyaSSL manual offering is included in the doc/ directory. For build +instructions and comments about the new features please check the manual. + +Please send any comments or questions to support@yassl.com. + +# CyaSSL Release 1.8.0 (12/23/2010) + +Release 1.8.0 for CyaSSL adds bug fixes, x509 v3 CA signed certificate +generation, a C standard library abstraction layer, lower memory use, increased +portability through the os_settings.h file, and the ability to use NTRU cipher +suites when used in conjunction with an NTRU license and library. + +The initial CyaSSL manual offering is included in the doc/ directory. For +build instructions and comments about the new features please check the manual. + +Please send any comments or questions to support@yassl.com. + +Happy Holidays. + + +# CyaSSL Release 1.6.5 (9/9/2010) + +Release 1.6.5 for CyaSSL adds bug fixes and x509 v3 self signed certificate +generation. + +For general build instructions see doc/Building_CyaSSL.pdf. + +To enable certificate generation support add this option to ./configure +./configure --enable-certgen + +An example is included in ctaocrypt/test/test.c and documentation is provided +in doc/CyaSSL_Extensions_Reference.pdf item 11. + +# CyaSSL Release 1.6.0 (8/27/2010) + +Release 1.6.0 for CyaSSL adds bug fixes, RIPEMD-160, SHA-512, and RSA key +generation. + +For general build instructions see doc/Building_CyaSSL.pdf. + +To add RIPEMD-160 support add this option to ./configure +./configure --enable-ripemd + +To add SHA-512 support add this option to ./configure +./configure --enable-sha512 + +To add RSA key generation support add this option to ./configure +./configure --enable-keygen + +Please see ctaocrypt/test/test.c for examples and usage. + +For Windows, RIPEMD-160 and SHA-512 are enabled by default but key generation is +off by default. To turn key generation on add the define CYASSL_KEY_GEN to +CyaSSL. + + +# CyaSSL Release 1.5.6 (7/28/2010) + +Release 1.5.6 for CyaSSL adds bug fixes, compatibility for our JSSE provider, +and a fix for GCC builds on some systems. + +For general build instructions see doc/Building_CyaSSL.pdf. + +To add AES-NI support add this option to ./configure +./configure --enable-aesni + +You'll need GCC 4.4.3 or later to make use of the assembly. + +# CyaSSL Release 1.5.4 (7/7/2010) + +Release 1.5.4 for CyaSSL adds bug fixes, support for AES-NI, SHA1 speed +improvements from loop unrolling, and support for the Mongoose Web Server. + +For general build instructions see doc/Building_CyaSSL.pdf. + +To add AES-NI support add this option to ./configure +./configure --enable-aesni + +You'll need GCC 4.4.3 or later to make use of the assembly. + +# CyaSSL Release 1.5.0 (5/11/2010) + +Release 1.5.0 for CyaSSL adds bug fixes, GoAhead WebServer support, sniffer +support, and initial swig interface support. + +For general build instructions see doc/Building_CyaSSL.pdf. + +To add support for GoAhead WebServer either --enable-opensslExtra or if you +don't want all the features of opensslExtra you can just define GOAHEAD_WS +instead. GOAHEAD_WS can be added to ./configure with CFLAGS=-DGOAHEAD_WS or +you can define it yourself. + +To look at the sniffer support please see the sniffertest app in +sslSniffer/sslSnifferTest. Build with --enable-sniffer on *nix or use the +vcproj files on windows. You'll need to have pcap installed on *nix and +WinPcap on windows. + +A swig interface file is now located in the swig directory for using Python, +Java, Perl, and others with CyaSSL. This is initial support and experimental, +please send questions or comments to support@yassl.com. + +When doing load testing with CyaSSL, on the echoserver example say, the client +machine may run out of tcp ephemeral ports, they will end up in the TIME_WAIT +queue, and can't be reused by default. There are generally two ways to fix +this. + +1. Reduce the length sockets remain on the TIME_WAIT queue OR +2. Allow items on the TIME_WAIT queue to be reused. + + +To reduce the TIME_WAIT length in OS X to 3 seconds (3000 milliseconds) + +`sudo sysctl -w net.inet.tcp.msl=3000` + +In Linux + +`sudo sysctl -w net.ipv4.tcp_tw_reuse=1` + +allows reuse of sockets in TIME_WAIT + +`sudo sysctl -w net.ipv4.tcp_tw_recycle=1` + +works but seems to remove sockets from TIME_WAIT entirely? + +`sudo sysctl -w net.ipv4.tcp_fin_timeout=1` + +doen't control TIME_WAIT, it controls FIN_WAIT(2) contrary to some posts + + +# CyaSSL Release 1.4.0 (2/18/2010) + +Release 1.3.0 for CyaSSL adds bug fixes, better multi TLS/SSL version support +through SSLv23_server_method(), and improved documentation in the doc/ folder. + +For general build instructions doc/Building_CyaSSL.pdf. + +# CyaSSL Release 1.3.0 (1/21/2010) + +Release 1.3.0 for CyaSSL adds bug fixes, a potential security problem fix, +better porting support, removal of assert()s, and a complete THREADX port. + +For general build instructions see rc1 below. + +# CyaSSL Release 1.2.0 (11/2/2009) + +Release 1.2.0 for CyaSSL adds bug fixes and session negotiation if first use is +read or write. + +For general build instructions see rc1 below. + +# CyaSSL Release 1.1.0 (9/2/2009) + +Release 1.1.0 for CyaSSL adds bug fixes, a check against malicious session +cache use, support for lighttpd, and TLS 1.2. + +To get TLS 1.2 support please use the client and server functions: + +```c +SSL_METHOD *TLSv1_2_server_method(void); +SSL_METHOD *TLSv1_2_client_method(void); +``` + +CyaSSL was tested against lighttpd 1.4.23. To build CyaSSL for use with +lighttpd use the following commands from the CyaSSL install dir : + +``` +./configure --disable-shared --enable-opensslExtra --enable-fastmath --without-zlib + +make +make openssl-links +``` + +Then to build lighttpd with CyaSSL use the following commands from the +lighttpd install dir: + +``` +./configure --with-openssl --with-openssl-includes=/include --with-openssl-libs=/lib LDFLAGS=-lm + +make +``` + +On some systems you may get a linker error about a duplicate symbol for +MD5_Init or other MD5 calls. This seems to be caused by the lighttpd src file +md5.c, which defines MD5_Init(), and is included in liblightcomp_la-md5.o. +When liblightcomp is linked with the SSL_LIBs the linker may complain about +the duplicate symbol. This can be fixed by editing the lighttpd src file md5.c +and adding this line to the beginning of the file: + +\#if 0 + +and this line to the end of the file + +\#endif + +Then from the lighttpd src dir do a: + +``` +make clean +make +``` + +If you get link errors about undefined symbols more than likely the actual +OpenSSL libraries are found by the linker before the CyaSSL openssl-links that +point to the CyaSSL library, causing the linker confusion. This can be fixed +by editing the Makefile in the lighttpd src directory and changing the line: + +`SSL_LIB = -lssl -lcrypto` + +to + +`SSL_LIB = -lcyassl` + +Then from the lighttpd src dir do a: + +``` +make clean +make +``` + +This should remove any confusion the linker may be having with missing symbols. + +For any questions or concerns please contact support@yassl.com . + +For general build instructions see rc1 below. + +# CyaSSL Release 1.0.6 (8/03/2009) + +Release 1.0.6 for CyaSSL adds bug fixes, an improved session cache, and faster +math with a huge code option. + +The session cache now defaults to a client mode, also good for embedded servers. +For servers not under heavy load (less than 200 new sessions per minute), define +BIG_SESSION_CACHE. If the server will be under heavy load, define +HUGE_SESSION_CACHE. + +There is now a fasthugemath option for configure. This enables fastmath plus +even faster math by greatly increasing the code size of the math library. Use +the benchmark utility to compare public key operations. + + +For general build instructions see rc1 below. + +# CyaSSL Release 1.0.3 (5/10/2009) + +Release 1.0.3 for CyaSSL adds bug fixes and add increased support for OpenSSL +compatibility when building other applications. + +Release 1.0.3 includes an alpha release of DTLS for both client and servers. +This is only for testing purposes at this time. Rebroadcast and reordering +aren't fully implemented at this time but will be for the next release. + +For general build instructions see rc1 below. + +# CyaSSL Release 1.0.2 (4/3/2009) + +Release 1.0.2 for CyaSSL adds bug fixes for a couple I/O issues. Some systems +will send a SIGPIPE on socket recv() at any time and this should be handled by +the application by turning off SIGPIPE through setsockopt() or returning from +the handler. + +Release 1.0.2 includes an alpha release of DTLS for both client and servers. +This is only for testing purposes at this time. Rebroadcast and reordering +aren't fully implemented at this time but will be for the next release. + +For general build instructions see rc1 below. + +## CyaSSL Release Candidiate 3 rc3-1.0.0 (2/25/2009) + + +Release Candidate 3 for CyaSSL 1.0.0 adds bug fixes and adds a project file for +iPhone development with Xcode. cyassl-iphone.xcodeproj is located in the root +directory. This release also includes a fix for supporting other +implementations that bundle multiple messages at the record layer, this was +lost when cyassl i/o was re-implemented but is now fixed. + +For general build instructions see rc1 below. + +## CyaSSL Release Candidiate 2 rc2-1.0.0 (1/21/2009) + + +Release Candidate 2 for CyaSSL 1.0.0 adds bug fixes and adds two new stream +ciphers along with their respective cipher suites. CyaSSL adds support for +HC-128 and RABBIT stream ciphers. The new suites are: + +``` +TLS_RSA_WITH_HC_128_SHA +TLS_RSA_WITH_RABBIT_SHA +``` + +And the corresponding cipher names are + +``` +HC128-SHA +RABBIT-SHA +``` + +CyaSSL also adds support for building with devkitPro for PPC by changing the +library proper to use libogc. The examples haven't been changed yet but if +there's interest they can be. Here's an example ./configure to build CyaSSL +for devkitPro: + +``` +./configure --disable-shared CC=/pathTo/devkitpro/devkitPPC/bin/powerpc-gekko-gcc --host=ppc --without-zlib --enable-singleThreaded RANLIB=/pathTo/devkitpro/devkitPPC/bin/powerpc-gekko-ranlib CFLAGS="-DDEVKITPRO -DGEKKO" +``` + +For linking purposes you'll need + +`LDFLAGS="-g -mrvl -mcpu=750 -meabi -mhard-float -Wl,-Map,$(notdir $@).map"` + +For general build instructions see rc1 below. + + +## CyaSSL Release Candidiate 1 rc1-1.0.0 (12/17/2008) + + +Release Candidate 1 for CyaSSL 1.0.0 contains major internal changes. Several +areas have optimization improvements, less dynamic memory use, and the I/O +strategy has been refactored to allow alternate I/O handling or Library use. +Many thanks to Thierry Fournier for providing these ideas and most of the work. + +Because of these changes, this release is only a candidate since some problems +are probably inevitable on some platform with some I/O use. Please report any +problems and we'll try to resolve them as soon as possible. You can contact us +at support@yassl.com or todd@yassl.com. + +Using TomsFastMath by passing --enable-fastmath to ./configure now uses assembly +on some platforms. This is new so please report any problems as every compiler, +mode, OS combination hasn't been tested. On ia32 all of the registers need to +be available so be sure to pass these options to CFLAGS: + +`CFLAGS="-O3 -fomit-frame-pointer"` + +OS X will also need -mdynamic-no-pic added to CFLAGS + +Also if you're building in shared mode for ia32 you'll need to pass options to +LDFLAGS as well on OS X: + +`LDFLAGS=-Wl,-read_only_relocs,warning` + +This gives warnings for some symbols but seems to work. + + +#### To build on Linux, Solaris, *BSD, Mac OS X, or Cygwin: + + ./configure + make + + from the ./testsuite/ directory run ./testsuite + +#### To make a debug build: + + ./configure --enable-debug --disable-shared + make + + + +#### To build on Win32 + +Choose (Re)Build All from the project workspace + +Run the testsuite program + + + + + +# CyaSSL version 0.9.9 (7/25/2008) + +This release of CyaSSL adds bug fixes, Pre-Shared Keys, over-rideable memory +handling, and optionally TomsFastMath. Thanks to Moisés Guimarães for the +work on TomsFastMath. + +To optionally use TomsFastMath pass --enable-fastmath to ./configure +Or define USE_FAST_MATH in each project from CyaSSL for MSVC. + +Please use the benchmark routine before and after to see the performance +difference, on some platforms the gains will be little but RSA encryption +always seems to be faster. On x86-64 machines with GCC the normal math library +may outperform the fast one when using CFLAGS=-m64 because TomsFastMath can't +yet use -m64 because of GCCs inability to do 128bit division. + + *** UPDATE GCC 4.2.1 can now do 128bit division *** + +See notes below (0.2.0) for complete build instructions. + + +# CyaSSL version 0.9.8 (5/7/2008) + +This release of CyaSSL adds bug fixes, client side Diffie-Hellman, and better +socket handling. + +See notes below (0.2.0) for complete build instructions. + + +# CyaSSL version 0.9.6 (1/31/2008) + +This release of CyaSSL adds bug fixes, increased session management, and a fix +for gnutls. + +See notes below (0.2.0) for complete build instructions. + + +# CyaSSL version 0.9.0 (10/15/2007) + +This release of CyaSSL adds bug fixes, MSVC 2005 support, GCC 4.2 support, +IPV6 support and test, and new test certificates. + +See notes below (0.2.0) for complete build instructions. + + +# CyaSSL version 0.8.0 (1/10/2007) + +This release of CyaSSL adds increased socket support, for non-blocking writes, +connects, and interrupted system calls. + +See notes below (0.2.0) for complete build instructions. + + +# CyaSSL version 0.6.3 (10/30/2006) + +This release of CyaSSL adds debug logging to stderr to aid in the debugging of +CyaSSL on systems that may not provide the best support. + +If CyaSSL is built with debugging support then you need to call +CyaSSL_Debugging_ON() to turn logging on. + +On Unix use ./configure --enable-debug + +On Windows define DEBUG_CYASSL when building CyaSSL + + +To turn logging back off call CyaSSL_Debugging_OFF() + +See notes below (0.2.0) for complete build instructions. + + +# CyaSSL version 0.6.2 (10/29/2006) + +This release of CyaSSL adds TLS 1.1. + +Note that CyaSSL has certificate verification on by default, unlike OpenSSL. +To emulate OpenSSL behavior, you must call SSL_CTX_set_verify() with +SSL_VERIFY_NONE. In order to have full security you should never do this, +provide CyaSSL with the proper certificates to eliminate impostors and call +CyaSSL_check_domain_name() to prevent man in the middle attacks. + +See notes below (0.2.0) for build instructions. + +# CyaSSL version 0.6.0 (10/25/2006) + +This release of CyaSSL adds more SSL functions, better autoconf, nonblocking +I/O for accept, connect, and read. There is now an --enable-small configure +option that turns off TLS, AES, DES3, HMAC, and ERROR_STRINGS, see configure.in +for the defines. Note that TLS requires HMAC and AES requires TLS. + +See notes below (0.2.0) for build instructions. + + +# CyaSSL version 0.5.5 (09/27/2006) + +This mini release of CyaSSL adds better input processing through buffered input +and big message support. Added SSL_pending() and some sanity checks on user +settings. + +See notes below (0.2.0) for build instructions. + + +# CyaSSL version 0.5.0 (03/27/2006) + +This release of CyaSSL adds AES support and minor bug fixes. + +See notes below (0.2.0) for build instructions. + + +# CyaSSL version 0.4.0 (03/15/2006) + +This release of CyaSSL adds TLSv1 client/server support and libtool. + +See notes below for build instructions. + + +# CyaSSL version 0.3.0 (02/26/2006) + +This release of CyaSSL adds SSLv3 server support and session resumption. + +See notes below for build instructions. + + +# CyaSSL version 0.2.0 (02/19/2006) + + +This is the first release of CyaSSL and its crypt brother, CTaoCrypt. CyaSSL +is written in ANSI C with the idea of a small code size, footprint, and memory +usage in mind. CTaoCrypt can be as small as 32K, and the current client +version of CyaSSL can be as small as 12K. + + +The first release of CTaoCrypt supports MD5, SHA-1, 3DES, ARC4, Big Integer +Support, RSA, ASN parsing, and basic x509 (en/de)coding. + +The first release of CyaSSL supports normal client RSA mode SSLv3 connections +with support for SHA-1 and MD5 digests. Ciphers include 3DES and RC4. + + +#### To build on Linux, Solaris, *BSD, Mac OS X, or Cygwin: + + ./configure + make + + from the ./testsuite/ directory run ./testsuite + +#### to make a debug build: + + ./configure --enable-debug --disable-shared + make + + + +#### To build on Win32 + +Choose (Re)Build All from the project workspace + +Run the testsuite program + + + +*** The next release of CyaSSL will support a server and more OpenSSL +compatibility functions. + + +Please send questions or comments to todd@yassl.com diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ReadMeFirst.url b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ReadMeFirst.url new file mode 100644 index 0000000..19432f5 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ReadMeFirst.url @@ -0,0 +1,5 @@ +[InternetShortcut] +URL=http://www.freertos.org/ssl +IDList= +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/aclocal.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/aclocal.m4 new file mode 100644 index 0000000..64fd2c6 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/aclocal.m4 @@ -0,0 +1,1195 @@ +# generated automatically by aclocal 1.14.1 -*- Autoconf -*- + +# Copyright (C) 1996-2013 Free Software Foundation, Inc. + +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +m4_ifndef([AC_CONFIG_MACRO_DIRS], [m4_defun([_AM_CONFIG_MACRO_DIRS], [])m4_defun([AC_CONFIG_MACRO_DIRS], [_AM_CONFIG_MACRO_DIRS($@)])]) +m4_ifndef([AC_AUTOCONF_VERSION], + [m4_copy([m4_PACKAGE_VERSION], [AC_AUTOCONF_VERSION])])dnl +m4_if(m4_defn([AC_AUTOCONF_VERSION]), [2.69],, +[m4_warning([this file was generated for autoconf 2.69. +You have another version of autoconf. It may work, but is not guaranteed to. +If you have problems, you may need to regenerate the build system entirely. +To do so, use the procedure documented by the package, typically 'autoreconf'.])]) + +# Copyright (C) 2002-2013 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# AM_AUTOMAKE_VERSION(VERSION) +# ---------------------------- +# Automake X.Y traces this macro to ensure aclocal.m4 has been +# generated from the m4 files accompanying Automake X.Y. +# (This private macro should not be called outside this file.) +AC_DEFUN([AM_AUTOMAKE_VERSION], +[am__api_version='1.14' +dnl Some users find AM_AUTOMAKE_VERSION and mistake it for a way to +dnl require some minimum version. Point them to the right macro. +m4_if([$1], [1.14.1], [], + [AC_FATAL([Do not call $0, use AM_INIT_AUTOMAKE([$1]).])])dnl +]) + +# _AM_AUTOCONF_VERSION(VERSION) +# ----------------------------- +# aclocal traces this macro to find the Autoconf version. +# This is a private macro too. Using m4_define simplifies +# the logic in aclocal, which can simply ignore this definition. +m4_define([_AM_AUTOCONF_VERSION], []) + +# AM_SET_CURRENT_AUTOMAKE_VERSION +# ------------------------------- +# Call AM_AUTOMAKE_VERSION and AM_AUTOMAKE_VERSION so they can be traced. +# This function is AC_REQUIREd by AM_INIT_AUTOMAKE. +AC_DEFUN([AM_SET_CURRENT_AUTOMAKE_VERSION], +[AM_AUTOMAKE_VERSION([1.14.1])dnl +m4_ifndef([AC_AUTOCONF_VERSION], + [m4_copy([m4_PACKAGE_VERSION], [AC_AUTOCONF_VERSION])])dnl +_AM_AUTOCONF_VERSION(m4_defn([AC_AUTOCONF_VERSION]))]) + +# Figure out how to run the assembler. -*- Autoconf -*- + +# Copyright (C) 2001-2013 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# AM_PROG_AS +# ---------- +AC_DEFUN([AM_PROG_AS], +[# By default we simply use the C compiler to build assembly code. +AC_REQUIRE([AC_PROG_CC]) +test "${CCAS+set}" = set || CCAS=$CC +test "${CCASFLAGS+set}" = set || CCASFLAGS=$CFLAGS +AC_ARG_VAR([CCAS], [assembler compiler command (defaults to CC)]) +AC_ARG_VAR([CCASFLAGS], [assembler compiler flags (defaults to CFLAGS)]) +_AM_IF_OPTION([no-dependencies],, [_AM_DEPENDENCIES([CCAS])])dnl +]) + +# AM_AUX_DIR_EXPAND -*- Autoconf -*- + +# Copyright (C) 2001-2013 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# For projects using AC_CONFIG_AUX_DIR([foo]), Autoconf sets +# $ac_aux_dir to '$srcdir/foo'. In other projects, it is set to +# '$srcdir', '$srcdir/..', or '$srcdir/../..'. +# +# Of course, Automake must honor this variable whenever it calls a +# tool from the auxiliary directory. The problem is that $srcdir (and +# therefore $ac_aux_dir as well) can be either absolute or relative, +# depending on how configure is run. This is pretty annoying, since +# it makes $ac_aux_dir quite unusable in subdirectories: in the top +# source directory, any form will work fine, but in subdirectories a +# relative path needs to be adjusted first. +# +# $ac_aux_dir/missing +# fails when called from a subdirectory if $ac_aux_dir is relative +# $top_srcdir/$ac_aux_dir/missing +# fails if $ac_aux_dir is absolute, +# fails when called from a subdirectory in a VPATH build with +# a relative $ac_aux_dir +# +# The reason of the latter failure is that $top_srcdir and $ac_aux_dir +# are both prefixed by $srcdir. In an in-source build this is usually +# harmless because $srcdir is '.', but things will broke when you +# start a VPATH build or use an absolute $srcdir. +# +# So we could use something similar to $top_srcdir/$ac_aux_dir/missing, +# iff we strip the leading $srcdir from $ac_aux_dir. That would be: +# am_aux_dir='\$(top_srcdir)/'`expr "$ac_aux_dir" : "$srcdir//*\(.*\)"` +# and then we would define $MISSING as +# MISSING="\${SHELL} $am_aux_dir/missing" +# This will work as long as MISSING is not called from configure, because +# unfortunately $(top_srcdir) has no meaning in configure. +# However there are other variables, like CC, which are often used in +# configure, and could therefore not use this "fixed" $ac_aux_dir. +# +# Another solution, used here, is to always expand $ac_aux_dir to an +# absolute PATH. The drawback is that using absolute paths prevent a +# configured tree to be moved without reconfiguration. + +AC_DEFUN([AM_AUX_DIR_EXPAND], +[dnl Rely on autoconf to set up CDPATH properly. +AC_PREREQ([2.50])dnl +# expand $ac_aux_dir to an absolute path +am_aux_dir=`cd $ac_aux_dir && pwd` +]) + +# AM_CONDITIONAL -*- Autoconf -*- + +# Copyright (C) 1997-2013 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# AM_CONDITIONAL(NAME, SHELL-CONDITION) +# ------------------------------------- +# Define a conditional. +AC_DEFUN([AM_CONDITIONAL], +[AC_PREREQ([2.52])dnl + m4_if([$1], [TRUE], [AC_FATAL([$0: invalid condition: $1])], + [$1], [FALSE], [AC_FATAL([$0: invalid condition: $1])])dnl +AC_SUBST([$1_TRUE])dnl +AC_SUBST([$1_FALSE])dnl +_AM_SUBST_NOTMAKE([$1_TRUE])dnl +_AM_SUBST_NOTMAKE([$1_FALSE])dnl +m4_define([_AM_COND_VALUE_$1], [$2])dnl +if $2; then + $1_TRUE= + $1_FALSE='#' +else + $1_TRUE='#' + $1_FALSE= +fi +AC_CONFIG_COMMANDS_PRE( +[if test -z "${$1_TRUE}" && test -z "${$1_FALSE}"; then + AC_MSG_ERROR([[conditional "$1" was never defined. +Usually this means the macro was only invoked conditionally.]]) +fi])]) + +# Copyright (C) 1999-2013 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + + +# There are a few dirty hacks below to avoid letting 'AC_PROG_CC' be +# written in clear, in which case automake, when reading aclocal.m4, +# will think it sees a *use*, and therefore will trigger all it's +# C support machinery. Also note that it means that autoscan, seeing +# CC etc. in the Makefile, will ask for an AC_PROG_CC use... + + +# _AM_DEPENDENCIES(NAME) +# ---------------------- +# See how the compiler implements dependency checking. +# NAME is "CC", "CXX", "OBJC", "OBJCXX", "UPC", or "GJC". +# We try a few techniques and use that to set a single cache variable. +# +# We don't AC_REQUIRE the corresponding AC_PROG_CC since the latter was +# modified to invoke _AM_DEPENDENCIES(CC); we would have a circular +# dependency, and given that the user is not expected to run this macro, +# just rely on AC_PROG_CC. +AC_DEFUN([_AM_DEPENDENCIES], +[AC_REQUIRE([AM_SET_DEPDIR])dnl +AC_REQUIRE([AM_OUTPUT_DEPENDENCY_COMMANDS])dnl +AC_REQUIRE([AM_MAKE_INCLUDE])dnl +AC_REQUIRE([AM_DEP_TRACK])dnl + +m4_if([$1], [CC], [depcc="$CC" am_compiler_list=], + [$1], [CXX], [depcc="$CXX" am_compiler_list=], + [$1], [OBJC], [depcc="$OBJC" am_compiler_list='gcc3 gcc'], + [$1], [OBJCXX], [depcc="$OBJCXX" am_compiler_list='gcc3 gcc'], + [$1], [UPC], [depcc="$UPC" am_compiler_list=], + [$1], [GCJ], [depcc="$GCJ" am_compiler_list='gcc3 gcc'], + [depcc="$$1" am_compiler_list=]) + +AC_CACHE_CHECK([dependency style of $depcc], + [am_cv_$1_dependencies_compiler_type], +[if test -z "$AMDEP_TRUE" && test -f "$am_depcomp"; then + # We make a subdir and do the tests there. Otherwise we can end up + # making bogus files that we don't know about and never remove. For + # instance it was reported that on HP-UX the gcc test will end up + # making a dummy file named 'D' -- because '-MD' means "put the output + # in D". + rm -rf conftest.dir + mkdir conftest.dir + # Copy depcomp to subdir because otherwise we won't find it if we're + # using a relative directory. + cp "$am_depcomp" conftest.dir + cd conftest.dir + # We will build objects and dependencies in a subdirectory because + # it helps to detect inapplicable dependency modes. For instance + # both Tru64's cc and ICC support -MD to output dependencies as a + # side effect of compilation, but ICC will put the dependencies in + # the current directory while Tru64 will put them in the object + # directory. + mkdir sub + + am_cv_$1_dependencies_compiler_type=none + if test "$am_compiler_list" = ""; then + am_compiler_list=`sed -n ['s/^#*\([a-zA-Z0-9]*\))$/\1/p'] < ./depcomp` + fi + am__universal=false + m4_case([$1], [CC], + [case " $depcc " in #( + *\ -arch\ *\ -arch\ *) am__universal=true ;; + esac], + [CXX], + [case " $depcc " in #( + *\ -arch\ *\ -arch\ *) am__universal=true ;; + esac]) + + for depmode in $am_compiler_list; do + # Setup a source with many dependencies, because some compilers + # like to wrap large dependency lists on column 80 (with \), and + # we should not choose a depcomp mode which is confused by this. + # + # We need to recreate these files for each test, as the compiler may + # overwrite some of them when testing with obscure command lines. + # This happens at least with the AIX C compiler. + : > sub/conftest.c + for i in 1 2 3 4 5 6; do + echo '#include "conftst'$i'.h"' >> sub/conftest.c + # Using ": > sub/conftst$i.h" creates only sub/conftst1.h with + # Solaris 10 /bin/sh. + echo '/* dummy */' > sub/conftst$i.h + done + echo "${am__include} ${am__quote}sub/conftest.Po${am__quote}" > confmf + + # We check with '-c' and '-o' for the sake of the "dashmstdout" + # mode. It turns out that the SunPro C++ compiler does not properly + # handle '-M -o', and we need to detect this. Also, some Intel + # versions had trouble with output in subdirs. + am__obj=sub/conftest.${OBJEXT-o} + am__minus_obj="-o $am__obj" + case $depmode in + gcc) + # This depmode causes a compiler race in universal mode. + test "$am__universal" = false || continue + ;; + nosideeffect) + # After this tag, mechanisms are not by side-effect, so they'll + # only be used when explicitly requested. + if test "x$enable_dependency_tracking" = xyes; then + continue + else + break + fi + ;; + msvc7 | msvc7msys | msvisualcpp | msvcmsys) + # This compiler won't grok '-c -o', but also, the minuso test has + # not run yet. These depmodes are late enough in the game, and + # so weak that their functioning should not be impacted. + am__obj=conftest.${OBJEXT-o} + am__minus_obj= + ;; + none) break ;; + esac + if depmode=$depmode \ + source=sub/conftest.c object=$am__obj \ + depfile=sub/conftest.Po tmpdepfile=sub/conftest.TPo \ + $SHELL ./depcomp $depcc -c $am__minus_obj sub/conftest.c \ + >/dev/null 2>conftest.err && + grep sub/conftst1.h sub/conftest.Po > /dev/null 2>&1 && + grep sub/conftst6.h sub/conftest.Po > /dev/null 2>&1 && + grep $am__obj sub/conftest.Po > /dev/null 2>&1 && + ${MAKE-make} -s -f confmf > /dev/null 2>&1; then + # icc doesn't choke on unknown options, it will just issue warnings + # or remarks (even with -Werror). So we grep stderr for any message + # that says an option was ignored or not supported. + # When given -MP, icc 7.0 and 7.1 complain thusly: + # icc: Command line warning: ignoring option '-M'; no argument required + # The diagnosis changed in icc 8.0: + # icc: Command line remark: option '-MP' not supported + if (grep 'ignoring option' conftest.err || + grep 'not supported' conftest.err) >/dev/null 2>&1; then :; else + am_cv_$1_dependencies_compiler_type=$depmode + break + fi + fi + done + + cd .. + rm -rf conftest.dir +else + am_cv_$1_dependencies_compiler_type=none +fi +]) +AC_SUBST([$1DEPMODE], [depmode=$am_cv_$1_dependencies_compiler_type]) +AM_CONDITIONAL([am__fastdep$1], [ + test "x$enable_dependency_tracking" != xno \ + && test "$am_cv_$1_dependencies_compiler_type" = gcc3]) +]) + + +# AM_SET_DEPDIR +# ------------- +# Choose a directory name for dependency files. +# This macro is AC_REQUIREd in _AM_DEPENDENCIES. +AC_DEFUN([AM_SET_DEPDIR], +[AC_REQUIRE([AM_SET_LEADING_DOT])dnl +AC_SUBST([DEPDIR], ["${am__leading_dot}deps"])dnl +]) + + +# AM_DEP_TRACK +# ------------ +AC_DEFUN([AM_DEP_TRACK], +[AC_ARG_ENABLE([dependency-tracking], [dnl +AS_HELP_STRING( + [--enable-dependency-tracking], + [do not reject slow dependency extractors]) +AS_HELP_STRING( + [--disable-dependency-tracking], + [speeds up one-time build])]) +if test "x$enable_dependency_tracking" != xno; then + am_depcomp="$ac_aux_dir/depcomp" + AMDEPBACKSLASH='\' + am__nodep='_no' +fi +AM_CONDITIONAL([AMDEP], [test "x$enable_dependency_tracking" != xno]) +AC_SUBST([AMDEPBACKSLASH])dnl +_AM_SUBST_NOTMAKE([AMDEPBACKSLASH])dnl +AC_SUBST([am__nodep])dnl +_AM_SUBST_NOTMAKE([am__nodep])dnl +]) + +# Generate code to set up dependency tracking. -*- Autoconf -*- + +# Copyright (C) 1999-2013 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + + +# _AM_OUTPUT_DEPENDENCY_COMMANDS +# ------------------------------ +AC_DEFUN([_AM_OUTPUT_DEPENDENCY_COMMANDS], +[{ + # Older Autoconf quotes --file arguments for eval, but not when files + # are listed without --file. Let's play safe and only enable the eval + # if we detect the quoting. + case $CONFIG_FILES in + *\'*) eval set x "$CONFIG_FILES" ;; + *) set x $CONFIG_FILES ;; + esac + shift + for mf + do + # Strip MF so we end up with the name of the file. + mf=`echo "$mf" | sed -e 's/:.*$//'` + # Check whether this is an Automake generated Makefile or not. + # We used to match only the files named 'Makefile.in', but + # some people rename them; so instead we look at the file content. + # Grep'ing the first line is not enough: some people post-process + # each Makefile.in and add a new line on top of each file to say so. + # Grep'ing the whole file is not good either: AIX grep has a line + # limit of 2048, but all sed's we know have understand at least 4000. + if sed -n 's,^#.*generated by automake.*,X,p' "$mf" | grep X >/dev/null 2>&1; then + dirpart=`AS_DIRNAME("$mf")` + else + continue + fi + # Extract the definition of DEPDIR, am__include, and am__quote + # from the Makefile without running 'make'. + DEPDIR=`sed -n 's/^DEPDIR = //p' < "$mf"` + test -z "$DEPDIR" && continue + am__include=`sed -n 's/^am__include = //p' < "$mf"` + test -z "$am__include" && continue + am__quote=`sed -n 's/^am__quote = //p' < "$mf"` + # Find all dependency output files, they are included files with + # $(DEPDIR) in their names. We invoke sed twice because it is the + # simplest approach to changing $(DEPDIR) to its actual value in the + # expansion. + for file in `sed -n " + s/^$am__include $am__quote\(.*(DEPDIR).*\)$am__quote"'$/\1/p' <"$mf" | \ + sed -e 's/\$(DEPDIR)/'"$DEPDIR"'/g'`; do + # Make sure the directory exists. + test -f "$dirpart/$file" && continue + fdir=`AS_DIRNAME(["$file"])` + AS_MKDIR_P([$dirpart/$fdir]) + # echo "creating $dirpart/$file" + echo '# dummy' > "$dirpart/$file" + done + done +} +])# _AM_OUTPUT_DEPENDENCY_COMMANDS + + +# AM_OUTPUT_DEPENDENCY_COMMANDS +# ----------------------------- +# This macro should only be invoked once -- use via AC_REQUIRE. +# +# This code is only required when automatic dependency tracking +# is enabled. FIXME. This creates each '.P' file that we will +# need in order to bootstrap the dependency handling code. +AC_DEFUN([AM_OUTPUT_DEPENDENCY_COMMANDS], +[AC_CONFIG_COMMANDS([depfiles], + [test x"$AMDEP_TRUE" != x"" || _AM_OUTPUT_DEPENDENCY_COMMANDS], + [AMDEP_TRUE="$AMDEP_TRUE" ac_aux_dir="$ac_aux_dir"]) +]) + +# Do all the work for Automake. -*- Autoconf -*- + +# Copyright (C) 1996-2013 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This macro actually does too much. Some checks are only needed if +# your package does certain things. But this isn't really a big deal. + +dnl Redefine AC_PROG_CC to automatically invoke _AM_PROG_CC_C_O. +m4_define([AC_PROG_CC], +m4_defn([AC_PROG_CC]) +[_AM_PROG_CC_C_O +]) + +# AM_INIT_AUTOMAKE(PACKAGE, VERSION, [NO-DEFINE]) +# AM_INIT_AUTOMAKE([OPTIONS]) +# ----------------------------------------------- +# The call with PACKAGE and VERSION arguments is the old style +# call (pre autoconf-2.50), which is being phased out. PACKAGE +# and VERSION should now be passed to AC_INIT and removed from +# the call to AM_INIT_AUTOMAKE. +# We support both call styles for the transition. After +# the next Automake release, Autoconf can make the AC_INIT +# arguments mandatory, and then we can depend on a new Autoconf +# release and drop the old call support. +AC_DEFUN([AM_INIT_AUTOMAKE], +[AC_PREREQ([2.65])dnl +dnl Autoconf wants to disallow AM_ names. We explicitly allow +dnl the ones we care about. +m4_pattern_allow([^AM_[A-Z]+FLAGS$])dnl +AC_REQUIRE([AM_SET_CURRENT_AUTOMAKE_VERSION])dnl +AC_REQUIRE([AC_PROG_INSTALL])dnl +if test "`cd $srcdir && pwd`" != "`pwd`"; then + # Use -I$(srcdir) only when $(srcdir) != ., so that make's output + # is not polluted with repeated "-I." + AC_SUBST([am__isrc], [' -I$(srcdir)'])_AM_SUBST_NOTMAKE([am__isrc])dnl + # test to see if srcdir already configured + if test -f $srcdir/config.status; then + AC_MSG_ERROR([source directory already configured; run "make distclean" there first]) + fi +fi + +# test whether we have cygpath +if test -z "$CYGPATH_W"; then + if (cygpath --version) >/dev/null 2>/dev/null; then + CYGPATH_W='cygpath -w' + else + CYGPATH_W=echo + fi +fi +AC_SUBST([CYGPATH_W]) + +# Define the identity of the package. +dnl Distinguish between old-style and new-style calls. +m4_ifval([$2], +[AC_DIAGNOSE([obsolete], + [$0: two- and three-arguments forms are deprecated.]) +m4_ifval([$3], [_AM_SET_OPTION([no-define])])dnl + AC_SUBST([PACKAGE], [$1])dnl + AC_SUBST([VERSION], [$2])], +[_AM_SET_OPTIONS([$1])dnl +dnl Diagnose old-style AC_INIT with new-style AM_AUTOMAKE_INIT. +m4_if( + m4_ifdef([AC_PACKAGE_NAME], [ok]):m4_ifdef([AC_PACKAGE_VERSION], [ok]), + [ok:ok],, + [m4_fatal([AC_INIT should be called with package and version arguments])])dnl + AC_SUBST([PACKAGE], ['AC_PACKAGE_TARNAME'])dnl + AC_SUBST([VERSION], ['AC_PACKAGE_VERSION'])])dnl + +_AM_IF_OPTION([no-define],, +[AC_DEFINE_UNQUOTED([PACKAGE], ["$PACKAGE"], [Name of package]) + AC_DEFINE_UNQUOTED([VERSION], ["$VERSION"], [Version number of package])])dnl + +# Some tools Automake needs. +AC_REQUIRE([AM_SANITY_CHECK])dnl +AC_REQUIRE([AC_ARG_PROGRAM])dnl +AM_MISSING_PROG([ACLOCAL], [aclocal-${am__api_version}]) +AM_MISSING_PROG([AUTOCONF], [autoconf]) +AM_MISSING_PROG([AUTOMAKE], [automake-${am__api_version}]) +AM_MISSING_PROG([AUTOHEADER], [autoheader]) +AM_MISSING_PROG([MAKEINFO], [makeinfo]) +AC_REQUIRE([AM_PROG_INSTALL_SH])dnl +AC_REQUIRE([AM_PROG_INSTALL_STRIP])dnl +AC_REQUIRE([AC_PROG_MKDIR_P])dnl +# For better backward compatibility. To be removed once Automake 1.9.x +# dies out for good. For more background, see: +# +# +AC_SUBST([mkdir_p], ['$(MKDIR_P)']) +# We need awk for the "check" target. The system "awk" is bad on +# some platforms. +AC_REQUIRE([AC_PROG_AWK])dnl +AC_REQUIRE([AC_PROG_MAKE_SET])dnl +AC_REQUIRE([AM_SET_LEADING_DOT])dnl +_AM_IF_OPTION([tar-ustar], [_AM_PROG_TAR([ustar])], + [_AM_IF_OPTION([tar-pax], [_AM_PROG_TAR([pax])], + [_AM_PROG_TAR([v7])])]) +_AM_IF_OPTION([no-dependencies],, +[AC_PROVIDE_IFELSE([AC_PROG_CC], + [_AM_DEPENDENCIES([CC])], + [m4_define([AC_PROG_CC], + m4_defn([AC_PROG_CC])[_AM_DEPENDENCIES([CC])])])dnl +AC_PROVIDE_IFELSE([AC_PROG_CXX], + [_AM_DEPENDENCIES([CXX])], + [m4_define([AC_PROG_CXX], + m4_defn([AC_PROG_CXX])[_AM_DEPENDENCIES([CXX])])])dnl +AC_PROVIDE_IFELSE([AC_PROG_OBJC], + [_AM_DEPENDENCIES([OBJC])], + [m4_define([AC_PROG_OBJC], + m4_defn([AC_PROG_OBJC])[_AM_DEPENDENCIES([OBJC])])])dnl +AC_PROVIDE_IFELSE([AC_PROG_OBJCXX], + [_AM_DEPENDENCIES([OBJCXX])], + [m4_define([AC_PROG_OBJCXX], + m4_defn([AC_PROG_OBJCXX])[_AM_DEPENDENCIES([OBJCXX])])])dnl +]) +AC_REQUIRE([AM_SILENT_RULES])dnl +dnl The testsuite driver may need to know about EXEEXT, so add the +dnl 'am__EXEEXT' conditional if _AM_COMPILER_EXEEXT was seen. This +dnl macro is hooked onto _AC_COMPILER_EXEEXT early, see below. +AC_CONFIG_COMMANDS_PRE(dnl +[m4_provide_if([_AM_COMPILER_EXEEXT], + [AM_CONDITIONAL([am__EXEEXT], [test -n "$EXEEXT"])])])dnl + +# POSIX will say in a future version that running "rm -f" with no argument +# is OK; and we want to be able to make that assumption in our Makefile +# recipes. So use an aggressive probe to check that the usage we want is +# actually supported "in the wild" to an acceptable degree. +# See automake bug#10828. +# To make any issue more visible, cause the running configure to be aborted +# by default if the 'rm' program in use doesn't match our expectations; the +# user can still override this though. +if rm -f && rm -fr && rm -rf; then : OK; else + cat >&2 <<'END' +Oops! + +Your 'rm' program seems unable to run without file operands specified +on the command line, even when the '-f' option is present. This is contrary +to the behaviour of most rm programs out there, and not conforming with +the upcoming POSIX standard: + +Please tell bug-automake@gnu.org about your system, including the value +of your $PATH and any error possibly output before this message. This +can help us improve future automake versions. + +END + if test x"$ACCEPT_INFERIOR_RM_PROGRAM" = x"yes"; then + echo 'Configuration will proceed anyway, since you have set the' >&2 + echo 'ACCEPT_INFERIOR_RM_PROGRAM variable to "yes"' >&2 + echo >&2 + else + cat >&2 <<'END' +Aborting the configuration process, to ensure you take notice of the issue. + +You can download and install GNU coreutils to get an 'rm' implementation +that behaves properly: . + +If you want to complete the configuration process using your problematic +'rm' anyway, export the environment variable ACCEPT_INFERIOR_RM_PROGRAM +to "yes", and re-run configure. + +END + AC_MSG_ERROR([Your 'rm' program is bad, sorry.]) + fi +fi]) + +dnl Hook into '_AC_COMPILER_EXEEXT' early to learn its expansion. Do not +dnl add the conditional right here, as _AC_COMPILER_EXEEXT may be further +dnl mangled by Autoconf and run in a shell conditional statement. +m4_define([_AC_COMPILER_EXEEXT], +m4_defn([_AC_COMPILER_EXEEXT])[m4_provide([_AM_COMPILER_EXEEXT])]) + +# When config.status generates a header, we must update the stamp-h file. +# This file resides in the same directory as the config header +# that is generated. The stamp files are numbered to have different names. + +# Autoconf calls _AC_AM_CONFIG_HEADER_HOOK (when defined) in the +# loop where config.status creates the headers, so we can generate +# our stamp files there. +AC_DEFUN([_AC_AM_CONFIG_HEADER_HOOK], +[# Compute $1's index in $config_headers. +_am_arg=$1 +_am_stamp_count=1 +for _am_header in $config_headers :; do + case $_am_header in + $_am_arg | $_am_arg:* ) + break ;; + * ) + _am_stamp_count=`expr $_am_stamp_count + 1` ;; + esac +done +echo "timestamp for $_am_arg" >`AS_DIRNAME(["$_am_arg"])`/stamp-h[]$_am_stamp_count]) + +# Copyright (C) 2001-2013 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# AM_PROG_INSTALL_SH +# ------------------ +# Define $install_sh. +AC_DEFUN([AM_PROG_INSTALL_SH], +[AC_REQUIRE([AM_AUX_DIR_EXPAND])dnl +if test x"${install_sh}" != xset; then + case $am_aux_dir in + *\ * | *\ *) + install_sh="\${SHELL} '$am_aux_dir/install-sh'" ;; + *) + install_sh="\${SHELL} $am_aux_dir/install-sh" + esac +fi +AC_SUBST([install_sh])]) + +# Copyright (C) 2003-2013 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# Check whether the underlying file-system supports filenames +# with a leading dot. For instance MS-DOS doesn't. +AC_DEFUN([AM_SET_LEADING_DOT], +[rm -rf .tst 2>/dev/null +mkdir .tst 2>/dev/null +if test -d .tst; then + am__leading_dot=. +else + am__leading_dot=_ +fi +rmdir .tst 2>/dev/null +AC_SUBST([am__leading_dot])]) + +# Check to see how 'make' treats includes. -*- Autoconf -*- + +# Copyright (C) 2001-2013 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# AM_MAKE_INCLUDE() +# ----------------- +# Check to see how make treats includes. +AC_DEFUN([AM_MAKE_INCLUDE], +[am_make=${MAKE-make} +cat > confinc << 'END' +am__doit: + @echo this is the am__doit target +.PHONY: am__doit +END +# If we don't find an include directive, just comment out the code. +AC_MSG_CHECKING([for style of include used by $am_make]) +am__include="#" +am__quote= +_am_result=none +# First try GNU make style include. +echo "include confinc" > confmf +# Ignore all kinds of additional output from 'make'. +case `$am_make -s -f confmf 2> /dev/null` in #( +*the\ am__doit\ target*) + am__include=include + am__quote= + _am_result=GNU + ;; +esac +# Now try BSD make style include. +if test "$am__include" = "#"; then + echo '.include "confinc"' > confmf + case `$am_make -s -f confmf 2> /dev/null` in #( + *the\ am__doit\ target*) + am__include=.include + am__quote="\"" + _am_result=BSD + ;; + esac +fi +AC_SUBST([am__include]) +AC_SUBST([am__quote]) +AC_MSG_RESULT([$_am_result]) +rm -f confinc confmf +]) + +# Fake the existence of programs that GNU maintainers use. -*- Autoconf -*- + +# Copyright (C) 1997-2013 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# AM_MISSING_PROG(NAME, PROGRAM) +# ------------------------------ +AC_DEFUN([AM_MISSING_PROG], +[AC_REQUIRE([AM_MISSING_HAS_RUN]) +$1=${$1-"${am_missing_run}$2"} +AC_SUBST($1)]) + +# AM_MISSING_HAS_RUN +# ------------------ +# Define MISSING if not defined so far and test if it is modern enough. +# If it is, set am_missing_run to use it, otherwise, to nothing. +AC_DEFUN([AM_MISSING_HAS_RUN], +[AC_REQUIRE([AM_AUX_DIR_EXPAND])dnl +AC_REQUIRE_AUX_FILE([missing])dnl +if test x"${MISSING+set}" != xset; then + case $am_aux_dir in + *\ * | *\ *) + MISSING="\${SHELL} \"$am_aux_dir/missing\"" ;; + *) + MISSING="\${SHELL} $am_aux_dir/missing" ;; + esac +fi +# Use eval to expand $SHELL +if eval "$MISSING --is-lightweight"; then + am_missing_run="$MISSING " +else + am_missing_run= + AC_MSG_WARN(['missing' script is too old or missing]) +fi +]) + +# Helper functions for option handling. -*- Autoconf -*- + +# Copyright (C) 2001-2013 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# _AM_MANGLE_OPTION(NAME) +# ----------------------- +AC_DEFUN([_AM_MANGLE_OPTION], +[[_AM_OPTION_]m4_bpatsubst($1, [[^a-zA-Z0-9_]], [_])]) + +# _AM_SET_OPTION(NAME) +# -------------------- +# Set option NAME. Presently that only means defining a flag for this option. +AC_DEFUN([_AM_SET_OPTION], +[m4_define(_AM_MANGLE_OPTION([$1]), [1])]) + +# _AM_SET_OPTIONS(OPTIONS) +# ------------------------ +# OPTIONS is a space-separated list of Automake options. +AC_DEFUN([_AM_SET_OPTIONS], +[m4_foreach_w([_AM_Option], [$1], [_AM_SET_OPTION(_AM_Option)])]) + +# _AM_IF_OPTION(OPTION, IF-SET, [IF-NOT-SET]) +# ------------------------------------------- +# Execute IF-SET if OPTION is set, IF-NOT-SET otherwise. +AC_DEFUN([_AM_IF_OPTION], +[m4_ifset(_AM_MANGLE_OPTION([$1]), [$2], [$3])]) + +# Copyright (C) 1999-2013 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# _AM_PROG_CC_C_O +# --------------- +# Like AC_PROG_CC_C_O, but changed for automake. We rewrite AC_PROG_CC +# to automatically call this. +AC_DEFUN([_AM_PROG_CC_C_O], +[AC_REQUIRE([AM_AUX_DIR_EXPAND])dnl +AC_REQUIRE_AUX_FILE([compile])dnl +AC_LANG_PUSH([C])dnl +AC_CACHE_CHECK( + [whether $CC understands -c and -o together], + [am_cv_prog_cc_c_o], + [AC_LANG_CONFTEST([AC_LANG_PROGRAM([])]) + # Make sure it works both with $CC and with simple cc. + # Following AC_PROG_CC_C_O, we do the test twice because some + # compilers refuse to overwrite an existing .o file with -o, + # though they will create one. + am_cv_prog_cc_c_o=yes + for am_i in 1 2; do + if AM_RUN_LOG([$CC -c conftest.$ac_ext -o conftest2.$ac_objext]) \ + && test -f conftest2.$ac_objext; then + : OK + else + am_cv_prog_cc_c_o=no + break + fi + done + rm -f core conftest* + unset am_i]) +if test "$am_cv_prog_cc_c_o" != yes; then + # Losing compiler, so override with the script. + # FIXME: It is wrong to rewrite CC. + # But if we don't then we get into trouble of one sort or another. + # A longer-term fix would be to have automake use am__CC in this case, + # and then we could set am__CC="\$(top_srcdir)/compile \$(CC)" + CC="$am_aux_dir/compile $CC" +fi +AC_LANG_POP([C])]) + +# For backward compatibility. +AC_DEFUN_ONCE([AM_PROG_CC_C_O], [AC_REQUIRE([AC_PROG_CC])]) + +# Copyright (C) 2001-2013 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# AM_RUN_LOG(COMMAND) +# ------------------- +# Run COMMAND, save the exit status in ac_status, and log it. +# (This has been adapted from Autoconf's _AC_RUN_LOG macro.) +AC_DEFUN([AM_RUN_LOG], +[{ echo "$as_me:$LINENO: $1" >&AS_MESSAGE_LOG_FD + ($1) >&AS_MESSAGE_LOG_FD 2>&AS_MESSAGE_LOG_FD + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&AS_MESSAGE_LOG_FD + (exit $ac_status); }]) + +# Check to make sure that the build environment is sane. -*- Autoconf -*- + +# Copyright (C) 1996-2013 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# AM_SANITY_CHECK +# --------------- +AC_DEFUN([AM_SANITY_CHECK], +[AC_MSG_CHECKING([whether build environment is sane]) +# Reject unsafe characters in $srcdir or the absolute working directory +# name. Accept space and tab only in the latter. +am_lf=' +' +case `pwd` in + *[[\\\"\#\$\&\'\`$am_lf]]*) + AC_MSG_ERROR([unsafe absolute working directory name]);; +esac +case $srcdir in + *[[\\\"\#\$\&\'\`$am_lf\ \ ]]*) + AC_MSG_ERROR([unsafe srcdir value: '$srcdir']);; +esac + +# Do 'set' in a subshell so we don't clobber the current shell's +# arguments. Must try -L first in case configure is actually a +# symlink; some systems play weird games with the mod time of symlinks +# (eg FreeBSD returns the mod time of the symlink's containing +# directory). +if ( + am_has_slept=no + for am_try in 1 2; do + echo "timestamp, slept: $am_has_slept" > conftest.file + set X `ls -Lt "$srcdir/configure" conftest.file 2> /dev/null` + if test "$[*]" = "X"; then + # -L didn't work. + set X `ls -t "$srcdir/configure" conftest.file` + fi + if test "$[*]" != "X $srcdir/configure conftest.file" \ + && test "$[*]" != "X conftest.file $srcdir/configure"; then + + # If neither matched, then we have a broken ls. This can happen + # if, for instance, CONFIG_SHELL is bash and it inherits a + # broken ls alias from the environment. This has actually + # happened. Such a system could not be considered "sane". + AC_MSG_ERROR([ls -t appears to fail. Make sure there is not a broken + alias in your environment]) + fi + if test "$[2]" = conftest.file || test $am_try -eq 2; then + break + fi + # Just in case. + sleep 1 + am_has_slept=yes + done + test "$[2]" = conftest.file + ) +then + # Ok. + : +else + AC_MSG_ERROR([newly created file is older than distributed files! +Check your system clock]) +fi +AC_MSG_RESULT([yes]) +# If we didn't sleep, we still need to ensure time stamps of config.status and +# generated files are strictly newer. +am_sleep_pid= +if grep 'slept: no' conftest.file >/dev/null 2>&1; then + ( sleep 1 ) & + am_sleep_pid=$! +fi +AC_CONFIG_COMMANDS_PRE( + [AC_MSG_CHECKING([that generated files are newer than configure]) + if test -n "$am_sleep_pid"; then + # Hide warnings about reused PIDs. + wait $am_sleep_pid 2>/dev/null + fi + AC_MSG_RESULT([done])]) +rm -f conftest.file +]) + +# Copyright (C) 2009-2013 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# AM_SILENT_RULES([DEFAULT]) +# -------------------------- +# Enable less verbose build rules; with the default set to DEFAULT +# ("yes" being less verbose, "no" or empty being verbose). +AC_DEFUN([AM_SILENT_RULES], +[AC_ARG_ENABLE([silent-rules], [dnl +AS_HELP_STRING( + [--enable-silent-rules], + [less verbose build output (undo: "make V=1")]) +AS_HELP_STRING( + [--disable-silent-rules], + [verbose build output (undo: "make V=0")])dnl +]) +case $enable_silent_rules in @%:@ ((( + yes) AM_DEFAULT_VERBOSITY=0;; + no) AM_DEFAULT_VERBOSITY=1;; + *) AM_DEFAULT_VERBOSITY=m4_if([$1], [yes], [0], [1]);; +esac +dnl +dnl A few 'make' implementations (e.g., NonStop OS and NextStep) +dnl do not support nested variable expansions. +dnl See automake bug#9928 and bug#10237. +am_make=${MAKE-make} +AC_CACHE_CHECK([whether $am_make supports nested variables], + [am_cv_make_support_nested_variables], + [if AS_ECHO([['TRUE=$(BAR$(V)) +BAR0=false +BAR1=true +V=1 +am__doit: + @$(TRUE) +.PHONY: am__doit']]) | $am_make -f - >/dev/null 2>&1; then + am_cv_make_support_nested_variables=yes +else + am_cv_make_support_nested_variables=no +fi]) +if test $am_cv_make_support_nested_variables = yes; then + dnl Using '$V' instead of '$(V)' breaks IRIX make. + AM_V='$(V)' + AM_DEFAULT_V='$(AM_DEFAULT_VERBOSITY)' +else + AM_V=$AM_DEFAULT_VERBOSITY + AM_DEFAULT_V=$AM_DEFAULT_VERBOSITY +fi +AC_SUBST([AM_V])dnl +AM_SUBST_NOTMAKE([AM_V])dnl +AC_SUBST([AM_DEFAULT_V])dnl +AM_SUBST_NOTMAKE([AM_DEFAULT_V])dnl +AC_SUBST([AM_DEFAULT_VERBOSITY])dnl +AM_BACKSLASH='\' +AC_SUBST([AM_BACKSLASH])dnl +_AM_SUBST_NOTMAKE([AM_BACKSLASH])dnl +]) + +# Copyright (C) 2001-2013 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# AM_PROG_INSTALL_STRIP +# --------------------- +# One issue with vendor 'install' (even GNU) is that you can't +# specify the program used to strip binaries. This is especially +# annoying in cross-compiling environments, where the build's strip +# is unlikely to handle the host's binaries. +# Fortunately install-sh will honor a STRIPPROG variable, so we +# always use install-sh in "make install-strip", and initialize +# STRIPPROG with the value of the STRIP variable (set by the user). +AC_DEFUN([AM_PROG_INSTALL_STRIP], +[AC_REQUIRE([AM_PROG_INSTALL_SH])dnl +# Installed binaries are usually stripped using 'strip' when the user +# run "make install-strip". However 'strip' might not be the right +# tool to use in cross-compilation environments, therefore Automake +# will honor the 'STRIP' environment variable to overrule this program. +dnl Don't test for $cross_compiling = yes, because it might be 'maybe'. +if test "$cross_compiling" != no; then + AC_CHECK_TOOL([STRIP], [strip], :) +fi +INSTALL_STRIP_PROGRAM="\$(install_sh) -c -s" +AC_SUBST([INSTALL_STRIP_PROGRAM])]) + +# Copyright (C) 2006-2013 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# _AM_SUBST_NOTMAKE(VARIABLE) +# --------------------------- +# Prevent Automake from outputting VARIABLE = @VARIABLE@ in Makefile.in. +# This macro is traced by Automake. +AC_DEFUN([_AM_SUBST_NOTMAKE]) + +# AM_SUBST_NOTMAKE(VARIABLE) +# -------------------------- +# Public sister of _AM_SUBST_NOTMAKE. +AC_DEFUN([AM_SUBST_NOTMAKE], [_AM_SUBST_NOTMAKE($@)]) + +# Check how to create a tarball. -*- Autoconf -*- + +# Copyright (C) 2004-2013 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# _AM_PROG_TAR(FORMAT) +# -------------------- +# Check how to create a tarball in format FORMAT. +# FORMAT should be one of 'v7', 'ustar', or 'pax'. +# +# Substitute a variable $(am__tar) that is a command +# writing to stdout a FORMAT-tarball containing the directory +# $tardir. +# tardir=directory && $(am__tar) > result.tar +# +# Substitute a variable $(am__untar) that extract such +# a tarball read from stdin. +# $(am__untar) < result.tar +# +AC_DEFUN([_AM_PROG_TAR], +[# Always define AMTAR for backward compatibility. Yes, it's still used +# in the wild :-( We should find a proper way to deprecate it ... +AC_SUBST([AMTAR], ['$${TAR-tar}']) + +# We'll loop over all known methods to create a tar archive until one works. +_am_tools='gnutar m4_if([$1], [ustar], [plaintar]) pax cpio none' + +m4_if([$1], [v7], + [am__tar='$${TAR-tar} chof - "$$tardir"' am__untar='$${TAR-tar} xf -'], + + [m4_case([$1], + [ustar], + [# The POSIX 1988 'ustar' format is defined with fixed-size fields. + # There is notably a 21 bits limit for the UID and the GID. In fact, + # the 'pax' utility can hang on bigger UID/GID (see automake bug#8343 + # and bug#13588). + am_max_uid=2097151 # 2^21 - 1 + am_max_gid=$am_max_uid + # The $UID and $GID variables are not portable, so we need to resort + # to the POSIX-mandated id(1) utility. Errors in the 'id' calls + # below are definitely unexpected, so allow the users to see them + # (that is, avoid stderr redirection). + am_uid=`id -u || echo unknown` + am_gid=`id -g || echo unknown` + AC_MSG_CHECKING([whether UID '$am_uid' is supported by ustar format]) + if test $am_uid -le $am_max_uid; then + AC_MSG_RESULT([yes]) + else + AC_MSG_RESULT([no]) + _am_tools=none + fi + AC_MSG_CHECKING([whether GID '$am_gid' is supported by ustar format]) + if test $am_gid -le $am_max_gid; then + AC_MSG_RESULT([yes]) + else + AC_MSG_RESULT([no]) + _am_tools=none + fi], + + [pax], + [], + + [m4_fatal([Unknown tar format])]) + + AC_MSG_CHECKING([how to create a $1 tar archive]) + + # Go ahead even if we have the value already cached. We do so because we + # need to set the values for the 'am__tar' and 'am__untar' variables. + _am_tools=${am_cv_prog_tar_$1-$_am_tools} + + for _am_tool in $_am_tools; do + case $_am_tool in + gnutar) + for _am_tar in tar gnutar gtar; do + AM_RUN_LOG([$_am_tar --version]) && break + done + am__tar="$_am_tar --format=m4_if([$1], [pax], [posix], [$1]) -chf - "'"$$tardir"' + am__tar_="$_am_tar --format=m4_if([$1], [pax], [posix], [$1]) -chf - "'"$tardir"' + am__untar="$_am_tar -xf -" + ;; + plaintar) + # Must skip GNU tar: if it does not support --format= it doesn't create + # ustar tarball either. + (tar --version) >/dev/null 2>&1 && continue + am__tar='tar chf - "$$tardir"' + am__tar_='tar chf - "$tardir"' + am__untar='tar xf -' + ;; + pax) + am__tar='pax -L -x $1 -w "$$tardir"' + am__tar_='pax -L -x $1 -w "$tardir"' + am__untar='pax -r' + ;; + cpio) + am__tar='find "$$tardir" -print | cpio -o -H $1 -L' + am__tar_='find "$tardir" -print | cpio -o -H $1 -L' + am__untar='cpio -i -H $1 -d' + ;; + none) + am__tar=false + am__tar_=false + am__untar=false + ;; + esac + + # If the value was cached, stop now. We just wanted to have am__tar + # and am__untar set. + test -n "${am_cv_prog_tar_$1}" && break + + # tar/untar a dummy directory, and stop if the command works. + rm -rf conftest.dir + mkdir conftest.dir + echo GrepMe > conftest.dir/file + AM_RUN_LOG([tardir=conftest.dir && eval $am__tar_ >conftest.tar]) + rm -rf conftest.dir + if test -s conftest.tar; then + AM_RUN_LOG([$am__untar /dev/null 2>&1 && break + fi + done + rm -rf conftest.dir + + AC_CACHE_VAL([am_cv_prog_tar_$1], [am_cv_prog_tar_$1=$_am_tool]) + AC_MSG_RESULT([$am_cv_prog_tar_$1])]) + +AC_SUBST([am__tar]) +AC_SUBST([am__untar]) +]) # _AM_PROG_TAR + +m4_include([m4/ax_add_am_macro.m4]) +m4_include([m4/ax_am_jobserver.m4]) +m4_include([m4/ax_am_macros.m4]) +m4_include([m4/ax_append_compile_flags.m4]) +m4_include([m4/ax_append_flag.m4]) +m4_include([m4/ax_append_to_file.m4]) +m4_include([m4/ax_check_compile_flag.m4]) +m4_include([m4/ax_check_link_flag.m4]) +m4_include([m4/ax_count_cpus.m4]) +m4_include([m4/ax_create_generic_config.m4]) +m4_include([m4/ax_debug.m4]) +m4_include([m4/ax_file_escapes.m4]) +m4_include([m4/ax_harden_compiler_flags.m4]) +m4_include([m4/ax_print_to_file.m4]) +m4_include([m4/ax_pthread.m4]) +m4_include([m4/ax_tls.m4]) +m4_include([m4/ax_vcs_checkout.m4]) +m4_include([m4/hexversion.m4]) +m4_include([m4/lib_socket_nsl.m4]) +m4_include([m4/libtool.m4]) +m4_include([m4/ltoptions.m4]) +m4_include([m4/ltsugar.m4]) +m4_include([m4/ltversion.m4]) +m4_include([m4/lt~obsolete.m4]) +m4_include([m4/visibility.m4]) +m4_include([m4/wolfssl_darwin_clang.m4]) diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/compile b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/compile new file mode 100644 index 0000000..531136b --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/compile @@ -0,0 +1,347 @@ +#! /bin/sh +# Wrapper for compilers which do not understand '-c -o'. + +scriptversion=2012-10-14.11; # UTC + +# Copyright (C) 1999-2013 Free Software Foundation, Inc. +# Written by Tom Tromey . +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that program. + +# This file is maintained in Automake, please report +# bugs to or send patches to +# . + +nl=' +' + +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent tools from complaining about whitespace usage. +IFS=" "" $nl" + +file_conv= + +# func_file_conv build_file lazy +# Convert a $build file to $host form and store it in $file +# Currently only supports Windows hosts. If the determined conversion +# type is listed in (the comma separated) LAZY, no conversion will +# take place. +func_file_conv () +{ + file=$1 + case $file in + / | /[!/]*) # absolute file, and not a UNC file + if test -z "$file_conv"; then + # lazily determine how to convert abs files + case `uname -s` in + MINGW*) + file_conv=mingw + ;; + CYGWIN*) + file_conv=cygwin + ;; + *) + file_conv=wine + ;; + esac + fi + case $file_conv/,$2, in + *,$file_conv,*) + ;; + mingw/*) + file=`cmd //C echo "$file " | sed -e 's/"\(.*\) " *$/\1/'` + ;; + cygwin/*) + file=`cygpath -m "$file" || echo "$file"` + ;; + wine/*) + file=`winepath -w "$file" || echo "$file"` + ;; + esac + ;; + esac +} + +# func_cl_dashL linkdir +# Make cl look for libraries in LINKDIR +func_cl_dashL () +{ + func_file_conv "$1" + if test -z "$lib_path"; then + lib_path=$file + else + lib_path="$lib_path;$file" + fi + linker_opts="$linker_opts -LIBPATH:$file" +} + +# func_cl_dashl library +# Do a library search-path lookup for cl +func_cl_dashl () +{ + lib=$1 + found=no + save_IFS=$IFS + IFS=';' + for dir in $lib_path $LIB + do + IFS=$save_IFS + if $shared && test -f "$dir/$lib.dll.lib"; then + found=yes + lib=$dir/$lib.dll.lib + break + fi + if test -f "$dir/$lib.lib"; then + found=yes + lib=$dir/$lib.lib + break + fi + if test -f "$dir/lib$lib.a"; then + found=yes + lib=$dir/lib$lib.a + break + fi + done + IFS=$save_IFS + + if test "$found" != yes; then + lib=$lib.lib + fi +} + +# func_cl_wrapper cl arg... +# Adjust compile command to suit cl +func_cl_wrapper () +{ + # Assume a capable shell + lib_path= + shared=: + linker_opts= + for arg + do + if test -n "$eat"; then + eat= + else + case $1 in + -o) + # configure might choose to run compile as 'compile cc -o foo foo.c'. + eat=1 + case $2 in + *.o | *.[oO][bB][jJ]) + func_file_conv "$2" + set x "$@" -Fo"$file" + shift + ;; + *) + func_file_conv "$2" + set x "$@" -Fe"$file" + shift + ;; + esac + ;; + -I) + eat=1 + func_file_conv "$2" mingw + set x "$@" -I"$file" + shift + ;; + -I*) + func_file_conv "${1#-I}" mingw + set x "$@" -I"$file" + shift + ;; + -l) + eat=1 + func_cl_dashl "$2" + set x "$@" "$lib" + shift + ;; + -l*) + func_cl_dashl "${1#-l}" + set x "$@" "$lib" + shift + ;; + -L) + eat=1 + func_cl_dashL "$2" + ;; + -L*) + func_cl_dashL "${1#-L}" + ;; + -static) + shared=false + ;; + -Wl,*) + arg=${1#-Wl,} + save_ifs="$IFS"; IFS=',' + for flag in $arg; do + IFS="$save_ifs" + linker_opts="$linker_opts $flag" + done + IFS="$save_ifs" + ;; + -Xlinker) + eat=1 + linker_opts="$linker_opts $2" + ;; + -*) + set x "$@" "$1" + shift + ;; + *.cc | *.CC | *.cxx | *.CXX | *.[cC]++) + func_file_conv "$1" + set x "$@" -Tp"$file" + shift + ;; + *.c | *.cpp | *.CPP | *.lib | *.LIB | *.Lib | *.OBJ | *.obj | *.[oO]) + func_file_conv "$1" mingw + set x "$@" "$file" + shift + ;; + *) + set x "$@" "$1" + shift + ;; + esac + fi + shift + done + if test -n "$linker_opts"; then + linker_opts="-link$linker_opts" + fi + exec "$@" $linker_opts + exit 1 +} + +eat= + +case $1 in + '') + echo "$0: No command. Try '$0 --help' for more information." 1>&2 + exit 1; + ;; + -h | --h*) + cat <<\EOF +Usage: compile [--help] [--version] PROGRAM [ARGS] + +Wrapper for compilers which do not understand '-c -o'. +Remove '-o dest.o' from ARGS, run PROGRAM with the remaining +arguments, and rename the output as expected. + +If you are trying to build a whole package this is not the +right script to run: please start by reading the file 'INSTALL'. + +Report bugs to . +EOF + exit $? + ;; + -v | --v*) + echo "compile $scriptversion" + exit $? + ;; + cl | *[/\\]cl | cl.exe | *[/\\]cl.exe ) + func_cl_wrapper "$@" # Doesn't return... + ;; +esac + +ofile= +cfile= + +for arg +do + if test -n "$eat"; then + eat= + else + case $1 in + -o) + # configure might choose to run compile as 'compile cc -o foo foo.c'. + # So we strip '-o arg' only if arg is an object. + eat=1 + case $2 in + *.o | *.obj) + ofile=$2 + ;; + *) + set x "$@" -o "$2" + shift + ;; + esac + ;; + *.c) + cfile=$1 + set x "$@" "$1" + shift + ;; + *) + set x "$@" "$1" + shift + ;; + esac + fi + shift +done + +if test -z "$ofile" || test -z "$cfile"; then + # If no '-o' option was seen then we might have been invoked from a + # pattern rule where we don't need one. That is ok -- this is a + # normal compilation that the losing compiler can handle. If no + # '.c' file was seen then we are probably linking. That is also + # ok. + exec "$@" +fi + +# Name of file we expect compiler to create. +cofile=`echo "$cfile" | sed 's|^.*[\\/]||; s|^[a-zA-Z]:||; s/\.c$/.o/'` + +# Create the lock directory. +# Note: use '[/\\:.-]' here to ensure that we don't use the same name +# that we are using for the .o file. Also, base the name on the expected +# object file name, since that is what matters with a parallel build. +lockdir=`echo "$cofile" | sed -e 's|[/\\:.-]|_|g'`.d +while true; do + if mkdir "$lockdir" >/dev/null 2>&1; then + break + fi + sleep 1 +done +# FIXME: race condition here if user kills between mkdir and trap. +trap "rmdir '$lockdir'; exit 1" 1 2 15 + +# Run the compile. +"$@" +ret=$? + +if test -f "$cofile"; then + test "$cofile" = "$ofile" || mv "$cofile" "$ofile" +elif test -f "${cofile}bj"; then + test "${cofile}bj" = "$ofile" || mv "${cofile}bj" "$ofile" +fi + +rmdir "$lockdir" +exit $ret + +# Local Variables: +# mode: shell-script +# sh-indentation: 2 +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "scriptversion=" +# time-stamp-format: "%:y-%02m-%02d.%02H" +# time-stamp-time-zone: "UTC" +# time-stamp-end: "; # UTC" +# End: diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/config.guess b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/config.guess new file mode 100644 index 0000000..9afd676 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/config.guess @@ -0,0 +1,1568 @@ +#! /bin/sh +# Attempt to guess a canonical system name. +# Copyright 1992-2013 Free Software Foundation, Inc. + +timestamp='2013-11-29' + +# This file is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see . +# +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that +# program. This Exception is an additional permission under section 7 +# of the GNU General Public License, version 3 ("GPLv3"). +# +# Originally written by Per Bothner. +# +# You can get the latest version of this script from: +# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.guess;hb=HEAD +# +# Please send patches with a ChangeLog entry to config-patches@gnu.org. + + +me=`echo "$0" | sed -e 's,.*/,,'` + +usage="\ +Usage: $0 [OPTION] + +Output the configuration name of the system \`$me' is run on. + +Operation modes: + -h, --help print this help, then exit + -t, --time-stamp print date of last modification, then exit + -v, --version print version number, then exit + +Report bugs and patches to ." + +version="\ +GNU config.guess ($timestamp) + +Originally written by Per Bothner. +Copyright 1992-2013 Free Software Foundation, Inc. + +This is free software; see the source for copying conditions. There is NO +warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." + +help=" +Try \`$me --help' for more information." + +# Parse command line +while test $# -gt 0 ; do + case $1 in + --time-stamp | --time* | -t ) + echo "$timestamp" ; exit ;; + --version | -v ) + echo "$version" ; exit ;; + --help | --h* | -h ) + echo "$usage"; exit ;; + -- ) # Stop option processing + shift; break ;; + - ) # Use stdin as input. + break ;; + -* ) + echo "$me: invalid option $1$help" >&2 + exit 1 ;; + * ) + break ;; + esac +done + +if test $# != 0; then + echo "$me: too many arguments$help" >&2 + exit 1 +fi + +trap 'exit 1' 1 2 15 + +# CC_FOR_BUILD -- compiler used by this script. Note that the use of a +# compiler to aid in system detection is discouraged as it requires +# temporary files to be created and, as you can see below, it is a +# headache to deal with in a portable fashion. + +# Historically, `CC_FOR_BUILD' used to be named `HOST_CC'. We still +# use `HOST_CC' if defined, but it is deprecated. + +# Portable tmp directory creation inspired by the Autoconf team. + +set_cc_for_build=' +trap "exitcode=\$?; (rm -f \$tmpfiles 2>/dev/null; rmdir \$tmp 2>/dev/null) && exit \$exitcode" 0 ; +trap "rm -f \$tmpfiles 2>/dev/null; rmdir \$tmp 2>/dev/null; exit 1" 1 2 13 15 ; +: ${TMPDIR=/tmp} ; + { tmp=`(umask 077 && mktemp -d "$TMPDIR/cgXXXXXX") 2>/dev/null` && test -n "$tmp" && test -d "$tmp" ; } || + { test -n "$RANDOM" && tmp=$TMPDIR/cg$$-$RANDOM && (umask 077 && mkdir $tmp) ; } || + { tmp=$TMPDIR/cg-$$ && (umask 077 && mkdir $tmp) && echo "Warning: creating insecure temp directory" >&2 ; } || + { echo "$me: cannot create a temporary directory in $TMPDIR" >&2 ; exit 1 ; } ; +dummy=$tmp/dummy ; +tmpfiles="$dummy.c $dummy.o $dummy.rel $dummy" ; +case $CC_FOR_BUILD,$HOST_CC,$CC in + ,,) echo "int x;" > $dummy.c ; + for c in cc gcc c89 c99 ; do + if ($c -c -o $dummy.o $dummy.c) >/dev/null 2>&1 ; then + CC_FOR_BUILD="$c"; break ; + fi ; + done ; + if test x"$CC_FOR_BUILD" = x ; then + CC_FOR_BUILD=no_compiler_found ; + fi + ;; + ,,*) CC_FOR_BUILD=$CC ;; + ,*,*) CC_FOR_BUILD=$HOST_CC ;; +esac ; set_cc_for_build= ;' + +# This is needed to find uname on a Pyramid OSx when run in the BSD universe. +# (ghazi@noc.rutgers.edu 1994-08-24) +if (test -f /.attbin/uname) >/dev/null 2>&1 ; then + PATH=$PATH:/.attbin ; export PATH +fi + +UNAME_MACHINE=`(uname -m) 2>/dev/null` || UNAME_MACHINE=unknown +UNAME_RELEASE=`(uname -r) 2>/dev/null` || UNAME_RELEASE=unknown +UNAME_SYSTEM=`(uname -s) 2>/dev/null` || UNAME_SYSTEM=unknown +UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown + +case "${UNAME_SYSTEM}" in +Linux|GNU|GNU/*) + # If the system lacks a compiler, then just pick glibc. + # We could probably try harder. + LIBC=gnu + + eval $set_cc_for_build + cat <<-EOF > $dummy.c + #include + #if defined(__UCLIBC__) + LIBC=uclibc + #elif defined(__dietlibc__) + LIBC=dietlibc + #else + LIBC=gnu + #endif + EOF + eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC'` + ;; +esac + +# Note: order is significant - the case branches are not exclusive. + +case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in + *:NetBSD:*:*) + # NetBSD (nbsd) targets should (where applicable) match one or + # more of the tuples: *-*-netbsdelf*, *-*-netbsdaout*, + # *-*-netbsdecoff* and *-*-netbsd*. For targets that recently + # switched to ELF, *-*-netbsd* would select the old + # object file format. This provides both forward + # compatibility and a consistent mechanism for selecting the + # object file format. + # + # Note: NetBSD doesn't particularly care about the vendor + # portion of the name. We always set it to "unknown". + sysctl="sysctl -n hw.machine_arch" + UNAME_MACHINE_ARCH=`(/sbin/$sysctl 2>/dev/null || \ + /usr/sbin/$sysctl 2>/dev/null || echo unknown)` + case "${UNAME_MACHINE_ARCH}" in + armeb) machine=armeb-unknown ;; + arm*) machine=arm-unknown ;; + sh3el) machine=shl-unknown ;; + sh3eb) machine=sh-unknown ;; + sh5el) machine=sh5le-unknown ;; + *) machine=${UNAME_MACHINE_ARCH}-unknown ;; + esac + # The Operating System including object format, if it has switched + # to ELF recently, or will in the future. + case "${UNAME_MACHINE_ARCH}" in + arm*|i386|m68k|ns32k|sh3*|sparc|vax) + eval $set_cc_for_build + if echo __ELF__ | $CC_FOR_BUILD -E - 2>/dev/null \ + | grep -q __ELF__ + then + # Once all utilities can be ECOFF (netbsdecoff) or a.out (netbsdaout). + # Return netbsd for either. FIX? + os=netbsd + else + os=netbsdelf + fi + ;; + *) + os=netbsd + ;; + esac + # The OS release + # Debian GNU/NetBSD machines have a different userland, and + # thus, need a distinct triplet. However, they do not need + # kernel version information, so it can be replaced with a + # suitable tag, in the style of linux-gnu. + case "${UNAME_VERSION}" in + Debian*) + release='-gnu' + ;; + *) + release=`echo ${UNAME_RELEASE}|sed -e 's/[-_].*/\./'` + ;; + esac + # Since CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM: + # contains redundant information, the shorter form: + # CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM is used. + echo "${machine}-${os}${release}" + exit ;; + *:Bitrig:*:*) + UNAME_MACHINE_ARCH=`arch | sed 's/Bitrig.//'` + echo ${UNAME_MACHINE_ARCH}-unknown-bitrig${UNAME_RELEASE} + exit ;; + *:OpenBSD:*:*) + UNAME_MACHINE_ARCH=`arch | sed 's/OpenBSD.//'` + echo ${UNAME_MACHINE_ARCH}-unknown-openbsd${UNAME_RELEASE} + exit ;; + *:ekkoBSD:*:*) + echo ${UNAME_MACHINE}-unknown-ekkobsd${UNAME_RELEASE} + exit ;; + *:SolidBSD:*:*) + echo ${UNAME_MACHINE}-unknown-solidbsd${UNAME_RELEASE} + exit ;; + macppc:MirBSD:*:*) + echo powerpc-unknown-mirbsd${UNAME_RELEASE} + exit ;; + *:MirBSD:*:*) + echo ${UNAME_MACHINE}-unknown-mirbsd${UNAME_RELEASE} + exit ;; + alpha:OSF1:*:*) + case $UNAME_RELEASE in + *4.0) + UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $3}'` + ;; + *5.*) + UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $4}'` + ;; + esac + # According to Compaq, /usr/sbin/psrinfo has been available on + # OSF/1 and Tru64 systems produced since 1995. I hope that + # covers most systems running today. This code pipes the CPU + # types through head -n 1, so we only detect the type of CPU 0. + ALPHA_CPU_TYPE=`/usr/sbin/psrinfo -v | sed -n -e 's/^ The alpha \(.*\) processor.*$/\1/p' | head -n 1` + case "$ALPHA_CPU_TYPE" in + "EV4 (21064)") + UNAME_MACHINE="alpha" ;; + "EV4.5 (21064)") + UNAME_MACHINE="alpha" ;; + "LCA4 (21066/21068)") + UNAME_MACHINE="alpha" ;; + "EV5 (21164)") + UNAME_MACHINE="alphaev5" ;; + "EV5.6 (21164A)") + UNAME_MACHINE="alphaev56" ;; + "EV5.6 (21164PC)") + UNAME_MACHINE="alphapca56" ;; + "EV5.7 (21164PC)") + UNAME_MACHINE="alphapca57" ;; + "EV6 (21264)") + UNAME_MACHINE="alphaev6" ;; + "EV6.7 (21264A)") + UNAME_MACHINE="alphaev67" ;; + "EV6.8CB (21264C)") + UNAME_MACHINE="alphaev68" ;; + "EV6.8AL (21264B)") + UNAME_MACHINE="alphaev68" ;; + "EV6.8CX (21264D)") + UNAME_MACHINE="alphaev68" ;; + "EV6.9A (21264/EV69A)") + UNAME_MACHINE="alphaev69" ;; + "EV7 (21364)") + UNAME_MACHINE="alphaev7" ;; + "EV7.9 (21364A)") + UNAME_MACHINE="alphaev79" ;; + esac + # A Pn.n version is a patched version. + # A Vn.n version is a released version. + # A Tn.n version is a released field test version. + # A Xn.n version is an unreleased experimental baselevel. + # 1.2 uses "1.2" for uname -r. + echo ${UNAME_MACHINE}-dec-osf`echo ${UNAME_RELEASE} | sed -e 's/^[PVTX]//' | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` + # Reset EXIT trap before exiting to avoid spurious non-zero exit code. + exitcode=$? + trap '' 0 + exit $exitcode ;; + Alpha\ *:Windows_NT*:*) + # How do we know it's Interix rather than the generic POSIX subsystem? + # Should we change UNAME_MACHINE based on the output of uname instead + # of the specific Alpha model? + echo alpha-pc-interix + exit ;; + 21064:Windows_NT:50:3) + echo alpha-dec-winnt3.5 + exit ;; + Amiga*:UNIX_System_V:4.0:*) + echo m68k-unknown-sysv4 + exit ;; + *:[Aa]miga[Oo][Ss]:*:*) + echo ${UNAME_MACHINE}-unknown-amigaos + exit ;; + *:[Mm]orph[Oo][Ss]:*:*) + echo ${UNAME_MACHINE}-unknown-morphos + exit ;; + *:OS/390:*:*) + echo i370-ibm-openedition + exit ;; + *:z/VM:*:*) + echo s390-ibm-zvmoe + exit ;; + *:OS400:*:*) + echo powerpc-ibm-os400 + exit ;; + arm:RISC*:1.[012]*:*|arm:riscix:1.[012]*:*) + echo arm-acorn-riscix${UNAME_RELEASE} + exit ;; + arm*:riscos:*:*|arm*:RISCOS:*:*) + echo arm-unknown-riscos + exit ;; + SR2?01:HI-UX/MPP:*:* | SR8000:HI-UX/MPP:*:*) + echo hppa1.1-hitachi-hiuxmpp + exit ;; + Pyramid*:OSx*:*:* | MIS*:OSx*:*:* | MIS*:SMP_DC-OSx*:*:*) + # akee@wpdis03.wpafb.af.mil (Earle F. Ake) contributed MIS and NILE. + if test "`(/bin/universe) 2>/dev/null`" = att ; then + echo pyramid-pyramid-sysv3 + else + echo pyramid-pyramid-bsd + fi + exit ;; + NILE*:*:*:dcosx) + echo pyramid-pyramid-svr4 + exit ;; + DRS?6000:unix:4.0:6*) + echo sparc-icl-nx6 + exit ;; + DRS?6000:UNIX_SV:4.2*:7* | DRS?6000:isis:4.2*:7*) + case `/usr/bin/uname -p` in + sparc) echo sparc-icl-nx7; exit ;; + esac ;; + s390x:SunOS:*:*) + echo ${UNAME_MACHINE}-ibm-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit ;; + sun4H:SunOS:5.*:*) + echo sparc-hal-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit ;; + sun4*:SunOS:5.*:* | tadpole*:SunOS:5.*:*) + echo sparc-sun-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit ;; + i86pc:AuroraUX:5.*:* | i86xen:AuroraUX:5.*:*) + echo i386-pc-auroraux${UNAME_RELEASE} + exit ;; + i86pc:SunOS:5.*:* | i86xen:SunOS:5.*:*) + eval $set_cc_for_build + SUN_ARCH="i386" + # If there is a compiler, see if it is configured for 64-bit objects. + # Note that the Sun cc does not turn __LP64__ into 1 like gcc does. + # This test works for both compilers. + if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then + if (echo '#ifdef __amd64'; echo IS_64BIT_ARCH; echo '#endif') | \ + (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \ + grep IS_64BIT_ARCH >/dev/null + then + SUN_ARCH="x86_64" + fi + fi + echo ${SUN_ARCH}-pc-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit ;; + sun4*:SunOS:6*:*) + # According to config.sub, this is the proper way to canonicalize + # SunOS6. Hard to guess exactly what SunOS6 will be like, but + # it's likely to be more like Solaris than SunOS4. + echo sparc-sun-solaris3`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit ;; + sun4*:SunOS:*:*) + case "`/usr/bin/arch -k`" in + Series*|S4*) + UNAME_RELEASE=`uname -v` + ;; + esac + # Japanese Language versions have a version number like `4.1.3-JL'. + echo sparc-sun-sunos`echo ${UNAME_RELEASE}|sed -e 's/-/_/'` + exit ;; + sun3*:SunOS:*:*) + echo m68k-sun-sunos${UNAME_RELEASE} + exit ;; + sun*:*:4.2BSD:*) + UNAME_RELEASE=`(sed 1q /etc/motd | awk '{print substr($5,1,3)}') 2>/dev/null` + test "x${UNAME_RELEASE}" = "x" && UNAME_RELEASE=3 + case "`/bin/arch`" in + sun3) + echo m68k-sun-sunos${UNAME_RELEASE} + ;; + sun4) + echo sparc-sun-sunos${UNAME_RELEASE} + ;; + esac + exit ;; + aushp:SunOS:*:*) + echo sparc-auspex-sunos${UNAME_RELEASE} + exit ;; + # The situation for MiNT is a little confusing. The machine name + # can be virtually everything (everything which is not + # "atarist" or "atariste" at least should have a processor + # > m68000). The system name ranges from "MiNT" over "FreeMiNT" + # to the lowercase version "mint" (or "freemint"). Finally + # the system name "TOS" denotes a system which is actually not + # MiNT. But MiNT is downward compatible to TOS, so this should + # be no problem. + atarist[e]:*MiNT:*:* | atarist[e]:*mint:*:* | atarist[e]:*TOS:*:*) + echo m68k-atari-mint${UNAME_RELEASE} + exit ;; + atari*:*MiNT:*:* | atari*:*mint:*:* | atarist[e]:*TOS:*:*) + echo m68k-atari-mint${UNAME_RELEASE} + exit ;; + *falcon*:*MiNT:*:* | *falcon*:*mint:*:* | *falcon*:*TOS:*:*) + echo m68k-atari-mint${UNAME_RELEASE} + exit ;; + milan*:*MiNT:*:* | milan*:*mint:*:* | *milan*:*TOS:*:*) + echo m68k-milan-mint${UNAME_RELEASE} + exit ;; + hades*:*MiNT:*:* | hades*:*mint:*:* | *hades*:*TOS:*:*) + echo m68k-hades-mint${UNAME_RELEASE} + exit ;; + *:*MiNT:*:* | *:*mint:*:* | *:*TOS:*:*) + echo m68k-unknown-mint${UNAME_RELEASE} + exit ;; + m68k:machten:*:*) + echo m68k-apple-machten${UNAME_RELEASE} + exit ;; + powerpc:machten:*:*) + echo powerpc-apple-machten${UNAME_RELEASE} + exit ;; + RISC*:Mach:*:*) + echo mips-dec-mach_bsd4.3 + exit ;; + RISC*:ULTRIX:*:*) + echo mips-dec-ultrix${UNAME_RELEASE} + exit ;; + VAX*:ULTRIX*:*:*) + echo vax-dec-ultrix${UNAME_RELEASE} + exit ;; + 2020:CLIX:*:* | 2430:CLIX:*:*) + echo clipper-intergraph-clix${UNAME_RELEASE} + exit ;; + mips:*:*:UMIPS | mips:*:*:RISCos) + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c +#ifdef __cplusplus +#include /* for printf() prototype */ + int main (int argc, char *argv[]) { +#else + int main (argc, argv) int argc; char *argv[]; { +#endif + #if defined (host_mips) && defined (MIPSEB) + #if defined (SYSTYPE_SYSV) + printf ("mips-mips-riscos%ssysv\n", argv[1]); exit (0); + #endif + #if defined (SYSTYPE_SVR4) + printf ("mips-mips-riscos%ssvr4\n", argv[1]); exit (0); + #endif + #if defined (SYSTYPE_BSD43) || defined(SYSTYPE_BSD) + printf ("mips-mips-riscos%sbsd\n", argv[1]); exit (0); + #endif + #endif + exit (-1); + } +EOF + $CC_FOR_BUILD -o $dummy $dummy.c && + dummyarg=`echo "${UNAME_RELEASE}" | sed -n 's/\([0-9]*\).*/\1/p'` && + SYSTEM_NAME=`$dummy $dummyarg` && + { echo "$SYSTEM_NAME"; exit; } + echo mips-mips-riscos${UNAME_RELEASE} + exit ;; + Motorola:PowerMAX_OS:*:*) + echo powerpc-motorola-powermax + exit ;; + Motorola:*:4.3:PL8-*) + echo powerpc-harris-powermax + exit ;; + Night_Hawk:*:*:PowerMAX_OS | Synergy:PowerMAX_OS:*:*) + echo powerpc-harris-powermax + exit ;; + Night_Hawk:Power_UNIX:*:*) + echo powerpc-harris-powerunix + exit ;; + m88k:CX/UX:7*:*) + echo m88k-harris-cxux7 + exit ;; + m88k:*:4*:R4*) + echo m88k-motorola-sysv4 + exit ;; + m88k:*:3*:R3*) + echo m88k-motorola-sysv3 + exit ;; + AViiON:dgux:*:*) + # DG/UX returns AViiON for all architectures + UNAME_PROCESSOR=`/usr/bin/uname -p` + if [ $UNAME_PROCESSOR = mc88100 ] || [ $UNAME_PROCESSOR = mc88110 ] + then + if [ ${TARGET_BINARY_INTERFACE}x = m88kdguxelfx ] || \ + [ ${TARGET_BINARY_INTERFACE}x = x ] + then + echo m88k-dg-dgux${UNAME_RELEASE} + else + echo m88k-dg-dguxbcs${UNAME_RELEASE} + fi + else + echo i586-dg-dgux${UNAME_RELEASE} + fi + exit ;; + M88*:DolphinOS:*:*) # DolphinOS (SVR3) + echo m88k-dolphin-sysv3 + exit ;; + M88*:*:R3*:*) + # Delta 88k system running SVR3 + echo m88k-motorola-sysv3 + exit ;; + XD88*:*:*:*) # Tektronix XD88 system running UTekV (SVR3) + echo m88k-tektronix-sysv3 + exit ;; + Tek43[0-9][0-9]:UTek:*:*) # Tektronix 4300 system running UTek (BSD) + echo m68k-tektronix-bsd + exit ;; + *:IRIX*:*:*) + echo mips-sgi-irix`echo ${UNAME_RELEASE}|sed -e 's/-/_/g'` + exit ;; + ????????:AIX?:[12].1:2) # AIX 2.2.1 or AIX 2.1.1 is RT/PC AIX. + echo romp-ibm-aix # uname -m gives an 8 hex-code CPU id + exit ;; # Note that: echo "'`uname -s`'" gives 'AIX ' + i*86:AIX:*:*) + echo i386-ibm-aix + exit ;; + ia64:AIX:*:*) + if [ -x /usr/bin/oslevel ] ; then + IBM_REV=`/usr/bin/oslevel` + else + IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} + fi + echo ${UNAME_MACHINE}-ibm-aix${IBM_REV} + exit ;; + *:AIX:2:3) + if grep bos325 /usr/include/stdio.h >/dev/null 2>&1; then + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #include + + main() + { + if (!__power_pc()) + exit(1); + puts("powerpc-ibm-aix3.2.5"); + exit(0); + } +EOF + if $CC_FOR_BUILD -o $dummy $dummy.c && SYSTEM_NAME=`$dummy` + then + echo "$SYSTEM_NAME" + else + echo rs6000-ibm-aix3.2.5 + fi + elif grep bos324 /usr/include/stdio.h >/dev/null 2>&1; then + echo rs6000-ibm-aix3.2.4 + else + echo rs6000-ibm-aix3.2 + fi + exit ;; + *:AIX:*:[4567]) + IBM_CPU_ID=`/usr/sbin/lsdev -C -c processor -S available | sed 1q | awk '{ print $1 }'` + if /usr/sbin/lsattr -El ${IBM_CPU_ID} | grep ' POWER' >/dev/null 2>&1; then + IBM_ARCH=rs6000 + else + IBM_ARCH=powerpc + fi + if [ -x /usr/bin/oslevel ] ; then + IBM_REV=`/usr/bin/oslevel` + else + IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} + fi + echo ${IBM_ARCH}-ibm-aix${IBM_REV} + exit ;; + *:AIX:*:*) + echo rs6000-ibm-aix + exit ;; + ibmrt:4.4BSD:*|romp-ibm:BSD:*) + echo romp-ibm-bsd4.4 + exit ;; + ibmrt:*BSD:*|romp-ibm:BSD:*) # covers RT/PC BSD and + echo romp-ibm-bsd${UNAME_RELEASE} # 4.3 with uname added to + exit ;; # report: romp-ibm BSD 4.3 + *:BOSX:*:*) + echo rs6000-bull-bosx + exit ;; + DPX/2?00:B.O.S.:*:*) + echo m68k-bull-sysv3 + exit ;; + 9000/[34]??:4.3bsd:1.*:*) + echo m68k-hp-bsd + exit ;; + hp300:4.4BSD:*:* | 9000/[34]??:4.3bsd:2.*:*) + echo m68k-hp-bsd4.4 + exit ;; + 9000/[34678]??:HP-UX:*:*) + HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` + case "${UNAME_MACHINE}" in + 9000/31? ) HP_ARCH=m68000 ;; + 9000/[34]?? ) HP_ARCH=m68k ;; + 9000/[678][0-9][0-9]) + if [ -x /usr/bin/getconf ]; then + sc_cpu_version=`/usr/bin/getconf SC_CPU_VERSION 2>/dev/null` + sc_kernel_bits=`/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null` + case "${sc_cpu_version}" in + 523) HP_ARCH="hppa1.0" ;; # CPU_PA_RISC1_0 + 528) HP_ARCH="hppa1.1" ;; # CPU_PA_RISC1_1 + 532) # CPU_PA_RISC2_0 + case "${sc_kernel_bits}" in + 32) HP_ARCH="hppa2.0n" ;; + 64) HP_ARCH="hppa2.0w" ;; + '') HP_ARCH="hppa2.0" ;; # HP-UX 10.20 + esac ;; + esac + fi + if [ "${HP_ARCH}" = "" ]; then + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + + #define _HPUX_SOURCE + #include + #include + + int main () + { + #if defined(_SC_KERNEL_BITS) + long bits = sysconf(_SC_KERNEL_BITS); + #endif + long cpu = sysconf (_SC_CPU_VERSION); + + switch (cpu) + { + case CPU_PA_RISC1_0: puts ("hppa1.0"); break; + case CPU_PA_RISC1_1: puts ("hppa1.1"); break; + case CPU_PA_RISC2_0: + #if defined(_SC_KERNEL_BITS) + switch (bits) + { + case 64: puts ("hppa2.0w"); break; + case 32: puts ("hppa2.0n"); break; + default: puts ("hppa2.0"); break; + } break; + #else /* !defined(_SC_KERNEL_BITS) */ + puts ("hppa2.0"); break; + #endif + default: puts ("hppa1.0"); break; + } + exit (0); + } +EOF + (CCOPTS= $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null) && HP_ARCH=`$dummy` + test -z "$HP_ARCH" && HP_ARCH=hppa + fi ;; + esac + if [ ${HP_ARCH} = "hppa2.0w" ] + then + eval $set_cc_for_build + + # hppa2.0w-hp-hpux* has a 64-bit kernel and a compiler generating + # 32-bit code. hppa64-hp-hpux* has the same kernel and a compiler + # generating 64-bit code. GNU and HP use different nomenclature: + # + # $ CC_FOR_BUILD=cc ./config.guess + # => hppa2.0w-hp-hpux11.23 + # $ CC_FOR_BUILD="cc +DA2.0w" ./config.guess + # => hppa64-hp-hpux11.23 + + if echo __LP64__ | (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | + grep -q __LP64__ + then + HP_ARCH="hppa2.0w" + else + HP_ARCH="hppa64" + fi + fi + echo ${HP_ARCH}-hp-hpux${HPUX_REV} + exit ;; + ia64:HP-UX:*:*) + HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` + echo ia64-hp-hpux${HPUX_REV} + exit ;; + 3050*:HI-UX:*:*) + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #include + int + main () + { + long cpu = sysconf (_SC_CPU_VERSION); + /* The order matters, because CPU_IS_HP_MC68K erroneously returns + true for CPU_PA_RISC1_0. CPU_IS_PA_RISC returns correct + results, however. */ + if (CPU_IS_PA_RISC (cpu)) + { + switch (cpu) + { + case CPU_PA_RISC1_0: puts ("hppa1.0-hitachi-hiuxwe2"); break; + case CPU_PA_RISC1_1: puts ("hppa1.1-hitachi-hiuxwe2"); break; + case CPU_PA_RISC2_0: puts ("hppa2.0-hitachi-hiuxwe2"); break; + default: puts ("hppa-hitachi-hiuxwe2"); break; + } + } + else if (CPU_IS_HP_MC68K (cpu)) + puts ("m68k-hitachi-hiuxwe2"); + else puts ("unknown-hitachi-hiuxwe2"); + exit (0); + } +EOF + $CC_FOR_BUILD -o $dummy $dummy.c && SYSTEM_NAME=`$dummy` && + { echo "$SYSTEM_NAME"; exit; } + echo unknown-hitachi-hiuxwe2 + exit ;; + 9000/7??:4.3bsd:*:* | 9000/8?[79]:4.3bsd:*:* ) + echo hppa1.1-hp-bsd + exit ;; + 9000/8??:4.3bsd:*:*) + echo hppa1.0-hp-bsd + exit ;; + *9??*:MPE/iX:*:* | *3000*:MPE/iX:*:*) + echo hppa1.0-hp-mpeix + exit ;; + hp7??:OSF1:*:* | hp8?[79]:OSF1:*:* ) + echo hppa1.1-hp-osf + exit ;; + hp8??:OSF1:*:*) + echo hppa1.0-hp-osf + exit ;; + i*86:OSF1:*:*) + if [ -x /usr/sbin/sysversion ] ; then + echo ${UNAME_MACHINE}-unknown-osf1mk + else + echo ${UNAME_MACHINE}-unknown-osf1 + fi + exit ;; + parisc*:Lites*:*:*) + echo hppa1.1-hp-lites + exit ;; + C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*) + echo c1-convex-bsd + exit ;; + C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*) + if getsysinfo -f scalar_acc + then echo c32-convex-bsd + else echo c2-convex-bsd + fi + exit ;; + C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*) + echo c34-convex-bsd + exit ;; + C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*) + echo c38-convex-bsd + exit ;; + C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*) + echo c4-convex-bsd + exit ;; + CRAY*Y-MP:*:*:*) + echo ymp-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit ;; + CRAY*[A-Z]90:*:*:*) + echo ${UNAME_MACHINE}-cray-unicos${UNAME_RELEASE} \ + | sed -e 's/CRAY.*\([A-Z]90\)/\1/' \ + -e y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/ \ + -e 's/\.[^.]*$/.X/' + exit ;; + CRAY*TS:*:*:*) + echo t90-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit ;; + CRAY*T3E:*:*:*) + echo alphaev5-cray-unicosmk${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit ;; + CRAY*SV1:*:*:*) + echo sv1-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit ;; + *:UNICOS/mp:*:*) + echo craynv-cray-unicosmp${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit ;; + F30[01]:UNIX_System_V:*:* | F700:UNIX_System_V:*:*) + FUJITSU_PROC=`uname -m | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` + FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` + FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'` + echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" + exit ;; + 5000:UNIX_System_V:4.*:*) + FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` + FUJITSU_REL=`echo ${UNAME_RELEASE} | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/ /_/'` + echo "sparc-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" + exit ;; + i*86:BSD/386:*:* | i*86:BSD/OS:*:* | *:Ascend\ Embedded/OS:*:*) + echo ${UNAME_MACHINE}-pc-bsdi${UNAME_RELEASE} + exit ;; + sparc*:BSD/OS:*:*) + echo sparc-unknown-bsdi${UNAME_RELEASE} + exit ;; + *:BSD/OS:*:*) + echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE} + exit ;; + *:FreeBSD:*:*) + UNAME_PROCESSOR=`/usr/bin/uname -p` + case ${UNAME_PROCESSOR} in + amd64) + echo x86_64-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; + *) + echo ${UNAME_PROCESSOR}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; + esac + exit ;; + i*:CYGWIN*:*) + echo ${UNAME_MACHINE}-pc-cygwin + exit ;; + *:MINGW64*:*) + echo ${UNAME_MACHINE}-pc-mingw64 + exit ;; + *:MINGW*:*) + echo ${UNAME_MACHINE}-pc-mingw32 + exit ;; + i*:MSYS*:*) + echo ${UNAME_MACHINE}-pc-msys + exit ;; + i*:windows32*:*) + # uname -m includes "-pc" on this system. + echo ${UNAME_MACHINE}-mingw32 + exit ;; + i*:PW*:*) + echo ${UNAME_MACHINE}-pc-pw32 + exit ;; + *:Interix*:*) + case ${UNAME_MACHINE} in + x86) + echo i586-pc-interix${UNAME_RELEASE} + exit ;; + authenticamd | genuineintel | EM64T) + echo x86_64-unknown-interix${UNAME_RELEASE} + exit ;; + IA64) + echo ia64-unknown-interix${UNAME_RELEASE} + exit ;; + esac ;; + [345]86:Windows_95:* | [345]86:Windows_98:* | [345]86:Windows_NT:*) + echo i${UNAME_MACHINE}-pc-mks + exit ;; + 8664:Windows_NT:*) + echo x86_64-pc-mks + exit ;; + i*:Windows_NT*:* | Pentium*:Windows_NT*:*) + # How do we know it's Interix rather than the generic POSIX subsystem? + # It also conflicts with pre-2.0 versions of AT&T UWIN. Should we + # UNAME_MACHINE based on the output of uname instead of i386? + echo i586-pc-interix + exit ;; + i*:UWIN*:*) + echo ${UNAME_MACHINE}-pc-uwin + exit ;; + amd64:CYGWIN*:*:* | x86_64:CYGWIN*:*:*) + echo x86_64-unknown-cygwin + exit ;; + p*:CYGWIN*:*) + echo powerpcle-unknown-cygwin + exit ;; + prep*:SunOS:5.*:*) + echo powerpcle-unknown-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit ;; + *:GNU:*:*) + # the GNU system + echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-${LIBC}`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` + exit ;; + *:GNU/*:*:*) + # other systems with GNU libc and userland + echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-${LIBC} + exit ;; + i*86:Minix:*:*) + echo ${UNAME_MACHINE}-pc-minix + exit ;; + aarch64:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + aarch64_be:Linux:*:*) + UNAME_MACHINE=aarch64_be + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + alpha:Linux:*:*) + case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in + EV5) UNAME_MACHINE=alphaev5 ;; + EV56) UNAME_MACHINE=alphaev56 ;; + PCA56) UNAME_MACHINE=alphapca56 ;; + PCA57) UNAME_MACHINE=alphapca56 ;; + EV6) UNAME_MACHINE=alphaev6 ;; + EV67) UNAME_MACHINE=alphaev67 ;; + EV68*) UNAME_MACHINE=alphaev68 ;; + esac + objdump --private-headers /bin/sh | grep -q ld.so.1 + if test "$?" = 0 ; then LIBC="gnulibc1" ; fi + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + arc:Linux:*:* | arceb:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + arm*:Linux:*:*) + eval $set_cc_for_build + if echo __ARM_EABI__ | $CC_FOR_BUILD -E - 2>/dev/null \ + | grep -q __ARM_EABI__ + then + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + else + if echo __ARM_PCS_VFP | $CC_FOR_BUILD -E - 2>/dev/null \ + | grep -q __ARM_PCS_VFP + then + echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabi + else + echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabihf + fi + fi + exit ;; + avr32*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + cris:Linux:*:*) + echo ${UNAME_MACHINE}-axis-linux-${LIBC} + exit ;; + crisv32:Linux:*:*) + echo ${UNAME_MACHINE}-axis-linux-${LIBC} + exit ;; + frv:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + hexagon:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + i*86:Linux:*:*) + echo ${UNAME_MACHINE}-pc-linux-${LIBC} + exit ;; + ia64:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + m32r*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + m68*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + mips:Linux:*:* | mips64:Linux:*:*) + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #undef CPU + #undef ${UNAME_MACHINE} + #undef ${UNAME_MACHINE}el + #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) + CPU=${UNAME_MACHINE}el + #else + #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) + CPU=${UNAME_MACHINE} + #else + CPU= + #endif + #endif +EOF + eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^CPU'` + test x"${CPU}" != x && { echo "${CPU}-unknown-linux-${LIBC}"; exit; } + ;; + or1k:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + or32:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + padre:Linux:*:*) + echo sparc-unknown-linux-${LIBC} + exit ;; + parisc64:Linux:*:* | hppa64:Linux:*:*) + echo hppa64-unknown-linux-${LIBC} + exit ;; + parisc:Linux:*:* | hppa:Linux:*:*) + # Look for CPU level + case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in + PA7*) echo hppa1.1-unknown-linux-${LIBC} ;; + PA8*) echo hppa2.0-unknown-linux-${LIBC} ;; + *) echo hppa-unknown-linux-${LIBC} ;; + esac + exit ;; + ppc64:Linux:*:*) + echo powerpc64-unknown-linux-${LIBC} + exit ;; + ppc:Linux:*:*) + echo powerpc-unknown-linux-${LIBC} + exit ;; + ppc64le:Linux:*:*) + echo powerpc64le-unknown-linux-${LIBC} + exit ;; + ppcle:Linux:*:*) + echo powerpcle-unknown-linux-${LIBC} + exit ;; + s390:Linux:*:* | s390x:Linux:*:*) + echo ${UNAME_MACHINE}-ibm-linux-${LIBC} + exit ;; + sh64*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + sh*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + sparc:Linux:*:* | sparc64:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + tile*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + vax:Linux:*:*) + echo ${UNAME_MACHINE}-dec-linux-${LIBC} + exit ;; + x86_64:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + xtensa*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + i*86:DYNIX/ptx:4*:*) + # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. + # earlier versions are messed up and put the nodename in both + # sysname and nodename. + echo i386-sequent-sysv4 + exit ;; + i*86:UNIX_SV:4.2MP:2.*) + # Unixware is an offshoot of SVR4, but it has its own version + # number series starting with 2... + # I am not positive that other SVR4 systems won't match this, + # I just have to hope. -- rms. + # Use sysv4.2uw... so that sysv4* matches it. + echo ${UNAME_MACHINE}-pc-sysv4.2uw${UNAME_VERSION} + exit ;; + i*86:OS/2:*:*) + # If we were able to find `uname', then EMX Unix compatibility + # is probably installed. + echo ${UNAME_MACHINE}-pc-os2-emx + exit ;; + i*86:XTS-300:*:STOP) + echo ${UNAME_MACHINE}-unknown-stop + exit ;; + i*86:atheos:*:*) + echo ${UNAME_MACHINE}-unknown-atheos + exit ;; + i*86:syllable:*:*) + echo ${UNAME_MACHINE}-pc-syllable + exit ;; + i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.[02]*:*) + echo i386-unknown-lynxos${UNAME_RELEASE} + exit ;; + i*86:*DOS:*:*) + echo ${UNAME_MACHINE}-pc-msdosdjgpp + exit ;; + i*86:*:4.*:* | i*86:SYSTEM_V:4.*:*) + UNAME_REL=`echo ${UNAME_RELEASE} | sed 's/\/MP$//'` + if grep Novell /usr/include/link.h >/dev/null 2>/dev/null; then + echo ${UNAME_MACHINE}-univel-sysv${UNAME_REL} + else + echo ${UNAME_MACHINE}-pc-sysv${UNAME_REL} + fi + exit ;; + i*86:*:5:[678]*) + # UnixWare 7.x, OpenUNIX and OpenServer 6. + case `/bin/uname -X | grep "^Machine"` in + *486*) UNAME_MACHINE=i486 ;; + *Pentium) UNAME_MACHINE=i586 ;; + *Pent*|*Celeron) UNAME_MACHINE=i686 ;; + esac + echo ${UNAME_MACHINE}-unknown-sysv${UNAME_RELEASE}${UNAME_SYSTEM}${UNAME_VERSION} + exit ;; + i*86:*:3.2:*) + if test -f /usr/options/cb.name; then + UNAME_REL=`sed -n 's/.*Version //p' /dev/null >/dev/null ; then + UNAME_REL=`(/bin/uname -X|grep Release|sed -e 's/.*= //')` + (/bin/uname -X|grep i80486 >/dev/null) && UNAME_MACHINE=i486 + (/bin/uname -X|grep '^Machine.*Pentium' >/dev/null) \ + && UNAME_MACHINE=i586 + (/bin/uname -X|grep '^Machine.*Pent *II' >/dev/null) \ + && UNAME_MACHINE=i686 + (/bin/uname -X|grep '^Machine.*Pentium Pro' >/dev/null) \ + && UNAME_MACHINE=i686 + echo ${UNAME_MACHINE}-pc-sco$UNAME_REL + else + echo ${UNAME_MACHINE}-pc-sysv32 + fi + exit ;; + pc:*:*:*) + # Left here for compatibility: + # uname -m prints for DJGPP always 'pc', but it prints nothing about + # the processor, so we play safe by assuming i586. + # Note: whatever this is, it MUST be the same as what config.sub + # prints for the "djgpp" host, or else GDB configury will decide that + # this is a cross-build. + echo i586-pc-msdosdjgpp + exit ;; + Intel:Mach:3*:*) + echo i386-pc-mach3 + exit ;; + paragon:*:*:*) + echo i860-intel-osf1 + exit ;; + i860:*:4.*:*) # i860-SVR4 + if grep Stardent /usr/include/sys/uadmin.h >/dev/null 2>&1 ; then + echo i860-stardent-sysv${UNAME_RELEASE} # Stardent Vistra i860-SVR4 + else # Add other i860-SVR4 vendors below as they are discovered. + echo i860-unknown-sysv${UNAME_RELEASE} # Unknown i860-SVR4 + fi + exit ;; + mini*:CTIX:SYS*5:*) + # "miniframe" + echo m68010-convergent-sysv + exit ;; + mc68k:UNIX:SYSTEM5:3.51m) + echo m68k-convergent-sysv + exit ;; + M680?0:D-NIX:5.3:*) + echo m68k-diab-dnix + exit ;; + M68*:*:R3V[5678]*:*) + test -r /sysV68 && { echo 'm68k-motorola-sysv'; exit; } ;; + 3[345]??:*:4.0:3.0 | 3[34]??A:*:4.0:3.0 | 3[34]??,*:*:4.0:3.0 | 3[34]??/*:*:4.0:3.0 | 4400:*:4.0:3.0 | 4850:*:4.0:3.0 | SKA40:*:4.0:3.0 | SDS2:*:4.0:3.0 | SHG2:*:4.0:3.0 | S7501*:*:4.0:3.0) + OS_REL='' + test -r /etc/.relid \ + && OS_REL=.`sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid` + /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ + && { echo i486-ncr-sysv4.3${OS_REL}; exit; } + /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \ + && { echo i586-ncr-sysv4.3${OS_REL}; exit; } ;; + 3[34]??:*:4.0:* | 3[34]??,*:*:4.0:*) + /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ + && { echo i486-ncr-sysv4; exit; } ;; + NCR*:*:4.2:* | MPRAS*:*:4.2:*) + OS_REL='.3' + test -r /etc/.relid \ + && OS_REL=.`sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid` + /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ + && { echo i486-ncr-sysv4.3${OS_REL}; exit; } + /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \ + && { echo i586-ncr-sysv4.3${OS_REL}; exit; } + /bin/uname -p 2>/dev/null | /bin/grep pteron >/dev/null \ + && { echo i586-ncr-sysv4.3${OS_REL}; exit; } ;; + m68*:LynxOS:2.*:* | m68*:LynxOS:3.0*:*) + echo m68k-unknown-lynxos${UNAME_RELEASE} + exit ;; + mc68030:UNIX_System_V:4.*:*) + echo m68k-atari-sysv4 + exit ;; + TSUNAMI:LynxOS:2.*:*) + echo sparc-unknown-lynxos${UNAME_RELEASE} + exit ;; + rs6000:LynxOS:2.*:*) + echo rs6000-unknown-lynxos${UNAME_RELEASE} + exit ;; + PowerPC:LynxOS:2.*:* | PowerPC:LynxOS:3.[01]*:* | PowerPC:LynxOS:4.[02]*:*) + echo powerpc-unknown-lynxos${UNAME_RELEASE} + exit ;; + SM[BE]S:UNIX_SV:*:*) + echo mips-dde-sysv${UNAME_RELEASE} + exit ;; + RM*:ReliantUNIX-*:*:*) + echo mips-sni-sysv4 + exit ;; + RM*:SINIX-*:*:*) + echo mips-sni-sysv4 + exit ;; + *:SINIX-*:*:*) + if uname -p 2>/dev/null >/dev/null ; then + UNAME_MACHINE=`(uname -p) 2>/dev/null` + echo ${UNAME_MACHINE}-sni-sysv4 + else + echo ns32k-sni-sysv + fi + exit ;; + PENTIUM:*:4.0*:*) # Unisys `ClearPath HMP IX 4000' SVR4/MP effort + # says + echo i586-unisys-sysv4 + exit ;; + *:UNIX_System_V:4*:FTX*) + # From Gerald Hewes . + # How about differentiating between stratus architectures? -djm + echo hppa1.1-stratus-sysv4 + exit ;; + *:*:*:FTX*) + # From seanf@swdc.stratus.com. + echo i860-stratus-sysv4 + exit ;; + i*86:VOS:*:*) + # From Paul.Green@stratus.com. + echo ${UNAME_MACHINE}-stratus-vos + exit ;; + *:VOS:*:*) + # From Paul.Green@stratus.com. + echo hppa1.1-stratus-vos + exit ;; + mc68*:A/UX:*:*) + echo m68k-apple-aux${UNAME_RELEASE} + exit ;; + news*:NEWS-OS:6*:*) + echo mips-sony-newsos6 + exit ;; + R[34]000:*System_V*:*:* | R4000:UNIX_SYSV:*:* | R*000:UNIX_SV:*:*) + if [ -d /usr/nec ]; then + echo mips-nec-sysv${UNAME_RELEASE} + else + echo mips-unknown-sysv${UNAME_RELEASE} + fi + exit ;; + BeBox:BeOS:*:*) # BeOS running on hardware made by Be, PPC only. + echo powerpc-be-beos + exit ;; + BeMac:BeOS:*:*) # BeOS running on Mac or Mac clone, PPC only. + echo powerpc-apple-beos + exit ;; + BePC:BeOS:*:*) # BeOS running on Intel PC compatible. + echo i586-pc-beos + exit ;; + BePC:Haiku:*:*) # Haiku running on Intel PC compatible. + echo i586-pc-haiku + exit ;; + x86_64:Haiku:*:*) + echo x86_64-unknown-haiku + exit ;; + SX-4:SUPER-UX:*:*) + echo sx4-nec-superux${UNAME_RELEASE} + exit ;; + SX-5:SUPER-UX:*:*) + echo sx5-nec-superux${UNAME_RELEASE} + exit ;; + SX-6:SUPER-UX:*:*) + echo sx6-nec-superux${UNAME_RELEASE} + exit ;; + SX-7:SUPER-UX:*:*) + echo sx7-nec-superux${UNAME_RELEASE} + exit ;; + SX-8:SUPER-UX:*:*) + echo sx8-nec-superux${UNAME_RELEASE} + exit ;; + SX-8R:SUPER-UX:*:*) + echo sx8r-nec-superux${UNAME_RELEASE} + exit ;; + Power*:Rhapsody:*:*) + echo powerpc-apple-rhapsody${UNAME_RELEASE} + exit ;; + *:Rhapsody:*:*) + echo ${UNAME_MACHINE}-apple-rhapsody${UNAME_RELEASE} + exit ;; + *:Darwin:*:*) + UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown + eval $set_cc_for_build + if test "$UNAME_PROCESSOR" = unknown ; then + UNAME_PROCESSOR=powerpc + fi + if test `echo "$UNAME_RELEASE" | sed -e 's/\..*//'` -le 10 ; then + if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then + if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \ + (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \ + grep IS_64BIT_ARCH >/dev/null + then + case $UNAME_PROCESSOR in + i386) UNAME_PROCESSOR=x86_64 ;; + powerpc) UNAME_PROCESSOR=powerpc64 ;; + esac + fi + fi + elif test "$UNAME_PROCESSOR" = i386 ; then + # Avoid executing cc on OS X 10.9, as it ships with a stub + # that puts up a graphical alert prompting to install + # developer tools. Any system running Mac OS X 10.7 or + # later (Darwin 11 and later) is required to have a 64-bit + # processor. This is not true of the ARM version of Darwin + # that Apple uses in portable devices. + UNAME_PROCESSOR=x86_64 + fi + echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE} + exit ;; + *:procnto*:*:* | *:QNX:[0123456789]*:*) + UNAME_PROCESSOR=`uname -p` + if test "$UNAME_PROCESSOR" = "x86"; then + UNAME_PROCESSOR=i386 + UNAME_MACHINE=pc + fi + echo ${UNAME_PROCESSOR}-${UNAME_MACHINE}-nto-qnx${UNAME_RELEASE} + exit ;; + *:QNX:*:4*) + echo i386-pc-qnx + exit ;; + NEO-?:NONSTOP_KERNEL:*:*) + echo neo-tandem-nsk${UNAME_RELEASE} + exit ;; + NSE-*:NONSTOP_KERNEL:*:*) + echo nse-tandem-nsk${UNAME_RELEASE} + exit ;; + NSR-?:NONSTOP_KERNEL:*:*) + echo nsr-tandem-nsk${UNAME_RELEASE} + exit ;; + *:NonStop-UX:*:*) + echo mips-compaq-nonstopux + exit ;; + BS2000:POSIX*:*:*) + echo bs2000-siemens-sysv + exit ;; + DS/*:UNIX_System_V:*:*) + echo ${UNAME_MACHINE}-${UNAME_SYSTEM}-${UNAME_RELEASE} + exit ;; + *:Plan9:*:*) + # "uname -m" is not consistent, so use $cputype instead. 386 + # is converted to i386 for consistency with other x86 + # operating systems. + if test "$cputype" = "386"; then + UNAME_MACHINE=i386 + else + UNAME_MACHINE="$cputype" + fi + echo ${UNAME_MACHINE}-unknown-plan9 + exit ;; + *:TOPS-10:*:*) + echo pdp10-unknown-tops10 + exit ;; + *:TENEX:*:*) + echo pdp10-unknown-tenex + exit ;; + KS10:TOPS-20:*:* | KL10:TOPS-20:*:* | TYPE4:TOPS-20:*:*) + echo pdp10-dec-tops20 + exit ;; + XKL-1:TOPS-20:*:* | TYPE5:TOPS-20:*:*) + echo pdp10-xkl-tops20 + exit ;; + *:TOPS-20:*:*) + echo pdp10-unknown-tops20 + exit ;; + *:ITS:*:*) + echo pdp10-unknown-its + exit ;; + SEI:*:*:SEIUX) + echo mips-sei-seiux${UNAME_RELEASE} + exit ;; + *:DragonFly:*:*) + echo ${UNAME_MACHINE}-unknown-dragonfly`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` + exit ;; + *:*VMS:*:*) + UNAME_MACHINE=`(uname -p) 2>/dev/null` + case "${UNAME_MACHINE}" in + A*) echo alpha-dec-vms ; exit ;; + I*) echo ia64-dec-vms ; exit ;; + V*) echo vax-dec-vms ; exit ;; + esac ;; + *:XENIX:*:SysV) + echo i386-pc-xenix + exit ;; + i*86:skyos:*:*) + echo ${UNAME_MACHINE}-pc-skyos`echo ${UNAME_RELEASE}` | sed -e 's/ .*$//' + exit ;; + i*86:rdos:*:*) + echo ${UNAME_MACHINE}-pc-rdos + exit ;; + i*86:AROS:*:*) + echo ${UNAME_MACHINE}-pc-aros + exit ;; + x86_64:VMkernel:*:*) + echo ${UNAME_MACHINE}-unknown-esx + exit ;; +esac + +eval $set_cc_for_build +cat >$dummy.c < +# include +#endif +main () +{ +#if defined (sony) +#if defined (MIPSEB) + /* BFD wants "bsd" instead of "newsos". Perhaps BFD should be changed, + I don't know.... */ + printf ("mips-sony-bsd\n"); exit (0); +#else +#include + printf ("m68k-sony-newsos%s\n", +#ifdef NEWSOS4 + "4" +#else + "" +#endif + ); exit (0); +#endif +#endif + +#if defined (__arm) && defined (__acorn) && defined (__unix) + printf ("arm-acorn-riscix\n"); exit (0); +#endif + +#if defined (hp300) && !defined (hpux) + printf ("m68k-hp-bsd\n"); exit (0); +#endif + +#if defined (NeXT) +#if !defined (__ARCHITECTURE__) +#define __ARCHITECTURE__ "m68k" +#endif + int version; + version=`(hostinfo | sed -n 's/.*NeXT Mach \([0-9]*\).*/\1/p') 2>/dev/null`; + if (version < 4) + printf ("%s-next-nextstep%d\n", __ARCHITECTURE__, version); + else + printf ("%s-next-openstep%d\n", __ARCHITECTURE__, version); + exit (0); +#endif + +#if defined (MULTIMAX) || defined (n16) +#if defined (UMAXV) + printf ("ns32k-encore-sysv\n"); exit (0); +#else +#if defined (CMU) + printf ("ns32k-encore-mach\n"); exit (0); +#else + printf ("ns32k-encore-bsd\n"); exit (0); +#endif +#endif +#endif + +#if defined (__386BSD__) + printf ("i386-pc-bsd\n"); exit (0); +#endif + +#if defined (sequent) +#if defined (i386) + printf ("i386-sequent-dynix\n"); exit (0); +#endif +#if defined (ns32000) + printf ("ns32k-sequent-dynix\n"); exit (0); +#endif +#endif + +#if defined (_SEQUENT_) + struct utsname un; + + uname(&un); + + if (strncmp(un.version, "V2", 2) == 0) { + printf ("i386-sequent-ptx2\n"); exit (0); + } + if (strncmp(un.version, "V1", 2) == 0) { /* XXX is V1 correct? */ + printf ("i386-sequent-ptx1\n"); exit (0); + } + printf ("i386-sequent-ptx\n"); exit (0); + +#endif + +#if defined (vax) +# if !defined (ultrix) +# include +# if defined (BSD) +# if BSD == 43 + printf ("vax-dec-bsd4.3\n"); exit (0); +# else +# if BSD == 199006 + printf ("vax-dec-bsd4.3reno\n"); exit (0); +# else + printf ("vax-dec-bsd\n"); exit (0); +# endif +# endif +# else + printf ("vax-dec-bsd\n"); exit (0); +# endif +# else + printf ("vax-dec-ultrix\n"); exit (0); +# endif +#endif + +#if defined (alliant) && defined (i860) + printf ("i860-alliant-bsd\n"); exit (0); +#endif + + exit (1); +} +EOF + +$CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null && SYSTEM_NAME=`$dummy` && + { echo "$SYSTEM_NAME"; exit; } + +# Apollos put the system type in the environment. + +test -d /usr/apollo && { echo ${ISP}-apollo-${SYSTYPE}; exit; } + +# Convex versions that predate uname can use getsysinfo(1) + +if [ -x /usr/convex/getsysinfo ] +then + case `getsysinfo -f cpu_type` in + c1*) + echo c1-convex-bsd + exit ;; + c2*) + if getsysinfo -f scalar_acc + then echo c32-convex-bsd + else echo c2-convex-bsd + fi + exit ;; + c34*) + echo c34-convex-bsd + exit ;; + c38*) + echo c38-convex-bsd + exit ;; + c4*) + echo c4-convex-bsd + exit ;; + esac +fi + +cat >&2 < in order to provide the needed +information to handle your system. + +config.guess timestamp = $timestamp + +uname -m = `(uname -m) 2>/dev/null || echo unknown` +uname -r = `(uname -r) 2>/dev/null || echo unknown` +uname -s = `(uname -s) 2>/dev/null || echo unknown` +uname -v = `(uname -v) 2>/dev/null || echo unknown` + +/usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null` +/bin/uname -X = `(/bin/uname -X) 2>/dev/null` + +hostinfo = `(hostinfo) 2>/dev/null` +/bin/universe = `(/bin/universe) 2>/dev/null` +/usr/bin/arch -k = `(/usr/bin/arch -k) 2>/dev/null` +/bin/arch = `(/bin/arch) 2>/dev/null` +/usr/bin/oslevel = `(/usr/bin/oslevel) 2>/dev/null` +/usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null` + +UNAME_MACHINE = ${UNAME_MACHINE} +UNAME_RELEASE = ${UNAME_RELEASE} +UNAME_SYSTEM = ${UNAME_SYSTEM} +UNAME_VERSION = ${UNAME_VERSION} +EOF + +exit 1 + +# Local variables: +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "timestamp='" +# time-stamp-format: "%:y-%02m-%02d" +# time-stamp-end: "'" +# End: diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/config.sub b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/config.sub new file mode 100644 index 0000000..61cb4bc --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/config.sub @@ -0,0 +1,1793 @@ +#! /bin/sh +# Configuration validation subroutine script. +# Copyright 1992-2013 Free Software Foundation, Inc. + +timestamp='2013-10-01' + +# This file is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see . +# +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that +# program. This Exception is an additional permission under section 7 +# of the GNU General Public License, version 3 ("GPLv3"). + + +# Please send patches with a ChangeLog entry to config-patches@gnu.org. +# +# Configuration subroutine to validate and canonicalize a configuration type. +# Supply the specified configuration type as an argument. +# If it is invalid, we print an error message on stderr and exit with code 1. +# Otherwise, we print the canonical config type on stdout and succeed. + +# You can get the latest version of this script from: +# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub;hb=HEAD + +# This file is supposed to be the same for all GNU packages +# and recognize all the CPU types, system types and aliases +# that are meaningful with *any* GNU software. +# Each package is responsible for reporting which valid configurations +# it does not support. The user should be able to distinguish +# a failure to support a valid configuration from a meaningless +# configuration. + +# The goal of this file is to map all the various variations of a given +# machine specification into a single specification in the form: +# CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM +# or in some cases, the newer four-part form: +# CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM +# It is wrong to echo any other type of specification. + +me=`echo "$0" | sed -e 's,.*/,,'` + +usage="\ +Usage: $0 [OPTION] CPU-MFR-OPSYS + $0 [OPTION] ALIAS + +Canonicalize a configuration name. + +Operation modes: + -h, --help print this help, then exit + -t, --time-stamp print date of last modification, then exit + -v, --version print version number, then exit + +Report bugs and patches to ." + +version="\ +GNU config.sub ($timestamp) + +Copyright 1992-2013 Free Software Foundation, Inc. + +This is free software; see the source for copying conditions. There is NO +warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." + +help=" +Try \`$me --help' for more information." + +# Parse command line +while test $# -gt 0 ; do + case $1 in + --time-stamp | --time* | -t ) + echo "$timestamp" ; exit ;; + --version | -v ) + echo "$version" ; exit ;; + --help | --h* | -h ) + echo "$usage"; exit ;; + -- ) # Stop option processing + shift; break ;; + - ) # Use stdin as input. + break ;; + -* ) + echo "$me: invalid option $1$help" + exit 1 ;; + + *local*) + # First pass through any local machine types. + echo $1 + exit ;; + + * ) + break ;; + esac +done + +case $# in + 0) echo "$me: missing argument$help" >&2 + exit 1;; + 1) ;; + *) echo "$me: too many arguments$help" >&2 + exit 1;; +esac + +# Separate what the user gave into CPU-COMPANY and OS or KERNEL-OS (if any). +# Here we must recognize all the valid KERNEL-OS combinations. +maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'` +case $maybe_os in + nto-qnx* | linux-gnu* | linux-android* | linux-dietlibc | linux-newlib* | \ + linux-musl* | linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | \ + knetbsd*-gnu* | netbsd*-gnu* | \ + kopensolaris*-gnu* | \ + storm-chaos* | os2-emx* | rtmk-nova*) + os=-$maybe_os + basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'` + ;; + android-linux) + os=-linux-android + basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'`-unknown + ;; + *) + basic_machine=`echo $1 | sed 's/-[^-]*$//'` + if [ $basic_machine != $1 ] + then os=`echo $1 | sed 's/.*-/-/'` + else os=; fi + ;; +esac + +### Let's recognize common machines as not being operating systems so +### that things like config.sub decstation-3100 work. We also +### recognize some manufacturers as not being operating systems, so we +### can provide default operating systems below. +case $os in + -sun*os*) + # Prevent following clause from handling this invalid input. + ;; + -dec* | -mips* | -sequent* | -encore* | -pc532* | -sgi* | -sony* | \ + -att* | -7300* | -3300* | -delta* | -motorola* | -sun[234]* | \ + -unicom* | -ibm* | -next | -hp | -isi* | -apollo | -altos* | \ + -convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\ + -c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \ + -harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \ + -apple | -axis | -knuth | -cray | -microblaze*) + os= + basic_machine=$1 + ;; + -bluegene*) + os=-cnk + ;; + -sim | -cisco | -oki | -wec | -winbond) + os= + basic_machine=$1 + ;; + -scout) + ;; + -wrs) + os=-vxworks + basic_machine=$1 + ;; + -chorusos*) + os=-chorusos + basic_machine=$1 + ;; + -chorusrdb) + os=-chorusrdb + basic_machine=$1 + ;; + -hiux*) + os=-hiuxwe2 + ;; + -sco6) + os=-sco5v6 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco5) + os=-sco3.2v5 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco4) + os=-sco3.2v4 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco3.2.[4-9]*) + os=`echo $os | sed -e 's/sco3.2./sco3.2v/'` + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco3.2v[4-9]*) + # Don't forget version if it is 3.2v4 or newer. + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco5v6*) + # Don't forget version if it is 3.2v4 or newer. + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco*) + os=-sco3.2v2 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -udk*) + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -isc) + os=-isc2.2 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -clix*) + basic_machine=clipper-intergraph + ;; + -isc*) + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -lynx*178) + os=-lynxos178 + ;; + -lynx*5) + os=-lynxos5 + ;; + -lynx*) + os=-lynxos + ;; + -ptx*) + basic_machine=`echo $1 | sed -e 's/86-.*/86-sequent/'` + ;; + -windowsnt*) + os=`echo $os | sed -e 's/windowsnt/winnt/'` + ;; + -psos*) + os=-psos + ;; + -mint | -mint[0-9]*) + basic_machine=m68k-atari + os=-mint + ;; +esac + +# Decode aliases for certain CPU-COMPANY combinations. +case $basic_machine in + # Recognize the basic CPU types without company name. + # Some are omitted here because they have special meanings below. + 1750a | 580 \ + | a29k \ + | aarch64 | aarch64_be \ + | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ + | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ + | am33_2.0 \ + | arc | arceb \ + | arm | arm[bl]e | arme[lb] | armv[2-8] | armv[3-8][lb] | armv7[arm] \ + | avr | avr32 \ + | be32 | be64 \ + | bfin \ + | c4x | c8051 | clipper \ + | d10v | d30v | dlx | dsp16xx \ + | epiphany \ + | fido | fr30 | frv \ + | h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \ + | hexagon \ + | i370 | i860 | i960 | ia64 \ + | ip2k | iq2000 \ + | k1om \ + | le32 | le64 \ + | lm32 \ + | m32c | m32r | m32rle | m68000 | m68k | m88k \ + | maxq | mb | microblaze | microblazeel | mcore | mep | metag \ + | mips | mipsbe | mipseb | mipsel | mipsle \ + | mips16 \ + | mips64 | mips64el \ + | mips64octeon | mips64octeonel \ + | mips64orion | mips64orionel \ + | mips64r5900 | mips64r5900el \ + | mips64vr | mips64vrel \ + | mips64vr4100 | mips64vr4100el \ + | mips64vr4300 | mips64vr4300el \ + | mips64vr5000 | mips64vr5000el \ + | mips64vr5900 | mips64vr5900el \ + | mipsisa32 | mipsisa32el \ + | mipsisa32r2 | mipsisa32r2el \ + | mipsisa64 | mipsisa64el \ + | mipsisa64r2 | mipsisa64r2el \ + | mipsisa64sb1 | mipsisa64sb1el \ + | mipsisa64sr71k | mipsisa64sr71kel \ + | mipsr5900 | mipsr5900el \ + | mipstx39 | mipstx39el \ + | mn10200 | mn10300 \ + | moxie \ + | mt \ + | msp430 \ + | nds32 | nds32le | nds32be \ + | nios | nios2 | nios2eb | nios2el \ + | ns16k | ns32k \ + | open8 \ + | or1k | or32 \ + | pdp10 | pdp11 | pj | pjl \ + | powerpc | powerpc64 | powerpc64le | powerpcle \ + | pyramid \ + | rl78 | rx \ + | score \ + | sh | sh[1234] | sh[24]a | sh[24]aeb | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \ + | sh64 | sh64le \ + | sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet | sparclite \ + | sparcv8 | sparcv9 | sparcv9b | sparcv9v \ + | spu \ + | tahoe | tic4x | tic54x | tic55x | tic6x | tic80 | tron \ + | ubicom32 \ + | v850 | v850e | v850e1 | v850e2 | v850es | v850e2v3 \ + | we32k \ + | x86 | xc16x | xstormy16 | xtensa \ + | z8k | z80) + basic_machine=$basic_machine-unknown + ;; + c54x) + basic_machine=tic54x-unknown + ;; + c55x) + basic_machine=tic55x-unknown + ;; + c6x) + basic_machine=tic6x-unknown + ;; + m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x | nvptx | picochip) + basic_machine=$basic_machine-unknown + os=-none + ;; + m88110 | m680[12346]0 | m683?2 | m68360 | m5200 | v70 | w65 | z8k) + ;; + ms1) + basic_machine=mt-unknown + ;; + + strongarm | thumb | xscale) + basic_machine=arm-unknown + ;; + xgate) + basic_machine=$basic_machine-unknown + os=-none + ;; + xscaleeb) + basic_machine=armeb-unknown + ;; + + xscaleel) + basic_machine=armel-unknown + ;; + + # We use `pc' rather than `unknown' + # because (1) that's what they normally are, and + # (2) the word "unknown" tends to confuse beginning users. + i*86 | x86_64) + basic_machine=$basic_machine-pc + ;; + # Object if more than one company name word. + *-*-*) + echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 + exit 1 + ;; + # Recognize the basic CPU types with company name. + 580-* \ + | a29k-* \ + | aarch64-* | aarch64_be-* \ + | alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \ + | alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \ + | alphapca5[67]-* | alpha64pca5[67]-* | arc-* | arceb-* \ + | arm-* | armbe-* | armle-* | armeb-* | armv*-* \ + | avr-* | avr32-* \ + | be32-* | be64-* \ + | bfin-* | bs2000-* \ + | c[123]* | c30-* | [cjt]90-* | c4x-* \ + | c8051-* | clipper-* | craynv-* | cydra-* \ + | d10v-* | d30v-* | dlx-* \ + | elxsi-* \ + | f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \ + | h8300-* | h8500-* \ + | hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \ + | hexagon-* \ + | i*86-* | i860-* | i960-* | ia64-* \ + | ip2k-* | iq2000-* \ + | k1om-* \ + | le32-* | le64-* \ + | lm32-* \ + | m32c-* | m32r-* | m32rle-* \ + | m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \ + | m88110-* | m88k-* | maxq-* | mcore-* | metag-* \ + | microblaze-* | microblazeel-* \ + | mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \ + | mips16-* \ + | mips64-* | mips64el-* \ + | mips64octeon-* | mips64octeonel-* \ + | mips64orion-* | mips64orionel-* \ + | mips64r5900-* | mips64r5900el-* \ + | mips64vr-* | mips64vrel-* \ + | mips64vr4100-* | mips64vr4100el-* \ + | mips64vr4300-* | mips64vr4300el-* \ + | mips64vr5000-* | mips64vr5000el-* \ + | mips64vr5900-* | mips64vr5900el-* \ + | mipsisa32-* | mipsisa32el-* \ + | mipsisa32r2-* | mipsisa32r2el-* \ + | mipsisa64-* | mipsisa64el-* \ + | mipsisa64r2-* | mipsisa64r2el-* \ + | mipsisa64sb1-* | mipsisa64sb1el-* \ + | mipsisa64sr71k-* | mipsisa64sr71kel-* \ + | mipsr5900-* | mipsr5900el-* \ + | mipstx39-* | mipstx39el-* \ + | mmix-* \ + | mt-* \ + | msp430-* \ + | nds32-* | nds32le-* | nds32be-* \ + | nios-* | nios2-* | nios2eb-* | nios2el-* \ + | none-* | np1-* | ns16k-* | ns32k-* \ + | open8-* \ + | orion-* \ + | pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \ + | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* \ + | pyramid-* \ + | rl78-* | romp-* | rs6000-* | rx-* \ + | sh-* | sh[1234]-* | sh[24]a-* | sh[24]aeb-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \ + | shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \ + | sparc-* | sparc64-* | sparc64b-* | sparc64v-* | sparc86x-* | sparclet-* \ + | sparclite-* \ + | sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | sv1-* | sx?-* \ + | tahoe-* \ + | tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* \ + | tile*-* \ + | tron-* \ + | ubicom32-* \ + | v850-* | v850e-* | v850e1-* | v850es-* | v850e2-* | v850e2v3-* \ + | vax-* \ + | we32k-* \ + | x86-* | x86_64-* | xc16x-* | xps100-* \ + | xstormy16-* | xtensa*-* \ + | ymp-* \ + | z8k-* | z80-*) + ;; + # Recognize the basic CPU types without company name, with glob match. + xtensa*) + basic_machine=$basic_machine-unknown + ;; + # Recognize the various machine names and aliases which stand + # for a CPU type and a company and sometimes even an OS. + 386bsd) + basic_machine=i386-unknown + os=-bsd + ;; + 3b1 | 7300 | 7300-att | att-7300 | pc7300 | safari | unixpc) + basic_machine=m68000-att + ;; + 3b*) + basic_machine=we32k-att + ;; + a29khif) + basic_machine=a29k-amd + os=-udi + ;; + abacus) + basic_machine=abacus-unknown + ;; + adobe68k) + basic_machine=m68010-adobe + os=-scout + ;; + alliant | fx80) + basic_machine=fx80-alliant + ;; + altos | altos3068) + basic_machine=m68k-altos + ;; + am29k) + basic_machine=a29k-none + os=-bsd + ;; + amd64) + basic_machine=x86_64-pc + ;; + amd64-*) + basic_machine=x86_64-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + amdahl) + basic_machine=580-amdahl + os=-sysv + ;; + amiga | amiga-*) + basic_machine=m68k-unknown + ;; + amigaos | amigados) + basic_machine=m68k-unknown + os=-amigaos + ;; + amigaunix | amix) + basic_machine=m68k-unknown + os=-sysv4 + ;; + apollo68) + basic_machine=m68k-apollo + os=-sysv + ;; + apollo68bsd) + basic_machine=m68k-apollo + os=-bsd + ;; + aros) + basic_machine=i386-pc + os=-aros + ;; + aux) + basic_machine=m68k-apple + os=-aux + ;; + balance) + basic_machine=ns32k-sequent + os=-dynix + ;; + blackfin) + basic_machine=bfin-unknown + os=-linux + ;; + blackfin-*) + basic_machine=bfin-`echo $basic_machine | sed 's/^[^-]*-//'` + os=-linux + ;; + bluegene*) + basic_machine=powerpc-ibm + os=-cnk + ;; + c54x-*) + basic_machine=tic54x-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + c55x-*) + basic_machine=tic55x-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + c6x-*) + basic_machine=tic6x-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + c90) + basic_machine=c90-cray + os=-unicos + ;; + cegcc) + basic_machine=arm-unknown + os=-cegcc + ;; + convex-c1) + basic_machine=c1-convex + os=-bsd + ;; + convex-c2) + basic_machine=c2-convex + os=-bsd + ;; + convex-c32) + basic_machine=c32-convex + os=-bsd + ;; + convex-c34) + basic_machine=c34-convex + os=-bsd + ;; + convex-c38) + basic_machine=c38-convex + os=-bsd + ;; + cray | j90) + basic_machine=j90-cray + os=-unicos + ;; + craynv) + basic_machine=craynv-cray + os=-unicosmp + ;; + cr16 | cr16-*) + basic_machine=cr16-unknown + os=-elf + ;; + crds | unos) + basic_machine=m68k-crds + ;; + crisv32 | crisv32-* | etraxfs*) + basic_machine=crisv32-axis + ;; + cris | cris-* | etrax*) + basic_machine=cris-axis + ;; + crx) + basic_machine=crx-unknown + os=-elf + ;; + da30 | da30-*) + basic_machine=m68k-da30 + ;; + decstation | decstation-3100 | pmax | pmax-* | pmin | dec3100 | decstatn) + basic_machine=mips-dec + ;; + decsystem10* | dec10*) + basic_machine=pdp10-dec + os=-tops10 + ;; + decsystem20* | dec20*) + basic_machine=pdp10-dec + os=-tops20 + ;; + delta | 3300 | motorola-3300 | motorola-delta \ + | 3300-motorola | delta-motorola) + basic_machine=m68k-motorola + ;; + delta88) + basic_machine=m88k-motorola + os=-sysv3 + ;; + dicos) + basic_machine=i686-pc + os=-dicos + ;; + djgpp) + basic_machine=i586-pc + os=-msdosdjgpp + ;; + dpx20 | dpx20-*) + basic_machine=rs6000-bull + os=-bosx + ;; + dpx2* | dpx2*-bull) + basic_machine=m68k-bull + os=-sysv3 + ;; + ebmon29k) + basic_machine=a29k-amd + os=-ebmon + ;; + elxsi) + basic_machine=elxsi-elxsi + os=-bsd + ;; + encore | umax | mmax) + basic_machine=ns32k-encore + ;; + es1800 | OSE68k | ose68k | ose | OSE) + basic_machine=m68k-ericsson + os=-ose + ;; + fx2800) + basic_machine=i860-alliant + ;; + genix) + basic_machine=ns32k-ns + ;; + gmicro) + basic_machine=tron-gmicro + os=-sysv + ;; + go32) + basic_machine=i386-pc + os=-go32 + ;; + h3050r* | hiux*) + basic_machine=hppa1.1-hitachi + os=-hiuxwe2 + ;; + h8300hms) + basic_machine=h8300-hitachi + os=-hms + ;; + h8300xray) + basic_machine=h8300-hitachi + os=-xray + ;; + h8500hms) + basic_machine=h8500-hitachi + os=-hms + ;; + harris) + basic_machine=m88k-harris + os=-sysv3 + ;; + hp300-*) + basic_machine=m68k-hp + ;; + hp300bsd) + basic_machine=m68k-hp + os=-bsd + ;; + hp300hpux) + basic_machine=m68k-hp + os=-hpux + ;; + hp3k9[0-9][0-9] | hp9[0-9][0-9]) + basic_machine=hppa1.0-hp + ;; + hp9k2[0-9][0-9] | hp9k31[0-9]) + basic_machine=m68000-hp + ;; + hp9k3[2-9][0-9]) + basic_machine=m68k-hp + ;; + hp9k6[0-9][0-9] | hp6[0-9][0-9]) + basic_machine=hppa1.0-hp + ;; + hp9k7[0-79][0-9] | hp7[0-79][0-9]) + basic_machine=hppa1.1-hp + ;; + hp9k78[0-9] | hp78[0-9]) + # FIXME: really hppa2.0-hp + basic_machine=hppa1.1-hp + ;; + hp9k8[67]1 | hp8[67]1 | hp9k80[24] | hp80[24] | hp9k8[78]9 | hp8[78]9 | hp9k893 | hp893) + # FIXME: really hppa2.0-hp + basic_machine=hppa1.1-hp + ;; + hp9k8[0-9][13679] | hp8[0-9][13679]) + basic_machine=hppa1.1-hp + ;; + hp9k8[0-9][0-9] | hp8[0-9][0-9]) + basic_machine=hppa1.0-hp + ;; + hppa-next) + os=-nextstep3 + ;; + hppaosf) + basic_machine=hppa1.1-hp + os=-osf + ;; + hppro) + basic_machine=hppa1.1-hp + os=-proelf + ;; + i370-ibm* | ibm*) + basic_machine=i370-ibm + ;; + i*86v32) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-sysv32 + ;; + i*86v4*) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-sysv4 + ;; + i*86v) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-sysv + ;; + i*86sol2) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-solaris2 + ;; + i386mach) + basic_machine=i386-mach + os=-mach + ;; + i386-vsta | vsta) + basic_machine=i386-unknown + os=-vsta + ;; + iris | iris4d) + basic_machine=mips-sgi + case $os in + -irix*) + ;; + *) + os=-irix4 + ;; + esac + ;; + isi68 | isi) + basic_machine=m68k-isi + os=-sysv + ;; + m68knommu) + basic_machine=m68k-unknown + os=-linux + ;; + m68knommu-*) + basic_machine=m68k-`echo $basic_machine | sed 's/^[^-]*-//'` + os=-linux + ;; + m88k-omron*) + basic_machine=m88k-omron + ;; + magnum | m3230) + basic_machine=mips-mips + os=-sysv + ;; + merlin) + basic_machine=ns32k-utek + os=-sysv + ;; + microblaze*) + basic_machine=microblaze-xilinx + ;; + mingw64) + basic_machine=x86_64-pc + os=-mingw64 + ;; + mingw32) + basic_machine=i686-pc + os=-mingw32 + ;; + mingw32ce) + basic_machine=arm-unknown + os=-mingw32ce + ;; + miniframe) + basic_machine=m68000-convergent + ;; + *mint | -mint[0-9]* | *MiNT | *MiNT[0-9]*) + basic_machine=m68k-atari + os=-mint + ;; + mips3*-*) + basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'` + ;; + mips3*) + basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`-unknown + ;; + monitor) + basic_machine=m68k-rom68k + os=-coff + ;; + morphos) + basic_machine=powerpc-unknown + os=-morphos + ;; + msdos) + basic_machine=i386-pc + os=-msdos + ;; + ms1-*) + basic_machine=`echo $basic_machine | sed -e 's/ms1-/mt-/'` + ;; + msys) + basic_machine=i686-pc + os=-msys + ;; + mvs) + basic_machine=i370-ibm + os=-mvs + ;; + nacl) + basic_machine=le32-unknown + os=-nacl + ;; + ncr3000) + basic_machine=i486-ncr + os=-sysv4 + ;; + netbsd386) + basic_machine=i386-unknown + os=-netbsd + ;; + netwinder) + basic_machine=armv4l-rebel + os=-linux + ;; + news | news700 | news800 | news900) + basic_machine=m68k-sony + os=-newsos + ;; + news1000) + basic_machine=m68030-sony + os=-newsos + ;; + news-3600 | risc-news) + basic_machine=mips-sony + os=-newsos + ;; + necv70) + basic_machine=v70-nec + os=-sysv + ;; + next | m*-next ) + basic_machine=m68k-next + case $os in + -nextstep* ) + ;; + -ns2*) + os=-nextstep2 + ;; + *) + os=-nextstep3 + ;; + esac + ;; + nh3000) + basic_machine=m68k-harris + os=-cxux + ;; + nh[45]000) + basic_machine=m88k-harris + os=-cxux + ;; + nindy960) + basic_machine=i960-intel + os=-nindy + ;; + mon960) + basic_machine=i960-intel + os=-mon960 + ;; + nonstopux) + basic_machine=mips-compaq + os=-nonstopux + ;; + np1) + basic_machine=np1-gould + ;; + neo-tandem) + basic_machine=neo-tandem + ;; + nse-tandem) + basic_machine=nse-tandem + ;; + nsr-tandem) + basic_machine=nsr-tandem + ;; + op50n-* | op60c-*) + basic_machine=hppa1.1-oki + os=-proelf + ;; + openrisc | openrisc-*) + basic_machine=or32-unknown + ;; + os400) + basic_machine=powerpc-ibm + os=-os400 + ;; + OSE68000 | ose68000) + basic_machine=m68000-ericsson + os=-ose + ;; + os68k) + basic_machine=m68k-none + os=-os68k + ;; + pa-hitachi) + basic_machine=hppa1.1-hitachi + os=-hiuxwe2 + ;; + paragon) + basic_machine=i860-intel + os=-osf + ;; + parisc) + basic_machine=hppa-unknown + os=-linux + ;; + parisc-*) + basic_machine=hppa-`echo $basic_machine | sed 's/^[^-]*-//'` + os=-linux + ;; + pbd) + basic_machine=sparc-tti + ;; + pbb) + basic_machine=m68k-tti + ;; + pc532 | pc532-*) + basic_machine=ns32k-pc532 + ;; + pc98) + basic_machine=i386-pc + ;; + pc98-*) + basic_machine=i386-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pentium | p5 | k5 | k6 | nexgen | viac3) + basic_machine=i586-pc + ;; + pentiumpro | p6 | 6x86 | athlon | athlon_*) + basic_machine=i686-pc + ;; + pentiumii | pentium2 | pentiumiii | pentium3) + basic_machine=i686-pc + ;; + pentium4) + basic_machine=i786-pc + ;; + pentium-* | p5-* | k5-* | k6-* | nexgen-* | viac3-*) + basic_machine=i586-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pentiumpro-* | p6-* | 6x86-* | athlon-*) + basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pentiumii-* | pentium2-* | pentiumiii-* | pentium3-*) + basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pentium4-*) + basic_machine=i786-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pn) + basic_machine=pn-gould + ;; + power) basic_machine=power-ibm + ;; + ppc | ppcbe) basic_machine=powerpc-unknown + ;; + ppc-* | ppcbe-*) + basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ppcle | powerpclittle | ppc-le | powerpc-little) + basic_machine=powerpcle-unknown + ;; + ppcle-* | powerpclittle-*) + basic_machine=powerpcle-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ppc64) basic_machine=powerpc64-unknown + ;; + ppc64-*) basic_machine=powerpc64-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ppc64le | powerpc64little | ppc64-le | powerpc64-little) + basic_machine=powerpc64le-unknown + ;; + ppc64le-* | powerpc64little-*) + basic_machine=powerpc64le-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ps2) + basic_machine=i386-ibm + ;; + pw32) + basic_machine=i586-unknown + os=-pw32 + ;; + rdos | rdos64) + basic_machine=x86_64-pc + os=-rdos + ;; + rdos32) + basic_machine=i386-pc + os=-rdos + ;; + rom68k) + basic_machine=m68k-rom68k + os=-coff + ;; + rm[46]00) + basic_machine=mips-siemens + ;; + rtpc | rtpc-*) + basic_machine=romp-ibm + ;; + s390 | s390-*) + basic_machine=s390-ibm + ;; + s390x | s390x-*) + basic_machine=s390x-ibm + ;; + sa29200) + basic_machine=a29k-amd + os=-udi + ;; + sb1) + basic_machine=mipsisa64sb1-unknown + ;; + sb1el) + basic_machine=mipsisa64sb1el-unknown + ;; + sde) + basic_machine=mipsisa32-sde + os=-elf + ;; + sei) + basic_machine=mips-sei + os=-seiux + ;; + sequent) + basic_machine=i386-sequent + ;; + sh) + basic_machine=sh-hitachi + os=-hms + ;; + sh5el) + basic_machine=sh5le-unknown + ;; + sh64) + basic_machine=sh64-unknown + ;; + sparclite-wrs | simso-wrs) + basic_machine=sparclite-wrs + os=-vxworks + ;; + sps7) + basic_machine=m68k-bull + os=-sysv2 + ;; + spur) + basic_machine=spur-unknown + ;; + st2000) + basic_machine=m68k-tandem + ;; + stratus) + basic_machine=i860-stratus + os=-sysv4 + ;; + strongarm-* | thumb-*) + basic_machine=arm-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + sun2) + basic_machine=m68000-sun + ;; + sun2os3) + basic_machine=m68000-sun + os=-sunos3 + ;; + sun2os4) + basic_machine=m68000-sun + os=-sunos4 + ;; + sun3os3) + basic_machine=m68k-sun + os=-sunos3 + ;; + sun3os4) + basic_machine=m68k-sun + os=-sunos4 + ;; + sun4os3) + basic_machine=sparc-sun + os=-sunos3 + ;; + sun4os4) + basic_machine=sparc-sun + os=-sunos4 + ;; + sun4sol2) + basic_machine=sparc-sun + os=-solaris2 + ;; + sun3 | sun3-*) + basic_machine=m68k-sun + ;; + sun4) + basic_machine=sparc-sun + ;; + sun386 | sun386i | roadrunner) + basic_machine=i386-sun + ;; + sv1) + basic_machine=sv1-cray + os=-unicos + ;; + symmetry) + basic_machine=i386-sequent + os=-dynix + ;; + t3e) + basic_machine=alphaev5-cray + os=-unicos + ;; + t90) + basic_machine=t90-cray + os=-unicos + ;; + tile*) + basic_machine=$basic_machine-unknown + os=-linux-gnu + ;; + tx39) + basic_machine=mipstx39-unknown + ;; + tx39el) + basic_machine=mipstx39el-unknown + ;; + toad1) + basic_machine=pdp10-xkl + os=-tops20 + ;; + tower | tower-32) + basic_machine=m68k-ncr + ;; + tpf) + basic_machine=s390x-ibm + os=-tpf + ;; + udi29k) + basic_machine=a29k-amd + os=-udi + ;; + ultra3) + basic_machine=a29k-nyu + os=-sym1 + ;; + v810 | necv810) + basic_machine=v810-nec + os=-none + ;; + vaxv) + basic_machine=vax-dec + os=-sysv + ;; + vms) + basic_machine=vax-dec + os=-vms + ;; + vpp*|vx|vx-*) + basic_machine=f301-fujitsu + ;; + vxworks960) + basic_machine=i960-wrs + os=-vxworks + ;; + vxworks68) + basic_machine=m68k-wrs + os=-vxworks + ;; + vxworks29k) + basic_machine=a29k-wrs + os=-vxworks + ;; + w65*) + basic_machine=w65-wdc + os=-none + ;; + w89k-*) + basic_machine=hppa1.1-winbond + os=-proelf + ;; + xbox) + basic_machine=i686-pc + os=-mingw32 + ;; + xps | xps100) + basic_machine=xps100-honeywell + ;; + xscale-* | xscalee[bl]-*) + basic_machine=`echo $basic_machine | sed 's/^xscale/arm/'` + ;; + ymp) + basic_machine=ymp-cray + os=-unicos + ;; + z8k-*-coff) + basic_machine=z8k-unknown + os=-sim + ;; + z80-*-coff) + basic_machine=z80-unknown + os=-sim + ;; + none) + basic_machine=none-none + os=-none + ;; + +# Here we handle the default manufacturer of certain CPU types. It is in +# some cases the only manufacturer, in others, it is the most popular. + w89k) + basic_machine=hppa1.1-winbond + ;; + op50n) + basic_machine=hppa1.1-oki + ;; + op60c) + basic_machine=hppa1.1-oki + ;; + romp) + basic_machine=romp-ibm + ;; + mmix) + basic_machine=mmix-knuth + ;; + rs6000) + basic_machine=rs6000-ibm + ;; + vax) + basic_machine=vax-dec + ;; + pdp10) + # there are many clones, so DEC is not a safe bet + basic_machine=pdp10-unknown + ;; + pdp11) + basic_machine=pdp11-dec + ;; + we32k) + basic_machine=we32k-att + ;; + sh[1234] | sh[24]a | sh[24]aeb | sh[34]eb | sh[1234]le | sh[23]ele) + basic_machine=sh-unknown + ;; + sparc | sparcv8 | sparcv9 | sparcv9b | sparcv9v) + basic_machine=sparc-sun + ;; + cydra) + basic_machine=cydra-cydrome + ;; + orion) + basic_machine=orion-highlevel + ;; + orion105) + basic_machine=clipper-highlevel + ;; + mac | mpw | mac-mpw) + basic_machine=m68k-apple + ;; + pmac | pmac-mpw) + basic_machine=powerpc-apple + ;; + *-unknown) + # Make sure to match an already-canonicalized machine name. + ;; + *) + echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 + exit 1 + ;; +esac + +# Here we canonicalize certain aliases for manufacturers. +case $basic_machine in + *-digital*) + basic_machine=`echo $basic_machine | sed 's/digital.*/dec/'` + ;; + *-commodore*) + basic_machine=`echo $basic_machine | sed 's/commodore.*/cbm/'` + ;; + *) + ;; +esac + +# Decode manufacturer-specific aliases for certain operating systems. + +if [ x"$os" != x"" ] +then +case $os in + # First match some system type aliases + # that might get confused with valid system types. + # -solaris* is a basic system type, with this one exception. + -auroraux) + os=-auroraux + ;; + -solaris1 | -solaris1.*) + os=`echo $os | sed -e 's|solaris1|sunos4|'` + ;; + -solaris) + os=-solaris2 + ;; + -svr4*) + os=-sysv4 + ;; + -unixware*) + os=-sysv4.2uw + ;; + -gnu/linux*) + os=`echo $os | sed -e 's|gnu/linux|linux-gnu|'` + ;; + # First accept the basic system types. + # The portable systems comes first. + # Each alternative MUST END IN A *, to match a version number. + # -sysv* is not here because it comes later, after sysvr4. + -gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \ + | -*vms* | -sco* | -esix* | -isc* | -aix* | -cnk* | -sunos | -sunos[34]*\ + | -hpux* | -unos* | -osf* | -luna* | -dgux* | -auroraux* | -solaris* \ + | -sym* | -kopensolaris* | -plan9* \ + | -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \ + | -aos* | -aros* \ + | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \ + | -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \ + | -hiux* | -386bsd* | -knetbsd* | -mirbsd* | -netbsd* \ + | -bitrig* | -openbsd* | -solidbsd* \ + | -ekkobsd* | -kfreebsd* | -freebsd* | -riscix* | -lynxos* \ + | -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \ + | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \ + | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \ + | -chorusos* | -chorusrdb* | -cegcc* \ + | -cygwin* | -msys* | -pe* | -psos* | -moss* | -proelf* | -rtems* \ + | -mingw32* | -mingw64* | -linux-gnu* | -linux-android* \ + | -linux-newlib* | -linux-musl* | -linux-uclibc* \ + | -uxpv* | -beos* | -mpeix* | -udk* \ + | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \ + | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \ + | -storm-chaos* | -tops10* | -tenex* | -tops20* | -its* \ + | -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \ + | -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \ + | -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly* \ + | -skyos* | -haiku* | -rdos* | -toppers* | -drops* | -es*) + # Remember, each alternative MUST END IN *, to match a version number. + ;; + -qnx*) + case $basic_machine in + x86-* | i*86-*) + ;; + *) + os=-nto$os + ;; + esac + ;; + -nto-qnx*) + ;; + -nto*) + os=`echo $os | sed -e 's|nto|nto-qnx|'` + ;; + -sim | -es1800* | -hms* | -xray | -os68k* | -none* | -v88r* \ + | -windows* | -osx | -abug | -netware* | -os9* | -beos* | -haiku* \ + | -macos* | -mpw* | -magic* | -mmixware* | -mon960* | -lnews*) + ;; + -mac*) + os=`echo $os | sed -e 's|mac|macos|'` + ;; + -linux-dietlibc) + os=-linux-dietlibc + ;; + -linux*) + os=`echo $os | sed -e 's|linux|linux-gnu|'` + ;; + -sunos5*) + os=`echo $os | sed -e 's|sunos5|solaris2|'` + ;; + -sunos6*) + os=`echo $os | sed -e 's|sunos6|solaris3|'` + ;; + -opened*) + os=-openedition + ;; + -os400*) + os=-os400 + ;; + -wince*) + os=-wince + ;; + -osfrose*) + os=-osfrose + ;; + -osf*) + os=-osf + ;; + -utek*) + os=-bsd + ;; + -dynix*) + os=-bsd + ;; + -acis*) + os=-aos + ;; + -atheos*) + os=-atheos + ;; + -syllable*) + os=-syllable + ;; + -386bsd) + os=-bsd + ;; + -ctix* | -uts*) + os=-sysv + ;; + -nova*) + os=-rtmk-nova + ;; + -ns2 ) + os=-nextstep2 + ;; + -nsk*) + os=-nsk + ;; + # Preserve the version number of sinix5. + -sinix5.*) + os=`echo $os | sed -e 's|sinix|sysv|'` + ;; + -sinix*) + os=-sysv4 + ;; + -tpf*) + os=-tpf + ;; + -triton*) + os=-sysv3 + ;; + -oss*) + os=-sysv3 + ;; + -svr4) + os=-sysv4 + ;; + -svr3) + os=-sysv3 + ;; + -sysvr4) + os=-sysv4 + ;; + # This must come after -sysvr4. + -sysv*) + ;; + -ose*) + os=-ose + ;; + -es1800*) + os=-ose + ;; + -xenix) + os=-xenix + ;; + -*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*) + os=-mint + ;; + -aros*) + os=-aros + ;; + -zvmoe) + os=-zvmoe + ;; + -dicos*) + os=-dicos + ;; + -nacl*) + ;; + -none) + ;; + *) + # Get rid of the `-' at the beginning of $os. + os=`echo $os | sed 's/[^-]*-//'` + echo Invalid configuration \`$1\': system \`$os\' not recognized 1>&2 + exit 1 + ;; +esac +else + +# Here we handle the default operating systems that come with various machines. +# The value should be what the vendor currently ships out the door with their +# machine or put another way, the most popular os provided with the machine. + +# Note that if you're going to try to match "-MANUFACTURER" here (say, +# "-sun"), then you have to tell the case statement up towards the top +# that MANUFACTURER isn't an operating system. Otherwise, code above +# will signal an error saying that MANUFACTURER isn't an operating +# system, and we'll never get to this point. + +case $basic_machine in + score-*) + os=-elf + ;; + spu-*) + os=-elf + ;; + *-acorn) + os=-riscix1.2 + ;; + arm*-rebel) + os=-linux + ;; + arm*-semi) + os=-aout + ;; + c4x-* | tic4x-*) + os=-coff + ;; + c8051-*) + os=-elf + ;; + hexagon-*) + os=-elf + ;; + tic54x-*) + os=-coff + ;; + tic55x-*) + os=-coff + ;; + tic6x-*) + os=-coff + ;; + # This must come before the *-dec entry. + pdp10-*) + os=-tops20 + ;; + pdp11-*) + os=-none + ;; + *-dec | vax-*) + os=-ultrix4.2 + ;; + m68*-apollo) + os=-domain + ;; + i386-sun) + os=-sunos4.0.2 + ;; + m68000-sun) + os=-sunos3 + ;; + m68*-cisco) + os=-aout + ;; + mep-*) + os=-elf + ;; + mips*-cisco) + os=-elf + ;; + mips*-*) + os=-elf + ;; + or1k-*) + os=-elf + ;; + or32-*) + os=-coff + ;; + *-tti) # must be before sparc entry or we get the wrong os. + os=-sysv3 + ;; + sparc-* | *-sun) + os=-sunos4.1.1 + ;; + *-be) + os=-beos + ;; + *-haiku) + os=-haiku + ;; + *-ibm) + os=-aix + ;; + *-knuth) + os=-mmixware + ;; + *-wec) + os=-proelf + ;; + *-winbond) + os=-proelf + ;; + *-oki) + os=-proelf + ;; + *-hp) + os=-hpux + ;; + *-hitachi) + os=-hiux + ;; + i860-* | *-att | *-ncr | *-altos | *-motorola | *-convergent) + os=-sysv + ;; + *-cbm) + os=-amigaos + ;; + *-dg) + os=-dgux + ;; + *-dolphin) + os=-sysv3 + ;; + m68k-ccur) + os=-rtu + ;; + m88k-omron*) + os=-luna + ;; + *-next ) + os=-nextstep + ;; + *-sequent) + os=-ptx + ;; + *-crds) + os=-unos + ;; + *-ns) + os=-genix + ;; + i370-*) + os=-mvs + ;; + *-next) + os=-nextstep3 + ;; + *-gould) + os=-sysv + ;; + *-highlevel) + os=-bsd + ;; + *-encore) + os=-bsd + ;; + *-sgi) + os=-irix + ;; + *-siemens) + os=-sysv4 + ;; + *-masscomp) + os=-rtu + ;; + f30[01]-fujitsu | f700-fujitsu) + os=-uxpv + ;; + *-rom68k) + os=-coff + ;; + *-*bug) + os=-coff + ;; + *-apple) + os=-macos + ;; + *-atari*) + os=-mint + ;; + *) + os=-none + ;; +esac +fi + +# Here we handle the case where we know the os, and the CPU type, but not the +# manufacturer. We pick the logical manufacturer. +vendor=unknown +case $basic_machine in + *-unknown) + case $os in + -riscix*) + vendor=acorn + ;; + -sunos*) + vendor=sun + ;; + -cnk*|-aix*) + vendor=ibm + ;; + -beos*) + vendor=be + ;; + -hpux*) + vendor=hp + ;; + -mpeix*) + vendor=hp + ;; + -hiux*) + vendor=hitachi + ;; + -unos*) + vendor=crds + ;; + -dgux*) + vendor=dg + ;; + -luna*) + vendor=omron + ;; + -genix*) + vendor=ns + ;; + -mvs* | -opened*) + vendor=ibm + ;; + -os400*) + vendor=ibm + ;; + -ptx*) + vendor=sequent + ;; + -tpf*) + vendor=ibm + ;; + -vxsim* | -vxworks* | -windiss*) + vendor=wrs + ;; + -aux*) + vendor=apple + ;; + -hms*) + vendor=hitachi + ;; + -mpw* | -macos*) + vendor=apple + ;; + -*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*) + vendor=atari + ;; + -vos*) + vendor=stratus + ;; + esac + basic_machine=`echo $basic_machine | sed "s/unknown/$vendor/"` + ;; +esac + +echo $basic_machine$os +exit + +# Local variables: +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "timestamp='" +# time-stamp-format: "%:y-%02m-%02d" +# time-stamp-end: "'" +# End: diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/depcomp b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/depcomp new file mode 100644 index 0000000..4ebd5b3 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/depcomp @@ -0,0 +1,791 @@ +#! /bin/sh +# depcomp - compile a program generating dependencies as side-effects + +scriptversion=2013-05-30.07; # UTC + +# Copyright (C) 1999-2013 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that program. + +# Originally written by Alexandre Oliva . + +case $1 in + '') + echo "$0: No command. Try '$0 --help' for more information." 1>&2 + exit 1; + ;; + -h | --h*) + cat <<\EOF +Usage: depcomp [--help] [--version] PROGRAM [ARGS] + +Run PROGRAMS ARGS to compile a file, generating dependencies +as side-effects. + +Environment variables: + depmode Dependency tracking mode. + source Source file read by 'PROGRAMS ARGS'. + object Object file output by 'PROGRAMS ARGS'. + DEPDIR directory where to store dependencies. + depfile Dependency file to output. + tmpdepfile Temporary file to use when outputting dependencies. + libtool Whether libtool is used (yes/no). + +Report bugs to . +EOF + exit $? + ;; + -v | --v*) + echo "depcomp $scriptversion" + exit $? + ;; +esac + +# Get the directory component of the given path, and save it in the +# global variables '$dir'. Note that this directory component will +# be either empty or ending with a '/' character. This is deliberate. +set_dir_from () +{ + case $1 in + */*) dir=`echo "$1" | sed -e 's|/[^/]*$|/|'`;; + *) dir=;; + esac +} + +# Get the suffix-stripped basename of the given path, and save it the +# global variable '$base'. +set_base_from () +{ + base=`echo "$1" | sed -e 's|^.*/||' -e 's/\.[^.]*$//'` +} + +# If no dependency file was actually created by the compiler invocation, +# we still have to create a dummy depfile, to avoid errors with the +# Makefile "include basename.Plo" scheme. +make_dummy_depfile () +{ + echo "#dummy" > "$depfile" +} + +# Factor out some common post-processing of the generated depfile. +# Requires the auxiliary global variable '$tmpdepfile' to be set. +aix_post_process_depfile () +{ + # If the compiler actually managed to produce a dependency file, + # post-process it. + if test -f "$tmpdepfile"; then + # Each line is of the form 'foo.o: dependency.h'. + # Do two passes, one to just change these to + # $object: dependency.h + # and one to simply output + # dependency.h: + # which is needed to avoid the deleted-header problem. + { sed -e "s,^.*\.[$lower]*:,$object:," < "$tmpdepfile" + sed -e "s,^.*\.[$lower]*:[$tab ]*,," -e 's,$,:,' < "$tmpdepfile" + } > "$depfile" + rm -f "$tmpdepfile" + else + make_dummy_depfile + fi +} + +# A tabulation character. +tab=' ' +# A newline character. +nl=' +' +# Character ranges might be problematic outside the C locale. +# These definitions help. +upper=ABCDEFGHIJKLMNOPQRSTUVWXYZ +lower=abcdefghijklmnopqrstuvwxyz +digits=0123456789 +alpha=${upper}${lower} + +if test -z "$depmode" || test -z "$source" || test -z "$object"; then + echo "depcomp: Variables source, object and depmode must be set" 1>&2 + exit 1 +fi + +# Dependencies for sub/bar.o or sub/bar.obj go into sub/.deps/bar.Po. +depfile=${depfile-`echo "$object" | + sed 's|[^\\/]*$|'${DEPDIR-.deps}'/&|;s|\.\([^.]*\)$|.P\1|;s|Pobj$|Po|'`} +tmpdepfile=${tmpdepfile-`echo "$depfile" | sed 's/\.\([^.]*\)$/.T\1/'`} + +rm -f "$tmpdepfile" + +# Avoid interferences from the environment. +gccflag= dashmflag= + +# Some modes work just like other modes, but use different flags. We +# parameterize here, but still list the modes in the big case below, +# to make depend.m4 easier to write. Note that we *cannot* use a case +# here, because this file can only contain one case statement. +if test "$depmode" = hp; then + # HP compiler uses -M and no extra arg. + gccflag=-M + depmode=gcc +fi + +if test "$depmode" = dashXmstdout; then + # This is just like dashmstdout with a different argument. + dashmflag=-xM + depmode=dashmstdout +fi + +cygpath_u="cygpath -u -f -" +if test "$depmode" = msvcmsys; then + # This is just like msvisualcpp but w/o cygpath translation. + # Just convert the backslash-escaped backslashes to single forward + # slashes to satisfy depend.m4 + cygpath_u='sed s,\\\\,/,g' + depmode=msvisualcpp +fi + +if test "$depmode" = msvc7msys; then + # This is just like msvc7 but w/o cygpath translation. + # Just convert the backslash-escaped backslashes to single forward + # slashes to satisfy depend.m4 + cygpath_u='sed s,\\\\,/,g' + depmode=msvc7 +fi + +if test "$depmode" = xlc; then + # IBM C/C++ Compilers xlc/xlC can output gcc-like dependency information. + gccflag=-qmakedep=gcc,-MF + depmode=gcc +fi + +case "$depmode" in +gcc3) +## gcc 3 implements dependency tracking that does exactly what +## we want. Yay! Note: for some reason libtool 1.4 doesn't like +## it if -MD -MP comes after the -MF stuff. Hmm. +## Unfortunately, FreeBSD c89 acceptance of flags depends upon +## the command line argument order; so add the flags where they +## appear in depend2.am. Note that the slowdown incurred here +## affects only configure: in makefiles, %FASTDEP% shortcuts this. + for arg + do + case $arg in + -c) set fnord "$@" -MT "$object" -MD -MP -MF "$tmpdepfile" "$arg" ;; + *) set fnord "$@" "$arg" ;; + esac + shift # fnord + shift # $arg + done + "$@" + stat=$? + if test $stat -ne 0; then + rm -f "$tmpdepfile" + exit $stat + fi + mv "$tmpdepfile" "$depfile" + ;; + +gcc) +## Note that this doesn't just cater to obsosete pre-3.x GCC compilers. +## but also to in-use compilers like IMB xlc/xlC and the HP C compiler. +## (see the conditional assignment to $gccflag above). +## There are various ways to get dependency output from gcc. Here's +## why we pick this rather obscure method: +## - Don't want to use -MD because we'd like the dependencies to end +## up in a subdir. Having to rename by hand is ugly. +## (We might end up doing this anyway to support other compilers.) +## - The DEPENDENCIES_OUTPUT environment variable makes gcc act like +## -MM, not -M (despite what the docs say). Also, it might not be +## supported by the other compilers which use the 'gcc' depmode. +## - Using -M directly means running the compiler twice (even worse +## than renaming). + if test -z "$gccflag"; then + gccflag=-MD, + fi + "$@" -Wp,"$gccflag$tmpdepfile" + stat=$? + if test $stat -ne 0; then + rm -f "$tmpdepfile" + exit $stat + fi + rm -f "$depfile" + echo "$object : \\" > "$depfile" + # The second -e expression handles DOS-style file names with drive + # letters. + sed -e 's/^[^:]*: / /' \ + -e 's/^['$alpha']:\/[^:]*: / /' < "$tmpdepfile" >> "$depfile" +## This next piece of magic avoids the "deleted header file" problem. +## The problem is that when a header file which appears in a .P file +## is deleted, the dependency causes make to die (because there is +## typically no way to rebuild the header). We avoid this by adding +## dummy dependencies for each header file. Too bad gcc doesn't do +## this for us directly. +## Some versions of gcc put a space before the ':'. On the theory +## that the space means something, we add a space to the output as +## well. hp depmode also adds that space, but also prefixes the VPATH +## to the object. Take care to not repeat it in the output. +## Some versions of the HPUX 10.20 sed can't process this invocation +## correctly. Breaking it into two sed invocations is a workaround. + tr ' ' "$nl" < "$tmpdepfile" \ + | sed -e 's/^\\$//' -e '/^$/d' -e "s|.*$object$||" -e '/:$/d' \ + | sed -e 's/$/ :/' >> "$depfile" + rm -f "$tmpdepfile" + ;; + +hp) + # This case exists only to let depend.m4 do its work. It works by + # looking at the text of this script. This case will never be run, + # since it is checked for above. + exit 1 + ;; + +sgi) + if test "$libtool" = yes; then + "$@" "-Wp,-MDupdate,$tmpdepfile" + else + "$@" -MDupdate "$tmpdepfile" + fi + stat=$? + if test $stat -ne 0; then + rm -f "$tmpdepfile" + exit $stat + fi + rm -f "$depfile" + + if test -f "$tmpdepfile"; then # yes, the sourcefile depend on other files + echo "$object : \\" > "$depfile" + # Clip off the initial element (the dependent). Don't try to be + # clever and replace this with sed code, as IRIX sed won't handle + # lines with more than a fixed number of characters (4096 in + # IRIX 6.2 sed, 8192 in IRIX 6.5). We also remove comment lines; + # the IRIX cc adds comments like '#:fec' to the end of the + # dependency line. + tr ' ' "$nl" < "$tmpdepfile" \ + | sed -e 's/^.*\.o://' -e 's/#.*$//' -e '/^$/ d' \ + | tr "$nl" ' ' >> "$depfile" + echo >> "$depfile" + # The second pass generates a dummy entry for each header file. + tr ' ' "$nl" < "$tmpdepfile" \ + | sed -e 's/^.*\.o://' -e 's/#.*$//' -e '/^$/ d' -e 's/$/:/' \ + >> "$depfile" + else + make_dummy_depfile + fi + rm -f "$tmpdepfile" + ;; + +xlc) + # This case exists only to let depend.m4 do its work. It works by + # looking at the text of this script. This case will never be run, + # since it is checked for above. + exit 1 + ;; + +aix) + # The C for AIX Compiler uses -M and outputs the dependencies + # in a .u file. In older versions, this file always lives in the + # current directory. Also, the AIX compiler puts '$object:' at the + # start of each line; $object doesn't have directory information. + # Version 6 uses the directory in both cases. + set_dir_from "$object" + set_base_from "$object" + if test "$libtool" = yes; then + tmpdepfile1=$dir$base.u + tmpdepfile2=$base.u + tmpdepfile3=$dir.libs/$base.u + "$@" -Wc,-M + else + tmpdepfile1=$dir$base.u + tmpdepfile2=$dir$base.u + tmpdepfile3=$dir$base.u + "$@" -M + fi + stat=$? + if test $stat -ne 0; then + rm -f "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" + exit $stat + fi + + for tmpdepfile in "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" + do + test -f "$tmpdepfile" && break + done + aix_post_process_depfile + ;; + +tcc) + # tcc (Tiny C Compiler) understand '-MD -MF file' since version 0.9.26 + # FIXME: That version still under development at the moment of writing. + # Make that this statement remains true also for stable, released + # versions. + # It will wrap lines (doesn't matter whether long or short) with a + # trailing '\', as in: + # + # foo.o : \ + # foo.c \ + # foo.h \ + # + # It will put a trailing '\' even on the last line, and will use leading + # spaces rather than leading tabs (at least since its commit 0394caf7 + # "Emit spaces for -MD"). + "$@" -MD -MF "$tmpdepfile" + stat=$? + if test $stat -ne 0; then + rm -f "$tmpdepfile" + exit $stat + fi + rm -f "$depfile" + # Each non-empty line is of the form 'foo.o : \' or ' dep.h \'. + # We have to change lines of the first kind to '$object: \'. + sed -e "s|.*:|$object :|" < "$tmpdepfile" > "$depfile" + # And for each line of the second kind, we have to emit a 'dep.h:' + # dummy dependency, to avoid the deleted-header problem. + sed -n -e 's|^ *\(.*\) *\\$|\1:|p' < "$tmpdepfile" >> "$depfile" + rm -f "$tmpdepfile" + ;; + +## The order of this option in the case statement is important, since the +## shell code in configure will try each of these formats in the order +## listed in this file. A plain '-MD' option would be understood by many +## compilers, so we must ensure this comes after the gcc and icc options. +pgcc) + # Portland's C compiler understands '-MD'. + # Will always output deps to 'file.d' where file is the root name of the + # source file under compilation, even if file resides in a subdirectory. + # The object file name does not affect the name of the '.d' file. + # pgcc 10.2 will output + # foo.o: sub/foo.c sub/foo.h + # and will wrap long lines using '\' : + # foo.o: sub/foo.c ... \ + # sub/foo.h ... \ + # ... + set_dir_from "$object" + # Use the source, not the object, to determine the base name, since + # that's sadly what pgcc will do too. + set_base_from "$source" + tmpdepfile=$base.d + + # For projects that build the same source file twice into different object + # files, the pgcc approach of using the *source* file root name can cause + # problems in parallel builds. Use a locking strategy to avoid stomping on + # the same $tmpdepfile. + lockdir=$base.d-lock + trap " + echo '$0: caught signal, cleaning up...' >&2 + rmdir '$lockdir' + exit 1 + " 1 2 13 15 + numtries=100 + i=$numtries + while test $i -gt 0; do + # mkdir is a portable test-and-set. + if mkdir "$lockdir" 2>/dev/null; then + # This process acquired the lock. + "$@" -MD + stat=$? + # Release the lock. + rmdir "$lockdir" + break + else + # If the lock is being held by a different process, wait + # until the winning process is done or we timeout. + while test -d "$lockdir" && test $i -gt 0; do + sleep 1 + i=`expr $i - 1` + done + fi + i=`expr $i - 1` + done + trap - 1 2 13 15 + if test $i -le 0; then + echo "$0: failed to acquire lock after $numtries attempts" >&2 + echo "$0: check lockdir '$lockdir'" >&2 + exit 1 + fi + + if test $stat -ne 0; then + rm -f "$tmpdepfile" + exit $stat + fi + rm -f "$depfile" + # Each line is of the form `foo.o: dependent.h', + # or `foo.o: dep1.h dep2.h \', or ` dep3.h dep4.h \'. + # Do two passes, one to just change these to + # `$object: dependent.h' and one to simply `dependent.h:'. + sed "s,^[^:]*:,$object :," < "$tmpdepfile" > "$depfile" + # Some versions of the HPUX 10.20 sed can't process this invocation + # correctly. Breaking it into two sed invocations is a workaround. + sed 's,^[^:]*: \(.*\)$,\1,;s/^\\$//;/^$/d;/:$/d' < "$tmpdepfile" \ + | sed -e 's/$/ :/' >> "$depfile" + rm -f "$tmpdepfile" + ;; + +hp2) + # The "hp" stanza above does not work with aCC (C++) and HP's ia64 + # compilers, which have integrated preprocessors. The correct option + # to use with these is +Maked; it writes dependencies to a file named + # 'foo.d', which lands next to the object file, wherever that + # happens to be. + # Much of this is similar to the tru64 case; see comments there. + set_dir_from "$object" + set_base_from "$object" + if test "$libtool" = yes; then + tmpdepfile1=$dir$base.d + tmpdepfile2=$dir.libs/$base.d + "$@" -Wc,+Maked + else + tmpdepfile1=$dir$base.d + tmpdepfile2=$dir$base.d + "$@" +Maked + fi + stat=$? + if test $stat -ne 0; then + rm -f "$tmpdepfile1" "$tmpdepfile2" + exit $stat + fi + + for tmpdepfile in "$tmpdepfile1" "$tmpdepfile2" + do + test -f "$tmpdepfile" && break + done + if test -f "$tmpdepfile"; then + sed -e "s,^.*\.[$lower]*:,$object:," "$tmpdepfile" > "$depfile" + # Add 'dependent.h:' lines. + sed -ne '2,${ + s/^ *// + s/ \\*$// + s/$/:/ + p + }' "$tmpdepfile" >> "$depfile" + else + make_dummy_depfile + fi + rm -f "$tmpdepfile" "$tmpdepfile2" + ;; + +tru64) + # The Tru64 compiler uses -MD to generate dependencies as a side + # effect. 'cc -MD -o foo.o ...' puts the dependencies into 'foo.o.d'. + # At least on Alpha/Redhat 6.1, Compaq CCC V6.2-504 seems to put + # dependencies in 'foo.d' instead, so we check for that too. + # Subdirectories are respected. + set_dir_from "$object" + set_base_from "$object" + + if test "$libtool" = yes; then + # Libtool generates 2 separate objects for the 2 libraries. These + # two compilations output dependencies in $dir.libs/$base.o.d and + # in $dir$base.o.d. We have to check for both files, because + # one of the two compilations can be disabled. We should prefer + # $dir$base.o.d over $dir.libs/$base.o.d because the latter is + # automatically cleaned when .libs/ is deleted, while ignoring + # the former would cause a distcleancheck panic. + tmpdepfile1=$dir$base.o.d # libtool 1.5 + tmpdepfile2=$dir.libs/$base.o.d # Likewise. + tmpdepfile3=$dir.libs/$base.d # Compaq CCC V6.2-504 + "$@" -Wc,-MD + else + tmpdepfile1=$dir$base.d + tmpdepfile2=$dir$base.d + tmpdepfile3=$dir$base.d + "$@" -MD + fi + + stat=$? + if test $stat -ne 0; then + rm -f "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" + exit $stat + fi + + for tmpdepfile in "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" + do + test -f "$tmpdepfile" && break + done + # Same post-processing that is required for AIX mode. + aix_post_process_depfile + ;; + +msvc7) + if test "$libtool" = yes; then + showIncludes=-Wc,-showIncludes + else + showIncludes=-showIncludes + fi + "$@" $showIncludes > "$tmpdepfile" + stat=$? + grep -v '^Note: including file: ' "$tmpdepfile" + if test $stat -ne 0; then + rm -f "$tmpdepfile" + exit $stat + fi + rm -f "$depfile" + echo "$object : \\" > "$depfile" + # The first sed program below extracts the file names and escapes + # backslashes for cygpath. The second sed program outputs the file + # name when reading, but also accumulates all include files in the + # hold buffer in order to output them again at the end. This only + # works with sed implementations that can handle large buffers. + sed < "$tmpdepfile" -n ' +/^Note: including file: *\(.*\)/ { + s//\1/ + s/\\/\\\\/g + p +}' | $cygpath_u | sort -u | sed -n ' +s/ /\\ /g +s/\(.*\)/'"$tab"'\1 \\/p +s/.\(.*\) \\/\1:/ +H +$ { + s/.*/'"$tab"'/ + G + p +}' >> "$depfile" + echo >> "$depfile" # make sure the fragment doesn't end with a backslash + rm -f "$tmpdepfile" + ;; + +msvc7msys) + # This case exists only to let depend.m4 do its work. It works by + # looking at the text of this script. This case will never be run, + # since it is checked for above. + exit 1 + ;; + +#nosideeffect) + # This comment above is used by automake to tell side-effect + # dependency tracking mechanisms from slower ones. + +dashmstdout) + # Important note: in order to support this mode, a compiler *must* + # always write the preprocessed file to stdout, regardless of -o. + "$@" || exit $? + + # Remove the call to Libtool. + if test "$libtool" = yes; then + while test "X$1" != 'X--mode=compile'; do + shift + done + shift + fi + + # Remove '-o $object'. + IFS=" " + for arg + do + case $arg in + -o) + shift + ;; + $object) + shift + ;; + *) + set fnord "$@" "$arg" + shift # fnord + shift # $arg + ;; + esac + done + + test -z "$dashmflag" && dashmflag=-M + # Require at least two characters before searching for ':' + # in the target name. This is to cope with DOS-style filenames: + # a dependency such as 'c:/foo/bar' could be seen as target 'c' otherwise. + "$@" $dashmflag | + sed "s|^[$tab ]*[^:$tab ][^:][^:]*:[$tab ]*|$object: |" > "$tmpdepfile" + rm -f "$depfile" + cat < "$tmpdepfile" > "$depfile" + # Some versions of the HPUX 10.20 sed can't process this sed invocation + # correctly. Breaking it into two sed invocations is a workaround. + tr ' ' "$nl" < "$tmpdepfile" \ + | sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' \ + | sed -e 's/$/ :/' >> "$depfile" + rm -f "$tmpdepfile" + ;; + +dashXmstdout) + # This case only exists to satisfy depend.m4. It is never actually + # run, as this mode is specially recognized in the preamble. + exit 1 + ;; + +makedepend) + "$@" || exit $? + # Remove any Libtool call + if test "$libtool" = yes; then + while test "X$1" != 'X--mode=compile'; do + shift + done + shift + fi + # X makedepend + shift + cleared=no eat=no + for arg + do + case $cleared in + no) + set ""; shift + cleared=yes ;; + esac + if test $eat = yes; then + eat=no + continue + fi + case "$arg" in + -D*|-I*) + set fnord "$@" "$arg"; shift ;; + # Strip any option that makedepend may not understand. Remove + # the object too, otherwise makedepend will parse it as a source file. + -arch) + eat=yes ;; + -*|$object) + ;; + *) + set fnord "$@" "$arg"; shift ;; + esac + done + obj_suffix=`echo "$object" | sed 's/^.*\././'` + touch "$tmpdepfile" + ${MAKEDEPEND-makedepend} -o"$obj_suffix" -f"$tmpdepfile" "$@" + rm -f "$depfile" + # makedepend may prepend the VPATH from the source file name to the object. + # No need to regex-escape $object, excess matching of '.' is harmless. + sed "s|^.*\($object *:\)|\1|" "$tmpdepfile" > "$depfile" + # Some versions of the HPUX 10.20 sed can't process the last invocation + # correctly. Breaking it into two sed invocations is a workaround. + sed '1,2d' "$tmpdepfile" \ + | tr ' ' "$nl" \ + | sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' \ + | sed -e 's/$/ :/' >> "$depfile" + rm -f "$tmpdepfile" "$tmpdepfile".bak + ;; + +cpp) + # Important note: in order to support this mode, a compiler *must* + # always write the preprocessed file to stdout. + "$@" || exit $? + + # Remove the call to Libtool. + if test "$libtool" = yes; then + while test "X$1" != 'X--mode=compile'; do + shift + done + shift + fi + + # Remove '-o $object'. + IFS=" " + for arg + do + case $arg in + -o) + shift + ;; + $object) + shift + ;; + *) + set fnord "$@" "$arg" + shift # fnord + shift # $arg + ;; + esac + done + + "$@" -E \ + | sed -n -e '/^# [0-9][0-9]* "\([^"]*\)".*/ s:: \1 \\:p' \ + -e '/^#line [0-9][0-9]* "\([^"]*\)".*/ s:: \1 \\:p' \ + | sed '$ s: \\$::' > "$tmpdepfile" + rm -f "$depfile" + echo "$object : \\" > "$depfile" + cat < "$tmpdepfile" >> "$depfile" + sed < "$tmpdepfile" '/^$/d;s/^ //;s/ \\$//;s/$/ :/' >> "$depfile" + rm -f "$tmpdepfile" + ;; + +msvisualcpp) + # Important note: in order to support this mode, a compiler *must* + # always write the preprocessed file to stdout. + "$@" || exit $? + + # Remove the call to Libtool. + if test "$libtool" = yes; then + while test "X$1" != 'X--mode=compile'; do + shift + done + shift + fi + + IFS=" " + for arg + do + case "$arg" in + -o) + shift + ;; + $object) + shift + ;; + "-Gm"|"/Gm"|"-Gi"|"/Gi"|"-ZI"|"/ZI") + set fnord "$@" + shift + shift + ;; + *) + set fnord "$@" "$arg" + shift + shift + ;; + esac + done + "$@" -E 2>/dev/null | + sed -n '/^#line [0-9][0-9]* "\([^"]*\)"/ s::\1:p' | $cygpath_u | sort -u > "$tmpdepfile" + rm -f "$depfile" + echo "$object : \\" > "$depfile" + sed < "$tmpdepfile" -n -e 's% %\\ %g' -e '/^\(.*\)$/ s::'"$tab"'\1 \\:p' >> "$depfile" + echo "$tab" >> "$depfile" + sed < "$tmpdepfile" -n -e 's% %\\ %g' -e '/^\(.*\)$/ s::\1\::p' >> "$depfile" + rm -f "$tmpdepfile" + ;; + +msvcmsys) + # This case exists only to let depend.m4 do its work. It works by + # looking at the text of this script. This case will never be run, + # since it is checked for above. + exit 1 + ;; + +none) + exec "$@" + ;; + +*) + echo "Unknown depmode $depmode" 1>&2 + exit 1 + ;; +esac + +exit 0 + +# Local Variables: +# mode: shell-script +# sh-indentation: 2 +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "scriptversion=" +# time-stamp-format: "%:y-%02m-%02d.%02H" +# time-stamp-time-zone: "UTC" +# time-stamp-end: "; # UTC" +# End: diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/install-sh b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/install-sh new file mode 100644 index 0000000..377bb86 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/install-sh @@ -0,0 +1,527 @@ +#!/bin/sh +# install - install a program, script, or datafile + +scriptversion=2011-11-20.07; # UTC + +# This originates from X11R5 (mit/util/scripts/install.sh), which was +# later released in X11R6 (xc/config/util/install.sh) with the +# following copyright and license. +# +# Copyright (C) 1994 X Consortium +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to +# deal in the Software without restriction, including without limitation the +# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +# sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +# AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNEC- +# TION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# +# Except as contained in this notice, the name of the X Consortium shall not +# be used in advertising or otherwise to promote the sale, use or other deal- +# ings in this Software without prior written authorization from the X Consor- +# tium. +# +# +# FSF changes to this file are in the public domain. +# +# Calling this script install-sh is preferred over install.sh, to prevent +# 'make' implicit rules from creating a file called install from it +# when there is no Makefile. +# +# This script is compatible with the BSD install script, but was written +# from scratch. + +nl=' +' +IFS=" "" $nl" + +# set DOITPROG to echo to test this script + +# Don't use :- since 4.3BSD and earlier shells don't like it. +doit=${DOITPROG-} +if test -z "$doit"; then + doit_exec=exec +else + doit_exec=$doit +fi + +# Put in absolute file names if you don't have them in your path; +# or use environment vars. + +chgrpprog=${CHGRPPROG-chgrp} +chmodprog=${CHMODPROG-chmod} +chownprog=${CHOWNPROG-chown} +cmpprog=${CMPPROG-cmp} +cpprog=${CPPROG-cp} +mkdirprog=${MKDIRPROG-mkdir} +mvprog=${MVPROG-mv} +rmprog=${RMPROG-rm} +stripprog=${STRIPPROG-strip} + +posix_glob='?' +initialize_posix_glob=' + test "$posix_glob" != "?" || { + if (set -f) 2>/dev/null; then + posix_glob= + else + posix_glob=: + fi + } +' + +posix_mkdir= + +# Desired mode of installed file. +mode=0755 + +chgrpcmd= +chmodcmd=$chmodprog +chowncmd= +mvcmd=$mvprog +rmcmd="$rmprog -f" +stripcmd= + +src= +dst= +dir_arg= +dst_arg= + +copy_on_change=false +no_target_directory= + +usage="\ +Usage: $0 [OPTION]... [-T] SRCFILE DSTFILE + or: $0 [OPTION]... SRCFILES... DIRECTORY + or: $0 [OPTION]... -t DIRECTORY SRCFILES... + or: $0 [OPTION]... -d DIRECTORIES... + +In the 1st form, copy SRCFILE to DSTFILE. +In the 2nd and 3rd, copy all SRCFILES to DIRECTORY. +In the 4th, create DIRECTORIES. + +Options: + --help display this help and exit. + --version display version info and exit. + + -c (ignored) + -C install only if different (preserve the last data modification time) + -d create directories instead of installing files. + -g GROUP $chgrpprog installed files to GROUP. + -m MODE $chmodprog installed files to MODE. + -o USER $chownprog installed files to USER. + -s $stripprog installed files. + -t DIRECTORY install into DIRECTORY. + -T report an error if DSTFILE is a directory. + +Environment variables override the default commands: + CHGRPPROG CHMODPROG CHOWNPROG CMPPROG CPPROG MKDIRPROG MVPROG + RMPROG STRIPPROG +" + +while test $# -ne 0; do + case $1 in + -c) ;; + + -C) copy_on_change=true;; + + -d) dir_arg=true;; + + -g) chgrpcmd="$chgrpprog $2" + shift;; + + --help) echo "$usage"; exit $?;; + + -m) mode=$2 + case $mode in + *' '* | *' '* | *' +'* | *'*'* | *'?'* | *'['*) + echo "$0: invalid mode: $mode" >&2 + exit 1;; + esac + shift;; + + -o) chowncmd="$chownprog $2" + shift;; + + -s) stripcmd=$stripprog;; + + -t) dst_arg=$2 + # Protect names problematic for 'test' and other utilities. + case $dst_arg in + -* | [=\(\)!]) dst_arg=./$dst_arg;; + esac + shift;; + + -T) no_target_directory=true;; + + --version) echo "$0 $scriptversion"; exit $?;; + + --) shift + break;; + + -*) echo "$0: invalid option: $1" >&2 + exit 1;; + + *) break;; + esac + shift +done + +if test $# -ne 0 && test -z "$dir_arg$dst_arg"; then + # When -d is used, all remaining arguments are directories to create. + # When -t is used, the destination is already specified. + # Otherwise, the last argument is the destination. Remove it from $@. + for arg + do + if test -n "$dst_arg"; then + # $@ is not empty: it contains at least $arg. + set fnord "$@" "$dst_arg" + shift # fnord + fi + shift # arg + dst_arg=$arg + # Protect names problematic for 'test' and other utilities. + case $dst_arg in + -* | [=\(\)!]) dst_arg=./$dst_arg;; + esac + done +fi + +if test $# -eq 0; then + if test -z "$dir_arg"; then + echo "$0: no input file specified." >&2 + exit 1 + fi + # It's OK to call 'install-sh -d' without argument. + # This can happen when creating conditional directories. + exit 0 +fi + +if test -z "$dir_arg"; then + do_exit='(exit $ret); exit $ret' + trap "ret=129; $do_exit" 1 + trap "ret=130; $do_exit" 2 + trap "ret=141; $do_exit" 13 + trap "ret=143; $do_exit" 15 + + # Set umask so as not to create temps with too-generous modes. + # However, 'strip' requires both read and write access to temps. + case $mode in + # Optimize common cases. + *644) cp_umask=133;; + *755) cp_umask=22;; + + *[0-7]) + if test -z "$stripcmd"; then + u_plus_rw= + else + u_plus_rw='% 200' + fi + cp_umask=`expr '(' 777 - $mode % 1000 ')' $u_plus_rw`;; + *) + if test -z "$stripcmd"; then + u_plus_rw= + else + u_plus_rw=,u+rw + fi + cp_umask=$mode$u_plus_rw;; + esac +fi + +for src +do + # Protect names problematic for 'test' and other utilities. + case $src in + -* | [=\(\)!]) src=./$src;; + esac + + if test -n "$dir_arg"; then + dst=$src + dstdir=$dst + test -d "$dstdir" + dstdir_status=$? + else + + # Waiting for this to be detected by the "$cpprog $src $dsttmp" command + # might cause directories to be created, which would be especially bad + # if $src (and thus $dsttmp) contains '*'. + if test ! -f "$src" && test ! -d "$src"; then + echo "$0: $src does not exist." >&2 + exit 1 + fi + + if test -z "$dst_arg"; then + echo "$0: no destination specified." >&2 + exit 1 + fi + dst=$dst_arg + + # If destination is a directory, append the input filename; won't work + # if double slashes aren't ignored. + if test -d "$dst"; then + if test -n "$no_target_directory"; then + echo "$0: $dst_arg: Is a directory" >&2 + exit 1 + fi + dstdir=$dst + dst=$dstdir/`basename "$src"` + dstdir_status=0 + else + # Prefer dirname, but fall back on a substitute if dirname fails. + dstdir=` + (dirname "$dst") 2>/dev/null || + expr X"$dst" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$dst" : 'X\(//\)[^/]' \| \ + X"$dst" : 'X\(//\)$' \| \ + X"$dst" : 'X\(/\)' \| . 2>/dev/null || + echo X"$dst" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q' + ` + + test -d "$dstdir" + dstdir_status=$? + fi + fi + + obsolete_mkdir_used=false + + if test $dstdir_status != 0; then + case $posix_mkdir in + '') + # Create intermediate dirs using mode 755 as modified by the umask. + # This is like FreeBSD 'install' as of 1997-10-28. + umask=`umask` + case $stripcmd.$umask in + # Optimize common cases. + *[2367][2367]) mkdir_umask=$umask;; + .*0[02][02] | .[02][02] | .[02]) mkdir_umask=22;; + + *[0-7]) + mkdir_umask=`expr $umask + 22 \ + - $umask % 100 % 40 + $umask % 20 \ + - $umask % 10 % 4 + $umask % 2 + `;; + *) mkdir_umask=$umask,go-w;; + esac + + # With -d, create the new directory with the user-specified mode. + # Otherwise, rely on $mkdir_umask. + if test -n "$dir_arg"; then + mkdir_mode=-m$mode + else + mkdir_mode= + fi + + posix_mkdir=false + case $umask in + *[123567][0-7][0-7]) + # POSIX mkdir -p sets u+wx bits regardless of umask, which + # is incompatible with FreeBSD 'install' when (umask & 300) != 0. + ;; + *) + tmpdir=${TMPDIR-/tmp}/ins$RANDOM-$$ + trap 'ret=$?; rmdir "$tmpdir/d" "$tmpdir" 2>/dev/null; exit $ret' 0 + + if (umask $mkdir_umask && + exec $mkdirprog $mkdir_mode -p -- "$tmpdir/d") >/dev/null 2>&1 + then + if test -z "$dir_arg" || { + # Check for POSIX incompatibilities with -m. + # HP-UX 11.23 and IRIX 6.5 mkdir -m -p sets group- or + # other-writable bit of parent directory when it shouldn't. + # FreeBSD 6.1 mkdir -m -p sets mode of existing directory. + ls_ld_tmpdir=`ls -ld "$tmpdir"` + case $ls_ld_tmpdir in + d????-?r-*) different_mode=700;; + d????-?--*) different_mode=755;; + *) false;; + esac && + $mkdirprog -m$different_mode -p -- "$tmpdir" && { + ls_ld_tmpdir_1=`ls -ld "$tmpdir"` + test "$ls_ld_tmpdir" = "$ls_ld_tmpdir_1" + } + } + then posix_mkdir=: + fi + rmdir "$tmpdir/d" "$tmpdir" + else + # Remove any dirs left behind by ancient mkdir implementations. + rmdir ./$mkdir_mode ./-p ./-- 2>/dev/null + fi + trap '' 0;; + esac;; + esac + + if + $posix_mkdir && ( + umask $mkdir_umask && + $doit_exec $mkdirprog $mkdir_mode -p -- "$dstdir" + ) + then : + else + + # The umask is ridiculous, or mkdir does not conform to POSIX, + # or it failed possibly due to a race condition. Create the + # directory the slow way, step by step, checking for races as we go. + + case $dstdir in + /*) prefix='/';; + [-=\(\)!]*) prefix='./';; + *) prefix='';; + esac + + eval "$initialize_posix_glob" + + oIFS=$IFS + IFS=/ + $posix_glob set -f + set fnord $dstdir + shift + $posix_glob set +f + IFS=$oIFS + + prefixes= + + for d + do + test X"$d" = X && continue + + prefix=$prefix$d + if test -d "$prefix"; then + prefixes= + else + if $posix_mkdir; then + (umask=$mkdir_umask && + $doit_exec $mkdirprog $mkdir_mode -p -- "$dstdir") && break + # Don't fail if two instances are running concurrently. + test -d "$prefix" || exit 1 + else + case $prefix in + *\'*) qprefix=`echo "$prefix" | sed "s/'/'\\\\\\\\''/g"`;; + *) qprefix=$prefix;; + esac + prefixes="$prefixes '$qprefix'" + fi + fi + prefix=$prefix/ + done + + if test -n "$prefixes"; then + # Don't fail if two instances are running concurrently. + (umask $mkdir_umask && + eval "\$doit_exec \$mkdirprog $prefixes") || + test -d "$dstdir" || exit 1 + obsolete_mkdir_used=true + fi + fi + fi + + if test -n "$dir_arg"; then + { test -z "$chowncmd" || $doit $chowncmd "$dst"; } && + { test -z "$chgrpcmd" || $doit $chgrpcmd "$dst"; } && + { test "$obsolete_mkdir_used$chowncmd$chgrpcmd" = false || + test -z "$chmodcmd" || $doit $chmodcmd $mode "$dst"; } || exit 1 + else + + # Make a couple of temp file names in the proper directory. + dsttmp=$dstdir/_inst.$$_ + rmtmp=$dstdir/_rm.$$_ + + # Trap to clean up those temp files at exit. + trap 'ret=$?; rm -f "$dsttmp" "$rmtmp" && exit $ret' 0 + + # Copy the file name to the temp name. + (umask $cp_umask && $doit_exec $cpprog "$src" "$dsttmp") && + + # and set any options; do chmod last to preserve setuid bits. + # + # If any of these fail, we abort the whole thing. If we want to + # ignore errors from any of these, just make sure not to ignore + # errors from the above "$doit $cpprog $src $dsttmp" command. + # + { test -z "$chowncmd" || $doit $chowncmd "$dsttmp"; } && + { test -z "$chgrpcmd" || $doit $chgrpcmd "$dsttmp"; } && + { test -z "$stripcmd" || $doit $stripcmd "$dsttmp"; } && + { test -z "$chmodcmd" || $doit $chmodcmd $mode "$dsttmp"; } && + + # If -C, don't bother to copy if it wouldn't change the file. + if $copy_on_change && + old=`LC_ALL=C ls -dlL "$dst" 2>/dev/null` && + new=`LC_ALL=C ls -dlL "$dsttmp" 2>/dev/null` && + + eval "$initialize_posix_glob" && + $posix_glob set -f && + set X $old && old=:$2:$4:$5:$6 && + set X $new && new=:$2:$4:$5:$6 && + $posix_glob set +f && + + test "$old" = "$new" && + $cmpprog "$dst" "$dsttmp" >/dev/null 2>&1 + then + rm -f "$dsttmp" + else + # Rename the file to the real destination. + $doit $mvcmd -f "$dsttmp" "$dst" 2>/dev/null || + + # The rename failed, perhaps because mv can't rename something else + # to itself, or perhaps because mv is so ancient that it does not + # support -f. + { + # Now remove or move aside any old file at destination location. + # We try this two ways since rm can't unlink itself on some + # systems and the destination file might be busy for other + # reasons. In this case, the final cleanup might fail but the new + # file should still install successfully. + { + test ! -f "$dst" || + $doit $rmcmd -f "$dst" 2>/dev/null || + { $doit $mvcmd -f "$dst" "$rmtmp" 2>/dev/null && + { $doit $rmcmd -f "$rmtmp" 2>/dev/null; :; } + } || + { echo "$0: cannot unlink or rename $dst" >&2 + (exit 1); exit 1 + } + } && + + # Now rename the file to the real destination. + $doit $mvcmd "$dsttmp" "$dst" + } + fi || exit 1 + + trap '' 0 + fi +done + +# Local variables: +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "scriptversion=" +# time-stamp-format: "%:y-%02m-%02d.%02H" +# time-stamp-time-zone: "UTC" +# time-stamp-end: "; # UTC" +# End: diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/ltmain.sh b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/ltmain.sh new file mode 100644 index 0000000..9ae038c --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/ltmain.sh @@ -0,0 +1,9656 @@ + +# libtool (GNU libtool) 2.4.2 +# Written by Gordon Matzigkeit , 1996 + +# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, +# 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. +# This is free software; see the source for copying conditions. There is NO +# warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + +# GNU Libtool is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# As a special exception to the GNU General Public License, +# if you distribute this file as part of a program or library that +# is built using GNU Libtool, you may include this file under the +# same distribution terms that you use for the rest of that program. +# +# GNU Libtool is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Libtool; see the file COPYING. If not, a copy +# can be downloaded from http://www.gnu.org/licenses/gpl.html, +# or obtained by writing to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + +# Usage: $progname [OPTION]... [MODE-ARG]... +# +# Provide generalized library-building support services. +# +# --config show all configuration variables +# --debug enable verbose shell tracing +# -n, --dry-run display commands without modifying any files +# --features display basic configuration information and exit +# --mode=MODE use operation mode MODE +# --preserve-dup-deps don't remove duplicate dependency libraries +# --quiet, --silent don't print informational messages +# --no-quiet, --no-silent +# print informational messages (default) +# --no-warn don't display warning messages +# --tag=TAG use configuration variables from tag TAG +# -v, --verbose print more informational messages than default +# --no-verbose don't print the extra informational messages +# --version print version information +# -h, --help, --help-all print short, long, or detailed help message +# +# MODE must be one of the following: +# +# clean remove files from the build directory +# compile compile a source file into a libtool object +# execute automatically set library path, then run a program +# finish complete the installation of libtool libraries +# install install libraries or executables +# link create a library or an executable +# uninstall remove libraries from an installed directory +# +# MODE-ARGS vary depending on the MODE. When passed as first option, +# `--mode=MODE' may be abbreviated as `MODE' or a unique abbreviation of that. +# Try `$progname --help --mode=MODE' for a more detailed description of MODE. +# +# When reporting a bug, please describe a test case to reproduce it and +# include the following information: +# +# host-triplet: $host +# shell: $SHELL +# compiler: $LTCC +# compiler flags: $LTCFLAGS +# linker: $LD (gnu? $with_gnu_ld) +# $progname: (GNU libtool) 2.4.2 +# automake: $automake_version +# autoconf: $autoconf_version +# +# Report bugs to . +# GNU libtool home page: . +# General help using GNU software: . + +PROGRAM=libtool +PACKAGE=libtool +VERSION=2.4.2 +TIMESTAMP="" +package_revision=1.3337 + +# Be Bourne compatible +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then + emulate sh + NULLCMD=: + # Zsh 3.x and 4.x performs word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in *posix*) set -o posix;; esac +fi +BIN_SH=xpg4; export BIN_SH # for Tru64 +DUALCASE=1; export DUALCASE # for MKS sh + +# A function that is used when there is no print builtin or printf. +func_fallback_echo () +{ + eval 'cat <<_LTECHO_EOF +$1 +_LTECHO_EOF' +} + +# NLS nuisances: We save the old values to restore during execute mode. +lt_user_locale= +lt_safe_locale= +for lt_var in LANG LANGUAGE LC_ALL LC_CTYPE LC_COLLATE LC_MESSAGES +do + eval "if test \"\${$lt_var+set}\" = set; then + save_$lt_var=\$$lt_var + $lt_var=C + export $lt_var + lt_user_locale=\"$lt_var=\\\$save_\$lt_var; \$lt_user_locale\" + lt_safe_locale=\"$lt_var=C; \$lt_safe_locale\" + fi" +done +LC_ALL=C +LANGUAGE=C +export LANGUAGE LC_ALL + +$lt_unset CDPATH + + +# Work around backward compatibility issue on IRIX 6.5. On IRIX 6.4+, sh +# is ksh but when the shell is invoked as "sh" and the current value of +# the _XPG environment variable is not equal to 1 (one), the special +# positional parameter $0, within a function call, is the name of the +# function. +progpath="$0" + + + +: ${CP="cp -f"} +test "${ECHO+set}" = set || ECHO=${as_echo-'printf %s\n'} +: ${MAKE="make"} +: ${MKDIR="mkdir"} +: ${MV="mv -f"} +: ${RM="rm -f"} +: ${SHELL="${CONFIG_SHELL-/bin/sh}"} +: ${Xsed="$SED -e 1s/^X//"} + +# Global variables: +EXIT_SUCCESS=0 +EXIT_FAILURE=1 +EXIT_MISMATCH=63 # $? = 63 is used to indicate version mismatch to missing. +EXIT_SKIP=77 # $? = 77 is used to indicate a skipped test to automake. + +exit_status=$EXIT_SUCCESS + +# Make sure IFS has a sensible default +lt_nl=' +' +IFS=" $lt_nl" + +dirname="s,/[^/]*$,," +basename="s,^.*/,," + +# func_dirname file append nondir_replacement +# Compute the dirname of FILE. If nonempty, add APPEND to the result, +# otherwise set result to NONDIR_REPLACEMENT. +func_dirname () +{ + func_dirname_result=`$ECHO "${1}" | $SED "$dirname"` + if test "X$func_dirname_result" = "X${1}"; then + func_dirname_result="${3}" + else + func_dirname_result="$func_dirname_result${2}" + fi +} # func_dirname may be replaced by extended shell implementation + + +# func_basename file +func_basename () +{ + func_basename_result=`$ECHO "${1}" | $SED "$basename"` +} # func_basename may be replaced by extended shell implementation + + +# func_dirname_and_basename file append nondir_replacement +# perform func_basename and func_dirname in a single function +# call: +# dirname: Compute the dirname of FILE. If nonempty, +# add APPEND to the result, otherwise set result +# to NONDIR_REPLACEMENT. +# value returned in "$func_dirname_result" +# basename: Compute filename of FILE. +# value retuned in "$func_basename_result" +# Implementation must be kept synchronized with func_dirname +# and func_basename. For efficiency, we do not delegate to +# those functions but instead duplicate the functionality here. +func_dirname_and_basename () +{ + # Extract subdirectory from the argument. + func_dirname_result=`$ECHO "${1}" | $SED -e "$dirname"` + if test "X$func_dirname_result" = "X${1}"; then + func_dirname_result="${3}" + else + func_dirname_result="$func_dirname_result${2}" + fi + func_basename_result=`$ECHO "${1}" | $SED -e "$basename"` +} # func_dirname_and_basename may be replaced by extended shell implementation + + +# func_stripname prefix suffix name +# strip PREFIX and SUFFIX off of NAME. +# PREFIX and SUFFIX must not contain globbing or regex special +# characters, hashes, percent signs, but SUFFIX may contain a leading +# dot (in which case that matches only a dot). +# func_strip_suffix prefix name +func_stripname () +{ + case ${2} in + .*) func_stripname_result=`$ECHO "${3}" | $SED "s%^${1}%%; s%\\\\${2}\$%%"`;; + *) func_stripname_result=`$ECHO "${3}" | $SED "s%^${1}%%; s%${2}\$%%"`;; + esac +} # func_stripname may be replaced by extended shell implementation + + +# These SED scripts presuppose an absolute path with a trailing slash. +pathcar='s,^/\([^/]*\).*$,\1,' +pathcdr='s,^/[^/]*,,' +removedotparts=':dotsl + s@/\./@/@g + t dotsl + s,/\.$,/,' +collapseslashes='s@/\{1,\}@/@g' +finalslash='s,/*$,/,' + +# func_normal_abspath PATH +# Remove doubled-up and trailing slashes, "." path components, +# and cancel out any ".." path components in PATH after making +# it an absolute path. +# value returned in "$func_normal_abspath_result" +func_normal_abspath () +{ + # Start from root dir and reassemble the path. + func_normal_abspath_result= + func_normal_abspath_tpath=$1 + func_normal_abspath_altnamespace= + case $func_normal_abspath_tpath in + "") + # Empty path, that just means $cwd. + func_stripname '' '/' "`pwd`" + func_normal_abspath_result=$func_stripname_result + return + ;; + # The next three entries are used to spot a run of precisely + # two leading slashes without using negated character classes; + # we take advantage of case's first-match behaviour. + ///*) + # Unusual form of absolute path, do nothing. + ;; + //*) + # Not necessarily an ordinary path; POSIX reserves leading '//' + # and for example Cygwin uses it to access remote file shares + # over CIFS/SMB, so we conserve a leading double slash if found. + func_normal_abspath_altnamespace=/ + ;; + /*) + # Absolute path, do nothing. + ;; + *) + # Relative path, prepend $cwd. + func_normal_abspath_tpath=`pwd`/$func_normal_abspath_tpath + ;; + esac + # Cancel out all the simple stuff to save iterations. We also want + # the path to end with a slash for ease of parsing, so make sure + # there is one (and only one) here. + func_normal_abspath_tpath=`$ECHO "$func_normal_abspath_tpath" | $SED \ + -e "$removedotparts" -e "$collapseslashes" -e "$finalslash"` + while :; do + # Processed it all yet? + if test "$func_normal_abspath_tpath" = / ; then + # If we ascended to the root using ".." the result may be empty now. + if test -z "$func_normal_abspath_result" ; then + func_normal_abspath_result=/ + fi + break + fi + func_normal_abspath_tcomponent=`$ECHO "$func_normal_abspath_tpath" | $SED \ + -e "$pathcar"` + func_normal_abspath_tpath=`$ECHO "$func_normal_abspath_tpath" | $SED \ + -e "$pathcdr"` + # Figure out what to do with it + case $func_normal_abspath_tcomponent in + "") + # Trailing empty path component, ignore it. + ;; + ..) + # Parent dir; strip last assembled component from result. + func_dirname "$func_normal_abspath_result" + func_normal_abspath_result=$func_dirname_result + ;; + *) + # Actual path component, append it. + func_normal_abspath_result=$func_normal_abspath_result/$func_normal_abspath_tcomponent + ;; + esac + done + # Restore leading double-slash if one was found on entry. + func_normal_abspath_result=$func_normal_abspath_altnamespace$func_normal_abspath_result +} + +# func_relative_path SRCDIR DSTDIR +# generates a relative path from SRCDIR to DSTDIR, with a trailing +# slash if non-empty, suitable for immediately appending a filename +# without needing to append a separator. +# value returned in "$func_relative_path_result" +func_relative_path () +{ + func_relative_path_result= + func_normal_abspath "$1" + func_relative_path_tlibdir=$func_normal_abspath_result + func_normal_abspath "$2" + func_relative_path_tbindir=$func_normal_abspath_result + + # Ascend the tree starting from libdir + while :; do + # check if we have found a prefix of bindir + case $func_relative_path_tbindir in + $func_relative_path_tlibdir) + # found an exact match + func_relative_path_tcancelled= + break + ;; + $func_relative_path_tlibdir*) + # found a matching prefix + func_stripname "$func_relative_path_tlibdir" '' "$func_relative_path_tbindir" + func_relative_path_tcancelled=$func_stripname_result + if test -z "$func_relative_path_result"; then + func_relative_path_result=. + fi + break + ;; + *) + func_dirname $func_relative_path_tlibdir + func_relative_path_tlibdir=${func_dirname_result} + if test "x$func_relative_path_tlibdir" = x ; then + # Have to descend all the way to the root! + func_relative_path_result=../$func_relative_path_result + func_relative_path_tcancelled=$func_relative_path_tbindir + break + fi + func_relative_path_result=../$func_relative_path_result + ;; + esac + done + + # Now calculate path; take care to avoid doubling-up slashes. + func_stripname '' '/' "$func_relative_path_result" + func_relative_path_result=$func_stripname_result + func_stripname '/' '/' "$func_relative_path_tcancelled" + if test "x$func_stripname_result" != x ; then + func_relative_path_result=${func_relative_path_result}/${func_stripname_result} + fi + + # Normalisation. If bindir is libdir, return empty string, + # else relative path ending with a slash; either way, target + # file name can be directly appended. + if test ! -z "$func_relative_path_result"; then + func_stripname './' '' "$func_relative_path_result/" + func_relative_path_result=$func_stripname_result + fi +} + +# The name of this program: +func_dirname_and_basename "$progpath" +progname=$func_basename_result + +# Make sure we have an absolute path for reexecution: +case $progpath in + [\\/]*|[A-Za-z]:\\*) ;; + *[\\/]*) + progdir=$func_dirname_result + progdir=`cd "$progdir" && pwd` + progpath="$progdir/$progname" + ;; + *) + save_IFS="$IFS" + IFS=${PATH_SEPARATOR-:} + for progdir in $PATH; do + IFS="$save_IFS" + test -x "$progdir/$progname" && break + done + IFS="$save_IFS" + test -n "$progdir" || progdir=`pwd` + progpath="$progdir/$progname" + ;; +esac + +# Sed substitution that helps us do robust quoting. It backslashifies +# metacharacters that are still active within double-quoted strings. +Xsed="${SED}"' -e 1s/^X//' +sed_quote_subst='s/\([`"$\\]\)/\\\1/g' + +# Same as above, but do not quote variable references. +double_quote_subst='s/\(["`\\]\)/\\\1/g' + +# Sed substitution that turns a string into a regex matching for the +# string literally. +sed_make_literal_regex='s,[].[^$\\*\/],\\&,g' + +# Sed substitution that converts a w32 file name or path +# which contains forward slashes, into one that contains +# (escaped) backslashes. A very naive implementation. +lt_sed_naive_backslashify='s|\\\\*|\\|g;s|/|\\|g;s|\\|\\\\|g' + +# Re-`\' parameter expansions in output of double_quote_subst that were +# `\'-ed in input to the same. If an odd number of `\' preceded a '$' +# in input to double_quote_subst, that '$' was protected from expansion. +# Since each input `\' is now two `\'s, look for any number of runs of +# four `\'s followed by two `\'s and then a '$'. `\' that '$'. +bs='\\' +bs2='\\\\' +bs4='\\\\\\\\' +dollar='\$' +sed_double_backslash="\ + s/$bs4/&\\ +/g + s/^$bs2$dollar/$bs&/ + s/\\([^$bs]\\)$bs2$dollar/\\1$bs2$bs$dollar/g + s/\n//g" + +# Standard options: +opt_dry_run=false +opt_help=false +opt_quiet=false +opt_verbose=false +opt_warning=: + +# func_echo arg... +# Echo program name prefixed message, along with the current mode +# name if it has been set yet. +func_echo () +{ + $ECHO "$progname: ${opt_mode+$opt_mode: }$*" +} + +# func_verbose arg... +# Echo program name prefixed message in verbose mode only. +func_verbose () +{ + $opt_verbose && func_echo ${1+"$@"} + + # A bug in bash halts the script if the last line of a function + # fails when set -e is in force, so we need another command to + # work around that: + : +} + +# func_echo_all arg... +# Invoke $ECHO with all args, space-separated. +func_echo_all () +{ + $ECHO "$*" +} + +# func_error arg... +# Echo program name prefixed message to standard error. +func_error () +{ + $ECHO "$progname: ${opt_mode+$opt_mode: }"${1+"$@"} 1>&2 +} + +# func_warning arg... +# Echo program name prefixed warning message to standard error. +func_warning () +{ + $opt_warning && $ECHO "$progname: ${opt_mode+$opt_mode: }warning: "${1+"$@"} 1>&2 + + # bash bug again: + : +} + +# func_fatal_error arg... +# Echo program name prefixed message to standard error, and exit. +func_fatal_error () +{ + func_error ${1+"$@"} + exit $EXIT_FAILURE +} + +# func_fatal_help arg... +# Echo program name prefixed message to standard error, followed by +# a help hint, and exit. +func_fatal_help () +{ + func_error ${1+"$@"} + func_fatal_error "$help" +} +help="Try \`$progname --help' for more information." ## default + + +# func_grep expression filename +# Check whether EXPRESSION matches any line of FILENAME, without output. +func_grep () +{ + $GREP "$1" "$2" >/dev/null 2>&1 +} + + +# func_mkdir_p directory-path +# Make sure the entire path to DIRECTORY-PATH is available. +func_mkdir_p () +{ + my_directory_path="$1" + my_dir_list= + + if test -n "$my_directory_path" && test "$opt_dry_run" != ":"; then + + # Protect directory names starting with `-' + case $my_directory_path in + -*) my_directory_path="./$my_directory_path" ;; + esac + + # While some portion of DIR does not yet exist... + while test ! -d "$my_directory_path"; do + # ...make a list in topmost first order. Use a colon delimited + # list incase some portion of path contains whitespace. + my_dir_list="$my_directory_path:$my_dir_list" + + # If the last portion added has no slash in it, the list is done + case $my_directory_path in */*) ;; *) break ;; esac + + # ...otherwise throw away the child directory and loop + my_directory_path=`$ECHO "$my_directory_path" | $SED -e "$dirname"` + done + my_dir_list=`$ECHO "$my_dir_list" | $SED 's,:*$,,'` + + save_mkdir_p_IFS="$IFS"; IFS=':' + for my_dir in $my_dir_list; do + IFS="$save_mkdir_p_IFS" + # mkdir can fail with a `File exist' error if two processes + # try to create one of the directories concurrently. Don't + # stop in that case! + $MKDIR "$my_dir" 2>/dev/null || : + done + IFS="$save_mkdir_p_IFS" + + # Bail out if we (or some other process) failed to create a directory. + test -d "$my_directory_path" || \ + func_fatal_error "Failed to create \`$1'" + fi +} + + +# func_mktempdir [string] +# Make a temporary directory that won't clash with other running +# libtool processes, and avoids race conditions if possible. If +# given, STRING is the basename for that directory. +func_mktempdir () +{ + my_template="${TMPDIR-/tmp}/${1-$progname}" + + if test "$opt_dry_run" = ":"; then + # Return a directory name, but don't create it in dry-run mode + my_tmpdir="${my_template}-$$" + else + + # If mktemp works, use that first and foremost + my_tmpdir=`mktemp -d "${my_template}-XXXXXXXX" 2>/dev/null` + + if test ! -d "$my_tmpdir"; then + # Failing that, at least try and use $RANDOM to avoid a race + my_tmpdir="${my_template}-${RANDOM-0}$$" + + save_mktempdir_umask=`umask` + umask 0077 + $MKDIR "$my_tmpdir" + umask $save_mktempdir_umask + fi + + # If we're not in dry-run mode, bomb out on failure + test -d "$my_tmpdir" || \ + func_fatal_error "cannot create temporary directory \`$my_tmpdir'" + fi + + $ECHO "$my_tmpdir" +} + + +# func_quote_for_eval arg +# Aesthetically quote ARG to be evaled later. +# This function returns two values: FUNC_QUOTE_FOR_EVAL_RESULT +# is double-quoted, suitable for a subsequent eval, whereas +# FUNC_QUOTE_FOR_EVAL_UNQUOTED_RESULT has merely all characters +# which are still active within double quotes backslashified. +func_quote_for_eval () +{ + case $1 in + *[\\\`\"\$]*) + func_quote_for_eval_unquoted_result=`$ECHO "$1" | $SED "$sed_quote_subst"` ;; + *) + func_quote_for_eval_unquoted_result="$1" ;; + esac + + case $func_quote_for_eval_unquoted_result in + # Double-quote args containing shell metacharacters to delay + # word splitting, command substitution and and variable + # expansion for a subsequent eval. + # Many Bourne shells cannot handle close brackets correctly + # in scan sets, so we specify it separately. + *[\[\~\#\^\&\*\(\)\{\}\|\;\<\>\?\'\ \ ]*|*]*|"") + func_quote_for_eval_result="\"$func_quote_for_eval_unquoted_result\"" + ;; + *) + func_quote_for_eval_result="$func_quote_for_eval_unquoted_result" + esac +} + + +# func_quote_for_expand arg +# Aesthetically quote ARG to be evaled later; same as above, +# but do not quote variable references. +func_quote_for_expand () +{ + case $1 in + *[\\\`\"]*) + my_arg=`$ECHO "$1" | $SED \ + -e "$double_quote_subst" -e "$sed_double_backslash"` ;; + *) + my_arg="$1" ;; + esac + + case $my_arg in + # Double-quote args containing shell metacharacters to delay + # word splitting and command substitution for a subsequent eval. + # Many Bourne shells cannot handle close brackets correctly + # in scan sets, so we specify it separately. + *[\[\~\#\^\&\*\(\)\{\}\|\;\<\>\?\'\ \ ]*|*]*|"") + my_arg="\"$my_arg\"" + ;; + esac + + func_quote_for_expand_result="$my_arg" +} + + +# func_show_eval cmd [fail_exp] +# Unless opt_silent is true, then output CMD. Then, if opt_dryrun is +# not true, evaluate CMD. If the evaluation of CMD fails, and FAIL_EXP +# is given, then evaluate it. +func_show_eval () +{ + my_cmd="$1" + my_fail_exp="${2-:}" + + ${opt_silent-false} || { + func_quote_for_expand "$my_cmd" + eval "func_echo $func_quote_for_expand_result" + } + + if ${opt_dry_run-false}; then :; else + eval "$my_cmd" + my_status=$? + if test "$my_status" -eq 0; then :; else + eval "(exit $my_status); $my_fail_exp" + fi + fi +} + + +# func_show_eval_locale cmd [fail_exp] +# Unless opt_silent is true, then output CMD. Then, if opt_dryrun is +# not true, evaluate CMD. If the evaluation of CMD fails, and FAIL_EXP +# is given, then evaluate it. Use the saved locale for evaluation. +func_show_eval_locale () +{ + my_cmd="$1" + my_fail_exp="${2-:}" + + ${opt_silent-false} || { + func_quote_for_expand "$my_cmd" + eval "func_echo $func_quote_for_expand_result" + } + + if ${opt_dry_run-false}; then :; else + eval "$lt_user_locale + $my_cmd" + my_status=$? + eval "$lt_safe_locale" + if test "$my_status" -eq 0; then :; else + eval "(exit $my_status); $my_fail_exp" + fi + fi +} + +# func_tr_sh +# Turn $1 into a string suitable for a shell variable name. +# Result is stored in $func_tr_sh_result. All characters +# not in the set a-zA-Z0-9_ are replaced with '_'. Further, +# if $1 begins with a digit, a '_' is prepended as well. +func_tr_sh () +{ + case $1 in + [0-9]* | *[!a-zA-Z0-9_]*) + func_tr_sh_result=`$ECHO "$1" | $SED 's/^\([0-9]\)/_\1/; s/[^a-zA-Z0-9_]/_/g'` + ;; + * ) + func_tr_sh_result=$1 + ;; + esac +} + + +# func_version +# Echo version message to standard output and exit. +func_version () +{ + $opt_debug + + $SED -n '/(C)/!b go + :more + /\./!{ + N + s/\n# / / + b more + } + :go + /^# '$PROGRAM' (GNU /,/# warranty; / { + s/^# // + s/^# *$// + s/\((C)\)[ 0-9,-]*\( [1-9][0-9]*\)/\1\2/ + p + }' < "$progpath" + exit $? +} + +# func_usage +# Echo short help message to standard output and exit. +func_usage () +{ + $opt_debug + + $SED -n '/^# Usage:/,/^# *.*--help/ { + s/^# // + s/^# *$// + s/\$progname/'$progname'/ + p + }' < "$progpath" + echo + $ECHO "run \`$progname --help | more' for full usage" + exit $? +} + +# func_help [NOEXIT] +# Echo long help message to standard output and exit, +# unless 'noexit' is passed as argument. +func_help () +{ + $opt_debug + + $SED -n '/^# Usage:/,/# Report bugs to/ { + :print + s/^# // + s/^# *$// + s*\$progname*'$progname'* + s*\$host*'"$host"'* + s*\$SHELL*'"$SHELL"'* + s*\$LTCC*'"$LTCC"'* + s*\$LTCFLAGS*'"$LTCFLAGS"'* + s*\$LD*'"$LD"'* + s/\$with_gnu_ld/'"$with_gnu_ld"'/ + s/\$automake_version/'"`(${AUTOMAKE-automake} --version) 2>/dev/null |$SED 1q`"'/ + s/\$autoconf_version/'"`(${AUTOCONF-autoconf} --version) 2>/dev/null |$SED 1q`"'/ + p + d + } + /^# .* home page:/b print + /^# General help using/b print + ' < "$progpath" + ret=$? + if test -z "$1"; then + exit $ret + fi +} + +# func_missing_arg argname +# Echo program name prefixed message to standard error and set global +# exit_cmd. +func_missing_arg () +{ + $opt_debug + + func_error "missing argument for $1." + exit_cmd=exit +} + + +# func_split_short_opt shortopt +# Set func_split_short_opt_name and func_split_short_opt_arg shell +# variables after splitting SHORTOPT after the 2nd character. +func_split_short_opt () +{ + my_sed_short_opt='1s/^\(..\).*$/\1/;q' + my_sed_short_rest='1s/^..\(.*\)$/\1/;q' + + func_split_short_opt_name=`$ECHO "$1" | $SED "$my_sed_short_opt"` + func_split_short_opt_arg=`$ECHO "$1" | $SED "$my_sed_short_rest"` +} # func_split_short_opt may be replaced by extended shell implementation + + +# func_split_long_opt longopt +# Set func_split_long_opt_name and func_split_long_opt_arg shell +# variables after splitting LONGOPT at the `=' sign. +func_split_long_opt () +{ + my_sed_long_opt='1s/^\(--[^=]*\)=.*/\1/;q' + my_sed_long_arg='1s/^--[^=]*=//' + + func_split_long_opt_name=`$ECHO "$1" | $SED "$my_sed_long_opt"` + func_split_long_opt_arg=`$ECHO "$1" | $SED "$my_sed_long_arg"` +} # func_split_long_opt may be replaced by extended shell implementation + +exit_cmd=: + + + + + +magic="%%%MAGIC variable%%%" +magic_exe="%%%MAGIC EXE variable%%%" + +# Global variables. +nonopt= +preserve_args= +lo2o="s/\\.lo\$/.${objext}/" +o2lo="s/\\.${objext}\$/.lo/" +extracted_archives= +extracted_serial=0 + +# If this variable is set in any of the actions, the command in it +# will be execed at the end. This prevents here-documents from being +# left over by shells. +exec_cmd= + +# func_append var value +# Append VALUE to the end of shell variable VAR. +func_append () +{ + eval "${1}=\$${1}\${2}" +} # func_append may be replaced by extended shell implementation + +# func_append_quoted var value +# Quote VALUE and append to the end of shell variable VAR, separated +# by a space. +func_append_quoted () +{ + func_quote_for_eval "${2}" + eval "${1}=\$${1}\\ \$func_quote_for_eval_result" +} # func_append_quoted may be replaced by extended shell implementation + + +# func_arith arithmetic-term... +func_arith () +{ + func_arith_result=`expr "${@}"` +} # func_arith may be replaced by extended shell implementation + + +# func_len string +# STRING may not start with a hyphen. +func_len () +{ + func_len_result=`expr "${1}" : ".*" 2>/dev/null || echo $max_cmd_len` +} # func_len may be replaced by extended shell implementation + + +# func_lo2o object +func_lo2o () +{ + func_lo2o_result=`$ECHO "${1}" | $SED "$lo2o"` +} # func_lo2o may be replaced by extended shell implementation + + +# func_xform libobj-or-source +func_xform () +{ + func_xform_result=`$ECHO "${1}" | $SED 's/\.[^.]*$/.lo/'` +} # func_xform may be replaced by extended shell implementation + + +# func_fatal_configuration arg... +# Echo program name prefixed message to standard error, followed by +# a configuration failure hint, and exit. +func_fatal_configuration () +{ + func_error ${1+"$@"} + func_error "See the $PACKAGE documentation for more information." + func_fatal_error "Fatal configuration error." +} + + +# func_config +# Display the configuration for all the tags in this script. +func_config () +{ + re_begincf='^# ### BEGIN LIBTOOL' + re_endcf='^# ### END LIBTOOL' + + # Default configuration. + $SED "1,/$re_begincf CONFIG/d;/$re_endcf CONFIG/,\$d" < "$progpath" + + # Now print the configurations for the tags. + for tagname in $taglist; do + $SED -n "/$re_begincf TAG CONFIG: $tagname\$/,/$re_endcf TAG CONFIG: $tagname\$/p" < "$progpath" + done + + exit $? +} + +# func_features +# Display the features supported by this script. +func_features () +{ + echo "host: $host" + if test "$build_libtool_libs" = yes; then + echo "enable shared libraries" + else + echo "disable shared libraries" + fi + if test "$build_old_libs" = yes; then + echo "enable static libraries" + else + echo "disable static libraries" + fi + + exit $? +} + +# func_enable_tag tagname +# Verify that TAGNAME is valid, and either flag an error and exit, or +# enable the TAGNAME tag. We also add TAGNAME to the global $taglist +# variable here. +func_enable_tag () +{ + # Global variable: + tagname="$1" + + re_begincf="^# ### BEGIN LIBTOOL TAG CONFIG: $tagname\$" + re_endcf="^# ### END LIBTOOL TAG CONFIG: $tagname\$" + sed_extractcf="/$re_begincf/,/$re_endcf/p" + + # Validate tagname. + case $tagname in + *[!-_A-Za-z0-9,/]*) + func_fatal_error "invalid tag name: $tagname" + ;; + esac + + # Don't test for the "default" C tag, as we know it's + # there but not specially marked. + case $tagname in + CC) ;; + *) + if $GREP "$re_begincf" "$progpath" >/dev/null 2>&1; then + taglist="$taglist $tagname" + + # Evaluate the configuration. Be careful to quote the path + # and the sed script, to avoid splitting on whitespace, but + # also don't use non-portable quotes within backquotes within + # quotes we have to do it in 2 steps: + extractedcf=`$SED -n -e "$sed_extractcf" < "$progpath"` + eval "$extractedcf" + else + func_error "ignoring unknown tag $tagname" + fi + ;; + esac +} + +# func_check_version_match +# Ensure that we are using m4 macros, and libtool script from the same +# release of libtool. +func_check_version_match () +{ + if test "$package_revision" != "$macro_revision"; then + if test "$VERSION" != "$macro_version"; then + if test -z "$macro_version"; then + cat >&2 <<_LT_EOF +$progname: Version mismatch error. This is $PACKAGE $VERSION, but the +$progname: definition of this LT_INIT comes from an older release. +$progname: You should recreate aclocal.m4 with macros from $PACKAGE $VERSION +$progname: and run autoconf again. +_LT_EOF + else + cat >&2 <<_LT_EOF +$progname: Version mismatch error. This is $PACKAGE $VERSION, but the +$progname: definition of this LT_INIT comes from $PACKAGE $macro_version. +$progname: You should recreate aclocal.m4 with macros from $PACKAGE $VERSION +$progname: and run autoconf again. +_LT_EOF + fi + else + cat >&2 <<_LT_EOF +$progname: Version mismatch error. This is $PACKAGE $VERSION, revision $package_revision, +$progname: but the definition of this LT_INIT comes from revision $macro_revision. +$progname: You should recreate aclocal.m4 with macros from revision $package_revision +$progname: of $PACKAGE $VERSION and run autoconf again. +_LT_EOF + fi + + exit $EXIT_MISMATCH + fi +} + + +# Shorthand for --mode=foo, only valid as the first argument +case $1 in +clean|clea|cle|cl) + shift; set dummy --mode clean ${1+"$@"}; shift + ;; +compile|compil|compi|comp|com|co|c) + shift; set dummy --mode compile ${1+"$@"}; shift + ;; +execute|execut|execu|exec|exe|ex|e) + shift; set dummy --mode execute ${1+"$@"}; shift + ;; +finish|finis|fini|fin|fi|f) + shift; set dummy --mode finish ${1+"$@"}; shift + ;; +install|instal|insta|inst|ins|in|i) + shift; set dummy --mode install ${1+"$@"}; shift + ;; +link|lin|li|l) + shift; set dummy --mode link ${1+"$@"}; shift + ;; +uninstall|uninstal|uninsta|uninst|unins|unin|uni|un|u) + shift; set dummy --mode uninstall ${1+"$@"}; shift + ;; +esac + + + +# Option defaults: +opt_debug=: +opt_dry_run=false +opt_config=false +opt_preserve_dup_deps=false +opt_features=false +opt_finish=false +opt_help=false +opt_help_all=false +opt_silent=: +opt_warning=: +opt_verbose=: +opt_silent=false +opt_verbose=false + + +# Parse options once, thoroughly. This comes as soon as possible in the +# script to make things like `--version' happen as quickly as we can. +{ + # this just eases exit handling + while test $# -gt 0; do + opt="$1" + shift + case $opt in + --debug|-x) opt_debug='set -x' + func_echo "enabling shell trace mode" + $opt_debug + ;; + --dry-run|--dryrun|-n) + opt_dry_run=: + ;; + --config) + opt_config=: +func_config + ;; + --dlopen|-dlopen) + optarg="$1" + opt_dlopen="${opt_dlopen+$opt_dlopen +}$optarg" + shift + ;; + --preserve-dup-deps) + opt_preserve_dup_deps=: + ;; + --features) + opt_features=: +func_features + ;; + --finish) + opt_finish=: +set dummy --mode finish ${1+"$@"}; shift + ;; + --help) + opt_help=: + ;; + --help-all) + opt_help_all=: +opt_help=': help-all' + ;; + --mode) + test $# = 0 && func_missing_arg $opt && break + optarg="$1" + opt_mode="$optarg" +case $optarg in + # Valid mode arguments: + clean|compile|execute|finish|install|link|relink|uninstall) ;; + + # Catch anything else as an error + *) func_error "invalid argument for $opt" + exit_cmd=exit + break + ;; +esac + shift + ;; + --no-silent|--no-quiet) + opt_silent=false +func_append preserve_args " $opt" + ;; + --no-warning|--no-warn) + opt_warning=false +func_append preserve_args " $opt" + ;; + --no-verbose) + opt_verbose=false +func_append preserve_args " $opt" + ;; + --silent|--quiet) + opt_silent=: +func_append preserve_args " $opt" + opt_verbose=false + ;; + --verbose|-v) + opt_verbose=: +func_append preserve_args " $opt" +opt_silent=false + ;; + --tag) + test $# = 0 && func_missing_arg $opt && break + optarg="$1" + opt_tag="$optarg" +func_append preserve_args " $opt $optarg" +func_enable_tag "$optarg" + shift + ;; + + -\?|-h) func_usage ;; + --help) func_help ;; + --version) func_version ;; + + # Separate optargs to long options: + --*=*) + func_split_long_opt "$opt" + set dummy "$func_split_long_opt_name" "$func_split_long_opt_arg" ${1+"$@"} + shift + ;; + + # Separate non-argument short options: + -\?*|-h*|-n*|-v*) + func_split_short_opt "$opt" + set dummy "$func_split_short_opt_name" "-$func_split_short_opt_arg" ${1+"$@"} + shift + ;; + + --) break ;; + -*) func_fatal_help "unrecognized option \`$opt'" ;; + *) set dummy "$opt" ${1+"$@"}; shift; break ;; + esac + done + + # Validate options: + + # save first non-option argument + if test "$#" -gt 0; then + nonopt="$opt" + shift + fi + + # preserve --debug + test "$opt_debug" = : || func_append preserve_args " --debug" + + case $host in + *cygwin* | *mingw* | *pw32* | *cegcc*) + # don't eliminate duplications in $postdeps and $predeps + opt_duplicate_compiler_generated_deps=: + ;; + *) + opt_duplicate_compiler_generated_deps=$opt_preserve_dup_deps + ;; + esac + + $opt_help || { + # Sanity checks first: + func_check_version_match + + if test "$build_libtool_libs" != yes && test "$build_old_libs" != yes; then + func_fatal_configuration "not configured to build any kind of library" + fi + + # Darwin sucks + eval std_shrext=\"$shrext_cmds\" + + # Only execute mode is allowed to have -dlopen flags. + if test -n "$opt_dlopen" && test "$opt_mode" != execute; then + func_error "unrecognized option \`-dlopen'" + $ECHO "$help" 1>&2 + exit $EXIT_FAILURE + fi + + # Change the help message to a mode-specific one. + generic_help="$help" + help="Try \`$progname --help --mode=$opt_mode' for more information." + } + + + # Bail if the options were screwed + $exit_cmd $EXIT_FAILURE +} + + + + +## ----------- ## +## Main. ## +## ----------- ## + +# func_lalib_p file +# True iff FILE is a libtool `.la' library or `.lo' object file. +# This function is only a basic sanity check; it will hardly flush out +# determined imposters. +func_lalib_p () +{ + test -f "$1" && + $SED -e 4q "$1" 2>/dev/null \ + | $GREP "^# Generated by .*$PACKAGE" > /dev/null 2>&1 +} + +# func_lalib_unsafe_p file +# True iff FILE is a libtool `.la' library or `.lo' object file. +# This function implements the same check as func_lalib_p without +# resorting to external programs. To this end, it redirects stdin and +# closes it afterwards, without saving the original file descriptor. +# As a safety measure, use it only where a negative result would be +# fatal anyway. Works if `file' does not exist. +func_lalib_unsafe_p () +{ + lalib_p=no + if test -f "$1" && test -r "$1" && exec 5<&0 <"$1"; then + for lalib_p_l in 1 2 3 4 + do + read lalib_p_line + case "$lalib_p_line" in + \#\ Generated\ by\ *$PACKAGE* ) lalib_p=yes; break;; + esac + done + exec 0<&5 5<&- + fi + test "$lalib_p" = yes +} + +# func_ltwrapper_script_p file +# True iff FILE is a libtool wrapper script +# This function is only a basic sanity check; it will hardly flush out +# determined imposters. +func_ltwrapper_script_p () +{ + func_lalib_p "$1" +} + +# func_ltwrapper_executable_p file +# True iff FILE is a libtool wrapper executable +# This function is only a basic sanity check; it will hardly flush out +# determined imposters. +func_ltwrapper_executable_p () +{ + func_ltwrapper_exec_suffix= + case $1 in + *.exe) ;; + *) func_ltwrapper_exec_suffix=.exe ;; + esac + $GREP "$magic_exe" "$1$func_ltwrapper_exec_suffix" >/dev/null 2>&1 +} + +# func_ltwrapper_scriptname file +# Assumes file is an ltwrapper_executable +# uses $file to determine the appropriate filename for a +# temporary ltwrapper_script. +func_ltwrapper_scriptname () +{ + func_dirname_and_basename "$1" "" "." + func_stripname '' '.exe' "$func_basename_result" + func_ltwrapper_scriptname_result="$func_dirname_result/$objdir/${func_stripname_result}_ltshwrapper" +} + +# func_ltwrapper_p file +# True iff FILE is a libtool wrapper script or wrapper executable +# This function is only a basic sanity check; it will hardly flush out +# determined imposters. +func_ltwrapper_p () +{ + func_ltwrapper_script_p "$1" || func_ltwrapper_executable_p "$1" +} + + +# func_execute_cmds commands fail_cmd +# Execute tilde-delimited COMMANDS. +# If FAIL_CMD is given, eval that upon failure. +# FAIL_CMD may read-access the current command in variable CMD! +func_execute_cmds () +{ + $opt_debug + save_ifs=$IFS; IFS='~' + for cmd in $1; do + IFS=$save_ifs + eval cmd=\"$cmd\" + func_show_eval "$cmd" "${2-:}" + done + IFS=$save_ifs +} + + +# func_source file +# Source FILE, adding directory component if necessary. +# Note that it is not necessary on cygwin/mingw to append a dot to +# FILE even if both FILE and FILE.exe exist: automatic-append-.exe +# behavior happens only for exec(3), not for open(2)! Also, sourcing +# `FILE.' does not work on cygwin managed mounts. +func_source () +{ + $opt_debug + case $1 in + */* | *\\*) . "$1" ;; + *) . "./$1" ;; + esac +} + + +# func_resolve_sysroot PATH +# Replace a leading = in PATH with a sysroot. Store the result into +# func_resolve_sysroot_result +func_resolve_sysroot () +{ + func_resolve_sysroot_result=$1 + case $func_resolve_sysroot_result in + =*) + func_stripname '=' '' "$func_resolve_sysroot_result" + func_resolve_sysroot_result=$lt_sysroot$func_stripname_result + ;; + esac +} + +# func_replace_sysroot PATH +# If PATH begins with the sysroot, replace it with = and +# store the result into func_replace_sysroot_result. +func_replace_sysroot () +{ + case "$lt_sysroot:$1" in + ?*:"$lt_sysroot"*) + func_stripname "$lt_sysroot" '' "$1" + func_replace_sysroot_result="=$func_stripname_result" + ;; + *) + # Including no sysroot. + func_replace_sysroot_result=$1 + ;; + esac +} + +# func_infer_tag arg +# Infer tagged configuration to use if any are available and +# if one wasn't chosen via the "--tag" command line option. +# Only attempt this if the compiler in the base compile +# command doesn't match the default compiler. +# arg is usually of the form 'gcc ...' +func_infer_tag () +{ + $opt_debug + if test -n "$available_tags" && test -z "$tagname"; then + CC_quoted= + for arg in $CC; do + func_append_quoted CC_quoted "$arg" + done + CC_expanded=`func_echo_all $CC` + CC_quoted_expanded=`func_echo_all $CC_quoted` + case $@ in + # Blanks in the command may have been stripped by the calling shell, + # but not from the CC environment variable when configure was run. + " $CC "* | "$CC "* | " $CC_expanded "* | "$CC_expanded "* | \ + " $CC_quoted"* | "$CC_quoted "* | " $CC_quoted_expanded "* | "$CC_quoted_expanded "*) ;; + # Blanks at the start of $base_compile will cause this to fail + # if we don't check for them as well. + *) + for z in $available_tags; do + if $GREP "^# ### BEGIN LIBTOOL TAG CONFIG: $z$" < "$progpath" > /dev/null; then + # Evaluate the configuration. + eval "`${SED} -n -e '/^# ### BEGIN LIBTOOL TAG CONFIG: '$z'$/,/^# ### END LIBTOOL TAG CONFIG: '$z'$/p' < $progpath`" + CC_quoted= + for arg in $CC; do + # Double-quote args containing other shell metacharacters. + func_append_quoted CC_quoted "$arg" + done + CC_expanded=`func_echo_all $CC` + CC_quoted_expanded=`func_echo_all $CC_quoted` + case "$@ " in + " $CC "* | "$CC "* | " $CC_expanded "* | "$CC_expanded "* | \ + " $CC_quoted"* | "$CC_quoted "* | " $CC_quoted_expanded "* | "$CC_quoted_expanded "*) + # The compiler in the base compile command matches + # the one in the tagged configuration. + # Assume this is the tagged configuration we want. + tagname=$z + break + ;; + esac + fi + done + # If $tagname still isn't set, then no tagged configuration + # was found and let the user know that the "--tag" command + # line option must be used. + if test -z "$tagname"; then + func_echo "unable to infer tagged configuration" + func_fatal_error "specify a tag with \`--tag'" +# else +# func_verbose "using $tagname tagged configuration" + fi + ;; + esac + fi +} + + + +# func_write_libtool_object output_name pic_name nonpic_name +# Create a libtool object file (analogous to a ".la" file), +# but don't create it if we're doing a dry run. +func_write_libtool_object () +{ + write_libobj=${1} + if test "$build_libtool_libs" = yes; then + write_lobj=\'${2}\' + else + write_lobj=none + fi + + if test "$build_old_libs" = yes; then + write_oldobj=\'${3}\' + else + write_oldobj=none + fi + + $opt_dry_run || { + cat >${write_libobj}T </dev/null` + if test "$?" -eq 0 && test -n "${func_convert_core_file_wine_to_w32_tmp}"; then + func_convert_core_file_wine_to_w32_result=`$ECHO "$func_convert_core_file_wine_to_w32_tmp" | + $SED -e "$lt_sed_naive_backslashify"` + else + func_convert_core_file_wine_to_w32_result= + fi + fi +} +# end: func_convert_core_file_wine_to_w32 + + +# func_convert_core_path_wine_to_w32 ARG +# Helper function used by path conversion functions when $build is *nix, and +# $host is mingw, cygwin, or some other w32 environment. Relies on a correctly +# configured wine environment available, with the winepath program in $build's +# $PATH. Assumes ARG has no leading or trailing path separator characters. +# +# ARG is path to be converted from $build format to win32. +# Result is available in $func_convert_core_path_wine_to_w32_result. +# Unconvertible file (directory) names in ARG are skipped; if no directory names +# are convertible, then the result may be empty. +func_convert_core_path_wine_to_w32 () +{ + $opt_debug + # unfortunately, winepath doesn't convert paths, only file names + func_convert_core_path_wine_to_w32_result="" + if test -n "$1"; then + oldIFS=$IFS + IFS=: + for func_convert_core_path_wine_to_w32_f in $1; do + IFS=$oldIFS + func_convert_core_file_wine_to_w32 "$func_convert_core_path_wine_to_w32_f" + if test -n "$func_convert_core_file_wine_to_w32_result" ; then + if test -z "$func_convert_core_path_wine_to_w32_result"; then + func_convert_core_path_wine_to_w32_result="$func_convert_core_file_wine_to_w32_result" + else + func_append func_convert_core_path_wine_to_w32_result ";$func_convert_core_file_wine_to_w32_result" + fi + fi + done + IFS=$oldIFS + fi +} +# end: func_convert_core_path_wine_to_w32 + + +# func_cygpath ARGS... +# Wrapper around calling the cygpath program via LT_CYGPATH. This is used when +# when (1) $build is *nix and Cygwin is hosted via a wine environment; or (2) +# $build is MSYS and $host is Cygwin, or (3) $build is Cygwin. In case (1) or +# (2), returns the Cygwin file name or path in func_cygpath_result (input +# file name or path is assumed to be in w32 format, as previously converted +# from $build's *nix or MSYS format). In case (3), returns the w32 file name +# or path in func_cygpath_result (input file name or path is assumed to be in +# Cygwin format). Returns an empty string on error. +# +# ARGS are passed to cygpath, with the last one being the file name or path to +# be converted. +# +# Specify the absolute *nix (or w32) name to cygpath in the LT_CYGPATH +# environment variable; do not put it in $PATH. +func_cygpath () +{ + $opt_debug + if test -n "$LT_CYGPATH" && test -f "$LT_CYGPATH"; then + func_cygpath_result=`$LT_CYGPATH "$@" 2>/dev/null` + if test "$?" -ne 0; then + # on failure, ensure result is empty + func_cygpath_result= + fi + else + func_cygpath_result= + func_error "LT_CYGPATH is empty or specifies non-existent file: \`$LT_CYGPATH'" + fi +} +#end: func_cygpath + + +# func_convert_core_msys_to_w32 ARG +# Convert file name or path ARG from MSYS format to w32 format. Return +# result in func_convert_core_msys_to_w32_result. +func_convert_core_msys_to_w32 () +{ + $opt_debug + # awkward: cmd appends spaces to result + func_convert_core_msys_to_w32_result=`( cmd //c echo "$1" ) 2>/dev/null | + $SED -e 's/[ ]*$//' -e "$lt_sed_naive_backslashify"` +} +#end: func_convert_core_msys_to_w32 + + +# func_convert_file_check ARG1 ARG2 +# Verify that ARG1 (a file name in $build format) was converted to $host +# format in ARG2. Otherwise, emit an error message, but continue (resetting +# func_to_host_file_result to ARG1). +func_convert_file_check () +{ + $opt_debug + if test -z "$2" && test -n "$1" ; then + func_error "Could not determine host file name corresponding to" + func_error " \`$1'" + func_error "Continuing, but uninstalled executables may not work." + # Fallback: + func_to_host_file_result="$1" + fi +} +# end func_convert_file_check + + +# func_convert_path_check FROM_PATHSEP TO_PATHSEP FROM_PATH TO_PATH +# Verify that FROM_PATH (a path in $build format) was converted to $host +# format in TO_PATH. Otherwise, emit an error message, but continue, resetting +# func_to_host_file_result to a simplistic fallback value (see below). +func_convert_path_check () +{ + $opt_debug + if test -z "$4" && test -n "$3"; then + func_error "Could not determine the host path corresponding to" + func_error " \`$3'" + func_error "Continuing, but uninstalled executables may not work." + # Fallback. This is a deliberately simplistic "conversion" and + # should not be "improved". See libtool.info. + if test "x$1" != "x$2"; then + lt_replace_pathsep_chars="s|$1|$2|g" + func_to_host_path_result=`echo "$3" | + $SED -e "$lt_replace_pathsep_chars"` + else + func_to_host_path_result="$3" + fi + fi +} +# end func_convert_path_check + + +# func_convert_path_front_back_pathsep FRONTPAT BACKPAT REPL ORIG +# Modifies func_to_host_path_result by prepending REPL if ORIG matches FRONTPAT +# and appending REPL if ORIG matches BACKPAT. +func_convert_path_front_back_pathsep () +{ + $opt_debug + case $4 in + $1 ) func_to_host_path_result="$3$func_to_host_path_result" + ;; + esac + case $4 in + $2 ) func_append func_to_host_path_result "$3" + ;; + esac +} +# end func_convert_path_front_back_pathsep + + +################################################## +# $build to $host FILE NAME CONVERSION FUNCTIONS # +################################################## +# invoked via `$to_host_file_cmd ARG' +# +# In each case, ARG is the path to be converted from $build to $host format. +# Result will be available in $func_to_host_file_result. + + +# func_to_host_file ARG +# Converts the file name ARG from $build format to $host format. Return result +# in func_to_host_file_result. +func_to_host_file () +{ + $opt_debug + $to_host_file_cmd "$1" +} +# end func_to_host_file + + +# func_to_tool_file ARG LAZY +# converts the file name ARG from $build format to toolchain format. Return +# result in func_to_tool_file_result. If the conversion in use is listed +# in (the comma separated) LAZY, no conversion takes place. +func_to_tool_file () +{ + $opt_debug + case ,$2, in + *,"$to_tool_file_cmd",*) + func_to_tool_file_result=$1 + ;; + *) + $to_tool_file_cmd "$1" + func_to_tool_file_result=$func_to_host_file_result + ;; + esac +} +# end func_to_tool_file + + +# func_convert_file_noop ARG +# Copy ARG to func_to_host_file_result. +func_convert_file_noop () +{ + func_to_host_file_result="$1" +} +# end func_convert_file_noop + + +# func_convert_file_msys_to_w32 ARG +# Convert file name ARG from (mingw) MSYS to (mingw) w32 format; automatic +# conversion to w32 is not available inside the cwrapper. Returns result in +# func_to_host_file_result. +func_convert_file_msys_to_w32 () +{ + $opt_debug + func_to_host_file_result="$1" + if test -n "$1"; then + func_convert_core_msys_to_w32 "$1" + func_to_host_file_result="$func_convert_core_msys_to_w32_result" + fi + func_convert_file_check "$1" "$func_to_host_file_result" +} +# end func_convert_file_msys_to_w32 + + +# func_convert_file_cygwin_to_w32 ARG +# Convert file name ARG from Cygwin to w32 format. Returns result in +# func_to_host_file_result. +func_convert_file_cygwin_to_w32 () +{ + $opt_debug + func_to_host_file_result="$1" + if test -n "$1"; then + # because $build is cygwin, we call "the" cygpath in $PATH; no need to use + # LT_CYGPATH in this case. + func_to_host_file_result=`cygpath -m "$1"` + fi + func_convert_file_check "$1" "$func_to_host_file_result" +} +# end func_convert_file_cygwin_to_w32 + + +# func_convert_file_nix_to_w32 ARG +# Convert file name ARG from *nix to w32 format. Requires a wine environment +# and a working winepath. Returns result in func_to_host_file_result. +func_convert_file_nix_to_w32 () +{ + $opt_debug + func_to_host_file_result="$1" + if test -n "$1"; then + func_convert_core_file_wine_to_w32 "$1" + func_to_host_file_result="$func_convert_core_file_wine_to_w32_result" + fi + func_convert_file_check "$1" "$func_to_host_file_result" +} +# end func_convert_file_nix_to_w32 + + +# func_convert_file_msys_to_cygwin ARG +# Convert file name ARG from MSYS to Cygwin format. Requires LT_CYGPATH set. +# Returns result in func_to_host_file_result. +func_convert_file_msys_to_cygwin () +{ + $opt_debug + func_to_host_file_result="$1" + if test -n "$1"; then + func_convert_core_msys_to_w32 "$1" + func_cygpath -u "$func_convert_core_msys_to_w32_result" + func_to_host_file_result="$func_cygpath_result" + fi + func_convert_file_check "$1" "$func_to_host_file_result" +} +# end func_convert_file_msys_to_cygwin + + +# func_convert_file_nix_to_cygwin ARG +# Convert file name ARG from *nix to Cygwin format. Requires Cygwin installed +# in a wine environment, working winepath, and LT_CYGPATH set. Returns result +# in func_to_host_file_result. +func_convert_file_nix_to_cygwin () +{ + $opt_debug + func_to_host_file_result="$1" + if test -n "$1"; then + # convert from *nix to w32, then use cygpath to convert from w32 to cygwin. + func_convert_core_file_wine_to_w32 "$1" + func_cygpath -u "$func_convert_core_file_wine_to_w32_result" + func_to_host_file_result="$func_cygpath_result" + fi + func_convert_file_check "$1" "$func_to_host_file_result" +} +# end func_convert_file_nix_to_cygwin + + +############################################# +# $build to $host PATH CONVERSION FUNCTIONS # +############################################# +# invoked via `$to_host_path_cmd ARG' +# +# In each case, ARG is the path to be converted from $build to $host format. +# The result will be available in $func_to_host_path_result. +# +# Path separators are also converted from $build format to $host format. If +# ARG begins or ends with a path separator character, it is preserved (but +# converted to $host format) on output. +# +# All path conversion functions are named using the following convention: +# file name conversion function : func_convert_file_X_to_Y () +# path conversion function : func_convert_path_X_to_Y () +# where, for any given $build/$host combination the 'X_to_Y' value is the +# same. If conversion functions are added for new $build/$host combinations, +# the two new functions must follow this pattern, or func_init_to_host_path_cmd +# will break. + + +# func_init_to_host_path_cmd +# Ensures that function "pointer" variable $to_host_path_cmd is set to the +# appropriate value, based on the value of $to_host_file_cmd. +to_host_path_cmd= +func_init_to_host_path_cmd () +{ + $opt_debug + if test -z "$to_host_path_cmd"; then + func_stripname 'func_convert_file_' '' "$to_host_file_cmd" + to_host_path_cmd="func_convert_path_${func_stripname_result}" + fi +} + + +# func_to_host_path ARG +# Converts the path ARG from $build format to $host format. Return result +# in func_to_host_path_result. +func_to_host_path () +{ + $opt_debug + func_init_to_host_path_cmd + $to_host_path_cmd "$1" +} +# end func_to_host_path + + +# func_convert_path_noop ARG +# Copy ARG to func_to_host_path_result. +func_convert_path_noop () +{ + func_to_host_path_result="$1" +} +# end func_convert_path_noop + + +# func_convert_path_msys_to_w32 ARG +# Convert path ARG from (mingw) MSYS to (mingw) w32 format; automatic +# conversion to w32 is not available inside the cwrapper. Returns result in +# func_to_host_path_result. +func_convert_path_msys_to_w32 () +{ + $opt_debug + func_to_host_path_result="$1" + if test -n "$1"; then + # Remove leading and trailing path separator characters from ARG. MSYS + # behavior is inconsistent here; cygpath turns them into '.;' and ';.'; + # and winepath ignores them completely. + func_stripname : : "$1" + func_to_host_path_tmp1=$func_stripname_result + func_convert_core_msys_to_w32 "$func_to_host_path_tmp1" + func_to_host_path_result="$func_convert_core_msys_to_w32_result" + func_convert_path_check : ";" \ + "$func_to_host_path_tmp1" "$func_to_host_path_result" + func_convert_path_front_back_pathsep ":*" "*:" ";" "$1" + fi +} +# end func_convert_path_msys_to_w32 + + +# func_convert_path_cygwin_to_w32 ARG +# Convert path ARG from Cygwin to w32 format. Returns result in +# func_to_host_file_result. +func_convert_path_cygwin_to_w32 () +{ + $opt_debug + func_to_host_path_result="$1" + if test -n "$1"; then + # See func_convert_path_msys_to_w32: + func_stripname : : "$1" + func_to_host_path_tmp1=$func_stripname_result + func_to_host_path_result=`cygpath -m -p "$func_to_host_path_tmp1"` + func_convert_path_check : ";" \ + "$func_to_host_path_tmp1" "$func_to_host_path_result" + func_convert_path_front_back_pathsep ":*" "*:" ";" "$1" + fi +} +# end func_convert_path_cygwin_to_w32 + + +# func_convert_path_nix_to_w32 ARG +# Convert path ARG from *nix to w32 format. Requires a wine environment and +# a working winepath. Returns result in func_to_host_file_result. +func_convert_path_nix_to_w32 () +{ + $opt_debug + func_to_host_path_result="$1" + if test -n "$1"; then + # See func_convert_path_msys_to_w32: + func_stripname : : "$1" + func_to_host_path_tmp1=$func_stripname_result + func_convert_core_path_wine_to_w32 "$func_to_host_path_tmp1" + func_to_host_path_result="$func_convert_core_path_wine_to_w32_result" + func_convert_path_check : ";" \ + "$func_to_host_path_tmp1" "$func_to_host_path_result" + func_convert_path_front_back_pathsep ":*" "*:" ";" "$1" + fi +} +# end func_convert_path_nix_to_w32 + + +# func_convert_path_msys_to_cygwin ARG +# Convert path ARG from MSYS to Cygwin format. Requires LT_CYGPATH set. +# Returns result in func_to_host_file_result. +func_convert_path_msys_to_cygwin () +{ + $opt_debug + func_to_host_path_result="$1" + if test -n "$1"; then + # See func_convert_path_msys_to_w32: + func_stripname : : "$1" + func_to_host_path_tmp1=$func_stripname_result + func_convert_core_msys_to_w32 "$func_to_host_path_tmp1" + func_cygpath -u -p "$func_convert_core_msys_to_w32_result" + func_to_host_path_result="$func_cygpath_result" + func_convert_path_check : : \ + "$func_to_host_path_tmp1" "$func_to_host_path_result" + func_convert_path_front_back_pathsep ":*" "*:" : "$1" + fi +} +# end func_convert_path_msys_to_cygwin + + +# func_convert_path_nix_to_cygwin ARG +# Convert path ARG from *nix to Cygwin format. Requires Cygwin installed in a +# a wine environment, working winepath, and LT_CYGPATH set. Returns result in +# func_to_host_file_result. +func_convert_path_nix_to_cygwin () +{ + $opt_debug + func_to_host_path_result="$1" + if test -n "$1"; then + # Remove leading and trailing path separator characters from + # ARG. msys behavior is inconsistent here, cygpath turns them + # into '.;' and ';.', and winepath ignores them completely. + func_stripname : : "$1" + func_to_host_path_tmp1=$func_stripname_result + func_convert_core_path_wine_to_w32 "$func_to_host_path_tmp1" + func_cygpath -u -p "$func_convert_core_path_wine_to_w32_result" + func_to_host_path_result="$func_cygpath_result" + func_convert_path_check : : \ + "$func_to_host_path_tmp1" "$func_to_host_path_result" + func_convert_path_front_back_pathsep ":*" "*:" : "$1" + fi +} +# end func_convert_path_nix_to_cygwin + + +# func_mode_compile arg... +func_mode_compile () +{ + $opt_debug + # Get the compilation command and the source file. + base_compile= + srcfile="$nonopt" # always keep a non-empty value in "srcfile" + suppress_opt=yes + suppress_output= + arg_mode=normal + libobj= + later= + pie_flag= + + for arg + do + case $arg_mode in + arg ) + # do not "continue". Instead, add this to base_compile + lastarg="$arg" + arg_mode=normal + ;; + + target ) + libobj="$arg" + arg_mode=normal + continue + ;; + + normal ) + # Accept any command-line options. + case $arg in + -o) + test -n "$libobj" && \ + func_fatal_error "you cannot specify \`-o' more than once" + arg_mode=target + continue + ;; + + -pie | -fpie | -fPIE) + func_append pie_flag " $arg" + continue + ;; + + -shared | -static | -prefer-pic | -prefer-non-pic) + func_append later " $arg" + continue + ;; + + -no-suppress) + suppress_opt=no + continue + ;; + + -Xcompiler) + arg_mode=arg # the next one goes into the "base_compile" arg list + continue # The current "srcfile" will either be retained or + ;; # replaced later. I would guess that would be a bug. + + -Wc,*) + func_stripname '-Wc,' '' "$arg" + args=$func_stripname_result + lastarg= + save_ifs="$IFS"; IFS=',' + for arg in $args; do + IFS="$save_ifs" + func_append_quoted lastarg "$arg" + done + IFS="$save_ifs" + func_stripname ' ' '' "$lastarg" + lastarg=$func_stripname_result + + # Add the arguments to base_compile. + func_append base_compile " $lastarg" + continue + ;; + + *) + # Accept the current argument as the source file. + # The previous "srcfile" becomes the current argument. + # + lastarg="$srcfile" + srcfile="$arg" + ;; + esac # case $arg + ;; + esac # case $arg_mode + + # Aesthetically quote the previous argument. + func_append_quoted base_compile "$lastarg" + done # for arg + + case $arg_mode in + arg) + func_fatal_error "you must specify an argument for -Xcompile" + ;; + target) + func_fatal_error "you must specify a target with \`-o'" + ;; + *) + # Get the name of the library object. + test -z "$libobj" && { + func_basename "$srcfile" + libobj="$func_basename_result" + } + ;; + esac + + # Recognize several different file suffixes. + # If the user specifies -o file.o, it is replaced with file.lo + case $libobj in + *.[cCFSifmso] | \ + *.ada | *.adb | *.ads | *.asm | \ + *.c++ | *.cc | *.ii | *.class | *.cpp | *.cxx | \ + *.[fF][09]? | *.for | *.java | *.go | *.obj | *.sx | *.cu | *.cup) + func_xform "$libobj" + libobj=$func_xform_result + ;; + esac + + case $libobj in + *.lo) func_lo2o "$libobj"; obj=$func_lo2o_result ;; + *) + func_fatal_error "cannot determine name of library object from \`$libobj'" + ;; + esac + + func_infer_tag $base_compile + + for arg in $later; do + case $arg in + -shared) + test "$build_libtool_libs" != yes && \ + func_fatal_configuration "can not build a shared library" + build_old_libs=no + continue + ;; + + -static) + build_libtool_libs=no + build_old_libs=yes + continue + ;; + + -prefer-pic) + pic_mode=yes + continue + ;; + + -prefer-non-pic) + pic_mode=no + continue + ;; + esac + done + + func_quote_for_eval "$libobj" + test "X$libobj" != "X$func_quote_for_eval_result" \ + && $ECHO "X$libobj" | $GREP '[]~#^*{};<>?"'"'"' &()|`$[]' \ + && func_warning "libobj name \`$libobj' may not contain shell special characters." + func_dirname_and_basename "$obj" "/" "" + objname="$func_basename_result" + xdir="$func_dirname_result" + lobj=${xdir}$objdir/$objname + + test -z "$base_compile" && \ + func_fatal_help "you must specify a compilation command" + + # Delete any leftover library objects. + if test "$build_old_libs" = yes; then + removelist="$obj $lobj $libobj ${libobj}T" + else + removelist="$lobj $libobj ${libobj}T" + fi + + # On Cygwin there's no "real" PIC flag so we must build both object types + case $host_os in + cygwin* | mingw* | pw32* | os2* | cegcc*) + pic_mode=default + ;; + esac + if test "$pic_mode" = no && test "$deplibs_check_method" != pass_all; then + # non-PIC code in shared libraries is not supported + pic_mode=default + fi + + # Calculate the filename of the output object if compiler does + # not support -o with -c + if test "$compiler_c_o" = no; then + output_obj=`$ECHO "$srcfile" | $SED 's%^.*/%%; s%\.[^.]*$%%'`.${objext} + lockfile="$output_obj.lock" + else + output_obj= + need_locks=no + lockfile= + fi + + # Lock this critical section if it is needed + # We use this script file to make the link, it avoids creating a new file + if test "$need_locks" = yes; then + until $opt_dry_run || ln "$progpath" "$lockfile" 2>/dev/null; do + func_echo "Waiting for $lockfile to be removed" + sleep 2 + done + elif test "$need_locks" = warn; then + if test -f "$lockfile"; then + $ECHO "\ +*** ERROR, $lockfile exists and contains: +`cat $lockfile 2>/dev/null` + +This indicates that another process is trying to use the same +temporary object file, and libtool could not work around it because +your compiler does not support \`-c' and \`-o' together. If you +repeat this compilation, it may succeed, by chance, but you had better +avoid parallel builds (make -j) in this platform, or get a better +compiler." + + $opt_dry_run || $RM $removelist + exit $EXIT_FAILURE + fi + func_append removelist " $output_obj" + $ECHO "$srcfile" > "$lockfile" + fi + + $opt_dry_run || $RM $removelist + func_append removelist " $lockfile" + trap '$opt_dry_run || $RM $removelist; exit $EXIT_FAILURE' 1 2 15 + + func_to_tool_file "$srcfile" func_convert_file_msys_to_w32 + srcfile=$func_to_tool_file_result + func_quote_for_eval "$srcfile" + qsrcfile=$func_quote_for_eval_result + + # Only build a PIC object if we are building libtool libraries. + if test "$build_libtool_libs" = yes; then + # Without this assignment, base_compile gets emptied. + fbsd_hideous_sh_bug=$base_compile + + if test "$pic_mode" != no; then + command="$base_compile $qsrcfile $pic_flag" + else + # Don't build PIC code + command="$base_compile $qsrcfile" + fi + + func_mkdir_p "$xdir$objdir" + + if test -z "$output_obj"; then + # Place PIC objects in $objdir + func_append command " -o $lobj" + fi + + func_show_eval_locale "$command" \ + 'test -n "$output_obj" && $RM $removelist; exit $EXIT_FAILURE' + + if test "$need_locks" = warn && + test "X`cat $lockfile 2>/dev/null`" != "X$srcfile"; then + $ECHO "\ +*** ERROR, $lockfile contains: +`cat $lockfile 2>/dev/null` + +but it should contain: +$srcfile + +This indicates that another process is trying to use the same +temporary object file, and libtool could not work around it because +your compiler does not support \`-c' and \`-o' together. If you +repeat this compilation, it may succeed, by chance, but you had better +avoid parallel builds (make -j) in this platform, or get a better +compiler." + + $opt_dry_run || $RM $removelist + exit $EXIT_FAILURE + fi + + # Just move the object if needed, then go on to compile the next one + if test -n "$output_obj" && test "X$output_obj" != "X$lobj"; then + func_show_eval '$MV "$output_obj" "$lobj"' \ + 'error=$?; $opt_dry_run || $RM $removelist; exit $error' + fi + + # Allow error messages only from the first compilation. + if test "$suppress_opt" = yes; then + suppress_output=' >/dev/null 2>&1' + fi + fi + + # Only build a position-dependent object if we build old libraries. + if test "$build_old_libs" = yes; then + if test "$pic_mode" != yes; then + # Don't build PIC code + command="$base_compile $qsrcfile$pie_flag" + else + command="$base_compile $qsrcfile $pic_flag" + fi + if test "$compiler_c_o" = yes; then + func_append command " -o $obj" + fi + + # Suppress compiler output if we already did a PIC compilation. + func_append command "$suppress_output" + func_show_eval_locale "$command" \ + '$opt_dry_run || $RM $removelist; exit $EXIT_FAILURE' + + if test "$need_locks" = warn && + test "X`cat $lockfile 2>/dev/null`" != "X$srcfile"; then + $ECHO "\ +*** ERROR, $lockfile contains: +`cat $lockfile 2>/dev/null` + +but it should contain: +$srcfile + +This indicates that another process is trying to use the same +temporary object file, and libtool could not work around it because +your compiler does not support \`-c' and \`-o' together. If you +repeat this compilation, it may succeed, by chance, but you had better +avoid parallel builds (make -j) in this platform, or get a better +compiler." + + $opt_dry_run || $RM $removelist + exit $EXIT_FAILURE + fi + + # Just move the object if needed + if test -n "$output_obj" && test "X$output_obj" != "X$obj"; then + func_show_eval '$MV "$output_obj" "$obj"' \ + 'error=$?; $opt_dry_run || $RM $removelist; exit $error' + fi + fi + + $opt_dry_run || { + func_write_libtool_object "$libobj" "$objdir/$objname" "$objname" + + # Unlock the critical section if it was locked + if test "$need_locks" != no; then + removelist=$lockfile + $RM "$lockfile" + fi + } + + exit $EXIT_SUCCESS +} + +$opt_help || { + test "$opt_mode" = compile && func_mode_compile ${1+"$@"} +} + +func_mode_help () +{ + # We need to display help for each of the modes. + case $opt_mode in + "") + # Generic help is extracted from the usage comments + # at the start of this file. + func_help + ;; + + clean) + $ECHO \ +"Usage: $progname [OPTION]... --mode=clean RM [RM-OPTION]... FILE... + +Remove files from the build directory. + +RM is the name of the program to use to delete files associated with each FILE +(typically \`/bin/rm'). RM-OPTIONS are options (such as \`-f') to be passed +to RM. + +If FILE is a libtool library, object or program, all the files associated +with it are deleted. Otherwise, only FILE itself is deleted using RM." + ;; + + compile) + $ECHO \ +"Usage: $progname [OPTION]... --mode=compile COMPILE-COMMAND... SOURCEFILE + +Compile a source file into a libtool library object. + +This mode accepts the following additional options: + + -o OUTPUT-FILE set the output file name to OUTPUT-FILE + -no-suppress do not suppress compiler output for multiple passes + -prefer-pic try to build PIC objects only + -prefer-non-pic try to build non-PIC objects only + -shared do not build a \`.o' file suitable for static linking + -static only build a \`.o' file suitable for static linking + -Wc,FLAG pass FLAG directly to the compiler + +COMPILE-COMMAND is a command to be used in creating a \`standard' object file +from the given SOURCEFILE. + +The output file name is determined by removing the directory component from +SOURCEFILE, then substituting the C source code suffix \`.c' with the +library object suffix, \`.lo'." + ;; + + execute) + $ECHO \ +"Usage: $progname [OPTION]... --mode=execute COMMAND [ARGS]... + +Automatically set library path, then run a program. + +This mode accepts the following additional options: + + -dlopen FILE add the directory containing FILE to the library path + +This mode sets the library path environment variable according to \`-dlopen' +flags. + +If any of the ARGS are libtool executable wrappers, then they are translated +into their corresponding uninstalled binary, and any of their required library +directories are added to the library path. + +Then, COMMAND is executed, with ARGS as arguments." + ;; + + finish) + $ECHO \ +"Usage: $progname [OPTION]... --mode=finish [LIBDIR]... + +Complete the installation of libtool libraries. + +Each LIBDIR is a directory that contains libtool libraries. + +The commands that this mode executes may require superuser privileges. Use +the \`--dry-run' option if you just want to see what would be executed." + ;; + + install) + $ECHO \ +"Usage: $progname [OPTION]... --mode=install INSTALL-COMMAND... + +Install executables or libraries. + +INSTALL-COMMAND is the installation command. The first component should be +either the \`install' or \`cp' program. + +The following components of INSTALL-COMMAND are treated specially: + + -inst-prefix-dir PREFIX-DIR Use PREFIX-DIR as a staging area for installation + +The rest of the components are interpreted as arguments to that command (only +BSD-compatible install options are recognized)." + ;; + + link) + $ECHO \ +"Usage: $progname [OPTION]... --mode=link LINK-COMMAND... + +Link object files or libraries together to form another library, or to +create an executable program. + +LINK-COMMAND is a command using the C compiler that you would use to create +a program from several object files. + +The following components of LINK-COMMAND are treated specially: + + -all-static do not do any dynamic linking at all + -avoid-version do not add a version suffix if possible + -bindir BINDIR specify path to binaries directory (for systems where + libraries must be found in the PATH setting at runtime) + -dlopen FILE \`-dlpreopen' FILE if it cannot be dlopened at runtime + -dlpreopen FILE link in FILE and add its symbols to lt_preloaded_symbols + -export-dynamic allow symbols from OUTPUT-FILE to be resolved with dlsym(3) + -export-symbols SYMFILE + try to export only the symbols listed in SYMFILE + -export-symbols-regex REGEX + try to export only the symbols matching REGEX + -LLIBDIR search LIBDIR for required installed libraries + -lNAME OUTPUT-FILE requires the installed library libNAME + -module build a library that can dlopened + -no-fast-install disable the fast-install mode + -no-install link a not-installable executable + -no-undefined declare that a library does not refer to external symbols + -o OUTPUT-FILE create OUTPUT-FILE from the specified objects + -objectlist FILE Use a list of object files found in FILE to specify objects + -precious-files-regex REGEX + don't remove output files matching REGEX + -release RELEASE specify package release information + -rpath LIBDIR the created library will eventually be installed in LIBDIR + -R[ ]LIBDIR add LIBDIR to the runtime path of programs and libraries + -shared only do dynamic linking of libtool libraries + -shrext SUFFIX override the standard shared library file extension + -static do not do any dynamic linking of uninstalled libtool libraries + -static-libtool-libs + do not do any dynamic linking of libtool libraries + -version-info CURRENT[:REVISION[:AGE]] + specify library version info [each variable defaults to 0] + -weak LIBNAME declare that the target provides the LIBNAME interface + -Wc,FLAG + -Xcompiler FLAG pass linker-specific FLAG directly to the compiler + -Wl,FLAG + -Xlinker FLAG pass linker-specific FLAG directly to the linker + -XCClinker FLAG pass link-specific FLAG to the compiler driver (CC) + +All other options (arguments beginning with \`-') are ignored. + +Every other argument is treated as a filename. Files ending in \`.la' are +treated as uninstalled libtool libraries, other files are standard or library +object files. + +If the OUTPUT-FILE ends in \`.la', then a libtool library is created, +only library objects (\`.lo' files) may be specified, and \`-rpath' is +required, except when creating a convenience library. + +If OUTPUT-FILE ends in \`.a' or \`.lib', then a standard library is created +using \`ar' and \`ranlib', or on Windows using \`lib'. + +If OUTPUT-FILE ends in \`.lo' or \`.${objext}', then a reloadable object file +is created, otherwise an executable program is created." + ;; + + uninstall) + $ECHO \ +"Usage: $progname [OPTION]... --mode=uninstall RM [RM-OPTION]... FILE... + +Remove libraries from an installation directory. + +RM is the name of the program to use to delete files associated with each FILE +(typically \`/bin/rm'). RM-OPTIONS are options (such as \`-f') to be passed +to RM. + +If FILE is a libtool library, all the files associated with it are deleted. +Otherwise, only FILE itself is deleted using RM." + ;; + + *) + func_fatal_help "invalid operation mode \`$opt_mode'" + ;; + esac + + echo + $ECHO "Try \`$progname --help' for more information about other modes." +} + +# Now that we've collected a possible --mode arg, show help if necessary +if $opt_help; then + if test "$opt_help" = :; then + func_mode_help + else + { + func_help noexit + for opt_mode in compile link execute install finish uninstall clean; do + func_mode_help + done + } | sed -n '1p; 2,$s/^Usage:/ or: /p' + { + func_help noexit + for opt_mode in compile link execute install finish uninstall clean; do + echo + func_mode_help + done + } | + sed '1d + /^When reporting/,/^Report/{ + H + d + } + $x + /information about other modes/d + /more detailed .*MODE/d + s/^Usage:.*--mode=\([^ ]*\) .*/Description of \1 mode:/' + fi + exit $? +fi + + +# func_mode_execute arg... +func_mode_execute () +{ + $opt_debug + # The first argument is the command name. + cmd="$nonopt" + test -z "$cmd" && \ + func_fatal_help "you must specify a COMMAND" + + # Handle -dlopen flags immediately. + for file in $opt_dlopen; do + test -f "$file" \ + || func_fatal_help "\`$file' is not a file" + + dir= + case $file in + *.la) + func_resolve_sysroot "$file" + file=$func_resolve_sysroot_result + + # Check to see that this really is a libtool archive. + func_lalib_unsafe_p "$file" \ + || func_fatal_help "\`$lib' is not a valid libtool archive" + + # Read the libtool library. + dlname= + library_names= + func_source "$file" + + # Skip this library if it cannot be dlopened. + if test -z "$dlname"; then + # Warn if it was a shared library. + test -n "$library_names" && \ + func_warning "\`$file' was not linked with \`-export-dynamic'" + continue + fi + + func_dirname "$file" "" "." + dir="$func_dirname_result" + + if test -f "$dir/$objdir/$dlname"; then + func_append dir "/$objdir" + else + if test ! -f "$dir/$dlname"; then + func_fatal_error "cannot find \`$dlname' in \`$dir' or \`$dir/$objdir'" + fi + fi + ;; + + *.lo) + # Just add the directory containing the .lo file. + func_dirname "$file" "" "." + dir="$func_dirname_result" + ;; + + *) + func_warning "\`-dlopen' is ignored for non-libtool libraries and objects" + continue + ;; + esac + + # Get the absolute pathname. + absdir=`cd "$dir" && pwd` + test -n "$absdir" && dir="$absdir" + + # Now add the directory to shlibpath_var. + if eval "test -z \"\$$shlibpath_var\""; then + eval "$shlibpath_var=\"\$dir\"" + else + eval "$shlibpath_var=\"\$dir:\$$shlibpath_var\"" + fi + done + + # This variable tells wrapper scripts just to set shlibpath_var + # rather than running their programs. + libtool_execute_magic="$magic" + + # Check if any of the arguments is a wrapper script. + args= + for file + do + case $file in + -* | *.la | *.lo ) ;; + *) + # Do a test to see if this is really a libtool program. + if func_ltwrapper_script_p "$file"; then + func_source "$file" + # Transform arg to wrapped name. + file="$progdir/$program" + elif func_ltwrapper_executable_p "$file"; then + func_ltwrapper_scriptname "$file" + func_source "$func_ltwrapper_scriptname_result" + # Transform arg to wrapped name. + file="$progdir/$program" + fi + ;; + esac + # Quote arguments (to preserve shell metacharacters). + func_append_quoted args "$file" + done + + if test "X$opt_dry_run" = Xfalse; then + if test -n "$shlibpath_var"; then + # Export the shlibpath_var. + eval "export $shlibpath_var" + fi + + # Restore saved environment variables + for lt_var in LANG LANGUAGE LC_ALL LC_CTYPE LC_COLLATE LC_MESSAGES + do + eval "if test \"\${save_$lt_var+set}\" = set; then + $lt_var=\$save_$lt_var; export $lt_var + else + $lt_unset $lt_var + fi" + done + + # Now prepare to actually exec the command. + exec_cmd="\$cmd$args" + else + # Display what would be done. + if test -n "$shlibpath_var"; then + eval "\$ECHO \"\$shlibpath_var=\$$shlibpath_var\"" + echo "export $shlibpath_var" + fi + $ECHO "$cmd$args" + exit $EXIT_SUCCESS + fi +} + +test "$opt_mode" = execute && func_mode_execute ${1+"$@"} + + +# func_mode_finish arg... +func_mode_finish () +{ + $opt_debug + libs= + libdirs= + admincmds= + + for opt in "$nonopt" ${1+"$@"} + do + if test -d "$opt"; then + func_append libdirs " $opt" + + elif test -f "$opt"; then + if func_lalib_unsafe_p "$opt"; then + func_append libs " $opt" + else + func_warning "\`$opt' is not a valid libtool archive" + fi + + else + func_fatal_error "invalid argument \`$opt'" + fi + done + + if test -n "$libs"; then + if test -n "$lt_sysroot"; then + sysroot_regex=`$ECHO "$lt_sysroot" | $SED "$sed_make_literal_regex"` + sysroot_cmd="s/\([ ']\)$sysroot_regex/\1/g;" + else + sysroot_cmd= + fi + + # Remove sysroot references + if $opt_dry_run; then + for lib in $libs; do + echo "removing references to $lt_sysroot and \`=' prefixes from $lib" + done + else + tmpdir=`func_mktempdir` + for lib in $libs; do + sed -e "${sysroot_cmd} s/\([ ']-[LR]\)=/\1/g; s/\([ ']\)=/\1/g" $lib \ + > $tmpdir/tmp-la + mv -f $tmpdir/tmp-la $lib + done + ${RM}r "$tmpdir" + fi + fi + + if test -n "$finish_cmds$finish_eval" && test -n "$libdirs"; then + for libdir in $libdirs; do + if test -n "$finish_cmds"; then + # Do each command in the finish commands. + func_execute_cmds "$finish_cmds" 'admincmds="$admincmds +'"$cmd"'"' + fi + if test -n "$finish_eval"; then + # Do the single finish_eval. + eval cmds=\"$finish_eval\" + $opt_dry_run || eval "$cmds" || func_append admincmds " + $cmds" + fi + done + fi + + # Exit here if they wanted silent mode. + $opt_silent && exit $EXIT_SUCCESS + + if test -n "$finish_cmds$finish_eval" && test -n "$libdirs"; then + echo "----------------------------------------------------------------------" + echo "Libraries have been installed in:" + for libdir in $libdirs; do + $ECHO " $libdir" + done + echo + echo "If you ever happen to want to link against installed libraries" + echo "in a given directory, LIBDIR, you must either use libtool, and" + echo "specify the full pathname of the library, or use the \`-LLIBDIR'" + echo "flag during linking and do at least one of the following:" + if test -n "$shlibpath_var"; then + echo " - add LIBDIR to the \`$shlibpath_var' environment variable" + echo " during execution" + fi + if test -n "$runpath_var"; then + echo " - add LIBDIR to the \`$runpath_var' environment variable" + echo " during linking" + fi + if test -n "$hardcode_libdir_flag_spec"; then + libdir=LIBDIR + eval flag=\"$hardcode_libdir_flag_spec\" + + $ECHO " - use the \`$flag' linker flag" + fi + if test -n "$admincmds"; then + $ECHO " - have your system administrator run these commands:$admincmds" + fi + if test -f /etc/ld.so.conf; then + echo " - have your system administrator add LIBDIR to \`/etc/ld.so.conf'" + fi + echo + + echo "See any operating system documentation about shared libraries for" + case $host in + solaris2.[6789]|solaris2.1[0-9]) + echo "more information, such as the ld(1), crle(1) and ld.so(8) manual" + echo "pages." + ;; + *) + echo "more information, such as the ld(1) and ld.so(8) manual pages." + ;; + esac + echo "----------------------------------------------------------------------" + fi + exit $EXIT_SUCCESS +} + +test "$opt_mode" = finish && func_mode_finish ${1+"$@"} + + +# func_mode_install arg... +func_mode_install () +{ + $opt_debug + # There may be an optional sh(1) argument at the beginning of + # install_prog (especially on Windows NT). + if test "$nonopt" = "$SHELL" || test "$nonopt" = /bin/sh || + # Allow the use of GNU shtool's install command. + case $nonopt in *shtool*) :;; *) false;; esac; then + # Aesthetically quote it. + func_quote_for_eval "$nonopt" + install_prog="$func_quote_for_eval_result " + arg=$1 + shift + else + install_prog= + arg=$nonopt + fi + + # The real first argument should be the name of the installation program. + # Aesthetically quote it. + func_quote_for_eval "$arg" + func_append install_prog "$func_quote_for_eval_result" + install_shared_prog=$install_prog + case " $install_prog " in + *[\\\ /]cp\ *) install_cp=: ;; + *) install_cp=false ;; + esac + + # We need to accept at least all the BSD install flags. + dest= + files= + opts= + prev= + install_type= + isdir=no + stripme= + no_mode=: + for arg + do + arg2= + if test -n "$dest"; then + func_append files " $dest" + dest=$arg + continue + fi + + case $arg in + -d) isdir=yes ;; + -f) + if $install_cp; then :; else + prev=$arg + fi + ;; + -g | -m | -o) + prev=$arg + ;; + -s) + stripme=" -s" + continue + ;; + -*) + ;; + *) + # If the previous option needed an argument, then skip it. + if test -n "$prev"; then + if test "x$prev" = x-m && test -n "$install_override_mode"; then + arg2=$install_override_mode + no_mode=false + fi + prev= + else + dest=$arg + continue + fi + ;; + esac + + # Aesthetically quote the argument. + func_quote_for_eval "$arg" + func_append install_prog " $func_quote_for_eval_result" + if test -n "$arg2"; then + func_quote_for_eval "$arg2" + fi + func_append install_shared_prog " $func_quote_for_eval_result" + done + + test -z "$install_prog" && \ + func_fatal_help "you must specify an install program" + + test -n "$prev" && \ + func_fatal_help "the \`$prev' option requires an argument" + + if test -n "$install_override_mode" && $no_mode; then + if $install_cp; then :; else + func_quote_for_eval "$install_override_mode" + func_append install_shared_prog " -m $func_quote_for_eval_result" + fi + fi + + if test -z "$files"; then + if test -z "$dest"; then + func_fatal_help "no file or destination specified" + else + func_fatal_help "you must specify a destination" + fi + fi + + # Strip any trailing slash from the destination. + func_stripname '' '/' "$dest" + dest=$func_stripname_result + + # Check to see that the destination is a directory. + test -d "$dest" && isdir=yes + if test "$isdir" = yes; then + destdir="$dest" + destname= + else + func_dirname_and_basename "$dest" "" "." + destdir="$func_dirname_result" + destname="$func_basename_result" + + # Not a directory, so check to see that there is only one file specified. + set dummy $files; shift + test "$#" -gt 1 && \ + func_fatal_help "\`$dest' is not a directory" + fi + case $destdir in + [\\/]* | [A-Za-z]:[\\/]*) ;; + *) + for file in $files; do + case $file in + *.lo) ;; + *) + func_fatal_help "\`$destdir' must be an absolute directory name" + ;; + esac + done + ;; + esac + + # This variable tells wrapper scripts just to set variables rather + # than running their programs. + libtool_install_magic="$magic" + + staticlibs= + future_libdirs= + current_libdirs= + for file in $files; do + + # Do each installation. + case $file in + *.$libext) + # Do the static libraries later. + func_append staticlibs " $file" + ;; + + *.la) + func_resolve_sysroot "$file" + file=$func_resolve_sysroot_result + + # Check to see that this really is a libtool archive. + func_lalib_unsafe_p "$file" \ + || func_fatal_help "\`$file' is not a valid libtool archive" + + library_names= + old_library= + relink_command= + func_source "$file" + + # Add the libdir to current_libdirs if it is the destination. + if test "X$destdir" = "X$libdir"; then + case "$current_libdirs " in + *" $libdir "*) ;; + *) func_append current_libdirs " $libdir" ;; + esac + else + # Note the libdir as a future libdir. + case "$future_libdirs " in + *" $libdir "*) ;; + *) func_append future_libdirs " $libdir" ;; + esac + fi + + func_dirname "$file" "/" "" + dir="$func_dirname_result" + func_append dir "$objdir" + + if test -n "$relink_command"; then + # Determine the prefix the user has applied to our future dir. + inst_prefix_dir=`$ECHO "$destdir" | $SED -e "s%$libdir\$%%"` + + # Don't allow the user to place us outside of our expected + # location b/c this prevents finding dependent libraries that + # are installed to the same prefix. + # At present, this check doesn't affect windows .dll's that + # are installed into $libdir/../bin (currently, that works fine) + # but it's something to keep an eye on. + test "$inst_prefix_dir" = "$destdir" && \ + func_fatal_error "error: cannot install \`$file' to a directory not ending in $libdir" + + if test -n "$inst_prefix_dir"; then + # Stick the inst_prefix_dir data into the link command. + relink_command=`$ECHO "$relink_command" | $SED "s%@inst_prefix_dir@%-inst-prefix-dir $inst_prefix_dir%"` + else + relink_command=`$ECHO "$relink_command" | $SED "s%@inst_prefix_dir@%%"` + fi + + func_warning "relinking \`$file'" + func_show_eval "$relink_command" \ + 'func_fatal_error "error: relink \`$file'\'' with the above command before installing it"' + fi + + # See the names of the shared library. + set dummy $library_names; shift + if test -n "$1"; then + realname="$1" + shift + + srcname="$realname" + test -n "$relink_command" && srcname="$realname"T + + # Install the shared library and build the symlinks. + func_show_eval "$install_shared_prog $dir/$srcname $destdir/$realname" \ + 'exit $?' + tstripme="$stripme" + case $host_os in + cygwin* | mingw* | pw32* | cegcc*) + case $realname in + *.dll.a) + tstripme="" + ;; + esac + ;; + esac + if test -n "$tstripme" && test -n "$striplib"; then + func_show_eval "$striplib $destdir/$realname" 'exit $?' + fi + + if test "$#" -gt 0; then + # Delete the old symlinks, and create new ones. + # Try `ln -sf' first, because the `ln' binary might depend on + # the symlink we replace! Solaris /bin/ln does not understand -f, + # so we also need to try rm && ln -s. + for linkname + do + test "$linkname" != "$realname" \ + && func_show_eval "(cd $destdir && { $LN_S -f $realname $linkname || { $RM $linkname && $LN_S $realname $linkname; }; })" + done + fi + + # Do each command in the postinstall commands. + lib="$destdir/$realname" + func_execute_cmds "$postinstall_cmds" 'exit $?' + fi + + # Install the pseudo-library for information purposes. + func_basename "$file" + name="$func_basename_result" + instname="$dir/$name"i + func_show_eval "$install_prog $instname $destdir/$name" 'exit $?' + + # Maybe install the static library, too. + test -n "$old_library" && func_append staticlibs " $dir/$old_library" + ;; + + *.lo) + # Install (i.e. copy) a libtool object. + + # Figure out destination file name, if it wasn't already specified. + if test -n "$destname"; then + destfile="$destdir/$destname" + else + func_basename "$file" + destfile="$func_basename_result" + destfile="$destdir/$destfile" + fi + + # Deduce the name of the destination old-style object file. + case $destfile in + *.lo) + func_lo2o "$destfile" + staticdest=$func_lo2o_result + ;; + *.$objext) + staticdest="$destfile" + destfile= + ;; + *) + func_fatal_help "cannot copy a libtool object to \`$destfile'" + ;; + esac + + # Install the libtool object if requested. + test -n "$destfile" && \ + func_show_eval "$install_prog $file $destfile" 'exit $?' + + # Install the old object if enabled. + if test "$build_old_libs" = yes; then + # Deduce the name of the old-style object file. + func_lo2o "$file" + staticobj=$func_lo2o_result + func_show_eval "$install_prog \$staticobj \$staticdest" 'exit $?' + fi + exit $EXIT_SUCCESS + ;; + + *) + # Figure out destination file name, if it wasn't already specified. + if test -n "$destname"; then + destfile="$destdir/$destname" + else + func_basename "$file" + destfile="$func_basename_result" + destfile="$destdir/$destfile" + fi + + # If the file is missing, and there is a .exe on the end, strip it + # because it is most likely a libtool script we actually want to + # install + stripped_ext="" + case $file in + *.exe) + if test ! -f "$file"; then + func_stripname '' '.exe' "$file" + file=$func_stripname_result + stripped_ext=".exe" + fi + ;; + esac + + # Do a test to see if this is really a libtool program. + case $host in + *cygwin* | *mingw*) + if func_ltwrapper_executable_p "$file"; then + func_ltwrapper_scriptname "$file" + wrapper=$func_ltwrapper_scriptname_result + else + func_stripname '' '.exe' "$file" + wrapper=$func_stripname_result + fi + ;; + *) + wrapper=$file + ;; + esac + if func_ltwrapper_script_p "$wrapper"; then + notinst_deplibs= + relink_command= + + func_source "$wrapper" + + # Check the variables that should have been set. + test -z "$generated_by_libtool_version" && \ + func_fatal_error "invalid libtool wrapper script \`$wrapper'" + + finalize=yes + for lib in $notinst_deplibs; do + # Check to see that each library is installed. + libdir= + if test -f "$lib"; then + func_source "$lib" + fi + libfile="$libdir/"`$ECHO "$lib" | $SED 's%^.*/%%g'` ### testsuite: skip nested quoting test + if test -n "$libdir" && test ! -f "$libfile"; then + func_warning "\`$lib' has not been installed in \`$libdir'" + finalize=no + fi + done + + relink_command= + func_source "$wrapper" + + outputname= + if test "$fast_install" = no && test -n "$relink_command"; then + $opt_dry_run || { + if test "$finalize" = yes; then + tmpdir=`func_mktempdir` + func_basename "$file$stripped_ext" + file="$func_basename_result" + outputname="$tmpdir/$file" + # Replace the output file specification. + relink_command=`$ECHO "$relink_command" | $SED 's%@OUTPUT@%'"$outputname"'%g'` + + $opt_silent || { + func_quote_for_expand "$relink_command" + eval "func_echo $func_quote_for_expand_result" + } + if eval "$relink_command"; then : + else + func_error "error: relink \`$file' with the above command before installing it" + $opt_dry_run || ${RM}r "$tmpdir" + continue + fi + file="$outputname" + else + func_warning "cannot relink \`$file'" + fi + } + else + # Install the binary that we compiled earlier. + file=`$ECHO "$file$stripped_ext" | $SED "s%\([^/]*\)$%$objdir/\1%"` + fi + fi + + # remove .exe since cygwin /usr/bin/install will append another + # one anyway + case $install_prog,$host in + */usr/bin/install*,*cygwin*) + case $file:$destfile in + *.exe:*.exe) + # this is ok + ;; + *.exe:*) + destfile=$destfile.exe + ;; + *:*.exe) + func_stripname '' '.exe' "$destfile" + destfile=$func_stripname_result + ;; + esac + ;; + esac + func_show_eval "$install_prog\$stripme \$file \$destfile" 'exit $?' + $opt_dry_run || if test -n "$outputname"; then + ${RM}r "$tmpdir" + fi + ;; + esac + done + + for file in $staticlibs; do + func_basename "$file" + name="$func_basename_result" + + # Set up the ranlib parameters. + oldlib="$destdir/$name" + func_to_tool_file "$oldlib" func_convert_file_msys_to_w32 + tool_oldlib=$func_to_tool_file_result + + func_show_eval "$install_prog \$file \$oldlib" 'exit $?' + + if test -n "$stripme" && test -n "$old_striplib"; then + func_show_eval "$old_striplib $tool_oldlib" 'exit $?' + fi + + # Do each command in the postinstall commands. + func_execute_cmds "$old_postinstall_cmds" 'exit $?' + done + + test -n "$future_libdirs" && \ + func_warning "remember to run \`$progname --finish$future_libdirs'" + + if test -n "$current_libdirs"; then + # Maybe just do a dry run. + $opt_dry_run && current_libdirs=" -n$current_libdirs" + exec_cmd='$SHELL $progpath $preserve_args --finish$current_libdirs' + else + exit $EXIT_SUCCESS + fi +} + +test "$opt_mode" = install && func_mode_install ${1+"$@"} + + +# func_generate_dlsyms outputname originator pic_p +# Extract symbols from dlprefiles and create ${outputname}S.o with +# a dlpreopen symbol table. +func_generate_dlsyms () +{ + $opt_debug + my_outputname="$1" + my_originator="$2" + my_pic_p="${3-no}" + my_prefix=`$ECHO "$my_originator" | sed 's%[^a-zA-Z0-9]%_%g'` + my_dlsyms= + + if test -n "$dlfiles$dlprefiles" || test "$dlself" != no; then + if test -n "$NM" && test -n "$global_symbol_pipe"; then + my_dlsyms="${my_outputname}S.c" + else + func_error "not configured to extract global symbols from dlpreopened files" + fi + fi + + if test -n "$my_dlsyms"; then + case $my_dlsyms in + "") ;; + *.c) + # Discover the nlist of each of the dlfiles. + nlist="$output_objdir/${my_outputname}.nm" + + func_show_eval "$RM $nlist ${nlist}S ${nlist}T" + + # Parse the name list into a source file. + func_verbose "creating $output_objdir/$my_dlsyms" + + $opt_dry_run || $ECHO > "$output_objdir/$my_dlsyms" "\ +/* $my_dlsyms - symbol resolution table for \`$my_outputname' dlsym emulation. */ +/* Generated by $PROGRAM (GNU $PACKAGE$TIMESTAMP) $VERSION */ + +#ifdef __cplusplus +extern \"C\" { +#endif + +#if defined(__GNUC__) && (((__GNUC__ == 4) && (__GNUC_MINOR__ >= 4)) || (__GNUC__ > 4)) +#pragma GCC diagnostic ignored \"-Wstrict-prototypes\" +#endif + +/* Keep this code in sync between libtool.m4, ltmain, lt_system.h, and tests. */ +#if defined(_WIN32) || defined(__CYGWIN__) || defined(_WIN32_WCE) +/* DATA imports from DLLs on WIN32 con't be const, because runtime + relocations are performed -- see ld's documentation on pseudo-relocs. */ +# define LT_DLSYM_CONST +#elif defined(__osf__) +/* This system does not cope well with relocations in const data. */ +# define LT_DLSYM_CONST +#else +# define LT_DLSYM_CONST const +#endif + +/* External symbol declarations for the compiler. */\ +" + + if test "$dlself" = yes; then + func_verbose "generating symbol list for \`$output'" + + $opt_dry_run || echo ': @PROGRAM@ ' > "$nlist" + + # Add our own program objects to the symbol list. + progfiles=`$ECHO "$objs$old_deplibs" | $SP2NL | $SED "$lo2o" | $NL2SP` + for progfile in $progfiles; do + func_to_tool_file "$progfile" func_convert_file_msys_to_w32 + func_verbose "extracting global C symbols from \`$func_to_tool_file_result'" + $opt_dry_run || eval "$NM $func_to_tool_file_result | $global_symbol_pipe >> '$nlist'" + done + + if test -n "$exclude_expsyms"; then + $opt_dry_run || { + eval '$EGREP -v " ($exclude_expsyms)$" "$nlist" > "$nlist"T' + eval '$MV "$nlist"T "$nlist"' + } + fi + + if test -n "$export_symbols_regex"; then + $opt_dry_run || { + eval '$EGREP -e "$export_symbols_regex" "$nlist" > "$nlist"T' + eval '$MV "$nlist"T "$nlist"' + } + fi + + # Prepare the list of exported symbols + if test -z "$export_symbols"; then + export_symbols="$output_objdir/$outputname.exp" + $opt_dry_run || { + $RM $export_symbols + eval "${SED} -n -e '/^: @PROGRAM@ $/d' -e 's/^.* \(.*\)$/\1/p' "'< "$nlist" > "$export_symbols"' + case $host in + *cygwin* | *mingw* | *cegcc* ) + eval "echo EXPORTS "'> "$output_objdir/$outputname.def"' + eval 'cat "$export_symbols" >> "$output_objdir/$outputname.def"' + ;; + esac + } + else + $opt_dry_run || { + eval "${SED} -e 's/\([].[*^$]\)/\\\\\1/g' -e 's/^/ /' -e 's/$/$/'"' < "$export_symbols" > "$output_objdir/$outputname.exp"' + eval '$GREP -f "$output_objdir/$outputname.exp" < "$nlist" > "$nlist"T' + eval '$MV "$nlist"T "$nlist"' + case $host in + *cygwin* | *mingw* | *cegcc* ) + eval "echo EXPORTS "'> "$output_objdir/$outputname.def"' + eval 'cat "$nlist" >> "$output_objdir/$outputname.def"' + ;; + esac + } + fi + fi + + for dlprefile in $dlprefiles; do + func_verbose "extracting global C symbols from \`$dlprefile'" + func_basename "$dlprefile" + name="$func_basename_result" + case $host in + *cygwin* | *mingw* | *cegcc* ) + # if an import library, we need to obtain dlname + if func_win32_import_lib_p "$dlprefile"; then + func_tr_sh "$dlprefile" + eval "curr_lafile=\$libfile_$func_tr_sh_result" + dlprefile_dlbasename="" + if test -n "$curr_lafile" && func_lalib_p "$curr_lafile"; then + # Use subshell, to avoid clobbering current variable values + dlprefile_dlname=`source "$curr_lafile" && echo "$dlname"` + if test -n "$dlprefile_dlname" ; then + func_basename "$dlprefile_dlname" + dlprefile_dlbasename="$func_basename_result" + else + # no lafile. user explicitly requested -dlpreopen . + $sharedlib_from_linklib_cmd "$dlprefile" + dlprefile_dlbasename=$sharedlib_from_linklib_result + fi + fi + $opt_dry_run || { + if test -n "$dlprefile_dlbasename" ; then + eval '$ECHO ": $dlprefile_dlbasename" >> "$nlist"' + else + func_warning "Could not compute DLL name from $name" + eval '$ECHO ": $name " >> "$nlist"' + fi + func_to_tool_file "$dlprefile" func_convert_file_msys_to_w32 + eval "$NM \"$func_to_tool_file_result\" 2>/dev/null | $global_symbol_pipe | + $SED -e '/I __imp/d' -e 's/I __nm_/D /;s/_nm__//' >> '$nlist'" + } + else # not an import lib + $opt_dry_run || { + eval '$ECHO ": $name " >> "$nlist"' + func_to_tool_file "$dlprefile" func_convert_file_msys_to_w32 + eval "$NM \"$func_to_tool_file_result\" 2>/dev/null | $global_symbol_pipe >> '$nlist'" + } + fi + ;; + *) + $opt_dry_run || { + eval '$ECHO ": $name " >> "$nlist"' + func_to_tool_file "$dlprefile" func_convert_file_msys_to_w32 + eval "$NM \"$func_to_tool_file_result\" 2>/dev/null | $global_symbol_pipe >> '$nlist'" + } + ;; + esac + done + + $opt_dry_run || { + # Make sure we have at least an empty file. + test -f "$nlist" || : > "$nlist" + + if test -n "$exclude_expsyms"; then + $EGREP -v " ($exclude_expsyms)$" "$nlist" > "$nlist"T + $MV "$nlist"T "$nlist" + fi + + # Try sorting and uniquifying the output. + if $GREP -v "^: " < "$nlist" | + if sort -k 3 /dev/null 2>&1; then + sort -k 3 + else + sort +2 + fi | + uniq > "$nlist"S; then + : + else + $GREP -v "^: " < "$nlist" > "$nlist"S + fi + + if test -f "$nlist"S; then + eval "$global_symbol_to_cdecl"' < "$nlist"S >> "$output_objdir/$my_dlsyms"' + else + echo '/* NONE */' >> "$output_objdir/$my_dlsyms" + fi + + echo >> "$output_objdir/$my_dlsyms" "\ + +/* The mapping between symbol names and symbols. */ +typedef struct { + const char *name; + void *address; +} lt_dlsymlist; +extern LT_DLSYM_CONST lt_dlsymlist +lt_${my_prefix}_LTX_preloaded_symbols[]; +LT_DLSYM_CONST lt_dlsymlist +lt_${my_prefix}_LTX_preloaded_symbols[] = +{\ + { \"$my_originator\", (void *) 0 }," + + case $need_lib_prefix in + no) + eval "$global_symbol_to_c_name_address" < "$nlist" >> "$output_objdir/$my_dlsyms" + ;; + *) + eval "$global_symbol_to_c_name_address_lib_prefix" < "$nlist" >> "$output_objdir/$my_dlsyms" + ;; + esac + echo >> "$output_objdir/$my_dlsyms" "\ + {0, (void *) 0} +}; + +/* This works around a problem in FreeBSD linker */ +#ifdef FREEBSD_WORKAROUND +static const void *lt_preloaded_setup() { + return lt_${my_prefix}_LTX_preloaded_symbols; +} +#endif + +#ifdef __cplusplus +} +#endif\ +" + } # !$opt_dry_run + + pic_flag_for_symtable= + case "$compile_command " in + *" -static "*) ;; + *) + case $host in + # compiling the symbol table file with pic_flag works around + # a FreeBSD bug that causes programs to crash when -lm is + # linked before any other PIC object. But we must not use + # pic_flag when linking with -static. The problem exists in + # FreeBSD 2.2.6 and is fixed in FreeBSD 3.1. + *-*-freebsd2.*|*-*-freebsd3.0*|*-*-freebsdelf3.0*) + pic_flag_for_symtable=" $pic_flag -DFREEBSD_WORKAROUND" ;; + *-*-hpux*) + pic_flag_for_symtable=" $pic_flag" ;; + *) + if test "X$my_pic_p" != Xno; then + pic_flag_for_symtable=" $pic_flag" + fi + ;; + esac + ;; + esac + symtab_cflags= + for arg in $LTCFLAGS; do + case $arg in + -pie | -fpie | -fPIE) ;; + *) func_append symtab_cflags " $arg" ;; + esac + done + + # Now compile the dynamic symbol file. + func_show_eval '(cd $output_objdir && $LTCC$symtab_cflags -c$no_builtin_flag$pic_flag_for_symtable "$my_dlsyms")' 'exit $?' + + # Clean up the generated files. + func_show_eval '$RM "$output_objdir/$my_dlsyms" "$nlist" "${nlist}S" "${nlist}T"' + + # Transform the symbol file into the correct name. + symfileobj="$output_objdir/${my_outputname}S.$objext" + case $host in + *cygwin* | *mingw* | *cegcc* ) + if test -f "$output_objdir/$my_outputname.def"; then + compile_command=`$ECHO "$compile_command" | $SED "s%@SYMFILE@%$output_objdir/$my_outputname.def $symfileobj%"` + finalize_command=`$ECHO "$finalize_command" | $SED "s%@SYMFILE@%$output_objdir/$my_outputname.def $symfileobj%"` + else + compile_command=`$ECHO "$compile_command" | $SED "s%@SYMFILE@%$symfileobj%"` + finalize_command=`$ECHO "$finalize_command" | $SED "s%@SYMFILE@%$symfileobj%"` + fi + ;; + *) + compile_command=`$ECHO "$compile_command" | $SED "s%@SYMFILE@%$symfileobj%"` + finalize_command=`$ECHO "$finalize_command" | $SED "s%@SYMFILE@%$symfileobj%"` + ;; + esac + ;; + *) + func_fatal_error "unknown suffix for \`$my_dlsyms'" + ;; + esac + else + # We keep going just in case the user didn't refer to + # lt_preloaded_symbols. The linker will fail if global_symbol_pipe + # really was required. + + # Nullify the symbol file. + compile_command=`$ECHO "$compile_command" | $SED "s% @SYMFILE@%%"` + finalize_command=`$ECHO "$finalize_command" | $SED "s% @SYMFILE@%%"` + fi +} + +# func_win32_libid arg +# return the library type of file 'arg' +# +# Need a lot of goo to handle *both* DLLs and import libs +# Has to be a shell function in order to 'eat' the argument +# that is supplied when $file_magic_command is called. +# Despite the name, also deal with 64 bit binaries. +func_win32_libid () +{ + $opt_debug + win32_libid_type="unknown" + win32_fileres=`file -L $1 2>/dev/null` + case $win32_fileres in + *ar\ archive\ import\ library*) # definitely import + win32_libid_type="x86 archive import" + ;; + *ar\ archive*) # could be an import, or static + # Keep the egrep pattern in sync with the one in _LT_CHECK_MAGIC_METHOD. + if eval $OBJDUMP -f $1 | $SED -e '10q' 2>/dev/null | + $EGREP 'file format (pei*-i386(.*architecture: i386)?|pe-arm-wince|pe-x86-64)' >/dev/null; then + func_to_tool_file "$1" func_convert_file_msys_to_w32 + win32_nmres=`eval $NM -f posix -A \"$func_to_tool_file_result\" | + $SED -n -e ' + 1,100{ + / I /{ + s,.*,import, + p + q + } + }'` + case $win32_nmres in + import*) win32_libid_type="x86 archive import";; + *) win32_libid_type="x86 archive static";; + esac + fi + ;; + *DLL*) + win32_libid_type="x86 DLL" + ;; + *executable*) # but shell scripts are "executable" too... + case $win32_fileres in + *MS\ Windows\ PE\ Intel*) + win32_libid_type="x86 DLL" + ;; + esac + ;; + esac + $ECHO "$win32_libid_type" +} + +# func_cygming_dll_for_implib ARG +# +# Platform-specific function to extract the +# name of the DLL associated with the specified +# import library ARG. +# Invoked by eval'ing the libtool variable +# $sharedlib_from_linklib_cmd +# Result is available in the variable +# $sharedlib_from_linklib_result +func_cygming_dll_for_implib () +{ + $opt_debug + sharedlib_from_linklib_result=`$DLLTOOL --identify-strict --identify "$1"` +} + +# func_cygming_dll_for_implib_fallback_core SECTION_NAME LIBNAMEs +# +# The is the core of a fallback implementation of a +# platform-specific function to extract the name of the +# DLL associated with the specified import library LIBNAME. +# +# SECTION_NAME is either .idata$6 or .idata$7, depending +# on the platform and compiler that created the implib. +# +# Echos the name of the DLL associated with the +# specified import library. +func_cygming_dll_for_implib_fallback_core () +{ + $opt_debug + match_literal=`$ECHO "$1" | $SED "$sed_make_literal_regex"` + $OBJDUMP -s --section "$1" "$2" 2>/dev/null | + $SED '/^Contents of section '"$match_literal"':/{ + # Place marker at beginning of archive member dllname section + s/.*/====MARK====/ + p + d + } + # These lines can sometimes be longer than 43 characters, but + # are always uninteresting + /:[ ]*file format pe[i]\{,1\}-/d + /^In archive [^:]*:/d + # Ensure marker is printed + /^====MARK====/p + # Remove all lines with less than 43 characters + /^.\{43\}/!d + # From remaining lines, remove first 43 characters + s/^.\{43\}//' | + $SED -n ' + # Join marker and all lines until next marker into a single line + /^====MARK====/ b para + H + $ b para + b + :para + x + s/\n//g + # Remove the marker + s/^====MARK====// + # Remove trailing dots and whitespace + s/[\. \t]*$// + # Print + /./p' | + # we now have a list, one entry per line, of the stringified + # contents of the appropriate section of all members of the + # archive which possess that section. Heuristic: eliminate + # all those which have a first or second character that is + # a '.' (that is, objdump's representation of an unprintable + # character.) This should work for all archives with less than + # 0x302f exports -- but will fail for DLLs whose name actually + # begins with a literal '.' or a single character followed by + # a '.'. + # + # Of those that remain, print the first one. + $SED -e '/^\./d;/^.\./d;q' +} + +# func_cygming_gnu_implib_p ARG +# This predicate returns with zero status (TRUE) if +# ARG is a GNU/binutils-style import library. Returns +# with nonzero status (FALSE) otherwise. +func_cygming_gnu_implib_p () +{ + $opt_debug + func_to_tool_file "$1" func_convert_file_msys_to_w32 + func_cygming_gnu_implib_tmp=`$NM "$func_to_tool_file_result" | eval "$global_symbol_pipe" | $EGREP ' (_head_[A-Za-z0-9_]+_[ad]l*|[A-Za-z0-9_]+_[ad]l*_iname)$'` + test -n "$func_cygming_gnu_implib_tmp" +} + +# func_cygming_ms_implib_p ARG +# This predicate returns with zero status (TRUE) if +# ARG is an MS-style import library. Returns +# with nonzero status (FALSE) otherwise. +func_cygming_ms_implib_p () +{ + $opt_debug + func_to_tool_file "$1" func_convert_file_msys_to_w32 + func_cygming_ms_implib_tmp=`$NM "$func_to_tool_file_result" | eval "$global_symbol_pipe" | $GREP '_NULL_IMPORT_DESCRIPTOR'` + test -n "$func_cygming_ms_implib_tmp" +} + +# func_cygming_dll_for_implib_fallback ARG +# Platform-specific function to extract the +# name of the DLL associated with the specified +# import library ARG. +# +# This fallback implementation is for use when $DLLTOOL +# does not support the --identify-strict option. +# Invoked by eval'ing the libtool variable +# $sharedlib_from_linklib_cmd +# Result is available in the variable +# $sharedlib_from_linklib_result +func_cygming_dll_for_implib_fallback () +{ + $opt_debug + if func_cygming_gnu_implib_p "$1" ; then + # binutils import library + sharedlib_from_linklib_result=`func_cygming_dll_for_implib_fallback_core '.idata$7' "$1"` + elif func_cygming_ms_implib_p "$1" ; then + # ms-generated import library + sharedlib_from_linklib_result=`func_cygming_dll_for_implib_fallback_core '.idata$6' "$1"` + else + # unknown + sharedlib_from_linklib_result="" + fi +} + + +# func_extract_an_archive dir oldlib +func_extract_an_archive () +{ + $opt_debug + f_ex_an_ar_dir="$1"; shift + f_ex_an_ar_oldlib="$1" + if test "$lock_old_archive_extraction" = yes; then + lockfile=$f_ex_an_ar_oldlib.lock + until $opt_dry_run || ln "$progpath" "$lockfile" 2>/dev/null; do + func_echo "Waiting for $lockfile to be removed" + sleep 2 + done + fi + func_show_eval "(cd \$f_ex_an_ar_dir && $AR x \"\$f_ex_an_ar_oldlib\")" \ + 'stat=$?; rm -f "$lockfile"; exit $stat' + if test "$lock_old_archive_extraction" = yes; then + $opt_dry_run || rm -f "$lockfile" + fi + if ($AR t "$f_ex_an_ar_oldlib" | sort | sort -uc >/dev/null 2>&1); then + : + else + func_fatal_error "object name conflicts in archive: $f_ex_an_ar_dir/$f_ex_an_ar_oldlib" + fi +} + + +# func_extract_archives gentop oldlib ... +func_extract_archives () +{ + $opt_debug + my_gentop="$1"; shift + my_oldlibs=${1+"$@"} + my_oldobjs="" + my_xlib="" + my_xabs="" + my_xdir="" + + for my_xlib in $my_oldlibs; do + # Extract the objects. + case $my_xlib in + [\\/]* | [A-Za-z]:[\\/]*) my_xabs="$my_xlib" ;; + *) my_xabs=`pwd`"/$my_xlib" ;; + esac + func_basename "$my_xlib" + my_xlib="$func_basename_result" + my_xlib_u=$my_xlib + while :; do + case " $extracted_archives " in + *" $my_xlib_u "*) + func_arith $extracted_serial + 1 + extracted_serial=$func_arith_result + my_xlib_u=lt$extracted_serial-$my_xlib ;; + *) break ;; + esac + done + extracted_archives="$extracted_archives $my_xlib_u" + my_xdir="$my_gentop/$my_xlib_u" + + func_mkdir_p "$my_xdir" + + case $host in + *-darwin*) + func_verbose "Extracting $my_xabs" + # Do not bother doing anything if just a dry run + $opt_dry_run || { + darwin_orig_dir=`pwd` + cd $my_xdir || exit $? + darwin_archive=$my_xabs + darwin_curdir=`pwd` + darwin_base_archive=`basename "$darwin_archive"` + darwin_arches=`$LIPO -info "$darwin_archive" 2>/dev/null | $GREP Architectures 2>/dev/null || true` + if test -n "$darwin_arches"; then + darwin_arches=`$ECHO "$darwin_arches" | $SED -e 's/.*are://'` + darwin_arch= + func_verbose "$darwin_base_archive has multiple architectures $darwin_arches" + for darwin_arch in $darwin_arches ; do + func_mkdir_p "unfat-$$/${darwin_base_archive}-${darwin_arch}" + $LIPO -thin $darwin_arch -output "unfat-$$/${darwin_base_archive}-${darwin_arch}/${darwin_base_archive}" "${darwin_archive}" + cd "unfat-$$/${darwin_base_archive}-${darwin_arch}" + func_extract_an_archive "`pwd`" "${darwin_base_archive}" + cd "$darwin_curdir" + $RM "unfat-$$/${darwin_base_archive}-${darwin_arch}/${darwin_base_archive}" + done # $darwin_arches + ## Okay now we've a bunch of thin objects, gotta fatten them up :) + darwin_filelist=`find unfat-$$ -type f -name \*.o -print -o -name \*.lo -print | $SED -e "$basename" | sort -u` + darwin_file= + darwin_files= + for darwin_file in $darwin_filelist; do + darwin_files=`find unfat-$$ -name $darwin_file -print | sort | $NL2SP` + $LIPO -create -output "$darwin_file" $darwin_files + done # $darwin_filelist + $RM -rf unfat-$$ + cd "$darwin_orig_dir" + else + cd $darwin_orig_dir + func_extract_an_archive "$my_xdir" "$my_xabs" + fi # $darwin_arches + } # !$opt_dry_run + ;; + *) + func_extract_an_archive "$my_xdir" "$my_xabs" + ;; + esac + my_oldobjs="$my_oldobjs "`find $my_xdir -name \*.$objext -print -o -name \*.lo -print | sort | $NL2SP` + done + + func_extract_archives_result="$my_oldobjs" +} + + +# func_emit_wrapper [arg=no] +# +# Emit a libtool wrapper script on stdout. +# Don't directly open a file because we may want to +# incorporate the script contents within a cygwin/mingw +# wrapper executable. Must ONLY be called from within +# func_mode_link because it depends on a number of variables +# set therein. +# +# ARG is the value that the WRAPPER_SCRIPT_BELONGS_IN_OBJDIR +# variable will take. If 'yes', then the emitted script +# will assume that the directory in which it is stored is +# the $objdir directory. This is a cygwin/mingw-specific +# behavior. +func_emit_wrapper () +{ + func_emit_wrapper_arg1=${1-no} + + $ECHO "\ +#! $SHELL + +# $output - temporary wrapper script for $objdir/$outputname +# Generated by $PROGRAM (GNU $PACKAGE$TIMESTAMP) $VERSION +# +# The $output program cannot be directly executed until all the libtool +# libraries that it depends on are installed. +# +# This wrapper script should never be moved out of the build directory. +# If it is, it will not operate correctly. + +# Sed substitution that helps us do robust quoting. It backslashifies +# metacharacters that are still active within double-quoted strings. +sed_quote_subst='$sed_quote_subst' + +# Be Bourne compatible +if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then + emulate sh + NULLCMD=: + # Zsh 3.x and 4.x performs word splitting on \${1+\"\$@\"}, which + # is contrary to our usage. Disable this feature. + alias -g '\${1+\"\$@\"}'='\"\$@\"' + setopt NO_GLOB_SUBST +else + case \`(set -o) 2>/dev/null\` in *posix*) set -o posix;; esac +fi +BIN_SH=xpg4; export BIN_SH # for Tru64 +DUALCASE=1; export DUALCASE # for MKS sh + +# The HP-UX ksh and POSIX shell print the target directory to stdout +# if CDPATH is set. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + +relink_command=\"$relink_command\" + +# This environment variable determines our operation mode. +if test \"\$libtool_install_magic\" = \"$magic\"; then + # install mode needs the following variables: + generated_by_libtool_version='$macro_version' + notinst_deplibs='$notinst_deplibs' +else + # When we are sourced in execute mode, \$file and \$ECHO are already set. + if test \"\$libtool_execute_magic\" != \"$magic\"; then + file=\"\$0\"" + + qECHO=`$ECHO "$ECHO" | $SED "$sed_quote_subst"` + $ECHO "\ + +# A function that is used when there is no print builtin or printf. +func_fallback_echo () +{ + eval 'cat <<_LTECHO_EOF +\$1 +_LTECHO_EOF' +} + ECHO=\"$qECHO\" + fi + +# Very basic option parsing. These options are (a) specific to +# the libtool wrapper, (b) are identical between the wrapper +# /script/ and the wrapper /executable/ which is used only on +# windows platforms, and (c) all begin with the string "--lt-" +# (application programs are unlikely to have options which match +# this pattern). +# +# There are only two supported options: --lt-debug and +# --lt-dump-script. There is, deliberately, no --lt-help. +# +# The first argument to this parsing function should be the +# script's $0 value, followed by "$@". +lt_option_debug= +func_parse_lt_options () +{ + lt_script_arg0=\$0 + shift + for lt_opt + do + case \"\$lt_opt\" in + --lt-debug) lt_option_debug=1 ;; + --lt-dump-script) + lt_dump_D=\`\$ECHO \"X\$lt_script_arg0\" | $SED -e 's/^X//' -e 's%/[^/]*$%%'\` + test \"X\$lt_dump_D\" = \"X\$lt_script_arg0\" && lt_dump_D=. + lt_dump_F=\`\$ECHO \"X\$lt_script_arg0\" | $SED -e 's/^X//' -e 's%^.*/%%'\` + cat \"\$lt_dump_D/\$lt_dump_F\" + exit 0 + ;; + --lt-*) + \$ECHO \"Unrecognized --lt- option: '\$lt_opt'\" 1>&2 + exit 1 + ;; + esac + done + + # Print the debug banner immediately: + if test -n \"\$lt_option_debug\"; then + echo \"${outputname}:${output}:\${LINENO}: libtool wrapper (GNU $PACKAGE$TIMESTAMP) $VERSION\" 1>&2 + fi +} + +# Used when --lt-debug. Prints its arguments to stdout +# (redirection is the responsibility of the caller) +func_lt_dump_args () +{ + lt_dump_args_N=1; + for lt_arg + do + \$ECHO \"${outputname}:${output}:\${LINENO}: newargv[\$lt_dump_args_N]: \$lt_arg\" + lt_dump_args_N=\`expr \$lt_dump_args_N + 1\` + done +} + +# Core function for launching the target application +func_exec_program_core () +{ +" + case $host in + # Backslashes separate directories on plain windows + *-*-mingw | *-*-os2* | *-cegcc*) + $ECHO "\ + if test -n \"\$lt_option_debug\"; then + \$ECHO \"${outputname}:${output}:\${LINENO}: newargv[0]: \$progdir\\\\\$program\" 1>&2 + func_lt_dump_args \${1+\"\$@\"} 1>&2 + fi + exec \"\$progdir\\\\\$program\" \${1+\"\$@\"} +" + ;; + + *) + $ECHO "\ + if test -n \"\$lt_option_debug\"; then + \$ECHO \"${outputname}:${output}:\${LINENO}: newargv[0]: \$progdir/\$program\" 1>&2 + func_lt_dump_args \${1+\"\$@\"} 1>&2 + fi + exec \"\$progdir/\$program\" \${1+\"\$@\"} +" + ;; + esac + $ECHO "\ + \$ECHO \"\$0: cannot exec \$program \$*\" 1>&2 + exit 1 +} + +# A function to encapsulate launching the target application +# Strips options in the --lt-* namespace from \$@ and +# launches target application with the remaining arguments. +func_exec_program () +{ + case \" \$* \" in + *\\ --lt-*) + for lt_wr_arg + do + case \$lt_wr_arg in + --lt-*) ;; + *) set x \"\$@\" \"\$lt_wr_arg\"; shift;; + esac + shift + done ;; + esac + func_exec_program_core \${1+\"\$@\"} +} + + # Parse options + func_parse_lt_options \"\$0\" \${1+\"\$@\"} + + # Find the directory that this script lives in. + thisdir=\`\$ECHO \"\$file\" | $SED 's%/[^/]*$%%'\` + test \"x\$thisdir\" = \"x\$file\" && thisdir=. + + # Follow symbolic links until we get to the real thisdir. + file=\`ls -ld \"\$file\" | $SED -n 's/.*-> //p'\` + while test -n \"\$file\"; do + destdir=\`\$ECHO \"\$file\" | $SED 's%/[^/]*\$%%'\` + + # If there was a directory component, then change thisdir. + if test \"x\$destdir\" != \"x\$file\"; then + case \"\$destdir\" in + [\\\\/]* | [A-Za-z]:[\\\\/]*) thisdir=\"\$destdir\" ;; + *) thisdir=\"\$thisdir/\$destdir\" ;; + esac + fi + + file=\`\$ECHO \"\$file\" | $SED 's%^.*/%%'\` + file=\`ls -ld \"\$thisdir/\$file\" | $SED -n 's/.*-> //p'\` + done + + # Usually 'no', except on cygwin/mingw when embedded into + # the cwrapper. + WRAPPER_SCRIPT_BELONGS_IN_OBJDIR=$func_emit_wrapper_arg1 + if test \"\$WRAPPER_SCRIPT_BELONGS_IN_OBJDIR\" = \"yes\"; then + # special case for '.' + if test \"\$thisdir\" = \".\"; then + thisdir=\`pwd\` + fi + # remove .libs from thisdir + case \"\$thisdir\" in + *[\\\\/]$objdir ) thisdir=\`\$ECHO \"\$thisdir\" | $SED 's%[\\\\/][^\\\\/]*$%%'\` ;; + $objdir ) thisdir=. ;; + esac + fi + + # Try to get the absolute directory name. + absdir=\`cd \"\$thisdir\" && pwd\` + test -n \"\$absdir\" && thisdir=\"\$absdir\" +" + + if test "$fast_install" = yes; then + $ECHO "\ + program=lt-'$outputname'$exeext + progdir=\"\$thisdir/$objdir\" + + if test ! -f \"\$progdir/\$program\" || + { file=\`ls -1dt \"\$progdir/\$program\" \"\$progdir/../\$program\" 2>/dev/null | ${SED} 1q\`; \\ + test \"X\$file\" != \"X\$progdir/\$program\"; }; then + + file=\"\$\$-\$program\" + + if test ! -d \"\$progdir\"; then + $MKDIR \"\$progdir\" + else + $RM \"\$progdir/\$file\" + fi" + + $ECHO "\ + + # relink executable if necessary + if test -n \"\$relink_command\"; then + if relink_command_output=\`eval \$relink_command 2>&1\`; then : + else + $ECHO \"\$relink_command_output\" >&2 + $RM \"\$progdir/\$file\" + exit 1 + fi + fi + + $MV \"\$progdir/\$file\" \"\$progdir/\$program\" 2>/dev/null || + { $RM \"\$progdir/\$program\"; + $MV \"\$progdir/\$file\" \"\$progdir/\$program\"; } + $RM \"\$progdir/\$file\" + fi" + else + $ECHO "\ + program='$outputname' + progdir=\"\$thisdir/$objdir\" +" + fi + + $ECHO "\ + + if test -f \"\$progdir/\$program\"; then" + + # fixup the dll searchpath if we need to. + # + # Fix the DLL searchpath if we need to. Do this before prepending + # to shlibpath, because on Windows, both are PATH and uninstalled + # libraries must come first. + if test -n "$dllsearchpath"; then + $ECHO "\ + # Add the dll search path components to the executable PATH + PATH=$dllsearchpath:\$PATH +" + fi + + # Export our shlibpath_var if we have one. + if test "$shlibpath_overrides_runpath" = yes && test -n "$shlibpath_var" && test -n "$temp_rpath"; then + $ECHO "\ + # Add our own library path to $shlibpath_var + $shlibpath_var=\"$temp_rpath\$$shlibpath_var\" + + # Some systems cannot cope with colon-terminated $shlibpath_var + # The second colon is a workaround for a bug in BeOS R4 sed + $shlibpath_var=\`\$ECHO \"\$$shlibpath_var\" | $SED 's/::*\$//'\` + + export $shlibpath_var +" + fi + + $ECHO "\ + if test \"\$libtool_execute_magic\" != \"$magic\"; then + # Run the actual program with our arguments. + func_exec_program \${1+\"\$@\"} + fi + else + # The program doesn't exist. + \$ECHO \"\$0: error: \\\`\$progdir/\$program' does not exist\" 1>&2 + \$ECHO \"This script is just a wrapper for \$program.\" 1>&2 + \$ECHO \"See the $PACKAGE documentation for more information.\" 1>&2 + exit 1 + fi +fi\ +" +} + + +# func_emit_cwrapperexe_src +# emit the source code for a wrapper executable on stdout +# Must ONLY be called from within func_mode_link because +# it depends on a number of variable set therein. +func_emit_cwrapperexe_src () +{ + cat < +#include +#ifdef _MSC_VER +# include +# include +# include +#else +# include +# include +# ifdef __CYGWIN__ +# include +# endif +#endif +#include +#include +#include +#include +#include +#include +#include +#include + +/* declarations of non-ANSI functions */ +#if defined(__MINGW32__) +# ifdef __STRICT_ANSI__ +int _putenv (const char *); +# endif +#elif defined(__CYGWIN__) +# ifdef __STRICT_ANSI__ +char *realpath (const char *, char *); +int putenv (char *); +int setenv (const char *, const char *, int); +# endif +/* #elif defined (other platforms) ... */ +#endif + +/* portability defines, excluding path handling macros */ +#if defined(_MSC_VER) +# define setmode _setmode +# define stat _stat +# define chmod _chmod +# define getcwd _getcwd +# define putenv _putenv +# define S_IXUSR _S_IEXEC +# ifndef _INTPTR_T_DEFINED +# define _INTPTR_T_DEFINED +# define intptr_t int +# endif +#elif defined(__MINGW32__) +# define setmode _setmode +# define stat _stat +# define chmod _chmod +# define getcwd _getcwd +# define putenv _putenv +#elif defined(__CYGWIN__) +# define HAVE_SETENV +# define FOPEN_WB "wb" +/* #elif defined (other platforms) ... */ +#endif + +#if defined(PATH_MAX) +# define LT_PATHMAX PATH_MAX +#elif defined(MAXPATHLEN) +# define LT_PATHMAX MAXPATHLEN +#else +# define LT_PATHMAX 1024 +#endif + +#ifndef S_IXOTH +# define S_IXOTH 0 +#endif +#ifndef S_IXGRP +# define S_IXGRP 0 +#endif + +/* path handling portability macros */ +#ifndef DIR_SEPARATOR +# define DIR_SEPARATOR '/' +# define PATH_SEPARATOR ':' +#endif + +#if defined (_WIN32) || defined (__MSDOS__) || defined (__DJGPP__) || \ + defined (__OS2__) +# define HAVE_DOS_BASED_FILE_SYSTEM +# define FOPEN_WB "wb" +# ifndef DIR_SEPARATOR_2 +# define DIR_SEPARATOR_2 '\\' +# endif +# ifndef PATH_SEPARATOR_2 +# define PATH_SEPARATOR_2 ';' +# endif +#endif + +#ifndef DIR_SEPARATOR_2 +# define IS_DIR_SEPARATOR(ch) ((ch) == DIR_SEPARATOR) +#else /* DIR_SEPARATOR_2 */ +# define IS_DIR_SEPARATOR(ch) \ + (((ch) == DIR_SEPARATOR) || ((ch) == DIR_SEPARATOR_2)) +#endif /* DIR_SEPARATOR_2 */ + +#ifndef PATH_SEPARATOR_2 +# define IS_PATH_SEPARATOR(ch) ((ch) == PATH_SEPARATOR) +#else /* PATH_SEPARATOR_2 */ +# define IS_PATH_SEPARATOR(ch) ((ch) == PATH_SEPARATOR_2) +#endif /* PATH_SEPARATOR_2 */ + +#ifndef FOPEN_WB +# define FOPEN_WB "w" +#endif +#ifndef _O_BINARY +# define _O_BINARY 0 +#endif + +#define XMALLOC(type, num) ((type *) xmalloc ((num) * sizeof(type))) +#define XFREE(stale) do { \ + if (stale) { free ((void *) stale); stale = 0; } \ +} while (0) + +#if defined(LT_DEBUGWRAPPER) +static int lt_debug = 1; +#else +static int lt_debug = 0; +#endif + +const char *program_name = "libtool-wrapper"; /* in case xstrdup fails */ + +void *xmalloc (size_t num); +char *xstrdup (const char *string); +const char *base_name (const char *name); +char *find_executable (const char *wrapper); +char *chase_symlinks (const char *pathspec); +int make_executable (const char *path); +int check_executable (const char *path); +char *strendzap (char *str, const char *pat); +void lt_debugprintf (const char *file, int line, const char *fmt, ...); +void lt_fatal (const char *file, int line, const char *message, ...); +static const char *nonnull (const char *s); +static const char *nonempty (const char *s); +void lt_setenv (const char *name, const char *value); +char *lt_extend_str (const char *orig_value, const char *add, int to_end); +void lt_update_exe_path (const char *name, const char *value); +void lt_update_lib_path (const char *name, const char *value); +char **prepare_spawn (char **argv); +void lt_dump_script (FILE *f); +EOF + + cat <= 0) + && (st.st_mode & (S_IXUSR | S_IXGRP | S_IXOTH))) + return 1; + else + return 0; +} + +int +make_executable (const char *path) +{ + int rval = 0; + struct stat st; + + lt_debugprintf (__FILE__, __LINE__, "(make_executable): %s\n", + nonempty (path)); + if ((!path) || (!*path)) + return 0; + + if (stat (path, &st) >= 0) + { + rval = chmod (path, st.st_mode | S_IXOTH | S_IXGRP | S_IXUSR); + } + return rval; +} + +/* Searches for the full path of the wrapper. Returns + newly allocated full path name if found, NULL otherwise + Does not chase symlinks, even on platforms that support them. +*/ +char * +find_executable (const char *wrapper) +{ + int has_slash = 0; + const char *p; + const char *p_next; + /* static buffer for getcwd */ + char tmp[LT_PATHMAX + 1]; + int tmp_len; + char *concat_name; + + lt_debugprintf (__FILE__, __LINE__, "(find_executable): %s\n", + nonempty (wrapper)); + + if ((wrapper == NULL) || (*wrapper == '\0')) + return NULL; + + /* Absolute path? */ +#if defined (HAVE_DOS_BASED_FILE_SYSTEM) + if (isalpha ((unsigned char) wrapper[0]) && wrapper[1] == ':') + { + concat_name = xstrdup (wrapper); + if (check_executable (concat_name)) + return concat_name; + XFREE (concat_name); + } + else + { +#endif + if (IS_DIR_SEPARATOR (wrapper[0])) + { + concat_name = xstrdup (wrapper); + if (check_executable (concat_name)) + return concat_name; + XFREE (concat_name); + } +#if defined (HAVE_DOS_BASED_FILE_SYSTEM) + } +#endif + + for (p = wrapper; *p; p++) + if (*p == '/') + { + has_slash = 1; + break; + } + if (!has_slash) + { + /* no slashes; search PATH */ + const char *path = getenv ("PATH"); + if (path != NULL) + { + for (p = path; *p; p = p_next) + { + const char *q; + size_t p_len; + for (q = p; *q; q++) + if (IS_PATH_SEPARATOR (*q)) + break; + p_len = q - p; + p_next = (*q == '\0' ? q : q + 1); + if (p_len == 0) + { + /* empty path: current directory */ + if (getcwd (tmp, LT_PATHMAX) == NULL) + lt_fatal (__FILE__, __LINE__, "getcwd failed: %s", + nonnull (strerror (errno))); + tmp_len = strlen (tmp); + concat_name = + XMALLOC (char, tmp_len + 1 + strlen (wrapper) + 1); + memcpy (concat_name, tmp, tmp_len); + concat_name[tmp_len] = '/'; + strcpy (concat_name + tmp_len + 1, wrapper); + } + else + { + concat_name = + XMALLOC (char, p_len + 1 + strlen (wrapper) + 1); + memcpy (concat_name, p, p_len); + concat_name[p_len] = '/'; + strcpy (concat_name + p_len + 1, wrapper); + } + if (check_executable (concat_name)) + return concat_name; + XFREE (concat_name); + } + } + /* not found in PATH; assume curdir */ + } + /* Relative path | not found in path: prepend cwd */ + if (getcwd (tmp, LT_PATHMAX) == NULL) + lt_fatal (__FILE__, __LINE__, "getcwd failed: %s", + nonnull (strerror (errno))); + tmp_len = strlen (tmp); + concat_name = XMALLOC (char, tmp_len + 1 + strlen (wrapper) + 1); + memcpy (concat_name, tmp, tmp_len); + concat_name[tmp_len] = '/'; + strcpy (concat_name + tmp_len + 1, wrapper); + + if (check_executable (concat_name)) + return concat_name; + XFREE (concat_name); + return NULL; +} + +char * +chase_symlinks (const char *pathspec) +{ +#ifndef S_ISLNK + return xstrdup (pathspec); +#else + char buf[LT_PATHMAX]; + struct stat s; + char *tmp_pathspec = xstrdup (pathspec); + char *p; + int has_symlinks = 0; + while (strlen (tmp_pathspec) && !has_symlinks) + { + lt_debugprintf (__FILE__, __LINE__, + "checking path component for symlinks: %s\n", + tmp_pathspec); + if (lstat (tmp_pathspec, &s) == 0) + { + if (S_ISLNK (s.st_mode) != 0) + { + has_symlinks = 1; + break; + } + + /* search backwards for last DIR_SEPARATOR */ + p = tmp_pathspec + strlen (tmp_pathspec) - 1; + while ((p > tmp_pathspec) && (!IS_DIR_SEPARATOR (*p))) + p--; + if ((p == tmp_pathspec) && (!IS_DIR_SEPARATOR (*p))) + { + /* no more DIR_SEPARATORS left */ + break; + } + *p = '\0'; + } + else + { + lt_fatal (__FILE__, __LINE__, + "error accessing file \"%s\": %s", + tmp_pathspec, nonnull (strerror (errno))); + } + } + XFREE (tmp_pathspec); + + if (!has_symlinks) + { + return xstrdup (pathspec); + } + + tmp_pathspec = realpath (pathspec, buf); + if (tmp_pathspec == 0) + { + lt_fatal (__FILE__, __LINE__, + "could not follow symlinks for %s", pathspec); + } + return xstrdup (tmp_pathspec); +#endif +} + +char * +strendzap (char *str, const char *pat) +{ + size_t len, patlen; + + assert (str != NULL); + assert (pat != NULL); + + len = strlen (str); + patlen = strlen (pat); + + if (patlen <= len) + { + str += len - patlen; + if (strcmp (str, pat) == 0) + *str = '\0'; + } + return str; +} + +void +lt_debugprintf (const char *file, int line, const char *fmt, ...) +{ + va_list args; + if (lt_debug) + { + (void) fprintf (stderr, "%s:%s:%d: ", program_name, file, line); + va_start (args, fmt); + (void) vfprintf (stderr, fmt, args); + va_end (args); + } +} + +static void +lt_error_core (int exit_status, const char *file, + int line, const char *mode, + const char *message, va_list ap) +{ + fprintf (stderr, "%s:%s:%d: %s: ", program_name, file, line, mode); + vfprintf (stderr, message, ap); + fprintf (stderr, ".\n"); + + if (exit_status >= 0) + exit (exit_status); +} + +void +lt_fatal (const char *file, int line, const char *message, ...) +{ + va_list ap; + va_start (ap, message); + lt_error_core (EXIT_FAILURE, file, line, "FATAL", message, ap); + va_end (ap); +} + +static const char * +nonnull (const char *s) +{ + return s ? s : "(null)"; +} + +static const char * +nonempty (const char *s) +{ + return (s && !*s) ? "(empty)" : nonnull (s); +} + +void +lt_setenv (const char *name, const char *value) +{ + lt_debugprintf (__FILE__, __LINE__, + "(lt_setenv) setting '%s' to '%s'\n", + nonnull (name), nonnull (value)); + { +#ifdef HAVE_SETENV + /* always make a copy, for consistency with !HAVE_SETENV */ + char *str = xstrdup (value); + setenv (name, str, 1); +#else + int len = strlen (name) + 1 + strlen (value) + 1; + char *str = XMALLOC (char, len); + sprintf (str, "%s=%s", name, value); + if (putenv (str) != EXIT_SUCCESS) + { + XFREE (str); + } +#endif + } +} + +char * +lt_extend_str (const char *orig_value, const char *add, int to_end) +{ + char *new_value; + if (orig_value && *orig_value) + { + int orig_value_len = strlen (orig_value); + int add_len = strlen (add); + new_value = XMALLOC (char, add_len + orig_value_len + 1); + if (to_end) + { + strcpy (new_value, orig_value); + strcpy (new_value + orig_value_len, add); + } + else + { + strcpy (new_value, add); + strcpy (new_value + add_len, orig_value); + } + } + else + { + new_value = xstrdup (add); + } + return new_value; +} + +void +lt_update_exe_path (const char *name, const char *value) +{ + lt_debugprintf (__FILE__, __LINE__, + "(lt_update_exe_path) modifying '%s' by prepending '%s'\n", + nonnull (name), nonnull (value)); + + if (name && *name && value && *value) + { + char *new_value = lt_extend_str (getenv (name), value, 0); + /* some systems can't cope with a ':'-terminated path #' */ + int len = strlen (new_value); + while (((len = strlen (new_value)) > 0) && IS_PATH_SEPARATOR (new_value[len-1])) + { + new_value[len-1] = '\0'; + } + lt_setenv (name, new_value); + XFREE (new_value); + } +} + +void +lt_update_lib_path (const char *name, const char *value) +{ + lt_debugprintf (__FILE__, __LINE__, + "(lt_update_lib_path) modifying '%s' by prepending '%s'\n", + nonnull (name), nonnull (value)); + + if (name && *name && value && *value) + { + char *new_value = lt_extend_str (getenv (name), value, 0); + lt_setenv (name, new_value); + XFREE (new_value); + } +} + +EOF + case $host_os in + mingw*) + cat <<"EOF" + +/* Prepares an argument vector before calling spawn(). + Note that spawn() does not by itself call the command interpreter + (getenv ("COMSPEC") != NULL ? getenv ("COMSPEC") : + ({ OSVERSIONINFO v; v.dwOSVersionInfoSize = sizeof(OSVERSIONINFO); + GetVersionEx(&v); + v.dwPlatformId == VER_PLATFORM_WIN32_NT; + }) ? "cmd.exe" : "command.com"). + Instead it simply concatenates the arguments, separated by ' ', and calls + CreateProcess(). We must quote the arguments since Win32 CreateProcess() + interprets characters like ' ', '\t', '\\', '"' (but not '<' and '>') in a + special way: + - Space and tab are interpreted as delimiters. They are not treated as + delimiters if they are surrounded by double quotes: "...". + - Unescaped double quotes are removed from the input. Their only effect is + that within double quotes, space and tab are treated like normal + characters. + - Backslashes not followed by double quotes are not special. + - But 2*n+1 backslashes followed by a double quote become + n backslashes followed by a double quote (n >= 0): + \" -> " + \\\" -> \" + \\\\\" -> \\" + */ +#define SHELL_SPECIAL_CHARS "\"\\ \001\002\003\004\005\006\007\010\011\012\013\014\015\016\017\020\021\022\023\024\025\026\027\030\031\032\033\034\035\036\037" +#define SHELL_SPACE_CHARS " \001\002\003\004\005\006\007\010\011\012\013\014\015\016\017\020\021\022\023\024\025\026\027\030\031\032\033\034\035\036\037" +char ** +prepare_spawn (char **argv) +{ + size_t argc; + char **new_argv; + size_t i; + + /* Count number of arguments. */ + for (argc = 0; argv[argc] != NULL; argc++) + ; + + /* Allocate new argument vector. */ + new_argv = XMALLOC (char *, argc + 1); + + /* Put quoted arguments into the new argument vector. */ + for (i = 0; i < argc; i++) + { + const char *string = argv[i]; + + if (string[0] == '\0') + new_argv[i] = xstrdup ("\"\""); + else if (strpbrk (string, SHELL_SPECIAL_CHARS) != NULL) + { + int quote_around = (strpbrk (string, SHELL_SPACE_CHARS) != NULL); + size_t length; + unsigned int backslashes; + const char *s; + char *quoted_string; + char *p; + + length = 0; + backslashes = 0; + if (quote_around) + length++; + for (s = string; *s != '\0'; s++) + { + char c = *s; + if (c == '"') + length += backslashes + 1; + length++; + if (c == '\\') + backslashes++; + else + backslashes = 0; + } + if (quote_around) + length += backslashes + 1; + + quoted_string = XMALLOC (char, length + 1); + + p = quoted_string; + backslashes = 0; + if (quote_around) + *p++ = '"'; + for (s = string; *s != '\0'; s++) + { + char c = *s; + if (c == '"') + { + unsigned int j; + for (j = backslashes + 1; j > 0; j--) + *p++ = '\\'; + } + *p++ = c; + if (c == '\\') + backslashes++; + else + backslashes = 0; + } + if (quote_around) + { + unsigned int j; + for (j = backslashes; j > 0; j--) + *p++ = '\\'; + *p++ = '"'; + } + *p = '\0'; + + new_argv[i] = quoted_string; + } + else + new_argv[i] = (char *) string; + } + new_argv[argc] = NULL; + + return new_argv; +} +EOF + ;; + esac + + cat <<"EOF" +void lt_dump_script (FILE* f) +{ +EOF + func_emit_wrapper yes | + $SED -n -e ' +s/^\(.\{79\}\)\(..*\)/\1\ +\2/ +h +s/\([\\"]\)/\\\1/g +s/$/\\n/ +s/\([^\n]*\).*/ fputs ("\1", f);/p +g +D' + cat <<"EOF" +} +EOF +} +# end: func_emit_cwrapperexe_src + +# func_win32_import_lib_p ARG +# True if ARG is an import lib, as indicated by $file_magic_cmd +func_win32_import_lib_p () +{ + $opt_debug + case `eval $file_magic_cmd \"\$1\" 2>/dev/null | $SED -e 10q` in + *import*) : ;; + *) false ;; + esac +} + +# func_mode_link arg... +func_mode_link () +{ + $opt_debug + case $host in + *-*-cygwin* | *-*-mingw* | *-*-pw32* | *-*-os2* | *-cegcc*) + # It is impossible to link a dll without this setting, and + # we shouldn't force the makefile maintainer to figure out + # which system we are compiling for in order to pass an extra + # flag for every libtool invocation. + # allow_undefined=no + + # FIXME: Unfortunately, there are problems with the above when trying + # to make a dll which has undefined symbols, in which case not + # even a static library is built. For now, we need to specify + # -no-undefined on the libtool link line when we can be certain + # that all symbols are satisfied, otherwise we get a static library. + allow_undefined=yes + ;; + *) + allow_undefined=yes + ;; + esac + libtool_args=$nonopt + base_compile="$nonopt $@" + compile_command=$nonopt + finalize_command=$nonopt + + compile_rpath= + finalize_rpath= + compile_shlibpath= + finalize_shlibpath= + convenience= + old_convenience= + deplibs= + old_deplibs= + compiler_flags= + linker_flags= + dllsearchpath= + lib_search_path=`pwd` + inst_prefix_dir= + new_inherited_linker_flags= + + avoid_version=no + bindir= + dlfiles= + dlprefiles= + dlself=no + export_dynamic=no + export_symbols= + export_symbols_regex= + generated= + libobjs= + ltlibs= + module=no + no_install=no + objs= + non_pic_objects= + precious_files_regex= + prefer_static_libs=no + preload=no + prev= + prevarg= + release= + rpath= + xrpath= + perm_rpath= + temp_rpath= + thread_safe=no + vinfo= + vinfo_number=no + weak_libs= + single_module="${wl}-single_module" + func_infer_tag $base_compile + + # We need to know -static, to get the right output filenames. + for arg + do + case $arg in + -shared) + test "$build_libtool_libs" != yes && \ + func_fatal_configuration "can not build a shared library" + build_old_libs=no + break + ;; + -all-static | -static | -static-libtool-libs) + case $arg in + -all-static) + if test "$build_libtool_libs" = yes && test -z "$link_static_flag"; then + func_warning "complete static linking is impossible in this configuration" + fi + if test -n "$link_static_flag"; then + dlopen_self=$dlopen_self_static + fi + prefer_static_libs=yes + ;; + -static) + if test -z "$pic_flag" && test -n "$link_static_flag"; then + dlopen_self=$dlopen_self_static + fi + prefer_static_libs=built + ;; + -static-libtool-libs) + if test -z "$pic_flag" && test -n "$link_static_flag"; then + dlopen_self=$dlopen_self_static + fi + prefer_static_libs=yes + ;; + esac + build_libtool_libs=no + build_old_libs=yes + break + ;; + esac + done + + # See if our shared archives depend on static archives. + test -n "$old_archive_from_new_cmds" && build_old_libs=yes + + # Go through the arguments, transforming them on the way. + while test "$#" -gt 0; do + arg="$1" + shift + func_quote_for_eval "$arg" + qarg=$func_quote_for_eval_unquoted_result + func_append libtool_args " $func_quote_for_eval_result" + + # If the previous option needs an argument, assign it. + if test -n "$prev"; then + case $prev in + output) + func_append compile_command " @OUTPUT@" + func_append finalize_command " @OUTPUT@" + ;; + esac + + case $prev in + bindir) + bindir="$arg" + prev= + continue + ;; + dlfiles|dlprefiles) + if test "$preload" = no; then + # Add the symbol object into the linking commands. + func_append compile_command " @SYMFILE@" + func_append finalize_command " @SYMFILE@" + preload=yes + fi + case $arg in + *.la | *.lo) ;; # We handle these cases below. + force) + if test "$dlself" = no; then + dlself=needless + export_dynamic=yes + fi + prev= + continue + ;; + self) + if test "$prev" = dlprefiles; then + dlself=yes + elif test "$prev" = dlfiles && test "$dlopen_self" != yes; then + dlself=yes + else + dlself=needless + export_dynamic=yes + fi + prev= + continue + ;; + *) + if test "$prev" = dlfiles; then + func_append dlfiles " $arg" + else + func_append dlprefiles " $arg" + fi + prev= + continue + ;; + esac + ;; + expsyms) + export_symbols="$arg" + test -f "$arg" \ + || func_fatal_error "symbol file \`$arg' does not exist" + prev= + continue + ;; + expsyms_regex) + export_symbols_regex="$arg" + prev= + continue + ;; + framework) + case $host in + *-*-darwin*) + case "$deplibs " in + *" $qarg.ltframework "*) ;; + *) func_append deplibs " $qarg.ltframework" # this is fixed later + ;; + esac + ;; + esac + prev= + continue + ;; + inst_prefix) + inst_prefix_dir="$arg" + prev= + continue + ;; + objectlist) + if test -f "$arg"; then + save_arg=$arg + moreargs= + for fil in `cat "$save_arg"` + do +# func_append moreargs " $fil" + arg=$fil + # A libtool-controlled object. + + # Check to see that this really is a libtool object. + if func_lalib_unsafe_p "$arg"; then + pic_object= + non_pic_object= + + # Read the .lo file + func_source "$arg" + + if test -z "$pic_object" || + test -z "$non_pic_object" || + test "$pic_object" = none && + test "$non_pic_object" = none; then + func_fatal_error "cannot find name of object for \`$arg'" + fi + + # Extract subdirectory from the argument. + func_dirname "$arg" "/" "" + xdir="$func_dirname_result" + + if test "$pic_object" != none; then + # Prepend the subdirectory the object is found in. + pic_object="$xdir$pic_object" + + if test "$prev" = dlfiles; then + if test "$build_libtool_libs" = yes && test "$dlopen_support" = yes; then + func_append dlfiles " $pic_object" + prev= + continue + else + # If libtool objects are unsupported, then we need to preload. + prev=dlprefiles + fi + fi + + # CHECK ME: I think I busted this. -Ossama + if test "$prev" = dlprefiles; then + # Preload the old-style object. + func_append dlprefiles " $pic_object" + prev= + fi + + # A PIC object. + func_append libobjs " $pic_object" + arg="$pic_object" + fi + + # Non-PIC object. + if test "$non_pic_object" != none; then + # Prepend the subdirectory the object is found in. + non_pic_object="$xdir$non_pic_object" + + # A standard non-PIC object + func_append non_pic_objects " $non_pic_object" + if test -z "$pic_object" || test "$pic_object" = none ; then + arg="$non_pic_object" + fi + else + # If the PIC object exists, use it instead. + # $xdir was prepended to $pic_object above. + non_pic_object="$pic_object" + func_append non_pic_objects " $non_pic_object" + fi + else + # Only an error if not doing a dry-run. + if $opt_dry_run; then + # Extract subdirectory from the argument. + func_dirname "$arg" "/" "" + xdir="$func_dirname_result" + + func_lo2o "$arg" + pic_object=$xdir$objdir/$func_lo2o_result + non_pic_object=$xdir$func_lo2o_result + func_append libobjs " $pic_object" + func_append non_pic_objects " $non_pic_object" + else + func_fatal_error "\`$arg' is not a valid libtool object" + fi + fi + done + else + func_fatal_error "link input file \`$arg' does not exist" + fi + arg=$save_arg + prev= + continue + ;; + precious_regex) + precious_files_regex="$arg" + prev= + continue + ;; + release) + release="-$arg" + prev= + continue + ;; + rpath | xrpath) + # We need an absolute path. + case $arg in + [\\/]* | [A-Za-z]:[\\/]*) ;; + *) + func_fatal_error "only absolute run-paths are allowed" + ;; + esac + if test "$prev" = rpath; then + case "$rpath " in + *" $arg "*) ;; + *) func_append rpath " $arg" ;; + esac + else + case "$xrpath " in + *" $arg "*) ;; + *) func_append xrpath " $arg" ;; + esac + fi + prev= + continue + ;; + shrext) + shrext_cmds="$arg" + prev= + continue + ;; + weak) + func_append weak_libs " $arg" + prev= + continue + ;; + xcclinker) + func_append linker_flags " $qarg" + func_append compiler_flags " $qarg" + prev= + func_append compile_command " $qarg" + func_append finalize_command " $qarg" + continue + ;; + xcompiler) + func_append compiler_flags " $qarg" + prev= + func_append compile_command " $qarg" + func_append finalize_command " $qarg" + continue + ;; + xlinker) + func_append linker_flags " $qarg" + func_append compiler_flags " $wl$qarg" + prev= + func_append compile_command " $wl$qarg" + func_append finalize_command " $wl$qarg" + continue + ;; + *) + eval "$prev=\"\$arg\"" + prev= + continue + ;; + esac + fi # test -n "$prev" + + prevarg="$arg" + + case $arg in + -all-static) + if test -n "$link_static_flag"; then + # See comment for -static flag below, for more details. + func_append compile_command " $link_static_flag" + func_append finalize_command " $link_static_flag" + fi + continue + ;; + + -allow-undefined) + # FIXME: remove this flag sometime in the future. + func_fatal_error "\`-allow-undefined' must not be used because it is the default" + ;; + + -avoid-version) + avoid_version=yes + continue + ;; + + -bindir) + prev=bindir + continue + ;; + + -dlopen) + prev=dlfiles + continue + ;; + + -dlpreopen) + prev=dlprefiles + continue + ;; + + -export-dynamic) + export_dynamic=yes + continue + ;; + + -export-symbols | -export-symbols-regex) + if test -n "$export_symbols" || test -n "$export_symbols_regex"; then + func_fatal_error "more than one -exported-symbols argument is not allowed" + fi + if test "X$arg" = "X-export-symbols"; then + prev=expsyms + else + prev=expsyms_regex + fi + continue + ;; + + -framework) + prev=framework + continue + ;; + + -inst-prefix-dir) + prev=inst_prefix + continue + ;; + + # The native IRIX linker understands -LANG:*, -LIST:* and -LNO:* + # so, if we see these flags be careful not to treat them like -L + -L[A-Z][A-Z]*:*) + case $with_gcc/$host in + no/*-*-irix* | /*-*-irix*) + func_append compile_command " $arg" + func_append finalize_command " $arg" + ;; + esac + continue + ;; + + -L*) + func_stripname "-L" '' "$arg" + if test -z "$func_stripname_result"; then + if test "$#" -gt 0; then + func_fatal_error "require no space between \`-L' and \`$1'" + else + func_fatal_error "need path for \`-L' option" + fi + fi + func_resolve_sysroot "$func_stripname_result" + dir=$func_resolve_sysroot_result + # We need an absolute path. + case $dir in + [\\/]* | [A-Za-z]:[\\/]*) ;; + *) + absdir=`cd "$dir" && pwd` + test -z "$absdir" && \ + func_fatal_error "cannot determine absolute directory name of \`$dir'" + dir="$absdir" + ;; + esac + case "$deplibs " in + *" -L$dir "* | *" $arg "*) + # Will only happen for absolute or sysroot arguments + ;; + *) + # Preserve sysroot, but never include relative directories + case $dir in + [\\/]* | [A-Za-z]:[\\/]* | =*) func_append deplibs " $arg" ;; + *) func_append deplibs " -L$dir" ;; + esac + func_append lib_search_path " $dir" + ;; + esac + case $host in + *-*-cygwin* | *-*-mingw* | *-*-pw32* | *-*-os2* | *-cegcc*) + testbindir=`$ECHO "$dir" | $SED 's*/lib$*/bin*'` + case :$dllsearchpath: in + *":$dir:"*) ;; + ::) dllsearchpath=$dir;; + *) func_append dllsearchpath ":$dir";; + esac + case :$dllsearchpath: in + *":$testbindir:"*) ;; + ::) dllsearchpath=$testbindir;; + *) func_append dllsearchpath ":$testbindir";; + esac + ;; + esac + continue + ;; + + -l*) + if test "X$arg" = "X-lc" || test "X$arg" = "X-lm"; then + case $host in + *-*-cygwin* | *-*-mingw* | *-*-pw32* | *-*-beos* | *-cegcc* | *-*-haiku*) + # These systems don't actually have a C or math library (as such) + continue + ;; + *-*-os2*) + # These systems don't actually have a C library (as such) + test "X$arg" = "X-lc" && continue + ;; + *-*-openbsd* | *-*-freebsd* | *-*-dragonfly*) + # Do not include libc due to us having libc/libc_r. + test "X$arg" = "X-lc" && continue + ;; + *-*-rhapsody* | *-*-darwin1.[012]) + # Rhapsody C and math libraries are in the System framework + func_append deplibs " System.ltframework" + continue + ;; + *-*-sco3.2v5* | *-*-sco5v6*) + # Causes problems with __ctype + test "X$arg" = "X-lc" && continue + ;; + *-*-sysv4.2uw2* | *-*-sysv5* | *-*-unixware* | *-*-OpenUNIX*) + # Compiler inserts libc in the correct place for threads to work + test "X$arg" = "X-lc" && continue + ;; + esac + elif test "X$arg" = "X-lc_r"; then + case $host in + *-*-openbsd* | *-*-freebsd* | *-*-dragonfly*) + # Do not include libc_r directly, use -pthread flag. + continue + ;; + esac + fi + func_append deplibs " $arg" + continue + ;; + + -module) + module=yes + continue + ;; + + # Tru64 UNIX uses -model [arg] to determine the layout of C++ + # classes, name mangling, and exception handling. + # Darwin uses the -arch flag to determine output architecture. + -model|-arch|-isysroot|--sysroot) + func_append compiler_flags " $arg" + func_append compile_command " $arg" + func_append finalize_command " $arg" + prev=xcompiler + continue + ;; + + -mt|-mthreads|-kthread|-Kthread|-pthread|-pthreads|--thread-safe \ + |-threads|-fopenmp|-openmp|-mp|-xopenmp|-omp|-qsmp=*) + func_append compiler_flags " $arg" + func_append compile_command " $arg" + func_append finalize_command " $arg" + case "$new_inherited_linker_flags " in + *" $arg "*) ;; + * ) func_append new_inherited_linker_flags " $arg" ;; + esac + continue + ;; + + -multi_module) + single_module="${wl}-multi_module" + continue + ;; + + -no-fast-install) + fast_install=no + continue + ;; + + -no-install) + case $host in + *-*-cygwin* | *-*-mingw* | *-*-pw32* | *-*-os2* | *-*-darwin* | *-cegcc*) + # The PATH hackery in wrapper scripts is required on Windows + # and Darwin in order for the loader to find any dlls it needs. + func_warning "\`-no-install' is ignored for $host" + func_warning "assuming \`-no-fast-install' instead" + fast_install=no + ;; + *) no_install=yes ;; + esac + continue + ;; + + -no-undefined) + allow_undefined=no + continue + ;; + + -objectlist) + prev=objectlist + continue + ;; + + -o) prev=output ;; + + -precious-files-regex) + prev=precious_regex + continue + ;; + + -release) + prev=release + continue + ;; + + -rpath) + prev=rpath + continue + ;; + + -R) + prev=xrpath + continue + ;; + + -R*) + func_stripname '-R' '' "$arg" + dir=$func_stripname_result + # We need an absolute path. + case $dir in + [\\/]* | [A-Za-z]:[\\/]*) ;; + =*) + func_stripname '=' '' "$dir" + dir=$lt_sysroot$func_stripname_result + ;; + *) + func_fatal_error "only absolute run-paths are allowed" + ;; + esac + case "$xrpath " in + *" $dir "*) ;; + *) func_append xrpath " $dir" ;; + esac + continue + ;; + + -shared) + # The effects of -shared are defined in a previous loop. + continue + ;; + + -shrext) + prev=shrext + continue + ;; + + -static | -static-libtool-libs) + # The effects of -static are defined in a previous loop. + # We used to do the same as -all-static on platforms that + # didn't have a PIC flag, but the assumption that the effects + # would be equivalent was wrong. It would break on at least + # Digital Unix and AIX. + continue + ;; + + -thread-safe) + thread_safe=yes + continue + ;; + + -version-info) + prev=vinfo + continue + ;; + + -version-number) + prev=vinfo + vinfo_number=yes + continue + ;; + + -weak) + prev=weak + continue + ;; + + -Wc,*) + func_stripname '-Wc,' '' "$arg" + args=$func_stripname_result + arg= + save_ifs="$IFS"; IFS=',' + for flag in $args; do + IFS="$save_ifs" + func_quote_for_eval "$flag" + func_append arg " $func_quote_for_eval_result" + func_append compiler_flags " $func_quote_for_eval_result" + done + IFS="$save_ifs" + func_stripname ' ' '' "$arg" + arg=$func_stripname_result + ;; + + -Wl,*) + func_stripname '-Wl,' '' "$arg" + args=$func_stripname_result + arg= + save_ifs="$IFS"; IFS=',' + for flag in $args; do + IFS="$save_ifs" + func_quote_for_eval "$flag" + func_append arg " $wl$func_quote_for_eval_result" + func_append compiler_flags " $wl$func_quote_for_eval_result" + func_append linker_flags " $func_quote_for_eval_result" + done + IFS="$save_ifs" + func_stripname ' ' '' "$arg" + arg=$func_stripname_result + ;; + + -Xcompiler) + prev=xcompiler + continue + ;; + + -Xlinker) + prev=xlinker + continue + ;; + + -XCClinker) + prev=xcclinker + continue + ;; + + # -msg_* for osf cc + -msg_*) + func_quote_for_eval "$arg" + arg="$func_quote_for_eval_result" + ;; + + # Flags to be passed through unchanged, with rationale: + # -64, -mips[0-9] enable 64-bit mode for the SGI compiler + # -r[0-9][0-9]* specify processor for the SGI compiler + # -xarch=*, -xtarget=* enable 64-bit mode for the Sun compiler + # +DA*, +DD* enable 64-bit mode for the HP compiler + # -q* compiler args for the IBM compiler + # -m*, -t[45]*, -txscale* architecture-specific flags for GCC + # -F/path path to uninstalled frameworks, gcc on darwin + # -p, -pg, --coverage, -fprofile-* profiling flags for GCC + # @file GCC response files + # -tp=* Portland pgcc target processor selection + # --sysroot=* for sysroot support + # -O*, -flto*, -fwhopr*, -fuse-linker-plugin GCC link-time optimization + # -stdlib=* select c++ std lib with clang + -64|-mips[0-9]|-r[0-9][0-9]*|-xarch=*|-xtarget=*|+DA*|+DD*|-q*|-m*| \ + -t[45]*|-txscale*|-p|-pg|--coverage|-fprofile-*|-F*|@*|-tp=*|--sysroot=*| \ + -O*|-flto*|-fwhopr*|-fuse-linker-plugin|-stdlib=*) + func_quote_for_eval "$arg" + arg="$func_quote_for_eval_result" + func_append compile_command " $arg" + func_append finalize_command " $arg" + func_append compiler_flags " $arg" + continue + ;; + + # Some other compiler flag. + -* | +*) + func_quote_for_eval "$arg" + arg="$func_quote_for_eval_result" + ;; + + *.$objext) + # A standard object. + func_append objs " $arg" + ;; + + *.lo) + # A libtool-controlled object. + + # Check to see that this really is a libtool object. + if func_lalib_unsafe_p "$arg"; then + pic_object= + non_pic_object= + + # Read the .lo file + func_source "$arg" + + if test -z "$pic_object" || + test -z "$non_pic_object" || + test "$pic_object" = none && + test "$non_pic_object" = none; then + func_fatal_error "cannot find name of object for \`$arg'" + fi + + # Extract subdirectory from the argument. + func_dirname "$arg" "/" "" + xdir="$func_dirname_result" + + if test "$pic_object" != none; then + # Prepend the subdirectory the object is found in. + pic_object="$xdir$pic_object" + + if test "$prev" = dlfiles; then + if test "$build_libtool_libs" = yes && test "$dlopen_support" = yes; then + func_append dlfiles " $pic_object" + prev= + continue + else + # If libtool objects are unsupported, then we need to preload. + prev=dlprefiles + fi + fi + + # CHECK ME: I think I busted this. -Ossama + if test "$prev" = dlprefiles; then + # Preload the old-style object. + func_append dlprefiles " $pic_object" + prev= + fi + + # A PIC object. + func_append libobjs " $pic_object" + arg="$pic_object" + fi + + # Non-PIC object. + if test "$non_pic_object" != none; then + # Prepend the subdirectory the object is found in. + non_pic_object="$xdir$non_pic_object" + + # A standard non-PIC object + func_append non_pic_objects " $non_pic_object" + if test -z "$pic_object" || test "$pic_object" = none ; then + arg="$non_pic_object" + fi + else + # If the PIC object exists, use it instead. + # $xdir was prepended to $pic_object above. + non_pic_object="$pic_object" + func_append non_pic_objects " $non_pic_object" + fi + else + # Only an error if not doing a dry-run. + if $opt_dry_run; then + # Extract subdirectory from the argument. + func_dirname "$arg" "/" "" + xdir="$func_dirname_result" + + func_lo2o "$arg" + pic_object=$xdir$objdir/$func_lo2o_result + non_pic_object=$xdir$func_lo2o_result + func_append libobjs " $pic_object" + func_append non_pic_objects " $non_pic_object" + else + func_fatal_error "\`$arg' is not a valid libtool object" + fi + fi + ;; + + *.$libext) + # An archive. + func_append deplibs " $arg" + func_append old_deplibs " $arg" + continue + ;; + + *.la) + # A libtool-controlled library. + + func_resolve_sysroot "$arg" + if test "$prev" = dlfiles; then + # This library was specified with -dlopen. + func_append dlfiles " $func_resolve_sysroot_result" + prev= + elif test "$prev" = dlprefiles; then + # The library was specified with -dlpreopen. + func_append dlprefiles " $func_resolve_sysroot_result" + prev= + else + func_append deplibs " $func_resolve_sysroot_result" + fi + continue + ;; + + # Some other compiler argument. + *) + # Unknown arguments in both finalize_command and compile_command need + # to be aesthetically quoted because they are evaled later. + func_quote_for_eval "$arg" + arg="$func_quote_for_eval_result" + ;; + esac # arg + + # Now actually substitute the argument into the commands. + if test -n "$arg"; then + func_append compile_command " $arg" + func_append finalize_command " $arg" + fi + done # argument parsing loop + + test -n "$prev" && \ + func_fatal_help "the \`$prevarg' option requires an argument" + + if test "$export_dynamic" = yes && test -n "$export_dynamic_flag_spec"; then + eval arg=\"$export_dynamic_flag_spec\" + func_append compile_command " $arg" + func_append finalize_command " $arg" + fi + + oldlibs= + # calculate the name of the file, without its directory + func_basename "$output" + outputname="$func_basename_result" + libobjs_save="$libobjs" + + if test -n "$shlibpath_var"; then + # get the directories listed in $shlibpath_var + eval shlib_search_path=\`\$ECHO \"\${$shlibpath_var}\" \| \$SED \'s/:/ /g\'\` + else + shlib_search_path= + fi + eval sys_lib_search_path=\"$sys_lib_search_path_spec\" + eval sys_lib_dlsearch_path=\"$sys_lib_dlsearch_path_spec\" + + func_dirname "$output" "/" "" + output_objdir="$func_dirname_result$objdir" + func_to_tool_file "$output_objdir/" + tool_output_objdir=$func_to_tool_file_result + # Create the object directory. + func_mkdir_p "$output_objdir" + + # Determine the type of output + case $output in + "") + func_fatal_help "you must specify an output file" + ;; + *.$libext) linkmode=oldlib ;; + *.lo | *.$objext) linkmode=obj ;; + *.la) linkmode=lib ;; + *) linkmode=prog ;; # Anything else should be a program. + esac + + specialdeplibs= + + libs= + # Find all interdependent deplibs by searching for libraries + # that are linked more than once (e.g. -la -lb -la) + for deplib in $deplibs; do + if $opt_preserve_dup_deps ; then + case "$libs " in + *" $deplib "*) func_append specialdeplibs " $deplib" ;; + esac + fi + func_append libs " $deplib" + done + + if test "$linkmode" = lib; then + libs="$predeps $libs $compiler_lib_search_path $postdeps" + + # Compute libraries that are listed more than once in $predeps + # $postdeps and mark them as special (i.e., whose duplicates are + # not to be eliminated). + pre_post_deps= + if $opt_duplicate_compiler_generated_deps; then + for pre_post_dep in $predeps $postdeps; do + case "$pre_post_deps " in + *" $pre_post_dep "*) func_append specialdeplibs " $pre_post_deps" ;; + esac + func_append pre_post_deps " $pre_post_dep" + done + fi + pre_post_deps= + fi + + deplibs= + newdependency_libs= + newlib_search_path= + need_relink=no # whether we're linking any uninstalled libtool libraries + notinst_deplibs= # not-installed libtool libraries + notinst_path= # paths that contain not-installed libtool libraries + + case $linkmode in + lib) + passes="conv dlpreopen link" + for file in $dlfiles $dlprefiles; do + case $file in + *.la) ;; + *) + func_fatal_help "libraries can \`-dlopen' only libtool libraries: $file" + ;; + esac + done + ;; + prog) + compile_deplibs= + finalize_deplibs= + alldeplibs=no + newdlfiles= + newdlprefiles= + passes="conv scan dlopen dlpreopen link" + ;; + *) passes="conv" + ;; + esac + + for pass in $passes; do + # The preopen pass in lib mode reverses $deplibs; put it back here + # so that -L comes before libs that need it for instance... + if test "$linkmode,$pass" = "lib,link"; then + ## FIXME: Find the place where the list is rebuilt in the wrong + ## order, and fix it there properly + tmp_deplibs= + for deplib in $deplibs; do + tmp_deplibs="$deplib $tmp_deplibs" + done + deplibs="$tmp_deplibs" + fi + + if test "$linkmode,$pass" = "lib,link" || + test "$linkmode,$pass" = "prog,scan"; then + libs="$deplibs" + deplibs= + fi + if test "$linkmode" = prog; then + case $pass in + dlopen) libs="$dlfiles" ;; + dlpreopen) libs="$dlprefiles" ;; + link) libs="$deplibs %DEPLIBS% $dependency_libs" ;; + esac + fi + if test "$linkmode,$pass" = "lib,dlpreopen"; then + # Collect and forward deplibs of preopened libtool libs + for lib in $dlprefiles; do + # Ignore non-libtool-libs + dependency_libs= + func_resolve_sysroot "$lib" + case $lib in + *.la) func_source "$func_resolve_sysroot_result" ;; + esac + + # Collect preopened libtool deplibs, except any this library + # has declared as weak libs + for deplib in $dependency_libs; do + func_basename "$deplib" + deplib_base=$func_basename_result + case " $weak_libs " in + *" $deplib_base "*) ;; + *) func_append deplibs " $deplib" ;; + esac + done + done + libs="$dlprefiles" + fi + if test "$pass" = dlopen; then + # Collect dlpreopened libraries + save_deplibs="$deplibs" + deplibs= + fi + + for deplib in $libs; do + lib= + found=no + case $deplib in + -mt|-mthreads|-kthread|-Kthread|-pthread|-pthreads|--thread-safe \ + |-threads|-fopenmp|-openmp|-mp|-xopenmp|-omp|-qsmp=*) + if test "$linkmode,$pass" = "prog,link"; then + compile_deplibs="$deplib $compile_deplibs" + finalize_deplibs="$deplib $finalize_deplibs" + else + func_append compiler_flags " $deplib" + if test "$linkmode" = lib ; then + case "$new_inherited_linker_flags " in + *" $deplib "*) ;; + * ) func_append new_inherited_linker_flags " $deplib" ;; + esac + fi + fi + continue + ;; + -l*) + if test "$linkmode" != lib && test "$linkmode" != prog; then + func_warning "\`-l' is ignored for archives/objects" + continue + fi + func_stripname '-l' '' "$deplib" + name=$func_stripname_result + if test "$linkmode" = lib; then + searchdirs="$newlib_search_path $lib_search_path $compiler_lib_search_dirs $sys_lib_search_path $shlib_search_path" + else + searchdirs="$newlib_search_path $lib_search_path $sys_lib_search_path $shlib_search_path" + fi + for searchdir in $searchdirs; do + for search_ext in .la $std_shrext .so .a; do + # Search the libtool library + lib="$searchdir/lib${name}${search_ext}" + if test -f "$lib"; then + if test "$search_ext" = ".la"; then + found=yes + else + found=no + fi + break 2 + fi + done + done + if test "$found" != yes; then + # deplib doesn't seem to be a libtool library + if test "$linkmode,$pass" = "prog,link"; then + compile_deplibs="$deplib $compile_deplibs" + finalize_deplibs="$deplib $finalize_deplibs" + else + deplibs="$deplib $deplibs" + test "$linkmode" = lib && newdependency_libs="$deplib $newdependency_libs" + fi + continue + else # deplib is a libtool library + # If $allow_libtool_libs_with_static_runtimes && $deplib is a stdlib, + # We need to do some special things here, and not later. + if test "X$allow_libtool_libs_with_static_runtimes" = "Xyes" ; then + case " $predeps $postdeps " in + *" $deplib "*) + if func_lalib_p "$lib"; then + library_names= + old_library= + func_source "$lib" + for l in $old_library $library_names; do + ll="$l" + done + if test "X$ll" = "X$old_library" ; then # only static version available + found=no + func_dirname "$lib" "" "." + ladir="$func_dirname_result" + lib=$ladir/$old_library + if test "$linkmode,$pass" = "prog,link"; then + compile_deplibs="$deplib $compile_deplibs" + finalize_deplibs="$deplib $finalize_deplibs" + else + deplibs="$deplib $deplibs" + test "$linkmode" = lib && newdependency_libs="$deplib $newdependency_libs" + fi + continue + fi + fi + ;; + *) ;; + esac + fi + fi + ;; # -l + *.ltframework) + if test "$linkmode,$pass" = "prog,link"; then + compile_deplibs="$deplib $compile_deplibs" + finalize_deplibs="$deplib $finalize_deplibs" + else + deplibs="$deplib $deplibs" + if test "$linkmode" = lib ; then + case "$new_inherited_linker_flags " in + *" $deplib "*) ;; + * ) func_append new_inherited_linker_flags " $deplib" ;; + esac + fi + fi + continue + ;; + -L*) + case $linkmode in + lib) + deplibs="$deplib $deplibs" + test "$pass" = conv && continue + newdependency_libs="$deplib $newdependency_libs" + func_stripname '-L' '' "$deplib" + func_resolve_sysroot "$func_stripname_result" + func_append newlib_search_path " $func_resolve_sysroot_result" + ;; + prog) + if test "$pass" = conv; then + deplibs="$deplib $deplibs" + continue + fi + if test "$pass" = scan; then + deplibs="$deplib $deplibs" + else + compile_deplibs="$deplib $compile_deplibs" + finalize_deplibs="$deplib $finalize_deplibs" + fi + func_stripname '-L' '' "$deplib" + func_resolve_sysroot "$func_stripname_result" + func_append newlib_search_path " $func_resolve_sysroot_result" + ;; + *) + func_warning "\`-L' is ignored for archives/objects" + ;; + esac # linkmode + continue + ;; # -L + -R*) + if test "$pass" = link; then + func_stripname '-R' '' "$deplib" + func_resolve_sysroot "$func_stripname_result" + dir=$func_resolve_sysroot_result + # Make sure the xrpath contains only unique directories. + case "$xrpath " in + *" $dir "*) ;; + *) func_append xrpath " $dir" ;; + esac + fi + deplibs="$deplib $deplibs" + continue + ;; + *.la) + func_resolve_sysroot "$deplib" + lib=$func_resolve_sysroot_result + ;; + *.$libext) + if test "$pass" = conv; then + deplibs="$deplib $deplibs" + continue + fi + case $linkmode in + lib) + # Linking convenience modules into shared libraries is allowed, + # but linking other static libraries is non-portable. + case " $dlpreconveniencelibs " in + *" $deplib "*) ;; + *) + valid_a_lib=no + case $deplibs_check_method in + match_pattern*) + set dummy $deplibs_check_method; shift + match_pattern_regex=`expr "$deplibs_check_method" : "$1 \(.*\)"` + if eval "\$ECHO \"$deplib\"" 2>/dev/null | $SED 10q \ + | $EGREP "$match_pattern_regex" > /dev/null; then + valid_a_lib=yes + fi + ;; + pass_all) + valid_a_lib=yes + ;; + esac + if test "$valid_a_lib" != yes; then + echo + $ECHO "*** Warning: Trying to link with static lib archive $deplib." + echo "*** I have the capability to make that library automatically link in when" + echo "*** you link to this library. But I can only do this if you have a" + echo "*** shared version of the library, which you do not appear to have" + echo "*** because the file extensions .$libext of this argument makes me believe" + echo "*** that it is just a static archive that I should not use here." + else + echo + $ECHO "*** Warning: Linking the shared library $output against the" + $ECHO "*** static library $deplib is not portable!" + deplibs="$deplib $deplibs" + fi + ;; + esac + continue + ;; + prog) + if test "$pass" != link; then + deplibs="$deplib $deplibs" + else + compile_deplibs="$deplib $compile_deplibs" + finalize_deplibs="$deplib $finalize_deplibs" + fi + continue + ;; + esac # linkmode + ;; # *.$libext + *.lo | *.$objext) + if test "$pass" = conv; then + deplibs="$deplib $deplibs" + elif test "$linkmode" = prog; then + if test "$pass" = dlpreopen || test "$dlopen_support" != yes || test "$build_libtool_libs" = no; then + # If there is no dlopen support or we're linking statically, + # we need to preload. + func_append newdlprefiles " $deplib" + compile_deplibs="$deplib $compile_deplibs" + finalize_deplibs="$deplib $finalize_deplibs" + else + func_append newdlfiles " $deplib" + fi + fi + continue + ;; + %DEPLIBS%) + alldeplibs=yes + continue + ;; + esac # case $deplib + + if test "$found" = yes || test -f "$lib"; then : + else + func_fatal_error "cannot find the library \`$lib' or unhandled argument \`$deplib'" + fi + + # Check to see that this really is a libtool archive. + func_lalib_unsafe_p "$lib" \ + || func_fatal_error "\`$lib' is not a valid libtool archive" + + func_dirname "$lib" "" "." + ladir="$func_dirname_result" + + dlname= + dlopen= + dlpreopen= + libdir= + library_names= + old_library= + inherited_linker_flags= + # If the library was installed with an old release of libtool, + # it will not redefine variables installed, or shouldnotlink + installed=yes + shouldnotlink=no + avoidtemprpath= + + + # Read the .la file + func_source "$lib" + + # Convert "-framework foo" to "foo.ltframework" + if test -n "$inherited_linker_flags"; then + tmp_inherited_linker_flags=`$ECHO "$inherited_linker_flags" | $SED 's/-framework \([^ $]*\)/\1.ltframework/g'` + for tmp_inherited_linker_flag in $tmp_inherited_linker_flags; do + case " $new_inherited_linker_flags " in + *" $tmp_inherited_linker_flag "*) ;; + *) func_append new_inherited_linker_flags " $tmp_inherited_linker_flag";; + esac + done + fi + dependency_libs=`$ECHO " $dependency_libs" | $SED 's% \([^ $]*\).ltframework% -framework \1%g'` + if test "$linkmode,$pass" = "lib,link" || + test "$linkmode,$pass" = "prog,scan" || + { test "$linkmode" != prog && test "$linkmode" != lib; }; then + test -n "$dlopen" && func_append dlfiles " $dlopen" + test -n "$dlpreopen" && func_append dlprefiles " $dlpreopen" + fi + + if test "$pass" = conv; then + # Only check for convenience libraries + deplibs="$lib $deplibs" + if test -z "$libdir"; then + if test -z "$old_library"; then + func_fatal_error "cannot find name of link library for \`$lib'" + fi + # It is a libtool convenience library, so add in its objects. + func_append convenience " $ladir/$objdir/$old_library" + func_append old_convenience " $ladir/$objdir/$old_library" + elif test "$linkmode" != prog && test "$linkmode" != lib; then + func_fatal_error "\`$lib' is not a convenience library" + fi + tmp_libs= + for deplib in $dependency_libs; do + deplibs="$deplib $deplibs" + if $opt_preserve_dup_deps ; then + case "$tmp_libs " in + *" $deplib "*) func_append specialdeplibs " $deplib" ;; + esac + fi + func_append tmp_libs " $deplib" + done + continue + fi # $pass = conv + + + # Get the name of the library we link against. + linklib= + if test -n "$old_library" && + { test "$prefer_static_libs" = yes || + test "$prefer_static_libs,$installed" = "built,no"; }; then + linklib=$old_library + else + for l in $old_library $library_names; do + linklib="$l" + done + fi + if test -z "$linklib"; then + func_fatal_error "cannot find name of link library for \`$lib'" + fi + + # This library was specified with -dlopen. + if test "$pass" = dlopen; then + if test -z "$libdir"; then + func_fatal_error "cannot -dlopen a convenience library: \`$lib'" + fi + if test -z "$dlname" || + test "$dlopen_support" != yes || + test "$build_libtool_libs" = no; then + # If there is no dlname, no dlopen support or we're linking + # statically, we need to preload. We also need to preload any + # dependent libraries so libltdl's deplib preloader doesn't + # bomb out in the load deplibs phase. + func_append dlprefiles " $lib $dependency_libs" + else + func_append newdlfiles " $lib" + fi + continue + fi # $pass = dlopen + + # We need an absolute path. + case $ladir in + [\\/]* | [A-Za-z]:[\\/]*) abs_ladir="$ladir" ;; + *) + abs_ladir=`cd "$ladir" && pwd` + if test -z "$abs_ladir"; then + func_warning "cannot determine absolute directory name of \`$ladir'" + func_warning "passing it literally to the linker, although it might fail" + abs_ladir="$ladir" + fi + ;; + esac + func_basename "$lib" + laname="$func_basename_result" + + # Find the relevant object directory and library name. + if test "X$installed" = Xyes; then + if test ! -f "$lt_sysroot$libdir/$linklib" && test -f "$abs_ladir/$linklib"; then + func_warning "library \`$lib' was moved." + dir="$ladir" + absdir="$abs_ladir" + libdir="$abs_ladir" + else + dir="$lt_sysroot$libdir" + absdir="$lt_sysroot$libdir" + fi + test "X$hardcode_automatic" = Xyes && avoidtemprpath=yes + else + if test ! -f "$ladir/$objdir/$linklib" && test -f "$abs_ladir/$linklib"; then + dir="$ladir" + absdir="$abs_ladir" + # Remove this search path later + func_append notinst_path " $abs_ladir" + else + dir="$ladir/$objdir" + absdir="$abs_ladir/$objdir" + # Remove this search path later + func_append notinst_path " $abs_ladir" + fi + fi # $installed = yes + func_stripname 'lib' '.la' "$laname" + name=$func_stripname_result + + # This library was specified with -dlpreopen. + if test "$pass" = dlpreopen; then + if test -z "$libdir" && test "$linkmode" = prog; then + func_fatal_error "only libraries may -dlpreopen a convenience library: \`$lib'" + fi + case "$host" in + # special handling for platforms with PE-DLLs. + *cygwin* | *mingw* | *cegcc* ) + # Linker will automatically link against shared library if both + # static and shared are present. Therefore, ensure we extract + # symbols from the import library if a shared library is present + # (otherwise, the dlopen module name will be incorrect). We do + # this by putting the import library name into $newdlprefiles. + # We recover the dlopen module name by 'saving' the la file + # name in a special purpose variable, and (later) extracting the + # dlname from the la file. + if test -n "$dlname"; then + func_tr_sh "$dir/$linklib" + eval "libfile_$func_tr_sh_result=\$abs_ladir/\$laname" + func_append newdlprefiles " $dir/$linklib" + else + func_append newdlprefiles " $dir/$old_library" + # Keep a list of preopened convenience libraries to check + # that they are being used correctly in the link pass. + test -z "$libdir" && \ + func_append dlpreconveniencelibs " $dir/$old_library" + fi + ;; + * ) + # Prefer using a static library (so that no silly _DYNAMIC symbols + # are required to link). + if test -n "$old_library"; then + func_append newdlprefiles " $dir/$old_library" + # Keep a list of preopened convenience libraries to check + # that they are being used correctly in the link pass. + test -z "$libdir" && \ + func_append dlpreconveniencelibs " $dir/$old_library" + # Otherwise, use the dlname, so that lt_dlopen finds it. + elif test -n "$dlname"; then + func_append newdlprefiles " $dir/$dlname" + else + func_append newdlprefiles " $dir/$linklib" + fi + ;; + esac + fi # $pass = dlpreopen + + if test -z "$libdir"; then + # Link the convenience library + if test "$linkmode" = lib; then + deplibs="$dir/$old_library $deplibs" + elif test "$linkmode,$pass" = "prog,link"; then + compile_deplibs="$dir/$old_library $compile_deplibs" + finalize_deplibs="$dir/$old_library $finalize_deplibs" + else + deplibs="$lib $deplibs" # used for prog,scan pass + fi + continue + fi + + + if test "$linkmode" = prog && test "$pass" != link; then + func_append newlib_search_path " $ladir" + deplibs="$lib $deplibs" + + linkalldeplibs=no + if test "$link_all_deplibs" != no || test -z "$library_names" || + test "$build_libtool_libs" = no; then + linkalldeplibs=yes + fi + + tmp_libs= + for deplib in $dependency_libs; do + case $deplib in + -L*) func_stripname '-L' '' "$deplib" + func_resolve_sysroot "$func_stripname_result" + func_append newlib_search_path " $func_resolve_sysroot_result" + ;; + esac + # Need to link against all dependency_libs? + if test "$linkalldeplibs" = yes; then + deplibs="$deplib $deplibs" + else + # Need to hardcode shared library paths + # or/and link against static libraries + newdependency_libs="$deplib $newdependency_libs" + fi + if $opt_preserve_dup_deps ; then + case "$tmp_libs " in + *" $deplib "*) func_append specialdeplibs " $deplib" ;; + esac + fi + func_append tmp_libs " $deplib" + done # for deplib + continue + fi # $linkmode = prog... + + if test "$linkmode,$pass" = "prog,link"; then + if test -n "$library_names" && + { { test "$prefer_static_libs" = no || + test "$prefer_static_libs,$installed" = "built,yes"; } || + test -z "$old_library"; }; then + # We need to hardcode the library path + if test -n "$shlibpath_var" && test -z "$avoidtemprpath" ; then + # Make sure the rpath contains only unique directories. + case "$temp_rpath:" in + *"$absdir:"*) ;; + *) func_append temp_rpath "$absdir:" ;; + esac + fi + + # Hardcode the library path. + # Skip directories that are in the system default run-time + # search path. + case " $sys_lib_dlsearch_path " in + *" $absdir "*) ;; + *) + case "$compile_rpath " in + *" $absdir "*) ;; + *) func_append compile_rpath " $absdir" ;; + esac + ;; + esac + case " $sys_lib_dlsearch_path " in + *" $libdir "*) ;; + *) + case "$finalize_rpath " in + *" $libdir "*) ;; + *) func_append finalize_rpath " $libdir" ;; + esac + ;; + esac + fi # $linkmode,$pass = prog,link... + + if test "$alldeplibs" = yes && + { test "$deplibs_check_method" = pass_all || + { test "$build_libtool_libs" = yes && + test -n "$library_names"; }; }; then + # We only need to search for static libraries + continue + fi + fi + + link_static=no # Whether the deplib will be linked statically + use_static_libs=$prefer_static_libs + if test "$use_static_libs" = built && test "$installed" = yes; then + use_static_libs=no + fi + if test -n "$library_names" && + { test "$use_static_libs" = no || test -z "$old_library"; }; then + case $host in + *cygwin* | *mingw* | *cegcc*) + # No point in relinking DLLs because paths are not encoded + func_append notinst_deplibs " $lib" + need_relink=no + ;; + *) + if test "$installed" = no; then + func_append notinst_deplibs " $lib" + need_relink=yes + fi + ;; + esac + # This is a shared library + + # Warn about portability, can't link against -module's on some + # systems (darwin). Don't bleat about dlopened modules though! + dlopenmodule="" + for dlpremoduletest in $dlprefiles; do + if test "X$dlpremoduletest" = "X$lib"; then + dlopenmodule="$dlpremoduletest" + break + fi + done + if test -z "$dlopenmodule" && test "$shouldnotlink" = yes && test "$pass" = link; then + echo + if test "$linkmode" = prog; then + $ECHO "*** Warning: Linking the executable $output against the loadable module" + else + $ECHO "*** Warning: Linking the shared library $output against the loadable module" + fi + $ECHO "*** $linklib is not portable!" + fi + if test "$linkmode" = lib && + test "$hardcode_into_libs" = yes; then + # Hardcode the library path. + # Skip directories that are in the system default run-time + # search path. + case " $sys_lib_dlsearch_path " in + *" $absdir "*) ;; + *) + case "$compile_rpath " in + *" $absdir "*) ;; + *) func_append compile_rpath " $absdir" ;; + esac + ;; + esac + case " $sys_lib_dlsearch_path " in + *" $libdir "*) ;; + *) + case "$finalize_rpath " in + *" $libdir "*) ;; + *) func_append finalize_rpath " $libdir" ;; + esac + ;; + esac + fi + + if test -n "$old_archive_from_expsyms_cmds"; then + # figure out the soname + set dummy $library_names + shift + realname="$1" + shift + libname=`eval "\\$ECHO \"$libname_spec\""` + # use dlname if we got it. it's perfectly good, no? + if test -n "$dlname"; then + soname="$dlname" + elif test -n "$soname_spec"; then + # bleh windows + case $host in + *cygwin* | mingw* | *cegcc*) + func_arith $current - $age + major=$func_arith_result + versuffix="-$major" + ;; + esac + eval soname=\"$soname_spec\" + else + soname="$realname" + fi + + # Make a new name for the extract_expsyms_cmds to use + soroot="$soname" + func_basename "$soroot" + soname="$func_basename_result" + func_stripname 'lib' '.dll' "$soname" + newlib=libimp-$func_stripname_result.a + + # If the library has no export list, then create one now + if test -f "$output_objdir/$soname-def"; then : + else + func_verbose "extracting exported symbol list from \`$soname'" + func_execute_cmds "$extract_expsyms_cmds" 'exit $?' + fi + + # Create $newlib + if test -f "$output_objdir/$newlib"; then :; else + func_verbose "generating import library for \`$soname'" + func_execute_cmds "$old_archive_from_expsyms_cmds" 'exit $?' + fi + # make sure the library variables are pointing to the new library + dir=$output_objdir + linklib=$newlib + fi # test -n "$old_archive_from_expsyms_cmds" + + if test "$linkmode" = prog || test "$opt_mode" != relink; then + add_shlibpath= + add_dir= + add= + lib_linked=yes + case $hardcode_action in + immediate | unsupported) + if test "$hardcode_direct" = no; then + add="$dir/$linklib" + case $host in + *-*-sco3.2v5.0.[024]*) add_dir="-L$dir" ;; + *-*-sysv4*uw2*) add_dir="-L$dir" ;; + *-*-sysv5OpenUNIX* | *-*-sysv5UnixWare7.[01].[10]* | \ + *-*-unixware7*) add_dir="-L$dir" ;; + *-*-darwin* ) + # if the lib is a (non-dlopened) module then we can not + # link against it, someone is ignoring the earlier warnings + if /usr/bin/file -L $add 2> /dev/null | + $GREP ": [^:]* bundle" >/dev/null ; then + if test "X$dlopenmodule" != "X$lib"; then + $ECHO "*** Warning: lib $linklib is a module, not a shared library" + if test -z "$old_library" ; then + echo + echo "*** And there doesn't seem to be a static archive available" + echo "*** The link will probably fail, sorry" + else + add="$dir/$old_library" + fi + elif test -n "$old_library"; then + add="$dir/$old_library" + fi + fi + esac + elif test "$hardcode_minus_L" = no; then + case $host in + *-*-sunos*) add_shlibpath="$dir" ;; + esac + add_dir="-L$dir" + add="-l$name" + elif test "$hardcode_shlibpath_var" = no; then + add_shlibpath="$dir" + add="-l$name" + else + lib_linked=no + fi + ;; + relink) + if test "$hardcode_direct" = yes && + test "$hardcode_direct_absolute" = no; then + add="$dir/$linklib" + elif test "$hardcode_minus_L" = yes; then + add_dir="-L$absdir" + # Try looking first in the location we're being installed to. + if test -n "$inst_prefix_dir"; then + case $libdir in + [\\/]*) + func_append add_dir " -L$inst_prefix_dir$libdir" + ;; + esac + fi + add="-l$name" + elif test "$hardcode_shlibpath_var" = yes; then + add_shlibpath="$dir" + add="-l$name" + else + lib_linked=no + fi + ;; + *) lib_linked=no ;; + esac + + if test "$lib_linked" != yes; then + func_fatal_configuration "unsupported hardcode properties" + fi + + if test -n "$add_shlibpath"; then + case :$compile_shlibpath: in + *":$add_shlibpath:"*) ;; + *) func_append compile_shlibpath "$add_shlibpath:" ;; + esac + fi + if test "$linkmode" = prog; then + test -n "$add_dir" && compile_deplibs="$add_dir $compile_deplibs" + test -n "$add" && compile_deplibs="$add $compile_deplibs" + else + test -n "$add_dir" && deplibs="$add_dir $deplibs" + test -n "$add" && deplibs="$add $deplibs" + if test "$hardcode_direct" != yes && + test "$hardcode_minus_L" != yes && + test "$hardcode_shlibpath_var" = yes; then + case :$finalize_shlibpath: in + *":$libdir:"*) ;; + *) func_append finalize_shlibpath "$libdir:" ;; + esac + fi + fi + fi + + if test "$linkmode" = prog || test "$opt_mode" = relink; then + add_shlibpath= + add_dir= + add= + # Finalize command for both is simple: just hardcode it. + if test "$hardcode_direct" = yes && + test "$hardcode_direct_absolute" = no; then + add="$libdir/$linklib" + elif test "$hardcode_minus_L" = yes; then + add_dir="-L$libdir" + add="-l$name" + elif test "$hardcode_shlibpath_var" = yes; then + case :$finalize_shlibpath: in + *":$libdir:"*) ;; + *) func_append finalize_shlibpath "$libdir:" ;; + esac + add="-l$name" + elif test "$hardcode_automatic" = yes; then + if test -n "$inst_prefix_dir" && + test -f "$inst_prefix_dir$libdir/$linklib" ; then + add="$inst_prefix_dir$libdir/$linklib" + else + add="$libdir/$linklib" + fi + else + # We cannot seem to hardcode it, guess we'll fake it. + add_dir="-L$libdir" + # Try looking first in the location we're being installed to. + if test -n "$inst_prefix_dir"; then + case $libdir in + [\\/]*) + func_append add_dir " -L$inst_prefix_dir$libdir" + ;; + esac + fi + add="-l$name" + fi + + if test "$linkmode" = prog; then + test -n "$add_dir" && finalize_deplibs="$add_dir $finalize_deplibs" + test -n "$add" && finalize_deplibs="$add $finalize_deplibs" + else + test -n "$add_dir" && deplibs="$add_dir $deplibs" + test -n "$add" && deplibs="$add $deplibs" + fi + fi + elif test "$linkmode" = prog; then + # Here we assume that one of hardcode_direct or hardcode_minus_L + # is not unsupported. This is valid on all known static and + # shared platforms. + if test "$hardcode_direct" != unsupported; then + test -n "$old_library" && linklib="$old_library" + compile_deplibs="$dir/$linklib $compile_deplibs" + finalize_deplibs="$dir/$linklib $finalize_deplibs" + else + compile_deplibs="-l$name -L$dir $compile_deplibs" + finalize_deplibs="-l$name -L$dir $finalize_deplibs" + fi + elif test "$build_libtool_libs" = yes; then + # Not a shared library + if test "$deplibs_check_method" != pass_all; then + # We're trying link a shared library against a static one + # but the system doesn't support it. + + # Just print a warning and add the library to dependency_libs so + # that the program can be linked against the static library. + echo + $ECHO "*** Warning: This system can not link to static lib archive $lib." + echo "*** I have the capability to make that library automatically link in when" + echo "*** you link to this library. But I can only do this if you have a" + echo "*** shared version of the library, which you do not appear to have." + if test "$module" = yes; then + echo "*** But as you try to build a module library, libtool will still create " + echo "*** a static module, that should work as long as the dlopening application" + echo "*** is linked with the -dlopen flag to resolve symbols at runtime." + if test -z "$global_symbol_pipe"; then + echo + echo "*** However, this would only work if libtool was able to extract symbol" + echo "*** lists from a program, using \`nm' or equivalent, but libtool could" + echo "*** not find such a program. So, this module is probably useless." + echo "*** \`nm' from GNU binutils and a full rebuild may help." + fi + if test "$build_old_libs" = no; then + build_libtool_libs=module + build_old_libs=yes + else + build_libtool_libs=no + fi + fi + else + deplibs="$dir/$old_library $deplibs" + link_static=yes + fi + fi # link shared/static library? + + if test "$linkmode" = lib; then + if test -n "$dependency_libs" && + { test "$hardcode_into_libs" != yes || + test "$build_old_libs" = yes || + test "$link_static" = yes; }; then + # Extract -R from dependency_libs + temp_deplibs= + for libdir in $dependency_libs; do + case $libdir in + -R*) func_stripname '-R' '' "$libdir" + temp_xrpath=$func_stripname_result + case " $xrpath " in + *" $temp_xrpath "*) ;; + *) func_append xrpath " $temp_xrpath";; + esac;; + *) func_append temp_deplibs " $libdir";; + esac + done + dependency_libs="$temp_deplibs" + fi + + func_append newlib_search_path " $absdir" + # Link against this library + test "$link_static" = no && newdependency_libs="$abs_ladir/$laname $newdependency_libs" + # ... and its dependency_libs + tmp_libs= + for deplib in $dependency_libs; do + newdependency_libs="$deplib $newdependency_libs" + case $deplib in + -L*) func_stripname '-L' '' "$deplib" + func_resolve_sysroot "$func_stripname_result";; + *) func_resolve_sysroot "$deplib" ;; + esac + if $opt_preserve_dup_deps ; then + case "$tmp_libs " in + *" $func_resolve_sysroot_result "*) + func_append specialdeplibs " $func_resolve_sysroot_result" ;; + esac + fi + func_append tmp_libs " $func_resolve_sysroot_result" + done + + if test "$link_all_deplibs" != no; then + # Add the search paths of all dependency libraries + for deplib in $dependency_libs; do + path= + case $deplib in + -L*) path="$deplib" ;; + *.la) + func_resolve_sysroot "$deplib" + deplib=$func_resolve_sysroot_result + func_dirname "$deplib" "" "." + dir=$func_dirname_result + # We need an absolute path. + case $dir in + [\\/]* | [A-Za-z]:[\\/]*) absdir="$dir" ;; + *) + absdir=`cd "$dir" && pwd` + if test -z "$absdir"; then + func_warning "cannot determine absolute directory name of \`$dir'" + absdir="$dir" + fi + ;; + esac + if $GREP "^installed=no" $deplib > /dev/null; then + case $host in + *-*-darwin*) + depdepl= + eval deplibrary_names=`${SED} -n -e 's/^library_names=\(.*\)$/\1/p' $deplib` + if test -n "$deplibrary_names" ; then + for tmp in $deplibrary_names ; do + depdepl=$tmp + done + if test -f "$absdir/$objdir/$depdepl" ; then + depdepl="$absdir/$objdir/$depdepl" + darwin_install_name=`${OTOOL} -L $depdepl | awk '{if (NR == 2) {print $1;exit}}'` + if test -z "$darwin_install_name"; then + darwin_install_name=`${OTOOL64} -L $depdepl | awk '{if (NR == 2) {print $1;exit}}'` + fi + func_append compiler_flags " ${wl}-dylib_file ${wl}${darwin_install_name}:${depdepl}" + func_append linker_flags " -dylib_file ${darwin_install_name}:${depdepl}" + path= + fi + fi + ;; + *) + path="-L$absdir/$objdir" + ;; + esac + else + eval libdir=`${SED} -n -e 's/^libdir=\(.*\)$/\1/p' $deplib` + test -z "$libdir" && \ + func_fatal_error "\`$deplib' is not a valid libtool archive" + test "$absdir" != "$libdir" && \ + func_warning "\`$deplib' seems to be moved" + + path="-L$absdir" + fi + ;; + esac + case " $deplibs " in + *" $path "*) ;; + *) deplibs="$path $deplibs" ;; + esac + done + fi # link_all_deplibs != no + fi # linkmode = lib + done # for deplib in $libs + if test "$pass" = link; then + if test "$linkmode" = "prog"; then + compile_deplibs="$new_inherited_linker_flags $compile_deplibs" + finalize_deplibs="$new_inherited_linker_flags $finalize_deplibs" + else + compiler_flags="$compiler_flags "`$ECHO " $new_inherited_linker_flags" | $SED 's% \([^ $]*\).ltframework% -framework \1%g'` + fi + fi + dependency_libs="$newdependency_libs" + if test "$pass" = dlpreopen; then + # Link the dlpreopened libraries before other libraries + for deplib in $save_deplibs; do + deplibs="$deplib $deplibs" + done + fi + if test "$pass" != dlopen; then + if test "$pass" != conv; then + # Make sure lib_search_path contains only unique directories. + lib_search_path= + for dir in $newlib_search_path; do + case "$lib_search_path " in + *" $dir "*) ;; + *) func_append lib_search_path " $dir" ;; + esac + done + newlib_search_path= + fi + + if test "$linkmode,$pass" != "prog,link"; then + vars="deplibs" + else + vars="compile_deplibs finalize_deplibs" + fi + for var in $vars dependency_libs; do + # Add libraries to $var in reverse order + eval tmp_libs=\"\$$var\" + new_libs= + for deplib in $tmp_libs; do + # FIXME: Pedantically, this is the right thing to do, so + # that some nasty dependency loop isn't accidentally + # broken: + #new_libs="$deplib $new_libs" + # Pragmatically, this seems to cause very few problems in + # practice: + case $deplib in + -L*) new_libs="$deplib $new_libs" ;; + -R*) ;; + *) + # And here is the reason: when a library appears more + # than once as an explicit dependence of a library, or + # is implicitly linked in more than once by the + # compiler, it is considered special, and multiple + # occurrences thereof are not removed. Compare this + # with having the same library being listed as a + # dependency of multiple other libraries: in this case, + # we know (pedantically, we assume) the library does not + # need to be listed more than once, so we keep only the + # last copy. This is not always right, but it is rare + # enough that we require users that really mean to play + # such unportable linking tricks to link the library + # using -Wl,-lname, so that libtool does not consider it + # for duplicate removal. + case " $specialdeplibs " in + *" $deplib "*) new_libs="$deplib $new_libs" ;; + *) + case " $new_libs " in + *" $deplib "*) ;; + *) new_libs="$deplib $new_libs" ;; + esac + ;; + esac + ;; + esac + done + tmp_libs= + for deplib in $new_libs; do + case $deplib in + -L*) + case " $tmp_libs " in + *" $deplib "*) ;; + *) func_append tmp_libs " $deplib" ;; + esac + ;; + *) func_append tmp_libs " $deplib" ;; + esac + done + eval $var=\"$tmp_libs\" + done # for var + fi + # Last step: remove runtime libs from dependency_libs + # (they stay in deplibs) + tmp_libs= + for i in $dependency_libs ; do + case " $predeps $postdeps $compiler_lib_search_path " in + *" $i "*) + i="" + ;; + esac + if test -n "$i" ; then + func_append tmp_libs " $i" + fi + done + dependency_libs=$tmp_libs + done # for pass + if test "$linkmode" = prog; then + dlfiles="$newdlfiles" + fi + if test "$linkmode" = prog || test "$linkmode" = lib; then + dlprefiles="$newdlprefiles" + fi + + case $linkmode in + oldlib) + if test -n "$dlfiles$dlprefiles" || test "$dlself" != no; then + func_warning "\`-dlopen' is ignored for archives" + fi + + case " $deplibs" in + *\ -l* | *\ -L*) + func_warning "\`-l' and \`-L' are ignored for archives" ;; + esac + + test -n "$rpath" && \ + func_warning "\`-rpath' is ignored for archives" + + test -n "$xrpath" && \ + func_warning "\`-R' is ignored for archives" + + test -n "$vinfo" && \ + func_warning "\`-version-info/-version-number' is ignored for archives" + + test -n "$release" && \ + func_warning "\`-release' is ignored for archives" + + test -n "$export_symbols$export_symbols_regex" && \ + func_warning "\`-export-symbols' is ignored for archives" + + # Now set the variables for building old libraries. + build_libtool_libs=no + oldlibs="$output" + func_append objs "$old_deplibs" + ;; + + lib) + # Make sure we only generate libraries of the form `libNAME.la'. + case $outputname in + lib*) + func_stripname 'lib' '.la' "$outputname" + name=$func_stripname_result + eval shared_ext=\"$shrext_cmds\" + eval libname=\"$libname_spec\" + ;; + *) + test "$module" = no && \ + func_fatal_help "libtool library \`$output' must begin with \`lib'" + + if test "$need_lib_prefix" != no; then + # Add the "lib" prefix for modules if required + func_stripname '' '.la' "$outputname" + name=$func_stripname_result + eval shared_ext=\"$shrext_cmds\" + eval libname=\"$libname_spec\" + else + func_stripname '' '.la' "$outputname" + libname=$func_stripname_result + fi + ;; + esac + + if test -n "$objs"; then + if test "$deplibs_check_method" != pass_all; then + func_fatal_error "cannot build libtool library \`$output' from non-libtool objects on this host:$objs" + else + echo + $ECHO "*** Warning: Linking the shared library $output against the non-libtool" + $ECHO "*** objects $objs is not portable!" + func_append libobjs " $objs" + fi + fi + + test "$dlself" != no && \ + func_warning "\`-dlopen self' is ignored for libtool libraries" + + set dummy $rpath + shift + test "$#" -gt 1 && \ + func_warning "ignoring multiple \`-rpath's for a libtool library" + + install_libdir="$1" + + oldlibs= + if test -z "$rpath"; then + if test "$build_libtool_libs" = yes; then + # Building a libtool convenience library. + # Some compilers have problems with a `.al' extension so + # convenience libraries should have the same extension an + # archive normally would. + oldlibs="$output_objdir/$libname.$libext $oldlibs" + build_libtool_libs=convenience + build_old_libs=yes + fi + + test -n "$vinfo" && \ + func_warning "\`-version-info/-version-number' is ignored for convenience libraries" + + test -n "$release" && \ + func_warning "\`-release' is ignored for convenience libraries" + else + + # Parse the version information argument. + save_ifs="$IFS"; IFS=':' + set dummy $vinfo 0 0 0 + shift + IFS="$save_ifs" + + test -n "$7" && \ + func_fatal_help "too many parameters to \`-version-info'" + + # convert absolute version numbers to libtool ages + # this retains compatibility with .la files and attempts + # to make the code below a bit more comprehensible + + case $vinfo_number in + yes) + number_major="$1" + number_minor="$2" + number_revision="$3" + # + # There are really only two kinds -- those that + # use the current revision as the major version + # and those that subtract age and use age as + # a minor version. But, then there is irix + # which has an extra 1 added just for fun + # + case $version_type in + # correct linux to gnu/linux during the next big refactor + darwin|linux|osf|windows|none) + func_arith $number_major + $number_minor + current=$func_arith_result + age="$number_minor" + revision="$number_revision" + ;; + freebsd-aout|freebsd-elf|qnx|sunos) + current="$number_major" + revision="$number_minor" + age="0" + ;; + irix|nonstopux) + func_arith $number_major + $number_minor + current=$func_arith_result + age="$number_minor" + revision="$number_minor" + lt_irix_increment=no + ;; + esac + ;; + no) + current="$1" + revision="$2" + age="$3" + ;; + esac + + # Check that each of the things are valid numbers. + case $current in + 0|[1-9]|[1-9][0-9]|[1-9][0-9][0-9]|[1-9][0-9][0-9][0-9]|[1-9][0-9][0-9][0-9][0-9]) ;; + *) + func_error "CURRENT \`$current' must be a nonnegative integer" + func_fatal_error "\`$vinfo' is not valid version information" + ;; + esac + + case $revision in + 0|[1-9]|[1-9][0-9]|[1-9][0-9][0-9]|[1-9][0-9][0-9][0-9]|[1-9][0-9][0-9][0-9][0-9]) ;; + *) + func_error "REVISION \`$revision' must be a nonnegative integer" + func_fatal_error "\`$vinfo' is not valid version information" + ;; + esac + + case $age in + 0|[1-9]|[1-9][0-9]|[1-9][0-9][0-9]|[1-9][0-9][0-9][0-9]|[1-9][0-9][0-9][0-9][0-9]) ;; + *) + func_error "AGE \`$age' must be a nonnegative integer" + func_fatal_error "\`$vinfo' is not valid version information" + ;; + esac + + if test "$age" -gt "$current"; then + func_error "AGE \`$age' is greater than the current interface number \`$current'" + func_fatal_error "\`$vinfo' is not valid version information" + fi + + # Calculate the version variables. + major= + versuffix= + verstring= + case $version_type in + none) ;; + + darwin) + # Like Linux, but with the current version available in + # verstring for coding it into the library header + func_arith $current - $age + major=.$func_arith_result + versuffix="$major.$age.$revision" + # Darwin ld doesn't like 0 for these options... + func_arith $current + 1 + minor_current=$func_arith_result + xlcverstring="${wl}-compatibility_version ${wl}$minor_current ${wl}-current_version ${wl}$minor_current.$revision" + verstring="-compatibility_version $minor_current -current_version $minor_current.$revision" + ;; + + freebsd-aout) + major=".$current" + versuffix=".$current.$revision"; + ;; + + freebsd-elf) + major=".$current" + versuffix=".$current" + ;; + + irix | nonstopux) + if test "X$lt_irix_increment" = "Xno"; then + func_arith $current - $age + else + func_arith $current - $age + 1 + fi + major=$func_arith_result + + case $version_type in + nonstopux) verstring_prefix=nonstopux ;; + *) verstring_prefix=sgi ;; + esac + verstring="$verstring_prefix$major.$revision" + + # Add in all the interfaces that we are compatible with. + loop=$revision + while test "$loop" -ne 0; do + func_arith $revision - $loop + iface=$func_arith_result + func_arith $loop - 1 + loop=$func_arith_result + verstring="$verstring_prefix$major.$iface:$verstring" + done + + # Before this point, $major must not contain `.'. + major=.$major + versuffix="$major.$revision" + ;; + + linux) # correct to gnu/linux during the next big refactor + func_arith $current - $age + major=.$func_arith_result + versuffix="$major.$age.$revision" + ;; + + osf) + func_arith $current - $age + major=.$func_arith_result + versuffix=".$current.$age.$revision" + verstring="$current.$age.$revision" + + # Add in all the interfaces that we are compatible with. + loop=$age + while test "$loop" -ne 0; do + func_arith $current - $loop + iface=$func_arith_result + func_arith $loop - 1 + loop=$func_arith_result + verstring="$verstring:${iface}.0" + done + + # Make executables depend on our current version. + func_append verstring ":${current}.0" + ;; + + qnx) + major=".$current" + versuffix=".$current" + ;; + + sunos) + major=".$current" + versuffix=".$current.$revision" + ;; + + windows) + # Use '-' rather than '.', since we only want one + # extension on DOS 8.3 filesystems. + func_arith $current - $age + major=$func_arith_result + versuffix="-$major" + ;; + + *) + func_fatal_configuration "unknown library version type \`$version_type'" + ;; + esac + + # Clear the version info if we defaulted, and they specified a release. + if test -z "$vinfo" && test -n "$release"; then + major= + case $version_type in + darwin) + # we can't check for "0.0" in archive_cmds due to quoting + # problems, so we reset it completely + verstring= + ;; + *) + verstring="0.0" + ;; + esac + if test "$need_version" = no; then + versuffix= + else + versuffix=".0.0" + fi + fi + + # Remove version info from name if versioning should be avoided + if test "$avoid_version" = yes && test "$need_version" = no; then + major= + versuffix= + verstring="" + fi + + # Check to see if the archive will have undefined symbols. + if test "$allow_undefined" = yes; then + if test "$allow_undefined_flag" = unsupported; then + func_warning "undefined symbols not allowed in $host shared libraries" + build_libtool_libs=no + build_old_libs=yes + fi + else + # Don't allow undefined symbols. + allow_undefined_flag="$no_undefined_flag" + fi + + fi + + func_generate_dlsyms "$libname" "$libname" "yes" + func_append libobjs " $symfileobj" + test "X$libobjs" = "X " && libobjs= + + if test "$opt_mode" != relink; then + # Remove our outputs, but don't remove object files since they + # may have been created when compiling PIC objects. + removelist= + tempremovelist=`$ECHO "$output_objdir/*"` + for p in $tempremovelist; do + case $p in + *.$objext | *.gcno) + ;; + $output_objdir/$outputname | $output_objdir/$libname.* | $output_objdir/${libname}${release}.*) + if test "X$precious_files_regex" != "X"; then + if $ECHO "$p" | $EGREP -e "$precious_files_regex" >/dev/null 2>&1 + then + continue + fi + fi + func_append removelist " $p" + ;; + *) ;; + esac + done + test -n "$removelist" && \ + func_show_eval "${RM}r \$removelist" + fi + + # Now set the variables for building old libraries. + if test "$build_old_libs" = yes && test "$build_libtool_libs" != convenience ; then + func_append oldlibs " $output_objdir/$libname.$libext" + + # Transform .lo files to .o files. + oldobjs="$objs "`$ECHO "$libobjs" | $SP2NL | $SED "/\.${libext}$/d; $lo2o" | $NL2SP` + fi + + # Eliminate all temporary directories. + #for path in $notinst_path; do + # lib_search_path=`$ECHO "$lib_search_path " | $SED "s% $path % %g"` + # deplibs=`$ECHO "$deplibs " | $SED "s% -L$path % %g"` + # dependency_libs=`$ECHO "$dependency_libs " | $SED "s% -L$path % %g"` + #done + + if test -n "$xrpath"; then + # If the user specified any rpath flags, then add them. + temp_xrpath= + for libdir in $xrpath; do + func_replace_sysroot "$libdir" + func_append temp_xrpath " -R$func_replace_sysroot_result" + case "$finalize_rpath " in + *" $libdir "*) ;; + *) func_append finalize_rpath " $libdir" ;; + esac + done + if test "$hardcode_into_libs" != yes || test "$build_old_libs" = yes; then + dependency_libs="$temp_xrpath $dependency_libs" + fi + fi + + # Make sure dlfiles contains only unique files that won't be dlpreopened + old_dlfiles="$dlfiles" + dlfiles= + for lib in $old_dlfiles; do + case " $dlprefiles $dlfiles " in + *" $lib "*) ;; + *) func_append dlfiles " $lib" ;; + esac + done + + # Make sure dlprefiles contains only unique files + old_dlprefiles="$dlprefiles" + dlprefiles= + for lib in $old_dlprefiles; do + case "$dlprefiles " in + *" $lib "*) ;; + *) func_append dlprefiles " $lib" ;; + esac + done + + if test "$build_libtool_libs" = yes; then + if test -n "$rpath"; then + case $host in + *-*-cygwin* | *-*-mingw* | *-*-pw32* | *-*-os2* | *-*-beos* | *-cegcc* | *-*-haiku*) + # these systems don't actually have a c library (as such)! + ;; + *-*-rhapsody* | *-*-darwin1.[012]) + # Rhapsody C library is in the System framework + func_append deplibs " System.ltframework" + ;; + *-*-netbsd*) + # Don't link with libc until the a.out ld.so is fixed. + ;; + *-*-openbsd* | *-*-freebsd* | *-*-dragonfly*) + # Do not include libc due to us having libc/libc_r. + ;; + *-*-sco3.2v5* | *-*-sco5v6*) + # Causes problems with __ctype + ;; + *-*-sysv4.2uw2* | *-*-sysv5* | *-*-unixware* | *-*-OpenUNIX*) + # Compiler inserts libc in the correct place for threads to work + ;; + *) + # Add libc to deplibs on all other systems if necessary. + if test "$build_libtool_need_lc" = "yes"; then + func_append deplibs " -lc" + fi + ;; + esac + fi + + # Transform deplibs into only deplibs that can be linked in shared. + name_save=$name + libname_save=$libname + release_save=$release + versuffix_save=$versuffix + major_save=$major + # I'm not sure if I'm treating the release correctly. I think + # release should show up in the -l (ie -lgmp5) so we don't want to + # add it in twice. Is that correct? + release="" + versuffix="" + major="" + newdeplibs= + droppeddeps=no + case $deplibs_check_method in + pass_all) + # Don't check for shared/static. Everything works. + # This might be a little naive. We might want to check + # whether the library exists or not. But this is on + # osf3 & osf4 and I'm not really sure... Just + # implementing what was already the behavior. + newdeplibs=$deplibs + ;; + test_compile) + # This code stresses the "libraries are programs" paradigm to its + # limits. Maybe even breaks it. We compile a program, linking it + # against the deplibs as a proxy for the library. Then we can check + # whether they linked in statically or dynamically with ldd. + $opt_dry_run || $RM conftest.c + cat > conftest.c </dev/null` + $nocaseglob + else + potential_libs=`ls $i/$libnameglob[.-]* 2>/dev/null` + fi + for potent_lib in $potential_libs; do + # Follow soft links. + if ls -lLd "$potent_lib" 2>/dev/null | + $GREP " -> " >/dev/null; then + continue + fi + # The statement above tries to avoid entering an + # endless loop below, in case of cyclic links. + # We might still enter an endless loop, since a link + # loop can be closed while we follow links, + # but so what? + potlib="$potent_lib" + while test -h "$potlib" 2>/dev/null; do + potliblink=`ls -ld $potlib | ${SED} 's/.* -> //'` + case $potliblink in + [\\/]* | [A-Za-z]:[\\/]*) potlib="$potliblink";; + *) potlib=`$ECHO "$potlib" | $SED 's,[^/]*$,,'`"$potliblink";; + esac + done + if eval $file_magic_cmd \"\$potlib\" 2>/dev/null | + $SED -e 10q | + $EGREP "$file_magic_regex" > /dev/null; then + func_append newdeplibs " $a_deplib" + a_deplib="" + break 2 + fi + done + done + fi + if test -n "$a_deplib" ; then + droppeddeps=yes + echo + $ECHO "*** Warning: linker path does not have real file for library $a_deplib." + echo "*** I have the capability to make that library automatically link in when" + echo "*** you link to this library. But I can only do this if you have a" + echo "*** shared version of the library, which you do not appear to have" + echo "*** because I did check the linker path looking for a file starting" + if test -z "$potlib" ; then + $ECHO "*** with $libname but no candidates were found. (...for file magic test)" + else + $ECHO "*** with $libname and none of the candidates passed a file format test" + $ECHO "*** using a file magic. Last file checked: $potlib" + fi + fi + ;; + *) + # Add a -L argument. + func_append newdeplibs " $a_deplib" + ;; + esac + done # Gone through all deplibs. + ;; + match_pattern*) + set dummy $deplibs_check_method; shift + match_pattern_regex=`expr "$deplibs_check_method" : "$1 \(.*\)"` + for a_deplib in $deplibs; do + case $a_deplib in + -l*) + func_stripname -l '' "$a_deplib" + name=$func_stripname_result + if test "X$allow_libtool_libs_with_static_runtimes" = "Xyes" ; then + case " $predeps $postdeps " in + *" $a_deplib "*) + func_append newdeplibs " $a_deplib" + a_deplib="" + ;; + esac + fi + if test -n "$a_deplib" ; then + libname=`eval "\\$ECHO \"$libname_spec\""` + for i in $lib_search_path $sys_lib_search_path $shlib_search_path; do + potential_libs=`ls $i/$libname[.-]* 2>/dev/null` + for potent_lib in $potential_libs; do + potlib="$potent_lib" # see symlink-check above in file_magic test + if eval "\$ECHO \"$potent_lib\"" 2>/dev/null | $SED 10q | \ + $EGREP "$match_pattern_regex" > /dev/null; then + func_append newdeplibs " $a_deplib" + a_deplib="" + break 2 + fi + done + done + fi + if test -n "$a_deplib" ; then + droppeddeps=yes + echo + $ECHO "*** Warning: linker path does not have real file for library $a_deplib." + echo "*** I have the capability to make that library automatically link in when" + echo "*** you link to this library. But I can only do this if you have a" + echo "*** shared version of the library, which you do not appear to have" + echo "*** because I did check the linker path looking for a file starting" + if test -z "$potlib" ; then + $ECHO "*** with $libname but no candidates were found. (...for regex pattern test)" + else + $ECHO "*** with $libname and none of the candidates passed a file format test" + $ECHO "*** using a regex pattern. Last file checked: $potlib" + fi + fi + ;; + *) + # Add a -L argument. + func_append newdeplibs " $a_deplib" + ;; + esac + done # Gone through all deplibs. + ;; + none | unknown | *) + newdeplibs="" + tmp_deplibs=`$ECHO " $deplibs" | $SED 's/ -lc$//; s/ -[LR][^ ]*//g'` + if test "X$allow_libtool_libs_with_static_runtimes" = "Xyes" ; then + for i in $predeps $postdeps ; do + # can't use Xsed below, because $i might contain '/' + tmp_deplibs=`$ECHO " $tmp_deplibs" | $SED "s,$i,,"` + done + fi + case $tmp_deplibs in + *[!\ \ ]*) + echo + if test "X$deplibs_check_method" = "Xnone"; then + echo "*** Warning: inter-library dependencies are not supported in this platform." + else + echo "*** Warning: inter-library dependencies are not known to be supported." + fi + echo "*** All declared inter-library dependencies are being dropped." + droppeddeps=yes + ;; + esac + ;; + esac + versuffix=$versuffix_save + major=$major_save + release=$release_save + libname=$libname_save + name=$name_save + + case $host in + *-*-rhapsody* | *-*-darwin1.[012]) + # On Rhapsody replace the C library with the System framework + newdeplibs=`$ECHO " $newdeplibs" | $SED 's/ -lc / System.ltframework /'` + ;; + esac + + if test "$droppeddeps" = yes; then + if test "$module" = yes; then + echo + echo "*** Warning: libtool could not satisfy all declared inter-library" + $ECHO "*** dependencies of module $libname. Therefore, libtool will create" + echo "*** a static module, that should work as long as the dlopening" + echo "*** application is linked with the -dlopen flag." + if test -z "$global_symbol_pipe"; then + echo + echo "*** However, this would only work if libtool was able to extract symbol" + echo "*** lists from a program, using \`nm' or equivalent, but libtool could" + echo "*** not find such a program. So, this module is probably useless." + echo "*** \`nm' from GNU binutils and a full rebuild may help." + fi + if test "$build_old_libs" = no; then + oldlibs="$output_objdir/$libname.$libext" + build_libtool_libs=module + build_old_libs=yes + else + build_libtool_libs=no + fi + else + echo "*** The inter-library dependencies that have been dropped here will be" + echo "*** automatically added whenever a program is linked with this library" + echo "*** or is declared to -dlopen it." + + if test "$allow_undefined" = no; then + echo + echo "*** Since this library must not contain undefined symbols," + echo "*** because either the platform does not support them or" + echo "*** it was explicitly requested with -no-undefined," + echo "*** libtool will only create a static version of it." + if test "$build_old_libs" = no; then + oldlibs="$output_objdir/$libname.$libext" + build_libtool_libs=module + build_old_libs=yes + else + build_libtool_libs=no + fi + fi + fi + fi + # Done checking deplibs! + deplibs=$newdeplibs + fi + # Time to change all our "foo.ltframework" stuff back to "-framework foo" + case $host in + *-*-darwin*) + newdeplibs=`$ECHO " $newdeplibs" | $SED 's% \([^ $]*\).ltframework% -framework \1%g'` + new_inherited_linker_flags=`$ECHO " $new_inherited_linker_flags" | $SED 's% \([^ $]*\).ltframework% -framework \1%g'` + deplibs=`$ECHO " $deplibs" | $SED 's% \([^ $]*\).ltframework% -framework \1%g'` + ;; + esac + + # move library search paths that coincide with paths to not yet + # installed libraries to the beginning of the library search list + new_libs= + for path in $notinst_path; do + case " $new_libs " in + *" -L$path/$objdir "*) ;; + *) + case " $deplibs " in + *" -L$path/$objdir "*) + func_append new_libs " -L$path/$objdir" ;; + esac + ;; + esac + done + for deplib in $deplibs; do + case $deplib in + -L*) + case " $new_libs " in + *" $deplib "*) ;; + *) func_append new_libs " $deplib" ;; + esac + ;; + *) func_append new_libs " $deplib" ;; + esac + done + deplibs="$new_libs" + + # All the library-specific variables (install_libdir is set above). + library_names= + old_library= + dlname= + + # Test again, we may have decided not to build it any more + if test "$build_libtool_libs" = yes; then + # Remove ${wl} instances when linking with ld. + # FIXME: should test the right _cmds variable. + case $archive_cmds in + *\$LD\ *) wl= ;; + esac + if test "$hardcode_into_libs" = yes; then + # Hardcode the library paths + hardcode_libdirs= + dep_rpath= + rpath="$finalize_rpath" + test "$opt_mode" != relink && rpath="$compile_rpath$rpath" + for libdir in $rpath; do + if test -n "$hardcode_libdir_flag_spec"; then + if test -n "$hardcode_libdir_separator"; then + func_replace_sysroot "$libdir" + libdir=$func_replace_sysroot_result + if test -z "$hardcode_libdirs"; then + hardcode_libdirs="$libdir" + else + # Just accumulate the unique libdirs. + case $hardcode_libdir_separator$hardcode_libdirs$hardcode_libdir_separator in + *"$hardcode_libdir_separator$libdir$hardcode_libdir_separator"*) + ;; + *) + func_append hardcode_libdirs "$hardcode_libdir_separator$libdir" + ;; + esac + fi + else + eval flag=\"$hardcode_libdir_flag_spec\" + func_append dep_rpath " $flag" + fi + elif test -n "$runpath_var"; then + case "$perm_rpath " in + *" $libdir "*) ;; + *) func_append perm_rpath " $libdir" ;; + esac + fi + done + # Substitute the hardcoded libdirs into the rpath. + if test -n "$hardcode_libdir_separator" && + test -n "$hardcode_libdirs"; then + libdir="$hardcode_libdirs" + eval "dep_rpath=\"$hardcode_libdir_flag_spec\"" + fi + if test -n "$runpath_var" && test -n "$perm_rpath"; then + # We should set the runpath_var. + rpath= + for dir in $perm_rpath; do + func_append rpath "$dir:" + done + eval "$runpath_var='$rpath\$$runpath_var'; export $runpath_var" + fi + test -n "$dep_rpath" && deplibs="$dep_rpath $deplibs" + fi + + shlibpath="$finalize_shlibpath" + test "$opt_mode" != relink && shlibpath="$compile_shlibpath$shlibpath" + if test -n "$shlibpath"; then + eval "$shlibpath_var='$shlibpath\$$shlibpath_var'; export $shlibpath_var" + fi + + # Get the real and link names of the library. + eval shared_ext=\"$shrext_cmds\" + eval library_names=\"$library_names_spec\" + set dummy $library_names + shift + realname="$1" + shift + + if test -n "$soname_spec"; then + eval soname=\"$soname_spec\" + else + soname="$realname" + fi + if test -z "$dlname"; then + dlname=$soname + fi + + lib="$output_objdir/$realname" + linknames= + for link + do + func_append linknames " $link" + done + + # Use standard objects if they are pic + test -z "$pic_flag" && libobjs=`$ECHO "$libobjs" | $SP2NL | $SED "$lo2o" | $NL2SP` + test "X$libobjs" = "X " && libobjs= + + delfiles= + if test -n "$export_symbols" && test -n "$include_expsyms"; then + $opt_dry_run || cp "$export_symbols" "$output_objdir/$libname.uexp" + export_symbols="$output_objdir/$libname.uexp" + func_append delfiles " $export_symbols" + fi + + orig_export_symbols= + case $host_os in + cygwin* | mingw* | cegcc*) + if test -n "$export_symbols" && test -z "$export_symbols_regex"; then + # exporting using user supplied symfile + if test "x`$SED 1q $export_symbols`" != xEXPORTS; then + # and it's NOT already a .def file. Must figure out + # which of the given symbols are data symbols and tag + # them as such. So, trigger use of export_symbols_cmds. + # export_symbols gets reassigned inside the "prepare + # the list of exported symbols" if statement, so the + # include_expsyms logic still works. + orig_export_symbols="$export_symbols" + export_symbols= + always_export_symbols=yes + fi + fi + ;; + esac + + # Prepare the list of exported symbols + if test -z "$export_symbols"; then + if test "$always_export_symbols" = yes || test -n "$export_symbols_regex"; then + func_verbose "generating symbol list for \`$libname.la'" + export_symbols="$output_objdir/$libname.exp" + $opt_dry_run || $RM $export_symbols + cmds=$export_symbols_cmds + save_ifs="$IFS"; IFS='~' + for cmd1 in $cmds; do + IFS="$save_ifs" + # Take the normal branch if the nm_file_list_spec branch + # doesn't work or if tool conversion is not needed. + case $nm_file_list_spec~$to_tool_file_cmd in + *~func_convert_file_noop | *~func_convert_file_msys_to_w32 | ~*) + try_normal_branch=yes + eval cmd=\"$cmd1\" + func_len " $cmd" + len=$func_len_result + ;; + *) + try_normal_branch=no + ;; + esac + if test "$try_normal_branch" = yes \ + && { test "$len" -lt "$max_cmd_len" \ + || test "$max_cmd_len" -le -1; } + then + func_show_eval "$cmd" 'exit $?' + skipped_export=false + elif test -n "$nm_file_list_spec"; then + func_basename "$output" + output_la=$func_basename_result + save_libobjs=$libobjs + save_output=$output + output=${output_objdir}/${output_la}.nm + func_to_tool_file "$output" + libobjs=$nm_file_list_spec$func_to_tool_file_result + func_append delfiles " $output" + func_verbose "creating $NM input file list: $output" + for obj in $save_libobjs; do + func_to_tool_file "$obj" + $ECHO "$func_to_tool_file_result" + done > "$output" + eval cmd=\"$cmd1\" + func_show_eval "$cmd" 'exit $?' + output=$save_output + libobjs=$save_libobjs + skipped_export=false + else + # The command line is too long to execute in one step. + func_verbose "using reloadable object file for export list..." + skipped_export=: + # Break out early, otherwise skipped_export may be + # set to false by a later but shorter cmd. + break + fi + done + IFS="$save_ifs" + if test -n "$export_symbols_regex" && test "X$skipped_export" != "X:"; then + func_show_eval '$EGREP -e "$export_symbols_regex" "$export_symbols" > "${export_symbols}T"' + func_show_eval '$MV "${export_symbols}T" "$export_symbols"' + fi + fi + fi + + if test -n "$export_symbols" && test -n "$include_expsyms"; then + tmp_export_symbols="$export_symbols" + test -n "$orig_export_symbols" && tmp_export_symbols="$orig_export_symbols" + $opt_dry_run || eval '$ECHO "$include_expsyms" | $SP2NL >> "$tmp_export_symbols"' + fi + + if test "X$skipped_export" != "X:" && test -n "$orig_export_symbols"; then + # The given exports_symbols file has to be filtered, so filter it. + func_verbose "filter symbol list for \`$libname.la' to tag DATA exports" + # FIXME: $output_objdir/$libname.filter potentially contains lots of + # 's' commands which not all seds can handle. GNU sed should be fine + # though. Also, the filter scales superlinearly with the number of + # global variables. join(1) would be nice here, but unfortunately + # isn't a blessed tool. + $opt_dry_run || $SED -e '/[ ,]DATA/!d;s,\(.*\)\([ \,].*\),s|^\1$|\1\2|,' < $export_symbols > $output_objdir/$libname.filter + func_append delfiles " $export_symbols $output_objdir/$libname.filter" + export_symbols=$output_objdir/$libname.def + $opt_dry_run || $SED -f $output_objdir/$libname.filter < $orig_export_symbols > $export_symbols + fi + + tmp_deplibs= + for test_deplib in $deplibs; do + case " $convenience " in + *" $test_deplib "*) ;; + *) + func_append tmp_deplibs " $test_deplib" + ;; + esac + done + deplibs="$tmp_deplibs" + + if test -n "$convenience"; then + if test -n "$whole_archive_flag_spec" && + test "$compiler_needs_object" = yes && + test -z "$libobjs"; then + # extract the archives, so we have objects to list. + # TODO: could optimize this to just extract one archive. + whole_archive_flag_spec= + fi + if test -n "$whole_archive_flag_spec"; then + save_libobjs=$libobjs + eval libobjs=\"\$libobjs $whole_archive_flag_spec\" + test "X$libobjs" = "X " && libobjs= + else + gentop="$output_objdir/${outputname}x" + func_append generated " $gentop" + + func_extract_archives $gentop $convenience + func_append libobjs " $func_extract_archives_result" + test "X$libobjs" = "X " && libobjs= + fi + fi + + if test "$thread_safe" = yes && test -n "$thread_safe_flag_spec"; then + eval flag=\"$thread_safe_flag_spec\" + func_append linker_flags " $flag" + fi + + # Make a backup of the uninstalled library when relinking + if test "$opt_mode" = relink; then + $opt_dry_run || eval '(cd $output_objdir && $RM ${realname}U && $MV $realname ${realname}U)' || exit $? + fi + + # Do each of the archive commands. + if test "$module" = yes && test -n "$module_cmds" ; then + if test -n "$export_symbols" && test -n "$module_expsym_cmds"; then + eval test_cmds=\"$module_expsym_cmds\" + cmds=$module_expsym_cmds + else + eval test_cmds=\"$module_cmds\" + cmds=$module_cmds + fi + else + if test -n "$export_symbols" && test -n "$archive_expsym_cmds"; then + eval test_cmds=\"$archive_expsym_cmds\" + cmds=$archive_expsym_cmds + else + eval test_cmds=\"$archive_cmds\" + cmds=$archive_cmds + fi + fi + + if test "X$skipped_export" != "X:" && + func_len " $test_cmds" && + len=$func_len_result && + test "$len" -lt "$max_cmd_len" || test "$max_cmd_len" -le -1; then + : + else + # The command line is too long to link in one step, link piecewise + # or, if using GNU ld and skipped_export is not :, use a linker + # script. + + # Save the value of $output and $libobjs because we want to + # use them later. If we have whole_archive_flag_spec, we + # want to use save_libobjs as it was before + # whole_archive_flag_spec was expanded, because we can't + # assume the linker understands whole_archive_flag_spec. + # This may have to be revisited, in case too many + # convenience libraries get linked in and end up exceeding + # the spec. + if test -z "$convenience" || test -z "$whole_archive_flag_spec"; then + save_libobjs=$libobjs + fi + save_output=$output + func_basename "$output" + output_la=$func_basename_result + + # Clear the reloadable object creation command queue and + # initialize k to one. + test_cmds= + concat_cmds= + objlist= + last_robj= + k=1 + + if test -n "$save_libobjs" && test "X$skipped_export" != "X:" && test "$with_gnu_ld" = yes; then + output=${output_objdir}/${output_la}.lnkscript + func_verbose "creating GNU ld script: $output" + echo 'INPUT (' > $output + for obj in $save_libobjs + do + func_to_tool_file "$obj" + $ECHO "$func_to_tool_file_result" >> $output + done + echo ')' >> $output + func_append delfiles " $output" + func_to_tool_file "$output" + output=$func_to_tool_file_result + elif test -n "$save_libobjs" && test "X$skipped_export" != "X:" && test "X$file_list_spec" != X; then + output=${output_objdir}/${output_la}.lnk + func_verbose "creating linker input file list: $output" + : > $output + set x $save_libobjs + shift + firstobj= + if test "$compiler_needs_object" = yes; then + firstobj="$1 " + shift + fi + for obj + do + func_to_tool_file "$obj" + $ECHO "$func_to_tool_file_result" >> $output + done + func_append delfiles " $output" + func_to_tool_file "$output" + output=$firstobj\"$file_list_spec$func_to_tool_file_result\" + else + if test -n "$save_libobjs"; then + func_verbose "creating reloadable object files..." + output=$output_objdir/$output_la-${k}.$objext + eval test_cmds=\"$reload_cmds\" + func_len " $test_cmds" + len0=$func_len_result + len=$len0 + + # Loop over the list of objects to be linked. + for obj in $save_libobjs + do + func_len " $obj" + func_arith $len + $func_len_result + len=$func_arith_result + if test "X$objlist" = X || + test "$len" -lt "$max_cmd_len"; then + func_append objlist " $obj" + else + # The command $test_cmds is almost too long, add a + # command to the queue. + if test "$k" -eq 1 ; then + # The first file doesn't have a previous command to add. + reload_objs=$objlist + eval concat_cmds=\"$reload_cmds\" + else + # All subsequent reloadable object files will link in + # the last one created. + reload_objs="$objlist $last_robj" + eval concat_cmds=\"\$concat_cmds~$reload_cmds~\$RM $last_robj\" + fi + last_robj=$output_objdir/$output_la-${k}.$objext + func_arith $k + 1 + k=$func_arith_result + output=$output_objdir/$output_la-${k}.$objext + objlist=" $obj" + func_len " $last_robj" + func_arith $len0 + $func_len_result + len=$func_arith_result + fi + done + # Handle the remaining objects by creating one last + # reloadable object file. All subsequent reloadable object + # files will link in the last one created. + test -z "$concat_cmds" || concat_cmds=$concat_cmds~ + reload_objs="$objlist $last_robj" + eval concat_cmds=\"\${concat_cmds}$reload_cmds\" + if test -n "$last_robj"; then + eval concat_cmds=\"\${concat_cmds}~\$RM $last_robj\" + fi + func_append delfiles " $output" + + else + output= + fi + + if ${skipped_export-false}; then + func_verbose "generating symbol list for \`$libname.la'" + export_symbols="$output_objdir/$libname.exp" + $opt_dry_run || $RM $export_symbols + libobjs=$output + # Append the command to create the export file. + test -z "$concat_cmds" || concat_cmds=$concat_cmds~ + eval concat_cmds=\"\$concat_cmds$export_symbols_cmds\" + if test -n "$last_robj"; then + eval concat_cmds=\"\$concat_cmds~\$RM $last_robj\" + fi + fi + + test -n "$save_libobjs" && + func_verbose "creating a temporary reloadable object file: $output" + + # Loop through the commands generated above and execute them. + save_ifs="$IFS"; IFS='~' + for cmd in $concat_cmds; do + IFS="$save_ifs" + $opt_silent || { + func_quote_for_expand "$cmd" + eval "func_echo $func_quote_for_expand_result" + } + $opt_dry_run || eval "$cmd" || { + lt_exit=$? + + # Restore the uninstalled library and exit + if test "$opt_mode" = relink; then + ( cd "$output_objdir" && \ + $RM "${realname}T" && \ + $MV "${realname}U" "$realname" ) + fi + + exit $lt_exit + } + done + IFS="$save_ifs" + + if test -n "$export_symbols_regex" && ${skipped_export-false}; then + func_show_eval '$EGREP -e "$export_symbols_regex" "$export_symbols" > "${export_symbols}T"' + func_show_eval '$MV "${export_symbols}T" "$export_symbols"' + fi + fi + + if ${skipped_export-false}; then + if test -n "$export_symbols" && test -n "$include_expsyms"; then + tmp_export_symbols="$export_symbols" + test -n "$orig_export_symbols" && tmp_export_symbols="$orig_export_symbols" + $opt_dry_run || eval '$ECHO "$include_expsyms" | $SP2NL >> "$tmp_export_symbols"' + fi + + if test -n "$orig_export_symbols"; then + # The given exports_symbols file has to be filtered, so filter it. + func_verbose "filter symbol list for \`$libname.la' to tag DATA exports" + # FIXME: $output_objdir/$libname.filter potentially contains lots of + # 's' commands which not all seds can handle. GNU sed should be fine + # though. Also, the filter scales superlinearly with the number of + # global variables. join(1) would be nice here, but unfortunately + # isn't a blessed tool. + $opt_dry_run || $SED -e '/[ ,]DATA/!d;s,\(.*\)\([ \,].*\),s|^\1$|\1\2|,' < $export_symbols > $output_objdir/$libname.filter + func_append delfiles " $export_symbols $output_objdir/$libname.filter" + export_symbols=$output_objdir/$libname.def + $opt_dry_run || $SED -f $output_objdir/$libname.filter < $orig_export_symbols > $export_symbols + fi + fi + + libobjs=$output + # Restore the value of output. + output=$save_output + + if test -n "$convenience" && test -n "$whole_archive_flag_spec"; then + eval libobjs=\"\$libobjs $whole_archive_flag_spec\" + test "X$libobjs" = "X " && libobjs= + fi + # Expand the library linking commands again to reset the + # value of $libobjs for piecewise linking. + + # Do each of the archive commands. + if test "$module" = yes && test -n "$module_cmds" ; then + if test -n "$export_symbols" && test -n "$module_expsym_cmds"; then + cmds=$module_expsym_cmds + else + cmds=$module_cmds + fi + else + if test -n "$export_symbols" && test -n "$archive_expsym_cmds"; then + cmds=$archive_expsym_cmds + else + cmds=$archive_cmds + fi + fi + fi + + if test -n "$delfiles"; then + # Append the command to remove temporary files to $cmds. + eval cmds=\"\$cmds~\$RM $delfiles\" + fi + + # Add any objects from preloaded convenience libraries + if test -n "$dlprefiles"; then + gentop="$output_objdir/${outputname}x" + func_append generated " $gentop" + + func_extract_archives $gentop $dlprefiles + func_append libobjs " $func_extract_archives_result" + test "X$libobjs" = "X " && libobjs= + fi + + save_ifs="$IFS"; IFS='~' + for cmd in $cmds; do + IFS="$save_ifs" + eval cmd=\"$cmd\" + $opt_silent || { + func_quote_for_expand "$cmd" + eval "func_echo $func_quote_for_expand_result" + } + $opt_dry_run || eval "$cmd" || { + lt_exit=$? + + # Restore the uninstalled library and exit + if test "$opt_mode" = relink; then + ( cd "$output_objdir" && \ + $RM "${realname}T" && \ + $MV "${realname}U" "$realname" ) + fi + + exit $lt_exit + } + done + IFS="$save_ifs" + + # Restore the uninstalled library and exit + if test "$opt_mode" = relink; then + $opt_dry_run || eval '(cd $output_objdir && $RM ${realname}T && $MV $realname ${realname}T && $MV ${realname}U $realname)' || exit $? + + if test -n "$convenience"; then + if test -z "$whole_archive_flag_spec"; then + func_show_eval '${RM}r "$gentop"' + fi + fi + + exit $EXIT_SUCCESS + fi + + # Create links to the real library. + for linkname in $linknames; do + if test "$realname" != "$linkname"; then + func_show_eval '(cd "$output_objdir" && $RM "$linkname" && $LN_S "$realname" "$linkname")' 'exit $?' + fi + done + + # If -module or -export-dynamic was specified, set the dlname. + if test "$module" = yes || test "$export_dynamic" = yes; then + # On all known operating systems, these are identical. + dlname="$soname" + fi + fi + ;; + + obj) + if test -n "$dlfiles$dlprefiles" || test "$dlself" != no; then + func_warning "\`-dlopen' is ignored for objects" + fi + + case " $deplibs" in + *\ -l* | *\ -L*) + func_warning "\`-l' and \`-L' are ignored for objects" ;; + esac + + test -n "$rpath" && \ + func_warning "\`-rpath' is ignored for objects" + + test -n "$xrpath" && \ + func_warning "\`-R' is ignored for objects" + + test -n "$vinfo" && \ + func_warning "\`-version-info' is ignored for objects" + + test -n "$release" && \ + func_warning "\`-release' is ignored for objects" + + case $output in + *.lo) + test -n "$objs$old_deplibs" && \ + func_fatal_error "cannot build library object \`$output' from non-libtool objects" + + libobj=$output + func_lo2o "$libobj" + obj=$func_lo2o_result + ;; + *) + libobj= + obj="$output" + ;; + esac + + # Delete the old objects. + $opt_dry_run || $RM $obj $libobj + + # Objects from convenience libraries. This assumes + # single-version convenience libraries. Whenever we create + # different ones for PIC/non-PIC, this we'll have to duplicate + # the extraction. + reload_conv_objs= + gentop= + # reload_cmds runs $LD directly, so let us get rid of + # -Wl from whole_archive_flag_spec and hope we can get by with + # turning comma into space.. + wl= + + if test -n "$convenience"; then + if test -n "$whole_archive_flag_spec"; then + eval tmp_whole_archive_flags=\"$whole_archive_flag_spec\" + reload_conv_objs=$reload_objs\ `$ECHO "$tmp_whole_archive_flags" | $SED 's|,| |g'` + else + gentop="$output_objdir/${obj}x" + func_append generated " $gentop" + + func_extract_archives $gentop $convenience + reload_conv_objs="$reload_objs $func_extract_archives_result" + fi + fi + + # If we're not building shared, we need to use non_pic_objs + test "$build_libtool_libs" != yes && libobjs="$non_pic_objects" + + # Create the old-style object. + reload_objs="$objs$old_deplibs "`$ECHO "$libobjs" | $SP2NL | $SED "/\.${libext}$/d; /\.lib$/d; $lo2o" | $NL2SP`" $reload_conv_objs" ### testsuite: skip nested quoting test + + output="$obj" + func_execute_cmds "$reload_cmds" 'exit $?' + + # Exit if we aren't doing a library object file. + if test -z "$libobj"; then + if test -n "$gentop"; then + func_show_eval '${RM}r "$gentop"' + fi + + exit $EXIT_SUCCESS + fi + + if test "$build_libtool_libs" != yes; then + if test -n "$gentop"; then + func_show_eval '${RM}r "$gentop"' + fi + + # Create an invalid libtool object if no PIC, so that we don't + # accidentally link it into a program. + # $show "echo timestamp > $libobj" + # $opt_dry_run || eval "echo timestamp > $libobj" || exit $? + exit $EXIT_SUCCESS + fi + + if test -n "$pic_flag" || test "$pic_mode" != default; then + # Only do commands if we really have different PIC objects. + reload_objs="$libobjs $reload_conv_objs" + output="$libobj" + func_execute_cmds "$reload_cmds" 'exit $?' + fi + + if test -n "$gentop"; then + func_show_eval '${RM}r "$gentop"' + fi + + exit $EXIT_SUCCESS + ;; + + prog) + case $host in + *cygwin*) func_stripname '' '.exe' "$output" + output=$func_stripname_result.exe;; + esac + test -n "$vinfo" && \ + func_warning "\`-version-info' is ignored for programs" + + test -n "$release" && \ + func_warning "\`-release' is ignored for programs" + + test "$preload" = yes \ + && test "$dlopen_support" = unknown \ + && test "$dlopen_self" = unknown \ + && test "$dlopen_self_static" = unknown && \ + func_warning "\`LT_INIT([dlopen])' not used. Assuming no dlopen support." + + case $host in + *-*-rhapsody* | *-*-darwin1.[012]) + # On Rhapsody replace the C library is the System framework + compile_deplibs=`$ECHO " $compile_deplibs" | $SED 's/ -lc / System.ltframework /'` + finalize_deplibs=`$ECHO " $finalize_deplibs" | $SED 's/ -lc / System.ltframework /'` + ;; + esac + + case $host in + *-*-darwin*) + # Don't allow lazy linking, it breaks C++ global constructors + # But is supposedly fixed on 10.4 or later (yay!). + if test "$tagname" = CXX ; then + case ${MACOSX_DEPLOYMENT_TARGET-10.0} in + 10.[0123]) + func_append compile_command " ${wl}-bind_at_load" + func_append finalize_command " ${wl}-bind_at_load" + ;; + esac + fi + # Time to change all our "foo.ltframework" stuff back to "-framework foo" + compile_deplibs=`$ECHO " $compile_deplibs" | $SED 's% \([^ $]*\).ltframework% -framework \1%g'` + finalize_deplibs=`$ECHO " $finalize_deplibs" | $SED 's% \([^ $]*\).ltframework% -framework \1%g'` + ;; + esac + + + # move library search paths that coincide with paths to not yet + # installed libraries to the beginning of the library search list + new_libs= + for path in $notinst_path; do + case " $new_libs " in + *" -L$path/$objdir "*) ;; + *) + case " $compile_deplibs " in + *" -L$path/$objdir "*) + func_append new_libs " -L$path/$objdir" ;; + esac + ;; + esac + done + for deplib in $compile_deplibs; do + case $deplib in + -L*) + case " $new_libs " in + *" $deplib "*) ;; + *) func_append new_libs " $deplib" ;; + esac + ;; + *) func_append new_libs " $deplib" ;; + esac + done + compile_deplibs="$new_libs" + + + func_append compile_command " $compile_deplibs" + func_append finalize_command " $finalize_deplibs" + + if test -n "$rpath$xrpath"; then + # If the user specified any rpath flags, then add them. + for libdir in $rpath $xrpath; do + # This is the magic to use -rpath. + case "$finalize_rpath " in + *" $libdir "*) ;; + *) func_append finalize_rpath " $libdir" ;; + esac + done + fi + + # Now hardcode the library paths + rpath= + hardcode_libdirs= + for libdir in $compile_rpath $finalize_rpath; do + if test -n "$hardcode_libdir_flag_spec"; then + if test -n "$hardcode_libdir_separator"; then + if test -z "$hardcode_libdirs"; then + hardcode_libdirs="$libdir" + else + # Just accumulate the unique libdirs. + case $hardcode_libdir_separator$hardcode_libdirs$hardcode_libdir_separator in + *"$hardcode_libdir_separator$libdir$hardcode_libdir_separator"*) + ;; + *) + func_append hardcode_libdirs "$hardcode_libdir_separator$libdir" + ;; + esac + fi + else + eval flag=\"$hardcode_libdir_flag_spec\" + func_append rpath " $flag" + fi + elif test -n "$runpath_var"; then + case "$perm_rpath " in + *" $libdir "*) ;; + *) func_append perm_rpath " $libdir" ;; + esac + fi + case $host in + *-*-cygwin* | *-*-mingw* | *-*-pw32* | *-*-os2* | *-cegcc*) + testbindir=`${ECHO} "$libdir" | ${SED} -e 's*/lib$*/bin*'` + case :$dllsearchpath: in + *":$libdir:"*) ;; + ::) dllsearchpath=$libdir;; + *) func_append dllsearchpath ":$libdir";; + esac + case :$dllsearchpath: in + *":$testbindir:"*) ;; + ::) dllsearchpath=$testbindir;; + *) func_append dllsearchpath ":$testbindir";; + esac + ;; + esac + done + # Substitute the hardcoded libdirs into the rpath. + if test -n "$hardcode_libdir_separator" && + test -n "$hardcode_libdirs"; then + libdir="$hardcode_libdirs" + eval rpath=\" $hardcode_libdir_flag_spec\" + fi + compile_rpath="$rpath" + + rpath= + hardcode_libdirs= + for libdir in $finalize_rpath; do + if test -n "$hardcode_libdir_flag_spec"; then + if test -n "$hardcode_libdir_separator"; then + if test -z "$hardcode_libdirs"; then + hardcode_libdirs="$libdir" + else + # Just accumulate the unique libdirs. + case $hardcode_libdir_separator$hardcode_libdirs$hardcode_libdir_separator in + *"$hardcode_libdir_separator$libdir$hardcode_libdir_separator"*) + ;; + *) + func_append hardcode_libdirs "$hardcode_libdir_separator$libdir" + ;; + esac + fi + else + eval flag=\"$hardcode_libdir_flag_spec\" + func_append rpath " $flag" + fi + elif test -n "$runpath_var"; then + case "$finalize_perm_rpath " in + *" $libdir "*) ;; + *) func_append finalize_perm_rpath " $libdir" ;; + esac + fi + done + # Substitute the hardcoded libdirs into the rpath. + if test -n "$hardcode_libdir_separator" && + test -n "$hardcode_libdirs"; then + libdir="$hardcode_libdirs" + eval rpath=\" $hardcode_libdir_flag_spec\" + fi + finalize_rpath="$rpath" + + if test -n "$libobjs" && test "$build_old_libs" = yes; then + # Transform all the library objects into standard objects. + compile_command=`$ECHO "$compile_command" | $SP2NL | $SED "$lo2o" | $NL2SP` + finalize_command=`$ECHO "$finalize_command" | $SP2NL | $SED "$lo2o" | $NL2SP` + fi + + func_generate_dlsyms "$outputname" "@PROGRAM@" "no" + + # template prelinking step + if test -n "$prelink_cmds"; then + func_execute_cmds "$prelink_cmds" 'exit $?' + fi + + wrappers_required=yes + case $host in + *cegcc* | *mingw32ce*) + # Disable wrappers for cegcc and mingw32ce hosts, we are cross compiling anyway. + wrappers_required=no + ;; + *cygwin* | *mingw* ) + if test "$build_libtool_libs" != yes; then + wrappers_required=no + fi + ;; + *) + if test "$need_relink" = no || test "$build_libtool_libs" != yes; then + wrappers_required=no + fi + ;; + esac + if test "$wrappers_required" = no; then + # Replace the output file specification. + compile_command=`$ECHO "$compile_command" | $SED 's%@OUTPUT@%'"$output"'%g'` + link_command="$compile_command$compile_rpath" + + # We have no uninstalled library dependencies, so finalize right now. + exit_status=0 + func_show_eval "$link_command" 'exit_status=$?' + + if test -n "$postlink_cmds"; then + func_to_tool_file "$output" + postlink_cmds=`func_echo_all "$postlink_cmds" | $SED -e 's%@OUTPUT@%'"$output"'%g' -e 's%@TOOL_OUTPUT@%'"$func_to_tool_file_result"'%g'` + func_execute_cmds "$postlink_cmds" 'exit $?' + fi + + # Delete the generated files. + if test -f "$output_objdir/${outputname}S.${objext}"; then + func_show_eval '$RM "$output_objdir/${outputname}S.${objext}"' + fi + + exit $exit_status + fi + + if test -n "$compile_shlibpath$finalize_shlibpath"; then + compile_command="$shlibpath_var=\"$compile_shlibpath$finalize_shlibpath\$$shlibpath_var\" $compile_command" + fi + if test -n "$finalize_shlibpath"; then + finalize_command="$shlibpath_var=\"$finalize_shlibpath\$$shlibpath_var\" $finalize_command" + fi + + compile_var= + finalize_var= + if test -n "$runpath_var"; then + if test -n "$perm_rpath"; then + # We should set the runpath_var. + rpath= + for dir in $perm_rpath; do + func_append rpath "$dir:" + done + compile_var="$runpath_var=\"$rpath\$$runpath_var\" " + fi + if test -n "$finalize_perm_rpath"; then + # We should set the runpath_var. + rpath= + for dir in $finalize_perm_rpath; do + func_append rpath "$dir:" + done + finalize_var="$runpath_var=\"$rpath\$$runpath_var\" " + fi + fi + + if test "$no_install" = yes; then + # We don't need to create a wrapper script. + link_command="$compile_var$compile_command$compile_rpath" + # Replace the output file specification. + link_command=`$ECHO "$link_command" | $SED 's%@OUTPUT@%'"$output"'%g'` + # Delete the old output file. + $opt_dry_run || $RM $output + # Link the executable and exit + func_show_eval "$link_command" 'exit $?' + + if test -n "$postlink_cmds"; then + func_to_tool_file "$output" + postlink_cmds=`func_echo_all "$postlink_cmds" | $SED -e 's%@OUTPUT@%'"$output"'%g' -e 's%@TOOL_OUTPUT@%'"$func_to_tool_file_result"'%g'` + func_execute_cmds "$postlink_cmds" 'exit $?' + fi + + exit $EXIT_SUCCESS + fi + + if test "$hardcode_action" = relink; then + # Fast installation is not supported + link_command="$compile_var$compile_command$compile_rpath" + relink_command="$finalize_var$finalize_command$finalize_rpath" + + func_warning "this platform does not like uninstalled shared libraries" + func_warning "\`$output' will be relinked during installation" + else + if test "$fast_install" != no; then + link_command="$finalize_var$compile_command$finalize_rpath" + if test "$fast_install" = yes; then + relink_command=`$ECHO "$compile_var$compile_command$compile_rpath" | $SED 's%@OUTPUT@%\$progdir/\$file%g'` + else + # fast_install is set to needless + relink_command= + fi + else + link_command="$compile_var$compile_command$compile_rpath" + relink_command="$finalize_var$finalize_command$finalize_rpath" + fi + fi + + # Replace the output file specification. + link_command=`$ECHO "$link_command" | $SED 's%@OUTPUT@%'"$output_objdir/$outputname"'%g'` + + # Delete the old output files. + $opt_dry_run || $RM $output $output_objdir/$outputname $output_objdir/lt-$outputname + + func_show_eval "$link_command" 'exit $?' + + if test -n "$postlink_cmds"; then + func_to_tool_file "$output_objdir/$outputname" + postlink_cmds=`func_echo_all "$postlink_cmds" | $SED -e 's%@OUTPUT@%'"$output_objdir/$outputname"'%g' -e 's%@TOOL_OUTPUT@%'"$func_to_tool_file_result"'%g'` + func_execute_cmds "$postlink_cmds" 'exit $?' + fi + + # Now create the wrapper script. + func_verbose "creating $output" + + # Quote the relink command for shipping. + if test -n "$relink_command"; then + # Preserve any variables that may affect compiler behavior + for var in $variables_saved_for_relink; do + if eval test -z \"\${$var+set}\"; then + relink_command="{ test -z \"\${$var+set}\" || $lt_unset $var || { $var=; export $var; }; }; $relink_command" + elif eval var_value=\$$var; test -z "$var_value"; then + relink_command="$var=; export $var; $relink_command" + else + func_quote_for_eval "$var_value" + relink_command="$var=$func_quote_for_eval_result; export $var; $relink_command" + fi + done + relink_command="(cd `pwd`; $relink_command)" + relink_command=`$ECHO "$relink_command" | $SED "$sed_quote_subst"` + fi + + # Only actually do things if not in dry run mode. + $opt_dry_run || { + # win32 will think the script is a binary if it has + # a .exe suffix, so we strip it off here. + case $output in + *.exe) func_stripname '' '.exe' "$output" + output=$func_stripname_result ;; + esac + # test for cygwin because mv fails w/o .exe extensions + case $host in + *cygwin*) + exeext=.exe + func_stripname '' '.exe' "$outputname" + outputname=$func_stripname_result ;; + *) exeext= ;; + esac + case $host in + *cygwin* | *mingw* ) + func_dirname_and_basename "$output" "" "." + output_name=$func_basename_result + output_path=$func_dirname_result + cwrappersource="$output_path/$objdir/lt-$output_name.c" + cwrapper="$output_path/$output_name.exe" + $RM $cwrappersource $cwrapper + trap "$RM $cwrappersource $cwrapper; exit $EXIT_FAILURE" 1 2 15 + + func_emit_cwrapperexe_src > $cwrappersource + + # The wrapper executable is built using the $host compiler, + # because it contains $host paths and files. If cross- + # compiling, it, like the target executable, must be + # executed on the $host or under an emulation environment. + $opt_dry_run || { + $LTCC $LTCFLAGS -o $cwrapper $cwrappersource + $STRIP $cwrapper + } + + # Now, create the wrapper script for func_source use: + func_ltwrapper_scriptname $cwrapper + $RM $func_ltwrapper_scriptname_result + trap "$RM $func_ltwrapper_scriptname_result; exit $EXIT_FAILURE" 1 2 15 + $opt_dry_run || { + # note: this script will not be executed, so do not chmod. + if test "x$build" = "x$host" ; then + $cwrapper --lt-dump-script > $func_ltwrapper_scriptname_result + else + func_emit_wrapper no > $func_ltwrapper_scriptname_result + fi + } + ;; + * ) + $RM $output + trap "$RM $output; exit $EXIT_FAILURE" 1 2 15 + + func_emit_wrapper no > $output + chmod +x $output + ;; + esac + } + exit $EXIT_SUCCESS + ;; + esac + + # See if we need to build an old-fashioned archive. + for oldlib in $oldlibs; do + + if test "$build_libtool_libs" = convenience; then + oldobjs="$libobjs_save $symfileobj" + addlibs="$convenience" + build_libtool_libs=no + else + if test "$build_libtool_libs" = module; then + oldobjs="$libobjs_save" + build_libtool_libs=no + else + oldobjs="$old_deplibs $non_pic_objects" + if test "$preload" = yes && test -f "$symfileobj"; then + func_append oldobjs " $symfileobj" + fi + fi + addlibs="$old_convenience" + fi + + if test -n "$addlibs"; then + gentop="$output_objdir/${outputname}x" + func_append generated " $gentop" + + func_extract_archives $gentop $addlibs + func_append oldobjs " $func_extract_archives_result" + fi + + # Do each command in the archive commands. + if test -n "$old_archive_from_new_cmds" && test "$build_libtool_libs" = yes; then + cmds=$old_archive_from_new_cmds + else + + # Add any objects from preloaded convenience libraries + if test -n "$dlprefiles"; then + gentop="$output_objdir/${outputname}x" + func_append generated " $gentop" + + func_extract_archives $gentop $dlprefiles + func_append oldobjs " $func_extract_archives_result" + fi + + # POSIX demands no paths to be encoded in archives. We have + # to avoid creating archives with duplicate basenames if we + # might have to extract them afterwards, e.g., when creating a + # static archive out of a convenience library, or when linking + # the entirety of a libtool archive into another (currently + # not supported by libtool). + if (for obj in $oldobjs + do + func_basename "$obj" + $ECHO "$func_basename_result" + done | sort | sort -uc >/dev/null 2>&1); then + : + else + echo "copying selected object files to avoid basename conflicts..." + gentop="$output_objdir/${outputname}x" + func_append generated " $gentop" + func_mkdir_p "$gentop" + save_oldobjs=$oldobjs + oldobjs= + counter=1 + for obj in $save_oldobjs + do + func_basename "$obj" + objbase="$func_basename_result" + case " $oldobjs " in + " ") oldobjs=$obj ;; + *[\ /]"$objbase "*) + while :; do + # Make sure we don't pick an alternate name that also + # overlaps. + newobj=lt$counter-$objbase + func_arith $counter + 1 + counter=$func_arith_result + case " $oldobjs " in + *[\ /]"$newobj "*) ;; + *) if test ! -f "$gentop/$newobj"; then break; fi ;; + esac + done + func_show_eval "ln $obj $gentop/$newobj || cp $obj $gentop/$newobj" + func_append oldobjs " $gentop/$newobj" + ;; + *) func_append oldobjs " $obj" ;; + esac + done + fi + func_to_tool_file "$oldlib" func_convert_file_msys_to_w32 + tool_oldlib=$func_to_tool_file_result + eval cmds=\"$old_archive_cmds\" + + func_len " $cmds" + len=$func_len_result + if test "$len" -lt "$max_cmd_len" || test "$max_cmd_len" -le -1; then + cmds=$old_archive_cmds + elif test -n "$archiver_list_spec"; then + func_verbose "using command file archive linking..." + for obj in $oldobjs + do + func_to_tool_file "$obj" + $ECHO "$func_to_tool_file_result" + done > $output_objdir/$libname.libcmd + func_to_tool_file "$output_objdir/$libname.libcmd" + oldobjs=" $archiver_list_spec$func_to_tool_file_result" + cmds=$old_archive_cmds + else + # the command line is too long to link in one step, link in parts + func_verbose "using piecewise archive linking..." + save_RANLIB=$RANLIB + RANLIB=: + objlist= + concat_cmds= + save_oldobjs=$oldobjs + oldobjs= + # Is there a better way of finding the last object in the list? + for obj in $save_oldobjs + do + last_oldobj=$obj + done + eval test_cmds=\"$old_archive_cmds\" + func_len " $test_cmds" + len0=$func_len_result + len=$len0 + for obj in $save_oldobjs + do + func_len " $obj" + func_arith $len + $func_len_result + len=$func_arith_result + func_append objlist " $obj" + if test "$len" -lt "$max_cmd_len"; then + : + else + # the above command should be used before it gets too long + oldobjs=$objlist + if test "$obj" = "$last_oldobj" ; then + RANLIB=$save_RANLIB + fi + test -z "$concat_cmds" || concat_cmds=$concat_cmds~ + eval concat_cmds=\"\${concat_cmds}$old_archive_cmds\" + objlist= + len=$len0 + fi + done + RANLIB=$save_RANLIB + oldobjs=$objlist + if test "X$oldobjs" = "X" ; then + eval cmds=\"\$concat_cmds\" + else + eval cmds=\"\$concat_cmds~\$old_archive_cmds\" + fi + fi + fi + func_execute_cmds "$cmds" 'exit $?' + done + + test -n "$generated" && \ + func_show_eval "${RM}r$generated" + + # Now create the libtool archive. + case $output in + *.la) + old_library= + test "$build_old_libs" = yes && old_library="$libname.$libext" + func_verbose "creating $output" + + # Preserve any variables that may affect compiler behavior + for var in $variables_saved_for_relink; do + if eval test -z \"\${$var+set}\"; then + relink_command="{ test -z \"\${$var+set}\" || $lt_unset $var || { $var=; export $var; }; }; $relink_command" + elif eval var_value=\$$var; test -z "$var_value"; then + relink_command="$var=; export $var; $relink_command" + else + func_quote_for_eval "$var_value" + relink_command="$var=$func_quote_for_eval_result; export $var; $relink_command" + fi + done + # Quote the link command for shipping. + relink_command="(cd `pwd`; $SHELL $progpath $preserve_args --mode=relink $libtool_args @inst_prefix_dir@)" + relink_command=`$ECHO "$relink_command" | $SED "$sed_quote_subst"` + if test "$hardcode_automatic" = yes ; then + relink_command= + fi + + # Only create the output if not a dry run. + $opt_dry_run || { + for installed in no yes; do + if test "$installed" = yes; then + if test -z "$install_libdir"; then + break + fi + output="$output_objdir/$outputname"i + # Replace all uninstalled libtool libraries with the installed ones + newdependency_libs= + for deplib in $dependency_libs; do + case $deplib in + *.la) + func_basename "$deplib" + name="$func_basename_result" + func_resolve_sysroot "$deplib" + eval libdir=`${SED} -n -e 's/^libdir=\(.*\)$/\1/p' $func_resolve_sysroot_result` + test -z "$libdir" && \ + func_fatal_error "\`$deplib' is not a valid libtool archive" + func_append newdependency_libs " ${lt_sysroot:+=}$libdir/$name" + ;; + -L*) + func_stripname -L '' "$deplib" + func_replace_sysroot "$func_stripname_result" + func_append newdependency_libs " -L$func_replace_sysroot_result" + ;; + -R*) + func_stripname -R '' "$deplib" + func_replace_sysroot "$func_stripname_result" + func_append newdependency_libs " -R$func_replace_sysroot_result" + ;; + *) func_append newdependency_libs " $deplib" ;; + esac + done + dependency_libs="$newdependency_libs" + newdlfiles= + + for lib in $dlfiles; do + case $lib in + *.la) + func_basename "$lib" + name="$func_basename_result" + eval libdir=`${SED} -n -e 's/^libdir=\(.*\)$/\1/p' $lib` + test -z "$libdir" && \ + func_fatal_error "\`$lib' is not a valid libtool archive" + func_append newdlfiles " ${lt_sysroot:+=}$libdir/$name" + ;; + *) func_append newdlfiles " $lib" ;; + esac + done + dlfiles="$newdlfiles" + newdlprefiles= + for lib in $dlprefiles; do + case $lib in + *.la) + # Only pass preopened files to the pseudo-archive (for + # eventual linking with the app. that links it) if we + # didn't already link the preopened objects directly into + # the library: + func_basename "$lib" + name="$func_basename_result" + eval libdir=`${SED} -n -e 's/^libdir=\(.*\)$/\1/p' $lib` + test -z "$libdir" && \ + func_fatal_error "\`$lib' is not a valid libtool archive" + func_append newdlprefiles " ${lt_sysroot:+=}$libdir/$name" + ;; + esac + done + dlprefiles="$newdlprefiles" + else + newdlfiles= + for lib in $dlfiles; do + case $lib in + [\\/]* | [A-Za-z]:[\\/]*) abs="$lib" ;; + *) abs=`pwd`"/$lib" ;; + esac + func_append newdlfiles " $abs" + done + dlfiles="$newdlfiles" + newdlprefiles= + for lib in $dlprefiles; do + case $lib in + [\\/]* | [A-Za-z]:[\\/]*) abs="$lib" ;; + *) abs=`pwd`"/$lib" ;; + esac + func_append newdlprefiles " $abs" + done + dlprefiles="$newdlprefiles" + fi + $RM $output + # place dlname in correct position for cygwin + # In fact, it would be nice if we could use this code for all target + # systems that can't hard-code library paths into their executables + # and that have no shared library path variable independent of PATH, + # but it turns out we can't easily determine that from inspecting + # libtool variables, so we have to hard-code the OSs to which it + # applies here; at the moment, that means platforms that use the PE + # object format with DLL files. See the long comment at the top of + # tests/bindir.at for full details. + tdlname=$dlname + case $host,$output,$installed,$module,$dlname in + *cygwin*,*lai,yes,no,*.dll | *mingw*,*lai,yes,no,*.dll | *cegcc*,*lai,yes,no,*.dll) + # If a -bindir argument was supplied, place the dll there. + if test "x$bindir" != x ; + then + func_relative_path "$install_libdir" "$bindir" + tdlname=$func_relative_path_result$dlname + else + # Otherwise fall back on heuristic. + tdlname=../bin/$dlname + fi + ;; + esac + $ECHO > $output "\ +# $outputname - a libtool library file +# Generated by $PROGRAM (GNU $PACKAGE$TIMESTAMP) $VERSION +# +# Please DO NOT delete this file! +# It is necessary for linking the library. + +# The name that we can dlopen(3). +dlname='$tdlname' + +# Names of this library. +library_names='$library_names' + +# The name of the static archive. +old_library='$old_library' + +# Linker flags that can not go in dependency_libs. +inherited_linker_flags='$new_inherited_linker_flags' + +# Libraries that this one depends upon. +dependency_libs='$dependency_libs' + +# Names of additional weak libraries provided by this library +weak_library_names='$weak_libs' + +# Version information for $libname. +current=$current +age=$age +revision=$revision + +# Is this an already installed library? +installed=$installed + +# Should we warn about portability when linking against -modules? +shouldnotlink=$module + +# Files to dlopen/dlpreopen +dlopen='$dlfiles' +dlpreopen='$dlprefiles' + +# Directory that this library needs to be installed in: +libdir='$install_libdir'" + if test "$installed" = no && test "$need_relink" = yes; then + $ECHO >> $output "\ +relink_command=\"$relink_command\"" + fi + done + } + + # Do a symbolic link so that the libtool archive can be found in + # LD_LIBRARY_PATH before the program is installed. + func_show_eval '( cd "$output_objdir" && $RM "$outputname" && $LN_S "../$outputname" "$outputname" )' 'exit $?' + ;; + esac + exit $EXIT_SUCCESS +} + +{ test "$opt_mode" = link || test "$opt_mode" = relink; } && + func_mode_link ${1+"$@"} + + +# func_mode_uninstall arg... +func_mode_uninstall () +{ + $opt_debug + RM="$nonopt" + files= + rmforce= + exit_status=0 + + # This variable tells wrapper scripts just to set variables rather + # than running their programs. + libtool_install_magic="$magic" + + for arg + do + case $arg in + -f) func_append RM " $arg"; rmforce=yes ;; + -*) func_append RM " $arg" ;; + *) func_append files " $arg" ;; + esac + done + + test -z "$RM" && \ + func_fatal_help "you must specify an RM program" + + rmdirs= + + for file in $files; do + func_dirname "$file" "" "." + dir="$func_dirname_result" + if test "X$dir" = X.; then + odir="$objdir" + else + odir="$dir/$objdir" + fi + func_basename "$file" + name="$func_basename_result" + test "$opt_mode" = uninstall && odir="$dir" + + # Remember odir for removal later, being careful to avoid duplicates + if test "$opt_mode" = clean; then + case " $rmdirs " in + *" $odir "*) ;; + *) func_append rmdirs " $odir" ;; + esac + fi + + # Don't error if the file doesn't exist and rm -f was used. + if { test -L "$file"; } >/dev/null 2>&1 || + { test -h "$file"; } >/dev/null 2>&1 || + test -f "$file"; then + : + elif test -d "$file"; then + exit_status=1 + continue + elif test "$rmforce" = yes; then + continue + fi + + rmfiles="$file" + + case $name in + *.la) + # Possibly a libtool archive, so verify it. + if func_lalib_p "$file"; then + func_source $dir/$name + + # Delete the libtool libraries and symlinks. + for n in $library_names; do + func_append rmfiles " $odir/$n" + done + test -n "$old_library" && func_append rmfiles " $odir/$old_library" + + case "$opt_mode" in + clean) + case " $library_names " in + *" $dlname "*) ;; + *) test -n "$dlname" && func_append rmfiles " $odir/$dlname" ;; + esac + test -n "$libdir" && func_append rmfiles " $odir/$name $odir/${name}i" + ;; + uninstall) + if test -n "$library_names"; then + # Do each command in the postuninstall commands. + func_execute_cmds "$postuninstall_cmds" 'test "$rmforce" = yes || exit_status=1' + fi + + if test -n "$old_library"; then + # Do each command in the old_postuninstall commands. + func_execute_cmds "$old_postuninstall_cmds" 'test "$rmforce" = yes || exit_status=1' + fi + # FIXME: should reinstall the best remaining shared library. + ;; + esac + fi + ;; + + *.lo) + # Possibly a libtool object, so verify it. + if func_lalib_p "$file"; then + + # Read the .lo file + func_source $dir/$name + + # Add PIC object to the list of files to remove. + if test -n "$pic_object" && + test "$pic_object" != none; then + func_append rmfiles " $dir/$pic_object" + fi + + # Add non-PIC object to the list of files to remove. + if test -n "$non_pic_object" && + test "$non_pic_object" != none; then + func_append rmfiles " $dir/$non_pic_object" + fi + fi + ;; + + *) + if test "$opt_mode" = clean ; then + noexename=$name + case $file in + *.exe) + func_stripname '' '.exe' "$file" + file=$func_stripname_result + func_stripname '' '.exe' "$name" + noexename=$func_stripname_result + # $file with .exe has already been added to rmfiles, + # add $file without .exe + func_append rmfiles " $file" + ;; + esac + # Do a test to see if this is a libtool program. + if func_ltwrapper_p "$file"; then + if func_ltwrapper_executable_p "$file"; then + func_ltwrapper_scriptname "$file" + relink_command= + func_source $func_ltwrapper_scriptname_result + func_append rmfiles " $func_ltwrapper_scriptname_result" + else + relink_command= + func_source $dir/$noexename + fi + + # note $name still contains .exe if it was in $file originally + # as does the version of $file that was added into $rmfiles + func_append rmfiles " $odir/$name $odir/${name}S.${objext}" + if test "$fast_install" = yes && test -n "$relink_command"; then + func_append rmfiles " $odir/lt-$name" + fi + if test "X$noexename" != "X$name" ; then + func_append rmfiles " $odir/lt-${noexename}.c" + fi + fi + fi + ;; + esac + func_show_eval "$RM $rmfiles" 'exit_status=1' + done + + # Try to remove the ${objdir}s in the directories where we deleted files + for dir in $rmdirs; do + if test -d "$dir"; then + func_show_eval "rmdir $dir >/dev/null 2>&1" + fi + done + + exit $exit_status +} + +{ test "$opt_mode" = uninstall || test "$opt_mode" = clean; } && + func_mode_uninstall ${1+"$@"} + +test -z "$opt_mode" && { + help="$generic_help" + func_fatal_help "you must specify a MODE" +} + +test -z "$exec_cmd" && \ + func_fatal_help "invalid operation mode \`$opt_mode'" + +if test -n "$exec_cmd"; then + eval exec "$exec_cmd" + exit $EXIT_FAILURE +fi + +exit $exit_status + + +# The TAGs below are defined such that we never get into a situation +# in which we disable both kinds of libraries. Given conflicting +# choices, we go for a static library, that is the most portable, +# since we can't tell whether shared libraries were disabled because +# the user asked for that or because the platform doesn't support +# them. This is particularly important on AIX, because we don't +# support having both static and shared libraries enabled at the same +# time on that platform, so we default to a shared-only configuration. +# If a disable-shared tag is given, we'll fallback to a static-only +# configuration. But we'll never go from static-only to shared-only. + +# ### BEGIN LIBTOOL TAG CONFIG: disable-shared +build_libtool_libs=no +build_old_libs=yes +# ### END LIBTOOL TAG CONFIG: disable-shared + +# ### BEGIN LIBTOOL TAG CONFIG: disable-static +build_old_libs=`case $build_libtool_libs in yes) echo no;; *) echo yes;; esac` +# ### END LIBTOOL TAG CONFIG: disable-static + +# Local Variables: +# mode:shell-script +# sh-indentation:2 +# End: +# vi:sw=2 + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/missing b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/missing new file mode 100644 index 0000000..db98974 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/missing @@ -0,0 +1,215 @@ +#! /bin/sh +# Common wrapper for a few potentially missing GNU programs. + +scriptversion=2013-10-28.13; # UTC + +# Copyright (C) 1996-2013 Free Software Foundation, Inc. +# Originally written by Fran,cois Pinard , 1996. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that program. + +if test $# -eq 0; then + echo 1>&2 "Try '$0 --help' for more information" + exit 1 +fi + +case $1 in + + --is-lightweight) + # Used by our autoconf macros to check whether the available missing + # script is modern enough. + exit 0 + ;; + + --run) + # Back-compat with the calling convention used by older automake. + shift + ;; + + -h|--h|--he|--hel|--help) + echo "\ +$0 [OPTION]... PROGRAM [ARGUMENT]... + +Run 'PROGRAM [ARGUMENT]...', returning a proper advice when this fails due +to PROGRAM being missing or too old. + +Options: + -h, --help display this help and exit + -v, --version output version information and exit + +Supported PROGRAM values: + aclocal autoconf autoheader autom4te automake makeinfo + bison yacc flex lex help2man + +Version suffixes to PROGRAM as well as the prefixes 'gnu-', 'gnu', and +'g' are ignored when checking the name. + +Send bug reports to ." + exit $? + ;; + + -v|--v|--ve|--ver|--vers|--versi|--versio|--version) + echo "missing $scriptversion (GNU Automake)" + exit $? + ;; + + -*) + echo 1>&2 "$0: unknown '$1' option" + echo 1>&2 "Try '$0 --help' for more information" + exit 1 + ;; + +esac + +# Run the given program, remember its exit status. +"$@"; st=$? + +# If it succeeded, we are done. +test $st -eq 0 && exit 0 + +# Also exit now if we it failed (or wasn't found), and '--version' was +# passed; such an option is passed most likely to detect whether the +# program is present and works. +case $2 in --version|--help) exit $st;; esac + +# Exit code 63 means version mismatch. This often happens when the user +# tries to use an ancient version of a tool on a file that requires a +# minimum version. +if test $st -eq 63; then + msg="probably too old" +elif test $st -eq 127; then + # Program was missing. + msg="missing on your system" +else + # Program was found and executed, but failed. Give up. + exit $st +fi + +perl_URL=http://www.perl.org/ +flex_URL=http://flex.sourceforge.net/ +gnu_software_URL=http://www.gnu.org/software + +program_details () +{ + case $1 in + aclocal|automake) + echo "The '$1' program is part of the GNU Automake package:" + echo "<$gnu_software_URL/automake>" + echo "It also requires GNU Autoconf, GNU m4 and Perl in order to run:" + echo "<$gnu_software_URL/autoconf>" + echo "<$gnu_software_URL/m4/>" + echo "<$perl_URL>" + ;; + autoconf|autom4te|autoheader) + echo "The '$1' program is part of the GNU Autoconf package:" + echo "<$gnu_software_URL/autoconf/>" + echo "It also requires GNU m4 and Perl in order to run:" + echo "<$gnu_software_URL/m4/>" + echo "<$perl_URL>" + ;; + esac +} + +give_advice () +{ + # Normalize program name to check for. + normalized_program=`echo "$1" | sed ' + s/^gnu-//; t + s/^gnu//; t + s/^g//; t'` + + printf '%s\n' "'$1' is $msg." + + configure_deps="'configure.ac' or m4 files included by 'configure.ac'" + case $normalized_program in + autoconf*) + echo "You should only need it if you modified 'configure.ac'," + echo "or m4 files included by it." + program_details 'autoconf' + ;; + autoheader*) + echo "You should only need it if you modified 'acconfig.h' or" + echo "$configure_deps." + program_details 'autoheader' + ;; + automake*) + echo "You should only need it if you modified 'Makefile.am' or" + echo "$configure_deps." + program_details 'automake' + ;; + aclocal*) + echo "You should only need it if you modified 'acinclude.m4' or" + echo "$configure_deps." + program_details 'aclocal' + ;; + autom4te*) + echo "You might have modified some maintainer files that require" + echo "the 'autom4te' program to be rebuilt." + program_details 'autom4te' + ;; + bison*|yacc*) + echo "You should only need it if you modified a '.y' file." + echo "You may want to install the GNU Bison package:" + echo "<$gnu_software_URL/bison/>" + ;; + lex*|flex*) + echo "You should only need it if you modified a '.l' file." + echo "You may want to install the Fast Lexical Analyzer package:" + echo "<$flex_URL>" + ;; + help2man*) + echo "You should only need it if you modified a dependency" \ + "of a man page." + echo "You may want to install the GNU Help2man package:" + echo "<$gnu_software_URL/help2man/>" + ;; + makeinfo*) + echo "You should only need it if you modified a '.texi' file, or" + echo "any other file indirectly affecting the aspect of the manual." + echo "You might want to install the Texinfo package:" + echo "<$gnu_software_URL/texinfo/>" + echo "The spurious makeinfo call might also be the consequence of" + echo "using a buggy 'make' (AIX, DU, IRIX), in which case you might" + echo "want to install GNU make:" + echo "<$gnu_software_URL/make/>" + ;; + *) + echo "You might have modified some files without having the proper" + echo "tools for further handling them. Check the 'README' file, it" + echo "often tells you about the needed prerequisites for installing" + echo "this package. You may also peek at any GNU archive site, in" + echo "case some other package contains this missing '$1' program." + ;; + esac +} + +give_advice "$1" | sed -e '1s/^/WARNING: /' \ + -e '2,$s/^/ /' >&2 + +# Propagate the correct exit status (expected to be 127 for a program +# not found, 63 for a program that failed due to version mismatch). +exit $st + +# Local variables: +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "scriptversion=" +# time-stamp-format: "%:y-%02m-%02d.%02H" +# time-stamp-time-zone: "UTC" +# time-stamp-end: "; # UTC" +# End: diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/test-driver b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/test-driver new file mode 100644 index 0000000..d306056 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/build-aux/test-driver @@ -0,0 +1,139 @@ +#! /bin/sh +# test-driver - basic testsuite driver script. + +scriptversion=2013-07-13.22; # UTC + +# Copyright (C) 2011-2013 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that program. + +# This file is maintained in Automake, please report +# bugs to or send patches to +# . + +# Make unconditional expansion of undefined variables an error. This +# helps a lot in preventing typo-related bugs. +set -u + +usage_error () +{ + echo "$0: $*" >&2 + print_usage >&2 + exit 2 +} + +print_usage () +{ + cat <$log_file 2>&1 +estatus=$? +if test $enable_hard_errors = no && test $estatus -eq 99; then + estatus=1 +fi + +case $estatus:$expect_failure in + 0:yes) col=$red res=XPASS recheck=yes gcopy=yes;; + 0:*) col=$grn res=PASS recheck=no gcopy=no;; + 77:*) col=$blu res=SKIP recheck=no gcopy=yes;; + 99:*) col=$mgn res=ERROR recheck=yes gcopy=yes;; + *:yes) col=$lgn res=XFAIL recheck=no gcopy=yes;; + *:*) col=$red res=FAIL recheck=yes gcopy=yes;; +esac + +# Report outcome to console. +echo "${col}${res}${std}: $test_name" + +# Register the test result, and other relevant metadata. +echo ":test-result: $res" > $trs_file +echo ":global-test-result: $res" >> $trs_file +echo ":recheck: $recheck" >> $trs_file +echo ":copy-in-global-log: $gcopy" >> $trs_file + +# Local Variables: +# mode: shell-script +# sh-indentation: 2 +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "scriptversion=" +# time-stamp-format: "%:y-%02m-%02d.%02H" +# time-stamp-time-zone: "UTC" +# time-stamp-end: "; # UTC" +# End: diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/client-cert.der b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/client-cert.der new file mode 100644 index 0000000..c2bd6df Binary files /dev/null and b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/client-cert.der differ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/client-cert.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/client-cert.pem new file mode 100644 index 0000000..2f13e8e --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/client-cert.pem @@ -0,0 +1,66 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 16417767964199037690 (0xe3d7a0fa76df2afa) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C=US, ST=Montana, L=Bozeman, O=wolfSSL_1024, OU=Programming-1024, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Validity + Not Before: May 7 18:21:01 2015 GMT + Not After : Jan 31 18:21:01 2018 GMT + Subject: C=US, ST=Montana, L=Bozeman, O=wolfSSL_1024, OU=Programming-1024, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (1024 bit) + Modulus: + 00:bc:73:0e:a8:49:f3:74:a2:a9:ef:18:a5:da:55: + 99:21:f9:c8:ec:b3:6d:48:e5:35:35:75:77:37:ec: + d1:61:90:5f:3e:d9:e4:d5:df:94:ca:c1:a9:d7:19: + da:86:c9:e8:4d:c4:61:36:82:fe:ab:ad:7e:77:25: + bb:8d:11:a5:bc:62:3a:a8:38:cc:39:a2:04:66:b4: + f7:f7:f3:aa:da:4d:02:0e:bb:5e:8d:69:48:dc:77: + c9:28:0e:22:e9:6b:a4:26:ba:4c:e8:c1:fd:4a:6f: + 2b:1f:ef:8a:ae:f6:90:62:e5:64:1e:eb:2b:3c:67: + c8:dc:27:00:f6:91:68:65:a9 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Subject Key Identifier: + 81:69:0F:F8:DF:DD:CF:34:29:D5:67:75:71:85:C7:75:10:69:59:EC + X509v3 Authority Key Identifier: + keyid:81:69:0F:F8:DF:DD:CF:34:29:D5:67:75:71:85:C7:75:10:69:59:EC + DirName:/C=US/ST=Montana/L=Bozeman/O=wolfSSL_1024/OU=Programming-1024/CN=www.wolfssl.com/emailAddress=info@wolfssl.com + serial:E3:D7:A0:FA:76:DF:2A:FA + + X509v3 Basic Constraints: + CA:TRUE + Signature Algorithm: sha256WithRSAEncryption + 1d:b7:d5:7c:e1:b1:d8:c0:67:5d:b5:d3:88:e7:50:29:71:63: + 8f:cc:26:1f:33:09:55:43:9b:ab:c6:1b:bc:c7:01:95:1a:fa: + 65:e0:fd:9c:eb:6f:0a:0f:14:ec:b5:2f:dc:1c:30:dd:52:97: + d4:1c:09:00:33:38:5f:cb:a8:16:8f:11:b7:b8:d0:66:e1:54: + 28:f3:3f:bf:6a:6f:76:48:2a:5e:56:a7:ce:1c:f0:04:dd:17: + bd:06:78:21:6d:d6:b1:9b:75:31:92:c1:fe:d4:8d:d4:67:2f: + 03:1b:27:8d:ab:ff:30:3b:c3:7f:23:e4:ab:5b:91:e1:1b:66: + e6:ed +-----BEGIN CERTIFICATE----- +MIIDxTCCAy6gAwIBAgIJAOPXoPp23yr6MA0GCSqGSIb3DQEBCwUAMIGeMQswCQYD +VQQGEwJVUzEQMA4GA1UECAwHTW9udGFuYTEQMA4GA1UEBwwHQm96ZW1hbjEVMBMG +A1UECgwMd29sZlNTTF8xMDI0MRkwFwYDVQQLDBBQcm9ncmFtbWluZy0xMDI0MRgw +FgYDVQQDDA93d3cud29sZnNzbC5jb20xHzAdBgkqhkiG9w0BCQEWEGluZm9Ad29s +ZnNzbC5jb20wHhcNMTUwNTA3MTgyMTAxWhcNMTgwMTMxMTgyMTAxWjCBnjELMAkG +A1UEBhMCVVMxEDAOBgNVBAgMB01vbnRhbmExEDAOBgNVBAcMB0JvemVtYW4xFTAT +BgNVBAoMDHdvbGZTU0xfMTAyNDEZMBcGA1UECwwQUHJvZ3JhbW1pbmctMTAyNDEY +MBYGA1UEAwwPd3d3LndvbGZzc2wuY29tMR8wHQYJKoZIhvcNAQkBFhBpbmZvQHdv +bGZzc2wuY29tMIGfMA0GCSqGSIb3DQEBAQUAA4GNADCBiQKBgQC8cw6oSfN0oqnv +GKXaVZkh+cjss21I5TU1dXc37NFhkF8+2eTV35TKwanXGdqGyehNxGE2gv6rrX53 +JbuNEaW8YjqoOMw5ogRmtPf386raTQIOu16NaUjcd8koDiLpa6Qmukzowf1Kbysf +74qu9pBi5WQe6ys8Z8jcJwD2kWhlqQIDAQABo4IBBzCCAQMwHQYDVR0OBBYEFIFp +D/jf3c80KdVndXGFx3UQaVnsMIHTBgNVHSMEgcswgciAFIFpD/jf3c80KdVndXGF +x3UQaVnsoYGkpIGhMIGeMQswCQYDVQQGEwJVUzEQMA4GA1UECAwHTW9udGFuYTEQ +MA4GA1UEBwwHQm96ZW1hbjEVMBMGA1UECgwMd29sZlNTTF8xMDI0MRkwFwYDVQQL +DBBQcm9ncmFtbWluZy0xMDI0MRgwFgYDVQQDDA93d3cud29sZnNzbC5jb20xHzAd +BgkqhkiG9w0BCQEWEGluZm9Ad29sZnNzbC5jb22CCQDj16D6dt8q+jAMBgNVHRME +BTADAQH/MA0GCSqGSIb3DQEBCwUAA4GBAB231XzhsdjAZ12104jnUClxY4/MJh8z +CVVDm6vGG7zHAZUa+mXg/ZzrbwoPFOy1L9wcMN1Sl9QcCQAzOF/LqBaPEbe40Gbh +VCjzP79qb3ZIKl5Wp84c8ATdF70GeCFt1rGbdTGSwf7UjdRnLwMbJ42r/zA7w38j +5KtbkeEbZubt +-----END CERTIFICATE----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/client-key.der b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/client-key.der new file mode 100644 index 0000000..1c47c25 Binary files /dev/null and b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/client-key.der differ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/client-key.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/client-key.pem new file mode 100644 index 0000000..79e398c --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/client-key.pem @@ -0,0 +1,15 @@ +-----BEGIN RSA PRIVATE KEY----- +MIICXAIBAAKBgQC8cw6oSfN0oqnvGKXaVZkh+cjss21I5TU1dXc37NFhkF8+2eTV +35TKwanXGdqGyehNxGE2gv6rrX53JbuNEaW8YjqoOMw5ogRmtPf386raTQIOu16N +aUjcd8koDiLpa6Qmukzowf1Kbysf74qu9pBi5WQe6ys8Z8jcJwD2kWhlqQIDAQAB +AoGAE5fq6Dh4JaJcBM4NQHwx5cRwzZuCO1gJhjtmX9wxkPFP1dsV3d7XO5WTMRgx +Dl6j1qIacW6BSBxLz9uOeoZhMtz7VcEWbSeSJEWL8bhIsUsdrN7a3Y4vwpH7palu ++Dpq8f1QGO+f58PKeOpW09NyW5bdTgZOOsPZvnK2ZQcHTAECQQD6R9R6fJI8Ve+B +8EEwLaPPjxzmhycFcA3fmDXW8Ys4LyS10IS2eU9xKZRa8GRqrOdyxu1NWZg+Zzrz +dCz5YRdpAkEAwMGCDQzrxi/ckvmdghox6en3S/KChxzuFmrRHRiCcPPAti/28/cd +8YYjyE7rj1aOj/W/8fcrtcw9xlc5DBtUQQJBAJ1+Bd7t9Ley+/wwS1Ud4y8BR5Zp +Bc0OLiy9g2O2q3y3bcpbZKfOvobfO1PeYdIe66X2N+2sq3jZTOdV+9cRmcECQBiY +GCnmHic5cCForAovoXLBIYaVOMZYkKBXnLrjp7EVyN72G8JhI3bvsJ0cRL4TQzln +F8idyvv1RWSLOIIs8oECQDmJ5ZwZVTC6t0iMSBQO9J9+d5dD4bQZNTEjdZw7RK1p +ElbuAGFkFmbTfHQrFbSi/r8IaxpdP5ASsQWGMSnb2eI= +-----END RSA PRIVATE KEY----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/dh1024.der b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/dh1024.der new file mode 100644 index 0000000..f29e6dc Binary files /dev/null and b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/dh1024.der differ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/dh1024.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/dh1024.pem new file mode 100644 index 0000000..372f50a --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/dh1024.pem @@ -0,0 +1,17 @@ + PKCS#3 DH Parameters: (1024 bit) + prime: + 00:a4:d2:b8:6e:78:f5:d9:ed:2d:7c:dd:b6:16:86: + 5a:4b:05:76:90:dd:66:61:b9:6d:52:a7:1c:af:62: + c6:69:47:7b:39:f2:fb:94:ec:bc:79:ff:24:5e:ef: + 79:bb:59:b2:fc:ca:07:d6:f4:e9:34:f7:e8:38:e7: + d7:33:44:1d:a3:64:76:1a:84:97:54:74:40:84:1f: + 15:fe:7c:25:2a:2b:25:fd:9e:c1:89:33:8c:39:25: + 2b:40:e6:cd:f8:a8:a1:8a:53:c6:47:b2:a0:d7:8f: + eb:2e:60:0a:0d:4b:f8:b4:94:8c:63:0a:ad:c7:10: + ea:c7:a1:b9:9d:f2:a8:37:73 + generator: 2 (0x2) +-----BEGIN DH PARAMETERS----- +MIGHAoGBAKTSuG549dntLXzdthaGWksFdpDdZmG5bVKnHK9ixmlHezny+5TsvHn/ +JF7vebtZsvzKB9b06TT36Djn1zNEHaNkdhqEl1R0QIQfFf58JSorJf2ewYkzjDkl +K0DmzfiooYpTxkeyoNeP6y5gCg1L+LSUjGMKrccQ6sehuZ3yqDdzAgEC +-----END DH PARAMETERS----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/dsa1024.der b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/dsa1024.der new file mode 100644 index 0000000..65db155 Binary files /dev/null and b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/dsa1024.der differ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/dsa1024.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/dsa1024.pem new file mode 100644 index 0000000..c5bb067 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/dsa1024.pem @@ -0,0 +1,12 @@ +-----BEGIN DSA PRIVATE KEY----- +MIIBvAIBAAKBgQD3S/m7FZjr3d4eTnGIhfK3uuJK2nZAzWlInoN8EfdlMXj1JS33 +t/hSP77YtsX+GBVbudWShryyF3zYsL6gfPLVc3pYj43lSgCZg0rAnhYJoRA01Rm7 +Y+Pdg3R/EMpzde4xSt2f4AJqne6yS6drKmzHhnfoBBXckrR6KR9Og2OFVQIVANIF +5HP7wZnF3GikjZInPeJSX4mLAoGBAKohAglDbvuiVBSFCvQofMvM2/UeohipId6I +iDOMLuuNo/AdyI/2fvjPEvW0oRFvDNTwBq3E/BRFx5QVvBlLru+Tak/MFNhHizlm +hwLUKAq47gk39ACgBKd5p9I89zRDVo7QfMLYTQ+J7RTBLJxMGZue3FMJn98t8Awn +VDp3FC3eAoGBAOgffLfAVFGnKC1YfN7UXN3VdoQ8NiDAwyXXOjjhVMj9QGgaIVQm +ORS/9qOcXtkr98klugAJy38MSiT9FRYVSM0LUkRAe5BjK5AixRgFgFOvgx9U4rCi +C1qSJOFiKD+3yrmJ1qC3ra4F4cFZQO1KG2ine/vDIIHvS/NpkbDOOrA4AhQlODuh +GXXfm/VyU0854RzsE4SCGA== +-----END DSA PRIVATE KEY----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/include.am new file mode 100644 index 0000000..c968497 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/include.am @@ -0,0 +1,17 @@ +# vim:ft=automake +# All paths should be given relative to the root +# + +EXTRA_DIST += \ + certs/1024/client-cert.pem \ + certs/1024/client-key.pem \ + certs/1024/dh1024.pem \ + certs/1024/dsa1024.pem + +EXTRA_DIST += \ + certs/1024/client-cert.der \ + certs/1024/client-key.der \ + certs/1024/dh1024.der \ + certs/1024/dsa1024.der \ + certs/1024/rsa1024.der + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/rsa1024.der b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/rsa1024.der new file mode 100644 index 0000000..173d32b Binary files /dev/null and b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/1024/rsa1024.der differ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ca-cert.der b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ca-cert.der new file mode 100644 index 0000000..d0eab7a Binary files /dev/null and b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ca-cert.der differ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ca-cert.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ca-cert.pem new file mode 100644 index 0000000..6eacbeb --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ca-cert.pem @@ -0,0 +1,86 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 15672591315981621815 (0xd9803ac3d2f4da37) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C=US, ST=Montana, L=Bozeman, O=Sawtooth, OU=Consulting, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Validity + Not Before: May 7 18:21:01 2015 GMT + Not After : Jan 31 18:21:01 2018 GMT + Subject: C=US, ST=Montana, L=Bozeman, O=Sawtooth, OU=Consulting, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:bf:0c:ca:2d:14:b2:1e:84:42:5b:cd:38:1f:4a: + f2:4d:75:10:f1:b6:35:9f:df:ca:7d:03:98:d3:ac: + de:03:66:ee:2a:f1:d8:b0:7d:6e:07:54:0b:10:98: + 21:4d:80:cb:12:20:e7:cc:4f:de:45:7d:c9:72:77: + 32:ea:ca:90:bb:69:52:10:03:2f:a8:f3:95:c5:f1: + 8b:62:56:1b:ef:67:6f:a4:10:41:95:ad:0a:9b:e3: + a5:c0:b0:d2:70:76:50:30:5b:a8:e8:08:2c:7c:ed: + a7:a2:7a:8d:38:29:1c:ac:c7:ed:f2:7c:95:b0:95: + 82:7d:49:5c:38:cd:77:25:ef:bd:80:75:53:94:3c: + 3d:ca:63:5b:9f:15:b5:d3:1d:13:2f:19:d1:3c:db: + 76:3a:cc:b8:7d:c9:e5:c2:d7:da:40:6f:d8:21:dc: + 73:1b:42:2d:53:9c:fe:1a:fc:7d:ab:7a:36:3f:98: + de:84:7c:05:67:ce:6a:14:38:87:a9:f1:8c:b5:68: + cb:68:7f:71:20:2b:f5:a0:63:f5:56:2f:a3:26:d2: + b7:6f:b1:5a:17:d7:38:99:08:fe:93:58:6f:fe:c3: + 13:49:08:16:0b:a7:4d:67:00:52:31:67:23:4e:98: + ed:51:45:1d:b9:04:d9:0b:ec:d8:28:b3:4b:bd:ed: + 36:79 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Subject Key Identifier: + 27:8E:67:11:74:C3:26:1D:3F:ED:33:63:B3:A4:D8:1D:30:E5:E8:D5 + X509v3 Authority Key Identifier: + keyid:27:8E:67:11:74:C3:26:1D:3F:ED:33:63:B3:A4:D8:1D:30:E5:E8:D5 + DirName:/C=US/ST=Montana/L=Bozeman/O=Sawtooth/OU=Consulting/CN=www.wolfssl.com/emailAddress=info@wolfssl.com + serial:D9:80:3A:C3:D2:F4:DA:37 + + X509v3 Basic Constraints: + CA:TRUE + Signature Algorithm: sha256WithRSAEncryption + 7a:af:44:3b:aa:6f:53:42:b2:33:aa:43:5f:56:30:d3:b9:96: + 0b:9a:55:5a:39:2a:0b:4e:e4:2e:f1:95:66:c9:86:36:82:8d: + 63:7c:4d:a2:ee:48:ba:03:c7:90:d7:a7:c6:74:60:48:5f:31: + a2:f9:5e:3e:c3:82:e1:e5:2f:41:81:83:29:25:79:d1:53:00: + 69:3c:ed:0a:30:3b:41:1d:92:a1:2c:a8:9d:2c:e3:23:87:79: + e0:55:6e:91:a8:50:da:46:2f:c2:20:50:3e:2b:47:97:14:b0: + 7d:04:ba:45:51:d0:6e:e1:5a:a2:4b:84:9c:4d:cd:85:04:f9: + 28:31:82:93:bc:c7:59:49:91:03:e8:df:6a:e4:56:ad:6a:cb: + 1f:0d:37:e4:5e:bd:e7:9f:d5:ec:9d:3c:18:25:9b:f1:2f:50: + 7d:eb:31:cb:f1:63:22:9d:57:fc:f3:84:20:1a:c6:07:87:92: + 26:9e:15:18:59:33:06:dc:fb:b0:b6:76:5d:f1:c1:2f:c8:2f: + 62:9c:c0:d6:de:eb:65:77:f3:5c:a6:c3:88:27:96:75:b4:f4: + 54:cd:ff:2d:21:2e:96:f0:07:73:4b:e9:93:92:90:de:62:d9: + a3:3b:ac:6e:24:5f:27:4a:b3:94:70:ff:30:17:e7:7e:32:8f: + 65:b7:75:58 +-----BEGIN CERTIFICATE----- +MIIEqjCCA5KgAwIBAgIJANmAOsPS9No3MA0GCSqGSIb3DQEBCwUAMIGUMQswCQYD +VQQGEwJVUzEQMA4GA1UECAwHTW9udGFuYTEQMA4GA1UEBwwHQm96ZW1hbjERMA8G +A1UECgwIU2F3dG9vdGgxEzARBgNVBAsMCkNvbnN1bHRpbmcxGDAWBgNVBAMMD3d3 +dy53b2xmc3NsLmNvbTEfMB0GCSqGSIb3DQEJARYQaW5mb0B3b2xmc3NsLmNvbTAe +Fw0xNTA1MDcxODIxMDFaFw0xODAxMzExODIxMDFaMIGUMQswCQYDVQQGEwJVUzEQ +MA4GA1UECAwHTW9udGFuYTEQMA4GA1UEBwwHQm96ZW1hbjERMA8GA1UECgwIU2F3 +dG9vdGgxEzARBgNVBAsMCkNvbnN1bHRpbmcxGDAWBgNVBAMMD3d3dy53b2xmc3Ns +LmNvbTEfMB0GCSqGSIb3DQEJARYQaW5mb0B3b2xmc3NsLmNvbTCCASIwDQYJKoZI +hvcNAQEBBQADggEPADCCAQoCggEBAL8Myi0Ush6EQlvNOB9K8k11EPG2NZ/fyn0D +mNOs3gNm7irx2LB9bgdUCxCYIU2AyxIg58xP3kV9yXJ3MurKkLtpUhADL6jzlcXx +i2JWG+9nb6QQQZWtCpvjpcCw0nB2UDBbqOgILHztp6J6jTgpHKzH7fJ8lbCVgn1J +XDjNdyXvvYB1U5Q8PcpjW58VtdMdEy8Z0TzbdjrMuH3J5cLX2kBv2CHccxtCLVOc +/hr8fat6Nj+Y3oR8BWfOahQ4h6nxjLVoy2h/cSAr9aBj9VYvoybSt2+xWhfXOJkI +/pNYb/7DE0kIFgunTWcAUjFnI06Y7VFFHbkE2Qvs2CizS73tNnkCAwEAAaOB/DCB ++TAdBgNVHQ4EFgQUJ45nEXTDJh0/7TNjs6TYHTDl6NUwgckGA1UdIwSBwTCBvoAU +J45nEXTDJh0/7TNjs6TYHTDl6NWhgZqkgZcwgZQxCzAJBgNVBAYTAlVTMRAwDgYD +VQQIDAdNb250YW5hMRAwDgYDVQQHDAdCb3plbWFuMREwDwYDVQQKDAhTYXd0b290 +aDETMBEGA1UECwwKQ29uc3VsdGluZzEYMBYGA1UEAwwPd3d3LndvbGZzc2wuY29t +MR8wHQYJKoZIhvcNAQkBFhBpbmZvQHdvbGZzc2wuY29tggkA2YA6w9L02jcwDAYD +VR0TBAUwAwEB/zANBgkqhkiG9w0BAQsFAAOCAQEAeq9EO6pvU0KyM6pDX1Yw07mW +C5pVWjkqC07kLvGVZsmGNoKNY3xNou5IugPHkNenxnRgSF8xovlePsOC4eUvQYGD +KSV50VMAaTztCjA7QR2SoSyonSzjI4d54FVukahQ2kYvwiBQPitHlxSwfQS6RVHQ +buFaokuEnE3NhQT5KDGCk7zHWUmRA+jfauRWrWrLHw035F6955/V7J08GCWb8S9Q +fesxy/FjIp1X/POEIBrGB4eSJp4VGFkzBtz7sLZ2XfHBL8gvYpzA1t7rZXfzXKbD +iCeWdbT0VM3/LSEulvAHc0vpk5KQ3mLZozusbiRfJ0qzlHD/MBfnfjKPZbd1WA== +-----END CERTIFICATE----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ca-key.der b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ca-key.der new file mode 100644 index 0000000..14456f3 Binary files /dev/null and b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ca-key.der differ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ca-key.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ca-key.pem new file mode 100644 index 0000000..774feba --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ca-key.pem @@ -0,0 +1,27 @@ +-----BEGIN RSA PRIVATE KEY----- +MIIEpAIBAAKCAQEAvwzKLRSyHoRCW804H0ryTXUQ8bY1n9/KfQOY06zeA2buKvHY +sH1uB1QLEJghTYDLEiDnzE/eRX3Jcncy6sqQu2lSEAMvqPOVxfGLYlYb72dvpBBB +la0Km+OlwLDScHZQMFuo6AgsfO2nonqNOCkcrMft8nyVsJWCfUlcOM13Je+9gHVT +lDw9ymNbnxW10x0TLxnRPNt2Osy4fcnlwtfaQG/YIdxzG0ItU5z+Gvx9q3o2P5je +hHwFZ85qFDiHqfGMtWjLaH9xICv1oGP1Vi+jJtK3b7FaF9c4mQj+k1hv/sMTSQgW +C6dNZwBSMWcjTpjtUUUduQTZC+zYKLNLve02eQIDAQABAoIBAD1uTmAahH+dhXzh +Swd84NaZKt6d+TY0DncOPgjqT+UGJtT2OPffDQ8cLgai9CponGNy4zXmBJGRtcGx +pFSs18b7QaDWdW+9C06/sVLoX0kmmFZHx97p6jxgAb8o3DG/SV+TSYd6gVuWS03K +XDhPt+Gy08ch2jwShwfkG9xD7OjsVGHn9u2mCy7134J/xh9hGZykgznfIYWJb3ev +hhUyCKJaCyZh+3AMypw4fbwi7uujqBYA+YqAHgCEqEpB+IQDZy8jWy+baybDBzSU +owM7ctWfcuCtzDSrvcfV9SYwhQ8wIzlS/zzLmSFNiKWr7mK5x+C7R4fBac9z8zC+ +zjkEnOUCgYEA4XZFgFm200nfCu8S1g/wt8sqN7+n+LVN9TE1reSjlKHb8ZattQVk +hYP8G1spqr74Jj92fq0c8MvXJrQbBY5Whn4IYiHBhtZHeT63XaTGOtexdCD2UJdB +BFPtPybWb5H6aCbsKtya8efc+3PweUMbIaNZBGNSB8nX5tEbXV6W+lMCgYEA2O1O +ZGFrkQxhAbUPu0RnUx7cB8Qkfp5shCORDOQSBBZNeJjMlj0gTg9Fmrb4s5MNsqIb +KfImecjF0nh+XnPy13Bhu0DOYQX+aR6CKeYUuKHnltAjPwWTAPLhTX7tt5Zs9/Dk +0c8BmE/cdFSqbV5aQTH+/5q2oAXdqRBU+GvQqoMCgYAh0wSKROtQt3xmv4cr5ihO +6oPi6TXh8hFH/6H1/J8t5TqB/AEDb1OtVCe2Uu7lVtETq+GzD3WQCoS0ocCMDNae +RrorPrUx7WO7pNUNj3LN0R4mNeu+G3L9mzm0h7cT9eqDRZOYuo/kSsy0TKh/CLpB +SahJKD1ePcHONwDL+SzdUQKBgQChV58+udavg22DP4/70NyozgMJI7GhG2PKxElW +NSvRLmVglQVVmRE1/dXfRMeliHJfsoJRqHFFkzbPXB9hUQwFgOivxXu6XiLjPHXD +hAVVbdY6LYSJkzPLONqqMQXNzmwt3VXTVwvwpTVqsK4xukOWygDHS+MZEkPTQvpv +6oDA0QKBgQC524kgNCdwYjTqXyViEvOdgb9I7poOwY0Q/2WanS0aipRayMClpYRh +ntQkue+pncl3C8dwZj26yFTf0jPh9X/5J2G+V0Xdt0UXJPUj5DgOkSfu4yDYFMiU +R3dAd0UYng3OeT9XMVYJSWe+lFhP9sSr4onj44rABVUsJMBKlwQnmg== +-----END RSA PRIVATE KEY----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/client-cert.der b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/client-cert.der new file mode 100644 index 0000000..9a7e0bf Binary files /dev/null and b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/client-cert.der differ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/client-cert.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/client-cert.pem new file mode 100644 index 0000000..569cddd --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/client-cert.pem @@ -0,0 +1,87 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 12260966172072242701 (0xaa27b3c5a9726e0d) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C=US, ST=Montana, L=Bozeman, O=wolfSSL_2048, OU=Programming-2048, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Validity + Not Before: May 7 18:21:01 2015 GMT + Not After : Jan 31 18:21:01 2018 GMT + Subject: C=US, ST=Montana, L=Bozeman, O=wolfSSL_2048, OU=Programming-2048, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:c3:03:d1:2b:fe:39:a4:32:45:3b:53:c8:84:2b: + 2a:7c:74:9a:bd:aa:2a:52:07:47:d6:a6:36:b2:07: + 32:8e:d0:ba:69:7b:c6:c3:44:9e:d4:81:48:fd:2d: + 68:a2:8b:67:bb:a1:75:c8:36:2c:4a:d2:1b:f7:8b: + ba:cf:0d:f9:ef:ec:f1:81:1e:7b:9b:03:47:9a:bf: + 65:cc:7f:65:24:69:a6:e8:14:89:5b:e4:34:f7:c5: + b0:14:93:f5:67:7b:3a:7a:78:e1:01:56:56:91:a6: + 13:42:8d:d2:3c:40:9c:4c:ef:d1:86:df:37:51:1b: + 0c:a1:3b:f5:f1:a3:4a:35:e4:e1:ce:96:df:1b:7e: + bf:4e:97:d0:10:e8:a8:08:30:81:af:20:0b:43:14: + c5:74:67:b4:32:82:6f:8d:86:c2:88:40:99:36:83: + ba:1e:40:72:22:17:d7:52:65:24:73:b0:ce:ef:19: + cd:ae:ff:78:6c:7b:c0:12:03:d4:4e:72:0d:50:6d: + 3b:a3:3b:a3:99:5e:9d:c8:d9:0c:85:b3:d9:8a:d9: + 54:26:db:6d:fa:ac:bb:ff:25:4c:c4:d1:79:f4:71: + d3:86:40:18:13:b0:63:b5:72:4e:30:c4:97:84:86: + 2d:56:2f:d7:15:f7:7f:c0:ae:f5:fc:5b:e5:fb:a1: + ba:d3 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Subject Key Identifier: + 33:D8:45:66:D7:68:87:18:7E:54:0D:70:27:91:C7:26:D7:85:65:C0 + X509v3 Authority Key Identifier: + keyid:33:D8:45:66:D7:68:87:18:7E:54:0D:70:27:91:C7:26:D7:85:65:C0 + DirName:/C=US/ST=Montana/L=Bozeman/O=wolfSSL_2048/OU=Programming-2048/CN=www.wolfssl.com/emailAddress=info@wolfssl.com + serial:AA:27:B3:C5:A9:72:6E:0D + + X509v3 Basic Constraints: + CA:TRUE + Signature Algorithm: sha256WithRSAEncryption + 51:96:a7:1c:26:5d:1c:90:c6:32:9f:96:15:f2:1d:e7:93:9c: + ac:75:56:95:fd:20:70:ab:45:6a:09:b0:f3:f2:03:a8:db:dc: + 2f:bc:1f:87:7a:a3:d4:8f:d5:49:97:7e:3c:54:ac:b1:e3:f0: + 39:0d:fe:09:9a:23:f6:32:a6:41:59:bd:60:e8:bd:de:00:36: + 6f:3e:e9:41:6f:a9:63:c7:aa:d5:7b:f3:e4:39:48:9e:f6:60: + c6:c6:86:d5:72:86:23:cd:f5:6a:63:53:a4:f8:fc:51:6a:cd: + 60:74:8e:a3:86:61:01:34:78:f7:29:97:b3:a7:34:b6:0a:de: + b5:71:7a:09:a6:3e:d6:82:58:89:67:9c:c5:68:62:ba:06:d6: + 39:bb:cb:3a:c0:e0:63:1f:c7:0c:9c:12:86:ec:f7:39:6a:61: + 93:d0:33:14:c6:55:3b:b6:cf:80:5b:8c:43:ef:43:44:0b:3c: + 93:39:a3:4e:15:d1:0b:5f:84:98:1d:cd:9f:a9:47:eb:3b:56: + 30:b6:76:92:c1:48:5f:bc:95:b0:50:1a:55:c8:4e:62:47:87: + 54:64:0c:9b:91:fa:43:b3:29:48:be:e6:12:eb:e3:44:c6:52: + e4:40:c6:83:95:1b:a7:65:27:69:73:2f:c8:a0:4d:7f:be:ea: + 9b:67:b2:7b +-----BEGIN CERTIFICATE----- +MIIEyjCCA7KgAwIBAgIJAKons8Wpcm4NMA0GCSqGSIb3DQEBCwUAMIGeMQswCQYD +VQQGEwJVUzEQMA4GA1UECAwHTW9udGFuYTEQMA4GA1UEBwwHQm96ZW1hbjEVMBMG +A1UECgwMd29sZlNTTF8yMDQ4MRkwFwYDVQQLDBBQcm9ncmFtbWluZy0yMDQ4MRgw +FgYDVQQDDA93d3cud29sZnNzbC5jb20xHzAdBgkqhkiG9w0BCQEWEGluZm9Ad29s +ZnNzbC5jb20wHhcNMTUwNTA3MTgyMTAxWhcNMTgwMTMxMTgyMTAxWjCBnjELMAkG +A1UEBhMCVVMxEDAOBgNVBAgMB01vbnRhbmExEDAOBgNVBAcMB0JvemVtYW4xFTAT +BgNVBAoMDHdvbGZTU0xfMjA0ODEZMBcGA1UECwwQUHJvZ3JhbW1pbmctMjA0ODEY +MBYGA1UEAwwPd3d3LndvbGZzc2wuY29tMR8wHQYJKoZIhvcNAQkBFhBpbmZvQHdv +bGZzc2wuY29tMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAwwPRK/45 +pDJFO1PIhCsqfHSavaoqUgdH1qY2sgcyjtC6aXvGw0Se1IFI/S1oootnu6F1yDYs +StIb94u6zw357+zxgR57mwNHmr9lzH9lJGmm6BSJW+Q098WwFJP1Z3s6enjhAVZW +kaYTQo3SPECcTO/Rht83URsMoTv18aNKNeThzpbfG36/TpfQEOioCDCBryALQxTF +dGe0MoJvjYbCiECZNoO6HkByIhfXUmUkc7DO7xnNrv94bHvAEgPUTnINUG07ozuj +mV6dyNkMhbPZitlUJttt+qy7/yVMxNF59HHThkAYE7BjtXJOMMSXhIYtVi/XFfd/ +wK71/Fvl+6G60wIDAQABo4IBBzCCAQMwHQYDVR0OBBYEFDPYRWbXaIcYflQNcCeR +xybXhWXAMIHTBgNVHSMEgcswgciAFDPYRWbXaIcYflQNcCeRxybXhWXAoYGkpIGh +MIGeMQswCQYDVQQGEwJVUzEQMA4GA1UECAwHTW9udGFuYTEQMA4GA1UEBwwHQm96 +ZW1hbjEVMBMGA1UECgwMd29sZlNTTF8yMDQ4MRkwFwYDVQQLDBBQcm9ncmFtbWlu +Zy0yMDQ4MRgwFgYDVQQDDA93d3cud29sZnNzbC5jb20xHzAdBgkqhkiG9w0BCQEW +EGluZm9Ad29sZnNzbC5jb22CCQCqJ7PFqXJuDTAMBgNVHRMEBTADAQH/MA0GCSqG +SIb3DQEBCwUAA4IBAQBRlqccJl0ckMYyn5YV8h3nk5ysdVaV/SBwq0VqCbDz8gOo +29wvvB+HeqPUj9VJl348VKyx4/A5Df4JmiP2MqZBWb1g6L3eADZvPulBb6ljx6rV +e/PkOUie9mDGxobVcoYjzfVqY1Ok+PxRas1gdI6jhmEBNHj3KZezpzS2Ct61cXoJ +pj7WgliJZ5zFaGK6BtY5u8s6wOBjH8cMnBKG7Pc5amGT0DMUxlU7ts+AW4xD70NE +CzyTOaNOFdELX4SYHc2fqUfrO1YwtnaSwUhfvJWwUBpVyE5iR4dUZAybkfpDsylI +vuYS6+NExlLkQMaDlRunZSdpcy/IoE1/vuqbZ7J7 +-----END CERTIFICATE----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/client-ecc-cert.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/client-ecc-cert.pem new file mode 100644 index 0000000..2090515 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/client-ecc-cert.pem @@ -0,0 +1,54 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 16108595702940209934 (0xdf8d3a71e022930e) + Signature Algorithm: ecdsa-with-SHA256 + Issuer: C=US, ST=Oregon, L=Salem, O=Client ECC, OU=Fast, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Validity + Not Before: May 7 18:21:01 2015 GMT + Not After : Jan 31 18:21:01 2018 GMT + Subject: C=US, ST=Oregon, L=Salem, O=Client ECC, OU=Fast, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Subject Public Key Info: + Public Key Algorithm: id-ecPublicKey + Public-Key: (256 bit) + pub: + 04:55:bf:f4:0f:44:50:9a:3d:ce:9b:b7:f0:c5:4d: + f5:70:7b:d4:ec:24:8e:19:80:ec:5a:4c:a2:24:03: + 62:2c:9b:da:ef:a2:35:12:43:84:76:16:c6:56:95: + 06:cc:01:a9:bd:f6:75:1a:42:f7:bd:a9:b2:36:22: + 5f:c7:5d:7f:b4 + ASN1 OID: prime256v1 + X509v3 extensions: + X509v3 Subject Key Identifier: + EB:D4:4B:59:6B:95:61:3F:51:57:B6:04:4D:89:41:88:44:5C:AB:F2 + X509v3 Authority Key Identifier: + keyid:EB:D4:4B:59:6B:95:61:3F:51:57:B6:04:4D:89:41:88:44:5C:AB:F2 + DirName:/C=US/ST=Oregon/L=Salem/O=Client ECC/OU=Fast/CN=www.wolfssl.com/emailAddress=info@wolfssl.com + serial:DF:8D:3A:71:E0:22:93:0E + + X509v3 Basic Constraints: + CA:TRUE + Signature Algorithm: ecdsa-with-SHA256 + 30:44:02:20:74:7b:ae:7e:9c:c8:69:95:8a:0b:ad:7f:c9:37: + 3d:3c:7f:b7:ef:f3:da:9b:ea:d0:a7:76:0a:a4:77:12:f7:a8: + 02:20:71:95:87:89:b7:a8:8b:bb:fa:9f:84:dc:2b:71:dc:4a: + c5:5a:65:b2:fc:33:c4:ce:36:4f:ab:c6:38:36:6c:88 +-----BEGIN CERTIFICATE----- +MIIDCDCCAq+gAwIBAgIJAN+NOnHgIpMOMAoGCCqGSM49BAMCMIGNMQswCQYDVQQG +EwJVUzEPMA0GA1UECAwGT3JlZ29uMQ4wDAYDVQQHDAVTYWxlbTETMBEGA1UECgwK +Q2xpZW50IEVDQzENMAsGA1UECwwERmFzdDEYMBYGA1UEAwwPd3d3LndvbGZzc2wu +Y29tMR8wHQYJKoZIhvcNAQkBFhBpbmZvQHdvbGZzc2wuY29tMB4XDTE1MDUwNzE4 +MjEwMVoXDTE4MDEzMTE4MjEwMVowgY0xCzAJBgNVBAYTAlVTMQ8wDQYDVQQIDAZP +cmVnb24xDjAMBgNVBAcMBVNhbGVtMRMwEQYDVQQKDApDbGllbnQgRUNDMQ0wCwYD +VQQLDARGYXN0MRgwFgYDVQQDDA93d3cud29sZnNzbC5jb20xHzAdBgkqhkiG9w0B +CQEWEGluZm9Ad29sZnNzbC5jb20wWTATBgcqhkjOPQIBBggqhkjOPQMBBwNCAARV +v/QPRFCaPc6bt/DFTfVwe9TsJI4ZgOxaTKIkA2Ism9rvojUSQ4R2FsZWlQbMAam9 +9nUaQve9qbI2Il/HXX+0o4H1MIHyMB0GA1UdDgQWBBTr1EtZa5VhP1FXtgRNiUGI +RFyr8jCBwgYDVR0jBIG6MIG3gBTr1EtZa5VhP1FXtgRNiUGIRFyr8qGBk6SBkDCB +jTELMAkGA1UEBhMCVVMxDzANBgNVBAgMBk9yZWdvbjEOMAwGA1UEBwwFU2FsZW0x +EzARBgNVBAoMCkNsaWVudCBFQ0MxDTALBgNVBAsMBEZhc3QxGDAWBgNVBAMMD3d3 +dy53b2xmc3NsLmNvbTEfMB0GCSqGSIb3DQEJARYQaW5mb0B3b2xmc3NsLmNvbYIJ +AN+NOnHgIpMOMAwGA1UdEwQFMAMBAf8wCgYIKoZIzj0EAwIDRwAwRAIgdHuufpzI +aZWKC61/yTc9PH+37/Pam+rQp3YKpHcS96gCIHGVh4m3qIu7+p+E3Ctx3ErFWmWy +/DPEzjZPq8Y4NmyI +-----END CERTIFICATE----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/client-key.der b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/client-key.der new file mode 100644 index 0000000..94dc253 Binary files /dev/null and b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/client-key.der differ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/client-key.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/client-key.pem new file mode 100644 index 0000000..c4e7ad2 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/client-key.pem @@ -0,0 +1,27 @@ +-----BEGIN RSA PRIVATE KEY----- +MIIEpAIBAAKCAQEAwwPRK/45pDJFO1PIhCsqfHSavaoqUgdH1qY2sgcyjtC6aXvG +w0Se1IFI/S1oootnu6F1yDYsStIb94u6zw357+zxgR57mwNHmr9lzH9lJGmm6BSJ +W+Q098WwFJP1Z3s6enjhAVZWkaYTQo3SPECcTO/Rht83URsMoTv18aNKNeThzpbf +G36/TpfQEOioCDCBryALQxTFdGe0MoJvjYbCiECZNoO6HkByIhfXUmUkc7DO7xnN +rv94bHvAEgPUTnINUG07ozujmV6dyNkMhbPZitlUJttt+qy7/yVMxNF59HHThkAY +E7BjtXJOMMSXhIYtVi/XFfd/wK71/Fvl+6G60wIDAQABAoIBAQCi5thfEHFkCJ4u +bdFtHoXSCrGMR84sUWqgEp5T3pFMHW3qWXvyd6rZxtmKq9jhFuRjJv+1bBNZuOOl +yHIXLgyfb+VZP3ZvSbERwlouFikN3reO3EDVou7gHqH0vpfbhmOWFM2YCWAtMHac +PM3miO5HknkLWgDiXl8RfH35CLcgBokqXf0AqyLh8LO8JKleJg4fAC3+IZpTW23T +K6uUgmhDNtj2L8Yi/LVBXQ0zYOqkfX7oS1WRVtNcV48flBcvqt7pnqj0z4pMjqDk +VnOyz0+GxWk88yQgi1yWDPprEjuaZ8HfxpaypdWSDZsJQmgkEEXUUOQXOUjQNYuU +bRHej8pZAoGBAOokp/lpM+lx3FJ9iCEoL0neunIW6cxHeogNlFeEWBY6gbA/os+m +bB6wBikAj+d3dqzbysfZXps/JpBSrvw4kAAUu7QPWJTnL2p+HE9BIdQxWR9OihqN +p1dsItjl9H4yphDLZKVVA4emJwWMw9e2J7JNujDaR49U0z2LhI2UmFilAoGBANU4 +G8OPxZMMRwtvNZLFsI1GyJIYj/WACvfvof6AubUqusoYsF2lB9CTjdicBBzUYo6m +JoEB/86KKmM0NUCqbYDeiSNqV02ebq2TTlaQC22dc4sMric93k7wqsVseGdslFKc +N2dsLe+7r9+mkDzER8+Nlp6YqbSfxaZQ3LPw+3QXAoGAXoMJYr26fKK/QnT1fBzS +ackEDYV+Pj0kEsMYe/Mp818OdmxZdeRBhGmdMvPNIquwNbpKsjzl2Vi2Yk9d3uWe +CspTsiz3nrNrClt5ZexukU6SIPb8/Bbt03YM4ux/smkTa3gOWkZktF63JaBadTpL +78c8Pvf9JrggxJkKmnO+wxkCgYEAukSTFKw0GTtfkWCs97TWgQU2UVM96GXcry7c +YT7Jfbh/h/A7mwOCKTfOck4R1bHBDAegmZFKjX/sec/xObXphexi99p9vGRNIjwO +8tZR9YfYmcARIF0PKf1b4q7ZHNkhVm38hNBf7RAVHBgh58Q9S9fQnmqVzyLJA3ue +42AB/C8CgYAR0EvPG2e5nxB1R4ZlrjHCxjCsWQZQ2Q+1cAb38NPIYnyo2m72IT/T +f1/qiqs/2Spe81HSwjA34y2jdQ0eTSE01VdwXIm/cuxKbmjVzRh0M06MOkWP5pZA +62P5GYY6Ud2JS7Dz+Z9dKJU4vjWrylznk1M0oUVdEzllQkahn831vw== +-----END RSA PRIVATE KEY----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/client-keyEnc.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/client-keyEnc.pem new file mode 100644 index 0000000..5476dc9 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/client-keyEnc.pem @@ -0,0 +1,30 @@ +-----BEGIN RSA PRIVATE KEY----- +Proc-Type: 4,ENCRYPTED +DEK-Info: DES-CBC,45B763473154576D + +8ZSASs14Oqtc8p2nx5sx8oqPsgZmf0IfZTCzXLFivaA0UXdCQLxtsthQRQ07xRrH +if96wh11dWuxW0dkSLKna9HguzNQ96ybbw5CwCCkYrfjef7sxoEUe9D6j3UMXZ/F +iaVPMmbHTcf9gn1ozkkxPSlsts/5f8AKFloHRXUE1jAih4wLB3mbIyDG9iKm45ck +Rn7+u6Fe3hDG/9JWtbLW3ePh5L455U6zP5hlneodDZEabUguUef7EMzXE01LqPAy +qeatI7t54cAGkUVgGbZrsKcXtiDtRNUefa9hb90tugY29LAt1ls5K68kR1x9U+TM +kWgjMzmhab5e7Alh+yMfDg2WplI2EHTDuLvcX9Vh1OHe7akN67EN/0IYcpGCryfe +RHLYvNNjXyJWfMKuo0XVqMY1JyBDebYJTlEafwNcjSBWSo5U4uihnVXvj8NfU36Z +JIeGGo6fyq5D0pPjvtRpk3XwbzQlvAQSDxbFp9dIX7m46Ji7YaeQO8Fgg1L5ENfm +wTx6xdPPdFb3ux0ksiU8QoF7190kjmS4SbeSLvpLjGh1f3dz6suJ+7+KN0ZwQd4e +Ki+IDuaKhYR1vn0ROVvUQ0+nmkunblcO6HyhcTgWiSCBIWhTwrRJIV4tmiQYS5bc +G7PqGIIOsFwwOwY4IWYt57YS0DGJsbdBuXToZgnnpG0yvnsIkeasEc5h4KCslQ0o +lztCFZxGITjDtt+b8acnCEN2calYBkKZfc1LV1u/Fh2no1CnDtjHqk0E0tcjuU6M +sZ3NSiiI0puvG91LtwidHP7x0okR2voG8joN3XmBDigUo/6SazjPoWwhOFIuE/MY +aXnPMFxgZ/KV5DcPWa3lOTMIfOzY84aMs4q4q4huCX9/MVe4ZjcuI1T8RCoSSvTu +jOV+eJL7N2uZi40BWVPMwFOIkgVn3oK99L/FtTJUzYDXqVb0Cmi6bg0FrwGQOJMV +M+ETvTW89k+Zy/RLXiFvdGeCHQXwkUJYlQGJkrkC5fWevEDmdH2qZbcgs/o8X5tg +lFOGoXRvmMLrNXLQVt5SGKsTjRxMbbSmNY3J+e2hFVkc8oslQZqtacDlZ29D0enQ +6me7+n2Qy6QOeTJ1pQOY5jHiJwsub2OCx1oML6lKBpn7g0taUGZauSIr+R14F/R7 +YhgO2QTydUrbs7jOwaIitdiwNuaHlFIujB8tqo1xAjPE18QL4NbqV/CUzLDuyiB+ +3hHmzRJ1aQTGO0/2ucbUqf6MUWvNuc6zFg5AETSg1or8A7gqi8/HdlBR6wUo+rug +IvJ2OkR9vyR8QJDOM9Pn8TS0e0B7TVqb8rUltzRtXOcbtLL3Xvy00+wlVyyiLRPz +u/u355ZoMDZLVhOoVoLGlXhA+St91qrELpe1O8aNrqOQy3pyhybiPOh9lgtqyr1C +QMQLcBGdoyMCsSiuDFbV+7thd/rQPE1Qqy06rStv1OEv9Y+hzZxrzF8HSfSLuNPd +UCDn9SSzZwGU9odLJNrzSNfz8GDVc72lKHlIR4bHMw0FW2QPsJR8NrN6ch4oYmfw +17R/cQ9CfWA0cEcSiAKIthbP7NHWw4SAhJ6sqwpDK4Vh8PrDF3U6WCEEshaokm+H +-----END RSA PRIVATE KEY----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/crl/cliCrl.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/crl/cliCrl.pem new file mode 100644 index 0000000..da4e617 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/crl/cliCrl.pem @@ -0,0 +1,39 @@ +Certificate Revocation List (CRL): + Version 2 (0x1) + Signature Algorithm: sha256WithRSAEncryption + Issuer: /C=US/ST=Montana/L=Bozeman/O=wolfSSL_2048/OU=Programming-2048/CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Last Update: May 7 18:21:01 2015 GMT + Next Update: Jan 31 18:21:01 2018 GMT + CRL extensions: + X509v3 CRL Number: + 3 +No Revoked Certificates. + Signature Algorithm: sha256WithRSAEncryption + a2:15:f0:cf:70:85:49:b9:5b:c1:af:2b:22:14:9d:ee:11:8d: + 93:2d:58:17:d8:f6:b6:1a:1a:25:a2:27:c9:6b:4f:b3:31:c7: + 2c:52:c4:53:59:19:ef:cf:91:ee:b5:19:28:37:49:9e:b6:e0: + 41:62:4c:9f:f1:34:bf:88:aa:ae:24:38:8d:29:0a:64:08:a8: + 68:f4:b5:28:73:d6:94:b9:0a:3f:7c:c1:22:72:be:14:ba:c9: + 1b:9d:26:af:78:c2:cf:5f:ff:1e:cc:25:c0:63:f1:9b:97:85: + 5c:c0:4d:14:ed:f9:ad:cb:02:7d:05:c7:5c:c1:7c:89:72:35: + 49:70:a8:b1:ae:91:96:77:9a:c6:cb:38:27:88:3f:f4:c8:ba: + c9:08:7f:dd:a6:41:82:62:65:a0:f2:0c:36:5a:d9:15:57:5e: + 66:c3:a2:ff:5e:4d:7c:bc:4b:7c:30:84:44:e3:06:34:a8:42: + 3b:d9:6a:04:4a:0b:e5:59:66:63:b9:7a:80:48:68:31:1c:aa: + 98:bc:09:0e:a7:83:5f:a7:00:f1:fb:78:bc:08:86:73:ef:53: + 25:b8:1b:5e:7c:77:a8:12:7b:52:7f:1e:63:bc:db:60:99:46: + ab:e1:2e:48:d1:28:40:68:1e:9e:a0:2f:14:04:66:b3:b1:b1: + 3b:d0:46:64 +-----BEGIN X509 CRL----- +MIIB+DCB4QIBATANBgkqhkiG9w0BAQsFADCBnjELMAkGA1UEBhMCVVMxEDAOBgNV +BAgMB01vbnRhbmExEDAOBgNVBAcMB0JvemVtYW4xFTATBgNVBAoMDHdvbGZTU0xf +MjA0ODEZMBcGA1UECwwQUHJvZ3JhbW1pbmctMjA0ODEYMBYGA1UEAwwPd3d3Lndv +bGZzc2wuY29tMR8wHQYJKoZIhvcNAQkBFhBpbmZvQHdvbGZzc2wuY29tFw0xNTA1 +MDcxODIxMDFaFw0xODAxMzExODIxMDFaoA4wDDAKBgNVHRQEAwIBAzANBgkqhkiG +9w0BAQsFAAOCAQEAohXwz3CFSblbwa8rIhSd7hGNky1YF9j2thoaJaInyWtPszHH +LFLEU1kZ78+R7rUZKDdJnrbgQWJMn/E0v4iqriQ4jSkKZAioaPS1KHPWlLkKP3zB +InK+FLrJG50mr3jCz1//HswlwGPxm5eFXMBNFO35rcsCfQXHXMF8iXI1SXCosa6R +lneaxss4J4g/9Mi6yQh/3aZBgmJloPIMNlrZFVdeZsOi/15NfLxLfDCEROMGNKhC +O9lqBEoL5VlmY7l6gEhoMRyqmLwJDqeDX6cA8ft4vAiGc+9TJbgbXnx3qBJ7Un8e +Y7zbYJlGq+EuSNEoQGgenqAvFARms7GxO9BGZA== +-----END X509 CRL----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/crl/crl.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/crl/crl.pem new file mode 100644 index 0000000..28311c7 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/crl/crl.pem @@ -0,0 +1,39 @@ +Certificate Revocation List (CRL): + Version 2 (0x1) + Signature Algorithm: sha256WithRSAEncryption + Issuer: /C=US/ST=Montana/L=Bozeman/O=Sawtooth/OU=Consulting/CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Last Update: May 7 18:21:01 2015 GMT + Next Update: Jan 31 18:21:01 2018 GMT + CRL extensions: + X509v3 CRL Number: + 1 +No Revoked Certificates. + Signature Algorithm: sha256WithRSAEncryption + 96:e2:b9:11:e0:e5:25:be:ab:69:e5:fa:8a:5c:7f:fc:6f:1d: + 8f:4a:54:70:f8:2e:87:fa:b0:f6:fd:3f:8f:9c:75:8a:eb:62: + cc:dd:2c:0a:8c:31:9e:30:3f:22:9b:91:50:6b:43:fd:32:8a: + 79:ea:0b:6b:68:6c:82:9c:79:da:20:95:83:25:5e:09:fc:57: + 2d:19:f9:bc:5a:67:95:98:65:dc:2d:91:13:2a:81:c2:6d:ff: + 12:48:6f:a4:ce:8a:b2:d3:19:b8:c2:86:e0:ba:91:3f:bb:ec: + c6:79:83:50:95:19:95:28:eb:ef:ff:bb:16:8f:3c:7d:4c:d1: + 3e:c3:82:22:8f:c5:e8:0e:b3:64:8f:5d:53:32:d5:98:64:9c: + 36:c4:6a:cf:68:21:4f:a8:4e:90:37:76:dc:05:70:66:2d:bc: + a0:d8:19:5c:96:90:d6:b9:09:56:46:07:be:3c:ae:08:bb:26: + 26:21:2c:d1:48:01:88:28:bc:21:a4:97:b7:3b:f0:7e:67:73: + 84:cf:21:43:e7:dd:53:9d:6a:59:c3:e5:98:c9:69:71:c3:e3: + 70:28:ba:f9:69:0a:af:78:e5:83:02:13:7e:08:70:8c:f3:8b: + 5d:96:b0:78:b9:d9:99:c5:1e:b7:45:dc:28:32:1a:d0:50:4b: + f4:41:92:19 +-----BEGIN X509 CRL----- +MIIB7jCB1wIBATANBgkqhkiG9w0BAQsFADCBlDELMAkGA1UEBhMCVVMxEDAOBgNV +BAgMB01vbnRhbmExEDAOBgNVBAcMB0JvemVtYW4xETAPBgNVBAoMCFNhd3Rvb3Ro +MRMwEQYDVQQLDApDb25zdWx0aW5nMRgwFgYDVQQDDA93d3cud29sZnNzbC5jb20x +HzAdBgkqhkiG9w0BCQEWEGluZm9Ad29sZnNzbC5jb20XDTE1MDUwNzE4MjEwMVoX +DTE4MDEzMTE4MjEwMVqgDjAMMAoGA1UdFAQDAgEBMA0GCSqGSIb3DQEBCwUAA4IB +AQCW4rkR4OUlvqtp5fqKXH/8bx2PSlRw+C6H+rD2/T+PnHWK62LM3SwKjDGeMD8i +m5FQa0P9Mop56gtraGyCnHnaIJWDJV4J/FctGfm8WmeVmGXcLZETKoHCbf8SSG+k +zoqy0xm4wobgupE/u+zGeYNQlRmVKOvv/7sWjzx9TNE+w4Iij8XoDrNkj11TMtWY +ZJw2xGrPaCFPqE6QN3bcBXBmLbyg2BlclpDWuQlWRge+PK4IuyYmISzRSAGIKLwh +pJe3O/B+Z3OEzyFD591TnWpZw+WYyWlxw+NwKLr5aQqveOWDAhN+CHCM84tdlrB4 +udmZxR63RdwoMhrQUEv0QZIZ +-----END X509 CRL----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/crl/crl.revoked b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/crl/crl.revoked new file mode 100644 index 0000000..60152d8 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/crl/crl.revoked @@ -0,0 +1,41 @@ +Certificate Revocation List (CRL): + Version 2 (0x1) + Signature Algorithm: sha256WithRSAEncryption + Issuer: /C=US/ST=Montana/L=Bozeman/O=Sawtooth/OU=Consulting/CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Last Update: May 7 18:21:01 2015 GMT + Next Update: Jan 31 18:21:01 2018 GMT + CRL extensions: + X509v3 CRL Number: + 2 +Revoked Certificates: + Serial Number: 01 + Revocation Date: May 7 18:21:01 2015 GMT + Signature Algorithm: sha256WithRSAEncryption + b7:34:2b:1c:09:6b:a2:9c:12:4f:fd:ef:69:4c:a4:1d:f2:39: + 52:29:98:78:b2:86:ea:54:9b:29:e5:c2:88:0e:2f:f9:d2:5b: + 9d:49:37:68:26:6c:45:61:d4:9d:05:ef:2d:ca:78:0a:d0:28: + c1:25:f2:f7:6a:ad:df:1d:eb:8a:66:64:4d:0c:02:91:fb:ff: + 70:b4:36:b6:e4:79:17:d5:18:6a:72:17:e1:8b:31:49:04:98: + 96:88:42:ea:8c:fe:91:40:5a:c5:ad:3b:da:9a:47:43:d6:e9: + f6:59:75:49:91:a9:e4:8b:c8:03:60:6b:36:69:87:71:f1:5b: + 92:00:51:bb:fe:d5:4f:0d:0e:f2:56:38:e3:b6:cb:76:11:7b: + 17:ad:a5:da:37:87:f2:49:af:73:42:56:ed:6c:a1:8d:46:5c: + dd:00:a7:8f:1f:5a:dd:d7:87:89:43:30:32:fe:e2:d4:b1:29: + 12:11:ef:22:0d:8f:7f:c5:33:3b:a9:a7:52:0c:25:b8:0c:e6: + 8a:8b:68:8f:55:84:65:04:c7:44:48:36:02:4d:4e:43:09:1d: + 1f:3b:f9:4a:0e:ff:59:42:ca:be:0e:a7:79:89:19:31:73:5a: + 45:6c:70:56:4d:1b:8a:59:c4:6d:ca:bc:f7:41:c4:f6:f0:fd: + 9c:7e:f1:7e +-----BEGIN X509 CRL----- +MIICBDCB7QIBATANBgkqhkiG9w0BAQsFADCBlDELMAkGA1UEBhMCVVMxEDAOBgNV +BAgMB01vbnRhbmExEDAOBgNVBAcMB0JvemVtYW4xETAPBgNVBAoMCFNhd3Rvb3Ro +MRMwEQYDVQQLDApDb25zdWx0aW5nMRgwFgYDVQQDDA93d3cud29sZnNzbC5jb20x +HzAdBgkqhkiG9w0BCQEWEGluZm9Ad29sZnNzbC5jb20XDTE1MDUwNzE4MjEwMVoX +DTE4MDEzMTE4MjEwMVowFDASAgEBFw0xNTA1MDcxODIxMDFaoA4wDDAKBgNVHRQE +AwIBAjANBgkqhkiG9w0BAQsFAAOCAQEAtzQrHAlropwST/3vaUykHfI5UimYeLKG +6lSbKeXCiA4v+dJbnUk3aCZsRWHUnQXvLcp4CtAowSXy92qt3x3rimZkTQwCkfv/ +cLQ2tuR5F9UYanIX4YsxSQSYlohC6oz+kUBaxa072ppHQ9bp9ll1SZGp5IvIA2Br +NmmHcfFbkgBRu/7VTw0O8lY447bLdhF7F62l2jeH8kmvc0JW7WyhjUZc3QCnjx9a +3deHiUMwMv7i1LEpEhHvIg2Pf8UzO6mnUgwluAzmiotoj1WEZQTHREg2Ak1OQwkd +Hzv5Sg7/WULKvg6neYkZMXNaRWxwVk0bilnEbcq890HE9vD9nH7xfg== +-----END X509 CRL----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/crl/eccCliCRL.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/crl/eccCliCRL.pem new file mode 100644 index 0000000..2e00a37 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/crl/eccCliCRL.pem @@ -0,0 +1,24 @@ +Certificate Revocation List (CRL): + Version 2 (0x1) + Signature Algorithm: ecdsa-with-SHA256 + Issuer: /C=US/ST=Oregon/L=Salem/O=Client ECC/OU=Fast/CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Last Update: May 7 18:21:01 2015 GMT + Next Update: Jan 31 18:21:01 2018 GMT + CRL extensions: + X509v3 CRL Number: + 4 +No Revoked Certificates. + Signature Algorithm: ecdsa-with-SHA256 + 30:44:02:20:62:9b:53:ee:21:52:bc:61:e8:ec:7b:f8:28:35: + 43:98:b8:57:9c:c7:73:cc:a0:45:e8:b9:96:2e:1c:c6:62:ff: + 02:20:2b:64:b8:3a:30:2c:15:7f:cf:57:99:60:9d:51:82:82: + ef:b6:13:cc:86:93:a2:19:41:12:a0:ec:7e:1e:07:09 +-----BEGIN X509 CRL----- +MIIBJTCBzQIBATAKBggqhkjOPQQDAjCBjTELMAkGA1UEBhMCVVMxDzANBgNVBAgM +Bk9yZWdvbjEOMAwGA1UEBwwFU2FsZW0xEzARBgNVBAoMCkNsaWVudCBFQ0MxDTAL +BgNVBAsMBEZhc3QxGDAWBgNVBAMMD3d3dy53b2xmc3NsLmNvbTEfMB0GCSqGSIb3 +DQEJARYQaW5mb0B3b2xmc3NsLmNvbRcNMTUwNTA3MTgyMTAxWhcNMTgwMTMxMTgy +MTAxWqAOMAwwCgYDVR0UBAMCAQQwCgYIKoZIzj0EAwIDRwAwRAIgYptT7iFSvGHo +7Hv4KDVDmLhXnMdzzKBF6LmWLhzGYv8CICtkuDowLBV/z1eZYJ1RgoLvthPMhpOi +GUESoOx+HgcJ +-----END X509 CRL----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/crl/eccSrvCRL.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/crl/eccSrvCRL.pem new file mode 100644 index 0000000..0746599 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/crl/eccSrvCRL.pem @@ -0,0 +1,24 @@ +Certificate Revocation List (CRL): + Version 2 (0x1) + Signature Algorithm: ecdsa-with-SHA256 + Issuer: /C=US/ST=Washington/L=Seattle/O=Eliptic/OU=ECC/CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Last Update: May 7 18:21:01 2015 GMT + Next Update: Jan 31 18:21:01 2018 GMT + CRL extensions: + X509v3 CRL Number: + 5 +No Revoked Certificates. + Signature Algorithm: ecdsa-with-SHA256 + 30:45:02:20:0d:fe:b7:79:fb:66:6c:cb:36:0a:1a:f3:6d:73: + ea:68:ab:fc:46:7e:49:bd:15:2a:9f:a1:17:50:56:82:cf:1f: + 02:21:00:ff:13:85:80:29:a4:60:54:10:93:fb:20:13:b8:9c: + 25:48:53:5e:4b:33:ef:5c:aa:9e:98:74:e0:c8:c3:ef:df +-----BEGIN X509 CRL----- +MIIBKDCBzwIBATAKBggqhkjOPQQDAjCBjzELMAkGA1UEBhMCVVMxEzARBgNVBAgM +Cldhc2hpbmd0b24xEDAOBgNVBAcMB1NlYXR0bGUxEDAOBgNVBAoMB0VsaXB0aWMx +DDAKBgNVBAsMA0VDQzEYMBYGA1UEAwwPd3d3LndvbGZzc2wuY29tMR8wHQYJKoZI +hvcNAQkBFhBpbmZvQHdvbGZzc2wuY29tFw0xNTA1MDcxODIxMDFaFw0xODAxMzEx +ODIxMDFaoA4wDDAKBgNVHRQEAwIBBTAKBggqhkjOPQQDAgNIADBFAiAN/rd5+2Zs +yzYKGvNtc+poq/xGfkm9FSqfoRdQVoLPHwIhAP8ThYAppGBUEJP7IBO4nCVIU15L +M+9cqp6YdODIw+/f +-----END X509 CRL----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/crl/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/crl/include.am new file mode 100644 index 0000000..7adca32 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/crl/include.am @@ -0,0 +1,14 @@ +# vim:ft=automake +# All paths should be given relative to the root +# + +EXTRA_DIST += \ + certs/crl/crl.pem \ + certs/crl/cliCrl.pem \ + certs/crl/eccSrvCRL.pem \ + certs/crl/eccCliCRL.pem + +EXTRA_DIST += \ + certs/crl/crl.revoked + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/dh2048.der b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/dh2048.der new file mode 100644 index 0000000..afdc522 Binary files /dev/null and b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/dh2048.der differ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/dh2048.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/dh2048.pem new file mode 100644 index 0000000..1e2b848 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/dh2048.pem @@ -0,0 +1,29 @@ +Diffie-Hellman-Parameters: (2048 bit) + prime: + 00:b0:a1:08:06:9c:08:13:ba:59:06:3c:bc:30:d5: + f5:00:c1:4f:44:a7:d6:ef:4a:c6:25:27:1c:e8:d2: + 96:53:0a:5c:91:dd:a2:c2:94:84:bf:7d:b2:44:9f: + 9b:d2:c1:8a:c5:be:72:5c:a7:e7:91:e6:d4:9f:73: + 07:85:5b:66:48:c7:70:fa:b4:ee:02:c9:3d:9a:4a: + da:3d:c1:46:3e:19:69:d1:17:46:07:a3:4d:9f:2b: + 96:17:39:6d:30:8d:2a:f3:94:d3:75:cf:a0:75:e6: + f2:92:1f:1a:70:05:aa:04:83:57:30:fb:da:76:93: + 38:50:e8:27:fd:63:ee:3c:e5:b7:c8:09:ae:6f:50: + 35:8e:84:ce:4a:00:e9:12:7e:5a:31:d7:33:fc:21: + 13:76:cc:16:30:db:0c:fc:c5:62:a7:35:b8:ef:b7: + b0:ac:c0:36:f6:d9:c9:46:48:f9:40:90:00:2b:1b: + aa:6c:e3:1a:c3:0b:03:9e:1b:c2:46:e4:48:4e:22: + 73:6f:c3:5f:d4:9a:d6:30:07:48:d6:8c:90:ab:d4: + f6:f1:e3:48:d3:58:4b:a6:b9:cd:29:bf:68:1f:08: + 4b:63:86:2f:5c:6b:d6:b6:06:65:f7:a6:dc:00:67: + 6b:bb:c3:a9:41:83:fb:c7:fa:c8:e2:1e:7e:af:00: + 3f:93 + generator: 2 (0x2) +-----BEGIN DH PARAMETERS----- +MIIBCAKCAQEAsKEIBpwIE7pZBjy8MNX1AMFPRKfW70rGJScc6NKWUwpckd2iwpSE +v32yRJ+b0sGKxb5yXKfnkebUn3MHhVtmSMdw+rTuAsk9mkraPcFGPhlp0RdGB6NN +nyuWFzltMI0q85TTdc+gdebykh8acAWqBINXMPvadpM4UOgn/WPuPOW3yAmub1A1 +joTOSgDpEn5aMdcz/CETdswWMNsM/MVipzW477ewrMA29tnJRkj5QJAAKxuqbOMa +wwsDnhvCRuRITiJzb8Nf1JrWMAdI1oyQq9T28eNI01hLprnNKb9oHwhLY4YvXGvW +tgZl96bcAGdru8OpQYP7x/rI4h5+rwA/kwIBAg== +-----END DH PARAMETERS----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/dsa2048.der b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/dsa2048.der new file mode 100644 index 0000000..0bcb0b4 Binary files /dev/null and b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/dsa2048.der differ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ecc-client-key.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ecc-client-key.pem new file mode 100644 index 0000000..cf9812d --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ecc-client-key.pem @@ -0,0 +1,9 @@ +ASN1 OID: prime256v1 +-----BEGIN EC PARAMETERS----- +BggqhkjOPQMBBw== +-----END EC PARAMETERS----- +-----BEGIN EC PRIVATE KEY----- +MHcCAQEEIPjPkmu9HijxqKuhI08ydBiIUK1+x+yS+I+XTa9WiWXHoAoGCCqGSM49 +AwEHoUQDQgAEVb/0D0RQmj3Om7fwxU31cHvU7CSOGYDsWkyiJANiLJva76I1EkOE +dhbGVpUGzAGpvfZ1GkL3vamyNiJfx11/tA== +-----END EC PRIVATE KEY----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ecc-key-comp.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ecc-key-comp.pem new file mode 100644 index 0000000..de76b8e --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ecc-key-comp.pem @@ -0,0 +1,4 @@ +-----BEGIN EC PRIVATE KEY----- +MFcCAQEEIEW2aQJznGyFoThbcujox6zEA41TNQT6bCjcNI3hqAmMoAoGCCqGSM49 +AwEHoSQDIgACuzOsTCdQSsZKpQTDPN6fNttyLc6U6iv6yyAJOSwW6GE= +-----END EC PRIVATE KEY----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ecc-key.der b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ecc-key.der new file mode 100644 index 0000000..a88d141 Binary files /dev/null and b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ecc-key.der differ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ecc-key.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ecc-key.pem new file mode 100644 index 0000000..03e7a61 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ecc-key.pem @@ -0,0 +1,9 @@ +ASN1 OID: prime256v1 +-----BEGIN EC PARAMETERS----- +BggqhkjOPQMBBw== +-----END EC PARAMETERS----- +-----BEGIN EC PRIVATE KEY----- +MHcCAQEEIEW2aQJznGyFoThbcujox6zEA41TNQT6bCjcNI3hqAmMoAoGCCqGSM49 +AwEHoUQDQgAEuzOsTCdQSsZKpQTDPN6fNttyLc6U6iv6yyAJOSwW6GEC6a9N0wKT +mjFbl5Ihf/DPGNqREQI0huggWDMLgDSJ2A== +-----END EC PRIVATE KEY----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ecc-keyPkcs8.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ecc-keyPkcs8.pem new file mode 100644 index 0000000..ca03d98 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ecc-keyPkcs8.pem @@ -0,0 +1,5 @@ +-----BEGIN PRIVATE KEY----- +MIGHAgEAMBMGByqGSM49AgEGCCqGSM49AwEHBG0wawIBAQQgRbZpAnOcbIWhOFty +6OjHrMQDjVM1BPpsKNw0jeGoCYyhRANCAAS7M6xMJ1BKxkqlBMM83p8223ItzpTq +K/rLIAk5LBboYQLpr03TApOaMVuXkiF/8M8Y2pERAjSG6CBYMwuANInY +-----END PRIVATE KEY----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/include.am new file mode 100644 index 0000000..b519204 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/include.am @@ -0,0 +1,44 @@ +# vim:ft=automake +# All paths should be given relative to the root +# + +EXTRA_DIST += \ + certs/ca-cert.pem \ + certs/ca-key.pem \ + certs/client-cert.pem \ + certs/client-keyEnc.pem \ + certs/client-key.pem \ + certs/ecc-key.pem \ + certs/ecc-key-comp.pem \ + certs/ecc-keyPkcs8.pem \ + certs/ecc-client-key.pem \ + certs/client-ecc-cert.pem \ + certs/ntru-cert.pem \ + certs/dh2048.pem \ + certs/server-cert.pem \ + certs/server-ecc.pem \ + certs/server-ecc-comp.pem \ + certs/server-ecc-rsa.pem \ + certs/server-keyEnc.pem \ + certs/server-key.pem \ + certs/server-keyPkcs8Enc12.pem \ + certs/server-keyPkcs8Enc2.pem \ + certs/server-keyPkcs8Enc.pem \ + certs/server-keyPkcs8.pem \ + certs/wolfssl-website-ca.pem +EXTRA_DIST += \ + certs/ca-key.der \ + certs/ca-cert.der \ + certs/client-cert.der \ + certs/client-key.der \ + certs/dh2048.der \ + certs/rsa2048.der \ + certs/dsa2048.der \ + certs/ecc-key.der \ + certs/server-key.der \ + certs/server-cert.der + +dist_doc_DATA+= certs/taoCert.txt + +EXTRA_DIST+= certs/ntru-key.raw + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ntru-cert.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ntru-cert.pem new file mode 100644 index 0000000..4e8aa3e --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ntru-cert.pem @@ -0,0 +1,28 @@ +-----BEGIN CERTIFICATE----- +MIIEzzCCA7egAwIBAgIIAazu2er3DUMwDQYJKoZIhvcNAQEFBQAwgZQxCzAJBgNV +BAYTAlVTMRAwDgYDVQQIDAdNb250YW5hMRAwDgYDVQQHDAdCb3plbWFuMREwDwYD +VQQKDAhTYXd0b290aDETMBEGA1UECwwKQ29uc3VsdGluZzEYMBYGA1UEAwwPd3d3 +LndvbGZzc2wuY29tMR8wHQYJKoZIhvcNAQkBFhBpbmZvQHdvbGZzc2wuY29tMCIY +DzIwMTUwMjA0MDYzMzI5WhgPMjAxNjA2MTkwNzMzMjlaMIGKMQswCQYDVQQGEwJV +UzELMAkGA1UECAwCT1IxETAPBgNVBAcMCFBvcnRsYW5kMQ4wDAYDVQQKDAV5YVNT +TDEUMBIGA1UECwwLRGV2ZWxvcG1lbnQxFjAUBgNVBAMMDXd3dy55YXNzbC5jb20x +HTAbBgkqhkiG9w0BCQEWDmluZm9AeWFzc2wuY29tMIICTTAaBgsrBgEEAcEWAQEB +AQYLKwYBBAHBFgEBAi4DggItAASCAiifDYOsBu8WQqIuom5HpD+jF7bvqvyO7LN4 +p7dOUfyBBX2zFc7fbhVoLcLw62Ye0i54UXMI/rglgOxEisVXPo0//Cs2rl3zwjho +fnEvEMpDU4mvqYTV8+N7FYoaUSEhMWTS0GMCJdK9aTvAz8l7F8gKP6MtgIv7Ght/ +r6JclP7fh12KMy9hiM/Tv3wqr+KhR8xFRfpL+paEIroidfpExFWbFB+xxA6KxGk4 +OEs/nus4rQl4w+6z5uf1cYfxKVRMFWLScEDQ3TdPcHz0+7fl/L7LYyCbK9z9LYVZ +5qZR1V27Iwx4H3d2w2D/3GGZpML/Uv8eBBHtODBbJC54U+bVh1ned28N1Y8I/bm8 +xRRCppfCJ3o+WxlsqHtyjIo/hi75SgUHknnbZ4hEuye1XhBBhUVhN2zybADMi1bv +S1RL/HAWsOO8qzBx5vkbVlDShsF+EccNUaNQyM98VE3FrUBbk4JxnyHBK5pA7aQ5 +7LOm83WkX2uR+ucR5en2TZIGVL+cJiTly+W7W8J83KEf5HJIUqnxFlgsre/0pMfe +7RqGer5Q4itWE+XWaPsDCUZnHy8a/CGdWlmdiGuw/0UvDqKQ4NRerbMgpo2Fl182 +fIQxfohhnm7iM0dAroIglkNBLM89A30d+73ZnUKgg4mRaqC5C29Me6LqpXjEUCiT +/s3g24IooqTj+8i8osRY5Zp4MQTmb3NrWVAWoOTtbFxDkhkwgqALupC8opUSIwAw +DQYJKoZIhvcNAQEFBQADggEBAHPi6MLfKV3ILr4wVgktXWNrPVgbqzUfoHhZhuhU +OgoT1KjiGQTpMrszGXyNKWTV+TpL2RmsBsXwI+lCl9nQMk5nkHAELShwXmgBpR+r +2dQTUy6C5xze8ZqPhsIjUjHyaagX8QY42SlSGOCChOEYshqO+QouPL2XOf2Hp4nJ +fgx4Mo2APTxGJ8TLYBCu4QzglCkKl7g1JRKBVA8Q4bkb1NWOnTgRQfIVv3N9DMn0 +ELw4uHkS2bXlzzbKRpwIMms0MIdWrVKFycQIp9Z2/7RsrIidZdGgsDeJLpItMZB8 +UM5Fz1UyZTy54Keoto4nBsU9ZJxzsTihT+Oq+/n1WaMEn+I= +-----END CERTIFICATE----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ntru-key.raw b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ntru-key.raw new file mode 100644 index 0000000..740bd34 Binary files /dev/null and b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/ntru-key.raw differ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/rsa2048.der b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/rsa2048.der new file mode 100644 index 0000000..837095b Binary files /dev/null and b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/rsa2048.der differ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-cert.der b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-cert.der new file mode 100644 index 0000000..0c936a2 Binary files /dev/null and b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-cert.der differ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-cert.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-cert.pem new file mode 100644 index 0000000..95df724 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-cert.pem @@ -0,0 +1,172 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 1 (0x1) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C=US, ST=Montana, L=Bozeman, O=Sawtooth, OU=Consulting, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Validity + Not Before: May 7 18:21:01 2015 GMT + Not After : Jan 31 18:21:01 2018 GMT + Subject: C=US, ST=Montana, L=Bozeman, O=wolfSSL, OU=Support, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:c0:95:08:e1:57:41:f2:71:6d:b7:d2:45:41:27: + 01:65:c6:45:ae:f2:bc:24:30:b8:95:ce:2f:4e:d6: + f6:1c:88:bc:7c:9f:fb:a8:67:7f:fe:5c:9c:51:75: + f7:8a:ca:07:e7:35:2f:8f:e1:bd:7b:c0:2f:7c:ab: + 64:a8:17:fc:ca:5d:7b:ba:e0:21:e5:72:2e:6f:2e: + 86:d8:95:73:da:ac:1b:53:b9:5f:3f:d7:19:0d:25: + 4f:e1:63:63:51:8b:0b:64:3f:ad:43:b8:a5:1c:5c: + 34:b3:ae:00:a0:63:c5:f6:7f:0b:59:68:78:73:a6: + 8c:18:a9:02:6d:af:c3:19:01:2e:b8:10:e3:c6:cc: + 40:b4:69:a3:46:33:69:87:6e:c4:bb:17:a6:f3:e8: + dd:ad:73:bc:7b:2f:21:b5:fd:66:51:0c:bd:54:b3: + e1:6d:5f:1c:bc:23:73:d1:09:03:89:14:d2:10:b9: + 64:c3:2a:d0:a1:96:4a:bc:e1:d4:1a:5b:c7:a0:c0: + c1:63:78:0f:44:37:30:32:96:80:32:23:95:a1:77: + ba:13:d2:97:73:e2:5d:25:c9:6a:0d:c3:39:60:a4: + b4:b0:69:42:42:09:e9:d8:08:bc:33:20:b3:58:22: + a7:aa:eb:c4:e1:e6:61:83:c5:d2:96:df:d9:d0:4f: + ad:d7 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Subject Key Identifier: + B3:11:32:C9:92:98:84:E2:C9:F8:D0:3B:6E:03:42:CA:1F:0E:8E:3C + X509v3 Authority Key Identifier: + keyid:27:8E:67:11:74:C3:26:1D:3F:ED:33:63:B3:A4:D8:1D:30:E5:E8:D5 + DirName:/C=US/ST=Montana/L=Bozeman/O=Sawtooth/OU=Consulting/CN=www.wolfssl.com/emailAddress=info@wolfssl.com + serial:D9:80:3A:C3:D2:F4:DA:37 + + X509v3 Basic Constraints: + CA:TRUE + Signature Algorithm: sha256WithRSAEncryption + 67:c0:2c:a9:43:47:e7:11:14:77:ae:cc:d8:e0:6b:23:82:91: + 63:e8:a8:0d:21:c5:c8:47:97:2f:d5:f3:86:fb:6c:ce:25:f9: + 7c:78:c8:3a:22:68:f2:16:1e:d2:d2:3f:24:04:87:f2:b7:c1: + 62:63:ba:c5:fa:ae:d2:20:81:1a:d2:0c:ae:26:6b:1b:2b:10: + d3:e1:9a:4e:64:6c:97:db:36:a8:8f:f8:05:63:bf:ba:0d:88: + 0b:87:46:c9:e4:64:e3:d7:bd:b8:2d:d5:c1:c3:c4:db:55:68: + dc:a3:7a:40:b9:a9:f6:04:4a:22:cf:98:76:1c:e4:a3:ff:79: + 19:96:57:63:07:6f:f6:32:77:16:50:9b:e3:34:18:d4:eb:be: + fd:b6:6f:e3:c7:f6:85:bf:ac:32:ad:98:57:be:13:92:44:10: + a5:f3:ae:e2:66:da:44:a9:94:71:3f:d0:2f:20:59:87:e4:5a: + 40:ee:d2:e4:0c:ce:25:94:dc:0f:fe:38:e0:41:52:34:5c:bb: + c3:db:c1:5f:76:c3:5d:0e:32:69:2b:9d:01:ed:50:1b:4f:77: + a9:a9:d8:71:30:cb:2e:2c:70:00:ab:78:4b:d7:15:d9:17:f8: + 64:b2:f7:3a:da:e1:0b:8b:0a:e1:4e:b1:03:46:14:ca:94:e3: + 44:77:d7:59 +-----BEGIN CERTIFICATE----- +MIIEnjCCA4agAwIBAgIBATANBgkqhkiG9w0BAQsFADCBlDELMAkGA1UEBhMCVVMx +EDAOBgNVBAgMB01vbnRhbmExEDAOBgNVBAcMB0JvemVtYW4xETAPBgNVBAoMCFNh +d3Rvb3RoMRMwEQYDVQQLDApDb25zdWx0aW5nMRgwFgYDVQQDDA93d3cud29sZnNz +bC5jb20xHzAdBgkqhkiG9w0BCQEWEGluZm9Ad29sZnNzbC5jb20wHhcNMTUwNTA3 +MTgyMTAxWhcNMTgwMTMxMTgyMTAxWjCBkDELMAkGA1UEBhMCVVMxEDAOBgNVBAgM +B01vbnRhbmExEDAOBgNVBAcMB0JvemVtYW4xEDAOBgNVBAoMB3dvbGZTU0wxEDAO +BgNVBAsMB1N1cHBvcnQxGDAWBgNVBAMMD3d3dy53b2xmc3NsLmNvbTEfMB0GCSqG +SIb3DQEJARYQaW5mb0B3b2xmc3NsLmNvbTCCASIwDQYJKoZIhvcNAQEBBQADggEP +ADCCAQoCggEBAMCVCOFXQfJxbbfSRUEnAWXGRa7yvCQwuJXOL07W9hyIvHyf+6hn +f/5cnFF194rKB+c1L4/hvXvAL3yrZKgX/Mpde7rgIeVyLm8uhtiVc9qsG1O5Xz/X +GQ0lT+FjY1GLC2Q/rUO4pRxcNLOuAKBjxfZ/C1loeHOmjBipAm2vwxkBLrgQ48bM +QLRpo0YzaYduxLsXpvPo3a1zvHsvIbX9ZlEMvVSz4W1fHLwjc9EJA4kU0hC5ZMMq +0KGWSrzh1Bpbx6DAwWN4D0Q3MDKWgDIjlaF3uhPSl3PiXSXJag3DOWCktLBpQkIJ +6dgIvDMgs1gip6rrxOHmYYPF0pbf2dBPrdcCAwEAAaOB/DCB+TAdBgNVHQ4EFgQU +sxEyyZKYhOLJ+NA7bgNCyh8OjjwwgckGA1UdIwSBwTCBvoAUJ45nEXTDJh0/7TNj +s6TYHTDl6NWhgZqkgZcwgZQxCzAJBgNVBAYTAlVTMRAwDgYDVQQIDAdNb250YW5h +MRAwDgYDVQQHDAdCb3plbWFuMREwDwYDVQQKDAhTYXd0b290aDETMBEGA1UECwwK +Q29uc3VsdGluZzEYMBYGA1UEAwwPd3d3LndvbGZzc2wuY29tMR8wHQYJKoZIhvcN +AQkBFhBpbmZvQHdvbGZzc2wuY29tggkA2YA6w9L02jcwDAYDVR0TBAUwAwEB/zAN +BgkqhkiG9w0BAQsFAAOCAQEAZ8AsqUNH5xEUd67M2OBrI4KRY+ioDSHFyEeXL9Xz +hvtsziX5fHjIOiJo8hYe0tI/JASH8rfBYmO6xfqu0iCBGtIMriZrGysQ0+GaTmRs +l9s2qI/4BWO/ug2IC4dGyeRk49e9uC3VwcPE21Vo3KN6QLmp9gRKIs+Ydhzko/95 +GZZXYwdv9jJ3FlCb4zQY1Ou+/bZv48f2hb+sMq2YV74TkkQQpfOu4mbaRKmUcT/Q +LyBZh+RaQO7S5AzOJZTcD/444EFSNFy7w9vBX3bDXQ4yaSudAe1QG093qanYcTDL +LixwAKt4S9cV2Rf4ZLL3OtrhC4sK4U6xA0YUypTjRHfXWQ== +-----END CERTIFICATE----- +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 15672591315981621815 (0xd9803ac3d2f4da37) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C=US, ST=Montana, L=Bozeman, O=Sawtooth, OU=Consulting, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Validity + Not Before: May 7 18:21:01 2015 GMT + Not After : Jan 31 18:21:01 2018 GMT + Subject: C=US, ST=Montana, L=Bozeman, O=Sawtooth, OU=Consulting, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:bf:0c:ca:2d:14:b2:1e:84:42:5b:cd:38:1f:4a: + f2:4d:75:10:f1:b6:35:9f:df:ca:7d:03:98:d3:ac: + de:03:66:ee:2a:f1:d8:b0:7d:6e:07:54:0b:10:98: + 21:4d:80:cb:12:20:e7:cc:4f:de:45:7d:c9:72:77: + 32:ea:ca:90:bb:69:52:10:03:2f:a8:f3:95:c5:f1: + 8b:62:56:1b:ef:67:6f:a4:10:41:95:ad:0a:9b:e3: + a5:c0:b0:d2:70:76:50:30:5b:a8:e8:08:2c:7c:ed: + a7:a2:7a:8d:38:29:1c:ac:c7:ed:f2:7c:95:b0:95: + 82:7d:49:5c:38:cd:77:25:ef:bd:80:75:53:94:3c: + 3d:ca:63:5b:9f:15:b5:d3:1d:13:2f:19:d1:3c:db: + 76:3a:cc:b8:7d:c9:e5:c2:d7:da:40:6f:d8:21:dc: + 73:1b:42:2d:53:9c:fe:1a:fc:7d:ab:7a:36:3f:98: + de:84:7c:05:67:ce:6a:14:38:87:a9:f1:8c:b5:68: + cb:68:7f:71:20:2b:f5:a0:63:f5:56:2f:a3:26:d2: + b7:6f:b1:5a:17:d7:38:99:08:fe:93:58:6f:fe:c3: + 13:49:08:16:0b:a7:4d:67:00:52:31:67:23:4e:98: + ed:51:45:1d:b9:04:d9:0b:ec:d8:28:b3:4b:bd:ed: + 36:79 + Exponent: 65537 (0x10001) + X509v3 extensions: + X509v3 Subject Key Identifier: + 27:8E:67:11:74:C3:26:1D:3F:ED:33:63:B3:A4:D8:1D:30:E5:E8:D5 + X509v3 Authority Key Identifier: + keyid:27:8E:67:11:74:C3:26:1D:3F:ED:33:63:B3:A4:D8:1D:30:E5:E8:D5 + DirName:/C=US/ST=Montana/L=Bozeman/O=Sawtooth/OU=Consulting/CN=www.wolfssl.com/emailAddress=info@wolfssl.com + serial:D9:80:3A:C3:D2:F4:DA:37 + + X509v3 Basic Constraints: + CA:TRUE + Signature Algorithm: sha256WithRSAEncryption + 7a:af:44:3b:aa:6f:53:42:b2:33:aa:43:5f:56:30:d3:b9:96: + 0b:9a:55:5a:39:2a:0b:4e:e4:2e:f1:95:66:c9:86:36:82:8d: + 63:7c:4d:a2:ee:48:ba:03:c7:90:d7:a7:c6:74:60:48:5f:31: + a2:f9:5e:3e:c3:82:e1:e5:2f:41:81:83:29:25:79:d1:53:00: + 69:3c:ed:0a:30:3b:41:1d:92:a1:2c:a8:9d:2c:e3:23:87:79: + e0:55:6e:91:a8:50:da:46:2f:c2:20:50:3e:2b:47:97:14:b0: + 7d:04:ba:45:51:d0:6e:e1:5a:a2:4b:84:9c:4d:cd:85:04:f9: + 28:31:82:93:bc:c7:59:49:91:03:e8:df:6a:e4:56:ad:6a:cb: + 1f:0d:37:e4:5e:bd:e7:9f:d5:ec:9d:3c:18:25:9b:f1:2f:50: + 7d:eb:31:cb:f1:63:22:9d:57:fc:f3:84:20:1a:c6:07:87:92: + 26:9e:15:18:59:33:06:dc:fb:b0:b6:76:5d:f1:c1:2f:c8:2f: + 62:9c:c0:d6:de:eb:65:77:f3:5c:a6:c3:88:27:96:75:b4:f4: + 54:cd:ff:2d:21:2e:96:f0:07:73:4b:e9:93:92:90:de:62:d9: + a3:3b:ac:6e:24:5f:27:4a:b3:94:70:ff:30:17:e7:7e:32:8f: + 65:b7:75:58 +-----BEGIN CERTIFICATE----- +MIIEqjCCA5KgAwIBAgIJANmAOsPS9No3MA0GCSqGSIb3DQEBCwUAMIGUMQswCQYD +VQQGEwJVUzEQMA4GA1UECAwHTW9udGFuYTEQMA4GA1UEBwwHQm96ZW1hbjERMA8G +A1UECgwIU2F3dG9vdGgxEzARBgNVBAsMCkNvbnN1bHRpbmcxGDAWBgNVBAMMD3d3 +dy53b2xmc3NsLmNvbTEfMB0GCSqGSIb3DQEJARYQaW5mb0B3b2xmc3NsLmNvbTAe +Fw0xNTA1MDcxODIxMDFaFw0xODAxMzExODIxMDFaMIGUMQswCQYDVQQGEwJVUzEQ +MA4GA1UECAwHTW9udGFuYTEQMA4GA1UEBwwHQm96ZW1hbjERMA8GA1UECgwIU2F3 +dG9vdGgxEzARBgNVBAsMCkNvbnN1bHRpbmcxGDAWBgNVBAMMD3d3dy53b2xmc3Ns +LmNvbTEfMB0GCSqGSIb3DQEJARYQaW5mb0B3b2xmc3NsLmNvbTCCASIwDQYJKoZI +hvcNAQEBBQADggEPADCCAQoCggEBAL8Myi0Ush6EQlvNOB9K8k11EPG2NZ/fyn0D +mNOs3gNm7irx2LB9bgdUCxCYIU2AyxIg58xP3kV9yXJ3MurKkLtpUhADL6jzlcXx +i2JWG+9nb6QQQZWtCpvjpcCw0nB2UDBbqOgILHztp6J6jTgpHKzH7fJ8lbCVgn1J +XDjNdyXvvYB1U5Q8PcpjW58VtdMdEy8Z0TzbdjrMuH3J5cLX2kBv2CHccxtCLVOc +/hr8fat6Nj+Y3oR8BWfOahQ4h6nxjLVoy2h/cSAr9aBj9VYvoybSt2+xWhfXOJkI +/pNYb/7DE0kIFgunTWcAUjFnI06Y7VFFHbkE2Qvs2CizS73tNnkCAwEAAaOB/DCB ++TAdBgNVHQ4EFgQUJ45nEXTDJh0/7TNjs6TYHTDl6NUwgckGA1UdIwSBwTCBvoAU +J45nEXTDJh0/7TNjs6TYHTDl6NWhgZqkgZcwgZQxCzAJBgNVBAYTAlVTMRAwDgYD +VQQIDAdNb250YW5hMRAwDgYDVQQHDAdCb3plbWFuMREwDwYDVQQKDAhTYXd0b290 +aDETMBEGA1UECwwKQ29uc3VsdGluZzEYMBYGA1UEAwwPd3d3LndvbGZzc2wuY29t +MR8wHQYJKoZIhvcNAQkBFhBpbmZvQHdvbGZzc2wuY29tggkA2YA6w9L02jcwDAYD +VR0TBAUwAwEB/zANBgkqhkiG9w0BAQsFAAOCAQEAeq9EO6pvU0KyM6pDX1Yw07mW +C5pVWjkqC07kLvGVZsmGNoKNY3xNou5IugPHkNenxnRgSF8xovlePsOC4eUvQYGD +KSV50VMAaTztCjA7QR2SoSyonSzjI4d54FVukahQ2kYvwiBQPitHlxSwfQS6RVHQ +buFaokuEnE3NhQT5KDGCk7zHWUmRA+jfauRWrWrLHw035F6955/V7J08GCWb8S9Q +fesxy/FjIp1X/POEIBrGB4eSJp4VGFkzBtz7sLZ2XfHBL8gvYpzA1t7rZXfzXKbD +iCeWdbT0VM3/LSEulvAHc0vpk5KQ3mLZozusbiRfJ0qzlHD/MBfnfjKPZbd1WA== +-----END CERTIFICATE----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-ecc-comp.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-ecc-comp.pem new file mode 100644 index 0000000..50b74f8 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-ecc-comp.pem @@ -0,0 +1,52 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 17764616133298603308 (0xf6889840946fc52c) + Signature Algorithm: ecdsa-with-SHA256 + Issuer: C=US, ST=Montana, L=Bozeman, O=Elliptic - comp, OU=Server ECC-comp, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Validity + Not Before: May 7 18:21:01 2015 GMT + Not After : Jan 31 18:21:01 2018 GMT + Subject: C=US, ST=Montana, L=Bozeman, O=Elliptic - comp, OU=Server ECC-comp, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Subject Public Key Info: + Public Key Algorithm: id-ecPublicKey + Public-Key: (256 bit) + pub: + 02:bb:33:ac:4c:27:50:4a:c6:4a:a5:04:c3:3c:de: + 9f:36:db:72:2d:ce:94:ea:2b:fa:cb:20:09:39:2c: + 16:e8:61 + ASN1 OID: prime256v1 + X509v3 extensions: + X509v3 Subject Key Identifier: + 8C:38:3A:6B:B8:24:B7:DF:6E:F4:59:AC:56:4E:AA:E2:58:A6:5A:18 + X509v3 Authority Key Identifier: + keyid:8C:38:3A:6B:B8:24:B7:DF:6E:F4:59:AC:56:4E:AA:E2:58:A6:5A:18 + DirName:/C=US/ST=Montana/L=Bozeman/O=Elliptic - comp/OU=Server ECC-comp/CN=www.wolfssl.com/emailAddress=info@wolfssl.com + serial:F6:88:98:40:94:6F:C5:2C + + X509v3 Basic Constraints: + CA:TRUE + Signature Algorithm: ecdsa-with-SHA256 + 30:46:02:21:00:9c:f8:3e:f6:5e:cd:da:b1:08:fe:e2:bd:78: + 14:b5:33:b3:29:69:d0:a0:de:19:05:ec:c3:46:29:01:8c:4c: + 56:02:21:00:e2:e7:ea:37:c1:08:f6:15:73:0c:92:4f:25:63: + f6:53:96:31:4c:9f:1d:1a:1f:c0:a0:a3:48:bd:71:ce:13:11 +-----BEGIN CERTIFICATE----- +MIIDJTCCAsqgAwIBAgIJAPaImECUb8UsMAoGCCqGSM49BAMCMIGgMQswCQYDVQQG +EwJVUzEQMA4GA1UECAwHTW9udGFuYTEQMA4GA1UEBwwHQm96ZW1hbjEYMBYGA1UE +CgwPRWxsaXB0aWMgLSBjb21wMRgwFgYDVQQLDA9TZXJ2ZXIgRUNDLWNvbXAxGDAW +BgNVBAMMD3d3dy53b2xmc3NsLmNvbTEfMB0GCSqGSIb3DQEJARYQaW5mb0B3b2xm +c3NsLmNvbTAeFw0xNTA1MDcxODIxMDFaFw0xODAxMzExODIxMDFaMIGgMQswCQYD +VQQGEwJVUzEQMA4GA1UECAwHTW9udGFuYTEQMA4GA1UEBwwHQm96ZW1hbjEYMBYG +A1UECgwPRWxsaXB0aWMgLSBjb21wMRgwFgYDVQQLDA9TZXJ2ZXIgRUNDLWNvbXAx +GDAWBgNVBAMMD3d3dy53b2xmc3NsLmNvbTEfMB0GCSqGSIb3DQEJARYQaW5mb0B3 +b2xmc3NsLmNvbTA5MBMGByqGSM49AgEGCCqGSM49AwEHAyIAArszrEwnUErGSqUE +wzzenzbbci3OlOor+ssgCTksFuhho4IBCTCCAQUwHQYDVR0OBBYEFIw4Omu4JLff +bvRZrFZOquJYploYMIHVBgNVHSMEgc0wgcqAFIw4Omu4JLffbvRZrFZOquJYploY +oYGmpIGjMIGgMQswCQYDVQQGEwJVUzEQMA4GA1UECAwHTW9udGFuYTEQMA4GA1UE +BwwHQm96ZW1hbjEYMBYGA1UECgwPRWxsaXB0aWMgLSBjb21wMRgwFgYDVQQLDA9T +ZXJ2ZXIgRUNDLWNvbXAxGDAWBgNVBAMMD3d3dy53b2xmc3NsLmNvbTEfMB0GCSqG +SIb3DQEJARYQaW5mb0B3b2xmc3NsLmNvbYIJAPaImECUb8UsMAwGA1UdEwQFMAMB +Af8wCgYIKoZIzj0EAwIDSQAwRgIhAJz4PvZezdqxCP7ivXgUtTOzKWnQoN4ZBezD +RikBjExWAiEA4ufqN8EI9hVzDJJPJWP2U5YxTJ8dGh/AoKNIvXHOExE= +-----END CERTIFICATE----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-ecc-rsa.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-ecc-rsa.pem new file mode 100644 index 0000000..4c90d1d --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-ecc-rsa.pem @@ -0,0 +1,69 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 1 (0x1) + Signature Algorithm: sha256WithRSAEncryption + Issuer: C=US, ST=Montana, L=Bozeman, O=Sawtooth, OU=Consulting, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Validity + Not Before: May 7 18:21:01 2015 GMT + Not After : Jan 31 18:21:01 2018 GMT + Subject: C=US, ST=Montana, L=Bozeman, O=Elliptic - RSAsig, OU=ECC-RSAsig, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Subject Public Key Info: + Public Key Algorithm: id-ecPublicKey + Public-Key: (256 bit) + pub: + 04:bb:33:ac:4c:27:50:4a:c6:4a:a5:04:c3:3c:de: + 9f:36:db:72:2d:ce:94:ea:2b:fa:cb:20:09:39:2c: + 16:e8:61:02:e9:af:4d:d3:02:93:9a:31:5b:97:92: + 21:7f:f0:cf:18:da:91:11:02:34:86:e8:20:58:33: + 0b:80:34:89:d8 + ASN1 OID: prime256v1 + X509v3 extensions: + X509v3 Subject Key Identifier: + 5D:5D:26:EF:AC:7E:36:F9:9B:76:15:2B:4A:25:02:23:EF:B2:89:30 + X509v3 Authority Key Identifier: + keyid:27:8E:67:11:74:C3:26:1D:3F:ED:33:63:B3:A4:D8:1D:30:E5:E8:D5 + DirName:/C=US/ST=Montana/L=Bozeman/O=Sawtooth/OU=Consulting/CN=www.wolfssl.com/emailAddress=info@wolfssl.com + serial:D9:80:3A:C3:D2:F4:DA:37 + + X509v3 Basic Constraints: + CA:TRUE + Signature Algorithm: sha256WithRSAEncryption + ac:2b:a9:d9:15:3b:9a:42:fb:86:2b:c1:f2:18:7c:a6:ca:27: + 0b:48:81:64:20:3b:d3:4f:ee:95:d4:c5:fd:5f:c7:d6:ab:a1: + 41:85:cc:e1:16:e1:fd:ce:8a:af:95:27:f2:f0:7a:3d:59:5d: + 3a:5d:03:99:cb:4c:5c:19:35:9c:b2:6e:7e:2b:10:e2:7f:ef: + 14:35:79:ca:67:eb:51:a9:e9:bb:5f:52:af:9d:79:80:b5:31: + 5c:f0:20:ca:c7:e9:9b:29:82:c4:a4:74:0a:2a:76:ea:ad:59: + a2:f9:a2:cf:53:40:11:ac:1a:de:fc:ab:28:96:9f:cf:ff:b9: + 74:31:95:c4:6d:d2:76:c1:93:97:75:a6:9f:69:a3:7d:92:75: + b8:27:a2:bd:4d:4b:54:11:b4:8a:43:f2:fc:10:a5:82:fb:51: + 45:57:86:00:85:71:91:21:37:5c:9f:f3:68:06:ae:9e:86:46: + 8d:4b:e3:d0:42:a4:cf:c1:5d:95:bc:1a:92:f8:44:1e:a0:1b: + c8:98:41:af:8e:94:41:60:69:b1:7c:8e:70:ce:88:42:44:3a: + 2d:3f:de:6e:3a:aa:d1:64:be:03:68:60:b6:ac:e5:44:c1:bb: + f1:c9:40:90:c2:c9:8f:ec:32:9d:e0:b4:4b:1a:e7:da:99:94: + fe:e2:b6:2a +-----BEGIN CERTIFICATE----- +MIID4DCCAsigAwIBAgIBATANBgkqhkiG9w0BAQsFADCBlDELMAkGA1UEBhMCVVMx +EDAOBgNVBAgMB01vbnRhbmExEDAOBgNVBAcMB0JvemVtYW4xETAPBgNVBAoMCFNh +d3Rvb3RoMRMwEQYDVQQLDApDb25zdWx0aW5nMRgwFgYDVQQDDA93d3cud29sZnNz +bC5jb20xHzAdBgkqhkiG9w0BCQEWEGluZm9Ad29sZnNzbC5jb20wHhcNMTUwNTA3 +MTgyMTAxWhcNMTgwMTMxMTgyMTAxWjCBnTELMAkGA1UEBhMCVVMxEDAOBgNVBAgM +B01vbnRhbmExEDAOBgNVBAcMB0JvemVtYW4xGjAYBgNVBAoMEUVsbGlwdGljIC0g +UlNBc2lnMRMwEQYDVQQLDApFQ0MtUlNBc2lnMRgwFgYDVQQDDA93d3cud29sZnNz +bC5jb20xHzAdBgkqhkiG9w0BCQEWEGluZm9Ad29sZnNzbC5jb20wWTATBgcqhkjO +PQIBBggqhkjOPQMBBwNCAAS7M6xMJ1BKxkqlBMM83p8223ItzpTqK/rLIAk5LBbo +YQLpr03TApOaMVuXkiF/8M8Y2pERAjSG6CBYMwuANInYo4H8MIH5MB0GA1UdDgQW +BBRdXSbvrH42+Zt2FStKJQIj77KJMDCByQYDVR0jBIHBMIG+gBQnjmcRdMMmHT/t +M2OzpNgdMOXo1aGBmqSBlzCBlDELMAkGA1UEBhMCVVMxEDAOBgNVBAgMB01vbnRh +bmExEDAOBgNVBAcMB0JvemVtYW4xETAPBgNVBAoMCFNhd3Rvb3RoMRMwEQYDVQQL +DApDb25zdWx0aW5nMRgwFgYDVQQDDA93d3cud29sZnNzbC5jb20xHzAdBgkqhkiG +9w0BCQEWEGluZm9Ad29sZnNzbC5jb22CCQDZgDrD0vTaNzAMBgNVHRMEBTADAQH/ +MA0GCSqGSIb3DQEBCwUAA4IBAQCsK6nZFTuaQvuGK8HyGHymyicLSIFkIDvTT+6V +1MX9X8fWq6FBhczhFuH9zoqvlSfy8Ho9WV06XQOZy0xcGTWcsm5+KxDif+8UNXnK +Z+tRqem7X1KvnXmAtTFc8CDKx+mbKYLEpHQKKnbqrVmi+aLPU0ARrBre/Ksolp/P +/7l0MZXEbdJ2wZOXdaafaaN9knW4J6K9TUtUEbSKQ/L8EKWC+1FFV4YAhXGRITdc +n/NoBq6ehkaNS+PQQqTPwV2VvBqS+EQeoBvImEGvjpRBYGmxfI5wzohCRDotP95u +OqrRZL4DaGC2rOVEwbvxyUCQwsmP7DKd4LRLGufamZT+4rYq +-----END CERTIFICATE----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-ecc.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-ecc.pem new file mode 100644 index 0000000..1957e0e --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-ecc.pem @@ -0,0 +1,54 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 12841786837162396166 (0xb2373116f65a0a06) + Signature Algorithm: ecdsa-with-SHA256 + Issuer: C=US, ST=Washington, L=Seattle, O=Eliptic, OU=ECC, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Validity + Not Before: May 7 18:21:01 2015 GMT + Not After : Jan 31 18:21:01 2018 GMT + Subject: C=US, ST=Washington, L=Seattle, O=Eliptic, OU=ECC, CN=www.wolfssl.com/emailAddress=info@wolfssl.com + Subject Public Key Info: + Public Key Algorithm: id-ecPublicKey + Public-Key: (256 bit) + pub: + 04:bb:33:ac:4c:27:50:4a:c6:4a:a5:04:c3:3c:de: + 9f:36:db:72:2d:ce:94:ea:2b:fa:cb:20:09:39:2c: + 16:e8:61:02:e9:af:4d:d3:02:93:9a:31:5b:97:92: + 21:7f:f0:cf:18:da:91:11:02:34:86:e8:20:58:33: + 0b:80:34:89:d8 + ASN1 OID: prime256v1 + X509v3 extensions: + X509v3 Subject Key Identifier: + 5D:5D:26:EF:AC:7E:36:F9:9B:76:15:2B:4A:25:02:23:EF:B2:89:30 + X509v3 Authority Key Identifier: + keyid:5D:5D:26:EF:AC:7E:36:F9:9B:76:15:2B:4A:25:02:23:EF:B2:89:30 + DirName:/C=US/ST=Washington/L=Seattle/O=Eliptic/OU=ECC/CN=www.wolfssl.com/emailAddress=info@wolfssl.com + serial:B2:37:31:16:F6:5A:0A:06 + + X509v3 Basic Constraints: + CA:TRUE + Signature Algorithm: ecdsa-with-SHA256 + 30:45:02:20:35:25:33:ea:7c:3b:e2:2e:ed:e4:2e:9a:91:f1: + c3:86:ff:a7:27:35:a9:f6:29:d6:f8:d5:9a:0b:35:f1:21:c7: + 02:21:00:bc:79:f7:fd:66:d4:d3:46:61:e4:19:e5:f7:74:03: + 83:27:f8:26:c0:86:15:a9:e2:10:e3:ad:6b:b9:1c:1d:eb +-----BEGIN CERTIFICATE----- +MIIDDzCCArWgAwIBAgIJALI3MRb2WgoGMAoGCCqGSM49BAMCMIGPMQswCQYDVQQG +EwJVUzETMBEGA1UECAwKV2FzaGluZ3RvbjEQMA4GA1UEBwwHU2VhdHRsZTEQMA4G +A1UECgwHRWxpcHRpYzEMMAoGA1UECwwDRUNDMRgwFgYDVQQDDA93d3cud29sZnNz +bC5jb20xHzAdBgkqhkiG9w0BCQEWEGluZm9Ad29sZnNzbC5jb20wHhcNMTUwNTA3 +MTgyMTAxWhcNMTgwMTMxMTgyMTAxWjCBjzELMAkGA1UEBhMCVVMxEzARBgNVBAgM +Cldhc2hpbmd0b24xEDAOBgNVBAcMB1NlYXR0bGUxEDAOBgNVBAoMB0VsaXB0aWMx +DDAKBgNVBAsMA0VDQzEYMBYGA1UEAwwPd3d3LndvbGZzc2wuY29tMR8wHQYJKoZI +hvcNAQkBFhBpbmZvQHdvbGZzc2wuY29tMFkwEwYHKoZIzj0CAQYIKoZIzj0DAQcD +QgAEuzOsTCdQSsZKpQTDPN6fNttyLc6U6iv6yyAJOSwW6GEC6a9N0wKTmjFbl5Ih +f/DPGNqREQI0huggWDMLgDSJ2KOB9zCB9DAdBgNVHQ4EFgQUXV0m76x+NvmbdhUr +SiUCI++yiTAwgcQGA1UdIwSBvDCBuYAUXV0m76x+NvmbdhUrSiUCI++yiTChgZWk +gZIwgY8xCzAJBgNVBAYTAlVTMRMwEQYDVQQIDApXYXNoaW5ndG9uMRAwDgYDVQQH +DAdTZWF0dGxlMRAwDgYDVQQKDAdFbGlwdGljMQwwCgYDVQQLDANFQ0MxGDAWBgNV +BAMMD3d3dy53b2xmc3NsLmNvbTEfMB0GCSqGSIb3DQEJARYQaW5mb0B3b2xmc3Ns +LmNvbYIJALI3MRb2WgoGMAwGA1UdEwQFMAMBAf8wCgYIKoZIzj0EAwIDSAAwRQIg +NSUz6nw74i7t5C6akfHDhv+nJzWp9inW+NWaCzXxIccCIQC8eff9ZtTTRmHkGeX3 +dAODJ/gmwIYVqeIQ461ruRwd6w== +-----END CERTIFICATE----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-key.der b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-key.der new file mode 100644 index 0000000..868f054 Binary files /dev/null and b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-key.der differ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-key.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-key.pem new file mode 100644 index 0000000..d1627f4 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-key.pem @@ -0,0 +1,27 @@ +-----BEGIN RSA PRIVATE KEY----- +MIIEpQIBAAKCAQEAwJUI4VdB8nFtt9JFQScBZcZFrvK8JDC4lc4vTtb2HIi8fJ/7 +qGd//lycUXX3isoH5zUvj+G9e8AvfKtkqBf8yl17uuAh5XIuby6G2JVz2qwbU7lf +P9cZDSVP4WNjUYsLZD+tQ7ilHFw0s64AoGPF9n8LWWh4c6aMGKkCba/DGQEuuBDj +xsxAtGmjRjNph27Euxem8+jdrXO8ey8htf1mUQy9VLPhbV8cvCNz0QkDiRTSELlk +wyrQoZZKvOHUGlvHoMDBY3gPRDcwMpaAMiOVoXe6E9KXc+JdJclqDcM5YKS0sGlC +Qgnp2Ai8MyCzWCKnquvE4eZhg8XSlt/Z0E+t1wIDAQABAoIBAQCa0DQPUmIFUAHv +n+1kbsLE2hryhNeSEEiSxOlq64t1bMZ5OPLJckqGZFSVd8vDmp231B2kAMieTuTd +x7pnFsF0vKnWlI8rMBr77d8hBSPZSjm9mGtlmrjcxH3upkMVLj2+HSJgKnMw1T7Y +oqyGQy7E9WReP4l1DxHYUSVOn9iqo85gs+KK2X4b8GTKmlsFC1uqy+XjP24yIgXz +0PrvdFKB4l90073/MYNFdfpjepcu1rYZxpIm5CgGUFAOeC6peA0Ul7QS2DFAq6EB +QcIw+AdfFuRhd9Jg8p+N6PS662PeKpeB70xs5lU0USsoNPRTHMRYCj+7r7X3SoVD +LTzxWFiBAoGBAPIsVHY5I2PJEDK3k62vvhl1loFk5rW4iUJB0W3QHBv4G6xpyzY8 +ZH3c9Bm4w2CxV0hfUk9ZOlV/MsAZQ1A/rs5vF/MOn0DKTq0VO8l56cBZOHNwnAp8 +yTpIMqfYSXUKhcLC/RVz2pkJKmmanwpxv7AEpox6Wm9IWlQ7xrFTF9/nAoGBAMuT +3ncVXbdcXHzYkKmYLdZpDmOzo9ymzItqpKISjI57SCyySzfcBhh96v52odSh6T8N +zRtfr1+elltbD6F8r7ObkNtXczrtsCNErkFPHwdCEyNMy/r0FKTV9542fFufqDzB +hV900jkt/9CE3/uzIHoumxeu5roLrl9TpFLtG8SRAoGBAOyY2rvV/vlSSn0CVUlv +VW5SL4SjK7OGYrNU0mNS2uOIdqDvixWl0xgUcndex6MEH54ZYrUbG57D8rUy+UzB +qusMJn3UX0pRXKRFBnBEp1bA1CIUdp7YY1CJkNPiv4GVkjFBhzkaQwsYpVMfORpf +H0O8h2rfbtMiAP4imHBOGhkpAoGBAIpBVihRnl/Ungs7mKNU8mxW1KrpaTOFJAza +1AwtxL9PAmk4fNTm3Ezt1xYRwz4A58MmwFEC3rt1nG9WnHrzju/PisUr0toGakTJ +c/5umYf4W77xfOZltU9s8MnF/xbKixsX4lg9ojerAby/QM5TjI7t7+5ZneBj5nxe +9Y5L8TvBAoGATUX5QIzFW/QqGoq08hysa+kMVja3TnKW1eWK0uL/8fEYEz2GCbjY +dqfJHHFSlDBD4PF4dP1hG0wJzOZoKnGtHN9DvFbbpaS+NXCkXs9P/ABVmTo9I89n +WvUi+LUp0EQR6zUuRr79jhiyX6i/GTKh9dwD5nyaHwx8qbAOITc78bA= +-----END RSA PRIVATE KEY----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-keyEnc.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-keyEnc.pem new file mode 100644 index 0000000..e5ab57d --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-keyEnc.pem @@ -0,0 +1,30 @@ +-----BEGIN RSA PRIVATE KEY----- +Proc-Type: 4,ENCRYPTED +DEK-Info: DES-CBC,136C7D8A69656668 + +jvNTyPaztxPIoAzbdmZnD0Zw2+60tMxNc0GMHNmeOyG25aHP/dT+TWiKFpFVkkkY +uoCIhYUyw7gmpw+CnRJwWd+ans4nrvAjwy5oWJvarvsyUpjqvnPoIlAqd+d4TDKN +eESzcI76+gHdisAtCrQD+fGqgTZhli5TgDbnpasL/QnY2qDlutvakkVw7gPXe156 +2Phy8WN+efr65J6wt3K/dj7Datl9u4JeHQK81gYyWBVX+EagEjPGDzkFQCj9Z0q7 +8K3iB5GW1JAqJS0IfZPB40AnSTF/n1TL1SN3qfU3l7hTGNrx9o7580bgDEoAR7pI +F8eZlS15KHtZmh11AnU1KTKZ6kmgnNqeMTGMN6N0ct2wMKW1dV87eTDlF0oiR2ol +XwtFgKmrIjfpmzkdWjbJmWnGMjD56KdiFZga/ZyKMsPrVoYLgfJEpn36iQspfygx +HCGNTf0PjIsjEWU0WyQiF86t+c45W3wNFsv/AxVyfMl+su02yrd6u2ecuQDir3Cs +b2k8IKtQgVe/NIpEWLKuiHG5oedIPPQyDYK5uq+gHxCGeOoKnWlsWFEHZRiza4X5 +tbgTrJB8Sw0ENWrvVGGmQZN4pSImlsMwzQ2qik5CQ00N1b3+56/obn0z75I3bUSb +tC5g8DRjl6oclAenNgh/MYMT287y5W2dD4npxHcekX4O3J2CDXNfg4vV2j5GRxtg +LVJdYE2p7bpYePCDHrYng8b9ubBprx0CrEnkIvvtUjzNPf6VDL0+MBKl+XgR2/nz +iRqTuZnlGGOyM+KYDwXpgwfs/HfvFGksxTAlO/40GkGh+WGPaIoNyCK0SgQKhyb4 +JIkR0vd2/yLg3lWMJrGwh7A0Gm07Z/781oURP3uWd+PaCOgGcd5ipcAjcEyuxNly +AthipWqmQWUcbf6Z2N9j3OA22Hv2Uzk8HSfi9VOZtL9svdEEZ0NnOekJgnc6stQp +bXiknlK/T5WdrWxSyCfgUq68Vf6DFfIRAVuFdJ3WHT2wVXHrDfft6D+Ne/XCxPoE +8zGmkyusaph33UHQ1oNyUbLbwcDCDSmOo8gYoedD3IwxtMA3wJRugomqosItwV8X +vkgmcy8eSE/+gZUxJEN2gnLcfKFhCkC80J6oFhmoDD6vuUnPHcFdKZgVPw2rzPk5 +Vb1kX+gpORplYmKpq1vz/ujscL4T0TmYLz02hkIS4edpW55ncTTv7JWefpRiTB1J +RB3td3me4htqR+YIDWJ+emrOmqsCG2WvpAS+MTw2mj1jYk9LL/ZYobTjSCEWmuwT +yVK6m303irR7HQDauxhslRFgoK21w63viOyj5NKIU1gQtaAANGDxcgORC1XLjjgt +oNutSQA+7P42vfHSHK4cnTBXl6V32H/GyVpdHQOZqSrqIjgLmUZodSmRPROxosZF +a46B1O7m/rJFxkiKW4vod+/WqjoE0Hhfrb8rRrkRjzGeCqqSSnQ3vrunVkvF8hlA +b6FOv4ZBJL4piC1GKH+rscqke9NEiDqXN8C3iYz86jbck/Ha21yUS8T3X7N52sg+ +B3AmOGnLK6BebYeto9vZxQjacChJZSixSxLV+l9/nVQ0+mW42azHdzk0ru59TGAj +-----END RSA PRIVATE KEY----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-keyPkcs8.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-keyPkcs8.pem new file mode 100644 index 0000000..a24c5a2 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-keyPkcs8.pem @@ -0,0 +1,28 @@ +-----BEGIN PRIVATE KEY----- +MIIEvwIBADANBgkqhkiG9w0BAQEFAASCBKkwggSlAgEAAoIBAQDAlQjhV0HycW23 +0kVBJwFlxkWu8rwkMLiVzi9O1vYciLx8n/uoZ3/+XJxRdfeKygfnNS+P4b17wC98 +q2SoF/zKXXu64CHlci5vLobYlXParBtTuV8/1xkNJU/hY2NRiwtkP61DuKUcXDSz +rgCgY8X2fwtZaHhzpowYqQJtr8MZAS64EOPGzEC0aaNGM2mHbsS7F6bz6N2tc7x7 +LyG1/WZRDL1Us+FtXxy8I3PRCQOJFNIQuWTDKtChlkq84dQaW8egwMFjeA9ENzAy +loAyI5Whd7oT0pdz4l0lyWoNwzlgpLSwaUJCCenYCLwzILNYIqeq68Th5mGDxdKW +39nQT63XAgMBAAECggEBAJrQNA9SYgVQAe+f7WRuwsTaGvKE15IQSJLE6Wrri3Vs +xnk48slySoZkVJV3y8OanbfUHaQAyJ5O5N3HumcWwXS8qdaUjyswGvvt3yEFI9lK +Ob2Ya2WauNzEfe6mQxUuPb4dImAqczDVPtiirIZDLsT1ZF4/iXUPEdhRJU6f2Kqj +zmCz4orZfhvwZMqaWwULW6rL5eM/bjIiBfPQ+u90UoHiX3TTvf8xg0V1+mN6ly7W +thnGkibkKAZQUA54Lql4DRSXtBLYMUCroQFBwjD4B18W5GF30mDyn43o9LrrY94q +l4HvTGzmVTRRKyg09FMcxFgKP7uvtfdKhUMtPPFYWIECgYEA8ixUdjkjY8kQMreT +ra++GXWWgWTmtbiJQkHRbdAcG/gbrGnLNjxkfdz0GbjDYLFXSF9ST1k6VX8ywBlD +UD+uzm8X8w6fQMpOrRU7yXnpwFk4c3CcCnzJOkgyp9hJdQqFwsL9FXPamQkqaZqf +CnG/sASmjHpab0haVDvGsVMX3+cCgYEAy5PedxVdt1xcfNiQqZgt1mkOY7Oj3KbM +i2qkohKMjntILLJLN9wGGH3q/nah1KHpPw3NG1+vX56WW1sPoXyvs5uQ21dzOu2w +I0SuQU8fB0ITI0zL+vQUpNX3njZ8W5+oPMGFX3TSOS3/0ITf+7Mgei6bF67muguu +X1OkUu0bxJECgYEA7Jjau9X++VJKfQJVSW9VblIvhKMrs4Zis1TSY1La44h2oO+L +FaXTGBRyd17HowQfnhlitRsbnsPytTL5TMGq6wwmfdRfSlFcpEUGcESnVsDUIhR2 +nthjUImQ0+K/gZWSMUGHORpDCxilUx85Gl8fQ7yHat9u0yIA/iKYcE4aGSkCgYEA +ikFWKFGeX9SeCzuYo1TybFbUqulpM4UkDNrUDC3Ev08CaTh81ObcTO3XFhHDPgDn +wybAUQLeu3Wcb1acevOO78+KxSvS2gZqRMlz/m6Zh/hbvvF85mW1T2zwycX/FsqL +GxfiWD2iN6sBvL9AzlOMju3v7lmd4GPmfF71jkvxO8ECgYBNRflAjMVb9CoairTy +HKxr6QxWNrdOcpbV5YrS4v/x8RgTPYYJuNh2p8kccVKUMEPg8Xh0/WEbTAnM5mgq +ca0c30O8VtulpL41cKRez0/8AFWZOj0jz2da9SL4tSnQRBHrNS5Gvv2OGLJfqL8Z +MqH13APmfJofDHypsA4hNzvxsA== +-----END PRIVATE KEY----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-keyPkcs8Enc.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-keyPkcs8Enc.pem new file mode 100644 index 0000000..4be31a3 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-keyPkcs8Enc.pem @@ -0,0 +1,29 @@ +-----BEGIN ENCRYPTED PRIVATE KEY----- +MIIE6TAbBgkqhkiG9w0BBQMwDgQIr3AyvPqfFRQCAggABIIEyPUs6wCboqtKmExH +zfez3vfHn2cp6s3X563Bz73hYn/8vXtI/q0oDNOpgav60/N7rMy50fno3LmW0/6E ++UN4MwofmBS3lp1ZVY3KmzDy6lz5vcFo4GCCj+X6dacsyBQ4lFOge5BihQ3R9cKt +dSrd1EFKwGGu3qTDG7ajTZukmYjxuRqpyHqPO5OJO7yXxHOB7B7sSKIyJRCkkucd +oBC86kQdWraweSYj+Klza6VjKzmNzDBx9Fyhrj9XGXJ3rJLhjgNpelwX+PIMU31i +/yklI4jm0aMSoAvXgdBXZuOsnsI27GXxy//i7AOgLLWi+Bu4dJSSl5PMtespf83u +5jSysJymXiNcN6vEautGyjCujdMs5c/FEMbgubAMXymCI9DsAN+5dNMDY8Zrfqdl +hFKfctcu8BxFa+0tavJ28fOEBuEyJLsQ9OvvS7dn4AV502JRKWObfsw7fi+mMzMu +oxhYo99MRqic6a9uDmYB3SPeU31eOHiEi0n51D7Gtcn++F+IaDFwSHMirThzakGn +go3nj0yq62euzVcEuhIfTTAe3F2tqzpzznVFbs1XgrGVREJ6gp5vRgMUUGYIqQir +p5oW0HVRI4iuoSjdN4/wNAxIP9zakwYx+vWx1VXhDVEJfgNmxDRvEbF+OOz+iJCf +7A2e8L+kZ/5oC3HO8h7GdHNTUjRRdh8FUM8lGo+HbMYDznMy/bJlIP2bx9hIIha7 +U70i09glS2Z7Ei+VecJbvFzdro0vdYyGO2ef8bWwCc5JMucxDcRklWdUxK6amKJN +VpXL3TW0VYCfr1rLmZXUfBGk/KXM20/BoM04WLjeR3oiV/2b7SYK7GnJ7kBmAHHx +gnrwMDO3JvH89CwlHRizVSQl59ViqEMGLmbHThcMqkEOkFphB2xox7/IOVyp6cFn +mY0ZCrbhdX+L6t5jiyq/4us5bzF7FOBYsJr6n1Rm9b8eeOL693y/6uM3CvTJcTOb +5RqWiHgTgmefeOeUQ0/dVgvEOIWz2yqBQmHKiB4+0CGGIRwUOXBrTKSLilumsjQe +qGhJ6yw25VIpdXsMD1WVviczgRTNYjdldIJoHQdvpCEAhQ1RR3rkuIPniTumJFmY +CnjfNqjtkaZWIN1nOCmcu50tswksWEEFEfkcP1xyzhr3EVCYAoFncLTp5vHBtdmg +6KBdar40/OFGAcbDGDX1g3XEEi6jHmy0Lyz7M3DwESgaMgwzscsQLr+wMITk1IUN +yfiXHl1CQjGxhDj8KoAhdDjjPENkSlCSd1vEO+lg1/IFb1dtnL2DJp6BQt9/VLHo +Fp3pdZ7r95H20+pEhCZp0HXLNo1o8xjJQ5RWUCs1Zc1cauDOAh8lAjps6MBxTa3a +LOgTW9lgiAQ+S1g2jK4BmqbLvZUF+Z6xupc8uE3E3HhJolmDRYojMNFNmmvODa8M +CneWmj3T1KvqEToAIq46mStlTfQufSMpaJ73Wds4gmIiGwn5hIuUN6f3kybbt4f2 +4DLZXMcjYweLi9tJtFC+JaO0rS5gtX/k/ys1QSblSU5qfRu1XfwNAcZO1ReKgGYN +ymI78cSACGIcEvAwin8CdRu3W99NbMqHW9AcCETFlTsC3wNlQxyYSem75sjPaWVF +sxLy7YxEJ8tDEJZbSQ== +-----END ENCRYPTED PRIVATE KEY----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-keyPkcs8Enc12.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-keyPkcs8Enc12.pem new file mode 100644 index 0000000..f9d30d2 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-keyPkcs8Enc12.pem @@ -0,0 +1,29 @@ +-----BEGIN ENCRYPTED PRIVATE KEY----- +MIIE6jAcBgoqhkiG9w0BDAEDMA4ECAGQiv1ZBAPqAgIIAASCBMhFUVwujBcs/XvB +vmxHOJWn27QJFXXADhKYA7pRFsSx3hlLAAZfQnRuulwoKUVLbyNN7wTB5z8R2PHb +WY1R/d34PIGfYTNZs2uzw3KMn6M4gio+dHwVoMN5eidda4sO861UpTRyy99Y2UXK +tNE84qQdm+ZbjN5PjFyvfpu5jRGyJWWnvvjlbTBoMP4exHJEEVfvV/QguaL5tOHv +lZqQ9Lynx6gy+Jt2dF87rz+90MdbjZgaaxqoMx6JYmCCRpkcIjCVdtWVmrUHzbIV +ee0w1/FiIKx+m63/8DzKxAsCvYuI8dAmWbNZ4KY7kWmGZ7A4dwZaqU87gUSvSnyL +J67K7+v7Tnx2y8muBkqVMX19EP5fnFRiM16x7/PIikR4Q4zJrN7sK6+zBSeq6szh +x3N94qm3EzBYY6nJAViEggY+Z+4+SQlErxZkBRfs7hGAejG1RoyyAr0/9ojwUH9p +0J4PiDmtnOq14eraRMMeWdIu+3301cZzrZLhBGXXPq1mYcoZxpt+vKTPHPfTSyEh +FuFSVDu43s89MwHpsK5b4FAqMd/rpLoXPYEboD6ZK3mhPKiIYkpjdOpQCCjcQ6Kf +acrFXo5jz+Zafz2U80qhpWxDz3RZQC/MBCwWVS8+iNv8KoxE40SSmlCFMcXSXNwP +dTRsZnRvNX91b8UAn37+dzRE1lJX79xT51uC1UjlkVeWz/ZV5KwupJ0MvdGDNVDN +4F+GpLvd/g2Q3xx4rl1Vx+fUPh+IDRIWRmaJ5rJqqgn1pzZx4tS+0Rjoekk28SUD +DIzmZFswWus385DYhYcn6FAWf2dTq3LulJcX2DovGLiGu3TUA4JlVl3ejWvf5FZY +kQx/Z9Cf7+nW69Okuwa+DX3d8g1pFPqWyoFN5cLqiNIiolqP/pIVTlCp5WZHRCJx +HO2f+mxt7lvymOKLrlq35DywLhYYj4J8OAXI95LRLGWY5GV68f4BKcVpPweAVrHm +V2zVgCvIDqe2rlXF/hB5eQiiUa9FOaoKJ2NAhfcCar8Ty0PnYwgFpcBh1fXaxfj+ +hwv7Pb2ioRDQOgaxtvF26phms79tMxK3HnDXfBvRzIn2pATOJr5om4z4JYna6DSp +dILlW9X5U5/OATIY9DdtvZiAom36YMUfXbHjHf6cZwIgkJQP3KF+2Jd9iMhQwAmQ +xiA114zmxlXzvJqGA1LTwVDPA3VyUTQXAZg/2RroB8rTufYRTYKC37h+YXXwtCkP +gLQtG6gsWPaQ23xddLQI1pk3HvLFR3y0Zr2vR7OYbv5CFXH3pCVeKN+Y9r6c/IbC +CRS2S7iwiEuI0YTvUrfscVIQGuc3iC2mJRjCrQUB28LQ6cbCccLk/P/2ynse/lyu ++29/QLZCL3GJlYHvOL1GBnupHygTOETtVW34+j/jDjyOVvZLTuOwtzb7+8R157OI +bUQujZ9f5IRYeRNTliwsZYQXjOI+iMheWHl1kd/qV3FFO946hp9BV1TeFQwCf1Vx +b8kWLgUpZpHz5d07EBKhzSQb0OacMEm5FsS3IRRIdnmqvpMsW1wsOjE6VxkS/Ozg +QE8YGeT1F10bfcJtp2m9uVRpPfffcckW89wBsI9uLsj6pETzLtHVVyepB7NxKRtT +3ChWuLWbwCQsrzyPdms= +-----END ENCRYPTED PRIVATE KEY----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-keyPkcs8Enc2.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-keyPkcs8Enc2.pem new file mode 100644 index 0000000..297f2a0 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/server-keyPkcs8Enc2.pem @@ -0,0 +1,30 @@ +-----BEGIN ENCRYPTED PRIVATE KEY----- +MIIFDjBABgkqhkiG9w0BBQ0wMzAbBgkqhkiG9w0BBQwwDgQIxaI9IblN3acCAggA +MBQGCCqGSIb3DQMHBAi7kwdRvCrqMgSCBMjkSOSVfmu42O0q2GzFrJVr3cam9ZKe +InQsxqtgADdBxMgJJVnr360tUNPQyyvfCH//Duhz+aJIC0MQZkWR3ZSy5pfHX+vr +C3wd741VOlI44uEdzRktlPc11saMDyKS04/K9aaYIDqspOiobt9WZLQildXl1n8j +N+7Laj7A/vxJ5GUJ4hdPwQOIeuJXTDDzn+Ld12XXGH+Iw1M5Cx3tBw1TNizSnmXQ +vf/MsfsWsZbHBppCXZbF27jJA+6Bg7dGT0OZM0pI+ZQvyHr+qjog0hollY9KjwTG +h+hsM7umWFJdeRMrmkTrX/R9HY/c5I4ExNSp1AtMmFeeU8h2VTJtYcoykUU1q2pF +KHfjPghwmYromQGR4nPA9sqa9s+VMq9OaqoJDoBwNobdFr7sEtMLT08vTa0+rMX7 +bmjAF44/dVBYpBxXjTQ0pXVeb24Q00Sn6NOI4fTsBnkR+WTtuwz/L0qaGnJlh10y +sQ3+95cUtZc3SZS67yYUx5auswqT3V4JCmhJcHNi+/jHyrj9D8nVWibQ2TBmgUf+ +0NzvdKb7sraEx7PSgFWDMLoQrd2+cqsJArpY9TbLSLhBDrOVc8v/lXYuK6QI0gMd +HIwAZARUZMoI3WS6icTLYyLdQPMsFzI6U0arkbrdhjNNd3kVqeFEJ+oF0rkuAcJJ +K8eUcsby1AIBS/9tuW1gSYubmuXsZX8xbYbJnHUqGOTAVa7jo8eVUTiyUfPXa+0N +s1tTpZXtOOlqncZ08mPHppshdKF2cpuh0JNjiR6fHvXytGWFGMsKtxdwKs/14UCg +qoTW0EQU4ONfBxR2PtX8PlNV4bOt704HP8Vc0H9JV2uWpJaLRzY2bBiPgKcrO9Eh +83zFrPu/0obBQTxnP3mMihxvCndflHQqeJ0V1YYw9n4+XbgBqULXDQs7OetRohnY +gYyc//NdC2I8mbdabFYvUTWSH6oMA6lqkwTjTTwtn5E8BJkRi1sIq4jNFUekpm2T +5AwP7xWn//PM+B12CPoIgYtYT6Yhbf8arXuGU28y1Ahhi/hKcpR9HRPQeyaR62vi +skjjycfn38wcj0WrIVnOceGgPa3EBrkkTaPUHvMQ5G/xzMZ82o3CnmwdnH+lp3eg +TLcLm8Yp9InkMJNVOrGLxFvmTljl3h9x2JVuE0wtuWt91QVmfCZo0k3Cx46ad7xB +eK20veTy+PySy2U3W1twGfsXXXRwaQiXXRrgPciK0LcGXZneShZuebk04U31sq4F +rYaMAzIDDmvwbjh+UpNcl1VdBDGGePxzzOD3HHYPbm240HVMPuS85P2kFjak3PdJ +GqsRUS1SRp1e451aFGjzggPLXFjAfDMaxrgjSWapRzu78i+xvcvf69979oX0KO9Y +KMSC14RnmnT1+UdKxX+p9r1AwfH/vJxM34AOSva1uLiSJckRGYGOzuaYsTT9ZAx/ +q3CNALF4qFUMWmJnvQDYmCUnw6lJl3CazbtV5RI2ILQX6ZHR6YAHT5hYY43k+AnZ +mFW6BGKoX/f4iVqYtjQWiGWAJAf6C9+548O2t9MiVcgQf4Nvj6lFLM00pzFn7jW4 +DsDFUBmmrSF8wfR7SRpOc/ViVZBRleYPLsMu0tmD29fowqqBY0MEkxqSahFAGTgk +sao= +-----END ENCRYPTED PRIVATE KEY----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/taoCert.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/taoCert.txt new file mode 100644 index 0000000..3c954a7 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/taoCert.txt @@ -0,0 +1,176 @@ + +***** Create a self signed cert ************ + +1) openssl genrsa 1024 > client-key.pem + +2) openssl req -new -x509 -nodes -sha1 -days 1000 -key client-key.pem > client-cert.pem + +3) note md5 would be -md5 + +-- adding metadata to beginning + +3) openssl x509 -in client-cert.pem -text > tmp.pem + +4) mv tmp.pem client-cert.pem + + +***** Create a CA, signing authority ********** + +same as self signed, use ca prefix instead of client + + +***** Create a cert signed by CA ************** + +1) openssl req -newkey rsa:1024 -sha1 -days 1000 -nodes -keyout server-key.pem > server-req.pem + +* note if using exisitng key do: -new -key keyName + +2) copy ca-key.pem ca-cert.srl (why ????) + +3) openssl x509 -req -in server-req.pem -days 1000 -sha1 -CA ca-cert.pem -CAkey ca-key.pem -set_serial 01 > server-cert.pem + + +***** Adding Subject Key ID and Authentication Key ID extensions to a cert ***** + +Create a config file for OpenSSL with the example contents: + + [skidakid] + subjectKeyIdentifier=hash + authorityKeyIdentifier=keyid + +Add to the openssl command for creating a cert signed by a CA step 3 the +following options: + + -extfile -extensions skidakid + +anywhere before the redirect. This will add the cert's public key hash as the +Subject Key Identifier, and the signer's SKID as the Authentication Key ID. + + +***** To create a dsa cert ******************** + +1) openssl dsaparam 512 > dsa512.param # creates group params + +2) openssl gendsa dsa512.param > dsa512.pem # creates private key + +3) openssl req -new -x509 -nodes -days 1000 -key dsa512.pem > dsa-cert.pem + + + + +***** To convert from PEM to DER ************** + +a) openssl x509 -in cert.pem -inform PEM -out cert.der -outform DER + +to convert rsa private PEM to DER : + +b) openssl rsa -in key.pem -outform DER -out key.der + + +**** To encrypt rsa key already in pem ********** + +a) openssl rsa server-keyEnc.pem + +note location of des, pass = yassl123 + + +*** To make a public key from a private key ****** + + +openssl rsa -in 1024rsa.priv -pubout -out 1024rsa.pub + + +**** To convert to pkcs8 ******* + +openssl pkcs8 -nocrypt -topk8 -in server-key.pem -out server-keyPkcs8.pem + + +**** To convert to pkcs8 encrypted ******* + +openssl pkcs8 -topk8 -in server-key.pem -out server-keyPkcs8Enc.pem + +passwd: yassl123 + +to use PKCS#5 v2 instead of v1.5 which is default add + +-v2 des3 # file Pkcs8Enc2 + +to use PKCS#12 instead use -v1 witch a 12 algo like + +-v1 PBE-SHA1-3DES # file Pkcs8Enc12 , see man pkcs8 for more info +-v1 PBE-SHA1-RC4-128 # no longer file Pkcs8Enc12, arc4 now off by default + + +**** To convert from pkcs8 to traditional **** + +openssl pkcs8 -nocrypt -in server-keyPkcs8.pem -out server-key.pem + + +*** DH paramters *** + +openssl dhparam 2048 > dh2048.param + +to add metadata + +openssl dhparam -in dh2048.param -text > dh2048.pem + +**** ECC ****** + +1) make a key + + to see types available do + openssl ecparam -list_curves + + make a new key + openssl ecparam -genkey -text -name secp256r1 -out ecc-key.pem + + convert to compressed + openssl ec -in ecc-key.pem -conv_form compressed -out ecc-key-comp.pem + +*** CRL *** + +1) create a crl + +a) openssl ca -gencrl -crldays 120 -out crl.pem -keyfile ./ca-key.pem -cert ./ca-cert.pem + +Error No ./CA root/index.txt so: + +b) touch ./CA root/index.txt + +a) again + +Error No ./CA root/crlnumber so: + +c) touch ./CA root/crlnumber + +a) again + +Error unable to load CRL number + +d) add '01' to crlnumber file + +a) again + +2) view crl file + +openssl crl -in crl.pem -text + +3) revoke + +openssl ca -revoke server-cert.pem -keyfile ./ca-key.pem -cert ./ca-cert.pem + +Then regenerate crl with a) + +4) verify + +openssl verify -CAfile ./ca-cert.pem ./server-cert.pem + +OK + +Make file with both ca and crl + +cat ca-cert.pem crl.pem > ca-crl.pem + +openssl verify -CAfile ./ca-crl.pem -crl_check ./ca-cert.pem + +revoked diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/wolfssl-website-ca.pem b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/wolfssl-website-ca.pem new file mode 100644 index 0000000..704a29f --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/certs/wolfssl-website-ca.pem @@ -0,0 +1,83 @@ +Certificate: + Data: + Version: 3 (0x2) + Serial Number: 0 (0x0) + Signature Algorithm: sha1WithRSAEncryption + Issuer: C=US, O=The Go Daddy Group, Inc., OU=Go Daddy Class 2 Certification Authority + Validity + Not Before: Jun 29 17:06:20 2004 GMT + Not After : Jun 29 17:06:20 2034 GMT + Subject: C=US, O=The Go Daddy Group, Inc., OU=Go Daddy Class 2 Certification Authority + Subject Public Key Info: + Public Key Algorithm: rsaEncryption + Public-Key: (2048 bit) + Modulus: + 00:de:9d:d7:ea:57:18:49:a1:5b:eb:d7:5f:48:86: + ea:be:dd:ff:e4:ef:67:1c:f4:65:68:b3:57:71:a0: + 5e:77:bb:ed:9b:49:e9:70:80:3d:56:18:63:08:6f: + da:f2:cc:d0:3f:7f:02:54:22:54:10:d8:b2:81:d4: + c0:75:3d:4b:7f:c7:77:c3:3e:78:ab:1a:03:b5:20: + 6b:2f:6a:2b:b1:c5:88:7e:c4:bb:1e:b0:c1:d8:45: + 27:6f:aa:37:58:f7:87:26:d7:d8:2d:f6:a9:17:b7: + 1f:72:36:4e:a6:17:3f:65:98:92:db:2a:6e:5d:a2: + fe:88:e0:0b:de:7f:e5:8d:15:e1:eb:cb:3a:d5:e2: + 12:a2:13:2d:d8:8e:af:5f:12:3d:a0:08:05:08:b6: + 5c:a5:65:38:04:45:99:1e:a3:60:60:74:c5:41:a5: + 72:62:1b:62:c5:1f:6f:5f:1a:42:be:02:51:65:a8: + ae:23:18:6a:fc:78:03:a9:4d:7f:80:c3:fa:ab:5a: + fc:a1:40:a4:ca:19:16:fe:b2:c8:ef:5e:73:0d:ee: + 77:bd:9a:f6:79:98:bc:b1:07:67:a2:15:0d:dd:a0: + 58:c6:44:7b:0a:3e:62:28:5f:ba:41:07:53:58:cf: + 11:7e:38:74:c5:f8:ff:b5:69:90:8f:84:74:ea:97: + 1b:af + Exponent: 3 (0x3) + X509v3 extensions: + X509v3 Subject Key Identifier: + D2:C4:B0:D2:91:D4:4C:11:71:B3:61:CB:3D:A1:FE:DD:A8:6A:D4:E3 + X509v3 Authority Key Identifier: + keyid:D2:C4:B0:D2:91:D4:4C:11:71:B3:61:CB:3D:A1:FE:DD:A8:6A:D4:E3 + DirName:/C=US/O=The Go Daddy Group, Inc./OU=Go Daddy Class 2 Certification Authority + serial:00 + + X509v3 Basic Constraints: + CA:TRUE + Signature Algorithm: sha1WithRSAEncryption + 32:4b:f3:b2:ca:3e:91:fc:12:c6:a1:07:8c:8e:77:a0:33:06: + 14:5c:90:1e:18:f7:08:a6:3d:0a:19:f9:87:80:11:6e:69:e4: + 96:17:30:ff:34:91:63:72:38:ee:cc:1c:01:a3:1d:94:28:a4: + 31:f6:7a:c4:54:d7:f6:e5:31:58:03:a2:cc:ce:62:db:94:45: + 73:b5:bf:45:c9:24:b5:d5:82:02:ad:23:79:69:8d:b8:b6:4d: + ce:cf:4c:ca:33:23:e8:1c:88:aa:9d:8b:41:6e:16:c9:20:e5: + 89:9e:cd:3b:da:70:f7:7e:99:26:20:14:54:25:ab:6e:73:85: + e6:9b:21:9d:0a:6c:82:0e:a8:f8:c2:0c:fa:10:1e:6c:96:ef: + 87:0d:c4:0f:61:8b:ad:ee:83:2b:95:f8:8e:92:84:72:39:eb: + 20:ea:83:ed:83:cd:97:6e:08:bc:eb:4e:26:b6:73:2b:e4:d3: + f6:4c:fe:26:71:e2:61:11:74:4a:ff:57:1a:87:0f:75:48:2e: + cf:51:69:17:a0:02:12:61:95:d5:d1:40:b2:10:4c:ee:c4:ac: + 10:43:a6:a5:9e:0a:d5:95:62:9a:0d:cf:88:82:c5:32:0c:e4: + 2b:9f:45:e6:0d:9f:28:9c:b1:b9:2a:5a:57:ad:37:0f:af:1d: + 7f:db:bd:9f +-----BEGIN CERTIFICATE----- +MIIEADCCAuigAwIBAgIBADANBgkqhkiG9w0BAQUFADBjMQswCQYDVQQGEwJVUzEh +MB8GA1UEChMYVGhlIEdvIERhZGR5IEdyb3VwLCBJbmMuMTEwLwYDVQQLEyhHbyBE +YWRkeSBDbGFzcyAyIENlcnRpZmljYXRpb24gQXV0aG9yaXR5MB4XDTA0MDYyOTE3 +MDYyMFoXDTM0MDYyOTE3MDYyMFowYzELMAkGA1UEBhMCVVMxITAfBgNVBAoTGFRo +ZSBHbyBEYWRkeSBHcm91cCwgSW5jLjExMC8GA1UECxMoR28gRGFkZHkgQ2xhc3Mg +MiBDZXJ0aWZpY2F0aW9uIEF1dGhvcml0eTCCASAwDQYJKoZIhvcNAQEBBQADggEN +ADCCAQgCggEBAN6d1+pXGEmhW+vXX0iG6r7d/+TvZxz0ZWizV3GgXne77ZtJ6XCA +PVYYYwhv2vLM0D9/AlQiVBDYsoHUwHU9S3/Hd8M+eKsaA7Ugay9qK7HFiH7Eux6w +wdhFJ2+qN1j3hybX2C32qRe3H3I2TqYXP2WYktsqbl2i/ojgC95/5Y0V4evLOtXi +EqITLdiOr18SPaAIBQi2XKVlOARFmR6jYGB0xUGlcmIbYsUfb18aQr4CUWWoriMY +avx4A6lNf4DD+qta/KFApMoZFv6yyO9ecw3ud72a9nmYvLEHZ6IVDd2gWMZEewo+ +YihfukEHU1jPEX44dMX4/7VpkI+EdOqXG68CAQOjgcAwgb0wHQYDVR0OBBYEFNLE +sNKR1EwRcbNhyz2h/t2oatTjMIGNBgNVHSMEgYUwgYKAFNLEsNKR1EwRcbNhyz2h +/t2oatTjoWekZTBjMQswCQYDVQQGEwJVUzEhMB8GA1UEChMYVGhlIEdvIERhZGR5 +IEdyb3VwLCBJbmMuMTEwLwYDVQQLEyhHbyBEYWRkeSBDbGFzcyAyIENlcnRpZmlj +YXRpb24gQXV0aG9yaXR5ggEAMAwGA1UdEwQFMAMBAf8wDQYJKoZIhvcNAQEFBQAD +ggEBADJL87LKPpH8EsahB4yOd6AzBhRckB4Y9wimPQoZ+YeAEW5p5JYXMP80kWNy +OO7MHAGjHZQopDH2esRU1/blMVgDoszOYtuURXO1v0XJJLXVggKtI3lpjbi2Tc7P +TMozI+gciKqdi0FuFskg5YmezTvacPd+mSYgFFQlq25zheabIZ0KbIIOqPjCDPoQ +HmyW74cNxA9hi63ugyuV+I6ShHI56yDqg+2DzZduCLzrTia2cyvk0/ZM/iZx4mER +dEr/VxqHD3VILs9RaRegAhJhldXRQLIQTO7ErBBDpqWeCtWVYpoNz4iCxTIM5Cuf +ReYNnyicsbkqWletNw+vHX/bvZ8= +-----END CERTIFICATE----- diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/config.in b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/config.in new file mode 100644 index 0000000..e040f36 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/config.in @@ -0,0 +1,178 @@ +/* config.in. Generated from configure.ac by autoheader. */ + +/* Define if building universal (internal helper macro) */ +#undef AC_APPLE_UNIVERSAL_BUILD + +/* Define to 1 to enable debugging code. */ +#undef DEBUG + +/* Define to 1 if you have the header file. */ +#undef HAVE_ARPA_INET_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_DLFCN_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_ERRNO_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_FCNTL_H + +/* Define to 1 if you have the `getaddrinfo' function. */ +#undef HAVE_GETADDRINFO + +/* Define to 1 if you have the `gethostbyname' function. */ +#undef HAVE_GETHOSTBYNAME + +/* Define to 1 if you have the `gettimeofday' function. */ +#undef HAVE_GETTIMEOFDAY + +/* Define to 1 if you have the `inet_ntoa' function. */ +#undef HAVE_INET_NTOA + +/* Define to 1 if you have the header file. */ +#undef HAVE_INTTYPES_H + +/* Define to 1 if you have the `network' library (-lnetwork). */ +#undef HAVE_LIBNETWORK + +/* Define to 1 if you have the `pthread' library (-lpthread). */ +#undef HAVE_LIBPTHREAD + +/* Define to 1 if you have the header file. */ +#undef HAVE_LIMITS_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_MEMORY_H + +/* Define to 1 if you have the `memset' function. */ +#undef HAVE_MEMSET + +/* Define to 1 if you have the header file. */ +#undef HAVE_NETDB_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_NETINET_IN_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_PCAP_PCAP_H + +/* Define if you have POSIX threads libraries and header files. */ +#undef HAVE_PTHREAD + +/* Have PTHREAD_PRIO_INHERIT. */ +#undef HAVE_PTHREAD_PRIO_INHERIT + +/* Define to 1 if you have the `socket' function. */ +#undef HAVE_SOCKET + +/* Define to 1 if you have the header file. */ +#undef HAVE_STDDEF_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STDINT_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STDLIB_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STRINGS_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STRING_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_IOCTL_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_SOCKET_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_STAT_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_TIME_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_TYPES_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_UNISTD_H + +/* Define to 1 or 0, depending whether the compiler supports simple visibility + declarations. */ +#undef HAVE_VISIBILITY + +/* Define to 1 if the system has the type `__uint128_t'. */ +#undef HAVE___UINT128_T + +/* Define to the sub-directory in which libtool stores uninstalled libraries. + */ +#undef LT_OBJDIR + +/* Define to 1 if your C compiler doesn't accept -c and -o together. */ +#undef NO_MINUS_C_MINUS_O + +/* Define to the address where bug reports for this package should be sent. */ +#undef PACKAGE_BUGREPORT + +/* Define to the full name of this package. */ +#undef PACKAGE_NAME + +/* Define to the full name and version of this package. */ +#undef PACKAGE_STRING + +/* Define to the one symbol short name of this package. */ +#undef PACKAGE_TARNAME + +/* Define to the home page for this package. */ +#undef PACKAGE_URL + +/* Define to the version of this package. */ +#undef PACKAGE_VERSION + +/* Define to necessary symbol if this constant uses a non-standard name on + your system. */ +#undef PTHREAD_CREATE_JOINABLE + +/* The size of `long', as computed by sizeof. */ +#undef SIZEOF_LONG + +/* The size of `long long', as computed by sizeof. */ +#undef SIZEOF_LONG_LONG + +/* Define to 1 if you have the ANSI C header files. */ +#undef STDC_HEADERS + +/* If the compiler supports a TLS storage class define it to that here */ +#undef TLS + +/* Define if the code was built from VCS. */ +#undef VCS_CHECKOUT + +/* VCS system */ +#undef VCS_SYSTEM + +/* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most + significant byte first (like Motorola and SPARC, unlike Intel). */ +#if defined AC_APPLE_UNIVERSAL_BUILD +# if defined __BIG_ENDIAN__ +# define WORDS_BIGENDIAN 1 +# endif +#else +# ifndef WORDS_BIGENDIAN +# undef WORDS_BIGENDIAN +# endif +#endif + +/* Define for Solaris 2.5.1 so the uint8_t typedef from , + , or is not used. If the typedef were allowed, the + #define below would cause a syntax error. */ +#undef _UINT8_T + +/* Define to `unsigned int' if does not define. */ +#undef size_t + +/* Define to the type of an unsigned integer type of width exactly 8 bits if + such a type exists and the standard includes do not define it. */ +#undef uint8_t diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/configure b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/configure new file mode 100644 index 0000000..6523b8c --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/configure @@ -0,0 +1,27938 @@ +#! /bin/sh +# Guess values for system-dependent variables and create Makefiles. +# Generated by GNU Autoconf 2.69 for wolfssl 3.6.0. +# +# Report bugs to . +# +# +# Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc. +# +# +# This configure script is free software; the Free Software Foundation +# gives unlimited permission to copy, distribute and modify it. +## -------------------- ## +## M4sh Initialization. ## +## -------------------- ## + +# Be more Bourne compatible +DUALCASE=1; export DUALCASE # for MKS sh +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi + + +as_nl=' +' +export as_nl +# Printing a long string crashes Solaris 7 /usr/bin/printf. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo +# Prefer a ksh shell builtin over an external printf program on Solaris, +# but without wasting forks for bash or zsh. +if test -z "$BASH_VERSION$ZSH_VERSION" \ + && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='print -r --' + as_echo_n='print -rn --' +elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='printf %s\n' + as_echo_n='printf %s' +else + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' + as_echo_n='/usr/ucb/echo -n' + else + as_echo_body='eval expr "X$1" : "X\\(.*\\)"' + as_echo_n_body='eval + arg=$1; + case $arg in #( + *"$as_nl"*) + expr "X$arg" : "X\\(.*\\)$as_nl"; + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; + esac; + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" + ' + export as_echo_n_body + as_echo_n='sh -c $as_echo_n_body as_echo' + fi + export as_echo_body + as_echo='sh -c $as_echo_body as_echo' +fi + +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + PATH_SEPARATOR=: + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || + PATH_SEPARATOR=';' + } +fi + + +# IFS +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent editors from complaining about space-tab. +# (If _AS_PATH_WALK were called with IFS unset, it would disable word +# splitting by setting IFS to empty value.) +IFS=" "" $as_nl" + +# Find who we are. Look in the path if we contain no directory separator. +as_myself= +case $0 in #(( + *[\\/]* ) as_myself=$0 ;; + *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + done +IFS=$as_save_IFS + + ;; +esac +# We did not find ourselves, most probably we were run as `sh COMMAND' +# in which case we are not to be found in the path. +if test "x$as_myself" = x; then + as_myself=$0 +fi +if test ! -f "$as_myself"; then + $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + exit 1 +fi + +# Unset variables that we do not need and which cause bugs (e.g. in +# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" +# suppresses any "Segmentation fault" message there. '((' could +# trigger a bug in pdksh 5.2.14. +for as_var in BASH_ENV ENV MAIL MAILPATH +do eval test x\${$as_var+set} = xset \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done +PS1='$ ' +PS2='> ' +PS4='+ ' + +# NLS nuisances. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# CDPATH. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + +# Use a proper internal environment variable to ensure we don't fall + # into an infinite loop, continuously re-executing ourselves. + if test x"${_as_can_reexec}" != xno && test "x$CONFIG_SHELL" != x; then + _as_can_reexec=no; export _as_can_reexec; + # We cannot yet assume a decent shell, so we have to provide a +# neutralization value for shells without unset; and this also +# works around shells that cannot unset nonexistent variables. +# Preserve -v and -x to the replacement shell. +BASH_ENV=/dev/null +ENV=/dev/null +(unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV +case $- in # (((( + *v*x* | *x*v* ) as_opts=-vx ;; + *v* ) as_opts=-v ;; + *x* ) as_opts=-x ;; + * ) as_opts= ;; +esac +exec $CONFIG_SHELL $as_opts "$as_myself" ${1+"$@"} +# Admittedly, this is quite paranoid, since all the known shells bail +# out after a failed `exec'. +$as_echo "$0: could not re-execute with $CONFIG_SHELL" >&2 +as_fn_exit 255 + fi + # We don't want this to propagate to other subprocesses. + { _as_can_reexec=; unset _as_can_reexec;} +if test "x$CONFIG_SHELL" = x; then + as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on \${1+\"\$@\"}, which + # is contrary to our usage. Disable this feature. + alias -g '\${1+\"\$@\"}'='\"\$@\"' + setopt NO_GLOB_SUBST +else + case \`(set -o) 2>/dev/null\` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi +" + as_required="as_fn_return () { (exit \$1); } +as_fn_success () { as_fn_return 0; } +as_fn_failure () { as_fn_return 1; } +as_fn_ret_success () { return 0; } +as_fn_ret_failure () { return 1; } + +exitcode=0 +as_fn_success || { exitcode=1; echo as_fn_success failed.; } +as_fn_failure && { exitcode=1; echo as_fn_failure succeeded.; } +as_fn_ret_success || { exitcode=1; echo as_fn_ret_success failed.; } +as_fn_ret_failure && { exitcode=1; echo as_fn_ret_failure succeeded.; } +if ( set x; as_fn_ret_success y && test x = \"\$1\" ); then : + +else + exitcode=1; echo positional parameters were not saved. +fi +test x\$exitcode = x0 || exit 1 +test -x / || exit 1" + as_suggested=" as_lineno_1=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_1a=\$LINENO + as_lineno_2=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_2a=\$LINENO + eval 'test \"x\$as_lineno_1'\$as_run'\" != \"x\$as_lineno_2'\$as_run'\" && + test \"x\`expr \$as_lineno_1'\$as_run' + 1\`\" = \"x\$as_lineno_2'\$as_run'\"' || exit 1 + + test -n \"\${ZSH_VERSION+set}\${BASH_VERSION+set}\" || ( + ECHO='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' + ECHO=\$ECHO\$ECHO\$ECHO\$ECHO\$ECHO + ECHO=\$ECHO\$ECHO\$ECHO\$ECHO\$ECHO\$ECHO + PATH=/empty FPATH=/empty; export PATH FPATH + test \"X\`printf %s \$ECHO\`\" = \"X\$ECHO\" \\ + || test \"X\`print -r -- \$ECHO\`\" = \"X\$ECHO\" ) || exit 1 +test \$(( 1 + 1 )) = 2 || exit 1" + if (eval "$as_required") 2>/dev/null; then : + as_have_required=yes +else + as_have_required=no +fi + if test x$as_have_required = xyes && (eval "$as_suggested") 2>/dev/null; then : + +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +as_found=false +for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + as_found=: + case $as_dir in #( + /*) + for as_base in sh bash ksh sh5; do + # Try only shells that exist, to save several forks. + as_shell=$as_dir/$as_base + if { test -f "$as_shell" || test -f "$as_shell.exe"; } && + { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$as_shell"; } 2>/dev/null; then : + CONFIG_SHELL=$as_shell as_have_required=yes + if { $as_echo "$as_bourne_compatible""$as_suggested" | as_run=a "$as_shell"; } 2>/dev/null; then : + break 2 +fi +fi + done;; + esac + as_found=false +done +$as_found || { if { test -f "$SHELL" || test -f "$SHELL.exe"; } && + { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$SHELL"; } 2>/dev/null; then : + CONFIG_SHELL=$SHELL as_have_required=yes +fi; } +IFS=$as_save_IFS + + + if test "x$CONFIG_SHELL" != x; then : + export CONFIG_SHELL + # We cannot yet assume a decent shell, so we have to provide a +# neutralization value for shells without unset; and this also +# works around shells that cannot unset nonexistent variables. +# Preserve -v and -x to the replacement shell. +BASH_ENV=/dev/null +ENV=/dev/null +(unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV +case $- in # (((( + *v*x* | *x*v* ) as_opts=-vx ;; + *v* ) as_opts=-v ;; + *x* ) as_opts=-x ;; + * ) as_opts= ;; +esac +exec $CONFIG_SHELL $as_opts "$as_myself" ${1+"$@"} +# Admittedly, this is quite paranoid, since all the known shells bail +# out after a failed `exec'. +$as_echo "$0: could not re-execute with $CONFIG_SHELL" >&2 +exit 255 +fi + + if test x$as_have_required = xno; then : + $as_echo "$0: This script requires a shell more modern than all" + $as_echo "$0: the shells that I found on your system." + if test x${ZSH_VERSION+set} = xset ; then + $as_echo "$0: In particular, zsh $ZSH_VERSION has bugs and should" + $as_echo "$0: be upgraded to zsh 4.3.4 or later." + else + $as_echo "$0: Please tell bug-autoconf@gnu.org and +$0: https://github.com/wolfssl/wolfssl/issues about your +$0: system, including any error possibly output before this +$0: message. Then install a modern shell, or manually run +$0: the script under such a shell if you do have one." + fi + exit 1 +fi +fi +fi +SHELL=${CONFIG_SHELL-/bin/sh} +export SHELL +# Unset more variables known to interfere with behavior of common tools. +CLICOLOR_FORCE= GREP_OPTIONS= +unset CLICOLOR_FORCE GREP_OPTIONS + +## --------------------- ## +## M4sh Shell Functions. ## +## --------------------- ## +# as_fn_unset VAR +# --------------- +# Portably unset VAR. +as_fn_unset () +{ + { eval $1=; unset $1;} +} +as_unset=as_fn_unset + +# as_fn_set_status STATUS +# ----------------------- +# Set $? to STATUS, without forking. +as_fn_set_status () +{ + return $1 +} # as_fn_set_status + +# as_fn_exit STATUS +# ----------------- +# Exit the shell with STATUS, even in a "trap 0" or "set -e" context. +as_fn_exit () +{ + set +e + as_fn_set_status $1 + exit $1 +} # as_fn_exit + +# as_fn_mkdir_p +# ------------- +# Create "$as_dir" as a directory, including parents if necessary. +as_fn_mkdir_p () +{ + + case $as_dir in #( + -*) as_dir=./$as_dir;; + esac + test -d "$as_dir" || eval $as_mkdir_p || { + as_dirs= + while :; do + case $as_dir in #( + *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( + *) as_qdir=$as_dir;; + esac + as_dirs="'$as_qdir' $as_dirs" + as_dir=`$as_dirname -- "$as_dir" || +$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$as_dir" : 'X\(//\)[^/]' \| \ + X"$as_dir" : 'X\(//\)$' \| \ + X"$as_dir" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X"$as_dir" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + test -d "$as_dir" && break + done + test -z "$as_dirs" || eval "mkdir $as_dirs" + } || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir" + + +} # as_fn_mkdir_p + +# as_fn_executable_p FILE +# ----------------------- +# Test if FILE is an executable regular file. +as_fn_executable_p () +{ + test -f "$1" && test -x "$1" +} # as_fn_executable_p +# as_fn_append VAR VALUE +# ---------------------- +# Append the text in VALUE to the end of the definition contained in VAR. Take +# advantage of any shell optimizations that allow amortized linear growth over +# repeated appends, instead of the typical quadratic growth present in naive +# implementations. +if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : + eval 'as_fn_append () + { + eval $1+=\$2 + }' +else + as_fn_append () + { + eval $1=\$$1\$2 + } +fi # as_fn_append + +# as_fn_arith ARG... +# ------------------ +# Perform arithmetic evaluation on the ARGs, and store the result in the +# global $as_val. Take advantage of shells that can avoid forks. The arguments +# must be portable across $(()) and expr. +if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : + eval 'as_fn_arith () + { + as_val=$(( $* )) + }' +else + as_fn_arith () + { + as_val=`expr "$@" || test $? -eq 1` + } +fi # as_fn_arith + + +# as_fn_error STATUS ERROR [LINENO LOG_FD] +# ---------------------------------------- +# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are +# provided, also output the error to LOG_FD, referencing LINENO. Then exit the +# script with STATUS, using 1 if that was 0. +as_fn_error () +{ + as_status=$1; test $as_status -eq 0 && as_status=1 + if test "$4"; then + as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4 + fi + $as_echo "$as_me: error: $2" >&2 + as_fn_exit $as_status +} # as_fn_error + +if expr a : '\(a\)' >/dev/null 2>&1 && + test "X`expr 00001 : '.*\(...\)'`" = X001; then + as_expr=expr +else + as_expr=false +fi + +if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then + as_basename=basename +else + as_basename=false +fi + +if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then + as_dirname=dirname +else + as_dirname=false +fi + +as_me=`$as_basename -- "$0" || +$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \ + X"$0" : 'X\(//\)$' \| \ + X"$0" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X/"$0" | + sed '/^.*\/\([^/][^/]*\)\/*$/{ + s//\1/ + q + } + /^X\/\(\/\/\)$/{ + s//\1/ + q + } + /^X\/\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + +# Avoid depending upon Character Ranges. +as_cr_letters='abcdefghijklmnopqrstuvwxyz' +as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ' +as_cr_Letters=$as_cr_letters$as_cr_LETTERS +as_cr_digits='0123456789' +as_cr_alnum=$as_cr_Letters$as_cr_digits + + + as_lineno_1=$LINENO as_lineno_1a=$LINENO + as_lineno_2=$LINENO as_lineno_2a=$LINENO + eval 'test "x$as_lineno_1'$as_run'" != "x$as_lineno_2'$as_run'" && + test "x`expr $as_lineno_1'$as_run' + 1`" = "x$as_lineno_2'$as_run'"' || { + # Blame Lee E. McMahon (1931-1989) for sed's syntax. :-) + sed -n ' + p + /[$]LINENO/= + ' <$as_myself | + sed ' + s/[$]LINENO.*/&-/ + t lineno + b + :lineno + N + :loop + s/[$]LINENO\([^'$as_cr_alnum'_].*\n\)\(.*\)/\2\1\2/ + t loop + s/-\n.*// + ' >$as_me.lineno && + chmod +x "$as_me.lineno" || + { $as_echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2; as_fn_exit 1; } + + # If we had to re-execute with $CONFIG_SHELL, we're ensured to have + # already done that, so ensure we don't try to do so again and fall + # in an infinite loop. This has already happened in practice. + _as_can_reexec=no; export _as_can_reexec + # Don't try to exec as it changes $[0], causing all sort of problems + # (the dirname of $[0] is not the place where we might find the + # original and so on. Autoconf is especially sensitive to this). + . "./$as_me.lineno" + # Exit status is that of the last command. + exit +} + +ECHO_C= ECHO_N= ECHO_T= +case `echo -n x` in #((((( +-n*) + case `echo 'xy\c'` in + *c*) ECHO_T=' ';; # ECHO_T is single tab character. + xy) ECHO_C='\c';; + *) echo `echo ksh88 bug on AIX 6.1` > /dev/null + ECHO_T=' ';; + esac;; +*) + ECHO_N='-n';; +esac + +rm -f conf$$ conf$$.exe conf$$.file +if test -d conf$$.dir; then + rm -f conf$$.dir/conf$$.file +else + rm -f conf$$.dir + mkdir conf$$.dir 2>/dev/null +fi +if (echo >conf$$.file) 2>/dev/null; then + if ln -s conf$$.file conf$$ 2>/dev/null; then + as_ln_s='ln -s' + # ... but there are two gotchas: + # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail. + # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable. + # In both cases, we have to default to `cp -pR'. + ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe || + as_ln_s='cp -pR' + elif ln conf$$.file conf$$ 2>/dev/null; then + as_ln_s=ln + else + as_ln_s='cp -pR' + fi +else + as_ln_s='cp -pR' +fi +rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file +rmdir conf$$.dir 2>/dev/null + +if mkdir -p . 2>/dev/null; then + as_mkdir_p='mkdir -p "$as_dir"' +else + test -d ./-p && rmdir ./-p + as_mkdir_p=false +fi + +as_test_x='test -x' +as_executable_p=as_fn_executable_p + +# Sed expression to map a string onto a valid CPP name. +as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" + +# Sed expression to map a string onto a valid variable name. +as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" + +SHELL=${CONFIG_SHELL-/bin/sh} + + +test -n "$DJDIR" || exec 7<&0 &1 + +# Name of the host. +# hostname on some systems (SVR3.2, old GNU/Linux) returns a bogus exit status, +# so uname gets run too. +ac_hostname=`(hostname || uname -n) 2>/dev/null | sed 1q` + +# +# Initializations. +# +ac_default_prefix=/usr/local +ac_clean_files= +ac_config_libobj_dir=. +LIBOBJS= +cross_compiling=no +subdirs= +MFLAGS= +MAKEFLAGS= + +# Identity of this package. +PACKAGE_NAME='wolfssl' +PACKAGE_TARNAME='wolfssl' +PACKAGE_VERSION='3.6.0' +PACKAGE_STRING='wolfssl 3.6.0' +PACKAGE_BUGREPORT='https://github.com/wolfssl/wolfssl/issues' +PACKAGE_URL='http://www.wolfssl.com' + +# Factoring default headers for most tests. +ac_includes_default="\ +#include +#ifdef HAVE_SYS_TYPES_H +# include +#endif +#ifdef HAVE_SYS_STAT_H +# include +#endif +#ifdef STDC_HEADERS +# include +# include +#else +# ifdef HAVE_STDLIB_H +# include +# endif +#endif +#ifdef HAVE_STRING_H +# if !defined STDC_HEADERS && defined HAVE_MEMORY_H +# include +# endif +# include +#endif +#ifdef HAVE_STRINGS_H +# include +#endif +#ifdef HAVE_INTTYPES_H +# include +#endif +#ifdef HAVE_STDINT_H +# include +#endif +#ifdef HAVE_UNISTD_H +# include +#endif" + +ac_subst_vars='am__EXEEXT_FALSE +am__EXEEXT_TRUE +LTLIBOBJS +LIBOBJS +INC_AMINCLUDE +AMINCLUDE +GENERIC_CONFIG +AM_LDFLAGS +AM_CFLAGS +AM_CPPFLAGS +HEX_VERSION +IS_VCS_CHECKOUT_FALSE +IS_VCS_CHECKOUT_TRUE +BUILD_MCAPI_FALSE +BUILD_MCAPI_TRUE +BUILD_LIBZ_FALSE +BUILD_LIBZ_TRUE +BUILD_EXAMPLES_FALSE +BUILD_EXAMPLES_TRUE +BUILD_SLOWMATH_FALSE +BUILD_SLOWMATH_TRUE +BUILD_FASTMATH_FALSE +BUILD_FASTMATH_TRUE +BUILD_PWDBASED_FALSE +BUILD_PWDBASED_TRUE +USE_VALGRIND_FALSE +USE_VALGRIND_TRUE +HAVE_VALGRIND +BUILD_PKCS7_FALSE +BUILD_PKCS7_TRUE +BUILD_NTRU_FALSE +BUILD_NTRU_TRUE +BUILD_CRL_MONITOR_FALSE +BUILD_CRL_MONITOR_TRUE +BUILD_CRL_FALSE +BUILD_CRL_TRUE +HAVE_OPENSSL_CMD +BUILD_OCSP_FALSE +BUILD_OCSP_TRUE +BUILD_INLINE_FALSE +BUILD_INLINE_TRUE +BUILD_CHACHA_FALSE +BUILD_CHACHA_TRUE +BUILD_POLY1305_FALSE +BUILD_POLY1305_TRUE +BUILD_FIPS_FALSE +BUILD_FIPS_TRUE +BUILD_RABBIT_FALSE +BUILD_RABBIT_TRUE +BUILD_HC128_FALSE +BUILD_HC128_TRUE +BUILD_MD4_FALSE +BUILD_MD4_TRUE +BUILD_SHA_FALSE +BUILD_SHA_TRUE +BUILD_MD5_FALSE +BUILD_MD5_TRUE +BUILD_RC4_FALSE +BUILD_RC4_TRUE +BUILD_DES3_FALSE +BUILD_DES3_TRUE +BUILD_CODING_FALSE +BUILD_CODING_TRUE +BUILD_AES_FALSE +BUILD_AES_TRUE +BUILD_ASN_FALSE +BUILD_ASN_TRUE +BUILD_DH_FALSE +BUILD_DH_TRUE +BUILD_RSA_FALSE +BUILD_RSA_TRUE +BUILD_MEMORY_FALSE +BUILD_MEMORY_TRUE +BUILD_GEMATH_FALSE +BUILD_GEMATH_TRUE +BUILD_FEMATH_FALSE +BUILD_FEMATH_TRUE +BUILD_CURVED25519_SMALL_FALSE +BUILD_CURVED25519_SMALL_TRUE +BUILD_ED25519_FALSE +BUILD_ED25519_TRUE +BUILD_CURVE25519_FALSE +BUILD_CURVE25519_TRUE +BUILD_ECC_FALSE +BUILD_ECC_TRUE +BUILD_DSA_FALSE +BUILD_DSA_TRUE +BUILD_SHA512_FALSE +BUILD_SHA512_TRUE +BUILD_BLAKE2_FALSE +BUILD_BLAKE2_TRUE +BUILD_RIPEMD_FALSE +BUILD_RIPEMD_TRUE +BUILD_MD2_FALSE +BUILD_MD2_TRUE +BUILD_CAMELLIA_FALSE +BUILD_CAMELLIA_TRUE +BUILD_AESNI_FALSE +BUILD_AESNI_TRUE +BUILD_AESCCM_FALSE +BUILD_AESCCM_TRUE +BUILD_AESGCM_FALSE +BUILD_AESGCM_TRUE +BUILD_SNIFFTEST_FALSE +BUILD_SNIFFTEST_TRUE +BUILD_SNIFFER_FALSE +BUILD_SNIFFER_TRUE +BUILD_LEANPSK_FALSE +BUILD_LEANPSK_TRUE +BUILD_IPV6_FALSE +BUILD_IPV6_TRUE +PTHREAD_CFLAGS +PTHREAD_LIBS +PTHREAD_CC +ax_pthread_config +DEBUG_FALSE +DEBUG_TRUE +MCHECK +LIBM +am__fastdepCCAS_FALSE +am__fastdepCCAS_TRUE +CCASDEPMODE +CCASFLAGS +CCAS +HAVE_VISIBILITY +CFLAG_VISIBILITY +CXXCPP +am__fastdepCXX_FALSE +am__fastdepCXX_TRUE +CXXDEPMODE +ac_ct_CXX +CXXFLAGS +CXX +CPP +OTOOL64 +OTOOL +LIPO +NMEDIT +DSYMUTIL +MANIFEST_TOOL +RANLIB +ac_ct_AR +AR +DLLTOOL +OBJDUMP +LN_S +NM +ac_ct_DUMPBIN +DUMPBIN +LD +FGREP +EGREP +GREP +SED +am__fastdepCC_FALSE +am__fastdepCC_TRUE +CCDEPMODE +am__nodep +AMDEPBACKSLASH +AMDEP_FALSE +AMDEP_TRUE +am__quote +am__include +DEPDIR +OBJEXT +EXEEXT +ac_ct_CC +CPPFLAGS +LDFLAGS +CFLAGS +CC +LIBTOOL +WOLFSSL_LIBRARY_VERSION +AM_BACKSLASH +AM_DEFAULT_VERBOSITY +AM_DEFAULT_V +AM_V +am__untar +am__tar +AMTAR +am__leading_dot +SET_MAKE +AWK +mkdir_p +MKDIR_P +INSTALL_STRIP_PROGRAM +STRIP +install_sh +MAKEINFO +AUTOHEADER +AUTOMAKE +AUTOCONF +ACLOCAL +VERSION +PACKAGE +CYGPATH_W +am__isrc +INSTALL_DATA +INSTALL_SCRIPT +INSTALL_PROGRAM +host_os +host_vendor +host_cpu +host +build_os +build_vendor +build_cpu +build +target_alias +host_alias +build_alias +LIBS +ECHO_T +ECHO_N +ECHO_C +DEFS +mandir +localedir +libdir +psdir +pdfdir +dvidir +htmldir +infodir +docdir +oldincludedir +includedir +localstatedir +sharedstatedir +sysconfdir +datadir +datarootdir +libexecdir +sbindir +bindir +program_transform_name +prefix +exec_prefix +PACKAGE_URL +PACKAGE_BUGREPORT +PACKAGE_STRING +PACKAGE_VERSION +PACKAGE_TARNAME +PACKAGE_NAME +PATH_SEPARATOR +SHELL' +ac_subst_files='' +ac_user_opts=' +enable_option_checking +enable_silent_rules +enable_static +enable_shared +with_pic +enable_fast_install +enable_dependency_tracking +with_gnu_ld +with_sysroot +enable_libtool_lock +enable_debug +enable_singlethreaded +enable_dtls +enable_opensslextra +enable_maxstrength +enable_ipv6 +enable_fortress +enable_bump +enable_leanpsk +enable_bigcache +enable_hugecache +enable_smallcache +enable_savesession +enable_savecert +enable_atomicuser +enable_pkcallbacks +enable_sniffer +enable_aesgcm +enable_aesccm +enable_aesni +enable_intelasm +enable_camellia +enable_md2 +enable_nullcipher +enable_ripemd +enable_blake2 +enable_sha512 +enable_sessioncerts +enable_keygen +enable_certgen +enable_certreq +enable_sep +enable_hkdf +enable_dsa +enable_ecc +enable_curve25519 +enable_ed25519 +enable_fpecc +enable_eccencrypt +enable_psk +enable_errorstrings +enable_oldtls +enable_stacksize +enable_memory +enable_rsa +enable_dh +enable_anon +enable_asn +enable_aes +enable_coding +enable_des3 +enable_arc4 +enable_md5 +enable_sha +enable_md4 +enable_webserver +enable_hc128 +enable_rabbit +enable_fips +enable_poly1305 +enable_chacha +enable_hashdrbg +enable_filesystem +enable_inline +enable_ocsp +enable_crl +enable_crl_monitor +with_ntru +enable_sni +enable_maxfragment +enable_truncatedhmac +enable_renegotiation_indication +enable_secure_renegotiation +enable_supportedcurves +enable_session_ticket +enable_tlsx +enable_pkcs7 +enable_scep +enable_smallstack +enable_valgrind +enable_testcert +enable_iopool +enable_certservice +enable_pwdbased +enable_fastmath +enable_fasthugemath +enable_examples +with_libz +with_cavium +enable_mcapi +enable_jni +enable_jobserver +' + ac_precious_vars='build_alias +host_alias +target_alias +CC +CFLAGS +LDFLAGS +LIBS +CPPFLAGS +CPP +CXX +CXXFLAGS +CCC +CXXCPP +CCAS +CCASFLAGS' + + +# Initialize some variables set by options. +ac_init_help= +ac_init_version=false +ac_unrecognized_opts= +ac_unrecognized_sep= +# The variables have the same names as the options, with +# dashes changed to underlines. +cache_file=/dev/null +exec_prefix=NONE +no_create= +no_recursion= +prefix=NONE +program_prefix=NONE +program_suffix=NONE +program_transform_name=s,x,x, +silent= +site= +srcdir= +verbose= +x_includes=NONE +x_libraries=NONE + +# Installation directory options. +# These are left unexpanded so users can "make install exec_prefix=/foo" +# and all the variables that are supposed to be based on exec_prefix +# by default will actually change. +# Use braces instead of parens because sh, perl, etc. also accept them. +# (The list follows the same order as the GNU Coding Standards.) +bindir='${exec_prefix}/bin' +sbindir='${exec_prefix}/sbin' +libexecdir='${exec_prefix}/libexec' +datarootdir='${prefix}/share' +datadir='${datarootdir}' +sysconfdir='${prefix}/etc' +sharedstatedir='${prefix}/com' +localstatedir='${prefix}/var' +includedir='${prefix}/include' +oldincludedir='/usr/include' +docdir='${datarootdir}/doc/${PACKAGE_TARNAME}' +infodir='${datarootdir}/info' +htmldir='${docdir}' +dvidir='${docdir}' +pdfdir='${docdir}' +psdir='${docdir}' +libdir='${exec_prefix}/lib' +localedir='${datarootdir}/locale' +mandir='${datarootdir}/man' + +ac_prev= +ac_dashdash= +for ac_option +do + # If the previous option needs an argument, assign it. + if test -n "$ac_prev"; then + eval $ac_prev=\$ac_option + ac_prev= + continue + fi + + case $ac_option in + *=?*) ac_optarg=`expr "X$ac_option" : '[^=]*=\(.*\)'` ;; + *=) ac_optarg= ;; + *) ac_optarg=yes ;; + esac + + # Accept the important Cygnus configure options, so we can diagnose typos. + + case $ac_dashdash$ac_option in + --) + ac_dashdash=yes ;; + + -bindir | --bindir | --bindi | --bind | --bin | --bi) + ac_prev=bindir ;; + -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*) + bindir=$ac_optarg ;; + + -build | --build | --buil | --bui | --bu) + ac_prev=build_alias ;; + -build=* | --build=* | --buil=* | --bui=* | --bu=*) + build_alias=$ac_optarg ;; + + -cache-file | --cache-file | --cache-fil | --cache-fi \ + | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c) + ac_prev=cache_file ;; + -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \ + | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*) + cache_file=$ac_optarg ;; + + --config-cache | -C) + cache_file=config.cache ;; + + -datadir | --datadir | --datadi | --datad) + ac_prev=datadir ;; + -datadir=* | --datadir=* | --datadi=* | --datad=*) + datadir=$ac_optarg ;; + + -datarootdir | --datarootdir | --datarootdi | --datarootd | --dataroot \ + | --dataroo | --dataro | --datar) + ac_prev=datarootdir ;; + -datarootdir=* | --datarootdir=* | --datarootdi=* | --datarootd=* \ + | --dataroot=* | --dataroo=* | --dataro=* | --datar=*) + datarootdir=$ac_optarg ;; + + -disable-* | --disable-*) + ac_useropt=`expr "x$ac_option" : 'x-*disable-\(.*\)'` + # Reject names that are not valid shell variable names. + expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && + as_fn_error $? "invalid feature name: $ac_useropt" + ac_useropt_orig=$ac_useropt + ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` + case $ac_user_opts in + *" +"enable_$ac_useropt" +"*) ;; + *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--disable-$ac_useropt_orig" + ac_unrecognized_sep=', ';; + esac + eval enable_$ac_useropt=no ;; + + -docdir | --docdir | --docdi | --doc | --do) + ac_prev=docdir ;; + -docdir=* | --docdir=* | --docdi=* | --doc=* | --do=*) + docdir=$ac_optarg ;; + + -dvidir | --dvidir | --dvidi | --dvid | --dvi | --dv) + ac_prev=dvidir ;; + -dvidir=* | --dvidir=* | --dvidi=* | --dvid=* | --dvi=* | --dv=*) + dvidir=$ac_optarg ;; + + -enable-* | --enable-*) + ac_useropt=`expr "x$ac_option" : 'x-*enable-\([^=]*\)'` + # Reject names that are not valid shell variable names. + expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && + as_fn_error $? "invalid feature name: $ac_useropt" + ac_useropt_orig=$ac_useropt + ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` + case $ac_user_opts in + *" +"enable_$ac_useropt" +"*) ;; + *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--enable-$ac_useropt_orig" + ac_unrecognized_sep=', ';; + esac + eval enable_$ac_useropt=\$ac_optarg ;; + + -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \ + | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \ + | --exec | --exe | --ex) + ac_prev=exec_prefix ;; + -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \ + | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \ + | --exec=* | --exe=* | --ex=*) + exec_prefix=$ac_optarg ;; + + -gas | --gas | --ga | --g) + # Obsolete; use --with-gas. + with_gas=yes ;; + + -help | --help | --hel | --he | -h) + ac_init_help=long ;; + -help=r* | --help=r* | --hel=r* | --he=r* | -hr*) + ac_init_help=recursive ;; + -help=s* | --help=s* | --hel=s* | --he=s* | -hs*) + ac_init_help=short ;; + + -host | --host | --hos | --ho) + ac_prev=host_alias ;; + -host=* | --host=* | --hos=* | --ho=*) + host_alias=$ac_optarg ;; + + -htmldir | --htmldir | --htmldi | --htmld | --html | --htm | --ht) + ac_prev=htmldir ;; + -htmldir=* | --htmldir=* | --htmldi=* | --htmld=* | --html=* | --htm=* \ + | --ht=*) + htmldir=$ac_optarg ;; + + -includedir | --includedir | --includedi | --included | --include \ + | --includ | --inclu | --incl | --inc) + ac_prev=includedir ;; + -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \ + | --includ=* | --inclu=* | --incl=* | --inc=*) + includedir=$ac_optarg ;; + + -infodir | --infodir | --infodi | --infod | --info | --inf) + ac_prev=infodir ;; + -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*) + infodir=$ac_optarg ;; + + -libdir | --libdir | --libdi | --libd) + ac_prev=libdir ;; + -libdir=* | --libdir=* | --libdi=* | --libd=*) + libdir=$ac_optarg ;; + + -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \ + | --libexe | --libex | --libe) + ac_prev=libexecdir ;; + -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \ + | --libexe=* | --libex=* | --libe=*) + libexecdir=$ac_optarg ;; + + -localedir | --localedir | --localedi | --localed | --locale) + ac_prev=localedir ;; + -localedir=* | --localedir=* | --localedi=* | --localed=* | --locale=*) + localedir=$ac_optarg ;; + + -localstatedir | --localstatedir | --localstatedi | --localstated \ + | --localstate | --localstat | --localsta | --localst | --locals) + ac_prev=localstatedir ;; + -localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \ + | --localstate=* | --localstat=* | --localsta=* | --localst=* | --locals=*) + localstatedir=$ac_optarg ;; + + -mandir | --mandir | --mandi | --mand | --man | --ma | --m) + ac_prev=mandir ;; + -mandir=* | --mandir=* | --mandi=* | --mand=* | --man=* | --ma=* | --m=*) + mandir=$ac_optarg ;; + + -nfp | --nfp | --nf) + # Obsolete; use --without-fp. + with_fp=no ;; + + -no-create | --no-create | --no-creat | --no-crea | --no-cre \ + | --no-cr | --no-c | -n) + no_create=yes ;; + + -no-recursion | --no-recursion | --no-recursio | --no-recursi \ + | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r) + no_recursion=yes ;; + + -oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \ + | --oldinclude | --oldinclud | --oldinclu | --oldincl | --oldinc \ + | --oldin | --oldi | --old | --ol | --o) + ac_prev=oldincludedir ;; + -oldincludedir=* | --oldincludedir=* | --oldincludedi=* | --oldincluded=* \ + | --oldinclude=* | --oldinclud=* | --oldinclu=* | --oldincl=* | --oldinc=* \ + | --oldin=* | --oldi=* | --old=* | --ol=* | --o=*) + oldincludedir=$ac_optarg ;; + + -prefix | --prefix | --prefi | --pref | --pre | --pr | --p) + ac_prev=prefix ;; + -prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*) + prefix=$ac_optarg ;; + + -program-prefix | --program-prefix | --program-prefi | --program-pref \ + | --program-pre | --program-pr | --program-p) + ac_prev=program_prefix ;; + -program-prefix=* | --program-prefix=* | --program-prefi=* \ + | --program-pref=* | --program-pre=* | --program-pr=* | --program-p=*) + program_prefix=$ac_optarg ;; + + -program-suffix | --program-suffix | --program-suffi | --program-suff \ + | --program-suf | --program-su | --program-s) + ac_prev=program_suffix ;; + -program-suffix=* | --program-suffix=* | --program-suffi=* \ + | --program-suff=* | --program-suf=* | --program-su=* | --program-s=*) + program_suffix=$ac_optarg ;; + + -program-transform-name | --program-transform-name \ + | --program-transform-nam | --program-transform-na \ + | --program-transform-n | --program-transform- \ + | --program-transform | --program-transfor \ + | --program-transfo | --program-transf \ + | --program-trans | --program-tran \ + | --progr-tra | --program-tr | --program-t) + ac_prev=program_transform_name ;; + -program-transform-name=* | --program-transform-name=* \ + | --program-transform-nam=* | --program-transform-na=* \ + | --program-transform-n=* | --program-transform-=* \ + | --program-transform=* | --program-transfor=* \ + | --program-transfo=* | --program-transf=* \ + | --program-trans=* | --program-tran=* \ + | --progr-tra=* | --program-tr=* | --program-t=*) + program_transform_name=$ac_optarg ;; + + -pdfdir | --pdfdir | --pdfdi | --pdfd | --pdf | --pd) + ac_prev=pdfdir ;; + -pdfdir=* | --pdfdir=* | --pdfdi=* | --pdfd=* | --pdf=* | --pd=*) + pdfdir=$ac_optarg ;; + + -psdir | --psdir | --psdi | --psd | --ps) + ac_prev=psdir ;; + -psdir=* | --psdir=* | --psdi=* | --psd=* | --ps=*) + psdir=$ac_optarg ;; + + -q | -quiet | --quiet | --quie | --qui | --qu | --q \ + | -silent | --silent | --silen | --sile | --sil) + silent=yes ;; + + -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb) + ac_prev=sbindir ;; + -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \ + | --sbi=* | --sb=*) + sbindir=$ac_optarg ;; + + -sharedstatedir | --sharedstatedir | --sharedstatedi \ + | --sharedstated | --sharedstate | --sharedstat | --sharedsta \ + | --sharedst | --shareds | --shared | --share | --shar \ + | --sha | --sh) + ac_prev=sharedstatedir ;; + -sharedstatedir=* | --sharedstatedir=* | --sharedstatedi=* \ + | --sharedstated=* | --sharedstate=* | --sharedstat=* | --sharedsta=* \ + | --sharedst=* | --shareds=* | --shared=* | --share=* | --shar=* \ + | --sha=* | --sh=*) + sharedstatedir=$ac_optarg ;; + + -site | --site | --sit) + ac_prev=site ;; + -site=* | --site=* | --sit=*) + site=$ac_optarg ;; + + -srcdir | --srcdir | --srcdi | --srcd | --src | --sr) + ac_prev=srcdir ;; + -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*) + srcdir=$ac_optarg ;; + + -sysconfdir | --sysconfdir | --sysconfdi | --sysconfd | --sysconf \ + | --syscon | --sysco | --sysc | --sys | --sy) + ac_prev=sysconfdir ;; + -sysconfdir=* | --sysconfdir=* | --sysconfdi=* | --sysconfd=* | --sysconf=* \ + | --syscon=* | --sysco=* | --sysc=* | --sys=* | --sy=*) + sysconfdir=$ac_optarg ;; + + -target | --target | --targe | --targ | --tar | --ta | --t) + ac_prev=target_alias ;; + -target=* | --target=* | --targe=* | --targ=* | --tar=* | --ta=* | --t=*) + target_alias=$ac_optarg ;; + + -v | -verbose | --verbose | --verbos | --verbo | --verb) + verbose=yes ;; + + -version | --version | --versio | --versi | --vers | -V) + ac_init_version=: ;; + + -with-* | --with-*) + ac_useropt=`expr "x$ac_option" : 'x-*with-\([^=]*\)'` + # Reject names that are not valid shell variable names. + expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && + as_fn_error $? "invalid package name: $ac_useropt" + ac_useropt_orig=$ac_useropt + ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` + case $ac_user_opts in + *" +"with_$ac_useropt" +"*) ;; + *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--with-$ac_useropt_orig" + ac_unrecognized_sep=', ';; + esac + eval with_$ac_useropt=\$ac_optarg ;; + + -without-* | --without-*) + ac_useropt=`expr "x$ac_option" : 'x-*without-\(.*\)'` + # Reject names that are not valid shell variable names. + expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && + as_fn_error $? "invalid package name: $ac_useropt" + ac_useropt_orig=$ac_useropt + ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` + case $ac_user_opts in + *" +"with_$ac_useropt" +"*) ;; + *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--without-$ac_useropt_orig" + ac_unrecognized_sep=', ';; + esac + eval with_$ac_useropt=no ;; + + --x) + # Obsolete; use --with-x. + with_x=yes ;; + + -x-includes | --x-includes | --x-include | --x-includ | --x-inclu \ + | --x-incl | --x-inc | --x-in | --x-i) + ac_prev=x_includes ;; + -x-includes=* | --x-includes=* | --x-include=* | --x-includ=* | --x-inclu=* \ + | --x-incl=* | --x-inc=* | --x-in=* | --x-i=*) + x_includes=$ac_optarg ;; + + -x-libraries | --x-libraries | --x-librarie | --x-librari \ + | --x-librar | --x-libra | --x-libr | --x-lib | --x-li | --x-l) + ac_prev=x_libraries ;; + -x-libraries=* | --x-libraries=* | --x-librarie=* | --x-librari=* \ + | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*) + x_libraries=$ac_optarg ;; + + -*) as_fn_error $? "unrecognized option: \`$ac_option' +Try \`$0 --help' for more information" + ;; + + *=*) + ac_envvar=`expr "x$ac_option" : 'x\([^=]*\)='` + # Reject names that are not valid shell variable names. + case $ac_envvar in #( + '' | [0-9]* | *[!_$as_cr_alnum]* ) + as_fn_error $? "invalid variable name: \`$ac_envvar'" ;; + esac + eval $ac_envvar=\$ac_optarg + export $ac_envvar ;; + + *) + # FIXME: should be removed in autoconf 3.0. + $as_echo "$as_me: WARNING: you should use --build, --host, --target" >&2 + expr "x$ac_option" : ".*[^-._$as_cr_alnum]" >/dev/null && + $as_echo "$as_me: WARNING: invalid host type: $ac_option" >&2 + : "${build_alias=$ac_option} ${host_alias=$ac_option} ${target_alias=$ac_option}" + ;; + + esac +done + +if test -n "$ac_prev"; then + ac_option=--`echo $ac_prev | sed 's/_/-/g'` + as_fn_error $? "missing argument to $ac_option" +fi + +if test -n "$ac_unrecognized_opts"; then + case $enable_option_checking in + no) ;; + fatal) as_fn_error $? "unrecognized options: $ac_unrecognized_opts" ;; + *) $as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2 ;; + esac +fi + +# Check all directory arguments for consistency. +for ac_var in exec_prefix prefix bindir sbindir libexecdir datarootdir \ + datadir sysconfdir sharedstatedir localstatedir includedir \ + oldincludedir docdir infodir htmldir dvidir pdfdir psdir \ + libdir localedir mandir +do + eval ac_val=\$$ac_var + # Remove trailing slashes. + case $ac_val in + */ ) + ac_val=`expr "X$ac_val" : 'X\(.*[^/]\)' \| "X$ac_val" : 'X\(.*\)'` + eval $ac_var=\$ac_val;; + esac + # Be sure to have absolute directory names. + case $ac_val in + [\\/$]* | ?:[\\/]* ) continue;; + NONE | '' ) case $ac_var in *prefix ) continue;; esac;; + esac + as_fn_error $? "expected an absolute directory name for --$ac_var: $ac_val" +done + +# There might be people who depend on the old broken behavior: `$host' +# used to hold the argument of --host etc. +# FIXME: To remove some day. +build=$build_alias +host=$host_alias +target=$target_alias + +# FIXME: To remove some day. +if test "x$host_alias" != x; then + if test "x$build_alias" = x; then + cross_compiling=maybe + elif test "x$build_alias" != "x$host_alias"; then + cross_compiling=yes + fi +fi + +ac_tool_prefix= +test -n "$host_alias" && ac_tool_prefix=$host_alias- + +test "$silent" = yes && exec 6>/dev/null + + +ac_pwd=`pwd` && test -n "$ac_pwd" && +ac_ls_di=`ls -di .` && +ac_pwd_ls_di=`cd "$ac_pwd" && ls -di .` || + as_fn_error $? "working directory cannot be determined" +test "X$ac_ls_di" = "X$ac_pwd_ls_di" || + as_fn_error $? "pwd does not report name of working directory" + + +# Find the source files, if location was not specified. +if test -z "$srcdir"; then + ac_srcdir_defaulted=yes + # Try the directory containing this script, then the parent directory. + ac_confdir=`$as_dirname -- "$as_myself" || +$as_expr X"$as_myself" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$as_myself" : 'X\(//\)[^/]' \| \ + X"$as_myself" : 'X\(//\)$' \| \ + X"$as_myself" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X"$as_myself" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + srcdir=$ac_confdir + if test ! -r "$srcdir/$ac_unique_file"; then + srcdir=.. + fi +else + ac_srcdir_defaulted=no +fi +if test ! -r "$srcdir/$ac_unique_file"; then + test "$ac_srcdir_defaulted" = yes && srcdir="$ac_confdir or .." + as_fn_error $? "cannot find sources ($ac_unique_file) in $srcdir" +fi +ac_msg="sources are in $srcdir, but \`cd $srcdir' does not work" +ac_abs_confdir=`( + cd "$srcdir" && test -r "./$ac_unique_file" || as_fn_error $? "$ac_msg" + pwd)` +# When building in place, set srcdir=. +if test "$ac_abs_confdir" = "$ac_pwd"; then + srcdir=. +fi +# Remove unnecessary trailing slashes from srcdir. +# Double slashes in file names in object file debugging info +# mess up M-x gdb in Emacs. +case $srcdir in +*/) srcdir=`expr "X$srcdir" : 'X\(.*[^/]\)' \| "X$srcdir" : 'X\(.*\)'`;; +esac +for ac_var in $ac_precious_vars; do + eval ac_env_${ac_var}_set=\${${ac_var}+set} + eval ac_env_${ac_var}_value=\$${ac_var} + eval ac_cv_env_${ac_var}_set=\${${ac_var}+set} + eval ac_cv_env_${ac_var}_value=\$${ac_var} +done + +# +# Report the --help message. +# +if test "$ac_init_help" = "long"; then + # Omit some internal or obsolete options to make the list less imposing. + # This message is too long to be a string in the A/UX 3.1 sh. + cat <<_ACEOF +\`configure' configures wolfssl 3.6.0 to adapt to many kinds of systems. + +Usage: $0 [OPTION]... [VAR=VALUE]... + +To assign environment variables (e.g., CC, CFLAGS...), specify them as +VAR=VALUE. See below for descriptions of some of the useful variables. + +Defaults for the options are specified in brackets. + +Configuration: + -h, --help display this help and exit + --help=short display options specific to this package + --help=recursive display the short help of all the included packages + -V, --version display version information and exit + -q, --quiet, --silent do not print \`checking ...' messages + --cache-file=FILE cache test results in FILE [disabled] + -C, --config-cache alias for \`--cache-file=config.cache' + -n, --no-create do not create output files + --srcdir=DIR find the sources in DIR [configure dir or \`..'] + +Installation directories: + --prefix=PREFIX install architecture-independent files in PREFIX + [$ac_default_prefix] + --exec-prefix=EPREFIX install architecture-dependent files in EPREFIX + [PREFIX] + +By default, \`make install' will install all the files in +\`$ac_default_prefix/bin', \`$ac_default_prefix/lib' etc. You can specify +an installation prefix other than \`$ac_default_prefix' using \`--prefix', +for instance \`--prefix=\$HOME'. + +For better control, use the options below. + +Fine tuning of the installation directories: + --bindir=DIR user executables [EPREFIX/bin] + --sbindir=DIR system admin executables [EPREFIX/sbin] + --libexecdir=DIR program executables [EPREFIX/libexec] + --sysconfdir=DIR read-only single-machine data [PREFIX/etc] + --sharedstatedir=DIR modifiable architecture-independent data [PREFIX/com] + --localstatedir=DIR modifiable single-machine data [PREFIX/var] + --libdir=DIR object code libraries [EPREFIX/lib] + --includedir=DIR C header files [PREFIX/include] + --oldincludedir=DIR C header files for non-gcc [/usr/include] + --datarootdir=DIR read-only arch.-independent data root [PREFIX/share] + --datadir=DIR read-only architecture-independent data [DATAROOTDIR] + --infodir=DIR info documentation [DATAROOTDIR/info] + --localedir=DIR locale-dependent data [DATAROOTDIR/locale] + --mandir=DIR man documentation [DATAROOTDIR/man] + --docdir=DIR documentation root [DATAROOTDIR/doc/wolfssl] + --htmldir=DIR html documentation [DOCDIR] + --dvidir=DIR dvi documentation [DOCDIR] + --pdfdir=DIR pdf documentation [DOCDIR] + --psdir=DIR ps documentation [DOCDIR] +_ACEOF + + cat <<\_ACEOF + +Program names: + --program-prefix=PREFIX prepend PREFIX to installed program names + --program-suffix=SUFFIX append SUFFIX to installed program names + --program-transform-name=PROGRAM run sed PROGRAM on installed program names + +System types: + --build=BUILD configure for building on BUILD [guessed] + --host=HOST cross-compile to build programs to run on HOST [BUILD] +_ACEOF +fi + +if test -n "$ac_init_help"; then + case $ac_init_help in + short | recursive ) echo "Configuration of wolfssl 3.6.0:";; + esac + cat <<\_ACEOF + +Optional Features: + --disable-option-checking ignore unrecognized --enable/--with options + --disable-FEATURE do not include FEATURE (same as --enable-FEATURE=no) + --enable-FEATURE[=ARG] include FEATURE [ARG=yes] + --enable-silent-rules less verbose build output (undo: "make V=1") + --disable-silent-rules verbose build output (undo: "make V=0") + --enable-static[=PKGS] build static libraries [default=no] + --enable-shared[=PKGS] build shared libraries [default=yes] + --enable-fast-install[=PKGS] + optimize for fast installation [default=yes] + --enable-dependency-tracking + do not reject slow dependency extractors + --disable-dependency-tracking + speeds up one-time build + --disable-libtool-lock avoid locking (might break parallel builds) + --enable-debug Add debug code/turns off optimizations (yes|no) + [default=no] + --enable-singlethreaded Enable wolfSSL single threaded (default: disabled) + --enable-dtls Enable wolfSSL DTLS (default: disabled) + --enable-opensslextra Enable extra OpenSSL API, size+ (default: disabled) + --enable-maxstrength Enable Max Strengh build, allows TLSv1.2-AEAD-PFS + ciphers only (default: disabled) + --enable-ipv6 Enable testing of IPV6 (default: disabled) + --enable-fortress Enable SSL fortress build (default: disabled) + --enable-bump Enable SSL Bump build (default: disabled) + --enable-leanpsk Enable Lean PSK build (default: disabled) + --enable-bigcache Enable big session cache (default: disabled) + --enable-hugecache Enable huge session cache (default: disabled) + --enable-smallcache Enable small session cache (default: disabled) + --enable-savesession Enable persistent session cache (default: disabled) + --enable-savecert Enable persistent cert cache (default: disabled) + --enable-atomicuser Enable Atomic User Record Layer (default: disabled) + --enable-pkcallbacks Enable Public Key Callbacks (default: disabled) + --enable-sniffer Enable wolfSSL sniffer support (default: disabled) + --enable-aesgcm Enable wolfSSL AES-GCM support (default: enabled) + --enable-aesccm Enable wolfSSL AES-CCM support (default: disabled) + --enable-aesni Enable wolfSSL AES-NI support (default: disabled) + --enable-intelasm Enable All Intel ASM speedups (default: disabled) + --enable-camellia Enable wolfSSL Camellia support (default: disabled) + --enable-md2 Enable wolfSSL MD2 support (default: disabled) + --enable-nullcipher Enable wolfSSL NULL cipher support (default: disabled) + --enable-ripemd Enable wolfSSL RIPEMD-160 support (default: disabled) + --enable-blake2 Enable wolfSSL BLAKE2 support (default: disabled) + --enable-sha512 Enable wolfSSL SHA-512 support (default: enabled on + x86_64) + --enable-sessioncerts Enable session cert storing (default: disabled) + --enable-keygen Enable key generation (default: disabled) + --enable-certgen Enable cert generation (default: disabled) + --enable-certreq Enable cert request generation (default: disabled) + --enable-sep Enable sep extensions (default: disabled) + --enable-hkdf Enable HKDF (HMAC-KDF) support (default: disabled) + --enable-dsa Enable DSA (default: disabled) + --enable-ecc Enable ECC (default: enabled on x86_64) + --enable-curve25519 Enable Curve25519 (default: disabled) + --enable-ed25519 Enable ED25519 (default: disabled) + --enable-fpecc Enable Fixed Point cache ECC (default: disabled) + --enable-eccencrypt Enable ECC encrypt (default: disabled) + --enable-psk Enable PSK (default: disabled) + --enable-errorstrings Enable error strings table (default: enabled) + --enable-oldtls Enable old TLS versions < 1.2 (default: enabled) + --enable-stacksize Enable stack size info on examples (default: disabled) + --enable-memory Enable memory callbacks (default: enabled) + --enable-rsa Enable RSA (default: enabled) + --enable-dh Enable DH (default: enabled) + --enable-anon Enable Anonymous (default: disabled) + --enable-asn Enable ASN (default: enabled) + --enable-aes Enable AES (default: enabled) + --enable-coding Enable Coding base 16/64 (default: enabled) + --enable-des3 Enable DES3 (default: enabled) + --enable-arc4 Enable ARC4 (default: disabled) + --enable-md5 Enable MD5 (default: enabled) + --enable-sha Enable SHA (default: enabled) + --enable-md4 Enable MD4 (default: disabled) + --enable-webserver Enable Web Server (default: disabled) + --enable-hc128 Enable HC-128 (default: disabled) + --enable-rabbit Enable RABBIT (default: disabled) + --enable-fips Enable FIPS 140-2, Will NOT work w/o FIPS license + (default: disabled) + --enable-poly1305 Enable wolfSSL POLY1305 support (default: enabled) + --enable-chacha Enable CHACHA (default: enabled) + --enable-hashdrbg Enable Hash DRBG support (default: enabled) + --enable-filesystem Enable Filesystem support (default: enabled) + --enable-inline Enable inline functions (default: enabled) + --enable-ocsp Enable OCSP (default: disabled) + --enable-crl Enable CRL (default: disabled) + --enable-crl-monitor Enable CRL Monitor (default: disabled) + --enable-sni Enable SNI (default: disabled) + --enable-maxfragment Enable Maximum Fragment Length (default: disabled) + --enable-truncatedhmac Enable Truncated HMAC (default: disabled) + --enable-renegotiation-indication + Enable Renegotiation Indication (default: disabled) + --enable-secure-renegotiation + Enable Secure Renegotiation (default: disabled) + --enable-supportedcurves + Enable Supported Elliptic Curves (default: disabled) + --enable-session-ticket Enable Session Ticket (default: disabled) + --enable-tlsx Enable all TLS Extensions (default: disabled) + --enable-pkcs7 Enable PKCS7 (default: disabled) + --enable-scep Enable wolfSCEP (default: disabled) + --enable-smallstack Enable Small Stack Usage (default: disabled) + --enable-valgrind Enable valgrind for unit tests (default: disabled) + --enable-testcert Enable Test Cert (default: disabled) + --enable-iopool Enable I/O Pool example (default: disabled) + --enable-certservice Enable cert service (default: disabled) + --enable-pwdbased Enable PWDBASED (default: disabled) + --enable-fastmath Enable fast math ops (default: enabled on x86_64) + --enable-fasthugemath Enable fast math + huge code (default: disabled) + --enable-examples Enable Examples (default: enabled) + --enable-mcapi Enable Microchip API (default: disabled) + --enable-jni Enable wolfSSL JNI (default: disabled) + --enable-jobserver[=no/yes/#] default=yes + Enable up to # make jobs + yes: enable one more than CPU count + + +Optional Packages: + --with-PACKAGE[=ARG] use PACKAGE [ARG=yes] + --without-PACKAGE do not use PACKAGE (same as --with-PACKAGE=no) + --with-pic[=PKGS] try to use only PIC/non-PIC objects [default=use + both] + --with-gnu-ld assume the C compiler uses GNU ld [default=no] + --with-sysroot=DIR Search for dependent libraries within DIR + (or the compiler's sysroot if not specified). + --with-ntru=PATH Path to NTRU install (default /usr/) + --with-libz=PATH PATH to libz install (default /usr/) + --with-cavium=PATH PATH to cavium/software dir + +Some influential environment variables: + CC C compiler command + CFLAGS C compiler flags + LDFLAGS linker flags, e.g. -L if you have libraries in a + nonstandard directory + LIBS libraries to pass to the linker, e.g. -l + CPPFLAGS (Objective) C/C++ preprocessor flags, e.g. -I if + you have headers in a nonstandard directory + CPP C preprocessor + CXX C++ compiler command + CXXFLAGS C++ compiler flags + CXXCPP C++ preprocessor + CCAS assembler compiler command (defaults to CC) + CCASFLAGS assembler compiler flags (defaults to CFLAGS) + +Use these variables to override the choices made by `configure' or to help +it to find libraries and programs with nonstandard names/locations. + +Report bugs to . +wolfssl home page: . +_ACEOF +ac_status=$? +fi + +if test "$ac_init_help" = "recursive"; then + # If there are subdirs, report their specific --help. + for ac_dir in : $ac_subdirs_all; do test "x$ac_dir" = x: && continue + test -d "$ac_dir" || + { cd "$srcdir" && ac_pwd=`pwd` && srcdir=. && test -d "$ac_dir"; } || + continue + ac_builddir=. + +case "$ac_dir" in +.) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;; +*) + ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'` + # A ".." for each directory in $ac_dir_suffix. + ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'` + case $ac_top_builddir_sub in + "") ac_top_builddir_sub=. ac_top_build_prefix= ;; + *) ac_top_build_prefix=$ac_top_builddir_sub/ ;; + esac ;; +esac +ac_abs_top_builddir=$ac_pwd +ac_abs_builddir=$ac_pwd$ac_dir_suffix +# for backward compatibility: +ac_top_builddir=$ac_top_build_prefix + +case $srcdir in + .) # We are building in place. + ac_srcdir=. + ac_top_srcdir=$ac_top_builddir_sub + ac_abs_top_srcdir=$ac_pwd ;; + [\\/]* | ?:[\\/]* ) # Absolute name. + ac_srcdir=$srcdir$ac_dir_suffix; + ac_top_srcdir=$srcdir + ac_abs_top_srcdir=$srcdir ;; + *) # Relative name. + ac_srcdir=$ac_top_build_prefix$srcdir$ac_dir_suffix + ac_top_srcdir=$ac_top_build_prefix$srcdir + ac_abs_top_srcdir=$ac_pwd/$srcdir ;; +esac +ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix + + cd "$ac_dir" || { ac_status=$?; continue; } + # Check for guested configure. + if test -f "$ac_srcdir/configure.gnu"; then + echo && + $SHELL "$ac_srcdir/configure.gnu" --help=recursive + elif test -f "$ac_srcdir/configure"; then + echo && + $SHELL "$ac_srcdir/configure" --help=recursive + else + $as_echo "$as_me: WARNING: no configuration information is in $ac_dir" >&2 + fi || ac_status=$? + cd "$ac_pwd" || { ac_status=$?; break; } + done +fi + +test -n "$ac_init_help" && exit $ac_status +if $ac_init_version; then + cat <<\_ACEOF +wolfssl configure 3.6.0 +generated by GNU Autoconf 2.69 + +Copyright (C) 2012 Free Software Foundation, Inc. +This configure script is free software; the Free Software Foundation +gives unlimited permission to copy, distribute and modify it. +_ACEOF + exit +fi + +## ------------------------ ## +## Autoconf initialization. ## +## ------------------------ ## + +# ac_fn_c_try_compile LINENO +# -------------------------- +# Try to compile conftest.$ac_ext, and return whether this succeeded. +ac_fn_c_try_compile () +{ + as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + rm -f conftest.$ac_objext + if { { ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compile") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + grep -v '^ *+' conftest.err >conftest.er1 + cat conftest.er1 >&5 + mv -f conftest.er1 conftest.err + fi + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then : + ac_retval=0 +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_retval=1 +fi + eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno + as_fn_set_status $ac_retval + +} # ac_fn_c_try_compile + +# ac_fn_c_try_link LINENO +# ----------------------- +# Try to link conftest.$ac_ext, and return whether this succeeded. +ac_fn_c_try_link () +{ + as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + rm -f conftest.$ac_objext conftest$ac_exeext + if { { ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + grep -v '^ *+' conftest.err >conftest.er1 + cat conftest.er1 >&5 + mv -f conftest.er1 conftest.err + fi + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest$ac_exeext && { + test "$cross_compiling" = yes || + test -x conftest$ac_exeext + }; then : + ac_retval=0 +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_retval=1 +fi + # Delete the IPA/IPO (Inter Procedural Analysis/Optimization) information + # created by the PGI compiler (conftest_ipa8_conftest.oo), as it would + # interfere with the next link command; also delete a directory that is + # left behind by Apple's compiler. We do this before executing the actions. + rm -rf conftest.dSYM conftest_ipa8_conftest.oo + eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno + as_fn_set_status $ac_retval + +} # ac_fn_c_try_link + +# ac_fn_c_check_header_compile LINENO HEADER VAR INCLUDES +# ------------------------------------------------------- +# Tests whether HEADER exists and can be compiled using the include files in +# INCLUDES, setting the cache variable VAR accordingly. +ac_fn_c_check_header_compile () +{ + as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5 +$as_echo_n "checking for $2... " >&6; } +if eval \${$3+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$4 +#include <$2> +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$3=yes" +else + eval "$3=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +eval ac_res=\$$3 + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } + eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno + +} # ac_fn_c_check_header_compile + +# ac_fn_c_try_cpp LINENO +# ---------------------- +# Try to preprocess conftest.$ac_ext, and return whether this succeeded. +ac_fn_c_try_cpp () +{ + as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + if { { ac_try="$ac_cpp conftest.$ac_ext" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_cpp conftest.$ac_ext") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + grep -v '^ *+' conftest.err >conftest.er1 + cat conftest.er1 >&5 + mv -f conftest.er1 conftest.err + fi + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } > conftest.i && { + test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || + test ! -s conftest.err + }; then : + ac_retval=0 +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_retval=1 +fi + eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno + as_fn_set_status $ac_retval + +} # ac_fn_c_try_cpp + +# ac_fn_c_try_run LINENO +# ---------------------- +# Try to link conftest.$ac_ext, and return whether this succeeded. Assumes +# that executables *can* be run. +ac_fn_c_try_run () +{ + as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + if { { ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } && { ac_try='./conftest$ac_exeext' + { { case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; }; then : + ac_retval=0 +else + $as_echo "$as_me: program exited with status $ac_status" >&5 + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_retval=$ac_status +fi + rm -rf conftest.dSYM conftest_ipa8_conftest.oo + eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno + as_fn_set_status $ac_retval + +} # ac_fn_c_try_run + +# ac_fn_c_check_func LINENO FUNC VAR +# ---------------------------------- +# Tests whether FUNC exists, setting the cache variable VAR accordingly +ac_fn_c_check_func () +{ + as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5 +$as_echo_n "checking for $2... " >&6; } +if eval \${$3+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +/* Define $2 to an innocuous variant, in case declares $2. + For example, HP-UX 11i declares gettimeofday. */ +#define $2 innocuous_$2 + +/* System header to define __stub macros and hopefully few prototypes, + which can conflict with char $2 (); below. + Prefer to if __STDC__ is defined, since + exists even on freestanding compilers. */ + +#ifdef __STDC__ +# include +#else +# include +#endif + +#undef $2 + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char $2 (); +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined __stub_$2 || defined __stub___$2 +choke me +#endif + +int +main () +{ +return $2 (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + eval "$3=yes" +else + eval "$3=no" +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +fi +eval ac_res=\$$3 + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } + eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno + +} # ac_fn_c_check_func + +# ac_fn_cxx_try_compile LINENO +# ---------------------------- +# Try to compile conftest.$ac_ext, and return whether this succeeded. +ac_fn_cxx_try_compile () +{ + as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + rm -f conftest.$ac_objext + if { { ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compile") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + grep -v '^ *+' conftest.err >conftest.er1 + cat conftest.er1 >&5 + mv -f conftest.er1 conftest.err + fi + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } && { + test -z "$ac_cxx_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then : + ac_retval=0 +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_retval=1 +fi + eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno + as_fn_set_status $ac_retval + +} # ac_fn_cxx_try_compile + +# ac_fn_cxx_try_cpp LINENO +# ------------------------ +# Try to preprocess conftest.$ac_ext, and return whether this succeeded. +ac_fn_cxx_try_cpp () +{ + as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + if { { ac_try="$ac_cpp conftest.$ac_ext" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_cpp conftest.$ac_ext") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + grep -v '^ *+' conftest.err >conftest.er1 + cat conftest.er1 >&5 + mv -f conftest.er1 conftest.err + fi + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } > conftest.i && { + test -z "$ac_cxx_preproc_warn_flag$ac_cxx_werror_flag" || + test ! -s conftest.err + }; then : + ac_retval=0 +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_retval=1 +fi + eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno + as_fn_set_status $ac_retval + +} # ac_fn_cxx_try_cpp + +# ac_fn_cxx_try_link LINENO +# ------------------------- +# Try to link conftest.$ac_ext, and return whether this succeeded. +ac_fn_cxx_try_link () +{ + as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + rm -f conftest.$ac_objext conftest$ac_exeext + if { { ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + grep -v '^ *+' conftest.err >conftest.er1 + cat conftest.er1 >&5 + mv -f conftest.er1 conftest.err + fi + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } && { + test -z "$ac_cxx_werror_flag" || + test ! -s conftest.err + } && test -s conftest$ac_exeext && { + test "$cross_compiling" = yes || + test -x conftest$ac_exeext + }; then : + ac_retval=0 +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_retval=1 +fi + # Delete the IPA/IPO (Inter Procedural Analysis/Optimization) information + # created by the PGI compiler (conftest_ipa8_conftest.oo), as it would + # interfere with the next link command; also delete a directory that is + # left behind by Apple's compiler. We do this before executing the actions. + rm -rf conftest.dSYM conftest_ipa8_conftest.oo + eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno + as_fn_set_status $ac_retval + +} # ac_fn_cxx_try_link + +# ac_fn_c_check_header_mongrel LINENO HEADER VAR INCLUDES +# ------------------------------------------------------- +# Tests whether HEADER exists, giving a warning if it cannot be compiled using +# the include files in INCLUDES and setting the cache variable VAR +# accordingly. +ac_fn_c_check_header_mongrel () +{ + as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + if eval \${$3+:} false; then : + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5 +$as_echo_n "checking for $2... " >&6; } +if eval \${$3+:} false; then : + $as_echo_n "(cached) " >&6 +fi +eval ac_res=\$$3 + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +else + # Is the header compilable? +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking $2 usability" >&5 +$as_echo_n "checking $2 usability... " >&6; } +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$4 +#include <$2> +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_header_compiler=yes +else + ac_header_compiler=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_header_compiler" >&5 +$as_echo "$ac_header_compiler" >&6; } + +# Is the header present? +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking $2 presence" >&5 +$as_echo_n "checking $2 presence... " >&6; } +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include <$2> +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + ac_header_preproc=yes +else + ac_header_preproc=no +fi +rm -f conftest.err conftest.i conftest.$ac_ext +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_header_preproc" >&5 +$as_echo "$ac_header_preproc" >&6; } + +# So? What about this header? +case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in #(( + yes:no: ) + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $2: accepted by the compiler, rejected by the preprocessor!" >&5 +$as_echo "$as_me: WARNING: $2: accepted by the compiler, rejected by the preprocessor!" >&2;} + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $2: proceeding with the compiler's result" >&5 +$as_echo "$as_me: WARNING: $2: proceeding with the compiler's result" >&2;} + ;; + no:yes:* ) + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $2: present but cannot be compiled" >&5 +$as_echo "$as_me: WARNING: $2: present but cannot be compiled" >&2;} + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $2: check for missing prerequisite headers?" >&5 +$as_echo "$as_me: WARNING: $2: check for missing prerequisite headers?" >&2;} + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $2: see the Autoconf documentation" >&5 +$as_echo "$as_me: WARNING: $2: see the Autoconf documentation" >&2;} + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $2: section \"Present But Cannot Be Compiled\"" >&5 +$as_echo "$as_me: WARNING: $2: section \"Present But Cannot Be Compiled\"" >&2;} + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $2: proceeding with the compiler's result" >&5 +$as_echo "$as_me: WARNING: $2: proceeding with the compiler's result" >&2;} +( $as_echo "## -------------------------------------------------------- ## +## Report this to https://github.com/wolfssl/wolfssl/issues ## +## -------------------------------------------------------- ##" + ) | sed "s/^/$as_me: WARNING: /" >&2 + ;; +esac + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5 +$as_echo_n "checking for $2... " >&6; } +if eval \${$3+:} false; then : + $as_echo_n "(cached) " >&6 +else + eval "$3=\$ac_header_compiler" +fi +eval ac_res=\$$3 + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +fi + eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno + +} # ac_fn_c_check_header_mongrel + +# ac_fn_c_compute_int LINENO EXPR VAR INCLUDES +# -------------------------------------------- +# Tries to find the compile-time value of EXPR in a program that includes +# INCLUDES, setting VAR accordingly. Returns whether the value could be +# computed +ac_fn_c_compute_int () +{ + as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + if test "$cross_compiling" = yes; then + # Depending upon the size, compute the lo and hi bounds. +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$4 +int +main () +{ +static int test_array [1 - 2 * !(($2) >= 0)]; +test_array [0] = 0; +return test_array [0]; + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_lo=0 ac_mid=0 + while :; do + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$4 +int +main () +{ +static int test_array [1 - 2 * !(($2) <= $ac_mid)]; +test_array [0] = 0; +return test_array [0]; + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_hi=$ac_mid; break +else + as_fn_arith $ac_mid + 1 && ac_lo=$as_val + if test $ac_lo -le $ac_mid; then + ac_lo= ac_hi= + break + fi + as_fn_arith 2 '*' $ac_mid + 1 && ac_mid=$as_val +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + done +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$4 +int +main () +{ +static int test_array [1 - 2 * !(($2) < 0)]; +test_array [0] = 0; +return test_array [0]; + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_hi=-1 ac_mid=-1 + while :; do + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$4 +int +main () +{ +static int test_array [1 - 2 * !(($2) >= $ac_mid)]; +test_array [0] = 0; +return test_array [0]; + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_lo=$ac_mid; break +else + as_fn_arith '(' $ac_mid ')' - 1 && ac_hi=$as_val + if test $ac_mid -le $ac_hi; then + ac_lo= ac_hi= + break + fi + as_fn_arith 2 '*' $ac_mid && ac_mid=$as_val +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + done +else + ac_lo= ac_hi= +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +# Binary search between lo and hi bounds. +while test "x$ac_lo" != "x$ac_hi"; do + as_fn_arith '(' $ac_hi - $ac_lo ')' / 2 + $ac_lo && ac_mid=$as_val + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$4 +int +main () +{ +static int test_array [1 - 2 * !(($2) <= $ac_mid)]; +test_array [0] = 0; +return test_array [0]; + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_hi=$ac_mid +else + as_fn_arith '(' $ac_mid ')' + 1 && ac_lo=$as_val +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +done +case $ac_lo in #(( +?*) eval "$3=\$ac_lo"; ac_retval=0 ;; +'') ac_retval=1 ;; +esac + else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$4 +static long int longval () { return $2; } +static unsigned long int ulongval () { return $2; } +#include +#include +int +main () +{ + + FILE *f = fopen ("conftest.val", "w"); + if (! f) + return 1; + if (($2) < 0) + { + long int i = longval (); + if (i != ($2)) + return 1; + fprintf (f, "%ld", i); + } + else + { + unsigned long int i = ulongval (); + if (i != ($2)) + return 1; + fprintf (f, "%lu", i); + } + /* Do not output a trailing newline, as this causes \r\n confusion + on some platforms. */ + return ferror (f) || fclose (f) != 0; + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + echo >>conftest.val; read $3 &5 +$as_echo_n "checking for $2... " >&6; } +if eval \${$3+:} false; then : + $as_echo_n "(cached) " >&6 +else + eval "$3=no" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$4 +int +main () +{ +if (sizeof ($2)) + return 0; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$4 +int +main () +{ +if (sizeof (($2))) + return 0; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + +else + eval "$3=yes" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +eval ac_res=\$$3 + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } + eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno + +} # ac_fn_c_check_type + +# ac_fn_c_find_uintX_t LINENO BITS VAR +# ------------------------------------ +# Finds an unsigned integer type with width BITS, setting cache variable VAR +# accordingly. +ac_fn_c_find_uintX_t () +{ + as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for uint$2_t" >&5 +$as_echo_n "checking for uint$2_t... " >&6; } +if eval \${$3+:} false; then : + $as_echo_n "(cached) " >&6 +else + eval "$3=no" + # Order is important - never check a type that is potentially smaller + # than half of the expected target width. + for ac_type in uint$2_t 'unsigned int' 'unsigned long int' \ + 'unsigned long long int' 'unsigned short int' 'unsigned char'; do + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$ac_includes_default +int +main () +{ +static int test_array [1 - 2 * !((($ac_type) -1 >> ($2 / 2 - 1)) >> ($2 / 2 - 1) == 3)]; +test_array [0] = 0; +return test_array [0]; + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + case $ac_type in #( + uint$2_t) : + eval "$3=yes" ;; #( + *) : + eval "$3=\$ac_type" ;; +esac +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if eval test \"x\$"$3"\" = x"no"; then : + +else + break +fi + done +fi +eval ac_res=\$$3 + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } + eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno + +} # ac_fn_c_find_uintX_t +cat >config.log <<_ACEOF +This file contains any messages produced by compilers while +running configure, to aid debugging if configure makes a mistake. + +It was created by wolfssl $as_me 3.6.0, which was +generated by GNU Autoconf 2.69. Invocation command line was + + $ $0 $@ + +_ACEOF +exec 5>>config.log +{ +cat <<_ASUNAME +## --------- ## +## Platform. ## +## --------- ## + +hostname = `(hostname || uname -n) 2>/dev/null | sed 1q` +uname -m = `(uname -m) 2>/dev/null || echo unknown` +uname -r = `(uname -r) 2>/dev/null || echo unknown` +uname -s = `(uname -s) 2>/dev/null || echo unknown` +uname -v = `(uname -v) 2>/dev/null || echo unknown` + +/usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null || echo unknown` +/bin/uname -X = `(/bin/uname -X) 2>/dev/null || echo unknown` + +/bin/arch = `(/bin/arch) 2>/dev/null || echo unknown` +/usr/bin/arch -k = `(/usr/bin/arch -k) 2>/dev/null || echo unknown` +/usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null || echo unknown` +/usr/bin/hostinfo = `(/usr/bin/hostinfo) 2>/dev/null || echo unknown` +/bin/machine = `(/bin/machine) 2>/dev/null || echo unknown` +/usr/bin/oslevel = `(/usr/bin/oslevel) 2>/dev/null || echo unknown` +/bin/universe = `(/bin/universe) 2>/dev/null || echo unknown` + +_ASUNAME + +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + $as_echo "PATH: $as_dir" + done +IFS=$as_save_IFS + +} >&5 + +cat >&5 <<_ACEOF + + +## ----------- ## +## Core tests. ## +## ----------- ## + +_ACEOF + + +# Keep a trace of the command line. +# Strip out --no-create and --no-recursion so they do not pile up. +# Strip out --silent because we don't want to record it for future runs. +# Also quote any args containing shell meta-characters. +# Make two passes to allow for proper duplicate-argument suppression. +ac_configure_args= +ac_configure_args0= +ac_configure_args1= +ac_must_keep_next=false +for ac_pass in 1 2 +do + for ac_arg + do + case $ac_arg in + -no-create | --no-c* | -n | -no-recursion | --no-r*) continue ;; + -q | -quiet | --quiet | --quie | --qui | --qu | --q \ + | -silent | --silent | --silen | --sile | --sil) + continue ;; + *\'*) + ac_arg=`$as_echo "$ac_arg" | sed "s/'/'\\\\\\\\''/g"` ;; + esac + case $ac_pass in + 1) as_fn_append ac_configure_args0 " '$ac_arg'" ;; + 2) + as_fn_append ac_configure_args1 " '$ac_arg'" + if test $ac_must_keep_next = true; then + ac_must_keep_next=false # Got value, back to normal. + else + case $ac_arg in + *=* | --config-cache | -C | -disable-* | --disable-* \ + | -enable-* | --enable-* | -gas | --g* | -nfp | --nf* \ + | -q | -quiet | --q* | -silent | --sil* | -v | -verb* \ + | -with-* | --with-* | -without-* | --without-* | --x) + case "$ac_configure_args0 " in + "$ac_configure_args1"*" '$ac_arg' "* ) continue ;; + esac + ;; + -* ) ac_must_keep_next=true ;; + esac + fi + as_fn_append ac_configure_args " '$ac_arg'" + ;; + esac + done +done +{ ac_configure_args0=; unset ac_configure_args0;} +{ ac_configure_args1=; unset ac_configure_args1;} + +# When interrupted or exit'd, cleanup temporary files, and complete +# config.log. We remove comments because anyway the quotes in there +# would cause problems or look ugly. +# WARNING: Use '\'' to represent an apostrophe within the trap. +# WARNING: Do not start the trap code with a newline, due to a FreeBSD 4.0 bug. +trap 'exit_status=$? + # Save into config.log some information that might help in debugging. + { + echo + + $as_echo "## ---------------- ## +## Cache variables. ## +## ---------------- ##" + echo + # The following way of writing the cache mishandles newlines in values, +( + for ac_var in `(set) 2>&1 | sed -n '\''s/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'\''`; do + eval ac_val=\$$ac_var + case $ac_val in #( + *${as_nl}*) + case $ac_var in #( + *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 +$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; + esac + case $ac_var in #( + _ | IFS | as_nl) ;; #( + BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #( + *) { eval $ac_var=; unset $ac_var;} ;; + esac ;; + esac + done + (set) 2>&1 | + case $as_nl`(ac_space='\'' '\''; set) 2>&1` in #( + *${as_nl}ac_space=\ *) + sed -n \ + "s/'\''/'\''\\\\'\'''\''/g; + s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\''\\2'\''/p" + ;; #( + *) + sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p" + ;; + esac | + sort +) + echo + + $as_echo "## ----------------- ## +## Output variables. ## +## ----------------- ##" + echo + for ac_var in $ac_subst_vars + do + eval ac_val=\$$ac_var + case $ac_val in + *\'\''*) ac_val=`$as_echo "$ac_val" | sed "s/'\''/'\''\\\\\\\\'\'''\''/g"`;; + esac + $as_echo "$ac_var='\''$ac_val'\''" + done | sort + echo + + if test -n "$ac_subst_files"; then + $as_echo "## ------------------- ## +## File substitutions. ## +## ------------------- ##" + echo + for ac_var in $ac_subst_files + do + eval ac_val=\$$ac_var + case $ac_val in + *\'\''*) ac_val=`$as_echo "$ac_val" | sed "s/'\''/'\''\\\\\\\\'\'''\''/g"`;; + esac + $as_echo "$ac_var='\''$ac_val'\''" + done | sort + echo + fi + + if test -s confdefs.h; then + $as_echo "## ----------- ## +## confdefs.h. ## +## ----------- ##" + echo + cat confdefs.h + echo + fi + test "$ac_signal" != 0 && + $as_echo "$as_me: caught signal $ac_signal" + $as_echo "$as_me: exit $exit_status" + } >&5 + rm -f core *.core core.conftest.* && + rm -f -r conftest* confdefs* conf$$* $ac_clean_files && + exit $exit_status +' 0 +for ac_signal in 1 2 13 15; do + trap 'ac_signal='$ac_signal'; as_fn_exit 1' $ac_signal +done +ac_signal=0 + +# confdefs.h avoids OS command line length limits that DEFS can exceed. +rm -f -r conftest* confdefs.h + +$as_echo "/* confdefs.h */" > confdefs.h + +# Predefined preprocessor variables. + +cat >>confdefs.h <<_ACEOF +#define PACKAGE_NAME "$PACKAGE_NAME" +_ACEOF + +cat >>confdefs.h <<_ACEOF +#define PACKAGE_TARNAME "$PACKAGE_TARNAME" +_ACEOF + +cat >>confdefs.h <<_ACEOF +#define PACKAGE_VERSION "$PACKAGE_VERSION" +_ACEOF + +cat >>confdefs.h <<_ACEOF +#define PACKAGE_STRING "$PACKAGE_STRING" +_ACEOF + +cat >>confdefs.h <<_ACEOF +#define PACKAGE_BUGREPORT "$PACKAGE_BUGREPORT" +_ACEOF + +cat >>confdefs.h <<_ACEOF +#define PACKAGE_URL "$PACKAGE_URL" +_ACEOF + + +# Let the site file select an alternate cache file if it wants to. +# Prefer an explicitly selected file to automatically selected ones. +ac_site_file1=NONE +ac_site_file2=NONE +if test -n "$CONFIG_SITE"; then + # We do not want a PATH search for config.site. + case $CONFIG_SITE in #(( + -*) ac_site_file1=./$CONFIG_SITE;; + */*) ac_site_file1=$CONFIG_SITE;; + *) ac_site_file1=./$CONFIG_SITE;; + esac +elif test "x$prefix" != xNONE; then + ac_site_file1=$prefix/share/config.site + ac_site_file2=$prefix/etc/config.site +else + ac_site_file1=$ac_default_prefix/share/config.site + ac_site_file2=$ac_default_prefix/etc/config.site +fi +for ac_site_file in "$ac_site_file1" "$ac_site_file2" +do + test "x$ac_site_file" = xNONE && continue + if test /dev/null != "$ac_site_file" && test -r "$ac_site_file"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: loading site script $ac_site_file" >&5 +$as_echo "$as_me: loading site script $ac_site_file" >&6;} + sed 's/^/| /' "$ac_site_file" >&5 + . "$ac_site_file" \ + || { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error $? "failed to load site script $ac_site_file +See \`config.log' for more details" "$LINENO" 5; } + fi +done + +if test -r "$cache_file"; then + # Some versions of bash will fail to source /dev/null (special files + # actually), so we avoid doing that. DJGPP emulates it as a regular file. + if test /dev/null != "$cache_file" && test -f "$cache_file"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: loading cache $cache_file" >&5 +$as_echo "$as_me: loading cache $cache_file" >&6;} + case $cache_file in + [\\/]* | ?:[\\/]* ) . "$cache_file";; + *) . "./$cache_file";; + esac + fi +else + { $as_echo "$as_me:${as_lineno-$LINENO}: creating cache $cache_file" >&5 +$as_echo "$as_me: creating cache $cache_file" >&6;} + >$cache_file +fi + +# Check that the precious variables saved in the cache have kept the same +# value. +ac_cache_corrupted=false +for ac_var in $ac_precious_vars; do + eval ac_old_set=\$ac_cv_env_${ac_var}_set + eval ac_new_set=\$ac_env_${ac_var}_set + eval ac_old_val=\$ac_cv_env_${ac_var}_value + eval ac_new_val=\$ac_env_${ac_var}_value + case $ac_old_set,$ac_new_set in + set,) + { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&5 +$as_echo "$as_me: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&2;} + ac_cache_corrupted=: ;; + ,set) + { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' was not set in the previous run" >&5 +$as_echo "$as_me: error: \`$ac_var' was not set in the previous run" >&2;} + ac_cache_corrupted=: ;; + ,);; + *) + if test "x$ac_old_val" != "x$ac_new_val"; then + # differences in whitespace do not lead to failure. + ac_old_val_w=`echo x $ac_old_val` + ac_new_val_w=`echo x $ac_new_val` + if test "$ac_old_val_w" != "$ac_new_val_w"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' has changed since the previous run:" >&5 +$as_echo "$as_me: error: \`$ac_var' has changed since the previous run:" >&2;} + ac_cache_corrupted=: + else + { $as_echo "$as_me:${as_lineno-$LINENO}: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&5 +$as_echo "$as_me: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&2;} + eval $ac_var=\$ac_old_val + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: former value: \`$ac_old_val'" >&5 +$as_echo "$as_me: former value: \`$ac_old_val'" >&2;} + { $as_echo "$as_me:${as_lineno-$LINENO}: current value: \`$ac_new_val'" >&5 +$as_echo "$as_me: current value: \`$ac_new_val'" >&2;} + fi;; + esac + # Pass precious variables to config.status. + if test "$ac_new_set" = set; then + case $ac_new_val in + *\'*) ac_arg=$ac_var=`$as_echo "$ac_new_val" | sed "s/'/'\\\\\\\\''/g"` ;; + *) ac_arg=$ac_var=$ac_new_val ;; + esac + case " $ac_configure_args " in + *" '$ac_arg' "*) ;; # Avoid dups. Use of quotes ensures accuracy. + *) as_fn_append ac_configure_args " '$ac_arg'" ;; + esac + fi +done +if $ac_cache_corrupted; then + { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} + { $as_echo "$as_me:${as_lineno-$LINENO}: error: changes in the environment can compromise the build" >&5 +$as_echo "$as_me: error: changes in the environment can compromise the build" >&2;} + as_fn_error $? "run \`make distclean' and/or \`rm $cache_file' and start over" "$LINENO" 5 +fi +## -------------------- ## +## Main body of script. ## +## -------------------- ## + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + + +ac_aux_dir= +for ac_dir in build-aux "$srcdir"/build-aux; do + if test -f "$ac_dir/install-sh"; then + ac_aux_dir=$ac_dir + ac_install_sh="$ac_aux_dir/install-sh -c" + break + elif test -f "$ac_dir/install.sh"; then + ac_aux_dir=$ac_dir + ac_install_sh="$ac_aux_dir/install.sh -c" + break + elif test -f "$ac_dir/shtool"; then + ac_aux_dir=$ac_dir + ac_install_sh="$ac_aux_dir/shtool install -c" + break + fi +done +if test -z "$ac_aux_dir"; then + as_fn_error $? "cannot find install-sh, install.sh, or shtool in build-aux \"$srcdir\"/build-aux" "$LINENO" 5 +fi + +# These three variables are undocumented and unsupported, +# and are intended to be withdrawn in a future Autoconf release. +# They can cause serious problems if a builder's source tree is in a directory +# whose full name contains unusual characters. +ac_config_guess="$SHELL $ac_aux_dir/config.guess" # Please don't use this var. +ac_config_sub="$SHELL $ac_aux_dir/config.sub" # Please don't use this var. +ac_configure="$SHELL $ac_aux_dir/configure" # Please don't use this var. + + + +# Make sure we can run config.sub. +$SHELL "$ac_aux_dir/config.sub" sun4 >/dev/null 2>&1 || + as_fn_error $? "cannot run $SHELL $ac_aux_dir/config.sub" "$LINENO" 5 + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking build system type" >&5 +$as_echo_n "checking build system type... " >&6; } +if ${ac_cv_build+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_build_alias=$build_alias +test "x$ac_build_alias" = x && + ac_build_alias=`$SHELL "$ac_aux_dir/config.guess"` +test "x$ac_build_alias" = x && + as_fn_error $? "cannot guess build type; you must specify one" "$LINENO" 5 +ac_cv_build=`$SHELL "$ac_aux_dir/config.sub" $ac_build_alias` || + as_fn_error $? "$SHELL $ac_aux_dir/config.sub $ac_build_alias failed" "$LINENO" 5 + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_build" >&5 +$as_echo "$ac_cv_build" >&6; } +case $ac_cv_build in +*-*-*) ;; +*) as_fn_error $? "invalid value of canonical build" "$LINENO" 5;; +esac +build=$ac_cv_build +ac_save_IFS=$IFS; IFS='-' +set x $ac_cv_build +shift +build_cpu=$1 +build_vendor=$2 +shift; shift +# Remember, the first character of IFS is used to create $*, +# except with old shells: +build_os=$* +IFS=$ac_save_IFS +case $build_os in *\ *) build_os=`echo "$build_os" | sed 's/ /-/g'`;; esac + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking host system type" >&5 +$as_echo_n "checking host system type... " >&6; } +if ${ac_cv_host+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test "x$host_alias" = x; then + ac_cv_host=$ac_cv_build +else + ac_cv_host=`$SHELL "$ac_aux_dir/config.sub" $host_alias` || + as_fn_error $? "$SHELL $ac_aux_dir/config.sub $host_alias failed" "$LINENO" 5 +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_host" >&5 +$as_echo "$ac_cv_host" >&6; } +case $ac_cv_host in +*-*-*) ;; +*) as_fn_error $? "invalid value of canonical host" "$LINENO" 5;; +esac +host=$ac_cv_host +ac_save_IFS=$IFS; IFS='-' +set x $ac_cv_host +shift +host_cpu=$1 +host_vendor=$2 +shift; shift +# Remember, the first character of IFS is used to create $*, +# except with old shells: +host_os=$* +IFS=$ac_save_IFS +case $host_os in *\ *) host_os=`echo "$host_os" | sed 's/ /-/g'`;; esac + + + + +am__api_version='1.14' + +# Find a good install program. We prefer a C program (faster), +# so one script is as good as another. But avoid the broken or +# incompatible versions: +# SysV /etc/install, /usr/sbin/install +# SunOS /usr/etc/install +# IRIX /sbin/install +# AIX /bin/install +# AmigaOS /C/install, which installs bootblocks on floppy discs +# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag +# AFS /usr/afsws/bin/install, which mishandles nonexistent args +# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" +# OS/2's system install, which has a completely different semantic +# ./install, which can be erroneously created by make from ./install.sh. +# Reject install programs that cannot install multiple files. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a BSD-compatible install" >&5 +$as_echo_n "checking for a BSD-compatible install... " >&6; } +if test -z "$INSTALL"; then +if ${ac_cv_path_install+:} false; then : + $as_echo_n "(cached) " >&6 +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + # Account for people who put trailing slashes in PATH elements. +case $as_dir/ in #(( + ./ | .// | /[cC]/* | \ + /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \ + ?:[\\/]os2[\\/]install[\\/]* | ?:[\\/]OS2[\\/]INSTALL[\\/]* | \ + /usr/ucb/* ) ;; + *) + # OSF1 and SCO ODT 3.0 have their own names for install. + # Don't use installbsd from OSF since it installs stuff as root + # by default. + for ac_prog in ginstall scoinst install; do + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_prog$ac_exec_ext"; then + if test $ac_prog = install && + grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # AIX install. It has an incompatible calling convention. + : + elif test $ac_prog = install && + grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # program-specific install script used by HP pwplus--don't use. + : + else + rm -rf conftest.one conftest.two conftest.dir + echo one > conftest.one + echo two > conftest.two + mkdir conftest.dir + if "$as_dir/$ac_prog$ac_exec_ext" -c conftest.one conftest.two "`pwd`/conftest.dir" && + test -s conftest.one && test -s conftest.two && + test -s conftest.dir/conftest.one && + test -s conftest.dir/conftest.two + then + ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c" + break 3 + fi + fi + fi + done + done + ;; +esac + + done +IFS=$as_save_IFS + +rm -rf conftest.one conftest.two conftest.dir + +fi + if test "${ac_cv_path_install+set}" = set; then + INSTALL=$ac_cv_path_install + else + # As a last resort, use the slow shell script. Don't cache a + # value for INSTALL within a source directory, because that will + # break other packages using the cache if that directory is + # removed, or if the value is a relative name. + INSTALL=$ac_install_sh + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $INSTALL" >&5 +$as_echo "$INSTALL" >&6; } + +# Use test -z because SunOS4 sh mishandles braces in ${var-val}. +# It thinks the first close brace ends the variable substitution. +test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}' + +test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}' + +test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether build environment is sane" >&5 +$as_echo_n "checking whether build environment is sane... " >&6; } +# Reject unsafe characters in $srcdir or the absolute working directory +# name. Accept space and tab only in the latter. +am_lf=' +' +case `pwd` in + *[\\\"\#\$\&\'\`$am_lf]*) + as_fn_error $? "unsafe absolute working directory name" "$LINENO" 5;; +esac +case $srcdir in + *[\\\"\#\$\&\'\`$am_lf\ \ ]*) + as_fn_error $? "unsafe srcdir value: '$srcdir'" "$LINENO" 5;; +esac + +# Do 'set' in a subshell so we don't clobber the current shell's +# arguments. Must try -L first in case configure is actually a +# symlink; some systems play weird games with the mod time of symlinks +# (eg FreeBSD returns the mod time of the symlink's containing +# directory). +if ( + am_has_slept=no + for am_try in 1 2; do + echo "timestamp, slept: $am_has_slept" > conftest.file + set X `ls -Lt "$srcdir/configure" conftest.file 2> /dev/null` + if test "$*" = "X"; then + # -L didn't work. + set X `ls -t "$srcdir/configure" conftest.file` + fi + if test "$*" != "X $srcdir/configure conftest.file" \ + && test "$*" != "X conftest.file $srcdir/configure"; then + + # If neither matched, then we have a broken ls. This can happen + # if, for instance, CONFIG_SHELL is bash and it inherits a + # broken ls alias from the environment. This has actually + # happened. Such a system could not be considered "sane". + as_fn_error $? "ls -t appears to fail. Make sure there is not a broken + alias in your environment" "$LINENO" 5 + fi + if test "$2" = conftest.file || test $am_try -eq 2; then + break + fi + # Just in case. + sleep 1 + am_has_slept=yes + done + test "$2" = conftest.file + ) +then + # Ok. + : +else + as_fn_error $? "newly created file is older than distributed files! +Check your system clock" "$LINENO" 5 +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } +# If we didn't sleep, we still need to ensure time stamps of config.status and +# generated files are strictly newer. +am_sleep_pid= +if grep 'slept: no' conftest.file >/dev/null 2>&1; then + ( sleep 1 ) & + am_sleep_pid=$! +fi + +rm -f conftest.file + +test "$program_prefix" != NONE && + program_transform_name="s&^&$program_prefix&;$program_transform_name" +# Use a double $ so make ignores it. +test "$program_suffix" != NONE && + program_transform_name="s&\$&$program_suffix&;$program_transform_name" +# Double any \ or $. +# By default was `s,x,x', remove it if useless. +ac_script='s/[\\$]/&&/g;s/;s,x,x,$//' +program_transform_name=`$as_echo "$program_transform_name" | sed "$ac_script"` + +# expand $ac_aux_dir to an absolute path +am_aux_dir=`cd $ac_aux_dir && pwd` + +if test x"${MISSING+set}" != xset; then + case $am_aux_dir in + *\ * | *\ *) + MISSING="\${SHELL} \"$am_aux_dir/missing\"" ;; + *) + MISSING="\${SHELL} $am_aux_dir/missing" ;; + esac +fi +# Use eval to expand $SHELL +if eval "$MISSING --is-lightweight"; then + am_missing_run="$MISSING " +else + am_missing_run= + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: 'missing' script is too old or missing" >&5 +$as_echo "$as_me: WARNING: 'missing' script is too old or missing" >&2;} +fi + +if test x"${install_sh}" != xset; then + case $am_aux_dir in + *\ * | *\ *) + install_sh="\${SHELL} '$am_aux_dir/install-sh'" ;; + *) + install_sh="\${SHELL} $am_aux_dir/install-sh" + esac +fi + +# Installed binaries are usually stripped using 'strip' when the user +# run "make install-strip". However 'strip' might not be the right +# tool to use in cross-compilation environments, therefore Automake +# will honor the 'STRIP' environment variable to overrule this program. +if test "$cross_compiling" != no; then + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args. +set dummy ${ac_tool_prefix}strip; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_STRIP+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$STRIP"; then + ac_cv_prog_STRIP="$STRIP" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_STRIP="${ac_tool_prefix}strip" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +STRIP=$ac_cv_prog_STRIP +if test -n "$STRIP"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $STRIP" >&5 +$as_echo "$STRIP" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_STRIP"; then + ac_ct_STRIP=$STRIP + # Extract the first word of "strip", so it can be a program name with args. +set dummy strip; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_STRIP+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_STRIP"; then + ac_cv_prog_ac_ct_STRIP="$ac_ct_STRIP" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_STRIP="strip" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_STRIP=$ac_cv_prog_ac_ct_STRIP +if test -n "$ac_ct_STRIP"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_STRIP" >&5 +$as_echo "$ac_ct_STRIP" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_STRIP" = x; then + STRIP=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + STRIP=$ac_ct_STRIP + fi +else + STRIP="$ac_cv_prog_STRIP" +fi + +fi +INSTALL_STRIP_PROGRAM="\$(install_sh) -c -s" + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a thread-safe mkdir -p" >&5 +$as_echo_n "checking for a thread-safe mkdir -p... " >&6; } +if test -z "$MKDIR_P"; then + if ${ac_cv_path_mkdir+:} false; then : + $as_echo_n "(cached) " >&6 +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/opt/sfw/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in mkdir gmkdir; do + for ac_exec_ext in '' $ac_executable_extensions; do + as_fn_executable_p "$as_dir/$ac_prog$ac_exec_ext" || continue + case `"$as_dir/$ac_prog$ac_exec_ext" --version 2>&1` in #( + 'mkdir (GNU coreutils) '* | \ + 'mkdir (coreutils) '* | \ + 'mkdir (fileutils) '4.1*) + ac_cv_path_mkdir=$as_dir/$ac_prog$ac_exec_ext + break 3;; + esac + done + done + done +IFS=$as_save_IFS + +fi + + test -d ./--version && rmdir ./--version + if test "${ac_cv_path_mkdir+set}" = set; then + MKDIR_P="$ac_cv_path_mkdir -p" + else + # As a last resort, use the slow shell script. Don't cache a + # value for MKDIR_P within a source directory, because that will + # break other packages using the cache if that directory is + # removed, or if the value is a relative name. + MKDIR_P="$ac_install_sh -d" + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $MKDIR_P" >&5 +$as_echo "$MKDIR_P" >&6; } + +for ac_prog in gawk mawk nawk awk +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_AWK+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$AWK"; then + ac_cv_prog_AWK="$AWK" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_AWK="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +AWK=$ac_cv_prog_AWK +if test -n "$AWK"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AWK" >&5 +$as_echo "$AWK" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$AWK" && break +done + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ${MAKE-make} sets \$(MAKE)" >&5 +$as_echo_n "checking whether ${MAKE-make} sets \$(MAKE)... " >&6; } +set x ${MAKE-make} +ac_make=`$as_echo "$2" | sed 's/+/p/g; s/[^a-zA-Z0-9_]/_/g'` +if eval \${ac_cv_prog_make_${ac_make}_set+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat >conftest.make <<\_ACEOF +SHELL = /bin/sh +all: + @echo '@@@%%%=$(MAKE)=@@@%%%' +_ACEOF +# GNU make sometimes prints "make[1]: Entering ...", which would confuse us. +case `${MAKE-make} -f conftest.make 2>/dev/null` in + *@@@%%%=?*=@@@%%%*) + eval ac_cv_prog_make_${ac_make}_set=yes;; + *) + eval ac_cv_prog_make_${ac_make}_set=no;; +esac +rm -f conftest.make +fi +if eval test \$ac_cv_prog_make_${ac_make}_set = yes; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + SET_MAKE= +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } + SET_MAKE="MAKE=${MAKE-make}" +fi + +rm -rf .tst 2>/dev/null +mkdir .tst 2>/dev/null +if test -d .tst; then + am__leading_dot=. +else + am__leading_dot=_ +fi +rmdir .tst 2>/dev/null + +# Check whether --enable-silent-rules was given. +if test "${enable_silent_rules+set}" = set; then : + enableval=$enable_silent_rules; +fi + +case $enable_silent_rules in # ((( + yes) AM_DEFAULT_VERBOSITY=0;; + no) AM_DEFAULT_VERBOSITY=1;; + *) AM_DEFAULT_VERBOSITY=1;; +esac +am_make=${MAKE-make} +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $am_make supports nested variables" >&5 +$as_echo_n "checking whether $am_make supports nested variables... " >&6; } +if ${am_cv_make_support_nested_variables+:} false; then : + $as_echo_n "(cached) " >&6 +else + if $as_echo 'TRUE=$(BAR$(V)) +BAR0=false +BAR1=true +V=1 +am__doit: + @$(TRUE) +.PHONY: am__doit' | $am_make -f - >/dev/null 2>&1; then + am_cv_make_support_nested_variables=yes +else + am_cv_make_support_nested_variables=no +fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_make_support_nested_variables" >&5 +$as_echo "$am_cv_make_support_nested_variables" >&6; } +if test $am_cv_make_support_nested_variables = yes; then + AM_V='$(V)' + AM_DEFAULT_V='$(AM_DEFAULT_VERBOSITY)' +else + AM_V=$AM_DEFAULT_VERBOSITY + AM_DEFAULT_V=$AM_DEFAULT_VERBOSITY +fi +AM_BACKSLASH='\' + +if test "`cd $srcdir && pwd`" != "`pwd`"; then + # Use -I$(srcdir) only when $(srcdir) != ., so that make's output + # is not polluted with repeated "-I." + am__isrc=' -I$(srcdir)' + # test to see if srcdir already configured + if test -f $srcdir/config.status; then + as_fn_error $? "source directory already configured; run \"make distclean\" there first" "$LINENO" 5 + fi +fi + +# test whether we have cygpath +if test -z "$CYGPATH_W"; then + if (cygpath --version) >/dev/null 2>/dev/null; then + CYGPATH_W='cygpath -w' + else + CYGPATH_W=echo + fi +fi + + +# Define the identity of the package. + PACKAGE='wolfssl' + VERSION='3.6.0' + + +# Some tools Automake needs. + +ACLOCAL=${ACLOCAL-"${am_missing_run}aclocal-${am__api_version}"} + + +AUTOCONF=${AUTOCONF-"${am_missing_run}autoconf"} + + +AUTOMAKE=${AUTOMAKE-"${am_missing_run}automake-${am__api_version}"} + + +AUTOHEADER=${AUTOHEADER-"${am_missing_run}autoheader"} + + +MAKEINFO=${MAKEINFO-"${am_missing_run}makeinfo"} + +# For better backward compatibility. To be removed once Automake 1.9.x +# dies out for good. For more background, see: +# +# +mkdir_p='$(MKDIR_P)' + +# We need awk for the "check" target. The system "awk" is bad on +# some platforms. +# Always define AMTAR for backward compatibility. Yes, it's still used +# in the wild :-( We should find a proper way to deprecate it ... +AMTAR='$${TAR-tar}' + + +# We'll loop over all known methods to create a tar archive until one works. +_am_tools='gnutar plaintar pax cpio none' + +# The POSIX 1988 'ustar' format is defined with fixed-size fields. + # There is notably a 21 bits limit for the UID and the GID. In fact, + # the 'pax' utility can hang on bigger UID/GID (see automake bug#8343 + # and bug#13588). + am_max_uid=2097151 # 2^21 - 1 + am_max_gid=$am_max_uid + # The $UID and $GID variables are not portable, so we need to resort + # to the POSIX-mandated id(1) utility. Errors in the 'id' calls + # below are definitely unexpected, so allow the users to see them + # (that is, avoid stderr redirection). + am_uid=`id -u || echo unknown` + am_gid=`id -g || echo unknown` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether UID '$am_uid' is supported by ustar format" >&5 +$as_echo_n "checking whether UID '$am_uid' is supported by ustar format... " >&6; } + if test $am_uid -le $am_max_uid; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } + _am_tools=none + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether GID '$am_gid' is supported by ustar format" >&5 +$as_echo_n "checking whether GID '$am_gid' is supported by ustar format... " >&6; } + if test $am_gid -le $am_max_gid; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } + _am_tools=none + fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking how to create a ustar tar archive" >&5 +$as_echo_n "checking how to create a ustar tar archive... " >&6; } + + # Go ahead even if we have the value already cached. We do so because we + # need to set the values for the 'am__tar' and 'am__untar' variables. + _am_tools=${am_cv_prog_tar_ustar-$_am_tools} + + for _am_tool in $_am_tools; do + case $_am_tool in + gnutar) + for _am_tar in tar gnutar gtar; do + { echo "$as_me:$LINENO: $_am_tar --version" >&5 + ($_am_tar --version) >&5 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && break + done + am__tar="$_am_tar --format=ustar -chf - "'"$$tardir"' + am__tar_="$_am_tar --format=ustar -chf - "'"$tardir"' + am__untar="$_am_tar -xf -" + ;; + plaintar) + # Must skip GNU tar: if it does not support --format= it doesn't create + # ustar tarball either. + (tar --version) >/dev/null 2>&1 && continue + am__tar='tar chf - "$$tardir"' + am__tar_='tar chf - "$tardir"' + am__untar='tar xf -' + ;; + pax) + am__tar='pax -L -x ustar -w "$$tardir"' + am__tar_='pax -L -x ustar -w "$tardir"' + am__untar='pax -r' + ;; + cpio) + am__tar='find "$$tardir" -print | cpio -o -H ustar -L' + am__tar_='find "$tardir" -print | cpio -o -H ustar -L' + am__untar='cpio -i -H ustar -d' + ;; + none) + am__tar=false + am__tar_=false + am__untar=false + ;; + esac + + # If the value was cached, stop now. We just wanted to have am__tar + # and am__untar set. + test -n "${am_cv_prog_tar_ustar}" && break + + # tar/untar a dummy directory, and stop if the command works. + rm -rf conftest.dir + mkdir conftest.dir + echo GrepMe > conftest.dir/file + { echo "$as_me:$LINENO: tardir=conftest.dir && eval $am__tar_ >conftest.tar" >&5 + (tardir=conftest.dir && eval $am__tar_ >conftest.tar) >&5 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } + rm -rf conftest.dir + if test -s conftest.tar; then + { echo "$as_me:$LINENO: $am__untar &5 + ($am__untar &5 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } + { echo "$as_me:$LINENO: cat conftest.dir/file" >&5 + (cat conftest.dir/file) >&5 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } + grep GrepMe conftest.dir/file >/dev/null 2>&1 && break + fi + done + rm -rf conftest.dir + + if ${am_cv_prog_tar_ustar+:} false; then : + $as_echo_n "(cached) " >&6 +else + am_cv_prog_tar_ustar=$_am_tool +fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_prog_tar_ustar" >&5 +$as_echo "$am_cv_prog_tar_ustar" >&6; } + + + + + + +# POSIX will say in a future version that running "rm -f" with no argument +# is OK; and we want to be able to make that assumption in our Makefile +# recipes. So use an aggressive probe to check that the usage we want is +# actually supported "in the wild" to an acceptable degree. +# See automake bug#10828. +# To make any issue more visible, cause the running configure to be aborted +# by default if the 'rm' program in use doesn't match our expectations; the +# user can still override this though. +if rm -f && rm -fr && rm -rf; then : OK; else + cat >&2 <<'END' +Oops! + +Your 'rm' program seems unable to run without file operands specified +on the command line, even when the '-f' option is present. This is contrary +to the behaviour of most rm programs out there, and not conforming with +the upcoming POSIX standard: + +Please tell bug-automake@gnu.org about your system, including the value +of your $PATH and any error possibly output before this message. This +can help us improve future automake versions. + +END + if test x"$ACCEPT_INFERIOR_RM_PROGRAM" = x"yes"; then + echo 'Configuration will proceed anyway, since you have set the' >&2 + echo 'ACCEPT_INFERIOR_RM_PROGRAM variable to "yes"' >&2 + echo >&2 + else + cat >&2 <<'END' +Aborting the configuration process, to ensure you take notice of the issue. + +You can download and install GNU coreutils to get an 'rm' implementation +that behaves properly: . + +If you want to complete the configuration process using your problematic +'rm' anyway, export the environment variable ACCEPT_INFERIOR_RM_PROGRAM +to "yes", and re-run configure. + +END + as_fn_error $? "Your 'rm' program is bad, sorry." "$LINENO" 5 + fi +fi + + + + +#PROTECT_AC_USE_SYSTEM_EXTENSIONS + + + +ac_config_headers="$ac_config_headers config.h:config.in" + +#shared library versioning +WOLFSSL_LIBRARY_VERSION=0:2:0 +# | | | +# +------+ | +---+ +# | | | +# current:revision:age +# | | | +# | | +- increment if interfaces have been added +# | | set to zero if interfaces have been removed +# | | or changed +# | +- increment if source code has changed +# | set to zero if current is incremented +# +- increment if interfaces have been added, removed or changed + + +# capture user C_EXTRA_FLAGS from ./configure line, CFLAGS may hold -g -O2 even +# if user doesn't override, no way to tell +USER_C_EXTRA_FLAGS="$C_EXTRA_FLAGS" + + +case `pwd` in + *\ * | *\ *) + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: Libtool does not cope well with whitespace in \`pwd\`" >&5 +$as_echo "$as_me: WARNING: Libtool does not cope well with whitespace in \`pwd\`" >&2;} ;; +esac + + + +macro_version='2.4.2' +macro_revision='1.3337' + + + + + + + + + + + + + +ltmain="$ac_aux_dir/ltmain.sh" + +# Backslashify metacharacters that are still active within +# double-quoted strings. +sed_quote_subst='s/\(["`$\\]\)/\\\1/g' + +# Same as above, but do not quote variable references. +double_quote_subst='s/\(["`\\]\)/\\\1/g' + +# Sed substitution to delay expansion of an escaped shell variable in a +# double_quote_subst'ed string. +delay_variable_subst='s/\\\\\\\\\\\$/\\\\\\$/g' + +# Sed substitution to delay expansion of an escaped single quote. +delay_single_quote_subst='s/'\''/'\'\\\\\\\'\''/g' + +# Sed substitution to avoid accidental globbing in evaled expressions +no_glob_subst='s/\*/\\\*/g' + +ECHO='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +ECHO=$ECHO$ECHO$ECHO$ECHO$ECHO +ECHO=$ECHO$ECHO$ECHO$ECHO$ECHO$ECHO + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to print strings" >&5 +$as_echo_n "checking how to print strings... " >&6; } +# Test print first, because it will be a builtin if present. +if test "X`( print -r -- -n ) 2>/dev/null`" = X-n && \ + test "X`print -r -- $ECHO 2>/dev/null`" = "X$ECHO"; then + ECHO='print -r --' +elif test "X`printf %s $ECHO 2>/dev/null`" = "X$ECHO"; then + ECHO='printf %s\n' +else + # Use this function as a fallback that always works. + func_fallback_echo () + { + eval 'cat <<_LTECHO_EOF +$1 +_LTECHO_EOF' + } + ECHO='func_fallback_echo' +fi + +# func_echo_all arg... +# Invoke $ECHO with all args, space-separated. +func_echo_all () +{ + $ECHO "" +} + +case "$ECHO" in + printf*) { $as_echo "$as_me:${as_lineno-$LINENO}: result: printf" >&5 +$as_echo "printf" >&6; } ;; + print*) { $as_echo "$as_me:${as_lineno-$LINENO}: result: print -r" >&5 +$as_echo "print -r" >&6; } ;; + *) { $as_echo "$as_me:${as_lineno-$LINENO}: result: cat" >&5 +$as_echo "cat" >&6; } ;; +esac + + + + + + + + + + + + + + +DEPDIR="${am__leading_dot}deps" + +ac_config_commands="$ac_config_commands depfiles" + + +am_make=${MAKE-make} +cat > confinc << 'END' +am__doit: + @echo this is the am__doit target +.PHONY: am__doit +END +# If we don't find an include directive, just comment out the code. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for style of include used by $am_make" >&5 +$as_echo_n "checking for style of include used by $am_make... " >&6; } +am__include="#" +am__quote= +_am_result=none +# First try GNU make style include. +echo "include confinc" > confmf +# Ignore all kinds of additional output from 'make'. +case `$am_make -s -f confmf 2> /dev/null` in #( +*the\ am__doit\ target*) + am__include=include + am__quote= + _am_result=GNU + ;; +esac +# Now try BSD make style include. +if test "$am__include" = "#"; then + echo '.include "confinc"' > confmf + case `$am_make -s -f confmf 2> /dev/null` in #( + *the\ am__doit\ target*) + am__include=.include + am__quote="\"" + _am_result=BSD + ;; + esac +fi + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $_am_result" >&5 +$as_echo "$_am_result" >&6; } +rm -f confinc confmf + +# Check whether --enable-dependency-tracking was given. +if test "${enable_dependency_tracking+set}" = set; then : + enableval=$enable_dependency_tracking; +fi + +if test "x$enable_dependency_tracking" != xno; then + am_depcomp="$ac_aux_dir/depcomp" + AMDEPBACKSLASH='\' + am__nodep='_no' +fi + if test "x$enable_dependency_tracking" != xno; then + AMDEP_TRUE= + AMDEP_FALSE='#' +else + AMDEP_TRUE='#' + AMDEP_FALSE= +fi + + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args. +set dummy ${ac_tool_prefix}gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_CC="${ac_tool_prefix}gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_CC"; then + ac_ct_CC=$CC + # Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_CC="gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +else + CC="$ac_cv_prog_CC" +fi + +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args. +set dummy ${ac_tool_prefix}cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_CC="${ac_tool_prefix}cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + fi +fi +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + ac_prog_rejected=no +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# != 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" + fi +fi +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + for ac_prog in cl.exe + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_CC="$ac_tool_prefix$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$CC" && break + done +fi +if test -z "$CC"; then + ac_ct_CC=$CC + for ac_prog in cl.exe +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_CC="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$ac_ct_CC" && break +done + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +fi + +fi + + +test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error $? "no acceptable C compiler found in \$PATH +See \`config.log' for more details" "$LINENO" 5; } + +# Provide some information about the compiler. +$as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5 +set X $ac_compile +ac_compiler=$2 +for ac_option in --version -v -V -qversion; do + { { ac_try="$ac_compiler $ac_option >&5" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compiler $ac_option >&5") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + sed '10a\ +... rest of stderr output deleted ... + 10q' conftest.err >conftest.er1 + cat conftest.er1 >&5 + fi + rm -f conftest.er1 conftest.err + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } +done + +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +ac_clean_files_save=$ac_clean_files +ac_clean_files="$ac_clean_files a.out a.out.dSYM a.exe b.out" +# Try to create an executable without -o first, disregard a.out. +# It will help us diagnose broken compilers, and finding out an intuition +# of exeext. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the C compiler works" >&5 +$as_echo_n "checking whether the C compiler works... " >&6; } +ac_link_default=`$as_echo "$ac_link" | sed 's/ -o *conftest[^ ]*//'` + +# The possible output files: +ac_files="a.out conftest.exe conftest a.exe a_out.exe b.out conftest.*" + +ac_rmfiles= +for ac_file in $ac_files +do + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; + * ) ac_rmfiles="$ac_rmfiles $ac_file";; + esac +done +rm -f $ac_rmfiles + +if { { ac_try="$ac_link_default" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link_default") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + # Autoconf-2.13 could set the ac_cv_exeext variable to `no'. +# So ignore a value of `no', otherwise this would lead to `EXEEXT = no' +# in a Makefile. We should not override ac_cv_exeext if it was cached, +# so that the user can short-circuit this test for compilers unknown to +# Autoconf. +for ac_file in $ac_files '' +do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) + ;; + [ab].out ) + # We found the default executable, but exeext='' is most + # certainly right. + break;; + *.* ) + if test "${ac_cv_exeext+set}" = set && test "$ac_cv_exeext" != no; + then :; else + ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + fi + # We set ac_cv_exeext here because the later test for it is not + # safe: cross compilers may not add the suffix if given an `-o' + # argument, so we may need to know it at that point already. + # Even if this section looks crufty: it has the advantage of + # actually working. + break;; + * ) + break;; + esac +done +test "$ac_cv_exeext" = no && ac_cv_exeext= + +else + ac_file='' +fi +if test -z "$ac_file"; then : + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +$as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error 77 "C compiler cannot create executables +See \`config.log' for more details" "$LINENO" 5; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler default output file name" >&5 +$as_echo_n "checking for C compiler default output file name... " >&6; } +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_file" >&5 +$as_echo "$ac_file" >&6; } +ac_exeext=$ac_cv_exeext + +rm -f -r a.out a.out.dSYM a.exe conftest$ac_cv_exeext b.out +ac_clean_files=$ac_clean_files_save +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of executables" >&5 +$as_echo_n "checking for suffix of executables... " >&6; } +if { { ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + # If both `conftest.exe' and `conftest' are `present' (well, observable) +# catch `conftest.exe'. For instance with Cygwin, `ls conftest' will +# work properly (i.e., refer to `conftest.exe'), while it won't with +# `rm'. +for ac_file in conftest.exe conftest conftest.*; do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; + *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + break;; + * ) break;; + esac +done +else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error $? "cannot compute suffix of executables: cannot compile and link +See \`config.log' for more details" "$LINENO" 5; } +fi +rm -f conftest conftest$ac_cv_exeext +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_exeext" >&5 +$as_echo "$ac_cv_exeext" >&6; } + +rm -f conftest.$ac_ext +EXEEXT=$ac_cv_exeext +ac_exeext=$EXEEXT +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +int +main () +{ +FILE *f = fopen ("conftest.out", "w"); + return ferror (f) || fclose (f) != 0; + + ; + return 0; +} +_ACEOF +ac_clean_files="$ac_clean_files conftest.out" +# Check that the compiler produces executables we can run. If not, either +# the compiler is broken, or we cross compile. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are cross compiling" >&5 +$as_echo_n "checking whether we are cross compiling... " >&6; } +if test "$cross_compiling" != yes; then + { { ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + if { ac_try='./conftest$ac_cv_exeext' + { { case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; }; then + cross_compiling=no + else + if test "$cross_compiling" = maybe; then + cross_compiling=yes + else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error $? "cannot run C compiled programs. +If you meant to cross compile, use \`--host'. +See \`config.log' for more details" "$LINENO" 5; } + fi + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $cross_compiling" >&5 +$as_echo "$cross_compiling" >&6; } + +rm -f conftest.$ac_ext conftest$ac_cv_exeext conftest.out +ac_clean_files=$ac_clean_files_save +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of object files" >&5 +$as_echo_n "checking for suffix of object files... " >&6; } +if ${ac_cv_objext+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +rm -f conftest.o conftest.obj +if { { ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compile") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + for ac_file in conftest.o conftest.obj conftest.*; do + test -f "$ac_file" || continue; + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM ) ;; + *) ac_cv_objext=`expr "$ac_file" : '.*\.\(.*\)'` + break;; + esac +done +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error $? "cannot compute suffix of object files: cannot compile +See \`config.log' for more details" "$LINENO" 5; } +fi +rm -f conftest.$ac_cv_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_objext" >&5 +$as_echo "$ac_cv_objext" >&6; } +OBJEXT=$ac_cv_objext +ac_objext=$OBJEXT +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C compiler" >&5 +$as_echo_n "checking whether we are using the GNU C compiler... " >&6; } +if ${ac_cv_c_compiler_gnu+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +#ifndef __GNUC__ + choke me +#endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_compiler_gnu=yes +else + ac_compiler_gnu=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +ac_cv_c_compiler_gnu=$ac_compiler_gnu + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_compiler_gnu" >&5 +$as_echo "$ac_cv_c_compiler_gnu" >&6; } +if test $ac_compiler_gnu = yes; then + GCC=yes +else + GCC= +fi +ac_test_CFLAGS=${CFLAGS+set} +ac_save_CFLAGS=$CFLAGS +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5 +$as_echo_n "checking whether $CC accepts -g... " >&6; } +if ${ac_cv_prog_cc_g+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_save_c_werror_flag=$ac_c_werror_flag + ac_c_werror_flag=yes + ac_cv_prog_cc_g=no + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +else + CFLAGS="" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + +else + ac_c_werror_flag=$ac_save_c_werror_flag + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_c_werror_flag=$ac_save_c_werror_flag +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_g" >&5 +$as_echo "$ac_cv_prog_cc_g" >&6; } +if test "$ac_test_CFLAGS" = set; then + CFLAGS=$ac_save_CFLAGS +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $CC option to accept ISO C89" >&5 +$as_echo_n "checking for $CC option to accept ISO C89... " >&6; } +if ${ac_cv_prog_cc_c89+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_cv_prog_cc_c89=no +ac_save_CC=$CC +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +struct stat; +/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ +struct buf { int x; }; +FILE * (*rcsopen) (struct buf *, struct stat *, int); +static char *e (p, i) + char **p; + int i; +{ + return p[i]; +} +static char *f (char * (*g) (char **, int), char **p, ...) +{ + char *s; + va_list v; + va_start (v,p); + s = g (p, va_arg (v,int)); + va_end (v); + return s; +} + +/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has + function prototypes and stuff, but not '\xHH' hex character constants. + These don't provoke an error unfortunately, instead are silently treated + as 'x'. The following induces an error, until -std is added to get + proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an + array size at least. It's necessary to write '\x00'==0 to get something + that's true only with -std. */ +int osf4_cc_array ['\x00' == 0 ? 1 : -1]; + +/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters + inside strings and character constants. */ +#define FOO(x) 'x' +int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1]; + +int test (int i, double x); +struct s1 {int (*f) (int a);}; +struct s2 {int (*f) (double a);}; +int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int); +int argc; +char **argv; +int +main () +{ +return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1]; + ; + return 0; +} +_ACEOF +for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \ + -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__" +do + CC="$ac_save_CC $ac_arg" + if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_c89=$ac_arg +fi +rm -f core conftest.err conftest.$ac_objext + test "x$ac_cv_prog_cc_c89" != "xno" && break +done +rm -f conftest.$ac_ext +CC=$ac_save_CC + +fi +# AC_CACHE_VAL +case "x$ac_cv_prog_cc_c89" in + x) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: none needed" >&5 +$as_echo "none needed" >&6; } ;; + xno) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5 +$as_echo "unsupported" >&6; } ;; + *) + CC="$CC $ac_cv_prog_cc_c89" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c89" >&5 +$as_echo "$ac_cv_prog_cc_c89" >&6; } ;; +esac +if test "x$ac_cv_prog_cc_c89" != xno; then : + +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC understands -c and -o together" >&5 +$as_echo_n "checking whether $CC understands -c and -o together... " >&6; } +if ${am_cv_prog_cc_c_o+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF + # Make sure it works both with $CC and with simple cc. + # Following AC_PROG_CC_C_O, we do the test twice because some + # compilers refuse to overwrite an existing .o file with -o, + # though they will create one. + am_cv_prog_cc_c_o=yes + for am_i in 1 2; do + if { echo "$as_me:$LINENO: $CC -c conftest.$ac_ext -o conftest2.$ac_objext" >&5 + ($CC -c conftest.$ac_ext -o conftest2.$ac_objext) >&5 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } \ + && test -f conftest2.$ac_objext; then + : OK + else + am_cv_prog_cc_c_o=no + break + fi + done + rm -f core conftest* + unset am_i +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_prog_cc_c_o" >&5 +$as_echo "$am_cv_prog_cc_c_o" >&6; } +if test "$am_cv_prog_cc_c_o" != yes; then + # Losing compiler, so override with the script. + # FIXME: It is wrong to rewrite CC. + # But if we don't then we get into trouble of one sort or another. + # A longer-term fix would be to have automake use am__CC in this case, + # and then we could set am__CC="\$(top_srcdir)/compile \$(CC)" + CC="$am_aux_dir/compile $CC" +fi +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + +depcc="$CC" am_compiler_list= + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking dependency style of $depcc" >&5 +$as_echo_n "checking dependency style of $depcc... " >&6; } +if ${am_cv_CC_dependencies_compiler_type+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -z "$AMDEP_TRUE" && test -f "$am_depcomp"; then + # We make a subdir and do the tests there. Otherwise we can end up + # making bogus files that we don't know about and never remove. For + # instance it was reported that on HP-UX the gcc test will end up + # making a dummy file named 'D' -- because '-MD' means "put the output + # in D". + rm -rf conftest.dir + mkdir conftest.dir + # Copy depcomp to subdir because otherwise we won't find it if we're + # using a relative directory. + cp "$am_depcomp" conftest.dir + cd conftest.dir + # We will build objects and dependencies in a subdirectory because + # it helps to detect inapplicable dependency modes. For instance + # both Tru64's cc and ICC support -MD to output dependencies as a + # side effect of compilation, but ICC will put the dependencies in + # the current directory while Tru64 will put them in the object + # directory. + mkdir sub + + am_cv_CC_dependencies_compiler_type=none + if test "$am_compiler_list" = ""; then + am_compiler_list=`sed -n 's/^#*\([a-zA-Z0-9]*\))$/\1/p' < ./depcomp` + fi + am__universal=false + case " $depcc " in #( + *\ -arch\ *\ -arch\ *) am__universal=true ;; + esac + + for depmode in $am_compiler_list; do + # Setup a source with many dependencies, because some compilers + # like to wrap large dependency lists on column 80 (with \), and + # we should not choose a depcomp mode which is confused by this. + # + # We need to recreate these files for each test, as the compiler may + # overwrite some of them when testing with obscure command lines. + # This happens at least with the AIX C compiler. + : > sub/conftest.c + for i in 1 2 3 4 5 6; do + echo '#include "conftst'$i'.h"' >> sub/conftest.c + # Using ": > sub/conftst$i.h" creates only sub/conftst1.h with + # Solaris 10 /bin/sh. + echo '/* dummy */' > sub/conftst$i.h + done + echo "${am__include} ${am__quote}sub/conftest.Po${am__quote}" > confmf + + # We check with '-c' and '-o' for the sake of the "dashmstdout" + # mode. It turns out that the SunPro C++ compiler does not properly + # handle '-M -o', and we need to detect this. Also, some Intel + # versions had trouble with output in subdirs. + am__obj=sub/conftest.${OBJEXT-o} + am__minus_obj="-o $am__obj" + case $depmode in + gcc) + # This depmode causes a compiler race in universal mode. + test "$am__universal" = false || continue + ;; + nosideeffect) + # After this tag, mechanisms are not by side-effect, so they'll + # only be used when explicitly requested. + if test "x$enable_dependency_tracking" = xyes; then + continue + else + break + fi + ;; + msvc7 | msvc7msys | msvisualcpp | msvcmsys) + # This compiler won't grok '-c -o', but also, the minuso test has + # not run yet. These depmodes are late enough in the game, and + # so weak that their functioning should not be impacted. + am__obj=conftest.${OBJEXT-o} + am__minus_obj= + ;; + none) break ;; + esac + if depmode=$depmode \ + source=sub/conftest.c object=$am__obj \ + depfile=sub/conftest.Po tmpdepfile=sub/conftest.TPo \ + $SHELL ./depcomp $depcc -c $am__minus_obj sub/conftest.c \ + >/dev/null 2>conftest.err && + grep sub/conftst1.h sub/conftest.Po > /dev/null 2>&1 && + grep sub/conftst6.h sub/conftest.Po > /dev/null 2>&1 && + grep $am__obj sub/conftest.Po > /dev/null 2>&1 && + ${MAKE-make} -s -f confmf > /dev/null 2>&1; then + # icc doesn't choke on unknown options, it will just issue warnings + # or remarks (even with -Werror). So we grep stderr for any message + # that says an option was ignored or not supported. + # When given -MP, icc 7.0 and 7.1 complain thusly: + # icc: Command line warning: ignoring option '-M'; no argument required + # The diagnosis changed in icc 8.0: + # icc: Command line remark: option '-MP' not supported + if (grep 'ignoring option' conftest.err || + grep 'not supported' conftest.err) >/dev/null 2>&1; then :; else + am_cv_CC_dependencies_compiler_type=$depmode + break + fi + fi + done + + cd .. + rm -rf conftest.dir +else + am_cv_CC_dependencies_compiler_type=none +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_CC_dependencies_compiler_type" >&5 +$as_echo "$am_cv_CC_dependencies_compiler_type" >&6; } +CCDEPMODE=depmode=$am_cv_CC_dependencies_compiler_type + + if + test "x$enable_dependency_tracking" != xno \ + && test "$am_cv_CC_dependencies_compiler_type" = gcc3; then + am__fastdepCC_TRUE= + am__fastdepCC_FALSE='#' +else + am__fastdepCC_TRUE='#' + am__fastdepCC_FALSE= +fi + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a sed that does not truncate output" >&5 +$as_echo_n "checking for a sed that does not truncate output... " >&6; } +if ${ac_cv_path_SED+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_script=s/aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa/bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb/ + for ac_i in 1 2 3 4 5 6 7; do + ac_script="$ac_script$as_nl$ac_script" + done + echo "$ac_script" 2>/dev/null | sed 99q >conftest.sed + { ac_script=; unset ac_script;} + if test -z "$SED"; then + ac_path_SED_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in sed gsed; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_SED="$as_dir/$ac_prog$ac_exec_ext" + as_fn_executable_p "$ac_path_SED" || continue +# Check for GNU ac_path_SED and select it if it is found. + # Check for GNU $ac_path_SED +case `"$ac_path_SED" --version 2>&1` in +*GNU*) + ac_cv_path_SED="$ac_path_SED" ac_path_SED_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo '' >> "conftest.nl" + "$ac_path_SED" -f conftest.sed < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_SED_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_SED="$ac_path_SED" + ac_path_SED_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_SED_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_SED"; then + as_fn_error $? "no acceptable sed could be found in \$PATH" "$LINENO" 5 + fi +else + ac_cv_path_SED=$SED +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_SED" >&5 +$as_echo "$ac_cv_path_SED" >&6; } + SED="$ac_cv_path_SED" + rm -f conftest.sed + +test -z "$SED" && SED=sed +Xsed="$SED -e 1s/^X//" + + + + + + + + + + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for grep that handles long lines and -e" >&5 +$as_echo_n "checking for grep that handles long lines and -e... " >&6; } +if ${ac_cv_path_GREP+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -z "$GREP"; then + ac_path_GREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in grep ggrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_GREP="$as_dir/$ac_prog$ac_exec_ext" + as_fn_executable_p "$ac_path_GREP" || continue +# Check for GNU ac_path_GREP and select it if it is found. + # Check for GNU $ac_path_GREP +case `"$ac_path_GREP" --version 2>&1` in +*GNU*) + ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'GREP' >> "conftest.nl" + "$ac_path_GREP" -e 'GREP$' -e '-(cannot match)-' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_GREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_GREP="$ac_path_GREP" + ac_path_GREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_GREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_GREP"; then + as_fn_error $? "no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_GREP=$GREP +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_GREP" >&5 +$as_echo "$ac_cv_path_GREP" >&6; } + GREP="$ac_cv_path_GREP" + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for egrep" >&5 +$as_echo_n "checking for egrep... " >&6; } +if ${ac_cv_path_EGREP+:} false; then : + $as_echo_n "(cached) " >&6 +else + if echo a | $GREP -E '(a|b)' >/dev/null 2>&1 + then ac_cv_path_EGREP="$GREP -E" + else + if test -z "$EGREP"; then + ac_path_EGREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in egrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_EGREP="$as_dir/$ac_prog$ac_exec_ext" + as_fn_executable_p "$ac_path_EGREP" || continue +# Check for GNU ac_path_EGREP and select it if it is found. + # Check for GNU $ac_path_EGREP +case `"$ac_path_EGREP" --version 2>&1` in +*GNU*) + ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'EGREP' >> "conftest.nl" + "$ac_path_EGREP" 'EGREP$' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_EGREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_EGREP="$ac_path_EGREP" + ac_path_EGREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_EGREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_EGREP"; then + as_fn_error $? "no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_EGREP=$EGREP +fi + + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_EGREP" >&5 +$as_echo "$ac_cv_path_EGREP" >&6; } + EGREP="$ac_cv_path_EGREP" + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for fgrep" >&5 +$as_echo_n "checking for fgrep... " >&6; } +if ${ac_cv_path_FGREP+:} false; then : + $as_echo_n "(cached) " >&6 +else + if echo 'ab*c' | $GREP -F 'ab*c' >/dev/null 2>&1 + then ac_cv_path_FGREP="$GREP -F" + else + if test -z "$FGREP"; then + ac_path_FGREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in fgrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_FGREP="$as_dir/$ac_prog$ac_exec_ext" + as_fn_executable_p "$ac_path_FGREP" || continue +# Check for GNU ac_path_FGREP and select it if it is found. + # Check for GNU $ac_path_FGREP +case `"$ac_path_FGREP" --version 2>&1` in +*GNU*) + ac_cv_path_FGREP="$ac_path_FGREP" ac_path_FGREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'FGREP' >> "conftest.nl" + "$ac_path_FGREP" FGREP < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_FGREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_FGREP="$ac_path_FGREP" + ac_path_FGREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_FGREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_FGREP"; then + as_fn_error $? "no acceptable fgrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_FGREP=$FGREP +fi + + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_FGREP" >&5 +$as_echo "$ac_cv_path_FGREP" >&6; } + FGREP="$ac_cv_path_FGREP" + + +test -z "$GREP" && GREP=grep + + + + + + + + + + + + + + + + + + + +# Check whether --with-gnu-ld was given. +if test "${with_gnu_ld+set}" = set; then : + withval=$with_gnu_ld; test "$withval" = no || with_gnu_ld=yes +else + with_gnu_ld=no +fi + +ac_prog=ld +if test "$GCC" = yes; then + # Check if gcc -print-prog-name=ld gives a path. + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for ld used by $CC" >&5 +$as_echo_n "checking for ld used by $CC... " >&6; } + case $host in + *-*-mingw*) + # gcc leaves a trailing carriage return which upsets mingw + ac_prog=`($CC -print-prog-name=ld) 2>&5 | tr -d '\015'` ;; + *) + ac_prog=`($CC -print-prog-name=ld) 2>&5` ;; + esac + case $ac_prog in + # Accept absolute paths. + [\\/]* | ?:[\\/]*) + re_direlt='/[^/][^/]*/\.\./' + # Canonicalize the pathname of ld + ac_prog=`$ECHO "$ac_prog"| $SED 's%\\\\%/%g'` + while $ECHO "$ac_prog" | $GREP "$re_direlt" > /dev/null 2>&1; do + ac_prog=`$ECHO $ac_prog| $SED "s%$re_direlt%/%"` + done + test -z "$LD" && LD="$ac_prog" + ;; + "") + # If it fails, then pretend we aren't using GCC. + ac_prog=ld + ;; + *) + # If it is relative, then search for the first ld in PATH. + with_gnu_ld=unknown + ;; + esac +elif test "$with_gnu_ld" = yes; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for GNU ld" >&5 +$as_echo_n "checking for GNU ld... " >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for non-GNU ld" >&5 +$as_echo_n "checking for non-GNU ld... " >&6; } +fi +if ${lt_cv_path_LD+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -z "$LD"; then + lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR + for ac_dir in $PATH; do + IFS="$lt_save_ifs" + test -z "$ac_dir" && ac_dir=. + if test -f "$ac_dir/$ac_prog" || test -f "$ac_dir/$ac_prog$ac_exeext"; then + lt_cv_path_LD="$ac_dir/$ac_prog" + # Check to see if the program is GNU ld. I'd rather use --version, + # but apparently some variants of GNU ld only accept -v. + # Break only if it was the GNU/non-GNU ld that we prefer. + case `"$lt_cv_path_LD" -v 2>&1 &5 +$as_echo "$LD" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi +test -z "$LD" && as_fn_error $? "no acceptable ld found in \$PATH" "$LINENO" 5 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if the linker ($LD) is GNU ld" >&5 +$as_echo_n "checking if the linker ($LD) is GNU ld... " >&6; } +if ${lt_cv_prog_gnu_ld+:} false; then : + $as_echo_n "(cached) " >&6 +else + # I'd rather use --version here, but apparently some GNU lds only accept -v. +case `$LD -v 2>&1 &5 +$as_echo "$lt_cv_prog_gnu_ld" >&6; } +with_gnu_ld=$lt_cv_prog_gnu_ld + + + + + + + + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for BSD- or MS-compatible name lister (nm)" >&5 +$as_echo_n "checking for BSD- or MS-compatible name lister (nm)... " >&6; } +if ${lt_cv_path_NM+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$NM"; then + # Let the user override the test. + lt_cv_path_NM="$NM" +else + lt_nm_to_check="${ac_tool_prefix}nm" + if test -n "$ac_tool_prefix" && test "$build" = "$host"; then + lt_nm_to_check="$lt_nm_to_check nm" + fi + for lt_tmp_nm in $lt_nm_to_check; do + lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR + for ac_dir in $PATH /usr/ccs/bin/elf /usr/ccs/bin /usr/ucb /bin; do + IFS="$lt_save_ifs" + test -z "$ac_dir" && ac_dir=. + tmp_nm="$ac_dir/$lt_tmp_nm" + if test -f "$tmp_nm" || test -f "$tmp_nm$ac_exeext" ; then + # Check to see if the nm accepts a BSD-compat flag. + # Adding the `sed 1q' prevents false positives on HP-UX, which says: + # nm: unknown option "B" ignored + # Tru64's nm complains that /dev/null is an invalid object file + case `"$tmp_nm" -B /dev/null 2>&1 | sed '1q'` in + */dev/null* | *'Invalid file or object type'*) + lt_cv_path_NM="$tmp_nm -B" + break + ;; + *) + case `"$tmp_nm" -p /dev/null 2>&1 | sed '1q'` in + */dev/null*) + lt_cv_path_NM="$tmp_nm -p" + break + ;; + *) + lt_cv_path_NM=${lt_cv_path_NM="$tmp_nm"} # keep the first match, but + continue # so that we can try to find one that supports BSD flags + ;; + esac + ;; + esac + fi + done + IFS="$lt_save_ifs" + done + : ${lt_cv_path_NM=no} +fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_path_NM" >&5 +$as_echo "$lt_cv_path_NM" >&6; } +if test "$lt_cv_path_NM" != "no"; then + NM="$lt_cv_path_NM" +else + # Didn't find any BSD compatible name lister, look for dumpbin. + if test -n "$DUMPBIN"; then : + # Let the user override the test. + else + if test -n "$ac_tool_prefix"; then + for ac_prog in dumpbin "link -dump" + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_DUMPBIN+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$DUMPBIN"; then + ac_cv_prog_DUMPBIN="$DUMPBIN" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_DUMPBIN="$ac_tool_prefix$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +DUMPBIN=$ac_cv_prog_DUMPBIN +if test -n "$DUMPBIN"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $DUMPBIN" >&5 +$as_echo "$DUMPBIN" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$DUMPBIN" && break + done +fi +if test -z "$DUMPBIN"; then + ac_ct_DUMPBIN=$DUMPBIN + for ac_prog in dumpbin "link -dump" +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_DUMPBIN+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_DUMPBIN"; then + ac_cv_prog_ac_ct_DUMPBIN="$ac_ct_DUMPBIN" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_DUMPBIN="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_DUMPBIN=$ac_cv_prog_ac_ct_DUMPBIN +if test -n "$ac_ct_DUMPBIN"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_DUMPBIN" >&5 +$as_echo "$ac_ct_DUMPBIN" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$ac_ct_DUMPBIN" && break +done + + if test "x$ac_ct_DUMPBIN" = x; then + DUMPBIN=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + DUMPBIN=$ac_ct_DUMPBIN + fi +fi + + case `$DUMPBIN -symbols /dev/null 2>&1 | sed '1q'` in + *COFF*) + DUMPBIN="$DUMPBIN -symbols" + ;; + *) + DUMPBIN=: + ;; + esac + fi + + if test "$DUMPBIN" != ":"; then + NM="$DUMPBIN" + fi +fi +test -z "$NM" && NM=nm + + + + + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking the name lister ($NM) interface" >&5 +$as_echo_n "checking the name lister ($NM) interface... " >&6; } +if ${lt_cv_nm_interface+:} false; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_nm_interface="BSD nm" + echo "int some_variable = 0;" > conftest.$ac_ext + (eval echo "\"\$as_me:$LINENO: $ac_compile\"" >&5) + (eval "$ac_compile" 2>conftest.err) + cat conftest.err >&5 + (eval echo "\"\$as_me:$LINENO: $NM \\\"conftest.$ac_objext\\\"\"" >&5) + (eval "$NM \"conftest.$ac_objext\"" 2>conftest.err > conftest.out) + cat conftest.err >&5 + (eval echo "\"\$as_me:$LINENO: output\"" >&5) + cat conftest.out >&5 + if $GREP 'External.*some_variable' conftest.out > /dev/null; then + lt_cv_nm_interface="MS dumpbin" + fi + rm -f conftest* +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_nm_interface" >&5 +$as_echo "$lt_cv_nm_interface" >&6; } + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ln -s works" >&5 +$as_echo_n "checking whether ln -s works... " >&6; } +LN_S=$as_ln_s +if test "$LN_S" = "ln -s"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no, using $LN_S" >&5 +$as_echo "no, using $LN_S" >&6; } +fi + +# find the maximum length of command line arguments +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking the maximum length of command line arguments" >&5 +$as_echo_n "checking the maximum length of command line arguments... " >&6; } +if ${lt_cv_sys_max_cmd_len+:} false; then : + $as_echo_n "(cached) " >&6 +else + i=0 + teststring="ABCD" + + case $build_os in + msdosdjgpp*) + # On DJGPP, this test can blow up pretty badly due to problems in libc + # (any single argument exceeding 2000 bytes causes a buffer overrun + # during glob expansion). Even if it were fixed, the result of this + # check would be larger than it should be. + lt_cv_sys_max_cmd_len=12288; # 12K is about right + ;; + + gnu*) + # Under GNU Hurd, this test is not required because there is + # no limit to the length of command line arguments. + # Libtool will interpret -1 as no limit whatsoever + lt_cv_sys_max_cmd_len=-1; + ;; + + cygwin* | mingw* | cegcc*) + # On Win9x/ME, this test blows up -- it succeeds, but takes + # about 5 minutes as the teststring grows exponentially. + # Worse, since 9x/ME are not pre-emptively multitasking, + # you end up with a "frozen" computer, even though with patience + # the test eventually succeeds (with a max line length of 256k). + # Instead, let's just punt: use the minimum linelength reported by + # all of the supported platforms: 8192 (on NT/2K/XP). + lt_cv_sys_max_cmd_len=8192; + ;; + + mint*) + # On MiNT this can take a long time and run out of memory. + lt_cv_sys_max_cmd_len=8192; + ;; + + amigaos*) + # On AmigaOS with pdksh, this test takes hours, literally. + # So we just punt and use a minimum line length of 8192. + lt_cv_sys_max_cmd_len=8192; + ;; + + netbsd* | freebsd* | openbsd* | darwin* | dragonfly*) + # This has been around since 386BSD, at least. Likely further. + if test -x /sbin/sysctl; then + lt_cv_sys_max_cmd_len=`/sbin/sysctl -n kern.argmax` + elif test -x /usr/sbin/sysctl; then + lt_cv_sys_max_cmd_len=`/usr/sbin/sysctl -n kern.argmax` + else + lt_cv_sys_max_cmd_len=65536 # usable default for all BSDs + fi + # And add a safety zone + lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 4` + lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \* 3` + ;; + + interix*) + # We know the value 262144 and hardcode it with a safety zone (like BSD) + lt_cv_sys_max_cmd_len=196608 + ;; + + os2*) + # The test takes a long time on OS/2. + lt_cv_sys_max_cmd_len=8192 + ;; + + osf*) + # Dr. Hans Ekkehard Plesser reports seeing a kernel panic running configure + # due to this test when exec_disable_arg_limit is 1 on Tru64. It is not + # nice to cause kernel panics so lets avoid the loop below. + # First set a reasonable default. + lt_cv_sys_max_cmd_len=16384 + # + if test -x /sbin/sysconfig; then + case `/sbin/sysconfig -q proc exec_disable_arg_limit` in + *1*) lt_cv_sys_max_cmd_len=-1 ;; + esac + fi + ;; + sco3.2v5*) + lt_cv_sys_max_cmd_len=102400 + ;; + sysv5* | sco5v6* | sysv4.2uw2*) + kargmax=`grep ARG_MAX /etc/conf/cf.d/stune 2>/dev/null` + if test -n "$kargmax"; then + lt_cv_sys_max_cmd_len=`echo $kargmax | sed 's/.*[ ]//'` + else + lt_cv_sys_max_cmd_len=32768 + fi + ;; + *) + lt_cv_sys_max_cmd_len=`(getconf ARG_MAX) 2> /dev/null` + if test -n "$lt_cv_sys_max_cmd_len"; then + lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 4` + lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \* 3` + else + # Make teststring a little bigger before we do anything with it. + # a 1K string should be a reasonable start. + for i in 1 2 3 4 5 6 7 8 ; do + teststring=$teststring$teststring + done + SHELL=${SHELL-${CONFIG_SHELL-/bin/sh}} + # If test is not a shell built-in, we'll probably end up computing a + # maximum length that is only half of the actual maximum length, but + # we can't tell. + while { test "X"`env echo "$teststring$teststring" 2>/dev/null` \ + = "X$teststring$teststring"; } >/dev/null 2>&1 && + test $i != 17 # 1/2 MB should be enough + do + i=`expr $i + 1` + teststring=$teststring$teststring + done + # Only check the string length outside the loop. + lt_cv_sys_max_cmd_len=`expr "X$teststring" : ".*" 2>&1` + teststring= + # Add a significant safety factor because C++ compilers can tack on + # massive amounts of additional arguments before passing them to the + # linker. It appears as though 1/2 is a usable value. + lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 2` + fi + ;; + esac + +fi + +if test -n $lt_cv_sys_max_cmd_len ; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_sys_max_cmd_len" >&5 +$as_echo "$lt_cv_sys_max_cmd_len" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: none" >&5 +$as_echo "none" >&6; } +fi +max_cmd_len=$lt_cv_sys_max_cmd_len + + + + + + +: ${CP="cp -f"} +: ${MV="mv -f"} +: ${RM="rm -f"} + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the shell understands some XSI constructs" >&5 +$as_echo_n "checking whether the shell understands some XSI constructs... " >&6; } +# Try some XSI features +xsi_shell=no +( _lt_dummy="a/b/c" + test "${_lt_dummy##*/},${_lt_dummy%/*},${_lt_dummy#??}"${_lt_dummy%"$_lt_dummy"}, \ + = c,a/b,b/c, \ + && eval 'test $(( 1 + 1 )) -eq 2 \ + && test "${#_lt_dummy}" -eq 5' ) >/dev/null 2>&1 \ + && xsi_shell=yes +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $xsi_shell" >&5 +$as_echo "$xsi_shell" >&6; } + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the shell understands \"+=\"" >&5 +$as_echo_n "checking whether the shell understands \"+=\"... " >&6; } +lt_shell_append=no +( foo=bar; set foo baz; eval "$1+=\$2" && test "$foo" = barbaz ) \ + >/dev/null 2>&1 \ + && lt_shell_append=yes +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_shell_append" >&5 +$as_echo "$lt_shell_append" >&6; } + + +if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then + lt_unset=unset +else + lt_unset=false +fi + + + + + +# test EBCDIC or ASCII +case `echo X|tr X '\101'` in + A) # ASCII based system + # \n is not interpreted correctly by Solaris 8 /usr/ucb/tr + lt_SP2NL='tr \040 \012' + lt_NL2SP='tr \015\012 \040\040' + ;; + *) # EBCDIC based system + lt_SP2NL='tr \100 \n' + lt_NL2SP='tr \r\n \100\100' + ;; +esac + + + + + + + + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to convert $build file names to $host format" >&5 +$as_echo_n "checking how to convert $build file names to $host format... " >&6; } +if ${lt_cv_to_host_file_cmd+:} false; then : + $as_echo_n "(cached) " >&6 +else + case $host in + *-*-mingw* ) + case $build in + *-*-mingw* ) # actually msys + lt_cv_to_host_file_cmd=func_convert_file_msys_to_w32 + ;; + *-*-cygwin* ) + lt_cv_to_host_file_cmd=func_convert_file_cygwin_to_w32 + ;; + * ) # otherwise, assume *nix + lt_cv_to_host_file_cmd=func_convert_file_nix_to_w32 + ;; + esac + ;; + *-*-cygwin* ) + case $build in + *-*-mingw* ) # actually msys + lt_cv_to_host_file_cmd=func_convert_file_msys_to_cygwin + ;; + *-*-cygwin* ) + lt_cv_to_host_file_cmd=func_convert_file_noop + ;; + * ) # otherwise, assume *nix + lt_cv_to_host_file_cmd=func_convert_file_nix_to_cygwin + ;; + esac + ;; + * ) # unhandled hosts (and "normal" native builds) + lt_cv_to_host_file_cmd=func_convert_file_noop + ;; +esac + +fi + +to_host_file_cmd=$lt_cv_to_host_file_cmd +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_to_host_file_cmd" >&5 +$as_echo "$lt_cv_to_host_file_cmd" >&6; } + + + + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to convert $build file names to toolchain format" >&5 +$as_echo_n "checking how to convert $build file names to toolchain format... " >&6; } +if ${lt_cv_to_tool_file_cmd+:} false; then : + $as_echo_n "(cached) " >&6 +else + #assume ordinary cross tools, or native build. +lt_cv_to_tool_file_cmd=func_convert_file_noop +case $host in + *-*-mingw* ) + case $build in + *-*-mingw* ) # actually msys + lt_cv_to_tool_file_cmd=func_convert_file_msys_to_w32 + ;; + esac + ;; +esac + +fi + +to_tool_file_cmd=$lt_cv_to_tool_file_cmd +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_to_tool_file_cmd" >&5 +$as_echo "$lt_cv_to_tool_file_cmd" >&6; } + + + + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $LD option to reload object files" >&5 +$as_echo_n "checking for $LD option to reload object files... " >&6; } +if ${lt_cv_ld_reload_flag+:} false; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_ld_reload_flag='-r' +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_ld_reload_flag" >&5 +$as_echo "$lt_cv_ld_reload_flag" >&6; } +reload_flag=$lt_cv_ld_reload_flag +case $reload_flag in +"" | " "*) ;; +*) reload_flag=" $reload_flag" ;; +esac +reload_cmds='$LD$reload_flag -o $output$reload_objs' +case $host_os in + cygwin* | mingw* | pw32* | cegcc*) + if test "$GCC" != yes; then + reload_cmds=false + fi + ;; + darwin*) + if test "$GCC" = yes; then + reload_cmds='$LTCC $LTCFLAGS -nostdlib ${wl}-r -o $output$reload_objs' + else + reload_cmds='$LD$reload_flag -o $output$reload_objs' + fi + ;; +esac + + + + + + + + + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}objdump", so it can be a program name with args. +set dummy ${ac_tool_prefix}objdump; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_OBJDUMP+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$OBJDUMP"; then + ac_cv_prog_OBJDUMP="$OBJDUMP" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_OBJDUMP="${ac_tool_prefix}objdump" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +OBJDUMP=$ac_cv_prog_OBJDUMP +if test -n "$OBJDUMP"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $OBJDUMP" >&5 +$as_echo "$OBJDUMP" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_OBJDUMP"; then + ac_ct_OBJDUMP=$OBJDUMP + # Extract the first word of "objdump", so it can be a program name with args. +set dummy objdump; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_OBJDUMP+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_OBJDUMP"; then + ac_cv_prog_ac_ct_OBJDUMP="$ac_ct_OBJDUMP" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_OBJDUMP="objdump" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_OBJDUMP=$ac_cv_prog_ac_ct_OBJDUMP +if test -n "$ac_ct_OBJDUMP"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_OBJDUMP" >&5 +$as_echo "$ac_ct_OBJDUMP" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_OBJDUMP" = x; then + OBJDUMP="false" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + OBJDUMP=$ac_ct_OBJDUMP + fi +else + OBJDUMP="$ac_cv_prog_OBJDUMP" +fi + +test -z "$OBJDUMP" && OBJDUMP=objdump + + + + + + + + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to recognize dependent libraries" >&5 +$as_echo_n "checking how to recognize dependent libraries... " >&6; } +if ${lt_cv_deplibs_check_method+:} false; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_file_magic_cmd='$MAGIC_CMD' +lt_cv_file_magic_test_file= +lt_cv_deplibs_check_method='unknown' +# Need to set the preceding variable on all platforms that support +# interlibrary dependencies. +# 'none' -- dependencies not supported. +# `unknown' -- same as none, but documents that we really don't know. +# 'pass_all' -- all dependencies passed with no checks. +# 'test_compile' -- check by making test program. +# 'file_magic [[regex]]' -- check by looking for files in library path +# which responds to the $file_magic_cmd with a given extended regex. +# If you have `file' or equivalent on your system and you're not sure +# whether `pass_all' will *always* work, you probably want this one. + +case $host_os in +aix[4-9]*) + lt_cv_deplibs_check_method=pass_all + ;; + +beos*) + lt_cv_deplibs_check_method=pass_all + ;; + +bsdi[45]*) + lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib)' + lt_cv_file_magic_cmd='/usr/bin/file -L' + lt_cv_file_magic_test_file=/shlib/libc.so + ;; + +cygwin*) + # func_win32_libid is a shell function defined in ltmain.sh + lt_cv_deplibs_check_method='file_magic ^x86 archive import|^x86 DLL' + lt_cv_file_magic_cmd='func_win32_libid' + ;; + +mingw* | pw32*) + # Base MSYS/MinGW do not provide the 'file' command needed by + # func_win32_libid shell function, so use a weaker test based on 'objdump', + # unless we find 'file', for example because we are cross-compiling. + # func_win32_libid assumes BSD nm, so disallow it if using MS dumpbin. + if ( test "$lt_cv_nm_interface" = "BSD nm" && file / ) >/dev/null 2>&1; then + lt_cv_deplibs_check_method='file_magic ^x86 archive import|^x86 DLL' + lt_cv_file_magic_cmd='func_win32_libid' + else + # Keep this pattern in sync with the one in func_win32_libid. + lt_cv_deplibs_check_method='file_magic file format (pei*-i386(.*architecture: i386)?|pe-arm-wince|pe-x86-64)' + lt_cv_file_magic_cmd='$OBJDUMP -f' + fi + ;; + +cegcc*) + # use the weaker test based on 'objdump'. See mingw*. + lt_cv_deplibs_check_method='file_magic file format pe-arm-.*little(.*architecture: arm)?' + lt_cv_file_magic_cmd='$OBJDUMP -f' + ;; + +darwin* | rhapsody*) + lt_cv_deplibs_check_method=pass_all + ;; + +freebsd* | dragonfly*) + if echo __ELF__ | $CC -E - | $GREP __ELF__ > /dev/null; then + case $host_cpu in + i*86 ) + # Not sure whether the presence of OpenBSD here was a mistake. + # Let's accept both of them until this is cleared up. + lt_cv_deplibs_check_method='file_magic (FreeBSD|OpenBSD|DragonFly)/i[3-9]86 (compact )?demand paged shared library' + lt_cv_file_magic_cmd=/usr/bin/file + lt_cv_file_magic_test_file=`echo /usr/lib/libc.so.*` + ;; + esac + else + lt_cv_deplibs_check_method=pass_all + fi + ;; + +gnu*) + lt_cv_deplibs_check_method=pass_all + ;; + +haiku*) + lt_cv_deplibs_check_method=pass_all + ;; + +hpux10.20* | hpux11*) + lt_cv_file_magic_cmd=/usr/bin/file + case $host_cpu in + ia64*) + lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0-9]) shared object file - IA64' + lt_cv_file_magic_test_file=/usr/lib/hpux32/libc.so + ;; + hppa*64*) + lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|ELF[ -][0-9][0-9])(-bit)?( [LM]SB)? shared object( file)?[, -]* PA-RISC [0-9]\.[0-9]' + lt_cv_file_magic_test_file=/usr/lib/pa20_64/libc.sl + ;; + *) + lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|PA-RISC[0-9]\.[0-9]) shared library' + lt_cv_file_magic_test_file=/usr/lib/libc.sl + ;; + esac + ;; + +interix[3-9]*) + # PIC code is broken on Interix 3.x, that's why |\.a not |_pic\.a here + lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so|\.a)$' + ;; + +irix5* | irix6* | nonstopux*) + case $LD in + *-32|*"-32 ") libmagic=32-bit;; + *-n32|*"-n32 ") libmagic=N32;; + *-64|*"-64 ") libmagic=64-bit;; + *) libmagic=never-match;; + esac + lt_cv_deplibs_check_method=pass_all + ;; + +# This must be glibc/ELF. +linux* | k*bsd*-gnu | kopensolaris*-gnu) + lt_cv_deplibs_check_method=pass_all + ;; + +netbsd*) + if echo __ELF__ | $CC -E - | $GREP __ELF__ > /dev/null; then + lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|_pic\.a)$' + else + lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so|_pic\.a)$' + fi + ;; + +newos6*) + lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (executable|dynamic lib)' + lt_cv_file_magic_cmd=/usr/bin/file + lt_cv_file_magic_test_file=/usr/lib/libnls.so + ;; + +*nto* | *qnx*) + lt_cv_deplibs_check_method=pass_all + ;; + +openbsd*) + if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then + lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|\.so|_pic\.a)$' + else + lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|_pic\.a)$' + fi + ;; + +osf3* | osf4* | osf5*) + lt_cv_deplibs_check_method=pass_all + ;; + +rdos*) + lt_cv_deplibs_check_method=pass_all + ;; + +solaris*) + lt_cv_deplibs_check_method=pass_all + ;; + +sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX* | sysv4*uw2*) + lt_cv_deplibs_check_method=pass_all + ;; + +sysv4 | sysv4.3*) + case $host_vendor in + motorola) + lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib) M[0-9][0-9]* Version [0-9]' + lt_cv_file_magic_test_file=`echo /usr/lib/libc.so*` + ;; + ncr) + lt_cv_deplibs_check_method=pass_all + ;; + sequent) + lt_cv_file_magic_cmd='/bin/file' + lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [LM]SB (shared object|dynamic lib )' + ;; + sni) + lt_cv_file_magic_cmd='/bin/file' + lt_cv_deplibs_check_method="file_magic ELF [0-9][0-9]*-bit [LM]SB dynamic lib" + lt_cv_file_magic_test_file=/lib/libc.so + ;; + siemens) + lt_cv_deplibs_check_method=pass_all + ;; + pc) + lt_cv_deplibs_check_method=pass_all + ;; + esac + ;; + +tpf*) + lt_cv_deplibs_check_method=pass_all + ;; +esac + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_deplibs_check_method" >&5 +$as_echo "$lt_cv_deplibs_check_method" >&6; } + +file_magic_glob= +want_nocaseglob=no +if test "$build" = "$host"; then + case $host_os in + mingw* | pw32*) + if ( shopt | grep nocaseglob ) >/dev/null 2>&1; then + want_nocaseglob=yes + else + file_magic_glob=`echo aAbBcCdDeEfFgGhHiIjJkKlLmMnNoOpPqQrRsStTuUvVwWxXyYzZ | $SED -e "s/\(..\)/s\/[\1]\/[\1]\/g;/g"` + fi + ;; + esac +fi + +file_magic_cmd=$lt_cv_file_magic_cmd +deplibs_check_method=$lt_cv_deplibs_check_method +test -z "$deplibs_check_method" && deplibs_check_method=unknown + + + + + + + + + + + + + + + + + + + + + + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}dlltool", so it can be a program name with args. +set dummy ${ac_tool_prefix}dlltool; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_DLLTOOL+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$DLLTOOL"; then + ac_cv_prog_DLLTOOL="$DLLTOOL" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_DLLTOOL="${ac_tool_prefix}dlltool" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +DLLTOOL=$ac_cv_prog_DLLTOOL +if test -n "$DLLTOOL"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $DLLTOOL" >&5 +$as_echo "$DLLTOOL" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_DLLTOOL"; then + ac_ct_DLLTOOL=$DLLTOOL + # Extract the first word of "dlltool", so it can be a program name with args. +set dummy dlltool; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_DLLTOOL+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_DLLTOOL"; then + ac_cv_prog_ac_ct_DLLTOOL="$ac_ct_DLLTOOL" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_DLLTOOL="dlltool" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_DLLTOOL=$ac_cv_prog_ac_ct_DLLTOOL +if test -n "$ac_ct_DLLTOOL"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_DLLTOOL" >&5 +$as_echo "$ac_ct_DLLTOOL" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_DLLTOOL" = x; then + DLLTOOL="false" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + DLLTOOL=$ac_ct_DLLTOOL + fi +else + DLLTOOL="$ac_cv_prog_DLLTOOL" +fi + +test -z "$DLLTOOL" && DLLTOOL=dlltool + + + + + + + + + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to associate runtime and link libraries" >&5 +$as_echo_n "checking how to associate runtime and link libraries... " >&6; } +if ${lt_cv_sharedlib_from_linklib_cmd+:} false; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_sharedlib_from_linklib_cmd='unknown' + +case $host_os in +cygwin* | mingw* | pw32* | cegcc*) + # two different shell functions defined in ltmain.sh + # decide which to use based on capabilities of $DLLTOOL + case `$DLLTOOL --help 2>&1` in + *--identify-strict*) + lt_cv_sharedlib_from_linklib_cmd=func_cygming_dll_for_implib + ;; + *) + lt_cv_sharedlib_from_linklib_cmd=func_cygming_dll_for_implib_fallback + ;; + esac + ;; +*) + # fallback: assume linklib IS sharedlib + lt_cv_sharedlib_from_linklib_cmd="$ECHO" + ;; +esac + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_sharedlib_from_linklib_cmd" >&5 +$as_echo "$lt_cv_sharedlib_from_linklib_cmd" >&6; } +sharedlib_from_linklib_cmd=$lt_cv_sharedlib_from_linklib_cmd +test -z "$sharedlib_from_linklib_cmd" && sharedlib_from_linklib_cmd=$ECHO + + + + + + + + +if test -n "$ac_tool_prefix"; then + for ac_prog in ar + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_AR+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$AR"; then + ac_cv_prog_AR="$AR" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_AR="$ac_tool_prefix$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +AR=$ac_cv_prog_AR +if test -n "$AR"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AR" >&5 +$as_echo "$AR" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$AR" && break + done +fi +if test -z "$AR"; then + ac_ct_AR=$AR + for ac_prog in ar +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_AR+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_AR"; then + ac_cv_prog_ac_ct_AR="$ac_ct_AR" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_AR="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_AR=$ac_cv_prog_ac_ct_AR +if test -n "$ac_ct_AR"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_AR" >&5 +$as_echo "$ac_ct_AR" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$ac_ct_AR" && break +done + + if test "x$ac_ct_AR" = x; then + AR="false" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + AR=$ac_ct_AR + fi +fi + +: ${AR=ar} +: ${AR_FLAGS=cru} + + + + + + + + + + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for archiver @FILE support" >&5 +$as_echo_n "checking for archiver @FILE support... " >&6; } +if ${lt_cv_ar_at_file+:} false; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_ar_at_file=no + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + echo conftest.$ac_objext > conftest.lst + lt_ar_try='$AR $AR_FLAGS libconftest.a @conftest.lst >&5' + { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$lt_ar_try\""; } >&5 + (eval $lt_ar_try) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + if test "$ac_status" -eq 0; then + # Ensure the archiver fails upon bogus file names. + rm -f conftest.$ac_objext libconftest.a + { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$lt_ar_try\""; } >&5 + (eval $lt_ar_try) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + if test "$ac_status" -ne 0; then + lt_cv_ar_at_file=@ + fi + fi + rm -f conftest.* libconftest.a + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_ar_at_file" >&5 +$as_echo "$lt_cv_ar_at_file" >&6; } + +if test "x$lt_cv_ar_at_file" = xno; then + archiver_list_spec= +else + archiver_list_spec=$lt_cv_ar_at_file +fi + + + + + + + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args. +set dummy ${ac_tool_prefix}strip; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_STRIP+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$STRIP"; then + ac_cv_prog_STRIP="$STRIP" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_STRIP="${ac_tool_prefix}strip" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +STRIP=$ac_cv_prog_STRIP +if test -n "$STRIP"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $STRIP" >&5 +$as_echo "$STRIP" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_STRIP"; then + ac_ct_STRIP=$STRIP + # Extract the first word of "strip", so it can be a program name with args. +set dummy strip; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_STRIP+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_STRIP"; then + ac_cv_prog_ac_ct_STRIP="$ac_ct_STRIP" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_STRIP="strip" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_STRIP=$ac_cv_prog_ac_ct_STRIP +if test -n "$ac_ct_STRIP"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_STRIP" >&5 +$as_echo "$ac_ct_STRIP" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_STRIP" = x; then + STRIP=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + STRIP=$ac_ct_STRIP + fi +else + STRIP="$ac_cv_prog_STRIP" +fi + +test -z "$STRIP" && STRIP=: + + + + + + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. +set dummy ${ac_tool_prefix}ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_RANLIB+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +RANLIB=$ac_cv_prog_RANLIB +if test -n "$RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $RANLIB" >&5 +$as_echo "$RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_RANLIB"; then + ac_ct_RANLIB=$RANLIB + # Extract the first word of "ranlib", so it can be a program name with args. +set dummy ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_RANLIB+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_RANLIB"; then + ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_RANLIB="ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB +if test -n "$ac_ct_RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_RANLIB" >&5 +$as_echo "$ac_ct_RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_RANLIB" = x; then + RANLIB=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + RANLIB=$ac_ct_RANLIB + fi +else + RANLIB="$ac_cv_prog_RANLIB" +fi + +test -z "$RANLIB" && RANLIB=: + + + + + + +# Determine commands to create old-style static archives. +old_archive_cmds='$AR $AR_FLAGS $oldlib$oldobjs' +old_postinstall_cmds='chmod 644 $oldlib' +old_postuninstall_cmds= + +if test -n "$RANLIB"; then + case $host_os in + openbsd*) + old_postinstall_cmds="$old_postinstall_cmds~\$RANLIB -t \$tool_oldlib" + ;; + *) + old_postinstall_cmds="$old_postinstall_cmds~\$RANLIB \$tool_oldlib" + ;; + esac + old_archive_cmds="$old_archive_cmds~\$RANLIB \$tool_oldlib" +fi + +case $host_os in + darwin*) + lock_old_archive_extraction=yes ;; + *) + lock_old_archive_extraction=no ;; +esac + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# If no C compiler was specified, use CC. +LTCC=${LTCC-"$CC"} + +# If no C compiler flags were specified, use CFLAGS. +LTCFLAGS=${LTCFLAGS-"$CFLAGS"} + +# Allow CC to be a program name with arguments. +compiler=$CC + + +# Check for command to grab the raw symbol name followed by C symbol from nm. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking command to parse $NM output from $compiler object" >&5 +$as_echo_n "checking command to parse $NM output from $compiler object... " >&6; } +if ${lt_cv_sys_global_symbol_pipe+:} false; then : + $as_echo_n "(cached) " >&6 +else + +# These are sane defaults that work on at least a few old systems. +# [They come from Ultrix. What could be older than Ultrix?!! ;)] + +# Character class describing NM global symbol codes. +symcode='[BCDEGRST]' + +# Regexp to match symbols that can be accessed directly from C. +sympat='\([_A-Za-z][_A-Za-z0-9]*\)' + +# Define system-specific variables. +case $host_os in +aix*) + symcode='[BCDT]' + ;; +cygwin* | mingw* | pw32* | cegcc*) + symcode='[ABCDGISTW]' + ;; +hpux*) + if test "$host_cpu" = ia64; then + symcode='[ABCDEGRST]' + fi + ;; +irix* | nonstopux*) + symcode='[BCDEGRST]' + ;; +osf*) + symcode='[BCDEGQRST]' + ;; +solaris*) + symcode='[BDRT]' + ;; +sco3.2v5*) + symcode='[DT]' + ;; +sysv4.2uw2*) + symcode='[DT]' + ;; +sysv5* | sco5v6* | unixware* | OpenUNIX*) + symcode='[ABDT]' + ;; +sysv4) + symcode='[DFNSTU]' + ;; +esac + +# If we're using GNU nm, then use its standard symbol codes. +case `$NM -V 2>&1` in +*GNU* | *'with BFD'*) + symcode='[ABCDGIRSTW]' ;; +esac + +# Transform an extracted symbol line into a proper C declaration. +# Some systems (esp. on ia64) link data and code symbols differently, +# so use this general approach. +lt_cv_sys_global_symbol_to_cdecl="sed -n -e 's/^T .* \(.*\)$/extern int \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'" + +# Transform an extracted symbol line into symbol name and symbol address +lt_cv_sys_global_symbol_to_c_name_address="sed -n -e 's/^: \([^ ]*\)[ ]*$/ {\\\"\1\\\", (void *) 0},/p' -e 's/^$symcode* \([^ ]*\) \([^ ]*\)$/ {\"\2\", (void *) \&\2},/p'" +lt_cv_sys_global_symbol_to_c_name_address_lib_prefix="sed -n -e 's/^: \([^ ]*\)[ ]*$/ {\\\"\1\\\", (void *) 0},/p' -e 's/^$symcode* \([^ ]*\) \(lib[^ ]*\)$/ {\"\2\", (void *) \&\2},/p' -e 's/^$symcode* \([^ ]*\) \([^ ]*\)$/ {\"lib\2\", (void *) \&\2},/p'" + +# Handle CRLF in mingw tool chain +opt_cr= +case $build_os in +mingw*) + opt_cr=`$ECHO 'x\{0,1\}' | tr x '\015'` # option cr in regexp + ;; +esac + +# Try without a prefix underscore, then with it. +for ac_symprfx in "" "_"; do + + # Transform symcode, sympat, and symprfx into a raw symbol and a C symbol. + symxfrm="\\1 $ac_symprfx\\2 \\2" + + # Write the raw and C identifiers. + if test "$lt_cv_nm_interface" = "MS dumpbin"; then + # Fake it for dumpbin and say T for any non-static function + # and D for any global variable. + # Also find C++ and __fastcall symbols from MSVC++, + # which start with @ or ?. + lt_cv_sys_global_symbol_pipe="$AWK '"\ +" {last_section=section; section=\$ 3};"\ +" /^COFF SYMBOL TABLE/{for(i in hide) delete hide[i]};"\ +" /Section length .*#relocs.*(pick any)/{hide[last_section]=1};"\ +" \$ 0!~/External *\|/{next};"\ +" / 0+ UNDEF /{next}; / UNDEF \([^|]\)*()/{next};"\ +" {if(hide[section]) next};"\ +" {f=0}; \$ 0~/\(\).*\|/{f=1}; {printf f ? \"T \" : \"D \"};"\ +" {split(\$ 0, a, /\||\r/); split(a[2], s)};"\ +" s[1]~/^[@?]/{print s[1], s[1]; next};"\ +" s[1]~prfx {split(s[1],t,\"@\"); print t[1], substr(t[1],length(prfx))}"\ +" ' prfx=^$ac_symprfx" + else + lt_cv_sys_global_symbol_pipe="sed -n -e 's/^.*[ ]\($symcode$symcode*\)[ ][ ]*$ac_symprfx$sympat$opt_cr$/$symxfrm/p'" + fi + lt_cv_sys_global_symbol_pipe="$lt_cv_sys_global_symbol_pipe | sed '/ __gnu_lto/d'" + + # Check to see that the pipe works correctly. + pipe_works=no + + rm -f conftest* + cat > conftest.$ac_ext <<_LT_EOF +#ifdef __cplusplus +extern "C" { +#endif +char nm_test_var; +void nm_test_func(void); +void nm_test_func(void){} +#ifdef __cplusplus +} +#endif +int main(){nm_test_var='a';nm_test_func();return(0);} +_LT_EOF + + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 + (eval $ac_compile) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then + # Now try to grab the symbols. + nlist=conftest.nm + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$NM conftest.$ac_objext \| "$lt_cv_sys_global_symbol_pipe" \> $nlist\""; } >&5 + (eval $NM conftest.$ac_objext \| "$lt_cv_sys_global_symbol_pipe" \> $nlist) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } && test -s "$nlist"; then + # Try sorting and uniquifying the output. + if sort "$nlist" | uniq > "$nlist"T; then + mv -f "$nlist"T "$nlist" + else + rm -f "$nlist"T + fi + + # Make sure that we snagged all the symbols we need. + if $GREP ' nm_test_var$' "$nlist" >/dev/null; then + if $GREP ' nm_test_func$' "$nlist" >/dev/null; then + cat <<_LT_EOF > conftest.$ac_ext +/* Keep this code in sync between libtool.m4, ltmain, lt_system.h, and tests. */ +#if defined(_WIN32) || defined(__CYGWIN__) || defined(_WIN32_WCE) +/* DATA imports from DLLs on WIN32 con't be const, because runtime + relocations are performed -- see ld's documentation on pseudo-relocs. */ +# define LT_DLSYM_CONST +#elif defined(__osf__) +/* This system does not cope well with relocations in const data. */ +# define LT_DLSYM_CONST +#else +# define LT_DLSYM_CONST const +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +_LT_EOF + # Now generate the symbol file. + eval "$lt_cv_sys_global_symbol_to_cdecl"' < "$nlist" | $GREP -v main >> conftest.$ac_ext' + + cat <<_LT_EOF >> conftest.$ac_ext + +/* The mapping between symbol names and symbols. */ +LT_DLSYM_CONST struct { + const char *name; + void *address; +} +lt__PROGRAM__LTX_preloaded_symbols[] = +{ + { "@PROGRAM@", (void *) 0 }, +_LT_EOF + $SED "s/^$symcode$symcode* \(.*\) \(.*\)$/ {\"\2\", (void *) \&\2},/" < "$nlist" | $GREP -v main >> conftest.$ac_ext + cat <<\_LT_EOF >> conftest.$ac_ext + {0, (void *) 0} +}; + +/* This works around a problem in FreeBSD linker */ +#ifdef FREEBSD_WORKAROUND +static const void *lt_preloaded_setup() { + return lt__PROGRAM__LTX_preloaded_symbols; +} +#endif + +#ifdef __cplusplus +} +#endif +_LT_EOF + # Now try linking the two files. + mv conftest.$ac_objext conftstm.$ac_objext + lt_globsym_save_LIBS=$LIBS + lt_globsym_save_CFLAGS=$CFLAGS + LIBS="conftstm.$ac_objext" + CFLAGS="$CFLAGS$lt_prog_compiler_no_builtin_flag" + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_link\""; } >&5 + (eval $ac_link) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } && test -s conftest${ac_exeext}; then + pipe_works=yes + fi + LIBS=$lt_globsym_save_LIBS + CFLAGS=$lt_globsym_save_CFLAGS + else + echo "cannot find nm_test_func in $nlist" >&5 + fi + else + echo "cannot find nm_test_var in $nlist" >&5 + fi + else + echo "cannot run $lt_cv_sys_global_symbol_pipe" >&5 + fi + else + echo "$progname: failed program was:" >&5 + cat conftest.$ac_ext >&5 + fi + rm -rf conftest* conftst* + + # Do not use the global_symbol_pipe unless it works. + if test "$pipe_works" = yes; then + break + else + lt_cv_sys_global_symbol_pipe= + fi +done + +fi + +if test -z "$lt_cv_sys_global_symbol_pipe"; then + lt_cv_sys_global_symbol_to_cdecl= +fi +if test -z "$lt_cv_sys_global_symbol_pipe$lt_cv_sys_global_symbol_to_cdecl"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: failed" >&5 +$as_echo "failed" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok" >&5 +$as_echo "ok" >&6; } +fi + +# Response file support. +if test "$lt_cv_nm_interface" = "MS dumpbin"; then + nm_file_list_spec='@' +elif $NM --help 2>/dev/null | grep '[@]FILE' >/dev/null; then + nm_file_list_spec='@' +fi + + + + + + + + + + + + + + + + + + + + + + + + + + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for sysroot" >&5 +$as_echo_n "checking for sysroot... " >&6; } + +# Check whether --with-sysroot was given. +if test "${with_sysroot+set}" = set; then : + withval=$with_sysroot; +else + with_sysroot=no +fi + + +lt_sysroot= +case ${with_sysroot} in #( + yes) + if test "$GCC" = yes; then + lt_sysroot=`$CC --print-sysroot 2>/dev/null` + fi + ;; #( + /*) + lt_sysroot=`echo "$with_sysroot" | sed -e "$sed_quote_subst"` + ;; #( + no|'') + ;; #( + *) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: ${with_sysroot}" >&5 +$as_echo "${with_sysroot}" >&6; } + as_fn_error $? "The sysroot must be an absolute path." "$LINENO" 5 + ;; +esac + + { $as_echo "$as_me:${as_lineno-$LINENO}: result: ${lt_sysroot:-no}" >&5 +$as_echo "${lt_sysroot:-no}" >&6; } + + + + + +# Check whether --enable-libtool-lock was given. +if test "${enable_libtool_lock+set}" = set; then : + enableval=$enable_libtool_lock; +fi + +test "x$enable_libtool_lock" != xno && enable_libtool_lock=yes + +# Some flags need to be propagated to the compiler or linker for good +# libtool support. +case $host in +ia64-*-hpux*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 + (eval $ac_compile) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then + case `/usr/bin/file conftest.$ac_objext` in + *ELF-32*) + HPUX_IA64_MODE="32" + ;; + *ELF-64*) + HPUX_IA64_MODE="64" + ;; + esac + fi + rm -rf conftest* + ;; +*-*-irix6*) + # Find out which ABI we are using. + echo '#line '$LINENO' "configure"' > conftest.$ac_ext + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 + (eval $ac_compile) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then + if test "$lt_cv_prog_gnu_ld" = yes; then + case `/usr/bin/file conftest.$ac_objext` in + *32-bit*) + LD="${LD-ld} -melf32bsmip" + ;; + *N32*) + LD="${LD-ld} -melf32bmipn32" + ;; + *64-bit*) + LD="${LD-ld} -melf64bmip" + ;; + esac + else + case `/usr/bin/file conftest.$ac_objext` in + *32-bit*) + LD="${LD-ld} -32" + ;; + *N32*) + LD="${LD-ld} -n32" + ;; + *64-bit*) + LD="${LD-ld} -64" + ;; + esac + fi + fi + rm -rf conftest* + ;; + +x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \ +s390*-*linux*|s390*-*tpf*|sparc*-*linux*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 + (eval $ac_compile) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then + case `/usr/bin/file conftest.o` in + *32-bit*) + case $host in + x86_64-*kfreebsd*-gnu) + LD="${LD-ld} -m elf_i386_fbsd" + ;; + x86_64-*linux*) + LD="${LD-ld} -m elf_i386" + ;; + ppc64-*linux*|powerpc64-*linux*) + LD="${LD-ld} -m elf32ppclinux" + ;; + s390x-*linux*) + LD="${LD-ld} -m elf_s390" + ;; + sparc64-*linux*) + LD="${LD-ld} -m elf32_sparc" + ;; + esac + ;; + *64-bit*) + case $host in + x86_64-*kfreebsd*-gnu) + LD="${LD-ld} -m elf_x86_64_fbsd" + ;; + x86_64-*linux*) + LD="${LD-ld} -m elf_x86_64" + ;; + ppc*-*linux*|powerpc*-*linux*) + LD="${LD-ld} -m elf64ppc" + ;; + s390*-*linux*|s390*-*tpf*) + LD="${LD-ld} -m elf64_s390" + ;; + sparc*-*linux*) + LD="${LD-ld} -m elf64_sparc" + ;; + esac + ;; + esac + fi + rm -rf conftest* + ;; + +*-*-sco3.2v5*) + # On SCO OpenServer 5, we need -belf to get full-featured binaries. + SAVE_CFLAGS="$CFLAGS" + CFLAGS="$CFLAGS -belf" + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the C compiler needs -belf" >&5 +$as_echo_n "checking whether the C compiler needs -belf... " >&6; } +if ${lt_cv_cc_needs_belf+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + lt_cv_cc_needs_belf=yes +else + lt_cv_cc_needs_belf=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_cc_needs_belf" >&5 +$as_echo "$lt_cv_cc_needs_belf" >&6; } + if test x"$lt_cv_cc_needs_belf" != x"yes"; then + # this is probably gcc 2.8.0, egcs 1.0 or newer; no need for -belf + CFLAGS="$SAVE_CFLAGS" + fi + ;; +*-*solaris*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 + (eval $ac_compile) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then + case `/usr/bin/file conftest.o` in + *64-bit*) + case $lt_cv_prog_gnu_ld in + yes*) + case $host in + i?86-*-solaris*) + LD="${LD-ld} -m elf_x86_64" + ;; + sparc*-*-solaris*) + LD="${LD-ld} -m elf64_sparc" + ;; + esac + # GNU ld 2.21 introduced _sol2 emulations. Use them if available. + if ${LD-ld} -V | grep _sol2 >/dev/null 2>&1; then + LD="${LD-ld}_sol2" + fi + ;; + *) + if ${LD-ld} -64 -r -o conftest2.o conftest.o >/dev/null 2>&1; then + LD="${LD-ld} -64" + fi + ;; + esac + ;; + esac + fi + rm -rf conftest* + ;; +esac + +need_locks="$enable_libtool_lock" + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}mt", so it can be a program name with args. +set dummy ${ac_tool_prefix}mt; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_MANIFEST_TOOL+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$MANIFEST_TOOL"; then + ac_cv_prog_MANIFEST_TOOL="$MANIFEST_TOOL" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_MANIFEST_TOOL="${ac_tool_prefix}mt" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +MANIFEST_TOOL=$ac_cv_prog_MANIFEST_TOOL +if test -n "$MANIFEST_TOOL"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $MANIFEST_TOOL" >&5 +$as_echo "$MANIFEST_TOOL" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_MANIFEST_TOOL"; then + ac_ct_MANIFEST_TOOL=$MANIFEST_TOOL + # Extract the first word of "mt", so it can be a program name with args. +set dummy mt; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_MANIFEST_TOOL+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_MANIFEST_TOOL"; then + ac_cv_prog_ac_ct_MANIFEST_TOOL="$ac_ct_MANIFEST_TOOL" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_MANIFEST_TOOL="mt" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_MANIFEST_TOOL=$ac_cv_prog_ac_ct_MANIFEST_TOOL +if test -n "$ac_ct_MANIFEST_TOOL"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_MANIFEST_TOOL" >&5 +$as_echo "$ac_ct_MANIFEST_TOOL" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_MANIFEST_TOOL" = x; then + MANIFEST_TOOL=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + MANIFEST_TOOL=$ac_ct_MANIFEST_TOOL + fi +else + MANIFEST_TOOL="$ac_cv_prog_MANIFEST_TOOL" +fi + +test -z "$MANIFEST_TOOL" && MANIFEST_TOOL=mt +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if $MANIFEST_TOOL is a manifest tool" >&5 +$as_echo_n "checking if $MANIFEST_TOOL is a manifest tool... " >&6; } +if ${lt_cv_path_mainfest_tool+:} false; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_path_mainfest_tool=no + echo "$as_me:$LINENO: $MANIFEST_TOOL '-?'" >&5 + $MANIFEST_TOOL '-?' 2>conftest.err > conftest.out + cat conftest.err >&5 + if $GREP 'Manifest Tool' conftest.out > /dev/null; then + lt_cv_path_mainfest_tool=yes + fi + rm -f conftest* +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_path_mainfest_tool" >&5 +$as_echo "$lt_cv_path_mainfest_tool" >&6; } +if test "x$lt_cv_path_mainfest_tool" != xyes; then + MANIFEST_TOOL=: +fi + + + + + + + case $host_os in + rhapsody* | darwin*) + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}dsymutil", so it can be a program name with args. +set dummy ${ac_tool_prefix}dsymutil; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_DSYMUTIL+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$DSYMUTIL"; then + ac_cv_prog_DSYMUTIL="$DSYMUTIL" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_DSYMUTIL="${ac_tool_prefix}dsymutil" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +DSYMUTIL=$ac_cv_prog_DSYMUTIL +if test -n "$DSYMUTIL"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $DSYMUTIL" >&5 +$as_echo "$DSYMUTIL" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_DSYMUTIL"; then + ac_ct_DSYMUTIL=$DSYMUTIL + # Extract the first word of "dsymutil", so it can be a program name with args. +set dummy dsymutil; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_DSYMUTIL+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_DSYMUTIL"; then + ac_cv_prog_ac_ct_DSYMUTIL="$ac_ct_DSYMUTIL" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_DSYMUTIL="dsymutil" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_DSYMUTIL=$ac_cv_prog_ac_ct_DSYMUTIL +if test -n "$ac_ct_DSYMUTIL"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_DSYMUTIL" >&5 +$as_echo "$ac_ct_DSYMUTIL" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_DSYMUTIL" = x; then + DSYMUTIL=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + DSYMUTIL=$ac_ct_DSYMUTIL + fi +else + DSYMUTIL="$ac_cv_prog_DSYMUTIL" +fi + + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}nmedit", so it can be a program name with args. +set dummy ${ac_tool_prefix}nmedit; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_NMEDIT+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$NMEDIT"; then + ac_cv_prog_NMEDIT="$NMEDIT" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_NMEDIT="${ac_tool_prefix}nmedit" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +NMEDIT=$ac_cv_prog_NMEDIT +if test -n "$NMEDIT"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $NMEDIT" >&5 +$as_echo "$NMEDIT" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_NMEDIT"; then + ac_ct_NMEDIT=$NMEDIT + # Extract the first word of "nmedit", so it can be a program name with args. +set dummy nmedit; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_NMEDIT+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_NMEDIT"; then + ac_cv_prog_ac_ct_NMEDIT="$ac_ct_NMEDIT" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_NMEDIT="nmedit" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_NMEDIT=$ac_cv_prog_ac_ct_NMEDIT +if test -n "$ac_ct_NMEDIT"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_NMEDIT" >&5 +$as_echo "$ac_ct_NMEDIT" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_NMEDIT" = x; then + NMEDIT=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + NMEDIT=$ac_ct_NMEDIT + fi +else + NMEDIT="$ac_cv_prog_NMEDIT" +fi + + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}lipo", so it can be a program name with args. +set dummy ${ac_tool_prefix}lipo; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_LIPO+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$LIPO"; then + ac_cv_prog_LIPO="$LIPO" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_LIPO="${ac_tool_prefix}lipo" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +LIPO=$ac_cv_prog_LIPO +if test -n "$LIPO"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $LIPO" >&5 +$as_echo "$LIPO" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_LIPO"; then + ac_ct_LIPO=$LIPO + # Extract the first word of "lipo", so it can be a program name with args. +set dummy lipo; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_LIPO+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_LIPO"; then + ac_cv_prog_ac_ct_LIPO="$ac_ct_LIPO" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_LIPO="lipo" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_LIPO=$ac_cv_prog_ac_ct_LIPO +if test -n "$ac_ct_LIPO"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_LIPO" >&5 +$as_echo "$ac_ct_LIPO" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_LIPO" = x; then + LIPO=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + LIPO=$ac_ct_LIPO + fi +else + LIPO="$ac_cv_prog_LIPO" +fi + + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}otool", so it can be a program name with args. +set dummy ${ac_tool_prefix}otool; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_OTOOL+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$OTOOL"; then + ac_cv_prog_OTOOL="$OTOOL" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_OTOOL="${ac_tool_prefix}otool" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +OTOOL=$ac_cv_prog_OTOOL +if test -n "$OTOOL"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $OTOOL" >&5 +$as_echo "$OTOOL" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_OTOOL"; then + ac_ct_OTOOL=$OTOOL + # Extract the first word of "otool", so it can be a program name with args. +set dummy otool; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_OTOOL+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_OTOOL"; then + ac_cv_prog_ac_ct_OTOOL="$ac_ct_OTOOL" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_OTOOL="otool" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_OTOOL=$ac_cv_prog_ac_ct_OTOOL +if test -n "$ac_ct_OTOOL"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_OTOOL" >&5 +$as_echo "$ac_ct_OTOOL" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_OTOOL" = x; then + OTOOL=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + OTOOL=$ac_ct_OTOOL + fi +else + OTOOL="$ac_cv_prog_OTOOL" +fi + + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}otool64", so it can be a program name with args. +set dummy ${ac_tool_prefix}otool64; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_OTOOL64+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$OTOOL64"; then + ac_cv_prog_OTOOL64="$OTOOL64" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_OTOOL64="${ac_tool_prefix}otool64" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +OTOOL64=$ac_cv_prog_OTOOL64 +if test -n "$OTOOL64"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $OTOOL64" >&5 +$as_echo "$OTOOL64" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_OTOOL64"; then + ac_ct_OTOOL64=$OTOOL64 + # Extract the first word of "otool64", so it can be a program name with args. +set dummy otool64; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_OTOOL64+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_OTOOL64"; then + ac_cv_prog_ac_ct_OTOOL64="$ac_ct_OTOOL64" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_OTOOL64="otool64" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_OTOOL64=$ac_cv_prog_ac_ct_OTOOL64 +if test -n "$ac_ct_OTOOL64"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_OTOOL64" >&5 +$as_echo "$ac_ct_OTOOL64" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_OTOOL64" = x; then + OTOOL64=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + OTOOL64=$ac_ct_OTOOL64 + fi +else + OTOOL64="$ac_cv_prog_OTOOL64" +fi + + + + + + + + + + + + + + + + + + + + + + + + + + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for -single_module linker flag" >&5 +$as_echo_n "checking for -single_module linker flag... " >&6; } +if ${lt_cv_apple_cc_single_mod+:} false; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_apple_cc_single_mod=no + if test -z "${LT_MULTI_MODULE}"; then + # By default we will add the -single_module flag. You can override + # by either setting the environment variable LT_MULTI_MODULE + # non-empty at configure time, or by adding -multi_module to the + # link flags. + rm -rf libconftest.dylib* + echo "int foo(void){return 1;}" > conftest.c + echo "$LTCC $LTCFLAGS $LDFLAGS -o libconftest.dylib \ +-dynamiclib -Wl,-single_module conftest.c" >&5 + $LTCC $LTCFLAGS $LDFLAGS -o libconftest.dylib \ + -dynamiclib -Wl,-single_module conftest.c 2>conftest.err + _lt_result=$? + # If there is a non-empty error log, and "single_module" + # appears in it, assume the flag caused a linker warning + if test -s conftest.err && $GREP single_module conftest.err; then + cat conftest.err >&5 + # Otherwise, if the output was created with a 0 exit code from + # the compiler, it worked. + elif test -f libconftest.dylib && test $_lt_result -eq 0; then + lt_cv_apple_cc_single_mod=yes + else + cat conftest.err >&5 + fi + rm -rf libconftest.dylib* + rm -f conftest.* + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_apple_cc_single_mod" >&5 +$as_echo "$lt_cv_apple_cc_single_mod" >&6; } + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for -exported_symbols_list linker flag" >&5 +$as_echo_n "checking for -exported_symbols_list linker flag... " >&6; } +if ${lt_cv_ld_exported_symbols_list+:} false; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_ld_exported_symbols_list=no + save_LDFLAGS=$LDFLAGS + echo "_main" > conftest.sym + LDFLAGS="$LDFLAGS -Wl,-exported_symbols_list,conftest.sym" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + lt_cv_ld_exported_symbols_list=yes +else + lt_cv_ld_exported_symbols_list=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + LDFLAGS="$save_LDFLAGS" + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_ld_exported_symbols_list" >&5 +$as_echo "$lt_cv_ld_exported_symbols_list" >&6; } + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for -force_load linker flag" >&5 +$as_echo_n "checking for -force_load linker flag... " >&6; } +if ${lt_cv_ld_force_load+:} false; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_ld_force_load=no + cat > conftest.c << _LT_EOF +int forced_loaded() { return 2;} +_LT_EOF + echo "$LTCC $LTCFLAGS -c -o conftest.o conftest.c" >&5 + $LTCC $LTCFLAGS -c -o conftest.o conftest.c 2>&5 + echo "$AR cru libconftest.a conftest.o" >&5 + $AR cru libconftest.a conftest.o 2>&5 + echo "$RANLIB libconftest.a" >&5 + $RANLIB libconftest.a 2>&5 + cat > conftest.c << _LT_EOF +int main() { return 0;} +_LT_EOF + echo "$LTCC $LTCFLAGS $LDFLAGS -o conftest conftest.c -Wl,-force_load,./libconftest.a" >&5 + $LTCC $LTCFLAGS $LDFLAGS -o conftest conftest.c -Wl,-force_load,./libconftest.a 2>conftest.err + _lt_result=$? + if test -s conftest.err && $GREP force_load conftest.err; then + cat conftest.err >&5 + elif test -f conftest && test $_lt_result -eq 0 && $GREP forced_load conftest >/dev/null 2>&1 ; then + lt_cv_ld_force_load=yes + else + cat conftest.err >&5 + fi + rm -f conftest.err libconftest.a conftest conftest.c + rm -rf conftest.dSYM + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_ld_force_load" >&5 +$as_echo "$lt_cv_ld_force_load" >&6; } + case $host_os in + rhapsody* | darwin1.[012]) + _lt_dar_allow_undefined='${wl}-undefined ${wl}suppress' ;; + darwin1.*) + _lt_dar_allow_undefined='${wl}-flat_namespace ${wl}-undefined ${wl}suppress' ;; + darwin*) # darwin 5.x on + # if running on 10.5 or later, the deployment target defaults + # to the OS version, if on x86, and 10.4, the deployment + # target defaults to 10.4. Don't you love it? + case ${MACOSX_DEPLOYMENT_TARGET-10.0},$host in + 10.0,*86*-darwin8*|10.0,*-darwin[91]*) + _lt_dar_allow_undefined='${wl}-undefined ${wl}dynamic_lookup' ;; + 10.[012][,.]*) + _lt_dar_allow_undefined='${wl}-flat_namespace ${wl}-undefined ${wl}suppress' ;; + 10.*) + _lt_dar_allow_undefined='${wl}-undefined ${wl}dynamic_lookup' ;; + esac + ;; + esac + if test "$lt_cv_apple_cc_single_mod" = "yes"; then + _lt_dar_single_mod='$single_module' + fi + if test "$lt_cv_ld_exported_symbols_list" = "yes"; then + _lt_dar_export_syms=' ${wl}-exported_symbols_list,$output_objdir/${libname}-symbols.expsym' + else + _lt_dar_export_syms='~$NMEDIT -s $output_objdir/${libname}-symbols.expsym ${lib}' + fi + if test "$DSYMUTIL" != ":" && test "$lt_cv_ld_force_load" = "no"; then + _lt_dsymutil='~$DSYMUTIL $lib || :' + else + _lt_dsymutil= + fi + ;; + esac + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to run the C preprocessor" >&5 +$as_echo_n "checking how to run the C preprocessor... " >&6; } +# On Suns, sometimes $CPP names a directory. +if test -n "$CPP" && test -d "$CPP"; then + CPP= +fi +if test -z "$CPP"; then + if ${ac_cv_prog_CPP+:} false; then : + $as_echo_n "(cached) " >&6 +else + # Double quotes because CPP needs to be expanded + for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp" + do + ac_preproc_ok=false +for ac_c_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef __STDC__ +# include +#else +# include +#endif + Syntax error +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + +else + # Broken: fails on valid input. +continue +fi +rm -f conftest.err conftest.i conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + # Broken: success on invalid input. +continue +else + # Passes both tests. +ac_preproc_ok=: +break +fi +rm -f conftest.err conftest.i conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.i conftest.err conftest.$ac_ext +if $ac_preproc_ok; then : + break +fi + + done + ac_cv_prog_CPP=$CPP + +fi + CPP=$ac_cv_prog_CPP +else + ac_cv_prog_CPP=$CPP +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $CPP" >&5 +$as_echo "$CPP" >&6; } +ac_preproc_ok=false +for ac_c_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef __STDC__ +# include +#else +# include +#endif + Syntax error +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + +else + # Broken: fails on valid input. +continue +fi +rm -f conftest.err conftest.i conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + # Broken: success on invalid input. +continue +else + # Passes both tests. +ac_preproc_ok=: +break +fi +rm -f conftest.err conftest.i conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.i conftest.err conftest.$ac_ext +if $ac_preproc_ok; then : + +else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error $? "C preprocessor \"$CPP\" fails sanity check +See \`config.log' for more details" "$LINENO" 5; } +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for ANSI C header files" >&5 +$as_echo_n "checking for ANSI C header files... " >&6; } +if ${ac_cv_header_stdc+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#include +#include + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_header_stdc=yes +else + ac_cv_header_stdc=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + +if test $ac_cv_header_stdc = yes; then + # SunOS 4.x string.h does not declare mem*, contrary to ANSI. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "memchr" >/dev/null 2>&1; then : + +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "free" >/dev/null 2>&1; then : + +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. + if test "$cross_compiling" = yes; then : + : +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#if ((' ' & 0x0FF) == 0x020) +# define ISLOWER(c) ('a' <= (c) && (c) <= 'z') +# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) +#else +# define ISLOWER(c) \ + (('a' <= (c) && (c) <= 'i') \ + || ('j' <= (c) && (c) <= 'r') \ + || ('s' <= (c) && (c) <= 'z')) +# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c)) +#endif + +#define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) +int +main () +{ + int i; + for (i = 0; i < 256; i++) + if (XOR (islower (i), ISLOWER (i)) + || toupper (i) != TOUPPER (i)) + return 2; + return 0; +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + +else + ac_cv_header_stdc=no +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + +fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_header_stdc" >&5 +$as_echo "$ac_cv_header_stdc" >&6; } +if test $ac_cv_header_stdc = yes; then + +$as_echo "#define STDC_HEADERS 1" >>confdefs.h + +fi + +# On IRIX 5.3, sys/types and inttypes.h are conflicting. +for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \ + inttypes.h stdint.h unistd.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_compile "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default +" +if eval test \"x\$"$as_ac_Header"\" = x"yes"; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + + +for ac_header in dlfcn.h +do : + ac_fn_c_check_header_compile "$LINENO" "dlfcn.h" "ac_cv_header_dlfcn_h" "$ac_includes_default +" +if test "x$ac_cv_header_dlfcn_h" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_DLFCN_H 1 +_ACEOF + +fi + +done + + + + + +# Set options +# Check whether --enable-static was given. +if test "${enable_static+set}" = set; then : + enableval=$enable_static; p=${PACKAGE-default} + case $enableval in + yes) enable_static=yes ;; + no) enable_static=no ;; + *) + enable_static=no + # Look at the argument we got. We use all the common list separators. + lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR," + for pkg in $enableval; do + IFS="$lt_save_ifs" + if test "X$pkg" = "X$p"; then + enable_static=yes + fi + done + IFS="$lt_save_ifs" + ;; + esac +else + enable_static=no +fi + + + + + + + + + + + enable_dlopen=no + + + enable_win32_dll=no + + + # Check whether --enable-shared was given. +if test "${enable_shared+set}" = set; then : + enableval=$enable_shared; p=${PACKAGE-default} + case $enableval in + yes) enable_shared=yes ;; + no) enable_shared=no ;; + *) + enable_shared=no + # Look at the argument we got. We use all the common list separators. + lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR," + for pkg in $enableval; do + IFS="$lt_save_ifs" + if test "X$pkg" = "X$p"; then + enable_shared=yes + fi + done + IFS="$lt_save_ifs" + ;; + esac +else + enable_shared=yes +fi + + + + + + + + + + + +# Check whether --with-pic was given. +if test "${with_pic+set}" = set; then : + withval=$with_pic; lt_p=${PACKAGE-default} + case $withval in + yes|no) pic_mode=$withval ;; + *) + pic_mode=default + # Look at the argument we got. We use all the common list separators. + lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR," + for lt_pkg in $withval; do + IFS="$lt_save_ifs" + if test "X$lt_pkg" = "X$lt_p"; then + pic_mode=yes + fi + done + IFS="$lt_save_ifs" + ;; + esac +else + pic_mode=default +fi + + +test -z "$pic_mode" && pic_mode=default + + + + + + + + # Check whether --enable-fast-install was given. +if test "${enable_fast_install+set}" = set; then : + enableval=$enable_fast_install; p=${PACKAGE-default} + case $enableval in + yes) enable_fast_install=yes ;; + no) enable_fast_install=no ;; + *) + enable_fast_install=no + # Look at the argument we got. We use all the common list separators. + lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR," + for pkg in $enableval; do + IFS="$lt_save_ifs" + if test "X$pkg" = "X$p"; then + enable_fast_install=yes + fi + done + IFS="$lt_save_ifs" + ;; + esac +else + enable_fast_install=yes +fi + + + + + + + + + + + +# This can be used to rebuild libtool when needed +LIBTOOL_DEPS="$ltmain" + +# Always use our own libtool. +LIBTOOL='$(SHELL) $(top_builddir)/libtool' + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +test -z "$LN_S" && LN_S="ln -s" + + + + + + + + + + + + + + +if test -n "${ZSH_VERSION+set}" ; then + setopt NO_GLOB_SUBST +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for objdir" >&5 +$as_echo_n "checking for objdir... " >&6; } +if ${lt_cv_objdir+:} false; then : + $as_echo_n "(cached) " >&6 +else + rm -f .libs 2>/dev/null +mkdir .libs 2>/dev/null +if test -d .libs; then + lt_cv_objdir=.libs +else + # MS-DOS does not allow filenames that begin with a dot. + lt_cv_objdir=_libs +fi +rmdir .libs 2>/dev/null +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_objdir" >&5 +$as_echo "$lt_cv_objdir" >&6; } +objdir=$lt_cv_objdir + + + + + +cat >>confdefs.h <<_ACEOF +#define LT_OBJDIR "$lt_cv_objdir/" +_ACEOF + + + + +case $host_os in +aix3*) + # AIX sometimes has problems with the GCC collect2 program. For some + # reason, if we set the COLLECT_NAMES environment variable, the problems + # vanish in a puff of smoke. + if test "X${COLLECT_NAMES+set}" != Xset; then + COLLECT_NAMES= + export COLLECT_NAMES + fi + ;; +esac + +# Global variables: +ofile=libtool +can_build_shared=yes + +# All known linkers require a `.a' archive for static linking (except MSVC, +# which needs '.lib'). +libext=a + +with_gnu_ld="$lt_cv_prog_gnu_ld" + +old_CC="$CC" +old_CFLAGS="$CFLAGS" + +# Set sane defaults for various variables +test -z "$CC" && CC=cc +test -z "$LTCC" && LTCC=$CC +test -z "$LTCFLAGS" && LTCFLAGS=$CFLAGS +test -z "$LD" && LD=ld +test -z "$ac_objext" && ac_objext=o + +for cc_temp in $compiler""; do + case $cc_temp in + compile | *[\\/]compile | ccache | *[\\/]ccache ) ;; + distcc | *[\\/]distcc | purify | *[\\/]purify ) ;; + \-*) ;; + *) break;; + esac +done +cc_basename=`$ECHO "$cc_temp" | $SED "s%.*/%%; s%^$host_alias-%%"` + + +# Only perform the check for file, if the check method requires it +test -z "$MAGIC_CMD" && MAGIC_CMD=file +case $deplibs_check_method in +file_magic*) + if test "$file_magic_cmd" = '$MAGIC_CMD'; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for ${ac_tool_prefix}file" >&5 +$as_echo_n "checking for ${ac_tool_prefix}file... " >&6; } +if ${lt_cv_path_MAGIC_CMD+:} false; then : + $as_echo_n "(cached) " >&6 +else + case $MAGIC_CMD in +[\\/*] | ?:[\\/]*) + lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path. + ;; +*) + lt_save_MAGIC_CMD="$MAGIC_CMD" + lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR + ac_dummy="/usr/bin$PATH_SEPARATOR$PATH" + for ac_dir in $ac_dummy; do + IFS="$lt_save_ifs" + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/${ac_tool_prefix}file; then + lt_cv_path_MAGIC_CMD="$ac_dir/${ac_tool_prefix}file" + if test -n "$file_magic_test_file"; then + case $deplibs_check_method in + "file_magic "*) + file_magic_regex=`expr "$deplibs_check_method" : "file_magic \(.*\)"` + MAGIC_CMD="$lt_cv_path_MAGIC_CMD" + if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null | + $EGREP "$file_magic_regex" > /dev/null; then + : + else + cat <<_LT_EOF 1>&2 + +*** Warning: the command libtool uses to detect shared libraries, +*** $file_magic_cmd, produces output that libtool cannot recognize. +*** The result is that libtool may fail to recognize shared libraries +*** as such. This will affect the creation of libtool libraries that +*** depend on shared libraries, but programs linked with such libtool +*** libraries will work regardless of this problem. Nevertheless, you +*** may want to report the problem to your system manager and/or to +*** bug-libtool@gnu.org + +_LT_EOF + fi ;; + esac + fi + break + fi + done + IFS="$lt_save_ifs" + MAGIC_CMD="$lt_save_MAGIC_CMD" + ;; +esac +fi + +MAGIC_CMD="$lt_cv_path_MAGIC_CMD" +if test -n "$MAGIC_CMD"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $MAGIC_CMD" >&5 +$as_echo "$MAGIC_CMD" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + + + +if test -z "$lt_cv_path_MAGIC_CMD"; then + if test -n "$ac_tool_prefix"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for file" >&5 +$as_echo_n "checking for file... " >&6; } +if ${lt_cv_path_MAGIC_CMD+:} false; then : + $as_echo_n "(cached) " >&6 +else + case $MAGIC_CMD in +[\\/*] | ?:[\\/]*) + lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path. + ;; +*) + lt_save_MAGIC_CMD="$MAGIC_CMD" + lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR + ac_dummy="/usr/bin$PATH_SEPARATOR$PATH" + for ac_dir in $ac_dummy; do + IFS="$lt_save_ifs" + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/file; then + lt_cv_path_MAGIC_CMD="$ac_dir/file" + if test -n "$file_magic_test_file"; then + case $deplibs_check_method in + "file_magic "*) + file_magic_regex=`expr "$deplibs_check_method" : "file_magic \(.*\)"` + MAGIC_CMD="$lt_cv_path_MAGIC_CMD" + if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null | + $EGREP "$file_magic_regex" > /dev/null; then + : + else + cat <<_LT_EOF 1>&2 + +*** Warning: the command libtool uses to detect shared libraries, +*** $file_magic_cmd, produces output that libtool cannot recognize. +*** The result is that libtool may fail to recognize shared libraries +*** as such. This will affect the creation of libtool libraries that +*** depend on shared libraries, but programs linked with such libtool +*** libraries will work regardless of this problem. Nevertheless, you +*** may want to report the problem to your system manager and/or to +*** bug-libtool@gnu.org + +_LT_EOF + fi ;; + esac + fi + break + fi + done + IFS="$lt_save_ifs" + MAGIC_CMD="$lt_save_MAGIC_CMD" + ;; +esac +fi + +MAGIC_CMD="$lt_cv_path_MAGIC_CMD" +if test -n "$MAGIC_CMD"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $MAGIC_CMD" >&5 +$as_echo "$MAGIC_CMD" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + else + MAGIC_CMD=: + fi +fi + + fi + ;; +esac + +# Use C for the default configuration in the libtool script + +lt_save_CC="$CC" +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + +# Source file extension for C test sources. +ac_ext=c + +# Object file extension for compiled C test sources. +objext=o +objext=$objext + +# Code to be used in simple compile tests +lt_simple_compile_test_code="int some_variable = 0;" + +# Code to be used in simple link tests +lt_simple_link_test_code='int main(){return(0);}' + + + + + + + +# If no C compiler was specified, use CC. +LTCC=${LTCC-"$CC"} + +# If no C compiler flags were specified, use CFLAGS. +LTCFLAGS=${LTCFLAGS-"$CFLAGS"} + +# Allow CC to be a program name with arguments. +compiler=$CC + +# Save the default compiler, since it gets overwritten when the other +# tags are being tested, and _LT_TAGVAR(compiler, []) is a NOP. +compiler_DEFAULT=$CC + +# save warnings/boilerplate of simple test code +ac_outfile=conftest.$ac_objext +echo "$lt_simple_compile_test_code" >conftest.$ac_ext +eval "$ac_compile" 2>&1 >/dev/null | $SED '/^$/d; /^ *+/d' >conftest.err +_lt_compiler_boilerplate=`cat conftest.err` +$RM conftest* + +ac_outfile=conftest.$ac_objext +echo "$lt_simple_link_test_code" >conftest.$ac_ext +eval "$ac_link" 2>&1 >/dev/null | $SED '/^$/d; /^ *+/d' >conftest.err +_lt_linker_boilerplate=`cat conftest.err` +$RM -r conftest* + + +## CAVEAT EMPTOR: +## There is no encapsulation within the following macros, do not change +## the running order or otherwise move them around unless you know exactly +## what you are doing... +if test -n "$compiler"; then + +lt_prog_compiler_no_builtin_flag= + +if test "$GCC" = yes; then + case $cc_basename in + nvcc*) + lt_prog_compiler_no_builtin_flag=' -Xcompiler -fno-builtin' ;; + *) + lt_prog_compiler_no_builtin_flag=' -fno-builtin' ;; + esac + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler supports -fno-rtti -fno-exceptions" >&5 +$as_echo_n "checking if $compiler supports -fno-rtti -fno-exceptions... " >&6; } +if ${lt_cv_prog_compiler_rtti_exceptions+:} false; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_prog_compiler_rtti_exceptions=no + ac_outfile=conftest.$ac_objext + echo "$lt_simple_compile_test_code" > conftest.$ac_ext + lt_compiler_flag="-fno-rtti -fno-exceptions" + # Insert the option either (1) after the last *FLAGS variable, or + # (2) before a word containing "conftest.", or (3) at the end. + # Note that $ac_compile itself does not contain backslashes and begins + # with a dollar sign (not a hyphen), so the echo should work correctly. + # The option is referenced via a variable to avoid confusing sed. + lt_compile=`echo "$ac_compile" | $SED \ + -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ + -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ + -e 's:$: $lt_compiler_flag:'` + (eval echo "\"\$as_me:$LINENO: $lt_compile\"" >&5) + (eval "$lt_compile" 2>conftest.err) + ac_status=$? + cat conftest.err >&5 + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + if (exit $ac_status) && test -s "$ac_outfile"; then + # The compiler can only warn and ignore the option if not recognized + # So say no if there are warnings other than the usual output. + $ECHO "$_lt_compiler_boilerplate" | $SED '/^$/d' >conftest.exp + $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2 + if test ! -s conftest.er2 || diff conftest.exp conftest.er2 >/dev/null; then + lt_cv_prog_compiler_rtti_exceptions=yes + fi + fi + $RM conftest* + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_rtti_exceptions" >&5 +$as_echo "$lt_cv_prog_compiler_rtti_exceptions" >&6; } + +if test x"$lt_cv_prog_compiler_rtti_exceptions" = xyes; then + lt_prog_compiler_no_builtin_flag="$lt_prog_compiler_no_builtin_flag -fno-rtti -fno-exceptions" +else + : +fi + +fi + + + + + + + lt_prog_compiler_wl= +lt_prog_compiler_pic= +lt_prog_compiler_static= + + + if test "$GCC" = yes; then + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_static='-static' + + case $host_os in + aix*) + # All AIX code is PIC. + if test "$host_cpu" = ia64; then + # AIX 5 now supports IA64 processor + lt_prog_compiler_static='-Bstatic' + fi + ;; + + amigaos*) + case $host_cpu in + powerpc) + # see comment about AmigaOS4 .so support + lt_prog_compiler_pic='-fPIC' + ;; + m68k) + # FIXME: we need at least 68020 code to build shared libraries, but + # adding the `-m68020' flag to GCC prevents building anything better, + # like `-m68040'. + lt_prog_compiler_pic='-m68020 -resident32 -malways-restore-a4' + ;; + esac + ;; + + beos* | irix5* | irix6* | nonstopux* | osf3* | osf4* | osf5*) + # PIC is the default for these OSes. + ;; + + mingw* | cygwin* | pw32* | os2* | cegcc*) + # This hack is so that the source file can tell whether it is being + # built for inclusion in a dll (and should export symbols for example). + # Although the cygwin gcc ignores -fPIC, still need this for old-style + # (--disable-auto-import) libraries + lt_prog_compiler_pic='-DDLL_EXPORT' + ;; + + darwin* | rhapsody*) + # PIC is the default on this platform + # Common symbols not allowed in MH_DYLIB files + lt_prog_compiler_pic='-fno-common' + ;; + + haiku*) + # PIC is the default for Haiku. + # The "-static" flag exists, but is broken. + lt_prog_compiler_static= + ;; + + hpux*) + # PIC is the default for 64-bit PA HP-UX, but not for 32-bit + # PA HP-UX. On IA64 HP-UX, PIC is the default but the pic flag + # sets the default TLS model and affects inlining. + case $host_cpu in + hppa*64*) + # +Z the default + ;; + *) + lt_prog_compiler_pic='-fPIC' + ;; + esac + ;; + + interix[3-9]*) + # Interix 3.x gcc -fpic/-fPIC options generate broken code. + # Instead, we relocate shared libraries at runtime. + ;; + + msdosdjgpp*) + # Just because we use GCC doesn't mean we suddenly get shared libraries + # on systems that don't support them. + lt_prog_compiler_can_build_shared=no + enable_shared=no + ;; + + *nto* | *qnx*) + # QNX uses GNU C++, but need to define -shared option too, otherwise + # it will coredump. + lt_prog_compiler_pic='-fPIC -shared' + ;; + + sysv4*MP*) + if test -d /usr/nec; then + lt_prog_compiler_pic=-Kconform_pic + fi + ;; + + *) + lt_prog_compiler_pic='-fPIC' + ;; + esac + + case $cc_basename in + nvcc*) # Cuda Compiler Driver 2.2 + lt_prog_compiler_wl='-Xlinker ' + if test -n "$lt_prog_compiler_pic"; then + lt_prog_compiler_pic="-Xcompiler $lt_prog_compiler_pic" + fi + ;; + esac + else + # PORTME Check for flag to pass linker flags through the system compiler. + case $host_os in + aix*) + lt_prog_compiler_wl='-Wl,' + if test "$host_cpu" = ia64; then + # AIX 5 now supports IA64 processor + lt_prog_compiler_static='-Bstatic' + else + lt_prog_compiler_static='-bnso -bI:/lib/syscalls.exp' + fi + ;; + + mingw* | cygwin* | pw32* | os2* | cegcc*) + # This hack is so that the source file can tell whether it is being + # built for inclusion in a dll (and should export symbols for example). + lt_prog_compiler_pic='-DDLL_EXPORT' + ;; + + hpux9* | hpux10* | hpux11*) + lt_prog_compiler_wl='-Wl,' + # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but + # not for PA HP-UX. + case $host_cpu in + hppa*64*|ia64*) + # +Z the default + ;; + *) + lt_prog_compiler_pic='+Z' + ;; + esac + # Is there a better lt_prog_compiler_static that works with the bundled CC? + lt_prog_compiler_static='${wl}-a ${wl}archive' + ;; + + irix5* | irix6* | nonstopux*) + lt_prog_compiler_wl='-Wl,' + # PIC (with -KPIC) is the default. + lt_prog_compiler_static='-non_shared' + ;; + + linux* | k*bsd*-gnu | kopensolaris*-gnu) + case $cc_basename in + # old Intel for x86_64 which still supported -KPIC. + ecc*) + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_pic='-KPIC' + lt_prog_compiler_static='-static' + ;; + # icc used to be incompatible with GCC. + # ICC 10 doesn't accept -KPIC any more. + icc* | ifort*) + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_pic='-fPIC' + lt_prog_compiler_static='-static' + ;; + # Lahey Fortran 8.1. + lf95*) + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_pic='--shared' + lt_prog_compiler_static='--static' + ;; + nagfor*) + # NAG Fortran compiler + lt_prog_compiler_wl='-Wl,-Wl,,' + lt_prog_compiler_pic='-PIC' + lt_prog_compiler_static='-Bstatic' + ;; + pgcc* | pgf77* | pgf90* | pgf95* | pgfortran*) + # Portland Group compilers (*not* the Pentium gcc compiler, + # which looks to be a dead project) + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_pic='-fpic' + lt_prog_compiler_static='-Bstatic' + ;; + ccc*) + lt_prog_compiler_wl='-Wl,' + # All Alpha code is PIC. + lt_prog_compiler_static='-non_shared' + ;; + xl* | bgxl* | bgf* | mpixl*) + # IBM XL C 8.0/Fortran 10.1, 11.1 on PPC and BlueGene + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_pic='-qpic' + lt_prog_compiler_static='-qstaticlink' + ;; + *) + case `$CC -V 2>&1 | sed 5q` in + *Sun\ Ceres\ Fortran* | *Sun*Fortran*\ [1-7].* | *Sun*Fortran*\ 8.[0-3]*) + # Sun Fortran 8.3 passes all unrecognized flags to the linker + lt_prog_compiler_pic='-KPIC' + lt_prog_compiler_static='-Bstatic' + lt_prog_compiler_wl='' + ;; + *Sun\ F* | *Sun*Fortran*) + lt_prog_compiler_pic='-KPIC' + lt_prog_compiler_static='-Bstatic' + lt_prog_compiler_wl='-Qoption ld ' + ;; + *Sun\ C*) + # Sun C 5.9 + lt_prog_compiler_pic='-KPIC' + lt_prog_compiler_static='-Bstatic' + lt_prog_compiler_wl='-Wl,' + ;; + *Intel*\ [CF]*Compiler*) + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_pic='-fPIC' + lt_prog_compiler_static='-static' + ;; + *Portland\ Group*) + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_pic='-fpic' + lt_prog_compiler_static='-Bstatic' + ;; + esac + ;; + esac + ;; + + newsos6) + lt_prog_compiler_pic='-KPIC' + lt_prog_compiler_static='-Bstatic' + ;; + + *nto* | *qnx*) + # QNX uses GNU C++, but need to define -shared option too, otherwise + # it will coredump. + lt_prog_compiler_pic='-fPIC -shared' + ;; + + osf3* | osf4* | osf5*) + lt_prog_compiler_wl='-Wl,' + # All OSF/1 code is PIC. + lt_prog_compiler_static='-non_shared' + ;; + + rdos*) + lt_prog_compiler_static='-non_shared' + ;; + + solaris*) + lt_prog_compiler_pic='-KPIC' + lt_prog_compiler_static='-Bstatic' + case $cc_basename in + f77* | f90* | f95* | sunf77* | sunf90* | sunf95*) + lt_prog_compiler_wl='-Qoption ld ';; + *) + lt_prog_compiler_wl='-Wl,';; + esac + ;; + + sunos4*) + lt_prog_compiler_wl='-Qoption ld ' + lt_prog_compiler_pic='-PIC' + lt_prog_compiler_static='-Bstatic' + ;; + + sysv4 | sysv4.2uw2* | sysv4.3*) + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_pic='-KPIC' + lt_prog_compiler_static='-Bstatic' + ;; + + sysv4*MP*) + if test -d /usr/nec ;then + lt_prog_compiler_pic='-Kconform_pic' + lt_prog_compiler_static='-Bstatic' + fi + ;; + + sysv5* | unixware* | sco3.2v5* | sco5v6* | OpenUNIX*) + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_pic='-KPIC' + lt_prog_compiler_static='-Bstatic' + ;; + + unicos*) + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_can_build_shared=no + ;; + + uts4*) + lt_prog_compiler_pic='-pic' + lt_prog_compiler_static='-Bstatic' + ;; + + *) + lt_prog_compiler_can_build_shared=no + ;; + esac + fi + +case $host_os in + # For platforms which do not support PIC, -DPIC is meaningless: + *djgpp*) + lt_prog_compiler_pic= + ;; + *) + lt_prog_compiler_pic="$lt_prog_compiler_pic -DPIC" + ;; +esac + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $compiler option to produce PIC" >&5 +$as_echo_n "checking for $compiler option to produce PIC... " >&6; } +if ${lt_cv_prog_compiler_pic+:} false; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_prog_compiler_pic=$lt_prog_compiler_pic +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_pic" >&5 +$as_echo "$lt_cv_prog_compiler_pic" >&6; } +lt_prog_compiler_pic=$lt_cv_prog_compiler_pic + +# +# Check to make sure the PIC flag actually works. +# +if test -n "$lt_prog_compiler_pic"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler PIC flag $lt_prog_compiler_pic works" >&5 +$as_echo_n "checking if $compiler PIC flag $lt_prog_compiler_pic works... " >&6; } +if ${lt_cv_prog_compiler_pic_works+:} false; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_prog_compiler_pic_works=no + ac_outfile=conftest.$ac_objext + echo "$lt_simple_compile_test_code" > conftest.$ac_ext + lt_compiler_flag="$lt_prog_compiler_pic -DPIC" + # Insert the option either (1) after the last *FLAGS variable, or + # (2) before a word containing "conftest.", or (3) at the end. + # Note that $ac_compile itself does not contain backslashes and begins + # with a dollar sign (not a hyphen), so the echo should work correctly. + # The option is referenced via a variable to avoid confusing sed. + lt_compile=`echo "$ac_compile" | $SED \ + -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ + -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ + -e 's:$: $lt_compiler_flag:'` + (eval echo "\"\$as_me:$LINENO: $lt_compile\"" >&5) + (eval "$lt_compile" 2>conftest.err) + ac_status=$? + cat conftest.err >&5 + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + if (exit $ac_status) && test -s "$ac_outfile"; then + # The compiler can only warn and ignore the option if not recognized + # So say no if there are warnings other than the usual output. + $ECHO "$_lt_compiler_boilerplate" | $SED '/^$/d' >conftest.exp + $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2 + if test ! -s conftest.er2 || diff conftest.exp conftest.er2 >/dev/null; then + lt_cv_prog_compiler_pic_works=yes + fi + fi + $RM conftest* + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_pic_works" >&5 +$as_echo "$lt_cv_prog_compiler_pic_works" >&6; } + +if test x"$lt_cv_prog_compiler_pic_works" = xyes; then + case $lt_prog_compiler_pic in + "" | " "*) ;; + *) lt_prog_compiler_pic=" $lt_prog_compiler_pic" ;; + esac +else + lt_prog_compiler_pic= + lt_prog_compiler_can_build_shared=no +fi + +fi + + + + + + + + + + + +# +# Check to make sure the static flag actually works. +# +wl=$lt_prog_compiler_wl eval lt_tmp_static_flag=\"$lt_prog_compiler_static\" +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler static flag $lt_tmp_static_flag works" >&5 +$as_echo_n "checking if $compiler static flag $lt_tmp_static_flag works... " >&6; } +if ${lt_cv_prog_compiler_static_works+:} false; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_prog_compiler_static_works=no + save_LDFLAGS="$LDFLAGS" + LDFLAGS="$LDFLAGS $lt_tmp_static_flag" + echo "$lt_simple_link_test_code" > conftest.$ac_ext + if (eval $ac_link 2>conftest.err) && test -s conftest$ac_exeext; then + # The linker can only warn and ignore the option if not recognized + # So say no if there are warnings + if test -s conftest.err; then + # Append any errors to the config.log. + cat conftest.err 1>&5 + $ECHO "$_lt_linker_boilerplate" | $SED '/^$/d' > conftest.exp + $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2 + if diff conftest.exp conftest.er2 >/dev/null; then + lt_cv_prog_compiler_static_works=yes + fi + else + lt_cv_prog_compiler_static_works=yes + fi + fi + $RM -r conftest* + LDFLAGS="$save_LDFLAGS" + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_static_works" >&5 +$as_echo "$lt_cv_prog_compiler_static_works" >&6; } + +if test x"$lt_cv_prog_compiler_static_works" = xyes; then + : +else + lt_prog_compiler_static= +fi + + + + + + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler supports -c -o file.$ac_objext" >&5 +$as_echo_n "checking if $compiler supports -c -o file.$ac_objext... " >&6; } +if ${lt_cv_prog_compiler_c_o+:} false; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_prog_compiler_c_o=no + $RM -r conftest 2>/dev/null + mkdir conftest + cd conftest + mkdir out + echo "$lt_simple_compile_test_code" > conftest.$ac_ext + + lt_compiler_flag="-o out/conftest2.$ac_objext" + # Insert the option either (1) after the last *FLAGS variable, or + # (2) before a word containing "conftest.", or (3) at the end. + # Note that $ac_compile itself does not contain backslashes and begins + # with a dollar sign (not a hyphen), so the echo should work correctly. + lt_compile=`echo "$ac_compile" | $SED \ + -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ + -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ + -e 's:$: $lt_compiler_flag:'` + (eval echo "\"\$as_me:$LINENO: $lt_compile\"" >&5) + (eval "$lt_compile" 2>out/conftest.err) + ac_status=$? + cat out/conftest.err >&5 + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + if (exit $ac_status) && test -s out/conftest2.$ac_objext + then + # The compiler can only warn and ignore the option if not recognized + # So say no if there are warnings + $ECHO "$_lt_compiler_boilerplate" | $SED '/^$/d' > out/conftest.exp + $SED '/^$/d; /^ *+/d' out/conftest.err >out/conftest.er2 + if test ! -s out/conftest.er2 || diff out/conftest.exp out/conftest.er2 >/dev/null; then + lt_cv_prog_compiler_c_o=yes + fi + fi + chmod u+w . 2>&5 + $RM conftest* + # SGI C++ compiler will create directory out/ii_files/ for + # template instantiation + test -d out/ii_files && $RM out/ii_files/* && rmdir out/ii_files + $RM out/* && rmdir out + cd .. + $RM -r conftest + $RM conftest* + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_c_o" >&5 +$as_echo "$lt_cv_prog_compiler_c_o" >&6; } + + + + + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler supports -c -o file.$ac_objext" >&5 +$as_echo_n "checking if $compiler supports -c -o file.$ac_objext... " >&6; } +if ${lt_cv_prog_compiler_c_o+:} false; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_prog_compiler_c_o=no + $RM -r conftest 2>/dev/null + mkdir conftest + cd conftest + mkdir out + echo "$lt_simple_compile_test_code" > conftest.$ac_ext + + lt_compiler_flag="-o out/conftest2.$ac_objext" + # Insert the option either (1) after the last *FLAGS variable, or + # (2) before a word containing "conftest.", or (3) at the end. + # Note that $ac_compile itself does not contain backslashes and begins + # with a dollar sign (not a hyphen), so the echo should work correctly. + lt_compile=`echo "$ac_compile" | $SED \ + -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ + -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ + -e 's:$: $lt_compiler_flag:'` + (eval echo "\"\$as_me:$LINENO: $lt_compile\"" >&5) + (eval "$lt_compile" 2>out/conftest.err) + ac_status=$? + cat out/conftest.err >&5 + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + if (exit $ac_status) && test -s out/conftest2.$ac_objext + then + # The compiler can only warn and ignore the option if not recognized + # So say no if there are warnings + $ECHO "$_lt_compiler_boilerplate" | $SED '/^$/d' > out/conftest.exp + $SED '/^$/d; /^ *+/d' out/conftest.err >out/conftest.er2 + if test ! -s out/conftest.er2 || diff out/conftest.exp out/conftest.er2 >/dev/null; then + lt_cv_prog_compiler_c_o=yes + fi + fi + chmod u+w . 2>&5 + $RM conftest* + # SGI C++ compiler will create directory out/ii_files/ for + # template instantiation + test -d out/ii_files && $RM out/ii_files/* && rmdir out/ii_files + $RM out/* && rmdir out + cd .. + $RM -r conftest + $RM conftest* + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_c_o" >&5 +$as_echo "$lt_cv_prog_compiler_c_o" >&6; } + + + + +hard_links="nottested" +if test "$lt_cv_prog_compiler_c_o" = no && test "$need_locks" != no; then + # do not overwrite the value of need_locks provided by the user + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if we can lock with hard links" >&5 +$as_echo_n "checking if we can lock with hard links... " >&6; } + hard_links=yes + $RM conftest* + ln conftest.a conftest.b 2>/dev/null && hard_links=no + touch conftest.a + ln conftest.a conftest.b 2>&5 || hard_links=no + ln conftest.a conftest.b 2>/dev/null && hard_links=no + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $hard_links" >&5 +$as_echo "$hard_links" >&6; } + if test "$hard_links" = no; then + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: \`$CC' does not support \`-c -o', so \`make -j' may be unsafe" >&5 +$as_echo "$as_me: WARNING: \`$CC' does not support \`-c -o', so \`make -j' may be unsafe" >&2;} + need_locks=warn + fi +else + need_locks=no +fi + + + + + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the $compiler linker ($LD) supports shared libraries" >&5 +$as_echo_n "checking whether the $compiler linker ($LD) supports shared libraries... " >&6; } + + runpath_var= + allow_undefined_flag= + always_export_symbols=no + archive_cmds= + archive_expsym_cmds= + compiler_needs_object=no + enable_shared_with_static_runtimes=no + export_dynamic_flag_spec= + export_symbols_cmds='$NM $libobjs $convenience | $global_symbol_pipe | $SED '\''s/.* //'\'' | sort | uniq > $export_symbols' + hardcode_automatic=no + hardcode_direct=no + hardcode_direct_absolute=no + hardcode_libdir_flag_spec= + hardcode_libdir_separator= + hardcode_minus_L=no + hardcode_shlibpath_var=unsupported + inherit_rpath=no + link_all_deplibs=unknown + module_cmds= + module_expsym_cmds= + old_archive_from_new_cmds= + old_archive_from_expsyms_cmds= + thread_safe_flag_spec= + whole_archive_flag_spec= + # include_expsyms should be a list of space-separated symbols to be *always* + # included in the symbol list + include_expsyms= + # exclude_expsyms can be an extended regexp of symbols to exclude + # it will be wrapped by ` (' and `)$', so one must not match beginning or + # end of line. Example: `a|bc|.*d.*' will exclude the symbols `a' and `bc', + # as well as any symbol that contains `d'. + exclude_expsyms='_GLOBAL_OFFSET_TABLE_|_GLOBAL__F[ID]_.*' + # Although _GLOBAL_OFFSET_TABLE_ is a valid symbol C name, most a.out + # platforms (ab)use it in PIC code, but their linkers get confused if + # the symbol is explicitly referenced. Since portable code cannot + # rely on this symbol name, it's probably fine to never include it in + # preloaded symbol tables. + # Exclude shared library initialization/finalization symbols. + extract_expsyms_cmds= + + case $host_os in + cygwin* | mingw* | pw32* | cegcc*) + # FIXME: the MSVC++ port hasn't been tested in a loooong time + # When not using gcc, we currently assume that we are using + # Microsoft Visual C++. + if test "$GCC" != yes; then + with_gnu_ld=no + fi + ;; + interix*) + # we just hope/assume this is gcc and not c89 (= MSVC++) + with_gnu_ld=yes + ;; + openbsd*) + with_gnu_ld=no + ;; + esac + + ld_shlibs=yes + + # On some targets, GNU ld is compatible enough with the native linker + # that we're better off using the native interface for both. + lt_use_gnu_ld_interface=no + if test "$with_gnu_ld" = yes; then + case $host_os in + aix*) + # The AIX port of GNU ld has always aspired to compatibility + # with the native linker. However, as the warning in the GNU ld + # block says, versions before 2.19.5* couldn't really create working + # shared libraries, regardless of the interface used. + case `$LD -v 2>&1` in + *\ \(GNU\ Binutils\)\ 2.19.5*) ;; + *\ \(GNU\ Binutils\)\ 2.[2-9]*) ;; + *\ \(GNU\ Binutils\)\ [3-9]*) ;; + *) + lt_use_gnu_ld_interface=yes + ;; + esac + ;; + *) + lt_use_gnu_ld_interface=yes + ;; + esac + fi + + if test "$lt_use_gnu_ld_interface" = yes; then + # If archive_cmds runs LD, not CC, wlarc should be empty + wlarc='${wl}' + + # Set some defaults for GNU ld with shared library support. These + # are reset later if shared libraries are not supported. Putting them + # here allows them to be overridden if necessary. + runpath_var=LD_RUN_PATH + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + export_dynamic_flag_spec='${wl}--export-dynamic' + # ancient GNU ld didn't support --whole-archive et. al. + if $LD --help 2>&1 | $GREP 'no-whole-archive' > /dev/null; then + whole_archive_flag_spec="$wlarc"'--whole-archive$convenience '"$wlarc"'--no-whole-archive' + else + whole_archive_flag_spec= + fi + supports_anon_versioning=no + case `$LD -v 2>&1` in + *GNU\ gold*) supports_anon_versioning=yes ;; + *\ [01].* | *\ 2.[0-9].* | *\ 2.10.*) ;; # catch versions < 2.11 + *\ 2.11.93.0.2\ *) supports_anon_versioning=yes ;; # RH7.3 ... + *\ 2.11.92.0.12\ *) supports_anon_versioning=yes ;; # Mandrake 8.2 ... + *\ 2.11.*) ;; # other 2.11 versions + *) supports_anon_versioning=yes ;; + esac + + # See if GNU ld supports shared libraries. + case $host_os in + aix[3-9]*) + # On AIX/PPC, the GNU linker is very broken + if test "$host_cpu" != ia64; then + ld_shlibs=no + cat <<_LT_EOF 1>&2 + +*** Warning: the GNU linker, at least up to release 2.19, is reported +*** to be unable to reliably create shared libraries on AIX. +*** Therefore, libtool is disabling shared libraries support. If you +*** really care for shared libraries, you may want to install binutils +*** 2.20 or above, or modify your PATH so that a non-GNU linker is found. +*** You will then need to restart the configuration process. + +_LT_EOF + fi + ;; + + amigaos*) + case $host_cpu in + powerpc) + # see comment about AmigaOS4 .so support + archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + archive_expsym_cmds='' + ;; + m68k) + archive_cmds='$RM $output_objdir/a2ixlibrary.data~$ECHO "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$ECHO "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$ECHO "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$ECHO "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)' + hardcode_libdir_flag_spec='-L$libdir' + hardcode_minus_L=yes + ;; + esac + ;; + + beos*) + if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then + allow_undefined_flag=unsupported + # Joseph Beckenbach says some releases of gcc + # support --undefined. This deserves some investigation. FIXME + archive_cmds='$CC -nostart $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + else + ld_shlibs=no + fi + ;; + + cygwin* | mingw* | pw32* | cegcc*) + # _LT_TAGVAR(hardcode_libdir_flag_spec, ) is actually meaningless, + # as there is no search path for DLLs. + hardcode_libdir_flag_spec='-L$libdir' + export_dynamic_flag_spec='${wl}--export-all-symbols' + allow_undefined_flag=unsupported + always_export_symbols=no + enable_shared_with_static_runtimes=yes + export_symbols_cmds='$NM $libobjs $convenience | $global_symbol_pipe | $SED -e '\''/^[BCDGRS][ ]/s/.*[ ]\([^ ]*\)/\1 DATA/;s/^.*[ ]__nm__\([^ ]*\)[ ][^ ]*/\1 DATA/;/^I[ ]/d;/^[AITW][ ]/s/.* //'\'' | sort | uniq > $export_symbols' + exclude_expsyms='[_]+GLOBAL_OFFSET_TABLE_|[_]+GLOBAL__[FID]_.*|[_]+head_[A-Za-z0-9_]+_dll|[A-Za-z0-9_]+_dll_iname' + + if $LD --help 2>&1 | $GREP 'auto-import' > /dev/null; then + archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib' + # If the export-symbols file already is a .def file (1st line + # is EXPORTS), use it as is; otherwise, prepend... + archive_expsym_cmds='if test "x`$SED 1q $export_symbols`" = xEXPORTS; then + cp $export_symbols $output_objdir/$soname.def; + else + echo EXPORTS > $output_objdir/$soname.def; + cat $export_symbols >> $output_objdir/$soname.def; + fi~ + $CC -shared $output_objdir/$soname.def $libobjs $deplibs $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib' + else + ld_shlibs=no + fi + ;; + + haiku*) + archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + link_all_deplibs=yes + ;; + + interix[3-9]*) + hardcode_direct=no + hardcode_shlibpath_var=no + hardcode_libdir_flag_spec='${wl}-rpath,$libdir' + export_dynamic_flag_spec='${wl}-E' + # Hack: On Interix 3.x, we cannot compile PIC because of a broken gcc. + # Instead, shared libraries are loaded at an image base (0x10000000 by + # default) and relocated if they conflict, which is a slow very memory + # consuming and fragmenting process. To avoid this, we pick a random, + # 256 KiB-aligned image base between 0x50000000 and 0x6FFC0000 at link + # time. Moving up from 0x10000000 also allows more sbrk(2) space. + archive_cmds='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib' + archive_expsym_cmds='sed "s,^,_," $export_symbols >$output_objdir/$soname.expsym~$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--retain-symbols-file,$output_objdir/$soname.expsym ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib' + ;; + + gnu* | linux* | tpf* | k*bsd*-gnu | kopensolaris*-gnu) + tmp_diet=no + if test "$host_os" = linux-dietlibc; then + case $cc_basename in + diet\ *) tmp_diet=yes;; # linux-dietlibc with static linking (!diet-dyn) + esac + fi + if $LD --help 2>&1 | $EGREP ': supported targets:.* elf' > /dev/null \ + && test "$tmp_diet" = no + then + tmp_addflag=' $pic_flag' + tmp_sharedflag='-shared' + case $cc_basename,$host_cpu in + pgcc*) # Portland Group C compiler + whole_archive_flag_spec='${wl}--whole-archive`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' + tmp_addflag=' $pic_flag' + ;; + pgf77* | pgf90* | pgf95* | pgfortran*) + # Portland Group f77 and f90 compilers + whole_archive_flag_spec='${wl}--whole-archive`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' + tmp_addflag=' $pic_flag -Mnomain' ;; + ecc*,ia64* | icc*,ia64*) # Intel C compiler on ia64 + tmp_addflag=' -i_dynamic' ;; + efc*,ia64* | ifort*,ia64*) # Intel Fortran compiler on ia64 + tmp_addflag=' -i_dynamic -nofor_main' ;; + ifc* | ifort*) # Intel Fortran compiler + tmp_addflag=' -nofor_main' ;; + lf95*) # Lahey Fortran 8.1 + whole_archive_flag_spec= + tmp_sharedflag='--shared' ;; + xl[cC]* | bgxl[cC]* | mpixl[cC]*) # IBM XL C 8.0 on PPC (deal with xlf below) + tmp_sharedflag='-qmkshrobj' + tmp_addflag= ;; + nvcc*) # Cuda Compiler Driver 2.2 + whole_archive_flag_spec='${wl}--whole-archive`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' + compiler_needs_object=yes + ;; + esac + case `$CC -V 2>&1 | sed 5q` in + *Sun\ C*) # Sun C 5.9 + whole_archive_flag_spec='${wl}--whole-archive`new_convenience=; for conv in $convenience\"\"; do test -z \"$conv\" || new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' + compiler_needs_object=yes + tmp_sharedflag='-G' ;; + *Sun\ F*) # Sun Fortran 8.3 + tmp_sharedflag='-G' ;; + esac + archive_cmds='$CC '"$tmp_sharedflag""$tmp_addflag"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + + if test "x$supports_anon_versioning" = xyes; then + archive_expsym_cmds='echo "{ global:" > $output_objdir/$libname.ver~ + cat $export_symbols | sed -e "s/\(.*\)/\1;/" >> $output_objdir/$libname.ver~ + echo "local: *; };" >> $output_objdir/$libname.ver~ + $CC '"$tmp_sharedflag""$tmp_addflag"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-version-script ${wl}$output_objdir/$libname.ver -o $lib' + fi + + case $cc_basename in + xlf* | bgf* | bgxlf* | mpixlf*) + # IBM XL Fortran 10.1 on PPC cannot create shared libs itself + whole_archive_flag_spec='--whole-archive$convenience --no-whole-archive' + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + archive_cmds='$LD -shared $libobjs $deplibs $linker_flags -soname $soname -o $lib' + if test "x$supports_anon_versioning" = xyes; then + archive_expsym_cmds='echo "{ global:" > $output_objdir/$libname.ver~ + cat $export_symbols | sed -e "s/\(.*\)/\1;/" >> $output_objdir/$libname.ver~ + echo "local: *; };" >> $output_objdir/$libname.ver~ + $LD -shared $libobjs $deplibs $linker_flags -soname $soname -version-script $output_objdir/$libname.ver -o $lib' + fi + ;; + esac + else + ld_shlibs=no + fi + ;; + + netbsd*) + if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then + archive_cmds='$LD -Bshareable $libobjs $deplibs $linker_flags -o $lib' + wlarc= + else + archive_cmds='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + archive_expsym_cmds='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' + fi + ;; + + solaris*) + if $LD -v 2>&1 | $GREP 'BFD 2\.8' > /dev/null; then + ld_shlibs=no + cat <<_LT_EOF 1>&2 + +*** Warning: The releases 2.8.* of the GNU linker cannot reliably +*** create shared libraries on Solaris systems. Therefore, libtool +*** is disabling shared libraries support. We urge you to upgrade GNU +*** binutils to release 2.9.1 or newer. Another option is to modify +*** your PATH or compiler configuration so that the native linker is +*** used, and then restart. + +_LT_EOF + elif $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then + archive_cmds='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + archive_expsym_cmds='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' + else + ld_shlibs=no + fi + ;; + + sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX*) + case `$LD -v 2>&1` in + *\ [01].* | *\ 2.[0-9].* | *\ 2.1[0-5].*) + ld_shlibs=no + cat <<_LT_EOF 1>&2 + +*** Warning: Releases of the GNU linker prior to 2.16.91.0.3 can not +*** reliably create shared libraries on SCO systems. Therefore, libtool +*** is disabling shared libraries support. We urge you to upgrade GNU +*** binutils to release 2.16.91.0.3 or newer. Another option is to modify +*** your PATH or compiler configuration so that the native linker is +*** used, and then restart. + +_LT_EOF + ;; + *) + # For security reasons, it is highly recommended that you always + # use absolute paths for naming shared libraries, and exclude the + # DT_RUNPATH tag from executables and libraries. But doing so + # requires that you compile everything twice, which is a pain. + if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' + else + ld_shlibs=no + fi + ;; + esac + ;; + + sunos4*) + archive_cmds='$LD -assert pure-text -Bshareable -o $lib $libobjs $deplibs $linker_flags' + wlarc= + hardcode_direct=yes + hardcode_shlibpath_var=no + ;; + + *) + if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then + archive_cmds='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + archive_expsym_cmds='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' + else + ld_shlibs=no + fi + ;; + esac + + if test "$ld_shlibs" = no; then + runpath_var= + hardcode_libdir_flag_spec= + export_dynamic_flag_spec= + whole_archive_flag_spec= + fi + else + # PORTME fill in a description of your system's linker (not GNU ld) + case $host_os in + aix3*) + allow_undefined_flag=unsupported + always_export_symbols=yes + archive_expsym_cmds='$LD -o $output_objdir/$soname $libobjs $deplibs $linker_flags -bE:$export_symbols -T512 -H512 -bM:SRE~$AR $AR_FLAGS $lib $output_objdir/$soname' + # Note: this linker hardcodes the directories in LIBPATH if there + # are no directories specified by -L. + hardcode_minus_L=yes + if test "$GCC" = yes && test -z "$lt_prog_compiler_static"; then + # Neither direct hardcoding nor static linking is supported with a + # broken collect2. + hardcode_direct=unsupported + fi + ;; + + aix[4-9]*) + if test "$host_cpu" = ia64; then + # On IA64, the linker does run time linking by default, so we don't + # have to do anything special. + aix_use_runtimelinking=no + exp_sym_flag='-Bexport' + no_entry_flag="" + else + # If we're using GNU nm, then we don't want the "-C" option. + # -C means demangle to AIX nm, but means don't demangle with GNU nm + # Also, AIX nm treats weak defined symbols like other global + # defined symbols, whereas GNU nm marks them as "W". + if $NM -V 2>&1 | $GREP 'GNU' > /dev/null; then + export_symbols_cmds='$NM -Bpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B") || (\$ 2 == "W")) && (substr(\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols' + else + export_symbols_cmds='$NM -BCpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B")) && (substr(\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols' + fi + aix_use_runtimelinking=no + + # Test if we are trying to use run time linking or normal + # AIX style linking. If -brtl is somewhere in LDFLAGS, we + # need to do runtime linking. + case $host_os in aix4.[23]|aix4.[23].*|aix[5-9]*) + for ld_flag in $LDFLAGS; do + if (test $ld_flag = "-brtl" || test $ld_flag = "-Wl,-brtl"); then + aix_use_runtimelinking=yes + break + fi + done + ;; + esac + + exp_sym_flag='-bexport' + no_entry_flag='-bnoentry' + fi + + # When large executables or shared objects are built, AIX ld can + # have problems creating the table of contents. If linking a library + # or program results in "error TOC overflow" add -mminimal-toc to + # CXXFLAGS/CFLAGS for g++/gcc. In the cases where that is not + # enough to fix the problem, add -Wl,-bbigtoc to LDFLAGS. + + archive_cmds='' + hardcode_direct=yes + hardcode_direct_absolute=yes + hardcode_libdir_separator=':' + link_all_deplibs=yes + file_list_spec='${wl}-f,' + + if test "$GCC" = yes; then + case $host_os in aix4.[012]|aix4.[012].*) + # We only want to do this on AIX 4.2 and lower, the check + # below for broken collect2 doesn't work under 4.3+ + collect2name=`${CC} -print-prog-name=collect2` + if test -f "$collect2name" && + strings "$collect2name" | $GREP resolve_lib_name >/dev/null + then + # We have reworked collect2 + : + else + # We have old collect2 + hardcode_direct=unsupported + # It fails to find uninstalled libraries when the uninstalled + # path is not listed in the libpath. Setting hardcode_minus_L + # to unsupported forces relinking + hardcode_minus_L=yes + hardcode_libdir_flag_spec='-L$libdir' + hardcode_libdir_separator= + fi + ;; + esac + shared_flag='-shared' + if test "$aix_use_runtimelinking" = yes; then + shared_flag="$shared_flag "'${wl}-G' + fi + else + # not using gcc + if test "$host_cpu" = ia64; then + # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release + # chokes on -Wl,-G. The following line is correct: + shared_flag='-G' + else + if test "$aix_use_runtimelinking" = yes; then + shared_flag='${wl}-G' + else + shared_flag='${wl}-bM:SRE' + fi + fi + fi + + export_dynamic_flag_spec='${wl}-bexpall' + # It seems that -bexpall does not export symbols beginning with + # underscore (_), so it is better to generate a list of symbols to export. + always_export_symbols=yes + if test "$aix_use_runtimelinking" = yes; then + # Warning - without using the other runtime loading flags (-brtl), + # -berok will link without error, but may produce a broken library. + allow_undefined_flag='-berok' + # Determine the default libpath from the value encoded in an + # empty executable. + if test "${lt_cv_aix_libpath+set}" = set; then + aix_libpath=$lt_cv_aix_libpath +else + if ${lt_cv_aix_libpath_+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + + lt_aix_libpath_sed=' + /Import File Strings/,/^$/ { + /^0/ { + s/^0 *\([^ ]*\) *$/\1/ + p + } + }' + lt_cv_aix_libpath_=`dump -H conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` + # Check for a 64-bit object if we didn't find anything. + if test -z "$lt_cv_aix_libpath_"; then + lt_cv_aix_libpath_=`dump -HX64 conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` + fi +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + if test -z "$lt_cv_aix_libpath_"; then + lt_cv_aix_libpath_="/usr/lib:/lib" + fi + +fi + + aix_libpath=$lt_cv_aix_libpath_ +fi + + hardcode_libdir_flag_spec='${wl}-blibpath:$libdir:'"$aix_libpath" + archive_expsym_cmds='$CC -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_flag}" != "x"; then func_echo_all "${wl}${allow_undefined_flag}"; else :; fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" + else + if test "$host_cpu" = ia64; then + hardcode_libdir_flag_spec='${wl}-R $libdir:/usr/lib:/lib' + allow_undefined_flag="-z nodefs" + archive_expsym_cmds="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undefined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" + else + # Determine the default libpath from the value encoded in an + # empty executable. + if test "${lt_cv_aix_libpath+set}" = set; then + aix_libpath=$lt_cv_aix_libpath +else + if ${lt_cv_aix_libpath_+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + + lt_aix_libpath_sed=' + /Import File Strings/,/^$/ { + /^0/ { + s/^0 *\([^ ]*\) *$/\1/ + p + } + }' + lt_cv_aix_libpath_=`dump -H conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` + # Check for a 64-bit object if we didn't find anything. + if test -z "$lt_cv_aix_libpath_"; then + lt_cv_aix_libpath_=`dump -HX64 conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` + fi +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + if test -z "$lt_cv_aix_libpath_"; then + lt_cv_aix_libpath_="/usr/lib:/lib" + fi + +fi + + aix_libpath=$lt_cv_aix_libpath_ +fi + + hardcode_libdir_flag_spec='${wl}-blibpath:$libdir:'"$aix_libpath" + # Warning - without using the other run time loading flags, + # -berok will link without error, but may produce a broken library. + no_undefined_flag=' ${wl}-bernotok' + allow_undefined_flag=' ${wl}-berok' + if test "$with_gnu_ld" = yes; then + # We only use this code for GNU lds that support --whole-archive. + whole_archive_flag_spec='${wl}--whole-archive$convenience ${wl}--no-whole-archive' + else + # Exported symbols can be pulled into shared objects from archives + whole_archive_flag_spec='$convenience' + fi + archive_cmds_need_lc=yes + # This is similar to how AIX traditionally builds its shared libraries. + archive_expsym_cmds="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${allow_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output_objdir/$soname' + fi + fi + ;; + + amigaos*) + case $host_cpu in + powerpc) + # see comment about AmigaOS4 .so support + archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + archive_expsym_cmds='' + ;; + m68k) + archive_cmds='$RM $output_objdir/a2ixlibrary.data~$ECHO "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$ECHO "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$ECHO "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$ECHO "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)' + hardcode_libdir_flag_spec='-L$libdir' + hardcode_minus_L=yes + ;; + esac + ;; + + bsdi[45]*) + export_dynamic_flag_spec=-rdynamic + ;; + + cygwin* | mingw* | pw32* | cegcc*) + # When not using gcc, we currently assume that we are using + # Microsoft Visual C++. + # hardcode_libdir_flag_spec is actually meaningless, as there is + # no search path for DLLs. + case $cc_basename in + cl*) + # Native MSVC + hardcode_libdir_flag_spec=' ' + allow_undefined_flag=unsupported + always_export_symbols=yes + file_list_spec='@' + # Tell ltmain to make .lib files, not .a files. + libext=lib + # Tell ltmain to make .dll files, not .so files. + shrext_cmds=".dll" + # FIXME: Setting linknames here is a bad hack. + archive_cmds='$CC -o $output_objdir/$soname $libobjs $compiler_flags $deplibs -Wl,-dll~linknames=' + archive_expsym_cmds='if test "x`$SED 1q $export_symbols`" = xEXPORTS; then + sed -n -e 's/\\\\\\\(.*\\\\\\\)/-link\\\ -EXPORT:\\\\\\\1/' -e '1\\\!p' < $export_symbols > $output_objdir/$soname.exp; + else + sed -e 's/\\\\\\\(.*\\\\\\\)/-link\\\ -EXPORT:\\\\\\\1/' < $export_symbols > $output_objdir/$soname.exp; + fi~ + $CC -o $tool_output_objdir$soname $libobjs $compiler_flags $deplibs "@$tool_output_objdir$soname.exp" -Wl,-DLL,-IMPLIB:"$tool_output_objdir$libname.dll.lib"~ + linknames=' + # The linker will not automatically build a static lib if we build a DLL. + # _LT_TAGVAR(old_archive_from_new_cmds, )='true' + enable_shared_with_static_runtimes=yes + exclude_expsyms='_NULL_IMPORT_DESCRIPTOR|_IMPORT_DESCRIPTOR_.*' + export_symbols_cmds='$NM $libobjs $convenience | $global_symbol_pipe | $SED -e '\''/^[BCDGRS][ ]/s/.*[ ]\([^ ]*\)/\1,DATA/'\'' | $SED -e '\''/^[AITW][ ]/s/.*[ ]//'\'' | sort | uniq > $export_symbols' + # Don't use ranlib + old_postinstall_cmds='chmod 644 $oldlib' + postlink_cmds='lt_outputfile="@OUTPUT@"~ + lt_tool_outputfile="@TOOL_OUTPUT@"~ + case $lt_outputfile in + *.exe|*.EXE) ;; + *) + lt_outputfile="$lt_outputfile.exe" + lt_tool_outputfile="$lt_tool_outputfile.exe" + ;; + esac~ + if test "$MANIFEST_TOOL" != ":" && test -f "$lt_outputfile.manifest"; then + $MANIFEST_TOOL -manifest "$lt_tool_outputfile.manifest" -outputresource:"$lt_tool_outputfile" || exit 1; + $RM "$lt_outputfile.manifest"; + fi' + ;; + *) + # Assume MSVC wrapper + hardcode_libdir_flag_spec=' ' + allow_undefined_flag=unsupported + # Tell ltmain to make .lib files, not .a files. + libext=lib + # Tell ltmain to make .dll files, not .so files. + shrext_cmds=".dll" + # FIXME: Setting linknames here is a bad hack. + archive_cmds='$CC -o $lib $libobjs $compiler_flags `func_echo_all "$deplibs" | $SED '\''s/ -lc$//'\''` -link -dll~linknames=' + # The linker will automatically build a .lib file if we build a DLL. + old_archive_from_new_cmds='true' + # FIXME: Should let the user specify the lib program. + old_archive_cmds='lib -OUT:$oldlib$oldobjs$old_deplibs' + enable_shared_with_static_runtimes=yes + ;; + esac + ;; + + darwin* | rhapsody*) + + + archive_cmds_need_lc=no + hardcode_direct=no + hardcode_automatic=yes + hardcode_shlibpath_var=unsupported + if test "$lt_cv_ld_force_load" = "yes"; then + whole_archive_flag_spec='`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience ${wl}-force_load,$conv\"; done; func_echo_all \"$new_convenience\"`' + + else + whole_archive_flag_spec='' + fi + link_all_deplibs=yes + allow_undefined_flag="$_lt_dar_allow_undefined" + case $cc_basename in + ifort*) _lt_dar_can_shared=yes ;; + *) _lt_dar_can_shared=$GCC ;; + esac + if test "$_lt_dar_can_shared" = "yes"; then + output_verbose_link_cmd=func_echo_all + archive_cmds="\$CC -dynamiclib \$allow_undefined_flag -o \$lib \$libobjs \$deplibs \$compiler_flags -install_name \$rpath/\$soname \$verstring $_lt_dar_single_mod${_lt_dsymutil}" + module_cmds="\$CC \$allow_undefined_flag -o \$lib -bundle \$libobjs \$deplibs \$compiler_flags${_lt_dsymutil}" + archive_expsym_cmds="sed 's,^,_,' < \$export_symbols > \$output_objdir/\${libname}-symbols.expsym~\$CC -dynamiclib \$allow_undefined_flag -o \$lib \$libobjs \$deplibs \$compiler_flags -install_name \$rpath/\$soname \$verstring ${_lt_dar_single_mod}${_lt_dar_export_syms}${_lt_dsymutil}" + module_expsym_cmds="sed -e 's,^,_,' < \$export_symbols > \$output_objdir/\${libname}-symbols.expsym~\$CC \$allow_undefined_flag -o \$lib -bundle \$libobjs \$deplibs \$compiler_flags${_lt_dar_export_syms}${_lt_dsymutil}" + + else + ld_shlibs=no + fi + + ;; + + dgux*) + archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' + hardcode_libdir_flag_spec='-L$libdir' + hardcode_shlibpath_var=no + ;; + + # FreeBSD 2.2.[012] allows us to include c++rt0.o to get C++ constructor + # support. Future versions do this automatically, but an explicit c++rt0.o + # does not break anything, and helps significantly (at the cost of a little + # extra space). + freebsd2.2*) + archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags /usr/lib/c++rt0.o' + hardcode_libdir_flag_spec='-R$libdir' + hardcode_direct=yes + hardcode_shlibpath_var=no + ;; + + # Unfortunately, older versions of FreeBSD 2 do not have this feature. + freebsd2.*) + archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' + hardcode_direct=yes + hardcode_minus_L=yes + hardcode_shlibpath_var=no + ;; + + # FreeBSD 3 and greater uses gcc -shared to do shared libraries. + freebsd* | dragonfly*) + archive_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags' + hardcode_libdir_flag_spec='-R$libdir' + hardcode_direct=yes + hardcode_shlibpath_var=no + ;; + + hpux9*) + if test "$GCC" = yes; then + archive_cmds='$RM $output_objdir/$soname~$CC -shared $pic_flag ${wl}+b ${wl}$install_libdir -o $output_objdir/$soname $libobjs $deplibs $compiler_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib' + else + archive_cmds='$RM $output_objdir/$soname~$LD -b +b $install_libdir -o $output_objdir/$soname $libobjs $deplibs $linker_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib' + fi + hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir' + hardcode_libdir_separator=: + hardcode_direct=yes + + # hardcode_minus_L: Not really in the search PATH, + # but as the default location of the library. + hardcode_minus_L=yes + export_dynamic_flag_spec='${wl}-E' + ;; + + hpux10*) + if test "$GCC" = yes && test "$with_gnu_ld" = no; then + archive_cmds='$CC -shared $pic_flag ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' + else + archive_cmds='$LD -b +h $soname +b $install_libdir -o $lib $libobjs $deplibs $linker_flags' + fi + if test "$with_gnu_ld" = no; then + hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir' + hardcode_libdir_separator=: + hardcode_direct=yes + hardcode_direct_absolute=yes + export_dynamic_flag_spec='${wl}-E' + # hardcode_minus_L: Not really in the search PATH, + # but as the default location of the library. + hardcode_minus_L=yes + fi + ;; + + hpux11*) + if test "$GCC" = yes && test "$with_gnu_ld" = no; then + case $host_cpu in + hppa*64*) + archive_cmds='$CC -shared ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' + ;; + ia64*) + archive_cmds='$CC -shared $pic_flag ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags' + ;; + *) + archive_cmds='$CC -shared $pic_flag ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' + ;; + esac + else + case $host_cpu in + hppa*64*) + archive_cmds='$CC -b ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' + ;; + ia64*) + archive_cmds='$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags' + ;; + *) + + # Older versions of the 11.00 compiler do not understand -b yet + # (HP92453-01 A.11.01.20 doesn't, HP92453-01 B.11.X.35175-35176.GP does) + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $CC understands -b" >&5 +$as_echo_n "checking if $CC understands -b... " >&6; } +if ${lt_cv_prog_compiler__b+:} false; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_prog_compiler__b=no + save_LDFLAGS="$LDFLAGS" + LDFLAGS="$LDFLAGS -b" + echo "$lt_simple_link_test_code" > conftest.$ac_ext + if (eval $ac_link 2>conftest.err) && test -s conftest$ac_exeext; then + # The linker can only warn and ignore the option if not recognized + # So say no if there are warnings + if test -s conftest.err; then + # Append any errors to the config.log. + cat conftest.err 1>&5 + $ECHO "$_lt_linker_boilerplate" | $SED '/^$/d' > conftest.exp + $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2 + if diff conftest.exp conftest.er2 >/dev/null; then + lt_cv_prog_compiler__b=yes + fi + else + lt_cv_prog_compiler__b=yes + fi + fi + $RM -r conftest* + LDFLAGS="$save_LDFLAGS" + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler__b" >&5 +$as_echo "$lt_cv_prog_compiler__b" >&6; } + +if test x"$lt_cv_prog_compiler__b" = xyes; then + archive_cmds='$CC -b ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' +else + archive_cmds='$LD -b +h $soname +b $install_libdir -o $lib $libobjs $deplibs $linker_flags' +fi + + ;; + esac + fi + if test "$with_gnu_ld" = no; then + hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir' + hardcode_libdir_separator=: + + case $host_cpu in + hppa*64*|ia64*) + hardcode_direct=no + hardcode_shlibpath_var=no + ;; + *) + hardcode_direct=yes + hardcode_direct_absolute=yes + export_dynamic_flag_spec='${wl}-E' + + # hardcode_minus_L: Not really in the search PATH, + # but as the default location of the library. + hardcode_minus_L=yes + ;; + esac + fi + ;; + + irix5* | irix6* | nonstopux*) + if test "$GCC" = yes; then + archive_cmds='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' + # Try to use the -exported_symbol ld option, if it does not + # work, assume that -exports_file does not work either and + # implicitly export all symbols. + # This should be the same for all languages, so no per-tag cache variable. + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the $host_os linker accepts -exported_symbol" >&5 +$as_echo_n "checking whether the $host_os linker accepts -exported_symbol... " >&6; } +if ${lt_cv_irix_exported_symbol+:} false; then : + $as_echo_n "(cached) " >&6 +else + save_LDFLAGS="$LDFLAGS" + LDFLAGS="$LDFLAGS -shared ${wl}-exported_symbol ${wl}foo ${wl}-update_registry ${wl}/dev/null" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +int foo (void) { return 0; } +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + lt_cv_irix_exported_symbol=yes +else + lt_cv_irix_exported_symbol=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + LDFLAGS="$save_LDFLAGS" +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_irix_exported_symbol" >&5 +$as_echo "$lt_cv_irix_exported_symbol" >&6; } + if test "$lt_cv_irix_exported_symbol" = yes; then + archive_expsym_cmds='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations ${wl}-exports_file ${wl}$export_symbols -o $lib' + fi + else + archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib' + archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -exports_file $export_symbols -o $lib' + fi + archive_cmds_need_lc='no' + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + hardcode_libdir_separator=: + inherit_rpath=yes + link_all_deplibs=yes + ;; + + netbsd*) + if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then + archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' # a.out + else + archive_cmds='$LD -shared -o $lib $libobjs $deplibs $linker_flags' # ELF + fi + hardcode_libdir_flag_spec='-R$libdir' + hardcode_direct=yes + hardcode_shlibpath_var=no + ;; + + newsos6) + archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' + hardcode_direct=yes + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + hardcode_libdir_separator=: + hardcode_shlibpath_var=no + ;; + + *nto* | *qnx*) + ;; + + openbsd*) + if test -f /usr/libexec/ld.so; then + hardcode_direct=yes + hardcode_shlibpath_var=no + hardcode_direct_absolute=yes + if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then + archive_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-retain-symbols-file,$export_symbols' + hardcode_libdir_flag_spec='${wl}-rpath,$libdir' + export_dynamic_flag_spec='${wl}-E' + else + case $host_os in + openbsd[01].* | openbsd2.[0-7] | openbsd2.[0-7].*) + archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' + hardcode_libdir_flag_spec='-R$libdir' + ;; + *) + archive_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags' + hardcode_libdir_flag_spec='${wl}-rpath,$libdir' + ;; + esac + fi + else + ld_shlibs=no + fi + ;; + + os2*) + hardcode_libdir_flag_spec='-L$libdir' + hardcode_minus_L=yes + allow_undefined_flag=unsupported + archive_cmds='$ECHO "LIBRARY $libname INITINSTANCE" > $output_objdir/$libname.def~$ECHO "DESCRIPTION \"$libname\"" >> $output_objdir/$libname.def~echo DATA >> $output_objdir/$libname.def~echo " SINGLE NONSHARED" >> $output_objdir/$libname.def~echo EXPORTS >> $output_objdir/$libname.def~emxexp $libobjs >> $output_objdir/$libname.def~$CC -Zdll -Zcrtdll -o $lib $libobjs $deplibs $compiler_flags $output_objdir/$libname.def' + old_archive_from_new_cmds='emximp -o $output_objdir/$libname.a $output_objdir/$libname.def' + ;; + + osf3*) + if test "$GCC" = yes; then + allow_undefined_flag=' ${wl}-expect_unresolved ${wl}\*' + archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' + else + allow_undefined_flag=' -expect_unresolved \*' + archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib' + fi + archive_cmds_need_lc='no' + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + hardcode_libdir_separator=: + ;; + + osf4* | osf5*) # as osf3* with the addition of -msym flag + if test "$GCC" = yes; then + allow_undefined_flag=' ${wl}-expect_unresolved ${wl}\*' + archive_cmds='$CC -shared${allow_undefined_flag} $pic_flag $libobjs $deplibs $compiler_flags ${wl}-msym ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + else + allow_undefined_flag=' -expect_unresolved \*' + archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags -msym -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib' + archive_expsym_cmds='for i in `cat $export_symbols`; do printf "%s %s\\n" -exported_symbol "\$i" >> $lib.exp; done; printf "%s\\n" "-hidden">> $lib.exp~ + $CC -shared${allow_undefined_flag} ${wl}-input ${wl}$lib.exp $compiler_flags $libobjs $deplibs -soname $soname `test -n "$verstring" && $ECHO "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib~$RM $lib.exp' + + # Both c and cxx compiler support -rpath directly + hardcode_libdir_flag_spec='-rpath $libdir' + fi + archive_cmds_need_lc='no' + hardcode_libdir_separator=: + ;; + + solaris*) + no_undefined_flag=' -z defs' + if test "$GCC" = yes; then + wlarc='${wl}' + archive_cmds='$CC -shared $pic_flag ${wl}-z ${wl}text ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~ + $CC -shared $pic_flag ${wl}-z ${wl}text ${wl}-M ${wl}$lib.exp ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags~$RM $lib.exp' + else + case `$CC -V 2>&1` in + *"Compilers 5.0"*) + wlarc='' + archive_cmds='$LD -G${allow_undefined_flag} -h $soname -o $lib $libobjs $deplibs $linker_flags' + archive_expsym_cmds='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~ + $LD -G${allow_undefined_flag} -M $lib.exp -h $soname -o $lib $libobjs $deplibs $linker_flags~$RM $lib.exp' + ;; + *) + wlarc='${wl}' + archive_cmds='$CC -G${allow_undefined_flag} -h $soname -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~ + $CC -G${allow_undefined_flag} -M $lib.exp -h $soname -o $lib $libobjs $deplibs $compiler_flags~$RM $lib.exp' + ;; + esac + fi + hardcode_libdir_flag_spec='-R$libdir' + hardcode_shlibpath_var=no + case $host_os in + solaris2.[0-5] | solaris2.[0-5].*) ;; + *) + # The compiler driver will combine and reorder linker options, + # but understands `-z linker_flag'. GCC discards it without `$wl', + # but is careful enough not to reorder. + # Supported since Solaris 2.6 (maybe 2.5.1?) + if test "$GCC" = yes; then + whole_archive_flag_spec='${wl}-z ${wl}allextract$convenience ${wl}-z ${wl}defaultextract' + else + whole_archive_flag_spec='-z allextract$convenience -z defaultextract' + fi + ;; + esac + link_all_deplibs=yes + ;; + + sunos4*) + if test "x$host_vendor" = xsequent; then + # Use $CC to link under sequent, because it throws in some extra .o + # files that make .init and .fini sections work. + archive_cmds='$CC -G ${wl}-h $soname -o $lib $libobjs $deplibs $compiler_flags' + else + archive_cmds='$LD -assert pure-text -Bstatic -o $lib $libobjs $deplibs $linker_flags' + fi + hardcode_libdir_flag_spec='-L$libdir' + hardcode_direct=yes + hardcode_minus_L=yes + hardcode_shlibpath_var=no + ;; + + sysv4) + case $host_vendor in + sni) + archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' + hardcode_direct=yes # is this really true??? + ;; + siemens) + ## LD is ld it makes a PLAMLIB + ## CC just makes a GrossModule. + archive_cmds='$LD -G -o $lib $libobjs $deplibs $linker_flags' + reload_cmds='$CC -r -o $output$reload_objs' + hardcode_direct=no + ;; + motorola) + archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' + hardcode_direct=no #Motorola manual says yes, but my tests say they lie + ;; + esac + runpath_var='LD_RUN_PATH' + hardcode_shlibpath_var=no + ;; + + sysv4.3*) + archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' + hardcode_shlibpath_var=no + export_dynamic_flag_spec='-Bexport' + ;; + + sysv4*MP*) + if test -d /usr/nec; then + archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' + hardcode_shlibpath_var=no + runpath_var=LD_RUN_PATH + hardcode_runpath_var=yes + ld_shlibs=yes + fi + ;; + + sysv4*uw2* | sysv5OpenUNIX* | sysv5UnixWare7.[01].[10]* | unixware7* | sco3.2v5.0.[024]*) + no_undefined_flag='${wl}-z,text' + archive_cmds_need_lc=no + hardcode_shlibpath_var=no + runpath_var='LD_RUN_PATH' + + if test "$GCC" = yes; then + archive_cmds='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + else + archive_cmds='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + fi + ;; + + sysv5* | sco3.2v5* | sco5v6*) + # Note: We can NOT use -z defs as we might desire, because we do not + # link with -lc, and that would cause any symbols used from libc to + # always be unresolved, which means just about no library would + # ever link correctly. If we're not using GNU ld we use -z text + # though, which does catch some bad symbols but isn't as heavy-handed + # as -z defs. + no_undefined_flag='${wl}-z,text' + allow_undefined_flag='${wl}-z,nodefs' + archive_cmds_need_lc=no + hardcode_shlibpath_var=no + hardcode_libdir_flag_spec='${wl}-R,$libdir' + hardcode_libdir_separator=':' + link_all_deplibs=yes + export_dynamic_flag_spec='${wl}-Bexport' + runpath_var='LD_RUN_PATH' + + if test "$GCC" = yes; then + archive_cmds='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + else + archive_cmds='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + fi + ;; + + uts4*) + archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' + hardcode_libdir_flag_spec='-L$libdir' + hardcode_shlibpath_var=no + ;; + + *) + ld_shlibs=no + ;; + esac + + if test x$host_vendor = xsni; then + case $host in + sysv4 | sysv4.2uw2* | sysv4.3* | sysv5*) + export_dynamic_flag_spec='${wl}-Blargedynsym' + ;; + esac + fi + fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ld_shlibs" >&5 +$as_echo "$ld_shlibs" >&6; } +test "$ld_shlibs" = no && can_build_shared=no + +with_gnu_ld=$with_gnu_ld + + + + + + + + + + + + + + + +# +# Do we need to explicitly link libc? +# +case "x$archive_cmds_need_lc" in +x|xyes) + # Assume -lc should be added + archive_cmds_need_lc=yes + + if test "$enable_shared" = yes && test "$GCC" = yes; then + case $archive_cmds in + *'~'*) + # FIXME: we may have to deal with multi-command sequences. + ;; + '$CC '*) + # Test whether the compiler implicitly links with -lc since on some + # systems, -lgcc has to come before -lc. If gcc already passes -lc + # to ld, don't add -lc before -lgcc. + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether -lc should be explicitly linked in" >&5 +$as_echo_n "checking whether -lc should be explicitly linked in... " >&6; } +if ${lt_cv_archive_cmds_need_lc+:} false; then : + $as_echo_n "(cached) " >&6 +else + $RM conftest* + echo "$lt_simple_compile_test_code" > conftest.$ac_ext + + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 + (eval $ac_compile) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } 2>conftest.err; then + soname=conftest + lib=conftest + libobjs=conftest.$ac_objext + deplibs= + wl=$lt_prog_compiler_wl + pic_flag=$lt_prog_compiler_pic + compiler_flags=-v + linker_flags=-v + verstring= + output_objdir=. + libname=conftest + lt_save_allow_undefined_flag=$allow_undefined_flag + allow_undefined_flag= + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$archive_cmds 2\>\&1 \| $GREP \" -lc \" \>/dev/null 2\>\&1\""; } >&5 + (eval $archive_cmds 2\>\&1 \| $GREP \" -lc \" \>/dev/null 2\>\&1) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + then + lt_cv_archive_cmds_need_lc=no + else + lt_cv_archive_cmds_need_lc=yes + fi + allow_undefined_flag=$lt_save_allow_undefined_flag + else + cat conftest.err 1>&5 + fi + $RM conftest* + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_archive_cmds_need_lc" >&5 +$as_echo "$lt_cv_archive_cmds_need_lc" >&6; } + archive_cmds_need_lc=$lt_cv_archive_cmds_need_lc + ;; + esac + fi + ;; +esac + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking dynamic linker characteristics" >&5 +$as_echo_n "checking dynamic linker characteristics... " >&6; } + +if test "$GCC" = yes; then + case $host_os in + darwin*) lt_awk_arg="/^libraries:/,/LR/" ;; + *) lt_awk_arg="/^libraries:/" ;; + esac + case $host_os in + mingw* | cegcc*) lt_sed_strip_eq="s,=\([A-Za-z]:\),\1,g" ;; + *) lt_sed_strip_eq="s,=/,/,g" ;; + esac + lt_search_path_spec=`$CC -print-search-dirs | awk $lt_awk_arg | $SED -e "s/^libraries://" -e $lt_sed_strip_eq` + case $lt_search_path_spec in + *\;*) + # if the path contains ";" then we assume it to be the separator + # otherwise default to the standard path separator (i.e. ":") - it is + # assumed that no part of a normal pathname contains ";" but that should + # okay in the real world where ";" in dirpaths is itself problematic. + lt_search_path_spec=`$ECHO "$lt_search_path_spec" | $SED 's/;/ /g'` + ;; + *) + lt_search_path_spec=`$ECHO "$lt_search_path_spec" | $SED "s/$PATH_SEPARATOR/ /g"` + ;; + esac + # Ok, now we have the path, separated by spaces, we can step through it + # and add multilib dir if necessary. + lt_tmp_lt_search_path_spec= + lt_multi_os_dir=`$CC $CPPFLAGS $CFLAGS $LDFLAGS -print-multi-os-directory 2>/dev/null` + for lt_sys_path in $lt_search_path_spec; do + if test -d "$lt_sys_path/$lt_multi_os_dir"; then + lt_tmp_lt_search_path_spec="$lt_tmp_lt_search_path_spec $lt_sys_path/$lt_multi_os_dir" + else + test -d "$lt_sys_path" && \ + lt_tmp_lt_search_path_spec="$lt_tmp_lt_search_path_spec $lt_sys_path" + fi + done + lt_search_path_spec=`$ECHO "$lt_tmp_lt_search_path_spec" | awk ' +BEGIN {RS=" "; FS="/|\n";} { + lt_foo=""; + lt_count=0; + for (lt_i = NF; lt_i > 0; lt_i--) { + if ($lt_i != "" && $lt_i != ".") { + if ($lt_i == "..") { + lt_count++; + } else { + if (lt_count == 0) { + lt_foo="/" $lt_i lt_foo; + } else { + lt_count--; + } + } + } + } + if (lt_foo != "") { lt_freq[lt_foo]++; } + if (lt_freq[lt_foo] == 1) { print lt_foo; } +}'` + # AWK program above erroneously prepends '/' to C:/dos/paths + # for these hosts. + case $host_os in + mingw* | cegcc*) lt_search_path_spec=`$ECHO "$lt_search_path_spec" |\ + $SED 's,/\([A-Za-z]:\),\1,g'` ;; + esac + sys_lib_search_path_spec=`$ECHO "$lt_search_path_spec" | $lt_NL2SP` +else + sys_lib_search_path_spec="/lib /usr/lib /usr/local/lib" +fi +library_names_spec= +libname_spec='lib$name' +soname_spec= +shrext_cmds=".so" +postinstall_cmds= +postuninstall_cmds= +finish_cmds= +finish_eval= +shlibpath_var= +shlibpath_overrides_runpath=unknown +version_type=none +dynamic_linker="$host_os ld.so" +sys_lib_dlsearch_path_spec="/lib /usr/lib" +need_lib_prefix=unknown +hardcode_into_libs=no + +# when you set need_version to no, make sure it does not cause -set_version +# flags to be left without arguments +need_version=unknown + +case $host_os in +aix3*) + version_type=linux # correct to gnu/linux during the next big refactor + library_names_spec='${libname}${release}${shared_ext}$versuffix $libname.a' + shlibpath_var=LIBPATH + + # AIX 3 has no versioning support, so we append a major version to the name. + soname_spec='${libname}${release}${shared_ext}$major' + ;; + +aix[4-9]*) + version_type=linux # correct to gnu/linux during the next big refactor + need_lib_prefix=no + need_version=no + hardcode_into_libs=yes + if test "$host_cpu" = ia64; then + # AIX 5 supports IA64 + library_names_spec='${libname}${release}${shared_ext}$major ${libname}${release}${shared_ext}$versuffix $libname${shared_ext}' + shlibpath_var=LD_LIBRARY_PATH + else + # With GCC up to 2.95.x, collect2 would create an import file + # for dependence libraries. The import file would start with + # the line `#! .'. This would cause the generated library to + # depend on `.', always an invalid library. This was fixed in + # development snapshots of GCC prior to 3.0. + case $host_os in + aix4 | aix4.[01] | aix4.[01].*) + if { echo '#if __GNUC__ > 2 || (__GNUC__ == 2 && __GNUC_MINOR__ >= 97)' + echo ' yes ' + echo '#endif'; } | ${CC} -E - | $GREP yes > /dev/null; then + : + else + can_build_shared=no + fi + ;; + esac + # AIX (on Power*) has no versioning support, so currently we can not hardcode correct + # soname into executable. Probably we can add versioning support to + # collect2, so additional links can be useful in future. + if test "$aix_use_runtimelinking" = yes; then + # If using run time linking (on AIX 4.2 or later) use lib.so + # instead of lib.a to let people know that these are not + # typical AIX shared libraries. + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + else + # We preserve .a as extension for shared libraries through AIX4.2 + # and later when we are not doing run time linking. + library_names_spec='${libname}${release}.a $libname.a' + soname_spec='${libname}${release}${shared_ext}$major' + fi + shlibpath_var=LIBPATH + fi + ;; + +amigaos*) + case $host_cpu in + powerpc) + # Since July 2007 AmigaOS4 officially supports .so libraries. + # When compiling the executable, add -use-dynld -Lsobjs: to the compileline. + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + ;; + m68k) + library_names_spec='$libname.ixlibrary $libname.a' + # Create ${libname}_ixlibrary.a entries in /sys/libs. + finish_eval='for lib in `ls $libdir/*.ixlibrary 2>/dev/null`; do libname=`func_echo_all "$lib" | $SED '\''s%^.*/\([^/]*\)\.ixlibrary$%\1%'\''`; test $RM /sys/libs/${libname}_ixlibrary.a; $show "cd /sys/libs && $LN_S $lib ${libname}_ixlibrary.a"; cd /sys/libs && $LN_S $lib ${libname}_ixlibrary.a || exit 1; done' + ;; + esac + ;; + +beos*) + library_names_spec='${libname}${shared_ext}' + dynamic_linker="$host_os ld.so" + shlibpath_var=LIBRARY_PATH + ;; + +bsdi[45]*) + version_type=linux # correct to gnu/linux during the next big refactor + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + finish_cmds='PATH="\$PATH:/sbin" ldconfig $libdir' + shlibpath_var=LD_LIBRARY_PATH + sys_lib_search_path_spec="/shlib /usr/lib /usr/X11/lib /usr/contrib/lib /lib /usr/local/lib" + sys_lib_dlsearch_path_spec="/shlib /usr/lib /usr/local/lib" + # the default ld.so.conf also contains /usr/contrib/lib and + # /usr/X11R6/lib (/usr/X11 is a link to /usr/X11R6), but let us allow + # libtool to hard-code these into programs + ;; + +cygwin* | mingw* | pw32* | cegcc*) + version_type=windows + shrext_cmds=".dll" + need_version=no + need_lib_prefix=no + + case $GCC,$cc_basename in + yes,*) + # gcc + library_names_spec='$libname.dll.a' + # DLL is installed to $(libdir)/../bin by postinstall_cmds + postinstall_cmds='base_file=`basename \${file}`~ + dlpath=`$SHELL 2>&1 -c '\''. $dir/'\''\${base_file}'\''i; echo \$dlname'\''`~ + dldir=$destdir/`dirname \$dlpath`~ + test -d \$dldir || mkdir -p \$dldir~ + $install_prog $dir/$dlname \$dldir/$dlname~ + chmod a+x \$dldir/$dlname~ + if test -n '\''$stripme'\'' && test -n '\''$striplib'\''; then + eval '\''$striplib \$dldir/$dlname'\'' || exit \$?; + fi' + postuninstall_cmds='dldll=`$SHELL 2>&1 -c '\''. $file; echo \$dlname'\''`~ + dlpath=$dir/\$dldll~ + $RM \$dlpath' + shlibpath_overrides_runpath=yes + + case $host_os in + cygwin*) + # Cygwin DLLs use 'cyg' prefix rather than 'lib' + soname_spec='`echo ${libname} | sed -e 's/^lib/cyg/'``echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}' + + sys_lib_search_path_spec="$sys_lib_search_path_spec /usr/lib/w32api" + ;; + mingw* | cegcc*) + # MinGW DLLs use traditional 'lib' prefix + soname_spec='${libname}`echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}' + ;; + pw32*) + # pw32 DLLs use 'pw' prefix rather than 'lib' + library_names_spec='`echo ${libname} | sed -e 's/^lib/pw/'``echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}' + ;; + esac + dynamic_linker='Win32 ld.exe' + ;; + + *,cl*) + # Native MSVC + libname_spec='$name' + soname_spec='${libname}`echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}' + library_names_spec='${libname}.dll.lib' + + case $build_os in + mingw*) + sys_lib_search_path_spec= + lt_save_ifs=$IFS + IFS=';' + for lt_path in $LIB + do + IFS=$lt_save_ifs + # Let DOS variable expansion print the short 8.3 style file name. + lt_path=`cd "$lt_path" 2>/dev/null && cmd //C "for %i in (".") do @echo %~si"` + sys_lib_search_path_spec="$sys_lib_search_path_spec $lt_path" + done + IFS=$lt_save_ifs + # Convert to MSYS style. + sys_lib_search_path_spec=`$ECHO "$sys_lib_search_path_spec" | sed -e 's|\\\\|/|g' -e 's| \\([a-zA-Z]\\):| /\\1|g' -e 's|^ ||'` + ;; + cygwin*) + # Convert to unix form, then to dos form, then back to unix form + # but this time dos style (no spaces!) so that the unix form looks + # like /cygdrive/c/PROGRA~1:/cygdr... + sys_lib_search_path_spec=`cygpath --path --unix "$LIB"` + sys_lib_search_path_spec=`cygpath --path --dos "$sys_lib_search_path_spec" 2>/dev/null` + sys_lib_search_path_spec=`cygpath --path --unix "$sys_lib_search_path_spec" | $SED -e "s/$PATH_SEPARATOR/ /g"` + ;; + *) + sys_lib_search_path_spec="$LIB" + if $ECHO "$sys_lib_search_path_spec" | $GREP ';[c-zC-Z]:/' >/dev/null; then + # It is most probably a Windows format PATH. + sys_lib_search_path_spec=`$ECHO "$sys_lib_search_path_spec" | $SED -e 's/;/ /g'` + else + sys_lib_search_path_spec=`$ECHO "$sys_lib_search_path_spec" | $SED -e "s/$PATH_SEPARATOR/ /g"` + fi + # FIXME: find the short name or the path components, as spaces are + # common. (e.g. "Program Files" -> "PROGRA~1") + ;; + esac + + # DLL is installed to $(libdir)/../bin by postinstall_cmds + postinstall_cmds='base_file=`basename \${file}`~ + dlpath=`$SHELL 2>&1 -c '\''. $dir/'\''\${base_file}'\''i; echo \$dlname'\''`~ + dldir=$destdir/`dirname \$dlpath`~ + test -d \$dldir || mkdir -p \$dldir~ + $install_prog $dir/$dlname \$dldir/$dlname' + postuninstall_cmds='dldll=`$SHELL 2>&1 -c '\''. $file; echo \$dlname'\''`~ + dlpath=$dir/\$dldll~ + $RM \$dlpath' + shlibpath_overrides_runpath=yes + dynamic_linker='Win32 link.exe' + ;; + + *) + # Assume MSVC wrapper + library_names_spec='${libname}`echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext} $libname.lib' + dynamic_linker='Win32 ld.exe' + ;; + esac + # FIXME: first we should search . and the directory the executable is in + shlibpath_var=PATH + ;; + +darwin* | rhapsody*) + dynamic_linker="$host_os dyld" + version_type=darwin + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${major}$shared_ext ${libname}$shared_ext' + soname_spec='${libname}${release}${major}$shared_ext' + shlibpath_overrides_runpath=yes + shlibpath_var=DYLD_LIBRARY_PATH + shrext_cmds='`test .$module = .yes && echo .so || echo .dylib`' + + sys_lib_search_path_spec="$sys_lib_search_path_spec /usr/local/lib" + sys_lib_dlsearch_path_spec='/usr/local/lib /lib /usr/lib' + ;; + +dgux*) + version_type=linux # correct to gnu/linux during the next big refactor + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname$shared_ext' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + ;; + +freebsd* | dragonfly*) + # DragonFly does not have aout. When/if they implement a new + # versioning mechanism, adjust this. + if test -x /usr/bin/objformat; then + objformat=`/usr/bin/objformat` + else + case $host_os in + freebsd[23].*) objformat=aout ;; + *) objformat=elf ;; + esac + fi + version_type=freebsd-$objformat + case $version_type in + freebsd-elf*) + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext} $libname${shared_ext}' + need_version=no + need_lib_prefix=no + ;; + freebsd-*) + library_names_spec='${libname}${release}${shared_ext}$versuffix $libname${shared_ext}$versuffix' + need_version=yes + ;; + esac + shlibpath_var=LD_LIBRARY_PATH + case $host_os in + freebsd2.*) + shlibpath_overrides_runpath=yes + ;; + freebsd3.[01]* | freebsdelf3.[01]*) + shlibpath_overrides_runpath=yes + hardcode_into_libs=yes + ;; + freebsd3.[2-9]* | freebsdelf3.[2-9]* | \ + freebsd4.[0-5] | freebsdelf4.[0-5] | freebsd4.1.1 | freebsdelf4.1.1) + shlibpath_overrides_runpath=no + hardcode_into_libs=yes + ;; + *) # from 4.6 on, and DragonFly + shlibpath_overrides_runpath=yes + hardcode_into_libs=yes + ;; + esac + ;; + +gnu*) + version_type=linux # correct to gnu/linux during the next big refactor + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}${major} ${libname}${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=no + hardcode_into_libs=yes + ;; + +haiku*) + version_type=linux # correct to gnu/linux during the next big refactor + need_lib_prefix=no + need_version=no + dynamic_linker="$host_os runtime_loader" + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}${major} ${libname}${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LIBRARY_PATH + shlibpath_overrides_runpath=yes + sys_lib_dlsearch_path_spec='/boot/home/config/lib /boot/common/lib /boot/system/lib' + hardcode_into_libs=yes + ;; + +hpux9* | hpux10* | hpux11*) + # Give a soname corresponding to the major version so that dld.sl refuses to + # link against other versions. + version_type=sunos + need_lib_prefix=no + need_version=no + case $host_cpu in + ia64*) + shrext_cmds='.so' + hardcode_into_libs=yes + dynamic_linker="$host_os dld.so" + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes # Unless +noenvvar is specified. + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + if test "X$HPUX_IA64_MODE" = X32; then + sys_lib_search_path_spec="/usr/lib/hpux32 /usr/local/lib/hpux32 /usr/local/lib" + else + sys_lib_search_path_spec="/usr/lib/hpux64 /usr/local/lib/hpux64" + fi + sys_lib_dlsearch_path_spec=$sys_lib_search_path_spec + ;; + hppa*64*) + shrext_cmds='.sl' + hardcode_into_libs=yes + dynamic_linker="$host_os dld.sl" + shlibpath_var=LD_LIBRARY_PATH # How should we handle SHLIB_PATH + shlibpath_overrides_runpath=yes # Unless +noenvvar is specified. + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + sys_lib_search_path_spec="/usr/lib/pa20_64 /usr/ccs/lib/pa20_64" + sys_lib_dlsearch_path_spec=$sys_lib_search_path_spec + ;; + *) + shrext_cmds='.sl' + dynamic_linker="$host_os dld.sl" + shlibpath_var=SHLIB_PATH + shlibpath_overrides_runpath=no # +s is required to enable SHLIB_PATH + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + ;; + esac + # HP-UX runs *really* slowly unless shared libraries are mode 555, ... + postinstall_cmds='chmod 555 $lib' + # or fails outright, so override atomically: + install_override_mode=555 + ;; + +interix[3-9]*) + version_type=linux # correct to gnu/linux during the next big refactor + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + dynamic_linker='Interix 3.x ld.so.1 (PE, like ELF)' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=no + hardcode_into_libs=yes + ;; + +irix5* | irix6* | nonstopux*) + case $host_os in + nonstopux*) version_type=nonstopux ;; + *) + if test "$lt_cv_prog_gnu_ld" = yes; then + version_type=linux # correct to gnu/linux during the next big refactor + else + version_type=irix + fi ;; + esac + need_lib_prefix=no + need_version=no + soname_spec='${libname}${release}${shared_ext}$major' + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${release}${shared_ext} $libname${shared_ext}' + case $host_os in + irix5* | nonstopux*) + libsuff= shlibsuff= + ;; + *) + case $LD in # libtool.m4 will add one of these switches to LD + *-32|*"-32 "|*-melf32bsmip|*"-melf32bsmip ") + libsuff= shlibsuff= libmagic=32-bit;; + *-n32|*"-n32 "|*-melf32bmipn32|*"-melf32bmipn32 ") + libsuff=32 shlibsuff=N32 libmagic=N32;; + *-64|*"-64 "|*-melf64bmip|*"-melf64bmip ") + libsuff=64 shlibsuff=64 libmagic=64-bit;; + *) libsuff= shlibsuff= libmagic=never-match;; + esac + ;; + esac + shlibpath_var=LD_LIBRARY${shlibsuff}_PATH + shlibpath_overrides_runpath=no + sys_lib_search_path_spec="/usr/lib${libsuff} /lib${libsuff} /usr/local/lib${libsuff}" + sys_lib_dlsearch_path_spec="/usr/lib${libsuff} /lib${libsuff}" + hardcode_into_libs=yes + ;; + +# No shared lib support for Linux oldld, aout, or coff. +linux*oldld* | linux*aout* | linux*coff*) + dynamic_linker=no + ;; + +# This must be glibc/ELF. +linux* | k*bsd*-gnu | kopensolaris*-gnu) + version_type=linux # correct to gnu/linux during the next big refactor + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + finish_cmds='PATH="\$PATH:/sbin" ldconfig -n $libdir' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=no + + # Some binutils ld are patched to set DT_RUNPATH + if ${lt_cv_shlibpath_overrides_runpath+:} false; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_shlibpath_overrides_runpath=no + save_LDFLAGS=$LDFLAGS + save_libdir=$libdir + eval "libdir=/foo; wl=\"$lt_prog_compiler_wl\"; \ + LDFLAGS=\"\$LDFLAGS $hardcode_libdir_flag_spec\"" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + if ($OBJDUMP -p conftest$ac_exeext) 2>/dev/null | grep "RUNPATH.*$libdir" >/dev/null; then : + lt_cv_shlibpath_overrides_runpath=yes +fi +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + LDFLAGS=$save_LDFLAGS + libdir=$save_libdir + +fi + + shlibpath_overrides_runpath=$lt_cv_shlibpath_overrides_runpath + + # This implies no fast_install, which is unacceptable. + # Some rework will be needed to allow for fast_install + # before this can be enabled. + hardcode_into_libs=yes + + # Append ld.so.conf contents to the search path + if test -f /etc/ld.so.conf; then + lt_ld_extra=`awk '/^include / { system(sprintf("cd /etc; cat %s 2>/dev/null", \$2)); skip = 1; } { if (!skip) print \$0; skip = 0; }' < /etc/ld.so.conf | $SED -e 's/#.*//;/^[ ]*hwcap[ ]/d;s/[:, ]/ /g;s/=[^=]*$//;s/=[^= ]* / /g;s/"//g;/^$/d' | tr '\n' ' '` + sys_lib_dlsearch_path_spec="/lib /usr/lib $lt_ld_extra" + fi + + # We used to test for /lib/ld.so.1 and disable shared libraries on + # powerpc, because MkLinux only supported shared libraries with the + # GNU dynamic linker. Since this was broken with cross compilers, + # most powerpc-linux boxes support dynamic linking these days and + # people can always --disable-shared, the test was removed, and we + # assume the GNU/Linux dynamic linker is in use. + dynamic_linker='GNU/Linux ld.so' + ;; + +netbsd*) + version_type=sunos + need_lib_prefix=no + need_version=no + if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix' + finish_cmds='PATH="\$PATH:/sbin" ldconfig -m $libdir' + dynamic_linker='NetBSD (a.out) ld.so' + else + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + dynamic_linker='NetBSD ld.elf_so' + fi + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes + hardcode_into_libs=yes + ;; + +newsos6) + version_type=linux # correct to gnu/linux during the next big refactor + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes + ;; + +*nto* | *qnx*) + version_type=qnx + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=no + hardcode_into_libs=yes + dynamic_linker='ldqnx.so' + ;; + +openbsd*) + version_type=sunos + sys_lib_dlsearch_path_spec="/usr/lib" + need_lib_prefix=no + # Some older versions of OpenBSD (3.3 at least) *do* need versioned libs. + case $host_os in + openbsd3.3 | openbsd3.3.*) need_version=yes ;; + *) need_version=no ;; + esac + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix' + finish_cmds='PATH="\$PATH:/sbin" ldconfig -m $libdir' + shlibpath_var=LD_LIBRARY_PATH + if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then + case $host_os in + openbsd2.[89] | openbsd2.[89].*) + shlibpath_overrides_runpath=no + ;; + *) + shlibpath_overrides_runpath=yes + ;; + esac + else + shlibpath_overrides_runpath=yes + fi + ;; + +os2*) + libname_spec='$name' + shrext_cmds=".dll" + need_lib_prefix=no + library_names_spec='$libname${shared_ext} $libname.a' + dynamic_linker='OS/2 ld.exe' + shlibpath_var=LIBPATH + ;; + +osf3* | osf4* | osf5*) + version_type=osf + need_lib_prefix=no + need_version=no + soname_spec='${libname}${release}${shared_ext}$major' + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + shlibpath_var=LD_LIBRARY_PATH + sys_lib_search_path_spec="/usr/shlib /usr/ccs/lib /usr/lib/cmplrs/cc /usr/lib /usr/local/lib /var/shlib" + sys_lib_dlsearch_path_spec="$sys_lib_search_path_spec" + ;; + +rdos*) + dynamic_linker=no + ;; + +solaris*) + version_type=linux # correct to gnu/linux during the next big refactor + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes + hardcode_into_libs=yes + # ldd complains unless libraries are executable + postinstall_cmds='chmod +x $lib' + ;; + +sunos4*) + version_type=sunos + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix' + finish_cmds='PATH="\$PATH:/usr/etc" ldconfig $libdir' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes + if test "$with_gnu_ld" = yes; then + need_lib_prefix=no + fi + need_version=yes + ;; + +sysv4 | sysv4.3*) + version_type=linux # correct to gnu/linux during the next big refactor + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + case $host_vendor in + sni) + shlibpath_overrides_runpath=no + need_lib_prefix=no + runpath_var=LD_RUN_PATH + ;; + siemens) + need_lib_prefix=no + ;; + motorola) + need_lib_prefix=no + need_version=no + shlibpath_overrides_runpath=no + sys_lib_search_path_spec='/lib /usr/lib /usr/ccs/lib' + ;; + esac + ;; + +sysv4*MP*) + if test -d /usr/nec ;then + version_type=linux # correct to gnu/linux during the next big refactor + library_names_spec='$libname${shared_ext}.$versuffix $libname${shared_ext}.$major $libname${shared_ext}' + soname_spec='$libname${shared_ext}.$major' + shlibpath_var=LD_LIBRARY_PATH + fi + ;; + +sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX* | sysv4*uw2*) + version_type=freebsd-elf + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext} $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes + hardcode_into_libs=yes + if test "$with_gnu_ld" = yes; then + sys_lib_search_path_spec='/usr/local/lib /usr/gnu/lib /usr/ccs/lib /usr/lib /lib' + else + sys_lib_search_path_spec='/usr/ccs/lib /usr/lib' + case $host_os in + sco3.2v5*) + sys_lib_search_path_spec="$sys_lib_search_path_spec /lib" + ;; + esac + fi + sys_lib_dlsearch_path_spec='/usr/lib' + ;; + +tpf*) + # TPF is a cross-target only. Preferred cross-host = GNU/Linux. + version_type=linux # correct to gnu/linux during the next big refactor + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=no + hardcode_into_libs=yes + ;; + +uts4*) + version_type=linux # correct to gnu/linux during the next big refactor + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + ;; + +*) + dynamic_linker=no + ;; +esac +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $dynamic_linker" >&5 +$as_echo "$dynamic_linker" >&6; } +test "$dynamic_linker" = no && can_build_shared=no + +variables_saved_for_relink="PATH $shlibpath_var $runpath_var" +if test "$GCC" = yes; then + variables_saved_for_relink="$variables_saved_for_relink GCC_EXEC_PREFIX COMPILER_PATH LIBRARY_PATH" +fi + +if test "${lt_cv_sys_lib_search_path_spec+set}" = set; then + sys_lib_search_path_spec="$lt_cv_sys_lib_search_path_spec" +fi +if test "${lt_cv_sys_lib_dlsearch_path_spec+set}" = set; then + sys_lib_dlsearch_path_spec="$lt_cv_sys_lib_dlsearch_path_spec" +fi + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking how to hardcode library paths into programs" >&5 +$as_echo_n "checking how to hardcode library paths into programs... " >&6; } +hardcode_action= +if test -n "$hardcode_libdir_flag_spec" || + test -n "$runpath_var" || + test "X$hardcode_automatic" = "Xyes" ; then + + # We can hardcode non-existent directories. + if test "$hardcode_direct" != no && + # If the only mechanism to avoid hardcoding is shlibpath_var, we + # have to relink, otherwise we might link with an installed library + # when we should be linking with a yet-to-be-installed one + ## test "$_LT_TAGVAR(hardcode_shlibpath_var, )" != no && + test "$hardcode_minus_L" != no; then + # Linking always hardcodes the temporary library directory. + hardcode_action=relink + else + # We can link without hardcoding, and we can hardcode nonexisting dirs. + hardcode_action=immediate + fi +else + # We cannot hardcode anything, or else we can only hardcode existing + # directories. + hardcode_action=unsupported +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $hardcode_action" >&5 +$as_echo "$hardcode_action" >&6; } + +if test "$hardcode_action" = relink || + test "$inherit_rpath" = yes; then + # Fast installation is not supported + enable_fast_install=no +elif test "$shlibpath_overrides_runpath" = yes || + test "$enable_shared" = no; then + # Fast installation is not necessary + enable_fast_install=needless +fi + + + + + + + if test "x$enable_dlopen" != xyes; then + enable_dlopen=unknown + enable_dlopen_self=unknown + enable_dlopen_self_static=unknown +else + lt_cv_dlopen=no + lt_cv_dlopen_libs= + + case $host_os in + beos*) + lt_cv_dlopen="load_add_on" + lt_cv_dlopen_libs= + lt_cv_dlopen_self=yes + ;; + + mingw* | pw32* | cegcc*) + lt_cv_dlopen="LoadLibrary" + lt_cv_dlopen_libs= + ;; + + cygwin*) + lt_cv_dlopen="dlopen" + lt_cv_dlopen_libs= + ;; + + darwin*) + # if libdl is installed we need to link against it + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dlopen in -ldl" >&5 +$as_echo_n "checking for dlopen in -ldl... " >&6; } +if ${ac_cv_lib_dl_dlopen+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-ldl $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char dlopen (); +int +main () +{ +return dlopen (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_dl_dlopen=yes +else + ac_cv_lib_dl_dlopen=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dl_dlopen" >&5 +$as_echo "$ac_cv_lib_dl_dlopen" >&6; } +if test "x$ac_cv_lib_dl_dlopen" = xyes; then : + lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-ldl" +else + + lt_cv_dlopen="dyld" + lt_cv_dlopen_libs= + lt_cv_dlopen_self=yes + +fi + + ;; + + *) + ac_fn_c_check_func "$LINENO" "shl_load" "ac_cv_func_shl_load" +if test "x$ac_cv_func_shl_load" = xyes; then : + lt_cv_dlopen="shl_load" +else + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for shl_load in -ldld" >&5 +$as_echo_n "checking for shl_load in -ldld... " >&6; } +if ${ac_cv_lib_dld_shl_load+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-ldld $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char shl_load (); +int +main () +{ +return shl_load (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_dld_shl_load=yes +else + ac_cv_lib_dld_shl_load=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dld_shl_load" >&5 +$as_echo "$ac_cv_lib_dld_shl_load" >&6; } +if test "x$ac_cv_lib_dld_shl_load" = xyes; then : + lt_cv_dlopen="shl_load" lt_cv_dlopen_libs="-ldld" +else + ac_fn_c_check_func "$LINENO" "dlopen" "ac_cv_func_dlopen" +if test "x$ac_cv_func_dlopen" = xyes; then : + lt_cv_dlopen="dlopen" +else + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dlopen in -ldl" >&5 +$as_echo_n "checking for dlopen in -ldl... " >&6; } +if ${ac_cv_lib_dl_dlopen+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-ldl $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char dlopen (); +int +main () +{ +return dlopen (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_dl_dlopen=yes +else + ac_cv_lib_dl_dlopen=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dl_dlopen" >&5 +$as_echo "$ac_cv_lib_dl_dlopen" >&6; } +if test "x$ac_cv_lib_dl_dlopen" = xyes; then : + lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-ldl" +else + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dlopen in -lsvld" >&5 +$as_echo_n "checking for dlopen in -lsvld... " >&6; } +if ${ac_cv_lib_svld_dlopen+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lsvld $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char dlopen (); +int +main () +{ +return dlopen (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_svld_dlopen=yes +else + ac_cv_lib_svld_dlopen=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_svld_dlopen" >&5 +$as_echo "$ac_cv_lib_svld_dlopen" >&6; } +if test "x$ac_cv_lib_svld_dlopen" = xyes; then : + lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-lsvld" +else + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dld_link in -ldld" >&5 +$as_echo_n "checking for dld_link in -ldld... " >&6; } +if ${ac_cv_lib_dld_dld_link+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-ldld $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char dld_link (); +int +main () +{ +return dld_link (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_dld_dld_link=yes +else + ac_cv_lib_dld_dld_link=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dld_dld_link" >&5 +$as_echo "$ac_cv_lib_dld_dld_link" >&6; } +if test "x$ac_cv_lib_dld_dld_link" = xyes; then : + lt_cv_dlopen="dld_link" lt_cv_dlopen_libs="-ldld" +fi + + +fi + + +fi + + +fi + + +fi + + +fi + + ;; + esac + + if test "x$lt_cv_dlopen" != xno; then + enable_dlopen=yes + else + enable_dlopen=no + fi + + case $lt_cv_dlopen in + dlopen) + save_CPPFLAGS="$CPPFLAGS" + test "x$ac_cv_header_dlfcn_h" = xyes && CPPFLAGS="$CPPFLAGS -DHAVE_DLFCN_H" + + save_LDFLAGS="$LDFLAGS" + wl=$lt_prog_compiler_wl eval LDFLAGS=\"\$LDFLAGS $export_dynamic_flag_spec\" + + save_LIBS="$LIBS" + LIBS="$lt_cv_dlopen_libs $LIBS" + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether a program can dlopen itself" >&5 +$as_echo_n "checking whether a program can dlopen itself... " >&6; } +if ${lt_cv_dlopen_self+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test "$cross_compiling" = yes; then : + lt_cv_dlopen_self=cross +else + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +#line $LINENO "configure" +#include "confdefs.h" + +#if HAVE_DLFCN_H +#include +#endif + +#include + +#ifdef RTLD_GLOBAL +# define LT_DLGLOBAL RTLD_GLOBAL +#else +# ifdef DL_GLOBAL +# define LT_DLGLOBAL DL_GLOBAL +# else +# define LT_DLGLOBAL 0 +# endif +#endif + +/* We may have to define LT_DLLAZY_OR_NOW in the command line if we + find out it does not work in some platform. */ +#ifndef LT_DLLAZY_OR_NOW +# ifdef RTLD_LAZY +# define LT_DLLAZY_OR_NOW RTLD_LAZY +# else +# ifdef DL_LAZY +# define LT_DLLAZY_OR_NOW DL_LAZY +# else +# ifdef RTLD_NOW +# define LT_DLLAZY_OR_NOW RTLD_NOW +# else +# ifdef DL_NOW +# define LT_DLLAZY_OR_NOW DL_NOW +# else +# define LT_DLLAZY_OR_NOW 0 +# endif +# endif +# endif +# endif +#endif + +/* When -fvisbility=hidden is used, assume the code has been annotated + correspondingly for the symbols needed. */ +#if defined(__GNUC__) && (((__GNUC__ == 3) && (__GNUC_MINOR__ >= 3)) || (__GNUC__ > 3)) +int fnord () __attribute__((visibility("default"))); +#endif + +int fnord () { return 42; } +int main () +{ + void *self = dlopen (0, LT_DLGLOBAL|LT_DLLAZY_OR_NOW); + int status = $lt_dlunknown; + + if (self) + { + if (dlsym (self,"fnord")) status = $lt_dlno_uscore; + else + { + if (dlsym( self,"_fnord")) status = $lt_dlneed_uscore; + else puts (dlerror ()); + } + /* dlclose (self); */ + } + else + puts (dlerror ()); + + return status; +} +_LT_EOF + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_link\""; } >&5 + (eval $ac_link) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } && test -s conftest${ac_exeext} 2>/dev/null; then + (./conftest; exit; ) >&5 2>/dev/null + lt_status=$? + case x$lt_status in + x$lt_dlno_uscore) lt_cv_dlopen_self=yes ;; + x$lt_dlneed_uscore) lt_cv_dlopen_self=yes ;; + x$lt_dlunknown|x*) lt_cv_dlopen_self=no ;; + esac + else : + # compilation failed + lt_cv_dlopen_self=no + fi +fi +rm -fr conftest* + + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_dlopen_self" >&5 +$as_echo "$lt_cv_dlopen_self" >&6; } + + if test "x$lt_cv_dlopen_self" = xyes; then + wl=$lt_prog_compiler_wl eval LDFLAGS=\"\$LDFLAGS $lt_prog_compiler_static\" + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether a statically linked program can dlopen itself" >&5 +$as_echo_n "checking whether a statically linked program can dlopen itself... " >&6; } +if ${lt_cv_dlopen_self_static+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test "$cross_compiling" = yes; then : + lt_cv_dlopen_self_static=cross +else + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +#line $LINENO "configure" +#include "confdefs.h" + +#if HAVE_DLFCN_H +#include +#endif + +#include + +#ifdef RTLD_GLOBAL +# define LT_DLGLOBAL RTLD_GLOBAL +#else +# ifdef DL_GLOBAL +# define LT_DLGLOBAL DL_GLOBAL +# else +# define LT_DLGLOBAL 0 +# endif +#endif + +/* We may have to define LT_DLLAZY_OR_NOW in the command line if we + find out it does not work in some platform. */ +#ifndef LT_DLLAZY_OR_NOW +# ifdef RTLD_LAZY +# define LT_DLLAZY_OR_NOW RTLD_LAZY +# else +# ifdef DL_LAZY +# define LT_DLLAZY_OR_NOW DL_LAZY +# else +# ifdef RTLD_NOW +# define LT_DLLAZY_OR_NOW RTLD_NOW +# else +# ifdef DL_NOW +# define LT_DLLAZY_OR_NOW DL_NOW +# else +# define LT_DLLAZY_OR_NOW 0 +# endif +# endif +# endif +# endif +#endif + +/* When -fvisbility=hidden is used, assume the code has been annotated + correspondingly for the symbols needed. */ +#if defined(__GNUC__) && (((__GNUC__ == 3) && (__GNUC_MINOR__ >= 3)) || (__GNUC__ > 3)) +int fnord () __attribute__((visibility("default"))); +#endif + +int fnord () { return 42; } +int main () +{ + void *self = dlopen (0, LT_DLGLOBAL|LT_DLLAZY_OR_NOW); + int status = $lt_dlunknown; + + if (self) + { + if (dlsym (self,"fnord")) status = $lt_dlno_uscore; + else + { + if (dlsym( self,"_fnord")) status = $lt_dlneed_uscore; + else puts (dlerror ()); + } + /* dlclose (self); */ + } + else + puts (dlerror ()); + + return status; +} +_LT_EOF + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_link\""; } >&5 + (eval $ac_link) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } && test -s conftest${ac_exeext} 2>/dev/null; then + (./conftest; exit; ) >&5 2>/dev/null + lt_status=$? + case x$lt_status in + x$lt_dlno_uscore) lt_cv_dlopen_self_static=yes ;; + x$lt_dlneed_uscore) lt_cv_dlopen_self_static=yes ;; + x$lt_dlunknown|x*) lt_cv_dlopen_self_static=no ;; + esac + else : + # compilation failed + lt_cv_dlopen_self_static=no + fi +fi +rm -fr conftest* + + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_dlopen_self_static" >&5 +$as_echo "$lt_cv_dlopen_self_static" >&6; } + fi + + CPPFLAGS="$save_CPPFLAGS" + LDFLAGS="$save_LDFLAGS" + LIBS="$save_LIBS" + ;; + esac + + case $lt_cv_dlopen_self in + yes|no) enable_dlopen_self=$lt_cv_dlopen_self ;; + *) enable_dlopen_self=unknown ;; + esac + + case $lt_cv_dlopen_self_static in + yes|no) enable_dlopen_self_static=$lt_cv_dlopen_self_static ;; + *) enable_dlopen_self_static=unknown ;; + esac +fi + + + + + + + + + + + + + + + + + +striplib= +old_striplib= +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether stripping libraries is possible" >&5 +$as_echo_n "checking whether stripping libraries is possible... " >&6; } +if test -n "$STRIP" && $STRIP -V 2>&1 | $GREP "GNU strip" >/dev/null; then + test -z "$old_striplib" && old_striplib="$STRIP --strip-debug" + test -z "$striplib" && striplib="$STRIP --strip-unneeded" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } +else +# FIXME - insert some real tests, host_os isn't really good enough + case $host_os in + darwin*) + if test -n "$STRIP" ; then + striplib="$STRIP -x" + old_striplib="$STRIP -S" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } + fi + ;; + *) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } + ;; + esac +fi + + + + + + + + + + + + + # Report which library types will actually be built + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if libtool supports shared libraries" >&5 +$as_echo_n "checking if libtool supports shared libraries... " >&6; } + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $can_build_shared" >&5 +$as_echo "$can_build_shared" >&6; } + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether to build shared libraries" >&5 +$as_echo_n "checking whether to build shared libraries... " >&6; } + test "$can_build_shared" = "no" && enable_shared=no + + # On AIX, shared libraries and static libraries use the same namespace, and + # are all built from PIC. + case $host_os in + aix3*) + test "$enable_shared" = yes && enable_static=no + if test -n "$RANLIB"; then + archive_cmds="$archive_cmds~\$RANLIB \$lib" + postinstall_cmds='$RANLIB $lib' + fi + ;; + + aix[4-9]*) + if test "$host_cpu" != ia64 && test "$aix_use_runtimelinking" = no ; then + test "$enable_shared" = yes && enable_static=no + fi + ;; + esac + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $enable_shared" >&5 +$as_echo "$enable_shared" >&6; } + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether to build static libraries" >&5 +$as_echo_n "checking whether to build static libraries... " >&6; } + # Make sure either enable_shared or enable_static is yes. + test "$enable_shared" = yes || enable_static=yes + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $enable_static" >&5 +$as_echo "$enable_static" >&6; } + + + + +fi +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + +CC="$lt_save_CC" + + + + + + + + + + + + + + + + ac_config_commands="$ac_config_commands libtool" + + + + +# Only expand once: + + +ac_ext=cpp +ac_cpp='$CXXCPP $CPPFLAGS' +ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_cxx_compiler_gnu +if test -z "$CXX"; then + if test -n "$CCC"; then + CXX=$CCC + else + if test -n "$ac_tool_prefix"; then + for ac_prog in g++ c++ gpp aCC CC cxx cc++ cl.exe FCC KCC RCC xlC_r xlC + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_CXX+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CXX"; then + ac_cv_prog_CXX="$CXX" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_CXX="$ac_tool_prefix$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CXX=$ac_cv_prog_CXX +if test -n "$CXX"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CXX" >&5 +$as_echo "$CXX" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$CXX" && break + done +fi +if test -z "$CXX"; then + ac_ct_CXX=$CXX + for ac_prog in g++ c++ gpp aCC CC cxx cc++ cl.exe FCC KCC RCC xlC_r xlC +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_CXX+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CXX"; then + ac_cv_prog_ac_ct_CXX="$ac_ct_CXX" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_CXX="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CXX=$ac_cv_prog_ac_ct_CXX +if test -n "$ac_ct_CXX"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CXX" >&5 +$as_echo "$ac_ct_CXX" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$ac_ct_CXX" && break +done + + if test "x$ac_ct_CXX" = x; then + CXX="g++" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CXX=$ac_ct_CXX + fi +fi + + fi +fi +# Provide some information about the compiler. +$as_echo "$as_me:${as_lineno-$LINENO}: checking for C++ compiler version" >&5 +set X $ac_compile +ac_compiler=$2 +for ac_option in --version -v -V -qversion; do + { { ac_try="$ac_compiler $ac_option >&5" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compiler $ac_option >&5") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + sed '10a\ +... rest of stderr output deleted ... + 10q' conftest.err >conftest.er1 + cat conftest.er1 >&5 + fi + rm -f conftest.er1 conftest.err + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } +done + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C++ compiler" >&5 +$as_echo_n "checking whether we are using the GNU C++ compiler... " >&6; } +if ${ac_cv_cxx_compiler_gnu+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +#ifndef __GNUC__ + choke me +#endif + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + ac_compiler_gnu=yes +else + ac_compiler_gnu=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +ac_cv_cxx_compiler_gnu=$ac_compiler_gnu + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_cxx_compiler_gnu" >&5 +$as_echo "$ac_cv_cxx_compiler_gnu" >&6; } +if test $ac_compiler_gnu = yes; then + GXX=yes +else + GXX= +fi +ac_test_CXXFLAGS=${CXXFLAGS+set} +ac_save_CXXFLAGS=$CXXFLAGS +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CXX accepts -g" >&5 +$as_echo_n "checking whether $CXX accepts -g... " >&6; } +if ${ac_cv_prog_cxx_g+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_save_cxx_werror_flag=$ac_cxx_werror_flag + ac_cxx_werror_flag=yes + ac_cv_prog_cxx_g=no + CXXFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + ac_cv_prog_cxx_g=yes +else + CXXFLAGS="" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + +else + ac_cxx_werror_flag=$ac_save_cxx_werror_flag + CXXFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + ac_cv_prog_cxx_g=yes +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_cxx_werror_flag=$ac_save_cxx_werror_flag +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cxx_g" >&5 +$as_echo "$ac_cv_prog_cxx_g" >&6; } +if test "$ac_test_CXXFLAGS" = set; then + CXXFLAGS=$ac_save_CXXFLAGS +elif test $ac_cv_prog_cxx_g = yes; then + if test "$GXX" = yes; then + CXXFLAGS="-g -O2" + else + CXXFLAGS="-g" + fi +else + if test "$GXX" = yes; then + CXXFLAGS="-O2" + else + CXXFLAGS= + fi +fi +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + +depcc="$CXX" am_compiler_list= + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking dependency style of $depcc" >&5 +$as_echo_n "checking dependency style of $depcc... " >&6; } +if ${am_cv_CXX_dependencies_compiler_type+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -z "$AMDEP_TRUE" && test -f "$am_depcomp"; then + # We make a subdir and do the tests there. Otherwise we can end up + # making bogus files that we don't know about and never remove. For + # instance it was reported that on HP-UX the gcc test will end up + # making a dummy file named 'D' -- because '-MD' means "put the output + # in D". + rm -rf conftest.dir + mkdir conftest.dir + # Copy depcomp to subdir because otherwise we won't find it if we're + # using a relative directory. + cp "$am_depcomp" conftest.dir + cd conftest.dir + # We will build objects and dependencies in a subdirectory because + # it helps to detect inapplicable dependency modes. For instance + # both Tru64's cc and ICC support -MD to output dependencies as a + # side effect of compilation, but ICC will put the dependencies in + # the current directory while Tru64 will put them in the object + # directory. + mkdir sub + + am_cv_CXX_dependencies_compiler_type=none + if test "$am_compiler_list" = ""; then + am_compiler_list=`sed -n 's/^#*\([a-zA-Z0-9]*\))$/\1/p' < ./depcomp` + fi + am__universal=false + case " $depcc " in #( + *\ -arch\ *\ -arch\ *) am__universal=true ;; + esac + + for depmode in $am_compiler_list; do + # Setup a source with many dependencies, because some compilers + # like to wrap large dependency lists on column 80 (with \), and + # we should not choose a depcomp mode which is confused by this. + # + # We need to recreate these files for each test, as the compiler may + # overwrite some of them when testing with obscure command lines. + # This happens at least with the AIX C compiler. + : > sub/conftest.c + for i in 1 2 3 4 5 6; do + echo '#include "conftst'$i'.h"' >> sub/conftest.c + # Using ": > sub/conftst$i.h" creates only sub/conftst1.h with + # Solaris 10 /bin/sh. + echo '/* dummy */' > sub/conftst$i.h + done + echo "${am__include} ${am__quote}sub/conftest.Po${am__quote}" > confmf + + # We check with '-c' and '-o' for the sake of the "dashmstdout" + # mode. It turns out that the SunPro C++ compiler does not properly + # handle '-M -o', and we need to detect this. Also, some Intel + # versions had trouble with output in subdirs. + am__obj=sub/conftest.${OBJEXT-o} + am__minus_obj="-o $am__obj" + case $depmode in + gcc) + # This depmode causes a compiler race in universal mode. + test "$am__universal" = false || continue + ;; + nosideeffect) + # After this tag, mechanisms are not by side-effect, so they'll + # only be used when explicitly requested. + if test "x$enable_dependency_tracking" = xyes; then + continue + else + break + fi + ;; + msvc7 | msvc7msys | msvisualcpp | msvcmsys) + # This compiler won't grok '-c -o', but also, the minuso test has + # not run yet. These depmodes are late enough in the game, and + # so weak that their functioning should not be impacted. + am__obj=conftest.${OBJEXT-o} + am__minus_obj= + ;; + none) break ;; + esac + if depmode=$depmode \ + source=sub/conftest.c object=$am__obj \ + depfile=sub/conftest.Po tmpdepfile=sub/conftest.TPo \ + $SHELL ./depcomp $depcc -c $am__minus_obj sub/conftest.c \ + >/dev/null 2>conftest.err && + grep sub/conftst1.h sub/conftest.Po > /dev/null 2>&1 && + grep sub/conftst6.h sub/conftest.Po > /dev/null 2>&1 && + grep $am__obj sub/conftest.Po > /dev/null 2>&1 && + ${MAKE-make} -s -f confmf > /dev/null 2>&1; then + # icc doesn't choke on unknown options, it will just issue warnings + # or remarks (even with -Werror). So we grep stderr for any message + # that says an option was ignored or not supported. + # When given -MP, icc 7.0 and 7.1 complain thusly: + # icc: Command line warning: ignoring option '-M'; no argument required + # The diagnosis changed in icc 8.0: + # icc: Command line remark: option '-MP' not supported + if (grep 'ignoring option' conftest.err || + grep 'not supported' conftest.err) >/dev/null 2>&1; then :; else + am_cv_CXX_dependencies_compiler_type=$depmode + break + fi + fi + done + + cd .. + rm -rf conftest.dir +else + am_cv_CXX_dependencies_compiler_type=none +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_CXX_dependencies_compiler_type" >&5 +$as_echo "$am_cv_CXX_dependencies_compiler_type" >&6; } +CXXDEPMODE=depmode=$am_cv_CXX_dependencies_compiler_type + + if + test "x$enable_dependency_tracking" != xno \ + && test "$am_cv_CXX_dependencies_compiler_type" = gcc3; then + am__fastdepCXX_TRUE= + am__fastdepCXX_FALSE='#' +else + am__fastdepCXX_TRUE='#' + am__fastdepCXX_FALSE= +fi + + + + + +func_stripname_cnf () +{ + case ${2} in + .*) func_stripname_result=`$ECHO "${3}" | $SED "s%^${1}%%; s%\\\\${2}\$%%"`;; + *) func_stripname_result=`$ECHO "${3}" | $SED "s%^${1}%%; s%${2}\$%%"`;; + esac +} # func_stripname_cnf + + if test -n "$CXX" && ( test "X$CXX" != "Xno" && + ( (test "X$CXX" = "Xg++" && `g++ -v >/dev/null 2>&1` ) || + (test "X$CXX" != "Xg++"))) ; then + ac_ext=cpp +ac_cpp='$CXXCPP $CPPFLAGS' +ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_cxx_compiler_gnu +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to run the C++ preprocessor" >&5 +$as_echo_n "checking how to run the C++ preprocessor... " >&6; } +if test -z "$CXXCPP"; then + if ${ac_cv_prog_CXXCPP+:} false; then : + $as_echo_n "(cached) " >&6 +else + # Double quotes because CXXCPP needs to be expanded + for CXXCPP in "$CXX -E" "/lib/cpp" + do + ac_preproc_ok=false +for ac_cxx_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef __STDC__ +# include +#else +# include +#endif + Syntax error +_ACEOF +if ac_fn_cxx_try_cpp "$LINENO"; then : + +else + # Broken: fails on valid input. +continue +fi +rm -f conftest.err conftest.i conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +_ACEOF +if ac_fn_cxx_try_cpp "$LINENO"; then : + # Broken: success on invalid input. +continue +else + # Passes both tests. +ac_preproc_ok=: +break +fi +rm -f conftest.err conftest.i conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.i conftest.err conftest.$ac_ext +if $ac_preproc_ok; then : + break +fi + + done + ac_cv_prog_CXXCPP=$CXXCPP + +fi + CXXCPP=$ac_cv_prog_CXXCPP +else + ac_cv_prog_CXXCPP=$CXXCPP +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $CXXCPP" >&5 +$as_echo "$CXXCPP" >&6; } +ac_preproc_ok=false +for ac_cxx_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef __STDC__ +# include +#else +# include +#endif + Syntax error +_ACEOF +if ac_fn_cxx_try_cpp "$LINENO"; then : + +else + # Broken: fails on valid input. +continue +fi +rm -f conftest.err conftest.i conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +_ACEOF +if ac_fn_cxx_try_cpp "$LINENO"; then : + # Broken: success on invalid input. +continue +else + # Passes both tests. +ac_preproc_ok=: +break +fi +rm -f conftest.err conftest.i conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.i conftest.err conftest.$ac_ext +if $ac_preproc_ok; then : + +else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error $? "C++ preprocessor \"$CXXCPP\" fails sanity check +See \`config.log' for more details" "$LINENO" 5; } +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + +else + _lt_caught_CXX_error=yes +fi + +ac_ext=cpp +ac_cpp='$CXXCPP $CPPFLAGS' +ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_cxx_compiler_gnu + +archive_cmds_need_lc_CXX=no +allow_undefined_flag_CXX= +always_export_symbols_CXX=no +archive_expsym_cmds_CXX= +compiler_needs_object_CXX=no +export_dynamic_flag_spec_CXX= +hardcode_direct_CXX=no +hardcode_direct_absolute_CXX=no +hardcode_libdir_flag_spec_CXX= +hardcode_libdir_separator_CXX= +hardcode_minus_L_CXX=no +hardcode_shlibpath_var_CXX=unsupported +hardcode_automatic_CXX=no +inherit_rpath_CXX=no +module_cmds_CXX= +module_expsym_cmds_CXX= +link_all_deplibs_CXX=unknown +old_archive_cmds_CXX=$old_archive_cmds +reload_flag_CXX=$reload_flag +reload_cmds_CXX=$reload_cmds +no_undefined_flag_CXX= +whole_archive_flag_spec_CXX= +enable_shared_with_static_runtimes_CXX=no + +# Source file extension for C++ test sources. +ac_ext=cpp + +# Object file extension for compiled C++ test sources. +objext=o +objext_CXX=$objext + +# No sense in running all these tests if we already determined that +# the CXX compiler isn't working. Some variables (like enable_shared) +# are currently assumed to apply to all compilers on this platform, +# and will be corrupted by setting them based on a non-working compiler. +if test "$_lt_caught_CXX_error" != yes; then + # Code to be used in simple compile tests + lt_simple_compile_test_code="int some_variable = 0;" + + # Code to be used in simple link tests + lt_simple_link_test_code='int main(int, char *[]) { return(0); }' + + # ltmain only uses $CC for tagged configurations so make sure $CC is set. + + + + + + +# If no C compiler was specified, use CC. +LTCC=${LTCC-"$CC"} + +# If no C compiler flags were specified, use CFLAGS. +LTCFLAGS=${LTCFLAGS-"$CFLAGS"} + +# Allow CC to be a program name with arguments. +compiler=$CC + + + # save warnings/boilerplate of simple test code + ac_outfile=conftest.$ac_objext +echo "$lt_simple_compile_test_code" >conftest.$ac_ext +eval "$ac_compile" 2>&1 >/dev/null | $SED '/^$/d; /^ *+/d' >conftest.err +_lt_compiler_boilerplate=`cat conftest.err` +$RM conftest* + + ac_outfile=conftest.$ac_objext +echo "$lt_simple_link_test_code" >conftest.$ac_ext +eval "$ac_link" 2>&1 >/dev/null | $SED '/^$/d; /^ *+/d' >conftest.err +_lt_linker_boilerplate=`cat conftest.err` +$RM -r conftest* + + + # Allow CC to be a program name with arguments. + lt_save_CC=$CC + lt_save_CFLAGS=$CFLAGS + lt_save_LD=$LD + lt_save_GCC=$GCC + GCC=$GXX + lt_save_with_gnu_ld=$with_gnu_ld + lt_save_path_LD=$lt_cv_path_LD + if test -n "${lt_cv_prog_gnu_ldcxx+set}"; then + lt_cv_prog_gnu_ld=$lt_cv_prog_gnu_ldcxx + else + $as_unset lt_cv_prog_gnu_ld + fi + if test -n "${lt_cv_path_LDCXX+set}"; then + lt_cv_path_LD=$lt_cv_path_LDCXX + else + $as_unset lt_cv_path_LD + fi + test -z "${LDCXX+set}" || LD=$LDCXX + CC=${CXX-"c++"} + CFLAGS=$CXXFLAGS + compiler=$CC + compiler_CXX=$CC + for cc_temp in $compiler""; do + case $cc_temp in + compile | *[\\/]compile | ccache | *[\\/]ccache ) ;; + distcc | *[\\/]distcc | purify | *[\\/]purify ) ;; + \-*) ;; + *) break;; + esac +done +cc_basename=`$ECHO "$cc_temp" | $SED "s%.*/%%; s%^$host_alias-%%"` + + + if test -n "$compiler"; then + # We don't want -fno-exception when compiling C++ code, so set the + # no_builtin_flag separately + if test "$GXX" = yes; then + lt_prog_compiler_no_builtin_flag_CXX=' -fno-builtin' + else + lt_prog_compiler_no_builtin_flag_CXX= + fi + + if test "$GXX" = yes; then + # Set up default GNU C++ configuration + + + +# Check whether --with-gnu-ld was given. +if test "${with_gnu_ld+set}" = set; then : + withval=$with_gnu_ld; test "$withval" = no || with_gnu_ld=yes +else + with_gnu_ld=no +fi + +ac_prog=ld +if test "$GCC" = yes; then + # Check if gcc -print-prog-name=ld gives a path. + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for ld used by $CC" >&5 +$as_echo_n "checking for ld used by $CC... " >&6; } + case $host in + *-*-mingw*) + # gcc leaves a trailing carriage return which upsets mingw + ac_prog=`($CC -print-prog-name=ld) 2>&5 | tr -d '\015'` ;; + *) + ac_prog=`($CC -print-prog-name=ld) 2>&5` ;; + esac + case $ac_prog in + # Accept absolute paths. + [\\/]* | ?:[\\/]*) + re_direlt='/[^/][^/]*/\.\./' + # Canonicalize the pathname of ld + ac_prog=`$ECHO "$ac_prog"| $SED 's%\\\\%/%g'` + while $ECHO "$ac_prog" | $GREP "$re_direlt" > /dev/null 2>&1; do + ac_prog=`$ECHO $ac_prog| $SED "s%$re_direlt%/%"` + done + test -z "$LD" && LD="$ac_prog" + ;; + "") + # If it fails, then pretend we aren't using GCC. + ac_prog=ld + ;; + *) + # If it is relative, then search for the first ld in PATH. + with_gnu_ld=unknown + ;; + esac +elif test "$with_gnu_ld" = yes; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for GNU ld" >&5 +$as_echo_n "checking for GNU ld... " >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for non-GNU ld" >&5 +$as_echo_n "checking for non-GNU ld... " >&6; } +fi +if ${lt_cv_path_LD+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -z "$LD"; then + lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR + for ac_dir in $PATH; do + IFS="$lt_save_ifs" + test -z "$ac_dir" && ac_dir=. + if test -f "$ac_dir/$ac_prog" || test -f "$ac_dir/$ac_prog$ac_exeext"; then + lt_cv_path_LD="$ac_dir/$ac_prog" + # Check to see if the program is GNU ld. I'd rather use --version, + # but apparently some variants of GNU ld only accept -v. + # Break only if it was the GNU/non-GNU ld that we prefer. + case `"$lt_cv_path_LD" -v 2>&1 &5 +$as_echo "$LD" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi +test -z "$LD" && as_fn_error $? "no acceptable ld found in \$PATH" "$LINENO" 5 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if the linker ($LD) is GNU ld" >&5 +$as_echo_n "checking if the linker ($LD) is GNU ld... " >&6; } +if ${lt_cv_prog_gnu_ld+:} false; then : + $as_echo_n "(cached) " >&6 +else + # I'd rather use --version here, but apparently some GNU lds only accept -v. +case `$LD -v 2>&1 &5 +$as_echo "$lt_cv_prog_gnu_ld" >&6; } +with_gnu_ld=$lt_cv_prog_gnu_ld + + + + + + + + # Check if GNU C++ uses GNU ld as the underlying linker, since the + # archiving commands below assume that GNU ld is being used. + if test "$with_gnu_ld" = yes; then + archive_cmds_CXX='$CC $pic_flag -shared -nostdlib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname $wl$soname -o $lib' + archive_expsym_cmds_CXX='$CC $pic_flag -shared -nostdlib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' + + hardcode_libdir_flag_spec_CXX='${wl}-rpath ${wl}$libdir' + export_dynamic_flag_spec_CXX='${wl}--export-dynamic' + + # If archive_cmds runs LD, not CC, wlarc should be empty + # XXX I think wlarc can be eliminated in ltcf-cxx, but I need to + # investigate it a little bit more. (MM) + wlarc='${wl}' + + # ancient GNU ld didn't support --whole-archive et. al. + if eval "`$CC -print-prog-name=ld` --help 2>&1" | + $GREP 'no-whole-archive' > /dev/null; then + whole_archive_flag_spec_CXX="$wlarc"'--whole-archive$convenience '"$wlarc"'--no-whole-archive' + else + whole_archive_flag_spec_CXX= + fi + else + with_gnu_ld=no + wlarc= + + # A generic and very simple default shared library creation + # command for GNU C++ for the case where it uses the native + # linker, instead of GNU ld. If possible, this setting should + # overridden to take advantage of the native linker features on + # the platform it is being used on. + archive_cmds_CXX='$CC -shared -nostdlib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags -o $lib' + fi + + # Commands to make compiler produce verbose output that lists + # what "hidden" libraries, object files and flags are used when + # linking a shared library. + output_verbose_link_cmd='$CC -shared $CFLAGS -v conftest.$objext 2>&1 | $GREP -v "^Configured with:" | $GREP "\-L"' + + else + GXX=no + with_gnu_ld=no + wlarc= + fi + + # PORTME: fill in a description of your system's C++ link characteristics + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the $compiler linker ($LD) supports shared libraries" >&5 +$as_echo_n "checking whether the $compiler linker ($LD) supports shared libraries... " >&6; } + ld_shlibs_CXX=yes + case $host_os in + aix3*) + # FIXME: insert proper C++ library support + ld_shlibs_CXX=no + ;; + aix[4-9]*) + if test "$host_cpu" = ia64; then + # On IA64, the linker does run time linking by default, so we don't + # have to do anything special. + aix_use_runtimelinking=no + exp_sym_flag='-Bexport' + no_entry_flag="" + else + aix_use_runtimelinking=no + + # Test if we are trying to use run time linking or normal + # AIX style linking. If -brtl is somewhere in LDFLAGS, we + # need to do runtime linking. + case $host_os in aix4.[23]|aix4.[23].*|aix[5-9]*) + for ld_flag in $LDFLAGS; do + case $ld_flag in + *-brtl*) + aix_use_runtimelinking=yes + break + ;; + esac + done + ;; + esac + + exp_sym_flag='-bexport' + no_entry_flag='-bnoentry' + fi + + # When large executables or shared objects are built, AIX ld can + # have problems creating the table of contents. If linking a library + # or program results in "error TOC overflow" add -mminimal-toc to + # CXXFLAGS/CFLAGS for g++/gcc. In the cases where that is not + # enough to fix the problem, add -Wl,-bbigtoc to LDFLAGS. + + archive_cmds_CXX='' + hardcode_direct_CXX=yes + hardcode_direct_absolute_CXX=yes + hardcode_libdir_separator_CXX=':' + link_all_deplibs_CXX=yes + file_list_spec_CXX='${wl}-f,' + + if test "$GXX" = yes; then + case $host_os in aix4.[012]|aix4.[012].*) + # We only want to do this on AIX 4.2 and lower, the check + # below for broken collect2 doesn't work under 4.3+ + collect2name=`${CC} -print-prog-name=collect2` + if test -f "$collect2name" && + strings "$collect2name" | $GREP resolve_lib_name >/dev/null + then + # We have reworked collect2 + : + else + # We have old collect2 + hardcode_direct_CXX=unsupported + # It fails to find uninstalled libraries when the uninstalled + # path is not listed in the libpath. Setting hardcode_minus_L + # to unsupported forces relinking + hardcode_minus_L_CXX=yes + hardcode_libdir_flag_spec_CXX='-L$libdir' + hardcode_libdir_separator_CXX= + fi + esac + shared_flag='-shared' + if test "$aix_use_runtimelinking" = yes; then + shared_flag="$shared_flag "'${wl}-G' + fi + else + # not using gcc + if test "$host_cpu" = ia64; then + # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release + # chokes on -Wl,-G. The following line is correct: + shared_flag='-G' + else + if test "$aix_use_runtimelinking" = yes; then + shared_flag='${wl}-G' + else + shared_flag='${wl}-bM:SRE' + fi + fi + fi + + export_dynamic_flag_spec_CXX='${wl}-bexpall' + # It seems that -bexpall does not export symbols beginning with + # underscore (_), so it is better to generate a list of symbols to + # export. + always_export_symbols_CXX=yes + if test "$aix_use_runtimelinking" = yes; then + # Warning - without using the other runtime loading flags (-brtl), + # -berok will link without error, but may produce a broken library. + allow_undefined_flag_CXX='-berok' + # Determine the default libpath from the value encoded in an empty + # executable. + if test "${lt_cv_aix_libpath+set}" = set; then + aix_libpath=$lt_cv_aix_libpath +else + if ${lt_cv_aix_libpath__CXX+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_link "$LINENO"; then : + + lt_aix_libpath_sed=' + /Import File Strings/,/^$/ { + /^0/ { + s/^0 *\([^ ]*\) *$/\1/ + p + } + }' + lt_cv_aix_libpath__CXX=`dump -H conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` + # Check for a 64-bit object if we didn't find anything. + if test -z "$lt_cv_aix_libpath__CXX"; then + lt_cv_aix_libpath__CXX=`dump -HX64 conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` + fi +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + if test -z "$lt_cv_aix_libpath__CXX"; then + lt_cv_aix_libpath__CXX="/usr/lib:/lib" + fi + +fi + + aix_libpath=$lt_cv_aix_libpath__CXX +fi + + hardcode_libdir_flag_spec_CXX='${wl}-blibpath:$libdir:'"$aix_libpath" + + archive_expsym_cmds_CXX='$CC -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_flag}" != "x"; then func_echo_all "${wl}${allow_undefined_flag}"; else :; fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" + else + if test "$host_cpu" = ia64; then + hardcode_libdir_flag_spec_CXX='${wl}-R $libdir:/usr/lib:/lib' + allow_undefined_flag_CXX="-z nodefs" + archive_expsym_cmds_CXX="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undefined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" + else + # Determine the default libpath from the value encoded in an + # empty executable. + if test "${lt_cv_aix_libpath+set}" = set; then + aix_libpath=$lt_cv_aix_libpath +else + if ${lt_cv_aix_libpath__CXX+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_link "$LINENO"; then : + + lt_aix_libpath_sed=' + /Import File Strings/,/^$/ { + /^0/ { + s/^0 *\([^ ]*\) *$/\1/ + p + } + }' + lt_cv_aix_libpath__CXX=`dump -H conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` + # Check for a 64-bit object if we didn't find anything. + if test -z "$lt_cv_aix_libpath__CXX"; then + lt_cv_aix_libpath__CXX=`dump -HX64 conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` + fi +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + if test -z "$lt_cv_aix_libpath__CXX"; then + lt_cv_aix_libpath__CXX="/usr/lib:/lib" + fi + +fi + + aix_libpath=$lt_cv_aix_libpath__CXX +fi + + hardcode_libdir_flag_spec_CXX='${wl}-blibpath:$libdir:'"$aix_libpath" + # Warning - without using the other run time loading flags, + # -berok will link without error, but may produce a broken library. + no_undefined_flag_CXX=' ${wl}-bernotok' + allow_undefined_flag_CXX=' ${wl}-berok' + if test "$with_gnu_ld" = yes; then + # We only use this code for GNU lds that support --whole-archive. + whole_archive_flag_spec_CXX='${wl}--whole-archive$convenience ${wl}--no-whole-archive' + else + # Exported symbols can be pulled into shared objects from archives + whole_archive_flag_spec_CXX='$convenience' + fi + archive_cmds_need_lc_CXX=yes + # This is similar to how AIX traditionally builds its shared + # libraries. + archive_expsym_cmds_CXX="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${allow_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output_objdir/$soname' + fi + fi + ;; + + beos*) + if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then + allow_undefined_flag_CXX=unsupported + # Joseph Beckenbach says some releases of gcc + # support --undefined. This deserves some investigation. FIXME + archive_cmds_CXX='$CC -nostart $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + else + ld_shlibs_CXX=no + fi + ;; + + chorus*) + case $cc_basename in + *) + # FIXME: insert proper C++ library support + ld_shlibs_CXX=no + ;; + esac + ;; + + cygwin* | mingw* | pw32* | cegcc*) + case $GXX,$cc_basename in + ,cl* | no,cl*) + # Native MSVC + # hardcode_libdir_flag_spec is actually meaningless, as there is + # no search path for DLLs. + hardcode_libdir_flag_spec_CXX=' ' + allow_undefined_flag_CXX=unsupported + always_export_symbols_CXX=yes + file_list_spec_CXX='@' + # Tell ltmain to make .lib files, not .a files. + libext=lib + # Tell ltmain to make .dll files, not .so files. + shrext_cmds=".dll" + # FIXME: Setting linknames here is a bad hack. + archive_cmds_CXX='$CC -o $output_objdir/$soname $libobjs $compiler_flags $deplibs -Wl,-dll~linknames=' + archive_expsym_cmds_CXX='if test "x`$SED 1q $export_symbols`" = xEXPORTS; then + $SED -n -e 's/\\\\\\\(.*\\\\\\\)/-link\\\ -EXPORT:\\\\\\\1/' -e '1\\\!p' < $export_symbols > $output_objdir/$soname.exp; + else + $SED -e 's/\\\\\\\(.*\\\\\\\)/-link\\\ -EXPORT:\\\\\\\1/' < $export_symbols > $output_objdir/$soname.exp; + fi~ + $CC -o $tool_output_objdir$soname $libobjs $compiler_flags $deplibs "@$tool_output_objdir$soname.exp" -Wl,-DLL,-IMPLIB:"$tool_output_objdir$libname.dll.lib"~ + linknames=' + # The linker will not automatically build a static lib if we build a DLL. + # _LT_TAGVAR(old_archive_from_new_cmds, CXX)='true' + enable_shared_with_static_runtimes_CXX=yes + # Don't use ranlib + old_postinstall_cmds_CXX='chmod 644 $oldlib' + postlink_cmds_CXX='lt_outputfile="@OUTPUT@"~ + lt_tool_outputfile="@TOOL_OUTPUT@"~ + case $lt_outputfile in + *.exe|*.EXE) ;; + *) + lt_outputfile="$lt_outputfile.exe" + lt_tool_outputfile="$lt_tool_outputfile.exe" + ;; + esac~ + func_to_tool_file "$lt_outputfile"~ + if test "$MANIFEST_TOOL" != ":" && test -f "$lt_outputfile.manifest"; then + $MANIFEST_TOOL -manifest "$lt_tool_outputfile.manifest" -outputresource:"$lt_tool_outputfile" || exit 1; + $RM "$lt_outputfile.manifest"; + fi' + ;; + *) + # g++ + # _LT_TAGVAR(hardcode_libdir_flag_spec, CXX) is actually meaningless, + # as there is no search path for DLLs. + hardcode_libdir_flag_spec_CXX='-L$libdir' + export_dynamic_flag_spec_CXX='${wl}--export-all-symbols' + allow_undefined_flag_CXX=unsupported + always_export_symbols_CXX=no + enable_shared_with_static_runtimes_CXX=yes + + if $LD --help 2>&1 | $GREP 'auto-import' > /dev/null; then + archive_cmds_CXX='$CC -shared -nostdlib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib' + # If the export-symbols file already is a .def file (1st line + # is EXPORTS), use it as is; otherwise, prepend... + archive_expsym_cmds_CXX='if test "x`$SED 1q $export_symbols`" = xEXPORTS; then + cp $export_symbols $output_objdir/$soname.def; + else + echo EXPORTS > $output_objdir/$soname.def; + cat $export_symbols >> $output_objdir/$soname.def; + fi~ + $CC -shared -nostdlib $output_objdir/$soname.def $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib' + else + ld_shlibs_CXX=no + fi + ;; + esac + ;; + darwin* | rhapsody*) + + + archive_cmds_need_lc_CXX=no + hardcode_direct_CXX=no + hardcode_automatic_CXX=yes + hardcode_shlibpath_var_CXX=unsupported + if test "$lt_cv_ld_force_load" = "yes"; then + whole_archive_flag_spec_CXX='`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience ${wl}-force_load,$conv\"; done; func_echo_all \"$new_convenience\"`' + + else + whole_archive_flag_spec_CXX='' + fi + link_all_deplibs_CXX=yes + allow_undefined_flag_CXX="$_lt_dar_allow_undefined" + case $cc_basename in + ifort*) _lt_dar_can_shared=yes ;; + *) _lt_dar_can_shared=$GCC ;; + esac + if test "$_lt_dar_can_shared" = "yes"; then + output_verbose_link_cmd=func_echo_all + archive_cmds_CXX="\$CC -dynamiclib \$allow_undefined_flag -o \$lib \$libobjs \$deplibs \$compiler_flags -install_name \$rpath/\$soname \$verstring $_lt_dar_single_mod${_lt_dsymutil}" + module_cmds_CXX="\$CC \$allow_undefined_flag -o \$lib -bundle \$libobjs \$deplibs \$compiler_flags${_lt_dsymutil}" + archive_expsym_cmds_CXX="sed 's,^,_,' < \$export_symbols > \$output_objdir/\${libname}-symbols.expsym~\$CC -dynamiclib \$allow_undefined_flag -o \$lib \$libobjs \$deplibs \$compiler_flags -install_name \$rpath/\$soname \$verstring ${_lt_dar_single_mod}${_lt_dar_export_syms}${_lt_dsymutil}" + module_expsym_cmds_CXX="sed -e 's,^,_,' < \$export_symbols > \$output_objdir/\${libname}-symbols.expsym~\$CC \$allow_undefined_flag -o \$lib -bundle \$libobjs \$deplibs \$compiler_flags${_lt_dar_export_syms}${_lt_dsymutil}" + if test "$lt_cv_apple_cc_single_mod" != "yes"; then + archive_cmds_CXX="\$CC -r -keep_private_externs -nostdlib -o \${lib}-master.o \$libobjs~\$CC -dynamiclib \$allow_undefined_flag -o \$lib \${lib}-master.o \$deplibs \$compiler_flags -install_name \$rpath/\$soname \$verstring${_lt_dsymutil}" + archive_expsym_cmds_CXX="sed 's,^,_,' < \$export_symbols > \$output_objdir/\${libname}-symbols.expsym~\$CC -r -keep_private_externs -nostdlib -o \${lib}-master.o \$libobjs~\$CC -dynamiclib \$allow_undefined_flag -o \$lib \${lib}-master.o \$deplibs \$compiler_flags -install_name \$rpath/\$soname \$verstring${_lt_dar_export_syms}${_lt_dsymutil}" + fi + + else + ld_shlibs_CXX=no + fi + + ;; + + dgux*) + case $cc_basename in + ec++*) + # FIXME: insert proper C++ library support + ld_shlibs_CXX=no + ;; + ghcx*) + # Green Hills C++ Compiler + # FIXME: insert proper C++ library support + ld_shlibs_CXX=no + ;; + *) + # FIXME: insert proper C++ library support + ld_shlibs_CXX=no + ;; + esac + ;; + + freebsd2.*) + # C++ shared libraries reported to be fairly broken before + # switch to ELF + ld_shlibs_CXX=no + ;; + + freebsd-elf*) + archive_cmds_need_lc_CXX=no + ;; + + freebsd* | dragonfly*) + # FreeBSD 3 and later use GNU C++ and GNU ld with standard ELF + # conventions + ld_shlibs_CXX=yes + ;; + + gnu*) + ;; + + haiku*) + archive_cmds_CXX='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + link_all_deplibs_CXX=yes + ;; + + hpux9*) + hardcode_libdir_flag_spec_CXX='${wl}+b ${wl}$libdir' + hardcode_libdir_separator_CXX=: + export_dynamic_flag_spec_CXX='${wl}-E' + hardcode_direct_CXX=yes + hardcode_minus_L_CXX=yes # Not in the search PATH, + # but as the default + # location of the library. + + case $cc_basename in + CC*) + # FIXME: insert proper C++ library support + ld_shlibs_CXX=no + ;; + aCC*) + archive_cmds_CXX='$RM $output_objdir/$soname~$CC -b ${wl}+b ${wl}$install_libdir -o $output_objdir/$soname $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib' + # Commands to make compiler produce verbose output that lists + # what "hidden" libraries, object files and flags are used when + # linking a shared library. + # + # There doesn't appear to be a way to prevent this compiler from + # explicitly linking system object files so we need to strip them + # from the output so that they don't get included in the library + # dependencies. + output_verbose_link_cmd='templist=`($CC -b $CFLAGS -v conftest.$objext 2>&1) | $EGREP "\-L"`; list=""; for z in $templist; do case $z in conftest.$objext) list="$list $z";; *.$objext);; *) list="$list $z";;esac; done; func_echo_all "$list"' + ;; + *) + if test "$GXX" = yes; then + archive_cmds_CXX='$RM $output_objdir/$soname~$CC -shared -nostdlib $pic_flag ${wl}+b ${wl}$install_libdir -o $output_objdir/$soname $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib' + else + # FIXME: insert proper C++ library support + ld_shlibs_CXX=no + fi + ;; + esac + ;; + + hpux10*|hpux11*) + if test $with_gnu_ld = no; then + hardcode_libdir_flag_spec_CXX='${wl}+b ${wl}$libdir' + hardcode_libdir_separator_CXX=: + + case $host_cpu in + hppa*64*|ia64*) + ;; + *) + export_dynamic_flag_spec_CXX='${wl}-E' + ;; + esac + fi + case $host_cpu in + hppa*64*|ia64*) + hardcode_direct_CXX=no + hardcode_shlibpath_var_CXX=no + ;; + *) + hardcode_direct_CXX=yes + hardcode_direct_absolute_CXX=yes + hardcode_minus_L_CXX=yes # Not in the search PATH, + # but as the default + # location of the library. + ;; + esac + + case $cc_basename in + CC*) + # FIXME: insert proper C++ library support + ld_shlibs_CXX=no + ;; + aCC*) + case $host_cpu in + hppa*64*) + archive_cmds_CXX='$CC -b ${wl}+h ${wl}$soname -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags' + ;; + ia64*) + archive_cmds_CXX='$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags' + ;; + *) + archive_cmds_CXX='$CC -b ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags' + ;; + esac + # Commands to make compiler produce verbose output that lists + # what "hidden" libraries, object files and flags are used when + # linking a shared library. + # + # There doesn't appear to be a way to prevent this compiler from + # explicitly linking system object files so we need to strip them + # from the output so that they don't get included in the library + # dependencies. + output_verbose_link_cmd='templist=`($CC -b $CFLAGS -v conftest.$objext 2>&1) | $GREP "\-L"`; list=""; for z in $templist; do case $z in conftest.$objext) list="$list $z";; *.$objext);; *) list="$list $z";;esac; done; func_echo_all "$list"' + ;; + *) + if test "$GXX" = yes; then + if test $with_gnu_ld = no; then + case $host_cpu in + hppa*64*) + archive_cmds_CXX='$CC -shared -nostdlib -fPIC ${wl}+h ${wl}$soname -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags' + ;; + ia64*) + archive_cmds_CXX='$CC -shared -nostdlib $pic_flag ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags' + ;; + *) + archive_cmds_CXX='$CC -shared -nostdlib $pic_flag ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags' + ;; + esac + fi + else + # FIXME: insert proper C++ library support + ld_shlibs_CXX=no + fi + ;; + esac + ;; + + interix[3-9]*) + hardcode_direct_CXX=no + hardcode_shlibpath_var_CXX=no + hardcode_libdir_flag_spec_CXX='${wl}-rpath,$libdir' + export_dynamic_flag_spec_CXX='${wl}-E' + # Hack: On Interix 3.x, we cannot compile PIC because of a broken gcc. + # Instead, shared libraries are loaded at an image base (0x10000000 by + # default) and relocated if they conflict, which is a slow very memory + # consuming and fragmenting process. To avoid this, we pick a random, + # 256 KiB-aligned image base between 0x50000000 and 0x6FFC0000 at link + # time. Moving up from 0x10000000 also allows more sbrk(2) space. + archive_cmds_CXX='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib' + archive_expsym_cmds_CXX='sed "s,^,_," $export_symbols >$output_objdir/$soname.expsym~$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--retain-symbols-file,$output_objdir/$soname.expsym ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib' + ;; + irix5* | irix6*) + case $cc_basename in + CC*) + # SGI C++ + archive_cmds_CXX='$CC -shared -all -multigot $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib' + + # Archives containing C++ object files must be created using + # "CC -ar", where "CC" is the IRIX C++ compiler. This is + # necessary to make sure instantiated templates are included + # in the archive. + old_archive_cmds_CXX='$CC -ar -WR,-u -o $oldlib $oldobjs' + ;; + *) + if test "$GXX" = yes; then + if test "$with_gnu_ld" = no; then + archive_cmds_CXX='$CC -shared $pic_flag -nostdlib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' + else + archive_cmds_CXX='$CC -shared $pic_flag -nostdlib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` -o $lib' + fi + fi + link_all_deplibs_CXX=yes + ;; + esac + hardcode_libdir_flag_spec_CXX='${wl}-rpath ${wl}$libdir' + hardcode_libdir_separator_CXX=: + inherit_rpath_CXX=yes + ;; + + linux* | k*bsd*-gnu | kopensolaris*-gnu) + case $cc_basename in + KCC*) + # Kuck and Associates, Inc. (KAI) C++ Compiler + + # KCC will only create a shared library if the output file + # ends with ".so" (or ".sl" for HP-UX), so rename the library + # to its proper name (with version) after linking. + archive_cmds_CXX='tempext=`echo $shared_ext | $SED -e '\''s/\([^()0-9A-Za-z{}]\)/\\\\\1/g'\''`; templib=`echo $lib | $SED -e "s/\${tempext}\..*/.so/"`; $CC $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags --soname $soname -o \$templib; mv \$templib $lib' + archive_expsym_cmds_CXX='tempext=`echo $shared_ext | $SED -e '\''s/\([^()0-9A-Za-z{}]\)/\\\\\1/g'\''`; templib=`echo $lib | $SED -e "s/\${tempext}\..*/.so/"`; $CC $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags --soname $soname -o \$templib ${wl}-retain-symbols-file,$export_symbols; mv \$templib $lib' + # Commands to make compiler produce verbose output that lists + # what "hidden" libraries, object files and flags are used when + # linking a shared library. + # + # There doesn't appear to be a way to prevent this compiler from + # explicitly linking system object files so we need to strip them + # from the output so that they don't get included in the library + # dependencies. + output_verbose_link_cmd='templist=`$CC $CFLAGS -v conftest.$objext -o libconftest$shared_ext 2>&1 | $GREP "ld"`; rm -f libconftest$shared_ext; list=""; for z in $templist; do case $z in conftest.$objext) list="$list $z";; *.$objext);; *) list="$list $z";;esac; done; func_echo_all "$list"' + + hardcode_libdir_flag_spec_CXX='${wl}-rpath,$libdir' + export_dynamic_flag_spec_CXX='${wl}--export-dynamic' + + # Archives containing C++ object files must be created using + # "CC -Bstatic", where "CC" is the KAI C++ compiler. + old_archive_cmds_CXX='$CC -Bstatic -o $oldlib $oldobjs' + ;; + icpc* | ecpc* ) + # Intel C++ + with_gnu_ld=yes + # version 8.0 and above of icpc choke on multiply defined symbols + # if we add $predep_objects and $postdep_objects, however 7.1 and + # earlier do not add the objects themselves. + case `$CC -V 2>&1` in + *"Version 7."*) + archive_cmds_CXX='$CC -shared $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname $wl$soname -o $lib' + archive_expsym_cmds_CXX='$CC -shared $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' + ;; + *) # Version 8.0 or newer + tmp_idyn= + case $host_cpu in + ia64*) tmp_idyn=' -i_dynamic';; + esac + archive_cmds_CXX='$CC -shared'"$tmp_idyn"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + archive_expsym_cmds_CXX='$CC -shared'"$tmp_idyn"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' + ;; + esac + archive_cmds_need_lc_CXX=no + hardcode_libdir_flag_spec_CXX='${wl}-rpath,$libdir' + export_dynamic_flag_spec_CXX='${wl}--export-dynamic' + whole_archive_flag_spec_CXX='${wl}--whole-archive$convenience ${wl}--no-whole-archive' + ;; + pgCC* | pgcpp*) + # Portland Group C++ compiler + case `$CC -V` in + *pgCC\ [1-5].* | *pgcpp\ [1-5].*) + prelink_cmds_CXX='tpldir=Template.dir~ + rm -rf $tpldir~ + $CC --prelink_objects --instantiation_dir $tpldir $objs $libobjs $compile_deplibs~ + compile_command="$compile_command `find $tpldir -name \*.o | sort | $NL2SP`"' + old_archive_cmds_CXX='tpldir=Template.dir~ + rm -rf $tpldir~ + $CC --prelink_objects --instantiation_dir $tpldir $oldobjs$old_deplibs~ + $AR $AR_FLAGS $oldlib$oldobjs$old_deplibs `find $tpldir -name \*.o | sort | $NL2SP`~ + $RANLIB $oldlib' + archive_cmds_CXX='tpldir=Template.dir~ + rm -rf $tpldir~ + $CC --prelink_objects --instantiation_dir $tpldir $predep_objects $libobjs $deplibs $convenience $postdep_objects~ + $CC -shared $pic_flag $predep_objects $libobjs $deplibs `find $tpldir -name \*.o | sort | $NL2SP` $postdep_objects $compiler_flags ${wl}-soname ${wl}$soname -o $lib' + archive_expsym_cmds_CXX='tpldir=Template.dir~ + rm -rf $tpldir~ + $CC --prelink_objects --instantiation_dir $tpldir $predep_objects $libobjs $deplibs $convenience $postdep_objects~ + $CC -shared $pic_flag $predep_objects $libobjs $deplibs `find $tpldir -name \*.o | sort | $NL2SP` $postdep_objects $compiler_flags ${wl}-soname ${wl}$soname ${wl}-retain-symbols-file ${wl}$export_symbols -o $lib' + ;; + *) # Version 6 and above use weak symbols + archive_cmds_CXX='$CC -shared $pic_flag $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname ${wl}$soname -o $lib' + archive_expsym_cmds_CXX='$CC -shared $pic_flag $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname ${wl}$soname ${wl}-retain-symbols-file ${wl}$export_symbols -o $lib' + ;; + esac + + hardcode_libdir_flag_spec_CXX='${wl}--rpath ${wl}$libdir' + export_dynamic_flag_spec_CXX='${wl}--export-dynamic' + whole_archive_flag_spec_CXX='${wl}--whole-archive`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' + ;; + cxx*) + # Compaq C++ + archive_cmds_CXX='$CC -shared $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname $wl$soname -o $lib' + archive_expsym_cmds_CXX='$CC -shared $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname $wl$soname -o $lib ${wl}-retain-symbols-file $wl$export_symbols' + + runpath_var=LD_RUN_PATH + hardcode_libdir_flag_spec_CXX='-rpath $libdir' + hardcode_libdir_separator_CXX=: + + # Commands to make compiler produce verbose output that lists + # what "hidden" libraries, object files and flags are used when + # linking a shared library. + # + # There doesn't appear to be a way to prevent this compiler from + # explicitly linking system object files so we need to strip them + # from the output so that they don't get included in the library + # dependencies. + output_verbose_link_cmd='templist=`$CC -shared $CFLAGS -v conftest.$objext 2>&1 | $GREP "ld"`; templist=`func_echo_all "$templist" | $SED "s/\(^.*ld.*\)\( .*ld .*$\)/\1/"`; list=""; for z in $templist; do case $z in conftest.$objext) list="$list $z";; *.$objext);; *) list="$list $z";;esac; done; func_echo_all "X$list" | $Xsed' + ;; + xl* | mpixl* | bgxl*) + # IBM XL 8.0 on PPC, with GNU ld + hardcode_libdir_flag_spec_CXX='${wl}-rpath ${wl}$libdir' + export_dynamic_flag_spec_CXX='${wl}--export-dynamic' + archive_cmds_CXX='$CC -qmkshrobj $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + if test "x$supports_anon_versioning" = xyes; then + archive_expsym_cmds_CXX='echo "{ global:" > $output_objdir/$libname.ver~ + cat $export_symbols | sed -e "s/\(.*\)/\1;/" >> $output_objdir/$libname.ver~ + echo "local: *; };" >> $output_objdir/$libname.ver~ + $CC -qmkshrobj $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-version-script ${wl}$output_objdir/$libname.ver -o $lib' + fi + ;; + *) + case `$CC -V 2>&1 | sed 5q` in + *Sun\ C*) + # Sun C++ 5.9 + no_undefined_flag_CXX=' -zdefs' + archive_cmds_CXX='$CC -G${allow_undefined_flag} -h$soname -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags' + archive_expsym_cmds_CXX='$CC -G${allow_undefined_flag} -h$soname -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-retain-symbols-file ${wl}$export_symbols' + hardcode_libdir_flag_spec_CXX='-R$libdir' + whole_archive_flag_spec_CXX='${wl}--whole-archive`new_convenience=; for conv in $convenience\"\"; do test -z \"$conv\" || new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' + compiler_needs_object_CXX=yes + + # Not sure whether something based on + # $CC $CFLAGS -v conftest.$objext -o libconftest$shared_ext 2>&1 + # would be better. + output_verbose_link_cmd='func_echo_all' + + # Archives containing C++ object files must be created using + # "CC -xar", where "CC" is the Sun C++ compiler. This is + # necessary to make sure instantiated templates are included + # in the archive. + old_archive_cmds_CXX='$CC -xar -o $oldlib $oldobjs' + ;; + esac + ;; + esac + ;; + + lynxos*) + # FIXME: insert proper C++ library support + ld_shlibs_CXX=no + ;; + + m88k*) + # FIXME: insert proper C++ library support + ld_shlibs_CXX=no + ;; + + mvs*) + case $cc_basename in + cxx*) + # FIXME: insert proper C++ library support + ld_shlibs_CXX=no + ;; + *) + # FIXME: insert proper C++ library support + ld_shlibs_CXX=no + ;; + esac + ;; + + netbsd*) + if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then + archive_cmds_CXX='$LD -Bshareable -o $lib $predep_objects $libobjs $deplibs $postdep_objects $linker_flags' + wlarc= + hardcode_libdir_flag_spec_CXX='-R$libdir' + hardcode_direct_CXX=yes + hardcode_shlibpath_var_CXX=no + fi + # Workaround some broken pre-1.5 toolchains + output_verbose_link_cmd='$CC -shared $CFLAGS -v conftest.$objext 2>&1 | $GREP conftest.$objext | $SED -e "s:-lgcc -lc -lgcc::"' + ;; + + *nto* | *qnx*) + ld_shlibs_CXX=yes + ;; + + openbsd2*) + # C++ shared libraries are fairly broken + ld_shlibs_CXX=no + ;; + + openbsd*) + if test -f /usr/libexec/ld.so; then + hardcode_direct_CXX=yes + hardcode_shlibpath_var_CXX=no + hardcode_direct_absolute_CXX=yes + archive_cmds_CXX='$CC -shared $pic_flag $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags -o $lib' + hardcode_libdir_flag_spec_CXX='${wl}-rpath,$libdir' + if test -z "`echo __ELF__ | $CC -E - | grep __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then + archive_expsym_cmds_CXX='$CC -shared $pic_flag $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-retain-symbols-file,$export_symbols -o $lib' + export_dynamic_flag_spec_CXX='${wl}-E' + whole_archive_flag_spec_CXX="$wlarc"'--whole-archive$convenience '"$wlarc"'--no-whole-archive' + fi + output_verbose_link_cmd=func_echo_all + else + ld_shlibs_CXX=no + fi + ;; + + osf3* | osf4* | osf5*) + case $cc_basename in + KCC*) + # Kuck and Associates, Inc. (KAI) C++ Compiler + + # KCC will only create a shared library if the output file + # ends with ".so" (or ".sl" for HP-UX), so rename the library + # to its proper name (with version) after linking. + archive_cmds_CXX='tempext=`echo $shared_ext | $SED -e '\''s/\([^()0-9A-Za-z{}]\)/\\\\\1/g'\''`; templib=`echo "$lib" | $SED -e "s/\${tempext}\..*/.so/"`; $CC $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags --soname $soname -o \$templib; mv \$templib $lib' + + hardcode_libdir_flag_spec_CXX='${wl}-rpath,$libdir' + hardcode_libdir_separator_CXX=: + + # Archives containing C++ object files must be created using + # the KAI C++ compiler. + case $host in + osf3*) old_archive_cmds_CXX='$CC -Bstatic -o $oldlib $oldobjs' ;; + *) old_archive_cmds_CXX='$CC -o $oldlib $oldobjs' ;; + esac + ;; + RCC*) + # Rational C++ 2.4.1 + # FIXME: insert proper C++ library support + ld_shlibs_CXX=no + ;; + cxx*) + case $host in + osf3*) + allow_undefined_flag_CXX=' ${wl}-expect_unresolved ${wl}\*' + archive_cmds_CXX='$CC -shared${allow_undefined_flag} $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname $soname `test -n "$verstring" && func_echo_all "${wl}-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib' + hardcode_libdir_flag_spec_CXX='${wl}-rpath ${wl}$libdir' + ;; + *) + allow_undefined_flag_CXX=' -expect_unresolved \*' + archive_cmds_CXX='$CC -shared${allow_undefined_flag} $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags -msym -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib' + archive_expsym_cmds_CXX='for i in `cat $export_symbols`; do printf "%s %s\\n" -exported_symbol "\$i" >> $lib.exp; done~ + echo "-hidden">> $lib.exp~ + $CC -shared$allow_undefined_flag $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags -msym -soname $soname ${wl}-input ${wl}$lib.exp `test -n "$verstring" && $ECHO "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib~ + $RM $lib.exp' + hardcode_libdir_flag_spec_CXX='-rpath $libdir' + ;; + esac + + hardcode_libdir_separator_CXX=: + + # Commands to make compiler produce verbose output that lists + # what "hidden" libraries, object files and flags are used when + # linking a shared library. + # + # There doesn't appear to be a way to prevent this compiler from + # explicitly linking system object files so we need to strip them + # from the output so that they don't get included in the library + # dependencies. + output_verbose_link_cmd='templist=`$CC -shared $CFLAGS -v conftest.$objext 2>&1 | $GREP "ld" | $GREP -v "ld:"`; templist=`func_echo_all "$templist" | $SED "s/\(^.*ld.*\)\( .*ld.*$\)/\1/"`; list=""; for z in $templist; do case $z in conftest.$objext) list="$list $z";; *.$objext);; *) list="$list $z";;esac; done; func_echo_all "$list"' + ;; + *) + if test "$GXX" = yes && test "$with_gnu_ld" = no; then + allow_undefined_flag_CXX=' ${wl}-expect_unresolved ${wl}\*' + case $host in + osf3*) + archive_cmds_CXX='$CC -shared -nostdlib ${allow_undefined_flag} $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' + ;; + *) + archive_cmds_CXX='$CC -shared $pic_flag -nostdlib ${allow_undefined_flag} $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-msym ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' + ;; + esac + + hardcode_libdir_flag_spec_CXX='${wl}-rpath ${wl}$libdir' + hardcode_libdir_separator_CXX=: + + # Commands to make compiler produce verbose output that lists + # what "hidden" libraries, object files and flags are used when + # linking a shared library. + output_verbose_link_cmd='$CC -shared $CFLAGS -v conftest.$objext 2>&1 | $GREP -v "^Configured with:" | $GREP "\-L"' + + else + # FIXME: insert proper C++ library support + ld_shlibs_CXX=no + fi + ;; + esac + ;; + + psos*) + # FIXME: insert proper C++ library support + ld_shlibs_CXX=no + ;; + + sunos4*) + case $cc_basename in + CC*) + # Sun C++ 4.x + # FIXME: insert proper C++ library support + ld_shlibs_CXX=no + ;; + lcc*) + # Lucid + # FIXME: insert proper C++ library support + ld_shlibs_CXX=no + ;; + *) + # FIXME: insert proper C++ library support + ld_shlibs_CXX=no + ;; + esac + ;; + + solaris*) + case $cc_basename in + CC* | sunCC*) + # Sun C++ 4.2, 5.x and Centerline C++ + archive_cmds_need_lc_CXX=yes + no_undefined_flag_CXX=' -zdefs' + archive_cmds_CXX='$CC -G${allow_undefined_flag} -h$soname -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags' + archive_expsym_cmds_CXX='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~ + $CC -G${allow_undefined_flag} ${wl}-M ${wl}$lib.exp -h$soname -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags~$RM $lib.exp' + + hardcode_libdir_flag_spec_CXX='-R$libdir' + hardcode_shlibpath_var_CXX=no + case $host_os in + solaris2.[0-5] | solaris2.[0-5].*) ;; + *) + # The compiler driver will combine and reorder linker options, + # but understands `-z linker_flag'. + # Supported since Solaris 2.6 (maybe 2.5.1?) + whole_archive_flag_spec_CXX='-z allextract$convenience -z defaultextract' + ;; + esac + link_all_deplibs_CXX=yes + + output_verbose_link_cmd='func_echo_all' + + # Archives containing C++ object files must be created using + # "CC -xar", where "CC" is the Sun C++ compiler. This is + # necessary to make sure instantiated templates are included + # in the archive. + old_archive_cmds_CXX='$CC -xar -o $oldlib $oldobjs' + ;; + gcx*) + # Green Hills C++ Compiler + archive_cmds_CXX='$CC -shared $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-h $wl$soname -o $lib' + + # The C++ compiler must be used to create the archive. + old_archive_cmds_CXX='$CC $LDFLAGS -archive -o $oldlib $oldobjs' + ;; + *) + # GNU C++ compiler with Solaris linker + if test "$GXX" = yes && test "$with_gnu_ld" = no; then + no_undefined_flag_CXX=' ${wl}-z ${wl}defs' + if $CC --version | $GREP -v '^2\.7' > /dev/null; then + archive_cmds_CXX='$CC -shared $pic_flag -nostdlib $LDFLAGS $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-h $wl$soname -o $lib' + archive_expsym_cmds_CXX='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~ + $CC -shared $pic_flag -nostdlib ${wl}-M $wl$lib.exp -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags~$RM $lib.exp' + + # Commands to make compiler produce verbose output that lists + # what "hidden" libraries, object files and flags are used when + # linking a shared library. + output_verbose_link_cmd='$CC -shared $CFLAGS -v conftest.$objext 2>&1 | $GREP -v "^Configured with:" | $GREP "\-L"' + else + # g++ 2.7 appears to require `-G' NOT `-shared' on this + # platform. + archive_cmds_CXX='$CC -G -nostdlib $LDFLAGS $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-h $wl$soname -o $lib' + archive_expsym_cmds_CXX='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~ + $CC -G -nostdlib ${wl}-M $wl$lib.exp -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags~$RM $lib.exp' + + # Commands to make compiler produce verbose output that lists + # what "hidden" libraries, object files and flags are used when + # linking a shared library. + output_verbose_link_cmd='$CC -G $CFLAGS -v conftest.$objext 2>&1 | $GREP -v "^Configured with:" | $GREP "\-L"' + fi + + hardcode_libdir_flag_spec_CXX='${wl}-R $wl$libdir' + case $host_os in + solaris2.[0-5] | solaris2.[0-5].*) ;; + *) + whole_archive_flag_spec_CXX='${wl}-z ${wl}allextract$convenience ${wl}-z ${wl}defaultextract' + ;; + esac + fi + ;; + esac + ;; + + sysv4*uw2* | sysv5OpenUNIX* | sysv5UnixWare7.[01].[10]* | unixware7* | sco3.2v5.0.[024]*) + no_undefined_flag_CXX='${wl}-z,text' + archive_cmds_need_lc_CXX=no + hardcode_shlibpath_var_CXX=no + runpath_var='LD_RUN_PATH' + + case $cc_basename in + CC*) + archive_cmds_CXX='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds_CXX='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + ;; + *) + archive_cmds_CXX='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds_CXX='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + ;; + esac + ;; + + sysv5* | sco3.2v5* | sco5v6*) + # Note: We can NOT use -z defs as we might desire, because we do not + # link with -lc, and that would cause any symbols used from libc to + # always be unresolved, which means just about no library would + # ever link correctly. If we're not using GNU ld we use -z text + # though, which does catch some bad symbols but isn't as heavy-handed + # as -z defs. + no_undefined_flag_CXX='${wl}-z,text' + allow_undefined_flag_CXX='${wl}-z,nodefs' + archive_cmds_need_lc_CXX=no + hardcode_shlibpath_var_CXX=no + hardcode_libdir_flag_spec_CXX='${wl}-R,$libdir' + hardcode_libdir_separator_CXX=':' + link_all_deplibs_CXX=yes + export_dynamic_flag_spec_CXX='${wl}-Bexport' + runpath_var='LD_RUN_PATH' + + case $cc_basename in + CC*) + archive_cmds_CXX='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds_CXX='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + old_archive_cmds_CXX='$CC -Tprelink_objects $oldobjs~ + '"$old_archive_cmds_CXX" + reload_cmds_CXX='$CC -Tprelink_objects $reload_objs~ + '"$reload_cmds_CXX" + ;; + *) + archive_cmds_CXX='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds_CXX='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + ;; + esac + ;; + + tandem*) + case $cc_basename in + NCC*) + # NonStop-UX NCC 3.20 + # FIXME: insert proper C++ library support + ld_shlibs_CXX=no + ;; + *) + # FIXME: insert proper C++ library support + ld_shlibs_CXX=no + ;; + esac + ;; + + vxworks*) + # FIXME: insert proper C++ library support + ld_shlibs_CXX=no + ;; + + *) + # FIXME: insert proper C++ library support + ld_shlibs_CXX=no + ;; + esac + + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ld_shlibs_CXX" >&5 +$as_echo "$ld_shlibs_CXX" >&6; } + test "$ld_shlibs_CXX" = no && can_build_shared=no + + GCC_CXX="$GXX" + LD_CXX="$LD" + + ## CAVEAT EMPTOR: + ## There is no encapsulation within the following macros, do not change + ## the running order or otherwise move them around unless you know exactly + ## what you are doing... + # Dependencies to place before and after the object being linked: +predep_objects_CXX= +postdep_objects_CXX= +predeps_CXX= +postdeps_CXX= +compiler_lib_search_path_CXX= + +cat > conftest.$ac_ext <<_LT_EOF +class Foo +{ +public: + Foo (void) { a = 0; } +private: + int a; +}; +_LT_EOF + + +_lt_libdeps_save_CFLAGS=$CFLAGS +case "$CC $CFLAGS " in #( +*\ -flto*\ *) CFLAGS="$CFLAGS -fno-lto" ;; +*\ -fwhopr*\ *) CFLAGS="$CFLAGS -fno-whopr" ;; +*\ -fuse-linker-plugin*\ *) CFLAGS="$CFLAGS -fno-use-linker-plugin" ;; +esac + +if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 + (eval $ac_compile) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then + # Parse the compiler output and extract the necessary + # objects, libraries and library flags. + + # Sentinel used to keep track of whether or not we are before + # the conftest object file. + pre_test_object_deps_done=no + + for p in `eval "$output_verbose_link_cmd"`; do + case ${prev}${p} in + + -L* | -R* | -l*) + # Some compilers place space between "-{L,R}" and the path. + # Remove the space. + if test $p = "-L" || + test $p = "-R"; then + prev=$p + continue + fi + + # Expand the sysroot to ease extracting the directories later. + if test -z "$prev"; then + case $p in + -L*) func_stripname_cnf '-L' '' "$p"; prev=-L; p=$func_stripname_result ;; + -R*) func_stripname_cnf '-R' '' "$p"; prev=-R; p=$func_stripname_result ;; + -l*) func_stripname_cnf '-l' '' "$p"; prev=-l; p=$func_stripname_result ;; + esac + fi + case $p in + =*) func_stripname_cnf '=' '' "$p"; p=$lt_sysroot$func_stripname_result ;; + esac + if test "$pre_test_object_deps_done" = no; then + case ${prev} in + -L | -R) + # Internal compiler library paths should come after those + # provided the user. The postdeps already come after the + # user supplied libs so there is no need to process them. + if test -z "$compiler_lib_search_path_CXX"; then + compiler_lib_search_path_CXX="${prev}${p}" + else + compiler_lib_search_path_CXX="${compiler_lib_search_path_CXX} ${prev}${p}" + fi + ;; + # The "-l" case would never come before the object being + # linked, so don't bother handling this case. + esac + else + if test -z "$postdeps_CXX"; then + postdeps_CXX="${prev}${p}" + else + postdeps_CXX="${postdeps_CXX} ${prev}${p}" + fi + fi + prev= + ;; + + *.lto.$objext) ;; # Ignore GCC LTO objects + *.$objext) + # This assumes that the test object file only shows up + # once in the compiler output. + if test "$p" = "conftest.$objext"; then + pre_test_object_deps_done=yes + continue + fi + + if test "$pre_test_object_deps_done" = no; then + if test -z "$predep_objects_CXX"; then + predep_objects_CXX="$p" + else + predep_objects_CXX="$predep_objects_CXX $p" + fi + else + if test -z "$postdep_objects_CXX"; then + postdep_objects_CXX="$p" + else + postdep_objects_CXX="$postdep_objects_CXX $p" + fi + fi + ;; + + *) ;; # Ignore the rest. + + esac + done + + # Clean up. + rm -f a.out a.exe +else + echo "libtool.m4: error: problem compiling CXX test program" +fi + +$RM -f confest.$objext +CFLAGS=$_lt_libdeps_save_CFLAGS + +# PORTME: override above test on systems where it is broken +case $host_os in +interix[3-9]*) + # Interix 3.5 installs completely hosed .la files for C++, so rather than + # hack all around it, let's just trust "g++" to DTRT. + predep_objects_CXX= + postdep_objects_CXX= + postdeps_CXX= + ;; + +linux*) + case `$CC -V 2>&1 | sed 5q` in + *Sun\ C*) + # Sun C++ 5.9 + + # The more standards-conforming stlport4 library is + # incompatible with the Cstd library. Avoid specifying + # it if it's in CXXFLAGS. Ignore libCrun as + # -library=stlport4 depends on it. + case " $CXX $CXXFLAGS " in + *" -library=stlport4 "*) + solaris_use_stlport4=yes + ;; + esac + + if test "$solaris_use_stlport4" != yes; then + postdeps_CXX='-library=Cstd -library=Crun' + fi + ;; + esac + ;; + +solaris*) + case $cc_basename in + CC* | sunCC*) + # The more standards-conforming stlport4 library is + # incompatible with the Cstd library. Avoid specifying + # it if it's in CXXFLAGS. Ignore libCrun as + # -library=stlport4 depends on it. + case " $CXX $CXXFLAGS " in + *" -library=stlport4 "*) + solaris_use_stlport4=yes + ;; + esac + + # Adding this requires a known-good setup of shared libraries for + # Sun compiler versions before 5.6, else PIC objects from an old + # archive will be linked into the output, leading to subtle bugs. + if test "$solaris_use_stlport4" != yes; then + postdeps_CXX='-library=Cstd -library=Crun' + fi + ;; + esac + ;; +esac + + +case " $postdeps_CXX " in +*" -lc "*) archive_cmds_need_lc_CXX=no ;; +esac + compiler_lib_search_dirs_CXX= +if test -n "${compiler_lib_search_path_CXX}"; then + compiler_lib_search_dirs_CXX=`echo " ${compiler_lib_search_path_CXX}" | ${SED} -e 's! -L! !g' -e 's!^ !!'` +fi + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + lt_prog_compiler_wl_CXX= +lt_prog_compiler_pic_CXX= +lt_prog_compiler_static_CXX= + + + # C++ specific cases for pic, static, wl, etc. + if test "$GXX" = yes; then + lt_prog_compiler_wl_CXX='-Wl,' + lt_prog_compiler_static_CXX='-static' + + case $host_os in + aix*) + # All AIX code is PIC. + if test "$host_cpu" = ia64; then + # AIX 5 now supports IA64 processor + lt_prog_compiler_static_CXX='-Bstatic' + fi + ;; + + amigaos*) + case $host_cpu in + powerpc) + # see comment about AmigaOS4 .so support + lt_prog_compiler_pic_CXX='-fPIC' + ;; + m68k) + # FIXME: we need at least 68020 code to build shared libraries, but + # adding the `-m68020' flag to GCC prevents building anything better, + # like `-m68040'. + lt_prog_compiler_pic_CXX='-m68020 -resident32 -malways-restore-a4' + ;; + esac + ;; + + beos* | irix5* | irix6* | nonstopux* | osf3* | osf4* | osf5*) + # PIC is the default for these OSes. + ;; + mingw* | cygwin* | os2* | pw32* | cegcc*) + # This hack is so that the source file can tell whether it is being + # built for inclusion in a dll (and should export symbols for example). + # Although the cygwin gcc ignores -fPIC, still need this for old-style + # (--disable-auto-import) libraries + lt_prog_compiler_pic_CXX='-DDLL_EXPORT' + ;; + darwin* | rhapsody*) + # PIC is the default on this platform + # Common symbols not allowed in MH_DYLIB files + lt_prog_compiler_pic_CXX='-fno-common' + ;; + *djgpp*) + # DJGPP does not support shared libraries at all + lt_prog_compiler_pic_CXX= + ;; + haiku*) + # PIC is the default for Haiku. + # The "-static" flag exists, but is broken. + lt_prog_compiler_static_CXX= + ;; + interix[3-9]*) + # Interix 3.x gcc -fpic/-fPIC options generate broken code. + # Instead, we relocate shared libraries at runtime. + ;; + sysv4*MP*) + if test -d /usr/nec; then + lt_prog_compiler_pic_CXX=-Kconform_pic + fi + ;; + hpux*) + # PIC is the default for 64-bit PA HP-UX, but not for 32-bit + # PA HP-UX. On IA64 HP-UX, PIC is the default but the pic flag + # sets the default TLS model and affects inlining. + case $host_cpu in + hppa*64*) + ;; + *) + lt_prog_compiler_pic_CXX='-fPIC' + ;; + esac + ;; + *qnx* | *nto*) + # QNX uses GNU C++, but need to define -shared option too, otherwise + # it will coredump. + lt_prog_compiler_pic_CXX='-fPIC -shared' + ;; + *) + lt_prog_compiler_pic_CXX='-fPIC' + ;; + esac + else + case $host_os in + aix[4-9]*) + # All AIX code is PIC. + if test "$host_cpu" = ia64; then + # AIX 5 now supports IA64 processor + lt_prog_compiler_static_CXX='-Bstatic' + else + lt_prog_compiler_static_CXX='-bnso -bI:/lib/syscalls.exp' + fi + ;; + chorus*) + case $cc_basename in + cxch68*) + # Green Hills C++ Compiler + # _LT_TAGVAR(lt_prog_compiler_static, CXX)="--no_auto_instantiation -u __main -u __premain -u _abort -r $COOL_DIR/lib/libOrb.a $MVME_DIR/lib/CC/libC.a $MVME_DIR/lib/classix/libcx.s.a" + ;; + esac + ;; + mingw* | cygwin* | os2* | pw32* | cegcc*) + # This hack is so that the source file can tell whether it is being + # built for inclusion in a dll (and should export symbols for example). + lt_prog_compiler_pic_CXX='-DDLL_EXPORT' + ;; + dgux*) + case $cc_basename in + ec++*) + lt_prog_compiler_pic_CXX='-KPIC' + ;; + ghcx*) + # Green Hills C++ Compiler + lt_prog_compiler_pic_CXX='-pic' + ;; + *) + ;; + esac + ;; + freebsd* | dragonfly*) + # FreeBSD uses GNU C++ + ;; + hpux9* | hpux10* | hpux11*) + case $cc_basename in + CC*) + lt_prog_compiler_wl_CXX='-Wl,' + lt_prog_compiler_static_CXX='${wl}-a ${wl}archive' + if test "$host_cpu" != ia64; then + lt_prog_compiler_pic_CXX='+Z' + fi + ;; + aCC*) + lt_prog_compiler_wl_CXX='-Wl,' + lt_prog_compiler_static_CXX='${wl}-a ${wl}archive' + case $host_cpu in + hppa*64*|ia64*) + # +Z the default + ;; + *) + lt_prog_compiler_pic_CXX='+Z' + ;; + esac + ;; + *) + ;; + esac + ;; + interix*) + # This is c89, which is MS Visual C++ (no shared libs) + # Anyone wants to do a port? + ;; + irix5* | irix6* | nonstopux*) + case $cc_basename in + CC*) + lt_prog_compiler_wl_CXX='-Wl,' + lt_prog_compiler_static_CXX='-non_shared' + # CC pic flag -KPIC is the default. + ;; + *) + ;; + esac + ;; + linux* | k*bsd*-gnu | kopensolaris*-gnu) + case $cc_basename in + KCC*) + # KAI C++ Compiler + lt_prog_compiler_wl_CXX='--backend -Wl,' + lt_prog_compiler_pic_CXX='-fPIC' + ;; + ecpc* ) + # old Intel C++ for x86_64 which still supported -KPIC. + lt_prog_compiler_wl_CXX='-Wl,' + lt_prog_compiler_pic_CXX='-KPIC' + lt_prog_compiler_static_CXX='-static' + ;; + icpc* ) + # Intel C++, used to be incompatible with GCC. + # ICC 10 doesn't accept -KPIC any more. + lt_prog_compiler_wl_CXX='-Wl,' + lt_prog_compiler_pic_CXX='-fPIC' + lt_prog_compiler_static_CXX='-static' + ;; + pgCC* | pgcpp*) + # Portland Group C++ compiler + lt_prog_compiler_wl_CXX='-Wl,' + lt_prog_compiler_pic_CXX='-fpic' + lt_prog_compiler_static_CXX='-Bstatic' + ;; + cxx*) + # Compaq C++ + # Make sure the PIC flag is empty. It appears that all Alpha + # Linux and Compaq Tru64 Unix objects are PIC. + lt_prog_compiler_pic_CXX= + lt_prog_compiler_static_CXX='-non_shared' + ;; + xlc* | xlC* | bgxl[cC]* | mpixl[cC]*) + # IBM XL 8.0, 9.0 on PPC and BlueGene + lt_prog_compiler_wl_CXX='-Wl,' + lt_prog_compiler_pic_CXX='-qpic' + lt_prog_compiler_static_CXX='-qstaticlink' + ;; + *) + case `$CC -V 2>&1 | sed 5q` in + *Sun\ C*) + # Sun C++ 5.9 + lt_prog_compiler_pic_CXX='-KPIC' + lt_prog_compiler_static_CXX='-Bstatic' + lt_prog_compiler_wl_CXX='-Qoption ld ' + ;; + esac + ;; + esac + ;; + lynxos*) + ;; + m88k*) + ;; + mvs*) + case $cc_basename in + cxx*) + lt_prog_compiler_pic_CXX='-W c,exportall' + ;; + *) + ;; + esac + ;; + netbsd*) + ;; + *qnx* | *nto*) + # QNX uses GNU C++, but need to define -shared option too, otherwise + # it will coredump. + lt_prog_compiler_pic_CXX='-fPIC -shared' + ;; + osf3* | osf4* | osf5*) + case $cc_basename in + KCC*) + lt_prog_compiler_wl_CXX='--backend -Wl,' + ;; + RCC*) + # Rational C++ 2.4.1 + lt_prog_compiler_pic_CXX='-pic' + ;; + cxx*) + # Digital/Compaq C++ + lt_prog_compiler_wl_CXX='-Wl,' + # Make sure the PIC flag is empty. It appears that all Alpha + # Linux and Compaq Tru64 Unix objects are PIC. + lt_prog_compiler_pic_CXX= + lt_prog_compiler_static_CXX='-non_shared' + ;; + *) + ;; + esac + ;; + psos*) + ;; + solaris*) + case $cc_basename in + CC* | sunCC*) + # Sun C++ 4.2, 5.x and Centerline C++ + lt_prog_compiler_pic_CXX='-KPIC' + lt_prog_compiler_static_CXX='-Bstatic' + lt_prog_compiler_wl_CXX='-Qoption ld ' + ;; + gcx*) + # Green Hills C++ Compiler + lt_prog_compiler_pic_CXX='-PIC' + ;; + *) + ;; + esac + ;; + sunos4*) + case $cc_basename in + CC*) + # Sun C++ 4.x + lt_prog_compiler_pic_CXX='-pic' + lt_prog_compiler_static_CXX='-Bstatic' + ;; + lcc*) + # Lucid + lt_prog_compiler_pic_CXX='-pic' + ;; + *) + ;; + esac + ;; + sysv5* | unixware* | sco3.2v5* | sco5v6* | OpenUNIX*) + case $cc_basename in + CC*) + lt_prog_compiler_wl_CXX='-Wl,' + lt_prog_compiler_pic_CXX='-KPIC' + lt_prog_compiler_static_CXX='-Bstatic' + ;; + esac + ;; + tandem*) + case $cc_basename in + NCC*) + # NonStop-UX NCC 3.20 + lt_prog_compiler_pic_CXX='-KPIC' + ;; + *) + ;; + esac + ;; + vxworks*) + ;; + *) + lt_prog_compiler_can_build_shared_CXX=no + ;; + esac + fi + +case $host_os in + # For platforms which do not support PIC, -DPIC is meaningless: + *djgpp*) + lt_prog_compiler_pic_CXX= + ;; + *) + lt_prog_compiler_pic_CXX="$lt_prog_compiler_pic_CXX -DPIC" + ;; +esac + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $compiler option to produce PIC" >&5 +$as_echo_n "checking for $compiler option to produce PIC... " >&6; } +if ${lt_cv_prog_compiler_pic_CXX+:} false; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_prog_compiler_pic_CXX=$lt_prog_compiler_pic_CXX +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_pic_CXX" >&5 +$as_echo "$lt_cv_prog_compiler_pic_CXX" >&6; } +lt_prog_compiler_pic_CXX=$lt_cv_prog_compiler_pic_CXX + +# +# Check to make sure the PIC flag actually works. +# +if test -n "$lt_prog_compiler_pic_CXX"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler PIC flag $lt_prog_compiler_pic_CXX works" >&5 +$as_echo_n "checking if $compiler PIC flag $lt_prog_compiler_pic_CXX works... " >&6; } +if ${lt_cv_prog_compiler_pic_works_CXX+:} false; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_prog_compiler_pic_works_CXX=no + ac_outfile=conftest.$ac_objext + echo "$lt_simple_compile_test_code" > conftest.$ac_ext + lt_compiler_flag="$lt_prog_compiler_pic_CXX -DPIC" + # Insert the option either (1) after the last *FLAGS variable, or + # (2) before a word containing "conftest.", or (3) at the end. + # Note that $ac_compile itself does not contain backslashes and begins + # with a dollar sign (not a hyphen), so the echo should work correctly. + # The option is referenced via a variable to avoid confusing sed. + lt_compile=`echo "$ac_compile" | $SED \ + -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ + -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ + -e 's:$: $lt_compiler_flag:'` + (eval echo "\"\$as_me:$LINENO: $lt_compile\"" >&5) + (eval "$lt_compile" 2>conftest.err) + ac_status=$? + cat conftest.err >&5 + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + if (exit $ac_status) && test -s "$ac_outfile"; then + # The compiler can only warn and ignore the option if not recognized + # So say no if there are warnings other than the usual output. + $ECHO "$_lt_compiler_boilerplate" | $SED '/^$/d' >conftest.exp + $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2 + if test ! -s conftest.er2 || diff conftest.exp conftest.er2 >/dev/null; then + lt_cv_prog_compiler_pic_works_CXX=yes + fi + fi + $RM conftest* + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_pic_works_CXX" >&5 +$as_echo "$lt_cv_prog_compiler_pic_works_CXX" >&6; } + +if test x"$lt_cv_prog_compiler_pic_works_CXX" = xyes; then + case $lt_prog_compiler_pic_CXX in + "" | " "*) ;; + *) lt_prog_compiler_pic_CXX=" $lt_prog_compiler_pic_CXX" ;; + esac +else + lt_prog_compiler_pic_CXX= + lt_prog_compiler_can_build_shared_CXX=no +fi + +fi + + + + + +# +# Check to make sure the static flag actually works. +# +wl=$lt_prog_compiler_wl_CXX eval lt_tmp_static_flag=\"$lt_prog_compiler_static_CXX\" +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler static flag $lt_tmp_static_flag works" >&5 +$as_echo_n "checking if $compiler static flag $lt_tmp_static_flag works... " >&6; } +if ${lt_cv_prog_compiler_static_works_CXX+:} false; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_prog_compiler_static_works_CXX=no + save_LDFLAGS="$LDFLAGS" + LDFLAGS="$LDFLAGS $lt_tmp_static_flag" + echo "$lt_simple_link_test_code" > conftest.$ac_ext + if (eval $ac_link 2>conftest.err) && test -s conftest$ac_exeext; then + # The linker can only warn and ignore the option if not recognized + # So say no if there are warnings + if test -s conftest.err; then + # Append any errors to the config.log. + cat conftest.err 1>&5 + $ECHO "$_lt_linker_boilerplate" | $SED '/^$/d' > conftest.exp + $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2 + if diff conftest.exp conftest.er2 >/dev/null; then + lt_cv_prog_compiler_static_works_CXX=yes + fi + else + lt_cv_prog_compiler_static_works_CXX=yes + fi + fi + $RM -r conftest* + LDFLAGS="$save_LDFLAGS" + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_static_works_CXX" >&5 +$as_echo "$lt_cv_prog_compiler_static_works_CXX" >&6; } + +if test x"$lt_cv_prog_compiler_static_works_CXX" = xyes; then + : +else + lt_prog_compiler_static_CXX= +fi + + + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler supports -c -o file.$ac_objext" >&5 +$as_echo_n "checking if $compiler supports -c -o file.$ac_objext... " >&6; } +if ${lt_cv_prog_compiler_c_o_CXX+:} false; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_prog_compiler_c_o_CXX=no + $RM -r conftest 2>/dev/null + mkdir conftest + cd conftest + mkdir out + echo "$lt_simple_compile_test_code" > conftest.$ac_ext + + lt_compiler_flag="-o out/conftest2.$ac_objext" + # Insert the option either (1) after the last *FLAGS variable, or + # (2) before a word containing "conftest.", or (3) at the end. + # Note that $ac_compile itself does not contain backslashes and begins + # with a dollar sign (not a hyphen), so the echo should work correctly. + lt_compile=`echo "$ac_compile" | $SED \ + -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ + -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ + -e 's:$: $lt_compiler_flag:'` + (eval echo "\"\$as_me:$LINENO: $lt_compile\"" >&5) + (eval "$lt_compile" 2>out/conftest.err) + ac_status=$? + cat out/conftest.err >&5 + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + if (exit $ac_status) && test -s out/conftest2.$ac_objext + then + # The compiler can only warn and ignore the option if not recognized + # So say no if there are warnings + $ECHO "$_lt_compiler_boilerplate" | $SED '/^$/d' > out/conftest.exp + $SED '/^$/d; /^ *+/d' out/conftest.err >out/conftest.er2 + if test ! -s out/conftest.er2 || diff out/conftest.exp out/conftest.er2 >/dev/null; then + lt_cv_prog_compiler_c_o_CXX=yes + fi + fi + chmod u+w . 2>&5 + $RM conftest* + # SGI C++ compiler will create directory out/ii_files/ for + # template instantiation + test -d out/ii_files && $RM out/ii_files/* && rmdir out/ii_files + $RM out/* && rmdir out + cd .. + $RM -r conftest + $RM conftest* + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_c_o_CXX" >&5 +$as_echo "$lt_cv_prog_compiler_c_o_CXX" >&6; } + + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler supports -c -o file.$ac_objext" >&5 +$as_echo_n "checking if $compiler supports -c -o file.$ac_objext... " >&6; } +if ${lt_cv_prog_compiler_c_o_CXX+:} false; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_prog_compiler_c_o_CXX=no + $RM -r conftest 2>/dev/null + mkdir conftest + cd conftest + mkdir out + echo "$lt_simple_compile_test_code" > conftest.$ac_ext + + lt_compiler_flag="-o out/conftest2.$ac_objext" + # Insert the option either (1) after the last *FLAGS variable, or + # (2) before a word containing "conftest.", or (3) at the end. + # Note that $ac_compile itself does not contain backslashes and begins + # with a dollar sign (not a hyphen), so the echo should work correctly. + lt_compile=`echo "$ac_compile" | $SED \ + -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ + -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ + -e 's:$: $lt_compiler_flag:'` + (eval echo "\"\$as_me:$LINENO: $lt_compile\"" >&5) + (eval "$lt_compile" 2>out/conftest.err) + ac_status=$? + cat out/conftest.err >&5 + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + if (exit $ac_status) && test -s out/conftest2.$ac_objext + then + # The compiler can only warn and ignore the option if not recognized + # So say no if there are warnings + $ECHO "$_lt_compiler_boilerplate" | $SED '/^$/d' > out/conftest.exp + $SED '/^$/d; /^ *+/d' out/conftest.err >out/conftest.er2 + if test ! -s out/conftest.er2 || diff out/conftest.exp out/conftest.er2 >/dev/null; then + lt_cv_prog_compiler_c_o_CXX=yes + fi + fi + chmod u+w . 2>&5 + $RM conftest* + # SGI C++ compiler will create directory out/ii_files/ for + # template instantiation + test -d out/ii_files && $RM out/ii_files/* && rmdir out/ii_files + $RM out/* && rmdir out + cd .. + $RM -r conftest + $RM conftest* + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_c_o_CXX" >&5 +$as_echo "$lt_cv_prog_compiler_c_o_CXX" >&6; } + + + + +hard_links="nottested" +if test "$lt_cv_prog_compiler_c_o_CXX" = no && test "$need_locks" != no; then + # do not overwrite the value of need_locks provided by the user + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if we can lock with hard links" >&5 +$as_echo_n "checking if we can lock with hard links... " >&6; } + hard_links=yes + $RM conftest* + ln conftest.a conftest.b 2>/dev/null && hard_links=no + touch conftest.a + ln conftest.a conftest.b 2>&5 || hard_links=no + ln conftest.a conftest.b 2>/dev/null && hard_links=no + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $hard_links" >&5 +$as_echo "$hard_links" >&6; } + if test "$hard_links" = no; then + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: \`$CC' does not support \`-c -o', so \`make -j' may be unsafe" >&5 +$as_echo "$as_me: WARNING: \`$CC' does not support \`-c -o', so \`make -j' may be unsafe" >&2;} + need_locks=warn + fi +else + need_locks=no +fi + + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the $compiler linker ($LD) supports shared libraries" >&5 +$as_echo_n "checking whether the $compiler linker ($LD) supports shared libraries... " >&6; } + + export_symbols_cmds_CXX='$NM $libobjs $convenience | $global_symbol_pipe | $SED '\''s/.* //'\'' | sort | uniq > $export_symbols' + exclude_expsyms_CXX='_GLOBAL_OFFSET_TABLE_|_GLOBAL__F[ID]_.*' + case $host_os in + aix[4-9]*) + # If we're using GNU nm, then we don't want the "-C" option. + # -C means demangle to AIX nm, but means don't demangle with GNU nm + # Also, AIX nm treats weak defined symbols like other global defined + # symbols, whereas GNU nm marks them as "W". + if $NM -V 2>&1 | $GREP 'GNU' > /dev/null; then + export_symbols_cmds_CXX='$NM -Bpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B") || (\$ 2 == "W")) && (substr(\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols' + else + export_symbols_cmds_CXX='$NM -BCpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B")) && (substr(\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols' + fi + ;; + pw32*) + export_symbols_cmds_CXX="$ltdll_cmds" + ;; + cygwin* | mingw* | cegcc*) + case $cc_basename in + cl*) + exclude_expsyms_CXX='_NULL_IMPORT_DESCRIPTOR|_IMPORT_DESCRIPTOR_.*' + ;; + *) + export_symbols_cmds_CXX='$NM $libobjs $convenience | $global_symbol_pipe | $SED -e '\''/^[BCDGRS][ ]/s/.*[ ]\([^ ]*\)/\1 DATA/;s/^.*[ ]__nm__\([^ ]*\)[ ][^ ]*/\1 DATA/;/^I[ ]/d;/^[AITW][ ]/s/.* //'\'' | sort | uniq > $export_symbols' + exclude_expsyms_CXX='[_]+GLOBAL_OFFSET_TABLE_|[_]+GLOBAL__[FID]_.*|[_]+head_[A-Za-z0-9_]+_dll|[A-Za-z0-9_]+_dll_iname' + ;; + esac + ;; + *) + export_symbols_cmds_CXX='$NM $libobjs $convenience | $global_symbol_pipe | $SED '\''s/.* //'\'' | sort | uniq > $export_symbols' + ;; + esac + +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ld_shlibs_CXX" >&5 +$as_echo "$ld_shlibs_CXX" >&6; } +test "$ld_shlibs_CXX" = no && can_build_shared=no + +with_gnu_ld_CXX=$with_gnu_ld + + + + + + +# +# Do we need to explicitly link libc? +# +case "x$archive_cmds_need_lc_CXX" in +x|xyes) + # Assume -lc should be added + archive_cmds_need_lc_CXX=yes + + if test "$enable_shared" = yes && test "$GCC" = yes; then + case $archive_cmds_CXX in + *'~'*) + # FIXME: we may have to deal with multi-command sequences. + ;; + '$CC '*) + # Test whether the compiler implicitly links with -lc since on some + # systems, -lgcc has to come before -lc. If gcc already passes -lc + # to ld, don't add -lc before -lgcc. + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether -lc should be explicitly linked in" >&5 +$as_echo_n "checking whether -lc should be explicitly linked in... " >&6; } +if ${lt_cv_archive_cmds_need_lc_CXX+:} false; then : + $as_echo_n "(cached) " >&6 +else + $RM conftest* + echo "$lt_simple_compile_test_code" > conftest.$ac_ext + + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 + (eval $ac_compile) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } 2>conftest.err; then + soname=conftest + lib=conftest + libobjs=conftest.$ac_objext + deplibs= + wl=$lt_prog_compiler_wl_CXX + pic_flag=$lt_prog_compiler_pic_CXX + compiler_flags=-v + linker_flags=-v + verstring= + output_objdir=. + libname=conftest + lt_save_allow_undefined_flag=$allow_undefined_flag_CXX + allow_undefined_flag_CXX= + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$archive_cmds_CXX 2\>\&1 \| $GREP \" -lc \" \>/dev/null 2\>\&1\""; } >&5 + (eval $archive_cmds_CXX 2\>\&1 \| $GREP \" -lc \" \>/dev/null 2\>\&1) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + then + lt_cv_archive_cmds_need_lc_CXX=no + else + lt_cv_archive_cmds_need_lc_CXX=yes + fi + allow_undefined_flag_CXX=$lt_save_allow_undefined_flag + else + cat conftest.err 1>&5 + fi + $RM conftest* + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_archive_cmds_need_lc_CXX" >&5 +$as_echo "$lt_cv_archive_cmds_need_lc_CXX" >&6; } + archive_cmds_need_lc_CXX=$lt_cv_archive_cmds_need_lc_CXX + ;; + esac + fi + ;; +esac + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking dynamic linker characteristics" >&5 +$as_echo_n "checking dynamic linker characteristics... " >&6; } + +library_names_spec= +libname_spec='lib$name' +soname_spec= +shrext_cmds=".so" +postinstall_cmds= +postuninstall_cmds= +finish_cmds= +finish_eval= +shlibpath_var= +shlibpath_overrides_runpath=unknown +version_type=none +dynamic_linker="$host_os ld.so" +sys_lib_dlsearch_path_spec="/lib /usr/lib" +need_lib_prefix=unknown +hardcode_into_libs=no + +# when you set need_version to no, make sure it does not cause -set_version +# flags to be left without arguments +need_version=unknown + +case $host_os in +aix3*) + version_type=linux # correct to gnu/linux during the next big refactor + library_names_spec='${libname}${release}${shared_ext}$versuffix $libname.a' + shlibpath_var=LIBPATH + + # AIX 3 has no versioning support, so we append a major version to the name. + soname_spec='${libname}${release}${shared_ext}$major' + ;; + +aix[4-9]*) + version_type=linux # correct to gnu/linux during the next big refactor + need_lib_prefix=no + need_version=no + hardcode_into_libs=yes + if test "$host_cpu" = ia64; then + # AIX 5 supports IA64 + library_names_spec='${libname}${release}${shared_ext}$major ${libname}${release}${shared_ext}$versuffix $libname${shared_ext}' + shlibpath_var=LD_LIBRARY_PATH + else + # With GCC up to 2.95.x, collect2 would create an import file + # for dependence libraries. The import file would start with + # the line `#! .'. This would cause the generated library to + # depend on `.', always an invalid library. This was fixed in + # development snapshots of GCC prior to 3.0. + case $host_os in + aix4 | aix4.[01] | aix4.[01].*) + if { echo '#if __GNUC__ > 2 || (__GNUC__ == 2 && __GNUC_MINOR__ >= 97)' + echo ' yes ' + echo '#endif'; } | ${CC} -E - | $GREP yes > /dev/null; then + : + else + can_build_shared=no + fi + ;; + esac + # AIX (on Power*) has no versioning support, so currently we can not hardcode correct + # soname into executable. Probably we can add versioning support to + # collect2, so additional links can be useful in future. + if test "$aix_use_runtimelinking" = yes; then + # If using run time linking (on AIX 4.2 or later) use lib.so + # instead of lib.a to let people know that these are not + # typical AIX shared libraries. + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + else + # We preserve .a as extension for shared libraries through AIX4.2 + # and later when we are not doing run time linking. + library_names_spec='${libname}${release}.a $libname.a' + soname_spec='${libname}${release}${shared_ext}$major' + fi + shlibpath_var=LIBPATH + fi + ;; + +amigaos*) + case $host_cpu in + powerpc) + # Since July 2007 AmigaOS4 officially supports .so libraries. + # When compiling the executable, add -use-dynld -Lsobjs: to the compileline. + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + ;; + m68k) + library_names_spec='$libname.ixlibrary $libname.a' + # Create ${libname}_ixlibrary.a entries in /sys/libs. + finish_eval='for lib in `ls $libdir/*.ixlibrary 2>/dev/null`; do libname=`func_echo_all "$lib" | $SED '\''s%^.*/\([^/]*\)\.ixlibrary$%\1%'\''`; test $RM /sys/libs/${libname}_ixlibrary.a; $show "cd /sys/libs && $LN_S $lib ${libname}_ixlibrary.a"; cd /sys/libs && $LN_S $lib ${libname}_ixlibrary.a || exit 1; done' + ;; + esac + ;; + +beos*) + library_names_spec='${libname}${shared_ext}' + dynamic_linker="$host_os ld.so" + shlibpath_var=LIBRARY_PATH + ;; + +bsdi[45]*) + version_type=linux # correct to gnu/linux during the next big refactor + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + finish_cmds='PATH="\$PATH:/sbin" ldconfig $libdir' + shlibpath_var=LD_LIBRARY_PATH + sys_lib_search_path_spec="/shlib /usr/lib /usr/X11/lib /usr/contrib/lib /lib /usr/local/lib" + sys_lib_dlsearch_path_spec="/shlib /usr/lib /usr/local/lib" + # the default ld.so.conf also contains /usr/contrib/lib and + # /usr/X11R6/lib (/usr/X11 is a link to /usr/X11R6), but let us allow + # libtool to hard-code these into programs + ;; + +cygwin* | mingw* | pw32* | cegcc*) + version_type=windows + shrext_cmds=".dll" + need_version=no + need_lib_prefix=no + + case $GCC,$cc_basename in + yes,*) + # gcc + library_names_spec='$libname.dll.a' + # DLL is installed to $(libdir)/../bin by postinstall_cmds + postinstall_cmds='base_file=`basename \${file}`~ + dlpath=`$SHELL 2>&1 -c '\''. $dir/'\''\${base_file}'\''i; echo \$dlname'\''`~ + dldir=$destdir/`dirname \$dlpath`~ + test -d \$dldir || mkdir -p \$dldir~ + $install_prog $dir/$dlname \$dldir/$dlname~ + chmod a+x \$dldir/$dlname~ + if test -n '\''$stripme'\'' && test -n '\''$striplib'\''; then + eval '\''$striplib \$dldir/$dlname'\'' || exit \$?; + fi' + postuninstall_cmds='dldll=`$SHELL 2>&1 -c '\''. $file; echo \$dlname'\''`~ + dlpath=$dir/\$dldll~ + $RM \$dlpath' + shlibpath_overrides_runpath=yes + + case $host_os in + cygwin*) + # Cygwin DLLs use 'cyg' prefix rather than 'lib' + soname_spec='`echo ${libname} | sed -e 's/^lib/cyg/'``echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}' + + ;; + mingw* | cegcc*) + # MinGW DLLs use traditional 'lib' prefix + soname_spec='${libname}`echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}' + ;; + pw32*) + # pw32 DLLs use 'pw' prefix rather than 'lib' + library_names_spec='`echo ${libname} | sed -e 's/^lib/pw/'``echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}' + ;; + esac + dynamic_linker='Win32 ld.exe' + ;; + + *,cl*) + # Native MSVC + libname_spec='$name' + soname_spec='${libname}`echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}' + library_names_spec='${libname}.dll.lib' + + case $build_os in + mingw*) + sys_lib_search_path_spec= + lt_save_ifs=$IFS + IFS=';' + for lt_path in $LIB + do + IFS=$lt_save_ifs + # Let DOS variable expansion print the short 8.3 style file name. + lt_path=`cd "$lt_path" 2>/dev/null && cmd //C "for %i in (".") do @echo %~si"` + sys_lib_search_path_spec="$sys_lib_search_path_spec $lt_path" + done + IFS=$lt_save_ifs + # Convert to MSYS style. + sys_lib_search_path_spec=`$ECHO "$sys_lib_search_path_spec" | sed -e 's|\\\\|/|g' -e 's| \\([a-zA-Z]\\):| /\\1|g' -e 's|^ ||'` + ;; + cygwin*) + # Convert to unix form, then to dos form, then back to unix form + # but this time dos style (no spaces!) so that the unix form looks + # like /cygdrive/c/PROGRA~1:/cygdr... + sys_lib_search_path_spec=`cygpath --path --unix "$LIB"` + sys_lib_search_path_spec=`cygpath --path --dos "$sys_lib_search_path_spec" 2>/dev/null` + sys_lib_search_path_spec=`cygpath --path --unix "$sys_lib_search_path_spec" | $SED -e "s/$PATH_SEPARATOR/ /g"` + ;; + *) + sys_lib_search_path_spec="$LIB" + if $ECHO "$sys_lib_search_path_spec" | $GREP ';[c-zC-Z]:/' >/dev/null; then + # It is most probably a Windows format PATH. + sys_lib_search_path_spec=`$ECHO "$sys_lib_search_path_spec" | $SED -e 's/;/ /g'` + else + sys_lib_search_path_spec=`$ECHO "$sys_lib_search_path_spec" | $SED -e "s/$PATH_SEPARATOR/ /g"` + fi + # FIXME: find the short name or the path components, as spaces are + # common. (e.g. "Program Files" -> "PROGRA~1") + ;; + esac + + # DLL is installed to $(libdir)/../bin by postinstall_cmds + postinstall_cmds='base_file=`basename \${file}`~ + dlpath=`$SHELL 2>&1 -c '\''. $dir/'\''\${base_file}'\''i; echo \$dlname'\''`~ + dldir=$destdir/`dirname \$dlpath`~ + test -d \$dldir || mkdir -p \$dldir~ + $install_prog $dir/$dlname \$dldir/$dlname' + postuninstall_cmds='dldll=`$SHELL 2>&1 -c '\''. $file; echo \$dlname'\''`~ + dlpath=$dir/\$dldll~ + $RM \$dlpath' + shlibpath_overrides_runpath=yes + dynamic_linker='Win32 link.exe' + ;; + + *) + # Assume MSVC wrapper + library_names_spec='${libname}`echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext} $libname.lib' + dynamic_linker='Win32 ld.exe' + ;; + esac + # FIXME: first we should search . and the directory the executable is in + shlibpath_var=PATH + ;; + +darwin* | rhapsody*) + dynamic_linker="$host_os dyld" + version_type=darwin + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${major}$shared_ext ${libname}$shared_ext' + soname_spec='${libname}${release}${major}$shared_ext' + shlibpath_overrides_runpath=yes + shlibpath_var=DYLD_LIBRARY_PATH + shrext_cmds='`test .$module = .yes && echo .so || echo .dylib`' + + sys_lib_dlsearch_path_spec='/usr/local/lib /lib /usr/lib' + ;; + +dgux*) + version_type=linux # correct to gnu/linux during the next big refactor + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname$shared_ext' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + ;; + +freebsd* | dragonfly*) + # DragonFly does not have aout. When/if they implement a new + # versioning mechanism, adjust this. + if test -x /usr/bin/objformat; then + objformat=`/usr/bin/objformat` + else + case $host_os in + freebsd[23].*) objformat=aout ;; + *) objformat=elf ;; + esac + fi + version_type=freebsd-$objformat + case $version_type in + freebsd-elf*) + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext} $libname${shared_ext}' + need_version=no + need_lib_prefix=no + ;; + freebsd-*) + library_names_spec='${libname}${release}${shared_ext}$versuffix $libname${shared_ext}$versuffix' + need_version=yes + ;; + esac + shlibpath_var=LD_LIBRARY_PATH + case $host_os in + freebsd2.*) + shlibpath_overrides_runpath=yes + ;; + freebsd3.[01]* | freebsdelf3.[01]*) + shlibpath_overrides_runpath=yes + hardcode_into_libs=yes + ;; + freebsd3.[2-9]* | freebsdelf3.[2-9]* | \ + freebsd4.[0-5] | freebsdelf4.[0-5] | freebsd4.1.1 | freebsdelf4.1.1) + shlibpath_overrides_runpath=no + hardcode_into_libs=yes + ;; + *) # from 4.6 on, and DragonFly + shlibpath_overrides_runpath=yes + hardcode_into_libs=yes + ;; + esac + ;; + +gnu*) + version_type=linux # correct to gnu/linux during the next big refactor + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}${major} ${libname}${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=no + hardcode_into_libs=yes + ;; + +haiku*) + version_type=linux # correct to gnu/linux during the next big refactor + need_lib_prefix=no + need_version=no + dynamic_linker="$host_os runtime_loader" + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}${major} ${libname}${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LIBRARY_PATH + shlibpath_overrides_runpath=yes + sys_lib_dlsearch_path_spec='/boot/home/config/lib /boot/common/lib /boot/system/lib' + hardcode_into_libs=yes + ;; + +hpux9* | hpux10* | hpux11*) + # Give a soname corresponding to the major version so that dld.sl refuses to + # link against other versions. + version_type=sunos + need_lib_prefix=no + need_version=no + case $host_cpu in + ia64*) + shrext_cmds='.so' + hardcode_into_libs=yes + dynamic_linker="$host_os dld.so" + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes # Unless +noenvvar is specified. + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + if test "X$HPUX_IA64_MODE" = X32; then + sys_lib_search_path_spec="/usr/lib/hpux32 /usr/local/lib/hpux32 /usr/local/lib" + else + sys_lib_search_path_spec="/usr/lib/hpux64 /usr/local/lib/hpux64" + fi + sys_lib_dlsearch_path_spec=$sys_lib_search_path_spec + ;; + hppa*64*) + shrext_cmds='.sl' + hardcode_into_libs=yes + dynamic_linker="$host_os dld.sl" + shlibpath_var=LD_LIBRARY_PATH # How should we handle SHLIB_PATH + shlibpath_overrides_runpath=yes # Unless +noenvvar is specified. + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + sys_lib_search_path_spec="/usr/lib/pa20_64 /usr/ccs/lib/pa20_64" + sys_lib_dlsearch_path_spec=$sys_lib_search_path_spec + ;; + *) + shrext_cmds='.sl' + dynamic_linker="$host_os dld.sl" + shlibpath_var=SHLIB_PATH + shlibpath_overrides_runpath=no # +s is required to enable SHLIB_PATH + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + ;; + esac + # HP-UX runs *really* slowly unless shared libraries are mode 555, ... + postinstall_cmds='chmod 555 $lib' + # or fails outright, so override atomically: + install_override_mode=555 + ;; + +interix[3-9]*) + version_type=linux # correct to gnu/linux during the next big refactor + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + dynamic_linker='Interix 3.x ld.so.1 (PE, like ELF)' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=no + hardcode_into_libs=yes + ;; + +irix5* | irix6* | nonstopux*) + case $host_os in + nonstopux*) version_type=nonstopux ;; + *) + if test "$lt_cv_prog_gnu_ld" = yes; then + version_type=linux # correct to gnu/linux during the next big refactor + else + version_type=irix + fi ;; + esac + need_lib_prefix=no + need_version=no + soname_spec='${libname}${release}${shared_ext}$major' + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${release}${shared_ext} $libname${shared_ext}' + case $host_os in + irix5* | nonstopux*) + libsuff= shlibsuff= + ;; + *) + case $LD in # libtool.m4 will add one of these switches to LD + *-32|*"-32 "|*-melf32bsmip|*"-melf32bsmip ") + libsuff= shlibsuff= libmagic=32-bit;; + *-n32|*"-n32 "|*-melf32bmipn32|*"-melf32bmipn32 ") + libsuff=32 shlibsuff=N32 libmagic=N32;; + *-64|*"-64 "|*-melf64bmip|*"-melf64bmip ") + libsuff=64 shlibsuff=64 libmagic=64-bit;; + *) libsuff= shlibsuff= libmagic=never-match;; + esac + ;; + esac + shlibpath_var=LD_LIBRARY${shlibsuff}_PATH + shlibpath_overrides_runpath=no + sys_lib_search_path_spec="/usr/lib${libsuff} /lib${libsuff} /usr/local/lib${libsuff}" + sys_lib_dlsearch_path_spec="/usr/lib${libsuff} /lib${libsuff}" + hardcode_into_libs=yes + ;; + +# No shared lib support for Linux oldld, aout, or coff. +linux*oldld* | linux*aout* | linux*coff*) + dynamic_linker=no + ;; + +# This must be glibc/ELF. +linux* | k*bsd*-gnu | kopensolaris*-gnu) + version_type=linux # correct to gnu/linux during the next big refactor + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + finish_cmds='PATH="\$PATH:/sbin" ldconfig -n $libdir' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=no + + # Some binutils ld are patched to set DT_RUNPATH + if ${lt_cv_shlibpath_overrides_runpath+:} false; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_shlibpath_overrides_runpath=no + save_LDFLAGS=$LDFLAGS + save_libdir=$libdir + eval "libdir=/foo; wl=\"$lt_prog_compiler_wl_CXX\"; \ + LDFLAGS=\"\$LDFLAGS $hardcode_libdir_flag_spec_CXX\"" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_link "$LINENO"; then : + if ($OBJDUMP -p conftest$ac_exeext) 2>/dev/null | grep "RUNPATH.*$libdir" >/dev/null; then : + lt_cv_shlibpath_overrides_runpath=yes +fi +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + LDFLAGS=$save_LDFLAGS + libdir=$save_libdir + +fi + + shlibpath_overrides_runpath=$lt_cv_shlibpath_overrides_runpath + + # This implies no fast_install, which is unacceptable. + # Some rework will be needed to allow for fast_install + # before this can be enabled. + hardcode_into_libs=yes + + # Append ld.so.conf contents to the search path + if test -f /etc/ld.so.conf; then + lt_ld_extra=`awk '/^include / { system(sprintf("cd /etc; cat %s 2>/dev/null", \$2)); skip = 1; } { if (!skip) print \$0; skip = 0; }' < /etc/ld.so.conf | $SED -e 's/#.*//;/^[ ]*hwcap[ ]/d;s/[:, ]/ /g;s/=[^=]*$//;s/=[^= ]* / /g;s/"//g;/^$/d' | tr '\n' ' '` + sys_lib_dlsearch_path_spec="/lib /usr/lib $lt_ld_extra" + fi + + # We used to test for /lib/ld.so.1 and disable shared libraries on + # powerpc, because MkLinux only supported shared libraries with the + # GNU dynamic linker. Since this was broken with cross compilers, + # most powerpc-linux boxes support dynamic linking these days and + # people can always --disable-shared, the test was removed, and we + # assume the GNU/Linux dynamic linker is in use. + dynamic_linker='GNU/Linux ld.so' + ;; + +netbsd*) + version_type=sunos + need_lib_prefix=no + need_version=no + if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix' + finish_cmds='PATH="\$PATH:/sbin" ldconfig -m $libdir' + dynamic_linker='NetBSD (a.out) ld.so' + else + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + dynamic_linker='NetBSD ld.elf_so' + fi + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes + hardcode_into_libs=yes + ;; + +newsos6) + version_type=linux # correct to gnu/linux during the next big refactor + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes + ;; + +*nto* | *qnx*) + version_type=qnx + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=no + hardcode_into_libs=yes + dynamic_linker='ldqnx.so' + ;; + +openbsd*) + version_type=sunos + sys_lib_dlsearch_path_spec="/usr/lib" + need_lib_prefix=no + # Some older versions of OpenBSD (3.3 at least) *do* need versioned libs. + case $host_os in + openbsd3.3 | openbsd3.3.*) need_version=yes ;; + *) need_version=no ;; + esac + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix' + finish_cmds='PATH="\$PATH:/sbin" ldconfig -m $libdir' + shlibpath_var=LD_LIBRARY_PATH + if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then + case $host_os in + openbsd2.[89] | openbsd2.[89].*) + shlibpath_overrides_runpath=no + ;; + *) + shlibpath_overrides_runpath=yes + ;; + esac + else + shlibpath_overrides_runpath=yes + fi + ;; + +os2*) + libname_spec='$name' + shrext_cmds=".dll" + need_lib_prefix=no + library_names_spec='$libname${shared_ext} $libname.a' + dynamic_linker='OS/2 ld.exe' + shlibpath_var=LIBPATH + ;; + +osf3* | osf4* | osf5*) + version_type=osf + need_lib_prefix=no + need_version=no + soname_spec='${libname}${release}${shared_ext}$major' + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + shlibpath_var=LD_LIBRARY_PATH + sys_lib_search_path_spec="/usr/shlib /usr/ccs/lib /usr/lib/cmplrs/cc /usr/lib /usr/local/lib /var/shlib" + sys_lib_dlsearch_path_spec="$sys_lib_search_path_spec" + ;; + +rdos*) + dynamic_linker=no + ;; + +solaris*) + version_type=linux # correct to gnu/linux during the next big refactor + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes + hardcode_into_libs=yes + # ldd complains unless libraries are executable + postinstall_cmds='chmod +x $lib' + ;; + +sunos4*) + version_type=sunos + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix' + finish_cmds='PATH="\$PATH:/usr/etc" ldconfig $libdir' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes + if test "$with_gnu_ld" = yes; then + need_lib_prefix=no + fi + need_version=yes + ;; + +sysv4 | sysv4.3*) + version_type=linux # correct to gnu/linux during the next big refactor + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + case $host_vendor in + sni) + shlibpath_overrides_runpath=no + need_lib_prefix=no + runpath_var=LD_RUN_PATH + ;; + siemens) + need_lib_prefix=no + ;; + motorola) + need_lib_prefix=no + need_version=no + shlibpath_overrides_runpath=no + sys_lib_search_path_spec='/lib /usr/lib /usr/ccs/lib' + ;; + esac + ;; + +sysv4*MP*) + if test -d /usr/nec ;then + version_type=linux # correct to gnu/linux during the next big refactor + library_names_spec='$libname${shared_ext}.$versuffix $libname${shared_ext}.$major $libname${shared_ext}' + soname_spec='$libname${shared_ext}.$major' + shlibpath_var=LD_LIBRARY_PATH + fi + ;; + +sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX* | sysv4*uw2*) + version_type=freebsd-elf + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext} $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes + hardcode_into_libs=yes + if test "$with_gnu_ld" = yes; then + sys_lib_search_path_spec='/usr/local/lib /usr/gnu/lib /usr/ccs/lib /usr/lib /lib' + else + sys_lib_search_path_spec='/usr/ccs/lib /usr/lib' + case $host_os in + sco3.2v5*) + sys_lib_search_path_spec="$sys_lib_search_path_spec /lib" + ;; + esac + fi + sys_lib_dlsearch_path_spec='/usr/lib' + ;; + +tpf*) + # TPF is a cross-target only. Preferred cross-host = GNU/Linux. + version_type=linux # correct to gnu/linux during the next big refactor + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=no + hardcode_into_libs=yes + ;; + +uts4*) + version_type=linux # correct to gnu/linux during the next big refactor + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + ;; + +*) + dynamic_linker=no + ;; +esac +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $dynamic_linker" >&5 +$as_echo "$dynamic_linker" >&6; } +test "$dynamic_linker" = no && can_build_shared=no + +variables_saved_for_relink="PATH $shlibpath_var $runpath_var" +if test "$GCC" = yes; then + variables_saved_for_relink="$variables_saved_for_relink GCC_EXEC_PREFIX COMPILER_PATH LIBRARY_PATH" +fi + +if test "${lt_cv_sys_lib_search_path_spec+set}" = set; then + sys_lib_search_path_spec="$lt_cv_sys_lib_search_path_spec" +fi +if test "${lt_cv_sys_lib_dlsearch_path_spec+set}" = set; then + sys_lib_dlsearch_path_spec="$lt_cv_sys_lib_dlsearch_path_spec" +fi + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking how to hardcode library paths into programs" >&5 +$as_echo_n "checking how to hardcode library paths into programs... " >&6; } +hardcode_action_CXX= +if test -n "$hardcode_libdir_flag_spec_CXX" || + test -n "$runpath_var_CXX" || + test "X$hardcode_automatic_CXX" = "Xyes" ; then + + # We can hardcode non-existent directories. + if test "$hardcode_direct_CXX" != no && + # If the only mechanism to avoid hardcoding is shlibpath_var, we + # have to relink, otherwise we might link with an installed library + # when we should be linking with a yet-to-be-installed one + ## test "$_LT_TAGVAR(hardcode_shlibpath_var, CXX)" != no && + test "$hardcode_minus_L_CXX" != no; then + # Linking always hardcodes the temporary library directory. + hardcode_action_CXX=relink + else + # We can link without hardcoding, and we can hardcode nonexisting dirs. + hardcode_action_CXX=immediate + fi +else + # We cannot hardcode anything, or else we can only hardcode existing + # directories. + hardcode_action_CXX=unsupported +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $hardcode_action_CXX" >&5 +$as_echo "$hardcode_action_CXX" >&6; } + +if test "$hardcode_action_CXX" = relink || + test "$inherit_rpath_CXX" = yes; then + # Fast installation is not supported + enable_fast_install=no +elif test "$shlibpath_overrides_runpath" = yes || + test "$enable_shared" = no; then + # Fast installation is not necessary + enable_fast_install=needless +fi + + + + + + + + fi # test -n "$compiler" + + CC=$lt_save_CC + CFLAGS=$lt_save_CFLAGS + LDCXX=$LD + LD=$lt_save_LD + GCC=$lt_save_GCC + with_gnu_ld=$lt_save_with_gnu_ld + lt_cv_path_LDCXX=$lt_cv_path_LD + lt_cv_path_LD=$lt_save_path_LD + lt_cv_prog_gnu_ldcxx=$lt_cv_prog_gnu_ld + lt_cv_prog_gnu_ld=$lt_save_with_gnu_ld +fi # test "$_lt_caught_CXX_error" != yes + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + + + + + + CFLAG_VISIBILITY= + HAVE_VISIBILITY=0 + if test -n "$GCC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the -Werror option is usable" >&5 +$as_echo_n "checking whether the -Werror option is usable... " >&6; } + if ${gl_cv_cc_vis_werror+:} false; then : + $as_echo_n "(cached) " >&6 +else + + gl_save_CFLAGS="$CFLAGS" + CFLAGS="$CFLAGS -Werror" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + gl_cv_cc_vis_werror=yes +else + gl_cv_cc_vis_werror=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS="$gl_save_CFLAGS" +fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $gl_cv_cc_vis_werror" >&5 +$as_echo "$gl_cv_cc_vis_werror" >&6; } + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for simple visibility declarations" >&5 +$as_echo_n "checking for simple visibility declarations... " >&6; } + if ${gl_cv_cc_visibility+:} false; then : + $as_echo_n "(cached) " >&6 +else + + gl_save_CFLAGS="$CFLAGS" + CFLAGS="$CFLAGS -fvisibility=hidden" + if test $gl_cv_cc_vis_werror = yes; then + CFLAGS="$CFLAGS -Werror" + fi + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +extern __attribute__((__visibility__("hidden"))) int hiddenvar; + extern __attribute__((__visibility__("default"))) int exportedvar; + extern __attribute__((__visibility__("hidden"))) int hiddenfunc (void); + extern __attribute__((__visibility__("default"))) int exportedfunc (void); + void dummyfunc (void) {} + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + gl_cv_cc_visibility=yes +else + gl_cv_cc_visibility=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS="$gl_save_CFLAGS" +fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $gl_cv_cc_visibility" >&5 +$as_echo "$gl_cv_cc_visibility" >&6; } + if test $gl_cv_cc_visibility = yes; then + CFLAG_VISIBILITY="-fvisibility=hidden" + HAVE_VISIBILITY=1 + fi + fi + + + +cat >>confdefs.h <<_ACEOF +#define HAVE_VISIBILITY $HAVE_VISIBILITY +_ACEOF + + +if test -n "$CFLAG_VISIBILITY" ; then : + + AM_CPPFLAGS="$AM_CPPFLAGS $CFLAG_VISIBILITY" + CPPFLAGS="$CPPFLAGS $CFLAG_VISIBILITY" + +fi + +# Check whether --enable-silent-rules was given. +if test "${enable_silent_rules+set}" = set; then : + enableval=$enable_silent_rules; +fi + +case $enable_silent_rules in # ((( + yes) AM_DEFAULT_VERBOSITY=0;; + no) AM_DEFAULT_VERBOSITY=1;; + *) AM_DEFAULT_VERBOSITY=0;; +esac +am_make=${MAKE-make} +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $am_make supports nested variables" >&5 +$as_echo_n "checking whether $am_make supports nested variables... " >&6; } +if ${am_cv_make_support_nested_variables+:} false; then : + $as_echo_n "(cached) " >&6 +else + if $as_echo 'TRUE=$(BAR$(V)) +BAR0=false +BAR1=true +V=1 +am__doit: + @$(TRUE) +.PHONY: am__doit' | $am_make -f - >/dev/null 2>&1; then + am_cv_make_support_nested_variables=yes +else + am_cv_make_support_nested_variables=no +fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_make_support_nested_variables" >&5 +$as_echo "$am_cv_make_support_nested_variables" >&6; } +if test $am_cv_make_support_nested_variables = yes; then + AM_V='$(V)' + AM_DEFAULT_V='$(AM_DEFAULT_VERBOSITY)' +else + AM_V=$AM_DEFAULT_VERBOSITY + AM_DEFAULT_V=$AM_DEFAULT_VERBOSITY +fi +AM_BACKSLASH='\' + + +for ac_func in gethostbyname +do : + ac_fn_c_check_func "$LINENO" "gethostbyname" "ac_cv_func_gethostbyname" +if test "x$ac_cv_func_gethostbyname" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_GETHOSTBYNAME 1 +_ACEOF + +fi +done + +for ac_func in getaddrinfo +do : + ac_fn_c_check_func "$LINENO" "getaddrinfo" "ac_cv_func_getaddrinfo" +if test "x$ac_cv_func_getaddrinfo" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_GETADDRINFO 1 +_ACEOF + +fi +done + +for ac_func in gettimeofday +do : + ac_fn_c_check_func "$LINENO" "gettimeofday" "ac_cv_func_gettimeofday" +if test "x$ac_cv_func_gettimeofday" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_GETTIMEOFDAY 1 +_ACEOF + +fi +done + +for ac_func in inet_ntoa +do : + ac_fn_c_check_func "$LINENO" "inet_ntoa" "ac_cv_func_inet_ntoa" +if test "x$ac_cv_func_inet_ntoa" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_INET_NTOA 1 +_ACEOF + +fi +done + +for ac_func in memset +do : + ac_fn_c_check_func "$LINENO" "memset" "ac_cv_func_memset" +if test "x$ac_cv_func_memset" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_MEMSET 1 +_ACEOF + +fi +done + +for ac_func in socket +do : + ac_fn_c_check_func "$LINENO" "socket" "ac_cv_func_socket" +if test "x$ac_cv_func_socket" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_SOCKET 1 +_ACEOF + +fi +done + +for ac_header in arpa/inet.h +do : + ac_fn_c_check_header_mongrel "$LINENO" "arpa/inet.h" "ac_cv_header_arpa_inet_h" "$ac_includes_default" +if test "x$ac_cv_header_arpa_inet_h" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_ARPA_INET_H 1 +_ACEOF + +fi + +done + +for ac_header in fcntl.h +do : + ac_fn_c_check_header_mongrel "$LINENO" "fcntl.h" "ac_cv_header_fcntl_h" "$ac_includes_default" +if test "x$ac_cv_header_fcntl_h" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_FCNTL_H 1 +_ACEOF + +fi + +done + +for ac_header in limits.h +do : + ac_fn_c_check_header_mongrel "$LINENO" "limits.h" "ac_cv_header_limits_h" "$ac_includes_default" +if test "x$ac_cv_header_limits_h" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_LIMITS_H 1 +_ACEOF + +fi + +done + +for ac_header in netdb.h +do : + ac_fn_c_check_header_mongrel "$LINENO" "netdb.h" "ac_cv_header_netdb_h" "$ac_includes_default" +if test "x$ac_cv_header_netdb_h" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_NETDB_H 1 +_ACEOF + +fi + +done + +for ac_header in netinet/in.h +do : + ac_fn_c_check_header_mongrel "$LINENO" "netinet/in.h" "ac_cv_header_netinet_in_h" "$ac_includes_default" +if test "x$ac_cv_header_netinet_in_h" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_NETINET_IN_H 1 +_ACEOF + +fi + +done + +for ac_header in stddef.h +do : + ac_fn_c_check_header_mongrel "$LINENO" "stddef.h" "ac_cv_header_stddef_h" "$ac_includes_default" +if test "x$ac_cv_header_stddef_h" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_STDDEF_H 1 +_ACEOF + +fi + +done + +for ac_header in sys/ioctl.h +do : + ac_fn_c_check_header_mongrel "$LINENO" "sys/ioctl.h" "ac_cv_header_sys_ioctl_h" "$ac_includes_default" +if test "x$ac_cv_header_sys_ioctl_h" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_SYS_IOCTL_H 1 +_ACEOF + +fi + +done + +for ac_header in sys/socket.h +do : + ac_fn_c_check_header_mongrel "$LINENO" "sys/socket.h" "ac_cv_header_sys_socket_h" "$ac_includes_default" +if test "x$ac_cv_header_sys_socket_h" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_SYS_SOCKET_H 1 +_ACEOF + +fi + +done + +for ac_header in sys/time.h +do : + ac_fn_c_check_header_mongrel "$LINENO" "sys/time.h" "ac_cv_header_sys_time_h" "$ac_includes_default" +if test "x$ac_cv_header_sys_time_h" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_SYS_TIME_H 1 +_ACEOF + +fi + +done + +for ac_header in errno.h +do : + ac_fn_c_check_header_mongrel "$LINENO" "errno.h" "ac_cv_header_errno_h" "$ac_includes_default" +if test "x$ac_cv_header_errno_h" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_ERRNO_H 1 +_ACEOF + +fi + +done + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for socket in -lnetwork" >&5 +$as_echo_n "checking for socket in -lnetwork... " >&6; } +if ${ac_cv_lib_network_socket+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lnetwork $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char socket (); +int +main () +{ +return socket (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_network_socket=yes +else + ac_cv_lib_network_socket=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_network_socket" >&5 +$as_echo "$ac_cv_lib_network_socket" >&6; } +if test "x$ac_cv_lib_network_socket" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_LIBNETWORK 1 +_ACEOF + + LIBS="-lnetwork $LIBS" + +fi + +# The cast to long int works around a bug in the HP C Compiler +# version HP92453-01 B.11.11.23709.GP, which incorrectly rejects +# declarations like `int a3[[(sizeof (unsigned char)) >= 0]];'. +# This bug is HP SR number 8606223364. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking size of long long" >&5 +$as_echo_n "checking size of long long... " >&6; } +if ${ac_cv_sizeof_long_long+:} false; then : + $as_echo_n "(cached) " >&6 +else + if ac_fn_c_compute_int "$LINENO" "(long int) (sizeof (long long))" "ac_cv_sizeof_long_long" "$ac_includes_default"; then : + +else + if test "$ac_cv_type_long_long" = yes; then + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error 77 "cannot compute sizeof (long long) +See \`config.log' for more details" "$LINENO" 5; } + else + ac_cv_sizeof_long_long=0 + fi +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_sizeof_long_long" >&5 +$as_echo "$ac_cv_sizeof_long_long" >&6; } + + + +cat >>confdefs.h <<_ACEOF +#define SIZEOF_LONG_LONG $ac_cv_sizeof_long_long +_ACEOF + + +# The cast to long int works around a bug in the HP C Compiler +# version HP92453-01 B.11.11.23709.GP, which incorrectly rejects +# declarations like `int a3[[(sizeof (unsigned char)) >= 0]];'. +# This bug is HP SR number 8606223364. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking size of long" >&5 +$as_echo_n "checking size of long... " >&6; } +if ${ac_cv_sizeof_long+:} false; then : + $as_echo_n "(cached) " >&6 +else + if ac_fn_c_compute_int "$LINENO" "(long int) (sizeof (long))" "ac_cv_sizeof_long" "$ac_includes_default"; then : + +else + if test "$ac_cv_type_long" = yes; then + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error 77 "cannot compute sizeof (long) +See \`config.log' for more details" "$LINENO" 5; } + else + ac_cv_sizeof_long=0 + fi +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_sizeof_long" >&5 +$as_echo "$ac_cv_sizeof_long" >&6; } + + + +cat >>confdefs.h <<_ACEOF +#define SIZEOF_LONG $ac_cv_sizeof_long +_ACEOF + + +ac_fn_c_check_type "$LINENO" "__uint128_t" "ac_cv_type___uint128_t" "$ac_includes_default" +if test "x$ac_cv_type___uint128_t" = xyes; then : + +cat >>confdefs.h <<_ACEOF +#define HAVE___UINT128_T 1 +_ACEOF + + +fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether byte ordering is bigendian" >&5 +$as_echo_n "checking whether byte ordering is bigendian... " >&6; } +if ${ac_cv_c_bigendian+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_cv_c_bigendian=unknown + # See if we're dealing with a universal compiler. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifndef __APPLE_CC__ + not a universal capable compiler + #endif + typedef int dummy; + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + + # Check for potential -arch flags. It is not universal unless + # there are at least two -arch flags with different values. + ac_arch= + ac_prev= + for ac_word in $CC $CFLAGS $CPPFLAGS $LDFLAGS; do + if test -n "$ac_prev"; then + case $ac_word in + i?86 | x86_64 | ppc | ppc64) + if test -z "$ac_arch" || test "$ac_arch" = "$ac_word"; then + ac_arch=$ac_word + else + ac_cv_c_bigendian=universal + break + fi + ;; + esac + ac_prev= + elif test "x$ac_word" = "x-arch"; then + ac_prev=arch + fi + done +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test $ac_cv_c_bigendian = unknown; then + # See if sys/param.h defines the BYTE_ORDER macro. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + #include + +int +main () +{ +#if ! (defined BYTE_ORDER && defined BIG_ENDIAN \ + && defined LITTLE_ENDIAN && BYTE_ORDER && BIG_ENDIAN \ + && LITTLE_ENDIAN) + bogus endian macros + #endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + # It does; now see whether it defined to BIG_ENDIAN or not. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + #include + +int +main () +{ +#if BYTE_ORDER != BIG_ENDIAN + not big endian + #endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_c_bigendian=yes +else + ac_cv_c_bigendian=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + fi + if test $ac_cv_c_bigendian = unknown; then + # See if defines _LITTLE_ENDIAN or _BIG_ENDIAN (e.g., Solaris). + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +int +main () +{ +#if ! (defined _LITTLE_ENDIAN || defined _BIG_ENDIAN) + bogus endian macros + #endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + # It does; now see whether it defined to _BIG_ENDIAN or not. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +int +main () +{ +#ifndef _BIG_ENDIAN + not big endian + #endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_c_bigendian=yes +else + ac_cv_c_bigendian=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + fi + if test $ac_cv_c_bigendian = unknown; then + # Compile a test program. + if test "$cross_compiling" = yes; then : + # Try to guess by grepping values from an object file. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +short int ascii_mm[] = + { 0x4249, 0x4765, 0x6E44, 0x6961, 0x6E53, 0x7953, 0 }; + short int ascii_ii[] = + { 0x694C, 0x5454, 0x656C, 0x6E45, 0x6944, 0x6E61, 0 }; + int use_ascii (int i) { + return ascii_mm[i] + ascii_ii[i]; + } + short int ebcdic_ii[] = + { 0x89D3, 0xE3E3, 0x8593, 0x95C5, 0x89C4, 0x9581, 0 }; + short int ebcdic_mm[] = + { 0xC2C9, 0xC785, 0x95C4, 0x8981, 0x95E2, 0xA8E2, 0 }; + int use_ebcdic (int i) { + return ebcdic_mm[i] + ebcdic_ii[i]; + } + extern int foo; + +int +main () +{ +return use_ascii (foo) == use_ebcdic (foo); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + if grep BIGenDianSyS conftest.$ac_objext >/dev/null; then + ac_cv_c_bigendian=yes + fi + if grep LiTTleEnDian conftest.$ac_objext >/dev/null ; then + if test "$ac_cv_c_bigendian" = unknown; then + ac_cv_c_bigendian=no + else + # finding both strings is unlikely to happen, but who knows? + ac_cv_c_bigendian=unknown + fi + fi +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$ac_includes_default +int +main () +{ + + /* Are we little or big endian? From Harbison&Steele. */ + union + { + long int l; + char c[sizeof (long int)]; + } u; + u.l = 1; + return u.c[sizeof (long int) - 1] == 1; + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + ac_cv_c_bigendian=no +else + ac_cv_c_bigendian=yes +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_bigendian" >&5 +$as_echo "$ac_cv_c_bigendian" >&6; } + case $ac_cv_c_bigendian in #( + yes) + $as_echo "#define WORDS_BIGENDIAN 1" >>confdefs.h +;; #( + no) + ;; #( + universal) + +$as_echo "#define AC_APPLE_UNIVERSAL_BUILD 1" >>confdefs.h + + ;; #( + *) + as_fn_error $? "unknown endianness + presetting ac_cv_c_bigendian=no (or yes) will help" "$LINENO" 5 ;; + esac + +# mktime check takes forever on some systems, if time supported it would be +# highly unusual for mktime to be missing +#AC_FUNC_MKTIME + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args. +set dummy ${ac_tool_prefix}gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_CC="${ac_tool_prefix}gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_CC"; then + ac_ct_CC=$CC + # Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_CC="gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +else + CC="$ac_cv_prog_CC" +fi + +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args. +set dummy ${ac_tool_prefix}cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_CC="${ac_tool_prefix}cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + fi +fi +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + ac_prog_rejected=no +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# != 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" + fi +fi +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + for ac_prog in cl.exe + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_CC="$ac_tool_prefix$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$CC" && break + done +fi +if test -z "$CC"; then + ac_ct_CC=$CC + for ac_prog in cl.exe +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_CC="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$ac_ct_CC" && break +done + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +fi + +fi + + +test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error $? "no acceptable C compiler found in \$PATH +See \`config.log' for more details" "$LINENO" 5; } + +# Provide some information about the compiler. +$as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5 +set X $ac_compile +ac_compiler=$2 +for ac_option in --version -v -V -qversion; do + { { ac_try="$ac_compiler $ac_option >&5" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compiler $ac_option >&5") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + sed '10a\ +... rest of stderr output deleted ... + 10q' conftest.err >conftest.er1 + cat conftest.er1 >&5 + fi + rm -f conftest.er1 conftest.err + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } +done + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C compiler" >&5 +$as_echo_n "checking whether we are using the GNU C compiler... " >&6; } +if ${ac_cv_c_compiler_gnu+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +#ifndef __GNUC__ + choke me +#endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_compiler_gnu=yes +else + ac_compiler_gnu=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +ac_cv_c_compiler_gnu=$ac_compiler_gnu + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_compiler_gnu" >&5 +$as_echo "$ac_cv_c_compiler_gnu" >&6; } +if test $ac_compiler_gnu = yes; then + GCC=yes +else + GCC= +fi +ac_test_CFLAGS=${CFLAGS+set} +ac_save_CFLAGS=$CFLAGS +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5 +$as_echo_n "checking whether $CC accepts -g... " >&6; } +if ${ac_cv_prog_cc_g+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_save_c_werror_flag=$ac_c_werror_flag + ac_c_werror_flag=yes + ac_cv_prog_cc_g=no + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +else + CFLAGS="" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + +else + ac_c_werror_flag=$ac_save_c_werror_flag + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_c_werror_flag=$ac_save_c_werror_flag +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_g" >&5 +$as_echo "$ac_cv_prog_cc_g" >&6; } +if test "$ac_test_CFLAGS" = set; then + CFLAGS=$ac_save_CFLAGS +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $CC option to accept ISO C89" >&5 +$as_echo_n "checking for $CC option to accept ISO C89... " >&6; } +if ${ac_cv_prog_cc_c89+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_cv_prog_cc_c89=no +ac_save_CC=$CC +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +struct stat; +/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ +struct buf { int x; }; +FILE * (*rcsopen) (struct buf *, struct stat *, int); +static char *e (p, i) + char **p; + int i; +{ + return p[i]; +} +static char *f (char * (*g) (char **, int), char **p, ...) +{ + char *s; + va_list v; + va_start (v,p); + s = g (p, va_arg (v,int)); + va_end (v); + return s; +} + +/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has + function prototypes and stuff, but not '\xHH' hex character constants. + These don't provoke an error unfortunately, instead are silently treated + as 'x'. The following induces an error, until -std is added to get + proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an + array size at least. It's necessary to write '\x00'==0 to get something + that's true only with -std. */ +int osf4_cc_array ['\x00' == 0 ? 1 : -1]; + +/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters + inside strings and character constants. */ +#define FOO(x) 'x' +int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1]; + +int test (int i, double x); +struct s1 {int (*f) (int a);}; +struct s2 {int (*f) (double a);}; +int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int); +int argc; +char **argv; +int +main () +{ +return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1]; + ; + return 0; +} +_ACEOF +for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \ + -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__" +do + CC="$ac_save_CC $ac_arg" + if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_c89=$ac_arg +fi +rm -f core conftest.err conftest.$ac_objext + test "x$ac_cv_prog_cc_c89" != "xno" && break +done +rm -f conftest.$ac_ext +CC=$ac_save_CC + +fi +# AC_CACHE_VAL +case "x$ac_cv_prog_cc_c89" in + x) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: none needed" >&5 +$as_echo "none needed" >&6; } ;; + xno) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5 +$as_echo "unsupported" >&6; } ;; + *) + CC="$CC $ac_cv_prog_cc_c89" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c89" >&5 +$as_echo "$ac_cv_prog_cc_c89" >&6; } ;; +esac +if test "x$ac_cv_prog_cc_c89" != xno; then : + +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC understands -c and -o together" >&5 +$as_echo_n "checking whether $CC understands -c and -o together... " >&6; } +if ${am_cv_prog_cc_c_o+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF + # Make sure it works both with $CC and with simple cc. + # Following AC_PROG_CC_C_O, we do the test twice because some + # compilers refuse to overwrite an existing .o file with -o, + # though they will create one. + am_cv_prog_cc_c_o=yes + for am_i in 1 2; do + if { echo "$as_me:$LINENO: $CC -c conftest.$ac_ext -o conftest2.$ac_objext" >&5 + ($CC -c conftest.$ac_ext -o conftest2.$ac_objext) >&5 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } \ + && test -f conftest2.$ac_objext; then + : OK + else + am_cv_prog_cc_c_o=no + break + fi + done + rm -f core conftest* + unset am_i +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_prog_cc_c_o" >&5 +$as_echo "$am_cv_prog_cc_c_o" >&6; } +if test "$am_cv_prog_cc_c_o" != yes; then + # Losing compiler, so override with the script. + # FIXME: It is wrong to rewrite CC. + # But if we don't then we get into trouble of one sort or another. + # A longer-term fix would be to have automake use am__CC in this case, + # and then we could set am__CC="\$(top_srcdir)/compile \$(CC)" + CC="$am_aux_dir/compile $CC" +fi +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + +depcc="$CC" am_compiler_list= + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking dependency style of $depcc" >&5 +$as_echo_n "checking dependency style of $depcc... " >&6; } +if ${am_cv_CC_dependencies_compiler_type+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -z "$AMDEP_TRUE" && test -f "$am_depcomp"; then + # We make a subdir and do the tests there. Otherwise we can end up + # making bogus files that we don't know about and never remove. For + # instance it was reported that on HP-UX the gcc test will end up + # making a dummy file named 'D' -- because '-MD' means "put the output + # in D". + rm -rf conftest.dir + mkdir conftest.dir + # Copy depcomp to subdir because otherwise we won't find it if we're + # using a relative directory. + cp "$am_depcomp" conftest.dir + cd conftest.dir + # We will build objects and dependencies in a subdirectory because + # it helps to detect inapplicable dependency modes. For instance + # both Tru64's cc and ICC support -MD to output dependencies as a + # side effect of compilation, but ICC will put the dependencies in + # the current directory while Tru64 will put them in the object + # directory. + mkdir sub + + am_cv_CC_dependencies_compiler_type=none + if test "$am_compiler_list" = ""; then + am_compiler_list=`sed -n 's/^#*\([a-zA-Z0-9]*\))$/\1/p' < ./depcomp` + fi + am__universal=false + case " $depcc " in #( + *\ -arch\ *\ -arch\ *) am__universal=true ;; + esac + + for depmode in $am_compiler_list; do + # Setup a source with many dependencies, because some compilers + # like to wrap large dependency lists on column 80 (with \), and + # we should not choose a depcomp mode which is confused by this. + # + # We need to recreate these files for each test, as the compiler may + # overwrite some of them when testing with obscure command lines. + # This happens at least with the AIX C compiler. + : > sub/conftest.c + for i in 1 2 3 4 5 6; do + echo '#include "conftst'$i'.h"' >> sub/conftest.c + # Using ": > sub/conftst$i.h" creates only sub/conftst1.h with + # Solaris 10 /bin/sh. + echo '/* dummy */' > sub/conftst$i.h + done + echo "${am__include} ${am__quote}sub/conftest.Po${am__quote}" > confmf + + # We check with '-c' and '-o' for the sake of the "dashmstdout" + # mode. It turns out that the SunPro C++ compiler does not properly + # handle '-M -o', and we need to detect this. Also, some Intel + # versions had trouble with output in subdirs. + am__obj=sub/conftest.${OBJEXT-o} + am__minus_obj="-o $am__obj" + case $depmode in + gcc) + # This depmode causes a compiler race in universal mode. + test "$am__universal" = false || continue + ;; + nosideeffect) + # After this tag, mechanisms are not by side-effect, so they'll + # only be used when explicitly requested. + if test "x$enable_dependency_tracking" = xyes; then + continue + else + break + fi + ;; + msvc7 | msvc7msys | msvisualcpp | msvcmsys) + # This compiler won't grok '-c -o', but also, the minuso test has + # not run yet. These depmodes are late enough in the game, and + # so weak that their functioning should not be impacted. + am__obj=conftest.${OBJEXT-o} + am__minus_obj= + ;; + none) break ;; + esac + if depmode=$depmode \ + source=sub/conftest.c object=$am__obj \ + depfile=sub/conftest.Po tmpdepfile=sub/conftest.TPo \ + $SHELL ./depcomp $depcc -c $am__minus_obj sub/conftest.c \ + >/dev/null 2>conftest.err && + grep sub/conftst1.h sub/conftest.Po > /dev/null 2>&1 && + grep sub/conftst6.h sub/conftest.Po > /dev/null 2>&1 && + grep $am__obj sub/conftest.Po > /dev/null 2>&1 && + ${MAKE-make} -s -f confmf > /dev/null 2>&1; then + # icc doesn't choke on unknown options, it will just issue warnings + # or remarks (even with -Werror). So we grep stderr for any message + # that says an option was ignored or not supported. + # When given -MP, icc 7.0 and 7.1 complain thusly: + # icc: Command line warning: ignoring option '-M'; no argument required + # The diagnosis changed in icc 8.0: + # icc: Command line remark: option '-MP' not supported + if (grep 'ignoring option' conftest.err || + grep 'not supported' conftest.err) >/dev/null 2>&1; then :; else + am_cv_CC_dependencies_compiler_type=$depmode + break + fi + fi + done + + cd .. + rm -rf conftest.dir +else + am_cv_CC_dependencies_compiler_type=none +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_CC_dependencies_compiler_type" >&5 +$as_echo "$am_cv_CC_dependencies_compiler_type" >&6; } +CCDEPMODE=depmode=$am_cv_CC_dependencies_compiler_type + + if + test "x$enable_dependency_tracking" != xno \ + && test "$am_cv_CC_dependencies_compiler_type" = gcc3; then + am__fastdepCC_TRUE= + am__fastdepCC_FALSE='#' +else + am__fastdepCC_TRUE='#' + am__fastdepCC_FALSE= +fi + + +if test "x$CC" != xcc; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC and cc understand -c and -o together" >&5 +$as_echo_n "checking whether $CC and cc understand -c and -o together... " >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether cc understands -c and -o together" >&5 +$as_echo_n "checking whether cc understands -c and -o together... " >&6; } +fi +set dummy $CC; ac_cc=`$as_echo "$2" | + sed 's/[^a-zA-Z0-9_]/_/g;s/^[0-9]/_/'` +if eval \${ac_cv_prog_cc_${ac_cc}_c_o+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +# Make sure it works both with $CC and with simple cc. +# We do the test twice because some compilers refuse to overwrite an +# existing .o file with -o, though they will create one. +ac_try='$CC -c conftest.$ac_ext -o conftest2.$ac_objext >&5' +rm -f conftest2.* +if { { case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } && + test -f conftest2.$ac_objext && { { case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; +then + eval ac_cv_prog_cc_${ac_cc}_c_o=yes + if test "x$CC" != xcc; then + # Test first that cc exists at all. + if { ac_try='cc -c conftest.$ac_ext >&5' + { { case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; }; then + ac_try='cc -c conftest.$ac_ext -o conftest2.$ac_objext >&5' + rm -f conftest2.* + if { { case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } && + test -f conftest2.$ac_objext && { { case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; + then + # cc works too. + : + else + # cc exists but doesn't like -o. + eval ac_cv_prog_cc_${ac_cc}_c_o=no + fi + fi + fi +else + eval ac_cv_prog_cc_${ac_cc}_c_o=no +fi +rm -f core conftest* + +fi +if eval test \$ac_cv_prog_cc_${ac_cc}_c_o = yes; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } + +$as_echo "#define NO_MINUS_C_MINUS_O 1" >>confdefs.h + +fi + +ac_ext=cpp +ac_cpp='$CXXCPP $CPPFLAGS' +ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_cxx_compiler_gnu +if test -z "$CXX"; then + if test -n "$CCC"; then + CXX=$CCC + else + if test -n "$ac_tool_prefix"; then + for ac_prog in g++ c++ gpp aCC CC cxx cc++ cl.exe FCC KCC RCC xlC_r xlC + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_CXX+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CXX"; then + ac_cv_prog_CXX="$CXX" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_CXX="$ac_tool_prefix$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CXX=$ac_cv_prog_CXX +if test -n "$CXX"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CXX" >&5 +$as_echo "$CXX" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$CXX" && break + done +fi +if test -z "$CXX"; then + ac_ct_CXX=$CXX + for ac_prog in g++ c++ gpp aCC CC cxx cc++ cl.exe FCC KCC RCC xlC_r xlC +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_CXX+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CXX"; then + ac_cv_prog_ac_ct_CXX="$ac_ct_CXX" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_CXX="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CXX=$ac_cv_prog_ac_ct_CXX +if test -n "$ac_ct_CXX"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CXX" >&5 +$as_echo "$ac_ct_CXX" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$ac_ct_CXX" && break +done + + if test "x$ac_ct_CXX" = x; then + CXX="g++" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CXX=$ac_ct_CXX + fi +fi + + fi +fi +# Provide some information about the compiler. +$as_echo "$as_me:${as_lineno-$LINENO}: checking for C++ compiler version" >&5 +set X $ac_compile +ac_compiler=$2 +for ac_option in --version -v -V -qversion; do + { { ac_try="$ac_compiler $ac_option >&5" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compiler $ac_option >&5") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + sed '10a\ +... rest of stderr output deleted ... + 10q' conftest.err >conftest.er1 + cat conftest.er1 >&5 + fi + rm -f conftest.er1 conftest.err + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } +done + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C++ compiler" >&5 +$as_echo_n "checking whether we are using the GNU C++ compiler... " >&6; } +if ${ac_cv_cxx_compiler_gnu+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +#ifndef __GNUC__ + choke me +#endif + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + ac_compiler_gnu=yes +else + ac_compiler_gnu=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +ac_cv_cxx_compiler_gnu=$ac_compiler_gnu + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_cxx_compiler_gnu" >&5 +$as_echo "$ac_cv_cxx_compiler_gnu" >&6; } +if test $ac_compiler_gnu = yes; then + GXX=yes +else + GXX= +fi +ac_test_CXXFLAGS=${CXXFLAGS+set} +ac_save_CXXFLAGS=$CXXFLAGS +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CXX accepts -g" >&5 +$as_echo_n "checking whether $CXX accepts -g... " >&6; } +if ${ac_cv_prog_cxx_g+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_save_cxx_werror_flag=$ac_cxx_werror_flag + ac_cxx_werror_flag=yes + ac_cv_prog_cxx_g=no + CXXFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + ac_cv_prog_cxx_g=yes +else + CXXFLAGS="" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + +else + ac_cxx_werror_flag=$ac_save_cxx_werror_flag + CXXFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + ac_cv_prog_cxx_g=yes +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_cxx_werror_flag=$ac_save_cxx_werror_flag +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cxx_g" >&5 +$as_echo "$ac_cv_prog_cxx_g" >&6; } +if test "$ac_test_CXXFLAGS" = set; then + CXXFLAGS=$ac_save_CXXFLAGS +elif test $ac_cv_prog_cxx_g = yes; then + if test "$GXX" = yes; then + CXXFLAGS="-g -O2" + else + CXXFLAGS="-g" + fi +else + if test "$GXX" = yes; then + CXXFLAGS="-O2" + else + CXXFLAGS= + fi +fi +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + +depcc="$CXX" am_compiler_list= + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking dependency style of $depcc" >&5 +$as_echo_n "checking dependency style of $depcc... " >&6; } +if ${am_cv_CXX_dependencies_compiler_type+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -z "$AMDEP_TRUE" && test -f "$am_depcomp"; then + # We make a subdir and do the tests there. Otherwise we can end up + # making bogus files that we don't know about and never remove. For + # instance it was reported that on HP-UX the gcc test will end up + # making a dummy file named 'D' -- because '-MD' means "put the output + # in D". + rm -rf conftest.dir + mkdir conftest.dir + # Copy depcomp to subdir because otherwise we won't find it if we're + # using a relative directory. + cp "$am_depcomp" conftest.dir + cd conftest.dir + # We will build objects and dependencies in a subdirectory because + # it helps to detect inapplicable dependency modes. For instance + # both Tru64's cc and ICC support -MD to output dependencies as a + # side effect of compilation, but ICC will put the dependencies in + # the current directory while Tru64 will put them in the object + # directory. + mkdir sub + + am_cv_CXX_dependencies_compiler_type=none + if test "$am_compiler_list" = ""; then + am_compiler_list=`sed -n 's/^#*\([a-zA-Z0-9]*\))$/\1/p' < ./depcomp` + fi + am__universal=false + case " $depcc " in #( + *\ -arch\ *\ -arch\ *) am__universal=true ;; + esac + + for depmode in $am_compiler_list; do + # Setup a source with many dependencies, because some compilers + # like to wrap large dependency lists on column 80 (with \), and + # we should not choose a depcomp mode which is confused by this. + # + # We need to recreate these files for each test, as the compiler may + # overwrite some of them when testing with obscure command lines. + # This happens at least with the AIX C compiler. + : > sub/conftest.c + for i in 1 2 3 4 5 6; do + echo '#include "conftst'$i'.h"' >> sub/conftest.c + # Using ": > sub/conftst$i.h" creates only sub/conftst1.h with + # Solaris 10 /bin/sh. + echo '/* dummy */' > sub/conftst$i.h + done + echo "${am__include} ${am__quote}sub/conftest.Po${am__quote}" > confmf + + # We check with '-c' and '-o' for the sake of the "dashmstdout" + # mode. It turns out that the SunPro C++ compiler does not properly + # handle '-M -o', and we need to detect this. Also, some Intel + # versions had trouble with output in subdirs. + am__obj=sub/conftest.${OBJEXT-o} + am__minus_obj="-o $am__obj" + case $depmode in + gcc) + # This depmode causes a compiler race in universal mode. + test "$am__universal" = false || continue + ;; + nosideeffect) + # After this tag, mechanisms are not by side-effect, so they'll + # only be used when explicitly requested. + if test "x$enable_dependency_tracking" = xyes; then + continue + else + break + fi + ;; + msvc7 | msvc7msys | msvisualcpp | msvcmsys) + # This compiler won't grok '-c -o', but also, the minuso test has + # not run yet. These depmodes are late enough in the game, and + # so weak that their functioning should not be impacted. + am__obj=conftest.${OBJEXT-o} + am__minus_obj= + ;; + none) break ;; + esac + if depmode=$depmode \ + source=sub/conftest.c object=$am__obj \ + depfile=sub/conftest.Po tmpdepfile=sub/conftest.TPo \ + $SHELL ./depcomp $depcc -c $am__minus_obj sub/conftest.c \ + >/dev/null 2>conftest.err && + grep sub/conftst1.h sub/conftest.Po > /dev/null 2>&1 && + grep sub/conftst6.h sub/conftest.Po > /dev/null 2>&1 && + grep $am__obj sub/conftest.Po > /dev/null 2>&1 && + ${MAKE-make} -s -f confmf > /dev/null 2>&1; then + # icc doesn't choke on unknown options, it will just issue warnings + # or remarks (even with -Werror). So we grep stderr for any message + # that says an option was ignored or not supported. + # When given -MP, icc 7.0 and 7.1 complain thusly: + # icc: Command line warning: ignoring option '-M'; no argument required + # The diagnosis changed in icc 8.0: + # icc: Command line remark: option '-MP' not supported + if (grep 'ignoring option' conftest.err || + grep 'not supported' conftest.err) >/dev/null 2>&1; then :; else + am_cv_CXX_dependencies_compiler_type=$depmode + break + fi + fi + done + + cd .. + rm -rf conftest.dir +else + am_cv_CXX_dependencies_compiler_type=none +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_CXX_dependencies_compiler_type" >&5 +$as_echo "$am_cv_CXX_dependencies_compiler_type" >&6; } +CXXDEPMODE=depmode=$am_cv_CXX_dependencies_compiler_type + + if + test "x$enable_dependency_tracking" != xno \ + && test "$am_cv_CXX_dependencies_compiler_type" = gcc3; then + am__fastdepCXX_TRUE= + am__fastdepCXX_FALSE='#' +else + am__fastdepCXX_TRUE='#' + am__fastdepCXX_FALSE= +fi + + + +ac_fn_c_check_type "$LINENO" "size_t" "ac_cv_type_size_t" "$ac_includes_default" +if test "x$ac_cv_type_size_t" = xyes; then : + +else + +cat >>confdefs.h <<_ACEOF +#define size_t unsigned int +_ACEOF + +fi + +ac_fn_c_find_uintX_t "$LINENO" "8" "ac_cv_c_uint8_t" +case $ac_cv_c_uint8_t in #( + no|yes) ;; #( + *) + +$as_echo "#define _UINT8_T 1" >>confdefs.h + + +cat >>confdefs.h <<_ACEOF +#define uint8_t $ac_cv_c_uint8_t +_ACEOF +;; + esac + +# By default we simply use the C compiler to build assembly code. + +test "${CCAS+set}" = set || CCAS=$CC +test "${CCASFLAGS+set}" = set || CCASFLAGS=$CFLAGS + + + +depcc="$CCAS" am_compiler_list= + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking dependency style of $depcc" >&5 +$as_echo_n "checking dependency style of $depcc... " >&6; } +if ${am_cv_CCAS_dependencies_compiler_type+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -z "$AMDEP_TRUE" && test -f "$am_depcomp"; then + # We make a subdir and do the tests there. Otherwise we can end up + # making bogus files that we don't know about and never remove. For + # instance it was reported that on HP-UX the gcc test will end up + # making a dummy file named 'D' -- because '-MD' means "put the output + # in D". + rm -rf conftest.dir + mkdir conftest.dir + # Copy depcomp to subdir because otherwise we won't find it if we're + # using a relative directory. + cp "$am_depcomp" conftest.dir + cd conftest.dir + # We will build objects and dependencies in a subdirectory because + # it helps to detect inapplicable dependency modes. For instance + # both Tru64's cc and ICC support -MD to output dependencies as a + # side effect of compilation, but ICC will put the dependencies in + # the current directory while Tru64 will put them in the object + # directory. + mkdir sub + + am_cv_CCAS_dependencies_compiler_type=none + if test "$am_compiler_list" = ""; then + am_compiler_list=`sed -n 's/^#*\([a-zA-Z0-9]*\))$/\1/p' < ./depcomp` + fi + am__universal=false + + + for depmode in $am_compiler_list; do + # Setup a source with many dependencies, because some compilers + # like to wrap large dependency lists on column 80 (with \), and + # we should not choose a depcomp mode which is confused by this. + # + # We need to recreate these files for each test, as the compiler may + # overwrite some of them when testing with obscure command lines. + # This happens at least with the AIX C compiler. + : > sub/conftest.c + for i in 1 2 3 4 5 6; do + echo '#include "conftst'$i'.h"' >> sub/conftest.c + # Using ": > sub/conftst$i.h" creates only sub/conftst1.h with + # Solaris 10 /bin/sh. + echo '/* dummy */' > sub/conftst$i.h + done + echo "${am__include} ${am__quote}sub/conftest.Po${am__quote}" > confmf + + # We check with '-c' and '-o' for the sake of the "dashmstdout" + # mode. It turns out that the SunPro C++ compiler does not properly + # handle '-M -o', and we need to detect this. Also, some Intel + # versions had trouble with output in subdirs. + am__obj=sub/conftest.${OBJEXT-o} + am__minus_obj="-o $am__obj" + case $depmode in + gcc) + # This depmode causes a compiler race in universal mode. + test "$am__universal" = false || continue + ;; + nosideeffect) + # After this tag, mechanisms are not by side-effect, so they'll + # only be used when explicitly requested. + if test "x$enable_dependency_tracking" = xyes; then + continue + else + break + fi + ;; + msvc7 | msvc7msys | msvisualcpp | msvcmsys) + # This compiler won't grok '-c -o', but also, the minuso test has + # not run yet. These depmodes are late enough in the game, and + # so weak that their functioning should not be impacted. + am__obj=conftest.${OBJEXT-o} + am__minus_obj= + ;; + none) break ;; + esac + if depmode=$depmode \ + source=sub/conftest.c object=$am__obj \ + depfile=sub/conftest.Po tmpdepfile=sub/conftest.TPo \ + $SHELL ./depcomp $depcc -c $am__minus_obj sub/conftest.c \ + >/dev/null 2>conftest.err && + grep sub/conftst1.h sub/conftest.Po > /dev/null 2>&1 && + grep sub/conftst6.h sub/conftest.Po > /dev/null 2>&1 && + grep $am__obj sub/conftest.Po > /dev/null 2>&1 && + ${MAKE-make} -s -f confmf > /dev/null 2>&1; then + # icc doesn't choke on unknown options, it will just issue warnings + # or remarks (even with -Werror). So we grep stderr for any message + # that says an option was ignored or not supported. + # When given -MP, icc 7.0 and 7.1 complain thusly: + # icc: Command line warning: ignoring option '-M'; no argument required + # The diagnosis changed in icc 8.0: + # icc: Command line remark: option '-MP' not supported + if (grep 'ignoring option' conftest.err || + grep 'not supported' conftest.err) >/dev/null 2>&1; then :; else + am_cv_CCAS_dependencies_compiler_type=$depmode + break + fi + fi + done + + cd .. + rm -rf conftest.dir +else + am_cv_CCAS_dependencies_compiler_type=none +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_CCAS_dependencies_compiler_type" >&5 +$as_echo "$am_cv_CCAS_dependencies_compiler_type" >&6; } +CCASDEPMODE=depmode=$am_cv_CCAS_dependencies_compiler_type + + if + test "x$enable_dependency_tracking" != xno \ + && test "$am_cv_CCAS_dependencies_compiler_type" = gcc3; then + am__fastdepCCAS_TRUE= + am__fastdepCCAS_FALSE='#' +else + am__fastdepCCAS_TRUE='#' + am__fastdepCCAS_FALSE= +fi + + + +LIBM= +case $host in +*-*-beos* | *-*-cegcc* | *-*-cygwin* | *-*-haiku* | *-*-pw32* | *-*-darwin*) + # These system don't have libm, or don't need it + ;; +*-ncr-sysv4.3*) + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for _mwvalidcheckl in -lmw" >&5 +$as_echo_n "checking for _mwvalidcheckl in -lmw... " >&6; } +if ${ac_cv_lib_mw__mwvalidcheckl+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lmw $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char _mwvalidcheckl (); +int +main () +{ +return _mwvalidcheckl (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_mw__mwvalidcheckl=yes +else + ac_cv_lib_mw__mwvalidcheckl=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_mw__mwvalidcheckl" >&5 +$as_echo "$ac_cv_lib_mw__mwvalidcheckl" >&6; } +if test "x$ac_cv_lib_mw__mwvalidcheckl" = xyes; then : + LIBM="-lmw" +fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for cos in -lm" >&5 +$as_echo_n "checking for cos in -lm... " >&6; } +if ${ac_cv_lib_m_cos+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lm $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char cos (); +int +main () +{ +return cos (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_m_cos=yes +else + ac_cv_lib_m_cos=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_m_cos" >&5 +$as_echo "$ac_cv_lib_m_cos" >&6; } +if test "x$ac_cv_lib_m_cos" = xyes; then : + LIBM="$LIBM -lm" +fi + + ;; +*) + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for cos in -lm" >&5 +$as_echo_n "checking for cos in -lm... " >&6; } +if ${ac_cv_lib_m_cos+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lm $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char cos (); +int +main () +{ +return cos (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_m_cos=yes +else + ac_cv_lib_m_cos=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_m_cos" >&5 +$as_echo "$ac_cv_lib_m_cos" >&6; } +if test "x$ac_cv_lib_m_cos" = xyes; then : + LIBM="-lm" +fi + + ;; +esac + + + +OPTIMIZE_CFLAGS="-Os -fomit-frame-pointer" +OPTIMIZE_FAST_CFLAGS="-O2 -fomit-frame-pointer" +OPTIMIZE_HUGE_CFLAGS="-funroll-loops -DTFM_SMALL_SET -DTFM_HUGE_SET" +DEBUG_CFLAGS="-g -DDEBUG -DDEBUG_WOLFSSL" + +thread_ls_on=no +# Thread local storage + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for thread local storage (TLS) class" >&5 +$as_echo_n "checking for thread local storage (TLS) class... " >&6; } + if ${ac_cv_tls+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_tls_keywords="__thread __declspec(thread) none" + for ax_tls_keyword in $ax_tls_keywords; do + case $ax_tls_keyword in #( + none) : + ac_cv_tls=none ; break ;; #( + *) : + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + static void + foo(void) { + static $ax_tls_keyword int bar; + exit(1); + } +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_tls=$ax_tls_keyword ; break +else + ac_cv_tls=none + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext ;; +esac + done + +fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_tls" >&5 +$as_echo "$ac_cv_tls" >&6; } + + if test "$ac_cv_tls" != "none"; then : + +cat >>confdefs.h <<_ACEOF +#define TLS $ac_cv_tls +_ACEOF + + + AM_CFLAGS="$AM_CFLAGS -DHAVE_THREAD_LS" + thread_ls_on=yes + +else + : + +fi + + + +# DEBUG + # Check whether --enable-debug was given. +if test "${enable_debug+set}" = set; then : + enableval=$enable_debug; ax_enable_debug=$enableval +else + ax_enable_debug=no +fi + + + if test "x$ax_enable_debug" = xyes; then : + +$as_echo "#define DEBUG 1" >>confdefs.h + +else + + +$as_echo "#define DEBUG 0" >>confdefs.h + +fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for debug" >&5 +$as_echo_n "checking for debug... " >&6; } + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ax_enable_debug" >&5 +$as_echo "$ax_enable_debug" >&6; } + if test "x${ax_enable_debug}" = xyes; then + DEBUG_TRUE= + DEBUG_FALSE='#' +else + DEBUG_TRUE='#' + DEBUG_FALSE= +fi + +if test "$ax_enable_debug" = "yes"; then : + AM_CFLAGS="$DEBUG_CFLAGS $AM_CFLAGS" +else + AM_CFLAGS="$AM_CFLAGS -DNDEBUG" +fi + + +# SINGLE THREADED +# Check whether --enable-singlethreaded was given. +if test "${enable_singlethreaded+set}" = set; then : + enableval=$enable_singlethreaded; ENABLED_SINGLETHREADED=$enableval +else + ENABLED_SINGLETHREADED=no +fi + + + + if test x"$CC" = xclang; then + wolfssl_darwin_clang=yes + elif test x"$CC" = x || test x"$CC" = xgcc; then + if /usr/bin/gcc -v 2>&1 | grep 'clang' >/dev/null 2>&1; then + wolfssl_darwin_clang=yes + fi + fi + +if test "x$ENABLED_SINGLETHREADED" = "xno" ; then : + + + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + +ax_pthread_ok=no + +# We used to check for pthread.h first, but this fails if pthread.h +# requires special compiler flags (e.g. on True64 or Sequent). +# It gets checked for in the link test anyway. + +# First of all, check if the user has set any of the PTHREAD_LIBS, +# etcetera environment variables, and if threads linking works using +# them: +if test x"$PTHREAD_LIBS$PTHREAD_CFLAGS" != x; then + save_CFLAGS="$CFLAGS" + CFLAGS="$CFLAGS $PTHREAD_CFLAGS" + save_LIBS="$LIBS" + LIBS="$PTHREAD_LIBS $LIBS" + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for pthread_join in LIBS=$PTHREAD_LIBS with CFLAGS=$PTHREAD_CFLAGS" >&5 +$as_echo_n "checking for pthread_join in LIBS=$PTHREAD_LIBS with CFLAGS=$PTHREAD_CFLAGS... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char pthread_join (); +int +main () +{ +return pthread_join (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ax_pthread_ok=yes +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ax_pthread_ok" >&5 +$as_echo "$ax_pthread_ok" >&6; } + if test x"$ax_pthread_ok" = xno; then + PTHREAD_LIBS="" + PTHREAD_CFLAGS="" + fi + LIBS="$save_LIBS" + CFLAGS="$save_CFLAGS" +fi + +# We must check for the threads library under a number of different +# names; the ordering is very important because some systems +# (e.g. DEC) have both -lpthread and -lpthreads, where one of the +# libraries is broken (non-POSIX). + +# Create a list of thread flags to try. Items starting with a "-" are +# C compiler flags, and other items are library names, except for "none" +# which indicates that we try without any flags at all, and "pthread-config" +# which is a program returning the flags for the Pth emulation library. + +ax_pthread_flags="pthreads none -Kthread -kthread lthread -pthread -pthreads -mthreads pthread --thread-safe -mt pthread-config" + +# The ordering *is* (sometimes) important. Some notes on the +# individual items follow: + +# pthreads: AIX (must check this before -lpthread) +# none: in case threads are in libc; should be tried before -Kthread and +# other compiler flags to prevent continual compiler warnings +# -Kthread: Sequent (threads in libc, but -Kthread needed for pthread.h) +# -kthread: FreeBSD kernel threads (preferred to -pthread since SMP-able) +# lthread: LinuxThreads port on FreeBSD (also preferred to -pthread) +# -pthread: Linux/gcc (kernel threads), BSD/gcc (userland threads) +# -pthreads: Solaris/gcc +# -mthreads: Mingw32/gcc, Lynx/gcc +# -mt: Sun Workshop C (may only link SunOS threads [-lthread], but it +# doesn't hurt to check since this sometimes defines pthreads too; +# also defines -D_REENTRANT) +# ... -mt is also the pthreads flag for HP/aCC +# pthread: Linux, etcetera +# --thread-safe: KAI C++ +# pthread-config: use pthread-config program (for GNU Pth library) + +case ${host_os} in + solaris*) + + # On Solaris (at least, for some versions), libc contains stubbed + # (non-functional) versions of the pthreads routines, so link-based + # tests will erroneously succeed. (We need to link with -pthreads/-mt/ + # -lpthread.) (The stubs are missing pthread_cleanup_push, or rather + # a function called by this macro, so we could check for that, but + # who knows whether they'll stub that too in a future libc.) So, + # we'll just look for -pthreads and -lpthread first: + + ax_pthread_flags="-pthreads pthread -mt -pthread $ax_pthread_flags" + ;; + + darwin*) + + if test x"$wolfssl_darwin_clang" = x"yes"; then : + ax_pthread_flags="$ax_pthread_flags" +else + ax_pthread_flags="-pthread $ax_pthread_flags" +fi + ;; +esac + +if test x"$ax_pthread_ok" = xno; then +for flag in $ax_pthread_flags; do + + case $flag in + none) + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether pthreads work without any flags" >&5 +$as_echo_n "checking whether pthreads work without any flags... " >&6; } + ;; + + -*) + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether pthreads work with $flag" >&5 +$as_echo_n "checking whether pthreads work with $flag... " >&6; } + PTHREAD_CFLAGS="$flag" + ;; + + pthread-config) + # Extract the first word of "pthread-config", so it can be a program name with args. +set dummy pthread-config; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ax_pthread_config+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ax_pthread_config"; then + ac_cv_prog_ax_pthread_config="$ax_pthread_config" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ax_pthread_config="yes" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + + test -z "$ac_cv_prog_ax_pthread_config" && ac_cv_prog_ax_pthread_config="no" +fi +fi +ax_pthread_config=$ac_cv_prog_ax_pthread_config +if test -n "$ax_pthread_config"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ax_pthread_config" >&5 +$as_echo "$ax_pthread_config" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + if test x"$ax_pthread_config" = xno; then continue; fi + PTHREAD_CFLAGS="`pthread-config --cflags`" + PTHREAD_LIBS="`pthread-config --ldflags` `pthread-config --libs`" + ;; + + *) + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for the pthreads library -l$flag" >&5 +$as_echo_n "checking for the pthreads library -l$flag... " >&6; } + PTHREAD_LIBS="-l$flag" + ;; + esac + + save_LIBS="$LIBS" + save_CFLAGS="$CFLAGS" + LIBS="$PTHREAD_LIBS $LIBS" + CFLAGS="$CFLAGS $PTHREAD_CFLAGS" + + # Check for various functions. We must include pthread.h, + # since some functions may be macros. (On the Sequent, we + # need a special flag -Kthread to make this header compile.) + # We check for pthread_join because it is in -lpthread on IRIX + # while pthread_create is in libc. We check for pthread_attr_init + # due to DEC craziness with -lpthreads. We check for + # pthread_cleanup_push because it is one of the few pthread + # functions on Solaris that doesn't have a non-functional libc stub. + # We try pthread_create on general principles. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + static void routine(void *a) { a = 0; } + static void *start_routine(void *a) { return a; } +int +main () +{ +pthread_t th; pthread_attr_t attr; + pthread_create(&th, 0, start_routine, 0); + pthread_join(th, 0); + pthread_attr_init(&attr); + pthread_cleanup_push(routine, 0); + pthread_cleanup_pop(0) /* ; */ + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ax_pthread_ok=yes +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + + LIBS="$save_LIBS" + CFLAGS="$save_CFLAGS" + + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ax_pthread_ok" >&5 +$as_echo "$ax_pthread_ok" >&6; } + if test "x$ax_pthread_ok" = xyes; then + break; + fi + + PTHREAD_LIBS="" + PTHREAD_CFLAGS="" +done +fi + +# Various other checks: +if test "x$ax_pthread_ok" = xyes; then + save_LIBS="$LIBS" + LIBS="$PTHREAD_LIBS $LIBS" + save_CFLAGS="$CFLAGS" + CFLAGS="$CFLAGS $PTHREAD_CFLAGS" + + # Detect AIX lossage: JOINABLE attribute is called UNDETACHED. + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for joinable pthread attribute" >&5 +$as_echo_n "checking for joinable pthread attribute... " >&6; } + attr_name=unknown + for attr in PTHREAD_CREATE_JOINABLE PTHREAD_CREATE_UNDETACHED; do + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +int +main () +{ +int attr = $attr; return attr /* ; */ + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + attr_name=$attr; break +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + done + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $attr_name" >&5 +$as_echo "$attr_name" >&6; } + if test "$attr_name" != PTHREAD_CREATE_JOINABLE; then + +cat >>confdefs.h <<_ACEOF +#define PTHREAD_CREATE_JOINABLE $attr_name +_ACEOF + + fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if more special flags are required for pthreads" >&5 +$as_echo_n "checking if more special flags are required for pthreads... " >&6; } + flag=no + case ${host_os} in + aix* | freebsd* | darwin*) flag="-D_THREAD_SAFE";; + osf* | hpux*) flag="-D_REENTRANT";; + solaris*) + if test "$GCC" = "yes"; then + flag="-D_REENTRANT" + else + flag="-mt -D_REENTRANT" + fi + ;; + esac + { $as_echo "$as_me:${as_lineno-$LINENO}: result: ${flag}" >&5 +$as_echo "${flag}" >&6; } + if test "x$flag" != xno; then + PTHREAD_CFLAGS="$flag $PTHREAD_CFLAGS" + fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for PTHREAD_PRIO_INHERIT" >&5 +$as_echo_n "checking for PTHREAD_PRIO_INHERIT... " >&6; } +if ${ax_cv_PTHREAD_PRIO_INHERIT+:} false; then : + $as_echo_n "(cached) " >&6 +else + + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + + #include +int +main () +{ +int i = PTHREAD_PRIO_INHERIT; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ax_cv_PTHREAD_PRIO_INHERIT=yes +else + ax_cv_PTHREAD_PRIO_INHERIT=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ax_cv_PTHREAD_PRIO_INHERIT" >&5 +$as_echo "$ax_cv_PTHREAD_PRIO_INHERIT" >&6; } + if test "x$ax_cv_PTHREAD_PRIO_INHERIT" = "xyes"; then : + +$as_echo "#define HAVE_PTHREAD_PRIO_INHERIT 1" >>confdefs.h + +fi + + LIBS="$save_LIBS" + CFLAGS="$save_CFLAGS" + + # More AIX lossage: compile with *_r variant + if test "x$GCC" != xyes; then + case $host_os in + aix*) + case "x/$CC" in #( + x*/c89|x*/c89_128|x*/c99|x*/c99_128|x*/cc|x*/cc128|x*/xlc|x*/xlc_v6|x*/xlc128|x*/xlc128_v6) : + #handle absolute path differently from PATH based program lookup + case "x$CC" in #( + x/*) : + if as_fn_executable_p ${CC}_r; then : + PTHREAD_CC="${CC}_r" +fi ;; #( + *) : + for ac_prog in ${CC}_r +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_PTHREAD_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$PTHREAD_CC"; then + ac_cv_prog_PTHREAD_CC="$PTHREAD_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_PTHREAD_CC="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +PTHREAD_CC=$ac_cv_prog_PTHREAD_CC +if test -n "$PTHREAD_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $PTHREAD_CC" >&5 +$as_echo "$PTHREAD_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$PTHREAD_CC" && break +done +test -n "$PTHREAD_CC" || PTHREAD_CC="$CC" + ;; +esac ;; #( + *) : + ;; +esac + ;; + esac + fi +fi + +test -n "$PTHREAD_CC" || PTHREAD_CC="$CC" + + + + + +# Finally, execute ACTION-IF-FOUND/ACTION-IF-NOT-FOUND: +if test x"$ax_pthread_ok" = xyes; then + + +$as_echo "#define HAVE_PTHREAD 1" >>confdefs.h + + AM_CFLAGS="-D_POSIX_THREADS $AM_CFLAGS $PTHREAD_CFLAGS" + LIBS="$LIBS $PTHREAD_LIBS" + + : +else + ax_pthread_ok=no + + ENABLED_SINGLETHREADED=yes + +fi +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + + +fi + +if test "x$ENABLED_SINGLETHREADED" = "xyes" ; then : + AM_CFLAGS="-DSINGLE_THREADED $AM_CFLAGS" +fi + + +# DTLS +# Check whether --enable-dtls was given. +if test "${enable_dtls+set}" = set; then : + enableval=$enable_dtls; ENABLED_DTLS=$enableval +else + ENABLED_DTLS=no + +fi + +if test "$ENABLED_DTLS" = "yes" +then + AM_CFLAGS="-DWOLFSSL_DTLS $AM_CFLAGS" +fi + + +# OPENSSL Extra Compatibility +# Check whether --enable-opensslextra was given. +if test "${enable_opensslextra+set}" = set; then : + enableval=$enable_opensslextra; ENABLED_OPENSSLEXTRA=$enableval +else + ENABLED_OPENSSLEXTRA=no + +fi + +if test "$ENABLED_OPENSSLEXTRA" = "yes" +then + AM_CFLAGS="-DOPENSSL_EXTRA $AM_CFLAGS" +fi + +if test "$ENABLED_OPENSSLEXTRA" = "yes" && test "$ENABLED_SMALL" = "yes" +then + as_fn_error $? "cannot enable small and opensslextra, only one or the other." "$LINENO" 5 +fi + + +# High Strength Build +# Check whether --enable-maxstrength was given. +if test "${enable_maxstrength+set}" = set; then : + enableval=$enable_maxstrength; ENABLED_MAXSTRENGTH=$enableval +else + ENABLED_MAXSTRENGTH=no +fi + + + +# IPv6 Test Apps +# Check whether --enable-ipv6 was given. +if test "${enable_ipv6+set}" = set; then : + enableval=$enable_ipv6; ENABLED_IPV6=$enableval +else + ENABLED_IPV6=no + +fi + + +if test "$ENABLED_IPV6" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DTEST_IPV6" +fi + + if test "x$ENABLED_IPV6" = "xyes"; then + BUILD_IPV6_TRUE= + BUILD_IPV6_FALSE='#' +else + BUILD_IPV6_TRUE='#' + BUILD_IPV6_FALSE= +fi + + + +# Fortress build +# Check whether --enable-fortress was given. +if test "${enable_fortress+set}" = set; then : + enableval=$enable_fortress; ENABLED_FORTRESS=$enableval +else + ENABLED_FORTRESS=no + +fi + + +if test "$ENABLED_FORTRESS" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DFORTRESS -DWOLFSSL_ALWAYS_VERIFY_CB -DOPENSSL_EXTRA -DWOLFSSL_DES_ECB -DWOLFSSL_AES_COUNTER -DWOLFSSL_AES_DIRECT -DWOLFSSL_DER_LOAD -DWOLFSSL_SHA512 -DWOLFSSL_SHA384 -DWOLFSSL_KEY_GEN" +fi + + +# ssl bump build +# Check whether --enable-bump was given. +if test "${enable_bump+set}" = set; then : + enableval=$enable_bump; ENABLED_BUMP=$enableval +else + ENABLED_BUMP=no + +fi + + +if test "$ENABLED_BUMP" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DLARGE_STATIC_BUFFERS -DWOLFSSL_CERT_GEN -DWOLFSSL_KEY_GEN -DHUGE_SESSION_CACHE -DOPENSSL_EXTRA -DFP_MAX_BITS=8192 -DWOLFSSL_DER_LOAD -DWOLFSSL_ALT_NAMES -DWOLFSSL_TEST_CERT" +fi + +ENABLED_SLOWMATH="yes" + +# lean psk build +# Check whether --enable-leanpsk was given. +if test "${enable_leanpsk+set}" = set; then : + enableval=$enable_leanpsk; ENABLED_LEANPSK=$enableval +else + ENABLED_LEANPSK=no + +fi + + +if test "$ENABLED_LEANPSK" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_LEANPSK -DHAVE_NULL_CIPHER -DSINGLE_THREADED -DNO_AES -DNO_FILESYSTEM -DNO_RABBIT -DNO_RSA -DNO_DSA -DNO_DH -DNO_CERTS -DNO_PWDBASED -DNO_DES3 -DNO_MD4 -DNO_MD5 -DNO_ERROR_STRINGS -DNO_OLD_TLS -DNO_RC4 -DNO_WRITEV -DNO_SESSION_CACHE -DNO_DEV_RANDOM -DWOLFSSL_USER_IO -DNO_SHA -DUSE_SLOW_SHA" + ENABLED_SLOWMATH="no" + ENABLED_SINGLETHREADED="yes" +fi + + if test "x$ENABLED_LEANPSK" = "xyes"; then + BUILD_LEANPSK_TRUE= + BUILD_LEANPSK_FALSE='#' +else + BUILD_LEANPSK_TRUE='#' + BUILD_LEANPSK_FALSE= +fi + + + +# big cache +# Check whether --enable-bigcache was given. +if test "${enable_bigcache+set}" = set; then : + enableval=$enable_bigcache; ENABLED_BIGCACHE=$enableval +else + ENABLED_BIGCACHE=no + +fi + + +if test "$ENABLED_BIGCACHE" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DBIG_SESSION_CACHE" +fi + + +# HUGE cache +# Check whether --enable-hugecache was given. +if test "${enable_hugecache+set}" = set; then : + enableval=$enable_hugecache; ENABLED_HUGECACHE=$enableval +else + ENABLED_HUGECACHE=no + +fi + + +if test "$ENABLED_HUGECACHE" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHUGE_SESSION_CACHE" +fi + + +# SMALL cache +# Check whether --enable-smallcache was given. +if test "${enable_smallcache+set}" = set; then : + enableval=$enable_smallcache; ENABLED_SMALLCACHE=$enableval +else + ENABLED_SMALLCACHE=no + +fi + + +if test "$ENABLED_SMALLCACHE" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DSMALL_SESSION_CACHE" +fi + + +# Persistent session cache +# Check whether --enable-savesession was given. +if test "${enable_savesession+set}" = set; then : + enableval=$enable_savesession; ENABLED_SAVESESSION=$enableval +else + ENABLED_SAVESESSION=no + +fi + + +if test "$ENABLED_SAVESESSION" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DPERSIST_SESSION_CACHE" +fi + + +# Persistent cert cache +# Check whether --enable-savecert was given. +if test "${enable_savecert+set}" = set; then : + enableval=$enable_savecert; ENABLED_SAVECERT=$enableval +else + ENABLED_SAVECERT=no + +fi + + +if test "$ENABLED_SAVECERT" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DPERSIST_CERT_CACHE" +fi + + +# Atomic User Record Layer +# Check whether --enable-atomicuser was given. +if test "${enable_atomicuser+set}" = set; then : + enableval=$enable_atomicuser; ENABLED_ATOMICUSER=$enableval +else + ENABLED_ATOMICUSER=no + +fi + + +if test "$ENABLED_ATOMICUSER" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DATOMIC_USER" +fi + + +# Public Key Callbacks +# Check whether --enable-pkcallbacks was given. +if test "${enable_pkcallbacks+set}" = set; then : + enableval=$enable_pkcallbacks; ENABLED_PKCALLBACKS=$enableval +else + ENABLED_PKCALLBACKS=no + +fi + + +if test "$ENABLED_PKCALLBACKS" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_PK_CALLBACKS" +fi + + +# SNIFFER +# Check whether --enable-sniffer was given. +if test "${enable_sniffer+set}" = set; then : + enableval=$enable_sniffer; ENABLED_SNIFFER=$enableval +else + ENABLED_SNIFFER=no + +fi + + +# sniffer does't work in maxstrength mode +if test "$ENABLED_SNIFFER" = "yes" && test "$ENABLED_MAXSTRENGTH" = "yes" +then + as_fn_error $? "cannot enable maxstrength in sniffer mode." "$LINENO" 5 +fi + +ENABLED_SNIFFTEST=no +if test "x$ENABLED_SNIFFER" = "xyes" ; then : + + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_SNIFFER -DOPENSSL_EXTRA" + for ac_header in pcap/pcap.h +do : + ac_fn_c_check_header_mongrel "$LINENO" "pcap/pcap.h" "ac_cv_header_pcap_pcap_h" "$ac_includes_default" +if test "x$ac_cv_header_pcap_pcap_h" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_PCAP_PCAP_H 1 +_ACEOF + ENABLED_SNIFFTEST=yes +else + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cannot enable sniffer test without having libpcap available." >&5 +$as_echo "$as_me: WARNING: cannot enable sniffer test without having libpcap available." >&2;} + +fi + +done + + +fi + + if test "x$ENABLED_SNIFFER" = "xyes" ; then + BUILD_SNIFFER_TRUE= + BUILD_SNIFFER_FALSE='#' +else + BUILD_SNIFFER_TRUE='#' + BUILD_SNIFFER_FALSE= +fi + + if test "x$ENABLED_SNIFFTEST" = "xyes" ; then + BUILD_SNIFFTEST_TRUE= + BUILD_SNIFFTEST_FALSE='#' +else + BUILD_SNIFFTEST_TRUE='#' + BUILD_SNIFFTEST_FALSE= +fi + + +# AES-GCM +# Check whether --enable-aesgcm was given. +if test "${enable_aesgcm+set}" = set; then : + enableval=$enable_aesgcm; ENABLED_AESGCM=$enableval +else + ENABLED_AESGCM=yes + +fi + + +# lean psk does't need gcm +if test "$ENABLED_LEANPSK" = "yes" +then + ENABLED_AESGCM=no +fi + +if test "$ENABLED_AESGCM" = "word32" +then + AM_CFLAGS="$AM_CFLAGS -DGCM_WORD32" + ENABLED_AESGCM=yes +fi + +if test "$ENABLED_AESGCM" = "small" +then + AM_CFLAGS="$AM_CFLAGS -DGCM_SMALL" + ENABLED_AESGCM=yes +fi + +if test "$ENABLED_AESGCM" = "table" +then + AM_CFLAGS="$AM_CFLAGS -DGCM_TABLE" + ENABLED_AESGCM=yes +fi + +if test "$ENABLED_AESGCM" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_AESGCM" +fi + + if test "x$ENABLED_AESGCM" = "xyes"; then + BUILD_AESGCM_TRUE= + BUILD_AESGCM_FALSE='#' +else + BUILD_AESGCM_TRUE='#' + BUILD_AESGCM_FALSE= +fi + + + +# AES-CCM +# Check whether --enable-aesccm was given. +if test "${enable_aesccm+set}" = set; then : + enableval=$enable_aesccm; ENABLED_AESCCM=$enableval +else + ENABLED_AESCCM=no + +fi + + +if test "$ENABLED_AESCCM" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_AESCCM" +fi + + if test "x$ENABLED_AESCCM" = "xyes"; then + BUILD_AESCCM_TRUE= + BUILD_AESCCM_FALSE='#' +else + BUILD_AESCCM_TRUE='#' + BUILD_AESCCM_FALSE= +fi + + + +# AES-NI +# Check whether --enable-aesni was given. +if test "${enable_aesni+set}" = set; then : + enableval=$enable_aesni; ENABLED_AESNI=$enableval +else + ENABLED_AESNI=no + +fi + + +# INTEL ASM +# Check whether --enable-intelasm was given. +if test "${enable_intelasm+set}" = set; then : + enableval=$enable_intelasm; ENABLED_INTELASM=$enableval +else + ENABLED_INTELASM=no + +fi + + +if test "$ENABLED_AESNI" = "yes" || test "$ENABLED_INTELASM" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_AESNI" + if test "$GCC" = "yes" + then + # GCC needs these flags, icc doesn't + # opt levels greater than 2 may cause problems on systems w/o aesni + if test "$CC" != "icc" + then + AM_CFLAGS="$AM_CFLAGS -maes -msse4" + fi + fi +fi + +if test "$ENABLED_INTELASM" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_INTEL_RDGEN -DUSE_INTEL_SPEEDUP" + ENABLED_AESNI=yes +fi + + if test "x$ENABLED_AESNI" = "xyes"; then + BUILD_AESNI_TRUE= + BUILD_AESNI_FALSE='#' +else + BUILD_AESNI_TRUE='#' + BUILD_AESNI_FALSE= +fi + + + +# Camellia +# Check whether --enable-camellia was given. +if test "${enable_camellia+set}" = set; then : + enableval=$enable_camellia; ENABLED_CAMELLIA=$enableval +else + ENABLED_CAMELLIA=no + +fi + + +if test "$ENABLED_CAMELLIA" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_CAMELLIA" +fi + + if test "x$ENABLED_CAMELLIA" = "xyes"; then + BUILD_CAMELLIA_TRUE= + BUILD_CAMELLIA_FALSE='#' +else + BUILD_CAMELLIA_TRUE='#' + BUILD_CAMELLIA_FALSE= +fi + + + +# MD2 +# Check whether --enable-md2 was given. +if test "${enable_md2+set}" = set; then : + enableval=$enable_md2; ENABLED_MD2=$enableval +else + ENABLED_MD2=no + +fi + + +if test "$ENABLED_BUMP" = "yes" +then + ENABLED_MD2="yes" +fi + +if test "$ENABLED_MD2" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_MD2" +fi + + if test "x$ENABLED_MD2" = "xyes"; then + BUILD_MD2_TRUE= + BUILD_MD2_FALSE='#' +else + BUILD_MD2_TRUE='#' + BUILD_MD2_FALSE= +fi + + + +# NULL CIPHER +# Check whether --enable-nullcipher was given. +if test "${enable_nullcipher+set}" = set; then : + enableval=$enable_nullcipher; ENABLED_NULL_CIPHER=$enableval +else + ENABLED_NULL_CIPHER=no + +fi + + +if test "$ENABLED_NULL_CIPHER" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_NULL_CIPHER" +fi + +# RIPEMD +# Check whether --enable-ripemd was given. +if test "${enable_ripemd+set}" = set; then : + enableval=$enable_ripemd; ENABLED_RIPEMD=$enableval +else + ENABLED_RIPEMD=no + +fi + + +if test "$ENABLED_RIPEMD" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_RIPEMD" +fi + + if test "x$ENABLED_RIPEMD" = "xyes"; then + BUILD_RIPEMD_TRUE= + BUILD_RIPEMD_FALSE='#' +else + BUILD_RIPEMD_TRUE='#' + BUILD_RIPEMD_FALSE= +fi + + + +# BLAKE2 +# Check whether --enable-blake2 was given. +if test "${enable_blake2+set}" = set; then : + enableval=$enable_blake2; ENABLED_BLAKE2=$enableval +else + ENABLED_BLAKE2=no + +fi + + +if test "$ENABLED_BLAKE2" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_BLAKE2" +fi + + if test "x$ENABLED_BLAKE2" = "xyes"; then + BUILD_BLAKE2_TRUE= + BUILD_BLAKE2_FALSE='#' +else + BUILD_BLAKE2_TRUE='#' + BUILD_BLAKE2_FALSE= +fi + + + +# set sha512 default +SHA512_DEFAULT=no +if test "$host_cpu" = "x86_64" +then +SHA512_DEFAULT=yes +fi + +# SHA512 +# Check whether --enable-sha512 was given. +if test "${enable_sha512+set}" = set; then : + enableval=$enable_sha512; ENABLED_SHA512=$enableval +else + ENABLED_SHA512=$SHA512_DEFAULT + +fi + + +# lean psk does't need sha512 +if test "$ENABLED_LEANPSK" = "yes" +then + ENABLED_SHA512=no +fi + +if test "$ENABLED_SHA512" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_SHA512 -DWOLFSSL_SHA384" +fi + +if test "$ENABLED_FORTRESS" = "yes" +then + ENABLED_SHA512="yes" +fi + + + if test "x$ENABLED_SHA512" = "xyes"; then + BUILD_SHA512_TRUE= + BUILD_SHA512_FALSE='#' +else + BUILD_SHA512_TRUE='#' + BUILD_SHA512_FALSE= +fi + + + +# SESSION CERTS +# Check whether --enable-sessioncerts was given. +if test "${enable_sessioncerts+set}" = set; then : + enableval=$enable_sessioncerts; ENABLED_SESSIONCERTS=$enableval +else + ENABLED_SESSIONCERTS=no + +fi + + +if test "$ENABLED_SESSIONCERTS" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DSESSION_CERTS" +fi + + +# KEY GENERATION +# Check whether --enable-keygen was given. +if test "${enable_keygen+set}" = set; then : + enableval=$enable_keygen; ENABLED_KEYGEN=$enableval +else + ENABLED_KEYGEN=no + +fi + + +if test "$ENABLED_KEYGEN" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_KEY_GEN" +fi + + +# CERT GENERATION +# Check whether --enable-certgen was given. +if test "${enable_certgen+set}" = set; then : + enableval=$enable_certgen; ENABLED_CERTGEN=$enableval +else + ENABLED_CERTGEN=no + +fi + + +if test "$ENABLED_CERTGEN" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_CERT_GEN" +fi + + +# CERT REQUEST GENERATION +# Check whether --enable-certreq was given. +if test "${enable_certreq+set}" = set; then : + enableval=$enable_certreq; ENABLED_CERTREQ=$enableval +else + ENABLED_CERTREQ=no + +fi + + +if test "$ENABLED_CERTREQ" = "yes" +then + if test "$ENABLED_CERTGEN" = "no" + then + as_fn_error $? "cannot enable certreq without enabling certgen." "$LINENO" 5 + fi + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_CERT_REQ" +fi + + +# SEP +# Check whether --enable-sep was given. +if test "${enable_sep+set}" = set; then : + enableval=$enable_sep; ENABLED_SEP=$enableval +else + ENABLED_SEP=no + +fi + +if test "$ENABLED_SEP" = "yes" +then + AM_CFLAGS="-DWOLFSSL_SEP -DKEEP_PEER_CERT $AM_CFLAGS" +fi + + +# HKDF +# Check whether --enable-hkdf was given. +if test "${enable_hkdf+set}" = set; then : + enableval=$enable_hkdf; ENABLED_HKDF=$enableval +else + ENABLED_HKDF=no + +fi + +if test "$ENABLED_HKDF" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_HKDF" +fi + + +# DSA +# Check whether --enable-dsa was given. +if test "${enable_dsa+set}" = set; then : + enableval=$enable_dsa; ENABLED_DSA=$enableval +else + ENABLED_DSA=no + +fi + + +if test "$ENABLED_DSA" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_DSA" +fi + + if test "x$ENABLED_DSA" = "xyes"; then + BUILD_DSA_TRUE= + BUILD_DSA_FALSE='#' +else + BUILD_DSA_TRUE='#' + BUILD_DSA_FALSE= +fi + + + +# set ecc default +ECC_DEFAULT=no + +if test "$host_cpu" = "x86_64" +then +ECC_DEFAULT=yes +fi + +# ECC +# Check whether --enable-ecc was given. +if test "${enable_ecc+set}" = set; then : + enableval=$enable_ecc; ENABLED_ECC=$enableval +else + ENABLED_ECC=$ECC_DEFAULT + +fi + + +# lean psk does't need ecc +if test "$ENABLED_LEANPSK" = "yes" +then + ENABLED_ECC=no +fi + +if test "$ENABLED_ECC" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_ECC -DTFM_ECC256 -DECC_SHAMIR" +fi + + if test "x$ENABLED_ECC" = "xyes"; then + BUILD_ECC_TRUE= + BUILD_ECC_FALSE='#' +else + BUILD_ECC_TRUE='#' + BUILD_ECC_FALSE= +fi + + + +if test "$ENABLED_ECC" = "yes" && test "$ENABLED_SMALL" = "yes" +then + as_fn_error $? "cannot enable ecc and small, ecc requires TLS which small turns off." "$LINENO" 5 +fi + + +# for using memory optimization setting on both curve25519 and ed25519 +ENABLED_CURVED25519_SMALL=no + +# CURVE25519 +# Check whether --enable-curve25519 was given. +if test "${enable_curve25519+set}" = set; then : + enableval=$enable_curve25519; ENABLED_CURVE25519=$enableval +else + ENABLED_CURVE25519=no + +fi + + + +if test "$ENABLED_CURVE25519" = "small" +then + AM_CFLAGS="$AM_CFLAGS -DCURVED25519_SMALL" + ENABLED_CURVED25519_SMALL=yes + ENABLED_CURVE25519=yes +fi + +if test "$ENABLED_CURVE25519" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_CURVE25519" + ENABLED_FEMATH=yes +fi + + + if test "x$ENABLED_CURVE25519" = "xyes"; then + BUILD_CURVE25519_TRUE= + BUILD_CURVE25519_FALSE='#' +else + BUILD_CURVE25519_TRUE='#' + BUILD_CURVE25519_FALSE= +fi + + + +# ED25519 +# Check whether --enable-ed25519 was given. +if test "${enable_ed25519+set}" = set; then : + enableval=$enable_ed25519; ENABLED_ED25519=$enableval +else + ENABLED_ED25519=no + +fi + + + +if test "$ENABLED_ED25519" = "small" +then + AM_CFLAGS="$AM_CFLAGS -DCURVED25519_SMALL" + ENABLED_CURVED25519_SMALL=yes + ENABLED_ED25519=yes +fi + +if test "$ENABLED_ED25519" = "yes" +then + if test "$ENABLED_SHA512" = "no" + then + as_fn_error $? "cannot enable ed25519 without enabling sha512." "$LINENO" 5 + fi + ENABLED_FEMATH=yes + ENABLED_GEMATH=yes + AM_CFLAGS="$AM_CFLAGS -DHAVE_ED25519" +fi + + if test "x$ENABLED_ED25519" = "xyes"; then + BUILD_ED25519_TRUE= + BUILD_ED25519_FALSE='#' +else + BUILD_ED25519_TRUE='#' + BUILD_ED25519_FALSE= +fi + + if test "x$ENABLED_CURVED25519_SMALL" = "xyes"; then + BUILD_CURVED25519_SMALL_TRUE= + BUILD_CURVED25519_SMALL_FALSE='#' +else + BUILD_CURVED25519_SMALL_TRUE='#' + BUILD_CURVED25519_SMALL_FALSE= +fi + + if test "x$ENABLED_FEMATH" = "xyes"; then + BUILD_FEMATH_TRUE= + BUILD_FEMATH_FALSE='#' +else + BUILD_FEMATH_TRUE='#' + BUILD_FEMATH_FALSE= +fi + + if test "x$ENABLED_GEMATH" = "xyes"; then + BUILD_GEMATH_TRUE= + BUILD_GEMATH_FALSE='#' +else + BUILD_GEMATH_TRUE='#' + BUILD_GEMATH_FALSE= +fi + + +# FP ECC, Fixed Point cache ECC +# Check whether --enable-fpecc was given. +if test "${enable_fpecc+set}" = set; then : + enableval=$enable_fpecc; ENABLED_FPECC=$enableval +else + ENABLED_FPECC=no + +fi + + +if test "$ENABLED_FPECC" = "yes" +then + if test "$ENABLED_ECC" = "no" + then + as_fn_error $? "cannot enable fpecc without enabling ecc." "$LINENO" 5 + fi + AM_CFLAGS="$AM_CFLAGS -DFP_ECC" +fi + + +# ECC encrypt +# Check whether --enable-eccencrypt was given. +if test "${enable_eccencrypt+set}" = set; then : + enableval=$enable_eccencrypt; ENABLED_ECC_ENCRYPT=$enableval +else + ENABLED_ECC_ENCRYPT=no + +fi + + +if test "$ENABLED_ECC_ENCRYPT" = "yes" +then + if test "$ENABLED_ECC" = "no" + then + as_fn_error $? "cannot enable eccencrypt without enabling ecc." "$LINENO" 5 + fi + if test "$ENABLED_HKDF" = "no" + then + as_fn_error $? "cannot enable eccencrypt without enabling hkdf." "$LINENO" 5 + fi + AM_CFLAGS="$AM_CFLAGS -DHAVE_ECC_ENCRYPT" +fi + + +# PSK +# Check whether --enable-psk was given. +if test "${enable_psk+set}" = set; then : + enableval=$enable_psk; ENABLED_PSK=$enableval +else + ENABLED_PSK=no + +fi + + +if test "$ENABLED_PSK" = "no" && test "$ENABLED_LEANPSK" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_PSK" +fi + +if test "$ENABLED_PSK" = "no" && test "$ENABLED_LEANPSK" = "yes" +then + ENABLED_PSK=yes +fi + + +# ERROR STRINGS +# Check whether --enable-errorstrings was given. +if test "${enable_errorstrings+set}" = set; then : + enableval=$enable_errorstrings; ENABLED_ERROR_STRINGS=$enableval +else + ENABLED_ERROR_STRINGS=yes + +fi + + +if test "$ENABLED_ERROR_STRINGS" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_ERROR_STRINGS" +else + # turn off error strings if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_ERROR_STRINGS" + ENABLED_ERROR_STRINGS=no + fi +fi + + +# OLD TLS +# Check whether --enable-oldtls was given. +if test "${enable_oldtls+set}" = set; then : + enableval=$enable_oldtls; ENABLED_OLD_TLS=$enableval +else + ENABLED_OLD_TLS=yes + +fi + + +if test "$ENABLED_OLD_TLS" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_OLD_TLS" +else + # turn off old if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_OLD_TLS" + ENABLED_OLD_TLS=no + fi +fi + + +# STACK SIZE info for examples +# Check whether --enable-stacksize was given. +if test "${enable_stacksize+set}" = set; then : + enableval=$enable_stacksize; ENABLED_STACKSIZE=$enableval +else + ENABLED_STACKSIZE=no + +fi + + +if test "$ENABLED_STACKSIZE" = "yes" +then + ac_fn_c_check_func "$LINENO" "posix_memalign" "ac_cv_func_posix_memalign" +if test "x$ac_cv_func_posix_memalign" = xyes; then : + +else + as_fn_error $? "stacksize needs posix_memalign" "$LINENO" 5 +fi + + ac_fn_c_check_func "$LINENO" "pthread_attr_setstack" "ac_cv_func_pthread_attr_setstack" +if test "x$ac_cv_func_pthread_attr_setstack" = xyes; then : + +else + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for pthread_attr_setstack in -lpthread" >&5 +$as_echo_n "checking for pthread_attr_setstack in -lpthread... " >&6; } +if ${ac_cv_lib_pthread_pthread_attr_setstack+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lpthread $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char pthread_attr_setstack (); +int +main () +{ +return pthread_attr_setstack (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_pthread_pthread_attr_setstack=yes +else + ac_cv_lib_pthread_pthread_attr_setstack=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_pthread_pthread_attr_setstack" >&5 +$as_echo "$ac_cv_lib_pthread_pthread_attr_setstack" >&6; } +if test "x$ac_cv_lib_pthread_pthread_attr_setstack" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_LIBPTHREAD 1 +_ACEOF + + LIBS="-lpthread $LIBS" + +fi + +fi + + AM_CFLAGS="$AM_CFLAGS -DHAVE_STACK_SIZE -DWOLFSSL_LOW_MEMORY" +fi + + +# MEMORY +# Check whether --enable-memory was given. +if test "${enable_memory+set}" = set; then : + enableval=$enable_memory; ENABLED_MEMORY=$enableval +else + ENABLED_MEMORY=yes + +fi + + +if test "$ENABLED_MEMORY" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_WOLFSSL_MEMORY" +else + # turn off memory cb if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + # but don't turn on NO_WOLFSSL_MEMORY because using own + ENABLED_MEMORY=no + fi +fi + + if test "x$ENABLED_MEMORY" = "xyes"; then + BUILD_MEMORY_TRUE= + BUILD_MEMORY_FALSE='#' +else + BUILD_MEMORY_TRUE='#' + BUILD_MEMORY_FALSE= +fi + + + +# RSA +# Check whether --enable-rsa was given. +if test "${enable_rsa+set}" = set; then : + enableval=$enable_rsa; ENABLED_RSA=$enableval +else + ENABLED_RSA=yes + +fi + + +if test "$ENABLED_RSA" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_RSA" +else + # turn off RSA if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_RSA" + ENABLED_RSA=no + fi +fi + + if test "x$ENABLED_RSA" = "xyes"; then + BUILD_RSA_TRUE= + BUILD_RSA_FALSE='#' +else + BUILD_RSA_TRUE='#' + BUILD_RSA_FALSE= +fi + + + +# DH +# Check whether --enable-dh was given. +if test "${enable_dh+set}" = set; then : + enableval=$enable_dh; ENABLED_DH=$enableval +else + ENABLED_DH=yes + +fi + + +if test "$ENABLED_DH" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_DH" +else + # turn off DH if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_DH" + ENABLED_DH=no + fi +fi + + if test "x$ENABLED_DH" = "xyes"; then + BUILD_DH_TRUE= + BUILD_DH_FALSE='#' +else + BUILD_DH_TRUE='#' + BUILD_DH_FALSE= +fi + + + +# Anonymous +# Check whether --enable-anon was given. +if test "${enable_anon+set}" = set; then : + enableval=$enable_anon; ENABLED_ANON=$enableval +else + ENABLED_ANON=no + +fi + + + +if test "x$ENABLED_ANON" = "xyes" +then + if test "x$ENABLED_DH" != "xyes" + then + as_fn_error $? "Anonymous suite requires DH." "$LINENO" 5 + fi + AM_CFLAGS="$AM_CFLAGS -DHAVE_ANON" +fi + + +# ASN +# turn off asn, which means no certs, no rsa, no dsa, no ecc, +# and no big int (unless dh is on) +# Check whether --enable-asn was given. +if test "${enable_asn+set}" = set; then : + enableval=$enable_asn; ENABLED_ASN=$enableval +else + ENABLED_ASN=yes + +fi + + +if test "$ENABLED_ASN" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_ASN -DNO_CERTS" + if test "$ENABLED_DH" = "no" + then + # DH needs bigint + AM_CFLAGS="$AM_CFLAGS -DNO_BIG_INT" + fi +else + # turn off ASN if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_ASN -DNO_CERTS -DNO_BIG_INT" + ENABLED_ASN=no + fi +fi + +if test "$ENABLED_RSA" = "yes" && test "$ENABLED_ASN" = "no" +then + as_fn_error $? "please disable rsa if disabling asn." "$LINENO" 5 +fi + +if test "$ENABLED_DSA" = "yes" && test "$ENABLED_ASN" = "no" +then + as_fn_error $? "please disable dsa if disabling asn." "$LINENO" 5 +fi + +if test "$ENABLED_ECC" = "yes" && test "$ENABLED_ASN" = "no" +then + as_fn_error $? "please disable ecc if disabling asn." "$LINENO" 5 +fi + +if test "$ENABLED_PSK" = "no" && test "$ENABLED_ASN" = "no" +then + as_fn_error $? "please enable psk if disabling asn." "$LINENO" 5 +fi + +# DH needs bigint +if test "$ENABLED_ASN" = "no" && test "$ENABLED_DH" = "no" +then + ENABLED_FASTMATH=no + ENABLED_SLOWMATH=no +fi + + if test "x$ENABLED_ASN" = "xyes"; then + BUILD_ASN_TRUE= + BUILD_ASN_FALSE='#' +else + BUILD_ASN_TRUE='#' + BUILD_ASN_FALSE= +fi + + + +# AES +# Check whether --enable-aes was given. +if test "${enable_aes+set}" = set; then : + enableval=$enable_aes; ENABLED_AES=$enableval +else + ENABLED_AES=yes + +fi + + +if test "$ENABLED_AES" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_AES" + if test "$ENABLED_AESGCM" = "yes" + then + as_fn_error $? "AESGCM requires AES." "$LINENO" 5 + fi + if test "$ENABLED_AESCCM" = "yes" + then + as_fn_error $? "AESCCM requires AES." "$LINENO" 5 + fi +else + # turn off AES if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_AES" + ENABLED_AES=no + fi +fi + + if test "x$ENABLED_AES" = "xyes"; then + BUILD_AES_TRUE= + BUILD_AES_FALSE='#' +else + BUILD_AES_TRUE='#' + BUILD_AES_FALSE= +fi + + + +# CODING +# Check whether --enable-coding was given. +if test "${enable_coding+set}" = set; then : + enableval=$enable_coding; ENABLED_CODING=$enableval +else + ENABLED_CODING=yes + +fi + + +if test "$ENABLED_CODING" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_CODING" +else + # turn off CODING if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_CODING" + ENABLED_CODING=no + fi +fi + + if test "x$ENABLED_CODING" = "xyes"; then + BUILD_CODING_TRUE= + BUILD_CODING_FALSE='#' +else + BUILD_CODING_TRUE='#' + BUILD_CODING_FALSE= +fi + + + +# DES3 +# Check whether --enable-des3 was given. +if test "${enable_des3+set}" = set; then : + enableval=$enable_des3; ENABLED_DES3=$enableval +else + ENABLED_DES3=yes + +fi + + +if test "$ENABLED_DES3" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_DES3" +else + # turn off DES3 if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_DES3" + ENABLED_DES3=no + fi +fi + + if test "x$ENABLED_DES3" = "xyes"; then + BUILD_DES3_TRUE= + BUILD_DES3_FALSE='#' +else + BUILD_DES3_TRUE='#' + BUILD_DES3_FALSE= +fi + + + +# ARC4 +# Check whether --enable-arc4 was given. +if test "${enable_arc4+set}" = set; then : + enableval=$enable_arc4; ENABLED_ARC4=$enableval +else + ENABLED_ARC4=no + +fi + + +if test "$ENABLED_ARC4" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_RC4" +else + # turn off ARC4 if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_RC4" + ENABLED_ARC4=no + fi +fi + + if test "x$ENABLED_ARC4" = "xyes"; then + BUILD_RC4_TRUE= + BUILD_RC4_FALSE='#' +else + BUILD_RC4_TRUE='#' + BUILD_RC4_FALSE= +fi + + + +# MD5 +# Check whether --enable-md5 was given. +if test "${enable_md5+set}" = set; then : + enableval=$enable_md5; ENABLED_MD5=$enableval +else + ENABLED_MD5=yes + +fi + + +if test "$ENABLED_MD5" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_MD5 -DNO_OLD_TLS" +else + # turn off MD5 if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_MD5 -DNO_OLD_TLS" + ENABLED_MD5=no + fi +fi + + if test "x$ENABLED_MD5" = "xyes"; then + BUILD_MD5_TRUE= + BUILD_MD5_FALSE='#' +else + BUILD_MD5_TRUE='#' + BUILD_MD5_FALSE= +fi + + + +# SHA +# Check whether --enable-sha was given. +if test "${enable_sha+set}" = set; then : + enableval=$enable_sha; ENABLED_SHA=$enableval +else + ENABLED_SHA=yes + +fi + + +if test "$ENABLED_SHA" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_SHA -DNO_OLD_TLS" +else + # turn off SHA if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_SHA -DNO_OLD_TLS" + ENABLED_SHA=no + fi +fi + + if test "x$ENABLED_SHA" = "xyes"; then + BUILD_SHA_TRUE= + BUILD_SHA_FALSE='#' +else + BUILD_SHA_TRUE='#' + BUILD_SHA_FALSE= +fi + + + +# MD4 +# Check whether --enable-md4 was given. +if test "${enable_md4+set}" = set; then : + enableval=$enable_md4; ENABLED_MD4=$enableval +else + ENABLED_MD4=no + +fi + + +if test "$ENABLED_MD4" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_MD4" +fi + + if test "x$ENABLED_MD4" = "xyes"; then + BUILD_MD4_TRUE= + BUILD_MD4_FALSE='#' +else + BUILD_MD4_TRUE='#' + BUILD_MD4_FALSE= +fi + + + +# Web Server Build +# Check whether --enable-webserver was given. +if test "${enable_webserver+set}" = set; then : + enableval=$enable_webserver; ENABLED_WEBSERVER=$enableval +else + ENABLED_WEBSERVER=no + +fi + + +if test "$ENABLED_WEBSERVER" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_WEBSERVER" +fi + + + +# HC128 +# Check whether --enable-hc128 was given. +if test "${enable_hc128+set}" = set; then : + enableval=$enable_hc128; ENABLED_HC128=$enableval +else + ENABLED_HC128=no + +fi + + +if test "$ENABLED_HC128" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_HC128" +else + AM_CFLAGS="$AM_CFLAGS -DHAVE_HC128" +fi + + if test "x$ENABLED_HC128" = "xyes"; then + BUILD_HC128_TRUE= + BUILD_HC128_FALSE='#' +else + BUILD_HC128_TRUE='#' + BUILD_HC128_FALSE= +fi + + + +# RABBIT +# Check whether --enable-rabbit was given. +if test "${enable_rabbit+set}" = set; then : + enableval=$enable_rabbit; ENABLED_RABBIT=$enableval +else + ENABLED_RABBIT=no + +fi + + +if test "$ENABLED_RABBIT" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_RABBIT" +else + AM_CFLAGS="$AM_CFLAGS -DHAVE_RABBIT" +fi + + if test "x$ENABLED_RABBIT" = "xyes"; then + BUILD_RABBIT_TRUE= + BUILD_RABBIT_FALSE='#' +else + BUILD_RABBIT_TRUE='#' + BUILD_RABBIT_FALSE= +fi + + + +# FIPS +# Check whether --enable-fips was given. +if test "${enable_fips+set}" = set; then : + enableval=$enable_fips; ENABLED_FIPS=$enableval +else + ENABLED_FIPS=no + +fi + + +if test "x$ENABLED_FIPS" = "xyes" +then + # requires thread local storage + if test "$thread_ls_on" = "no" + then + as_fn_error $? "FIPS requires Thread Local Storage" "$LINENO" 5 + fi + # requires SHA512 + if test "x$ENABLED_SHA512" = "xno" + then + ENABLED_SHA512="yes" + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_SHA512 -DWOLFSSL_SHA384" + if test "x$ENABLED_SHA512" = "xyes"; then + BUILD_SHA512_TRUE= + BUILD_SHA512_FALSE='#' +else + BUILD_SHA512_TRUE='#' + BUILD_SHA512_FALSE= +fi + + fi + # requires AESGCM + if test "x$ENABLED_AESGCM" != "xyes" + then + ENABLED_AESGCM="yes" + AM_CFLAGS="$AM_CFLAGS -DHAVE_AESGCM" + if test "x$ENABLED_SHA512" = "xyes"; then + BUILD_SHA512_TRUE= + BUILD_SHA512_FALSE='#' +else + BUILD_SHA512_TRUE='#' + BUILD_SHA512_FALSE= +fi + + fi + AM_CFLAGS="$AM_CFLAGS -DHAVE_FIPS" +fi + + if test "x$ENABLED_FIPS" = "xyes"; then + BUILD_FIPS_TRUE= + BUILD_FIPS_FALSE='#' +else + BUILD_FIPS_TRUE='#' + BUILD_FIPS_FALSE= +fi + + + +# set POLY1305 default +POLY1305_DEFAULT=yes + +if test "x$ENABLED_FIPS" = "xyes" +then +POLY1305_DEFAULT=no +fi + +# POLY1305 +# Check whether --enable-poly1305 was given. +if test "${enable_poly1305+set}" = set; then : + enableval=$enable_poly1305; ENABLED_POLY1305=$enableval +else + ENABLED_POLY1305=$POLY1305_DEFAULT + +fi + + +# lean psk does't need poly1305 +if test "$ENABLED_LEANPSK" = "yes" +then + ENABLED_POLY1305=no +fi + +if test "$ENABLED_POLY1305" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_POLY1305 -DHAVE_ONE_TIME_AUTH" +fi + + if test "x$ENABLED_POLY1305" = "xyes"; then + BUILD_POLY1305_TRUE= + BUILD_POLY1305_FALSE='#' +else + BUILD_POLY1305_TRUE='#' + BUILD_POLY1305_FALSE= +fi + + + +# set CHACHA default +CHACHA_DEFAULT=yes + +if test "x$ENABLED_FIPS" = "xyes" +then +CHACHA_DEFAULT=no +fi + +# CHACHA +# Check whether --enable-chacha was given. +if test "${enable_chacha+set}" = set; then : + enableval=$enable_chacha; ENABLED_CHACHA=$enableval +else + ENABLED_CHACHA=$CHACHA_DEFAULT + +fi + + +# lean psk does't need chacha +if test "$ENABLED_LEANPSK" = "yes" +then + ENABLED_CHACHA=no +fi + +if test "$ENABLED_CHACHA" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_CHACHA" +fi + + if test "x$ENABLED_CHACHA" = "xyes"; then + BUILD_CHACHA_TRUE= + BUILD_CHACHA_FALSE='#' +else + BUILD_CHACHA_TRUE='#' + BUILD_CHACHA_FALSE= +fi + + + +# Hash DRBG +# Check whether --enable-hashdrbg was given. +if test "${enable_hashdrbg+set}" = set; then : + enableval=$enable_hashdrbg; ENABLED_HASHDRBG=$enableval +else + ENABLED_HASHDRBG=yes + +fi + + +if test "x$ENABLED_HASHDRBG" = "xyes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_HASHDRBG" +else + # turn on Hash DRBG if FIPS is on or ARC4 is off + if test "x$ENABLED_FIPS" = "xyes" || test "x$ENABLED_ARC4" = "xno" + then + AM_CFLAGS="$AM_CFLAGS -DHAVE_HASHDRBG" + ENABLED_HASHDRBG=yes + fi +fi + + +# Filesystem Build +# Check whether --enable-filesystem was given. +if test "${enable_filesystem+set}" = set; then : + enableval=$enable_filesystem; ENABLED_FILESYSTEM=$enableval +else + ENABLED_FILESYSTEM=yes + +fi + + +if test "$ENABLED_FILESYSTEM" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_FILESYSTEM" +else + # turn off filesystem if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_FILESYSTEM" + ENABLED_FILESYSTEM=no + fi +fi + + +# inline Build +# Check whether --enable-inline was given. +if test "${enable_inline+set}" = set; then : + enableval=$enable_inline; ENABLED_INLINE=$enableval +else + ENABLED_INLINE=yes + +fi + + +if test "$ENABLED_INLINE" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_INLINE" +fi + + if test "x$ENABLED_INLINE" = "xyes"; then + BUILD_INLINE_TRUE= + BUILD_INLINE_FALSE='#' +else + BUILD_INLINE_TRUE='#' + BUILD_INLINE_FALSE= +fi + + + +# OCSP +# Check whether --enable-ocsp was given. +if test "${enable_ocsp+set}" = set; then : + enableval=$enable_ocsp; ENABLED_OCSP=$enableval +else + ENABLED_OCSP=no +fi + + +if test "$ENABLED_OCSP" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_OCSP" +fi + + if test "x$ENABLED_OCSP" = "xyes"; then + BUILD_OCSP_TRUE= + BUILD_OCSP_FALSE='#' +else + BUILD_OCSP_TRUE='#' + BUILD_OCSP_FALSE= +fi + + + +if test "$ENABLED_OCSP" = "yes" +then + # check openssl command tool for testing ocsp + # Extract the first word of "openssl", so it can be a program name with args. +set dummy openssl; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_HAVE_OPENSSL_CMD+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$HAVE_OPENSSL_CMD"; then + ac_cv_prog_HAVE_OPENSSL_CMD="$HAVE_OPENSSL_CMD" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_HAVE_OPENSSL_CMD="yes" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + + test -z "$ac_cv_prog_HAVE_OPENSSL_CMD" && ac_cv_prog_HAVE_OPENSSL_CMD="no" +fi +fi +HAVE_OPENSSL_CMD=$ac_cv_prog_HAVE_OPENSSL_CMD +if test -n "$HAVE_OPENSSL_CMD"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $HAVE_OPENSSL_CMD" >&5 +$as_echo "$HAVE_OPENSSL_CMD" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + + if test "$HAVE_OPENSSL_CMD" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DHAVE_OPENSSL_CMD" + else + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: openssl command line tool not available for testing ocsp" >&5 +$as_echo "$as_me: WARNING: openssl command line tool not available for testing ocsp" >&2;} + fi +fi + + +# CRL +# Check whether --enable-crl was given. +if test "${enable_crl+set}" = set; then : + enableval=$enable_crl; ENABLED_CRL=$enableval +else + ENABLED_CRL=no +fi + + +if test "$ENABLED_CRL" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_CRL" +fi + + if test "x$ENABLED_CRL" = "xyes"; then + BUILD_CRL_TRUE= + BUILD_CRL_FALSE='#' +else + BUILD_CRL_TRUE='#' + BUILD_CRL_FALSE= +fi + + + +# CRL Monitor +# Check whether --enable-crl-monitor was given. +if test "${enable_crl_monitor+set}" = set; then : + enableval=$enable_crl_monitor; ENABLED_CRL_MONITOR=$enableval +else + ENABLED_CRL_MONITOR=no +fi + + +if test "$ENABLED_CRL_MONITOR" = "yes" +then + case $host_os in + *linux* | *darwin* | *freebsd*) + AM_CFLAGS="$AM_CFLAGS -DHAVE_CRL_MONITOR" ;; + *) + as_fn_error $? "crl monitor only allowed on linux, OS X, or freebsd" "$LINENO" 5 ;; + esac +fi + + if test "x$ENABLED_CRL_MONITOR" = "xyes"; then + BUILD_CRL_MONITOR_TRUE= + BUILD_CRL_MONITOR_FALSE='#' +else + BUILD_CRL_MONITOR_TRUE='#' + BUILD_CRL_MONITOR_FALSE= +fi + + + +# NTRU +ENABLED_NTRU="no" +tryntrudir="" + +# Check whether --with-ntru was given. +if test "${with_ntru+set}" = set; then : + withval=$with_ntru; + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for NTRU" >&5 +$as_echo_n "checking for NTRU... " >&6; } + CPPFLAGS="$CPPFLAGS -DHAVE_NTRU" + LIBS="$LIBS -lNTRUEncrypt" + + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +int +main () +{ + ntru_crypto_drbg_instantiate(0, 0, 0, 0, 0); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ntru_linked=yes +else + ntru_linked=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + + if test "x$ntru_linked" == "xno" ; then + if test "x$withval" != "xno" ; then + tryntrudir=$withval + fi + if test "x$withval" == "xyes" ; then + tryntrudir="/usr" + fi + + LDFLAGS="$AM_LDFLAGS -L$tryntrudir/lib" + CPPFLAGS="$CPPFLAGS -I$tryntrudir/include" + + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +int +main () +{ + ntru_crypto_drbg_instantiate(0, 0, 0, 0, 0); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ntru_linked=yes +else + ntru_linked=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + + if test "x$ntru_linked" == "xno" ; then + as_fn_error $? "NTRU isn't found. + If it's already installed, specify its path using --with-ntru=/dir/" "$LINENO" 5 + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + AM_LDFLAGS="$AM_LDFLAGS -L$tryntrudir/lib" + else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + fi + + AM_CFLAGS="$AM_CFLAGS -DHAVE_NTRU" + ENABLED_NTRU="yes" + + +fi + + + if test "x$ENABLED_NTRU" = "xyes"; then + BUILD_NTRU_TRUE= + BUILD_NTRU_FALSE='#' +else + BUILD_NTRU_TRUE='#' + BUILD_NTRU_FALSE= +fi + + +if test "$ENABLED_NTRU" = "yes" && test "$ENABLED_SMALL" = "yes" +then + as_fn_error $? "cannot enable ntru and small, ntru requires TLS which small turns off." "$LINENO" 5 +fi + +# SNI +# Check whether --enable-sni was given. +if test "${enable_sni+set}" = set; then : + enableval=$enable_sni; ENABLED_SNI=$enableval +else + ENABLED_SNI=no + +fi + + +if test "x$ENABLED_SNI" = "xyes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_TLS_EXTENSIONS -DHAVE_SNI" +fi + +# Maximum Fragment Length +# Check whether --enable-maxfragment was given. +if test "${enable_maxfragment+set}" = set; then : + enableval=$enable_maxfragment; ENABLED_MAX_FRAGMENT=$enableval +else + ENABLED_MAX_FRAGMENT=no + +fi + + +if test "x$ENABLED_MAX_FRAGMENT" = "xyes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_TLS_EXTENSIONS -DHAVE_MAX_FRAGMENT" +fi + +# Truncated HMAC +# Check whether --enable-truncatedhmac was given. +if test "${enable_truncatedhmac+set}" = set; then : + enableval=$enable_truncatedhmac; ENABLED_TRUNCATED_HMAC=$enableval +else + ENABLED_TRUNCATED_HMAC=no + +fi + + +if test "x$ENABLED_TRUNCATED_HMAC" = "xyes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_TLS_EXTENSIONS -DHAVE_TRUNCATED_HMAC" +fi + +# Renegotiation Indication - (FAKE Secure Renegotiation) +# Check whether --enable-renegotiation-indication was given. +if test "${enable_renegotiation_indication+set}" = set; then : + enableval=$enable_renegotiation_indication; ENABLED_RENEGOTIATION_INDICATION=$enableval +else + ENABLED_RENEGOTIATION_INDICATION=no + +fi + + +if test "x$ENABLED_RENEGOTIATION_INDICATION" = "xyes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_RENEGOTIATION_INDICATION" +fi + +# Secure Renegotiation +# Check whether --enable-secure-renegotiation was given. +if test "${enable_secure_renegotiation+set}" = set; then : + enableval=$enable_secure_renegotiation; ENABLED_SECURE_RENEGOTIATION=$enableval +else + ENABLED_SECURE_RENEGOTIATION=no + +fi + + +if test "x$ENABLED_SECURE_RENEGOTIATION" = "xyes" +then + if test "x$ENABLED_RENEGOTIATION_INDICATION" = "xyes" + then + as_fn_error $? "cannot enable renegotiation-indication and secure-renegotiation." "$LINENO" 5 + fi + AM_CFLAGS="$AM_CFLAGS -DHAVE_TLS_EXTENSIONS -DHAVE_SECURE_RENEGOTIATION" +fi + +# Supported Elliptic Curves Extensions +# Check whether --enable-supportedcurves was given. +if test "${enable_supportedcurves+set}" = set; then : + enableval=$enable_supportedcurves; ENABLED_SUPPORTED_CURVES=$enableval +else + ENABLED_SUPPORTED_CURVES=no + +fi + + +if test "x$ENABLED_SUPPORTED_CURVES" = "xyes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_TLS_EXTENSIONS -DHAVE_SUPPORTED_CURVES" +fi + +# Session Ticket Extension +# Check whether --enable-session-ticket was given. +if test "${enable_session_ticket+set}" = set; then : + enableval=$enable_session_ticket; ENABLED_SESSION_TICKET=$enableval +else + ENABLED_SESSION_TICKET=no + +fi + + +if test "x$ENABLED_SESSION_TICKET" = "xyes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_TLS_EXTENSIONS -DHAVE_SESSION_TICKET" +fi + +# TLS Extensions +# Check whether --enable-tlsx was given. +if test "${enable_tlsx+set}" = set; then : + enableval=$enable_tlsx; ENABLED_TLSX=$enableval +else + ENABLED_TLSX=no + +fi + + +if test "x$ENABLED_TLSX" = "xyes" +then + ENABLED_SNI=yes + ENABLED_MAX_FRAGMENT=yes + ENABLED_TRUNCATED_HMAC=yes + ENABLED_SUPPORTED_CURVES=yes + AM_CFLAGS="$AM_CFLAGS -DHAVE_TLS_EXTENSIONS -DHAVE_SNI -DHAVE_MAX_FRAGMENT -DHAVE_TRUNCATED_HMAC -DHAVE_SUPPORTED_CURVES" +fi + +# PKCS7 +# Check whether --enable-pkcs7 was given. +if test "${enable_pkcs7+set}" = set; then : + enableval=$enable_pkcs7; ENABLED_PKCS7=$enableval +else + ENABLED_PKCS7=no +fi + + +if test "$ENABLED_PKCS7" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_PKCS7" +fi + + if test "x$ENABLED_PKCS7" = "xyes"; then + BUILD_PKCS7_TRUE= + BUILD_PKCS7_FALSE='#' +else + BUILD_PKCS7_TRUE='#' + BUILD_PKCS7_FALSE= +fi + + + +# Simple Certificate Enrollment Protocol (SCEP) +# Check whether --enable-scep was given. +if test "${enable_scep+set}" = set; then : + enableval=$enable_scep; ENABLED_WOLFSCEP=$enableval +else + ENABLED_WOLFSCEP=no + +fi + +if test "$ENABLED_WOLFSCEP" = "yes" +then + # Enable prereqs if not already enabled + if test "x$ENABLED_KEYGEN" = "xno" + then + ENABLED_KEYGEN="yes" + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_KEY_GEN" + fi + if test "x$ENABLED_CERTGEN" = "xno" + then + ENABLED_CERTGEN="yes" + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_CERT_GEN" + fi + if test "x$ENABLED_CERTREQ" = "xno" + then + ENABLED_CERTREQ="yes" + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_CERT_REQ" + fi + if test "x$ENABLED_PKCS7" = "xno" + then + ENABLED_PKCS7="yes" + AM_CFLAGS="$AM_CFLAGS -DHAVE_PKCS7" + if test "x$ENABLED_PKCS7" = "xyes"; then + BUILD_PKCS7_TRUE= + BUILD_PKCS7_FALSE='#' +else + BUILD_PKCS7_TRUE='#' + BUILD_PKCS7_FALSE= +fi + + fi + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_HAVE_WOLFSCEP" +fi + + +# Small Stack +# Check whether --enable-smallstack was given. +if test "${enable_smallstack+set}" = set; then : + enableval=$enable_smallstack; ENABLED_SMALL_STACK=$enableval +else + ENABLED_SMALL_STACK=no + +fi + + +if test "x$ENABLED_SMALL_STACK" = "xyes" +then + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_SMALL_STACK" +fi + + +#valgrind +# Check whether --enable-valgrind was given. +if test "${enable_valgrind+set}" = set; then : + enableval=$enable_valgrind; ENABLED_VALGRIND=$enableval +else + ENABLED_VALGRIND=no + +fi + + +if test "$ENABLED_VALGRIND" = "yes" +then + # Extract the first word of "valgrind", so it can be a program name with args. +set dummy valgrind; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_HAVE_VALGRIND+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$HAVE_VALGRIND"; then + ac_cv_prog_HAVE_VALGRIND="$HAVE_VALGRIND" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_HAVE_VALGRIND="yes" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + + test -z "$ac_cv_prog_HAVE_VALGRIND" && ac_cv_prog_HAVE_VALGRIND="no" +fi +fi +HAVE_VALGRIND=$ac_cv_prog_HAVE_VALGRIND +if test -n "$HAVE_VALGRIND"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $HAVE_VALGRIND" >&5 +$as_echo "$HAVE_VALGRIND" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + + if test "$HAVE_VALGRIND" = "no" + then + as_fn_error $? "Valgrind not found." "$LINENO" 5 + fi + enable_shared=no + enable_static=yes + AM_CFLAGS="$AM_CFLAGS -DHAVE_VALGRIND" +fi + + if test "x$ENABLED_VALGRIND" = "xyes"; then + USE_VALGRIND_TRUE= + USE_VALGRIND_FALSE='#' +else + USE_VALGRIND_TRUE='#' + USE_VALGRIND_FALSE= +fi + + + +# Test certs, use internal cert functions for extra testing +# Check whether --enable-testcert was given. +if test "${enable_testcert+set}" = set; then : + enableval=$enable_testcert; ENABLED_TESTCERT=$enableval +else + ENABLED_TESTCERT=no + +fi + + +if test "$ENABLED_TESTCERT" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_TEST_CERT" +fi + + +# I/O Pool, an example to show user how to override memory handler and use +# a pool for the input/output buffer requests +# Check whether --enable-iopool was given. +if test "${enable_iopool+set}" = set; then : + enableval=$enable_iopool; ENABLED_IOPOOL=$enableval +else + ENABLED_IOPOOL=no + +fi + + +if test "$ENABLED_IOPOOL" = "yes" +then + if test "$thread_ls_on" = "no" + then + as_fn_error $? "I/O Pool example requires Thread Local Storage" "$LINENO" 5 + fi + AM_CFLAGS="$AM_CFLAGS -DHAVE_IO_POOL -DXMALLOC_USER" +fi + + +# Certificate Service Support +# Check whether --enable-certservice was given. +if test "${enable_certservice+set}" = set; then : + enableval=$enable_certservice; ENABLED_CERT_SERVICE=$enableval +else + ENABLED_CERT_SERVICE=no + +fi + +if test "$ENABLED_CERT_SERVICE" = "yes" +then + # Requires ecc,certgen, and opensslextra make sure on + if test "x$ENABLED_CERTGEN" = "xno" + then + ENABLED_CERTGEN="yes" + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_CERT_GEN" + fi + if test "x$ENABLED_ECC" = "xno" + then + ENABLED_ECC="yes" + AM_CFLAGS="$AM_CFLAGS -DHAVE_ECC -DTFM_ECC256 -DECC_SHAMIR" + if test "x$ENABLED_ECC" = "xyes"; then + BUILD_ECC_TRUE= + BUILD_ECC_FALSE='#' +else + BUILD_ECC_TRUE='#' + BUILD_ECC_FALSE= +fi + + fi + if test "x$ENABLED_OPENSSLEXTRA" = "xno" + then + ENABLED_OPENSSLEXTRA="yes" + AM_CFLAGS="-DOPENSSL_EXTRA $AM_CFLAGS" + fi + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_HAVE_CERT_SERVICE" +fi + + +# PWDBASED has to come after certservice since we want it on w/o explicit on +# PWDBASED +# Check whether --enable-pwdbased was given. +if test "${enable_pwdbased+set}" = set; then : + enableval=$enable_pwdbased; ENABLED_PWDBASED=$enableval +else + ENABLED_PWDBASED=no + +fi + + +if test "$ENABLED_PWDBASED" = "no" +then + if test "$ENABLED_OPENSSLEXTRA" = "yes" || test "$ENABLED_WEBSERVER" = "yes" + then + # opensslextra and webserver needs pwdbased + ENABLED_PWDBASED=yes + else + AM_CFLAGS="$AM_CFLAGS -DNO_PWDBASED" + fi +fi + + if test "x$ENABLED_PWDBASED" = "xyes"; then + BUILD_PWDBASED_TRUE= + BUILD_PWDBASED_FALSE='#' +else + BUILD_PWDBASED_TRUE='#' + BUILD_PWDBASED_FALSE= +fi + + + +# set fastmath default +FASTMATH_DEFAULT=no + +if test "$host_cpu" = "x86_64" +then +FASTMATH_DEFAULT=yes +fi + +# fastmath +# Check whether --enable-fastmath was given. +if test "${enable_fastmath+set}" = set; then : + enableval=$enable_fastmath; ENABLED_FASTMATH=$enableval +else + ENABLED_FASTMATH=$FASTMATH_DEFAULT + +fi + + +if test "x$ENABLED_FASTMATH" = "xyes" +then + # turn off fastmth if leanpsk on or asn off (w/o dh) + if test "$ENABLED_LEANPSK" = "yes" || test "$ENABLED_ASN" = "no" + then + if test "$ENABLED_DH" = "no" + then + ENABLED_FASTMATH=no + else + AM_CFLAGS="$AM_CFLAGS -DUSE_FAST_MATH" + ENABLED_SLOWMATH="no" + fi + else + AM_CFLAGS="$AM_CFLAGS -DUSE_FAST_MATH" + ENABLED_SLOWMATH="no" + fi + if test "$host_cpu" = "x86_64" + then + # Have settings.h set FP_MAX_BITS higher if user didn't set directly + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_X86_64_BUILD" + fi +fi + + +# fast HUGE math +# Check whether --enable-fasthugemath was given. +if test "${enable_fasthugemath+set}" = set; then : + enableval=$enable_fasthugemath; ENABLED_FASTHUGEMATH=$enableval +else + ENABLED_FASTHUGEMATH=no + +fi + + +if test "$ENABLED_BUMP" = "yes" +then + ENABLED_FASTHUGEMATH="yes" +fi + +if test "$ENABLED_FASTHUGEMATH" = "yes" +then + ENABLED_FASTMATH="yes" + AM_CFLAGS="$AM_CFLAGS -DUSE_FAST_MATH" + ENABLED_SLOWMATH="no" +fi + + if test "x$ENABLED_FASTMATH" = "xyes"; then + BUILD_FASTMATH_TRUE= + BUILD_FASTMATH_FALSE='#' +else + BUILD_FASTMATH_TRUE='#' + BUILD_FASTMATH_FALSE= +fi + + if test "x$ENABLED_SLOWMATH" = "xyes"; then + BUILD_SLOWMATH_TRUE= + BUILD_SLOWMATH_FALSE='#' +else + BUILD_SLOWMATH_TRUE='#' + BUILD_SLOWMATH_FALSE= +fi + + + +# Enable Examples, used to disable examples +# Check whether --enable-examples was given. +if test "${enable_examples+set}" = set; then : + enableval=$enable_examples; ENABLED_EXAMPLES=$enableval +else + ENABLED_EXAMPLES=yes + +fi + + +if test "x$ENABLED_FILESYSTEM" = "xno"; then : + ENABLED_EXAMPLES="no" +fi +if test "x$ENABLED_INLINE" = "xno"; then : + ENABLED_EXAMPLES="no" +fi + if test "x$ENABLED_EXAMPLES" = "xyes"; then + BUILD_EXAMPLES_TRUE= + BUILD_EXAMPLES_FALSE='#' +else + BUILD_EXAMPLES_TRUE='#' + BUILD_EXAMPLES_FALSE= +fi + + + +# LIBZ +ENABLED_LIBZ="no" +trylibzdir="" + +# Check whether --with-libz was given. +if test "${with_libz+set}" = set; then : + withval=$with_libz; + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for libz" >&5 +$as_echo_n "checking for libz... " >&6; } + CPPFLAGS="$CPPFLAGS -DHAVE_LIBZ" + LIBS="$LIBS -lz" + + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +int +main () +{ + deflateInit(0, 8); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + libz_linked=yes +else + libz_linked=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + + if test "x$libz_linked" == "xno" ; then + if test "x$withval" != "xno" ; then + trylibzdir=$withval + fi + if test "x$withval" == "xyes" ; then + trylibzdir="/usr" + fi + + AM_LDFLAGS="$AM_LDFLAGS -L$trylibzdir/lib" + CPPFLAGS="$CPPFLAGS -I$trylibzdir/include" + + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +int +main () +{ + deflateInit(0, 8); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + libz_linked=yes +else + libz_linked=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + + if test "x$libz_linked" == "xno" ; then + as_fn_error $? "libz isn't found. + If it's already installed, specify its path using --with-libz=/dir/" "$LINENO" 5 + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + fi + ENABLED_LIBZ="yes" + + +fi + + if test "x$ENABLED_LIBZ" = "xyes"; then + BUILD_LIBZ_TRUE= + BUILD_LIBZ_FALSE='#' +else + BUILD_LIBZ_TRUE='#' + BUILD_LIBZ_FALSE= +fi + + + +# cavium +trycaviumdir="" + +# Check whether --with-cavium was given. +if test "${with_cavium+set}" = set; then : + withval=$with_cavium; + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for cavium" >&5 +$as_echo_n "checking for cavium... " >&6; } + CPPFLAGS="$CPPFLAGS -DHAVE_CAVIUM" + + if test "x$withval" == "xyes" ; then + as_fn_error $? "need a PATH for --with-cavium" "$LINENO" 5 + fi + if test "x$withval" != "xno" ; then + trycaviumdir=$withval + fi + + LDFLAGS="$AM_LDFLAGS $trycaviumdir/api/cavium_common.o" + CPPFLAGS="$CPPFLAGS -I$trycaviumdir/include" + + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include "cavium_common.h" +int +main () +{ + CspShutdown(CAVIUM_DEV_ID); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + cavium_linked=yes +else + cavium_linked=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + + if test "x$cavium_linked" == "xno" ; then + as_fn_error $? "cavium isn't found. + If it's already installed, specify its path using --with-cavium=/dir/" "$LINENO" 5 + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + enable_shared=no + enable_static=yes + + +fi + + + +# microchip api +# Check whether --enable-mcapi was given. +if test "${enable_mcapi+set}" = set; then : + enableval=$enable_mcapi; ENABLED_MCAPI=$enableval +else + ENABLED_MCAPI=no + +fi + + +if test "$ENABLED_MCAPI" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_MCAPI -DWOLFSSL_AES_COUNTER -DWOLFSSL_AES_DIRECT" +fi + +if test "$ENABLED_MCAPI" = "yes" && test "$ENABLED_SHA512" = "no" +then + as_fn_error $? "please enable sha512 if enabling mcapi." "$LINENO" 5 +fi + +if test "$ENABLED_MCAPI" = "yes" && test "$ENABLED_ECC" = "no" +then + as_fn_error $? "please enable ecc if enabling mcapi." "$LINENO" 5 +fi + +if test "$ENABLED_MCAPI" = "yes" && test "$ENABLED_LIBZ" = "no" +then + as_fn_error $? "please use --with-libz if enabling mcapi." "$LINENO" 5 +fi + + if test "x$ENABLED_MCAPI" = "xyes"; then + BUILD_MCAPI_TRUE= + BUILD_MCAPI_FALSE='#' +else + BUILD_MCAPI_TRUE='#' + BUILD_MCAPI_FALSE= +fi + + + +# wolfSSL JNI +# Check whether --enable-jni was given. +if test "${enable_jni+set}" = set; then : + enableval=$enable_jni; ENABLED_JNI=$enableval +else + ENABLED_JNI=no + +fi + +if test "$ENABLED_JNI" = "yes" +then + # Enable prereqs if not already enabled + if test "x$ENABLED_DTLS" = "xno" + then + ENABLED_DTLS="yes" + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_DTLS" + fi + if test "x$ENABLED_OPENSSLEXTRA" = "xno" + then + ENABLED_OPENSSLEXTRA="yes" + AM_CFLAGS="$AM_CFLAGS -DOPENSSL_EXTRA" + fi + if test "x$ENABLED_CRL" = "xno" + then + ENABLED_CRL="yes" + AM_CFLAGS="$AM_CFLAGS -DHAVE_CRL" + if test "x$ENABLED_CRL" = "xyes"; then + BUILD_CRL_TRUE= + BUILD_CRL_FALSE='#' +else + BUILD_CRL_TRUE='#' + BUILD_CRL_FALSE= +fi + + fi + if test "x$ENABLED_OCSP" = "xno" + then + ENABLED_OCSP="yes" + AM_CFLAGS="$AM_CFLAGS -DHAVE_OCSP" + if test "x$ENABLED_OCSP" = "xyes"; then + BUILD_OCSP_TRUE= + BUILD_OCSP_FALSE='#' +else + BUILD_OCSP_TRUE='#' + BUILD_OCSP_FALSE= +fi + + fi + if test "x$ENABLED_CRL_MONITOR" = "xno" + then + ENABLED_CRL_MONITOR="yes" + AM_CFLAGS="$AM_CFLAGS -DHAVE_CRL_MONITOR" + fi + if test "x$ENABLED_SAVESESSION" = "xno" + then + ENABLED_SAVESESSION="yes" + AM_CFLAGS="$AM_CFLAGS -DPERSIST_SESSION_CACHE" + fi + if test "x$ENABLED_SAVECERT" = "xno" + then + ENABLED_SAVECERT="yes" + AM_CFLAGS="$AM_CFLAGS -DPERSIST_CERT_CACHE" + fi + if test "x$ENABLED_ATOMICUSER" = "xno" + then + ENABLED_ATOMICUSER="yes" + AM_CFLAGS="$AM_CFLAGS -DATOMIC_USER" + fi + if test "x$ENABLED_ECC" = "xno" + then + ENABLED_ECC="yes" + AM_CFLAGS="$AM_CFLAGS -DHAVE_ECC" + fi + if test "x$ENABLED_PKCALLBACKS" = "xno" + then + ENABLED_PKCALLBACKS="yes" + AM_CFLAGS="$AM_CFLAGS -DHAVE_PK_CALLBACKS" + fi + if test "x$ENABLED_DH" = "xno" + then + ENABLED_DH="yes" + AM_CFLAGS="$AM_CFLAGS -DHAVE_DH" + fi +fi + + +# Check for build-type conflicts +if test "x$ENABLED_MAXSTRENGTH" = "xyes" && \ + test "x$ENABLED_LEANPSK" = "xyes"; then : + as_fn_error $? "Cannot use Max Strength and Lean PSK at the same time." "$LINENO" 5 +fi + + +# Update CFLAGS based on options +if test "x$ENABLED_MAXSTRENGTH" = "xyes"; then : + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_MAX_STRENGTH" +fi + +if test "x$ENABLED_MAXSTRENGTH" = "xyes" && \ + test "x$ENABLED_OLD_TLS" = "xyes"; then : + AM_CFLAGS="$AM_CFLAGS -DNO_OLD_TLS" + ENABLED_OLD_TLS=no +fi + + +# OPTIMIZE FLAGS +if test "$GCC" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -Wall -Wno-unused" + if test "$ax_enable_debug" = "no" + then + if test "$ENABLED_FASTMATH" = "yes" + then + AM_CFLAGS="$AM_CFLAGS $OPTIMIZE_FAST_CFLAGS" + if test "$ENABLED_FASTHUGEMATH" = "yes" + then + AM_CFLAGS="$AM_CFLAGS $OPTIMIZE_HUGE_CFLAGS" + fi + else + AM_CFLAGS="$AM_CFLAGS $OPTIMIZE_CFLAGS" + fi + fi +fi + +# ICC command line warning for non supported warning flags +if test "$CC" = "icc" +then + AM_CFLAGS="$AM_CFLAGS -wd10006" +fi + + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing gethostbyname" >&5 +$as_echo_n "checking for library containing gethostbyname... " >&6; } +if ${ac_cv_search_gethostbyname+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_func_search_save_LIBS=$LIBS +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char gethostbyname (); +int +main () +{ +return gethostbyname (); + ; + return 0; +} +_ACEOF +for ac_lib in '' nsl; do + if test -z "$ac_lib"; then + ac_res="none required" + else + ac_res=-l$ac_lib + LIBS="-l$ac_lib $ac_func_search_save_LIBS" + fi + if ac_fn_c_try_link "$LINENO"; then : + ac_cv_search_gethostbyname=$ac_res +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext + if ${ac_cv_search_gethostbyname+:} false; then : + break +fi +done +if ${ac_cv_search_gethostbyname+:} false; then : + +else + ac_cv_search_gethostbyname=no +fi +rm conftest.$ac_ext +LIBS=$ac_func_search_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_search_gethostbyname" >&5 +$as_echo "$ac_cv_search_gethostbyname" >&6; } +ac_res=$ac_cv_search_gethostbyname +if test "$ac_res" != no; then : + test "$ac_res" = "none required" || LIBS="$ac_res $LIBS" + +fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing socket" >&5 +$as_echo_n "checking for library containing socket... " >&6; } +if ${ac_cv_search_socket+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_func_search_save_LIBS=$LIBS +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char socket (); +int +main () +{ +return socket (); + ; + return 0; +} +_ACEOF +for ac_lib in '' socket; do + if test -z "$ac_lib"; then + ac_res="none required" + else + ac_res=-l$ac_lib + LIBS="-l$ac_lib $ac_func_search_save_LIBS" + fi + if ac_fn_c_try_link "$LINENO"; then : + ac_cv_search_socket=$ac_res +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext + if ${ac_cv_search_socket+:} false; then : + break +fi +done +if ${ac_cv_search_socket+:} false; then : + +else + ac_cv_search_socket=no +fi +rm conftest.$ac_ext +LIBS=$ac_func_search_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_search_socket" >&5 +$as_echo "$ac_cv_search_socket" >&6; } +ac_res=$ac_cv_search_socket +if test "$ac_res" != no; then : + test "$ac_res" = "none required" || LIBS="$ac_res $LIBS" + +else + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for socket in -lsocket" >&5 +$as_echo_n "checking for socket in -lsocket... " >&6; } +if ${ac_cv_lib_socket_socket+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lsocket -lnsl $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char socket (); +int +main () +{ +return socket (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_socket_socket=yes +else + ac_cv_lib_socket_socket=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_socket_socket" >&5 +$as_echo "$ac_cv_lib_socket_socket" >&6; } +if test "x$ac_cv_lib_socket_socket" = xyes; then : + LIBS="-lsocket -lnsl $LIBS" +fi + +fi + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for vcs system" >&5 +$as_echo_n "checking for vcs system... " >&6; } +if ${ac_cv_vcs_system+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_cv_vcs_system="none" + if test -d ".bzr"; then : + ac_cv_vcs_system="bazaar" +fi + if test -d ".svn"; then : + ac_cv_vcs_system="svn" +fi + if test -d ".hg"; then : + ac_cv_vcs_system="mercurial" +fi + if test -d ".git"; then : + ac_cv_vcs_system="git" +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_vcs_system" >&5 +$as_echo "$ac_cv_vcs_system" >&6; } + +cat >>confdefs.h <<_ACEOF +#define VCS_SYSTEM "$ac_cv_vcs_system" +_ACEOF + + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for vcs checkout" >&5 +$as_echo_n "checking for vcs checkout... " >&6; } +if ${ac_cv_vcs_checkout+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test "x$ac_cv_vcs_system" != "xnone"; then : + ac_cv_vcs_checkout=yes +else + ac_cv_vcs_checkout=no +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_vcs_checkout" >&5 +$as_echo "$ac_cv_vcs_checkout" >&6; } + + if test "x$ac_cv_vcs_checkout" = "xyes"; then + IS_VCS_CHECKOUT_TRUE= + IS_VCS_CHECKOUT_FALSE='#' +else + IS_VCS_CHECKOUT_TRUE='#' + IS_VCS_CHECKOUT_FALSE= +fi + + if test "x$ac_cv_vcs_checkout" = "xyes"; then : + +$as_echo "#define VCS_CHECKOUT 1" >>confdefs.h + +else + +$as_echo "#define VCS_CHECKOUT 0" >>confdefs.h + +fi + + + + + + AX_HARDEN_LIB= + ax_append_compile_link_flags_extra= + if test "x$ac_cv_vcs_checkout" = "xyes"; then : + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the linker accepts -Werror" >&5 +$as_echo_n "checking whether the linker accepts -Werror... " >&6; } +if ${ax_cv_check_ldflags___Werror+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$LDFLAGS + LDFLAGS="$LDFLAGS -Werror" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ax_cv_check_ldflags___Werror=yes +else + ax_cv_check_ldflags___Werror=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + LDFLAGS=$ax_check_save_flags +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ax_cv_check_ldflags___Werror" >&5 +$as_echo "$ax_cv_check_ldflags___Werror" >&6; } +if test x"$ax_cv_check_ldflags___Werror" = xyes; then : + + AX_HARDEN_LIB="-Werror $AX_HARDEN_LIB" + +else + : +fi + + +else + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the linker accepts -Werror" >&5 +$as_echo_n "checking whether the linker accepts -Werror... " >&6; } +if ${ax_cv_check_ldflags___Werror+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$LDFLAGS + LDFLAGS="$LDFLAGS -Werror" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ax_cv_check_ldflags___Werror=yes +else + ax_cv_check_ldflags___Werror=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + LDFLAGS=$ax_check_save_flags +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ax_cv_check_ldflags___Werror" >&5 +$as_echo "$ax_cv_check_ldflags___Werror" >&6; } +if test x"$ax_cv_check_ldflags___Werror" = xyes; then : + + ax_append_compile_link_flags_extra='-Werror' + +else + : +fi + + +fi + + as_CACHEVAR=`$as_echo "ax_cv_check_ldflags_$ax_append_compile_link_flags_extra_-z relro -z now" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the linker accepts -z relro -z now" >&5 +$as_echo_n "checking whether the linker accepts -z relro -z now... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$LDFLAGS + LDFLAGS="$LDFLAGS $ax_append_compile_link_flags_extra -z relro -z now" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + LDFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + + AX_HARDEN_LIB="-z relro -z now $AX_HARDEN_LIB" + +else + : +fi + + + as_CACHEVAR=`$as_echo "ax_cv_check_ldflags_$ax_append_compile_link_flags_extra_-pie" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the linker accepts -pie" >&5 +$as_echo_n "checking whether the linker accepts -pie... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$LDFLAGS + LDFLAGS="$LDFLAGS $ax_append_compile_link_flags_extra -pie" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + LDFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + + AX_HARDEN_LIB="-pie $AX_HARDEN_LIB" + +else + : +fi + + + LIB="$LIB $AX_HARDEN_LIB" + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts " >&5 +$as_echo_n "checking whether C compiler accepts ... " >&6; } +if ${ax_cv_check_cflags__+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS " + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ax_cv_check_cflags__=yes +else + ax_cv_check_cflags__=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ax_cv_check_cflags__" >&5 +$as_echo "$ax_cv_check_cflags__" >&6; } +if test x"$ax_cv_check_cflags__" = xyes; then : + : +else + : +fi + +if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains "; } >&5 + (: CFLAGS already contains ) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \""; } >&5 + (: CFLAGS="$CFLAGS ") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS " + ;; + esac +else + CFLAGS="" +fi + + + + + ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + + CFLAGS= + ac_cv_warnings_as_errors=no + ax_append_compile_cflags_extra= + if test "$ac_cv_vcs_checkout" = "yes"; then : + + + +for flag in -Werror; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags__$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + ac_cv_warnings_as_errors=yes + +else + + + +for flag in -Werror; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags__$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${ax_append_compile_cflags_extra+:} false; then : + case " $ax_append_compile_cflags_extra " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : ax_append_compile_cflags_extra already contains \$flag"; } >&5 + (: ax_append_compile_cflags_extra already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : ax_append_compile_cflags_extra=\"\$ax_append_compile_cflags_extra \$flag\""; } >&5 + (: ax_append_compile_cflags_extra="$ax_append_compile_cflags_extra $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ax_append_compile_cflags_extra="$ax_append_compile_cflags_extra $flag" + ;; + esac +else + ax_append_compile_cflags_extra="$flag" +fi + +else + : +fi + +done + + +fi + + if test "$ax_enable_debug" = "yes"; then : + + + +for flag in -g; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags__$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -ggdb; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -O0; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + +fi + + + +for flag in -Wno-pragmas; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + + +for flag in -Wall; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wno-strict-aliasing; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wextra; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wunknown-pragmas; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wthis-test-should-fail; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + if test "$CC" = "clang"; then : + +else + + + +for flag in --param=ssp-buffer-size=1; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + +fi + + +for flag in -Waddress; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Warray-bounds; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wbad-function-cast; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wchar-subscripts; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wcomment; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wfloat-equal; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wformat-security; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wformat=2; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wmaybe-uninitialized; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wmissing-field-initializers; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wmissing-noreturn; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wmissing-prototypes; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wnested-externs; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wnormalized=id; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Woverride-init; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wpointer-arith; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wpointer-sign; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wredundant-decls; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wshadow; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wshorten-64-to-32; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wsign-compare; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wstrict-overflow=1; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wstrict-prototypes; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wswitch-enum; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wundef; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wunused; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wunused-result; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wunused-variable; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -Wwrite-strings; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -fwrapv; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + + +for flag in -fPIE; do + as_CACHEVAR=`$as_echo "ax_cv_check_cflags_$ax_append_compile_cflags_extra_$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C compiler accepts $flag" >&5 +$as_echo_n "checking whether C compiler accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CFLAGS + CFLAGS="$CFLAGS $ax_append_compile_cflags_extra $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if test x"`eval 'as_val=${'$as_CACHEVAR'};$as_echo "$as_val"'`" = xyes; then : + if ${CFLAGS+:} false; then : + case " $CFLAGS " in + *" $flag "*) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS already contains \$flag"; } >&5 + (: CFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; + *) + { { $as_echo "$as_me:${as_lineno-$LINENO}: : CFLAGS=\"\$CFLAGS \$flag\""; } >&5 + (: CFLAGS="$CFLAGS $flag") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + CFLAGS="$CFLAGS $flag" + ;; + esac +else + CFLAGS="$flag" +fi + +else + : +fi + +done + + ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + + +# link to ws2_32 if on mingw +case $host_os in + *mingw32) + LDFLAGS="$LDFLAGS -lws2_32" ;; +esac + +# add user C_EXTRA_FLAGS back +CFLAGS="$CFLAGS $USER_C_EXTRA_FLAGS" +OPTION_FLAGS="$USER_C_EXTRA_FLAGS $AM_CFLAGS" + + + + HEX_VERSION=`echo $VERSION | sed 's|\-a-z0-9*$||' | \ + awk -F. '{printf "0x%0.2d%0.3d%0.3d", $1, $2, $3}'` + + + + + + +# FINAL +ac_config_files="$ac_config_files stamp-h" + +ac_config_files="$ac_config_files Makefile" + +ac_config_files="$ac_config_files wolfssl/version.h" + +ac_config_files="$ac_config_files wolfssl/options.h" + +#have options.h and version.h for autoconf fips tag and build +#if test "x$ENABLED_FIPS" = "xyes" +#then +# AC_CONFIG_FILES([cyassl/version.h]) +# AC_CONFIG_FILES([cyassl/options.h]) +#fi +ac_config_files="$ac_config_files support/wolfssl.pc" + +ac_config_files="$ac_config_files rpm/spec" + + +# create a generic PACKAGE-config file +L=`echo $PACKAGE $LIBS` +P=`echo $L | sed -e 's/ -.*//'` +P=`echo $P` +V=`echo $VERSION` +F=`echo $P-config` +L=`echo -l$L | sed -e 's/^-llib/-l/'` +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: creating $F - generic $V for $L" >&5 +$as_echo "creating $F - generic $V for $L" >&6; } +test "x$prefix" = xNONE && prefix="$ac_default_prefix" +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' +echo '#! /bin/sh' >$F +echo ' ' >>$F +echo 'package="'$P'"' >>$F +echo 'version="'$V'"' >>$F +echo 'libs="'$L'"' >>$F +echo ' ' >>$F +# in the order of occurence a standard automake Makefile +echo 'prefix="'$prefix'"' >>$F +echo 'exec_prefix="'$exec_prefix'"' >>$F +echo 'bindir="'$bindir'"' >>$F +echo 'sbindir="'$sbindir'"' >>$F +echo 'libexecdir="'$libexecdir'"' >>$F +echo 'datadir="'$datadir'"' >>$F +echo 'sysconfdir="'$sysconfdir'"' >>$F +echo 'sharedstatedir="'$sharedstatedir'"' >>$F +echo 'localstatedir="'$localstatedir'"' >>$F +echo 'libdir="'$libdir'"' >>$F +echo 'infodir="'$infodir'"' >>$F +echo 'mandir="'$mandir'"' >>$F +echo 'includedir="'$includedir'"' >>$F +echo 'target="'$target'"' >>$F +echo 'host="'$host'"' >>$F +echo 'build="'$build'"' >>$F +echo ' ' >>$F +echo 'if test "'"\$""#"'" -eq 0; then' >>$F +echo ' cat <>$F +echo 'Usage: $package-config OPTIONS' >>$F +echo 'Options:' >>$F +echo ' --prefix=DIR) : \$prefix' >>$F +echo ' --package) : \$package' >>$F +echo ' --version) : \$version' >>$F +echo ' --cflags) : -I\$includedir' >>$F +echo ' --libs) : -L\$libdir -l\$package' >>$F +echo ' --help) print all the options (not just these)' >>$F +echo 'EOF' >>$F +echo 'fi' >>$F +echo ' ' >>$F +echo 'o=""' >>$F +echo 'h=""' >>$F +echo 'for i in "$@"; do' >>$F +echo ' case $i in' >>$F +echo ' --prefix=*) prefix=`echo $i | sed -e "s/--prefix=//"` ;;' >>$F +echo ' --prefix) o="$o $prefix" ;;' >>$F +echo ' --package) o="$o $package" ;;' >>$F +echo ' --version) o="$o $version" ;;' >>$F +echo ' --cflags) if test "_$includedir" != "_/usr/include"' >>$F +echo ' then o="$o -I$includedir" ; fi' >>$F +echo ' ;;' >>$F +echo ' --libs) o="$o -L$libdir $libs" ;;' >>$F +echo ' --exec_prefix|--eprefix) o="$o $exec_prefix" ;;' >>$F +echo ' --bindir) o="$o $bindir" ;;' >>$F +echo ' --sbindir) o="$o $sbindir" ;;' >>$F +echo ' --libexecdir) o="$o $libexecdir" ;;' >>$F +echo ' --datadir) o="$o $datadir" ;;' >>$F +echo ' --datainc) o="$o -I$datadir" ;;' >>$F +echo ' --datalib) o="$o -L$datadir" ;;' >>$F +echo ' --sysconfdir) o="$o $sysconfdir" ;;' >>$F +echo ' --sharedstatedir) o="$o $sharedstatedir" ;;' >>$F +echo ' --localstatedir) o="$o $localstatedir" ;;' >>$F +echo ' --libdir) o="$o $libdir" ;;' >>$F +echo ' --libadd) o="$o -L$libdir" ;;' >>$F +echo ' --infodir) o="$o $infodir" ;;' >>$F +echo ' --mandir) o="$o $mandir" ;;' >>$F +echo ' --target) o="$o $target" ;;' >>$F +echo ' --host) o="$o $host" ;;' >>$F +echo ' --build) o="$o $build" ;;' >>$F +echo ' --data) o="$o -I$datadir/$package" ;;' >>$F +echo ' --pkgdatadir) o="$o $datadir/$package" ;;' >>$F +echo ' --pkgdatainc) o="$o -I$datadir/$package" ;;' >>$F +echo ' --pkgdatalib) o="$o -L$datadir/$package" ;;' >>$F +echo ' --pkglibdir) o="$o $libdir/$package" ;;' >>$F +echo ' --pkglibinc) o="$o -I$libinc/$package" ;;' >>$F +echo ' --pkglibadd) o="$o -L$libadd/$package" ;;' >>$F +echo ' --pkgincludedir) o="$o $includedir/$package" ;;' >>$F +echo ' --help) h="1" ;;' >>$F +echo ' -?//*|-?/*//*|-?./*//*|//*|/*//*|./*//*) ' >>$F +echo ' v=`echo $i | sed -e s://:\$:g`' >>$F +echo ' v=`eval "echo $v"` ' >>$F +echo ' o="$o $v" ;; ' >>$F +echo ' esac' >>$F +echo 'done' >>$F +echo ' ' >>$F +echo 'o=`eval "echo $o"`' >>$F +echo 'o=`eval "echo $o"`' >>$F +echo 'eval "echo $o"' >>$F +echo ' ' >>$F +echo 'if test ! -z "$h" ; then ' >>$F +echo 'cat <>$F +echo ' --prefix=xxx) (what is that for anyway?)' >>$F +echo ' --prefix) \$prefix $prefix' >>$F +echo ' --package) \$package $package' >>$F +echo ' --version) \$version $version' >>$F +echo ' --cflags) -I\$includedir unless it is /usr/include' >>$F +echo ' --libs) -L\$libdir -l\$PACKAGE \$LIBS' >>$F +echo ' --exec_prefix) or... ' >>$F +echo ' --eprefix) \$exec_prefix $exec_prefix' >>$F +echo ' --bindir) \$bindir $bindir' >>$F +echo ' --sbindir) \$sbindir $sbindir' >>$F +echo ' --libexecdir) \$libexecdir $libexecdir' >>$F +echo ' --datadir) \$datadir $datadir' >>$F +echo ' --sysconfdir) \$sysconfdir $sysconfdir' >>$F +echo ' --sharedstatedir) \$sharedstatedir$sharedstatedir' >>$F +echo ' --localstatedir) \$localstatedir $localstatedir' >>$F +echo ' --libdir) \$libdir $libdir' >>$F +echo ' --infodir) \$infodir $infodir' >>$F +echo ' --mandir) \$mandir $mandir' >>$F +echo ' --target) \$target $target' >>$F +echo ' --host) \$host $host' >>$F +echo ' --build) \$build $build' >>$F +echo ' --data) -I\$datadir/\$package' >>$F +echo ' --pkgdatadir) \$datadir/\$package' >>$F +echo ' --pkglibdir) \$libdir/\$package' >>$F +echo ' --pkgincludedir) \$includedir/\$package' >>$F +echo ' --help) generated by ax_create_generic_config.m4' >>$F +echo ' -I//varname and other inc-targets like --pkgdatainc supported' >>$F +echo ' -L//varname and other lib-targets, e.g. --pkgdatalib or --libadd' >>$F +echo 'EOF' >>$F +echo 'fi' >>$F +GENERIC_CONFIG="$F" + + + + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking the number of available CPUs" >&5 +$as_echo_n "checking the number of available CPUs... " >&6; } + CPU_COUNT="0" + + case $host_os in #( + + *darwin*) : + + if test -x /usr/sbin/sysctl; then : + + sysctl_a=`/usr/sbin/sysctl -a 2>/dev/null| grep -c hw.cpu` + if test sysctl_a; then : + + CPU_COUNT=`/usr/sbin/sysctl -n hw.ncpu` + +fi + +fi ;; #( + + *linux*) : + + if test "x$CPU_COUNT" = "x0" -a -e /proc/cpuinfo; then : + + if test "x$CPU_COUNT" = "x0" -a -e /proc/cpuinfo; then : + + CPU_COUNT=`$EGREP -c '^processor' /proc/cpuinfo` + +fi + +fi + ;; #( + *) : + ;; +esac + + if test "x$CPU_COUNT" = "x0"; then : + + CPU_COUNT="1" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: unable to detect (assuming 1) " >&5 +$as_echo "unable to detect (assuming 1) " >&6; } + +else + + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CPU_COUNT " >&5 +$as_echo "$CPU_COUNT " >&6; } + +fi + + +AX_DOLLAR="\$" +AX_SRB="\\135" +AX_SLB="\\133" +AX_BS="\\\\" +AX_DQ="\"" + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: adding automake macro support" >&5 +$as_echo "$as_me: adding automake macro support" >&6;} +AMINCLUDE="aminclude.am" + +{ $as_echo "$as_me:${as_lineno-$LINENO}: creating $AMINCLUDE" >&5 +$as_echo "$as_me: creating $AMINCLUDE" >&6;} +AMINCLUDE_TIME=`date` + + +printf " +# generated automatically by configure from AX_AUTOMAKE_MACROS +# on $AMINCLUDE_TIME + +" > "$AMINCLUDE" + + +INC_AMINCLUDE="include \$(top_builddir)/$AMINCLUDE" + + + + + + # Check whether --enable-jobserver was given. +if test "${enable_jobserver+set}" = set; then : + enableval=$enable_jobserver; +else + enable_jobserver=yes +fi + + if test "x$enable_jobserver" = "xyes"; then + let enable_jobserver=$CPU_COUNT+1 + fi + + if test "x$enable_jobserver" != "xno"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: added jobserver support to make for $enable_jobserver jobs" >&5 +$as_echo "$as_me: added jobserver support to make for $enable_jobserver jobs" >&6;} + + + + +printf "AM_MAKEFLAGS += -j$enable_jobserver \n" >> "$AMINCLUDE" + + + fi + + +cat >confcache <<\_ACEOF +# This file is a shell script that caches the results of configure +# tests run on this system so they can be shared between configure +# scripts and configure runs, see configure's option --config-cache. +# It is not useful on other systems. If it contains results you don't +# want to keep, you may remove or edit it. +# +# config.status only pays attention to the cache file if you give it +# the --recheck option to rerun configure. +# +# `ac_cv_env_foo' variables (set or unset) will be overridden when +# loading this file, other *unset* `ac_cv_foo' will be assigned the +# following values. + +_ACEOF + +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, we kill variables containing newlines. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +( + for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do + eval ac_val=\$$ac_var + case $ac_val in #( + *${as_nl}*) + case $ac_var in #( + *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 +$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; + esac + case $ac_var in #( + _ | IFS | as_nl) ;; #( + BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #( + *) { eval $ac_var=; unset $ac_var;} ;; + esac ;; + esac + done + + (set) 2>&1 | + case $as_nl`(ac_space=' '; set) 2>&1` in #( + *${as_nl}ac_space=\ *) + # `set' does not quote correctly, so add quotes: double-quote + # substitution turns \\\\ into \\, and sed turns \\ into \. + sed -n \ + "s/'/'\\\\''/g; + s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p" + ;; #( + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p" + ;; + esac | + sort +) | + sed ' + /^ac_cv_env_/b end + t clear + :clear + s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/ + t end + s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/ + :end' >>confcache +if diff "$cache_file" confcache >/dev/null 2>&1; then :; else + if test -w "$cache_file"; then + if test "x$cache_file" != "x/dev/null"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5 +$as_echo "$as_me: updating cache $cache_file" >&6;} + if test ! -f "$cache_file" || test -h "$cache_file"; then + cat confcache >"$cache_file" + else + case $cache_file in #( + */* | ?:*) + mv -f confcache "$cache_file"$$ && + mv -f "$cache_file"$$ "$cache_file" ;; #( + *) + mv -f confcache "$cache_file" ;; + esac + fi + fi + else + { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5 +$as_echo "$as_me: not updating unwritable cache $cache_file" >&6;} + fi +fi +rm -f confcache + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +DEFS=-DHAVE_CONFIG_H + +ac_libobjs= +ac_ltlibobjs= +U= +for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue + # 1. Remove the extension, and $U if already installed. + ac_script='s/\$U\././;s/\.o$//;s/\.obj$//' + ac_i=`$as_echo "$ac_i" | sed "$ac_script"` + # 2. Prepend LIBOBJDIR. When used with automake>=1.10 LIBOBJDIR + # will be set to the directory where LIBOBJS objects are built. + as_fn_append ac_libobjs " \${LIBOBJDIR}$ac_i\$U.$ac_objext" + as_fn_append ac_ltlibobjs " \${LIBOBJDIR}$ac_i"'$U.lo' +done +LIBOBJS=$ac_libobjs + +LTLIBOBJS=$ac_ltlibobjs + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking that generated files are newer than configure" >&5 +$as_echo_n "checking that generated files are newer than configure... " >&6; } + if test -n "$am_sleep_pid"; then + # Hide warnings about reused PIDs. + wait $am_sleep_pid 2>/dev/null + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: done" >&5 +$as_echo "done" >&6; } + if test -n "$EXEEXT"; then + am__EXEEXT_TRUE= + am__EXEEXT_FALSE='#' +else + am__EXEEXT_TRUE='#' + am__EXEEXT_FALSE= +fi + +if test -z "${AMDEP_TRUE}" && test -z "${AMDEP_FALSE}"; then + as_fn_error $? "conditional \"AMDEP\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${am__fastdepCC_TRUE}" && test -z "${am__fastdepCC_FALSE}"; then + as_fn_error $? "conditional \"am__fastdepCC\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${am__fastdepCXX_TRUE}" && test -z "${am__fastdepCXX_FALSE}"; then + as_fn_error $? "conditional \"am__fastdepCXX\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi + +if test -z "${am__fastdepCC_TRUE}" && test -z "${am__fastdepCC_FALSE}"; then + as_fn_error $? "conditional \"am__fastdepCC\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${am__fastdepCXX_TRUE}" && test -z "${am__fastdepCXX_FALSE}"; then + as_fn_error $? "conditional \"am__fastdepCXX\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${am__fastdepCCAS_TRUE}" && test -z "${am__fastdepCCAS_FALSE}"; then + as_fn_error $? "conditional \"am__fastdepCCAS\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${DEBUG_TRUE}" && test -z "${DEBUG_FALSE}"; then + as_fn_error $? "conditional \"DEBUG\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_IPV6_TRUE}" && test -z "${BUILD_IPV6_FALSE}"; then + as_fn_error $? "conditional \"BUILD_IPV6\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_LEANPSK_TRUE}" && test -z "${BUILD_LEANPSK_FALSE}"; then + as_fn_error $? "conditional \"BUILD_LEANPSK\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_SNIFFER_TRUE}" && test -z "${BUILD_SNIFFER_FALSE}"; then + as_fn_error $? "conditional \"BUILD_SNIFFER\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_SNIFFTEST_TRUE}" && test -z "${BUILD_SNIFFTEST_FALSE}"; then + as_fn_error $? "conditional \"BUILD_SNIFFTEST\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_AESGCM_TRUE}" && test -z "${BUILD_AESGCM_FALSE}"; then + as_fn_error $? "conditional \"BUILD_AESGCM\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_AESCCM_TRUE}" && test -z "${BUILD_AESCCM_FALSE}"; then + as_fn_error $? "conditional \"BUILD_AESCCM\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_AESNI_TRUE}" && test -z "${BUILD_AESNI_FALSE}"; then + as_fn_error $? "conditional \"BUILD_AESNI\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_CAMELLIA_TRUE}" && test -z "${BUILD_CAMELLIA_FALSE}"; then + as_fn_error $? "conditional \"BUILD_CAMELLIA\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_MD2_TRUE}" && test -z "${BUILD_MD2_FALSE}"; then + as_fn_error $? "conditional \"BUILD_MD2\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_RIPEMD_TRUE}" && test -z "${BUILD_RIPEMD_FALSE}"; then + as_fn_error $? "conditional \"BUILD_RIPEMD\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_BLAKE2_TRUE}" && test -z "${BUILD_BLAKE2_FALSE}"; then + as_fn_error $? "conditional \"BUILD_BLAKE2\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_SHA512_TRUE}" && test -z "${BUILD_SHA512_FALSE}"; then + as_fn_error $? "conditional \"BUILD_SHA512\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_DSA_TRUE}" && test -z "${BUILD_DSA_FALSE}"; then + as_fn_error $? "conditional \"BUILD_DSA\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_ECC_TRUE}" && test -z "${BUILD_ECC_FALSE}"; then + as_fn_error $? "conditional \"BUILD_ECC\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_CURVE25519_TRUE}" && test -z "${BUILD_CURVE25519_FALSE}"; then + as_fn_error $? "conditional \"BUILD_CURVE25519\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_ED25519_TRUE}" && test -z "${BUILD_ED25519_FALSE}"; then + as_fn_error $? "conditional \"BUILD_ED25519\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_CURVED25519_SMALL_TRUE}" && test -z "${BUILD_CURVED25519_SMALL_FALSE}"; then + as_fn_error $? "conditional \"BUILD_CURVED25519_SMALL\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_FEMATH_TRUE}" && test -z "${BUILD_FEMATH_FALSE}"; then + as_fn_error $? "conditional \"BUILD_FEMATH\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_GEMATH_TRUE}" && test -z "${BUILD_GEMATH_FALSE}"; then + as_fn_error $? "conditional \"BUILD_GEMATH\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_MEMORY_TRUE}" && test -z "${BUILD_MEMORY_FALSE}"; then + as_fn_error $? "conditional \"BUILD_MEMORY\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_RSA_TRUE}" && test -z "${BUILD_RSA_FALSE}"; then + as_fn_error $? "conditional \"BUILD_RSA\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_DH_TRUE}" && test -z "${BUILD_DH_FALSE}"; then + as_fn_error $? "conditional \"BUILD_DH\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_ASN_TRUE}" && test -z "${BUILD_ASN_FALSE}"; then + as_fn_error $? "conditional \"BUILD_ASN\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_AES_TRUE}" && test -z "${BUILD_AES_FALSE}"; then + as_fn_error $? "conditional \"BUILD_AES\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_CODING_TRUE}" && test -z "${BUILD_CODING_FALSE}"; then + as_fn_error $? "conditional \"BUILD_CODING\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_DES3_TRUE}" && test -z "${BUILD_DES3_FALSE}"; then + as_fn_error $? "conditional \"BUILD_DES3\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_RC4_TRUE}" && test -z "${BUILD_RC4_FALSE}"; then + as_fn_error $? "conditional \"BUILD_RC4\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_MD5_TRUE}" && test -z "${BUILD_MD5_FALSE}"; then + as_fn_error $? "conditional \"BUILD_MD5\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_SHA_TRUE}" && test -z "${BUILD_SHA_FALSE}"; then + as_fn_error $? "conditional \"BUILD_SHA\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_MD4_TRUE}" && test -z "${BUILD_MD4_FALSE}"; then + as_fn_error $? "conditional \"BUILD_MD4\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_HC128_TRUE}" && test -z "${BUILD_HC128_FALSE}"; then + as_fn_error $? "conditional \"BUILD_HC128\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_RABBIT_TRUE}" && test -z "${BUILD_RABBIT_FALSE}"; then + as_fn_error $? "conditional \"BUILD_RABBIT\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_SHA512_TRUE}" && test -z "${BUILD_SHA512_FALSE}"; then + as_fn_error $? "conditional \"BUILD_SHA512\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_SHA512_TRUE}" && test -z "${BUILD_SHA512_FALSE}"; then + as_fn_error $? "conditional \"BUILD_SHA512\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_FIPS_TRUE}" && test -z "${BUILD_FIPS_FALSE}"; then + as_fn_error $? "conditional \"BUILD_FIPS\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_POLY1305_TRUE}" && test -z "${BUILD_POLY1305_FALSE}"; then + as_fn_error $? "conditional \"BUILD_POLY1305\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_CHACHA_TRUE}" && test -z "${BUILD_CHACHA_FALSE}"; then + as_fn_error $? "conditional \"BUILD_CHACHA\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_INLINE_TRUE}" && test -z "${BUILD_INLINE_FALSE}"; then + as_fn_error $? "conditional \"BUILD_INLINE\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_OCSP_TRUE}" && test -z "${BUILD_OCSP_FALSE}"; then + as_fn_error $? "conditional \"BUILD_OCSP\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_CRL_TRUE}" && test -z "${BUILD_CRL_FALSE}"; then + as_fn_error $? "conditional \"BUILD_CRL\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_CRL_MONITOR_TRUE}" && test -z "${BUILD_CRL_MONITOR_FALSE}"; then + as_fn_error $? "conditional \"BUILD_CRL_MONITOR\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_NTRU_TRUE}" && test -z "${BUILD_NTRU_FALSE}"; then + as_fn_error $? "conditional \"BUILD_NTRU\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_PKCS7_TRUE}" && test -z "${BUILD_PKCS7_FALSE}"; then + as_fn_error $? "conditional \"BUILD_PKCS7\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_PKCS7_TRUE}" && test -z "${BUILD_PKCS7_FALSE}"; then + as_fn_error $? "conditional \"BUILD_PKCS7\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${USE_VALGRIND_TRUE}" && test -z "${USE_VALGRIND_FALSE}"; then + as_fn_error $? "conditional \"USE_VALGRIND\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_ECC_TRUE}" && test -z "${BUILD_ECC_FALSE}"; then + as_fn_error $? "conditional \"BUILD_ECC\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_PWDBASED_TRUE}" && test -z "${BUILD_PWDBASED_FALSE}"; then + as_fn_error $? "conditional \"BUILD_PWDBASED\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_FASTMATH_TRUE}" && test -z "${BUILD_FASTMATH_FALSE}"; then + as_fn_error $? "conditional \"BUILD_FASTMATH\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_SLOWMATH_TRUE}" && test -z "${BUILD_SLOWMATH_FALSE}"; then + as_fn_error $? "conditional \"BUILD_SLOWMATH\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_EXAMPLES_TRUE}" && test -z "${BUILD_EXAMPLES_FALSE}"; then + as_fn_error $? "conditional \"BUILD_EXAMPLES\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_LIBZ_TRUE}" && test -z "${BUILD_LIBZ_FALSE}"; then + as_fn_error $? "conditional \"BUILD_LIBZ\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_MCAPI_TRUE}" && test -z "${BUILD_MCAPI_FALSE}"; then + as_fn_error $? "conditional \"BUILD_MCAPI\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_CRL_TRUE}" && test -z "${BUILD_CRL_FALSE}"; then + as_fn_error $? "conditional \"BUILD_CRL\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${BUILD_OCSP_TRUE}" && test -z "${BUILD_OCSP_FALSE}"; then + as_fn_error $? "conditional \"BUILD_OCSP\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${IS_VCS_CHECKOUT_TRUE}" && test -z "${IS_VCS_CHECKOUT_FALSE}"; then + as_fn_error $? "conditional \"IS_VCS_CHECKOUT\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi + +: "${CONFIG_STATUS=./config.status}" +ac_write_fail=0 +ac_clean_files_save=$ac_clean_files +ac_clean_files="$ac_clean_files $CONFIG_STATUS" +{ $as_echo "$as_me:${as_lineno-$LINENO}: creating $CONFIG_STATUS" >&5 +$as_echo "$as_me: creating $CONFIG_STATUS" >&6;} +as_write_fail=0 +cat >$CONFIG_STATUS <<_ASEOF || as_write_fail=1 +#! $SHELL +# Generated by $as_me. +# Run this file to recreate the current configuration. +# Compiler output produced by configure, useful for debugging +# configure, is in config.log if it exists. + +debug=false +ac_cs_recheck=false +ac_cs_silent=false + +SHELL=\${CONFIG_SHELL-$SHELL} +export SHELL +_ASEOF +cat >>$CONFIG_STATUS <<\_ASEOF || as_write_fail=1 +## -------------------- ## +## M4sh Initialization. ## +## -------------------- ## + +# Be more Bourne compatible +DUALCASE=1; export DUALCASE # for MKS sh +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi + + +as_nl=' +' +export as_nl +# Printing a long string crashes Solaris 7 /usr/bin/printf. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo +# Prefer a ksh shell builtin over an external printf program on Solaris, +# but without wasting forks for bash or zsh. +if test -z "$BASH_VERSION$ZSH_VERSION" \ + && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='print -r --' + as_echo_n='print -rn --' +elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='printf %s\n' + as_echo_n='printf %s' +else + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' + as_echo_n='/usr/ucb/echo -n' + else + as_echo_body='eval expr "X$1" : "X\\(.*\\)"' + as_echo_n_body='eval + arg=$1; + case $arg in #( + *"$as_nl"*) + expr "X$arg" : "X\\(.*\\)$as_nl"; + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; + esac; + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" + ' + export as_echo_n_body + as_echo_n='sh -c $as_echo_n_body as_echo' + fi + export as_echo_body + as_echo='sh -c $as_echo_body as_echo' +fi + +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + PATH_SEPARATOR=: + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || + PATH_SEPARATOR=';' + } +fi + + +# IFS +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent editors from complaining about space-tab. +# (If _AS_PATH_WALK were called with IFS unset, it would disable word +# splitting by setting IFS to empty value.) +IFS=" "" $as_nl" + +# Find who we are. Look in the path if we contain no directory separator. +as_myself= +case $0 in #(( + *[\\/]* ) as_myself=$0 ;; + *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + done +IFS=$as_save_IFS + + ;; +esac +# We did not find ourselves, most probably we were run as `sh COMMAND' +# in which case we are not to be found in the path. +if test "x$as_myself" = x; then + as_myself=$0 +fi +if test ! -f "$as_myself"; then + $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + exit 1 +fi + +# Unset variables that we do not need and which cause bugs (e.g. in +# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" +# suppresses any "Segmentation fault" message there. '((' could +# trigger a bug in pdksh 5.2.14. +for as_var in BASH_ENV ENV MAIL MAILPATH +do eval test x\${$as_var+set} = xset \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done +PS1='$ ' +PS2='> ' +PS4='+ ' + +# NLS nuisances. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# CDPATH. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + + +# as_fn_error STATUS ERROR [LINENO LOG_FD] +# ---------------------------------------- +# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are +# provided, also output the error to LOG_FD, referencing LINENO. Then exit the +# script with STATUS, using 1 if that was 0. +as_fn_error () +{ + as_status=$1; test $as_status -eq 0 && as_status=1 + if test "$4"; then + as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4 + fi + $as_echo "$as_me: error: $2" >&2 + as_fn_exit $as_status +} # as_fn_error + + +# as_fn_set_status STATUS +# ----------------------- +# Set $? to STATUS, without forking. +as_fn_set_status () +{ + return $1 +} # as_fn_set_status + +# as_fn_exit STATUS +# ----------------- +# Exit the shell with STATUS, even in a "trap 0" or "set -e" context. +as_fn_exit () +{ + set +e + as_fn_set_status $1 + exit $1 +} # as_fn_exit + +# as_fn_unset VAR +# --------------- +# Portably unset VAR. +as_fn_unset () +{ + { eval $1=; unset $1;} +} +as_unset=as_fn_unset +# as_fn_append VAR VALUE +# ---------------------- +# Append the text in VALUE to the end of the definition contained in VAR. Take +# advantage of any shell optimizations that allow amortized linear growth over +# repeated appends, instead of the typical quadratic growth present in naive +# implementations. +if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : + eval 'as_fn_append () + { + eval $1+=\$2 + }' +else + as_fn_append () + { + eval $1=\$$1\$2 + } +fi # as_fn_append + +# as_fn_arith ARG... +# ------------------ +# Perform arithmetic evaluation on the ARGs, and store the result in the +# global $as_val. Take advantage of shells that can avoid forks. The arguments +# must be portable across $(()) and expr. +if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : + eval 'as_fn_arith () + { + as_val=$(( $* )) + }' +else + as_fn_arith () + { + as_val=`expr "$@" || test $? -eq 1` + } +fi # as_fn_arith + + +if expr a : '\(a\)' >/dev/null 2>&1 && + test "X`expr 00001 : '.*\(...\)'`" = X001; then + as_expr=expr +else + as_expr=false +fi + +if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then + as_basename=basename +else + as_basename=false +fi + +if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then + as_dirname=dirname +else + as_dirname=false +fi + +as_me=`$as_basename -- "$0" || +$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \ + X"$0" : 'X\(//\)$' \| \ + X"$0" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X/"$0" | + sed '/^.*\/\([^/][^/]*\)\/*$/{ + s//\1/ + q + } + /^X\/\(\/\/\)$/{ + s//\1/ + q + } + /^X\/\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + +# Avoid depending upon Character Ranges. +as_cr_letters='abcdefghijklmnopqrstuvwxyz' +as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ' +as_cr_Letters=$as_cr_letters$as_cr_LETTERS +as_cr_digits='0123456789' +as_cr_alnum=$as_cr_Letters$as_cr_digits + +ECHO_C= ECHO_N= ECHO_T= +case `echo -n x` in #((((( +-n*) + case `echo 'xy\c'` in + *c*) ECHO_T=' ';; # ECHO_T is single tab character. + xy) ECHO_C='\c';; + *) echo `echo ksh88 bug on AIX 6.1` > /dev/null + ECHO_T=' ';; + esac;; +*) + ECHO_N='-n';; +esac + +rm -f conf$$ conf$$.exe conf$$.file +if test -d conf$$.dir; then + rm -f conf$$.dir/conf$$.file +else + rm -f conf$$.dir + mkdir conf$$.dir 2>/dev/null +fi +if (echo >conf$$.file) 2>/dev/null; then + if ln -s conf$$.file conf$$ 2>/dev/null; then + as_ln_s='ln -s' + # ... but there are two gotchas: + # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail. + # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable. + # In both cases, we have to default to `cp -pR'. + ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe || + as_ln_s='cp -pR' + elif ln conf$$.file conf$$ 2>/dev/null; then + as_ln_s=ln + else + as_ln_s='cp -pR' + fi +else + as_ln_s='cp -pR' +fi +rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file +rmdir conf$$.dir 2>/dev/null + + +# as_fn_mkdir_p +# ------------- +# Create "$as_dir" as a directory, including parents if necessary. +as_fn_mkdir_p () +{ + + case $as_dir in #( + -*) as_dir=./$as_dir;; + esac + test -d "$as_dir" || eval $as_mkdir_p || { + as_dirs= + while :; do + case $as_dir in #( + *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( + *) as_qdir=$as_dir;; + esac + as_dirs="'$as_qdir' $as_dirs" + as_dir=`$as_dirname -- "$as_dir" || +$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$as_dir" : 'X\(//\)[^/]' \| \ + X"$as_dir" : 'X\(//\)$' \| \ + X"$as_dir" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X"$as_dir" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + test -d "$as_dir" && break + done + test -z "$as_dirs" || eval "mkdir $as_dirs" + } || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir" + + +} # as_fn_mkdir_p +if mkdir -p . 2>/dev/null; then + as_mkdir_p='mkdir -p "$as_dir"' +else + test -d ./-p && rmdir ./-p + as_mkdir_p=false +fi + + +# as_fn_executable_p FILE +# ----------------------- +# Test if FILE is an executable regular file. +as_fn_executable_p () +{ + test -f "$1" && test -x "$1" +} # as_fn_executable_p +as_test_x='test -x' +as_executable_p=as_fn_executable_p + +# Sed expression to map a string onto a valid CPP name. +as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" + +# Sed expression to map a string onto a valid variable name. +as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" + + +exec 6>&1 +## ----------------------------------- ## +## Main body of $CONFIG_STATUS script. ## +## ----------------------------------- ## +_ASEOF +test $as_write_fail = 0 && chmod +x $CONFIG_STATUS || ac_write_fail=1 + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# Save the log message, to keep $0 and so on meaningful, and to +# report actual input values of CONFIG_FILES etc. instead of their +# values after options handling. +ac_log=" +This file was extended by wolfssl $as_me 3.6.0, which was +generated by GNU Autoconf 2.69. Invocation command line was + + CONFIG_FILES = $CONFIG_FILES + CONFIG_HEADERS = $CONFIG_HEADERS + CONFIG_LINKS = $CONFIG_LINKS + CONFIG_COMMANDS = $CONFIG_COMMANDS + $ $0 $@ + +on `(hostname || uname -n) 2>/dev/null | sed 1q` +" + +_ACEOF + +case $ac_config_files in *" +"*) set x $ac_config_files; shift; ac_config_files=$*;; +esac + +case $ac_config_headers in *" +"*) set x $ac_config_headers; shift; ac_config_headers=$*;; +esac + + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +# Files that config.status was made for. +config_files="$ac_config_files" +config_headers="$ac_config_headers" +config_commands="$ac_config_commands" + +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +ac_cs_usage="\ +\`$as_me' instantiates files and other configuration actions +from templates according to the current configuration. Unless the files +and actions are specified as TAGs, all are instantiated by default. + +Usage: $0 [OPTION]... [TAG]... + + -h, --help print this help, then exit + -V, --version print version number and configuration settings, then exit + --config print configuration, then exit + -q, --quiet, --silent + do not print progress messages + -d, --debug don't remove temporary files + --recheck update $as_me by reconfiguring in the same conditions + --file=FILE[:TEMPLATE] + instantiate the configuration file FILE + --header=FILE[:TEMPLATE] + instantiate the configuration header FILE + +Configuration files: +$config_files + +Configuration headers: +$config_headers + +Configuration commands: +$config_commands + +Report bugs to . +wolfssl home page: ." + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`" +ac_cs_version="\\ +wolfssl config.status 3.6.0 +configured by $0, generated by GNU Autoconf 2.69, + with options \\"\$ac_cs_config\\" + +Copyright (C) 2012 Free Software Foundation, Inc. +This config.status script is free software; the Free Software Foundation +gives unlimited permission to copy, distribute and modify it." + +ac_pwd='$ac_pwd' +srcdir='$srcdir' +INSTALL='$INSTALL' +MKDIR_P='$MKDIR_P' +AWK='$AWK' +test -n "\$AWK" || AWK=awk +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# The default lists apply if the user does not specify any file. +ac_need_defaults=: +while test $# != 0 +do + case $1 in + --*=?*) + ac_option=`expr "X$1" : 'X\([^=]*\)='` + ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'` + ac_shift=: + ;; + --*=) + ac_option=`expr "X$1" : 'X\([^=]*\)='` + ac_optarg= + ac_shift=: + ;; + *) + ac_option=$1 + ac_optarg=$2 + ac_shift=shift + ;; + esac + + case $ac_option in + # Handling of the options. + -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) + ac_cs_recheck=: ;; + --version | --versio | --versi | --vers | --ver | --ve | --v | -V ) + $as_echo "$ac_cs_version"; exit ;; + --config | --confi | --conf | --con | --co | --c ) + $as_echo "$ac_cs_config"; exit ;; + --debug | --debu | --deb | --de | --d | -d ) + debug=: ;; + --file | --fil | --fi | --f ) + $ac_shift + case $ac_optarg in + *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; + '') as_fn_error $? "missing file argument" ;; + esac + as_fn_append CONFIG_FILES " '$ac_optarg'" + ac_need_defaults=false;; + --header | --heade | --head | --hea ) + $ac_shift + case $ac_optarg in + *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; + esac + as_fn_append CONFIG_HEADERS " '$ac_optarg'" + ac_need_defaults=false;; + --he | --h) + # Conflict between --help and --header + as_fn_error $? "ambiguous option: \`$1' +Try \`$0 --help' for more information.";; + --help | --hel | -h ) + $as_echo "$ac_cs_usage"; exit ;; + -q | -quiet | --quiet | --quie | --qui | --qu | --q \ + | -silent | --silent | --silen | --sile | --sil | --si | --s) + ac_cs_silent=: ;; + + # This is an error. + -*) as_fn_error $? "unrecognized option: \`$1' +Try \`$0 --help' for more information." ;; + + *) as_fn_append ac_config_targets " $1" + ac_need_defaults=false ;; + + esac + shift +done + +ac_configure_extra_args= + +if $ac_cs_silent; then + exec 6>/dev/null + ac_configure_extra_args="$ac_configure_extra_args --silent" +fi + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +if \$ac_cs_recheck; then + set X $SHELL '$0' $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion + shift + \$as_echo "running CONFIG_SHELL=$SHELL \$*" >&6 + CONFIG_SHELL='$SHELL' + export CONFIG_SHELL + exec "\$@" +fi + +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +exec 5>>config.log +{ + echo + sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX +## Running $as_me. ## +_ASBOX + $as_echo "$ac_log" +} >&5 + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +# +# INIT-COMMANDS +# +AMDEP_TRUE="$AMDEP_TRUE" ac_aux_dir="$ac_aux_dir" + + +# The HP-UX ksh and POSIX shell print the target directory to stdout +# if CDPATH is set. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + +sed_quote_subst='$sed_quote_subst' +double_quote_subst='$double_quote_subst' +delay_variable_subst='$delay_variable_subst' +macro_version='`$ECHO "$macro_version" | $SED "$delay_single_quote_subst"`' +macro_revision='`$ECHO "$macro_revision" | $SED "$delay_single_quote_subst"`' +enable_static='`$ECHO "$enable_static" | $SED "$delay_single_quote_subst"`' +enable_shared='`$ECHO "$enable_shared" | $SED "$delay_single_quote_subst"`' +pic_mode='`$ECHO "$pic_mode" | $SED "$delay_single_quote_subst"`' +enable_fast_install='`$ECHO "$enable_fast_install" | $SED "$delay_single_quote_subst"`' +SHELL='`$ECHO "$SHELL" | $SED "$delay_single_quote_subst"`' +ECHO='`$ECHO "$ECHO" | $SED "$delay_single_quote_subst"`' +PATH_SEPARATOR='`$ECHO "$PATH_SEPARATOR" | $SED "$delay_single_quote_subst"`' +host_alias='`$ECHO "$host_alias" | $SED "$delay_single_quote_subst"`' +host='`$ECHO "$host" | $SED "$delay_single_quote_subst"`' +host_os='`$ECHO "$host_os" | $SED "$delay_single_quote_subst"`' +build_alias='`$ECHO "$build_alias" | $SED "$delay_single_quote_subst"`' +build='`$ECHO "$build" | $SED "$delay_single_quote_subst"`' +build_os='`$ECHO "$build_os" | $SED "$delay_single_quote_subst"`' +SED='`$ECHO "$SED" | $SED "$delay_single_quote_subst"`' +Xsed='`$ECHO "$Xsed" | $SED "$delay_single_quote_subst"`' +GREP='`$ECHO "$GREP" | $SED "$delay_single_quote_subst"`' +EGREP='`$ECHO "$EGREP" | $SED "$delay_single_quote_subst"`' +FGREP='`$ECHO "$FGREP" | $SED "$delay_single_quote_subst"`' +LD='`$ECHO "$LD" | $SED "$delay_single_quote_subst"`' +NM='`$ECHO "$NM" | $SED "$delay_single_quote_subst"`' +LN_S='`$ECHO "$LN_S" | $SED "$delay_single_quote_subst"`' +max_cmd_len='`$ECHO "$max_cmd_len" | $SED "$delay_single_quote_subst"`' +ac_objext='`$ECHO "$ac_objext" | $SED "$delay_single_quote_subst"`' +exeext='`$ECHO "$exeext" | $SED "$delay_single_quote_subst"`' +lt_unset='`$ECHO "$lt_unset" | $SED "$delay_single_quote_subst"`' +lt_SP2NL='`$ECHO "$lt_SP2NL" | $SED "$delay_single_quote_subst"`' +lt_NL2SP='`$ECHO "$lt_NL2SP" | $SED "$delay_single_quote_subst"`' +lt_cv_to_host_file_cmd='`$ECHO "$lt_cv_to_host_file_cmd" | $SED "$delay_single_quote_subst"`' +lt_cv_to_tool_file_cmd='`$ECHO "$lt_cv_to_tool_file_cmd" | $SED "$delay_single_quote_subst"`' +reload_flag='`$ECHO "$reload_flag" | $SED "$delay_single_quote_subst"`' +reload_cmds='`$ECHO "$reload_cmds" | $SED "$delay_single_quote_subst"`' +OBJDUMP='`$ECHO "$OBJDUMP" | $SED "$delay_single_quote_subst"`' +deplibs_check_method='`$ECHO "$deplibs_check_method" | $SED "$delay_single_quote_subst"`' +file_magic_cmd='`$ECHO "$file_magic_cmd" | $SED "$delay_single_quote_subst"`' +file_magic_glob='`$ECHO "$file_magic_glob" | $SED "$delay_single_quote_subst"`' +want_nocaseglob='`$ECHO "$want_nocaseglob" | $SED "$delay_single_quote_subst"`' +DLLTOOL='`$ECHO "$DLLTOOL" | $SED "$delay_single_quote_subst"`' +sharedlib_from_linklib_cmd='`$ECHO "$sharedlib_from_linklib_cmd" | $SED "$delay_single_quote_subst"`' +AR='`$ECHO "$AR" | $SED "$delay_single_quote_subst"`' +AR_FLAGS='`$ECHO "$AR_FLAGS" | $SED "$delay_single_quote_subst"`' +archiver_list_spec='`$ECHO "$archiver_list_spec" | $SED "$delay_single_quote_subst"`' +STRIP='`$ECHO "$STRIP" | $SED "$delay_single_quote_subst"`' +RANLIB='`$ECHO "$RANLIB" | $SED "$delay_single_quote_subst"`' +old_postinstall_cmds='`$ECHO "$old_postinstall_cmds" | $SED "$delay_single_quote_subst"`' +old_postuninstall_cmds='`$ECHO "$old_postuninstall_cmds" | $SED "$delay_single_quote_subst"`' +old_archive_cmds='`$ECHO "$old_archive_cmds" | $SED "$delay_single_quote_subst"`' +lock_old_archive_extraction='`$ECHO "$lock_old_archive_extraction" | $SED "$delay_single_quote_subst"`' +CC='`$ECHO "$CC" | $SED "$delay_single_quote_subst"`' +CFLAGS='`$ECHO "$CFLAGS" | $SED "$delay_single_quote_subst"`' +compiler='`$ECHO "$compiler" | $SED "$delay_single_quote_subst"`' +GCC='`$ECHO "$GCC" | $SED "$delay_single_quote_subst"`' +lt_cv_sys_global_symbol_pipe='`$ECHO "$lt_cv_sys_global_symbol_pipe" | $SED "$delay_single_quote_subst"`' +lt_cv_sys_global_symbol_to_cdecl='`$ECHO "$lt_cv_sys_global_symbol_to_cdecl" | $SED "$delay_single_quote_subst"`' +lt_cv_sys_global_symbol_to_c_name_address='`$ECHO "$lt_cv_sys_global_symbol_to_c_name_address" | $SED "$delay_single_quote_subst"`' +lt_cv_sys_global_symbol_to_c_name_address_lib_prefix='`$ECHO "$lt_cv_sys_global_symbol_to_c_name_address_lib_prefix" | $SED "$delay_single_quote_subst"`' +nm_file_list_spec='`$ECHO "$nm_file_list_spec" | $SED "$delay_single_quote_subst"`' +lt_sysroot='`$ECHO "$lt_sysroot" | $SED "$delay_single_quote_subst"`' +objdir='`$ECHO "$objdir" | $SED "$delay_single_quote_subst"`' +MAGIC_CMD='`$ECHO "$MAGIC_CMD" | $SED "$delay_single_quote_subst"`' +lt_prog_compiler_no_builtin_flag='`$ECHO "$lt_prog_compiler_no_builtin_flag" | $SED "$delay_single_quote_subst"`' +lt_prog_compiler_pic='`$ECHO "$lt_prog_compiler_pic" | $SED "$delay_single_quote_subst"`' +lt_prog_compiler_wl='`$ECHO "$lt_prog_compiler_wl" | $SED "$delay_single_quote_subst"`' +lt_prog_compiler_static='`$ECHO "$lt_prog_compiler_static" | $SED "$delay_single_quote_subst"`' +lt_cv_prog_compiler_c_o='`$ECHO "$lt_cv_prog_compiler_c_o" | $SED "$delay_single_quote_subst"`' +need_locks='`$ECHO "$need_locks" | $SED "$delay_single_quote_subst"`' +MANIFEST_TOOL='`$ECHO "$MANIFEST_TOOL" | $SED "$delay_single_quote_subst"`' +DSYMUTIL='`$ECHO "$DSYMUTIL" | $SED "$delay_single_quote_subst"`' +NMEDIT='`$ECHO "$NMEDIT" | $SED "$delay_single_quote_subst"`' +LIPO='`$ECHO "$LIPO" | $SED "$delay_single_quote_subst"`' +OTOOL='`$ECHO "$OTOOL" | $SED "$delay_single_quote_subst"`' +OTOOL64='`$ECHO "$OTOOL64" | $SED "$delay_single_quote_subst"`' +libext='`$ECHO "$libext" | $SED "$delay_single_quote_subst"`' +shrext_cmds='`$ECHO "$shrext_cmds" | $SED "$delay_single_quote_subst"`' +extract_expsyms_cmds='`$ECHO "$extract_expsyms_cmds" | $SED "$delay_single_quote_subst"`' +archive_cmds_need_lc='`$ECHO "$archive_cmds_need_lc" | $SED "$delay_single_quote_subst"`' +enable_shared_with_static_runtimes='`$ECHO "$enable_shared_with_static_runtimes" | $SED "$delay_single_quote_subst"`' +export_dynamic_flag_spec='`$ECHO "$export_dynamic_flag_spec" | $SED "$delay_single_quote_subst"`' +whole_archive_flag_spec='`$ECHO "$whole_archive_flag_spec" | $SED "$delay_single_quote_subst"`' +compiler_needs_object='`$ECHO "$compiler_needs_object" | $SED "$delay_single_quote_subst"`' +old_archive_from_new_cmds='`$ECHO "$old_archive_from_new_cmds" | $SED "$delay_single_quote_subst"`' +old_archive_from_expsyms_cmds='`$ECHO "$old_archive_from_expsyms_cmds" | $SED "$delay_single_quote_subst"`' +archive_cmds='`$ECHO "$archive_cmds" | $SED "$delay_single_quote_subst"`' +archive_expsym_cmds='`$ECHO "$archive_expsym_cmds" | $SED "$delay_single_quote_subst"`' +module_cmds='`$ECHO "$module_cmds" | $SED "$delay_single_quote_subst"`' +module_expsym_cmds='`$ECHO "$module_expsym_cmds" | $SED "$delay_single_quote_subst"`' +with_gnu_ld='`$ECHO "$with_gnu_ld" | $SED "$delay_single_quote_subst"`' +allow_undefined_flag='`$ECHO "$allow_undefined_flag" | $SED "$delay_single_quote_subst"`' +no_undefined_flag='`$ECHO "$no_undefined_flag" | $SED "$delay_single_quote_subst"`' +hardcode_libdir_flag_spec='`$ECHO "$hardcode_libdir_flag_spec" | $SED "$delay_single_quote_subst"`' +hardcode_libdir_separator='`$ECHO "$hardcode_libdir_separator" | $SED "$delay_single_quote_subst"`' +hardcode_direct='`$ECHO "$hardcode_direct" | $SED "$delay_single_quote_subst"`' +hardcode_direct_absolute='`$ECHO "$hardcode_direct_absolute" | $SED "$delay_single_quote_subst"`' +hardcode_minus_L='`$ECHO "$hardcode_minus_L" | $SED "$delay_single_quote_subst"`' +hardcode_shlibpath_var='`$ECHO "$hardcode_shlibpath_var" | $SED "$delay_single_quote_subst"`' +hardcode_automatic='`$ECHO "$hardcode_automatic" | $SED "$delay_single_quote_subst"`' +inherit_rpath='`$ECHO "$inherit_rpath" | $SED "$delay_single_quote_subst"`' +link_all_deplibs='`$ECHO "$link_all_deplibs" | $SED "$delay_single_quote_subst"`' +always_export_symbols='`$ECHO "$always_export_symbols" | $SED "$delay_single_quote_subst"`' +export_symbols_cmds='`$ECHO "$export_symbols_cmds" | $SED "$delay_single_quote_subst"`' +exclude_expsyms='`$ECHO "$exclude_expsyms" | $SED "$delay_single_quote_subst"`' +include_expsyms='`$ECHO "$include_expsyms" | $SED "$delay_single_quote_subst"`' +prelink_cmds='`$ECHO "$prelink_cmds" | $SED "$delay_single_quote_subst"`' +postlink_cmds='`$ECHO "$postlink_cmds" | $SED "$delay_single_quote_subst"`' +file_list_spec='`$ECHO "$file_list_spec" | $SED "$delay_single_quote_subst"`' +variables_saved_for_relink='`$ECHO "$variables_saved_for_relink" | $SED "$delay_single_quote_subst"`' +need_lib_prefix='`$ECHO "$need_lib_prefix" | $SED "$delay_single_quote_subst"`' +need_version='`$ECHO "$need_version" | $SED "$delay_single_quote_subst"`' +version_type='`$ECHO "$version_type" | $SED "$delay_single_quote_subst"`' +runpath_var='`$ECHO "$runpath_var" | $SED "$delay_single_quote_subst"`' +shlibpath_var='`$ECHO "$shlibpath_var" | $SED "$delay_single_quote_subst"`' +shlibpath_overrides_runpath='`$ECHO "$shlibpath_overrides_runpath" | $SED "$delay_single_quote_subst"`' +libname_spec='`$ECHO "$libname_spec" | $SED "$delay_single_quote_subst"`' +library_names_spec='`$ECHO "$library_names_spec" | $SED "$delay_single_quote_subst"`' +soname_spec='`$ECHO "$soname_spec" | $SED "$delay_single_quote_subst"`' +install_override_mode='`$ECHO "$install_override_mode" | $SED "$delay_single_quote_subst"`' +postinstall_cmds='`$ECHO "$postinstall_cmds" | $SED "$delay_single_quote_subst"`' +postuninstall_cmds='`$ECHO "$postuninstall_cmds" | $SED "$delay_single_quote_subst"`' +finish_cmds='`$ECHO "$finish_cmds" | $SED "$delay_single_quote_subst"`' +finish_eval='`$ECHO "$finish_eval" | $SED "$delay_single_quote_subst"`' +hardcode_into_libs='`$ECHO "$hardcode_into_libs" | $SED "$delay_single_quote_subst"`' +sys_lib_search_path_spec='`$ECHO "$sys_lib_search_path_spec" | $SED "$delay_single_quote_subst"`' +sys_lib_dlsearch_path_spec='`$ECHO "$sys_lib_dlsearch_path_spec" | $SED "$delay_single_quote_subst"`' +hardcode_action='`$ECHO "$hardcode_action" | $SED "$delay_single_quote_subst"`' +enable_dlopen='`$ECHO "$enable_dlopen" | $SED "$delay_single_quote_subst"`' +enable_dlopen_self='`$ECHO "$enable_dlopen_self" | $SED "$delay_single_quote_subst"`' +enable_dlopen_self_static='`$ECHO "$enable_dlopen_self_static" | $SED "$delay_single_quote_subst"`' +old_striplib='`$ECHO "$old_striplib" | $SED "$delay_single_quote_subst"`' +striplib='`$ECHO "$striplib" | $SED "$delay_single_quote_subst"`' +compiler_lib_search_dirs='`$ECHO "$compiler_lib_search_dirs" | $SED "$delay_single_quote_subst"`' +predep_objects='`$ECHO "$predep_objects" | $SED "$delay_single_quote_subst"`' +postdep_objects='`$ECHO "$postdep_objects" | $SED "$delay_single_quote_subst"`' +predeps='`$ECHO "$predeps" | $SED "$delay_single_quote_subst"`' +postdeps='`$ECHO "$postdeps" | $SED "$delay_single_quote_subst"`' +compiler_lib_search_path='`$ECHO "$compiler_lib_search_path" | $SED "$delay_single_quote_subst"`' +LD_CXX='`$ECHO "$LD_CXX" | $SED "$delay_single_quote_subst"`' +reload_flag_CXX='`$ECHO "$reload_flag_CXX" | $SED "$delay_single_quote_subst"`' +reload_cmds_CXX='`$ECHO "$reload_cmds_CXX" | $SED "$delay_single_quote_subst"`' +old_archive_cmds_CXX='`$ECHO "$old_archive_cmds_CXX" | $SED "$delay_single_quote_subst"`' +compiler_CXX='`$ECHO "$compiler_CXX" | $SED "$delay_single_quote_subst"`' +GCC_CXX='`$ECHO "$GCC_CXX" | $SED "$delay_single_quote_subst"`' +lt_prog_compiler_no_builtin_flag_CXX='`$ECHO "$lt_prog_compiler_no_builtin_flag_CXX" | $SED "$delay_single_quote_subst"`' +lt_prog_compiler_pic_CXX='`$ECHO "$lt_prog_compiler_pic_CXX" | $SED "$delay_single_quote_subst"`' +lt_prog_compiler_wl_CXX='`$ECHO "$lt_prog_compiler_wl_CXX" | $SED "$delay_single_quote_subst"`' +lt_prog_compiler_static_CXX='`$ECHO "$lt_prog_compiler_static_CXX" | $SED "$delay_single_quote_subst"`' +lt_cv_prog_compiler_c_o_CXX='`$ECHO "$lt_cv_prog_compiler_c_o_CXX" | $SED "$delay_single_quote_subst"`' +archive_cmds_need_lc_CXX='`$ECHO "$archive_cmds_need_lc_CXX" | $SED "$delay_single_quote_subst"`' +enable_shared_with_static_runtimes_CXX='`$ECHO "$enable_shared_with_static_runtimes_CXX" | $SED "$delay_single_quote_subst"`' +export_dynamic_flag_spec_CXX='`$ECHO "$export_dynamic_flag_spec_CXX" | $SED "$delay_single_quote_subst"`' +whole_archive_flag_spec_CXX='`$ECHO "$whole_archive_flag_spec_CXX" | $SED "$delay_single_quote_subst"`' +compiler_needs_object_CXX='`$ECHO "$compiler_needs_object_CXX" | $SED "$delay_single_quote_subst"`' +old_archive_from_new_cmds_CXX='`$ECHO "$old_archive_from_new_cmds_CXX" | $SED "$delay_single_quote_subst"`' +old_archive_from_expsyms_cmds_CXX='`$ECHO "$old_archive_from_expsyms_cmds_CXX" | $SED "$delay_single_quote_subst"`' +archive_cmds_CXX='`$ECHO "$archive_cmds_CXX" | $SED "$delay_single_quote_subst"`' +archive_expsym_cmds_CXX='`$ECHO "$archive_expsym_cmds_CXX" | $SED "$delay_single_quote_subst"`' +module_cmds_CXX='`$ECHO "$module_cmds_CXX" | $SED "$delay_single_quote_subst"`' +module_expsym_cmds_CXX='`$ECHO "$module_expsym_cmds_CXX" | $SED "$delay_single_quote_subst"`' +with_gnu_ld_CXX='`$ECHO "$with_gnu_ld_CXX" | $SED "$delay_single_quote_subst"`' +allow_undefined_flag_CXX='`$ECHO "$allow_undefined_flag_CXX" | $SED "$delay_single_quote_subst"`' +no_undefined_flag_CXX='`$ECHO "$no_undefined_flag_CXX" | $SED "$delay_single_quote_subst"`' +hardcode_libdir_flag_spec_CXX='`$ECHO "$hardcode_libdir_flag_spec_CXX" | $SED "$delay_single_quote_subst"`' +hardcode_libdir_separator_CXX='`$ECHO "$hardcode_libdir_separator_CXX" | $SED "$delay_single_quote_subst"`' +hardcode_direct_CXX='`$ECHO "$hardcode_direct_CXX" | $SED "$delay_single_quote_subst"`' +hardcode_direct_absolute_CXX='`$ECHO "$hardcode_direct_absolute_CXX" | $SED "$delay_single_quote_subst"`' +hardcode_minus_L_CXX='`$ECHO "$hardcode_minus_L_CXX" | $SED "$delay_single_quote_subst"`' +hardcode_shlibpath_var_CXX='`$ECHO "$hardcode_shlibpath_var_CXX" | $SED "$delay_single_quote_subst"`' +hardcode_automatic_CXX='`$ECHO "$hardcode_automatic_CXX" | $SED "$delay_single_quote_subst"`' +inherit_rpath_CXX='`$ECHO "$inherit_rpath_CXX" | $SED "$delay_single_quote_subst"`' +link_all_deplibs_CXX='`$ECHO "$link_all_deplibs_CXX" | $SED "$delay_single_quote_subst"`' +always_export_symbols_CXX='`$ECHO "$always_export_symbols_CXX" | $SED "$delay_single_quote_subst"`' +export_symbols_cmds_CXX='`$ECHO "$export_symbols_cmds_CXX" | $SED "$delay_single_quote_subst"`' +exclude_expsyms_CXX='`$ECHO "$exclude_expsyms_CXX" | $SED "$delay_single_quote_subst"`' +include_expsyms_CXX='`$ECHO "$include_expsyms_CXX" | $SED "$delay_single_quote_subst"`' +prelink_cmds_CXX='`$ECHO "$prelink_cmds_CXX" | $SED "$delay_single_quote_subst"`' +postlink_cmds_CXX='`$ECHO "$postlink_cmds_CXX" | $SED "$delay_single_quote_subst"`' +file_list_spec_CXX='`$ECHO "$file_list_spec_CXX" | $SED "$delay_single_quote_subst"`' +hardcode_action_CXX='`$ECHO "$hardcode_action_CXX" | $SED "$delay_single_quote_subst"`' +compiler_lib_search_dirs_CXX='`$ECHO "$compiler_lib_search_dirs_CXX" | $SED "$delay_single_quote_subst"`' +predep_objects_CXX='`$ECHO "$predep_objects_CXX" | $SED "$delay_single_quote_subst"`' +postdep_objects_CXX='`$ECHO "$postdep_objects_CXX" | $SED "$delay_single_quote_subst"`' +predeps_CXX='`$ECHO "$predeps_CXX" | $SED "$delay_single_quote_subst"`' +postdeps_CXX='`$ECHO "$postdeps_CXX" | $SED "$delay_single_quote_subst"`' +compiler_lib_search_path_CXX='`$ECHO "$compiler_lib_search_path_CXX" | $SED "$delay_single_quote_subst"`' + +LTCC='$LTCC' +LTCFLAGS='$LTCFLAGS' +compiler='$compiler_DEFAULT' + +# A function that is used when there is no print builtin or printf. +func_fallback_echo () +{ + eval 'cat <<_LTECHO_EOF +\$1 +_LTECHO_EOF' +} + +# Quote evaled strings. +for var in SHELL \ +ECHO \ +PATH_SEPARATOR \ +SED \ +GREP \ +EGREP \ +FGREP \ +LD \ +NM \ +LN_S \ +lt_SP2NL \ +lt_NL2SP \ +reload_flag \ +OBJDUMP \ +deplibs_check_method \ +file_magic_cmd \ +file_magic_glob \ +want_nocaseglob \ +DLLTOOL \ +sharedlib_from_linklib_cmd \ +AR \ +AR_FLAGS \ +archiver_list_spec \ +STRIP \ +RANLIB \ +CC \ +CFLAGS \ +compiler \ +lt_cv_sys_global_symbol_pipe \ +lt_cv_sys_global_symbol_to_cdecl \ +lt_cv_sys_global_symbol_to_c_name_address \ +lt_cv_sys_global_symbol_to_c_name_address_lib_prefix \ +nm_file_list_spec \ +lt_prog_compiler_no_builtin_flag \ +lt_prog_compiler_pic \ +lt_prog_compiler_wl \ +lt_prog_compiler_static \ +lt_cv_prog_compiler_c_o \ +need_locks \ +MANIFEST_TOOL \ +DSYMUTIL \ +NMEDIT \ +LIPO \ +OTOOL \ +OTOOL64 \ +shrext_cmds \ +export_dynamic_flag_spec \ +whole_archive_flag_spec \ +compiler_needs_object \ +with_gnu_ld \ +allow_undefined_flag \ +no_undefined_flag \ +hardcode_libdir_flag_spec \ +hardcode_libdir_separator \ +exclude_expsyms \ +include_expsyms \ +file_list_spec \ +variables_saved_for_relink \ +libname_spec \ +library_names_spec \ +soname_spec \ +install_override_mode \ +finish_eval \ +old_striplib \ +striplib \ +compiler_lib_search_dirs \ +predep_objects \ +postdep_objects \ +predeps \ +postdeps \ +compiler_lib_search_path \ +LD_CXX \ +reload_flag_CXX \ +compiler_CXX \ +lt_prog_compiler_no_builtin_flag_CXX \ +lt_prog_compiler_pic_CXX \ +lt_prog_compiler_wl_CXX \ +lt_prog_compiler_static_CXX \ +lt_cv_prog_compiler_c_o_CXX \ +export_dynamic_flag_spec_CXX \ +whole_archive_flag_spec_CXX \ +compiler_needs_object_CXX \ +with_gnu_ld_CXX \ +allow_undefined_flag_CXX \ +no_undefined_flag_CXX \ +hardcode_libdir_flag_spec_CXX \ +hardcode_libdir_separator_CXX \ +exclude_expsyms_CXX \ +include_expsyms_CXX \ +file_list_spec_CXX \ +compiler_lib_search_dirs_CXX \ +predep_objects_CXX \ +postdep_objects_CXX \ +predeps_CXX \ +postdeps_CXX \ +compiler_lib_search_path_CXX; do + case \`eval \\\\\$ECHO \\\\""\\\\\$\$var"\\\\"\` in + *[\\\\\\\`\\"\\\$]*) + eval "lt_\$var=\\\\\\"\\\`\\\$ECHO \\"\\\$\$var\\" | \\\$SED \\"\\\$sed_quote_subst\\"\\\`\\\\\\"" + ;; + *) + eval "lt_\$var=\\\\\\"\\\$\$var\\\\\\"" + ;; + esac +done + +# Double-quote double-evaled strings. +for var in reload_cmds \ +old_postinstall_cmds \ +old_postuninstall_cmds \ +old_archive_cmds \ +extract_expsyms_cmds \ +old_archive_from_new_cmds \ +old_archive_from_expsyms_cmds \ +archive_cmds \ +archive_expsym_cmds \ +module_cmds \ +module_expsym_cmds \ +export_symbols_cmds \ +prelink_cmds \ +postlink_cmds \ +postinstall_cmds \ +postuninstall_cmds \ +finish_cmds \ +sys_lib_search_path_spec \ +sys_lib_dlsearch_path_spec \ +reload_cmds_CXX \ +old_archive_cmds_CXX \ +old_archive_from_new_cmds_CXX \ +old_archive_from_expsyms_cmds_CXX \ +archive_cmds_CXX \ +archive_expsym_cmds_CXX \ +module_cmds_CXX \ +module_expsym_cmds_CXX \ +export_symbols_cmds_CXX \ +prelink_cmds_CXX \ +postlink_cmds_CXX; do + case \`eval \\\\\$ECHO \\\\""\\\\\$\$var"\\\\"\` in + *[\\\\\\\`\\"\\\$]*) + eval "lt_\$var=\\\\\\"\\\`\\\$ECHO \\"\\\$\$var\\" | \\\$SED -e \\"\\\$double_quote_subst\\" -e \\"\\\$sed_quote_subst\\" -e \\"\\\$delay_variable_subst\\"\\\`\\\\\\"" + ;; + *) + eval "lt_\$var=\\\\\\"\\\$\$var\\\\\\"" + ;; + esac +done + +ac_aux_dir='$ac_aux_dir' +xsi_shell='$xsi_shell' +lt_shell_append='$lt_shell_append' + +# See if we are running on zsh, and set the options which allow our +# commands through without removal of \ escapes INIT. +if test -n "\${ZSH_VERSION+set}" ; then + setopt NO_GLOB_SUBST +fi + + + PACKAGE='$PACKAGE' + VERSION='$VERSION' + TIMESTAMP='$TIMESTAMP' + RM='$RM' + ofile='$ofile' + + + + + + +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + +# Handling of arguments. +for ac_config_target in $ac_config_targets +do + case $ac_config_target in + "config.h") CONFIG_HEADERS="$CONFIG_HEADERS config.h:config.in" ;; + "depfiles") CONFIG_COMMANDS="$CONFIG_COMMANDS depfiles" ;; + "libtool") CONFIG_COMMANDS="$CONFIG_COMMANDS libtool" ;; + "stamp-h") CONFIG_FILES="$CONFIG_FILES stamp-h" ;; + "Makefile") CONFIG_FILES="$CONFIG_FILES Makefile" ;; + "wolfssl/version.h") CONFIG_FILES="$CONFIG_FILES wolfssl/version.h" ;; + "wolfssl/options.h") CONFIG_FILES="$CONFIG_FILES wolfssl/options.h" ;; + "support/wolfssl.pc") CONFIG_FILES="$CONFIG_FILES support/wolfssl.pc" ;; + "rpm/spec") CONFIG_FILES="$CONFIG_FILES rpm/spec" ;; + + *) as_fn_error $? "invalid argument: \`$ac_config_target'" "$LINENO" 5;; + esac +done + + +# If the user did not use the arguments to specify the items to instantiate, +# then the envvar interface is used. Set only those that are not. +# We use the long form for the default assignment because of an extremely +# bizarre bug on SunOS 4.1.3. +if $ac_need_defaults; then + test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files + test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers + test "${CONFIG_COMMANDS+set}" = set || CONFIG_COMMANDS=$config_commands +fi + +# Have a temporary directory for convenience. Make it in the build tree +# simply because there is no reason against having it here, and in addition, +# creating and moving files from /tmp can sometimes cause problems. +# Hook for its removal unless debugging. +# Note that there is a small window in which the directory will not be cleaned: +# after its creation but before its name has been assigned to `$tmp'. +$debug || +{ + tmp= ac_tmp= + trap 'exit_status=$? + : "${ac_tmp:=$tmp}" + { test ! -d "$ac_tmp" || rm -fr "$ac_tmp"; } && exit $exit_status +' 0 + trap 'as_fn_exit 1' 1 2 13 15 +} +# Create a (secure) tmp directory for tmp files. + +{ + tmp=`(umask 077 && mktemp -d "./confXXXXXX") 2>/dev/null` && + test -d "$tmp" +} || +{ + tmp=./conf$$-$RANDOM + (umask 077 && mkdir "$tmp") +} || as_fn_error $? "cannot create a temporary directory in ." "$LINENO" 5 +ac_tmp=$tmp + +# Set up the scripts for CONFIG_FILES section. +# No need to generate them if there are no CONFIG_FILES. +# This happens for instance with `./config.status config.h'. +if test -n "$CONFIG_FILES"; then + + +ac_cr=`echo X | tr X '\015'` +# On cygwin, bash can eat \r inside `` if the user requested igncr. +# But we know of no other shell where ac_cr would be empty at this +# point, so we can use a bashism as a fallback. +if test "x$ac_cr" = x; then + eval ac_cr=\$\'\\r\' +fi +ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' /dev/null` +if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then + ac_cs_awk_cr='\\r' +else + ac_cs_awk_cr=$ac_cr +fi + +echo 'BEGIN {' >"$ac_tmp/subs1.awk" && +_ACEOF + + +{ + echo "cat >conf$$subs.awk <<_ACEOF" && + echo "$ac_subst_vars" | sed 's/.*/&!$&$ac_delim/' && + echo "_ACEOF" +} >conf$$subs.sh || + as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5 +ac_delim_num=`echo "$ac_subst_vars" | grep -c '^'` +ac_delim='%!_!# ' +for ac_last_try in false false false false false :; do + . ./conf$$subs.sh || + as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5 + + ac_delim_n=`sed -n "s/.*$ac_delim\$/X/p" conf$$subs.awk | grep -c X` + if test $ac_delim_n = $ac_delim_num; then + break + elif $ac_last_try; then + as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5 + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! " + fi +done +rm -f conf$$subs.sh + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +cat >>"\$ac_tmp/subs1.awk" <<\\_ACAWK && +_ACEOF +sed -n ' +h +s/^/S["/; s/!.*/"]=/ +p +g +s/^[^!]*!// +:repl +t repl +s/'"$ac_delim"'$// +t delim +:nl +h +s/\(.\{148\}\)..*/\1/ +t more1 +s/["\\]/\\&/g; s/^/"/; s/$/\\n"\\/ +p +n +b repl +:more1 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t nl +:delim +h +s/\(.\{148\}\)..*/\1/ +t more2 +s/["\\]/\\&/g; s/^/"/; s/$/"/ +p +b +:more2 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t delim +' >$CONFIG_STATUS || ac_write_fail=1 +rm -f conf$$subs.awk +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +_ACAWK +cat >>"\$ac_tmp/subs1.awk" <<_ACAWK && + for (key in S) S_is_set[key] = 1 + FS = "" + +} +{ + line = $ 0 + nfields = split(line, field, "@") + substed = 0 + len = length(field[1]) + for (i = 2; i < nfields; i++) { + key = field[i] + keylen = length(key) + if (S_is_set[key]) { + value = S[key] + line = substr(line, 1, len) "" value "" substr(line, len + keylen + 3) + len += length(value) + length(field[++i]) + substed = 1 + } else + len += 1 + keylen + } + + print line +} + +_ACAWK +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then + sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g" +else + cat +fi < "$ac_tmp/subs1.awk" > "$ac_tmp/subs.awk" \ + || as_fn_error $? "could not setup config files machinery" "$LINENO" 5 +_ACEOF + +# VPATH may cause trouble with some makes, so we remove sole $(srcdir), +# ${srcdir} and @srcdir@ entries from VPATH if srcdir is ".", strip leading and +# trailing colons and then remove the whole line if VPATH becomes empty +# (actually we leave an empty line to preserve line numbers). +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=[ ]*/{ +h +s/// +s/^/:/ +s/[ ]*$/:/ +s/:\$(srcdir):/:/g +s/:\${srcdir}:/:/g +s/:@srcdir@:/:/g +s/^:*// +s/:*$// +x +s/\(=[ ]*\).*/\1/ +G +s/\n// +s/^[^=]*=[ ]*$// +}' +fi + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +fi # test -n "$CONFIG_FILES" + +# Set up the scripts for CONFIG_HEADERS section. +# No need to generate them if there are no CONFIG_HEADERS. +# This happens for instance with `./config.status Makefile'. +if test -n "$CONFIG_HEADERS"; then +cat >"$ac_tmp/defines.awk" <<\_ACAWK || +BEGIN { +_ACEOF + +# Transform confdefs.h into an awk script `defines.awk', embedded as +# here-document in config.status, that substitutes the proper values into +# config.h.in to produce config.h. + +# Create a delimiter string that does not exist in confdefs.h, to ease +# handling of long lines. +ac_delim='%!_!# ' +for ac_last_try in false false :; do + ac_tt=`sed -n "/$ac_delim/p" confdefs.h` + if test -z "$ac_tt"; then + break + elif $ac_last_try; then + as_fn_error $? "could not make $CONFIG_HEADERS" "$LINENO" 5 + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! " + fi +done + +# For the awk script, D is an array of macro values keyed by name, +# likewise P contains macro parameters if any. Preserve backslash +# newline sequences. + +ac_word_re=[_$as_cr_Letters][_$as_cr_alnum]* +sed -n ' +s/.\{148\}/&'"$ac_delim"'/g +t rset +:rset +s/^[ ]*#[ ]*define[ ][ ]*/ / +t def +d +:def +s/\\$// +t bsnl +s/["\\]/\\&/g +s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\ +D["\1"]=" \3"/p +s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2"/p +d +:bsnl +s/["\\]/\\&/g +s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\ +D["\1"]=" \3\\\\\\n"\\/p +t cont +s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2\\\\\\n"\\/p +t cont +d +:cont +n +s/.\{148\}/&'"$ac_delim"'/g +t clear +:clear +s/\\$// +t bsnlc +s/["\\]/\\&/g; s/^/"/; s/$/"/p +d +:bsnlc +s/["\\]/\\&/g; s/^/"/; s/$/\\\\\\n"\\/p +b cont +' >$CONFIG_STATUS || ac_write_fail=1 + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 + for (key in D) D_is_set[key] = 1 + FS = "" +} +/^[\t ]*#[\t ]*(define|undef)[\t ]+$ac_word_re([\t (]|\$)/ { + line = \$ 0 + split(line, arg, " ") + if (arg[1] == "#") { + defundef = arg[2] + mac1 = arg[3] + } else { + defundef = substr(arg[1], 2) + mac1 = arg[2] + } + split(mac1, mac2, "(") #) + macro = mac2[1] + prefix = substr(line, 1, index(line, defundef) - 1) + if (D_is_set[macro]) { + # Preserve the white space surrounding the "#". + print prefix "define", macro P[macro] D[macro] + next + } else { + # Replace #undef with comments. This is necessary, for example, + # in the case of _POSIX_SOURCE, which is predefined and required + # on some systems where configure will not decide to define it. + if (defundef == "undef") { + print "/*", prefix defundef, macro, "*/" + next + } + } +} +{ print } +_ACAWK +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + as_fn_error $? "could not setup config headers machinery" "$LINENO" 5 +fi # test -n "$CONFIG_HEADERS" + + +eval set X " :F $CONFIG_FILES :H $CONFIG_HEADERS :C $CONFIG_COMMANDS" +shift +for ac_tag +do + case $ac_tag in + :[FHLC]) ac_mode=$ac_tag; continue;; + esac + case $ac_mode$ac_tag in + :[FHL]*:*);; + :L* | :C*:*) as_fn_error $? "invalid tag \`$ac_tag'" "$LINENO" 5;; + :[FH]-) ac_tag=-:-;; + :[FH]*) ac_tag=$ac_tag:$ac_tag.in;; + esac + ac_save_IFS=$IFS + IFS=: + set x $ac_tag + IFS=$ac_save_IFS + shift + ac_file=$1 + shift + + case $ac_mode in + :L) ac_source=$1;; + :[FH]) + ac_file_inputs= + for ac_f + do + case $ac_f in + -) ac_f="$ac_tmp/stdin";; + *) # Look for the file first in the build tree, then in the source tree + # (if the path is not absolute). The absolute path cannot be DOS-style, + # because $ac_f cannot contain `:'. + test -f "$ac_f" || + case $ac_f in + [\\/$]*) false;; + *) test -f "$srcdir/$ac_f" && ac_f="$srcdir/$ac_f";; + esac || + as_fn_error 1 "cannot find input file: \`$ac_f'" "$LINENO" 5;; + esac + case $ac_f in *\'*) ac_f=`$as_echo "$ac_f" | sed "s/'/'\\\\\\\\''/g"`;; esac + as_fn_append ac_file_inputs " '$ac_f'" + done + + # Let's still pretend it is `configure' which instantiates (i.e., don't + # use $as_me), people would be surprised to read: + # /* config.h. Generated by config.status. */ + configure_input='Generated from '` + $as_echo "$*" | sed 's|^[^:]*/||;s|:[^:]*/|, |g' + `' by configure.' + if test x"$ac_file" != x-; then + configure_input="$ac_file. $configure_input" + { $as_echo "$as_me:${as_lineno-$LINENO}: creating $ac_file" >&5 +$as_echo "$as_me: creating $ac_file" >&6;} + fi + # Neutralize special characters interpreted by sed in replacement strings. + case $configure_input in #( + *\&* | *\|* | *\\* ) + ac_sed_conf_input=`$as_echo "$configure_input" | + sed 's/[\\\\&|]/\\\\&/g'`;; #( + *) ac_sed_conf_input=$configure_input;; + esac + + case $ac_tag in + *:-:* | *:-) cat >"$ac_tmp/stdin" \ + || as_fn_error $? "could not create $ac_file" "$LINENO" 5 ;; + esac + ;; + esac + + ac_dir=`$as_dirname -- "$ac_file" || +$as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$ac_file" : 'X\(//\)[^/]' \| \ + X"$ac_file" : 'X\(//\)$' \| \ + X"$ac_file" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X"$ac_file" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + as_dir="$ac_dir"; as_fn_mkdir_p + ac_builddir=. + +case "$ac_dir" in +.) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;; +*) + ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'` + # A ".." for each directory in $ac_dir_suffix. + ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'` + case $ac_top_builddir_sub in + "") ac_top_builddir_sub=. ac_top_build_prefix= ;; + *) ac_top_build_prefix=$ac_top_builddir_sub/ ;; + esac ;; +esac +ac_abs_top_builddir=$ac_pwd +ac_abs_builddir=$ac_pwd$ac_dir_suffix +# for backward compatibility: +ac_top_builddir=$ac_top_build_prefix + +case $srcdir in + .) # We are building in place. + ac_srcdir=. + ac_top_srcdir=$ac_top_builddir_sub + ac_abs_top_srcdir=$ac_pwd ;; + [\\/]* | ?:[\\/]* ) # Absolute name. + ac_srcdir=$srcdir$ac_dir_suffix; + ac_top_srcdir=$srcdir + ac_abs_top_srcdir=$srcdir ;; + *) # Relative name. + ac_srcdir=$ac_top_build_prefix$srcdir$ac_dir_suffix + ac_top_srcdir=$ac_top_build_prefix$srcdir + ac_abs_top_srcdir=$ac_pwd/$srcdir ;; +esac +ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix + + + case $ac_mode in + :F) + # + # CONFIG_FILE + # + + case $INSTALL in + [\\/$]* | ?:[\\/]* ) ac_INSTALL=$INSTALL ;; + *) ac_INSTALL=$ac_top_build_prefix$INSTALL ;; + esac + ac_MKDIR_P=$MKDIR_P + case $MKDIR_P in + [\\/$]* | ?:[\\/]* ) ;; + */*) ac_MKDIR_P=$ac_top_build_prefix$MKDIR_P ;; + esac +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# If the template does not know about datarootdir, expand it. +# FIXME: This hack should be removed a few years after 2.60. +ac_datarootdir_hack=; ac_datarootdir_seen= +ac_sed_dataroot=' +/datarootdir/ { + p + q +} +/@datadir@/p +/@docdir@/p +/@infodir@/p +/@localedir@/p +/@mandir@/p' +case `eval "sed -n \"\$ac_sed_dataroot\" $ac_file_inputs"` in +*datarootdir*) ac_datarootdir_seen=yes;; +*@datadir@*|*@docdir@*|*@infodir@*|*@localedir@*|*@mandir@*) + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&5 +$as_echo "$as_me: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&2;} +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 + ac_datarootdir_hack=' + s&@datadir@&$datadir&g + s&@docdir@&$docdir&g + s&@infodir@&$infodir&g + s&@localedir@&$localedir&g + s&@mandir@&$mandir&g + s&\\\${datarootdir}&$datarootdir&g' ;; +esac +_ACEOF + +# Neutralize VPATH when `$srcdir' = `.'. +# Shell code in configure.ac might set extrasub. +# FIXME: do we really want to maintain this feature? +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +ac_sed_extra="$ac_vpsub +$extrasub +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +:t +/@[a-zA-Z_][a-zA-Z_0-9]*@/!b +s|@configure_input@|$ac_sed_conf_input|;t t +s&@top_builddir@&$ac_top_builddir_sub&;t t +s&@top_build_prefix@&$ac_top_build_prefix&;t t +s&@srcdir@&$ac_srcdir&;t t +s&@abs_srcdir@&$ac_abs_srcdir&;t t +s&@top_srcdir@&$ac_top_srcdir&;t t +s&@abs_top_srcdir@&$ac_abs_top_srcdir&;t t +s&@builddir@&$ac_builddir&;t t +s&@abs_builddir@&$ac_abs_builddir&;t t +s&@abs_top_builddir@&$ac_abs_top_builddir&;t t +s&@INSTALL@&$ac_INSTALL&;t t +s&@MKDIR_P@&$ac_MKDIR_P&;t t +$ac_datarootdir_hack +" +eval sed \"\$ac_sed_extra\" "$ac_file_inputs" | $AWK -f "$ac_tmp/subs.awk" \ + >$ac_tmp/out || as_fn_error $? "could not create $ac_file" "$LINENO" 5 + +test -z "$ac_datarootdir_hack$ac_datarootdir_seen" && + { ac_out=`sed -n '/\${datarootdir}/p' "$ac_tmp/out"`; test -n "$ac_out"; } && + { ac_out=`sed -n '/^[ ]*datarootdir[ ]*:*=/p' \ + "$ac_tmp/out"`; test -z "$ac_out"; } && + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file contains a reference to the variable \`datarootdir' +which seems to be undefined. Please make sure it is defined" >&5 +$as_echo "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir' +which seems to be undefined. Please make sure it is defined" >&2;} + + rm -f "$ac_tmp/stdin" + case $ac_file in + -) cat "$ac_tmp/out" && rm -f "$ac_tmp/out";; + *) rm -f "$ac_file" && mv "$ac_tmp/out" "$ac_file";; + esac \ + || as_fn_error $? "could not create $ac_file" "$LINENO" 5 + ;; + :H) + # + # CONFIG_HEADER + # + if test x"$ac_file" != x-; then + { + $as_echo "/* $configure_input */" \ + && eval '$AWK -f "$ac_tmp/defines.awk"' "$ac_file_inputs" + } >"$ac_tmp/config.h" \ + || as_fn_error $? "could not create $ac_file" "$LINENO" 5 + if diff "$ac_file" "$ac_tmp/config.h" >/dev/null 2>&1; then + { $as_echo "$as_me:${as_lineno-$LINENO}: $ac_file is unchanged" >&5 +$as_echo "$as_me: $ac_file is unchanged" >&6;} + else + rm -f "$ac_file" + mv "$ac_tmp/config.h" "$ac_file" \ + || as_fn_error $? "could not create $ac_file" "$LINENO" 5 + fi + else + $as_echo "/* $configure_input */" \ + && eval '$AWK -f "$ac_tmp/defines.awk"' "$ac_file_inputs" \ + || as_fn_error $? "could not create -" "$LINENO" 5 + fi +# Compute "$ac_file"'s index in $config_headers. +_am_arg="$ac_file" +_am_stamp_count=1 +for _am_header in $config_headers :; do + case $_am_header in + $_am_arg | $_am_arg:* ) + break ;; + * ) + _am_stamp_count=`expr $_am_stamp_count + 1` ;; + esac +done +echo "timestamp for $_am_arg" >`$as_dirname -- "$_am_arg" || +$as_expr X"$_am_arg" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$_am_arg" : 'X\(//\)[^/]' \| \ + X"$_am_arg" : 'X\(//\)$' \| \ + X"$_am_arg" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X"$_am_arg" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'`/stamp-h$_am_stamp_count + ;; + + :C) { $as_echo "$as_me:${as_lineno-$LINENO}: executing $ac_file commands" >&5 +$as_echo "$as_me: executing $ac_file commands" >&6;} + ;; + esac + + + case $ac_file$ac_mode in + "depfiles":C) test x"$AMDEP_TRUE" != x"" || { + # Older Autoconf quotes --file arguments for eval, but not when files + # are listed without --file. Let's play safe and only enable the eval + # if we detect the quoting. + case $CONFIG_FILES in + *\'*) eval set x "$CONFIG_FILES" ;; + *) set x $CONFIG_FILES ;; + esac + shift + for mf + do + # Strip MF so we end up with the name of the file. + mf=`echo "$mf" | sed -e 's/:.*$//'` + # Check whether this is an Automake generated Makefile or not. + # We used to match only the files named 'Makefile.in', but + # some people rename them; so instead we look at the file content. + # Grep'ing the first line is not enough: some people post-process + # each Makefile.in and add a new line on top of each file to say so. + # Grep'ing the whole file is not good either: AIX grep has a line + # limit of 2048, but all sed's we know have understand at least 4000. + if sed -n 's,^#.*generated by automake.*,X,p' "$mf" | grep X >/dev/null 2>&1; then + dirpart=`$as_dirname -- "$mf" || +$as_expr X"$mf" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$mf" : 'X\(//\)[^/]' \| \ + X"$mf" : 'X\(//\)$' \| \ + X"$mf" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X"$mf" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + else + continue + fi + # Extract the definition of DEPDIR, am__include, and am__quote + # from the Makefile without running 'make'. + DEPDIR=`sed -n 's/^DEPDIR = //p' < "$mf"` + test -z "$DEPDIR" && continue + am__include=`sed -n 's/^am__include = //p' < "$mf"` + test -z "$am__include" && continue + am__quote=`sed -n 's/^am__quote = //p' < "$mf"` + # Find all dependency output files, they are included files with + # $(DEPDIR) in their names. We invoke sed twice because it is the + # simplest approach to changing $(DEPDIR) to its actual value in the + # expansion. + for file in `sed -n " + s/^$am__include $am__quote\(.*(DEPDIR).*\)$am__quote"'$/\1/p' <"$mf" | \ + sed -e 's/\$(DEPDIR)/'"$DEPDIR"'/g'`; do + # Make sure the directory exists. + test -f "$dirpart/$file" && continue + fdir=`$as_dirname -- "$file" || +$as_expr X"$file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$file" : 'X\(//\)[^/]' \| \ + X"$file" : 'X\(//\)$' \| \ + X"$file" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X"$file" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + as_dir=$dirpart/$fdir; as_fn_mkdir_p + # echo "creating $dirpart/$file" + echo '# dummy' > "$dirpart/$file" + done + done +} + ;; + "libtool":C) + + # See if we are running on zsh, and set the options which allow our + # commands through without removal of \ escapes. + if test -n "${ZSH_VERSION+set}" ; then + setopt NO_GLOB_SUBST + fi + + cfgfile="${ofile}T" + trap "$RM \"$cfgfile\"; exit 1" 1 2 15 + $RM "$cfgfile" + + cat <<_LT_EOF >> "$cfgfile" +#! $SHELL + +# `$ECHO "$ofile" | sed 's%^.*/%%'` - Provide generalized library-building support services. +# Generated automatically by $as_me ($PACKAGE$TIMESTAMP) $VERSION +# Libtool was configured on host `(hostname || uname -n) 2>/dev/null | sed 1q`: +# NOTE: Changes made to this file will be lost: look at ltmain.sh. +# +# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, +# 2006, 2007, 2008, 2009, 2010, 2011 Free Software +# Foundation, Inc. +# Written by Gordon Matzigkeit, 1996 +# +# This file is part of GNU Libtool. +# +# GNU Libtool is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# As a special exception to the GNU General Public License, +# if you distribute this file as part of a program or library that +# is built using GNU Libtool, you may include this file under the +# same distribution terms that you use for the rest of that program. +# +# GNU Libtool is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Libtool; see the file COPYING. If not, a copy +# can be downloaded from http://www.gnu.org/licenses/gpl.html, or +# obtained by writing to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + + +# The names of the tagged configurations supported by this script. +available_tags="CXX " + +# ### BEGIN LIBTOOL CONFIG + +# Which release of libtool.m4 was used? +macro_version=$macro_version +macro_revision=$macro_revision + +# Whether or not to build static libraries. +build_old_libs=$enable_static + +# Whether or not to build shared libraries. +build_libtool_libs=$enable_shared + +# What type of objects to build. +pic_mode=$pic_mode + +# Whether or not to optimize for fast installation. +fast_install=$enable_fast_install + +# Shell to use when invoking shell scripts. +SHELL=$lt_SHELL + +# An echo program that protects backslashes. +ECHO=$lt_ECHO + +# The PATH separator for the build system. +PATH_SEPARATOR=$lt_PATH_SEPARATOR + +# The host system. +host_alias=$host_alias +host=$host +host_os=$host_os + +# The build system. +build_alias=$build_alias +build=$build +build_os=$build_os + +# A sed program that does not truncate output. +SED=$lt_SED + +# Sed that helps us avoid accidentally triggering echo(1) options like -n. +Xsed="\$SED -e 1s/^X//" + +# A grep program that handles long lines. +GREP=$lt_GREP + +# An ERE matcher. +EGREP=$lt_EGREP + +# A literal string matcher. +FGREP=$lt_FGREP + +# A BSD- or MS-compatible name lister. +NM=$lt_NM + +# Whether we need soft or hard links. +LN_S=$lt_LN_S + +# What is the maximum length of a command? +max_cmd_len=$max_cmd_len + +# Object file suffix (normally "o"). +objext=$ac_objext + +# Executable file suffix (normally ""). +exeext=$exeext + +# whether the shell understands "unset". +lt_unset=$lt_unset + +# turn spaces into newlines. +SP2NL=$lt_lt_SP2NL + +# turn newlines into spaces. +NL2SP=$lt_lt_NL2SP + +# convert \$build file names to \$host format. +to_host_file_cmd=$lt_cv_to_host_file_cmd + +# convert \$build files to toolchain format. +to_tool_file_cmd=$lt_cv_to_tool_file_cmd + +# An object symbol dumper. +OBJDUMP=$lt_OBJDUMP + +# Method to check whether dependent libraries are shared objects. +deplibs_check_method=$lt_deplibs_check_method + +# Command to use when deplibs_check_method = "file_magic". +file_magic_cmd=$lt_file_magic_cmd + +# How to find potential files when deplibs_check_method = "file_magic". +file_magic_glob=$lt_file_magic_glob + +# Find potential files using nocaseglob when deplibs_check_method = "file_magic". +want_nocaseglob=$lt_want_nocaseglob + +# DLL creation program. +DLLTOOL=$lt_DLLTOOL + +# Command to associate shared and link libraries. +sharedlib_from_linklib_cmd=$lt_sharedlib_from_linklib_cmd + +# The archiver. +AR=$lt_AR + +# Flags to create an archive. +AR_FLAGS=$lt_AR_FLAGS + +# How to feed a file listing to the archiver. +archiver_list_spec=$lt_archiver_list_spec + +# A symbol stripping program. +STRIP=$lt_STRIP + +# Commands used to install an old-style archive. +RANLIB=$lt_RANLIB +old_postinstall_cmds=$lt_old_postinstall_cmds +old_postuninstall_cmds=$lt_old_postuninstall_cmds + +# Whether to use a lock for old archive extraction. +lock_old_archive_extraction=$lock_old_archive_extraction + +# A C compiler. +LTCC=$lt_CC + +# LTCC compiler flags. +LTCFLAGS=$lt_CFLAGS + +# Take the output of nm and produce a listing of raw symbols and C names. +global_symbol_pipe=$lt_lt_cv_sys_global_symbol_pipe + +# Transform the output of nm in a proper C declaration. +global_symbol_to_cdecl=$lt_lt_cv_sys_global_symbol_to_cdecl + +# Transform the output of nm in a C name address pair. +global_symbol_to_c_name_address=$lt_lt_cv_sys_global_symbol_to_c_name_address + +# Transform the output of nm in a C name address pair when lib prefix is needed. +global_symbol_to_c_name_address_lib_prefix=$lt_lt_cv_sys_global_symbol_to_c_name_address_lib_prefix + +# Specify filename containing input files for \$NM. +nm_file_list_spec=$lt_nm_file_list_spec + +# The root where to search for dependent libraries,and in which our libraries should be installed. +lt_sysroot=$lt_sysroot + +# The name of the directory that contains temporary libtool files. +objdir=$objdir + +# Used to examine libraries when file_magic_cmd begins with "file". +MAGIC_CMD=$MAGIC_CMD + +# Must we lock files when doing compilation? +need_locks=$lt_need_locks + +# Manifest tool. +MANIFEST_TOOL=$lt_MANIFEST_TOOL + +# Tool to manipulate archived DWARF debug symbol files on Mac OS X. +DSYMUTIL=$lt_DSYMUTIL + +# Tool to change global to local symbols on Mac OS X. +NMEDIT=$lt_NMEDIT + +# Tool to manipulate fat objects and archives on Mac OS X. +LIPO=$lt_LIPO + +# ldd/readelf like tool for Mach-O binaries on Mac OS X. +OTOOL=$lt_OTOOL + +# ldd/readelf like tool for 64 bit Mach-O binaries on Mac OS X 10.4. +OTOOL64=$lt_OTOOL64 + +# Old archive suffix (normally "a"). +libext=$libext + +# Shared library suffix (normally ".so"). +shrext_cmds=$lt_shrext_cmds + +# The commands to extract the exported symbol list from a shared archive. +extract_expsyms_cmds=$lt_extract_expsyms_cmds + +# Variables whose values should be saved in libtool wrapper scripts and +# restored at link time. +variables_saved_for_relink=$lt_variables_saved_for_relink + +# Do we need the "lib" prefix for modules? +need_lib_prefix=$need_lib_prefix + +# Do we need a version for libraries? +need_version=$need_version + +# Library versioning type. +version_type=$version_type + +# Shared library runtime path variable. +runpath_var=$runpath_var + +# Shared library path variable. +shlibpath_var=$shlibpath_var + +# Is shlibpath searched before the hard-coded library search path? +shlibpath_overrides_runpath=$shlibpath_overrides_runpath + +# Format of library name prefix. +libname_spec=$lt_libname_spec + +# List of archive names. First name is the real one, the rest are links. +# The last name is the one that the linker finds with -lNAME +library_names_spec=$lt_library_names_spec + +# The coded name of the library, if different from the real name. +soname_spec=$lt_soname_spec + +# Permission mode override for installation of shared libraries. +install_override_mode=$lt_install_override_mode + +# Command to use after installation of a shared archive. +postinstall_cmds=$lt_postinstall_cmds + +# Command to use after uninstallation of a shared archive. +postuninstall_cmds=$lt_postuninstall_cmds + +# Commands used to finish a libtool library installation in a directory. +finish_cmds=$lt_finish_cmds + +# As "finish_cmds", except a single script fragment to be evaled but +# not shown. +finish_eval=$lt_finish_eval + +# Whether we should hardcode library paths into libraries. +hardcode_into_libs=$hardcode_into_libs + +# Compile-time system search path for libraries. +sys_lib_search_path_spec=$lt_sys_lib_search_path_spec + +# Run-time system search path for libraries. +sys_lib_dlsearch_path_spec=$lt_sys_lib_dlsearch_path_spec + +# Whether dlopen is supported. +dlopen_support=$enable_dlopen + +# Whether dlopen of programs is supported. +dlopen_self=$enable_dlopen_self + +# Whether dlopen of statically linked programs is supported. +dlopen_self_static=$enable_dlopen_self_static + +# Commands to strip libraries. +old_striplib=$lt_old_striplib +striplib=$lt_striplib + + +# The linker used to build libraries. +LD=$lt_LD + +# How to create reloadable object files. +reload_flag=$lt_reload_flag +reload_cmds=$lt_reload_cmds + +# Commands used to build an old-style archive. +old_archive_cmds=$lt_old_archive_cmds + +# A language specific compiler. +CC=$lt_compiler + +# Is the compiler the GNU compiler? +with_gcc=$GCC + +# Compiler flag to turn off builtin functions. +no_builtin_flag=$lt_lt_prog_compiler_no_builtin_flag + +# Additional compiler flags for building library objects. +pic_flag=$lt_lt_prog_compiler_pic + +# How to pass a linker flag through the compiler. +wl=$lt_lt_prog_compiler_wl + +# Compiler flag to prevent dynamic linking. +link_static_flag=$lt_lt_prog_compiler_static + +# Does compiler simultaneously support -c and -o options? +compiler_c_o=$lt_lt_cv_prog_compiler_c_o + +# Whether or not to add -lc for building shared libraries. +build_libtool_need_lc=$archive_cmds_need_lc + +# Whether or not to disallow shared libs when runtime libs are static. +allow_libtool_libs_with_static_runtimes=$enable_shared_with_static_runtimes + +# Compiler flag to allow reflexive dlopens. +export_dynamic_flag_spec=$lt_export_dynamic_flag_spec + +# Compiler flag to generate shared objects directly from archives. +whole_archive_flag_spec=$lt_whole_archive_flag_spec + +# Whether the compiler copes with passing no objects directly. +compiler_needs_object=$lt_compiler_needs_object + +# Create an old-style archive from a shared archive. +old_archive_from_new_cmds=$lt_old_archive_from_new_cmds + +# Create a temporary old-style archive to link instead of a shared archive. +old_archive_from_expsyms_cmds=$lt_old_archive_from_expsyms_cmds + +# Commands used to build a shared archive. +archive_cmds=$lt_archive_cmds +archive_expsym_cmds=$lt_archive_expsym_cmds + +# Commands used to build a loadable module if different from building +# a shared archive. +module_cmds=$lt_module_cmds +module_expsym_cmds=$lt_module_expsym_cmds + +# Whether we are building with GNU ld or not. +with_gnu_ld=$lt_with_gnu_ld + +# Flag that allows shared libraries with undefined symbols to be built. +allow_undefined_flag=$lt_allow_undefined_flag + +# Flag that enforces no undefined symbols. +no_undefined_flag=$lt_no_undefined_flag + +# Flag to hardcode \$libdir into a binary during linking. +# This must work even if \$libdir does not exist +hardcode_libdir_flag_spec=$lt_hardcode_libdir_flag_spec + +# Whether we need a single "-rpath" flag with a separated argument. +hardcode_libdir_separator=$lt_hardcode_libdir_separator + +# Set to "yes" if using DIR/libNAME\${shared_ext} during linking hardcodes +# DIR into the resulting binary. +hardcode_direct=$hardcode_direct + +# Set to "yes" if using DIR/libNAME\${shared_ext} during linking hardcodes +# DIR into the resulting binary and the resulting library dependency is +# "absolute",i.e impossible to change by setting \${shlibpath_var} if the +# library is relocated. +hardcode_direct_absolute=$hardcode_direct_absolute + +# Set to "yes" if using the -LDIR flag during linking hardcodes DIR +# into the resulting binary. +hardcode_minus_L=$hardcode_minus_L + +# Set to "yes" if using SHLIBPATH_VAR=DIR during linking hardcodes DIR +# into the resulting binary. +hardcode_shlibpath_var=$hardcode_shlibpath_var + +# Set to "yes" if building a shared library automatically hardcodes DIR +# into the library and all subsequent libraries and executables linked +# against it. +hardcode_automatic=$hardcode_automatic + +# Set to yes if linker adds runtime paths of dependent libraries +# to runtime path list. +inherit_rpath=$inherit_rpath + +# Whether libtool must link a program against all its dependency libraries. +link_all_deplibs=$link_all_deplibs + +# Set to "yes" if exported symbols are required. +always_export_symbols=$always_export_symbols + +# The commands to list exported symbols. +export_symbols_cmds=$lt_export_symbols_cmds + +# Symbols that should not be listed in the preloaded symbols. +exclude_expsyms=$lt_exclude_expsyms + +# Symbols that must always be exported. +include_expsyms=$lt_include_expsyms + +# Commands necessary for linking programs (against libraries) with templates. +prelink_cmds=$lt_prelink_cmds + +# Commands necessary for finishing linking programs. +postlink_cmds=$lt_postlink_cmds + +# Specify filename containing input files. +file_list_spec=$lt_file_list_spec + +# How to hardcode a shared library path into an executable. +hardcode_action=$hardcode_action + +# The directories searched by this compiler when creating a shared library. +compiler_lib_search_dirs=$lt_compiler_lib_search_dirs + +# Dependencies to place before and after the objects being linked to +# create a shared library. +predep_objects=$lt_predep_objects +postdep_objects=$lt_postdep_objects +predeps=$lt_predeps +postdeps=$lt_postdeps + +# The library search path used internally by the compiler when linking +# a shared library. +compiler_lib_search_path=$lt_compiler_lib_search_path + +# ### END LIBTOOL CONFIG + +_LT_EOF + + case $host_os in + aix3*) + cat <<\_LT_EOF >> "$cfgfile" +# AIX sometimes has problems with the GCC collect2 program. For some +# reason, if we set the COLLECT_NAMES environment variable, the problems +# vanish in a puff of smoke. +if test "X${COLLECT_NAMES+set}" != Xset; then + COLLECT_NAMES= + export COLLECT_NAMES +fi +_LT_EOF + ;; + esac + + +ltmain="$ac_aux_dir/ltmain.sh" + + + # We use sed instead of cat because bash on DJGPP gets confused if + # if finds mixed CR/LF and LF-only lines. Since sed operates in + # text mode, it properly converts lines to CR/LF. This bash problem + # is reportedly fixed, but why not run on old versions too? + sed '$q' "$ltmain" >> "$cfgfile" \ + || (rm -f "$cfgfile"; exit 1) + + if test x"$xsi_shell" = xyes; then + sed -e '/^func_dirname ()$/,/^} # func_dirname /c\ +func_dirname ()\ +{\ +\ case ${1} in\ +\ */*) func_dirname_result="${1%/*}${2}" ;;\ +\ * ) func_dirname_result="${3}" ;;\ +\ esac\ +} # Extended-shell func_dirname implementation' "$cfgfile" > $cfgfile.tmp \ + && mv -f "$cfgfile.tmp" "$cfgfile" \ + || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") +test 0 -eq $? || _lt_function_replace_fail=: + + + sed -e '/^func_basename ()$/,/^} # func_basename /c\ +func_basename ()\ +{\ +\ func_basename_result="${1##*/}"\ +} # Extended-shell func_basename implementation' "$cfgfile" > $cfgfile.tmp \ + && mv -f "$cfgfile.tmp" "$cfgfile" \ + || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") +test 0 -eq $? || _lt_function_replace_fail=: + + + sed -e '/^func_dirname_and_basename ()$/,/^} # func_dirname_and_basename /c\ +func_dirname_and_basename ()\ +{\ +\ case ${1} in\ +\ */*) func_dirname_result="${1%/*}${2}" ;;\ +\ * ) func_dirname_result="${3}" ;;\ +\ esac\ +\ func_basename_result="${1##*/}"\ +} # Extended-shell func_dirname_and_basename implementation' "$cfgfile" > $cfgfile.tmp \ + && mv -f "$cfgfile.tmp" "$cfgfile" \ + || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") +test 0 -eq $? || _lt_function_replace_fail=: + + + sed -e '/^func_stripname ()$/,/^} # func_stripname /c\ +func_stripname ()\ +{\ +\ # pdksh 5.2.14 does not do ${X%$Y} correctly if both X and Y are\ +\ # positional parameters, so assign one to ordinary parameter first.\ +\ func_stripname_result=${3}\ +\ func_stripname_result=${func_stripname_result#"${1}"}\ +\ func_stripname_result=${func_stripname_result%"${2}"}\ +} # Extended-shell func_stripname implementation' "$cfgfile" > $cfgfile.tmp \ + && mv -f "$cfgfile.tmp" "$cfgfile" \ + || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") +test 0 -eq $? || _lt_function_replace_fail=: + + + sed -e '/^func_split_long_opt ()$/,/^} # func_split_long_opt /c\ +func_split_long_opt ()\ +{\ +\ func_split_long_opt_name=${1%%=*}\ +\ func_split_long_opt_arg=${1#*=}\ +} # Extended-shell func_split_long_opt implementation' "$cfgfile" > $cfgfile.tmp \ + && mv -f "$cfgfile.tmp" "$cfgfile" \ + || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") +test 0 -eq $? || _lt_function_replace_fail=: + + + sed -e '/^func_split_short_opt ()$/,/^} # func_split_short_opt /c\ +func_split_short_opt ()\ +{\ +\ func_split_short_opt_arg=${1#??}\ +\ func_split_short_opt_name=${1%"$func_split_short_opt_arg"}\ +} # Extended-shell func_split_short_opt implementation' "$cfgfile" > $cfgfile.tmp \ + && mv -f "$cfgfile.tmp" "$cfgfile" \ + || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") +test 0 -eq $? || _lt_function_replace_fail=: + + + sed -e '/^func_lo2o ()$/,/^} # func_lo2o /c\ +func_lo2o ()\ +{\ +\ case ${1} in\ +\ *.lo) func_lo2o_result=${1%.lo}.${objext} ;;\ +\ *) func_lo2o_result=${1} ;;\ +\ esac\ +} # Extended-shell func_lo2o implementation' "$cfgfile" > $cfgfile.tmp \ + && mv -f "$cfgfile.tmp" "$cfgfile" \ + || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") +test 0 -eq $? || _lt_function_replace_fail=: + + + sed -e '/^func_xform ()$/,/^} # func_xform /c\ +func_xform ()\ +{\ + func_xform_result=${1%.*}.lo\ +} # Extended-shell func_xform implementation' "$cfgfile" > $cfgfile.tmp \ + && mv -f "$cfgfile.tmp" "$cfgfile" \ + || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") +test 0 -eq $? || _lt_function_replace_fail=: + + + sed -e '/^func_arith ()$/,/^} # func_arith /c\ +func_arith ()\ +{\ + func_arith_result=$(( $* ))\ +} # Extended-shell func_arith implementation' "$cfgfile" > $cfgfile.tmp \ + && mv -f "$cfgfile.tmp" "$cfgfile" \ + || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") +test 0 -eq $? || _lt_function_replace_fail=: + + + sed -e '/^func_len ()$/,/^} # func_len /c\ +func_len ()\ +{\ + func_len_result=${#1}\ +} # Extended-shell func_len implementation' "$cfgfile" > $cfgfile.tmp \ + && mv -f "$cfgfile.tmp" "$cfgfile" \ + || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") +test 0 -eq $? || _lt_function_replace_fail=: + +fi + +if test x"$lt_shell_append" = xyes; then + sed -e '/^func_append ()$/,/^} # func_append /c\ +func_append ()\ +{\ + eval "${1}+=\\${2}"\ +} # Extended-shell func_append implementation' "$cfgfile" > $cfgfile.tmp \ + && mv -f "$cfgfile.tmp" "$cfgfile" \ + || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") +test 0 -eq $? || _lt_function_replace_fail=: + + + sed -e '/^func_append_quoted ()$/,/^} # func_append_quoted /c\ +func_append_quoted ()\ +{\ +\ func_quote_for_eval "${2}"\ +\ eval "${1}+=\\\\ \\$func_quote_for_eval_result"\ +} # Extended-shell func_append_quoted implementation' "$cfgfile" > $cfgfile.tmp \ + && mv -f "$cfgfile.tmp" "$cfgfile" \ + || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") +test 0 -eq $? || _lt_function_replace_fail=: + + + # Save a `func_append' function call where possible by direct use of '+=' + sed -e 's%func_append \([a-zA-Z_]\{1,\}\) "%\1+="%g' $cfgfile > $cfgfile.tmp \ + && mv -f "$cfgfile.tmp" "$cfgfile" \ + || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") + test 0 -eq $? || _lt_function_replace_fail=: +else + # Save a `func_append' function call even when '+=' is not available + sed -e 's%func_append \([a-zA-Z_]\{1,\}\) "%\1="$\1%g' $cfgfile > $cfgfile.tmp \ + && mv -f "$cfgfile.tmp" "$cfgfile" \ + || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") + test 0 -eq $? || _lt_function_replace_fail=: +fi + +if test x"$_lt_function_replace_fail" = x":"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: Unable to substitute extended shell functions in $ofile" >&5 +$as_echo "$as_me: WARNING: Unable to substitute extended shell functions in $ofile" >&2;} +fi + + + mv -f "$cfgfile" "$ofile" || + (rm -f "$ofile" && cp "$cfgfile" "$ofile" && rm -f "$cfgfile") + chmod +x "$ofile" + + + cat <<_LT_EOF >> "$ofile" + +# ### BEGIN LIBTOOL TAG CONFIG: CXX + +# The linker used to build libraries. +LD=$lt_LD_CXX + +# How to create reloadable object files. +reload_flag=$lt_reload_flag_CXX +reload_cmds=$lt_reload_cmds_CXX + +# Commands used to build an old-style archive. +old_archive_cmds=$lt_old_archive_cmds_CXX + +# A language specific compiler. +CC=$lt_compiler_CXX + +# Is the compiler the GNU compiler? +with_gcc=$GCC_CXX + +# Compiler flag to turn off builtin functions. +no_builtin_flag=$lt_lt_prog_compiler_no_builtin_flag_CXX + +# Additional compiler flags for building library objects. +pic_flag=$lt_lt_prog_compiler_pic_CXX + +# How to pass a linker flag through the compiler. +wl=$lt_lt_prog_compiler_wl_CXX + +# Compiler flag to prevent dynamic linking. +link_static_flag=$lt_lt_prog_compiler_static_CXX + +# Does compiler simultaneously support -c and -o options? +compiler_c_o=$lt_lt_cv_prog_compiler_c_o_CXX + +# Whether or not to add -lc for building shared libraries. +build_libtool_need_lc=$archive_cmds_need_lc_CXX + +# Whether or not to disallow shared libs when runtime libs are static. +allow_libtool_libs_with_static_runtimes=$enable_shared_with_static_runtimes_CXX + +# Compiler flag to allow reflexive dlopens. +export_dynamic_flag_spec=$lt_export_dynamic_flag_spec_CXX + +# Compiler flag to generate shared objects directly from archives. +whole_archive_flag_spec=$lt_whole_archive_flag_spec_CXX + +# Whether the compiler copes with passing no objects directly. +compiler_needs_object=$lt_compiler_needs_object_CXX + +# Create an old-style archive from a shared archive. +old_archive_from_new_cmds=$lt_old_archive_from_new_cmds_CXX + +# Create a temporary old-style archive to link instead of a shared archive. +old_archive_from_expsyms_cmds=$lt_old_archive_from_expsyms_cmds_CXX + +# Commands used to build a shared archive. +archive_cmds=$lt_archive_cmds_CXX +archive_expsym_cmds=$lt_archive_expsym_cmds_CXX + +# Commands used to build a loadable module if different from building +# a shared archive. +module_cmds=$lt_module_cmds_CXX +module_expsym_cmds=$lt_module_expsym_cmds_CXX + +# Whether we are building with GNU ld or not. +with_gnu_ld=$lt_with_gnu_ld_CXX + +# Flag that allows shared libraries with undefined symbols to be built. +allow_undefined_flag=$lt_allow_undefined_flag_CXX + +# Flag that enforces no undefined symbols. +no_undefined_flag=$lt_no_undefined_flag_CXX + +# Flag to hardcode \$libdir into a binary during linking. +# This must work even if \$libdir does not exist +hardcode_libdir_flag_spec=$lt_hardcode_libdir_flag_spec_CXX + +# Whether we need a single "-rpath" flag with a separated argument. +hardcode_libdir_separator=$lt_hardcode_libdir_separator_CXX + +# Set to "yes" if using DIR/libNAME\${shared_ext} during linking hardcodes +# DIR into the resulting binary. +hardcode_direct=$hardcode_direct_CXX + +# Set to "yes" if using DIR/libNAME\${shared_ext} during linking hardcodes +# DIR into the resulting binary and the resulting library dependency is +# "absolute",i.e impossible to change by setting \${shlibpath_var} if the +# library is relocated. +hardcode_direct_absolute=$hardcode_direct_absolute_CXX + +# Set to "yes" if using the -LDIR flag during linking hardcodes DIR +# into the resulting binary. +hardcode_minus_L=$hardcode_minus_L_CXX + +# Set to "yes" if using SHLIBPATH_VAR=DIR during linking hardcodes DIR +# into the resulting binary. +hardcode_shlibpath_var=$hardcode_shlibpath_var_CXX + +# Set to "yes" if building a shared library automatically hardcodes DIR +# into the library and all subsequent libraries and executables linked +# against it. +hardcode_automatic=$hardcode_automatic_CXX + +# Set to yes if linker adds runtime paths of dependent libraries +# to runtime path list. +inherit_rpath=$inherit_rpath_CXX + +# Whether libtool must link a program against all its dependency libraries. +link_all_deplibs=$link_all_deplibs_CXX + +# Set to "yes" if exported symbols are required. +always_export_symbols=$always_export_symbols_CXX + +# The commands to list exported symbols. +export_symbols_cmds=$lt_export_symbols_cmds_CXX + +# Symbols that should not be listed in the preloaded symbols. +exclude_expsyms=$lt_exclude_expsyms_CXX + +# Symbols that must always be exported. +include_expsyms=$lt_include_expsyms_CXX + +# Commands necessary for linking programs (against libraries) with templates. +prelink_cmds=$lt_prelink_cmds_CXX + +# Commands necessary for finishing linking programs. +postlink_cmds=$lt_postlink_cmds_CXX + +# Specify filename containing input files. +file_list_spec=$lt_file_list_spec_CXX + +# How to hardcode a shared library path into an executable. +hardcode_action=$hardcode_action_CXX + +# The directories searched by this compiler when creating a shared library. +compiler_lib_search_dirs=$lt_compiler_lib_search_dirs_CXX + +# Dependencies to place before and after the objects being linked to +# create a shared library. +predep_objects=$lt_predep_objects_CXX +postdep_objects=$lt_postdep_objects_CXX +predeps=$lt_predeps_CXX +postdeps=$lt_postdeps_CXX + +# The library search path used internally by the compiler when linking +# a shared library. +compiler_lib_search_path=$lt_compiler_lib_search_path_CXX + +# ### END LIBTOOL TAG CONFIG: CXX +_LT_EOF + + ;; + "stamp-h":F) echo timestamp > stamp-h ;; + + esac +done # for ac_tag + + +as_fn_exit 0 +_ACEOF +ac_clean_files=$ac_clean_files_save + +test $ac_write_fail = 0 || + as_fn_error $? "write failure creating $CONFIG_STATUS" "$LINENO" 5 + + +# configure is writing to config.log, and then calls config.status. +# config.status does its own redirection, appending to config.log. +# Unfortunately, on DOS this fails, as config.log is still kept open +# by configure, so config.status won't be able to write to it; its +# output is simply discarded. So we exec the FD to /dev/null, +# effectively closing config.log, so it can be properly (re)opened and +# appended to by config.status. When coming back to configure, we +# need to make the FD available again. +if test "$no_create" != yes; then + ac_cs_success=: + ac_config_status_args= + test "$silent" = yes && + ac_config_status_args="$ac_config_status_args --quiet" + exec 5>/dev/null + $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false + exec 5>>config.log + # Use ||, not &&, to avoid exiting from the if with $? = 1, which + # would make configure fail if this is the last instruction. + $ac_cs_success || as_fn_exit 1 +fi +if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 +$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;} +fi + + + +# force make clean +echo "---" +echo "Running make clean..." +make clean >/dev/null 2>&1 +# Touch files that may not be in repository +echo "Touching File..." +touch ctaocrypt/src/fips.c +touch ctaocrypt/src/fips_test.c +echo + +# generate user options header +echo "---" +echo "Generating user options header..." + +OPTION_FILE="wolfssl/options.h" +#if +#OPTION_FILE+="cyassl/options.h" +#fi +rm -f $OPTION_FILE + +echo "/* wolfssl options.h" > $OPTION_FILE +echo " * generated from configure options" >> $OPTION_FILE +echo " *" >> $OPTION_FILE +echo " * Copyright (C) 2006-2015 wolfSSL Inc." >> $OPTION_FILE +echo " *" >> $OPTION_FILE +echo " * This file is part of wolfSSL. (formerly known as CyaSSL)" >> $OPTION_FILE +echo " *" >> $OPTION_FILE +echo " */" >> $OPTION_FILE + +echo "" >> $OPTION_FILE +echo "#pragma once" >> $OPTION_FILE +echo "" >> $OPTION_FILE +echo "#ifdef __cplusplus" >> $OPTION_FILE +echo "extern \"C\" {" >> $OPTION_FILE +echo "#endif" >> $OPTION_FILE +echo "" >> $OPTION_FILE + +for option in $OPTION_FLAGS; do + defonly=`echo $option | sed 's/-D//'` + if test "$defonly" != "$option" + then + noequalsign=`echo $defonly | sed 's/=/ /'` + if test "$noequalsign" = "NDEBUG" || test "$noequalsign" = "DEBUG" + then + echo "not outputing (N)DEBUG to $OPTION_FILE" + continue + fi + + # allow user to igonore system options + ignoresys=no + if [[ $noequalsign == _* ]] ; + then + ignoresys=yes + echo "#ifndef WOLFSSL_OPTIONS_IGNORE_SYS" >> $OPTION_FILE + fi + + noarg=`echo $defonly | sed 's/=.*//'` + echo "#undef $noarg" >> $OPTION_FILE + echo "#define $noequalsign" >> $OPTION_FILE + + if test "$ignoresys" = "yes" + then + echo "#endif" >> $OPTION_FILE + fi + + echo "" >> $OPTION_FILE + else + echo "option w/o begin -D is $option, not saving to $OPTION_FILE" + fi +done + +echo "" >> $OPTION_FILE +echo "#ifdef __cplusplus" >> $OPTION_FILE +echo "}" >> $OPTION_FILE +echo "#endif" >> $OPTION_FILE +echo "" >> $OPTION_FILE +echo + +#backwards compatability for those who have included options or version +touch cyassl/options.h +echo "/* cyassl options.h" > cyassl/options.h +echo " * generated from wolfssl/options.h" >> cyassl/options.h +echo " */" >> cyassl/options.h +echo "" +while read -r line +do + echo "$line" >> cyassl/options.h +done < $OPTION_FILE + +# output config summary +echo "---" +echo "Configuration summary for $PACKAGE_NAME version $VERSION" +echo "" +echo " * Installation prefix: $prefix" +echo " * System type: $host_vendor-$host_os" +echo " * Host CPU: $host_cpu" +echo " * C Compiler: $CC" +echo " * C Flags: $CFLAGS" +echo " * C++ Compiler: $CXX" +echo " * C++ Flags: $CXXFLAGS" +echo " * CPP Flags: $CPPFLAGS" +echo " * LIB Flags: $LIB" +echo " * Debug enabled: $ax_enable_debug" +echo " * Warnings as failure: $ac_cv_warnings_as_errors" +echo " * make -j: $enable_jobserver" +echo " * VCS checkout: $ac_cv_vcs_checkout" +echo +echo " Features " +echo " * Single threaded: $ENABLED_SINGLETHREADED" +echo " * Filesystem: $ENABLED_FILESYSTEM" +echo " * OpenSSL Extra API: $ENABLED_OPENSSLEXTRA" +echo " * Max Strength Build: $ENABLED_MAXSTRENGTH" +echo " * fastmath: $ENABLED_FASTMATH" +echo " * sniffer: $ENABLED_SNIFFER" +echo " * snifftest: $ENABLED_SNIFFTEST" +echo " * ARC4: $ENABLED_ARC4" +echo " * AES: $ENABLED_AES" +echo " * AES-NI: $ENABLED_AESNI" +echo " * AES-GCM: $ENABLED_AESGCM" +echo " * AES-CCM: $ENABLED_AESCCM" +echo " * DES3: $ENABLED_DES3" +echo " * Camellia: $ENABLED_CAMELLIA" +echo " * NULL Cipher: $ENABLED_NULL_CIPHER" +echo " * MD5: $ENABLED_MD5" +echo " * RIPEMD: $ENABLED_RIPEMD" +echo " * SHA: $ENABLED_SHA" +echo " * SHA-512: $ENABLED_SHA512" +echo " * BLAKE2: $ENABLED_BLAKE2" +echo " * keygen: $ENABLED_KEYGEN" +echo " * certgen: $ENABLED_CERTGEN" +echo " * certreq: $ENABLED_CERTREQ" +echo " * HC-128: $ENABLED_HC128" +echo " * RABBIT: $ENABLED_RABBIT" +echo " * CHACHA: $ENABLED_CHACHA" +echo " * Hash DRBG: $ENABLED_HASHDRBG" +echo " * PWDBASED: $ENABLED_PWDBASED" +echo " * HKDF: $ENABLED_HKDF" +echo " * MD4: $ENABLED_MD4" +echo " * PSK: $ENABLED_PSK" +echo " * Poly1305: $ENABLED_POLY1305" +echo " * LEANPSK: $ENABLED_LEANPSK" +echo " * RSA: $ENABLED_RSA" +echo " * DSA: $ENABLED_DSA" +echo " * DH: $ENABLED_DH" +echo " * ECC: $ENABLED_ECC" +echo " * CURVE25519: $ENABLED_CURVE25519" +echo " * ED25519: $ENABLED_ED25519" +echo " * FPECC: $ENABLED_FPECC" +echo " * ECC_ENCRYPT: $ENABLED_ECC_ENCRYPT" +echo " * ASN: $ENABLED_ASN" +echo " * Anonymous cipher: $ENABLED_ANON" +echo " * CODING: $ENABLED_CODING" +echo " * MEMORY: $ENABLED_MEMORY" +echo " * I/O POOL: $ENABLED_IOPOOL" +echo " * ERROR_STRINGS: $ENABLED_ERROR_STRINGS" +echo " * DTLS: $ENABLED_DTLS" +echo " * Old TLS Versions: $ENABLED_OLD_TLS" +echo " * OCSP: $ENABLED_OCSP" +echo " * CRL: $ENABLED_CRL" +echo " * CRL-MONITOR: $ENABLED_CRL_MONITOR" +echo " * Persistent session cache: $ENABLED_SAVESESSION" +echo " * Persistent cert cache: $ENABLED_SAVECERT" +echo " * Atomic User Record Layer: $ENABLED_ATOMICUSER" +echo " * Public Key Callbacks: $ENABLED_PKCALLBACKS" +echo " * NTRU: $ENABLED_NTRU" +echo " * SNI: $ENABLED_SNI" +echo " * Maximum Fragment Length: $ENABLED_MAX_FRAGMENT" +echo " * Truncated HMAC: $ENABLED_TRUNCATED_HMAC" +echo " * Renegotiation Indication: $ENABLED_RENEGOTIATION_INDICATION" +echo " * Secure Renegotiation: $ENABLED_SECURE_RENEGOTIATION" +echo " * Supported Elliptic Curves: $ENABLED_SUPPORTED_CURVES" +echo " * Session Ticket: $ENABLED_SESSION_TICKET" +echo " * All TLS Extensions: $ENABLED_TLSX" +echo " * PKCS#7 $ENABLED_PKCS7" +echo " * wolfSCEP $ENABLED_WOLFSCEP" +echo " * Small Stack: $ENABLED_SMALL_STACK" +echo " * valgrind unit tests: $ENABLED_VALGRIND" +echo " * LIBZ: $ENABLED_LIBZ" +echo " * Examples: $ENABLED_EXAMPLES" +echo "" +echo "---" + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/configure.ac b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/configure.ac new file mode 100644 index 0000000..4b6d331 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/configure.ac @@ -0,0 +1,2229 @@ +# configure.ac +# +# Copyright (C) 2006-2015 wolfSSL Inc. +# +# This file is part of wolfSSL. (formerly known as CyaSSL) +# +# + +AC_INIT([wolfssl],[3.6.0],[https://github.com/wolfssl/wolfssl/issues],[wolfssl],[http://www.wolfssl.com]) + +AC_CONFIG_AUX_DIR([build-aux]) + +AC_CANONICAL_HOST +AC_CANONICAL_BUILD + +AM_INIT_AUTOMAKE([1.11 -Wall -Werror -Wno-portability foreign tar-ustar subdir-objects no-define color-tests]) +AC_PREREQ([2.63]) + +AC_ARG_PROGRAM +AC_DEFUN([PROTECT_AC_USE_SYSTEM_EXTENSIONS], + [AX_SAVE_FLAGS + AC_LANG_PUSH([C]) + AC_USE_SYSTEM_EXTENSIONS + AC_LANG_POP([C]) + AX_RESTORE_FLAGS + ]) +#PROTECT_AC_USE_SYSTEM_EXTENSIONS + +AC_CONFIG_MACRO_DIR([m4]) + +AC_CONFIG_HEADERS([config.h:config.in])dnl Keep filename to 8.3 for MS-DOS. + +#shared library versioning +WOLFSSL_LIBRARY_VERSION=0:2:0 +# | | | +# +------+ | +---+ +# | | | +# current:revision:age +# | | | +# | | +- increment if interfaces have been added +# | | set to zero if interfaces have been removed +# | | or changed +# | +- increment if source code has changed +# | set to zero if current is incremented +# +- increment if interfaces have been added, removed or changed +AC_SUBST([WOLFSSL_LIBRARY_VERSION]) + +# capture user C_EXTRA_FLAGS from ./configure line, CFLAGS may hold -g -O2 even +# if user doesn't override, no way to tell +USER_C_EXTRA_FLAGS="$C_EXTRA_FLAGS" + +LT_PREREQ([2.2]) +LT_INIT([disable-static],[win32-dll]) +LT_LANG([C++]) +LT_LANG([C]) + +gl_VISIBILITY +AS_IF([ test -n "$CFLAG_VISIBILITY" ], [ + AM_CPPFLAGS="$AM_CPPFLAGS $CFLAG_VISIBILITY" + CPPFLAGS="$CPPFLAGS $CFLAG_VISIBILITY" + ]) + +m4_ifdef([AM_SILENT_RULES],[AM_SILENT_RULES([yes])]) + +AC_CHECK_FUNCS([gethostbyname]) +AC_CHECK_FUNCS([getaddrinfo]) +AC_CHECK_FUNCS([gettimeofday]) +AC_CHECK_FUNCS([inet_ntoa]) +AC_CHECK_FUNCS([memset]) +AC_CHECK_FUNCS([socket]) +AC_CHECK_HEADERS([arpa/inet.h]) +AC_CHECK_HEADERS([fcntl.h]) +AC_CHECK_HEADERS([limits.h]) +AC_CHECK_HEADERS([netdb.h]) +AC_CHECK_HEADERS([netinet/in.h]) +AC_CHECK_HEADERS([stddef.h]) +AC_CHECK_HEADERS([sys/ioctl.h]) +AC_CHECK_HEADERS([sys/socket.h]) +AC_CHECK_HEADERS([sys/time.h]) +AC_CHECK_HEADERS([errno.h]) +AC_CHECK_LIB(network,socket) +AC_CHECK_SIZEOF(long long, 8) +AC_CHECK_SIZEOF(long, 4) +AC_CHECK_TYPES(__uint128_t) +AC_C_BIGENDIAN +# mktime check takes forever on some systems, if time supported it would be +# highly unusual for mktime to be missing +#AC_FUNC_MKTIME + +AC_PROG_CC +AC_PROG_CC_C_O +AC_PROG_CXX +AC_PROG_INSTALL +AC_TYPE_SIZE_T +AC_TYPE_UINT8_T +AM_PROG_AS +AM_PROG_CC_C_O +LT_LIB_M + +OPTIMIZE_CFLAGS="-Os -fomit-frame-pointer" +OPTIMIZE_FAST_CFLAGS="-O2 -fomit-frame-pointer" +OPTIMIZE_HUGE_CFLAGS="-funroll-loops -DTFM_SMALL_SET -DTFM_HUGE_SET" +DEBUG_CFLAGS="-g -DDEBUG -DDEBUG_WOLFSSL" + +thread_ls_on=no +# Thread local storage +AX_TLS([ + [AM_CFLAGS="$AM_CFLAGS -DHAVE_THREAD_LS"] + [thread_ls_on=yes] + ] , [:]) + + +# DEBUG +AX_DEBUG +AS_IF([test "$ax_enable_debug" = "yes"], + [AM_CFLAGS="$DEBUG_CFLAGS $AM_CFLAGS"], + [AM_CFLAGS="$AM_CFLAGS -DNDEBUG"]) + + +# SINGLE THREADED +AC_ARG_ENABLE([singlethreaded], + [ --enable-singlethreaded Enable wolfSSL single threaded (default: disabled)], + [ ENABLED_SINGLETHREADED=$enableval ], + [ ENABLED_SINGLETHREADED=no ]) + +AS_IF([ test "x$ENABLED_SINGLETHREADED" = "xno" ],[ + AX_PTHREAD([ + AC_DEFINE([HAVE_PTHREAD], [1], [Define if you have POSIX threads libraries and header files.]) + AM_CFLAGS="-D_POSIX_THREADS $AM_CFLAGS $PTHREAD_CFLAGS" + LIBS="$LIBS $PTHREAD_LIBS" + ],[ + ENABLED_SINGLETHREADED=yes + ]) + ]) + +AS_IF([ test "x$ENABLED_SINGLETHREADED" = "xyes" ],[ AM_CFLAGS="-DSINGLE_THREADED $AM_CFLAGS" ]) + + +# DTLS +AC_ARG_ENABLE([dtls], + [ --enable-dtls Enable wolfSSL DTLS (default: disabled)], + [ ENABLED_DTLS=$enableval ], + [ ENABLED_DTLS=no ] + ) +if test "$ENABLED_DTLS" = "yes" +then + AM_CFLAGS="-DWOLFSSL_DTLS $AM_CFLAGS" +fi + + +# OPENSSL Extra Compatibility +AC_ARG_ENABLE([opensslextra], + [ --enable-opensslextra Enable extra OpenSSL API, size+ (default: disabled)], + [ ENABLED_OPENSSLEXTRA=$enableval ], + [ ENABLED_OPENSSLEXTRA=no ] + ) +if test "$ENABLED_OPENSSLEXTRA" = "yes" +then + AM_CFLAGS="-DOPENSSL_EXTRA $AM_CFLAGS" +fi + +if test "$ENABLED_OPENSSLEXTRA" = "yes" && test "$ENABLED_SMALL" = "yes" +then + AC_MSG_ERROR([cannot enable small and opensslextra, only one or the other.]) +fi + + +# High Strength Build +AC_ARG_ENABLE([maxstrength], + [AS_HELP_STRING([--enable-maxstrength],[Enable Max Strengh build, allows TLSv1.2-AEAD-PFS ciphers only (default: disabled)])], + [ENABLED_MAXSTRENGTH=$enableval], + [ENABLED_MAXSTRENGTH=no]) + + +# IPv6 Test Apps +AC_ARG_ENABLE([ipv6], + [ --enable-ipv6 Enable testing of IPV6 (default: disabled)], + [ ENABLED_IPV6=$enableval ], + [ ENABLED_IPV6=no ] + ) + +if test "$ENABLED_IPV6" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DTEST_IPV6" +fi + +AM_CONDITIONAL([BUILD_IPV6], [test "x$ENABLED_IPV6" = "xyes"]) + + +# Fortress build +AC_ARG_ENABLE([fortress], + [ --enable-fortress Enable SSL fortress build (default: disabled)], + [ ENABLED_FORTRESS=$enableval ], + [ ENABLED_FORTRESS=no ] + ) + +if test "$ENABLED_FORTRESS" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DFORTRESS -DWOLFSSL_ALWAYS_VERIFY_CB -DOPENSSL_EXTRA -DWOLFSSL_DES_ECB -DWOLFSSL_AES_COUNTER -DWOLFSSL_AES_DIRECT -DWOLFSSL_DER_LOAD -DWOLFSSL_SHA512 -DWOLFSSL_SHA384 -DWOLFSSL_KEY_GEN" +fi + + +# ssl bump build +AC_ARG_ENABLE([bump], + [ --enable-bump Enable SSL Bump build (default: disabled)], + [ ENABLED_BUMP=$enableval ], + [ ENABLED_BUMP=no ] + ) + +if test "$ENABLED_BUMP" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DLARGE_STATIC_BUFFERS -DWOLFSSL_CERT_GEN -DWOLFSSL_KEY_GEN -DHUGE_SESSION_CACHE -DOPENSSL_EXTRA -DFP_MAX_BITS=8192 -DWOLFSSL_DER_LOAD -DWOLFSSL_ALT_NAMES -DWOLFSSL_TEST_CERT" +fi + +ENABLED_SLOWMATH="yes" + +# lean psk build +AC_ARG_ENABLE([leanpsk], + [ --enable-leanpsk Enable Lean PSK build (default: disabled)], + [ ENABLED_LEANPSK=$enableval ], + [ ENABLED_LEANPSK=no ] + ) + +if test "$ENABLED_LEANPSK" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_LEANPSK -DHAVE_NULL_CIPHER -DSINGLE_THREADED -DNO_AES -DNO_FILESYSTEM -DNO_RABBIT -DNO_RSA -DNO_DSA -DNO_DH -DNO_CERTS -DNO_PWDBASED -DNO_DES3 -DNO_MD4 -DNO_MD5 -DNO_ERROR_STRINGS -DNO_OLD_TLS -DNO_RC4 -DNO_WRITEV -DNO_SESSION_CACHE -DNO_DEV_RANDOM -DWOLFSSL_USER_IO -DNO_SHA -DUSE_SLOW_SHA" + ENABLED_SLOWMATH="no" + ENABLED_SINGLETHREADED="yes" +fi + +AM_CONDITIONAL([BUILD_LEANPSK], [test "x$ENABLED_LEANPSK" = "xyes"]) + + +# big cache +AC_ARG_ENABLE([bigcache], + [ --enable-bigcache Enable big session cache (default: disabled)], + [ ENABLED_BIGCACHE=$enableval ], + [ ENABLED_BIGCACHE=no ] + ) + +if test "$ENABLED_BIGCACHE" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DBIG_SESSION_CACHE" +fi + + +# HUGE cache +AC_ARG_ENABLE([hugecache], + [ --enable-hugecache Enable huge session cache (default: disabled)], + [ ENABLED_HUGECACHE=$enableval ], + [ ENABLED_HUGECACHE=no ] + ) + +if test "$ENABLED_HUGECACHE" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHUGE_SESSION_CACHE" +fi + + +# SMALL cache +AC_ARG_ENABLE([smallcache], + [ --enable-smallcache Enable small session cache (default: disabled)], + [ ENABLED_SMALLCACHE=$enableval ], + [ ENABLED_SMALLCACHE=no ] + ) + +if test "$ENABLED_SMALLCACHE" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DSMALL_SESSION_CACHE" +fi + + +# Persistent session cache +AC_ARG_ENABLE([savesession], + [ --enable-savesession Enable persistent session cache (default: disabled)], + [ ENABLED_SAVESESSION=$enableval ], + [ ENABLED_SAVESESSION=no ] + ) + +if test "$ENABLED_SAVESESSION" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DPERSIST_SESSION_CACHE" +fi + + +# Persistent cert cache +AC_ARG_ENABLE([savecert], + [ --enable-savecert Enable persistent cert cache (default: disabled)], + [ ENABLED_SAVECERT=$enableval ], + [ ENABLED_SAVECERT=no ] + ) + +if test "$ENABLED_SAVECERT" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DPERSIST_CERT_CACHE" +fi + + +# Atomic User Record Layer +AC_ARG_ENABLE([atomicuser], + [ --enable-atomicuser Enable Atomic User Record Layer (default: disabled)], + [ ENABLED_ATOMICUSER=$enableval ], + [ ENABLED_ATOMICUSER=no ] + ) + +if test "$ENABLED_ATOMICUSER" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DATOMIC_USER" +fi + + +# Public Key Callbacks +AC_ARG_ENABLE([pkcallbacks], + [ --enable-pkcallbacks Enable Public Key Callbacks (default: disabled)], + [ ENABLED_PKCALLBACKS=$enableval ], + [ ENABLED_PKCALLBACKS=no ] + ) + +if test "$ENABLED_PKCALLBACKS" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_PK_CALLBACKS" +fi + + +# SNIFFER +AC_ARG_ENABLE([sniffer], + [AS_HELP_STRING([--enable-sniffer],[Enable wolfSSL sniffer support (default: disabled)])], + [ ENABLED_SNIFFER=$enableval ], + [ ENABLED_SNIFFER=no ] + ) + +# sniffer does't work in maxstrength mode +if test "$ENABLED_SNIFFER" = "yes" && test "$ENABLED_MAXSTRENGTH" = "yes" +then + AC_MSG_ERROR([cannot enable maxstrength in sniffer mode.]) +fi + +ENABLED_SNIFFTEST=no +AS_IF([ test "x$ENABLED_SNIFFER" = "xyes" ], + [ + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_SNIFFER -DOPENSSL_EXTRA" + AC_CHECK_HEADERS([pcap/pcap.h], + [ ENABLED_SNIFFTEST=yes ], + [ AC_MSG_WARN([cannot enable sniffer test without having libpcap available.]) ] + ) + ]) + +AM_CONDITIONAL([BUILD_SNIFFER], [ test "x$ENABLED_SNIFFER" = "xyes" ]) +AM_CONDITIONAL([BUILD_SNIFFTEST], [ test "x$ENABLED_SNIFFTEST" = "xyes" ]) + +# AES-GCM +AC_ARG_ENABLE([aesgcm], + [AS_HELP_STRING([--enable-aesgcm],[Enable wolfSSL AES-GCM support (default: enabled)])], + [ ENABLED_AESGCM=$enableval ], + [ ENABLED_AESGCM=yes ] + ) + +# lean psk does't need gcm +if test "$ENABLED_LEANPSK" = "yes" +then + ENABLED_AESGCM=no +fi + +if test "$ENABLED_AESGCM" = "word32" +then + AM_CFLAGS="$AM_CFLAGS -DGCM_WORD32" + ENABLED_AESGCM=yes +fi + +if test "$ENABLED_AESGCM" = "small" +then + AM_CFLAGS="$AM_CFLAGS -DGCM_SMALL" + ENABLED_AESGCM=yes +fi + +if test "$ENABLED_AESGCM" = "table" +then + AM_CFLAGS="$AM_CFLAGS -DGCM_TABLE" + ENABLED_AESGCM=yes +fi + +if test "$ENABLED_AESGCM" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_AESGCM" +fi + +AM_CONDITIONAL([BUILD_AESGCM], [test "x$ENABLED_AESGCM" = "xyes"]) + + +# AES-CCM +AC_ARG_ENABLE([aesccm], + [ --enable-aesccm Enable wolfSSL AES-CCM support (default: disabled)], + [ ENABLED_AESCCM=$enableval ], + [ ENABLED_AESCCM=no ] + ) + +if test "$ENABLED_AESCCM" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_AESCCM" +fi + +AM_CONDITIONAL([BUILD_AESCCM], [test "x$ENABLED_AESCCM" = "xyes"]) + + +# AES-NI +AC_ARG_ENABLE([aesni], + [AS_HELP_STRING([--enable-aesni],[Enable wolfSSL AES-NI support (default: disabled)])], + [ ENABLED_AESNI=$enableval ], + [ ENABLED_AESNI=no ] + ) + +# INTEL ASM +AC_ARG_ENABLE([intelasm], + [AS_HELP_STRING([--enable-intelasm],[Enable All Intel ASM speedups (default: disabled)])], + [ ENABLED_INTELASM=$enableval ], + [ ENABLED_INTELASM=no ] + ) + +if test "$ENABLED_AESNI" = "yes" || test "$ENABLED_INTELASM" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_AESNI" + if test "$GCC" = "yes" + then + # GCC needs these flags, icc doesn't + # opt levels greater than 2 may cause problems on systems w/o aesni + if test "$CC" != "icc" + then + AM_CFLAGS="$AM_CFLAGS -maes -msse4" + fi + fi +fi + +if test "$ENABLED_INTELASM" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_INTEL_RDGEN -DUSE_INTEL_SPEEDUP" + ENABLED_AESNI=yes +fi + +AM_CONDITIONAL([BUILD_AESNI], [test "x$ENABLED_AESNI" = "xyes"]) + + +# Camellia +AC_ARG_ENABLE([camellia], + [ --enable-camellia Enable wolfSSL Camellia support (default: disabled)], + [ ENABLED_CAMELLIA=$enableval ], + [ ENABLED_CAMELLIA=no ] + ) + +if test "$ENABLED_CAMELLIA" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_CAMELLIA" +fi + +AM_CONDITIONAL([BUILD_CAMELLIA], [test "x$ENABLED_CAMELLIA" = "xyes"]) + + +# MD2 +AC_ARG_ENABLE([md2], + [ --enable-md2 Enable wolfSSL MD2 support (default: disabled)], + [ ENABLED_MD2=$enableval ], + [ ENABLED_MD2=no ] + ) + +if test "$ENABLED_BUMP" = "yes" +then + ENABLED_MD2="yes" +fi + +if test "$ENABLED_MD2" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_MD2" +fi + +AM_CONDITIONAL([BUILD_MD2], [test "x$ENABLED_MD2" = "xyes"]) + + +# NULL CIPHER +AC_ARG_ENABLE([nullcipher], + [ --enable-nullcipher Enable wolfSSL NULL cipher support (default: disabled)], + [ ENABLED_NULL_CIPHER=$enableval ], + [ ENABLED_NULL_CIPHER=no ] + ) + +if test "$ENABLED_NULL_CIPHER" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_NULL_CIPHER" +fi + +# RIPEMD +AC_ARG_ENABLE([ripemd], + [ --enable-ripemd Enable wolfSSL RIPEMD-160 support (default: disabled)], + [ ENABLED_RIPEMD=$enableval ], + [ ENABLED_RIPEMD=no ] + ) + +if test "$ENABLED_RIPEMD" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_RIPEMD" +fi + +AM_CONDITIONAL([BUILD_RIPEMD], [test "x$ENABLED_RIPEMD" = "xyes"]) + + +# BLAKE2 +AC_ARG_ENABLE([blake2], + [ --enable-blake2 Enable wolfSSL BLAKE2 support (default: disabled)], + [ ENABLED_BLAKE2=$enableval ], + [ ENABLED_BLAKE2=no ] + ) + +if test "$ENABLED_BLAKE2" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_BLAKE2" +fi + +AM_CONDITIONAL([BUILD_BLAKE2], [test "x$ENABLED_BLAKE2" = "xyes"]) + + +# set sha512 default +SHA512_DEFAULT=no +if test "$host_cpu" = "x86_64" +then +SHA512_DEFAULT=yes +fi + +# SHA512 +AC_ARG_ENABLE([sha512], + [AS_HELP_STRING([--enable-sha512],[Enable wolfSSL SHA-512 support (default: enabled on x86_64)])], + [ ENABLED_SHA512=$enableval ], + [ ENABLED_SHA512=$SHA512_DEFAULT ] + ) + +# lean psk does't need sha512 +if test "$ENABLED_LEANPSK" = "yes" +then + ENABLED_SHA512=no +fi + +if test "$ENABLED_SHA512" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_SHA512 -DWOLFSSL_SHA384" +fi + +if test "$ENABLED_FORTRESS" = "yes" +then + ENABLED_SHA512="yes" +fi + + +AM_CONDITIONAL([BUILD_SHA512], [test "x$ENABLED_SHA512" = "xyes"]) + + +# SESSION CERTS +AC_ARG_ENABLE([sessioncerts], + [ --enable-sessioncerts Enable session cert storing (default: disabled)], + [ ENABLED_SESSIONCERTS=$enableval ], + [ ENABLED_SESSIONCERTS=no ] + ) + +if test "$ENABLED_SESSIONCERTS" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DSESSION_CERTS" +fi + + +# KEY GENERATION +AC_ARG_ENABLE([keygen], + [ --enable-keygen Enable key generation (default: disabled)], + [ ENABLED_KEYGEN=$enableval ], + [ ENABLED_KEYGEN=no ] + ) + +if test "$ENABLED_KEYGEN" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_KEY_GEN" +fi + + +# CERT GENERATION +AC_ARG_ENABLE([certgen], + [ --enable-certgen Enable cert generation (default: disabled)], + [ ENABLED_CERTGEN=$enableval ], + [ ENABLED_CERTGEN=no ] + ) + +if test "$ENABLED_CERTGEN" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_CERT_GEN" +fi + + +# CERT REQUEST GENERATION +AC_ARG_ENABLE([certreq], + [ --enable-certreq Enable cert request generation (default: disabled)], + [ ENABLED_CERTREQ=$enableval ], + [ ENABLED_CERTREQ=no ] + ) + +if test "$ENABLED_CERTREQ" = "yes" +then + if test "$ENABLED_CERTGEN" = "no" + then + AC_MSG_ERROR([cannot enable certreq without enabling certgen.]) + fi + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_CERT_REQ" +fi + + +# SEP +AC_ARG_ENABLE([sep], + [ --enable-sep Enable sep extensions (default: disabled)], + [ ENABLED_SEP=$enableval ], + [ ENABLED_SEP=no ] + ) +if test "$ENABLED_SEP" = "yes" +then + AM_CFLAGS="-DWOLFSSL_SEP -DKEEP_PEER_CERT $AM_CFLAGS" +fi + + +# HKDF +AC_ARG_ENABLE([hkdf], + [ --enable-hkdf Enable HKDF (HMAC-KDF) support (default: disabled)], + [ ENABLED_HKDF=$enableval ], + [ ENABLED_HKDF=no ] + ) +if test "$ENABLED_HKDF" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_HKDF" +fi + + +# DSA +AC_ARG_ENABLE([dsa], + [ --enable-dsa Enable DSA (default: disabled)], + [ ENABLED_DSA=$enableval ], + [ ENABLED_DSA=no ] + ) + +if test "$ENABLED_DSA" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_DSA" +fi + +AM_CONDITIONAL([BUILD_DSA], [test "x$ENABLED_DSA" = "xyes"]) + + +# set ecc default +ECC_DEFAULT=no + +if test "$host_cpu" = "x86_64" +then +ECC_DEFAULT=yes +fi + +# ECC +AC_ARG_ENABLE([ecc], + [AS_HELP_STRING([--enable-ecc],[Enable ECC (default: enabled on x86_64)])], + [ ENABLED_ECC=$enableval ], + [ ENABLED_ECC=$ECC_DEFAULT ] + ) + +# lean psk does't need ecc +if test "$ENABLED_LEANPSK" = "yes" +then + ENABLED_ECC=no +fi + +if test "$ENABLED_ECC" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_ECC -DTFM_ECC256 -DECC_SHAMIR" +fi + +AM_CONDITIONAL([BUILD_ECC], [test "x$ENABLED_ECC" = "xyes"]) + + +if test "$ENABLED_ECC" = "yes" && test "$ENABLED_SMALL" = "yes" +then + AC_MSG_ERROR([cannot enable ecc and small, ecc requires TLS which small turns off.]) +fi + + +# for using memory optimization setting on both curve25519 and ed25519 +ENABLED_CURVED25519_SMALL=no + +# CURVE25519 +AC_ARG_ENABLE([curve25519], + [AS_HELP_STRING([--enable-curve25519],[Enable Curve25519 (default: disabled)])], + [ ENABLED_CURVE25519=$enableval ], + [ ENABLED_CURVE25519=no ] + ) + + +if test "$ENABLED_CURVE25519" = "small" +then + AM_CFLAGS="$AM_CFLAGS -DCURVED25519_SMALL" + ENABLED_CURVED25519_SMALL=yes + ENABLED_CURVE25519=yes +fi + +if test "$ENABLED_CURVE25519" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_CURVE25519" + ENABLED_FEMATH=yes +fi + + +AM_CONDITIONAL([BUILD_CURVE25519], [test "x$ENABLED_CURVE25519" = "xyes"]) + + +# ED25519 +AC_ARG_ENABLE([ed25519], + [AS_HELP_STRING([--enable-ed25519],[Enable ED25519 (default: disabled)])], + [ ENABLED_ED25519=$enableval ], + [ ENABLED_ED25519=no ] + ) + + +if test "$ENABLED_ED25519" = "small" +then + AM_CFLAGS="$AM_CFLAGS -DCURVED25519_SMALL" + ENABLED_CURVED25519_SMALL=yes + ENABLED_ED25519=yes +fi + +if test "$ENABLED_ED25519" = "yes" +then + if test "$ENABLED_SHA512" = "no" + then + AC_MSG_ERROR([cannot enable ed25519 without enabling sha512.]) + fi + ENABLED_FEMATH=yes + ENABLED_GEMATH=yes + AM_CFLAGS="$AM_CFLAGS -DHAVE_ED25519" +fi + +AM_CONDITIONAL([BUILD_ED25519], [test "x$ENABLED_ED25519" = "xyes"]) +AM_CONDITIONAL([BUILD_CURVED25519_SMALL], [test "x$ENABLED_CURVED25519_SMALL" = "xyes"]) +AM_CONDITIONAL([BUILD_FEMATH], [test "x$ENABLED_FEMATH" = "xyes"]) +AM_CONDITIONAL([BUILD_GEMATH], [test "x$ENABLED_GEMATH" = "xyes"]) + +# FP ECC, Fixed Point cache ECC +AC_ARG_ENABLE([fpecc], + [ --enable-fpecc Enable Fixed Point cache ECC (default: disabled)], + [ ENABLED_FPECC=$enableval ], + [ ENABLED_FPECC=no ] + ) + +if test "$ENABLED_FPECC" = "yes" +then + if test "$ENABLED_ECC" = "no" + then + AC_MSG_ERROR([cannot enable fpecc without enabling ecc.]) + fi + AM_CFLAGS="$AM_CFLAGS -DFP_ECC" +fi + + +# ECC encrypt +AC_ARG_ENABLE([eccencrypt], + [ --enable-eccencrypt Enable ECC encrypt (default: disabled)], + [ ENABLED_ECC_ENCRYPT=$enableval ], + [ ENABLED_ECC_ENCRYPT=no ] + ) + +if test "$ENABLED_ECC_ENCRYPT" = "yes" +then + if test "$ENABLED_ECC" = "no" + then + AC_MSG_ERROR([cannot enable eccencrypt without enabling ecc.]) + fi + if test "$ENABLED_HKDF" = "no" + then + AC_MSG_ERROR([cannot enable eccencrypt without enabling hkdf.]) + fi + AM_CFLAGS="$AM_CFLAGS -DHAVE_ECC_ENCRYPT" +fi + + +# PSK +AC_ARG_ENABLE([psk], + [ --enable-psk Enable PSK (default: disabled)], + [ ENABLED_PSK=$enableval ], + [ ENABLED_PSK=no ] + ) + +if test "$ENABLED_PSK" = "no" && test "$ENABLED_LEANPSK" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_PSK" +fi + +if test "$ENABLED_PSK" = "no" && test "$ENABLED_LEANPSK" = "yes" +then + ENABLED_PSK=yes +fi + + +# ERROR STRINGS +AC_ARG_ENABLE([errorstrings], + [ --enable-errorstrings Enable error strings table (default: enabled)], + [ ENABLED_ERROR_STRINGS=$enableval ], + [ ENABLED_ERROR_STRINGS=yes ] + ) + +if test "$ENABLED_ERROR_STRINGS" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_ERROR_STRINGS" +else + # turn off error strings if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_ERROR_STRINGS" + ENABLED_ERROR_STRINGS=no + fi +fi + + +# OLD TLS +AC_ARG_ENABLE([oldtls], + [ --enable-oldtls Enable old TLS versions < 1.2 (default: enabled)], + [ ENABLED_OLD_TLS=$enableval ], + [ ENABLED_OLD_TLS=yes ] + ) + +if test "$ENABLED_OLD_TLS" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_OLD_TLS" +else + # turn off old if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_OLD_TLS" + ENABLED_OLD_TLS=no + fi +fi + + +# STACK SIZE info for examples +AC_ARG_ENABLE([stacksize], + [ --enable-stacksize Enable stack size info on examples (default: disabled)], + [ ENABLED_STACKSIZE=$enableval ], + [ ENABLED_STACKSIZE=no ] + ) + +if test "$ENABLED_STACKSIZE" = "yes" +then + AC_CHECK_FUNC([posix_memalign], [], [AC_MSG_ERROR(stacksize needs posix_memalign)]) + AC_CHECK_FUNC([pthread_attr_setstack], [], AC_CHECK_LIB([pthread],[pthread_attr_setstack])) + AM_CFLAGS="$AM_CFLAGS -DHAVE_STACK_SIZE -DWOLFSSL_LOW_MEMORY" +fi + + +# MEMORY +AC_ARG_ENABLE([memory], + [ --enable-memory Enable memory callbacks (default: enabled)], + [ ENABLED_MEMORY=$enableval ], + [ ENABLED_MEMORY=yes ] + ) + +if test "$ENABLED_MEMORY" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_WOLFSSL_MEMORY" +else + # turn off memory cb if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + # but don't turn on NO_WOLFSSL_MEMORY because using own + ENABLED_MEMORY=no + fi +fi + +AM_CONDITIONAL([BUILD_MEMORY], [test "x$ENABLED_MEMORY" = "xyes"]) + + +# RSA +AC_ARG_ENABLE([rsa], + [ --enable-rsa Enable RSA (default: enabled)], + [ ENABLED_RSA=$enableval ], + [ ENABLED_RSA=yes ] + ) + +if test "$ENABLED_RSA" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_RSA" +else + # turn off RSA if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_RSA" + ENABLED_RSA=no + fi +fi + +AM_CONDITIONAL([BUILD_RSA], [test "x$ENABLED_RSA" = "xyes"]) + + +# DH +AC_ARG_ENABLE([dh], + [AS_HELP_STRING([--enable-dh],[Enable DH (default: enabled)])], + [ ENABLED_DH=$enableval ], + [ ENABLED_DH=yes ] + ) + +if test "$ENABLED_DH" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_DH" +else + # turn off DH if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_DH" + ENABLED_DH=no + fi +fi + +AM_CONDITIONAL([BUILD_DH], [test "x$ENABLED_DH" = "xyes"]) + + +# Anonymous +AC_ARG_ENABLE([anon], + [AS_HELP_STRING([--enable-anon],[Enable Anonymous (default: disabled)])], + [ ENABLED_ANON=$enableval ], + [ ENABLED_ANON=no ] + ) + + +if test "x$ENABLED_ANON" = "xyes" +then + if test "x$ENABLED_DH" != "xyes" + then + AC_MSG_ERROR([Anonymous suite requires DH.]) + fi + AM_CFLAGS="$AM_CFLAGS -DHAVE_ANON" +fi + + +# ASN +# turn off asn, which means no certs, no rsa, no dsa, no ecc, +# and no big int (unless dh is on) +AC_ARG_ENABLE([asn], + [ --enable-asn Enable ASN (default: enabled)], + [ ENABLED_ASN=$enableval ], + [ ENABLED_ASN=yes ] + ) + +if test "$ENABLED_ASN" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_ASN -DNO_CERTS" + if test "$ENABLED_DH" = "no" + then + # DH needs bigint + AM_CFLAGS="$AM_CFLAGS -DNO_BIG_INT" + fi +else + # turn off ASN if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_ASN -DNO_CERTS -DNO_BIG_INT" + ENABLED_ASN=no + fi +fi + +if test "$ENABLED_RSA" = "yes" && test "$ENABLED_ASN" = "no" +then + AC_MSG_ERROR([please disable rsa if disabling asn.]) +fi + +if test "$ENABLED_DSA" = "yes" && test "$ENABLED_ASN" = "no" +then + AC_MSG_ERROR([please disable dsa if disabling asn.]) +fi + +if test "$ENABLED_ECC" = "yes" && test "$ENABLED_ASN" = "no" +then + AC_MSG_ERROR([please disable ecc if disabling asn.]) +fi + +if test "$ENABLED_PSK" = "no" && test "$ENABLED_ASN" = "no" +then + AC_MSG_ERROR([please enable psk if disabling asn.]) +fi + +# DH needs bigint +if test "$ENABLED_ASN" = "no" && test "$ENABLED_DH" = "no" +then + ENABLED_FASTMATH=no + ENABLED_SLOWMATH=no +fi + +AM_CONDITIONAL([BUILD_ASN], [test "x$ENABLED_ASN" = "xyes"]) + + +# AES +AC_ARG_ENABLE([aes], + [ --enable-aes Enable AES (default: enabled)], + [ ENABLED_AES=$enableval ], + [ ENABLED_AES=yes ] + ) + +if test "$ENABLED_AES" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_AES" + if test "$ENABLED_AESGCM" = "yes" + then + AC_MSG_ERROR([AESGCM requires AES.]) + fi + if test "$ENABLED_AESCCM" = "yes" + then + AC_MSG_ERROR([AESCCM requires AES.]) + fi +else + # turn off AES if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_AES" + ENABLED_AES=no + fi +fi + +AM_CONDITIONAL([BUILD_AES], [test "x$ENABLED_AES" = "xyes"]) + + +# CODING +AC_ARG_ENABLE([coding], + [ --enable-coding Enable Coding base 16/64 (default: enabled)], + [ ENABLED_CODING=$enableval ], + [ ENABLED_CODING=yes ] + ) + +if test "$ENABLED_CODING" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_CODING" +else + # turn off CODING if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_CODING" + ENABLED_CODING=no + fi +fi + +AM_CONDITIONAL([BUILD_CODING], [test "x$ENABLED_CODING" = "xyes"]) + + +# DES3 +AC_ARG_ENABLE([des3], + [ --enable-des3 Enable DES3 (default: enabled)], + [ ENABLED_DES3=$enableval ], + [ ENABLED_DES3=yes ] + ) + +if test "$ENABLED_DES3" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_DES3" +else + # turn off DES3 if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_DES3" + ENABLED_DES3=no + fi +fi + +AM_CONDITIONAL([BUILD_DES3], [test "x$ENABLED_DES3" = "xyes"]) + + +# ARC4 +AC_ARG_ENABLE([arc4], + [ --enable-arc4 Enable ARC4 (default: disabled)], + [ ENABLED_ARC4=$enableval ], + [ ENABLED_ARC4=no ] + ) + +if test "$ENABLED_ARC4" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_RC4" +else + # turn off ARC4 if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_RC4" + ENABLED_ARC4=no + fi +fi + +AM_CONDITIONAL([BUILD_RC4], [test "x$ENABLED_ARC4" = "xyes"]) + + +# MD5 +AC_ARG_ENABLE([md5], + [ --enable-md5 Enable MD5 (default: enabled)], + [ ENABLED_MD5=$enableval ], + [ ENABLED_MD5=yes ] + ) + +if test "$ENABLED_MD5" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_MD5 -DNO_OLD_TLS" +else + # turn off MD5 if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_MD5 -DNO_OLD_TLS" + ENABLED_MD5=no + fi +fi + +AM_CONDITIONAL([BUILD_MD5], [test "x$ENABLED_MD5" = "xyes"]) + + +# SHA +AC_ARG_ENABLE([sha], + [ --enable-sha Enable SHA (default: enabled)], + [ ENABLED_SHA=$enableval ], + [ ENABLED_SHA=yes ] + ) + +if test "$ENABLED_SHA" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_SHA -DNO_OLD_TLS" +else + # turn off SHA if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_SHA -DNO_OLD_TLS" + ENABLED_SHA=no + fi +fi + +AM_CONDITIONAL([BUILD_SHA], [test "x$ENABLED_SHA" = "xyes"]) + + +# MD4 +AC_ARG_ENABLE([md4], + [ --enable-md4 Enable MD4 (default: disabled)], + [ ENABLED_MD4=$enableval ], + [ ENABLED_MD4=no ] + ) + +if test "$ENABLED_MD4" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_MD4" +fi + +AM_CONDITIONAL([BUILD_MD4], [test "x$ENABLED_MD4" = "xyes"]) + + +# Web Server Build +AC_ARG_ENABLE([webserver], + [ --enable-webserver Enable Web Server (default: disabled)], + [ ENABLED_WEBSERVER=$enableval ], + [ ENABLED_WEBSERVER=no ] + ) + +if test "$ENABLED_WEBSERVER" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_WEBSERVER" +fi + + + +# HC128 +AC_ARG_ENABLE([hc128], + [ --enable-hc128 Enable HC-128 (default: disabled)], + [ ENABLED_HC128=$enableval ], + [ ENABLED_HC128=no ] + ) + +if test "$ENABLED_HC128" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_HC128" +else + AM_CFLAGS="$AM_CFLAGS -DHAVE_HC128" +fi + +AM_CONDITIONAL([BUILD_HC128], [test "x$ENABLED_HC128" = "xyes"]) + + +# RABBIT +AC_ARG_ENABLE([rabbit], + [ --enable-rabbit Enable RABBIT (default: disabled)], + [ ENABLED_RABBIT=$enableval ], + [ ENABLED_RABBIT=no ] + ) + +if test "$ENABLED_RABBIT" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_RABBIT" +else + AM_CFLAGS="$AM_CFLAGS -DHAVE_RABBIT" +fi + +AM_CONDITIONAL([BUILD_RABBIT], [test "x$ENABLED_RABBIT" = "xyes"]) + + +# FIPS +AC_ARG_ENABLE([fips], + [AS_HELP_STRING([--enable-fips],[Enable FIPS 140-2, Will NOT work w/o FIPS license (default: disabled)])], + [ ENABLED_FIPS=$enableval ], + [ ENABLED_FIPS=no ] + ) + +if test "x$ENABLED_FIPS" = "xyes" +then + # requires thread local storage + if test "$thread_ls_on" = "no" + then + AC_MSG_ERROR([FIPS requires Thread Local Storage]) + fi + # requires SHA512 + if test "x$ENABLED_SHA512" = "xno" + then + ENABLED_SHA512="yes" + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_SHA512 -DWOLFSSL_SHA384" + AM_CONDITIONAL([BUILD_SHA512], [test "x$ENABLED_SHA512" = "xyes"]) + fi + # requires AESGCM + if test "x$ENABLED_AESGCM" != "xyes" + then + ENABLED_AESGCM="yes" + AM_CFLAGS="$AM_CFLAGS -DHAVE_AESGCM" + AM_CONDITIONAL([BUILD_SHA512], [test "x$ENABLED_SHA512" = "xyes"]) + fi + AM_CFLAGS="$AM_CFLAGS -DHAVE_FIPS" +fi + +AM_CONDITIONAL([BUILD_FIPS], [test "x$ENABLED_FIPS" = "xyes"]) + + +# set POLY1305 default +POLY1305_DEFAULT=yes + +if test "x$ENABLED_FIPS" = "xyes" +then +POLY1305_DEFAULT=no +fi + +# POLY1305 +AC_ARG_ENABLE([poly1305], + [AS_HELP_STRING([--enable-poly1305],[Enable wolfSSL POLY1305 support (default: enabled)])], + [ ENABLED_POLY1305=$enableval ], + [ ENABLED_POLY1305=$POLY1305_DEFAULT] + ) + +# lean psk does't need poly1305 +if test "$ENABLED_LEANPSK" = "yes" +then + ENABLED_POLY1305=no +fi + +if test "$ENABLED_POLY1305" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_POLY1305 -DHAVE_ONE_TIME_AUTH" +fi + +AM_CONDITIONAL([BUILD_POLY1305], [test "x$ENABLED_POLY1305" = "xyes"]) + + +# set CHACHA default +CHACHA_DEFAULT=yes + +if test "x$ENABLED_FIPS" = "xyes" +then +CHACHA_DEFAULT=no +fi + +# CHACHA +AC_ARG_ENABLE([chacha], + [ --enable-chacha Enable CHACHA (default: enabled)], + [ ENABLED_CHACHA=$enableval ], + [ ENABLED_CHACHA=$CHACHA_DEFAULT] + ) + +# lean psk does't need chacha +if test "$ENABLED_LEANPSK" = "yes" +then + ENABLED_CHACHA=no +fi + +if test "$ENABLED_CHACHA" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_CHACHA" +fi + +AM_CONDITIONAL([BUILD_CHACHA], [test "x$ENABLED_CHACHA" = "xyes"]) + + +# Hash DRBG +AC_ARG_ENABLE([hashdrbg], + [ --enable-hashdrbg Enable Hash DRBG support (default: enabled)], + [ ENABLED_HASHDRBG=$enableval ], + [ ENABLED_HASHDRBG=yes ] + ) + +if test "x$ENABLED_HASHDRBG" = "xyes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_HASHDRBG" +else + # turn on Hash DRBG if FIPS is on or ARC4 is off + if test "x$ENABLED_FIPS" = "xyes" || test "x$ENABLED_ARC4" = "xno" + then + AM_CFLAGS="$AM_CFLAGS -DHAVE_HASHDRBG" + ENABLED_HASHDRBG=yes + fi +fi + + +# Filesystem Build +AC_ARG_ENABLE([filesystem], + [ --enable-filesystem Enable Filesystem support (default: enabled)], + [ ENABLED_FILESYSTEM=$enableval ], + [ ENABLED_FILESYSTEM=yes ] + ) + +if test "$ENABLED_FILESYSTEM" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_FILESYSTEM" +else + # turn off filesystem if leanpsk on + if test "$ENABLED_LEANPSK" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DNO_FILESYSTEM" + ENABLED_FILESYSTEM=no + fi +fi + + +# inline Build +AC_ARG_ENABLE([inline], + [ --enable-inline Enable inline functions (default: enabled)], + [ ENABLED_INLINE=$enableval ], + [ ENABLED_INLINE=yes ] + ) + +if test "$ENABLED_INLINE" = "no" +then + AM_CFLAGS="$AM_CFLAGS -DNO_INLINE" +fi + +AM_CONDITIONAL([BUILD_INLINE], [test "x$ENABLED_INLINE" = "xyes"]) + + +# OCSP +AC_ARG_ENABLE([ocsp], + [ --enable-ocsp Enable OCSP (default: disabled)], + [ ENABLED_OCSP=$enableval ], + [ ENABLED_OCSP=no ], + ) + +if test "$ENABLED_OCSP" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_OCSP" +fi + +AM_CONDITIONAL([BUILD_OCSP], [test "x$ENABLED_OCSP" = "xyes"]) + + +if test "$ENABLED_OCSP" = "yes" +then + # check openssl command tool for testing ocsp + AC_CHECK_PROG([HAVE_OPENSSL_CMD],[openssl],[yes],[no]) + + if test "$HAVE_OPENSSL_CMD" = "yes" + then + AM_CFLAGS="$AM_CFLAGS -DHAVE_OPENSSL_CMD" + else + AC_MSG_WARN([openssl command line tool not available for testing ocsp]) + fi +fi + + +# CRL +AC_ARG_ENABLE([crl], + [ --enable-crl Enable CRL (default: disabled)], + [ ENABLED_CRL=$enableval ], + [ ENABLED_CRL=no ], + ) + +if test "$ENABLED_CRL" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_CRL" +fi + +AM_CONDITIONAL([BUILD_CRL], [test "x$ENABLED_CRL" = "xyes"]) + + +# CRL Monitor +AC_ARG_ENABLE([crl-monitor], + [ --enable-crl-monitor Enable CRL Monitor (default: disabled)], + [ ENABLED_CRL_MONITOR=$enableval ], + [ ENABLED_CRL_MONITOR=no ], + ) + +if test "$ENABLED_CRL_MONITOR" = "yes" +then + case $host_os in + *linux* | *darwin* | *freebsd*) + AM_CFLAGS="$AM_CFLAGS -DHAVE_CRL_MONITOR" ;; + *) + AC_MSG_ERROR([crl monitor only allowed on linux, OS X, or freebsd]) ;; + esac +fi + +AM_CONDITIONAL([BUILD_CRL_MONITOR], [test "x$ENABLED_CRL_MONITOR" = "xyes"]) + + +# NTRU +ENABLED_NTRU="no" +tryntrudir="" +AC_ARG_WITH([ntru], + [ --with-ntru=PATH Path to NTRU install (default /usr/) ], + [ + AC_MSG_CHECKING([for NTRU]) + CPPFLAGS="$CPPFLAGS -DHAVE_NTRU" + LIBS="$LIBS -lNTRUEncrypt" + + AC_LINK_IFELSE([AC_LANG_PROGRAM([[#include ]], [[ ntru_crypto_drbg_instantiate(0, 0, 0, 0, 0); ]])], [ ntru_linked=yes ],[ ntru_linked=no ]) + + if test "x$ntru_linked" == "xno" ; then + if test "x$withval" != "xno" ; then + tryntrudir=$withval + fi + if test "x$withval" == "xyes" ; then + tryntrudir="/usr" + fi + + LDFLAGS="$AM_LDFLAGS -L$tryntrudir/lib" + CPPFLAGS="$CPPFLAGS -I$tryntrudir/include" + + AC_LINK_IFELSE([AC_LANG_PROGRAM([[#include ]], [[ ntru_crypto_drbg_instantiate(0, 0, 0, 0, 0); ]])], [ ntru_linked=yes ],[ ntru_linked=no ]) + + if test "x$ntru_linked" == "xno" ; then + AC_MSG_ERROR([NTRU isn't found. + If it's already installed, specify its path using --with-ntru=/dir/]) + fi + AC_MSG_RESULT([yes]) + AM_LDFLAGS="$AM_LDFLAGS -L$tryntrudir/lib" + else + AC_MSG_RESULT([yes]) + fi + + AM_CFLAGS="$AM_CFLAGS -DHAVE_NTRU" + ENABLED_NTRU="yes" + ] +) + +AM_CONDITIONAL([BUILD_NTRU], [test "x$ENABLED_NTRU" = "xyes"]) + +if test "$ENABLED_NTRU" = "yes" && test "$ENABLED_SMALL" = "yes" +then + AC_MSG_ERROR([cannot enable ntru and small, ntru requires TLS which small turns off.]) +fi + +# SNI +AC_ARG_ENABLE([sni], + [ --enable-sni Enable SNI (default: disabled)], + [ ENABLED_SNI=$enableval ], + [ ENABLED_SNI=no ] + ) + +if test "x$ENABLED_SNI" = "xyes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_TLS_EXTENSIONS -DHAVE_SNI" +fi + +# Maximum Fragment Length +AC_ARG_ENABLE([maxfragment], + [ --enable-maxfragment Enable Maximum Fragment Length (default: disabled)], + [ ENABLED_MAX_FRAGMENT=$enableval ], + [ ENABLED_MAX_FRAGMENT=no ] + ) + +if test "x$ENABLED_MAX_FRAGMENT" = "xyes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_TLS_EXTENSIONS -DHAVE_MAX_FRAGMENT" +fi + +# Truncated HMAC +AC_ARG_ENABLE([truncatedhmac], + [ --enable-truncatedhmac Enable Truncated HMAC (default: disabled)], + [ ENABLED_TRUNCATED_HMAC=$enableval ], + [ ENABLED_TRUNCATED_HMAC=no ] + ) + +if test "x$ENABLED_TRUNCATED_HMAC" = "xyes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_TLS_EXTENSIONS -DHAVE_TRUNCATED_HMAC" +fi + +# Renegotiation Indication - (FAKE Secure Renegotiation) +AC_ARG_ENABLE([renegotiation-indication], + [AS_HELP_STRING([--enable-renegotiation-indication],[Enable Renegotiation Indication (default: disabled)])], + [ ENABLED_RENEGOTIATION_INDICATION=$enableval ], + [ ENABLED_RENEGOTIATION_INDICATION=no ] + ) + +if test "x$ENABLED_RENEGOTIATION_INDICATION" = "xyes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_RENEGOTIATION_INDICATION" +fi + +# Secure Renegotiation +AC_ARG_ENABLE([secure-renegotiation], + [AS_HELP_STRING([--enable-secure-renegotiation],[Enable Secure Renegotiation (default: disabled)])], + [ ENABLED_SECURE_RENEGOTIATION=$enableval ], + [ ENABLED_SECURE_RENEGOTIATION=no ] + ) + +if test "x$ENABLED_SECURE_RENEGOTIATION" = "xyes" +then + if test "x$ENABLED_RENEGOTIATION_INDICATION" = "xyes" + then + AC_MSG_ERROR([cannot enable renegotiation-indication and secure-renegotiation.]) + fi + AM_CFLAGS="$AM_CFLAGS -DHAVE_TLS_EXTENSIONS -DHAVE_SECURE_RENEGOTIATION" +fi + +# Supported Elliptic Curves Extensions +AC_ARG_ENABLE([supportedcurves], + [AS_HELP_STRING([--enable-supportedcurves],[Enable Supported Elliptic Curves (default: disabled)])], + [ ENABLED_SUPPORTED_CURVES=$enableval ], + [ ENABLED_SUPPORTED_CURVES=no ] + ) + +if test "x$ENABLED_SUPPORTED_CURVES" = "xyes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_TLS_EXTENSIONS -DHAVE_SUPPORTED_CURVES" +fi + +# Session Ticket Extension +AC_ARG_ENABLE([session-ticket], + [AS_HELP_STRING([--enable-session-ticket],[Enable Session Ticket (default: disabled)])], + [ ENABLED_SESSION_TICKET=$enableval ], + [ ENABLED_SESSION_TICKET=no ] + ) + +if test "x$ENABLED_SESSION_TICKET" = "xyes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_TLS_EXTENSIONS -DHAVE_SESSION_TICKET" +fi + +# TLS Extensions +AC_ARG_ENABLE([tlsx], + [ --enable-tlsx Enable all TLS Extensions (default: disabled)], + [ ENABLED_TLSX=$enableval ], + [ ENABLED_TLSX=no ] + ) + +if test "x$ENABLED_TLSX" = "xyes" +then + ENABLED_SNI=yes + ENABLED_MAX_FRAGMENT=yes + ENABLED_TRUNCATED_HMAC=yes + ENABLED_SUPPORTED_CURVES=yes + AM_CFLAGS="$AM_CFLAGS -DHAVE_TLS_EXTENSIONS -DHAVE_SNI -DHAVE_MAX_FRAGMENT -DHAVE_TRUNCATED_HMAC -DHAVE_SUPPORTED_CURVES" +fi + +# PKCS7 +AC_ARG_ENABLE([pkcs7], + [ --enable-pkcs7 Enable PKCS7 (default: disabled)], + [ ENABLED_PKCS7=$enableval ], + [ ENABLED_PKCS7=no ], + ) + +if test "$ENABLED_PKCS7" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_PKCS7" +fi + +AM_CONDITIONAL([BUILD_PKCS7], [test "x$ENABLED_PKCS7" = "xyes"]) + + +# Simple Certificate Enrollment Protocol (SCEP) +AC_ARG_ENABLE([scep], + [ --enable-scep Enable wolfSCEP (default: disabled)], + [ ENABLED_WOLFSCEP=$enableval ], + [ ENABLED_WOLFSCEP=no ] + ) +if test "$ENABLED_WOLFSCEP" = "yes" +then + # Enable prereqs if not already enabled + if test "x$ENABLED_KEYGEN" = "xno" + then + ENABLED_KEYGEN="yes" + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_KEY_GEN" + fi + if test "x$ENABLED_CERTGEN" = "xno" + then + ENABLED_CERTGEN="yes" + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_CERT_GEN" + fi + if test "x$ENABLED_CERTREQ" = "xno" + then + ENABLED_CERTREQ="yes" + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_CERT_REQ" + fi + if test "x$ENABLED_PKCS7" = "xno" + then + ENABLED_PKCS7="yes" + AM_CFLAGS="$AM_CFLAGS -DHAVE_PKCS7" + AM_CONDITIONAL([BUILD_PKCS7], [test "x$ENABLED_PKCS7" = "xyes"]) + fi + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_HAVE_WOLFSCEP" +fi + + +# Small Stack +AC_ARG_ENABLE([smallstack], + [ --enable-smallstack Enable Small Stack Usage (default: disabled)], + [ ENABLED_SMALL_STACK=$enableval ], + [ ENABLED_SMALL_STACK=no ] + ) + +if test "x$ENABLED_SMALL_STACK" = "xyes" +then + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_SMALL_STACK" +fi + + +#valgrind +AC_ARG_ENABLE([valgrind], + [ --enable-valgrind Enable valgrind for unit tests (default: disabled)], + [ ENABLED_VALGRIND=$enableval ], + [ ENABLED_VALGRIND=no ] + ) + +if test "$ENABLED_VALGRIND" = "yes" +then + AC_CHECK_PROG([HAVE_VALGRIND],[valgrind],[yes],[no]) + + if test "$HAVE_VALGRIND" = "no" + then + AC_MSG_ERROR([Valgrind not found.]) + fi + enable_shared=no + enable_static=yes + AM_CFLAGS="$AM_CFLAGS -DHAVE_VALGRIND" +fi + +AM_CONDITIONAL([USE_VALGRIND], [test "x$ENABLED_VALGRIND" = "xyes"]) + + +# Test certs, use internal cert functions for extra testing +AC_ARG_ENABLE([testcert], + [ --enable-testcert Enable Test Cert (default: disabled)], + [ ENABLED_TESTCERT=$enableval ], + [ ENABLED_TESTCERT=no ] + ) + +if test "$ENABLED_TESTCERT" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_TEST_CERT" +fi + + +# I/O Pool, an example to show user how to override memory handler and use +# a pool for the input/output buffer requests +AC_ARG_ENABLE([iopool], + [ --enable-iopool Enable I/O Pool example (default: disabled)], + [ ENABLED_IOPOOL=$enableval ], + [ ENABLED_IOPOOL=no ] + ) + +if test "$ENABLED_IOPOOL" = "yes" +then + if test "$thread_ls_on" = "no" + then + AC_MSG_ERROR([I/O Pool example requires Thread Local Storage]) + fi + AM_CFLAGS="$AM_CFLAGS -DHAVE_IO_POOL -DXMALLOC_USER" +fi + + +# Certificate Service Support +AC_ARG_ENABLE([certservice], + [ --enable-certservice Enable cert service (default: disabled)], + [ ENABLED_CERT_SERVICE=$enableval ], + [ ENABLED_CERT_SERVICE=no ] + ) +if test "$ENABLED_CERT_SERVICE" = "yes" +then + # Requires ecc,certgen, and opensslextra make sure on + if test "x$ENABLED_CERTGEN" = "xno" + then + ENABLED_CERTGEN="yes" + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_CERT_GEN" + fi + if test "x$ENABLED_ECC" = "xno" + then + ENABLED_ECC="yes" + AM_CFLAGS="$AM_CFLAGS -DHAVE_ECC -DTFM_ECC256 -DECC_SHAMIR" + AM_CONDITIONAL([BUILD_ECC], [test "x$ENABLED_ECC" = "xyes"]) + fi + if test "x$ENABLED_OPENSSLEXTRA" = "xno" + then + ENABLED_OPENSSLEXTRA="yes" + AM_CFLAGS="-DOPENSSL_EXTRA $AM_CFLAGS" + fi + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_HAVE_CERT_SERVICE" +fi + + +# PWDBASED has to come after certservice since we want it on w/o explicit on +# PWDBASED +AC_ARG_ENABLE([pwdbased], + [ --enable-pwdbased Enable PWDBASED (default: disabled)], + [ ENABLED_PWDBASED=$enableval ], + [ ENABLED_PWDBASED=no ] + ) + +if test "$ENABLED_PWDBASED" = "no" +then + if test "$ENABLED_OPENSSLEXTRA" = "yes" || test "$ENABLED_WEBSERVER" = "yes" + then + # opensslextra and webserver needs pwdbased + ENABLED_PWDBASED=yes + else + AM_CFLAGS="$AM_CFLAGS -DNO_PWDBASED" + fi +fi + +AM_CONDITIONAL([BUILD_PWDBASED], [test "x$ENABLED_PWDBASED" = "xyes"]) + + +# set fastmath default +FASTMATH_DEFAULT=no + +if test "$host_cpu" = "x86_64" +then +FASTMATH_DEFAULT=yes +fi + +# fastmath +AC_ARG_ENABLE([fastmath], + [ --enable-fastmath Enable fast math ops (default: enabled on x86_64)], + [ ENABLED_FASTMATH=$enableval ], + [ ENABLED_FASTMATH=$FASTMATH_DEFAULT] + ) + +if test "x$ENABLED_FASTMATH" = "xyes" +then + # turn off fastmth if leanpsk on or asn off (w/o dh) + if test "$ENABLED_LEANPSK" = "yes" || test "$ENABLED_ASN" = "no" + then + if test "$ENABLED_DH" = "no" + then + ENABLED_FASTMATH=no + else + AM_CFLAGS="$AM_CFLAGS -DUSE_FAST_MATH" + ENABLED_SLOWMATH="no" + fi + else + AM_CFLAGS="$AM_CFLAGS -DUSE_FAST_MATH" + ENABLED_SLOWMATH="no" + fi + if test "$host_cpu" = "x86_64" + then + # Have settings.h set FP_MAX_BITS higher if user didn't set directly + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_X86_64_BUILD" + fi +fi + + +# fast HUGE math +AC_ARG_ENABLE([fasthugemath], + [ --enable-fasthugemath Enable fast math + huge code (default: disabled)], + [ ENABLED_FASTHUGEMATH=$enableval ], + [ ENABLED_FASTHUGEMATH=no ] + ) + +if test "$ENABLED_BUMP" = "yes" +then + ENABLED_FASTHUGEMATH="yes" +fi + +if test "$ENABLED_FASTHUGEMATH" = "yes" +then + ENABLED_FASTMATH="yes" + AM_CFLAGS="$AM_CFLAGS -DUSE_FAST_MATH" + ENABLED_SLOWMATH="no" +fi + +AM_CONDITIONAL([BUILD_FASTMATH], [test "x$ENABLED_FASTMATH" = "xyes"]) +AM_CONDITIONAL([BUILD_SLOWMATH], [test "x$ENABLED_SLOWMATH" = "xyes"]) + + +# Enable Examples, used to disable examples +AC_ARG_ENABLE([examples], + [ --enable-examples Enable Examples (default: enabled)], + [ ENABLED_EXAMPLES=$enableval ], + [ ENABLED_EXAMPLES=yes ] + ) + +AS_IF([test "x$ENABLED_FILESYSTEM" = "xno"], [ENABLED_EXAMPLES="no"]) +AS_IF([test "x$ENABLED_INLINE" = "xno"], [ENABLED_EXAMPLES="no"]) +AM_CONDITIONAL([BUILD_EXAMPLES], [test "x$ENABLED_EXAMPLES" = "xyes"]) + + +# LIBZ +ENABLED_LIBZ="no" +trylibzdir="" +AC_ARG_WITH([libz], + [ --with-libz=PATH PATH to libz install (default /usr/) ], + [ + AC_MSG_CHECKING([for libz]) + CPPFLAGS="$CPPFLAGS -DHAVE_LIBZ" + LIBS="$LIBS -lz" + + AC_LINK_IFELSE([AC_LANG_PROGRAM([[#include ]], [[ deflateInit(0, 8); ]])],[ libz_linked=yes ],[ libz_linked=no ]) + + if test "x$libz_linked" == "xno" ; then + if test "x$withval" != "xno" ; then + trylibzdir=$withval + fi + if test "x$withval" == "xyes" ; then + trylibzdir="/usr" + fi + + AM_LDFLAGS="$AM_LDFLAGS -L$trylibzdir/lib" + CPPFLAGS="$CPPFLAGS -I$trylibzdir/include" + + AC_LINK_IFELSE([AC_LANG_PROGRAM([[#include ]], [[ deflateInit(0, 8); ]])],[ libz_linked=yes ],[ libz_linked=no ]) + + if test "x$libz_linked" == "xno" ; then + AC_MSG_ERROR([libz isn't found. + If it's already installed, specify its path using --with-libz=/dir/]) + fi + AC_MSG_RESULT([yes]) + else + AC_MSG_RESULT([yes]) + fi + ENABLED_LIBZ="yes" + ] +) +AM_CONDITIONAL([BUILD_LIBZ], [test "x$ENABLED_LIBZ" = "xyes"]) + + +# cavium +trycaviumdir="" +AC_ARG_WITH([cavium], + [ --with-cavium=PATH PATH to cavium/software dir ], + [ + AC_MSG_CHECKING([for cavium]) + CPPFLAGS="$CPPFLAGS -DHAVE_CAVIUM" + + if test "x$withval" == "xyes" ; then + AC_MSG_ERROR([need a PATH for --with-cavium]) + fi + if test "x$withval" != "xno" ; then + trycaviumdir=$withval + fi + + LDFLAGS="$AM_LDFLAGS $trycaviumdir/api/cavium_common.o" + CPPFLAGS="$CPPFLAGS -I$trycaviumdir/include" + + AC_LINK_IFELSE([AC_LANG_PROGRAM([[#include "cavium_common.h"]], [[ CspShutdown(CAVIUM_DEV_ID); ]])],[ cavium_linked=yes ],[ cavium_linked=no ]) + + if test "x$cavium_linked" == "xno" ; then + AC_MSG_ERROR([cavium isn't found. + If it's already installed, specify its path using --with-cavium=/dir/]) + fi + AC_MSG_RESULT([yes]) + enable_shared=no + enable_static=yes + ] +) + + +# microchip api +AC_ARG_ENABLE([mcapi], + [ --enable-mcapi Enable Microchip API (default: disabled)], + [ ENABLED_MCAPI=$enableval ], + [ ENABLED_MCAPI=no ] + ) + +if test "$ENABLED_MCAPI" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -DHAVE_MCAPI -DWOLFSSL_AES_COUNTER -DWOLFSSL_AES_DIRECT" +fi + +if test "$ENABLED_MCAPI" = "yes" && test "$ENABLED_SHA512" = "no" +then + AC_MSG_ERROR([please enable sha512 if enabling mcapi.]) +fi + +if test "$ENABLED_MCAPI" = "yes" && test "$ENABLED_ECC" = "no" +then + AC_MSG_ERROR([please enable ecc if enabling mcapi.]) +fi + +if test "$ENABLED_MCAPI" = "yes" && test "$ENABLED_LIBZ" = "no" +then + AC_MSG_ERROR([please use --with-libz if enabling mcapi.]) +fi + +AM_CONDITIONAL([BUILD_MCAPI], [test "x$ENABLED_MCAPI" = "xyes"]) + + +# wolfSSL JNI +AC_ARG_ENABLE([jni], + [ --enable-jni Enable wolfSSL JNI (default: disabled)], + [ ENABLED_JNI=$enableval ], + [ ENABLED_JNI=no ] + ) +if test "$ENABLED_JNI" = "yes" +then + # Enable prereqs if not already enabled + if test "x$ENABLED_DTLS" = "xno" + then + ENABLED_DTLS="yes" + AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_DTLS" + fi + if test "x$ENABLED_OPENSSLEXTRA" = "xno" + then + ENABLED_OPENSSLEXTRA="yes" + AM_CFLAGS="$AM_CFLAGS -DOPENSSL_EXTRA" + fi + if test "x$ENABLED_CRL" = "xno" + then + ENABLED_CRL="yes" + AM_CFLAGS="$AM_CFLAGS -DHAVE_CRL" + AM_CONDITIONAL([BUILD_CRL], [test "x$ENABLED_CRL" = "xyes"]) + fi + if test "x$ENABLED_OCSP" = "xno" + then + ENABLED_OCSP="yes" + AM_CFLAGS="$AM_CFLAGS -DHAVE_OCSP" + AM_CONDITIONAL([BUILD_OCSP], [test "x$ENABLED_OCSP" = "xyes"]) + fi + if test "x$ENABLED_CRL_MONITOR" = "xno" + then + ENABLED_CRL_MONITOR="yes" + AM_CFLAGS="$AM_CFLAGS -DHAVE_CRL_MONITOR" + fi + if test "x$ENABLED_SAVESESSION" = "xno" + then + ENABLED_SAVESESSION="yes" + AM_CFLAGS="$AM_CFLAGS -DPERSIST_SESSION_CACHE" + fi + if test "x$ENABLED_SAVECERT" = "xno" + then + ENABLED_SAVECERT="yes" + AM_CFLAGS="$AM_CFLAGS -DPERSIST_CERT_CACHE" + fi + if test "x$ENABLED_ATOMICUSER" = "xno" + then + ENABLED_ATOMICUSER="yes" + AM_CFLAGS="$AM_CFLAGS -DATOMIC_USER" + fi + if test "x$ENABLED_ECC" = "xno" + then + ENABLED_ECC="yes" + AM_CFLAGS="$AM_CFLAGS -DHAVE_ECC" + fi + if test "x$ENABLED_PKCALLBACKS" = "xno" + then + ENABLED_PKCALLBACKS="yes" + AM_CFLAGS="$AM_CFLAGS -DHAVE_PK_CALLBACKS" + fi + if test "x$ENABLED_DH" = "xno" + then + ENABLED_DH="yes" + AM_CFLAGS="$AM_CFLAGS -DHAVE_DH" + fi +fi + + +# Check for build-type conflicts +AS_IF([test "x$ENABLED_MAXSTRENGTH" = "xyes" && \ + test "x$ENABLED_LEANPSK" = "xyes"], + [AC_MSG_ERROR([Cannot use Max Strength and Lean PSK at the same time.])]) + + +# Update CFLAGS based on options +AS_IF([test "x$ENABLED_MAXSTRENGTH" = "xyes"], + [AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_MAX_STRENGTH"]) + +AS_IF([test "x$ENABLED_MAXSTRENGTH" = "xyes" && \ + test "x$ENABLED_OLD_TLS" = "xyes"], + [AM_CFLAGS="$AM_CFLAGS -DNO_OLD_TLS" + ENABLED_OLD_TLS=no]) + + +# OPTIMIZE FLAGS +if test "$GCC" = "yes" +then + AM_CFLAGS="$AM_CFLAGS -Wall -Wno-unused" + if test "$ax_enable_debug" = "no" + then + if test "$ENABLED_FASTMATH" = "yes" + then + AM_CFLAGS="$AM_CFLAGS $OPTIMIZE_FAST_CFLAGS" + if test "$ENABLED_FASTHUGEMATH" = "yes" + then + AM_CFLAGS="$AM_CFLAGS $OPTIMIZE_HUGE_CFLAGS" + fi + else + AM_CFLAGS="$AM_CFLAGS $OPTIMIZE_CFLAGS" + fi + fi +fi + +# ICC command line warning for non supported warning flags +if test "$CC" = "icc" +then + AM_CFLAGS="$AM_CFLAGS -wd10006" +fi + + +LIB_SOCKET_NSL +AX_HARDEN_CC_COMPILER_FLAGS + +# link to ws2_32 if on mingw +case $host_os in + *mingw32) + LDFLAGS="$LDFLAGS -lws2_32" ;; +esac + +# add user C_EXTRA_FLAGS back +CFLAGS="$CFLAGS $USER_C_EXTRA_FLAGS" +OPTION_FLAGS="$USER_C_EXTRA_FLAGS $AM_CFLAGS" + +CREATE_HEX_VERSION +AC_SUBST([AM_CPPFLAGS]) +AC_SUBST([AM_CFLAGS]) +AC_SUBST([AM_LDFLAGS]) + +# FINAL +AC_CONFIG_FILES([stamp-h], [echo timestamp > stamp-h]) +AC_CONFIG_FILES([Makefile]) +AC_CONFIG_FILES([wolfssl/version.h]) +AC_CONFIG_FILES([wolfssl/options.h]) +#have options.h and version.h for autoconf fips tag and build +#if test "x$ENABLED_FIPS" = "xyes" +#then +# AC_CONFIG_FILES([cyassl/version.h]) +# AC_CONFIG_FILES([cyassl/options.h]) +#fi +AC_CONFIG_FILES([support/wolfssl.pc]) +AC_CONFIG_FILES([rpm/spec]) + +AX_CREATE_GENERIC_CONFIG +AX_AM_JOBSERVER([yes]) + +AC_OUTPUT + + +# force make clean +echo "---" +echo "Running make clean..." +make clean >/dev/null 2>&1 +# Touch files that may not be in repository +echo "Touching File..." +touch ctaocrypt/src/fips.c +touch ctaocrypt/src/fips_test.c +echo + +# generate user options header +echo "---" +echo "Generating user options header..." + +OPTION_FILE="wolfssl/options.h" +#if +#OPTION_FILE+="cyassl/options.h" +#fi +rm -f $OPTION_FILE + +echo "/* wolfssl options.h" > $OPTION_FILE +echo " * generated from configure options" >> $OPTION_FILE +echo " *" >> $OPTION_FILE +echo " * Copyright (C) 2006-2015 wolfSSL Inc." >> $OPTION_FILE +echo " *" >> $OPTION_FILE +echo " * This file is part of wolfSSL. (formerly known as CyaSSL)" >> $OPTION_FILE +echo " *" >> $OPTION_FILE +echo " */" >> $OPTION_FILE + +echo "" >> $OPTION_FILE +echo "#pragma once" >> $OPTION_FILE +echo "" >> $OPTION_FILE +echo "#ifdef __cplusplus" >> $OPTION_FILE +echo "extern \"C\" {" >> $OPTION_FILE +echo "#endif" >> $OPTION_FILE +echo "" >> $OPTION_FILE + +for option in $OPTION_FLAGS; do + defonly=`echo $option | sed 's/-D//'` + if test "$defonly" != "$option" + then + noequalsign=`echo $defonly | sed 's/=/ /'` + if test "$noequalsign" = "NDEBUG" || test "$noequalsign" = "DEBUG" + then + echo "not outputing (N)DEBUG to $OPTION_FILE" + continue + fi + + # allow user to igonore system options + ignoresys=no + if [[[ $noequalsign == _* ]]] ; + then + ignoresys=yes + echo "#ifndef WOLFSSL_OPTIONS_IGNORE_SYS" >> $OPTION_FILE + fi + + noarg=`echo $defonly | sed 's/=.*//'` + echo "#undef $noarg" >> $OPTION_FILE + echo "#define $noequalsign" >> $OPTION_FILE + + if test "$ignoresys" = "yes" + then + echo "#endif" >> $OPTION_FILE + fi + + echo "" >> $OPTION_FILE + else + echo "option w/o begin -D is $option, not saving to $OPTION_FILE" + fi +done + +echo "" >> $OPTION_FILE +echo "#ifdef __cplusplus" >> $OPTION_FILE +echo "}" >> $OPTION_FILE +echo "#endif" >> $OPTION_FILE +echo "" >> $OPTION_FILE +echo + +#backwards compatability for those who have included options or version +touch cyassl/options.h +echo "/* cyassl options.h" > cyassl/options.h +echo " * generated from wolfssl/options.h" >> cyassl/options.h +echo " */" >> cyassl/options.h +echo "" +while read -r line +do + echo "$line" >> cyassl/options.h +done < $OPTION_FILE + +# output config summary +echo "---" +echo "Configuration summary for $PACKAGE_NAME version $VERSION" +echo "" +echo " * Installation prefix: $prefix" +echo " * System type: $host_vendor-$host_os" +echo " * Host CPU: $host_cpu" +echo " * C Compiler: $CC" +echo " * C Flags: $CFLAGS" +echo " * C++ Compiler: $CXX" +echo " * C++ Flags: $CXXFLAGS" +echo " * CPP Flags: $CPPFLAGS" +echo " * LIB Flags: $LIB" +echo " * Debug enabled: $ax_enable_debug" +echo " * Warnings as failure: $ac_cv_warnings_as_errors" +echo " * make -j: $enable_jobserver" +echo " * VCS checkout: $ac_cv_vcs_checkout" +echo +echo " Features " +echo " * Single threaded: $ENABLED_SINGLETHREADED" +echo " * Filesystem: $ENABLED_FILESYSTEM" +echo " * OpenSSL Extra API: $ENABLED_OPENSSLEXTRA" +echo " * Max Strength Build: $ENABLED_MAXSTRENGTH" +echo " * fastmath: $ENABLED_FASTMATH" +echo " * sniffer: $ENABLED_SNIFFER" +echo " * snifftest: $ENABLED_SNIFFTEST" +echo " * ARC4: $ENABLED_ARC4" +echo " * AES: $ENABLED_AES" +echo " * AES-NI: $ENABLED_AESNI" +echo " * AES-GCM: $ENABLED_AESGCM" +echo " * AES-CCM: $ENABLED_AESCCM" +echo " * DES3: $ENABLED_DES3" +echo " * Camellia: $ENABLED_CAMELLIA" +echo " * NULL Cipher: $ENABLED_NULL_CIPHER" +echo " * MD5: $ENABLED_MD5" +echo " * RIPEMD: $ENABLED_RIPEMD" +echo " * SHA: $ENABLED_SHA" +echo " * SHA-512: $ENABLED_SHA512" +echo " * BLAKE2: $ENABLED_BLAKE2" +echo " * keygen: $ENABLED_KEYGEN" +echo " * certgen: $ENABLED_CERTGEN" +echo " * certreq: $ENABLED_CERTREQ" +echo " * HC-128: $ENABLED_HC128" +echo " * RABBIT: $ENABLED_RABBIT" +echo " * CHACHA: $ENABLED_CHACHA" +echo " * Hash DRBG: $ENABLED_HASHDRBG" +echo " * PWDBASED: $ENABLED_PWDBASED" +echo " * HKDF: $ENABLED_HKDF" +echo " * MD4: $ENABLED_MD4" +echo " * PSK: $ENABLED_PSK" +echo " * Poly1305: $ENABLED_POLY1305" +echo " * LEANPSK: $ENABLED_LEANPSK" +echo " * RSA: $ENABLED_RSA" +echo " * DSA: $ENABLED_DSA" +echo " * DH: $ENABLED_DH" +echo " * ECC: $ENABLED_ECC" +echo " * CURVE25519: $ENABLED_CURVE25519" +echo " * ED25519: $ENABLED_ED25519" +echo " * FPECC: $ENABLED_FPECC" +echo " * ECC_ENCRYPT: $ENABLED_ECC_ENCRYPT" +echo " * ASN: $ENABLED_ASN" +echo " * Anonymous cipher: $ENABLED_ANON" +echo " * CODING: $ENABLED_CODING" +echo " * MEMORY: $ENABLED_MEMORY" +echo " * I/O POOL: $ENABLED_IOPOOL" +echo " * ERROR_STRINGS: $ENABLED_ERROR_STRINGS" +echo " * DTLS: $ENABLED_DTLS" +echo " * Old TLS Versions: $ENABLED_OLD_TLS" +echo " * OCSP: $ENABLED_OCSP" +echo " * CRL: $ENABLED_CRL" +echo " * CRL-MONITOR: $ENABLED_CRL_MONITOR" +echo " * Persistent session cache: $ENABLED_SAVESESSION" +echo " * Persistent cert cache: $ENABLED_SAVECERT" +echo " * Atomic User Record Layer: $ENABLED_ATOMICUSER" +echo " * Public Key Callbacks: $ENABLED_PKCALLBACKS" +echo " * NTRU: $ENABLED_NTRU" +echo " * SNI: $ENABLED_SNI" +echo " * Maximum Fragment Length: $ENABLED_MAX_FRAGMENT" +echo " * Truncated HMAC: $ENABLED_TRUNCATED_HMAC" +echo " * Renegotiation Indication: $ENABLED_RENEGOTIATION_INDICATION" +echo " * Secure Renegotiation: $ENABLED_SECURE_RENEGOTIATION" +echo " * Supported Elliptic Curves: $ENABLED_SUPPORTED_CURVES" +echo " * Session Ticket: $ENABLED_SESSION_TICKET" +echo " * All TLS Extensions: $ENABLED_TLSX" +echo " * PKCS#7 $ENABLED_PKCS7" +echo " * wolfSCEP $ENABLED_WOLFSCEP" +echo " * Small Stack: $ENABLED_SMALL_STACK" +echo " * valgrind unit tests: $ENABLED_VALGRIND" +echo " * LIBZ: $ENABLED_LIBZ" +echo " * Examples: $ENABLED_EXAMPLES" +echo "" +echo "---" + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/aes.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/aes.c new file mode 100644 index 0000000..e9f5886 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/aes.c @@ -0,0 +1 @@ +/* dummy file for autoconf */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/des3.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/des3.c new file mode 100644 index 0000000..e9f5886 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/des3.c @@ -0,0 +1 @@ +/* dummy file for autoconf */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/fips.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/fips.c new file mode 100644 index 0000000..e69de29 diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/fips_test.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/fips_test.c new file mode 100644 index 0000000..e69de29 diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/hmac.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/hmac.c new file mode 100644 index 0000000..e9f5886 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/hmac.c @@ -0,0 +1 @@ +/* dummy file for autoconf */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/misc.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/misc.c new file mode 100644 index 0000000..dc4198b --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/misc.c @@ -0,0 +1,27 @@ +/* misc.c + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#ifdef NO_INLINE + #include +#else + /* for inline includes */ + #include +#endif diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/random.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/random.c new file mode 100644 index 0000000..e9f5886 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/random.c @@ -0,0 +1 @@ +/* dummy file for autoconf */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/rsa.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/rsa.c new file mode 100644 index 0000000..e9f5886 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/rsa.c @@ -0,0 +1 @@ +/* dummy file for autoconf */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/sha.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/sha.c new file mode 100644 index 0000000..e9f5886 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/sha.c @@ -0,0 +1 @@ +/* dummy file for autoconf */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/sha256.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/sha256.c new file mode 100644 index 0000000..e9f5886 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/sha256.c @@ -0,0 +1 @@ +/* dummy file for autoconf */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/sha512.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/sha512.c new file mode 100644 index 0000000..e9f5886 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/sha512.c @@ -0,0 +1 @@ +/* dummy file for autoconf */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/wolfcrypt_first.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/wolfcrypt_first.c new file mode 100644 index 0000000..c694aa0 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/wolfcrypt_first.c @@ -0,0 +1,47 @@ +/* wolfcrypt_first.c + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +/* This file needs to be linked first in order to work correctly */ + +#ifdef HAVE_CONFIG_H + #include +#endif + +/* in case user set HAVE_FIPS there */ +#include + +#ifdef HAVE_FIPS + +/* read only start address */ +const unsigned int wolfCrypt_FIPS_ro_start[] = +{ 0x1a2b3c4d, 0x00000001 }; + + +/* first function of text/code segment */ +int wolfCrypt_FIPS_first(void); +int wolfCrypt_FIPS_first(void) +{ + return 0; +} + + +#endif /* HAVE_FIPS */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/wolfcrypt_last.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/wolfcrypt_last.c new file mode 100644 index 0000000..cdcd741 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/ctaocrypt/src/wolfcrypt_last.c @@ -0,0 +1,47 @@ +/* wolfcrypt_last.c + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +/* This file needs to be linked last in order to work correctly */ + +#ifdef HAVE_CONFIG_H + #include +#endif + +/* in case user set HAVE_FIPS there */ +#include + +#ifdef HAVE_FIPS + +/* last function of text/code segment */ +int wolfCrypt_FIPS_last(void); +int wolfCrypt_FIPS_last(void) +{ + return 0; +} + + +/* read only end address */ +const unsigned int wolfCrypt_FIPS_ro_end[] = +{ 0x1a2b3c4d, 0xffffffff }; + + +#endif /* HAVE_FIPS */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/callbacks.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/callbacks.h new file mode 100644 index 0000000..f74f7a6 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/callbacks.h @@ -0,0 +1,22 @@ +/* callbacks.h + * + * Copyright (C) 2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/certs_test.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/certs_test.h new file mode 100644 index 0000000..c8465ac --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/certs_test.h @@ -0,0 +1,10 @@ +/* certs_test.h */ + +#include + +#ifndef CYASSL_CERTS_TEST_H + #define CYASSL_CERTS_TEST_H WOLFSSL_CERTS_TEST_H +#else + #undef CYASSL_CERTS_TEST_H + #define CYASSL_CERTS_TEST_H WOLFSSL_CERTS_TEST_H +#endif diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/crl.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/crl.h new file mode 100644 index 0000000..87e402f --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/crl.h @@ -0,0 +1,22 @@ +/* crl.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/aes.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/aes.h new file mode 100644 index 0000000..2bb2135 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/aes.h @@ -0,0 +1,65 @@ +/* aes.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifndef NO_AES + +#ifndef CTAO_CRYPT_AES_H +#define CTAO_CRYPT_AES_H + +#include +#define AesSetKey wc_AesSetKey +#define AesSetIV wc_AesSetIV +#define AesCbcEncrypt wc_AesCbcEncrypt +#define AesCbcDecrypt wc_AesCbcDecrypt +#define AesCbcDecryptWithKey wc_AesCbcDecryptWithKey + +/* AES-CTR */ +#ifdef WOLFSSL_AES_COUNTER + #define AesCtrEncrypt wc_AesCtrEncrypt +#endif +/* AES-DIRECT */ +#if defined(WOLFSSL_AES_DIRECT) + #define AesEncryptDirect wc_AesEncryptDirect + #define AesDecryptDirect wc_AesDecryptDirect + #define AesSetKeyDirect wc_AesSetKeyDirect +#endif +#ifdef HAVE_AESGCM + #define AesGcmSetKey wc_AesGcmSetKey + #define AesGcmEncrypt wc_AesGcmEncrypt + #define AesGcmDecrypt wc_AesGcmDecrypt + #define GmacSetKey wc_GmacSetKey + #define GmacUpdate wc_GmacUpdate +#endif /* HAVE_AESGCM */ +#ifdef HAVE_AESCCM + #define AesCcmSetKey wc_AesCcmSetKey + #define AesCcmEncrypt wc_AesCcmEncrypt + #define AesCcmDecrypt wc_AesCcmDecrypt +#endif /* HAVE_AESCCM */ + +#ifdef HAVE_CAVIUM + #define AesInitCavium wc_AesInitCavium + #define AesFreeCavium wc_AesFreeCavium +#endif + +#endif /* CTAO_CRYPT_AES_H */ +#endif /* NO_AES */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/arc4.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/arc4.h new file mode 100644 index 0000000..965b079 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/arc4.h @@ -0,0 +1,36 @@ +/* arc4.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#ifndef CTAO_CRYPT_ARC4_H +#define CTAO_CRYPT_ARC4_H + +/* for arc4 reverse compatibility */ +#ifndef NO_RC4 +#include + #define CYASSL_ARC4_CAVIUM_MAGIC WOLFSSL_ARC4_CAVIUM_MAGIC + #define Arc4Process wc_Arc4Process + #define Arc4SetKey wc_Arc4SetKey + #define Arc4InitCavium wc_Arc4InitCavium + #define Arc4FreeCavium wc_Arc4FreeCavium +#endif + +#endif /* CTAO_CRYPT_ARC4_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/asn.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/asn.h new file mode 100644 index 0000000..c27c144 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/asn.h @@ -0,0 +1,49 @@ +/* asn.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#ifndef NO_ASN + +#ifndef CTAO_CRYPT_ASN_H +#define CTAO_CRYPT_ASN_H + +/* pull in compatibility for each include */ +#include +#include +#include +#include +#include /* public interface */ +#ifdef HAVE_ECC + #include +#endif + + +#include + +#ifndef WOLFSSL_PEMCERT_TODER_DEFINED +#ifndef NO_FILESYSTEM + #define CyaSSL_PemCertToDer wolfSSL_PemCertToDer +#endif +#endif + +#endif /* CTAO_CRYPT_ASN_H */ + +#endif /* !NO_ASN */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/asn_public.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/asn_public.h new file mode 100644 index 0000000..040734e --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/asn_public.h @@ -0,0 +1,78 @@ +/* asn_public.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifndef CTAO_CRYPT_ASN_PUBLIC_H +#define CTAO_CRYPT_ASN_PUBLIC_H + +/* pull in compatibility for each of the includes */ +#include +#include +#include +#ifdef WOLFSSL_CERT_GEN + #include +#endif + +#include +#ifdef WOLFSSL_CERT_GEN + #define InitCert wc_InitCert + #define MakeCert wc_MakeCert + + #ifdef WOLFSSL_CERT_REQ + #define MakeCertReq wc_MakeCertReq +#endif + + #define SignCert wc_SignCert + #define MakeSelfCert wc_MakeSelfCert + #define SetIssuer wc_SetIssuer + #define SetSubject wc_SetSubject + + #ifdef WOLFSSL_ALT_NAMES + #define SetAltNames wc_SetAltNames +#endif + + #define SetIssuerBuffer wc_SetIssuerBuffer + #define SetSubjectBuffer wc_SetSubjectBuffer + #define SetAltNamesBuffer wc_SetAltNamesBuffer + #define SetDatesBuffer wc_SetDatesBuffer + + #ifdef HAVE_NTRU + #define MakeNtruCert wc_MakeNtruCert + #endif + +#endif /* WOLFSSL_CERT_GEN */ + + #if defined(WOLFSSL_KEY_GEN) || defined(WOLFSSL_CERT_GEN) + #define DerToPem wc_DerToPem +#endif + +#ifdef HAVE_ECC + /* private key helpers */ + #define EccPrivateKeyDecode wc_EccPrivateKeyDecode + #define EccKeyToDer wc_EccKeyToDer +#endif + + /* DER encode signature */ + #define EncodeSignature wc_EncodeSignature + #define GetCTC_HashOID wc_GetCTC_HashOID + +#endif /* CTAO_CRYPT_ASN_PUBLIC_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/blake2-impl.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/blake2-impl.h new file mode 100644 index 0000000..fc5ec3a --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/blake2-impl.h @@ -0,0 +1,42 @@ +/* + BLAKE2 reference source code package - reference C implementations + + Written in 2012 by Samuel Neves + + To the extent possible under law, the author(s) have dedicated all copyright + and related and neighboring rights to this software to the public domain + worldwide. This software is distributed without any warranty. + + You should have received a copy of the CC0 Public Domain Dedication along with + this software. If not, see . +*/ +/* blake2-impl.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifndef CTAOCRYPT_BLAKE2_IMPL_H +#define CTAOCRYPT_BLAKE2_IMPL_H + +#include +#include + +#endif /* CTAOCRYPT_BLAKE2_IMPL_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/blake2-int.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/blake2-int.h new file mode 100644 index 0000000..07ea8e7 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/blake2-int.h @@ -0,0 +1,43 @@ +/* + BLAKE2 reference source code package - reference C implementations + + Written in 2012 by Samuel Neves + + To the extent possible under law, the author(s) have dedicated all copyright + and related and neighboring rights to this software to the public domain + worldwide. This software is distributed without any warranty. + + You should have received a copy of the CC0 Public Domain Dedication along with + this software. If not, see . +*/ +/* blake2-int.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + + +#ifndef CTAOCRYPT_BLAKE2_INT_H +#define CTAOCRYPT_BLAKE2_INT_H + +#include +#include + +#endif /* CTAOCRYPT_BLAKE2_INT_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/blake2.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/blake2.h new file mode 100644 index 0000000..b774917 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/blake2.h @@ -0,0 +1,44 @@ +/* blake2.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifdef HAVE_BLAKE2 + +#ifndef CTAOCRYPT_BLAKE2_H +#define CTAOCRYPT_BLAKE2_H + +#include + +/* for blake2 reverse compatibility */ +#ifndef HAVE_FIPS + #define InitBlake2b wc_InitBlake2b + #define Blake2bUpdate wc_Blake2bUpdate + #define Blake2bFinal wc_Blake2bFinal +#else + /* name for when fips hmac calls blake */ + #define wc_InitBlake2b InitBlake2b + #define wc_Blake2bUpdate Blake2bUpdate + #define wc_Blake2bFinal Blake2bFinal +#endif /* HAVE_FIPS */ + +#endif /* CTAOCRYPT_BLAKE2_H */ +#endif /* HAVE_BLAKE2 */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/camellia.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/camellia.h new file mode 100644 index 0000000..bbe7dcf --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/camellia.h @@ -0,0 +1,38 @@ +/* camellia.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#ifndef CTAO_CRYPT_CAMELLIA_H +#define CTAO_CRYPT_CAMELLIA_H + + +/* for camellia reverse compatibility */ +#ifdef HAVE_CAMELLIA + #include + #define CamelliaSetKey wc_CamelliaSetKey + #define CamelliaSetIV wc_CamelliaSetIV + #define CamelliaEncryptDirect wc_CamelliaEncryptDirect + #define CamelliaDecryptDirect wc_CamelliaDecryptDirect + #define CamelliaCbcEncrypt wc_CamelliaCbcEncrypt + #define CamelliaCbcDecrypt wc_CamelliaCbcDecrypt +#endif + +#endif /* CTAO_CRYPT_CAMELLIA_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/chacha.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/chacha.h new file mode 100644 index 0000000..7651d28 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/chacha.h @@ -0,0 +1,35 @@ +/* chacha.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#ifndef CTAO_CRYPT_CHACHA_H +#define CTAO_CRYPT_CHACHA_H + + +/* for chacha reverse compatibility */ +#ifdef HAVE_CHACHA + #include + #define Chacha_Process wc_Chacha_Process + #define Chacha_SetKey wc_Chacha_SetKey + #define Chacha_SetIV wc_Chacha_SetIV +#endif + +#endif /* CTAO_CRYPT_CHACHA_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/coding.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/coding.h new file mode 100644 index 0000000..47f5d25 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/coding.h @@ -0,0 +1,29 @@ +/* coding.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifndef CTAO_CRYPT_CODING_H +#define CTAO_CRYPT_CODING_H + +#include + +#endif /* CTAO_CRYPT_CODING_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/compress.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/compress.h new file mode 100644 index 0000000..632af2e --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/compress.h @@ -0,0 +1,37 @@ +/* compress.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifdef HAVE_LIBZ + +#ifndef CTAO_CRYPT_COMPRESS_H +#define CTAO_CRYPT_COMPRESS_H + +#include + +/* reverse compatibility */ +#define Compress wc_Compress +#define DeCompress wc_DeCompress + +#endif /* CTAO_CRYPT_COMPRESS_H */ + +#endif /* HAVE_LIBZ */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/des3.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/des3.h new file mode 100644 index 0000000..c6fbaa8 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/des3.h @@ -0,0 +1,48 @@ +/* des3.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifndef NO_DES3 + +#ifndef CTAO_CRYPT_DES3_H +#define CTAO_CRYPT_DES3_H + + +#include +#define Des_SetKey wc_Des_SetKey +#define Des_SetIV wc_Des_SetIV +#define Des_CbcEncrypt wc_Des_CbcEncrypt +#define Des_CbcDecrypt wc_Des_CbcDecrypt +#define Des_EcbEncrypt wc_Des_EcbEncrypt +#define Des_CbcDecryptWithKey wc_Des_CbcDecryptWithKey +#define Des3_SetKey wc_Des3_SetKey +#define Des3_SetIV wc_Des3_SetIV +#define Des3_CbcEncrypt wc_Des3_CbcEncrypt +#define Des3_CbcDecrypt wc_Des3_CbcDecrypt +#define Des3_CbcDecryptWithKey wc_Des3_CbcDecryptWithKey +#ifdef HAVE_CAVIUM + #define Des3_InitCavium wc_Des3_InitCavium + #define Des3_FreeCavium wc_Des3_FreeCavium +#endif + +#endif /* NO_DES3 */ +#endif /* CTAO_CRYPT_DES3_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/dh.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/dh.h new file mode 100644 index 0000000..4bd7757 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/dh.h @@ -0,0 +1,41 @@ +/* dh.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifndef NO_DH + +#ifndef CTAO_CRYPT_DH_H +#define CTAO_CRYPT_DH_H + +/* for dh reverse compatibility */ +#include +#define InitDhKey wc_InitDhKey +#define FreeDhKey wc_FreeDhKey +#define DhGenerateKeyPair wc_DhGenerateKeyPair +#define DhAgree wc_DhAgree +#define DhKeyDecode wc_DhKeyDecode +#define DhSetKey wc_DhSetKey +#define DhParamsLoad wc_DhParamsLoad + +#endif /* CTAO_CRYPT_DH_H */ + +#endif /* NO_DH */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/dsa.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/dsa.h new file mode 100644 index 0000000..bdc8cd5 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/dsa.h @@ -0,0 +1,32 @@ +/* dsa.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifndef NO_DSA + +#ifndef CTAO_CRYPT_DSA_H +#define CTAO_CRYPT_DSA_H + +#include + +#endif /* CTAO_CRYPT_DSA_H */ +#endif /* NO_DSA */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/ecc.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/ecc.h new file mode 100644 index 0000000..3ae13f7 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/ecc.h @@ -0,0 +1,68 @@ +/* ecc.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#ifdef HAVE_ECC + +#ifndef CTAO_CRYPT_ECC_H +#define CTAO_CRYPT_ECC_H + +#include + +/* includes for compatibility */ +#include +#include +#include + +/* for ecc reverse compatibility */ +#ifdef HAVE_ECC + #define ecc_make_key wc_ecc_make_key + #define ecc_shared_secret wc_ecc_shared_secret + #define ecc_sign_hash wc_ecc_sign_hash + #define ecc_verify_hash wc_ecc_verify_hash + #define ecc_init wc_ecc_init + #define ecc_free wc_ecc_free + #define ecc_fp_free wc_ecc_fp_free + #define ecc_export_x963 wc_ecc_export_x963 + #define ecc_size wc_ecc_size + #define ecc_sig_size wc_ecc_sig_size + #define ecc_export_x963_ex wc_ecc_export_x963_ex + #define ecc_import_x963 wc_ecc_import_x963 + #define ecc_import_private_key wc_ecc_import_private_key + #define ecc_rs_to_sig wc_ecc_rs_to_sig + #define ecc_import_raw wc_ecc_import_raw + #define ecc_export_private_only wc_ecc_export_private_only + +#ifdef HAVE_ECC_ENCRYPT + /* ecc encrypt */ + #define ecc_ctx_new wc_ecc_ctx_new + #define ecc_ctx_free wc_ecc_ctx_free + #define ecc_ctx_reset wc_ecc_ctx_reset + #define ecc_ctx_get_own_salt wc_ecc_ctx_get_own_salt + #define ecc_ctx_set_peer_salt wc_ecc_ctx_set_peer_salt + #define ecc_ctx_set_info wc_ecc_ctx_set_info + #define ecc_encrypt wc_ecc_encrypt + #define ecc_decrypt wc_ecc_decrypt +#endif /* HAVE_ECC_ENCRYPT */ +#endif + +#endif /* CTAO_CRYPT_ECC_H */ +#endif /* HAVE_ECC */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/error-crypt.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/error-crypt.h new file mode 100644 index 0000000..f201455 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/error-crypt.h @@ -0,0 +1,32 @@ +/* error-crypt.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifndef CTAO_CRYPT_ERROR_H +#define CTAO_CRYPT_ERROR_H + +/* for name change and fips compatibility @wc_fips */ +#include +#define CTaoCryptErrorString wc_ErrorString +#define CTaoCryptGetErrorString wc_GetErrorString + +#endif /* CTAO_CRYPT_ERROR_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/fips_test.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/fips_test.h new file mode 100644 index 0000000..12e1ce0 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/fips_test.h @@ -0,0 +1,58 @@ +/* fips_test.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifndef CTAO_CRYPT_FIPS_TEST_H +#define CTAO_CRYPT_FIPS_TEST_H + +#include + + +#ifdef __cplusplus + extern "C" { +#endif + +/* Known Answer Test string inputs are hex, internal */ +CYASSL_LOCAL int DoKnownAnswerTests(char*, int); + + +/* FIPS failure callback */ +typedef void(*wolfCrypt_fips_cb)(int ok, int err, const char* hash); + +/* Public set function */ +CYASSL_API int wolfCrypt_SetCb_fips(wolfCrypt_fips_cb cbf); + +/* Public get status functions */ +CYASSL_API int wolfCrypt_GetStatus_fips(void); +CYASSL_API const char* wolfCrypt_GetCoreHash_fips(void); + +#ifdef HAVE_FORCE_FIPS_FAILURE + /* Public function to force failure mode for operational testing */ + CYASSL_API int wolfCrypt_SetStatus_fips(int); +#endif + + +#ifdef __cplusplus + } /* extern "C" */ +#endif + +#endif /* CTAO_CRYPT_FIPS_TEST_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/hc128.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/hc128.h new file mode 100644 index 0000000..b2c9bc9 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/hc128.h @@ -0,0 +1,39 @@ +/* hc128.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifndef NO_HC128 + +#ifndef CTAO_CRYPT_HC128_H +#define CTAO_CRYPT_HC128_H + +#include + +/* for hc128 reverse compatibility */ +#ifdef HAVE_HC128 + #define Hc128_Process wc_Hc128_Process + #define Hc128_SetKey wc_Hc128_SetKey +#endif + +#endif /* CTAO_CRYPT_HC128_H */ + +#endif /* HAVE_HC128 */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/hmac.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/hmac.h new file mode 100644 index 0000000..4625f10 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/hmac.h @@ -0,0 +1,44 @@ +/* hmac.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifndef NO_HMAC + +#ifndef CTAO_CRYPT_HMAC_H +#define CTAO_CRYPT_HMAC_H + +#include +#define HmacSetKey wc_HmacSetKey +#define HmacUpdate wc_HmacUpdate +#define HmacFinal wc_HmacFinal +#ifdef HAVE_CAVIUM + #define HmacInitCavium wc_HmacInitCavium + #define HmacFreeCavium wc_HmacFreeCavium +#endif +#define CyaSSL_GetHmacMaxSize wolfSSL_GetHmacMaxSize +#ifdef HAVE_HKDF + #define HKDF wc_HKDF +#endif /* HAVE_HKDF */ + +#endif /* CTAO_CRYPT_HMAC_H */ + +#endif /* NO_HMAC */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/include.am new file mode 100644 index 0000000..c30b26f --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/include.am @@ -0,0 +1,54 @@ +# vim:ft=automake +# All paths should be given relative to the root + +EXTRA_DIST+= ctaocrypt/src/misc.c + +nobase_include_HEADERS+= \ + cyassl/ctaocrypt/aes.h \ + cyassl/ctaocrypt/arc4.h \ + cyassl/ctaocrypt/asn.h \ + cyassl/ctaocrypt/asn_public.h \ + cyassl/ctaocrypt/poly1305.h \ + cyassl/ctaocrypt/camellia.h \ + cyassl/ctaocrypt/coding.h \ + cyassl/ctaocrypt/compress.h \ + cyassl/ctaocrypt/des3.h \ + cyassl/ctaocrypt/dh.h \ + cyassl/ctaocrypt/dsa.h \ + cyassl/ctaocrypt/ecc.h \ + cyassl/ctaocrypt/error-crypt.h \ + cyassl/ctaocrypt/fips_test.h \ + cyassl/ctaocrypt/hc128.h \ + cyassl/ctaocrypt/hmac.h \ + cyassl/ctaocrypt/integer.h \ + cyassl/ctaocrypt/md2.h \ + cyassl/ctaocrypt/md4.h \ + cyassl/ctaocrypt/md5.h \ + cyassl/ctaocrypt/misc.h \ + cyassl/ctaocrypt/pkcs7.h \ + cyassl/ctaocrypt/wc_port.h \ + cyassl/ctaocrypt/pwdbased.h \ + cyassl/ctaocrypt/rabbit.h \ + cyassl/ctaocrypt/chacha.h \ + cyassl/ctaocrypt/random.h \ + cyassl/ctaocrypt/ripemd.h \ + cyassl/ctaocrypt/rsa.h \ + cyassl/ctaocrypt/settings.h \ + cyassl/ctaocrypt/settings_comp.h \ + cyassl/ctaocrypt/sha256.h \ + cyassl/ctaocrypt/sha512.h \ + cyassl/ctaocrypt/sha.h \ + cyassl/ctaocrypt/blake2.h \ + cyassl/ctaocrypt/blake2-int.h \ + cyassl/ctaocrypt/blake2-impl.h \ + cyassl/ctaocrypt/tfm.h \ + cyassl/ctaocrypt/types.h \ + cyassl/ctaocrypt/visibility.h \ + cyassl/ctaocrypt/logging.h \ + cyassl/ctaocrypt/memory.h \ + cyassl/ctaocrypt/mpi_class.h \ + cyassl/ctaocrypt/mpi_superclass.h + +noinst_HEADERS+= \ + cyassl/ctaocrypt/port/pic32/pic32mz-crypt.h + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/integer.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/integer.h new file mode 100644 index 0000000..97b2282 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/integer.h @@ -0,0 +1,34 @@ +/* integer.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +/* + * Based on public domain LibTomMath 0.38 by Tom St Denis, tomstdenis@iahu.ca, + * http://math.libtomcrypt.com + */ + + +#ifndef CTAO_CRYPT_INTEGER_H +#define CTAO_CRYPT_INTEGER_H + +#include + +#endif /* CTAO_CRYPT_INTEGER_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/logging.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/logging.h new file mode 100644 index 0000000..faa85d4 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/logging.h @@ -0,0 +1,40 @@ +/* logging.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +/* submitted by eof */ + + +#ifndef CYASSL_LOGGING_H +#define CYASSL_LOGGING_H + +/* for fips compatibility @wc_fips */ +#include +#define CYASSL_LEAVE WOLFSSL_LEAVE +#define CYASSL_ERROR WOLFSSL_ERROR +#define CYASSL_ENTER WOLFSSL_ENTER +#define CYASSL_MSG WOLFSSL_MSG +/* check old macros possibly declared */ +#if defined(DEBUG_CYASSL) && !defined(DEBUG_WOLFSSL) + #define DEBUG_WOLFSSL +#endif + +#endif /* CYASSL_LOGGING_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/md2.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/md2.h new file mode 100644 index 0000000..cb76337 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/md2.h @@ -0,0 +1,42 @@ +/* md2.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +/* check for old macro */ +#if !defined(CYASSL_MD2) && defined(WOLFSSL_MD2) + #define CYASSL_MD2 +#endif + +#ifdef CYASSL_MD2 + +#ifndef CTAO_CRYPT_MD2_H +#define CTAO_CRYPT_MD2_H + +#include + +#define InitMd2 wc_InitMd2 +#define Md2Update wc_Md2Update +#define Md2Final wc_Md2Final +#define Md2Hash wc_Md2Hash + +#endif /* CTAO_CRYPT_MD2_H */ +#endif /* CYASSL_MD2 */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/md4.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/md4.h new file mode 100644 index 0000000..4584656 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/md4.h @@ -0,0 +1,37 @@ +/* md4.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifndef NO_MD4 + +#ifndef CTAO_CRYPT_MD4_H +#define CTAO_CRYPT_MD4_H + +#include + +#define InitMd4 wc_InitMd4 +#define Md4Update wc_Md4Update +#define Md4Final wc_Md4Final + +#endif /* CTAO_CRYPT_MD4_H */ + +#endif /* NO_MD4 */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/md5.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/md5.h new file mode 100644 index 0000000..3f5d017 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/md5.h @@ -0,0 +1,44 @@ +/* md5.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#ifndef NO_MD5 + +#ifndef CTAO_CRYPT_MD5_H +#define CTAO_CRYPT_MD5_H + +#include + +#ifndef HAVE_FIPS + #define InitMd5 wc_InitMd5 + #define Md5Update wc_Md5Update + #define Md5Final wc_Md5Final + #define Md5Hash wc_Md5Hash +#else + /* redfined name so that hmac is calling same function names with fips */ + #define wc_InitMd5 InitMd5 + #define wc_Md5Update Md5Update + #define wc_Md5Final Md5Final + #define wc_Md5Hash Md5Hash +#endif + +#endif /* CTAO_CRYPT_MD5_H */ +#endif /* NO_MD5 */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/memory.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/memory.h new file mode 100644 index 0000000..2850053 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/memory.h @@ -0,0 +1,41 @@ +/* memory.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +/* submitted by eof */ + + +#ifndef CYASSL_MEMORY_H +#define CYASSL_MEMORY_H + + +#include +#define CyaSSL_Malloc_cb wolfSSL_Malloc_cb +#define CyaSSL_Free_cb wolfSSL_Free_cb +#define CyaSSL_Realloc_cb wolfSSL_Realloc_cb +#define CyaSSL_SetAllocators wolfSSL_SetAllocators + +/* Public in case user app wants to use XMALLOC/XFREE */ +#define CyaSSL_Malloc wolfSSL_Malloc +#define CyaSSL_Free wolfSSL_Free +#define CyaSSL_Realloc wolfSSL_Realloc + +#endif /* CYASSL_MEMORY_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/misc.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/misc.h new file mode 100644 index 0000000..a640044 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/misc.h @@ -0,0 +1,29 @@ +/* misc.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifndef CTAO_CRYPT_MISC_H +#define CTAO_CRYPT_MISC_H + +#include + +#endif /* CTAO_CRYPT_MISC_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/mpi_class.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/mpi_class.h new file mode 100644 index 0000000..0ce92a6 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/mpi_class.h @@ -0,0 +1,23 @@ +/* mpi_class.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#include + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/mpi_superclass.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/mpi_superclass.h new file mode 100644 index 0000000..68cd0a6 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/mpi_superclass.h @@ -0,0 +1,26 @@ +/* mpi_superclass.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +/* super class file for PK algos */ + +#include + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/pkcs7.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/pkcs7.h new file mode 100644 index 0000000..dfb7c2f --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/pkcs7.h @@ -0,0 +1,52 @@ +/* pkcs7.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifdef HAVE_PKCS7 + +#ifndef CTAO_CRYPT_PKCS7_H +#define CTAO_CRYPT_PKCS7_H + +/* pull in compatibility for old includes */ +#include +#include +#include +#include +#include + +#include + +/* for pkcs7 reverse compatibility */ +#define SetContentType wc_SetContentType +#define GetContentType wc_GetContentType +#define CreateRecipientInfo wc_CreateRecipientInfo +#define PKCS7_InitWithCert wc_PKCS7_InitWithCert +#define PKCS7_Free wc_PKCS7_Free +#define PKCS7_EncodeData wc_PKCS7_EncodeData +#define PKCS7_EncodeSignedData wc_PKCS7_EncodeSignedData +#define PKCS7_VerifySignedData wc_PKCS7_VerifySignedData +#define PKCS7_EncodeEnvelopedData wc_PKCS7_EncodeEnvelopedData +#define PKCS7_DecodeEnvelopedData wc_PKCS7_DecodeEnvelopedData + +#endif /* CTAO_CRYPT_PKCS7_H */ + +#endif /* HAVE_PKCS7 */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/poly1305.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/poly1305.h new file mode 100644 index 0000000..bceb772 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/poly1305.h @@ -0,0 +1,38 @@ +/* poly1305.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifdef HAVE_POLY1305 + +#ifndef CTAO_CRYPT_POLY1305_H +#define CTAO_CRYPT_POLY1305_H + +#include + +/* for poly1305 reverse compatibility */ +#define Poly1305SetKey wc_Poly1305SetKey +#define Poly1305Update wc_Poly1305Update +#define Poly1305Final wc_Poly1305Final + +#endif /* CTAO_CRYPT_POLY1305_H */ + +#endif /* HAVE_POLY1305 */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/port/pic32/pic32mz-crypt.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/port/pic32/pic32mz-crypt.h new file mode 100644 index 0000000..a5dca89 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/port/pic32/pic32mz-crypt.h @@ -0,0 +1,28 @@ +/* pic32mz-crypt.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#ifndef PIC32MZ_CRYPT_H +#define PIC32MZ_CRYPT_H + +#include + +#endif /* PIC32MZ_CRYPT_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/pwdbased.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/pwdbased.h new file mode 100644 index 0000000..7d6dced --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/pwdbased.h @@ -0,0 +1,36 @@ +/* pwdbased.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifndef NO_PWDBASED + +#ifndef CTAO_CRYPT_PWDBASED_H +#define CTAO_CRYPT_PWDBASED_H + +/* for pwdbased reverse compatibility */ +#include +#define PBKDF1 wc_PBKDF1 +#define PBKDF2 wc_PBKDF2 +#define PKCS12_PBKDF wc_PKCS12_PBKDF + +#endif /* CTAO_CRYPT_PWDBASED_H */ +#endif /* NO_PWDBASED */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/rabbit.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/rabbit.h new file mode 100644 index 0000000..a6e92ec --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/rabbit.h @@ -0,0 +1,39 @@ +/* rabbit.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifndef NO_RABBIT + +#ifndef CTAO_CRYPT_RABBIT_H +#define CTAO_CRYPT_RABBIT_H + +#include + +/* for rabbit reverse compatibility */ +#ifndef NO_RABBIT + #define RabbitProcess wc_RabbitProcess + #define RabbitSetKey wc_RabbitSetKey +#endif + +#endif /* CTAO_CRYPT_RABBIT_H */ + +#endif /* NO_RABBIT */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/random.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/random.h new file mode 100644 index 0000000..6d3a96f --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/random.h @@ -0,0 +1,38 @@ +/* random.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifndef CTAO_CRYPT_RANDOM_H +#define CTAO_CRYPT_RANDOM_H + + /* for random.h compatibility */ + #include + #define InitRng wc_InitRng + #define RNG_GenerateBlock wc_RNG_GenerateBlock + #define RNG_GenerateByte wc_RNG_GenerateByte + #define FreeRng wc_FreeRng + + #if defined(HAVE_HASHDRBG) || defined(NO_RC4) + #define RNG_HealthTest wc_RNG_HealthTest + #endif /* HAVE_HASHDRBG || NO_RC4 */ + +#endif /* CTAO_CRYPT_RANDOM_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/ripemd.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/ripemd.h new file mode 100644 index 0000000..4458fcc --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/ripemd.h @@ -0,0 +1,37 @@ +/* ripemd.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + + +#ifndef CTAO_CRYPT_RIPEMD_H +#define CTAO_CRYPT_RIPEME_H + +#include + +/* for ripemd reverse compatibility */ +#ifdef WOLFSSL_RIPEMD + #define InitRipeMd wc_InitRipeMd + #define RipeMdUpdate wc_RipeMdUpdate + #define RipeMdFinal wc_RipeMdFinal +#endif + +#endif /* CTAO_CRYPT_RIPEMD_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/rsa.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/rsa.h new file mode 100644 index 0000000..72f8dc5 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/rsa.h @@ -0,0 +1,56 @@ +/* rsa.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#ifndef NO_RSA + +#ifndef CTAO_CRYPT_RSA_H +#define CTAO_CRYPT_RSA_H + +#include +/* includes for their compatibility */ +#include +#include +#include + +#define InitRsaKey wc_InitRsaKey +#define FreeRsaKey wc_FreeRsaKey +#define RsaPublicEncrypt wc_RsaPublicEncrypt +#define RsaPrivateDecryptInline wc_RsaPrivateDecryptInline +#define RsaPrivateDecrypt wc_RsaPrivateDecrypt +#define RsaSSL_Sign wc_RsaSSL_Sign +#define RsaSSL_VerifyInline wc_RsaSSL_VerifyInline +#define RsaSSL_Verify wc_RsaSSL_Verify +#define RsaEncryptSize wc_RsaEncryptSize +#define RsaFlattenPublicKey wc_RsaFlattenPublicKey + +#ifdef WOLFSSL_KEY_GEN + #define MakeRsaKey wc_MakeRsaKey + #define RsaKeyToDer wc_RsaKeyToDer +#endif + +#ifdef HAVE_CAVIUM + #define RsaInitCavium wc_RsaInitCavium + #define RsaFreeCavium wc_RsaFreeCavium +#endif + +#endif /* CTAO_CRYPT_RSA_H */ + +#endif /* NO_RSA */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/settings.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/settings.h new file mode 100644 index 0000000..2d1ab55 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/settings.h @@ -0,0 +1,745 @@ +/* settings.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +/* Place OS specific preprocessor flags, defines, includes here, will be + included into every file because types.h includes it */ + + +#ifndef CTAO_CRYPT_SETTINGS_H +#define CTAO_CRYPT_SETTINGS_H + +/* for reverse compatibility after name change */ +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/* Uncomment next line if using IPHONE */ +/* #define IPHONE */ + +/* Uncomment next line if using ThreadX */ +/* #define THREADX */ + +/* Uncomment next line if using Micrium ucOS */ +/* #define MICRIUM */ + +/* Uncomment next line if using Mbed */ +/* #define MBED */ + +/* Uncomment next line if using Microchip PIC32 ethernet starter kit */ +/* #define MICROCHIP_PIC32 */ + +/* Uncomment next line if using Microchip TCP/IP stack, version 5 */ +/* #define MICROCHIP_TCPIP_V5 */ + +/* Uncomment next line if using Microchip TCP/IP stack, version 6 or later */ +/* #define MICROCHIP_TCPIP */ + +/* Uncomment next line if using PIC32MZ Crypto Engine */ +/* #define CYASSL_MICROCHIP_PIC32MZ */ + +/* Uncomment next line if using FreeRTOS */ +/* #define FREERTOS */ + +/* Uncomment next line if using FreeRTOS Windows Simulator */ +/* #define FREERTOS_WINSIM */ + +/* Uncomment next line if using RTIP */ +/* #define EBSNET */ + +/* Uncomment next line if using lwip */ +/* #define CYASSL_LWIP */ + +/* Uncomment next line if building CyaSSL for a game console */ +/* #define CYASSL_GAME_BUILD */ + +/* Uncomment next line if building CyaSSL for LSR */ +/* #define CYASSL_LSR */ + +/* Uncomment next line if building CyaSSL for Freescale MQX/RTCS/MFS */ +/* #define FREESCALE_MQX */ + +/* Uncomment next line if using STM32F2 */ +/* #define CYASSL_STM32F2 */ + +/* Uncomment next line if using Comverge settings */ +/* #define COMVERGE */ + +/* Uncomment next line if using QL SEP settings */ +/* #define CYASSL_QL */ + +/* Uncomment next line if building for EROAD */ +/* #define CYASSL_EROAD */ + +/* Uncomment next line if building for IAR EWARM */ +/* #define CYASSL_IAR_ARM */ + +/* Uncomment next line if using TI-RTOS settings */ +/* #define CYASSL_TIRTOS */ + +/* Uncomment next line if building with PicoTCP */ +/* #define CYASSL_PICOTCP */ + +/* Uncomment next line if building for PicoTCP demo bundle */ +/* #define CYASSL_PICOTCP_DEMO */ + +#include + +#ifdef IPHONE + #define SIZEOF_LONG_LONG 8 +#endif + + +#ifdef CYASSL_USER_SETTINGS + #include +#endif + + +#ifdef COMVERGE + #define THREADX + #define HAVE_NETX + #define CYASSL_USER_IO + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_FILESYSTEM + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 + #define NO_RSA + #define NO_SESSION_CACHE + #define HAVE_ECC +#endif + + +#ifdef THREADX + #define SIZEOF_LONG_LONG 8 +#endif + +#ifdef HAVE_NETX + #include "nx_api.h" +#endif + +#if defined(HAVE_LWIP_NATIVE) /* using LwIP native TCP socket */ + #define CYASSL_LWIP + #define NO_WRITEV + #define SINGLE_THREADED + #define CYASSL_USER_IO + #define NO_FILESYSTEM +#endif + +#if defined(CYASSL_IAR_ARM) + #define NO_MAIN_DRIVER + #define SINGLE_THREADED + #define USE_CERT_BUFFERS_1024 + #define BENCH_EMBEDDED + #define NO_FILESYSTEM + #define NO_WRITEV + #define CYASSL_USER_IO + #define BENCH_EMBEDDED +#endif + +#ifdef MICROCHIP_PIC32 + /* #define CYASSL_MICROCHIP_PIC32MZ */ + #define SIZEOF_LONG_LONG 8 + #define SINGLE_THREADED + #define CYASSL_USER_IO + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_FILESYSTEM + #define USE_FAST_MATH + #define TFM_TIMING_RESISTANT +#endif + +#ifdef CYASSL_MICROCHIP_PIC32MZ + #define CYASSL_PIC32MZ_CE + #define CYASSL_PIC32MZ_CRYPT + #define HAVE_AES_ENGINE + #define CYASSL_PIC32MZ_RNG + /* #define CYASSL_PIC32MZ_HASH */ + #define CYASSL_AES_COUNTER + #define HAVE_AESGCM + #define NO_BIG_INT + +#endif + +#ifdef MICROCHIP_TCPIP_V5 + /* include timer functions */ + #include "TCPIP Stack/TCPIP.h" +#endif + +#ifdef MICROCHIP_TCPIP + /* include timer, NTP functions */ + #ifdef MICROCHIP_MPLAB_HARMONY + #include "tcpip/tcpip.h" + #else + #include "system/system_services.h" + #include "tcpip/sntp.h" + #endif +#endif + +#ifdef MBED + #define CYASSL_USER_IO + #define NO_FILESYSTEM + #define NO_CERT + #define USE_CERT_BUFFERS_1024 + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 + #define HAVE_ECC + #define NO_SESSION_CACHE + #define CYASSL_CMSIS_RTOS +#endif + + +#ifdef CYASSL_EROAD + #define FREESCALE_MQX + #define FREESCALE_MMCAU + #define SINGLE_THREADED + #define NO_STDIO_FILESYSTEM + #define CYASSL_LEANPSK + #define HAVE_NULL_CIPHER + #define NO_OLD_TLS + #define NO_ASN + #define NO_BIG_INT + #define NO_RSA + #define NO_DSA + #define NO_DH + #define NO_CERTS + #define NO_PWDBASED + #define NO_DES3 + #define NO_MD4 + #define NO_RC4 + #define NO_MD5 + #define NO_SESSION_CACHE + #define NO_MAIN_DRIVER +#endif + +#ifdef CYASSL_PICOTCP + #define errno pico_err + #include "pico_defines.h" + #include "pico_stack.h" + #include "pico_constants.h" + #define CUSTOM_RAND_GENERATE pico_rand +#endif + +#ifdef CYASSL_PICOTCP_DEMO + #define CYASSL_STM32 + #define USE_FAST_MATH + #define TFM_TIMING_RESISTANT + #define XMALLOC(s, h, type) PICO_ZALLOC((s)) + #define XFREE(p, h, type) PICO_FREE((p)) + #define SINGLE_THREADED + #define NO_WRITEV + #define CYASSL_USER_IO + #define NO_DEV_RANDOM + #define NO_FILESYSTEM +#endif + +#ifdef FREERTOS_WINSIM + #define FREERTOS + #define USE_WINDOWS_API +#endif + + +/* Micrium will use Visual Studio for compilation but not the Win32 API */ +#if defined(_WIN32) && !defined(MICRIUM) && !defined(FREERTOS) \ + && !defined(EBSNET) && !defined(CYASSL_EROAD) + #define USE_WINDOWS_API +#endif + + +#if defined(CYASSL_LEANPSK) && !defined(XMALLOC_USER) + #include + #define XMALLOC(s, h, type) malloc((s)) + #define XFREE(p, h, type) free((p)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) +#endif + +#if defined(XMALLOC_USER) && defined(SSN_BUILDING_LIBYASSL) + #undef XMALLOC + #define XMALLOC yaXMALLOC + #undef XFREE + #define XFREE yaXFREE + #undef XREALLOC + #define XREALLOC yaXREALLOC +#endif + + +#ifdef FREERTOS + #ifndef NO_WRITEV + #define NO_WRITEV + #endif + #ifndef NO_SHA512 + #define NO_SHA512 + #endif + #ifndef NO_DH + #define NO_DH + #endif + #ifndef NO_DSA + #define NO_DSA + #endif + #ifndef NO_HC128 + #define NO_HC128 + #endif + + #ifndef SINGLE_THREADED + #include "FreeRTOS.h" + #include "semphr.h" + #endif +#endif + +#ifdef CYASSL_TIRTOS + #define SIZEOF_LONG_LONG 8 + #define NO_WRITEV + #define NO_CYASSL_DIR + #define USE_FAST_MATH + #define TFM_TIMING_RESISTANT + #define NO_DEV_RANDOM + #define NO_FILESYSTEM + #define USE_CERT_BUFFERS_2048 + #define NO_ERROR_STRINGS + #define USER_TIME + + #ifdef __IAR_SYSTEMS_ICC__ + #pragma diag_suppress=Pa089 + #elif !defined(__GNUC__) + /* Suppress the sslpro warning */ + #pragma diag_suppress=11 + #endif + + #include +#endif + +#ifdef EBSNET + #include "rtip.h" + + /* #define DEBUG_CYASSL */ + #define NO_CYASSL_DIR /* tbd */ + + #if (POLLOS) + #define SINGLE_THREADED + #endif + + #if (RTPLATFORM) + #if (!RTP_LITTLE_ENDIAN) + #define BIG_ENDIAN_ORDER + #endif + #else + #if (!KS_LITTLE_ENDIAN) + #define BIG_ENDIAN_ORDER + #endif + #endif + + #if (WINMSP3) + #undef SIZEOF_LONG + #define SIZEOF_LONG_LONG 8 + #else + #sslpro: settings.h - please implement SIZEOF_LONG and SIZEOF_LONG_LONG + #endif + + #define XMALLOC(s, h, type) ((void *)rtp_malloc((s), SSL_PRO_MALLOC)) + #define XFREE(p, h, type) (rtp_free(p)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) + +#endif /* EBSNET */ + +#ifdef CYASSL_GAME_BUILD + #define SIZEOF_LONG_LONG 8 + #if defined(__PPU) || defined(__XENON) + #define BIG_ENDIAN_ORDER + #endif +#endif + +#ifdef CYASSL_LSR + #define HAVE_WEBSERVER + #define SIZEOF_LONG_LONG 8 + #define CYASSL_LOW_MEMORY + #define NO_WRITEV + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 + #define NO_DEV_RANDOM + #define NO_CYASSL_DIR + #define NO_RABBIT + #ifndef NO_FILESYSTEM + #define LSR_FS + #include "inc/hw_types.h" + #include "fs.h" + #endif + #define CYASSL_LWIP + #include /* for tcp errno */ + #define CYASSL_SAFERTOS + #if defined(__IAR_SYSTEMS_ICC__) + /* enum uses enum */ + #pragma diag_suppress=Pa089 + #endif +#endif + +#ifdef CYASSL_SAFERTOS + #ifndef SINGLE_THREADED + #include "SafeRTOS/semphr.h" + #endif + + #include "SafeRTOS/heap.h" + #define XMALLOC(s, h, type) pvPortMalloc((s)) + #define XFREE(p, h, type) vPortFree((p)) + #define XREALLOC(p, n, h, t) pvPortRealloc((p), (n)) +#endif + +#ifdef CYASSL_LOW_MEMORY + #undef RSA_LOW_MEM + #define RSA_LOW_MEM + #undef CYASSL_SMALL_STACK + #define CYASSL_SMALL_STACK + #undef TFM_TIMING_RESISTANT + #define TFM_TIMING_RESISTANT +#endif + +#ifdef FREESCALE_MQX + #define SIZEOF_LONG_LONG 8 + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_RABBIT + #define NO_CYASSL_DIR + #define USE_FAST_MATH + #define TFM_TIMING_RESISTANT + #define FREESCALE_K70_RNGA + /* #define FREESCALE_K53_RNGB */ + #include "mqx.h" + #ifndef NO_FILESYSTEM + #include "mfs.h" + #include "fio.h" + #endif + #ifndef SINGLE_THREADED + #include "mutex.h" + #endif + + #define XMALLOC(s, h, t) (void *)_mem_alloc_system((s)) + #define XFREE(p, h, t) {void* xp = (p); if ((xp)) _mem_free((xp));} + /* Note: MQX has no realloc, using fastmath above */ +#endif + +#ifdef CYASSL_STM32F2 + #define SIZEOF_LONG_LONG 8 + #define NO_DEV_RANDOM + #define NO_CYASSL_DIR + #define NO_RABBIT + #define STM32F2_RNG + #define STM32F2_CRYPTO + #define KEIL_INTRINSICS +#endif + +#ifdef MICRIUM + + #include "stdlib.h" + #include "net_cfg.h" + #include "ssl_cfg.h" + #include "net_secure_os.h" + + #define CYASSL_TYPES + + typedef CPU_INT08U byte; + typedef CPU_INT16U word16; + typedef CPU_INT32U word32; + + #if (NET_SECURE_MGR_CFG_WORD_SIZE == CPU_WORD_SIZE_32) + #define SIZEOF_LONG 4 + #undef SIZEOF_LONG_LONG + #else + #undef SIZEOF_LONG + #define SIZEOF_LONG_LONG 8 + #endif + + #define STRING_USER + + #define XSTRLEN(pstr) ((CPU_SIZE_T)Str_Len((CPU_CHAR *)(pstr))) + #define XSTRNCPY(pstr_dest, pstr_src, len_max) \ + ((CPU_CHAR *)Str_Copy_N((CPU_CHAR *)(pstr_dest), \ + (CPU_CHAR *)(pstr_src), (CPU_SIZE_T)(len_max))) + #define XSTRNCMP(pstr_1, pstr_2, len_max) \ + ((CPU_INT16S)Str_Cmp_N((CPU_CHAR *)(pstr_1), \ + (CPU_CHAR *)(pstr_2), (CPU_SIZE_T)(len_max))) + #define XSTRSTR(pstr, pstr_srch) \ + ((CPU_CHAR *)Str_Str((CPU_CHAR *)(pstr), \ + (CPU_CHAR *)(pstr_srch))) + #define XMEMSET(pmem, data_val, size) \ + ((void)Mem_Set((void *)(pmem), (CPU_INT08U) (data_val), \ + (CPU_SIZE_T)(size))) + #define XMEMCPY(pdest, psrc, size) ((void)Mem_Copy((void *)(pdest), \ + (void *)(psrc), (CPU_SIZE_T)(size))) + #define XMEMCMP(pmem_1, pmem_2, size) \ + (((CPU_BOOLEAN)Mem_Cmp((void *)(pmem_1), (void *)(pmem_2), \ + (CPU_SIZE_T)(size))) ? DEF_NO : DEF_YES) + #define XMEMMOVE XMEMCPY + +#if (NET_SECURE_MGR_CFG_EN == DEF_ENABLED) + #define MICRIUM_MALLOC + #define XMALLOC(s, h, type) ((void *)NetSecure_BlkGet((CPU_INT08U)(type), \ + (CPU_SIZE_T)(s), (void *)0)) + #define XFREE(p, h, type) (NetSecure_BlkFree((CPU_INT08U)(type), \ + (p), (void *)0)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) +#endif + + #if (NET_SECURE_MGR_CFG_FS_EN == DEF_ENABLED) + #undef NO_FILESYSTEM + #else + #define NO_FILESYSTEM + #endif + + #if (SSL_CFG_TRACE_LEVEL == CYASSL_TRACE_LEVEL_DBG) + #define DEBUG_CYASSL + #else + #undef DEBUG_CYASSL + #endif + + #if (SSL_CFG_OPENSSL_EN == DEF_ENABLED) + #define OPENSSL_EXTRA + #else + #undef OPENSSL_EXTRA + #endif + + #if (SSL_CFG_MULTI_THREAD_EN == DEF_ENABLED) + #undef SINGLE_THREADED + #else + #define SINGLE_THREADED + #endif + + #if (SSL_CFG_DH_EN == DEF_ENABLED) + #undef NO_DH + #else + #define NO_DH + #endif + + #if (SSL_CFG_DSA_EN == DEF_ENABLED) + #undef NO_DSA + #else + #define NO_DSA + #endif + + #if (SSL_CFG_PSK_EN == DEF_ENABLED) + #undef NO_PSK + #else + #define NO_PSK + #endif + + #if (SSL_CFG_3DES_EN == DEF_ENABLED) + #undef NO_DES + #else + #define NO_DES + #endif + + #if (SSL_CFG_AES_EN == DEF_ENABLED) + #undef NO_AES + #else + #define NO_AES + #endif + + #if (SSL_CFG_RC4_EN == DEF_ENABLED) + #undef NO_RC4 + #else + #define NO_RC4 + #endif + + #if (SSL_CFG_RABBIT_EN == DEF_ENABLED) + #undef NO_RABBIT + #else + #define NO_RABBIT + #endif + + #if (SSL_CFG_HC128_EN == DEF_ENABLED) + #undef NO_HC128 + #else + #define NO_HC128 + #endif + + #if (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_BIG) + #define BIG_ENDIAN_ORDER + #else + #undef BIG_ENDIAN_ORDER + #define LITTLE_ENDIAN_ORDER + #endif + + #if (SSL_CFG_MD4_EN == DEF_ENABLED) + #undef NO_MD4 + #else + #define NO_MD4 + #endif + + #if (SSL_CFG_WRITEV_EN == DEF_ENABLED) + #undef NO_WRITEV + #else + #define NO_WRITEV + #endif + + #if (SSL_CFG_USER_RNG_SEED_EN == DEF_ENABLED) + #define NO_DEV_RANDOM + #else + #undef NO_DEV_RANDOM + #endif + + #if (SSL_CFG_USER_IO_EN == DEF_ENABLED) + #define CYASSL_USER_IO + #else + #undef CYASSL_USER_IO + #endif + + #if (SSL_CFG_DYNAMIC_BUFFERS_EN == DEF_ENABLED) + #undef LARGE_STATIC_BUFFERS + #undef STATIC_CHUNKS_ONLY + #else + #define LARGE_STATIC_BUFFERS + #define STATIC_CHUNKS_ONLY + #endif + + #if (SSL_CFG_DER_LOAD_EN == DEF_ENABLED) + #define CYASSL_DER_LOAD + #else + #undef CYASSL_DER_LOAD + #endif + + #if (SSL_CFG_DTLS_EN == DEF_ENABLED) + #define CYASSL_DTLS + #else + #undef CYASSL_DTLS + #endif + + #if (SSL_CFG_CALLBACKS_EN == DEF_ENABLED) + #define CYASSL_CALLBACKS + #else + #undef CYASSL_CALLBACKS + #endif + + #if (SSL_CFG_FAST_MATH_EN == DEF_ENABLED) + #define USE_FAST_MATH + #else + #undef USE_FAST_MATH + #endif + + #if (SSL_CFG_TFM_TIMING_RESISTANT_EN == DEF_ENABLED) + #define TFM_TIMING_RESISTANT + #else + #undef TFM_TIMING_RESISTANT + #endif + +#endif /* MICRIUM */ + + +#ifdef CYASSL_QL + #ifndef CYASSL_SEP + #define CYASSL_SEP + #endif + #ifndef OPENSSL_EXTRA + #define OPENSSL_EXTRA + #endif + #ifndef SESSION_CERTS + #define SESSION_CERTS + #endif + #ifndef HAVE_AESCCM + #define HAVE_AESCCM + #endif + #ifndef ATOMIC_USER + #define ATOMIC_USER + #endif + #ifndef CYASSL_DER_LOAD + #define CYASSL_DER_LOAD + #endif + #ifndef KEEP_PEER_CERT + #define KEEP_PEER_CERT + #endif + #ifndef HAVE_ECC + #define HAVE_ECC + #endif + #ifndef SESSION_INDEX + #define SESSION_INDEX + #endif +#endif /* CYASSL_QL */ + + +#if !defined(XMALLOC_USER) && !defined(MICRIUM_MALLOC) && \ + !defined(CYASSL_LEANPSK) && !defined(NO_CYASSL_MEMORY) + #define USE_CYASSL_MEMORY +#endif + + +#if defined(OPENSSL_EXTRA) && !defined(NO_CERTS) + #undef KEEP_PEER_CERT + #define KEEP_PEER_CERT +#endif + + +/* stream ciphers except arc4 need 32bit alignment, intel ok without */ +#ifndef XSTREAM_ALIGNMENT + #if defined(__x86_64__) || defined(__ia64__) || defined(__i386__) + #define NO_XSTREAM_ALIGNMENT + #else + #define XSTREAM_ALIGNMENT + #endif +#endif + + +/* FreeScale MMCAU hardware crypto has 4 byte alignment */ +#ifdef FREESCALE_MMCAU + #define CYASSL_MMCAU_ALIGNMENT 4 +#endif + +/* if using hardware crypto and have alignment requirements, specify the + requirement here. The record header of SSL/TLS will prvent easy alignment. + This hint tries to help as much as possible. */ +#ifndef CYASSL_GENERAL_ALIGNMENT + #ifdef CYASSL_AESNI + #define CYASSL_GENERAL_ALIGNMENT 16 + #elif defined(XSTREAM_ALIGNMENT) + #define CYASSL_GENERAL_ALIGNMENT 4 + #elif defined(FREESCALE_MMCAU) + #define CYASSL_GENERAL_ALIGNMENT CYASSL_MMCAU_ALIGNMENT + #else + #define CYASSL_GENERAL_ALIGNMENT 0 + #endif +#endif + +#ifdef HAVE_CRL + /* not widely supported yet */ + #undef NO_SKID + #define NO_SKID +#endif + + +#ifdef __INTEL_COMPILER + #pragma warning(disable:2259) /* explicit casts to smaller sizes, disable */ +#endif + + +/* Place any other flags or defines here */ + + +#ifdef __cplusplus + } /* extern "C" */ +#endif + + +#endif /* CTAO_CRYPT_SETTINGS_H */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/settings_comp.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/settings_comp.h new file mode 100644 index 0000000..89278a2 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/settings_comp.h @@ -0,0 +1,58 @@ +/* settings_comp.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#ifndef CTAO_CRYPT_SETTINGS_C_H +#define CTAO_CRYPT_SETTINGS_C_H + + +/* since fips overrides rsa.h map compatibility here */ +#if !defined(NO_RSA) + #ifdef WOLFSSL_KEY_GEN + #define RsaKeyToDer wc_RsaKeyToDer + #endif + + #define RsaPrivateKeyDecode wc_RsaPrivateKeyDecode + #define RsaPublicKeyDecode wc_RsaPublicKeyDecode + #define RsaPublicKeyDecodeRaw wc_RsaPublicKeyDecodeRaw +#endif /* have rsa and HAVE_FIPS */ + +/* Macro redefinitions for compatibility */ +#ifdef HAVE_NTRU + #define MakeNtruCert wc_MakeNtruCert +#endif +#if defined(WOLFSSL_SHA512) && !defined(CYASSL_SHA512) + #define CYASSL_SHA512 +#endif +#if defined(WOLFSSL_SHA384) && !defined(CYASSL_SHA384) + #define CYASSL_SHA384 +#endif +#if defined(WOLFSSL_LEANPSK) && !defined(CYASSL_LEANPSK) + #define CYASSL_LEANPSK +#endif +#if defined(NO_WOLFSSL_MEMORY) && !defined(NO_CYASSL_MEMORY) + #define NO_CYASSL_MEMORY +#endif +#ifdef WOLFSSL_KEY_GEN + #define CYASSL_KEY_GEN +#endif + +#endif /* CTAO_CRYPT_SETTINGS_C_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/sha.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/sha.h new file mode 100644 index 0000000..56927e2 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/sha.h @@ -0,0 +1,36 @@ +/* sha.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifndef NO_SHA + +#ifndef CTAO_CRYPT_SHA_H +#define CTAO_CRYPT_SHA_H + +#include +#define InitSha wc_InitSha +#define ShaUpdate wc_ShaUpdate +#define ShaFinal wc_ShaFinal +#define ShaHash wc_ShaHash + +#endif /* CTAO_CRYPT_SHA_H */ +#endif /* NO_SHA */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/sha256.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/sha256.h new file mode 100644 index 0000000..b8b1f24 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/sha256.h @@ -0,0 +1,39 @@ +/* sha256.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +/* code submitted by raphael.huck@efixo.com */ + + +#ifndef NO_SHA256 + +#ifndef CTAO_CRYPT_SHA256_H +#define CTAO_CRYPT_SHA256_H + +#include +#define InitSha256 wc_InitSha256 +#define Sha256Update wc_Sha256Update +#define Sha256Final wc_Sha256Final +#define Sha256Hash wc_Sha256Hash + +#endif /* CTAO_CRYPT_SHA256_H */ +#endif /* NO_SHA256 */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/sha512.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/sha512.h new file mode 100644 index 0000000..3eab760 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/sha512.h @@ -0,0 +1,40 @@ +/* sha512.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifndef CTAO_CRYPT_SHA512_H +#define CTAO_CRYPT_SHA512_H + +#include +#define InitSha512 wc_InitSha512 +#define Sha512Update wc_Sha512Update +#define Sha512Final wc_Sha512Final +#define Sha512Hash wc_Sha512Hash + +#if defined(WOLFSSL_SHA384) || defined(HAVE_AESGCM) + #define InitSha384 wc_InitSha384 + #define Sha384Update wc_Sha384Update + #define Sha384Final wc_Sha384Final + #define Sha384Hash wc_Sha384Hash +#endif /* WOLFSSL_SHA384 */ + +#endif /* CTAO_CRYPT_SHA512_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/tfm.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/tfm.h new file mode 100644 index 0000000..0b16b51 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/tfm.h @@ -0,0 +1,41 @@ +/* tfm.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +/* + * Based on public domain TomsFastMath 0.10 by Tom St Denis, tomstdenis@iahu.ca, + * http://math.libtomcrypt.com + */ + + +/** + * Edited by Moisés Guimarães (moises.guimaraes@phoebus.com.br) + * to fit CyaSSL's needs. + */ + + +#ifndef CTAO_CRYPT_TFM_H +#define CTAO_CRYPT_TFM_H + +#include + +#endif /* CTAO_CRYPT_TFM_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/types.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/types.h new file mode 100644 index 0000000..95bfb45 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/types.h @@ -0,0 +1,39 @@ +/* types.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifndef CTAO_CRYPT_TYPES_H +#define CTAO_CRYPT_TYPES_H + +#include +#include +#include + +/* compatibility macros */ +#define CYASSL_WORD_SIZE WOLFSSL_WORD_SIZE +#define CYASSL_BIT_SIZE WOLFSSL_BIT_SIZE +#define CYASSL_MAX_16BIT WOLFSSL_MAX_16BIT +#define CYASSL_MAX_ERROR_SZ WOLFSSL_MAX_ERROR_SZ +#define cyassl_word wolfssl_word +#define CYASSL_MAX_ERROR_SZ WOLFSSL_MAX_ERROR_SZ + +#endif /* CTAO_CRYPT_TYPES_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/visibility.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/visibility.h new file mode 100644 index 0000000..6bb4953 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/visibility.h @@ -0,0 +1,72 @@ +/* visibility.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +/* Visibility control macros */ + +#ifndef CTAO_CRYPT_VISIBILITY_H +#define CTAO_CRYPT_VISIBILITY_H + +/* fips compatibility @wc_fips */ +#ifndef HAVE_FIPS + #include + #define CYASSL_API WOLFSSL_API + #define CYASSL_LOCAL WOLFSSL_LOCAL +#else +/* CYASSL_API is used for the public API symbols. + It either imports or exports (or does nothing for static builds) + + CYASSL_LOCAL is used for non-API symbols (private). +*/ + +#if defined(BUILDING_WOLFSSL) + #if defined(HAVE_VISIBILITY) && HAVE_VISIBILITY + #define CYASSL_API __attribute__ ((visibility("default"))) + #define CYASSL_LOCAL __attribute__ ((visibility("hidden"))) + #elif defined(__SUNPRO_C) && (__SUNPRO_C >= 0x550) + #define CYASSL_API __global + #define CYASSL_LOCAL __hidden + #elif defined(_MSC_VER) + #ifdef CYASSL_DLL + #define CYASSL_API extern __declspec(dllexport) + #else + #define CYASSL_API + #endif + #define CYASSL_LOCAL + #else + #define CYASSL_API + #define CYASSL_LOCAL + #endif /* HAVE_VISIBILITY */ +#else /* BUILDING_WOLFSSL */ + #if defined(_MSC_VER) + #ifdef CYASSL_DLL + #define CYASSL_API extern __declspec(dllimport) + #else + #define CYASSL_API + #endif + #define CYASSL_LOCAL + #else + #define CYASSL_API + #define CYASSL_LOCAL + #endif +#endif /* BUILDING_WOLFSSL */ +#endif /* HAVE_FIPS */ +#endif /* CTAO_CRYPT_VISIBILITY_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/wc_port.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/wc_port.h new file mode 100644 index 0000000..f35a451 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ctaocrypt/wc_port.h @@ -0,0 +1,31 @@ +/* port.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#ifndef CTAO_CRYPT_PORT_H +#define CTAO_CRYPT_PORT_H + +#include +#include +#define CyaSSL_Mutex wolfSSL_Mutex + +#endif /* CTAO_CRYPT_PORT_H */ + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/error-ssl.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/error-ssl.h new file mode 100644 index 0000000..8eab843 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/error-ssl.h @@ -0,0 +1,22 @@ +/* error-ssl.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/include.am new file mode 100644 index 0000000..db1f089 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/include.am @@ -0,0 +1,25 @@ +# vim:ft=automake +# All paths should be given relative to the root +# + +include cyassl/ctaocrypt/include.am +include cyassl/openssl/include.am + +EXTRA_DIST+= cyassl/sniffer_error.rc + +nobase_include_HEADERS+= \ + cyassl/error-ssl.h \ + cyassl/ssl.h \ + cyassl/sniffer_error.h \ + cyassl/sniffer.h \ + cyassl/callbacks.h \ + cyassl/certs_test.h \ + cyassl/test.h \ + cyassl/version.h \ + cyassl/options.h \ + cyassl/ocsp.h \ + cyassl/crl.h + +noinst_HEADERS+= \ + cyassl/internal.h + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/internal.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/internal.h new file mode 100644 index 0000000..c0ba722 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/internal.h @@ -0,0 +1,22 @@ +/* internal.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ocsp.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ocsp.h new file mode 100644 index 0000000..1ad9efe --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ocsp.h @@ -0,0 +1,22 @@ +/* ocsp.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/asn1.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/asn1.h new file mode 100644 index 0000000..35be23f --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/asn1.h @@ -0,0 +1,3 @@ +/* asn1.h for openssl */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/bio.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/bio.h new file mode 100644 index 0000000..8f52983 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/bio.h @@ -0,0 +1,4 @@ +/* bio.h for openssl */ + +#include + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/bn.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/bn.h new file mode 100644 index 0000000..e14f4e2 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/bn.h @@ -0,0 +1,3 @@ +/* bn.h for openssl */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/conf.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/conf.h new file mode 100644 index 0000000..4005ea9 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/conf.h @@ -0,0 +1,3 @@ +/* conf.h for openssl */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/crypto.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/crypto.h new file mode 100644 index 0000000..32e1108 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/crypto.h @@ -0,0 +1,4 @@ +/* crypto.h for openSSL */ + +#include + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/des.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/des.h new file mode 100644 index 0000000..0c8d55c --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/des.h @@ -0,0 +1,27 @@ +/* des.h + * + * Copyright (C) 2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +/* des.h defines mini des openssl compatibility layer + * + */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/dh.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/dh.h new file mode 100644 index 0000000..6fd8e36 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/dh.h @@ -0,0 +1,4 @@ +/* dh.h for openSSL */ + + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/dsa.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/dsa.h new file mode 100644 index 0000000..2bb476b --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/dsa.h @@ -0,0 +1,3 @@ +/* dsa.h for openSSL */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/ec.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/ec.h new file mode 100644 index 0000000..1ce8aa9 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/ec.h @@ -0,0 +1,3 @@ +/* ec.h for openssl */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/ecdsa.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/ecdsa.h new file mode 100644 index 0000000..9a1c02b --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/ecdsa.h @@ -0,0 +1,3 @@ +/* ecdsa.h for openssl */ + +#include \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/engine.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/engine.h new file mode 100644 index 0000000..fcce4bd --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/engine.h @@ -0,0 +1,5 @@ +/* engine.h for libcurl */ + +#include + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/err.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/err.h new file mode 100644 index 0000000..3611117 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/err.h @@ -0,0 +1,3 @@ +/* err.h for openssl */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/evp.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/evp.h new file mode 100644 index 0000000..fe9f424 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/evp.h @@ -0,0 +1,27 @@ +/* evp.h + * + * Copyright (C) 2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +/* evp.h defines mini evp openssl compatibility layer + * + */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/hmac.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/hmac.h new file mode 100644 index 0000000..f35fd75 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/hmac.h @@ -0,0 +1,27 @@ +/* hmac.h + * + * Copyright (C) 2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +/* hmac.h defines mini hamc openssl compatibility layer + * + */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/include.am new file mode 100644 index 0000000..e531f76 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/include.am @@ -0,0 +1,36 @@ +# vim:ft=automake +# All paths should be given relative to the root + +nobase_include_HEADERS+= \ + cyassl/openssl/asn1.h \ + cyassl/openssl/bio.h \ + cyassl/openssl/bn.h \ + cyassl/openssl/conf.h \ + cyassl/openssl/crypto.h \ + cyassl/openssl/des.h \ + cyassl/openssl/dh.h \ + cyassl/openssl/dsa.h \ + cyassl/openssl/ecdsa.h \ + cyassl/openssl/ec.h \ + cyassl/openssl/engine.h \ + cyassl/openssl/err.h \ + cyassl/openssl/evp.h \ + cyassl/openssl/hmac.h \ + cyassl/openssl/lhash.h \ + cyassl/openssl/md4.h \ + cyassl/openssl/md5.h \ + cyassl/openssl/ripemd.h \ + cyassl/openssl/ocsp.h \ + cyassl/openssl/opensslconf.h \ + cyassl/openssl/opensslv.h \ + cyassl/openssl/ossl_typ.h \ + cyassl/openssl/pem.h \ + cyassl/openssl/pkcs12.h \ + cyassl/openssl/rand.h \ + cyassl/openssl/rsa.h \ + cyassl/openssl/sha.h \ + cyassl/openssl/ssl.h \ + cyassl/openssl/stack.h \ + cyassl/openssl/ui.h \ + cyassl/openssl/x509.h \ + cyassl/openssl/x509v3.h diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/lhash.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/lhash.h new file mode 100644 index 0000000..6285f6a --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/lhash.h @@ -0,0 +1,3 @@ +/* lhash.h for openSSL */ + +#include \ No newline at end of file diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/md4.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/md4.h new file mode 100644 index 0000000..fb0d437 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/md4.h @@ -0,0 +1,3 @@ +/* md4.h for libcurl */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/md5.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/md5.h new file mode 100644 index 0000000..f3dd4e4 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/md5.h @@ -0,0 +1,5 @@ +/* md5.h for openssl */ + + +#include + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/ocsp.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/ocsp.h new file mode 100644 index 0000000..8c0f468 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/ocsp.h @@ -0,0 +1,3 @@ +/* ocsp.h for libcurl */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/opensslconf.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/opensslconf.h new file mode 100644 index 0000000..7f21cd9 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/opensslconf.h @@ -0,0 +1,3 @@ +/* opensslconf.h for openSSL */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/opensslv.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/opensslv.h new file mode 100644 index 0000000..d119f82 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/opensslv.h @@ -0,0 +1,3 @@ +/* opensslv.h compatibility */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/ossl_typ.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/ossl_typ.h new file mode 100644 index 0000000..5e6e627 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/ossl_typ.h @@ -0,0 +1,3 @@ +/* ossl_typ.h for openssl */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/pem.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/pem.h new file mode 100644 index 0000000..a07b912 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/pem.h @@ -0,0 +1,3 @@ +/* pem.h for openssl */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/pkcs12.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/pkcs12.h new file mode 100644 index 0000000..1fb089f --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/pkcs12.h @@ -0,0 +1,3 @@ +/* pkcs12.h for openssl */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/rand.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/rand.h new file mode 100644 index 0000000..5bd77b6 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/rand.h @@ -0,0 +1,3 @@ +/* rand.h for openSSL */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/ripemd.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/ripemd.h new file mode 100644 index 0000000..b25de78 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/ripemd.h @@ -0,0 +1,3 @@ +/* ripemd.h for openssl */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/rsa.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/rsa.h new file mode 100644 index 0000000..06f10a5 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/rsa.h @@ -0,0 +1,3 @@ +/* rsa.h for openSSL */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/sha.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/sha.h new file mode 100644 index 0000000..ced3ca1 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/sha.h @@ -0,0 +1,3 @@ +/* sha.h for openssl */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/ssl.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/ssl.h new file mode 100644 index 0000000..094b994 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/ssl.h @@ -0,0 +1,27 @@ +/* ssl.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * a with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +/* ssl.h defines openssl compatibility layer + * + */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/stack.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/stack.h new file mode 100644 index 0000000..831502f --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/stack.h @@ -0,0 +1,3 @@ +/* stack.h for openssl */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/ui.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/ui.h new file mode 100644 index 0000000..b1f4042 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/ui.h @@ -0,0 +1,3 @@ +/* ui.h for openssl */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/x509.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/x509.h new file mode 100644 index 0000000..9d13002 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/x509.h @@ -0,0 +1,3 @@ +/* x509.h for openssl */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/x509v3.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/x509v3.h new file mode 100644 index 0000000..2a5240d --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/openssl/x509v3.h @@ -0,0 +1,3 @@ +/* x509v3.h for openssl */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/options.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/options.h new file mode 100644 index 0000000..ff58ee4 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/options.h @@ -0,0 +1,93 @@ +/* cyassl options.h + * generated from wolfssl/options.h + */ +/* wolfssl options.h +* generated from configure options +* +* Copyright (C) 2006-2015 wolfSSL Inc. +* +* This file is part of wolfSSL. (formerly known as CyaSSL) +* +*/ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef WOLFSSL_OPTIONS_IGNORE_SYS +#undef _POSIX_THREADS +#define _POSIX_THREADS +#endif + +#undef HAVE_THREAD_LS +#define HAVE_THREAD_LS + +#ifndef WOLFSSL_OPTIONS_IGNORE_SYS +#undef _THREAD_SAFE +#define _THREAD_SAFE +#endif + +#undef HAVE_AESGCM +#define HAVE_AESGCM + +#undef WOLFSSL_SHA512 +#define WOLFSSL_SHA512 + +#undef WOLFSSL_SHA384 +#define WOLFSSL_SHA384 + +#undef NO_DSA +#define NO_DSA + +#undef HAVE_ECC +#define HAVE_ECC + +#undef TFM_ECC256 +#define TFM_ECC256 + +#undef ECC_SHAMIR +#define ECC_SHAMIR + +#undef NO_PSK +#define NO_PSK + +#undef NO_RC4 +#define NO_RC4 + +#undef NO_MD4 +#define NO_MD4 + +#undef NO_HC128 +#define NO_HC128 + +#undef NO_RABBIT +#define NO_RABBIT + +#undef HAVE_POLY1305 +#define HAVE_POLY1305 + +#undef HAVE_ONE_TIME_AUTH +#define HAVE_ONE_TIME_AUTH + +#undef HAVE_CHACHA +#define HAVE_CHACHA + +#undef HAVE_HASHDRBG +#define HAVE_HASHDRBG + +#undef NO_PWDBASED +#define NO_PWDBASED + +#undef USE_FAST_MATH +#define USE_FAST_MATH + +#undef WOLFSSL_X86_64_BUILD +#define WOLFSSL_X86_64_BUILD + + +#ifdef __cplusplus +} +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/sniffer.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/sniffer.h new file mode 100644 index 0000000..2ae6744 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/sniffer.h @@ -0,0 +1,22 @@ +/* sniffer.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/sniffer_error.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/sniffer_error.h new file mode 100644 index 0000000..8b3e003 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/sniffer_error.h @@ -0,0 +1,22 @@ +/* sniffer_error.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/sniffer_error.rc b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/sniffer_error.rc new file mode 100644 index 0000000..8bcd692 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/sniffer_error.rc @@ -0,0 +1,93 @@ + +STRINGTABLE +{ + 1, "Out of Memory" + 2, "New SSL Sniffer Server Registered" + 3, "Checking IP Header" + 4, "SSL Sniffer Server Not Registered" + 5, "Checking TCP Header" + + 6, "SSL Sniffer Server Port Not Registered" + 7, "RSA Private Decrypt Error" + 8, "RSA Private Decode Error" + 9, "Set Cipher Spec Error" + 10, "Server Hello Input Malformed" + + 11, "Couldn't Resume Session Error" + 12, "Server Did Resumption" + 13, "Client Hello Input Malformed" + 14, "Client Trying to Resume" + 15, "Handshake Input Malformed" + + 16, "Got Hello Verify msg" + 17, "Got Server Hello msg" + 18, "Got Cert Request msg" + 19, "Got Server Key Exchange msg" + 20, "Got Cert msg" + + 21, "Got Server Hello Done msg" + 22, "Got Finished msg" + 23, "Got Client Hello msg" + 24, "Got Client Key Exchange msg" + 25, "Got Cert Verify msg" + + 26, "Got Unknown Handshake msg" + 27, "New SSL Sniffer Session created" + 28, "Couldn't create new SSL" + 29, "Got a Packet to decode" + 30, "No data present" + + 31, "Session Not Found" + 32, "Got an Old Client Hello msg" + 33, "Old Client Hello Input Malformed" + 34, "Old Client Hello OK" + 35, "Bad Old Client Hello" + + 36, "Bad Record Header" + 37, "Record Header Input Malformed" + 38, "Got a HandShake msg" + 39, "Bad HandShake msg" + 40, "Got a Change Cipher Spec msg" + + 41, "Got Application Data msg" + 42, "Bad Application Data" + 43, "Got an Alert msg" + 44, "Another msg to Process" + 45, "Removing Session From Table" + + 46, "Bad Key File" + 47, "Wrong IP Version" + 48, "Wrong Protocol type" + 49, "Packet Short for header processing" + 50, "Got Unknown Record Type" + + 51, "Can't Open Trace File" + 52, "Session in Fatal Error State" + 53, "Partial SSL record received" + 54, "Buffer Error, malformed input" + 55, "Added to Partial Input" + + 56, "Received a Duplicate Packet" + 57, "Received an Out of Order Packet" + 58, "Received an Overlap Duplicate Packet" + 59, "Received an Overlap Reassembly Begin Duplicate Packet" + 60, "Received an Overlap Reassembly End Duplicate Packet" + + 61, "Missed the Client Hello Entirely" + 62, "Got Hello Request msg" + 63, "Got Session Ticket msg" + 64, "Bad Input" + 65, "Bad Decrypt Type" + + 66, "Bad Finished Message Processing" + 67, "Bad Compression Type" + 68, "Bad DeriveKeys Error" + 69, "Saw ACK for Missing Packet Error" + 70, "Bad Decrypt Operation" + + 71, "Decrypt Keys Not Set Up" + 72, "Late Key Load Error" + 73, "Got Certificate Status msg" + 74, "RSA Key Missing Error" +} + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ssl.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ssl.h new file mode 100644 index 0000000..eadf296 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/ssl.h @@ -0,0 +1,720 @@ +/* ssl.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * a with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +/* + * ssl.h makes wolfssl backwards compatibile with cyassl + */ + +#ifndef WOLFSSL_CYASSL_H_ +#define WOLFSSL_CYASSL_H_ +/* + * Name change + * include the new ssl.h + */ +#include +#include +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#ifdef _WIN32 + /* wincrypt.h clashes */ + #undef X509_NAME +#endif + +#ifdef CYASSL_TIRTOS + #undef CYASSL_TIRTOS + #define CYASSL_TIRTOS WOLFSSL_TIRTOS +#endif + +#define CYASSL WOLFSSL +#define DEBUG_CYASSL DEBUG_WOLFSSL +#define CYASSL_CTX WOLFSSL_CTX +#define CYASSL_METHOD WOLFSSL_METHOD +#define CYASSL_SESSION WOLFSSL_SESSION + +#define CYASSL_X509 WOLFSSL_X509 +#define CYASSL_X509_NAME WOLFSSL_X509_NAME +#define CYASSL_X509_CHAIN WOLFSSL_X509_CHAIN +#ifdef WOLFSSL_SNIFFER + #define CYASSL_SNIFFER WOLFSSL_SNIFFER +#endif + +/* redeclare guard */ +#define CYASSL_TYPES_DEFINED WOLFSSL_TYPES_DEFINED + +/* legacy defines */ +#define yasslIP wolfSSLIP /**/ +#define yasslPort wolfSSLPort /**/ + +/* cyassl/ssl.h (structs) */ +#define CYASSL_RSA WOLFSSL_RSA +#define CYASSL_DSA WOLFSSL_DSA +#define CYASSL_BIO WOLFSSL_BIO +#define CYASSL_CIPHER WOLFSSL_CIPHER +#define CYASSL_MD4_CTX WOLFSSL_MD4_CTX +#define CYASSL_MFL_2_9 WOLFSSL_MFL_2_9 /**/ +#define CYASSL_MFL_2_13 WOLFSSL_MFL_2_13 /**/ +#define CYASSL_EVP_PKEY WOLFSSL_EVP_PKEY +#define CYASSL_X509_CRL WOLFSSL_X509_CRL +#define CYASSL_ASN1_TIME WOLFSSL_ASN1_TIME +#define CYASSL_BIO_METHOD WOLFSSL_BIO_METHOD +#define CYASSL_X509_STORE WOLFSSL_X509_STORE +#define CYASSL_X509_OBJECT WOLFSSL_X509_OBJECT +#define CYASSL_X509_LOOKUP WOLFSSL_X509_LOOKUP +#define CYASSL_ASN1_OBJECT WOLFSSL_ASN1_OBJECT +#define CYASSL_ASN1_STRING WOLFSSL_ASN1_STRING +#define CYASSL_COMP_METHOD WOLFSSL_COMP_METHOD +#define CYASSL_CRL_CHECKALL WOLFSSL_CRL_CHECKALL +#define CYASSL_ASN1_INTEGER WOLFSSL_ASN1_INTEGER +#define CYASSL_X509_REVOKED WOLFSSL_X509_REVOKED +#define CYASSL_dynlock_value WOLFSSL_dynlock_value +#define CYASSL_X509_EXTENSION WOLFSSL_X509_EXTENSION +#define CYASSL_X509_STORE_CTX WOLFSSL_X509_STORE_CTX +#define CYASSL_X509_LOOKUP_METHOD WOLFSSL_X509_LOOKUP_METHOD + +#define CyaSSL_LoadCRL wolfSSL_LoadCRL +#define CyaSSL_EnableCRL wolfSSL_EnableCRL +#define CyaSSL_SetCRL_Cb wolfSSL_SetCRL_Cb + +/* cyassl/test.h */ +#ifdef CyaSSL_TEST_H + #define CYASSL_THREAD WOLFSSL_THREAD +#endif + +/* src/ssl.c */ +#define CYASSL_CRL WOLFSSL_CRL +#define CYASSL_SSLV3 WOLFSSL_SSLV3 +#define CYASSL_TLSV1 WOLFSSL_TLSV1 +#define CYASSL_TLSV1_1 WOLFSSL_TLSV1_1 +#define CYASSL_TLSV1_2 WOLFSSL_TLSV1_2 +#define CYASSL_USER_CA WOLFSSL_USER_CA +#define CYASSL_CLIENT_END WOLFSSL_CLIENT_END +#define CYASSL_CERT_MANAGER WOLFSSL_CERT_MANAGER +#define MAX_CYASSL_FILE_SIZE MAX_WOLFSSL_FILE_SIZE + +#define CyaSSL_get_cipher wolfSSL_get_cipher +#define CyaSSL_get_ciphers wolfSSL_get_ciphers +#define CyaSSL_KeyPemToDer wolfSSL_KeyPemToDer +#define CyaSSL_get_version wolfSSL_get_version +#define CyaSSL_SetServerID wolfSSL_SetServerID +#define CyaSSL_use_old_poly wolfSSL_use_old_poly +#define CyaSSL_SetCertCbCtx wolfSSL_SetCertCbCtx +#define CyaSSL_CertPemToDer wolfSSL_CertPemToDer +#define CyaSSL_get_shutdown wolfSSL_get_shutdown +#define CyaSSL_SetMinVersion wolfSSL_SetMinVersion +#define CyaSSL_CTX_UnloadCAs wolfSSL_CTX_UnloadCAs +#define CyaSSL_session_reused wolfSSL_session_reused +#define CyaSSL_UnloadCertsKeys wolfSSL_UnloadCertsKeys +#define CyaSSL_CIPHER_get_name wolfSSL_CIPHER_get_name +#define CyaSSL_is_init_finished wolfSSL_is_init_finished +#define CyaSSL_get_alert_history wolfSSL_get_alert_history +#define CyaSSL_get_current_cipher wolfSSL_get_current_cipher +#define CyaSSL_CertManagerUnloadCAs wolfSSL_CertManagerUnloadCAs +#define CyaSSL_CertManagerEnableOCSP wolfSSL_CertManagerEnableOCSP +#define CyaSSL_CTX_check_private_key wolfSSL_CTX_check_private_key +#define CyaSSL_CertManagerDisableOCSP wolfSSL_CertManagerDisableOCSP +#define CyaSSL_get_current_cipher_suite wolfSSL_get_current_cipher_suite +#define CyaSSL_CTX_load_verify_locations wolfSSL_CTX_load_verify_locations +#define CyaSSL_CTX_set_default_passwd_cb wolfSSL_CTX_set_default_passwd_cb + +#define CyaSSL_save_session_cache wolfSSL_save_session_cache +#define CyaSSL_restore_session_cache wolfSSL_restore_session_cache +#define CyaSSL_memsave_session_cache wolfSSL_memsave_session_cache +#define CyaSSL_memrestore_session_cache wolfSSL_memrestore_session_cache +#define CyaSSL_get_session_cache_memsize wolfSSL_get_session_cache_memsize + +/* certificate cache persistence, uses ctx since certs are per ctx */ +#define CyaSSL_CTX_save_cert_cache wolfSSL_CTX_save_cert_cache +#define CyaSSL_CTX_restore_cert_cache wolfSSL_CTX_restore_cert_cache +#define CyaSSL_CTX_memsave_cert_cache wolfSSL_CTX_memsave_cert_cache +#define CyaSSL_CTX_memrestore_cert_cache wolfSSL_CTX_memrestore_cert_cache +#define CyaSSL_CTX_get_cert_cache_memsize wolfSSL_CTX_get_cert_cache_memsize + +/* wolfSSL extensions */ +/* get wolfSSL peer X509_CHAIN */ +#define CyaSSL_get_chain_count wolfSSL_get_chain_count +/* index cert length */ +#define CyaSSL_get_chain_length wolfSSL_get_chain_length +/* index cert in X509 */ +#define CyaSSL_get_chain_X509 wolfSSL_get_chain_X509 +/* free X509 */ +#define CyaSSL_FreeX509 wolfSSL_FreeX509 +/* get index cert in PEM */ +#define CyaSSL_X509_get_subjectCN wolfSSL_X509_get_subjectCN +#define CyaSSL_X509_get_der wolfSSL_X509_get_der +#define CyaSSL_X509_notBefore wolfSSL_X509_notBefore +#define CyaSSL_X509_notAfter wolfSSL_X509_notAfter +#define CyaSSL_X509_version wolfSSL_X509_version + +#define CyaSSL_cmp_peer_cert_to_file wolfSSL_cmp_peer_cert_to_file + +#define CyaSSL_X509_get_next_altname wolfSSL_X509_get_next_altname + +#define CyaSSL_X509_d2i wolfSSL_X509_d2i +#ifndef NO_FILESYSTEM + #ifndef NO_STDIO_FILESYSTEM + #define CyaSSL_X509_d2i_fp wolfSSL_X509_d2i_fp + #endif +#define CyaSSL_X509_load_certificate_file wolfSSL_X509_load_certificate_file +#endif + +#ifdef WOLFSSL_SEP +#define CyaSSL_X509_get_device_type wolfSSL_X509_get_device_type +#define CyaSSL_X509_get_hw_type wolfSSL_X509_get_hw_type +#define CyaSSL_X509_get_hw_serial_number wolfSSL_X509_get_hw_serial_number +#endif + +#define CyaSSL_CTX_SetGenCookie wolfSSL_CTX_SetGenCookie +#define CyaSSL_SetCookieCtx wolfSSL_SetCookieCtx +#define CyaSSL_GetCookieCtx wolfSSL_GetCookieCtx +#define CyaSSL_ERR_get_error_line_data wolfSSL_ERR_get_error_line_data +#define CyaSSL_ERR_get_error wolfSSL_ERR_get_error +#define CyaSSL_ERR_clear_error wolfSSL_ERR_clear_error +#define CyaSSL_RAND_status wolfSSL_RAND_status +#define CyaSSL_RAND_bytes wolfSSL_RAND_bytes +#define CyaSSL_CTX_set_options wolfSSL_CTX_set_options +#define CyaSSL_ERR_free_strings wolfSSL_ERR_free_strings +#define CyaSSL_ERR_remove_state wolfSSL_ERR_remove_state +#define CyaSSL_EVP_cleanup wolfSSL_EVP_cleanup +#define CyaSSL_cleanup_all_ex_data wolfSSL_cleanup_all_ex_data +#define CyaSSL_CTX_set_mode wolfSSL_CTX_set_mode +#define CyaSSL_CTX_get_mode wolfSSL_CTX_get_mode +#define CyaSSL_CTX_set_default_read_ahead wolfSSL_CTX_set_default_read_ahead +#define CyaSSL_CTX_sess_set_cache_size wolfSSL_CTX_sess_set_cache_size +#define CyaSSL_CTX_set_default_verify_paths wolfSSL_CTX_set_default_verify_paths +#define CyaSSL_CTX_set_session_id_context wolfSSL_CTX_set_session_id_context +#define CyaSSL_get_peer_certificate wolfSSL_get_peer_certificate +#define CyaSSL_BIO_printf wolfSSL_BIO_printf +#define CyaSSL_ASN1_UTCTIME_print wolfSSL_ASN1_UTCTIME_print +#define CyaSSL_sk_num wolfSSL_sk_num +#define CyaSSL_sk_value wolfSSL_sk_value + +/* stunnel 4.28 needs */ +#define CyaSSL_CTX_get_ex_data wolfSSL_CTX_get_ex_data +#define CyaSSL_CTX_set_ex_data wolfSSL_CTX_set_ex_data +#define CyaSSL_CTX_sess_set_get_cb wolfSSL_CTX_sess_set_get_cb +#define CyaSSL_CTX_sess_set_new_cb wolfSSL_CTX_sess_set_new_cb +#define CyaSSL_CTX_sess_set_remove_cb wolfSSL_CTX_sess_set_remove_cb + +#define CyaSSL_i2d_SSL_SESSION wolfSSL_i2d_SSL_SESSION +#define CyaSSL_d2i_SSL_SESSION wolfSSL_d2i_SSL_SESSION + +#define CyaSSL_SESSION_get_timeout wolfSSL_SESSION_get_timeout +#define CyaSSL_SESSION_get_time wolfSSL_SESSION_get_time +#define CyaSSL_CTX_get_ex_new_index wolfSSL_CTX_get_ex_new_index + + +/* io.c */ +#define CYASSL_CBIO_ERR_ISR WOLFSSL_CBIO_ERR_ISR +#define CYASSL_CBIO_ERR_TIMEOUT WOLFSSL_CBIO_ERR_TIMEOUT +#define CYASSL_CBIO_ERR_GENERAL WOLFSSL_CBIO_ERR_GENERAL +#define CYASSL_CBIO_ERR_CONN_RST WOLFSSL_CBIO_ERR_CONN_RST +#define CYASSL_CBIO_ERR_WANT_READ WOLFSSL_CBIO_ERR_WANT_READ +#define CYASSL_CBIO_ERR_WANT_WRITE WOLFSSL_CBIO_ERR_WANT_WRITE +#define CYASSL_CBIO_ERR_CONN_CLOSE WOLFSSL_CBIO_ERR_CONN_CLOSE + +#define CyaSSL_GetIOReadCtx wolfSSL_GetIOReadCtx +#define CyaSSL_GetIOWriteCtx wolfSSL_GetIOWriteCtx + +/* src/tls.c */ +#define CYASSL_SERVER_END WOLFSSL_SERVER_END +#define CYASSL_TLS_HMAC_INNER_SZ WOLFSSL_TLS_HMAC_INNER_SZ + +#define CyaSSL_DeriveTlsKeys wolfSSL_DeriveTlsKeys +#define CyaSSL_make_eap_keys wolfSSL_make_eap_keys +#define CyaSSL_MakeTlsMasterSecret wolfSSL_MakeTlsMasterSecret + +/* src/internal.c */ +#define CYASSL_CHAIN_CA WOLFSSL_CHAIN_CA +#define CYASSL_ALERT_HISTORY WOLFSSL_ALERT_HISTORY +#define CYASSL_SESSION_TIMEOUT WOLFSSL_SESSION_TIMEOUT +#define CYASSL_CBIO_ERR_CONN_RST WOLFSSL_CBIO_ERR_CONN_RST + +#define cyassl_rc4 wolfssl_rc4 +#define cyassl_aes wolfssl_aes +#define cyassl_chacha wolfssl_chacha +#define CyaSSL_ERR_reason_error_string wolfSSL_ERR_reason_error_string + +#define CyaSSL_set_ex_data wolfSSL_set_ex_data +#define CyaSSL_get_shutdown wolfSSL_get_shutdown +#define CyaSSL_set_rfd wolfSSL_set_rfd +#define CyaSSL_set_wfd wolfSSL_set_wfd +#define CyaSSL_set_shutdown wolfSSL_set_shutdown +#define CyaSSL_set_session_id_context wolfSSL_set_session_id_context +#define CyaSSL_set_connect_state wolfSSL_set_connect_state +#define CyaSSL_set_accept_state wolfSSL_set_accept_state +#define CyaSSL_session_reused wolfSSL_session_reused +#define CyaSSL_SESSION_free wolfSSL_SESSION_free +#define CyaSSL_is_init_finished wolfSSL_is_init_finished + +#define CyaSSL_get_version wolfSSL_get_version +#define CyaSSL_get_current_cipher_suite wolfSSL_get_current_cipher_suite +#define CyaSSL_get_current_cipher wolfSSL_get_current_cipher +#define CyaSSL_CIPHER_description wolfSSL_CIPHER_description +#define CyaSSL_CIPHER_get_name wolfSSL_CIPHER_get_name +#define CyaSSL_get_cipher wolfSSL_get_cipher +#define CyaSSL_get1_session wolfSSL_get1_session + +#define CyaSSL_X509_free wolfSSL_X509_free +#define CyaSSL_OPENSSL_free wolfSSL_OPENSSL_free +#define CyaSSL_OCSP_parse_url wolfSSL_OCSP_parse_url + +#define CyaSSLv23_client_method wolfSSLv23_client_method +#define CyaSSLv2_client_method wolfSSLv2_client_method +#define CyaSSLv2_server_method wolfSSLv2_server_method + +#define CyaSSL_MD4_Init wolfSSL_MD4_Init +#define CyaSSL_MD4_Update wolfSSL_MD4_Update +#define CyaSSL_MD4_Final wolfSSL_MD4_Final + + +#define CyaSSL_BIO_new wolfSSL_BIO_new +#define CyaSSL_BIO_free wolfSSL_BIO_free +#define CyaSSL_BIO_free_all wolfSSL_BIO_free_all +#define CyaSSL_BIO_read wolfSSL_BIO_read +#define CyaSSL_BIO_write wolfSSL_BIO_write +#define CyaSSL_BIO_push wolfSSL_BIO_push +#define CyaSSL_BIO_pop wolfSSL_BIO_pop +#define CyaSSL_BIO_flush wolfSSL_BIO_flush +#define CyaSSL_BIO_pending wolfSSL_BIO_pending + +#define CyaSSL_BIO_f_buffer wolfSSL_BIO_f_buffer +#define CyaSSL_BIO_set_write_buffer_size wolfSSL_BIO_set_write_buffer_size +#define CyaSSL_BIO_f_ssl wolfSSL_BIO_f_ssl +#define CyaSSL_BIO_new_socket wolfSSL_BIO_new_socket +#define CyaSSL_BIO_eof wolfSSL_BIO_eof + +#define CyaSSL_BIO_s_mem wolfSSL_BIO_s_mem +#define CyaSSL_BIO_f_base64 wolfSSL_BIO_f_base64 +#define CyaSSL_BIO_set_flags wolfSSL_BIO_set_flags +#define CyaSSL_BIO_get_mem_data wolfSSL_BIO_get_mem_data +#define CyaSSL_BIO_new_mem_buf wolfSSL_BIO_new_mem_buf + + +#define CyaSSL_BIO_set_ssl wolfSSL_BIO_set_ssl +#define CyaSSL_set_bio wolfSSL_set_bio + +#define CyaSSL_add_all_algorithms wolfSSL_add_all_algorithms +#define CyaSSL_RAND_screen wolfSSL_RAND_screen +#define CyaSSL_RAND_file_name wolfSSL_RAND_file_name +#define CyaSSL_RAND_write_file wolfSSL_RAND_write_file +#define CyaSSL_RAND_load_file wolfSSL_RAND_load_file +#define CyaSSL_RAND_egd wolfSSL_RAND_egd +#define CyaSSL_RAND_seed wolfSSL_RAND_seed +#define CyaSSL_RAND_add wolfSSL_RAND_add + +#define CyaSSL_COMP_zlib wolfSSL_COMP_zlib +#define CyaSSL_COMP_rle wolfSSL_COMP_rle +#define CyaSSL_COMP_add_compression_method wolfSSL_COMP_add_compression_method +#define CyaSSL_set_dynlock_create_callback wolfSSL_set_dynlock_create_callback +#define CyaSSL_set_dynlock_lock_callback wolfSSL_set_dynlock_lock_callback +#define CyaSSL_set_dynlock_destroy_callback wolfSSL_set_dynlock_destroy_callback +#define CyaSSL_get_ex_new_index wolfSSL_get_ex_new_index +#define CyaSSL_set_id_callback wolfSSL_set_id_callback +#define CyaSSL_set_locking_callback wolfSSL_set_locking_callback +#define CyaSSL_num_locks wolfSSL_num_locks + +#define CyaSSL_X509_STORE_CTX_get_current_cert wolfSSL_X509_STORE_CTX_get_current_cert +#define CyaSSL_X509_STORE_CTX_get_error wolfSSL_X509_STORE_CTX_get_error +#define CyaSSL_X509_STORE_CTX_get_error_depth wolfSSL_X509_STORE_CTX_get_error_depth + +#define CyaSSL_X509_NAME_oneline wolfSSL_X509_NAME_oneline +#define CyaSSL_X509_get_issuer_name wolfSSL_X509_get_issuer_name +#define CyaSSL_X509_get_subject_name wolfSSL_X509_get_subject_name +#define CyaSSL_X509_ext_isSet_by_NID wolfSSL_X509_ext_isSet_by_NID +#define CyaSSL_X509_ext_get_critical_by_NID wolfSSL_X509_ext_get_critical_by_NID +#define CyaSSL_X509_get_isCA wolfSSL_X509_get_isCA +#define CyaSSL_X509_get_isSet_pathLength wolfSSL_X509_get_isSet_pathLength +#define CyaSSL_X509_get_pathLength wolfSSL_X509_get_pathLength +#define CyaSSL_X509_get_keyUsage wolfSSL_X509_get_keyUsage +#define CyaSSL_X509_get_authorityKeyID wolfSSL_X509_get_authorityKeyID +#define CyaSSL_X509_get_subjectKeyID wolfSSL_X509_get_subjectKeyID +#define CyaSSL_X509_NAME_entry_count wolfSSL_X509_NAME_entry_count +#define CyaSSL_X509_NAME_get_text_by_NID wolfSSL_X509_NAME_get_text_by_NID +#define CyaSSL_X509_verify_cert wolfSSL_X509_verify_cert +#define CyaSSL_X509_verify_cert_error_string wolfSSL_X509_verify_cert_error_string +#define CyaSSL_X509_get_signature_type wolfSSL_X509_get_signature_type +#define CyaSSL_X509_get_signature wolfSSL_X509_get_signature + +#define CyaSSL_X509_LOOKUP_add_dir wolfSSL_X509_LOOKUP_add_dir +#define CyaSSL_X509_LOOKUP_load_file wolfSSL_X509_LOOKUP_load_file +#define CyaSSL_X509_LOOKUP_hash_dir wolfSSL_X509_LOOKUP_hash_dir +#define CyaSSL_X509_LOOKUP_file wolfSSL_X509_LOOKUP_file + +#define CyaSSL_X509_STORE_add_lookup wolfSSL_X509_STORE_add_lookup +#define CyaSSL_X509_STORE_new wolfSSL_X509_STORE_new +#define CyaSSL_X509_STORE_free wolfSSL_X509_STORE_free +#define CyaSSL_X509_STORE_add_cert wolfSSL_X509_STORE_add_cert +#define CyaSSL_X509_STORE_set_default_paths wolfSSL_X509_STORE_set_default_paths +#define CyaSSL_X509_STORE_get_by_subject wolfSSL_X509_STORE_get_by_subject +#define CyaSSL_X509_STORE_CTX_new wolfSSL_X509_STORE_CTX_new +#define CyaSSL_X509_STORE_CTX_init wolfSSL_X509_STORE_CTX_init +#define CyaSSL_X509_STORE_CTX_free wolfSSL_X509_STORE_CTX_free +#define CyaSSL_X509_STORE_CTX_cleanup wolfSSL_X509_STORE_CTX_cleanup + +#define CyaSSL_X509_CRL_get_lastUpdate wolfSSL_X509_CRL_get_lastUpdate +#define CyaSSL_X509_CRL_get_nextUpdate wolfSSL_X509_CRL_get_nextUpdate + +#define CyaSSL_X509_get_pubkey wolfSSL_X509_get_pubkey +#define CyaSSL_X509_CRL_verify wolfSSL_X509_CRL_verify +#define CyaSSL_X509_STORE_CTX_set_error wolfSSL_X509_STORE_CTX_set_error +#define CyaSSL_X509_OBJECT_free_contents wolfSSL_X509_OBJECT_free_contents +#define CyaSSL_EVP_PKEY_free wolfSSL_EVP_PKEY_free +#define CyaSSL_X509_cmp_current_time wolfSSL_X509_cmp_current_time +#define CyaSSL_sk_X509_REVOKED_num wolfSSL_sk_X509_REVOKED_num + +#define CyaSSL_X509_CRL_get_REVOKED wolfSSL_X509_CRL_get_REVOKED +#define CyaSSL_sk_X509_REVOKED_value wolfSSL_sk_X509_REVOKED_value +#define CyaSSL_X509_get_serialNumber wolfSSL_X509_get_serialNumber +#define CyaSSL_ASN1_TIME_print wolfSSL_ASN1_TIME_print +#define CyaSSL_ASN1_INTEGER_cmp wolfSSL_ASN1_INTEGER_cmp +#define CyaSSL_ASN1_INTEGER_get wolfSSL_ASN1_INTEGER_get +#define CyaSSL_load_client_CA_file wolfSSL_load_client_CA_file +#define CyaSSL_CTX_set_client_CA_list wolfSSL_CTX_set_client_CA_list +#define CyaSSL_X509_STORE_CTX_get_ex_data wolfSSL_X509_STORE_CTX_get_ex_data +#define CyaSSL_get_ex_data_X509_STORE_CTX_idx wolfSSL_get_ex_data_X509_STORE_CTX_idx +#define CyaSSL_get_ex_data wolfSSL_get_ex_data + +#define CyaSSL_CTX_set_default_passwd_cb_userdata wolfSSL_CTX_set_default_passwd_cb_userdata +#define CyaSSL_CTX_set_default_passwd_cb wolfSSL_CTX_set_default_passwd_cb +#define CyaSSL_CTX_set_info_callback wolfSSL_CTX_set_info_callback +#define CyaSSL_ERR_peek_error wolfSSL_ERR_peek_error +#define CyaSSL_GET_REASON wolfSSL_GET_REASON +#define CyaSSL_alert_type_string_long wolfSSL_alert_type_string_long +#define CyaSSL_alert_desc_string_long wolfSSL_alert_desc_string_long +#define CyaSSL_state_string_long wolfSSL_state_string_long + +#define CyaSSL_RSA_generate_key wolfSSL_RSA_generate_key +#define CyaSSL_CTX_set_tmp_rsa_callback wolfSSL_CTX_set_tmp_rsa_callback +#define CyaSSL_PEM_def_callback wolfSSL_PEM_def_callback +#define CyaSSL_CTX_sess_accept wolfSSL_CTX_sess_accept +#define CyaSSL_CTX_sess_connect wolfSSL_CTX_sess_connect +#define CyaSSL_CTX_sess_accept_good wolfSSL_CTX_sess_accept_good +#define CyaSSL_CTX_sess_connect_good wolfSSL_CTX_sess_connect_good +#define CyaSSL_CTX_sess_accept_renegotiate wolfSSL_CTX_sess_accept_renegotiate +#define CyaSSL_CTX_sess_connect_renegotiate wolfSSL_CTX_sess_connect_renegotiate +#define CyaSSL_CTX_sess_hits wolfSSL_CTX_sess_hits +#define CyaSSL_CTX_sess_cb_hits wolfSSL_CTX_sess_cb_hits +#define CyaSSL_CTX_sess_cache_full wolfSSL_CTX_sess_cache_full +#define CyaSSL_CTX_sess_misses wolfSSL_CTX_sess_misses +#define CyaSSL_CTX_sess_timeouts wolfSSL_CTX_sess_timeouts +#define CyaSSL_CTX_sess_number wolfSSL_CTX_sess_number +#define CyaSSL_CTX_sess_get_cache_size wolfSSL_CTX_sess_get_cache_size + + + +/* src/keys.c */ +#define cyassl_triple_des wolfssl_triple_des + +/* Initialization and Shutdown */ +#define CyaSSL_Init wolfSSL_Init +#define CyaSSL_library_init wolfSSL_library_init +#define CyaSSL_Cleanup wolfSSL_Cleanup +#define CyaSSL_shutdown wolfSSL_shutdown + +/* Certs and keys */ +#define CyaSSL_SetTmpDH wolfSSL_SetTmpDH +#define CyaSSL_KeepArrays wolfSSL_KeepArrays +#define CyaSSL_FreeArrays wolfSSL_FreeArrays +#define CyaSSL_SetTmpDH_file wolfSSL_SetTmpDH_file +#define CyaSSL_use_PrivateKey_buffer wolfSSL_use_PrivateKey_buffer +#define CyaSSL_use_certificate_buffer wolfSSL_use_certificate_buffer +#define CyaSSL_CTX_load_verify_buffer wolfSSL_CTX_load_verify_buffer +#define CyaSSL_CTX_use_PrivateKey_file wolfSSL_CTX_use_PrivateKey_file +#define CyaSSL_CTX_use_certificate_file wolfSSL_CTX_use_certificate_file +#define CyaSSL_CTX_use_PrivateKey_buffer wolfSSL_CTX_use_PrivateKey_buffer +#define CyaSSL_CTX_use_PrivateKey_buffer wolfSSL_CTX_use_PrivateKey_buffer +#define CyaSSL_CTX_use_certificate_buffer wolfSSL_CTX_use_certificate_buffer +#define CyaSSL_CTX_use_NTRUPrivateKey_file wolfSSL_CTX_use_NTRUPrivateKey_file +#define CyaSSL_use_certificate_chain_buffer wolfSSL_use_certificate_chain_buffer +#define CyaSSL_CTX_der_load_verify_locations \ + wolfSSL_CTX_der_load_verify_locations +#define CyaSSL_CTX_use_certificate_chain_file \ + wolfSSL_CTX_use_certificate_chain_file +#define CyaSSL_CTX_use_certificate_chain_buffer \ + wolfSSL_CTX_use_certificate_chain_buffer + +/* Context and Session Setup*/ +#define CyaSSL_new wolfSSL_new +#define CyaSSL_free wolfSSL_free +#define CyaSSL_set_fd wolfSSL_set_fd +#define CyaSSL_CTX_new wolfSSL_CTX_new +#define CyaSSL_CTX_free wolfSSL_CTX_free +#define CyaSSL_SetVersion wolfSSL_SetVersion +#define CyaSSL_set_verify wolfSSL_set_verify +#define CyaSSL_set_session wolfSSL_set_session +#define CyaSSL_set_timeout wolfSSL_set_timeout +#define CyaSSL_CTX_set_verify wolfSSL_CTX_set_verify +#define CyaSSL_CTX_set_timeout wolfSSL_CTX_set_timeout +#define CyaSSL_set_cipher_list wolfSSL_set_cipher_list +#define CyaSSL_set_compression wolfSSL_set_compression +#define CyaTLSv1_client_method wolfTLSv1_client_method +#define CyaTLSv1_server_method wolfTLSv1_server_method +#define CyaSSLv3_client_method wolfSSLv3_client_method +#define CyaSSLv3_server_method wolfSSLv3_server_method +#define CyaSSLv23_client_method wolfSSLv23_client_method +#define CyaSSLv23_server_method wolfSSLv23_server_method +#define CyaDTLSv1_client_method wolfDTLSv1_client_method +#define CyaDTLSv1_server_method wolfDTLSv1_server_method +#define CyaSSL_check_domain_name wolfSSL_check_domain_name +#define CyaTLSv1_1_client_method wolfTLSv1_1_client_method +#define CyaTLSv1_1_server_method wolfTLSv1_1_server_method +#define CyaTLSv1_2_client_method wolfTLSv1_2_client_method +#define CyaTLSv1_2_server_method wolfTLSv1_2_server_method +#define CyaDTLSv1_2_client_method wolfDTLSv1_2_client_method +#define CyaDTLSv1_2_server_method wolfDTLSv1_2_server_method +#define CyaSSL_set_group_messages wolfSSL_set_group_messages +#define CyaSSL_set_using_nonblock wolfSSL_set_using_nonblock +#define CyaSSL_CTX_set_cipher_list wolfSSL_CTX_set_cipher_list +#define CyaSSL_CTX_set_group_messages wolfSSL_CTX_set_group_messages +#define CyaSSL_CTX_set_session_cache_mode wolfSSL_CTX_set_session_cache_mode + +/* Callbacks */ + +/* + * Empty commment denotes not listed in CyaSSL Manual + * (soon to be wolfSSL Manual) + */ + +#define CyaSSL_accept_ex wolfSSL_accept_ex +#define CyaSSL_SetIORecv wolfSSL_SetIORecv +#define CyaSSL_SetIOSend wolfSSL_SetIOSend +#define CyaSSL_connect_ex wolfSSL_connect_ex +#define CyaSSL_CTX_SetCACb wolfSSL_CTX_SetCACb +#define CyaSSL_SetIOReadCtx wolfSSL_SetIOReadCtx +#define CyaSSL_SetRsaEncCtx wolfSSL_SetRsaEncCtx +#define CyaSSL_GetRsaEncCtx wolfSSL_GetRsaEncCtx +#define CyaSSL_SetRsaDecCtx wolfSSL_SetRsaDecCtx +#define CyaSSL_GetRsaDecCtx wolfSSL_GetRsaDecCtx +#define CyaSSL_SetLoggingCb wolfSSL_SetLoggingCb +#define CyaSSL_SetEccSignCtx wolfSSL_SetEccSignCtx +#define CyaSSL_GetEccSignCtx wolfSSL_GetEccSignCtx +#define CyaSSL_SetRsaSignCtx wolfSSL_SetRsaSignCtx +#define CyaSSL_GetRsaSignCtx wolfSSL_GetRsaSignCtx +#define CyaSSL_SetIOWriteCtx wolfSSL_SetIOWriteCtx +#define CyaSSL_SetIOReadFlags wolfSSL_SetIOReadFlags +#define CyaSSL_SetEccVerifyCtx wolfSSL_SetEccVerifyCtx +#define CyaSSL_GetEccVerifyCtx wolfSSL_GetEccVerifyCtx +#define CyaSSL_SetRsaVerifyCtx wolfSSL_SetRsaVerifyCtx +#define CyaSSL_GetRsaVerifyCtx wolfSSL_GetRsaVerifyCtx +#define CyaSSL_CTX_SetRsaEncCb wolfSSL_CTX_SetRsaEncCb +#define CyaSSL_CTX_SetRsaDecCb wolfSSL_CTX_SetRsaDecCb +#define CyaSSL_SetIOWriteFlags wolfSSL_SetIOWriteFlags +#define CyaSSL_SetTlsHmacInner wolfSSL_SetTlsHmacInner +#define CyaSSL_SetMacEncryptCtx wolfSSL_SetMacEncryptCtx +#define CyaSSL_GetMacEncryptCtx wolfSSL_GetMacEncryptCtx +#define CyaSSL_CTX_SetEccSignCb wolfSSL_CTX_SetEccSignCb +#define CyaSSL_CTX_SetRsaSignCb wolfSSL_CTX_SetRsaSignCb +#define CyaSSL_CTX_SetEccVerifyCb wolfSSL_CTX_SetEccVerifyCb +#define CyaSSL_CTX_SetRsaVerifyCb wolfSSL_CTX_SetRsaVerifyCb +#define CyaSSL_CTX_SetMacEncryptCb wolfSSL_CTX_SetMacEncryptCb +#define CyaSSL_SetDecryptVerifyCtx wolfSSL_SetDecryptVerifyCtx +#define CyaSSL_GetDecryptVerifyCtx wolfSSL_GetDecryptVerifyCtx +#define CyaSSL_CTX_SetDecryptVerifyCb wolfSSL_CTX_SetDecryptVerifyCb + +/* psk specific */ +#ifndef NO_PSK + +#define CyaSSL_get_psk_identity wolfSSL_get_psk_identity /**/ +#define CyaSSL_get_psk_identity_hint wolfSSL_get_psk_identity_hint /**/ +#define CyaSSL_use_psk_identity_hint wolfSSL_use_psk_identity_hint /**/ +#define CyaSSL_set_psk_client_callback wolfSSL_set_psk_client_callback /**/ +#define CyaSSL_set_psk_server_callback wolfSSL_set_psk_server_callback /**/ +#define CyaSSL_CTX_use_psk_identity_hint wolfSSL_CTX_use_psk_identity_hint /**/ +#define CyaSSL_CTX_set_psk_client_callback \ + wolfSSL_CTX_set_psk_client_callback /**/ +#define CyaSSL_CTX_set_psk_server_callback \ + wolfSSL_CTX_set_psk_server_callback /**/ + +#endif +/* end psk specific */ + +/* Anonymous */ +#define CyaSSL_CTX_allow_anon_cipher wolfSSL_CTX_allow_anon_cipher /**/ + +/* Error Handling and Debugging*/ +#define CyaSSL_get_error wolfSSL_get_error +#define CyaSSL_want_read wolfSSL_want_read +#define CyaSSL_want_write wolfSSL_want_write +#define CyaSSL_Debugging_ON wolfSSL_Debugging_ON +#define CyaSSL_Debugging_OFF wolfSSL_Debugging_OFF +#define CyaSSL_ERR_error_string wolfSSL_ERR_error_string +#define CyaSSL_load_error_strings wolfSSL_load_error_strings +#define CyaSSL_ERR_error_string_n wolfSSL_ERR_error_string_n +#define CyaSSL_ERR_print_errors_fp wolfSSL_ERR_print_errors_fp + +/* OCSP and CRL */ + +/* + * Empty commment denotes not listed in CyaSSL Manual + * (soon to be wolfSSL Manual) + */ + +#define CYASSL_CRL_MONITOR WOLFSSL_CRL_MONITOR /**/ +#define CYASSL_CRL_START_MON WOLFSSL_CRL_START_MON /**/ +#define CYASSL_OCSP_NO_NONCE WOLFSSL_OCSP_NO_NONCE /**/ +#define CYASSL_OCSP_URL_OVERRIDE WOLFSSL_OCSP_URL_OVERRIDE +#define CYASSL_OCSP_CHECKALL WOLFSSL_OCSP_CHECKALL + +#define CyaSSL_CTX_EnableOCSP wolfSSL_CTX_EnableOCSP +#define CyaSSL_CTX_OCSP_set_options wolfSSL_CTX_OCSP_set_options /**/ +#define CyaSSL_CTX_SetOCSP_OverrideURL wolfSSL_CTX_SetOCSP_OverrideURL /**/ +#define CyaSSL_CTX_OCSP_set_override_url wolfSSL_CTX_OCSP_set_override_url /**/ + +/* Informational */ +#define CyaSSL_GetSide wolfSSL_GetSide +#define CyaSSL_IsTLSv1_1 wolfSSL_IsTLSv1_1 +#define CyaSSL_GetKeySize wolfSSL_GetKeySize +#define CyaSSL_GetHmacSize wolfSSL_GetHmacSize +#define CyaSSL_GetHmacType wolfSSL_GetHmacType +#define CyaSSL_GetMacSecret wolfSSL_GetMacSecret +#define CyaSSL_GetObjectSize wolfSSL_GetObjectSize +#define CyaSSL_GetBulkCipher wolfSSL_GetBulkCipher +#define CyaSSL_GetCipherType wolfSSL_GetCipherType +#define CyaSSL_GetAeadMacSize wolfSSL_GetAeadMacSize +#define CyaSSL_GetClientWriteIV wolfSSL_GetClientWriteIV +#define CyaSSL_GetServerWriteIV wolfSSL_GetServerWriteIV +#define CyaSSL_GetClientWriteKey wolfSSL_GetClientWriteKey +#define CyaSSL_GetServerWriteKey wolfSSL_GetServerWriteKey +#define CyaSSL_GetCipherBlockSize wolfSSL_GetCipherBlockSize + +/* Connection, Session, and I/O */ +#define CyaSSL_peek wolfSSL_peek +#define CyaSSL_read wolfSSL_read +#define CyaSSL_recv wolfSSL_recv +#define CyaSSL_send wolfSSL_send +#define CyaSSL_write wolfSSL_write +#define CyaSSL_writev wolfSSL_writev +#define CyaSSL_accept wolfSSL_accept +#define CyaSSL_get_fd wolfSSL_get_fd +#define CyaSSL_connect wolfSSL_connect +#define CyaSSL_pending wolfSSL_pending +#define CyaSSL_negotiate wolfSSL_negotiate +#define CyaSSL_get_session wolfSSL_get_session +#define CyaSSL_connect_cert wolfSSL_connect_cert +#define CyaSSL_flush_sessions wolfSSL_flush_sessions +#define CyaSSL_get_using_nonblock wolfSSL_get_using_nonblock +#define CyaSSL_PrintSessionStats wolfSSL_PrintSessionStats + +/* DTLS Specific */ +#define CyaSSL_dtls wolfSSL_dtls +#define CyaSSL_dtls_set_peer wolfSSL_dtls_set_peer +#define CyaSSL_dtls_get_peer wolfSSL_dtls_get_peer +#define CyaSSL_dtls_got_timeout wolfSSL_dtls_got_timeout +#define CyaSSL_dtls_get_current_timeout wolfSSL_dtls_get_current_timeout + +/* Certificate Manager */ +#define CyaSSL_CertManagerNew wolfSSL_CertManagerNew +#define CyaSSL_CertManagerFree wolfSSL_CertManagerFree +#define CyaSSL_CertManagerLoadCA wolfSSL_CertManagerLoadCA +#define CyaSSL_CertManagerVerify wolfSSL_CertManagerVerify +#define CyaSSL_CertManagerEnableCRL wolfSSL_CertManagerEnableCRL +#define CyaSSL_CertManagerDisableCRL wolfSSL_CertManagerDisableCRL +#define CyaSSL_CertManagerVerifyBuffer wolfSSL_CertManagerVerifyBuffer +#ifndef NO_CERTS + #define CyaSSL_CertManagerCheckCRL wolfSSL_CertManagerCheckCRL + #define CyaSSL_CertManagerLoadCRL wolfSSL_CertManagerLoadCRL + #define CyaSSL_CertManagerSetCRL_Cb wolfSSL_CertManagerSetCRL_Cb + #define CyaSSL_CertManagerCheckOCSP wolfSSL_CertManagerCheckOCSP + #define CyaSSL_CertManagerSetOCSP_Cb wolfSSL_CertManagerSetOCSP_Cb + #define CyaSSL_CertManagerSetOCSPOverrideURL \ + wolfSSL_CertManagerSetOCSPOverrideURL + + #define CyaSSL_DisableCRL wolfSSL_DisableCRL + #define CyaSSL_EnableOCSP wolfSSL_EnableOCSP + #define CyaSSL_DisableOCSP wolfSSL_DisableOCSP + #define CyaSSL_SetOCSP_OverrideURL wolfSSL_SetOCSP_OverrideURL + #define CyaSSL_SetOCSP_Cb wolfSSL_SetOCSP_Cb + + #define CyaSSL_CTX_EnableCRL wolfSSL_CTX_EnableCRL + #define CyaSSL_CTX_DisableCRL wolfSSL_CTX_DisableCRL + #define CyaSSL_CTX_LoadCRL wolfSSL_CTX_LoadCRL + #define CyaSSL_CTX_SetCRL_Cb wolfSSL_CTX_SetCRL_Cb + #define CyaSSL_CTX_DisableOCSP wolfSSL_CTX_DisableOCSP + #define CyaSSL_CTX_SetOCSP_Cb wolfSSL_CTX_SetOCSP_Cb +#endif /* !NO_CERTS */ + + +/* OpenSSL Compatibility Layer */ +#define CyaSSL_PemCertToDer wolfSSL_PemCertToDer +#define CyaSSL_get_sessionID wolfSSL_get_sessionID +#define CyaSSL_get_peer_count wolfSSL_get_peer_count +#define CyaSSL_get_chain_cert wolfSSL_get_chain_cert +#define CyaSSL_get_peer_chain wolfSSL_get_peer_chain +#define CyaSSL_get_peer_length wolfSSL_get_peer_length +#define CyaSSL_get_chain_cert_pem wolfSSL_get_chain_cert_pem +#define CyaSSL_use_PrivateKey_file wolfSSL_use_PrivateKey_file +#define CyaSSL_use_certificate_file wolfSSL_use_certificate_file +#define CyaSSL_use_RSAPrivateKey_file wolfSSL_use_RSAPrivateKey_file +#define CyaSSL_X509_get_serial_number wolfSSL_X509_get_serial_number +#define CyaSSL_CTX_use_RSAPrivateKey_file wolfSSL_CTX_use_RSAPrivateKey_file +#define CyaSSL_use_certificate_chain_file wolfSSL_use_certificate_chain_file + +/* TLS Extensions */ +#define CYASSL_SNI_HOST_NAME WOLFSSL_SNI_HOST_NAME + +#define CyaSSL_UseSNI wolfSSL_UseSNI +#define CyaSSL_CTX_UseSNI wolfSSL_CTX_UseSNI +#define CyaSSL_SNI_SetOptions wolfSSL_SNI_SetOptions +#define CyaSSL_SNI_GetRequest wolfSSL_SNI_GetRequest +#define CyaSSL_UseMaxFragment wolfSSL_UseMaxFragment +#define CyaSSL_UseTruncatedHMAC wolfSSL_UseTruncatedHMAC +#define CyaSSL_UseSupportedCurve wolfSSL_UseSupportedCurve +#define CyaSSL_SNI_GetFromBuffer wolfSSL_SNI_GetFromBuffer +#define CyaSSL_CTX_SNI_SetOptions wolfSSL_CTX_SNI_SetOptions +#define CyaSSL_CTX_UseMaxFragment wolfSSL_CTX_UseMaxFragment +#define CyaSSL_CTX_UseTruncatedHMAC wolfSSL_CTX_UseTruncatedHMAC +#define CyaSSL_CTX_UseSupportedCurve wolfSSL_CTX_UseSupportedCurve + +/* End wolfssl -> cyassl -> openssl compatibility */ + +/* JRB macro redefinitions and api calls for cryptography for reverse compat. */ + +#ifdef WOLFSSL_SMALL_STACK + #define CYASSL_SMALL_STACK +#endif + + +/* + * wrapper around macros until they are changed in cyassl code + * needs investigation in regards to macros in fips + */ +#define NO_WOLFSSL_ALLOC_ALIGN NO_CYASSL_ALLOC_ALIGN /* @TODO */ + + +/* examples/client/client.h */ +#define CYASSL_THREAD WOLFSSL_THREAD +#ifdef WOLFSSL_DTLS + #define CYASSL_DTLS WOLFSSL_DTLS +#endif + +/* examples/client/client.c */ +#define LIBCYASSL_VERSION_STRING LIBWOLFSSL_VERSION_STRING + +#ifdef __cplusplus + } /* extern "C" */ +#endif + + +#endif /* CyaSSL_openssl_h__ */ diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/test.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/test.h new file mode 100644 index 0000000..428b141 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/test.h @@ -0,0 +1,3 @@ +/* test.h */ + +#include diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/version.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/version.h new file mode 100644 index 0000000..79bcc17 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/cyassl/version.h @@ -0,0 +1,26 @@ +/* cyassl/version.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#include + +#define LIBCYASSL_VERSION_STRING LIBWOLFSSL_VERSION_STRING +#define LIBCYASSL_VERSION_HEX LIBWOLFSSL_VERSION_HEX + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/doc/README.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/doc/README.txt new file mode 100644 index 0000000..e969894 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/doc/README.txt @@ -0,0 +1,3 @@ +The wolfSSL manual is available at: +http://www.wolfssl.com/documentation/wolfSSL-Manual.pdf + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/doc/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/doc/include.am new file mode 100644 index 0000000..5bef623 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/doc/include.am @@ -0,0 +1,5 @@ +# vim:ft=automake +# included from Top Level Makefile.am +# All paths should be given relative to the root + +dist_doc_DATA+= doc/README.txt diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/client/client-ntru.vcproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/client/client-ntru.vcproj new file mode 100644 index 0000000..b3eccc0 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/client/client-ntru.vcproj @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/client/client.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/client/client.c new file mode 100644 index 0000000..5838c67 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/client/client.c @@ -0,0 +1,1083 @@ +/* client.c + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#ifdef HAVE_CONFIG_H + #include +#endif + +#include + +#if defined(WOLFSSL_MDK_ARM) + #include + #include + + #if defined(WOLFSSL_MDK5) + #include "cmsis_os.h" + #include "rl_fs.h" + #include "rl_net.h" + #else + #include "rtl.h" + #endif + + #include "wolfssl_MDK_ARM.h" +#endif + +#include + +#if !defined(WOLFSSL_TRACK_MEMORY) && !defined(NO_MAIN_DRIVER) + /* in case memory tracker wants stats */ + #define WOLFSSL_TRACK_MEMORY +#endif + +#include + +#include + +#include "examples/client/client.h" + + +#ifdef WOLFSSL_CALLBACKS + int handShakeCB(HandShakeInfo*); + int timeoutCB(TimeoutInfo*); + Timeval timeout; +#endif + +#ifdef HAVE_SESSION_TICKET + int sessionTicketCB(WOLFSSL*, const unsigned char*, int, void*); +#endif + + +static void NonBlockingSSL_Connect(WOLFSSL* ssl) +{ +#ifndef WOLFSSL_CALLBACKS + int ret = wolfSSL_connect(ssl); +#else + int ret = wolfSSL_connect_ex(ssl, handShakeCB, timeoutCB, timeout); +#endif + int error = wolfSSL_get_error(ssl, 0); + SOCKET_T sockfd = (SOCKET_T)wolfSSL_get_fd(ssl); + int select_ret; + + while (ret != SSL_SUCCESS && (error == SSL_ERROR_WANT_READ || + error == SSL_ERROR_WANT_WRITE)) { + int currTimeout = 1; + + if (error == SSL_ERROR_WANT_READ) + printf("... client would read block\n"); + else + printf("... client would write block\n"); + +#ifdef WOLFSSL_DTLS + currTimeout = wolfSSL_dtls_get_current_timeout(ssl); +#endif + select_ret = tcp_select(sockfd, currTimeout); + + if ((select_ret == TEST_RECV_READY) || + (select_ret == TEST_ERROR_READY)) { + #ifndef WOLFSSL_CALLBACKS + ret = wolfSSL_connect(ssl); + #else + ret = wolfSSL_connect_ex(ssl,handShakeCB,timeoutCB,timeout); + #endif + error = wolfSSL_get_error(ssl, 0); + } + else if (select_ret == TEST_TIMEOUT && !wolfSSL_dtls(ssl)) { + error = SSL_ERROR_WANT_READ; + } +#ifdef WOLFSSL_DTLS + else if (select_ret == TEST_TIMEOUT && wolfSSL_dtls(ssl) && + wolfSSL_dtls_got_timeout(ssl) >= 0) { + error = SSL_ERROR_WANT_READ; + } +#endif + else { + error = SSL_FATAL_ERROR; + } + } + if (ret != SSL_SUCCESS) + err_sys("SSL_connect failed"); +} + + +static void Usage(void) +{ + printf("client " LIBWOLFSSL_VERSION_STRING + " NOTE: All files relative to wolfSSL home dir\n"); + printf("-? Help, print this usage\n"); + printf("-h Host to connect to, default %s\n", wolfSSLIP); + printf("-p Port to connect on, not 0, default %d\n", wolfSSLPort); + printf("-v SSL version [0-3], SSLv3(0) - TLS1.2(3)), default %d\n", + CLIENT_DEFAULT_VERSION); + printf("-l Cipher list\n"); + printf("-c Certificate file, default %s\n", cliCert); + printf("-k Key file, default %s\n", cliKey); + printf("-A Certificate Authority file, default %s\n", caCert); +#ifndef NO_DH + printf("-Z Minimum DH key bits, default %d\n", + DEFAULT_MIN_DHKEY_BITS); +#endif + printf("-b Benchmark connections and print stats\n"); + printf("-s Use pre Shared keys\n"); + printf("-t Track wolfSSL memory use\n"); + printf("-d Disable peer checks\n"); + printf("-D Override Date Errors example\n"); + printf("-g Send server HTTP GET\n"); + printf("-u Use UDP DTLS," + " add -v 2 for DTLSv1 (default), -v 3 for DTLSv1.2\n"); + printf("-m Match domain name in cert\n"); + printf("-N Use Non-blocking sockets\n"); + printf("-r Resume session\n"); + printf("-w Wait for bidirectional shutdown\n"); +#ifdef HAVE_SECURE_RENEGOTIATION + printf("-R Allow Secure Renegotiation\n"); + printf("-i Force client Initiated Secure Renegotiation\n"); +#endif + printf("-f Fewer packets/group messages\n"); + printf("-x Disable client cert/key loading\n"); + printf("-X Driven by eXternal test case\n"); +#ifdef SHOW_SIZES + printf("-z Print structure sizes\n"); +#endif +#ifdef HAVE_SNI + printf("-S Use Host Name Indication\n"); +#endif +#ifdef HAVE_MAX_FRAGMENT + printf("-L Use Maximum Fragment Length [1-5]\n"); +#endif +#ifdef HAVE_TRUNCATED_HMAC + printf("-T Use Truncated HMAC\n"); +#endif +#ifdef HAVE_OCSP + printf("-o Perform OCSP lookup on peer certificate\n"); + printf("-O Perform OCSP lookup using as responder\n"); +#endif +#ifdef ATOMIC_USER + printf("-U Atomic User Record Layer Callbacks\n"); +#endif +#ifdef HAVE_PK_CALLBACKS + printf("-P Public Key Callbacks\n"); +#endif +#ifdef HAVE_ANON + printf("-a Anonymous client\n"); +#endif +#ifdef HAVE_CRL + printf("-C Disable CRL\n"); +#endif +} + +THREAD_RETURN WOLFSSL_THREAD client_test(void* args) +{ + SOCKET_T sockfd = 0; + + WOLFSSL_METHOD* method = 0; + WOLFSSL_CTX* ctx = 0; + WOLFSSL* ssl = 0; + + WOLFSSL* sslResume = 0; + WOLFSSL_SESSION* session = 0; + char resumeMsg[] = "resuming wolfssl!"; + int resumeSz = sizeof(resumeMsg); + + char msg[32] = "hello wolfssl!"; /* GET may make bigger */ + char reply[80]; + int input; + int msgSz = (int)strlen(msg); + + word16 port = wolfSSLPort; + char* host = (char*)wolfSSLIP; + const char* domain = "www.wolfssl.com"; + + int ch; + int version = CLIENT_INVALID_VERSION; + int usePsk = 0; + int useAnon = 0; + int sendGET = 0; + int benchmark = 0; + int doDTLS = 0; + int matchName = 0; + int doPeerCheck = 1; + int nonBlocking = 0; + int resumeSession = 0; + int wc_shutdown = 0; + int disableCRL = 0; + int externalTest = 0; + int ret; + int scr = 0; /* allow secure renegotiation */ + int forceScr = 0; /* force client initiaed scr */ + int trackMemory = 0; + int useClientCert = 1; + int fewerPackets = 0; + int atomicUser = 0; + int pkCallbacks = 0; + int overrideDateErrors = 0; + int minDhKeyBits = DEFAULT_MIN_DHKEY_BITS; + char* cipherList = NULL; + const char* verifyCert = caCert; + const char* ourCert = cliCert; + const char* ourKey = cliKey; + +#ifdef HAVE_SNI + char* sniHostName = NULL; +#endif +#ifdef HAVE_MAX_FRAGMENT + byte maxFragment = 0; +#endif +#ifdef HAVE_TRUNCATED_HMAC + byte truncatedHMAC = 0; +#endif + + +#ifdef HAVE_OCSP + int useOcsp = 0; + char* ocspUrl = NULL; +#endif + + int argc = ((func_args*)args)->argc; + char** argv = ((func_args*)args)->argv; + + ((func_args*)args)->return_code = -1; /* error state */ + +#ifdef NO_RSA + verifyCert = (char*)eccCert; + ourCert = (char*)cliEccCert; + ourKey = (char*)cliEccKey; +#endif + (void)resumeSz; + (void)session; + (void)sslResume; + (void)trackMemory; + (void)atomicUser; + (void)pkCallbacks; + (void)scr; + (void)forceScr; + (void)ourKey; + (void)ourCert; + (void)verifyCert; + (void)useClientCert; + (void)overrideDateErrors; + (void)disableCRL; + (void)minDhKeyBits; + + StackTrap(); + + while ((ch = mygetopt(argc, argv, + "?gdDusmNrwRitfxXUPCh:p:v:l:A:c:k:Z:b:zS:L:ToO:a")) + != -1) { + switch (ch) { + case '?' : + Usage(); + exit(EXIT_SUCCESS); + + case 'g' : + sendGET = 1; + break; + + case 'd' : + doPeerCheck = 0; + break; + + case 'D' : + overrideDateErrors = 1; + break; + + case 'C' : + #ifdef HAVE_CRL + disableCRL = 1; + #endif + break; + + case 'u' : + doDTLS = 1; + break; + + case 's' : + usePsk = 1; + break; + + case 't' : + #ifdef USE_WOLFSSL_MEMORY + trackMemory = 1; + #endif + break; + + case 'm' : + matchName = 1; + break; + + case 'x' : + useClientCert = 0; + break; + + case 'X' : + externalTest = 1; + break; + + case 'f' : + fewerPackets = 1; + break; + + case 'U' : + #ifdef ATOMIC_USER + atomicUser = 1; + #endif + break; + + case 'P' : + #ifdef HAVE_PK_CALLBACKS + pkCallbacks = 1; + #endif + break; + + case 'h' : + host = myoptarg; + domain = myoptarg; + break; + + case 'p' : + port = (word16)atoi(myoptarg); + #if !defined(NO_MAIN_DRIVER) || defined(USE_WINDOWS_API) + if (port == 0) + err_sys("port number cannot be 0"); + #endif + break; + + case 'v' : + version = atoi(myoptarg); + if (version < 0 || version > 3) { + Usage(); + exit(MY_EX_USAGE); + } + break; + + case 'l' : + cipherList = myoptarg; + break; + + case 'A' : + verifyCert = myoptarg; + break; + + case 'c' : + ourCert = myoptarg; + break; + + case 'k' : + ourKey = myoptarg; + break; + + case 'Z' : + #ifndef NO_DH + minDhKeyBits = atoi(myoptarg); + if (minDhKeyBits <= 0 || minDhKeyBits > 16000) { + Usage(); + exit(MY_EX_USAGE); + } + #endif + break; + + case 'b' : + benchmark = atoi(myoptarg); + if (benchmark < 0 || benchmark > 1000000) { + Usage(); + exit(MY_EX_USAGE); + } + break; + + case 'N' : + nonBlocking = 1; + break; + + case 'r' : + resumeSession = 1; + break; + + case 'w' : + wc_shutdown = 1; + break; + + case 'R' : + #ifdef HAVE_SECURE_RENEGOTIATION + scr = 1; + #endif + break; + + case 'i' : + #ifdef HAVE_SECURE_RENEGOTIATION + scr = 1; + forceScr = 1; + #endif + break; + + case 'z' : + #ifndef WOLFSSL_LEANPSK + wolfSSL_GetObjectSize(); + #endif + break; + + case 'S' : + #ifdef HAVE_SNI + sniHostName = myoptarg; + #endif + break; + + case 'L' : + #ifdef HAVE_MAX_FRAGMENT + maxFragment = atoi(myoptarg); + if (maxFragment < WOLFSSL_MFL_2_9 || + maxFragment > WOLFSSL_MFL_2_13) { + Usage(); + exit(MY_EX_USAGE); + } + #endif + break; + + case 'T' : + #ifdef HAVE_TRUNCATED_HMAC + truncatedHMAC = 1; + #endif + break; + + case 'o' : + #ifdef HAVE_OCSP + useOcsp = 1; + #endif + break; + + case 'O' : + #ifdef HAVE_OCSP + useOcsp = 1; + ocspUrl = myoptarg; + #endif + break; + + case 'a' : + #ifdef HAVE_ANON + useAnon = 1; + #endif + break; + + default: + Usage(); + exit(MY_EX_USAGE); + } + } + + myoptind = 0; /* reset for test cases */ + + if (externalTest) { + /* detect build cases that wouldn't allow test against wolfssl.com */ + int done = 0; + (void)done; + + #ifdef NO_RSA + done = 1; + #endif + + #ifndef NO_PSK + done = 1; + #endif + + #ifdef NO_SHA + done = 1; /* external cert chain most likely has SHA */ + #endif + + if (done) { + printf("external test can't be run in this mode"); + + ((func_args*)args)->return_code = 0; + exit(EXIT_SUCCESS); + } + } + + /* sort out DTLS versus TLS versions */ + if (version == CLIENT_INVALID_VERSION) { + if (doDTLS) + version = CLIENT_DTLS_DEFAULT_VERSION; + else + version = CLIENT_DEFAULT_VERSION; + } + else { + if (doDTLS) { + if (version == 3) + version = -2; + else + version = -1; + } + } + +#ifdef USE_WOLFSSL_MEMORY + if (trackMemory) + InitMemoryTracker(); +#endif + + switch (version) { +#ifndef NO_OLD_TLS + case 0: + method = wolfSSLv3_client_method(); + break; + + + #ifndef NO_TLS + case 1: + method = wolfTLSv1_client_method(); + break; + + case 2: + method = wolfTLSv1_1_client_method(); + break; + #endif /* NO_TLS */ + +#endif /* NO_OLD_TLS */ + +#ifndef NO_TLS + case 3: + method = wolfTLSv1_2_client_method(); + break; +#endif + +#ifdef WOLFSSL_DTLS + #ifndef NO_OLD_TLS + case -1: + method = wolfDTLSv1_client_method(); + break; + #endif + + case -2: + method = wolfDTLSv1_2_client_method(); + break; +#endif + + default: + err_sys("Bad SSL version"); + break; + } + + if (method == NULL) + err_sys("unable to get method"); + + ctx = wolfSSL_CTX_new(method); + if (ctx == NULL) + err_sys("unable to get ctx"); + + if (cipherList) + if (wolfSSL_CTX_set_cipher_list(ctx, cipherList) != SSL_SUCCESS) + err_sys("client can't set cipher list 1"); + +#ifdef WOLFSSL_LEANPSK + usePsk = 1; +#endif + +#if defined(NO_RSA) && !defined(HAVE_ECC) + usePsk = 1; +#endif + + if (fewerPackets) + wolfSSL_CTX_set_group_messages(ctx); + +#ifndef NO_DH + wolfSSL_CTX_SetMinDhKey_Sz(ctx, (word16)minDhKeyBits); +#endif + + if (usePsk) { +#ifndef NO_PSK + wolfSSL_CTX_set_psk_client_callback(ctx, my_psk_client_cb); + if (cipherList == NULL) { + const char *defaultCipherList; + #if defined(HAVE_AESGCM) && !defined(NO_DH) + defaultCipherList = "DHE-PSK-AES128-GCM-SHA256"; + #elif defined(HAVE_NULL_CIPHER) + defaultCipherList = "PSK-NULL-SHA256"; + #else + defaultCipherList = "PSK-AES128-CBC-SHA256"; + #endif + if (wolfSSL_CTX_set_cipher_list(ctx,defaultCipherList) + !=SSL_SUCCESS) + err_sys("client can't set cipher list 2"); + } +#endif + useClientCert = 0; + } + + if (useAnon) { +#ifdef HAVE_ANON + if (cipherList == NULL) { + wolfSSL_CTX_allow_anon_cipher(ctx); + if (wolfSSL_CTX_set_cipher_list(ctx,"ADH-AES128-SHA") != SSL_SUCCESS) + err_sys("client can't set cipher list 4"); + } +#endif + useClientCert = 0; + } + +#if defined(OPENSSL_EXTRA) || defined(HAVE_WEBSERVER) + wolfSSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack); +#endif + +#if defined(WOLFSSL_SNIFFER) + if (cipherList == NULL) { + /* don't use EDH, can't sniff tmp keys */ + if (wolfSSL_CTX_set_cipher_list(ctx, "AES256-SHA256") != SSL_SUCCESS) { + err_sys("client can't set cipher list 3"); + } + } +#endif + +#ifdef HAVE_OCSP + if (useOcsp) { + if (ocspUrl != NULL) { + wolfSSL_CTX_SetOCSP_OverrideURL(ctx, ocspUrl); + wolfSSL_CTX_EnableOCSP(ctx, WOLFSSL_OCSP_NO_NONCE + | WOLFSSL_OCSP_URL_OVERRIDE); + } + else + wolfSSL_CTX_EnableOCSP(ctx, WOLFSSL_OCSP_NO_NONCE); + } +#endif + +#ifdef USER_CA_CB + wolfSSL_CTX_SetCACb(ctx, CaCb); +#endif + +#ifdef VERIFY_CALLBACK + wolfSSL_CTX_set_verify(ctx, SSL_VERIFY_PEER, myVerify); +#endif +#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS) + if (useClientCert){ + if (wolfSSL_CTX_use_certificate_chain_file(ctx, ourCert) != SSL_SUCCESS) + err_sys("can't load client cert file, check file and run from" + " wolfSSL home dir"); + + if (wolfSSL_CTX_use_PrivateKey_file(ctx, ourKey, SSL_FILETYPE_PEM) + != SSL_SUCCESS) + err_sys("can't load client private key file, check file and run " + "from wolfSSL home dir"); + } + + if (!usePsk && !useAnon) { + if (wolfSSL_CTX_load_verify_locations(ctx, verifyCert,0) != SSL_SUCCESS) + err_sys("can't load ca file, Please run from wolfSSL home dir"); +#ifdef HAVE_ECC + /* load ecc verify too, echoserver uses it by default w/ ecc */ + if (wolfSSL_CTX_load_verify_locations(ctx, eccCert, 0) != SSL_SUCCESS) + err_sys("can't load ecc ca file, Please run from wolfSSL home dir"); +#endif /* HAVE_ECC */ + } +#endif /* !NO_FILESYSTEM && !NO_CERTS */ +#if !defined(NO_CERTS) + if (!usePsk && !useAnon && doPeerCheck == 0) + wolfSSL_CTX_set_verify(ctx, SSL_VERIFY_NONE, 0); + if (!usePsk && !useAnon && overrideDateErrors == 1) + wolfSSL_CTX_set_verify(ctx, SSL_VERIFY_PEER, myDateCb); +#endif + +#ifdef HAVE_CAVIUM + wolfSSL_CTX_UseCavium(ctx, CAVIUM_DEV_ID); +#endif + +#ifdef HAVE_SNI + if (sniHostName) + if (wolfSSL_CTX_UseSNI(ctx, 0, sniHostName, XSTRLEN(sniHostName)) + != SSL_SUCCESS) + err_sys("UseSNI failed"); +#endif +#ifdef HAVE_MAX_FRAGMENT + if (maxFragment) + if (wolfSSL_CTX_UseMaxFragment(ctx, maxFragment) != SSL_SUCCESS) + err_sys("UseMaxFragment failed"); +#endif +#ifdef HAVE_TRUNCATED_HMAC + if (truncatedHMAC) + if (wolfSSL_CTX_UseTruncatedHMAC(ctx) != SSL_SUCCESS) + err_sys("UseTruncatedHMAC failed"); +#endif +#ifdef HAVE_SESSION_TICKET + if (wolfSSL_CTX_UseSessionTicket(ctx) != SSL_SUCCESS) + err_sys("UseSessionTicket failed"); +#endif + + if (benchmark) { + /* time passed in number of connects give average */ + int times = benchmark; + int loops = resumeSession ? 2 : 1; + int i = 0; + WOLFSSL_SESSION* benchSession = NULL; + + while (loops--) { + int benchResume = resumeSession && loops == 0; + double start = current_time(), avg; + + for (i = 0; i < times; i++) { + tcp_connect(&sockfd, host, port, doDTLS); + + ssl = wolfSSL_new(ctx); + if (benchResume) + wolfSSL_set_session(ssl, benchSession); + wolfSSL_set_fd(ssl, sockfd); + if (wolfSSL_connect(ssl) != SSL_SUCCESS) + err_sys("SSL_connect failed"); + + wolfSSL_shutdown(ssl); + if (i == (times-1) && resumeSession) { + benchSession = wolfSSL_get_session(ssl); + } + wolfSSL_free(ssl); + CloseSocket(sockfd); + } + avg = current_time() - start; + avg /= times; + avg *= 1000; /* milliseconds */ + if (benchResume) + printf("wolfSSL_resume avg took: %8.3f milliseconds\n", avg); + else + printf("wolfSSL_connect avg took: %8.3f milliseconds\n", avg); + } + + wolfSSL_CTX_free(ctx); + ((func_args*)args)->return_code = 0; + + exit(EXIT_SUCCESS); + } + + #if defined(WOLFSSL_MDK_ARM) + wolfSSL_CTX_set_verify(ctx, SSL_VERIFY_NONE, 0); + #endif + + ssl = wolfSSL_new(ctx); + if (ssl == NULL) + err_sys("unable to get SSL object"); + #ifdef HAVE_SESSION_TICKET + wolfSSL_set_SessionTicket_cb(ssl, sessionTicketCB, (void*)"initial session"); + #endif + if (doDTLS) { + SOCKADDR_IN_T addr; + build_addr(&addr, host, port, 1); + wolfSSL_dtls_set_peer(ssl, &addr, sizeof(addr)); + tcp_socket(&sockfd, 1); + } + else { + tcp_connect(&sockfd, host, port, 0); + } + +#ifdef HAVE_POLY1305 + /* use old poly to connect with google server */ + if (!XSTRNCMP(domain, "www.google.com", 14)) { + if (wolfSSL_use_old_poly(ssl, 1) != 0) + err_sys("unable to set to old poly"); + } +#endif + + wolfSSL_set_fd(ssl, sockfd); +#ifdef HAVE_CRL + if (disableCRL == 0) { + if (wolfSSL_EnableCRL(ssl, WOLFSSL_CRL_CHECKALL) != SSL_SUCCESS) + err_sys("can't enable crl check"); + if (wolfSSL_LoadCRL(ssl, crlPemDir, SSL_FILETYPE_PEM, 0) != SSL_SUCCESS) + err_sys("can't load crl, check crlfile and date validity"); + if (wolfSSL_SetCRL_Cb(ssl, CRL_CallBack) != SSL_SUCCESS) + err_sys("can't set crl callback"); + } +#endif +#ifdef HAVE_SECURE_RENEGOTIATION + if (scr) { + if (wolfSSL_UseSecureRenegotiation(ssl) != SSL_SUCCESS) + err_sys("can't enable secure renegotiation"); + } +#endif +#ifdef ATOMIC_USER + if (atomicUser) + SetupAtomicUser(ctx, ssl); +#endif +#ifdef HAVE_PK_CALLBACKS + if (pkCallbacks) + SetupPkCallbacks(ctx, ssl); +#endif + if (matchName && doPeerCheck) + wolfSSL_check_domain_name(ssl, domain); +#ifndef WOLFSSL_CALLBACKS + if (nonBlocking) { + wolfSSL_set_using_nonblock(ssl, 1); + tcp_set_nonblocking(&sockfd); + NonBlockingSSL_Connect(ssl); + } + else if (wolfSSL_connect(ssl) != SSL_SUCCESS) { + /* see note at top of README */ + int err = wolfSSL_get_error(ssl, 0); + char buffer[WOLFSSL_MAX_ERROR_SZ]; + printf("err = %d, %s\n", err, + wolfSSL_ERR_error_string(err, buffer)); + err_sys("SSL_connect failed"); + /* if you're getting an error here */ + } +#else + timeout.tv_sec = 2; + timeout.tv_usec = 0; + NonBlockingSSL_Connect(ssl); /* will keep retrying on timeout */ +#endif + showPeer(ssl); + +#ifdef HAVE_SECURE_RENEGOTIATION + if (scr && forceScr) { + if (nonBlocking) { + printf("not doing secure renegotiation on example with" + " nonblocking yet"); + } else { + if (wolfSSL_Rehandshake(ssl) != SSL_SUCCESS) { + int err = wolfSSL_get_error(ssl, 0); + char buffer[WOLFSSL_MAX_ERROR_SZ]; + printf("err = %d, %s\n", err, + wolfSSL_ERR_error_string(err, buffer)); + err_sys("wolfSSL_Rehandshake failed"); + } + } + } +#endif /* HAVE_SECURE_RENEGOTIATION */ + + if (sendGET) { + printf("SSL connect ok, sending GET...\n"); + msgSz = 28; + strncpy(msg, "GET /index.html HTTP/1.0\r\n\r\n", msgSz); + msg[msgSz] = '\0'; + } + if (wolfSSL_write(ssl, msg, msgSz) != msgSz) + err_sys("SSL_write failed"); + + input = wolfSSL_read(ssl, reply, sizeof(reply)-1); + if (input > 0) { + reply[input] = 0; + printf("Server response: %s\n", reply); + + if (sendGET) { /* get html */ + while (1) { + input = wolfSSL_read(ssl, reply, sizeof(reply)-1); + if (input > 0) { + reply[input] = 0; + printf("%s\n", reply); + } + else + break; + } + } + } + else if (input < 0) { + int readErr = wolfSSL_get_error(ssl, 0); + if (readErr != SSL_ERROR_WANT_READ) + err_sys("wolfSSL_read failed"); + } + +#ifndef NO_SESSION_CACHE + if (resumeSession) { + session = wolfSSL_get_session(ssl); + sslResume = wolfSSL_new(ctx); + } +#endif + + if (doDTLS == 0) { /* don't send alert after "break" command */ + ret = wolfSSL_shutdown(ssl); + if (wc_shutdown && ret == SSL_SHUTDOWN_NOT_DONE) + wolfSSL_shutdown(ssl); /* bidirectional shutdown */ + } +#ifdef ATOMIC_USER + if (atomicUser) + FreeAtomicUser(ssl); +#endif + wolfSSL_free(ssl); + CloseSocket(sockfd); + +#ifndef NO_SESSION_CACHE + if (resumeSession) { + if (doDTLS) { + SOCKADDR_IN_T addr; + #ifdef USE_WINDOWS_API + Sleep(500); + #elif defined(WOLFSSL_TIRTOS) + Task_sleep(1); + #else + sleep(1); + #endif + build_addr(&addr, host, port, 1); + wolfSSL_dtls_set_peer(sslResume, &addr, sizeof(addr)); + tcp_socket(&sockfd, 1); + } + else { + tcp_connect(&sockfd, host, port, 0); + } + wolfSSL_set_fd(sslResume, sockfd); +#ifdef HAVE_SECURE_RENEGOTIATION + if (scr) { + if (wolfSSL_UseSecureRenegotiation(sslResume) != SSL_SUCCESS) + err_sys("can't enable secure renegotiation"); + } +#endif + wolfSSL_set_session(sslResume, session); +#ifdef HAVE_SESSION_TICKET + wolfSSL_set_SessionTicket_cb(sslResume, sessionTicketCB, + (void*)"resumed session"); +#endif + + showPeer(sslResume); +#ifndef WOLFSSL_CALLBACKS + if (nonBlocking) { + wolfSSL_set_using_nonblock(sslResume, 1); + tcp_set_nonblocking(&sockfd); + NonBlockingSSL_Connect(sslResume); + } + else if (wolfSSL_connect(sslResume) != SSL_SUCCESS) + err_sys("SSL resume failed"); +#else + timeout.tv_sec = 2; + timeout.tv_usec = 0; + NonBlockingSSL_Connect(ssl); /* will keep retrying on timeout */ +#endif + + if (wolfSSL_session_reused(sslResume)) + printf("reused session id\n"); + else + printf("didn't reuse session id!!!\n"); + + if (wolfSSL_write(sslResume, resumeMsg, resumeSz) != resumeSz) + err_sys("SSL_write failed"); + + if (nonBlocking) { + /* give server a chance to bounce a message back to client */ + #ifdef USE_WINDOWS_API + Sleep(500); + #elif defined(WOLFSSL_TIRTOS) + Task_sleep(1); + #else + sleep(1); + #endif + } + + input = wolfSSL_read(sslResume, reply, sizeof(reply)-1); + if (input > 0) { + reply[input] = 0; + printf("Server resume response: %s\n", reply); + } + + /* try to send session break */ + wolfSSL_write(sslResume, msg, msgSz); + + ret = wolfSSL_shutdown(sslResume); + if (wc_shutdown && ret == SSL_SHUTDOWN_NOT_DONE) + wolfSSL_shutdown(sslResume); /* bidirectional shutdown */ + + wolfSSL_free(sslResume); + CloseSocket(sockfd); + } +#endif /* NO_SESSION_CACHE */ + + wolfSSL_CTX_free(ctx); + + ((func_args*)args)->return_code = 0; + +#ifdef USE_WOLFSSL_MEMORY + if (trackMemory) + ShowMemoryTracker(); +#endif /* USE_WOLFSSL_MEMORY */ + +#if !defined(WOLFSSL_TIRTOS) + return 0; +#endif +} + + +/* so overall tests can pull in test function */ +#ifndef NO_MAIN_DRIVER + + int main(int argc, char** argv) + { + func_args args; + +#ifdef HAVE_CAVIUM + int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID); + if (ret != 0) + err_sys("Cavium OpenNitroxDevice failed"); +#endif /* HAVE_CAVIUM */ + + StartTCP(); + + args.argc = argc; + args.argv = argv; + + wolfSSL_Init(); +#if defined(DEBUG_WOLFSSL) && !defined(WOLFSSL_MDK_SHELL) && !defined(STACK_TRAP) + wolfSSL_Debugging_ON(); +#endif + if (CurrentDir("_build")) + ChangeDirBack(1); + else if (CurrentDir("client")) + ChangeDirBack(2); + else if (CurrentDir("Debug") || CurrentDir("Release")) + ChangeDirBack(3); + +#ifdef HAVE_STACK_SIZE + StackSizeCheck(&args, client_test); +#else + client_test(&args); +#endif + wolfSSL_Cleanup(); + +#ifdef HAVE_CAVIUM + CspShutdown(CAVIUM_DEV_ID); +#endif + return args.return_code; + } + + int myoptind = 0; + char* myoptarg = NULL; + +#endif /* NO_MAIN_DRIVER */ + + + +#ifdef WOLFSSL_CALLBACKS + + int handShakeCB(HandShakeInfo* info) + { + (void)info; + return 0; + } + + + int timeoutCB(TimeoutInfo* info) + { + (void)info; + return 0; + } + +#endif + + +#ifdef HAVE_SESSION_TICKET + + int sessionTicketCB(WOLFSSL* ssl, + const unsigned char* ticket, int ticketSz, + void* ctx) + { + (void)ssl; + (void)ticket; + printf("Session Ticket CB: ticketSz = %d, ctx = %s\n", + ticketSz, (char*)ctx); + return 0; + } + +#endif + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/client/client.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/client/client.h new file mode 100644 index 0000000..e4b13be --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/client/client.h @@ -0,0 +1,25 @@ +/* client.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#pragma once + +THREAD_RETURN WOLFSSL_THREAD client_test(void* args); + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/client/client.sln b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/client/client.sln new file mode 100644 index 0000000..3c4bbb1 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/client/client.sln @@ -0,0 +1,20 @@ + +Microsoft Visual Studio Solution File, Format Version 9.00 +# Visual C++ Express 2005 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "client", "client.vcproj", "{F117DD21-2672-4001-9FF8-8DBEBBFCA380}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Win32 = Debug|Win32 + Release|Win32 = Release|Win32 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {F117DD21-2672-4001-9FF8-8DBEBBFCA380}.Debug|Win32.ActiveCfg = Debug|Win32 + {F117DD21-2672-4001-9FF8-8DBEBBFCA380}.Debug|Win32.Build.0 = Debug|Win32 + {F117DD21-2672-4001-9FF8-8DBEBBFCA380}.Release|Win32.ActiveCfg = Release|Win32 + {F117DD21-2672-4001-9FF8-8DBEBBFCA380}.Release|Win32.Build.0 = Release|Win32 + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/client/client.vcproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/client/client.vcproj new file mode 100644 index 0000000..a743bca --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/client/client.vcproj @@ -0,0 +1,197 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/client/client.vcxproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/client/client.vcxproj new file mode 100644 index 0000000..dec191d --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/client/client.vcxproj @@ -0,0 +1,332 @@ + + + + + Debug + Win32 + + + Debug + x64 + + + DLL Debug + Win32 + + + DLL Debug + x64 + + + DLL Release + Win32 + + + DLL Release + x64 + + + Release + Win32 + + + Release + x64 + + + + {3ADE9549-582D-4D8E-9826-B172197A7959} + client + Win32Proj + + + + Application + v110 + Unicode + true + + + Application + v110 + Unicode + true + + + Application + v110 + Unicode + true + + + Application + v110 + Unicode + true + + + Application + v110 + Unicode + + + Application + v110 + Unicode + + + Application + v110 + Unicode + + + Application + v110 + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + <_ProjectFileVersion>11.0.61030.0 + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\obj\ + true + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\obj\ + true + + + true + $(SolutionDir)$(Platform)\$(Configuration)\ + $(Platform)\$(Configuration)\obj\ + + + true + $(SolutionDir)$(Platform)\$(Configuration)\ + $(Platform)\$(Configuration)\obj\ + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\obj\ + false + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\obj\ + false + + + false + $(SolutionDir)$(Platform)\$(Configuration)\ + $(Platform)\$(Configuration)\obj\ + + + false + $(SolutionDir)$(Platform)\$(Configuration)\ + $(Platform)\$(Configuration)\obj\ + + + + Disabled + ../../;%(AdditionalIncludeDirectories) + WIN32;_DEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;%(PreprocessorDefinitions) + true + EnableFastChecks + MultiThreadedDebugDLL + + Level3 + EditAndContinue + + + Ws2_32.lib;%(AdditionalDependencies) + true + Console + MachineX86 + false + + + + + Disabled + ../../;%(AdditionalIncludeDirectories) + WIN32;_DEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;WOLFSSL_DLL;%(PreprocessorDefinitions) + true + EnableFastChecks + MultiThreadedDebugDLL + + + Level3 + EditAndContinue + + + Ws2_32.lib;%(AdditionalDependencies) + true + Console + MachineX86 + + + + + Disabled + ../../;%(AdditionalIncludeDirectories) + WIN32;_DEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;%(PreprocessorDefinitions) + EnableFastChecks + MultiThreadedDebugDLL + + + Level3 + ProgramDatabase + + + Ws2_32.lib;%(AdditionalDependencies) + true + Console + + + + + Disabled + ../../;%(AdditionalIncludeDirectories) + WIN32;_DEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;WOLFSSL_DLL;%(PreprocessorDefinitions) + EnableFastChecks + MultiThreadedDebugDLL + + + Level3 + ProgramDatabase + + + Ws2_32.lib;%(AdditionalDependencies) + true + Console + + + + + MaxSpeed + true + ../../;%(AdditionalIncludeDirectories) + WIN32;NDEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;%(PreprocessorDefinitions) + MultiThreadedDLL + true + + Level3 + ProgramDatabase + + + Ws2_32.lib;%(AdditionalDependencies) + true + Console + true + true + MachineX86 + false + + + + + MaxSpeed + true + ../../;%(AdditionalIncludeDirectories) + WIN32;NDEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;WOLFSSL_DLL;%(PreprocessorDefinitions) + MultiThreadedDLL + true + + + Level3 + ProgramDatabase + + + Ws2_32.lib;%(AdditionalDependencies) + true + Console + true + true + MachineX86 + + + + + MaxSpeed + true + ../../;%(AdditionalIncludeDirectories) + WIN32;NDEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;%(PreprocessorDefinitions) + MultiThreadedDLL + true + + + Level3 + ProgramDatabase + + + Ws2_32.lib;%(AdditionalDependencies) + true + Console + true + true + + + + + MaxSpeed + true + ../../;%(AdditionalIncludeDirectories) + WIN32;NDEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;WOLFSSL_DLL;%(PreprocessorDefinitions) + MultiThreadedDLL + true + + + Level3 + ProgramDatabase + + + Ws2_32.lib;%(AdditionalDependencies) + true + Console + true + true + + + + + + + + {73973223-5ee8-41ca-8e88-1d60e89a237b} + false + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/client/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/client/include.am new file mode 100644 index 0000000..d0ddcdf --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/client/include.am @@ -0,0 +1,17 @@ +# vim:ft=automake +# All paths should be given relative to the root + +if BUILD_EXAMPLES +noinst_PROGRAMS += examples/client/client +noinst_HEADERS += examples/client/client.h +examples_client_client_SOURCES = examples/client/client.c +examples_client_client_LDADD = src/libwolfssl.la +examples_client_client_DEPENDENCIES = src/libwolfssl.la +endif +EXTRA_DIST += examples/client/client.sln +EXTRA_DIST += examples/client/client-ntru.vcproj +EXTRA_DIST += examples/client/client.vcproj +EXTRA_DIST += examples/client/client.vcxproj + +dist_example_DATA+= examples/client/client.c +DISTCLEANFILES+= examples/client/.libs/client diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoclient/echoclient-ntru.vcproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoclient/echoclient-ntru.vcproj new file mode 100644 index 0000000..9a4ebb6 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoclient/echoclient-ntru.vcproj @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoclient/echoclient.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoclient/echoclient.c new file mode 100644 index 0000000..594d146 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoclient/echoclient.c @@ -0,0 +1,284 @@ +/* echoclient.c + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#ifdef HAVE_CONFIG_H + #include +#endif + +#include + +/* let's use cyassl layer AND cyassl openssl layer */ +#include +#include + +#if defined(CYASSL_MDK_ARM) + #include + #include + + #if defined(CYASSL_MDK5) + #include "cmsis_os.h" + #include "rl_fs.h" + #include "rl_net.h" + #else + #include "rtl.h" + #endif + + #include "cyassl_MDK_ARM.h" +#endif + +#include + +#include "examples/echoclient/echoclient.h" + +void echoclient_test(void* args) +{ + SOCKET_T sockfd = 0; + + FILE* fin = stdin ; + FILE* fout = stdout; + + int inCreated = 0; + int outCreated = 0; + + char msg[1024]; + char reply[1024+1]; + + SSL_METHOD* method = 0; + SSL_CTX* ctx = 0; + SSL* ssl = 0; + + int doDTLS = 0; + int doPSK = 0; + int sendSz; + int argc = 0; + char** argv = 0; + word16 port = yasslPort; + + ((func_args*)args)->return_code = -1; /* error state */ + +#ifndef CYASSL_MDK_SHELL + argc = ((func_args*)args)->argc; + argv = ((func_args*)args)->argv; +#endif + + if (argc >= 2) { + fin = fopen(argv[1], "r"); + inCreated = 1; + } + if (argc >= 3) { + fout = fopen(argv[2], "w"); + outCreated = 1; + } + + if (!fin) err_sys("can't open input file"); + if (!fout) err_sys("can't open output file"); + +#ifdef CYASSL_DTLS + doDTLS = 1; +#endif + +#ifdef CYASSL_LEANPSK + doPSK = 1; +#endif + +#if defined(NO_RSA) && !defined(HAVE_ECC) + doPSK = 1; +#endif + +#if defined(NO_MAIN_DRIVER) && !defined(USE_WINDOWS_API) && !defined(CYASSL_MDK_SHELL) + port = ((func_args*)args)->signal->port; +#endif + +#if defined(CYASSL_DTLS) + method = DTLSv1_2_client_method(); +#elif !defined(NO_TLS) + method = CyaSSLv23_client_method(); +#else + method = SSLv3_client_method(); +#endif + ctx = SSL_CTX_new(method); + +#ifndef NO_FILESYSTEM + #ifndef NO_RSA + if (SSL_CTX_load_verify_locations(ctx, caCert, 0) != SSL_SUCCESS) + err_sys("can't load ca file, Please run from wolfSSL home dir"); + #endif + #ifdef HAVE_ECC + if (SSL_CTX_load_verify_locations(ctx, eccCert, 0) != SSL_SUCCESS) + err_sys("can't load ca file, Please run from wolfSSL home dir"); + #endif +#elif !defined(NO_CERTS) + if (!doPSK) + load_buffer(ctx, caCert, CYASSL_CA); +#endif + +#if defined(CYASSL_SNIFFER) + /* don't use EDH, can't sniff tmp keys */ + SSL_CTX_set_cipher_list(ctx, "AES256-SHA"); +#endif + if (doPSK) { +#ifndef NO_PSK + const char *defaultCipherList; + + CyaSSL_CTX_set_psk_client_callback(ctx, my_psk_client_cb); + #ifdef HAVE_NULL_CIPHER + defaultCipherList = "PSK-NULL-SHA256"; + #else + defaultCipherList = "PSK-AES128-CBC-SHA256"; + #endif + if (CyaSSL_CTX_set_cipher_list(ctx,defaultCipherList) !=SSL_SUCCESS) + err_sys("client can't set cipher list 2"); +#endif + } + +#if defined(OPENSSL_EXTRA) || defined(HAVE_WEBSERVER) + SSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack); +#endif + + #if defined(CYASSL_MDK_ARM) + CyaSSL_CTX_set_verify(ctx, SSL_VERIFY_NONE, 0); + #endif + + ssl = SSL_new(ctx); + + if (doDTLS) { + SOCKADDR_IN_T addr; + build_addr(&addr, yasslIP, port, 1); + CyaSSL_dtls_set_peer(ssl, &addr, sizeof(addr)); + tcp_socket(&sockfd, 1); + } + else { + tcp_connect(&sockfd, yasslIP, port, 0); + } + + SSL_set_fd(ssl, sockfd); +#if defined(USE_WINDOWS_API) && defined(CYASSL_DTLS) && defined(NO_MAIN_DRIVER) + /* let echoserver bind first, TODO: add Windows signal like pthreads does */ + Sleep(100); +#endif + + if (SSL_connect(ssl) != SSL_SUCCESS) err_sys("SSL_connect failed"); + + while (fgets(msg, sizeof(msg), fin) != 0) { + + sendSz = (int)strlen(msg); + + if (SSL_write(ssl, msg, sendSz) != sendSz) + err_sys("SSL_write failed"); + + if (strncmp(msg, "quit", 4) == 0) { + fputs("sending server shutdown command: quit!\n", fout); + break; + } + + if (strncmp(msg, "break", 5) == 0) { + fputs("sending server session close: break!\n", fout); + break; + } + + #ifndef CYASSL_MDK_SHELL + while (sendSz) { + int got; + if ( (got = SSL_read(ssl, reply, sizeof(reply)-1)) > 0) { + reply[got] = 0; + fputs(reply, fout); + fflush(fout) ; + sendSz -= got; + } + else + break; + } + #else + { + int got; + if ( (got = SSL_read(ssl, reply, sizeof(reply)-1)) > 0) { + reply[got] = 0; + fputs(reply, fout); + fflush(fout) ; + sendSz -= got; + } + } + #endif + } + + +#ifdef CYASSL_DTLS + strncpy(msg, "break", 6); + sendSz = (int)strlen(msg); + /* try to tell server done */ + SSL_write(ssl, msg, sendSz); +#else + SSL_shutdown(ssl); +#endif + + SSL_free(ssl); + SSL_CTX_free(ctx); + + fflush(fout); + if (inCreated) fclose(fin); + if (outCreated) fclose(fout); + + CloseSocket(sockfd); + ((func_args*)args)->return_code = 0; +} + + +/* so overall tests can pull in test function */ +#ifndef NO_MAIN_DRIVER + + int main(int argc, char** argv) + { + func_args args; + +#ifdef HAVE_CAVIUM + int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID); + if (ret != 0) + err_sys("Cavium OpenNitroxDevice failed"); +#endif /* HAVE_CAVIUM */ + + StartTCP(); + + args.argc = argc; + args.argv = argv; + + CyaSSL_Init(); +#if defined(DEBUG_CYASSL) && !defined(CYASSL_MDK_SHELL) + CyaSSL_Debugging_ON(); +#endif +#ifndef CYASSL_TIRTOS + if (CurrentDir("echoclient")) + ChangeDirBack(2); + else if (CurrentDir("Debug") || CurrentDir("Release")) + ChangeDirBack(3); +#endif + echoclient_test(&args); + + CyaSSL_Cleanup(); + +#ifdef HAVE_CAVIUM + CspShutdown(CAVIUM_DEV_ID); +#endif + return args.return_code; + } + +#endif /* NO_MAIN_DRIVER */ + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoclient/echoclient.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoclient/echoclient.h new file mode 100644 index 0000000..d945edb --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoclient/echoclient.h @@ -0,0 +1,23 @@ +/* echoclient.h + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#pragma once +void echoclient_test(void* args); diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoclient/echoclient.sln b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoclient/echoclient.sln new file mode 100644 index 0000000..3fb7851 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoclient/echoclient.sln @@ -0,0 +1,20 @@ + +Microsoft Visual Studio Solution File, Format Version 9.00 +# Visual C++ Express 2005 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "echoclient", "echoclient.vcproj", "{A7AA93AD-AFF0-4FF0-8AED-14685DE55CF3}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Win32 = Debug|Win32 + Release|Win32 = Release|Win32 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {A7AA93AD-AFF0-4FF0-8AED-14685DE55CF3}.Debug|Win32.ActiveCfg = Debug|Win32 + {A7AA93AD-AFF0-4FF0-8AED-14685DE55CF3}.Debug|Win32.Build.0 = Debug|Win32 + {A7AA93AD-AFF0-4FF0-8AED-14685DE55CF3}.Release|Win32.ActiveCfg = Release|Win32 + {A7AA93AD-AFF0-4FF0-8AED-14685DE55CF3}.Release|Win32.Build.0 = Release|Win32 + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoclient/echoclient.vcproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoclient/echoclient.vcproj new file mode 100644 index 0000000..3a2a085 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoclient/echoclient.vcproj @@ -0,0 +1,197 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoclient/echoclient.vcxproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoclient/echoclient.vcxproj new file mode 100644 index 0000000..a3a6054 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoclient/echoclient.vcxproj @@ -0,0 +1,334 @@ + + + + + Debug + Win32 + + + Debug + x64 + + + DLL Debug + Win32 + + + DLL Debug + x64 + + + DLL Release + Win32 + + + DLL Release + x64 + + + Release + Win32 + + + Release + x64 + + + + {8362A816-C5DC-4E22-B5C5-9E6806387073} + echoclient + Win32Proj + + + + Application + v110 + Unicode + true + + + Application + v110 + Unicode + true + + + Application + v110 + Unicode + true + + + Application + v110 + Unicode + true + + + Application + v110 + Unicode + + + Application + v110 + Unicode + + + Application + v110 + Unicode + + + Application + v110 + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + <_ProjectFileVersion>11.0.61030.0 + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\obj\ + true + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\obj\ + true + + + true + $(SolutionDir)$(Platform)\$(Configuration)\ + $(Platform)\$(Configuration)\obj\ + + + true + $(SolutionDir)$(Platform)\$(Configuration)\ + $(Platform)\$(Configuration)\obj\ + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\obj\ + false + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\obj\ + false + + + false + $(SolutionDir)$(Platform)\$(Configuration)\ + $(Platform)\$(Configuration)\obj\ + + + false + $(SolutionDir)$(Platform)\$(Configuration)\ + $(Platform)\$(Configuration)\obj\ + + + + Disabled + ../../;%(AdditionalIncludeDirectories) + WIN32;_DEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;%(PreprocessorDefinitions) + true + EnableFastChecks + MultiThreadedDebugDLL + + Level3 + EditAndContinue + + + Ws2_32.lib;%(AdditionalDependencies) + true + Console + MachineX86 + false + + + + + + Disabled + ../../;%(AdditionalIncludeDirectories) + WIN32;_DEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;WOLFSSL_DLL;%(PreprocessorDefinitions) + true + EnableFastChecks + MultiThreadedDebugDLL + + + Level3 + EditAndContinue + + + Ws2_32.lib;%(AdditionalDependencies) + true + Console + MachineX86 + + + + + Disabled + ../../;%(AdditionalIncludeDirectories) + WIN32;_DEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;%(PreprocessorDefinitions) + EnableFastChecks + MultiThreadedDebugDLL + + + Level3 + ProgramDatabase + + + Ws2_32.lib;%(AdditionalDependencies) + true + Console + + + + + Disabled + ../../;%(AdditionalIncludeDirectories) + WIN32;_DEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;WOLFSSL_DLL;%(PreprocessorDefinitions) + EnableFastChecks + MultiThreadedDebugDLL + + + Level3 + ProgramDatabase + + + Ws2_32.lib;%(AdditionalDependencies) + true + Console + + + + + MaxSpeed + true + ../../;%(AdditionalIncludeDirectories) + WIN32;NDEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;%(PreprocessorDefinitions) + MultiThreadedDLL + true + + Level3 + ProgramDatabase + + + Ws2_32.lib;%(AdditionalDependencies) + true + Console + true + true + MachineX86 + false + + + + + + MaxSpeed + true + ../../;%(AdditionalIncludeDirectories) + WIN32;NDEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;WOLFSSL_DLL;%(PreprocessorDefinitions) + MultiThreadedDLL + true + + + Level3 + ProgramDatabase + + + Ws2_32.lib;%(AdditionalDependencies) + true + Console + true + true + MachineX86 + + + + + MaxSpeed + true + ../../;%(AdditionalIncludeDirectories) + WIN32;NDEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;%(PreprocessorDefinitions) + MultiThreadedDLL + true + + + Level3 + ProgramDatabase + + + Ws2_32.lib;%(AdditionalDependencies) + true + Console + true + true + + + + + MaxSpeed + true + ../../;%(AdditionalIncludeDirectories) + WIN32;NDEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;WOLFSSL_DLL;%(PreprocessorDefinitions) + MultiThreadedDLL + true + + + Level3 + ProgramDatabase + + + Ws2_32.lib;%(AdditionalDependencies) + true + Console + true + true + + + + + + + + {73973223-5ee8-41ca-8e88-1d60e89a237b} + false + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoclient/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoclient/include.am new file mode 100644 index 0000000..179cf99 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoclient/include.am @@ -0,0 +1,20 @@ +# vim:ft=automake +# included from Top Level Makefile.am +# All paths should be given relative to the root + + +if BUILD_EXAMPLES +noinst_PROGRAMS += examples/echoclient/echoclient +noinst_HEADERS += examples/echoclient/echoclient.h +examples_echoclient_echoclient_SOURCES = examples/echoclient/echoclient.c +examples_echoclient_echoclient_LDADD = src/libwolfssl.la +examples_echoclient_echoclient_DEPENDENCIES = src/libwolfssl.la +endif +EXTRA_DIST += examples/echoclient/echoclient.sln +EXTRA_DIST += examples/echoclient/echoclient-ntru.vcproj +EXTRA_DIST += examples/echoclient/echoclient.vcproj +EXTRA_DIST += examples/echoclient/echoclient.vcxproj + +dist_example_DATA+= examples/echoclient/echoclient.c +DISTCLEANFILES+= examples/echoclient/.libs/echoclient + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoserver/echoserver-ntru.vcproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoserver/echoserver-ntru.vcproj new file mode 100644 index 0000000..924fdd8 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoserver/echoserver-ntru.vcproj @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoserver/echoserver.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoserver/echoserver.c new file mode 100644 index 0000000..6b5c575 --- /dev/null +++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoserver/echoserver.c @@ -0,0 +1,395 @@ +/* echoserver.c + * + * Copyright (C) 2006-2015 wolfSSL Inc. + * + * This file is part of wolfSSL. (formerly known as CyaSSL) + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#ifdef HAVE_CONFIG_H + #include +#endif + +#include /* name change portability layer */ +#include +#ifdef HAVE_ECC + #include /* ecc_fp_free */ +#endif + +#if defined(CYASSL_MDK_ARM) + #include + #include + + #if defined(CYASSL_MDK5) + #include "cmsis_os.h" + #include "rl_fs.h" + #include "rl_net.h" + #else + #include "rtl.h" + #endif + + #include "cyassl_MDK_ARM.h" +#endif + +#include +#include + +#ifndef NO_MAIN_DRIVER + #define ECHO_OUT +#endif + +#include "examples/echoserver/echoserver.h" + +#define SVR_COMMAND_SIZE 256 + +static void SignalReady(void* args, word16 port) +{ +#if defined(_POSIX_THREADS) && defined(NO_MAIN_DRIVER) && !defined(__MINGW32__) + /* signal ready to tcp_accept */ + func_args* server_args = (func_args*)args; + tcp_ready* ready = server_args->signal; + pthread_mutex_lock(&ready->mutex); + ready->ready = 1; + ready->port = port; + pthread_cond_signal(&ready->cond); + pthread_mutex_unlock(&ready->mutex); +#endif + (void)args; + (void)port; +} + + +THREAD_RETURN CYASSL_THREAD echoserver_test(void* args) +{ + SOCKET_T sockfd = 0; + CYASSL_METHOD* method = 0; + CYASSL_CTX* ctx = 0; + + int doDTLS = 0; + int doPSK = 0; + int outCreated = 0; + int shutDown = 0; + int useAnyAddr = 0; + word16 port = yasslPort; + int argc = ((func_args*)args)->argc; + char** argv = ((func_args*)args)->argv; + +#ifdef ECHO_OUT + FILE* fout = stdout; + if (argc >= 2) { + fout = fopen(argv[1], "w"); + outCreated = 1; + } + if (!fout) err_sys("can't open output file"); +#endif + (void)outCreated; + (void)argc; + (void)argv; + + ((func_args*)args)->return_code = -1; /* error state */ + +#ifdef CYASSL_DTLS + doDTLS = 1; +#endif + +#ifdef CYASSL_LEANPSK + doPSK = 1; +#endif + +#if defined(NO_RSA) && !defined(HAVE_ECC) + doPSK = 1; +#endif + + #if defined(NO_MAIN_DRIVER) && !defined(USE_WINDOWS_API) && \ + !defined(CYASSL_SNIFFER) && !defined(CYASSL_MDK_SHELL) && \ + !defined(CYASSL_TIRTOS) + port = 0; + #endif + #if defined(USE_ANY_ADDR) + useAnyAddr = 1; + #endif + +#ifdef CYASSL_TIRTOS + fdOpenSession(Task_self()); +#endif + + tcp_listen(&sockfd, &port, useAnyAddr, doDTLS); + +#if defined(CYASSL_DTLS) + method = CyaDTLSv1_2_server_method(); +#elif !defined(NO_TLS) + method = CyaSSLv23_server_method(); +#else + method = CyaSSLv3_server_method(); +#endif + ctx = CyaSSL_CTX_new(method); + /* CyaSSL_CTX_set_session_cache_mode(ctx, SSL_SESS_CACHE_OFF); */ + +#if defined(OPENSSL_EXTRA) || defined(HAVE_WEBSERVER) + CyaSSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack); +#endif + +#if defined(HAVE_SESSION_TICKET) && defined(HAVE_CHACHA) && \ + defined(HAVE_POLY1305) + if (TicketInit() != 0) + err_sys("unable to setup Session Ticket Key context"); + wolfSSL_CTX_set_TicketEncCb(ctx, myTicketEncCb); +#endif + +#ifndef NO_FILESYSTEM + if (doPSK == 0) { + #ifdef HAVE_NTRU + /* ntru */ + if (CyaSSL_CTX_use_certificate_file(ctx, ntruCert, SSL_FILETYPE_PEM) + != SSL_SUCCESS) + err_sys("can't load ntru cert file, " + "Please run from wolfSSL home dir"); + + if (CyaSSL_CTX_use_NTRUPrivateKey_file(ctx, ntruKey) + != SSL_SUCCESS) + err_sys("can't load ntru key file, " + "Please run from wolfSSL home dir"); + #elif defined(HAVE_ECC) && !defined(CYASSL_SNIFFER) + /* ecc */ + if (CyaSSL_CTX_use_certificate_file(ctx, eccCert, SSL_FILETYPE_PEM) + != SSL_SUCCESS) + err_sys("can't load server cert file, " + "Please run from wolfSSL home dir"); + + if (CyaSSL_CTX_use_PrivateKey_file(ctx, eccKey, SSL_FILETYPE_PEM) + != SSL_SUCCESS) + err_sys("can't load server key file, " + "Please run from wolfSSL home dir"); + #elif defined(NO_CERTS) + /* do nothing, just don't load cert files */ + #else + /* normal */ + if (CyaSSL_CTX_use_certificate_file(ctx, svrCert, SSL_FILETYPE_PEM) + != SSL_SUCCESS) + err_sys("can't load server cert file, " + "Please run from wolfSSL home dir"); + + if (CyaSSL_CTX_use_PrivateKey_file(ctx, svrKey, SSL_FILETYPE_PEM) + != SSL_SUCCESS) + err_sys("can't load server key file, " + "Please run from wolfSSL home dir"); + #endif + } /* doPSK */ +#elif !defined(NO_CERTS) + if (!doPSK) { + load_buffer(ctx, svrCert, CYASSL_CERT); + load_buffer(ctx, svrKey, CYASSL_KEY); + } +#endif + +#if defined(CYASSL_SNIFFER) + /* don't use EDH, can't sniff tmp keys */ + CyaSSL_CTX_set_cipher_list(ctx, "AES256-SHA"); +#endif + + if (doPSK) { +#ifndef NO_PSK + const char *defaultCipherList; + + CyaSSL_CTX_set_psk_server_callback(ctx, my_psk_server_cb); + CyaSSL_CTX_use_psk_identity_hint(ctx, "cyassl server"); + #ifdef HAVE_NULL_CIPHER + defaultCipherList = "PSK-NULL-SHA256"; + #else + defaultCipherList = "PSK-AES128-CBC-SHA256"; + #endif + if (CyaSSL_CTX_set_cipher_list(ctx, defaultCipherList) != SSL_SUCCESS) + err_sys("server can't set cipher list 2"); +#endif + } + + SignalReady(args, port); + + while (!shutDown) { + CYASSL* ssl = 0; + char command[SVR_COMMAND_SIZE+1]; + int echoSz = 0; + int clientfd; + int firstRead = 1; + int gotFirstG = 0; + +#ifndef CYASSL_DTLS + SOCKADDR_IN_T client; + socklen_t client_len = sizeof(client); + clientfd = accept(sockfd, (struct sockaddr*)&client, + (ACCEPT_THIRD_T)&client_len); +#else + clientfd = udp_read_connect(sockfd); +#endif + if (clientfd == -1) err_sys("tcp accept failed"); + + ssl = CyaSSL_new(ctx); + if (ssl == NULL) err_sys("SSL_new failed"); + CyaSSL_set_fd(ssl, clientfd); + #if !defined(NO_FILESYSTEM) && !defined(NO_DH) && !defined(NO_ASN) + CyaSSL_SetTmpDH_file(ssl, dhParam, SSL_FILETYPE_PEM); + #elif !defined(NO_DH) + SetDH(ssl); /* will repick suites with DHE, higher than PSK */ + #endif + if (CyaSSL_accept(ssl) != SSL_SUCCESS) { + printf("SSL_accept failed\n"); + CyaSSL_free(ssl); + CloseSocket(clientfd); + continue; + } +#if defined(PEER_INFO) + showPeer(ssl); +#endif + + while ( (echoSz = CyaSSL_read(ssl, command, sizeof(command)-1)) > 0) { + + if (firstRead == 1) { + firstRead = 0; /* browser may send 1 byte 'G' to start */ + if (echoSz == 1 && command[0] == 'G') { + gotFirstG = 1; + continue; + } + } + else if (gotFirstG == 1 && strncmp(command, "ET /", 4) == 0) { + strncpy(command, "GET", 4); + /* fall through to normal GET */ + } + + if ( strncmp(command, "quit", 4) == 0) { + printf("client sent quit command: shutting down!\n"); + shutDown = 1; + break; + } + if ( strncmp(command, "break", 5) == 0) { + printf("client sent break command: closing session!\n"); + break; + } +#ifdef PRINT_SESSION_STATS + if ( strncmp(command, "printstats", 10) == 0) { + CyaSSL_PrintSessionStats(); + break; + } +#endif + if ( strncmp(command, "GET", 3) == 0) { + char type[] = "HTTP/1.0 200 ok\r\nContent-type:" + " text/html\r\n\r\n"; + char header[] = "\n
\n";
+                char body[]   = "greetings from wolfSSL\n";
+                char footer[] = "\r\n\r\n";
+            
+                strncpy(command, type, sizeof(type));
+                echoSz = sizeof(type) - 1;
+
+                strncpy(&command[echoSz], header, sizeof(header));
+                echoSz += (int)sizeof(header) - 1;
+                strncpy(&command[echoSz], body, sizeof(body));
+                echoSz += (int)sizeof(body) - 1;
+                strncpy(&command[echoSz], footer, sizeof(footer));
+                echoSz += (int)sizeof(footer);
+
+                if (CyaSSL_write(ssl, command, echoSz) != echoSz)
+                    err_sys("SSL_write failed");
+                break;
+            }
+            command[echoSz] = 0;
+
+            #ifdef ECHO_OUT
+                fputs(command, fout);
+            #endif
+
+            if (CyaSSL_write(ssl, command, echoSz) != echoSz)
+                err_sys("SSL_write failed");
+        }
+#ifndef CYASSL_DTLS
+        CyaSSL_shutdown(ssl);
+#endif
+        CyaSSL_free(ssl);
+        CloseSocket(clientfd);
+#ifdef CYASSL_DTLS
+        tcp_listen(&sockfd, &port, useAnyAddr, doDTLS);
+        SignalReady(args, port);
+#endif
+    }
+
+    CloseSocket(sockfd);
+    CyaSSL_CTX_free(ctx);
+
+#ifdef ECHO_OUT
+    if (outCreated)
+        fclose(fout);
+#endif
+
+    ((func_args*)args)->return_code = 0;
+
+#if defined(NO_MAIN_DRIVER) && defined(HAVE_ECC) && defined(FP_ECC) \
+                            && defined(HAVE_THREAD_LS)
+    ecc_fp_free();  /* free per thread cache */
+#endif
+
+#ifdef CYASSL_TIRTOS
+    fdCloseSession(Task_self());
+#endif
+
+#if defined(HAVE_SESSION_TICKET) && defined(HAVE_CHACHA) && \
+                                    defined(HAVE_POLY1305)
+    TicketCleanup();
+#endif
+
+#ifndef CYASSL_TIRTOS
+    return 0;
+#endif
+}
+
+
+/* so overall tests can pull in test function */
+#ifndef NO_MAIN_DRIVER
+
+    int main(int argc, char** argv)
+    {
+        func_args args;
+
+#ifdef HAVE_CAVIUM
+        int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID);
+        if (ret != 0)
+            err_sys("Cavium OpenNitroxDevice failed");
+#endif /* HAVE_CAVIUM */
+
+        StartTCP();
+
+        args.argc = argc;
+        args.argv = argv;
+
+        CyaSSL_Init();
+#if defined(DEBUG_CYASSL) && !defined(CYASSL_MDK_SHELL)
+        CyaSSL_Debugging_ON();
+#endif
+        if (CurrentDir("echoserver"))
+            ChangeDirBack(2);
+        else if (CurrentDir("Debug") || CurrentDir("Release"))
+            ChangeDirBack(3);
+        echoserver_test(&args);
+        CyaSSL_Cleanup();
+
+#ifdef HAVE_CAVIUM
+        CspShutdown(CAVIUM_DEV_ID);
+#endif
+        return args.return_code;
+    }
+
+        
+#endif /* NO_MAIN_DRIVER */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoserver/echoserver.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoserver/echoserver.h
new file mode 100644
index 0000000..2f0d88d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoserver/echoserver.h
@@ -0,0 +1,24 @@
+/* echoserver.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#pragma once
+
+THREAD_RETURN WOLFSSL_THREAD echoserver_test(void* args);
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoserver/echoserver.sln b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoserver/echoserver.sln
new file mode 100644
index 0000000..6bda354
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoserver/echoserver.sln
@@ -0,0 +1,20 @@
+
+Microsoft Visual Studio Solution File, Format Version 9.00
+# Visual C++ Express 2005
+Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "echoserver", "echoserver.vcproj", "{4F3F3EF1-BB95-466A-87B2-A91C059D0197}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|Win32 = Debug|Win32
+		Release|Win32 = Release|Win32
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{4F3F3EF1-BB95-466A-87B2-A91C059D0197}.Debug|Win32.ActiveCfg = Debug|Win32
+		{4F3F3EF1-BB95-466A-87B2-A91C059D0197}.Debug|Win32.Build.0 = Debug|Win32
+		{4F3F3EF1-BB95-466A-87B2-A91C059D0197}.Release|Win32.ActiveCfg = Release|Win32
+		{4F3F3EF1-BB95-466A-87B2-A91C059D0197}.Release|Win32.Build.0 = Release|Win32
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoserver/echoserver.vcproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoserver/echoserver.vcproj
new file mode 100644
index 0000000..0fc396f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoserver/echoserver.vcproj
@@ -0,0 +1,197 @@
+
+
+	
+		
+	
+	
+	
+	
+		
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+		
+		
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+		
+	
+	
+	
+	
+		
+			
+			
+		
+		
+		
+		
+		
+	
+	
+	
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoserver/echoserver.vcxproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoserver/echoserver.vcxproj
new file mode 100644
index 0000000..096ba75
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoserver/echoserver.vcxproj
@@ -0,0 +1,333 @@
+
+
+  
+    
+      Debug
+      Win32
+    
+    
+      Debug
+      x64
+    
+    
+      DLL Debug
+      Win32
+    
+    
+      DLL Debug
+      x64
+    
+    
+      DLL Release
+      Win32
+    
+    
+      DLL Release
+      x64
+    
+    
+      Release
+      Win32
+    
+    
+      Release
+      x64
+    
+  
+  
+    {07D97C48-E08F-4E34-9F67-3064039FF2CB}
+    echoserver
+    Win32Proj
+  
+  
+  
+    Application
+    v110
+    Unicode
+    true
+  
+  
+    Application
+    v110
+    Unicode
+    true
+  
+  
+    Application
+    v110
+    Unicode
+    true
+  
+  
+    Application
+    v110
+    Unicode
+    true
+  
+  
+    Application
+    v110
+    Unicode
+  
+  
+    Application
+    v110
+    Unicode
+  
+  
+    Application
+    v110
+    Unicode
+  
+  
+    Application
+    v110
+    Unicode
+  
+  
+  
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+  
+    <_ProjectFileVersion>11.0.61030.0
+  
+  
+    $(SolutionDir)$(Configuration)\
+    $(Configuration)\obj\
+    true
+  
+  
+    $(SolutionDir)$(Configuration)\
+    $(Configuration)\obj\
+    true
+  
+  
+    true
+    $(SolutionDir)$(Platform)\$(Configuration)\
+    $(Platform)\$(Configuration)\obj\
+  
+  
+    true
+    $(SolutionDir)$(Platform)\$(Configuration)\
+    $(Platform)\$(Configuration)\obj\
+  
+  
+    $(SolutionDir)$(Configuration)\
+    $(Configuration)\obj\
+    false
+  
+  
+    $(SolutionDir)$(Configuration)\
+    $(Configuration)\obj\
+    false
+  
+  
+    false
+    $(SolutionDir)$(Platform)\$(Configuration)\
+    $(Platform)\$(Configuration)\obj\
+  
+  
+    false
+    $(SolutionDir)$(Platform)\$(Configuration)\
+    $(Platform)\$(Configuration)\obj\
+  
+  
+    
+      Disabled
+      ../../;%(AdditionalIncludeDirectories)
+      USE_ANY_ADDR;OPENSSL_EXTRA;NO_PSK;%(PreprocessorDefinitions)
+      true
+      EnableFastChecks
+      MultiThreadedDebugDLL
+      
+      Level3
+      EditAndContinue
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+      MachineX86
+      false
+
+    
+  
+  
+    
+      Disabled
+      ../../;%(AdditionalIncludeDirectories)
+      USE_ANY_ADDR;OPENSSL_EXTRA;NO_PSK;WOLFSSL_DLL;%(PreprocessorDefinitions)
+      true
+      EnableFastChecks
+      MultiThreadedDebugDLL
+      
+      
+      Level3
+      EditAndContinue
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+      MachineX86
+    
+  
+  
+    
+      Disabled
+      ../../;%(AdditionalIncludeDirectories)
+      USE_ANY_ADDR;OPENSSL_EXTRA;NO_PSK;%(PreprocessorDefinitions)
+      EnableFastChecks
+      MultiThreadedDebugDLL
+      
+      
+      Level3
+      ProgramDatabase
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+    
+  
+  
+    
+      Disabled
+      ../../;%(AdditionalIncludeDirectories)
+      USE_ANY_ADDR;OPENSSL_EXTRA;NO_PSK;WOLFSSL_DLL;%(PreprocessorDefinitions)
+      EnableFastChecks
+      MultiThreadedDebugDLL
+      
+      
+      Level3
+      ProgramDatabase
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+    
+  
+  
+    
+      MaxSpeed
+      true
+      ../../;%(AdditionalIncludeDirectories)
+      USE_ANY_ADDR;OPENSSL_EXTRA;NO_PSK;%(PreprocessorDefinitions)
+      MultiThreadedDLL
+      true
+      
+      Level3
+      ProgramDatabase
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+      true
+      true
+      MachineX86
+      false
+    
+  
+  
+    
+      MaxSpeed
+      true
+      ../../;%(AdditionalIncludeDirectories)
+      USE_ANY_ADDR;OPENSSL_EXTRA;NO_PSK;WOLFSSL_DLL;%(PreprocessorDefinitions)
+      MultiThreadedDLL
+      true
+      
+      
+      Level3
+      ProgramDatabase
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+      true
+      true
+      MachineX86
+    
+  
+  
+    
+      MaxSpeed
+      true
+      ../../;%(AdditionalIncludeDirectories)
+      USE_ANY_ADDR;OPENSSL_EXTRA;NO_PSK;%(PreprocessorDefinitions)
+      MultiThreadedDLL
+      true
+      
+      
+      Level3
+      ProgramDatabase
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+      true
+      true
+    
+  
+  
+    
+      MaxSpeed
+      true
+      ../../;%(AdditionalIncludeDirectories)
+      USE_ANY_ADDR;OPENSSL_EXTRA;NO_PSK;WOLFSSL_DLL;%(PreprocessorDefinitions)
+      MultiThreadedDLL
+      true
+      
+      
+      Level3
+      ProgramDatabase
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+      true
+      true
+    
+  
+  
+    
+  
+  
+    
+      {73973223-5ee8-41ca-8e88-1d60e89a237b}
+      false
+    
+  
+  
+  
+  
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoserver/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoserver/include.am
new file mode 100644
index 0000000..a843121
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/echoserver/include.am
@@ -0,0 +1,19 @@
+# vim:ft=automake
+# included from Top Level Makefile.am
+# All paths should be given relative to the root
+
+
+if BUILD_EXAMPLES
+noinst_PROGRAMS += examples/echoserver/echoserver
+noinst_HEADERS += examples/echoserver/echoserver.h
+examples_echoserver_echoserver_SOURCES      = examples/echoserver/echoserver.c
+examples_echoserver_echoserver_LDADD        = src/libwolfssl.la
+examples_echoserver_echoserver_DEPENDENCIES = src/libwolfssl.la
+endif
+EXTRA_DIST += examples/echoserver/echoserver.sln
+EXTRA_DIST += examples/echoserver/echoserver-ntru.vcproj
+EXTRA_DIST += examples/echoserver/echoserver.vcproj
+EXTRA_DIST += examples/echoserver/echoserver.vcxproj
+
+dist_example_DATA+= examples/echoserver/echoserver.c
+DISTCLEANFILES+= examples/echoserver/.libs/echoserver
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/server/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/server/include.am
new file mode 100644
index 0000000..bd70376
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/server/include.am
@@ -0,0 +1,20 @@
+# vim:ft=automake
+# included from Top Level Makefile.am
+# All paths should be given relative to the root
+
+
+if BUILD_EXAMPLES
+noinst_PROGRAMS += examples/server/server
+noinst_HEADERS += examples/server/server.h
+examples_server_server_SOURCES      = examples/server/server.c
+examples_server_server_LDADD        = src/libwolfssl.la
+examples_server_server_DEPENDENCIES = src/libwolfssl.la
+endif
+EXTRA_DIST += examples/server/server.sln
+EXTRA_DIST += examples/server/server-ntru.vcproj
+EXTRA_DIST += examples/server/server.vcproj
+EXTRA_DIST += examples/server/server.vcxproj
+
+dist_example_DATA+= examples/server/server.c
+DISTCLEANFILES+= examples/server/.libs/server
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/server/server-ntru.vcproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/server/server-ntru.vcproj
new file mode 100644
index 0000000..8e45e16
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/server/server-ntru.vcproj
@@ -0,0 +1,199 @@
+
+
+	
+		
+	
+	
+	
+	
+		
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+		
+		
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+		
+	
+	
+	
+	
+		
+			
+			
+		
+		
+		
+		
+		
+	
+	
+	
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/server/server.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/server/server.c
new file mode 100644
index 0000000..a8d597a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/server/server.c
@@ -0,0 +1,777 @@
+/* server.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+#include  /* name change portability layer */
+
+#include 
+#ifdef HAVE_ECC
+    #include    /* ecc_fp_free */
+#endif
+
+#if !defined(WOLFSSL_TRACK_MEMORY) && !defined(NO_MAIN_DRIVER)
+    /* in case memory tracker wants stats */
+    #define WOLFSSL_TRACK_MEMORY
+#endif
+
+#if defined(CYASSL_MDK_ARM)
+        #include 
+        #include 
+
+        #if defined(CYASSL_MDK5)
+            #include "cmsis_os.h"
+            #include "rl_fs.h" 
+            #include "rl_net.h" 
+        #else
+            #include "rtl.h"
+        #endif
+
+        #include "cyassl_MDK_ARM.h"
+#endif
+#include 
+#include 
+
+#include "examples/server/server.h"
+
+
+#ifdef CYASSL_CALLBACKS
+    int srvHandShakeCB(HandShakeInfo*);
+    int srvTimeoutCB(TimeoutInfo*);
+    Timeval srvTo;
+#endif
+
+#ifndef NO_HANDSHAKE_DONE_CB
+    int myHsDoneCb(WOLFSSL* ssl, void* user_ctx);
+#endif
+
+
+
+static void NonBlockingSSL_Accept(SSL* ssl)
+{
+#ifndef CYASSL_CALLBACKS
+    int ret = SSL_accept(ssl);
+#else
+    int ret = CyaSSL_accept_ex(ssl, srvHandShakeCB, srvTimeoutCB, srvTo);
+#endif
+    int error = SSL_get_error(ssl, 0);
+    SOCKET_T sockfd = (SOCKET_T)CyaSSL_get_fd(ssl);
+    int select_ret;
+
+    while (ret != SSL_SUCCESS && (error == SSL_ERROR_WANT_READ ||
+                                  error == SSL_ERROR_WANT_WRITE)) {
+        int currTimeout = 1;
+
+        if (error == SSL_ERROR_WANT_READ)
+            printf("... server would read block\n");
+        else
+            printf("... server would write block\n");
+
+#ifdef CYASSL_DTLS
+        currTimeout = CyaSSL_dtls_get_current_timeout(ssl);
+#endif
+        select_ret = tcp_select(sockfd, currTimeout);
+
+        if ((select_ret == TEST_RECV_READY) ||
+                                        (select_ret == TEST_ERROR_READY)) {
+            #ifndef CYASSL_CALLBACKS
+                ret = SSL_accept(ssl);
+            #else
+                ret = CyaSSL_accept_ex(ssl,
+                                    srvHandShakeCB, srvTimeoutCB, srvTo);
+            #endif
+            error = SSL_get_error(ssl, 0);
+        }
+        else if (select_ret == TEST_TIMEOUT && !CyaSSL_dtls(ssl)) {
+            error = SSL_ERROR_WANT_READ;
+        }
+#ifdef CYASSL_DTLS
+        else if (select_ret == TEST_TIMEOUT && CyaSSL_dtls(ssl) &&
+                                            CyaSSL_dtls_got_timeout(ssl) >= 0) {
+            error = SSL_ERROR_WANT_READ;
+        }
+#endif
+        else {
+            error = SSL_FATAL_ERROR;
+        }
+    }
+    if (ret != SSL_SUCCESS)
+        err_sys("SSL_accept failed");
+}
+
+
+static void Usage(void)
+{
+    printf("server "    LIBCYASSL_VERSION_STRING
+           " NOTE: All files relative to wolfSSL home dir\n");
+    printf("-?          Help, print this usage\n");
+    printf("-p     Port to listen on, not 0, default %d\n", yasslPort);
+    printf("-v     SSL version [0-3], SSLv3(0) - TLS1.2(3)), default %d\n",
+                                 SERVER_DEFAULT_VERSION);
+    printf("-l     Cipher list\n");
+    printf("-c    Certificate file,           default %s\n", svrCert);
+    printf("-k    Key file,                   default %s\n", svrKey);
+    printf("-A    Certificate Authority file, default %s\n", cliCert);
+#ifndef NO_DH
+    printf("-D    Diffie-Hellman Params file, default %s\n", dhParam);
+    printf("-Z     Minimum DH key bits,        default %d\n",
+                                 DEFAULT_MIN_DHKEY_BITS);
+#endif
+    printf("-d          Disable client cert check\n");
+    printf("-b          Bind to any interface instead of localhost only\n");
+    printf("-s          Use pre Shared keys\n");
+    printf("-t          Track wolfSSL memory use\n");
+    printf("-u          Use UDP DTLS,"
+           " add -v 2 for DTLSv1 (default), -v 3 for DTLSv1.2\n");
+    printf("-f          Fewer packets/group messages\n");
+    printf("-R          Create server ready file, for external monitor\n");
+    printf("-r          Allow one client Resumption\n");
+    printf("-N          Use Non-blocking sockets\n");
+    printf("-S     Use Host Name Indication\n");
+    printf("-w          Wait for bidirectional shutdown\n");
+#ifdef HAVE_OCSP
+    printf("-o          Perform OCSP lookup on peer certificate\n");
+    printf("-O     Perform OCSP lookup using  as responder\n");
+#endif
+#ifdef HAVE_PK_CALLBACKS 
+    printf("-P          Public Key Callbacks\n");
+#endif
+#ifdef HAVE_ANON
+    printf("-a          Anonymous server\n");
+#endif
+}
+
+THREAD_RETURN CYASSL_THREAD server_test(void* args)
+{
+    SOCKET_T sockfd   = 0;
+    SOCKET_T clientfd = 0;
+
+    SSL_METHOD* method = 0;
+    SSL_CTX*    ctx    = 0;
+    SSL*        ssl    = 0;
+
+    char   msg[] = "I hear you fa shizzle!";
+    char   input[80];
+    int    idx;
+    int    ch;
+    int    version = SERVER_DEFAULT_VERSION;
+    int    doCliCertCheck = 1;
+    int    useAnyAddr = 0;
+    word16 port = yasslPort;
+    int    usePsk = 0;
+    int    useAnon = 0;
+    int    doDTLS = 0;
+    int    needDH = 0;
+    int    useNtruKey   = 0;
+    int    nonBlocking  = 0;
+    int    trackMemory  = 0;
+    int    fewerPackets = 0;
+    int    pkCallbacks  = 0;
+    int    serverReadyFile = 0;
+    int    wc_shutdown     = 0;
+    int    resume = 0;            /* do resume, and resume count */
+    int    minDhKeyBits = DEFAULT_MIN_DHKEY_BITS;
+    int    ret;
+    char*  cipherList = NULL;
+    const char* verifyCert = cliCert;
+    const char* ourCert    = svrCert;
+    const char* ourKey     = svrKey;
+    const char* ourDhParam = dhParam;
+    int    argc = ((func_args*)args)->argc;
+    char** argv = ((func_args*)args)->argv;
+
+#ifdef HAVE_SNI
+    char*  sniHostName = NULL;
+#endif
+
+#ifdef HAVE_OCSP
+    int    useOcsp  = 0;
+    char*  ocspUrl  = NULL;
+#endif
+
+    ((func_args*)args)->return_code = -1; /* error state */
+
+#ifdef NO_RSA
+    verifyCert = (char*)cliEccCert;
+    ourCert    = (char*)eccCert;
+    ourKey     = (char*)eccKey;
+#endif
+    (void)trackMemory;
+    (void)pkCallbacks;
+    (void)needDH;
+    (void)ourKey;
+    (void)ourCert;
+    (void)ourDhParam;
+    (void)verifyCert;
+    (void)useNtruKey;
+    (void)doCliCertCheck;
+    (void)minDhKeyBits;
+
+#ifdef CYASSL_TIRTOS
+    fdOpenSession(Task_self());
+#endif
+
+    while ((ch = mygetopt(argc, argv, "?dbstnNufrRawPp:v:l:A:c:k:Z:S:oO:D:"))
+                         != -1) {
+        switch (ch) {
+            case '?' :
+                Usage();
+                exit(EXIT_SUCCESS);
+
+            case 'd' :
+                doCliCertCheck = 0;
+                break;
+
+            case 'b' :
+                useAnyAddr = 1;
+                break;
+
+            case 's' :
+                usePsk = 1;
+                break;
+
+            case 't' :
+            #ifdef USE_WOLFSSL_MEMORY
+                trackMemory = 1;
+            #endif
+                break;
+
+            case 'n' :
+                useNtruKey = 1;
+                break;
+
+            case 'u' :
+                doDTLS  = 1;
+                break;
+
+            case 'f' :
+                fewerPackets = 1;
+                break;
+
+            case 'R' :
+                serverReadyFile = 1;
+                break;
+
+            case 'r' :
+                #ifndef NO_SESSION_CACHE
+                    resume = 1;
+                #endif
+                break;
+
+            case 'P' :
+            #ifdef HAVE_PK_CALLBACKS 
+                pkCallbacks = 1;
+            #endif
+                break;
+
+            case 'p' :
+                port = (word16)atoi(myoptarg);
+                #if !defined(NO_MAIN_DRIVER) || defined(USE_WINDOWS_API)
+                    if (port == 0)
+                        err_sys("port number cannot be 0");
+                #endif
+                break;
+
+            case 'w' :
+                wc_shutdown = 1;
+                break;
+
+            case 'v' :
+                version = atoi(myoptarg);
+                if (version < 0 || version > 3) {
+                    Usage();
+                    exit(MY_EX_USAGE);
+                }
+                break;
+
+            case 'l' :
+                cipherList = myoptarg;
+                break;
+
+            case 'A' :
+                verifyCert = myoptarg;
+                break;
+
+            case 'c' :
+                ourCert = myoptarg;
+                break;
+
+            case 'k' :
+                ourKey = myoptarg;
+                break;
+
+            case 'D' :
+                #ifndef NO_DH
+                    ourDhParam = myoptarg;
+                #endif
+                break;
+
+            case 'Z' :
+                #ifndef NO_DH
+                    minDhKeyBits = atoi(myoptarg);
+                    if (minDhKeyBits <= 0 || minDhKeyBits > 16000) {
+                        Usage();
+                        exit(MY_EX_USAGE);
+                    }
+                #endif
+                break;
+
+            case 'N':
+                nonBlocking = 1;
+                break;
+
+            case 'S' :
+                #ifdef HAVE_SNI
+                    sniHostName = myoptarg;
+                #endif
+                break;
+
+            case 'o' :
+                #ifdef HAVE_OCSP
+                    useOcsp = 1;
+                #endif
+                break;
+
+            case 'O' :
+                #ifdef HAVE_OCSP
+                    useOcsp = 1;
+                    ocspUrl = myoptarg;
+                #endif
+                break;
+
+            case 'a' :
+                #ifdef HAVE_ANON
+                    useAnon = 1;
+                #endif
+                break;
+
+            default:
+                Usage();
+                exit(MY_EX_USAGE);
+        }
+    }
+
+    myoptind = 0;      /* reset for test cases */
+
+    /* sort out DTLS versus TLS versions */
+    if (version == CLIENT_INVALID_VERSION) {
+        if (doDTLS)
+            version = CLIENT_DTLS_DEFAULT_VERSION;
+        else
+            version = CLIENT_DEFAULT_VERSION;
+    }
+    else {
+        if (doDTLS) {
+            if (version == 3)
+                version = -2;
+            else
+                version = -1;
+        }
+    }
+
+#ifdef USE_CYASSL_MEMORY
+    if (trackMemory)
+        InitMemoryTracker(); 
+#endif
+
+    switch (version) {
+#ifndef NO_OLD_TLS
+        case 0:
+            method = SSLv3_server_method();
+            break;
+
+    #ifndef NO_TLS
+        case 1:
+            method = TLSv1_server_method();
+            break;
+
+
+        case 2:
+            method = TLSv1_1_server_method();
+            break;
+
+        #endif
+#endif
+
+#ifndef NO_TLS
+        case 3:
+            method = TLSv1_2_server_method();
+            break;
+#endif
+                
+#ifdef CYASSL_DTLS
+    #ifndef NO_OLD_TLS
+        case -1:
+            method = DTLSv1_server_method();
+            break;
+    #endif
+
+        case -2:
+            method = DTLSv1_2_server_method();
+            break;
+#endif
+
+        default:
+            err_sys("Bad SSL version");
+    }
+
+    if (method == NULL)
+        err_sys("unable to get method");
+
+    ctx = SSL_CTX_new(method);
+    if (ctx == NULL)
+        err_sys("unable to get ctx");
+
+#if defined(HAVE_SESSION_TICKET) && defined(HAVE_CHACHA) && \
+                                    defined(HAVE_POLY1305)
+    if (TicketInit() != 0)
+        err_sys("unable to setup Session Ticket Key context");
+    wolfSSL_CTX_set_TicketEncCb(ctx, myTicketEncCb);
+#endif
+
+    if (cipherList)
+        if (SSL_CTX_set_cipher_list(ctx, cipherList) != SSL_SUCCESS)
+            err_sys("server can't set cipher list 1");
+
+#ifdef CYASSL_LEANPSK
+    usePsk = 1;
+#endif
+
+#if defined(NO_RSA) && !defined(HAVE_ECC)
+    usePsk = 1;
+#endif
+
+    if (fewerPackets)
+        CyaSSL_CTX_set_group_messages(ctx);
+
+#if defined(OPENSSL_EXTRA) || defined(HAVE_WEBSERVER)
+    SSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack);
+#endif
+
+#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS)
+    if (!usePsk && !useAnon) {
+        if (SSL_CTX_use_certificate_file(ctx, ourCert, SSL_FILETYPE_PEM)
+                                         != SSL_SUCCESS)
+            err_sys("can't load server cert file, check file and run from"
+                    " wolfSSL home dir");
+    }
+#endif
+
+#ifndef NO_DH
+    wolfSSL_CTX_SetMinDhKey_Sz(ctx, (word16)minDhKeyBits);
+#endif
+
+#ifdef HAVE_NTRU
+    if (useNtruKey) {
+        if (CyaSSL_CTX_use_NTRUPrivateKey_file(ctx, ourKey)
+                                               != SSL_SUCCESS)
+            err_sys("can't load ntru key file, "
+                    "Please run from wolfSSL home dir");
+    }
+#endif
+
+#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS)
+    if (!useNtruKey && !usePsk && !useAnon) {
+        if (SSL_CTX_use_PrivateKey_file(ctx, ourKey, SSL_FILETYPE_PEM)
+                                         != SSL_SUCCESS)
+            err_sys("can't load server private key file, check file and run "
+                "from wolfSSL home dir");
+    }
+#endif
+
+    if (usePsk) {
+#ifndef NO_PSK
+        SSL_CTX_set_psk_server_callback(ctx, my_psk_server_cb);
+        SSL_CTX_use_psk_identity_hint(ctx, "cyassl server");
+        if (cipherList == NULL) {
+            const char *defaultCipherList;
+            #if defined(HAVE_AESGCM) && !defined(NO_DH)
+                defaultCipherList = "DHE-PSK-AES128-GCM-SHA256";
+                needDH = 1;
+            #elif defined(HAVE_NULL_CIPHER)
+                defaultCipherList = "PSK-NULL-SHA256";
+            #else
+                defaultCipherList = "PSK-AES128-CBC-SHA256";
+            #endif
+            if (SSL_CTX_set_cipher_list(ctx, defaultCipherList) != SSL_SUCCESS)
+                err_sys("server can't set cipher list 2");
+        }
+#endif
+    }
+
+    if (useAnon) {
+#ifdef HAVE_ANON
+        CyaSSL_CTX_allow_anon_cipher(ctx);
+        if (cipherList == NULL) {
+            if (SSL_CTX_set_cipher_list(ctx, "ADH-AES128-SHA") != SSL_SUCCESS)
+                err_sys("server can't set cipher list 4");
+        }
+#endif
+    }
+
+#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS)
+    /* if not using PSK, verify peer with certs */
+    if (doCliCertCheck && usePsk == 0 && useAnon == 0) {
+        SSL_CTX_set_verify(ctx, SSL_VERIFY_PEER |
+                                SSL_VERIFY_FAIL_IF_NO_PEER_CERT,0);
+        if (SSL_CTX_load_verify_locations(ctx, verifyCert, 0) != SSL_SUCCESS)
+            err_sys("can't load ca file, Please run from wolfSSL home dir");
+    }
+#endif
+
+#if defined(CYASSL_SNIFFER)
+    /* don't use EDH, can't sniff tmp keys */
+    if (cipherList == NULL) {
+        if (SSL_CTX_set_cipher_list(ctx, "AES256-SHA256") != SSL_SUCCESS)
+            err_sys("server can't set cipher list 3");
+    }
+#endif
+
+#ifdef HAVE_SNI
+    if (sniHostName)
+        if (CyaSSL_CTX_UseSNI(ctx, CYASSL_SNI_HOST_NAME, sniHostName,
+                                           XSTRLEN(sniHostName)) != SSL_SUCCESS)
+            err_sys("UseSNI failed");
+#endif
+
+while (1) {  /* allow resume option */
+    if (resume > 1) {  /* already did listen, just do accept */
+        if (doDTLS == 0) {
+            SOCKADDR_IN_T client;
+            socklen_t client_len = sizeof(client);
+            clientfd = accept(sockfd, (struct sockaddr*)&client,
+                             (ACCEPT_THIRD_T)&client_len);
+        } else {
+            tcp_listen(&sockfd, &port, useAnyAddr, doDTLS);
+            clientfd = udp_read_connect(sockfd);
+        }
+        #ifdef USE_WINDOWS_API
+            if (clientfd == INVALID_SOCKET) err_sys("tcp accept failed");
+        #else
+            if (clientfd == -1) err_sys("tcp accept failed");
+        #endif
+    }
+
+    ssl = SSL_new(ctx);
+    if (ssl == NULL)
+        err_sys("unable to get SSL");
+
+#ifndef NO_HANDSHAKE_DONE_CB
+    wolfSSL_SetHsDoneCb(ssl, myHsDoneCb, NULL);
+#endif
+#ifdef HAVE_CRL
+    CyaSSL_EnableCRL(ssl, 0);
+    CyaSSL_LoadCRL(ssl, crlPemDir, SSL_FILETYPE_PEM, CYASSL_CRL_MONITOR |
+                                                     CYASSL_CRL_START_MON);
+    CyaSSL_SetCRL_Cb(ssl, CRL_CallBack);
+#endif
+#ifdef HAVE_OCSP
+    if (useOcsp) {
+        if (ocspUrl != NULL) {
+            CyaSSL_CTX_SetOCSP_OverrideURL(ctx, ocspUrl);
+            CyaSSL_CTX_EnableOCSP(ctx, CYASSL_OCSP_NO_NONCE
+                                                    | CYASSL_OCSP_URL_OVERRIDE);
+        }
+        else
+            CyaSSL_CTX_EnableOCSP(ctx, CYASSL_OCSP_NO_NONCE);
+    }
+#endif
+#ifdef HAVE_PK_CALLBACKS
+    if (pkCallbacks)
+        SetupPkCallbacks(ctx, ssl);
+#endif
+
+    if (resume < 2) {  /* do listen and accept */
+        tcp_accept(&sockfd, &clientfd, (func_args*)args, port, useAnyAddr,
+                   doDTLS, serverReadyFile);
+    }
+
+    SSL_set_fd(ssl, clientfd);
+    if (usePsk == 0 || useAnon == 1 || cipherList != NULL || needDH == 1) {
+        #if !defined(NO_FILESYSTEM) && !defined(NO_DH) && !defined(NO_ASN)
+            CyaSSL_SetTmpDH_file(ssl, ourDhParam, SSL_FILETYPE_PEM);
+        #elif !defined(NO_DH)
+            SetDH(ssl);  /* repick suites with DHE, higher priority than PSK */
+        #endif
+    }
+
+#ifndef CYASSL_CALLBACKS
+    if (nonBlocking) {
+        CyaSSL_set_using_nonblock(ssl, 1);
+        tcp_set_nonblocking(&clientfd);
+        NonBlockingSSL_Accept(ssl);
+    } else if (SSL_accept(ssl) != SSL_SUCCESS) {
+        int err = SSL_get_error(ssl, 0);
+        char buffer[CYASSL_MAX_ERROR_SZ];
+        printf("error = %d, %s\n", err, ERR_error_string(err, buffer));
+        err_sys("SSL_accept failed");
+    }
+#else
+    NonBlockingSSL_Accept(ssl);
+#endif
+    showPeer(ssl);
+
+    idx = SSL_read(ssl, input, sizeof(input)-1);
+    if (idx > 0) {
+        input[idx] = 0;
+        printf("Client message: %s\n", input);
+
+    }
+    else if (idx < 0) {
+        int readErr = SSL_get_error(ssl, 0);
+        if (readErr != SSL_ERROR_WANT_READ)
+            err_sys("SSL_read failed");
+    }
+
+    if (SSL_write(ssl, msg, sizeof(msg)) != sizeof(msg))
+        err_sys("SSL_write failed");
+        
+    #if defined(CYASSL_MDK_SHELL) && defined(HAVE_MDK_RTX)
+        os_dly_wait(500) ;
+    #elif defined (CYASSL_TIRTOS)
+        Task_yield();
+    #endif
+
+    if (doDTLS == 0) {
+        ret = SSL_shutdown(ssl);
+        if (wc_shutdown && ret == SSL_SHUTDOWN_NOT_DONE)
+            SSL_shutdown(ssl);    /* bidirectional shutdown */
+    }
+    SSL_free(ssl);
+    if (resume == 1) {
+        CloseSocket(clientfd);
+        resume++;           /* only do one resume for testing */
+        continue;
+    }
+    break;  /* out of while loop, done with normal and resume option */
+}
+    SSL_CTX_free(ctx);
+
+    CloseSocket(clientfd);
+    CloseSocket(sockfd);
+    ((func_args*)args)->return_code = 0;
+
+
+#if defined(NO_MAIN_DRIVER) && defined(HAVE_ECC) && defined(FP_ECC) \
+                            && defined(HAVE_THREAD_LS)
+    ecc_fp_free();  /* free per thread cache */
+#endif
+
+#ifdef USE_WOLFSSL_MEMORY
+    if (trackMemory)
+        ShowMemoryTracker();
+#endif
+
+#ifdef CYASSL_TIRTOS
+    fdCloseSession(Task_self());
+#endif
+
+#if defined(HAVE_SESSION_TICKET) && defined(HAVE_CHACHA) && \
+                                    defined(HAVE_POLY1305)
+    TicketCleanup();
+#endif
+
+#ifndef CYASSL_TIRTOS
+    return 0;
+#endif
+}
+
+
+/* so overall tests can pull in test function */
+#ifndef NO_MAIN_DRIVER
+
+    int main(int argc, char** argv)
+    {
+        func_args args;
+
+#ifdef HAVE_CAVIUM
+        int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID);
+        if (ret != 0)
+            err_sys("Cavium OpenNitroxDevice failed");
+#endif /* HAVE_CAVIUM */
+
+        StartTCP();
+
+        args.argc = argc;
+        args.argv = argv;
+
+        CyaSSL_Init();
+#if defined(DEBUG_CYASSL) && !defined(CYASSL_MDK_SHELL)
+        CyaSSL_Debugging_ON();
+#endif
+        if (CurrentDir("_build"))
+            ChangeDirBack(1);
+        else if (CurrentDir("server"))
+            ChangeDirBack(2);
+        else if (CurrentDir("Debug") || CurrentDir("Release"))
+            ChangeDirBack(3);
+   
+#ifdef HAVE_STACK_SIZE
+        StackSizeCheck(&args, server_test);
+#else 
+        server_test(&args);
+#endif
+        CyaSSL_Cleanup();
+
+#ifdef HAVE_CAVIUM
+        CspShutdown(CAVIUM_DEV_ID);
+#endif
+        return args.return_code;
+    }
+
+    int myoptind = 0;
+    char* myoptarg = NULL;
+
+#endif /* NO_MAIN_DRIVER */
+
+
+#ifdef CYASSL_CALLBACKS
+
+    int srvHandShakeCB(HandShakeInfo* info)
+    {
+        (void)info;
+        return 0;
+    }
+
+
+    int srvTimeoutCB(TimeoutInfo* info)
+    {
+        (void)info;
+        return 0;
+    }
+
+#endif
+
+#ifndef NO_HANDSHAKE_DONE_CB
+    int myHsDoneCb(WOLFSSL* ssl, void* user_ctx)
+    {
+        (void)user_ctx;
+        (void)ssl;
+
+        /* printf("Notified HandShake done\n"); */
+
+        /* return negative number to end TLS connection now */
+        return 0;
+    }
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/server/server.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/server/server.h
new file mode 100644
index 0000000..c42260f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/server/server.h
@@ -0,0 +1,24 @@
+/* server.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#pragma once
+
+THREAD_RETURN WOLFSSL_THREAD server_test(void* args);
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/server/server.sln b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/server/server.sln
new file mode 100644
index 0000000..7c9de30
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/server/server.sln
@@ -0,0 +1,20 @@
+
+Microsoft Visual Studio Solution File, Format Version 9.00
+# Visual C++ Express 2005
+Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "server", "server.vcproj", "{13A60276-EFB2-4D3F-AFC3-D66E4C4CC27B}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|Win32 = Debug|Win32
+		Release|Win32 = Release|Win32
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{13A60276-EFB2-4D3F-AFC3-D66E4C4CC27B}.Debug|Win32.ActiveCfg = Debug|Win32
+		{13A60276-EFB2-4D3F-AFC3-D66E4C4CC27B}.Debug|Win32.Build.0 = Debug|Win32
+		{13A60276-EFB2-4D3F-AFC3-D66E4C4CC27B}.Release|Win32.ActiveCfg = Release|Win32
+		{13A60276-EFB2-4D3F-AFC3-D66E4C4CC27B}.Release|Win32.Build.0 = Release|Win32
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/server/server.vcproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/server/server.vcproj
new file mode 100644
index 0000000..ebb1af4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/server/server.vcproj
@@ -0,0 +1,197 @@
+
+
+	
+		
+	
+	
+	
+	
+		
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+		
+		
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+		
+	
+	
+	
+	
+		
+			
+			
+		
+		
+		
+		
+		
+	
+	
+	
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/server/server.vcxproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/server/server.vcxproj
new file mode 100644
index 0000000..f6b53fc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/examples/server/server.vcxproj
@@ -0,0 +1,334 @@
+
+
+  
+    
+      Debug
+      Win32
+    
+    
+      Debug
+      x64
+    
+    
+      DLL Debug
+      Win32
+    
+    
+      DLL Debug
+      x64
+    
+    
+      DLL Release
+      Win32
+    
+    
+      DLL Release
+      x64
+    
+    
+      Release
+      Win32
+    
+    
+      Release
+      x64
+    
+  
+  
+    {E9FB0BA5-BA46-4A59-A953-39C18CD1DCB1}
+    server
+    Win32Proj
+  
+  
+  
+    Application
+    v110
+    Unicode
+    true
+  
+  
+    Application
+    v110
+    Unicode
+    true
+  
+  
+    Application
+    v110
+    Unicode
+    true
+  
+  
+    Application
+    v110
+    Unicode
+    true
+  
+  
+    Application
+    v110
+    Unicode
+  
+  
+    Application
+    v110
+    Unicode
+  
+  
+    Application
+    v110
+    Unicode
+  
+  
+    Application
+    v110
+    Unicode
+  
+  
+  
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+  
+    <_ProjectFileVersion>11.0.61030.0
+  
+  
+    $(SolutionDir)$(Configuration)\
+    $(Configuration)\obj\
+    true
+  
+  
+    $(SolutionDir)$(Configuration)\
+    $(Configuration)\obj\
+    true
+  
+  
+    true
+    $(SolutionDir)$(Platform)\$(Configuration)\
+    $(Platform)\$(Configuration)\obj\
+  
+  
+    true
+    $(SolutionDir)$(Platform)\$(Configuration)\
+    $(Platform)\$(Configuration)\obj\
+  
+  
+    $(SolutionDir)$(Configuration)\
+    $(Configuration)\obj\
+    false
+  
+  
+    $(SolutionDir)$(Configuration)\
+    $(Configuration)\obj\
+    false
+  
+  
+    false
+    $(SolutionDir)$(Platform)\$(Configuration)\
+    $(Platform)\$(Configuration)\obj\
+  
+  
+    false
+    $(SolutionDir)$(Platform)\$(Configuration)\
+    $(Platform)\$(Configuration)\obj\
+  
+  
+    
+      Disabled
+      ../../;%(AdditionalIncludeDirectories)
+      WIN32;_DEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;%(PreprocessorDefinitions)
+      true
+      EnableFastChecks
+      MultiThreadedDebugDLL
+      
+      Level3
+      EditAndContinue
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+      MachineX86
+      false
+
+    
+  
+  
+    
+      Disabled
+      ../../;%(AdditionalIncludeDirectories)
+      WIN32;_DEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;WOLFSSL_DLL;%(PreprocessorDefinitions)
+      true
+      EnableFastChecks
+      MultiThreadedDebugDLL
+      
+      
+      Level3
+      EditAndContinue
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+      MachineX86
+    
+  
+  
+    
+      Disabled
+      ../../;%(AdditionalIncludeDirectories)
+      WIN32;_DEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;%(PreprocessorDefinitions)
+      EnableFastChecks
+      MultiThreadedDebugDLL
+      
+      
+      Level3
+      ProgramDatabase
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+    
+  
+  
+    
+      Disabled
+      ../../;%(AdditionalIncludeDirectories)
+      WIN32;_DEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;WOLFSSL_DLL;%(PreprocessorDefinitions)
+      EnableFastChecks
+      MultiThreadedDebugDLL
+      
+      
+      Level3
+      ProgramDatabase
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+    
+  
+  
+    
+      MaxSpeed
+      true
+      ../../;%(AdditionalIncludeDirectories)
+      WIN32;NDEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;%(PreprocessorDefinitions)
+      MultiThreadedDLL
+      true
+      
+      Level3
+      ProgramDatabase
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+      true
+      true
+      MachineX86
+      false
+
+    
+  
+  
+    
+      MaxSpeed
+      true
+      ../../;%(AdditionalIncludeDirectories)
+      WIN32;NDEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;WOLFSSL_DLL;%(PreprocessorDefinitions)
+      MultiThreadedDLL
+      true
+      
+      
+      Level3
+      ProgramDatabase
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+      true
+      true
+      MachineX86
+    
+  
+  
+    
+      MaxSpeed
+      true
+      ../../;%(AdditionalIncludeDirectories)
+      WIN32;NDEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;%(PreprocessorDefinitions)
+      MultiThreadedDLL
+      true
+      
+      
+      Level3
+      ProgramDatabase
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+      true
+      true
+    
+  
+  
+    
+      MaxSpeed
+      true
+      ../../;%(AdditionalIncludeDirectories)
+      WIN32;NDEBUG;_CONSOLE;OPENSSL_EXTRA;NO_PSK;WOLFSSL_DLL;%(PreprocessorDefinitions)
+      MultiThreadedDLL
+      true
+      
+      
+      Level3
+      ProgramDatabase
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+      true
+      true
+    
+  
+  
+    
+  
+  
+    
+      {73973223-5ee8-41ca-8e88-1d60e89a237b}
+      false
+    
+  
+  
+  
+  
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/gencertbuf.pl b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/gencertbuf.pl
new file mode 100644
index 0000000..d3d1166
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/gencertbuf.pl
@@ -0,0 +1,145 @@
+#!/usr/bin/perl
+
+# gencertbuf.pl
+# version 1.1
+# Updated 07/01/2014
+#
+# Copyright (C) 2006-2015 wolfSSL Inc.
+#
+
+use strict;
+use warnings;
+
+# ---- SCRIPT SETTINGS -------------------------------------------------------
+
+# output C header file to write cert/key buffers to
+my $outputFile = "./wolfssl/certs_test.h";
+
+# 1024-bit certs/keys to be converted
+# Used with USE_CERT_BUFFERS_1024 define.
+
+my @fileList_1024 = (
+        [ "./certs/1024/client-key.der", "client_key_der_1024" ],
+        [ "./certs/1024/client-cert.der", "client_cert_der_1024" ],
+        [ "./certs/1024/dh1024.der", "dh_key_der_1024" ],
+        [ "./certs/1024/dsa1024.der", "dsa_key_der_1024" ],
+        [ "./certs/1024/rsa1024.der", "rsa_key_der_1024" ]
+        );
+
+# 2048-bit certs/keys to be converted
+# Used with USE_CERT_BUFFERS_2048 define.
+
+my @fileList_2048 = (
+        [ "./certs/client-key.der", "client_key_der_2048" ],
+        [ "./certs/client-cert.der", "client_cert_der_2048" ],
+        [ "./certs/dh2048.der", "dh_key_der_2048" ],
+        [ "./certs/dsa2048.der", "dsa_key_der_2048" ],
+        [ "./certs/rsa2048.der", "rsa_key_der_2048" ],
+        [ "./certs/ca-cert.der", "ca_cert_der_2048" ],
+        [ "./certs/server-key.der", "server_key_der_2048" ],
+        [ "./certs/server-cert.der", "server_cert_der_2048" ]
+        );
+
+# ----------------------------------------------------------------------------
+
+my $num_1024 = @fileList_1024;
+my $num_2048 = @fileList_2048;
+
+# open our output file, "+>" creates and/or truncates
+open OUT_FILE, "+>", $outputFile  or die $!;
+
+print OUT_FILE "/* certs_test.h */\n\n";
+print OUT_FILE "#ifndef WOLFSSL_CERTS_TEST_H\n";
+print OUT_FILE "#define WOLFSSL_CERTS_TEST_H\n\n";
+
+# convert and print 1024-bit cert/keys
+print OUT_FILE "#ifdef USE_CERT_BUFFERS_1024\n\n";
+for (my $i = 0; $i < $num_1024; $i++) {
+
+    my $fname = $fileList_1024[$i][0];
+    my $sname = $fileList_1024[$i][1];
+
+    print OUT_FILE "/* $fname, 1024-bit */\n";
+    print OUT_FILE "static const unsigned char $sname\[] =\n";
+    print OUT_FILE "{\n";
+    file_to_hex($fname);
+    print OUT_FILE "};\n";
+    print OUT_FILE "static const int sizeof_$sname = sizeof($sname);\n\n";
+}
+
+# convert and print 2048-bit certs/keys
+print OUT_FILE "#elif defined(USE_CERT_BUFFERS_2048)\n\n";
+for (my $i = 0; $i < $num_2048; $i++) {
+
+    my $fname = $fileList_2048[$i][0];
+    my $sname = $fileList_2048[$i][1];
+
+    print OUT_FILE "/* $fname, 2048-bit */\n";
+    print OUT_FILE "static const unsigned char $sname\[] =\n";
+    print OUT_FILE "{\n";
+    file_to_hex($fname);
+    print OUT_FILE "};\n";
+    print OUT_FILE "static const int sizeof_$sname = sizeof($sname);\n\n";
+}
+
+print OUT_FILE "#endif /* USE_CERT_BUFFERS_1024 */\n\n";
+print OUT_FILE "/* dh1024 p */
+static const unsigned char dh_p[] =
+{
+    0xE6, 0x96, 0x9D, 0x3D, 0x49, 0x5B, 0xE3, 0x2C, 0x7C, 0xF1, 0x80, 0xC3,
+    0xBD, 0xD4, 0x79, 0x8E, 0x91, 0xB7, 0x81, 0x82, 0x51, 0xBB, 0x05, 0x5E,
+    0x2A, 0x20, 0x64, 0x90, 0x4A, 0x79, 0xA7, 0x70, 0xFA, 0x15, 0xA2, 0x59,
+    0xCB, 0xD5, 0x23, 0xA6, 0xA6, 0xEF, 0x09, 0xC4, 0x30, 0x48, 0xD5, 0xA2,
+    0x2F, 0x97, 0x1F, 0x3C, 0x20, 0x12, 0x9B, 0x48, 0x00, 0x0E, 0x6E, 0xDD,
+    0x06, 0x1C, 0xBC, 0x05, 0x3E, 0x37, 0x1D, 0x79, 0x4E, 0x53, 0x27, 0xDF,
+    0x61, 0x1E, 0xBB, 0xBE, 0x1B, 0xAC, 0x9B, 0x5C, 0x60, 0x44, 0xCF, 0x02,
+    0x3D, 0x76, 0xE0, 0x5E, 0xEA, 0x9B, 0xAD, 0x99, 0x1B, 0x13, 0xA6, 0x3C,
+    0x97, 0x4E, 0x9E, 0xF1, 0x83, 0x9E, 0xB5, 0xDB, 0x12, 0x51, 0x36, 0xF7,
+    0x26, 0x2E, 0x56, 0xA8, 0x87, 0x15, 0x38, 0xDF, 0xD8, 0x23, 0xC6, 0x50,
+    0x50, 0x85, 0xE2, 0x1F, 0x0D, 0xD5, 0xC8, 0x6B,
+};
+
+/* dh1024 g */
+static const unsigned char dh_g[] =
+{
+  0x02,
+};\n\n\n";
+print OUT_FILE "#endif /* WOLFSSL_CERTS_TEST_H */\n\n";
+
+# close certs_test.h file
+close OUT_FILE or die $!;
+
+# print file as hex, comma-separated, as needed by C buffer
+sub file_to_hex {
+    my $fileName = $_[0];
+
+    open my $fp, "<", $fileName or die $!;
+    binmode($fp);
+
+    my $fileLen = -s $fileName;
+    my $byte;
+
+    for (my $i = 0, my $j = 1; $i < $fileLen; $i++, $j++)
+    {
+        if ($j == 1) {
+            print OUT_FILE "\t";
+        }
+        read($fp, $byte, 1) or die "Error reading $fileName";
+        my $output = sprintf("0x%02X", ord($byte));
+        print OUT_FILE $output;
+
+        if ($i != ($fileLen - 1)) {
+            print OUT_FILE ", ";
+        }
+
+        if ($j == 10) {
+            $j = 0;
+            print OUT_FILE "\n";
+        }
+    }
+
+    print OUT_FILE "\n";
+
+    close($fp); 
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/input b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/input
new file mode 100644
index 0000000..06dbbf0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/input
@@ -0,0 +1,87 @@
+/* echoclient.c  */
+
+#include "openssl/ssl.h"
+#include "../test.h"
+
+
+int main(int argc, char** argv)
+{
+    SOCKET_T sockfd = 0;
+
+    FILE* fin  = stdin;
+    FILE* fout = stdout;
+
+    int inCreated  = 0;
+    int outCreated = 0;
+
+    char send[1024];
+    char reply[1024];
+
+    SSL_METHOD* method = 0;
+    SSL_CTX*    ctx    = 0;
+    SSL*        ssl    = 0;
+
+#ifdef _WIN32
+    WSADATA wsd;
+    WSAStartup(0x0002, &wsd);
+#endif
+
+    if (argc >= 2) {
+        fin  = fopen(argv[1], "r"); 
+        inCreated = 1;
+    }
+    if (argc >= 3) {
+        fout = fopen(argv[2], "w");
+        outCreated = 1;
+    }
+
+    if (!fin)  err_sys("can't open input file");
+    if (!fout) err_sys("can't open output file");
+
+    tcp_connect(&sockfd);
+
+    method = SSLv3_client_method();
+    ctx    = SSL_CTX_new(method);
+
+    if (SSL_CTX_load_verify_locations(ctx, caCert, 0) != SSL_SUCCESS)
+        err_sys("can't load ca file");
+
+    ssl = SSL_new(ctx);
+
+    SSL_set_fd(ssl, sockfd);
+    if (SSL_connect(ssl) != SSL_SUCCESS) err_sys("SSL_connect failed");
+
+    while (fgets(send, sizeof(send), fin)) {
+
+        int  sendSz = strlen(send) + 1;
+
+        if (SSL_write(ssl, send, sendSz) != sendSz)
+            err_sys("SSL_write failed");
+
+        if (strncmp(send, "quit", 4) == 0) {
+            fputs("sending server shutdown command: quit!\n", fout);
+            break;
+        }
+
+        if (SSL_read(ssl, reply, sizeof(reply)) > 0) 
+            fputs(reply, fout);
+    }
+
+    SSL_shutdown(ssl);
+    SSL_free(ssl);
+    SSL_CTX_free(ctx);
+
+    fflush(fout);
+    if (inCreated)  fclose(fin);
+    if (outCreated) fclose(fout);
+
+#ifdef _WIN32
+    closesocket(sockfd);
+#else
+    close(sockfd);
+#endif
+
+    return 0;
+}
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/lib/dummy b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/lib/dummy
new file mode 100644
index 0000000..13c3b18
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/lib/dummy
@@ -0,0 +1,2 @@
+// this is a dummy file
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_add_am_macro.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_add_am_macro.m4
new file mode 100644
index 0000000..51ce0d0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_add_am_macro.m4
@@ -0,0 +1,29 @@
+# ===========================================================================
+#      http://www.gnu.org/software/autoconf-archive/ax_add_am_macro.html
+# ===========================================================================
+#
+# SYNOPSIS
+#
+#   AX_ADD_AM_MACRO([RULE])
+#
+# DESCRIPTION
+#
+#   Adds the specified rule to $AMINCLUDE. This macro will only work
+#   properly with implementations of Make which allow include statements.
+#   See also AX_ADD_AM_MACRO_STATIC.
+#
+# LICENSE
+#
+#   Copyright (c) 2009 Tom Howard 
+#
+#   Copying and distribution of this file, with or without modification, are
+#   permitted in any medium without royalty provided the copyright notice
+#   and this notice are preserved. This file is offered as-is, without any
+#   warranty.
+
+#serial 9
+
+AC_DEFUN([AX_ADD_AM_MACRO],[
+  AC_REQUIRE([AX_AM_MACROS])
+  AX_APPEND_TO_FILE([$AMINCLUDE],[$1])
+])
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_am_jobserver.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_am_jobserver.m4
new file mode 100644
index 0000000..5a398f8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_am_jobserver.m4
@@ -0,0 +1,54 @@
+# ===========================================================================
+#      http://www.gnu.org/software/autoconf-archive/ax_am_jobserver.html
+# ===========================================================================
+#
+# SYNOPSIS
+#
+#   AX_AM_JOBSERVER([default_value])
+#
+# DESCRIPTION
+#
+#   Enables the use of make's jobserver for the purpose of parallel building
+#   by passing the -j option to make.
+#
+#   The option --enable-jobserver is added to configure which can accept a
+#   yes, no, or an integer. The integer is the number of separate jobs to
+#   allow. If 'yes' is given, then the is assumed to be one more than the
+#   number of CPUs (determined through AX_COUNT_CPUS). If the value of no is
+#   given, then the jobserver is disabled. The default value is given by the
+#   first argument of the macro, or 'yes' if the argument is omitted.
+#
+#   This macro makes use of AX_AM_MACROS, so you must add the following line
+#
+#     @INC_AMINCLUDE@
+#
+#   to your Makefile.am files.
+#
+# LICENSE
+#
+#   Copyright (c) 2008 Michael Paul Bailey 
+#
+#   Copying and distribution of this file, with or without modification, are
+#   permitted in any medium without royalty provided the copyright notice
+#   and this notice are preserved. This file is offered as-is, without any
+#   warranty.
+
+#serial 7.1
+
+AC_DEFUN([AX_AM_JOBSERVER], [
+    AC_REQUIRE([AX_COUNT_CPUS])
+    AC_REQUIRE([AX_AM_MACROS])
+    AC_ARG_ENABLE( jobserver,
+    [  --enable-jobserver@<:@=no/yes/@%:@@:>@ default=m4_ifval([$1],[$1],[yes])
+                        Enable up to @%:@ make jobs
+                        yes: enable one more than CPU count
+    ],, [enable_jobserver=m4_ifval([$1],[$1],[yes])])
+    if test "x$enable_jobserver" = "xyes"; then
+        let enable_jobserver=$CPU_COUNT+1
+    fi
+    m4_pattern_allow(AM_MAKEFLAGS)
+    if test "x$enable_jobserver" != "xno"; then
+        AC_MSG_NOTICE([added jobserver support to make for $enable_jobserver jobs])
+        AX_ADD_AM_MACRO( AM_MAKEFLAGS += -j$enable_jobserver )
+    fi
+])
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_am_macros.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_am_macros.m4
new file mode 100644
index 0000000..6b4bd22
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_am_macros.m4
@@ -0,0 +1,44 @@
+# ===========================================================================
+#       http://www.gnu.org/software/autoconf-archive/ax_am_macros.html
+# ===========================================================================
+#
+# SYNOPSIS
+#
+#   AX_AM_MACROS
+#
+# DESCRIPTION
+#
+#   Adds support for macros that create Make rules. You must manually add
+#   the following line
+#
+#     @INC_AMINCLUDE@
+#
+#   to your Makefile.in (or Makefile.am if you use Automake) files.
+#
+# LICENSE
+#
+#   Copyright (c) 2009 Tom Howard 
+#
+#   Copying and distribution of this file, with or without modification, are
+#   permitted in any medium without royalty provided the copyright notice
+#   and this notice are preserved. This file is offered as-is, without any
+#   warranty.
+
+#serial 9
+
+AC_DEFUN([AX_AM_MACROS],
+[
+AC_MSG_NOTICE([adding automake macro support])
+AMINCLUDE="aminclude.am"
+AC_SUBST(AMINCLUDE)
+AC_MSG_NOTICE([creating $AMINCLUDE])
+AMINCLUDE_TIME=`date`
+AX_PRINT_TO_FILE([$AMINCLUDE],[[
+# generated automatically by configure from AX_AUTOMAKE_MACROS
+# on $AMINCLUDE_TIME
+
+]])
+
+INC_AMINCLUDE="include \$(top_builddir)/$AMINCLUDE"
+AC_SUBST(INC_AMINCLUDE)
+])
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_append_compile_flags.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_append_compile_flags.m4
new file mode 100644
index 0000000..1f8e708
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_append_compile_flags.m4
@@ -0,0 +1,65 @@
+# ===========================================================================
+#  http://www.gnu.org/software/autoconf-archive/ax_append_compile_flags.html
+# ===========================================================================
+#
+# SYNOPSIS
+#
+#   AX_APPEND_COMPILE_FLAGS([FLAG1 FLAG2 ...], [FLAGS-VARIABLE], [EXTRA-FLAGS])
+#
+# DESCRIPTION
+#
+#   For every FLAG1, FLAG2 it is checked whether the compiler works with the
+#   flag.  If it does, the flag is added FLAGS-VARIABLE
+#
+#   If FLAGS-VARIABLE is not specified, the current language's flags (e.g.
+#   CFLAGS) is used.  During the check the flag is always added to the
+#   current language's flags.
+#
+#   If EXTRA-FLAGS is defined, it is added to the current language's default
+#   flags (e.g. CFLAGS) when the check is done.  The check is thus made with
+#   the flags: "CFLAGS EXTRA-FLAGS FLAG".  This can for example be used to
+#   force the compiler to issue an error when a bad flag is given.
+#
+#   NOTE: This macro depends on the AX_APPEND_FLAG and
+#   AX_CHECK_COMPILE_FLAG. Please keep this macro in sync with
+#   AX_APPEND_LINK_FLAGS.
+#
+# LICENSE
+#
+#   Copyright (c) 2011 Maarten Bosmans 
+#
+#   This program is free software: you can redistribute it and/or modify it
+#   under the terms of the GNU General Public License as published by the
+#   Free Software Foundation, either version 3 of the License, or (at your
+#   option) any later version.
+#
+#   This program is distributed in the hope that it will be useful, but
+#   WITHOUT ANY WARRANTY; without even the implied warranty of
+#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
+#   Public License for more details.
+#
+#   You should have received a copy of the GNU General Public License along
+#   with this program. If not, see .
+#
+#   As a special exception, the respective Autoconf Macro's copyright owner
+#   gives unlimited permission to copy, distribute and modify the configure
+#   scripts that are the output of Autoconf when processing the Macro. You
+#   need not follow the terms of the GNU General Public License when using
+#   or distributing such scripts, even though portions of the text of the
+#   Macro appear in them. The GNU General Public License (GPL) does govern
+#   all other use of the material that constitutes the Autoconf Macro.
+#
+#   This special exception to the GPL applies to versions of the Autoconf
+#   Macro released by the Autoconf Archive. When you make and distribute a
+#   modified version of the Autoconf Macro, you may extend this special
+#   exception to the GPL to apply to your modified version as well.
+
+#serial 3
+
+AC_DEFUN([AX_APPEND_COMPILE_FLAGS],
+[AC_REQUIRE([AX_CHECK_COMPILE_FLAG])
+AC_REQUIRE([AX_APPEND_FLAG])
+for flag in $1; do
+  AX_CHECK_COMPILE_FLAG([$flag], [AX_APPEND_FLAG([$flag], [$2])], [], [$3])
+done
+])dnl AX_APPEND_COMPILE_FLAGS
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_append_flag.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_append_flag.m4
new file mode 100644
index 0000000..1d38b76
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_append_flag.m4
@@ -0,0 +1,69 @@
+# ===========================================================================
+#      http://www.gnu.org/software/autoconf-archive/ax_append_flag.html
+# ===========================================================================
+#
+# SYNOPSIS
+#
+#   AX_APPEND_FLAG(FLAG, [FLAGS-VARIABLE])
+#
+# DESCRIPTION
+#
+#   FLAG is appended to the FLAGS-VARIABLE shell variable, with a space
+#   added in between.
+#
+#   If FLAGS-VARIABLE is not specified, the current language's flags (e.g.
+#   CFLAGS) is used.  FLAGS-VARIABLE is not changed if it already contains
+#   FLAG.  If FLAGS-VARIABLE is unset in the shell, it is set to exactly
+#   FLAG.
+#
+#   NOTE: Implementation based on AX_CFLAGS_GCC_OPTION.
+#
+# LICENSE
+#
+#   Copyright (c) 2008 Guido U. Draheim 
+#   Copyright (c) 2011 Maarten Bosmans 
+#
+#   This program is free software: you can redistribute it and/or modify it
+#   under the terms of the GNU General Public License as published by the
+#   Free Software Foundation, either version 3 of the License, or (at your
+#   option) any later version.
+#
+#   This program is distributed in the hope that it will be useful, but
+#   WITHOUT ANY WARRANTY; without even the implied warranty of
+#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
+#   Public License for more details.
+#
+#   You should have received a copy of the GNU General Public License along
+#   with this program. If not, see .
+#
+#   As a special exception, the respective Autoconf Macro's copyright owner
+#   gives unlimited permission to copy, distribute and modify the configure
+#   scripts that are the output of Autoconf when processing the Macro. You
+#   need not follow the terms of the GNU General Public License when using
+#   or distributing such scripts, even though portions of the text of the
+#   Macro appear in them. The GNU General Public License (GPL) does govern
+#   all other use of the material that constitutes the Autoconf Macro.
+#
+#   This special exception to the GPL applies to versions of the Autoconf
+#   Macro released by the Autoconf Archive. When you make and distribute a
+#   modified version of the Autoconf Macro, you may extend this special
+#   exception to the GPL to apply to your modified version as well.
+
+#serial 2
+
+AC_DEFUN([AX_APPEND_FLAG],
+[AC_PREREQ(2.59)dnl for _AC_LANG_PREFIX
+AS_VAR_PUSHDEF([FLAGS], [m4_default($2,_AC_LANG_PREFIX[FLAGS])])dnl
+AS_VAR_SET_IF(FLAGS,
+  [case " AS_VAR_GET(FLAGS) " in
+    *" $1 "*)
+      AC_RUN_LOG([: FLAGS already contains $1])
+      ;;
+    *)
+      AC_RUN_LOG([: FLAGS="$FLAGS $1"])
+      AS_VAR_SET(FLAGS, ["AS_VAR_GET(FLAGS) $1"])
+      ;;
+   esac],
+  [AS_VAR_SET(FLAGS,["$1"])])
+AS_VAR_POPDEF([FLAGS])dnl
+])dnl AX_APPEND_FLAG
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_append_to_file.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_append_to_file.m4
new file mode 100644
index 0000000..f9f54e0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_append_to_file.m4
@@ -0,0 +1,27 @@
+# ===========================================================================
+#     http://www.gnu.org/software/autoconf-archive/ax_append_to_file.html
+# ===========================================================================
+#
+# SYNOPSIS
+#
+#   AX_APPEND_TO_FILE([FILE],[DATA])
+#
+# DESCRIPTION
+#
+#   Appends the specified data to the specified file.
+#
+# LICENSE
+#
+#   Copyright (c) 2008 Tom Howard 
+#
+#   Copying and distribution of this file, with or without modification, are
+#   permitted in any medium without royalty provided the copyright notice
+#   and this notice are preserved. This file is offered as-is, without any
+#   warranty.
+
+#serial 8
+
+AC_DEFUN([AX_APPEND_TO_FILE],[
+AC_REQUIRE([AX_FILE_ESCAPES])
+printf "$2\n" >> "$1"
+])
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_check_compile_flag.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_check_compile_flag.m4
new file mode 100644
index 0000000..c3a8d69
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_check_compile_flag.m4
@@ -0,0 +1,72 @@
+# ===========================================================================
+#   http://www.gnu.org/software/autoconf-archive/ax_check_compile_flag.html
+# ===========================================================================
+#
+# SYNOPSIS
+#
+#   AX_CHECK_COMPILE_FLAG(FLAG, [ACTION-SUCCESS], [ACTION-FAILURE], [EXTRA-FLAGS])
+#
+# DESCRIPTION
+#
+#   Check whether the given FLAG works with the current language's compiler
+#   or gives an error.  (Warnings, however, are ignored)
+#
+#   ACTION-SUCCESS/ACTION-FAILURE are shell commands to execute on
+#   success/failure.
+#
+#   If EXTRA-FLAGS is defined, it is added to the current language's default
+#   flags (e.g. CFLAGS) when the check is done.  The check is thus made with
+#   the flags: "CFLAGS EXTRA-FLAGS FLAG".  This can for example be used to
+#   force the compiler to issue an error when a bad flag is given.
+#
+#   NOTE: Implementation based on AX_CFLAGS_GCC_OPTION. Please keep this
+#   macro in sync with AX_CHECK_{PREPROC,LINK}_FLAG.
+#
+# LICENSE
+#
+#   Copyright (c) 2008 Guido U. Draheim 
+#   Copyright (c) 2011 Maarten Bosmans 
+#
+#   This program is free software: you can redistribute it and/or modify it
+#   under the terms of the GNU General Public License as published by the
+#   Free Software Foundation, either version 3 of the License, or (at your
+#   option) any later version.
+#
+#   This program is distributed in the hope that it will be useful, but
+#   WITHOUT ANY WARRANTY; without even the implied warranty of
+#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
+#   Public License for more details.
+#
+#   You should have received a copy of the GNU General Public License along
+#   with this program. If not, see .
+#
+#   As a special exception, the respective Autoconf Macro's copyright owner
+#   gives unlimited permission to copy, distribute and modify the configure
+#   scripts that are the output of Autoconf when processing the Macro. You
+#   need not follow the terms of the GNU General Public License when using
+#   or distributing such scripts, even though portions of the text of the
+#   Macro appear in them. The GNU General Public License (GPL) does govern
+#   all other use of the material that constitutes the Autoconf Macro.
+#
+#   This special exception to the GPL applies to versions of the Autoconf
+#   Macro released by the Autoconf Archive. When you make and distribute a
+#   modified version of the Autoconf Macro, you may extend this special
+#   exception to the GPL to apply to your modified version as well.
+
+#serial 2
+
+AC_DEFUN([AX_CHECK_COMPILE_FLAG],
+[AC_PREREQ(2.59)dnl for _AC_LANG_PREFIX
+AS_VAR_PUSHDEF([CACHEVAR],[ax_cv_check_[]_AC_LANG_ABBREV[]flags_$4_$1])dnl
+AC_CACHE_CHECK([whether _AC_LANG compiler accepts $1], CACHEVAR, [
+  ax_check_save_flags=$[]_AC_LANG_PREFIX[]FLAGS
+  _AC_LANG_PREFIX[]FLAGS="$[]_AC_LANG_PREFIX[]FLAGS $4 $1"
+  AC_COMPILE_IFELSE([AC_LANG_PROGRAM()],
+    [AS_VAR_SET(CACHEVAR,[yes])],
+    [AS_VAR_SET(CACHEVAR,[no])])
+  _AC_LANG_PREFIX[]FLAGS=$ax_check_save_flags])
+AS_IF([test x"AS_VAR_GET(CACHEVAR)" = xyes],
+  [m4_default([$2], :)],
+  [m4_default([$3], :)])
+AS_VAR_POPDEF([CACHEVAR])dnl
+])dnl AX_CHECK_COMPILE_FLAGS
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_check_link_flag.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_check_link_flag.m4
new file mode 100644
index 0000000..e2d0d36
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_check_link_flag.m4
@@ -0,0 +1,71 @@
+# ===========================================================================
+#    http://www.gnu.org/software/autoconf-archive/ax_check_link_flag.html
+# ===========================================================================
+#
+# SYNOPSIS
+#
+#   AX_CHECK_LINK_FLAG(FLAG, [ACTION-SUCCESS], [ACTION-FAILURE], [EXTRA-FLAGS])
+#
+# DESCRIPTION
+#
+#   Check whether the given FLAG works with the linker or gives an error.
+#   (Warnings, however, are ignored)
+#
+#   ACTION-SUCCESS/ACTION-FAILURE are shell commands to execute on
+#   success/failure.
+#
+#   If EXTRA-FLAGS is defined, it is added to the linker's default flags
+#   when the check is done.  The check is thus made with the flags: "LDFLAGS
+#   EXTRA-FLAGS FLAG".  This can for example be used to force the linker to
+#   issue an error when a bad flag is given.
+#
+#   NOTE: Implementation based on AX_CFLAGS_GCC_OPTION. Please keep this
+#   macro in sync with AX_CHECK_{PREPROC,COMPILE}_FLAG.
+#
+# LICENSE
+#
+#   Copyright (c) 2008 Guido U. Draheim 
+#   Copyright (c) 2011 Maarten Bosmans 
+#
+#   This program is free software: you can redistribute it and/or modify it
+#   under the terms of the GNU General Public License as published by the
+#   Free Software Foundation, either version 3 of the License, or (at your
+#   option) any later version.
+#
+#   This program is distributed in the hope that it will be useful, but
+#   WITHOUT ANY WARRANTY; without even the implied warranty of
+#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
+#   Public License for more details.
+#
+#   You should have received a copy of the GNU General Public License along
+#   with this program. If not, see .
+#
+#   As a special exception, the respective Autoconf Macro's copyright owner
+#   gives unlimited permission to copy, distribute and modify the configure
+#   scripts that are the output of Autoconf when processing the Macro. You
+#   need not follow the terms of the GNU General Public License when using
+#   or distributing such scripts, even though portions of the text of the
+#   Macro appear in them. The GNU General Public License (GPL) does govern
+#   all other use of the material that constitutes the Autoconf Macro.
+#
+#   This special exception to the GPL applies to versions of the Autoconf
+#   Macro released by the Autoconf Archive. When you make and distribute a
+#   modified version of the Autoconf Macro, you may extend this special
+#   exception to the GPL to apply to your modified version as well.
+
+#serial 2
+
+AC_DEFUN([AX_CHECK_LINK_FLAG],
+[AS_VAR_PUSHDEF([CACHEVAR],[ax_cv_check_ldflags_$4_$1])dnl
+AC_CACHE_CHECK([whether the linker accepts $1], CACHEVAR, [
+  ax_check_save_flags=$LDFLAGS
+  LDFLAGS="$LDFLAGS $4 $1"
+  AC_LINK_IFELSE([AC_LANG_PROGRAM()],
+    [AS_VAR_SET(CACHEVAR,[yes])],
+    [AS_VAR_SET(CACHEVAR,[no])])
+  LDFLAGS=$ax_check_save_flags])
+AS_IF([test x"AS_VAR_GET(CACHEVAR)" = xyes],
+  [m4_default([$2], :)],
+  [m4_default([$3], :)])
+AS_VAR_POPDEF([CACHEVAR])dnl
+])dnl AX_CHECK_LINK_FLAGS
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_count_cpus.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_count_cpus.m4
new file mode 100644
index 0000000..d4f3d29
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_count_cpus.m4
@@ -0,0 +1,57 @@
+# ===========================================================================
+#       http://www.gnu.org/software/autoconf-archive/ax_count_cpus.html
+# ===========================================================================
+#
+# SYNOPSIS
+#
+#   AX_COUNT_CPUS
+#
+# DESCRIPTION
+#
+#   Attempt to count the number of processors present on the machine. If the
+#   detection fails, then a value of 1 is assumed.
+#
+#   The value is placed in the CPU_COUNT variable.
+#
+# LICENSE
+#
+#   Copyright (c) 2012 Brian Aker 
+#   Copyright (c) 2008 Michael Paul Bailey 
+#   Copyright (c) 2008 Christophe Tournayre 
+#
+#   Copying and distribution of this file, with or without modification, are
+#   permitted in any medium without royalty provided the copyright notice
+#   and this notice are preserved. This file is offered as-is, without any
+#   warranty.
+
+#serial 10
+
+  AC_DEFUN([AX_COUNT_CPUS],[
+      AC_REQUIRE([AC_CANONICAL_HOST])
+      AC_REQUIRE([AC_PROG_EGREP])
+      AC_MSG_CHECKING([the number of available CPUs])
+      CPU_COUNT="0"
+
+      AS_CASE([$host_os],[
+        *darwin*],[
+        AS_IF([test -x /usr/sbin/sysctl],[
+          sysctl_a=`/usr/sbin/sysctl -a 2>/dev/null| grep -c hw.cpu`
+          AS_IF([test sysctl_a],[
+            CPU_COUNT=`/usr/sbin/sysctl -n hw.ncpu`
+            ])
+          ])],[
+        *linux*],[
+        AS_IF([test "x$CPU_COUNT" = "x0" -a -e /proc/cpuinfo],[
+          AS_IF([test "x$CPU_COUNT" = "x0" -a -e /proc/cpuinfo],[
+            CPU_COUNT=`$EGREP -c '^processor' /proc/cpuinfo`
+            ])
+          ])
+        ])
+
+      AS_IF([test "x$CPU_COUNT" = "x0"],[
+        CPU_COUNT="1"
+        AC_MSG_RESULT( [unable to detect (assuming 1)] )
+        ],[
+        AC_MSG_RESULT( $CPU_COUNT )
+        ])
+      ])
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_create_generic_config.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_create_generic_config.m4
new file mode 100644
index 0000000..535838f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_create_generic_config.m4
@@ -0,0 +1,195 @@
+# ============================================================================
+#  http://www.gnu.org/software/autoconf-archive/ax_create_generic_config.html
+# ============================================================================
+#
+# SYNOPSIS
+#
+#   AX_CREATE_GENERIC_CONFIG [(PACKAGEnlibs [, VERSION])]
+#
+# DESCRIPTION
+#
+#   Creates a generic PACKAGE-config file that has all the things that you
+#   want, hmm, well, atleast it has --cflags, --version, --libs. Ahhm, did
+#   you see ax_path_generic in the autoconf-archive? ;-)
+#
+#   this macros saves you all the typing for a pkg-config.in script, you
+#   don't even need to distribute one along. Place this macro in your
+#   configure.ac, et voila, you got one that you want to install.
+#
+#   oh, btw, if the first arg looks like "mylib -lwhat' then it will go to
+#   be added to the --libs, and mylib is extracted.
+#
+#   the defaults: $1 = $PACKAGE $LIBS $2 = $VERSION there is also an
+#   AC_SUBST(GENERIC_CONFIG) that will be set to the name of the file that
+#   we did output in this macro. Use as:
+#
+#    install-exec-local:    install-generic-config
+#
+#    install-generic-config:
+#       $(mkinstalldirs) $(DESTDIR)$(bindir)
+#       $(INSTALL_SCRIPT) @GENERIC_CONFIG@ $(DESTDIR)$(bindir)
+#
+# LICENSE
+#
+#   Copyright (c) 2008 Guido U. Draheim 
+#
+#   This program is free software; you can redistribute it and/or modify it
+#   under the terms of the GNU General Public License as published by the
+#   Free Software Foundation; either version 3 of the License, or (at your
+#   option) any later version.
+#
+#   This program is distributed in the hope that it will be useful, but
+#   WITHOUT ANY WARRANTY; without even the implied warranty of
+#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
+#   Public License for more details.
+#
+#   You should have received a copy of the GNU General Public License along
+#   with this program. If not, see .
+#
+#   As a special exception, the respective Autoconf Macro's copyright owner
+#   gives unlimited permission to copy, distribute and modify the configure
+#   scripts that are the output of Autoconf when processing the Macro. You
+#   need not follow the terms of the GNU General Public License when using
+#   or distributing such scripts, even though portions of the text of the
+#   Macro appear in them. The GNU General Public License (GPL) does govern
+#   all other use of the material that constitutes the Autoconf Macro.
+#
+#   This special exception to the GPL applies to versions of the Autoconf
+#   Macro released by the Autoconf Archive. When you make and distribute a
+#   modified version of the Autoconf Macro, you may extend this special
+#   exception to the GPL to apply to your modified version as well.
+
+#serial 6
+
+AU_ALIAS([AC_CREATE_GENERIC_CONFIG], [AX_CREATE_GENERIC_CONFIG])
+AC_DEFUN([AX_CREATE_GENERIC_CONFIG],[# create a generic PACKAGE-config file
+L=`echo ifelse($1, , $PACKAGE $LIBS, $1)`
+P=`echo $L | sed -e 's/ -.*//'`
+P=`echo $P`
+V=`echo ifelse($2, , $VERSION, $2)`
+F=`echo $P-config`
+L=`echo -l$L | sed -e 's/^-llib/-l/'`
+AC_MSG_RESULT(creating $F - generic $V for $L)
+test "x$prefix" = xNONE && prefix="$ac_default_prefix"
+test "x$exec_prefix" = xNONE && exec_prefix='${prefix}'
+echo '#! /bin/sh' >$F
+echo ' ' >>$F
+echo 'package="'$P'"' >>$F
+echo 'version="'$V'"' >>$F
+echo 'libs="'$L'"' >>$F
+echo ' ' >>$F
+# in the order of occurence a standard automake Makefile
+echo 'prefix="'$prefix'"' >>$F
+echo 'exec_prefix="'$exec_prefix'"' >>$F
+echo 'bindir="'$bindir'"' >>$F
+echo 'sbindir="'$sbindir'"' >>$F
+echo 'libexecdir="'$libexecdir'"' >>$F
+echo 'datadir="'$datadir'"' >>$F
+echo 'sysconfdir="'$sysconfdir'"' >>$F
+echo 'sharedstatedir="'$sharedstatedir'"' >>$F
+echo 'localstatedir="'$localstatedir'"' >>$F
+echo 'libdir="'$libdir'"' >>$F
+echo 'infodir="'$infodir'"' >>$F
+echo 'mandir="'$mandir'"' >>$F
+echo 'includedir="'$includedir'"' >>$F
+echo 'target="'$target'"' >>$F
+echo 'host="'$host'"' >>$F
+echo 'build="'$build'"' >>$F
+echo ' ' >>$F
+echo 'if test "'"\$""#"'" -eq 0; then' >>$F
+echo '   cat <>$F
+echo 'Usage: $package-config [OPTIONS]' >>$F
+echo 'Options:' >>$F
+echo '  --prefix[=DIR]) : \$prefix' >>$F
+echo '  --package) : \$package' >>$F
+echo '  --version) : \$version' >>$F
+echo '  --cflags) : -I\$includedir' >>$F
+echo '  --libs) : -L\$libdir -l\$package' >>$F
+echo '  --help) print all the options (not just these)' >>$F
+echo 'EOF' >>$F
+echo 'fi' >>$F
+echo ' ' >>$F
+echo 'o=""' >>$F
+echo 'h=""' >>$F
+echo 'for i in "[$]@"; do' >>$F
+echo '  case $i in' >>$F
+echo '  --prefix=*) prefix=`echo $i | sed -e "s/--prefix=//"` ;;' >>$F
+echo '  --prefix)    o="$o $prefix" ;;' >>$F
+echo '  --package)   o="$o $package" ;;' >>$F
+echo '  --version)   o="$o $version" ;;' >>$F
+echo '  --cflags) if test "_$includedir" != "_/usr/include"' >>$F
+echo '          then o="$o -I$includedir" ; fi' >>$F
+echo '  ;;' >>$F
+echo '  --libs)      o="$o -L$libdir $libs" ;;' >>$F
+echo '  --exec_prefix|--eprefix) o="$o $exec_prefix" ;;' >>$F
+echo '  --bindir)                o="$o $bindir" ;;' >>$F
+echo '  --sbindir)               o="$o $sbindir" ;;' >>$F
+echo '  --libexecdir)            o="$o $libexecdir" ;;' >>$F
+echo '  --datadir)               o="$o $datadir" ;;' >>$F
+echo '  --datainc)               o="$o -I$datadir" ;;' >>$F
+echo '  --datalib)               o="$o -L$datadir" ;;' >>$F
+echo '  --sysconfdir)            o="$o $sysconfdir" ;;' >>$F
+echo '  --sharedstatedir)        o="$o $sharedstatedir" ;;' >>$F
+echo '  --localstatedir)         o="$o $localstatedir" ;;' >>$F
+echo '  --libdir)                o="$o $libdir" ;;' >>$F
+echo '  --libadd)                o="$o -L$libdir" ;;' >>$F
+echo '  --infodir)               o="$o $infodir" ;;' >>$F
+echo '  --mandir)                o="$o $mandir" ;;' >>$F
+echo '  --target)                o="$o $target" ;;' >>$F
+echo '  --host)                  o="$o $host" ;;' >>$F
+echo '  --build)                 o="$o $build" ;;' >>$F
+echo '  --data)                  o="$o -I$datadir/$package" ;;' >>$F
+echo '  --pkgdatadir)            o="$o $datadir/$package" ;;' >>$F
+echo '  --pkgdatainc)            o="$o -I$datadir/$package" ;;' >>$F
+echo '  --pkgdatalib)            o="$o -L$datadir/$package" ;;' >>$F
+echo '  --pkglibdir)             o="$o $libdir/$package" ;;' >>$F
+echo '  --pkglibinc)             o="$o -I$libinc/$package" ;;' >>$F
+echo '  --pkglibadd)             o="$o -L$libadd/$package" ;;' >>$F
+echo '  --pkgincludedir)         o="$o $includedir/$package" ;;' >>$F
+echo '  --help) h="1" ;;' >>$F
+echo '  -?//*|-?/*//*|-?./*//*|//*|/*//*|./*//*) ' >>$F
+echo '       v=`echo $i | sed -e s://:\$:g`' >>$F
+echo '       v=`eval "echo $v"` ' >>$F
+echo '       o="$o $v" ;; ' >>$F
+echo '  esac' >>$F
+echo 'done' >>$F
+echo ' ' >>$F
+echo 'o=`eval "echo $o"`' >>$F
+echo 'o=`eval "echo $o"`' >>$F
+echo 'eval "echo $o"' >>$F
+echo ' ' >>$F
+echo 'if test ! -z "$h" ; then ' >>$F
+echo 'cat <>$F
+echo '  --prefix=xxx)      (what is that for anyway?)' >>$F
+echo '  --prefix)         \$prefix        $prefix' >>$F
+echo '  --package)        \$package       $package' >>$F
+echo '  --version)        \$version       $version' >>$F
+echo '  --cflags)         -I\$includedir    unless it is /usr/include' >>$F
+echo '  --libs)           -L\$libdir -l\$PACKAGE \$LIBS' >>$F
+echo '  --exec_prefix) or... ' >>$F
+echo '  --eprefix)        \$exec_prefix   $exec_prefix' >>$F
+echo '  --bindir)         \$bindir        $bindir' >>$F
+echo '  --sbindir)        \$sbindir       $sbindir' >>$F
+echo '  --libexecdir)     \$libexecdir    $libexecdir' >>$F
+echo '  --datadir)        \$datadir       $datadir' >>$F
+echo '  --sysconfdir)     \$sysconfdir    $sysconfdir' >>$F
+echo '  --sharedstatedir) \$sharedstatedir$sharedstatedir' >>$F
+echo '  --localstatedir)  \$localstatedir $localstatedir' >>$F
+echo '  --libdir)         \$libdir        $libdir' >>$F
+echo '  --infodir)        \$infodir       $infodir' >>$F
+echo '  --mandir)         \$mandir        $mandir' >>$F
+echo '  --target)         \$target        $target' >>$F
+echo '  --host)           \$host          $host' >>$F
+echo '  --build)          \$build         $build' >>$F
+echo '  --data)           -I\$datadir/\$package' >>$F
+echo '  --pkgdatadir)     \$datadir/\$package' >>$F
+echo '  --pkglibdir)      \$libdir/\$package' >>$F
+echo '  --pkgincludedir)  \$includedir/\$package' >>$F
+echo '  --help)           generated by ax_create_generic_config.m4' >>$F
+echo '  -I//varname and other inc-targets like --pkgdatainc supported' >>$F
+echo '  -L//varname and other lib-targets, e.g. --pkgdatalib or --libadd' >>$F
+echo 'EOF' >>$F
+echo 'fi' >>$F
+GENERIC_CONFIG="$F"
+AC_SUBST(GENERIC_CONFIG)
+])
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_debug.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_debug.m4
new file mode 100644
index 0000000..94e4c9c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_debug.m4
@@ -0,0 +1,63 @@
+# ===========================================================================
+#      https://github.com/BrianAker/ddm4/
+# ===========================================================================
+#
+# SYNOPSIS
+#
+#   AX_DEBUG()
+#
+# DESCRIPTION
+#
+#   --enable-debug
+#
+# LICENSE
+#
+#  Copyright (C) 2012 Brian Aker
+#  All rights reserved.
+#  
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions are
+#  met:
+#  
+#      * Redistributions of source code must retain the above copyright
+#  notice, this list of conditions and the following disclaimer.
+#  
+#      * Redistributions in binary form must reproduce the above
+#  copyright notice, this list of conditions and the following disclaimer
+#  in the documentation and/or other materials provided with the
+#  distribution.
+#  
+#      * The names of its contributors may not be used to endorse or
+#  promote products derived from this software without specific prior
+#  written permission.
+#  
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#serial 6.1
+
+AC_DEFUN([AX_DEBUG],
+    [AC_PREREQ([2.63])dnl
+    AC_ARG_ENABLE([debug],
+      [AS_HELP_STRING([--enable-debug],
+        [Add debug code/turns off optimizations (yes|no) @<:@default=no@:>@])],
+      [ax_enable_debug=$enableval],
+      [ax_enable_debug=no])
+
+	AS_IF([test "x$ax_enable_debug" = xyes],
+		[AC_DEFINE([DEBUG],[1],[Define to 1 to enable debugging code.])],
+		[AC_SUBST([MCHECK])
+         AC_DEFINE([DEBUG],[0],[Define to 1 to enable debugging code.])])
+
+    AC_MSG_CHECKING([for debug])
+    AC_MSG_RESULT([$ax_enable_debug])
+    AM_CONDITIONAL([DEBUG],[test "x${ax_enable_debug}" = xyes])])
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_file_escapes.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_file_escapes.m4
new file mode 100644
index 0000000..f4c6a06
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_file_escapes.m4
@@ -0,0 +1,30 @@
+# ===========================================================================
+#      http://www.gnu.org/software/autoconf-archive/ax_file_escapes.html
+# ===========================================================================
+#
+# SYNOPSIS
+#
+#   AX_FILE_ESCAPES
+#
+# DESCRIPTION
+#
+#   Writes the specified data to the specified file.
+#
+# LICENSE
+#
+#   Copyright (c) 2008 Tom Howard 
+#
+#   Copying and distribution of this file, with or without modification, are
+#   permitted in any medium without royalty provided the copyright notice
+#   and this notice are preserved. This file is offered as-is, without any
+#   warranty.
+
+#serial 7
+
+AC_DEFUN([AX_FILE_ESCAPES],[
+AX_DOLLAR="\$"
+AX_SRB="\\135"
+AX_SLB="\\133"
+AX_BS="\\\\"
+AX_DQ="\""
+])
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_harden_compiler_flags.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_harden_compiler_flags.m4
new file mode 100644
index 0000000..018ffcb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_harden_compiler_flags.m4
@@ -0,0 +1,235 @@
+# ===========================================================================
+#      https://github.com/BrianAker/ddm4/
+# ===========================================================================
+#
+# SYNOPSIS
+#
+#   AX_HARDEN_COMPILER_FLAGS()
+#   AX_HARDEN_LINKER_FLAGS()
+#   AX_HARDEN_CC_COMPILER_FLAGS()
+#   AX_HARDEN_CXX_COMPILER_FLAGS()
+#
+# DESCRIPTION
+#
+#   Any compiler flag that "hardens" or tests code. C99 is assumed.
+#
+#   NOTE: Implementation based on AX_APPEND_FLAG.
+#
+# LICENSE
+#
+#  Copyright (C) 2012 Brian Aker
+#  All rights reserved.
+#  
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions are
+#  met:
+#  
+#      * Redistributions of source code must retain the above copyright
+#  notice, this list of conditions and the following disclaimer.
+#  
+#      * Redistributions in binary form must reproduce the above
+#  copyright notice, this list of conditions and the following disclaimer
+#  in the documentation and/or other materials provided with the
+#  distribution.
+#  
+#      * The names of its contributors may not be used to endorse or
+#  promote products derived from this software without specific prior
+#  written permission.
+#  
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+# The Following flags are not checked for
+# -Wdeclaration-after-statement is counter to C99
+# AX_APPEND_COMPILE_FLAGS([-std=c++11]) -- Not ready yet
+# AX_APPEND_COMPILE_FLAGS([-pedantic]) -- ?
+# AX_APPEND_COMPILE_FLAGS([-Wstack-protector]) -- Issues on 32bit compile
+# AX_APPEND_COMPILE_FLAGS([-fstack-protector-all]) -- Issues on 32bit compile
+# AX_APPEND_COMPILE_FLAGS([-Wlong-long]) -- Don't turn on for compatibility issues memcached_stat_st
+# AX_APPEND_COMPILE_FLAGS([-Wold-style-definition],,[$ax_append_compile_cflags_extra])
+# AX_APPEND_COMPILE_FLAGS([-std=c99],,[$ax_append_compile_cflags_extra])
+# AX_APPEND_COMPILE_FLAGS([-Wlogical-op],,[$ax_append_compile_cflags_extra])
+# AX_APPEND_COMPILE_FLAGS([-fstack-check],,[$ax_append_compile_cflags_extra]) -- problems with fastmath stack size checks
+# AX_APPEND_COMPILE_FLAGS([-floop-parallelize-all],,[$ax_append_compile_cflags_extra]) -- causes RSA verify problem on x64
+# AX_APPEND_COMPILE_FLAGS([-Wunreachable-code],,[$ax_append_compile_cflags_extra])  -- older clang and when gcc had it are buggy
+
+#serial 4.1
+
+  AC_DEFUN([AX_HARDEN_LINKER_FLAGS], [
+      AC_REQUIRE([AX_VCS_CHECKOUT])
+      AC_REQUIRE([AX_DEBUG])
+
+      dnl If we are inside of VCS we append -Werror, otherwise we just use it to test other flags
+      AX_HARDEN_LIB=
+      ax_append_compile_link_flags_extra=
+      AS_IF([test "x$ac_cv_vcs_checkout" = "xyes"],[
+        AX_CHECK_LINK_FLAG([-Werror],[
+          AX_HARDEN_LIB="-Werror $AX_HARDEN_LIB"
+          ])
+        ],[
+        AX_CHECK_LINK_FLAG([-Werror],[
+          ax_append_compile_link_flags_extra='-Werror'
+          ])
+        ])
+
+      AX_CHECK_LINK_FLAG([-z relro -z now],[
+        AX_HARDEN_LIB="-z relro -z now $AX_HARDEN_LIB"
+        ],,[$ax_append_compile_link_flags_extra])
+
+      AX_CHECK_LINK_FLAG([-pie],[
+          AX_HARDEN_LIB="-pie $AX_HARDEN_LIB"
+          ],,[$ax_append_compile_link_flags_extra])
+
+      LIB="$LIB $AX_HARDEN_LIB"
+      ])
+
+  AC_DEFUN([AX_HARDEN_CC_COMPILER_FLAGS], [
+      AC_REQUIRE([AX_HARDEN_LINKER_FLAGS])
+
+      AC_LANG_PUSH([C])
+
+      CFLAGS=
+      ac_cv_warnings_as_errors=no
+      ax_append_compile_cflags_extra=
+      AS_IF([test "$ac_cv_vcs_checkout" = "yes"],[
+        AX_APPEND_COMPILE_FLAGS([-Werror])
+        ac_cv_warnings_as_errors=yes
+        ],[
+        AX_APPEND_COMPILE_FLAGS([-Werror],[ax_append_compile_cflags_extra])
+        ])
+
+      AS_IF([test "$ax_enable_debug" = "yes"], [
+        AX_APPEND_COMPILE_FLAGS([-g])
+        AX_APPEND_COMPILE_FLAGS([-ggdb],,[$ax_append_compile_cflags_extra])
+        AX_APPEND_COMPILE_FLAGS([-O0],,[$ax_append_compile_cflags_extra])
+        ],[])
+
+      AX_APPEND_COMPILE_FLAGS([-Wno-pragmas],,[$ax_append_compile_cflags_extra])
+
+      AX_APPEND_COMPILE_FLAGS([-Wall],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wno-strict-aliasing],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wextra],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wunknown-pragmas],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wthis-test-should-fail],,[$ax_append_compile_cflags_extra])
+      dnl Anything below this comment please keep sorted.
+      AS_IF([test "$CC" = "clang"],[],[
+        AX_APPEND_COMPILE_FLAGS([--param=ssp-buffer-size=1],,[$ax_append_compile_cflags_extra])
+        ])
+      AX_APPEND_COMPILE_FLAGS([-Waddress],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Warray-bounds],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wbad-function-cast],,[$ax_append_compile_cflags_extra])
+      dnl Not in use -Wc++-compat
+      AX_APPEND_COMPILE_FLAGS([-Wchar-subscripts],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wcomment],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wfloat-equal],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wformat-security],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wformat=2],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wmaybe-uninitialized],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wmissing-field-initializers],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wmissing-noreturn],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wmissing-prototypes],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wnested-externs],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wnormalized=id],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Woverride-init],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wpointer-arith],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wpointer-sign],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wredundant-decls],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wshadow],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wshorten-64-to-32],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wsign-compare],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wstrict-overflow=1],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wstrict-prototypes],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wswitch-enum],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wundef],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wunused],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wunused-result],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wunused-variable],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wwrite-strings],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-fwrapv],,[$ax_append_compile_cflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-fPIE],,[$ax_append_compile_cflags_extra])
+      AC_LANG_POP
+      ])
+
+  AC_DEFUN([AX_HARDEN_CXX_COMPILER_FLAGS], [
+      AC_REQUIRE([AX_HARDEN_CC_COMPILER_FLAGS])
+      AC_LANG_PUSH([C++])
+
+      ax_append_compile_cxxflags_extra=
+      AS_IF([test "$ac_cv_warnings_as_errors" = "yes"],[
+        AX_APPEND_COMPILE_FLAGS([-Werror])
+        ],[
+        AX_APPEND_COMPILE_FLAGS([-Werror],[ax_append_compile_cxxflags_extra])
+        ])
+
+      AS_IF([test "$ax_enable_debug" = "yes" ], [
+        AX_APPEND_COMPILE_FLAGS([-g],,[$ax_append_compile_cxxflags_extra])
+        AX_APPEND_COMPILE_FLAGS([-O0],,[$ax_append_compile_cxxflags_extra])
+        AX_APPEND_COMPILE_FLAGS([-ggdb],,[$ax_append_compile_cxxflags_extra])
+        ],[
+        AX_APPEND_COMPILE_FLAGS([-D_FORTIFY_SOURCE=2],,[$ax_append_compile_cxxflags_extra])
+        ])
+
+      AS_IF([test "$ac_cv_vcs_checkout" = "yes" ], [
+        AX_APPEND_COMPILE_FLAGS([-Werror],,[$ax_append_compile_cxxflags_extra])
+        ],[
+        AX_APPEND_COMPILE_FLAGS([-Wno-pragmas],,[$ax_append_compile_cxxflags_extra])
+        ])
+
+      AX_APPEND_COMPILE_FLAGS([-Wall],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wno-strict-aliasing],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wextra],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wunknown-pragmas],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wthis-test-should-fail],,[$ax_append_compile_cxxflags_extra])
+      dnl Anything below this comment please keep sorted.
+      AX_APPEND_COMPILE_FLAGS([--param=ssp-buffer-size=1],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Waddress],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Warray-bounds],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wchar-subscripts],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wcomment],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wctor-dtor-privacy],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wfloat-equal],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wformat=2],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wmaybe-uninitialized],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wmissing-field-initializers],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wmissing-noreturn],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wnon-virtual-dtor],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wnormalized=id],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Woverloaded-virtual],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wpointer-arith],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wredundant-decls],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wshadow],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wshorten-64-to-32],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wsign-compare],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wstrict-overflow=1],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wswitch-enum],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wundef],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wc++11-compat],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wunused],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wunused-result],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wunused-variable],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wwrite-strings],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-Wformat-security],,[$ax_append_compile_cxxflags_extra])
+      AX_APPEND_COMPILE_FLAGS([-fwrapv],,[$ax_append_compile_cxxflags_extra])
+      AC_LANG_POP
+  ])
+
+  AC_DEFUN([AX_HARDEN_COMPILER_FLAGS], [
+      AC_REQUIRE([AX_HARDEN_CXX_COMPILER_FLAGS])
+      ])
+
+  AC_DEFUN([AX_CC_OTHER_FLAGS], [
+      AC_REQUIRE([AX_HARDEN_CC_COMPILER_FLAGS])
+
+      AC_LANG_PUSH([C])
+      AX_APPEND_COMPILE_FLAGS([-pipe],,[$ax_append_compile_cflags_extra])
+      AC_LANG_POP
+      ])
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_print_to_file.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_print_to_file.m4
new file mode 100644
index 0000000..5b9d1c3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_print_to_file.m4
@@ -0,0 +1,27 @@
+# ===========================================================================
+#     http://www.gnu.org/software/autoconf-archive/ax_print_to_file.html
+# ===========================================================================
+#
+# SYNOPSIS
+#
+#   AX_PRINT_TO_FILE([FILE],[DATA])
+#
+# DESCRIPTION
+#
+#   Writes the specified data to the specified file.
+#
+# LICENSE
+#
+#   Copyright (c) 2008 Tom Howard 
+#
+#   Copying and distribution of this file, with or without modification, are
+#   permitted in any medium without royalty provided the copyright notice
+#   and this notice are preserved. This file is offered as-is, without any
+#   warranty.
+
+#serial 7
+
+AC_DEFUN([AX_PRINT_TO_FILE],[
+AC_REQUIRE([AX_FILE_ESCAPES])
+printf "$2" > "$1"
+])
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_pthread.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_pthread.m4
new file mode 100644
index 0000000..bdb34b0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_pthread.m4
@@ -0,0 +1,320 @@
+# ===========================================================================
+#        http://www.gnu.org/software/autoconf-archive/ax_pthread.html
+# ===========================================================================
+#
+# SYNOPSIS
+#
+#   AX_PTHREAD([ACTION-IF-FOUND[, ACTION-IF-NOT-FOUND]])
+#
+# DESCRIPTION
+#
+#   This macro figures out how to build C programs using POSIX threads. It
+#   sets the PTHREAD_LIBS output variable to the threads library and linker
+#   flags, and the PTHREAD_CFLAGS output variable to any special C compiler
+#   flags that are needed. (The user can also force certain compiler
+#   flags/libs to be tested by setting these environment variables.)
+#
+#   Also sets PTHREAD_CC to any special C compiler that is needed for
+#   multi-threaded programs (defaults to the value of CC otherwise). (This
+#   is necessary on AIX to use the special cc_r compiler alias.)
+#
+#   NOTE: You are assumed to not only compile your program with these flags,
+#   but also link it with them as well. e.g. you should link with
+#   $PTHREAD_CC $CFLAGS $PTHREAD_CFLAGS $LDFLAGS ... $PTHREAD_LIBS $LIBS
+#
+#   If you are only building threads programs, you may wish to use these
+#   variables in your default LIBS, CFLAGS, and CC:
+#
+#     LIBS="$PTHREAD_LIBS $LIBS"
+#     CFLAGS="$CFLAGS $PTHREAD_CFLAGS"
+#     CC="$PTHREAD_CC"
+#
+#   In addition, if the PTHREAD_CREATE_JOINABLE thread-attribute constant
+#   has a nonstandard name, defines PTHREAD_CREATE_JOINABLE to that name
+#   (e.g. PTHREAD_CREATE_UNDETACHED on AIX).
+#
+#   Also HAVE_PTHREAD_PRIO_INHERIT is defined if pthread is found and the
+#   PTHREAD_PRIO_INHERIT symbol is defined when compiling with
+#   PTHREAD_CFLAGS.
+#
+#   ACTION-IF-FOUND is a list of shell commands to run if a threads library
+#   is found, and ACTION-IF-NOT-FOUND is a list of commands to run it if it
+#   is not found. If ACTION-IF-FOUND is not specified, the default action
+#   will define HAVE_PTHREAD.
+#
+#   Please let the authors know if this macro fails on any platform, or if
+#   you have any other suggestions or comments. This macro was based on work
+#   by SGJ on autoconf scripts for FFTW (http://www.fftw.org/) (with help
+#   from M. Frigo), as well as ac_pthread and hb_pthread macros posted by
+#   Alejandro Forero Cuervo to the autoconf macro repository. We are also
+#   grateful for the helpful feedback of numerous users.
+#
+#   Updated for Autoconf 2.68 by Daniel Richard G.
+#
+# LICENSE
+#
+#   Copyright (c) 2008 Steven G. Johnson 
+#   Copyright (c) 2011 Daniel Richard G. 
+#
+#   This program is free software: you can redistribute it and/or modify it
+#   under the terms of the GNU General Public License as published by the
+#   Free Software Foundation, either version 3 of the License, or (at your
+#   option) any later version.
+#
+#   This program is distributed in the hope that it will be useful, but
+#   WITHOUT ANY WARRANTY; without even the implied warranty of
+#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
+#   Public License for more details.
+#
+#   You should have received a copy of the GNU General Public License along
+#   with this program. If not, see .
+#
+#   As a special exception, the respective Autoconf Macro's copyright owner
+#   gives unlimited permission to copy, distribute and modify the configure
+#   scripts that are the output of Autoconf when processing the Macro. You
+#   need not follow the terms of the GNU General Public License when using
+#   or distributing such scripts, even though portions of the text of the
+#   Macro appear in them. The GNU General Public License (GPL) does govern
+#   all other use of the material that constitutes the Autoconf Macro.
+#
+#   This special exception to the GPL applies to versions of the Autoconf
+#   Macro released by the Autoconf Archive. When you make and distribute a
+#   modified version of the Autoconf Macro, you may extend this special
+#   exception to the GPL to apply to your modified version as well.
+
+#serial 20
+
+AU_ALIAS([ACX_PTHREAD], [AX_PTHREAD])
+AC_DEFUN([AX_PTHREAD], [
+AC_REQUIRE([AC_CANONICAL_HOST])
+AC_LANG_PUSH([C])
+ax_pthread_ok=no
+
+# We used to check for pthread.h first, but this fails if pthread.h
+# requires special compiler flags (e.g. on True64 or Sequent).
+# It gets checked for in the link test anyway.
+
+# First of all, check if the user has set any of the PTHREAD_LIBS,
+# etcetera environment variables, and if threads linking works using
+# them:
+if test x"$PTHREAD_LIBS$PTHREAD_CFLAGS" != x; then
+        save_CFLAGS="$CFLAGS"
+        CFLAGS="$CFLAGS $PTHREAD_CFLAGS"
+        save_LIBS="$LIBS"
+        LIBS="$PTHREAD_LIBS $LIBS"
+        AC_MSG_CHECKING([for pthread_join in LIBS=$PTHREAD_LIBS with CFLAGS=$PTHREAD_CFLAGS])
+        AC_TRY_LINK_FUNC(pthread_join, ax_pthread_ok=yes)
+        AC_MSG_RESULT($ax_pthread_ok)
+        if test x"$ax_pthread_ok" = xno; then
+                PTHREAD_LIBS=""
+                PTHREAD_CFLAGS=""
+        fi
+        LIBS="$save_LIBS"
+        CFLAGS="$save_CFLAGS"
+fi
+
+# We must check for the threads library under a number of different
+# names; the ordering is very important because some systems
+# (e.g. DEC) have both -lpthread and -lpthreads, where one of the
+# libraries is broken (non-POSIX).
+
+# Create a list of thread flags to try.  Items starting with a "-" are
+# C compiler flags, and other items are library names, except for "none"
+# which indicates that we try without any flags at all, and "pthread-config"
+# which is a program returning the flags for the Pth emulation library.
+
+ax_pthread_flags="pthreads none -Kthread -kthread lthread -pthread -pthreads -mthreads pthread --thread-safe -mt pthread-config"
+
+# The ordering *is* (sometimes) important.  Some notes on the
+# individual items follow:
+
+# pthreads: AIX (must check this before -lpthread)
+# none: in case threads are in libc; should be tried before -Kthread and
+#       other compiler flags to prevent continual compiler warnings
+# -Kthread: Sequent (threads in libc, but -Kthread needed for pthread.h)
+# -kthread: FreeBSD kernel threads (preferred to -pthread since SMP-able)
+# lthread: LinuxThreads port on FreeBSD (also preferred to -pthread)
+# -pthread: Linux/gcc (kernel threads), BSD/gcc (userland threads)
+# -pthreads: Solaris/gcc
+# -mthreads: Mingw32/gcc, Lynx/gcc
+# -mt: Sun Workshop C (may only link SunOS threads [-lthread], but it
+#      doesn't hurt to check since this sometimes defines pthreads too;
+#      also defines -D_REENTRANT)
+#      ... -mt is also the pthreads flag for HP/aCC
+# pthread: Linux, etcetera
+# --thread-safe: KAI C++
+# pthread-config: use pthread-config program (for GNU Pth library)
+
+case ${host_os} in
+        solaris*)
+
+        # On Solaris (at least, for some versions), libc contains stubbed
+        # (non-functional) versions of the pthreads routines, so link-based
+        # tests will erroneously succeed.  (We need to link with -pthreads/-mt/
+        # -lpthread.)  (The stubs are missing pthread_cleanup_push, or rather
+        # a function called by this macro, so we could check for that, but
+        # who knows whether they'll stub that too in a future libc.)  So,
+        # we'll just look for -pthreads and -lpthread first:
+
+        ax_pthread_flags="-pthreads pthread -mt -pthread $ax_pthread_flags"
+        ;;
+
+        darwin*)
+        AC_REQUIRE([WOLFSSL_DARWIN_USING_CLANG])
+        AS_IF([test x"$wolfssl_darwin_clang" = x"yes"],
+                [ax_pthread_flags="$ax_pthread_flags"],
+                [ax_pthread_flags="-pthread $ax_pthread_flags"])
+        ;;
+esac
+
+if test x"$ax_pthread_ok" = xno; then
+for flag in $ax_pthread_flags; do
+
+        case $flag in
+                none)
+                AC_MSG_CHECKING([whether pthreads work without any flags])
+                ;;
+
+                -*)
+                AC_MSG_CHECKING([whether pthreads work with $flag])
+                PTHREAD_CFLAGS="$flag"
+                ;;
+
+                pthread-config)
+                AC_CHECK_PROG(ax_pthread_config, pthread-config, yes, no)
+                if test x"$ax_pthread_config" = xno; then continue; fi
+                PTHREAD_CFLAGS="`pthread-config --cflags`"
+                PTHREAD_LIBS="`pthread-config --ldflags` `pthread-config --libs`"
+                ;;
+
+                *)
+                AC_MSG_CHECKING([for the pthreads library -l$flag])
+                PTHREAD_LIBS="-l$flag"
+                ;;
+        esac
+
+        save_LIBS="$LIBS"
+        save_CFLAGS="$CFLAGS"
+        LIBS="$PTHREAD_LIBS $LIBS"
+        CFLAGS="$CFLAGS $PTHREAD_CFLAGS"
+
+        # Check for various functions.  We must include pthread.h,
+        # since some functions may be macros.  (On the Sequent, we
+        # need a special flag -Kthread to make this header compile.)
+        # We check for pthread_join because it is in -lpthread on IRIX
+        # while pthread_create is in libc.  We check for pthread_attr_init
+        # due to DEC craziness with -lpthreads.  We check for
+        # pthread_cleanup_push because it is one of the few pthread
+        # functions on Solaris that doesn't have a non-functional libc stub.
+        # We try pthread_create on general principles.
+        AC_LINK_IFELSE([AC_LANG_PROGRAM([#include 
+                        static void routine(void *a) { a = 0; }
+                        static void *start_routine(void *a) { return a; }],
+                       [pthread_t th; pthread_attr_t attr;
+                        pthread_create(&th, 0, start_routine, 0);
+                        pthread_join(th, 0);
+                        pthread_attr_init(&attr);
+                        pthread_cleanup_push(routine, 0);
+                        pthread_cleanup_pop(0) /* ; */])],
+                [ax_pthread_ok=yes],
+                [])
+
+        LIBS="$save_LIBS"
+        CFLAGS="$save_CFLAGS"
+
+        AC_MSG_RESULT($ax_pthread_ok)
+        if test "x$ax_pthread_ok" = xyes; then
+                break;
+        fi
+
+        PTHREAD_LIBS=""
+        PTHREAD_CFLAGS=""
+done
+fi
+
+# Various other checks:
+if test "x$ax_pthread_ok" = xyes; then
+        save_LIBS="$LIBS"
+        LIBS="$PTHREAD_LIBS $LIBS"
+        save_CFLAGS="$CFLAGS"
+        CFLAGS="$CFLAGS $PTHREAD_CFLAGS"
+
+        # Detect AIX lossage: JOINABLE attribute is called UNDETACHED.
+        AC_MSG_CHECKING([for joinable pthread attribute])
+        attr_name=unknown
+        for attr in PTHREAD_CREATE_JOINABLE PTHREAD_CREATE_UNDETACHED; do
+            AC_LINK_IFELSE([AC_LANG_PROGRAM([#include ],
+                           [int attr = $attr; return attr /* ; */])],
+                [attr_name=$attr; break],
+                [])
+        done
+        AC_MSG_RESULT($attr_name)
+        if test "$attr_name" != PTHREAD_CREATE_JOINABLE; then
+            AC_DEFINE_UNQUOTED(PTHREAD_CREATE_JOINABLE, $attr_name,
+                               [Define to necessary symbol if this constant
+                                uses a non-standard name on your system.])
+        fi
+
+        AC_MSG_CHECKING([if more special flags are required for pthreads])
+        flag=no
+        case ${host_os} in
+            aix* | freebsd* | darwin*) flag="-D_THREAD_SAFE";;
+            osf* | hpux*) flag="-D_REENTRANT";;
+            solaris*)
+            if test "$GCC" = "yes"; then
+                flag="-D_REENTRANT"
+            else
+                flag="-mt -D_REENTRANT"
+            fi
+            ;;
+        esac
+        AC_MSG_RESULT(${flag})
+        if test "x$flag" != xno; then
+            PTHREAD_CFLAGS="$flag $PTHREAD_CFLAGS"
+        fi
+
+        AC_CACHE_CHECK([for PTHREAD_PRIO_INHERIT],
+            ax_cv_PTHREAD_PRIO_INHERIT, [
+                AC_LINK_IFELSE([
+                    AC_LANG_PROGRAM([[#include ]], [[int i = PTHREAD_PRIO_INHERIT;]])],
+                    [ax_cv_PTHREAD_PRIO_INHERIT=yes],
+                    [ax_cv_PTHREAD_PRIO_INHERIT=no])
+            ])
+        AS_IF([test "x$ax_cv_PTHREAD_PRIO_INHERIT" = "xyes"],
+            AC_DEFINE([HAVE_PTHREAD_PRIO_INHERIT], 1, [Have PTHREAD_PRIO_INHERIT.]))
+
+        LIBS="$save_LIBS"
+        CFLAGS="$save_CFLAGS"
+
+        # More AIX lossage: compile with *_r variant
+        if test "x$GCC" != xyes; then
+            case $host_os in
+                aix*)
+                AS_CASE(["x/$CC"],
+                  [x*/c89|x*/c89_128|x*/c99|x*/c99_128|x*/cc|x*/cc128|x*/xlc|x*/xlc_v6|x*/xlc128|x*/xlc128_v6],
+                  [#handle absolute path differently from PATH based program lookup
+                   AS_CASE(["x$CC"],
+                     [x/*],
+                     [AS_IF([AS_EXECUTABLE_P([${CC}_r])],[PTHREAD_CC="${CC}_r"])],
+                     [AC_CHECK_PROGS([PTHREAD_CC],[${CC}_r],[$CC])])])
+                ;;
+            esac
+        fi
+fi
+
+test -n "$PTHREAD_CC" || PTHREAD_CC="$CC"
+
+AC_SUBST(PTHREAD_LIBS)
+AC_SUBST(PTHREAD_CFLAGS)
+AC_SUBST(PTHREAD_CC)
+
+# Finally, execute ACTION-IF-FOUND/ACTION-IF-NOT-FOUND:
+if test x"$ax_pthread_ok" = xyes; then
+        ifelse([$1],,AC_DEFINE(HAVE_PTHREAD,1,[Define if you have POSIX threads libraries and header files.]),[$1])
+        :
+else
+        ax_pthread_ok=no
+        $2
+fi
+AC_LANG_POP
+])dnl AX_PTHREAD
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_tls.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_tls.m4
new file mode 100644
index 0000000..3f6b5e1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_tls.m4
@@ -0,0 +1,92 @@
+# ===========================================================================
+#          http://www.gnu.org/software/autoconf-archive/ax_tls.html
+# ===========================================================================
+#
+# SYNOPSIS
+#
+#   AX_TLS([action-if-found], [action-if-not-found])
+#
+# DESCRIPTION
+#
+#   Provides a test for the compiler support of thread local storage (TLS)
+#   extensions. Defines TLS if it is found. Currently knows about GCC/ICC
+#   and MSVC. I think SunPro uses the same as GCC, and Borland apparently
+#   supports either.
+#
+# LICENSE
+#
+#   Copyright (c) 2008 Alan Woodland 
+#   Copyright (c) 2010 Diego Elio Petteno` 
+#
+#   This program is free software: you can redistribute it and/or modify it
+#   under the terms of the GNU General Public License as published by the
+#   Free Software Foundation, either version 3 of the License, or (at your
+#   option) any later version.
+#
+#   This program is distributed in the hope that it will be useful, but
+#   WITHOUT ANY WARRANTY; without even the implied warranty of
+#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
+#   Public License for more details.
+#
+#   You should have received a copy of the GNU General Public License along
+#   with this program. If not, see .
+#
+#   As a special exception, the respective Autoconf Macro's copyright owner
+#   gives unlimited permission to copy, distribute and modify the configure
+#   scripts that are the output of Autoconf when processing the Macro. You
+#   need not follow the terms of the GNU General Public License when using
+#   or distributing such scripts, even though portions of the text of the
+#   Macro appear in them. The GNU General Public License (GPL) does govern
+#   all other use of the material that constitutes the Autoconf Macro.
+#
+#   This special exception to the GPL applies to versions of the Autoconf
+#   Macro released by the Autoconf Archive. When you make and distribute a
+#   modified version of the Autoconf Macro, you may extend this special
+#   exception to the GPL to apply to your modified version as well.
+
+#serial 11
+
+#   Define m4_ifblank and m4_ifnblank macros from introduced in
+#   autotools 2.64 m4sugar.m4 if using an earlier autotools.
+
+ifdef([m4_ifblank], [], [
+    m4_define([m4_ifblank],
+    [m4_if(m4_translit([[$1]], [ ][	][
+]), [], [$2], [$3])])
+    ])
+
+
+ifdef([m4_ifnblank], [], [
+    m4_define([m4_ifnblank],
+    [m4_if(m4_translit([[$1]], [ ][	][
+]), [], [$3], [$2])])
+    ])
+
+AC_DEFUN([AX_TLS], [
+  AC_MSG_CHECKING(for thread local storage (TLS) class)
+  AC_CACHE_VAL(ac_cv_tls, [
+    ax_tls_keywords="__thread __declspec(thread) none"
+    for ax_tls_keyword in $ax_tls_keywords; do
+       AS_CASE([$ax_tls_keyword],
+          [none], [ac_cv_tls=none ; break],
+          [AC_TRY_COMPILE(
+              [#include 
+               static void
+               foo(void) {
+               static ] $ax_tls_keyword [ int bar;
+               exit(1);
+               }],
+               [],
+               [ac_cv_tls=$ax_tls_keyword ; break],
+               ac_cv_tls=none
+           )])
+    done
+  ])
+  AC_MSG_RESULT($ac_cv_tls)
+
+  AS_IF([test "$ac_cv_tls" != "none"],
+    AC_DEFINE_UNQUOTED([TLS], $ac_cv_tls, [If the compiler supports a TLS storage class define it to that here])
+      m4_ifnblank([$1], [$1]),
+    m4_ifnblank([$2], [$2])
+  )
+])
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_vcs_checkout.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_vcs_checkout.m4
new file mode 100644
index 0000000..8047b65
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ax_vcs_checkout.m4
@@ -0,0 +1,75 @@
+# ===========================================================================
+#      http://
+# ===========================================================================
+#
+# SYNOPSIS
+#
+#   AX_VCS_CHECKOUT
+#
+# DESCRIPTION
+#
+#   Discover whether or not we are operating with a tree which
+#   has been checked out of a version control system.
+#
+#
+# LICENSE
+#
+#  Copyright (C) 2012 Brian Aker
+#  All rights reserved.
+#  
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions are
+#  met:
+#  
+#      * Redistributions of source code must retain the above copyright
+#  notice, this list of conditions and the following disclaimer.
+#  
+#      * Redistributions in binary form must reproduce the above
+#  copyright notice, this list of conditions and the following disclaimer
+#  in the documentation and/or other materials provided with the
+#  distribution.
+#  
+#      * The names of its contributors may not be used to endorse or
+#  promote products derived from this software without specific prior
+#  written permission.
+#  
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#serial 6
+
+AC_DEFUN([AX_VCS_SYSTEM],
+    [AC_PREREQ([2.63])dnl
+    AC_CACHE_CHECK([for vcs system], [ac_cv_vcs_system],
+      [ac_cv_vcs_system="none"
+      AS_IF([test -d ".bzr"],[ac_cv_vcs_system="bazaar"])
+      AS_IF([test -d ".svn"],[ac_cv_vcs_system="svn"])
+      AS_IF([test -d ".hg"],[ac_cv_vcs_system="mercurial"])
+      AS_IF([test -d ".git"],[ac_cv_vcs_system="git"])
+      ])
+    AC_DEFINE_UNQUOTED([VCS_SYSTEM],["$ac_cv_vcs_system"],[VCS system])
+    ])
+
+AC_DEFUN([AX_VCS_CHECKOUT],
+    [AC_PREREQ([2.63])dnl
+    AC_REQUIRE([AX_VCS_SYSTEM])
+    AC_CACHE_CHECK([for vcs checkout],[ac_cv_vcs_checkout],
+      [AS_IF([test "x$ac_cv_vcs_system" != "xnone"],
+        [ac_cv_vcs_checkout=yes],
+        [ac_cv_vcs_checkout=no])
+      ])
+
+    AM_CONDITIONAL([IS_VCS_CHECKOUT],[test "x$ac_cv_vcs_checkout" = "xyes"])
+    AS_IF([test "x$ac_cv_vcs_checkout" = "xyes"],
+      [AC_DEFINE([VCS_CHECKOUT],[1],[Define if the code was built from VCS.])],
+      [AC_DEFINE([VCS_CHECKOUT],[0],[Define if the code was built from VCS.])])
+    ])
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/hexversion.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/hexversion.m4
new file mode 100644
index 0000000..8d26155
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/hexversion.m4
@@ -0,0 +1,6 @@
+AC_DEFUN([CREATE_HEX_VERSION],[
+
+  HEX_VERSION=`echo $VERSION | sed 's|[\-a-z0-9]*$||' | \
+    awk -F. '{printf "0x%0.2d%0.3d%0.3d", $[]1, $[]2, $[]3}'`
+  AC_SUBST([HEX_VERSION])
+])
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/lib_socket_nsl.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/lib_socket_nsl.m4
new file mode 100644
index 0000000..e786e61
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/lib_socket_nsl.m4
@@ -0,0 +1,25 @@
+dnl @synopsis LIB_SOCKET_NSL
+dnl
+dnl This macro figures out what libraries are required on this platform
+dnl to link sockets programs.
+dnl
+dnl The common cases are not to need any extra libraries, or to need
+dnl -lsocket and -lnsl. We need to avoid linking with libnsl unless we
+dnl need it, though, since on some OSes where it isn't necessary it
+dnl will totally break networking. Unisys also includes gethostbyname()
+dnl in libsocket but needs libnsl for socket().
+dnl
+dnl @category Misc
+dnl @author Russ Allbery 
+dnl @author Stepan Kasal 
+dnl @author Warren Young 
+dnl @version 2005-09-06
+dnl @license AllPermissive
+
+AC_DEFUN([LIB_SOCKET_NSL],
+[
+	AC_SEARCH_LIBS([gethostbyname], [nsl])
+	AC_SEARCH_LIBS([socket], [socket], [], [
+		AC_CHECK_LIB([socket], [socket], [LIBS="-lsocket -lnsl $LIBS"],
+		[], [-lnsl])])
+])
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/libtool.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/libtool.m4
new file mode 100644
index 0000000..4adcf73
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/libtool.m4
@@ -0,0 +1,7982 @@
+# libtool.m4 - Configure libtool for the host system. -*-Autoconf-*-
+#
+#   Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005,
+#                 2006, 2007, 2008, 2009, 2010, 2011 Free Software
+#                 Foundation, Inc.
+#   Written by Gordon Matzigkeit, 1996
+#
+# This file is free software; the Free Software Foundation gives
+# unlimited permission to copy and/or distribute it, with or without
+# modifications, as long as this notice is preserved.
+
+m4_define([_LT_COPYING], [dnl
+#   Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005,
+#                 2006, 2007, 2008, 2009, 2010, 2011 Free Software
+#                 Foundation, Inc.
+#   Written by Gordon Matzigkeit, 1996
+#
+#   This file is part of GNU Libtool.
+#
+# GNU Libtool is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# As a special exception to the GNU General Public License,
+# if you distribute this file as part of a program or library that
+# is built using GNU Libtool, you may include this file under the
+# same distribution terms that you use for the rest of that program.
+#
+# GNU Libtool is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Libtool; see the file COPYING.  If not, a copy
+# can be downloaded from http://www.gnu.org/licenses/gpl.html, or
+# obtained by writing to the Free Software Foundation, Inc.,
+# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+])
+
+# serial 57 LT_INIT
+
+
+# LT_PREREQ(VERSION)
+# ------------------
+# Complain and exit if this libtool version is less that VERSION.
+m4_defun([LT_PREREQ],
+[m4_if(m4_version_compare(m4_defn([LT_PACKAGE_VERSION]), [$1]), -1,
+       [m4_default([$3],
+		   [m4_fatal([Libtool version $1 or higher is required],
+		             63)])],
+       [$2])])
+
+
+# _LT_CHECK_BUILDDIR
+# ------------------
+# Complain if the absolute build directory name contains unusual characters
+m4_defun([_LT_CHECK_BUILDDIR],
+[case `pwd` in
+  *\ * | *\	*)
+    AC_MSG_WARN([Libtool does not cope well with whitespace in `pwd`]) ;;
+esac
+])
+
+
+# LT_INIT([OPTIONS])
+# ------------------
+AC_DEFUN([LT_INIT],
+[AC_PREREQ([2.58])dnl We use AC_INCLUDES_DEFAULT
+AC_REQUIRE([AC_CONFIG_AUX_DIR_DEFAULT])dnl
+AC_BEFORE([$0], [LT_LANG])dnl
+AC_BEFORE([$0], [LT_OUTPUT])dnl
+AC_BEFORE([$0], [LTDL_INIT])dnl
+m4_require([_LT_CHECK_BUILDDIR])dnl
+
+dnl Autoconf doesn't catch unexpanded LT_ macros by default:
+m4_pattern_forbid([^_?LT_[A-Z_]+$])dnl
+m4_pattern_allow([^(_LT_EOF|LT_DLGLOBAL|LT_DLLAZY_OR_NOW|LT_MULTI_MODULE)$])dnl
+dnl aclocal doesn't pull ltoptions.m4, ltsugar.m4, or ltversion.m4
+dnl unless we require an AC_DEFUNed macro:
+AC_REQUIRE([LTOPTIONS_VERSION])dnl
+AC_REQUIRE([LTSUGAR_VERSION])dnl
+AC_REQUIRE([LTVERSION_VERSION])dnl
+AC_REQUIRE([LTOBSOLETE_VERSION])dnl
+m4_require([_LT_PROG_LTMAIN])dnl
+
+_LT_SHELL_INIT([SHELL=${CONFIG_SHELL-/bin/sh}])
+
+dnl Parse OPTIONS
+_LT_SET_OPTIONS([$0], [$1])
+
+# This can be used to rebuild libtool when needed
+LIBTOOL_DEPS="$ltmain"
+
+# Always use our own libtool.
+LIBTOOL='$(SHELL) $(top_builddir)/libtool'
+AC_SUBST(LIBTOOL)dnl
+
+_LT_SETUP
+
+# Only expand once:
+m4_define([LT_INIT])
+])# LT_INIT
+
+# Old names:
+AU_ALIAS([AC_PROG_LIBTOOL], [LT_INIT])
+AU_ALIAS([AM_PROG_LIBTOOL], [LT_INIT])
+dnl aclocal-1.4 backwards compatibility:
+dnl AC_DEFUN([AC_PROG_LIBTOOL], [])
+dnl AC_DEFUN([AM_PROG_LIBTOOL], [])
+
+
+# _LT_CC_BASENAME(CC)
+# -------------------
+# Calculate cc_basename.  Skip known compiler wrappers and cross-prefix.
+m4_defun([_LT_CC_BASENAME],
+[for cc_temp in $1""; do
+  case $cc_temp in
+    compile | *[[\\/]]compile | ccache | *[[\\/]]ccache ) ;;
+    distcc | *[[\\/]]distcc | purify | *[[\\/]]purify ) ;;
+    \-*) ;;
+    *) break;;
+  esac
+done
+cc_basename=`$ECHO "$cc_temp" | $SED "s%.*/%%; s%^$host_alias-%%"`
+])
+
+
+# _LT_FILEUTILS_DEFAULTS
+# ----------------------
+# It is okay to use these file commands and assume they have been set
+# sensibly after `m4_require([_LT_FILEUTILS_DEFAULTS])'.
+m4_defun([_LT_FILEUTILS_DEFAULTS],
+[: ${CP="cp -f"}
+: ${MV="mv -f"}
+: ${RM="rm -f"}
+])# _LT_FILEUTILS_DEFAULTS
+
+
+# _LT_SETUP
+# ---------
+m4_defun([_LT_SETUP],
+[AC_REQUIRE([AC_CANONICAL_HOST])dnl
+AC_REQUIRE([AC_CANONICAL_BUILD])dnl
+AC_REQUIRE([_LT_PREPARE_SED_QUOTE_VARS])dnl
+AC_REQUIRE([_LT_PROG_ECHO_BACKSLASH])dnl
+
+_LT_DECL([], [PATH_SEPARATOR], [1], [The PATH separator for the build system])dnl
+dnl
+_LT_DECL([], [host_alias], [0], [The host system])dnl
+_LT_DECL([], [host], [0])dnl
+_LT_DECL([], [host_os], [0])dnl
+dnl
+_LT_DECL([], [build_alias], [0], [The build system])dnl
+_LT_DECL([], [build], [0])dnl
+_LT_DECL([], [build_os], [0])dnl
+dnl
+AC_REQUIRE([AC_PROG_CC])dnl
+AC_REQUIRE([LT_PATH_LD])dnl
+AC_REQUIRE([LT_PATH_NM])dnl
+dnl
+AC_REQUIRE([AC_PROG_LN_S])dnl
+test -z "$LN_S" && LN_S="ln -s"
+_LT_DECL([], [LN_S], [1], [Whether we need soft or hard links])dnl
+dnl
+AC_REQUIRE([LT_CMD_MAX_LEN])dnl
+_LT_DECL([objext], [ac_objext], [0], [Object file suffix (normally "o")])dnl
+_LT_DECL([], [exeext], [0], [Executable file suffix (normally "")])dnl
+dnl
+m4_require([_LT_FILEUTILS_DEFAULTS])dnl
+m4_require([_LT_CHECK_SHELL_FEATURES])dnl
+m4_require([_LT_PATH_CONVERSION_FUNCTIONS])dnl
+m4_require([_LT_CMD_RELOAD])dnl
+m4_require([_LT_CHECK_MAGIC_METHOD])dnl
+m4_require([_LT_CHECK_SHAREDLIB_FROM_LINKLIB])dnl
+m4_require([_LT_CMD_OLD_ARCHIVE])dnl
+m4_require([_LT_CMD_GLOBAL_SYMBOLS])dnl
+m4_require([_LT_WITH_SYSROOT])dnl
+
+_LT_CONFIG_LIBTOOL_INIT([
+# See if we are running on zsh, and set the options which allow our
+# commands through without removal of \ escapes INIT.
+if test -n "\${ZSH_VERSION+set}" ; then
+   setopt NO_GLOB_SUBST
+fi
+])
+if test -n "${ZSH_VERSION+set}" ; then
+   setopt NO_GLOB_SUBST
+fi
+
+_LT_CHECK_OBJDIR
+
+m4_require([_LT_TAG_COMPILER])dnl
+
+case $host_os in
+aix3*)
+  # AIX sometimes has problems with the GCC collect2 program.  For some
+  # reason, if we set the COLLECT_NAMES environment variable, the problems
+  # vanish in a puff of smoke.
+  if test "X${COLLECT_NAMES+set}" != Xset; then
+    COLLECT_NAMES=
+    export COLLECT_NAMES
+  fi
+  ;;
+esac
+
+# Global variables:
+ofile=libtool
+can_build_shared=yes
+
+# All known linkers require a `.a' archive for static linking (except MSVC,
+# which needs '.lib').
+libext=a
+
+with_gnu_ld="$lt_cv_prog_gnu_ld"
+
+old_CC="$CC"
+old_CFLAGS="$CFLAGS"
+
+# Set sane defaults for various variables
+test -z "$CC" && CC=cc
+test -z "$LTCC" && LTCC=$CC
+test -z "$LTCFLAGS" && LTCFLAGS=$CFLAGS
+test -z "$LD" && LD=ld
+test -z "$ac_objext" && ac_objext=o
+
+_LT_CC_BASENAME([$compiler])
+
+# Only perform the check for file, if the check method requires it
+test -z "$MAGIC_CMD" && MAGIC_CMD=file
+case $deplibs_check_method in
+file_magic*)
+  if test "$file_magic_cmd" = '$MAGIC_CMD'; then
+    _LT_PATH_MAGIC
+  fi
+  ;;
+esac
+
+# Use C for the default configuration in the libtool script
+LT_SUPPORTED_TAG([CC])
+_LT_LANG_C_CONFIG
+_LT_LANG_DEFAULT_CONFIG
+_LT_CONFIG_COMMANDS
+])# _LT_SETUP
+
+
+# _LT_PREPARE_SED_QUOTE_VARS
+# --------------------------
+# Define a few sed substitution that help us do robust quoting.
+m4_defun([_LT_PREPARE_SED_QUOTE_VARS],
+[# Backslashify metacharacters that are still active within
+# double-quoted strings.
+sed_quote_subst='s/\([["`$\\]]\)/\\\1/g'
+
+# Same as above, but do not quote variable references.
+double_quote_subst='s/\([["`\\]]\)/\\\1/g'
+
+# Sed substitution to delay expansion of an escaped shell variable in a
+# double_quote_subst'ed string.
+delay_variable_subst='s/\\\\\\\\\\\$/\\\\\\$/g'
+
+# Sed substitution to delay expansion of an escaped single quote.
+delay_single_quote_subst='s/'\''/'\'\\\\\\\'\''/g'
+
+# Sed substitution to avoid accidental globbing in evaled expressions
+no_glob_subst='s/\*/\\\*/g'
+])
+
+# _LT_PROG_LTMAIN
+# ---------------
+# Note that this code is called both from `configure', and `config.status'
+# now that we use AC_CONFIG_COMMANDS to generate libtool.  Notably,
+# `config.status' has no value for ac_aux_dir unless we are using Automake,
+# so we pass a copy along to make sure it has a sensible value anyway.
+m4_defun([_LT_PROG_LTMAIN],
+[m4_ifdef([AC_REQUIRE_AUX_FILE], [AC_REQUIRE_AUX_FILE([ltmain.sh])])dnl
+_LT_CONFIG_LIBTOOL_INIT([ac_aux_dir='$ac_aux_dir'])
+ltmain="$ac_aux_dir/ltmain.sh"
+])# _LT_PROG_LTMAIN
+
+
+## ------------------------------------- ##
+## Accumulate code for creating libtool. ##
+## ------------------------------------- ##
+
+# So that we can recreate a full libtool script including additional
+# tags, we accumulate the chunks of code to send to AC_CONFIG_COMMANDS
+# in macros and then make a single call at the end using the `libtool'
+# label.
+
+
+# _LT_CONFIG_LIBTOOL_INIT([INIT-COMMANDS])
+# ----------------------------------------
+# Register INIT-COMMANDS to be passed to AC_CONFIG_COMMANDS later.
+m4_define([_LT_CONFIG_LIBTOOL_INIT],
+[m4_ifval([$1],
+          [m4_append([_LT_OUTPUT_LIBTOOL_INIT],
+                     [$1
+])])])
+
+# Initialize.
+m4_define([_LT_OUTPUT_LIBTOOL_INIT])
+
+
+# _LT_CONFIG_LIBTOOL([COMMANDS])
+# ------------------------------
+# Register COMMANDS to be passed to AC_CONFIG_COMMANDS later.
+m4_define([_LT_CONFIG_LIBTOOL],
+[m4_ifval([$1],
+          [m4_append([_LT_OUTPUT_LIBTOOL_COMMANDS],
+                     [$1
+])])])
+
+# Initialize.
+m4_define([_LT_OUTPUT_LIBTOOL_COMMANDS])
+
+
+# _LT_CONFIG_SAVE_COMMANDS([COMMANDS], [INIT_COMMANDS])
+# -----------------------------------------------------
+m4_defun([_LT_CONFIG_SAVE_COMMANDS],
+[_LT_CONFIG_LIBTOOL([$1])
+_LT_CONFIG_LIBTOOL_INIT([$2])
+])
+
+
+# _LT_FORMAT_COMMENT([COMMENT])
+# -----------------------------
+# Add leading comment marks to the start of each line, and a trailing
+# full-stop to the whole comment if one is not present already.
+m4_define([_LT_FORMAT_COMMENT],
+[m4_ifval([$1], [
+m4_bpatsubst([m4_bpatsubst([$1], [^ *], [# ])],
+              [['`$\]], [\\\&])]m4_bmatch([$1], [[!?.]$], [], [.])
+)])
+
+
+
+## ------------------------ ##
+## FIXME: Eliminate VARNAME ##
+## ------------------------ ##
+
+
+# _LT_DECL([CONFIGNAME], VARNAME, VALUE, [DESCRIPTION], [IS-TAGGED?])
+# -------------------------------------------------------------------
+# CONFIGNAME is the name given to the value in the libtool script.
+# VARNAME is the (base) name used in the configure script.
+# VALUE may be 0, 1 or 2 for a computed quote escaped value based on
+# VARNAME.  Any other value will be used directly.
+m4_define([_LT_DECL],
+[lt_if_append_uniq([lt_decl_varnames], [$2], [, ],
+    [lt_dict_add_subkey([lt_decl_dict], [$2], [libtool_name],
+	[m4_ifval([$1], [$1], [$2])])
+    lt_dict_add_subkey([lt_decl_dict], [$2], [value], [$3])
+    m4_ifval([$4],
+	[lt_dict_add_subkey([lt_decl_dict], [$2], [description], [$4])])
+    lt_dict_add_subkey([lt_decl_dict], [$2],
+	[tagged?], [m4_ifval([$5], [yes], [no])])])
+])
+
+
+# _LT_TAGDECL([CONFIGNAME], VARNAME, VALUE, [DESCRIPTION])
+# --------------------------------------------------------
+m4_define([_LT_TAGDECL], [_LT_DECL([$1], [$2], [$3], [$4], [yes])])
+
+
+# lt_decl_tag_varnames([SEPARATOR], [VARNAME1...])
+# ------------------------------------------------
+m4_define([lt_decl_tag_varnames],
+[_lt_decl_filter([tagged?], [yes], $@)])
+
+
+# _lt_decl_filter(SUBKEY, VALUE, [SEPARATOR], [VARNAME1..])
+# ---------------------------------------------------------
+m4_define([_lt_decl_filter],
+[m4_case([$#],
+  [0], [m4_fatal([$0: too few arguments: $#])],
+  [1], [m4_fatal([$0: too few arguments: $#: $1])],
+  [2], [lt_dict_filter([lt_decl_dict], [$1], [$2], [], lt_decl_varnames)],
+  [3], [lt_dict_filter([lt_decl_dict], [$1], [$2], [$3], lt_decl_varnames)],
+  [lt_dict_filter([lt_decl_dict], $@)])[]dnl
+])
+
+
+# lt_decl_quote_varnames([SEPARATOR], [VARNAME1...])
+# --------------------------------------------------
+m4_define([lt_decl_quote_varnames],
+[_lt_decl_filter([value], [1], $@)])
+
+
+# lt_decl_dquote_varnames([SEPARATOR], [VARNAME1...])
+# ---------------------------------------------------
+m4_define([lt_decl_dquote_varnames],
+[_lt_decl_filter([value], [2], $@)])
+
+
+# lt_decl_varnames_tagged([SEPARATOR], [VARNAME1...])
+# ---------------------------------------------------
+m4_define([lt_decl_varnames_tagged],
+[m4_assert([$# <= 2])dnl
+_$0(m4_quote(m4_default([$1], [[, ]])),
+    m4_ifval([$2], [[$2]], [m4_dquote(lt_decl_tag_varnames)]),
+    m4_split(m4_normalize(m4_quote(_LT_TAGS)), [ ]))])
+m4_define([_lt_decl_varnames_tagged],
+[m4_ifval([$3], [lt_combine([$1], [$2], [_], $3)])])
+
+
+# lt_decl_all_varnames([SEPARATOR], [VARNAME1...])
+# ------------------------------------------------
+m4_define([lt_decl_all_varnames],
+[_$0(m4_quote(m4_default([$1], [[, ]])),
+     m4_if([$2], [],
+	   m4_quote(lt_decl_varnames),
+	m4_quote(m4_shift($@))))[]dnl
+])
+m4_define([_lt_decl_all_varnames],
+[lt_join($@, lt_decl_varnames_tagged([$1],
+			lt_decl_tag_varnames([[, ]], m4_shift($@))))dnl
+])
+
+
+# _LT_CONFIG_STATUS_DECLARE([VARNAME])
+# ------------------------------------
+# Quote a variable value, and forward it to `config.status' so that its
+# declaration there will have the same value as in `configure'.  VARNAME
+# must have a single quote delimited value for this to work.
+m4_define([_LT_CONFIG_STATUS_DECLARE],
+[$1='`$ECHO "$][$1" | $SED "$delay_single_quote_subst"`'])
+
+
+# _LT_CONFIG_STATUS_DECLARATIONS
+# ------------------------------
+# We delimit libtool config variables with single quotes, so when
+# we write them to config.status, we have to be sure to quote all
+# embedded single quotes properly.  In configure, this macro expands
+# each variable declared with _LT_DECL (and _LT_TAGDECL) into:
+#
+#    ='`$ECHO "$" | $SED "$delay_single_quote_subst"`'
+m4_defun([_LT_CONFIG_STATUS_DECLARATIONS],
+[m4_foreach([_lt_var], m4_quote(lt_decl_all_varnames),
+    [m4_n([_LT_CONFIG_STATUS_DECLARE(_lt_var)])])])
+
+
+# _LT_LIBTOOL_TAGS
+# ----------------
+# Output comment and list of tags supported by the script
+m4_defun([_LT_LIBTOOL_TAGS],
+[_LT_FORMAT_COMMENT([The names of the tagged configurations supported by this script])dnl
+available_tags="_LT_TAGS"dnl
+])
+
+
+# _LT_LIBTOOL_DECLARE(VARNAME, [TAG])
+# -----------------------------------
+# Extract the dictionary values for VARNAME (optionally with TAG) and
+# expand to a commented shell variable setting:
+#
+#    # Some comment about what VAR is for.
+#    visible_name=$lt_internal_name
+m4_define([_LT_LIBTOOL_DECLARE],
+[_LT_FORMAT_COMMENT(m4_quote(lt_dict_fetch([lt_decl_dict], [$1],
+					   [description])))[]dnl
+m4_pushdef([_libtool_name],
+    m4_quote(lt_dict_fetch([lt_decl_dict], [$1], [libtool_name])))[]dnl
+m4_case(m4_quote(lt_dict_fetch([lt_decl_dict], [$1], [value])),
+    [0], [_libtool_name=[$]$1],
+    [1], [_libtool_name=$lt_[]$1],
+    [2], [_libtool_name=$lt_[]$1],
+    [_libtool_name=lt_dict_fetch([lt_decl_dict], [$1], [value])])[]dnl
+m4_ifval([$2], [_$2])[]m4_popdef([_libtool_name])[]dnl
+])
+
+
+# _LT_LIBTOOL_CONFIG_VARS
+# -----------------------
+# Produce commented declarations of non-tagged libtool config variables
+# suitable for insertion in the LIBTOOL CONFIG section of the `libtool'
+# script.  Tagged libtool config variables (even for the LIBTOOL CONFIG
+# section) are produced by _LT_LIBTOOL_TAG_VARS.
+m4_defun([_LT_LIBTOOL_CONFIG_VARS],
+[m4_foreach([_lt_var],
+    m4_quote(_lt_decl_filter([tagged?], [no], [], lt_decl_varnames)),
+    [m4_n([_LT_LIBTOOL_DECLARE(_lt_var)])])])
+
+
+# _LT_LIBTOOL_TAG_VARS(TAG)
+# -------------------------
+m4_define([_LT_LIBTOOL_TAG_VARS],
+[m4_foreach([_lt_var], m4_quote(lt_decl_tag_varnames),
+    [m4_n([_LT_LIBTOOL_DECLARE(_lt_var, [$1])])])])
+
+
+# _LT_TAGVAR(VARNAME, [TAGNAME])
+# ------------------------------
+m4_define([_LT_TAGVAR], [m4_ifval([$2], [$1_$2], [$1])])
+
+
+# _LT_CONFIG_COMMANDS
+# -------------------
+# Send accumulated output to $CONFIG_STATUS.  Thanks to the lists of
+# variables for single and double quote escaping we saved from calls
+# to _LT_DECL, we can put quote escaped variables declarations
+# into `config.status', and then the shell code to quote escape them in
+# for loops in `config.status'.  Finally, any additional code accumulated
+# from calls to _LT_CONFIG_LIBTOOL_INIT is expanded.
+m4_defun([_LT_CONFIG_COMMANDS],
+[AC_PROVIDE_IFELSE([LT_OUTPUT],
+	dnl If the libtool generation code has been placed in $CONFIG_LT,
+	dnl instead of duplicating it all over again into config.status,
+	dnl then we will have config.status run $CONFIG_LT later, so it
+	dnl needs to know what name is stored there:
+        [AC_CONFIG_COMMANDS([libtool],
+            [$SHELL $CONFIG_LT || AS_EXIT(1)], [CONFIG_LT='$CONFIG_LT'])],
+    dnl If the libtool generation code is destined for config.status,
+    dnl expand the accumulated commands and init code now:
+    [AC_CONFIG_COMMANDS([libtool],
+        [_LT_OUTPUT_LIBTOOL_COMMANDS], [_LT_OUTPUT_LIBTOOL_COMMANDS_INIT])])
+])#_LT_CONFIG_COMMANDS
+
+
+# Initialize.
+m4_define([_LT_OUTPUT_LIBTOOL_COMMANDS_INIT],
+[
+
+# The HP-UX ksh and POSIX shell print the target directory to stdout
+# if CDPATH is set.
+(unset CDPATH) >/dev/null 2>&1 && unset CDPATH
+
+sed_quote_subst='$sed_quote_subst'
+double_quote_subst='$double_quote_subst'
+delay_variable_subst='$delay_variable_subst'
+_LT_CONFIG_STATUS_DECLARATIONS
+LTCC='$LTCC'
+LTCFLAGS='$LTCFLAGS'
+compiler='$compiler_DEFAULT'
+
+# A function that is used when there is no print builtin or printf.
+func_fallback_echo ()
+{
+  eval 'cat <<_LTECHO_EOF
+\$[]1
+_LTECHO_EOF'
+}
+
+# Quote evaled strings.
+for var in lt_decl_all_varnames([[ \
+]], lt_decl_quote_varnames); do
+    case \`eval \\\\\$ECHO \\\\""\\\\\$\$var"\\\\"\` in
+    *[[\\\\\\\`\\"\\\$]]*)
+      eval "lt_\$var=\\\\\\"\\\`\\\$ECHO \\"\\\$\$var\\" | \\\$SED \\"\\\$sed_quote_subst\\"\\\`\\\\\\""
+      ;;
+    *)
+      eval "lt_\$var=\\\\\\"\\\$\$var\\\\\\""
+      ;;
+    esac
+done
+
+# Double-quote double-evaled strings.
+for var in lt_decl_all_varnames([[ \
+]], lt_decl_dquote_varnames); do
+    case \`eval \\\\\$ECHO \\\\""\\\\\$\$var"\\\\"\` in
+    *[[\\\\\\\`\\"\\\$]]*)
+      eval "lt_\$var=\\\\\\"\\\`\\\$ECHO \\"\\\$\$var\\" | \\\$SED -e \\"\\\$double_quote_subst\\" -e \\"\\\$sed_quote_subst\\" -e \\"\\\$delay_variable_subst\\"\\\`\\\\\\""
+      ;;
+    *)
+      eval "lt_\$var=\\\\\\"\\\$\$var\\\\\\""
+      ;;
+    esac
+done
+
+_LT_OUTPUT_LIBTOOL_INIT
+])
+
+# _LT_GENERATED_FILE_INIT(FILE, [COMMENT])
+# ------------------------------------
+# Generate a child script FILE with all initialization necessary to
+# reuse the environment learned by the parent script, and make the
+# file executable.  If COMMENT is supplied, it is inserted after the
+# `#!' sequence but before initialization text begins.  After this
+# macro, additional text can be appended to FILE to form the body of
+# the child script.  The macro ends with non-zero status if the
+# file could not be fully written (such as if the disk is full).
+m4_ifdef([AS_INIT_GENERATED],
+[m4_defun([_LT_GENERATED_FILE_INIT],[AS_INIT_GENERATED($@)])],
+[m4_defun([_LT_GENERATED_FILE_INIT],
+[m4_require([AS_PREPARE])]dnl
+[m4_pushdef([AS_MESSAGE_LOG_FD])]dnl
+[lt_write_fail=0
+cat >$1 <<_ASEOF || lt_write_fail=1
+#! $SHELL
+# Generated by $as_me.
+$2
+SHELL=\${CONFIG_SHELL-$SHELL}
+export SHELL
+_ASEOF
+cat >>$1 <<\_ASEOF || lt_write_fail=1
+AS_SHELL_SANITIZE
+_AS_PREPARE
+exec AS_MESSAGE_FD>&1
+_ASEOF
+test $lt_write_fail = 0 && chmod +x $1[]dnl
+m4_popdef([AS_MESSAGE_LOG_FD])])])# _LT_GENERATED_FILE_INIT
+
+# LT_OUTPUT
+# ---------
+# This macro allows early generation of the libtool script (before
+# AC_OUTPUT is called), incase it is used in configure for compilation
+# tests.
+AC_DEFUN([LT_OUTPUT],
+[: ${CONFIG_LT=./config.lt}
+AC_MSG_NOTICE([creating $CONFIG_LT])
+_LT_GENERATED_FILE_INIT(["$CONFIG_LT"],
+[# Run this file to recreate a libtool stub with the current configuration.])
+
+cat >>"$CONFIG_LT" <<\_LTEOF
+lt_cl_silent=false
+exec AS_MESSAGE_LOG_FD>>config.log
+{
+  echo
+  AS_BOX([Running $as_me.])
+} >&AS_MESSAGE_LOG_FD
+
+lt_cl_help="\
+\`$as_me' creates a local libtool stub from the current configuration,
+for use in further configure time tests before the real libtool is
+generated.
+
+Usage: $[0] [[OPTIONS]]
+
+  -h, --help      print this help, then exit
+  -V, --version   print version number, then exit
+  -q, --quiet     do not print progress messages
+  -d, --debug     don't remove temporary files
+
+Report bugs to ."
+
+lt_cl_version="\
+m4_ifset([AC_PACKAGE_NAME], [AC_PACKAGE_NAME ])config.lt[]dnl
+m4_ifset([AC_PACKAGE_VERSION], [ AC_PACKAGE_VERSION])
+configured by $[0], generated by m4_PACKAGE_STRING.
+
+Copyright (C) 2011 Free Software Foundation, Inc.
+This config.lt script is free software; the Free Software Foundation
+gives unlimited permision to copy, distribute and modify it."
+
+while test $[#] != 0
+do
+  case $[1] in
+    --version | --v* | -V )
+      echo "$lt_cl_version"; exit 0 ;;
+    --help | --h* | -h )
+      echo "$lt_cl_help"; exit 0 ;;
+    --debug | --d* | -d )
+      debug=: ;;
+    --quiet | --q* | --silent | --s* | -q )
+      lt_cl_silent=: ;;
+
+    -*) AC_MSG_ERROR([unrecognized option: $[1]
+Try \`$[0] --help' for more information.]) ;;
+
+    *) AC_MSG_ERROR([unrecognized argument: $[1]
+Try \`$[0] --help' for more information.]) ;;
+  esac
+  shift
+done
+
+if $lt_cl_silent; then
+  exec AS_MESSAGE_FD>/dev/null
+fi
+_LTEOF
+
+cat >>"$CONFIG_LT" <<_LTEOF
+_LT_OUTPUT_LIBTOOL_COMMANDS_INIT
+_LTEOF
+
+cat >>"$CONFIG_LT" <<\_LTEOF
+AC_MSG_NOTICE([creating $ofile])
+_LT_OUTPUT_LIBTOOL_COMMANDS
+AS_EXIT(0)
+_LTEOF
+chmod +x "$CONFIG_LT"
+
+# configure is writing to config.log, but config.lt does its own redirection,
+# appending to config.log, which fails on DOS, as config.log is still kept
+# open by configure.  Here we exec the FD to /dev/null, effectively closing
+# config.log, so it can be properly (re)opened and appended to by config.lt.
+lt_cl_success=:
+test "$silent" = yes &&
+  lt_config_lt_args="$lt_config_lt_args --quiet"
+exec AS_MESSAGE_LOG_FD>/dev/null
+$SHELL "$CONFIG_LT" $lt_config_lt_args || lt_cl_success=false
+exec AS_MESSAGE_LOG_FD>>config.log
+$lt_cl_success || AS_EXIT(1)
+])# LT_OUTPUT
+
+
+# _LT_CONFIG(TAG)
+# ---------------
+# If TAG is the built-in tag, create an initial libtool script with a
+# default configuration from the untagged config vars.  Otherwise add code
+# to config.status for appending the configuration named by TAG from the
+# matching tagged config vars.
+m4_defun([_LT_CONFIG],
+[m4_require([_LT_FILEUTILS_DEFAULTS])dnl
+_LT_CONFIG_SAVE_COMMANDS([
+  m4_define([_LT_TAG], m4_if([$1], [], [C], [$1]))dnl
+  m4_if(_LT_TAG, [C], [
+    # See if we are running on zsh, and set the options which allow our
+    # commands through without removal of \ escapes.
+    if test -n "${ZSH_VERSION+set}" ; then
+      setopt NO_GLOB_SUBST
+    fi
+
+    cfgfile="${ofile}T"
+    trap "$RM \"$cfgfile\"; exit 1" 1 2 15
+    $RM "$cfgfile"
+
+    cat <<_LT_EOF >> "$cfgfile"
+#! $SHELL
+
+# `$ECHO "$ofile" | sed 's%^.*/%%'` - Provide generalized library-building support services.
+# Generated automatically by $as_me ($PACKAGE$TIMESTAMP) $VERSION
+# Libtool was configured on host `(hostname || uname -n) 2>/dev/null | sed 1q`:
+# NOTE: Changes made to this file will be lost: look at ltmain.sh.
+#
+_LT_COPYING
+_LT_LIBTOOL_TAGS
+
+# ### BEGIN LIBTOOL CONFIG
+_LT_LIBTOOL_CONFIG_VARS
+_LT_LIBTOOL_TAG_VARS
+# ### END LIBTOOL CONFIG
+
+_LT_EOF
+
+  case $host_os in
+  aix3*)
+    cat <<\_LT_EOF >> "$cfgfile"
+# AIX sometimes has problems with the GCC collect2 program.  For some
+# reason, if we set the COLLECT_NAMES environment variable, the problems
+# vanish in a puff of smoke.
+if test "X${COLLECT_NAMES+set}" != Xset; then
+  COLLECT_NAMES=
+  export COLLECT_NAMES
+fi
+_LT_EOF
+    ;;
+  esac
+
+  _LT_PROG_LTMAIN
+
+  # We use sed instead of cat because bash on DJGPP gets confused if
+  # if finds mixed CR/LF and LF-only lines.  Since sed operates in
+  # text mode, it properly converts lines to CR/LF.  This bash problem
+  # is reportedly fixed, but why not run on old versions too?
+  sed '$q' "$ltmain" >> "$cfgfile" \
+     || (rm -f "$cfgfile"; exit 1)
+
+  _LT_PROG_REPLACE_SHELLFNS
+
+   mv -f "$cfgfile" "$ofile" ||
+    (rm -f "$ofile" && cp "$cfgfile" "$ofile" && rm -f "$cfgfile")
+  chmod +x "$ofile"
+],
+[cat <<_LT_EOF >> "$ofile"
+
+dnl Unfortunately we have to use $1 here, since _LT_TAG is not expanded
+dnl in a comment (ie after a #).
+# ### BEGIN LIBTOOL TAG CONFIG: $1
+_LT_LIBTOOL_TAG_VARS(_LT_TAG)
+# ### END LIBTOOL TAG CONFIG: $1
+_LT_EOF
+])dnl /m4_if
+],
+[m4_if([$1], [], [
+    PACKAGE='$PACKAGE'
+    VERSION='$VERSION'
+    TIMESTAMP='$TIMESTAMP'
+    RM='$RM'
+    ofile='$ofile'], [])
+])dnl /_LT_CONFIG_SAVE_COMMANDS
+])# _LT_CONFIG
+
+
+# LT_SUPPORTED_TAG(TAG)
+# ---------------------
+# Trace this macro to discover what tags are supported by the libtool
+# --tag option, using:
+#    autoconf --trace 'LT_SUPPORTED_TAG:$1'
+AC_DEFUN([LT_SUPPORTED_TAG], [])
+
+
+# C support is built-in for now
+m4_define([_LT_LANG_C_enabled], [])
+m4_define([_LT_TAGS], [])
+
+
+# LT_LANG(LANG)
+# -------------
+# Enable libtool support for the given language if not already enabled.
+AC_DEFUN([LT_LANG],
+[AC_BEFORE([$0], [LT_OUTPUT])dnl
+m4_case([$1],
+  [C],			[_LT_LANG(C)],
+  [C++],		[_LT_LANG(CXX)],
+  [Go],			[_LT_LANG(GO)],
+  [Java],		[_LT_LANG(GCJ)],
+  [Fortran 77],		[_LT_LANG(F77)],
+  [Fortran],		[_LT_LANG(FC)],
+  [Windows Resource],	[_LT_LANG(RC)],
+  [m4_ifdef([_LT_LANG_]$1[_CONFIG],
+    [_LT_LANG($1)],
+    [m4_fatal([$0: unsupported language: "$1"])])])dnl
+])# LT_LANG
+
+
+# _LT_LANG(LANGNAME)
+# ------------------
+m4_defun([_LT_LANG],
+[m4_ifdef([_LT_LANG_]$1[_enabled], [],
+  [LT_SUPPORTED_TAG([$1])dnl
+  m4_append([_LT_TAGS], [$1 ])dnl
+  m4_define([_LT_LANG_]$1[_enabled], [])dnl
+  _LT_LANG_$1_CONFIG($1)])dnl
+])# _LT_LANG
+
+
+m4_ifndef([AC_PROG_GO], [
+############################################################
+# NOTE: This macro has been submitted for inclusion into   #
+#  GNU Autoconf as AC_PROG_GO.  When it is available in    #
+#  a released version of Autoconf we should remove this    #
+#  macro and use it instead.                               #
+############################################################
+m4_defun([AC_PROG_GO],
+[AC_LANG_PUSH(Go)dnl
+AC_ARG_VAR([GOC],     [Go compiler command])dnl
+AC_ARG_VAR([GOFLAGS], [Go compiler flags])dnl
+_AC_ARG_VAR_LDFLAGS()dnl
+AC_CHECK_TOOL(GOC, gccgo)
+if test -z "$GOC"; then
+  if test -n "$ac_tool_prefix"; then
+    AC_CHECK_PROG(GOC, [${ac_tool_prefix}gccgo], [${ac_tool_prefix}gccgo])
+  fi
+fi
+if test -z "$GOC"; then
+  AC_CHECK_PROG(GOC, gccgo, gccgo, false)
+fi
+])#m4_defun
+])#m4_ifndef
+
+
+# _LT_LANG_DEFAULT_CONFIG
+# -----------------------
+m4_defun([_LT_LANG_DEFAULT_CONFIG],
+[AC_PROVIDE_IFELSE([AC_PROG_CXX],
+  [LT_LANG(CXX)],
+  [m4_define([AC_PROG_CXX], defn([AC_PROG_CXX])[LT_LANG(CXX)])])
+
+AC_PROVIDE_IFELSE([AC_PROG_F77],
+  [LT_LANG(F77)],
+  [m4_define([AC_PROG_F77], defn([AC_PROG_F77])[LT_LANG(F77)])])
+
+AC_PROVIDE_IFELSE([AC_PROG_FC],
+  [LT_LANG(FC)],
+  [m4_define([AC_PROG_FC], defn([AC_PROG_FC])[LT_LANG(FC)])])
+
+dnl The call to [A][M_PROG_GCJ] is quoted like that to stop aclocal
+dnl pulling things in needlessly.
+AC_PROVIDE_IFELSE([AC_PROG_GCJ],
+  [LT_LANG(GCJ)],
+  [AC_PROVIDE_IFELSE([A][M_PROG_GCJ],
+    [LT_LANG(GCJ)],
+    [AC_PROVIDE_IFELSE([LT_PROG_GCJ],
+      [LT_LANG(GCJ)],
+      [m4_ifdef([AC_PROG_GCJ],
+	[m4_define([AC_PROG_GCJ], defn([AC_PROG_GCJ])[LT_LANG(GCJ)])])
+       m4_ifdef([A][M_PROG_GCJ],
+	[m4_define([A][M_PROG_GCJ], defn([A][M_PROG_GCJ])[LT_LANG(GCJ)])])
+       m4_ifdef([LT_PROG_GCJ],
+	[m4_define([LT_PROG_GCJ], defn([LT_PROG_GCJ])[LT_LANG(GCJ)])])])])])
+
+AC_PROVIDE_IFELSE([AC_PROG_GO],
+  [LT_LANG(GO)],
+  [m4_define([AC_PROG_GO], defn([AC_PROG_GO])[LT_LANG(GO)])])
+
+AC_PROVIDE_IFELSE([LT_PROG_RC],
+  [LT_LANG(RC)],
+  [m4_define([LT_PROG_RC], defn([LT_PROG_RC])[LT_LANG(RC)])])
+])# _LT_LANG_DEFAULT_CONFIG
+
+# Obsolete macros:
+AU_DEFUN([AC_LIBTOOL_CXX], [LT_LANG(C++)])
+AU_DEFUN([AC_LIBTOOL_F77], [LT_LANG(Fortran 77)])
+AU_DEFUN([AC_LIBTOOL_FC], [LT_LANG(Fortran)])
+AU_DEFUN([AC_LIBTOOL_GCJ], [LT_LANG(Java)])
+AU_DEFUN([AC_LIBTOOL_RC], [LT_LANG(Windows Resource)])
+dnl aclocal-1.4 backwards compatibility:
+dnl AC_DEFUN([AC_LIBTOOL_CXX], [])
+dnl AC_DEFUN([AC_LIBTOOL_F77], [])
+dnl AC_DEFUN([AC_LIBTOOL_FC], [])
+dnl AC_DEFUN([AC_LIBTOOL_GCJ], [])
+dnl AC_DEFUN([AC_LIBTOOL_RC], [])
+
+
+# _LT_TAG_COMPILER
+# ----------------
+m4_defun([_LT_TAG_COMPILER],
+[AC_REQUIRE([AC_PROG_CC])dnl
+
+_LT_DECL([LTCC], [CC], [1], [A C compiler])dnl
+_LT_DECL([LTCFLAGS], [CFLAGS], [1], [LTCC compiler flags])dnl
+_LT_TAGDECL([CC], [compiler], [1], [A language specific compiler])dnl
+_LT_TAGDECL([with_gcc], [GCC], [0], [Is the compiler the GNU compiler?])dnl
+
+# If no C compiler was specified, use CC.
+LTCC=${LTCC-"$CC"}
+
+# If no C compiler flags were specified, use CFLAGS.
+LTCFLAGS=${LTCFLAGS-"$CFLAGS"}
+
+# Allow CC to be a program name with arguments.
+compiler=$CC
+])# _LT_TAG_COMPILER
+
+
+# _LT_COMPILER_BOILERPLATE
+# ------------------------
+# Check for compiler boilerplate output or warnings with
+# the simple compiler test code.
+m4_defun([_LT_COMPILER_BOILERPLATE],
+[m4_require([_LT_DECL_SED])dnl
+ac_outfile=conftest.$ac_objext
+echo "$lt_simple_compile_test_code" >conftest.$ac_ext
+eval "$ac_compile" 2>&1 >/dev/null | $SED '/^$/d; /^ *+/d' >conftest.err
+_lt_compiler_boilerplate=`cat conftest.err`
+$RM conftest*
+])# _LT_COMPILER_BOILERPLATE
+
+
+# _LT_LINKER_BOILERPLATE
+# ----------------------
+# Check for linker boilerplate output or warnings with
+# the simple link test code.
+m4_defun([_LT_LINKER_BOILERPLATE],
+[m4_require([_LT_DECL_SED])dnl
+ac_outfile=conftest.$ac_objext
+echo "$lt_simple_link_test_code" >conftest.$ac_ext
+eval "$ac_link" 2>&1 >/dev/null | $SED '/^$/d; /^ *+/d' >conftest.err
+_lt_linker_boilerplate=`cat conftest.err`
+$RM -r conftest*
+])# _LT_LINKER_BOILERPLATE
+
+# _LT_REQUIRED_DARWIN_CHECKS
+# -------------------------
+m4_defun_once([_LT_REQUIRED_DARWIN_CHECKS],[
+  case $host_os in
+    rhapsody* | darwin*)
+    AC_CHECK_TOOL([DSYMUTIL], [dsymutil], [:])
+    AC_CHECK_TOOL([NMEDIT], [nmedit], [:])
+    AC_CHECK_TOOL([LIPO], [lipo], [:])
+    AC_CHECK_TOOL([OTOOL], [otool], [:])
+    AC_CHECK_TOOL([OTOOL64], [otool64], [:])
+    _LT_DECL([], [DSYMUTIL], [1],
+      [Tool to manipulate archived DWARF debug symbol files on Mac OS X])
+    _LT_DECL([], [NMEDIT], [1],
+      [Tool to change global to local symbols on Mac OS X])
+    _LT_DECL([], [LIPO], [1],
+      [Tool to manipulate fat objects and archives on Mac OS X])
+    _LT_DECL([], [OTOOL], [1],
+      [ldd/readelf like tool for Mach-O binaries on Mac OS X])
+    _LT_DECL([], [OTOOL64], [1],
+      [ldd/readelf like tool for 64 bit Mach-O binaries on Mac OS X 10.4])
+
+    AC_CACHE_CHECK([for -single_module linker flag],[lt_cv_apple_cc_single_mod],
+      [lt_cv_apple_cc_single_mod=no
+      if test -z "${LT_MULTI_MODULE}"; then
+	# By default we will add the -single_module flag. You can override
+	# by either setting the environment variable LT_MULTI_MODULE
+	# non-empty at configure time, or by adding -multi_module to the
+	# link flags.
+	rm -rf libconftest.dylib*
+	echo "int foo(void){return 1;}" > conftest.c
+	echo "$LTCC $LTCFLAGS $LDFLAGS -o libconftest.dylib \
+-dynamiclib -Wl,-single_module conftest.c" >&AS_MESSAGE_LOG_FD
+	$LTCC $LTCFLAGS $LDFLAGS -o libconftest.dylib \
+	  -dynamiclib -Wl,-single_module conftest.c 2>conftest.err
+        _lt_result=$?
+	# If there is a non-empty error log, and "single_module"
+	# appears in it, assume the flag caused a linker warning
+        if test -s conftest.err && $GREP single_module conftest.err; then
+	  cat conftest.err >&AS_MESSAGE_LOG_FD
+	# Otherwise, if the output was created with a 0 exit code from
+	# the compiler, it worked.
+	elif test -f libconftest.dylib && test $_lt_result -eq 0; then
+	  lt_cv_apple_cc_single_mod=yes
+	else
+	  cat conftest.err >&AS_MESSAGE_LOG_FD
+	fi
+	rm -rf libconftest.dylib*
+	rm -f conftest.*
+      fi])
+
+    AC_CACHE_CHECK([for -exported_symbols_list linker flag],
+      [lt_cv_ld_exported_symbols_list],
+      [lt_cv_ld_exported_symbols_list=no
+      save_LDFLAGS=$LDFLAGS
+      echo "_main" > conftest.sym
+      LDFLAGS="$LDFLAGS -Wl,-exported_symbols_list,conftest.sym"
+      AC_LINK_IFELSE([AC_LANG_PROGRAM([],[])],
+	[lt_cv_ld_exported_symbols_list=yes],
+	[lt_cv_ld_exported_symbols_list=no])
+	LDFLAGS="$save_LDFLAGS"
+    ])
+
+    AC_CACHE_CHECK([for -force_load linker flag],[lt_cv_ld_force_load],
+      [lt_cv_ld_force_load=no
+      cat > conftest.c << _LT_EOF
+int forced_loaded() { return 2;}
+_LT_EOF
+      echo "$LTCC $LTCFLAGS -c -o conftest.o conftest.c" >&AS_MESSAGE_LOG_FD
+      $LTCC $LTCFLAGS -c -o conftest.o conftest.c 2>&AS_MESSAGE_LOG_FD
+      echo "$AR cru libconftest.a conftest.o" >&AS_MESSAGE_LOG_FD
+      $AR cru libconftest.a conftest.o 2>&AS_MESSAGE_LOG_FD
+      echo "$RANLIB libconftest.a" >&AS_MESSAGE_LOG_FD
+      $RANLIB libconftest.a 2>&AS_MESSAGE_LOG_FD
+      cat > conftest.c << _LT_EOF
+int main() { return 0;}
+_LT_EOF
+      echo "$LTCC $LTCFLAGS $LDFLAGS -o conftest conftest.c -Wl,-force_load,./libconftest.a" >&AS_MESSAGE_LOG_FD
+      $LTCC $LTCFLAGS $LDFLAGS -o conftest conftest.c -Wl,-force_load,./libconftest.a 2>conftest.err
+      _lt_result=$?
+      if test -s conftest.err && $GREP force_load conftest.err; then
+	cat conftest.err >&AS_MESSAGE_LOG_FD
+      elif test -f conftest && test $_lt_result -eq 0 && $GREP forced_load conftest >/dev/null 2>&1 ; then
+	lt_cv_ld_force_load=yes
+      else
+	cat conftest.err >&AS_MESSAGE_LOG_FD
+      fi
+        rm -f conftest.err libconftest.a conftest conftest.c
+        rm -rf conftest.dSYM
+    ])
+    case $host_os in
+    rhapsody* | darwin1.[[012]])
+      _lt_dar_allow_undefined='${wl}-undefined ${wl}suppress' ;;
+    darwin1.*)
+      _lt_dar_allow_undefined='${wl}-flat_namespace ${wl}-undefined ${wl}suppress' ;;
+    darwin*) # darwin 5.x on
+      # if running on 10.5 or later, the deployment target defaults
+      # to the OS version, if on x86, and 10.4, the deployment
+      # target defaults to 10.4. Don't you love it?
+      case ${MACOSX_DEPLOYMENT_TARGET-10.0},$host in
+	10.0,*86*-darwin8*|10.0,*-darwin[[91]]*)
+	  _lt_dar_allow_undefined='${wl}-undefined ${wl}dynamic_lookup' ;;
+	10.[[012]][[,.]]*)
+	  _lt_dar_allow_undefined='${wl}-flat_namespace ${wl}-undefined ${wl}suppress' ;;
+	10.*)
+	  _lt_dar_allow_undefined='${wl}-undefined ${wl}dynamic_lookup' ;;
+      esac
+    ;;
+  esac
+    if test "$lt_cv_apple_cc_single_mod" = "yes"; then
+      _lt_dar_single_mod='$single_module'
+    fi
+    if test "$lt_cv_ld_exported_symbols_list" = "yes"; then
+      _lt_dar_export_syms=' ${wl}-exported_symbols_list,$output_objdir/${libname}-symbols.expsym'
+    else
+      _lt_dar_export_syms='~$NMEDIT -s $output_objdir/${libname}-symbols.expsym ${lib}'
+    fi
+    if test "$DSYMUTIL" != ":" && test "$lt_cv_ld_force_load" = "no"; then
+      _lt_dsymutil='~$DSYMUTIL $lib || :'
+    else
+      _lt_dsymutil=
+    fi
+    ;;
+  esac
+])
+
+
+# _LT_DARWIN_LINKER_FEATURES([TAG])
+# ---------------------------------
+# Checks for linker and compiler features on darwin
+m4_defun([_LT_DARWIN_LINKER_FEATURES],
+[
+  m4_require([_LT_REQUIRED_DARWIN_CHECKS])
+  _LT_TAGVAR(archive_cmds_need_lc, $1)=no
+  _LT_TAGVAR(hardcode_direct, $1)=no
+  _LT_TAGVAR(hardcode_automatic, $1)=yes
+  _LT_TAGVAR(hardcode_shlibpath_var, $1)=unsupported
+  if test "$lt_cv_ld_force_load" = "yes"; then
+    _LT_TAGVAR(whole_archive_flag_spec, $1)='`for conv in $convenience\"\"; do test  -n \"$conv\" && new_convenience=\"$new_convenience ${wl}-force_load,$conv\"; done; func_echo_all \"$new_convenience\"`'
+    m4_case([$1], [F77], [_LT_TAGVAR(compiler_needs_object, $1)=yes],
+                  [FC],  [_LT_TAGVAR(compiler_needs_object, $1)=yes])
+  else
+    _LT_TAGVAR(whole_archive_flag_spec, $1)=''
+  fi
+  _LT_TAGVAR(link_all_deplibs, $1)=yes
+  _LT_TAGVAR(allow_undefined_flag, $1)="$_lt_dar_allow_undefined"
+  case $cc_basename in
+     ifort*) _lt_dar_can_shared=yes ;;
+     *) _lt_dar_can_shared=$GCC ;;
+  esac
+  if test "$_lt_dar_can_shared" = "yes"; then
+    output_verbose_link_cmd=func_echo_all
+    _LT_TAGVAR(archive_cmds, $1)="\$CC -dynamiclib \$allow_undefined_flag -o \$lib \$libobjs \$deplibs \$compiler_flags -install_name \$rpath/\$soname \$verstring $_lt_dar_single_mod${_lt_dsymutil}"
+    _LT_TAGVAR(module_cmds, $1)="\$CC \$allow_undefined_flag -o \$lib -bundle \$libobjs \$deplibs \$compiler_flags${_lt_dsymutil}"
+    _LT_TAGVAR(archive_expsym_cmds, $1)="sed 's,^,_,' < \$export_symbols > \$output_objdir/\${libname}-symbols.expsym~\$CC -dynamiclib \$allow_undefined_flag -o \$lib \$libobjs \$deplibs \$compiler_flags -install_name \$rpath/\$soname \$verstring ${_lt_dar_single_mod}${_lt_dar_export_syms}${_lt_dsymutil}"
+    _LT_TAGVAR(module_expsym_cmds, $1)="sed -e 's,^,_,' < \$export_symbols > \$output_objdir/\${libname}-symbols.expsym~\$CC \$allow_undefined_flag -o \$lib -bundle \$libobjs \$deplibs \$compiler_flags${_lt_dar_export_syms}${_lt_dsymutil}"
+    m4_if([$1], [CXX],
+[   if test "$lt_cv_apple_cc_single_mod" != "yes"; then
+      _LT_TAGVAR(archive_cmds, $1)="\$CC -r -keep_private_externs -nostdlib -o \${lib}-master.o \$libobjs~\$CC -dynamiclib \$allow_undefined_flag -o \$lib \${lib}-master.o \$deplibs \$compiler_flags -install_name \$rpath/\$soname \$verstring${_lt_dsymutil}"
+      _LT_TAGVAR(archive_expsym_cmds, $1)="sed 's,^,_,' < \$export_symbols > \$output_objdir/\${libname}-symbols.expsym~\$CC -r -keep_private_externs -nostdlib -o \${lib}-master.o \$libobjs~\$CC -dynamiclib \$allow_undefined_flag -o \$lib \${lib}-master.o \$deplibs \$compiler_flags -install_name \$rpath/\$soname \$verstring${_lt_dar_export_syms}${_lt_dsymutil}"
+    fi
+],[])
+  else
+  _LT_TAGVAR(ld_shlibs, $1)=no
+  fi
+])
+
+# _LT_SYS_MODULE_PATH_AIX([TAGNAME])
+# ----------------------------------
+# Links a minimal program and checks the executable
+# for the system default hardcoded library path. In most cases,
+# this is /usr/lib:/lib, but when the MPI compilers are used
+# the location of the communication and MPI libs are included too.
+# If we don't find anything, use the default library path according
+# to the aix ld manual.
+# Store the results from the different compilers for each TAGNAME.
+# Allow to override them for all tags through lt_cv_aix_libpath.
+m4_defun([_LT_SYS_MODULE_PATH_AIX],
+[m4_require([_LT_DECL_SED])dnl
+if test "${lt_cv_aix_libpath+set}" = set; then
+  aix_libpath=$lt_cv_aix_libpath
+else
+  AC_CACHE_VAL([_LT_TAGVAR([lt_cv_aix_libpath_], [$1])],
+  [AC_LINK_IFELSE([AC_LANG_PROGRAM],[
+  lt_aix_libpath_sed='[
+      /Import File Strings/,/^$/ {
+	  /^0/ {
+	      s/^0  *\([^ ]*\) *$/\1/
+	      p
+	  }
+      }]'
+  _LT_TAGVAR([lt_cv_aix_libpath_], [$1])=`dump -H conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"`
+  # Check for a 64-bit object if we didn't find anything.
+  if test -z "$_LT_TAGVAR([lt_cv_aix_libpath_], [$1])"; then
+    _LT_TAGVAR([lt_cv_aix_libpath_], [$1])=`dump -HX64 conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"`
+  fi],[])
+  if test -z "$_LT_TAGVAR([lt_cv_aix_libpath_], [$1])"; then
+    _LT_TAGVAR([lt_cv_aix_libpath_], [$1])="/usr/lib:/lib"
+  fi
+  ])
+  aix_libpath=$_LT_TAGVAR([lt_cv_aix_libpath_], [$1])
+fi
+])# _LT_SYS_MODULE_PATH_AIX
+
+
+# _LT_SHELL_INIT(ARG)
+# -------------------
+m4_define([_LT_SHELL_INIT],
+[m4_divert_text([M4SH-INIT], [$1
+])])# _LT_SHELL_INIT
+
+
+
+# _LT_PROG_ECHO_BACKSLASH
+# -----------------------
+# Find how we can fake an echo command that does not interpret backslash.
+# In particular, with Autoconf 2.60 or later we add some code to the start
+# of the generated configure script which will find a shell with a builtin
+# printf (which we can use as an echo command).
+m4_defun([_LT_PROG_ECHO_BACKSLASH],
+[ECHO='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\'
+ECHO=$ECHO$ECHO$ECHO$ECHO$ECHO
+ECHO=$ECHO$ECHO$ECHO$ECHO$ECHO$ECHO
+
+AC_MSG_CHECKING([how to print strings])
+# Test print first, because it will be a builtin if present.
+if test "X`( print -r -- -n ) 2>/dev/null`" = X-n && \
+   test "X`print -r -- $ECHO 2>/dev/null`" = "X$ECHO"; then
+  ECHO='print -r --'
+elif test "X`printf %s $ECHO 2>/dev/null`" = "X$ECHO"; then
+  ECHO='printf %s\n'
+else
+  # Use this function as a fallback that always works.
+  func_fallback_echo ()
+  {
+    eval 'cat <<_LTECHO_EOF
+$[]1
+_LTECHO_EOF'
+  }
+  ECHO='func_fallback_echo'
+fi
+
+# func_echo_all arg...
+# Invoke $ECHO with all args, space-separated.
+func_echo_all ()
+{
+    $ECHO "$*" 
+}
+
+case "$ECHO" in
+  printf*) AC_MSG_RESULT([printf]) ;;
+  print*) AC_MSG_RESULT([print -r]) ;;
+  *) AC_MSG_RESULT([cat]) ;;
+esac
+
+m4_ifdef([_AS_DETECT_SUGGESTED],
+[_AS_DETECT_SUGGESTED([
+  test -n "${ZSH_VERSION+set}${BASH_VERSION+set}" || (
+    ECHO='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\'
+    ECHO=$ECHO$ECHO$ECHO$ECHO$ECHO
+    ECHO=$ECHO$ECHO$ECHO$ECHO$ECHO$ECHO
+    PATH=/empty FPATH=/empty; export PATH FPATH
+    test "X`printf %s $ECHO`" = "X$ECHO" \
+      || test "X`print -r -- $ECHO`" = "X$ECHO" )])])
+
+_LT_DECL([], [SHELL], [1], [Shell to use when invoking shell scripts])
+_LT_DECL([], [ECHO], [1], [An echo program that protects backslashes])
+])# _LT_PROG_ECHO_BACKSLASH
+
+
+# _LT_WITH_SYSROOT
+# ----------------
+AC_DEFUN([_LT_WITH_SYSROOT],
+[AC_MSG_CHECKING([for sysroot])
+AC_ARG_WITH([sysroot],
+[  --with-sysroot[=DIR] Search for dependent libraries within DIR
+                        (or the compiler's sysroot if not specified).],
+[], [with_sysroot=no])
+
+dnl lt_sysroot will always be passed unquoted.  We quote it here
+dnl in case the user passed a directory name.
+lt_sysroot=
+case ${with_sysroot} in #(
+ yes)
+   if test "$GCC" = yes; then
+     lt_sysroot=`$CC --print-sysroot 2>/dev/null`
+   fi
+   ;; #(
+ /*)
+   lt_sysroot=`echo "$with_sysroot" | sed -e "$sed_quote_subst"`
+   ;; #(
+ no|'')
+   ;; #(
+ *)
+   AC_MSG_RESULT([${with_sysroot}])
+   AC_MSG_ERROR([The sysroot must be an absolute path.])
+   ;;
+esac
+
+ AC_MSG_RESULT([${lt_sysroot:-no}])
+_LT_DECL([], [lt_sysroot], [0], [The root where to search for ]dnl
+[dependent libraries, and in which our libraries should be installed.])])
+
+# _LT_ENABLE_LOCK
+# ---------------
+m4_defun([_LT_ENABLE_LOCK],
+[AC_ARG_ENABLE([libtool-lock],
+  [AS_HELP_STRING([--disable-libtool-lock],
+    [avoid locking (might break parallel builds)])])
+test "x$enable_libtool_lock" != xno && enable_libtool_lock=yes
+
+# Some flags need to be propagated to the compiler or linker for good
+# libtool support.
+case $host in
+ia64-*-hpux*)
+  # Find out which ABI we are using.
+  echo 'int i;' > conftest.$ac_ext
+  if AC_TRY_EVAL(ac_compile); then
+    case `/usr/bin/file conftest.$ac_objext` in
+      *ELF-32*)
+	HPUX_IA64_MODE="32"
+	;;
+      *ELF-64*)
+	HPUX_IA64_MODE="64"
+	;;
+    esac
+  fi
+  rm -rf conftest*
+  ;;
+*-*-irix6*)
+  # Find out which ABI we are using.
+  echo '[#]line '$LINENO' "configure"' > conftest.$ac_ext
+  if AC_TRY_EVAL(ac_compile); then
+    if test "$lt_cv_prog_gnu_ld" = yes; then
+      case `/usr/bin/file conftest.$ac_objext` in
+	*32-bit*)
+	  LD="${LD-ld} -melf32bsmip"
+	  ;;
+	*N32*)
+	  LD="${LD-ld} -melf32bmipn32"
+	  ;;
+	*64-bit*)
+	  LD="${LD-ld} -melf64bmip"
+	;;
+      esac
+    else
+      case `/usr/bin/file conftest.$ac_objext` in
+	*32-bit*)
+	  LD="${LD-ld} -32"
+	  ;;
+	*N32*)
+	  LD="${LD-ld} -n32"
+	  ;;
+	*64-bit*)
+	  LD="${LD-ld} -64"
+	  ;;
+      esac
+    fi
+  fi
+  rm -rf conftest*
+  ;;
+
+x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
+s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
+  # Find out which ABI we are using.
+  echo 'int i;' > conftest.$ac_ext
+  if AC_TRY_EVAL(ac_compile); then
+    case `/usr/bin/file conftest.o` in
+      *32-bit*)
+	case $host in
+	  x86_64-*kfreebsd*-gnu)
+	    LD="${LD-ld} -m elf_i386_fbsd"
+	    ;;
+	  x86_64-*linux*)
+	    LD="${LD-ld} -m elf_i386"
+	    ;;
+	  ppc64-*linux*|powerpc64-*linux*)
+	    LD="${LD-ld} -m elf32ppclinux"
+	    ;;
+	  s390x-*linux*)
+	    LD="${LD-ld} -m elf_s390"
+	    ;;
+	  sparc64-*linux*)
+	    LD="${LD-ld} -m elf32_sparc"
+	    ;;
+	esac
+	;;
+      *64-bit*)
+	case $host in
+	  x86_64-*kfreebsd*-gnu)
+	    LD="${LD-ld} -m elf_x86_64_fbsd"
+	    ;;
+	  x86_64-*linux*)
+	    LD="${LD-ld} -m elf_x86_64"
+	    ;;
+	  ppc*-*linux*|powerpc*-*linux*)
+	    LD="${LD-ld} -m elf64ppc"
+	    ;;
+	  s390*-*linux*|s390*-*tpf*)
+	    LD="${LD-ld} -m elf64_s390"
+	    ;;
+	  sparc*-*linux*)
+	    LD="${LD-ld} -m elf64_sparc"
+	    ;;
+	esac
+	;;
+    esac
+  fi
+  rm -rf conftest*
+  ;;
+
+*-*-sco3.2v5*)
+  # On SCO OpenServer 5, we need -belf to get full-featured binaries.
+  SAVE_CFLAGS="$CFLAGS"
+  CFLAGS="$CFLAGS -belf"
+  AC_CACHE_CHECK([whether the C compiler needs -belf], lt_cv_cc_needs_belf,
+    [AC_LANG_PUSH(C)
+     AC_LINK_IFELSE([AC_LANG_PROGRAM([[]],[[]])],[lt_cv_cc_needs_belf=yes],[lt_cv_cc_needs_belf=no])
+     AC_LANG_POP])
+  if test x"$lt_cv_cc_needs_belf" != x"yes"; then
+    # this is probably gcc 2.8.0, egcs 1.0 or newer; no need for -belf
+    CFLAGS="$SAVE_CFLAGS"
+  fi
+  ;;
+*-*solaris*)
+  # Find out which ABI we are using.
+  echo 'int i;' > conftest.$ac_ext
+  if AC_TRY_EVAL(ac_compile); then
+    case `/usr/bin/file conftest.o` in
+    *64-bit*)
+      case $lt_cv_prog_gnu_ld in
+      yes*)
+        case $host in
+        i?86-*-solaris*)
+          LD="${LD-ld} -m elf_x86_64"
+          ;;
+        sparc*-*-solaris*)
+          LD="${LD-ld} -m elf64_sparc"
+          ;;
+        esac
+        # GNU ld 2.21 introduced _sol2 emulations.  Use them if available.
+        if ${LD-ld} -V | grep _sol2 >/dev/null 2>&1; then
+          LD="${LD-ld}_sol2"
+        fi
+        ;;
+      *)
+	if ${LD-ld} -64 -r -o conftest2.o conftest.o >/dev/null 2>&1; then
+	  LD="${LD-ld} -64"
+	fi
+	;;
+      esac
+      ;;
+    esac
+  fi
+  rm -rf conftest*
+  ;;
+esac
+
+need_locks="$enable_libtool_lock"
+])# _LT_ENABLE_LOCK
+
+
+# _LT_PROG_AR
+# -----------
+m4_defun([_LT_PROG_AR],
+[AC_CHECK_TOOLS(AR, [ar], false)
+: ${AR=ar}
+: ${AR_FLAGS=cru}
+_LT_DECL([], [AR], [1], [The archiver])
+_LT_DECL([], [AR_FLAGS], [1], [Flags to create an archive])
+
+AC_CACHE_CHECK([for archiver @FILE support], [lt_cv_ar_at_file],
+  [lt_cv_ar_at_file=no
+   AC_COMPILE_IFELSE([AC_LANG_PROGRAM],
+     [echo conftest.$ac_objext > conftest.lst
+      lt_ar_try='$AR $AR_FLAGS libconftest.a @conftest.lst >&AS_MESSAGE_LOG_FD'
+      AC_TRY_EVAL([lt_ar_try])
+      if test "$ac_status" -eq 0; then
+	# Ensure the archiver fails upon bogus file names.
+	rm -f conftest.$ac_objext libconftest.a
+	AC_TRY_EVAL([lt_ar_try])
+	if test "$ac_status" -ne 0; then
+          lt_cv_ar_at_file=@
+        fi
+      fi
+      rm -f conftest.* libconftest.a
+     ])
+  ])
+
+if test "x$lt_cv_ar_at_file" = xno; then
+  archiver_list_spec=
+else
+  archiver_list_spec=$lt_cv_ar_at_file
+fi
+_LT_DECL([], [archiver_list_spec], [1],
+  [How to feed a file listing to the archiver])
+])# _LT_PROG_AR
+
+
+# _LT_CMD_OLD_ARCHIVE
+# -------------------
+m4_defun([_LT_CMD_OLD_ARCHIVE],
+[_LT_PROG_AR
+
+AC_CHECK_TOOL(STRIP, strip, :)
+test -z "$STRIP" && STRIP=:
+_LT_DECL([], [STRIP], [1], [A symbol stripping program])
+
+AC_CHECK_TOOL(RANLIB, ranlib, :)
+test -z "$RANLIB" && RANLIB=:
+_LT_DECL([], [RANLIB], [1],
+    [Commands used to install an old-style archive])
+
+# Determine commands to create old-style static archives.
+old_archive_cmds='$AR $AR_FLAGS $oldlib$oldobjs'
+old_postinstall_cmds='chmod 644 $oldlib'
+old_postuninstall_cmds=
+
+if test -n "$RANLIB"; then
+  case $host_os in
+  openbsd*)
+    old_postinstall_cmds="$old_postinstall_cmds~\$RANLIB -t \$tool_oldlib"
+    ;;
+  *)
+    old_postinstall_cmds="$old_postinstall_cmds~\$RANLIB \$tool_oldlib"
+    ;;
+  esac
+  old_archive_cmds="$old_archive_cmds~\$RANLIB \$tool_oldlib"
+fi
+
+case $host_os in
+  darwin*)
+    lock_old_archive_extraction=yes ;;
+  *)
+    lock_old_archive_extraction=no ;;
+esac
+_LT_DECL([], [old_postinstall_cmds], [2])
+_LT_DECL([], [old_postuninstall_cmds], [2])
+_LT_TAGDECL([], [old_archive_cmds], [2],
+    [Commands used to build an old-style archive])
+_LT_DECL([], [lock_old_archive_extraction], [0],
+    [Whether to use a lock for old archive extraction])
+])# _LT_CMD_OLD_ARCHIVE
+
+
+# _LT_COMPILER_OPTION(MESSAGE, VARIABLE-NAME, FLAGS,
+#		[OUTPUT-FILE], [ACTION-SUCCESS], [ACTION-FAILURE])
+# ----------------------------------------------------------------
+# Check whether the given compiler option works
+AC_DEFUN([_LT_COMPILER_OPTION],
+[m4_require([_LT_FILEUTILS_DEFAULTS])dnl
+m4_require([_LT_DECL_SED])dnl
+AC_CACHE_CHECK([$1], [$2],
+  [$2=no
+   m4_if([$4], , [ac_outfile=conftest.$ac_objext], [ac_outfile=$4])
+   echo "$lt_simple_compile_test_code" > conftest.$ac_ext
+   lt_compiler_flag="$3"
+   # Insert the option either (1) after the last *FLAGS variable, or
+   # (2) before a word containing "conftest.", or (3) at the end.
+   # Note that $ac_compile itself does not contain backslashes and begins
+   # with a dollar sign (not a hyphen), so the echo should work correctly.
+   # The option is referenced via a variable to avoid confusing sed.
+   lt_compile=`echo "$ac_compile" | $SED \
+   -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
+   -e 's: [[^ ]]*conftest\.: $lt_compiler_flag&:; t' \
+   -e 's:$: $lt_compiler_flag:'`
+   (eval echo "\"\$as_me:$LINENO: $lt_compile\"" >&AS_MESSAGE_LOG_FD)
+   (eval "$lt_compile" 2>conftest.err)
+   ac_status=$?
+   cat conftest.err >&AS_MESSAGE_LOG_FD
+   echo "$as_me:$LINENO: \$? = $ac_status" >&AS_MESSAGE_LOG_FD
+   if (exit $ac_status) && test -s "$ac_outfile"; then
+     # The compiler can only warn and ignore the option if not recognized
+     # So say no if there are warnings other than the usual output.
+     $ECHO "$_lt_compiler_boilerplate" | $SED '/^$/d' >conftest.exp
+     $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2
+     if test ! -s conftest.er2 || diff conftest.exp conftest.er2 >/dev/null; then
+       $2=yes
+     fi
+   fi
+   $RM conftest*
+])
+
+if test x"[$]$2" = xyes; then
+    m4_if([$5], , :, [$5])
+else
+    m4_if([$6], , :, [$6])
+fi
+])# _LT_COMPILER_OPTION
+
+# Old name:
+AU_ALIAS([AC_LIBTOOL_COMPILER_OPTION], [_LT_COMPILER_OPTION])
+dnl aclocal-1.4 backwards compatibility:
+dnl AC_DEFUN([AC_LIBTOOL_COMPILER_OPTION], [])
+
+
+# _LT_LINKER_OPTION(MESSAGE, VARIABLE-NAME, FLAGS,
+#                  [ACTION-SUCCESS], [ACTION-FAILURE])
+# ----------------------------------------------------
+# Check whether the given linker option works
+AC_DEFUN([_LT_LINKER_OPTION],
+[m4_require([_LT_FILEUTILS_DEFAULTS])dnl
+m4_require([_LT_DECL_SED])dnl
+AC_CACHE_CHECK([$1], [$2],
+  [$2=no
+   save_LDFLAGS="$LDFLAGS"
+   LDFLAGS="$LDFLAGS $3"
+   echo "$lt_simple_link_test_code" > conftest.$ac_ext
+   if (eval $ac_link 2>conftest.err) && test -s conftest$ac_exeext; then
+     # The linker can only warn and ignore the option if not recognized
+     # So say no if there are warnings
+     if test -s conftest.err; then
+       # Append any errors to the config.log.
+       cat conftest.err 1>&AS_MESSAGE_LOG_FD
+       $ECHO "$_lt_linker_boilerplate" | $SED '/^$/d' > conftest.exp
+       $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2
+       if diff conftest.exp conftest.er2 >/dev/null; then
+         $2=yes
+       fi
+     else
+       $2=yes
+     fi
+   fi
+   $RM -r conftest*
+   LDFLAGS="$save_LDFLAGS"
+])
+
+if test x"[$]$2" = xyes; then
+    m4_if([$4], , :, [$4])
+else
+    m4_if([$5], , :, [$5])
+fi
+])# _LT_LINKER_OPTION
+
+# Old name:
+AU_ALIAS([AC_LIBTOOL_LINKER_OPTION], [_LT_LINKER_OPTION])
+dnl aclocal-1.4 backwards compatibility:
+dnl AC_DEFUN([AC_LIBTOOL_LINKER_OPTION], [])
+
+
+# LT_CMD_MAX_LEN
+#---------------
+AC_DEFUN([LT_CMD_MAX_LEN],
+[AC_REQUIRE([AC_CANONICAL_HOST])dnl
+# find the maximum length of command line arguments
+AC_MSG_CHECKING([the maximum length of command line arguments])
+AC_CACHE_VAL([lt_cv_sys_max_cmd_len], [dnl
+  i=0
+  teststring="ABCD"
+
+  case $build_os in
+  msdosdjgpp*)
+    # On DJGPP, this test can blow up pretty badly due to problems in libc
+    # (any single argument exceeding 2000 bytes causes a buffer overrun
+    # during glob expansion).  Even if it were fixed, the result of this
+    # check would be larger than it should be.
+    lt_cv_sys_max_cmd_len=12288;    # 12K is about right
+    ;;
+
+  gnu*)
+    # Under GNU Hurd, this test is not required because there is
+    # no limit to the length of command line arguments.
+    # Libtool will interpret -1 as no limit whatsoever
+    lt_cv_sys_max_cmd_len=-1;
+    ;;
+
+  cygwin* | mingw* | cegcc*)
+    # On Win9x/ME, this test blows up -- it succeeds, but takes
+    # about 5 minutes as the teststring grows exponentially.
+    # Worse, since 9x/ME are not pre-emptively multitasking,
+    # you end up with a "frozen" computer, even though with patience
+    # the test eventually succeeds (with a max line length of 256k).
+    # Instead, let's just punt: use the minimum linelength reported by
+    # all of the supported platforms: 8192 (on NT/2K/XP).
+    lt_cv_sys_max_cmd_len=8192;
+    ;;
+
+  mint*)
+    # On MiNT this can take a long time and run out of memory.
+    lt_cv_sys_max_cmd_len=8192;
+    ;;
+
+  amigaos*)
+    # On AmigaOS with pdksh, this test takes hours, literally.
+    # So we just punt and use a minimum line length of 8192.
+    lt_cv_sys_max_cmd_len=8192;
+    ;;
+
+  netbsd* | freebsd* | openbsd* | darwin* | dragonfly*)
+    # This has been around since 386BSD, at least.  Likely further.
+    if test -x /sbin/sysctl; then
+      lt_cv_sys_max_cmd_len=`/sbin/sysctl -n kern.argmax`
+    elif test -x /usr/sbin/sysctl; then
+      lt_cv_sys_max_cmd_len=`/usr/sbin/sysctl -n kern.argmax`
+    else
+      lt_cv_sys_max_cmd_len=65536	# usable default for all BSDs
+    fi
+    # And add a safety zone
+    lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 4`
+    lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \* 3`
+    ;;
+
+  interix*)
+    # We know the value 262144 and hardcode it with a safety zone (like BSD)
+    lt_cv_sys_max_cmd_len=196608
+    ;;
+
+  os2*)
+    # The test takes a long time on OS/2.
+    lt_cv_sys_max_cmd_len=8192
+    ;;
+
+  osf*)
+    # Dr. Hans Ekkehard Plesser reports seeing a kernel panic running configure
+    # due to this test when exec_disable_arg_limit is 1 on Tru64. It is not
+    # nice to cause kernel panics so lets avoid the loop below.
+    # First set a reasonable default.
+    lt_cv_sys_max_cmd_len=16384
+    #
+    if test -x /sbin/sysconfig; then
+      case `/sbin/sysconfig -q proc exec_disable_arg_limit` in
+        *1*) lt_cv_sys_max_cmd_len=-1 ;;
+      esac
+    fi
+    ;;
+  sco3.2v5*)
+    lt_cv_sys_max_cmd_len=102400
+    ;;
+  sysv5* | sco5v6* | sysv4.2uw2*)
+    kargmax=`grep ARG_MAX /etc/conf/cf.d/stune 2>/dev/null`
+    if test -n "$kargmax"; then
+      lt_cv_sys_max_cmd_len=`echo $kargmax | sed 's/.*[[	 ]]//'`
+    else
+      lt_cv_sys_max_cmd_len=32768
+    fi
+    ;;
+  *)
+    lt_cv_sys_max_cmd_len=`(getconf ARG_MAX) 2> /dev/null`
+    if test -n "$lt_cv_sys_max_cmd_len"; then
+      lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 4`
+      lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \* 3`
+    else
+      # Make teststring a little bigger before we do anything with it.
+      # a 1K string should be a reasonable start.
+      for i in 1 2 3 4 5 6 7 8 ; do
+        teststring=$teststring$teststring
+      done
+      SHELL=${SHELL-${CONFIG_SHELL-/bin/sh}}
+      # If test is not a shell built-in, we'll probably end up computing a
+      # maximum length that is only half of the actual maximum length, but
+      # we can't tell.
+      while { test "X"`env echo "$teststring$teststring" 2>/dev/null` \
+	         = "X$teststring$teststring"; } >/dev/null 2>&1 &&
+	      test $i != 17 # 1/2 MB should be enough
+      do
+        i=`expr $i + 1`
+        teststring=$teststring$teststring
+      done
+      # Only check the string length outside the loop.
+      lt_cv_sys_max_cmd_len=`expr "X$teststring" : ".*" 2>&1`
+      teststring=
+      # Add a significant safety factor because C++ compilers can tack on
+      # massive amounts of additional arguments before passing them to the
+      # linker.  It appears as though 1/2 is a usable value.
+      lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 2`
+    fi
+    ;;
+  esac
+])
+if test -n $lt_cv_sys_max_cmd_len ; then
+  AC_MSG_RESULT($lt_cv_sys_max_cmd_len)
+else
+  AC_MSG_RESULT(none)
+fi
+max_cmd_len=$lt_cv_sys_max_cmd_len
+_LT_DECL([], [max_cmd_len], [0],
+    [What is the maximum length of a command?])
+])# LT_CMD_MAX_LEN
+
+# Old name:
+AU_ALIAS([AC_LIBTOOL_SYS_MAX_CMD_LEN], [LT_CMD_MAX_LEN])
+dnl aclocal-1.4 backwards compatibility:
+dnl AC_DEFUN([AC_LIBTOOL_SYS_MAX_CMD_LEN], [])
+
+
+# _LT_HEADER_DLFCN
+# ----------------
+m4_defun([_LT_HEADER_DLFCN],
+[AC_CHECK_HEADERS([dlfcn.h], [], [], [AC_INCLUDES_DEFAULT])dnl
+])# _LT_HEADER_DLFCN
+
+
+# _LT_TRY_DLOPEN_SELF (ACTION-IF-TRUE, ACTION-IF-TRUE-W-USCORE,
+#                      ACTION-IF-FALSE, ACTION-IF-CROSS-COMPILING)
+# ----------------------------------------------------------------
+m4_defun([_LT_TRY_DLOPEN_SELF],
+[m4_require([_LT_HEADER_DLFCN])dnl
+if test "$cross_compiling" = yes; then :
+  [$4]
+else
+  lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
+  lt_status=$lt_dlunknown
+  cat > conftest.$ac_ext <<_LT_EOF
+[#line $LINENO "configure"
+#include "confdefs.h"
+
+#if HAVE_DLFCN_H
+#include 
+#endif
+
+#include 
+
+#ifdef RTLD_GLOBAL
+#  define LT_DLGLOBAL		RTLD_GLOBAL
+#else
+#  ifdef DL_GLOBAL
+#    define LT_DLGLOBAL		DL_GLOBAL
+#  else
+#    define LT_DLGLOBAL		0
+#  endif
+#endif
+
+/* We may have to define LT_DLLAZY_OR_NOW in the command line if we
+   find out it does not work in some platform. */
+#ifndef LT_DLLAZY_OR_NOW
+#  ifdef RTLD_LAZY
+#    define LT_DLLAZY_OR_NOW		RTLD_LAZY
+#  else
+#    ifdef DL_LAZY
+#      define LT_DLLAZY_OR_NOW		DL_LAZY
+#    else
+#      ifdef RTLD_NOW
+#        define LT_DLLAZY_OR_NOW	RTLD_NOW
+#      else
+#        ifdef DL_NOW
+#          define LT_DLLAZY_OR_NOW	DL_NOW
+#        else
+#          define LT_DLLAZY_OR_NOW	0
+#        endif
+#      endif
+#    endif
+#  endif
+#endif
+
+/* When -fvisbility=hidden is used, assume the code has been annotated
+   correspondingly for the symbols needed.  */
+#if defined(__GNUC__) && (((__GNUC__ == 3) && (__GNUC_MINOR__ >= 3)) || (__GNUC__ > 3))
+int fnord () __attribute__((visibility("default")));
+#endif
+
+int fnord () { return 42; }
+int main ()
+{
+  void *self = dlopen (0, LT_DLGLOBAL|LT_DLLAZY_OR_NOW);
+  int status = $lt_dlunknown;
+
+  if (self)
+    {
+      if (dlsym (self,"fnord"))       status = $lt_dlno_uscore;
+      else
+        {
+	  if (dlsym( self,"_fnord"))  status = $lt_dlneed_uscore;
+          else puts (dlerror ());
+	}
+      /* dlclose (self); */
+    }
+  else
+    puts (dlerror ());
+
+  return status;
+}]
+_LT_EOF
+  if AC_TRY_EVAL(ac_link) && test -s conftest${ac_exeext} 2>/dev/null; then
+    (./conftest; exit; ) >&AS_MESSAGE_LOG_FD 2>/dev/null
+    lt_status=$?
+    case x$lt_status in
+      x$lt_dlno_uscore) $1 ;;
+      x$lt_dlneed_uscore) $2 ;;
+      x$lt_dlunknown|x*) $3 ;;
+    esac
+  else :
+    # compilation failed
+    $3
+  fi
+fi
+rm -fr conftest*
+])# _LT_TRY_DLOPEN_SELF
+
+
+# LT_SYS_DLOPEN_SELF
+# ------------------
+AC_DEFUN([LT_SYS_DLOPEN_SELF],
+[m4_require([_LT_HEADER_DLFCN])dnl
+if test "x$enable_dlopen" != xyes; then
+  enable_dlopen=unknown
+  enable_dlopen_self=unknown
+  enable_dlopen_self_static=unknown
+else
+  lt_cv_dlopen=no
+  lt_cv_dlopen_libs=
+
+  case $host_os in
+  beos*)
+    lt_cv_dlopen="load_add_on"
+    lt_cv_dlopen_libs=
+    lt_cv_dlopen_self=yes
+    ;;
+
+  mingw* | pw32* | cegcc*)
+    lt_cv_dlopen="LoadLibrary"
+    lt_cv_dlopen_libs=
+    ;;
+
+  cygwin*)
+    lt_cv_dlopen="dlopen"
+    lt_cv_dlopen_libs=
+    ;;
+
+  darwin*)
+  # if libdl is installed we need to link against it
+    AC_CHECK_LIB([dl], [dlopen],
+		[lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-ldl"],[
+    lt_cv_dlopen="dyld"
+    lt_cv_dlopen_libs=
+    lt_cv_dlopen_self=yes
+    ])
+    ;;
+
+  *)
+    AC_CHECK_FUNC([shl_load],
+	  [lt_cv_dlopen="shl_load"],
+      [AC_CHECK_LIB([dld], [shl_load],
+	    [lt_cv_dlopen="shl_load" lt_cv_dlopen_libs="-ldld"],
+	[AC_CHECK_FUNC([dlopen],
+	      [lt_cv_dlopen="dlopen"],
+	  [AC_CHECK_LIB([dl], [dlopen],
+		[lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-ldl"],
+	    [AC_CHECK_LIB([svld], [dlopen],
+		  [lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-lsvld"],
+	      [AC_CHECK_LIB([dld], [dld_link],
+		    [lt_cv_dlopen="dld_link" lt_cv_dlopen_libs="-ldld"])
+	      ])
+	    ])
+	  ])
+	])
+      ])
+    ;;
+  esac
+
+  if test "x$lt_cv_dlopen" != xno; then
+    enable_dlopen=yes
+  else
+    enable_dlopen=no
+  fi
+
+  case $lt_cv_dlopen in
+  dlopen)
+    save_CPPFLAGS="$CPPFLAGS"
+    test "x$ac_cv_header_dlfcn_h" = xyes && CPPFLAGS="$CPPFLAGS -DHAVE_DLFCN_H"
+
+    save_LDFLAGS="$LDFLAGS"
+    wl=$lt_prog_compiler_wl eval LDFLAGS=\"\$LDFLAGS $export_dynamic_flag_spec\"
+
+    save_LIBS="$LIBS"
+    LIBS="$lt_cv_dlopen_libs $LIBS"
+
+    AC_CACHE_CHECK([whether a program can dlopen itself],
+	  lt_cv_dlopen_self, [dnl
+	  _LT_TRY_DLOPEN_SELF(
+	    lt_cv_dlopen_self=yes, lt_cv_dlopen_self=yes,
+	    lt_cv_dlopen_self=no, lt_cv_dlopen_self=cross)
+    ])
+
+    if test "x$lt_cv_dlopen_self" = xyes; then
+      wl=$lt_prog_compiler_wl eval LDFLAGS=\"\$LDFLAGS $lt_prog_compiler_static\"
+      AC_CACHE_CHECK([whether a statically linked program can dlopen itself],
+	  lt_cv_dlopen_self_static, [dnl
+	  _LT_TRY_DLOPEN_SELF(
+	    lt_cv_dlopen_self_static=yes, lt_cv_dlopen_self_static=yes,
+	    lt_cv_dlopen_self_static=no,  lt_cv_dlopen_self_static=cross)
+      ])
+    fi
+
+    CPPFLAGS="$save_CPPFLAGS"
+    LDFLAGS="$save_LDFLAGS"
+    LIBS="$save_LIBS"
+    ;;
+  esac
+
+  case $lt_cv_dlopen_self in
+  yes|no) enable_dlopen_self=$lt_cv_dlopen_self ;;
+  *) enable_dlopen_self=unknown ;;
+  esac
+
+  case $lt_cv_dlopen_self_static in
+  yes|no) enable_dlopen_self_static=$lt_cv_dlopen_self_static ;;
+  *) enable_dlopen_self_static=unknown ;;
+  esac
+fi
+_LT_DECL([dlopen_support], [enable_dlopen], [0],
+	 [Whether dlopen is supported])
+_LT_DECL([dlopen_self], [enable_dlopen_self], [0],
+	 [Whether dlopen of programs is supported])
+_LT_DECL([dlopen_self_static], [enable_dlopen_self_static], [0],
+	 [Whether dlopen of statically linked programs is supported])
+])# LT_SYS_DLOPEN_SELF
+
+# Old name:
+AU_ALIAS([AC_LIBTOOL_DLOPEN_SELF], [LT_SYS_DLOPEN_SELF])
+dnl aclocal-1.4 backwards compatibility:
+dnl AC_DEFUN([AC_LIBTOOL_DLOPEN_SELF], [])
+
+
+# _LT_COMPILER_C_O([TAGNAME])
+# ---------------------------
+# Check to see if options -c and -o are simultaneously supported by compiler.
+# This macro does not hard code the compiler like AC_PROG_CC_C_O.
+m4_defun([_LT_COMPILER_C_O],
+[m4_require([_LT_DECL_SED])dnl
+m4_require([_LT_FILEUTILS_DEFAULTS])dnl
+m4_require([_LT_TAG_COMPILER])dnl
+AC_CACHE_CHECK([if $compiler supports -c -o file.$ac_objext],
+  [_LT_TAGVAR(lt_cv_prog_compiler_c_o, $1)],
+  [_LT_TAGVAR(lt_cv_prog_compiler_c_o, $1)=no
+   $RM -r conftest 2>/dev/null
+   mkdir conftest
+   cd conftest
+   mkdir out
+   echo "$lt_simple_compile_test_code" > conftest.$ac_ext
+
+   lt_compiler_flag="-o out/conftest2.$ac_objext"
+   # Insert the option either (1) after the last *FLAGS variable, or
+   # (2) before a word containing "conftest.", or (3) at the end.
+   # Note that $ac_compile itself does not contain backslashes and begins
+   # with a dollar sign (not a hyphen), so the echo should work correctly.
+   lt_compile=`echo "$ac_compile" | $SED \
+   -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
+   -e 's: [[^ ]]*conftest\.: $lt_compiler_flag&:; t' \
+   -e 's:$: $lt_compiler_flag:'`
+   (eval echo "\"\$as_me:$LINENO: $lt_compile\"" >&AS_MESSAGE_LOG_FD)
+   (eval "$lt_compile" 2>out/conftest.err)
+   ac_status=$?
+   cat out/conftest.err >&AS_MESSAGE_LOG_FD
+   echo "$as_me:$LINENO: \$? = $ac_status" >&AS_MESSAGE_LOG_FD
+   if (exit $ac_status) && test -s out/conftest2.$ac_objext
+   then
+     # The compiler can only warn and ignore the option if not recognized
+     # So say no if there are warnings
+     $ECHO "$_lt_compiler_boilerplate" | $SED '/^$/d' > out/conftest.exp
+     $SED '/^$/d; /^ *+/d' out/conftest.err >out/conftest.er2
+     if test ! -s out/conftest.er2 || diff out/conftest.exp out/conftest.er2 >/dev/null; then
+       _LT_TAGVAR(lt_cv_prog_compiler_c_o, $1)=yes
+     fi
+   fi
+   chmod u+w . 2>&AS_MESSAGE_LOG_FD
+   $RM conftest*
+   # SGI C++ compiler will create directory out/ii_files/ for
+   # template instantiation
+   test -d out/ii_files && $RM out/ii_files/* && rmdir out/ii_files
+   $RM out/* && rmdir out
+   cd ..
+   $RM -r conftest
+   $RM conftest*
+])
+_LT_TAGDECL([compiler_c_o], [lt_cv_prog_compiler_c_o], [1],
+	[Does compiler simultaneously support -c and -o options?])
+])# _LT_COMPILER_C_O
+
+
+# _LT_COMPILER_FILE_LOCKS([TAGNAME])
+# ----------------------------------
+# Check to see if we can do hard links to lock some files if needed
+m4_defun([_LT_COMPILER_FILE_LOCKS],
+[m4_require([_LT_ENABLE_LOCK])dnl
+m4_require([_LT_FILEUTILS_DEFAULTS])dnl
+_LT_COMPILER_C_O([$1])
+
+hard_links="nottested"
+if test "$_LT_TAGVAR(lt_cv_prog_compiler_c_o, $1)" = no && test "$need_locks" != no; then
+  # do not overwrite the value of need_locks provided by the user
+  AC_MSG_CHECKING([if we can lock with hard links])
+  hard_links=yes
+  $RM conftest*
+  ln conftest.a conftest.b 2>/dev/null && hard_links=no
+  touch conftest.a
+  ln conftest.a conftest.b 2>&5 || hard_links=no
+  ln conftest.a conftest.b 2>/dev/null && hard_links=no
+  AC_MSG_RESULT([$hard_links])
+  if test "$hard_links" = no; then
+    AC_MSG_WARN([`$CC' does not support `-c -o', so `make -j' may be unsafe])
+    need_locks=warn
+  fi
+else
+  need_locks=no
+fi
+_LT_DECL([], [need_locks], [1], [Must we lock files when doing compilation?])
+])# _LT_COMPILER_FILE_LOCKS
+
+
+# _LT_CHECK_OBJDIR
+# ----------------
+m4_defun([_LT_CHECK_OBJDIR],
+[AC_CACHE_CHECK([for objdir], [lt_cv_objdir],
+[rm -f .libs 2>/dev/null
+mkdir .libs 2>/dev/null
+if test -d .libs; then
+  lt_cv_objdir=.libs
+else
+  # MS-DOS does not allow filenames that begin with a dot.
+  lt_cv_objdir=_libs
+fi
+rmdir .libs 2>/dev/null])
+objdir=$lt_cv_objdir
+_LT_DECL([], [objdir], [0],
+         [The name of the directory that contains temporary libtool files])dnl
+m4_pattern_allow([LT_OBJDIR])dnl
+AC_DEFINE_UNQUOTED(LT_OBJDIR, "$lt_cv_objdir/",
+  [Define to the sub-directory in which libtool stores uninstalled libraries.])
+])# _LT_CHECK_OBJDIR
+
+
+# _LT_LINKER_HARDCODE_LIBPATH([TAGNAME])
+# --------------------------------------
+# Check hardcoding attributes.
+m4_defun([_LT_LINKER_HARDCODE_LIBPATH],
+[AC_MSG_CHECKING([how to hardcode library paths into programs])
+_LT_TAGVAR(hardcode_action, $1)=
+if test -n "$_LT_TAGVAR(hardcode_libdir_flag_spec, $1)" ||
+   test -n "$_LT_TAGVAR(runpath_var, $1)" ||
+   test "X$_LT_TAGVAR(hardcode_automatic, $1)" = "Xyes" ; then
+
+  # We can hardcode non-existent directories.
+  if test "$_LT_TAGVAR(hardcode_direct, $1)" != no &&
+     # If the only mechanism to avoid hardcoding is shlibpath_var, we
+     # have to relink, otherwise we might link with an installed library
+     # when we should be linking with a yet-to-be-installed one
+     ## test "$_LT_TAGVAR(hardcode_shlibpath_var, $1)" != no &&
+     test "$_LT_TAGVAR(hardcode_minus_L, $1)" != no; then
+    # Linking always hardcodes the temporary library directory.
+    _LT_TAGVAR(hardcode_action, $1)=relink
+  else
+    # We can link without hardcoding, and we can hardcode nonexisting dirs.
+    _LT_TAGVAR(hardcode_action, $1)=immediate
+  fi
+else
+  # We cannot hardcode anything, or else we can only hardcode existing
+  # directories.
+  _LT_TAGVAR(hardcode_action, $1)=unsupported
+fi
+AC_MSG_RESULT([$_LT_TAGVAR(hardcode_action, $1)])
+
+if test "$_LT_TAGVAR(hardcode_action, $1)" = relink ||
+   test "$_LT_TAGVAR(inherit_rpath, $1)" = yes; then
+  # Fast installation is not supported
+  enable_fast_install=no
+elif test "$shlibpath_overrides_runpath" = yes ||
+     test "$enable_shared" = no; then
+  # Fast installation is not necessary
+  enable_fast_install=needless
+fi
+_LT_TAGDECL([], [hardcode_action], [0],
+    [How to hardcode a shared library path into an executable])
+])# _LT_LINKER_HARDCODE_LIBPATH
+
+
+# _LT_CMD_STRIPLIB
+# ----------------
+m4_defun([_LT_CMD_STRIPLIB],
+[m4_require([_LT_DECL_EGREP])
+striplib=
+old_striplib=
+AC_MSG_CHECKING([whether stripping libraries is possible])
+if test -n "$STRIP" && $STRIP -V 2>&1 | $GREP "GNU strip" >/dev/null; then
+  test -z "$old_striplib" && old_striplib="$STRIP --strip-debug"
+  test -z "$striplib" && striplib="$STRIP --strip-unneeded"
+  AC_MSG_RESULT([yes])
+else
+# FIXME - insert some real tests, host_os isn't really good enough
+  case $host_os in
+  darwin*)
+    if test -n "$STRIP" ; then
+      striplib="$STRIP -x"
+      old_striplib="$STRIP -S"
+      AC_MSG_RESULT([yes])
+    else
+      AC_MSG_RESULT([no])
+    fi
+    ;;
+  *)
+    AC_MSG_RESULT([no])
+    ;;
+  esac
+fi
+_LT_DECL([], [old_striplib], [1], [Commands to strip libraries])
+_LT_DECL([], [striplib], [1])
+])# _LT_CMD_STRIPLIB
+
+
+# _LT_SYS_DYNAMIC_LINKER([TAG])
+# -----------------------------
+# PORTME Fill in your ld.so characteristics
+m4_defun([_LT_SYS_DYNAMIC_LINKER],
+[AC_REQUIRE([AC_CANONICAL_HOST])dnl
+m4_require([_LT_DECL_EGREP])dnl
+m4_require([_LT_FILEUTILS_DEFAULTS])dnl
+m4_require([_LT_DECL_OBJDUMP])dnl
+m4_require([_LT_DECL_SED])dnl
+m4_require([_LT_CHECK_SHELL_FEATURES])dnl
+AC_MSG_CHECKING([dynamic linker characteristics])
+m4_if([$1],
+	[], [
+if test "$GCC" = yes; then
+  case $host_os in
+    darwin*) lt_awk_arg="/^libraries:/,/LR/" ;;
+    *) lt_awk_arg="/^libraries:/" ;;
+  esac
+  case $host_os in
+    mingw* | cegcc*) lt_sed_strip_eq="s,=\([[A-Za-z]]:\),\1,g" ;;
+    *) lt_sed_strip_eq="s,=/,/,g" ;;
+  esac
+  lt_search_path_spec=`$CC -print-search-dirs | awk $lt_awk_arg | $SED -e "s/^libraries://" -e $lt_sed_strip_eq`
+  case $lt_search_path_spec in
+  *\;*)
+    # if the path contains ";" then we assume it to be the separator
+    # otherwise default to the standard path separator (i.e. ":") - it is
+    # assumed that no part of a normal pathname contains ";" but that should
+    # okay in the real world where ";" in dirpaths is itself problematic.
+    lt_search_path_spec=`$ECHO "$lt_search_path_spec" | $SED 's/;/ /g'`
+    ;;
+  *)
+    lt_search_path_spec=`$ECHO "$lt_search_path_spec" | $SED "s/$PATH_SEPARATOR/ /g"`
+    ;;
+  esac
+  # Ok, now we have the path, separated by spaces, we can step through it
+  # and add multilib dir if necessary.
+  lt_tmp_lt_search_path_spec=
+  lt_multi_os_dir=`$CC $CPPFLAGS $CFLAGS $LDFLAGS -print-multi-os-directory 2>/dev/null`
+  for lt_sys_path in $lt_search_path_spec; do
+    if test -d "$lt_sys_path/$lt_multi_os_dir"; then
+      lt_tmp_lt_search_path_spec="$lt_tmp_lt_search_path_spec $lt_sys_path/$lt_multi_os_dir"
+    else
+      test -d "$lt_sys_path" && \
+	lt_tmp_lt_search_path_spec="$lt_tmp_lt_search_path_spec $lt_sys_path"
+    fi
+  done
+  lt_search_path_spec=`$ECHO "$lt_tmp_lt_search_path_spec" | awk '
+BEGIN {RS=" "; FS="/|\n";} {
+  lt_foo="";
+  lt_count=0;
+  for (lt_i = NF; lt_i > 0; lt_i--) {
+    if ($lt_i != "" && $lt_i != ".") {
+      if ($lt_i == "..") {
+        lt_count++;
+      } else {
+        if (lt_count == 0) {
+          lt_foo="/" $lt_i lt_foo;
+        } else {
+          lt_count--;
+        }
+      }
+    }
+  }
+  if (lt_foo != "") { lt_freq[[lt_foo]]++; }
+  if (lt_freq[[lt_foo]] == 1) { print lt_foo; }
+}'`
+  # AWK program above erroneously prepends '/' to C:/dos/paths
+  # for these hosts.
+  case $host_os in
+    mingw* | cegcc*) lt_search_path_spec=`$ECHO "$lt_search_path_spec" |\
+      $SED 's,/\([[A-Za-z]]:\),\1,g'` ;;
+  esac
+  sys_lib_search_path_spec=`$ECHO "$lt_search_path_spec" | $lt_NL2SP`
+else
+  sys_lib_search_path_spec="/lib /usr/lib /usr/local/lib"
+fi])
+library_names_spec=
+libname_spec='lib$name'
+soname_spec=
+shrext_cmds=".so"
+postinstall_cmds=
+postuninstall_cmds=
+finish_cmds=
+finish_eval=
+shlibpath_var=
+shlibpath_overrides_runpath=unknown
+version_type=none
+dynamic_linker="$host_os ld.so"
+sys_lib_dlsearch_path_spec="/lib /usr/lib"
+need_lib_prefix=unknown
+hardcode_into_libs=no
+
+# when you set need_version to no, make sure it does not cause -set_version
+# flags to be left without arguments
+need_version=unknown
+
+case $host_os in
+aix3*)
+  version_type=linux # correct to gnu/linux during the next big refactor
+  library_names_spec='${libname}${release}${shared_ext}$versuffix $libname.a'
+  shlibpath_var=LIBPATH
+
+  # AIX 3 has no versioning support, so we append a major version to the name.
+  soname_spec='${libname}${release}${shared_ext}$major'
+  ;;
+
+aix[[4-9]]*)
+  version_type=linux # correct to gnu/linux during the next big refactor
+  need_lib_prefix=no
+  need_version=no
+  hardcode_into_libs=yes
+  if test "$host_cpu" = ia64; then
+    # AIX 5 supports IA64
+    library_names_spec='${libname}${release}${shared_ext}$major ${libname}${release}${shared_ext}$versuffix $libname${shared_ext}'
+    shlibpath_var=LD_LIBRARY_PATH
+  else
+    # With GCC up to 2.95.x, collect2 would create an import file
+    # for dependence libraries.  The import file would start with
+    # the line `#! .'.  This would cause the generated library to
+    # depend on `.', always an invalid library.  This was fixed in
+    # development snapshots of GCC prior to 3.0.
+    case $host_os in
+      aix4 | aix4.[[01]] | aix4.[[01]].*)
+      if { echo '#if __GNUC__ > 2 || (__GNUC__ == 2 && __GNUC_MINOR__ >= 97)'
+	   echo ' yes '
+	   echo '#endif'; } | ${CC} -E - | $GREP yes > /dev/null; then
+	:
+      else
+	can_build_shared=no
+      fi
+      ;;
+    esac
+    # AIX (on Power*) has no versioning support, so currently we can not hardcode correct
+    # soname into executable. Probably we can add versioning support to
+    # collect2, so additional links can be useful in future.
+    if test "$aix_use_runtimelinking" = yes; then
+      # If using run time linking (on AIX 4.2 or later) use lib.so
+      # instead of lib.a to let people know that these are not
+      # typical AIX shared libraries.
+      library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+    else
+      # We preserve .a as extension for shared libraries through AIX4.2
+      # and later when we are not doing run time linking.
+      library_names_spec='${libname}${release}.a $libname.a'
+      soname_spec='${libname}${release}${shared_ext}$major'
+    fi
+    shlibpath_var=LIBPATH
+  fi
+  ;;
+
+amigaos*)
+  case $host_cpu in
+  powerpc)
+    # Since July 2007 AmigaOS4 officially supports .so libraries.
+    # When compiling the executable, add -use-dynld -Lsobjs: to the compileline.
+    library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+    ;;
+  m68k)
+    library_names_spec='$libname.ixlibrary $libname.a'
+    # Create ${libname}_ixlibrary.a entries in /sys/libs.
+    finish_eval='for lib in `ls $libdir/*.ixlibrary 2>/dev/null`; do libname=`func_echo_all "$lib" | $SED '\''s%^.*/\([[^/]]*\)\.ixlibrary$%\1%'\''`; test $RM /sys/libs/${libname}_ixlibrary.a; $show "cd /sys/libs && $LN_S $lib ${libname}_ixlibrary.a"; cd /sys/libs && $LN_S $lib ${libname}_ixlibrary.a || exit 1; done'
+    ;;
+  esac
+  ;;
+
+beos*)
+  library_names_spec='${libname}${shared_ext}'
+  dynamic_linker="$host_os ld.so"
+  shlibpath_var=LIBRARY_PATH
+  ;;
+
+bsdi[[45]]*)
+  version_type=linux # correct to gnu/linux during the next big refactor
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  finish_cmds='PATH="\$PATH:/sbin" ldconfig $libdir'
+  shlibpath_var=LD_LIBRARY_PATH
+  sys_lib_search_path_spec="/shlib /usr/lib /usr/X11/lib /usr/contrib/lib /lib /usr/local/lib"
+  sys_lib_dlsearch_path_spec="/shlib /usr/lib /usr/local/lib"
+  # the default ld.so.conf also contains /usr/contrib/lib and
+  # /usr/X11R6/lib (/usr/X11 is a link to /usr/X11R6), but let us allow
+  # libtool to hard-code these into programs
+  ;;
+
+cygwin* | mingw* | pw32* | cegcc*)
+  version_type=windows
+  shrext_cmds=".dll"
+  need_version=no
+  need_lib_prefix=no
+
+  case $GCC,$cc_basename in
+  yes,*)
+    # gcc
+    library_names_spec='$libname.dll.a'
+    # DLL is installed to $(libdir)/../bin by postinstall_cmds
+    postinstall_cmds='base_file=`basename \${file}`~
+      dlpath=`$SHELL 2>&1 -c '\''. $dir/'\''\${base_file}'\''i; echo \$dlname'\''`~
+      dldir=$destdir/`dirname \$dlpath`~
+      test -d \$dldir || mkdir -p \$dldir~
+      $install_prog $dir/$dlname \$dldir/$dlname~
+      chmod a+x \$dldir/$dlname~
+      if test -n '\''$stripme'\'' && test -n '\''$striplib'\''; then
+        eval '\''$striplib \$dldir/$dlname'\'' || exit \$?;
+      fi'
+    postuninstall_cmds='dldll=`$SHELL 2>&1 -c '\''. $file; echo \$dlname'\''`~
+      dlpath=$dir/\$dldll~
+       $RM \$dlpath'
+    shlibpath_overrides_runpath=yes
+
+    case $host_os in
+    cygwin*)
+      # Cygwin DLLs use 'cyg' prefix rather than 'lib'
+      soname_spec='`echo ${libname} | sed -e 's/^lib/cyg/'``echo ${release} | $SED -e 's/[[.]]/-/g'`${versuffix}${shared_ext}'
+m4_if([$1], [],[
+      sys_lib_search_path_spec="$sys_lib_search_path_spec /usr/lib/w32api"])
+      ;;
+    mingw* | cegcc*)
+      # MinGW DLLs use traditional 'lib' prefix
+      soname_spec='${libname}`echo ${release} | $SED -e 's/[[.]]/-/g'`${versuffix}${shared_ext}'
+      ;;
+    pw32*)
+      # pw32 DLLs use 'pw' prefix rather than 'lib'
+      library_names_spec='`echo ${libname} | sed -e 's/^lib/pw/'``echo ${release} | $SED -e 's/[[.]]/-/g'`${versuffix}${shared_ext}'
+      ;;
+    esac
+    dynamic_linker='Win32 ld.exe'
+    ;;
+
+  *,cl*)
+    # Native MSVC
+    libname_spec='$name'
+    soname_spec='${libname}`echo ${release} | $SED -e 's/[[.]]/-/g'`${versuffix}${shared_ext}'
+    library_names_spec='${libname}.dll.lib'
+
+    case $build_os in
+    mingw*)
+      sys_lib_search_path_spec=
+      lt_save_ifs=$IFS
+      IFS=';'
+      for lt_path in $LIB
+      do
+        IFS=$lt_save_ifs
+        # Let DOS variable expansion print the short 8.3 style file name.
+        lt_path=`cd "$lt_path" 2>/dev/null && cmd //C "for %i in (".") do @echo %~si"`
+        sys_lib_search_path_spec="$sys_lib_search_path_spec $lt_path"
+      done
+      IFS=$lt_save_ifs
+      # Convert to MSYS style.
+      sys_lib_search_path_spec=`$ECHO "$sys_lib_search_path_spec" | sed -e 's|\\\\|/|g' -e 's| \\([[a-zA-Z]]\\):| /\\1|g' -e 's|^ ||'`
+      ;;
+    cygwin*)
+      # Convert to unix form, then to dos form, then back to unix form
+      # but this time dos style (no spaces!) so that the unix form looks
+      # like /cygdrive/c/PROGRA~1:/cygdr...
+      sys_lib_search_path_spec=`cygpath --path --unix "$LIB"`
+      sys_lib_search_path_spec=`cygpath --path --dos "$sys_lib_search_path_spec" 2>/dev/null`
+      sys_lib_search_path_spec=`cygpath --path --unix "$sys_lib_search_path_spec" | $SED -e "s/$PATH_SEPARATOR/ /g"`
+      ;;
+    *)
+      sys_lib_search_path_spec="$LIB"
+      if $ECHO "$sys_lib_search_path_spec" | [$GREP ';[c-zC-Z]:/' >/dev/null]; then
+        # It is most probably a Windows format PATH.
+        sys_lib_search_path_spec=`$ECHO "$sys_lib_search_path_spec" | $SED -e 's/;/ /g'`
+      else
+        sys_lib_search_path_spec=`$ECHO "$sys_lib_search_path_spec" | $SED -e "s/$PATH_SEPARATOR/ /g"`
+      fi
+      # FIXME: find the short name or the path components, as spaces are
+      # common. (e.g. "Program Files" -> "PROGRA~1")
+      ;;
+    esac
+
+    # DLL is installed to $(libdir)/../bin by postinstall_cmds
+    postinstall_cmds='base_file=`basename \${file}`~
+      dlpath=`$SHELL 2>&1 -c '\''. $dir/'\''\${base_file}'\''i; echo \$dlname'\''`~
+      dldir=$destdir/`dirname \$dlpath`~
+      test -d \$dldir || mkdir -p \$dldir~
+      $install_prog $dir/$dlname \$dldir/$dlname'
+    postuninstall_cmds='dldll=`$SHELL 2>&1 -c '\''. $file; echo \$dlname'\''`~
+      dlpath=$dir/\$dldll~
+       $RM \$dlpath'
+    shlibpath_overrides_runpath=yes
+    dynamic_linker='Win32 link.exe'
+    ;;
+
+  *)
+    # Assume MSVC wrapper
+    library_names_spec='${libname}`echo ${release} | $SED -e 's/[[.]]/-/g'`${versuffix}${shared_ext} $libname.lib'
+    dynamic_linker='Win32 ld.exe'
+    ;;
+  esac
+  # FIXME: first we should search . and the directory the executable is in
+  shlibpath_var=PATH
+  ;;
+
+darwin* | rhapsody*)
+  dynamic_linker="$host_os dyld"
+  version_type=darwin
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${major}$shared_ext ${libname}$shared_ext'
+  soname_spec='${libname}${release}${major}$shared_ext'
+  shlibpath_overrides_runpath=yes
+  shlibpath_var=DYLD_LIBRARY_PATH
+  shrext_cmds='`test .$module = .yes && echo .so || echo .dylib`'
+m4_if([$1], [],[
+  sys_lib_search_path_spec="$sys_lib_search_path_spec /usr/local/lib"])
+  sys_lib_dlsearch_path_spec='/usr/local/lib /lib /usr/lib'
+  ;;
+
+dgux*)
+  version_type=linux # correct to gnu/linux during the next big refactor
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname$shared_ext'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  shlibpath_var=LD_LIBRARY_PATH
+  ;;
+
+freebsd* | dragonfly*)
+  # DragonFly does not have aout.  When/if they implement a new
+  # versioning mechanism, adjust this.
+  if test -x /usr/bin/objformat; then
+    objformat=`/usr/bin/objformat`
+  else
+    case $host_os in
+    freebsd[[23]].*) objformat=aout ;;
+    *) objformat=elf ;;
+    esac
+  fi
+  version_type=freebsd-$objformat
+  case $version_type in
+    freebsd-elf*)
+      library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext} $libname${shared_ext}'
+      need_version=no
+      need_lib_prefix=no
+      ;;
+    freebsd-*)
+      library_names_spec='${libname}${release}${shared_ext}$versuffix $libname${shared_ext}$versuffix'
+      need_version=yes
+      ;;
+  esac
+  shlibpath_var=LD_LIBRARY_PATH
+  case $host_os in
+  freebsd2.*)
+    shlibpath_overrides_runpath=yes
+    ;;
+  freebsd3.[[01]]* | freebsdelf3.[[01]]*)
+    shlibpath_overrides_runpath=yes
+    hardcode_into_libs=yes
+    ;;
+  freebsd3.[[2-9]]* | freebsdelf3.[[2-9]]* | \
+  freebsd4.[[0-5]] | freebsdelf4.[[0-5]] | freebsd4.1.1 | freebsdelf4.1.1)
+    shlibpath_overrides_runpath=no
+    hardcode_into_libs=yes
+    ;;
+  *) # from 4.6 on, and DragonFly
+    shlibpath_overrides_runpath=yes
+    hardcode_into_libs=yes
+    ;;
+  esac
+  ;;
+
+gnu*)
+  version_type=linux # correct to gnu/linux during the next big refactor
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}${major} ${libname}${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=no
+  hardcode_into_libs=yes
+  ;;
+
+haiku*)
+  version_type=linux # correct to gnu/linux during the next big refactor
+  need_lib_prefix=no
+  need_version=no
+  dynamic_linker="$host_os runtime_loader"
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}${major} ${libname}${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  shlibpath_var=LIBRARY_PATH
+  shlibpath_overrides_runpath=yes
+  sys_lib_dlsearch_path_spec='/boot/home/config/lib /boot/common/lib /boot/system/lib'
+  hardcode_into_libs=yes
+  ;;
+
+hpux9* | hpux10* | hpux11*)
+  # Give a soname corresponding to the major version so that dld.sl refuses to
+  # link against other versions.
+  version_type=sunos
+  need_lib_prefix=no
+  need_version=no
+  case $host_cpu in
+  ia64*)
+    shrext_cmds='.so'
+    hardcode_into_libs=yes
+    dynamic_linker="$host_os dld.so"
+    shlibpath_var=LD_LIBRARY_PATH
+    shlibpath_overrides_runpath=yes # Unless +noenvvar is specified.
+    library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+    soname_spec='${libname}${release}${shared_ext}$major'
+    if test "X$HPUX_IA64_MODE" = X32; then
+      sys_lib_search_path_spec="/usr/lib/hpux32 /usr/local/lib/hpux32 /usr/local/lib"
+    else
+      sys_lib_search_path_spec="/usr/lib/hpux64 /usr/local/lib/hpux64"
+    fi
+    sys_lib_dlsearch_path_spec=$sys_lib_search_path_spec
+    ;;
+  hppa*64*)
+    shrext_cmds='.sl'
+    hardcode_into_libs=yes
+    dynamic_linker="$host_os dld.sl"
+    shlibpath_var=LD_LIBRARY_PATH # How should we handle SHLIB_PATH
+    shlibpath_overrides_runpath=yes # Unless +noenvvar is specified.
+    library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+    soname_spec='${libname}${release}${shared_ext}$major'
+    sys_lib_search_path_spec="/usr/lib/pa20_64 /usr/ccs/lib/pa20_64"
+    sys_lib_dlsearch_path_spec=$sys_lib_search_path_spec
+    ;;
+  *)
+    shrext_cmds='.sl'
+    dynamic_linker="$host_os dld.sl"
+    shlibpath_var=SHLIB_PATH
+    shlibpath_overrides_runpath=no # +s is required to enable SHLIB_PATH
+    library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+    soname_spec='${libname}${release}${shared_ext}$major'
+    ;;
+  esac
+  # HP-UX runs *really* slowly unless shared libraries are mode 555, ...
+  postinstall_cmds='chmod 555 $lib'
+  # or fails outright, so override atomically:
+  install_override_mode=555
+  ;;
+
+interix[[3-9]]*)
+  version_type=linux # correct to gnu/linux during the next big refactor
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  dynamic_linker='Interix 3.x ld.so.1 (PE, like ELF)'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=no
+  hardcode_into_libs=yes
+  ;;
+
+irix5* | irix6* | nonstopux*)
+  case $host_os in
+    nonstopux*) version_type=nonstopux ;;
+    *)
+	if test "$lt_cv_prog_gnu_ld" = yes; then
+		version_type=linux # correct to gnu/linux during the next big refactor
+	else
+		version_type=irix
+	fi ;;
+  esac
+  need_lib_prefix=no
+  need_version=no
+  soname_spec='${libname}${release}${shared_ext}$major'
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${release}${shared_ext} $libname${shared_ext}'
+  case $host_os in
+  irix5* | nonstopux*)
+    libsuff= shlibsuff=
+    ;;
+  *)
+    case $LD in # libtool.m4 will add one of these switches to LD
+    *-32|*"-32 "|*-melf32bsmip|*"-melf32bsmip ")
+      libsuff= shlibsuff= libmagic=32-bit;;
+    *-n32|*"-n32 "|*-melf32bmipn32|*"-melf32bmipn32 ")
+      libsuff=32 shlibsuff=N32 libmagic=N32;;
+    *-64|*"-64 "|*-melf64bmip|*"-melf64bmip ")
+      libsuff=64 shlibsuff=64 libmagic=64-bit;;
+    *) libsuff= shlibsuff= libmagic=never-match;;
+    esac
+    ;;
+  esac
+  shlibpath_var=LD_LIBRARY${shlibsuff}_PATH
+  shlibpath_overrides_runpath=no
+  sys_lib_search_path_spec="/usr/lib${libsuff} /lib${libsuff} /usr/local/lib${libsuff}"
+  sys_lib_dlsearch_path_spec="/usr/lib${libsuff} /lib${libsuff}"
+  hardcode_into_libs=yes
+  ;;
+
+# No shared lib support for Linux oldld, aout, or coff.
+linux*oldld* | linux*aout* | linux*coff*)
+  dynamic_linker=no
+  ;;
+
+# This must be glibc/ELF.
+linux* | k*bsd*-gnu | kopensolaris*-gnu)
+  version_type=linux # correct to gnu/linux during the next big refactor
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  finish_cmds='PATH="\$PATH:/sbin" ldconfig -n $libdir'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=no
+
+  # Some binutils ld are patched to set DT_RUNPATH
+  AC_CACHE_VAL([lt_cv_shlibpath_overrides_runpath],
+    [lt_cv_shlibpath_overrides_runpath=no
+    save_LDFLAGS=$LDFLAGS
+    save_libdir=$libdir
+    eval "libdir=/foo; wl=\"$_LT_TAGVAR(lt_prog_compiler_wl, $1)\"; \
+	 LDFLAGS=\"\$LDFLAGS $_LT_TAGVAR(hardcode_libdir_flag_spec, $1)\""
+    AC_LINK_IFELSE([AC_LANG_PROGRAM([],[])],
+      [AS_IF([ ($OBJDUMP -p conftest$ac_exeext) 2>/dev/null | grep "RUNPATH.*$libdir" >/dev/null],
+	 [lt_cv_shlibpath_overrides_runpath=yes])])
+    LDFLAGS=$save_LDFLAGS
+    libdir=$save_libdir
+    ])
+  shlibpath_overrides_runpath=$lt_cv_shlibpath_overrides_runpath
+
+  # This implies no fast_install, which is unacceptable.
+  # Some rework will be needed to allow for fast_install
+  # before this can be enabled.
+  hardcode_into_libs=yes
+
+  # Append ld.so.conf contents to the search path
+  if test -f /etc/ld.so.conf; then
+    lt_ld_extra=`awk '/^include / { system(sprintf("cd /etc; cat %s 2>/dev/null", \[$]2)); skip = 1; } { if (!skip) print \[$]0; skip = 0; }' < /etc/ld.so.conf | $SED -e 's/#.*//;/^[	 ]*hwcap[	 ]/d;s/[:,	]/ /g;s/=[^=]*$//;s/=[^= ]* / /g;s/"//g;/^$/d' | tr '\n' ' '`
+    sys_lib_dlsearch_path_spec="/lib /usr/lib $lt_ld_extra"
+  fi
+
+  # We used to test for /lib/ld.so.1 and disable shared libraries on
+  # powerpc, because MkLinux only supported shared libraries with the
+  # GNU dynamic linker.  Since this was broken with cross compilers,
+  # most powerpc-linux boxes support dynamic linking these days and
+  # people can always --disable-shared, the test was removed, and we
+  # assume the GNU/Linux dynamic linker is in use.
+  dynamic_linker='GNU/Linux ld.so'
+  ;;
+
+netbsd*)
+  version_type=sunos
+  need_lib_prefix=no
+  need_version=no
+  if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then
+    library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix'
+    finish_cmds='PATH="\$PATH:/sbin" ldconfig -m $libdir'
+    dynamic_linker='NetBSD (a.out) ld.so'
+  else
+    library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${shared_ext}'
+    soname_spec='${libname}${release}${shared_ext}$major'
+    dynamic_linker='NetBSD ld.elf_so'
+  fi
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=yes
+  hardcode_into_libs=yes
+  ;;
+
+newsos6)
+  version_type=linux # correct to gnu/linux during the next big refactor
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=yes
+  ;;
+
+*nto* | *qnx*)
+  version_type=qnx
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=no
+  hardcode_into_libs=yes
+  dynamic_linker='ldqnx.so'
+  ;;
+
+openbsd*)
+  version_type=sunos
+  sys_lib_dlsearch_path_spec="/usr/lib"
+  need_lib_prefix=no
+  # Some older versions of OpenBSD (3.3 at least) *do* need versioned libs.
+  case $host_os in
+    openbsd3.3 | openbsd3.3.*)	need_version=yes ;;
+    *)				need_version=no  ;;
+  esac
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix'
+  finish_cmds='PATH="\$PATH:/sbin" ldconfig -m $libdir'
+  shlibpath_var=LD_LIBRARY_PATH
+  if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then
+    case $host_os in
+      openbsd2.[[89]] | openbsd2.[[89]].*)
+	shlibpath_overrides_runpath=no
+	;;
+      *)
+	shlibpath_overrides_runpath=yes
+	;;
+      esac
+  else
+    shlibpath_overrides_runpath=yes
+  fi
+  ;;
+
+os2*)
+  libname_spec='$name'
+  shrext_cmds=".dll"
+  need_lib_prefix=no
+  library_names_spec='$libname${shared_ext} $libname.a'
+  dynamic_linker='OS/2 ld.exe'
+  shlibpath_var=LIBPATH
+  ;;
+
+osf3* | osf4* | osf5*)
+  version_type=osf
+  need_lib_prefix=no
+  need_version=no
+  soname_spec='${libname}${release}${shared_ext}$major'
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  shlibpath_var=LD_LIBRARY_PATH
+  sys_lib_search_path_spec="/usr/shlib /usr/ccs/lib /usr/lib/cmplrs/cc /usr/lib /usr/local/lib /var/shlib"
+  sys_lib_dlsearch_path_spec="$sys_lib_search_path_spec"
+  ;;
+
+rdos*)
+  dynamic_linker=no
+  ;;
+
+solaris*)
+  version_type=linux # correct to gnu/linux during the next big refactor
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=yes
+  hardcode_into_libs=yes
+  # ldd complains unless libraries are executable
+  postinstall_cmds='chmod +x $lib'
+  ;;
+
+sunos4*)
+  version_type=sunos
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix'
+  finish_cmds='PATH="\$PATH:/usr/etc" ldconfig $libdir'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=yes
+  if test "$with_gnu_ld" = yes; then
+    need_lib_prefix=no
+  fi
+  need_version=yes
+  ;;
+
+sysv4 | sysv4.3*)
+  version_type=linux # correct to gnu/linux during the next big refactor
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  shlibpath_var=LD_LIBRARY_PATH
+  case $host_vendor in
+    sni)
+      shlibpath_overrides_runpath=no
+      need_lib_prefix=no
+      runpath_var=LD_RUN_PATH
+      ;;
+    siemens)
+      need_lib_prefix=no
+      ;;
+    motorola)
+      need_lib_prefix=no
+      need_version=no
+      shlibpath_overrides_runpath=no
+      sys_lib_search_path_spec='/lib /usr/lib /usr/ccs/lib'
+      ;;
+  esac
+  ;;
+
+sysv4*MP*)
+  if test -d /usr/nec ;then
+    version_type=linux # correct to gnu/linux during the next big refactor
+    library_names_spec='$libname${shared_ext}.$versuffix $libname${shared_ext}.$major $libname${shared_ext}'
+    soname_spec='$libname${shared_ext}.$major'
+    shlibpath_var=LD_LIBRARY_PATH
+  fi
+  ;;
+
+sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX* | sysv4*uw2*)
+  version_type=freebsd-elf
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext} $libname${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=yes
+  hardcode_into_libs=yes
+  if test "$with_gnu_ld" = yes; then
+    sys_lib_search_path_spec='/usr/local/lib /usr/gnu/lib /usr/ccs/lib /usr/lib /lib'
+  else
+    sys_lib_search_path_spec='/usr/ccs/lib /usr/lib'
+    case $host_os in
+      sco3.2v5*)
+        sys_lib_search_path_spec="$sys_lib_search_path_spec /lib"
+	;;
+    esac
+  fi
+  sys_lib_dlsearch_path_spec='/usr/lib'
+  ;;
+
+tpf*)
+  # TPF is a cross-target only.  Preferred cross-host = GNU/Linux.
+  version_type=linux # correct to gnu/linux during the next big refactor
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=no
+  hardcode_into_libs=yes
+  ;;
+
+uts4*)
+  version_type=linux # correct to gnu/linux during the next big refactor
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  shlibpath_var=LD_LIBRARY_PATH
+  ;;
+
+*)
+  dynamic_linker=no
+  ;;
+esac
+AC_MSG_RESULT([$dynamic_linker])
+test "$dynamic_linker" = no && can_build_shared=no
+
+variables_saved_for_relink="PATH $shlibpath_var $runpath_var"
+if test "$GCC" = yes; then
+  variables_saved_for_relink="$variables_saved_for_relink GCC_EXEC_PREFIX COMPILER_PATH LIBRARY_PATH"
+fi
+
+if test "${lt_cv_sys_lib_search_path_spec+set}" = set; then
+  sys_lib_search_path_spec="$lt_cv_sys_lib_search_path_spec"
+fi
+if test "${lt_cv_sys_lib_dlsearch_path_spec+set}" = set; then
+  sys_lib_dlsearch_path_spec="$lt_cv_sys_lib_dlsearch_path_spec"
+fi
+
+_LT_DECL([], [variables_saved_for_relink], [1],
+    [Variables whose values should be saved in libtool wrapper scripts and
+    restored at link time])
+_LT_DECL([], [need_lib_prefix], [0],
+    [Do we need the "lib" prefix for modules?])
+_LT_DECL([], [need_version], [0], [Do we need a version for libraries?])
+_LT_DECL([], [version_type], [0], [Library versioning type])
+_LT_DECL([], [runpath_var], [0],  [Shared library runtime path variable])
+_LT_DECL([], [shlibpath_var], [0],[Shared library path variable])
+_LT_DECL([], [shlibpath_overrides_runpath], [0],
+    [Is shlibpath searched before the hard-coded library search path?])
+_LT_DECL([], [libname_spec], [1], [Format of library name prefix])
+_LT_DECL([], [library_names_spec], [1],
+    [[List of archive names.  First name is the real one, the rest are links.
+    The last name is the one that the linker finds with -lNAME]])
+_LT_DECL([], [soname_spec], [1],
+    [[The coded name of the library, if different from the real name]])
+_LT_DECL([], [install_override_mode], [1],
+    [Permission mode override for installation of shared libraries])
+_LT_DECL([], [postinstall_cmds], [2],
+    [Command to use after installation of a shared archive])
+_LT_DECL([], [postuninstall_cmds], [2],
+    [Command to use after uninstallation of a shared archive])
+_LT_DECL([], [finish_cmds], [2],
+    [Commands used to finish a libtool library installation in a directory])
+_LT_DECL([], [finish_eval], [1],
+    [[As "finish_cmds", except a single script fragment to be evaled but
+    not shown]])
+_LT_DECL([], [hardcode_into_libs], [0],
+    [Whether we should hardcode library paths into libraries])
+_LT_DECL([], [sys_lib_search_path_spec], [2],
+    [Compile-time system search path for libraries])
+_LT_DECL([], [sys_lib_dlsearch_path_spec], [2],
+    [Run-time system search path for libraries])
+])# _LT_SYS_DYNAMIC_LINKER
+
+
+# _LT_PATH_TOOL_PREFIX(TOOL)
+# --------------------------
+# find a file program which can recognize shared library
+AC_DEFUN([_LT_PATH_TOOL_PREFIX],
+[m4_require([_LT_DECL_EGREP])dnl
+AC_MSG_CHECKING([for $1])
+AC_CACHE_VAL(lt_cv_path_MAGIC_CMD,
+[case $MAGIC_CMD in
+[[\\/*] |  ?:[\\/]*])
+  lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path.
+  ;;
+*)
+  lt_save_MAGIC_CMD="$MAGIC_CMD"
+  lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR
+dnl $ac_dummy forces splitting on constant user-supplied paths.
+dnl POSIX.2 word splitting is done only on the output of word expansions,
+dnl not every word.  This closes a longstanding sh security hole.
+  ac_dummy="m4_if([$2], , $PATH, [$2])"
+  for ac_dir in $ac_dummy; do
+    IFS="$lt_save_ifs"
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/$1; then
+      lt_cv_path_MAGIC_CMD="$ac_dir/$1"
+      if test -n "$file_magic_test_file"; then
+	case $deplibs_check_method in
+	"file_magic "*)
+	  file_magic_regex=`expr "$deplibs_check_method" : "file_magic \(.*\)"`
+	  MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
+	  if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null |
+	    $EGREP "$file_magic_regex" > /dev/null; then
+	    :
+	  else
+	    cat <<_LT_EOF 1>&2
+
+*** Warning: the command libtool uses to detect shared libraries,
+*** $file_magic_cmd, produces output that libtool cannot recognize.
+*** The result is that libtool may fail to recognize shared libraries
+*** as such.  This will affect the creation of libtool libraries that
+*** depend on shared libraries, but programs linked with such libtool
+*** libraries will work regardless of this problem.  Nevertheless, you
+*** may want to report the problem to your system manager and/or to
+*** bug-libtool@gnu.org
+
+_LT_EOF
+	  fi ;;
+	esac
+      fi
+      break
+    fi
+  done
+  IFS="$lt_save_ifs"
+  MAGIC_CMD="$lt_save_MAGIC_CMD"
+  ;;
+esac])
+MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
+if test -n "$MAGIC_CMD"; then
+  AC_MSG_RESULT($MAGIC_CMD)
+else
+  AC_MSG_RESULT(no)
+fi
+_LT_DECL([], [MAGIC_CMD], [0],
+	 [Used to examine libraries when file_magic_cmd begins with "file"])dnl
+])# _LT_PATH_TOOL_PREFIX
+
+# Old name:
+AU_ALIAS([AC_PATH_TOOL_PREFIX], [_LT_PATH_TOOL_PREFIX])
+dnl aclocal-1.4 backwards compatibility:
+dnl AC_DEFUN([AC_PATH_TOOL_PREFIX], [])
+
+
+# _LT_PATH_MAGIC
+# --------------
+# find a file program which can recognize a shared library
+m4_defun([_LT_PATH_MAGIC],
+[_LT_PATH_TOOL_PREFIX(${ac_tool_prefix}file, /usr/bin$PATH_SEPARATOR$PATH)
+if test -z "$lt_cv_path_MAGIC_CMD"; then
+  if test -n "$ac_tool_prefix"; then
+    _LT_PATH_TOOL_PREFIX(file, /usr/bin$PATH_SEPARATOR$PATH)
+  else
+    MAGIC_CMD=:
+  fi
+fi
+])# _LT_PATH_MAGIC
+
+
+# LT_PATH_LD
+# ----------
+# find the pathname to the GNU or non-GNU linker
+AC_DEFUN([LT_PATH_LD],
+[AC_REQUIRE([AC_PROG_CC])dnl
+AC_REQUIRE([AC_CANONICAL_HOST])dnl
+AC_REQUIRE([AC_CANONICAL_BUILD])dnl
+m4_require([_LT_DECL_SED])dnl
+m4_require([_LT_DECL_EGREP])dnl
+m4_require([_LT_PROG_ECHO_BACKSLASH])dnl
+
+AC_ARG_WITH([gnu-ld],
+    [AS_HELP_STRING([--with-gnu-ld],
+	[assume the C compiler uses GNU ld @<:@default=no@:>@])],
+    [test "$withval" = no || with_gnu_ld=yes],
+    [with_gnu_ld=no])dnl
+
+ac_prog=ld
+if test "$GCC" = yes; then
+  # Check if gcc -print-prog-name=ld gives a path.
+  AC_MSG_CHECKING([for ld used by $CC])
+  case $host in
+  *-*-mingw*)
+    # gcc leaves a trailing carriage return which upsets mingw
+    ac_prog=`($CC -print-prog-name=ld) 2>&5 | tr -d '\015'` ;;
+  *)
+    ac_prog=`($CC -print-prog-name=ld) 2>&5` ;;
+  esac
+  case $ac_prog in
+    # Accept absolute paths.
+    [[\\/]]* | ?:[[\\/]]*)
+      re_direlt='/[[^/]][[^/]]*/\.\./'
+      # Canonicalize the pathname of ld
+      ac_prog=`$ECHO "$ac_prog"| $SED 's%\\\\%/%g'`
+      while $ECHO "$ac_prog" | $GREP "$re_direlt" > /dev/null 2>&1; do
+	ac_prog=`$ECHO $ac_prog| $SED "s%$re_direlt%/%"`
+      done
+      test -z "$LD" && LD="$ac_prog"
+      ;;
+  "")
+    # If it fails, then pretend we aren't using GCC.
+    ac_prog=ld
+    ;;
+  *)
+    # If it is relative, then search for the first ld in PATH.
+    with_gnu_ld=unknown
+    ;;
+  esac
+elif test "$with_gnu_ld" = yes; then
+  AC_MSG_CHECKING([for GNU ld])
+else
+  AC_MSG_CHECKING([for non-GNU ld])
+fi
+AC_CACHE_VAL(lt_cv_path_LD,
+[if test -z "$LD"; then
+  lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR
+  for ac_dir in $PATH; do
+    IFS="$lt_save_ifs"
+    test -z "$ac_dir" && ac_dir=.
+    if test -f "$ac_dir/$ac_prog" || test -f "$ac_dir/$ac_prog$ac_exeext"; then
+      lt_cv_path_LD="$ac_dir/$ac_prog"
+      # Check to see if the program is GNU ld.  I'd rather use --version,
+      # but apparently some variants of GNU ld only accept -v.
+      # Break only if it was the GNU/non-GNU ld that we prefer.
+      case `"$lt_cv_path_LD" -v 2>&1 &1 /dev/null 2>&1; then
+    lt_cv_deplibs_check_method='file_magic ^x86 archive import|^x86 DLL'
+    lt_cv_file_magic_cmd='func_win32_libid'
+  else
+    # Keep this pattern in sync with the one in func_win32_libid.
+    lt_cv_deplibs_check_method='file_magic file format (pei*-i386(.*architecture: i386)?|pe-arm-wince|pe-x86-64)'
+    lt_cv_file_magic_cmd='$OBJDUMP -f'
+  fi
+  ;;
+
+cegcc*)
+  # use the weaker test based on 'objdump'. See mingw*.
+  lt_cv_deplibs_check_method='file_magic file format pe-arm-.*little(.*architecture: arm)?'
+  lt_cv_file_magic_cmd='$OBJDUMP -f'
+  ;;
+
+darwin* | rhapsody*)
+  lt_cv_deplibs_check_method=pass_all
+  ;;
+
+freebsd* | dragonfly*)
+  if echo __ELF__ | $CC -E - | $GREP __ELF__ > /dev/null; then
+    case $host_cpu in
+    i*86 )
+      # Not sure whether the presence of OpenBSD here was a mistake.
+      # Let's accept both of them until this is cleared up.
+      lt_cv_deplibs_check_method='file_magic (FreeBSD|OpenBSD|DragonFly)/i[[3-9]]86 (compact )?demand paged shared library'
+      lt_cv_file_magic_cmd=/usr/bin/file
+      lt_cv_file_magic_test_file=`echo /usr/lib/libc.so.*`
+      ;;
+    esac
+  else
+    lt_cv_deplibs_check_method=pass_all
+  fi
+  ;;
+
+gnu*)
+  lt_cv_deplibs_check_method=pass_all
+  ;;
+
+haiku*)
+  lt_cv_deplibs_check_method=pass_all
+  ;;
+
+hpux10.20* | hpux11*)
+  lt_cv_file_magic_cmd=/usr/bin/file
+  case $host_cpu in
+  ia64*)
+    lt_cv_deplibs_check_method='file_magic (s[[0-9]][[0-9]][[0-9]]|ELF-[[0-9]][[0-9]]) shared object file - IA64'
+    lt_cv_file_magic_test_file=/usr/lib/hpux32/libc.so
+    ;;
+  hppa*64*)
+    [lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|ELF[ -][0-9][0-9])(-bit)?( [LM]SB)? shared object( file)?[, -]* PA-RISC [0-9]\.[0-9]']
+    lt_cv_file_magic_test_file=/usr/lib/pa20_64/libc.sl
+    ;;
+  *)
+    lt_cv_deplibs_check_method='file_magic (s[[0-9]][[0-9]][[0-9]]|PA-RISC[[0-9]]\.[[0-9]]) shared library'
+    lt_cv_file_magic_test_file=/usr/lib/libc.sl
+    ;;
+  esac
+  ;;
+
+interix[[3-9]]*)
+  # PIC code is broken on Interix 3.x, that's why |\.a not |_pic\.a here
+  lt_cv_deplibs_check_method='match_pattern /lib[[^/]]+(\.so|\.a)$'
+  ;;
+
+irix5* | irix6* | nonstopux*)
+  case $LD in
+  *-32|*"-32 ") libmagic=32-bit;;
+  *-n32|*"-n32 ") libmagic=N32;;
+  *-64|*"-64 ") libmagic=64-bit;;
+  *) libmagic=never-match;;
+  esac
+  lt_cv_deplibs_check_method=pass_all
+  ;;
+
+# This must be glibc/ELF.
+linux* | k*bsd*-gnu | kopensolaris*-gnu)
+  lt_cv_deplibs_check_method=pass_all
+  ;;
+
+netbsd*)
+  if echo __ELF__ | $CC -E - | $GREP __ELF__ > /dev/null; then
+    lt_cv_deplibs_check_method='match_pattern /lib[[^/]]+(\.so\.[[0-9]]+\.[[0-9]]+|_pic\.a)$'
+  else
+    lt_cv_deplibs_check_method='match_pattern /lib[[^/]]+(\.so|_pic\.a)$'
+  fi
+  ;;
+
+newos6*)
+  lt_cv_deplibs_check_method='file_magic ELF [[0-9]][[0-9]]*-bit [[ML]]SB (executable|dynamic lib)'
+  lt_cv_file_magic_cmd=/usr/bin/file
+  lt_cv_file_magic_test_file=/usr/lib/libnls.so
+  ;;
+
+*nto* | *qnx*)
+  lt_cv_deplibs_check_method=pass_all
+  ;;
+
+openbsd*)
+  if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then
+    lt_cv_deplibs_check_method='match_pattern /lib[[^/]]+(\.so\.[[0-9]]+\.[[0-9]]+|\.so|_pic\.a)$'
+  else
+    lt_cv_deplibs_check_method='match_pattern /lib[[^/]]+(\.so\.[[0-9]]+\.[[0-9]]+|_pic\.a)$'
+  fi
+  ;;
+
+osf3* | osf4* | osf5*)
+  lt_cv_deplibs_check_method=pass_all
+  ;;
+
+rdos*)
+  lt_cv_deplibs_check_method=pass_all
+  ;;
+
+solaris*)
+  lt_cv_deplibs_check_method=pass_all
+  ;;
+
+sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX* | sysv4*uw2*)
+  lt_cv_deplibs_check_method=pass_all
+  ;;
+
+sysv4 | sysv4.3*)
+  case $host_vendor in
+  motorola)
+    lt_cv_deplibs_check_method='file_magic ELF [[0-9]][[0-9]]*-bit [[ML]]SB (shared object|dynamic lib) M[[0-9]][[0-9]]* Version [[0-9]]'
+    lt_cv_file_magic_test_file=`echo /usr/lib/libc.so*`
+    ;;
+  ncr)
+    lt_cv_deplibs_check_method=pass_all
+    ;;
+  sequent)
+    lt_cv_file_magic_cmd='/bin/file'
+    lt_cv_deplibs_check_method='file_magic ELF [[0-9]][[0-9]]*-bit [[LM]]SB (shared object|dynamic lib )'
+    ;;
+  sni)
+    lt_cv_file_magic_cmd='/bin/file'
+    lt_cv_deplibs_check_method="file_magic ELF [[0-9]][[0-9]]*-bit [[LM]]SB dynamic lib"
+    lt_cv_file_magic_test_file=/lib/libc.so
+    ;;
+  siemens)
+    lt_cv_deplibs_check_method=pass_all
+    ;;
+  pc)
+    lt_cv_deplibs_check_method=pass_all
+    ;;
+  esac
+  ;;
+
+tpf*)
+  lt_cv_deplibs_check_method=pass_all
+  ;;
+esac
+])
+
+file_magic_glob=
+want_nocaseglob=no
+if test "$build" = "$host"; then
+  case $host_os in
+  mingw* | pw32*)
+    if ( shopt | grep nocaseglob ) >/dev/null 2>&1; then
+      want_nocaseglob=yes
+    else
+      file_magic_glob=`echo aAbBcCdDeEfFgGhHiIjJkKlLmMnNoOpPqQrRsStTuUvVwWxXyYzZ | $SED -e "s/\(..\)/s\/[[\1]]\/[[\1]]\/g;/g"`
+    fi
+    ;;
+  esac
+fi
+
+file_magic_cmd=$lt_cv_file_magic_cmd
+deplibs_check_method=$lt_cv_deplibs_check_method
+test -z "$deplibs_check_method" && deplibs_check_method=unknown
+
+_LT_DECL([], [deplibs_check_method], [1],
+    [Method to check whether dependent libraries are shared objects])
+_LT_DECL([], [file_magic_cmd], [1],
+    [Command to use when deplibs_check_method = "file_magic"])
+_LT_DECL([], [file_magic_glob], [1],
+    [How to find potential files when deplibs_check_method = "file_magic"])
+_LT_DECL([], [want_nocaseglob], [1],
+    [Find potential files using nocaseglob when deplibs_check_method = "file_magic"])
+])# _LT_CHECK_MAGIC_METHOD
+
+
+# LT_PATH_NM
+# ----------
+# find the pathname to a BSD- or MS-compatible name lister
+AC_DEFUN([LT_PATH_NM],
+[AC_REQUIRE([AC_PROG_CC])dnl
+AC_CACHE_CHECK([for BSD- or MS-compatible name lister (nm)], lt_cv_path_NM,
+[if test -n "$NM"; then
+  # Let the user override the test.
+  lt_cv_path_NM="$NM"
+else
+  lt_nm_to_check="${ac_tool_prefix}nm"
+  if test -n "$ac_tool_prefix" && test "$build" = "$host"; then
+    lt_nm_to_check="$lt_nm_to_check nm"
+  fi
+  for lt_tmp_nm in $lt_nm_to_check; do
+    lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR
+    for ac_dir in $PATH /usr/ccs/bin/elf /usr/ccs/bin /usr/ucb /bin; do
+      IFS="$lt_save_ifs"
+      test -z "$ac_dir" && ac_dir=.
+      tmp_nm="$ac_dir/$lt_tmp_nm"
+      if test -f "$tmp_nm" || test -f "$tmp_nm$ac_exeext" ; then
+	# Check to see if the nm accepts a BSD-compat flag.
+	# Adding the `sed 1q' prevents false positives on HP-UX, which says:
+	#   nm: unknown option "B" ignored
+	# Tru64's nm complains that /dev/null is an invalid object file
+	case `"$tmp_nm" -B /dev/null 2>&1 | sed '1q'` in
+	*/dev/null* | *'Invalid file or object type'*)
+	  lt_cv_path_NM="$tmp_nm -B"
+	  break
+	  ;;
+	*)
+	  case `"$tmp_nm" -p /dev/null 2>&1 | sed '1q'` in
+	  */dev/null*)
+	    lt_cv_path_NM="$tmp_nm -p"
+	    break
+	    ;;
+	  *)
+	    lt_cv_path_NM=${lt_cv_path_NM="$tmp_nm"} # keep the first match, but
+	    continue # so that we can try to find one that supports BSD flags
+	    ;;
+	  esac
+	  ;;
+	esac
+      fi
+    done
+    IFS="$lt_save_ifs"
+  done
+  : ${lt_cv_path_NM=no}
+fi])
+if test "$lt_cv_path_NM" != "no"; then
+  NM="$lt_cv_path_NM"
+else
+  # Didn't find any BSD compatible name lister, look for dumpbin.
+  if test -n "$DUMPBIN"; then :
+    # Let the user override the test.
+  else
+    AC_CHECK_TOOLS(DUMPBIN, [dumpbin "link -dump"], :)
+    case `$DUMPBIN -symbols /dev/null 2>&1 | sed '1q'` in
+    *COFF*)
+      DUMPBIN="$DUMPBIN -symbols"
+      ;;
+    *)
+      DUMPBIN=:
+      ;;
+    esac
+  fi
+  AC_SUBST([DUMPBIN])
+  if test "$DUMPBIN" != ":"; then
+    NM="$DUMPBIN"
+  fi
+fi
+test -z "$NM" && NM=nm
+AC_SUBST([NM])
+_LT_DECL([], [NM], [1], [A BSD- or MS-compatible name lister])dnl
+
+AC_CACHE_CHECK([the name lister ($NM) interface], [lt_cv_nm_interface],
+  [lt_cv_nm_interface="BSD nm"
+  echo "int some_variable = 0;" > conftest.$ac_ext
+  (eval echo "\"\$as_me:$LINENO: $ac_compile\"" >&AS_MESSAGE_LOG_FD)
+  (eval "$ac_compile" 2>conftest.err)
+  cat conftest.err >&AS_MESSAGE_LOG_FD
+  (eval echo "\"\$as_me:$LINENO: $NM \\\"conftest.$ac_objext\\\"\"" >&AS_MESSAGE_LOG_FD)
+  (eval "$NM \"conftest.$ac_objext\"" 2>conftest.err > conftest.out)
+  cat conftest.err >&AS_MESSAGE_LOG_FD
+  (eval echo "\"\$as_me:$LINENO: output\"" >&AS_MESSAGE_LOG_FD)
+  cat conftest.out >&AS_MESSAGE_LOG_FD
+  if $GREP 'External.*some_variable' conftest.out > /dev/null; then
+    lt_cv_nm_interface="MS dumpbin"
+  fi
+  rm -f conftest*])
+])# LT_PATH_NM
+
+# Old names:
+AU_ALIAS([AM_PROG_NM], [LT_PATH_NM])
+AU_ALIAS([AC_PROG_NM], [LT_PATH_NM])
+dnl aclocal-1.4 backwards compatibility:
+dnl AC_DEFUN([AM_PROG_NM], [])
+dnl AC_DEFUN([AC_PROG_NM], [])
+
+# _LT_CHECK_SHAREDLIB_FROM_LINKLIB
+# --------------------------------
+# how to determine the name of the shared library
+# associated with a specific link library.
+#  -- PORTME fill in with the dynamic library characteristics
+m4_defun([_LT_CHECK_SHAREDLIB_FROM_LINKLIB],
+[m4_require([_LT_DECL_EGREP])
+m4_require([_LT_DECL_OBJDUMP])
+m4_require([_LT_DECL_DLLTOOL])
+AC_CACHE_CHECK([how to associate runtime and link libraries],
+lt_cv_sharedlib_from_linklib_cmd,
+[lt_cv_sharedlib_from_linklib_cmd='unknown'
+
+case $host_os in
+cygwin* | mingw* | pw32* | cegcc*)
+  # two different shell functions defined in ltmain.sh
+  # decide which to use based on capabilities of $DLLTOOL
+  case `$DLLTOOL --help 2>&1` in
+  *--identify-strict*)
+    lt_cv_sharedlib_from_linklib_cmd=func_cygming_dll_for_implib
+    ;;
+  *)
+    lt_cv_sharedlib_from_linklib_cmd=func_cygming_dll_for_implib_fallback
+    ;;
+  esac
+  ;;
+*)
+  # fallback: assume linklib IS sharedlib
+  lt_cv_sharedlib_from_linklib_cmd="$ECHO"
+  ;;
+esac
+])
+sharedlib_from_linklib_cmd=$lt_cv_sharedlib_from_linklib_cmd
+test -z "$sharedlib_from_linklib_cmd" && sharedlib_from_linklib_cmd=$ECHO
+
+_LT_DECL([], [sharedlib_from_linklib_cmd], [1],
+    [Command to associate shared and link libraries])
+])# _LT_CHECK_SHAREDLIB_FROM_LINKLIB
+
+
+# _LT_PATH_MANIFEST_TOOL
+# ----------------------
+# locate the manifest tool
+m4_defun([_LT_PATH_MANIFEST_TOOL],
+[AC_CHECK_TOOL(MANIFEST_TOOL, mt, :)
+test -z "$MANIFEST_TOOL" && MANIFEST_TOOL=mt
+AC_CACHE_CHECK([if $MANIFEST_TOOL is a manifest tool], [lt_cv_path_mainfest_tool],
+  [lt_cv_path_mainfest_tool=no
+  echo "$as_me:$LINENO: $MANIFEST_TOOL '-?'" >&AS_MESSAGE_LOG_FD
+  $MANIFEST_TOOL '-?' 2>conftest.err > conftest.out
+  cat conftest.err >&AS_MESSAGE_LOG_FD
+  if $GREP 'Manifest Tool' conftest.out > /dev/null; then
+    lt_cv_path_mainfest_tool=yes
+  fi
+  rm -f conftest*])
+if test "x$lt_cv_path_mainfest_tool" != xyes; then
+  MANIFEST_TOOL=:
+fi
+_LT_DECL([], [MANIFEST_TOOL], [1], [Manifest tool])dnl
+])# _LT_PATH_MANIFEST_TOOL
+
+
+# LT_LIB_M
+# --------
+# check for math library
+AC_DEFUN([LT_LIB_M],
+[AC_REQUIRE([AC_CANONICAL_HOST])dnl
+LIBM=
+case $host in
+*-*-beos* | *-*-cegcc* | *-*-cygwin* | *-*-haiku* | *-*-pw32* | *-*-darwin*)
+  # These system don't have libm, or don't need it
+  ;;
+*-ncr-sysv4.3*)
+  AC_CHECK_LIB(mw, _mwvalidcheckl, LIBM="-lmw")
+  AC_CHECK_LIB(m, cos, LIBM="$LIBM -lm")
+  ;;
+*)
+  AC_CHECK_LIB(m, cos, LIBM="-lm")
+  ;;
+esac
+AC_SUBST([LIBM])
+])# LT_LIB_M
+
+# Old name:
+AU_ALIAS([AC_CHECK_LIBM], [LT_LIB_M])
+dnl aclocal-1.4 backwards compatibility:
+dnl AC_DEFUN([AC_CHECK_LIBM], [])
+
+
+# _LT_COMPILER_NO_RTTI([TAGNAME])
+# -------------------------------
+m4_defun([_LT_COMPILER_NO_RTTI],
+[m4_require([_LT_TAG_COMPILER])dnl
+
+_LT_TAGVAR(lt_prog_compiler_no_builtin_flag, $1)=
+
+if test "$GCC" = yes; then
+  case $cc_basename in
+  nvcc*)
+    _LT_TAGVAR(lt_prog_compiler_no_builtin_flag, $1)=' -Xcompiler -fno-builtin' ;;
+  *)
+    _LT_TAGVAR(lt_prog_compiler_no_builtin_flag, $1)=' -fno-builtin' ;;
+  esac
+
+  _LT_COMPILER_OPTION([if $compiler supports -fno-rtti -fno-exceptions],
+    lt_cv_prog_compiler_rtti_exceptions,
+    [-fno-rtti -fno-exceptions], [],
+    [_LT_TAGVAR(lt_prog_compiler_no_builtin_flag, $1)="$_LT_TAGVAR(lt_prog_compiler_no_builtin_flag, $1) -fno-rtti -fno-exceptions"])
+fi
+_LT_TAGDECL([no_builtin_flag], [lt_prog_compiler_no_builtin_flag], [1],
+	[Compiler flag to turn off builtin functions])
+])# _LT_COMPILER_NO_RTTI
+
+
+# _LT_CMD_GLOBAL_SYMBOLS
+# ----------------------
+m4_defun([_LT_CMD_GLOBAL_SYMBOLS],
+[AC_REQUIRE([AC_CANONICAL_HOST])dnl
+AC_REQUIRE([AC_PROG_CC])dnl
+AC_REQUIRE([AC_PROG_AWK])dnl
+AC_REQUIRE([LT_PATH_NM])dnl
+AC_REQUIRE([LT_PATH_LD])dnl
+m4_require([_LT_DECL_SED])dnl
+m4_require([_LT_DECL_EGREP])dnl
+m4_require([_LT_TAG_COMPILER])dnl
+
+# Check for command to grab the raw symbol name followed by C symbol from nm.
+AC_MSG_CHECKING([command to parse $NM output from $compiler object])
+AC_CACHE_VAL([lt_cv_sys_global_symbol_pipe],
+[
+# These are sane defaults that work on at least a few old systems.
+# [They come from Ultrix.  What could be older than Ultrix?!! ;)]
+
+# Character class describing NM global symbol codes.
+symcode='[[BCDEGRST]]'
+
+# Regexp to match symbols that can be accessed directly from C.
+sympat='\([[_A-Za-z]][[_A-Za-z0-9]]*\)'
+
+# Define system-specific variables.
+case $host_os in
+aix*)
+  symcode='[[BCDT]]'
+  ;;
+cygwin* | mingw* | pw32* | cegcc*)
+  symcode='[[ABCDGISTW]]'
+  ;;
+hpux*)
+  if test "$host_cpu" = ia64; then
+    symcode='[[ABCDEGRST]]'
+  fi
+  ;;
+irix* | nonstopux*)
+  symcode='[[BCDEGRST]]'
+  ;;
+osf*)
+  symcode='[[BCDEGQRST]]'
+  ;;
+solaris*)
+  symcode='[[BDRT]]'
+  ;;
+sco3.2v5*)
+  symcode='[[DT]]'
+  ;;
+sysv4.2uw2*)
+  symcode='[[DT]]'
+  ;;
+sysv5* | sco5v6* | unixware* | OpenUNIX*)
+  symcode='[[ABDT]]'
+  ;;
+sysv4)
+  symcode='[[DFNSTU]]'
+  ;;
+esac
+
+# If we're using GNU nm, then use its standard symbol codes.
+case `$NM -V 2>&1` in
+*GNU* | *'with BFD'*)
+  symcode='[[ABCDGIRSTW]]' ;;
+esac
+
+# Transform an extracted symbol line into a proper C declaration.
+# Some systems (esp. on ia64) link data and code symbols differently,
+# so use this general approach.
+lt_cv_sys_global_symbol_to_cdecl="sed -n -e 's/^T .* \(.*\)$/extern int \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'"
+
+# Transform an extracted symbol line into symbol name and symbol address
+lt_cv_sys_global_symbol_to_c_name_address="sed -n -e 's/^: \([[^ ]]*\)[[ ]]*$/  {\\\"\1\\\", (void *) 0},/p' -e 's/^$symcode* \([[^ ]]*\) \([[^ ]]*\)$/  {\"\2\", (void *) \&\2},/p'"
+lt_cv_sys_global_symbol_to_c_name_address_lib_prefix="sed -n -e 's/^: \([[^ ]]*\)[[ ]]*$/  {\\\"\1\\\", (void *) 0},/p' -e 's/^$symcode* \([[^ ]]*\) \(lib[[^ ]]*\)$/  {\"\2\", (void *) \&\2},/p' -e 's/^$symcode* \([[^ ]]*\) \([[^ ]]*\)$/  {\"lib\2\", (void *) \&\2},/p'"
+
+# Handle CRLF in mingw tool chain
+opt_cr=
+case $build_os in
+mingw*)
+  opt_cr=`$ECHO 'x\{0,1\}' | tr x '\015'` # option cr in regexp
+  ;;
+esac
+
+# Try without a prefix underscore, then with it.
+for ac_symprfx in "" "_"; do
+
+  # Transform symcode, sympat, and symprfx into a raw symbol and a C symbol.
+  symxfrm="\\1 $ac_symprfx\\2 \\2"
+
+  # Write the raw and C identifiers.
+  if test "$lt_cv_nm_interface" = "MS dumpbin"; then
+    # Fake it for dumpbin and say T for any non-static function
+    # and D for any global variable.
+    # Also find C++ and __fastcall symbols from MSVC++,
+    # which start with @ or ?.
+    lt_cv_sys_global_symbol_pipe="$AWK ['"\
+"     {last_section=section; section=\$ 3};"\
+"     /^COFF SYMBOL TABLE/{for(i in hide) delete hide[i]};"\
+"     /Section length .*#relocs.*(pick any)/{hide[last_section]=1};"\
+"     \$ 0!~/External *\|/{next};"\
+"     / 0+ UNDEF /{next}; / UNDEF \([^|]\)*()/{next};"\
+"     {if(hide[section]) next};"\
+"     {f=0}; \$ 0~/\(\).*\|/{f=1}; {printf f ? \"T \" : \"D \"};"\
+"     {split(\$ 0, a, /\||\r/); split(a[2], s)};"\
+"     s[1]~/^[@?]/{print s[1], s[1]; next};"\
+"     s[1]~prfx {split(s[1],t,\"@\"); print t[1], substr(t[1],length(prfx))}"\
+"     ' prfx=^$ac_symprfx]"
+  else
+    lt_cv_sys_global_symbol_pipe="sed -n -e 's/^.*[[	 ]]\($symcode$symcode*\)[[	 ]][[	 ]]*$ac_symprfx$sympat$opt_cr$/$symxfrm/p'"
+  fi
+  lt_cv_sys_global_symbol_pipe="$lt_cv_sys_global_symbol_pipe | sed '/ __gnu_lto/d'"
+
+  # Check to see that the pipe works correctly.
+  pipe_works=no
+
+  rm -f conftest*
+  cat > conftest.$ac_ext <<_LT_EOF
+#ifdef __cplusplus
+extern "C" {
+#endif
+char nm_test_var;
+void nm_test_func(void);
+void nm_test_func(void){}
+#ifdef __cplusplus
+}
+#endif
+int main(){nm_test_var='a';nm_test_func();return(0);}
+_LT_EOF
+
+  if AC_TRY_EVAL(ac_compile); then
+    # Now try to grab the symbols.
+    nlist=conftest.nm
+    if AC_TRY_EVAL(NM conftest.$ac_objext \| "$lt_cv_sys_global_symbol_pipe" \> $nlist) && test -s "$nlist"; then
+      # Try sorting and uniquifying the output.
+      if sort "$nlist" | uniq > "$nlist"T; then
+	mv -f "$nlist"T "$nlist"
+      else
+	rm -f "$nlist"T
+      fi
+
+      # Make sure that we snagged all the symbols we need.
+      if $GREP ' nm_test_var$' "$nlist" >/dev/null; then
+	if $GREP ' nm_test_func$' "$nlist" >/dev/null; then
+	  cat <<_LT_EOF > conftest.$ac_ext
+/* Keep this code in sync between libtool.m4, ltmain, lt_system.h, and tests.  */
+#if defined(_WIN32) || defined(__CYGWIN__) || defined(_WIN32_WCE)
+/* DATA imports from DLLs on WIN32 con't be const, because runtime
+   relocations are performed -- see ld's documentation on pseudo-relocs.  */
+# define LT@&t@_DLSYM_CONST
+#elif defined(__osf__)
+/* This system does not cope well with relocations in const data.  */
+# define LT@&t@_DLSYM_CONST
+#else
+# define LT@&t@_DLSYM_CONST const
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+_LT_EOF
+	  # Now generate the symbol file.
+	  eval "$lt_cv_sys_global_symbol_to_cdecl"' < "$nlist" | $GREP -v main >> conftest.$ac_ext'
+
+	  cat <<_LT_EOF >> conftest.$ac_ext
+
+/* The mapping between symbol names and symbols.  */
+LT@&t@_DLSYM_CONST struct {
+  const char *name;
+  void       *address;
+}
+lt__PROGRAM__LTX_preloaded_symbols[[]] =
+{
+  { "@PROGRAM@", (void *) 0 },
+_LT_EOF
+	  $SED "s/^$symcode$symcode* \(.*\) \(.*\)$/  {\"\2\", (void *) \&\2},/" < "$nlist" | $GREP -v main >> conftest.$ac_ext
+	  cat <<\_LT_EOF >> conftest.$ac_ext
+  {0, (void *) 0}
+};
+
+/* This works around a problem in FreeBSD linker */
+#ifdef FREEBSD_WORKAROUND
+static const void *lt_preloaded_setup() {
+  return lt__PROGRAM__LTX_preloaded_symbols;
+}
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+_LT_EOF
+	  # Now try linking the two files.
+	  mv conftest.$ac_objext conftstm.$ac_objext
+	  lt_globsym_save_LIBS=$LIBS
+	  lt_globsym_save_CFLAGS=$CFLAGS
+	  LIBS="conftstm.$ac_objext"
+	  CFLAGS="$CFLAGS$_LT_TAGVAR(lt_prog_compiler_no_builtin_flag, $1)"
+	  if AC_TRY_EVAL(ac_link) && test -s conftest${ac_exeext}; then
+	    pipe_works=yes
+	  fi
+	  LIBS=$lt_globsym_save_LIBS
+	  CFLAGS=$lt_globsym_save_CFLAGS
+	else
+	  echo "cannot find nm_test_func in $nlist" >&AS_MESSAGE_LOG_FD
+	fi
+      else
+	echo "cannot find nm_test_var in $nlist" >&AS_MESSAGE_LOG_FD
+      fi
+    else
+      echo "cannot run $lt_cv_sys_global_symbol_pipe" >&AS_MESSAGE_LOG_FD
+    fi
+  else
+    echo "$progname: failed program was:" >&AS_MESSAGE_LOG_FD
+    cat conftest.$ac_ext >&5
+  fi
+  rm -rf conftest* conftst*
+
+  # Do not use the global_symbol_pipe unless it works.
+  if test "$pipe_works" = yes; then
+    break
+  else
+    lt_cv_sys_global_symbol_pipe=
+  fi
+done
+])
+if test -z "$lt_cv_sys_global_symbol_pipe"; then
+  lt_cv_sys_global_symbol_to_cdecl=
+fi
+if test -z "$lt_cv_sys_global_symbol_pipe$lt_cv_sys_global_symbol_to_cdecl"; then
+  AC_MSG_RESULT(failed)
+else
+  AC_MSG_RESULT(ok)
+fi
+
+# Response file support.
+if test "$lt_cv_nm_interface" = "MS dumpbin"; then
+  nm_file_list_spec='@'
+elif $NM --help 2>/dev/null | grep '[[@]]FILE' >/dev/null; then
+  nm_file_list_spec='@'
+fi
+
+_LT_DECL([global_symbol_pipe], [lt_cv_sys_global_symbol_pipe], [1],
+    [Take the output of nm and produce a listing of raw symbols and C names])
+_LT_DECL([global_symbol_to_cdecl], [lt_cv_sys_global_symbol_to_cdecl], [1],
+    [Transform the output of nm in a proper C declaration])
+_LT_DECL([global_symbol_to_c_name_address],
+    [lt_cv_sys_global_symbol_to_c_name_address], [1],
+    [Transform the output of nm in a C name address pair])
+_LT_DECL([global_symbol_to_c_name_address_lib_prefix],
+    [lt_cv_sys_global_symbol_to_c_name_address_lib_prefix], [1],
+    [Transform the output of nm in a C name address pair when lib prefix is needed])
+_LT_DECL([], [nm_file_list_spec], [1],
+    [Specify filename containing input files for $NM])
+]) # _LT_CMD_GLOBAL_SYMBOLS
+
+
+# _LT_COMPILER_PIC([TAGNAME])
+# ---------------------------
+m4_defun([_LT_COMPILER_PIC],
+[m4_require([_LT_TAG_COMPILER])dnl
+_LT_TAGVAR(lt_prog_compiler_wl, $1)=
+_LT_TAGVAR(lt_prog_compiler_pic, $1)=
+_LT_TAGVAR(lt_prog_compiler_static, $1)=
+
+m4_if([$1], [CXX], [
+  # C++ specific cases for pic, static, wl, etc.
+  if test "$GXX" = yes; then
+    _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+    _LT_TAGVAR(lt_prog_compiler_static, $1)='-static'
+
+    case $host_os in
+    aix*)
+      # All AIX code is PIC.
+      if test "$host_cpu" = ia64; then
+	# AIX 5 now supports IA64 processor
+	_LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic'
+      fi
+      ;;
+
+    amigaos*)
+      case $host_cpu in
+      powerpc)
+            # see comment about AmigaOS4 .so support
+            _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC'
+        ;;
+      m68k)
+            # FIXME: we need at least 68020 code to build shared libraries, but
+            # adding the `-m68020' flag to GCC prevents building anything better,
+            # like `-m68040'.
+            _LT_TAGVAR(lt_prog_compiler_pic, $1)='-m68020 -resident32 -malways-restore-a4'
+        ;;
+      esac
+      ;;
+
+    beos* | irix5* | irix6* | nonstopux* | osf3* | osf4* | osf5*)
+      # PIC is the default for these OSes.
+      ;;
+    mingw* | cygwin* | os2* | pw32* | cegcc*)
+      # This hack is so that the source file can tell whether it is being
+      # built for inclusion in a dll (and should export symbols for example).
+      # Although the cygwin gcc ignores -fPIC, still need this for old-style
+      # (--disable-auto-import) libraries
+      m4_if([$1], [GCJ], [],
+	[_LT_TAGVAR(lt_prog_compiler_pic, $1)='-DDLL_EXPORT'])
+      ;;
+    darwin* | rhapsody*)
+      # PIC is the default on this platform
+      # Common symbols not allowed in MH_DYLIB files
+      _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fno-common'
+      ;;
+    *djgpp*)
+      # DJGPP does not support shared libraries at all
+      _LT_TAGVAR(lt_prog_compiler_pic, $1)=
+      ;;
+    haiku*)
+      # PIC is the default for Haiku.
+      # The "-static" flag exists, but is broken.
+      _LT_TAGVAR(lt_prog_compiler_static, $1)=
+      ;;
+    interix[[3-9]]*)
+      # Interix 3.x gcc -fpic/-fPIC options generate broken code.
+      # Instead, we relocate shared libraries at runtime.
+      ;;
+    sysv4*MP*)
+      if test -d /usr/nec; then
+	_LT_TAGVAR(lt_prog_compiler_pic, $1)=-Kconform_pic
+      fi
+      ;;
+    hpux*)
+      # PIC is the default for 64-bit PA HP-UX, but not for 32-bit
+      # PA HP-UX.  On IA64 HP-UX, PIC is the default but the pic flag
+      # sets the default TLS model and affects inlining.
+      case $host_cpu in
+      hppa*64*)
+	;;
+      *)
+	_LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC'
+	;;
+      esac
+      ;;
+    *qnx* | *nto*)
+      # QNX uses GNU C++, but need to define -shared option too, otherwise
+      # it will coredump.
+      _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC -shared'
+      ;;
+    *)
+      _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC'
+      ;;
+    esac
+  else
+    case $host_os in
+      aix[[4-9]]*)
+	# All AIX code is PIC.
+	if test "$host_cpu" = ia64; then
+	  # AIX 5 now supports IA64 processor
+	  _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic'
+	else
+	  _LT_TAGVAR(lt_prog_compiler_static, $1)='-bnso -bI:/lib/syscalls.exp'
+	fi
+	;;
+      chorus*)
+	case $cc_basename in
+	cxch68*)
+	  # Green Hills C++ Compiler
+	  # _LT_TAGVAR(lt_prog_compiler_static, $1)="--no_auto_instantiation -u __main -u __premain -u _abort -r $COOL_DIR/lib/libOrb.a $MVME_DIR/lib/CC/libC.a $MVME_DIR/lib/classix/libcx.s.a"
+	  ;;
+	esac
+	;;
+      mingw* | cygwin* | os2* | pw32* | cegcc*)
+	# This hack is so that the source file can tell whether it is being
+	# built for inclusion in a dll (and should export symbols for example).
+	m4_if([$1], [GCJ], [],
+	  [_LT_TAGVAR(lt_prog_compiler_pic, $1)='-DDLL_EXPORT'])
+	;;
+      dgux*)
+	case $cc_basename in
+	  ec++*)
+	    _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC'
+	    ;;
+	  ghcx*)
+	    # Green Hills C++ Compiler
+	    _LT_TAGVAR(lt_prog_compiler_pic, $1)='-pic'
+	    ;;
+	  *)
+	    ;;
+	esac
+	;;
+      freebsd* | dragonfly*)
+	# FreeBSD uses GNU C++
+	;;
+      hpux9* | hpux10* | hpux11*)
+	case $cc_basename in
+	  CC*)
+	    _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+	    _LT_TAGVAR(lt_prog_compiler_static, $1)='${wl}-a ${wl}archive'
+	    if test "$host_cpu" != ia64; then
+	      _LT_TAGVAR(lt_prog_compiler_pic, $1)='+Z'
+	    fi
+	    ;;
+	  aCC*)
+	    _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+	    _LT_TAGVAR(lt_prog_compiler_static, $1)='${wl}-a ${wl}archive'
+	    case $host_cpu in
+	    hppa*64*|ia64*)
+	      # +Z the default
+	      ;;
+	    *)
+	      _LT_TAGVAR(lt_prog_compiler_pic, $1)='+Z'
+	      ;;
+	    esac
+	    ;;
+	  *)
+	    ;;
+	esac
+	;;
+      interix*)
+	# This is c89, which is MS Visual C++ (no shared libs)
+	# Anyone wants to do a port?
+	;;
+      irix5* | irix6* | nonstopux*)
+	case $cc_basename in
+	  CC*)
+	    _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+	    _LT_TAGVAR(lt_prog_compiler_static, $1)='-non_shared'
+	    # CC pic flag -KPIC is the default.
+	    ;;
+	  *)
+	    ;;
+	esac
+	;;
+      linux* | k*bsd*-gnu | kopensolaris*-gnu)
+	case $cc_basename in
+	  KCC*)
+	    # KAI C++ Compiler
+	    _LT_TAGVAR(lt_prog_compiler_wl, $1)='--backend -Wl,'
+	    _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC'
+	    ;;
+	  ecpc* )
+	    # old Intel C++ for x86_64 which still supported -KPIC.
+	    _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+	    _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC'
+	    _LT_TAGVAR(lt_prog_compiler_static, $1)='-static'
+	    ;;
+	  icpc* )
+	    # Intel C++, used to be incompatible with GCC.
+	    # ICC 10 doesn't accept -KPIC any more.
+	    _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+	    _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC'
+	    _LT_TAGVAR(lt_prog_compiler_static, $1)='-static'
+	    ;;
+	  pgCC* | pgcpp*)
+	    # Portland Group C++ compiler
+	    _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+	    _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fpic'
+	    _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic'
+	    ;;
+	  cxx*)
+	    # Compaq C++
+	    # Make sure the PIC flag is empty.  It appears that all Alpha
+	    # Linux and Compaq Tru64 Unix objects are PIC.
+	    _LT_TAGVAR(lt_prog_compiler_pic, $1)=
+	    _LT_TAGVAR(lt_prog_compiler_static, $1)='-non_shared'
+	    ;;
+	  xlc* | xlC* | bgxl[[cC]]* | mpixl[[cC]]*)
+	    # IBM XL 8.0, 9.0 on PPC and BlueGene
+	    _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+	    _LT_TAGVAR(lt_prog_compiler_pic, $1)='-qpic'
+	    _LT_TAGVAR(lt_prog_compiler_static, $1)='-qstaticlink'
+	    ;;
+	  *)
+	    case `$CC -V 2>&1 | sed 5q` in
+	    *Sun\ C*)
+	      # Sun C++ 5.9
+	      _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC'
+	      _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic'
+	      _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Qoption ld '
+	      ;;
+	    esac
+	    ;;
+	esac
+	;;
+      lynxos*)
+	;;
+      m88k*)
+	;;
+      mvs*)
+	case $cc_basename in
+	  cxx*)
+	    _LT_TAGVAR(lt_prog_compiler_pic, $1)='-W c,exportall'
+	    ;;
+	  *)
+	    ;;
+	esac
+	;;
+      netbsd*)
+	;;
+      *qnx* | *nto*)
+        # QNX uses GNU C++, but need to define -shared option too, otherwise
+        # it will coredump.
+        _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC -shared'
+        ;;
+      osf3* | osf4* | osf5*)
+	case $cc_basename in
+	  KCC*)
+	    _LT_TAGVAR(lt_prog_compiler_wl, $1)='--backend -Wl,'
+	    ;;
+	  RCC*)
+	    # Rational C++ 2.4.1
+	    _LT_TAGVAR(lt_prog_compiler_pic, $1)='-pic'
+	    ;;
+	  cxx*)
+	    # Digital/Compaq C++
+	    _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+	    # Make sure the PIC flag is empty.  It appears that all Alpha
+	    # Linux and Compaq Tru64 Unix objects are PIC.
+	    _LT_TAGVAR(lt_prog_compiler_pic, $1)=
+	    _LT_TAGVAR(lt_prog_compiler_static, $1)='-non_shared'
+	    ;;
+	  *)
+	    ;;
+	esac
+	;;
+      psos*)
+	;;
+      solaris*)
+	case $cc_basename in
+	  CC* | sunCC*)
+	    # Sun C++ 4.2, 5.x and Centerline C++
+	    _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC'
+	    _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic'
+	    _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Qoption ld '
+	    ;;
+	  gcx*)
+	    # Green Hills C++ Compiler
+	    _LT_TAGVAR(lt_prog_compiler_pic, $1)='-PIC'
+	    ;;
+	  *)
+	    ;;
+	esac
+	;;
+      sunos4*)
+	case $cc_basename in
+	  CC*)
+	    # Sun C++ 4.x
+	    _LT_TAGVAR(lt_prog_compiler_pic, $1)='-pic'
+	    _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic'
+	    ;;
+	  lcc*)
+	    # Lucid
+	    _LT_TAGVAR(lt_prog_compiler_pic, $1)='-pic'
+	    ;;
+	  *)
+	    ;;
+	esac
+	;;
+      sysv5* | unixware* | sco3.2v5* | sco5v6* | OpenUNIX*)
+	case $cc_basename in
+	  CC*)
+	    _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+	    _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC'
+	    _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic'
+	    ;;
+	esac
+	;;
+      tandem*)
+	case $cc_basename in
+	  NCC*)
+	    # NonStop-UX NCC 3.20
+	    _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC'
+	    ;;
+	  *)
+	    ;;
+	esac
+	;;
+      vxworks*)
+	;;
+      *)
+	_LT_TAGVAR(lt_prog_compiler_can_build_shared, $1)=no
+	;;
+    esac
+  fi
+],
+[
+  if test "$GCC" = yes; then
+    _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+    _LT_TAGVAR(lt_prog_compiler_static, $1)='-static'
+
+    case $host_os in
+      aix*)
+      # All AIX code is PIC.
+      if test "$host_cpu" = ia64; then
+	# AIX 5 now supports IA64 processor
+	_LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic'
+      fi
+      ;;
+
+    amigaos*)
+      case $host_cpu in
+      powerpc)
+            # see comment about AmigaOS4 .so support
+            _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC'
+        ;;
+      m68k)
+            # FIXME: we need at least 68020 code to build shared libraries, but
+            # adding the `-m68020' flag to GCC prevents building anything better,
+            # like `-m68040'.
+            _LT_TAGVAR(lt_prog_compiler_pic, $1)='-m68020 -resident32 -malways-restore-a4'
+        ;;
+      esac
+      ;;
+
+    beos* | irix5* | irix6* | nonstopux* | osf3* | osf4* | osf5*)
+      # PIC is the default for these OSes.
+      ;;
+
+    mingw* | cygwin* | pw32* | os2* | cegcc*)
+      # This hack is so that the source file can tell whether it is being
+      # built for inclusion in a dll (and should export symbols for example).
+      # Although the cygwin gcc ignores -fPIC, still need this for old-style
+      # (--disable-auto-import) libraries
+      m4_if([$1], [GCJ], [],
+	[_LT_TAGVAR(lt_prog_compiler_pic, $1)='-DDLL_EXPORT'])
+      ;;
+
+    darwin* | rhapsody*)
+      # PIC is the default on this platform
+      # Common symbols not allowed in MH_DYLIB files
+      _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fno-common'
+      ;;
+
+    haiku*)
+      # PIC is the default for Haiku.
+      # The "-static" flag exists, but is broken.
+      _LT_TAGVAR(lt_prog_compiler_static, $1)=
+      ;;
+
+    hpux*)
+      # PIC is the default for 64-bit PA HP-UX, but not for 32-bit
+      # PA HP-UX.  On IA64 HP-UX, PIC is the default but the pic flag
+      # sets the default TLS model and affects inlining.
+      case $host_cpu in
+      hppa*64*)
+	# +Z the default
+	;;
+      *)
+	_LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC'
+	;;
+      esac
+      ;;
+
+    interix[[3-9]]*)
+      # Interix 3.x gcc -fpic/-fPIC options generate broken code.
+      # Instead, we relocate shared libraries at runtime.
+      ;;
+
+    msdosdjgpp*)
+      # Just because we use GCC doesn't mean we suddenly get shared libraries
+      # on systems that don't support them.
+      _LT_TAGVAR(lt_prog_compiler_can_build_shared, $1)=no
+      enable_shared=no
+      ;;
+
+    *nto* | *qnx*)
+      # QNX uses GNU C++, but need to define -shared option too, otherwise
+      # it will coredump.
+      _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC -shared'
+      ;;
+
+    sysv4*MP*)
+      if test -d /usr/nec; then
+	_LT_TAGVAR(lt_prog_compiler_pic, $1)=-Kconform_pic
+      fi
+      ;;
+
+    *)
+      _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC'
+      ;;
+    esac
+
+    case $cc_basename in
+    nvcc*) # Cuda Compiler Driver 2.2
+      _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Xlinker '
+      if test -n "$_LT_TAGVAR(lt_prog_compiler_pic, $1)"; then
+        _LT_TAGVAR(lt_prog_compiler_pic, $1)="-Xcompiler $_LT_TAGVAR(lt_prog_compiler_pic, $1)"
+      fi
+      ;;
+    esac
+  else
+    # PORTME Check for flag to pass linker flags through the system compiler.
+    case $host_os in
+    aix*)
+      _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+      if test "$host_cpu" = ia64; then
+	# AIX 5 now supports IA64 processor
+	_LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic'
+      else
+	_LT_TAGVAR(lt_prog_compiler_static, $1)='-bnso -bI:/lib/syscalls.exp'
+      fi
+      ;;
+
+    mingw* | cygwin* | pw32* | os2* | cegcc*)
+      # This hack is so that the source file can tell whether it is being
+      # built for inclusion in a dll (and should export symbols for example).
+      m4_if([$1], [GCJ], [],
+	[_LT_TAGVAR(lt_prog_compiler_pic, $1)='-DDLL_EXPORT'])
+      ;;
+
+    hpux9* | hpux10* | hpux11*)
+      _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+      # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but
+      # not for PA HP-UX.
+      case $host_cpu in
+      hppa*64*|ia64*)
+	# +Z the default
+	;;
+      *)
+	_LT_TAGVAR(lt_prog_compiler_pic, $1)='+Z'
+	;;
+      esac
+      # Is there a better lt_prog_compiler_static that works with the bundled CC?
+      _LT_TAGVAR(lt_prog_compiler_static, $1)='${wl}-a ${wl}archive'
+      ;;
+
+    irix5* | irix6* | nonstopux*)
+      _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+      # PIC (with -KPIC) is the default.
+      _LT_TAGVAR(lt_prog_compiler_static, $1)='-non_shared'
+      ;;
+
+    linux* | k*bsd*-gnu | kopensolaris*-gnu)
+      case $cc_basename in
+      # old Intel for x86_64 which still supported -KPIC.
+      ecc*)
+	_LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+	_LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC'
+	_LT_TAGVAR(lt_prog_compiler_static, $1)='-static'
+        ;;
+      # icc used to be incompatible with GCC.
+      # ICC 10 doesn't accept -KPIC any more.
+      icc* | ifort*)
+	_LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+	_LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC'
+	_LT_TAGVAR(lt_prog_compiler_static, $1)='-static'
+        ;;
+      # Lahey Fortran 8.1.
+      lf95*)
+	_LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+	_LT_TAGVAR(lt_prog_compiler_pic, $1)='--shared'
+	_LT_TAGVAR(lt_prog_compiler_static, $1)='--static'
+	;;
+      nagfor*)
+	# NAG Fortran compiler
+	_LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,-Wl,,'
+	_LT_TAGVAR(lt_prog_compiler_pic, $1)='-PIC'
+	_LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic'
+	;;
+      pgcc* | pgf77* | pgf90* | pgf95* | pgfortran*)
+        # Portland Group compilers (*not* the Pentium gcc compiler,
+	# which looks to be a dead project)
+	_LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+	_LT_TAGVAR(lt_prog_compiler_pic, $1)='-fpic'
+	_LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic'
+        ;;
+      ccc*)
+        _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+        # All Alpha code is PIC.
+        _LT_TAGVAR(lt_prog_compiler_static, $1)='-non_shared'
+        ;;
+      xl* | bgxl* | bgf* | mpixl*)
+	# IBM XL C 8.0/Fortran 10.1, 11.1 on PPC and BlueGene
+	_LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+	_LT_TAGVAR(lt_prog_compiler_pic, $1)='-qpic'
+	_LT_TAGVAR(lt_prog_compiler_static, $1)='-qstaticlink'
+	;;
+      *)
+	case `$CC -V 2>&1 | sed 5q` in
+	*Sun\ Ceres\ Fortran* | *Sun*Fortran*\ [[1-7]].* | *Sun*Fortran*\ 8.[[0-3]]*)
+	  # Sun Fortran 8.3 passes all unrecognized flags to the linker
+	  _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC'
+	  _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic'
+	  _LT_TAGVAR(lt_prog_compiler_wl, $1)=''
+	  ;;
+	*Sun\ F* | *Sun*Fortran*)
+	  _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC'
+	  _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic'
+	  _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Qoption ld '
+	  ;;
+	*Sun\ C*)
+	  # Sun C 5.9
+	  _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC'
+	  _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic'
+	  _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+	  ;;
+        *Intel*\ [[CF]]*Compiler*)
+	  _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+	  _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC'
+	  _LT_TAGVAR(lt_prog_compiler_static, $1)='-static'
+	  ;;
+	*Portland\ Group*)
+	  _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+	  _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fpic'
+	  _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic'
+	  ;;
+	esac
+	;;
+      esac
+      ;;
+
+    newsos6)
+      _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC'
+      _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic'
+      ;;
+
+    *nto* | *qnx*)
+      # QNX uses GNU C++, but need to define -shared option too, otherwise
+      # it will coredump.
+      _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC -shared'
+      ;;
+
+    osf3* | osf4* | osf5*)
+      _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+      # All OSF/1 code is PIC.
+      _LT_TAGVAR(lt_prog_compiler_static, $1)='-non_shared'
+      ;;
+
+    rdos*)
+      _LT_TAGVAR(lt_prog_compiler_static, $1)='-non_shared'
+      ;;
+
+    solaris*)
+      _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC'
+      _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic'
+      case $cc_basename in
+      f77* | f90* | f95* | sunf77* | sunf90* | sunf95*)
+	_LT_TAGVAR(lt_prog_compiler_wl, $1)='-Qoption ld ';;
+      *)
+	_LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,';;
+      esac
+      ;;
+
+    sunos4*)
+      _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Qoption ld '
+      _LT_TAGVAR(lt_prog_compiler_pic, $1)='-PIC'
+      _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic'
+      ;;
+
+    sysv4 | sysv4.2uw2* | sysv4.3*)
+      _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+      _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC'
+      _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic'
+      ;;
+
+    sysv4*MP*)
+      if test -d /usr/nec ;then
+	_LT_TAGVAR(lt_prog_compiler_pic, $1)='-Kconform_pic'
+	_LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic'
+      fi
+      ;;
+
+    sysv5* | unixware* | sco3.2v5* | sco5v6* | OpenUNIX*)
+      _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+      _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC'
+      _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic'
+      ;;
+
+    unicos*)
+      _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,'
+      _LT_TAGVAR(lt_prog_compiler_can_build_shared, $1)=no
+      ;;
+
+    uts4*)
+      _LT_TAGVAR(lt_prog_compiler_pic, $1)='-pic'
+      _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic'
+      ;;
+
+    *)
+      _LT_TAGVAR(lt_prog_compiler_can_build_shared, $1)=no
+      ;;
+    esac
+  fi
+])
+case $host_os in
+  # For platforms which do not support PIC, -DPIC is meaningless:
+  *djgpp*)
+    _LT_TAGVAR(lt_prog_compiler_pic, $1)=
+    ;;
+  *)
+    _LT_TAGVAR(lt_prog_compiler_pic, $1)="$_LT_TAGVAR(lt_prog_compiler_pic, $1)@&t@m4_if([$1],[],[ -DPIC],[m4_if([$1],[CXX],[ -DPIC],[])])"
+    ;;
+esac
+
+AC_CACHE_CHECK([for $compiler option to produce PIC],
+  [_LT_TAGVAR(lt_cv_prog_compiler_pic, $1)],
+  [_LT_TAGVAR(lt_cv_prog_compiler_pic, $1)=$_LT_TAGVAR(lt_prog_compiler_pic, $1)])
+_LT_TAGVAR(lt_prog_compiler_pic, $1)=$_LT_TAGVAR(lt_cv_prog_compiler_pic, $1)
+
+#
+# Check to make sure the PIC flag actually works.
+#
+if test -n "$_LT_TAGVAR(lt_prog_compiler_pic, $1)"; then
+  _LT_COMPILER_OPTION([if $compiler PIC flag $_LT_TAGVAR(lt_prog_compiler_pic, $1) works],
+    [_LT_TAGVAR(lt_cv_prog_compiler_pic_works, $1)],
+    [$_LT_TAGVAR(lt_prog_compiler_pic, $1)@&t@m4_if([$1],[],[ -DPIC],[m4_if([$1],[CXX],[ -DPIC],[])])], [],
+    [case $_LT_TAGVAR(lt_prog_compiler_pic, $1) in
+     "" | " "*) ;;
+     *) _LT_TAGVAR(lt_prog_compiler_pic, $1)=" $_LT_TAGVAR(lt_prog_compiler_pic, $1)" ;;
+     esac],
+    [_LT_TAGVAR(lt_prog_compiler_pic, $1)=
+     _LT_TAGVAR(lt_prog_compiler_can_build_shared, $1)=no])
+fi
+_LT_TAGDECL([pic_flag], [lt_prog_compiler_pic], [1],
+	[Additional compiler flags for building library objects])
+
+_LT_TAGDECL([wl], [lt_prog_compiler_wl], [1],
+	[How to pass a linker flag through the compiler])
+#
+# Check to make sure the static flag actually works.
+#
+wl=$_LT_TAGVAR(lt_prog_compiler_wl, $1) eval lt_tmp_static_flag=\"$_LT_TAGVAR(lt_prog_compiler_static, $1)\"
+_LT_LINKER_OPTION([if $compiler static flag $lt_tmp_static_flag works],
+  _LT_TAGVAR(lt_cv_prog_compiler_static_works, $1),
+  $lt_tmp_static_flag,
+  [],
+  [_LT_TAGVAR(lt_prog_compiler_static, $1)=])
+_LT_TAGDECL([link_static_flag], [lt_prog_compiler_static], [1],
+	[Compiler flag to prevent dynamic linking])
+])# _LT_COMPILER_PIC
+
+
+# _LT_LINKER_SHLIBS([TAGNAME])
+# ----------------------------
+# See if the linker supports building shared libraries.
+m4_defun([_LT_LINKER_SHLIBS],
+[AC_REQUIRE([LT_PATH_LD])dnl
+AC_REQUIRE([LT_PATH_NM])dnl
+m4_require([_LT_PATH_MANIFEST_TOOL])dnl
+m4_require([_LT_FILEUTILS_DEFAULTS])dnl
+m4_require([_LT_DECL_EGREP])dnl
+m4_require([_LT_DECL_SED])dnl
+m4_require([_LT_CMD_GLOBAL_SYMBOLS])dnl
+m4_require([_LT_TAG_COMPILER])dnl
+AC_MSG_CHECKING([whether the $compiler linker ($LD) supports shared libraries])
+m4_if([$1], [CXX], [
+  _LT_TAGVAR(export_symbols_cmds, $1)='$NM $libobjs $convenience | $global_symbol_pipe | $SED '\''s/.* //'\'' | sort | uniq > $export_symbols'
+  _LT_TAGVAR(exclude_expsyms, $1)=['_GLOBAL_OFFSET_TABLE_|_GLOBAL__F[ID]_.*']
+  case $host_os in
+  aix[[4-9]]*)
+    # If we're using GNU nm, then we don't want the "-C" option.
+    # -C means demangle to AIX nm, but means don't demangle with GNU nm
+    # Also, AIX nm treats weak defined symbols like other global defined
+    # symbols, whereas GNU nm marks them as "W".
+    if $NM -V 2>&1 | $GREP 'GNU' > /dev/null; then
+      _LT_TAGVAR(export_symbols_cmds, $1)='$NM -Bpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B") || (\$ 2 == "W")) && ([substr](\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols'
+    else
+      _LT_TAGVAR(export_symbols_cmds, $1)='$NM -BCpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B")) && ([substr](\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols'
+    fi
+    ;;
+  pw32*)
+    _LT_TAGVAR(export_symbols_cmds, $1)="$ltdll_cmds"
+    ;;
+  cygwin* | mingw* | cegcc*)
+    case $cc_basename in
+    cl*)
+      _LT_TAGVAR(exclude_expsyms, $1)='_NULL_IMPORT_DESCRIPTOR|_IMPORT_DESCRIPTOR_.*'
+      ;;
+    *)
+      _LT_TAGVAR(export_symbols_cmds, $1)='$NM $libobjs $convenience | $global_symbol_pipe | $SED -e '\''/^[[BCDGRS]][[ ]]/s/.*[[ ]]\([[^ ]]*\)/\1 DATA/;s/^.*[[ ]]__nm__\([[^ ]]*\)[[ ]][[^ ]]*/\1 DATA/;/^I[[ ]]/d;/^[[AITW]][[ ]]/s/.* //'\'' | sort | uniq > $export_symbols'
+      _LT_TAGVAR(exclude_expsyms, $1)=['[_]+GLOBAL_OFFSET_TABLE_|[_]+GLOBAL__[FID]_.*|[_]+head_[A-Za-z0-9_]+_dll|[A-Za-z0-9_]+_dll_iname']
+      ;;
+    esac
+    ;;
+  *)
+    _LT_TAGVAR(export_symbols_cmds, $1)='$NM $libobjs $convenience | $global_symbol_pipe | $SED '\''s/.* //'\'' | sort | uniq > $export_symbols'
+    ;;
+  esac
+], [
+  runpath_var=
+  _LT_TAGVAR(allow_undefined_flag, $1)=
+  _LT_TAGVAR(always_export_symbols, $1)=no
+  _LT_TAGVAR(archive_cmds, $1)=
+  _LT_TAGVAR(archive_expsym_cmds, $1)=
+  _LT_TAGVAR(compiler_needs_object, $1)=no
+  _LT_TAGVAR(enable_shared_with_static_runtimes, $1)=no
+  _LT_TAGVAR(export_dynamic_flag_spec, $1)=
+  _LT_TAGVAR(export_symbols_cmds, $1)='$NM $libobjs $convenience | $global_symbol_pipe | $SED '\''s/.* //'\'' | sort | uniq > $export_symbols'
+  _LT_TAGVAR(hardcode_automatic, $1)=no
+  _LT_TAGVAR(hardcode_direct, $1)=no
+  _LT_TAGVAR(hardcode_direct_absolute, $1)=no
+  _LT_TAGVAR(hardcode_libdir_flag_spec, $1)=
+  _LT_TAGVAR(hardcode_libdir_separator, $1)=
+  _LT_TAGVAR(hardcode_minus_L, $1)=no
+  _LT_TAGVAR(hardcode_shlibpath_var, $1)=unsupported
+  _LT_TAGVAR(inherit_rpath, $1)=no
+  _LT_TAGVAR(link_all_deplibs, $1)=unknown
+  _LT_TAGVAR(module_cmds, $1)=
+  _LT_TAGVAR(module_expsym_cmds, $1)=
+  _LT_TAGVAR(old_archive_from_new_cmds, $1)=
+  _LT_TAGVAR(old_archive_from_expsyms_cmds, $1)=
+  _LT_TAGVAR(thread_safe_flag_spec, $1)=
+  _LT_TAGVAR(whole_archive_flag_spec, $1)=
+  # include_expsyms should be a list of space-separated symbols to be *always*
+  # included in the symbol list
+  _LT_TAGVAR(include_expsyms, $1)=
+  # exclude_expsyms can be an extended regexp of symbols to exclude
+  # it will be wrapped by ` (' and `)$', so one must not match beginning or
+  # end of line.  Example: `a|bc|.*d.*' will exclude the symbols `a' and `bc',
+  # as well as any symbol that contains `d'.
+  _LT_TAGVAR(exclude_expsyms, $1)=['_GLOBAL_OFFSET_TABLE_|_GLOBAL__F[ID]_.*']
+  # Although _GLOBAL_OFFSET_TABLE_ is a valid symbol C name, most a.out
+  # platforms (ab)use it in PIC code, but their linkers get confused if
+  # the symbol is explicitly referenced.  Since portable code cannot
+  # rely on this symbol name, it's probably fine to never include it in
+  # preloaded symbol tables.
+  # Exclude shared library initialization/finalization symbols.
+dnl Note also adjust exclude_expsyms for C++ above.
+  extract_expsyms_cmds=
+
+  case $host_os in
+  cygwin* | mingw* | pw32* | cegcc*)
+    # FIXME: the MSVC++ port hasn't been tested in a loooong time
+    # When not using gcc, we currently assume that we are using
+    # Microsoft Visual C++.
+    if test "$GCC" != yes; then
+      with_gnu_ld=no
+    fi
+    ;;
+  interix*)
+    # we just hope/assume this is gcc and not c89 (= MSVC++)
+    with_gnu_ld=yes
+    ;;
+  openbsd*)
+    with_gnu_ld=no
+    ;;
+  esac
+
+  _LT_TAGVAR(ld_shlibs, $1)=yes
+
+  # On some targets, GNU ld is compatible enough with the native linker
+  # that we're better off using the native interface for both.
+  lt_use_gnu_ld_interface=no
+  if test "$with_gnu_ld" = yes; then
+    case $host_os in
+      aix*)
+	# The AIX port of GNU ld has always aspired to compatibility
+	# with the native linker.  However, as the warning in the GNU ld
+	# block says, versions before 2.19.5* couldn't really create working
+	# shared libraries, regardless of the interface used.
+	case `$LD -v 2>&1` in
+	  *\ \(GNU\ Binutils\)\ 2.19.5*) ;;
+	  *\ \(GNU\ Binutils\)\ 2.[[2-9]]*) ;;
+	  *\ \(GNU\ Binutils\)\ [[3-9]]*) ;;
+	  *)
+	    lt_use_gnu_ld_interface=yes
+	    ;;
+	esac
+	;;
+      *)
+	lt_use_gnu_ld_interface=yes
+	;;
+    esac
+  fi
+
+  if test "$lt_use_gnu_ld_interface" = yes; then
+    # If archive_cmds runs LD, not CC, wlarc should be empty
+    wlarc='${wl}'
+
+    # Set some defaults for GNU ld with shared library support. These
+    # are reset later if shared libraries are not supported. Putting them
+    # here allows them to be overridden if necessary.
+    runpath_var=LD_RUN_PATH
+    _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath ${wl}$libdir'
+    _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}--export-dynamic'
+    # ancient GNU ld didn't support --whole-archive et. al.
+    if $LD --help 2>&1 | $GREP 'no-whole-archive' > /dev/null; then
+      _LT_TAGVAR(whole_archive_flag_spec, $1)="$wlarc"'--whole-archive$convenience '"$wlarc"'--no-whole-archive'
+    else
+      _LT_TAGVAR(whole_archive_flag_spec, $1)=
+    fi
+    supports_anon_versioning=no
+    case `$LD -v 2>&1` in
+      *GNU\ gold*) supports_anon_versioning=yes ;;
+      *\ [[01]].* | *\ 2.[[0-9]].* | *\ 2.10.*) ;; # catch versions < 2.11
+      *\ 2.11.93.0.2\ *) supports_anon_versioning=yes ;; # RH7.3 ...
+      *\ 2.11.92.0.12\ *) supports_anon_versioning=yes ;; # Mandrake 8.2 ...
+      *\ 2.11.*) ;; # other 2.11 versions
+      *) supports_anon_versioning=yes ;;
+    esac
+
+    # See if GNU ld supports shared libraries.
+    case $host_os in
+    aix[[3-9]]*)
+      # On AIX/PPC, the GNU linker is very broken
+      if test "$host_cpu" != ia64; then
+	_LT_TAGVAR(ld_shlibs, $1)=no
+	cat <<_LT_EOF 1>&2
+
+*** Warning: the GNU linker, at least up to release 2.19, is reported
+*** to be unable to reliably create shared libraries on AIX.
+*** Therefore, libtool is disabling shared libraries support.  If you
+*** really care for shared libraries, you may want to install binutils
+*** 2.20 or above, or modify your PATH so that a non-GNU linker is found.
+*** You will then need to restart the configuration process.
+
+_LT_EOF
+      fi
+      ;;
+
+    amigaos*)
+      case $host_cpu in
+      powerpc)
+            # see comment about AmigaOS4 .so support
+            _LT_TAGVAR(archive_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+            _LT_TAGVAR(archive_expsym_cmds, $1)=''
+        ;;
+      m68k)
+            _LT_TAGVAR(archive_cmds, $1)='$RM $output_objdir/a2ixlibrary.data~$ECHO "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$ECHO "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$ECHO "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$ECHO "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)'
+            _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir'
+            _LT_TAGVAR(hardcode_minus_L, $1)=yes
+        ;;
+      esac
+      ;;
+
+    beos*)
+      if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then
+	_LT_TAGVAR(allow_undefined_flag, $1)=unsupported
+	# Joseph Beckenbach  says some releases of gcc
+	# support --undefined.  This deserves some investigation.  FIXME
+	_LT_TAGVAR(archive_cmds, $1)='$CC -nostart $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+      else
+	_LT_TAGVAR(ld_shlibs, $1)=no
+      fi
+      ;;
+
+    cygwin* | mingw* | pw32* | cegcc*)
+      # _LT_TAGVAR(hardcode_libdir_flag_spec, $1) is actually meaningless,
+      # as there is no search path for DLLs.
+      _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir'
+      _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}--export-all-symbols'
+      _LT_TAGVAR(allow_undefined_flag, $1)=unsupported
+      _LT_TAGVAR(always_export_symbols, $1)=no
+      _LT_TAGVAR(enable_shared_with_static_runtimes, $1)=yes
+      _LT_TAGVAR(export_symbols_cmds, $1)='$NM $libobjs $convenience | $global_symbol_pipe | $SED -e '\''/^[[BCDGRS]][[ ]]/s/.*[[ ]]\([[^ ]]*\)/\1 DATA/;s/^.*[[ ]]__nm__\([[^ ]]*\)[[ ]][[^ ]]*/\1 DATA/;/^I[[ ]]/d;/^[[AITW]][[ ]]/s/.* //'\'' | sort | uniq > $export_symbols'
+      _LT_TAGVAR(exclude_expsyms, $1)=['[_]+GLOBAL_OFFSET_TABLE_|[_]+GLOBAL__[FID]_.*|[_]+head_[A-Za-z0-9_]+_dll|[A-Za-z0-9_]+_dll_iname']
+
+      if $LD --help 2>&1 | $GREP 'auto-import' > /dev/null; then
+        _LT_TAGVAR(archive_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib'
+	# If the export-symbols file already is a .def file (1st line
+	# is EXPORTS), use it as is; otherwise, prepend...
+	_LT_TAGVAR(archive_expsym_cmds, $1)='if test "x`$SED 1q $export_symbols`" = xEXPORTS; then
+	  cp $export_symbols $output_objdir/$soname.def;
+	else
+	  echo EXPORTS > $output_objdir/$soname.def;
+	  cat $export_symbols >> $output_objdir/$soname.def;
+	fi~
+	$CC -shared $output_objdir/$soname.def $libobjs $deplibs $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib'
+      else
+	_LT_TAGVAR(ld_shlibs, $1)=no
+      fi
+      ;;
+
+    haiku*)
+      _LT_TAGVAR(archive_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+      _LT_TAGVAR(link_all_deplibs, $1)=yes
+      ;;
+
+    interix[[3-9]]*)
+      _LT_TAGVAR(hardcode_direct, $1)=no
+      _LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+      _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath,$libdir'
+      _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-E'
+      # Hack: On Interix 3.x, we cannot compile PIC because of a broken gcc.
+      # Instead, shared libraries are loaded at an image base (0x10000000 by
+      # default) and relocated if they conflict, which is a slow very memory
+      # consuming and fragmenting process.  To avoid this, we pick a random,
+      # 256 KiB-aligned image base between 0x50000000 and 0x6FFC0000 at link
+      # time.  Moving up from 0x10000000 also allows more sbrk(2) space.
+      _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib'
+      _LT_TAGVAR(archive_expsym_cmds, $1)='sed "s,^,_," $export_symbols >$output_objdir/$soname.expsym~$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--retain-symbols-file,$output_objdir/$soname.expsym ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib'
+      ;;
+
+    gnu* | linux* | tpf* | k*bsd*-gnu | kopensolaris*-gnu)
+      tmp_diet=no
+      if test "$host_os" = linux-dietlibc; then
+	case $cc_basename in
+	  diet\ *) tmp_diet=yes;;	# linux-dietlibc with static linking (!diet-dyn)
+	esac
+      fi
+      if $LD --help 2>&1 | $EGREP ': supported targets:.* elf' > /dev/null \
+	 && test "$tmp_diet" = no
+      then
+	tmp_addflag=' $pic_flag'
+	tmp_sharedflag='-shared'
+	case $cc_basename,$host_cpu in
+        pgcc*)				# Portland Group C compiler
+	  _LT_TAGVAR(whole_archive_flag_spec, $1)='${wl}--whole-archive`for conv in $convenience\"\"; do test  -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive'
+	  tmp_addflag=' $pic_flag'
+	  ;;
+	pgf77* | pgf90* | pgf95* | pgfortran*)
+					# Portland Group f77 and f90 compilers
+	  _LT_TAGVAR(whole_archive_flag_spec, $1)='${wl}--whole-archive`for conv in $convenience\"\"; do test  -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive'
+	  tmp_addflag=' $pic_flag -Mnomain' ;;
+	ecc*,ia64* | icc*,ia64*)	# Intel C compiler on ia64
+	  tmp_addflag=' -i_dynamic' ;;
+	efc*,ia64* | ifort*,ia64*)	# Intel Fortran compiler on ia64
+	  tmp_addflag=' -i_dynamic -nofor_main' ;;
+	ifc* | ifort*)			# Intel Fortran compiler
+	  tmp_addflag=' -nofor_main' ;;
+	lf95*)				# Lahey Fortran 8.1
+	  _LT_TAGVAR(whole_archive_flag_spec, $1)=
+	  tmp_sharedflag='--shared' ;;
+	xl[[cC]]* | bgxl[[cC]]* | mpixl[[cC]]*) # IBM XL C 8.0 on PPC (deal with xlf below)
+	  tmp_sharedflag='-qmkshrobj'
+	  tmp_addflag= ;;
+	nvcc*)	# Cuda Compiler Driver 2.2
+	  _LT_TAGVAR(whole_archive_flag_spec, $1)='${wl}--whole-archive`for conv in $convenience\"\"; do test  -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive'
+	  _LT_TAGVAR(compiler_needs_object, $1)=yes
+	  ;;
+	esac
+	case `$CC -V 2>&1 | sed 5q` in
+	*Sun\ C*)			# Sun C 5.9
+	  _LT_TAGVAR(whole_archive_flag_spec, $1)='${wl}--whole-archive`new_convenience=; for conv in $convenience\"\"; do test -z \"$conv\" || new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive'
+	  _LT_TAGVAR(compiler_needs_object, $1)=yes
+	  tmp_sharedflag='-G' ;;
+	*Sun\ F*)			# Sun Fortran 8.3
+	  tmp_sharedflag='-G' ;;
+	esac
+	_LT_TAGVAR(archive_cmds, $1)='$CC '"$tmp_sharedflag""$tmp_addflag"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+
+        if test "x$supports_anon_versioning" = xyes; then
+          _LT_TAGVAR(archive_expsym_cmds, $1)='echo "{ global:" > $output_objdir/$libname.ver~
+	    cat $export_symbols | sed -e "s/\(.*\)/\1;/" >> $output_objdir/$libname.ver~
+	    echo "local: *; };" >> $output_objdir/$libname.ver~
+	    $CC '"$tmp_sharedflag""$tmp_addflag"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-version-script ${wl}$output_objdir/$libname.ver -o $lib'
+        fi
+
+	case $cc_basename in
+	xlf* | bgf* | bgxlf* | mpixlf*)
+	  # IBM XL Fortran 10.1 on PPC cannot create shared libs itself
+	  _LT_TAGVAR(whole_archive_flag_spec, $1)='--whole-archive$convenience --no-whole-archive'
+	  _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath ${wl}$libdir'
+	  _LT_TAGVAR(archive_cmds, $1)='$LD -shared $libobjs $deplibs $linker_flags -soname $soname -o $lib'
+	  if test "x$supports_anon_versioning" = xyes; then
+	    _LT_TAGVAR(archive_expsym_cmds, $1)='echo "{ global:" > $output_objdir/$libname.ver~
+	      cat $export_symbols | sed -e "s/\(.*\)/\1;/" >> $output_objdir/$libname.ver~
+	      echo "local: *; };" >> $output_objdir/$libname.ver~
+	      $LD -shared $libobjs $deplibs $linker_flags -soname $soname -version-script $output_objdir/$libname.ver -o $lib'
+	  fi
+	  ;;
+	esac
+      else
+        _LT_TAGVAR(ld_shlibs, $1)=no
+      fi
+      ;;
+
+    netbsd*)
+      if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then
+	_LT_TAGVAR(archive_cmds, $1)='$LD -Bshareable $libobjs $deplibs $linker_flags -o $lib'
+	wlarc=
+      else
+	_LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+	_LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib'
+      fi
+      ;;
+
+    solaris*)
+      if $LD -v 2>&1 | $GREP 'BFD 2\.8' > /dev/null; then
+	_LT_TAGVAR(ld_shlibs, $1)=no
+	cat <<_LT_EOF 1>&2
+
+*** Warning: The releases 2.8.* of the GNU linker cannot reliably
+*** create shared libraries on Solaris systems.  Therefore, libtool
+*** is disabling shared libraries support.  We urge you to upgrade GNU
+*** binutils to release 2.9.1 or newer.  Another option is to modify
+*** your PATH or compiler configuration so that the native linker is
+*** used, and then restart.
+
+_LT_EOF
+      elif $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then
+	_LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+	_LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib'
+      else
+	_LT_TAGVAR(ld_shlibs, $1)=no
+      fi
+      ;;
+
+    sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX*)
+      case `$LD -v 2>&1` in
+        *\ [[01]].* | *\ 2.[[0-9]].* | *\ 2.1[[0-5]].*)
+	_LT_TAGVAR(ld_shlibs, $1)=no
+	cat <<_LT_EOF 1>&2
+
+*** Warning: Releases of the GNU linker prior to 2.16.91.0.3 can not
+*** reliably create shared libraries on SCO systems.  Therefore, libtool
+*** is disabling shared libraries support.  We urge you to upgrade GNU
+*** binutils to release 2.16.91.0.3 or newer.  Another option is to modify
+*** your PATH or compiler configuration so that the native linker is
+*** used, and then restart.
+
+_LT_EOF
+	;;
+	*)
+	  # For security reasons, it is highly recommended that you always
+	  # use absolute paths for naming shared libraries, and exclude the
+	  # DT_RUNPATH tag from executables and libraries.  But doing so
+	  # requires that you compile everything twice, which is a pain.
+	  if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then
+	    _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath ${wl}$libdir'
+	    _LT_TAGVAR(archive_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+	    _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib'
+	  else
+	    _LT_TAGVAR(ld_shlibs, $1)=no
+	  fi
+	;;
+      esac
+      ;;
+
+    sunos4*)
+      _LT_TAGVAR(archive_cmds, $1)='$LD -assert pure-text -Bshareable -o $lib $libobjs $deplibs $linker_flags'
+      wlarc=
+      _LT_TAGVAR(hardcode_direct, $1)=yes
+      _LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+      ;;
+
+    *)
+      if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then
+	_LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+	_LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib'
+      else
+	_LT_TAGVAR(ld_shlibs, $1)=no
+      fi
+      ;;
+    esac
+
+    if test "$_LT_TAGVAR(ld_shlibs, $1)" = no; then
+      runpath_var=
+      _LT_TAGVAR(hardcode_libdir_flag_spec, $1)=
+      _LT_TAGVAR(export_dynamic_flag_spec, $1)=
+      _LT_TAGVAR(whole_archive_flag_spec, $1)=
+    fi
+  else
+    # PORTME fill in a description of your system's linker (not GNU ld)
+    case $host_os in
+    aix3*)
+      _LT_TAGVAR(allow_undefined_flag, $1)=unsupported
+      _LT_TAGVAR(always_export_symbols, $1)=yes
+      _LT_TAGVAR(archive_expsym_cmds, $1)='$LD -o $output_objdir/$soname $libobjs $deplibs $linker_flags -bE:$export_symbols -T512 -H512 -bM:SRE~$AR $AR_FLAGS $lib $output_objdir/$soname'
+      # Note: this linker hardcodes the directories in LIBPATH if there
+      # are no directories specified by -L.
+      _LT_TAGVAR(hardcode_minus_L, $1)=yes
+      if test "$GCC" = yes && test -z "$lt_prog_compiler_static"; then
+	# Neither direct hardcoding nor static linking is supported with a
+	# broken collect2.
+	_LT_TAGVAR(hardcode_direct, $1)=unsupported
+      fi
+      ;;
+
+    aix[[4-9]]*)
+      if test "$host_cpu" = ia64; then
+	# On IA64, the linker does run time linking by default, so we don't
+	# have to do anything special.
+	aix_use_runtimelinking=no
+	exp_sym_flag='-Bexport'
+	no_entry_flag=""
+      else
+	# If we're using GNU nm, then we don't want the "-C" option.
+	# -C means demangle to AIX nm, but means don't demangle with GNU nm
+	# Also, AIX nm treats weak defined symbols like other global
+	# defined symbols, whereas GNU nm marks them as "W".
+	if $NM -V 2>&1 | $GREP 'GNU' > /dev/null; then
+	  _LT_TAGVAR(export_symbols_cmds, $1)='$NM -Bpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B") || (\$ 2 == "W")) && ([substr](\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols'
+	else
+	  _LT_TAGVAR(export_symbols_cmds, $1)='$NM -BCpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B")) && ([substr](\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols'
+	fi
+	aix_use_runtimelinking=no
+
+	# Test if we are trying to use run time linking or normal
+	# AIX style linking. If -brtl is somewhere in LDFLAGS, we
+	# need to do runtime linking.
+	case $host_os in aix4.[[23]]|aix4.[[23]].*|aix[[5-9]]*)
+	  for ld_flag in $LDFLAGS; do
+	  if (test $ld_flag = "-brtl" || test $ld_flag = "-Wl,-brtl"); then
+	    aix_use_runtimelinking=yes
+	    break
+	  fi
+	  done
+	  ;;
+	esac
+
+	exp_sym_flag='-bexport'
+	no_entry_flag='-bnoentry'
+      fi
+
+      # When large executables or shared objects are built, AIX ld can
+      # have problems creating the table of contents.  If linking a library
+      # or program results in "error TOC overflow" add -mminimal-toc to
+      # CXXFLAGS/CFLAGS for g++/gcc.  In the cases where that is not
+      # enough to fix the problem, add -Wl,-bbigtoc to LDFLAGS.
+
+      _LT_TAGVAR(archive_cmds, $1)=''
+      _LT_TAGVAR(hardcode_direct, $1)=yes
+      _LT_TAGVAR(hardcode_direct_absolute, $1)=yes
+      _LT_TAGVAR(hardcode_libdir_separator, $1)=':'
+      _LT_TAGVAR(link_all_deplibs, $1)=yes
+      _LT_TAGVAR(file_list_spec, $1)='${wl}-f,'
+
+      if test "$GCC" = yes; then
+	case $host_os in aix4.[[012]]|aix4.[[012]].*)
+	# We only want to do this on AIX 4.2 and lower, the check
+	# below for broken collect2 doesn't work under 4.3+
+	  collect2name=`${CC} -print-prog-name=collect2`
+	  if test -f "$collect2name" &&
+	   strings "$collect2name" | $GREP resolve_lib_name >/dev/null
+	  then
+	  # We have reworked collect2
+	  :
+	  else
+	  # We have old collect2
+	  _LT_TAGVAR(hardcode_direct, $1)=unsupported
+	  # It fails to find uninstalled libraries when the uninstalled
+	  # path is not listed in the libpath.  Setting hardcode_minus_L
+	  # to unsupported forces relinking
+	  _LT_TAGVAR(hardcode_minus_L, $1)=yes
+	  _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir'
+	  _LT_TAGVAR(hardcode_libdir_separator, $1)=
+	  fi
+	  ;;
+	esac
+	shared_flag='-shared'
+	if test "$aix_use_runtimelinking" = yes; then
+	  shared_flag="$shared_flag "'${wl}-G'
+	fi
+      else
+	# not using gcc
+	if test "$host_cpu" = ia64; then
+	# VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release
+	# chokes on -Wl,-G. The following line is correct:
+	  shared_flag='-G'
+	else
+	  if test "$aix_use_runtimelinking" = yes; then
+	    shared_flag='${wl}-G'
+	  else
+	    shared_flag='${wl}-bM:SRE'
+	  fi
+	fi
+      fi
+
+      _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-bexpall'
+      # It seems that -bexpall does not export symbols beginning with
+      # underscore (_), so it is better to generate a list of symbols to export.
+      _LT_TAGVAR(always_export_symbols, $1)=yes
+      if test "$aix_use_runtimelinking" = yes; then
+	# Warning - without using the other runtime loading flags (-brtl),
+	# -berok will link without error, but may produce a broken library.
+	_LT_TAGVAR(allow_undefined_flag, $1)='-berok'
+        # Determine the default libpath from the value encoded in an
+        # empty executable.
+        _LT_SYS_MODULE_PATH_AIX([$1])
+        _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-blibpath:$libdir:'"$aix_libpath"
+        _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_flag}" != "x"; then func_echo_all "${wl}${allow_undefined_flag}"; else :; fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag"
+      else
+	if test "$host_cpu" = ia64; then
+	  _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-R $libdir:/usr/lib:/lib'
+	  _LT_TAGVAR(allow_undefined_flag, $1)="-z nodefs"
+	  _LT_TAGVAR(archive_expsym_cmds, $1)="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undefined_flag} '"\${wl}$exp_sym_flag:\$export_symbols"
+	else
+	 # Determine the default libpath from the value encoded in an
+	 # empty executable.
+	 _LT_SYS_MODULE_PATH_AIX([$1])
+	 _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-blibpath:$libdir:'"$aix_libpath"
+	  # Warning - without using the other run time loading flags,
+	  # -berok will link without error, but may produce a broken library.
+	  _LT_TAGVAR(no_undefined_flag, $1)=' ${wl}-bernotok'
+	  _LT_TAGVAR(allow_undefined_flag, $1)=' ${wl}-berok'
+	  if test "$with_gnu_ld" = yes; then
+	    # We only use this code for GNU lds that support --whole-archive.
+	    _LT_TAGVAR(whole_archive_flag_spec, $1)='${wl}--whole-archive$convenience ${wl}--no-whole-archive'
+	  else
+	    # Exported symbols can be pulled into shared objects from archives
+	    _LT_TAGVAR(whole_archive_flag_spec, $1)='$convenience'
+	  fi
+	  _LT_TAGVAR(archive_cmds_need_lc, $1)=yes
+	  # This is similar to how AIX traditionally builds its shared libraries.
+	  _LT_TAGVAR(archive_expsym_cmds, $1)="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${allow_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output_objdir/$soname'
+	fi
+      fi
+      ;;
+
+    amigaos*)
+      case $host_cpu in
+      powerpc)
+            # see comment about AmigaOS4 .so support
+            _LT_TAGVAR(archive_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+            _LT_TAGVAR(archive_expsym_cmds, $1)=''
+        ;;
+      m68k)
+            _LT_TAGVAR(archive_cmds, $1)='$RM $output_objdir/a2ixlibrary.data~$ECHO "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$ECHO "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$ECHO "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$ECHO "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)'
+            _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir'
+            _LT_TAGVAR(hardcode_minus_L, $1)=yes
+        ;;
+      esac
+      ;;
+
+    bsdi[[45]]*)
+      _LT_TAGVAR(export_dynamic_flag_spec, $1)=-rdynamic
+      ;;
+
+    cygwin* | mingw* | pw32* | cegcc*)
+      # When not using gcc, we currently assume that we are using
+      # Microsoft Visual C++.
+      # hardcode_libdir_flag_spec is actually meaningless, as there is
+      # no search path for DLLs.
+      case $cc_basename in
+      cl*)
+	# Native MSVC
+	_LT_TAGVAR(hardcode_libdir_flag_spec, $1)=' '
+	_LT_TAGVAR(allow_undefined_flag, $1)=unsupported
+	_LT_TAGVAR(always_export_symbols, $1)=yes
+	_LT_TAGVAR(file_list_spec, $1)='@'
+	# Tell ltmain to make .lib files, not .a files.
+	libext=lib
+	# Tell ltmain to make .dll files, not .so files.
+	shrext_cmds=".dll"
+	# FIXME: Setting linknames here is a bad hack.
+	_LT_TAGVAR(archive_cmds, $1)='$CC -o $output_objdir/$soname $libobjs $compiler_flags $deplibs -Wl,-dll~linknames='
+	_LT_TAGVAR(archive_expsym_cmds, $1)='if test "x`$SED 1q $export_symbols`" = xEXPORTS; then
+	    sed -n -e 's/\\\\\\\(.*\\\\\\\)/-link\\\ -EXPORT:\\\\\\\1/' -e '1\\\!p' < $export_symbols > $output_objdir/$soname.exp;
+	  else
+	    sed -e 's/\\\\\\\(.*\\\\\\\)/-link\\\ -EXPORT:\\\\\\\1/' < $export_symbols > $output_objdir/$soname.exp;
+	  fi~
+	  $CC -o $tool_output_objdir$soname $libobjs $compiler_flags $deplibs "@$tool_output_objdir$soname.exp" -Wl,-DLL,-IMPLIB:"$tool_output_objdir$libname.dll.lib"~
+	  linknames='
+	# The linker will not automatically build a static lib if we build a DLL.
+	# _LT_TAGVAR(old_archive_from_new_cmds, $1)='true'
+	_LT_TAGVAR(enable_shared_with_static_runtimes, $1)=yes
+	_LT_TAGVAR(exclude_expsyms, $1)='_NULL_IMPORT_DESCRIPTOR|_IMPORT_DESCRIPTOR_.*'
+	_LT_TAGVAR(export_symbols_cmds, $1)='$NM $libobjs $convenience | $global_symbol_pipe | $SED -e '\''/^[[BCDGRS]][[ ]]/s/.*[[ ]]\([[^ ]]*\)/\1,DATA/'\'' | $SED -e '\''/^[[AITW]][[ ]]/s/.*[[ ]]//'\'' | sort | uniq > $export_symbols'
+	# Don't use ranlib
+	_LT_TAGVAR(old_postinstall_cmds, $1)='chmod 644 $oldlib'
+	_LT_TAGVAR(postlink_cmds, $1)='lt_outputfile="@OUTPUT@"~
+	  lt_tool_outputfile="@TOOL_OUTPUT@"~
+	  case $lt_outputfile in
+	    *.exe|*.EXE) ;;
+	    *)
+	      lt_outputfile="$lt_outputfile.exe"
+	      lt_tool_outputfile="$lt_tool_outputfile.exe"
+	      ;;
+	  esac~
+	  if test "$MANIFEST_TOOL" != ":" && test -f "$lt_outputfile.manifest"; then
+	    $MANIFEST_TOOL -manifest "$lt_tool_outputfile.manifest" -outputresource:"$lt_tool_outputfile" || exit 1;
+	    $RM "$lt_outputfile.manifest";
+	  fi'
+	;;
+      *)
+	# Assume MSVC wrapper
+	_LT_TAGVAR(hardcode_libdir_flag_spec, $1)=' '
+	_LT_TAGVAR(allow_undefined_flag, $1)=unsupported
+	# Tell ltmain to make .lib files, not .a files.
+	libext=lib
+	# Tell ltmain to make .dll files, not .so files.
+	shrext_cmds=".dll"
+	# FIXME: Setting linknames here is a bad hack.
+	_LT_TAGVAR(archive_cmds, $1)='$CC -o $lib $libobjs $compiler_flags `func_echo_all "$deplibs" | $SED '\''s/ -lc$//'\''` -link -dll~linknames='
+	# The linker will automatically build a .lib file if we build a DLL.
+	_LT_TAGVAR(old_archive_from_new_cmds, $1)='true'
+	# FIXME: Should let the user specify the lib program.
+	_LT_TAGVAR(old_archive_cmds, $1)='lib -OUT:$oldlib$oldobjs$old_deplibs'
+	_LT_TAGVAR(enable_shared_with_static_runtimes, $1)=yes
+	;;
+      esac
+      ;;
+
+    darwin* | rhapsody*)
+      _LT_DARWIN_LINKER_FEATURES($1)
+      ;;
+
+    dgux*)
+      _LT_TAGVAR(archive_cmds, $1)='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
+      _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir'
+      _LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+      ;;
+
+    # FreeBSD 2.2.[012] allows us to include c++rt0.o to get C++ constructor
+    # support.  Future versions do this automatically, but an explicit c++rt0.o
+    # does not break anything, and helps significantly (at the cost of a little
+    # extra space).
+    freebsd2.2*)
+      _LT_TAGVAR(archive_cmds, $1)='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags /usr/lib/c++rt0.o'
+      _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-R$libdir'
+      _LT_TAGVAR(hardcode_direct, $1)=yes
+      _LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+      ;;
+
+    # Unfortunately, older versions of FreeBSD 2 do not have this feature.
+    freebsd2.*)
+      _LT_TAGVAR(archive_cmds, $1)='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags'
+      _LT_TAGVAR(hardcode_direct, $1)=yes
+      _LT_TAGVAR(hardcode_minus_L, $1)=yes
+      _LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+      ;;
+
+    # FreeBSD 3 and greater uses gcc -shared to do shared libraries.
+    freebsd* | dragonfly*)
+      _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags'
+      _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-R$libdir'
+      _LT_TAGVAR(hardcode_direct, $1)=yes
+      _LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+      ;;
+
+    hpux9*)
+      if test "$GCC" = yes; then
+	_LT_TAGVAR(archive_cmds, $1)='$RM $output_objdir/$soname~$CC -shared $pic_flag ${wl}+b ${wl}$install_libdir -o $output_objdir/$soname $libobjs $deplibs $compiler_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib'
+      else
+	_LT_TAGVAR(archive_cmds, $1)='$RM $output_objdir/$soname~$LD -b +b $install_libdir -o $output_objdir/$soname $libobjs $deplibs $linker_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib'
+      fi
+      _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}+b ${wl}$libdir'
+      _LT_TAGVAR(hardcode_libdir_separator, $1)=:
+      _LT_TAGVAR(hardcode_direct, $1)=yes
+
+      # hardcode_minus_L: Not really in the search PATH,
+      # but as the default location of the library.
+      _LT_TAGVAR(hardcode_minus_L, $1)=yes
+      _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-E'
+      ;;
+
+    hpux10*)
+      if test "$GCC" = yes && test "$with_gnu_ld" = no; then
+	_LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags'
+      else
+	_LT_TAGVAR(archive_cmds, $1)='$LD -b +h $soname +b $install_libdir -o $lib $libobjs $deplibs $linker_flags'
+      fi
+      if test "$with_gnu_ld" = no; then
+	_LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}+b ${wl}$libdir'
+	_LT_TAGVAR(hardcode_libdir_separator, $1)=:
+	_LT_TAGVAR(hardcode_direct, $1)=yes
+	_LT_TAGVAR(hardcode_direct_absolute, $1)=yes
+	_LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-E'
+	# hardcode_minus_L: Not really in the search PATH,
+	# but as the default location of the library.
+	_LT_TAGVAR(hardcode_minus_L, $1)=yes
+      fi
+      ;;
+
+    hpux11*)
+      if test "$GCC" = yes && test "$with_gnu_ld" = no; then
+	case $host_cpu in
+	hppa*64*)
+	  _LT_TAGVAR(archive_cmds, $1)='$CC -shared ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags'
+	  ;;
+	ia64*)
+	  _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags'
+	  ;;
+	*)
+	  _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags'
+	  ;;
+	esac
+      else
+	case $host_cpu in
+	hppa*64*)
+	  _LT_TAGVAR(archive_cmds, $1)='$CC -b ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags'
+	  ;;
+	ia64*)
+	  _LT_TAGVAR(archive_cmds, $1)='$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags'
+	  ;;
+	*)
+	m4_if($1, [], [
+	  # Older versions of the 11.00 compiler do not understand -b yet
+	  # (HP92453-01 A.11.01.20 doesn't, HP92453-01 B.11.X.35175-35176.GP does)
+	  _LT_LINKER_OPTION([if $CC understands -b],
+	    _LT_TAGVAR(lt_cv_prog_compiler__b, $1), [-b],
+	    [_LT_TAGVAR(archive_cmds, $1)='$CC -b ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags'],
+	    [_LT_TAGVAR(archive_cmds, $1)='$LD -b +h $soname +b $install_libdir -o $lib $libobjs $deplibs $linker_flags'])],
+	  [_LT_TAGVAR(archive_cmds, $1)='$CC -b ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags'])
+	  ;;
+	esac
+      fi
+      if test "$with_gnu_ld" = no; then
+	_LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}+b ${wl}$libdir'
+	_LT_TAGVAR(hardcode_libdir_separator, $1)=:
+
+	case $host_cpu in
+	hppa*64*|ia64*)
+	  _LT_TAGVAR(hardcode_direct, $1)=no
+	  _LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+	  ;;
+	*)
+	  _LT_TAGVAR(hardcode_direct, $1)=yes
+	  _LT_TAGVAR(hardcode_direct_absolute, $1)=yes
+	  _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-E'
+
+	  # hardcode_minus_L: Not really in the search PATH,
+	  # but as the default location of the library.
+	  _LT_TAGVAR(hardcode_minus_L, $1)=yes
+	  ;;
+	esac
+      fi
+      ;;
+
+    irix5* | irix6* | nonstopux*)
+      if test "$GCC" = yes; then
+	_LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib'
+	# Try to use the -exported_symbol ld option, if it does not
+	# work, assume that -exports_file does not work either and
+	# implicitly export all symbols.
+	# This should be the same for all languages, so no per-tag cache variable.
+	AC_CACHE_CHECK([whether the $host_os linker accepts -exported_symbol],
+	  [lt_cv_irix_exported_symbol],
+	  [save_LDFLAGS="$LDFLAGS"
+	   LDFLAGS="$LDFLAGS -shared ${wl}-exported_symbol ${wl}foo ${wl}-update_registry ${wl}/dev/null"
+	   AC_LINK_IFELSE(
+	     [AC_LANG_SOURCE(
+	        [AC_LANG_CASE([C], [[int foo (void) { return 0; }]],
+			      [C++], [[int foo (void) { return 0; }]],
+			      [Fortran 77], [[
+      subroutine foo
+      end]],
+			      [Fortran], [[
+      subroutine foo
+      end]])])],
+	      [lt_cv_irix_exported_symbol=yes],
+	      [lt_cv_irix_exported_symbol=no])
+           LDFLAGS="$save_LDFLAGS"])
+	if test "$lt_cv_irix_exported_symbol" = yes; then
+          _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations ${wl}-exports_file ${wl}$export_symbols -o $lib'
+	fi
+      else
+	_LT_TAGVAR(archive_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib'
+	_LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -exports_file $export_symbols -o $lib'
+      fi
+      _LT_TAGVAR(archive_cmds_need_lc, $1)='no'
+      _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath ${wl}$libdir'
+      _LT_TAGVAR(hardcode_libdir_separator, $1)=:
+      _LT_TAGVAR(inherit_rpath, $1)=yes
+      _LT_TAGVAR(link_all_deplibs, $1)=yes
+      ;;
+
+    netbsd*)
+      if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then
+	_LT_TAGVAR(archive_cmds, $1)='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags'  # a.out
+      else
+	_LT_TAGVAR(archive_cmds, $1)='$LD -shared -o $lib $libobjs $deplibs $linker_flags'      # ELF
+      fi
+      _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-R$libdir'
+      _LT_TAGVAR(hardcode_direct, $1)=yes
+      _LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+      ;;
+
+    newsos6)
+      _LT_TAGVAR(archive_cmds, $1)='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
+      _LT_TAGVAR(hardcode_direct, $1)=yes
+      _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath ${wl}$libdir'
+      _LT_TAGVAR(hardcode_libdir_separator, $1)=:
+      _LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+      ;;
+
+    *nto* | *qnx*)
+      ;;
+
+    openbsd*)
+      if test -f /usr/libexec/ld.so; then
+	_LT_TAGVAR(hardcode_direct, $1)=yes
+	_LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+	_LT_TAGVAR(hardcode_direct_absolute, $1)=yes
+	if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then
+	  _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags'
+	  _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-retain-symbols-file,$export_symbols'
+	  _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath,$libdir'
+	  _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-E'
+	else
+	  case $host_os in
+	   openbsd[[01]].* | openbsd2.[[0-7]] | openbsd2.[[0-7]].*)
+	     _LT_TAGVAR(archive_cmds, $1)='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags'
+	     _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-R$libdir'
+	     ;;
+	   *)
+	     _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags'
+	     _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath,$libdir'
+	     ;;
+	  esac
+	fi
+      else
+	_LT_TAGVAR(ld_shlibs, $1)=no
+      fi
+      ;;
+
+    os2*)
+      _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir'
+      _LT_TAGVAR(hardcode_minus_L, $1)=yes
+      _LT_TAGVAR(allow_undefined_flag, $1)=unsupported
+      _LT_TAGVAR(archive_cmds, $1)='$ECHO "LIBRARY $libname INITINSTANCE" > $output_objdir/$libname.def~$ECHO "DESCRIPTION \"$libname\"" >> $output_objdir/$libname.def~echo DATA >> $output_objdir/$libname.def~echo " SINGLE NONSHARED" >> $output_objdir/$libname.def~echo EXPORTS >> $output_objdir/$libname.def~emxexp $libobjs >> $output_objdir/$libname.def~$CC -Zdll -Zcrtdll -o $lib $libobjs $deplibs $compiler_flags $output_objdir/$libname.def'
+      _LT_TAGVAR(old_archive_from_new_cmds, $1)='emximp -o $output_objdir/$libname.a $output_objdir/$libname.def'
+      ;;
+
+    osf3*)
+      if test "$GCC" = yes; then
+	_LT_TAGVAR(allow_undefined_flag, $1)=' ${wl}-expect_unresolved ${wl}\*'
+	_LT_TAGVAR(archive_cmds, $1)='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib'
+      else
+	_LT_TAGVAR(allow_undefined_flag, $1)=' -expect_unresolved \*'
+	_LT_TAGVAR(archive_cmds, $1)='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib'
+      fi
+      _LT_TAGVAR(archive_cmds_need_lc, $1)='no'
+      _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath ${wl}$libdir'
+      _LT_TAGVAR(hardcode_libdir_separator, $1)=:
+      ;;
+
+    osf4* | osf5*)	# as osf3* with the addition of -msym flag
+      if test "$GCC" = yes; then
+	_LT_TAGVAR(allow_undefined_flag, $1)=' ${wl}-expect_unresolved ${wl}\*'
+	_LT_TAGVAR(archive_cmds, $1)='$CC -shared${allow_undefined_flag} $pic_flag $libobjs $deplibs $compiler_flags ${wl}-msym ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib'
+	_LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath ${wl}$libdir'
+      else
+	_LT_TAGVAR(allow_undefined_flag, $1)=' -expect_unresolved \*'
+	_LT_TAGVAR(archive_cmds, $1)='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags -msym -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib'
+	_LT_TAGVAR(archive_expsym_cmds, $1)='for i in `cat $export_symbols`; do printf "%s %s\\n" -exported_symbol "\$i" >> $lib.exp; done; printf "%s\\n" "-hidden">> $lib.exp~
+	$CC -shared${allow_undefined_flag} ${wl}-input ${wl}$lib.exp $compiler_flags $libobjs $deplibs -soname $soname `test -n "$verstring" && $ECHO "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib~$RM $lib.exp'
+
+	# Both c and cxx compiler support -rpath directly
+	_LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-rpath $libdir'
+      fi
+      _LT_TAGVAR(archive_cmds_need_lc, $1)='no'
+      _LT_TAGVAR(hardcode_libdir_separator, $1)=:
+      ;;
+
+    solaris*)
+      _LT_TAGVAR(no_undefined_flag, $1)=' -z defs'
+      if test "$GCC" = yes; then
+	wlarc='${wl}'
+	_LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag ${wl}-z ${wl}text ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags'
+	_LT_TAGVAR(archive_expsym_cmds, $1)='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~
+	  $CC -shared $pic_flag ${wl}-z ${wl}text ${wl}-M ${wl}$lib.exp ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags~$RM $lib.exp'
+      else
+	case `$CC -V 2>&1` in
+	*"Compilers 5.0"*)
+	  wlarc=''
+	  _LT_TAGVAR(archive_cmds, $1)='$LD -G${allow_undefined_flag} -h $soname -o $lib $libobjs $deplibs $linker_flags'
+	  _LT_TAGVAR(archive_expsym_cmds, $1)='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~
+	  $LD -G${allow_undefined_flag} -M $lib.exp -h $soname -o $lib $libobjs $deplibs $linker_flags~$RM $lib.exp'
+	  ;;
+	*)
+	  wlarc='${wl}'
+	  _LT_TAGVAR(archive_cmds, $1)='$CC -G${allow_undefined_flag} -h $soname -o $lib $libobjs $deplibs $compiler_flags'
+	  _LT_TAGVAR(archive_expsym_cmds, $1)='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~
+	  $CC -G${allow_undefined_flag} -M $lib.exp -h $soname -o $lib $libobjs $deplibs $compiler_flags~$RM $lib.exp'
+	  ;;
+	esac
+      fi
+      _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-R$libdir'
+      _LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+      case $host_os in
+      solaris2.[[0-5]] | solaris2.[[0-5]].*) ;;
+      *)
+	# The compiler driver will combine and reorder linker options,
+	# but understands `-z linker_flag'.  GCC discards it without `$wl',
+	# but is careful enough not to reorder.
+	# Supported since Solaris 2.6 (maybe 2.5.1?)
+	if test "$GCC" = yes; then
+	  _LT_TAGVAR(whole_archive_flag_spec, $1)='${wl}-z ${wl}allextract$convenience ${wl}-z ${wl}defaultextract'
+	else
+	  _LT_TAGVAR(whole_archive_flag_spec, $1)='-z allextract$convenience -z defaultextract'
+	fi
+	;;
+      esac
+      _LT_TAGVAR(link_all_deplibs, $1)=yes
+      ;;
+
+    sunos4*)
+      if test "x$host_vendor" = xsequent; then
+	# Use $CC to link under sequent, because it throws in some extra .o
+	# files that make .init and .fini sections work.
+	_LT_TAGVAR(archive_cmds, $1)='$CC -G ${wl}-h $soname -o $lib $libobjs $deplibs $compiler_flags'
+      else
+	_LT_TAGVAR(archive_cmds, $1)='$LD -assert pure-text -Bstatic -o $lib $libobjs $deplibs $linker_flags'
+      fi
+      _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir'
+      _LT_TAGVAR(hardcode_direct, $1)=yes
+      _LT_TAGVAR(hardcode_minus_L, $1)=yes
+      _LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+      ;;
+
+    sysv4)
+      case $host_vendor in
+	sni)
+	  _LT_TAGVAR(archive_cmds, $1)='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
+	  _LT_TAGVAR(hardcode_direct, $1)=yes # is this really true???
+	;;
+	siemens)
+	  ## LD is ld it makes a PLAMLIB
+	  ## CC just makes a GrossModule.
+	  _LT_TAGVAR(archive_cmds, $1)='$LD -G -o $lib $libobjs $deplibs $linker_flags'
+	  _LT_TAGVAR(reload_cmds, $1)='$CC -r -o $output$reload_objs'
+	  _LT_TAGVAR(hardcode_direct, $1)=no
+        ;;
+	motorola)
+	  _LT_TAGVAR(archive_cmds, $1)='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
+	  _LT_TAGVAR(hardcode_direct, $1)=no #Motorola manual says yes, but my tests say they lie
+	;;
+      esac
+      runpath_var='LD_RUN_PATH'
+      _LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+      ;;
+
+    sysv4.3*)
+      _LT_TAGVAR(archive_cmds, $1)='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
+      _LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+      _LT_TAGVAR(export_dynamic_flag_spec, $1)='-Bexport'
+      ;;
+
+    sysv4*MP*)
+      if test -d /usr/nec; then
+	_LT_TAGVAR(archive_cmds, $1)='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
+	_LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+	runpath_var=LD_RUN_PATH
+	hardcode_runpath_var=yes
+	_LT_TAGVAR(ld_shlibs, $1)=yes
+      fi
+      ;;
+
+    sysv4*uw2* | sysv5OpenUNIX* | sysv5UnixWare7.[[01]].[[10]]* | unixware7* | sco3.2v5.0.[[024]]*)
+      _LT_TAGVAR(no_undefined_flag, $1)='${wl}-z,text'
+      _LT_TAGVAR(archive_cmds_need_lc, $1)=no
+      _LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+      runpath_var='LD_RUN_PATH'
+
+      if test "$GCC" = yes; then
+	_LT_TAGVAR(archive_cmds, $1)='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+	_LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+      else
+	_LT_TAGVAR(archive_cmds, $1)='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+	_LT_TAGVAR(archive_expsym_cmds, $1)='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+      fi
+      ;;
+
+    sysv5* | sco3.2v5* | sco5v6*)
+      # Note: We can NOT use -z defs as we might desire, because we do not
+      # link with -lc, and that would cause any symbols used from libc to
+      # always be unresolved, which means just about no library would
+      # ever link correctly.  If we're not using GNU ld we use -z text
+      # though, which does catch some bad symbols but isn't as heavy-handed
+      # as -z defs.
+      _LT_TAGVAR(no_undefined_flag, $1)='${wl}-z,text'
+      _LT_TAGVAR(allow_undefined_flag, $1)='${wl}-z,nodefs'
+      _LT_TAGVAR(archive_cmds_need_lc, $1)=no
+      _LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+      _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-R,$libdir'
+      _LT_TAGVAR(hardcode_libdir_separator, $1)=':'
+      _LT_TAGVAR(link_all_deplibs, $1)=yes
+      _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-Bexport'
+      runpath_var='LD_RUN_PATH'
+
+      if test "$GCC" = yes; then
+	_LT_TAGVAR(archive_cmds, $1)='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+	_LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+      else
+	_LT_TAGVAR(archive_cmds, $1)='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+	_LT_TAGVAR(archive_expsym_cmds, $1)='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+      fi
+      ;;
+
+    uts4*)
+      _LT_TAGVAR(archive_cmds, $1)='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
+      _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir'
+      _LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+      ;;
+
+    *)
+      _LT_TAGVAR(ld_shlibs, $1)=no
+      ;;
+    esac
+
+    if test x$host_vendor = xsni; then
+      case $host in
+      sysv4 | sysv4.2uw2* | sysv4.3* | sysv5*)
+	_LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-Blargedynsym'
+	;;
+      esac
+    fi
+  fi
+])
+AC_MSG_RESULT([$_LT_TAGVAR(ld_shlibs, $1)])
+test "$_LT_TAGVAR(ld_shlibs, $1)" = no && can_build_shared=no
+
+_LT_TAGVAR(with_gnu_ld, $1)=$with_gnu_ld
+
+_LT_DECL([], [libext], [0], [Old archive suffix (normally "a")])dnl
+_LT_DECL([], [shrext_cmds], [1], [Shared library suffix (normally ".so")])dnl
+_LT_DECL([], [extract_expsyms_cmds], [2],
+    [The commands to extract the exported symbol list from a shared archive])
+
+#
+# Do we need to explicitly link libc?
+#
+case "x$_LT_TAGVAR(archive_cmds_need_lc, $1)" in
+x|xyes)
+  # Assume -lc should be added
+  _LT_TAGVAR(archive_cmds_need_lc, $1)=yes
+
+  if test "$enable_shared" = yes && test "$GCC" = yes; then
+    case $_LT_TAGVAR(archive_cmds, $1) in
+    *'~'*)
+      # FIXME: we may have to deal with multi-command sequences.
+      ;;
+    '$CC '*)
+      # Test whether the compiler implicitly links with -lc since on some
+      # systems, -lgcc has to come before -lc. If gcc already passes -lc
+      # to ld, don't add -lc before -lgcc.
+      AC_CACHE_CHECK([whether -lc should be explicitly linked in],
+	[lt_cv_]_LT_TAGVAR(archive_cmds_need_lc, $1),
+	[$RM conftest*
+	echo "$lt_simple_compile_test_code" > conftest.$ac_ext
+
+	if AC_TRY_EVAL(ac_compile) 2>conftest.err; then
+	  soname=conftest
+	  lib=conftest
+	  libobjs=conftest.$ac_objext
+	  deplibs=
+	  wl=$_LT_TAGVAR(lt_prog_compiler_wl, $1)
+	  pic_flag=$_LT_TAGVAR(lt_prog_compiler_pic, $1)
+	  compiler_flags=-v
+	  linker_flags=-v
+	  verstring=
+	  output_objdir=.
+	  libname=conftest
+	  lt_save_allow_undefined_flag=$_LT_TAGVAR(allow_undefined_flag, $1)
+	  _LT_TAGVAR(allow_undefined_flag, $1)=
+	  if AC_TRY_EVAL(_LT_TAGVAR(archive_cmds, $1) 2\>\&1 \| $GREP \" -lc \" \>/dev/null 2\>\&1)
+	  then
+	    lt_cv_[]_LT_TAGVAR(archive_cmds_need_lc, $1)=no
+	  else
+	    lt_cv_[]_LT_TAGVAR(archive_cmds_need_lc, $1)=yes
+	  fi
+	  _LT_TAGVAR(allow_undefined_flag, $1)=$lt_save_allow_undefined_flag
+	else
+	  cat conftest.err 1>&5
+	fi
+	$RM conftest*
+	])
+      _LT_TAGVAR(archive_cmds_need_lc, $1)=$lt_cv_[]_LT_TAGVAR(archive_cmds_need_lc, $1)
+      ;;
+    esac
+  fi
+  ;;
+esac
+
+_LT_TAGDECL([build_libtool_need_lc], [archive_cmds_need_lc], [0],
+    [Whether or not to add -lc for building shared libraries])
+_LT_TAGDECL([allow_libtool_libs_with_static_runtimes],
+    [enable_shared_with_static_runtimes], [0],
+    [Whether or not to disallow shared libs when runtime libs are static])
+_LT_TAGDECL([], [export_dynamic_flag_spec], [1],
+    [Compiler flag to allow reflexive dlopens])
+_LT_TAGDECL([], [whole_archive_flag_spec], [1],
+    [Compiler flag to generate shared objects directly from archives])
+_LT_TAGDECL([], [compiler_needs_object], [1],
+    [Whether the compiler copes with passing no objects directly])
+_LT_TAGDECL([], [old_archive_from_new_cmds], [2],
+    [Create an old-style archive from a shared archive])
+_LT_TAGDECL([], [old_archive_from_expsyms_cmds], [2],
+    [Create a temporary old-style archive to link instead of a shared archive])
+_LT_TAGDECL([], [archive_cmds], [2], [Commands used to build a shared archive])
+_LT_TAGDECL([], [archive_expsym_cmds], [2])
+_LT_TAGDECL([], [module_cmds], [2],
+    [Commands used to build a loadable module if different from building
+    a shared archive.])
+_LT_TAGDECL([], [module_expsym_cmds], [2])
+_LT_TAGDECL([], [with_gnu_ld], [1],
+    [Whether we are building with GNU ld or not])
+_LT_TAGDECL([], [allow_undefined_flag], [1],
+    [Flag that allows shared libraries with undefined symbols to be built])
+_LT_TAGDECL([], [no_undefined_flag], [1],
+    [Flag that enforces no undefined symbols])
+_LT_TAGDECL([], [hardcode_libdir_flag_spec], [1],
+    [Flag to hardcode $libdir into a binary during linking.
+    This must work even if $libdir does not exist])
+_LT_TAGDECL([], [hardcode_libdir_separator], [1],
+    [Whether we need a single "-rpath" flag with a separated argument])
+_LT_TAGDECL([], [hardcode_direct], [0],
+    [Set to "yes" if using DIR/libNAME${shared_ext} during linking hardcodes
+    DIR into the resulting binary])
+_LT_TAGDECL([], [hardcode_direct_absolute], [0],
+    [Set to "yes" if using DIR/libNAME${shared_ext} during linking hardcodes
+    DIR into the resulting binary and the resulting library dependency is
+    "absolute", i.e impossible to change by setting ${shlibpath_var} if the
+    library is relocated])
+_LT_TAGDECL([], [hardcode_minus_L], [0],
+    [Set to "yes" if using the -LDIR flag during linking hardcodes DIR
+    into the resulting binary])
+_LT_TAGDECL([], [hardcode_shlibpath_var], [0],
+    [Set to "yes" if using SHLIBPATH_VAR=DIR during linking hardcodes DIR
+    into the resulting binary])
+_LT_TAGDECL([], [hardcode_automatic], [0],
+    [Set to "yes" if building a shared library automatically hardcodes DIR
+    into the library and all subsequent libraries and executables linked
+    against it])
+_LT_TAGDECL([], [inherit_rpath], [0],
+    [Set to yes if linker adds runtime paths of dependent libraries
+    to runtime path list])
+_LT_TAGDECL([], [link_all_deplibs], [0],
+    [Whether libtool must link a program against all its dependency libraries])
+_LT_TAGDECL([], [always_export_symbols], [0],
+    [Set to "yes" if exported symbols are required])
+_LT_TAGDECL([], [export_symbols_cmds], [2],
+    [The commands to list exported symbols])
+_LT_TAGDECL([], [exclude_expsyms], [1],
+    [Symbols that should not be listed in the preloaded symbols])
+_LT_TAGDECL([], [include_expsyms], [1],
+    [Symbols that must always be exported])
+_LT_TAGDECL([], [prelink_cmds], [2],
+    [Commands necessary for linking programs (against libraries) with templates])
+_LT_TAGDECL([], [postlink_cmds], [2],
+    [Commands necessary for finishing linking programs])
+_LT_TAGDECL([], [file_list_spec], [1],
+    [Specify filename containing input files])
+dnl FIXME: Not yet implemented
+dnl _LT_TAGDECL([], [thread_safe_flag_spec], [1],
+dnl    [Compiler flag to generate thread safe objects])
+])# _LT_LINKER_SHLIBS
+
+
+# _LT_LANG_C_CONFIG([TAG])
+# ------------------------
+# Ensure that the configuration variables for a C compiler are suitably
+# defined.  These variables are subsequently used by _LT_CONFIG to write
+# the compiler configuration to `libtool'.
+m4_defun([_LT_LANG_C_CONFIG],
+[m4_require([_LT_DECL_EGREP])dnl
+lt_save_CC="$CC"
+AC_LANG_PUSH(C)
+
+# Source file extension for C test sources.
+ac_ext=c
+
+# Object file extension for compiled C test sources.
+objext=o
+_LT_TAGVAR(objext, $1)=$objext
+
+# Code to be used in simple compile tests
+lt_simple_compile_test_code="int some_variable = 0;"
+
+# Code to be used in simple link tests
+lt_simple_link_test_code='int main(){return(0);}'
+
+_LT_TAG_COMPILER
+# Save the default compiler, since it gets overwritten when the other
+# tags are being tested, and _LT_TAGVAR(compiler, []) is a NOP.
+compiler_DEFAULT=$CC
+
+# save warnings/boilerplate of simple test code
+_LT_COMPILER_BOILERPLATE
+_LT_LINKER_BOILERPLATE
+
+## CAVEAT EMPTOR:
+## There is no encapsulation within the following macros, do not change
+## the running order or otherwise move them around unless you know exactly
+## what you are doing...
+if test -n "$compiler"; then
+  _LT_COMPILER_NO_RTTI($1)
+  _LT_COMPILER_PIC($1)
+  _LT_COMPILER_C_O($1)
+  _LT_COMPILER_FILE_LOCKS($1)
+  _LT_LINKER_SHLIBS($1)
+  _LT_SYS_DYNAMIC_LINKER($1)
+  _LT_LINKER_HARDCODE_LIBPATH($1)
+  LT_SYS_DLOPEN_SELF
+  _LT_CMD_STRIPLIB
+
+  # Report which library types will actually be built
+  AC_MSG_CHECKING([if libtool supports shared libraries])
+  AC_MSG_RESULT([$can_build_shared])
+
+  AC_MSG_CHECKING([whether to build shared libraries])
+  test "$can_build_shared" = "no" && enable_shared=no
+
+  # On AIX, shared libraries and static libraries use the same namespace, and
+  # are all built from PIC.
+  case $host_os in
+  aix3*)
+    test "$enable_shared" = yes && enable_static=no
+    if test -n "$RANLIB"; then
+      archive_cmds="$archive_cmds~\$RANLIB \$lib"
+      postinstall_cmds='$RANLIB $lib'
+    fi
+    ;;
+
+  aix[[4-9]]*)
+    if test "$host_cpu" != ia64 && test "$aix_use_runtimelinking" = no ; then
+      test "$enable_shared" = yes && enable_static=no
+    fi
+    ;;
+  esac
+  AC_MSG_RESULT([$enable_shared])
+
+  AC_MSG_CHECKING([whether to build static libraries])
+  # Make sure either enable_shared or enable_static is yes.
+  test "$enable_shared" = yes || enable_static=yes
+  AC_MSG_RESULT([$enable_static])
+
+  _LT_CONFIG($1)
+fi
+AC_LANG_POP
+CC="$lt_save_CC"
+])# _LT_LANG_C_CONFIG
+
+
+# _LT_LANG_CXX_CONFIG([TAG])
+# --------------------------
+# Ensure that the configuration variables for a C++ compiler are suitably
+# defined.  These variables are subsequently used by _LT_CONFIG to write
+# the compiler configuration to `libtool'.
+m4_defun([_LT_LANG_CXX_CONFIG],
+[m4_require([_LT_FILEUTILS_DEFAULTS])dnl
+m4_require([_LT_DECL_EGREP])dnl
+m4_require([_LT_PATH_MANIFEST_TOOL])dnl
+if test -n "$CXX" && ( test "X$CXX" != "Xno" &&
+    ( (test "X$CXX" = "Xg++" && `g++ -v >/dev/null 2>&1` ) ||
+    (test "X$CXX" != "Xg++"))) ; then
+  AC_PROG_CXXCPP
+else
+  _lt_caught_CXX_error=yes
+fi
+
+AC_LANG_PUSH(C++)
+_LT_TAGVAR(archive_cmds_need_lc, $1)=no
+_LT_TAGVAR(allow_undefined_flag, $1)=
+_LT_TAGVAR(always_export_symbols, $1)=no
+_LT_TAGVAR(archive_expsym_cmds, $1)=
+_LT_TAGVAR(compiler_needs_object, $1)=no
+_LT_TAGVAR(export_dynamic_flag_spec, $1)=
+_LT_TAGVAR(hardcode_direct, $1)=no
+_LT_TAGVAR(hardcode_direct_absolute, $1)=no
+_LT_TAGVAR(hardcode_libdir_flag_spec, $1)=
+_LT_TAGVAR(hardcode_libdir_separator, $1)=
+_LT_TAGVAR(hardcode_minus_L, $1)=no
+_LT_TAGVAR(hardcode_shlibpath_var, $1)=unsupported
+_LT_TAGVAR(hardcode_automatic, $1)=no
+_LT_TAGVAR(inherit_rpath, $1)=no
+_LT_TAGVAR(module_cmds, $1)=
+_LT_TAGVAR(module_expsym_cmds, $1)=
+_LT_TAGVAR(link_all_deplibs, $1)=unknown
+_LT_TAGVAR(old_archive_cmds, $1)=$old_archive_cmds
+_LT_TAGVAR(reload_flag, $1)=$reload_flag
+_LT_TAGVAR(reload_cmds, $1)=$reload_cmds
+_LT_TAGVAR(no_undefined_flag, $1)=
+_LT_TAGVAR(whole_archive_flag_spec, $1)=
+_LT_TAGVAR(enable_shared_with_static_runtimes, $1)=no
+
+# Source file extension for C++ test sources.
+ac_ext=cpp
+
+# Object file extension for compiled C++ test sources.
+objext=o
+_LT_TAGVAR(objext, $1)=$objext
+
+# No sense in running all these tests if we already determined that
+# the CXX compiler isn't working.  Some variables (like enable_shared)
+# are currently assumed to apply to all compilers on this platform,
+# and will be corrupted by setting them based on a non-working compiler.
+if test "$_lt_caught_CXX_error" != yes; then
+  # Code to be used in simple compile tests
+  lt_simple_compile_test_code="int some_variable = 0;"
+
+  # Code to be used in simple link tests
+  lt_simple_link_test_code='int main(int, char *[[]]) { return(0); }'
+
+  # ltmain only uses $CC for tagged configurations so make sure $CC is set.
+  _LT_TAG_COMPILER
+
+  # save warnings/boilerplate of simple test code
+  _LT_COMPILER_BOILERPLATE
+  _LT_LINKER_BOILERPLATE
+
+  # Allow CC to be a program name with arguments.
+  lt_save_CC=$CC
+  lt_save_CFLAGS=$CFLAGS
+  lt_save_LD=$LD
+  lt_save_GCC=$GCC
+  GCC=$GXX
+  lt_save_with_gnu_ld=$with_gnu_ld
+  lt_save_path_LD=$lt_cv_path_LD
+  if test -n "${lt_cv_prog_gnu_ldcxx+set}"; then
+    lt_cv_prog_gnu_ld=$lt_cv_prog_gnu_ldcxx
+  else
+    $as_unset lt_cv_prog_gnu_ld
+  fi
+  if test -n "${lt_cv_path_LDCXX+set}"; then
+    lt_cv_path_LD=$lt_cv_path_LDCXX
+  else
+    $as_unset lt_cv_path_LD
+  fi
+  test -z "${LDCXX+set}" || LD=$LDCXX
+  CC=${CXX-"c++"}
+  CFLAGS=$CXXFLAGS
+  compiler=$CC
+  _LT_TAGVAR(compiler, $1)=$CC
+  _LT_CC_BASENAME([$compiler])
+
+  if test -n "$compiler"; then
+    # We don't want -fno-exception when compiling C++ code, so set the
+    # no_builtin_flag separately
+    if test "$GXX" = yes; then
+      _LT_TAGVAR(lt_prog_compiler_no_builtin_flag, $1)=' -fno-builtin'
+    else
+      _LT_TAGVAR(lt_prog_compiler_no_builtin_flag, $1)=
+    fi
+
+    if test "$GXX" = yes; then
+      # Set up default GNU C++ configuration
+
+      LT_PATH_LD
+
+      # Check if GNU C++ uses GNU ld as the underlying linker, since the
+      # archiving commands below assume that GNU ld is being used.
+      if test "$with_gnu_ld" = yes; then
+        _LT_TAGVAR(archive_cmds, $1)='$CC $pic_flag -shared -nostdlib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname $wl$soname -o $lib'
+        _LT_TAGVAR(archive_expsym_cmds, $1)='$CC $pic_flag -shared -nostdlib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib'
+
+        _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath ${wl}$libdir'
+        _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}--export-dynamic'
+
+        # If archive_cmds runs LD, not CC, wlarc should be empty
+        # XXX I think wlarc can be eliminated in ltcf-cxx, but I need to
+        #     investigate it a little bit more. (MM)
+        wlarc='${wl}'
+
+        # ancient GNU ld didn't support --whole-archive et. al.
+        if eval "`$CC -print-prog-name=ld` --help 2>&1" |
+	  $GREP 'no-whole-archive' > /dev/null; then
+          _LT_TAGVAR(whole_archive_flag_spec, $1)="$wlarc"'--whole-archive$convenience '"$wlarc"'--no-whole-archive'
+        else
+          _LT_TAGVAR(whole_archive_flag_spec, $1)=
+        fi
+      else
+        with_gnu_ld=no
+        wlarc=
+
+        # A generic and very simple default shared library creation
+        # command for GNU C++ for the case where it uses the native
+        # linker, instead of GNU ld.  If possible, this setting should
+        # overridden to take advantage of the native linker features on
+        # the platform it is being used on.
+        _LT_TAGVAR(archive_cmds, $1)='$CC -shared -nostdlib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags -o $lib'
+      fi
+
+      # Commands to make compiler produce verbose output that lists
+      # what "hidden" libraries, object files and flags are used when
+      # linking a shared library.
+      output_verbose_link_cmd='$CC -shared $CFLAGS -v conftest.$objext 2>&1 | $GREP -v "^Configured with:" | $GREP "\-L"'
+
+    else
+      GXX=no
+      with_gnu_ld=no
+      wlarc=
+    fi
+
+    # PORTME: fill in a description of your system's C++ link characteristics
+    AC_MSG_CHECKING([whether the $compiler linker ($LD) supports shared libraries])
+    _LT_TAGVAR(ld_shlibs, $1)=yes
+    case $host_os in
+      aix3*)
+        # FIXME: insert proper C++ library support
+        _LT_TAGVAR(ld_shlibs, $1)=no
+        ;;
+      aix[[4-9]]*)
+        if test "$host_cpu" = ia64; then
+          # On IA64, the linker does run time linking by default, so we don't
+          # have to do anything special.
+          aix_use_runtimelinking=no
+          exp_sym_flag='-Bexport'
+          no_entry_flag=""
+        else
+          aix_use_runtimelinking=no
+
+          # Test if we are trying to use run time linking or normal
+          # AIX style linking. If -brtl is somewhere in LDFLAGS, we
+          # need to do runtime linking.
+          case $host_os in aix4.[[23]]|aix4.[[23]].*|aix[[5-9]]*)
+	    for ld_flag in $LDFLAGS; do
+	      case $ld_flag in
+	      *-brtl*)
+	        aix_use_runtimelinking=yes
+	        break
+	        ;;
+	      esac
+	    done
+	    ;;
+          esac
+
+          exp_sym_flag='-bexport'
+          no_entry_flag='-bnoentry'
+        fi
+
+        # When large executables or shared objects are built, AIX ld can
+        # have problems creating the table of contents.  If linking a library
+        # or program results in "error TOC overflow" add -mminimal-toc to
+        # CXXFLAGS/CFLAGS for g++/gcc.  In the cases where that is not
+        # enough to fix the problem, add -Wl,-bbigtoc to LDFLAGS.
+
+        _LT_TAGVAR(archive_cmds, $1)=''
+        _LT_TAGVAR(hardcode_direct, $1)=yes
+        _LT_TAGVAR(hardcode_direct_absolute, $1)=yes
+        _LT_TAGVAR(hardcode_libdir_separator, $1)=':'
+        _LT_TAGVAR(link_all_deplibs, $1)=yes
+        _LT_TAGVAR(file_list_spec, $1)='${wl}-f,'
+
+        if test "$GXX" = yes; then
+          case $host_os in aix4.[[012]]|aix4.[[012]].*)
+          # We only want to do this on AIX 4.2 and lower, the check
+          # below for broken collect2 doesn't work under 4.3+
+	  collect2name=`${CC} -print-prog-name=collect2`
+	  if test -f "$collect2name" &&
+	     strings "$collect2name" | $GREP resolve_lib_name >/dev/null
+	  then
+	    # We have reworked collect2
+	    :
+	  else
+	    # We have old collect2
+	    _LT_TAGVAR(hardcode_direct, $1)=unsupported
+	    # It fails to find uninstalled libraries when the uninstalled
+	    # path is not listed in the libpath.  Setting hardcode_minus_L
+	    # to unsupported forces relinking
+	    _LT_TAGVAR(hardcode_minus_L, $1)=yes
+	    _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir'
+	    _LT_TAGVAR(hardcode_libdir_separator, $1)=
+	  fi
+          esac
+          shared_flag='-shared'
+	  if test "$aix_use_runtimelinking" = yes; then
+	    shared_flag="$shared_flag "'${wl}-G'
+	  fi
+        else
+          # not using gcc
+          if test "$host_cpu" = ia64; then
+	  # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release
+	  # chokes on -Wl,-G. The following line is correct:
+	  shared_flag='-G'
+          else
+	    if test "$aix_use_runtimelinking" = yes; then
+	      shared_flag='${wl}-G'
+	    else
+	      shared_flag='${wl}-bM:SRE'
+	    fi
+          fi
+        fi
+
+        _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-bexpall'
+        # It seems that -bexpall does not export symbols beginning with
+        # underscore (_), so it is better to generate a list of symbols to
+	# export.
+        _LT_TAGVAR(always_export_symbols, $1)=yes
+        if test "$aix_use_runtimelinking" = yes; then
+          # Warning - without using the other runtime loading flags (-brtl),
+          # -berok will link without error, but may produce a broken library.
+          _LT_TAGVAR(allow_undefined_flag, $1)='-berok'
+          # Determine the default libpath from the value encoded in an empty
+          # executable.
+          _LT_SYS_MODULE_PATH_AIX([$1])
+          _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-blibpath:$libdir:'"$aix_libpath"
+
+          _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_flag}" != "x"; then func_echo_all "${wl}${allow_undefined_flag}"; else :; fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag"
+        else
+          if test "$host_cpu" = ia64; then
+	    _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-R $libdir:/usr/lib:/lib'
+	    _LT_TAGVAR(allow_undefined_flag, $1)="-z nodefs"
+	    _LT_TAGVAR(archive_expsym_cmds, $1)="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undefined_flag} '"\${wl}$exp_sym_flag:\$export_symbols"
+          else
+	    # Determine the default libpath from the value encoded in an
+	    # empty executable.
+	    _LT_SYS_MODULE_PATH_AIX([$1])
+	    _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-blibpath:$libdir:'"$aix_libpath"
+	    # Warning - without using the other run time loading flags,
+	    # -berok will link without error, but may produce a broken library.
+	    _LT_TAGVAR(no_undefined_flag, $1)=' ${wl}-bernotok'
+	    _LT_TAGVAR(allow_undefined_flag, $1)=' ${wl}-berok'
+	    if test "$with_gnu_ld" = yes; then
+	      # We only use this code for GNU lds that support --whole-archive.
+	      _LT_TAGVAR(whole_archive_flag_spec, $1)='${wl}--whole-archive$convenience ${wl}--no-whole-archive'
+	    else
+	      # Exported symbols can be pulled into shared objects from archives
+	      _LT_TAGVAR(whole_archive_flag_spec, $1)='$convenience'
+	    fi
+	    _LT_TAGVAR(archive_cmds_need_lc, $1)=yes
+	    # This is similar to how AIX traditionally builds its shared
+	    # libraries.
+	    _LT_TAGVAR(archive_expsym_cmds, $1)="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${allow_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output_objdir/$soname'
+          fi
+        fi
+        ;;
+
+      beos*)
+	if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then
+	  _LT_TAGVAR(allow_undefined_flag, $1)=unsupported
+	  # Joseph Beckenbach  says some releases of gcc
+	  # support --undefined.  This deserves some investigation.  FIXME
+	  _LT_TAGVAR(archive_cmds, $1)='$CC -nostart $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+	else
+	  _LT_TAGVAR(ld_shlibs, $1)=no
+	fi
+	;;
+
+      chorus*)
+        case $cc_basename in
+          *)
+	  # FIXME: insert proper C++ library support
+	  _LT_TAGVAR(ld_shlibs, $1)=no
+	  ;;
+        esac
+        ;;
+
+      cygwin* | mingw* | pw32* | cegcc*)
+	case $GXX,$cc_basename in
+	,cl* | no,cl*)
+	  # Native MSVC
+	  # hardcode_libdir_flag_spec is actually meaningless, as there is
+	  # no search path for DLLs.
+	  _LT_TAGVAR(hardcode_libdir_flag_spec, $1)=' '
+	  _LT_TAGVAR(allow_undefined_flag, $1)=unsupported
+	  _LT_TAGVAR(always_export_symbols, $1)=yes
+	  _LT_TAGVAR(file_list_spec, $1)='@'
+	  # Tell ltmain to make .lib files, not .a files.
+	  libext=lib
+	  # Tell ltmain to make .dll files, not .so files.
+	  shrext_cmds=".dll"
+	  # FIXME: Setting linknames here is a bad hack.
+	  _LT_TAGVAR(archive_cmds, $1)='$CC -o $output_objdir/$soname $libobjs $compiler_flags $deplibs -Wl,-dll~linknames='
+	  _LT_TAGVAR(archive_expsym_cmds, $1)='if test "x`$SED 1q $export_symbols`" = xEXPORTS; then
+	      $SED -n -e 's/\\\\\\\(.*\\\\\\\)/-link\\\ -EXPORT:\\\\\\\1/' -e '1\\\!p' < $export_symbols > $output_objdir/$soname.exp;
+	    else
+	      $SED -e 's/\\\\\\\(.*\\\\\\\)/-link\\\ -EXPORT:\\\\\\\1/' < $export_symbols > $output_objdir/$soname.exp;
+	    fi~
+	    $CC -o $tool_output_objdir$soname $libobjs $compiler_flags $deplibs "@$tool_output_objdir$soname.exp" -Wl,-DLL,-IMPLIB:"$tool_output_objdir$libname.dll.lib"~
+	    linknames='
+	  # The linker will not automatically build a static lib if we build a DLL.
+	  # _LT_TAGVAR(old_archive_from_new_cmds, $1)='true'
+	  _LT_TAGVAR(enable_shared_with_static_runtimes, $1)=yes
+	  # Don't use ranlib
+	  _LT_TAGVAR(old_postinstall_cmds, $1)='chmod 644 $oldlib'
+	  _LT_TAGVAR(postlink_cmds, $1)='lt_outputfile="@OUTPUT@"~
+	    lt_tool_outputfile="@TOOL_OUTPUT@"~
+	    case $lt_outputfile in
+	      *.exe|*.EXE) ;;
+	      *)
+		lt_outputfile="$lt_outputfile.exe"
+		lt_tool_outputfile="$lt_tool_outputfile.exe"
+		;;
+	    esac~
+	    func_to_tool_file "$lt_outputfile"~
+	    if test "$MANIFEST_TOOL" != ":" && test -f "$lt_outputfile.manifest"; then
+	      $MANIFEST_TOOL -manifest "$lt_tool_outputfile.manifest" -outputresource:"$lt_tool_outputfile" || exit 1;
+	      $RM "$lt_outputfile.manifest";
+	    fi'
+	  ;;
+	*)
+	  # g++
+	  # _LT_TAGVAR(hardcode_libdir_flag_spec, $1) is actually meaningless,
+	  # as there is no search path for DLLs.
+	  _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir'
+	  _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}--export-all-symbols'
+	  _LT_TAGVAR(allow_undefined_flag, $1)=unsupported
+	  _LT_TAGVAR(always_export_symbols, $1)=no
+	  _LT_TAGVAR(enable_shared_with_static_runtimes, $1)=yes
+
+	  if $LD --help 2>&1 | $GREP 'auto-import' > /dev/null; then
+	    _LT_TAGVAR(archive_cmds, $1)='$CC -shared -nostdlib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib'
+	    # If the export-symbols file already is a .def file (1st line
+	    # is EXPORTS), use it as is; otherwise, prepend...
+	    _LT_TAGVAR(archive_expsym_cmds, $1)='if test "x`$SED 1q $export_symbols`" = xEXPORTS; then
+	      cp $export_symbols $output_objdir/$soname.def;
+	    else
+	      echo EXPORTS > $output_objdir/$soname.def;
+	      cat $export_symbols >> $output_objdir/$soname.def;
+	    fi~
+	    $CC -shared -nostdlib $output_objdir/$soname.def $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib'
+	  else
+	    _LT_TAGVAR(ld_shlibs, $1)=no
+	  fi
+	  ;;
+	esac
+	;;
+      darwin* | rhapsody*)
+        _LT_DARWIN_LINKER_FEATURES($1)
+	;;
+
+      dgux*)
+        case $cc_basename in
+          ec++*)
+	    # FIXME: insert proper C++ library support
+	    _LT_TAGVAR(ld_shlibs, $1)=no
+	    ;;
+          ghcx*)
+	    # Green Hills C++ Compiler
+	    # FIXME: insert proper C++ library support
+	    _LT_TAGVAR(ld_shlibs, $1)=no
+	    ;;
+          *)
+	    # FIXME: insert proper C++ library support
+	    _LT_TAGVAR(ld_shlibs, $1)=no
+	    ;;
+        esac
+        ;;
+
+      freebsd2.*)
+        # C++ shared libraries reported to be fairly broken before
+	# switch to ELF
+        _LT_TAGVAR(ld_shlibs, $1)=no
+        ;;
+
+      freebsd-elf*)
+        _LT_TAGVAR(archive_cmds_need_lc, $1)=no
+        ;;
+
+      freebsd* | dragonfly*)
+        # FreeBSD 3 and later use GNU C++ and GNU ld with standard ELF
+        # conventions
+        _LT_TAGVAR(ld_shlibs, $1)=yes
+        ;;
+
+      gnu*)
+        ;;
+
+      haiku*)
+        _LT_TAGVAR(archive_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+        _LT_TAGVAR(link_all_deplibs, $1)=yes
+        ;;
+
+      hpux9*)
+        _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}+b ${wl}$libdir'
+        _LT_TAGVAR(hardcode_libdir_separator, $1)=:
+        _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-E'
+        _LT_TAGVAR(hardcode_direct, $1)=yes
+        _LT_TAGVAR(hardcode_minus_L, $1)=yes # Not in the search PATH,
+				             # but as the default
+				             # location of the library.
+
+        case $cc_basename in
+          CC*)
+            # FIXME: insert proper C++ library support
+            _LT_TAGVAR(ld_shlibs, $1)=no
+            ;;
+          aCC*)
+            _LT_TAGVAR(archive_cmds, $1)='$RM $output_objdir/$soname~$CC -b ${wl}+b ${wl}$install_libdir -o $output_objdir/$soname $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib'
+            # Commands to make compiler produce verbose output that lists
+            # what "hidden" libraries, object files and flags are used when
+            # linking a shared library.
+            #
+            # There doesn't appear to be a way to prevent this compiler from
+            # explicitly linking system object files so we need to strip them
+            # from the output so that they don't get included in the library
+            # dependencies.
+            output_verbose_link_cmd='templist=`($CC -b $CFLAGS -v conftest.$objext 2>&1) | $EGREP "\-L"`; list=""; for z in $templist; do case $z in conftest.$objext) list="$list $z";; *.$objext);; *) list="$list $z";;esac; done; func_echo_all "$list"'
+            ;;
+          *)
+            if test "$GXX" = yes; then
+              _LT_TAGVAR(archive_cmds, $1)='$RM $output_objdir/$soname~$CC -shared -nostdlib $pic_flag ${wl}+b ${wl}$install_libdir -o $output_objdir/$soname $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib'
+            else
+              # FIXME: insert proper C++ library support
+              _LT_TAGVAR(ld_shlibs, $1)=no
+            fi
+            ;;
+        esac
+        ;;
+
+      hpux10*|hpux11*)
+        if test $with_gnu_ld = no; then
+	  _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}+b ${wl}$libdir'
+	  _LT_TAGVAR(hardcode_libdir_separator, $1)=:
+
+          case $host_cpu in
+            hppa*64*|ia64*)
+              ;;
+            *)
+	      _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-E'
+              ;;
+          esac
+        fi
+        case $host_cpu in
+          hppa*64*|ia64*)
+            _LT_TAGVAR(hardcode_direct, $1)=no
+            _LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+            ;;
+          *)
+            _LT_TAGVAR(hardcode_direct, $1)=yes
+            _LT_TAGVAR(hardcode_direct_absolute, $1)=yes
+            _LT_TAGVAR(hardcode_minus_L, $1)=yes # Not in the search PATH,
+					         # but as the default
+					         # location of the library.
+            ;;
+        esac
+
+        case $cc_basename in
+          CC*)
+	    # FIXME: insert proper C++ library support
+	    _LT_TAGVAR(ld_shlibs, $1)=no
+	    ;;
+          aCC*)
+	    case $host_cpu in
+	      hppa*64*)
+	        _LT_TAGVAR(archive_cmds, $1)='$CC -b ${wl}+h ${wl}$soname -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags'
+	        ;;
+	      ia64*)
+	        _LT_TAGVAR(archive_cmds, $1)='$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags'
+	        ;;
+	      *)
+	        _LT_TAGVAR(archive_cmds, $1)='$CC -b ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags'
+	        ;;
+	    esac
+	    # Commands to make compiler produce verbose output that lists
+	    # what "hidden" libraries, object files and flags are used when
+	    # linking a shared library.
+	    #
+	    # There doesn't appear to be a way to prevent this compiler from
+	    # explicitly linking system object files so we need to strip them
+	    # from the output so that they don't get included in the library
+	    # dependencies.
+	    output_verbose_link_cmd='templist=`($CC -b $CFLAGS -v conftest.$objext 2>&1) | $GREP "\-L"`; list=""; for z in $templist; do case $z in conftest.$objext) list="$list $z";; *.$objext);; *) list="$list $z";;esac; done; func_echo_all "$list"'
+	    ;;
+          *)
+	    if test "$GXX" = yes; then
+	      if test $with_gnu_ld = no; then
+	        case $host_cpu in
+	          hppa*64*)
+	            _LT_TAGVAR(archive_cmds, $1)='$CC -shared -nostdlib -fPIC ${wl}+h ${wl}$soname -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags'
+	            ;;
+	          ia64*)
+	            _LT_TAGVAR(archive_cmds, $1)='$CC -shared -nostdlib $pic_flag ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags'
+	            ;;
+	          *)
+	            _LT_TAGVAR(archive_cmds, $1)='$CC -shared -nostdlib $pic_flag ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags'
+	            ;;
+	        esac
+	      fi
+	    else
+	      # FIXME: insert proper C++ library support
+	      _LT_TAGVAR(ld_shlibs, $1)=no
+	    fi
+	    ;;
+        esac
+        ;;
+
+      interix[[3-9]]*)
+	_LT_TAGVAR(hardcode_direct, $1)=no
+	_LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+	_LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath,$libdir'
+	_LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-E'
+	# Hack: On Interix 3.x, we cannot compile PIC because of a broken gcc.
+	# Instead, shared libraries are loaded at an image base (0x10000000 by
+	# default) and relocated if they conflict, which is a slow very memory
+	# consuming and fragmenting process.  To avoid this, we pick a random,
+	# 256 KiB-aligned image base between 0x50000000 and 0x6FFC0000 at link
+	# time.  Moving up from 0x10000000 also allows more sbrk(2) space.
+	_LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib'
+	_LT_TAGVAR(archive_expsym_cmds, $1)='sed "s,^,_," $export_symbols >$output_objdir/$soname.expsym~$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--retain-symbols-file,$output_objdir/$soname.expsym ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib'
+	;;
+      irix5* | irix6*)
+        case $cc_basename in
+          CC*)
+	    # SGI C++
+	    _LT_TAGVAR(archive_cmds, $1)='$CC -shared -all -multigot $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib'
+
+	    # Archives containing C++ object files must be created using
+	    # "CC -ar", where "CC" is the IRIX C++ compiler.  This is
+	    # necessary to make sure instantiated templates are included
+	    # in the archive.
+	    _LT_TAGVAR(old_archive_cmds, $1)='$CC -ar -WR,-u -o $oldlib $oldobjs'
+	    ;;
+          *)
+	    if test "$GXX" = yes; then
+	      if test "$with_gnu_ld" = no; then
+	        _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag -nostdlib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib'
+	      else
+	        _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag -nostdlib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` -o $lib'
+	      fi
+	    fi
+	    _LT_TAGVAR(link_all_deplibs, $1)=yes
+	    ;;
+        esac
+        _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath ${wl}$libdir'
+        _LT_TAGVAR(hardcode_libdir_separator, $1)=:
+        _LT_TAGVAR(inherit_rpath, $1)=yes
+        ;;
+
+      linux* | k*bsd*-gnu | kopensolaris*-gnu)
+        case $cc_basename in
+          KCC*)
+	    # Kuck and Associates, Inc. (KAI) C++ Compiler
+
+	    # KCC will only create a shared library if the output file
+	    # ends with ".so" (or ".sl" for HP-UX), so rename the library
+	    # to its proper name (with version) after linking.
+	    _LT_TAGVAR(archive_cmds, $1)='tempext=`echo $shared_ext | $SED -e '\''s/\([[^()0-9A-Za-z{}]]\)/\\\\\1/g'\''`; templib=`echo $lib | $SED -e "s/\${tempext}\..*/.so/"`; $CC $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags --soname $soname -o \$templib; mv \$templib $lib'
+	    _LT_TAGVAR(archive_expsym_cmds, $1)='tempext=`echo $shared_ext | $SED -e '\''s/\([[^()0-9A-Za-z{}]]\)/\\\\\1/g'\''`; templib=`echo $lib | $SED -e "s/\${tempext}\..*/.so/"`; $CC $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags --soname $soname -o \$templib ${wl}-retain-symbols-file,$export_symbols; mv \$templib $lib'
+	    # Commands to make compiler produce verbose output that lists
+	    # what "hidden" libraries, object files and flags are used when
+	    # linking a shared library.
+	    #
+	    # There doesn't appear to be a way to prevent this compiler from
+	    # explicitly linking system object files so we need to strip them
+	    # from the output so that they don't get included in the library
+	    # dependencies.
+	    output_verbose_link_cmd='templist=`$CC $CFLAGS -v conftest.$objext -o libconftest$shared_ext 2>&1 | $GREP "ld"`; rm -f libconftest$shared_ext; list=""; for z in $templist; do case $z in conftest.$objext) list="$list $z";; *.$objext);; *) list="$list $z";;esac; done; func_echo_all "$list"'
+
+	    _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath,$libdir'
+	    _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}--export-dynamic'
+
+	    # Archives containing C++ object files must be created using
+	    # "CC -Bstatic", where "CC" is the KAI C++ compiler.
+	    _LT_TAGVAR(old_archive_cmds, $1)='$CC -Bstatic -o $oldlib $oldobjs'
+	    ;;
+	  icpc* | ecpc* )
+	    # Intel C++
+	    with_gnu_ld=yes
+	    # version 8.0 and above of icpc choke on multiply defined symbols
+	    # if we add $predep_objects and $postdep_objects, however 7.1 and
+	    # earlier do not add the objects themselves.
+	    case `$CC -V 2>&1` in
+	      *"Version 7."*)
+	        _LT_TAGVAR(archive_cmds, $1)='$CC -shared $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname $wl$soname -o $lib'
+		_LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib'
+		;;
+	      *)  # Version 8.0 or newer
+	        tmp_idyn=
+	        case $host_cpu in
+		  ia64*) tmp_idyn=' -i_dynamic';;
+		esac
+	        _LT_TAGVAR(archive_cmds, $1)='$CC -shared'"$tmp_idyn"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+		_LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared'"$tmp_idyn"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib'
+		;;
+	    esac
+	    _LT_TAGVAR(archive_cmds_need_lc, $1)=no
+	    _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath,$libdir'
+	    _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}--export-dynamic'
+	    _LT_TAGVAR(whole_archive_flag_spec, $1)='${wl}--whole-archive$convenience ${wl}--no-whole-archive'
+	    ;;
+          pgCC* | pgcpp*)
+            # Portland Group C++ compiler
+	    case `$CC -V` in
+	    *pgCC\ [[1-5]].* | *pgcpp\ [[1-5]].*)
+	      _LT_TAGVAR(prelink_cmds, $1)='tpldir=Template.dir~
+		rm -rf $tpldir~
+		$CC --prelink_objects --instantiation_dir $tpldir $objs $libobjs $compile_deplibs~
+		compile_command="$compile_command `find $tpldir -name \*.o | sort | $NL2SP`"'
+	      _LT_TAGVAR(old_archive_cmds, $1)='tpldir=Template.dir~
+		rm -rf $tpldir~
+		$CC --prelink_objects --instantiation_dir $tpldir $oldobjs$old_deplibs~
+		$AR $AR_FLAGS $oldlib$oldobjs$old_deplibs `find $tpldir -name \*.o | sort | $NL2SP`~
+		$RANLIB $oldlib'
+	      _LT_TAGVAR(archive_cmds, $1)='tpldir=Template.dir~
+		rm -rf $tpldir~
+		$CC --prelink_objects --instantiation_dir $tpldir $predep_objects $libobjs $deplibs $convenience $postdep_objects~
+		$CC -shared $pic_flag $predep_objects $libobjs $deplibs `find $tpldir -name \*.o | sort | $NL2SP` $postdep_objects $compiler_flags ${wl}-soname ${wl}$soname -o $lib'
+	      _LT_TAGVAR(archive_expsym_cmds, $1)='tpldir=Template.dir~
+		rm -rf $tpldir~
+		$CC --prelink_objects --instantiation_dir $tpldir $predep_objects $libobjs $deplibs $convenience $postdep_objects~
+		$CC -shared $pic_flag $predep_objects $libobjs $deplibs `find $tpldir -name \*.o | sort | $NL2SP` $postdep_objects $compiler_flags ${wl}-soname ${wl}$soname ${wl}-retain-symbols-file ${wl}$export_symbols -o $lib'
+	      ;;
+	    *) # Version 6 and above use weak symbols
+	      _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname ${wl}$soname -o $lib'
+	      _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $pic_flag $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname ${wl}$soname ${wl}-retain-symbols-file ${wl}$export_symbols -o $lib'
+	      ;;
+	    esac
+
+	    _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}--rpath ${wl}$libdir'
+	    _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}--export-dynamic'
+	    _LT_TAGVAR(whole_archive_flag_spec, $1)='${wl}--whole-archive`for conv in $convenience\"\"; do test  -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive'
+            ;;
+	  cxx*)
+	    # Compaq C++
+	    _LT_TAGVAR(archive_cmds, $1)='$CC -shared $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname $wl$soname -o $lib'
+	    _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname $wl$soname  -o $lib ${wl}-retain-symbols-file $wl$export_symbols'
+
+	    runpath_var=LD_RUN_PATH
+	    _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-rpath $libdir'
+	    _LT_TAGVAR(hardcode_libdir_separator, $1)=:
+
+	    # Commands to make compiler produce verbose output that lists
+	    # what "hidden" libraries, object files and flags are used when
+	    # linking a shared library.
+	    #
+	    # There doesn't appear to be a way to prevent this compiler from
+	    # explicitly linking system object files so we need to strip them
+	    # from the output so that they don't get included in the library
+	    # dependencies.
+	    output_verbose_link_cmd='templist=`$CC -shared $CFLAGS -v conftest.$objext 2>&1 | $GREP "ld"`; templist=`func_echo_all "$templist" | $SED "s/\(^.*ld.*\)\( .*ld .*$\)/\1/"`; list=""; for z in $templist; do case $z in conftest.$objext) list="$list $z";; *.$objext);; *) list="$list $z";;esac; done; func_echo_all "X$list" | $Xsed'
+	    ;;
+	  xl* | mpixl* | bgxl*)
+	    # IBM XL 8.0 on PPC, with GNU ld
+	    _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath ${wl}$libdir'
+	    _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}--export-dynamic'
+	    _LT_TAGVAR(archive_cmds, $1)='$CC -qmkshrobj $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+	    if test "x$supports_anon_versioning" = xyes; then
+	      _LT_TAGVAR(archive_expsym_cmds, $1)='echo "{ global:" > $output_objdir/$libname.ver~
+		cat $export_symbols | sed -e "s/\(.*\)/\1;/" >> $output_objdir/$libname.ver~
+		echo "local: *; };" >> $output_objdir/$libname.ver~
+		$CC -qmkshrobj $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-version-script ${wl}$output_objdir/$libname.ver -o $lib'
+	    fi
+	    ;;
+	  *)
+	    case `$CC -V 2>&1 | sed 5q` in
+	    *Sun\ C*)
+	      # Sun C++ 5.9
+	      _LT_TAGVAR(no_undefined_flag, $1)=' -zdefs'
+	      _LT_TAGVAR(archive_cmds, $1)='$CC -G${allow_undefined_flag} -h$soname -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags'
+	      _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -G${allow_undefined_flag} -h$soname -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-retain-symbols-file ${wl}$export_symbols'
+	      _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-R$libdir'
+	      _LT_TAGVAR(whole_archive_flag_spec, $1)='${wl}--whole-archive`new_convenience=; for conv in $convenience\"\"; do test -z \"$conv\" || new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive'
+	      _LT_TAGVAR(compiler_needs_object, $1)=yes
+
+	      # Not sure whether something based on
+	      # $CC $CFLAGS -v conftest.$objext -o libconftest$shared_ext 2>&1
+	      # would be better.
+	      output_verbose_link_cmd='func_echo_all'
+
+	      # Archives containing C++ object files must be created using
+	      # "CC -xar", where "CC" is the Sun C++ compiler.  This is
+	      # necessary to make sure instantiated templates are included
+	      # in the archive.
+	      _LT_TAGVAR(old_archive_cmds, $1)='$CC -xar -o $oldlib $oldobjs'
+	      ;;
+	    esac
+	    ;;
+	esac
+	;;
+
+      lynxos*)
+        # FIXME: insert proper C++ library support
+	_LT_TAGVAR(ld_shlibs, $1)=no
+	;;
+
+      m88k*)
+        # FIXME: insert proper C++ library support
+        _LT_TAGVAR(ld_shlibs, $1)=no
+	;;
+
+      mvs*)
+        case $cc_basename in
+          cxx*)
+	    # FIXME: insert proper C++ library support
+	    _LT_TAGVAR(ld_shlibs, $1)=no
+	    ;;
+	  *)
+	    # FIXME: insert proper C++ library support
+	    _LT_TAGVAR(ld_shlibs, $1)=no
+	    ;;
+	esac
+	;;
+
+      netbsd*)
+        if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then
+	  _LT_TAGVAR(archive_cmds, $1)='$LD -Bshareable  -o $lib $predep_objects $libobjs $deplibs $postdep_objects $linker_flags'
+	  wlarc=
+	  _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-R$libdir'
+	  _LT_TAGVAR(hardcode_direct, $1)=yes
+	  _LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+	fi
+	# Workaround some broken pre-1.5 toolchains
+	output_verbose_link_cmd='$CC -shared $CFLAGS -v conftest.$objext 2>&1 | $GREP conftest.$objext | $SED -e "s:-lgcc -lc -lgcc::"'
+	;;
+
+      *nto* | *qnx*)
+        _LT_TAGVAR(ld_shlibs, $1)=yes
+	;;
+
+      openbsd2*)
+        # C++ shared libraries are fairly broken
+	_LT_TAGVAR(ld_shlibs, $1)=no
+	;;
+
+      openbsd*)
+	if test -f /usr/libexec/ld.so; then
+	  _LT_TAGVAR(hardcode_direct, $1)=yes
+	  _LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+	  _LT_TAGVAR(hardcode_direct_absolute, $1)=yes
+	  _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags -o $lib'
+	  _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath,$libdir'
+	  if test -z "`echo __ELF__ | $CC -E - | grep __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then
+	    _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $pic_flag $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-retain-symbols-file,$export_symbols -o $lib'
+	    _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-E'
+	    _LT_TAGVAR(whole_archive_flag_spec, $1)="$wlarc"'--whole-archive$convenience '"$wlarc"'--no-whole-archive'
+	  fi
+	  output_verbose_link_cmd=func_echo_all
+	else
+	  _LT_TAGVAR(ld_shlibs, $1)=no
+	fi
+	;;
+
+      osf3* | osf4* | osf5*)
+        case $cc_basename in
+          KCC*)
+	    # Kuck and Associates, Inc. (KAI) C++ Compiler
+
+	    # KCC will only create a shared library if the output file
+	    # ends with ".so" (or ".sl" for HP-UX), so rename the library
+	    # to its proper name (with version) after linking.
+	    _LT_TAGVAR(archive_cmds, $1)='tempext=`echo $shared_ext | $SED -e '\''s/\([[^()0-9A-Za-z{}]]\)/\\\\\1/g'\''`; templib=`echo "$lib" | $SED -e "s/\${tempext}\..*/.so/"`; $CC $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags --soname $soname -o \$templib; mv \$templib $lib'
+
+	    _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath,$libdir'
+	    _LT_TAGVAR(hardcode_libdir_separator, $1)=:
+
+	    # Archives containing C++ object files must be created using
+	    # the KAI C++ compiler.
+	    case $host in
+	      osf3*) _LT_TAGVAR(old_archive_cmds, $1)='$CC -Bstatic -o $oldlib $oldobjs' ;;
+	      *) _LT_TAGVAR(old_archive_cmds, $1)='$CC -o $oldlib $oldobjs' ;;
+	    esac
+	    ;;
+          RCC*)
+	    # Rational C++ 2.4.1
+	    # FIXME: insert proper C++ library support
+	    _LT_TAGVAR(ld_shlibs, $1)=no
+	    ;;
+          cxx*)
+	    case $host in
+	      osf3*)
+	        _LT_TAGVAR(allow_undefined_flag, $1)=' ${wl}-expect_unresolved ${wl}\*'
+	        _LT_TAGVAR(archive_cmds, $1)='$CC -shared${allow_undefined_flag} $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname $soname `test -n "$verstring" && func_echo_all "${wl}-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib'
+	        _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath ${wl}$libdir'
+		;;
+	      *)
+	        _LT_TAGVAR(allow_undefined_flag, $1)=' -expect_unresolved \*'
+	        _LT_TAGVAR(archive_cmds, $1)='$CC -shared${allow_undefined_flag} $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags -msym -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib'
+	        _LT_TAGVAR(archive_expsym_cmds, $1)='for i in `cat $export_symbols`; do printf "%s %s\\n" -exported_symbol "\$i" >> $lib.exp; done~
+	          echo "-hidden">> $lib.exp~
+	          $CC -shared$allow_undefined_flag $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags -msym -soname $soname ${wl}-input ${wl}$lib.exp  `test -n "$verstring" && $ECHO "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib~
+	          $RM $lib.exp'
+	        _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-rpath $libdir'
+		;;
+	    esac
+
+	    _LT_TAGVAR(hardcode_libdir_separator, $1)=:
+
+	    # Commands to make compiler produce verbose output that lists
+	    # what "hidden" libraries, object files and flags are used when
+	    # linking a shared library.
+	    #
+	    # There doesn't appear to be a way to prevent this compiler from
+	    # explicitly linking system object files so we need to strip them
+	    # from the output so that they don't get included in the library
+	    # dependencies.
+	    output_verbose_link_cmd='templist=`$CC -shared $CFLAGS -v conftest.$objext 2>&1 | $GREP "ld" | $GREP -v "ld:"`; templist=`func_echo_all "$templist" | $SED "s/\(^.*ld.*\)\( .*ld.*$\)/\1/"`; list=""; for z in $templist; do case $z in conftest.$objext) list="$list $z";; *.$objext);; *) list="$list $z";;esac; done; func_echo_all "$list"'
+	    ;;
+	  *)
+	    if test "$GXX" = yes && test "$with_gnu_ld" = no; then
+	      _LT_TAGVAR(allow_undefined_flag, $1)=' ${wl}-expect_unresolved ${wl}\*'
+	      case $host in
+	        osf3*)
+	          _LT_TAGVAR(archive_cmds, $1)='$CC -shared -nostdlib ${allow_undefined_flag} $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib'
+		  ;;
+	        *)
+	          _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag -nostdlib ${allow_undefined_flag} $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-msym ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib'
+		  ;;
+	      esac
+
+	      _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath ${wl}$libdir'
+	      _LT_TAGVAR(hardcode_libdir_separator, $1)=:
+
+	      # Commands to make compiler produce verbose output that lists
+	      # what "hidden" libraries, object files and flags are used when
+	      # linking a shared library.
+	      output_verbose_link_cmd='$CC -shared $CFLAGS -v conftest.$objext 2>&1 | $GREP -v "^Configured with:" | $GREP "\-L"'
+
+	    else
+	      # FIXME: insert proper C++ library support
+	      _LT_TAGVAR(ld_shlibs, $1)=no
+	    fi
+	    ;;
+        esac
+        ;;
+
+      psos*)
+        # FIXME: insert proper C++ library support
+        _LT_TAGVAR(ld_shlibs, $1)=no
+        ;;
+
+      sunos4*)
+        case $cc_basename in
+          CC*)
+	    # Sun C++ 4.x
+	    # FIXME: insert proper C++ library support
+	    _LT_TAGVAR(ld_shlibs, $1)=no
+	    ;;
+          lcc*)
+	    # Lucid
+	    # FIXME: insert proper C++ library support
+	    _LT_TAGVAR(ld_shlibs, $1)=no
+	    ;;
+          *)
+	    # FIXME: insert proper C++ library support
+	    _LT_TAGVAR(ld_shlibs, $1)=no
+	    ;;
+        esac
+        ;;
+
+      solaris*)
+        case $cc_basename in
+          CC* | sunCC*)
+	    # Sun C++ 4.2, 5.x and Centerline C++
+            _LT_TAGVAR(archive_cmds_need_lc,$1)=yes
+	    _LT_TAGVAR(no_undefined_flag, $1)=' -zdefs'
+	    _LT_TAGVAR(archive_cmds, $1)='$CC -G${allow_undefined_flag}  -h$soname -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags'
+	    _LT_TAGVAR(archive_expsym_cmds, $1)='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~
+	      $CC -G${allow_undefined_flag} ${wl}-M ${wl}$lib.exp -h$soname -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags~$RM $lib.exp'
+
+	    _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-R$libdir'
+	    _LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+	    case $host_os in
+	      solaris2.[[0-5]] | solaris2.[[0-5]].*) ;;
+	      *)
+		# The compiler driver will combine and reorder linker options,
+		# but understands `-z linker_flag'.
+	        # Supported since Solaris 2.6 (maybe 2.5.1?)
+		_LT_TAGVAR(whole_archive_flag_spec, $1)='-z allextract$convenience -z defaultextract'
+	        ;;
+	    esac
+	    _LT_TAGVAR(link_all_deplibs, $1)=yes
+
+	    output_verbose_link_cmd='func_echo_all'
+
+	    # Archives containing C++ object files must be created using
+	    # "CC -xar", where "CC" is the Sun C++ compiler.  This is
+	    # necessary to make sure instantiated templates are included
+	    # in the archive.
+	    _LT_TAGVAR(old_archive_cmds, $1)='$CC -xar -o $oldlib $oldobjs'
+	    ;;
+          gcx*)
+	    # Green Hills C++ Compiler
+	    _LT_TAGVAR(archive_cmds, $1)='$CC -shared $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-h $wl$soname -o $lib'
+
+	    # The C++ compiler must be used to create the archive.
+	    _LT_TAGVAR(old_archive_cmds, $1)='$CC $LDFLAGS -archive -o $oldlib $oldobjs'
+	    ;;
+          *)
+	    # GNU C++ compiler with Solaris linker
+	    if test "$GXX" = yes && test "$with_gnu_ld" = no; then
+	      _LT_TAGVAR(no_undefined_flag, $1)=' ${wl}-z ${wl}defs'
+	      if $CC --version | $GREP -v '^2\.7' > /dev/null; then
+	        _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag -nostdlib $LDFLAGS $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-h $wl$soname -o $lib'
+	        _LT_TAGVAR(archive_expsym_cmds, $1)='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~
+		  $CC -shared $pic_flag -nostdlib ${wl}-M $wl$lib.exp -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags~$RM $lib.exp'
+
+	        # Commands to make compiler produce verbose output that lists
+	        # what "hidden" libraries, object files and flags are used when
+	        # linking a shared library.
+	        output_verbose_link_cmd='$CC -shared $CFLAGS -v conftest.$objext 2>&1 | $GREP -v "^Configured with:" | $GREP "\-L"'
+	      else
+	        # g++ 2.7 appears to require `-G' NOT `-shared' on this
+	        # platform.
+	        _LT_TAGVAR(archive_cmds, $1)='$CC -G -nostdlib $LDFLAGS $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-h $wl$soname -o $lib'
+	        _LT_TAGVAR(archive_expsym_cmds, $1)='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~
+		  $CC -G -nostdlib ${wl}-M $wl$lib.exp -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags~$RM $lib.exp'
+
+	        # Commands to make compiler produce verbose output that lists
+	        # what "hidden" libraries, object files and flags are used when
+	        # linking a shared library.
+	        output_verbose_link_cmd='$CC -G $CFLAGS -v conftest.$objext 2>&1 | $GREP -v "^Configured with:" | $GREP "\-L"'
+	      fi
+
+	      _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-R $wl$libdir'
+	      case $host_os in
+		solaris2.[[0-5]] | solaris2.[[0-5]].*) ;;
+		*)
+		  _LT_TAGVAR(whole_archive_flag_spec, $1)='${wl}-z ${wl}allextract$convenience ${wl}-z ${wl}defaultextract'
+		  ;;
+	      esac
+	    fi
+	    ;;
+        esac
+        ;;
+
+    sysv4*uw2* | sysv5OpenUNIX* | sysv5UnixWare7.[[01]].[[10]]* | unixware7* | sco3.2v5.0.[[024]]*)
+      _LT_TAGVAR(no_undefined_flag, $1)='${wl}-z,text'
+      _LT_TAGVAR(archive_cmds_need_lc, $1)=no
+      _LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+      runpath_var='LD_RUN_PATH'
+
+      case $cc_basename in
+        CC*)
+	  _LT_TAGVAR(archive_cmds, $1)='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+	  _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+	  ;;
+	*)
+	  _LT_TAGVAR(archive_cmds, $1)='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+	  _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+	  ;;
+      esac
+      ;;
+
+      sysv5* | sco3.2v5* | sco5v6*)
+	# Note: We can NOT use -z defs as we might desire, because we do not
+	# link with -lc, and that would cause any symbols used from libc to
+	# always be unresolved, which means just about no library would
+	# ever link correctly.  If we're not using GNU ld we use -z text
+	# though, which does catch some bad symbols but isn't as heavy-handed
+	# as -z defs.
+	_LT_TAGVAR(no_undefined_flag, $1)='${wl}-z,text'
+	_LT_TAGVAR(allow_undefined_flag, $1)='${wl}-z,nodefs'
+	_LT_TAGVAR(archive_cmds_need_lc, $1)=no
+	_LT_TAGVAR(hardcode_shlibpath_var, $1)=no
+	_LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-R,$libdir'
+	_LT_TAGVAR(hardcode_libdir_separator, $1)=':'
+	_LT_TAGVAR(link_all_deplibs, $1)=yes
+	_LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-Bexport'
+	runpath_var='LD_RUN_PATH'
+
+	case $cc_basename in
+          CC*)
+	    _LT_TAGVAR(archive_cmds, $1)='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+	    _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+	    _LT_TAGVAR(old_archive_cmds, $1)='$CC -Tprelink_objects $oldobjs~
+	      '"$_LT_TAGVAR(old_archive_cmds, $1)"
+	    _LT_TAGVAR(reload_cmds, $1)='$CC -Tprelink_objects $reload_objs~
+	      '"$_LT_TAGVAR(reload_cmds, $1)"
+	    ;;
+	  *)
+	    _LT_TAGVAR(archive_cmds, $1)='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+	    _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+	    ;;
+	esac
+      ;;
+
+      tandem*)
+        case $cc_basename in
+          NCC*)
+	    # NonStop-UX NCC 3.20
+	    # FIXME: insert proper C++ library support
+	    _LT_TAGVAR(ld_shlibs, $1)=no
+	    ;;
+          *)
+	    # FIXME: insert proper C++ library support
+	    _LT_TAGVAR(ld_shlibs, $1)=no
+	    ;;
+        esac
+        ;;
+
+      vxworks*)
+        # FIXME: insert proper C++ library support
+        _LT_TAGVAR(ld_shlibs, $1)=no
+        ;;
+
+      *)
+        # FIXME: insert proper C++ library support
+        _LT_TAGVAR(ld_shlibs, $1)=no
+        ;;
+    esac
+
+    AC_MSG_RESULT([$_LT_TAGVAR(ld_shlibs, $1)])
+    test "$_LT_TAGVAR(ld_shlibs, $1)" = no && can_build_shared=no
+
+    _LT_TAGVAR(GCC, $1)="$GXX"
+    _LT_TAGVAR(LD, $1)="$LD"
+
+    ## CAVEAT EMPTOR:
+    ## There is no encapsulation within the following macros, do not change
+    ## the running order or otherwise move them around unless you know exactly
+    ## what you are doing...
+    _LT_SYS_HIDDEN_LIBDEPS($1)
+    _LT_COMPILER_PIC($1)
+    _LT_COMPILER_C_O($1)
+    _LT_COMPILER_FILE_LOCKS($1)
+    _LT_LINKER_SHLIBS($1)
+    _LT_SYS_DYNAMIC_LINKER($1)
+    _LT_LINKER_HARDCODE_LIBPATH($1)
+
+    _LT_CONFIG($1)
+  fi # test -n "$compiler"
+
+  CC=$lt_save_CC
+  CFLAGS=$lt_save_CFLAGS
+  LDCXX=$LD
+  LD=$lt_save_LD
+  GCC=$lt_save_GCC
+  with_gnu_ld=$lt_save_with_gnu_ld
+  lt_cv_path_LDCXX=$lt_cv_path_LD
+  lt_cv_path_LD=$lt_save_path_LD
+  lt_cv_prog_gnu_ldcxx=$lt_cv_prog_gnu_ld
+  lt_cv_prog_gnu_ld=$lt_save_with_gnu_ld
+fi # test "$_lt_caught_CXX_error" != yes
+
+AC_LANG_POP
+])# _LT_LANG_CXX_CONFIG
+
+
+# _LT_FUNC_STRIPNAME_CNF
+# ----------------------
+# func_stripname_cnf prefix suffix name
+# strip PREFIX and SUFFIX off of NAME.
+# PREFIX and SUFFIX must not contain globbing or regex special
+# characters, hashes, percent signs, but SUFFIX may contain a leading
+# dot (in which case that matches only a dot).
+#
+# This function is identical to the (non-XSI) version of func_stripname,
+# except this one can be used by m4 code that may be executed by configure,
+# rather than the libtool script.
+m4_defun([_LT_FUNC_STRIPNAME_CNF],[dnl
+AC_REQUIRE([_LT_DECL_SED])
+AC_REQUIRE([_LT_PROG_ECHO_BACKSLASH])
+func_stripname_cnf ()
+{
+  case ${2} in
+  .*) func_stripname_result=`$ECHO "${3}" | $SED "s%^${1}%%; s%\\\\${2}\$%%"`;;
+  *)  func_stripname_result=`$ECHO "${3}" | $SED "s%^${1}%%; s%${2}\$%%"`;;
+  esac
+} # func_stripname_cnf
+])# _LT_FUNC_STRIPNAME_CNF
+
+# _LT_SYS_HIDDEN_LIBDEPS([TAGNAME])
+# ---------------------------------
+# Figure out "hidden" library dependencies from verbose
+# compiler output when linking a shared library.
+# Parse the compiler output and extract the necessary
+# objects, libraries and library flags.
+m4_defun([_LT_SYS_HIDDEN_LIBDEPS],
+[m4_require([_LT_FILEUTILS_DEFAULTS])dnl
+AC_REQUIRE([_LT_FUNC_STRIPNAME_CNF])dnl
+# Dependencies to place before and after the object being linked:
+_LT_TAGVAR(predep_objects, $1)=
+_LT_TAGVAR(postdep_objects, $1)=
+_LT_TAGVAR(predeps, $1)=
+_LT_TAGVAR(postdeps, $1)=
+_LT_TAGVAR(compiler_lib_search_path, $1)=
+
+dnl we can't use the lt_simple_compile_test_code here,
+dnl because it contains code intended for an executable,
+dnl not a library.  It's possible we should let each
+dnl tag define a new lt_????_link_test_code variable,
+dnl but it's only used here...
+m4_if([$1], [], [cat > conftest.$ac_ext <<_LT_EOF
+int a;
+void foo (void) { a = 0; }
+_LT_EOF
+], [$1], [CXX], [cat > conftest.$ac_ext <<_LT_EOF
+class Foo
+{
+public:
+  Foo (void) { a = 0; }
+private:
+  int a;
+};
+_LT_EOF
+], [$1], [F77], [cat > conftest.$ac_ext <<_LT_EOF
+      subroutine foo
+      implicit none
+      integer*4 a
+      a=0
+      return
+      end
+_LT_EOF
+], [$1], [FC], [cat > conftest.$ac_ext <<_LT_EOF
+      subroutine foo
+      implicit none
+      integer a
+      a=0
+      return
+      end
+_LT_EOF
+], [$1], [GCJ], [cat > conftest.$ac_ext <<_LT_EOF
+public class foo {
+  private int a;
+  public void bar (void) {
+    a = 0;
+  }
+};
+_LT_EOF
+], [$1], [GO], [cat > conftest.$ac_ext <<_LT_EOF
+package foo
+func foo() {
+}
+_LT_EOF
+])
+
+_lt_libdeps_save_CFLAGS=$CFLAGS
+case "$CC $CFLAGS " in #(
+*\ -flto*\ *) CFLAGS="$CFLAGS -fno-lto" ;;
+*\ -fwhopr*\ *) CFLAGS="$CFLAGS -fno-whopr" ;;
+*\ -fuse-linker-plugin*\ *) CFLAGS="$CFLAGS -fno-use-linker-plugin" ;;
+esac
+
+dnl Parse the compiler output and extract the necessary
+dnl objects, libraries and library flags.
+if AC_TRY_EVAL(ac_compile); then
+  # Parse the compiler output and extract the necessary
+  # objects, libraries and library flags.
+
+  # Sentinel used to keep track of whether or not we are before
+  # the conftest object file.
+  pre_test_object_deps_done=no
+
+  for p in `eval "$output_verbose_link_cmd"`; do
+    case ${prev}${p} in
+
+    -L* | -R* | -l*)
+       # Some compilers place space between "-{L,R}" and the path.
+       # Remove the space.
+       if test $p = "-L" ||
+          test $p = "-R"; then
+	 prev=$p
+	 continue
+       fi
+
+       # Expand the sysroot to ease extracting the directories later.
+       if test -z "$prev"; then
+         case $p in
+         -L*) func_stripname_cnf '-L' '' "$p"; prev=-L; p=$func_stripname_result ;;
+         -R*) func_stripname_cnf '-R' '' "$p"; prev=-R; p=$func_stripname_result ;;
+         -l*) func_stripname_cnf '-l' '' "$p"; prev=-l; p=$func_stripname_result ;;
+         esac
+       fi
+       case $p in
+       =*) func_stripname_cnf '=' '' "$p"; p=$lt_sysroot$func_stripname_result ;;
+       esac
+       if test "$pre_test_object_deps_done" = no; then
+	 case ${prev} in
+	 -L | -R)
+	   # Internal compiler library paths should come after those
+	   # provided the user.  The postdeps already come after the
+	   # user supplied libs so there is no need to process them.
+	   if test -z "$_LT_TAGVAR(compiler_lib_search_path, $1)"; then
+	     _LT_TAGVAR(compiler_lib_search_path, $1)="${prev}${p}"
+	   else
+	     _LT_TAGVAR(compiler_lib_search_path, $1)="${_LT_TAGVAR(compiler_lib_search_path, $1)} ${prev}${p}"
+	   fi
+	   ;;
+	 # The "-l" case would never come before the object being
+	 # linked, so don't bother handling this case.
+	 esac
+       else
+	 if test -z "$_LT_TAGVAR(postdeps, $1)"; then
+	   _LT_TAGVAR(postdeps, $1)="${prev}${p}"
+	 else
+	   _LT_TAGVAR(postdeps, $1)="${_LT_TAGVAR(postdeps, $1)} ${prev}${p}"
+	 fi
+       fi
+       prev=
+       ;;
+
+    *.lto.$objext) ;; # Ignore GCC LTO objects
+    *.$objext)
+       # This assumes that the test object file only shows up
+       # once in the compiler output.
+       if test "$p" = "conftest.$objext"; then
+	 pre_test_object_deps_done=yes
+	 continue
+       fi
+
+       if test "$pre_test_object_deps_done" = no; then
+	 if test -z "$_LT_TAGVAR(predep_objects, $1)"; then
+	   _LT_TAGVAR(predep_objects, $1)="$p"
+	 else
+	   _LT_TAGVAR(predep_objects, $1)="$_LT_TAGVAR(predep_objects, $1) $p"
+	 fi
+       else
+	 if test -z "$_LT_TAGVAR(postdep_objects, $1)"; then
+	   _LT_TAGVAR(postdep_objects, $1)="$p"
+	 else
+	   _LT_TAGVAR(postdep_objects, $1)="$_LT_TAGVAR(postdep_objects, $1) $p"
+	 fi
+       fi
+       ;;
+
+    *) ;; # Ignore the rest.
+
+    esac
+  done
+
+  # Clean up.
+  rm -f a.out a.exe
+else
+  echo "libtool.m4: error: problem compiling $1 test program"
+fi
+
+$RM -f confest.$objext
+CFLAGS=$_lt_libdeps_save_CFLAGS
+
+# PORTME: override above test on systems where it is broken
+m4_if([$1], [CXX],
+[case $host_os in
+interix[[3-9]]*)
+  # Interix 3.5 installs completely hosed .la files for C++, so rather than
+  # hack all around it, let's just trust "g++" to DTRT.
+  _LT_TAGVAR(predep_objects,$1)=
+  _LT_TAGVAR(postdep_objects,$1)=
+  _LT_TAGVAR(postdeps,$1)=
+  ;;
+
+linux*)
+  case `$CC -V 2>&1 | sed 5q` in
+  *Sun\ C*)
+    # Sun C++ 5.9
+
+    # The more standards-conforming stlport4 library is
+    # incompatible with the Cstd library. Avoid specifying
+    # it if it's in CXXFLAGS. Ignore libCrun as
+    # -library=stlport4 depends on it.
+    case " $CXX $CXXFLAGS " in
+    *" -library=stlport4 "*)
+      solaris_use_stlport4=yes
+      ;;
+    esac
+
+    if test "$solaris_use_stlport4" != yes; then
+      _LT_TAGVAR(postdeps,$1)='-library=Cstd -library=Crun'
+    fi
+    ;;
+  esac
+  ;;
+
+solaris*)
+  case $cc_basename in
+  CC* | sunCC*)
+    # The more standards-conforming stlport4 library is
+    # incompatible with the Cstd library. Avoid specifying
+    # it if it's in CXXFLAGS. Ignore libCrun as
+    # -library=stlport4 depends on it.
+    case " $CXX $CXXFLAGS " in
+    *" -library=stlport4 "*)
+      solaris_use_stlport4=yes
+      ;;
+    esac
+
+    # Adding this requires a known-good setup of shared libraries for
+    # Sun compiler versions before 5.6, else PIC objects from an old
+    # archive will be linked into the output, leading to subtle bugs.
+    if test "$solaris_use_stlport4" != yes; then
+      _LT_TAGVAR(postdeps,$1)='-library=Cstd -library=Crun'
+    fi
+    ;;
+  esac
+  ;;
+esac
+])
+
+case " $_LT_TAGVAR(postdeps, $1) " in
+*" -lc "*) _LT_TAGVAR(archive_cmds_need_lc, $1)=no ;;
+esac
+ _LT_TAGVAR(compiler_lib_search_dirs, $1)=
+if test -n "${_LT_TAGVAR(compiler_lib_search_path, $1)}"; then
+ _LT_TAGVAR(compiler_lib_search_dirs, $1)=`echo " ${_LT_TAGVAR(compiler_lib_search_path, $1)}" | ${SED} -e 's! -L! !g' -e 's!^ !!'`
+fi
+_LT_TAGDECL([], [compiler_lib_search_dirs], [1],
+    [The directories searched by this compiler when creating a shared library])
+_LT_TAGDECL([], [predep_objects], [1],
+    [Dependencies to place before and after the objects being linked to
+    create a shared library])
+_LT_TAGDECL([], [postdep_objects], [1])
+_LT_TAGDECL([], [predeps], [1])
+_LT_TAGDECL([], [postdeps], [1])
+_LT_TAGDECL([], [compiler_lib_search_path], [1],
+    [The library search path used internally by the compiler when linking
+    a shared library])
+])# _LT_SYS_HIDDEN_LIBDEPS
+
+
+# _LT_LANG_F77_CONFIG([TAG])
+# --------------------------
+# Ensure that the configuration variables for a Fortran 77 compiler are
+# suitably defined.  These variables are subsequently used by _LT_CONFIG
+# to write the compiler configuration to `libtool'.
+m4_defun([_LT_LANG_F77_CONFIG],
+[AC_LANG_PUSH(Fortran 77)
+if test -z "$F77" || test "X$F77" = "Xno"; then
+  _lt_disable_F77=yes
+fi
+
+_LT_TAGVAR(archive_cmds_need_lc, $1)=no
+_LT_TAGVAR(allow_undefined_flag, $1)=
+_LT_TAGVAR(always_export_symbols, $1)=no
+_LT_TAGVAR(archive_expsym_cmds, $1)=
+_LT_TAGVAR(export_dynamic_flag_spec, $1)=
+_LT_TAGVAR(hardcode_direct, $1)=no
+_LT_TAGVAR(hardcode_direct_absolute, $1)=no
+_LT_TAGVAR(hardcode_libdir_flag_spec, $1)=
+_LT_TAGVAR(hardcode_libdir_separator, $1)=
+_LT_TAGVAR(hardcode_minus_L, $1)=no
+_LT_TAGVAR(hardcode_automatic, $1)=no
+_LT_TAGVAR(inherit_rpath, $1)=no
+_LT_TAGVAR(module_cmds, $1)=
+_LT_TAGVAR(module_expsym_cmds, $1)=
+_LT_TAGVAR(link_all_deplibs, $1)=unknown
+_LT_TAGVAR(old_archive_cmds, $1)=$old_archive_cmds
+_LT_TAGVAR(reload_flag, $1)=$reload_flag
+_LT_TAGVAR(reload_cmds, $1)=$reload_cmds
+_LT_TAGVAR(no_undefined_flag, $1)=
+_LT_TAGVAR(whole_archive_flag_spec, $1)=
+_LT_TAGVAR(enable_shared_with_static_runtimes, $1)=no
+
+# Source file extension for f77 test sources.
+ac_ext=f
+
+# Object file extension for compiled f77 test sources.
+objext=o
+_LT_TAGVAR(objext, $1)=$objext
+
+# No sense in running all these tests if we already determined that
+# the F77 compiler isn't working.  Some variables (like enable_shared)
+# are currently assumed to apply to all compilers on this platform,
+# and will be corrupted by setting them based on a non-working compiler.
+if test "$_lt_disable_F77" != yes; then
+  # Code to be used in simple compile tests
+  lt_simple_compile_test_code="\
+      subroutine t
+      return
+      end
+"
+
+  # Code to be used in simple link tests
+  lt_simple_link_test_code="\
+      program t
+      end
+"
+
+  # ltmain only uses $CC for tagged configurations so make sure $CC is set.
+  _LT_TAG_COMPILER
+
+  # save warnings/boilerplate of simple test code
+  _LT_COMPILER_BOILERPLATE
+  _LT_LINKER_BOILERPLATE
+
+  # Allow CC to be a program name with arguments.
+  lt_save_CC="$CC"
+  lt_save_GCC=$GCC
+  lt_save_CFLAGS=$CFLAGS
+  CC=${F77-"f77"}
+  CFLAGS=$FFLAGS
+  compiler=$CC
+  _LT_TAGVAR(compiler, $1)=$CC
+  _LT_CC_BASENAME([$compiler])
+  GCC=$G77
+  if test -n "$compiler"; then
+    AC_MSG_CHECKING([if libtool supports shared libraries])
+    AC_MSG_RESULT([$can_build_shared])
+
+    AC_MSG_CHECKING([whether to build shared libraries])
+    test "$can_build_shared" = "no" && enable_shared=no
+
+    # On AIX, shared libraries and static libraries use the same namespace, and
+    # are all built from PIC.
+    case $host_os in
+      aix3*)
+        test "$enable_shared" = yes && enable_static=no
+        if test -n "$RANLIB"; then
+          archive_cmds="$archive_cmds~\$RANLIB \$lib"
+          postinstall_cmds='$RANLIB $lib'
+        fi
+        ;;
+      aix[[4-9]]*)
+	if test "$host_cpu" != ia64 && test "$aix_use_runtimelinking" = no ; then
+	  test "$enable_shared" = yes && enable_static=no
+	fi
+        ;;
+    esac
+    AC_MSG_RESULT([$enable_shared])
+
+    AC_MSG_CHECKING([whether to build static libraries])
+    # Make sure either enable_shared or enable_static is yes.
+    test "$enable_shared" = yes || enable_static=yes
+    AC_MSG_RESULT([$enable_static])
+
+    _LT_TAGVAR(GCC, $1)="$G77"
+    _LT_TAGVAR(LD, $1)="$LD"
+
+    ## CAVEAT EMPTOR:
+    ## There is no encapsulation within the following macros, do not change
+    ## the running order or otherwise move them around unless you know exactly
+    ## what you are doing...
+    _LT_COMPILER_PIC($1)
+    _LT_COMPILER_C_O($1)
+    _LT_COMPILER_FILE_LOCKS($1)
+    _LT_LINKER_SHLIBS($1)
+    _LT_SYS_DYNAMIC_LINKER($1)
+    _LT_LINKER_HARDCODE_LIBPATH($1)
+
+    _LT_CONFIG($1)
+  fi # test -n "$compiler"
+
+  GCC=$lt_save_GCC
+  CC="$lt_save_CC"
+  CFLAGS="$lt_save_CFLAGS"
+fi # test "$_lt_disable_F77" != yes
+
+AC_LANG_POP
+])# _LT_LANG_F77_CONFIG
+
+
+# _LT_LANG_FC_CONFIG([TAG])
+# -------------------------
+# Ensure that the configuration variables for a Fortran compiler are
+# suitably defined.  These variables are subsequently used by _LT_CONFIG
+# to write the compiler configuration to `libtool'.
+m4_defun([_LT_LANG_FC_CONFIG],
+[AC_LANG_PUSH(Fortran)
+
+if test -z "$FC" || test "X$FC" = "Xno"; then
+  _lt_disable_FC=yes
+fi
+
+_LT_TAGVAR(archive_cmds_need_lc, $1)=no
+_LT_TAGVAR(allow_undefined_flag, $1)=
+_LT_TAGVAR(always_export_symbols, $1)=no
+_LT_TAGVAR(archive_expsym_cmds, $1)=
+_LT_TAGVAR(export_dynamic_flag_spec, $1)=
+_LT_TAGVAR(hardcode_direct, $1)=no
+_LT_TAGVAR(hardcode_direct_absolute, $1)=no
+_LT_TAGVAR(hardcode_libdir_flag_spec, $1)=
+_LT_TAGVAR(hardcode_libdir_separator, $1)=
+_LT_TAGVAR(hardcode_minus_L, $1)=no
+_LT_TAGVAR(hardcode_automatic, $1)=no
+_LT_TAGVAR(inherit_rpath, $1)=no
+_LT_TAGVAR(module_cmds, $1)=
+_LT_TAGVAR(module_expsym_cmds, $1)=
+_LT_TAGVAR(link_all_deplibs, $1)=unknown
+_LT_TAGVAR(old_archive_cmds, $1)=$old_archive_cmds
+_LT_TAGVAR(reload_flag, $1)=$reload_flag
+_LT_TAGVAR(reload_cmds, $1)=$reload_cmds
+_LT_TAGVAR(no_undefined_flag, $1)=
+_LT_TAGVAR(whole_archive_flag_spec, $1)=
+_LT_TAGVAR(enable_shared_with_static_runtimes, $1)=no
+
+# Source file extension for fc test sources.
+ac_ext=${ac_fc_srcext-f}
+
+# Object file extension for compiled fc test sources.
+objext=o
+_LT_TAGVAR(objext, $1)=$objext
+
+# No sense in running all these tests if we already determined that
+# the FC compiler isn't working.  Some variables (like enable_shared)
+# are currently assumed to apply to all compilers on this platform,
+# and will be corrupted by setting them based on a non-working compiler.
+if test "$_lt_disable_FC" != yes; then
+  # Code to be used in simple compile tests
+  lt_simple_compile_test_code="\
+      subroutine t
+      return
+      end
+"
+
+  # Code to be used in simple link tests
+  lt_simple_link_test_code="\
+      program t
+      end
+"
+
+  # ltmain only uses $CC for tagged configurations so make sure $CC is set.
+  _LT_TAG_COMPILER
+
+  # save warnings/boilerplate of simple test code
+  _LT_COMPILER_BOILERPLATE
+  _LT_LINKER_BOILERPLATE
+
+  # Allow CC to be a program name with arguments.
+  lt_save_CC="$CC"
+  lt_save_GCC=$GCC
+  lt_save_CFLAGS=$CFLAGS
+  CC=${FC-"f95"}
+  CFLAGS=$FCFLAGS
+  compiler=$CC
+  GCC=$ac_cv_fc_compiler_gnu
+
+  _LT_TAGVAR(compiler, $1)=$CC
+  _LT_CC_BASENAME([$compiler])
+
+  if test -n "$compiler"; then
+    AC_MSG_CHECKING([if libtool supports shared libraries])
+    AC_MSG_RESULT([$can_build_shared])
+
+    AC_MSG_CHECKING([whether to build shared libraries])
+    test "$can_build_shared" = "no" && enable_shared=no
+
+    # On AIX, shared libraries and static libraries use the same namespace, and
+    # are all built from PIC.
+    case $host_os in
+      aix3*)
+        test "$enable_shared" = yes && enable_static=no
+        if test -n "$RANLIB"; then
+          archive_cmds="$archive_cmds~\$RANLIB \$lib"
+          postinstall_cmds='$RANLIB $lib'
+        fi
+        ;;
+      aix[[4-9]]*)
+	if test "$host_cpu" != ia64 && test "$aix_use_runtimelinking" = no ; then
+	  test "$enable_shared" = yes && enable_static=no
+	fi
+        ;;
+    esac
+    AC_MSG_RESULT([$enable_shared])
+
+    AC_MSG_CHECKING([whether to build static libraries])
+    # Make sure either enable_shared or enable_static is yes.
+    test "$enable_shared" = yes || enable_static=yes
+    AC_MSG_RESULT([$enable_static])
+
+    _LT_TAGVAR(GCC, $1)="$ac_cv_fc_compiler_gnu"
+    _LT_TAGVAR(LD, $1)="$LD"
+
+    ## CAVEAT EMPTOR:
+    ## There is no encapsulation within the following macros, do not change
+    ## the running order or otherwise move them around unless you know exactly
+    ## what you are doing...
+    _LT_SYS_HIDDEN_LIBDEPS($1)
+    _LT_COMPILER_PIC($1)
+    _LT_COMPILER_C_O($1)
+    _LT_COMPILER_FILE_LOCKS($1)
+    _LT_LINKER_SHLIBS($1)
+    _LT_SYS_DYNAMIC_LINKER($1)
+    _LT_LINKER_HARDCODE_LIBPATH($1)
+
+    _LT_CONFIG($1)
+  fi # test -n "$compiler"
+
+  GCC=$lt_save_GCC
+  CC=$lt_save_CC
+  CFLAGS=$lt_save_CFLAGS
+fi # test "$_lt_disable_FC" != yes
+
+AC_LANG_POP
+])# _LT_LANG_FC_CONFIG
+
+
+# _LT_LANG_GCJ_CONFIG([TAG])
+# --------------------------
+# Ensure that the configuration variables for the GNU Java Compiler compiler
+# are suitably defined.  These variables are subsequently used by _LT_CONFIG
+# to write the compiler configuration to `libtool'.
+m4_defun([_LT_LANG_GCJ_CONFIG],
+[AC_REQUIRE([LT_PROG_GCJ])dnl
+AC_LANG_SAVE
+
+# Source file extension for Java test sources.
+ac_ext=java
+
+# Object file extension for compiled Java test sources.
+objext=o
+_LT_TAGVAR(objext, $1)=$objext
+
+# Code to be used in simple compile tests
+lt_simple_compile_test_code="class foo {}"
+
+# Code to be used in simple link tests
+lt_simple_link_test_code='public class conftest { public static void main(String[[]] argv) {}; }'
+
+# ltmain only uses $CC for tagged configurations so make sure $CC is set.
+_LT_TAG_COMPILER
+
+# save warnings/boilerplate of simple test code
+_LT_COMPILER_BOILERPLATE
+_LT_LINKER_BOILERPLATE
+
+# Allow CC to be a program name with arguments.
+lt_save_CC=$CC
+lt_save_CFLAGS=$CFLAGS
+lt_save_GCC=$GCC
+GCC=yes
+CC=${GCJ-"gcj"}
+CFLAGS=$GCJFLAGS
+compiler=$CC
+_LT_TAGVAR(compiler, $1)=$CC
+_LT_TAGVAR(LD, $1)="$LD"
+_LT_CC_BASENAME([$compiler])
+
+# GCJ did not exist at the time GCC didn't implicitly link libc in.
+_LT_TAGVAR(archive_cmds_need_lc, $1)=no
+
+_LT_TAGVAR(old_archive_cmds, $1)=$old_archive_cmds
+_LT_TAGVAR(reload_flag, $1)=$reload_flag
+_LT_TAGVAR(reload_cmds, $1)=$reload_cmds
+
+## CAVEAT EMPTOR:
+## There is no encapsulation within the following macros, do not change
+## the running order or otherwise move them around unless you know exactly
+## what you are doing...
+if test -n "$compiler"; then
+  _LT_COMPILER_NO_RTTI($1)
+  _LT_COMPILER_PIC($1)
+  _LT_COMPILER_C_O($1)
+  _LT_COMPILER_FILE_LOCKS($1)
+  _LT_LINKER_SHLIBS($1)
+  _LT_LINKER_HARDCODE_LIBPATH($1)
+
+  _LT_CONFIG($1)
+fi
+
+AC_LANG_RESTORE
+
+GCC=$lt_save_GCC
+CC=$lt_save_CC
+CFLAGS=$lt_save_CFLAGS
+])# _LT_LANG_GCJ_CONFIG
+
+
+# _LT_LANG_GO_CONFIG([TAG])
+# --------------------------
+# Ensure that the configuration variables for the GNU Go compiler
+# are suitably defined.  These variables are subsequently used by _LT_CONFIG
+# to write the compiler configuration to `libtool'.
+m4_defun([_LT_LANG_GO_CONFIG],
+[AC_REQUIRE([LT_PROG_GO])dnl
+AC_LANG_SAVE
+
+# Source file extension for Go test sources.
+ac_ext=go
+
+# Object file extension for compiled Go test sources.
+objext=o
+_LT_TAGVAR(objext, $1)=$objext
+
+# Code to be used in simple compile tests
+lt_simple_compile_test_code="package main; func main() { }"
+
+# Code to be used in simple link tests
+lt_simple_link_test_code='package main; func main() { }'
+
+# ltmain only uses $CC for tagged configurations so make sure $CC is set.
+_LT_TAG_COMPILER
+
+# save warnings/boilerplate of simple test code
+_LT_COMPILER_BOILERPLATE
+_LT_LINKER_BOILERPLATE
+
+# Allow CC to be a program name with arguments.
+lt_save_CC=$CC
+lt_save_CFLAGS=$CFLAGS
+lt_save_GCC=$GCC
+GCC=yes
+CC=${GOC-"gccgo"}
+CFLAGS=$GOFLAGS
+compiler=$CC
+_LT_TAGVAR(compiler, $1)=$CC
+_LT_TAGVAR(LD, $1)="$LD"
+_LT_CC_BASENAME([$compiler])
+
+# Go did not exist at the time GCC didn't implicitly link libc in.
+_LT_TAGVAR(archive_cmds_need_lc, $1)=no
+
+_LT_TAGVAR(old_archive_cmds, $1)=$old_archive_cmds
+_LT_TAGVAR(reload_flag, $1)=$reload_flag
+_LT_TAGVAR(reload_cmds, $1)=$reload_cmds
+
+## CAVEAT EMPTOR:
+## There is no encapsulation within the following macros, do not change
+## the running order or otherwise move them around unless you know exactly
+## what you are doing...
+if test -n "$compiler"; then
+  _LT_COMPILER_NO_RTTI($1)
+  _LT_COMPILER_PIC($1)
+  _LT_COMPILER_C_O($1)
+  _LT_COMPILER_FILE_LOCKS($1)
+  _LT_LINKER_SHLIBS($1)
+  _LT_LINKER_HARDCODE_LIBPATH($1)
+
+  _LT_CONFIG($1)
+fi
+
+AC_LANG_RESTORE
+
+GCC=$lt_save_GCC
+CC=$lt_save_CC
+CFLAGS=$lt_save_CFLAGS
+])# _LT_LANG_GO_CONFIG
+
+
+# _LT_LANG_RC_CONFIG([TAG])
+# -------------------------
+# Ensure that the configuration variables for the Windows resource compiler
+# are suitably defined.  These variables are subsequently used by _LT_CONFIG
+# to write the compiler configuration to `libtool'.
+m4_defun([_LT_LANG_RC_CONFIG],
+[AC_REQUIRE([LT_PROG_RC])dnl
+AC_LANG_SAVE
+
+# Source file extension for RC test sources.
+ac_ext=rc
+
+# Object file extension for compiled RC test sources.
+objext=o
+_LT_TAGVAR(objext, $1)=$objext
+
+# Code to be used in simple compile tests
+lt_simple_compile_test_code='sample MENU { MENUITEM "&Soup", 100, CHECKED }'
+
+# Code to be used in simple link tests
+lt_simple_link_test_code="$lt_simple_compile_test_code"
+
+# ltmain only uses $CC for tagged configurations so make sure $CC is set.
+_LT_TAG_COMPILER
+
+# save warnings/boilerplate of simple test code
+_LT_COMPILER_BOILERPLATE
+_LT_LINKER_BOILERPLATE
+
+# Allow CC to be a program name with arguments.
+lt_save_CC="$CC"
+lt_save_CFLAGS=$CFLAGS
+lt_save_GCC=$GCC
+GCC=
+CC=${RC-"windres"}
+CFLAGS=
+compiler=$CC
+_LT_TAGVAR(compiler, $1)=$CC
+_LT_CC_BASENAME([$compiler])
+_LT_TAGVAR(lt_cv_prog_compiler_c_o, $1)=yes
+
+if test -n "$compiler"; then
+  :
+  _LT_CONFIG($1)
+fi
+
+GCC=$lt_save_GCC
+AC_LANG_RESTORE
+CC=$lt_save_CC
+CFLAGS=$lt_save_CFLAGS
+])# _LT_LANG_RC_CONFIG
+
+
+# LT_PROG_GCJ
+# -----------
+AC_DEFUN([LT_PROG_GCJ],
+[m4_ifdef([AC_PROG_GCJ], [AC_PROG_GCJ],
+  [m4_ifdef([A][M_PROG_GCJ], [A][M_PROG_GCJ],
+    [AC_CHECK_TOOL(GCJ, gcj,)
+      test "x${GCJFLAGS+set}" = xset || GCJFLAGS="-g -O2"
+      AC_SUBST(GCJFLAGS)])])[]dnl
+])
+
+# Old name:
+AU_ALIAS([LT_AC_PROG_GCJ], [LT_PROG_GCJ])
+dnl aclocal-1.4 backwards compatibility:
+dnl AC_DEFUN([LT_AC_PROG_GCJ], [])
+
+
+# LT_PROG_GO
+# ----------
+AC_DEFUN([LT_PROG_GO],
+[AC_CHECK_TOOL(GOC, gccgo,)
+])
+
+
+# LT_PROG_RC
+# ----------
+AC_DEFUN([LT_PROG_RC],
+[AC_CHECK_TOOL(RC, windres,)
+])
+
+# Old name:
+AU_ALIAS([LT_AC_PROG_RC], [LT_PROG_RC])
+dnl aclocal-1.4 backwards compatibility:
+dnl AC_DEFUN([LT_AC_PROG_RC], [])
+
+
+# _LT_DECL_EGREP
+# --------------
+# If we don't have a new enough Autoconf to choose the best grep
+# available, choose the one first in the user's PATH.
+m4_defun([_LT_DECL_EGREP],
+[AC_REQUIRE([AC_PROG_EGREP])dnl
+AC_REQUIRE([AC_PROG_FGREP])dnl
+test -z "$GREP" && GREP=grep
+_LT_DECL([], [GREP], [1], [A grep program that handles long lines])
+_LT_DECL([], [EGREP], [1], [An ERE matcher])
+_LT_DECL([], [FGREP], [1], [A literal string matcher])
+dnl Non-bleeding-edge autoconf doesn't subst GREP, so do it here too
+AC_SUBST([GREP])
+])
+
+
+# _LT_DECL_OBJDUMP
+# --------------
+# If we don't have a new enough Autoconf to choose the best objdump
+# available, choose the one first in the user's PATH.
+m4_defun([_LT_DECL_OBJDUMP],
+[AC_CHECK_TOOL(OBJDUMP, objdump, false)
+test -z "$OBJDUMP" && OBJDUMP=objdump
+_LT_DECL([], [OBJDUMP], [1], [An object symbol dumper])
+AC_SUBST([OBJDUMP])
+])
+
+# _LT_DECL_DLLTOOL
+# ----------------
+# Ensure DLLTOOL variable is set.
+m4_defun([_LT_DECL_DLLTOOL],
+[AC_CHECK_TOOL(DLLTOOL, dlltool, false)
+test -z "$DLLTOOL" && DLLTOOL=dlltool
+_LT_DECL([], [DLLTOOL], [1], [DLL creation program])
+AC_SUBST([DLLTOOL])
+])
+
+# _LT_DECL_SED
+# ------------
+# Check for a fully-functional sed program, that truncates
+# as few characters as possible.  Prefer GNU sed if found.
+m4_defun([_LT_DECL_SED],
+[AC_PROG_SED
+test -z "$SED" && SED=sed
+Xsed="$SED -e 1s/^X//"
+_LT_DECL([], [SED], [1], [A sed program that does not truncate output])
+_LT_DECL([], [Xsed], ["\$SED -e 1s/^X//"],
+    [Sed that helps us avoid accidentally triggering echo(1) options like -n])
+])# _LT_DECL_SED
+
+m4_ifndef([AC_PROG_SED], [
+############################################################
+# NOTE: This macro has been submitted for inclusion into   #
+#  GNU Autoconf as AC_PROG_SED.  When it is available in   #
+#  a released version of Autoconf we should remove this    #
+#  macro and use it instead.                               #
+############################################################
+
+m4_defun([AC_PROG_SED],
+[AC_MSG_CHECKING([for a sed that does not truncate output])
+AC_CACHE_VAL(lt_cv_path_SED,
+[# Loop through the user's path and test for sed and gsed.
+# Then use that list of sed's as ones to test for truncation.
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for lt_ac_prog in sed gsed; do
+    for ac_exec_ext in '' $ac_executable_extensions; do
+      if $as_executable_p "$as_dir/$lt_ac_prog$ac_exec_ext"; then
+        lt_ac_sed_list="$lt_ac_sed_list $as_dir/$lt_ac_prog$ac_exec_ext"
+      fi
+    done
+  done
+done
+IFS=$as_save_IFS
+lt_ac_max=0
+lt_ac_count=0
+# Add /usr/xpg4/bin/sed as it is typically found on Solaris
+# along with /bin/sed that truncates output.
+for lt_ac_sed in $lt_ac_sed_list /usr/xpg4/bin/sed; do
+  test ! -f $lt_ac_sed && continue
+  cat /dev/null > conftest.in
+  lt_ac_count=0
+  echo $ECHO_N "0123456789$ECHO_C" >conftest.in
+  # Check for GNU sed and select it if it is found.
+  if "$lt_ac_sed" --version 2>&1 < /dev/null | grep 'GNU' > /dev/null; then
+    lt_cv_path_SED=$lt_ac_sed
+    break
+  fi
+  while true; do
+    cat conftest.in conftest.in >conftest.tmp
+    mv conftest.tmp conftest.in
+    cp conftest.in conftest.nl
+    echo >>conftest.nl
+    $lt_ac_sed -e 's/a$//' < conftest.nl >conftest.out || break
+    cmp -s conftest.out conftest.nl || break
+    # 10000 chars as input seems more than enough
+    test $lt_ac_count -gt 10 && break
+    lt_ac_count=`expr $lt_ac_count + 1`
+    if test $lt_ac_count -gt $lt_ac_max; then
+      lt_ac_max=$lt_ac_count
+      lt_cv_path_SED=$lt_ac_sed
+    fi
+  done
+done
+])
+SED=$lt_cv_path_SED
+AC_SUBST([SED])
+AC_MSG_RESULT([$SED])
+])#AC_PROG_SED
+])#m4_ifndef
+
+# Old name:
+AU_ALIAS([LT_AC_PROG_SED], [AC_PROG_SED])
+dnl aclocal-1.4 backwards compatibility:
+dnl AC_DEFUN([LT_AC_PROG_SED], [])
+
+
+# _LT_CHECK_SHELL_FEATURES
+# ------------------------
+# Find out whether the shell is Bourne or XSI compatible,
+# or has some other useful features.
+m4_defun([_LT_CHECK_SHELL_FEATURES],
+[AC_MSG_CHECKING([whether the shell understands some XSI constructs])
+# Try some XSI features
+xsi_shell=no
+( _lt_dummy="a/b/c"
+  test "${_lt_dummy##*/},${_lt_dummy%/*},${_lt_dummy#??}"${_lt_dummy%"$_lt_dummy"}, \
+      = c,a/b,b/c, \
+    && eval 'test $(( 1 + 1 )) -eq 2 \
+    && test "${#_lt_dummy}" -eq 5' ) >/dev/null 2>&1 \
+  && xsi_shell=yes
+AC_MSG_RESULT([$xsi_shell])
+_LT_CONFIG_LIBTOOL_INIT([xsi_shell='$xsi_shell'])
+
+AC_MSG_CHECKING([whether the shell understands "+="])
+lt_shell_append=no
+( foo=bar; set foo baz; eval "$[1]+=\$[2]" && test "$foo" = barbaz ) \
+    >/dev/null 2>&1 \
+  && lt_shell_append=yes
+AC_MSG_RESULT([$lt_shell_append])
+_LT_CONFIG_LIBTOOL_INIT([lt_shell_append='$lt_shell_append'])
+
+if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then
+  lt_unset=unset
+else
+  lt_unset=false
+fi
+_LT_DECL([], [lt_unset], [0], [whether the shell understands "unset"])dnl
+
+# test EBCDIC or ASCII
+case `echo X|tr X '\101'` in
+ A) # ASCII based system
+    # \n is not interpreted correctly by Solaris 8 /usr/ucb/tr
+  lt_SP2NL='tr \040 \012'
+  lt_NL2SP='tr \015\012 \040\040'
+  ;;
+ *) # EBCDIC based system
+  lt_SP2NL='tr \100 \n'
+  lt_NL2SP='tr \r\n \100\100'
+  ;;
+esac
+_LT_DECL([SP2NL], [lt_SP2NL], [1], [turn spaces into newlines])dnl
+_LT_DECL([NL2SP], [lt_NL2SP], [1], [turn newlines into spaces])dnl
+])# _LT_CHECK_SHELL_FEATURES
+
+
+# _LT_PROG_FUNCTION_REPLACE (FUNCNAME, REPLACEMENT-BODY)
+# ------------------------------------------------------
+# In `$cfgfile', look for function FUNCNAME delimited by `^FUNCNAME ()$' and
+# '^} FUNCNAME ', and replace its body with REPLACEMENT-BODY.
+m4_defun([_LT_PROG_FUNCTION_REPLACE],
+[dnl {
+sed -e '/^$1 ()$/,/^} # $1 /c\
+$1 ()\
+{\
+m4_bpatsubsts([$2], [$], [\\], [^\([	 ]\)], [\\\1])
+} # Extended-shell $1 implementation' "$cfgfile" > $cfgfile.tmp \
+  && mv -f "$cfgfile.tmp" "$cfgfile" \
+    || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp")
+test 0 -eq $? || _lt_function_replace_fail=:
+])
+
+
+# _LT_PROG_REPLACE_SHELLFNS
+# -------------------------
+# Replace existing portable implementations of several shell functions with
+# equivalent extended shell implementations where those features are available..
+m4_defun([_LT_PROG_REPLACE_SHELLFNS],
+[if test x"$xsi_shell" = xyes; then
+  _LT_PROG_FUNCTION_REPLACE([func_dirname], [dnl
+    case ${1} in
+      */*) func_dirname_result="${1%/*}${2}" ;;
+      *  ) func_dirname_result="${3}" ;;
+    esac])
+
+  _LT_PROG_FUNCTION_REPLACE([func_basename], [dnl
+    func_basename_result="${1##*/}"])
+
+  _LT_PROG_FUNCTION_REPLACE([func_dirname_and_basename], [dnl
+    case ${1} in
+      */*) func_dirname_result="${1%/*}${2}" ;;
+      *  ) func_dirname_result="${3}" ;;
+    esac
+    func_basename_result="${1##*/}"])
+
+  _LT_PROG_FUNCTION_REPLACE([func_stripname], [dnl
+    # pdksh 5.2.14 does not do ${X%$Y} correctly if both X and Y are
+    # positional parameters, so assign one to ordinary parameter first.
+    func_stripname_result=${3}
+    func_stripname_result=${func_stripname_result#"${1}"}
+    func_stripname_result=${func_stripname_result%"${2}"}])
+
+  _LT_PROG_FUNCTION_REPLACE([func_split_long_opt], [dnl
+    func_split_long_opt_name=${1%%=*}
+    func_split_long_opt_arg=${1#*=}])
+
+  _LT_PROG_FUNCTION_REPLACE([func_split_short_opt], [dnl
+    func_split_short_opt_arg=${1#??}
+    func_split_short_opt_name=${1%"$func_split_short_opt_arg"}])
+
+  _LT_PROG_FUNCTION_REPLACE([func_lo2o], [dnl
+    case ${1} in
+      *.lo) func_lo2o_result=${1%.lo}.${objext} ;;
+      *)    func_lo2o_result=${1} ;;
+    esac])
+
+  _LT_PROG_FUNCTION_REPLACE([func_xform], [    func_xform_result=${1%.*}.lo])
+
+  _LT_PROG_FUNCTION_REPLACE([func_arith], [    func_arith_result=$(( $[*] ))])
+
+  _LT_PROG_FUNCTION_REPLACE([func_len], [    func_len_result=${#1}])
+fi
+
+if test x"$lt_shell_append" = xyes; then
+  _LT_PROG_FUNCTION_REPLACE([func_append], [    eval "${1}+=\\${2}"])
+
+  _LT_PROG_FUNCTION_REPLACE([func_append_quoted], [dnl
+    func_quote_for_eval "${2}"
+dnl m4 expansion turns \\\\ into \\, and then the shell eval turns that into \
+    eval "${1}+=\\\\ \\$func_quote_for_eval_result"])
+
+  # Save a `func_append' function call where possible by direct use of '+='
+  sed -e 's%func_append \([[a-zA-Z_]]\{1,\}\) "%\1+="%g' $cfgfile > $cfgfile.tmp \
+    && mv -f "$cfgfile.tmp" "$cfgfile" \
+      || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp")
+  test 0 -eq $? || _lt_function_replace_fail=:
+else
+  # Save a `func_append' function call even when '+=' is not available
+  sed -e 's%func_append \([[a-zA-Z_]]\{1,\}\) "%\1="$\1%g' $cfgfile > $cfgfile.tmp \
+    && mv -f "$cfgfile.tmp" "$cfgfile" \
+      || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp")
+  test 0 -eq $? || _lt_function_replace_fail=:
+fi
+
+if test x"$_lt_function_replace_fail" = x":"; then
+  AC_MSG_WARN([Unable to substitute extended shell functions in $ofile])
+fi
+])
+
+# _LT_PATH_CONVERSION_FUNCTIONS
+# -----------------------------
+# Determine which file name conversion functions should be used by
+# func_to_host_file (and, implicitly, by func_to_host_path).  These are needed
+# for certain cross-compile configurations and native mingw.
+m4_defun([_LT_PATH_CONVERSION_FUNCTIONS],
+[AC_REQUIRE([AC_CANONICAL_HOST])dnl
+AC_REQUIRE([AC_CANONICAL_BUILD])dnl
+AC_MSG_CHECKING([how to convert $build file names to $host format])
+AC_CACHE_VAL(lt_cv_to_host_file_cmd,
+[case $host in
+  *-*-mingw* )
+    case $build in
+      *-*-mingw* ) # actually msys
+        lt_cv_to_host_file_cmd=func_convert_file_msys_to_w32
+        ;;
+      *-*-cygwin* )
+        lt_cv_to_host_file_cmd=func_convert_file_cygwin_to_w32
+        ;;
+      * ) # otherwise, assume *nix
+        lt_cv_to_host_file_cmd=func_convert_file_nix_to_w32
+        ;;
+    esac
+    ;;
+  *-*-cygwin* )
+    case $build in
+      *-*-mingw* ) # actually msys
+        lt_cv_to_host_file_cmd=func_convert_file_msys_to_cygwin
+        ;;
+      *-*-cygwin* )
+        lt_cv_to_host_file_cmd=func_convert_file_noop
+        ;;
+      * ) # otherwise, assume *nix
+        lt_cv_to_host_file_cmd=func_convert_file_nix_to_cygwin
+        ;;
+    esac
+    ;;
+  * ) # unhandled hosts (and "normal" native builds)
+    lt_cv_to_host_file_cmd=func_convert_file_noop
+    ;;
+esac
+])
+to_host_file_cmd=$lt_cv_to_host_file_cmd
+AC_MSG_RESULT([$lt_cv_to_host_file_cmd])
+_LT_DECL([to_host_file_cmd], [lt_cv_to_host_file_cmd],
+         [0], [convert $build file names to $host format])dnl
+
+AC_MSG_CHECKING([how to convert $build file names to toolchain format])
+AC_CACHE_VAL(lt_cv_to_tool_file_cmd,
+[#assume ordinary cross tools, or native build.
+lt_cv_to_tool_file_cmd=func_convert_file_noop
+case $host in
+  *-*-mingw* )
+    case $build in
+      *-*-mingw* ) # actually msys
+        lt_cv_to_tool_file_cmd=func_convert_file_msys_to_w32
+        ;;
+    esac
+    ;;
+esac
+])
+to_tool_file_cmd=$lt_cv_to_tool_file_cmd
+AC_MSG_RESULT([$lt_cv_to_tool_file_cmd])
+_LT_DECL([to_tool_file_cmd], [lt_cv_to_tool_file_cmd],
+         [0], [convert $build files to toolchain format])dnl
+])# _LT_PATH_CONVERSION_FUNCTIONS
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ltoptions.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ltoptions.m4
new file mode 100644
index 0000000..5d9acd8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ltoptions.m4
@@ -0,0 +1,384 @@
+# Helper functions for option handling.                    -*- Autoconf -*-
+#
+#   Copyright (C) 2004, 2005, 2007, 2008, 2009 Free Software Foundation,
+#   Inc.
+#   Written by Gary V. Vaughan, 2004
+#
+# This file is free software; the Free Software Foundation gives
+# unlimited permission to copy and/or distribute it, with or without
+# modifications, as long as this notice is preserved.
+
+# serial 7 ltoptions.m4
+
+# This is to help aclocal find these macros, as it can't see m4_define.
+AC_DEFUN([LTOPTIONS_VERSION], [m4_if([1])])
+
+
+# _LT_MANGLE_OPTION(MACRO-NAME, OPTION-NAME)
+# ------------------------------------------
+m4_define([_LT_MANGLE_OPTION],
+[[_LT_OPTION_]m4_bpatsubst($1__$2, [[^a-zA-Z0-9_]], [_])])
+
+
+# _LT_SET_OPTION(MACRO-NAME, OPTION-NAME)
+# ---------------------------------------
+# Set option OPTION-NAME for macro MACRO-NAME, and if there is a
+# matching handler defined, dispatch to it.  Other OPTION-NAMEs are
+# saved as a flag.
+m4_define([_LT_SET_OPTION],
+[m4_define(_LT_MANGLE_OPTION([$1], [$2]))dnl
+m4_ifdef(_LT_MANGLE_DEFUN([$1], [$2]),
+        _LT_MANGLE_DEFUN([$1], [$2]),
+    [m4_warning([Unknown $1 option `$2'])])[]dnl
+])
+
+
+# _LT_IF_OPTION(MACRO-NAME, OPTION-NAME, IF-SET, [IF-NOT-SET])
+# ------------------------------------------------------------
+# Execute IF-SET if OPTION is set, IF-NOT-SET otherwise.
+m4_define([_LT_IF_OPTION],
+[m4_ifdef(_LT_MANGLE_OPTION([$1], [$2]), [$3], [$4])])
+
+
+# _LT_UNLESS_OPTIONS(MACRO-NAME, OPTION-LIST, IF-NOT-SET)
+# -------------------------------------------------------
+# Execute IF-NOT-SET unless all options in OPTION-LIST for MACRO-NAME
+# are set.
+m4_define([_LT_UNLESS_OPTIONS],
+[m4_foreach([_LT_Option], m4_split(m4_normalize([$2])),
+	    [m4_ifdef(_LT_MANGLE_OPTION([$1], _LT_Option),
+		      [m4_define([$0_found])])])[]dnl
+m4_ifdef([$0_found], [m4_undefine([$0_found])], [$3
+])[]dnl
+])
+
+
+# _LT_SET_OPTIONS(MACRO-NAME, OPTION-LIST)
+# ----------------------------------------
+# OPTION-LIST is a space-separated list of Libtool options associated
+# with MACRO-NAME.  If any OPTION has a matching handler declared with
+# LT_OPTION_DEFINE, dispatch to that macro; otherwise complain about
+# the unknown option and exit.
+m4_defun([_LT_SET_OPTIONS],
+[# Set options
+m4_foreach([_LT_Option], m4_split(m4_normalize([$2])),
+    [_LT_SET_OPTION([$1], _LT_Option)])
+
+m4_if([$1],[LT_INIT],[
+  dnl
+  dnl Simply set some default values (i.e off) if boolean options were not
+  dnl specified:
+  _LT_UNLESS_OPTIONS([LT_INIT], [dlopen], [enable_dlopen=no
+  ])
+  _LT_UNLESS_OPTIONS([LT_INIT], [win32-dll], [enable_win32_dll=no
+  ])
+  dnl
+  dnl If no reference was made to various pairs of opposing options, then
+  dnl we run the default mode handler for the pair.  For example, if neither
+  dnl `shared' nor `disable-shared' was passed, we enable building of shared
+  dnl archives by default:
+  _LT_UNLESS_OPTIONS([LT_INIT], [shared disable-shared], [_LT_ENABLE_SHARED])
+  _LT_UNLESS_OPTIONS([LT_INIT], [static disable-static], [_LT_ENABLE_STATIC])
+  _LT_UNLESS_OPTIONS([LT_INIT], [pic-only no-pic], [_LT_WITH_PIC])
+  _LT_UNLESS_OPTIONS([LT_INIT], [fast-install disable-fast-install],
+  		   [_LT_ENABLE_FAST_INSTALL])
+  ])
+])# _LT_SET_OPTIONS
+
+
+## --------------------------------- ##
+## Macros to handle LT_INIT options. ##
+## --------------------------------- ##
+
+# _LT_MANGLE_DEFUN(MACRO-NAME, OPTION-NAME)
+# -----------------------------------------
+m4_define([_LT_MANGLE_DEFUN],
+[[_LT_OPTION_DEFUN_]m4_bpatsubst(m4_toupper([$1__$2]), [[^A-Z0-9_]], [_])])
+
+
+# LT_OPTION_DEFINE(MACRO-NAME, OPTION-NAME, CODE)
+# -----------------------------------------------
+m4_define([LT_OPTION_DEFINE],
+[m4_define(_LT_MANGLE_DEFUN([$1], [$2]), [$3])[]dnl
+])# LT_OPTION_DEFINE
+
+
+# dlopen
+# ------
+LT_OPTION_DEFINE([LT_INIT], [dlopen], [enable_dlopen=yes
+])
+
+AU_DEFUN([AC_LIBTOOL_DLOPEN],
+[_LT_SET_OPTION([LT_INIT], [dlopen])
+AC_DIAGNOSE([obsolete],
+[$0: Remove this warning and the call to _LT_SET_OPTION when you
+put the `dlopen' option into LT_INIT's first parameter.])
+])
+
+dnl aclocal-1.4 backwards compatibility:
+dnl AC_DEFUN([AC_LIBTOOL_DLOPEN], [])
+
+
+# win32-dll
+# ---------
+# Declare package support for building win32 dll's.
+LT_OPTION_DEFINE([LT_INIT], [win32-dll],
+[enable_win32_dll=yes
+
+case $host in
+*-*-cygwin* | *-*-mingw* | *-*-pw32* | *-*-cegcc*)
+  AC_CHECK_TOOL(AS, as, false)
+  AC_CHECK_TOOL(DLLTOOL, dlltool, false)
+  AC_CHECK_TOOL(OBJDUMP, objdump, false)
+  ;;
+esac
+
+test -z "$AS" && AS=as
+_LT_DECL([], [AS],      [1], [Assembler program])dnl
+
+test -z "$DLLTOOL" && DLLTOOL=dlltool
+_LT_DECL([], [DLLTOOL], [1], [DLL creation program])dnl
+
+test -z "$OBJDUMP" && OBJDUMP=objdump
+_LT_DECL([], [OBJDUMP], [1], [Object dumper program])dnl
+])# win32-dll
+
+AU_DEFUN([AC_LIBTOOL_WIN32_DLL],
+[AC_REQUIRE([AC_CANONICAL_HOST])dnl
+_LT_SET_OPTION([LT_INIT], [win32-dll])
+AC_DIAGNOSE([obsolete],
+[$0: Remove this warning and the call to _LT_SET_OPTION when you
+put the `win32-dll' option into LT_INIT's first parameter.])
+])
+
+dnl aclocal-1.4 backwards compatibility:
+dnl AC_DEFUN([AC_LIBTOOL_WIN32_DLL], [])
+
+
+# _LT_ENABLE_SHARED([DEFAULT])
+# ----------------------------
+# implement the --enable-shared flag, and supports the `shared' and
+# `disable-shared' LT_INIT options.
+# DEFAULT is either `yes' or `no'.  If omitted, it defaults to `yes'.
+m4_define([_LT_ENABLE_SHARED],
+[m4_define([_LT_ENABLE_SHARED_DEFAULT], [m4_if($1, no, no, yes)])dnl
+AC_ARG_ENABLE([shared],
+    [AS_HELP_STRING([--enable-shared@<:@=PKGS@:>@],
+	[build shared libraries @<:@default=]_LT_ENABLE_SHARED_DEFAULT[@:>@])],
+    [p=${PACKAGE-default}
+    case $enableval in
+    yes) enable_shared=yes ;;
+    no) enable_shared=no ;;
+    *)
+      enable_shared=no
+      # Look at the argument we got.  We use all the common list separators.
+      lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR,"
+      for pkg in $enableval; do
+	IFS="$lt_save_ifs"
+	if test "X$pkg" = "X$p"; then
+	  enable_shared=yes
+	fi
+      done
+      IFS="$lt_save_ifs"
+      ;;
+    esac],
+    [enable_shared=]_LT_ENABLE_SHARED_DEFAULT)
+
+    _LT_DECL([build_libtool_libs], [enable_shared], [0],
+	[Whether or not to build shared libraries])
+])# _LT_ENABLE_SHARED
+
+LT_OPTION_DEFINE([LT_INIT], [shared], [_LT_ENABLE_SHARED([yes])])
+LT_OPTION_DEFINE([LT_INIT], [disable-shared], [_LT_ENABLE_SHARED([no])])
+
+# Old names:
+AC_DEFUN([AC_ENABLE_SHARED],
+[_LT_SET_OPTION([LT_INIT], m4_if([$1], [no], [disable-])[shared])
+])
+
+AC_DEFUN([AC_DISABLE_SHARED],
+[_LT_SET_OPTION([LT_INIT], [disable-shared])
+])
+
+AU_DEFUN([AM_ENABLE_SHARED], [AC_ENABLE_SHARED($@)])
+AU_DEFUN([AM_DISABLE_SHARED], [AC_DISABLE_SHARED($@)])
+
+dnl aclocal-1.4 backwards compatibility:
+dnl AC_DEFUN([AM_ENABLE_SHARED], [])
+dnl AC_DEFUN([AM_DISABLE_SHARED], [])
+
+
+
+# _LT_ENABLE_STATIC([DEFAULT])
+# ----------------------------
+# implement the --enable-static flag, and support the `static' and
+# `disable-static' LT_INIT options.
+# DEFAULT is either `yes' or `no'.  If omitted, it defaults to `yes'.
+m4_define([_LT_ENABLE_STATIC],
+[m4_define([_LT_ENABLE_STATIC_DEFAULT], [m4_if($1, no, no, yes)])dnl
+AC_ARG_ENABLE([static],
+    [AS_HELP_STRING([--enable-static@<:@=PKGS@:>@],
+	[build static libraries @<:@default=]_LT_ENABLE_STATIC_DEFAULT[@:>@])],
+    [p=${PACKAGE-default}
+    case $enableval in
+    yes) enable_static=yes ;;
+    no) enable_static=no ;;
+    *)
+     enable_static=no
+      # Look at the argument we got.  We use all the common list separators.
+      lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR,"
+      for pkg in $enableval; do
+	IFS="$lt_save_ifs"
+	if test "X$pkg" = "X$p"; then
+	  enable_static=yes
+	fi
+      done
+      IFS="$lt_save_ifs"
+      ;;
+    esac],
+    [enable_static=]_LT_ENABLE_STATIC_DEFAULT)
+
+    _LT_DECL([build_old_libs], [enable_static], [0],
+	[Whether or not to build static libraries])
+])# _LT_ENABLE_STATIC
+
+LT_OPTION_DEFINE([LT_INIT], [static], [_LT_ENABLE_STATIC([yes])])
+LT_OPTION_DEFINE([LT_INIT], [disable-static], [_LT_ENABLE_STATIC([no])])
+
+# Old names:
+AC_DEFUN([AC_ENABLE_STATIC],
+[_LT_SET_OPTION([LT_INIT], m4_if([$1], [no], [disable-])[static])
+])
+
+AC_DEFUN([AC_DISABLE_STATIC],
+[_LT_SET_OPTION([LT_INIT], [disable-static])
+])
+
+AU_DEFUN([AM_ENABLE_STATIC], [AC_ENABLE_STATIC($@)])
+AU_DEFUN([AM_DISABLE_STATIC], [AC_DISABLE_STATIC($@)])
+
+dnl aclocal-1.4 backwards compatibility:
+dnl AC_DEFUN([AM_ENABLE_STATIC], [])
+dnl AC_DEFUN([AM_DISABLE_STATIC], [])
+
+
+
+# _LT_ENABLE_FAST_INSTALL([DEFAULT])
+# ----------------------------------
+# implement the --enable-fast-install flag, and support the `fast-install'
+# and `disable-fast-install' LT_INIT options.
+# DEFAULT is either `yes' or `no'.  If omitted, it defaults to `yes'.
+m4_define([_LT_ENABLE_FAST_INSTALL],
+[m4_define([_LT_ENABLE_FAST_INSTALL_DEFAULT], [m4_if($1, no, no, yes)])dnl
+AC_ARG_ENABLE([fast-install],
+    [AS_HELP_STRING([--enable-fast-install@<:@=PKGS@:>@],
+    [optimize for fast installation @<:@default=]_LT_ENABLE_FAST_INSTALL_DEFAULT[@:>@])],
+    [p=${PACKAGE-default}
+    case $enableval in
+    yes) enable_fast_install=yes ;;
+    no) enable_fast_install=no ;;
+    *)
+      enable_fast_install=no
+      # Look at the argument we got.  We use all the common list separators.
+      lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR,"
+      for pkg in $enableval; do
+	IFS="$lt_save_ifs"
+	if test "X$pkg" = "X$p"; then
+	  enable_fast_install=yes
+	fi
+      done
+      IFS="$lt_save_ifs"
+      ;;
+    esac],
+    [enable_fast_install=]_LT_ENABLE_FAST_INSTALL_DEFAULT)
+
+_LT_DECL([fast_install], [enable_fast_install], [0],
+	 [Whether or not to optimize for fast installation])dnl
+])# _LT_ENABLE_FAST_INSTALL
+
+LT_OPTION_DEFINE([LT_INIT], [fast-install], [_LT_ENABLE_FAST_INSTALL([yes])])
+LT_OPTION_DEFINE([LT_INIT], [disable-fast-install], [_LT_ENABLE_FAST_INSTALL([no])])
+
+# Old names:
+AU_DEFUN([AC_ENABLE_FAST_INSTALL],
+[_LT_SET_OPTION([LT_INIT], m4_if([$1], [no], [disable-])[fast-install])
+AC_DIAGNOSE([obsolete],
+[$0: Remove this warning and the call to _LT_SET_OPTION when you put
+the `fast-install' option into LT_INIT's first parameter.])
+])
+
+AU_DEFUN([AC_DISABLE_FAST_INSTALL],
+[_LT_SET_OPTION([LT_INIT], [disable-fast-install])
+AC_DIAGNOSE([obsolete],
+[$0: Remove this warning and the call to _LT_SET_OPTION when you put
+the `disable-fast-install' option into LT_INIT's first parameter.])
+])
+
+dnl aclocal-1.4 backwards compatibility:
+dnl AC_DEFUN([AC_ENABLE_FAST_INSTALL], [])
+dnl AC_DEFUN([AM_DISABLE_FAST_INSTALL], [])
+
+
+# _LT_WITH_PIC([MODE])
+# --------------------
+# implement the --with-pic flag, and support the `pic-only' and `no-pic'
+# LT_INIT options.
+# MODE is either `yes' or `no'.  If omitted, it defaults to `both'.
+m4_define([_LT_WITH_PIC],
+[AC_ARG_WITH([pic],
+    [AS_HELP_STRING([--with-pic@<:@=PKGS@:>@],
+	[try to use only PIC/non-PIC objects @<:@default=use both@:>@])],
+    [lt_p=${PACKAGE-default}
+    case $withval in
+    yes|no) pic_mode=$withval ;;
+    *)
+      pic_mode=default
+      # Look at the argument we got.  We use all the common list separators.
+      lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR,"
+      for lt_pkg in $withval; do
+	IFS="$lt_save_ifs"
+	if test "X$lt_pkg" = "X$lt_p"; then
+	  pic_mode=yes
+	fi
+      done
+      IFS="$lt_save_ifs"
+      ;;
+    esac],
+    [pic_mode=default])
+
+test -z "$pic_mode" && pic_mode=m4_default([$1], [default])
+
+_LT_DECL([], [pic_mode], [0], [What type of objects to build])dnl
+])# _LT_WITH_PIC
+
+LT_OPTION_DEFINE([LT_INIT], [pic-only], [_LT_WITH_PIC([yes])])
+LT_OPTION_DEFINE([LT_INIT], [no-pic], [_LT_WITH_PIC([no])])
+
+# Old name:
+AU_DEFUN([AC_LIBTOOL_PICMODE],
+[_LT_SET_OPTION([LT_INIT], [pic-only])
+AC_DIAGNOSE([obsolete],
+[$0: Remove this warning and the call to _LT_SET_OPTION when you
+put the `pic-only' option into LT_INIT's first parameter.])
+])
+
+dnl aclocal-1.4 backwards compatibility:
+dnl AC_DEFUN([AC_LIBTOOL_PICMODE], [])
+
+## ----------------- ##
+## LTDL_INIT Options ##
+## ----------------- ##
+
+m4_define([_LTDL_MODE], [])
+LT_OPTION_DEFINE([LTDL_INIT], [nonrecursive],
+		 [m4_define([_LTDL_MODE], [nonrecursive])])
+LT_OPTION_DEFINE([LTDL_INIT], [recursive],
+		 [m4_define([_LTDL_MODE], [recursive])])
+LT_OPTION_DEFINE([LTDL_INIT], [subproject],
+		 [m4_define([_LTDL_MODE], [subproject])])
+
+m4_define([_LTDL_TYPE], [])
+LT_OPTION_DEFINE([LTDL_INIT], [installable],
+		 [m4_define([_LTDL_TYPE], [installable])])
+LT_OPTION_DEFINE([LTDL_INIT], [convenience],
+		 [m4_define([_LTDL_TYPE], [convenience])])
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ltsugar.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ltsugar.m4
new file mode 100644
index 0000000..9000a05
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ltsugar.m4
@@ -0,0 +1,123 @@
+# ltsugar.m4 -- libtool m4 base layer.                         -*-Autoconf-*-
+#
+# Copyright (C) 2004, 2005, 2007, 2008 Free Software Foundation, Inc.
+# Written by Gary V. Vaughan, 2004
+#
+# This file is free software; the Free Software Foundation gives
+# unlimited permission to copy and/or distribute it, with or without
+# modifications, as long as this notice is preserved.
+
+# serial 6 ltsugar.m4
+
+# This is to help aclocal find these macros, as it can't see m4_define.
+AC_DEFUN([LTSUGAR_VERSION], [m4_if([0.1])])
+
+
+# lt_join(SEP, ARG1, [ARG2...])
+# -----------------------------
+# Produce ARG1SEPARG2...SEPARGn, omitting [] arguments and their
+# associated separator.
+# Needed until we can rely on m4_join from Autoconf 2.62, since all earlier
+# versions in m4sugar had bugs.
+m4_define([lt_join],
+[m4_if([$#], [1], [],
+       [$#], [2], [[$2]],
+       [m4_if([$2], [], [], [[$2]_])$0([$1], m4_shift(m4_shift($@)))])])
+m4_define([_lt_join],
+[m4_if([$#$2], [2], [],
+       [m4_if([$2], [], [], [[$1$2]])$0([$1], m4_shift(m4_shift($@)))])])
+
+
+# lt_car(LIST)
+# lt_cdr(LIST)
+# ------------
+# Manipulate m4 lists.
+# These macros are necessary as long as will still need to support
+# Autoconf-2.59 which quotes differently.
+m4_define([lt_car], [[$1]])
+m4_define([lt_cdr],
+[m4_if([$#], 0, [m4_fatal([$0: cannot be called without arguments])],
+       [$#], 1, [],
+       [m4_dquote(m4_shift($@))])])
+m4_define([lt_unquote], $1)
+
+
+# lt_append(MACRO-NAME, STRING, [SEPARATOR])
+# ------------------------------------------
+# Redefine MACRO-NAME to hold its former content plus `SEPARATOR'`STRING'.
+# Note that neither SEPARATOR nor STRING are expanded; they are appended
+# to MACRO-NAME as is (leaving the expansion for when MACRO-NAME is invoked).
+# No SEPARATOR is output if MACRO-NAME was previously undefined (different
+# than defined and empty).
+#
+# This macro is needed until we can rely on Autoconf 2.62, since earlier
+# versions of m4sugar mistakenly expanded SEPARATOR but not STRING.
+m4_define([lt_append],
+[m4_define([$1],
+	   m4_ifdef([$1], [m4_defn([$1])[$3]])[$2])])
+
+
+
+# lt_combine(SEP, PREFIX-LIST, INFIX, SUFFIX1, [SUFFIX2...])
+# ----------------------------------------------------------
+# Produce a SEP delimited list of all paired combinations of elements of
+# PREFIX-LIST with SUFFIX1 through SUFFIXn.  Each element of the list
+# has the form PREFIXmINFIXSUFFIXn.
+# Needed until we can rely on m4_combine added in Autoconf 2.62.
+m4_define([lt_combine],
+[m4_if(m4_eval([$# > 3]), [1],
+       [m4_pushdef([_Lt_sep], [m4_define([_Lt_sep], m4_defn([lt_car]))])]]dnl
+[[m4_foreach([_Lt_prefix], [$2],
+	     [m4_foreach([_Lt_suffix],
+		]m4_dquote(m4_dquote(m4_shift(m4_shift(m4_shift($@)))))[,
+	[_Lt_sep([$1])[]m4_defn([_Lt_prefix])[$3]m4_defn([_Lt_suffix])])])])])
+
+
+# lt_if_append_uniq(MACRO-NAME, VARNAME, [SEPARATOR], [UNIQ], [NOT-UNIQ])
+# -----------------------------------------------------------------------
+# Iff MACRO-NAME does not yet contain VARNAME, then append it (delimited
+# by SEPARATOR if supplied) and expand UNIQ, else NOT-UNIQ.
+m4_define([lt_if_append_uniq],
+[m4_ifdef([$1],
+	  [m4_if(m4_index([$3]m4_defn([$1])[$3], [$3$2$3]), [-1],
+		 [lt_append([$1], [$2], [$3])$4],
+		 [$5])],
+	  [lt_append([$1], [$2], [$3])$4])])
+
+
+# lt_dict_add(DICT, KEY, VALUE)
+# -----------------------------
+m4_define([lt_dict_add],
+[m4_define([$1($2)], [$3])])
+
+
+# lt_dict_add_subkey(DICT, KEY, SUBKEY, VALUE)
+# --------------------------------------------
+m4_define([lt_dict_add_subkey],
+[m4_define([$1($2:$3)], [$4])])
+
+
+# lt_dict_fetch(DICT, KEY, [SUBKEY])
+# ----------------------------------
+m4_define([lt_dict_fetch],
+[m4_ifval([$3],
+	m4_ifdef([$1($2:$3)], [m4_defn([$1($2:$3)])]),
+    m4_ifdef([$1($2)], [m4_defn([$1($2)])]))])
+
+
+# lt_if_dict_fetch(DICT, KEY, [SUBKEY], VALUE, IF-TRUE, [IF-FALSE])
+# -----------------------------------------------------------------
+m4_define([lt_if_dict_fetch],
+[m4_if(lt_dict_fetch([$1], [$2], [$3]), [$4],
+	[$5],
+    [$6])])
+
+
+# lt_dict_filter(DICT, [SUBKEY], VALUE, [SEPARATOR], KEY, [...])
+# --------------------------------------------------------------
+m4_define([lt_dict_filter],
+[m4_if([$5], [], [],
+  [lt_join(m4_quote(m4_default([$4], [[, ]])),
+           lt_unquote(m4_split(m4_normalize(m4_foreach(_Lt_key, lt_car([m4_shiftn(4, $@)]),
+		      [lt_if_dict_fetch([$1], _Lt_key, [$2], [$3], [_Lt_key ])])))))])[]dnl
+])
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ltversion.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ltversion.m4
new file mode 100644
index 0000000..07a8602
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/ltversion.m4
@@ -0,0 +1,23 @@
+# ltversion.m4 -- version numbers			-*- Autoconf -*-
+#
+#   Copyright (C) 2004 Free Software Foundation, Inc.
+#   Written by Scott James Remnant, 2004
+#
+# This file is free software; the Free Software Foundation gives
+# unlimited permission to copy and/or distribute it, with or without
+# modifications, as long as this notice is preserved.
+
+# @configure_input@
+
+# serial 3337 ltversion.m4
+# This file is part of GNU Libtool
+
+m4_define([LT_PACKAGE_VERSION], [2.4.2])
+m4_define([LT_PACKAGE_REVISION], [1.3337])
+
+AC_DEFUN([LTVERSION_VERSION],
+[macro_version='2.4.2'
+macro_revision='1.3337'
+_LT_DECL(, macro_version, 0, [Which release of libtool.m4 was used?])
+_LT_DECL(, macro_revision, 0)
+])
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/lt~obsolete.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/lt~obsolete.m4
new file mode 100644
index 0000000..c573da9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/lt~obsolete.m4
@@ -0,0 +1,98 @@
+# lt~obsolete.m4 -- aclocal satisfying obsolete definitions.    -*-Autoconf-*-
+#
+#   Copyright (C) 2004, 2005, 2007, 2009 Free Software Foundation, Inc.
+#   Written by Scott James Remnant, 2004.
+#
+# This file is free software; the Free Software Foundation gives
+# unlimited permission to copy and/or distribute it, with or without
+# modifications, as long as this notice is preserved.
+
+# serial 5 lt~obsolete.m4
+
+# These exist entirely to fool aclocal when bootstrapping libtool.
+#
+# In the past libtool.m4 has provided macros via AC_DEFUN (or AU_DEFUN)
+# which have later been changed to m4_define as they aren't part of the
+# exported API, or moved to Autoconf or Automake where they belong.
+#
+# The trouble is, aclocal is a bit thick.  It'll see the old AC_DEFUN
+# in /usr/share/aclocal/libtool.m4 and remember it, then when it sees us
+# using a macro with the same name in our local m4/libtool.m4 it'll
+# pull the old libtool.m4 in (it doesn't see our shiny new m4_define
+# and doesn't know about Autoconf macros at all.)
+#
+# So we provide this file, which has a silly filename so it's always
+# included after everything else.  This provides aclocal with the
+# AC_DEFUNs it wants, but when m4 processes it, it doesn't do anything
+# because those macros already exist, or will be overwritten later.
+# We use AC_DEFUN over AU_DEFUN for compatibility with aclocal-1.6. 
+#
+# Anytime we withdraw an AC_DEFUN or AU_DEFUN, remember to add it here.
+# Yes, that means every name once taken will need to remain here until
+# we give up compatibility with versions before 1.7, at which point
+# we need to keep only those names which we still refer to.
+
+# This is to help aclocal find these macros, as it can't see m4_define.
+AC_DEFUN([LTOBSOLETE_VERSION], [m4_if([1])])
+
+m4_ifndef([AC_LIBTOOL_LINKER_OPTION],	[AC_DEFUN([AC_LIBTOOL_LINKER_OPTION])])
+m4_ifndef([AC_PROG_EGREP],		[AC_DEFUN([AC_PROG_EGREP])])
+m4_ifndef([_LT_AC_PROG_ECHO_BACKSLASH],	[AC_DEFUN([_LT_AC_PROG_ECHO_BACKSLASH])])
+m4_ifndef([_LT_AC_SHELL_INIT],		[AC_DEFUN([_LT_AC_SHELL_INIT])])
+m4_ifndef([_LT_AC_SYS_LIBPATH_AIX],	[AC_DEFUN([_LT_AC_SYS_LIBPATH_AIX])])
+m4_ifndef([_LT_PROG_LTMAIN],		[AC_DEFUN([_LT_PROG_LTMAIN])])
+m4_ifndef([_LT_AC_TAGVAR],		[AC_DEFUN([_LT_AC_TAGVAR])])
+m4_ifndef([AC_LTDL_ENABLE_INSTALL],	[AC_DEFUN([AC_LTDL_ENABLE_INSTALL])])
+m4_ifndef([AC_LTDL_PREOPEN],		[AC_DEFUN([AC_LTDL_PREOPEN])])
+m4_ifndef([_LT_AC_SYS_COMPILER],	[AC_DEFUN([_LT_AC_SYS_COMPILER])])
+m4_ifndef([_LT_AC_LOCK],		[AC_DEFUN([_LT_AC_LOCK])])
+m4_ifndef([AC_LIBTOOL_SYS_OLD_ARCHIVE],	[AC_DEFUN([AC_LIBTOOL_SYS_OLD_ARCHIVE])])
+m4_ifndef([_LT_AC_TRY_DLOPEN_SELF],	[AC_DEFUN([_LT_AC_TRY_DLOPEN_SELF])])
+m4_ifndef([AC_LIBTOOL_PROG_CC_C_O],	[AC_DEFUN([AC_LIBTOOL_PROG_CC_C_O])])
+m4_ifndef([AC_LIBTOOL_SYS_HARD_LINK_LOCKS], [AC_DEFUN([AC_LIBTOOL_SYS_HARD_LINK_LOCKS])])
+m4_ifndef([AC_LIBTOOL_OBJDIR],		[AC_DEFUN([AC_LIBTOOL_OBJDIR])])
+m4_ifndef([AC_LTDL_OBJDIR],		[AC_DEFUN([AC_LTDL_OBJDIR])])
+m4_ifndef([AC_LIBTOOL_PROG_LD_HARDCODE_LIBPATH], [AC_DEFUN([AC_LIBTOOL_PROG_LD_HARDCODE_LIBPATH])])
+m4_ifndef([AC_LIBTOOL_SYS_LIB_STRIP],	[AC_DEFUN([AC_LIBTOOL_SYS_LIB_STRIP])])
+m4_ifndef([AC_PATH_MAGIC],		[AC_DEFUN([AC_PATH_MAGIC])])
+m4_ifndef([AC_PROG_LD_GNU],		[AC_DEFUN([AC_PROG_LD_GNU])])
+m4_ifndef([AC_PROG_LD_RELOAD_FLAG],	[AC_DEFUN([AC_PROG_LD_RELOAD_FLAG])])
+m4_ifndef([AC_DEPLIBS_CHECK_METHOD],	[AC_DEFUN([AC_DEPLIBS_CHECK_METHOD])])
+m4_ifndef([AC_LIBTOOL_PROG_COMPILER_NO_RTTI], [AC_DEFUN([AC_LIBTOOL_PROG_COMPILER_NO_RTTI])])
+m4_ifndef([AC_LIBTOOL_SYS_GLOBAL_SYMBOL_PIPE], [AC_DEFUN([AC_LIBTOOL_SYS_GLOBAL_SYMBOL_PIPE])])
+m4_ifndef([AC_LIBTOOL_PROG_COMPILER_PIC], [AC_DEFUN([AC_LIBTOOL_PROG_COMPILER_PIC])])
+m4_ifndef([AC_LIBTOOL_PROG_LD_SHLIBS],	[AC_DEFUN([AC_LIBTOOL_PROG_LD_SHLIBS])])
+m4_ifndef([AC_LIBTOOL_POSTDEP_PREDEP],	[AC_DEFUN([AC_LIBTOOL_POSTDEP_PREDEP])])
+m4_ifndef([LT_AC_PROG_EGREP],		[AC_DEFUN([LT_AC_PROG_EGREP])])
+m4_ifndef([LT_AC_PROG_SED],		[AC_DEFUN([LT_AC_PROG_SED])])
+m4_ifndef([_LT_CC_BASENAME],		[AC_DEFUN([_LT_CC_BASENAME])])
+m4_ifndef([_LT_COMPILER_BOILERPLATE],	[AC_DEFUN([_LT_COMPILER_BOILERPLATE])])
+m4_ifndef([_LT_LINKER_BOILERPLATE],	[AC_DEFUN([_LT_LINKER_BOILERPLATE])])
+m4_ifndef([_AC_PROG_LIBTOOL],		[AC_DEFUN([_AC_PROG_LIBTOOL])])
+m4_ifndef([AC_LIBTOOL_SETUP],		[AC_DEFUN([AC_LIBTOOL_SETUP])])
+m4_ifndef([_LT_AC_CHECK_DLFCN],		[AC_DEFUN([_LT_AC_CHECK_DLFCN])])
+m4_ifndef([AC_LIBTOOL_SYS_DYNAMIC_LINKER],	[AC_DEFUN([AC_LIBTOOL_SYS_DYNAMIC_LINKER])])
+m4_ifndef([_LT_AC_TAGCONFIG],		[AC_DEFUN([_LT_AC_TAGCONFIG])])
+m4_ifndef([AC_DISABLE_FAST_INSTALL],	[AC_DEFUN([AC_DISABLE_FAST_INSTALL])])
+m4_ifndef([_LT_AC_LANG_CXX],		[AC_DEFUN([_LT_AC_LANG_CXX])])
+m4_ifndef([_LT_AC_LANG_F77],		[AC_DEFUN([_LT_AC_LANG_F77])])
+m4_ifndef([_LT_AC_LANG_GCJ],		[AC_DEFUN([_LT_AC_LANG_GCJ])])
+m4_ifndef([AC_LIBTOOL_LANG_C_CONFIG],	[AC_DEFUN([AC_LIBTOOL_LANG_C_CONFIG])])
+m4_ifndef([_LT_AC_LANG_C_CONFIG],	[AC_DEFUN([_LT_AC_LANG_C_CONFIG])])
+m4_ifndef([AC_LIBTOOL_LANG_CXX_CONFIG],	[AC_DEFUN([AC_LIBTOOL_LANG_CXX_CONFIG])])
+m4_ifndef([_LT_AC_LANG_CXX_CONFIG],	[AC_DEFUN([_LT_AC_LANG_CXX_CONFIG])])
+m4_ifndef([AC_LIBTOOL_LANG_F77_CONFIG],	[AC_DEFUN([AC_LIBTOOL_LANG_F77_CONFIG])])
+m4_ifndef([_LT_AC_LANG_F77_CONFIG],	[AC_DEFUN([_LT_AC_LANG_F77_CONFIG])])
+m4_ifndef([AC_LIBTOOL_LANG_GCJ_CONFIG],	[AC_DEFUN([AC_LIBTOOL_LANG_GCJ_CONFIG])])
+m4_ifndef([_LT_AC_LANG_GCJ_CONFIG],	[AC_DEFUN([_LT_AC_LANG_GCJ_CONFIG])])
+m4_ifndef([AC_LIBTOOL_LANG_RC_CONFIG],	[AC_DEFUN([AC_LIBTOOL_LANG_RC_CONFIG])])
+m4_ifndef([_LT_AC_LANG_RC_CONFIG],	[AC_DEFUN([_LT_AC_LANG_RC_CONFIG])])
+m4_ifndef([AC_LIBTOOL_CONFIG],		[AC_DEFUN([AC_LIBTOOL_CONFIG])])
+m4_ifndef([_LT_AC_FILE_LTDLL_C],	[AC_DEFUN([_LT_AC_FILE_LTDLL_C])])
+m4_ifndef([_LT_REQUIRED_DARWIN_CHECKS],	[AC_DEFUN([_LT_REQUIRED_DARWIN_CHECKS])])
+m4_ifndef([_LT_AC_PROG_CXXCPP],		[AC_DEFUN([_LT_AC_PROG_CXXCPP])])
+m4_ifndef([_LT_PREPARE_SED_QUOTE_VARS],	[AC_DEFUN([_LT_PREPARE_SED_QUOTE_VARS])])
+m4_ifndef([_LT_PROG_ECHO_BACKSLASH],	[AC_DEFUN([_LT_PROG_ECHO_BACKSLASH])])
+m4_ifndef([_LT_PROG_F77],		[AC_DEFUN([_LT_PROG_F77])])
+m4_ifndef([_LT_PROG_FC],		[AC_DEFUN([_LT_PROG_FC])])
+m4_ifndef([_LT_PROG_CXX],		[AC_DEFUN([_LT_PROG_CXX])])
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/visibility.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/visibility.m4
new file mode 100644
index 0000000..75c34b6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/visibility.m4
@@ -0,0 +1,77 @@
+# visibility.m4 serial 4 (gettext-0.18.2)
+dnl Copyright (C) 2005, 2008, 2010-2011 Free Software Foundation, Inc.
+dnl This file is free software; the Free Software Foundation
+dnl gives unlimited permission to copy and/or distribute it,
+dnl with or without modifications, as long as this notice is preserved.
+
+dnl From Bruno Haible.
+
+dnl Tests whether the compiler supports the command-line option
+dnl -fvisibility=hidden and the function and variable attributes
+dnl __attribute__((__visibility__("hidden"))) and
+dnl __attribute__((__visibility__("default"))).
+dnl Does *not* test for __visibility__("protected") - which has tricky
+dnl semantics (see the 'vismain' test in glibc) and does not exist e.g. on
+dnl MacOS X.
+dnl Does *not* test for __visibility__("internal") - which has processor
+dnl dependent semantics.
+dnl Does *not* test for #pragma GCC visibility push(hidden) - which is
+dnl "really only recommended for legacy code".
+dnl Set the variable CFLAG_VISIBILITY.
+dnl Defines and sets the variable HAVE_VISIBILITY.
+
+AC_DEFUN([gl_VISIBILITY],
+[
+  AC_REQUIRE([AC_PROG_CC])
+  CFLAG_VISIBILITY=
+  HAVE_VISIBILITY=0
+  if test -n "$GCC"; then
+    dnl First, check whether -Werror can be added to the command line, or
+    dnl whether it leads to an error because of some other option that the
+    dnl user has put into $CC $CFLAGS $CPPFLAGS.
+    AC_MSG_CHECKING([whether the -Werror option is usable])
+    AC_CACHE_VAL([gl_cv_cc_vis_werror], [
+      gl_save_CFLAGS="$CFLAGS"
+      CFLAGS="$CFLAGS -Werror"
+      AC_COMPILE_IFELSE(
+        [AC_LANG_PROGRAM([[]], [[]])],
+        [gl_cv_cc_vis_werror=yes],
+        [gl_cv_cc_vis_werror=no])
+      CFLAGS="$gl_save_CFLAGS"])
+    AC_MSG_RESULT([$gl_cv_cc_vis_werror])
+    dnl Now check whether visibility declarations are supported.
+    AC_MSG_CHECKING([for simple visibility declarations])
+    AC_CACHE_VAL([gl_cv_cc_visibility], [
+      gl_save_CFLAGS="$CFLAGS"
+      CFLAGS="$CFLAGS -fvisibility=hidden"
+      dnl We use the option -Werror and a function dummyfunc, because on some
+      dnl platforms (Cygwin 1.7) the use of -fvisibility triggers a warning
+      dnl "visibility attribute not supported in this configuration; ignored"
+      dnl at the first function definition in every compilation unit, and we
+      dnl don't want to use the option in this case.
+      if test $gl_cv_cc_vis_werror = yes; then
+        CFLAGS="$CFLAGS -Werror"
+      fi
+      AC_COMPILE_IFELSE(
+        [AC_LANG_PROGRAM(
+           [[extern __attribute__((__visibility__("hidden"))) int hiddenvar;
+             extern __attribute__((__visibility__("default"))) int exportedvar;
+             extern __attribute__((__visibility__("hidden"))) int hiddenfunc (void);
+             extern __attribute__((__visibility__("default"))) int exportedfunc (void);
+             void dummyfunc (void) {}
+           ]],
+           [[]])],
+        [gl_cv_cc_visibility=yes],
+        [gl_cv_cc_visibility=no])
+      CFLAGS="$gl_save_CFLAGS"])
+    AC_MSG_RESULT([$gl_cv_cc_visibility])
+    if test $gl_cv_cc_visibility = yes; then
+      CFLAG_VISIBILITY="-fvisibility=hidden"
+      HAVE_VISIBILITY=1
+    fi
+  fi
+  AC_SUBST([CFLAG_VISIBILITY])
+  AC_SUBST([HAVE_VISIBILITY])
+  AC_DEFINE_UNQUOTED([HAVE_VISIBILITY], [$HAVE_VISIBILITY],
+    [Define to 1 or 0, depending whether the compiler supports simple visibility declarations.])
+])
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/wolfssl_darwin_clang.m4 b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/wolfssl_darwin_clang.m4
new file mode 100644
index 0000000..fee9b6a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/m4/wolfssl_darwin_clang.m4
@@ -0,0 +1,37 @@
+# ===========================================================================
+#
+# SYNOPSIS
+#
+#   WOLFSSL_DARWIN_USING_CLANG
+#
+# DESCRIPTION
+#
+#   With the advent of Apple Xcode v5.0, the old tool sets are missing from
+#   the distribution. The provided "gcc" executable wrapper accepts the
+#   "-pthread" flag, and passes it to the underlying "clang" which chokes
+#   on it. This script checks the version of the gcc executable to see if
+#   it reports it is really "clang".
+#
+#   The value is placed in the wolfssl_darwin_clang variable.
+#
+# LICENSE
+#
+#   Copyright (c) 2013 John Safranek 
+#
+#   Copying and distribution of this file, with or without modification, are
+#   permitted in any medium without royalty provided the copyright notice
+#   and this notice are preserved. This file is offered as-is, without any
+#   warranty.
+
+#serial 1
+
+AC_DEFUN([WOLFSSL_DARWIN_USING_CLANG],
+        [
+            if test x"$CC" = xclang; then
+                wolfssl_darwin_clang=yes
+            elif test x"$CC" = x || test x"$CC" = xgcc; then
+                if /usr/bin/gcc -v 2>&1 | grep 'clang' >/dev/null 2>&1; then
+                    wolfssl_darwin_clang=yes
+                fi
+            fi
+        ])
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/quit b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/quit
new file mode 100644
index 0000000..3db49b3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/quit
@@ -0,0 +1,2 @@
+quit
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/rpm/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/rpm/include.am
new file mode 100644
index 0000000..e5253dd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/rpm/include.am
@@ -0,0 +1,37 @@
+# vim:ft=automake
+
+rpm-build: rpm/spec dist
+	@rm -f *.rpm
+	@rm -f ~/rpmbuild/RPMS/x86_64/$(PACKAGE)-$(VERSION)*.rpm
+	@rm -f ~/rpmbuild/SRPMS/$(PACKAGE)-$(VERSION)*.rpm
+	@mkdir -p ~/rpmbuild/BUILD/
+	@mkdir -p ~/rpmbuild/RPMS/i386/
+	@mkdir -p ~/rpmbuild/RPMS/i686/
+	@mkdir -p ~/rpmbuild/RPMS/noarch/
+	@mkdir -p ~/rpmbuild/RPMS/x86_64/
+	@mkdir -p ~/rpmbuild/SOURCES/
+	@mkdir -p ~/rpmbuild/SPECS/
+	@mkdir -p ~/rpmbuild/SRPMS/
+	@cp $(PACKAGE)-$(VERSION).tar.gz ~/rpmbuild/SOURCES/
+	@rpmbuild -ba --clean rpm/spec
+	@cp ~/rpmbuild/RPMS/x86_64/$(PACKAGE)-$(VERSION)*.rpm .
+	@cp ~/rpmbuild/RPMS/x86_64/$(PACKAGE)-devel-$(VERSION)*.rpm .
+	@cp ~/rpmbuild/RPMS/x86_64/$(PACKAGE)-debuginfo-$(VERSION)*.rpm .
+	@cp ~/rpmbuild/SRPMS/$(PACKAGE)-$(VERSION)*.rpm .
+
+rpm-sign: rpm-build
+	@rpm --addsign *.rpm
+	@rpm --checksig *.rpm
+
+clean-rpm:
+	@rm -f *.tar.gz
+	@rm -f *.src.rpm
+	@rm -f *.rpm
+
+rpm: rpm-build
+
+release: rpm-sign
+
+auto-rpmbuild:
+	@auto-br-rpmbuild -ba rpm/spec
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/rpm/spec.in b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/rpm/spec.in
new file mode 100644
index 0000000..1e291dd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/rpm/spec.in
@@ -0,0 +1,265 @@
+Summary: Embedded SSL Library
+Name: @PACKAGE@
+Version: @VERSION@
+Release: 1
+License: GPLv2
+Group: System Environment/Libraries
+BuildRequires: gcc
+BuildRequires: glibc
+BuildRequires: glibc-common
+BuildRequires: glibc-devel
+BuildRequires: glibc-headers
+BuildRequires: make
+BuildRequires: pkgconfig
+BuildRequires: sed
+BuildRequires: tar
+URL: http://www.wolfssl.com/
+
+Packager: Brian Aker 
+
+Source: http://wolfssl.com/%{name}-%{version}.tar.gz
+BuildRoot: %{_tmppath}/%{name}-%{version}-%{release}-buildroot
+
+%description
+Misc tools for wolfSSL.
+
+%package devel
+Summary: Header files and development libraries for %{name}
+Group: Development/Libraries
+Requires: %{name} = %{version}-%{release}
+
+%description devel
+This package contains the header files and development libraries
+for %{name}. If you like to develop programs using %{name},
+you will need to install %{name}-devel.
+
+%prep
+%setup -q
+
+%configure
+
+
+%build
+%{__make} %{?_smp_mflags}
+
+%install
+%{__rm} -rf %{buildroot}
+%{__make} install  DESTDIR="%{buildroot}" AM_INSTALL_PROGRAM_FLAGS=""
+mkdir -p $RPM_BUILD_ROOT/
+
+%check
+
+
+%clean
+%{__rm} -rf %{buildroot}
+
+%post -p /sbin/ldconfig
+
+%postun -p /sbin/ldconfig
+
+%files
+%defattr(-,root,root,-)
+%doc AUTHORS ChangeLog COPYING NEWS README
+%{_docdir}/wolfssl/taoCert.txt
+%{_docdir}/wolfssl/example/echoserver.c
+%{_docdir}/wolfssl/example/server.c
+%{_docdir}/wolfssl/example/echoclient.c
+%{_docdir}/wolfssl/example/client.c
+%{_docdir}/wolfssl/README.txt
+%{_libdir}/libwolfssl.la
+%{_libdir}/libwolfssl.so
+%{_libdir}/libwolfssl.so.0
+%{_libdir}/libwolfssl.so.0.0.2
+
+%files devel
+%defattr(-,root,root,-)
+%doc AUTHORS ChangeLog COPYING NEWS README
+%{_bindir}/wolfssl-config
+%{_includedir}/cyassl/callbacks.h
+%{_includedir}/cyassl/certs_test.h
+%{_includedir}/cyassl/crl.h
+%{_includedir}/cyassl/ctaocrypt/aes.h
+%{_includedir}/cyassl/ctaocrypt/arc4.h
+%{_includedir}/cyassl/ctaocrypt/asn.h
+%{_includedir}/cyassl/ctaocrypt/asn_public.h
+%{_includedir}/cyassl/ctaocrypt/blake2-impl.h
+%{_includedir}/cyassl/ctaocrypt/blake2-int.h
+%{_includedir}/cyassl/ctaocrypt/blake2.h
+%{_includedir}/cyassl/ctaocrypt/camellia.h
+%{_includedir}/cyassl/ctaocrypt/chacha.h
+%{_includedir}/cyassl/ctaocrypt/coding.h
+%{_includedir}/cyassl/ctaocrypt/compress.h
+%{_includedir}/cyassl/ctaocrypt/des3.h
+%{_includedir}/cyassl/ctaocrypt/dh.h
+%{_includedir}/cyassl/ctaocrypt/dsa.h
+%{_includedir}/cyassl/ctaocrypt/ecc.h
+%{_includedir}/cyassl/ctaocrypt/error-crypt.h
+%{_includedir}/cyassl/ctaocrypt/fips_test.h
+%{_includedir}/cyassl/ctaocrypt/hc128.h
+%{_includedir}/cyassl/ctaocrypt/hmac.h
+%{_includedir}/cyassl/ctaocrypt/integer.h
+%{_includedir}/cyassl/ctaocrypt/logging.h
+%{_includedir}/cyassl/ctaocrypt/md2.h
+%{_includedir}/cyassl/ctaocrypt/md4.h
+%{_includedir}/cyassl/ctaocrypt/md5.h
+%{_includedir}/cyassl/ctaocrypt/memory.h
+%{_includedir}/cyassl/ctaocrypt/misc.h
+%{_includedir}/cyassl/ctaocrypt/mpi_class.h
+%{_includedir}/cyassl/ctaocrypt/mpi_superclass.h
+%{_includedir}/cyassl/ctaocrypt/pkcs7.h
+%{_includedir}/cyassl/ctaocrypt/poly1305.h
+%{_includedir}/cyassl/ctaocrypt/wc_port.h
+%{_includedir}/cyassl/ctaocrypt/pwdbased.h
+%{_includedir}/cyassl/ctaocrypt/rabbit.h
+%{_includedir}/cyassl/ctaocrypt/random.h
+%{_includedir}/cyassl/ctaocrypt/ripemd.h
+%{_includedir}/cyassl/ctaocrypt/rsa.h
+%{_includedir}/cyassl/ctaocrypt/settings.h
+%{_includedir}/cyassl/ctaocrypt/settings_comp.h
+%{_includedir}/cyassl/ctaocrypt/sha.h
+%{_includedir}/cyassl/ctaocrypt/sha256.h
+%{_includedir}/cyassl/ctaocrypt/sha512.h
+%{_includedir}/cyassl/ctaocrypt/tfm.h
+%{_includedir}/cyassl/ctaocrypt/types.h
+%{_includedir}/cyassl/ctaocrypt/visibility.h
+%{_includedir}/cyassl/error-ssl.h
+%{_includedir}/cyassl/ocsp.h
+%{_includedir}/cyassl/openssl/asn1.h
+%{_includedir}/cyassl/openssl/bio.h
+%{_includedir}/cyassl/openssl/bn.h
+%{_includedir}/cyassl/openssl/conf.h
+%{_includedir}/cyassl/openssl/crypto.h
+%{_includedir}/cyassl/openssl/des.h
+%{_includedir}/cyassl/openssl/dh.h
+%{_includedir}/cyassl/openssl/dsa.h
+%{_includedir}/cyassl/openssl/ec.h
+%{_includedir}/cyassl/openssl/ecdsa.h
+%{_includedir}/cyassl/openssl/engine.h
+%{_includedir}/cyassl/openssl/err.h
+%{_includedir}/cyassl/openssl/evp.h
+%{_includedir}/cyassl/openssl/hmac.h
+%{_includedir}/cyassl/openssl/lhash.h
+%{_includedir}/cyassl/openssl/md4.h
+%{_includedir}/cyassl/openssl/md5.h
+%{_includedir}/cyassl/openssl/ocsp.h
+%{_includedir}/cyassl/openssl/opensslconf.h
+%{_includedir}/cyassl/openssl/opensslv.h
+%{_includedir}/cyassl/openssl/ossl_typ.h
+%{_includedir}/cyassl/openssl/pem.h
+%{_includedir}/cyassl/openssl/pkcs12.h
+%{_includedir}/cyassl/openssl/rand.h
+%{_includedir}/cyassl/openssl/ripemd.h
+%{_includedir}/cyassl/openssl/rsa.h
+%{_includedir}/cyassl/openssl/sha.h
+%{_includedir}/cyassl/openssl/ssl.h
+%{_includedir}/cyassl/openssl/stack.h
+%{_includedir}/cyassl/openssl/ui.h
+%{_includedir}/cyassl/openssl/x509.h
+%{_includedir}/cyassl/openssl/x509v3.h
+%{_includedir}/cyassl/options.h
+%{_includedir}/cyassl/sniffer.h
+%{_includedir}/cyassl/sniffer_error.h
+%{_includedir}/cyassl/ssl.h
+%{_includedir}/cyassl/test.h
+%{_includedir}/cyassl/version.h
+%{_includedir}/wolfssl/callbacks.h
+%{_includedir}/wolfssl/certs_test.h
+%{_includedir}/wolfssl/crl.h
+%{_includedir}/wolfssl/wolfcrypt/aes.h
+%{_includedir}/wolfssl/wolfcrypt/arc4.h
+%{_includedir}/wolfssl/wolfcrypt/asn.h
+%{_includedir}/wolfssl/wolfcrypt/asn_public.h
+%{_includedir}/wolfssl/wolfcrypt/blake2-impl.h
+%{_includedir}/wolfssl/wolfcrypt/blake2-int.h
+%{_includedir}/wolfssl/wolfcrypt/blake2.h
+%{_includedir}/wolfssl/wolfcrypt/camellia.h
+%{_includedir}/wolfssl/wolfcrypt/chacha.h
+%{_includedir}/wolfssl/wolfcrypt/chacha20_poly1305.h
+%{_includedir}/wolfssl/wolfcrypt/coding.h
+%{_includedir}/wolfssl/wolfcrypt/compress.h
+%{_includedir}/wolfssl/wolfcrypt/curve25519.h
+%{_includedir}/wolfssl/wolfcrypt/des3.h
+%{_includedir}/wolfssl/wolfcrypt/dh.h
+%{_includedir}/wolfssl/wolfcrypt/dsa.h
+%{_includedir}/wolfssl/wolfcrypt/ecc.h
+%{_includedir}/wolfssl/wolfcrypt/ed25519.h
+%{_includedir}/wolfssl/wolfcrypt/error-crypt.h
+%{_includedir}/wolfssl/wolfcrypt/fe_operations.h
+%{_includedir}/wolfssl/wolfcrypt/fips_test.h
+%{_includedir}/wolfssl/wolfcrypt/ge_operations.h
+%{_includedir}/wolfssl/wolfcrypt/hash.h
+%{_includedir}/wolfssl/wolfcrypt/hc128.h
+%{_includedir}/wolfssl/wolfcrypt/hmac.h
+%{_includedir}/wolfssl/wolfcrypt/integer.h
+%{_includedir}/wolfssl/wolfcrypt/logging.h
+%{_includedir}/wolfssl/wolfcrypt/md2.h
+%{_includedir}/wolfssl/wolfcrypt/md4.h
+%{_includedir}/wolfssl/wolfcrypt/md5.h
+%{_includedir}/wolfssl/wolfcrypt/memory.h
+%{_includedir}/wolfssl/wolfcrypt/misc.h
+%{_includedir}/wolfssl/wolfcrypt/mpi_class.h
+%{_includedir}/wolfssl/wolfcrypt/mpi_superclass.h
+%{_includedir}/wolfssl/wolfcrypt/pkcs7.h
+%{_includedir}/wolfssl/wolfcrypt/wc_port.h
+%{_includedir}/wolfssl/wolfcrypt/poly1305.h
+%{_includedir}/wolfssl/wolfcrypt/pwdbased.h
+%{_includedir}/wolfssl/wolfcrypt/rabbit.h
+%{_includedir}/wolfssl/wolfcrypt/random.h
+%{_includedir}/wolfssl/wolfcrypt/ripemd.h
+%{_includedir}/wolfssl/wolfcrypt/rsa.h
+%{_includedir}/wolfssl/wolfcrypt/settings.h
+%{_includedir}/wolfssl/wolfcrypt/sha.h
+%{_includedir}/wolfssl/wolfcrypt/sha256.h
+%{_includedir}/wolfssl/wolfcrypt/sha512.h
+%{_includedir}/wolfssl/wolfcrypt/tfm.h
+%{_includedir}/wolfssl/wolfcrypt/types.h
+%{_includedir}/wolfssl/wolfcrypt/visibility.h
+%{_includedir}/wolfssl/error-ssl.h
+%{_includedir}/wolfssl/ocsp.h
+%{_includedir}/wolfssl/openssl/asn1.h
+%{_includedir}/wolfssl/openssl/bio.h
+%{_includedir}/wolfssl/openssl/bn.h
+%{_includedir}/wolfssl/openssl/conf.h
+%{_includedir}/wolfssl/openssl/crypto.h
+%{_includedir}/wolfssl/openssl/des.h
+%{_includedir}/wolfssl/openssl/dh.h
+%{_includedir}/wolfssl/openssl/dsa.h
+%{_includedir}/wolfssl/openssl/ec.h
+%{_includedir}/wolfssl/openssl/ecdsa.h
+%{_includedir}/wolfssl/openssl/engine.h
+%{_includedir}/wolfssl/openssl/err.h
+%{_includedir}/wolfssl/openssl/evp.h
+%{_includedir}/wolfssl/openssl/hmac.h
+%{_includedir}/wolfssl/openssl/lhash.h
+%{_includedir}/wolfssl/openssl/md4.h
+%{_includedir}/wolfssl/openssl/md5.h
+%{_includedir}/wolfssl/openssl/ocsp.h
+%{_includedir}/wolfssl/openssl/opensslconf.h
+%{_includedir}/wolfssl/openssl/opensslv.h
+%{_includedir}/wolfssl/openssl/ossl_typ.h
+%{_includedir}/wolfssl/openssl/pem.h
+%{_includedir}/wolfssl/openssl/pkcs12.h
+%{_includedir}/wolfssl/openssl/rand.h
+%{_includedir}/wolfssl/openssl/ripemd.h
+%{_includedir}/wolfssl/openssl/rsa.h
+%{_includedir}/wolfssl/openssl/sha.h
+%{_includedir}/wolfssl/openssl/ssl.h
+%{_includedir}/wolfssl/openssl/stack.h
+%{_includedir}/wolfssl/openssl/ui.h
+%{_includedir}/wolfssl/openssl/x509.h
+%{_includedir}/wolfssl/openssl/x509v3.h
+%{_includedir}/wolfssl/options.h
+%{_includedir}/wolfssl/sniffer.h
+%{_includedir}/wolfssl/sniffer_error.h
+%{_includedir}/wolfssl/ssl.h
+%{_includedir}/wolfssl/test.h
+%{_includedir}/wolfssl/version.h
+%{_libdir}/pkgconfig/wolfssl.pc
+
+%changelog
+* Tue Mar 31 2015 John Safranek 
+- Added recent new wolfcrypt headers for curve25519
+* Fri Jan 09 2015 John Safranek 
+- Update for cyassl->wolfssl name change
+* Fri Oct 20 2012 Brian Aker 
+- Initial package
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/crl.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/crl.c
new file mode 100644
index 0000000..0f47ee1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/crl.c
@@ -0,0 +1,790 @@
+/* crl.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+  /* Name change compatibility layer no longer needs included here */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifdef HAVE_CRL
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#ifdef HAVE_CRL_MONITOR
+    static int StopMonitor(int mfd);
+#endif
+
+
+/* Initialze CRL members */
+int InitCRL(WOLFSSL_CRL* crl, WOLFSSL_CERT_MANAGER* cm)
+{
+    WOLFSSL_ENTER("InitCRL");
+
+    crl->cm = cm;
+    crl->crlList = NULL;
+    crl->monitors[0].path = NULL;
+    crl->monitors[1].path = NULL;
+#ifdef HAVE_CRL_MONITOR
+    crl->tid =  0;
+    crl->mfd = -1;   /* mfd for bsd is kqueue fd, eventfd for linux */
+#endif
+    if (InitMutex(&crl->crlLock) != 0)
+        return BAD_MUTEX_E; 
+
+    return 0;
+}
+
+
+/* Initialze CRL Entry */
+static int InitCRL_Entry(CRL_Entry* crle, DecodedCRL* dcrl)
+{
+    WOLFSSL_ENTER("InitCRL_Entry");
+
+    XMEMCPY(crle->issuerHash, dcrl->issuerHash, CRL_DIGEST_SIZE);
+    /* XMEMCPY(crle->crlHash, dcrl->crlHash, CRL_DIGEST_SIZE);
+     *   copy the hash here if needed for optimized comparisons */
+    XMEMCPY(crle->lastDate, dcrl->lastDate, MAX_DATE_SIZE);
+    XMEMCPY(crle->nextDate, dcrl->nextDate, MAX_DATE_SIZE);
+    crle->lastDateFormat = dcrl->lastDateFormat;
+    crle->nextDateFormat = dcrl->nextDateFormat;
+
+    crle->certs = dcrl->certs;   /* take ownsership */
+    dcrl->certs = NULL;
+    crle->totalCerts = dcrl->totalCerts;
+
+    return 0;
+}
+
+
+/* Free all CRL Entry resources */
+static void FreeCRL_Entry(CRL_Entry* crle)
+{
+    RevokedCert* tmp = crle->certs; 
+
+    WOLFSSL_ENTER("FreeCRL_Entry");
+
+    while(tmp) {
+        RevokedCert* next = tmp->next;
+        XFREE(tmp, NULL, DYNAMIC_TYPE_REVOKED);
+        tmp = next;
+    }
+}
+
+
+
+/* Free all CRL resources */
+void FreeCRL(WOLFSSL_CRL* crl, int dynamic)
+{
+    CRL_Entry* tmp = crl->crlList;
+
+    WOLFSSL_ENTER("FreeCRL");
+
+    if (crl->monitors[0].path)
+        XFREE(crl->monitors[0].path, NULL, DYNAMIC_TYPE_CRL_MONITOR);
+
+    if (crl->monitors[1].path)
+        XFREE(crl->monitors[1].path, NULL, DYNAMIC_TYPE_CRL_MONITOR);
+
+    while(tmp) {
+        CRL_Entry* next = tmp->next;
+        FreeCRL_Entry(tmp);
+        XFREE(tmp, NULL, DYNAMIC_TYPE_CRL_ENTRY);
+        tmp = next;
+    }	
+
+#ifdef HAVE_CRL_MONITOR
+    if (crl->tid != 0) {
+        WOLFSSL_MSG("stopping monitor thread");
+        if (StopMonitor(crl->mfd) == 0)
+            pthread_join(crl->tid, NULL);
+        else {
+            WOLFSSL_MSG("stop monitor failed, cancel instead");
+            pthread_cancel(crl->tid);
+        }
+    }
+#endif
+    FreeMutex(&crl->crlLock);
+    if (dynamic)   /* free self */
+        XFREE(crl, NULL, DYNAMIC_TYPE_CRL);
+}
+
+
+/* Is the cert ok with CRL, return 0 on success */
+int CheckCertCRL(WOLFSSL_CRL* crl, DecodedCert* cert)
+{
+    CRL_Entry* crle;
+    int        foundEntry = 0;
+    int        ret = 0;
+
+    WOLFSSL_ENTER("CheckCertCRL");
+
+    if (LockMutex(&crl->crlLock) != 0) {
+        WOLFSSL_MSG("LockMutex failed");
+        return BAD_MUTEX_E;
+    }
+
+    crle = crl->crlList;
+
+    while (crle) {
+        if (XMEMCMP(crle->issuerHash, cert->issuerHash, CRL_DIGEST_SIZE) == 0) {
+            WOLFSSL_MSG("Found CRL Entry on list");
+            WOLFSSL_MSG("Checking next date validity");
+
+            if (!ValidateDate(crle->nextDate, crle->nextDateFormat, AFTER)) {
+                WOLFSSL_MSG("CRL next date is no longer valid");
+                ret = ASN_AFTER_DATE_E;
+            }
+            else
+                foundEntry = 1;
+            break;
+        }
+        crle = crle->next;
+    }
+
+    if (foundEntry) {
+        RevokedCert* rc = crle->certs;
+
+        while (rc) {
+            if (XMEMCMP(rc->serialNumber, cert->serial, rc->serialSz) == 0) {
+                WOLFSSL_MSG("Cert revoked");
+                ret = CRL_CERT_REVOKED;
+                break;
+            }
+            rc = rc->next;	
+        }
+    }
+
+    UnLockMutex(&crl->crlLock);
+
+    if (foundEntry == 0) {
+        WOLFSSL_MSG("Couldn't find CRL for status check");
+        ret = CRL_MISSING;
+        if (crl->cm->cbMissingCRL) {
+            char url[256];
+
+            WOLFSSL_MSG("Issuing missing CRL callback");
+            url[0] = '\0';
+            if (cert->extCrlInfoSz < (int)sizeof(url) -1 ) {
+                XMEMCPY(url, cert->extCrlInfo, cert->extCrlInfoSz);
+                url[cert->extCrlInfoSz] = '\0';
+            }
+            else  {
+                WOLFSSL_MSG("CRL url too long");
+            }
+            crl->cm->cbMissingCRL(url);
+        }
+    }
+
+
+    return ret;	
+}
+
+
+/* Add Decoded CRL, 0 on success */
+static int AddCRL(WOLFSSL_CRL* crl, DecodedCRL* dcrl)
+{
+    CRL_Entry* crle;
+
+    WOLFSSL_ENTER("AddCRL");
+
+    crle = (CRL_Entry*)XMALLOC(sizeof(CRL_Entry), NULL, DYNAMIC_TYPE_CRL_ENTRY);
+    if (crle == NULL) {
+        WOLFSSL_MSG("alloc CRL Entry failed");
+        return -1;
+    }
+
+    if (InitCRL_Entry(crle, dcrl) < 0) {
+        WOLFSSL_MSG("Init CRL Entry failed");
+        XFREE(crle, NULL, DYNAMIC_TYPE_CRL_ENTRY);
+        return -1;
+    }
+
+    if (LockMutex(&crl->crlLock) != 0) {
+        WOLFSSL_MSG("LockMutex failed");
+        FreeCRL_Entry(crle);
+        XFREE(crle, NULL, DYNAMIC_TYPE_CRL_ENTRY);
+        return BAD_MUTEX_E;
+    }
+    crle->next = crl->crlList;
+    crl->crlList = crle;
+    UnLockMutex(&crl->crlLock);
+
+    return 0;
+}
+
+
+/* Load CRL File of type, SSL_SUCCESS on ok */
+int BufferLoadCRL(WOLFSSL_CRL* crl, const byte* buff, long sz, int type)
+{
+    int          ret = SSL_SUCCESS;
+    const byte*  myBuffer = buff;    /* if DER ok, otherwise switch */
+    buffer       der;
+#ifdef WOLFSSL_SMALL_STACK
+    DecodedCRL*  dcrl;
+#else
+    DecodedCRL   dcrl[1];
+#endif
+
+    der.buffer = NULL;
+
+    WOLFSSL_ENTER("BufferLoadCRL");
+
+    if (crl == NULL || buff == NULL || sz == 0)
+        return BAD_FUNC_ARG;
+
+    if (type == SSL_FILETYPE_PEM) {
+        int eccKey = 0;   /* not used */
+        EncryptedInfo info;
+        info.ctx = NULL;
+
+        ret = PemToDer(buff, sz, CRL_TYPE, &der, NULL, &info, &eccKey);
+        if (ret == 0) {
+            myBuffer = der.buffer;
+            sz = der.length;
+        }
+        else {
+            WOLFSSL_MSG("Pem to Der failed");
+            return -1;
+        }
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    dcrl = (DecodedCRL*)XMALLOC(sizeof(DecodedCRL), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (dcrl == NULL) {
+        if (der.buffer)
+            XFREE(der.buffer, NULL, DYNAMIC_TYPE_CRL);
+
+        return MEMORY_E;
+    }
+#endif
+
+    InitDecodedCRL(dcrl);
+    ret = ParseCRL(dcrl, myBuffer, (word32)sz, crl->cm);
+    if (ret != 0) {
+        WOLFSSL_MSG("ParseCRL error");
+    }
+    else {
+        ret = AddCRL(crl, dcrl);
+        if (ret != 0) {
+            WOLFSSL_MSG("AddCRL error");
+        }
+    }
+
+    FreeDecodedCRL(dcrl);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(dcrl, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    if (der.buffer)
+        XFREE(der.buffer, NULL, DYNAMIC_TYPE_CRL);
+
+    return ret ? ret : SSL_SUCCESS; /* convert 0 to SSL_SUCCESS */
+}
+
+
+#ifdef HAVE_CRL_MONITOR
+
+
+/* read in new CRL entries and save new list */
+static int SwapLists(WOLFSSL_CRL* crl)
+{
+    int        ret;
+    CRL_Entry* newList;
+#ifdef WOLFSSL_SMALL_STACK
+    WOLFSSL_CRL* tmp;    
+#else
+    WOLFSSL_CRL tmp[1];
+#endif
+    
+#ifdef WOLFSSL_SMALL_STACK
+    tmp = (WOLFSSL_CRL*)XMALLOC(sizeof(WOLFSSL_CRL), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (tmp == NULL)
+        return MEMORY_E;
+#endif   
+
+    if (InitCRL(tmp, crl->cm) < 0) {
+        WOLFSSL_MSG("Init tmp CRL failed");
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(tmp, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return -1;
+    }
+
+    if (crl->monitors[0].path) {
+        ret = LoadCRL(tmp, crl->monitors[0].path, SSL_FILETYPE_PEM, 0);
+        if (ret != SSL_SUCCESS) {
+            WOLFSSL_MSG("PEM LoadCRL on dir change failed");
+            FreeCRL(tmp, 0);
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(tmp, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return -1;
+        }
+    }
+
+    if (crl->monitors[1].path) {
+        ret = LoadCRL(tmp, crl->monitors[1].path, SSL_FILETYPE_ASN1, 0);
+        if (ret != SSL_SUCCESS) {
+            WOLFSSL_MSG("DER LoadCRL on dir change failed");
+            FreeCRL(tmp, 0);
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(tmp, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return -1;
+        }
+    }
+
+    if (LockMutex(&crl->crlLock) != 0) {
+        WOLFSSL_MSG("LockMutex failed");
+        FreeCRL(tmp, 0);
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(tmp, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return -1;
+    }
+
+    newList = tmp->crlList;
+
+    /* swap lists */
+    tmp->crlList  = crl->crlList;
+    crl->crlList = newList;
+
+    UnLockMutex(&crl->crlLock);
+
+    FreeCRL(tmp, 0);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(tmp, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return 0;
+}
+
+
+#if (defined(__MACH__) || defined(__FreeBSD__))
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifdef __MACH__
+    #define XEVENT_MODE O_EVTONLY
+#elif defined(__FreeBSD__)
+    #define XEVENT_MODE EVFILT_VNODE
+#endif
+
+
+/* we need a unique kqueue user filter fd for crl in case user is doing custom
+ * events too */
+#ifndef CRL_CUSTOM_FD
+    #define CRL_CUSTOM_FD 123456
+#endif
+
+
+/* shutdown monitor thread, 0 on success */
+static int StopMonitor(int mfd)
+{
+    struct kevent change;
+
+    /* trigger custom shutdown */
+    EV_SET(&change, CRL_CUSTOM_FD, EVFILT_USER, 0, NOTE_TRIGGER, 0, NULL);
+    if (kevent(mfd, &change, 1, NULL, 0, NULL) < 0) {
+        WOLFSSL_MSG("kevent trigger customer event failed");
+        return -1;
+    }
+
+    return 0;
+}
+
+
+/* OS X  monitoring */
+static void* DoMonitor(void* arg)
+{
+    int fPEM, fDER;
+    struct kevent change;
+
+    WOLFSSL_CRL* crl = (WOLFSSL_CRL*)arg;
+
+    WOLFSSL_ENTER("DoMonitor");
+
+    crl->mfd = kqueue();
+    if (crl->mfd == -1) {
+        WOLFSSL_MSG("kqueue failed");
+        return NULL;
+    }
+
+    /* listen for custom shutdown event */
+    EV_SET(&change, CRL_CUSTOM_FD, EVFILT_USER, EV_ADD, 0, 0, NULL);
+    if (kevent(crl->mfd, &change, 1, NULL, 0, NULL) < 0) {
+        WOLFSSL_MSG("kevent monitor customer event failed");
+        close(crl->mfd);
+        return NULL;
+    }
+
+    fPEM = -1;
+    fDER = -1;
+
+    if (crl->monitors[0].path) {
+        fPEM = open(crl->monitors[0].path, XEVENT_MODE);
+        if (fPEM == -1) {
+            WOLFSSL_MSG("PEM event dir open failed");
+            close(crl->mfd);
+            return NULL;
+        }
+    }
+
+    if (crl->monitors[1].path) {
+        fDER = open(crl->monitors[1].path, XEVENT_MODE);
+        if (fDER == -1) {
+            WOLFSSL_MSG("DER event dir open failed");
+            close(crl->mfd);
+            return NULL;
+        }
+    }
+
+    if (fPEM != -1)
+        EV_SET(&change, fPEM, EVFILT_VNODE, EV_ADD | EV_ENABLE | EV_ONESHOT,
+                NOTE_DELETE | NOTE_EXTEND | NOTE_WRITE | NOTE_ATTRIB, 0, 0);
+
+    if (fDER != -1)
+        EV_SET(&change, fDER, EVFILT_VNODE, EV_ADD | EV_ENABLE | EV_ONESHOT,
+                NOTE_DELETE | NOTE_EXTEND | NOTE_WRITE | NOTE_ATTRIB, 0, 0);
+
+    for (;;) {
+        struct kevent event;
+        int           numEvents = kevent(crl->mfd, &change, 1, &event, 1, NULL);
+       
+        WOLFSSL_MSG("Got kevent");
+
+        if (numEvents == -1) {
+            WOLFSSL_MSG("kevent problem, continue");
+            continue;
+        }
+
+        if (event.filter == EVFILT_USER) {
+            WOLFSSL_MSG("Got user shutdown event, breaking out");
+            break;
+        }
+
+        if (SwapLists(crl) < 0) {
+            WOLFSSL_MSG("SwapLists problem, continue");
+        }
+    }
+
+    if (fPEM != -1)
+        close(fPEM);
+    if (fDER != -1)
+        close(fDER);
+
+    close(crl->mfd);
+
+    return NULL;
+}
+
+
+#elif defined(__linux__)
+
+#include 
+#include 
+#include 
+#include 
+
+
+#ifndef max
+    static INLINE int max(int a, int b)
+    {
+        return a > b ? a : b;
+    }
+#endif /* max */
+
+
+/* shutdown monitor thread, 0 on success */
+static int StopMonitor(int mfd)
+{
+    word64 w64 = 1;
+
+    /* write to our custom event */
+    if (write(mfd, &w64, sizeof(w64)) < 0) {
+        WOLFSSL_MSG("StopMonitor write failed");
+        return -1;
+    }
+
+    return 0;
+}
+
+
+/* linux monitoring */
+static void* DoMonitor(void* arg)
+{
+    int         notifyFd;
+    int         wd  = -1;
+    WOLFSSL_CRL* crl = (WOLFSSL_CRL*)arg;
+#ifdef WOLFSSL_SMALL_STACK
+    char*       buff;
+#else
+    char        buff[8192];
+#endif
+
+    WOLFSSL_ENTER("DoMonitor");
+
+    crl->mfd = eventfd(0, 0);  /* our custom shutdown event */
+    if (crl->mfd < 0) {
+        WOLFSSL_MSG("eventfd failed");
+        return NULL;
+    }
+
+    notifyFd = inotify_init();
+    if (notifyFd < 0) {
+        WOLFSSL_MSG("inotify failed");
+        close(crl->mfd);
+        return NULL;
+    }
+
+    if (crl->monitors[0].path) {
+        wd = inotify_add_watch(notifyFd, crl->monitors[0].path, IN_CLOSE_WRITE |
+                                                                IN_DELETE);
+        if (wd < 0) {
+            WOLFSSL_MSG("PEM notify add watch failed");
+            close(crl->mfd);
+            close(notifyFd);
+            return NULL;
+        }
+    }
+
+    if (crl->monitors[1].path) {
+        wd = inotify_add_watch(notifyFd, crl->monitors[1].path, IN_CLOSE_WRITE |
+                                                                IN_DELETE);
+        if (wd < 0) {
+            WOLFSSL_MSG("DER notify add watch failed");
+            close(crl->mfd);
+            close(notifyFd);
+            return NULL;
+        }
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    buff = (char*)XMALLOC(8192, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (buff == NULL)
+        return NULL;
+#endif
+
+    for (;;) {
+        fd_set readfds;
+        int    result;
+        int    length;
+
+        FD_ZERO(&readfds);
+        FD_SET(notifyFd, &readfds);
+        FD_SET(crl->mfd, &readfds);
+
+        result = select(max(notifyFd, crl->mfd) + 1, &readfds, NULL, NULL,NULL);
+       
+        WOLFSSL_MSG("Got notify event");
+
+        if (result < 0) {
+            WOLFSSL_MSG("select problem, continue");
+            continue;
+        }
+
+        if (FD_ISSET(crl->mfd, &readfds)) {
+            WOLFSSL_MSG("got custom shutdown event, breaking out");
+            break;
+        }
+
+        length = read(notifyFd, buff, 8192);
+        if (length < 0) {
+            WOLFSSL_MSG("notify read problem, continue");
+            continue;
+        } 
+
+        if (SwapLists(crl) < 0) {
+            WOLFSSL_MSG("SwapLists problem, continue");
+        }
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(buff, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    if (wd > 0)
+        inotify_rm_watch(notifyFd, wd);
+    close(crl->mfd);
+    close(notifyFd);
+
+    return NULL;
+}
+
+
+#else
+
+#error "CRL monitor only currently supported on linux or mach"
+
+#endif /* MACH or linux */
+
+
+/* Start Monitoring the CRL path(s) in a thread */
+static int StartMonitorCRL(WOLFSSL_CRL* crl)
+{
+    pthread_attr_t attr;
+
+    WOLFSSL_ENTER("StartMonitorCRL");
+
+    if (crl == NULL) 
+        return BAD_FUNC_ARG;
+
+    if (crl->tid != 0) {
+        WOLFSSL_MSG("Monitor thread already running");
+        return MONITOR_RUNNING_E;
+    }
+
+    pthread_attr_init(&attr);
+
+    if (pthread_create(&crl->tid, &attr, DoMonitor, crl) != 0) {
+        WOLFSSL_MSG("Thread creation error");
+        return THREAD_CREATE_E;
+    }
+
+    return SSL_SUCCESS;
+}
+
+
+#else /* HAVE_CRL_MONITOR */
+
+static int StartMonitorCRL(WOLFSSL_CRL* crl)
+{
+    (void)crl;
+
+    WOLFSSL_ENTER("StartMonitorCRL");
+    WOLFSSL_MSG("Not compiled in");
+
+    return NOT_COMPILED_IN;
+}
+
+#endif  /* HAVE_CRL_MONITOR */
+
+
+/* Load CRL path files of type, SSL_SUCCESS on ok */ 
+int LoadCRL(WOLFSSL_CRL* crl, const char* path, int type, int monitor)
+{
+    struct dirent* entry;
+    DIR*           dir;
+    int            ret = SSL_SUCCESS;
+#ifdef WOLFSSL_SMALL_STACK
+    char*          name;
+#else
+    char           name[MAX_FILENAME_SZ];
+#endif
+
+    WOLFSSL_ENTER("LoadCRL");
+    if (crl == NULL)
+        return BAD_FUNC_ARG;
+
+    dir = opendir(path);
+    if (dir == NULL) {
+        WOLFSSL_MSG("opendir path crl load failed");
+        return BAD_PATH_ERROR;
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    name = (char*)XMALLOC(MAX_FILENAME_SZ, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (name == NULL)
+        return MEMORY_E;
+#endif
+
+    while ( (entry = readdir(dir)) != NULL) {
+        struct stat s;
+
+        XMEMSET(name, 0, MAX_FILENAME_SZ);
+        XSTRNCPY(name, path, MAX_FILENAME_SZ/2 - 2);
+        XSTRNCAT(name, "/", 1);
+        XSTRNCAT(name, entry->d_name, MAX_FILENAME_SZ/2);
+
+        if (stat(name, &s) != 0) {
+            WOLFSSL_MSG("stat on name failed");
+            continue;
+        }
+        if (s.st_mode & S_IFREG) {
+
+            if (type == SSL_FILETYPE_PEM) {
+                if (strstr(entry->d_name, ".pem") == NULL) {
+                    WOLFSSL_MSG("not .pem file, skipping");
+                    continue;
+                }
+            }
+            else {
+                if (strstr(entry->d_name, ".der") == NULL &&
+                    strstr(entry->d_name, ".crl") == NULL) {
+
+                    WOLFSSL_MSG("not .der or .crl file, skipping");
+                    continue;
+                }
+            }
+
+            if (ProcessFile(NULL, name, type, CRL_TYPE, NULL, 0, crl)
+                                                               != SSL_SUCCESS) {
+                WOLFSSL_MSG("CRL file load failed, continuing");
+            }
+        }
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(name, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    if (monitor & WOLFSSL_CRL_MONITOR) {
+        WOLFSSL_MSG("monitor path requested");
+
+        if (type == SSL_FILETYPE_PEM) {
+            crl->monitors[0].path = strdup(path);
+            crl->monitors[0].type = SSL_FILETYPE_PEM;
+            if (crl->monitors[0].path == NULL)
+                ret = MEMORY_E;
+        } else {
+            crl->monitors[1].path = strdup(path);
+            crl->monitors[1].type = SSL_FILETYPE_ASN1;
+            if (crl->monitors[1].path == NULL)
+                ret = MEMORY_E;
+        }
+      
+        if (monitor & WOLFSSL_CRL_START_MON) {
+            WOLFSSL_MSG("start monitoring requested");
+    
+            ret = StartMonitorCRL(crl);
+       } 
+    }
+    
+    closedir(dir);
+
+    return ret;
+}
+
+#endif /* HAVE_CRL */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/include.am
new file mode 100644
index 0000000..80ed4de
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/include.am
@@ -0,0 +1,222 @@
+# vim:ft=automake
+# included from Top Level Makefile.am
+# All paths should be given relative to the root
+
+lib_LTLIBRARIES+= src/libwolfssl.la
+src_libwolfssl_la_SOURCES =
+
+src_libwolfssl_la_LDFLAGS = ${AM_LDFLAGS} -no-undefined -version-info ${WOLFSSL_LIBRARY_VERSION}
+src_libwolfssl_la_LIBADD = $(LIBM)
+src_libwolfssl_la_CFLAGS = -DBUILDING_WOLFSSL $(AM_CFLAGS)
+src_libwolfssl_la_CPPFLAGS = -DBUILDING_WOLFSSL $(AM_CPPFLAGS)
+
+# fips first  file
+if BUILD_FIPS
+src_libwolfssl_la_SOURCES += ctaocrypt/src/wolfcrypt_first.c
+
+src_libwolfssl_la_SOURCES += \
+               ctaocrypt/src/hmac.c \
+               ctaocrypt/src/random.c \
+               ctaocrypt/src/sha256.c
+
+if BUILD_RSA
+src_libwolfssl_la_SOURCES += ctaocrypt/src/rsa.c
+endif
+
+if BUILD_AES
+src_libwolfssl_la_SOURCES += ctaocrypt/src/aes.c
+endif
+
+if BUILD_DES3
+src_libwolfssl_la_SOURCES += ctaocrypt/src/des3.c
+endif
+
+if BUILD_SHA
+src_libwolfssl_la_SOURCES += ctaocrypt/src/sha.c
+endif
+
+if BUILD_SHA512
+src_libwolfssl_la_SOURCES += ctaocrypt/src/sha512.c
+endif
+
+src_libwolfssl_la_SOURCES += ctaocrypt/src/fips.c
+src_libwolfssl_la_SOURCES += ctaocrypt/src/fips_test.c
+
+# fips last file
+src_libwolfssl_la_SOURCES += ctaocrypt/src/wolfcrypt_last.c
+endif
+
+src_libwolfssl_la_SOURCES += \
+               wolfcrypt/src/hmac.c \
+               wolfcrypt/src/random.c \
+               wolfcrypt/src/sha256.c \
+               wolfcrypt/src/hash.c
+
+if BUILD_RSA
+src_libwolfssl_la_SOURCES += wolfcrypt/src/rsa.c
+endif
+
+if BUILD_AES
+src_libwolfssl_la_SOURCES += wolfcrypt/src/aes.c
+endif
+
+if BUILD_DES3
+src_libwolfssl_la_SOURCES += wolfcrypt/src/des3.c
+endif
+
+if BUILD_SHA
+src_libwolfssl_la_SOURCES += wolfcrypt/src/sha.c
+endif
+
+if BUILD_SHA512
+src_libwolfssl_la_SOURCES += wolfcrypt/src/sha512.c
+endif
+
+src_libwolfssl_la_SOURCES += \
+               wolfcrypt/src/logging.c \
+               wolfcrypt/src/wc_port.c \
+               wolfcrypt/src/error.c
+
+if BUILD_MEMORY
+src_libwolfssl_la_SOURCES += wolfcrypt/src/memory.c
+endif
+
+if BUILD_DH
+src_libwolfssl_la_SOURCES += wolfcrypt/src/dh.c
+endif
+
+if BUILD_ASN
+src_libwolfssl_la_SOURCES += wolfcrypt/src/asn.c
+endif
+
+if BUILD_CODING
+src_libwolfssl_la_SOURCES += wolfcrypt/src/coding.c
+endif
+
+if BUILD_POLY1305
+src_libwolfssl_la_SOURCES += wolfcrypt/src/poly1305.c
+endif
+
+if BUILD_RC4
+src_libwolfssl_la_SOURCES += wolfcrypt/src/arc4.c
+endif
+
+if BUILD_MD4
+src_libwolfssl_la_SOURCES += wolfcrypt/src/md4.c
+endif
+
+if BUILD_MD5
+src_libwolfssl_la_SOURCES += wolfcrypt/src/md5.c
+endif
+
+if BUILD_PWDBASED
+src_libwolfssl_la_SOURCES += wolfcrypt/src/pwdbased.c
+endif
+
+if BUILD_DSA
+src_libwolfssl_la_SOURCES += wolfcrypt/src/dsa.c
+endif
+
+if BUILD_AESNI
+src_libwolfssl_la_SOURCES += wolfcrypt/src/aes_asm.s
+endif
+
+if BUILD_CAMELLIA
+src_libwolfssl_la_SOURCES += wolfcrypt/src/camellia.c
+endif
+
+if BUILD_MD2
+src_libwolfssl_la_SOURCES += wolfcrypt/src/md2.c
+endif
+
+if BUILD_RIPEMD
+src_libwolfssl_la_SOURCES += wolfcrypt/src/ripemd.c
+endif
+
+if BUILD_BLAKE2
+src_libwolfssl_la_SOURCES += wolfcrypt/src/blake2b.c
+endif
+
+if BUILD_HC128
+src_libwolfssl_la_SOURCES += wolfcrypt/src/hc128.c
+endif
+
+if BUILD_RABBIT
+src_libwolfssl_la_SOURCES += wolfcrypt/src/rabbit.c
+endif
+
+if BUILD_CHACHA
+src_libwolfssl_la_SOURCES += wolfcrypt/src/chacha.c
+if BUILD_POLY1305
+src_libwolfssl_la_SOURCES += wolfcrypt/src/chacha20_poly1305.c
+endif
+endif
+
+if !BUILD_INLINE
+src_libwolfssl_la_SOURCES += wolfcrypt/src/misc.c
+endif
+
+if BUILD_FASTMATH
+src_libwolfssl_la_SOURCES += wolfcrypt/src/tfm.c
+endif
+
+if BUILD_SLOWMATH
+src_libwolfssl_la_SOURCES += wolfcrypt/src/integer.c
+endif
+
+if BUILD_ECC
+src_libwolfssl_la_SOURCES += wolfcrypt/src/ecc.c
+endif
+
+if BUILD_CURVE25519
+src_libwolfssl_la_SOURCES += wolfcrypt/src/curve25519.c
+endif
+
+if BUILD_ED25519
+src_libwolfssl_la_SOURCES += wolfcrypt/src/ed25519.c
+endif
+
+if BUILD_FEMATH
+if BUILD_CURVED25519_SMALL
+src_libwolfssl_la_SOURCES += wolfcrypt/src/fe_low_mem.c
+else
+src_libwolfssl_la_SOURCES += wolfcrypt/src/fe_operations.c
+endif
+endif
+
+if BUILD_GEMATH
+if BUILD_CURVED25519_SMALL
+src_libwolfssl_la_SOURCES += wolfcrypt/src/ge_low_mem.c
+else
+src_libwolfssl_la_SOURCES += wolfcrypt/src/ge_operations.c
+endif
+endif
+
+if BUILD_LIBZ
+src_libwolfssl_la_SOURCES += wolfcrypt/src/compress.c
+endif
+
+if BUILD_PKCS7
+src_libwolfssl_la_SOURCES += wolfcrypt/src/pkcs7.c
+endif
+
+# ssl files
+src_libwolfssl_la_SOURCES += \
+               src/internal.c \
+               src/io.c \
+               src/keys.c \
+               src/ssl.c \
+               src/tls.c
+
+if BUILD_OCSP
+src_libwolfssl_la_SOURCES += src/ocsp.c
+endif
+
+if BUILD_CRL
+src_libwolfssl_la_SOURCES += src/crl.c
+endif
+
+if BUILD_SNIFFER
+src_libwolfssl_la_SOURCES += src/sniffer.c
+endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/internal.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/internal.c
new file mode 100644
index 0000000..75d85b1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/internal.c
@@ -0,0 +1,14388 @@
+/* internal.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+#ifdef HAVE_LIBZ
+    #include "zlib.h"
+#endif
+
+#ifdef HAVE_NTRU
+    #include "ntru_crypto.h"
+#endif
+
+#if defined(DEBUG_WOLFSSL) || defined(SHOW_SECRETS) || defined(CHACHA_AEAD_TEST)
+    #ifdef FREESCALE_MQX
+        #include 
+    #else
+        #include 
+    #endif
+#endif
+
+#ifdef __sun
+    #include 
+#endif
+
+#ifndef TRUE
+    #define TRUE  1
+#endif
+#ifndef FALSE
+    #define FALSE 0
+#endif
+
+#ifdef _MSC_VER
+    /* disable for while(0) cases at the .c level for now */
+    #pragma warning(disable:4127)
+#endif
+
+#if defined(WOLFSSL_CALLBACKS) && !defined(LARGE_STATIC_BUFFERS)
+    #error \
+WOLFSSL_CALLBACKS needs LARGE_STATIC_BUFFERS, please add LARGE_STATIC_BUFFERS
+#endif
+
+#if defined(HAVE_SECURE_RENEGOTIATION) && defined(HAVE_RENEGOTIATION_INDICATION)
+    #error Cannot use both secure-renegotiation and renegotiation-indication
+#endif
+
+static int BuildMessage(WOLFSSL* ssl, byte* output, int outSz,
+                        const byte* input, int inSz, int type);
+
+#ifndef NO_WOLFSSL_CLIENT
+    static int DoHelloVerifyRequest(WOLFSSL* ssl, const byte* input, word32*,
+                                                                        word32);
+    static int DoServerHello(WOLFSSL* ssl, const byte* input, word32*, word32);
+    static int DoServerKeyExchange(WOLFSSL* ssl, const byte* input, word32*,
+                                                                        word32);
+    #ifndef NO_CERTS
+        static int DoCertificateRequest(WOLFSSL* ssl, const byte* input, word32*,
+                                                                        word32);
+    #endif
+    #ifdef HAVE_SESSION_TICKET
+        static int DoSessionTicket(WOLFSSL* ssl, const byte* input, word32*,
+                                                                        word32);
+    #endif
+#endif
+
+
+#ifndef NO_WOLFSSL_SERVER
+    static int DoClientHello(WOLFSSL* ssl, const byte* input, word32*, word32);
+    static int DoClientKeyExchange(WOLFSSL* ssl, byte* input, word32*, word32);
+    #if !defined(NO_RSA) || defined(HAVE_ECC)
+        static int DoCertificateVerify(WOLFSSL* ssl, byte*, word32*, word32);
+    #endif
+#endif
+
+
+#ifdef WOLFSSL_DTLS
+    static INLINE int DtlsCheckWindow(DtlsState* state);
+    static INLINE int DtlsUpdateWindow(DtlsState* state);
+#endif
+
+
+typedef enum {
+    doProcessInit = 0,
+#ifndef NO_WOLFSSL_SERVER
+    runProcessOldClientHello,
+#endif
+    getRecordLayerHeader,
+    getData,
+    runProcessingOneMessage
+} processReply;
+
+#ifndef NO_OLD_TLS
+static int SSL_hmac(WOLFSSL* ssl, byte* digest, const byte* in, word32 sz,
+                    int content, int verify);
+
+#endif
+
+#ifndef NO_CERTS
+static int BuildCertHashes(WOLFSSL* ssl, Hashes* hashes);
+#endif
+
+static void PickHashSigAlgo(WOLFSSL* ssl,
+                                const byte* hashSigAlgo, word32 hashSigAlgoSz);
+
+#ifndef WOLFSSL_HAVE_MIN
+#define WOLFSSL_HAVE_MIN
+
+    static INLINE word32 min(word32 a, word32 b)
+    {
+        return a > b ? b : a;
+    }
+
+#endif /* WOLFSSL_HAVE_MIN */
+
+
+int IsTLS(const WOLFSSL* ssl)
+{
+    if (ssl->version.major == SSLv3_MAJOR && ssl->version.minor >=TLSv1_MINOR)
+        return 1;
+
+    return 0;
+}
+
+
+int IsAtLeastTLSv1_2(const WOLFSSL* ssl)
+{
+    if (ssl->version.major == SSLv3_MAJOR && ssl->version.minor >=TLSv1_2_MINOR)
+        return 1;
+    if (ssl->version.major == DTLS_MAJOR && ssl->version.minor <= DTLSv1_2_MINOR)
+        return 1;
+
+    return 0;
+}
+
+
+#ifdef HAVE_NTRU
+
+static byte GetEntropy(ENTROPY_CMD cmd, byte* out)
+{
+    /* TODO: add locking? */
+    static RNG rng;
+
+    if (cmd == INIT)
+        return (wc_InitRng(&rng) == 0) ? 1 : 0;
+
+    if (out == NULL)
+        return 0;
+
+    if (cmd == GET_BYTE_OF_ENTROPY)
+        return (wc_RNG_GenerateBlock(&rng, out, 1) == 0) ? 1 : 0;
+
+    if (cmd == GET_NUM_BYTES_PER_BYTE_OF_ENTROPY) {
+        *out = 1;
+        return 1;
+    }
+
+    return 0;
+}
+
+#endif /* HAVE_NTRU */
+
+/* used by ssl.c too */
+void c32to24(word32 in, word24 out)
+{
+    out[0] = (in >> 16) & 0xff;
+    out[1] = (in >>  8) & 0xff;
+    out[2] =  in & 0xff;
+}
+
+
+#ifdef WOLFSSL_DTLS
+
+static INLINE void c32to48(word32 in, byte out[6])
+{
+    out[0] = 0;
+    out[1] = 0;
+    out[2] = (in >> 24) & 0xff;
+    out[3] = (in >> 16) & 0xff;
+    out[4] = (in >>  8) & 0xff;
+    out[5] =  in & 0xff;
+}
+
+#endif /* WOLFSSL_DTLS */
+
+
+/* convert 16 bit integer to opaque */
+static INLINE void c16toa(word16 u16, byte* c)
+{
+    c[0] = (u16 >> 8) & 0xff;
+    c[1] =  u16 & 0xff;
+}
+
+
+#if !defined(NO_OLD_TLS) || defined(HAVE_CHACHA) || defined(HAVE_AESCCM) \
+    || defined(HAVE_AESGCM)
+/* convert 32 bit integer to opaque */
+static INLINE void c32toa(word32 u32, byte* c)
+{
+    c[0] = (u32 >> 24) & 0xff;
+    c[1] = (u32 >> 16) & 0xff;
+    c[2] = (u32 >>  8) & 0xff;
+    c[3] =  u32 & 0xff;
+}
+#endif
+
+
+/* convert a 24 bit integer into a 32 bit one */
+static INLINE void c24to32(const word24 u24, word32* u32)
+{
+    *u32 = (u24[0] << 16) | (u24[1] << 8) | u24[2];
+}
+
+
+/* convert opaque to 16 bit integer */
+static INLINE void ato16(const byte* c, word16* u16)
+{
+    *u16 = (word16) ((c[0] << 8) | (c[1]));
+}
+
+
+#if defined(WOLFSSL_DTLS) || defined(HAVE_SESSION_TICKET)
+
+/* convert opaque to 32 bit integer */
+static INLINE void ato32(const byte* c, word32* u32)
+{
+    *u32 = (c[0] << 24) | (c[1] << 16) | (c[2] << 8) | c[3];
+}
+
+#endif /* WOLFSSL_DTLS */
+
+
+#ifdef HAVE_LIBZ
+
+    /* alloc user allocs to work with zlib */
+    static void* myAlloc(void* opaque, unsigned int item, unsigned int size)
+    {
+        (void)opaque;
+        return XMALLOC(item * size, opaque, DYNAMIC_TYPE_LIBZ);
+    }
+
+
+    static void myFree(void* opaque, void* memory)
+    {
+        (void)opaque;
+        XFREE(memory, opaque, DYNAMIC_TYPE_LIBZ);
+    }
+
+
+    /* init zlib comp/decomp streams, 0 on success */
+    static int InitStreams(WOLFSSL* ssl)
+    {
+        ssl->c_stream.zalloc = (alloc_func)myAlloc;
+        ssl->c_stream.zfree  = (free_func)myFree;
+        ssl->c_stream.opaque = (voidpf)ssl->heap;
+
+        if (deflateInit(&ssl->c_stream, Z_DEFAULT_COMPRESSION) != Z_OK)
+            return ZLIB_INIT_ERROR;
+
+        ssl->didStreamInit = 1;
+
+        ssl->d_stream.zalloc = (alloc_func)myAlloc;
+        ssl->d_stream.zfree  = (free_func)myFree;
+        ssl->d_stream.opaque = (voidpf)ssl->heap;
+
+        if (inflateInit(&ssl->d_stream) != Z_OK) return ZLIB_INIT_ERROR;
+
+        return 0;
+    }
+
+
+    static void FreeStreams(WOLFSSL* ssl)
+    {
+        if (ssl->didStreamInit) {
+            deflateEnd(&ssl->c_stream);
+            inflateEnd(&ssl->d_stream);
+        }
+    }
+
+
+    /* compress in to out, return out size or error */
+    static int myCompress(WOLFSSL* ssl, byte* in, int inSz, byte* out, int outSz)
+    {
+        int    err;
+        int    currTotal = (int)ssl->c_stream.total_out;
+
+        ssl->c_stream.next_in   = in;
+        ssl->c_stream.avail_in  = inSz;
+        ssl->c_stream.next_out  = out;
+        ssl->c_stream.avail_out = outSz;
+
+        err = deflate(&ssl->c_stream, Z_SYNC_FLUSH);
+        if (err != Z_OK && err != Z_STREAM_END) return ZLIB_COMPRESS_ERROR;
+
+        return (int)ssl->c_stream.total_out - currTotal;
+    }
+
+
+    /* decompress in to out, returnn out size or error */
+    static int myDeCompress(WOLFSSL* ssl, byte* in,int inSz, byte* out,int outSz)
+    {
+        int    err;
+        int    currTotal = (int)ssl->d_stream.total_out;
+
+        ssl->d_stream.next_in   = in;
+        ssl->d_stream.avail_in  = inSz;
+        ssl->d_stream.next_out  = out;
+        ssl->d_stream.avail_out = outSz;
+
+        err = inflate(&ssl->d_stream, Z_SYNC_FLUSH);
+        if (err != Z_OK && err != Z_STREAM_END) return ZLIB_DECOMPRESS_ERROR;
+
+        return (int)ssl->d_stream.total_out - currTotal;
+    }
+
+#endif /* HAVE_LIBZ */
+
+
+void InitSSL_Method(WOLFSSL_METHOD* method, ProtocolVersion pv)
+{
+    method->version    = pv;
+    method->side       = WOLFSSL_CLIENT_END;
+    method->downgrade  = 0;
+}
+
+
+/* Initialze SSL context, return 0 on success */
+int InitSSL_Ctx(WOLFSSL_CTX* ctx, WOLFSSL_METHOD* method)
+{
+    XMEMSET(ctx, 0, sizeof(WOLFSSL_CTX));
+
+    ctx->method   = method;
+    ctx->refCount = 1;          /* so either CTX_free or SSL_free can release */
+    ctx->heap     = ctx;        /* defaults to self */
+    ctx->timeout  = WOLFSSL_SESSION_TIMEOUT;
+    ctx->minDowngrade = TLSv1_MINOR;     /* current default */
+
+    if (InitMutex(&ctx->countMutex) < 0) {
+        WOLFSSL_MSG("Mutex error on CTX init");
+        return BAD_MUTEX_E;
+    }
+
+#ifndef NO_DH
+    ctx->minDhKeySz = MIN_DHKEY_SZ;
+#endif
+
+#ifdef HAVE_ECC
+    ctx->eccTempKeySz = ECDHE_SIZE;
+#endif
+
+#ifndef WOLFSSL_USER_IO
+    ctx->CBIORecv = EmbedReceive;
+    ctx->CBIOSend = EmbedSend;
+    #ifdef WOLFSSL_DTLS
+        if (method->version.major == DTLS_MAJOR) {
+            ctx->CBIORecv   = EmbedReceiveFrom;
+            ctx->CBIOSend   = EmbedSendTo;
+            ctx->CBIOCookie = EmbedGenerateCookie;
+        }
+    #endif
+#endif /* WOLFSSL_USER_IO */
+
+#ifdef HAVE_NETX
+    ctx->CBIORecv = NetX_Receive;
+    ctx->CBIOSend = NetX_Send;
+#endif
+
+#ifdef HAVE_NTRU
+    if (method->side == WOLFSSL_CLIENT_END)
+        ctx->haveNTRU = 1;           /* always on cliet side */
+                                     /* server can turn on by loading key */
+#endif
+#ifdef HAVE_ECC
+    if (method->side == WOLFSSL_CLIENT_END) {
+        ctx->haveECDSAsig  = 1;        /* always on cliet side */
+        ctx->haveStaticECC = 1;        /* server can turn on by loading key */
+    }
+#endif
+
+#ifdef HAVE_CAVIUM
+    ctx->devId = NO_CAVIUM_DEVICE;
+#endif
+
+#ifndef NO_CERTS
+    ctx->cm = wolfSSL_CertManagerNew();
+    if (ctx->cm == NULL) {
+        WOLFSSL_MSG("Bad Cert Manager New");
+        return BAD_CERT_MANAGER_ERROR;
+    }
+#endif
+
+#if defined(HAVE_SESSION_TICKET) && !defined(NO_WOLFSSL_SERVER)
+    ctx->ticketHint = SESSION_TICKET_HINT_DEFAULT;
+#endif
+
+    return 0;
+}
+
+
+/* In case contexts are held in array and don't want to free actual ctx */
+void SSL_CtxResourceFree(WOLFSSL_CTX* ctx)
+{
+    XFREE(ctx->method, ctx->heap, DYNAMIC_TYPE_METHOD);
+    if (ctx->suites)
+        XFREE(ctx->suites, ctx->heap, DYNAMIC_TYPE_SUITES);
+
+#ifndef NO_DH
+    XFREE(ctx->serverDH_G.buffer, ctx->heap, DYNAMIC_TYPE_DH);
+    XFREE(ctx->serverDH_P.buffer, ctx->heap, DYNAMIC_TYPE_DH);
+#endif
+#ifndef NO_CERTS
+    XFREE(ctx->privateKey.buffer, ctx->heap, DYNAMIC_TYPE_KEY);
+    XFREE(ctx->certificate.buffer, ctx->heap, DYNAMIC_TYPE_CERT);
+    XFREE(ctx->certChain.buffer, ctx->heap, DYNAMIC_TYPE_CERT);
+    wolfSSL_CertManagerFree(ctx->cm);
+#endif
+#ifdef HAVE_TLS_EXTENSIONS
+    TLSX_FreeAll(ctx->extensions);
+#endif
+}
+
+
+void FreeSSL_Ctx(WOLFSSL_CTX* ctx)
+{
+    int doFree = 0;
+
+    if (LockMutex(&ctx->countMutex) != 0) {
+        WOLFSSL_MSG("Couldn't lock count mutex");
+        return;
+    }
+    ctx->refCount--;
+    if (ctx->refCount == 0)
+        doFree = 1;
+    UnLockMutex(&ctx->countMutex);
+
+    if (doFree) {
+        WOLFSSL_MSG("CTX ref count down to 0, doing full free");
+        SSL_CtxResourceFree(ctx);
+        FreeMutex(&ctx->countMutex);
+        XFREE(ctx, ctx->heap, DYNAMIC_TYPE_CTX);
+    }
+    else {
+        (void)ctx;
+        WOLFSSL_MSG("CTX ref count not 0 yet, no free");
+    }
+}
+
+
+/* Set cipher pointers to null */
+void InitCiphers(WOLFSSL* ssl)
+{
+#ifdef BUILD_ARC4
+    ssl->encrypt.arc4 = NULL;
+    ssl->decrypt.arc4 = NULL;
+#endif
+#ifdef BUILD_DES3
+    ssl->encrypt.des3 = NULL;
+    ssl->decrypt.des3 = NULL;
+#endif
+#ifdef BUILD_AES
+    ssl->encrypt.aes = NULL;
+    ssl->decrypt.aes = NULL;
+#endif
+#ifdef HAVE_CAMELLIA
+    ssl->encrypt.cam = NULL;
+    ssl->decrypt.cam = NULL;
+#endif
+#ifdef HAVE_HC128
+    ssl->encrypt.hc128 = NULL;
+    ssl->decrypt.hc128 = NULL;
+#endif
+#ifdef BUILD_RABBIT
+    ssl->encrypt.rabbit = NULL;
+    ssl->decrypt.rabbit = NULL;
+#endif
+#ifdef HAVE_CHACHA
+    ssl->encrypt.chacha = NULL;
+    ssl->decrypt.chacha = NULL;
+#endif
+#ifdef HAVE_POLY1305
+    ssl->auth.poly1305 = NULL;
+#endif
+    ssl->encrypt.setup = 0;
+    ssl->decrypt.setup = 0;
+#ifdef HAVE_ONE_TIME_AUTH
+    ssl->auth.setup    = 0;
+#endif
+}
+
+
+/* Free ciphers */
+void FreeCiphers(WOLFSSL* ssl)
+{
+    (void)ssl;
+#ifdef BUILD_ARC4
+    #ifdef HAVE_CAVIUM
+    if (ssl->devId != NO_CAVIUM_DEVICE) {
+        wc_Arc4FreeCavium(ssl->encrypt.arc4);
+        wc_Arc4FreeCavium(ssl->decrypt.arc4);
+    }
+    #endif
+    XFREE(ssl->encrypt.arc4, ssl->heap, DYNAMIC_TYPE_CIPHER);
+    XFREE(ssl->decrypt.arc4, ssl->heap, DYNAMIC_TYPE_CIPHER);
+#endif
+#ifdef BUILD_DES3
+    #ifdef HAVE_CAVIUM
+    if (ssl->devId != NO_CAVIUM_DEVICE) {
+        wc_Des3_FreeCavium(ssl->encrypt.des3);
+        wc_Des3_FreeCavium(ssl->decrypt.des3);
+    }
+    #endif
+    XFREE(ssl->encrypt.des3, ssl->heap, DYNAMIC_TYPE_CIPHER);
+    XFREE(ssl->decrypt.des3, ssl->heap, DYNAMIC_TYPE_CIPHER);
+#endif
+#ifdef BUILD_AES
+    #ifdef HAVE_CAVIUM
+    if (ssl->devId != NO_CAVIUM_DEVICE) {
+        wc_AesFreeCavium(ssl->encrypt.aes);
+        wc_AesFreeCavium(ssl->decrypt.aes);
+    }
+    #endif
+    XFREE(ssl->encrypt.aes, ssl->heap, DYNAMIC_TYPE_CIPHER);
+    XFREE(ssl->decrypt.aes, ssl->heap, DYNAMIC_TYPE_CIPHER);
+#endif
+#ifdef HAVE_CAMELLIA
+    XFREE(ssl->encrypt.cam, ssl->heap, DYNAMIC_TYPE_CIPHER);
+    XFREE(ssl->decrypt.cam, ssl->heap, DYNAMIC_TYPE_CIPHER);
+#endif
+#ifdef HAVE_HC128
+    XFREE(ssl->encrypt.hc128, ssl->heap, DYNAMIC_TYPE_CIPHER);
+    XFREE(ssl->decrypt.hc128, ssl->heap, DYNAMIC_TYPE_CIPHER);
+#endif
+#ifdef BUILD_RABBIT
+    XFREE(ssl->encrypt.rabbit, ssl->heap, DYNAMIC_TYPE_CIPHER);
+    XFREE(ssl->decrypt.rabbit, ssl->heap, DYNAMIC_TYPE_CIPHER);
+#endif
+#ifdef HAVE_CHACHA
+    XFREE(ssl->encrypt.chacha, ssl->heap, DYNAMIC_TYPE_CIPHER);
+    XFREE(ssl->decrypt.chacha, ssl->heap, DYNAMIC_TYPE_CIPHER);
+#endif
+#ifdef HAVE_POLY1305
+    XFREE(ssl->auth.poly1305, ssl->heap, DYNAMIC_TYPE_CIPHER);
+#endif
+}
+
+
+void InitCipherSpecs(CipherSpecs* cs)
+{
+    cs->bulk_cipher_algorithm = INVALID_BYTE;
+    cs->cipher_type           = INVALID_BYTE;
+    cs->mac_algorithm         = INVALID_BYTE;
+    cs->kea                   = INVALID_BYTE;
+    cs->sig_algo              = INVALID_BYTE;
+
+    cs->hash_size   = 0;
+    cs->static_ecdh = 0;
+    cs->key_size    = 0;
+    cs->iv_size     = 0;
+    cs->block_size  = 0;
+}
+
+static void InitSuitesHashSigAlgo(Suites* suites, int haveECDSAsig,
+                                                  int haveRSAsig, int haveAnon)
+{
+    int idx = 0;
+
+    if (haveECDSAsig) {
+        #ifdef WOLFSSL_SHA512
+            suites->hashSigAlgo[idx++] = sha512_mac;
+            suites->hashSigAlgo[idx++] = ecc_dsa_sa_algo;
+        #endif
+        #ifdef WOLFSSL_SHA384
+            suites->hashSigAlgo[idx++] = sha384_mac;
+            suites->hashSigAlgo[idx++] = ecc_dsa_sa_algo;
+        #endif
+        #ifndef NO_SHA256
+            suites->hashSigAlgo[idx++] = sha256_mac;
+            suites->hashSigAlgo[idx++] = ecc_dsa_sa_algo;
+        #endif
+        #ifndef NO_SHA
+            suites->hashSigAlgo[idx++] = sha_mac;
+            suites->hashSigAlgo[idx++] = ecc_dsa_sa_algo;
+        #endif
+    }
+
+    if (haveRSAsig) {
+        #ifdef WOLFSSL_SHA512
+            suites->hashSigAlgo[idx++] = sha512_mac;
+            suites->hashSigAlgo[idx++] = rsa_sa_algo;
+        #endif
+        #ifdef WOLFSSL_SHA384
+            suites->hashSigAlgo[idx++] = sha384_mac;
+            suites->hashSigAlgo[idx++] = rsa_sa_algo;
+        #endif
+        #ifndef NO_SHA256
+            suites->hashSigAlgo[idx++] = sha256_mac;
+            suites->hashSigAlgo[idx++] = rsa_sa_algo;
+        #endif
+        #ifndef NO_SHA
+            suites->hashSigAlgo[idx++] = sha_mac;
+            suites->hashSigAlgo[idx++] = rsa_sa_algo;
+        #endif
+    }
+
+    if (haveAnon) {
+        #ifdef HAVE_ANON
+            suites->hashSigAlgo[idx++] = sha_mac;
+            suites->hashSigAlgo[idx++] = anonymous_sa_algo;
+        #endif
+    }
+
+    suites->hashSigAlgoSz = (word16)idx;
+}
+
+void InitSuites(Suites* suites, ProtocolVersion pv, word16 haveRSA,
+                word16 havePSK, word16 haveDH, word16 haveNTRU,
+                word16 haveECDSAsig, word16 haveStaticECC, int side)
+{
+    word16 idx = 0;
+    int    tls    = pv.major == SSLv3_MAJOR && pv.minor >= TLSv1_MINOR;
+    int    tls1_2 = pv.major == SSLv3_MAJOR && pv.minor >= TLSv1_2_MINOR;
+    int    haveRSAsig = 1;
+
+    (void)tls;  /* shut up compiler */
+    (void)tls1_2;
+    (void)haveDH;
+    (void)havePSK;
+    (void)haveNTRU;
+    (void)haveStaticECC;
+
+    if (suites == NULL) {
+        WOLFSSL_MSG("InitSuites pointer error");
+        return;
+    }
+
+    if (suites->setSuites)
+        return;      /* trust user settings, don't override */
+
+    if (side == WOLFSSL_SERVER_END && haveStaticECC) {
+        haveRSA = 0;   /* can't do RSA with ECDSA key */
+        (void)haveRSA; /* some builds won't read */
+    }
+
+    if (side == WOLFSSL_SERVER_END && haveECDSAsig) {
+        haveRSAsig = 0;     /* can't have RSA sig if signed by ECDSA */
+        (void)haveRSAsig;   /* non ecc builds won't read */
+    }
+
+#ifdef WOLFSSL_DTLS
+    if (pv.major == DTLS_MAJOR) {
+        tls    = 1;
+        tls1_2 = pv.minor <= DTLSv1_2_MINOR;
+    }
+#endif
+
+#ifdef HAVE_RENEGOTIATION_INDICATION
+    if (side == WOLFSSL_CLIENT_END) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_EMPTY_RENEGOTIATION_INFO_SCSV;
+    }
+#endif
+
+#ifdef BUILD_TLS_NTRU_RSA_WITH_AES_256_CBC_SHA
+    if (tls && haveNTRU && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_NTRU_RSA_WITH_AES_256_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_NTRU_RSA_WITH_AES_128_CBC_SHA
+    if (tls && haveNTRU && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_NTRU_RSA_WITH_AES_128_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_NTRU_RSA_WITH_RC4_128_SHA
+    if (tls && haveNTRU && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_NTRU_RSA_WITH_RC4_128_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_NTRU_RSA_WITH_3DES_EDE_CBC_SHA
+    if (tls && haveNTRU && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_NTRU_RSA_WITH_3DES_EDE_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
+    if (tls1_2 && haveECDSAsig) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
+    if (tls1_2 && haveECDSAsig) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
+    if (tls1_2 && haveRSA) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
+    if (tls1_2 && haveRSA) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
+    if (tls1_2 && haveDH && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_DHE_RSA_WITH_AES_256_GCM_SHA384;
+    }
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
+    if (tls1_2 && haveDH && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_DHE_RSA_WITH_AES_128_GCM_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_256_GCM_SHA384
+    if (tls1_2 && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_RSA_WITH_AES_256_GCM_SHA384;
+    }
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_128_GCM_SHA256
+    if (tls1_2 && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_RSA_WITH_AES_128_GCM_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384
+    if (tls1_2 && haveECDSAsig && haveStaticECC) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256
+    if (tls1_2 && haveECDSAsig && haveStaticECC) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384
+    if (tls1_2 && haveRSAsig && haveStaticECC) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256
+    if (tls1_2 && haveRSAsig && haveStaticECC) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384
+    if (tls1_2 && haveDH && havePSK) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_DHE_PSK_WITH_AES_256_GCM_SHA384;
+    }
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256
+    if (tls1_2 && haveDH && havePSK) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_DHE_PSK_WITH_AES_128_GCM_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_256_GCM_SHA384
+    if (tls1_2 && havePSK) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_PSK_WITH_AES_256_GCM_SHA384;
+    }
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_128_GCM_SHA256
+    if (tls1_2 && havePSK) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_PSK_WITH_AES_128_GCM_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256
+    if (tls1_2 && haveECDSAsig) {
+        suites->suites[idx++] = CHACHA_BYTE;
+        suites->suites[idx++] = TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256
+    if (tls && haveRSA) {
+        suites->suites[idx++] = CHACHA_BYTE;
+        suites->suites[idx++] = TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256
+    if (tls && haveRSA) {
+        suites->suites[idx++] = CHACHA_BYTE;
+        suites->suites[idx++] = TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
+    if (tls1_2 && haveRSAsig) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
+    if (tls1_2 && haveECDSAsig) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256
+    if (tls1_2 && haveRSAsig && haveStaticECC) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256
+    if (tls1_2 && haveECDSAsig && haveStaticECC) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384
+    if (tls1_2 && haveRSAsig) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384
+    if (tls1_2 && haveECDSAsig) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384
+    if (tls1_2 && haveRSAsig && haveStaticECC) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384
+    if (tls1_2 && haveECDSAsig && haveStaticECC) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
+    if (tls && haveECDSAsig) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA
+    if (tls && haveECDSAsig && haveStaticECC) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
+    if (tls && haveECDSAsig) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA
+    if (tls && haveECDSAsig && haveStaticECC) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA
+    if (tls && haveECDSAsig) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDHE_ECDSA_WITH_RC4_128_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_RC4_128_SHA
+    if (tls && haveECDSAsig && haveStaticECC) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDH_ECDSA_WITH_RC4_128_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA
+    if (tls && haveECDSAsig) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA
+    if (tls && haveECDSAsig && haveStaticECC) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
+    if (tls && haveRSA) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA
+    if (tls && haveRSAsig && haveStaticECC) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDH_RSA_WITH_AES_256_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA
+    if (tls && haveRSA) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA
+    if (tls && haveRSAsig && haveStaticECC) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDH_RSA_WITH_AES_128_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_RC4_128_SHA
+    if (tls && haveRSA) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDHE_RSA_WITH_RC4_128_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_RC4_128_SHA
+    if (tls && haveRSAsig && haveStaticECC) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDH_RSA_WITH_RC4_128_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA
+    if (tls && haveRSA) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA
+    if (tls && haveRSAsig && haveStaticECC) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8
+    if (tls1_2 && haveECDSAsig) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8;
+    }
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8
+    if (tls1_2 && haveECDSAsig) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8;
+    }
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_128_CCM_8
+    if (tls1_2 && haveRSA) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_RSA_WITH_AES_128_CCM_8;
+    }
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_256_CCM_8
+    if (tls1_2 && haveRSA) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_RSA_WITH_AES_256_CCM_8;
+    }
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
+    if (tls1_2 && haveDH && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_DHE_RSA_WITH_AES_256_CBC_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256
+    if (tls1_2 && haveDH && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_DHE_RSA_WITH_AES_128_CBC_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
+    if (tls && haveDH && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_DHE_RSA_WITH_AES_256_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_128_CBC_SHA
+    if (tls && haveDH && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_DHE_RSA_WITH_AES_128_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_256_CBC_SHA256
+    if (tls1_2 && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_RSA_WITH_AES_256_CBC_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_128_CBC_SHA256
+    if (tls1_2 && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_RSA_WITH_AES_128_CBC_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_256_CBC_SHA
+    if (tls && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_RSA_WITH_AES_256_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_128_CBC_SHA
+    if (tls && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_RSA_WITH_AES_128_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_NULL_SHA
+    if (tls && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_RSA_WITH_NULL_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_NULL_SHA256
+    if (tls && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_RSA_WITH_NULL_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_256_CBC_SHA
+    if (tls && havePSK) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_PSK_WITH_AES_256_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384
+    if (tls && haveDH && havePSK) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_DHE_PSK_WITH_AES_256_CBC_SHA384;
+    }
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_256_CBC_SHA384
+    if (tls && havePSK) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_PSK_WITH_AES_256_CBC_SHA384;
+    }
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256
+    if (tls && haveDH && havePSK) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_DHE_PSK_WITH_AES_128_CBC_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_128_CBC_SHA256
+    if (tls && havePSK) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_PSK_WITH_AES_128_CBC_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_128_CBC_SHA
+    if (tls && havePSK) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_PSK_WITH_AES_128_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_128_CCM
+    if (tls && haveDH && havePSK) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_DHE_PSK_WITH_AES_128_CCM;
+    }
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_256_CCM
+    if (tls && haveDH && havePSK) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_DHE_PSK_WITH_AES_256_CCM;
+    }
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_128_CCM
+    if (tls && havePSK) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_PSK_WITH_AES_128_CCM;
+    }
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_256_CCM
+    if (tls && havePSK) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_PSK_WITH_AES_256_CCM;
+    }
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_128_CCM_8
+    if (tls && havePSK) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_PSK_WITH_AES_128_CCM_8;
+    }
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_256_CCM_8
+    if (tls && havePSK) {
+        suites->suites[idx++] = ECC_BYTE;
+        suites->suites[idx++] = TLS_PSK_WITH_AES_256_CCM_8;
+    }
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_NULL_SHA384
+    if (tls && haveDH && havePSK) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_DHE_PSK_WITH_NULL_SHA384;
+    }
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_NULL_SHA384
+    if (tls && havePSK) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_PSK_WITH_NULL_SHA384;
+    }
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_NULL_SHA256
+    if (tls && haveDH && havePSK) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_DHE_PSK_WITH_NULL_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_NULL_SHA256
+    if (tls && havePSK) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_PSK_WITH_NULL_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_NULL_SHA
+    if (tls && havePSK) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_PSK_WITH_NULL_SHA;
+    }
+#endif
+
+#ifdef BUILD_SSL_RSA_WITH_RC4_128_SHA
+    if (haveRSA ) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = SSL_RSA_WITH_RC4_128_SHA;
+    }
+#endif
+
+#ifdef BUILD_SSL_RSA_WITH_RC4_128_MD5
+    if (haveRSA ) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = SSL_RSA_WITH_RC4_128_MD5;
+    }
+#endif
+
+#ifdef BUILD_SSL_RSA_WITH_3DES_EDE_CBC_SHA
+    if (haveRSA ) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = SSL_RSA_WITH_3DES_EDE_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_HC_128_MD5
+    if (tls && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_RSA_WITH_HC_128_MD5;
+    }
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_HC_128_SHA
+    if (tls && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_RSA_WITH_HC_128_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_HC_128_B2B256
+    if (tls && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_RSA_WITH_HC_128_B2B256;
+    }
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_128_CBC_B2B256
+    if (tls && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_RSA_WITH_AES_128_CBC_B2B256;
+    }
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_256_CBC_B2B256
+    if (tls && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_RSA_WITH_AES_256_CBC_B2B256;
+    }
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_RABBIT_SHA
+    if (tls && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_RSA_WITH_RABBIT_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA
+    if (tls && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_RSA_WITH_CAMELLIA_128_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA
+    if (tls && haveDH && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA
+    if (tls && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_RSA_WITH_CAMELLIA_256_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_DHE_WITH_RSA_CAMELLIA_256_CBC_SHA
+    if (tls && haveDH && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA;
+    }
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256
+    if (tls && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+    if (tls && haveDH && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256
+    if (tls && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256;
+    }
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256
+    if (tls && haveDH && haveRSA) {
+        suites->suites[idx++] = 0;
+        suites->suites[idx++] = TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256;
+    }
+#endif
+
+    suites->suiteSz = idx;
+
+    InitSuitesHashSigAlgo(suites, haveECDSAsig, haveRSAsig, 0);
+}
+
+
+#ifndef NO_CERTS
+
+
+void InitX509Name(WOLFSSL_X509_NAME* name, int dynamicFlag)
+{
+    (void)dynamicFlag;
+
+    if (name != NULL) {
+        name->name        = name->staticName;
+        name->dynamicName = 0;
+#ifdef OPENSSL_EXTRA
+        XMEMSET(&name->fullName, 0, sizeof(DecodedName));
+#endif /* OPENSSL_EXTRA */
+    }
+}
+
+
+void FreeX509Name(WOLFSSL_X509_NAME* name)
+{
+    if (name != NULL) {
+        if (name->dynamicName)
+            XFREE(name->name, NULL, DYNAMIC_TYPE_SUBJECT_CN);
+#ifdef OPENSSL_EXTRA
+        if (name->fullName.fullName != NULL)
+            XFREE(name->fullName.fullName, NULL, DYNAMIC_TYPE_X509);
+#endif /* OPENSSL_EXTRA */
+    }
+}
+
+
+/* Initialize wolfSSL X509 type */
+void InitX509(WOLFSSL_X509* x509, int dynamicFlag)
+{
+    InitX509Name(&x509->issuer, 0);
+    InitX509Name(&x509->subject, 0);
+    x509->version        = 0;
+    x509->pubKey.buffer  = NULL;
+    x509->sig.buffer     = NULL;
+    x509->derCert.buffer = NULL;
+    x509->altNames       = NULL;
+    x509->altNamesNext   = NULL;
+    x509->dynamicMemory  = (byte)dynamicFlag;
+    x509->isCa           = 0;
+#ifdef HAVE_ECC
+    x509->pkCurveOID = 0;
+#endif /* HAVE_ECC */
+#ifdef OPENSSL_EXTRA
+    x509->pathLength     = 0;
+    x509->basicConstSet  = 0;
+    x509->basicConstCrit = 0;
+    x509->basicConstPlSet = 0;
+    x509->subjAltNameSet = 0;
+    x509->subjAltNameCrit = 0;
+    x509->authKeyIdSet   = 0;
+    x509->authKeyIdCrit  = 0;
+    x509->authKeyId      = NULL;
+    x509->authKeyIdSz    = 0;
+    x509->subjKeyIdSet   = 0;
+    x509->subjKeyIdCrit  = 0;
+    x509->subjKeyId      = NULL;
+    x509->subjKeyIdSz    = 0;
+    x509->keyUsageSet    = 0;
+    x509->keyUsageCrit   = 0;
+    x509->keyUsage       = 0;
+    #ifdef WOLFSSL_SEP
+        x509->certPolicySet  = 0;
+        x509->certPolicyCrit = 0;
+    #endif /* WOLFSSL_SEP */
+#endif /* OPENSSL_EXTRA */
+}
+
+
+/* Free wolfSSL X509 type */
+void FreeX509(WOLFSSL_X509* x509)
+{
+    if (x509 == NULL)
+        return;
+
+    FreeX509Name(&x509->issuer);
+    FreeX509Name(&x509->subject);
+    if (x509->pubKey.buffer)
+        XFREE(x509->pubKey.buffer, NULL, DYNAMIC_TYPE_PUBLIC_KEY);
+    XFREE(x509->derCert.buffer, NULL, DYNAMIC_TYPE_SUBJECT_CN);
+    XFREE(x509->sig.buffer, NULL, DYNAMIC_TYPE_SIGNATURE);
+    #ifdef OPENSSL_EXTRA
+        XFREE(x509->authKeyId, NULL, 0);
+        XFREE(x509->subjKeyId, NULL, 0);
+    #endif /* OPENSSL_EXTRA */
+    if (x509->altNames)
+        FreeAltNames(x509->altNames, NULL);
+    if (x509->dynamicMemory)
+        XFREE(x509, NULL, DYNAMIC_TYPE_X509);
+}
+
+#endif /* NO_CERTS */
+
+
+/* init everything to 0, NULL, default values before calling anything that may
+   fail so that desctructor has a "good" state to cleanup */
+int InitSSL(WOLFSSL* ssl, WOLFSSL_CTX* ctx)
+{
+    int  ret;
+    byte haveRSA = 0;
+    byte havePSK = 0;
+    byte haveAnon = 0;
+
+    (void) haveAnon;
+
+    XMEMSET(ssl, 0, sizeof(WOLFSSL));
+
+    ssl->ctx     = ctx; /* only for passing to calls, options could change */
+    ssl->version = ctx->method->version;
+
+#ifndef NO_RSA
+    haveRSA = 1;
+#endif
+
+    ssl->buffers.inputBuffer.buffer = ssl->buffers.inputBuffer.staticBuffer;
+    ssl->buffers.inputBuffer.bufferSize  = STATIC_BUFFER_LEN;
+
+    ssl->buffers.outputBuffer.buffer = ssl->buffers.outputBuffer.staticBuffer;
+    ssl->buffers.outputBuffer.bufferSize  = STATIC_BUFFER_LEN;
+
+#ifdef KEEP_PEER_CERT
+    InitX509(&ssl->peerCert, 0);
+#endif
+
+#ifdef HAVE_ECC
+    ssl->eccTempKeySz = ctx->eccTempKeySz;
+    ssl->pkCurveOID = ctx->pkCurveOID;
+#endif
+
+    ssl->timeout = ctx->timeout;
+    ssl->rfd = -1;   /* set to invalid descriptor */
+    ssl->wfd = -1;
+
+    ssl->IOCB_ReadCtx  = &ssl->rfd;  /* prevent invalid pointer access if not */
+    ssl->IOCB_WriteCtx = &ssl->wfd;  /* correctly set */
+
+#ifdef HAVE_NETX
+    ssl->IOCB_ReadCtx  = &ssl->nxCtx;  /* default NetX IO ctx, same for read */
+    ssl->IOCB_WriteCtx = &ssl->nxCtx;  /* and write */
+#endif
+#ifdef WOLFSSL_DTLS
+    ssl->dtls_expected_rx = MAX_MTU;
+#endif
+
+    ssl->verifyCallback    = ctx->verifyCallback;
+    ssl->options.side      = ctx->method->side;
+    ssl->options.downgrade    = ctx->method->downgrade;
+    ssl->options.minDowngrade = ctx->minDowngrade;
+
+    if (ssl->options.side == WOLFSSL_SERVER_END)
+        ssl->options.haveDH = ctx->haveDH;
+
+    ssl->options.haveNTRU      = ctx->haveNTRU;
+    ssl->options.haveECDSAsig  = ctx->haveECDSAsig;
+    ssl->options.haveStaticECC = ctx->haveStaticECC;
+
+#ifndef NO_PSK
+    havePSK = ctx->havePSK;
+    ssl->options.havePSK   = ctx->havePSK;
+    ssl->options.client_psk_cb = ctx->client_psk_cb;
+    ssl->options.server_psk_cb = ctx->server_psk_cb;
+#endif /* NO_PSK */
+
+#ifdef HAVE_ANON
+    haveAnon = ctx->haveAnon;
+    ssl->options.haveAnon = ctx->haveAnon;
+#endif
+
+    ssl->options.serverState = NULL_STATE;
+    ssl->options.clientState = NULL_STATE;
+    ssl->options.connectState = CONNECT_BEGIN;
+    ssl->options.acceptState  = ACCEPT_BEGIN;
+    ssl->options.handShakeState  = NULL_STATE;
+    ssl->options.processReply = doProcessInit;
+
+#ifndef NO_DH
+    ssl->options.minDhKeySz = ctx->minDhKeySz;
+#endif
+
+#ifdef WOLFSSL_DTLS
+    ssl->dtls_timeout_init              = DTLS_TIMEOUT_INIT;
+    ssl->dtls_timeout_max               = DTLS_TIMEOUT_MAX;
+    ssl->dtls_timeout                   = ssl->dtls_timeout_init;
+#endif
+
+    ssl->options.sessionCacheOff      = ctx->sessionCacheOff;
+    ssl->options.sessionCacheFlushOff = ctx->sessionCacheFlushOff;
+
+    ssl->options.verifyPeer = ctx->verifyPeer;
+    ssl->options.verifyNone = ctx->verifyNone;
+    ssl->options.failNoCert = ctx->failNoCert;
+    ssl->options.sendVerify = ctx->sendVerify;
+
+    #ifndef NO_OLD_TLS
+        ssl->hmac = SSL_hmac; /* default to SSLv3 */
+    #else
+        ssl->hmac = TLS_hmac;
+    #endif
+
+    ssl->heap = ctx->heap;    /* defaults to self */
+
+    ssl->options.dtls = ssl->version.major == DTLS_MAJOR;
+    ssl->options.partialWrite  = ctx->partialWrite;
+    ssl->options.quietShutdown = ctx->quietShutdown;
+    ssl->options.groupMessages = ctx->groupMessages;
+
+#ifndef NO_DH
+    if (ssl->options.side == WOLFSSL_SERVER_END) {
+        ssl->buffers.serverDH_P = ctx->serverDH_P;
+        ssl->buffers.serverDH_G = ctx->serverDH_G;
+    }
+#endif
+#ifndef NO_CERTS
+    /* ctx still owns certificate, certChain, key, dh, and cm */
+    ssl->buffers.certificate = ctx->certificate;
+    ssl->buffers.certChain = ctx->certChain;
+    ssl->buffers.key = ctx->privateKey;
+#endif
+
+#ifdef WOLFSSL_DTLS
+    ssl->buffers.dtlsCtx.fd = -1;
+#endif
+
+    ssl->cipher.ssl = ssl;
+
+#ifdef HAVE_CAVIUM
+    ssl->devId = ctx->devId;
+#endif
+
+#ifdef HAVE_TLS_EXTENSIONS
+#ifdef HAVE_MAX_FRAGMENT
+    ssl->max_fragment = MAX_RECORD_SIZE;
+#endif
+#endif
+
+    /* default alert state (none) */
+    ssl->alert_history.last_rx.code  = -1;
+    ssl->alert_history.last_rx.level = -1;
+    ssl->alert_history.last_tx.code  = -1;
+    ssl->alert_history.last_tx.level = -1;
+
+    InitCiphers(ssl);
+    InitCipherSpecs(&ssl->specs);
+
+    /* all done with init, now can return errors, call other stuff */
+
+    /* hsHashes */
+    ssl->hsHashes = (HS_Hashes*)XMALLOC(sizeof(HS_Hashes), ssl->heap,
+                                                           DYNAMIC_TYPE_HASHES);
+    if (ssl->hsHashes == NULL) {
+        WOLFSSL_MSG("HS_Hashes Memory error");
+        return MEMORY_E;
+    }
+
+#ifndef NO_OLD_TLS
+#ifndef NO_MD5
+    wc_InitMd5(&ssl->hsHashes->hashMd5);
+#endif
+#ifndef NO_SHA
+    ret = wc_InitSha(&ssl->hsHashes->hashSha);
+    if (ret != 0) {
+        return ret;
+    }
+#endif
+#endif
+#ifndef NO_SHA256
+    ret = wc_InitSha256(&ssl->hsHashes->hashSha256);
+    if (ret != 0) {
+        return ret;
+    }
+#endif
+#ifdef WOLFSSL_SHA384
+    ret = wc_InitSha384(&ssl->hsHashes->hashSha384);
+    if (ret != 0) {
+        return ret;
+    }
+#endif
+#ifdef WOLFSSL_SHA512
+    ret = wc_InitSha512(&ssl->hsHashes->hashSha512);
+    if (ret != 0) {
+        return ret;
+    }
+#endif
+
+    /* increment CTX reference count */
+    if (LockMutex(&ctx->countMutex) != 0) {
+        WOLFSSL_MSG("Couldn't lock CTX count mutex");
+        return BAD_MUTEX_E;
+    }
+    ctx->refCount++;
+    UnLockMutex(&ctx->countMutex);
+
+    /* arrays */
+    ssl->arrays = (Arrays*)XMALLOC(sizeof(Arrays), ssl->heap,
+                                                           DYNAMIC_TYPE_ARRAYS);
+    if (ssl->arrays == NULL) {
+        WOLFSSL_MSG("Arrays Memory error");
+        return MEMORY_E;
+    }
+    XMEMSET(ssl->arrays, 0, sizeof(Arrays));
+
+#ifndef NO_PSK
+    if (ctx->server_hint[0]) {   /* set in CTX */
+        XSTRNCPY(ssl->arrays->server_hint, ctx->server_hint, MAX_PSK_ID_LEN);
+        ssl->arrays->server_hint[MAX_PSK_ID_LEN - 1] = '\0';
+    }
+#endif /* NO_PSK */
+
+    /* RNG */
+    ssl->rng = (RNG*)XMALLOC(sizeof(RNG), ssl->heap, DYNAMIC_TYPE_RNG);
+    if (ssl->rng == NULL) {
+        WOLFSSL_MSG("RNG Memory error");
+        return MEMORY_E;
+    }
+
+    if ( (ret = wc_InitRng(ssl->rng)) != 0) {
+        WOLFSSL_MSG("RNG Init error");
+        return ret;
+    }
+
+    /* suites */
+    ssl->suites = (Suites*)XMALLOC(sizeof(Suites), ssl->heap,
+                                   DYNAMIC_TYPE_SUITES);
+    if (ssl->suites == NULL) {
+        WOLFSSL_MSG("Suites Memory error");
+        return MEMORY_E;
+    }
+    if (ctx->suites)
+        *ssl->suites = *ctx->suites;
+    else
+        XMEMSET(ssl->suites, 0, sizeof(Suites));
+
+
+#ifndef NO_CERTS
+    /* make sure server has cert and key unless using PSK or Anon */
+    if (ssl->options.side == WOLFSSL_SERVER_END && !havePSK && !haveAnon)
+        if (!ssl->buffers.certificate.buffer || !ssl->buffers.key.buffer) {
+            WOLFSSL_MSG("Server missing certificate and/or private key");
+            return NO_PRIVATE_KEY;
+        }
+#endif
+#ifdef HAVE_SECRET_CALLBACK
+    ssl->sessionSecretCb  = NULL;
+    ssl->sessionSecretCtx = NULL;
+#endif
+
+    /* make sure server has DH parms, and add PSK if there, add NTRU too */
+    if (ssl->options.side == WOLFSSL_SERVER_END)
+        InitSuites(ssl->suites, ssl->version, haveRSA, havePSK,
+                   ssl->options.haveDH, ssl->options.haveNTRU,
+                   ssl->options.haveECDSAsig, ssl->options.haveStaticECC,
+                   ssl->options.side);
+    else
+        InitSuites(ssl->suites, ssl->version, haveRSA, havePSK, TRUE,
+                   ssl->options.haveNTRU, ssl->options.haveECDSAsig,
+                   ssl->options.haveStaticECC, ssl->options.side);
+
+    return 0;
+}
+
+
+/* free use of temporary arrays */
+void FreeArrays(WOLFSSL* ssl, int keep)
+{
+    if (ssl->arrays && keep) {
+        /* keeps session id for user retrieval */
+        XMEMCPY(ssl->session.sessionID, ssl->arrays->sessionID, ID_LEN);
+        ssl->session.sessionIDSz = ssl->arrays->sessionIDSz;
+    }
+    XFREE(ssl->arrays, ssl->heap, DYNAMIC_TYPE_ARRAYS);
+    ssl->arrays = NULL;
+}
+
+
+/* In case holding SSL object in array and don't want to free actual ssl */
+void SSL_ResourceFree(WOLFSSL* ssl)
+{
+    /* Note: any resources used during the handshake should be released in the
+     * function FreeHandshakeResources(). Be careful with the special cases
+     * like the RNG which may optionally be kept for the whole session. (For
+     * example with the RNG, it isn't used beyond the handshake except when
+     * using stream ciphers where it is retained. */
+
+    FreeCiphers(ssl);
+    FreeArrays(ssl, 0);
+    wc_FreeRng(ssl->rng);
+    XFREE(ssl->rng, ssl->heap, DYNAMIC_TYPE_RNG);
+    XFREE(ssl->suites, ssl->heap, DYNAMIC_TYPE_SUITES);
+    XFREE(ssl->hsHashes, ssl->heap, DYNAMIC_TYPE_HASHES);
+    XFREE(ssl->buffers.domainName.buffer, ssl->heap, DYNAMIC_TYPE_DOMAIN);
+
+#ifndef NO_DH
+    XFREE(ssl->buffers.serverDH_Priv.buffer, ssl->heap, DYNAMIC_TYPE_DH);
+    XFREE(ssl->buffers.serverDH_Pub.buffer, ssl->heap, DYNAMIC_TYPE_DH);
+    /* parameters (p,g) may be owned by ctx */
+    if (ssl->buffers.weOwnDH || ssl->options.side == WOLFSSL_CLIENT_END) {
+        XFREE(ssl->buffers.serverDH_G.buffer, ssl->heap, DYNAMIC_TYPE_DH);
+        XFREE(ssl->buffers.serverDH_P.buffer, ssl->heap, DYNAMIC_TYPE_DH);
+    }
+#endif
+#ifndef NO_CERTS
+    if (ssl->buffers.weOwnCert)
+        XFREE(ssl->buffers.certificate.buffer, ssl->heap, DYNAMIC_TYPE_CERT);
+    if (ssl->buffers.weOwnCertChain)
+        XFREE(ssl->buffers.certChain.buffer, ssl->heap, DYNAMIC_TYPE_CERT);
+    if (ssl->buffers.weOwnKey)
+        XFREE(ssl->buffers.key.buffer, ssl->heap, DYNAMIC_TYPE_KEY);
+#endif
+#ifndef NO_RSA
+    if (ssl->peerRsaKey) {
+        wc_FreeRsaKey(ssl->peerRsaKey);
+        XFREE(ssl->peerRsaKey, ssl->heap, DYNAMIC_TYPE_RSA);
+    }
+#endif
+    if (ssl->buffers.inputBuffer.dynamicFlag)
+        ShrinkInputBuffer(ssl, FORCED_FREE);
+    if (ssl->buffers.outputBuffer.dynamicFlag)
+        ShrinkOutputBuffer(ssl);
+#ifdef WOLFSSL_DTLS
+    if (ssl->dtls_pool != NULL) {
+        DtlsPoolReset(ssl);
+        XFREE(ssl->dtls_pool, ssl->heap, DYNAMIC_TYPE_NONE);
+    }
+    if (ssl->dtls_msg_list != NULL) {
+        DtlsMsgListDelete(ssl->dtls_msg_list, ssl->heap);
+        ssl->dtls_msg_list = NULL;
+    }
+    XFREE(ssl->buffers.dtlsCtx.peer.sa, ssl->heap, DYNAMIC_TYPE_SOCKADDR);
+    ssl->buffers.dtlsCtx.peer.sa = NULL;
+#endif
+#if defined(KEEP_PEER_CERT) || defined(GOAHEAD_WS)
+    FreeX509(&ssl->peerCert);
+#endif
+#if defined(OPENSSL_EXTRA) || defined(GOAHEAD_WS)
+    wolfSSL_BIO_free(ssl->biord);
+    if (ssl->biord != ssl->biowr)        /* in case same as write */
+        wolfSSL_BIO_free(ssl->biowr);
+#endif
+#ifdef HAVE_LIBZ
+    FreeStreams(ssl);
+#endif
+#ifdef HAVE_ECC
+    if (ssl->peerEccKey) {
+        if (ssl->peerEccKeyPresent)
+            wc_ecc_free(ssl->peerEccKey);
+        XFREE(ssl->peerEccKey, ssl->heap, DYNAMIC_TYPE_ECC);
+    }
+    if (ssl->peerEccDsaKey) {
+        if (ssl->peerEccDsaKeyPresent)
+            wc_ecc_free(ssl->peerEccDsaKey);
+        XFREE(ssl->peerEccDsaKey, ssl->heap, DYNAMIC_TYPE_ECC);
+    }
+    if (ssl->eccTempKey) {
+        if (ssl->eccTempKeyPresent)
+            wc_ecc_free(ssl->eccTempKey);
+        XFREE(ssl->eccTempKey, ssl->heap, DYNAMIC_TYPE_ECC);
+    }
+#endif
+#ifdef HAVE_PK_CALLBACKS
+    #ifdef HAVE_ECC
+        XFREE(ssl->buffers.peerEccDsaKey.buffer, ssl->heap, DYNAMIC_TYPE_ECC);
+    #endif /* HAVE_ECC */
+    #ifndef NO_RSA
+        XFREE(ssl->buffers.peerRsaKey.buffer, ssl->heap, DYNAMIC_TYPE_RSA);
+    #endif /* NO_RSA */
+#endif /* HAVE_PK_CALLBACKS */
+#ifdef HAVE_TLS_EXTENSIONS
+    TLSX_FreeAll(ssl->extensions);
+#endif
+#ifdef HAVE_NETX
+    if (ssl->nxCtx.nxPacket)
+        nx_packet_release(ssl->nxCtx.nxPacket);
+#endif
+}
+
+#ifdef WOLFSSL_TI_HASH
+static void HashFinal(WOLFSSL * ssl) {
+    byte dummyHash[32] ;
+#ifndef NO_MD5
+    wc_Md5Final(&(ssl->hsHashes->hashMd5), dummyHash) ;
+#endif
+#ifndef NO_SHA
+    wc_ShaFinal(&(ssl->hsHashes->hashSha), dummyHash) ;
+#endif
+#ifndef NO_SHA256
+    wc_Sha256Final(&(ssl->hsHashes->hashSha256), dummyHash) ;
+#endif
+}
+#else
+
+    #define HashFinal(ssl)
+
+#endif
+
+/* Free any handshake resources no longer needed */
+void FreeHandshakeResources(WOLFSSL* ssl)
+{
+
+    HashFinal(ssl) ;
+#ifdef HAVE_SECURE_RENEGOTIATION
+    if (ssl->secure_renegotiation && ssl->secure_renegotiation->enabled) {
+        WOLFSSL_MSG("Secure Renegotiation needs to retain handshake resources");
+        return;
+    }
+#endif
+
+    /* input buffer */
+    if (ssl->buffers.inputBuffer.dynamicFlag)
+        ShrinkInputBuffer(ssl, NO_FORCED_FREE);
+
+    /* suites */
+    XFREE(ssl->suites, ssl->heap, DYNAMIC_TYPE_SUITES);
+    ssl->suites = NULL;
+
+    /* hsHashes */
+    XFREE(ssl->hsHashes, ssl->heap, DYNAMIC_TYPE_HASHES);
+    ssl->hsHashes = NULL;
+
+    /* RNG */
+    if (ssl->specs.cipher_type == stream || ssl->options.tls1_1 == 0) {
+        wc_FreeRng(ssl->rng);
+        XFREE(ssl->rng, ssl->heap, DYNAMIC_TYPE_RNG);
+        ssl->rng = NULL;
+    }
+
+#ifdef WOLFSSL_DTLS
+    /* DTLS_POOL */
+    if (ssl->options.dtls && ssl->dtls_pool != NULL) {
+        DtlsPoolReset(ssl);
+        XFREE(ssl->dtls_pool, ssl->heap, DYNAMIC_TYPE_DTLS_POOL);
+        ssl->dtls_pool = NULL;
+    }
+#endif
+
+    /* arrays */
+    if (ssl->options.saveArrays == 0)
+        FreeArrays(ssl, 1);
+
+#ifndef NO_RSA
+    /* peerRsaKey */
+    if (ssl->peerRsaKey) {
+        wc_FreeRsaKey(ssl->peerRsaKey);
+        XFREE(ssl->peerRsaKey, ssl->heap, DYNAMIC_TYPE_RSA);
+        ssl->peerRsaKey = NULL;
+    }
+#endif
+
+#ifdef HAVE_ECC
+    if (ssl->peerEccKey)
+    {
+        if (ssl->peerEccKeyPresent) {
+            wc_ecc_free(ssl->peerEccKey);
+            ssl->peerEccKeyPresent = 0;
+        }
+        XFREE(ssl->peerEccKey, ssl->heap, DYNAMIC_TYPE_ECC);
+        ssl->peerEccKey = NULL;
+    }
+    if (ssl->peerEccDsaKey)
+    {
+        if (ssl->peerEccDsaKeyPresent) {
+            wc_ecc_free(ssl->peerEccDsaKey);
+            ssl->peerEccDsaKeyPresent = 0;
+        }
+        XFREE(ssl->peerEccDsaKey, ssl->heap, DYNAMIC_TYPE_ECC);
+        ssl->peerEccDsaKey = NULL;
+    }
+    if (ssl->eccTempKey)
+    {
+        if (ssl->eccTempKeyPresent) {
+            wc_ecc_free(ssl->eccTempKey);
+            ssl->eccTempKeyPresent = 0;
+        }
+        XFREE(ssl->eccTempKey, ssl->heap, DYNAMIC_TYPE_ECC);
+        ssl->eccTempKey = NULL;
+    }
+#endif
+#ifndef NO_DH
+    XFREE(ssl->buffers.serverDH_Priv.buffer, ssl->heap, DYNAMIC_TYPE_DH);
+    ssl->buffers.serverDH_Priv.buffer = NULL;
+    XFREE(ssl->buffers.serverDH_Pub.buffer, ssl->heap, DYNAMIC_TYPE_DH);
+    ssl->buffers.serverDH_Pub.buffer = NULL;
+    /* parameters (p,g) may be owned by ctx */
+    if (ssl->buffers.weOwnDH || ssl->options.side == WOLFSSL_CLIENT_END) {
+        XFREE(ssl->buffers.serverDH_G.buffer, ssl->heap, DYNAMIC_TYPE_DH);
+        ssl->buffers.serverDH_G.buffer = NULL;
+        XFREE(ssl->buffers.serverDH_P.buffer, ssl->heap, DYNAMIC_TYPE_DH);
+        ssl->buffers.serverDH_P.buffer = NULL;
+    }
+#endif
+#ifndef NO_CERTS
+    if (ssl->buffers.weOwnCert) {
+        XFREE(ssl->buffers.certificate.buffer, ssl->heap, DYNAMIC_TYPE_CERT);
+        ssl->buffers.certificate.buffer = NULL;
+    }
+    if (ssl->buffers.weOwnCertChain) {
+        XFREE(ssl->buffers.certChain.buffer, ssl->heap, DYNAMIC_TYPE_CERT);
+        ssl->buffers.certChain.buffer = NULL;
+    }
+    if (ssl->buffers.weOwnKey) {
+        XFREE(ssl->buffers.key.buffer, ssl->heap, DYNAMIC_TYPE_KEY);
+        ssl->buffers.key.buffer = NULL;
+    }
+#endif
+#ifdef HAVE_PK_CALLBACKS
+    #ifdef HAVE_ECC
+        XFREE(ssl->buffers.peerEccDsaKey.buffer, ssl->heap, DYNAMIC_TYPE_ECC);
+        ssl->buffers.peerEccDsaKey.buffer = NULL;
+    #endif /* HAVE_ECC */
+    #ifndef NO_RSA
+        XFREE(ssl->buffers.peerRsaKey.buffer, ssl->heap, DYNAMIC_TYPE_RSA);
+        ssl->buffers.peerRsaKey.buffer = NULL;
+    #endif /* NO_RSA */
+#endif /* HAVE_PK_CALLBACKS */
+}
+
+
+void FreeSSL(WOLFSSL* ssl)
+{
+    FreeSSL_Ctx(ssl->ctx);  /* will decrement and free underyling CTX if 0 */
+    SSL_ResourceFree(ssl);
+    XFREE(ssl, ssl->heap, DYNAMIC_TYPE_SSL);
+}
+
+
+#ifdef WOLFSSL_DTLS
+
+int DtlsPoolInit(WOLFSSL* ssl)
+{
+    if (ssl->dtls_pool == NULL) {
+        DtlsPool *pool = (DtlsPool*)XMALLOC(sizeof(DtlsPool),
+                                             ssl->heap, DYNAMIC_TYPE_DTLS_POOL);
+        if (pool == NULL) {
+            WOLFSSL_MSG("DTLS Buffer Pool Memory error");
+            return MEMORY_E;
+        }
+        else {
+            int i;
+
+            for (i = 0; i < DTLS_POOL_SZ; i++) {
+                pool->buf[i].length = 0;
+                pool->buf[i].buffer = NULL;
+            }
+            pool->used = 0;
+            ssl->dtls_pool = pool;
+        }
+    }
+    return 0;
+}
+
+
+int DtlsPoolSave(WOLFSSL* ssl, const byte *src, int sz)
+{
+    DtlsPool *pool = ssl->dtls_pool;
+    if (pool != NULL && pool->used < DTLS_POOL_SZ) {
+        buffer *pBuf = &pool->buf[pool->used];
+        pBuf->buffer = (byte*)XMALLOC(sz, ssl->heap, DYNAMIC_TYPE_DTLS_POOL);
+        if (pBuf->buffer == NULL) {
+            WOLFSSL_MSG("DTLS Buffer Memory error");
+            return MEMORY_ERROR;
+        }
+        XMEMCPY(pBuf->buffer, src, sz);
+        pBuf->length = (word32)sz;
+        pool->used++;
+    }
+    return 0;
+}
+
+
+void DtlsPoolReset(WOLFSSL* ssl)
+{
+    DtlsPool *pool = ssl->dtls_pool;
+    if (pool != NULL) {
+        buffer *pBuf;
+        int i, used;
+
+        used = pool->used;
+        for (i = 0, pBuf = &pool->buf[0]; i < used; i++, pBuf++) {
+            XFREE(pBuf->buffer, ssl->heap, DYNAMIC_TYPE_DTLS_POOL);
+            pBuf->buffer = NULL;
+            pBuf->length = 0;
+        }
+        pool->used = 0;
+    }
+    ssl->dtls_timeout = ssl->dtls_timeout_init;
+}
+
+
+int DtlsPoolTimeout(WOLFSSL* ssl)
+{
+    int result = -1;
+    if (ssl->dtls_timeout <  ssl->dtls_timeout_max) {
+        ssl->dtls_timeout *= DTLS_TIMEOUT_MULTIPLIER;
+        result = 0;
+    }
+    return result;
+}
+
+
+int DtlsPoolSend(WOLFSSL* ssl)
+{
+    int ret;
+    DtlsPool *pool = ssl->dtls_pool;
+
+    if (pool != NULL && pool->used > 0) {
+        int i;
+        for (i = 0; i < pool->used; i++) {
+            int sendResult;
+            buffer* buf = &pool->buf[i];
+
+            DtlsRecordLayerHeader* dtls = (DtlsRecordLayerHeader*)buf->buffer;
+
+            word16 message_epoch;
+            ato16(dtls->epoch, &message_epoch);
+            if (message_epoch == ssl->keys.dtls_epoch) {
+                /* Increment record sequence number on retransmitted handshake
+                 * messages */
+                c32to48(ssl->keys.dtls_sequence_number, dtls->sequence_number);
+                ssl->keys.dtls_sequence_number++;
+            }
+            else {
+                /* The Finished message is sent with the next epoch, keep its
+                 * sequence number */
+            }
+
+            if ((ret = CheckAvailableSize(ssl, buf->length)) != 0)
+                return ret;
+
+            XMEMCPY(ssl->buffers.outputBuffer.buffer, buf->buffer, buf->length);
+            ssl->buffers.outputBuffer.idx = 0;
+            ssl->buffers.outputBuffer.length = buf->length;
+
+            sendResult = SendBuffered(ssl);
+            if (sendResult < 0) {
+                return sendResult;
+            }
+        }
+    }
+    return 0;
+}
+
+
+/* functions for managing DTLS datagram reordering */
+
+/* Need to allocate space for the handshake message header. The hashing
+ * routines assume the message pointer is still within the buffer that
+ * has the headers, and will include those headers in the hash. The store
+ * routines need to take that into account as well. New will allocate
+ * extra space for the headers. */
+DtlsMsg* DtlsMsgNew(word32 sz, void* heap)
+{
+    DtlsMsg* msg = NULL;
+
+    msg = (DtlsMsg*)XMALLOC(sizeof(DtlsMsg), heap, DYNAMIC_TYPE_DTLS_MSG);
+
+    if (msg != NULL) {
+        msg->buf = (byte*)XMALLOC(sz + DTLS_HANDSHAKE_HEADER_SZ,
+                                                     heap, DYNAMIC_TYPE_NONE);
+        if (msg->buf != NULL) {
+            msg->next = NULL;
+            msg->seq = 0;
+            msg->sz = sz;
+            msg->fragSz = 0;
+            msg->msg = msg->buf + DTLS_HANDSHAKE_HEADER_SZ;
+        }
+        else {
+            XFREE(msg, heap, DYNAMIC_TYPE_DTLS_MSG);
+            msg = NULL;
+        }
+    }
+
+    return msg;
+}
+
+void DtlsMsgDelete(DtlsMsg* item, void* heap)
+{
+    (void)heap;
+
+    if (item != NULL) {
+        if (item->buf != NULL)
+            XFREE(item->buf, heap, DYNAMIC_TYPE_NONE);
+        XFREE(item, heap, DYNAMIC_TYPE_DTLS_MSG);
+    }
+}
+
+
+void DtlsMsgListDelete(DtlsMsg* head, void* heap)
+{
+    DtlsMsg* next;
+    while (head) {
+        next = head->next;
+        DtlsMsgDelete(head, heap);
+        head = next;
+    }
+}
+
+
+void DtlsMsgSet(DtlsMsg* msg, word32 seq, const byte* data, byte type,
+                                              word32 fragOffset, word32 fragSz)
+{
+    if (msg != NULL && data != NULL && msg->fragSz <= msg->sz &&
+                    fragOffset <= msg->sz && (fragOffset + fragSz) <= msg->sz) {
+
+        msg->seq = seq;
+        msg->type = type;
+        msg->fragSz += fragSz;
+        /* If fragOffset is zero, this is either a full message that is out
+         * of order, or the first fragment of a fragmented message. Copy the
+         * handshake message header with the message data. Zero length messages
+         * like Server Hello Done should be saved as well. */
+        if (fragOffset == 0)
+            XMEMCPY(msg->buf, data - DTLS_HANDSHAKE_HEADER_SZ,
+                                            fragSz + DTLS_HANDSHAKE_HEADER_SZ);
+        else {
+            /* If fragOffet is non-zero, this is an additional fragment that
+             * needs to be copied to its location in the message buffer. Also
+             * copy the total size of the message over the fragment size. The
+             * hash routines look at a defragmented message if it had actually
+             * come across as a single handshake message. */
+            XMEMCPY(msg->msg + fragOffset, data, fragSz);
+        }
+        c32to24(msg->sz, msg->msg - DTLS_HANDSHAKE_FRAG_SZ);
+    }
+}
+
+
+DtlsMsg* DtlsMsgFind(DtlsMsg* head, word32 seq)
+{
+    while (head != NULL && head->seq != seq) {
+        head = head->next;
+    }
+    return head;
+}
+
+
+DtlsMsg* DtlsMsgStore(DtlsMsg* head, word32 seq, const byte* data,
+        word32 dataSz, byte type, word32 fragOffset, word32 fragSz, void* heap)
+{
+
+    /* See if seq exists in the list. If it isn't in the list, make
+     * a new item of size dataSz, copy fragSz bytes from data to msg->msg
+     * starting at offset fragOffset, and add fragSz to msg->fragSz. If
+     * the seq is in the list and it isn't full, copy fragSz bytes from
+     * data to msg->msg starting at offset fragOffset, and add fragSz to
+     * msg->fragSz. The new item should be inserted into the list in its
+     * proper position.
+     *
+     * 1. Find seq in list, or where seq should go in list. If seq not in
+     *    list, create new item and insert into list. Either case, keep
+     *    pointer to item.
+     * 2. If msg->fragSz + fragSz < sz, copy data to msg->msg at offset
+     *    fragOffset. Add fragSz to msg->fragSz.
+     */
+
+    if (head != NULL) {
+        DtlsMsg* cur = DtlsMsgFind(head, seq);
+        if (cur == NULL) {
+            cur = DtlsMsgNew(dataSz, heap);
+            if (cur != NULL) {
+                DtlsMsgSet(cur, seq, data, type, fragOffset, fragSz);
+                head = DtlsMsgInsert(head, cur);
+            }
+        }
+        else {
+            DtlsMsgSet(cur, seq, data, type, fragOffset, fragSz);
+        }
+    }
+    else {
+        head = DtlsMsgNew(dataSz, heap);
+        DtlsMsgSet(head, seq, data, type, fragOffset, fragSz);
+    }
+
+    return head;
+}
+
+
+/* DtlsMsgInsert() is an in-order insert. */
+DtlsMsg* DtlsMsgInsert(DtlsMsg* head, DtlsMsg* item)
+{
+    if (head == NULL || item->seq < head->seq) {
+        item->next = head;
+        head = item;
+    }
+    else if (head->next == NULL) {
+        head->next = item;
+    }
+    else {
+        DtlsMsg* cur = head->next;
+        DtlsMsg* prev = head;
+        while (cur) {
+            if (item->seq < cur->seq) {
+                item->next = cur;
+                prev->next = item;
+                break;
+            }
+            prev = cur;
+            cur = cur->next;
+        }
+        if (cur == NULL) {
+            prev->next = item;
+        }
+    }
+
+    return head;
+}
+
+#endif /* WOLFSSL_DTLS */
+
+#ifndef NO_OLD_TLS
+
+ProtocolVersion MakeSSLv3(void)
+{
+    ProtocolVersion pv;
+    pv.major = SSLv3_MAJOR;
+    pv.minor = SSLv3_MINOR;
+
+    return pv;
+}
+
+#endif /* NO_OLD_TLS */
+
+
+#ifdef WOLFSSL_DTLS
+
+ProtocolVersion MakeDTLSv1(void)
+{
+    ProtocolVersion pv;
+    pv.major = DTLS_MAJOR;
+    pv.minor = DTLS_MINOR;
+
+    return pv;
+}
+
+ProtocolVersion MakeDTLSv1_2(void)
+{
+    ProtocolVersion pv;
+    pv.major = DTLS_MAJOR;
+    pv.minor = DTLSv1_2_MINOR;
+
+    return pv;
+}
+
+#endif /* WOLFSSL_DTLS */
+
+
+
+
+#ifdef USE_WINDOWS_API
+
+    word32 LowResTimer(void)
+    {
+        static int           init = 0;
+        static LARGE_INTEGER freq;
+        LARGE_INTEGER        count;
+
+        if (!init) {
+            QueryPerformanceFrequency(&freq);
+            init = 1;
+        }
+
+        QueryPerformanceCounter(&count);
+
+        return (word32)(count.QuadPart / freq.QuadPart);
+    }
+
+#elif defined(HAVE_RTP_SYS)
+
+    #include "rtptime.h"
+
+    word32 LowResTimer(void)
+    {
+        return (word32)rtp_get_system_sec();
+    }
+
+
+#elif defined(MICRIUM)
+
+    word32 LowResTimer(void)
+    {
+        NET_SECURE_OS_TICK  clk;
+
+        #if (NET_SECURE_MGR_CFG_EN == DEF_ENABLED)
+            clk = NetSecure_OS_TimeGet();
+        #endif
+        return (word32)clk;
+    }
+
+
+#elif defined(MICROCHIP_TCPIP_V5)
+
+    word32 LowResTimer(void)
+    {
+        return (word32) TickGet();
+    }
+
+
+#elif defined(MICROCHIP_TCPIP)
+
+    #if defined(MICROCHIP_MPLAB_HARMONY)
+
+        #include 
+
+        word32 LowResTimer(void)
+        {
+            return (word32) SYS_TMR_TickCountGet();
+        }
+
+    #else
+
+        word32 LowResTimer(void)
+        {
+            return (word32) SYS_TICK_Get();
+        }
+
+    #endif
+
+#elif defined(FREESCALE_MQX)
+
+    word32 LowResTimer(void)
+    {
+        TIME_STRUCT mqxTime;
+
+        _time_get_elapsed(&mqxTime);
+
+        return (word32) mqxTime.SECONDS;
+    }
+
+#elif defined(WOLFSSL_TIRTOS)
+
+    word32 LowResTimer(void)
+    {
+        return (word32) Seconds_get();
+    }
+
+#elif defined(USER_TICKS)
+#if 0
+    word32 LowResTimer(void)
+    {
+        /*
+        write your own clock tick function if don't want time(0)
+        needs second accuracy but doesn't have to correlated to EPOCH
+        */
+    }
+#endif
+
+#elif defined(TIME_OVERRIDES)
+
+    /* use same asn time overrides unless user wants tick override above */
+
+    #ifndef HAVE_TIME_T_TYPE
+        typedef long time_t;
+    #endif
+    extern time_t XTIME(time_t * timer);
+
+    word32 LowResTimer(void)
+    {
+        return (word32) XTIME(0);
+    }
+
+#else /* !USE_WINDOWS_API && !HAVE_RTP_SYS && !MICRIUM && !USER_TICKS */
+
+    #include 
+
+    word32 LowResTimer(void)
+    {
+        return (word32)time(0);
+    }
+
+
+#endif /* USE_WINDOWS_API */
+
+
+/* add output to md5 and sha handshake hashes, exclude record header */
+static int HashOutput(WOLFSSL* ssl, const byte* output, int sz, int ivSz)
+{
+    const byte* adj = output + RECORD_HEADER_SZ + ivSz;
+    sz -= RECORD_HEADER_SZ;
+
+#ifdef HAVE_FUZZER
+    if (ssl->fuzzerCb)
+        ssl->fuzzerCb(ssl, output, sz, FUZZ_HASH, ssl->fuzzerCtx);
+#endif
+#ifdef WOLFSSL_DTLS
+    if (ssl->options.dtls) {
+        adj += DTLS_RECORD_EXTRA;
+        sz  -= DTLS_RECORD_EXTRA;
+    }
+#endif
+#ifndef NO_OLD_TLS
+#ifndef NO_SHA
+    wc_ShaUpdate(&ssl->hsHashes->hashSha, adj, sz);
+#endif
+#ifndef NO_MD5
+    wc_Md5Update(&ssl->hsHashes->hashMd5, adj, sz);
+#endif
+#endif
+
+    if (IsAtLeastTLSv1_2(ssl)) {
+        int ret;
+
+#ifndef NO_SHA256
+        ret = wc_Sha256Update(&ssl->hsHashes->hashSha256, adj, sz);
+        if (ret != 0)
+            return ret;
+#endif
+#ifdef WOLFSSL_SHA384
+        ret = wc_Sha384Update(&ssl->hsHashes->hashSha384, adj, sz);
+        if (ret != 0)
+            return ret;
+#endif
+#ifdef WOLFSSL_SHA512
+        ret = wc_Sha512Update(&ssl->hsHashes->hashSha512, adj, sz);
+        if (ret != 0)
+            return ret;
+#endif
+    }
+
+    return 0;
+}
+
+
+/* add input to md5 and sha handshake hashes, include handshake header */
+static int HashInput(WOLFSSL* ssl, const byte* input, int sz)
+{
+    const byte* adj = input - HANDSHAKE_HEADER_SZ;
+    sz += HANDSHAKE_HEADER_SZ;
+
+#ifdef WOLFSSL_DTLS
+    if (ssl->options.dtls) {
+        adj -= DTLS_HANDSHAKE_EXTRA;
+        sz  += DTLS_HANDSHAKE_EXTRA;
+    }
+#endif
+
+#ifndef NO_OLD_TLS
+#ifndef NO_SHA
+    wc_ShaUpdate(&ssl->hsHashes->hashSha, adj, sz);
+#endif
+#ifndef NO_MD5
+    wc_Md5Update(&ssl->hsHashes->hashMd5, adj, sz);
+#endif
+#endif
+
+    if (IsAtLeastTLSv1_2(ssl)) {
+        int ret;
+
+#ifndef NO_SHA256
+        ret = wc_Sha256Update(&ssl->hsHashes->hashSha256, adj, sz);
+        if (ret != 0)
+            return ret;
+#endif
+#ifdef WOLFSSL_SHA384
+        ret = wc_Sha384Update(&ssl->hsHashes->hashSha384, adj, sz);
+        if (ret != 0)
+            return ret;
+#endif
+#ifdef WOLFSSL_SHA512
+        ret = wc_Sha512Update(&ssl->hsHashes->hashSha512, adj, sz);
+        if (ret != 0)
+            return ret;
+#endif
+    }
+
+    return 0;
+}
+
+
+/* add record layer header for message */
+static void AddRecordHeader(byte* output, word32 length, byte type, WOLFSSL* ssl)
+{
+    RecordLayerHeader* rl;
+
+    /* record layer header */
+    rl = (RecordLayerHeader*)output;
+    rl->type    = type;
+    rl->pvMajor = ssl->version.major;       /* type and version same in each */
+    rl->pvMinor = ssl->version.minor;
+
+    if (!ssl->options.dtls)
+        c16toa((word16)length, rl->length);
+    else {
+#ifdef WOLFSSL_DTLS
+        DtlsRecordLayerHeader* dtls;
+
+        /* dtls record layer header extensions */
+        dtls = (DtlsRecordLayerHeader*)output;
+        c16toa(ssl->keys.dtls_epoch, dtls->epoch);
+        c32to48(ssl->keys.dtls_sequence_number++, dtls->sequence_number);
+        c16toa((word16)length, dtls->length);
+#endif
+    }
+}
+
+
+/* add handshake header for message */
+static void AddHandShakeHeader(byte* output, word32 length, byte type,
+                               WOLFSSL* ssl)
+{
+    HandShakeHeader* hs;
+    (void)ssl;
+
+    /* handshake header */
+    hs = (HandShakeHeader*)output;
+    hs->type = type;
+    c32to24(length, hs->length);         /* type and length same for each */
+#ifdef WOLFSSL_DTLS
+    if (ssl->options.dtls) {
+        DtlsHandShakeHeader* dtls;
+
+        /* dtls handshake header extensions */
+        dtls = (DtlsHandShakeHeader*)output;
+        c16toa(ssl->keys.dtls_handshake_number++, dtls->message_seq);
+        c32to24(0, dtls->fragment_offset);
+        c32to24(length, dtls->fragment_length);
+    }
+#endif
+}
+
+
+/* add both headers for handshake message */
+static void AddHeaders(byte* output, word32 length, byte type, WOLFSSL* ssl)
+{
+    if (!ssl->options.dtls) {
+        AddRecordHeader(output, length + HANDSHAKE_HEADER_SZ, handshake, ssl);
+        AddHandShakeHeader(output + RECORD_HEADER_SZ, length, type, ssl);
+    }
+#ifdef WOLFSSL_DTLS
+    else  {
+        AddRecordHeader(output, length+DTLS_HANDSHAKE_HEADER_SZ, handshake,ssl);
+        AddHandShakeHeader(output + DTLS_RECORD_HEADER_SZ, length, type, ssl);
+    }
+#endif
+}
+
+
+/* return bytes received, -1 on error */
+static int Receive(WOLFSSL* ssl, byte* buf, word32 sz)
+{
+    int recvd;
+
+    if (ssl->ctx->CBIORecv == NULL) {
+        WOLFSSL_MSG("Your IO Recv callback is null, please set");
+        return -1;
+    }
+
+retry:
+    recvd = ssl->ctx->CBIORecv(ssl, (char *)buf, (int)sz, ssl->IOCB_ReadCtx);
+    if (recvd < 0)
+        switch (recvd) {
+            case WOLFSSL_CBIO_ERR_GENERAL:        /* general/unknown error */
+                return -1;
+
+            case WOLFSSL_CBIO_ERR_WANT_READ:      /* want read, would block */
+                return WANT_READ;
+
+            case WOLFSSL_CBIO_ERR_CONN_RST:       /* connection reset */
+                #ifdef USE_WINDOWS_API
+                if (ssl->options.dtls) {
+                    goto retry;
+                }
+                #endif
+                ssl->options.connReset = 1;
+                return -1;
+
+            case WOLFSSL_CBIO_ERR_ISR:            /* interrupt */
+                /* see if we got our timeout */
+                #ifdef WOLFSSL_CALLBACKS
+                    if (ssl->toInfoOn) {
+                        struct itimerval timeout;
+                        getitimer(ITIMER_REAL, &timeout);
+                        if (timeout.it_value.tv_sec == 0 &&
+                                                timeout.it_value.tv_usec == 0) {
+                            XSTRNCPY(ssl->timeoutInfo.timeoutName,
+                                    "recv() timeout", MAX_TIMEOUT_NAME_SZ);
+                            WOLFSSL_MSG("Got our timeout");
+                            return WANT_READ;
+                        }
+                    }
+                #endif
+                goto retry;
+
+            case WOLFSSL_CBIO_ERR_CONN_CLOSE:     /* peer closed connection */
+                ssl->options.isClosed = 1;
+                return -1;
+
+            case WOLFSSL_CBIO_ERR_TIMEOUT:
+#ifdef WOLFSSL_DTLS
+                if (DtlsPoolTimeout(ssl) == 0 && DtlsPoolSend(ssl) == 0)
+                    goto retry;
+                else
+#endif
+                    return -1;
+
+            default:
+                return recvd;
+        }
+
+    return recvd;
+}
+
+
+/* Switch dynamic output buffer back to static, buffer is assumed clear */
+void ShrinkOutputBuffer(WOLFSSL* ssl)
+{
+    WOLFSSL_MSG("Shrinking output buffer\n");
+    XFREE(ssl->buffers.outputBuffer.buffer - ssl->buffers.outputBuffer.offset,
+          ssl->heap, DYNAMIC_TYPE_OUT_BUFFER);
+    ssl->buffers.outputBuffer.buffer = ssl->buffers.outputBuffer.staticBuffer;
+    ssl->buffers.outputBuffer.bufferSize  = STATIC_BUFFER_LEN;
+    ssl->buffers.outputBuffer.dynamicFlag = 0;
+    ssl->buffers.outputBuffer.offset      = 0;
+}
+
+
+/* Switch dynamic input buffer back to static, keep any remaining input */
+/* forced free means cleaning up */
+void ShrinkInputBuffer(WOLFSSL* ssl, int forcedFree)
+{
+    int usedLength = ssl->buffers.inputBuffer.length -
+                     ssl->buffers.inputBuffer.idx;
+    if (!forcedFree && usedLength > STATIC_BUFFER_LEN)
+        return;
+
+    WOLFSSL_MSG("Shrinking input buffer\n");
+
+    if (!forcedFree && usedLength)
+        XMEMCPY(ssl->buffers.inputBuffer.staticBuffer,
+               ssl->buffers.inputBuffer.buffer + ssl->buffers.inputBuffer.idx,
+               usedLength);
+
+    XFREE(ssl->buffers.inputBuffer.buffer - ssl->buffers.inputBuffer.offset,
+          ssl->heap, DYNAMIC_TYPE_IN_BUFFER);
+    ssl->buffers.inputBuffer.buffer = ssl->buffers.inputBuffer.staticBuffer;
+    ssl->buffers.inputBuffer.bufferSize  = STATIC_BUFFER_LEN;
+    ssl->buffers.inputBuffer.dynamicFlag = 0;
+    ssl->buffers.inputBuffer.offset      = 0;
+    ssl->buffers.inputBuffer.idx = 0;
+    ssl->buffers.inputBuffer.length = usedLength;
+}
+
+int SendBuffered(WOLFSSL* ssl)
+{
+    if (ssl->ctx->CBIOSend == NULL) {
+        WOLFSSL_MSG("Your IO Send callback is null, please set");
+        return SOCKET_ERROR_E;
+    }
+
+    while (ssl->buffers.outputBuffer.length > 0) {
+        int sent = ssl->ctx->CBIOSend(ssl,
+                                      (char*)ssl->buffers.outputBuffer.buffer +
+                                      ssl->buffers.outputBuffer.idx,
+                                      (int)ssl->buffers.outputBuffer.length,
+                                      ssl->IOCB_WriteCtx);
+        if (sent < 0) {
+            switch (sent) {
+
+                case WOLFSSL_CBIO_ERR_WANT_WRITE:        /* would block */
+                    return WANT_WRITE;
+
+                case WOLFSSL_CBIO_ERR_CONN_RST:          /* connection reset */
+                    ssl->options.connReset = 1;
+                    break;
+
+                case WOLFSSL_CBIO_ERR_ISR:               /* interrupt */
+                    /* see if we got our timeout */
+                    #ifdef WOLFSSL_CALLBACKS
+                        if (ssl->toInfoOn) {
+                            struct itimerval timeout;
+                            getitimer(ITIMER_REAL, &timeout);
+                            if (timeout.it_value.tv_sec == 0 &&
+                                                timeout.it_value.tv_usec == 0) {
+                                XSTRNCPY(ssl->timeoutInfo.timeoutName,
+                                        "send() timeout", MAX_TIMEOUT_NAME_SZ);
+                                WOLFSSL_MSG("Got our timeout");
+                                return WANT_WRITE;
+                            }
+                        }
+                    #endif
+                    continue;
+
+                case WOLFSSL_CBIO_ERR_CONN_CLOSE: /* epipe / conn closed */
+                    ssl->options.connReset = 1;  /* treat same as reset */
+                    break;
+
+                default:
+                    return SOCKET_ERROR_E;
+            }
+
+            return SOCKET_ERROR_E;
+        }
+
+        if (sent > (int)ssl->buffers.outputBuffer.length) {
+            WOLFSSL_MSG("SendBuffered() out of bounds read");
+            return SEND_OOB_READ_E;
+        }
+
+        ssl->buffers.outputBuffer.idx += sent;
+        ssl->buffers.outputBuffer.length -= sent;
+    }
+
+    ssl->buffers.outputBuffer.idx = 0;
+
+    if (ssl->buffers.outputBuffer.dynamicFlag)
+        ShrinkOutputBuffer(ssl);
+
+    return 0;
+}
+
+
+/* Grow the output buffer */
+static INLINE int GrowOutputBuffer(WOLFSSL* ssl, int size)
+{
+    byte* tmp;
+    byte  hdrSz = ssl->options.dtls ? DTLS_RECORD_HEADER_SZ :
+                                      RECORD_HEADER_SZ;
+    byte  align = WOLFSSL_GENERAL_ALIGNMENT;
+    /* the encrypted data will be offset from the front of the buffer by
+       the header, if the user wants encrypted alignment they need
+       to define their alignment requirement */
+
+    if (align) {
+       while (align < hdrSz)
+           align *= 2;
+    }
+
+    tmp = (byte*) XMALLOC(size + ssl->buffers.outputBuffer.length + align,
+                          ssl->heap, DYNAMIC_TYPE_OUT_BUFFER);
+    WOLFSSL_MSG("growing output buffer\n");
+
+    if (!tmp) return MEMORY_E;
+    if (align)
+        tmp += align - hdrSz;
+
+    if (ssl->buffers.outputBuffer.length)
+        XMEMCPY(tmp, ssl->buffers.outputBuffer.buffer,
+               ssl->buffers.outputBuffer.length);
+
+    if (ssl->buffers.outputBuffer.dynamicFlag)
+        XFREE(ssl->buffers.outputBuffer.buffer -
+              ssl->buffers.outputBuffer.offset, ssl->heap,
+              DYNAMIC_TYPE_OUT_BUFFER);
+    ssl->buffers.outputBuffer.dynamicFlag = 1;
+    if (align)
+        ssl->buffers.outputBuffer.offset = align - hdrSz;
+    else
+        ssl->buffers.outputBuffer.offset = 0;
+    ssl->buffers.outputBuffer.buffer = tmp;
+    ssl->buffers.outputBuffer.bufferSize = size +
+                                           ssl->buffers.outputBuffer.length;
+    return 0;
+}
+
+
+/* Grow the input buffer, should only be to read cert or big app data */
+int GrowInputBuffer(WOLFSSL* ssl, int size, int usedLength)
+{
+    byte* tmp;
+    byte  hdrSz = DTLS_RECORD_HEADER_SZ;
+    byte  align = ssl->options.dtls ? WOLFSSL_GENERAL_ALIGNMENT : 0;
+    /* the encrypted data will be offset from the front of the buffer by
+       the dtls record header, if the user wants encrypted alignment they need
+       to define their alignment requirement. in tls we read record header
+       to get size of record and put actual data back at front, so don't need */
+
+    if (align) {
+       while (align < hdrSz)
+           align *= 2;
+    }
+    tmp = (byte*) XMALLOC(size + usedLength + align, ssl->heap,
+                          DYNAMIC_TYPE_IN_BUFFER);
+    WOLFSSL_MSG("growing input buffer\n");
+
+    if (!tmp) return MEMORY_E;
+    if (align)
+        tmp += align - hdrSz;
+
+    if (usedLength)
+        XMEMCPY(tmp, ssl->buffers.inputBuffer.buffer +
+                    ssl->buffers.inputBuffer.idx, usedLength);
+
+    if (ssl->buffers.inputBuffer.dynamicFlag)
+        XFREE(ssl->buffers.inputBuffer.buffer - ssl->buffers.inputBuffer.offset,
+              ssl->heap,DYNAMIC_TYPE_IN_BUFFER);
+
+    ssl->buffers.inputBuffer.dynamicFlag = 1;
+    if (align)
+        ssl->buffers.inputBuffer.offset = align - hdrSz;
+    else
+        ssl->buffers.inputBuffer.offset = 0;
+    ssl->buffers.inputBuffer.buffer = tmp;
+    ssl->buffers.inputBuffer.bufferSize = size + usedLength;
+    ssl->buffers.inputBuffer.idx    = 0;
+    ssl->buffers.inputBuffer.length = usedLength;
+
+    return 0;
+}
+
+
+/* check available size into output buffer, make room if needed */
+int CheckAvailableSize(WOLFSSL *ssl, int size)
+{
+
+    if (size < 0) {
+        WOLFSSL_MSG("CheckAvailableSize() called with negative number");
+        return BAD_FUNC_ARG;
+    }
+
+    if (ssl->buffers.outputBuffer.bufferSize - ssl->buffers.outputBuffer.length
+                                             < (word32)size) {
+        if (GrowOutputBuffer(ssl, size) < 0)
+            return MEMORY_E;
+    }
+
+    return 0;
+}
+
+
+/* do all verify and sanity checks on record header */
+static int GetRecordHeader(WOLFSSL* ssl, const byte* input, word32* inOutIdx,
+                           RecordLayerHeader* rh, word16 *size)
+{
+    if (!ssl->options.dtls) {
+#ifdef HAVE_FUZZER
+        if (ssl->fuzzerCb)
+            ssl->fuzzerCb(ssl, input + *inOutIdx, RECORD_HEADER_SZ, FUZZ_HEAD,
+                    ssl->fuzzerCtx);
+#endif
+        XMEMCPY(rh, input + *inOutIdx, RECORD_HEADER_SZ);
+        *inOutIdx += RECORD_HEADER_SZ;
+        ato16(rh->length, size);
+    }
+    else {
+#ifdef WOLFSSL_DTLS
+        /* type and version in same sport */
+        XMEMCPY(rh, input + *inOutIdx, ENUM_LEN + VERSION_SZ);
+        *inOutIdx += ENUM_LEN + VERSION_SZ;
+        ato16(input + *inOutIdx, &ssl->keys.dtls_state.curEpoch);
+        *inOutIdx += 4; /* advance past epoch, skip first 2 seq bytes for now */
+        ato32(input + *inOutIdx, &ssl->keys.dtls_state.curSeq);
+        *inOutIdx += 4;  /* advance past rest of seq */
+        ato16(input + *inOutIdx, size);
+        *inOutIdx += LENGTH_SZ;
+#ifdef HAVE_FUZZER
+        if (ssl->fuzzerCb)
+            ssl->fuzzerCb(ssl, input + *inOutIdx - LENGTH_SZ - 8 - ENUM_LEN -
+                           VERSION_SZ, ENUM_LEN + VERSION_SZ + 8 + LENGTH_SZ,
+                           FUZZ_HEAD, ssl->fuzzerCtx);
+#endif
+#endif
+    }
+
+    /* catch version mismatch */
+    if (rh->pvMajor != ssl->version.major || rh->pvMinor != ssl->version.minor){
+        if (ssl->options.side == WOLFSSL_SERVER_END &&
+            ssl->options.acceptState == ACCEPT_BEGIN)
+            WOLFSSL_MSG("Client attempting to connect with different version");
+        else if (ssl->options.side == WOLFSSL_CLIENT_END &&
+                                 ssl->options.downgrade &&
+                                 ssl->options.connectState < FIRST_REPLY_DONE)
+            WOLFSSL_MSG("Server attempting to accept with different version");
+        else {
+            WOLFSSL_MSG("SSL version error");
+            return VERSION_ERROR;              /* only use requested version */
+        }
+    }
+
+#ifdef WOLFSSL_DTLS
+    if (ssl->options.dtls) {
+        if (DtlsCheckWindow(&ssl->keys.dtls_state) != 1)
+            return SEQUENCE_ERROR;
+    }
+#endif
+
+    /* record layer length check */
+#ifdef HAVE_MAX_FRAGMENT
+    if (*size > (ssl->max_fragment + MAX_COMP_EXTRA + MAX_MSG_EXTRA)) {
+        SendAlert(ssl, alert_fatal, record_overflow);
+        return LENGTH_ERROR;
+    }
+#else
+    if (*size > (MAX_RECORD_SIZE + MAX_COMP_EXTRA + MAX_MSG_EXTRA))
+        return LENGTH_ERROR;
+#endif
+
+    /* verify record type here as well */
+    switch (rh->type) {
+        case handshake:
+        case change_cipher_spec:
+        case application_data:
+        case alert:
+            break;
+        case no_type:
+        default:
+            WOLFSSL_MSG("Unknown Record Type");
+            return UNKNOWN_RECORD_TYPE;
+    }
+
+    /* haven't decrypted this record yet */
+    ssl->keys.decryptedCur = 0;
+
+    return 0;
+}
+
+
+static int GetHandShakeHeader(WOLFSSL* ssl, const byte* input, word32* inOutIdx,
+                              byte *type, word32 *size, word32 totalSz)
+{
+    const byte *ptr = input + *inOutIdx;
+    (void)ssl;
+
+    *inOutIdx += HANDSHAKE_HEADER_SZ;
+    if (*inOutIdx > totalSz)
+        return BUFFER_E;
+
+    *type = ptr[0];
+    c24to32(&ptr[1], size);
+
+    return 0;
+}
+
+
+#ifdef WOLFSSL_DTLS
+static int GetDtlsHandShakeHeader(WOLFSSL* ssl, const byte* input,
+                                  word32* inOutIdx, byte *type, word32 *size,
+                                  word32 *fragOffset, word32 *fragSz,
+                                  word32 totalSz)
+{
+    word32 idx = *inOutIdx;
+
+    *inOutIdx += HANDSHAKE_HEADER_SZ + DTLS_HANDSHAKE_EXTRA;
+    if (*inOutIdx > totalSz)
+        return BUFFER_E;
+
+    *type = input[idx++];
+    c24to32(input + idx, size);
+    idx += BYTE3_LEN;
+
+    ato16(input + idx, &ssl->keys.dtls_peer_handshake_number);
+    idx += DTLS_HANDSHAKE_SEQ_SZ;
+
+    c24to32(input + idx, fragOffset);
+    idx += DTLS_HANDSHAKE_FRAG_SZ;
+    c24to32(input + idx, fragSz);
+
+    return 0;
+}
+#endif
+
+
+#ifndef NO_OLD_TLS
+/* fill with MD5 pad size since biggest required */
+static const byte PAD1[PAD_MD5] =
+                              { 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+                                0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+                                0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+                                0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+                                0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
+                                0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36
+                              };
+static const byte PAD2[PAD_MD5] =
+                              { 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c,
+                                0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c,
+                                0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c,
+                                0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c,
+                                0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c,
+                                0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c
+                              };
+
+/* calculate MD5 hash for finished */
+#ifdef WOLFSSL_TI_HASH
+#include 
+#endif
+
+static void BuildMD5(WOLFSSL* ssl, Hashes* hashes, const byte* sender)
+{
+
+    byte md5_result[MD5_DIGEST_SIZE];
+
+#ifdef WOLFSSL_SMALL_STACK
+        Md5* md5   = (Md5*)XMALLOC(sizeof(Md5), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        Md5* md5_2 = (Md5*)XMALLOC(sizeof(Md5), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#else
+        Md5 md5[1];
+        Md5 md5_2[1];
+#endif
+
+    /* make md5 inner */
+    md5[0] = ssl->hsHashes->hashMd5 ; /* Save current position */
+
+    wc_Md5Update(&ssl->hsHashes->hashMd5, sender, SIZEOF_SENDER);
+    wc_Md5Update(&ssl->hsHashes->hashMd5, ssl->arrays->masterSecret,SECRET_LEN);
+    wc_Md5Update(&ssl->hsHashes->hashMd5, PAD1, PAD_MD5);
+    wc_Md5GetHash(&ssl->hsHashes->hashMd5, md5_result);
+    wc_Md5RestorePos(&ssl->hsHashes->hashMd5, md5) ; /* Restore current position */
+
+    /* make md5 outer */
+    wc_InitMd5(md5_2) ;
+    wc_Md5Update(md5_2, ssl->arrays->masterSecret,SECRET_LEN);
+    wc_Md5Update(md5_2, PAD2, PAD_MD5);
+    wc_Md5Update(md5_2, md5_result, MD5_DIGEST_SIZE);
+    wc_Md5Final(md5_2, hashes->md5);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(md5, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(md5_2, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+}
+
+
+/* calculate SHA hash for finished */
+static void BuildSHA(WOLFSSL* ssl, Hashes* hashes, const byte* sender)
+{
+    byte sha_result[SHA_DIGEST_SIZE];
+
+#ifdef WOLFSSL_SMALL_STACK
+        Sha* sha = (Sha*)XMALLOC(sizeof(Sha), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        Sha* sha2 = (Sha*)XMALLOC(sizeof(Sha), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#else
+        Sha sha[1];
+        Sha sha2[1] ;
+#endif
+    /* make sha inner */
+    sha[0] = ssl->hsHashes->hashSha ; /* Save current position */
+
+    wc_ShaUpdate(&ssl->hsHashes->hashSha, sender, SIZEOF_SENDER);
+    wc_ShaUpdate(&ssl->hsHashes->hashSha, ssl->arrays->masterSecret,SECRET_LEN);
+    wc_ShaUpdate(&ssl->hsHashes->hashSha, PAD1, PAD_SHA);
+    wc_ShaGetHash(&ssl->hsHashes->hashSha, sha_result);
+    wc_ShaRestorePos(&ssl->hsHashes->hashSha, sha) ; /* Restore current position */
+
+    /* make sha outer */
+    wc_InitSha(sha2) ;
+    wc_ShaUpdate(sha2, ssl->arrays->masterSecret,SECRET_LEN);
+    wc_ShaUpdate(sha2, PAD2, PAD_SHA);
+    wc_ShaUpdate(sha2, sha_result, SHA_DIGEST_SIZE);
+    wc_ShaFinal(sha2, hashes->sha);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(sha, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(sha2, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+}
+#endif
+
+/* Finished doesn't support SHA512, not SHA512 cipher suites yet */
+static int BuildFinished(WOLFSSL* ssl, Hashes* hashes, const byte* sender)
+{
+    int ret = 0;
+#ifdef WOLFSSL_SMALL_STACK
+    #ifdef WOLFSSL_SHA384
+        Sha384* sha384 = (Sha384*)XMALLOC(sizeof(Sha384), NULL,                                                                        DYNAMIC_TYPE_TMP_BUFFER);
+    #endif
+#else
+    #ifdef WOLFSSL_SHA384
+        Sha384 sha384[1];
+    #endif
+#endif
+
+#ifdef WOLFSSL_SMALL_STACK
+    if (ssl == NULL
+    #ifdef WOLFSSL_SHA384
+        || sha384 == NULL
+    #endif
+        ) {
+    #ifdef WOLFSSL_SHA384
+        XFREE(sha384, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    #endif
+        return MEMORY_E;
+    }
+#endif
+
+    /* store current states, building requires get_digest which resets state */
+#ifdef WOLFSSL_SHA384
+    sha384[0] = ssl->hsHashes->hashSha384;
+#endif
+
+#ifndef NO_TLS
+    if (ssl->options.tls) {
+        ret = BuildTlsFinished(ssl, hashes, sender);
+    }
+#endif
+#ifndef NO_OLD_TLS
+    if (!ssl->options.tls) {
+        BuildMD5(ssl, hashes, sender);
+        BuildSHA(ssl, hashes, sender);
+    }
+#endif
+
+    /* restore */
+    if (IsAtLeastTLSv1_2(ssl)) {
+    #ifdef WOLFSSL_SHA384
+        ssl->hsHashes->hashSha384 = sha384[0];
+    #endif
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+#ifdef WOLFSSL_SHA384
+    XFREE(sha384, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+#endif
+
+    return ret;
+}
+
+
+    /* cipher requirements */
+    enum {
+        REQUIRES_RSA,
+        REQUIRES_DHE,
+        REQUIRES_ECC_DSA,
+        REQUIRES_ECC_STATIC,
+        REQUIRES_PSK,
+        REQUIRES_NTRU,
+        REQUIRES_RSA_SIG
+    };
+
+
+
+    /* Does this cipher suite (first, second) have the requirement
+       an ephemeral key exchange will still require the key for signing
+       the key exchange so ECHDE_RSA requires an rsa key thus rsa_kea */
+    static int CipherRequires(byte first, byte second, int requirement)
+    {
+
+        if (first == CHACHA_BYTE) {
+
+        switch (second) {
+
+        case TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256 :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            break;
+
+        case TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256 :
+            if (requirement == REQUIRES_ECC_DSA)
+                return 1;
+            break;
+
+        case TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256 :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            if (requirement == REQUIRES_DHE)
+                return 1;
+            break;
+            }
+        }
+
+        /* ECC extensions */
+        if (first == ECC_BYTE) {
+
+        switch (second) {
+
+#ifndef NO_RSA
+        case TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            break;
+
+        case TLS_ECDH_RSA_WITH_AES_128_CBC_SHA :
+            if (requirement == REQUIRES_ECC_STATIC)
+                return 1;
+            if (requirement == REQUIRES_RSA_SIG)
+                return 1;
+            break;
+
+#ifndef NO_DES3
+        case TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            break;
+
+        case TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA :
+            if (requirement == REQUIRES_ECC_STATIC)
+                return 1;
+            if (requirement == REQUIRES_RSA_SIG)
+                return 1;
+            break;
+#endif
+
+#ifndef NO_RC4
+        case TLS_ECDHE_RSA_WITH_RC4_128_SHA :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            break;
+
+        case TLS_ECDH_RSA_WITH_RC4_128_SHA :
+            if (requirement == REQUIRES_ECC_STATIC)
+                return 1;
+            if (requirement == REQUIRES_RSA_SIG)
+                return 1;
+            break;
+#endif
+#endif /* NO_RSA */
+
+#ifndef NO_DES3
+        case TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA :
+            if (requirement == REQUIRES_ECC_DSA)
+                return 1;
+            break;
+
+        case TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA :
+            if (requirement == REQUIRES_ECC_STATIC)
+                return 1;
+            break;
+#endif
+#ifndef NO_RC4
+        case TLS_ECDHE_ECDSA_WITH_RC4_128_SHA :
+            if (requirement == REQUIRES_ECC_DSA)
+                return 1;
+            break;
+
+        case TLS_ECDH_ECDSA_WITH_RC4_128_SHA :
+            if (requirement == REQUIRES_ECC_STATIC)
+                return 1;
+            break;
+#endif
+#ifndef NO_RSA
+        case TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            break;
+
+        case TLS_ECDH_RSA_WITH_AES_256_CBC_SHA :
+            if (requirement == REQUIRES_ECC_STATIC)
+                return 1;
+            if (requirement == REQUIRES_RSA_SIG)
+                return 1;
+            break;
+#endif
+
+        case TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA :
+            if (requirement == REQUIRES_ECC_DSA)
+                return 1;
+            break;
+
+        case TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA :
+            if (requirement == REQUIRES_ECC_STATIC)
+                return 1;
+            break;
+
+        case TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA :
+            if (requirement == REQUIRES_ECC_DSA)
+                return 1;
+            break;
+
+        case TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA :
+            if (requirement == REQUIRES_ECC_STATIC)
+                return 1;
+            break;
+
+        case TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 :
+            if (requirement == REQUIRES_ECC_DSA)
+                return 1;
+            break;
+
+        case TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 :
+            if (requirement == REQUIRES_ECC_DSA)
+                return 1;
+            break;
+
+        case TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256 :
+            if (requirement == REQUIRES_ECC_STATIC)
+                return 1;
+            break;
+
+        case TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384 :
+            if (requirement == REQUIRES_ECC_STATIC)
+                return 1;
+            break;
+
+#ifndef NO_RSA
+        case TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            break;
+
+        case TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            break;
+
+        case TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256 :
+            if (requirement == REQUIRES_ECC_STATIC)
+                return 1;
+            if (requirement == REQUIRES_RSA_SIG)
+                return 1;
+            break;
+
+        case TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384 :
+            if (requirement == REQUIRES_ECC_STATIC)
+                return 1;
+            if (requirement == REQUIRES_RSA_SIG)
+                return 1;
+            break;
+
+        case TLS_RSA_WITH_AES_128_CCM_8 :
+        case TLS_RSA_WITH_AES_256_CCM_8 :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            if (requirement == REQUIRES_RSA_SIG)
+                return 1;
+            break;
+
+        case TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 :
+        case TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384 :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            if (requirement == REQUIRES_RSA_SIG)
+                return 1;
+            break;
+
+        case TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256 :
+        case TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384 :
+            if (requirement == REQUIRES_RSA_SIG)
+                return 1;
+            if (requirement == REQUIRES_ECC_STATIC)
+                return 1;
+            break;
+#endif
+
+        case TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8 :
+        case TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8 :
+            if (requirement == REQUIRES_ECC_DSA)
+                return 1;
+            break;
+
+        case TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384 :
+        case TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 :
+            if (requirement == REQUIRES_ECC_DSA)
+                return 1;
+            break;
+
+        case TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256 :
+        case TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384 :
+            if (requirement == REQUIRES_ECC_DSA)
+                return 1;
+            if (requirement == REQUIRES_ECC_STATIC)
+                return 1;
+            break;
+
+        case TLS_PSK_WITH_AES_128_CCM:
+        case TLS_PSK_WITH_AES_256_CCM:
+        case TLS_PSK_WITH_AES_128_CCM_8:
+        case TLS_PSK_WITH_AES_256_CCM_8:
+            if (requirement == REQUIRES_PSK)
+                return 1;
+            break;
+
+        case TLS_DHE_PSK_WITH_AES_128_CCM:
+        case TLS_DHE_PSK_WITH_AES_256_CCM:
+            if (requirement == REQUIRES_PSK)
+                return 1;
+            if (requirement == REQUIRES_DHE)
+                return 1;
+            break;
+
+        default:
+            WOLFSSL_MSG("Unsupported cipher suite, CipherRequires ECC");
+            return 0;
+        }   /* switch */
+        }   /* if     */
+        if (first != ECC_BYTE) {   /* normal suites */
+        switch (second) {
+
+#ifndef NO_RSA
+        case SSL_RSA_WITH_RC4_128_SHA :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            break;
+
+        case TLS_NTRU_RSA_WITH_RC4_128_SHA :
+            if (requirement == REQUIRES_NTRU)
+                return 1;
+            break;
+
+        case SSL_RSA_WITH_RC4_128_MD5 :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            break;
+
+        case SSL_RSA_WITH_3DES_EDE_CBC_SHA :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            break;
+
+        case TLS_NTRU_RSA_WITH_3DES_EDE_CBC_SHA :
+            if (requirement == REQUIRES_NTRU)
+                return 1;
+            break;
+
+        case TLS_RSA_WITH_AES_128_CBC_SHA :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            break;
+
+        case TLS_RSA_WITH_AES_128_CBC_SHA256 :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            break;
+
+        case TLS_NTRU_RSA_WITH_AES_128_CBC_SHA :
+            if (requirement == REQUIRES_NTRU)
+                return 1;
+            break;
+
+        case TLS_RSA_WITH_AES_256_CBC_SHA :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            break;
+
+        case TLS_RSA_WITH_AES_256_CBC_SHA256 :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            break;
+
+        case TLS_RSA_WITH_NULL_SHA :
+        case TLS_RSA_WITH_NULL_SHA256 :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            break;
+
+        case TLS_NTRU_RSA_WITH_AES_256_CBC_SHA :
+            if (requirement == REQUIRES_NTRU)
+                return 1;
+            break;
+#endif
+
+        case TLS_PSK_WITH_AES_128_GCM_SHA256 :
+        case TLS_PSK_WITH_AES_256_GCM_SHA384 :
+        case TLS_PSK_WITH_AES_128_CBC_SHA256 :
+        case TLS_PSK_WITH_AES_256_CBC_SHA384 :
+        case TLS_PSK_WITH_AES_128_CBC_SHA :
+        case TLS_PSK_WITH_AES_256_CBC_SHA :
+        case TLS_PSK_WITH_NULL_SHA384 :
+        case TLS_PSK_WITH_NULL_SHA256 :
+        case TLS_PSK_WITH_NULL_SHA :
+            if (requirement == REQUIRES_PSK)
+                return 1;
+            break;
+
+        case TLS_DHE_PSK_WITH_AES_128_GCM_SHA256 :
+        case TLS_DHE_PSK_WITH_AES_256_GCM_SHA384 :
+        case TLS_DHE_PSK_WITH_AES_128_CBC_SHA256 :
+        case TLS_DHE_PSK_WITH_AES_256_CBC_SHA384 :
+        case TLS_DHE_PSK_WITH_NULL_SHA384 :
+        case TLS_DHE_PSK_WITH_NULL_SHA256 :
+            if (requirement == REQUIRES_DHE)
+                return 1;
+            if (requirement == REQUIRES_PSK)
+                return 1;
+            break;
+
+#ifndef NO_RSA
+        case TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            if (requirement == REQUIRES_DHE)
+                return 1;
+            break;
+
+        case TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            if (requirement == REQUIRES_DHE)
+                return 1;
+            break;
+
+        case TLS_DHE_RSA_WITH_AES_128_CBC_SHA :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            if (requirement == REQUIRES_DHE)
+                return 1;
+            break;
+
+        case TLS_DHE_RSA_WITH_AES_256_CBC_SHA :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            if (requirement == REQUIRES_DHE)
+                return 1;
+            break;
+
+        case TLS_RSA_WITH_HC_128_MD5 :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            break;
+
+        case TLS_RSA_WITH_HC_128_SHA :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            break;
+
+        case TLS_RSA_WITH_HC_128_B2B256:
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            break;
+
+        case TLS_RSA_WITH_AES_128_CBC_B2B256:
+        case TLS_RSA_WITH_AES_256_CBC_B2B256:
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            break;
+
+        case TLS_RSA_WITH_RABBIT_SHA :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            break;
+
+        case TLS_RSA_WITH_AES_128_GCM_SHA256 :
+        case TLS_RSA_WITH_AES_256_GCM_SHA384 :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            break;
+
+        case TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 :
+        case TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            if (requirement == REQUIRES_DHE)
+                return 1;
+            break;
+
+        case TLS_RSA_WITH_CAMELLIA_128_CBC_SHA :
+        case TLS_RSA_WITH_CAMELLIA_256_CBC_SHA :
+        case TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256 :
+        case TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256 :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            break;
+
+        case TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA :
+        case TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA :
+        case TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 :
+        case TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256 :
+            if (requirement == REQUIRES_RSA)
+                return 1;
+            if (requirement == REQUIRES_RSA_SIG)
+                return 1;
+            if (requirement == REQUIRES_DHE)
+                return 1;
+            break;
+#endif
+#ifdef HAVE_ANON
+        case TLS_DH_anon_WITH_AES_128_CBC_SHA :
+            if (requirement == REQUIRES_DHE)
+                return 1;
+            break;
+#endif
+
+        default:
+            WOLFSSL_MSG("Unsupported cipher suite, CipherRequires");
+            return 0;
+        }  /* switch */
+        }  /* if ECC / Normal suites else */
+
+        return 0;
+    }
+
+
+#ifndef NO_CERTS
+
+
+/* Match names with wildcards, each wildcard can represent a single name
+   component or fragment but not mulitple names, i.e.,
+   *.z.com matches y.z.com but not x.y.z.com
+
+   return 1 on success */
+static int MatchDomainName(const char* pattern, int len, const char* str)
+{
+    char p, s;
+
+    if (pattern == NULL || str == NULL || len <= 0)
+        return 0;
+
+    while (len > 0) {
+
+        p = (char)XTOLOWER((unsigned char)*pattern++);
+        if (p == 0)
+            break;
+
+        if (p == '*') {
+            while (--len > 0 &&
+                         (p = (char)XTOLOWER((unsigned char)*pattern++)) == '*')
+                ;
+
+            if (len == 0)
+                p = '\0';
+
+            while ( (s = (char)XTOLOWER((unsigned char) *str)) != '\0') {
+                if (s == p)
+                    break;
+                if (s == '.')
+                    return 0;
+                str++;
+            }
+        }
+        else {
+            if (p != (char)XTOLOWER((unsigned char) *str))
+                return 0;
+        }
+
+        if (*str != '\0')
+            str++;
+
+        if (len > 0)
+            len--;
+    }
+
+    return *str == '\0';
+}
+
+
+/* try to find an altName match to domain, return 1 on success */
+static int CheckAltNames(DecodedCert* dCert, char* domain)
+{
+    int        match = 0;
+    DNS_entry* altName = NULL;
+
+    WOLFSSL_MSG("Checking AltNames");
+
+    if (dCert)
+        altName = dCert->altNames;
+
+    while (altName) {
+        WOLFSSL_MSG("    individual AltName check");
+
+        if (MatchDomainName(altName->name,(int)XSTRLEN(altName->name), domain)){
+            match = 1;
+            break;
+        }
+
+        altName = altName->next;
+    }
+
+    return match;
+}
+
+
+#if defined(KEEP_PEER_CERT) || defined(SESSION_CERTS)
+
+/* Copy parts X509 needs from Decoded cert, 0 on success */
+int CopyDecodedToX509(WOLFSSL_X509* x509, DecodedCert* dCert)
+{
+    int ret = 0;
+
+    if (x509 == NULL || dCert == NULL)
+        return BAD_FUNC_ARG;
+
+    x509->version = dCert->version + 1;
+
+    XSTRNCPY(x509->issuer.name, dCert->issuer, ASN_NAME_MAX);
+    x509->issuer.name[ASN_NAME_MAX - 1] = '\0';
+    x509->issuer.sz = (int)XSTRLEN(x509->issuer.name) + 1;
+#ifdef OPENSSL_EXTRA
+    if (dCert->issuerName.fullName != NULL) {
+        XMEMCPY(&x509->issuer.fullName,
+                                       &dCert->issuerName, sizeof(DecodedName));
+        x509->issuer.fullName.fullName = (char*)XMALLOC(
+                        dCert->issuerName.fullNameLen, NULL, DYNAMIC_TYPE_X509);
+        if (x509->issuer.fullName.fullName != NULL)
+            XMEMCPY(x509->issuer.fullName.fullName,
+                     dCert->issuerName.fullName, dCert->issuerName.fullNameLen);
+    }
+#endif /* OPENSSL_EXTRA */
+
+    XSTRNCPY(x509->subject.name, dCert->subject, ASN_NAME_MAX);
+    x509->subject.name[ASN_NAME_MAX - 1] = '\0';
+    x509->subject.sz = (int)XSTRLEN(x509->subject.name) + 1;
+#ifdef OPENSSL_EXTRA
+    if (dCert->subjectName.fullName != NULL) {
+        XMEMCPY(&x509->subject.fullName,
+                                      &dCert->subjectName, sizeof(DecodedName));
+        x509->subject.fullName.fullName = (char*)XMALLOC(
+                       dCert->subjectName.fullNameLen, NULL, DYNAMIC_TYPE_X509);
+        if (x509->subject.fullName.fullName != NULL)
+            XMEMCPY(x509->subject.fullName.fullName,
+                   dCert->subjectName.fullName, dCert->subjectName.fullNameLen);
+    }
+#endif /* OPENSSL_EXTRA */
+
+    XMEMCPY(x509->serial, dCert->serial, EXTERNAL_SERIAL_SIZE);
+    x509->serialSz = dCert->serialSz;
+    if (dCert->subjectCNLen < ASN_NAME_MAX) {
+        XMEMCPY(x509->subjectCN, dCert->subjectCN, dCert->subjectCNLen);
+        x509->subjectCN[dCert->subjectCNLen] = '\0';
+    }
+    else
+        x509->subjectCN[0] = '\0';
+
+#ifdef WOLFSSL_SEP
+    {
+        int minSz = min(dCert->deviceTypeSz, EXTERNAL_SERIAL_SIZE);
+        if (minSz > 0) {
+            x509->deviceTypeSz = minSz;
+            XMEMCPY(x509->deviceType, dCert->deviceType, minSz);
+        }
+        else
+            x509->deviceTypeSz = 0;
+        minSz = min(dCert->hwTypeSz, EXTERNAL_SERIAL_SIZE);
+        if (minSz != 0) {
+            x509->hwTypeSz = minSz;
+            XMEMCPY(x509->hwType, dCert->hwType, minSz);
+        }
+        else
+            x509->hwTypeSz = 0;
+        minSz = min(dCert->hwSerialNumSz, EXTERNAL_SERIAL_SIZE);
+        if (minSz != 0) {
+            x509->hwSerialNumSz = minSz;
+            XMEMCPY(x509->hwSerialNum, dCert->hwSerialNum, minSz);
+        }
+        else
+            x509->hwSerialNumSz = 0;
+    }
+#endif /* WOLFSSL_SEP */
+    {
+        int minSz = min(dCert->beforeDateLen, MAX_DATE_SZ);
+        if (minSz != 0) {
+            x509->notBeforeSz = minSz;
+            XMEMCPY(x509->notBefore, dCert->beforeDate, minSz);
+        }
+        else
+            x509->notBeforeSz = 0;
+        minSz = min(dCert->afterDateLen, MAX_DATE_SZ);
+        if (minSz != 0) {
+            x509->notAfterSz = minSz;
+            XMEMCPY(x509->notAfter, dCert->afterDate, minSz);
+        }
+        else
+            x509->notAfterSz = 0;
+    }
+
+    if (dCert->publicKey != NULL && dCert->pubKeySize != 0) {
+        x509->pubKey.buffer = (byte*)XMALLOC(
+                              dCert->pubKeySize, NULL, DYNAMIC_TYPE_PUBLIC_KEY);
+        if (x509->pubKey.buffer != NULL) {
+            x509->pubKeyOID = dCert->keyOID;
+            x509->pubKey.length = dCert->pubKeySize;
+            XMEMCPY(x509->pubKey.buffer, dCert->publicKey, dCert->pubKeySize);
+        }
+        else
+            ret = MEMORY_E;
+    }
+
+    if (dCert->signature != NULL && dCert->sigLength != 0) {
+        x509->sig.buffer = (byte*)XMALLOC(
+                                dCert->sigLength, NULL, DYNAMIC_TYPE_SIGNATURE);
+        if (x509->sig.buffer == NULL) {
+            ret = MEMORY_E;
+        }
+        else {
+            XMEMCPY(x509->sig.buffer, dCert->signature, dCert->sigLength);
+            x509->sig.length = dCert->sigLength;
+            x509->sigOID = dCert->signatureOID;
+        }
+    }
+
+    /* store cert for potential retrieval */
+    x509->derCert.buffer = (byte*)XMALLOC(dCert->maxIdx, NULL,
+                                          DYNAMIC_TYPE_CERT);
+    if (x509->derCert.buffer == NULL) {
+        ret = MEMORY_E;
+    }
+    else {
+        XMEMCPY(x509->derCert.buffer, dCert->source, dCert->maxIdx);
+        x509->derCert.length = dCert->maxIdx;
+    }
+
+    x509->altNames       = dCert->altNames;
+    dCert->weOwnAltNames = 0;
+    x509->altNamesNext   = x509->altNames;  /* index hint */
+
+    x509->isCa = dCert->isCA;
+#ifdef OPENSSL_EXTRA
+    x509->pathLength = dCert->pathLength;
+    x509->keyUsage = dCert->extKeyUsage;
+
+    x509->basicConstSet = dCert->extBasicConstSet;
+    x509->basicConstCrit = dCert->extBasicConstCrit;
+    x509->basicConstPlSet = dCert->extBasicConstPlSet;
+    x509->subjAltNameSet = dCert->extSubjAltNameSet;
+    x509->subjAltNameCrit = dCert->extSubjAltNameCrit;
+    x509->authKeyIdSet = dCert->extAuthKeyIdSet;
+    x509->authKeyIdCrit = dCert->extAuthKeyIdCrit;
+    if (dCert->extAuthKeyIdSrc != NULL && dCert->extAuthKeyIdSz != 0) {
+        x509->authKeyId = (byte*)XMALLOC(dCert->extAuthKeyIdSz, NULL, 0);
+        if (x509->authKeyId != NULL) {
+            XMEMCPY(x509->authKeyId,
+                                 dCert->extAuthKeyIdSrc, dCert->extAuthKeyIdSz);
+            x509->authKeyIdSz = dCert->extAuthKeyIdSz;
+        }
+        else
+            ret = MEMORY_E;
+    }
+    x509->subjKeyIdSet = dCert->extSubjKeyIdSet;
+    x509->subjKeyIdCrit = dCert->extSubjKeyIdCrit;
+    if (dCert->extSubjKeyIdSrc != NULL && dCert->extSubjKeyIdSz != 0) {
+        x509->subjKeyId = (byte*)XMALLOC(dCert->extSubjKeyIdSz, NULL, 0);
+        if (x509->subjKeyId != NULL) {
+            XMEMCPY(x509->subjKeyId,
+                                 dCert->extSubjKeyIdSrc, dCert->extSubjKeyIdSz);
+            x509->subjKeyIdSz = dCert->extSubjKeyIdSz;
+        }
+        else
+            ret = MEMORY_E;
+    }
+    x509->keyUsageSet = dCert->extKeyUsageSet;
+    x509->keyUsageCrit = dCert->extKeyUsageCrit;
+    #ifdef WOLFSSL_SEP
+        x509->certPolicySet = dCert->extCertPolicySet;
+        x509->certPolicyCrit = dCert->extCertPolicyCrit;
+    #endif /* WOLFSSL_SEP */
+#endif /* OPENSSL_EXTRA */
+#ifdef HAVE_ECC
+    x509->pkCurveOID = dCert->pkCurveOID;
+#endif /* HAVE_ECC */
+
+    return ret;
+}
+
+#endif /* KEEP_PEER_CERT || SESSION_CERTS */
+
+
+static int DoCertificate(WOLFSSL* ssl, byte* input, word32* inOutIdx,
+                                                                    word32 size)
+{
+    word32 listSz;
+    word32 begin = *inOutIdx;
+    int    ret = 0;
+    int    anyError = 0;
+    int    totalCerts = 0;    /* number of certs in certs buffer */
+    int    count;
+    buffer certs[MAX_CHAIN_DEPTH];
+
+#ifdef WOLFSSL_SMALL_STACK
+    char*                  domain = NULL;
+    DecodedCert*           dCert  = NULL;
+    WOLFSSL_X509_STORE_CTX* store  = NULL;
+#else
+    char                   domain[ASN_NAME_MAX];
+    DecodedCert            dCert[1];
+    WOLFSSL_X509_STORE_CTX  store[1];
+#endif
+
+    #ifdef WOLFSSL_CALLBACKS
+        if (ssl->hsInfoOn) AddPacketName("Certificate", &ssl->handShakeInfo);
+        if (ssl->toInfoOn) AddLateName("Certificate", &ssl->timeoutInfo);
+    #endif
+
+    if ((*inOutIdx - begin) + OPAQUE24_LEN > size)
+        return BUFFER_ERROR;
+
+    c24to32(input + *inOutIdx, &listSz);
+    *inOutIdx += OPAQUE24_LEN;
+
+#ifdef HAVE_MAX_FRAGMENT
+    if (listSz > ssl->max_fragment) {
+        SendAlert(ssl, alert_fatal, record_overflow);
+        return BUFFER_E;
+    }
+#else
+    if (listSz > MAX_RECORD_SIZE)
+        return BUFFER_E;
+#endif
+
+    if ((*inOutIdx - begin) + listSz != size)
+        return BUFFER_ERROR;
+
+    WOLFSSL_MSG("Loading peer's cert chain");
+    /* first put cert chain into buffer so can verify top down
+       we're sent bottom up */
+    while (listSz) {
+        word32 certSz;
+
+        if (totalCerts >= MAX_CHAIN_DEPTH)
+            return MAX_CHAIN_ERROR;
+
+        if ((*inOutIdx - begin) + OPAQUE24_LEN > size)
+            return BUFFER_ERROR;
+
+        c24to32(input + *inOutIdx, &certSz);
+        *inOutIdx += OPAQUE24_LEN;
+
+        if ((*inOutIdx - begin) + certSz > size)
+            return BUFFER_ERROR;
+
+        certs[totalCerts].length = certSz;
+        certs[totalCerts].buffer = input + *inOutIdx;
+
+#ifdef SESSION_CERTS
+        if (ssl->session.chain.count < MAX_CHAIN_DEPTH &&
+                                       certSz < MAX_X509_SIZE) {
+            ssl->session.chain.certs[ssl->session.chain.count].length = certSz;
+            XMEMCPY(ssl->session.chain.certs[ssl->session.chain.count].buffer,
+                    input + *inOutIdx, certSz);
+            ssl->session.chain.count++;
+        } else {
+            WOLFSSL_MSG("Couldn't store chain cert for session");
+        }
+#endif
+
+        *inOutIdx += certSz;
+        listSz -= certSz + CERT_HEADER_SZ;
+
+        totalCerts++;
+        WOLFSSL_MSG("    Put another cert into chain");
+    }
+
+    count = totalCerts;
+
+#ifdef WOLFSSL_SMALL_STACK
+    dCert = (DecodedCert*)XMALLOC(sizeof(DecodedCert), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+    if (dCert == NULL)
+        return MEMORY_E;
+#endif
+
+    /* verify up to peer's first */
+    while (count > 1) {
+        buffer myCert = certs[count - 1];
+        byte* subjectHash;
+
+        InitDecodedCert(dCert, myCert.buffer, myCert.length, ssl->heap);
+        ret = ParseCertRelative(dCert, CERT_TYPE, !ssl->options.verifyNone,
+                                ssl->ctx->cm);
+        #ifndef NO_SKID
+            subjectHash = dCert->extSubjKeyId;
+        #else
+            subjectHash = dCert->subjectHash;
+        #endif
+
+        if (ret == 0 && dCert->isCA == 0) {
+            WOLFSSL_MSG("Chain cert is not a CA, not adding as one");
+        }
+        else if (ret == 0 && ssl->options.verifyNone) {
+            WOLFSSL_MSG("Chain cert not verified by option, not adding as CA");
+        }
+        else if (ret == 0 && !AlreadySigner(ssl->ctx->cm, subjectHash)) {
+            buffer add;
+            add.length = myCert.length;
+            add.buffer = (byte*)XMALLOC(myCert.length, ssl->heap,
+                                        DYNAMIC_TYPE_CA);
+            WOLFSSL_MSG("Adding CA from chain");
+
+            if (add.buffer == NULL)
+                return MEMORY_E;
+            XMEMCPY(add.buffer, myCert.buffer, myCert.length);
+
+            ret = AddCA(ssl->ctx->cm, add, WOLFSSL_CHAIN_CA,
+                        ssl->ctx->verifyPeer);
+            if (ret == 1) ret = 0;   /* SSL_SUCCESS for external */
+        }
+        else if (ret != 0) {
+            WOLFSSL_MSG("Failed to verify CA from chain");
+        }
+        else {
+            WOLFSSL_MSG("Verified CA from chain and already had it");
+        }
+
+#if defined(HAVE_OCSP) || defined(HAVE_CRL)
+        if (ret == 0) {
+            int doCrlLookup = 1;
+            (void)doCrlLookup;
+#ifdef HAVE_OCSP
+            if (ssl->ctx->cm->ocspEnabled && ssl->ctx->cm->ocspCheckAll) {
+                WOLFSSL_MSG("Doing Non Leaf OCSP check");
+                ret = CheckCertOCSP(ssl->ctx->cm->ocsp, dCert);
+                doCrlLookup = (ret == OCSP_CERT_UNKNOWN);
+                if (ret != 0) {
+                    doCrlLookup = 0;
+                    WOLFSSL_MSG("\tOCSP Lookup not ok");
+                }
+            }
+#endif /* HAVE_OCSP */
+
+#ifdef HAVE_CRL
+            if (doCrlLookup && ssl->ctx->cm->crlEnabled
+                                                 && ssl->ctx->cm->crlCheckAll) {
+                WOLFSSL_MSG("Doing Non Leaf CRL check");
+                ret = CheckCertCRL(ssl->ctx->cm->crl, dCert);
+
+                if (ret != 0) {
+                    WOLFSSL_MSG("\tCRL check not ok");
+                }
+            }
+#endif /* HAVE_CRL */
+        }
+#endif /* HAVE_OCSP || HAVE_CRL */
+
+        if (ret != 0 && anyError == 0)
+            anyError = ret;   /* save error from last time */
+
+        FreeDecodedCert(dCert);
+        count--;
+    }
+
+    /* peer's, may not have one if blank client cert sent by TLSv1.2 */
+    if (count) {
+        buffer myCert = certs[0];
+        int    fatal  = 0;
+
+        WOLFSSL_MSG("Verifying Peer's cert");
+
+        InitDecodedCert(dCert, myCert.buffer, myCert.length, ssl->heap);
+        ret = ParseCertRelative(dCert, CERT_TYPE, !ssl->options.verifyNone,
+                                ssl->ctx->cm);
+        if (ret == 0) {
+            WOLFSSL_MSG("Verified Peer's cert");
+            fatal = 0;
+        }
+        else if (ret == ASN_PARSE_E) {
+            WOLFSSL_MSG("Got Peer cert ASN PARSE ERROR, fatal");
+            fatal = 1;
+        }
+        else {
+            WOLFSSL_MSG("Failed to verify Peer's cert");
+            if (ssl->verifyCallback) {
+                WOLFSSL_MSG("\tCallback override available, will continue");
+                fatal = 0;
+            }
+            else {
+                WOLFSSL_MSG("\tNo callback override available, fatal");
+                fatal = 1;
+            }
+        }
+
+#ifdef HAVE_SECURE_RENEGOTIATION
+        if (fatal == 0 && ssl->secure_renegotiation
+                       && ssl->secure_renegotiation->enabled) {
+
+            if (ssl->keys.encryptionOn) {
+                /* compare against previous time */
+                if (XMEMCMP(dCert->subjectHash,
+                            ssl->secure_renegotiation->subject_hash,
+                            SHA_DIGEST_SIZE) != 0) {
+                    WOLFSSL_MSG("Peer sent different cert during scr, fatal");
+                    fatal = 1;
+                    ret   = SCR_DIFFERENT_CERT_E;
+                }
+            }
+
+            /* cache peer's hash */
+            if (fatal == 0) {
+                XMEMCPY(ssl->secure_renegotiation->subject_hash,
+                        dCert->subjectHash, SHA_DIGEST_SIZE);
+            }
+        }
+#endif
+
+#if defined(HAVE_OCSP) || defined(HAVE_CRL)
+        if (fatal == 0) {
+            int doCrlLookup = 1;
+            (void)doCrlLookup;
+#ifdef HAVE_OCSP
+            if (ssl->ctx->cm->ocspEnabled) {
+                ret = CheckCertOCSP(ssl->ctx->cm->ocsp, dCert);
+                doCrlLookup = (ret == OCSP_CERT_UNKNOWN);
+                if (ret != 0) {
+                    WOLFSSL_MSG("\tOCSP Lookup not ok");
+                    fatal = 0;
+                }
+            }
+#endif /* HAVE_OCSP */
+
+#ifdef HAVE_CRL
+            if (doCrlLookup && ssl->ctx->cm->crlEnabled) {
+                WOLFSSL_MSG("Doing Leaf CRL check");
+                ret = CheckCertCRL(ssl->ctx->cm->crl, dCert);
+                if (ret != 0) {
+                    WOLFSSL_MSG("\tCRL check not ok");
+                    fatal = 0;
+                }
+            }
+#endif /* HAVE_CRL */
+        }
+#endif /* HAVE_OCSP || HAVE_CRL */
+
+#ifdef KEEP_PEER_CERT
+        {
+        /* set X509 format for peer cert even if fatal */
+        int copyRet = CopyDecodedToX509(&ssl->peerCert, dCert);
+        if (copyRet == MEMORY_E)
+            fatal = 1;
+        }
+#endif
+
+#ifndef IGNORE_KEY_EXTENSIONS
+        if (dCert->extKeyUsageSet) {
+            if ((ssl->specs.kea == rsa_kea) &&
+                (dCert->extKeyUsage & KEYUSE_KEY_ENCIPHER) == 0) {
+                ret = KEYUSE_ENCIPHER_E;
+            }
+            if ((ssl->specs.sig_algo == rsa_sa_algo ||
+                    (ssl->specs.sig_algo == ecc_dsa_sa_algo &&
+                         !ssl->specs.static_ecdh)) &&
+                (dCert->extKeyUsage & KEYUSE_DIGITAL_SIG) == 0) {
+                WOLFSSL_MSG("KeyUse Digital Sig not set");
+                ret = KEYUSE_SIGNATURE_E;
+            }
+        }
+
+        if (dCert->extExtKeyUsageSet) {
+            if (ssl->options.side == WOLFSSL_CLIENT_END) {
+                if ((dCert->extExtKeyUsage &
+                        (EXTKEYUSE_ANY | EXTKEYUSE_SERVER_AUTH)) == 0) {
+                    WOLFSSL_MSG("ExtKeyUse Server Auth not set");
+                    ret = EXTKEYUSE_AUTH_E;
+                }
+            }
+            else {
+                if ((dCert->extExtKeyUsage &
+                        (EXTKEYUSE_ANY | EXTKEYUSE_CLIENT_AUTH)) == 0) {
+                    WOLFSSL_MSG("ExtKeyUse Client Auth not set");
+                    ret = EXTKEYUSE_AUTH_E;
+                }
+            }
+        }
+#endif /* IGNORE_KEY_EXTENSIONS */
+
+        if (fatal) {
+            FreeDecodedCert(dCert);
+        #ifdef WOLFSSL_SMALL_STACK
+            XFREE(dCert, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        #endif
+            ssl->error = ret;
+            return ret;
+        }
+        ssl->options.havePeerCert = 1;
+
+#ifdef WOLFSSL_SMALL_STACK
+        domain = (char*)XMALLOC(ASN_NAME_MAX, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (domain == NULL) {
+            FreeDecodedCert(dCert);
+            XFREE(dCert, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            return MEMORY_E;
+        }
+#endif
+        /* store for callback use */
+        if (dCert->subjectCNLen < ASN_NAME_MAX) {
+            XMEMCPY(domain, dCert->subjectCN, dCert->subjectCNLen);
+            domain[dCert->subjectCNLen] = '\0';
+        }
+        else
+            domain[0] = '\0';
+
+        if (!ssl->options.verifyNone && ssl->buffers.domainName.buffer) {
+            if (MatchDomainName(dCert->subjectCN, dCert->subjectCNLen,
+                                (char*)ssl->buffers.domainName.buffer) == 0) {
+                WOLFSSL_MSG("DomainName match on common name failed");
+                if (CheckAltNames(dCert,
+                                 (char*)ssl->buffers.domainName.buffer) == 0 ) {
+                    WOLFSSL_MSG("DomainName match on alt names failed too");
+                    ret = DOMAIN_NAME_MISMATCH; /* try to get peer key still */
+                }
+            }
+        }
+
+        /* decode peer key */
+        switch (dCert->keyOID) {
+        #ifndef NO_RSA
+            case RSAk:
+                {
+                    word32 idx = 0;
+                    int    keyRet = 0;
+
+                    if (ssl->peerRsaKey == NULL) {
+                        ssl->peerRsaKey = (RsaKey*)XMALLOC(sizeof(RsaKey),
+                                                   ssl->heap, DYNAMIC_TYPE_RSA);
+                        if (ssl->peerRsaKey == NULL) {
+                            WOLFSSL_MSG("PeerRsaKey Memory error");
+                            keyRet = MEMORY_E;
+                        } else {
+                            keyRet = wc_InitRsaKey(ssl->peerRsaKey,
+                                                   ssl->ctx->heap);
+                        }
+                    } else if (ssl->peerRsaKeyPresent) {
+                        /* don't leak on reuse */
+                        wc_FreeRsaKey(ssl->peerRsaKey);
+                        ssl->peerRsaKeyPresent = 0;
+                        keyRet = wc_InitRsaKey(ssl->peerRsaKey, ssl->heap);
+                    }
+
+                    if (keyRet != 0 || wc_RsaPublicKeyDecode(dCert->publicKey,
+                               &idx, ssl->peerRsaKey, dCert->pubKeySize) != 0) {
+                        ret = PEER_KEY_ERROR;
+                    }
+                    else {
+                        ssl->peerRsaKeyPresent = 1;
+                        #ifdef HAVE_PK_CALLBACKS
+                            #ifndef NO_RSA
+                                ssl->buffers.peerRsaKey.buffer =
+                                       (byte*)XMALLOC(dCert->pubKeySize,
+                                               ssl->heap, DYNAMIC_TYPE_RSA);
+                                if (ssl->buffers.peerRsaKey.buffer == NULL)
+                                    ret = MEMORY_ERROR;
+                                else {
+                                    XMEMCPY(ssl->buffers.peerRsaKey.buffer,
+                                           dCert->publicKey, dCert->pubKeySize);
+                                    ssl->buffers.peerRsaKey.length =
+                                            dCert->pubKeySize;
+                                }
+                            #endif /* NO_RSA */
+                        #endif /*HAVE_PK_CALLBACKS */
+                    }
+                }
+                break;
+        #endif /* NO_RSA */
+        #ifdef HAVE_NTRU
+            case NTRUk:
+                {
+                    if (dCert->pubKeySize > sizeof(ssl->peerNtruKey)) {
+                        ret = PEER_KEY_ERROR;
+                    }
+                    else {
+                        XMEMCPY(ssl->peerNtruKey, dCert->publicKey,
+                                                             dCert->pubKeySize);
+                        ssl->peerNtruKeyLen = (word16)dCert->pubKeySize;
+                        ssl->peerNtruKeyPresent = 1;
+                    }
+                }
+                break;
+        #endif /* HAVE_NTRU */
+        #ifdef HAVE_ECC
+            case ECDSAk:
+                {
+                    if (ssl->peerEccDsaKey == NULL) {
+                        /* alloc/init on demand */
+                        ssl->peerEccDsaKey = (ecc_key*)XMALLOC(sizeof(ecc_key),
+                                              ssl->ctx->heap, DYNAMIC_TYPE_ECC);
+                        if (ssl->peerEccDsaKey == NULL) {
+                            WOLFSSL_MSG("PeerEccDsaKey Memory error");
+                            return MEMORY_E;
+                        }
+                        wc_ecc_init(ssl->peerEccDsaKey);
+                    } else if (ssl->peerEccDsaKeyPresent) {
+                        /* don't leak on reuse */
+                        wc_ecc_free(ssl->peerEccDsaKey);
+                        ssl->peerEccDsaKeyPresent = 0;
+                        wc_ecc_init(ssl->peerEccDsaKey);
+                    }
+                    if (wc_ecc_import_x963(dCert->publicKey, dCert->pubKeySize,
+                                        ssl->peerEccDsaKey) != 0) {
+                        ret = PEER_KEY_ERROR;
+                    }
+                    else {
+                        ssl->peerEccDsaKeyPresent = 1;
+                        #ifdef HAVE_PK_CALLBACKS
+                            #ifdef HAVE_ECC
+                                ssl->buffers.peerEccDsaKey.buffer =
+                                       (byte*)XMALLOC(dCert->pubKeySize,
+                                               ssl->heap, DYNAMIC_TYPE_ECC);
+                                if (ssl->buffers.peerEccDsaKey.buffer == NULL)
+                                    ret = MEMORY_ERROR;
+                                else {
+                                    XMEMCPY(ssl->buffers.peerEccDsaKey.buffer,
+                                           dCert->publicKey, dCert->pubKeySize);
+                                    ssl->buffers.peerEccDsaKey.length =
+                                            dCert->pubKeySize;
+                                }
+                            #endif /* HAVE_ECC */
+                        #endif /*HAVE_PK_CALLBACKS */
+                    }
+                }
+                break;
+        #endif /* HAVE_ECC */
+            default:
+                break;
+        }
+
+        FreeDecodedCert(dCert);
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(dCert, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+
+    store = (WOLFSSL_X509_STORE_CTX*)XMALLOC(sizeof(WOLFSSL_X509_STORE_CTX),
+                                                 NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (store == NULL) {
+        XFREE(domain, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        return MEMORY_E;
+    }
+#endif
+
+    if (anyError != 0 && ret == 0)
+        ret = anyError;
+
+    if (ret != 0) {
+        if (!ssl->options.verifyNone) {
+            int why = bad_certificate;
+
+            if (ret == ASN_AFTER_DATE_E || ret == ASN_BEFORE_DATE_E)
+                why = certificate_expired;
+            if (ssl->verifyCallback) {
+                int ok;
+
+                store->error = ret;
+                store->error_depth = totalCerts;
+                store->discardSessionCerts = 0;
+                store->domain = domain;
+                store->userCtx = ssl->verifyCbCtx;
+#ifdef KEEP_PEER_CERT
+                store->current_cert = &ssl->peerCert;
+#else
+                store->current_cert = NULL;
+#endif
+#ifdef FORTRESS
+                store->ex_data = ssl;
+#endif
+                ok = ssl->verifyCallback(0, store);
+                if (ok) {
+                    WOLFSSL_MSG("Verify callback overriding error!");
+                    ret = 0;
+                }
+                #ifdef SESSION_CERTS
+                if (store->discardSessionCerts) {
+                    WOLFSSL_MSG("Verify callback requested discard sess certs");
+                    ssl->session.chain.count = 0;
+                }
+                #endif
+            }
+            if (ret != 0) {
+                SendAlert(ssl, alert_fatal, why);   /* try to send */
+                ssl->options.isClosed = 1;
+            }
+        }
+        ssl->error = ret;
+    }
+#ifdef WOLFSSL_ALWAYS_VERIFY_CB
+    else {
+        if (ssl->verifyCallback) {
+            int ok;
+
+            store->error = ret;
+            store->error_depth = totalCerts;
+            store->discardSessionCerts = 0;
+            store->domain = domain;
+            store->userCtx = ssl->verifyCbCtx;
+#ifdef KEEP_PEER_CERT
+            store->current_cert = &ssl->peerCert;
+#endif
+            store->ex_data = ssl;
+
+            ok = ssl->verifyCallback(1, store);
+            if (!ok) {
+                WOLFSSL_MSG("Verify callback overriding valid certificate!");
+                ret = -1;
+                SendAlert(ssl, alert_fatal, bad_certificate);
+                ssl->options.isClosed = 1;
+            }
+            #ifdef SESSION_CERTS
+            if (store->discardSessionCerts) {
+                WOLFSSL_MSG("Verify callback requested discard sess certs");
+                ssl->session.chain.count = 0;
+            }
+            #endif
+        }
+    }
+#endif
+
+    if (ssl->options.verifyNone &&
+                              (ret == CRL_MISSING || ret == CRL_CERT_REVOKED)) {
+        WOLFSSL_MSG("Ignoring CRL problem based on verify setting");
+        ret = ssl->error = 0;
+    }
+
+    if (ret == 0 && ssl->options.side == WOLFSSL_CLIENT_END)
+        ssl->options.serverState = SERVER_CERT_COMPLETE;
+
+    if (ssl->keys.encryptionOn) {
+        *inOutIdx += ssl->keys.padSz;
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(store,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(domain, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+#endif /* !NO_CERTS */
+
+
+static int DoHelloRequest(WOLFSSL* ssl, const byte* input, word32* inOutIdx,
+                                                    word32 size, word32 totalSz)
+{
+    (void)input;
+
+    if (size) /* must be 0 */
+        return BUFFER_ERROR;
+
+    if (ssl->keys.encryptionOn) {
+        /* access beyond input + size should be checked against totalSz */
+        if (*inOutIdx + ssl->keys.padSz > totalSz)
+            return BUFFER_E;
+
+        *inOutIdx += ssl->keys.padSz;
+    }
+
+    if (ssl->options.side == WOLFSSL_SERVER_END) {
+        SendAlert(ssl, alert_fatal, unexpected_message); /* try */
+        return FATAL_ERROR;
+    }
+#ifdef HAVE_SECURE_RENEGOTIATION
+    else if (ssl->secure_renegotiation && ssl->secure_renegotiation->enabled) {
+        ssl->secure_renegotiation->startScr = 1;
+        return 0;
+    }
+#endif
+    else {
+        return SendAlert(ssl, alert_warning, no_renegotiation);
+    }
+}
+
+
+int DoFinished(WOLFSSL* ssl, const byte* input, word32* inOutIdx, word32 size,
+                                                      word32 totalSz, int sniff)
+{
+    word32 finishedSz = (ssl->options.tls ? TLS_FINISHED_SZ : FINISHED_SZ);
+
+    if (finishedSz != size)
+        return BUFFER_ERROR;
+
+    /* check against totalSz */
+    if (*inOutIdx + size + ssl->keys.padSz > totalSz)
+        return BUFFER_E;
+
+    #ifdef WOLFSSL_CALLBACKS
+        if (ssl->hsInfoOn) AddPacketName("Finished", &ssl->handShakeInfo);
+        if (ssl->toInfoOn) AddLateName("Finished", &ssl->timeoutInfo);
+    #endif
+
+    if (sniff == NO_SNIFF) {
+        if (XMEMCMP(input + *inOutIdx, &ssl->hsHashes->verifyHashes,size) != 0){
+            WOLFSSL_MSG("Verify finished error on hashes");
+            return VERIFY_FINISHED_ERROR;
+        }
+    }
+
+#ifdef HAVE_SECURE_RENEGOTIATION
+    if (ssl->secure_renegotiation) {
+        /* save peer's state */
+        if (ssl->options.side == WOLFSSL_CLIENT_END)
+            XMEMCPY(ssl->secure_renegotiation->server_verify_data,
+                    input + *inOutIdx, TLS_FINISHED_SZ);
+        else
+            XMEMCPY(ssl->secure_renegotiation->client_verify_data,
+                    input + *inOutIdx, TLS_FINISHED_SZ);
+    }
+#endif
+
+    /* force input exhaustion at ProcessReply consuming padSz */
+    *inOutIdx += size + ssl->keys.padSz;
+
+    if (ssl->options.side == WOLFSSL_CLIENT_END) {
+        ssl->options.serverState = SERVER_FINISHED_COMPLETE;
+        if (!ssl->options.resuming) {
+            ssl->options.handShakeState = HANDSHAKE_DONE;
+            ssl->options.handShakeDone  = 1;
+
+#ifdef WOLFSSL_DTLS
+            if (ssl->options.dtls) {
+                /* Other side has received our Finished, go to next epoch */
+                ssl->keys.dtls_epoch++;
+                ssl->keys.dtls_sequence_number = 1;
+            }
+#endif
+        }
+    }
+    else {
+        ssl->options.clientState = CLIENT_FINISHED_COMPLETE;
+        if (ssl->options.resuming) {
+            ssl->options.handShakeState = HANDSHAKE_DONE;
+            ssl->options.handShakeDone  = 1;
+
+#ifdef WOLFSSL_DTLS
+            if (ssl->options.dtls) {
+                /* Other side has received our Finished, go to next epoch */
+                ssl->keys.dtls_epoch++;
+                ssl->keys.dtls_sequence_number = 1;
+            }
+#endif
+        }
+    }
+
+    return 0;
+}
+
+
+/* Make sure no duplicates, no fast forward, or other problems; 0 on success */
+static int SanityCheckMsgReceived(WOLFSSL* ssl, byte type)
+{
+    /* verify not a duplicate, mark received, check state */
+    switch (type) {
+
+#ifndef NO_WOLFSSL_CLIENT
+        case hello_request:
+            if (ssl->msgsReceived.got_hello_request) {
+                WOLFSSL_MSG("Duplicate HelloRequest received");
+                return DUPLICATE_MSG_E;
+            }
+            ssl->msgsReceived.got_hello_request = 1;
+
+            break;
+#endif
+
+#ifndef NO_WOLFSSL_SERVER
+        case client_hello:
+            if (ssl->msgsReceived.got_client_hello) {
+                WOLFSSL_MSG("Duplicate ClientHello received");
+                return DUPLICATE_MSG_E;
+            }
+            ssl->msgsReceived.got_client_hello = 1;
+
+            break;
+#endif
+
+#ifndef NO_WOLFSSL_CLIENT
+        case server_hello:
+            if (ssl->msgsReceived.got_server_hello) {
+                WOLFSSL_MSG("Duplicate ServerHello received");
+                return DUPLICATE_MSG_E;
+            }
+            ssl->msgsReceived.got_server_hello = 1;
+
+            break;
+#endif
+
+#ifndef NO_WOLFSSL_CLIENT
+        case hello_verify_request:
+            if (ssl->msgsReceived.got_hello_verify_request) {
+                WOLFSSL_MSG("Duplicate HelloVerifyRequest received");
+                return DUPLICATE_MSG_E;
+            }
+            ssl->msgsReceived.got_hello_verify_request = 1;
+
+            break;
+#endif
+
+#ifndef NO_WOLFSSL_CLIENT
+        case session_ticket:
+            if (ssl->msgsReceived.got_session_ticket) {
+                WOLFSSL_MSG("Duplicate SessionTicket received");
+                return DUPLICATE_MSG_E;
+            }
+            ssl->msgsReceived.got_session_ticket = 1;
+
+            break;
+#endif
+
+        case certificate:
+            if (ssl->msgsReceived.got_certificate) {
+                WOLFSSL_MSG("Duplicate Certificate received");
+                return DUPLICATE_MSG_E;
+            }
+            ssl->msgsReceived.got_certificate = 1;
+
+#ifndef NO_WOLFSSL_CLIENT
+            if (ssl->options.side == WOLFSSL_CLIENT_END) {
+                if ( ssl->msgsReceived.got_server_hello == 0) {
+                    WOLFSSL_MSG("No ServerHello before Cert");
+                    return OUT_OF_ORDER_E;
+                }
+            }
+#endif
+#ifndef NO_WOLFSSL_SERVER
+            if (ssl->options.side == WOLFSSL_SERVER_END) {
+                if ( ssl->msgsReceived.got_client_hello == 0) {
+                    WOLFSSL_MSG("No ClientHello before Cert");
+                    return OUT_OF_ORDER_E;
+                }
+            }
+#endif
+            break;
+
+#ifndef NO_WOLFSSL_CLIENT
+        case server_key_exchange:
+            if (ssl->msgsReceived.got_server_key_exchange) {
+                WOLFSSL_MSG("Duplicate ServerKeyExchange received");
+                return DUPLICATE_MSG_E;
+            }
+            ssl->msgsReceived.got_server_key_exchange = 1;
+
+            if ( ssl->msgsReceived.got_server_hello == 0) {
+                WOLFSSL_MSG("No ServerHello before Cert");
+                return OUT_OF_ORDER_E;
+            }
+
+            break;
+#endif
+
+#ifndef NO_WOLFSSL_CLIENT
+        case certificate_request:
+            if (ssl->msgsReceived.got_certificate_request) {
+                WOLFSSL_MSG("Duplicate CertificateRequest received");
+                return DUPLICATE_MSG_E;
+            }
+            ssl->msgsReceived.got_certificate_request = 1;
+
+            break;
+#endif
+
+#ifndef NO_WOLFSSL_CLIENT
+        case server_hello_done:
+            if (ssl->msgsReceived.got_server_hello_done) {
+                WOLFSSL_MSG("Duplicate ServerHelloDone received");
+                return DUPLICATE_MSG_E;
+            }
+            ssl->msgsReceived.got_server_hello_done = 1;
+
+            if (ssl->msgsReceived.got_certificate == 0) {
+                if (ssl->specs.kea == psk_kea ||
+                    ssl->specs.kea == dhe_psk_kea ||
+                    ssl->options.usingAnon_cipher) {
+                    WOLFSSL_MSG("No Cert required");
+                } else {
+                    WOLFSSL_MSG("No Certificate before ServerHelloDone");
+                    return OUT_OF_ORDER_E;
+                }
+            }
+            if (ssl->msgsReceived.got_server_key_exchange == 0) {
+                if (ssl->specs.static_ecdh == 1 ||
+                    ssl->specs.kea == rsa_kea ||
+                    ssl->specs.kea == ntru_kea) {
+                    WOLFSSL_MSG("No KeyExchange required");
+                } else {
+                    WOLFSSL_MSG("No ServerKeyExchange before ServerDone");
+                    return OUT_OF_ORDER_E;
+                }
+            }
+            break;
+#endif
+
+#ifndef NO_WOLFSSL_SERVER
+        case certificate_verify:
+            if (ssl->msgsReceived.got_certificate_verify) {
+                WOLFSSL_MSG("Duplicate CertificateVerify received");
+                return DUPLICATE_MSG_E;
+            }
+            ssl->msgsReceived.got_certificate_verify = 1;
+
+            if ( ssl->msgsReceived.got_certificate == 0) {
+                WOLFSSL_MSG("No Cert before CertVerify");
+                return OUT_OF_ORDER_E;
+            }
+            break;
+#endif
+
+#ifndef NO_WOLFSSL_SERVER
+        case client_key_exchange:
+            if (ssl->msgsReceived.got_client_key_exchange) {
+                WOLFSSL_MSG("Duplicate ClientKeyExchange received");
+                return DUPLICATE_MSG_E;
+            }
+            ssl->msgsReceived.got_client_key_exchange = 1;
+
+            if (ssl->msgsReceived.got_client_hello == 0) {
+                WOLFSSL_MSG("No ClientHello before ClientKeyExchange");
+                return OUT_OF_ORDER_E;
+            }
+            break;
+#endif
+
+        case finished:
+            if (ssl->msgsReceived.got_finished) {
+                WOLFSSL_MSG("Duplicate Finished received");
+                return DUPLICATE_MSG_E;
+            }
+            ssl->msgsReceived.got_finished = 1;
+
+            if (ssl->msgsReceived.got_change_cipher == 0) {
+                WOLFSSL_MSG("Finished received before ChangeCipher");
+                return NO_CHANGE_CIPHER_E;
+            }
+
+            break;
+
+        case change_cipher_hs:
+            if (ssl->msgsReceived.got_change_cipher) {
+                WOLFSSL_MSG("Duplicate ChangeCipher received");
+                return DUPLICATE_MSG_E;
+            }
+            ssl->msgsReceived.got_change_cipher = 1;
+
+#ifndef NO_WOLFSSL_CLIENT
+            if (ssl->options.side == WOLFSSL_CLIENT_END) {
+                if (!ssl->options.resuming &&
+                                 ssl->msgsReceived.got_server_hello_done == 0) {
+                    WOLFSSL_MSG("No ServerHelloDone before ChangeCipher");
+                    return OUT_OF_ORDER_E;
+                }
+            }
+#endif
+#ifndef NO_WOLFSSL_SERVER
+            if (ssl->options.side == WOLFSSL_SERVER_END) {
+                if (!ssl->options.resuming &&
+                               ssl->msgsReceived.got_client_key_exchange == 0) {
+                    WOLFSSL_MSG("No ClientKeyExchange before ChangeCipher");
+                    return OUT_OF_ORDER_E;
+                }
+            }
+#endif
+
+            break;
+
+        default:
+            WOLFSSL_MSG("Unknown message type");
+            return SANITY_MSG_E;
+    }
+
+    return 0;
+}
+
+
+static int DoHandShakeMsgType(WOLFSSL* ssl, byte* input, word32* inOutIdx,
+                          byte type, word32 size, word32 totalSz)
+{
+    int ret = 0;
+    (void)totalSz;
+
+    WOLFSSL_ENTER("DoHandShakeMsgType");
+
+    /* make sure can read the message */
+    if (*inOutIdx + size > totalSz)
+        return INCOMPLETE_DATA;
+
+    /* sanity check msg received */
+    if ( (ret = SanityCheckMsgReceived(ssl, type)) != 0) {
+        WOLFSSL_MSG("Sanity Check on handshake message type received failed");
+        return ret;
+    }
+
+#ifdef WOLFSSL_CALLBACKS
+    /* add name later, add on record and handshake header part back on */
+    if (ssl->toInfoOn) {
+        int add = RECORD_HEADER_SZ + HANDSHAKE_HEADER_SZ;
+        AddPacketInfo(0, &ssl->timeoutInfo, input + *inOutIdx - add,
+                      size + add, ssl->heap);
+        AddLateRecordHeader(&ssl->curRL, &ssl->timeoutInfo);
+    }
+#endif
+
+    if (ssl->options.handShakeState == HANDSHAKE_DONE && type != hello_request){
+        WOLFSSL_MSG("HandShake message after handshake complete");
+        SendAlert(ssl, alert_fatal, unexpected_message);
+        return OUT_OF_ORDER_E;
+    }
+
+    if (ssl->options.side == WOLFSSL_CLIENT_END && ssl->options.dtls == 0 &&
+               ssl->options.serverState == NULL_STATE && type != server_hello) {
+        WOLFSSL_MSG("First server message not server hello");
+        SendAlert(ssl, alert_fatal, unexpected_message);
+        return OUT_OF_ORDER_E;
+    }
+
+    if (ssl->options.side == WOLFSSL_CLIENT_END && ssl->options.dtls &&
+            type == server_hello_done &&
+            ssl->options.serverState < SERVER_HELLO_COMPLETE) {
+        WOLFSSL_MSG("Server hello done received before server hello in DTLS");
+        SendAlert(ssl, alert_fatal, unexpected_message);
+        return OUT_OF_ORDER_E;
+    }
+
+    if (ssl->options.side == WOLFSSL_SERVER_END &&
+               ssl->options.clientState == NULL_STATE && type != client_hello) {
+        WOLFSSL_MSG("First client message not client hello");
+        SendAlert(ssl, alert_fatal, unexpected_message);
+        return OUT_OF_ORDER_E;
+    }
+
+    /* above checks handshake state */
+    /* hello_request not hashed */
+    if (type != hello_request) {
+        ret = HashInput(ssl, input + *inOutIdx, size);
+        if (ret != 0) return ret;
+    }
+
+    switch (type) {
+
+    case hello_request:
+        WOLFSSL_MSG("processing hello request");
+        ret = DoHelloRequest(ssl, input, inOutIdx, size, totalSz);
+        break;
+
+#ifndef NO_WOLFSSL_CLIENT
+    case hello_verify_request:
+        WOLFSSL_MSG("processing hello verify request");
+        ret = DoHelloVerifyRequest(ssl, input,inOutIdx, size);
+        break;
+
+    case server_hello:
+        WOLFSSL_MSG("processing server hello");
+        ret = DoServerHello(ssl, input, inOutIdx, size);
+        break;
+
+#ifndef NO_CERTS
+    case certificate_request:
+        WOLFSSL_MSG("processing certificate request");
+        ret = DoCertificateRequest(ssl, input, inOutIdx, size);
+        break;
+#endif
+
+    case server_key_exchange:
+        WOLFSSL_MSG("processing server key exchange");
+        ret = DoServerKeyExchange(ssl, input, inOutIdx, size);
+        break;
+
+#ifdef HAVE_SESSION_TICKET
+    case session_ticket:
+        WOLFSSL_MSG("processing session ticket");
+        ret = DoSessionTicket(ssl, input, inOutIdx, size);
+        break;
+#endif /* HAVE_SESSION_TICKET */
+#endif
+
+#ifndef NO_CERTS
+    case certificate:
+        WOLFSSL_MSG("processing certificate");
+        ret =  DoCertificate(ssl, input, inOutIdx, size);
+        break;
+#endif
+
+    case server_hello_done:
+        WOLFSSL_MSG("processing server hello done");
+        #ifdef WOLFSSL_CALLBACKS
+            if (ssl->hsInfoOn)
+                AddPacketName("ServerHelloDone", &ssl->handShakeInfo);
+            if (ssl->toInfoOn)
+                AddLateName("ServerHelloDone", &ssl->timeoutInfo);
+        #endif
+        ssl->options.serverState = SERVER_HELLODONE_COMPLETE;
+        if (ssl->keys.encryptionOn) {
+            *inOutIdx += ssl->keys.padSz;
+        }
+        if (ssl->options.resuming) {
+            WOLFSSL_MSG("Not resuming as thought");
+            ssl->options.resuming = 0;
+        }
+        break;
+
+    case finished:
+        WOLFSSL_MSG("processing finished");
+        ret = DoFinished(ssl, input, inOutIdx, size, totalSz, NO_SNIFF);
+        break;
+
+#ifndef NO_WOLFSSL_SERVER
+    case client_hello:
+        WOLFSSL_MSG("processing client hello");
+        ret = DoClientHello(ssl, input, inOutIdx, size);
+        break;
+
+    case client_key_exchange:
+        WOLFSSL_MSG("processing client key exchange");
+        ret = DoClientKeyExchange(ssl, input, inOutIdx, size);
+        break;
+
+#if !defined(NO_RSA) || defined(HAVE_ECC)
+    case certificate_verify:
+        WOLFSSL_MSG("processing certificate verify");
+        ret = DoCertificateVerify(ssl, input, inOutIdx, size);
+        break;
+#endif /* !NO_RSA || HAVE_ECC */
+
+#endif /* !NO_WOLFSSL_SERVER */
+
+    default:
+        WOLFSSL_MSG("Unknown handshake message type");
+        ret = UNKNOWN_HANDSHAKE_TYPE;
+        break;
+    }
+
+    WOLFSSL_LEAVE("DoHandShakeMsgType()", ret);
+    return ret;
+}
+
+
+static int DoHandShakeMsg(WOLFSSL* ssl, byte* input, word32* inOutIdx,
+                          word32 totalSz)
+{
+    byte   type;
+    word32 size;
+    int    ret = 0;
+
+    WOLFSSL_ENTER("DoHandShakeMsg()");
+
+    if (GetHandShakeHeader(ssl, input, inOutIdx, &type, &size, totalSz) != 0)
+        return PARSE_ERROR;
+
+    ret = DoHandShakeMsgType(ssl, input, inOutIdx, type, size, totalSz);
+
+    WOLFSSL_LEAVE("DoHandShakeMsg()", ret);
+    return ret;
+}
+
+
+#ifdef WOLFSSL_DTLS
+
+static INLINE int DtlsCheckWindow(DtlsState* state)
+{
+    word32 cur;
+    word32 next;
+    DtlsSeq window;
+
+    if (state->curEpoch == state->nextEpoch) {
+        next = state->nextSeq;
+        window = state->window;
+    }
+    else if (state->curEpoch < state->nextEpoch) {
+        next = state->prevSeq;
+        window = state->prevWindow;
+    }
+    else {
+        return 0;
+    }
+
+    cur = state->curSeq;
+
+    if ((next > DTLS_SEQ_BITS) && (cur < next - DTLS_SEQ_BITS)) {
+        return 0;
+    }
+    else if ((cur < next) && (window & ((DtlsSeq)1 << (next - cur - 1)))) {
+        return 0;
+    }
+
+    return 1;
+}
+
+
+static INLINE int DtlsUpdateWindow(DtlsState* state)
+{
+    word32 cur;
+    word32* next;
+    DtlsSeq* window;
+
+    if (state->curEpoch == state->nextEpoch) {
+        next = &state->nextSeq;
+        window = &state->window;
+    }
+    else {
+        next = &state->prevSeq;
+        window = &state->prevWindow;
+    }
+
+    cur = state->curSeq;
+
+    if (cur < *next) {
+        *window |= ((DtlsSeq)1 << (*next - cur - 1));
+    }
+    else {
+        *window <<= (1 + cur - *next);
+        *window |= 1;
+        *next = cur + 1;
+    }
+
+    return 1;
+}
+
+
+static int DtlsMsgDrain(WOLFSSL* ssl)
+{
+    DtlsMsg* item = ssl->dtls_msg_list;
+    int ret = 0;
+
+    /* While there is an item in the store list, and it is the expected
+     * message, and it is complete, and there hasn't been an error in the
+     * last messge... */
+    while (item != NULL &&
+            ssl->keys.dtls_expected_peer_handshake_number == item->seq &&
+            item->fragSz == item->sz &&
+            ret == 0) {
+        word32 idx = 0;
+        ssl->keys.dtls_expected_peer_handshake_number++;
+        ret = DoHandShakeMsgType(ssl, item->msg,
+                                 &idx, item->type, item->sz, item->sz);
+        ssl->dtls_msg_list = item->next;
+        DtlsMsgDelete(item, ssl->heap);
+        item = ssl->dtls_msg_list;
+    }
+
+    return ret;
+}
+
+
+static int DoDtlsHandShakeMsg(WOLFSSL* ssl, byte* input, word32* inOutIdx,
+                          word32 totalSz)
+{
+    byte type;
+    word32 size;
+    word32 fragOffset, fragSz;
+    int ret = 0;
+
+    WOLFSSL_ENTER("DoDtlsHandShakeMsg()");
+    if (GetDtlsHandShakeHeader(ssl, input, inOutIdx, &type,
+                               &size, &fragOffset, &fragSz, totalSz) != 0)
+        return PARSE_ERROR;
+
+    if (*inOutIdx + fragSz > totalSz)
+        return INCOMPLETE_DATA;
+
+    /* Check the handshake sequence number first. If out of order,
+     * add the current message to the list. If the message is in order,
+     * but it is a fragment, add the current message to the list, then
+     * check the head of the list to see if it is complete, if so, pop
+     * it out as the current message. If the message is complete and in
+     * order, process it. Check the head of the list to see if it is in
+     * order, if so, process it. (Repeat until list exhausted.) If the
+     * head is out of order, return for more processing.
+     */
+    if (ssl->keys.dtls_peer_handshake_number >
+                                ssl->keys.dtls_expected_peer_handshake_number) {
+        /* Current message is out of order. It will get stored in the list.
+         * Storing also takes care of defragmentation. */
+        ssl->dtls_msg_list = DtlsMsgStore(ssl->dtls_msg_list,
+                        ssl->keys.dtls_peer_handshake_number, input + *inOutIdx,
+                        size, type, fragOffset, fragSz, ssl->heap);
+        *inOutIdx += fragSz;
+        ret = 0;
+    }
+    else if (ssl->keys.dtls_peer_handshake_number <
+                                ssl->keys.dtls_expected_peer_handshake_number) {
+        /* Already saw this message and processed it. It can be ignored. */
+        *inOutIdx += fragSz;
+        ret = 0;
+    }
+    else if (fragSz < size) {
+        /* Since this branch is in order, but fragmented, dtls_msg_list will be
+         * pointing to the message with this fragment in it. Check it to see
+         * if it is completed. */
+        ssl->dtls_msg_list = DtlsMsgStore(ssl->dtls_msg_list,
+                        ssl->keys.dtls_peer_handshake_number, input + *inOutIdx,
+                        size, type, fragOffset, fragSz, ssl->heap);
+        *inOutIdx += fragSz;
+        ret = 0;
+        if (ssl->dtls_msg_list != NULL &&
+            ssl->dtls_msg_list->fragSz >= ssl->dtls_msg_list->sz)
+            ret = DtlsMsgDrain(ssl);
+    }
+    else {
+        /* This branch is in order next, and a complete message. */
+        ssl->keys.dtls_expected_peer_handshake_number++;
+        ret = DoHandShakeMsgType(ssl, input, inOutIdx, type, size, totalSz);
+        if (ret == 0 && ssl->dtls_msg_list != NULL)
+            ret = DtlsMsgDrain(ssl);
+    }
+
+    WOLFSSL_LEAVE("DoDtlsHandShakeMsg()", ret);
+    return ret;
+}
+#endif
+
+
+#if !defined(NO_OLD_TLS) || defined(HAVE_CHACHA) || defined(HAVE_AESCCM) \
+    || defined(HAVE_AESGCM)
+static INLINE word32 GetSEQIncrement(WOLFSSL* ssl, int verify)
+{
+#ifdef WOLFSSL_DTLS
+    if (ssl->options.dtls) {
+        if (verify)
+            return ssl->keys.dtls_state.curSeq; /* explicit from peer */
+        else
+            return ssl->keys.dtls_sequence_number - 1; /* already incremented */
+    }
+#endif
+    if (verify)
+        return ssl->keys.peer_sequence_number++;
+    else
+        return ssl->keys.sequence_number++;
+}
+#endif
+
+
+#ifdef HAVE_AEAD
+static INLINE void AeadIncrementExpIV(WOLFSSL* ssl)
+{
+    int i;
+    for (i = AEAD_EXP_IV_SZ-1; i >= 0; i--) {
+        if (++ssl->keys.aead_exp_IV[i]) return;
+    }
+}
+
+
+#if defined(HAVE_POLY1305) && defined(HAVE_CHACHA)
+/*more recent rfc's concatonate input for poly1305 differently*/
+static int Poly1305Tag(WOLFSSL* ssl, byte* additional, const byte* out,
+                       byte* cipher, word16 sz, byte* tag)
+{
+    int ret       = 0;
+    int paddingSz = 0;
+    int msglen    = (sz - ssl->specs.aead_mac_size);
+    word32 keySz  = 32;
+    int blockSz   = 16;
+    byte padding[16];
+
+    if (msglen < 0)
+        return INPUT_CASE_ERROR;
+
+    XMEMSET(padding, 0, sizeof(padding));
+
+    if ((ret = wc_Poly1305SetKey(ssl->auth.poly1305, cipher, keySz)) != 0)
+        return ret;
+
+    /* additional input to poly1305 */
+    if ((ret = wc_Poly1305Update(ssl->auth.poly1305, additional, blockSz)) != 0)
+        return ret;
+
+    /* cipher input */
+    if ((ret = wc_Poly1305Update(ssl->auth.poly1305, out, msglen)) != 0)
+        return ret;
+
+    /* handle padding for cipher input to make it 16 bytes long */
+    if (msglen % 16 != 0) {
+          paddingSz = (16 - (sz - ssl->specs.aead_mac_size) % 16);
+          if (paddingSz < 0)
+              return INPUT_CASE_ERROR;
+
+          if ((ret = wc_Poly1305Update(ssl->auth.poly1305, padding, paddingSz))
+                 != 0)
+              return ret;
+    }
+
+    /* add size of AD and size of cipher to poly input */
+    XMEMSET(padding, 0, sizeof(padding));
+    padding[0] = blockSz;
+
+    /* 32 bit size of cipher to 64 bit endian */
+    padding[8]  =  msglen       & 0xff;
+    padding[9]  = (msglen >> 8) & 0xff;
+    padding[10] = (msglen >>16) & 0xff;
+    padding[11] = (msglen >>24) & 0xff;
+    if ((ret = wc_Poly1305Update(ssl->auth.poly1305, padding, sizeof(padding)))
+                != 0)
+        return ret;
+
+    /* generate tag */
+    if ((ret = wc_Poly1305Final(ssl->auth.poly1305, tag)) != 0)
+        return ret;
+
+    return ret;
+}
+
+
+/* Used for the older version of creating AEAD tags with Poly1305 */
+static int Poly1305TagOld(WOLFSSL* ssl, byte* additional, const byte* out,
+                       byte* cipher, word16 sz, byte* tag)
+{
+    int ret       = 0;
+    int msglen    = (sz - ssl->specs.aead_mac_size);
+    word32 keySz  = 32;
+    byte padding[8]; /* used to temporarly store lengths */
+
+#ifdef CHACHA_AEAD_TEST
+      printf("Using old version of poly1305 input.\n");
+#endif
+
+    if (msglen < 0)
+        return INPUT_CASE_ERROR;
+
+    if ((ret = wc_Poly1305SetKey(ssl->auth.poly1305, cipher, keySz)) != 0)
+        return ret;
+
+    /* add TLS compressed length and additional input to poly1305 */
+    additional[AEAD_AUTH_DATA_SZ - 2] = (msglen >> 8) & 0xff;
+    additional[AEAD_AUTH_DATA_SZ - 1] =  msglen       & 0xff;
+    if ((ret = wc_Poly1305Update(ssl->auth.poly1305, additional,
+                   AEAD_AUTH_DATA_SZ)) != 0)
+        return ret;
+
+    /* length of additional input plus padding */
+    XMEMSET(padding, 0, sizeof(padding));
+    padding[0] = AEAD_AUTH_DATA_SZ;
+    if ((ret = wc_Poly1305Update(ssl->auth.poly1305, padding,
+                    sizeof(padding))) != 0)
+        return ret;
+
+
+    /* add cipher info and then its length */
+    XMEMSET(padding, 0, sizeof(padding));
+    if ((ret = wc_Poly1305Update(ssl->auth.poly1305, out, msglen)) != 0)
+        return ret;
+
+    /* 32 bit size of cipher to 64 bit endian */
+    padding[0] =  msglen        & 0xff;
+    padding[1] = (msglen >>  8) & 0xff;
+    padding[2] = (msglen >> 16) & 0xff;
+    padding[3] = (msglen >> 24) & 0xff;
+    if ((ret = wc_Poly1305Update(ssl->auth.poly1305, padding, sizeof(padding)))
+        != 0)
+        return ret;
+
+    /* generate tag */
+    if ((ret = wc_Poly1305Final(ssl->auth.poly1305, tag)) != 0)
+        return ret;
+
+    return ret;
+}
+
+
+static int  ChachaAEADEncrypt(WOLFSSL* ssl, byte* out, const byte* input,
+                              word16 sz)
+{
+    const byte* additionalSrc = input - RECORD_HEADER_SZ;
+    int ret = 0;
+    byte tag[POLY1305_AUTH_SZ];
+    byte additional[CHACHA20_BLOCK_SIZE];
+    byte nonce[AEAD_NONCE_SZ];
+    byte cipher[CHACHA20_256_KEY_SIZE]; /* generated key for poly1305 */
+    #ifdef CHACHA_AEAD_TEST
+        int i;
+    #endif
+
+    XMEMSET(tag, 0, sizeof(tag));
+    XMEMSET(nonce, 0, AEAD_NONCE_SZ);
+    XMEMSET(cipher, 0, sizeof(cipher));
+    XMEMSET(additional, 0, CHACHA20_BLOCK_SIZE);
+
+    /* get nonce */
+    c32toa(ssl->keys.sequence_number, nonce + AEAD_IMP_IV_SZ
+           + AEAD_SEQ_OFFSET);
+
+    /* opaque SEQ number stored for AD */
+    c32toa(GetSEQIncrement(ssl, 0), additional + AEAD_SEQ_OFFSET);
+
+    /* Store the type, version. Unfortunately, they are in
+     * the input buffer ahead of the plaintext. */
+    #ifdef WOLFSSL_DTLS
+        if (ssl->options.dtls) {
+            c16toa(ssl->keys.dtls_epoch, additional);
+            additionalSrc -= DTLS_HANDSHAKE_EXTRA;
+        }
+    #endif
+
+    XMEMCPY(additional + AEAD_TYPE_OFFSET, additionalSrc, 3);
+
+    #ifdef CHACHA_AEAD_TEST
+        printf("Encrypt Additional : ");
+        for (i = 0; i < CHACHA20_BLOCK_SIZE; i++) {
+            printf("%02x", additional[i]);
+        }
+        printf("\n\n");
+        printf("input before encryption :\n");
+        for (i = 0; i < sz; i++) {
+            printf("%02x", input[i]);
+            if ((i + 1) % 16 == 0)
+                printf("\n");
+        }
+        printf("\n");
+    #endif
+
+    /* set the nonce for chacha and get poly1305 key */
+    if ((ret = wc_Chacha_SetIV(ssl->encrypt.chacha, nonce, 0)) != 0)
+        return ret;
+
+        if ((ret = wc_Chacha_Process(ssl->encrypt.chacha, cipher,
+                    cipher, sizeof(cipher))) != 0)
+        return ret;
+
+    /* encrypt the plain text */
+    if ((ret = wc_Chacha_Process(ssl->encrypt.chacha, out, input,
+                   sz - ssl->specs.aead_mac_size)) != 0)
+        return ret;
+
+    /* get the tag : future use of hmac could go here*/
+    if (ssl->options.oldPoly == 1) {
+        if ((ret = Poly1305TagOld(ssl, additional, (const byte* )out,
+                    cipher, sz, tag)) != 0)
+            return ret;
+    }
+    else {
+        if ((ret = Poly1305Tag(ssl, additional, (const byte* )out,
+                    cipher, sz, tag)) != 0)
+            return ret;
+    }
+
+    /* append tag to ciphertext */
+    XMEMCPY(out + sz - ssl->specs.aead_mac_size, tag, sizeof(tag));
+
+    AeadIncrementExpIV(ssl);
+    ForceZero(nonce, AEAD_NONCE_SZ);
+
+    #ifdef CHACHA_AEAD_TEST
+       printf("mac tag :\n");
+        for (i = 0; i < 16; i++) {
+           printf("%02x", tag[i]);
+           if ((i + 1) % 16 == 0)
+               printf("\n");
+        }
+       printf("\n\noutput after encrypt :\n");
+        for (i = 0; i < sz; i++) {
+           printf("%02x", out[i]);
+           if ((i + 1) % 16 == 0)
+               printf("\n");
+        }
+        printf("\n");
+    #endif
+
+    return ret;
+}
+
+
+static int ChachaAEADDecrypt(WOLFSSL* ssl, byte* plain, const byte* input,
+                           word16 sz)
+{
+    byte additional[CHACHA20_BLOCK_SIZE];
+    byte nonce[AEAD_NONCE_SZ];
+    byte tag[POLY1305_AUTH_SZ];
+    byte cipher[CHACHA20_256_KEY_SIZE]; /* generated key for mac */
+    int ret = 0;
+
+    XMEMSET(tag, 0, sizeof(tag));
+    XMEMSET(cipher, 0, sizeof(cipher));
+    XMEMSET(nonce, 0, AEAD_NONCE_SZ);
+    XMEMSET(additional, 0, CHACHA20_BLOCK_SIZE);
+
+    #ifdef CHACHA_AEAD_TEST
+       int i;
+       printf("input before decrypt :\n");
+        for (i = 0; i < sz; i++) {
+           printf("%02x", input[i]);
+           if ((i + 1) % 16 == 0)
+               printf("\n");
+        }
+        printf("\n");
+    #endif
+
+    /* get nonce */
+    c32toa(ssl->keys.peer_sequence_number, nonce + AEAD_IMP_IV_SZ
+            + AEAD_SEQ_OFFSET);
+
+    /* sequence number field is 64-bits, we only use 32-bits */
+    c32toa(GetSEQIncrement(ssl, 1), additional + AEAD_SEQ_OFFSET);
+
+    /* get AD info */
+    additional[AEAD_TYPE_OFFSET] = ssl->curRL.type;
+    additional[AEAD_VMAJ_OFFSET] = ssl->curRL.pvMajor;
+    additional[AEAD_VMIN_OFFSET] = ssl->curRL.pvMinor;
+
+    /* Store the type, version. */
+    #ifdef WOLFSSL_DTLS
+        if (ssl->options.dtls)
+            c16toa(ssl->keys.dtls_state.curEpoch, additional);
+    #endif
+
+    #ifdef CHACHA_AEAD_TEST
+        printf("Decrypt Additional : ");
+        for (i = 0; i < CHACHA20_BLOCK_SIZE; i++) {
+            printf("%02x", additional[i]);
+        }
+        printf("\n\n");
+    #endif
+
+    /* set nonce and get poly1305 key */
+    if ((ret = wc_Chacha_SetIV(ssl->decrypt.chacha, nonce, 0)) != 0)
+        return ret;
+
+    if ((ret = wc_Chacha_Process(ssl->decrypt.chacha, cipher,
+                    cipher, sizeof(cipher))) != 0)
+        return ret;
+
+    /* get the tag : future use of hmac could go here*/
+    if (ssl->options.oldPoly == 1) {
+        if ((ret = Poly1305TagOld(ssl, additional, input, cipher,
+                        sz, tag)) != 0)
+            return ret;
+    }
+    else {
+        if ((ret = Poly1305Tag(ssl, additional, input, cipher,
+                        sz, tag)) != 0)
+            return ret;
+    }
+
+    /* check mac sent along with packet */
+    if (ConstantCompare(input + sz - ssl->specs.aead_mac_size, tag,
+                ssl->specs.aead_mac_size) != 0) {
+        WOLFSSL_MSG("Mac did not match");
+        SendAlert(ssl, alert_fatal, bad_record_mac);
+        ForceZero(nonce, AEAD_NONCE_SZ);
+        return VERIFY_MAC_ERROR;
+    }
+
+    /* if mac was good decrypt message */
+    if ((ret = wc_Chacha_Process(ssl->decrypt.chacha, plain, input,
+                   sz - ssl->specs.aead_mac_size)) != 0)
+        return ret;
+
+    #ifdef CHACHA_AEAD_TEST
+       printf("plain after decrypt :\n");
+        for (i = 0; i < sz; i++) {
+           printf("%02x", plain[i]);
+           if ((i + 1) % 16 == 0)
+               printf("\n");
+        }
+        printf("\n");
+    #endif
+
+    return ret;
+}
+#endif /* HAVE_CHACHA && HAVE_POLY1305 */
+#endif /* HAVE_AEAD */
+
+
+static INLINE int Encrypt(WOLFSSL* ssl, byte* out, const byte* input, word16 sz)
+{
+    int ret = 0;
+
+    (void)out;
+    (void)input;
+    (void)sz;
+
+    if (ssl->encrypt.setup == 0) {
+        WOLFSSL_MSG("Encrypt ciphers not setup");
+        return ENCRYPT_ERROR;
+    }
+
+#ifdef HAVE_FUZZER
+    if (ssl->fuzzerCb)
+        ssl->fuzzerCb(ssl, input, sz, FUZZ_ENCRYPT, ssl->fuzzerCtx);
+#endif
+
+    switch (ssl->specs.bulk_cipher_algorithm) {
+        #ifdef BUILD_ARC4
+            case wolfssl_rc4:
+                wc_Arc4Process(ssl->encrypt.arc4, out, input, sz);
+                break;
+        #endif
+
+        #ifdef BUILD_DES3
+            case wolfssl_triple_des:
+                ret = wc_Des3_CbcEncrypt(ssl->encrypt.des3, out, input, sz);
+                break;
+        #endif
+
+        #ifdef BUILD_AES
+            case wolfssl_aes:
+                ret = wc_AesCbcEncrypt(ssl->encrypt.aes, out, input, sz);
+                break;
+        #endif
+
+        #ifdef BUILD_AESGCM
+            case wolfssl_aes_gcm:
+                {
+                    byte additional[AEAD_AUTH_DATA_SZ];
+                    byte nonce[AEAD_NONCE_SZ];
+                    const byte* additionalSrc = input - 5;
+
+                    XMEMSET(additional, 0, AEAD_AUTH_DATA_SZ);
+
+                    /* sequence number field is 64-bits, we only use 32-bits */
+                    c32toa(GetSEQIncrement(ssl, 0),
+                                            additional + AEAD_SEQ_OFFSET);
+
+                    /* Store the type, version. Unfortunately, they are in
+                     * the input buffer ahead of the plaintext. */
+                    #ifdef WOLFSSL_DTLS
+                        if (ssl->options.dtls) {
+                            c16toa(ssl->keys.dtls_epoch, additional);
+                            additionalSrc -= DTLS_HANDSHAKE_EXTRA;
+                        }
+                    #endif
+                    XMEMCPY(additional + AEAD_TYPE_OFFSET, additionalSrc, 3);
+
+                    /* Store the length of the plain text minus the explicit
+                     * IV length minus the authentication tag size. */
+                    c16toa(sz - AEAD_EXP_IV_SZ - ssl->specs.aead_mac_size,
+                                                additional + AEAD_LEN_OFFSET);
+                    XMEMCPY(nonce,
+                                 ssl->keys.aead_enc_imp_IV, AEAD_IMP_IV_SZ);
+                    XMEMCPY(nonce + AEAD_IMP_IV_SZ,
+                                     ssl->keys.aead_exp_IV, AEAD_EXP_IV_SZ);
+                    ret = wc_AesGcmEncrypt(ssl->encrypt.aes,
+                                 out + AEAD_EXP_IV_SZ, input + AEAD_EXP_IV_SZ,
+                                 sz - AEAD_EXP_IV_SZ - ssl->specs.aead_mac_size,
+                                 nonce, AEAD_NONCE_SZ,
+                                 out + sz - ssl->specs.aead_mac_size,
+                                 ssl->specs.aead_mac_size,
+                                 additional, AEAD_AUTH_DATA_SZ);
+                    if (ret == 0)
+                        AeadIncrementExpIV(ssl);
+                    ForceZero(nonce, AEAD_NONCE_SZ);
+                }
+                break;
+        #endif
+
+        #ifdef HAVE_AESCCM
+            case wolfssl_aes_ccm:
+                {
+                    byte additional[AEAD_AUTH_DATA_SZ];
+                    byte nonce[AEAD_NONCE_SZ];
+                    const byte* additionalSrc = input - 5;
+
+                    XMEMSET(additional, 0, AEAD_AUTH_DATA_SZ);
+
+                    /* sequence number field is 64-bits, we only use 32-bits */
+                    c32toa(GetSEQIncrement(ssl, 0),
+                                            additional + AEAD_SEQ_OFFSET);
+
+                    /* Store the type, version. Unfortunately, they are in
+                     * the input buffer ahead of the plaintext. */
+                    #ifdef WOLFSSL_DTLS
+                        if (ssl->options.dtls) {
+                            c16toa(ssl->keys.dtls_epoch, additional);
+                            additionalSrc -= DTLS_HANDSHAKE_EXTRA;
+                        }
+                    #endif
+                    XMEMCPY(additional + AEAD_TYPE_OFFSET, additionalSrc, 3);
+
+                    /* Store the length of the plain text minus the explicit
+                     * IV length minus the authentication tag size. */
+                    c16toa(sz - AEAD_EXP_IV_SZ - ssl->specs.aead_mac_size,
+                                                additional + AEAD_LEN_OFFSET);
+                    XMEMCPY(nonce,
+                                 ssl->keys.aead_enc_imp_IV, AEAD_IMP_IV_SZ);
+                    XMEMCPY(nonce + AEAD_IMP_IV_SZ,
+                                     ssl->keys.aead_exp_IV, AEAD_EXP_IV_SZ);
+                    wc_AesCcmEncrypt(ssl->encrypt.aes,
+                        out + AEAD_EXP_IV_SZ, input + AEAD_EXP_IV_SZ,
+                            sz - AEAD_EXP_IV_SZ - ssl->specs.aead_mac_size,
+                        nonce, AEAD_NONCE_SZ,
+                        out + sz - ssl->specs.aead_mac_size,
+                        ssl->specs.aead_mac_size,
+                        additional, AEAD_AUTH_DATA_SZ);
+                    AeadIncrementExpIV(ssl);
+                    ForceZero(nonce, AEAD_NONCE_SZ);
+                }
+                break;
+        #endif
+
+        #ifdef HAVE_CAMELLIA
+            case wolfssl_camellia:
+                wc_CamelliaCbcEncrypt(ssl->encrypt.cam, out, input, sz);
+                break;
+        #endif
+
+        #ifdef HAVE_HC128
+            case wolfssl_hc128:
+                ret = wc_Hc128_Process(ssl->encrypt.hc128, out, input, sz);
+                break;
+        #endif
+
+        #ifdef BUILD_RABBIT
+            case wolfssl_rabbit:
+                ret = wc_RabbitProcess(ssl->encrypt.rabbit, out, input, sz);
+                break;
+        #endif
+
+        #if defined(HAVE_CHACHA) && defined(HAVE_POLY1305)
+            case wolfssl_chacha:
+                ret = ChachaAEADEncrypt(ssl, out, input, sz);
+                break;
+        #endif
+
+        #ifdef HAVE_NULL_CIPHER
+            case wolfssl_cipher_null:
+                if (input != out) {
+                    XMEMMOVE(out, input, sz);
+                }
+                break;
+        #endif
+
+            default:
+                WOLFSSL_MSG("wolfSSL Encrypt programming error");
+                ret = ENCRYPT_ERROR;
+    }
+
+    return ret;
+}
+
+
+
+static INLINE int Decrypt(WOLFSSL* ssl, byte* plain, const byte* input,
+                           word16 sz)
+{
+    int ret = 0;
+
+    (void)plain;
+    (void)input;
+    (void)sz;
+
+    if (ssl->decrypt.setup == 0) {
+        WOLFSSL_MSG("Decrypt ciphers not setup");
+        return DECRYPT_ERROR;
+    }
+
+    switch (ssl->specs.bulk_cipher_algorithm) {
+        #ifdef BUILD_ARC4
+            case wolfssl_rc4:
+                wc_Arc4Process(ssl->decrypt.arc4, plain, input, sz);
+                break;
+        #endif
+
+        #ifdef BUILD_DES3
+            case wolfssl_triple_des:
+                ret = wc_Des3_CbcDecrypt(ssl->decrypt.des3, plain, input, sz);
+                break;
+        #endif
+
+        #ifdef BUILD_AES
+            case wolfssl_aes:
+                ret = wc_AesCbcDecrypt(ssl->decrypt.aes, plain, input, sz);
+                break;
+        #endif
+
+        #ifdef BUILD_AESGCM
+            case wolfssl_aes_gcm:
+            {
+                byte additional[AEAD_AUTH_DATA_SZ];
+                byte nonce[AEAD_NONCE_SZ];
+
+                XMEMSET(additional, 0, AEAD_AUTH_DATA_SZ);
+
+                /* sequence number field is 64-bits, we only use 32-bits */
+                c32toa(GetSEQIncrement(ssl, 1), additional + AEAD_SEQ_OFFSET);
+
+                #ifdef WOLFSSL_DTLS
+                    if (ssl->options.dtls)
+                        c16toa(ssl->keys.dtls_state.curEpoch, additional);
+                #endif
+
+                additional[AEAD_TYPE_OFFSET] = ssl->curRL.type;
+                additional[AEAD_VMAJ_OFFSET] = ssl->curRL.pvMajor;
+                additional[AEAD_VMIN_OFFSET] = ssl->curRL.pvMinor;
+
+                c16toa(sz - AEAD_EXP_IV_SZ - ssl->specs.aead_mac_size,
+                                        additional + AEAD_LEN_OFFSET);
+                XMEMCPY(nonce, ssl->keys.aead_dec_imp_IV, AEAD_IMP_IV_SZ);
+                XMEMCPY(nonce + AEAD_IMP_IV_SZ, input, AEAD_EXP_IV_SZ);
+                if (wc_AesGcmDecrypt(ssl->decrypt.aes,
+                            plain + AEAD_EXP_IV_SZ,
+                            input + AEAD_EXP_IV_SZ,
+                                sz - AEAD_EXP_IV_SZ - ssl->specs.aead_mac_size,
+                            nonce, AEAD_NONCE_SZ,
+                            input + sz - ssl->specs.aead_mac_size,
+                            ssl->specs.aead_mac_size,
+                            additional, AEAD_AUTH_DATA_SZ) < 0) {
+                    SendAlert(ssl, alert_fatal, bad_record_mac);
+                    ret = VERIFY_MAC_ERROR;
+                }
+                ForceZero(nonce, AEAD_NONCE_SZ);
+            }
+            break;
+        #endif
+
+        #ifdef HAVE_AESCCM
+            case wolfssl_aes_ccm:
+            {
+                byte additional[AEAD_AUTH_DATA_SZ];
+                byte nonce[AEAD_NONCE_SZ];
+
+                XMEMSET(additional, 0, AEAD_AUTH_DATA_SZ);
+
+                /* sequence number field is 64-bits, we only use 32-bits */
+                c32toa(GetSEQIncrement(ssl, 1), additional + AEAD_SEQ_OFFSET);
+
+                #ifdef WOLFSSL_DTLS
+                    if (ssl->options.dtls)
+                        c16toa(ssl->keys.dtls_state.curEpoch, additional);
+                #endif
+
+                additional[AEAD_TYPE_OFFSET] = ssl->curRL.type;
+                additional[AEAD_VMAJ_OFFSET] = ssl->curRL.pvMajor;
+                additional[AEAD_VMIN_OFFSET] = ssl->curRL.pvMinor;
+
+                c16toa(sz - AEAD_EXP_IV_SZ - ssl->specs.aead_mac_size,
+                                        additional + AEAD_LEN_OFFSET);
+                XMEMCPY(nonce, ssl->keys.aead_dec_imp_IV, AEAD_IMP_IV_SZ);
+                XMEMCPY(nonce + AEAD_IMP_IV_SZ, input, AEAD_EXP_IV_SZ);
+                if (wc_AesCcmDecrypt(ssl->decrypt.aes,
+                            plain + AEAD_EXP_IV_SZ,
+                            input + AEAD_EXP_IV_SZ,
+                                sz - AEAD_EXP_IV_SZ - ssl->specs.aead_mac_size,
+                            nonce, AEAD_NONCE_SZ,
+                            input + sz - ssl->specs.aead_mac_size,
+                            ssl->specs.aead_mac_size,
+                            additional, AEAD_AUTH_DATA_SZ) < 0) {
+                    SendAlert(ssl, alert_fatal, bad_record_mac);
+                    ret = VERIFY_MAC_ERROR;
+                }
+                ForceZero(nonce, AEAD_NONCE_SZ);
+            }
+            break;
+        #endif
+
+        #ifdef HAVE_CAMELLIA
+            case wolfssl_camellia:
+                wc_CamelliaCbcDecrypt(ssl->decrypt.cam, plain, input, sz);
+                break;
+        #endif
+
+        #ifdef HAVE_HC128
+            case wolfssl_hc128:
+                ret = wc_Hc128_Process(ssl->decrypt.hc128, plain, input, sz);
+                break;
+        #endif
+
+        #ifdef BUILD_RABBIT
+            case wolfssl_rabbit:
+                ret = wc_RabbitProcess(ssl->decrypt.rabbit, plain, input, sz);
+                break;
+        #endif
+
+        #if defined(HAVE_CHACHA) && defined(HAVE_POLY1305)
+            case wolfssl_chacha:
+                ret = ChachaAEADDecrypt(ssl, plain, input, sz);
+                break;
+        #endif
+
+        #ifdef HAVE_NULL_CIPHER
+            case wolfssl_cipher_null:
+                if (input != plain) {
+                    XMEMMOVE(plain, input, sz);
+                }
+                break;
+        #endif
+
+            default:
+                WOLFSSL_MSG("wolfSSL Decrypt programming error");
+                ret = DECRYPT_ERROR;
+    }
+
+    return ret;
+}
+
+
+/* check cipher text size for sanity */
+static int SanityCheckCipherText(WOLFSSL* ssl, word32 encryptSz)
+{
+#ifdef HAVE_TRUNCATED_HMAC
+    word32 minLength = ssl->truncated_hmac ? TRUNCATED_HMAC_SZ
+                                           : ssl->specs.hash_size;
+#else
+    word32 minLength = ssl->specs.hash_size; /* covers stream */
+#endif
+
+    if (ssl->specs.cipher_type == block) {
+        if (encryptSz % ssl->specs.block_size) {
+            WOLFSSL_MSG("Block ciphertext not block size");
+            return SANITY_CIPHER_E;
+        }
+
+        minLength++;  /* pad byte */
+
+        if (ssl->specs.block_size > minLength)
+            minLength = ssl->specs.block_size;
+
+        if (ssl->options.tls1_1)
+            minLength += ssl->specs.block_size;  /* explicit IV */
+    }
+    else if (ssl->specs.cipher_type == aead) {
+        minLength = ssl->specs.aead_mac_size;    /* authTag size */
+        if (ssl->specs.bulk_cipher_algorithm != wolfssl_chacha)
+           minLength += AEAD_EXP_IV_SZ;          /* explicit IV  */
+    }
+
+    if (encryptSz < minLength) {
+        WOLFSSL_MSG("Ciphertext not minimum size");
+        return SANITY_CIPHER_E;
+    }
+
+    return 0;
+}
+
+
+#ifndef NO_OLD_TLS
+
+static INLINE void Md5Rounds(int rounds, const byte* data, int sz)
+{
+    Md5 md5;
+    int i;
+
+    wc_InitMd5(&md5);
+
+    for (i = 0; i < rounds; i++)
+        wc_Md5Update(&md5, data, sz);
+}
+
+
+
+/* do a dummy sha round */
+static INLINE void ShaRounds(int rounds, const byte* data, int sz)
+{
+    Sha sha;
+    int i;
+
+    wc_InitSha(&sha);  /* no error check on purpose, dummy round */
+
+    for (i = 0; i < rounds; i++)
+        wc_ShaUpdate(&sha, data, sz);
+}
+#endif
+
+
+#ifndef NO_SHA256
+
+static INLINE void Sha256Rounds(int rounds, const byte* data, int sz)
+{
+    Sha256 sha256;
+    int i;
+
+    wc_InitSha256(&sha256);  /* no error check on purpose, dummy round */
+
+    for (i = 0; i < rounds; i++) {
+        wc_Sha256Update(&sha256, data, sz);
+        /* no error check on purpose, dummy round */
+    }
+
+}
+
+#endif
+
+
+#ifdef WOLFSSL_SHA384
+
+static INLINE void Sha384Rounds(int rounds, const byte* data, int sz)
+{
+    Sha384 sha384;
+    int i;
+
+    wc_InitSha384(&sha384);  /* no error check on purpose, dummy round */
+
+    for (i = 0; i < rounds; i++) {
+        wc_Sha384Update(&sha384, data, sz);
+        /* no error check on purpose, dummy round */
+    }
+}
+
+#endif
+
+
+#ifdef WOLFSSL_SHA512
+
+static INLINE void Sha512Rounds(int rounds, const byte* data, int sz)
+{
+    Sha512 sha512;
+    int i;
+
+    wc_InitSha512(&sha512);  /* no error check on purpose, dummy round */
+
+    for (i = 0; i < rounds; i++) {
+        wc_Sha512Update(&sha512, data, sz);
+        /* no error check on purpose, dummy round */
+    }
+}
+
+#endif
+
+
+#ifdef WOLFSSL_RIPEMD
+
+static INLINE void RmdRounds(int rounds, const byte* data, int sz)
+{
+    RipeMd ripemd;
+    int i;
+
+    wc_InitRipeMd(&ripemd);
+
+    for (i = 0; i < rounds; i++)
+        wc_RipeMdUpdate(&ripemd, data, sz);
+}
+
+#endif
+
+
+/* Do dummy rounds */
+static INLINE void DoRounds(int type, int rounds, const byte* data, int sz)
+{
+    switch (type) {
+
+        case no_mac :
+            break;
+
+#ifndef NO_OLD_TLS
+#ifndef NO_MD5
+        case md5_mac :
+            Md5Rounds(rounds, data, sz);
+            break;
+#endif
+
+#ifndef NO_SHA
+        case sha_mac :
+            ShaRounds(rounds, data, sz);
+            break;
+#endif
+#endif
+
+#ifndef NO_SHA256
+        case sha256_mac :
+            Sha256Rounds(rounds, data, sz);
+            break;
+#endif
+
+#ifdef WOLFSSL_SHA384
+        case sha384_mac :
+            Sha384Rounds(rounds, data, sz);
+            break;
+#endif
+
+#ifdef WOLFSSL_SHA512
+        case sha512_mac :
+            Sha512Rounds(rounds, data, sz);
+            break;
+#endif
+
+#ifdef WOLFSSL_RIPEMD
+        case rmd_mac :
+            RmdRounds(rounds, data, sz);
+            break;
+#endif
+
+        default:
+            WOLFSSL_MSG("Bad round type");
+            break;
+    }
+}
+
+
+/* do number of compression rounds on dummy data */
+static INLINE void CompressRounds(WOLFSSL* ssl, int rounds, const byte* dummy)
+{
+    if (rounds)
+        DoRounds(ssl->specs.mac_algorithm, rounds, dummy, COMPRESS_LOWER);
+}
+
+
+/* check all length bytes for the pad value, return 0 on success */
+static int PadCheck(const byte* a, byte pad, int length)
+{
+    int i;
+    int compareSum = 0;
+
+    for (i = 0; i < length; i++) {
+        compareSum |= a[i] ^ pad;
+    }
+
+    return compareSum;
+}
+
+
+/* get compression extra rounds */
+static INLINE int GetRounds(int pLen, int padLen, int t)
+{
+    int  roundL1 = 1;  /* round up flags */
+    int  roundL2 = 1;
+
+    int L1 = COMPRESS_CONSTANT + pLen - t;
+    int L2 = COMPRESS_CONSTANT + pLen - padLen - 1 - t;
+
+    L1 -= COMPRESS_UPPER;
+    L2 -= COMPRESS_UPPER;
+
+    if ( (L1 % COMPRESS_LOWER) == 0)
+        roundL1 = 0;
+    if ( (L2 % COMPRESS_LOWER) == 0)
+        roundL2 = 0;
+
+    L1 /= COMPRESS_LOWER;
+    L2 /= COMPRESS_LOWER;
+
+    L1 += roundL1;
+    L2 += roundL2;
+
+    return L1 - L2;
+}
+
+
+/* timing resistant pad/verify check, return 0 on success */
+static int TimingPadVerify(WOLFSSL* ssl, const byte* input, int padLen, int t,
+                           int pLen, int content)
+{
+    byte verify[MAX_DIGEST_SIZE];
+    byte dmy[sizeof(WOLFSSL) >= MAX_PAD_SIZE ? 1 : MAX_PAD_SIZE] = {0};
+    byte* dummy = sizeof(dmy) < MAX_PAD_SIZE ? (byte*) ssl : dmy;
+    int  ret = 0;
+
+    (void)dmy;
+
+    if ( (t + padLen + 1) > pLen) {
+        WOLFSSL_MSG("Plain Len not long enough for pad/mac");
+        PadCheck(dummy, (byte)padLen, MAX_PAD_SIZE);
+        ssl->hmac(ssl, verify, input, pLen - t, content, 1); /* still compare */
+        ConstantCompare(verify, input + pLen - t, t);
+
+        return VERIFY_MAC_ERROR;
+    }
+
+    if (PadCheck(input + pLen - (padLen + 1), (byte)padLen, padLen + 1) != 0) {
+        WOLFSSL_MSG("PadCheck failed");
+        PadCheck(dummy, (byte)padLen, MAX_PAD_SIZE - padLen - 1);
+        ssl->hmac(ssl, verify, input, pLen - t, content, 1); /* still compare */
+        ConstantCompare(verify, input + pLen - t, t);
+
+        return VERIFY_MAC_ERROR;
+    }
+
+    PadCheck(dummy, (byte)padLen, MAX_PAD_SIZE - padLen - 1);
+    ret = ssl->hmac(ssl, verify, input, pLen - padLen - 1 - t, content, 1);
+
+    CompressRounds(ssl, GetRounds(pLen, padLen, t), dummy);
+
+    if (ConstantCompare(verify, input + (pLen - padLen - 1 - t), t) != 0) {
+        WOLFSSL_MSG("Verify MAC compare failed");
+        return VERIFY_MAC_ERROR;
+    }
+
+    if (ret != 0)
+        return VERIFY_MAC_ERROR;
+    return 0;
+}
+
+
+int DoApplicationData(WOLFSSL* ssl, byte* input, word32* inOutIdx)
+{
+    word32 msgSz   = ssl->keys.encryptSz;
+    word32 idx     = *inOutIdx;
+    int    dataSz;
+    int    ivExtra = 0;
+    byte*  rawData = input + idx;  /* keep current  for hmac */
+#ifdef HAVE_LIBZ
+    byte   decomp[MAX_RECORD_SIZE + MAX_COMP_EXTRA];
+#endif
+
+    if (ssl->options.handShakeDone == 0) {
+        WOLFSSL_MSG("Received App data before a handshake completed");
+        SendAlert(ssl, alert_fatal, unexpected_message);
+        return OUT_OF_ORDER_E;
+    }
+
+    if (ssl->specs.cipher_type == block) {
+        if (ssl->options.tls1_1)
+            ivExtra = ssl->specs.block_size;
+    }
+    else if (ssl->specs.cipher_type == aead) {
+        if (ssl->specs.bulk_cipher_algorithm != wolfssl_chacha)
+            ivExtra = AEAD_EXP_IV_SZ;
+    }
+
+    dataSz = msgSz - ivExtra - ssl->keys.padSz;
+    if (dataSz < 0) {
+        WOLFSSL_MSG("App data buffer error, malicious input?");
+        return BUFFER_ERROR;
+    }
+
+    /* read data */
+    if (dataSz) {
+        int rawSz = dataSz;       /* keep raw size for idx adjustment */
+
+#ifdef HAVE_LIBZ
+        if (ssl->options.usingCompression) {
+            dataSz = myDeCompress(ssl, rawData, dataSz, decomp, sizeof(decomp));
+            if (dataSz < 0) return dataSz;
+        }
+#endif
+        idx += rawSz;
+
+        ssl->buffers.clearOutputBuffer.buffer = rawData;
+        ssl->buffers.clearOutputBuffer.length = dataSz;
+    }
+
+    idx += ssl->keys.padSz;
+
+#ifdef HAVE_LIBZ
+    /* decompress could be bigger, overwrite after verify */
+    if (ssl->options.usingCompression)
+        XMEMMOVE(rawData, decomp, dataSz);
+#endif
+
+    *inOutIdx = idx;
+    return 0;
+}
+
+
+/* process alert, return level */
+static int DoAlert(WOLFSSL* ssl, byte* input, word32* inOutIdx, int* type,
+                   word32 totalSz)
+{
+    byte level;
+    byte code;
+
+    #ifdef WOLFSSL_CALLBACKS
+        if (ssl->hsInfoOn)
+            AddPacketName("Alert", &ssl->handShakeInfo);
+        if (ssl->toInfoOn)
+            /* add record header back on to info + 2 byte level, data */
+            AddPacketInfo("Alert", &ssl->timeoutInfo, input + *inOutIdx -
+                          RECORD_HEADER_SZ, 2 + RECORD_HEADER_SZ, ssl->heap);
+    #endif
+
+    /* make sure can read the message */
+    if (*inOutIdx + ALERT_SIZE > totalSz)
+        return BUFFER_E;
+
+    level = input[(*inOutIdx)++];
+    code  = input[(*inOutIdx)++];
+    ssl->alert_history.last_rx.code = code;
+    ssl->alert_history.last_rx.level = level;
+    *type = code;
+    if (level == alert_fatal) {
+        ssl->options.isClosed = 1;  /* Don't send close_notify */
+    }
+
+    WOLFSSL_MSG("Got alert");
+    if (*type == close_notify) {
+        WOLFSSL_MSG("    close notify");
+        ssl->options.closeNotify = 1;
+    }
+    WOLFSSL_ERROR(*type);
+    if (ssl->keys.encryptionOn) {
+        if (*inOutIdx + ssl->keys.padSz > totalSz)
+            return BUFFER_E;
+        *inOutIdx += ssl->keys.padSz;
+    }
+
+    return level;
+}
+
+static int GetInputData(WOLFSSL *ssl, word32 size)
+{
+    int in;
+    int inSz;
+    int maxLength;
+    int usedLength;
+    int dtlsExtra = 0;
+
+
+    /* check max input length */
+    usedLength = ssl->buffers.inputBuffer.length - ssl->buffers.inputBuffer.idx;
+    maxLength  = ssl->buffers.inputBuffer.bufferSize - usedLength;
+    inSz       = (int)(size - usedLength);      /* from last partial read */
+
+#ifdef WOLFSSL_DTLS
+    if (ssl->options.dtls) {
+        if (size < ssl->dtls_expected_rx)
+            dtlsExtra = (int)(ssl->dtls_expected_rx - size);
+        inSz = ssl->dtls_expected_rx;
+    }
+#endif
+
+    if (inSz > maxLength) {
+        if (GrowInputBuffer(ssl, size + dtlsExtra, usedLength) < 0)
+            return MEMORY_E;
+    }
+
+    if (inSz <= 0)
+        return BUFFER_ERROR;
+
+    /* Put buffer data at start if not there */
+    if (usedLength > 0 && ssl->buffers.inputBuffer.idx != 0)
+        XMEMMOVE(ssl->buffers.inputBuffer.buffer,
+                ssl->buffers.inputBuffer.buffer + ssl->buffers.inputBuffer.idx,
+                usedLength);
+
+    /* remove processed data */
+    ssl->buffers.inputBuffer.idx    = 0;
+    ssl->buffers.inputBuffer.length = usedLength;
+
+    /* read data from network */
+    do {
+        in = Receive(ssl,
+                     ssl->buffers.inputBuffer.buffer +
+                     ssl->buffers.inputBuffer.length,
+                     inSz);
+        if (in == -1)
+            return SOCKET_ERROR_E;
+
+        if (in == WANT_READ)
+            return WANT_READ;
+
+        if (in > inSz)
+            return RECV_OVERFLOW_E;
+
+        ssl->buffers.inputBuffer.length += in;
+        inSz -= in;
+
+    } while (ssl->buffers.inputBuffer.length < size);
+
+    return 0;
+}
+
+
+static INLINE int VerifyMac(WOLFSSL* ssl, const byte* input, word32 msgSz,
+                            int content, word32* padSz)
+{
+    int    ivExtra = 0;
+    int    ret;
+    word32 pad     = 0;
+    word32 padByte = 0;
+#ifdef HAVE_TRUNCATED_HMAC
+    word32 digestSz = ssl->truncated_hmac ? TRUNCATED_HMAC_SZ
+                                          : ssl->specs.hash_size;
+#else
+    word32 digestSz = ssl->specs.hash_size;
+#endif
+    byte   verify[MAX_DIGEST_SIZE];
+
+    if (ssl->specs.cipher_type == block) {
+        if (ssl->options.tls1_1)
+            ivExtra = ssl->specs.block_size;
+        pad = *(input + msgSz - ivExtra - 1);
+        padByte = 1;
+
+        if (ssl->options.tls) {
+            ret = TimingPadVerify(ssl, input, pad, digestSz, msgSz - ivExtra,
+                                  content);
+            if (ret != 0)
+                return ret;
+        }
+        else {  /* sslv3, some implementations have bad padding, but don't
+                 * allow bad read */
+            int  badPadLen = 0;
+            byte dmy[sizeof(WOLFSSL) >= MAX_PAD_SIZE ? 1 : MAX_PAD_SIZE] = {0};
+            byte* dummy = sizeof(dmy) < MAX_PAD_SIZE ? (byte*) ssl : dmy;
+
+            (void)dmy;
+
+            if (pad > (msgSz - digestSz - 1)) {
+                WOLFSSL_MSG("Plain Len not long enough for pad/mac");
+                pad       = 0;  /* no bad read */
+                badPadLen = 1;
+            }
+            PadCheck(dummy, (byte)pad, MAX_PAD_SIZE);  /* timing only */
+            ret = ssl->hmac(ssl, verify, input, msgSz - digestSz - pad - 1,
+                            content, 1);
+            if (ConstantCompare(verify, input + msgSz - digestSz - pad - 1,
+                                digestSz) != 0)
+                return VERIFY_MAC_ERROR;
+            if (ret != 0 || badPadLen)
+                return VERIFY_MAC_ERROR;
+        }
+    }
+    else if (ssl->specs.cipher_type == stream) {
+        ret = ssl->hmac(ssl, verify, input, msgSz - digestSz, content, 1);
+        if (ConstantCompare(verify, input + msgSz - digestSz, digestSz) != 0){
+            return VERIFY_MAC_ERROR;
+        }
+        if (ret != 0)
+            return VERIFY_MAC_ERROR;
+    }
+
+    if (ssl->specs.cipher_type == aead) {
+        *padSz = ssl->specs.aead_mac_size;
+    }
+    else {
+        *padSz = digestSz + pad + padByte;
+    }
+
+    return 0;
+}
+
+
+/* process input requests, return 0 is done, 1 is call again to complete, and
+   negative number is error */
+int ProcessReply(WOLFSSL* ssl)
+{
+    int    ret = 0, type, readSz;
+    int    atomicUser = 0;
+    word32 startIdx = 0;
+#ifdef WOLFSSL_DTLS
+    int    used;
+#endif
+
+#ifdef ATOMIC_USER
+    if (ssl->ctx->DecryptVerifyCb)
+        atomicUser = 1;
+#endif
+
+    if (ssl->error != 0 && ssl->error != WANT_READ && ssl->error != WANT_WRITE){
+        WOLFSSL_MSG("ProcessReply retry in error state, not allowed");
+        return ssl->error;
+    }
+
+    for (;;) {
+        switch (ssl->options.processReply) {
+
+        /* in the WOLFSSL_SERVER case, get the first byte for detecting
+         * old client hello */
+        case doProcessInit:
+
+            readSz = RECORD_HEADER_SZ;
+
+            #ifdef WOLFSSL_DTLS
+                if (ssl->options.dtls)
+                    readSz = DTLS_RECORD_HEADER_SZ;
+            #endif
+
+            /* get header or return error */
+            if (!ssl->options.dtls) {
+                if ((ret = GetInputData(ssl, readSz)) < 0)
+                    return ret;
+            } else {
+            #ifdef WOLFSSL_DTLS
+                /* read ahead may already have header */
+                used = ssl->buffers.inputBuffer.length -
+                       ssl->buffers.inputBuffer.idx;
+                if (used < readSz)
+                    if ((ret = GetInputData(ssl, readSz)) < 0)
+                        return ret;
+            #endif
+            }
+
+#ifdef OLD_HELLO_ALLOWED
+
+            /* see if sending SSLv2 client hello */
+            if ( ssl->options.side == WOLFSSL_SERVER_END &&
+                 ssl->options.clientState == NULL_STATE &&
+                 ssl->buffers.inputBuffer.buffer[ssl->buffers.inputBuffer.idx]
+                         != handshake) {
+                byte b0, b1;
+
+                ssl->options.processReply = runProcessOldClientHello;
+
+                /* sanity checks before getting size at front */
+                if (ssl->buffers.inputBuffer.buffer[
+                          ssl->buffers.inputBuffer.idx + 2] != OLD_HELLO_ID) {
+                    WOLFSSL_MSG("Not a valid old client hello");
+                    return PARSE_ERROR;
+                }
+
+                if (ssl->buffers.inputBuffer.buffer[
+                          ssl->buffers.inputBuffer.idx + 3] != SSLv3_MAJOR &&
+                    ssl->buffers.inputBuffer.buffer[
+                          ssl->buffers.inputBuffer.idx + 3] != DTLS_MAJOR) {
+                    WOLFSSL_MSG("Not a valid version in old client hello");
+                    return PARSE_ERROR;
+                }
+
+                /* how many bytes need ProcessOldClientHello */
+                b0 =
+                ssl->buffers.inputBuffer.buffer[ssl->buffers.inputBuffer.idx++];
+                b1 =
+                ssl->buffers.inputBuffer.buffer[ssl->buffers.inputBuffer.idx++];
+                ssl->curSize = (word16)(((b0 & 0x7f) << 8) | b1);
+            }
+            else {
+                ssl->options.processReply = getRecordLayerHeader;
+                continue;
+            }
+
+        /* in the WOLFSSL_SERVER case, run the old client hello */
+        case runProcessOldClientHello:
+
+            /* get sz bytes or return error */
+            if (!ssl->options.dtls) {
+                if ((ret = GetInputData(ssl, ssl->curSize)) < 0)
+                    return ret;
+            } else {
+            #ifdef WOLFSSL_DTLS
+                /* read ahead may already have */
+                used = ssl->buffers.inputBuffer.length -
+                       ssl->buffers.inputBuffer.idx;
+                if (used < ssl->curSize)
+                    if ((ret = GetInputData(ssl, ssl->curSize)) < 0)
+                        return ret;
+            #endif  /* WOLFSSL_DTLS */
+            }
+
+            ret = ProcessOldClientHello(ssl, ssl->buffers.inputBuffer.buffer,
+                                        &ssl->buffers.inputBuffer.idx,
+                                        ssl->buffers.inputBuffer.length -
+                                        ssl->buffers.inputBuffer.idx,
+                                        ssl->curSize);
+            if (ret < 0)
+                return ret;
+
+            else if (ssl->buffers.inputBuffer.idx ==
+                     ssl->buffers.inputBuffer.length) {
+                ssl->options.processReply = doProcessInit;
+                return 0;
+            }
+
+#endif  /* OLD_HELLO_ALLOWED */
+
+        /* get the record layer header */
+        case getRecordLayerHeader:
+
+            ret = GetRecordHeader(ssl, ssl->buffers.inputBuffer.buffer,
+                                       &ssl->buffers.inputBuffer.idx,
+                                       &ssl->curRL, &ssl->curSize);
+#ifdef WOLFSSL_DTLS
+            if (ssl->options.dtls && ret == SEQUENCE_ERROR) {
+                ssl->options.processReply = doProcessInit;
+                ssl->buffers.inputBuffer.length = 0;
+                ssl->buffers.inputBuffer.idx = 0;
+                continue;
+            }
+#endif
+            if (ret != 0)
+                return ret;
+
+            ssl->options.processReply = getData;
+
+        /* retrieve record layer data */
+        case getData:
+
+            /* get sz bytes or return error */
+            if (!ssl->options.dtls) {
+                if ((ret = GetInputData(ssl, ssl->curSize)) < 0)
+                    return ret;
+            } else {
+#ifdef WOLFSSL_DTLS
+                /* read ahead may already have */
+                used = ssl->buffers.inputBuffer.length -
+                       ssl->buffers.inputBuffer.idx;
+                if (used < ssl->curSize)
+                    if ((ret = GetInputData(ssl, ssl->curSize)) < 0)
+                        return ret;
+#endif
+            }
+
+            ssl->options.processReply = runProcessingOneMessage;
+            startIdx = ssl->buffers.inputBuffer.idx;  /* in case > 1 msg per */
+
+        /* the record layer is here */
+        case runProcessingOneMessage:
+
+            #ifdef WOLFSSL_DTLS
+            if (ssl->options.dtls &&
+                ssl->keys.dtls_state.curEpoch < ssl->keys.dtls_state.nextEpoch)
+                ssl->keys.decryptedCur = 1;
+            #endif
+
+            if (ssl->keys.encryptionOn && ssl->keys.decryptedCur == 0)
+            {
+                ret = SanityCheckCipherText(ssl, ssl->curSize);
+                if (ret < 0)
+                    return ret;
+
+                if (atomicUser) {
+                #ifdef ATOMIC_USER
+                    ret = ssl->ctx->DecryptVerifyCb(ssl,
+                                  ssl->buffers.inputBuffer.buffer +
+                                  ssl->buffers.inputBuffer.idx,
+                                  ssl->buffers.inputBuffer.buffer +
+                                  ssl->buffers.inputBuffer.idx,
+                                  ssl->curSize, ssl->curRL.type, 1,
+                                  &ssl->keys.padSz, ssl->DecryptVerifyCtx);
+                    if (ssl->options.tls1_1 && ssl->specs.cipher_type == block)
+                        ssl->buffers.inputBuffer.idx += ssl->specs.block_size;
+                        /* go past TLSv1.1 IV */
+                    if (ssl->specs.cipher_type == aead &&
+                            ssl->specs.bulk_cipher_algorithm != wolfssl_chacha)
+                        ssl->buffers.inputBuffer.idx += AEAD_EXP_IV_SZ;
+                #endif /* ATOMIC_USER */
+                }
+                else {
+                    ret = Decrypt(ssl, ssl->buffers.inputBuffer.buffer +
+                                  ssl->buffers.inputBuffer.idx,
+                                  ssl->buffers.inputBuffer.buffer +
+                                  ssl->buffers.inputBuffer.idx,
+                                  ssl->curSize);
+                    if (ret < 0) {
+                        WOLFSSL_ERROR(ret);
+                        return DECRYPT_ERROR;
+                    }
+                    if (ssl->options.tls1_1 && ssl->specs.cipher_type == block)
+                        ssl->buffers.inputBuffer.idx += ssl->specs.block_size;
+                        /* go past TLSv1.1 IV */
+                    if (ssl->specs.cipher_type == aead &&
+                            ssl->specs.bulk_cipher_algorithm != wolfssl_chacha)
+                        ssl->buffers.inputBuffer.idx += AEAD_EXP_IV_SZ;
+
+                    ret = VerifyMac(ssl, ssl->buffers.inputBuffer.buffer +
+                                    ssl->buffers.inputBuffer.idx,
+                                    ssl->curSize, ssl->curRL.type,
+                                    &ssl->keys.padSz);
+                }
+                if (ret < 0) {
+                    WOLFSSL_ERROR(ret);
+                    return DECRYPT_ERROR;
+                }
+                ssl->keys.encryptSz    = ssl->curSize;
+                ssl->keys.decryptedCur = 1;
+            }
+
+            if (ssl->options.dtls) {
+            #ifdef WOLFSSL_DTLS
+                DtlsUpdateWindow(&ssl->keys.dtls_state);
+            #endif /* WOLFSSL_DTLS */
+            }
+
+            WOLFSSL_MSG("received record layer msg");
+
+            switch (ssl->curRL.type) {
+                case handshake :
+                    /* debugging in DoHandShakeMsg */
+                    if (!ssl->options.dtls) {
+                        ret = DoHandShakeMsg(ssl,
+                                            ssl->buffers.inputBuffer.buffer,
+                                            &ssl->buffers.inputBuffer.idx,
+                                            ssl->buffers.inputBuffer.length);
+                    }
+                    else {
+#ifdef WOLFSSL_DTLS
+                        ret = DoDtlsHandShakeMsg(ssl,
+                                            ssl->buffers.inputBuffer.buffer,
+                                            &ssl->buffers.inputBuffer.idx,
+                                            ssl->buffers.inputBuffer.length);
+#endif
+                    }
+                    if (ret != 0)
+                        return ret;
+                    break;
+
+                case change_cipher_spec:
+                    WOLFSSL_MSG("got CHANGE CIPHER SPEC");
+                    #ifdef WOLFSSL_CALLBACKS
+                        if (ssl->hsInfoOn)
+                            AddPacketName("ChangeCipher", &ssl->handShakeInfo);
+                        /* add record header back on info */
+                        if (ssl->toInfoOn) {
+                            AddPacketInfo("ChangeCipher", &ssl->timeoutInfo,
+                                ssl->buffers.inputBuffer.buffer +
+                                ssl->buffers.inputBuffer.idx - RECORD_HEADER_SZ,
+                                1 + RECORD_HEADER_SZ, ssl->heap);
+                            AddLateRecordHeader(&ssl->curRL, &ssl->timeoutInfo);
+                        }
+                    #endif
+
+                    ret = SanityCheckMsgReceived(ssl, change_cipher_hs);
+                    if (ret != 0)
+                        return ret;
+
+#ifdef HAVE_SESSION_TICKET
+                    if (ssl->options.side == WOLFSSL_CLIENT_END &&
+                                                  ssl->expect_session_ticket) {
+                        WOLFSSL_MSG("Expected session ticket missing");
+                        return SESSION_TICKET_EXPECT_E;
+                    }
+#endif
+
+                    if (ssl->keys.encryptionOn && ssl->options.handShakeDone) {
+                        ssl->buffers.inputBuffer.idx += ssl->keys.padSz;
+                        ssl->curSize -= (word16) ssl->buffers.inputBuffer.idx;
+                    }
+
+                    if (ssl->curSize != 1) {
+                        WOLFSSL_MSG("Malicious or corrupted ChangeCipher msg");
+                        return LENGTH_ERROR;
+                    }
+                    #ifndef NO_CERTS
+                        if (ssl->options.side == WOLFSSL_SERVER_END &&
+                                 ssl->options.verifyPeer &&
+                                 ssl->options.havePeerCert)
+                            if (!ssl->options.havePeerVerify) {
+                                WOLFSSL_MSG("client didn't send cert verify");
+                                return NO_PEER_VERIFY;
+                            }
+                    #endif
+
+
+                    ssl->buffers.inputBuffer.idx++;
+                    ssl->keys.encryptionOn = 1;
+
+                    /* setup decrypt keys for following messages */
+                    if ((ret = SetKeysSide(ssl, DECRYPT_SIDE_ONLY)) != 0)
+                        return ret;
+
+                    #ifdef WOLFSSL_DTLS
+                        if (ssl->options.dtls) {
+                            DtlsPoolReset(ssl);
+                            ssl->keys.dtls_state.nextEpoch++;
+                            ssl->keys.dtls_state.nextSeq = 0;
+                        }
+                    #endif
+
+                    #ifdef HAVE_LIBZ
+                        if (ssl->options.usingCompression)
+                            if ( (ret = InitStreams(ssl)) != 0)
+                                return ret;
+                    #endif
+                    ret = BuildFinished(ssl, &ssl->hsHashes->verifyHashes,
+                                       ssl->options.side == WOLFSSL_CLIENT_END ?
+                                       server : client);
+                    if (ret != 0)
+                        return ret;
+                    break;
+
+                case application_data:
+                    WOLFSSL_MSG("got app DATA");
+                    if ((ret = DoApplicationData(ssl,
+                                                ssl->buffers.inputBuffer.buffer,
+                                               &ssl->buffers.inputBuffer.idx))
+                                                                         != 0) {
+                        WOLFSSL_ERROR(ret);
+                        return ret;
+                    }
+                    break;
+
+                case alert:
+                    WOLFSSL_MSG("got ALERT!");
+                    ret = DoAlert(ssl, ssl->buffers.inputBuffer.buffer,
+                                  &ssl->buffers.inputBuffer.idx, &type,
+                                   ssl->buffers.inputBuffer.length);
+                    if (ret == alert_fatal)
+                        return FATAL_ERROR;
+                    else if (ret < 0)
+                        return ret;
+
+                    /* catch warnings that are handled as errors */
+                    if (type == close_notify)
+                        return ssl->error = ZERO_RETURN;
+
+                    if (type == decrypt_error)
+                        return FATAL_ERROR;
+                    break;
+
+                default:
+                    WOLFSSL_ERROR(UNKNOWN_RECORD_TYPE);
+                    return UNKNOWN_RECORD_TYPE;
+            }
+
+            ssl->options.processReply = doProcessInit;
+
+            /* input exhausted? */
+            if (ssl->buffers.inputBuffer.idx == ssl->buffers.inputBuffer.length)
+                return 0;
+
+            /* more messages per record */
+            else if ((ssl->buffers.inputBuffer.idx - startIdx) < ssl->curSize) {
+                WOLFSSL_MSG("More messages in record");
+                #ifdef WOLFSSL_DTLS
+                    /* read-ahead but dtls doesn't bundle messages per record */
+                    if (ssl->options.dtls) {
+                        ssl->options.processReply = doProcessInit;
+                        continue;
+                    }
+                #endif
+                ssl->options.processReply = runProcessingOneMessage;
+
+                if (ssl->keys.encryptionOn) {
+                    WOLFSSL_MSG("Bundled encrypted messages, remove middle pad");
+                    ssl->buffers.inputBuffer.idx -= ssl->keys.padSz;
+                }
+
+                continue;
+            }
+            /* more records */
+            else {
+                WOLFSSL_MSG("More records in input");
+                ssl->options.processReply = doProcessInit;
+                continue;
+            }
+
+        default:
+            WOLFSSL_MSG("Bad process input state, programming error");
+            return INPUT_CASE_ERROR;
+        }
+    }
+}
+
+
+int SendChangeCipher(WOLFSSL* ssl)
+{
+    byte              *output;
+    int                sendSz = RECORD_HEADER_SZ + ENUM_LEN;
+    int                idx    = RECORD_HEADER_SZ;
+    int                ret;
+
+    #ifdef WOLFSSL_DTLS
+        if (ssl->options.dtls) {
+            sendSz += DTLS_RECORD_EXTRA;
+            idx    += DTLS_RECORD_EXTRA;
+        }
+    #endif
+
+    /* are we in scr */
+    if (ssl->keys.encryptionOn && ssl->options.handShakeDone) {
+        sendSz += MAX_MSG_EXTRA;
+    }
+
+    /* check for avalaible size */
+    if ((ret = CheckAvailableSize(ssl, sendSz)) != 0)
+        return ret;
+
+    /* get ouput buffer */
+    output = ssl->buffers.outputBuffer.buffer +
+             ssl->buffers.outputBuffer.length;
+
+    AddRecordHeader(output, 1, change_cipher_spec, ssl);
+
+    output[idx] = 1;             /* turn it on */
+
+    if (ssl->keys.encryptionOn && ssl->options.handShakeDone) {
+        byte input[ENUM_LEN];
+        int  inputSz = ENUM_LEN;
+
+        input[0] = 1;  /* turn it on */
+        sendSz = BuildMessage(ssl, output, sendSz, input, inputSz,
+                              change_cipher_spec);
+        if (sendSz < 0)
+            return sendSz;
+    }
+
+    #ifdef WOLFSSL_DTLS
+        if (ssl->options.dtls) {
+            if ((ret = DtlsPoolSave(ssl, output, sendSz)) != 0)
+                return ret;
+        }
+    #endif
+    #ifdef WOLFSSL_CALLBACKS
+        if (ssl->hsInfoOn) AddPacketName("ChangeCipher", &ssl->handShakeInfo);
+        if (ssl->toInfoOn)
+            AddPacketInfo("ChangeCipher", &ssl->timeoutInfo, output, sendSz,
+                           ssl->heap);
+    #endif
+    ssl->buffers.outputBuffer.length += sendSz;
+
+    if (ssl->options.groupMessages)
+        return 0;
+    #ifdef WOLFSSL_DTLS
+    else if (ssl->options.dtls) {
+        /* If using DTLS, force the ChangeCipherSpec message to be in the
+         * same datagram as the finished message. */
+        return 0;
+    }
+    #endif
+    else
+        return SendBuffered(ssl);
+}
+
+
+#ifndef NO_OLD_TLS
+static int SSL_hmac(WOLFSSL* ssl, byte* digest, const byte* in, word32 sz,
+                 int content, int verify)
+{
+    byte   result[MAX_DIGEST_SIZE];
+    word32 digestSz = ssl->specs.hash_size;            /* actual sizes */
+    word32 padSz    = ssl->specs.pad_size;
+    int    ret      = 0;
+
+    Md5 md5;
+    Sha sha;
+
+    /* data */
+    byte seq[SEQ_SZ];
+    byte conLen[ENUM_LEN + LENGTH_SZ];     /* content & length */
+    const byte* macSecret = wolfSSL_GetMacSecret(ssl, verify);
+
+#ifdef HAVE_FUZZER
+    if (ssl->fuzzerCb)
+        ssl->fuzzerCb(ssl, in, sz, FUZZ_HMAC, ssl->fuzzerCtx);
+#endif
+
+    XMEMSET(seq, 0, SEQ_SZ);
+    conLen[0] = (byte)content;
+    c16toa((word16)sz, &conLen[ENUM_LEN]);
+    c32toa(GetSEQIncrement(ssl, verify), &seq[sizeof(word32)]);
+
+    if (ssl->specs.mac_algorithm == md5_mac) {
+        wc_InitMd5(&md5);
+        /* inner */
+        wc_Md5Update(&md5, macSecret, digestSz);
+        wc_Md5Update(&md5, PAD1, padSz);
+        wc_Md5Update(&md5, seq, SEQ_SZ);
+        wc_Md5Update(&md5, conLen, sizeof(conLen));
+        /* in buffer */
+        wc_Md5Update(&md5, in, sz);
+        wc_Md5Final(&md5, result);
+        /* outer */
+        wc_Md5Update(&md5, macSecret, digestSz);
+        wc_Md5Update(&md5, PAD2, padSz);
+        wc_Md5Update(&md5, result, digestSz);
+        wc_Md5Final(&md5, digest);
+    }
+    else {
+        ret = wc_InitSha(&sha);
+        if (ret != 0)
+            return ret;
+        /* inner */
+        wc_ShaUpdate(&sha, macSecret, digestSz);
+        wc_ShaUpdate(&sha, PAD1, padSz);
+        wc_ShaUpdate(&sha, seq, SEQ_SZ);
+        wc_ShaUpdate(&sha, conLen, sizeof(conLen));
+        /* in buffer */
+        wc_ShaUpdate(&sha, in, sz);
+        wc_ShaFinal(&sha, result);
+        /* outer */
+        wc_ShaUpdate(&sha, macSecret, digestSz);
+        wc_ShaUpdate(&sha, PAD2, padSz);
+        wc_ShaUpdate(&sha, result, digestSz);
+        wc_ShaFinal(&sha, digest);
+    }
+    return 0;
+}
+
+#ifndef NO_CERTS
+static void BuildMD5_CertVerify(WOLFSSL* ssl, byte* digest)
+{
+    byte md5_result[MD5_DIGEST_SIZE];
+
+#ifdef WOLFSSL_SMALL_STACK
+        Md5* md5   = (Md5*)XMALLOC(sizeof(Md5), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        Md5* md5_2 = (Md5*)XMALLOC(sizeof(Md5), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#else
+        Md5 md5[1];
+        Md5 md5_2[1];
+#endif
+
+    /* make md5 inner */
+    md5[0] = ssl->hsHashes->hashMd5 ; /* Save current position */
+    wc_Md5Update(&ssl->hsHashes->hashMd5, ssl->arrays->masterSecret,SECRET_LEN);
+    wc_Md5Update(&ssl->hsHashes->hashMd5, PAD1, PAD_MD5);
+    wc_Md5GetHash(&ssl->hsHashes->hashMd5, md5_result);
+    wc_Md5RestorePos(&ssl->hsHashes->hashMd5, md5) ; /* Restore current position */
+
+    /* make md5 outer */
+    wc_InitMd5(md5_2) ;
+    wc_Md5Update(md5_2, ssl->arrays->masterSecret, SECRET_LEN);
+    wc_Md5Update(md5_2, PAD2, PAD_MD5);
+    wc_Md5Update(md5_2, md5_result, MD5_DIGEST_SIZE);
+
+    wc_Md5Final(md5_2, digest);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(md5, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(md5_2, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+}
+
+
+static void BuildSHA_CertVerify(WOLFSSL* ssl, byte* digest)
+{
+    byte sha_result[SHA_DIGEST_SIZE];
+
+#ifdef WOLFSSL_SMALL_STACK
+        Sha* sha   = (Sha*)XMALLOC(sizeof(Sha), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        Sha* sha2 = (Sha*)XMALLOC(sizeof(Sha), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#else
+        Sha sha[1];
+        Sha sha2[1];
+#endif
+
+    /* make sha inner */
+    sha[0] = ssl->hsHashes->hashSha ; /* Save current position */
+    wc_ShaUpdate(&ssl->hsHashes->hashSha, ssl->arrays->masterSecret,SECRET_LEN);
+    wc_ShaUpdate(&ssl->hsHashes->hashSha, PAD1, PAD_SHA);
+    wc_ShaGetHash(&ssl->hsHashes->hashSha, sha_result);
+    wc_ShaRestorePos(&ssl->hsHashes->hashSha, sha) ; /* Restore current position */
+
+    /* make sha outer */
+    wc_InitSha(sha2) ;
+    wc_ShaUpdate(sha2, ssl->arrays->masterSecret,SECRET_LEN);
+    wc_ShaUpdate(sha2, PAD2, PAD_SHA);
+    wc_ShaUpdate(sha2, sha_result, SHA_DIGEST_SIZE);
+
+    wc_ShaFinal(sha2, digest);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(sha, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(sha2, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+}
+#endif /* NO_CERTS */
+#endif /* NO_OLD_TLS */
+
+
+#ifndef NO_CERTS
+
+static int BuildCertHashes(WOLFSSL* ssl, Hashes* hashes)
+{
+    /* store current states, building requires get_digest which resets state */
+    #ifdef WOLFSSL_SHA384
+        Sha384 sha384 = ssl->hsHashes->hashSha384;
+    #endif
+    #ifdef WOLFSSL_SHA512
+        Sha512 sha512 = ssl->hsHashes->hashSha512;
+    #endif
+
+    if (ssl->options.tls) {
+#if ! defined( NO_OLD_TLS )
+        wc_Md5GetHash(&ssl->hsHashes->hashMd5, hashes->md5);
+        wc_ShaGetHash(&ssl->hsHashes->hashSha, hashes->sha);
+#endif
+        if (IsAtLeastTLSv1_2(ssl)) {
+            int ret;
+
+            #ifndef NO_SHA256
+                ret = wc_Sha256GetHash(&ssl->hsHashes->hashSha256,hashes->sha256);
+                if (ret != 0)
+                    return ret;
+            #endif
+            #ifdef WOLFSSL_SHA384
+                ret = wc_Sha384Final(&ssl->hsHashes->hashSha384,hashes->sha384);
+                if (ret != 0)
+                    return ret;
+            #endif
+            #ifdef WOLFSSL_SHA512
+                ret = wc_Sha512Final(&ssl->hsHashes->hashSha512,hashes->sha512);
+                if (ret != 0)
+                    return ret;
+            #endif
+        }
+    }
+#if ! defined( NO_OLD_TLS )
+    else {
+        BuildMD5_CertVerify(ssl, hashes->md5);
+        BuildSHA_CertVerify(ssl, hashes->sha);
+    }
+
+    /* restore */
+#endif
+    if (IsAtLeastTLSv1_2(ssl)) {
+        #ifdef WOLFSSL_SHA384
+            ssl->hsHashes->hashSha384 = sha384;
+        #endif
+        #ifdef WOLFSSL_SHA512
+            ssl->hsHashes->hashSha512 = sha512;
+        #endif
+    }
+
+    return 0;
+}
+
+#endif /* WOLFSSL_LEANPSK */
+
+/* Build SSL Message, encrypted */
+static int BuildMessage(WOLFSSL* ssl, byte* output, int outSz,
+                        const byte* input, int inSz, int type)
+{
+#ifdef HAVE_TRUNCATED_HMAC
+    word32 digestSz = min(ssl->specs.hash_size,
+                ssl->truncated_hmac ? TRUNCATED_HMAC_SZ : ssl->specs.hash_size);
+#else
+    word32 digestSz = ssl->specs.hash_size;
+#endif
+    word32 sz = RECORD_HEADER_SZ + inSz + digestSz;
+    word32 pad  = 0, i;
+    word32 idx  = RECORD_HEADER_SZ;
+    word32 ivSz = 0;      /* TLSv1.1  IV */
+    word32 headerSz = RECORD_HEADER_SZ;
+    word16 size;
+    byte               iv[AES_BLOCK_SIZE];                  /* max size */
+    int ret        = 0;
+    int atomicUser = 0;
+
+#ifdef WOLFSSL_DTLS
+    if (ssl->options.dtls) {
+        sz       += DTLS_RECORD_EXTRA;
+        idx      += DTLS_RECORD_EXTRA;
+        headerSz += DTLS_RECORD_EXTRA;
+    }
+#endif
+
+#ifdef ATOMIC_USER
+    if (ssl->ctx->MacEncryptCb)
+        atomicUser = 1;
+#endif
+
+    if (ssl->specs.cipher_type == block) {
+        word32 blockSz = ssl->specs.block_size;
+        if (ssl->options.tls1_1) {
+            ivSz = blockSz;
+            sz  += ivSz;
+
+            if (ivSz > (word32)sizeof(iv))
+                return BUFFER_E;
+
+            ret = wc_RNG_GenerateBlock(ssl->rng, iv, ivSz);
+            if (ret != 0)
+                return ret;
+
+        }
+        sz += 1;       /* pad byte */
+        pad = (sz - headerSz) % blockSz;
+        pad = blockSz - pad;
+        sz += pad;
+    }
+
+#ifdef HAVE_AEAD
+    if (ssl->specs.cipher_type == aead) {
+        if (ssl->specs.bulk_cipher_algorithm != wolfssl_chacha)
+            ivSz = AEAD_EXP_IV_SZ;
+
+        sz += (ivSz + ssl->specs.aead_mac_size - digestSz);
+        XMEMCPY(iv, ssl->keys.aead_exp_IV, AEAD_EXP_IV_SZ);
+    }
+#endif
+    if (sz > (word32)outSz) {
+        WOLFSSL_MSG("Oops, want to write past output buffer size");
+        return BUFFER_E;
+    }
+    size = (word16)(sz - headerSz);    /* include mac and digest */
+    AddRecordHeader(output, size, (byte)type, ssl);
+
+    /* write to output */
+    if (ivSz) {
+        XMEMCPY(output + idx, iv, min(ivSz, sizeof(iv)));
+        idx += ivSz;
+    }
+    XMEMCPY(output + idx, input, inSz);
+    idx += inSz;
+
+    if (type == handshake) {
+        ret = HashOutput(ssl, output, headerSz + inSz, ivSz);
+        if (ret != 0)
+            return ret;
+    }
+
+    if (ssl->specs.cipher_type == block) {
+        word32 tmpIdx = idx + digestSz;
+
+        for (i = 0; i <= pad; i++)
+            output[tmpIdx++] = (byte)pad; /* pad byte gets pad value too */
+    }
+
+    if (atomicUser) {   /* User Record Layer Callback handling */
+#ifdef ATOMIC_USER
+        if ( (ret = ssl->ctx->MacEncryptCb(ssl, output + idx,
+                        output + headerSz + ivSz, inSz, type, 0,
+                        output + headerSz, output + headerSz, size,
+                        ssl->MacEncryptCtx)) != 0)
+            return ret;
+#endif
+    }
+    else {
+        if (ssl->specs.cipher_type != aead) {
+#ifdef HAVE_TRUNCATED_HMAC
+            if (ssl->truncated_hmac && ssl->specs.hash_size > digestSz) {
+            #ifdef WOLFSSL_SMALL_STACK
+                byte* hmac = NULL;
+            #else
+                byte  hmac[MAX_DIGEST_SIZE];
+            #endif
+
+            #ifdef WOLFSSL_SMALL_STACK
+                hmac = (byte*)XMALLOC(MAX_DIGEST_SIZE, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+                if (hmac == NULL)
+                    return MEMORY_E;
+            #endif
+
+                ret = ssl->hmac(ssl, hmac, output + headerSz + ivSz, inSz,
+                                                                       type, 0);
+                XMEMCPY(output + idx, hmac, digestSz);
+
+            #ifdef WOLFSSL_SMALL_STACK
+                XFREE(hmac, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            #endif
+            } else
+#endif
+                ret = ssl->hmac(ssl, output+idx, output + headerSz + ivSz, inSz,
+                                                                       type, 0);
+        }
+        if (ret != 0)
+            return ret;
+
+        if ( (ret = Encrypt(ssl, output + headerSz, output+headerSz,size)) != 0)
+            return ret;
+    }
+
+    return sz;
+}
+
+
+int SendFinished(WOLFSSL* ssl)
+{
+    int              sendSz,
+                     finishedSz = ssl->options.tls ? TLS_FINISHED_SZ :
+                                                     FINISHED_SZ;
+    byte             input[FINISHED_SZ + DTLS_HANDSHAKE_HEADER_SZ];  /* max */
+    byte            *output;
+    Hashes*          hashes;
+    int              ret;
+    int              headerSz = HANDSHAKE_HEADER_SZ;
+    int              outputSz;
+
+    #ifdef WOLFSSL_DTLS
+        word32 sequence_number = ssl->keys.dtls_sequence_number;
+        word16 epoch           = ssl->keys.dtls_epoch;
+    #endif
+
+    /* setup encrypt keys */
+    if ((ret = SetKeysSide(ssl, ENCRYPT_SIDE_ONLY)) != 0)
+        return ret;
+
+    /* check for available size */
+    outputSz = sizeof(input) + MAX_MSG_EXTRA;
+    if ((ret = CheckAvailableSize(ssl, outputSz)) != 0)
+        return ret;
+
+    #ifdef WOLFSSL_DTLS
+        if (ssl->options.dtls) {
+            /* Send Finished message with the next epoch, but don't commit that
+             * change until the other end confirms its reception. */
+            headerSz += DTLS_HANDSHAKE_EXTRA;
+            ssl->keys.dtls_epoch++;
+            ssl->keys.dtls_sequence_number = 0;  /* reset after epoch change */
+        }
+    #endif
+
+    /* get ouput buffer */
+    output = ssl->buffers.outputBuffer.buffer +
+             ssl->buffers.outputBuffer.length;
+
+    AddHandShakeHeader(input, finishedSz, finished, ssl);
+
+    /* make finished hashes */
+    hashes = (Hashes*)&input[headerSz];
+    ret = BuildFinished(ssl, hashes,
+                     ssl->options.side == WOLFSSL_CLIENT_END ? client : server);
+    if (ret != 0) return ret;
+
+#ifdef HAVE_SECURE_RENEGOTIATION
+    if (ssl->secure_renegotiation) {
+        if (ssl->options.side == WOLFSSL_CLIENT_END)
+            XMEMCPY(ssl->secure_renegotiation->client_verify_data, hashes,
+                    TLS_FINISHED_SZ);
+        else
+            XMEMCPY(ssl->secure_renegotiation->server_verify_data, hashes,
+                    TLS_FINISHED_SZ);
+    }
+#endif
+
+    sendSz = BuildMessage(ssl, output, outputSz, input, headerSz + finishedSz,
+                          handshake);
+    if (sendSz < 0)
+        return BUILD_MSG_ERROR;
+
+    #ifdef WOLFSSL_DTLS
+    if (ssl->options.dtls) {
+        ssl->keys.dtls_epoch = epoch;
+        ssl->keys.dtls_sequence_number = sequence_number;
+    }
+    #endif
+
+    if (!ssl->options.resuming) {
+#ifndef NO_SESSION_CACHE
+        AddSession(ssl);    /* just try */
+#endif
+        if (ssl->options.side == WOLFSSL_SERVER_END) {
+            ssl->options.handShakeState = HANDSHAKE_DONE;
+            ssl->options.handShakeDone  = 1;
+            #ifdef WOLFSSL_DTLS
+                if (ssl->options.dtls) {
+                    /* Other side will soon receive our Finished, go to next
+                     * epoch. */
+                    ssl->keys.dtls_epoch++;
+                    ssl->keys.dtls_sequence_number = 1;
+                }
+            #endif
+        }
+    }
+    else {
+        if (ssl->options.side == WOLFSSL_CLIENT_END) {
+            ssl->options.handShakeState = HANDSHAKE_DONE;
+            ssl->options.handShakeDone  = 1;
+            #ifdef WOLFSSL_DTLS
+                if (ssl->options.dtls) {
+                    /* Other side will soon receive our Finished, go to next
+                     * epoch. */
+                    ssl->keys.dtls_epoch++;
+                    ssl->keys.dtls_sequence_number = 1;
+                }
+            #endif
+        }
+    }
+    #ifdef WOLFSSL_DTLS
+        if (ssl->options.dtls) {
+            if ((ret = DtlsPoolSave(ssl, output, sendSz)) != 0)
+                return ret;
+        }
+    #endif
+
+    #ifdef WOLFSSL_CALLBACKS
+        if (ssl->hsInfoOn) AddPacketName("Finished", &ssl->handShakeInfo);
+        if (ssl->toInfoOn)
+            AddPacketInfo("Finished", &ssl->timeoutInfo, output, sendSz,
+                          ssl->heap);
+    #endif
+
+    ssl->buffers.outputBuffer.length += sendSz;
+
+    return SendBuffered(ssl);
+}
+
+#ifndef NO_CERTS
+int SendCertificate(WOLFSSL* ssl)
+{
+    int    sendSz, length, ret = 0;
+    word32 i = RECORD_HEADER_SZ + HANDSHAKE_HEADER_SZ;
+    word32 certSz, listSz;
+    byte*  output = 0;
+
+    if (ssl->options.usingPSK_cipher || ssl->options.usingAnon_cipher)
+        return 0;  /* not needed */
+
+    if (ssl->options.sendVerify == SEND_BLANK_CERT) {
+        certSz = 0;
+        length = CERT_HEADER_SZ;
+        listSz = 0;
+    }
+    else {
+        certSz = ssl->buffers.certificate.length;
+        /* list + cert size */
+        length = certSz + 2 * CERT_HEADER_SZ;
+        listSz = certSz + CERT_HEADER_SZ;
+
+        /* may need to send rest of chain, already has leading size(s) */
+        if (ssl->buffers.certChain.buffer) {
+            length += ssl->buffers.certChain.length;
+            listSz += ssl->buffers.certChain.length;
+        }
+    }
+    sendSz = length + RECORD_HEADER_SZ + HANDSHAKE_HEADER_SZ;
+
+    #ifdef WOLFSSL_DTLS
+        if (ssl->options.dtls) {
+            sendSz += DTLS_RECORD_EXTRA + DTLS_HANDSHAKE_EXTRA;
+            i      += DTLS_RECORD_EXTRA + DTLS_HANDSHAKE_EXTRA;
+        }
+    #endif
+
+    if (ssl->keys.encryptionOn)
+        sendSz += MAX_MSG_EXTRA;
+
+    /* check for available size */
+    if ((ret = CheckAvailableSize(ssl, sendSz)) != 0)
+        return ret;
+
+    /* get ouput buffer */
+    output = ssl->buffers.outputBuffer.buffer +
+             ssl->buffers.outputBuffer.length;
+
+    AddHeaders(output, length, certificate, ssl);
+
+    /* list total */
+    c32to24(listSz, output + i);
+    i += CERT_HEADER_SZ;
+
+    /* member */
+    if (certSz) {
+        c32to24(certSz, output + i);
+        i += CERT_HEADER_SZ;
+        XMEMCPY(output + i, ssl->buffers.certificate.buffer, certSz);
+        i += certSz;
+
+        /* send rest of chain? */
+        if (ssl->buffers.certChain.buffer) {
+            XMEMCPY(output + i, ssl->buffers.certChain.buffer,
+                                ssl->buffers.certChain.length);
+            i += ssl->buffers.certChain.length;
+        }
+    }
+
+    if (ssl->keys.encryptionOn) {
+        byte* input;
+        int   inputSz = i - RECORD_HEADER_SZ; /* build msg adds rec hdr */
+
+        input = (byte*)XMALLOC(inputSz, ssl->heap, DYNAMIC_TYPE_TMP_BUFFER);
+        if (input == NULL)
+            return MEMORY_E;
+
+        XMEMCPY(input, output + RECORD_HEADER_SZ, inputSz);
+        sendSz = BuildMessage(ssl, output, sendSz, input,inputSz,handshake);
+        XFREE(input, ssl->heap, DYNAMIC_TYPE_TMP_BUFFER);
+
+        if (sendSz < 0)
+            return sendSz;
+    } else {
+        ret = HashOutput(ssl, output, sendSz, 0);
+        if (ret != 0)
+            return ret;
+    }
+
+    #ifdef WOLFSSL_DTLS
+        if (ssl->options.dtls) {
+            if ((ret = DtlsPoolSave(ssl, output, sendSz)) != 0)
+                return ret;
+        }
+    #endif
+
+    #ifdef WOLFSSL_CALLBACKS
+        if (ssl->hsInfoOn) AddPacketName("Certificate", &ssl->handShakeInfo);
+        if (ssl->toInfoOn)
+            AddPacketInfo("Certificate", &ssl->timeoutInfo, output, sendSz,
+                           ssl->heap);
+    #endif
+
+    if (ssl->options.side == WOLFSSL_SERVER_END)
+        ssl->options.serverState = SERVER_CERT_COMPLETE;
+
+    ssl->buffers.outputBuffer.length += sendSz;
+    if (ssl->options.groupMessages)
+        return 0;
+    else
+        return SendBuffered(ssl);
+}
+
+
+int SendCertificateRequest(WOLFSSL* ssl)
+{
+    byte   *output;
+    int    ret;
+    int    sendSz;
+    word32 i = RECORD_HEADER_SZ + HANDSHAKE_HEADER_SZ;
+
+    int  typeTotal = 1;  /* only 1 for now */
+    int  reqSz = ENUM_LEN + typeTotal + REQ_HEADER_SZ;  /* add auth later */
+
+    if (IsAtLeastTLSv1_2(ssl))
+        reqSz += LENGTH_SZ + ssl->suites->hashSigAlgoSz;
+
+    if (ssl->options.usingPSK_cipher || ssl->options.usingAnon_cipher)
+        return 0;  /* not needed */
+
+    sendSz = RECORD_HEADER_SZ + HANDSHAKE_HEADER_SZ + reqSz;
+
+    #ifdef WOLFSSL_DTLS
+        if (ssl->options.dtls) {
+            sendSz += DTLS_RECORD_EXTRA + DTLS_HANDSHAKE_EXTRA;
+            i      += DTLS_RECORD_EXTRA + DTLS_HANDSHAKE_EXTRA;
+        }
+    #endif
+    /* check for available size */
+    if ((ret = CheckAvailableSize(ssl, sendSz)) != 0)
+        return ret;
+
+    /* get ouput buffer */
+    output = ssl->buffers.outputBuffer.buffer +
+             ssl->buffers.outputBuffer.length;
+
+    AddHeaders(output, reqSz, certificate_request, ssl);
+
+    /* write to output */
+    output[i++] = (byte)typeTotal;  /* # of types */
+#ifdef HAVE_ECC
+    if (ssl->options.cipherSuite0 == ECC_BYTE &&
+                     ssl->specs.sig_algo == ecc_dsa_sa_algo) {
+        output[i++] = ecdsa_sign;
+    } else
+#endif /* HAVE_ECC */
+    {
+        output[i++] = rsa_sign;
+    }
+
+    /* supported hash/sig */
+    if (IsAtLeastTLSv1_2(ssl)) {
+        c16toa(ssl->suites->hashSigAlgoSz, &output[i]);
+        i += LENGTH_SZ;
+
+        XMEMCPY(&output[i],
+                         ssl->suites->hashSigAlgo, ssl->suites->hashSigAlgoSz);
+        i += ssl->suites->hashSigAlgoSz;
+    }
+
+    c16toa(0, &output[i]);  /* auth's */
+    /* if add more to output, adjust i
+    i += REQ_HEADER_SZ; */
+
+    #ifdef WOLFSSL_DTLS
+        if (ssl->options.dtls) {
+            if ((ret = DtlsPoolSave(ssl, output, sendSz)) != 0)
+                return ret;
+        }
+    #endif
+
+    ret = HashOutput(ssl, output, sendSz, 0);
+    if (ret != 0)
+        return ret;
+
+    #ifdef WOLFSSL_CALLBACKS
+        if (ssl->hsInfoOn)
+            AddPacketName("CertificateRequest", &ssl->handShakeInfo);
+        if (ssl->toInfoOn)
+            AddPacketInfo("CertificateRequest", &ssl->timeoutInfo, output,
+                          sendSz, ssl->heap);
+    #endif
+    ssl->buffers.outputBuffer.length += sendSz;
+    if (ssl->options.groupMessages)
+        return 0;
+    else
+        return SendBuffered(ssl);
+}
+#endif /* !NO_CERTS */
+
+
+int SendData(WOLFSSL* ssl, const void* data, int sz)
+{
+    int sent = 0,  /* plainText size */
+        sendSz,
+        ret,
+        dtlsExtra = 0;
+
+    if (ssl->error == WANT_WRITE)
+        ssl->error = 0;
+
+    if (ssl->options.handShakeState != HANDSHAKE_DONE) {
+        int err;
+        WOLFSSL_MSG("handshake not complete, trying to finish");
+        if ( (err = wolfSSL_negotiate(ssl)) != SSL_SUCCESS)
+            return  err;
+    }
+
+    /* last time system socket output buffer was full, try again to send */
+    if (ssl->buffers.outputBuffer.length > 0) {
+        WOLFSSL_MSG("output buffer was full, trying to send again");
+        if ( (ssl->error = SendBuffered(ssl)) < 0) {
+            WOLFSSL_ERROR(ssl->error);
+            if (ssl->error == SOCKET_ERROR_E && ssl->options.connReset)
+                return 0;     /* peer reset */
+            return ssl->error;
+        }
+        else {
+            /* advance sent to previous sent + plain size just sent */
+            sent = ssl->buffers.prevSent + ssl->buffers.plainSz;
+            WOLFSSL_MSG("sent write buffered data");
+
+            if (sent > sz) {
+                WOLFSSL_MSG("error: write() after WANT_WRITE with short size");
+                return ssl->error = BAD_FUNC_ARG;
+            }
+        }
+    }
+
+#ifdef WOLFSSL_DTLS
+    if (ssl->options.dtls) {
+        dtlsExtra = DTLS_RECORD_EXTRA;
+    }
+#endif
+
+    for (;;) {
+#ifdef HAVE_MAX_FRAGMENT
+        int   len = min(sz - sent, min(ssl->max_fragment, OUTPUT_RECORD_SIZE));
+#else
+        int   len = min(sz - sent, OUTPUT_RECORD_SIZE);
+#endif
+        byte* out;
+        byte* sendBuffer = (byte*)data + sent;  /* may switch on comp */
+        int   buffSz = len;                     /* may switch on comp */
+        int   outputSz;
+#ifdef HAVE_LIBZ
+        byte  comp[MAX_RECORD_SIZE + MAX_COMP_EXTRA];
+#endif
+
+        if (sent == sz) break;
+
+#ifdef WOLFSSL_DTLS
+        if (ssl->options.dtls) {
+            len    = min(len, MAX_UDP_SIZE);
+            buffSz = len;
+        }
+#endif
+
+        /* check for available size */
+        outputSz = len + COMP_EXTRA + dtlsExtra + MAX_MSG_EXTRA;
+        if ((ret = CheckAvailableSize(ssl, outputSz)) != 0)
+            return ssl->error = ret;
+
+        /* get ouput buffer */
+        out = ssl->buffers.outputBuffer.buffer +
+              ssl->buffers.outputBuffer.length;
+
+#ifdef HAVE_LIBZ
+        if (ssl->options.usingCompression) {
+            buffSz = myCompress(ssl, sendBuffer, buffSz, comp, sizeof(comp));
+            if (buffSz < 0) {
+                return buffSz;
+            }
+            sendBuffer = comp;
+        }
+#endif
+        sendSz = BuildMessage(ssl, out, outputSz, sendBuffer, buffSz,
+                              application_data);
+        if (sendSz < 0)
+            return BUILD_MSG_ERROR;
+
+        ssl->buffers.outputBuffer.length += sendSz;
+
+        if ( (ret = SendBuffered(ssl)) < 0) {
+            WOLFSSL_ERROR(ret);
+            /* store for next call if WANT_WRITE or user embedSend() that
+               doesn't present like WANT_WRITE */
+            ssl->buffers.plainSz  = len;
+            ssl->buffers.prevSent = sent;
+            if (ret == SOCKET_ERROR_E && ssl->options.connReset)
+                return 0;  /* peer reset */
+            return ssl->error = ret;
+        }
+
+        sent += len;
+
+        /* only one message per attempt */
+        if (ssl->options.partialWrite == 1) {
+            WOLFSSL_MSG("Paritial Write on, only sending one record");
+            break;
+        }
+    }
+
+    return sent;
+}
+
+/* process input data */
+int ReceiveData(WOLFSSL* ssl, byte* output, int sz, int peek)
+{
+    int size;
+
+    WOLFSSL_ENTER("ReceiveData()");
+
+    if (ssl->error == WANT_READ)
+        ssl->error = 0;
+
+    if (ssl->error != 0 && ssl->error != WANT_WRITE) {
+        WOLFSSL_MSG("User calling wolfSSL_read in error state, not allowed");
+        return ssl->error;
+    }
+
+    if (ssl->options.handShakeState != HANDSHAKE_DONE) {
+        int err;
+        WOLFSSL_MSG("Handshake not complete, trying to finish");
+        if ( (err = wolfSSL_negotiate(ssl)) != SSL_SUCCESS)
+            return  err;
+    }
+
+#ifdef HAVE_SECURE_RENEGOTIATION
+startScr:
+    if (ssl->secure_renegotiation && ssl->secure_renegotiation->startScr) {
+        int err;
+        ssl->secure_renegotiation->startScr = 0;  /* only start once */
+        WOLFSSL_MSG("Need to start scr, server requested");
+        if ( (err = wolfSSL_Rehandshake(ssl)) != SSL_SUCCESS)
+            return  err;
+    }
+#endif
+
+    while (ssl->buffers.clearOutputBuffer.length == 0) {
+        if ( (ssl->error = ProcessReply(ssl)) < 0) {
+            WOLFSSL_ERROR(ssl->error);
+            if (ssl->error == ZERO_RETURN) {
+                WOLFSSL_MSG("Zero return, no more data coming");
+                return 0;         /* no more data coming */
+            }
+            if (ssl->error == SOCKET_ERROR_E) {
+                if (ssl->options.connReset || ssl->options.isClosed) {
+                    WOLFSSL_MSG("Peer reset or closed, connection done");
+                    ssl->error = SOCKET_PEER_CLOSED_E;
+                    WOLFSSL_ERROR(ssl->error);
+                    return 0;     /* peer reset or closed */
+                }
+            }
+            return ssl->error;
+        }
+        #ifdef HAVE_SECURE_RENEGOTIATION
+            if (ssl->secure_renegotiation &&
+                ssl->secure_renegotiation->startScr) {
+                goto startScr;
+            }
+        #endif
+    }
+
+    if (sz < (int)ssl->buffers.clearOutputBuffer.length)
+        size = sz;
+    else
+        size = ssl->buffers.clearOutputBuffer.length;
+
+    XMEMCPY(output, ssl->buffers.clearOutputBuffer.buffer, size);
+
+    if (peek == 0) {
+        ssl->buffers.clearOutputBuffer.length -= size;
+        ssl->buffers.clearOutputBuffer.buffer += size;
+    }
+
+    if (ssl->buffers.clearOutputBuffer.length == 0 &&
+                                           ssl->buffers.inputBuffer.dynamicFlag)
+       ShrinkInputBuffer(ssl, NO_FORCED_FREE);
+
+    WOLFSSL_LEAVE("ReceiveData()", size);
+    return size;
+}
+
+
+/* send alert message */
+int SendAlert(WOLFSSL* ssl, int severity, int type)
+{
+    byte input[ALERT_SIZE];
+    byte *output;
+    int  sendSz;
+    int  ret;
+    int  outputSz;
+    int  dtlsExtra = 0;
+
+    /* if sendalert is called again for nonbloking */
+    if (ssl->options.sendAlertState != 0) {
+        ret = SendBuffered(ssl);
+        if (ret == 0)
+            ssl->options.sendAlertState = 0;
+        return ret;
+    }
+
+   #ifdef WOLFSSL_DTLS
+        if (ssl->options.dtls)
+           dtlsExtra = DTLS_RECORD_EXTRA;
+   #endif
+
+    /* check for available size */
+    outputSz = ALERT_SIZE + MAX_MSG_EXTRA + dtlsExtra;
+    if ((ret = CheckAvailableSize(ssl, outputSz)) != 0)
+        return ret;
+
+    /* get ouput buffer */
+    output = ssl->buffers.outputBuffer.buffer +
+             ssl->buffers.outputBuffer.length;
+
+    input[0] = (byte)severity;
+    input[1] = (byte)type;
+    ssl->alert_history.last_tx.code = type;
+    ssl->alert_history.last_tx.level = severity;
+    if (severity == alert_fatal) {
+        ssl->options.isClosed = 1;  /* Don't send close_notify */
+    }
+
+    /* only send encrypted alert if handshake actually complete, otherwise
+       other side may not be able to handle it */
+    if (ssl->keys.encryptionOn && ssl->options.handShakeDone)
+        sendSz = BuildMessage(ssl, output, outputSz, input, ALERT_SIZE, alert);
+    else {
+
+        AddRecordHeader(output, ALERT_SIZE, alert, ssl);
+        output += RECORD_HEADER_SZ;
+        #ifdef WOLFSSL_DTLS
+            if (ssl->options.dtls)
+                output += DTLS_RECORD_EXTRA;
+        #endif
+        XMEMCPY(output, input, ALERT_SIZE);
+
+        sendSz = RECORD_HEADER_SZ + ALERT_SIZE;
+        #ifdef WOLFSSL_DTLS
+            if (ssl->options.dtls)
+                sendSz += DTLS_RECORD_EXTRA;
+        #endif
+    }
+    if (sendSz < 0)
+        return BUILD_MSG_ERROR;
+
+    #ifdef WOLFSSL_CALLBACKS
+        if (ssl->hsInfoOn)
+            AddPacketName("Alert", &ssl->handShakeInfo);
+        if (ssl->toInfoOn)
+            AddPacketInfo("Alert", &ssl->timeoutInfo, output, sendSz,ssl->heap);
+    #endif
+
+    ssl->buffers.outputBuffer.length += sendSz;
+    ssl->options.sendAlertState = 1;
+
+    return SendBuffered(ssl);
+}
+
+const char* wolfSSL_ERR_reason_error_string(unsigned long e)
+{
+#ifdef NO_ERROR_STRINGS
+
+    (void)e;
+    return "no support for error strings built in";
+
+#else
+
+    int error = (int)e;
+
+    /* pass to wolfCrypt */
+    if (error < MAX_CODE_E && error > MIN_CODE_E) {
+        return wc_GetErrorString(error);
+    }
+
+    switch (error) {
+
+    case UNSUPPORTED_SUITE :
+        return "unsupported cipher suite";
+
+    case INPUT_CASE_ERROR :
+        return "input state error";
+
+    case PREFIX_ERROR :
+        return "bad index to key rounds";
+
+    case MEMORY_ERROR :
+        return "out of memory";
+
+    case VERIFY_FINISHED_ERROR :
+        return "verify problem on finished";
+
+    case VERIFY_MAC_ERROR :
+        return "verify mac problem";
+
+    case PARSE_ERROR :
+        return "parse error on header";
+
+    case SIDE_ERROR :
+        return "wrong client/server type";
+
+    case NO_PEER_CERT :
+        return "peer didn't send cert";
+
+    case UNKNOWN_HANDSHAKE_TYPE :
+        return "weird handshake type";
+
+    case SOCKET_ERROR_E :
+        return "error state on socket";
+
+    case SOCKET_NODATA :
+        return "expected data, not there";
+
+    case INCOMPLETE_DATA :
+        return "don't have enough data to complete task";
+
+    case UNKNOWN_RECORD_TYPE :
+        return "unknown type in record hdr";
+
+    case DECRYPT_ERROR :
+        return "error during decryption";
+
+    case FATAL_ERROR :
+        return "revcd alert fatal error";
+
+    case ENCRYPT_ERROR :
+        return "error during encryption";
+
+    case FREAD_ERROR :
+        return "fread problem";
+
+    case NO_PEER_KEY :
+        return "need peer's key";
+
+    case NO_PRIVATE_KEY :
+        return "need the private key";
+
+    case NO_DH_PARAMS :
+        return "server missing DH params";
+
+    case RSA_PRIVATE_ERROR :
+        return "error during rsa priv op";
+
+    case MATCH_SUITE_ERROR :
+        return "can't match cipher suite";
+
+    case BUILD_MSG_ERROR :
+        return "build message failure";
+
+    case BAD_HELLO :
+        return "client hello malformed";
+
+    case DOMAIN_NAME_MISMATCH :
+        return "peer subject name mismatch";
+
+    case WANT_READ :
+    case SSL_ERROR_WANT_READ :
+        return "non-blocking socket wants data to be read";
+
+    case NOT_READY_ERROR :
+        return "handshake layer not ready yet, complete first";
+
+    case PMS_VERSION_ERROR :
+        return "premaster secret version mismatch error";
+
+    case VERSION_ERROR :
+        return "record layer version error";
+
+    case WANT_WRITE :
+    case SSL_ERROR_WANT_WRITE :
+        return "non-blocking socket write buffer full";
+
+    case BUFFER_ERROR :
+        return "malformed buffer input error";
+
+    case VERIFY_CERT_ERROR :
+        return "verify problem on certificate";
+
+    case VERIFY_SIGN_ERROR :
+        return "verify problem based on signature";
+
+    case CLIENT_ID_ERROR :
+        return "psk client identity error";
+
+    case SERVER_HINT_ERROR:
+        return "psk server hint error";
+
+    case PSK_KEY_ERROR:
+        return "psk key callback error";
+
+    case NTRU_KEY_ERROR:
+        return "NTRU key error";
+
+    case NTRU_DRBG_ERROR:
+        return "NTRU drbg error";
+
+    case NTRU_ENCRYPT_ERROR:
+        return "NTRU encrypt error";
+
+    case NTRU_DECRYPT_ERROR:
+        return "NTRU decrypt error";
+
+    case ZLIB_INIT_ERROR:
+        return "zlib init error";
+
+    case ZLIB_COMPRESS_ERROR:
+        return "zlib compress error";
+
+    case ZLIB_DECOMPRESS_ERROR:
+        return "zlib decompress error";
+
+    case GETTIME_ERROR:
+        return "gettimeofday() error";
+
+    case GETITIMER_ERROR:
+        return "getitimer() error";
+
+    case SIGACT_ERROR:
+        return "sigaction() error";
+
+    case SETITIMER_ERROR:
+        return "setitimer() error";
+
+    case LENGTH_ERROR:
+        return "record layer length error";
+
+    case PEER_KEY_ERROR:
+        return "cant decode peer key";
+
+    case ZERO_RETURN:
+    case SSL_ERROR_ZERO_RETURN:
+        return "peer sent close notify alert";
+
+    case ECC_CURVETYPE_ERROR:
+        return "Bad ECC Curve Type or unsupported";
+
+    case ECC_CURVE_ERROR:
+        return "Bad ECC Curve or unsupported";
+
+    case ECC_PEERKEY_ERROR:
+        return "Bad ECC Peer Key";
+
+    case ECC_MAKEKEY_ERROR:
+        return "ECC Make Key failure";
+
+    case ECC_EXPORT_ERROR:
+        return "ECC Export Key failure";
+
+    case ECC_SHARED_ERROR:
+        return "ECC DHE shared failure";
+
+    case NOT_CA_ERROR:
+        return "Not a CA by basic constraint error";
+
+    case BAD_PATH_ERROR:
+        return "Bad path for opendir error";
+
+    case BAD_CERT_MANAGER_ERROR:
+        return "Bad Cert Manager error";
+
+    case OCSP_CERT_REVOKED:
+        return "OCSP Cert revoked";
+
+    case CRL_CERT_REVOKED:
+        return "CRL Cert revoked";
+
+    case CRL_MISSING:
+        return "CRL missing, not loaded";
+
+    case MONITOR_RUNNING_E:
+        return "CRL monitor already running";
+
+    case THREAD_CREATE_E:
+        return "Thread creation problem";
+
+    case OCSP_NEED_URL:
+        return "OCSP need URL";
+
+    case OCSP_CERT_UNKNOWN:
+        return "OCSP Cert unknown";
+
+    case OCSP_LOOKUP_FAIL:
+        return "OCSP Responder lookup fail";
+
+    case MAX_CHAIN_ERROR:
+        return "Maximum Chain Depth Exceeded";
+
+    case COOKIE_ERROR:
+        return "DTLS Cookie Error";
+
+    case SEQUENCE_ERROR:
+        return "DTLS Sequence Error";
+
+    case SUITES_ERROR:
+        return "Suites Pointer Error";
+
+    case SSL_NO_PEM_HEADER:
+        return "No PEM Header Error";
+
+    case OUT_OF_ORDER_E:
+        return "Out of order message, fatal";
+
+    case BAD_KEA_TYPE_E:
+        return "Bad KEA type found";
+
+    case SANITY_CIPHER_E:
+        return "Sanity check on ciphertext failed";
+
+    case RECV_OVERFLOW_E:
+        return "Receive callback returned more than requested";
+
+    case GEN_COOKIE_E:
+        return "Generate Cookie Error";
+
+    case NO_PEER_VERIFY:
+        return "Need peer certificate verify Error";
+
+    case FWRITE_ERROR:
+        return "fwrite Error";
+
+    case CACHE_MATCH_ERROR:
+        return "Cache restore header match Error";
+
+    case UNKNOWN_SNI_HOST_NAME_E:
+        return "Unrecognized host name Error";
+
+    case KEYUSE_SIGNATURE_E:
+        return "Key Use digitalSignature not set Error";
+
+    case KEYUSE_ENCIPHER_E:
+        return "Key Use keyEncipherment not set Error";
+
+    case EXTKEYUSE_AUTH_E:
+        return "Ext Key Use server/client auth not set Error";
+
+    case SEND_OOB_READ_E:
+        return "Send Callback Out of Bounds Read Error";
+
+    case SECURE_RENEGOTIATION_E:
+        return "Invalid Renegotiation Error";
+
+    case SESSION_TICKET_LEN_E:
+        return "Session Ticket Too Long Error";
+
+    case SESSION_TICKET_EXPECT_E:
+        return "Session Ticket Error";
+
+    case SCR_DIFFERENT_CERT_E:
+        return "Peer sent different cert during SCR";
+
+    case SESSION_SECRET_CB_E:
+        return "Session Secret Callback Error";
+
+    case NO_CHANGE_CIPHER_E:
+        return "Finished received from peer before Change Cipher Error";
+
+    case SANITY_MSG_E:
+        return "Sanity Check on message order Error";
+
+    case DUPLICATE_MSG_E:
+        return "Duplicate HandShake message Error";
+
+    case SNI_UNSUPPORTED:
+        return "Protocol version does not support SNI Error";
+
+    case SOCKET_PEER_CLOSED_E:
+        return "Peer closed underlying transport Error";
+
+    case BAD_TICKET_KEY_CB_SZ:
+        return "Bad user session ticket key callback Size Error";
+
+    case BAD_TICKET_MSG_SZ:
+        return "Bad session ticket message Size Error";
+
+    case BAD_TICKET_ENCRYPT:
+        return "Bad user ticket callback encrypt Error";
+
+    case DH_KEY_SIZE_E:
+        return "DH key too small Error";
+
+    default :
+        return "unknown error number";
+    }
+
+#endif /* NO_ERROR_STRINGS */
+}
+
+void SetErrorString(int error, char* str)
+{
+    XSTRNCPY(str, wolfSSL_ERR_reason_error_string(error), WOLFSSL_MAX_ERROR_SZ);
+}
+
+
+/* be sure to add to cipher_name_idx too !!!! */
+static const char* const cipher_names[] =
+{
+#ifdef BUILD_SSL_RSA_WITH_RC4_128_SHA
+    "RC4-SHA",
+#endif
+
+#ifdef BUILD_SSL_RSA_WITH_RC4_128_MD5
+    "RC4-MD5",
+#endif
+
+#ifdef BUILD_SSL_RSA_WITH_3DES_EDE_CBC_SHA
+    "DES-CBC3-SHA",
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_128_CBC_SHA
+    "AES128-SHA",
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_256_CBC_SHA
+    "AES256-SHA",
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_NULL_SHA
+    "NULL-SHA",
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_NULL_SHA256
+    "NULL-SHA256",
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_128_CBC_SHA
+    "DHE-RSA-AES128-SHA",
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
+    "DHE-RSA-AES256-SHA",
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384
+    "DHE-PSK-AES256-GCM-SHA384",
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256
+    "DHE-PSK-AES128-GCM-SHA256",
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_256_GCM_SHA384
+    "PSK-AES256-GCM-SHA384",
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_128_GCM_SHA256
+    "PSK-AES128-GCM-SHA256",
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384
+    "DHE-PSK-AES256-CBC-SHA384",
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256
+    "DHE-PSK-AES128-CBC-SHA256",
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_256_CBC_SHA384
+    "PSK-AES256-CBC-SHA384",
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_128_CBC_SHA256
+    "PSK-AES128-CBC-SHA256",
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_128_CBC_SHA
+    "PSK-AES128-CBC-SHA",
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_256_CBC_SHA
+    "PSK-AES256-CBC-SHA",
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_128_CCM
+    "DHE-PSK-AES128-CCM",
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_256_CCM
+    "DHE-PSK-AES256-CCM",
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_128_CCM
+    "PSK-AES128-CCM",
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_256_CCM
+    "PSK-AES256-CCM",
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_128_CCM_8
+    "PSK-AES128-CCM-8",
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_256_CCM_8
+    "PSK-AES256-CCM-8",
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_NULL_SHA384
+    "DHE-PSK-NULL-SHA384",
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_NULL_SHA256
+    "DHE-PSK-NULL-SHA256",
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_NULL_SHA384
+    "PSK-NULL-SHA384",
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_NULL_SHA256
+    "PSK-NULL-SHA256",
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_NULL_SHA
+    "PSK-NULL-SHA",
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_HC_128_MD5
+    "HC128-MD5",
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_HC_128_SHA
+    "HC128-SHA",
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_HC_128_B2B256
+    "HC128-B2B256",
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_128_CBC_B2B256
+    "AES128-B2B256",
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_256_CBC_B2B256
+    "AES256-B2B256",
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_RABBIT_SHA
+    "RABBIT-SHA",
+#endif
+
+#ifdef BUILD_TLS_NTRU_RSA_WITH_RC4_128_SHA
+    "NTRU-RC4-SHA",
+#endif
+
+#ifdef BUILD_TLS_NTRU_RSA_WITH_3DES_EDE_CBC_SHA
+    "NTRU-DES-CBC3-SHA",
+#endif
+
+#ifdef BUILD_TLS_NTRU_RSA_WITH_AES_128_CBC_SHA
+    "NTRU-AES128-SHA",
+#endif
+
+#ifdef BUILD_TLS_NTRU_RSA_WITH_AES_256_CBC_SHA
+    "NTRU-AES256-SHA",
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_128_CCM_8
+    "AES128-CCM-8",
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_256_CCM_8
+    "AES256-CCM-8",
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8
+    "ECDHE-ECDSA-AES128-CCM-8",
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8
+    "ECDHE-ECDSA-AES256-CCM-8",
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA
+    "ECDHE-RSA-AES128-SHA",
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
+    "ECDHE-RSA-AES256-SHA",
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
+    "ECDHE-ECDSA-AES128-SHA",
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
+    "ECDHE-ECDSA-AES256-SHA",
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_RC4_128_SHA
+    "ECDHE-RSA-RC4-SHA",
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA
+    "ECDHE-RSA-DES-CBC3-SHA",
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA
+    "ECDHE-ECDSA-RC4-SHA",
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA
+    "ECDHE-ECDSA-DES-CBC3-SHA",
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_128_CBC_SHA256
+    "AES128-SHA256",
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_256_CBC_SHA256
+    "AES256-SHA256",
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256
+    "DHE-RSA-AES128-SHA256",
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
+    "DHE-RSA-AES256-SHA256",
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA
+    "ECDH-RSA-AES128-SHA",
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA
+    "ECDH-RSA-AES256-SHA",
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA
+    "ECDH-ECDSA-AES128-SHA",
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA
+    "ECDH-ECDSA-AES256-SHA",
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_RC4_128_SHA
+    "ECDH-RSA-RC4-SHA",
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA
+    "ECDH-RSA-DES-CBC3-SHA",
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_RC4_128_SHA
+    "ECDH-ECDSA-RC4-SHA",
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA
+    "ECDH-ECDSA-DES-CBC3-SHA",
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_128_GCM_SHA256
+    "AES128-GCM-SHA256",
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_256_GCM_SHA384
+    "AES256-GCM-SHA384",
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
+    "DHE-RSA-AES128-GCM-SHA256",
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
+    "DHE-RSA-AES256-GCM-SHA384",
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
+    "ECDHE-RSA-AES128-GCM-SHA256",
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
+    "ECDHE-RSA-AES256-GCM-SHA384",
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
+    "ECDHE-ECDSA-AES128-GCM-SHA256",
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
+    "ECDHE-ECDSA-AES256-GCM-SHA384",
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256
+    "ECDH-RSA-AES128-GCM-SHA256",
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384
+    "ECDH-RSA-AES256-GCM-SHA384",
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256
+    "ECDH-ECDSA-AES128-GCM-SHA256",
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384
+    "ECDH-ECDSA-AES256-GCM-SHA384",
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA
+    "CAMELLIA128-SHA",
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA
+    "DHE-RSA-CAMELLIA128-SHA",
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA
+    "CAMELLIA256-SHA",
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA
+    "DHE-RSA-CAMELLIA256-SHA",
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256
+    "CAMELLIA128-SHA256",
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+    "DHE-RSA-CAMELLIA128-SHA256",
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256
+    "CAMELLIA256-SHA256",
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256
+    "DHE-RSA-CAMELLIA256-SHA256",
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
+    "ECDHE-RSA-AES128-SHA256",
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
+    "ECDHE-ECDSA-AES128-SHA256",
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256
+    "ECDH-RSA-AES128-SHA256",
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256
+    "ECDH-ECDSA-AES128-SHA256",
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384
+    "ECDHE-RSA-AES256-SHA384",
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384
+    "ECDHE-ECDSA-AES256-SHA384",
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384
+    "ECDH-RSA-AES256-SHA384",
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384
+    "ECDH-ECDSA-AES256-SHA384",
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256
+    "ECDHE-RSA-CHACHA20-POLY1305",
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256
+    "ECDHE-ECDSA-CHACHA20-POLY1305",
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256
+    "DHE-RSA-CHACHA20-POLY1305",
+#endif
+
+#ifdef BUILD_TLS_DH_anon_WITH_AES_128_CBC_SHA
+    "ADH-AES128-SHA",
+#endif
+
+#ifdef HAVE_RENEGOTIATION_INDICATION
+    "RENEGOTIATION-INFO",
+#endif
+};
+
+
+/* cipher suite number that matches above name table */
+static int cipher_name_idx[] =
+{
+
+#ifdef BUILD_SSL_RSA_WITH_RC4_128_SHA
+    SSL_RSA_WITH_RC4_128_SHA,
+#endif
+
+#ifdef BUILD_SSL_RSA_WITH_RC4_128_MD5
+    SSL_RSA_WITH_RC4_128_MD5,
+#endif
+
+#ifdef BUILD_SSL_RSA_WITH_3DES_EDE_CBC_SHA
+    SSL_RSA_WITH_3DES_EDE_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_128_CBC_SHA
+    TLS_RSA_WITH_AES_128_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_256_CBC_SHA
+    TLS_RSA_WITH_AES_256_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_NULL_SHA
+    TLS_RSA_WITH_NULL_SHA,
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_NULL_SHA256
+    TLS_RSA_WITH_NULL_SHA256,
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_128_CBC_SHA
+    TLS_DHE_RSA_WITH_AES_128_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
+    TLS_DHE_RSA_WITH_AES_256_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384
+    TLS_DHE_PSK_WITH_AES_256_GCM_SHA384,
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256
+    TLS_DHE_PSK_WITH_AES_128_GCM_SHA256,
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_256_GCM_SHA384
+    TLS_PSK_WITH_AES_256_GCM_SHA384,
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_128_GCM_SHA256
+    TLS_PSK_WITH_AES_128_GCM_SHA256,
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384
+    TLS_DHE_PSK_WITH_AES_256_CBC_SHA384,
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256
+    TLS_DHE_PSK_WITH_AES_128_CBC_SHA256,
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_256_CBC_SHA384
+    TLS_PSK_WITH_AES_256_CBC_SHA384,
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_128_CBC_SHA256
+    TLS_PSK_WITH_AES_128_CBC_SHA256,
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_128_CBC_SHA
+    TLS_PSK_WITH_AES_128_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_256_CBC_SHA
+    TLS_PSK_WITH_AES_256_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_128_CCM
+    TLS_DHE_PSK_WITH_AES_128_CCM,
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_256_CCM
+    TLS_DHE_PSK_WITH_AES_256_CCM,
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_128_CCM
+    TLS_PSK_WITH_AES_128_CCM,
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_256_CCM
+    TLS_PSK_WITH_AES_256_CCM,
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_128_CCM_8
+    TLS_PSK_WITH_AES_128_CCM_8,
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_256_CCM_8
+    TLS_PSK_WITH_AES_256_CCM_8,
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_NULL_SHA384
+    TLS_DHE_PSK_WITH_NULL_SHA384,
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_NULL_SHA256
+    TLS_DHE_PSK_WITH_NULL_SHA256,
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_NULL_SHA384
+    TLS_PSK_WITH_NULL_SHA384,
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_NULL_SHA256
+    TLS_PSK_WITH_NULL_SHA256,
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_NULL_SHA
+    TLS_PSK_WITH_NULL_SHA,
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_HC_128_MD5
+    TLS_RSA_WITH_HC_128_MD5,
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_HC_128_SHA
+    TLS_RSA_WITH_HC_128_SHA,
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_HC_128_B2B256
+    TLS_RSA_WITH_HC_128_B2B256,
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_128_CBC_B2B256
+    TLS_RSA_WITH_AES_128_CBC_B2B256,
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_256_CBC_B2B256
+    TLS_RSA_WITH_AES_256_CBC_B2B256,
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_RABBIT_SHA
+    TLS_RSA_WITH_RABBIT_SHA,
+#endif
+
+#ifdef BUILD_TLS_NTRU_RSA_WITH_RC4_128_SHA
+    TLS_NTRU_RSA_WITH_RC4_128_SHA,
+#endif
+
+#ifdef BUILD_TLS_NTRU_RSA_WITH_3DES_EDE_CBC_SHA
+    TLS_NTRU_RSA_WITH_3DES_EDE_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_NTRU_RSA_WITH_AES_128_CBC_SHA
+    TLS_NTRU_RSA_WITH_AES_128_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_NTRU_RSA_WITH_AES_256_CBC_SHA
+    TLS_NTRU_RSA_WITH_AES_256_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_128_CCM_8
+    TLS_RSA_WITH_AES_128_CCM_8,
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_256_CCM_8
+    TLS_RSA_WITH_AES_256_CCM_8,
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8
+    TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8,
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8
+    TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8,
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA
+    TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
+    TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
+    TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
+    TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_RC4_128_SHA
+    TLS_ECDHE_RSA_WITH_RC4_128_SHA,
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA
+    TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA
+    TLS_ECDHE_ECDSA_WITH_RC4_128_SHA,
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA
+    TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_128_CBC_SHA256
+    TLS_RSA_WITH_AES_128_CBC_SHA256,
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_256_CBC_SHA256
+    TLS_RSA_WITH_AES_256_CBC_SHA256,
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256
+    TLS_DHE_RSA_WITH_AES_128_CBC_SHA256,
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
+    TLS_DHE_RSA_WITH_AES_256_CBC_SHA256,
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA
+    TLS_ECDH_RSA_WITH_AES_128_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA
+    TLS_ECDH_RSA_WITH_AES_256_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA
+    TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA
+    TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_RC4_128_SHA
+    TLS_ECDH_RSA_WITH_RC4_128_SHA,
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA
+    TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_RC4_128_SHA
+    TLS_ECDH_ECDSA_WITH_RC4_128_SHA,
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA
+    TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_128_GCM_SHA256
+    TLS_RSA_WITH_AES_128_GCM_SHA256,
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_256_GCM_SHA384
+    TLS_RSA_WITH_AES_256_GCM_SHA384,
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
+    TLS_DHE_RSA_WITH_AES_128_GCM_SHA256,
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
+    TLS_DHE_RSA_WITH_AES_256_GCM_SHA384,
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
+    TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256,
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
+    TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384,
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
+    TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256,
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
+    TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256
+    TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256,
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384
+    TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384,
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256
+    TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256,
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384
+    TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384,
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA
+    TLS_RSA_WITH_CAMELLIA_128_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA
+    TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA
+    TLS_RSA_WITH_CAMELLIA_256_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA
+    TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA,
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256
+    TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256,
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+    TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256,
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256
+    TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256,
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256
+    TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256,
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
+    TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256,
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
+    TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256,
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256
+    TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256,
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256
+    TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256,
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384
+    TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384,
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384
+    TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384,
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384
+    TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384,
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384
+    TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384,
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256
+    TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256,
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256
+    TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256,
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256
+    TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256,
+#endif
+
+#ifdef BUILD_TLS_DH_anon_WITH_AES_128_CBC_SHA
+    TLS_DH_anon_WITH_AES_128_CBC_SHA,
+#endif
+
+#ifdef HAVE_RENEGOTIATION_INDICATION
+    TLS_EMPTY_RENEGOTIATION_INFO_SCSV,
+#endif
+};
+
+
+/* returns the cipher_names array */
+const char* const* GetCipherNames(void)
+{
+    return cipher_names;
+}
+
+
+/* returns the size of the cipher_names array */
+int GetCipherNamesSize(void)
+{
+    return (int)(sizeof(cipher_names) / sizeof(char*));
+}
+
+
+/**
+Set the enabled cipher suites.
+
+@param [out] suites Suites structure.
+@param [in]  list   List of cipher suites, only supports full name from
+                    cipher_name[] delimited by ':'.
+
+@return true on success, else false.
+*/
+int SetCipherList(Suites* suites, const char* list)
+{
+    int       ret          = 0;
+    int       idx          = 0;
+    int       haveRSAsig   = 0;
+    int       haveECDSAsig = 0;
+    int       haveAnon     = 0;
+    const int suiteSz      = GetCipherNamesSize();
+    char*     next         = (char*)list;
+
+    if (suites == NULL || list == NULL) {
+        WOLFSSL_MSG("SetCipherList parameter error");
+        return 0;
+    }
+
+    if (next[0] == 0 || XSTRNCMP(next, "ALL", 3) == 0)
+        return 1; /* wolfSSL defualt */
+
+    do {
+        char*  current = next;
+        char   name[MAX_SUITE_NAME + 1];
+        int    i;
+        word32 length;
+
+        next   = XSTRSTR(next, ":");
+        length = min(sizeof(name), !next ? (word32)XSTRLEN(current) /* last */
+                                         : (word32)(next - current));
+
+        XSTRNCPY(name, current, length);
+        name[(length == sizeof(name)) ? length - 1 : length] = 0;
+
+        for (i = 0; i < suiteSz; i++) {
+            if (XSTRNCMP(name, cipher_names[i], sizeof(name)) == 0) {
+                suites->suites[idx++] = (XSTRSTR(name, "CHACHA")) ? CHACHA_BYTE
+                                      : (XSTRSTR(name, "EC"))     ? ECC_BYTE
+                                      : (XSTRSTR(name, "CCM"))    ? ECC_BYTE
+                                      : 0x00; /* normal */
+
+                suites->suites[idx++] = (byte)cipher_name_idx[i];
+
+                /* The suites are either ECDSA, RSA, PSK, or Anon. The RSA
+                 * suites don't necessarily have RSA in the name. */
+                if ((haveECDSAsig == 0) && XSTRSTR(name, "ECDSA"))
+                    haveECDSAsig = 1;
+                else if (XSTRSTR(name, "ADH"))
+                    haveAnon = 1;
+                else if ((haveRSAsig == 0) && (XSTRSTR(name, "PSK") == NULL))
+                    haveRSAsig = 1;
+
+                ret = 1; /* found at least one */
+                break;
+            }
+        }
+    }
+    while (next++); /* ++ needed to skip ':' */
+
+    if (ret) {
+        suites->setSuites = 1;
+        suites->suiteSz   = (word16)idx;
+        InitSuitesHashSigAlgo(suites, haveECDSAsig, haveRSAsig, haveAnon);
+    }
+
+    return ret;
+}
+
+
+static void PickHashSigAlgo(WOLFSSL* ssl,
+                             const byte* hashSigAlgo, word32 hashSigAlgoSz)
+{
+    word32 i;
+
+    ssl->suites->sigAlgo = ssl->specs.sig_algo;
+    ssl->suites->hashAlgo = sha_mac;
+
+    /* i+1 since peek a byte ahead for type */
+    for (i = 0; (i+1) < hashSigAlgoSz; i += 2) {
+        if (hashSigAlgo[i+1] == ssl->specs.sig_algo) {
+            if (hashSigAlgo[i] == sha_mac) {
+                break;
+            }
+            #ifndef NO_SHA256
+            else if (hashSigAlgo[i] == sha256_mac) {
+                ssl->suites->hashAlgo = sha256_mac;
+                break;
+            }
+            #endif
+            #ifdef WOLFSSL_SHA384
+            else if (hashSigAlgo[i] == sha384_mac) {
+                ssl->suites->hashAlgo = sha384_mac;
+                break;
+            }
+            #endif
+            #ifdef WOLFSSL_SHA512
+            else if (hashSigAlgo[i] == sha512_mac) {
+                ssl->suites->hashAlgo = sha512_mac;
+                break;
+            }
+            #endif
+        }
+    }
+}
+
+
+#ifdef WOLFSSL_CALLBACKS
+
+    /* Initialisze HandShakeInfo */
+    void InitHandShakeInfo(HandShakeInfo* info)
+    {
+        int i;
+
+        info->cipherName[0] = 0;
+        for (i = 0; i < MAX_PACKETS_HANDSHAKE; i++)
+            info->packetNames[i][0] = 0;
+        info->numberPackets = 0;
+        info->negotiationError = 0;
+    }
+
+    /* Set Final HandShakeInfo parameters */
+    void FinishHandShakeInfo(HandShakeInfo* info, const WOLFSSL* ssl)
+    {
+        int i;
+        int sz = sizeof(cipher_name_idx)/sizeof(int);
+
+        for (i = 0; i < sz; i++)
+            if (ssl->options.cipherSuite == (byte)cipher_name_idx[i]) {
+                if (ssl->options.cipherSuite0 == ECC_BYTE)
+                    continue;   /* ECC suites at end */
+                XSTRNCPY(info->cipherName, cipher_names[i], MAX_CIPHERNAME_SZ);
+                break;
+            }
+
+        /* error max and min are negative numbers */
+        if (ssl->error <= MIN_PARAM_ERR && ssl->error >= MAX_PARAM_ERR)
+            info->negotiationError = ssl->error;
+    }
+
+
+    /* Add name to info packet names, increase packet name count */
+    void AddPacketName(const char* name, HandShakeInfo* info)
+    {
+        if (info->numberPackets < MAX_PACKETS_HANDSHAKE) {
+            XSTRNCPY(info->packetNames[info->numberPackets++], name,
+                    MAX_PACKETNAME_SZ);
+        }
+    }
+
+
+    /* Initialisze TimeoutInfo */
+    void InitTimeoutInfo(TimeoutInfo* info)
+    {
+        int i;
+
+        info->timeoutName[0] = 0;
+        info->flags          = 0;
+
+        for (i = 0; i < MAX_PACKETS_HANDSHAKE; i++) {
+            info->packets[i].packetName[0]     = 0;
+            info->packets[i].timestamp.tv_sec  = 0;
+            info->packets[i].timestamp.tv_usec = 0;
+            info->packets[i].bufferValue       = 0;
+            info->packets[i].valueSz           = 0;
+        }
+        info->numberPackets        = 0;
+        info->timeoutValue.tv_sec  = 0;
+        info->timeoutValue.tv_usec = 0;
+    }
+
+
+    /* Free TimeoutInfo */
+    void FreeTimeoutInfo(TimeoutInfo* info, void* heap)
+    {
+        int i;
+        (void)heap;
+        for (i = 0; i < MAX_PACKETS_HANDSHAKE; i++)
+            if (info->packets[i].bufferValue) {
+                XFREE(info->packets[i].bufferValue, heap, DYNAMIC_TYPE_INFO);
+                info->packets[i].bufferValue = 0;
+            }
+
+    }
+
+
+    /* Add PacketInfo to TimeoutInfo */
+    void AddPacketInfo(const char* name, TimeoutInfo* info, const byte* data,
+                       int sz, void* heap)
+    {
+        if (info->numberPackets < (MAX_PACKETS_HANDSHAKE - 1)) {
+            Timeval currTime;
+
+            /* may add name after */
+            if (name)
+                XSTRNCPY(info->packets[info->numberPackets].packetName, name,
+                        MAX_PACKETNAME_SZ);
+
+            /* add data, put in buffer if bigger than static buffer */
+            info->packets[info->numberPackets].valueSz = sz;
+            if (sz < MAX_VALUE_SZ)
+                XMEMCPY(info->packets[info->numberPackets].value, data, sz);
+            else {
+                info->packets[info->numberPackets].bufferValue =
+                           XMALLOC(sz, heap, DYNAMIC_TYPE_INFO);
+                if (!info->packets[info->numberPackets].bufferValue)
+                    /* let next alloc catch, just don't fill, not fatal here  */
+                    info->packets[info->numberPackets].valueSz = 0;
+                else
+                    XMEMCPY(info->packets[info->numberPackets].bufferValue,
+                           data, sz);
+            }
+            gettimeofday(&currTime, 0);
+            info->packets[info->numberPackets].timestamp.tv_sec  =
+                                                             currTime.tv_sec;
+            info->packets[info->numberPackets].timestamp.tv_usec =
+                                                             currTime.tv_usec;
+            info->numberPackets++;
+        }
+    }
+
+
+    /* Add packet name to previsouly added packet info */
+    void AddLateName(const char* name, TimeoutInfo* info)
+    {
+        /* make sure we have a valid previous one */
+        if (info->numberPackets > 0 && info->numberPackets <
+                                                        MAX_PACKETS_HANDSHAKE) {
+            XSTRNCPY(info->packets[info->numberPackets - 1].packetName, name,
+                    MAX_PACKETNAME_SZ);
+        }
+    }
+
+    /* Add record header to previsouly added packet info */
+    void AddLateRecordHeader(const RecordLayerHeader* rl, TimeoutInfo* info)
+    {
+        /* make sure we have a valid previous one */
+        if (info->numberPackets > 0 && info->numberPackets <
+                                                        MAX_PACKETS_HANDSHAKE) {
+            if (info->packets[info->numberPackets - 1].bufferValue)
+                XMEMCPY(info->packets[info->numberPackets - 1].bufferValue, rl,
+                       RECORD_HEADER_SZ);
+            else
+                XMEMCPY(info->packets[info->numberPackets - 1].value, rl,
+                       RECORD_HEADER_SZ);
+        }
+    }
+
+#endif /* WOLFSSL_CALLBACKS */
+
+
+
+/* client only parts */
+#ifndef NO_WOLFSSL_CLIENT
+
+    int SendClientHello(WOLFSSL* ssl)
+    {
+        byte              *output;
+        word32             length, idx = RECORD_HEADER_SZ + HANDSHAKE_HEADER_SZ;
+        int                sendSz;
+        int                idSz = ssl->options.resuming
+                                ? ssl->session.sessionIDSz
+                                : 0;
+        int                ret;
+
+        if (ssl->suites == NULL) {
+            WOLFSSL_MSG("Bad suites pointer in SendClientHello");
+            return SUITES_ERROR;
+        }
+
+#ifdef HAVE_SESSION_TICKET
+        if (ssl->options.resuming && ssl->session.ticketLen > 0) {
+            SessionTicket* ticket;
+
+            ticket = TLSX_SessionTicket_Create(0,
+                                   ssl->session.ticket, ssl->session.ticketLen);
+            if (ticket == NULL) return MEMORY_E;
+
+            ret = TLSX_UseSessionTicket(&ssl->extensions, ticket);
+            if (ret != SSL_SUCCESS) return ret;
+
+            idSz = 0;
+        }
+#endif
+
+        length = VERSION_SZ + RAN_LEN
+               + idSz + ENUM_LEN
+               + ssl->suites->suiteSz + SUITE_LEN
+               + COMP_LEN + ENUM_LEN;
+
+#ifdef HAVE_TLS_EXTENSIONS
+        length += TLSX_GetRequestSize(ssl);
+#else
+        if (IsAtLeastTLSv1_2(ssl) && ssl->suites->hashSigAlgoSz) {
+            length += ssl->suites->hashSigAlgoSz + HELLO_EXT_SZ;
+        }
+#endif
+        sendSz = length + HANDSHAKE_HEADER_SZ + RECORD_HEADER_SZ;
+
+#ifdef WOLFSSL_DTLS
+        if (ssl->options.dtls) {
+            length += ENUM_LEN;   /* cookie */
+            if (ssl->arrays->cookieSz != 0) length += ssl->arrays->cookieSz;
+            sendSz  = length + DTLS_HANDSHAKE_HEADER_SZ + DTLS_RECORD_HEADER_SZ;
+            idx    += DTLS_HANDSHAKE_EXTRA + DTLS_RECORD_EXTRA;
+        }
+#endif
+
+        if (ssl->keys.encryptionOn)
+            sendSz += MAX_MSG_EXTRA;
+
+        /* check for available size */
+        if ((ret = CheckAvailableSize(ssl, sendSz)) != 0)
+            return ret;
+
+        /* get ouput buffer */
+        output = ssl->buffers.outputBuffer.buffer +
+                 ssl->buffers.outputBuffer.length;
+
+        AddHeaders(output, length, client_hello, ssl);
+
+            /* client hello, first version */
+        output[idx++] = ssl->version.major;
+        output[idx++] = ssl->version.minor;
+        ssl->chVersion = ssl->version;  /* store in case changed */
+
+            /* then random */
+        if (ssl->options.connectState == CONNECT_BEGIN) {
+            ret = wc_RNG_GenerateBlock(ssl->rng, output + idx, RAN_LEN);
+            if (ret != 0)
+                return ret;
+
+                /* store random */
+            XMEMCPY(ssl->arrays->clientRandom, output + idx, RAN_LEN);
+        } else {
+#ifdef WOLFSSL_DTLS
+                /* send same random on hello again */
+            XMEMCPY(output + idx, ssl->arrays->clientRandom, RAN_LEN);
+#endif
+        }
+        idx += RAN_LEN;
+
+            /* then session id */
+        output[idx++] = (byte)idSz;
+        if (idSz) {
+            XMEMCPY(output + idx, ssl->session.sessionID,
+                                                      ssl->session.sessionIDSz);
+            idx += ssl->session.sessionIDSz;
+        }
+
+            /* then DTLS cookie */
+#ifdef WOLFSSL_DTLS
+        if (ssl->options.dtls) {
+            byte cookieSz = ssl->arrays->cookieSz;
+
+            output[idx++] = cookieSz;
+            if (cookieSz) {
+                XMEMCPY(&output[idx], ssl->arrays->cookie, cookieSz);
+                idx += cookieSz;
+            }
+        }
+#endif
+            /* then cipher suites */
+        c16toa(ssl->suites->suiteSz, output + idx);
+        idx += 2;
+        XMEMCPY(output + idx, &ssl->suites->suites, ssl->suites->suiteSz);
+        idx += ssl->suites->suiteSz;
+
+            /* last, compression */
+        output[idx++] = COMP_LEN;
+        if (ssl->options.usingCompression)
+            output[idx++] = ZLIB_COMPRESSION;
+        else
+            output[idx++] = NO_COMPRESSION;
+
+#ifdef HAVE_TLS_EXTENSIONS
+        idx += TLSX_WriteRequest(ssl, output + idx);
+
+        (void)idx; /* suppress analyzer warning, keep idx current */
+#else
+        if (IsAtLeastTLSv1_2(ssl) && ssl->suites->hashSigAlgoSz)
+        {
+            int i;
+            /* add in the extensions length */
+            c16toa(HELLO_EXT_LEN + ssl->suites->hashSigAlgoSz, output + idx);
+            idx += 2;
+
+            c16toa(HELLO_EXT_SIG_ALGO, output + idx);
+            idx += 2;
+            c16toa(HELLO_EXT_SIGALGO_SZ+ssl->suites->hashSigAlgoSz, output+idx);
+            idx += 2;
+            c16toa(ssl->suites->hashSigAlgoSz, output + idx);
+            idx += 2;
+            for (i = 0; i < ssl->suites->hashSigAlgoSz; i++, idx++) {
+                output[idx] = ssl->suites->hashSigAlgo[i];
+            }
+        }
+#endif
+
+        if (ssl->keys.encryptionOn) {
+            byte* input;
+            int   inputSz = idx - RECORD_HEADER_SZ; /* build msg adds rec hdr */
+
+            input = (byte*)XMALLOC(inputSz, ssl->heap, DYNAMIC_TYPE_TMP_BUFFER);
+            if (input == NULL)
+                return MEMORY_E;
+
+            XMEMCPY(input, output + RECORD_HEADER_SZ, inputSz);
+            sendSz = BuildMessage(ssl, output, sendSz, input,inputSz,handshake);
+            XFREE(input, ssl->heap, DYNAMIC_TYPE_TMP_BUFFER);
+
+            if (sendSz < 0)
+                return sendSz;
+        } else {
+            ret = HashOutput(ssl, output, sendSz, 0);
+            if (ret != 0)
+                return ret;
+        }
+
+        #ifdef WOLFSSL_DTLS
+            if (ssl->options.dtls) {
+                if ((ret = DtlsPoolSave(ssl, output, sendSz)) != 0)
+                    return ret;
+            }
+        #endif
+
+        ssl->options.clientState = CLIENT_HELLO_COMPLETE;
+
+#ifdef WOLFSSL_CALLBACKS
+        if (ssl->hsInfoOn) AddPacketName("ClientHello", &ssl->handShakeInfo);
+        if (ssl->toInfoOn)
+            AddPacketInfo("ClientHello", &ssl->timeoutInfo, output, sendSz,
+                          ssl->heap);
+#endif
+
+        ssl->buffers.outputBuffer.length += sendSz;
+
+        return SendBuffered(ssl);
+    }
+
+
+    static int DoHelloVerifyRequest(WOLFSSL* ssl, const byte* input,
+                                    word32* inOutIdx, word32 size)
+    {
+        ProtocolVersion pv;
+        byte            cookieSz;
+        word32          begin = *inOutIdx;
+
+#ifdef WOLFSSL_CALLBACKS
+        if (ssl->hsInfoOn) AddPacketName("HelloVerifyRequest",
+                                         &ssl->handShakeInfo);
+        if (ssl->toInfoOn) AddLateName("HelloVerifyRequest", &ssl->timeoutInfo);
+#endif
+
+#ifdef WOLFSSL_DTLS
+        if (ssl->options.dtls) {
+            DtlsPoolReset(ssl);
+        }
+#endif
+
+        if ((*inOutIdx - begin) + OPAQUE16_LEN + OPAQUE8_LEN > size)
+            return BUFFER_ERROR;
+
+        XMEMCPY(&pv, input + *inOutIdx, OPAQUE16_LEN);
+        *inOutIdx += OPAQUE16_LEN;
+
+        cookieSz = input[(*inOutIdx)++];
+
+        if (cookieSz) {
+            if ((*inOutIdx - begin) + cookieSz > size)
+                return BUFFER_ERROR;
+
+#ifdef WOLFSSL_DTLS
+            if (cookieSz <= MAX_COOKIE_LEN) {
+                XMEMCPY(ssl->arrays->cookie, input + *inOutIdx, cookieSz);
+                ssl->arrays->cookieSz = cookieSz;
+            }
+#endif
+            *inOutIdx += cookieSz;
+        }
+
+        ssl->options.serverState = SERVER_HELLOVERIFYREQUEST_COMPLETE;
+        return 0;
+    }
+
+
+    static INLINE int DSH_CheckSessionId(WOLFSSL* ssl)
+    {
+        int ret = 0;
+
+#ifdef HAVE_SECRET_CALLBACK
+        /* If a session secret callback exists, we are using that
+         * key instead of the saved session key. */
+        ret = ret || (ssl->sessionSecretCb != NULL);
+#endif
+
+#ifdef HAVE_SESSION_TICKET
+        /* server may send blank ticket which may not be expected to indicate
+         * exisiting one ok but will also be sending a new one */
+        ret = ret || (ssl->session.ticketLen > 0);
+#endif
+
+        ret = ret ||
+              (ssl->options.haveSessionId && XMEMCMP(ssl->arrays->sessionID,
+                                          ssl->session.sessionID, ID_LEN) == 0);
+
+        return ret;
+    }
+
+    static int DoServerHello(WOLFSSL* ssl, const byte* input, word32* inOutIdx,
+                             word32 helloSz)
+    {
+        byte            cs0;   /* cipher suite bytes 0, 1 */
+        byte            cs1;
+        ProtocolVersion pv;
+        byte            compression;
+        word32          i = *inOutIdx;
+        word32          begin = i;
+
+#ifdef WOLFSSL_CALLBACKS
+        if (ssl->hsInfoOn) AddPacketName("ServerHello", &ssl->handShakeInfo);
+        if (ssl->toInfoOn) AddLateName("ServerHello", &ssl->timeoutInfo);
+#endif
+
+        /* protocol version, random and session id length check */
+        if (OPAQUE16_LEN + RAN_LEN + OPAQUE8_LEN > helloSz)
+            return BUFFER_ERROR;
+
+        /* protocol version */
+        XMEMCPY(&pv, input + i, OPAQUE16_LEN);
+        i += OPAQUE16_LEN;
+
+        if (pv.minor > ssl->version.minor) {
+            WOLFSSL_MSG("Server using higher version, fatal error");
+            return VERSION_ERROR;
+        }
+        else if (pv.minor < ssl->version.minor) {
+            WOLFSSL_MSG("server using lower version");
+
+            if (!ssl->options.downgrade) {
+                WOLFSSL_MSG("    no downgrade allowed, fatal error");
+                return VERSION_ERROR;
+            }
+            if (pv.minor < ssl->options.minDowngrade) {
+                WOLFSSL_MSG("    version below minimum allowed, fatal error");
+                return VERSION_ERROR;
+            }
+
+            #ifdef HAVE_SECURE_RENEGOTIATION
+                if (ssl->secure_renegotiation &&
+                                         ssl->secure_renegotiation->enabled &&
+                                         ssl->options.handShakeDone) {
+                    WOLFSSL_MSG("Server changed version during scr");
+                    return VERSION_ERROR;
+                }
+            #endif
+
+            if (pv.minor == SSLv3_MINOR) {
+                /* turn off tls */
+                WOLFSSL_MSG("    downgrading to SSLv3");
+                ssl->options.tls    = 0;
+                ssl->options.tls1_1 = 0;
+                ssl->version.minor  = SSLv3_MINOR;
+            }
+            else if (pv.minor == TLSv1_MINOR) {
+                /* turn off tls 1.1+ */
+                WOLFSSL_MSG("    downgrading to TLSv1");
+                ssl->options.tls1_1 = 0;
+                ssl->version.minor  = TLSv1_MINOR;
+            }
+            else if (pv.minor == TLSv1_1_MINOR) {
+                WOLFSSL_MSG("    downgrading to TLSv1.1");
+                ssl->version.minor  = TLSv1_1_MINOR;
+            }
+        }
+
+        /* random */
+        XMEMCPY(ssl->arrays->serverRandom, input + i, RAN_LEN);
+        i += RAN_LEN;
+
+        /* session id */
+        ssl->arrays->sessionIDSz = input[i++];
+
+        if (ssl->arrays->sessionIDSz > ID_LEN) {
+            WOLFSSL_MSG("Invalid session ID size");
+            ssl->arrays->sessionIDSz = 0;
+            return BUFFER_ERROR;
+        }
+        else if (ssl->arrays->sessionIDSz) {
+            if ((i - begin) + ssl->arrays->sessionIDSz > helloSz)
+                return BUFFER_ERROR;
+
+            XMEMCPY(ssl->arrays->sessionID, input + i,
+                                                      ssl->arrays->sessionIDSz);
+            i += ssl->arrays->sessionIDSz;
+            ssl->options.haveSessionId = 1;
+        }
+
+
+        /* suite and compression */
+        if ((i - begin) + OPAQUE16_LEN + OPAQUE8_LEN > helloSz)
+            return BUFFER_ERROR;
+
+        cs0 = input[i++];
+        cs1 = input[i++];
+
+#ifdef HAVE_SECURE_RENEGOTIATION
+        if (ssl->secure_renegotiation && ssl->secure_renegotiation->enabled &&
+                                         ssl->options.handShakeDone) {
+            if (ssl->options.cipherSuite0 != cs0 ||
+                ssl->options.cipherSuite  != cs1) {
+                WOLFSSL_MSG("Server changed cipher suite during scr");
+                return MATCH_SUITE_ERROR;
+            }
+        }
+#endif
+
+        ssl->options.cipherSuite0 = cs0;
+        ssl->options.cipherSuite  = cs1;
+        compression = input[i++];
+
+        if (compression != ZLIB_COMPRESSION && ssl->options.usingCompression) {
+            WOLFSSL_MSG("Server refused compression, turning off");
+            ssl->options.usingCompression = 0;  /* turn off if server refused */
+        }
+
+        *inOutIdx = i;
+
+        /* tls extensions */
+        if ( (i - begin) < helloSz) {
+#ifdef HAVE_TLS_EXTENSIONS
+            if (TLSX_SupportExtensions(ssl)) {
+                int    ret = 0;
+                word16 totalExtSz;
+
+                if ((i - begin) + OPAQUE16_LEN > helloSz)
+                    return BUFFER_ERROR;
+
+                ato16(&input[i], &totalExtSz);
+                i += OPAQUE16_LEN;
+
+                if ((i - begin) + totalExtSz > helloSz)
+                    return BUFFER_ERROR;
+
+                if ((ret = TLSX_Parse(ssl, (byte *) input + i,
+                                                          totalExtSz, 0, NULL)))
+                    return ret;
+
+                i += totalExtSz;
+                *inOutIdx = i;
+            }
+            else
+#endif
+                *inOutIdx = begin + helloSz; /* skip extensions */
+        }
+
+        ssl->options.serverState = SERVER_HELLO_COMPLETE;
+
+        if (ssl->keys.encryptionOn) {
+            *inOutIdx += ssl->keys.padSz;
+        }
+
+#ifdef HAVE_SECRET_CALLBACK
+        if (ssl->sessionSecretCb != NULL) {
+            int secretSz = SECRET_LEN, ret;
+            ret = ssl->sessionSecretCb(ssl, ssl->session.masterSecret,
+                                              &secretSz, ssl->sessionSecretCtx);
+            if (ret != 0 || secretSz != SECRET_LEN)
+                return SESSION_SECRET_CB_E;
+        }
+#endif /* HAVE_SECRET_CALLBACK */
+
+        if (ssl->options.resuming) {
+            if (DSH_CheckSessionId(ssl)) {
+                if (SetCipherSpecs(ssl) == 0) {
+                    int ret = -1;
+
+                    XMEMCPY(ssl->arrays->masterSecret,
+                            ssl->session.masterSecret, SECRET_LEN);
+                    #ifdef NO_OLD_TLS
+                        ret = DeriveTlsKeys(ssl);
+                    #else
+                        #ifndef NO_TLS
+                            if (ssl->options.tls)
+                                ret = DeriveTlsKeys(ssl);
+                        #endif
+                            if (!ssl->options.tls)
+                                ret = DeriveKeys(ssl);
+                    #endif
+                    ssl->options.serverState = SERVER_HELLODONE_COMPLETE;
+
+                    return ret;
+                }
+                else {
+                    WOLFSSL_MSG("Unsupported cipher suite, DoServerHello");
+                    return UNSUPPORTED_SUITE;
+                }
+            }
+            else {
+                WOLFSSL_MSG("Server denied resumption attempt");
+                ssl->options.resuming = 0; /* server denied resumption try */
+            }
+        }
+        #ifdef WOLFSSL_DTLS
+            if (ssl->options.dtls) {
+                DtlsPoolReset(ssl);
+            }
+        #endif
+
+        return SetCipherSpecs(ssl);
+    }
+
+
+    /* Make sure client setup is valid for this suite, true on success */
+    int VerifyClientSuite(WOLFSSL* ssl)
+    {
+        int  havePSK = 0;
+        byte first   = ssl->options.cipherSuite0;
+        byte second  = ssl->options.cipherSuite;
+
+        WOLFSSL_ENTER("VerifyClientSuite");
+
+        #ifndef NO_PSK
+            havePSK = ssl->options.havePSK;
+        #endif
+
+        if (CipherRequires(first, second, REQUIRES_PSK)) {
+            WOLFSSL_MSG("Requires PSK");
+            if (havePSK == 0) {
+                WOLFSSL_MSG("Don't have PSK");
+                return 0;
+            }
+        }
+
+        return 1;  /* success */
+    }
+
+
+#ifndef NO_CERTS
+    /* just read in and ignore for now TODO: */
+    static int DoCertificateRequest(WOLFSSL* ssl, const byte* input, word32*
+                                    inOutIdx, word32 size)
+    {
+        word16 len;
+        word32 begin = *inOutIdx;
+
+        #ifdef WOLFSSL_CALLBACKS
+            if (ssl->hsInfoOn)
+                AddPacketName("CertificateRequest", &ssl->handShakeInfo);
+            if (ssl->toInfoOn)
+                AddLateName("CertificateRequest", &ssl->timeoutInfo);
+        #endif
+
+        if ((*inOutIdx - begin) + OPAQUE8_LEN > size)
+            return BUFFER_ERROR;
+
+        len = input[(*inOutIdx)++];
+
+        if ((*inOutIdx - begin) + len > size)
+            return BUFFER_ERROR;
+
+        /* types, read in here */
+        *inOutIdx += len;
+
+        /* signature and hash signature algorithm */
+        if (IsAtLeastTLSv1_2(ssl)) {
+            if ((*inOutIdx - begin) + OPAQUE16_LEN > size)
+                return BUFFER_ERROR;
+
+            ato16(input + *inOutIdx, &len);
+            *inOutIdx += OPAQUE16_LEN;
+
+            if ((*inOutIdx - begin) + len > size)
+                return BUFFER_ERROR;
+
+            PickHashSigAlgo(ssl, input + *inOutIdx, len);
+            *inOutIdx += len;
+        }
+
+        /* authorities */
+        if ((*inOutIdx - begin) + OPAQUE16_LEN > size)
+            return BUFFER_ERROR;
+
+        ato16(input + *inOutIdx, &len);
+        *inOutIdx += OPAQUE16_LEN;
+
+        if ((*inOutIdx - begin) + len > size)
+            return BUFFER_ERROR;
+
+        while (len) {
+            word16 dnSz;
+
+            if ((*inOutIdx - begin) + OPAQUE16_LEN > size)
+                return BUFFER_ERROR;
+
+            ato16(input + *inOutIdx, &dnSz);
+            *inOutIdx += OPAQUE16_LEN;
+
+            if ((*inOutIdx - begin) + dnSz > size)
+                return BUFFER_ERROR;
+
+            *inOutIdx += dnSz;
+            len -= OPAQUE16_LEN + dnSz;
+        }
+
+        /* don't send client cert or cert verify if user hasn't provided
+           cert and private key */
+        if (ssl->buffers.certificate.buffer && ssl->buffers.key.buffer)
+            ssl->options.sendVerify = SEND_CERT;
+        else if (IsTLS(ssl))
+            ssl->options.sendVerify = SEND_BLANK_CERT;
+
+        if (ssl->keys.encryptionOn)
+            *inOutIdx += ssl->keys.padSz;
+
+        return 0;
+    }
+#endif /* !NO_CERTS */
+
+
+#ifdef HAVE_ECC
+
+    static int CheckCurveId(int oid)
+    {
+        int ret = 0;
+
+        switch (oid) {
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC160)
+            case WOLFSSL_ECC_SECP160R1:
+#endif
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC192)
+            case WOLFSSL_ECC_SECP192R1:
+#endif
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC224)
+            case WOLFSSL_ECC_SECP224R1:
+#endif
+#if defined(HAVE_ALL_CURVES) || !defined(NO_ECC256)
+            case WOLFSSL_ECC_SECP256R1:
+#endif
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC384)
+            case WOLFSSL_ECC_SECP384R1:
+#endif
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC521)
+            case WOLFSSL_ECC_SECP521R1:
+#endif
+                break;
+
+            default:
+                ret = -1;
+        }
+
+        return ret;
+    }
+
+#endif /* HAVE_ECC */
+
+    static int DoServerKeyExchange(WOLFSSL* ssl, const byte* input,
+                                   word32* inOutIdx, word32 size)
+    {
+        word16 length = 0;
+        word32 begin  = *inOutIdx;
+        int    ret    = 0;
+        #define ERROR_OUT(err, eLabel) do { ret = err; goto eLabel; } while(0)
+
+        (void)length; /* shut up compiler warnings */
+        (void)begin;
+        (void)ssl;
+        (void)input;
+        (void)size;
+        (void)ret;
+
+    #ifdef WOLFSSL_CALLBACKS
+        if (ssl->hsInfoOn)
+            AddPacketName("ServerKeyExchange", &ssl->handShakeInfo);
+        if (ssl->toInfoOn)
+            AddLateName("ServerKeyExchange", &ssl->timeoutInfo);
+    #endif
+
+    #ifndef NO_PSK
+        if (ssl->specs.kea == psk_kea) {
+
+            if ((*inOutIdx - begin) + OPAQUE16_LEN > size)
+                return BUFFER_ERROR;
+
+            ato16(input + *inOutIdx, &length);
+            *inOutIdx += OPAQUE16_LEN;
+
+            if ((*inOutIdx - begin) + length > size)
+                return BUFFER_ERROR;
+
+            XMEMCPY(ssl->arrays->server_hint, input + *inOutIdx,
+                   min(length, MAX_PSK_ID_LEN));
+
+            ssl->arrays->server_hint[min(length, MAX_PSK_ID_LEN - 1)] = 0;
+            *inOutIdx += length;
+
+            return 0;
+        }
+    #endif
+    #ifndef NO_DH
+        if (ssl->specs.kea == diffie_hellman_kea)
+        {
+        /* p */
+        if ((*inOutIdx - begin) + OPAQUE16_LEN > size)
+            return BUFFER_ERROR;
+
+        ato16(input + *inOutIdx, &length);
+        *inOutIdx += OPAQUE16_LEN;
+
+        if ((*inOutIdx - begin) + length > size)
+            return BUFFER_ERROR;
+
+        if (length < ssl->options.minDhKeySz) {
+            WOLFSSL_MSG("Server using a DH key that is too small");
+            SendAlert(ssl, alert_fatal, handshake_failure);
+            return DH_KEY_SIZE_E;
+        }
+
+        ssl->buffers.serverDH_P.buffer = (byte*) XMALLOC(length, ssl->heap,
+                                                         DYNAMIC_TYPE_DH);
+
+        if (ssl->buffers.serverDH_P.buffer)
+            ssl->buffers.serverDH_P.length = length;
+        else
+            return MEMORY_ERROR;
+
+        XMEMCPY(ssl->buffers.serverDH_P.buffer, input + *inOutIdx, length);
+        *inOutIdx += length;
+
+        ssl->options.dhKeySz = length;
+
+        /* g */
+        if ((*inOutIdx - begin) + OPAQUE16_LEN > size)
+            return BUFFER_ERROR;
+
+        ato16(input + *inOutIdx, &length);
+        *inOutIdx += OPAQUE16_LEN;
+
+        if ((*inOutIdx - begin) + length > size)
+            return BUFFER_ERROR;
+
+        ssl->buffers.serverDH_G.buffer = (byte*) XMALLOC(length, ssl->heap,
+                                                         DYNAMIC_TYPE_DH);
+
+        if (ssl->buffers.serverDH_G.buffer)
+            ssl->buffers.serverDH_G.length = length;
+        else
+            return MEMORY_ERROR;
+
+        XMEMCPY(ssl->buffers.serverDH_G.buffer, input + *inOutIdx, length);
+        *inOutIdx += length;
+
+        /* pub */
+        if ((*inOutIdx - begin) + OPAQUE16_LEN > size)
+            return BUFFER_ERROR;
+
+        ato16(input + *inOutIdx, &length);
+        *inOutIdx += OPAQUE16_LEN;
+
+        if ((*inOutIdx - begin) + length > size)
+            return BUFFER_ERROR;
+
+        ssl->buffers.serverDH_Pub.buffer = (byte*) XMALLOC(length, ssl->heap,
+                                                           DYNAMIC_TYPE_DH);
+
+        if (ssl->buffers.serverDH_Pub.buffer)
+            ssl->buffers.serverDH_Pub.length = length;
+        else
+            return MEMORY_ERROR;
+
+        XMEMCPY(ssl->buffers.serverDH_Pub.buffer, input + *inOutIdx, length);
+        *inOutIdx += length;
+        }  /* dh_kea */
+    #endif /* NO_DH */
+
+    #ifdef HAVE_ECC
+        if (ssl->specs.kea == ecc_diffie_hellman_kea)
+        {
+        byte b;
+
+        if ((*inOutIdx - begin) + ENUM_LEN + OPAQUE16_LEN + OPAQUE8_LEN > size)
+            return BUFFER_ERROR;
+
+        b = input[(*inOutIdx)++];
+
+        if (b != named_curve)
+            return ECC_CURVETYPE_ERROR;
+
+        *inOutIdx += 1;   /* curve type, eat leading 0 */
+        b = input[(*inOutIdx)++];
+
+        if (CheckCurveId(b) != 0) {
+            return ECC_CURVE_ERROR;
+        }
+
+        length = input[(*inOutIdx)++];
+
+        if ((*inOutIdx - begin) + length > size)
+            return BUFFER_ERROR;
+
+        if (ssl->peerEccKey == NULL) {
+            /* alloc/init on demand */
+            ssl->peerEccKey = (ecc_key*)XMALLOC(sizeof(ecc_key),
+                                              ssl->ctx->heap, DYNAMIC_TYPE_ECC);
+            if (ssl->peerEccKey == NULL) {
+                WOLFSSL_MSG("PeerEccKey Memory error");
+                return MEMORY_E;
+            }
+            wc_ecc_init(ssl->peerEccKey);
+        } else if (ssl->peerEccKeyPresent) {  /* don't leak on reuse */
+            wc_ecc_free(ssl->peerEccKey);
+            ssl->peerEccKeyPresent = 0;
+            wc_ecc_init(ssl->peerEccKey);
+        }
+
+        if (wc_ecc_import_x963(input + *inOutIdx, length, ssl->peerEccKey) != 0)
+            return ECC_PEERKEY_ERROR;
+
+        *inOutIdx += length;
+        ssl->peerEccKeyPresent = 1;
+        }
+    #endif /* HAVE_ECC */
+
+    #if !defined(NO_DH) && !defined(NO_PSK)
+    if (ssl->specs.kea == dhe_psk_kea) {
+        if ((*inOutIdx - begin) + OPAQUE16_LEN > size)
+            return BUFFER_ERROR;
+
+        ato16(input + *inOutIdx, &length);
+        *inOutIdx += OPAQUE16_LEN;
+
+        if ((*inOutIdx - begin) + length > size)
+            return BUFFER_ERROR;
+
+        XMEMCPY(ssl->arrays->server_hint, input + *inOutIdx,
+               min(length, MAX_PSK_ID_LEN));
+
+        ssl->arrays->server_hint[min(length, MAX_PSK_ID_LEN - 1)] = 0;
+        *inOutIdx += length;
+
+        /* p */
+        if ((*inOutIdx - begin) + OPAQUE16_LEN > size)
+            return BUFFER_ERROR;
+
+        ato16(input + *inOutIdx, &length);
+        *inOutIdx += OPAQUE16_LEN;
+
+        if ((*inOutIdx - begin) + length > size)
+            return BUFFER_ERROR;
+
+        if (length < ssl->options.minDhKeySz) {
+            WOLFSSL_MSG("Server using a DH key that is too small");
+            SendAlert(ssl, alert_fatal, handshake_failure);
+            return DH_KEY_SIZE_E;
+        }
+
+        ssl->buffers.serverDH_P.buffer = (byte*) XMALLOC(length, ssl->heap,
+                                                         DYNAMIC_TYPE_DH);
+
+        if (ssl->buffers.serverDH_P.buffer)
+            ssl->buffers.serverDH_P.length = length;
+        else
+            return MEMORY_ERROR;
+
+        XMEMCPY(ssl->buffers.serverDH_P.buffer, input + *inOutIdx, length);
+        *inOutIdx += length;
+
+        ssl->options.dhKeySz = length;
+
+        /* g */
+        if ((*inOutIdx - begin) + OPAQUE16_LEN > size)
+            return BUFFER_ERROR;
+
+        ato16(input + *inOutIdx, &length);
+        *inOutIdx += OPAQUE16_LEN;
+
+        if ((*inOutIdx - begin) + length > size)
+            return BUFFER_ERROR;
+
+        ssl->buffers.serverDH_G.buffer = (byte*) XMALLOC(length, ssl->heap,
+                                                         DYNAMIC_TYPE_DH);
+
+        if (ssl->buffers.serverDH_G.buffer)
+            ssl->buffers.serverDH_G.length = length;
+        else
+            return MEMORY_ERROR;
+
+        XMEMCPY(ssl->buffers.serverDH_G.buffer, input + *inOutIdx, length);
+        *inOutIdx += length;
+
+        /* pub */
+        if ((*inOutIdx - begin) + OPAQUE16_LEN > size)
+            return BUFFER_ERROR;
+
+        ato16(input + *inOutIdx, &length);
+        *inOutIdx += OPAQUE16_LEN;
+
+        if ((*inOutIdx - begin) + length > size)
+            return BUFFER_ERROR;
+
+        ssl->buffers.serverDH_Pub.buffer = (byte*) XMALLOC(length, ssl->heap,
+                                                           DYNAMIC_TYPE_DH);
+
+        if (ssl->buffers.serverDH_Pub.buffer)
+            ssl->buffers.serverDH_Pub.length = length;
+        else
+            return MEMORY_ERROR;
+
+        XMEMCPY(ssl->buffers.serverDH_Pub.buffer, input + *inOutIdx, length);
+        *inOutIdx += length;
+    }
+    #endif /* !NO_DH || !NO_PSK */
+
+    #if !defined(NO_DH) || defined(HAVE_ECC)
+    if (!ssl->options.usingAnon_cipher &&
+        (ssl->specs.kea == ecc_diffie_hellman_kea ||
+         ssl->specs.kea == diffie_hellman_kea))
+    {
+#ifndef NO_OLD_TLS
+#ifdef WOLFSSL_SMALL_STACK
+        Md5*    md5 = NULL;
+        Sha*    sha = NULL;
+#else
+        Md5     md5[1];
+        Sha     sha[1];
+#endif
+#endif
+#ifndef NO_SHA256
+#ifdef WOLFSSL_SMALL_STACK
+        Sha256* sha256  = NULL;
+        byte*   hash256 = NULL;
+#else
+        Sha256  sha256[1];
+        byte    hash256[SHA256_DIGEST_SIZE];
+#endif
+#endif
+#ifdef WOLFSSL_SHA384
+#ifdef WOLFSSL_SMALL_STACK
+        Sha384* sha384  = NULL;
+        byte*   hash384 = NULL;
+#else
+        Sha384  sha384[1];
+        byte    hash384[SHA384_DIGEST_SIZE];
+#endif
+#endif
+#ifdef WOLFSSL_SHA512
+#ifdef WOLFSSL_SMALL_STACK
+        Sha512* sha512  = NULL;
+        byte*   hash512 = NULL;
+#else
+        Sha512  sha512[1];
+        byte    hash512[SHA512_DIGEST_SIZE];
+#endif
+#endif
+#ifdef WOLFSSL_SMALL_STACK
+        byte*   hash          = NULL;
+        byte*   messageVerify = NULL;
+#else
+        byte    hash[FINISHED_SZ];
+        byte    messageVerify[MAX_DH_SZ];
+#endif
+        byte    hashAlgo = sha_mac;
+        byte    sigAlgo  = ssl->specs.sig_algo;
+        word16  verifySz = (word16) (*inOutIdx - begin);
+
+#ifndef NO_OLD_TLS
+        byte doMd5 = 0;
+        byte doSha = 0;
+#endif
+#ifndef NO_SHA256
+        byte doSha256 = 0;
+#endif
+#ifdef WOLFSSL_SHA384
+        byte doSha384 = 0;
+#endif
+#ifdef WOLFSSL_SHA512
+        byte doSha512 = 0;
+#endif
+
+        (void)hash;
+        (void)sigAlgo;
+        (void)hashAlgo;
+
+        /* save message for hash verify */
+        if (verifySz > MAX_DH_SZ)
+            ERROR_OUT(BUFFER_ERROR, done);
+
+    #ifdef WOLFSSL_SMALL_STACK
+        messageVerify = (byte*)XMALLOC(MAX_DH_SZ, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+        if (messageVerify == NULL)
+            ERROR_OUT(MEMORY_E, done);
+    #endif
+
+        XMEMCPY(messageVerify, input + begin, verifySz);
+
+        if (IsAtLeastTLSv1_2(ssl)) {
+            byte setHash = 0;
+            if ((*inOutIdx - begin) + ENUM_LEN + ENUM_LEN > size)
+                ERROR_OUT(BUFFER_ERROR, done);
+
+            hashAlgo = input[(*inOutIdx)++];
+            sigAlgo  = input[(*inOutIdx)++];
+
+            switch (hashAlgo) {
+                case sha512_mac:
+                    #ifdef WOLFSSL_SHA512
+                        doSha512 = 1;
+                        setHash  = 1;
+                    #endif
+                    break;
+
+                case sha384_mac:
+                    #ifdef WOLFSSL_SHA384
+                        doSha384 = 1;
+                        setHash  = 1;
+                    #endif
+                    break;
+
+                case sha256_mac:
+                    #ifndef NO_SHA256
+                        doSha256 = 1;
+                        setHash  = 1;
+                    #endif
+                    break;
+
+                case sha_mac:
+                    #ifndef NO_OLD_TLS
+                        doSha = 1;
+                        setHash  = 1;
+                    #endif
+                    break;
+
+                default:
+                    ERROR_OUT(ALGO_ID_E, done);
+            }
+
+            if (setHash == 0) {
+                ERROR_OUT(ALGO_ID_E, done);
+            }
+
+        } else {
+            /* only using sha and md5 for rsa */
+            #ifndef NO_OLD_TLS
+                doSha = 1;
+                if (sigAlgo == rsa_sa_algo) {
+                    doMd5 = 1;
+                }
+            #else
+                ERROR_OUT(ALGO_ID_E, done);
+            #endif
+        }
+
+        /* signature */
+        if ((*inOutIdx - begin) + OPAQUE16_LEN > size)
+            ERROR_OUT(BUFFER_ERROR, done);
+
+        ato16(input + *inOutIdx, &length);
+        *inOutIdx += OPAQUE16_LEN;
+
+        if ((*inOutIdx - begin) + length > size)
+            ERROR_OUT(BUFFER_ERROR, done);
+
+        /* inOutIdx updated at the end of the function */
+
+        /* verify signature */
+    #ifdef WOLFSSL_SMALL_STACK
+        hash = (byte*)XMALLOC(FINISHED_SZ, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (hash == NULL)
+            ERROR_OUT(MEMORY_E, done);
+    #endif
+
+#ifndef NO_OLD_TLS
+        /* md5 */
+    #ifdef WOLFSSL_SMALL_STACK
+        if (doMd5) {
+            md5 = (Md5*)XMALLOC(sizeof(Md5), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            if (md5 == NULL)
+                ERROR_OUT(MEMORY_E, done);
+        }
+    #endif
+        if (doMd5) {
+            wc_InitMd5(md5);
+            wc_Md5Update(md5, ssl->arrays->clientRandom, RAN_LEN);
+            wc_Md5Update(md5, ssl->arrays->serverRandom, RAN_LEN);
+            wc_Md5Update(md5, messageVerify, verifySz);
+            wc_Md5Final(md5, hash);
+        }
+        /* sha */
+    #ifdef WOLFSSL_SMALL_STACK
+        if (doSha) {
+            sha = (Sha*)XMALLOC(sizeof(Sha), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            if (sha == NULL)
+                ERROR_OUT(MEMORY_E, done);
+        }
+    #endif
+        if (doSha) {
+            ret = wc_InitSha(sha);
+            if (ret != 0) goto done;
+            wc_ShaUpdate(sha, ssl->arrays->clientRandom, RAN_LEN);
+            wc_ShaUpdate(sha, ssl->arrays->serverRandom, RAN_LEN);
+            wc_ShaUpdate(sha, messageVerify, verifySz);
+            wc_ShaFinal(sha, hash + MD5_DIGEST_SIZE);
+        }
+#endif
+
+#ifndef NO_SHA256
+    #ifdef WOLFSSL_SMALL_STACK
+        if (doSha256) {
+            sha256 = (Sha256*)XMALLOC(sizeof(Sha256), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+            hash256 = (byte*)XMALLOC(SHA256_DIGEST_SIZE, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+            if (sha256 == NULL || hash256 == NULL)
+                ERROR_OUT(MEMORY_E, done);
+        }
+    #endif
+        if (doSha256) {
+            if (!(ret = wc_InitSha256(sha256))
+            &&  !(ret = wc_Sha256Update(sha256, ssl->arrays->clientRandom,
+                                        RAN_LEN))
+            &&  !(ret = wc_Sha256Update(sha256, ssl->arrays->serverRandom,
+                                        RAN_LEN))
+            &&  !(ret = wc_Sha256Update(sha256, messageVerify, verifySz)))
+                  ret = wc_Sha256Final(sha256, hash256);
+            if (ret != 0) goto done;
+        }
+#endif
+
+#ifdef WOLFSSL_SHA384
+    #ifdef WOLFSSL_SMALL_STACK
+        if (doSha384) {
+            sha384 = (Sha384*)XMALLOC(sizeof(Sha384), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+            hash384 = (byte*)XMALLOC(SHA384_DIGEST_SIZE, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+            if (sha384 == NULL || hash384 == NULL)
+                ERROR_OUT(MEMORY_E, done);
+        }
+    #endif
+        if (doSha384) {
+            if (!(ret = wc_InitSha384(sha384))
+            &&  !(ret = wc_Sha384Update(sha384, ssl->arrays->clientRandom,
+                                        RAN_LEN))
+            &&  !(ret = wc_Sha384Update(sha384, ssl->arrays->serverRandom,
+                                        RAN_LEN))
+            &&  !(ret = wc_Sha384Update(sha384, messageVerify, verifySz)))
+                  ret = wc_Sha384Final(sha384, hash384);
+            if (ret != 0) goto done;
+        }
+#endif
+
+#ifdef WOLFSSL_SHA512
+    #ifdef WOLFSSL_SMALL_STACK
+        if (doSha512) {
+            sha512 = (Sha512*)XMALLOC(sizeof(Sha512), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+            hash512 = (byte*)XMALLOC(SHA512_DIGEST_SIZE, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+            if (sha512 == NULL || hash512 == NULL)
+                ERROR_OUT(MEMORY_E, done);
+        }
+    #endif
+        if (doSha512) {
+            if (!(ret = wc_InitSha512(sha512))
+            &&  !(ret = wc_Sha512Update(sha512, ssl->arrays->clientRandom,
+                                        RAN_LEN))
+            &&  !(ret = wc_Sha512Update(sha512, ssl->arrays->serverRandom,
+                                        RAN_LEN))
+            &&  !(ret = wc_Sha512Update(sha512, messageVerify, verifySz)))
+                  ret = wc_Sha512Final(sha512, hash512);
+            if (ret != 0) goto done;
+        }
+#endif
+
+#ifndef NO_RSA
+        /* rsa */
+        if (sigAlgo == rsa_sa_algo)
+        {
+            byte*  out        = NULL;
+            byte   doUserRsa  = 0;
+            word32 verifiedSz = 0;
+
+            #ifdef HAVE_PK_CALLBACKS
+                if (ssl->ctx->RsaVerifyCb)
+                    doUserRsa = 1;
+            #endif /*HAVE_PK_CALLBACKS */
+
+            if (ssl->peerRsaKey == NULL || !ssl->peerRsaKeyPresent)
+                ERROR_OUT(NO_PEER_KEY, done);
+
+            if (doUserRsa) {
+            #ifdef HAVE_PK_CALLBACKS
+                verifiedSz = ssl->ctx->RsaVerifyCb(ssl,
+                                                 (byte *)input + *inOutIdx,
+                                                 length, &out,
+                                                 ssl->buffers.peerRsaKey.buffer,
+                                                 ssl->buffers.peerRsaKey.length,
+                                                 ssl->RsaVerifyCtx);
+            #endif /*HAVE_PK_CALLBACKS */
+            }
+            else
+                verifiedSz = wc_RsaSSL_VerifyInline((byte *)input + *inOutIdx,
+                                                 length, &out, ssl->peerRsaKey);
+
+            if (IsAtLeastTLSv1_2(ssl)) {
+                word32 encSigSz;
+#ifndef NO_OLD_TLS
+                byte*  digest = &hash[MD5_DIGEST_SIZE];
+                int    typeH = SHAh;
+                int    digestSz = SHA_DIGEST_SIZE;
+#else
+                byte*  digest = hash256;
+                int    typeH =  SHA256h;
+                int    digestSz = SHA256_DIGEST_SIZE;
+#endif
+#ifdef WOLFSSL_SMALL_STACK
+                byte*  encodedSig = NULL;
+#else
+                byte   encodedSig[MAX_ENCODED_SIG_SZ];
+#endif
+
+                if (hashAlgo == sha_mac) {
+                    #ifndef NO_SHA
+                        digest   = &hash[MD5_DIGEST_SIZE];
+                        typeH    = SHAh;
+                        digestSz = SHA_DIGEST_SIZE;
+                    #endif
+                }
+                else if (hashAlgo == sha256_mac) {
+                    #ifndef NO_SHA256
+                        digest   = hash256;
+                        typeH    = SHA256h;
+                        digestSz = SHA256_DIGEST_SIZE;
+                    #endif
+                }
+                else if (hashAlgo == sha384_mac) {
+                    #ifdef WOLFSSL_SHA384
+                        digest   = hash384;
+                        typeH    = SHA384h;
+                        digestSz = SHA384_DIGEST_SIZE;
+                    #endif
+                }
+                else if (hashAlgo == sha512_mac) {
+                    #ifdef WOLFSSL_SHA512
+                        digest   = hash512;
+                        typeH    = SHA512h;
+                        digestSz = SHA512_DIGEST_SIZE;
+                    #endif
+                }
+
+            #ifdef WOLFSSL_SMALL_STACK
+                encodedSig = (byte*)XMALLOC(MAX_ENCODED_SIG_SZ, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+                if (encodedSig == NULL)
+                    ERROR_OUT(MEMORY_E, done);
+            #endif
+
+                if (digest == NULL)
+                    ERROR_OUT(ALGO_ID_E, done);
+                encSigSz = wc_EncodeSignature(encodedSig, digest, digestSz,
+                                              typeH);
+                if (encSigSz != verifiedSz || !out || XMEMCMP(out, encodedSig,
+                                        min(encSigSz, MAX_ENCODED_SIG_SZ)) != 0)
+                    ret = VERIFY_SIGN_ERROR;
+
+            #ifdef WOLFSSL_SMALL_STACK
+                XFREE(encodedSig, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            #endif
+                if (ret != 0)
+                    goto done;
+            }
+            else if (verifiedSz != FINISHED_SZ || !out || XMEMCMP(out,
+                                                        hash, FINISHED_SZ) != 0)
+                ERROR_OUT(VERIFY_SIGN_ERROR, done);
+        } else
+#endif
+#ifdef HAVE_ECC
+        /* ecdsa */
+        if (sigAlgo == ecc_dsa_sa_algo) {
+            int verify = 0;
+#ifndef NO_OLD_TLS
+            byte* digest = &hash[MD5_DIGEST_SIZE];
+            word32 digestSz = SHA_DIGEST_SIZE;
+#else
+            byte* digest = hash256;
+            word32 digestSz = SHA256_DIGEST_SIZE;
+#endif
+            byte doUserEcc = 0;
+
+            #ifdef HAVE_PK_CALLBACKS
+                if (ssl->ctx->EccVerifyCb)
+                    doUserEcc = 1;
+            #endif
+
+            if (!ssl->peerEccDsaKeyPresent)
+                ERROR_OUT(NO_PEER_KEY, done);
+
+            if (IsAtLeastTLSv1_2(ssl)) {
+                if (hashAlgo == sha_mac) {
+                    #ifndef NO_SHA
+                        digest   = &hash[MD5_DIGEST_SIZE];
+                        digestSz = SHA_DIGEST_SIZE;
+                    #endif
+                }
+                else if (hashAlgo == sha256_mac) {
+                    #ifndef NO_SHA256
+                        digest   = hash256;
+                        digestSz = SHA256_DIGEST_SIZE;
+                    #endif
+                }
+                else if (hashAlgo == sha384_mac) {
+                    #ifdef WOLFSSL_SHA384
+                        digest   = hash384;
+                        digestSz = SHA384_DIGEST_SIZE;
+                    #endif
+                }
+                else if (hashAlgo == sha512_mac) {
+                    #ifdef WOLFSSL_SHA512
+                        digest   = hash512;
+                        digestSz = SHA512_DIGEST_SIZE;
+                    #endif
+                }
+            }
+            if (doUserEcc) {
+            #ifdef HAVE_PK_CALLBACKS
+                ret = ssl->ctx->EccVerifyCb(ssl, input + *inOutIdx, length,
+                                            digest, digestSz,
+                                            ssl->buffers.peerEccDsaKey.buffer,
+                                            ssl->buffers.peerEccDsaKey.length,
+                                            &verify, ssl->EccVerifyCtx);
+            #endif
+            }
+            else {
+                ret = wc_ecc_verify_hash(input + *inOutIdx, length,
+                                 digest, digestSz, &verify, ssl->peerEccDsaKey);
+            }
+            if (ret != 0 || verify == 0)
+                ERROR_OUT(VERIFY_SIGN_ERROR, done);
+        }
+        else
+#endif /* HAVE_ECC */
+            ERROR_OUT(ALGO_ID_E, done);
+
+        /* signature length */
+        *inOutIdx += length;
+
+        ssl->options.serverState = SERVER_KEYEXCHANGE_COMPLETE;
+
+    done:
+#ifdef WOLFSSL_SMALL_STACK
+    #ifndef NO_OLD_TLS
+        XFREE(md5,           NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(sha,           NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    #endif
+    #ifndef NO_SHA256
+        XFREE(sha256,        NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(hash256,       NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    #endif
+    #ifdef WOLFSSL_SHA384
+        XFREE(sha384,        NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(hash384,       NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    #endif
+    #ifdef WOLFSSL_SHA512
+        XFREE(sha512,        NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(hash512,       NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    #endif
+        XFREE(hash,          NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(messageVerify, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        if (ret != 0)
+            return ret;
+    }
+
+    if (ssl->keys.encryptionOn) {
+        *inOutIdx += ssl->keys.padSz;
+    }
+
+    return 0;
+#else  /* !NO_DH or HAVE_ECC */
+        return NOT_COMPILED_IN;  /* not supported by build */
+#endif /* !NO_DH or HAVE_ECC */
+
+        #undef ERROR_OUT
+    }
+
+
+    int SendClientKeyExchange(WOLFSSL* ssl)
+    {
+#ifdef WOLFSSL_SMALL_STACK
+        byte*  encSecret = NULL;
+#else
+        byte   encSecret[MAX_ENCRYPT_SZ];
+#endif
+        word32 encSz = 0;
+        word32 idx = 0;
+        int    ret = 0;
+        byte   doUserRsa = 0;
+
+        (void)doUserRsa;
+
+#ifdef HAVE_PK_CALLBACKS
+    #ifndef NO_RSA
+        if (ssl->ctx->RsaEncCb)
+            doUserRsa = 1;
+    #endif /* NO_RSA */
+#endif /*HAVE_PK_CALLBACKS */
+
+    #ifdef WOLFSSL_SMALL_STACK
+        encSecret = (byte*)XMALLOC(MAX_ENCRYPT_SZ, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+        if (encSecret == NULL)
+            return MEMORY_E;
+    #endif
+
+        switch (ssl->specs.kea) {
+        #ifndef NO_RSA
+            case rsa_kea:
+                ret = wc_RNG_GenerateBlock(ssl->rng, ssl->arrays->preMasterSecret,
+                                                                    SECRET_LEN);
+                if (ret != 0) {
+                #ifdef WOLFSSL_SMALL_STACK
+                    XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                #endif
+                    return ret;
+                }
+
+                ssl->arrays->preMasterSecret[0] = ssl->chVersion.major;
+                ssl->arrays->preMasterSecret[1] = ssl->chVersion.minor;
+                ssl->arrays->preMasterSz = SECRET_LEN;
+
+                if (ssl->peerRsaKey == NULL || ssl->peerRsaKeyPresent == 0) {
+                #ifdef WOLFSSL_SMALL_STACK
+                    XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                #endif
+                    return NO_PEER_KEY;
+                }
+
+                if (doUserRsa) {
+                #ifdef HAVE_PK_CALLBACKS
+                    #ifndef NO_RSA
+                        encSz = MAX_ENCRYPT_SZ;
+                        ret = ssl->ctx->RsaEncCb(ssl,
+                                            ssl->arrays->preMasterSecret,
+                                            SECRET_LEN,
+                                            encSecret, &encSz,
+                                            ssl->buffers.peerRsaKey.buffer,
+                                            ssl->buffers.peerRsaKey.length,
+                                            ssl->RsaEncCtx);
+                    #endif /* NO_RSA */
+                #endif /*HAVE_PK_CALLBACKS */
+                }
+                else {
+                    ret = wc_RsaPublicEncrypt(ssl->arrays->preMasterSecret,
+                                 SECRET_LEN, encSecret, MAX_ENCRYPT_SZ,
+                                 ssl->peerRsaKey, ssl->rng);
+                    if (ret > 0) {
+                        encSz = ret;
+                        ret = 0;   /* set success to 0 */
+                    }
+                }
+                break;
+        #endif
+        #ifndef NO_DH
+            case diffie_hellman_kea:
+                {
+                    buffer  serverP   = ssl->buffers.serverDH_P;
+                    buffer  serverG   = ssl->buffers.serverDH_G;
+                    buffer  serverPub = ssl->buffers.serverDH_Pub;
+                #ifdef WOLFSSL_SMALL_STACK
+                    byte*   priv = NULL;
+                #else
+                    byte    priv[ENCRYPT_LEN];
+                #endif
+                    word32  privSz = 0;
+                    DhKey   key;
+
+                    if (serverP.buffer == 0 || serverG.buffer == 0 ||
+                                               serverPub.buffer == 0) {
+                    #ifdef WOLFSSL_SMALL_STACK
+                        XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                    #endif
+                        return NO_PEER_KEY;
+                    }
+
+                #ifdef WOLFSSL_SMALL_STACK
+                    priv = (byte*)XMALLOC(ENCRYPT_LEN, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+                    if (priv == NULL) {
+                        XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                        return MEMORY_E;
+                    }
+                #endif
+
+                    wc_InitDhKey(&key);
+                    ret = wc_DhSetKey(&key, serverP.buffer, serverP.length,
+                                   serverG.buffer, serverG.length);
+                    if (ret == 0)
+                        /* for DH, encSecret is Yc, agree is pre-master */
+                        ret = wc_DhGenerateKeyPair(&key, ssl->rng, priv, &privSz,
+                                                encSecret, &encSz);
+                    if (ret == 0)
+                        ret = wc_DhAgree(&key, ssl->arrays->preMasterSecret,
+                                      &ssl->arrays->preMasterSz, priv, privSz,
+                                      serverPub.buffer, serverPub.length);
+                #ifdef WOLFSSL_SMALL_STACK
+                    XFREE(priv, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                #endif
+                    wc_FreeDhKey(&key);
+                }
+                break;
+        #endif /* NO_DH */
+        #ifndef NO_PSK
+            case psk_kea:
+                {
+                    byte* pms = ssl->arrays->preMasterSecret;
+
+                    ssl->arrays->psk_keySz = ssl->options.client_psk_cb(ssl,
+                        ssl->arrays->server_hint, ssl->arrays->client_identity,
+                        MAX_PSK_ID_LEN, ssl->arrays->psk_key, MAX_PSK_KEY_LEN);
+                    if (ssl->arrays->psk_keySz == 0 ||
+                        ssl->arrays->psk_keySz > MAX_PSK_KEY_LEN) {
+                    #ifdef WOLFSSL_SMALL_STACK
+                        XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                    #endif
+                        return PSK_KEY_ERROR;
+                    }
+                    encSz = (word32)XSTRLEN(ssl->arrays->client_identity);
+                    if (encSz > MAX_PSK_ID_LEN) {
+                    #ifdef WOLFSSL_SMALL_STACK
+                        XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                    #endif
+                        return CLIENT_ID_ERROR;
+                    }
+                    XMEMCPY(encSecret, ssl->arrays->client_identity, encSz);
+
+                    /* make psk pre master secret */
+                    /* length of key + length 0s + length of key + key */
+                    c16toa((word16)ssl->arrays->psk_keySz, pms);
+                    pms += 2;
+                    XMEMSET(pms, 0, ssl->arrays->psk_keySz);
+                    pms += ssl->arrays->psk_keySz;
+                    c16toa((word16)ssl->arrays->psk_keySz, pms);
+                    pms += 2;
+                    XMEMCPY(pms, ssl->arrays->psk_key, ssl->arrays->psk_keySz);
+                    ssl->arrays->preMasterSz = ssl->arrays->psk_keySz * 2 + 4;
+                    ForceZero(ssl->arrays->psk_key, ssl->arrays->psk_keySz);
+                    ssl->arrays->psk_keySz = 0; /* No further need */
+                }
+                break;
+        #endif /* NO_PSK */
+        #if !defined(NO_DH) && !defined(NO_PSK)
+            case dhe_psk_kea:
+                {
+                    byte* pms = ssl->arrays->preMasterSecret;
+                    byte* es  = encSecret;
+                    buffer  serverP   = ssl->buffers.serverDH_P;
+                    buffer  serverG   = ssl->buffers.serverDH_G;
+                    buffer  serverPub = ssl->buffers.serverDH_Pub;
+                #ifdef WOLFSSL_SMALL_STACK
+                    byte*   priv = NULL;
+                #else
+                    byte    priv[ENCRYPT_LEN];
+                #endif
+                    word32  privSz = 0;
+                    word32  pubSz = 0;
+                    word32  esSz = 0;
+                    DhKey   key;
+
+                    if (serverP.buffer == 0 || serverG.buffer == 0 ||
+                                               serverPub.buffer == 0) {
+                    #ifdef WOLFSSL_SMALL_STACK
+                        XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                    #endif
+                        return NO_PEER_KEY;
+                    }
+
+                    ssl->arrays->psk_keySz = ssl->options.client_psk_cb(ssl,
+                         ssl->arrays->server_hint, ssl->arrays->client_identity,
+                         MAX_PSK_ID_LEN, ssl->arrays->psk_key, MAX_PSK_KEY_LEN);
+                    if (ssl->arrays->psk_keySz == 0 ||
+                                     ssl->arrays->psk_keySz > MAX_PSK_KEY_LEN) {
+                    #ifdef WOLFSSL_SMALL_STACK
+                        XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                    #endif
+                        return PSK_KEY_ERROR;
+                    }
+                    esSz = (word32)XSTRLEN(ssl->arrays->client_identity);
+
+                    if (esSz > MAX_PSK_ID_LEN) {
+                    #ifdef WOLFSSL_SMALL_STACK
+                        XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                    #endif
+                        return CLIENT_ID_ERROR;
+                    }
+
+                #ifdef WOLFSSL_SMALL_STACK
+                    priv = (byte*)XMALLOC(ENCRYPT_LEN, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+                    if (priv == NULL) {
+                        XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                        return MEMORY_E;
+                    }
+                #endif
+                    c16toa((word16)esSz, es);
+                    es += OPAQUE16_LEN;
+                    XMEMCPY(es, ssl->arrays->client_identity, esSz);
+                    es += esSz;
+                    encSz = esSz + OPAQUE16_LEN;
+
+                    wc_InitDhKey(&key);
+                    ret = wc_DhSetKey(&key, serverP.buffer, serverP.length,
+                                   serverG.buffer, serverG.length);
+                    if (ret == 0)
+                        /* for DH, encSecret is Yc, agree is pre-master */
+                        ret = wc_DhGenerateKeyPair(&key, ssl->rng, priv, &privSz,
+                                                es + OPAQUE16_LEN, &pubSz);
+                    if (ret == 0)
+                        ret = wc_DhAgree(&key, pms + OPAQUE16_LEN,
+                                      &ssl->arrays->preMasterSz, priv, privSz,
+                                      serverPub.buffer, serverPub.length);
+                    wc_FreeDhKey(&key);
+                #ifdef WOLFSSL_SMALL_STACK
+                    XFREE(priv, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                #endif
+                    if (ret != 0) {
+                    #ifdef WOLFSSL_SMALL_STACK
+                        XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                    #endif
+                        return ret;
+                    }
+
+                    c16toa((word16)pubSz, es);
+                    encSz += pubSz + OPAQUE16_LEN;
+                    c16toa((word16)ssl->arrays->preMasterSz, pms);
+                    ssl->arrays->preMasterSz += OPAQUE16_LEN;
+                    pms += ssl->arrays->preMasterSz;
+
+                    /* make psk pre master secret */
+                    /* length of key + length 0s + length of key + key */
+                    c16toa((word16)ssl->arrays->psk_keySz, pms);
+                    pms += OPAQUE16_LEN;
+                    XMEMCPY(pms, ssl->arrays->psk_key, ssl->arrays->psk_keySz);
+                    ssl->arrays->preMasterSz +=
+                                          ssl->arrays->psk_keySz + OPAQUE16_LEN;
+                    ForceZero(ssl->arrays->psk_key, ssl->arrays->psk_keySz);
+                    ssl->arrays->psk_keySz = 0; /* No further need */
+                }
+                break;
+        #endif /* !NO_DH && !NO_PSK */
+        #ifdef HAVE_NTRU
+            case ntru_kea:
+                {
+                    word32 rc;
+                    word16 cipherLen = MAX_ENCRYPT_SZ;
+                    DRBG_HANDLE drbg;
+                    static uint8_t const wolfsslStr[] = {
+                        'C', 'y', 'a', 'S', 'S', 'L', ' ', 'N', 'T', 'R', 'U'
+                    };
+
+                    ret = wc_RNG_GenerateBlock(ssl->rng,
+                                      ssl->arrays->preMasterSecret, SECRET_LEN);
+                    if (ret != 0) {
+                    #ifdef WOLFSSL_SMALL_STACK
+                        XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                    #endif
+                        return ret;
+                    }
+
+                    ssl->arrays->preMasterSz = SECRET_LEN;
+
+                    if (ssl->peerNtruKeyPresent == 0) {
+                    #ifdef WOLFSSL_SMALL_STACK
+                        XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                    #endif
+                        return NO_PEER_KEY;
+                    }
+
+                    rc = ntru_crypto_drbg_instantiate(MAX_NTRU_BITS, wolfsslStr,
+                                                 sizeof(wolfsslStr), GetEntropy,
+                                                 &drbg);
+                    if (rc != DRBG_OK) {
+                    #ifdef WOLFSSL_SMALL_STACK
+                        XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                    #endif
+                        return NTRU_DRBG_ERROR;
+                    }
+
+                    rc = ntru_crypto_ntru_encrypt(drbg, ssl->peerNtruKeyLen,
+                                                  ssl->peerNtruKey,
+                                                  ssl->arrays->preMasterSz,
+                                                  ssl->arrays->preMasterSecret,
+                                                  &cipherLen, encSecret);
+                    ntru_crypto_drbg_uninstantiate(drbg);
+                    if (rc != NTRU_OK) {
+                    #ifdef WOLFSSL_SMALL_STACK
+                        XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                    #endif
+                        return NTRU_ENCRYPT_ERROR;
+                    }
+
+                    encSz = cipherLen;
+                    ret = 0;
+                }
+                break;
+        #endif /* HAVE_NTRU */
+        #ifdef HAVE_ECC
+            case ecc_diffie_hellman_kea:
+                {
+                    ecc_key  myKey;
+                    ecc_key* peerKey = NULL;
+                    word32   size = MAX_ENCRYPT_SZ;
+
+                    if (ssl->specs.static_ecdh) {
+                        /* TODO: EccDsa is really fixed Ecc change naming */
+                        if (!ssl->peerEccDsaKey || !ssl->peerEccDsaKeyPresent ||
+                                                   !ssl->peerEccDsaKey->dp) {
+                        #ifdef WOLFSSL_SMALL_STACK
+                            XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                        #endif
+                            return NO_PEER_KEY;
+                        }
+                        peerKey = ssl->peerEccDsaKey;
+                    }
+                    else {
+                        if (!ssl->peerEccKey || !ssl->peerEccKeyPresent ||
+                                                !ssl->peerEccKey->dp) {
+                        #ifdef WOLFSSL_SMALL_STACK
+                            XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                        #endif
+                            return NO_PEER_KEY;
+                        }
+                        peerKey = ssl->peerEccKey;
+                    }
+
+                    if (peerKey == NULL) {
+                    #ifdef WOLFSSL_SMALL_STACK
+                        XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                    #endif
+                        return NO_PEER_KEY;
+                    }
+
+                    wc_ecc_init(&myKey);
+                    ret = wc_ecc_make_key(ssl->rng, peerKey->dp->size, &myKey);
+                    if (ret != 0) {
+                    #ifdef WOLFSSL_SMALL_STACK
+                        XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                    #endif
+                        return ECC_MAKEKEY_ERROR;
+                    }
+
+                    /* precede export with 1 byte length */
+                    ret = wc_ecc_export_x963(&myKey, encSecret + 1, &size);
+                    encSecret[0] = (byte)size;
+                    encSz = size + 1;
+
+                    if (ret != 0)
+                        ret = ECC_EXPORT_ERROR;
+                    else {
+                        size = sizeof(ssl->arrays->preMasterSecret);
+                        ret  = wc_ecc_shared_secret(&myKey, peerKey,
+                                                 ssl->arrays->preMasterSecret, &size);
+                        if (ret != 0)
+                            ret = ECC_SHARED_ERROR;
+                    }
+
+                    ssl->arrays->preMasterSz = size;
+                    wc_ecc_free(&myKey);
+                }
+                break;
+        #endif /* HAVE_ECC */
+            default:
+            #ifdef WOLFSSL_SMALL_STACK
+                XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            #endif
+                return ALGO_ID_E; /* unsupported kea */
+        }
+
+        if (ret == 0) {
+            byte              *output;
+            int                sendSz;
+            word32             tlsSz = 0;
+
+            if (ssl->options.tls || ssl->specs.kea == diffie_hellman_kea)
+                tlsSz = 2;
+
+            if (ssl->specs.kea == ecc_diffie_hellman_kea ||
+                ssl->specs.kea == dhe_psk_kea)  /* always off */
+                tlsSz = 0;
+
+            sendSz = encSz + tlsSz + HANDSHAKE_HEADER_SZ + RECORD_HEADER_SZ;
+            idx    = HANDSHAKE_HEADER_SZ + RECORD_HEADER_SZ;
+
+            #ifdef WOLFSSL_DTLS
+                if (ssl->options.dtls) {
+                    sendSz += DTLS_HANDSHAKE_EXTRA + DTLS_RECORD_EXTRA;
+                    idx    += DTLS_HANDSHAKE_EXTRA + DTLS_RECORD_EXTRA;
+                }
+            #endif
+
+            if (ssl->keys.encryptionOn)
+                sendSz += MAX_MSG_EXTRA;
+
+            /* check for available size */
+            if ((ret = CheckAvailableSize(ssl, sendSz)) != 0) {
+            #ifdef WOLFSSL_SMALL_STACK
+                XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            #endif
+                return ret;
+            }
+
+            /* get ouput buffer */
+            output = ssl->buffers.outputBuffer.buffer +
+                     ssl->buffers.outputBuffer.length;
+
+            AddHeaders(output, encSz + tlsSz, client_key_exchange, ssl);
+
+            if (tlsSz) {
+                c16toa((word16)encSz, &output[idx]);
+                idx += 2;
+            }
+            XMEMCPY(output + idx, encSecret, encSz);
+            idx += encSz;
+
+            if (ssl->keys.encryptionOn) {
+                byte* input;
+                int   inputSz = idx-RECORD_HEADER_SZ; /* buildmsg adds rechdr */
+
+                input = (byte*)XMALLOC(inputSz, ssl->heap,
+                                       DYNAMIC_TYPE_TMP_BUFFER);
+                if (input == NULL) {
+                #ifdef WOLFSSL_SMALL_STACK
+                    XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                #endif
+                    return MEMORY_E;
+                }
+
+                XMEMCPY(input, output + RECORD_HEADER_SZ, inputSz);
+                sendSz = BuildMessage(ssl, output, sendSz, input, inputSz,
+                                      handshake);
+                XFREE(input, ssl->heap, DYNAMIC_TYPE_TMP_BUFFER);
+                if (sendSz < 0) {
+                #ifdef WOLFSSL_SMALL_STACK
+                    XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                #endif
+                    return sendSz;
+                }
+            } else {
+                ret = HashOutput(ssl, output, sendSz, 0);
+                if (ret != 0) {
+                #ifdef WOLFSSL_SMALL_STACK
+                    XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                #endif
+                    return ret;
+                }
+            }
+
+            #ifdef WOLFSSL_DTLS
+                if (ssl->options.dtls) {
+                    if ((ret = DtlsPoolSave(ssl, output, sendSz)) != 0) {
+                    #ifdef WOLFSSL_SMALL_STACK
+                        XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                    #endif
+                        return ret;
+                    }
+                }
+            #endif
+
+            #ifdef WOLFSSL_CALLBACKS
+                if (ssl->hsInfoOn)
+                    AddPacketName("ClientKeyExchange", &ssl->handShakeInfo);
+                if (ssl->toInfoOn)
+                    AddPacketInfo("ClientKeyExchange", &ssl->timeoutInfo,
+                                  output, sendSz, ssl->heap);
+            #endif
+
+            ssl->buffers.outputBuffer.length += sendSz;
+
+            if (ssl->options.groupMessages)
+                ret = 0;
+            else
+                ret = SendBuffered(ssl);
+        }
+
+    #ifdef WOLFSSL_SMALL_STACK
+        XFREE(encSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    #endif
+
+        if (ret == 0 || ret == WANT_WRITE) {
+            int tmpRet = MakeMasterSecret(ssl);
+            if (tmpRet != 0)
+                ret = tmpRet;   /* save WANT_WRITE unless more serious */
+            ssl->options.clientState = CLIENT_KEYEXCHANGE_COMPLETE;
+        }
+        /* No further need for PMS */
+        ForceZero(ssl->arrays->preMasterSecret, ssl->arrays->preMasterSz);
+        ssl->arrays->preMasterSz = 0;
+
+        return ret;
+    }
+
+#ifndef NO_CERTS
+    int SendCertificateVerify(WOLFSSL* ssl)
+    {
+        byte              *output;
+        int                sendSz = MAX_CERT_VERIFY_SZ, length, ret;
+        word32             idx = 0;
+        word32             sigOutSz = 0;
+#ifndef NO_RSA
+        RsaKey             key;
+        int                initRsaKey = 0;
+#endif
+        int                usingEcc = 0;
+#ifdef HAVE_ECC
+        ecc_key            eccKey;
+#endif
+
+        (void)idx;
+
+        if (ssl->options.sendVerify == SEND_BLANK_CERT)
+            return 0;  /* sent blank cert, can't verify */
+
+        if (ssl->keys.encryptionOn)
+            sendSz += MAX_MSG_EXTRA;
+
+        /* check for available size */
+        if ((ret = CheckAvailableSize(ssl, sendSz)) != 0)
+            return ret;
+
+        /* get ouput buffer */
+        output = ssl->buffers.outputBuffer.buffer +
+                 ssl->buffers.outputBuffer.length;
+
+        ret = BuildCertHashes(ssl, &ssl->hsHashes->certHashes);
+        if (ret != 0)
+            return ret;
+
+#ifdef HAVE_ECC
+        wc_ecc_init(&eccKey);
+#endif
+#ifndef NO_RSA
+        ret = wc_InitRsaKey(&key, ssl->heap);
+        if (ret == 0) initRsaKey = 1;
+        if (ret == 0)
+            ret = wc_RsaPrivateKeyDecode(ssl->buffers.key.buffer, &idx, &key,
+                                      ssl->buffers.key.length);
+        if (ret == 0)
+            sigOutSz = wc_RsaEncryptSize(&key);
+        else
+#endif
+        {
+    #ifdef HAVE_ECC
+            WOLFSSL_MSG("Trying ECC client cert, RSA didn't work");
+
+            idx = 0;
+            ret = wc_EccPrivateKeyDecode(ssl->buffers.key.buffer, &idx, &eccKey,
+                                      ssl->buffers.key.length);
+            if (ret == 0) {
+                WOLFSSL_MSG("Using ECC client cert");
+                usingEcc = 1;
+                sigOutSz = MAX_ENCODED_SIG_SZ;
+            }
+            else {
+                WOLFSSL_MSG("Bad client cert type");
+            }
+    #endif
+        }
+        if (ret == 0) {
+            byte*  verify = (byte*)&output[RECORD_HEADER_SZ +
+                                           HANDSHAKE_HEADER_SZ];
+#ifndef NO_OLD_TLS
+            byte*  signBuffer = ssl->hsHashes->certHashes.md5;
+#else
+            byte*  signBuffer = NULL;
+#endif
+            word32 signSz = FINISHED_SZ;
+            word32 extraSz = 0;  /* tls 1.2 hash/sig */
+#ifdef WOLFSSL_SMALL_STACK
+            byte*  encodedSig = NULL;
+#else
+            byte   encodedSig[MAX_ENCODED_SIG_SZ];
+#endif
+
+#ifdef WOLFSSL_SMALL_STACK
+            encodedSig = (byte*)XMALLOC(MAX_ENCODED_SIG_SZ, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+            if (encodedSig == NULL) {
+            #ifndef NO_RSA
+                if (initRsaKey)
+                    wc_FreeRsaKey(&key);
+            #endif
+            #ifdef HAVE_ECC
+                wc_ecc_free(&eccKey);
+            #endif
+                return MEMORY_E;
+            }
+#endif
+
+            (void)encodedSig;
+            (void)signSz;
+            (void)signBuffer;
+
+            #ifdef WOLFSSL_DTLS
+                if (ssl->options.dtls)
+                    verify += DTLS_RECORD_EXTRA + DTLS_HANDSHAKE_EXTRA;
+            #endif
+            length = sigOutSz;
+            if (IsAtLeastTLSv1_2(ssl)) {
+                verify[0] = ssl->suites->hashAlgo;
+                verify[1] = usingEcc ? ecc_dsa_sa_algo : rsa_sa_algo;
+                extraSz = HASH_SIG_SIZE;
+            }
+
+            if (usingEcc) {
+#ifdef HAVE_ECC
+                word32 localSz = MAX_ENCODED_SIG_SZ;
+                word32 digestSz;
+                byte*  digest;
+                byte   doUserEcc = 0;
+#ifndef NO_OLD_TLS
+                /* old tls default */
+                digestSz = SHA_DIGEST_SIZE;
+                digest   = ssl->hsHashes->certHashes.sha;
+#else
+                /* new tls default */
+                digestSz = SHA256_DIGEST_SIZE;
+                digest   = ssl->hsHashes->certHashes.sha256;
+#endif
+
+                #ifdef HAVE_PK_CALLBACKS
+                    #ifdef HAVE_ECC
+                        if (ssl->ctx->EccSignCb)
+                            doUserEcc = 1;
+                    #endif /* HAVE_ECC */
+                #endif /*HAVE_PK_CALLBACKS */
+
+                if (IsAtLeastTLSv1_2(ssl)) {
+                    if (ssl->suites->hashAlgo == sha_mac) {
+                        #ifndef NO_SHA
+                            digest = ssl->hsHashes->certHashes.sha;
+                            digestSz = SHA_DIGEST_SIZE;
+                        #endif
+                    }
+                    else if (ssl->suites->hashAlgo == sha256_mac) {
+                        #ifndef NO_SHA256
+                            digest = ssl->hsHashes->certHashes.sha256;
+                            digestSz = SHA256_DIGEST_SIZE;
+                        #endif
+                    }
+                    else if (ssl->suites->hashAlgo == sha384_mac) {
+                        #ifdef WOLFSSL_SHA384
+                            digest = ssl->hsHashes->certHashes.sha384;
+                            digestSz = SHA384_DIGEST_SIZE;
+                        #endif
+                    }
+                    else if (ssl->suites->hashAlgo == sha512_mac) {
+                        #ifdef WOLFSSL_SHA512
+                            digest = ssl->hsHashes->certHashes.sha512;
+                            digestSz = SHA512_DIGEST_SIZE;
+                        #endif
+                    }
+                }
+
+                if (doUserEcc) {
+                #ifdef HAVE_PK_CALLBACKS
+                    #ifdef HAVE_ECC
+                        ret = ssl->ctx->EccSignCb(ssl, digest, digestSz,
+                                        encodedSig, &localSz,
+                                        ssl->buffers.key.buffer,
+                                        ssl->buffers.key.length,
+                                        ssl->EccSignCtx);
+                    #endif /* HAVE_ECC */
+                #endif /*HAVE_PK_CALLBACKS */
+                }
+                else {
+                    ret = wc_ecc_sign_hash(digest, digestSz, encodedSig,
+                                        &localSz, ssl->rng, &eccKey);
+                }
+                if (ret == 0) {
+                    length = localSz;
+                    c16toa((word16)length, verify + extraSz); /* prepend hdr */
+                    XMEMCPY(verify + extraSz + VERIFY_HEADER,encodedSig,length);
+                }
+#endif
+            }
+#ifndef NO_RSA
+            else {
+                byte doUserRsa = 0;
+
+                #ifdef HAVE_PK_CALLBACKS
+                    if (ssl->ctx->RsaSignCb)
+                        doUserRsa = 1;
+                #endif /*HAVE_PK_CALLBACKS */
+
+                if (IsAtLeastTLSv1_2(ssl)) {
+                    /*
+                     * MSVC Compiler complains because it can not
+                     * guarantee any of the conditionals will succeed in
+                     * assigning a value before wc_EncodeSignature executes.
+                     */
+                    byte* digest    = NULL;
+                    int   digestSz  = 0;
+                    int   typeH     = 0;
+                    int   didSet    = 0;
+
+                    if (ssl->suites->hashAlgo == sha_mac) {
+                        #ifndef NO_SHA
+                            digest   = ssl->hsHashes->certHashes.sha;
+                            typeH    = SHAh;
+                            digestSz = SHA_DIGEST_SIZE;
+                            didSet   = 1;
+                        #endif
+                    }
+                    else if (ssl->suites->hashAlgo == sha256_mac) {
+                        #ifndef NO_SHA256
+                            digest   = ssl->hsHashes->certHashes.sha256;
+                            typeH    = SHA256h;
+                            digestSz = SHA256_DIGEST_SIZE;
+                            didSet   = 1;
+                        #endif
+                    }
+                    else if (ssl->suites->hashAlgo == sha384_mac) {
+                        #ifdef WOLFSSL_SHA384
+                            digest   = ssl->hsHashes->certHashes.sha384;
+                            typeH    = SHA384h;
+                            digestSz = SHA384_DIGEST_SIZE;
+                            didSet   = 1;
+                        #endif
+                    }
+                    else if (ssl->suites->hashAlgo == sha512_mac) {
+                        #ifdef WOLFSSL_SHA512
+                            digest   = ssl->hsHashes->certHashes.sha512;
+                            typeH    = SHA512h;
+                            digestSz = SHA512_DIGEST_SIZE;
+                            didSet   = 1;
+                        #endif
+                    }
+
+                    if (didSet == 0) {
+                        /* defaults */
+                        #ifndef NO_OLD_TLS
+                            digest = ssl->hsHashes->certHashes.sha;
+                            digestSz = SHA_DIGEST_SIZE;
+                            typeH = SHAh;
+                        #else
+                            digest = ssl->hsHashes->certHashes.sha256;
+                            digestSz = SHA256_DIGEST_SIZE;
+                            typeH = SHA256h;
+                        #endif
+                    }
+
+                    signSz = wc_EncodeSignature(encodedSig, digest,digestSz,typeH);
+                    signBuffer = encodedSig;
+                }
+
+                c16toa((word16)length, verify + extraSz); /* prepend hdr */
+                if (doUserRsa) {
+                #ifdef HAVE_PK_CALLBACKS
+                    #ifndef NO_RSA
+                        word32 ioLen = ENCRYPT_LEN;
+                        ret = ssl->ctx->RsaSignCb(ssl, signBuffer, signSz,
+                                            verify + extraSz + VERIFY_HEADER,
+                                            &ioLen,
+                                            ssl->buffers.key.buffer,
+                                            ssl->buffers.key.length,
+                                            ssl->RsaSignCtx);
+                    #endif /* NO_RSA */
+                #endif /*HAVE_PK_CALLBACKS */
+                }
+                else {
+                    ret = wc_RsaSSL_Sign(signBuffer, signSz, verify + extraSz +
+                                  VERIFY_HEADER, ENCRYPT_LEN, &key, ssl->rng);
+                }
+
+                if (ret > 0)
+                    ret = 0;  /* RSA reset */
+            }
+#endif
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(encodedSig, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+            if (ret == 0) {
+                AddHeaders(output, length + extraSz + VERIFY_HEADER,
+                           certificate_verify, ssl);
+
+                sendSz = RECORD_HEADER_SZ + HANDSHAKE_HEADER_SZ + length +
+                         extraSz + VERIFY_HEADER;
+
+                #ifdef WOLFSSL_DTLS
+                    if (ssl->options.dtls) {
+                        sendSz += DTLS_RECORD_EXTRA + DTLS_HANDSHAKE_EXTRA;
+                    }
+                #endif
+
+                if (ssl->keys.encryptionOn) {
+                    byte* input;
+                    int   inputSz = sendSz - RECORD_HEADER_SZ;
+                                    /* build msg adds rec hdr */
+                    input = (byte*)XMALLOC(inputSz, ssl->heap,
+                                           DYNAMIC_TYPE_TMP_BUFFER);
+                    if (input == NULL)
+                        ret = MEMORY_E;
+                    else {
+                        XMEMCPY(input, output + RECORD_HEADER_SZ, inputSz);
+                        sendSz = BuildMessage(ssl, output,
+                                              MAX_CERT_VERIFY_SZ +MAX_MSG_EXTRA,
+                                              input, inputSz, handshake);
+                        XFREE(input, ssl->heap, DYNAMIC_TYPE_TMP_BUFFER);
+
+                        if (sendSz < 0)
+                            ret = sendSz;
+                    }
+                } else {
+                    ret = HashOutput(ssl, output, sendSz, 0);
+                }
+
+                #ifdef WOLFSSL_DTLS
+                    if (ssl->options.dtls) {
+                        if ((ret = DtlsPoolSave(ssl, output, sendSz)) != 0)
+                            return ret;
+                    }
+                #endif
+            }
+        }
+#ifndef NO_RSA
+        if (initRsaKey)
+            wc_FreeRsaKey(&key);
+#endif
+#ifdef HAVE_ECC
+        wc_ecc_free(&eccKey);
+#endif
+
+        if (ret == 0) {
+            #ifdef WOLFSSL_CALLBACKS
+                if (ssl->hsInfoOn)
+                    AddPacketName("CertificateVerify", &ssl->handShakeInfo);
+                if (ssl->toInfoOn)
+                    AddPacketInfo("CertificateVerify", &ssl->timeoutInfo,
+                                  output, sendSz, ssl->heap);
+            #endif
+            ssl->buffers.outputBuffer.length += sendSz;
+            if (ssl->options.groupMessages)
+                return 0;
+            else
+                return SendBuffered(ssl);
+        }
+        else
+            return ret;
+    }
+#endif /* NO_CERTS */
+
+#ifdef HAVE_SESSION_TICKET
+int DoSessionTicket(WOLFSSL* ssl,
+                               const byte* input, word32* inOutIdx, word32 size)
+{
+    word32 begin = *inOutIdx;
+    word32 lifetime;
+    word16 length;
+
+    if (ssl->expect_session_ticket == 0) {
+        WOLFSSL_MSG("Unexpected session ticket");
+        return SESSION_TICKET_EXPECT_E;
+    }
+
+    if ((*inOutIdx - begin) + OPAQUE32_LEN > size)
+        return BUFFER_ERROR;
+
+    ato32(input + *inOutIdx, &lifetime);
+    *inOutIdx += OPAQUE32_LEN;
+
+    if ((*inOutIdx - begin) + OPAQUE16_LEN > size)
+        return BUFFER_ERROR;
+
+    ato16(input + *inOutIdx, &length);
+    *inOutIdx += OPAQUE16_LEN;
+
+    if (length > sizeof(ssl->session.ticket))
+        return SESSION_TICKET_LEN_E;
+
+    if ((*inOutIdx - begin) + length > size)
+        return BUFFER_ERROR;
+
+    /* If the received ticket including its length is greater than
+     * a length value, the save it. Otherwise, don't save it. */
+    if (length > 0) {
+        XMEMCPY(ssl->session.ticket, input + *inOutIdx, length);
+        *inOutIdx += length;
+        ssl->session.ticketLen = length;
+        ssl->timeout = lifetime;
+        if (ssl->session_ticket_cb != NULL) {
+            ssl->session_ticket_cb(ssl,
+                                   ssl->session.ticket, ssl->session.ticketLen,
+                                   ssl->session_ticket_ctx);
+        }
+        /* Create a fake sessionID based on the ticket, this will
+         * supercede the existing session cache info. */
+        ssl->options.haveSessionId = 1;
+        XMEMCPY(ssl->arrays->sessionID,
+                                 ssl->session.ticket + length - ID_LEN, ID_LEN);
+#ifndef NO_SESSION_CACHE
+        AddSession(ssl);
+#endif
+
+    }
+    else {
+        ssl->session.ticketLen = 0;
+    }
+
+    if (ssl->keys.encryptionOn) {
+        *inOutIdx += ssl->keys.padSz;
+    }
+
+    ssl->expect_session_ticket = 0;
+
+    return 0;
+}
+#endif /* HAVE_SESSION_TICKET */
+
+#endif /* NO_WOLFSSL_CLIENT */
+
+
+#ifndef NO_WOLFSSL_SERVER
+
+    int SendServerHello(WOLFSSL* ssl)
+    {
+        byte              *output;
+        word32             length, idx = RECORD_HEADER_SZ + HANDSHAKE_HEADER_SZ;
+        int                sendSz;
+        int                ret;
+        byte               sessIdSz = ID_LEN;
+
+        length = VERSION_SZ + RAN_LEN
+               + ID_LEN + ENUM_LEN
+               + SUITE_LEN
+               + ENUM_LEN;
+
+#ifdef HAVE_TLS_EXTENSIONS
+        length += TLSX_GetResponseSize(ssl);
+
+    #ifdef HAVE_SESSION_TICKET
+        if (ssl->options.useTicket && ssl->arrays->sessionIDSz == 0) {
+            /* no session id */
+            length  -= ID_LEN;
+            sessIdSz = 0;
+        }
+    #endif /* HAVE_SESSION_TICKET */
+#endif
+
+        /* check for avalaible size */
+        if ((ret = CheckAvailableSize(ssl, MAX_HELLO_SZ)) != 0)
+            return ret;
+
+        /* get ouput buffer */
+        output = ssl->buffers.outputBuffer.buffer +
+                 ssl->buffers.outputBuffer.length;
+
+        sendSz = length + HANDSHAKE_HEADER_SZ + RECORD_HEADER_SZ;
+        AddHeaders(output, length, server_hello, ssl);
+
+        #ifdef WOLFSSL_DTLS
+            if (ssl->options.dtls) {
+                idx    += DTLS_RECORD_EXTRA + DTLS_HANDSHAKE_EXTRA;
+                sendSz += DTLS_RECORD_EXTRA + DTLS_HANDSHAKE_EXTRA;
+            }
+        #endif
+        /* now write to output */
+            /* first version */
+        output[idx++] = ssl->version.major;
+        output[idx++] = ssl->version.minor;
+
+            /* then random */
+        if (!ssl->options.resuming) {
+            ret = wc_RNG_GenerateBlock(ssl->rng, ssl->arrays->serverRandom,
+                                                                       RAN_LEN);
+            if (ret != 0)
+                return ret;
+        }
+
+        XMEMCPY(output + idx, ssl->arrays->serverRandom, RAN_LEN);
+        idx += RAN_LEN;
+
+#ifdef SHOW_SECRETS
+        {
+            int j;
+            printf("server random: ");
+            for (j = 0; j < RAN_LEN; j++)
+                printf("%02x", ssl->arrays->serverRandom[j]);
+            printf("\n");
+        }
+#endif
+            /* then session id */
+        output[idx++] = sessIdSz;
+        if (sessIdSz) {
+
+            if (!ssl->options.resuming) {
+                ret = wc_RNG_GenerateBlock(ssl->rng, ssl->arrays->sessionID,
+                                           sessIdSz);
+                if (ret != 0) return ret;
+            }
+
+            XMEMCPY(output + idx, ssl->arrays->sessionID, sessIdSz);
+            idx += sessIdSz;
+        }
+
+            /* then cipher suite */
+        output[idx++] = ssl->options.cipherSuite0;
+        output[idx++] = ssl->options.cipherSuite;
+
+            /* then compression */
+        if (ssl->options.usingCompression)
+            output[idx++] = ZLIB_COMPRESSION;
+        else
+            output[idx++] = NO_COMPRESSION;
+
+            /* last, extensions */
+#ifdef HAVE_TLS_EXTENSIONS
+        TLSX_WriteResponse(ssl, output + idx);
+#endif
+
+        ssl->buffers.outputBuffer.length += sendSz;
+        #ifdef WOLFSSL_DTLS
+            if (ssl->options.dtls) {
+                if ((ret = DtlsPoolSave(ssl, output, sendSz)) != 0)
+                    return ret;
+            }
+        #endif
+
+        ret = HashOutput(ssl, output, sendSz, 0);
+        if (ret != 0)
+            return ret;
+
+        #ifdef WOLFSSL_CALLBACKS
+            if (ssl->hsInfoOn)
+                AddPacketName("ServerHello", &ssl->handShakeInfo);
+            if (ssl->toInfoOn)
+                AddPacketInfo("ServerHello", &ssl->timeoutInfo, output, sendSz,
+                              ssl->heap);
+        #endif
+
+        ssl->options.serverState = SERVER_HELLO_COMPLETE;
+
+        if (ssl->options.groupMessages)
+            return 0;
+        else
+            return SendBuffered(ssl);
+    }
+
+
+#ifdef HAVE_ECC
+
+    static byte SetCurveId(int size)
+    {
+        switch(size) {
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC160)
+            case 20:
+                return WOLFSSL_ECC_SECP160R1;
+#endif
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC192)
+            case 24:
+                return WOLFSSL_ECC_SECP192R1;
+#endif
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC224)
+            case 28:
+                return WOLFSSL_ECC_SECP224R1;
+#endif
+#if defined(HAVE_ALL_CURVES) || !defined(NO_ECC256)
+            case 32:
+                return WOLFSSL_ECC_SECP256R1;
+#endif
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC384)
+            case 48:
+                return WOLFSSL_ECC_SECP384R1;
+#endif
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC521)
+            case 66:
+                return WOLFSSL_ECC_SECP521R1;
+#endif
+            default:
+                return 0;
+        }
+    }
+
+#endif /* HAVE_ECC */
+
+
+    int SendServerKeyExchange(WOLFSSL* ssl)
+    {
+        int ret = 0;
+        (void)ssl;
+        #define ERROR_OUT(err, eLabel) do { ret = err; goto eLabel; } while(0)
+
+    #ifndef NO_PSK
+        if (ssl->specs.kea == psk_kea)
+        {
+            byte    *output;
+            word32   length, idx = RECORD_HEADER_SZ + HANDSHAKE_HEADER_SZ;
+            int      sendSz;
+            if (ssl->arrays->server_hint[0] == 0) return 0; /* don't send */
+
+            /* include size part */
+            length = (word32)XSTRLEN(ssl->arrays->server_hint);
+            if (length > MAX_PSK_ID_LEN)
+                return SERVER_HINT_ERROR;
+
+            length += HINT_LEN_SZ;
+            sendSz = length + HANDSHAKE_HEADER_SZ + RECORD_HEADER_SZ;
+
+        #ifdef WOLFSSL_DTLS
+            if (ssl->options.dtls) {
+                sendSz += DTLS_RECORD_EXTRA + DTLS_HANDSHAKE_EXTRA;
+                idx    += DTLS_RECORD_EXTRA + DTLS_HANDSHAKE_EXTRA;
+            }
+        #endif
+            /* check for available size */
+            if ((ret = CheckAvailableSize(ssl, sendSz)) != 0)
+               return ret;
+
+            /* get ouput buffer */
+            output = ssl->buffers.outputBuffer.buffer +
+                     ssl->buffers.outputBuffer.length;
+
+            AddHeaders(output, length, server_key_exchange, ssl);
+
+            /* key data */
+            c16toa((word16)(length - HINT_LEN_SZ), output + idx);
+            idx += HINT_LEN_SZ;
+            XMEMCPY(output + idx, ssl->arrays->server_hint,length -HINT_LEN_SZ);
+
+        #ifdef WOLFSSL_DTLS
+            if (ssl->options.dtls)
+                if ((ret = DtlsPoolSave(ssl, output, sendSz)) != 0)
+                    return ret;
+        #endif
+
+            ret = HashOutput(ssl, output, sendSz, 0);
+            if (ret != 0)
+                return ret;
+
+        #ifdef WOLFSSL_CALLBACKS
+            if (ssl->hsInfoOn)
+                AddPacketName("ServerKeyExchange", &ssl->handShakeInfo);
+            if (ssl->toInfoOn)
+                AddPacketInfo("ServerKeyExchange", &ssl->timeoutInfo, output,
+                                                             sendSz, ssl->heap);
+        #endif
+
+            ssl->buffers.outputBuffer.length += sendSz;
+            if (ssl->options.groupMessages)
+                ret = 0;
+            else
+                ret = SendBuffered(ssl);
+            ssl->options.serverState = SERVER_KEYEXCHANGE_COMPLETE;
+        }
+    #endif /*NO_PSK */
+
+    #if !defined(NO_DH) && !defined(NO_PSK)
+        if (ssl->specs.kea == dhe_psk_kea) {
+            byte    *output;
+            word32   length, idx = RECORD_HEADER_SZ + HANDSHAKE_HEADER_SZ;
+            word32   hintLen;
+            int      sendSz;
+            DhKey    dhKey;
+
+            if (ssl->buffers.serverDH_P.buffer == NULL ||
+                ssl->buffers.serverDH_G.buffer == NULL)
+                return NO_DH_PARAMS;
+
+            if (ssl->buffers.serverDH_Pub.buffer == NULL) {
+                ssl->buffers.serverDH_Pub.buffer = (byte*)XMALLOC(
+                        ssl->buffers.serverDH_P.length + 2, ssl->ctx->heap,
+                        DYNAMIC_TYPE_DH);
+                if (ssl->buffers.serverDH_Pub.buffer == NULL)
+                    return MEMORY_E;
+            }
+
+            if (ssl->buffers.serverDH_Priv.buffer == NULL) {
+                ssl->buffers.serverDH_Priv.buffer = (byte*)XMALLOC(
+                        ssl->buffers.serverDH_P.length + 2, ssl->ctx->heap,
+                        DYNAMIC_TYPE_DH);
+                if (ssl->buffers.serverDH_Priv.buffer == NULL)
+                    return MEMORY_E;
+            }
+
+            wc_InitDhKey(&dhKey);
+            ret = wc_DhSetKey(&dhKey, ssl->buffers.serverDH_P.buffer,
+                                   ssl->buffers.serverDH_P.length,
+                                   ssl->buffers.serverDH_G.buffer,
+                                   ssl->buffers.serverDH_G.length);
+            if (ret == 0)
+                ret = wc_DhGenerateKeyPair(&dhKey, ssl->rng,
+                                         ssl->buffers.serverDH_Priv.buffer,
+                                        &ssl->buffers.serverDH_Priv.length,
+                                         ssl->buffers.serverDH_Pub.buffer,
+                                        &ssl->buffers.serverDH_Pub.length);
+            wc_FreeDhKey(&dhKey);
+            if (ret != 0)
+                return ret;
+
+            length = LENGTH_SZ * 3 + /* p, g, pub */
+                     ssl->buffers.serverDH_P.length +
+                     ssl->buffers.serverDH_G.length +
+                     ssl->buffers.serverDH_Pub.length;
+
+            /* include size part */
+            hintLen = (word32)XSTRLEN(ssl->arrays->server_hint);
+            if (hintLen > MAX_PSK_ID_LEN)
+                return SERVER_HINT_ERROR;
+            length += hintLen + HINT_LEN_SZ;
+            sendSz = length + HANDSHAKE_HEADER_SZ + RECORD_HEADER_SZ;
+
+        #ifdef WOLFSSL_DTLS
+            if (ssl->options.dtls) {
+                sendSz += DTLS_RECORD_EXTRA + DTLS_HANDSHAKE_EXTRA;
+                idx    += DTLS_RECORD_EXTRA + DTLS_HANDSHAKE_EXTRA;
+            }
+        #endif
+
+            /* check for available size */
+            if ((ret = CheckAvailableSize(ssl, sendSz)) != 0)
+               return ret;
+
+            /* get ouput buffer */
+            output = ssl->buffers.outputBuffer.buffer +
+                     ssl->buffers.outputBuffer.length;
+
+            AddHeaders(output, length, server_key_exchange, ssl);
+
+            /* key data */
+            c16toa((word16)hintLen, output + idx);
+            idx += HINT_LEN_SZ;
+            XMEMCPY(output + idx, ssl->arrays->server_hint, hintLen);
+            idx += hintLen;
+
+            /* add p, g, pub */
+            c16toa((word16)ssl->buffers.serverDH_P.length, output + idx);
+            idx += LENGTH_SZ;
+            XMEMCPY(output + idx, ssl->buffers.serverDH_P.buffer,
+                                  ssl->buffers.serverDH_P.length);
+            idx += ssl->buffers.serverDH_P.length;
+
+            /*  g */
+            c16toa((word16)ssl->buffers.serverDH_G.length, output + idx);
+            idx += LENGTH_SZ;
+            XMEMCPY(output + idx, ssl->buffers.serverDH_G.buffer,
+                                  ssl->buffers.serverDH_G.length);
+            idx += ssl->buffers.serverDH_G.length;
+
+            /*  pub */
+            c16toa((word16)ssl->buffers.serverDH_Pub.length, output + idx);
+            idx += LENGTH_SZ;
+            XMEMCPY(output + idx, ssl->buffers.serverDH_Pub.buffer,
+                                  ssl->buffers.serverDH_Pub.length);
+            idx += ssl->buffers.serverDH_Pub.length;
+            (void)idx; /* suppress analyzer warning, and keep idx current */
+
+        #ifdef WOLFSSL_DTLS
+            if (ssl->options.dtls)
+                if ((ret = DtlsPoolSave(ssl, output, sendSz)) != 0)
+                    return ret;
+        #endif
+
+            ret = HashOutput(ssl, output, sendSz, 0);
+
+            if (ret != 0)
+                return ret;
+
+        #ifdef WOLFSSL_CALLBACKS
+            if (ssl->hsInfoOn)
+                AddPacketName("ServerKeyExchange", &ssl->handShakeInfo);
+            if (ssl->toInfoOn)
+                AddPacketInfo("ServerKeyExchange", &ssl->timeoutInfo, output,
+                                                             sendSz, ssl->heap);
+        #endif
+
+            ssl->buffers.outputBuffer.length += sendSz;
+            if (ssl->options.groupMessages)
+                ret = 0;
+            else
+                ret = SendBuffered(ssl);
+            ssl->options.serverState = SERVER_KEYEXCHANGE_COMPLETE;
+        }
+    #endif /* !NO_DH && !NO_PSK */
+
+    #ifdef HAVE_ECC
+        if (ssl->specs.kea == ecc_diffie_hellman_kea)
+        {
+            byte    *output;
+            word32   length, idx = RECORD_HEADER_SZ + HANDSHAKE_HEADER_SZ;
+            int      sendSz;
+            word32   sigSz;
+            word32   preSigSz, preSigIdx;
+        #ifndef NO_RSA
+            RsaKey   rsaKey;
+        #endif
+            ecc_key  dsaKey;
+        #ifdef WOLFSSL_SMALL_STACK
+            byte*    exportBuf = NULL;
+        #else
+            byte     exportBuf[MAX_EXPORT_ECC_SZ];
+        #endif
+            word32   expSz = MAX_EXPORT_ECC_SZ;
+
+        #ifndef NO_OLD_TLS
+            byte doMd5 = 0;
+            byte doSha = 0;
+        #endif
+        #ifndef NO_SHA256
+            byte doSha256 = 0;
+        #endif
+        #ifdef WOLFSSL_SHA384
+            byte doSha384 = 0;
+        #endif
+        #ifdef WOLFSSL_SHA512
+            byte doSha512 = 0;
+        #endif
+
+            if (ssl->specs.static_ecdh) {
+                WOLFSSL_MSG("Using Static ECDH, not sending ServerKeyExchagne");
+                return 0;
+            }
+
+            /* curve type, named curve, length(1) */
+            length = ENUM_LEN + CURVE_LEN + ENUM_LEN;
+            /* pub key size */
+            WOLFSSL_MSG("Using ephemeral ECDH");
+
+            /* need ephemeral key now, create it if missing */
+            if (ssl->eccTempKey == NULL) {
+                /* alloc/init on demand */
+                ssl->eccTempKey = (ecc_key*)XMALLOC(sizeof(ecc_key),
+                                              ssl->ctx->heap, DYNAMIC_TYPE_ECC);
+                if (ssl->eccTempKey == NULL) {
+                    WOLFSSL_MSG("EccTempKey Memory error");
+                    return MEMORY_E;
+                }
+                wc_ecc_init(ssl->eccTempKey);
+            }
+            if (ssl->eccTempKeyPresent == 0) {
+                if (wc_ecc_make_key(ssl->rng, ssl->eccTempKeySz,
+                                 ssl->eccTempKey) != 0) {
+                    return ECC_MAKEKEY_ERROR;
+                }
+                ssl->eccTempKeyPresent = 1;
+            }
+
+        #ifdef WOLFSSL_SMALL_STACK
+            exportBuf = (byte*)XMALLOC(MAX_EXPORT_ECC_SZ, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+            if (exportBuf == NULL)
+                return MEMORY_E;
+        #endif
+
+            if (wc_ecc_export_x963(ssl->eccTempKey, exportBuf, &expSz) != 0)
+                ERROR_OUT(ECC_EXPORT_ERROR, done_a);
+            length += expSz;
+
+            preSigSz  = length;
+            preSigIdx = idx;
+
+        #ifndef NO_RSA
+            ret = wc_InitRsaKey(&rsaKey, ssl->heap);
+            if (ret != 0)
+                goto done_a;
+        #endif
+
+            wc_ecc_init(&dsaKey);
+
+            /* sig length */
+            length += LENGTH_SZ;
+
+            if (!ssl->buffers.key.buffer) {
+            #ifndef NO_RSA
+                wc_FreeRsaKey(&rsaKey);
+            #endif
+                wc_ecc_free(&dsaKey);
+                ERROR_OUT(NO_PRIVATE_KEY, done_a);
+            }
+
+        #ifndef NO_RSA
+            if (ssl->specs.sig_algo == rsa_sa_algo) {
+                /* rsa sig size */
+                word32 i = 0;
+                ret = wc_RsaPrivateKeyDecode(ssl->buffers.key.buffer, &i,
+                                          &rsaKey, ssl->buffers.key.length);
+                if (ret != 0)
+                    goto done_a;
+                sigSz = wc_RsaEncryptSize(&rsaKey);
+            } else
+        #endif
+
+            if (ssl->specs.sig_algo == ecc_dsa_sa_algo) {
+                /* ecdsa sig size */
+                word32 i = 0;
+                ret = wc_EccPrivateKeyDecode(ssl->buffers.key.buffer, &i,
+                                          &dsaKey, ssl->buffers.key.length);
+                if (ret != 0)
+                    goto done_a;
+                sigSz = wc_ecc_sig_size(&dsaKey);  /* worst case estimate */
+            }
+            else {
+            #ifndef NO_RSA
+                wc_FreeRsaKey(&rsaKey);
+            #endif
+                wc_ecc_free(&dsaKey);
+                ERROR_OUT(ALGO_ID_E, done_a);  /* unsupported type */
+            }
+            length += sigSz;
+
+            if (IsAtLeastTLSv1_2(ssl))
+                length += HASH_SIG_SIZE;
+
+            sendSz = length + HANDSHAKE_HEADER_SZ + RECORD_HEADER_SZ;
+
+        #ifdef WOLFSSL_DTLS
+            if (ssl->options.dtls) {
+                sendSz += DTLS_RECORD_EXTRA + DTLS_HANDSHAKE_EXTRA;
+                idx    += DTLS_RECORD_EXTRA + DTLS_HANDSHAKE_EXTRA;
+                preSigIdx = idx;
+            }
+        #endif
+            /* check for available size */
+            if ((ret = CheckAvailableSize(ssl, sendSz)) != 0) {
+            #ifndef NO_RSA
+                wc_FreeRsaKey(&rsaKey);
+            #endif
+                wc_ecc_free(&dsaKey);
+                goto done_a;
+            }
+
+            /* get ouput buffer */
+            output = ssl->buffers.outputBuffer.buffer +
+                     ssl->buffers.outputBuffer.length;
+
+            /* record and message headers will be added below, when we're sure
+               of the sig length */
+
+            /* key exchange data */
+            output[idx++] = named_curve;
+            output[idx++] = 0x00;          /* leading zero */
+            output[idx++] = SetCurveId(wc_ecc_size(ssl->eccTempKey));
+            output[idx++] = (byte)expSz;
+            XMEMCPY(output + idx, exportBuf, expSz);
+            idx += expSz;
+            if (IsAtLeastTLSv1_2(ssl)) {
+                byte setHash = 0;
+
+                output[idx++] = ssl->suites->hashAlgo;
+                output[idx++] = ssl->suites->sigAlgo;
+
+                switch (ssl->suites->hashAlgo) {
+                    case sha512_mac:
+                        #ifdef WOLFSSL_SHA512
+                            doSha512 = 1;
+                            setHash  = 1;
+                        #endif
+                        break;
+
+                    case sha384_mac:
+                        #ifdef WOLFSSL_SHA384
+                            doSha384 = 1;
+                            setHash  = 1;
+                        #endif
+                        break;
+
+                    case sha256_mac:
+                        #ifndef NO_SHA256
+                            doSha256 = 1;
+                            setHash  = 1;
+                        #endif
+                        break;
+
+                    case sha_mac:
+                        #ifndef NO_OLD_TLS
+                            doSha = 1;
+                            setHash  = 1;
+                        #endif
+                        break;
+
+                    default:
+                        WOLFSSL_MSG("Bad hash sig algo");
+                        break;
+                }
+
+                if (setHash == 0) {
+                    #ifndef NO_RSA
+                        wc_FreeRsaKey(&rsaKey);
+                    #endif
+                    wc_ecc_free(&dsaKey);
+                    ERROR_OUT(ALGO_ID_E, done_a);
+                }
+            } else {
+                /* only using sha and md5 for rsa */
+                #ifndef NO_OLD_TLS
+                    doSha = 1;
+                    if (ssl->suites->sigAlgo == rsa_sa_algo) {
+                        doMd5 = 1;
+                    }
+                #else
+                    #ifndef NO_RSA
+                        wc_FreeRsaKey(&rsaKey);
+                    #endif
+                    wc_ecc_free(&dsaKey);
+                    ERROR_OUT(ALGO_ID_E, done_a);
+                #endif
+            }
+
+            /* Signtaure length will be written later, when we're sure what it
+               is */
+
+        #ifdef HAVE_FUZZER
+            if (ssl->fuzzerCb)
+                ssl->fuzzerCb(ssl, output + preSigIdx, preSigSz, FUZZ_SIGNATURE,
+                              ssl->fuzzerCtx);
+        #endif
+
+            /* do signature */
+            {
+        #ifndef NO_OLD_TLS
+            #ifdef WOLFSSL_SMALL_STACK
+                Md5*   md5  = NULL;
+                Sha*   sha  = NULL;
+            #else
+                Md5    md5[1];
+                Sha    sha[1];
+            #endif
+        #endif
+            #ifdef WOLFSSL_SMALL_STACK
+                byte*  hash = NULL;
+            #else
+                byte   hash[FINISHED_SZ];
+            #endif
+        #ifndef NO_SHA256
+            #ifdef WOLFSSL_SMALL_STACK
+                Sha256* sha256  = NULL;
+                byte*   hash256 = NULL;
+            #else
+                Sha256  sha256[1];
+                byte    hash256[SHA256_DIGEST_SIZE];
+            #endif
+        #endif
+        #ifdef WOLFSSL_SHA384
+            #ifdef WOLFSSL_SMALL_STACK
+                Sha384* sha384  = NULL;
+                byte*   hash384 = NULL;
+            #else
+                Sha384  sha384[1];
+                byte    hash384[SHA384_DIGEST_SIZE];
+            #endif
+        #endif
+        #ifdef WOLFSSL_SHA512
+            #ifdef WOLFSSL_SMALL_STACK
+                Sha512* sha512  = NULL;
+                byte*   hash512 = NULL;
+            #else
+                Sha512  sha512[1];
+                byte    hash512[SHA512_DIGEST_SIZE];
+            #endif
+        #endif
+
+            #ifdef WOLFSSL_SMALL_STACK
+                hash = (byte*)XMALLOC(FINISHED_SZ, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+                if (hash == NULL)
+                    ERROR_OUT(MEMORY_E, done_a);
+            #endif
+
+        #ifndef NO_OLD_TLS
+                /* md5 */
+            #ifdef WOLFSSL_SMALL_STACK
+                if (doMd5) {
+                    md5 = (Md5*)XMALLOC(sizeof(Md5), NULL,
+                                        DYNAMIC_TYPE_TMP_BUFFER);
+                    if (md5 == NULL)
+                        ERROR_OUT(MEMORY_E, done_a2);
+                }
+            #endif
+                if (doMd5) {
+                    wc_InitMd5(md5);
+                    wc_Md5Update(md5, ssl->arrays->clientRandom, RAN_LEN);
+                    wc_Md5Update(md5, ssl->arrays->serverRandom, RAN_LEN);
+                    wc_Md5Update(md5, output + preSigIdx, preSigSz);
+                    wc_Md5Final(md5, hash);
+                }
+                /* sha */
+            #ifdef WOLFSSL_SMALL_STACK
+                if (doSha) {
+                    sha = (Sha*)XMALLOC(sizeof(Sha), NULL,
+                                        DYNAMIC_TYPE_TMP_BUFFER);
+                    if (sha == NULL)
+                        ERROR_OUT(MEMORY_E, done_a2);
+                }
+            #endif
+                if (doSha) {
+                    ret = wc_InitSha(sha);
+                    if (ret != 0) goto done_a2;
+                    wc_ShaUpdate(sha, ssl->arrays->clientRandom, RAN_LEN);
+                    wc_ShaUpdate(sha, ssl->arrays->serverRandom, RAN_LEN);
+                    wc_ShaUpdate(sha, output + preSigIdx, preSigSz);
+                    wc_ShaFinal(sha, &hash[MD5_DIGEST_SIZE]);
+                }
+        #endif
+
+        #ifndef NO_SHA256
+            #ifdef WOLFSSL_SMALL_STACK
+                if (doSha256) {
+                    sha256 = (Sha256*)XMALLOC(sizeof(Sha256), NULL,
+                                              DYNAMIC_TYPE_TMP_BUFFER);
+                    hash256 = (byte*)XMALLOC(SHA256_DIGEST_SIZE, NULL,
+                                             DYNAMIC_TYPE_TMP_BUFFER);
+                    if (sha256 == NULL || hash256 == NULL)
+                        ERROR_OUT(MEMORY_E, done_a2);
+                }
+            #endif
+
+                if (doSha256) {
+                    if (!(ret = wc_InitSha256(sha256))
+                    &&  !(ret = wc_Sha256Update(sha256,
+                                            ssl->arrays->clientRandom, RAN_LEN))
+                    &&  !(ret = wc_Sha256Update(sha256,
+                                            ssl->arrays->serverRandom, RAN_LEN))
+                    &&  !(ret = wc_Sha256Update(sha256,
+                                            output + preSigIdx, preSigSz)))
+                        ret = wc_Sha256Final(sha256, hash256);
+
+                    if (ret != 0) goto done_a2;
+                }
+        #endif
+
+        #ifdef WOLFSSL_SHA384
+            #ifdef WOLFSSL_SMALL_STACK
+                if (doSha384) {
+                    sha384 = (Sha384*)XMALLOC(sizeof(Sha384), NULL,
+                                              DYNAMIC_TYPE_TMP_BUFFER);
+                    hash384 = (byte*)XMALLOC(SHA384_DIGEST_SIZE, NULL,
+                                             DYNAMIC_TYPE_TMP_BUFFER);
+                    if (sha384 == NULL || hash384 == NULL)
+                        ERROR_OUT(MEMORY_E, done_a2);
+                }
+            #endif
+
+                if (doSha384) {
+                    if (!(ret = wc_InitSha384(sha384))
+                    &&  !(ret = wc_Sha384Update(sha384,
+                                            ssl->arrays->clientRandom, RAN_LEN))
+                    &&  !(ret = wc_Sha384Update(sha384,
+                                            ssl->arrays->serverRandom, RAN_LEN))
+                    &&  !(ret = wc_Sha384Update(sha384,
+                                            output + preSigIdx, preSigSz)))
+                        ret = wc_Sha384Final(sha384, hash384);
+
+                    if (ret != 0) goto done_a2;
+                }
+        #endif
+
+        #ifdef WOLFSSL_SHA512
+            #ifdef WOLFSSL_SMALL_STACK
+                if (doSha512) {
+                    sha512 = (Sha512*)XMALLOC(sizeof(Sha512), NULL,
+                                              DYNAMIC_TYPE_TMP_BUFFER);
+                    hash512 = (byte*)XMALLOC(SHA512_DIGEST_SIZE, NULL,
+                                             DYNAMIC_TYPE_TMP_BUFFER);
+                    if (sha512 == NULL || hash512 == NULL)
+                        ERROR_OUT(MEMORY_E, done_a2);
+                }
+            #endif
+
+                if (doSha512) {
+                    if (!(ret = wc_InitSha512(sha512))
+                    &&  !(ret = wc_Sha512Update(sha512,
+                                            ssl->arrays->clientRandom, RAN_LEN))
+                    &&  !(ret = wc_Sha512Update(sha512,
+                                            ssl->arrays->serverRandom, RAN_LEN))
+                    &&  !(ret = wc_Sha512Update(sha512,
+                                            output + preSigIdx, preSigSz)))
+                        ret = wc_Sha512Final(sha512, hash512);
+
+                    if (ret != 0) goto done_a2;
+                }
+        #endif
+
+            #ifndef NO_RSA
+                if (ssl->suites->sigAlgo == rsa_sa_algo) {
+                    byte*  signBuffer = hash;
+                    word32 signSz     = FINISHED_SZ;
+                    byte   doUserRsa = 0;
+                #ifdef WOLFSSL_SMALL_STACK
+                    byte*  encodedSig = NULL;
+                #else
+                    byte   encodedSig[MAX_ENCODED_SIG_SZ];
+                #endif
+
+                #ifdef HAVE_PK_CALLBACKS
+                    if (ssl->ctx->RsaSignCb)
+                        doUserRsa = 1;
+                #endif
+
+                #ifdef WOLFSSL_SMALL_STACK
+                    encodedSig = (byte*)XMALLOC(MAX_ENCODED_SIG_SZ, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+                    if (encodedSig == NULL)
+                        ERROR_OUT(MEMORY_E, done_a2);
+                #endif
+
+                    if (IsAtLeastTLSv1_2(ssl)) {
+                        byte* digest   = &hash[MD5_DIGEST_SIZE];
+                        int   typeH    = SHAh;
+                        int   digestSz = SHA_DIGEST_SIZE;
+
+                        if (ssl->suites->hashAlgo == sha256_mac) {
+                        #ifndef NO_SHA256
+                            digest   = hash256;
+                            typeH    = SHA256h;
+                            digestSz = SHA256_DIGEST_SIZE;
+                        #endif
+                        }
+                        else if (ssl->suites->hashAlgo == sha384_mac) {
+                        #ifdef WOLFSSL_SHA384
+                            digest   = hash384;
+                            typeH    = SHA384h;
+                            digestSz = SHA384_DIGEST_SIZE;
+                        #endif
+                        }
+                        else if (ssl->suites->hashAlgo == sha512_mac) {
+                        #ifdef WOLFSSL_SHA512
+                            digest   = hash512;
+                            typeH    = SHA512h;
+                            digestSz = SHA512_DIGEST_SIZE;
+                        #endif
+                        }
+
+                        if (digest == NULL) {
+                            #ifndef NO_RSA
+                                wc_FreeRsaKey(&rsaKey);
+                            #endif
+                            wc_ecc_free(&dsaKey);
+                            ERROR_OUT(ALGO_ID_E, done_a2);
+                        }
+                        signSz = wc_EncodeSignature(encodedSig, digest,
+                                                    digestSz, typeH);
+                        signBuffer = encodedSig;
+                    }
+                    /* write sig size here */
+                    c16toa((word16)sigSz, output + idx);
+                    idx += LENGTH_SZ;
+
+                    if (doUserRsa) {
+                    #ifdef HAVE_PK_CALLBACKS
+                        word32 ioLen = sigSz;
+                        ret = ssl->ctx->RsaSignCb(ssl, signBuffer, signSz,
+                                            output + idx, &ioLen,
+                                            ssl->buffers.key.buffer,
+                                            ssl->buffers.key.length,
+                                            ssl->RsaSignCtx);
+                    #endif /*HAVE_PK_CALLBACKS */
+                    }
+                    else
+                        ret = wc_RsaSSL_Sign(signBuffer, signSz, output + idx,
+                                          sigSz, &rsaKey, ssl->rng);
+
+                    wc_FreeRsaKey(&rsaKey);
+                    wc_ecc_free(&dsaKey);
+
+                #ifdef WOLFSSL_SMALL_STACK
+                    XFREE(encodedSig, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                #endif
+
+                    if (ret < 0)
+                        goto done_a2;
+                } else
+            #endif
+
+                if (ssl->suites->sigAlgo == ecc_dsa_sa_algo) {
+                #ifndef NO_OLD_TLS
+                    byte* digest = &hash[MD5_DIGEST_SIZE];
+                    word32 digestSz = SHA_DIGEST_SIZE;
+                #else
+                    byte* digest = hash256;
+                    word32 digestSz = SHA256_DIGEST_SIZE;
+                #endif
+                    word32 sz = sigSz;
+                    byte   doUserEcc = 0;
+
+                #if defined(HAVE_PK_CALLBACKS) && defined(HAVE_ECC)
+                    if (ssl->ctx->EccSignCb)
+                        doUserEcc = 1;
+                #endif
+
+                    if (IsAtLeastTLSv1_2(ssl)) {
+                        if (ssl->suites->hashAlgo == sha_mac) {
+                        #ifndef NO_SHA
+                            digest   = &hash[MD5_DIGEST_SIZE];
+                            digestSz = SHA_DIGEST_SIZE;
+                        #endif
+                        }
+                        else if (ssl->suites->hashAlgo == sha256_mac) {
+                        #ifndef NO_SHA256
+                            digest   = hash256;
+                            digestSz = SHA256_DIGEST_SIZE;
+                        #endif
+                        }
+                        else if (ssl->suites->hashAlgo == sha384_mac) {
+                        #ifdef WOLFSSL_SHA384
+                            digest   = hash384;
+                            digestSz = SHA384_DIGEST_SIZE;
+                        #endif
+                        }
+                        else if (ssl->suites->hashAlgo == sha512_mac) {
+                        #ifdef WOLFSSL_SHA512
+                            digest   = hash512;
+                            digestSz = SHA512_DIGEST_SIZE;
+                        #endif
+                        }
+                    }
+
+                    if (doUserEcc) {
+                    #if defined(HAVE_PK_CALLBACKS) && defined(HAVE_ECC)
+                        ret = ssl->ctx->EccSignCb(ssl, digest, digestSz,
+                                                  output + LENGTH_SZ + idx, &sz,
+                                                  ssl->buffers.key.buffer,
+                                                  ssl->buffers.key.length,
+                                                  ssl->EccSignCtx);
+                    #endif
+                    }
+                    else {
+                        ret = wc_ecc_sign_hash(digest, digestSz,
+                              output + LENGTH_SZ + idx, &sz, ssl->rng, &dsaKey);
+                    }
+                #ifndef NO_RSA
+                    wc_FreeRsaKey(&rsaKey);
+                #endif
+                    wc_ecc_free(&dsaKey);
+
+                    if (ret < 0)
+                        goto done_a2;
+
+                    /* Now that we know the real sig size, write it. */
+                    c16toa((word16)sz, output + idx);
+
+                    /* And adjust length and sendSz from estimates */
+                    length += sz - sigSz;
+                    sendSz += sz - sigSz;
+                }
+
+            done_a2:
+        #ifdef WOLFSSL_SMALL_STACK
+            #ifndef NO_OLD_TLS
+                XFREE(md5,     NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                XFREE(sha,     NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            #endif
+                XFREE(hash,    NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            #ifndef NO_SHA256
+                XFREE(sha256,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                XFREE(hash256, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            #endif
+            #ifdef WOLFSSL_SHA384
+                XFREE(sha384,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                XFREE(hash384, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            #endif
+            #ifdef WOLFSSL_SHA512
+                XFREE(sha512,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                XFREE(hash512, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            #endif
+        #endif
+
+                if (ret < 0)
+                    goto done_a;
+            }
+
+            AddHeaders(output, length, server_key_exchange, ssl);
+
+        #ifdef WOLFSSL_DTLS
+            if (ssl->options.dtls)
+                if ((ret = DtlsPoolSave(ssl, output, sendSz)) != 0)
+                    goto done_a;
+        #endif
+
+            if ((ret = HashOutput(ssl, output, sendSz, 0)) != 0)
+                goto done_a;
+
+        #ifdef WOLFSSL_CALLBACKS
+            if (ssl->hsInfoOn)
+                AddPacketName("ServerKeyExchange", &ssl->handShakeInfo);
+            if (ssl->toInfoOn)
+                AddPacketInfo("ServerKeyExchange", &ssl->timeoutInfo,
+                              output, sendSz, ssl->heap);
+        #endif
+
+            ssl->buffers.outputBuffer.length += sendSz;
+            if (ssl->options.groupMessages)
+                ret = 0;
+            else
+                ret = SendBuffered(ssl);
+            ssl->options.serverState = SERVER_KEYEXCHANGE_COMPLETE;
+
+        done_a:
+        #ifdef WOLFSSL_SMALL_STACK
+            XFREE(exportBuf, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        #endif
+
+            return ret;
+        }
+    #endif /* HAVE_ECC */
+
+    #if !defined(NO_DH) && !defined(NO_RSA)
+        if (ssl->specs.kea == diffie_hellman_kea) {
+            byte    *output;
+            word32   length = 0, idx = RECORD_HEADER_SZ + HANDSHAKE_HEADER_SZ;
+            int      sendSz;
+            word32   sigSz = 0, i = 0;
+            word32   preSigSz = 0, preSigIdx = 0;
+            RsaKey   rsaKey;
+            DhKey    dhKey;
+
+            if (ssl->buffers.serverDH_P.buffer == NULL ||
+                ssl->buffers.serverDH_G.buffer == NULL)
+                return NO_DH_PARAMS;
+
+            if (ssl->buffers.serverDH_Pub.buffer == NULL) {
+                ssl->buffers.serverDH_Pub.buffer = (byte*)XMALLOC(
+                        ssl->buffers.serverDH_P.length + 2, ssl->ctx->heap,
+                        DYNAMIC_TYPE_DH);
+                if (ssl->buffers.serverDH_Pub.buffer == NULL)
+                    return MEMORY_E;
+            }
+
+            if (ssl->buffers.serverDH_Priv.buffer == NULL) {
+                ssl->buffers.serverDH_Priv.buffer = (byte*)XMALLOC(
+                        ssl->buffers.serverDH_P.length + 2, ssl->ctx->heap,
+                        DYNAMIC_TYPE_DH);
+                if (ssl->buffers.serverDH_Priv.buffer == NULL)
+                    return MEMORY_E;
+            }
+
+            wc_InitDhKey(&dhKey);
+            ret = wc_DhSetKey(&dhKey, ssl->buffers.serverDH_P.buffer,
+                                   ssl->buffers.serverDH_P.length,
+                                   ssl->buffers.serverDH_G.buffer,
+                                   ssl->buffers.serverDH_G.length);
+            if (ret == 0)
+                ret = wc_DhGenerateKeyPair(&dhKey, ssl->rng,
+                                         ssl->buffers.serverDH_Priv.buffer,
+                                        &ssl->buffers.serverDH_Priv.length,
+                                         ssl->buffers.serverDH_Pub.buffer,
+                                        &ssl->buffers.serverDH_Pub.length);
+            wc_FreeDhKey(&dhKey);
+
+            if (ret != 0) return ret;
+
+            length = LENGTH_SZ * 3;  /* p, g, pub */
+            length += ssl->buffers.serverDH_P.length +
+                      ssl->buffers.serverDH_G.length +
+                      ssl->buffers.serverDH_Pub.length;
+
+            preSigIdx = idx;
+            preSigSz  = length;
+
+            if (!ssl->options.usingAnon_cipher) {
+                ret = wc_InitRsaKey(&rsaKey, ssl->heap);
+                if (ret != 0) return ret;
+
+                /* sig length */
+                length += LENGTH_SZ;
+
+                if (!ssl->buffers.key.buffer)
+                    return NO_PRIVATE_KEY;
+
+                ret = wc_RsaPrivateKeyDecode(ssl->buffers.key.buffer, &i, &rsaKey,
+                                          ssl->buffers.key.length);
+                if (ret == 0) {
+                    sigSz = wc_RsaEncryptSize(&rsaKey);
+                    length += sigSz;
+                }
+                else {
+                    wc_FreeRsaKey(&rsaKey);
+                    return ret;
+                }
+
+                if (IsAtLeastTLSv1_2(ssl))
+                    length += HASH_SIG_SIZE;
+            }
+
+            sendSz = length + HANDSHAKE_HEADER_SZ + RECORD_HEADER_SZ;
+
+        #ifdef WOLFSSL_DTLS
+            if (ssl->options.dtls) {
+                sendSz += DTLS_RECORD_EXTRA + DTLS_HANDSHAKE_EXTRA;
+                idx    += DTLS_RECORD_EXTRA + DTLS_HANDSHAKE_EXTRA;
+                preSigIdx = idx;
+            }
+        #endif
+
+            /* check for available size */
+            if ((ret = CheckAvailableSize(ssl, sendSz)) != 0) {
+                if (!ssl->options.usingAnon_cipher)
+                    wc_FreeRsaKey(&rsaKey);
+                return ret;
+            }
+
+            /* get ouput buffer */
+            output = ssl->buffers.outputBuffer.buffer +
+                     ssl->buffers.outputBuffer.length;
+
+            AddHeaders(output, length, server_key_exchange, ssl);
+
+            /* add p, g, pub */
+            c16toa((word16)ssl->buffers.serverDH_P.length, output + idx);
+            idx += LENGTH_SZ;
+            XMEMCPY(output + idx, ssl->buffers.serverDH_P.buffer,
+                                  ssl->buffers.serverDH_P.length);
+            idx += ssl->buffers.serverDH_P.length;
+
+            /*  g */
+            c16toa((word16)ssl->buffers.serverDH_G.length, output + idx);
+            idx += LENGTH_SZ;
+            XMEMCPY(output + idx, ssl->buffers.serverDH_G.buffer,
+                                  ssl->buffers.serverDH_G.length);
+            idx += ssl->buffers.serverDH_G.length;
+
+            /*  pub */
+            c16toa((word16)ssl->buffers.serverDH_Pub.length, output + idx);
+            idx += LENGTH_SZ;
+            XMEMCPY(output + idx, ssl->buffers.serverDH_Pub.buffer,
+                                  ssl->buffers.serverDH_Pub.length);
+            idx += ssl->buffers.serverDH_Pub.length;
+
+        #ifdef HAVE_FUZZER
+            if (ssl->fuzzerCb)
+                ssl->fuzzerCb(ssl, output + preSigIdx, preSigSz, FUZZ_SIGNATURE,
+                        ssl->fuzzerCtx);
+        #endif
+
+            /* Add signature */
+            if (!ssl->options.usingAnon_cipher) {
+        #ifndef NO_OLD_TLS
+            #ifdef WOLFSSL_SMALL_STACK
+                Md5*   md5  = NULL;
+                Sha*   sha  = NULL;
+            #else
+                Md5    md5[1];
+                Sha    sha[1];
+            #endif
+        #endif
+            #ifdef WOLFSSL_SMALL_STACK
+                byte*  hash = NULL;
+            #else
+                byte   hash[FINISHED_SZ];
+            #endif
+        #ifndef NO_SHA256
+            #ifdef WOLFSSL_SMALL_STACK
+                Sha256* sha256  = NULL;
+                byte*   hash256 = NULL;
+            #else
+                Sha256  sha256[1];
+                byte    hash256[SHA256_DIGEST_SIZE];
+            #endif
+        #endif
+        #ifdef WOLFSSL_SHA384
+            #ifdef WOLFSSL_SMALL_STACK
+                Sha384* sha384  = NULL;
+                byte*   hash384 = NULL;
+            #else
+                Sha384  sha384[1];
+                byte    hash384[SHA384_DIGEST_SIZE];
+            #endif
+        #endif
+        #ifdef WOLFSSL_SHA512
+            #ifdef WOLFSSL_SMALL_STACK
+                Sha512* sha512  = NULL;
+                byte*   hash512 = NULL;
+            #else
+                Sha512  sha512[1];
+                byte    hash512[SHA512_DIGEST_SIZE];
+            #endif
+        #endif
+
+        #ifndef NO_OLD_TLS
+            byte doMd5 = 0;
+            byte doSha = 0;
+        #endif
+        #ifndef NO_SHA256
+            byte doSha256 = 0;
+        #endif
+        #ifdef WOLFSSL_SHA384
+            byte doSha384 = 0;
+        #endif
+        #ifdef WOLFSSL_SHA512
+            byte doSha512 = 0;
+        #endif
+
+            /* Add hash/signature algo ID */
+            if (IsAtLeastTLSv1_2(ssl)) {
+                byte setHash = 0;
+
+                output[idx++] = ssl->suites->hashAlgo;
+                output[idx++] = ssl->suites->sigAlgo;
+
+                switch (ssl->suites->hashAlgo) {
+                    case sha512_mac:
+                        #ifdef WOLFSSL_SHA512
+                            doSha512 = 1;
+                            setHash  = 1;
+                        #endif
+                        break;
+
+                    case sha384_mac:
+                        #ifdef WOLFSSL_SHA384
+                            doSha384 = 1;
+                            setHash  = 1;
+                        #endif
+                        break;
+
+                    case sha256_mac:
+                        #ifndef NO_SHA256
+                            doSha256 = 1;
+                            setHash  = 1;
+                        #endif
+                        break;
+
+                    case sha_mac:
+                        #ifndef NO_OLD_TLS
+                            doSha = 1;
+                            setHash  = 1;
+                        #endif
+                        break;
+
+                    default:
+                        WOLFSSL_MSG("Bad hash sig algo");
+                        break;
+                }
+
+                if (setHash == 0) {
+                    wc_FreeRsaKey(&rsaKey);
+                    return ALGO_ID_E;
+                }
+            } else {
+                /* only using sha and md5 for rsa */
+                #ifndef NO_OLD_TLS
+                    doSha = 1;
+                    if (ssl->suites->sigAlgo == rsa_sa_algo) {
+                        doMd5 = 1;
+                    }
+                #else
+                    wc_FreeRsaKey(&rsaKey);
+                    return ALGO_ID_E;
+                #endif
+            }
+
+            /* signature size */
+            c16toa((word16)sigSz, output + idx);
+            idx += LENGTH_SZ;
+
+            /* do signature */
+            #ifdef WOLFSSL_SMALL_STACK
+                hash = (byte*)XMALLOC(FINISHED_SZ, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+                if (hash == NULL)
+                    return MEMORY_E; /* No heap commitment before this point,
+                                        from now on, the resources are freed
+                                        at done_b. */
+            #endif
+
+        #ifndef NO_OLD_TLS
+                /* md5 */
+            #ifdef WOLFSSL_SMALL_STACK
+                if (doMd5) {
+                    md5 = (Md5*)XMALLOC(sizeof(Md5), NULL,
+                                        DYNAMIC_TYPE_TMP_BUFFER);
+                    if (md5 == NULL)
+                        ERROR_OUT(MEMORY_E, done_b);
+                }
+            #endif
+                if (doMd5) {
+                    wc_InitMd5(md5);
+                    wc_Md5Update(md5, ssl->arrays->clientRandom, RAN_LEN);
+                    wc_Md5Update(md5, ssl->arrays->serverRandom, RAN_LEN);
+                    wc_Md5Update(md5, output + preSigIdx, preSigSz);
+                    wc_Md5Final(md5, hash);
+                }
+
+                /* sha */
+            #ifdef WOLFSSL_SMALL_STACK
+                if (doSha) {
+                    sha = (Sha*)XMALLOC(sizeof(Sha), NULL,
+                                        DYNAMIC_TYPE_TMP_BUFFER);
+                    if (sha == NULL)
+                        ERROR_OUT(MEMORY_E, done_b);
+                }
+            #endif
+
+                if (doSha) {
+                    if ((ret = wc_InitSha(sha)) != 0)
+                        goto done_b;
+                    wc_ShaUpdate(sha, ssl->arrays->clientRandom, RAN_LEN);
+                    wc_ShaUpdate(sha, ssl->arrays->serverRandom, RAN_LEN);
+                    wc_ShaUpdate(sha, output + preSigIdx, preSigSz);
+                    wc_ShaFinal(sha, &hash[MD5_DIGEST_SIZE]);
+                }
+        #endif
+
+        #ifndef NO_SHA256
+            #ifdef WOLFSSL_SMALL_STACK
+                if (doSha256) {
+                    sha256 = (Sha256*)XMALLOC(sizeof(Sha256), NULL,
+                                              DYNAMIC_TYPE_TMP_BUFFER);
+                    hash256 = (byte*)XMALLOC(SHA256_DIGEST_SIZE, NULL,
+                                             DYNAMIC_TYPE_TMP_BUFFER);
+                    if (sha256 == NULL || hash256 == NULL)
+                        ERROR_OUT(MEMORY_E, done_b);
+                }
+            #endif
+
+                if (doSha256) {
+                    if (!(ret = wc_InitSha256(sha256))
+                    &&  !(ret = wc_Sha256Update(sha256,
+                                            ssl->arrays->clientRandom, RAN_LEN))
+                    &&  !(ret = wc_Sha256Update(sha256,
+                                            ssl->arrays->serverRandom, RAN_LEN))
+                    &&  !(ret = wc_Sha256Update(sha256,
+                                            output + preSigIdx, preSigSz)))
+                        ret = wc_Sha256Final(sha256, hash256);
+
+                    if (ret != 0) goto done_b;
+                }
+            #endif
+
+        #ifdef WOLFSSL_SHA384
+            #ifdef WOLFSSL_SMALL_STACK
+                if (doSha384) {
+                    sha384 = (Sha384*)XMALLOC(sizeof(Sha384), NULL,
+                                              DYNAMIC_TYPE_TMP_BUFFER);
+                    hash384 = (byte*)XMALLOC(SHA384_DIGEST_SIZE, NULL,
+                                             DYNAMIC_TYPE_TMP_BUFFER);
+                    if (sha384 == NULL || hash384 == NULL)
+                        ERROR_OUT(MEMORY_E, done_b);
+                }
+            #endif
+
+                if (doSha384) {
+                    if (!(ret = wc_InitSha384(sha384))
+                    &&  !(ret = wc_Sha384Update(sha384,
+                                            ssl->arrays->clientRandom, RAN_LEN))
+                    &&  !(ret = wc_Sha384Update(sha384,
+                                            ssl->arrays->serverRandom, RAN_LEN))
+                    &&  !(ret = wc_Sha384Update(sha384,
+                                            output + preSigIdx, preSigSz)))
+                        ret = wc_Sha384Final(sha384, hash384);
+
+                    if (ret != 0) goto done_b;
+                }
+        #endif
+
+        #ifdef WOLFSSL_SHA512
+            #ifdef WOLFSSL_SMALL_STACK
+                if (doSha512) {
+                    sha512 = (Sha512*)XMALLOC(sizeof(Sha512), NULL,
+                                              DYNAMIC_TYPE_TMP_BUFFER);
+                    hash512 = (byte*)XMALLOC(SHA512_DIGEST_SIZE, NULL,
+                                             DYNAMIC_TYPE_TMP_BUFFER);
+                    if (sha512 == NULL || hash512 == NULL)
+                        ERROR_OUT(MEMORY_E, done_b);
+                }
+            #endif
+
+                if (doSha512) {
+                    if (!(ret = wc_InitSha512(sha512))
+                    &&  !(ret = wc_Sha512Update(sha512,
+                                            ssl->arrays->clientRandom, RAN_LEN))
+                    &&  !(ret = wc_Sha512Update(sha512,
+                                            ssl->arrays->serverRandom, RAN_LEN))
+                    &&  !(ret = wc_Sha512Update(sha512,
+                                            output + preSigIdx, preSigSz)))
+                        ret = wc_Sha512Final(sha512, hash512);
+
+                    if (ret != 0) goto done_b;
+                }
+        #endif
+
+            #ifndef NO_RSA
+                if (ssl->suites->sigAlgo == rsa_sa_algo) {
+                    byte*  signBuffer = hash;
+                    word32 signSz     = FINISHED_SZ;
+                #ifdef WOLFSSL_SMALL_STACK
+                    byte*  encodedSig = NULL;
+                #else
+                    byte   encodedSig[MAX_ENCODED_SIG_SZ];
+                #endif
+                    byte   doUserRsa = 0;
+
+                #ifdef HAVE_PK_CALLBACKS
+                    if (ssl->ctx->RsaSignCb)
+                        doUserRsa = 1;
+                #endif
+
+                #ifdef WOLFSSL_SMALL_STACK
+                    encodedSig = (byte*)XMALLOC(MAX_ENCODED_SIG_SZ, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+                    if (encodedSig == NULL)
+                        ERROR_OUT(MEMORY_E, done_b);
+                #endif
+
+                    if (IsAtLeastTLSv1_2(ssl)) {
+                        byte* digest   = &hash[MD5_DIGEST_SIZE];
+                        int   typeH    = SHAh;
+                        int   digestSz = SHA_DIGEST_SIZE;
+
+                        if (ssl->suites->hashAlgo == sha256_mac) {
+                        #ifndef NO_SHA256
+                            digest   = hash256;
+                            typeH    = SHA256h;
+                            digestSz = SHA256_DIGEST_SIZE;
+                        #endif
+                        }
+                        else if (ssl->suites->hashAlgo == sha384_mac) {
+                        #ifdef WOLFSSL_SHA384
+                            digest   = hash384;
+                            typeH    = SHA384h;
+                            digestSz = SHA384_DIGEST_SIZE;
+                        #endif
+                        }
+                        else if (ssl->suites->hashAlgo == sha512_mac) {
+                        #ifdef WOLFSSL_SHA512
+                            digest   = hash512;
+                            typeH    = SHA512h;
+                            digestSz = SHA512_DIGEST_SIZE;
+                        #endif
+                        }
+
+                        if (digest == NULL) {
+                            ret = ALGO_ID_E;
+                        } else {
+                            signSz = wc_EncodeSignature(encodedSig, digest,
+                                                        digestSz, typeH);
+                            signBuffer = encodedSig;
+                        }
+                    }
+                    if (doUserRsa && ret == 0) {
+                    #ifdef HAVE_PK_CALLBACKS
+                        word32 ioLen = sigSz;
+                        ret = ssl->ctx->RsaSignCb(ssl, signBuffer, signSz,
+                                                  output + idx, &ioLen,
+                                                  ssl->buffers.key.buffer,
+                                                  ssl->buffers.key.length,
+                                                  ssl->RsaSignCtx);
+                    #endif
+                    } else if (ret == 0) {
+                        ret = wc_RsaSSL_Sign(signBuffer, signSz, output + idx,
+                                          sigSz, &rsaKey, ssl->rng);
+                    }
+
+                    wc_FreeRsaKey(&rsaKey);
+
+                #ifdef WOLFSSL_SMALL_STACK
+                    XFREE(encodedSig, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                #endif
+                }
+            #endif
+
+            done_b:
+        #ifdef WOLFSSL_SMALL_STACK
+            #ifndef NO_OLD_TLS
+                XFREE(md5,     NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                XFREE(sha,     NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            #endif
+                XFREE(hash,    NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            #ifndef NO_SHA256
+                XFREE(sha256,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                XFREE(hash256, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            #endif
+            #ifdef WOLFSSL_SHA384
+                XFREE(sha384,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                XFREE(hash384, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            #endif
+            #ifdef WOLFSSL_SHA512
+                XFREE(sha512,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                XFREE(hash512, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            #endif
+        #endif
+
+                if (ret < 0) return ret;
+            }
+
+        #ifdef WOLFSSL_DTLS
+            if (ssl->options.dtls)
+                if ((ret = DtlsPoolSave(ssl, output, sendSz)) != 0)
+                    return ret;
+        #endif
+
+            if ((ret = HashOutput(ssl, output, sendSz, 0)) != 0)
+                return ret;
+
+        #ifdef WOLFSSL_CALLBACKS
+            if (ssl->hsInfoOn)
+                AddPacketName("ServerKeyExchange", &ssl->handShakeInfo);
+            if (ssl->toInfoOn)
+                AddPacketInfo("ServerKeyExchange", &ssl->timeoutInfo,
+                              output, sendSz, ssl->heap);
+        #endif
+
+            ssl->buffers.outputBuffer.length += sendSz;
+            if (ssl->options.groupMessages)
+                ret = 0;
+            else
+                ret = SendBuffered(ssl);
+            ssl->options.serverState = SERVER_KEYEXCHANGE_COMPLETE;
+        }
+    #endif /* NO_DH */
+
+        return ret;
+        #undef ERROR_OUT
+    }
+
+
+    /* Make sure server cert/key are valid for this suite, true on success */
+    static int VerifyServerSuite(WOLFSSL* ssl, word16 idx)
+    {
+        int  haveRSA = !ssl->options.haveStaticECC;
+        int  havePSK = 0;
+        byte first;
+        byte second;
+
+        WOLFSSL_ENTER("VerifyServerSuite");
+
+        if (ssl->suites == NULL) {
+            WOLFSSL_MSG("Suites pointer error");
+            return 0;
+        }
+
+        first   = ssl->suites->suites[idx];
+        second  = ssl->suites->suites[idx+1];
+
+        #ifndef NO_PSK
+            havePSK = ssl->options.havePSK;
+        #endif
+
+        if (ssl->options.haveNTRU)
+            haveRSA = 0;
+
+        if (CipherRequires(first, second, REQUIRES_RSA)) {
+            WOLFSSL_MSG("Requires RSA");
+            if (haveRSA == 0) {
+                WOLFSSL_MSG("Don't have RSA");
+                return 0;
+            }
+        }
+
+        if (CipherRequires(first, second, REQUIRES_DHE)) {
+            WOLFSSL_MSG("Requires DHE");
+            if (ssl->options.haveDH == 0) {
+                WOLFSSL_MSG("Don't have DHE");
+                return 0;
+            }
+        }
+
+        if (CipherRequires(first, second, REQUIRES_ECC_DSA)) {
+            WOLFSSL_MSG("Requires ECCDSA");
+            if (ssl->options.haveECDSAsig == 0) {
+                WOLFSSL_MSG("Don't have ECCDSA");
+                return 0;
+            }
+        }
+
+        if (CipherRequires(first, second, REQUIRES_ECC_STATIC)) {
+            WOLFSSL_MSG("Requires static ECC");
+            if (ssl->options.haveStaticECC == 0) {
+                WOLFSSL_MSG("Don't have static ECC");
+                return 0;
+            }
+        }
+
+        if (CipherRequires(first, second, REQUIRES_PSK)) {
+            WOLFSSL_MSG("Requires PSK");
+            if (havePSK == 0) {
+                WOLFSSL_MSG("Don't have PSK");
+                return 0;
+            }
+        }
+
+        if (CipherRequires(first, second, REQUIRES_NTRU)) {
+            WOLFSSL_MSG("Requires NTRU");
+            if (ssl->options.haveNTRU == 0) {
+                WOLFSSL_MSG("Don't have NTRU");
+                return 0;
+            }
+        }
+
+        if (CipherRequires(first, second, REQUIRES_RSA_SIG)) {
+            WOLFSSL_MSG("Requires RSA Signature");
+            if (ssl->options.side == WOLFSSL_SERVER_END &&
+                                           ssl->options.haveECDSAsig == 1) {
+                WOLFSSL_MSG("Don't have RSA Signature");
+                return 0;
+            }
+        }
+
+#ifdef HAVE_SUPPORTED_CURVES
+        if (!TLSX_ValidateEllipticCurves(ssl, first, second)) {
+            WOLFSSL_MSG("Don't have matching curves");
+                return 0;
+        }
+#endif
+
+        /* ECCDHE is always supported if ECC on */
+
+        return 1;
+    }
+
+
+    static int MatchSuite(WOLFSSL* ssl, Suites* peerSuites)
+    {
+        word16 i, j;
+
+        WOLFSSL_ENTER("MatchSuite");
+
+        /* & 0x1 equivalent % 2 */
+        if (peerSuites->suiteSz == 0 || peerSuites->suiteSz & 0x1)
+            return MATCH_SUITE_ERROR;
+
+        if (ssl->suites == NULL)
+            return SUITES_ERROR;
+        /* start with best, if a match we are good */
+        for (i = 0; i < ssl->suites->suiteSz; i += 2)
+            for (j = 0; j < peerSuites->suiteSz; j += 2)
+                if (ssl->suites->suites[i]   == peerSuites->suites[j] &&
+                    ssl->suites->suites[i+1] == peerSuites->suites[j+1] ) {
+
+                    if (VerifyServerSuite(ssl, i)) {
+                        int result;
+                        WOLFSSL_MSG("Verified suite validity");
+                        ssl->options.cipherSuite0 = ssl->suites->suites[i];
+                        ssl->options.cipherSuite  = ssl->suites->suites[i+1];
+                        result = SetCipherSpecs(ssl);
+                        if (result == 0)
+                            PickHashSigAlgo(ssl, peerSuites->hashSigAlgo,
+                                                 peerSuites->hashSigAlgoSz);
+                        return result;
+                    }
+                    else {
+                        WOLFSSL_MSG("Could not verify suite validity, continue");
+                    }
+                }
+
+        return MATCH_SUITE_ERROR;
+    }
+
+
+#ifdef OLD_HELLO_ALLOWED
+
+    /* process old style client hello, deprecate? */
+    int ProcessOldClientHello(WOLFSSL* ssl, const byte* input, word32* inOutIdx,
+                              word32 inSz, word16 sz)
+    {
+        word32          idx = *inOutIdx;
+        word16          sessionSz;
+        word16          randomSz;
+        word16          i, j;
+        ProtocolVersion pv;
+        Suites          clSuites;
+
+        (void)inSz;
+        WOLFSSL_MSG("Got old format client hello");
+#ifdef WOLFSSL_CALLBACKS
+        if (ssl->hsInfoOn)
+            AddPacketName("ClientHello", &ssl->handShakeInfo);
+        if (ssl->toInfoOn)
+            AddLateName("ClientHello", &ssl->timeoutInfo);
+#endif
+
+        /* manually hash input since different format */
+#ifndef NO_OLD_TLS
+#ifndef NO_MD5
+        wc_Md5Update(&ssl->hsHashes->hashMd5, input + idx, sz);
+#endif
+#ifndef NO_SHA
+        wc_ShaUpdate(&ssl->hsHashes->hashSha, input + idx, sz);
+#endif
+#endif
+#ifndef NO_SHA256
+        if (IsAtLeastTLSv1_2(ssl)) {
+            int shaRet = wc_Sha256Update(&ssl->hsHashes->hashSha256,
+                                         input + idx, sz);
+            if (shaRet != 0)
+                return shaRet;
+        }
+#endif
+
+        /* does this value mean client_hello? */
+        idx++;
+
+        /* version */
+        pv.major = input[idx++];
+        pv.minor = input[idx++];
+        ssl->chVersion = pv;  /* store */
+
+        if (ssl->version.minor > pv.minor) {
+            byte haveRSA = 0;
+            byte havePSK = 0;
+            if (!ssl->options.downgrade) {
+                WOLFSSL_MSG("Client trying to connect with lesser version");
+                return VERSION_ERROR;
+            }
+            if (pv.minor < ssl->options.minDowngrade) {
+                WOLFSSL_MSG("    version below minimum allowed, fatal error");
+                return VERSION_ERROR;
+            }
+            if (pv.minor == SSLv3_MINOR) {
+                /* turn off tls */
+                WOLFSSL_MSG("    downgrading to SSLv3");
+                ssl->options.tls    = 0;
+                ssl->options.tls1_1 = 0;
+                ssl->version.minor  = SSLv3_MINOR;
+            }
+            else if (pv.minor == TLSv1_MINOR) {
+                WOLFSSL_MSG("    downgrading to TLSv1");
+                /* turn off tls 1.1+ */
+                ssl->options.tls1_1 = 0;
+                ssl->version.minor  = TLSv1_MINOR;
+            }
+            else if (pv.minor == TLSv1_1_MINOR) {
+                WOLFSSL_MSG("    downgrading to TLSv1.1");
+                ssl->version.minor  = TLSv1_1_MINOR;
+            }
+#ifndef NO_RSA
+            haveRSA = 1;
+#endif
+#ifndef NO_PSK
+            havePSK = ssl->options.havePSK;
+#endif
+
+            InitSuites(ssl->suites, ssl->version, haveRSA, havePSK,
+                       ssl->options.haveDH, ssl->options.haveNTRU,
+                       ssl->options.haveECDSAsig, ssl->options.haveStaticECC,
+                       ssl->options.side);
+        }
+
+        /* suite size */
+        ato16(&input[idx], &clSuites.suiteSz);
+        idx += 2;
+
+        if (clSuites.suiteSz > MAX_SUITE_SZ)
+            return BUFFER_ERROR;
+        clSuites.hashSigAlgoSz = 0;
+
+        /* session size */
+        ato16(&input[idx], &sessionSz);
+        idx += 2;
+
+        if (sessionSz > ID_LEN)
+            return BUFFER_ERROR;
+
+        /* random size */
+        ato16(&input[idx], &randomSz);
+        idx += 2;
+
+        if (randomSz > RAN_LEN)
+            return BUFFER_ERROR;
+
+        /* suites */
+        for (i = 0, j = 0; i < clSuites.suiteSz; i += 3) {
+            byte first = input[idx++];
+            if (!first) { /* implicit: skip sslv2 type */
+                XMEMCPY(&clSuites.suites[j], &input[idx], 2);
+                j += 2;
+            }
+            idx += 2;
+        }
+        clSuites.suiteSz = j;
+
+        /* session id */
+        if (sessionSz) {
+            XMEMCPY(ssl->arrays->sessionID, input + idx, sessionSz);
+            ssl->arrays->sessionIDSz = (byte)sessionSz;
+            idx += sessionSz;
+            ssl->options.resuming = 1;
+        }
+
+        /* random */
+        if (randomSz < RAN_LEN)
+            XMEMSET(ssl->arrays->clientRandom, 0, RAN_LEN - randomSz);
+        XMEMCPY(&ssl->arrays->clientRandom[RAN_LEN - randomSz], input + idx,
+               randomSz);
+        idx += randomSz;
+
+        if (ssl->options.usingCompression)
+            ssl->options.usingCompression = 0;  /* turn off */
+
+        ssl->options.clientState = CLIENT_HELLO_COMPLETE;
+        *inOutIdx = idx;
+
+        ssl->options.haveSessionId = 1;
+        /* DoClientHello uses same resume code */
+        if (ssl->options.resuming) {  /* let's try */
+            int ret = -1;
+            WOLFSSL_SESSION* session = GetSession(ssl,
+                                                  ssl->arrays->masterSecret);
+            #ifdef HAVE_SESSION_TICKET
+                if (ssl->options.useTicket == 1) {
+                    session = &ssl->session;
+                }
+            #endif
+
+            if (!session) {
+                WOLFSSL_MSG("Session lookup for resume failed");
+                ssl->options.resuming = 0;
+            } else {
+                if (MatchSuite(ssl, &clSuites) < 0) {
+                    WOLFSSL_MSG("Unsupported cipher suite, OldClientHello");
+                    return UNSUPPORTED_SUITE;
+                }
+                #ifdef SESSION_CERTS
+                    ssl->session = *session; /* restore session certs. */
+                #endif
+
+                ret = wc_RNG_GenerateBlock(ssl->rng, ssl->arrays->serverRandom,
+                                                                       RAN_LEN);
+                if (ret != 0)
+                    return ret;
+
+                #ifdef NO_OLD_TLS
+                    ret = DeriveTlsKeys(ssl);
+                #else
+                    #ifndef NO_TLS
+                        if (ssl->options.tls)
+                            ret = DeriveTlsKeys(ssl);
+                    #endif
+                        if (!ssl->options.tls)
+                            ret = DeriveKeys(ssl);
+                #endif
+                ssl->options.clientState = CLIENT_KEYEXCHANGE_COMPLETE;
+
+                return ret;
+            }
+        }
+
+        return MatchSuite(ssl, &clSuites);
+    }
+
+#endif /* OLD_HELLO_ALLOWED */
+
+
+    static int DoClientHello(WOLFSSL* ssl, const byte* input, word32* inOutIdx,
+                             word32 helloSz)
+    {
+        byte            b;
+        ProtocolVersion pv;
+        Suites          clSuites;
+        word32          i = *inOutIdx;
+        word32          begin = i;
+
+#ifdef WOLFSSL_CALLBACKS
+        if (ssl->hsInfoOn) AddPacketName("ClientHello", &ssl->handShakeInfo);
+        if (ssl->toInfoOn) AddLateName("ClientHello", &ssl->timeoutInfo);
+#endif
+
+        /* protocol version, random and session id length check */
+        if ((i - begin) + OPAQUE16_LEN + RAN_LEN + OPAQUE8_LEN > helloSz)
+            return BUFFER_ERROR;
+
+        /* protocol version */
+        XMEMCPY(&pv, input + i, OPAQUE16_LEN);
+        ssl->chVersion = pv;   /* store */
+        i += OPAQUE16_LEN;
+
+        if (ssl->version.minor > pv.minor) {
+            byte haveRSA = 0;
+            byte havePSK = 0;
+
+            if (!ssl->options.downgrade) {
+                WOLFSSL_MSG("Client trying to connect with lesser version");
+                return VERSION_ERROR;
+            }
+            if (pv.minor < ssl->options.minDowngrade) {
+                WOLFSSL_MSG("    version below minimum allowed, fatal error");
+                return VERSION_ERROR;
+            }
+
+            if (pv.minor == SSLv3_MINOR) {
+                /* turn off tls */
+                WOLFSSL_MSG("    downgrading to SSLv3");
+                ssl->options.tls    = 0;
+                ssl->options.tls1_1 = 0;
+                ssl->version.minor  = SSLv3_MINOR;
+            }
+            else if (pv.minor == TLSv1_MINOR) {
+                /* turn off tls 1.1+ */
+                WOLFSSL_MSG("    downgrading to TLSv1");
+                ssl->options.tls1_1 = 0;
+                ssl->version.minor  = TLSv1_MINOR;
+            }
+            else if (pv.minor == TLSv1_1_MINOR) {
+                WOLFSSL_MSG("    downgrading to TLSv1.1");
+                ssl->version.minor  = TLSv1_1_MINOR;
+            }
+#ifndef NO_RSA
+            haveRSA = 1;
+#endif
+#ifndef NO_PSK
+            havePSK = ssl->options.havePSK;
+#endif
+            InitSuites(ssl->suites, ssl->version, haveRSA, havePSK,
+                       ssl->options.haveDH, ssl->options.haveNTRU,
+                       ssl->options.haveECDSAsig, ssl->options.haveStaticECC,
+                       ssl->options.side);
+        }
+
+        /* random */
+        XMEMCPY(ssl->arrays->clientRandom, input + i, RAN_LEN);
+        i += RAN_LEN;
+
+#ifdef SHOW_SECRETS
+        {
+            int j;
+            printf("client random: ");
+            for (j = 0; j < RAN_LEN; j++)
+                printf("%02x", ssl->arrays->clientRandom[j]);
+            printf("\n");
+        }
+#endif
+
+        /* session id */
+        b = input[i++];
+
+        if (b == ID_LEN) {
+            if ((i - begin) + ID_LEN > helloSz)
+                return BUFFER_ERROR;
+
+            XMEMCPY(ssl->arrays->sessionID, input + i, ID_LEN);
+            ssl->arrays->sessionIDSz = ID_LEN;
+            i += ID_LEN;
+            ssl->options.resuming = 1; /* client wants to resume */
+            WOLFSSL_MSG("Client wants to resume session");
+        }
+        else if (b) {
+            WOLFSSL_MSG("Invalid session ID size");
+            return BUFFER_ERROR; /* session ID nor 0 neither 32 bytes long */
+        }
+
+        #ifdef WOLFSSL_DTLS
+            /* cookie */
+            if (ssl->options.dtls) {
+
+                if ((i - begin) + OPAQUE8_LEN > helloSz)
+                    return BUFFER_ERROR;
+
+                b = input[i++];
+
+                if (b) {
+                    byte cookie[MAX_COOKIE_LEN];
+
+                    if (b > MAX_COOKIE_LEN)
+                        return BUFFER_ERROR;
+
+                    if ((i - begin) + b > helloSz)
+                        return BUFFER_ERROR;
+
+                    if (ssl->ctx->CBIOCookie == NULL) {
+                        WOLFSSL_MSG("Your Cookie callback is null, please set");
+                        return COOKIE_ERROR;
+                    }
+
+                    if ((ssl->ctx->CBIOCookie(ssl, cookie, COOKIE_SZ,
+                                              ssl->IOCB_CookieCtx) != COOKIE_SZ)
+                            || (b != COOKIE_SZ)
+                            || (XMEMCMP(cookie, input + i, b) != 0)) {
+                        return COOKIE_ERROR;
+                    }
+
+                    i += b;
+                }
+            }
+        #endif
+
+        /* suites */
+        if ((i - begin) + OPAQUE16_LEN > helloSz)
+            return BUFFER_ERROR;
+
+        ato16(&input[i], &clSuites.suiteSz);
+        i += OPAQUE16_LEN;
+
+        /* suites and compression length check */
+        if ((i - begin) + clSuites.suiteSz + OPAQUE8_LEN > helloSz)
+            return BUFFER_ERROR;
+
+        if (clSuites.suiteSz > MAX_SUITE_SZ)
+            return BUFFER_ERROR;
+
+        XMEMCPY(clSuites.suites, input + i, clSuites.suiteSz);
+        i += clSuites.suiteSz;
+        clSuites.hashSigAlgoSz = 0;
+
+        /* compression length */
+        b = input[i++];
+
+        if ((i - begin) + b > helloSz)
+            return BUFFER_ERROR;
+
+        if (ssl->options.usingCompression) {
+            int match = 0;
+
+            while (b--) {
+                byte comp = input[i++];
+
+                if (comp == ZLIB_COMPRESSION)
+                    match = 1;
+            }
+
+            if (!match) {
+                WOLFSSL_MSG("Not matching compression, turning off");
+                ssl->options.usingCompression = 0;  /* turn off */
+            }
+        }
+        else
+            i += b; /* ignore, since we're not on */
+
+        *inOutIdx = i;
+
+        /* tls extensions */
+        if ((i - begin) < helloSz) {
+#ifdef HAVE_TLS_EXTENSIONS
+            if (TLSX_SupportExtensions(ssl)) {
+                int ret = 0;
+#else
+            if (IsAtLeastTLSv1_2(ssl)) {
+#endif
+                /* Process the hello extension. Skip unsupported. */
+                word16 totalExtSz;
+
+                if ((i - begin) + OPAQUE16_LEN > helloSz)
+                    return BUFFER_ERROR;
+
+                ato16(&input[i], &totalExtSz);
+                i += OPAQUE16_LEN;
+
+                if ((i - begin) + totalExtSz > helloSz)
+                    return BUFFER_ERROR;
+
+#ifdef HAVE_TLS_EXTENSIONS
+                if ((ret = TLSX_Parse(ssl, (byte *) input + i,
+                                                     totalExtSz, 1, &clSuites)))
+                    return ret;
+
+                i += totalExtSz;
+#else
+                while (totalExtSz) {
+                    word16 extId, extSz;
+
+                    if (OPAQUE16_LEN + OPAQUE16_LEN > totalExtSz)
+                        return BUFFER_ERROR;
+
+                    ato16(&input[i], &extId);
+                    i += OPAQUE16_LEN;
+                    ato16(&input[i], &extSz);
+                    i += OPAQUE16_LEN;
+
+                    if (OPAQUE16_LEN + OPAQUE16_LEN + extSz > totalExtSz)
+                        return BUFFER_ERROR;
+
+                    if (extId == HELLO_EXT_SIG_ALGO) {
+                        ato16(&input[i], &clSuites.hashSigAlgoSz);
+                        i += OPAQUE16_LEN;
+
+                        if (OPAQUE16_LEN + clSuites.hashSigAlgoSz > extSz)
+                            return BUFFER_ERROR;
+
+                        XMEMCPY(clSuites.hashSigAlgo, &input[i],
+                            min(clSuites.hashSigAlgoSz, HELLO_EXT_SIGALGO_MAX));
+                        i += clSuites.hashSigAlgoSz;
+
+                        if (clSuites.hashSigAlgoSz > HELLO_EXT_SIGALGO_MAX)
+                            clSuites.hashSigAlgoSz = HELLO_EXT_SIGALGO_MAX;
+                    }
+                    else
+                        i += extSz;
+
+                    totalExtSz -= OPAQUE16_LEN + OPAQUE16_LEN + extSz;
+                }
+#endif
+                *inOutIdx = i;
+            }
+            else
+                *inOutIdx = begin + helloSz; /* skip extensions */
+        }
+
+        ssl->options.clientState   = CLIENT_HELLO_COMPLETE;
+        ssl->options.haveSessionId = 1;
+
+        /* ProcessOld uses same resume code */
+        if (ssl->options.resuming && (!ssl->options.dtls ||
+               ssl->options.acceptState == HELLO_VERIFY_SENT)) { /* let's try */
+            int ret = -1;
+            WOLFSSL_SESSION* session = GetSession(ssl,
+                                                  ssl->arrays->masterSecret);
+            #ifdef HAVE_SESSION_TICKET
+                if (ssl->options.useTicket == 1) {
+                    session = &ssl->session;
+                }
+            #endif
+
+            if (!session) {
+                WOLFSSL_MSG("Session lookup for resume failed");
+                ssl->options.resuming = 0;
+            }
+            else {
+                if (MatchSuite(ssl, &clSuites) < 0) {
+                    WOLFSSL_MSG("Unsupported cipher suite, ClientHello");
+                    return UNSUPPORTED_SUITE;
+                }
+                #ifdef SESSION_CERTS
+                    ssl->session = *session; /* restore session certs. */
+                #endif
+
+                ret = wc_RNG_GenerateBlock(ssl->rng, ssl->arrays->serverRandom,
+                                                                       RAN_LEN);
+                if (ret != 0)
+                    return ret;
+
+                #ifdef NO_OLD_TLS
+                    ret = DeriveTlsKeys(ssl);
+                #else
+                    #ifndef NO_TLS
+                        if (ssl->options.tls)
+                            ret = DeriveTlsKeys(ssl);
+                    #endif
+                        if (!ssl->options.tls)
+                            ret = DeriveKeys(ssl);
+                #endif
+                ssl->options.clientState = CLIENT_KEYEXCHANGE_COMPLETE;
+
+                return ret;
+            }
+        }
+        return MatchSuite(ssl, &clSuites);
+    }
+
+#if !defined(NO_RSA) || defined(HAVE_ECC)
+    static int DoCertificateVerify(WOLFSSL* ssl, byte* input, word32* inOutIdx,
+                                   word32 size)
+    {
+        word16      sz = 0;
+        int         ret = VERIFY_CERT_ERROR;   /* start in error state */
+        byte        hashAlgo = sha_mac;
+        byte        sigAlgo = anonymous_sa_algo;
+        word32      begin = *inOutIdx;
+
+        #ifdef WOLFSSL_CALLBACKS
+            if (ssl->hsInfoOn)
+                AddPacketName("CertificateVerify", &ssl->handShakeInfo);
+            if (ssl->toInfoOn)
+                AddLateName("CertificateVerify", &ssl->timeoutInfo);
+        #endif
+
+
+        if (IsAtLeastTLSv1_2(ssl)) {
+            if ((*inOutIdx - begin) + ENUM_LEN + ENUM_LEN > size)
+                return BUFFER_ERROR;
+
+            hashAlgo = input[(*inOutIdx)++];
+            sigAlgo  = input[(*inOutIdx)++];
+        }
+
+        if ((*inOutIdx - begin) + OPAQUE16_LEN > size)
+            return BUFFER_ERROR;
+
+        ato16(input + *inOutIdx, &sz);
+        *inOutIdx += OPAQUE16_LEN;
+
+        if ((*inOutIdx - begin) + sz > size || sz > ENCRYPT_LEN)
+            return BUFFER_ERROR;
+
+        /* RSA */
+#ifndef NO_RSA
+        if (ssl->peerRsaKey != NULL && ssl->peerRsaKeyPresent != 0) {
+            byte* out       = NULL;
+            int   outLen    = 0;
+            byte  doUserRsa = 0;
+
+            #ifdef HAVE_PK_CALLBACKS
+                if (ssl->ctx->RsaVerifyCb)
+                    doUserRsa = 1;
+            #endif /*HAVE_PK_CALLBACKS */
+
+            WOLFSSL_MSG("Doing RSA peer cert verify");
+
+            if (doUserRsa) {
+            #ifdef HAVE_PK_CALLBACKS
+                outLen = ssl->ctx->RsaVerifyCb(ssl, input + *inOutIdx, sz,
+                                            &out,
+                                            ssl->buffers.peerRsaKey.buffer,
+                                            ssl->buffers.peerRsaKey.length,
+                                            ssl->RsaVerifyCtx);
+            #endif /*HAVE_PK_CALLBACKS */
+            }
+            else {
+                outLen = wc_RsaSSL_VerifyInline(input + *inOutIdx, sz, &out,
+                                                               ssl->peerRsaKey);
+            }
+
+            if (IsAtLeastTLSv1_2(ssl)) {
+#ifdef WOLFSSL_SMALL_STACK
+                byte*  encodedSig = NULL;
+#else
+                byte   encodedSig[MAX_ENCODED_SIG_SZ];
+#endif
+                word32 sigSz;
+                byte*  digest = ssl->hsHashes->certHashes.sha;
+                int    typeH = SHAh;
+                int    digestSz = SHA_DIGEST_SIZE;
+
+#ifdef WOLFSSL_SMALL_STACK
+                encodedSig = (byte*)XMALLOC(MAX_ENCODED_SIG_SZ, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+                if (encodedSig == NULL)
+                    return MEMORY_E;
+#endif
+
+                if (sigAlgo != rsa_sa_algo) {
+                    WOLFSSL_MSG("Oops, peer sent RSA key but not in verify");
+                }
+
+                if (hashAlgo == sha256_mac) {
+                    #ifndef NO_SHA256
+                        digest = ssl->hsHashes->certHashes.sha256;
+                        typeH    = SHA256h;
+                        digestSz = SHA256_DIGEST_SIZE;
+                    #endif
+                }
+                else if (hashAlgo == sha384_mac) {
+                    #ifdef WOLFSSL_SHA384
+                        digest = ssl->hsHashes->certHashes.sha384;
+                        typeH    = SHA384h;
+                        digestSz = SHA384_DIGEST_SIZE;
+                    #endif
+                }
+                else if (hashAlgo == sha512_mac) {
+                    #ifdef WOLFSSL_SHA512
+                        digest = ssl->hsHashes->certHashes.sha512;
+                        typeH    = SHA512h;
+                        digestSz = SHA512_DIGEST_SIZE;
+                    #endif
+                }
+
+                sigSz = wc_EncodeSignature(encodedSig, digest, digestSz, typeH);
+
+                if (outLen == (int)sigSz && out && XMEMCMP(out, encodedSig,
+                                           min(sigSz, MAX_ENCODED_SIG_SZ)) == 0)
+                    ret = 0; /* verified */
+
+#ifdef WOLFSSL_SMALL_STACK
+                XFREE(encodedSig, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            }
+            else {
+                if (outLen == FINISHED_SZ && out && XMEMCMP(out,
+                                            &ssl->hsHashes->certHashes,
+                                            FINISHED_SZ) == 0) {
+                    ret = 0; /* verified */
+                }
+            }
+        }
+#endif
+#ifdef HAVE_ECC
+        if (ssl->peerEccDsaKeyPresent) {
+            int verify =  0;
+            int err    = -1;
+            byte* digest = ssl->hsHashes->certHashes.sha;
+            word32 digestSz = SHA_DIGEST_SIZE;
+            byte doUserEcc = 0;
+
+            #ifdef HAVE_PK_CALLBACKS
+                if (ssl->ctx->EccVerifyCb)
+                    doUserEcc = 1;
+            #endif
+
+            WOLFSSL_MSG("Doing ECC peer cert verify");
+
+            if (IsAtLeastTLSv1_2(ssl)) {
+                if (sigAlgo != ecc_dsa_sa_algo) {
+                    WOLFSSL_MSG("Oops, peer sent ECC key but not in verify");
+                }
+
+                if (hashAlgo == sha256_mac) {
+                    #ifndef NO_SHA256
+                        digest = ssl->hsHashes->certHashes.sha256;
+                        digestSz = SHA256_DIGEST_SIZE;
+                    #endif
+                }
+                else if (hashAlgo == sha384_mac) {
+                    #ifdef WOLFSSL_SHA384
+                        digest = ssl->hsHashes->certHashes.sha384;
+                        digestSz = SHA384_DIGEST_SIZE;
+                    #endif
+                }
+                else if (hashAlgo == sha512_mac) {
+                    #ifdef WOLFSSL_SHA512
+                        digest = ssl->hsHashes->certHashes.sha512;
+                        digestSz = SHA512_DIGEST_SIZE;
+                    #endif
+                }
+            }
+
+            if (doUserEcc) {
+            #ifdef HAVE_PK_CALLBACKS
+                ret = ssl->ctx->EccVerifyCb(ssl, input + *inOutIdx, sz, digest,
+                                            digestSz,
+                                            ssl->buffers.peerEccDsaKey.buffer,
+                                            ssl->buffers.peerEccDsaKey.length,
+                                            &verify, ssl->EccVerifyCtx);
+            #endif
+            }
+            else {
+                err = wc_ecc_verify_hash(input + *inOutIdx, sz, digest,
+                                         digestSz, &verify, ssl->peerEccDsaKey);
+            }
+
+            if (err == 0 && verify == 1)
+               ret = 0; /* verified */
+        }
+#endif
+        *inOutIdx += sz;
+
+        if (ret == 0)
+            ssl->options.havePeerVerify = 1;
+
+        return ret;
+    }
+#endif /* !NO_RSA || HAVE_ECC */
+
+    int SendServerHelloDone(WOLFSSL* ssl)
+    {
+        byte              *output;
+        int                sendSz = RECORD_HEADER_SZ + HANDSHAKE_HEADER_SZ;
+        int                ret;
+
+        #ifdef WOLFSSL_DTLS
+            if (ssl->options.dtls)
+                sendSz += DTLS_RECORD_EXTRA + DTLS_HANDSHAKE_EXTRA;
+        #endif
+        /* check for available size */
+        if ((ret = CheckAvailableSize(ssl, sendSz)) != 0)
+            return ret;
+
+        /* get ouput buffer */
+        output = ssl->buffers.outputBuffer.buffer +
+                 ssl->buffers.outputBuffer.length;
+
+        AddHeaders(output, 0, server_hello_done, ssl);
+
+        #ifdef WOLFSSL_DTLS
+            if (ssl->options.dtls) {
+                if ((ret = DtlsPoolSave(ssl, output, sendSz)) != 0)
+                    return 0;
+            }
+        #endif
+
+        ret = HashOutput(ssl, output, sendSz, 0);
+            if (ret != 0)
+                return ret;
+
+#ifdef WOLFSSL_CALLBACKS
+        if (ssl->hsInfoOn)
+            AddPacketName("ServerHelloDone", &ssl->handShakeInfo);
+        if (ssl->toInfoOn)
+            AddPacketInfo("ServerHelloDone", &ssl->timeoutInfo, output, sendSz,
+                          ssl->heap);
+#endif
+        ssl->options.serverState = SERVER_HELLODONE_COMPLETE;
+
+        ssl->buffers.outputBuffer.length += sendSz;
+
+        return SendBuffered(ssl);
+    }
+
+
+#ifdef HAVE_SESSION_TICKET
+
+#define WOLFSSL_TICKET_FIXED_SZ (WOLFSSL_TICKET_NAME_SZ + \
+                WOLFSSL_TICKET_IV_SZ + WOLFSSL_TICKET_MAC_SZ + LENGTH_SZ)
+#define WOLFSSL_TICKET_ENC_SZ (SESSION_TICKET_LEN - WOLFSSL_TICKET_FIXED_SZ)
+
+    /* our ticket format */
+    typedef struct InternalTicket {
+        ProtocolVersion pv;                    /* version when ticket created */
+        byte            suite[SUITE_LEN];      /* cipher suite when created */
+        byte            msecret[SECRET_LEN];   /* master secret */
+        word32          timestamp;             /* born on */
+    } InternalTicket;
+
+    /* fit within SESSION_TICKET_LEN */
+    typedef struct ExternalTicket {
+        byte key_name[WOLFSSL_TICKET_NAME_SZ];  /* key context name */
+        byte iv[WOLFSSL_TICKET_IV_SZ];          /* this ticket's iv */
+        byte enc_len[LENGTH_SZ];                /* encrypted length */
+        byte enc_ticket[WOLFSSL_TICKET_ENC_SZ]; /* encrypted internal ticket */
+        byte mac[WOLFSSL_TICKET_MAC_SZ];        /* total mac */
+        /* !! if add to structure, add to TICKET_FIXED_SZ !! */
+    } ExternalTicket;
+
+    /* create a new session ticket, 0 on success */
+    static int CreateTicket(WOLFSSL* ssl)
+    {
+        InternalTicket  it;
+        ExternalTicket* et = (ExternalTicket*)ssl->session.ticket;
+        int encLen;
+        int ret;
+        byte zeros[WOLFSSL_TICKET_MAC_SZ];   /* biggest cmp size */
+
+        /* build internal */
+        it.pv.major = ssl->version.major;
+        it.pv.minor = ssl->version.minor;
+
+        it.suite[0] = ssl->options.cipherSuite0;
+        it.suite[1] = ssl->options.cipherSuite;
+
+        XMEMCPY(it.msecret, ssl->arrays->masterSecret, SECRET_LEN);
+        c32toa(LowResTimer(), (byte*)&it.timestamp);
+
+        /* build external */
+        XMEMCPY(et->enc_ticket, &it, sizeof(InternalTicket));
+
+        /* encrypt */
+        encLen = WOLFSSL_TICKET_ENC_SZ;  /* max size user can use */
+        ret = ssl->ctx->ticketEncCb(ssl, et->key_name, et->iv, et->mac, 1,
+                                    et->enc_ticket, sizeof(InternalTicket),
+                                    &encLen, ssl->ctx->ticketEncCtx);
+        if (ret == WOLFSSL_TICKET_RET_OK) {
+            if (encLen < (int)sizeof(InternalTicket) ||
+                encLen > WOLFSSL_TICKET_ENC_SZ) {
+                WOLFSSL_MSG("Bad user ticket encrypt size");
+                return BAD_TICKET_KEY_CB_SZ;
+            }
+
+            /* sanity checks on encrypt callback */
+
+            /* internal ticket can't be the same if encrypted */
+            if (XMEMCMP(et->enc_ticket, &it, sizeof(InternalTicket)) == 0) {
+                WOLFSSL_MSG("User ticket encrypt didn't encrypt");
+                return BAD_TICKET_ENCRYPT;
+            }
+
+            XMEMSET(zeros, 0, sizeof(zeros));
+
+            /* name */
+            if (XMEMCMP(et->key_name, zeros, WOLFSSL_TICKET_NAME_SZ) == 0) {
+                WOLFSSL_MSG("User ticket encrypt didn't set name");
+                return BAD_TICKET_ENCRYPT;
+            }
+
+            /* iv */
+            if (XMEMCMP(et->iv, zeros, WOLFSSL_TICKET_IV_SZ) == 0) {
+                WOLFSSL_MSG("User ticket encrypt didn't set iv");
+                return BAD_TICKET_ENCRYPT;
+            }
+
+            /* mac */
+            if (XMEMCMP(et->mac, zeros, WOLFSSL_TICKET_MAC_SZ) == 0) {
+                WOLFSSL_MSG("User ticket encrypt didn't set mac");
+                return BAD_TICKET_ENCRYPT;
+            }
+
+            /* set size */
+            c16toa((word16)encLen, et->enc_len);
+            ssl->session.ticketLen = (word16)(encLen + WOLFSSL_TICKET_FIXED_SZ);
+            if (encLen < WOLFSSL_TICKET_ENC_SZ) {
+                /* move mac up since whole enc buffer not used */
+                XMEMMOVE(et->enc_ticket +encLen, et->mac,WOLFSSL_TICKET_MAC_SZ);
+            }
+        }
+
+        return ret;
+    }
+
+
+    /* Parse ticket sent by client, returns callback return value */
+    int DoClientTicket(WOLFSSL* ssl, const byte* input, word32 len)
+    {
+        ExternalTicket* et;
+        InternalTicket* it;
+        int             ret;
+        int             outLen;
+        word16          inLen;
+
+        if (len > SESSION_TICKET_LEN ||
+             len < (word32)(sizeof(InternalTicket) + WOLFSSL_TICKET_FIXED_SZ)) {
+            return BAD_TICKET_MSG_SZ;
+        }
+
+        et = (ExternalTicket*)input;
+        it = (InternalTicket*)et->enc_ticket;
+
+        /* decrypt */
+        ato16(et->enc_len, &inLen);
+        if (inLen > (word16)(len - WOLFSSL_TICKET_FIXED_SZ)) {
+            return BAD_TICKET_MSG_SZ;
+        }
+        outLen = inLen;   /* may be reduced by user padding */
+        ret = ssl->ctx->ticketEncCb(ssl, et->key_name, et->iv,
+                                    et->enc_ticket + inLen, 0,
+                                    et->enc_ticket, inLen, &outLen,
+                                    ssl->ctx->ticketEncCtx);
+        if (ret == WOLFSSL_TICKET_RET_FATAL || ret < 0) return ret;
+        if (outLen > inLen || outLen < (int)sizeof(InternalTicket)) {
+            WOLFSSL_MSG("Bad user ticket decrypt len");
+            return BAD_TICKET_KEY_CB_SZ;
+        }
+
+        /* get master secret */
+        if (ret == WOLFSSL_TICKET_RET_OK || ret == WOLFSSL_TICKET_RET_CREATE)
+            XMEMCPY(ssl->arrays->masterSecret, it->msecret, SECRET_LEN);
+
+        return ret;
+    }
+
+
+    /* send Session Ticket */
+    int SendTicket(WOLFSSL* ssl)
+    {
+        byte*              output;
+        int                ret;
+        int                sendSz;
+        word32             length = SESSION_HINT_SZ + LENGTH_SZ;
+        word32             idx    = RECORD_HEADER_SZ + HANDSHAKE_HEADER_SZ;
+
+    #ifdef WOLFSSL_DTLS
+        if (ssl->options.dtls) {
+            length += DTLS_RECORD_EXTRA;
+            idx    += DTLS_RECORD_EXTRA;
+        }
+    #endif
+
+        if (ssl->options.createTicket) {
+            ret = CreateTicket(ssl);
+            if (ret != 0) return ret;
+        }
+
+        length += ssl->session.ticketLen;
+        sendSz = length + HANDSHAKE_HEADER_SZ + RECORD_HEADER_SZ;
+
+        /* check for available size */
+        if ((ret = CheckAvailableSize(ssl, sendSz)) != 0)
+            return ret;
+
+        /* get ouput buffer */
+        output = ssl->buffers.outputBuffer.buffer +
+                 ssl->buffers.outputBuffer.length;
+
+        AddHeaders(output, length, session_ticket, ssl);
+
+        /* hint */
+        c32toa(ssl->ctx->ticketHint, output + idx);
+        idx += SESSION_HINT_SZ;
+
+        /* length */
+        c16toa(ssl->session.ticketLen, output + idx);
+        idx += LENGTH_SZ;
+
+        /* ticket */
+        XMEMCPY(output + idx, ssl->session.ticket, ssl->session.ticketLen);
+        /* idx += ssl->session.ticketLen; */
+
+        ret = HashOutput(ssl, output, sendSz, 0);
+        if (ret != 0) return ret;
+        ssl->buffers.outputBuffer.length += sendSz;
+
+        return SendBuffered(ssl);
+    }
+
+#endif /* HAVE_SESSION_TICKET */
+
+
+#ifdef WOLFSSL_DTLS
+    int SendHelloVerifyRequest(WOLFSSL* ssl)
+    {
+        byte* output;
+        byte  cookieSz = COOKIE_SZ;
+        int   length = VERSION_SZ + ENUM_LEN + cookieSz;
+        int   idx    = DTLS_RECORD_HEADER_SZ + DTLS_HANDSHAKE_HEADER_SZ;
+        int   sendSz = length + idx;
+        int   ret;
+
+        /* check for available size */
+        if ((ret = CheckAvailableSize(ssl, sendSz)) != 0)
+            return ret;
+
+        /* get ouput buffer */
+        output = ssl->buffers.outputBuffer.buffer +
+                 ssl->buffers.outputBuffer.length;
+
+        AddHeaders(output, length, hello_verify_request, ssl);
+
+        output[idx++] =  ssl->chVersion.major;
+        output[idx++] =  ssl->chVersion.minor;
+
+        output[idx++] = cookieSz;
+        if (ssl->ctx->CBIOCookie == NULL) {
+            WOLFSSL_MSG("Your Cookie callback is null, please set");
+            return COOKIE_ERROR;
+        }
+        if ((ret = ssl->ctx->CBIOCookie(ssl, output + idx, cookieSz,
+                                        ssl->IOCB_CookieCtx)) < 0)
+            return ret;
+
+        ret = HashOutput(ssl, output, sendSz, 0);
+        if (ret != 0)
+            return ret;
+
+#ifdef WOLFSSL_CALLBACKS
+        if (ssl->hsInfoOn)
+            AddPacketName("HelloVerifyRequest", &ssl->handShakeInfo);
+        if (ssl->toInfoOn)
+            AddPacketInfo("HelloVerifyRequest", &ssl->timeoutInfo, output,
+                          sendSz, ssl->heap);
+#endif
+        ssl->options.serverState = SERVER_HELLOVERIFYREQUEST_COMPLETE;
+
+        ssl->buffers.outputBuffer.length += sendSz;
+
+        return SendBuffered(ssl);
+    }
+#endif
+
+    static int DoClientKeyExchange(WOLFSSL* ssl, byte* input, word32* inOutIdx,
+                                                                    word32 size)
+    {
+        int    ret = 0;
+        word32 length = 0;
+        byte*  out = NULL;
+        word32 begin = *inOutIdx;
+
+        (void)length; /* shut up compiler warnings */
+        (void)out;
+        (void)input;
+        (void)size;
+        (void)begin;
+
+        if (ssl->options.side != WOLFSSL_SERVER_END) {
+            WOLFSSL_MSG("Client received client keyexchange, attack?");
+            WOLFSSL_ERROR(ssl->error = SIDE_ERROR);
+            return SSL_FATAL_ERROR;
+        }
+
+        if (ssl->options.clientState < CLIENT_HELLO_COMPLETE) {
+            WOLFSSL_MSG("Client sending keyexchange at wrong time");
+            SendAlert(ssl, alert_fatal, unexpected_message);
+            return OUT_OF_ORDER_E;
+        }
+
+        #ifndef NO_CERTS
+            if (ssl->options.verifyPeer && ssl->options.failNoCert)
+                if (!ssl->options.havePeerCert) {
+                    WOLFSSL_MSG("client didn't present peer cert");
+                    return NO_PEER_CERT;
+                }
+        #endif
+
+        #ifdef WOLFSSL_CALLBACKS
+            if (ssl->hsInfoOn)
+                AddPacketName("ClientKeyExchange", &ssl->handShakeInfo);
+            if (ssl->toInfoOn)
+                AddLateName("ClientKeyExchange", &ssl->timeoutInfo);
+        #endif
+
+        switch (ssl->specs.kea) {
+        #ifndef NO_RSA
+            case rsa_kea:
+            {
+                word32 idx = 0;
+                RsaKey key;
+                byte   doUserRsa = 0;
+
+                #ifdef HAVE_PK_CALLBACKS
+                    if (ssl->ctx->RsaDecCb)
+                        doUserRsa = 1;
+                #endif
+
+                ret = wc_InitRsaKey(&key, ssl->heap);
+                if (ret != 0) return ret;
+
+                if (ssl->buffers.key.buffer)
+                    ret = wc_RsaPrivateKeyDecode(ssl->buffers.key.buffer, &idx,
+                                             &key, ssl->buffers.key.length);
+                else
+                    return NO_PRIVATE_KEY;
+
+                if (ret == 0) {
+                    length = wc_RsaEncryptSize(&key);
+                    ssl->arrays->preMasterSz = SECRET_LEN;
+
+                    if (ssl->options.tls) {
+                        word16 check;
+
+                        if ((*inOutIdx - begin) + OPAQUE16_LEN > size)
+                            return BUFFER_ERROR;
+
+                        ato16(input + *inOutIdx, &check);
+                        *inOutIdx += OPAQUE16_LEN;
+
+                        if ((word32) check != length) {
+                            WOLFSSL_MSG("RSA explicit size doesn't match");
+                            wc_FreeRsaKey(&key);
+                            return RSA_PRIVATE_ERROR;
+                        }
+                    }
+
+                    if ((*inOutIdx - begin) + length > size) {
+                        WOLFSSL_MSG("RSA message too big");
+                        wc_FreeRsaKey(&key);
+                        return BUFFER_ERROR;
+                    }
+
+                    if (doUserRsa) {
+                        #ifdef HAVE_PK_CALLBACKS
+                            ret = ssl->ctx->RsaDecCb(ssl,
+                                        input + *inOutIdx, length, &out,
+                                        ssl->buffers.key.buffer,
+                                        ssl->buffers.key.length,
+                                        ssl->RsaDecCtx);
+                        #endif
+                    }
+                    else {
+                        ret = wc_RsaPrivateDecryptInline(input + *inOutIdx, length,
+                                                                    &out, &key);
+                    }
+
+                    *inOutIdx += length;
+
+                    if (ret == SECRET_LEN) {
+                        XMEMCPY(ssl->arrays->preMasterSecret, out, SECRET_LEN);
+                        if (ssl->arrays->preMasterSecret[0] !=
+                                                           ssl->chVersion.major
+                            || ssl->arrays->preMasterSecret[1] !=
+                                                           ssl->chVersion.minor)
+                            ret = PMS_VERSION_ERROR;
+                        else
+                            ret = MakeMasterSecret(ssl);
+                    }
+                    else {
+                        ret = RSA_PRIVATE_ERROR;
+                    }
+                }
+
+                wc_FreeRsaKey(&key);
+            }
+            break;
+        #endif
+        #ifndef NO_PSK
+            case psk_kea:
+            {
+                byte* pms = ssl->arrays->preMasterSecret;
+                word16 ci_sz;
+
+                if ((*inOutIdx - begin) + OPAQUE16_LEN > size)
+                    return BUFFER_ERROR;
+
+                ato16(input + *inOutIdx, &ci_sz);
+                *inOutIdx += OPAQUE16_LEN;
+
+                if (ci_sz > MAX_PSK_ID_LEN)
+                    return CLIENT_ID_ERROR;
+
+                if ((*inOutIdx - begin) + ci_sz > size)
+                    return BUFFER_ERROR;
+
+                XMEMCPY(ssl->arrays->client_identity, input + *inOutIdx, ci_sz);
+                *inOutIdx += ci_sz;
+
+                ssl->arrays->client_identity[min(ci_sz, MAX_PSK_ID_LEN-1)] = 0;
+                ssl->arrays->psk_keySz = ssl->options.server_psk_cb(ssl,
+                    ssl->arrays->client_identity, ssl->arrays->psk_key,
+                    MAX_PSK_KEY_LEN);
+
+                if (ssl->arrays->psk_keySz == 0 ||
+                                       ssl->arrays->psk_keySz > MAX_PSK_KEY_LEN)
+                    return PSK_KEY_ERROR;
+
+                /* make psk pre master secret */
+                /* length of key + length 0s + length of key + key */
+                c16toa((word16) ssl->arrays->psk_keySz, pms);
+                pms += OPAQUE16_LEN;
+
+                XMEMSET(pms, 0, ssl->arrays->psk_keySz);
+                pms += ssl->arrays->psk_keySz;
+
+                c16toa((word16) ssl->arrays->psk_keySz, pms);
+                pms += OPAQUE16_LEN;
+
+                XMEMCPY(pms, ssl->arrays->psk_key, ssl->arrays->psk_keySz);
+                ssl->arrays->preMasterSz = ssl->arrays->psk_keySz * 2 + 4;
+
+                ret = MakeMasterSecret(ssl);
+
+                /* No further need for PSK */
+                ForceZero(ssl->arrays->psk_key, ssl->arrays->psk_keySz);
+                ssl->arrays->psk_keySz = 0;
+            }
+            break;
+        #endif /* NO_PSK */
+        #ifdef HAVE_NTRU
+            case ntru_kea:
+            {
+                word16 cipherLen;
+                word16 plainLen = sizeof(ssl->arrays->preMasterSecret);
+
+                if (!ssl->buffers.key.buffer)
+                    return NO_PRIVATE_KEY;
+
+                if ((*inOutIdx - begin) + OPAQUE16_LEN > size)
+                    return BUFFER_ERROR;
+
+                ato16(input + *inOutIdx, &cipherLen);
+                *inOutIdx += OPAQUE16_LEN;
+
+                if (cipherLen > MAX_NTRU_ENCRYPT_SZ)
+                    return NTRU_KEY_ERROR;
+
+                if ((*inOutIdx - begin) + cipherLen > size)
+                    return BUFFER_ERROR;
+
+                if (NTRU_OK != ntru_crypto_ntru_decrypt(
+                            (word16) ssl->buffers.key.length,
+                            ssl->buffers.key.buffer, cipherLen,
+                            input + *inOutIdx, &plainLen,
+                            ssl->arrays->preMasterSecret))
+                    return NTRU_DECRYPT_ERROR;
+
+                if (plainLen != SECRET_LEN)
+                    return NTRU_DECRYPT_ERROR;
+
+                *inOutIdx += cipherLen;
+
+                ssl->arrays->preMasterSz = plainLen;
+                ret = MakeMasterSecret(ssl);
+            }
+            break;
+        #endif /* HAVE_NTRU */
+        #ifdef HAVE_ECC
+            case ecc_diffie_hellman_kea:
+            {
+                if ((*inOutIdx - begin) + OPAQUE8_LEN > size)
+                    return BUFFER_ERROR;
+
+                length = input[(*inOutIdx)++];
+
+                if ((*inOutIdx - begin) + length > size)
+                    return BUFFER_ERROR;
+
+                if (ssl->peerEccKey == NULL) {
+                    /* alloc/init on demand */
+                    ssl->peerEccKey = (ecc_key*)XMALLOC(sizeof(ecc_key),
+                                              ssl->ctx->heap, DYNAMIC_TYPE_ECC);
+                    if (ssl->peerEccKey == NULL) {
+                        WOLFSSL_MSG("PeerEccKey Memory error");
+                        return MEMORY_E;
+                    }
+                    wc_ecc_init(ssl->peerEccKey);
+                } else if (ssl->peerEccKeyPresent) {  /* don't leak on reuse */
+                    wc_ecc_free(ssl->peerEccKey);
+                    ssl->peerEccKeyPresent = 0;
+                    wc_ecc_init(ssl->peerEccKey);
+                }
+
+                if (wc_ecc_import_x963(input + *inOutIdx, length, ssl->peerEccKey))
+                    return ECC_PEERKEY_ERROR;
+
+                *inOutIdx += length;
+                ssl->peerEccKeyPresent = 1;
+
+                length = sizeof(ssl->arrays->preMasterSecret);
+
+                if (ssl->specs.static_ecdh) {
+                    ecc_key staticKey;
+                    word32 i = 0;
+
+                    wc_ecc_init(&staticKey);
+                    ret = wc_EccPrivateKeyDecode(ssl->buffers.key.buffer, &i,
+                                           &staticKey, ssl->buffers.key.length);
+
+                    if (ret == 0)
+                        ret = wc_ecc_shared_secret(&staticKey, ssl->peerEccKey,
+                                         ssl->arrays->preMasterSecret, &length);
+
+                    wc_ecc_free(&staticKey);
+                }
+                else {
+                    if (ssl->eccTempKeyPresent == 0) {
+                        WOLFSSL_MSG("Ecc ephemeral key not made correctly");
+                        ret = ECC_MAKEKEY_ERROR;
+                    } else {
+                        ret = wc_ecc_shared_secret(ssl->eccTempKey,ssl->peerEccKey,
+                                         ssl->arrays->preMasterSecret, &length);
+                    }
+                }
+
+                if (ret != 0)
+                    return ECC_SHARED_ERROR;
+
+                ssl->arrays->preMasterSz = length;
+                ret = MakeMasterSecret(ssl);
+            }
+            break;
+        #endif /* HAVE_ECC */
+        #ifndef NO_DH
+            case diffie_hellman_kea:
+            {
+                word16 clientPubSz;
+                DhKey  dhKey;
+
+                if ((*inOutIdx - begin) + OPAQUE16_LEN > size)
+                    return BUFFER_ERROR;
+
+                ato16(input + *inOutIdx, &clientPubSz);
+                *inOutIdx += OPAQUE16_LEN;
+
+                if ((*inOutIdx - begin) + clientPubSz > size)
+                    return BUFFER_ERROR;
+
+                wc_InitDhKey(&dhKey);
+                ret = wc_DhSetKey(&dhKey, ssl->buffers.serverDH_P.buffer,
+                                       ssl->buffers.serverDH_P.length,
+                                       ssl->buffers.serverDH_G.buffer,
+                                       ssl->buffers.serverDH_G.length);
+                if (ret == 0)
+                    ret = wc_DhAgree(&dhKey, ssl->arrays->preMasterSecret,
+                                         &ssl->arrays->preMasterSz,
+                                          ssl->buffers.serverDH_Priv.buffer,
+                                          ssl->buffers.serverDH_Priv.length,
+                                          input + *inOutIdx, clientPubSz);
+                wc_FreeDhKey(&dhKey);
+
+                *inOutIdx += clientPubSz;
+
+                if (ret == 0)
+                    ret = MakeMasterSecret(ssl);
+            }
+            break;
+        #endif /* NO_DH */
+        #if !defined(NO_DH) && !defined(NO_PSK)
+            case dhe_psk_kea:
+            {
+                byte* pms = ssl->arrays->preMasterSecret;
+                word16 clientSz;
+                DhKey  dhKey;
+
+                /* Read in the PSK hint */
+                if ((*inOutIdx - begin) + OPAQUE16_LEN > size)
+                    return BUFFER_ERROR;
+
+                ato16(input + *inOutIdx, &clientSz);
+                *inOutIdx += OPAQUE16_LEN;
+                if (clientSz > MAX_PSK_ID_LEN)
+                    return CLIENT_ID_ERROR;
+
+                if ((*inOutIdx - begin) + clientSz > size)
+                    return BUFFER_ERROR;
+
+                XMEMCPY(ssl->arrays->client_identity,
+                                                   input + *inOutIdx, clientSz);
+                *inOutIdx += clientSz;
+                ssl->arrays->client_identity[min(clientSz, MAX_PSK_ID_LEN-1)] =
+                                                                              0;
+
+                /* Read in the DHE business */
+                if ((*inOutIdx - begin) + OPAQUE16_LEN > size)
+                    return BUFFER_ERROR;
+
+                ato16(input + *inOutIdx, &clientSz);
+                *inOutIdx += OPAQUE16_LEN;
+
+                if ((*inOutIdx - begin) + clientSz > size)
+                    return BUFFER_ERROR;
+
+                wc_InitDhKey(&dhKey);
+                ret = wc_DhSetKey(&dhKey, ssl->buffers.serverDH_P.buffer,
+                                       ssl->buffers.serverDH_P.length,
+                                       ssl->buffers.serverDH_G.buffer,
+                                       ssl->buffers.serverDH_G.length);
+                if (ret == 0)
+                    ret = wc_DhAgree(&dhKey, pms + OPAQUE16_LEN,
+                                          &ssl->arrays->preMasterSz,
+                                          ssl->buffers.serverDH_Priv.buffer,
+                                          ssl->buffers.serverDH_Priv.length,
+                                          input + *inOutIdx, clientSz);
+                wc_FreeDhKey(&dhKey);
+
+                *inOutIdx += clientSz;
+                c16toa((word16)ssl->arrays->preMasterSz, pms);
+                ssl->arrays->preMasterSz += OPAQUE16_LEN;
+                pms += ssl->arrays->preMasterSz;
+
+                /* Use the PSK hint to look up the PSK and add it to the
+                 * preMasterSecret here. */
+                ssl->arrays->psk_keySz = ssl->options.server_psk_cb(ssl,
+                    ssl->arrays->client_identity, ssl->arrays->psk_key,
+                    MAX_PSK_KEY_LEN);
+
+                if (ssl->arrays->psk_keySz == 0 ||
+                                       ssl->arrays->psk_keySz > MAX_PSK_KEY_LEN)
+                    return PSK_KEY_ERROR;
+
+                c16toa((word16) ssl->arrays->psk_keySz, pms);
+                pms += OPAQUE16_LEN;
+
+                XMEMCPY(pms, ssl->arrays->psk_key, ssl->arrays->psk_keySz);
+                ssl->arrays->preMasterSz +=
+                                          ssl->arrays->psk_keySz + OPAQUE16_LEN;
+                if (ret == 0)
+                    ret = MakeMasterSecret(ssl);
+
+                /* No further need for PSK */
+                ForceZero(ssl->arrays->psk_key, ssl->arrays->psk_keySz);
+                ssl->arrays->psk_keySz = 0;
+            }
+            break;
+        #endif /* !NO_DH && !NO_PSK */
+            default:
+            {
+                WOLFSSL_MSG("Bad kea type");
+                ret = BAD_KEA_TYPE_E;
+            }
+            break;
+        }
+
+        /* No further need for PMS */
+        ForceZero(ssl->arrays->preMasterSecret, ssl->arrays->preMasterSz);
+        ssl->arrays->preMasterSz = 0;
+
+        if (ret == 0) {
+            ssl->options.clientState = CLIENT_KEYEXCHANGE_COMPLETE;
+            #ifndef NO_CERTS
+                if (ssl->options.verifyPeer)
+                    ret = BuildCertHashes(ssl, &ssl->hsHashes->certHashes);
+            #endif
+        }
+
+        return ret;
+    }
+
+#endif /* NO_WOLFSSL_SERVER */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/io.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/io.c
new file mode 100644
index 0000000..1950566
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/io.c
@@ -0,0 +1,1141 @@
+/* io.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifdef _WIN32_WCE
+    /* On WinCE winsock2.h must be included before windows.h for socket stuff */
+    #include 
+#endif
+
+#include 
+#include 
+
+
+/* if user writes own I/O callbacks they can define WOLFSSL_USER_IO to remove
+   automatic setting of default I/O functions EmbedSend() and EmbedReceive()
+   but they'll still need SetCallback xxx() at end of file 
+*/
+#ifndef WOLFSSL_USER_IO
+
+#ifdef HAVE_LIBZ
+    #include "zlib.h"
+#endif
+
+#ifndef USE_WINDOWS_API
+    #ifdef WOLFSSL_LWIP
+        /* lwIP needs to be configured to use sockets API in this mode */
+        /* LWIP_SOCKET 1 in lwip/opt.h or in build */
+        #include "lwip/sockets.h"
+        #include 
+        #ifndef LWIP_PROVIDE_ERRNO
+            #define LWIP_PROVIDE_ERRNO 1
+        #endif
+    #elif defined(FREESCALE_MQX)
+        #include 
+        #include 
+    #elif defined(WOLFSSL_MDK_ARM)
+        #if defined(WOLFSSL_MDK5)
+            #include "cmsis_os.h"
+            #include "rl_fs.h" 
+            #include "rl_net.h" 
+        #else
+            #include 
+        #endif
+        #undef RNG
+        #include "WOLFSSL_MDK_ARM.h"
+        #undef RNG
+        #define RNG wolfSSL_RNG 
+        /* for avoiding name conflict in "stm32f2xx.h" */
+        static int errno;
+    #elif defined(WOLFSSL_TIRTOS)
+        #include 
+    #elif defined(WOLFSSL_IAR_ARM)
+        /* nothing */
+    #else
+        #include 
+        #include 
+        #ifndef EBSNET
+            #include 
+        #endif
+        #include 
+        #if !(defined(DEVKITPRO) || defined(HAVE_RTP_SYS) || defined(EBSNET)) \
+            && !(defined(WOLFSSL_PICOTCP))
+            #include 
+            #include 
+            #include 
+            #include 
+            #ifdef __PPU
+                #include 
+            #else
+                #include 
+            #endif
+        #endif
+        #ifdef HAVE_RTP_SYS
+            #include 
+        #endif
+        #ifdef EBSNET
+            #include "rtipapi.h"  /* errno */
+            #include "socket.h"
+        #endif
+    #endif
+#endif /* USE_WINDOWS_API */
+
+#ifdef __sun
+    #include 
+#endif
+
+#ifdef USE_WINDOWS_API 
+    /* no epipe yet */
+    #ifndef WSAEPIPE
+        #define WSAEPIPE       -12345
+    #endif
+    #define SOCKET_EWOULDBLOCK WSAEWOULDBLOCK
+    #define SOCKET_EAGAIN      WSAETIMEDOUT
+    #define SOCKET_ECONNRESET  WSAECONNRESET
+    #define SOCKET_EINTR       WSAEINTR
+    #define SOCKET_EPIPE       WSAEPIPE
+    #define SOCKET_ECONNREFUSED WSAENOTCONN
+    #define SOCKET_ECONNABORTED WSAECONNABORTED
+    #define close(s) closesocket(s)
+#elif defined(__PPU)
+    #define SOCKET_EWOULDBLOCK SYS_NET_EWOULDBLOCK
+    #define SOCKET_EAGAIN      SYS_NET_EAGAIN
+    #define SOCKET_ECONNRESET  SYS_NET_ECONNRESET
+    #define SOCKET_EINTR       SYS_NET_EINTR
+    #define SOCKET_EPIPE       SYS_NET_EPIPE
+    #define SOCKET_ECONNREFUSED SYS_NET_ECONNREFUSED
+    #define SOCKET_ECONNABORTED SYS_NET_ECONNABORTED
+#elif defined(FREESCALE_MQX)
+    /* RTCS doesn't have an EWOULDBLOCK error */
+    #define SOCKET_EWOULDBLOCK EAGAIN
+    #define SOCKET_EAGAIN      EAGAIN
+    #define SOCKET_ECONNRESET  RTCSERR_TCP_CONN_RESET
+    #define SOCKET_EINTR       EINTR
+    #define SOCKET_EPIPE       EPIPE
+    #define SOCKET_ECONNREFUSED RTCSERR_TCP_CONN_REFUSED
+    #define SOCKET_ECONNABORTED RTCSERR_TCP_CONN_ABORTED
+#elif defined(WOLFSSL_MDK_ARM)
+    #if defined(WOLFSSL_MDK5)
+        #define SOCKET_EWOULDBLOCK BSD_ERROR_WOULDBLOCK
+        #define SOCKET_EAGAIN      BSD_ERROR_LOCKED
+        #define SOCKET_ECONNRESET  BSD_ERROR_CLOSED
+        #define SOCKET_EINTR       BSD_ERROR
+        #define SOCKET_EPIPE       BSD_ERROR
+        #define SOCKET_ECONNREFUSED BSD_ERROR
+        #define SOCKET_ECONNABORTED BSD_ERROR
+    #else
+        #define SOCKET_EWOULDBLOCK SCK_EWOULDBLOCK
+        #define SOCKET_EAGAIN      SCK_ELOCKED
+        #define SOCKET_ECONNRESET  SCK_ECLOSED
+        #define SOCKET_EINTR       SCK_ERROR
+        #define SOCKET_EPIPE       SCK_ERROR
+        #define SOCKET_ECONNREFUSED SCK_ERROR
+        #define SOCKET_ECONNABORTED SCK_ERROR
+    #endif
+#elif defined(WOLFSSL_PICOTCP)
+    #define SOCKET_EWOULDBLOCK  PICO_ERR_EAGAIN
+    #define SOCKET_EAGAIN       PICO_ERR_EAGAIN
+    #define SOCKET_ECONNRESET   PICO_ERR_ECONNRESET
+    #define SOCKET_EINTR        PICO_ERR_EINTR
+    #define SOCKET_EPIPE        PICO_ERR_EIO
+    #define SOCKET_ECONNREFUSED PICO_ERR_ECONNREFUSED
+    #define SOCKET_ECONNABORTED PICO_ERR_ESHUTDOWN
+#else
+    #define SOCKET_EWOULDBLOCK EWOULDBLOCK
+    #define SOCKET_EAGAIN      EAGAIN
+    #define SOCKET_ECONNRESET  ECONNRESET
+    #define SOCKET_EINTR       EINTR
+    #define SOCKET_EPIPE       EPIPE
+    #define SOCKET_ECONNREFUSED ECONNREFUSED
+    #define SOCKET_ECONNABORTED ECONNABORTED
+#endif /* USE_WINDOWS_API */
+
+
+#ifdef DEVKITPRO
+    /* from network.h */
+    int net_send(int, const void*, int, unsigned int);
+    int net_recv(int, void*, int, unsigned int);
+    #define SEND_FUNCTION net_send
+    #define RECV_FUNCTION net_recv
+#elif defined(WOLFSSL_LWIP)
+    #define SEND_FUNCTION lwip_send
+    #define RECV_FUNCTION lwip_recv
+#elif defined(WOLFSSL_PICOTCP)
+    #define SEND_FUNCTION pico_send
+    #define RECV_FUNCTION pico_recv
+#else
+    #define SEND_FUNCTION send
+    #define RECV_FUNCTION recv
+#endif
+
+
+/* Translates return codes returned from 
+ * send() and recv() if need be. 
+ */
+static INLINE int TranslateReturnCode(int old, int sd)
+{
+    (void)sd;
+
+#ifdef FREESCALE_MQX
+    if (old == 0) {
+        errno = SOCKET_EWOULDBLOCK;
+        return -1;  /* convert to BSD style wouldblock as error */
+    }
+
+    if (old < 0) {
+        errno = RTCS_geterror(sd);
+        if (errno == RTCSERR_TCP_CONN_CLOSING)
+            return 0;   /* convert to BSD style closing */
+    }
+#endif
+
+    return old;
+}
+
+static INLINE int LastError(void)
+{
+#ifdef USE_WINDOWS_API 
+    return WSAGetLastError();
+#elif defined(EBSNET)
+    return xn_getlasterror();
+#else
+    return errno;
+#endif
+}
+
+/* The receive embedded callback
+ *  return : nb bytes read, or error
+ */
+int EmbedReceive(WOLFSSL *ssl, char *buf, int sz, void *ctx)
+{
+    int recvd;
+    int err;
+    int sd = *(int*)ctx;
+
+#ifdef WOLFSSL_DTLS
+    {
+        int dtls_timeout = wolfSSL_dtls_get_current_timeout(ssl);
+        if (wolfSSL_dtls(ssl)
+                     && !wolfSSL_get_using_nonblock(ssl)
+                     && dtls_timeout != 0) {
+            #ifdef USE_WINDOWS_API
+                DWORD timeout = dtls_timeout * 1000;
+            #else
+                struct timeval timeout;
+                XMEMSET(&timeout, 0, sizeof(timeout));
+                timeout.tv_sec = dtls_timeout;
+            #endif
+            if (setsockopt(sd, SOL_SOCKET, SO_RCVTIMEO, (char*)&timeout,
+                           sizeof(timeout)) != 0) {
+                WOLFSSL_MSG("setsockopt rcvtimeo failed");
+            }
+        }
+    }
+#endif
+
+    recvd = (int)RECV_FUNCTION(sd, buf, sz, ssl->rflags);
+
+    recvd = TranslateReturnCode(recvd, sd);
+
+    if (recvd < 0) {
+        err = LastError();
+        WOLFSSL_MSG("Embed Receive error");
+
+        if (err == SOCKET_EWOULDBLOCK || err == SOCKET_EAGAIN) {
+            if (!wolfSSL_dtls(ssl) || wolfSSL_get_using_nonblock(ssl)) {
+                WOLFSSL_MSG("    Would block");
+                return WOLFSSL_CBIO_ERR_WANT_READ;
+            }
+            else {
+                WOLFSSL_MSG("    Socket timeout");
+                return WOLFSSL_CBIO_ERR_TIMEOUT;
+            }
+        }
+        else if (err == SOCKET_ECONNRESET) {
+            WOLFSSL_MSG("    Connection reset");
+            return WOLFSSL_CBIO_ERR_CONN_RST;
+        }
+        else if (err == SOCKET_EINTR) {
+            WOLFSSL_MSG("    Socket interrupted");
+            return WOLFSSL_CBIO_ERR_ISR;
+        }
+        else if (err == SOCKET_ECONNREFUSED) {
+            WOLFSSL_MSG("    Connection refused");
+            return WOLFSSL_CBIO_ERR_WANT_READ;
+        }
+        else if (err == SOCKET_ECONNABORTED) {
+            WOLFSSL_MSG("    Connection aborted");
+            return WOLFSSL_CBIO_ERR_CONN_CLOSE;
+        }
+        else {
+            WOLFSSL_MSG("    General error");
+            return WOLFSSL_CBIO_ERR_GENERAL;
+        }
+    }
+    else if (recvd == 0) {
+        WOLFSSL_MSG("Embed receive connection closed");
+        return WOLFSSL_CBIO_ERR_CONN_CLOSE;
+    }
+
+    return recvd;
+}
+
+/* The send embedded callback
+ *  return : nb bytes sent, or error
+ */
+int EmbedSend(WOLFSSL* ssl, char *buf, int sz, void *ctx)
+{
+    int sd = *(int*)ctx;
+    int sent;
+    int len = sz;
+    int err;
+
+    sent = (int)SEND_FUNCTION(sd, &buf[sz - len], len, ssl->wflags);
+
+    if (sent < 0) {
+        err = LastError();
+        WOLFSSL_MSG("Embed Send error");
+
+        if (err == SOCKET_EWOULDBLOCK || err == SOCKET_EAGAIN) {
+            WOLFSSL_MSG("    Would Block");
+            return WOLFSSL_CBIO_ERR_WANT_WRITE;
+        }
+        else if (err == SOCKET_ECONNRESET) {
+            WOLFSSL_MSG("    Connection reset");
+            return WOLFSSL_CBIO_ERR_CONN_RST;
+        }
+        else if (err == SOCKET_EINTR) {
+            WOLFSSL_MSG("    Socket interrupted");
+            return WOLFSSL_CBIO_ERR_ISR;
+        }
+        else if (err == SOCKET_EPIPE) {
+            WOLFSSL_MSG("    Socket EPIPE");
+            return WOLFSSL_CBIO_ERR_CONN_CLOSE;
+        }
+        else {
+            WOLFSSL_MSG("    General error");
+            return WOLFSSL_CBIO_ERR_GENERAL;
+        }
+    }
+ 
+    return sent;
+}
+
+
+#ifdef WOLFSSL_DTLS
+
+#include 
+
+#ifdef USE_WINDOWS_API
+   #define XSOCKLENT int
+#else
+   #define XSOCKLENT socklen_t
+#endif
+
+#define SENDTO_FUNCTION sendto
+#define RECVFROM_FUNCTION recvfrom
+
+
+/* The receive embedded callback
+ *  return : nb bytes read, or error
+ */
+int EmbedReceiveFrom(WOLFSSL *ssl, char *buf, int sz, void *ctx)
+{
+    WOLFSSL_DTLS_CTX* dtlsCtx = (WOLFSSL_DTLS_CTX*)ctx;
+    int recvd;
+    int err;
+    int sd = dtlsCtx->fd;
+    int dtls_timeout = wolfSSL_dtls_get_current_timeout(ssl);
+    struct sockaddr_storage peer;
+    XSOCKLENT peerSz = sizeof(peer);
+
+    WOLFSSL_ENTER("EmbedReceiveFrom()");
+
+    if (!wolfSSL_get_using_nonblock(ssl) && dtls_timeout != 0) {
+        #ifdef USE_WINDOWS_API
+            DWORD timeout = dtls_timeout * 1000;
+        #else
+            struct timeval timeout;
+            XMEMSET(&timeout, 0, sizeof(timeout));
+            timeout.tv_sec = dtls_timeout;
+        #endif
+        if (setsockopt(sd, SOL_SOCKET, SO_RCVTIMEO, (char*)&timeout,
+                       sizeof(timeout)) != 0) {
+                WOLFSSL_MSG("setsockopt rcvtimeo failed");
+        }
+    }
+
+    recvd = (int)RECVFROM_FUNCTION(sd, buf, sz, ssl->rflags,
+                                  (struct sockaddr*)&peer, &peerSz);
+
+    recvd = TranslateReturnCode(recvd, sd);
+
+    if (recvd < 0) {
+        err = LastError();
+        WOLFSSL_MSG("Embed Receive From error");
+
+        if (err == SOCKET_EWOULDBLOCK || err == SOCKET_EAGAIN) {
+            if (wolfSSL_get_using_nonblock(ssl)) {
+                WOLFSSL_MSG("    Would block");
+                return WOLFSSL_CBIO_ERR_WANT_READ;
+            }
+            else {
+                WOLFSSL_MSG("    Socket timeout");
+                return WOLFSSL_CBIO_ERR_TIMEOUT;
+            }
+        }
+        else if (err == SOCKET_ECONNRESET) {
+            WOLFSSL_MSG("    Connection reset");
+            return WOLFSSL_CBIO_ERR_CONN_RST;
+        }
+        else if (err == SOCKET_EINTR) {
+            WOLFSSL_MSG("    Socket interrupted");
+            return WOLFSSL_CBIO_ERR_ISR;
+        }
+        else if (err == SOCKET_ECONNREFUSED) {
+            WOLFSSL_MSG("    Connection refused");
+            return WOLFSSL_CBIO_ERR_WANT_READ;
+        }
+        else {
+            WOLFSSL_MSG("    General error");
+            return WOLFSSL_CBIO_ERR_GENERAL;
+        }
+    }
+    else {
+        if (dtlsCtx->peer.sz > 0
+                && peerSz != (XSOCKLENT)dtlsCtx->peer.sz
+                && memcmp(&peer, dtlsCtx->peer.sa, peerSz) != 0) {
+            WOLFSSL_MSG("    Ignored packet from invalid peer");
+            return WOLFSSL_CBIO_ERR_WANT_READ;
+        }
+    }
+
+    return recvd;
+}
+
+
+/* The send embedded callback
+ *  return : nb bytes sent, or error
+ */
+int EmbedSendTo(WOLFSSL* ssl, char *buf, int sz, void *ctx)
+{
+    WOLFSSL_DTLS_CTX* dtlsCtx = (WOLFSSL_DTLS_CTX*)ctx;
+    int sd = dtlsCtx->fd;
+    int sent;
+    int len = sz;
+    int err;
+
+    WOLFSSL_ENTER("EmbedSendTo()");
+
+    sent = (int)SENDTO_FUNCTION(sd, &buf[sz - len], len, ssl->wflags,
+                                (const struct sockaddr*)dtlsCtx->peer.sa,
+                                dtlsCtx->peer.sz);
+    if (sent < 0) {
+        err = LastError();
+        WOLFSSL_MSG("Embed Send To error");
+
+        if (err == SOCKET_EWOULDBLOCK || err == SOCKET_EAGAIN) {
+            WOLFSSL_MSG("    Would Block");
+            return WOLFSSL_CBIO_ERR_WANT_WRITE;
+        }
+        else if (err == SOCKET_ECONNRESET) {
+            WOLFSSL_MSG("    Connection reset");
+            return WOLFSSL_CBIO_ERR_CONN_RST;
+        }
+        else if (err == SOCKET_EINTR) {
+            WOLFSSL_MSG("    Socket interrupted");
+            return WOLFSSL_CBIO_ERR_ISR;
+        }
+        else if (err == SOCKET_EPIPE) {
+            WOLFSSL_MSG("    Socket EPIPE");
+            return WOLFSSL_CBIO_ERR_CONN_CLOSE;
+        }
+        else {
+            WOLFSSL_MSG("    General error");
+            return WOLFSSL_CBIO_ERR_GENERAL;
+        }
+    }
+ 
+    return sent;
+}
+
+
+/* The DTLS Generate Cookie callback
+ *  return : number of bytes copied into buf, or error
+ */
+int EmbedGenerateCookie(WOLFSSL* ssl, byte *buf, int sz, void *ctx)
+{
+    int sd = ssl->wfd;
+    struct sockaddr_storage peer;
+    XSOCKLENT peerSz = sizeof(peer);
+    byte digest[SHA_DIGEST_SIZE];
+    int  ret = 0;
+
+    (void)ctx;
+
+    XMEMSET(&peer, 0, sizeof(peer));
+    if (getpeername(sd, (struct sockaddr*)&peer, &peerSz) != 0) {
+        WOLFSSL_MSG("getpeername failed in EmbedGenerateCookie");
+        return GEN_COOKIE_E;
+    }
+
+    ret = wc_ShaHash((byte*)&peer, peerSz, digest);
+    if (ret != 0)
+        return ret;
+
+    if (sz > SHA_DIGEST_SIZE)
+        sz = SHA_DIGEST_SIZE;
+    XMEMCPY(buf, digest, sz);
+
+    return sz;
+}
+
+#endif /* WOLFSSL_DTLS */
+
+#ifdef HAVE_OCSP
+
+
+static int Word16ToString(char* d, word16 number)
+{
+    int i = 0;
+
+    if (d != NULL) {
+        word16 order = 10000;
+        word16 digit;
+
+        if (number == 0) {
+            d[i++] = '0';
+        }
+        else {
+            while (order) {
+                digit = number / order;
+                if (i > 0 || digit != 0) {
+                    d[i++] = (char)digit + '0';
+                }
+                if (digit != 0)
+                    number %= digit * order;
+                if (order > 1)
+                    order /= 10;
+                else
+                    order = 0;
+            }
+        }
+        d[i] = 0;
+    }
+
+    return i;
+}
+
+
+static int tcp_connect(SOCKET_T* sockfd, const char* ip, word16 port)
+{
+    struct sockaddr_storage addr;
+    int sockaddr_len = sizeof(struct sockaddr_in);
+    XMEMSET(&addr, 0, sizeof(addr));
+
+    #ifdef HAVE_GETADDRINFO
+    {
+        struct addrinfo hints;
+        struct addrinfo* answer = NULL;
+        char strPort[6];
+
+        XMEMSET(&hints, 0, sizeof(hints));
+        hints.ai_family = AF_UNSPEC;
+        hints.ai_socktype = SOCK_STREAM;
+        hints.ai_protocol = IPPROTO_TCP;
+
+        if (Word16ToString(strPort, port) == 0) {
+            WOLFSSL_MSG("invalid port number for OCSP responder");
+            return -1;
+        }
+
+        if (getaddrinfo(ip, strPort, &hints, &answer) < 0 || answer == NULL) {
+            WOLFSSL_MSG("no addr info for OCSP responder");
+            return -1;
+        }
+
+        sockaddr_len = answer->ai_addrlen;
+        XMEMCPY(&addr, answer->ai_addr, sockaddr_len);
+        freeaddrinfo(answer);
+
+    }
+    #else /* HAVE_GETADDRINFO */
+    {
+        struct hostent* entry = gethostbyname(ip);
+        struct sockaddr_in *sin = (struct sockaddr_in *)&addr;
+
+        if (entry) {
+            sin->sin_family = AF_INET;
+            sin->sin_port = htons(port);
+            XMEMCPY(&sin->sin_addr.s_addr, entry->h_addr_list[0],
+                                                               entry->h_length);
+        }
+        else {
+            WOLFSSL_MSG("no addr info for OCSP responder");
+            return -1;
+        }
+    }
+    #endif /* HAVE_GETADDRINFO */
+
+    *sockfd = socket(addr.ss_family, SOCK_STREAM, 0);
+
+#ifdef USE_WINDOWS_API
+    if (*sockfd == INVALID_SOCKET) {
+        WOLFSSL_MSG("bad socket fd, out of fds?");
+        return -1;
+    }
+#else
+     if (*sockfd < 0) {
+         WOLFSSL_MSG("bad socket fd, out of fds?");
+         return -1;
+     }
+#endif
+
+    if (connect(*sockfd, (struct sockaddr *)&addr, sockaddr_len) != 0) {
+        WOLFSSL_MSG("OCSP responder tcp connect failed");
+        return -1;
+    }
+
+    return 0;
+}
+
+
+static int build_http_request(const char* domainName, const char* path,
+                                    int ocspReqSz, byte* buf, int bufSize)
+{
+    word32 domainNameLen, pathLen, ocspReqSzStrLen, completeLen;
+    char ocspReqSzStr[6];
+
+    domainNameLen = (word32)XSTRLEN(domainName);
+    pathLen = (word32)XSTRLEN(path);
+    ocspReqSzStrLen = Word16ToString(ocspReqSzStr, (word16)ocspReqSz);
+
+    completeLen = domainNameLen + pathLen + ocspReqSzStrLen + 84;
+    if (completeLen > (word32)bufSize)
+        return 0;
+
+    XSTRNCPY((char*)buf, "POST ", 5);
+    buf += 5;
+    XSTRNCPY((char*)buf, path, pathLen);
+    buf += pathLen;
+    XSTRNCPY((char*)buf, " HTTP/1.1\r\nHost: ", 17);
+    buf += 17;
+    XSTRNCPY((char*)buf, domainName, domainNameLen);
+    buf += domainNameLen;
+    XSTRNCPY((char*)buf, "\r\nContent-Length: ", 18);
+    buf += 18;
+    XSTRNCPY((char*)buf, ocspReqSzStr, ocspReqSzStrLen);
+    buf += ocspReqSzStrLen;
+    XSTRNCPY((char*)buf,
+                      "\r\nContent-Type: application/ocsp-request\r\n\r\n", 44);
+
+    return completeLen;
+}
+
+
+static int decode_url(const char* url, int urlSz,
+    char* outName, char* outPath, word16* outPort)
+{
+    int result = -1;
+
+    if (outName != NULL && outPath != NULL && outPort != NULL)
+    {
+        if (url == NULL || urlSz == 0)
+        {
+            *outName = 0;
+            *outPath = 0;
+            *outPort = 0;
+        }
+        else
+        {
+            int i, cur;
+    
+            /* need to break the url down into scheme, address, and port */
+            /*     "http://example.com:8080/" */
+            /*     "http://[::1]:443/"        */
+            if (XSTRNCMP(url, "http://", 7) == 0) {
+                cur = 7;
+            } else cur = 0;
+    
+            i = 0;
+            if (url[cur] == '[') {
+                cur++;
+                /* copy until ']' */
+                while (url[cur] != 0 && url[cur] != ']' && cur < urlSz) {
+                    outName[i++] = url[cur++];
+                }
+                cur++; /* skip ']' */
+            }
+            else {
+                while (url[cur] != 0 && url[cur] != ':' &&
+                                               url[cur] != '/' && cur < urlSz) {
+                    outName[i++] = url[cur++];
+                }
+            }
+            outName[i] = 0;
+            /* Need to pick out the path after the domain name */
+    
+            if (cur < urlSz && url[cur] == ':') {
+                char port[6];
+                int j;
+                word32 bigPort = 0;
+                i = 0;
+                cur++;
+                while (cur < urlSz && url[cur] != 0 && url[cur] != '/' &&
+                        i < 6) {
+                    port[i++] = url[cur++];
+                }
+    
+                for (j = 0; j < i; j++) {
+                    if (port[j] < '0' || port[j] > '9') return -1;
+                    bigPort = (bigPort * 10) + (port[j] - '0');
+                }
+                *outPort = (word16)bigPort;
+            }
+            else
+                *outPort = 80;
+    
+            if (cur < urlSz && url[cur] == '/') {
+                i = 0;
+                while (cur < urlSz && url[cur] != 0 && i < 80) {
+                    outPath[i++] = url[cur++];
+                }
+                outPath[i] = 0;
+            }
+            else {
+                outPath[0] = '/';
+                outPath[1] = 0;
+            }
+            result = 0;
+        }
+    }
+
+    return result;
+}
+
+
+/* return: >0 OCSP Response Size
+ *         -1 error */
+static int process_http_response(int sfd, byte** respBuf,
+                                                  byte* httpBuf, int httpBufSz)
+{
+    int result;
+    int len = 0;
+    char *start, *end;
+    byte *recvBuf = NULL;
+    int recvBufSz = 0;
+    enum phr_state { phr_init, phr_http_start, phr_have_length,
+                     phr_have_type, phr_wait_end, phr_http_end
+    } state = phr_init;
+
+    start = end = NULL;
+    do {
+        if (end == NULL) {
+            result = (int)recv(sfd, (char*)httpBuf+len, httpBufSz-len-1, 0);
+            if (result > 0) {
+                len += result;
+                start = (char*)httpBuf;
+                start[len] = 0;
+            }
+            else {
+                WOLFSSL_MSG("process_http_response recv http from peer failed");
+                return -1;
+            }
+        }
+        end = XSTRSTR(start, "\r\n");
+
+        if (end == NULL) {
+            if (len != 0)
+                XMEMMOVE(httpBuf, start, len);
+            start = end = NULL;
+        }
+        else if (end == start) {
+            if (state == phr_wait_end) {
+                state = phr_http_end;
+                len -= 2;
+                start += 2;
+             }
+             else {
+                WOLFSSL_MSG("process_http_response header ended early");
+                return -1;
+             }
+        }
+        else {
+            *end = 0;
+            len -= (int)(end - start) + 2;
+                /* adjust len to remove the first line including the /r/n */
+
+            if (XSTRNCASECMP(start, "HTTP/1", 6) == 0) {
+                start += 9;
+                if (XSTRNCASECMP(start, "200 OK", 6) != 0 ||
+                                                           state != phr_init) {
+                    WOLFSSL_MSG("process_http_response not OK");
+                    return -1;
+                }
+                state = phr_http_start;
+            }
+            else if (XSTRNCASECMP(start, "Content-Type:", 13) == 0) {
+                start += 13;
+                while (*start == ' ' && *start != '\0') start++;
+                if (XSTRNCASECMP(start, "application/ocsp-response", 25) != 0) {
+                    WOLFSSL_MSG("process_http_response not ocsp-response");
+                    return -1;
+                }
+                
+                if (state == phr_http_start) state = phr_have_type;
+                else if (state == phr_have_length) state = phr_wait_end;
+                else {
+                    WOLFSSL_MSG("process_http_response type invalid state");
+                    return -1;
+                }
+            }
+            else if (XSTRNCASECMP(start, "Content-Length:", 15) == 0) {
+                start += 15;
+                while (*start == ' ' && *start != '\0') start++;
+                recvBufSz = atoi(start);
+
+                if (state == phr_http_start) state = phr_have_length;
+                else if (state == phr_have_type) state = phr_wait_end;
+                else {
+                    WOLFSSL_MSG("process_http_response length invalid state");
+                    return -1;
+                }
+            }
+            
+            start = end + 2;
+        }
+    } while (state != phr_http_end);
+
+    recvBuf = (byte*)XMALLOC(recvBufSz, NULL, DYNAMIC_TYPE_IN_BUFFER);
+    if (recvBuf == NULL) {
+        WOLFSSL_MSG("process_http_response couldn't create response buffer");
+        return -1;
+    }
+
+    /* copy the remainder of the httpBuf into the respBuf */
+    if (len != 0)
+        XMEMCPY(recvBuf, start, len);
+
+    /* receive the OCSP response data */
+    do {
+        result = (int)recv(sfd, (char*)recvBuf+len, recvBufSz-len, 0);
+        if (result > 0)
+            len += result;
+        else {
+            WOLFSSL_MSG("process_http_response recv ocsp from peer failed");
+            return -1;
+        }
+    } while (len != recvBufSz);
+
+    *respBuf = recvBuf;
+    return recvBufSz;
+}
+
+
+#define SCRATCH_BUFFER_SIZE 512
+
+int EmbedOcspLookup(void* ctx, const char* url, int urlSz,
+                        byte* ocspReqBuf, int ocspReqSz, byte** ocspRespBuf)
+{
+    SOCKET_T sfd = 0;
+    word16   port;
+    int      ret = -1;
+#ifdef WOLFSSL_SMALL_STACK
+    char*    path;
+    char*    domainName;
+#else
+    char     path[80];
+    char     domainName[80];
+#endif
+
+#ifdef WOLFSSL_SMALL_STACK
+    path = (char*)XMALLOC(80, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (path == NULL)
+        return -1;
+    
+    domainName = (char*)XMALLOC(80, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (domainName == NULL) {
+        XFREE(path, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        return -1;
+    }
+#endif
+
+    (void)ctx;
+
+    if (ocspReqBuf == NULL || ocspReqSz == 0) {
+        WOLFSSL_MSG("OCSP request is required for lookup");
+    }
+    else if (ocspRespBuf == NULL) {
+        WOLFSSL_MSG("Cannot save OCSP response");
+    }
+    else if (decode_url(url, urlSz, domainName, path, &port) < 0) {
+        WOLFSSL_MSG("Unable to decode OCSP URL");
+    }
+    else {
+        /* Note, the library uses the EmbedOcspRespFree() callback to
+         * free this buffer. */
+        int   httpBufSz = SCRATCH_BUFFER_SIZE;
+        byte* httpBuf   = (byte*)XMALLOC(httpBufSz, NULL, 
+                                                        DYNAMIC_TYPE_IN_BUFFER);
+
+        if (httpBuf == NULL) {
+            WOLFSSL_MSG("Unable to create OCSP response buffer");
+        }
+        else {
+            httpBufSz = build_http_request(domainName, path, ocspReqSz,
+                                                            httpBuf, httpBufSz);
+
+            if ((tcp_connect(&sfd, domainName, port) != 0) || (sfd <= 0)) {
+                WOLFSSL_MSG("OCSP Responder connection failed");
+            }
+            else if ((int)send(sfd, (char*)httpBuf, httpBufSz, 0) !=
+                                                                    httpBufSz) {
+                WOLFSSL_MSG("OCSP http request failed");
+            }
+            else if ((int)send(sfd, (char*)ocspReqBuf, ocspReqSz, 0) !=
+                                                                    ocspReqSz) {
+                WOLFSSL_MSG("OCSP ocsp request failed");
+            }
+            else {
+                ret = process_http_response(sfd, ocspRespBuf, httpBuf,
+                                                           SCRATCH_BUFFER_SIZE);
+            }
+
+            close(sfd);
+            XFREE(httpBuf, NULL, DYNAMIC_TYPE_IN_BUFFER);
+        }
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(path,       NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(domainName, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+
+void EmbedOcspRespFree(void* ctx, byte *resp)
+{
+    (void)ctx;
+
+    if (resp)
+        XFREE(resp, NULL, DYNAMIC_TYPE_IN_BUFFER);
+}
+
+
+#endif
+
+#endif /* WOLFSSL_USER_IO */
+
+WOLFSSL_API void wolfSSL_SetIORecv(WOLFSSL_CTX *ctx, CallbackIORecv CBIORecv)
+{
+    ctx->CBIORecv = CBIORecv;
+}
+
+
+WOLFSSL_API void wolfSSL_SetIOSend(WOLFSSL_CTX *ctx, CallbackIOSend CBIOSend)
+{
+    ctx->CBIOSend = CBIOSend;
+}
+
+
+WOLFSSL_API void wolfSSL_SetIOReadCtx(WOLFSSL* ssl, void *rctx)
+{
+	ssl->IOCB_ReadCtx = rctx;
+}
+
+
+WOLFSSL_API void wolfSSL_SetIOWriteCtx(WOLFSSL* ssl, void *wctx)
+{
+	ssl->IOCB_WriteCtx = wctx;
+}
+
+
+WOLFSSL_API void* wolfSSL_GetIOReadCtx(WOLFSSL* ssl)
+{
+    if (ssl)
+        return ssl->IOCB_ReadCtx;
+
+    return NULL;
+}
+
+
+WOLFSSL_API void* wolfSSL_GetIOWriteCtx(WOLFSSL* ssl)
+{
+    if (ssl)
+        return ssl->IOCB_WriteCtx;
+
+    return NULL;
+}
+
+
+WOLFSSL_API void wolfSSL_SetIOReadFlags(WOLFSSL* ssl, int flags)
+{
+    ssl->rflags = flags; 
+}
+
+
+WOLFSSL_API void wolfSSL_SetIOWriteFlags(WOLFSSL* ssl, int flags)
+{
+    ssl->wflags = flags;
+}
+
+
+#ifdef WOLFSSL_DTLS
+
+WOLFSSL_API void wolfSSL_CTX_SetGenCookie(WOLFSSL_CTX* ctx, CallbackGenCookie cb)
+{
+    ctx->CBIOCookie = cb;
+}
+
+
+WOLFSSL_API void wolfSSL_SetCookieCtx(WOLFSSL* ssl, void *ctx)
+{
+	ssl->IOCB_CookieCtx = ctx;
+}
+
+
+WOLFSSL_API void* wolfSSL_GetCookieCtx(WOLFSSL* ssl)
+{
+    if (ssl)
+	    return ssl->IOCB_CookieCtx;
+
+    return NULL;
+}
+
+#endif /* WOLFSSL_DTLS */
+
+
+#ifdef HAVE_NETX
+
+/* The NetX receive callback
+ *  return :  bytes read, or error
+ */
+int NetX_Receive(WOLFSSL *ssl, char *buf, int sz, void *ctx)
+{
+    NetX_Ctx* nxCtx = (NetX_Ctx*)ctx;
+    ULONG left;
+    ULONG total;
+    ULONG copied = 0;
+    UINT  status;
+
+    if (nxCtx == NULL || nxCtx->nxSocket == NULL) {
+        WOLFSSL_MSG("NetX Recv NULL parameters");
+        return WOLFSSL_CBIO_ERR_GENERAL;
+    }
+
+    if (nxCtx->nxPacket == NULL) {
+        status = nx_tcp_socket_receive(nxCtx->nxSocket, &nxCtx->nxPacket,
+                                       nxCtx->nxWait);
+        if (status != NX_SUCCESS) {
+            WOLFSSL_MSG("NetX Recv receive error");
+            return WOLFSSL_CBIO_ERR_GENERAL;
+        }
+    }
+
+    if (nxCtx->nxPacket) {
+        status = nx_packet_length_get(nxCtx->nxPacket, &total);
+        if (status != NX_SUCCESS) {
+            WOLFSSL_MSG("NetX Recv length get error");
+            return WOLFSSL_CBIO_ERR_GENERAL;
+        }
+
+        left = total - nxCtx->nxOffset;
+        status = nx_packet_data_extract_offset(nxCtx->nxPacket, nxCtx->nxOffset,
+                                               buf, sz, &copied);
+        if (status != NX_SUCCESS) {
+            WOLFSSL_MSG("NetX Recv data extract offset error");
+            return WOLFSSL_CBIO_ERR_GENERAL;
+        }
+
+        nxCtx->nxOffset += copied;
+
+        if (copied == left) {
+            WOLFSSL_MSG("NetX Recv Drained packet");
+            nx_packet_release(nxCtx->nxPacket);
+            nxCtx->nxPacket = NULL;
+            nxCtx->nxOffset = 0;
+        }
+    }
+
+    return copied;
+}
+
+
+/* The NetX send callback
+ *  return : bytes sent, or error
+ */
+int NetX_Send(WOLFSSL* ssl, char *buf, int sz, void *ctx)
+{
+    NetX_Ctx*       nxCtx = (NetX_Ctx*)ctx;
+    NX_PACKET*      packet;
+    NX_PACKET_POOL* pool;   /* shorthand */
+    UINT            status;
+
+    if (nxCtx == NULL || nxCtx->nxSocket == NULL) {
+        WOLFSSL_MSG("NetX Send NULL parameters");
+        return WOLFSSL_CBIO_ERR_GENERAL;
+    }
+
+    pool = nxCtx->nxSocket->nx_tcp_socket_ip_ptr->nx_ip_default_packet_pool;
+    status = nx_packet_allocate(pool, &packet, NX_TCP_PACKET,
+                                nxCtx->nxWait);
+    if (status != NX_SUCCESS) {
+        WOLFSSL_MSG("NetX Send packet alloc error");
+        return WOLFSSL_CBIO_ERR_GENERAL;
+    }
+
+    status = nx_packet_data_append(packet, buf, sz, pool, nxCtx->nxWait);
+    if (status != NX_SUCCESS) {
+        nx_packet_release(packet);
+        WOLFSSL_MSG("NetX Send data append error");
+        return WOLFSSL_CBIO_ERR_GENERAL;
+    }
+
+    status = nx_tcp_socket_send(nxCtx->nxSocket, packet, nxCtx->nxWait);
+    if (status != NX_SUCCESS) {
+        nx_packet_release(packet);
+        WOLFSSL_MSG("NetX Send socket send error");
+        return WOLFSSL_CBIO_ERR_GENERAL;
+    }
+
+    return sz;
+}
+
+
+/* like set_fd, but for default NetX context */
+void wolfSSL_SetIO_NetX(WOLFSSL* ssl, NX_TCP_SOCKET* nxSocket, ULONG waitOption)
+{
+    if (ssl) {
+        ssl->nxCtx.nxSocket = nxSocket;
+        ssl->nxCtx.nxWait   = waitOption;
+    }
+}
+
+#endif /* HAVE_NETX */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/keys.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/keys.c
new file mode 100644
index 0000000..b06debb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/keys.c
@@ -0,0 +1,2735 @@
+/* keys.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+/* Name change compatibility layer no longer needs to be included here */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#include 
+#include 
+#if defined(SHOW_SECRETS) || defined(CHACHA_AEAD_TEST)
+    #ifdef FREESCALE_MQX
+        #include 
+    #else
+        #include 
+    #endif
+#endif
+
+
+int SetCipherSpecs(WOLFSSL* ssl)
+{
+#ifndef NO_WOLFSSL_CLIENT
+    if (ssl->options.side == WOLFSSL_CLIENT_END) {
+        /* server side verified before SetCipherSpecs call */
+        if (VerifyClientSuite(ssl) != 1) {
+            WOLFSSL_MSG("SetCipherSpecs() client has an unusuable suite");
+            return UNSUPPORTED_SUITE;
+        }
+    }
+#endif /* NO_WOLFSSL_CLIENT */
+
+    /* Chacha extensions, 0xcc */
+    if (ssl->options.cipherSuite0 == CHACHA_BYTE) {
+    
+    switch (ssl->options.cipherSuite) {
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256
+    case TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256:
+        ssl->specs.bulk_cipher_algorithm = wolfssl_chacha;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = CHACHA20_256_KEY_SIZE;
+        ssl->specs.block_size            = CHACHA20_BLOCK_SIZE;
+        ssl->specs.iv_size               = CHACHA20_IV_SIZE;
+        ssl->specs.aead_mac_size         = POLY1305_AUTH_SZ;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256
+    case TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256:
+        ssl->specs.bulk_cipher_algorithm = wolfssl_chacha;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = ecc_dsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = CHACHA20_256_KEY_SIZE;
+        ssl->specs.block_size            = CHACHA20_BLOCK_SIZE;
+        ssl->specs.iv_size               = CHACHA20_IV_SIZE;
+        ssl->specs.aead_mac_size         = POLY1305_AUTH_SZ;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256
+    case TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256:
+        ssl->specs.bulk_cipher_algorithm = wolfssl_chacha;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = CHACHA20_256_KEY_SIZE;
+        ssl->specs.block_size            = CHACHA20_BLOCK_SIZE;
+        ssl->specs.iv_size               = CHACHA20_IV_SIZE;
+        ssl->specs.aead_mac_size         = POLY1305_AUTH_SZ;
+
+        break;
+#endif
+    default:
+        WOLFSSL_MSG("Unsupported cipher suite, SetCipherSpecs ChaCha");
+        return UNSUPPORTED_SUITE;
+    }
+    }
+
+    /* ECC extensions, or AES-CCM */
+    if (ssl->options.cipherSuite0 == ECC_BYTE) {
+    
+    switch (ssl->options.cipherSuite) {
+
+#ifdef HAVE_ECC
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
+    case TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+    break;
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
+    case TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = ecc_dsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+    break;
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256
+    case TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 1;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+    break;
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256
+    case TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = ecc_dsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 1;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+    break;
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384
+    case TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha384_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA384_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+    break;
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384
+    case TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha384_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = ecc_dsa_sa_algo;
+        ssl->specs.hash_size             = SHA384_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+    break;
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384
+    case TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha384_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA384_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 1;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+    break;
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384
+    case TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha384_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = ecc_dsa_sa_algo;
+        ssl->specs.hash_size             = SHA384_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 1;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+    break;
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA
+    case TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA
+    case TLS_ECDH_RSA_WITH_AES_128_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 1;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA
+    case TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_triple_des;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = DES3_KEY_SIZE;
+        ssl->specs.block_size            = DES_BLOCK_SIZE;
+        ssl->specs.iv_size               = DES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA
+    case TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_triple_des;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 1;
+        ssl->specs.key_size              = DES3_KEY_SIZE;
+        ssl->specs.block_size            = DES_BLOCK_SIZE;
+        ssl->specs.iv_size               = DES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_RC4_128_SHA
+    case TLS_ECDHE_RSA_WITH_RC4_128_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_rc4;
+        ssl->specs.cipher_type           = stream;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = RC4_KEY_SIZE;
+        ssl->specs.iv_size               = 0;
+        ssl->specs.block_size            = 0;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_RC4_128_SHA
+    case TLS_ECDH_RSA_WITH_RC4_128_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_rc4;
+        ssl->specs.cipher_type           = stream;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 1;
+        ssl->specs.key_size              = RC4_KEY_SIZE;
+        ssl->specs.iv_size               = 0;
+        ssl->specs.block_size            = 0;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA
+    case TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_triple_des;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = ecc_dsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = DES3_KEY_SIZE;
+        ssl->specs.block_size            = DES_BLOCK_SIZE;
+        ssl->specs.iv_size               = DES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA
+    case TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_triple_des;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = ecc_dsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 1;
+        ssl->specs.key_size              = DES3_KEY_SIZE;
+        ssl->specs.block_size            = DES_BLOCK_SIZE;
+        ssl->specs.iv_size               = DES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA
+    case TLS_ECDHE_ECDSA_WITH_RC4_128_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_rc4;
+        ssl->specs.cipher_type           = stream;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = ecc_dsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = RC4_KEY_SIZE;
+        ssl->specs.iv_size               = 0;
+        ssl->specs.block_size            = 0;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_RC4_128_SHA
+    case TLS_ECDH_ECDSA_WITH_RC4_128_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_rc4;
+        ssl->specs.cipher_type           = stream;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = ecc_dsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 1;
+        ssl->specs.key_size              = RC4_KEY_SIZE;
+        ssl->specs.iv_size               = 0;
+        ssl->specs.block_size            = 0;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
+    case TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA
+    case TLS_ECDH_RSA_WITH_AES_256_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 1;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
+    case TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = ecc_dsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA
+    case TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = ecc_dsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 1;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
+    case TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = ecc_dsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA
+    case TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = ecc_dsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 1;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
+    case TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_gcm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_GCM_AUTH_SZ;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
+    case TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_gcm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha384_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA384_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_GCM_AUTH_SZ;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
+    case TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_gcm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = ecc_dsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_GCM_AUTH_SZ;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
+    case TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_gcm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha384_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = ecc_dsa_sa_algo;
+        ssl->specs.hash_size             = SHA384_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_GCM_AUTH_SZ;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256
+    case TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_gcm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 1;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_GCM_AUTH_SZ;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384
+    case TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_gcm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha384_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA384_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 1;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_GCM_AUTH_SZ;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256
+    case TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_gcm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = ecc_dsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 1;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_GCM_AUTH_SZ;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384
+    case TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_gcm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha384_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = ecc_dsa_sa_algo;
+        ssl->specs.hash_size             = SHA384_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 1;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_GCM_AUTH_SZ;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8
+    case TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_ccm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = ecc_dsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_CCM_8_AUTH_SZ;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8
+    case TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_ccm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = ecc_diffie_hellman_kea;
+        ssl->specs.sig_algo              = ecc_dsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_CCM_8_AUTH_SZ;
+
+        break;
+#endif
+#endif /* HAVE_ECC */
+
+#ifdef BUILD_TLS_RSA_WITH_AES_128_CCM_8
+    case TLS_RSA_WITH_AES_128_CCM_8 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_ccm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = rsa_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_CCM_8_AUTH_SZ;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_256_CCM_8
+    case TLS_RSA_WITH_AES_256_CCM_8 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_ccm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = rsa_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_CCM_8_AUTH_SZ;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_128_CCM_8
+    case TLS_PSK_WITH_AES_128_CCM_8 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_ccm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = psk_kea;
+        ssl->specs.sig_algo              = anonymous_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_CCM_8_AUTH_SZ;
+
+        ssl->options.usingPSK_cipher     = 1;
+        break;
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_256_CCM_8
+    case TLS_PSK_WITH_AES_256_CCM_8 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_ccm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = psk_kea;
+        ssl->specs.sig_algo              = anonymous_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_CCM_8_AUTH_SZ;
+
+        ssl->options.usingPSK_cipher     = 1;
+        break;
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_128_CCM
+    case TLS_PSK_WITH_AES_128_CCM :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_ccm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = psk_kea;
+        ssl->specs.sig_algo              = anonymous_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_CCM_16_AUTH_SZ;
+
+        ssl->options.usingPSK_cipher     = 1;
+        break;
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_256_CCM
+    case TLS_PSK_WITH_AES_256_CCM :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_ccm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = psk_kea;
+        ssl->specs.sig_algo              = anonymous_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_CCM_16_AUTH_SZ;
+
+        ssl->options.usingPSK_cipher     = 1;
+        break;
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_128_CCM
+    case TLS_DHE_PSK_WITH_AES_128_CCM :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_ccm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = dhe_psk_kea;
+        ssl->specs.sig_algo              = anonymous_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_CCM_16_AUTH_SZ;
+
+        ssl->options.usingPSK_cipher     = 1;
+        break;
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_256_CCM
+    case TLS_DHE_PSK_WITH_AES_256_CCM :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_ccm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = dhe_psk_kea;
+        ssl->specs.sig_algo              = anonymous_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_CCM_16_AUTH_SZ;
+
+        ssl->options.usingPSK_cipher     = 1;
+        break;
+#endif
+
+    default:
+        WOLFSSL_MSG("Unsupported cipher suite, SetCipherSpecs ECC");
+        return UNSUPPORTED_SUITE;
+    }   /* switch */
+    }   /* if     */
+    if (ssl->options.cipherSuite0 != ECC_BYTE && 
+            ssl->options.cipherSuite0 != CHACHA_BYTE) {   /* normal suites */
+    switch (ssl->options.cipherSuite) {
+
+#ifdef BUILD_SSL_RSA_WITH_RC4_128_SHA
+    case SSL_RSA_WITH_RC4_128_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_rc4;
+        ssl->specs.cipher_type           = stream;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = rsa_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = RC4_KEY_SIZE;
+        ssl->specs.iv_size               = 0;
+        ssl->specs.block_size            = 0;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_NTRU_RSA_WITH_RC4_128_SHA
+    case TLS_NTRU_RSA_WITH_RC4_128_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_rc4;
+        ssl->specs.cipher_type           = stream;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = ntru_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = RC4_KEY_SIZE;
+        ssl->specs.iv_size               = 0;
+        ssl->specs.block_size            = 0;
+
+        break;
+#endif
+
+#ifdef BUILD_SSL_RSA_WITH_RC4_128_MD5
+    case SSL_RSA_WITH_RC4_128_MD5 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_rc4;
+        ssl->specs.cipher_type           = stream;
+        ssl->specs.mac_algorithm         = md5_mac;
+        ssl->specs.kea                   = rsa_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = MD5_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_MD5;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = RC4_KEY_SIZE;
+        ssl->specs.iv_size               = 0;
+        ssl->specs.block_size            = 0;
+
+        break;
+#endif
+
+#ifdef BUILD_SSL_RSA_WITH_3DES_EDE_CBC_SHA
+    case SSL_RSA_WITH_3DES_EDE_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_triple_des;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = rsa_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = DES3_KEY_SIZE;
+        ssl->specs.block_size            = DES_BLOCK_SIZE;
+        ssl->specs.iv_size               = DES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_NTRU_RSA_WITH_3DES_EDE_CBC_SHA
+    case TLS_NTRU_RSA_WITH_3DES_EDE_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_triple_des;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = ntru_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = DES3_KEY_SIZE;
+        ssl->specs.block_size            = DES_BLOCK_SIZE;
+        ssl->specs.iv_size               = DES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_128_CBC_SHA
+    case TLS_RSA_WITH_AES_128_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = rsa_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_128_CBC_SHA256
+    case TLS_RSA_WITH_AES_128_CBC_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = rsa_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_NULL_SHA
+    case TLS_RSA_WITH_NULL_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_cipher_null;
+        ssl->specs.cipher_type           = stream;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = rsa_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = 0;
+        ssl->specs.block_size            = 0;
+        ssl->specs.iv_size               = 0;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_NULL_SHA256
+    case TLS_RSA_WITH_NULL_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_cipher_null;
+        ssl->specs.cipher_type           = stream;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = rsa_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = 0;
+        ssl->specs.block_size            = 0;
+        ssl->specs.iv_size               = 0;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_NTRU_RSA_WITH_AES_128_CBC_SHA
+    case TLS_NTRU_RSA_WITH_AES_128_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = ntru_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_256_CBC_SHA
+    case TLS_RSA_WITH_AES_256_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = rsa_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_256_CBC_SHA256
+    case TLS_RSA_WITH_AES_256_CBC_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = rsa_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_NTRU_RSA_WITH_AES_256_CBC_SHA
+    case TLS_NTRU_RSA_WITH_AES_256_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = ntru_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_128_GCM_SHA256
+    case TLS_PSK_WITH_AES_128_GCM_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_gcm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = psk_kea;
+        ssl->specs.sig_algo              = anonymous_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_GCM_AUTH_SZ;
+
+        ssl->options.usingPSK_cipher     = 1;
+        break;
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_256_GCM_SHA384
+    case TLS_PSK_WITH_AES_256_GCM_SHA384 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_gcm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha384_mac;
+        ssl->specs.kea                   = psk_kea;
+        ssl->specs.sig_algo              = anonymous_sa_algo;
+        ssl->specs.hash_size             = SHA384_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_GCM_AUTH_SZ;
+
+        ssl->options.usingPSK_cipher     = 1;
+        break;
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256
+    case TLS_DHE_PSK_WITH_AES_128_GCM_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_gcm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = dhe_psk_kea;
+        ssl->specs.sig_algo              = anonymous_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_GCM_AUTH_SZ;
+
+        ssl->options.usingPSK_cipher     = 1;
+        break;
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384
+    case TLS_DHE_PSK_WITH_AES_256_GCM_SHA384 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_gcm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha384_mac;
+        ssl->specs.kea                   = dhe_psk_kea;
+        ssl->specs.sig_algo              = anonymous_sa_algo;
+        ssl->specs.hash_size             = SHA384_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_GCM_AUTH_SZ;
+
+        ssl->options.usingPSK_cipher     = 1;
+        break;
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_128_CBC_SHA256
+    case TLS_PSK_WITH_AES_128_CBC_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = psk_kea;
+        ssl->specs.sig_algo              = anonymous_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        ssl->options.usingPSK_cipher     = 1;
+        break;
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_256_CBC_SHA384
+    case TLS_PSK_WITH_AES_256_CBC_SHA384 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha384_mac;
+        ssl->specs.kea                   = psk_kea;
+        ssl->specs.sig_algo              = anonymous_sa_algo;
+        ssl->specs.hash_size             = SHA384_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        ssl->options.usingPSK_cipher     = 1;
+        break;
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256
+    case TLS_DHE_PSK_WITH_AES_128_CBC_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = dhe_psk_kea;
+        ssl->specs.sig_algo              = anonymous_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        ssl->options.usingPSK_cipher     = 1;
+        break;
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384
+    case TLS_DHE_PSK_WITH_AES_256_CBC_SHA384 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha384_mac;
+        ssl->specs.kea                   = dhe_psk_kea;
+        ssl->specs.sig_algo              = anonymous_sa_algo;
+        ssl->specs.hash_size             = SHA384_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        ssl->options.usingPSK_cipher     = 1;
+        break;
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_128_CBC_SHA
+    case TLS_PSK_WITH_AES_128_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = psk_kea;
+        ssl->specs.sig_algo              = anonymous_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        ssl->options.usingPSK_cipher     = 1;
+        break;
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_AES_256_CBC_SHA
+    case TLS_PSK_WITH_AES_256_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = psk_kea;
+        ssl->specs.sig_algo              = anonymous_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        ssl->options.usingPSK_cipher     = 1;
+        break;
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_NULL_SHA256
+    case TLS_PSK_WITH_NULL_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_cipher_null;
+        ssl->specs.cipher_type           = stream;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = psk_kea;
+        ssl->specs.sig_algo              = anonymous_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = 0;
+        ssl->specs.block_size            = 0;
+        ssl->specs.iv_size               = 0;
+
+        ssl->options.usingPSK_cipher     = 1;
+        break;
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_NULL_SHA384
+    case TLS_PSK_WITH_NULL_SHA384 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_cipher_null;
+        ssl->specs.cipher_type           = stream;
+        ssl->specs.mac_algorithm         = sha384_mac;
+        ssl->specs.kea                   = psk_kea;
+        ssl->specs.sig_algo              = anonymous_sa_algo;
+        ssl->specs.hash_size             = SHA384_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = 0;
+        ssl->specs.block_size            = 0;
+        ssl->specs.iv_size               = 0;
+
+        ssl->options.usingPSK_cipher     = 1;
+        break;
+#endif
+
+#ifdef BUILD_TLS_PSK_WITH_NULL_SHA
+    case TLS_PSK_WITH_NULL_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_cipher_null;
+        ssl->specs.cipher_type           = stream;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = psk_kea;
+        ssl->specs.sig_algo              = anonymous_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = 0;
+        ssl->specs.block_size            = 0;
+        ssl->specs.iv_size               = 0;
+
+        ssl->options.usingPSK_cipher     = 1;
+        break;
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_NULL_SHA256
+    case TLS_DHE_PSK_WITH_NULL_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_cipher_null;
+        ssl->specs.cipher_type           = stream;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = dhe_psk_kea;
+        ssl->specs.sig_algo              = anonymous_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = 0;
+        ssl->specs.block_size            = 0;
+        ssl->specs.iv_size               = 0;
+
+        ssl->options.usingPSK_cipher     = 1;
+        break;
+#endif
+
+#ifdef BUILD_TLS_DHE_PSK_WITH_NULL_SHA384
+    case TLS_DHE_PSK_WITH_NULL_SHA384 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_cipher_null;
+        ssl->specs.cipher_type           = stream;
+        ssl->specs.mac_algorithm         = sha384_mac;
+        ssl->specs.kea                   = dhe_psk_kea;
+        ssl->specs.sig_algo              = anonymous_sa_algo;
+        ssl->specs.hash_size             = SHA384_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = 0;
+        ssl->specs.block_size            = 0;
+        ssl->specs.iv_size               = 0;
+
+        ssl->options.usingPSK_cipher     = 1;
+        break;
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256
+    case TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
+    case TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_128_CBC_SHA
+    case TLS_DHE_RSA_WITH_AES_128_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
+    case TLS_DHE_RSA_WITH_AES_256_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_HC_128_MD5
+    case TLS_RSA_WITH_HC_128_MD5 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_hc128;
+        ssl->specs.cipher_type           = stream;
+        ssl->specs.mac_algorithm         = md5_mac;
+        ssl->specs.kea                   = rsa_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = MD5_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_MD5;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = HC_128_KEY_SIZE;
+        ssl->specs.block_size            = 0;
+        ssl->specs.iv_size               = HC_128_IV_SIZE;
+
+        break;
+#endif
+            
+#ifdef BUILD_TLS_RSA_WITH_HC_128_SHA
+        case TLS_RSA_WITH_HC_128_SHA :
+            ssl->specs.bulk_cipher_algorithm = wolfssl_hc128;
+            ssl->specs.cipher_type           = stream;
+            ssl->specs.mac_algorithm         = sha_mac;
+            ssl->specs.kea                   = rsa_kea;
+            ssl->specs.sig_algo              = rsa_sa_algo;
+            ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+            ssl->specs.pad_size              = PAD_SHA;
+            ssl->specs.static_ecdh           = 0;
+            ssl->specs.key_size              = HC_128_KEY_SIZE;
+            ssl->specs.block_size            = 0;
+            ssl->specs.iv_size               = HC_128_IV_SIZE;
+            
+            break;
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_HC_128_B2B256
+        case TLS_RSA_WITH_HC_128_B2B256:
+            ssl->specs.bulk_cipher_algorithm = wolfssl_hc128;
+            ssl->specs.cipher_type           = stream;
+            ssl->specs.mac_algorithm         = blake2b_mac;
+            ssl->specs.kea                   = rsa_kea;
+            ssl->specs.sig_algo              = rsa_sa_algo;
+            ssl->specs.hash_size             = BLAKE2B_256;
+            ssl->specs.pad_size              = PAD_SHA;
+            ssl->specs.static_ecdh           = 0;
+            ssl->specs.key_size              = HC_128_KEY_SIZE;
+            ssl->specs.block_size            = 0;
+            ssl->specs.iv_size               = HC_128_IV_SIZE;
+            
+            break;
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_128_CBC_B2B256
+        case TLS_RSA_WITH_AES_128_CBC_B2B256:
+            ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+            ssl->specs.cipher_type           = block;
+            ssl->specs.mac_algorithm         = blake2b_mac;
+            ssl->specs.kea                   = rsa_kea;
+            ssl->specs.sig_algo              = rsa_sa_algo;
+            ssl->specs.hash_size             = BLAKE2B_256;
+            ssl->specs.pad_size              = PAD_SHA;
+            ssl->specs.static_ecdh           = 0;
+            ssl->specs.key_size              = AES_128_KEY_SIZE;
+            ssl->specs.iv_size               = AES_IV_SIZE;
+            ssl->specs.block_size            = AES_BLOCK_SIZE;
+            
+            break;
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_256_CBC_B2B256
+        case TLS_RSA_WITH_AES_256_CBC_B2B256:
+            ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+            ssl->specs.cipher_type           = block;
+            ssl->specs.mac_algorithm         = blake2b_mac;
+            ssl->specs.kea                   = rsa_kea;
+            ssl->specs.sig_algo              = rsa_sa_algo;
+            ssl->specs.hash_size             = BLAKE2B_256;
+            ssl->specs.pad_size              = PAD_SHA;
+            ssl->specs.static_ecdh           = 0;
+            ssl->specs.key_size              = AES_256_KEY_SIZE;
+            ssl->specs.iv_size               = AES_IV_SIZE;
+            ssl->specs.block_size            = AES_BLOCK_SIZE;
+            
+            break;
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_RABBIT_SHA
+    case TLS_RSA_WITH_RABBIT_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_rabbit;
+        ssl->specs.cipher_type           = stream;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = rsa_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = RABBIT_KEY_SIZE;
+        ssl->specs.block_size            = 0;
+        ssl->specs.iv_size               = RABBIT_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_128_GCM_SHA256
+    case TLS_RSA_WITH_AES_128_GCM_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_gcm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = rsa_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_GCM_AUTH_SZ;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_AES_256_GCM_SHA384
+    case TLS_RSA_WITH_AES_256_GCM_SHA384 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_gcm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha384_mac;
+        ssl->specs.kea                   = rsa_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA384_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_GCM_AUTH_SZ;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
+    case TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_gcm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_GCM_AUTH_SZ;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
+    case TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes_gcm;
+        ssl->specs.cipher_type           = aead;
+        ssl->specs.mac_algorithm         = sha384_mac;
+        ssl->specs.kea                   = diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA384_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_256_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AEAD_IMP_IV_SZ;
+        ssl->specs.aead_mac_size         = AES_GCM_AUTH_SZ;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA
+    case TLS_RSA_WITH_CAMELLIA_128_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_camellia;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = rsa_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = CAMELLIA_128_KEY_SIZE;
+        ssl->specs.block_size            = CAMELLIA_BLOCK_SIZE;
+        ssl->specs.iv_size               = CAMELLIA_IV_SIZE;
+
+        break;
+#endif
+    
+#ifdef BUILD_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA
+    case TLS_RSA_WITH_CAMELLIA_256_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_camellia;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = rsa_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = CAMELLIA_256_KEY_SIZE;
+        ssl->specs.block_size            = CAMELLIA_BLOCK_SIZE;
+        ssl->specs.iv_size               = CAMELLIA_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256
+    case TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_camellia;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = rsa_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = CAMELLIA_128_KEY_SIZE;
+        ssl->specs.block_size            = CAMELLIA_BLOCK_SIZE;
+        ssl->specs.iv_size               = CAMELLIA_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256
+    case TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_camellia;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = rsa_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = CAMELLIA_256_KEY_SIZE;
+        ssl->specs.block_size            = CAMELLIA_BLOCK_SIZE;
+        ssl->specs.iv_size               = CAMELLIA_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA
+    case TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_camellia;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = CAMELLIA_128_KEY_SIZE;
+        ssl->specs.block_size            = CAMELLIA_BLOCK_SIZE;
+        ssl->specs.iv_size               = CAMELLIA_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA
+    case TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_camellia;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = CAMELLIA_256_KEY_SIZE;
+        ssl->specs.block_size            = CAMELLIA_BLOCK_SIZE;
+        ssl->specs.iv_size               = CAMELLIA_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+    case TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_camellia;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = CAMELLIA_128_KEY_SIZE;
+        ssl->specs.block_size            = CAMELLIA_BLOCK_SIZE;
+        ssl->specs.iv_size               = CAMELLIA_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256
+    case TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256 :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_camellia;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha256_mac;
+        ssl->specs.kea                   = diffie_hellman_kea;
+        ssl->specs.sig_algo              = rsa_sa_algo;
+        ssl->specs.hash_size             = SHA256_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = CAMELLIA_256_KEY_SIZE;
+        ssl->specs.block_size            = CAMELLIA_BLOCK_SIZE;
+        ssl->specs.iv_size               = CAMELLIA_IV_SIZE;
+
+        break;
+#endif
+
+#ifdef BUILD_TLS_DH_anon_WITH_AES_128_CBC_SHA
+    case TLS_DH_anon_WITH_AES_128_CBC_SHA :
+        ssl->specs.bulk_cipher_algorithm = wolfssl_aes;
+        ssl->specs.cipher_type           = block;
+        ssl->specs.mac_algorithm         = sha_mac;
+        ssl->specs.kea                   = diffie_hellman_kea;
+        ssl->specs.sig_algo              = anonymous_sa_algo;
+        ssl->specs.hash_size             = SHA_DIGEST_SIZE;
+        ssl->specs.pad_size              = PAD_SHA;
+        ssl->specs.static_ecdh           = 0;
+        ssl->specs.key_size              = AES_128_KEY_SIZE;
+        ssl->specs.block_size            = AES_BLOCK_SIZE;
+        ssl->specs.iv_size               = AES_IV_SIZE;
+
+        ssl->options.usingAnon_cipher    = 1;
+        break;
+#endif
+
+    default:
+        WOLFSSL_MSG("Unsupported cipher suite, SetCipherSpecs");
+        return UNSUPPORTED_SUITE;
+    }  /* switch */
+    }  /* if ECC / Normal suites else */
+
+    /* set TLS if it hasn't been turned off */
+    if (ssl->version.major == 3 && ssl->version.minor >= 1) {
+#ifndef NO_TLS
+        ssl->options.tls = 1;
+        ssl->hmac = TLS_hmac;
+        if (ssl->version.minor >= 2)
+            ssl->options.tls1_1 = 1;
+#endif
+    }
+
+#ifdef WOLFSSL_DTLS
+    if (ssl->options.dtls)
+        ssl->hmac = TLS_hmac;
+#endif
+
+    return 0;
+}
+
+
+enum KeyStuff {
+    MASTER_ROUNDS = 3,
+    PREFIX        = 3,     /* up to three letters for master prefix */
+    KEY_PREFIX    = 7      /* up to 7 prefix letters for key rounds */
+
+
+};
+
+#ifndef NO_OLD_TLS
+/* true or false, zero for error */
+static int SetPrefix(byte* sha_input, int idx)
+{
+    switch (idx) {
+    case 0:
+        XMEMCPY(sha_input, "A", 1);
+        break;
+    case 1:
+        XMEMCPY(sha_input, "BB", 2);
+        break;
+    case 2:
+        XMEMCPY(sha_input, "CCC", 3);
+        break;
+    case 3:
+        XMEMCPY(sha_input, "DDDD", 4);
+        break;
+    case 4:
+        XMEMCPY(sha_input, "EEEEE", 5);
+        break;
+    case 5:
+        XMEMCPY(sha_input, "FFFFFF", 6);
+        break;
+    case 6:
+        XMEMCPY(sha_input, "GGGGGGG", 7);
+        break;
+    default:
+        WOLFSSL_MSG("Set Prefix error, bad input");
+        return 0; 
+    }
+    return 1;
+}
+#endif
+
+
+static int SetKeys(Ciphers* enc, Ciphers* dec, Keys* keys, CipherSpecs* specs,
+                   int side, void* heap, int devId)
+{
+#ifdef BUILD_ARC4
+    word32 sz = specs->key_size;
+    if (specs->bulk_cipher_algorithm == wolfssl_rc4) {
+        if (enc && enc->arc4 == NULL)
+            enc->arc4 = (Arc4*)XMALLOC(sizeof(Arc4), heap, DYNAMIC_TYPE_CIPHER);
+        if (enc && enc->arc4 == NULL)
+            return MEMORY_E;
+        if (dec && dec->arc4 == NULL)
+            dec->arc4 = (Arc4*)XMALLOC(sizeof(Arc4), heap, DYNAMIC_TYPE_CIPHER);
+        if (dec && dec->arc4 == NULL)
+            return MEMORY_E;
+#ifdef HAVE_CAVIUM
+        if (devId != NO_CAVIUM_DEVICE) {
+            if (enc) {
+                if (Arc4InitCavium(enc->arc4, devId) != 0) {
+                    WOLFSSL_MSG("Arc4InitCavium failed in SetKeys");
+                    return CAVIUM_INIT_E;
+                }
+            }
+            if (dec) {
+                if (Arc4InitCavium(dec->arc4, devId) != 0) {
+                    WOLFSSL_MSG("Arc4InitCavium failed in SetKeys");
+                    return CAVIUM_INIT_E;
+                }
+            }
+        }
+#endif
+        if (side == WOLFSSL_CLIENT_END) {
+            if (enc)
+                wc_Arc4SetKey(enc->arc4, keys->client_write_key, sz);
+            if (dec)
+                wc_Arc4SetKey(dec->arc4, keys->server_write_key, sz);
+        }
+        else {
+            if (enc)
+                wc_Arc4SetKey(enc->arc4, keys->server_write_key, sz);
+            if (dec)
+                wc_Arc4SetKey(dec->arc4, keys->client_write_key, sz);
+        }
+        if (enc)
+            enc->setup = 1;
+        if (dec)
+            dec->setup = 1;
+    }
+#endif
+
+    
+#if defined(HAVE_CHACHA) && defined(HAVE_POLY1305)
+    if (specs->bulk_cipher_algorithm == wolfssl_chacha) {
+        int chachaRet;
+        if (enc && enc->chacha == NULL)
+            enc->chacha =
+                    (ChaCha*)XMALLOC(sizeof(ChaCha), heap, DYNAMIC_TYPE_CIPHER);
+        if (enc && enc->chacha == NULL)
+            return MEMORY_E;
+        if (dec && dec->chacha == NULL)
+            dec->chacha =
+                    (ChaCha*)XMALLOC(sizeof(ChaCha), heap, DYNAMIC_TYPE_CIPHER);
+        if (dec && dec->chacha == NULL)
+            return MEMORY_E;
+        if (side == WOLFSSL_CLIENT_END) {
+            if (enc) {
+                chachaRet = wc_Chacha_SetKey(enc->chacha, keys->client_write_key,
+                                          specs->key_size);
+                XMEMCPY(keys->aead_enc_imp_IV, keys->client_write_IV,
+                        AEAD_IMP_IV_SZ);
+                if (chachaRet != 0) return chachaRet;
+            }
+            if (dec) {
+                chachaRet = wc_Chacha_SetKey(dec->chacha, keys->server_write_key,
+                                          specs->key_size);
+                XMEMCPY(keys->aead_dec_imp_IV, keys->server_write_IV,
+                        AEAD_IMP_IV_SZ);
+                if (chachaRet != 0) return chachaRet;
+            }
+        }
+        else {
+            if (enc) {
+                chachaRet = wc_Chacha_SetKey(enc->chacha, keys->server_write_key,
+                                          specs->key_size);
+                XMEMCPY(keys->aead_enc_imp_IV, keys->server_write_IV,
+                        AEAD_IMP_IV_SZ);
+                if (chachaRet != 0) return chachaRet;
+            }
+            if (dec) {
+                chachaRet = wc_Chacha_SetKey(dec->chacha, keys->client_write_key,
+                                          specs->key_size);
+                XMEMCPY(keys->aead_dec_imp_IV, keys->client_write_IV,
+                        AEAD_IMP_IV_SZ);
+                if (chachaRet != 0) return chachaRet;
+            }
+        }
+
+        if (enc)
+            enc->setup = 1;
+        if (dec)
+            dec->setup = 1;
+    }
+#endif
+
+#ifdef HAVE_HC128
+    if (specs->bulk_cipher_algorithm == wolfssl_hc128) {
+        int hcRet;
+        if (enc && enc->hc128 == NULL)
+            enc->hc128 =
+                      (HC128*)XMALLOC(sizeof(HC128), heap, DYNAMIC_TYPE_CIPHER);
+        if (enc && enc->hc128 == NULL)
+            return MEMORY_E;
+        if (dec && dec->hc128 == NULL)
+            dec->hc128 =
+                      (HC128*)XMALLOC(sizeof(HC128), heap, DYNAMIC_TYPE_CIPHER);
+        if (dec && dec->hc128 == NULL)
+            return MEMORY_E;
+        if (side == WOLFSSL_CLIENT_END) {
+            if (enc) {
+                hcRet = wc_Hc128_SetKey(enc->hc128, keys->client_write_key,
+                                     keys->client_write_IV);
+                if (hcRet != 0) return hcRet;
+            }
+            if (dec) {
+                hcRet = wc_Hc128_SetKey(dec->hc128, keys->server_write_key,
+                                     keys->server_write_IV);
+                if (hcRet != 0) return hcRet;
+            }
+        }
+        else {
+            if (enc) {
+                hcRet = wc_Hc128_SetKey(enc->hc128, keys->server_write_key,
+                                     keys->server_write_IV);
+                if (hcRet != 0) return hcRet;
+            }
+            if (dec) {
+                hcRet = wc_Hc128_SetKey(dec->hc128, keys->client_write_key,
+                                     keys->client_write_IV);
+                if (hcRet != 0) return hcRet;
+            }
+        }
+        if (enc)
+            enc->setup = 1;
+        if (dec)
+            dec->setup = 1;
+    }
+#endif
+    
+#ifdef BUILD_RABBIT
+    if (specs->bulk_cipher_algorithm == wolfssl_rabbit) {
+        int rabRet;
+        if (enc && enc->rabbit == NULL)
+            enc->rabbit =
+                    (Rabbit*)XMALLOC(sizeof(Rabbit), heap, DYNAMIC_TYPE_CIPHER);
+        if (enc && enc->rabbit == NULL)
+            return MEMORY_E;
+        if (dec && dec->rabbit == NULL)
+            dec->rabbit =
+                    (Rabbit*)XMALLOC(sizeof(Rabbit), heap, DYNAMIC_TYPE_CIPHER);
+        if (dec && dec->rabbit == NULL)
+            return MEMORY_E;
+        if (side == WOLFSSL_CLIENT_END) {
+            if (enc) {
+                rabRet = wc_RabbitSetKey(enc->rabbit, keys->client_write_key,
+                                      keys->client_write_IV);
+                if (rabRet != 0) return rabRet;
+            }
+            if (dec) {
+                rabRet = wc_RabbitSetKey(dec->rabbit, keys->server_write_key,
+                                      keys->server_write_IV);
+                if (rabRet != 0) return rabRet;
+            }
+        }
+        else {
+            if (enc) {
+                rabRet = wc_RabbitSetKey(enc->rabbit, keys->server_write_key,
+                                      keys->server_write_IV);
+                if (rabRet != 0) return rabRet;
+            }
+            if (dec) {
+                rabRet = wc_RabbitSetKey(dec->rabbit, keys->client_write_key,
+                                      keys->client_write_IV);
+                if (rabRet != 0) return rabRet;
+            }
+        }
+        if (enc)
+            enc->setup = 1;
+        if (dec)
+            dec->setup = 1;
+    }
+#endif
+    
+#ifdef BUILD_DES3
+    if (specs->bulk_cipher_algorithm == wolfssl_triple_des) {
+        int desRet = 0;
+
+        if (enc && enc->des3 == NULL)
+            enc->des3 = (Des3*)XMALLOC(sizeof(Des3), heap, DYNAMIC_TYPE_CIPHER);
+        if (enc && enc->des3 == NULL)
+            return MEMORY_E;
+        if (dec && dec->des3 == NULL)
+            dec->des3 = (Des3*)XMALLOC(sizeof(Des3), heap, DYNAMIC_TYPE_CIPHER);
+        if (dec && dec->des3 == NULL)
+            return MEMORY_E;
+#ifdef HAVE_CAVIUM
+        if (devId != NO_CAVIUM_DEVICE) {
+            if (enc) {
+                if (Des3_InitCavium(enc->des3, devId) != 0) {
+                    WOLFSSL_MSG("Des3_InitCavium failed in SetKeys");
+                    return CAVIUM_INIT_E;
+                }
+            }
+            if (dec) {
+                if (Des3_InitCavium(dec->des3, devId) != 0) {
+                    WOLFSSL_MSG("Des3_InitCavium failed in SetKeys");
+                    return CAVIUM_INIT_E;
+                }
+            }
+        }
+#endif
+        if (side == WOLFSSL_CLIENT_END) {
+            if (enc) {
+                desRet = wc_Des3_SetKey(enc->des3, keys->client_write_key,
+                                     keys->client_write_IV, DES_ENCRYPTION);
+                if (desRet != 0) return desRet;
+            }
+            if (dec) {
+                desRet = wc_Des3_SetKey(dec->des3, keys->server_write_key,
+                                     keys->server_write_IV, DES_DECRYPTION);
+                if (desRet != 0) return desRet;
+            }
+        }
+        else {
+            if (enc) {
+                desRet = wc_Des3_SetKey(enc->des3, keys->server_write_key,
+                                     keys->server_write_IV, DES_ENCRYPTION);
+                if (desRet != 0) return desRet;
+            }
+            if (dec) {
+                desRet = wc_Des3_SetKey(dec->des3, keys->client_write_key,
+                                     keys->client_write_IV, DES_DECRYPTION);
+                if (desRet != 0) return desRet;
+            }
+        }
+        if (enc)
+            enc->setup = 1;
+        if (dec)
+            dec->setup = 1;
+    }
+#endif
+
+#ifdef BUILD_AES
+    if (specs->bulk_cipher_algorithm == wolfssl_aes) {
+        int aesRet = 0;
+
+        if (enc && enc->aes == NULL)
+            enc->aes = (Aes*)XMALLOC(sizeof(Aes), heap, DYNAMIC_TYPE_CIPHER);
+        if (enc && enc->aes == NULL)
+            return MEMORY_E;
+        if (dec && dec->aes == NULL)
+            dec->aes = (Aes*)XMALLOC(sizeof(Aes), heap, DYNAMIC_TYPE_CIPHER);
+        if (dec && dec->aes == NULL)
+            return MEMORY_E;
+#ifdef HAVE_CAVIUM
+        if (devId != NO_CAVIUM_DEVICE) {
+            if (enc) {
+                if (wc_AesInitCavium(enc->aes, devId) != 0) {
+                    WOLFSSL_MSG("AesInitCavium failed in SetKeys");
+                    return CAVIUM_INIT_E;
+                }
+            }
+            if (dec) {
+                if (wc_AesInitCavium(dec->aes, devId) != 0) {
+                    WOLFSSL_MSG("AesInitCavium failed in SetKeys");
+                    return CAVIUM_INIT_E;
+                }
+            }
+        }
+#endif
+        if (side == WOLFSSL_CLIENT_END) {
+            if (enc) {
+                aesRet = wc_AesSetKey(enc->aes, keys->client_write_key,
+                                   specs->key_size, keys->client_write_IV,
+                                   AES_ENCRYPTION);
+                if (aesRet != 0) return aesRet;
+            }
+            if (dec) {
+                aesRet = wc_AesSetKey(dec->aes, keys->server_write_key,
+                                   specs->key_size, keys->server_write_IV,
+                                   AES_DECRYPTION);
+                if (aesRet != 0) return aesRet;
+            }
+        }
+        else {
+            if (enc) {
+                aesRet = wc_AesSetKey(enc->aes, keys->server_write_key,
+                                   specs->key_size, keys->server_write_IV,
+                                   AES_ENCRYPTION);
+                if (aesRet != 0) return aesRet;
+            }
+            if (dec) {
+                aesRet = wc_AesSetKey(dec->aes, keys->client_write_key,
+                                   specs->key_size, keys->client_write_IV,
+                                   AES_DECRYPTION);
+                if (aesRet != 0) return aesRet;
+            }
+        }
+        if (enc)
+            enc->setup = 1;
+        if (dec)
+            dec->setup = 1;
+    }
+#endif
+
+#ifdef BUILD_AESGCM
+    if (specs->bulk_cipher_algorithm == wolfssl_aes_gcm) {
+        int gcmRet;
+
+        if (enc && enc->aes == NULL)
+            enc->aes = (Aes*)XMALLOC(sizeof(Aes), heap, DYNAMIC_TYPE_CIPHER);
+        if (enc && enc->aes == NULL)
+            return MEMORY_E;
+        if (dec && dec->aes == NULL)
+            dec->aes = (Aes*)XMALLOC(sizeof(Aes), heap, DYNAMIC_TYPE_CIPHER);
+        if (dec && dec->aes == NULL)
+            return MEMORY_E;
+
+        if (side == WOLFSSL_CLIENT_END) {
+            if (enc) {
+                gcmRet = wc_AesGcmSetKey(enc->aes, keys->client_write_key,
+                                      specs->key_size);
+                if (gcmRet != 0) return gcmRet;
+                XMEMCPY(keys->aead_enc_imp_IV, keys->client_write_IV,
+                        AEAD_IMP_IV_SZ);
+            }
+            if (dec) {
+                gcmRet = wc_AesGcmSetKey(dec->aes, keys->server_write_key,
+                                      specs->key_size);
+                if (gcmRet != 0) return gcmRet;
+                XMEMCPY(keys->aead_dec_imp_IV, keys->server_write_IV,
+                        AEAD_IMP_IV_SZ);
+            }
+        }
+        else {
+            if (enc) {
+                gcmRet = wc_AesGcmSetKey(enc->aes, keys->server_write_key,
+                                      specs->key_size);
+                if (gcmRet != 0) return gcmRet;
+                XMEMCPY(keys->aead_enc_imp_IV, keys->server_write_IV,
+                        AEAD_IMP_IV_SZ);
+            }
+            if (dec) {
+                gcmRet = wc_AesGcmSetKey(dec->aes, keys->client_write_key,
+                                      specs->key_size);
+                if (gcmRet != 0) return gcmRet;
+                XMEMCPY(keys->aead_dec_imp_IV, keys->client_write_IV,
+                        AEAD_IMP_IV_SZ);
+            }
+        }
+        if (enc)
+            enc->setup = 1;
+        if (dec)
+            dec->setup = 1;
+    }
+#endif
+
+#ifdef HAVE_AESCCM
+    if (specs->bulk_cipher_algorithm == wolfssl_aes_ccm) {
+        if (enc && enc->aes == NULL)
+            enc->aes = (Aes*)XMALLOC(sizeof(Aes), heap, DYNAMIC_TYPE_CIPHER);
+        if (enc && enc->aes == NULL)
+            return MEMORY_E;
+        if (dec && dec->aes == NULL)
+            dec->aes = (Aes*)XMALLOC(sizeof(Aes), heap, DYNAMIC_TYPE_CIPHER);
+        if (dec && dec->aes == NULL)
+            return MEMORY_E;
+
+        if (side == WOLFSSL_CLIENT_END) {
+            if (enc) {
+                wc_AesCcmSetKey(enc->aes, keys->client_write_key, specs->key_size);
+                XMEMCPY(keys->aead_enc_imp_IV, keys->client_write_IV,
+                        AEAD_IMP_IV_SZ);
+            }
+            if (dec) {
+                wc_AesCcmSetKey(dec->aes, keys->server_write_key, specs->key_size);
+                XMEMCPY(keys->aead_dec_imp_IV, keys->server_write_IV,
+                        AEAD_IMP_IV_SZ);
+            }
+        }
+        else {
+            if (enc) {
+                wc_AesCcmSetKey(enc->aes, keys->server_write_key, specs->key_size);
+                XMEMCPY(keys->aead_enc_imp_IV, keys->server_write_IV,
+                        AEAD_IMP_IV_SZ);
+            }
+            if (dec) {
+                wc_AesCcmSetKey(dec->aes, keys->client_write_key, specs->key_size);
+                XMEMCPY(keys->aead_dec_imp_IV, keys->client_write_IV,
+                        AEAD_IMP_IV_SZ);
+            }
+        }
+        if (enc)
+            enc->setup = 1;
+        if (dec)
+            dec->setup = 1;
+    }
+#endif
+
+#ifdef HAVE_CAMELLIA
+    if (specs->bulk_cipher_algorithm == wolfssl_camellia) {
+        int camRet;
+
+        if (enc && enc->cam == NULL)
+            enc->cam =
+                (Camellia*)XMALLOC(sizeof(Camellia), heap, DYNAMIC_TYPE_CIPHER);
+        if (enc && enc->cam == NULL)
+            return MEMORY_E;
+
+        if (dec && dec->cam == NULL)
+            dec->cam =
+                (Camellia*)XMALLOC(sizeof(Camellia), heap, DYNAMIC_TYPE_CIPHER);
+        if (dec && dec->cam == NULL)
+            return MEMORY_E;
+
+        if (side == WOLFSSL_CLIENT_END) {
+            if (enc) {
+                camRet = wc_CamelliaSetKey(enc->cam, keys->client_write_key,
+                                        specs->key_size, keys->client_write_IV);
+                if (camRet != 0) return camRet;
+            }
+            if (dec) {
+                camRet = wc_CamelliaSetKey(dec->cam, keys->server_write_key,
+                                        specs->key_size, keys->server_write_IV);
+                if (camRet != 0) return camRet;
+            }
+        }
+        else {
+            if (enc) {
+                camRet = wc_CamelliaSetKey(enc->cam, keys->server_write_key,
+                                        specs->key_size, keys->server_write_IV);
+                if (camRet != 0) return camRet;
+            }
+            if (dec) {
+                camRet = wc_CamelliaSetKey(dec->cam, keys->client_write_key,
+                                        specs->key_size, keys->client_write_IV);
+                if (camRet != 0) return camRet;
+            }
+        }
+        if (enc)
+            enc->setup = 1;
+        if (dec)
+            dec->setup = 1;
+    }
+#endif
+
+#ifdef HAVE_NULL_CIPHER
+    if (specs->bulk_cipher_algorithm == wolfssl_cipher_null) {
+        if (enc)
+            enc->setup = 1;
+        if (dec)
+            dec->setup = 1;
+    }
+#endif
+
+    if (enc)
+        keys->sequence_number      = 0;
+    if (dec)
+        keys->peer_sequence_number = 0;
+    (void)side;
+    (void)heap;
+    (void)enc;
+    (void)dec;
+    (void)specs;
+    (void)devId;
+
+    return 0;
+}
+
+
+#ifdef HAVE_ONE_TIME_AUTH
+/* set one time authentication keys */
+static int SetAuthKeys(OneTimeAuth* authentication, Keys* keys,
+                       CipherSpecs* specs, void* heap, int devId)
+{
+
+#ifdef HAVE_POLY1305
+        /* set up memory space for poly1305 */
+        if (authentication && authentication->poly1305 == NULL)
+            authentication->poly1305 =
+                (Poly1305*)XMALLOC(sizeof(Poly1305), heap, DYNAMIC_TYPE_CIPHER);
+        if (authentication && authentication->poly1305 == NULL)
+            return MEMORY_E;
+        if (authentication)
+            authentication->setup = 1;
+#endif
+        (void)heap;
+        (void)keys;
+        (void)specs;
+        (void)devId;
+
+        return 0;
+}
+#endif /* HAVE_ONE_TIME_AUTH */
+
+
+/* Set wc_encrypt/wc_decrypt or both sides of key setup
+ * note: use wc_encrypt to avoid shadowing global encrypt
+ * declared in unistd.h
+ */
+int SetKeysSide(WOLFSSL* ssl, enum encrypt_side side)
+{
+    int devId = NO_CAVIUM_DEVICE, ret, copy = 0;
+    Ciphers* wc_encrypt = NULL;
+    Ciphers* wc_decrypt = NULL;
+    Keys*    keys    = &ssl->keys;
+
+    (void)copy;
+
+#ifdef HAVE_CAVIUM
+    devId = ssl->devId;
+#endif
+
+#ifdef HAVE_SECURE_RENEGOTIATION
+    if (ssl->secure_renegotiation && ssl->secure_renegotiation->cache_status) {
+        keys = &ssl->secure_renegotiation->tmp_keys;
+        copy = 1;
+    }
+#endif /* HAVE_SECURE_RENEGOTIATION */
+
+    switch (side) {
+        case ENCRYPT_SIDE_ONLY:
+            wc_encrypt = &ssl->encrypt;
+            break;
+
+        case DECRYPT_SIDE_ONLY:
+            wc_decrypt = &ssl->decrypt;
+            break;
+
+        case ENCRYPT_AND_DECRYPT_SIDE:
+            wc_encrypt = &ssl->encrypt;
+            wc_decrypt = &ssl->decrypt;
+            break;
+
+        default:
+            return BAD_FUNC_ARG;
+    }
+
+#ifdef HAVE_ONE_TIME_AUTH
+    if (!ssl->auth.setup && ssl->specs.bulk_cipher_algorithm == wolfssl_chacha){
+        ret = SetAuthKeys(&ssl->auth, keys, &ssl->specs, ssl->heap, devId);
+        if (ret != 0)
+           return ret;
+    }
+#endif
+
+    ret = SetKeys(wc_encrypt, wc_decrypt, keys, &ssl->specs, ssl->options.side,
+                  ssl->heap, devId);
+
+#ifdef HAVE_SECURE_RENEGOTIATION
+    if (copy) {
+        int clientCopy = 0;
+
+        if (ssl->options.side == WOLFSSL_CLIENT_END && wc_encrypt)
+            clientCopy = 1;
+        else if (ssl->options.side == WOLFSSL_SERVER_END && wc_decrypt)
+            clientCopy = 1;
+
+        if (clientCopy) {
+            XMEMCPY(ssl->keys.client_write_MAC_secret,
+                    keys->client_write_MAC_secret, MAX_DIGEST_SIZE);
+            XMEMCPY(ssl->keys.client_write_key,
+                    keys->client_write_key, AES_256_KEY_SIZE);
+            XMEMCPY(ssl->keys.client_write_IV,
+                    keys->client_write_IV, AES_IV_SIZE);
+        } else {
+            XMEMCPY(ssl->keys.server_write_MAC_secret,
+                    keys->server_write_MAC_secret, MAX_DIGEST_SIZE);
+            XMEMCPY(ssl->keys.server_write_key,
+                    keys->server_write_key, AES_256_KEY_SIZE);
+            XMEMCPY(ssl->keys.server_write_IV,
+                    keys->server_write_IV, AES_IV_SIZE);
+        }
+        if (wc_encrypt) {
+            ssl->keys.sequence_number = keys->sequence_number;
+            #ifdef HAVE_AEAD
+                if (ssl->specs.cipher_type == aead) {
+                    /* Initialize the AES-GCM/CCM explicit IV to a zero. */
+                    XMEMCPY(ssl->keys.aead_exp_IV, keys->aead_exp_IV,
+                            AEAD_EXP_IV_SZ);
+
+                    /* Initialize encrypt implicit IV by encrypt side */
+                    if (ssl->options.side == WOLFSSL_CLIENT_END) {
+                        XMEMCPY(ssl->keys.aead_enc_imp_IV,
+                                keys->client_write_IV, AEAD_IMP_IV_SZ);
+                    } else {
+                        XMEMCPY(ssl->keys.aead_enc_imp_IV,
+                                keys->server_write_IV, AEAD_IMP_IV_SZ);
+                    }
+                }
+            #endif
+        }
+        if (wc_decrypt) {
+            ssl->keys.peer_sequence_number = keys->peer_sequence_number;
+            #ifdef HAVE_AEAD
+                if (ssl->specs.cipher_type == aead) {
+                    /* Initialize decrypt implicit IV by decrypt side */
+                    if (ssl->options.side == WOLFSSL_SERVER_END) {
+                        XMEMCPY(ssl->keys.aead_dec_imp_IV,
+                                keys->client_write_IV, AEAD_IMP_IV_SZ);
+                    } else {
+                        XMEMCPY(ssl->keys.aead_dec_imp_IV,
+                                keys->server_write_IV, AEAD_IMP_IV_SZ);
+                    }
+                }
+            #endif
+        }
+        ssl->secure_renegotiation->cache_status++;
+    }
+#endif /* HAVE_SECURE_RENEGOTIATION */
+
+    return ret;
+}
+
+
+/* TLS can call too */
+int StoreKeys(WOLFSSL* ssl, const byte* keyData)
+{
+    int sz, i = 0;
+    Keys* keys = &ssl->keys;
+
+#ifdef HAVE_SECURE_RENEGOTIATION
+    if (ssl->secure_renegotiation && ssl->secure_renegotiation->cache_status ==
+                                                            SCR_CACHE_NEEDED) {
+        keys = &ssl->secure_renegotiation->tmp_keys;
+        ssl->secure_renegotiation->cache_status++;
+    }
+#endif /* HAVE_SECURE_RENEGOTIATION */
+
+    if (ssl->specs.cipher_type != aead) {
+        sz = ssl->specs.hash_size;
+        XMEMCPY(keys->client_write_MAC_secret,&keyData[i], sz);
+        i += sz;
+        XMEMCPY(keys->server_write_MAC_secret,&keyData[i], sz);
+        i += sz;
+    }
+    sz = ssl->specs.key_size;
+    XMEMCPY(keys->client_write_key, &keyData[i], sz);
+    i += sz;
+    XMEMCPY(keys->server_write_key, &keyData[i], sz);
+    i += sz;
+
+    sz = ssl->specs.iv_size;
+    XMEMCPY(keys->client_write_IV, &keyData[i], sz);
+    i += sz;
+    XMEMCPY(keys->server_write_IV, &keyData[i], sz);
+
+#ifdef HAVE_AEAD
+    if (ssl->specs.cipher_type == aead) {
+        /* Initialize the AES-GCM/CCM explicit IV to a zero. */
+        XMEMSET(keys->aead_exp_IV, 0, AEAD_EXP_IV_SZ);
+    }
+#endif
+
+    return 0;
+}
+
+#ifndef NO_OLD_TLS
+int DeriveKeys(WOLFSSL* ssl)
+{
+    int    length = 2 * ssl->specs.hash_size + 
+                    2 * ssl->specs.key_size  +
+                    2 * ssl->specs.iv_size;
+    int    rounds = (length + MD5_DIGEST_SIZE - 1 ) / MD5_DIGEST_SIZE, i;
+    int    ret = 0;
+    
+#ifdef WOLFSSL_SMALL_STACK
+    byte*  shaOutput;
+    byte*  md5Input;
+    byte*  shaInput;
+    byte*  keyData;
+    Md5*   md5;
+    Sha*   sha;
+#else
+    byte   shaOutput[SHA_DIGEST_SIZE];
+    byte   md5Input[SECRET_LEN + SHA_DIGEST_SIZE];
+    byte   shaInput[KEY_PREFIX + SECRET_LEN + 2 * RAN_LEN];
+    byte   keyData[KEY_PREFIX * MD5_DIGEST_SIZE];
+    Md5    md5[1];
+    Sha    sha[1];
+#endif
+    
+#ifdef WOLFSSL_SMALL_STACK
+    shaOutput = (byte*)XMALLOC(SHA_DIGEST_SIZE, 
+                                            NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    md5Input  = (byte*)XMALLOC(SECRET_LEN + SHA_DIGEST_SIZE,
+                                            NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    shaInput  = (byte*)XMALLOC(KEY_PREFIX + SECRET_LEN + 2 * RAN_LEN,
+                                            NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    keyData   = (byte*)XMALLOC(KEY_PREFIX * MD5_DIGEST_SIZE,
+                                            NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    md5       =  (Md5*)XMALLOC(sizeof(Md5), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    sha       =  (Sha*)XMALLOC(sizeof(Sha), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    
+    if (shaOutput == NULL || md5Input == NULL || shaInput == NULL ||
+        keyData   == NULL || md5      == NULL || sha      == NULL) {
+        if (shaOutput) XFREE(shaOutput, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (md5Input)  XFREE(md5Input,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (shaInput)  XFREE(shaInput,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (keyData)   XFREE(keyData,   NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (md5)       XFREE(md5,       NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (sha)       XFREE(sha,       NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        
+        return MEMORY_E;
+    }
+#endif
+
+    wc_InitMd5(md5);
+
+    ret = wc_InitSha(sha);
+
+    if (ret == 0) {
+        XMEMCPY(md5Input, ssl->arrays->masterSecret, SECRET_LEN);
+
+        for (i = 0; i < rounds; ++i) {
+            int j   = i + 1;
+            int idx = j;
+
+            if (!SetPrefix(shaInput, i)) {
+                ret = PREFIX_ERROR;
+                break;
+            }
+
+            XMEMCPY(shaInput + idx, ssl->arrays->masterSecret, SECRET_LEN);
+            idx += SECRET_LEN;
+            XMEMCPY(shaInput + idx, ssl->arrays->serverRandom, RAN_LEN);
+            idx += RAN_LEN;
+            XMEMCPY(shaInput + idx, ssl->arrays->clientRandom, RAN_LEN);
+
+            wc_ShaUpdate(sha, shaInput, (KEY_PREFIX + SECRET_LEN + 2 * RAN_LEN)
+                                                              - KEY_PREFIX + j);
+            wc_ShaFinal(sha, shaOutput);
+
+            XMEMCPY(md5Input + SECRET_LEN, shaOutput, SHA_DIGEST_SIZE);
+            wc_Md5Update(md5, md5Input, SECRET_LEN + SHA_DIGEST_SIZE);
+            wc_Md5Final(md5, keyData + i * MD5_DIGEST_SIZE);
+        }
+
+        if (ret == 0)
+            ret = StoreKeys(ssl, keyData);
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(shaOutput, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(md5Input,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(shaInput,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(keyData,   NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(md5,       NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(sha,       NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+
+static int CleanPreMaster(WOLFSSL* ssl)
+{
+    int i, ret, sz = ssl->arrays->preMasterSz;
+
+    for (i = 0; i < sz; i++)
+        ssl->arrays->preMasterSecret[i] = 0;
+
+    ret = wc_RNG_GenerateBlock(ssl->rng, ssl->arrays->preMasterSecret, sz);
+    if (ret != 0)
+        return ret;
+
+    for (i = 0; i < sz; i++)
+        ssl->arrays->preMasterSecret[i] = 0;
+
+    return 0;
+}
+
+
+/* Create and store the master secret see page 32, 6.1 */
+static int MakeSslMasterSecret(WOLFSSL* ssl)
+{
+    int    i, ret;
+    word32 idx;
+    word32 pmsSz = ssl->arrays->preMasterSz;
+
+#ifdef WOLFSSL_SMALL_STACK
+    byte*  shaOutput;
+    byte*  md5Input;
+    byte*  shaInput;
+    Md5*   md5;
+    Sha*   sha;
+#else
+    byte   shaOutput[SHA_DIGEST_SIZE];
+    byte   md5Input[ENCRYPT_LEN + SHA_DIGEST_SIZE];
+    byte   shaInput[PREFIX + ENCRYPT_LEN + 2 * RAN_LEN];
+    Md5    md5[1];
+    Sha    sha[1];
+#endif
+
+#ifdef SHOW_SECRETS
+    {
+        word32 j;
+        printf("pre master secret: ");
+        for (j = 0; j < pmsSz; j++)
+            printf("%02x", ssl->arrays->preMasterSecret[j]);
+        printf("\n");
+    }
+#endif
+    
+#ifdef WOLFSSL_SMALL_STACK
+    shaOutput = (byte*)XMALLOC(SHA_DIGEST_SIZE, 
+                                            NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    md5Input  = (byte*)XMALLOC(ENCRYPT_LEN + SHA_DIGEST_SIZE,
+                                            NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    shaInput  = (byte*)XMALLOC(PREFIX + ENCRYPT_LEN + 2 * RAN_LEN,
+                                            NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    md5       =  (Md5*)XMALLOC(sizeof(Md5), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    sha       =  (Sha*)XMALLOC(sizeof(Sha), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    
+    if (shaOutput == NULL || md5Input == NULL || shaInput == NULL ||
+                             md5      == NULL || sha      == NULL) {
+        if (shaOutput) XFREE(shaOutput, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (md5Input)  XFREE(md5Input,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (shaInput)  XFREE(shaInput,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (md5)       XFREE(md5,       NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (sha)       XFREE(sha,       NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        
+        return MEMORY_E;
+    }
+#endif
+
+    wc_InitMd5(md5);
+    
+    ret = wc_InitSha(sha);
+    
+    if (ret == 0) {
+        XMEMCPY(md5Input, ssl->arrays->preMasterSecret, pmsSz);
+
+        for (i = 0; i < MASTER_ROUNDS; ++i) {
+            byte prefix[KEY_PREFIX];      /* only need PREFIX bytes but static */
+            if (!SetPrefix(prefix, i)) {  /* analysis thinks will overrun      */
+                ret = PREFIX_ERROR;
+                break;
+            }
+
+            idx = 0;
+            XMEMCPY(shaInput, prefix, i + 1);
+            idx += i + 1;
+
+            XMEMCPY(shaInput + idx, ssl->arrays->preMasterSecret, pmsSz);
+            idx += pmsSz;
+            XMEMCPY(shaInput + idx, ssl->arrays->clientRandom, RAN_LEN);
+            idx += RAN_LEN;
+            XMEMCPY(shaInput + idx, ssl->arrays->serverRandom, RAN_LEN);
+            idx += RAN_LEN;
+            wc_ShaUpdate(sha, shaInput, idx);
+            wc_ShaFinal(sha, shaOutput);
+
+            idx = pmsSz;  /* preSz */
+            XMEMCPY(md5Input + idx, shaOutput, SHA_DIGEST_SIZE);
+            idx += SHA_DIGEST_SIZE;
+            wc_Md5Update(md5, md5Input, idx);
+            wc_Md5Final(md5, &ssl->arrays->masterSecret[i * MD5_DIGEST_SIZE]);
+        }
+
+#ifdef SHOW_SECRETS
+        {
+            word32 j;
+            printf("master secret: ");
+            for (j = 0; j < SECRET_LEN; j++)
+                printf("%02x", ssl->arrays->masterSecret[j]);
+            printf("\n");
+        }
+#endif
+
+        if (ret == 0)
+            ret = DeriveKeys(ssl);
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(shaOutput, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(md5Input,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(shaInput,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(md5,       NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(sha,       NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+    
+    if (ret == 0)
+        ret = CleanPreMaster(ssl);
+    else
+        CleanPreMaster(ssl);
+
+    return ret;
+}
+#endif
+
+
+/* Master wrapper, doesn't use SSL stack space in TLS mode */
+int MakeMasterSecret(WOLFSSL* ssl)
+{
+#ifdef NO_OLD_TLS
+    return MakeTlsMasterSecret(ssl);
+#elif !defined(NO_TLS)
+    if (ssl->options.tls) return MakeTlsMasterSecret(ssl);
+#endif
+
+#ifndef NO_OLD_TLS
+    return MakeSslMasterSecret(ssl);
+#endif
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/ocsp.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/ocsp.c
new file mode 100644
index 0000000..1794d63
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/ocsp.c
@@ -0,0 +1,303 @@
+/* ocsp.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+  /* Name change compatibility layer no longer needs to be included here */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifdef HAVE_OCSP
+
+#include 
+#include 
+#include 
+
+
+int InitOCSP(WOLFSSL_OCSP* ocsp, WOLFSSL_CERT_MANAGER* cm)
+{
+    WOLFSSL_ENTER("InitOCSP");
+    XMEMSET(ocsp, 0, sizeof(*ocsp));
+    ocsp->cm = cm;
+    if (InitMutex(&ocsp->ocspLock) != 0)
+        return BAD_MUTEX_E;
+
+    return 0;
+}
+
+
+static int InitOCSP_Entry(OCSP_Entry* ocspe, DecodedCert* cert)
+{
+    WOLFSSL_ENTER("InitOCSP_Entry");
+
+    XMEMSET(ocspe, 0, sizeof(*ocspe));
+    XMEMCPY(ocspe->issuerHash, cert->issuerHash, SHA_DIGEST_SIZE);
+    XMEMCPY(ocspe->issuerKeyHash, cert->issuerKeyHash, SHA_DIGEST_SIZE);
+
+    return 0;
+}
+
+
+static void FreeOCSP_Entry(OCSP_Entry* ocspe)
+{
+    CertStatus* tmp = ocspe->status;
+
+    WOLFSSL_ENTER("FreeOCSP_Entry");
+
+    while (tmp) {
+        CertStatus* next = tmp->next;
+        XFREE(tmp, NULL, DYNAMIC_TYPE_OCSP_STATUS);
+        tmp = next;
+    }
+}
+
+
+void FreeOCSP(WOLFSSL_OCSP* ocsp, int dynamic)
+{
+    OCSP_Entry* tmp = ocsp->ocspList;
+
+    WOLFSSL_ENTER("FreeOCSP");
+
+    while (tmp) {
+        OCSP_Entry* next = tmp->next;
+        FreeOCSP_Entry(tmp);
+        XFREE(tmp, NULL, DYNAMIC_TYPE_OCSP_ENTRY);
+        tmp = next;
+    }
+
+    FreeMutex(&ocsp->ocspLock);
+    if (dynamic)
+        XFREE(ocsp, NULL, DYNAMIC_TYPE_OCSP);
+}
+
+
+static int xstat2err(int stat)
+{
+    switch (stat) {
+        case CERT_GOOD:
+            return 0;
+        case CERT_REVOKED:
+            return OCSP_CERT_REVOKED;
+        default:
+            return OCSP_CERT_UNKNOWN;
+    }
+}
+
+
+int CheckCertOCSP(WOLFSSL_OCSP* ocsp, DecodedCert* cert)
+{
+    byte* ocspReqBuf = NULL;
+    int ocspReqSz = 2048;
+    byte* ocspRespBuf = NULL;
+    int result = -1;
+    OCSP_Entry* ocspe;
+    CertStatus* certStatus = NULL;
+    const char *url;
+    int urlSz;
+#ifdef WOLFSSL_SMALL_STACK
+    CertStatus* newStatus;
+    OcspRequest* ocspRequest;
+    OcspResponse* ocspResponse;
+#else
+    CertStatus newStatus[1];
+    OcspRequest ocspRequest[1];
+    OcspResponse ocspResponse[1];
+#endif
+
+    WOLFSSL_ENTER("CheckCertOCSP");
+
+    if (LockMutex(&ocsp->ocspLock) != 0) {
+        WOLFSSL_LEAVE("CheckCertOCSP", BAD_MUTEX_E);
+        return BAD_MUTEX_E;
+    }
+
+    ocspe = ocsp->ocspList;
+    while (ocspe) {
+        if (XMEMCMP(ocspe->issuerHash, cert->issuerHash, SHA_DIGEST_SIZE) == 0
+            && XMEMCMP(ocspe->issuerKeyHash, cert->issuerKeyHash,
+                                                        SHA_DIGEST_SIZE) == 0)
+            break;
+        else
+            ocspe = ocspe->next;
+    }
+
+    if (ocspe == NULL) {
+        ocspe = (OCSP_Entry*)XMALLOC(sizeof(OCSP_Entry),
+                                                NULL, DYNAMIC_TYPE_OCSP_ENTRY);
+        if (ocspe != NULL) {
+            InitOCSP_Entry(ocspe, cert);
+            ocspe->next = ocsp->ocspList;
+            ocsp->ocspList = ocspe;
+        }
+        else {
+            UnLockMutex(&ocsp->ocspLock);
+            WOLFSSL_LEAVE("CheckCertOCSP", MEMORY_ERROR);
+            return MEMORY_ERROR;
+        }
+    }
+    else {
+        certStatus = ocspe->status;
+        while (certStatus) {
+            if (certStatus->serialSz == cert->serialSz &&
+                 XMEMCMP(certStatus->serial, cert->serial, cert->serialSz) == 0)
+                break;
+            else
+                certStatus = certStatus->next;
+        }
+    }
+
+    if (certStatus != NULL) {
+        if (!ValidateDate(certStatus->thisDate,
+                                        certStatus->thisDateFormat, BEFORE) ||
+            (certStatus->nextDate[0] == 0) ||
+            !ValidateDate(certStatus->nextDate,
+                                        certStatus->nextDateFormat, AFTER)) {
+            WOLFSSL_MSG("\tinvalid status date, looking up cert");
+        }
+        else {
+            result = xstat2err(certStatus->status);
+            UnLockMutex(&ocsp->ocspLock);
+            WOLFSSL_LEAVE("CheckCertOCSP", result);
+            return result;
+        }
+    }
+
+    UnLockMutex(&ocsp->ocspLock);
+
+    if (ocsp->cm->ocspUseOverrideURL) {
+        url = ocsp->cm->ocspOverrideURL;
+        if (url != NULL && url[0] != '\0')
+            urlSz = (int)XSTRLEN(url);
+        else
+            return OCSP_NEED_URL;
+    }
+    else if (cert->extAuthInfoSz != 0 && cert->extAuthInfo != NULL) {
+        url = (const char *)cert->extAuthInfo;
+        urlSz = cert->extAuthInfoSz;
+    }
+    else {
+        /* cert doesn't have extAuthInfo, assuming CERT_GOOD */
+        return 0;
+    }
+
+    ocspReqBuf = (byte*)XMALLOC(ocspReqSz, NULL, DYNAMIC_TYPE_IN_BUFFER);
+    if (ocspReqBuf == NULL) {
+        WOLFSSL_LEAVE("CheckCertOCSP", MEMORY_ERROR);
+        return MEMORY_ERROR;
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    newStatus = (CertStatus*)XMALLOC(sizeof(CertStatus), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+    ocspRequest = (OcspRequest*)XMALLOC(sizeof(OcspRequest), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+    ocspResponse = (OcspResponse*)XMALLOC(sizeof(OcspResponse), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+
+    if (newStatus == NULL || ocspRequest == NULL || ocspResponse == NULL) {
+        if (newStatus)    XFREE(newStatus,    NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (ocspRequest)  XFREE(ocspRequest,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (ocspResponse) XFREE(ocspResponse, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+
+        XFREE(ocspReqBuf, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+
+        WOLFSSL_LEAVE("CheckCertOCSP", MEMORY_ERROR);
+        return MEMORY_E;
+    }
+#endif
+
+    InitOcspRequest(ocspRequest, cert, ocsp->cm->ocspSendNonce,
+                                                         ocspReqBuf, ocspReqSz);
+    ocspReqSz = EncodeOcspRequest(ocspRequest);
+    
+    if (ocsp->cm->ocspIOCb)
+        result = ocsp->cm->ocspIOCb(ocsp->cm->ocspIOCtx, url, urlSz,
+                                           ocspReqBuf, ocspReqSz, &ocspRespBuf);
+
+    if (result >= 0 && ocspRespBuf) {
+        XMEMSET(newStatus, 0, sizeof(CertStatus));
+
+        InitOcspResponse(ocspResponse, newStatus, ocspRespBuf, result);
+        OcspResponseDecode(ocspResponse);
+    
+        if (ocspResponse->responseStatus != OCSP_SUCCESSFUL)
+            result = OCSP_LOOKUP_FAIL;
+        else {
+            if (CompareOcspReqResp(ocspRequest, ocspResponse) == 0) {
+                result = xstat2err(ocspResponse->status->status);
+
+                if (LockMutex(&ocsp->ocspLock) != 0)
+                    result = BAD_MUTEX_E;
+                else {
+                    if (certStatus != NULL)
+                        /* Replace existing certificate entry with updated */
+                        XMEMCPY(certStatus, newStatus, sizeof(CertStatus));
+                    else {
+                        /* Save new certificate entry */
+                        certStatus = (CertStatus*)XMALLOC(sizeof(CertStatus),
+                                          NULL, DYNAMIC_TYPE_OCSP_STATUS);
+                        if (certStatus != NULL) {
+                            XMEMCPY(certStatus, newStatus, sizeof(CertStatus));
+                            certStatus->next = ocspe->status;
+                            ocspe->status = certStatus;
+                            ocspe->totalStatus++;
+                        }
+                    }
+
+                    UnLockMutex(&ocsp->ocspLock);
+                }
+            }
+            else
+                result = OCSP_LOOKUP_FAIL;
+        }
+    }
+    else
+        result = OCSP_LOOKUP_FAIL;
+
+    XFREE(ocspReqBuf, NULL, DYNAMIC_TYPE_IN_BUFFER);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(newStatus,    NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(ocspRequest,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(ocspResponse, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    if (ocspRespBuf != NULL && ocsp->cm->ocspRespFreeCb)
+        ocsp->cm->ocspRespFreeCb(ocsp->cm->ocspIOCtx, ocspRespBuf);
+
+    WOLFSSL_LEAVE("CheckCertOCSP", result);
+    return result;
+}
+
+
+#else /* HAVE_OCSP */
+
+
+#ifdef _MSC_VER
+    /* 4206 warning for blank file */
+    #pragma warning(disable: 4206)
+#endif
+
+
+#endif /* HAVE_OCSP */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/sniffer.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/sniffer.c
new file mode 100644
index 0000000..b961f7b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/sniffer.c
@@ -0,0 +1,2948 @@
+/* sniffer.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifdef WOLFSSL_SNIFFER
+
+#include 
+#include 
+
+#ifndef _WIN32
+  #include 
+#endif
+
+#ifdef _WIN32
+    #define SNPRINTF _snprintf
+#else
+    #define SNPRINTF snprintf
+#endif
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+
+#ifndef WOLFSSL_HAVE_MIN
+#define WOLFSSL_HAVE_MIN
+
+static INLINE word32 min(word32 a, word32 b)
+{
+    return a > b ? b : a;
+}
+
+#endif /* WOLFSSL_HAVE_MIN */
+
+#ifndef WOLFSSL_SNIFFER_TIMEOUT
+    #define WOLFSSL_SNIFFER_TIMEOUT 900
+    /* Cache unclosed Sessions for 15 minutes since last used */
+#endif
+
+/* Misc constants */
+enum {
+    MAX_SERVER_ADDRESS = 128, /* maximum server address length */
+    MAX_SERVER_NAME    = 128, /* maximum server name length */
+    MAX_ERROR_LEN      = 80,  /* maximum error length */
+    ETHER_IF_ADDR_LEN  = 6,   /* ethernet interface address length */
+    LOCAL_IF_ADDR_LEN  = 4,   /* localhost interface address length, !windows */
+    TCP_PROTO          = 6,   /* TCP_PROTOCOL */
+    IP_HDR_SZ          = 20,  /* IP header legnth, min */
+    TCP_HDR_SZ         = 20,  /* TCP header legnth, min */
+    IPV4               = 4,   /* IP version 4 */
+    TCP_PROTOCOL       = 6,   /* TCP Protocol id */
+    TRACE_MSG_SZ       = 80,  /* Trace Message buffer size */
+    HASH_SIZE          = 499, /* Session Hash Table Rows */
+    PSEUDO_HDR_SZ      = 12,  /* TCP Pseudo Header size in bytes */
+    FATAL_ERROR_STATE  =  1,  /* SnifferSession fatal error state */
+    TICKET_HINT_LEN    = 4,   /* Session Ticket Hint length */
+    EXT_TYPE_SZ        = 2,   /* Extension length */
+    MAX_INPUT_SZ       = MAX_RECORD_SIZE + COMP_EXTRA + MAX_MSG_EXTRA +
+                         MTU_EXTRA,  /* Max input sz of reassembly */
+    TICKET_EXT_ID      = 0x23 /* Session Ticket Extension ID */
+};
+
+
+#ifdef _WIN32
+
+static HMODULE dllModule;  /* for error string resources */
+
+BOOL APIENTRY DllMain( HMODULE hModule,
+                       DWORD  ul_reason_for_call,
+                       LPVOID lpReserved
+                     )
+{
+	static int didInit = 0;
+
+    switch (ul_reason_for_call)
+    {
+    case DLL_PROCESS_ATTACH:
+		if (didInit == 0) {
+            dllModule = hModule;
+			ssl_InitSniffer();
+			didInit = 1;
+		}
+        break;
+    case DLL_THREAD_ATTACH:
+        break;
+    case DLL_THREAD_DETACH:
+        break;
+    case DLL_PROCESS_DETACH:
+		if (didInit) {
+			ssl_FreeSniffer();
+			didInit = 0;
+		}
+        break;
+    }
+    return TRUE;
+}
+
+#endif /* _WIN32 */
+
+
+static int TraceOn = 0;         /* Trace is off by default */
+static FILE* TraceFile = 0;
+
+
+/* windows uses .rc table for this */
+#ifndef _WIN32
+
+static const char* const msgTable[] =
+{
+    /* 1 */
+    "Out of Memory",
+    "New SSL Sniffer Server Registered",
+    "Checking IP Header",
+    "SSL Sniffer Server Not Registered",
+    "Checking TCP Header",
+
+    /* 6 */
+    "SSL Sniffer Server Port Not Registered",
+    "RSA Private Decrypt Error",
+    "RSA Private Decode Error",
+    "Set Cipher Spec Error",
+    "Server Hello Input Malformed",
+
+    /* 11 */
+    "Couldn't Resume Session Error",
+    "Server Did Resumption",
+    "Client Hello Input Malformed",
+    "Client Trying to Resume",
+    "Handshake Input Malformed",
+
+    /* 16 */
+    "Got Hello Verify msg",
+    "Got Server Hello msg",
+    "Got Cert Request msg",
+    "Got Server Key Exchange msg",
+    "Got Cert msg",
+
+    /* 21 */
+    "Got Server Hello Done msg",
+    "Got Finished msg",
+    "Got Client Hello msg",
+    "Got Client Key Exchange msg",
+    "Got Cert Verify msg",
+
+    /* 26 */
+    "Got Unknown Handshake msg",
+    "New SSL Sniffer Session created",
+    "Couldn't create new SSL",
+    "Got a Packet to decode",
+    "No data present",
+
+    /* 31 */
+    "Session Not Found",
+    "Got an Old Client Hello msg",
+    "Old Client Hello Input Malformed",
+    "Old Client Hello OK",
+    "Bad Old Client Hello",
+
+    /* 36 */
+    "Bad Record Header",
+    "Record Header Input Malformed",
+    "Got a HandShake msg",
+    "Bad HandShake msg",
+    "Got a Change Cipher Spec msg",
+
+    /* 41 */
+    "Got Application Data msg",
+    "Bad Application Data",
+    "Got an Alert msg",
+    "Another msg to Process",
+    "Removing Session From Table",
+    
+    /* 46 */
+    "Bad Key File",
+    "Wrong IP Version",
+    "Wrong Protocol type",
+    "Packet Short for header processing",
+    "Got Unknown Record Type",
+    
+    /* 51 */
+    "Can't Open Trace File",
+    "Session in Fatal Error State",
+    "Partial SSL record received",
+    "Buffer Error, malformed input",
+    "Added to Partial Input",
+    
+    /* 56 */
+    "Received a Duplicate Packet",
+    "Received an Out of Order Packet",
+    "Received an Overlap Duplicate Packet",
+    "Received an Overlap Reassembly Begin Duplicate Packet",
+    "Received an Overlap Reassembly End Duplicate Packet",
+
+    /* 61 */
+    "Missed the Client Hello Entirely",
+    "Got Hello Request msg",
+    "Got Session Ticket msg",
+    "Bad Input",
+    "Bad Decrypt Type",
+
+    /* 66 */
+    "Bad Finished Message Processing",
+    "Bad Compression Type",
+    "Bad DeriveKeys Error",
+    "Saw ACK for Missing Packet Error",
+    "Bad Decrypt Operation",
+
+    /* 71 */
+    "Decrypt Keys Not Set Up",
+    "Late Key Load Error",
+    "Got Certificate Status msg",
+    "RSA Key Missing Error"
+};
+
+
+/* *nix version uses table above */
+static void GetError(int idx, char* str)
+{
+    XSTRNCPY(str, msgTable[idx - 1], MAX_ERROR_LEN);
+}
+
+
+#else /* _WIN32 */
+
+
+/* Windows version uses .rc table */
+static void GetError(int idx, char* buffer)
+{
+    if (!LoadStringA(dllModule, idx, buffer, MAX_ERROR_LEN))
+        buffer[0] = 0;
+}
+
+
+#endif /* _WIN32 */
+
+
+/* Packet Buffer for reassembly list and ready list */
+typedef struct PacketBuffer {
+    word32  begin;      /* relative sequence begin */
+    word32  end;        /* relative sequence end   */
+    byte*   data;       /* actual data             */
+    struct PacketBuffer* next; /* next on reassembly list or ready list */
+} PacketBuffer;
+
+
+#ifdef HAVE_SNI
+
+/* NamedKey maps a SNI name to a specific private key */
+typedef struct NamedKey {
+    char             name[MAX_SERVER_NAME];      /* server DNS name */
+    word32           nameSz;                     /* size of server DNS name */
+    byte*            key;                        /* DER private key */
+    word32           keySz;                      /* size of DER private key */
+    struct NamedKey* next;                       /* for list */
+} NamedKey;
+
+#endif
+
+
+/* Sniffer Server holds info for each server/port monitored */
+typedef struct SnifferServer {
+    SSL_CTX*       ctx;                          /* SSL context */
+    char           address[MAX_SERVER_ADDRESS];  /* passed in server address */
+    word32         server;                       /* netowrk order address */
+    int            port;                         /* server port */
+#ifdef HAVE_SNI
+    NamedKey*      namedKeys;                    /* mapping of names and keys */
+    wolfSSL_Mutex   namedKeysMutex;               /* mutex for namedKey list */
+#endif
+    struct SnifferServer* next;                  /* for list */
+} SnifferServer;
+
+
+/* Session Flags */
+typedef struct Flags {
+    byte           side;            /* which end is current packet headed */
+    byte           serverCipherOn;  /* indicates whether cipher is active */
+    byte           clientCipherOn;  /* indicates whether cipher is active */
+    byte           resuming;        /* did this session come from resumption */
+    byte           cached;          /* have we cached this session yet */
+    byte           clientHello;     /* processed client hello yet, for SSLv2 */
+    byte           finCount;        /* get both FINs before removing */
+    byte           fatalError;      /* fatal error state */
+} Flags;
+
+
+/* Out of Order FIN caputre */
+typedef struct FinCaputre {
+    word32 cliFinSeq;               /* client relative sequence FIN  0 is no */
+    word32 srvFinSeq;               /* server relative sequence FIN, 0 is no */
+    byte   cliCounted;              /* did we count yet, detects duplicates */
+    byte   srvCounted;              /* did we count yet, detects duplicates */
+} FinCaputre;
+
+
+/* Sniffer Session holds info for each client/server SSL/TLS session */
+typedef struct SnifferSession {
+    SnifferServer* context;         /* server context */
+    SSL*           sslServer;       /* SSL server side decode */
+    SSL*           sslClient;       /* SSL client side decode */
+    word32         server;          /* server address in network byte order */
+    word32         client;          /* client address in network byte order */
+    word16         srvPort;         /* server port */
+    word16         cliPort;         /* client port */
+    word32         cliSeqStart;     /* client start sequence */
+    word32         srvSeqStart;     /* server start sequence */
+    word32         cliExpected;     /* client expected sequence (relative) */
+    word32         srvExpected;     /* server expected sequence (relative) */
+    FinCaputre     finCaputre;      /* retain out of order FIN s */
+    Flags          flags;           /* session flags */
+    time_t         lastUsed;          /* last used ticks */
+    PacketBuffer*  cliReassemblyList; /* client out of order packets */
+    PacketBuffer*  srvReassemblyList; /* server out of order packets */
+    struct SnifferSession* next;      /* for hash table list */
+    byte*          ticketID;          /* mac ID of session ticket */
+} SnifferSession;
+
+
+/* Sniffer Server List and mutex */
+static SnifferServer* ServerList = 0;
+static wolfSSL_Mutex ServerListMutex;
+
+
+/* Session Hash Table, mutex, and count */
+static SnifferSession* SessionTable[HASH_SIZE];
+static wolfSSL_Mutex SessionMutex;
+static int SessionCount = 0;
+
+
+/* Initialize overall Sniffer */
+void ssl_InitSniffer(void)
+{
+    wolfSSL_Init();
+    InitMutex(&ServerListMutex);
+    InitMutex(&SessionMutex);
+}
+
+
+#ifdef HAVE_SNI
+
+/* Free Named Key and the zero out the private key it holds */
+static void FreeNamedKey(NamedKey* in)
+{
+    if (in) {
+        if (in->key) {
+            ForceZero(in->key, in->keySz);
+            free(in->key);
+        }
+        free(in);
+    }
+}
+
+
+static void FreeNamedKeyList(NamedKey* in)
+{
+    NamedKey* next;
+
+    while (in) {
+        next = in->next;
+        FreeNamedKey(in);
+        in = next;
+    }
+}
+
+#endif
+
+
+/* Free Sniffer Server's resources/self */
+static void FreeSnifferServer(SnifferServer* srv)
+{
+    if (srv) {
+#ifdef HAVE_SNI
+        LockMutex(&srv->namedKeysMutex);
+        FreeNamedKeyList(srv->namedKeys);
+        UnLockMutex(&srv->namedKeysMutex);
+        FreeMutex(&srv->namedKeysMutex);
+#endif
+        SSL_CTX_free(srv->ctx);
+    }
+    free(srv);
+}
+
+
+/* free PacketBuffer's resources/self */
+static void FreePacketBuffer(PacketBuffer* del)
+{
+    if (del) {
+        free(del->data);
+        free(del);
+    }
+}
+
+
+/* remove PacketBuffer List */
+static void FreePacketList(PacketBuffer* in)
+{
+    if (in) {
+        PacketBuffer* del;
+        PacketBuffer* packet = in;
+        
+        while (packet) {
+            del = packet;
+            packet = packet->next;
+            FreePacketBuffer(del);
+        }
+    }
+}
+
+
+/* Free Sniffer Session's resources/self */
+static void FreeSnifferSession(SnifferSession* session)
+{
+    if (session) {
+        SSL_free(session->sslClient);
+        SSL_free(session->sslServer);
+        
+        FreePacketList(session->cliReassemblyList);
+        FreePacketList(session->srvReassemblyList);
+
+        free(session->ticketID);
+    }
+    free(session);
+}
+
+
+/* Free overall Sniffer */
+void ssl_FreeSniffer(void)
+{
+    SnifferServer*  srv;
+    SnifferServer*  removeServer;
+    SnifferSession* session;
+    SnifferSession* removeSession;
+    int i;
+
+    LockMutex(&ServerListMutex);
+    LockMutex(&SessionMutex);
+    
+    srv = ServerList;
+    while (srv) {
+        removeServer = srv;
+        srv = srv->next;
+        FreeSnifferServer(removeServer);
+    }
+
+    for (i = 0; i < HASH_SIZE; i++) {
+        session = SessionTable[i];
+        while (session) {
+            removeSession = session;
+            session = session->next;
+            FreeSnifferSession(removeSession);
+        }
+    }
+
+    UnLockMutex(&SessionMutex);
+    UnLockMutex(&ServerListMutex);
+
+    FreeMutex(&SessionMutex);
+    FreeMutex(&ServerListMutex);
+
+    if (TraceFile) {
+        TraceOn = 0;
+        fclose(TraceFile);
+        TraceFile = NULL;
+    }
+
+    wolfSSL_Cleanup();
+}
+
+
+/* Initialize a SnifferServer */
+static void InitSnifferServer(SnifferServer* sniffer)
+{
+    sniffer->ctx = 0;
+    XMEMSET(sniffer->address, 0, MAX_SERVER_ADDRESS);
+    sniffer->server   = 0;
+    sniffer->port     = 0;
+#ifdef HAVE_SNI
+    sniffer->namedKeys = 0;
+    InitMutex(&sniffer->namedKeysMutex);
+#endif
+    sniffer->next     = 0;
+}
+
+
+/* Initialize session flags */
+static void InitFlags(Flags* flags)
+{
+    flags->side           = 0;
+    flags->serverCipherOn = 0;
+    flags->clientCipherOn = 0;
+    flags->resuming       = 0;
+    flags->cached         = 0;
+    flags->clientHello    = 0;
+    flags->finCount       = 0;
+    flags->fatalError     = 0;
+}
+
+
+/* Initialize FIN Capture */
+static void InitFinCapture(FinCaputre* cap)
+{
+    cap->cliFinSeq  = 0;
+    cap->srvFinSeq  = 0;
+    cap->cliCounted = 0;
+    cap->srvCounted = 0;
+}
+
+
+/* Initialize a Sniffer Session */
+static void InitSession(SnifferSession* session)
+{
+    session->context        = 0;
+    session->sslServer      = 0;
+    session->sslClient      = 0;
+    session->server         = 0;
+    session->client         = 0;
+    session->srvPort        = 0;
+    session->cliPort        = 0;
+    session->cliSeqStart    = 0;
+    session->srvSeqStart    = 0;
+    session->cliExpected    = 0;
+    session->srvExpected    = 0;
+    session->lastUsed       = 0;
+    session->cliReassemblyList = 0;
+    session->srvReassemblyList = 0;
+    session->next           = 0;
+    session->ticketID       = 0;
+    
+    InitFlags(&session->flags);
+    InitFinCapture(&session->finCaputre);
+}
+
+
+/* IP Info from IP Header */
+typedef struct IpInfo {
+    int    length;        /* length of this header */
+    int    total;         /* total length of fragment */
+    word32 src;           /* network order source address */
+    word32 dst;           /* network order destination address */
+} IpInfo;
+
+
+/* TCP Info from TCP Header */
+typedef struct TcpInfo {
+    int    srcPort;       /* source port */
+    int    dstPort;       /* source port */
+    int    length;        /* length of this header */
+    word32 sequence;      /* sequence number */
+    word32 ackNumber;     /* ack number */
+    byte   fin;           /* FIN set */
+    byte   rst;           /* RST set */
+    byte   syn;           /* SYN set */
+    byte   ack;           /* ACK set */
+} TcpInfo;
+
+
+/* Tcp Pseudo Header for Checksum calculation */
+typedef struct TcpPseudoHdr {
+    word32  src;        /* source address */
+    word32  dst;        /* destination address */
+    byte    rsv;        /* reserved, always 0 */
+    byte    protocol;   /* IP protocol */
+    word16  legnth;     /* tcp header length + data length (doesn't include */
+                        /* pseudo header length) network order */
+} TcpPseudoHdr;
+
+
+/* Password Setting Callback */
+static int SetPassword(char* passwd, int sz, int rw, void* userdata)
+{
+    (void)rw;
+    XSTRNCPY(passwd, (const char*)userdata, sz);
+    return (int)XSTRLEN((const char*)userdata);
+}
+
+
+/* Ethernet Header */
+typedef struct EthernetHdr {
+    byte   dst[ETHER_IF_ADDR_LEN];    /* destination host address */ 
+    byte   src[ETHER_IF_ADDR_LEN];    /* source  host address */ 
+    word16 type;                      /* IP, ARP, etc */ 
+} EthernetHdr;
+
+
+/* IP Header */
+typedef struct IpHdr {
+    byte    ver_hl;              /* version/header length */
+    byte    tos;                 /* type of service */
+    word16  length;              /* total length */
+    word16  id;                  /* identification */
+    word16  offset;              /* fragment offset field */
+    byte    ttl;                 /* time to live */
+    byte    protocol;            /* protocol */
+    word16  sum;                 /* checksum */
+    word32  src;                 /* source address */
+    word32  dst;                 /* destination address */
+} IpHdr;
+
+
+#define IP_HL(ip)      ( (((ip)->ver_hl) & 0x0f) * 4)
+#define IP_V(ip)       ( ((ip)->ver_hl) >> 4)
+
+/* TCP Header */
+typedef struct TcpHdr {
+    word16  srcPort;            /* source port */
+    word16  dstPort;            /* destination port */
+    word32  sequence;           /* sequence number */ 
+    word32  ack;                /* acknoledgment number */ 
+    byte    offset;             /* data offset, reserved */
+    byte    flags;              /* option flags */
+    word16  window;             /* window */
+    word16  sum;                /* checksum */
+    word16  urgent;             /* urgent pointer */
+} TcpHdr;
+
+#define TCP_LEN(tcp)  ( (((tcp)->offset & 0xf0) >> 4) * 4)
+#define TCP_FIN 0x01
+#define TCP_SYN 0x02
+#define TCP_RST 0x04
+#define TCP_ACK 0x10
+
+
+
+
+
+/* Use platform specific GetError to write to tracfile if tracing */ 
+static void Trace(int idx) 
+{
+    if (TraceOn) {
+        char myBuffer[MAX_ERROR_LEN];
+        GetError(idx, myBuffer);
+        fprintf(TraceFile, "\t%s\n", myBuffer);
+#ifdef DEBUG_SNIFFER
+        fprintf(stderr,    "\t%s\n", myBuffer);
+#endif
+    }
+}
+
+
+/* Show TimeStamp for beginning of packet Trace */
+static void TraceHeader(void)
+{
+    if (TraceOn) {
+        time_t ticks = time(NULL);
+        fprintf(TraceFile, "\n%s", ctime(&ticks));
+    }
+}
+
+
+/* Show Set Server info for Trace */
+static void TraceSetServer(const char* srv, int port, const char* keyFile)
+{
+    if (TraceOn) {
+        fprintf(TraceFile, "\tTrying to install a new Sniffer Server with\n");
+        fprintf(TraceFile, "\tserver: %s, port: %d, keyFile: %s\n", srv, port,
+                                                                    keyFile);
+    }
+}
+
+
+#ifdef HAVE_SNI
+
+/* Show Set Named Server info for Trace */
+static void TraceSetNamedServer(const char* name,
+                                 const char* srv, int port, const char* keyFile)
+{
+    if (TraceOn) {
+        fprintf(TraceFile, "\tTrying to install a new Sniffer Server with\n");
+        fprintf(TraceFile, "\tname: %s, server: %s, port: %d, keyFile: %s\n",
+                                                      name, srv, port, keyFile);
+    }
+}
+
+#endif
+
+
+/* Trace got packet number */
+static void TracePacket(void)
+{
+    if (TraceOn) {
+        static word32 packetNumber = 0;
+        fprintf(TraceFile, "\tGot a Packet to decode, packet %u\n",
+                ++packetNumber);
+    }
+}
+
+
+/* Convert network byte order address into human readable */
+static char* IpToS(word32 addr, char* str)
+{
+    byte* p = (byte*)&addr;
+    
+    SNPRINTF(str, TRACE_MSG_SZ, "%d.%d.%d.%d", p[0], p[1], p[2], p[3]);
+    
+    return str;
+}
+
+
+/* Show destination and source address from Ip Hdr for packet Trace */
+static void TraceIP(IpHdr* iphdr)
+{
+    if (TraceOn) {
+        char src[TRACE_MSG_SZ];
+        char dst[TRACE_MSG_SZ];
+        fprintf(TraceFile, "\tdst:%s src:%s\n", IpToS(iphdr->dst, dst),
+                IpToS(iphdr->src, src));
+    }
+}
+
+
+/* Show destination and source port from Tcp Hdr for packet Trace */
+static void TraceTcp(TcpHdr* tcphdr)
+{
+    if (TraceOn) {
+        fprintf(TraceFile, "\tdstPort:%u srcPort:%u\n", ntohs(tcphdr->dstPort),
+                ntohs(tcphdr->srcPort));
+    }
+}
+
+
+/* Show sequence and payload length for Trace */
+static void TraceSequence(word32 seq, int len)
+{
+    if (TraceOn) {
+        fprintf(TraceFile, "\tSequence:%u, payload length:%d\n", seq, len);
+    }
+}
+
+
+/* Show sequence and payload length for Trace */
+static void TraceAck(word32 ack, word32 expected)
+{
+    if (TraceOn) {
+        fprintf(TraceFile, "\tAck:%u Expected:%u\n", ack, expected);
+    }
+}
+
+
+/* Show relative expected and relative received sequences */
+static void TraceRelativeSequence(word32 expected, word32 got)
+{
+    if (TraceOn) {
+        fprintf(TraceFile, "\tExpected sequence:%u, received sequence:%u\n",
+                expected, got);
+    }
+}
+
+
+/* Show server sequence startup from SYN */
+static void TraceServerSyn(word32 seq)
+{
+    if (TraceOn) {
+        fprintf(TraceFile, "\tServer SYN, Sequence Start:%u\n", seq);
+    }
+}
+
+
+/* Show client sequence startup from SYN */
+static void TraceClientSyn(word32 seq)
+{
+    if (TraceOn) {
+        fprintf(TraceFile, "\tClient SYN, Sequence Start:%u\n", seq);
+    }
+}
+
+
+/* Show client FIN capture */
+static void TraceClientFin(word32 finSeq, word32 relSeq)
+{
+    if (TraceOn) {
+        fprintf(TraceFile, "\tClient FIN capture:%u, current SEQ:%u\n",
+                finSeq, relSeq);
+    }
+}
+
+
+/* Show server FIN capture */
+static void TraceServerFin(word32 finSeq, word32 relSeq)
+{
+    if (TraceOn) {
+        fprintf(TraceFile, "\tServer FIN capture:%u, current SEQ:%u\n",
+                finSeq, relSeq);
+    }
+}
+
+
+/* Show number of SSL data bytes decoded, could be 0 (ok) */
+static void TraceGotData(int bytes)
+{
+    if (TraceOn) {
+        fprintf(TraceFile, "\t%d bytes of SSL App data processed\n", bytes);
+    }
+}
+
+
+/* Show bytes added to old SSL App data */
+static void TraceAddedData(int newBytes, int existingBytes)
+{
+    if (TraceOn) {
+        fprintf(TraceFile,
+                "\t%d bytes added to %d exisiting bytes in User Buffer\n",
+                newBytes, existingBytes);
+    }
+}
+
+
+/* Show Stale Session */
+static void TraceStaleSession(void)
+{
+    if (TraceOn) {
+        fprintf(TraceFile, "\tFound a stale session\n");
+    }
+}
+
+
+/* Show Finding Stale Sessions */
+static void TraceFindingStale(void)
+{
+    if (TraceOn) {
+        fprintf(TraceFile, "\tTrying to find Stale Sessions\n");
+    }
+}
+
+
+/* Show Removed Session */
+static void TraceRemovedSession(void)
+{
+    if (TraceOn) {
+        fprintf(TraceFile, "\tRemoved it\n");
+    }
+}
+
+
+/* Set user error string */
+static void SetError(int idx, char* error, SnifferSession* session, int fatal)
+{
+    GetError(idx, error);
+    Trace(idx);
+    if (session && fatal == FATAL_ERROR_STATE)
+        session->flags.fatalError = 1;
+}
+
+
+/* See if this IPV4 network order address has been registered */
+/* return 1 is true, 0 is false */
+static int IsServerRegistered(word32 addr)
+{
+    int ret = 0;     /* false */
+    SnifferServer* sniffer;
+
+    LockMutex(&ServerListMutex);
+    
+    sniffer = ServerList;
+    while (sniffer) {
+        if (sniffer->server == addr) {
+            ret = 1;
+            break;
+        }
+        sniffer = sniffer->next;
+    }
+    
+    UnLockMutex(&ServerListMutex);
+
+    return ret;
+}
+
+
+/* See if this port has been registered to watch */
+/* return 1 is true, 0 is false */
+static int IsPortRegistered(word32 port)
+{
+    int ret = 0;    /* false */
+    SnifferServer* sniffer;
+    
+    LockMutex(&ServerListMutex);
+    
+    sniffer = ServerList;
+    while (sniffer) {
+        if (sniffer->port == (int)port) {
+            ret = 1; 
+            break;
+        }
+        sniffer = sniffer->next;
+    }
+    
+    UnLockMutex(&ServerListMutex);
+
+    return ret;
+}
+
+
+/* Get SnifferServer from IP and Port */
+static SnifferServer* GetSnifferServer(IpInfo* ipInfo, TcpInfo* tcpInfo)
+{
+    SnifferServer* sniffer;
+    
+    LockMutex(&ServerListMutex);
+    
+    sniffer = ServerList;
+    while (sniffer) {
+        if (sniffer->port == tcpInfo->srcPort && sniffer->server == ipInfo->src)
+            break;
+        if (sniffer->port == tcpInfo->dstPort && sniffer->server == ipInfo->dst)
+            break;
+        sniffer = sniffer->next;
+    }
+    
+    UnLockMutex(&ServerListMutex);
+    
+    return sniffer;
+}
+
+
+/* Hash the Session Info, return hash row */
+static word32 SessionHash(IpInfo* ipInfo, TcpInfo* tcpInfo)
+{
+    word32 hash = ipInfo->src * ipInfo->dst;
+    hash *= tcpInfo->srcPort * tcpInfo->dstPort;
+    
+    return hash % HASH_SIZE;
+}
+
+
+/* Get Exisiting SnifferSession from IP and Port */
+static SnifferSession* GetSnifferSession(IpInfo* ipInfo, TcpInfo* tcpInfo)
+{
+    SnifferSession* session;
+    time_t          currTime = time(NULL); 
+    word32          row = SessionHash(ipInfo, tcpInfo);
+
+    assert(row <= HASH_SIZE);
+    
+    LockMutex(&SessionMutex);
+    
+    session = SessionTable[row];
+    while (session) {
+        if (session->server == ipInfo->src && session->client == ipInfo->dst &&
+                    session->srvPort == tcpInfo->srcPort &&
+                    session->cliPort == tcpInfo->dstPort)
+            break;
+        if (session->client == ipInfo->src && session->server == ipInfo->dst &&
+                    session->cliPort == tcpInfo->srcPort &&
+                    session->srvPort == tcpInfo->dstPort)
+            break;
+        
+        session = session->next;
+    }
+
+    if (session)
+        session->lastUsed= currTime; /* keep session alive, remove stale will */
+                                     /* leave alone */   
+    UnLockMutex(&SessionMutex);
+    
+    /* determine side */
+    if (session) {
+        if (ipInfo->dst == session->context->server &&
+            tcpInfo->dstPort == session->context->port)
+            session->flags.side = WOLFSSL_SERVER_END;
+        else
+            session->flags.side = WOLFSSL_CLIENT_END;
+    }    
+    
+    return session;
+}
+
+
+#ifdef HAVE_SNI
+
+static int LoadKeyFile(byte** keyBuf, word32* keyBufSz,
+                const char* keyFile, int typeKey,
+                const char* password)
+{
+    byte* loadBuf;
+    byte* saveBuf;
+    long fileSz = 0;
+    int saveBufSz;
+    XFILE file;
+    int ret;
+
+    if (keyBuf == NULL || keyBufSz == NULL || keyFile == NULL) {
+        return -1;
+    }
+
+    file = XFOPEN(keyFile, "rb");
+    if (file == XBADFILE) return -1;
+    XFSEEK(file, 0, XSEEK_END);
+    fileSz = XFTELL(file);
+    XREWIND(file);
+
+    loadBuf = (byte*)malloc(fileSz);
+    if (loadBuf == NULL) {
+        XFCLOSE(file);
+        return -1;
+    }
+
+    ret = (int)XFREAD(loadBuf, fileSz, 1, file);
+    XFCLOSE(file);
+
+    if (typeKey == SSL_FILETYPE_PEM) {
+        saveBuf = (byte*)malloc(fileSz);
+
+        saveBufSz = wolfSSL_KeyPemToDer(loadBuf, (int)fileSz,
+                                                saveBuf, (int)fileSz, password);
+        free(loadBuf);
+
+        *keyBuf = saveBuf;
+        *keyBufSz = (word32)saveBufSz;
+    }
+    else {
+        *keyBuf = loadBuf;
+        *keyBufSz = (word32)fileSz;
+    }
+
+
+    if (ret < 0) {
+        return -1;
+    }
+
+    return ret;
+}
+
+#endif
+
+
+static int SetNamedPrivateKey(const char* name, const char* address, int port,
+            const char* keyFile, int typeKey, const char* password, char* error)
+{
+    SnifferServer* sniffer;
+    int            ret;
+    int            type = (typeKey == FILETYPE_PEM) ? SSL_FILETYPE_PEM :
+                                                      SSL_FILETYPE_ASN1;
+    int            isNew = 0;
+    word32         serverIp;
+
+#ifdef HAVE_SNI
+    NamedKey* namedKey = NULL;
+#endif
+
+    (void)name;
+#ifdef HAVE_SNI
+    if (name != NULL) {
+        namedKey = (NamedKey*)malloc(sizeof(NamedKey));
+        if (namedKey == NULL) {
+            SetError(MEMORY_STR, error, NULL, 0);
+            return -1;
+        }
+        XMEMSET(namedKey, 0, sizeof(NamedKey));
+
+        namedKey->nameSz = (word32)XSTRLEN(name);
+        XSTRNCPY(namedKey->name, name, sizeof(namedKey->name));
+        if (namedKey->nameSz >= sizeof(namedKey->name)) {
+            namedKey->nameSz = sizeof(namedKey->name) - 1;
+            namedKey->name[namedKey->nameSz] = '\0';
+        }
+
+        ret = LoadKeyFile(&namedKey->key, &namedKey->keySz,
+                          keyFile, type, password);
+        if (ret < 0) {
+            SetError(KEY_FILE_STR, error, NULL, 0);
+            FreeNamedKey(namedKey);
+            return -1;
+        }
+    }
+#endif
+
+    serverIp = inet_addr(address);
+    sniffer = ServerList;
+    while (sniffer != NULL &&
+           (sniffer->server != serverIp || sniffer->port != port)) {
+        sniffer = sniffer->next;
+    }
+
+    if (sniffer == NULL) {
+        isNew = 1;
+        sniffer = (SnifferServer*)malloc(sizeof(SnifferServer));
+        if (sniffer == NULL) {
+            SetError(MEMORY_STR, error, NULL, 0);
+#ifdef HAVE_SNI
+            FreeNamedKey(namedKey);
+#endif
+            return -1;
+        }
+        InitSnifferServer(sniffer);
+
+        XSTRNCPY(sniffer->address, address, MAX_SERVER_ADDRESS-1);
+        sniffer->address[MAX_SERVER_ADDRESS-1] = '\0';
+        sniffer->server = serverIp;
+        sniffer->port = port;
+
+        sniffer->ctx = SSL_CTX_new(SSLv3_client_method());
+        if (!sniffer->ctx) {
+            SetError(MEMORY_STR, error, NULL, 0);
+#ifdef HAVE_SNI
+            FreeNamedKey(namedKey);
+#endif
+            FreeSnifferServer(sniffer);
+            return -1;
+        }
+    }
+
+    if (name == NULL) {
+        if (password) {
+            SSL_CTX_set_default_passwd_cb(sniffer->ctx, SetPassword);
+            SSL_CTX_set_default_passwd_cb_userdata(
+                                                 sniffer->ctx, (void*)password);
+        }
+        ret = SSL_CTX_use_PrivateKey_file(sniffer->ctx, keyFile, type);
+        if (ret != SSL_SUCCESS) {
+            SetError(KEY_FILE_STR, error, NULL, 0);
+            if (isNew)
+                FreeSnifferServer(sniffer);
+            return -1;
+        }
+    }
+#ifdef HAVE_SNI
+    else {
+        LockMutex(&sniffer->namedKeysMutex);
+        namedKey->next = sniffer->namedKeys;
+        sniffer->namedKeys = namedKey;
+        UnLockMutex(&sniffer->namedKeysMutex);
+    }
+#endif
+
+    if (isNew) {
+        sniffer->next = ServerList;
+        ServerList = sniffer;
+    }
+
+    return 0;
+}
+
+
+#ifdef HAVE_SNI
+
+/* Sets the private key for a specific name, server and port  */
+/* returns 0 on success, -1 on error */
+int ssl_SetNamedPrivateKey(const char* name,
+                           const char* address, int port,
+                           const char* keyFile, int typeKey,
+                           const char* password, char* error)
+{
+    int ret;
+
+    TraceHeader();
+    TraceSetNamedServer(name, address, port, keyFile);
+
+    LockMutex(&ServerListMutex);
+    ret = SetNamedPrivateKey(name, address, port, keyFile,
+                             typeKey, password, error);
+    UnLockMutex(&ServerListMutex);
+
+    if (ret == 0)
+        Trace(NEW_SERVER_STR);
+
+    return ret;
+}
+
+#endif
+
+
+/* Sets the private key for a specific server and port  */
+/* returns 0 on success, -1 on error */
+int ssl_SetPrivateKey(const char* address, int port, const char* keyFile,
+                      int typeKey, const char* password, char* error)
+{
+    int ret;
+
+    TraceHeader();
+    TraceSetServer(address, port, keyFile);
+
+    LockMutex(&ServerListMutex);
+    ret = SetNamedPrivateKey(NULL, address, port, keyFile,
+                             typeKey, password, error);
+    UnLockMutex(&ServerListMutex);
+
+    if (ret == 0)
+        Trace(NEW_SERVER_STR);
+
+    return ret;
+}
+
+
+/* Check IP Header for IPV4, TCP, and a registered server address */
+/* returns 0 on success, -1 on error */
+static int CheckIpHdr(IpHdr* iphdr, IpInfo* info, int length, char* error)
+{
+    int    version = IP_V(iphdr);
+
+    TraceIP(iphdr);
+    Trace(IP_CHECK_STR);
+
+    if (version != IPV4) {
+        SetError(BAD_IPVER_STR, error, NULL, 0); 
+        return -1;
+    }
+
+    if (iphdr->protocol != TCP_PROTOCOL) { 
+        SetError(BAD_PROTO_STR, error, NULL, 0);
+        return -1;
+    }
+
+    if (!IsServerRegistered(iphdr->src) && !IsServerRegistered(iphdr->dst)) {
+        SetError(SERVER_NOT_REG_STR, error, NULL, 0);
+        return -1;
+    }
+
+    info->length  = IP_HL(iphdr);
+    info->total   = ntohs(iphdr->length);
+    info->src     = iphdr->src;
+    info->dst     = iphdr->dst;
+
+    if (info->total == 0)
+        info->total = length;  /* reassembled may be off */
+
+    return 0;
+}
+
+
+/* Check TCP Header for a registered port */
+/* returns 0 on success, -1 on error */
+static int CheckTcpHdr(TcpHdr* tcphdr, TcpInfo* info, char* error)
+{
+    TraceTcp(tcphdr);
+    Trace(TCP_CHECK_STR);
+    info->srcPort   = ntohs(tcphdr->srcPort);
+    info->dstPort   = ntohs(tcphdr->dstPort);
+    info->length    = TCP_LEN(tcphdr);
+    info->sequence  = ntohl(tcphdr->sequence);
+    info->fin       = tcphdr->flags & TCP_FIN;
+    info->rst       = tcphdr->flags & TCP_RST;
+    info->syn       = tcphdr->flags & TCP_SYN;
+    info->ack       = tcphdr->flags & TCP_ACK;
+    if (info->ack)
+        info->ackNumber = ntohl(tcphdr->ack); 
+
+    if (!IsPortRegistered(info->srcPort) && !IsPortRegistered(info->dstPort)) {
+        SetError(SERVER_PORT_NOT_REG_STR, error, NULL, 0);
+        return -1;
+    }
+
+    return 0;
+}
+
+
+/* Decode Record Layer Header */
+static int GetRecordHeader(const byte* input, RecordLayerHeader* rh, int* size)
+{
+    XMEMCPY(rh, input, RECORD_HEADER_SZ);
+    *size = (rh->length[0] << 8) | rh->length[1];
+
+    if (*size > (MAX_RECORD_SIZE + COMP_EXTRA + MAX_MSG_EXTRA))
+        return LENGTH_ERROR;
+
+    return 0;
+}
+
+
+/* Process Client Key Exchange, RSA only */
+static int ProcessClientKeyExchange(const byte* input, int* sslBytes,
+                                    SnifferSession* session, char* error)
+{
+    word32 idx = 0;
+    RsaKey key;
+    int    ret;
+
+    if (session->sslServer->buffers.key.buffer == NULL ||
+        session->sslServer->buffers.key.length == 0) {
+
+        SetError(RSA_KEY_MISSING_STR, error, session, FATAL_ERROR_STATE);
+        return -1;
+    }
+    ret = wc_InitRsaKey(&key, 0);
+    if (ret == 0)
+        ret = wc_RsaPrivateKeyDecode(session->sslServer->buffers.key.buffer,
+                          &idx, &key, session->sslServer->buffers.key.length);
+    if (ret == 0) {
+        int length = wc_RsaEncryptSize(&key);
+
+        if (IsTLS(session->sslServer))
+            input += 2;     /* tls pre length */
+
+        if (length > *sslBytes) {
+            SetError(PARTIAL_INPUT_STR, error, session, FATAL_ERROR_STATE);
+            wc_FreeRsaKey(&key);
+            return -1;
+        }
+        ret = wc_RsaPrivateDecrypt(input, length,
+                  session->sslServer->arrays->preMasterSecret,SECRET_LEN, &key);
+
+        if (ret != SECRET_LEN) {
+            SetError(RSA_DECRYPT_STR, error, session, FATAL_ERROR_STATE);
+            wc_FreeRsaKey(&key);
+            return -1;
+        }
+        ret = 0;  /* not in error state */
+        session->sslServer->arrays->preMasterSz = SECRET_LEN;
+
+        /* store for client side as well */
+        XMEMCPY(session->sslClient->arrays->preMasterSecret,
+               session->sslServer->arrays->preMasterSecret, SECRET_LEN);
+        session->sslClient->arrays->preMasterSz = SECRET_LEN;
+
+        #ifdef SHOW_SECRETS
+        {
+            int i;
+            printf("pre master secret: ");
+            for (i = 0; i < SECRET_LEN; i++)
+                printf("%02x", session->sslServer->arrays->preMasterSecret[i]);
+            printf("\n");
+        }
+        #endif
+    }
+    else {
+        SetError(RSA_DECODE_STR, error, session, FATAL_ERROR_STATE);
+        wc_FreeRsaKey(&key);
+        return -1;
+    }
+
+    if (SetCipherSpecs(session->sslServer) != 0) {
+        SetError(BAD_CIPHER_SPEC_STR, error, session, FATAL_ERROR_STATE);
+        wc_FreeRsaKey(&key);
+        return -1;
+    }
+
+    if (SetCipherSpecs(session->sslClient) != 0) {
+        SetError(BAD_CIPHER_SPEC_STR, error, session, FATAL_ERROR_STATE);
+        wc_FreeRsaKey(&key);
+        return -1;
+    }
+
+    ret  = MakeMasterSecret(session->sslServer);
+    ret += MakeMasterSecret(session->sslClient);
+    ret += SetKeysSide(session->sslServer, ENCRYPT_AND_DECRYPT_SIDE);
+    ret += SetKeysSide(session->sslClient, ENCRYPT_AND_DECRYPT_SIDE);
+
+    if (ret != 0) {
+        SetError(BAD_DERIVE_STR, error, session, FATAL_ERROR_STATE);
+        return -1;
+    }
+
+#ifdef SHOW_SECRETS
+    {
+        int i;
+        printf("server master secret: ");
+        for (i = 0; i < SECRET_LEN; i++)
+            printf("%02x", session->sslServer->arrays->masterSecret[i]);
+        printf("\n");
+
+        printf("client master secret: ");
+        for (i = 0; i < SECRET_LEN; i++)
+            printf("%02x", session->sslClient->arrays->masterSecret[i]);
+        printf("\n");
+
+        printf("server suite = %d\n", session->sslServer->options.cipherSuite);
+        printf("client suite = %d\n", session->sslClient->options.cipherSuite);
+    }
+#endif
+
+    wc_FreeRsaKey(&key);
+    return ret;
+}
+
+
+/* Process Session Ticket */
+static int ProcessSessionTicket(const byte* input, int* sslBytes,
+                                SnifferSession* session, char* error)
+{
+    word16 len;
+
+    /* make sure can read through hint and len */
+    if (TICKET_HINT_LEN + LENGTH_SZ > *sslBytes) {
+        SetError(BAD_INPUT_STR, error, session, FATAL_ERROR_STATE);
+        return -1;
+    }
+
+    input     += TICKET_HINT_LEN;  /* skip over hint */
+    *sslBytes -= TICKET_HINT_LEN;
+
+    len = (word16)((input[0] << 8) | input[1]);
+    input     += LENGTH_SZ;
+    *sslBytes -= LENGTH_SZ;
+
+    /* make sure can read through ticket */
+    if (len > *sslBytes || len < ID_LEN) {
+        SetError(BAD_INPUT_STR, error, session, FATAL_ERROR_STATE);
+        return -1;
+    }
+
+    /* store session with macID as sessionID */
+    session->sslServer->options.haveSessionId = 1;
+    XMEMCPY(session->sslServer->arrays->sessionID, input + len - ID_LEN,ID_LEN);
+
+    return 0;
+}
+
+
+/* Process Server Hello */
+static int ProcessServerHello(const byte* input, int* sslBytes,
+                              SnifferSession* session, char* error)
+{
+    ProtocolVersion pv;
+    byte            b;
+    int             toRead = VERSION_SZ + RAN_LEN + ENUM_LEN;
+    int             doResume     = 0;
+
+    /* make sure we didn't miss ClientHello */
+    if (session->flags.clientHello == 0) {
+        SetError(MISSED_CLIENT_HELLO_STR, error, session, FATAL_ERROR_STATE);
+        return -1;
+    }
+
+    /* make sure can read through session len */
+    if (toRead > *sslBytes) {
+        SetError(SERVER_HELLO_INPUT_STR, error, session, FATAL_ERROR_STATE);
+        return -1;
+    }
+
+    XMEMCPY(&pv, input, VERSION_SZ);
+    input     += VERSION_SZ;
+    *sslBytes -= VERSION_SZ;
+
+    session->sslServer->version = pv;
+    session->sslClient->version = pv;
+
+    XMEMCPY(session->sslServer->arrays->serverRandom, input, RAN_LEN);
+    XMEMCPY(session->sslClient->arrays->serverRandom, input, RAN_LEN);
+    input    += RAN_LEN;
+    *sslBytes -= RAN_LEN;
+
+    b = *input++;
+    *sslBytes -= 1;
+
+    /* make sure can read through compression */
+    if ( (b + SUITE_LEN + ENUM_LEN) > *sslBytes) {
+        SetError(SERVER_HELLO_INPUT_STR, error, session, FATAL_ERROR_STATE);
+        return -1;
+    }
+    if (b) {
+        XMEMCPY(session->sslServer->arrays->sessionID, input, ID_LEN);
+        session->sslServer->options.haveSessionId = 1;
+    }
+    input     += b;
+    *sslBytes -= b;
+
+    /* cipher suite */
+    b = *input++;  /* first byte, ECC or not */
+    session->sslServer->options.cipherSuite0 = b;
+    session->sslClient->options.cipherSuite0 = b;
+    b = *input++;
+    session->sslServer->options.cipherSuite = b;
+    session->sslClient->options.cipherSuite = b;
+    *sslBytes -= SUITE_LEN;
+
+    /* compression */
+    b = *input++;
+    *sslBytes -= ENUM_LEN;
+
+    if (b) {
+        SetError(BAD_COMPRESSION_STR, error, session, FATAL_ERROR_STATE);
+        return -1;
+    }
+
+    if (session->sslServer->options.haveSessionId &&
+            XMEMCMP(session->sslServer->arrays->sessionID,
+                    session->sslClient->arrays->sessionID, ID_LEN) == 0)
+        doResume = 1;
+    else if (session->sslClient->options.haveSessionId == 0 &&
+             session->sslServer->options.haveSessionId == 0 &&
+             session->ticketID)
+        doResume = 1;
+
+    if (session->ticketID && doResume) {
+        /* use ticketID to retrieve from session, prefer over sessionID */
+        XMEMCPY(session->sslServer->arrays->sessionID,session->ticketID,ID_LEN);
+        session->sslServer->options.haveSessionId = 1;  /* may not have
+                                                           actual sessionID */
+    }
+
+    if (doResume ) {
+        int ret = 0;
+        SSL_SESSION* resume = GetSession(session->sslServer,
+                                      session->sslServer->arrays->masterSecret);
+        if (resume == NULL) {
+            SetError(BAD_SESSION_RESUME_STR, error, session, FATAL_ERROR_STATE);
+            return -1;
+        }
+        /* make sure client has master secret too */
+        XMEMCPY(session->sslClient->arrays->masterSecret,
+               session->sslServer->arrays->masterSecret, SECRET_LEN);
+        session->flags.resuming = 1;
+
+        Trace(SERVER_DID_RESUMPTION_STR);
+        if (SetCipherSpecs(session->sslServer) != 0) {
+            SetError(BAD_CIPHER_SPEC_STR, error, session, FATAL_ERROR_STATE);
+            return -1;
+        }
+
+        if (SetCipherSpecs(session->sslClient) != 0) {
+            SetError(BAD_CIPHER_SPEC_STR, error, session, FATAL_ERROR_STATE);
+            return -1;
+        }
+
+        if (session->sslServer->options.tls) {
+            ret =  DeriveTlsKeys(session->sslServer);
+            ret += DeriveTlsKeys(session->sslClient);
+        }
+        else {
+            ret =  DeriveKeys(session->sslServer);
+            ret += DeriveKeys(session->sslClient);
+        }
+        ret += SetKeysSide(session->sslServer, ENCRYPT_AND_DECRYPT_SIDE);
+        ret += SetKeysSide(session->sslClient, ENCRYPT_AND_DECRYPT_SIDE);
+
+        if (ret != 0) {
+            SetError(BAD_DERIVE_STR, error, session, FATAL_ERROR_STATE);
+            return -1;
+        }
+    }
+#ifdef SHOW_SECRETS
+    {
+        int i;
+        printf("cipher suite = 0x%02x\n",
+               session->sslServer->options.cipherSuite);
+        printf("server random: ");
+        for (i = 0; i < RAN_LEN; i++)
+            printf("%02x", session->sslServer->arrays->serverRandom[i]);
+        printf("\n");
+    }
+#endif
+    return 0;
+}
+
+
+/* Process normal Client Hello */
+static int ProcessClientHello(const byte* input, int* sslBytes,
+                              SnifferSession* session, char* error)
+{
+    byte   bLen;
+    word16 len;
+    int    toRead = VERSION_SZ + RAN_LEN + ENUM_LEN;
+
+#ifdef HAVE_SNI
+    {
+        byte name[MAX_SERVER_NAME];
+        word32 nameSz = sizeof(name);
+        int ret;
+
+        ret = wolfSSL_SNI_GetFromBuffer(
+                             input - HANDSHAKE_HEADER_SZ - RECORD_HEADER_SZ,
+                             *sslBytes + HANDSHAKE_HEADER_SZ + RECORD_HEADER_SZ,
+                             WOLFSSL_SNI_HOST_NAME, name, &nameSz);
+
+        if (ret == SSL_SUCCESS) {
+            NamedKey* namedKey;
+
+            if (nameSz >= sizeof(name))
+                nameSz = sizeof(name) - 1;
+            name[nameSz] = 0;
+            LockMutex(&session->context->namedKeysMutex);
+            namedKey = session->context->namedKeys;
+            while (namedKey != NULL) {
+                if (nameSz == namedKey->nameSz &&
+                           XSTRNCMP((char*)name, namedKey->name, nameSz) == 0) {
+                    if (wolfSSL_use_PrivateKey_buffer(session->sslServer,
+                                            namedKey->key, namedKey->keySz,
+                                            SSL_FILETYPE_ASN1) != SSL_SUCCESS) {
+                        UnLockMutex(&session->context->namedKeysMutex);
+                        SetError(CLIENT_HELLO_LATE_KEY_STR, error, session,
+                                                             FATAL_ERROR_STATE);
+                        return -1;
+                    }
+                    break;
+                }
+                else
+                    namedKey = namedKey->next;
+            }
+            UnLockMutex(&session->context->namedKeysMutex);
+        }
+    }
+#endif
+
+    session->flags.clientHello = 1;  /* don't process again */
+
+    /* make sure can read up to session len */
+    if (toRead > *sslBytes) {
+        SetError(CLIENT_HELLO_INPUT_STR, error, session, FATAL_ERROR_STATE);
+        return -1;
+    }
+
+    /* skip, get negotiated one from server hello */
+    input     += VERSION_SZ;
+    *sslBytes -= VERSION_SZ;
+
+    XMEMCPY(session->sslServer->arrays->clientRandom, input, RAN_LEN);
+    XMEMCPY(session->sslClient->arrays->clientRandom, input, RAN_LEN);
+
+    input     += RAN_LEN;
+    *sslBytes -= RAN_LEN;
+
+    /* store session in case trying to resume */
+    bLen = *input++;
+    *sslBytes -= ENUM_LEN;
+    if (bLen) {
+        if (ID_LEN > *sslBytes) {
+            SetError(CLIENT_HELLO_INPUT_STR, error, session, FATAL_ERROR_STATE);
+            return -1;
+        }
+        Trace(CLIENT_RESUME_TRY_STR);
+        XMEMCPY(session->sslClient->arrays->sessionID, input, ID_LEN);
+        session->sslClient->options.haveSessionId = 1;
+    }
+#ifdef SHOW_SECRETS
+    {
+        int i;
+        printf("client random: ");
+        for (i = 0; i < RAN_LEN; i++)
+            printf("%02x", session->sslServer->arrays->clientRandom[i]);
+        printf("\n");
+    }
+#endif
+
+    input     += bLen;
+    *sslBytes -= bLen;
+
+    /* skip cipher suites */
+    /* make sure can read len */
+    if (SUITE_LEN > *sslBytes) {
+        SetError(CLIENT_HELLO_INPUT_STR, error, session, FATAL_ERROR_STATE);
+        return -1;
+    }
+    len = (word16)((input[0] << 8) | input[1]);
+    input     += SUITE_LEN;
+    *sslBytes -= SUITE_LEN;
+    /* make sure can read suites + comp len */
+    if (len + ENUM_LEN > *sslBytes) {
+        SetError(CLIENT_HELLO_INPUT_STR, error, session, FATAL_ERROR_STATE);
+        return -1;
+    }
+    input     += len;
+    *sslBytes -= len;
+
+    /* skip compression */
+    bLen       = *input++;
+    *sslBytes -= ENUM_LEN;
+    /* make sure can read len */
+    if (bLen > *sslBytes) {
+        SetError(CLIENT_HELLO_INPUT_STR, error, session, FATAL_ERROR_STATE);
+        return -1;
+    }
+    input     += bLen;
+    *sslBytes -= bLen;
+  
+    if (*sslBytes == 0) {
+        /* no extensions */
+        return 0;
+    }
+    
+    /* skip extensions until session ticket */
+    /* make sure can read len */
+    if (SUITE_LEN > *sslBytes) {
+        SetError(CLIENT_HELLO_INPUT_STR, error, session, FATAL_ERROR_STATE);
+        return -1;
+    }
+    len = (word16)((input[0] << 8) | input[1]);
+    input     += SUITE_LEN;
+    *sslBytes -= SUITE_LEN;
+    /* make sure can read through all extensions */
+    if (len > *sslBytes) {
+        SetError(CLIENT_HELLO_INPUT_STR, error, session, FATAL_ERROR_STATE);
+        return -1;
+    }
+
+    while (len > EXT_TYPE_SZ + LENGTH_SZ) {
+        byte   extType[EXT_TYPE_SZ];
+        word16 extLen;
+
+        extType[0] = input[0];
+        extType[1] = input[1];
+        input     += EXT_TYPE_SZ;
+        *sslBytes -= EXT_TYPE_SZ;
+
+        extLen = (word16)((input[0] << 8) | input[1]);
+        input     += LENGTH_SZ;
+        *sslBytes -= LENGTH_SZ;
+
+        /* make sure can read through individual extension */
+        if (extLen > *sslBytes) {
+            SetError(CLIENT_HELLO_INPUT_STR, error, session, FATAL_ERROR_STATE);
+            return -1;
+        }
+
+        if (extType[0] == 0x00 && extType[1] == TICKET_EXT_ID) {
+
+            /* make sure can read through ticket if there is a non blank one */
+            if (extLen && extLen < ID_LEN) {
+                SetError(CLIENT_HELLO_INPUT_STR, error, session,
+                         FATAL_ERROR_STATE);
+                return -1;
+            }
+
+            if (extLen) {
+                if (session->ticketID == 0) {
+                    session->ticketID = (byte*)malloc(ID_LEN);
+                    if (session->ticketID == 0) {
+                        SetError(MEMORY_STR, error, session,
+                                 FATAL_ERROR_STATE);
+                        return -1;
+                    }
+                }
+                XMEMCPY(session->ticketID, input + extLen - ID_LEN, ID_LEN);
+            }
+        }
+
+        input     += extLen;
+        *sslBytes -= extLen;
+        len       -= extLen + EXT_TYPE_SZ + LENGTH_SZ;
+    }
+
+    return 0;
+}
+
+
+/* Process Finished */
+static int ProcessFinished(const byte* input, int size, int* sslBytes,
+                           SnifferSession* session, char* error)
+{
+    SSL*   ssl;
+    word32 inOutIdx = 0;
+    int    ret;
+                
+    if (session->flags.side == WOLFSSL_SERVER_END)
+        ssl = session->sslServer;
+    else
+        ssl = session->sslClient;
+
+    ret = DoFinished(ssl, input, &inOutIdx, (word32) size, (word32) *sslBytes,
+                                                                         SNIFF);
+    *sslBytes -= (int)inOutIdx;
+
+    if (ret < 0) {
+        SetError(BAD_FINISHED_MSG, error, session, FATAL_ERROR_STATE);
+        return ret;
+    }
+                
+    if (ret == 0 && session->flags.cached == 0) {
+        if (session->sslServer->options.haveSessionId) {
+            WOLFSSL_SESSION* sess = GetSession(session->sslServer, NULL);
+            if (sess == NULL)
+                AddSession(session->sslServer);  /* don't re add */
+            session->flags.cached = 1;
+         }
+    }
+
+    /* If receiving a finished message from one side, free the resources
+     * from the other side's tracker. */
+    if (session->flags.side == WOLFSSL_SERVER_END)
+        FreeHandshakeResources(session->sslClient);
+    else
+        FreeHandshakeResources(session->sslServer);
+
+    return ret;
+}
+
+
+/* Process HandShake input */
+static int DoHandShake(const byte* input, int* sslBytes,
+                       SnifferSession* session, char* error)
+{
+    byte type;
+    int  size;
+    int  ret = 0;
+    int  startBytes;
+
+    if (*sslBytes < HANDSHAKE_HEADER_SZ) {
+        SetError(HANDSHAKE_INPUT_STR, error, session, FATAL_ERROR_STATE);
+        return -1;
+    }
+    type = input[0];
+    size = (input[1] << 16) | (input[2] << 8) | input[3];
+    
+    input     += HANDSHAKE_HEADER_SZ;
+    *sslBytes -= HANDSHAKE_HEADER_SZ;
+    startBytes = *sslBytes;
+
+    if (*sslBytes < size) {
+        SetError(HANDSHAKE_INPUT_STR, error, session, FATAL_ERROR_STATE);
+        return -1;
+    }
+    
+    switch (type) {
+        case hello_verify_request:
+            Trace(GOT_HELLO_VERIFY_STR);
+            break;
+        case hello_request:
+            Trace(GOT_HELLO_REQUEST_STR);
+            break;
+        case session_ticket:
+            Trace(GOT_SESSION_TICKET_STR);
+            ret = ProcessSessionTicket(input, sslBytes, session, error);
+            break;
+        case server_hello:
+            Trace(GOT_SERVER_HELLO_STR);
+            ret = ProcessServerHello(input, sslBytes, session, error);
+            break;
+        case certificate_request:
+            Trace(GOT_CERT_REQ_STR);
+            break;
+        case server_key_exchange:
+            Trace(GOT_SERVER_KEY_EX_STR);
+            /* can't know temp key passively */
+            SetError(BAD_CIPHER_SPEC_STR, error, session, FATAL_ERROR_STATE);
+            ret = -1;
+            break;
+        case certificate:
+            Trace(GOT_CERT_STR);
+            break;
+        case server_hello_done:
+            Trace(GOT_SERVER_HELLO_DONE_STR);
+            break;
+        case finished:
+            Trace(GOT_FINISHED_STR);
+            ret = ProcessFinished(input, size, sslBytes, session, error);
+            break;
+        case client_hello:
+            Trace(GOT_CLIENT_HELLO_STR);
+            ret = ProcessClientHello(input, sslBytes, session, error);
+            break;
+        case client_key_exchange:
+            Trace(GOT_CLIENT_KEY_EX_STR);
+            ret = ProcessClientKeyExchange(input, sslBytes, session, error);
+            break;
+        case certificate_verify:
+            Trace(GOT_CERT_VER_STR);
+            break;
+        case certificate_status:
+            Trace(GOT_CERT_STATUS_STR);
+            break;
+        default:
+            SetError(GOT_UNKNOWN_HANDSHAKE_STR, error, session, 0);
+            return -1;
+    }
+
+    *sslBytes = startBytes - size;  /* actual bytes of full process */
+
+    return ret;
+}
+
+
+/* Decrypt input into plain output, 0 on success */
+static int Decrypt(SSL* ssl, byte* output, const byte* input, word32 sz)
+{
+    int ret = 0;
+
+    switch (ssl->specs.bulk_cipher_algorithm) {
+        #ifdef BUILD_ARC4
+        case wolfssl_rc4:
+            wc_Arc4Process(ssl->decrypt.arc4, output, input, sz);
+            break;
+        #endif
+            
+        #ifdef BUILD_DES3
+        case wolfssl_triple_des:
+            ret = wc_Des3_CbcDecrypt(ssl->decrypt.des3, output, input, sz);
+            break;
+        #endif
+            
+        #ifdef BUILD_AES
+        case wolfssl_aes:
+            ret = wc_AesCbcDecrypt(ssl->decrypt.aes, output, input, sz);
+            break;
+        #endif
+            
+        #ifdef HAVE_HC128
+        case wolfssl_hc128:
+            wc_Hc128_Process(ssl->decrypt.hc128, output, input, sz);
+            break;
+        #endif
+            
+        #ifdef BUILD_RABBIT
+        case wolfssl_rabbit:
+            wc_RabbitProcess(ssl->decrypt.rabbit, output, input, sz);
+            break;
+        #endif
+
+        #ifdef HAVE_CAMELLIA 
+        case wolfssl_camellia:
+            wc_CamelliaCbcDecrypt(ssl->decrypt.cam, output, input, sz);
+            break;
+        #endif
+
+        default:
+            Trace(BAD_DECRYPT_TYPE);
+            ret = -1;
+            break;
+    }
+
+    return ret;
+}
+
+
+/* Decrypt input message into output, adjust output steam if needed */
+static const byte* DecryptMessage(SSL* ssl, const byte* input, word32 sz,
+                                  byte* output, int* error, int* advance)
+{
+    int ivExtra = 0;
+
+    int ret = Decrypt(ssl, output, input, sz);
+    if (ret != 0) {
+        *error = ret;
+        return NULL;
+    }
+    ssl->keys.encryptSz = sz;
+    if (ssl->options.tls1_1 && ssl->specs.cipher_type == block) {
+        output += ssl->specs.block_size;     /* go past TLSv1.1 IV */
+        ivExtra = ssl->specs.block_size;
+        *advance = ssl->specs.block_size;
+    }
+
+    ssl->keys.padSz = ssl->specs.hash_size;
+
+    if (ssl->specs.cipher_type == block)
+        ssl->keys.padSz += *(output + sz - ivExtra - 1) + 1;
+    
+    return output;
+}
+
+
+/* remove session from table, use rowHint if no info (means we have a lock) */
+static void RemoveSession(SnifferSession* session, IpInfo* ipInfo,
+                        TcpInfo* tcpInfo, word32 rowHint)
+{
+    SnifferSession* previous = 0;
+    SnifferSession* current;
+    word32          row = rowHint;
+    int             haveLock = 0;
+   
+    if (ipInfo && tcpInfo)
+        row = SessionHash(ipInfo, tcpInfo);
+    else
+        haveLock = 1;
+    
+    assert(row <= HASH_SIZE);
+    Trace(REMOVE_SESSION_STR);
+    
+    if (!haveLock)
+        LockMutex(&SessionMutex);
+    
+    current = SessionTable[row];
+    
+    while (current) {
+        if (current == session) {
+            if (previous)
+                previous->next = current->next;
+            else
+                SessionTable[row] = current->next;
+            FreeSnifferSession(session);
+            TraceRemovedSession();
+            break;
+        }
+        previous = current;
+        current  = current->next;
+    }
+    
+    if (!haveLock)
+        UnLockMutex(&SessionMutex);
+}
+
+
+/* Remove stale sessions from the Session Table, have a lock */
+static void RemoveStaleSessions(void)
+{
+    word32 i;
+    SnifferSession* session;
+    
+    for (i = 0; i < HASH_SIZE; i++) {
+        session = SessionTable[i];
+        while (session) {
+            SnifferSession* next = session->next; 
+            if (time(NULL) >= session->lastUsed + WOLFSSL_SNIFFER_TIMEOUT) {
+                TraceStaleSession();
+                RemoveSession(session, NULL, NULL, i);
+            }
+            session = next;
+        }
+    }
+}
+
+
+/* Create a new Sniffer Session */
+static SnifferSession* CreateSession(IpInfo* ipInfo, TcpInfo* tcpInfo,
+                                     char* error)
+{
+    SnifferSession* session = 0;
+    int row;
+        
+    Trace(NEW_SESSION_STR);
+    /* create a new one */
+    session = (SnifferSession*)malloc(sizeof(SnifferSession));
+    if (session == NULL) {
+        SetError(MEMORY_STR, error, NULL, 0);
+        return 0;
+    }
+    InitSession(session);
+    session->server  = ipInfo->dst;
+    session->client  = ipInfo->src;
+    session->srvPort = (word16)tcpInfo->dstPort;
+    session->cliPort = (word16)tcpInfo->srcPort;
+    session->cliSeqStart = tcpInfo->sequence;
+    session->cliExpected = 1;  /* relative */
+    session->lastUsed= time(NULL);
+                
+    session->context = GetSnifferServer(ipInfo, tcpInfo);
+    if (session->context == NULL) {
+        SetError(SERVER_NOT_REG_STR, error, NULL, 0);
+        free(session);
+        return 0;
+    }
+        
+    session->sslServer = SSL_new(session->context->ctx);
+    if (session->sslServer == NULL) {
+        SetError(BAD_NEW_SSL_STR, error, session, FATAL_ERROR_STATE);
+        free(session);
+        return 0;
+    }
+    session->sslClient = SSL_new(session->context->ctx);
+    if (session->sslClient == NULL) {
+        SSL_free(session->sslServer);
+        session->sslServer = 0;
+
+        SetError(BAD_NEW_SSL_STR, error, session, FATAL_ERROR_STATE);
+        free(session);
+        return 0;
+    }
+    /* put server back into server mode */
+    session->sslServer->options.side = WOLFSSL_SERVER_END;
+        
+    row = SessionHash(ipInfo, tcpInfo);
+    
+    /* add it to the session table */
+    LockMutex(&SessionMutex);
+        
+    session->next = SessionTable[row];
+    SessionTable[row] = session;
+    
+    SessionCount++;
+    
+    if ( (SessionCount % HASH_SIZE) == 0) {
+        TraceFindingStale();
+        RemoveStaleSessions();
+    }
+        
+    UnLockMutex(&SessionMutex);
+        
+    /* determine headed side */
+    if (ipInfo->dst == session->context->server &&
+        tcpInfo->dstPort == session->context->port)
+        session->flags.side = WOLFSSL_SERVER_END;
+    else
+        session->flags.side = WOLFSSL_CLIENT_END;        
+    
+    return session;
+}
+
+
+#ifdef OLD_HELLO_ALLOWED
+
+/* Process Old Client Hello Input */
+static int DoOldHello(SnifferSession* session, const byte* sslFrame,
+                      int* rhSize, int* sslBytes, char* error)
+{
+    const byte* input = sslFrame;
+    byte        b0, b1;
+    word32      idx = 0;
+    int         ret;
+
+    Trace(GOT_OLD_CLIENT_HELLO_STR);
+    session->flags.clientHello = 1;    /* don't process again */
+    b0 = *input++;
+    b1 = *input++;
+    *sslBytes -= 2;
+    *rhSize = ((b0 & 0x7f) << 8) | b1;
+
+    if (*rhSize > *sslBytes) {
+        SetError(OLD_CLIENT_INPUT_STR, error, session, FATAL_ERROR_STATE);
+        return -1;
+    }
+
+    ret = ProcessOldClientHello(session->sslServer, input, &idx, *sslBytes,
+                                (word16)*rhSize);    
+    if (ret < 0 && ret != MATCH_SUITE_ERROR) {
+        SetError(BAD_OLD_CLIENT_STR, error, session, FATAL_ERROR_STATE);
+        return -1;
+    }
+    
+    Trace(OLD_CLIENT_OK_STR);
+    XMEMCPY(session->sslClient->arrays->clientRandom,
+           session->sslServer->arrays->clientRandom, RAN_LEN);
+    
+    *sslBytes -= *rhSize;
+    return 0;
+}
+
+#endif /* OLD_HELLO_ALLOWED */
+
+
+#if 0
+/* Calculate the TCP checksum, see RFC 1071 */
+/* return 0 for success, -1 on error */
+/* can be called from decode() with
+   TcpChecksum(&ipInfo, &tcpInfo, sslBytes, packet + ipInfo.length);
+   could also add a 64bit version if type available and using this
+*/
+int TcpChecksum(IpInfo* ipInfo, TcpInfo* tcpInfo, int dataLen,
+                const byte* packet)
+{
+    TcpPseudoHdr  pseudo;
+    int           count = PSEUDO_HDR_SZ;
+    const word16* data = (word16*)&pseudo;
+    word32        sum = 0;
+    word16        checksum;
+    
+    pseudo.src = ipInfo->src;
+    pseudo.dst = ipInfo->dst;
+    pseudo.rsv = 0;
+    pseudo.protocol = TCP_PROTO;
+    pseudo.legnth = htons(tcpInfo->length + dataLen);
+    
+    /* pseudo header sum */
+    while (count >= 2) {
+        sum   += *data++;
+        count -= 2;
+    }
+    
+    count = tcpInfo->length + dataLen;
+    data = (word16*)packet;
+    
+    /* main sum */
+    while (count > 1) {
+        sum   += *data++;
+        count -=2;
+    }
+    
+    /* get left-over, if any */
+    packet = (byte*)data;
+    if (count > 0) {
+        sum += *packet;
+    }
+    
+    /* fold 32bit sum into 16 bits */
+    while (sum >> 16)
+        sum = (sum & 0xffff) + (sum >> 16);
+    
+    checksum = (word16)~sum;
+    /* checksum should now equal 0, since included already calcd checksum */
+    /* field, but tcp checksum offloading could negate calculation */
+    if (checksum == 0)
+        return 0;
+    return -1;
+}
+#endif
+
+
+/* Check IP and TCP headers, set payload */
+/* returns 0 on success, -1 on error */
+static int CheckHeaders(IpInfo* ipInfo, TcpInfo* tcpInfo, const byte* packet,
+                  int length, const byte** sslFrame, int* sslBytes, char* error)
+{
+    TraceHeader();
+    TracePacket();
+
+    /* ip header */
+    if (length < IP_HDR_SZ) {
+        SetError(PACKET_HDR_SHORT_STR, error, NULL, 0);
+        return -1;
+    }
+    if (CheckIpHdr((IpHdr*)packet, ipInfo, length, error) != 0)
+        return -1;
+   
+    /* tcp header */ 
+    if (length < (ipInfo->length + TCP_HDR_SZ)) {
+        SetError(PACKET_HDR_SHORT_STR, error, NULL, 0);
+        return -1;
+    }
+    if (CheckTcpHdr((TcpHdr*)(packet + ipInfo->length), tcpInfo, error) != 0)
+        return -1;
+   
+    /* setup */ 
+    *sslFrame = packet + ipInfo->length + tcpInfo->length;
+    if (*sslFrame > packet + length) {
+        SetError(PACKET_HDR_SHORT_STR, error, NULL, 0);
+        return -1;
+    }
+    *sslBytes = (int)(packet + length - *sslFrame);
+    
+    return 0;
+}
+
+
+/* Create or Find existing session */
+/* returns 0 on success (continue), -1 on error, 1 on success (end) */
+static int CheckSession(IpInfo* ipInfo, TcpInfo* tcpInfo, int sslBytes,
+                        SnifferSession** session, char* error)
+{
+    /* create a new SnifferSession on client SYN */
+    if (tcpInfo->syn && !tcpInfo->ack) {
+        TraceClientSyn(tcpInfo->sequence);
+        *session = CreateSession(ipInfo, tcpInfo, error);
+        if (*session == NULL) {
+            *session = GetSnifferSession(ipInfo, tcpInfo);
+            /* already had exisiting, so OK */
+            if (*session)
+                return 1;
+            
+            SetError(MEMORY_STR, error, NULL, 0);
+            return -1;
+        }
+        return 1;
+    }
+    /* get existing sniffer session */
+    else {
+        *session = GetSnifferSession(ipInfo, tcpInfo);
+        if (*session == NULL) {
+            /* don't worry about extraneous RST or duplicate FINs */
+            if (tcpInfo->fin || tcpInfo->rst)
+                return 1;
+            /* don't worry about duplicate ACKs either */
+            if (sslBytes == 0 && tcpInfo->ack)
+                return 1;
+            
+            SetError(BAD_SESSION_STR, error, NULL, 0);
+            return -1;
+        }        
+    }
+    return 0;
+}
+
+
+/* Create a Packet Buffer from *begin - end, adjust new *begin and bytesLeft */
+static PacketBuffer* CreateBuffer(word32* begin, word32 end, const byte* data,
+                                  int* bytesLeft)
+{
+    PacketBuffer* pb;
+    
+    int added = end - *begin + 1;
+    assert(*begin <= end);
+    
+    pb = (PacketBuffer*)malloc(sizeof(PacketBuffer));
+    if (pb == NULL) return NULL;
+    
+    pb->next  = 0;
+    pb->begin = *begin;
+    pb->end   = end;
+    pb->data = (byte*)malloc(added);
+    
+    if (pb->data == NULL) {
+        free(pb);
+        return NULL;
+    }
+    XMEMCPY(pb->data, data, added);
+    
+    *bytesLeft -= added;
+    *begin      = pb->end + 1;
+    
+    return pb;
+}
+
+
+/* Add sslFrame to Reassembly List */
+/* returns 1 (end) on success, -1, on error */
+static int AddToReassembly(byte from, word32 seq, const byte* sslFrame,
+                           int sslBytes, SnifferSession* session, char* error)
+{
+    PacketBuffer*  add;
+    PacketBuffer** front = (from == WOLFSSL_SERVER_END) ?
+                       &session->cliReassemblyList: &session->srvReassemblyList;
+    PacketBuffer*  curr = *front;
+    PacketBuffer*  prev = curr;
+    
+    word32  startSeq = seq;
+    word32  added;
+    int     bytesLeft = sslBytes;  /* could be overlapping fragment */
+
+    /* if list is empty add full frame to front */
+    if (!curr) {
+        add = CreateBuffer(&seq, seq + sslBytes - 1, sslFrame, &bytesLeft);
+        if (add == NULL) {
+            SetError(MEMORY_STR, error, session, FATAL_ERROR_STATE);
+            return -1;
+        }
+        *front = add;
+        return 1;
+    }
+    
+    /* add to front if before current front, up to next->begin */
+    if (seq < curr->begin) {
+        word32 end = seq + sslBytes - 1;
+        
+        if (end >= curr->begin)
+            end = curr->begin - 1;
+        
+        add = CreateBuffer(&seq, end, sslFrame, &bytesLeft);
+        if (add == NULL) {
+            SetError(MEMORY_STR, error, session, FATAL_ERROR_STATE);
+            return -1;
+        }
+        add->next = curr;
+        *front = add;
+    }
+    
+    /* while we have bytes left, try to find a gap to fill */
+    while (bytesLeft > 0) {
+        /* get previous packet in list */
+        while (curr && (seq >= curr->begin)) {
+            prev = curr;
+            curr = curr->next;
+        }
+        
+        /* don't add  duplicate data */
+        if (prev->end >= seq) {
+            if ( (seq + bytesLeft - 1) <= prev->end)
+                return 1;
+            seq = prev->end + 1;
+            bytesLeft = startSeq + sslBytes - seq;
+        }
+        
+        if (!curr)
+            /* we're at the end */
+            added = bytesLeft;
+        else 
+            /* we're in between two frames */
+            added = min((word32)bytesLeft, curr->begin - seq);
+        
+        /* data already there */
+        if (added == 0)
+            continue;
+        
+        add = CreateBuffer(&seq, seq + added - 1, &sslFrame[seq - startSeq],
+                           &bytesLeft);
+        if (add == NULL) {
+            SetError(MEMORY_STR, error, session, FATAL_ERROR_STATE);
+            return -1;
+        }
+        add->next  = prev->next;
+        prev->next = add;
+    }
+    return 1;
+}
+
+
+/* Add out of order FIN capture */
+/* returns 1 for success (end) */
+static int AddFinCapture(SnifferSession* session, word32 sequence)
+{
+    if (session->flags.side == WOLFSSL_SERVER_END) {
+        if (session->finCaputre.cliCounted == 0)
+            session->finCaputre.cliFinSeq = sequence;
+    }
+    else {
+        if (session->finCaputre.srvCounted == 0)
+            session->finCaputre.srvFinSeq = sequence;
+    }
+    return 1;
+}
+
+
+/* Adjust incoming sequence based on side */
+/* returns 0 on success (continue), -1 on error, 1 on success (end) */
+static int AdjustSequence(TcpInfo* tcpInfo, SnifferSession* session,
+                          int* sslBytes, const byte** sslFrame, char* error)
+{
+    word32  seqStart = (session->flags.side == WOLFSSL_SERVER_END) ? 
+                                     session->cliSeqStart :session->srvSeqStart;
+    word32  real     = tcpInfo->sequence - seqStart;
+    word32* expected = (session->flags.side == WOLFSSL_SERVER_END) ?
+                                  &session->cliExpected : &session->srvExpected;
+    PacketBuffer* reassemblyList = (session->flags.side == WOLFSSL_SERVER_END) ?
+                        session->cliReassemblyList : session->srvReassemblyList;
+    
+    /* handle rollover of sequence */
+    if (tcpInfo->sequence < seqStart)
+        real = 0xffffffffU - seqStart + tcpInfo->sequence;
+        
+    TraceRelativeSequence(*expected, real);
+    
+    if (real < *expected) {
+        Trace(DUPLICATE_STR);
+        if (real + *sslBytes > *expected) {
+            int overlap = *expected - real;
+            Trace(OVERLAP_DUPLICATE_STR);
+                
+            /* adjust to expected, remove duplicate */
+            *sslFrame += overlap;
+            *sslBytes -= overlap;
+                
+            if (reassemblyList) {
+                word32 newEnd = *expected + *sslBytes;
+                    
+                if (newEnd > reassemblyList->begin) {
+                    Trace(OVERLAP_REASSEMBLY_BEGIN_STR);
+                    
+                    /* remove bytes already on reassembly list */
+                    *sslBytes -= newEnd - reassemblyList->begin;
+                }
+                if (newEnd > reassemblyList->end) {
+                    Trace(OVERLAP_REASSEMBLY_END_STR);
+                    
+                    /* may be past reassembly list end (could have more on list)
+                       so try to add what's past the front->end */
+                    AddToReassembly(session->flags.side, reassemblyList->end +1,
+                                *sslFrame + reassemblyList->end - *expected + 1,
+                                 newEnd - reassemblyList->end, session, error);
+                }
+            }
+        }
+        else
+            return 1;
+    }
+    else if (real > *expected) {
+        Trace(OUT_OF_ORDER_STR);
+        if (*sslBytes > 0)
+            return AddToReassembly(session->flags.side, real, *sslFrame,
+                                   *sslBytes, session, error);
+        else if (tcpInfo->fin)
+            return AddFinCapture(session, real);
+    }
+    /* got expected sequence */
+    *expected += *sslBytes;
+    if (tcpInfo->fin)
+        *expected += 1;
+    
+    return 0;
+}
+
+
+/* Check latest ack number for missing packets
+   return 0 ok, <0 on error */
+static int CheckAck(TcpInfo* tcpInfo, SnifferSession* session)
+{
+    if (tcpInfo->ack) {
+        word32  seqStart = (session->flags.side == WOLFSSL_SERVER_END) ? 
+                                     session->srvSeqStart :session->cliSeqStart;
+        word32  real     = tcpInfo->ackNumber - seqStart;
+        word32  expected = (session->flags.side == WOLFSSL_SERVER_END) ?
+                                  session->srvExpected : session->cliExpected;
+    
+        /* handle rollover of sequence */
+        if (tcpInfo->ackNumber < seqStart)
+            real = 0xffffffffU - seqStart + tcpInfo->ackNumber;
+        
+        TraceAck(real, expected);
+
+        if (real > expected)
+            return -1;  /* we missed a packet, ACKing data we never saw */
+    }
+    return 0;
+}
+
+
+/* Check TCP Sequence status */
+/* returns 0 on success (continue), -1 on error, 1 on success (end) */
+static int CheckSequence(IpInfo* ipInfo, TcpInfo* tcpInfo,
+                         SnifferSession* session, int* sslBytes,
+                         const byte** sslFrame, char* error)
+{
+    int actualLen;
+    
+    /* init SEQ from server to client */
+    if (tcpInfo->syn && tcpInfo->ack) {
+        session->srvSeqStart = tcpInfo->sequence;
+        session->srvExpected = 1;
+        TraceServerSyn(tcpInfo->sequence);
+        return 1;
+    }
+    
+    /* adjust potential ethernet trailer */
+    actualLen = ipInfo->total - ipInfo->length - tcpInfo->length;
+    if (*sslBytes > actualLen) {
+        *sslBytes = actualLen;
+    }
+    
+    TraceSequence(tcpInfo->sequence, *sslBytes);
+    if (CheckAck(tcpInfo, session) < 0) {
+        SetError(ACK_MISSED_STR, error, session, FATAL_ERROR_STATE);
+        return -1;
+    }
+    
+    return AdjustSequence(tcpInfo, session, sslBytes, sslFrame, error);    
+}
+
+
+/* Check Status before record processing */
+/* returns 0 on success (continue), -1 on error, 1 on success (end) */
+static int CheckPreRecord(IpInfo* ipInfo, TcpInfo* tcpInfo,
+                          const byte** sslFrame, SnifferSession** session,
+                          int* sslBytes, const byte** end, char* error)
+{
+    word32 length;
+    SSL*  ssl = ((*session)->flags.side == WOLFSSL_SERVER_END) ?
+                                  (*session)->sslServer : (*session)->sslClient;
+    /* remove SnifferSession on 2nd FIN or RST */
+    if (tcpInfo->fin || tcpInfo->rst) {
+        /* flag FIN and RST */
+        if (tcpInfo->fin)
+            (*session)->flags.finCount += 1;
+        else if (tcpInfo->rst)
+            (*session)->flags.finCount += 2;
+        
+        if ((*session)->flags.finCount >= 2) {
+            RemoveSession(*session, ipInfo, tcpInfo, 0);
+            *session = NULL;
+            return 1;
+        }
+    }
+    
+    if ((*session)->flags.fatalError == FATAL_ERROR_STATE) {
+        SetError(FATAL_ERROR_STR, error, NULL, 0);
+        return -1;
+    }
+    
+    if (*sslBytes == 0) {
+        Trace(NO_DATA_STR);
+        return 1;
+    }
+    
+    /* if current partial data, add to end of partial */
+    if ( (length = ssl->buffers.inputBuffer.length) ) {
+        Trace(PARTIAL_ADD_STR);
+        
+        if ( (*sslBytes + length) > ssl->buffers.inputBuffer.bufferSize) {
+            if (GrowInputBuffer(ssl, *sslBytes, length) < 0) {
+                SetError(MEMORY_STR, error, *session, FATAL_ERROR_STATE);
+                return -1;
+            }
+        }
+        XMEMCPY(&ssl->buffers.inputBuffer.buffer[length], *sslFrame, *sslBytes);
+        *sslBytes += length;
+        ssl->buffers.inputBuffer.length = *sslBytes;
+        *sslFrame = ssl->buffers.inputBuffer.buffer;
+        *end = *sslFrame + *sslBytes;
+    }
+
+    if ((*session)->flags.clientHello == 0 && **sslFrame != handshake) {
+        /* Sanity check the packet for an old style client hello. */
+        int rhSize = (((*sslFrame)[0] & 0x7f) << 8) | ((*sslFrame)[1]);
+
+        if ((rhSize <= (*sslBytes - 2)) &&
+            (*sslFrame)[2] == OLD_HELLO_ID && (*sslFrame)[3] == SSLv3_MAJOR) {
+#ifdef OLD_HELLO_ALLOWED
+        int ret = DoOldHello(*session, *sslFrame, &rhSize, sslBytes, error);
+        if (ret < 0)
+            return -1;  /* error already set */
+        if (*sslBytes <= 0)
+            return 1;
+#endif
+        }
+        else {
+#ifdef STARTTLS_ALLOWED
+            return 1;
+#endif
+        }
+    }
+
+    return 0;
+}
+
+
+/* See if input on the reassembly list is ready for consuming */
+/* returns 1 for TRUE, 0 for FALSE */
+static int HaveMoreInput(SnifferSession* session, const byte** sslFrame,
+                         int* sslBytes, const byte** end, char* error)
+{
+    /* sequence and reassembly based on from, not to */
+    int            moreInput = 0;
+    PacketBuffer** front = (session->flags.side == WOLFSSL_SERVER_END) ?
+                      &session->cliReassemblyList : &session->srvReassemblyList;
+    word32*        expected = (session->flags.side == WOLFSSL_SERVER_END) ?
+                                  &session->cliExpected : &session->srvExpected;
+    /* buffer is on receiving end */
+    word32*        length = (session->flags.side == WOLFSSL_SERVER_END) ?
+                               &session->sslServer->buffers.inputBuffer.length :
+                               &session->sslClient->buffers.inputBuffer.length;
+    byte*          myBuffer = (session->flags.side == WOLFSSL_SERVER_END) ?
+                                session->sslServer->buffers.inputBuffer.buffer :
+                                session->sslClient->buffers.inputBuffer.buffer;
+    word32       bufferSize = (session->flags.side == WOLFSSL_SERVER_END) ?
+                            session->sslServer->buffers.inputBuffer.bufferSize :
+                            session->sslClient->buffers.inputBuffer.bufferSize;
+    SSL*               ssl  = (session->flags.side == WOLFSSL_SERVER_END) ?
+                            session->sslServer : session->sslClient;
+    
+    while (*front && ((*front)->begin == *expected) ) {
+        word32 room = bufferSize - *length;
+        word32 packetLen = (*front)->end - (*front)->begin + 1;
+
+        if (packetLen > room && bufferSize < MAX_INPUT_SZ) {
+            if (GrowInputBuffer(ssl, packetLen, *length) < 0) {
+                SetError(MEMORY_STR, error, session, FATAL_ERROR_STATE);
+                return 0;
+            }
+        }
+        
+        if (packetLen <= room) {
+            PacketBuffer* del = *front;
+            
+            XMEMCPY(&myBuffer[*length], (*front)->data, packetLen);
+            *length   += packetLen;
+            *expected += packetLen;
+            
+            /* remove used packet */
+            *front = (*front)->next;
+            FreePacketBuffer(del);
+            
+            moreInput = 1;
+        }
+        else
+            break;
+    }
+    if (moreInput) {
+        *sslFrame = myBuffer;
+        *sslBytes = *length;
+        *end      = myBuffer + *length;
+    }
+    return moreInput;
+}
+                         
+
+
+/* Process Message(s) from sslFrame */
+/* return Number of bytes on success, 0 for no data yet, and -1 on error */
+static int ProcessMessage(const byte* sslFrame, SnifferSession* session,
+                          int sslBytes, byte* data, const byte* end,char* error)
+{
+    const byte*       sslBegin = sslFrame;
+    const byte*       recordEnd;   /* end of record indicator */
+    const byte*       inRecordEnd; /* indictor from input stream not decrypt */
+    RecordLayerHeader rh;
+    int               rhSize = 0;
+    int               ret;
+    int               errCode = 0;
+    int               decoded = 0;      /* bytes stored for user in data */
+    int               notEnough;        /* notEnough bytes yet flag */
+    int               decrypted = 0;    /* was current msg decrypted */
+    SSL*              ssl = (session->flags.side == WOLFSSL_SERVER_END) ?
+                                        session->sslServer : session->sslClient;
+doMessage:
+    notEnough = 0;
+    if (sslBytes < 0) {
+        SetError(PACKET_HDR_SHORT_STR, error, session, FATAL_ERROR_STATE);
+        return -1;
+    }
+    if (sslBytes >= RECORD_HEADER_SZ) {
+        if (GetRecordHeader(sslFrame, &rh, &rhSize) != 0) {
+            SetError(BAD_RECORD_HDR_STR, error, session, FATAL_ERROR_STATE);
+            return -1;
+        }
+    }
+    else
+        notEnough = 1;
+
+    if (notEnough || rhSize > (sslBytes - RECORD_HEADER_SZ)) {
+        /* don't have enough input yet to process full SSL record */
+        Trace(PARTIAL_INPUT_STR);
+        
+        /* store partial if not there already or we advanced */
+        if (ssl->buffers.inputBuffer.length == 0 || sslBegin != sslFrame) {
+            if (sslBytes > (int)ssl->buffers.inputBuffer.bufferSize) {
+                if (GrowInputBuffer(ssl, sslBytes, 0) < 0) { 
+                    SetError(MEMORY_STR, error, session, FATAL_ERROR_STATE);
+                    return -1;
+                }
+            }
+            XMEMMOVE(ssl->buffers.inputBuffer.buffer, sslFrame, sslBytes);
+            ssl->buffers.inputBuffer.length = sslBytes;
+        }
+        if (HaveMoreInput(session, &sslFrame, &sslBytes, &end, error))
+            goto doMessage;
+        return decoded;
+    }
+    sslFrame += RECORD_HEADER_SZ;
+    sslBytes -= RECORD_HEADER_SZ;
+    recordEnd = sslFrame + rhSize;   /* may have more than one record */
+    inRecordEnd = recordEnd;
+    
+    /* decrypt if needed */
+    if ((session->flags.side == WOLFSSL_SERVER_END &&
+                                               session->flags.serverCipherOn)
+     || (session->flags.side == WOLFSSL_CLIENT_END &&
+                                               session->flags.clientCipherOn)) {
+        int ivAdvance = 0;  /* TLSv1.1 advance amount */
+        if (ssl->decrypt.setup != 1) {
+            SetError(DECRYPT_KEYS_NOT_SETUP, error, session, FATAL_ERROR_STATE);
+            return -1;
+        }
+        if (CheckAvailableSize(ssl, rhSize) < 0) {
+            SetError(MEMORY_STR, error, session, FATAL_ERROR_STATE);
+            return -1;
+        }
+        sslFrame = DecryptMessage(ssl, sslFrame, rhSize,
+                                  ssl->buffers.outputBuffer.buffer, &errCode,
+                                  &ivAdvance);
+        recordEnd = sslFrame - ivAdvance + rhSize;  /* sslFrame moved so
+                                                       should recordEnd */
+        decrypted = 1;
+        if (errCode != 0) {
+            SetError(BAD_DECRYPT, error, session, FATAL_ERROR_STATE);
+            return -1;
+        }
+    }
+
+doPart:
+            
+    switch ((enum ContentType)rh.type) {
+        case handshake:
+            {
+                int startIdx = sslBytes;
+                int used;
+
+                Trace(GOT_HANDSHAKE_STR);
+                ret = DoHandShake(sslFrame, &sslBytes, session, error);
+                if (ret != 0) {
+                    if (session->flags.fatalError == 0)
+                        SetError(BAD_HANDSHAKE_STR, error, session,
+                                 FATAL_ERROR_STATE);
+                    return -1;
+                }
+
+                /* DoHandShake now fully decrements sslBytes to remaining */
+                used = startIdx - sslBytes;
+                sslFrame += used;
+                if (decrypted)
+                    sslFrame += ssl->keys.padSz;
+            }
+            break;
+        case change_cipher_spec:
+            if (session->flags.side == WOLFSSL_SERVER_END)
+                session->flags.serverCipherOn = 1;
+            else
+                session->flags.clientCipherOn = 1;
+            Trace(GOT_CHANGE_CIPHER_STR);
+            ssl->options.handShakeState = HANDSHAKE_DONE;
+            ssl->options.handShakeDone  = 1;
+
+            sslFrame += 1;
+            sslBytes -= 1;
+
+            break;
+        case application_data:
+            Trace(GOT_APP_DATA_STR);
+            {
+                word32 inOutIdx = 0;
+                    
+                ret = DoApplicationData(ssl, (byte*)sslFrame, &inOutIdx);
+                if (ret == 0) {
+                    ret = ssl->buffers.clearOutputBuffer.length;
+                    TraceGotData(ret);
+                    if (ret) {  /* may be blank message */
+                        XMEMCPY(&data[decoded],
+                               ssl->buffers.clearOutputBuffer.buffer, ret);
+                        TraceAddedData(ret, decoded);
+                        decoded += ret;
+                        ssl->buffers.clearOutputBuffer.length = 0;
+                    }
+                }
+                else {
+                    SetError(BAD_APP_DATA_STR, error,session,FATAL_ERROR_STATE);
+                    return -1;
+                }
+                if (ssl->buffers.outputBuffer.dynamicFlag)
+                    ShrinkOutputBuffer(ssl);
+
+                sslFrame += inOutIdx;
+                sslBytes -= inOutIdx;
+            }
+            break;
+        case alert:
+            Trace(GOT_ALERT_STR);
+            sslFrame += rhSize;
+            sslBytes -= rhSize;
+            break;
+        case no_type:
+        default:
+            SetError(GOT_UNKNOWN_RECORD_STR, error, session, FATAL_ERROR_STATE);
+            return -1;
+    }
+
+    /* do we have another msg in record ? */
+    if (sslFrame < recordEnd) {
+        Trace(ANOTHER_MSG_STR);
+        goto doPart;
+    }
+
+    /* back to input stream instead of potential decrypt buffer */
+    recordEnd = inRecordEnd;
+
+    /* do we have more records ? */
+    if (recordEnd < end) {
+        Trace(ANOTHER_MSG_STR);
+        sslFrame = recordEnd;
+        sslBytes = (int)(end - recordEnd);
+        goto doMessage;
+    }
+    
+    /* clear used input */
+    ssl->buffers.inputBuffer.length = 0;
+    
+    /* could have more input ready now */
+    if (HaveMoreInput(session, &sslFrame, &sslBytes, &end, error))
+        goto doMessage;
+
+    if (ssl->buffers.inputBuffer.dynamicFlag)
+        ShrinkInputBuffer(ssl, NO_FORCED_FREE);
+    
+    return decoded;
+}
+
+
+/* See if we need to process any pending FIN captures */
+static void CheckFinCapture(IpInfo* ipInfo, TcpInfo* tcpInfo, 
+                            SnifferSession* session)
+{
+    if (session->finCaputre.cliFinSeq && session->finCaputre.cliFinSeq <= 
+                                         session->cliExpected) {
+        if (session->finCaputre.cliCounted == 0) {
+            session->flags.finCount += 1;
+            session->finCaputre.cliCounted = 1;
+            TraceClientFin(session->finCaputre.cliFinSeq, session->cliExpected);
+        }
+    }
+        
+    if (session->finCaputre.srvFinSeq && session->finCaputre.srvFinSeq <= 
+                                         session->srvExpected) {
+        if (session->finCaputre.srvCounted == 0) {
+            session->flags.finCount += 1;
+            session->finCaputre.srvCounted = 1;
+            TraceServerFin(session->finCaputre.srvFinSeq, session->srvExpected);
+        }
+    }
+                
+    if (session->flags.finCount >= 2) 
+        RemoveSession(session, ipInfo, tcpInfo, 0);
+}
+
+
+/* If session is in fatal error state free resources now 
+   return true if removed, 0 otherwise */
+static int RemoveFatalSession(IpInfo* ipInfo, TcpInfo* tcpInfo,
+                              SnifferSession* session, char* error)
+{
+    if (session && session->flags.fatalError == FATAL_ERROR_STATE) {
+        RemoveSession(session, ipInfo, tcpInfo, 0);
+        SetError(FATAL_ERROR_STR, error, NULL, 0);
+        return 1;
+    }
+    return 0;
+}
+
+
+/* Passes in an IP/TCP packet for decoding (ethernet/localhost frame) removed */
+/* returns Number of bytes on success, 0 for no data yet, and -1 on error */
+int ssl_DecodePacket(const byte* packet, int length, byte* data, char* error)
+{
+    TcpInfo           tcpInfo;
+    IpInfo            ipInfo;
+    const byte*       sslFrame;
+    const byte*       end = packet + length;
+    int               sslBytes;                /* ssl bytes unconsumed */
+    int               ret;
+    SnifferSession*   session = 0;
+
+    if (CheckHeaders(&ipInfo, &tcpInfo, packet, length, &sslFrame, &sslBytes,
+                     error) != 0)
+        return -1;
+    
+    ret = CheckSession(&ipInfo, &tcpInfo, sslBytes, &session, error);
+    if (RemoveFatalSession(&ipInfo, &tcpInfo, session, error)) return -1;
+    else if (ret == -1) return -1;
+    else if (ret ==  1) return  0;   /* done for now */
+    
+    ret = CheckSequence(&ipInfo, &tcpInfo, session, &sslBytes, &sslFrame,error);
+    if (RemoveFatalSession(&ipInfo, &tcpInfo, session, error)) return -1;
+    else if (ret == -1) return -1;
+    else if (ret ==  1) return  0;   /* done for now */
+    
+    ret = CheckPreRecord(&ipInfo, &tcpInfo, &sslFrame, &session, &sslBytes,
+                         &end, error);
+    if (RemoveFatalSession(&ipInfo, &tcpInfo, session, error)) return -1;
+    else if (ret == -1) return -1;
+    else if (ret ==  1) return  0;   /* done for now */
+
+    ret = ProcessMessage(sslFrame, session, sslBytes, data, end, error);
+    if (RemoveFatalSession(&ipInfo, &tcpInfo, session, error)) return -1;
+    CheckFinCapture(&ipInfo, &tcpInfo, session);
+    return ret;
+}
+
+
+/* Enables (if traceFile)/ Disables debug tracing */
+/* returns 0 on success, -1 on error */
+int ssl_Trace(const char* traceFile, char* error)
+{
+    if (traceFile) {
+        TraceFile = fopen(traceFile, "a");
+        if (!TraceFile) {
+            SetError(BAD_TRACE_FILE_STR, error, NULL, 0);
+            return -1;
+        }
+        TraceOn = 1;
+    }
+    else 
+        TraceOn = 0;
+
+    return 0;
+}
+
+
+
+
+#endif /* WOLFSSL_SNIFFER */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/ssl.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/ssl.c
new file mode 100644
index 0000000..139e343
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/ssl.c
@@ -0,0 +1,12937 @@
+/* ssl.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifdef HAVE_ERRNO_H
+    #include 
+#endif
+
+#include 
+#include 
+#include 
+
+#if defined(OPENSSL_EXTRA) || defined(HAVE_WEBSERVER)
+    #include 
+#endif
+
+#ifdef OPENSSL_EXTRA
+    /* openssl headers begin */
+    #include 
+    #include 
+    #include 
+    #include 
+    #include 
+    #include 
+    #include 
+    /* openssl headers end, wolfssl internal headers next */
+    #include 
+    #include 
+    #include 
+    #include 
+    #include 
+    #include 
+    #ifdef WOLFSSL_SHA512
+        #include 
+    #endif
+#endif
+
+#ifndef NO_FILESYSTEM
+    #if !defined(USE_WINDOWS_API) && !defined(NO_WOLFSSL_DIR) \
+            && !defined(EBSNET)
+        #include 
+        #include 
+    #endif
+    #ifdef EBSNET
+        #include "vfapi.h"
+        #include "vfile.h"
+    #endif
+#endif /* NO_FILESYSTEM */
+
+#ifndef TRUE
+    #define TRUE  1
+#endif
+#ifndef FALSE
+    #define FALSE 0
+#endif
+
+#ifndef WOLFSSL_HAVE_MIN
+#define WOLFSSL_HAVE_MIN
+
+    static INLINE word32 min(word32 a, word32 b)
+    {
+        return a > b ? b : a;
+    }
+
+#endif /* WOLFSSSL_HAVE_MIN */
+
+#ifndef WOLFSSL_HAVE_MAX
+#define WOLFSSL_HAVE_MAX
+
+#ifdef WOLFSSL_DTLS
+    static INLINE word32 max(word32 a, word32 b)
+    {
+        return a > b ? a : b;
+    }
+#endif /* WOLFSSL_DTLS */
+
+#endif /* WOLFSSL_HAVE_MAX */
+
+
+#ifndef WOLFSSL_LEANPSK
+char* mystrnstr(const char* s1, const char* s2, unsigned int n)
+{
+    unsigned int s2_len = (unsigned int)XSTRLEN(s2);
+
+    if (s2_len == 0)
+        return (char*)s1;
+
+    while (n >= s2_len && s1[0]) {
+        if (s1[0] == s2[0])
+            if (XMEMCMP(s1, s2, s2_len) == 0)
+                return (char*)s1;
+        s1++;
+        n--;
+    }
+
+    return NULL;
+}
+#endif
+
+
+/* prevent multiple mutex initializations */
+static volatile int initRefCount = 0;
+static wolfSSL_Mutex count_mutex;   /* init ref count mutex */
+
+
+WOLFSSL_CTX* wolfSSL_CTX_new(WOLFSSL_METHOD* method)
+{
+    WOLFSSL_CTX* ctx = NULL;
+
+    WOLFSSL_ENTER("WOLFSSL_CTX_new");
+
+    if (initRefCount == 0)
+        wolfSSL_Init(); /* user no longer forced to call Init themselves */
+
+    if (method == NULL)
+        return ctx;
+
+    ctx = (WOLFSSL_CTX*) XMALLOC(sizeof(WOLFSSL_CTX), 0, DYNAMIC_TYPE_CTX);
+    if (ctx) {
+        if (InitSSL_Ctx(ctx, method) < 0) {
+            WOLFSSL_MSG("Init CTX failed");
+            wolfSSL_CTX_free(ctx);
+            ctx = NULL;
+        }
+    }
+    else {
+        WOLFSSL_MSG("Alloc CTX failed, method freed");
+        XFREE(method, NULL, DYNAMIC_TYPE_METHOD);
+    }
+
+    WOLFSSL_LEAVE("WOLFSSL_CTX_new", 0);
+    return ctx;
+}
+
+
+void wolfSSL_CTX_free(WOLFSSL_CTX* ctx)
+{
+    WOLFSSL_ENTER("SSL_CTX_free");
+    if (ctx)
+        FreeSSL_Ctx(ctx);
+    WOLFSSL_LEAVE("SSL_CTX_free", 0);
+}
+
+
+WOLFSSL* wolfSSL_new(WOLFSSL_CTX* ctx)
+{
+    WOLFSSL* ssl = NULL;
+    int ret = 0;
+
+    (void)ret;
+    WOLFSSL_ENTER("SSL_new");
+
+    if (ctx == NULL)
+        return ssl;
+
+    ssl = (WOLFSSL*) XMALLOC(sizeof(WOLFSSL), ctx->heap,DYNAMIC_TYPE_SSL);
+    if (ssl)
+        if ( (ret = InitSSL(ssl, ctx)) < 0) {
+            FreeSSL(ssl);
+            ssl = 0;
+        }
+
+    WOLFSSL_LEAVE("SSL_new", ret);
+    return ssl;
+}
+
+
+void wolfSSL_free(WOLFSSL* ssl)
+{
+    WOLFSSL_ENTER("SSL_free");
+    if (ssl)
+        FreeSSL(ssl);
+    WOLFSSL_LEAVE("SSL_free", 0);
+}
+
+#ifdef HAVE_POLY1305
+/* set if to use old poly 1 for yes 0 to use new poly */
+int wolfSSL_use_old_poly(WOLFSSL* ssl, int value)
+{
+    WOLFSSL_ENTER("SSL_use_old_poly");
+    ssl->options.oldPoly = value;
+    WOLFSSL_LEAVE("SSL_use_old_poly", 0);
+    return 0;
+}
+#endif
+
+int wolfSSL_set_fd(WOLFSSL* ssl, int fd)
+{
+    WOLFSSL_ENTER("SSL_set_fd");
+    ssl->rfd = fd;      /* not used directly to allow IO callbacks */
+    ssl->wfd = fd;
+
+    ssl->IOCB_ReadCtx  = &ssl->rfd;
+    ssl->IOCB_WriteCtx = &ssl->wfd;
+
+    #ifdef WOLFSSL_DTLS
+        if (ssl->options.dtls) {
+            ssl->IOCB_ReadCtx = &ssl->buffers.dtlsCtx;
+            ssl->IOCB_WriteCtx = &ssl->buffers.dtlsCtx;
+            ssl->buffers.dtlsCtx.fd = fd;
+        }
+    #endif
+
+    WOLFSSL_LEAVE("SSL_set_fd", SSL_SUCCESS);
+    return SSL_SUCCESS;
+}
+
+
+/**
+  * Get the name of cipher at priotity level passed in.
+  */
+char* wolfSSL_get_cipher_list(int priority)
+{
+    const char* const* ciphers = GetCipherNames();
+
+    if (priority >= GetCipherNamesSize() || priority < 0) {
+        return 0;
+    }
+
+    return (char*)ciphers[priority];
+}
+
+
+int wolfSSL_get_ciphers(char* buf, int len)
+{
+    const char* const* ciphers = GetCipherNames();
+    int  totalInc = 0;
+    int  step     = 0;
+    char delim    = ':';
+    int  size     = GetCipherNamesSize();
+    int  i;
+
+    if (buf == NULL || len <= 0)
+        return BAD_FUNC_ARG;
+
+    /* Add each member to the buffer delimitted by a : */
+    for (i = 0; i < size; i++) {
+        step = (int)(XSTRLEN(ciphers[i]) + 1);  /* delimiter */
+        totalInc += step;
+
+        /* Check to make sure buf is large enough and will not overflow */
+        if (totalInc < len) {
+            XSTRNCPY(buf, ciphers[i], XSTRLEN(ciphers[i]));
+            buf += XSTRLEN(ciphers[i]);
+
+            if (i < size - 1)
+                *buf++ = delim;
+        }
+        else
+            return BUFFER_E;
+    }
+    return SSL_SUCCESS;
+}
+
+
+int wolfSSL_get_fd(const WOLFSSL* ssl)
+{
+    WOLFSSL_ENTER("SSL_get_fd");
+    WOLFSSL_LEAVE("SSL_get_fd", ssl->rfd);
+    return ssl->rfd;
+}
+
+
+int wolfSSL_get_using_nonblock(WOLFSSL* ssl)
+{
+    WOLFSSL_ENTER("wolfSSL_get_using_nonblock");
+    WOLFSSL_LEAVE("wolfSSL_get_using_nonblock", ssl->options.usingNonblock);
+    return ssl->options.usingNonblock;
+}
+
+
+int wolfSSL_dtls(WOLFSSL* ssl)
+{
+    return ssl->options.dtls;
+}
+
+
+#ifndef WOLFSSL_LEANPSK
+void wolfSSL_set_using_nonblock(WOLFSSL* ssl, int nonblock)
+{
+    WOLFSSL_ENTER("wolfSSL_set_using_nonblock");
+    ssl->options.usingNonblock = (nonblock != 0);
+}
+
+
+int wolfSSL_dtls_set_peer(WOLFSSL* ssl, void* peer, unsigned int peerSz)
+{
+#ifdef WOLFSSL_DTLS
+    void* sa = (void*)XMALLOC(peerSz, ssl->heap, DYNAMIC_TYPE_SOCKADDR);
+    if (sa != NULL) {
+        if (ssl->buffers.dtlsCtx.peer.sa != NULL)
+            XFREE(ssl->buffers.dtlsCtx.peer.sa,ssl->heap,DYNAMIC_TYPE_SOCKADDR);
+        XMEMCPY(sa, peer, peerSz);
+        ssl->buffers.dtlsCtx.peer.sa = sa;
+        ssl->buffers.dtlsCtx.peer.sz = peerSz;
+        return SSL_SUCCESS;
+    }
+    return SSL_FAILURE;
+#else
+    (void)ssl;
+    (void)peer;
+    (void)peerSz;
+    return SSL_NOT_IMPLEMENTED;
+#endif
+}
+
+int wolfSSL_dtls_get_peer(WOLFSSL* ssl, void* peer, unsigned int* peerSz)
+{
+#ifdef WOLFSSL_DTLS
+    if (peer != NULL && peerSz != NULL
+            && *peerSz >= ssl->buffers.dtlsCtx.peer.sz) {
+        *peerSz = ssl->buffers.dtlsCtx.peer.sz;
+        XMEMCPY(peer, ssl->buffers.dtlsCtx.peer.sa, *peerSz);
+        return SSL_SUCCESS;
+    }
+    return SSL_FAILURE;
+#else
+    (void)ssl;
+    (void)peer;
+    (void)peerSz;
+    return SSL_NOT_IMPLEMENTED;
+#endif
+}
+#endif /* WOLFSSL_LEANPSK */
+
+
+/* return underlyig connect or accept, SSL_SUCCESS on ok */
+int wolfSSL_negotiate(WOLFSSL* ssl)
+{
+    int err = SSL_FATAL_ERROR;
+
+    WOLFSSL_ENTER("wolfSSL_negotiate");
+#ifndef NO_WOLFSSL_SERVER
+    if (ssl->options.side == WOLFSSL_SERVER_END)
+        err = wolfSSL_accept(ssl);
+#endif
+
+#ifndef NO_WOLFSSL_CLIENT
+    if (ssl->options.side == WOLFSSL_CLIENT_END)
+        err = wolfSSL_connect(ssl);
+#endif
+
+    WOLFSSL_LEAVE("wolfSSL_negotiate", err);
+
+    return err;
+}
+
+
+#ifndef WOLFSSL_LEANPSK
+/* object size based on build */
+int wolfSSL_GetObjectSize(void)
+{
+#ifdef SHOW_SIZES
+    printf("sizeof suites           = %lu\n", sizeof(Suites));
+    printf("sizeof ciphers(2)       = %lu\n", sizeof(Ciphers));
+#ifndef NO_RC4
+    printf("    sizeof arc4         = %lu\n", sizeof(Arc4));
+#endif
+    printf("    sizeof aes          = %lu\n", sizeof(Aes));
+#ifndef NO_DES3
+    printf("    sizeof des3         = %lu\n", sizeof(Des3));
+#endif
+#ifndef NO_RABBIT
+    printf("    sizeof rabbit       = %lu\n", sizeof(Rabbit));
+#endif
+#ifdef HAVE_CHACHA
+    printf("    sizeof chacha       = %lu\n", sizeof(Chacha));
+#endif
+    printf("sizeof cipher specs     = %lu\n", sizeof(CipherSpecs));
+    printf("sizeof keys             = %lu\n", sizeof(Keys));
+    printf("sizeof Hashes(2)        = %lu\n", sizeof(Hashes));
+#ifndef NO_MD5
+    printf("    sizeof MD5          = %lu\n", sizeof(Md5));
+#endif
+#ifndef NO_SHA
+    printf("    sizeof SHA          = %lu\n", sizeof(Sha));
+#endif
+#ifndef NO_SHA256
+    printf("    sizeof SHA256       = %lu\n", sizeof(Sha256));
+#endif
+#ifdef WOLFSSL_SHA384
+    printf("    sizeof SHA384       = %lu\n", sizeof(Sha384));
+#endif
+#ifdef WOLFSSL_SHA384
+    printf("    sizeof SHA512       = %lu\n", sizeof(Sha512));
+#endif
+    printf("sizeof Buffers          = %lu\n", sizeof(Buffers));
+    printf("sizeof Options          = %lu\n", sizeof(Options));
+    printf("sizeof Arrays           = %lu\n", sizeof(Arrays));
+#ifndef NO_RSA
+    printf("sizeof RsaKey           = %lu\n", sizeof(RsaKey));
+#endif
+#ifdef HAVE_ECC
+    printf("sizeof ecc_key          = %lu\n", sizeof(ecc_key));
+#endif
+    printf("sizeof WOLFSSL_CIPHER    = %lu\n", sizeof(WOLFSSL_CIPHER));
+    printf("sizeof WOLFSSL_SESSION   = %lu\n", sizeof(WOLFSSL_SESSION));
+    printf("sizeof WOLFSSL           = %lu\n", sizeof(WOLFSSL));
+    printf("sizeof WOLFSSL_CTX       = %lu\n", sizeof(WOLFSSL_CTX));
+#endif
+
+    return sizeof(WOLFSSL);
+}
+#endif
+
+
+#ifndef NO_DH
+/* server Diffie-Hellman parameters, SSL_SUCCESS on ok */
+int wolfSSL_SetTmpDH(WOLFSSL* ssl, const unsigned char* p, int pSz,
+                    const unsigned char* g, int gSz)
+{
+    byte havePSK = 0;
+    byte haveRSA = 1;
+
+    WOLFSSL_ENTER("wolfSSL_SetTmpDH");
+    if (ssl == NULL || p == NULL || g == NULL) return BAD_FUNC_ARG;
+
+    if (pSz < ssl->options.minDhKeySz)
+        return DH_KEY_SIZE_E;
+
+    if (ssl->options.side != WOLFSSL_SERVER_END)
+        return SIDE_ERROR;
+
+    if (ssl->buffers.serverDH_P.buffer && ssl->buffers.weOwnDH)
+        XFREE(ssl->buffers.serverDH_P.buffer, ssl->ctx->heap, DYNAMIC_TYPE_DH);
+    if (ssl->buffers.serverDH_G.buffer && ssl->buffers.weOwnDH)
+        XFREE(ssl->buffers.serverDH_G.buffer, ssl->ctx->heap, DYNAMIC_TYPE_DH);
+
+    ssl->buffers.weOwnDH = 1;  /* SSL owns now */
+    ssl->buffers.serverDH_P.buffer = (byte*)XMALLOC(pSz, ssl->ctx->heap,
+                                                    DYNAMIC_TYPE_DH);
+    if (ssl->buffers.serverDH_P.buffer == NULL)
+        return MEMORY_E;
+
+    ssl->buffers.serverDH_G.buffer = (byte*)XMALLOC(gSz, ssl->ctx->heap,
+                                                    DYNAMIC_TYPE_DH);
+    if (ssl->buffers.serverDH_G.buffer == NULL) {
+        XFREE(ssl->buffers.serverDH_P.buffer, ssl->ctx->heap, DYNAMIC_TYPE_DH);
+        return MEMORY_E;
+    }
+
+    ssl->buffers.serverDH_P.length = pSz;
+    ssl->buffers.serverDH_G.length = gSz;
+
+    XMEMCPY(ssl->buffers.serverDH_P.buffer, p, pSz);
+    XMEMCPY(ssl->buffers.serverDH_G.buffer, g, gSz);
+
+    ssl->options.haveDH = 1;
+    #ifndef NO_PSK
+        havePSK = ssl->options.havePSK;
+    #endif
+    #ifdef NO_RSA
+        haveRSA = 0;
+    #endif
+    InitSuites(ssl->suites, ssl->version, haveRSA, havePSK, ssl->options.haveDH,
+               ssl->options.haveNTRU, ssl->options.haveECDSAsig,
+               ssl->options.haveStaticECC, ssl->options.side);
+
+    WOLFSSL_LEAVE("wolfSSL_SetTmpDH", 0);
+    return SSL_SUCCESS;
+}
+
+/* server ctx Diffie-Hellman parameters, SSL_SUCCESS on ok */
+int wolfSSL_CTX_SetTmpDH(WOLFSSL_CTX* ctx, const unsigned char* p, int pSz,
+                         const unsigned char* g, int gSz)
+{
+    WOLFSSL_ENTER("wolfSSL_CTX_SetTmpDH");
+    if (ctx == NULL || p == NULL || g == NULL) return BAD_FUNC_ARG;
+
+    if (pSz < ctx->minDhKeySz)
+        return DH_KEY_SIZE_E;
+
+    XFREE(ctx->serverDH_P.buffer, ctx->heap, DYNAMIC_TYPE_DH);
+    XFREE(ctx->serverDH_G.buffer, ctx->heap, DYNAMIC_TYPE_DH);
+
+    ctx->serverDH_P.buffer = (byte*)XMALLOC(pSz, ctx->heap,DYNAMIC_TYPE_DH);
+    if (ctx->serverDH_P.buffer == NULL)
+       return MEMORY_E;
+
+    ctx->serverDH_G.buffer = (byte*)XMALLOC(gSz, ctx->heap,DYNAMIC_TYPE_DH);
+    if (ctx->serverDH_G.buffer == NULL) {
+        XFREE(ctx->serverDH_P.buffer, ctx->heap, DYNAMIC_TYPE_DH);
+        return MEMORY_E;
+    }
+
+    ctx->serverDH_P.length = pSz;
+    ctx->serverDH_G.length = gSz;
+
+    XMEMCPY(ctx->serverDH_P.buffer, p, pSz);
+    XMEMCPY(ctx->serverDH_G.buffer, g, gSz);
+
+    ctx->haveDH = 1;
+
+    WOLFSSL_LEAVE("wolfSSL_CTX_SetTmpDH", 0);
+    return SSL_SUCCESS;
+}
+
+#endif /* !NO_DH */
+
+
+int wolfSSL_write(WOLFSSL* ssl, const void* data, int sz)
+{
+    int ret;
+
+    WOLFSSL_ENTER("SSL_write()");
+
+    if (ssl == NULL || data == NULL || sz < 0)
+        return BAD_FUNC_ARG;
+
+#ifdef HAVE_ERRNO_H
+    errno = 0;
+#endif
+
+    ret = SendData(ssl, data, sz);
+
+    WOLFSSL_LEAVE("SSL_write()", ret);
+
+    if (ret < 0)
+        return SSL_FATAL_ERROR;
+    else
+        return ret;
+}
+
+
+static int wolfSSL_read_internal(WOLFSSL* ssl, void* data, int sz, int peek)
+{
+    int ret;
+
+    WOLFSSL_ENTER("wolfSSL_read_internal()");
+
+    if (ssl == NULL || data == NULL || sz < 0)
+        return BAD_FUNC_ARG;
+
+#ifdef HAVE_ERRNO_H
+        errno = 0;
+#endif
+#ifdef WOLFSSL_DTLS
+    if (ssl->options.dtls)
+        ssl->dtls_expected_rx = max(sz + 100, MAX_MTU);
+#endif
+
+#ifdef HAVE_MAX_FRAGMENT
+    ret = ReceiveData(ssl, (byte*)data,
+                     min(sz, min(ssl->max_fragment, OUTPUT_RECORD_SIZE)), peek);
+#else
+    ret = ReceiveData(ssl, (byte*)data, min(sz, OUTPUT_RECORD_SIZE), peek);
+#endif
+
+    WOLFSSL_LEAVE("wolfSSL_read_internal()", ret);
+
+    if (ret < 0)
+        return SSL_FATAL_ERROR;
+    else
+        return ret;
+}
+
+
+int wolfSSL_peek(WOLFSSL* ssl, void* data, int sz)
+{
+    WOLFSSL_ENTER("wolfSSL_peek()");
+
+    return wolfSSL_read_internal(ssl, data, sz, TRUE);
+}
+
+
+int wolfSSL_read(WOLFSSL* ssl, void* data, int sz)
+{
+    WOLFSSL_ENTER("wolfSSL_read()");
+
+    return wolfSSL_read_internal(ssl, data, sz, FALSE);
+}
+
+
+#ifdef HAVE_CAVIUM
+
+/* let's use cavium, SSL_SUCCESS on ok */
+int wolfSSL_UseCavium(WOLFSSL* ssl, int devId)
+{
+    if (ssl == NULL)
+        return BAD_FUNC_ARG;
+
+    ssl->devId = devId;
+
+    return SSL_SUCCESS;
+}
+
+
+/* let's use cavium, SSL_SUCCESS on ok */
+int wolfSSL_CTX_UseCavium(WOLFSSL_CTX* ctx, int devId)
+{
+    if (ctx == NULL)
+        return BAD_FUNC_ARG;
+
+    ctx->devId = devId;
+
+    return SSL_SUCCESS;
+}
+
+
+#endif /* HAVE_CAVIUM */
+
+#ifdef HAVE_SNI
+
+int wolfSSL_UseSNI(WOLFSSL* ssl, byte type, const void* data, word16 size)
+{
+    if (ssl == NULL)
+        return BAD_FUNC_ARG;
+
+    return TLSX_UseSNI(&ssl->extensions, type, data, size);
+}
+
+int wolfSSL_CTX_UseSNI(WOLFSSL_CTX* ctx, byte type, const void* data, word16 size)
+{
+    if (ctx == NULL)
+        return BAD_FUNC_ARG;
+
+    return TLSX_UseSNI(&ctx->extensions, type, data, size);
+}
+
+#ifndef NO_WOLFSSL_SERVER
+
+void wolfSSL_SNI_SetOptions(WOLFSSL* ssl, byte type, byte options)
+{
+    if (ssl && ssl->extensions)
+        TLSX_SNI_SetOptions(ssl->extensions, type, options);
+}
+
+void wolfSSL_CTX_SNI_SetOptions(WOLFSSL_CTX* ctx, byte type, byte options)
+{
+    if (ctx && ctx->extensions)
+        TLSX_SNI_SetOptions(ctx->extensions, type, options);
+}
+
+byte wolfSSL_SNI_Status(WOLFSSL* ssl, byte type)
+{
+    return TLSX_SNI_Status(ssl ? ssl->extensions : NULL, type);
+}
+
+word16 wolfSSL_SNI_GetRequest(WOLFSSL* ssl, byte type, void** data)
+{
+    if (data)
+        *data = NULL;
+
+    if (ssl && ssl->extensions)
+        return TLSX_SNI_GetRequest(ssl->extensions, type, data);
+
+    return 0;
+}
+
+int wolfSSL_SNI_GetFromBuffer(const byte* clientHello, word32 helloSz, byte type,
+                                                     byte* sni, word32* inOutSz)
+{
+    if (clientHello && helloSz > 0 && sni && inOutSz && *inOutSz > 0)
+        return TLSX_SNI_GetFromBuffer(clientHello, helloSz, type, sni, inOutSz);
+
+    return BAD_FUNC_ARG;
+}
+
+#endif /* NO_WOLFSSL_SERVER */
+
+#endif /* HAVE_SNI */
+
+
+#ifdef HAVE_MAX_FRAGMENT
+#ifndef NO_WOLFSSL_CLIENT
+int wolfSSL_UseMaxFragment(WOLFSSL* ssl, byte mfl)
+{
+    if (ssl == NULL)
+        return BAD_FUNC_ARG;
+
+    return TLSX_UseMaxFragment(&ssl->extensions, mfl);
+}
+
+int wolfSSL_CTX_UseMaxFragment(WOLFSSL_CTX* ctx, byte mfl)
+{
+    if (ctx == NULL)
+        return BAD_FUNC_ARG;
+
+    return TLSX_UseMaxFragment(&ctx->extensions, mfl);
+}
+#endif /* NO_WOLFSSL_CLIENT */
+#endif /* HAVE_MAX_FRAGMENT */
+
+#ifdef HAVE_TRUNCATED_HMAC
+#ifndef NO_WOLFSSL_CLIENT
+int wolfSSL_UseTruncatedHMAC(WOLFSSL* ssl)
+{
+    if (ssl == NULL)
+        return BAD_FUNC_ARG;
+
+    return TLSX_UseTruncatedHMAC(&ssl->extensions);
+}
+
+int wolfSSL_CTX_UseTruncatedHMAC(WOLFSSL_CTX* ctx)
+{
+    if (ctx == NULL)
+        return BAD_FUNC_ARG;
+
+    return TLSX_UseTruncatedHMAC(&ctx->extensions);
+}
+#endif /* NO_WOLFSSL_CLIENT */
+#endif /* HAVE_TRUNCATED_HMAC */
+
+/* Elliptic Curves */
+#ifdef HAVE_SUPPORTED_CURVES
+#ifndef NO_WOLFSSL_CLIENT
+
+int wolfSSL_UseSupportedCurve(WOLFSSL* ssl, word16 name)
+{
+    if (ssl == NULL)
+        return BAD_FUNC_ARG;
+
+    switch (name) {
+        case WOLFSSL_ECC_SECP160R1:
+        case WOLFSSL_ECC_SECP192R1:
+        case WOLFSSL_ECC_SECP224R1:
+        case WOLFSSL_ECC_SECP256R1:
+        case WOLFSSL_ECC_SECP384R1:
+        case WOLFSSL_ECC_SECP521R1:
+            break;
+
+        default:
+            return BAD_FUNC_ARG;
+    }
+
+    return TLSX_UseSupportedCurve(&ssl->extensions, name);
+}
+
+int wolfSSL_CTX_UseSupportedCurve(WOLFSSL_CTX* ctx, word16 name)
+{
+    if (ctx == NULL)
+        return BAD_FUNC_ARG;
+
+    switch (name) {
+        case WOLFSSL_ECC_SECP160R1:
+        case WOLFSSL_ECC_SECP192R1:
+        case WOLFSSL_ECC_SECP224R1:
+        case WOLFSSL_ECC_SECP256R1:
+        case WOLFSSL_ECC_SECP384R1:
+        case WOLFSSL_ECC_SECP521R1:
+            break;
+
+        default:
+            return BAD_FUNC_ARG;
+    }
+
+    return TLSX_UseSupportedCurve(&ctx->extensions, name);
+}
+
+#endif /* NO_WOLFSSL_CLIENT */
+#endif /* HAVE_SUPPORTED_CURVES */
+
+/* Secure Renegotiation */
+#ifdef HAVE_SECURE_RENEGOTIATION
+
+/* user is forcing ability to use secure renegotiation, we discourage it */
+int wolfSSL_UseSecureRenegotiation(WOLFSSL* ssl)
+{
+    int ret = BAD_FUNC_ARG;
+
+    if (ssl)
+        ret = TLSX_UseSecureRenegotiation(&ssl->extensions);
+
+    if (ret == SSL_SUCCESS) {
+        TLSX* extension = TLSX_Find(ssl->extensions, SECURE_RENEGOTIATION);
+        
+        if (extension)
+            ssl->secure_renegotiation = (SecureRenegotiation*)extension->data;
+    }
+
+    return ret;
+}
+
+
+/* do a secure renegotiation handshake, user forced, we discourage */
+int wolfSSL_Rehandshake(WOLFSSL* ssl)
+{
+    int ret;
+
+    if (ssl == NULL)
+        return BAD_FUNC_ARG;
+
+    if (ssl->secure_renegotiation == NULL) {
+        WOLFSSL_MSG("Secure Renegotiation not forced on by user");
+        return SECURE_RENEGOTIATION_E;
+    }
+
+    if (ssl->secure_renegotiation->enabled == 0) {
+        WOLFSSL_MSG("Secure Renegotiation not enabled at extension level");
+        return SECURE_RENEGOTIATION_E;
+    }
+
+    if (ssl->options.handShakeState != HANDSHAKE_DONE) {
+        WOLFSSL_MSG("Can't renegotiate until previous handshake complete");
+        return SECURE_RENEGOTIATION_E;
+    }
+
+#ifndef NO_FORCE_SCR_SAME_SUITE
+    /* force same suite */
+    if (ssl->suites) {
+        ssl->suites->suiteSz = SUITE_LEN;
+        ssl->suites->suites[0] = ssl->options.cipherSuite0;
+        ssl->suites->suites[1] = ssl->options.cipherSuite;
+    }
+#endif
+
+    /* reset handshake states */
+    ssl->options.serverState = NULL_STATE;
+    ssl->options.clientState = NULL_STATE;
+    ssl->options.connectState  = CONNECT_BEGIN;
+    ssl->options.acceptState   = ACCEPT_BEGIN;
+    ssl->options.handShakeState = NULL_STATE;
+    ssl->options.processReply  = 0;  /* TODO, move states in internal.h */
+
+    XMEMSET(&ssl->msgsReceived, 0, sizeof(ssl->msgsReceived));
+
+    ssl->secure_renegotiation->cache_status = SCR_CACHE_NEEDED;
+
+#ifndef NO_OLD_TLS
+#ifndef NO_MD5
+    wc_InitMd5(&ssl->hsHashes->hashMd5);
+#endif
+#ifndef NO_SHA
+    ret = wc_InitSha(&ssl->hsHashes->hashSha);
+    if (ret !=0)
+        return ret;
+#endif
+#endif /* NO_OLD_TLS */
+#ifndef NO_SHA256
+    ret = wc_InitSha256(&ssl->hsHashes->hashSha256);
+    if (ret !=0)
+        return ret;
+#endif
+#ifdef WOLFSSL_SHA384
+    ret = wc_InitSha384(&ssl->hsHashes->hashSha384);
+    if (ret !=0)
+        return ret;
+#endif
+#ifdef WOLFSSL_SHA512
+    ret = wc_InitSha512(&ssl->hsHashes->hashSha512);
+    if (ret !=0)
+        return ret;
+#endif
+
+    ret = wolfSSL_negotiate(ssl);
+    return ret;
+}
+
+#endif /* HAVE_SECURE_RENEGOTIATION */
+
+/* Session Ticket */
+#if !defined(NO_WOLFSSL_SERVER) && defined(HAVE_SESSION_TICKET)
+/* SSL_SUCCESS on ok */
+int wolfSSL_CTX_set_TicketEncCb(WOLFSSL_CTX* ctx, SessionTicketEncCb cb)
+{
+    if (ctx == NULL)
+        return BAD_FUNC_ARG;
+
+    ctx->ticketEncCb = cb;
+
+    return SSL_SUCCESS;
+}
+
+/* set hint interval, SSL_SUCCESS on ok */
+int wolfSSL_CTX_set_TicketHint(WOLFSSL_CTX* ctx, int hint)
+{
+    if (ctx == NULL)
+        return BAD_FUNC_ARG;
+
+    ctx->ticketHint = hint;
+
+    return SSL_SUCCESS;
+}
+
+/* set user context, SSL_SUCCESS on ok */
+int wolfSSL_CTX_set_TicketEncCtx(WOLFSSL_CTX* ctx, void* userCtx)
+{
+    if (ctx == NULL)
+        return BAD_FUNC_ARG;
+
+    ctx->ticketEncCtx = userCtx;
+
+    return SSL_SUCCESS;
+}
+
+#endif /* !defined(NO_WOLFSSL_CLIENT) && defined(HAVE_SESSION_TICKET) */
+
+/* Session Ticket */
+#if !defined(NO_WOLFSSL_CLIENT) && defined(HAVE_SESSION_TICKET)
+int wolfSSL_UseSessionTicket(WOLFSSL* ssl)
+{
+    if (ssl == NULL)
+        return BAD_FUNC_ARG;
+
+    return TLSX_UseSessionTicket(&ssl->extensions, NULL);
+}
+
+int wolfSSL_CTX_UseSessionTicket(WOLFSSL_CTX* ctx)
+{
+    if (ctx == NULL)
+        return BAD_FUNC_ARG;
+
+    return TLSX_UseSessionTicket(&ctx->extensions, NULL);
+}
+
+WOLFSSL_API int wolfSSL_get_SessionTicket(WOLFSSL* ssl, byte* buf, word32* bufSz)
+{
+    if (ssl == NULL || buf == NULL || bufSz == NULL || *bufSz == 0)
+        return BAD_FUNC_ARG;
+
+    if (ssl->session.ticketLen <= *bufSz) {
+        XMEMCPY(buf, ssl->session.ticket, ssl->session.ticketLen);
+        *bufSz = ssl->session.ticketLen;
+    }
+    else
+        *bufSz = 0;
+
+    return SSL_SUCCESS;
+}
+
+WOLFSSL_API int wolfSSL_set_SessionTicket(WOLFSSL* ssl, byte* buf, word32 bufSz)
+{
+    if (ssl == NULL || (buf == NULL && bufSz > 0))
+        return BAD_FUNC_ARG;
+
+    if (bufSz > 0)
+        XMEMCPY(ssl->session.ticket, buf, bufSz);
+    ssl->session.ticketLen = (word16)bufSz;
+
+    return SSL_SUCCESS;
+}
+
+
+WOLFSSL_API int wolfSSL_set_SessionTicket_cb(WOLFSSL* ssl,
+                                            CallbackSessionTicket cb, void* ctx)
+{
+    if (ssl == NULL)
+        return BAD_FUNC_ARG;
+
+    ssl->session_ticket_cb = cb;
+    ssl->session_ticket_ctx = ctx;
+
+    return SSL_SUCCESS;
+}
+#endif
+
+#ifndef WOLFSSL_LEANPSK
+
+int wolfSSL_send(WOLFSSL* ssl, const void* data, int sz, int flags)
+{
+    int ret;
+    int oldFlags;
+
+    WOLFSSL_ENTER("wolfSSL_send()");
+
+    if (ssl == NULL || data == NULL || sz < 0)
+        return BAD_FUNC_ARG;
+
+    oldFlags = ssl->wflags;
+
+    ssl->wflags = flags;
+    ret = wolfSSL_write(ssl, data, sz);
+    ssl->wflags = oldFlags;
+
+    WOLFSSL_LEAVE("wolfSSL_send()", ret);
+
+    return ret;
+}
+
+
+int wolfSSL_recv(WOLFSSL* ssl, void* data, int sz, int flags)
+{
+    int ret;
+    int oldFlags;
+
+    WOLFSSL_ENTER("wolfSSL_recv()");
+
+    if (ssl == NULL || data == NULL || sz < 0)
+        return BAD_FUNC_ARG;
+
+    oldFlags = ssl->rflags;
+
+    ssl->rflags = flags;
+    ret = wolfSSL_read(ssl, data, sz);
+    ssl->rflags = oldFlags;
+
+    WOLFSSL_LEAVE("wolfSSL_recv()", ret);
+
+    return ret;
+}
+#endif
+
+
+/* SSL_SUCCESS on ok */
+int wolfSSL_shutdown(WOLFSSL* ssl)
+{
+    int  ret = SSL_FATAL_ERROR;
+    byte tmp;
+    WOLFSSL_ENTER("SSL_shutdown()");
+
+    if (ssl == NULL)
+        return SSL_FATAL_ERROR;
+
+    if (ssl->options.quietShutdown) {
+        WOLFSSL_MSG("quiet shutdown, no close notify sent");
+        return SSL_SUCCESS;
+    }
+
+    /* try to send close notify, not an error if can't */
+    if (!ssl->options.isClosed && !ssl->options.connReset &&
+                                  !ssl->options.sentNotify) {
+        ssl->error = SendAlert(ssl, alert_warning, close_notify);
+        if (ssl->error < 0) {
+            WOLFSSL_ERROR(ssl->error);
+            return SSL_FATAL_ERROR;
+        }
+        ssl->options.sentNotify = 1;  /* don't send close_notify twice */
+        if (ssl->options.closeNotify)
+            ret = SSL_SUCCESS;
+        else
+            ret = SSL_SHUTDOWN_NOT_DONE;
+
+        WOLFSSL_LEAVE("SSL_shutdown()", ret);
+        return ret;
+    }
+
+    /* call wolfSSL_shutdown again for bidirectional shudown */
+    if (ssl->options.sentNotify && !ssl->options.closeNotify) {
+        ret = wolfSSL_read(ssl, &tmp, 0);
+        if (ret < 0) {
+            WOLFSSL_ERROR(ssl->error);
+            ret = SSL_FATAL_ERROR;
+        } else if (ssl->options.closeNotify) {
+            ssl->error = SSL_ERROR_SYSCALL;   /* simulate OpenSSL behavior */
+            ret = SSL_SUCCESS;
+        }
+    }
+
+    WOLFSSL_LEAVE("SSL_shutdown()", ret);
+
+    return ret;
+}
+
+
+int wolfSSL_get_error(WOLFSSL* ssl, int ret)
+{
+    WOLFSSL_ENTER("SSL_get_error");
+
+    if (ret > 0)
+        return SSL_ERROR_NONE;
+    if (ssl == NULL)
+        return BAD_FUNC_ARG;
+
+    WOLFSSL_LEAVE("SSL_get_error", ssl->error);
+
+    /* make sure converted types are handled in SetErrorString() too */
+    if (ssl->error == WANT_READ)
+        return SSL_ERROR_WANT_READ;         /* convert to OpenSSL type */
+    else if (ssl->error == WANT_WRITE)
+        return SSL_ERROR_WANT_WRITE;        /* convert to OpenSSL type */
+    else if (ssl->error == ZERO_RETURN)
+        return SSL_ERROR_ZERO_RETURN;       /* convert to OpenSSL type */
+    return ssl->error;
+}
+
+
+/* retrive alert history, SSL_SUCCESS on ok */
+int wolfSSL_get_alert_history(WOLFSSL* ssl, WOLFSSL_ALERT_HISTORY *h)
+{
+    if (ssl && h) {
+        *h = ssl->alert_history;
+    }
+    return SSL_SUCCESS;
+}
+
+
+/* return TRUE if current error is want read */
+int wolfSSL_want_read(WOLFSSL* ssl)
+{
+    WOLFSSL_ENTER("SSL_want_read");
+    if (ssl->error == WANT_READ)
+        return 1;
+
+    return 0;
+}
+
+
+/* return TRUE if current error is want write */
+int wolfSSL_want_write(WOLFSSL* ssl)
+{
+    WOLFSSL_ENTER("SSL_want_write");
+    if (ssl->error == WANT_WRITE)
+        return 1;
+
+    return 0;
+}
+
+
+char* wolfSSL_ERR_error_string(unsigned long errNumber, char* data)
+{
+    static const char* msg = "Please supply a buffer for error string";
+
+    WOLFSSL_ENTER("ERR_error_string");
+    if (data) {
+        SetErrorString((int)errNumber, data);
+        return data;
+    }
+
+    return (char*)msg;
+}
+
+
+void wolfSSL_ERR_error_string_n(unsigned long e, char* buf, unsigned long len)
+{
+    WOLFSSL_ENTER("wolfSSL_ERR_error_string_n");
+    if (len >= WOLFSSL_MAX_ERROR_SZ)
+        wolfSSL_ERR_error_string(e, buf);
+    else {
+        char tmp[WOLFSSL_MAX_ERROR_SZ];
+
+        WOLFSSL_MSG("Error buffer too short, truncating");
+        if (len) {
+            wolfSSL_ERR_error_string(e, tmp);
+            XMEMCPY(buf, tmp, len-1);
+            buf[len-1] = '\0';
+        }
+    }
+}
+
+
+/* don't free temporary arrays at end of handshake */
+void wolfSSL_KeepArrays(WOLFSSL* ssl)
+{
+    if (ssl)
+        ssl->options.saveArrays = 1;
+}
+
+
+/* user doesn't need temporary arrays anymore, Free */
+void wolfSSL_FreeArrays(WOLFSSL* ssl)
+{
+    if (ssl && ssl->options.handShakeState == HANDSHAKE_DONE) {
+        ssl->options.saveArrays = 0;
+        FreeArrays(ssl, 1);
+    }
+}
+
+
+const byte* wolfSSL_GetMacSecret(WOLFSSL* ssl, int verify)
+{
+    if (ssl == NULL)
+        return NULL;
+
+    if ( (ssl->options.side == WOLFSSL_CLIENT_END && !verify) ||
+         (ssl->options.side == WOLFSSL_SERVER_END &&  verify) )
+        return ssl->keys.client_write_MAC_secret;
+    else
+        return ssl->keys.server_write_MAC_secret;
+}
+
+
+#ifdef ATOMIC_USER
+
+void  wolfSSL_CTX_SetMacEncryptCb(WOLFSSL_CTX* ctx, CallbackMacEncrypt cb)
+{
+    if (ctx)
+        ctx->MacEncryptCb = cb;
+}
+
+
+void  wolfSSL_SetMacEncryptCtx(WOLFSSL* ssl, void *ctx)
+{
+    if (ssl)
+        ssl->MacEncryptCtx = ctx;
+}
+
+
+void* wolfSSL_GetMacEncryptCtx(WOLFSSL* ssl)
+{
+    if (ssl)
+        return ssl->MacEncryptCtx;
+
+    return NULL;
+}
+
+
+void  wolfSSL_CTX_SetDecryptVerifyCb(WOLFSSL_CTX* ctx, CallbackDecryptVerify cb)
+{
+    if (ctx)
+        ctx->DecryptVerifyCb = cb;
+}
+
+
+void  wolfSSL_SetDecryptVerifyCtx(WOLFSSL* ssl, void *ctx)
+{
+    if (ssl)
+        ssl->DecryptVerifyCtx = ctx;
+}
+
+
+void* wolfSSL_GetDecryptVerifyCtx(WOLFSSL* ssl)
+{
+    if (ssl)
+        return ssl->DecryptVerifyCtx;
+
+    return NULL;
+}
+
+
+const byte* wolfSSL_GetClientWriteKey(WOLFSSL* ssl)
+{
+    if (ssl)
+        return ssl->keys.client_write_key;
+
+    return NULL;
+}
+
+
+const byte* wolfSSL_GetClientWriteIV(WOLFSSL* ssl)
+{
+    if (ssl)
+        return ssl->keys.client_write_IV;
+
+    return NULL;
+}
+
+
+const byte* wolfSSL_GetServerWriteKey(WOLFSSL* ssl)
+{
+    if (ssl)
+        return ssl->keys.server_write_key;
+
+    return NULL;
+}
+
+
+const byte* wolfSSL_GetServerWriteIV(WOLFSSL* ssl)
+{
+    if (ssl)
+        return ssl->keys.server_write_IV;
+
+    return NULL;
+}
+
+
+int wolfSSL_GetKeySize(WOLFSSL* ssl)
+{
+    if (ssl)
+        return ssl->specs.key_size;
+
+    return BAD_FUNC_ARG;
+}
+
+
+int wolfSSL_GetIVSize(WOLFSSL* ssl)
+{
+    if (ssl)
+        return ssl->specs.iv_size;
+
+    return BAD_FUNC_ARG;
+}
+
+
+int wolfSSL_GetBulkCipher(WOLFSSL* ssl)
+{
+    if (ssl)
+        return ssl->specs.bulk_cipher_algorithm;
+
+    return BAD_FUNC_ARG;
+}
+
+
+int wolfSSL_GetCipherType(WOLFSSL* ssl)
+{
+    if (ssl == NULL)
+        return BAD_FUNC_ARG;
+
+    if (ssl->specs.cipher_type == block)
+        return WOLFSSL_BLOCK_TYPE;
+    if (ssl->specs.cipher_type == stream)
+        return WOLFSSL_STREAM_TYPE;
+    if (ssl->specs.cipher_type == aead)
+        return WOLFSSL_AEAD_TYPE;
+
+    return -1;
+}
+
+
+int wolfSSL_GetCipherBlockSize(WOLFSSL* ssl)
+{
+    if (ssl == NULL)
+        return BAD_FUNC_ARG;
+
+    return ssl->specs.block_size;
+}
+
+
+int wolfSSL_GetAeadMacSize(WOLFSSL* ssl)
+{
+    if (ssl == NULL)
+        return BAD_FUNC_ARG;
+
+    return ssl->specs.aead_mac_size;
+}
+
+
+int wolfSSL_IsTLSv1_1(WOLFSSL* ssl)
+{
+    if (ssl == NULL)
+        return BAD_FUNC_ARG;
+
+    if (ssl->options.tls1_1)
+        return 1;
+
+    return 0;
+}
+
+
+int wolfSSL_GetSide(WOLFSSL* ssl)
+{
+    if (ssl)
+        return ssl->options.side;
+
+    return BAD_FUNC_ARG;
+}
+
+
+int wolfSSL_GetHmacSize(WOLFSSL* ssl)
+{
+    /* AEAD ciphers don't have HMAC keys */
+    if (ssl)
+        return (ssl->specs.cipher_type != aead) ? ssl->specs.hash_size : 0;
+
+    return BAD_FUNC_ARG;
+}
+
+#endif /* ATOMIC_USER */
+
+#ifndef NO_CERTS
+
+WOLFSSL_CERT_MANAGER* wolfSSL_CertManagerNew(void)
+{
+    WOLFSSL_CERT_MANAGER* cm = NULL;
+
+    WOLFSSL_ENTER("wolfSSL_CertManagerNew");
+
+    cm = (WOLFSSL_CERT_MANAGER*) XMALLOC(sizeof(WOLFSSL_CERT_MANAGER), 0,
+                                        DYNAMIC_TYPE_CERT_MANAGER);
+    if (cm) {
+        XMEMSET(cm, 0, sizeof(WOLFSSL_CERT_MANAGER));
+
+        if (InitMutex(&cm->caLock) != 0) {
+            WOLFSSL_MSG("Bad mutex init");
+            wolfSSL_CertManagerFree(cm);
+            return NULL;
+        }
+    }
+
+    return cm;
+}
+
+
+void wolfSSL_CertManagerFree(WOLFSSL_CERT_MANAGER* cm)
+{
+    WOLFSSL_ENTER("wolfSSL_CertManagerFree");
+
+    if (cm) {
+        #ifdef HAVE_CRL
+            if (cm->crl)
+                FreeCRL(cm->crl, 1);
+        #endif
+        #ifdef HAVE_OCSP
+            if (cm->ocsp)
+                FreeOCSP(cm->ocsp, 1);
+        #endif
+        FreeSignerTable(cm->caTable, CA_TABLE_SIZE, NULL);
+        FreeMutex(&cm->caLock);
+        XFREE(cm, NULL, DYNAMIC_TYPE_CERT_MANAGER);
+    }
+
+}
+
+
+/* Unload the CA signer list */
+int wolfSSL_CertManagerUnloadCAs(WOLFSSL_CERT_MANAGER* cm)
+{
+    WOLFSSL_ENTER("wolfSSL_CertManagerUnloadCAs");
+
+    if (cm == NULL)
+        return BAD_FUNC_ARG;
+
+    if (LockMutex(&cm->caLock) != 0)
+        return BAD_MUTEX_E;
+
+    FreeSignerTable(cm->caTable, CA_TABLE_SIZE, NULL);
+
+    UnLockMutex(&cm->caLock);
+
+
+    return SSL_SUCCESS;
+}
+
+
+/* Return bytes written to buff or < 0 for error */
+int wolfSSL_CertPemToDer(const unsigned char* pem, int pemSz,
+                        unsigned char* buff, int buffSz,
+                        int type)
+{
+    int            eccKey = 0;
+    int            ret;
+    buffer         der;
+#ifdef WOLFSSL_SMALL_STACK
+    EncryptedInfo* info = NULL;
+#else
+    EncryptedInfo  info[1];
+#endif
+
+    WOLFSSL_ENTER("wolfSSL_CertPemToDer");
+
+    if (pem == NULL || buff == NULL || buffSz <= 0) {
+        WOLFSSL_MSG("Bad pem der args");
+        return BAD_FUNC_ARG;
+    }
+
+    if (type != CERT_TYPE && type != CA_TYPE && type != CERTREQ_TYPE) {
+        WOLFSSL_MSG("Bad cert type");
+        return BAD_FUNC_ARG;
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    info = (EncryptedInfo*)XMALLOC(sizeof(EncryptedInfo), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+    if (info == NULL)
+        return MEMORY_E;
+#endif
+
+    info->set      = 0;
+    info->ctx      = NULL;
+    info->consumed = 0;
+    der.buffer     = NULL;
+
+    ret = PemToDer(pem, pemSz, type, &der, NULL, info, &eccKey);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(info, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    if (ret < 0) {
+        WOLFSSL_MSG("Bad Pem To Der");
+    }
+    else {
+        if (der.length <= (word32)buffSz) {
+            XMEMCPY(buff, der.buffer, der.length);
+            ret = der.length;
+        }
+        else {
+            WOLFSSL_MSG("Bad der length");
+            ret = BAD_FUNC_ARG;
+        }
+    }
+
+    XFREE(der.buffer, NULL, DYNAMIC_TYPE_KEY);
+
+    return ret;
+}
+
+
+#if defined(OPENSSL_EXTRA) || defined(HAVE_WEBSERVER)
+
+/* our KeyPemToDer password callback, password in userData */
+static INLINE int OurPasswordCb(char* passwd, int sz, int rw, void* userdata)
+{
+    (void)rw;
+
+    if (userdata == NULL)
+        return 0;
+
+    XSTRNCPY(passwd, (char*)userdata, sz);
+    return min((word32)sz, (word32)XSTRLEN((char*)userdata));
+}
+
+#endif /* OPENSSL_EXTRA || HAVE_WEBSERVER */
+
+
+/* Return bytes written to buff or < 0 for error */
+int wolfSSL_KeyPemToDer(const unsigned char* pem, int pemSz, unsigned char* buff,
+                       int buffSz, const char* pass)
+{
+    int            eccKey = 0;
+    int            ret;
+    buffer         der;
+#ifdef WOLFSSL_SMALL_STACK
+    EncryptedInfo* info = NULL;
+#else
+    EncryptedInfo  info[1];
+#endif
+
+    (void)pass;
+
+    WOLFSSL_ENTER("wolfSSL_KeyPemToDer");
+
+    if (pem == NULL || buff == NULL || buffSz <= 0) {
+        WOLFSSL_MSG("Bad pem der args");
+        return BAD_FUNC_ARG;
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    info = (EncryptedInfo*)XMALLOC(sizeof(EncryptedInfo), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+    if (info == NULL)
+        return MEMORY_E;
+#endif
+
+    info->set      = 0;
+    info->ctx      = NULL;
+    info->consumed = 0;
+    der.buffer     = NULL;
+
+#if defined(OPENSSL_EXTRA) || defined(HAVE_WEBSERVER)
+    if (pass) {
+        info->ctx = wolfSSL_CTX_new(wolfSSLv23_client_method());
+        if (info->ctx == NULL) {
+        #ifdef WOLFSSL_SMALL_STACK
+            XFREE(info, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        #endif
+            return MEMORY_E;
+        }
+
+        wolfSSL_CTX_set_default_passwd_cb(info->ctx, OurPasswordCb);
+        wolfSSL_CTX_set_default_passwd_cb_userdata(info->ctx, (void*)pass);
+    }
+#endif
+
+    ret = PemToDer(pem, pemSz, PRIVATEKEY_TYPE, &der, NULL, info, &eccKey);
+
+    if (info->ctx)
+        wolfSSL_CTX_free(info->ctx);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(info, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    if (ret < 0) {
+        WOLFSSL_MSG("Bad Pem To Der");
+    }
+    else {
+        if (der.length <= (word32)buffSz) {
+            XMEMCPY(buff, der.buffer, der.length);
+            ret = der.length;
+        }
+        else {
+            WOLFSSL_MSG("Bad der length");
+            ret = BAD_FUNC_ARG;
+        }
+    }
+
+    XFREE(der.buffer, NULL, DYNAMIC_TYPE_KEY);
+
+    return ret;
+}
+
+
+#endif /* !NO_CERTS */
+
+
+
+#if !defined(NO_FILESYSTEM) && !defined(NO_STDIO_FILESYSTEM)
+
+void wolfSSL_ERR_print_errors_fp(FILE* fp, int err)
+{
+    char data[WOLFSSL_MAX_ERROR_SZ + 1];
+
+    WOLFSSL_ENTER("wolfSSL_ERR_print_errors_fp");
+    SetErrorString(err, data);
+    fprintf(fp, "%s", data);
+}
+
+#endif
+
+
+int wolfSSL_pending(WOLFSSL* ssl)
+{
+    WOLFSSL_ENTER("SSL_pending");
+    return ssl->buffers.clearOutputBuffer.length;
+}
+
+
+#ifndef WOLFSSL_LEANPSK
+/* trun on handshake group messages for context */
+int wolfSSL_CTX_set_group_messages(WOLFSSL_CTX* ctx)
+{
+    if (ctx == NULL)
+       return BAD_FUNC_ARG;
+
+    ctx->groupMessages = 1;
+
+    return SSL_SUCCESS;
+}
+#endif
+
+
+#ifndef NO_WOLFSSL_CLIENT
+/* connect enough to get peer cert chain */
+int wolfSSL_connect_cert(WOLFSSL* ssl)
+{
+    int  ret;
+
+    if (ssl == NULL)
+        return SSL_FAILURE;
+
+    ssl->options.certOnly = 1;
+    ret = wolfSSL_connect(ssl);
+    ssl->options.certOnly   = 0;
+
+    return ret;
+}
+#endif
+
+
+#ifndef WOLFSSL_LEANPSK
+/* trun on handshake group messages for ssl object */
+int wolfSSL_set_group_messages(WOLFSSL* ssl)
+{
+    if (ssl == NULL)
+       return BAD_FUNC_ARG;
+
+    ssl->options.groupMessages = 1;
+
+    return SSL_SUCCESS;
+}
+
+
+/* make minVersion the internal equivilant SSL version */
+static int SetMinVersionHelper(byte* minVersion, int version)
+{
+    switch (version) {
+#ifndef NO_OLD_TLS
+        case WOLFSSL_SSLV3:
+            *minVersion = SSLv3_MINOR;
+            break;
+#endif
+
+#ifndef NO_TLS
+    #ifndef NO_OLD_TLS
+        case WOLFSSL_TLSV1:
+            *minVersion = TLSv1_MINOR;
+            break;
+
+        case WOLFSSL_TLSV1_1:
+            *minVersion = TLSv1_1_MINOR;
+            break;
+    #endif
+        case WOLFSSL_TLSV1_2:
+            *minVersion = TLSv1_2_MINOR;
+            break;
+#endif
+
+        default:
+            WOLFSSL_MSG("Bad function argument");
+            return BAD_FUNC_ARG;
+    }
+
+    return SSL_SUCCESS;
+}
+
+
+/* Set minimum downgrade version allowed, SSL_SUCCESS on ok */
+int wolfSSL_CTX_SetMinVersion(WOLFSSL_CTX* ctx, int version)
+{
+    WOLFSSL_ENTER("wolfSSL_CTX_SetMinVersion");
+
+    if (ctx == NULL) {
+        WOLFSSL_MSG("Bad function argument");
+        return BAD_FUNC_ARG;
+    }
+
+    return SetMinVersionHelper(&ctx->minDowngrade, version);
+}
+
+
+/* Set minimum downgrade version allowed, SSL_SUCCESS on ok */
+int wolfSSL_SetMinVersion(WOLFSSL* ssl, int version)
+{
+    WOLFSSL_ENTER("wolfSSL_SetMinVersion");
+
+    if (ssl == NULL) {
+        WOLFSSL_MSG("Bad function argument");
+        return BAD_FUNC_ARG;
+    }
+
+    return SetMinVersionHelper(&ssl->options.minDowngrade, version);
+}
+
+
+int wolfSSL_SetVersion(WOLFSSL* ssl, int version)
+{
+    byte haveRSA = 1;
+    byte havePSK = 0;
+
+    WOLFSSL_ENTER("wolfSSL_SetVersion");
+
+    if (ssl == NULL) {
+        WOLFSSL_MSG("Bad function argument");
+        return BAD_FUNC_ARG;
+    }
+
+    switch (version) {
+#ifndef NO_OLD_TLS
+        case WOLFSSL_SSLV3:
+            ssl->version = MakeSSLv3();
+            break;
+#endif
+
+#ifndef NO_TLS
+    #ifndef NO_OLD_TLS
+        case WOLFSSL_TLSV1:
+            ssl->version = MakeTLSv1();
+            break;
+
+        case WOLFSSL_TLSV1_1:
+            ssl->version = MakeTLSv1_1();
+            break;
+    #endif
+        case WOLFSSL_TLSV1_2:
+            ssl->version = MakeTLSv1_2();
+            break;
+#endif
+
+        default:
+            WOLFSSL_MSG("Bad function argument");
+            return BAD_FUNC_ARG;
+    }
+
+    #ifdef NO_RSA
+        haveRSA = 0;
+    #endif
+    #ifndef NO_PSK
+        havePSK = ssl->options.havePSK;
+    #endif
+
+    InitSuites(ssl->suites, ssl->version, haveRSA, havePSK, ssl->options.haveDH,
+                ssl->options.haveNTRU, ssl->options.haveECDSAsig,
+                ssl->options.haveStaticECC, ssl->options.side);
+
+    return SSL_SUCCESS;
+}
+#endif /* !leanpsk */
+
+
+#if !defined(NO_CERTS) || !defined(NO_SESSION_CACHE)
+
+/* Make a work from the front of random hash */
+static INLINE word32 MakeWordFromHash(const byte* hashID)
+{
+    return (hashID[0] << 24) | (hashID[1] << 16) | (hashID[2] <<  8) |
+            hashID[3];
+}
+
+#endif /* !NO_CERTS || !NO_SESSION_CACHE */
+
+
+#ifndef NO_CERTS
+
+/* hash is the SHA digest of name, just use first 32 bits as hash */
+static INLINE word32 HashSigner(const byte* hash)
+{
+    return MakeWordFromHash(hash) % CA_TABLE_SIZE;
+}
+
+
+/* does CA already exist on signer list */
+int AlreadySigner(WOLFSSL_CERT_MANAGER* cm, byte* hash)
+{
+    Signer* signers;
+    int     ret = 0;
+    word32  row = HashSigner(hash);
+
+    if (LockMutex(&cm->caLock) != 0)
+        return  ret;
+    signers = cm->caTable[row];
+    while (signers) {
+        byte* subjectHash;
+        #ifndef NO_SKID
+            subjectHash = signers->subjectKeyIdHash;
+        #else
+            subjectHash = signers->subjectNameHash;
+        #endif
+        if (XMEMCMP(hash, subjectHash, SIGNER_DIGEST_SIZE) == 0) {
+            ret = 1;
+            break;
+        }
+        signers = signers->next;
+    }
+    UnLockMutex(&cm->caLock);
+
+    return ret;
+}
+
+
+/* return CA if found, otherwise NULL */
+Signer* GetCA(void* vp, byte* hash)
+{
+    WOLFSSL_CERT_MANAGER* cm = (WOLFSSL_CERT_MANAGER*)vp;
+    Signer* ret = NULL;
+    Signer* signers;
+    word32  row = HashSigner(hash);
+
+    if (cm == NULL)
+        return NULL;
+
+    if (LockMutex(&cm->caLock) != 0)
+        return ret;
+
+    signers = cm->caTable[row];
+    while (signers) {
+        byte* subjectHash;
+        #ifndef NO_SKID
+            subjectHash = signers->subjectKeyIdHash;
+        #else
+            subjectHash = signers->subjectNameHash;
+        #endif
+        if (XMEMCMP(hash, subjectHash, SIGNER_DIGEST_SIZE) == 0) {
+            ret = signers;
+            break;
+        }
+        signers = signers->next;
+    }
+    UnLockMutex(&cm->caLock);
+
+    return ret;
+}
+
+
+#ifndef NO_SKID
+/* return CA if found, otherwise NULL. Walk through hash table. */
+Signer* GetCAByName(void* vp, byte* hash)
+{
+    WOLFSSL_CERT_MANAGER* cm = (WOLFSSL_CERT_MANAGER*)vp;
+    Signer* ret = NULL;
+    Signer* signers;
+    word32  row;
+
+    if (cm == NULL)
+        return NULL;
+
+    if (LockMutex(&cm->caLock) != 0)
+        return ret;
+
+    for (row = 0; row < CA_TABLE_SIZE && ret == NULL; row++) {
+        signers = cm->caTable[row];
+        while (signers && ret == NULL) {
+            if (XMEMCMP(hash,
+                           signers->subjectNameHash, SIGNER_DIGEST_SIZE) == 0) {
+                ret = signers;
+            }
+            signers = signers->next;
+        }
+    }
+    UnLockMutex(&cm->caLock);
+
+    return ret;
+}
+#endif
+
+
+/* owns der, internal now uses too */
+/* type flag ids from user or from chain received during verify
+   don't allow chain ones to be added w/o isCA extension */
+int AddCA(WOLFSSL_CERT_MANAGER* cm, buffer der, int type, int verify)
+{
+    int         ret;
+    Signer*     signer = 0;
+    word32      row;
+    byte*       subjectHash;
+#ifdef WOLFSSL_SMALL_STACK
+    DecodedCert* cert = NULL;
+#else
+    DecodedCert  cert[1];
+#endif
+
+    WOLFSSL_MSG("Adding a CA");
+
+#ifdef WOLFSSL_SMALL_STACK
+    cert = (DecodedCert*)XMALLOC(sizeof(DecodedCert), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+    if (cert == NULL)
+        return MEMORY_E;
+#endif
+
+    InitDecodedCert(cert, der.buffer, der.length, cm->heap);
+    ret = ParseCert(cert, CA_TYPE, verify, cm);
+    WOLFSSL_MSG("    Parsed new CA");
+
+#ifndef NO_SKID
+    subjectHash = cert->extSubjKeyId;
+#else
+    subjectHash = cert->subjectHash;
+#endif
+
+    if (ret == 0 && cert->isCA == 0 && type != WOLFSSL_USER_CA) {
+        WOLFSSL_MSG("    Can't add as CA if not actually one");
+        ret = NOT_CA_ERROR;
+    }
+#ifndef ALLOW_INVALID_CERTSIGN
+    else if (ret == 0 && cert->isCA == 1 && type != WOLFSSL_USER_CA &&
+                              (cert->extKeyUsage & KEYUSE_KEY_CERT_SIGN) == 0) {
+        /* Intermediate CA certs are required to have the keyCertSign
+        * extension set. User loaded root certs are not. */
+        WOLFSSL_MSG("    Doesn't have key usage certificate signing");
+        ret = NOT_CA_ERROR;
+    }
+#endif
+    else if (ret == 0 && AlreadySigner(cm, subjectHash)) {
+        WOLFSSL_MSG("    Already have this CA, not adding again");
+        (void)ret;
+    }
+    else if (ret == 0) {
+        /* take over signer parts */
+        signer = MakeSigner(cm->heap);
+        if (!signer)
+            ret = MEMORY_ERROR;
+        else {
+            signer->keyOID         = cert->keyOID;
+            signer->publicKey      = cert->publicKey;
+            signer->pubKeySize     = cert->pubKeySize;
+            signer->nameLen        = cert->subjectCNLen;
+            signer->name           = cert->subjectCN;
+        #ifndef IGNORE_NAME_CONSTRAINTS
+            signer->permittedNames = cert->permittedNames;
+            signer->excludedNames  = cert->excludedNames;
+        #endif
+        #ifndef NO_SKID
+            XMEMCPY(signer->subjectKeyIdHash, cert->extSubjKeyId,
+                                                            SIGNER_DIGEST_SIZE);
+        #endif
+            XMEMCPY(signer->subjectNameHash, cert->subjectHash,
+                                                            SIGNER_DIGEST_SIZE);
+            signer->keyUsage = cert->extKeyUsageSet ? cert->extKeyUsage
+                                                    : 0xFFFF;
+            signer->next    = NULL; /* If Key Usage not set, all uses valid. */
+            cert->publicKey = 0;    /* in case lock fails don't free here.   */
+            cert->subjectCN = 0;
+        #ifndef IGNORE_NAME_CONSTRAINTS
+            cert->permittedNames = NULL;
+            cert->excludedNames = NULL;
+        #endif
+
+        #ifndef NO_SKID
+            row = HashSigner(signer->subjectKeyIdHash);
+        #else
+            row = HashSigner(signer->subjectNameHash);
+        #endif
+
+            if (LockMutex(&cm->caLock) == 0) {
+                signer->next = cm->caTable[row];
+                cm->caTable[row] = signer;   /* takes ownership */
+                UnLockMutex(&cm->caLock);
+                if (cm->caCacheCallback)
+                    cm->caCacheCallback(der.buffer, (int)der.length, type);
+            }
+            else {
+                WOLFSSL_MSG("    CA Mutex Lock failed");
+                ret = BAD_MUTEX_E;
+                FreeSigner(signer, cm->heap);
+            }
+        }
+    }
+
+    WOLFSSL_MSG("    Freeing Parsed CA");
+    FreeDecodedCert(cert);
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(cert, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+    WOLFSSL_MSG("    Freeing der CA");
+    XFREE(der.buffer, cm->heap, DYNAMIC_TYPE_CA);
+    WOLFSSL_MSG("        OK Freeing der CA");
+
+    WOLFSSL_LEAVE("AddCA", ret);
+
+    return ret == 0 ? SSL_SUCCESS : ret;
+}
+
+#endif /* !NO_CERTS */
+
+
+#ifndef NO_SESSION_CACHE
+
+    /* basic config gives a cache with 33 sessions, adequate for clients and
+       embedded servers
+
+       MEDIUM_SESSION_CACHE allows 1055 sessions, adequate for servers that
+       aren't under heavy load, basically allows 200 new sessions per minute
+
+       BIG_SESSION_CACHE yields 20,027 sessions
+
+       HUGE_SESSION_CACHE yields 65,791 sessions, for servers under heavy load,
+       allows over 13,000 new sessions per minute or over 200 new sessions per
+       second
+
+       SMALL_SESSION_CACHE only stores 6 sessions, good for embedded clients
+       or systems where the default of nearly 3kB is too much RAM, this define
+       uses less than 500 bytes RAM
+
+       default SESSION_CACHE stores 33 sessions (no XXX_SESSION_CACHE defined)
+    */
+    #ifdef HUGE_SESSION_CACHE
+        #define SESSIONS_PER_ROW 11
+        #define SESSION_ROWS 5981
+    #elif defined(BIG_SESSION_CACHE)
+        #define SESSIONS_PER_ROW 7
+        #define SESSION_ROWS 2861
+    #elif defined(MEDIUM_SESSION_CACHE)
+        #define SESSIONS_PER_ROW 5
+        #define SESSION_ROWS 211
+    #elif defined(SMALL_SESSION_CACHE)
+        #define SESSIONS_PER_ROW 2
+        #define SESSION_ROWS 3
+    #else
+        #define SESSIONS_PER_ROW 3
+        #define SESSION_ROWS 11
+    #endif
+
+    typedef struct SessionRow {
+        int nextIdx;                           /* where to place next one   */
+        int totalCount;                        /* sessions ever on this row */
+        WOLFSSL_SESSION Sessions[SESSIONS_PER_ROW];
+    } SessionRow;
+
+    static SessionRow SessionCache[SESSION_ROWS];
+
+    #if defined(WOLFSSL_SESSION_STATS) && defined(WOLFSSL_PEAK_SESSIONS)
+        static word32 PeakSessions;
+    #endif
+
+    static wolfSSL_Mutex session_mutex;   /* SessionCache mutex */
+
+    #ifndef NO_CLIENT_CACHE
+
+        typedef struct ClientSession {
+            word16 serverRow;            /* SessionCache Row id */
+            word16 serverIdx;            /* SessionCache Idx (column) */
+        } ClientSession;
+
+        typedef struct ClientRow {
+            int nextIdx;                /* where to place next one   */
+            int totalCount;             /* sessions ever on this row */
+            ClientSession Clients[SESSIONS_PER_ROW];
+        } ClientRow;
+
+        static ClientRow ClientCache[SESSION_ROWS];  /* Client Cache */
+                                                     /* uses session mutex */
+    #endif  /* NO_CLIENT_CACHE */
+
+#endif /* NO_SESSION_CACHE */
+
+
+int wolfSSL_Init(void)
+{
+    int ret = SSL_SUCCESS;
+
+    WOLFSSL_ENTER("wolfSSL_Init");
+
+    if (initRefCount == 0) {
+#ifndef NO_SESSION_CACHE
+        if (InitMutex(&session_mutex) != 0)
+            ret = BAD_MUTEX_E;
+#endif
+        if (InitMutex(&count_mutex) != 0)
+            ret = BAD_MUTEX_E;
+    }
+    if (ret == SSL_SUCCESS) {
+        if (LockMutex(&count_mutex) != 0) {
+            WOLFSSL_MSG("Bad Lock Mutex count");
+            return BAD_MUTEX_E;
+        }
+        initRefCount++;
+        UnLockMutex(&count_mutex);
+    }
+
+    return ret;
+}
+
+
+#ifndef NO_CERTS
+
+static const char* BEGIN_CERT         = "-----BEGIN CERTIFICATE-----";
+static const char* END_CERT           = "-----END CERTIFICATE-----";
+static const char* BEGIN_CERT_REQ     = "-----BEGIN CERTIFICATE REQUEST-----";
+static const char* END_CERT_REQ       = "-----END CERTIFICATE REQUEST-----";
+static const char* BEGIN_DH_PARAM     = "-----BEGIN DH PARAMETERS-----";
+static const char* END_DH_PARAM       = "-----END DH PARAMETERS-----";
+static const char* BEGIN_X509_CRL     = "-----BEGIN X509 CRL-----";
+static const char* END_X509_CRL       = "-----END X509 CRL-----";
+static const char* BEGIN_RSA_PRIV     = "-----BEGIN RSA PRIVATE KEY-----";
+static const char* END_RSA_PRIV       = "-----END RSA PRIVATE KEY-----";
+static const char* BEGIN_PRIV_KEY     = "-----BEGIN PRIVATE KEY-----";
+static const char* END_PRIV_KEY       = "-----END PRIVATE KEY-----";
+static const char* BEGIN_ENC_PRIV_KEY = "-----BEGIN ENCRYPTED PRIVATE KEY-----";
+static const char* END_ENC_PRIV_KEY   = "-----END ENCRYPTED PRIVATE KEY-----";
+static const char* BEGIN_EC_PRIV      = "-----BEGIN EC PRIVATE KEY-----";
+static const char* END_EC_PRIV        = "-----END EC PRIVATE KEY-----";
+static const char* BEGIN_DSA_PRIV     = "-----BEGIN DSA PRIVATE KEY-----";
+static const char* END_DSA_PRIV       = "-----END DSA PRIVATE KEY-----";
+
+/* Remove PEM header/footer, convert to ASN1, store any encrypted data
+   info->consumed tracks of PEM bytes consumed in case multiple parts */
+int PemToDer(const unsigned char* buff, long longSz, int type,
+                  buffer* der, void* heap, EncryptedInfo* info, int* eccKey)
+{
+    const char* header      = NULL;
+    const char* footer      = NULL;
+    char*       headerEnd;
+    char*       footerEnd;
+    char*       consumedEnd;
+    char*       bufferEnd   = (char*)(buff + longSz);
+    long        neededSz;
+    int         ret         = 0;
+    int         dynamicType = 0;
+    int         sz          = (int)longSz;
+
+    switch (type) {
+        case CA_TYPE:       /* same as below */
+        case CERT_TYPE:     header= BEGIN_CERT;     footer= END_CERT;     break;
+        case CRL_TYPE:      header= BEGIN_X509_CRL; footer= END_X509_CRL; break;
+        case DH_PARAM_TYPE: header= BEGIN_DH_PARAM; footer= END_DH_PARAM; break;
+        case CERTREQ_TYPE:  header= BEGIN_CERT_REQ; footer= END_CERT_REQ; break;
+        default:            header= BEGIN_RSA_PRIV; footer= END_RSA_PRIV; break;
+    }
+    
+    switch (type) {
+        case CA_TYPE:   dynamicType = DYNAMIC_TYPE_CA;   break;
+        case CERT_TYPE: dynamicType = DYNAMIC_TYPE_CERT; break;
+        case CRL_TYPE:  dynamicType = DYNAMIC_TYPE_CRL;  break;
+        default:        dynamicType = DYNAMIC_TYPE_KEY;  break;
+    }
+
+    /* find header */
+    for (;;) {
+        headerEnd = XSTRNSTR((char*)buff, header, sz);
+        
+        if (headerEnd || type != PRIVATEKEY_TYPE) {
+            break;
+        } else if (header == BEGIN_RSA_PRIV) {
+                   header =  BEGIN_PRIV_KEY;       footer = END_PRIV_KEY;
+        } else if (header == BEGIN_PRIV_KEY) {
+                   header =  BEGIN_ENC_PRIV_KEY;   footer = END_ENC_PRIV_KEY;
+        } else if (header == BEGIN_ENC_PRIV_KEY) {
+                   header =  BEGIN_EC_PRIV;        footer = END_EC_PRIV;
+        } else if (header == BEGIN_EC_PRIV) {
+                   header =  BEGIN_DSA_PRIV;       footer = END_DSA_PRIV;
+        } else
+            break;
+    }
+
+    if (!headerEnd) {
+        WOLFSSL_MSG("Couldn't find PEM header");
+        return SSL_NO_PEM_HEADER;
+    }
+
+    headerEnd += XSTRLEN(header);
+
+    /* eat end of line */
+    if (headerEnd[0] == '\n')
+        headerEnd++;
+    else if (headerEnd[1] == '\n')
+        headerEnd += 2;
+    else
+        return SSL_BAD_FILE;
+
+    if (type == PRIVATEKEY_TYPE) {
+        if (eccKey)
+            *eccKey = header == BEGIN_EC_PRIV;      
+    }
+
+#if defined(OPENSSL_EXTRA) || defined(HAVE_WEBSERVER)
+    {
+        /* remove encrypted header if there */
+        char encHeader[] = "Proc-Type";
+        char* line = XSTRNSTR(headerEnd, encHeader, PEM_LINE_LEN);
+        if (line) {
+            char* newline;
+            char* finish;
+            char* start  = XSTRNSTR(line, "DES", PEM_LINE_LEN);
+
+            if (!start)
+                start = XSTRNSTR(line, "AES", PEM_LINE_LEN);
+
+            if (!start) return SSL_BAD_FILE;
+            if (!info)  return SSL_BAD_FILE;
+
+            finish = XSTRNSTR(start, ",", PEM_LINE_LEN);
+
+            if (start && finish && (start < finish)) {
+                newline = XSTRNSTR(finish, "\r", PEM_LINE_LEN);
+
+                XMEMCPY(info->name, start, finish - start);
+                info->name[finish - start] = 0;
+                XMEMCPY(info->iv, finish + 1, sizeof(info->iv));
+
+                if (!newline) newline = XSTRNSTR(finish, "\n", PEM_LINE_LEN);
+                if (newline && (newline > finish)) {
+                    info->ivSz = (word32)(newline - (finish + 1));
+                    info->set = 1;
+                }
+                else
+                    return SSL_BAD_FILE;
+            }
+            else
+                return SSL_BAD_FILE;
+
+            /* eat blank line */
+            while (*newline == '\r' || *newline == '\n')
+                newline++;
+            headerEnd = newline;
+        }
+    }
+#endif /* OPENSSL_EXTRA || HAVE_WEBSERVER */
+
+    /* find footer */
+    footerEnd = XSTRNSTR((char*)buff, footer, sz);
+    if (!footerEnd)
+        return SSL_BAD_FILE;
+
+    consumedEnd = footerEnd + XSTRLEN(footer);
+
+    if (consumedEnd < bufferEnd) {  /* handle no end of line on last line */
+        /* eat end of line */
+        if (consumedEnd[0] == '\n')
+            consumedEnd++;
+        else if (consumedEnd[1] == '\n')
+            consumedEnd += 2;
+        else
+            return SSL_BAD_FILE;
+    }
+
+    if (info)
+        info->consumed = (long)(consumedEnd - (char*)buff);
+
+    /* set up der buffer */
+    neededSz = (long)(footerEnd - headerEnd);
+    if (neededSz > sz || neededSz < 0)
+        return SSL_BAD_FILE;
+
+    der->buffer = (byte*)XMALLOC(neededSz, heap, dynamicType);
+    if (!der->buffer)
+        return MEMORY_ERROR;
+
+    der->length = (word32)neededSz;
+
+    if (Base64_Decode((byte*)headerEnd, (word32)neededSz, der->buffer,
+                                                              &der->length) < 0)
+        return SSL_BAD_FILE;
+
+    if (header == BEGIN_PRIV_KEY) {
+        /* pkcs8 key, convert and adjust length */
+        if ((ret = ToTraditional(der->buffer, der->length)) < 0)
+            return ret;
+
+        der->length = ret;
+        return 0;
+    }
+
+#if (defined(OPENSSL_EXTRA) || defined(HAVE_WEBSERVER)) && !defined(NO_PWDBASED)
+    if (header == BEGIN_ENC_PRIV_KEY) {
+        int   passwordSz;
+    #ifdef WOLFSSL_SMALL_STACK
+        char* password = NULL;
+    #else
+        char  password[80];
+    #endif
+
+        if (!info || !info->ctx || !info->ctx->passwd_cb)
+            return SSL_BAD_FILE;  /* no callback error */
+
+    #ifdef WOLFSSL_SMALL_STACK
+        password = (char*)XMALLOC(80, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (password == NULL)
+            return MEMORY_E;
+    #endif
+        passwordSz = info->ctx->passwd_cb(password, sizeof(password), 0,
+                                                           info->ctx->userdata);
+        /* convert and adjust length */
+        ret = ToTraditionalEnc(der->buffer, der->length, password, passwordSz);
+
+    #ifdef WOLFSSL_SMALL_STACK
+        XFREE(password, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    #endif
+
+        if (ret < 0)
+            return ret;
+
+        der->length = ret;
+        return 0;
+    }
+#endif
+
+    return 0;
+}
+
+
+/* process the buffer buff, legnth sz, into ctx of format and type
+   used tracks bytes consumed, userChain specifies a user cert chain
+   to pass during the handshake */
+static int ProcessBuffer(WOLFSSL_CTX* ctx, const unsigned char* buff,
+                         long sz, int format, int type, WOLFSSL* ssl,
+                         long* used, int userChain)
+{
+    buffer        der;        /* holds DER or RAW (for NTRU) */
+    int           ret;
+    int           dynamicType = 0;
+    int           eccKey = 0;
+    int           rsaKey = 0;
+    void*         heap = ctx ? ctx->heap : NULL;
+#ifdef WOLFSSL_SMALL_STACK
+    EncryptedInfo* info = NULL;
+#else
+    EncryptedInfo  info[1];
+#endif
+
+    (void)dynamicType;
+    (void)rsaKey;
+
+    if (used)
+        *used = sz;     /* used bytes default to sz, PEM chain may shorten*/
+
+    if (format != SSL_FILETYPE_ASN1 && format != SSL_FILETYPE_PEM
+                                    && format != SSL_FILETYPE_RAW)
+        return SSL_BAD_FILETYPE;
+
+    if (ctx == NULL && ssl == NULL)
+        return BAD_FUNC_ARG;
+
+    if (type == CA_TYPE)
+        dynamicType = DYNAMIC_TYPE_CA;
+    else if (type == CERT_TYPE)
+        dynamicType = DYNAMIC_TYPE_CERT;
+    else
+        dynamicType = DYNAMIC_TYPE_KEY;
+
+#ifdef WOLFSSL_SMALL_STACK
+    info = (EncryptedInfo*)XMALLOC(sizeof(EncryptedInfo), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+    if (info == NULL)
+        return MEMORY_E;
+#endif
+
+    info->set      = 0;
+    info->ctx      = ctx;
+    info->consumed = 0;
+    der.buffer     = 0;
+
+    if (format == SSL_FILETYPE_PEM) {
+        ret = PemToDer(buff, sz, type, &der, heap, info, &eccKey);
+        if (ret < 0) {
+        #ifdef WOLFSSL_SMALL_STACK
+            XFREE(info, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        #endif
+            XFREE(der.buffer, heap, dynamicType);
+            return ret;
+        }
+
+        if (used)
+            *used = info->consumed;
+
+        /* we may have a user cert chain, try to consume */
+        if (userChain && type == CERT_TYPE && info->consumed < sz) {
+        #ifdef WOLFSSL_SMALL_STACK
+            byte   staticBuffer[1];                 /* force heap usage */
+        #else
+            byte   staticBuffer[FILE_BUFFER_SIZE];  /* tmp chain buffer */
+        #endif
+            byte*  chainBuffer = staticBuffer;
+            byte*  shrinked    = NULL;   /* shrinked to size chainBuffer
+                                          * or staticBuffer */
+            int    dynamicBuffer = 0;
+            word32 bufferSz = sizeof(staticBuffer);
+            long   consumed = info->consumed;
+            word32 idx = 0;
+            int    gotOne = 0;
+
+            if ( (sz - consumed) > (int)bufferSz) {
+                WOLFSSL_MSG("Growing Tmp Chain Buffer");
+                bufferSz = (word32)(sz - consumed);
+                           /* will shrink to actual size */
+                chainBuffer = (byte*)XMALLOC(bufferSz, heap, DYNAMIC_TYPE_FILE);
+                if (chainBuffer == NULL) {
+                #ifdef WOLFSSL_SMALL_STACK
+                    XFREE(info, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                #endif
+                    XFREE(der.buffer, heap, dynamicType);
+                    return MEMORY_E;
+                }
+                dynamicBuffer = 1;
+            }
+
+            WOLFSSL_MSG("Processing Cert Chain");
+            while (consumed < sz) {
+                buffer part;
+                info->consumed = 0;
+                part.buffer = 0;
+
+                ret = PemToDer(buff + consumed, sz - consumed, type, &part,
+                                                           heap, info, &eccKey);
+                if (ret == 0) {
+                    gotOne = 1;
+                    if ( (idx + part.length) > bufferSz) {
+                        WOLFSSL_MSG("   Cert Chain bigger than buffer");
+                        ret = BUFFER_E;
+                    }
+                    else {
+                        c32to24(part.length, &chainBuffer[idx]);
+                        idx += CERT_HEADER_SZ;
+                        XMEMCPY(&chainBuffer[idx], part.buffer,part.length);
+                        idx += part.length;
+                        consumed  += info->consumed;
+                        if (used)
+                            *used += info->consumed;
+                    }
+                }
+
+                XFREE(part.buffer, heap, dynamicType);
+
+                if (ret == SSL_NO_PEM_HEADER && gotOne) {
+                    WOLFSSL_MSG("We got one good PEM so stuff at end ok");
+                    break;
+                }
+
+                if (ret < 0) {
+                    WOLFSSL_MSG("   Error in Cert in Chain");
+                    if (dynamicBuffer)
+                        XFREE(chainBuffer, heap, DYNAMIC_TYPE_FILE);
+                #ifdef WOLFSSL_SMALL_STACK
+                    XFREE(info, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                #endif
+                    XFREE(der.buffer, heap, dynamicType);
+                    return ret;
+                }
+                WOLFSSL_MSG("   Consumed another Cert in Chain");
+            }
+            WOLFSSL_MSG("Finished Processing Cert Chain");
+
+            /* only retain actual size used */
+            shrinked = (byte*)XMALLOC(idx, heap, dynamicType);
+            if (shrinked) {
+                if (ssl) {
+                    if (ssl->buffers.certChain.buffer &&
+                                                  ssl->buffers.weOwnCertChain) {
+                        XFREE(ssl->buffers.certChain.buffer, heap,
+                              dynamicType);
+                    }
+                    ssl->buffers.certChain.buffer = shrinked;
+                    ssl->buffers.certChain.length = idx;
+                    XMEMCPY(ssl->buffers.certChain.buffer, chainBuffer,idx);
+                    ssl->buffers.weOwnCertChain = 1;
+                } else if (ctx) {
+                    if (ctx->certChain.buffer)
+                        XFREE(ctx->certChain.buffer, heap, dynamicType);
+                    ctx->certChain.buffer = shrinked;
+                    ctx->certChain.length = idx;
+                    XMEMCPY(ctx->certChain.buffer, chainBuffer, idx);
+                }
+            }
+
+            if (dynamicBuffer)
+                XFREE(chainBuffer, heap, DYNAMIC_TYPE_FILE);
+
+            if (shrinked == NULL) {
+            #ifdef WOLFSSL_SMALL_STACK
+                XFREE(info, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            #endif
+                XFREE(der.buffer, heap, dynamicType);
+                return MEMORY_E;
+            }
+        }
+    }
+    else {  /* ASN1 (DER) or RAW (NTRU) */
+        der.buffer = (byte*) XMALLOC(sz, heap, dynamicType);
+        if (!der.buffer) {
+        #ifdef WOLFSSL_SMALL_STACK
+            XFREE(info, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        #endif
+            return MEMORY_ERROR;
+        }
+
+        XMEMCPY(der.buffer, buff, sz);
+        der.length = (word32)sz;
+    }
+
+#if defined(OPENSSL_EXTRA) || defined(HAVE_WEBSERVER)
+    if (info->set) {
+        /* decrypt */
+        int   passwordSz;
+#ifdef WOLFSSL_SMALL_STACK
+        char* password = NULL;
+        byte* key      = NULL;
+        byte* iv       = NULL;
+#else
+        char  password[80];
+        byte  key[AES_256_KEY_SIZE];
+        #ifndef NO_MD5
+        byte  iv[AES_IV_SIZE];
+        #endif
+#endif
+
+    #ifdef WOLFSSL_SMALL_STACK
+        password = (char*)XMALLOC(80, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        key      = (byte*)XMALLOC(AES_256_KEY_SIZE, NULL,
+                                                   DYNAMIC_TYPE_TMP_BUFFER);
+        iv       = (byte*)XMALLOC(AES_IV_SIZE, NULL, 
+                                                   DYNAMIC_TYPE_TMP_BUFFER);
+
+        if (password == NULL || key == NULL || iv == NULL) {
+            XFREE(password, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            XFREE(key,      NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            XFREE(iv,       NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            ret = MEMORY_E;
+        }
+        else
+    #endif
+        if (!ctx || !ctx->passwd_cb) {
+            ret = NO_PASSWORD;
+        }
+        else {
+            passwordSz = ctx->passwd_cb(password, sizeof(password), 0,
+                                                             ctx->userdata);
+
+            /* use file's salt for key derivation, hex decode first */
+            if (Base16_Decode(info->iv, info->ivSz, info->iv, &info->ivSz)
+                                                                         != 0) {
+                ret = ASN_INPUT_E;
+            }
+#ifndef NO_MD5
+            else if ((ret = EVP_BytesToKey(info->name, "MD5", info->iv,
+                           (byte*)password, passwordSz, 1, key, iv)) <= 0) {
+                /* empty */
+            }
+#endif
+#ifndef NO_DES3
+            else if (XSTRNCMP(info->name, "DES-CBC", 7) == 0) {
+                ret = wc_Des_CbcDecryptWithKey(der.buffer, der.buffer, der.length,
+                                                                 key, info->iv);
+            }
+            else if (XSTRNCMP(info->name, "DES-EDE3-CBC", 13) == 0) {
+                ret = wc_Des3_CbcDecryptWithKey(der.buffer, der.buffer, der.length,
+                                                                 key, info->iv);
+            }
+#endif
+#ifndef NO_AES
+            else if (XSTRNCMP(info->name, "AES-128-CBC", 13) == 0) {
+                ret = wc_AesCbcDecryptWithKey(der.buffer, der.buffer, der.length,
+                                               key, AES_128_KEY_SIZE, info->iv);
+            }
+            else if (XSTRNCMP(info->name, "AES-192-CBC", 13) == 0) {
+                ret = wc_AesCbcDecryptWithKey(der.buffer, der.buffer, der.length,
+                                               key, AES_192_KEY_SIZE, info->iv);
+            }
+            else if (XSTRNCMP(info->name, "AES-256-CBC", 13) == 0) {
+                ret = wc_AesCbcDecryptWithKey(der.buffer, der.buffer, der.length,
+                                               key, AES_256_KEY_SIZE, info->iv);
+            }
+#endif
+            else {
+                ret = SSL_BAD_FILE;
+            }
+        }
+
+    #ifdef WOLFSSL_SMALL_STACK
+        XFREE(password, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(key,      NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(iv,       NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    #endif
+
+        if (ret != 0) {
+        #ifdef WOLFSSL_SMALL_STACK
+            XFREE(info, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        #endif
+            XFREE(der.buffer, heap, dynamicType);
+            return ret;
+        }
+    }
+#endif /* OPENSSL_EXTRA || HAVE_WEBSERVER */
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(info, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    if (type == CA_TYPE) {
+        if (ctx == NULL) {
+            WOLFSSL_MSG("Need context for CA load");
+            XFREE(der.buffer, heap, dynamicType);
+            return BAD_FUNC_ARG;
+        }
+        return AddCA(ctx->cm, der, WOLFSSL_USER_CA, ctx->verifyPeer);
+                                                      /* takes der over */
+    }
+    else if (type == CERT_TYPE) {
+        if (ssl) {
+            if (ssl->buffers.weOwnCert && ssl->buffers.certificate.buffer)
+                XFREE(ssl->buffers.certificate.buffer, heap, dynamicType);
+            ssl->buffers.certificate = der;
+            ssl->buffers.weOwnCert = 1;
+        }
+        else if (ctx) {
+            if (ctx->certificate.buffer)
+                XFREE(ctx->certificate.buffer, heap, dynamicType);
+            ctx->certificate = der;     /* takes der over */
+        }
+    }
+    else if (type == PRIVATEKEY_TYPE) {
+        if (ssl) {
+            if (ssl->buffers.weOwnKey && ssl->buffers.key.buffer)
+                XFREE(ssl->buffers.key.buffer, heap, dynamicType);
+            ssl->buffers.key = der;
+            ssl->buffers.weOwnKey = 1;
+        }
+        else if (ctx) {
+            if (ctx->privateKey.buffer)
+                XFREE(ctx->privateKey.buffer, heap, dynamicType);
+            ctx->privateKey = der;      /* takes der over */
+        }
+    }
+    else {
+        XFREE(der.buffer, heap, dynamicType);
+        return SSL_BAD_CERTTYPE;
+    }
+
+    if (type == PRIVATEKEY_TYPE && format != SSL_FILETYPE_RAW) {
+    #ifndef NO_RSA
+        if (!eccKey) {
+            /* make sure RSA key can be used */
+            word32 idx = 0;
+        #ifdef WOLFSSL_SMALL_STACK
+            RsaKey* key = NULL;
+        #else
+            RsaKey  key[1];
+        #endif
+
+        #ifdef WOLFSSL_SMALL_STACK
+            key = (RsaKey*)XMALLOC(sizeof(RsaKey), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+            if (key == NULL)
+                return MEMORY_E;
+        #endif
+
+            ret = wc_InitRsaKey(key, 0);
+            if (ret == 0) {
+                if (wc_RsaPrivateKeyDecode(der.buffer, &idx, key, der.length) !=
+                                                                            0) {
+                #ifdef HAVE_ECC
+                    /* could have DER ECC (or pkcs8 ecc), no easy way to tell */
+                    eccKey = 1;  /* so try it out */
+                #endif
+                    if (!eccKey)
+                        ret = SSL_BAD_FILE;
+                } else {
+                    rsaKey = 1;
+                    (void)rsaKey;  /* for no ecc builds */
+                }
+            }
+
+            wc_FreeRsaKey(key);
+
+        #ifdef WOLFSSL_SMALL_STACK
+            XFREE(key, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        #endif
+
+            if (ret != 0)
+                return ret;
+        }
+    #endif
+    #ifdef HAVE_ECC
+        if (!rsaKey) {
+            /* make sure ECC key can be used */
+            word32  idx = 0;
+            ecc_key key;
+
+            wc_ecc_init(&key);
+            if (wc_EccPrivateKeyDecode(der.buffer,&idx,&key,der.length) != 0) {
+                wc_ecc_free(&key);
+                return SSL_BAD_FILE;
+            }
+            wc_ecc_free(&key);
+            eccKey = 1;
+            if (ctx)
+                ctx->haveStaticECC = 1;
+            if (ssl)
+                ssl->options.haveStaticECC = 1;
+        }
+    #endif /* HAVE_ECC */
+    }
+    else if (type == CERT_TYPE) {
+    #ifdef WOLFSSL_SMALL_STACK
+        DecodedCert* cert = NULL;
+    #else
+        DecodedCert  cert[1];
+    #endif
+
+    #ifdef WOLFSSL_SMALL_STACK
+        cert = (DecodedCert*)XMALLOC(sizeof(DecodedCert), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+        if (cert == NULL)
+            return MEMORY_E;
+    #endif
+
+        WOLFSSL_MSG("Checking cert signature type");
+        InitDecodedCert(cert, der.buffer, der.length, heap);
+
+        if (DecodeToKey(cert, 0) < 0) {
+            WOLFSSL_MSG("Decode to key failed");
+        #ifdef WOLFSSL_SMALL_STACK
+            XFREE(cert, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        #endif
+            return SSL_BAD_FILE;
+        }
+        switch (cert->signatureOID) {
+            case CTC_SHAwECDSA:
+            case CTC_SHA256wECDSA:
+            case CTC_SHA384wECDSA:
+            case CTC_SHA512wECDSA:
+                WOLFSSL_MSG("ECDSA cert signature");
+                if (ctx)
+                    ctx->haveECDSAsig = 1;
+                if (ssl)
+                    ssl->options.haveECDSAsig = 1;
+                break;
+            default:
+                WOLFSSL_MSG("Not ECDSA cert signature");
+                break;
+        }
+
+    #ifdef HAVE_ECC
+        if (ctx)
+            ctx->pkCurveOID = cert->pkCurveOID;
+        if (ssl)
+            ssl->pkCurveOID = cert->pkCurveOID;
+    #endif
+
+        FreeDecodedCert(cert);
+    #ifdef WOLFSSL_SMALL_STACK
+        XFREE(cert, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    #endif
+    }
+
+    return SSL_SUCCESS;
+}
+
+
+/* CA PEM file for verification, may have multiple/chain certs to process */
+static int ProcessChainBuffer(WOLFSSL_CTX* ctx, const unsigned char* buff,
+                            long sz, int format, int type, WOLFSSL* ssl)
+{
+    long used   = 0;
+    int  ret    = 0;
+    int  gotOne = 0;
+
+    WOLFSSL_MSG("Processing CA PEM file");
+    while (used < sz) {
+        long consumed = 0;
+
+        ret = ProcessBuffer(ctx, buff + used, sz - used, format, type, ssl,
+                            &consumed, 0);
+
+        if (ret == SSL_NO_PEM_HEADER && gotOne) {
+            WOLFSSL_MSG("We got one good PEM file so stuff at end ok");
+            ret = SSL_SUCCESS;
+            break;
+        }
+
+        if (ret < 0)
+            break;
+
+        WOLFSSL_MSG("   Processed a CA");
+        gotOne = 1;
+        used += consumed;
+    }
+
+    return ret;
+}
+
+
+/* Verify the ceritficate, SSL_SUCCESS for ok, < 0 for error */
+int wolfSSL_CertManagerVerifyBuffer(WOLFSSL_CERT_MANAGER* cm, const byte* buff,
+                                   long sz, int format)
+{
+    int ret = 0;
+    buffer der;
+#ifdef WOLFSSL_SMALL_STACK
+    DecodedCert* cert = NULL;
+#else
+    DecodedCert  cert[1];
+#endif
+
+    WOLFSSL_ENTER("wolfSSL_CertManagerVerifyBuffer");
+
+#ifdef WOLFSSL_SMALL_STACK
+    cert = (DecodedCert*)XMALLOC(sizeof(DecodedCert), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+    if (cert == NULL)
+        return MEMORY_E;
+#endif
+
+    der.buffer = NULL;
+    der.length = 0;
+
+    if (format == SSL_FILETYPE_PEM) {
+        int eccKey = 0; /* not used */
+    #ifdef WOLFSSL_SMALL_STACK
+        EncryptedInfo* info = NULL;
+    #else
+        EncryptedInfo  info[1];
+    #endif
+
+    #ifdef WOLFSSL_SMALL_STACK
+        info = (EncryptedInfo*)XMALLOC(sizeof(EncryptedInfo), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+        if (info == NULL) {
+            XFREE(cert, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            return MEMORY_E;
+        }
+    #endif
+
+        info->set      = 0;
+        info->ctx      = NULL;
+        info->consumed = 0;
+
+        ret = PemToDer(buff, sz, CERT_TYPE, &der, cm->heap, info, &eccKey);
+
+        if (ret == 0)
+            InitDecodedCert(cert, der.buffer, der.length, cm->heap);
+
+    #ifdef WOLFSSL_SMALL_STACK
+        XFREE(info, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    #endif
+    }
+    else
+        InitDecodedCert(cert, (byte*)buff, (word32)sz, cm->heap);
+
+    if (ret == 0)
+        ret = ParseCertRelative(cert, CERT_TYPE, 1, cm);
+
+#ifdef HAVE_CRL
+    if (ret == 0 && cm->crlEnabled)
+        ret = CheckCertCRL(cm->crl, cert);
+#endif
+
+    FreeDecodedCert(cert);
+
+    XFREE(der.buffer, cm->heap, DYNAMIC_TYPE_CERT);
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(cert, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret == 0 ? SSL_SUCCESS : ret;
+}
+
+
+/* turn on OCSP if off and compiled in, set options */
+int wolfSSL_CertManagerEnableOCSP(WOLFSSL_CERT_MANAGER* cm, int options)
+{
+    int ret = SSL_SUCCESS;
+
+    (void)options;
+
+    WOLFSSL_ENTER("wolfSSL_CertManagerEnableOCSP");
+    if (cm == NULL)
+        return BAD_FUNC_ARG;
+
+    #ifdef HAVE_OCSP
+        if (cm->ocsp == NULL) {
+            cm->ocsp = (WOLFSSL_OCSP*)XMALLOC(sizeof(WOLFSSL_OCSP), cm->heap,
+                                                             DYNAMIC_TYPE_OCSP);
+            if (cm->ocsp == NULL)
+                return MEMORY_E;
+
+            if (InitOCSP(cm->ocsp, cm) != 0) {
+                WOLFSSL_MSG("Init OCSP failed");
+                FreeOCSP(cm->ocsp, 1);
+                cm->ocsp = NULL;
+                return SSL_FAILURE;
+            }
+        }
+        cm->ocspEnabled = 1;
+        if (options & WOLFSSL_OCSP_URL_OVERRIDE)
+            cm->ocspUseOverrideURL = 1;
+        if (options & WOLFSSL_OCSP_NO_NONCE)
+            cm->ocspSendNonce = 0;
+        else
+            cm->ocspSendNonce = 1;
+        if (options & WOLFSSL_OCSP_CHECKALL)
+            cm->ocspCheckAll = 1;
+        #ifndef WOLFSSL_USER_IO
+            cm->ocspIOCb = EmbedOcspLookup;
+            cm->ocspRespFreeCb = EmbedOcspRespFree;
+        #endif /* WOLFSSL_USER_IO */
+    #else
+        ret = NOT_COMPILED_IN;
+    #endif
+
+    return ret;
+}
+
+
+int wolfSSL_CertManagerDisableOCSP(WOLFSSL_CERT_MANAGER* cm)
+{
+    WOLFSSL_ENTER("wolfSSL_CertManagerDisableOCSP");
+    if (cm == NULL)
+        return BAD_FUNC_ARG;
+
+    cm->ocspEnabled = 0;
+
+    return SSL_SUCCESS;
+}
+
+
+#ifdef HAVE_OCSP
+
+
+/* check CRL if enabled, SSL_SUCCESS  */
+int wolfSSL_CertManagerCheckOCSP(WOLFSSL_CERT_MANAGER* cm, byte* der, int sz)
+{
+    int ret;
+#ifdef WOLFSSL_SMALL_STACK
+    DecodedCert* cert = NULL;
+#else
+    DecodedCert  cert[1];
+#endif
+
+    WOLFSSL_ENTER("wolfSSL_CertManagerCheckOCSP");
+
+    if (cm == NULL)
+        return BAD_FUNC_ARG;
+
+    if (cm->ocspEnabled == 0)
+        return SSL_SUCCESS;
+
+#ifdef WOLFSSL_SMALL_STACK
+    cert = (DecodedCert*)XMALLOC(sizeof(DecodedCert), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+    if (cert == NULL)
+        return MEMORY_E;
+#endif
+
+    InitDecodedCert(cert, der, sz, NULL);
+
+    if ((ret = ParseCertRelative(cert, CERT_TYPE, NO_VERIFY, cm)) != 0) {
+        WOLFSSL_MSG("ParseCert failed");
+    }
+    else if ((ret = CheckCertOCSP(cm->ocsp, cert)) != 0) {
+        WOLFSSL_MSG("CheckCertOCSP failed");
+    }
+
+    FreeDecodedCert(cert);
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(cert, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret == 0 ? SSL_SUCCESS : ret;
+}
+
+
+int wolfSSL_CertManagerSetOCSPOverrideURL(WOLFSSL_CERT_MANAGER* cm,
+                                                                const char* url)
+{
+    WOLFSSL_ENTER("wolfSSL_CertManagerSetOCSPOverrideURL");
+    if (cm == NULL)
+        return BAD_FUNC_ARG;
+
+    XFREE(cm->ocspOverrideURL, cm->heap, 0);
+    if (url != NULL) {
+        int urlSz = (int)XSTRLEN(url) + 1;
+        cm->ocspOverrideURL = (char*)XMALLOC(urlSz, cm->heap, 0);
+        if (cm->ocspOverrideURL != NULL) {
+            XMEMCPY(cm->ocspOverrideURL, url, urlSz);
+        }
+        else
+            return MEMORY_E;
+    }
+    else
+        cm->ocspOverrideURL = NULL;
+
+    return SSL_SUCCESS;
+}
+
+
+int wolfSSL_CertManagerSetOCSP_Cb(WOLFSSL_CERT_MANAGER* cm,
+                        CbOCSPIO ioCb, CbOCSPRespFree respFreeCb, void* ioCbCtx)
+{
+    WOLFSSL_ENTER("wolfSSL_CertManagerSetOCSP_Cb");
+    if (cm == NULL)
+        return BAD_FUNC_ARG;
+
+    cm->ocspIOCb = ioCb;
+    cm->ocspRespFreeCb = respFreeCb;
+    cm->ocspIOCtx = ioCbCtx;
+
+    return SSL_SUCCESS;
+}
+
+
+int wolfSSL_EnableOCSP(WOLFSSL* ssl, int options)
+{
+    WOLFSSL_ENTER("wolfSSL_EnableOCSP");
+    if (ssl)
+        return wolfSSL_CertManagerEnableOCSP(ssl->ctx->cm, options);
+    else
+        return BAD_FUNC_ARG;
+}
+
+
+int wolfSSL_DisableOCSP(WOLFSSL* ssl)
+{
+    WOLFSSL_ENTER("wolfSSL_DisableOCSP");
+    if (ssl)
+        return wolfSSL_CertManagerDisableOCSP(ssl->ctx->cm);
+    else
+        return BAD_FUNC_ARG;
+}
+
+
+int wolfSSL_SetOCSP_OverrideURL(WOLFSSL* ssl, const char* url)
+{
+    WOLFSSL_ENTER("wolfSSL_SetOCSP_OverrideURL");
+    if (ssl)
+        return wolfSSL_CertManagerSetOCSPOverrideURL(ssl->ctx->cm, url);
+    else
+        return BAD_FUNC_ARG;
+}
+
+
+int wolfSSL_SetOCSP_Cb(WOLFSSL* ssl,
+                        CbOCSPIO ioCb, CbOCSPRespFree respFreeCb, void* ioCbCtx)
+{
+    WOLFSSL_ENTER("wolfSSL_SetOCSP_Cb");
+    if (ssl)
+        return wolfSSL_CertManagerSetOCSP_Cb(ssl->ctx->cm,
+                                                     ioCb, respFreeCb, ioCbCtx);
+    else
+        return BAD_FUNC_ARG;
+}
+
+
+int wolfSSL_CTX_EnableOCSP(WOLFSSL_CTX* ctx, int options)
+{
+    WOLFSSL_ENTER("wolfSSL_CTX_EnableOCSP");
+    if (ctx)
+        return wolfSSL_CertManagerEnableOCSP(ctx->cm, options);
+    else
+        return BAD_FUNC_ARG;
+}
+
+
+int wolfSSL_CTX_DisableOCSP(WOLFSSL_CTX* ctx)
+{
+    WOLFSSL_ENTER("wolfSSL_CTX_DisableOCSP");
+    if (ctx)
+        return wolfSSL_CertManagerDisableOCSP(ctx->cm);
+    else
+        return BAD_FUNC_ARG;
+}
+
+
+int wolfSSL_CTX_SetOCSP_OverrideURL(WOLFSSL_CTX* ctx, const char* url)
+{
+    WOLFSSL_ENTER("wolfSSL_SetOCSP_OverrideURL");
+    if (ctx)
+        return wolfSSL_CertManagerSetOCSPOverrideURL(ctx->cm, url);
+    else
+        return BAD_FUNC_ARG;
+}
+
+
+int wolfSSL_CTX_SetOCSP_Cb(WOLFSSL_CTX* ctx,
+                        CbOCSPIO ioCb, CbOCSPRespFree respFreeCb, void* ioCbCtx)
+{
+    WOLFSSL_ENTER("wolfSSL_CTX_SetOCSP_Cb");
+    if (ctx)
+        return wolfSSL_CertManagerSetOCSP_Cb(ctx->cm, ioCb, respFreeCb, ioCbCtx);
+    else
+        return BAD_FUNC_ARG;
+}
+
+
+#endif /* HAVE_OCSP */
+
+
+#ifndef NO_FILESYSTEM
+
+    #if defined(WOLFSSL_MDK_ARM)
+        extern FILE * wolfSSL_fopen(const char *name, const char *mode) ;
+        #define XFOPEN     wolfSSL_fopen
+    #else
+        #define XFOPEN     fopen
+    #endif
+
+/* process a file with name fname into ctx of format and type
+   userChain specifies a user certificate chain to pass during handshake */
+int ProcessFile(WOLFSSL_CTX* ctx, const char* fname, int format, int type,
+                WOLFSSL* ssl, int userChain, WOLFSSL_CRL* crl)
+{
+#ifdef WOLFSSL_SMALL_STACK
+    byte   staticBuffer[1]; /* force heap usage */
+#else
+    byte   staticBuffer[FILE_BUFFER_SIZE];
+#endif
+    byte*  myBuffer = staticBuffer;
+    int    dynamic = 0;
+    int    ret;
+    long   sz = 0;
+    XFILE  file;
+    void*  heapHint = ctx ? ctx->heap : NULL;
+
+    (void)crl;
+    (void)heapHint;
+
+    if (fname == NULL) return SSL_BAD_FILE;
+
+    file = XFOPEN(fname, "rb");
+    if (file == XBADFILE) return SSL_BAD_FILE;
+    XFSEEK(file, 0, XSEEK_END);
+    sz = XFTELL(file);
+    XREWIND(file);
+
+    if (sz > (long)sizeof(staticBuffer)) {
+        WOLFSSL_MSG("Getting dynamic buffer");
+        myBuffer = (byte*)XMALLOC(sz, heapHint, DYNAMIC_TYPE_FILE);
+        if (myBuffer == NULL) {
+            XFCLOSE(file);
+            return SSL_BAD_FILE;
+        }
+        dynamic = 1;
+    }
+    else if (sz < 0) {
+        XFCLOSE(file);
+        return SSL_BAD_FILE;
+    }
+
+    if ( (ret = (int)XFREAD(myBuffer, sz, 1, file)) < 0)
+        ret = SSL_BAD_FILE;
+    else {
+        if (type == CA_TYPE && format == SSL_FILETYPE_PEM)
+            ret = ProcessChainBuffer(ctx, myBuffer, sz, format, type, ssl);
+#ifdef HAVE_CRL
+        else if (type == CRL_TYPE)
+            ret = BufferLoadCRL(crl, myBuffer, sz, format);
+#endif
+        else
+            ret = ProcessBuffer(ctx, myBuffer, sz, format, type, ssl, NULL,
+                                userChain);
+    }
+
+    XFCLOSE(file);
+    if (dynamic)
+        XFREE(myBuffer, heapHint, DYNAMIC_TYPE_FILE);
+
+    return ret;
+}
+
+
+/* loads file then loads each file in path, no c_rehash */
+int wolfSSL_CTX_load_verify_locations(WOLFSSL_CTX* ctx, const char* file,
+                                     const char* path)
+{
+    int ret = SSL_SUCCESS;
+
+    WOLFSSL_ENTER("wolfSSL_CTX_load_verify_locations");
+    (void)path;
+
+    if (ctx == NULL || (file == NULL && path == NULL) )
+        return SSL_FAILURE;
+
+    if (file)
+        ret = ProcessFile(ctx, file, SSL_FILETYPE_PEM, CA_TYPE, NULL, 0, NULL);
+
+    if (ret == SSL_SUCCESS && path) {
+        /* try to load each regular file in path */
+    #ifdef USE_WINDOWS_API
+        WIN32_FIND_DATAA FindFileData;
+        HANDLE hFind;
+    #ifdef WOLFSSL_SMALL_STACK
+        char*  name = NULL;
+    #else
+        char   name[MAX_FILENAME_SZ];
+    #endif
+
+    #ifdef WOLFSSL_SMALL_STACK
+        name = (char*)XMALLOC(MAX_FILENAME_SZ, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (name == NULL)
+            return MEMORY_E;
+    #endif
+
+        XMEMSET(name, 0, MAX_FILENAME_SZ);
+        XSTRNCPY(name, path, MAX_FILENAME_SZ - 4);
+        XSTRNCAT(name, "\\*", 3);
+
+        hFind = FindFirstFileA(name, &FindFileData);
+        if (hFind == INVALID_HANDLE_VALUE) {
+            WOLFSSL_MSG("FindFirstFile for path verify locations failed");
+        #ifdef WOLFSSL_SMALL_STACK
+            XFREE(name, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        #endif
+            return BAD_PATH_ERROR;
+        }
+
+        do {
+            if (FindFileData.dwFileAttributes != FILE_ATTRIBUTE_DIRECTORY) {
+                XSTRNCPY(name, path, MAX_FILENAME_SZ/2 - 3);
+                XSTRNCAT(name, "\\", 2);
+                XSTRNCAT(name, FindFileData.cFileName, MAX_FILENAME_SZ/2);
+
+                ret = ProcessFile(ctx, name, SSL_FILETYPE_PEM, CA_TYPE, NULL,0,
+                                                                          NULL);
+            }
+        } while (ret == SSL_SUCCESS && FindNextFileA(hFind, &FindFileData));
+
+    #ifdef WOLFSSL_SMALL_STACK
+        XFREE(name, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    #endif
+
+        FindClose(hFind);
+    #elif !defined(NO_WOLFSSL_DIR)
+        struct dirent* entry;
+        DIR*   dir = opendir(path);
+    #ifdef WOLFSSL_SMALL_STACK
+        char*  name = NULL;
+    #else
+        char   name[MAX_FILENAME_SZ];
+    #endif
+
+        if (dir == NULL) {
+            WOLFSSL_MSG("opendir path verify locations failed");
+            return BAD_PATH_ERROR;
+        }
+
+    #ifdef WOLFSSL_SMALL_STACK
+        name = (char*)XMALLOC(MAX_FILENAME_SZ, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (name == NULL)
+            return MEMORY_E;
+    #endif
+
+        while ( ret == SSL_SUCCESS && (entry = readdir(dir)) != NULL) {
+            struct stat s;
+
+            XMEMSET(name, 0, MAX_FILENAME_SZ);
+            XSTRNCPY(name, path, MAX_FILENAME_SZ/2 - 2);
+            XSTRNCAT(name, "/", 1);
+            XSTRNCAT(name, entry->d_name, MAX_FILENAME_SZ/2);
+
+            if (stat(name, &s) != 0) {
+                WOLFSSL_MSG("stat on name failed");
+                ret = BAD_PATH_ERROR;
+            } else if (s.st_mode & S_IFREG)
+                ret = ProcessFile(ctx, name, SSL_FILETYPE_PEM, CA_TYPE, NULL,0,
+                                                                          NULL);
+        }
+
+    #ifdef WOLFSSL_SMALL_STACK
+        XFREE(name, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    #endif
+
+        closedir(dir);
+    #endif
+    }
+
+    return ret;
+}
+
+
+/* Verify the ceritficate, SSL_SUCCESS for ok, < 0 for error */
+int wolfSSL_CertManagerVerify(WOLFSSL_CERT_MANAGER* cm, const char* fname,
+                             int format)
+{
+    int    ret = SSL_FATAL_ERROR;
+#ifdef WOLFSSL_SMALL_STACK
+    byte   staticBuffer[1]; /* force heap usage */
+#else
+    byte   staticBuffer[FILE_BUFFER_SIZE];
+#endif
+    byte*  myBuffer = staticBuffer;
+    int    dynamic = 0;
+    long   sz = 0;
+    XFILE  file = XFOPEN(fname, "rb");
+
+    WOLFSSL_ENTER("wolfSSL_CertManagerVerify");
+
+    if (file == XBADFILE) return SSL_BAD_FILE;
+    XFSEEK(file, 0, XSEEK_END);
+    sz = XFTELL(file);
+    XREWIND(file);
+
+    if (sz > MAX_WOLFSSL_FILE_SIZE || sz < 0) {
+        WOLFSSL_MSG("CertManagerVerify file bad size");
+        XFCLOSE(file);
+        return SSL_BAD_FILE;
+    }
+
+    if (sz > (long)sizeof(staticBuffer)) {
+        WOLFSSL_MSG("Getting dynamic buffer");
+        myBuffer = (byte*) XMALLOC(sz, cm->heap, DYNAMIC_TYPE_FILE);
+        if (myBuffer == NULL) {
+            XFCLOSE(file);
+            return SSL_BAD_FILE;
+        }
+        dynamic = 1;
+    }
+
+    if ( (ret = (int)XFREAD(myBuffer, sz, 1, file)) < 0)
+        ret = SSL_BAD_FILE;
+    else
+        ret = wolfSSL_CertManagerVerifyBuffer(cm, myBuffer, sz, format);
+
+    XFCLOSE(file);
+    if (dynamic)
+        XFREE(myBuffer, cm->heap, DYNAMIC_TYPE_FILE);
+
+    return ret;
+}
+
+
+static INLINE WOLFSSL_METHOD* cm_pick_method(void)
+{
+    #ifndef NO_WOLFSSL_CLIENT
+        #ifdef NO_OLD_TLS
+            return wolfTLSv1_2_client_method();
+        #else
+            return wolfSSLv3_client_method();
+        #endif      
+    #elif !defined(NO_WOLFSSL_SERVER)
+        #ifdef NO_OLD_TLS
+            return wolfTLSv1_2_server_method();
+        #else
+            return wolfSSLv3_server_method();
+        #endif
+    #else
+        return NULL;
+    #endif
+}
+
+
+/* like load verify locations, 1 for success, < 0 for error */
+int wolfSSL_CertManagerLoadCA(WOLFSSL_CERT_MANAGER* cm, const char* file,
+                             const char* path)
+{
+    int ret = SSL_FATAL_ERROR;
+    WOLFSSL_CTX* tmp;
+
+    WOLFSSL_ENTER("wolfSSL_CertManagerLoadCA");
+
+    if (cm == NULL) {
+        WOLFSSL_MSG("No CertManager error");
+        return ret;
+    }
+    tmp = wolfSSL_CTX_new(cm_pick_method());
+
+    if (tmp == NULL) {
+        WOLFSSL_MSG("CTX new failed");
+        return ret;
+    }
+
+    /* for tmp use */
+    wolfSSL_CertManagerFree(tmp->cm);
+    tmp->cm = cm;
+
+    ret = wolfSSL_CTX_load_verify_locations(tmp, file, path);
+
+    /* don't loose our good one */
+    tmp->cm = NULL;
+    wolfSSL_CTX_free(tmp);
+
+    return ret;
+}
+
+
+
+/* turn on CRL if off and compiled in, set options */
+int wolfSSL_CertManagerEnableCRL(WOLFSSL_CERT_MANAGER* cm, int options)
+{
+    int ret = SSL_SUCCESS;
+
+    (void)options;
+
+    WOLFSSL_ENTER("wolfSSL_CertManagerEnableCRL");
+    if (cm == NULL)
+        return BAD_FUNC_ARG;
+
+    #ifdef HAVE_CRL
+        if (cm->crl == NULL) {
+            cm->crl = (WOLFSSL_CRL*)XMALLOC(sizeof(WOLFSSL_CRL), cm->heap,
+                                           DYNAMIC_TYPE_CRL);
+            if (cm->crl == NULL)
+                return MEMORY_E;
+
+            if (InitCRL(cm->crl, cm) != 0) {
+                WOLFSSL_MSG("Init CRL failed");
+                FreeCRL(cm->crl, 1);
+                cm->crl = NULL;
+                return SSL_FAILURE;
+            }
+        }
+        cm->crlEnabled = 1;
+        if (options & WOLFSSL_CRL_CHECKALL)
+            cm->crlCheckAll = 1;
+    #else
+        ret = NOT_COMPILED_IN;
+    #endif
+
+    return ret;
+}
+
+
+int wolfSSL_CertManagerDisableCRL(WOLFSSL_CERT_MANAGER* cm)
+{
+    WOLFSSL_ENTER("wolfSSL_CertManagerDisableCRL");
+    if (cm == NULL)
+        return BAD_FUNC_ARG;
+
+    cm->crlEnabled = 0;
+
+    return SSL_SUCCESS;
+}
+
+
+int wolfSSL_CTX_check_private_key(WOLFSSL_CTX* ctx)
+{
+    /* TODO: check private against public for RSA match */
+    (void)ctx;
+    WOLFSSL_ENTER("SSL_CTX_check_private_key");
+    return SSL_SUCCESS;
+}
+
+
+#ifdef HAVE_CRL
+
+
+/* check CRL if enabled, SSL_SUCCESS  */
+int wolfSSL_CertManagerCheckCRL(WOLFSSL_CERT_MANAGER* cm, byte* der, int sz)
+{
+    int ret = 0;
+#ifdef WOLFSSL_SMALL_STACK
+    DecodedCert* cert = NULL;
+#else
+    DecodedCert  cert[1];
+#endif
+
+    WOLFSSL_ENTER("wolfSSL_CertManagerCheckCRL");
+
+    if (cm == NULL)
+        return BAD_FUNC_ARG;
+
+    if (cm->crlEnabled == 0)
+        return SSL_SUCCESS;
+
+#ifdef WOLFSSL_SMALL_STACK
+    cert = (DecodedCert*)XMALLOC(sizeof(DecodedCert), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+    if (cert == NULL)
+        return MEMORY_E;
+#endif
+
+    InitDecodedCert(cert, der, sz, NULL);
+
+    if ((ret = ParseCertRelative(cert, CERT_TYPE, NO_VERIFY, cm)) != 0) {
+        WOLFSSL_MSG("ParseCert failed");
+    }
+    else if ((ret = CheckCertCRL(cm->crl, cert)) != 0) {
+        WOLFSSL_MSG("CheckCertCRL failed");
+    }
+
+    FreeDecodedCert(cert);
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(cert, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret == 0 ? SSL_SUCCESS : ret;
+}
+
+
+int wolfSSL_CertManagerSetCRL_Cb(WOLFSSL_CERT_MANAGER* cm, CbMissingCRL cb)
+{
+    WOLFSSL_ENTER("wolfSSL_CertManagerSetCRL_Cb");
+    if (cm == NULL)
+        return BAD_FUNC_ARG;
+
+    cm->cbMissingCRL = cb;
+
+    return SSL_SUCCESS;
+}
+
+
+int wolfSSL_CertManagerLoadCRL(WOLFSSL_CERT_MANAGER* cm, const char* path,
+                              int type, int monitor)
+{
+    WOLFSSL_ENTER("wolfSSL_CertManagerLoadCRL");
+    if (cm == NULL)
+        return BAD_FUNC_ARG;
+
+    if (cm->crl == NULL) {
+        if (wolfSSL_CertManagerEnableCRL(cm, 0) != SSL_SUCCESS) {
+            WOLFSSL_MSG("Enable CRL failed");
+            return SSL_FATAL_ERROR;
+        }
+    }
+
+    return LoadCRL(cm->crl, path, type, monitor);
+}
+
+
+int wolfSSL_EnableCRL(WOLFSSL* ssl, int options)
+{
+    WOLFSSL_ENTER("wolfSSL_EnableCRL");
+    if (ssl)
+        return wolfSSL_CertManagerEnableCRL(ssl->ctx->cm, options);
+    else
+        return BAD_FUNC_ARG;
+}
+
+
+int wolfSSL_DisableCRL(WOLFSSL* ssl)
+{
+    WOLFSSL_ENTER("wolfSSL_DisableCRL");
+    if (ssl)
+        return wolfSSL_CertManagerDisableCRL(ssl->ctx->cm);
+    else
+        return BAD_FUNC_ARG;
+}
+
+
+int wolfSSL_LoadCRL(WOLFSSL* ssl, const char* path, int type, int monitor)
+{
+    WOLFSSL_ENTER("wolfSSL_LoadCRL");
+    if (ssl)
+        return wolfSSL_CertManagerLoadCRL(ssl->ctx->cm, path, type, monitor);
+    else
+        return BAD_FUNC_ARG;
+}
+
+
+int wolfSSL_SetCRL_Cb(WOLFSSL* ssl, CbMissingCRL cb)
+{
+    WOLFSSL_ENTER("wolfSSL_SetCRL_Cb");
+    if (ssl)
+        return wolfSSL_CertManagerSetCRL_Cb(ssl->ctx->cm, cb);
+    else
+        return BAD_FUNC_ARG;
+}
+
+
+int wolfSSL_CTX_EnableCRL(WOLFSSL_CTX* ctx, int options)
+{
+    WOLFSSL_ENTER("wolfSSL_CTX_EnableCRL");
+    if (ctx)
+        return wolfSSL_CertManagerEnableCRL(ctx->cm, options);
+    else
+        return BAD_FUNC_ARG;
+}
+
+
+int wolfSSL_CTX_DisableCRL(WOLFSSL_CTX* ctx)
+{
+    WOLFSSL_ENTER("wolfSSL_CTX_DisableCRL");
+    if (ctx)
+        return wolfSSL_CertManagerDisableCRL(ctx->cm);
+    else
+        return BAD_FUNC_ARG;
+}
+
+
+int wolfSSL_CTX_LoadCRL(WOLFSSL_CTX* ctx, const char* path, int type, int monitor)
+{
+    WOLFSSL_ENTER("wolfSSL_CTX_LoadCRL");
+    if (ctx)
+        return wolfSSL_CertManagerLoadCRL(ctx->cm, path, type, monitor);
+    else
+        return BAD_FUNC_ARG;
+}
+
+
+int wolfSSL_CTX_SetCRL_Cb(WOLFSSL_CTX* ctx, CbMissingCRL cb)
+{
+    WOLFSSL_ENTER("wolfSSL_CTX_SetCRL_Cb");
+    if (ctx)
+        return wolfSSL_CertManagerSetCRL_Cb(ctx->cm, cb);
+    else
+        return BAD_FUNC_ARG;
+}
+
+
+#endif /* HAVE_CRL */
+
+
+#ifdef WOLFSSL_DER_LOAD
+
+/* Add format parameter to allow DER load of CA files */
+int wolfSSL_CTX_der_load_verify_locations(WOLFSSL_CTX* ctx, const char* file,
+                                         int format)
+{
+    WOLFSSL_ENTER("wolfSSL_CTX_der_load_verify_locations");
+    if (ctx == NULL || file == NULL)
+        return SSL_FAILURE;
+
+    if (ProcessFile(ctx, file, format, CA_TYPE, NULL, 0, NULL) == SSL_SUCCESS)
+        return SSL_SUCCESS;
+
+    return SSL_FAILURE;
+}
+
+#endif /* WOLFSSL_DER_LOAD */
+
+
+#ifdef WOLFSSL_CERT_GEN
+
+/* load pem cert from file into der buffer, return der size or error */
+int wolfSSL_PemCertToDer(const char* fileName, unsigned char* derBuf, int derSz)
+{
+#ifdef WOLFSSL_SMALL_STACK
+    EncryptedInfo* info = NULL;
+    byte   staticBuffer[1]; /* force XMALLOC */
+#else
+    EncryptedInfo info[1];
+    byte   staticBuffer[FILE_BUFFER_SIZE];
+#endif
+    byte*  fileBuf = staticBuffer;
+    int    dynamic = 0;
+    int    ret     = 0;
+    int    ecc     = 0;
+    long   sz      = 0;
+    XFILE  file    = XFOPEN(fileName, "rb");
+    buffer converted;
+
+    WOLFSSL_ENTER("wolfSSL_PemCertToDer");
+
+    if (file == XBADFILE)
+        ret = SSL_BAD_FILE;
+    else {
+        XFSEEK(file, 0, XSEEK_END);
+        sz = XFTELL(file);
+        XREWIND(file);
+
+        if (sz < 0) {
+            ret = SSL_BAD_FILE;
+        }
+        else if (sz > (long)sizeof(staticBuffer)) {
+            fileBuf = (byte*)XMALLOC(sz, 0, DYNAMIC_TYPE_FILE);
+            if (fileBuf == NULL)
+                ret = MEMORY_E;
+            else
+                dynamic = 1;
+        }
+
+        converted.buffer = 0;
+
+        if (ret == 0) {
+            if ( (ret = (int)XFREAD(fileBuf, sz, 1, file)) < 0)
+                ret = SSL_BAD_FILE;
+            else {
+            #ifdef WOLFSSL_SMALL_STACK
+                info = (EncryptedInfo*)XMALLOC(sizeof(EncryptedInfo), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+                if (info == NULL)
+                    ret = MEMORY_E;
+                else
+            #endif
+                {
+                    ret = PemToDer(fileBuf, sz, CA_TYPE, &converted, 0, info,
+                                                                          &ecc);
+                #ifdef WOLFSSL_SMALL_STACK
+                    XFREE(info, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                #endif
+                }
+            }
+
+            if (ret == 0) {
+                if (converted.length < (word32)derSz) {
+                    XMEMCPY(derBuf, converted.buffer, converted.length);
+                    ret = converted.length;
+                }
+                else
+                    ret = BUFFER_E;
+            }
+
+            XFREE(converted.buffer, 0, DYNAMIC_TYPE_CA);
+        }
+
+        XFCLOSE(file);
+        if (dynamic)
+            XFREE(fileBuf, 0, DYNAMIC_TYPE_FILE);
+    }
+
+    return ret;
+}
+
+#endif /* WOLFSSL_CERT_GEN */
+
+
+int wolfSSL_CTX_use_certificate_file(WOLFSSL_CTX* ctx, const char* file,
+                                    int format)
+{
+    WOLFSSL_ENTER("wolfSSL_CTX_use_certificate_file");
+    if (ProcessFile(ctx, file, format, CERT_TYPE, NULL, 0, NULL) == SSL_SUCCESS)
+        return SSL_SUCCESS;
+
+    return SSL_FAILURE;
+}
+
+
+int wolfSSL_CTX_use_PrivateKey_file(WOLFSSL_CTX* ctx, const char* file,int format)
+{
+    WOLFSSL_ENTER("wolfSSL_CTX_use_PrivateKey_file");
+    if (ProcessFile(ctx, file, format, PRIVATEKEY_TYPE, NULL, 0, NULL)
+                    == SSL_SUCCESS)
+        return SSL_SUCCESS;
+
+    return SSL_FAILURE;
+}
+
+
+/* get cert chaining depth using ssl struct */
+long wolfSSL_get_verify_depth(WOLFSSL* ssl)
+{
+    if(ssl == NULL) {
+        return BAD_FUNC_ARG;
+    }
+    return MAX_CHAIN_DEPTH;
+}
+
+
+/* get cert chaining depth using ctx struct */
+long wolfSSL_CTX_get_verify_depth(WOLFSSL_CTX* ctx)
+{
+    if(ctx == NULL) {
+        return BAD_FUNC_ARG;
+    }
+    return MAX_CHAIN_DEPTH;
+}
+
+
+int wolfSSL_CTX_use_certificate_chain_file(WOLFSSL_CTX* ctx, const char* file)
+{
+   /* procces up to MAX_CHAIN_DEPTH plus subject cert */
+   WOLFSSL_ENTER("wolfSSL_CTX_use_certificate_chain_file");
+   if (ProcessFile(ctx, file, SSL_FILETYPE_PEM,CERT_TYPE,NULL,1, NULL)
+                   == SSL_SUCCESS)
+       return SSL_SUCCESS;
+
+   return SSL_FAILURE;
+}
+
+
+#ifndef NO_DH
+
+/* server wrapper for ctx or ssl Diffie-Hellman parameters */
+static int wolfSSL_SetTmpDH_buffer_wrapper(WOLFSSL_CTX* ctx, WOLFSSL* ssl,
+                                  const unsigned char* buf, long sz, int format)
+{
+    buffer der;
+    int    ret      = 0;
+    int    weOwnDer = 0;
+    word32 pSz = MAX_DH_SIZE;
+    word32 gSz = MAX_DH_SIZE;
+#ifdef WOLFSSL_SMALL_STACK
+    byte*  p = NULL;
+    byte*  g = NULL;
+#else
+    byte   p[MAX_DH_SIZE];
+    byte   g[MAX_DH_SIZE];
+#endif
+
+    der.buffer = (byte*)buf;
+    der.length = (word32)sz;
+
+#ifdef WOLFSSL_SMALL_STACK
+    p = (byte*)XMALLOC(pSz, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    g = (byte*)XMALLOC(gSz, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+
+    if (p == NULL || g == NULL) {
+        XFREE(p, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(g, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        return MEMORY_E;
+    }
+#endif
+
+    if (format != SSL_FILETYPE_ASN1 && format != SSL_FILETYPE_PEM)
+        ret = SSL_BAD_FILETYPE;
+    else {
+        if (format == SSL_FILETYPE_PEM) {
+            der.buffer = NULL;
+            ret = PemToDer(buf, sz, DH_PARAM_TYPE, &der, ctx->heap, NULL,NULL);
+            weOwnDer = 1;
+        }
+        
+        if (ret == 0) {
+            if (wc_DhParamsLoad(der.buffer, der.length, p, &pSz, g, &gSz) < 0)
+                ret = SSL_BAD_FILETYPE;
+            else if (ssl)
+                ret = wolfSSL_SetTmpDH(ssl, p, pSz, g, gSz);
+            else
+                ret = wolfSSL_CTX_SetTmpDH(ctx, p, pSz, g, gSz);
+        }
+    }
+
+    if (weOwnDer)
+        XFREE(der.buffer, ctx->heap, DYNAMIC_TYPE_KEY);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(p, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(g, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+
+/* server Diffie-Hellman parameters, SSL_SUCCESS on ok */
+int wolfSSL_SetTmpDH_buffer(WOLFSSL* ssl, const unsigned char* buf, long sz,
+                           int format)
+{
+    return wolfSSL_SetTmpDH_buffer_wrapper(ssl->ctx, ssl, buf, sz, format);
+}
+
+
+/* server ctx Diffie-Hellman parameters, SSL_SUCCESS on ok */
+int wolfSSL_CTX_SetTmpDH_buffer(WOLFSSL_CTX* ctx, const unsigned char* buf,
+                               long sz, int format)
+{
+    return wolfSSL_SetTmpDH_buffer_wrapper(ctx, NULL, buf, sz, format);
+}
+
+
+/* server Diffie-Hellman parameters */
+static int wolfSSL_SetTmpDH_file_wrapper(WOLFSSL_CTX* ctx, WOLFSSL* ssl,
+                                        const char* fname, int format)
+{
+#ifdef WOLFSSL_SMALL_STACK
+    byte   staticBuffer[1]; /* force heap usage */
+#else
+    byte   staticBuffer[FILE_BUFFER_SIZE];
+#endif
+    byte*  myBuffer = staticBuffer;
+    int    dynamic = 0;
+    int    ret;
+    long   sz = 0;
+    XFILE  file = XFOPEN(fname, "rb");
+
+    if (file == XBADFILE) return SSL_BAD_FILE;
+    XFSEEK(file, 0, XSEEK_END);
+    sz = XFTELL(file);
+    XREWIND(file);
+
+    if (sz > (long)sizeof(staticBuffer)) {
+        WOLFSSL_MSG("Getting dynamic buffer");
+        myBuffer = (byte*) XMALLOC(sz, ctx->heap, DYNAMIC_TYPE_FILE);
+        if (myBuffer == NULL) {
+            XFCLOSE(file);
+            return SSL_BAD_FILE;
+        }
+        dynamic = 1;
+    }
+    else if (sz < 0) {
+        XFCLOSE(file);
+        return SSL_BAD_FILE;
+    }
+
+    if ( (ret = (int)XFREAD(myBuffer, sz, 1, file)) < 0)
+        ret = SSL_BAD_FILE;
+    else {
+        if (ssl)
+            ret = wolfSSL_SetTmpDH_buffer(ssl, myBuffer, sz, format);
+        else
+            ret = wolfSSL_CTX_SetTmpDH_buffer(ctx, myBuffer, sz, format);
+    }
+
+    XFCLOSE(file);
+    if (dynamic)
+        XFREE(myBuffer, ctx->heap, DYNAMIC_TYPE_FILE);
+
+    return ret;
+}
+
+/* server Diffie-Hellman parameters */
+int wolfSSL_SetTmpDH_file(WOLFSSL* ssl, const char* fname, int format)
+{
+    return wolfSSL_SetTmpDH_file_wrapper(ssl->ctx, ssl, fname, format);
+}
+
+
+/* server Diffie-Hellman parameters */
+int wolfSSL_CTX_SetTmpDH_file(WOLFSSL_CTX* ctx, const char* fname, int format)
+{
+    return wolfSSL_SetTmpDH_file_wrapper(ctx, NULL, fname, format);
+}
+
+
+int wolfSSL_CTX_SetMinDhKey_Sz(WOLFSSL_CTX* ctx, word16 keySz)
+{
+    if (ctx == NULL || keySz > 16000 || keySz % 8 != 0)
+        return BAD_FUNC_ARG;
+
+    ctx->minDhKeySz = keySz / 8;
+    return SSL_SUCCESS;
+}
+
+
+int wolfSSL_SetMinDhKey_Sz(WOLFSSL* ssl, word16 keySz)
+{
+    if (ssl == NULL || keySz > 16000 || keySz % 8 != 0)
+        return BAD_FUNC_ARG;
+
+    ssl->options.minDhKeySz = keySz / 8;
+    return SSL_SUCCESS;
+}
+
+
+int wolfSSL_GetDhKey_Sz(WOLFSSL* ssl)
+{
+    if (ssl == NULL)
+        return BAD_FUNC_ARG;
+
+    return (ssl->options.dhKeySz * 8);
+}
+
+
+#endif /* NO_DH */
+
+
+#ifdef OPENSSL_EXTRA
+/* put SSL type in extra for now, not very common */
+
+int wolfSSL_use_certificate_file(WOLFSSL* ssl, const char* file, int format)
+{
+    WOLFSSL_ENTER("wolfSSL_use_certificate_file");
+    if (ProcessFile(ssl->ctx, file, format, CERT_TYPE, ssl, 0, NULL)
+                    == SSL_SUCCESS)
+        return SSL_SUCCESS;
+
+    return SSL_FAILURE;
+}
+
+
+int wolfSSL_use_PrivateKey_file(WOLFSSL* ssl, const char* file, int format)
+{
+    WOLFSSL_ENTER("wolfSSL_use_PrivateKey_file");
+    if (ProcessFile(ssl->ctx, file, format, PRIVATEKEY_TYPE, ssl, 0, NULL)
+                                                                 == SSL_SUCCESS)
+        return SSL_SUCCESS;
+
+    return SSL_FAILURE;
+}
+
+
+int wolfSSL_use_certificate_chain_file(WOLFSSL* ssl, const char* file)
+{
+   /* procces up to MAX_CHAIN_DEPTH plus subject cert */
+   WOLFSSL_ENTER("wolfSSL_use_certificate_chain_file");
+   if (ProcessFile(ssl->ctx, file, SSL_FILETYPE_PEM, CERT_TYPE, ssl, 1, NULL)
+                                                                 == SSL_SUCCESS)
+       return SSL_SUCCESS;
+
+   return SSL_FAILURE;
+}
+
+
+
+#ifdef HAVE_ECC
+
+/* Set Temp CTX EC-DHE size in octets, should be 20 - 66 for 160 - 521 bit */
+int wolfSSL_CTX_SetTmpEC_DHE_Sz(WOLFSSL_CTX* ctx, word16 sz)
+{
+    if (ctx == NULL || sz < ECC_MINSIZE || sz > ECC_MAXSIZE)
+        return BAD_FUNC_ARG;
+
+    ctx->eccTempKeySz = sz;
+
+    return SSL_SUCCESS;
+}
+
+
+/* Set Temp SSL EC-DHE size in octets, should be 20 - 66 for 160 - 521 bit */
+int wolfSSL_SetTmpEC_DHE_Sz(WOLFSSL* ssl, word16 sz)
+{
+    if (ssl == NULL || sz < ECC_MINSIZE || sz > ECC_MAXSIZE)
+        return BAD_FUNC_ARG;
+
+    ssl->eccTempKeySz = sz;
+
+    return SSL_SUCCESS;
+}
+
+#endif /* HAVE_ECC */
+
+
+
+
+int wolfSSL_CTX_use_RSAPrivateKey_file(WOLFSSL_CTX* ctx,const char* file,
+                                   int format)
+{
+    WOLFSSL_ENTER("SSL_CTX_use_RSAPrivateKey_file");
+
+    return wolfSSL_CTX_use_PrivateKey_file(ctx, file, format);
+}
+
+
+int wolfSSL_use_RSAPrivateKey_file(WOLFSSL* ssl, const char* file, int format)
+{
+    WOLFSSL_ENTER("wolfSSL_use_RSAPrivateKey_file");
+
+    return wolfSSL_use_PrivateKey_file(ssl, file, format);
+}
+
+#endif /* OPENSSL_EXTRA */
+
+#ifdef HAVE_NTRU
+
+int wolfSSL_CTX_use_NTRUPrivateKey_file(WOLFSSL_CTX* ctx, const char* file)
+{
+    WOLFSSL_ENTER("wolfSSL_CTX_use_NTRUPrivateKey_file");
+    if (ctx == NULL)
+        return SSL_FAILURE;
+
+    if (ProcessFile(ctx, file, SSL_FILETYPE_RAW, PRIVATEKEY_TYPE, NULL, 0, NULL)
+                         == SSL_SUCCESS) {
+        ctx->haveNTRU = 1;
+        return SSL_SUCCESS;
+    }
+
+    return SSL_FAILURE;
+}
+
+#endif /* HAVE_NTRU */
+
+
+#endif /* NO_FILESYSTEM */
+
+
+void wolfSSL_CTX_set_verify(WOLFSSL_CTX* ctx, int mode, VerifyCallback vc)
+{
+    WOLFSSL_ENTER("wolfSSL_CTX_set_verify");
+    if (mode & SSL_VERIFY_PEER) {
+        ctx->verifyPeer = 1;
+        ctx->verifyNone = 0;  /* in case perviously set */
+    }
+
+    if (mode == SSL_VERIFY_NONE) {
+        ctx->verifyNone = 1;
+        ctx->verifyPeer = 0;  /* in case previously set */
+    }
+
+    if (mode & SSL_VERIFY_FAIL_IF_NO_PEER_CERT)
+        ctx->failNoCert = 1;
+
+    ctx->verifyCallback = vc;
+}
+
+
+void wolfSSL_set_verify(WOLFSSL* ssl, int mode, VerifyCallback vc)
+{
+    WOLFSSL_ENTER("wolfSSL_set_verify");
+    if (mode & SSL_VERIFY_PEER) {
+        ssl->options.verifyPeer = 1;
+        ssl->options.verifyNone = 0;  /* in case perviously set */
+    }
+
+    if (mode == SSL_VERIFY_NONE) {
+        ssl->options.verifyNone = 1;
+        ssl->options.verifyPeer = 0;  /* in case previously set */
+    }
+
+    if (mode & SSL_VERIFY_FAIL_IF_NO_PEER_CERT)
+        ssl->options.failNoCert = 1;
+
+    ssl->verifyCallback = vc;
+}
+
+
+/* store user ctx for verify callback */
+void wolfSSL_SetCertCbCtx(WOLFSSL* ssl, void* ctx)
+{
+    WOLFSSL_ENTER("wolfSSL_SetCertCbCtx");
+    if (ssl)
+        ssl->verifyCbCtx = ctx;
+}
+
+
+/* store context CA Cache addition callback */
+void wolfSSL_CTX_SetCACb(WOLFSSL_CTX* ctx, CallbackCACache cb)
+{
+    if (ctx && ctx->cm)
+        ctx->cm->caCacheCallback = cb;
+}
+
+
+#if defined(PERSIST_CERT_CACHE)
+
+#if !defined(NO_FILESYSTEM)
+
+/* Persist cert cache to file */
+int wolfSSL_CTX_save_cert_cache(WOLFSSL_CTX* ctx, const char* fname)
+{
+    WOLFSSL_ENTER("wolfSSL_CTX_save_cert_cache");
+
+    if (ctx == NULL || fname == NULL)
+        return BAD_FUNC_ARG;
+
+    return CM_SaveCertCache(ctx->cm, fname);
+}
+
+
+/* Persist cert cache from file */
+int wolfSSL_CTX_restore_cert_cache(WOLFSSL_CTX* ctx, const char* fname)
+{
+    WOLFSSL_ENTER("wolfSSL_CTX_restore_cert_cache");
+
+    if (ctx == NULL || fname == NULL)
+        return BAD_FUNC_ARG;
+
+    return CM_RestoreCertCache(ctx->cm, fname);
+}
+
+#endif /* NO_FILESYSTEM */
+
+/* Persist cert cache to memory */
+int wolfSSL_CTX_memsave_cert_cache(WOLFSSL_CTX* ctx, void* mem, int sz, int* used)
+{
+    WOLFSSL_ENTER("wolfSSL_CTX_memsave_cert_cache");
+
+    if (ctx == NULL || mem == NULL || used == NULL || sz <= 0)
+        return BAD_FUNC_ARG;
+
+    return CM_MemSaveCertCache(ctx->cm, mem, sz, used);
+}
+
+
+/* Restore cert cache from memory */
+int wolfSSL_CTX_memrestore_cert_cache(WOLFSSL_CTX* ctx, const void* mem, int sz)
+{
+    WOLFSSL_ENTER("wolfSSL_CTX_memrestore_cert_cache");
+
+    if (ctx == NULL || mem == NULL || sz <= 0)
+        return BAD_FUNC_ARG;
+
+    return CM_MemRestoreCertCache(ctx->cm, mem, sz);
+}
+
+
+/* get how big the the cert cache save buffer needs to be */
+int wolfSSL_CTX_get_cert_cache_memsize(WOLFSSL_CTX* ctx)
+{
+    WOLFSSL_ENTER("wolfSSL_CTX_get_cert_cache_memsize");
+
+    if (ctx == NULL)
+        return BAD_FUNC_ARG;
+
+    return CM_GetCertCacheMemSize(ctx->cm);
+}
+
+#endif /* PERSISTE_CERT_CACHE */
+#endif /* !NO_CERTS */
+
+
+#ifndef NO_SESSION_CACHE
+
+WOLFSSL_SESSION* wolfSSL_get_session(WOLFSSL* ssl)
+{
+    WOLFSSL_ENTER("SSL_get_session");
+    if (ssl)
+        return GetSession(ssl, 0);
+
+    return NULL;
+}
+
+
+int wolfSSL_set_session(WOLFSSL* ssl, WOLFSSL_SESSION* session)
+{
+    WOLFSSL_ENTER("SSL_set_session");
+    if (session)
+        return SetSession(ssl, session);
+
+    return SSL_FAILURE;
+}
+
+
+#ifndef NO_CLIENT_CACHE
+
+/* Associate client session with serverID, find existing or store for saving
+   if newSession flag on, don't reuse existing session
+   SSL_SUCCESS on ok */
+int wolfSSL_SetServerID(WOLFSSL* ssl, const byte* id, int len, int newSession)
+{
+    WOLFSSL_SESSION* session = NULL;
+
+    WOLFSSL_ENTER("wolfSSL_SetServerID");
+
+    if (ssl == NULL || id == NULL || len <= 0)
+        return BAD_FUNC_ARG;
+
+    if (newSession == 0) {
+        session = GetSessionClient(ssl, id, len);
+        if (session) {
+            if (SetSession(ssl, session) != SSL_SUCCESS) {
+                WOLFSSL_MSG("SetSession failed");
+                session = NULL;
+            }
+        }
+    }
+
+    if (session == NULL) {
+        WOLFSSL_MSG("Valid ServerID not cached already");
+
+        ssl->session.idLen = (word16)min(SERVER_ID_LEN, (word32)len);
+        XMEMCPY(ssl->session.serverID, id, ssl->session.idLen);
+    }
+
+    return SSL_SUCCESS;
+}
+
+#endif /* NO_CLIENT_CACHE */
+
+#if defined(PERSIST_SESSION_CACHE)
+
+/* for persistance, if changes to layout need to increment and modify
+   save_session_cache() and restore_session_cache and memory versions too */
+#define WOLFSSL_CACHE_VERSION 2
+
+/* Session Cache Header information */
+typedef struct {
+    int version;     /* cache layout version id */
+    int rows;        /* session rows */
+    int columns;     /* session columns */
+    int sessionSz;   /* sizeof WOLFSSL_SESSION */
+} cache_header_t;
+
+/* current persistence layout is:
+
+   1) cache_header_t
+   2) SessionCache
+   3) ClientCache
+
+   update WOLFSSL_CACHE_VERSION if change layout for the following
+   PERSISTENT_SESSION_CACHE functions
+*/
+
+
+/* get how big the the session cache save buffer needs to be */
+int wolfSSL_get_session_cache_memsize(void)
+{
+    int sz  = (int)(sizeof(SessionCache) + sizeof(cache_header_t));
+
+    #ifndef NO_CLIENT_CACHE
+        sz += (int)(sizeof(ClientCache));
+    #endif
+
+    return sz;
+}
+
+
+/* Persist session cache to memory */
+int wolfSSL_memsave_session_cache(void* mem, int sz)
+{
+    int i;
+    cache_header_t cache_header;
+    SessionRow*    row  = (SessionRow*)((byte*)mem + sizeof(cache_header));
+#ifndef NO_CLIENT_CACHE
+    ClientRow*     clRow;
+#endif
+
+    WOLFSSL_ENTER("wolfSSL_memsave_session_cache");
+
+    if (sz < wolfSSL_get_session_cache_memsize()) {
+        WOLFSSL_MSG("Memory buffer too small");
+        return BUFFER_E;
+    }
+
+    cache_header.version   = WOLFSSL_CACHE_VERSION;
+    cache_header.rows      = SESSION_ROWS;
+    cache_header.columns   = SESSIONS_PER_ROW;
+    cache_header.sessionSz = (int)sizeof(WOLFSSL_SESSION);
+    XMEMCPY(mem, &cache_header, sizeof(cache_header));
+
+    if (LockMutex(&session_mutex) != 0) {
+        WOLFSSL_MSG("Session cache mutex lock failed");
+        return BAD_MUTEX_E;
+    }
+
+    for (i = 0; i < cache_header.rows; ++i)
+        XMEMCPY(row++, SessionCache + i, sizeof(SessionRow));
+
+#ifndef NO_CLIENT_CACHE
+    clRow = (ClientRow*)row;
+    for (i = 0; i < cache_header.rows; ++i)
+        XMEMCPY(clRow++, ClientCache + i, sizeof(ClientRow));
+#endif
+
+    UnLockMutex(&session_mutex);
+
+    WOLFSSL_LEAVE("wolfSSL_memsave_session_cache", SSL_SUCCESS);
+
+    return SSL_SUCCESS;
+}
+
+
+/* Restore the persistant session cache from memory */
+int wolfSSL_memrestore_session_cache(const void* mem, int sz)
+{
+    int    i;
+    cache_header_t cache_header;
+    SessionRow*    row  = (SessionRow*)((byte*)mem + sizeof(cache_header));
+#ifndef NO_CLIENT_CACHE
+    ClientRow*     clRow;
+#endif
+
+    WOLFSSL_ENTER("wolfSSL_memrestore_session_cache");
+
+    if (sz < wolfSSL_get_session_cache_memsize()) {
+        WOLFSSL_MSG("Memory buffer too small");
+        return BUFFER_E;
+    }
+
+    XMEMCPY(&cache_header, mem, sizeof(cache_header));
+    if (cache_header.version   != WOLFSSL_CACHE_VERSION ||
+        cache_header.rows      != SESSION_ROWS ||
+        cache_header.columns   != SESSIONS_PER_ROW ||
+        cache_header.sessionSz != (int)sizeof(WOLFSSL_SESSION)) {
+
+        WOLFSSL_MSG("Session cache header match failed");
+        return CACHE_MATCH_ERROR;
+    }
+
+    if (LockMutex(&session_mutex) != 0) {
+        WOLFSSL_MSG("Session cache mutex lock failed");
+        return BAD_MUTEX_E;
+    }
+
+    for (i = 0; i < cache_header.rows; ++i)
+        XMEMCPY(SessionCache + i, row++, sizeof(SessionRow));
+
+#ifndef NO_CLIENT_CACHE
+    clRow = (ClientRow*)row;
+    for (i = 0; i < cache_header.rows; ++i)
+        XMEMCPY(ClientCache + i, clRow++, sizeof(ClientRow));
+#endif
+
+    UnLockMutex(&session_mutex);
+
+    WOLFSSL_LEAVE("wolfSSL_memrestore_session_cache", SSL_SUCCESS);
+
+    return SSL_SUCCESS;
+}
+
+#if !defined(NO_FILESYSTEM)
+
+/* Persist session cache to file */
+/* doesn't use memsave because of additional memory use */
+int wolfSSL_save_session_cache(const char *fname)
+{
+    XFILE  file;
+    int    ret;
+    int    rc = SSL_SUCCESS;
+    int    i;
+    cache_header_t cache_header;
+
+    WOLFSSL_ENTER("wolfSSL_save_session_cache");
+
+    file = XFOPEN(fname, "w+b");
+    if (file == XBADFILE) {
+        WOLFSSL_MSG("Couldn't open session cache save file");
+        return SSL_BAD_FILE;
+    }
+    cache_header.version   = WOLFSSL_CACHE_VERSION;
+    cache_header.rows      = SESSION_ROWS;
+    cache_header.columns   = SESSIONS_PER_ROW;
+    cache_header.sessionSz = (int)sizeof(WOLFSSL_SESSION);
+
+    /* cache header */
+    ret = (int)XFWRITE(&cache_header, sizeof cache_header, 1, file);
+    if (ret != 1) {
+        WOLFSSL_MSG("Session cache header file write failed");
+        XFCLOSE(file);
+        return FWRITE_ERROR;
+    }
+
+    if (LockMutex(&session_mutex) != 0) {
+        WOLFSSL_MSG("Session cache mutex lock failed");
+        XFCLOSE(file);
+        return BAD_MUTEX_E;
+    }
+
+    /* session cache */
+    for (i = 0; i < cache_header.rows; ++i) {
+        ret = (int)XFWRITE(SessionCache + i, sizeof(SessionRow), 1, file);
+        if (ret != 1) {
+            WOLFSSL_MSG("Session cache member file write failed");
+            rc = FWRITE_ERROR;
+            break;
+        }
+    }
+
+#ifndef NO_CLIENT_CACHE
+    /* client cache */
+    for (i = 0; i < cache_header.rows; ++i) {
+        ret = (int)XFWRITE(ClientCache + i, sizeof(ClientRow), 1, file);
+        if (ret != 1) {
+            WOLFSSL_MSG("Client cache member file write failed");
+            rc = FWRITE_ERROR;
+            break;
+        }
+    }
+#endif /* NO_CLIENT_CACHE */
+
+    UnLockMutex(&session_mutex);
+
+    XFCLOSE(file);
+    WOLFSSL_LEAVE("wolfSSL_save_session_cache", rc);
+
+    return rc;
+}
+
+
+/* Restore the persistant session cache from file */
+/* doesn't use memstore because of additional memory use */
+int wolfSSL_restore_session_cache(const char *fname)
+{
+    XFILE  file;
+    int    rc = SSL_SUCCESS;
+    int    ret;
+    int    i;
+    cache_header_t cache_header;
+
+    WOLFSSL_ENTER("wolfSSL_restore_session_cache");
+
+    file = XFOPEN(fname, "rb");
+    if (file == XBADFILE) {
+        WOLFSSL_MSG("Couldn't open session cache save file");
+        return SSL_BAD_FILE;
+    }
+    /* cache header */
+    ret = (int)XFREAD(&cache_header, sizeof cache_header, 1, file);
+    if (ret != 1) {
+        WOLFSSL_MSG("Session cache header file read failed");
+        XFCLOSE(file);
+        return FREAD_ERROR;
+    }
+    if (cache_header.version   != WOLFSSL_CACHE_VERSION ||
+        cache_header.rows      != SESSION_ROWS ||
+        cache_header.columns   != SESSIONS_PER_ROW ||
+        cache_header.sessionSz != (int)sizeof(WOLFSSL_SESSION)) {
+
+        WOLFSSL_MSG("Session cache header match failed");
+        XFCLOSE(file);
+        return CACHE_MATCH_ERROR;
+    }
+
+    if (LockMutex(&session_mutex) != 0) {
+        WOLFSSL_MSG("Session cache mutex lock failed");
+        XFCLOSE(file);
+        return BAD_MUTEX_E;
+    }
+
+    /* session cache */
+    for (i = 0; i < cache_header.rows; ++i) {
+        ret = (int)XFREAD(SessionCache + i, sizeof(SessionRow), 1, file);
+        if (ret != 1) {
+            WOLFSSL_MSG("Session cache member file read failed");
+            XMEMSET(SessionCache, 0, sizeof SessionCache);
+            rc = FREAD_ERROR;
+            break;
+        }
+    }
+
+#ifndef NO_CLIENT_CACHE
+    /* client cache */
+    for (i = 0; i < cache_header.rows; ++i) {
+        ret = (int)XFREAD(ClientCache + i, sizeof(ClientRow), 1, file);
+        if (ret != 1) {
+            WOLFSSL_MSG("Client cache member file read failed");
+            XMEMSET(ClientCache, 0, sizeof ClientCache);
+            rc = FREAD_ERROR;
+            break;
+        }
+    }
+
+#endif /* NO_CLIENT_CACHE */
+
+    UnLockMutex(&session_mutex);
+
+    XFCLOSE(file);
+    WOLFSSL_LEAVE("wolfSSL_restore_session_cache", rc);
+
+    return rc;
+}
+
+#endif /* !NO_FILESYSTEM */
+#endif /* PERSIST_SESSION_CACHE */
+#endif /* NO_SESSION_CACHE */
+
+
+void wolfSSL_load_error_strings(void)   /* compatibility only */
+{}
+
+
+int wolfSSL_library_init(void)
+{
+    WOLFSSL_ENTER("SSL_library_init");
+    if (wolfSSL_Init() == SSL_SUCCESS)
+        return SSL_SUCCESS;
+    else
+        return SSL_FATAL_ERROR;
+}
+
+
+#ifdef HAVE_SECRET_CALLBACK
+
+int wolfSSL_set_session_secret_cb(WOLFSSL* ssl, SessionSecretCb cb, void* ctx)
+{
+    WOLFSSL_ENTER("wolfSSL_set_session_secret_cb");
+    if (ssl == NULL)
+        return SSL_FATAL_ERROR;
+
+    ssl->sessionSecretCb = cb;
+    ssl->sessionSecretCtx = ctx;
+    /* If using a pre-set key, assume session resumption. */
+    ssl->session.sessionIDSz = 0;
+    ssl->options.resuming = 1;
+
+    return SSL_SUCCESS;
+}
+
+#endif
+
+
+#ifndef NO_SESSION_CACHE
+
+/* on by default if built in but allow user to turn off */
+long wolfSSL_CTX_set_session_cache_mode(WOLFSSL_CTX* ctx, long mode)
+{
+    WOLFSSL_ENTER("SSL_CTX_set_session_cache_mode");
+    if (mode == SSL_SESS_CACHE_OFF)
+        ctx->sessionCacheOff = 1;
+
+    if (mode == SSL_SESS_CACHE_NO_AUTO_CLEAR)
+        ctx->sessionCacheFlushOff = 1;
+
+    return SSL_SUCCESS;
+}
+
+#endif /* NO_SESSION_CACHE */
+
+
+#if !defined(NO_CERTS)
+#if defined(PERSIST_CERT_CACHE)
+
+
+#define WOLFSSL_CACHE_CERT_VERSION 1
+
+typedef struct {
+    int version;                 /* cache cert layout version id */
+    int rows;                    /* hash table rows, CA_TABLE_SIZE */
+    int columns[CA_TABLE_SIZE];  /* columns per row on list */
+    int signerSz;                /* sizeof Signer object */
+} CertCacheHeader;
+
+/* current cert persistance layout is:
+
+   1) CertCacheHeader
+   2) caTable
+
+   update WOLFSSL_CERT_CACHE_VERSION if change layout for the following
+   PERSIST_CERT_CACHE functions
+*/
+
+
+/* Return memory needed to persist this signer, have lock */
+static INLINE int GetSignerMemory(Signer* signer)
+{
+    int sz = sizeof(signer->pubKeySize) + sizeof(signer->keyOID)
+           + sizeof(signer->nameLen)    + sizeof(signer->subjectNameHash);
+
+#if !defined(NO_SKID)
+        sz += (int)sizeof(signer->subjectKeyIdHash);
+#endif
+
+    /* add dynamic bytes needed */
+    sz += signer->pubKeySize;
+    sz += signer->nameLen;
+
+    return sz;
+}
+
+
+/* Return memory needed to persist this row, have lock */
+static INLINE int GetCertCacheRowMemory(Signer* row)
+{
+    int sz = 0;
+
+    while (row) {
+        sz += GetSignerMemory(row);
+        row = row->next;
+    }
+
+    return sz;
+}
+
+
+/* get the size of persist cert cache, have lock */
+static INLINE int GetCertCacheMemSize(WOLFSSL_CERT_MANAGER* cm)
+{
+    int sz;
+    int i;
+
+    sz = sizeof(CertCacheHeader);
+
+    for (i = 0; i < CA_TABLE_SIZE; i++)
+        sz += GetCertCacheRowMemory(cm->caTable[i]);
+
+    return sz;
+}
+
+
+/* Store cert cache header columns with number of items per list, have lock */
+static INLINE void SetCertHeaderColumns(WOLFSSL_CERT_MANAGER* cm, int* columns)
+{
+    int     i;
+    Signer* row;
+
+    for (i = 0; i < CA_TABLE_SIZE; i++) {
+        int count = 0;
+        row = cm->caTable[i];
+
+        while (row) {
+            ++count;
+            row = row->next;
+        }
+        columns[i] = count;
+    }
+}
+
+
+/* Restore whole cert row from memory, have lock, return bytes consumed,
+   < 0 on error, have lock */
+static INLINE int RestoreCertRow(WOLFSSL_CERT_MANAGER* cm, byte* current,
+                                 int row, int listSz, const byte* end)
+{
+    int idx = 0;
+
+    if (listSz < 0) {
+        WOLFSSL_MSG("Row header corrupted, negative value");
+        return PARSE_ERROR;
+    }
+
+    while (listSz) {
+        Signer* signer;
+        byte*   start = current + idx;  /* for end checks on this signer */
+        int     minSz = sizeof(signer->pubKeySize) + sizeof(signer->keyOID) +
+                      sizeof(signer->nameLen) + sizeof(signer->subjectNameHash);
+        #ifndef NO_SKID
+                minSz += (int)sizeof(signer->subjectKeyIdHash);
+        #endif
+
+        if (start + minSz > end) {
+            WOLFSSL_MSG("Would overread restore buffer");
+            return BUFFER_E;
+        }
+        signer = MakeSigner(cm->heap);
+        if (signer == NULL)
+            return MEMORY_E;
+
+        /* pubKeySize */
+        XMEMCPY(&signer->pubKeySize, current + idx, sizeof(signer->pubKeySize));
+        idx += (int)sizeof(signer->pubKeySize);
+
+        /* keyOID */
+        XMEMCPY(&signer->keyOID, current + idx, sizeof(signer->keyOID));
+        idx += (int)sizeof(signer->keyOID);
+
+        /* pulicKey */
+        if (start + minSz + signer->pubKeySize > end) {
+            WOLFSSL_MSG("Would overread restore buffer");
+            FreeSigner(signer, cm->heap);
+            return BUFFER_E;
+        }
+        signer->publicKey = (byte*)XMALLOC(signer->pubKeySize, cm->heap,
+                                           DYNAMIC_TYPE_KEY);
+        if (signer->publicKey == NULL) {
+            FreeSigner(signer, cm->heap);
+            return MEMORY_E;
+        }
+
+        XMEMCPY(signer->publicKey, current + idx, signer->pubKeySize);
+        idx += signer->pubKeySize;
+
+        /* nameLen */
+        XMEMCPY(&signer->nameLen, current + idx, sizeof(signer->nameLen));
+        idx += (int)sizeof(signer->nameLen);
+
+        /* name */
+        if (start + minSz + signer->pubKeySize + signer->nameLen > end) {
+            WOLFSSL_MSG("Would overread restore buffer");
+            FreeSigner(signer, cm->heap);
+            return BUFFER_E;
+        }
+        signer->name = (char*)XMALLOC(signer->nameLen, cm->heap,
+                                      DYNAMIC_TYPE_SUBJECT_CN);
+        if (signer->name == NULL) {
+            FreeSigner(signer, cm->heap);
+            return MEMORY_E;
+        }
+
+        XMEMCPY(signer->name, current + idx, signer->nameLen);
+        idx += signer->nameLen;
+
+        /* subjectNameHash */
+        XMEMCPY(signer->subjectNameHash, current + idx, SIGNER_DIGEST_SIZE);
+        idx += SIGNER_DIGEST_SIZE;
+
+        #ifndef NO_SKID
+            /* subjectKeyIdHash */
+            XMEMCPY(signer->subjectKeyIdHash, current + idx,SIGNER_DIGEST_SIZE);
+            idx += SIGNER_DIGEST_SIZE;
+        #endif
+
+        signer->next = cm->caTable[row];
+        cm->caTable[row] = signer;
+
+        --listSz;
+    }
+
+    return idx;
+}
+
+
+/* Store whole cert row into memory, have lock, return bytes added */
+static INLINE int StoreCertRow(WOLFSSL_CERT_MANAGER* cm, byte* current, int row)
+{
+    int     added  = 0;
+    Signer* list   = cm->caTable[row];
+
+    while (list) {
+        XMEMCPY(current + added, &list->pubKeySize, sizeof(list->pubKeySize));
+        added += (int)sizeof(list->pubKeySize);
+
+        XMEMCPY(current + added, &list->keyOID,     sizeof(list->keyOID));
+        added += (int)sizeof(list->keyOID);
+
+        XMEMCPY(current + added, list->publicKey, list->pubKeySize);
+        added += list->pubKeySize;
+
+        XMEMCPY(current + added, &list->nameLen, sizeof(list->nameLen));
+        added += (int)sizeof(list->nameLen);
+
+        XMEMCPY(current + added, list->name, list->nameLen);
+        added += list->nameLen;
+
+        XMEMCPY(current + added, list->subjectNameHash, SIGNER_DIGEST_SIZE);
+        added += SIGNER_DIGEST_SIZE;
+
+        #ifndef NO_SKID
+            XMEMCPY(current + added, list->subjectKeyIdHash,SIGNER_DIGEST_SIZE);
+            added += SIGNER_DIGEST_SIZE;
+        #endif
+
+        list = list->next;
+    }
+
+    return added;
+}
+
+
+/* Persist cert cache to memory, have lock */
+static INLINE int DoMemSaveCertCache(WOLFSSL_CERT_MANAGER* cm, void* mem, int sz)
+{
+    int realSz;
+    int ret = SSL_SUCCESS;
+    int i;
+
+    WOLFSSL_ENTER("DoMemSaveCertCache");
+
+    realSz = GetCertCacheMemSize(cm);
+    if (realSz > sz) {
+        WOLFSSL_MSG("Mem output buffer too small");
+        ret = BUFFER_E;
+    }
+    else {
+        byte*           current;
+        CertCacheHeader hdr;
+
+        hdr.version  = WOLFSSL_CACHE_CERT_VERSION;
+        hdr.rows     = CA_TABLE_SIZE;
+        SetCertHeaderColumns(cm, hdr.columns);
+        hdr.signerSz = (int)sizeof(Signer);
+
+        XMEMCPY(mem, &hdr, sizeof(CertCacheHeader));
+        current = (byte*)mem + sizeof(CertCacheHeader);
+
+        for (i = 0; i < CA_TABLE_SIZE; ++i)
+            current += StoreCertRow(cm, current, i);
+    }
+
+    return ret;
+}
+
+
+#if !defined(NO_FILESYSTEM)
+
+/* Persist cert cache to file */
+int CM_SaveCertCache(WOLFSSL_CERT_MANAGER* cm, const char* fname)
+{
+    XFILE file;
+    int   rc = SSL_SUCCESS;
+    int   memSz;
+    byte* mem;
+
+    WOLFSSL_ENTER("CM_SaveCertCache");
+
+    file = XFOPEN(fname, "w+b");
+    if (file == XBADFILE) {
+       WOLFSSL_MSG("Couldn't open cert cache save file");
+       return SSL_BAD_FILE;
+    }
+
+    if (LockMutex(&cm->caLock) != 0) {
+        WOLFSSL_MSG("LockMutex on caLock failed");
+        XFCLOSE(file);
+        return BAD_MUTEX_E;
+    }
+
+    memSz = GetCertCacheMemSize(cm);
+    mem   = (byte*)XMALLOC(memSz, cm->heap, DYNAMIC_TYPE_TMP_BUFFER);
+    if (mem == NULL) {
+        WOLFSSL_MSG("Alloc for tmp buffer failed");
+        rc = MEMORY_E;
+    } else {
+        rc = DoMemSaveCertCache(cm, mem, memSz);
+        if (rc == SSL_SUCCESS) {
+            int ret = (int)XFWRITE(mem, memSz, 1, file);
+            if (ret != 1) {
+                WOLFSSL_MSG("Cert cache file write failed");
+                rc = FWRITE_ERROR;
+            }
+        }
+        XFREE(mem, cm->heap, DYNAMIC_TYPE_TMP_BUFFER);
+    }
+
+    UnLockMutex(&cm->caLock);
+    XFCLOSE(file);
+
+    return rc;
+}
+
+
+/* Restore cert cache from file */
+int CM_RestoreCertCache(WOLFSSL_CERT_MANAGER* cm, const char* fname)
+{
+    XFILE file;
+    int   rc = SSL_SUCCESS;
+    int   ret;
+    int   memSz;
+    byte* mem;
+
+    WOLFSSL_ENTER("CM_RestoreCertCache");
+
+    file = XFOPEN(fname, "rb");
+    if (file == XBADFILE) {
+       WOLFSSL_MSG("Couldn't open cert cache save file");
+       return SSL_BAD_FILE;
+    }
+
+    XFSEEK(file, 0, XSEEK_END);
+    memSz = (int)XFTELL(file);
+    XREWIND(file);
+
+    if (memSz <= 0) {
+        WOLFSSL_MSG("Bad file size");
+        XFCLOSE(file);
+        return SSL_BAD_FILE;
+    }
+
+    mem = (byte*)XMALLOC(memSz, cm->heap, DYNAMIC_TYPE_TMP_BUFFER);
+    if (mem == NULL) {
+        WOLFSSL_MSG("Alloc for tmp buffer failed");
+        XFCLOSE(file);
+        return MEMORY_E;
+    }
+
+    ret = (int)XFREAD(mem, memSz, 1, file);
+    if (ret != 1) {
+        WOLFSSL_MSG("Cert file read error");
+        rc = FREAD_ERROR;
+    } else {
+        rc = CM_MemRestoreCertCache(cm, mem, memSz);
+        if (rc != SSL_SUCCESS) {
+            WOLFSSL_MSG("Mem restore cert cache failed");
+        }
+    }
+
+    XFREE(mem, cm->heap, DYNAMIC_TYPE_TMP_BUFFER);
+    XFCLOSE(file);
+
+    return rc;
+}
+
+#endif /* NO_FILESYSTEM */
+
+
+/* Persist cert cache to memory */
+int CM_MemSaveCertCache(WOLFSSL_CERT_MANAGER* cm, void* mem, int sz, int* used)
+{
+    int ret = SSL_SUCCESS;
+
+    WOLFSSL_ENTER("CM_MemSaveCertCache");
+
+    if (LockMutex(&cm->caLock) != 0) {
+        WOLFSSL_MSG("LockMutex on caLock failed");
+        return BAD_MUTEX_E;
+    }
+
+    ret = DoMemSaveCertCache(cm, mem, sz);
+    if (ret == SSL_SUCCESS)
+        *used  = GetCertCacheMemSize(cm);
+
+    UnLockMutex(&cm->caLock);
+
+    return ret;
+}
+
+
+/* Restore cert cache from memory */
+int CM_MemRestoreCertCache(WOLFSSL_CERT_MANAGER* cm, const void* mem, int sz)
+{
+    int ret = SSL_SUCCESS;
+    int i;
+    CertCacheHeader* hdr = (CertCacheHeader*)mem;
+    byte*            current = (byte*)mem + sizeof(CertCacheHeader);
+    byte*            end     = (byte*)mem + sz;  /* don't go over */
+
+    WOLFSSL_ENTER("CM_MemRestoreCertCache");
+
+    if (current > end) {
+        WOLFSSL_MSG("Cert Cache Memory buffer too small");
+        return BUFFER_E;
+    }
+
+    if (hdr->version  != WOLFSSL_CACHE_CERT_VERSION ||
+        hdr->rows     != CA_TABLE_SIZE ||
+        hdr->signerSz != (int)sizeof(Signer)) {
+
+        WOLFSSL_MSG("Cert Cache Memory header mismatch");
+        return CACHE_MATCH_ERROR;
+    }
+
+    if (LockMutex(&cm->caLock) != 0) {
+        WOLFSSL_MSG("LockMutex on caLock failed");
+        return BAD_MUTEX_E;
+    }
+
+    FreeSignerTable(cm->caTable, CA_TABLE_SIZE, cm->heap);
+
+    for (i = 0; i < CA_TABLE_SIZE; ++i) {
+        int added = RestoreCertRow(cm, current, i, hdr->columns[i], end);
+        if (added < 0) {
+            WOLFSSL_MSG("RestoreCertRow error");
+            ret = added;
+            break;
+        }
+        current += added;
+    }
+
+    UnLockMutex(&cm->caLock);
+
+    return ret;
+}
+
+
+/* get how big the the cert cache save buffer needs to be */
+int CM_GetCertCacheMemSize(WOLFSSL_CERT_MANAGER* cm)
+{
+    int sz;
+
+    WOLFSSL_ENTER("CM_GetCertCacheMemSize");
+
+    if (LockMutex(&cm->caLock) != 0) {
+        WOLFSSL_MSG("LockMutex on caLock failed");
+        return BAD_MUTEX_E;
+    }
+
+    sz = GetCertCacheMemSize(cm);
+
+    UnLockMutex(&cm->caLock);
+
+    return sz;
+}
+
+#endif /* PERSIST_CERT_CACHE */
+#endif /* NO_CERTS */
+
+
+int wolfSSL_CTX_set_cipher_list(WOLFSSL_CTX* ctx, const char* list)
+{
+    WOLFSSL_ENTER("wolfSSL_CTX_set_cipher_list");
+
+    /* alloc/init on demand only */
+    if (ctx->suites == NULL) {
+        ctx->suites = (Suites*)XMALLOC(sizeof(Suites), ctx->heap,
+                                       DYNAMIC_TYPE_SUITES);
+        if (ctx->suites == NULL) {
+            WOLFSSL_MSG("Memory alloc for Suites failed");
+            return SSL_FAILURE;
+        }
+        XMEMSET(ctx->suites, 0, sizeof(Suites));
+    }
+
+    return (SetCipherList(ctx->suites, list)) ? SSL_SUCCESS : SSL_FAILURE;
+}
+
+
+int wolfSSL_set_cipher_list(WOLFSSL* ssl, const char* list)
+{
+    WOLFSSL_ENTER("wolfSSL_set_cipher_list");
+    return (SetCipherList(ssl->suites, list)) ? SSL_SUCCESS : SSL_FAILURE;
+}
+
+
+#ifndef WOLFSSL_LEANPSK
+#ifdef WOLFSSL_DTLS
+
+int wolfSSL_dtls_get_current_timeout(WOLFSSL* ssl)
+{
+    (void)ssl;
+
+    return ssl->dtls_timeout;
+}
+
+
+/* user may need to alter init dtls recv timeout, SSL_SUCCESS on ok */
+int wolfSSL_dtls_set_timeout_init(WOLFSSL* ssl, int timeout)
+{
+    if (ssl == NULL || timeout < 0)
+        return BAD_FUNC_ARG;
+
+    if (timeout > ssl->dtls_timeout_max) {
+        WOLFSSL_MSG("Can't set dtls timeout init greater than dtls timeout max");
+        return BAD_FUNC_ARG;
+    }
+
+    ssl->dtls_timeout_init = timeout;
+    ssl->dtls_timeout = timeout;
+
+    return SSL_SUCCESS;
+}
+
+
+/* user may need to alter max dtls recv timeout, SSL_SUCCESS on ok */
+int wolfSSL_dtls_set_timeout_max(WOLFSSL* ssl, int timeout)
+{
+    if (ssl == NULL || timeout < 0)
+        return BAD_FUNC_ARG;
+
+    if (timeout < ssl->dtls_timeout_init) {
+        WOLFSSL_MSG("Can't set dtls timeout max less than dtls timeout init");
+        return BAD_FUNC_ARG;
+    }
+
+    ssl->dtls_timeout_max = timeout;
+
+    return SSL_SUCCESS;
+}
+
+
+int wolfSSL_dtls_got_timeout(WOLFSSL* ssl)
+{
+    int result = SSL_SUCCESS;
+
+    DtlsMsgListDelete(ssl->dtls_msg_list, ssl->heap);
+    ssl->dtls_msg_list = NULL;
+    if (DtlsPoolTimeout(ssl) < 0 || DtlsPoolSend(ssl) < 0) {
+        result = SSL_FATAL_ERROR;
+    }
+    return result;
+}
+
+#endif /* DTLS */
+#endif /* LEANPSK */
+
+
+/* client only parts */
+#ifndef NO_WOLFSSL_CLIENT
+
+    #ifndef NO_OLD_TLS
+    WOLFSSL_METHOD* wolfSSLv3_client_method(void)
+    {
+        WOLFSSL_METHOD* method =
+                              (WOLFSSL_METHOD*) XMALLOC(sizeof(WOLFSSL_METHOD), 0,
+                                                       DYNAMIC_TYPE_METHOD);
+        WOLFSSL_ENTER("SSLv3_client_method");
+        if (method)
+            InitSSL_Method(method, MakeSSLv3());
+        return method;
+    }
+    #endif
+
+    #ifdef WOLFSSL_DTLS
+
+        #ifndef NO_OLD_TLS
+        WOLFSSL_METHOD* wolfDTLSv1_client_method(void)
+        {
+            WOLFSSL_METHOD* method =
+                              (WOLFSSL_METHOD*) XMALLOC(sizeof(WOLFSSL_METHOD), 0,
+                                                       DYNAMIC_TYPE_METHOD);
+            WOLFSSL_ENTER("DTLSv1_client_method");
+            if (method)
+                InitSSL_Method(method, MakeDTLSv1());
+            return method;
+        }
+        #endif  /* NO_OLD_TLS */
+
+        WOLFSSL_METHOD* wolfDTLSv1_2_client_method(void)
+        {
+            WOLFSSL_METHOD* method =
+                              (WOLFSSL_METHOD*) XMALLOC(sizeof(WOLFSSL_METHOD), 0,
+                                                       DYNAMIC_TYPE_METHOD);
+            WOLFSSL_ENTER("DTLSv1_2_client_method");
+            if (method)
+                InitSSL_Method(method, MakeDTLSv1_2());
+            return method;
+        }
+    #endif
+
+
+    /* please see note at top of README if you get an error from connect */
+    int wolfSSL_connect(WOLFSSL* ssl)
+    {
+        int neededState;
+
+        WOLFSSL_ENTER("SSL_connect()");
+
+        #ifdef HAVE_ERRNO_H
+            errno = 0;
+        #endif
+
+        if (ssl->options.side != WOLFSSL_CLIENT_END) {
+            WOLFSSL_ERROR(ssl->error = SIDE_ERROR);
+            return SSL_FATAL_ERROR;
+        }
+
+        #ifdef WOLFSSL_DTLS
+            if (ssl->version.major == DTLS_MAJOR) {
+                ssl->options.dtls   = 1;
+                ssl->options.tls    = 1;
+                ssl->options.tls1_1 = 1;
+
+                if (DtlsPoolInit(ssl) != 0) {
+                    ssl->error = MEMORY_ERROR;
+                    WOLFSSL_ERROR(ssl->error);
+                    return SSL_FATAL_ERROR;
+                }
+            }
+        #endif
+
+        if (ssl->buffers.outputBuffer.length > 0) {
+            if ( (ssl->error = SendBuffered(ssl)) == 0) {
+                ssl->options.connectState++;
+                WOLFSSL_MSG("connect state: Advanced from buffered send");
+            }
+            else {
+                WOLFSSL_ERROR(ssl->error);
+                return SSL_FATAL_ERROR;
+            }
+        }
+
+        switch (ssl->options.connectState) {
+
+        case CONNECT_BEGIN :
+            /* always send client hello first */
+            if ( (ssl->error = SendClientHello(ssl)) != 0) {
+                WOLFSSL_ERROR(ssl->error);
+                return SSL_FATAL_ERROR;
+            }
+            ssl->options.connectState = CLIENT_HELLO_SENT;
+            WOLFSSL_MSG("connect state: CLIENT_HELLO_SENT");
+
+        case CLIENT_HELLO_SENT :
+            neededState = ssl->options.resuming ? SERVER_FINISHED_COMPLETE :
+                                          SERVER_HELLODONE_COMPLETE;
+            #ifdef WOLFSSL_DTLS
+                /* In DTLS, when resuming, we can go straight to FINISHED,
+                 * or do a cookie exchange and then skip to FINISHED, assume
+                 * we need the cookie exchange first. */
+                if (ssl->options.dtls)
+                    neededState = SERVER_HELLOVERIFYREQUEST_COMPLETE;
+            #endif
+            /* get response */
+            while (ssl->options.serverState < neededState) {
+                if ( (ssl->error = ProcessReply(ssl)) < 0) {
+                    WOLFSSL_ERROR(ssl->error);
+                    return SSL_FATAL_ERROR;
+                }
+                /* if resumption failed, reset needed state */
+                else if (neededState == SERVER_FINISHED_COMPLETE)
+                    if (!ssl->options.resuming) {
+                        if (!ssl->options.dtls)
+                            neededState = SERVER_HELLODONE_COMPLETE;
+                        else
+                            neededState = SERVER_HELLOVERIFYREQUEST_COMPLETE;
+                    }
+            }
+
+            ssl->options.connectState = HELLO_AGAIN;
+            WOLFSSL_MSG("connect state: HELLO_AGAIN");
+
+        case HELLO_AGAIN :
+            if (ssl->options.certOnly)
+                return SSL_SUCCESS;
+
+            #ifdef WOLFSSL_DTLS
+                if (ssl->options.dtls) {
+                    /* re-init hashes, exclude first hello and verify request */
+#ifndef NO_OLD_TLS
+                    wc_InitMd5(&ssl->hsHashes->hashMd5);
+                    if ( (ssl->error = wc_InitSha(&ssl->hsHashes->hashSha))
+                                                                         != 0) {
+                        WOLFSSL_ERROR(ssl->error);
+                        return SSL_FATAL_ERROR;
+                    }
+#endif
+                    if (IsAtLeastTLSv1_2(ssl)) {
+                        #ifndef NO_SHA256
+                            if ( (ssl->error = wc_InitSha256(
+                                            &ssl->hsHashes->hashSha256)) != 0) {
+                                WOLFSSL_ERROR(ssl->error);
+                                return SSL_FATAL_ERROR;
+                            }
+                        #endif
+                        #ifdef WOLFSSL_SHA384
+                            if ( (ssl->error = wc_InitSha384(
+                                            &ssl->hsHashes->hashSha384)) != 0) {
+                                WOLFSSL_ERROR(ssl->error);
+                                return SSL_FATAL_ERROR;
+                            }
+                        #endif
+                        #ifdef WOLFSSL_SHA512
+                            if ( (ssl->error = wc_InitSha512(
+                                            &ssl->hsHashes->hashSha512)) != 0) {
+                                WOLFSSL_ERROR(ssl->error);
+                                return SSL_FATAL_ERROR;
+                            }
+                        #endif
+                    }
+                    if ( (ssl->error = SendClientHello(ssl)) != 0) {
+                        WOLFSSL_ERROR(ssl->error);
+                        return SSL_FATAL_ERROR;
+                    }
+                }
+            #endif
+
+            ssl->options.connectState = HELLO_AGAIN_REPLY;
+            WOLFSSL_MSG("connect state: HELLO_AGAIN_REPLY");
+
+        case HELLO_AGAIN_REPLY :
+            #ifdef WOLFSSL_DTLS
+                if (ssl->options.dtls) {
+                    neededState = ssl->options.resuming ?
+                           SERVER_FINISHED_COMPLETE : SERVER_HELLODONE_COMPLETE;
+
+                    /* get response */
+                    while (ssl->options.serverState < neededState) {
+                        if ( (ssl->error = ProcessReply(ssl)) < 0) {
+                                WOLFSSL_ERROR(ssl->error);
+                                return SSL_FATAL_ERROR;
+                        }
+                        /* if resumption failed, reset needed state */
+                        else if (neededState == SERVER_FINISHED_COMPLETE)
+                            if (!ssl->options.resuming)
+                                neededState = SERVER_HELLODONE_COMPLETE;
+                    }
+                }
+            #endif
+
+            ssl->options.connectState = FIRST_REPLY_DONE;
+            WOLFSSL_MSG("connect state: FIRST_REPLY_DONE");
+
+        case FIRST_REPLY_DONE :
+            #ifndef NO_CERTS
+                if (ssl->options.sendVerify) {
+                    if ( (ssl->error = SendCertificate(ssl)) != 0) {
+                        WOLFSSL_ERROR(ssl->error);
+                        return SSL_FATAL_ERROR;
+                    }
+                    WOLFSSL_MSG("sent: certificate");
+                }
+
+            #endif
+            ssl->options.connectState = FIRST_REPLY_FIRST;
+            WOLFSSL_MSG("connect state: FIRST_REPLY_FIRST");
+
+        case FIRST_REPLY_FIRST :
+            if (!ssl->options.resuming) {
+                if ( (ssl->error = SendClientKeyExchange(ssl)) != 0) {
+                    WOLFSSL_ERROR(ssl->error);
+                    return SSL_FATAL_ERROR;
+                }
+                WOLFSSL_MSG("sent: client key exchange");
+            }
+
+            ssl->options.connectState = FIRST_REPLY_SECOND;
+            WOLFSSL_MSG("connect state: FIRST_REPLY_SECOND");
+
+        case FIRST_REPLY_SECOND :
+            #ifndef NO_CERTS
+                if (ssl->options.sendVerify) {
+                    if ( (ssl->error = SendCertificateVerify(ssl)) != 0) {
+                        WOLFSSL_ERROR(ssl->error);
+                        return SSL_FATAL_ERROR;
+                    }
+                    WOLFSSL_MSG("sent: certificate verify");
+                }
+            #endif
+            ssl->options.connectState = FIRST_REPLY_THIRD;
+            WOLFSSL_MSG("connect state: FIRST_REPLY_THIRD");
+
+        case FIRST_REPLY_THIRD :
+            if ( (ssl->error = SendChangeCipher(ssl)) != 0) {
+                WOLFSSL_ERROR(ssl->error);
+                return SSL_FATAL_ERROR;
+            }
+            WOLFSSL_MSG("sent: change cipher spec");
+            ssl->options.connectState = FIRST_REPLY_FOURTH;
+            WOLFSSL_MSG("connect state: FIRST_REPLY_FOURTH");
+
+        case FIRST_REPLY_FOURTH :
+            if ( (ssl->error = SendFinished(ssl)) != 0) {
+                WOLFSSL_ERROR(ssl->error);
+                return SSL_FATAL_ERROR;
+            }
+            WOLFSSL_MSG("sent: finished");
+            ssl->options.connectState = FINISHED_DONE;
+            WOLFSSL_MSG("connect state: FINISHED_DONE");
+
+        case FINISHED_DONE :
+            /* get response */
+            while (ssl->options.serverState < SERVER_FINISHED_COMPLETE)
+                if ( (ssl->error = ProcessReply(ssl)) < 0) {
+                    WOLFSSL_ERROR(ssl->error);
+                    return SSL_FATAL_ERROR;
+                }
+
+            ssl->options.connectState = SECOND_REPLY_DONE;
+            WOLFSSL_MSG("connect state: SECOND_REPLY_DONE");
+
+        case SECOND_REPLY_DONE:
+#ifndef NO_HANDSHAKE_DONE_CB
+            if (ssl->hsDoneCb) {
+                int cbret = ssl->hsDoneCb(ssl, ssl->hsDoneCtx);
+                if (cbret < 0) {
+                    ssl->error = cbret;
+                    WOLFSSL_MSG("HandShake Done Cb don't continue error");
+                    return SSL_FATAL_ERROR;
+                }
+            }
+#endif /* NO_HANDSHAKE_DONE_CB */
+            FreeHandshakeResources(ssl);
+            WOLFSSL_LEAVE("SSL_connect()", SSL_SUCCESS);
+            return SSL_SUCCESS;
+
+        default:
+            WOLFSSL_MSG("Unknown connect state ERROR");
+            return SSL_FATAL_ERROR; /* unknown connect state */
+        }
+    }
+
+#endif /* NO_WOLFSSL_CLIENT */
+
+
+/* server only parts */
+#ifndef NO_WOLFSSL_SERVER
+
+    #ifndef NO_OLD_TLS
+    WOLFSSL_METHOD* wolfSSLv3_server_method(void)
+    {
+        WOLFSSL_METHOD* method =
+                              (WOLFSSL_METHOD*) XMALLOC(sizeof(WOLFSSL_METHOD), 0,
+                                                       DYNAMIC_TYPE_METHOD);
+        WOLFSSL_ENTER("SSLv3_server_method");
+        if (method) {
+            InitSSL_Method(method, MakeSSLv3());
+            method->side = WOLFSSL_SERVER_END;
+        }
+        return method;
+    }
+    #endif
+
+
+    #ifdef WOLFSSL_DTLS
+
+        #ifndef NO_OLD_TLS
+        WOLFSSL_METHOD* wolfDTLSv1_server_method(void)
+        {
+            WOLFSSL_METHOD* method =
+                              (WOLFSSL_METHOD*) XMALLOC(sizeof(WOLFSSL_METHOD),
+                                                        0, DYNAMIC_TYPE_METHOD);
+            WOLFSSL_ENTER("DTLSv1_server_method");
+            if (method) {
+                InitSSL_Method(method, MakeDTLSv1());
+                method->side = WOLFSSL_SERVER_END;
+            }
+            return method;
+        }
+        #endif /* NO_OLD_TLS */
+
+        WOLFSSL_METHOD* wolfDTLSv1_2_server_method(void)
+        {
+            WOLFSSL_METHOD* method =
+                              (WOLFSSL_METHOD*) XMALLOC(sizeof(WOLFSSL_METHOD),
+                                                        0, DYNAMIC_TYPE_METHOD);
+            WOLFSSL_ENTER("DTLSv1_2_server_method");
+            if (method) {
+                InitSSL_Method(method, MakeDTLSv1_2());
+                method->side = WOLFSSL_SERVER_END;
+            }
+            return method;
+        }
+    #endif
+
+
+    int wolfSSL_accept(WOLFSSL* ssl)
+    {
+        byte havePSK = 0;
+        byte haveAnon = 0;
+        WOLFSSL_ENTER("SSL_accept()");
+
+        #ifdef HAVE_ERRNO_H
+            errno = 0;
+        #endif
+
+        #ifndef NO_PSK
+            havePSK = ssl->options.havePSK;
+        #endif
+        (void)havePSK;
+
+        #ifdef HAVE_ANON
+            haveAnon = ssl->options.haveAnon;
+        #endif
+        (void)haveAnon;
+
+        if (ssl->options.side != WOLFSSL_SERVER_END) {
+            WOLFSSL_ERROR(ssl->error = SIDE_ERROR);
+            return SSL_FATAL_ERROR;
+        }
+
+        #ifndef NO_CERTS
+            /* in case used set_accept_state after init */
+            if (!havePSK && !haveAnon &&
+                            (ssl->buffers.certificate.buffer == NULL ||
+                             ssl->buffers.key.buffer == NULL)) {
+                WOLFSSL_MSG("accept error: don't have server cert and key");
+                ssl->error = NO_PRIVATE_KEY;
+                WOLFSSL_ERROR(ssl->error);
+                return SSL_FATAL_ERROR;
+            }
+        #endif
+
+        #ifdef WOLFSSL_DTLS
+            if (ssl->version.major == DTLS_MAJOR) {
+                ssl->options.dtls   = 1;
+                ssl->options.tls    = 1;
+                ssl->options.tls1_1 = 1;
+
+                if (DtlsPoolInit(ssl) != 0) {
+                    ssl->error = MEMORY_ERROR;
+                    WOLFSSL_ERROR(ssl->error);
+                    return SSL_FATAL_ERROR;
+                }
+            }
+        #endif
+
+        if (ssl->buffers.outputBuffer.length > 0) {
+            if ( (ssl->error = SendBuffered(ssl)) == 0) {
+                ssl->options.acceptState++;
+                WOLFSSL_MSG("accept state: Advanced from buffered send");
+            }
+            else {
+                WOLFSSL_ERROR(ssl->error);
+                return SSL_FATAL_ERROR;
+            }
+        }
+
+        switch (ssl->options.acceptState) {
+
+        case ACCEPT_BEGIN :
+            /* get response */
+            while (ssl->options.clientState < CLIENT_HELLO_COMPLETE)
+                if ( (ssl->error = ProcessReply(ssl)) < 0) {
+                    WOLFSSL_ERROR(ssl->error);
+                    return SSL_FATAL_ERROR;
+                }
+            ssl->options.acceptState = ACCEPT_CLIENT_HELLO_DONE;
+            WOLFSSL_MSG("accept state ACCEPT_CLIENT_HELLO_DONE");
+
+        case ACCEPT_CLIENT_HELLO_DONE :
+            #ifdef WOLFSSL_DTLS
+                if (ssl->options.dtls)
+                    if ( (ssl->error = SendHelloVerifyRequest(ssl)) != 0) {
+                        WOLFSSL_ERROR(ssl->error);
+                        return SSL_FATAL_ERROR;
+                    }
+            #endif
+            ssl->options.acceptState = HELLO_VERIFY_SENT;
+            WOLFSSL_MSG("accept state HELLO_VERIFY_SENT");
+
+        case HELLO_VERIFY_SENT:
+            #ifdef WOLFSSL_DTLS
+                if (ssl->options.dtls) {
+                    ssl->options.clientState = NULL_STATE;  /* get again */
+                    /* reset messages received */
+                    XMEMSET(&ssl->msgsReceived, 0, sizeof(ssl->msgsReceived));
+                    /* re-init hashes, exclude first hello and verify request */
+#ifndef NO_OLD_TLS
+                    wc_InitMd5(&ssl->hsHashes->hashMd5);
+                    if ( (ssl->error = wc_InitSha(&ssl->hsHashes->hashSha))
+                                                                         != 0) {
+                        WOLFSSL_ERROR(ssl->error);
+                        return SSL_FATAL_ERROR;
+                    }
+#endif
+                    if (IsAtLeastTLSv1_2(ssl)) {
+                        #ifndef NO_SHA256
+                            if ( (ssl->error = wc_InitSha256(
+                                            &ssl->hsHashes->hashSha256)) != 0) {
+                               WOLFSSL_ERROR(ssl->error);
+                               return SSL_FATAL_ERROR;
+                            }
+                        #endif
+                        #ifdef WOLFSSL_SHA384
+                            if ( (ssl->error = wc_InitSha384(
+                                            &ssl->hsHashes->hashSha384)) != 0) {
+                               WOLFSSL_ERROR(ssl->error);
+                               return SSL_FATAL_ERROR;
+                            }
+                        #endif
+                        #ifdef WOLFSSL_SHA512
+                            if ( (ssl->error = wc_InitSha512(
+                                            &ssl->hsHashes->hashSha512)) != 0) {
+                               WOLFSSL_ERROR(ssl->error);
+                               return SSL_FATAL_ERROR;
+                            }
+                        #endif
+                    }
+
+                    while (ssl->options.clientState < CLIENT_HELLO_COMPLETE)
+                        if ( (ssl->error = ProcessReply(ssl)) < 0) {
+                            WOLFSSL_ERROR(ssl->error);
+                            return SSL_FATAL_ERROR;
+                        }
+                }
+            #endif
+            ssl->options.acceptState = ACCEPT_FIRST_REPLY_DONE;
+            WOLFSSL_MSG("accept state ACCEPT_FIRST_REPLY_DONE");
+
+        case ACCEPT_FIRST_REPLY_DONE :
+            if ( (ssl->error = SendServerHello(ssl)) != 0) {
+                WOLFSSL_ERROR(ssl->error);
+                return SSL_FATAL_ERROR;
+            }
+            ssl->options.acceptState = SERVER_HELLO_SENT;
+            WOLFSSL_MSG("accept state SERVER_HELLO_SENT");
+
+        case SERVER_HELLO_SENT :
+            #ifndef NO_CERTS
+                if (!ssl->options.resuming)
+                    if ( (ssl->error = SendCertificate(ssl)) != 0) {
+                        WOLFSSL_ERROR(ssl->error);
+                        return SSL_FATAL_ERROR;
+                    }
+            #endif
+            ssl->options.acceptState = CERT_SENT;
+            WOLFSSL_MSG("accept state CERT_SENT");
+
+        case CERT_SENT :
+            if (!ssl->options.resuming)
+                if ( (ssl->error = SendServerKeyExchange(ssl)) != 0) {
+                    WOLFSSL_ERROR(ssl->error);
+                    return SSL_FATAL_ERROR;
+                }
+            ssl->options.acceptState = KEY_EXCHANGE_SENT;
+            WOLFSSL_MSG("accept state KEY_EXCHANGE_SENT");
+
+        case KEY_EXCHANGE_SENT :
+            #ifndef NO_CERTS
+                if (!ssl->options.resuming)
+                    if (ssl->options.verifyPeer)
+                        if ( (ssl->error = SendCertificateRequest(ssl)) != 0) {
+                            WOLFSSL_ERROR(ssl->error);
+                            return SSL_FATAL_ERROR;
+                        }
+            #endif
+            ssl->options.acceptState = CERT_REQ_SENT;
+            WOLFSSL_MSG("accept state CERT_REQ_SENT");
+
+        case CERT_REQ_SENT :
+            if (!ssl->options.resuming)
+                if ( (ssl->error = SendServerHelloDone(ssl)) != 0) {
+                    WOLFSSL_ERROR(ssl->error);
+                    return SSL_FATAL_ERROR;
+                }
+            ssl->options.acceptState = SERVER_HELLO_DONE;
+            WOLFSSL_MSG("accept state SERVER_HELLO_DONE");
+
+        case SERVER_HELLO_DONE :
+            if (!ssl->options.resuming) {
+                while (ssl->options.clientState < CLIENT_FINISHED_COMPLETE)
+                    if ( (ssl->error = ProcessReply(ssl)) < 0) {
+                        WOLFSSL_ERROR(ssl->error);
+                        return SSL_FATAL_ERROR;
+                    }
+            }
+            ssl->options.acceptState = ACCEPT_SECOND_REPLY_DONE;
+            WOLFSSL_MSG("accept state  ACCEPT_SECOND_REPLY_DONE");
+
+        case ACCEPT_SECOND_REPLY_DONE :
+#ifdef HAVE_SESSION_TICKET
+            if (ssl->options.createTicket) {
+                if ( (ssl->error = SendTicket(ssl)) != 0) {
+                    WOLFSSL_ERROR(ssl->error);
+                    return SSL_FATAL_ERROR;
+                }
+            }
+#endif /* HAVE_SESSION_TICKET */
+            ssl->options.acceptState = TICKET_SENT;
+            WOLFSSL_MSG("accept state  TICKET_SENT");
+
+        case TICKET_SENT:
+            if ( (ssl->error = SendChangeCipher(ssl)) != 0) {
+                WOLFSSL_ERROR(ssl->error);
+                return SSL_FATAL_ERROR;
+            }
+            ssl->options.acceptState = CHANGE_CIPHER_SENT;
+            WOLFSSL_MSG("accept state  CHANGE_CIPHER_SENT");
+
+        case CHANGE_CIPHER_SENT :
+            if ( (ssl->error = SendFinished(ssl)) != 0) {
+                WOLFSSL_ERROR(ssl->error);
+                return SSL_FATAL_ERROR;
+            }
+
+            ssl->options.acceptState = ACCEPT_FINISHED_DONE;
+            WOLFSSL_MSG("accept state ACCEPT_FINISHED_DONE");
+
+        case ACCEPT_FINISHED_DONE :
+            if (ssl->options.resuming)
+                while (ssl->options.clientState < CLIENT_FINISHED_COMPLETE)
+                    if ( (ssl->error = ProcessReply(ssl)) < 0) {
+                        WOLFSSL_ERROR(ssl->error);
+                        return SSL_FATAL_ERROR;
+                    }
+
+            ssl->options.acceptState = ACCEPT_THIRD_REPLY_DONE;
+            WOLFSSL_MSG("accept state ACCEPT_THIRD_REPLY_DONE");
+
+        case ACCEPT_THIRD_REPLY_DONE :
+#ifndef NO_HANDSHAKE_DONE_CB
+            if (ssl->hsDoneCb) {
+                int cbret = ssl->hsDoneCb(ssl, ssl->hsDoneCtx);
+                if (cbret < 0) {
+                    ssl->error = cbret;
+                    WOLFSSL_MSG("HandShake Done Cb don't continue error");
+                    return SSL_FATAL_ERROR;
+                }
+            }
+#endif /* NO_HANDSHAKE_DONE_CB */
+            FreeHandshakeResources(ssl);
+            WOLFSSL_LEAVE("SSL_accept()", SSL_SUCCESS);
+            return SSL_SUCCESS;
+
+        default :
+            WOLFSSL_MSG("Unknown accept state ERROR");
+            return SSL_FATAL_ERROR;
+        }
+    }
+
+#endif /* NO_WOLFSSL_SERVER */
+
+
+#ifndef NO_HANDSHAKE_DONE_CB
+
+int wolfSSL_SetHsDoneCb(WOLFSSL* ssl, HandShakeDoneCb cb, void* user_ctx)
+{
+    WOLFSSL_ENTER("wolfSSL_SetHsDoneCb");
+
+    if (ssl == NULL)
+        return BAD_FUNC_ARG;
+
+    ssl->hsDoneCb  = cb;
+    ssl->hsDoneCtx = user_ctx;
+
+
+    return SSL_SUCCESS;
+}
+
+#endif /* NO_HANDSHAKE_DONE_CB */
+
+
+int wolfSSL_Cleanup(void)
+{
+    int ret = SSL_SUCCESS;
+    int release = 0;
+
+    WOLFSSL_ENTER("wolfSSL_Cleanup");
+
+    if (initRefCount == 0)
+        return ret;  /* possibly no init yet, but not failure either way */
+
+    if (LockMutex(&count_mutex) != 0) {
+        WOLFSSL_MSG("Bad Lock Mutex count");
+        return BAD_MUTEX_E;
+    }
+
+    release = initRefCount-- == 1;
+    if (initRefCount < 0)
+        initRefCount = 0;
+
+    UnLockMutex(&count_mutex);
+
+    if (!release)
+        return ret;
+
+#ifndef NO_SESSION_CACHE
+    if (FreeMutex(&session_mutex) != 0)
+        ret = BAD_MUTEX_E;
+#endif
+    if (FreeMutex(&count_mutex) != 0)
+        ret = BAD_MUTEX_E;
+
+#if defined(HAVE_ECC) && defined(FP_ECC)
+    wc_ecc_fp_free();
+#endif
+
+    return ret;
+}
+
+
+#ifndef NO_SESSION_CACHE
+
+
+/* some session IDs aren't random afterall, let's make them random */
+static INLINE word32 HashSession(const byte* sessionID, word32 len, int* error)
+{
+    byte digest[MAX_DIGEST_SIZE];
+
+#ifndef NO_MD5
+    *error =  wc_Md5Hash(sessionID, len, digest);
+#elif !defined(NO_SHA)
+    *error =  wc_ShaHash(sessionID, len, digest);
+#elif !defined(NO_SHA256)
+    *error =  wc_Sha256Hash(sessionID, len, digest);
+#else
+    #error "We need a digest to hash the session IDs"
+#endif
+
+    return *error == 0 ? MakeWordFromHash(digest) : 0; /* 0 on failure */
+}
+
+
+void wolfSSL_flush_sessions(WOLFSSL_CTX* ctx, long tm)
+{
+    /* static table now, no flusing needed */
+    (void)ctx;
+    (void)tm;
+}
+
+
+/* set ssl session timeout in seconds */
+int wolfSSL_set_timeout(WOLFSSL* ssl, unsigned int to)
+{
+    if (ssl == NULL)
+        return BAD_FUNC_ARG;
+
+    ssl->timeout = to;
+
+    return SSL_SUCCESS;
+}
+
+
+/* set ctx session timeout in seconds */
+int wolfSSL_CTX_set_timeout(WOLFSSL_CTX* ctx, unsigned int to)
+{
+    if (ctx == NULL)
+        return BAD_FUNC_ARG;
+
+    ctx->timeout = to;
+
+    return SSL_SUCCESS;
+}
+
+
+#ifndef NO_CLIENT_CACHE
+
+/* Get Session from Client cache based on id/len, return NULL on failure */
+WOLFSSL_SESSION* GetSessionClient(WOLFSSL* ssl, const byte* id, int len)
+{
+    WOLFSSL_SESSION* ret = NULL;
+    word32          row;
+    int             idx;
+    int             count;
+    int             error = 0;
+
+    WOLFSSL_ENTER("GetSessionClient");
+
+    if (ssl->options.side == WOLFSSL_SERVER_END)
+        return NULL;
+
+    len = min(SERVER_ID_LEN, (word32)len);
+    row = HashSession(id, len, &error) % SESSION_ROWS;
+    if (error != 0) {
+        WOLFSSL_MSG("Hash session failed");
+        return NULL;
+    }
+
+    if (LockMutex(&session_mutex) != 0) {
+        WOLFSSL_MSG("Lock session mutex failed");
+        return NULL;
+    }
+
+    /* start from most recently used */
+    count = min((word32)ClientCache[row].totalCount, SESSIONS_PER_ROW);
+    idx = ClientCache[row].nextIdx - 1;
+    if (idx < 0)
+        idx = SESSIONS_PER_ROW - 1; /* if back to front, the previous was end */
+
+    for (; count > 0; --count, idx = idx ? idx - 1 : SESSIONS_PER_ROW - 1) {
+        WOLFSSL_SESSION* current;
+        ClientSession   clSess;
+
+        if (idx >= SESSIONS_PER_ROW || idx < 0) { /* sanity check */
+            WOLFSSL_MSG("Bad idx");
+            break;
+        }
+
+        clSess = ClientCache[row].Clients[idx];
+
+        current = &SessionCache[clSess.serverRow].Sessions[clSess.serverIdx];
+        if (XMEMCMP(current->serverID, id, len) == 0) {
+            WOLFSSL_MSG("Found a serverid match for client");
+            if (LowResTimer() < (current->bornOn + current->timeout)) {
+                WOLFSSL_MSG("Session valid");
+                ret = current;
+                break;
+            } else {
+                WOLFSSL_MSG("Session timed out");  /* could have more for id */
+            }
+        } else {
+            WOLFSSL_MSG("ServerID not a match from client table");
+        }
+    }
+
+    UnLockMutex(&session_mutex);
+
+    return ret;
+}
+
+#endif /* NO_CLIENT_CACHE */
+
+
+WOLFSSL_SESSION* GetSession(WOLFSSL* ssl, byte* masterSecret)
+{
+    WOLFSSL_SESSION* ret = 0;
+    const byte*  id = NULL;
+    word32       row;
+    int          idx;
+    int          count;
+    int          error = 0;
+
+    if (ssl->options.sessionCacheOff)
+        return NULL;
+
+    if (ssl->options.haveSessionId == 0)
+        return NULL;
+
+#ifdef HAVE_SESSION_TICKET
+    if (ssl->options.side == WOLFSSL_SERVER_END && ssl->options.useTicket == 1)
+        return NULL;
+#endif
+
+    if (ssl->arrays)
+        id = ssl->arrays->sessionID;
+    else
+        id = ssl->session.sessionID;
+
+    row = HashSession(id, ID_LEN, &error) % SESSION_ROWS;
+    if (error != 0) {
+        WOLFSSL_MSG("Hash session failed");
+        return NULL;
+    }
+
+    if (LockMutex(&session_mutex) != 0)
+        return 0;
+
+    /* start from most recently used */
+    count = min((word32)SessionCache[row].totalCount, SESSIONS_PER_ROW);
+    idx = SessionCache[row].nextIdx - 1;
+    if (idx < 0)
+        idx = SESSIONS_PER_ROW - 1; /* if back to front, the previous was end */
+
+    for (; count > 0; --count, idx = idx ? idx - 1 : SESSIONS_PER_ROW - 1) {
+        WOLFSSL_SESSION* current;
+
+        if (idx >= SESSIONS_PER_ROW || idx < 0) { /* sanity check */
+            WOLFSSL_MSG("Bad idx");
+            break;
+        }
+
+        current = &SessionCache[row].Sessions[idx];
+        if (XMEMCMP(current->sessionID, id, ID_LEN) == 0) {
+            WOLFSSL_MSG("Found a session match");
+            if (LowResTimer() < (current->bornOn + current->timeout)) {
+                WOLFSSL_MSG("Session valid");
+                ret = current;
+                if (masterSecret)
+                    XMEMCPY(masterSecret, current->masterSecret, SECRET_LEN);
+            } else {
+                WOLFSSL_MSG("Session timed out");
+            }
+            break;  /* no more sessionIDs whether valid or not that match */
+        } else {
+            WOLFSSL_MSG("SessionID not a match at this idx");
+        }
+    }
+
+    UnLockMutex(&session_mutex);
+
+    return ret;
+}
+
+
+int SetSession(WOLFSSL* ssl, WOLFSSL_SESSION* session)
+{
+    if (ssl->options.sessionCacheOff)
+        return SSL_FAILURE;
+
+    if (LowResTimer() < (session->bornOn + session->timeout)) {
+        ssl->session  = *session;
+        ssl->options.resuming = 1;
+
+#ifdef SESSION_CERTS
+        ssl->version              = session->version;
+        ssl->options.cipherSuite0 = session->cipherSuite0;
+        ssl->options.cipherSuite  = session->cipherSuite;
+#endif
+
+        return SSL_SUCCESS;
+    }
+    return SSL_FAILURE;  /* session timed out */
+}
+
+
+#ifdef WOLFSSL_SESSION_STATS
+static int get_locked_session_stats(word32* active, word32* total,
+                                    word32* peak);
+#endif
+
+int AddSession(WOLFSSL* ssl)
+{
+    word32 row, idx;
+    int    error = 0;
+
+    if (ssl->options.sessionCacheOff)
+        return 0;
+
+    if (ssl->options.haveSessionId == 0)
+        return 0;
+
+#ifdef HAVE_SESSION_TICKET
+    if (ssl->options.side == WOLFSSL_SERVER_END && ssl->options.useTicket == 1)
+        return 0;
+#endif
+
+    row = HashSession(ssl->arrays->sessionID, ID_LEN, &error) % SESSION_ROWS;
+    if (error != 0) {
+        WOLFSSL_MSG("Hash session failed");
+        return error;
+    }
+
+    if (LockMutex(&session_mutex) != 0)
+        return BAD_MUTEX_E;
+
+    idx = SessionCache[row].nextIdx++;
+#ifdef SESSION_INDEX
+    ssl->sessionIndex = (row << SESSIDX_ROW_SHIFT) | idx;
+#endif
+
+    XMEMCPY(SessionCache[row].Sessions[idx].masterSecret,
+           ssl->arrays->masterSecret, SECRET_LEN);
+    XMEMCPY(SessionCache[row].Sessions[idx].sessionID, ssl->arrays->sessionID,
+           ID_LEN);
+    SessionCache[row].Sessions[idx].sessionIDSz = ssl->arrays->sessionIDSz;
+
+    SessionCache[row].Sessions[idx].timeout = ssl->timeout;
+    SessionCache[row].Sessions[idx].bornOn  = LowResTimer();
+
+#ifdef HAVE_SESSION_TICKET
+    SessionCache[row].Sessions[idx].ticketLen     = ssl->session.ticketLen;
+    XMEMCPY(SessionCache[row].Sessions[idx].ticket,
+                                   ssl->session.ticket, ssl->session.ticketLen);
+#endif
+
+#ifdef SESSION_CERTS
+    SessionCache[row].Sessions[idx].chain.count = ssl->session.chain.count;
+    XMEMCPY(SessionCache[row].Sessions[idx].chain.certs,
+           ssl->session.chain.certs, sizeof(x509_buffer) * MAX_CHAIN_DEPTH);
+
+    SessionCache[row].Sessions[idx].version      = ssl->version;
+    SessionCache[row].Sessions[idx].cipherSuite0 = ssl->options.cipherSuite0;
+    SessionCache[row].Sessions[idx].cipherSuite  = ssl->options.cipherSuite;
+#endif /* SESSION_CERTS */
+
+    SessionCache[row].totalCount++;
+    if (SessionCache[row].nextIdx == SESSIONS_PER_ROW)
+        SessionCache[row].nextIdx = 0;
+
+#ifndef NO_CLIENT_CACHE
+    if (ssl->options.side == WOLFSSL_CLIENT_END && ssl->session.idLen) {
+        word32 clientRow, clientIdx;
+
+        WOLFSSL_MSG("Adding client cache entry");
+
+        SessionCache[row].Sessions[idx].idLen = ssl->session.idLen;
+        XMEMCPY(SessionCache[row].Sessions[idx].serverID, ssl->session.serverID,
+                ssl->session.idLen);
+
+        clientRow = HashSession(ssl->session.serverID, ssl->session.idLen,
+                                &error) % SESSION_ROWS;
+        if (error != 0) {
+            WOLFSSL_MSG("Hash session failed");
+        } else {
+            clientIdx = ClientCache[clientRow].nextIdx++;
+
+            ClientCache[clientRow].Clients[clientIdx].serverRow = (word16)row;
+            ClientCache[clientRow].Clients[clientIdx].serverIdx = (word16)idx;
+
+            ClientCache[clientRow].totalCount++;
+            if (ClientCache[clientRow].nextIdx == SESSIONS_PER_ROW)
+                ClientCache[clientRow].nextIdx = 0;
+        }
+    }
+    else
+        SessionCache[row].Sessions[idx].idLen = 0;
+#endif /* NO_CLIENT_CACHE */
+
+#if defined(WOLFSSL_SESSION_STATS) && defined(WOLFSSL_PEAK_SESSIONS)
+    if (error == 0) {
+        word32 active = 0;
+
+        error = get_locked_session_stats(&active, NULL, NULL);
+        if (error == SSL_SUCCESS) {
+            error = 0;  /* back to this function ok */
+
+            if (active > PeakSessions)
+                PeakSessions = active;
+        }
+    }
+#endif /* defined(WOLFSSL_SESSION_STATS) && defined(WOLFSSL_PEAK_SESSIONS) */
+
+    if (UnLockMutex(&session_mutex) != 0)
+        return BAD_MUTEX_E;
+
+    return error;
+}
+
+
+#ifdef SESSION_INDEX
+
+int wolfSSL_GetSessionIndex(WOLFSSL* ssl)
+{
+    WOLFSSL_ENTER("wolfSSL_GetSessionIndex");
+    WOLFSSL_LEAVE("wolfSSL_GetSessionIndex", ssl->sessionIndex);
+    return ssl->sessionIndex;
+}
+
+
+int wolfSSL_GetSessionAtIndex(int idx, WOLFSSL_SESSION* session)
+{
+    int row, col, result = SSL_FAILURE;
+
+    WOLFSSL_ENTER("wolfSSL_GetSessionAtIndex");
+
+    row = idx >> SESSIDX_ROW_SHIFT;
+    col = idx & SESSIDX_IDX_MASK;
+
+    if (LockMutex(&session_mutex) != 0) {
+        return BAD_MUTEX_E;
+    }
+
+    if (row < SESSION_ROWS &&
+        col < (int)min(SessionCache[row].totalCount, SESSIONS_PER_ROW)) {
+        XMEMCPY(session,
+                 &SessionCache[row].Sessions[col], sizeof(WOLFSSL_SESSION));
+        result = SSL_SUCCESS;
+    }
+
+    if (UnLockMutex(&session_mutex) != 0)
+        result = BAD_MUTEX_E;
+
+    WOLFSSL_LEAVE("wolfSSL_GetSessionAtIndex", result);
+    return result;
+}
+
+#endif /* SESSION_INDEX */
+
+#if defined(SESSION_INDEX) && defined(SESSION_CERTS)
+
+WOLFSSL_X509_CHAIN* wolfSSL_SESSION_get_peer_chain(WOLFSSL_SESSION* session)
+{
+    WOLFSSL_X509_CHAIN* chain = NULL;
+
+    WOLFSSL_ENTER("wolfSSL_SESSION_get_peer_chain");
+    if (session)
+        chain = &session->chain;
+
+    WOLFSSL_LEAVE("wolfSSL_SESSION_get_peer_chain", chain ? 1 : 0);
+    return chain;
+}
+
+#endif /* SESSION_INDEX && SESSION_CERTS */
+
+
+#ifdef WOLFSSL_SESSION_STATS
+
+/* requires session_mutex lock held, SSL_SUCCESS on ok */
+static int get_locked_session_stats(word32* active, word32* total, word32* peak)
+{
+    int result = SSL_SUCCESS;
+    int i;
+    int count;
+    int idx;
+    word32 now   = 0;
+    word32 seen  = 0;
+    word32 ticks = LowResTimer();
+
+    (void)peak;
+
+    WOLFSSL_ENTER("get_locked_session_stats");
+
+    for (i = 0; i < SESSION_ROWS; i++) {
+        seen += SessionCache[i].totalCount;
+
+        if (active == NULL)
+            continue;  /* no need to calculate what we can't set */
+
+        count = min((word32)SessionCache[i].totalCount, SESSIONS_PER_ROW);
+        idx   = SessionCache[i].nextIdx - 1;
+        if (idx < 0)
+            idx = SESSIONS_PER_ROW - 1; /* if back to front previous was end */
+
+        for (; count > 0; --count, idx = idx ? idx - 1 : SESSIONS_PER_ROW - 1) {
+            if (idx >= SESSIONS_PER_ROW || idx < 0) {  /* sanity check */
+                WOLFSSL_MSG("Bad idx");
+                break;
+            }
+
+            /* if not expried then good */
+            if (ticks < (SessionCache[i].Sessions[idx].bornOn +
+                         SessionCache[i].Sessions[idx].timeout) ) {
+                now++;
+            }
+        }
+    }
+
+    if (active)
+        *active = now;
+
+    if (total)
+        *total = seen;
+
+#ifdef WOLFSSL_PEAK_SESSIONS
+    if (peak)
+        *peak = PeakSessions;
+#endif
+
+    WOLFSSL_LEAVE("get_locked_session_stats", result);
+
+    return result;
+}
+
+
+/* return SSL_SUCCESS on ok */
+int wolfSSL_get_session_stats(word32* active, word32* total, word32* peak,
+                              word32* maxSessions)
+{
+    int result = SSL_SUCCESS;
+
+    WOLFSSL_ENTER("wolfSSL_get_session_stats");
+
+    if (maxSessions) {
+        *maxSessions = SESSIONS_PER_ROW * SESSION_ROWS;
+
+        if (active == NULL && total == NULL && peak == NULL)
+            return result;  /* we're done */
+    }
+
+    /* user must provide at least one query value */
+    if (active == NULL && total == NULL && peak == NULL)
+        return BAD_FUNC_ARG;
+
+    if (LockMutex(&session_mutex) != 0) {
+        return BAD_MUTEX_E;
+    }
+
+    result = get_locked_session_stats(active, total, peak);
+
+    if (UnLockMutex(&session_mutex) != 0)
+        result = BAD_MUTEX_E;
+
+    WOLFSSL_LEAVE("wolfSSL_get_session_stats", result);
+
+    return result;
+}
+
+#endif /* WOLFSSL_SESSION_STATS */
+
+
+    #ifdef PRINT_SESSION_STATS
+
+    /* SSL_SUCCESS on ok */
+    int wolfSSL_PrintSessionStats(void)
+    {
+        word32 totalSessionsSeen = 0;
+        word32 totalSessionsNow = 0;
+        word32 peak = 0;
+        word32 maxSessions = 0;
+        int    i;
+        int    ret;
+        double E;               /* expected freq */
+        double chiSquare = 0;
+
+        ret = wolfSSL_get_session_stats(&totalSessionsNow, &totalSessionsSeen,
+                                        &peak, &maxSessions);
+        if (ret != SSL_SUCCESS)
+            return ret;
+        printf("Total Sessions Seen = %d\n", totalSessionsSeen);
+        printf("Total Sessions Now  = %d\n", totalSessionsNow);
+#ifdef WOLFSSL_PEAK_SESSIONS
+        printf("Peak  Sessions      = %d\n", peak);
+#endif
+        printf("Max   Sessions      = %d\n", maxSessions);
+
+        E = (double)totalSessionsSeen / SESSION_ROWS;
+
+        for (i = 0; i < SESSION_ROWS; i++) {
+            double diff = SessionCache[i].totalCount - E;
+            diff *= diff;                /* square    */
+            diff /= E;                   /* normalize */
+
+            chiSquare += diff;
+        }
+        printf("  chi-square = %5.1f, d.f. = %d\n", chiSquare,
+                                                     SESSION_ROWS - 1);
+        #if (SESSION_ROWS == 11)
+            printf(" .05 p value =  18.3, chi-square should be less\n");
+        #elif (SESSION_ROWS == 211)
+            printf(".05 p value  = 244.8, chi-square should be less\n");
+        #elif (SESSION_ROWS == 5981)
+            printf(".05 p value  = 6161.0, chi-square should be less\n");
+        #elif (SESSION_ROWS == 3)
+            printf(".05 p value  =   6.0, chi-square should be less\n");
+        #elif (SESSION_ROWS == 2861)
+            printf(".05 p value  = 2985.5, chi-square should be less\n");
+        #endif
+        printf("\n");
+
+        return ret;
+    }
+
+    #endif /* SESSION_STATS */
+
+#else  /* NO_SESSION_CACHE */
+
+/* No session cache version */
+WOLFSSL_SESSION* GetSession(WOLFSSL* ssl, byte* masterSecret)
+{
+    (void)ssl;
+    (void)masterSecret;
+
+    return NULL;
+}
+
+#endif /* NO_SESSION_CACHE */
+
+
+/* call before SSL_connect, if verifying will add name check to
+   date check and signature check */
+int wolfSSL_check_domain_name(WOLFSSL* ssl, const char* dn)
+{
+    WOLFSSL_ENTER("wolfSSL_check_domain_name");
+    if (ssl->buffers.domainName.buffer)
+        XFREE(ssl->buffers.domainName.buffer, ssl->heap, DYNAMIC_TYPE_DOMAIN);
+
+    ssl->buffers.domainName.length = (word32)XSTRLEN(dn) + 1;
+    ssl->buffers.domainName.buffer = (byte*) XMALLOC(
+                ssl->buffers.domainName.length, ssl->heap, DYNAMIC_TYPE_DOMAIN);
+
+    if (ssl->buffers.domainName.buffer) {
+        XSTRNCPY((char*)ssl->buffers.domainName.buffer, dn,
+                ssl->buffers.domainName.length);
+        return SSL_SUCCESS;
+    }
+    else {
+        ssl->error = MEMORY_ERROR;
+        return SSL_FAILURE;
+    }
+}
+
+
+/* turn on wolfSSL zlib compression
+   returns SSL_SUCCESS for success, else error (not built in)
+*/
+int wolfSSL_set_compression(WOLFSSL* ssl)
+{
+    WOLFSSL_ENTER("wolfSSL_set_compression");
+    (void)ssl;
+#ifdef HAVE_LIBZ
+    ssl->options.usingCompression = 1;
+    return SSL_SUCCESS;
+#else
+    return NOT_COMPILED_IN;
+#endif
+}
+
+
+#ifndef USE_WINDOWS_API
+    #ifndef NO_WRITEV
+
+        /* simulate writev semantics, doesn't actually do block at a time though
+           because of SSL_write behavior and because front adds may be small */
+        int wolfSSL_writev(WOLFSSL* ssl, const struct iovec* iov, int iovcnt)
+        {
+        #ifdef WOLFSSL_SMALL_STACK
+            byte   staticBuffer[1]; /* force heap usage */
+        #else
+            byte   staticBuffer[FILE_BUFFER_SIZE];
+        #endif
+            byte* myBuffer  = staticBuffer;
+            int   dynamic   = 0;
+            int   sending   = 0;
+            int   idx       = 0;
+            int   i;
+            int   ret;
+
+            WOLFSSL_ENTER("wolfSSL_writev");
+
+            for (i = 0; i < iovcnt; i++)
+                sending += (int)iov[i].iov_len;
+
+            if (sending > (int)sizeof(staticBuffer)) {
+                myBuffer = (byte*)XMALLOC(sending, ssl->heap,
+                                                           DYNAMIC_TYPE_WRITEV);
+                if (!myBuffer)
+                    return MEMORY_ERROR;
+
+                dynamic = 1;
+            }
+
+            for (i = 0; i < iovcnt; i++) {
+                XMEMCPY(&myBuffer[idx], iov[i].iov_base, iov[i].iov_len);
+                idx += (int)iov[i].iov_len;
+            }
+
+            ret = wolfSSL_write(ssl, myBuffer, sending);
+
+            if (dynamic)
+                XFREE(myBuffer, ssl->heap, DYNAMIC_TYPE_WRITEV);
+
+            return ret;
+        }
+    #endif
+#endif
+
+
+#ifdef WOLFSSL_CALLBACKS
+
+    typedef struct itimerval Itimerval;
+
+    /* don't keep calling simple functions while setting up timer and singals
+       if no inlining these are the next best */
+
+    #define AddTimes(a, b, c)                       \
+        do {                                        \
+            c.tv_sec  = a.tv_sec  + b.tv_sec;       \
+            c.tv_usec = a.tv_usec + b.tv_usec;      \
+            if (c.tv_usec >=  1000000) {            \
+                c.tv_sec++;                         \
+                c.tv_usec -= 1000000;               \
+            }                                       \
+        } while (0)
+
+
+    #define SubtractTimes(a, b, c)                  \
+        do {                                        \
+            c.tv_sec  = a.tv_sec  - b.tv_sec;       \
+            c.tv_usec = a.tv_usec - b.tv_usec;      \
+            if (c.tv_usec < 0) {                    \
+                c.tv_sec--;                         \
+                c.tv_usec += 1000000;               \
+            }                                       \
+        } while (0)
+
+    #define CmpTimes(a, b, cmp)                     \
+        ((a.tv_sec  ==  b.tv_sec) ?                 \
+            (a.tv_usec cmp b.tv_usec) :             \
+            (a.tv_sec  cmp b.tv_sec))               \
+
+
+    /* do nothing handler */
+    static void myHandler(int signo)
+    {
+        (void)signo;
+        return;
+    }
+
+
+    static int wolfSSL_ex_wrapper(WOLFSSL* ssl, HandShakeCallBack hsCb,
+                                 TimeoutCallBack toCb, Timeval timeout)
+    {
+        int       ret        = SSL_FATAL_ERROR;
+        int       oldTimerOn = 0;   /* was timer already on */
+        Timeval   startTime;
+        Timeval   endTime;
+        Timeval   totalTime;
+        Itimerval myTimeout;
+        Itimerval oldTimeout; /* if old timer adjust from total time to reset */
+        struct sigaction act, oact;
+
+        #define ERR_OUT(x) { ssl->hsInfoOn = 0; ssl->toInfoOn = 0; return x; }
+
+        if (hsCb) {
+            ssl->hsInfoOn = 1;
+            InitHandShakeInfo(&ssl->handShakeInfo);
+        }
+        if (toCb) {
+            ssl->toInfoOn = 1;
+            InitTimeoutInfo(&ssl->timeoutInfo);
+
+            if (gettimeofday(&startTime, 0) < 0)
+                ERR_OUT(GETTIME_ERROR);
+
+            /* use setitimer to simulate getitimer, init 0 myTimeout */
+            myTimeout.it_interval.tv_sec  = 0;
+            myTimeout.it_interval.tv_usec = 0;
+            myTimeout.it_value.tv_sec     = 0;
+            myTimeout.it_value.tv_usec    = 0;
+            if (setitimer(ITIMER_REAL, &myTimeout, &oldTimeout) < 0)
+                ERR_OUT(SETITIMER_ERROR);
+
+            if (oldTimeout.it_value.tv_sec || oldTimeout.it_value.tv_usec) {
+                oldTimerOn = 1;
+
+                /* is old timer going to expire before ours */
+                if (CmpTimes(oldTimeout.it_value, timeout, <)) {
+                    timeout.tv_sec  = oldTimeout.it_value.tv_sec;
+                    timeout.tv_usec = oldTimeout.it_value.tv_usec;
+                }
+            }
+            myTimeout.it_value.tv_sec  = timeout.tv_sec;
+            myTimeout.it_value.tv_usec = timeout.tv_usec;
+
+            /* set up signal handler, don't restart socket send/recv */
+            act.sa_handler = myHandler;
+            sigemptyset(&act.sa_mask);
+            act.sa_flags = 0;
+#ifdef SA_INTERRUPT
+            act.sa_flags |= SA_INTERRUPT;
+#endif
+            if (sigaction(SIGALRM, &act, &oact) < 0)
+                ERR_OUT(SIGACT_ERROR);
+
+            if (setitimer(ITIMER_REAL, &myTimeout, 0) < 0)
+                ERR_OUT(SETITIMER_ERROR);
+        }
+
+        /* do main work */
+#ifndef NO_WOLFSSL_CLIENT
+        if (ssl->options.side == WOLFSSL_CLIENT_END)
+            ret = wolfSSL_connect(ssl);
+#endif
+#ifndef NO_WOLFSSL_SERVER
+        if (ssl->options.side == WOLFSSL_SERVER_END)
+            ret = wolfSSL_accept(ssl);
+#endif
+
+        /* do callbacks */
+        if (toCb) {
+            if (oldTimerOn) {
+                gettimeofday(&endTime, 0);
+                SubtractTimes(endTime, startTime, totalTime);
+                /* adjust old timer for elapsed time */
+                if (CmpTimes(totalTime, oldTimeout.it_value, <))
+                    SubtractTimes(oldTimeout.it_value, totalTime,
+                                  oldTimeout.it_value);
+                else {
+                    /* reset value to interval, may be off */
+                    oldTimeout.it_value.tv_sec = oldTimeout.it_interval.tv_sec;
+                    oldTimeout.it_value.tv_usec =oldTimeout.it_interval.tv_usec;
+                }
+                /* keep iter the same whether there or not */
+            }
+            /* restore old handler */
+            if (sigaction(SIGALRM, &oact, 0) < 0)
+                ret = SIGACT_ERROR;    /* more pressing error, stomp */
+            else
+                /* use old settings which may turn off (expired or not there) */
+                if (setitimer(ITIMER_REAL, &oldTimeout, 0) < 0)
+                    ret = SETITIMER_ERROR;
+
+            /* if we had a timeout call callback */
+            if (ssl->timeoutInfo.timeoutName[0]) {
+                ssl->timeoutInfo.timeoutValue.tv_sec  = timeout.tv_sec;
+                ssl->timeoutInfo.timeoutValue.tv_usec = timeout.tv_usec;
+                (toCb)(&ssl->timeoutInfo);
+            }
+            /* clean up */
+            FreeTimeoutInfo(&ssl->timeoutInfo, ssl->heap);
+            ssl->toInfoOn = 0;
+        }
+        if (hsCb) {
+            FinishHandShakeInfo(&ssl->handShakeInfo, ssl);
+            (hsCb)(&ssl->handShakeInfo);
+            ssl->hsInfoOn = 0;
+        }
+        return ret;
+    }
+
+
+#ifndef NO_WOLFSSL_CLIENT
+
+    int wolfSSL_connect_ex(WOLFSSL* ssl, HandShakeCallBack hsCb,
+                          TimeoutCallBack toCb, Timeval timeout)
+    {
+        WOLFSSL_ENTER("wolfSSL_connect_ex");
+        return wolfSSL_ex_wrapper(ssl, hsCb, toCb, timeout);
+    }
+
+#endif
+
+
+#ifndef NO_WOLFSSL_SERVER
+
+    int wolfSSL_accept_ex(WOLFSSL* ssl, HandShakeCallBack hsCb,
+                         TimeoutCallBack toCb,Timeval timeout)
+    {
+        WOLFSSL_ENTER("wolfSSL_accept_ex");
+        return wolfSSL_ex_wrapper(ssl, hsCb, toCb, timeout);
+    }
+
+#endif
+
+#endif /* WOLFSSL_CALLBACKS */
+
+
+#ifndef NO_PSK
+
+    void wolfSSL_CTX_set_psk_client_callback(WOLFSSL_CTX* ctx,
+                                         psk_client_callback cb)
+    {
+        WOLFSSL_ENTER("SSL_CTX_set_psk_client_callback");
+        ctx->havePSK = 1;
+        ctx->client_psk_cb = cb;
+    }
+
+
+    void wolfSSL_set_psk_client_callback(WOLFSSL* ssl, psk_client_callback cb)
+    {
+        byte haveRSA = 1;
+
+        WOLFSSL_ENTER("SSL_set_psk_client_callback");
+        ssl->options.havePSK = 1;
+        ssl->options.client_psk_cb = cb;
+
+        #ifdef NO_RSA
+            haveRSA = 0;
+        #endif
+        InitSuites(ssl->suites, ssl->version, haveRSA, TRUE,
+                   ssl->options.haveDH, ssl->options.haveNTRU,
+                   ssl->options.haveECDSAsig, ssl->options.haveStaticECC,
+                   ssl->options.side);
+    }
+
+
+    void wolfSSL_CTX_set_psk_server_callback(WOLFSSL_CTX* ctx,
+                                         psk_server_callback cb)
+    {
+        WOLFSSL_ENTER("SSL_CTX_set_psk_server_callback");
+        ctx->havePSK = 1;
+        ctx->server_psk_cb = cb;
+    }
+
+
+    void wolfSSL_set_psk_server_callback(WOLFSSL* ssl, psk_server_callback cb)
+    {
+        byte haveRSA = 1;
+
+        WOLFSSL_ENTER("SSL_set_psk_server_callback");
+        ssl->options.havePSK = 1;
+        ssl->options.server_psk_cb = cb;
+
+        #ifdef NO_RSA
+            haveRSA = 0;
+        #endif
+        InitSuites(ssl->suites, ssl->version, haveRSA, TRUE,
+                   ssl->options.haveDH, ssl->options.haveNTRU,
+                   ssl->options.haveECDSAsig, ssl->options.haveStaticECC,
+                   ssl->options.side);
+    }
+
+
+    const char* wolfSSL_get_psk_identity_hint(const WOLFSSL* ssl)
+    {
+        WOLFSSL_ENTER("SSL_get_psk_identity_hint");
+
+        if (ssl == NULL || ssl->arrays == NULL)
+            return NULL;
+
+        return ssl->arrays->server_hint;
+    }
+
+
+    const char* wolfSSL_get_psk_identity(const WOLFSSL* ssl)
+    {
+        WOLFSSL_ENTER("SSL_get_psk_identity");
+
+        if (ssl == NULL || ssl->arrays == NULL)
+            return NULL;
+
+        return ssl->arrays->client_identity;
+    }
+
+
+    int wolfSSL_CTX_use_psk_identity_hint(WOLFSSL_CTX* ctx, const char* hint)
+    {
+        WOLFSSL_ENTER("SSL_CTX_use_psk_identity_hint");
+        if (hint == 0)
+            ctx->server_hint[0] = 0;
+        else {
+            XSTRNCPY(ctx->server_hint, hint, MAX_PSK_ID_LEN);
+            ctx->server_hint[MAX_PSK_ID_LEN - 1] = '\0';
+        }
+        return SSL_SUCCESS;
+    }
+
+
+    int wolfSSL_use_psk_identity_hint(WOLFSSL* ssl, const char* hint)
+    {
+        WOLFSSL_ENTER("SSL_use_psk_identity_hint");
+
+        if (ssl == NULL || ssl->arrays == NULL)
+            return SSL_FAILURE;
+
+        if (hint == 0)
+            ssl->arrays->server_hint[0] = 0;
+        else {
+            XSTRNCPY(ssl->arrays->server_hint, hint, MAX_PSK_ID_LEN);
+            ssl->arrays->server_hint[MAX_PSK_ID_LEN - 1] = '\0';
+        }
+        return SSL_SUCCESS;
+    }
+
+#endif /* NO_PSK */
+
+
+#ifdef HAVE_ANON
+
+    int wolfSSL_CTX_allow_anon_cipher(WOLFSSL_CTX* ctx)
+    {
+        WOLFSSL_ENTER("wolfSSL_CTX_allow_anon_cipher");
+
+        if (ctx == NULL)
+            return SSL_FAILURE;
+
+        ctx->haveAnon = 1;
+
+        return SSL_SUCCESS;
+    }
+
+#endif /* HAVE_ANON */
+
+
+#ifndef NO_CERTS
+/* used to be defined on NO_FILESYSTEM only, but are generally useful */
+
+    /* wolfSSL extension allows DER files to be loaded from buffers as well */
+    int wolfSSL_CTX_load_verify_buffer(WOLFSSL_CTX* ctx, const unsigned char* in,
+                                      long sz, int format)
+    {
+        WOLFSSL_ENTER("wolfSSL_CTX_load_verify_buffer");
+        if (format == SSL_FILETYPE_PEM)
+            return ProcessChainBuffer(ctx, in, sz, format, CA_TYPE, NULL);
+        else
+            return ProcessBuffer(ctx, in, sz, format, CA_TYPE, NULL,NULL,0);
+    }
+
+
+    int wolfSSL_CTX_use_certificate_buffer(WOLFSSL_CTX* ctx,
+                                 const unsigned char* in, long sz, int format)
+    {
+        WOLFSSL_ENTER("wolfSSL_CTX_use_certificate_buffer");
+        return ProcessBuffer(ctx, in, sz, format, CERT_TYPE, NULL, NULL, 0);
+    }
+
+
+    int wolfSSL_CTX_use_PrivateKey_buffer(WOLFSSL_CTX* ctx,
+                                 const unsigned char* in, long sz, int format)
+    {
+        WOLFSSL_ENTER("wolfSSL_CTX_use_PrivateKey_buffer");
+        return ProcessBuffer(ctx, in, sz, format, PRIVATEKEY_TYPE, NULL,NULL,0);
+    }
+
+
+    int wolfSSL_CTX_use_certificate_chain_buffer(WOLFSSL_CTX* ctx,
+                                 const unsigned char* in, long sz)
+    {
+        WOLFSSL_ENTER("wolfSSL_CTX_use_certificate_chain_buffer");
+        return ProcessBuffer(ctx, in, sz, SSL_FILETYPE_PEM, CERT_TYPE, NULL,
+                             NULL, 1);
+    }
+
+    int wolfSSL_use_certificate_buffer(WOLFSSL* ssl,
+                                 const unsigned char* in, long sz, int format)
+    {
+        WOLFSSL_ENTER("wolfSSL_use_certificate_buffer");
+        return ProcessBuffer(ssl->ctx, in, sz, format,CERT_TYPE,ssl,NULL,0);
+    }
+
+
+    int wolfSSL_use_PrivateKey_buffer(WOLFSSL* ssl,
+                                 const unsigned char* in, long sz, int format)
+    {
+        WOLFSSL_ENTER("wolfSSL_use_PrivateKey_buffer");
+        return ProcessBuffer(ssl->ctx, in, sz, format, PRIVATEKEY_TYPE,
+                             ssl, NULL, 0);
+    }
+
+
+    int wolfSSL_use_certificate_chain_buffer(WOLFSSL* ssl,
+                                 const unsigned char* in, long sz)
+    {
+        WOLFSSL_ENTER("wolfSSL_use_certificate_chain_buffer");
+        return ProcessBuffer(ssl->ctx, in, sz, SSL_FILETYPE_PEM, CERT_TYPE,
+                             ssl, NULL, 1);
+    }
+
+
+    /* unload any certs or keys that SSL owns, leave CTX as is
+       SSL_SUCCESS on ok */
+    int wolfSSL_UnloadCertsKeys(WOLFSSL* ssl)
+    {
+        if (ssl == NULL) {
+            WOLFSSL_MSG("Null function arg");
+            return BAD_FUNC_ARG;
+        }
+
+        if (ssl->buffers.weOwnCert) {
+            WOLFSSL_MSG("Unloading cert");
+            XFREE(ssl->buffers.certificate.buffer, ssl->heap,DYNAMIC_TYPE_CERT);
+            ssl->buffers.weOwnCert = 0;
+            ssl->buffers.certificate.length = 0;
+            ssl->buffers.certificate.buffer = NULL;
+        }
+
+        if (ssl->buffers.weOwnCertChain) {
+            WOLFSSL_MSG("Unloading cert chain");
+            XFREE(ssl->buffers.certChain.buffer, ssl->heap,DYNAMIC_TYPE_CERT);
+            ssl->buffers.weOwnCertChain = 0;
+            ssl->buffers.certChain.length = 0;
+            ssl->buffers.certChain.buffer = NULL;
+        }
+
+        if (ssl->buffers.weOwnKey) {
+            WOLFSSL_MSG("Unloading key");
+            XFREE(ssl->buffers.key.buffer, ssl->heap, DYNAMIC_TYPE_KEY);
+            ssl->buffers.weOwnKey = 0;
+            ssl->buffers.key.length = 0;
+            ssl->buffers.key.buffer = NULL;
+        }
+
+        return SSL_SUCCESS;
+    }
+
+
+    int wolfSSL_CTX_UnloadCAs(WOLFSSL_CTX* ctx)
+    {
+        WOLFSSL_ENTER("wolfSSL_CTX_UnloadCAs");
+
+        if (ctx == NULL)
+            return BAD_FUNC_ARG;
+
+        return wolfSSL_CertManagerUnloadCAs(ctx->cm);
+    }
+
+/* old NO_FILESYSTEM end */
+#endif /* !NO_CERTS */
+
+
+#if defined(OPENSSL_EXTRA) || defined(GOAHEAD_WS)
+
+
+    int wolfSSL_add_all_algorithms(void)
+    {
+        WOLFSSL_ENTER("wolfSSL_add_all_algorithms");
+        wolfSSL_Init();
+        return SSL_SUCCESS;
+    }
+
+
+    long wolfSSL_CTX_sess_set_cache_size(WOLFSSL_CTX* ctx, long sz)
+    {
+        /* cache size fixed at compile time in wolfSSL */
+        (void)ctx;
+        (void)sz;
+        return 0;
+    }
+
+
+    void wolfSSL_CTX_set_quiet_shutdown(WOLFSSL_CTX* ctx, int mode)
+    {
+        WOLFSSL_ENTER("wolfSSL_CTX_set_quiet_shutdown");
+        if (mode)
+            ctx->quietShutdown = 1;
+    }
+
+
+    void wolfSSL_set_quiet_shutdown(WOLFSSL* ssl, int mode)
+    {
+        WOLFSSL_ENTER("wolfSSL_CTX_set_quiet_shutdown");
+        if (mode)
+            ssl->options.quietShutdown = 1;
+    }
+
+
+    void wolfSSL_set_bio(WOLFSSL* ssl, WOLFSSL_BIO* rd, WOLFSSL_BIO* wr)
+    {
+        WOLFSSL_ENTER("SSL_set_bio");
+        wolfSSL_set_rfd(ssl, rd->fd);
+        wolfSSL_set_wfd(ssl, wr->fd);
+
+        ssl->biord = rd;
+        ssl->biowr = wr;
+    }
+
+
+    void wolfSSL_CTX_set_client_CA_list(WOLFSSL_CTX* ctx,
+                                       STACK_OF(WOLFSSL_X509_NAME)* names)
+    {
+        (void)ctx;
+        (void)names;
+    }
+
+
+    STACK_OF(WOLFSSL_X509_NAME)* wolfSSL_load_client_CA_file(const char* fname)
+    {
+        (void)fname;
+        return 0;
+    }
+
+
+    int wolfSSL_CTX_set_default_verify_paths(WOLFSSL_CTX* ctx)
+    {
+        /* TODO:, not needed in goahead */
+        (void)ctx;
+        return SSL_NOT_IMPLEMENTED;
+    }
+
+
+    /* keyblock size in bytes or -1 */
+    int wolfSSL_get_keyblock_size(WOLFSSL* ssl)
+    {
+        if (ssl == NULL)
+            return SSL_FATAL_ERROR;
+
+        return 2 * (ssl->specs.key_size + ssl->specs.iv_size +
+                    ssl->specs.hash_size);
+    }
+
+
+    /* store keys returns SSL_SUCCESS or -1 on error */
+    int wolfSSL_get_keys(WOLFSSL* ssl, unsigned char** ms, unsigned int* msLen,
+                                     unsigned char** sr, unsigned int* srLen,
+                                     unsigned char** cr, unsigned int* crLen)
+    {
+        if (ssl == NULL || ssl->arrays == NULL)
+            return SSL_FATAL_ERROR;
+
+        *ms = ssl->arrays->masterSecret;
+        *sr = ssl->arrays->serverRandom;
+        *cr = ssl->arrays->clientRandom;
+
+        *msLen = SECRET_LEN;
+        *srLen = RAN_LEN;
+        *crLen = RAN_LEN;
+
+        return SSL_SUCCESS;
+    }
+
+
+    void wolfSSL_set_accept_state(WOLFSSL* ssl)
+    {
+        byte haveRSA = 1;
+        byte havePSK = 0;
+
+        WOLFSSL_ENTER("SSL_set_accept_state");
+        ssl->options.side = WOLFSSL_SERVER_END;
+        /* reset suites in case user switched */
+
+        #ifdef NO_RSA
+            haveRSA = 0;
+        #endif
+        #ifndef NO_PSK
+            havePSK = ssl->options.havePSK;
+        #endif
+        InitSuites(ssl->suites, ssl->version, haveRSA, havePSK,
+                   ssl->options.haveDH, ssl->options.haveNTRU,
+                   ssl->options.haveECDSAsig, ssl->options.haveStaticECC,
+                   ssl->options.side);
+    }
+#endif
+
+    /* return true if connection established */
+    int wolfSSL_is_init_finished(WOLFSSL* ssl)
+    {
+        if (ssl == NULL)
+            return 0;
+
+        if (ssl->options.handShakeState == HANDSHAKE_DONE)
+            return 1;
+
+        return 0;
+    }
+
+#if defined(OPENSSL_EXTRA) || defined(GOAHEAD_WS)
+    void wolfSSL_CTX_set_tmp_rsa_callback(WOLFSSL_CTX* ctx,
+                                      WOLFSSL_RSA*(*f)(WOLFSSL*, int, int))
+    {
+        /* wolfSSL verifies all these internally */
+        (void)ctx;
+        (void)f;
+    }
+
+
+    void wolfSSL_set_shutdown(WOLFSSL* ssl, int opt)
+    {
+        (void)ssl;
+        (void)opt;
+    }
+
+
+    long wolfSSL_CTX_set_options(WOLFSSL_CTX* ctx, long opt)
+    {
+        /* goahead calls with 0, do nothing */
+        WOLFSSL_ENTER("SSL_CTX_set_options");
+        (void)ctx;
+        return opt;
+    }
+
+
+    int wolfSSL_set_rfd(WOLFSSL* ssl, int rfd)
+    {
+        WOLFSSL_ENTER("SSL_set_rfd");
+        ssl->rfd = rfd;      /* not used directly to allow IO callbacks */
+
+        ssl->IOCB_ReadCtx  = &ssl->rfd;
+
+        return SSL_SUCCESS;
+    }
+
+
+    int wolfSSL_set_wfd(WOLFSSL* ssl, int wfd)
+    {
+        WOLFSSL_ENTER("SSL_set_wfd");
+        ssl->wfd = wfd;      /* not used directly to allow IO callbacks */
+
+        ssl->IOCB_WriteCtx  = &ssl->wfd;
+
+        return SSL_SUCCESS;
+    }
+
+
+    WOLFSSL_RSA* wolfSSL_RSA_generate_key(int len, unsigned long bits,
+                                          void(*f)(int, int, void*), void* data)
+    {
+        /* no tmp key needed, actual generation not supported */
+        WOLFSSL_ENTER("RSA_generate_key");
+        (void)len;
+        (void)bits;
+        (void)f;
+        (void)data;
+        return NULL;
+    }
+
+
+
+    WOLFSSL_X509* wolfSSL_X509_STORE_CTX_get_current_cert(
+                                                     WOLFSSL_X509_STORE_CTX* ctx)
+    {
+        (void)ctx;
+        return 0;
+    }
+
+
+    int wolfSSL_X509_STORE_CTX_get_error(WOLFSSL_X509_STORE_CTX* ctx)
+    {
+        if (ctx != NULL)
+            return ctx->error;
+        return 0;
+    }
+
+
+    int wolfSSL_X509_STORE_CTX_get_error_depth(WOLFSSL_X509_STORE_CTX* ctx)
+    {
+        (void)ctx;
+        return 0;
+    }
+
+
+    WOLFSSL_BIO_METHOD* wolfSSL_BIO_f_buffer(void)
+    {
+        static WOLFSSL_BIO_METHOD meth;
+
+        WOLFSSL_ENTER("BIO_f_buffer");
+        meth.type = BIO_BUFFER;
+
+        return &meth;
+    }
+
+
+    long wolfSSL_BIO_set_write_buffer_size(WOLFSSL_BIO* bio, long size)
+    {
+        /* wolfSSL has internal buffer, compatibility only */
+        WOLFSSL_ENTER("BIO_set_write_buffer_size");
+        (void)bio;
+        return size;
+    }
+
+
+    WOLFSSL_BIO_METHOD* wolfSSL_BIO_f_ssl(void)
+    {
+        static WOLFSSL_BIO_METHOD meth;
+
+        WOLFSSL_ENTER("BIO_f_ssl");
+        meth.type = BIO_SSL;
+
+        return &meth;
+    }
+
+
+    WOLFSSL_BIO* wolfSSL_BIO_new_socket(int sfd, int closeF)
+    {
+        WOLFSSL_BIO* bio = (WOLFSSL_BIO*) XMALLOC(sizeof(WOLFSSL_BIO), 0,
+                                                DYNAMIC_TYPE_OPENSSL);
+
+        WOLFSSL_ENTER("BIO_new_socket");
+        if (bio) {
+            bio->type  = BIO_SOCKET;
+            bio->close = (byte)closeF;
+            bio->eof   = 0;
+            bio->ssl   = 0;
+            bio->fd    = sfd;
+            bio->prev  = 0;
+            bio->next  = 0;
+            bio->mem   = NULL;
+            bio->memLen = 0;
+        }
+        return bio;
+    }
+
+
+    int wolfSSL_BIO_eof(WOLFSSL_BIO* b)
+    {
+        WOLFSSL_ENTER("BIO_eof");
+        if (b->eof)
+            return 1;
+
+        return 0;
+    }
+
+
+    long wolfSSL_BIO_set_ssl(WOLFSSL_BIO* b, WOLFSSL* ssl, int closeF)
+    {
+        WOLFSSL_ENTER("BIO_set_ssl");
+        b->ssl   = ssl;
+        b->close = (byte)closeF;
+    /* add to ssl for bio free if SSL_free called before/instead of free_all? */
+
+        return 0;
+    }
+
+
+    WOLFSSL_BIO* wolfSSL_BIO_new(WOLFSSL_BIO_METHOD* method)
+    {
+        WOLFSSL_BIO* bio = (WOLFSSL_BIO*) XMALLOC(sizeof(WOLFSSL_BIO), 0,
+                                                DYNAMIC_TYPE_OPENSSL);
+        WOLFSSL_ENTER("BIO_new");
+        if (bio) {
+            bio->type   = method->type;
+            bio->close  = 0;
+            bio->eof    = 0;
+            bio->ssl    = NULL;
+            bio->mem    = NULL;
+            bio->memLen = 0;
+            bio->fd     = 0;
+            bio->prev   = NULL;
+            bio->next   = NULL;
+        }
+        return bio;
+    }
+
+
+    int wolfSSL_BIO_get_mem_data(WOLFSSL_BIO* bio, const byte** p)
+    {
+        if (bio == NULL || p == NULL)
+            return SSL_FATAL_ERROR;
+
+        *p = bio->mem;
+
+        return bio->memLen;
+    }
+
+
+    WOLFSSL_BIO* wolfSSL_BIO_new_mem_buf(void* buf, int len)
+    {
+        WOLFSSL_BIO* bio = NULL;
+        if (buf == NULL)
+            return bio;
+
+        bio = wolfSSL_BIO_new(wolfSSL_BIO_s_mem());
+        if (bio == NULL)
+            return bio;
+
+        bio->memLen = len;
+        bio->mem    = (byte*)XMALLOC(len, 0, DYNAMIC_TYPE_OPENSSL);
+        if (bio->mem == NULL) {
+            XFREE(bio, 0, DYNAMIC_TYPE_OPENSSL);
+            return NULL;
+        }
+
+        XMEMCPY(bio->mem, buf, len);
+
+        return bio;
+    }
+
+
+#ifdef USE_WINDOWS_API
+    #define CloseSocket(s) closesocket(s)
+#elif defined(WOLFSSL_MDK_ARM)
+    #define CloseSocket(s) closesocket(s)
+    extern int closesocket(int) ;
+#else
+    #define CloseSocket(s) close(s)
+#endif
+
+    int wolfSSL_BIO_free(WOLFSSL_BIO* bio)
+    {
+        /* unchain?, doesn't matter in goahead since from free all */
+        WOLFSSL_ENTER("BIO_free");
+        if (bio) {
+            if (bio->close) {
+                if (bio->ssl)
+                    wolfSSL_free(bio->ssl);
+                if (bio->fd)
+                    CloseSocket(bio->fd);
+            }
+            if (bio->mem)
+                XFREE(bio->mem, 0, DYNAMIC_TYPE_OPENSSL);
+            XFREE(bio, 0, DYNAMIC_TYPE_OPENSSL);
+        }
+        return 0;
+    }
+
+
+    int wolfSSL_BIO_free_all(WOLFSSL_BIO* bio)
+    {
+        WOLFSSL_ENTER("BIO_free_all");
+        while (bio) {
+            WOLFSSL_BIO* next = bio->next;
+            wolfSSL_BIO_free(bio);
+            bio = next;
+        }
+        return 0;
+    }
+
+
+    int wolfSSL_BIO_read(WOLFSSL_BIO* bio, void* buf, int len)
+    {
+        int  ret;
+        WOLFSSL* ssl = 0;
+        WOLFSSL_BIO* front = bio;
+
+        WOLFSSL_ENTER("BIO_read");
+        /* already got eof, again is error */
+        if (front->eof)
+            return SSL_FATAL_ERROR;
+
+        while(bio && ((ssl = bio->ssl) == 0) )
+            bio = bio->next;
+
+        if (ssl == 0) return BAD_FUNC_ARG;
+
+        ret = wolfSSL_read(ssl, buf, len);
+        if (ret == 0)
+            front->eof = 1;
+        else if (ret < 0) {
+            int err = wolfSSL_get_error(ssl, 0);
+            if ( !(err == SSL_ERROR_WANT_READ || err == SSL_ERROR_WANT_WRITE) )
+                front->eof = 1;
+        }
+        return ret;
+    }
+
+
+    int wolfSSL_BIO_write(WOLFSSL_BIO* bio, const void* data, int len)
+    {
+        int  ret;
+        WOLFSSL* ssl = 0;
+        WOLFSSL_BIO* front = bio;
+
+        WOLFSSL_ENTER("BIO_write");
+        /* already got eof, again is error */
+        if (front->eof)
+            return SSL_FATAL_ERROR;
+
+        while(bio && ((ssl = bio->ssl) == 0) )
+            bio = bio->next;
+
+        if (ssl == 0) return BAD_FUNC_ARG;
+
+        ret = wolfSSL_write(ssl, data, len);
+        if (ret == 0)
+            front->eof = 1;
+        else if (ret < 0) {
+            int err = wolfSSL_get_error(ssl, 0);
+            if ( !(err == SSL_ERROR_WANT_READ || err == SSL_ERROR_WANT_WRITE) )
+                front->eof = 1;
+        }
+
+        return ret;
+    }
+
+
+    WOLFSSL_BIO* wolfSSL_BIO_push(WOLFSSL_BIO* top, WOLFSSL_BIO* append)
+    {
+        WOLFSSL_ENTER("BIO_push");
+        top->next    = append;
+        append->prev = top;
+
+        return top;
+    }
+
+
+    int wolfSSL_BIO_flush(WOLFSSL_BIO* bio)
+    {
+        /* for wolfSSL no flushing needed */
+        WOLFSSL_ENTER("BIO_flush");
+        (void)bio;
+        return 1;
+    }
+
+
+#endif /* OPENSSL_EXTRA || GOAHEAD_WS */
+
+
+#if defined(OPENSSL_EXTRA) || defined(HAVE_WEBSERVER)
+
+    void wolfSSL_CTX_set_default_passwd_cb_userdata(WOLFSSL_CTX* ctx,
+                                                   void* userdata)
+    {
+        WOLFSSL_ENTER("SSL_CTX_set_default_passwd_cb_userdata");
+        ctx->userdata = userdata;
+    }
+
+
+    void wolfSSL_CTX_set_default_passwd_cb(WOLFSSL_CTX* ctx, pem_password_cb cb)
+    {
+        WOLFSSL_ENTER("SSL_CTX_set_default_passwd_cb");
+        ctx->passwd_cb = cb;
+    }
+
+    int wolfSSL_num_locks(void)
+    {
+        return 0;
+    }
+
+    void wolfSSL_set_locking_callback(void (*f)(int, int, const char*, int))
+    {
+        (void)f;
+    }
+
+    void wolfSSL_set_id_callback(unsigned long (*f)(void))
+    {
+        (void)f;
+    }
+
+    unsigned long wolfSSL_ERR_get_error(void)
+    {
+        /* TODO: */
+        return 0;
+    }
+
+#ifndef NO_MD5
+
+    int wolfSSL_EVP_BytesToKey(const WOLFSSL_EVP_CIPHER* type,
+                       const WOLFSSL_EVP_MD* md, const byte* salt,
+                       const byte* data, int sz, int count, byte* key, byte* iv)
+    {
+        int  keyLen = 0;
+        int  ivLen  = 0;
+        int  j;
+        int  keyLeft;
+        int  ivLeft;
+        int  keyOutput = 0;
+        byte digest[MD5_DIGEST_SIZE];
+    #ifdef WOLFSSL_SMALL_STACK
+        Md5* md5 = NULL;
+    #else
+        Md5  md5[1];
+    #endif
+
+    #ifdef WOLFSSL_SMALL_STACK
+        md5 = (Md5*)XMALLOC(sizeof(Md5), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (md5 == NULL)
+            return 0;
+    #endif
+
+        WOLFSSL_ENTER("EVP_BytesToKey");
+        wc_InitMd5(md5);
+
+        /* only support MD5 for now */
+        if (XSTRNCMP(md, "MD5", 3) != 0) return 0;
+
+        /* only support CBC DES and AES for now */
+        if (XSTRNCMP(type, "DES-CBC", 7) == 0) {
+            keyLen = DES_KEY_SIZE;
+            ivLen  = DES_IV_SIZE;
+        }
+        else if (XSTRNCMP(type, "DES-EDE3-CBC", 12) == 0) {
+            keyLen = DES3_KEY_SIZE;
+            ivLen  = DES_IV_SIZE;
+        }
+        else if (XSTRNCMP(type, "AES-128-CBC", 11) == 0) {
+            keyLen = AES_128_KEY_SIZE;
+            ivLen  = AES_IV_SIZE;
+        }
+        else if (XSTRNCMP(type, "AES-192-CBC", 11) == 0) {
+            keyLen = AES_192_KEY_SIZE;
+            ivLen  = AES_IV_SIZE;
+        }
+        else if (XSTRNCMP(type, "AES-256-CBC", 11) == 0) {
+            keyLen = AES_256_KEY_SIZE;
+            ivLen  = AES_IV_SIZE;
+        }
+        else {
+        #ifdef WOLFSSL_SMALL_STACK
+            XFREE(md5, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        #endif
+            return 0;
+        }
+
+        keyLeft   = keyLen;
+        ivLeft    = ivLen;
+
+        while (keyOutput < (keyLen + ivLen)) {
+            int digestLeft = MD5_DIGEST_SIZE;
+            /* D_(i - 1) */
+            if (keyOutput)                      /* first time D_0 is empty */
+                wc_Md5Update(md5, digest, MD5_DIGEST_SIZE);
+            /* data */
+            wc_Md5Update(md5, data, sz);
+            /* salt */
+            if (salt)
+                wc_Md5Update(md5, salt, EVP_SALT_SIZE);
+            wc_Md5Final(md5, digest);
+            /* count */
+            for (j = 1; j < count; j++) {
+                wc_Md5Update(md5, digest, MD5_DIGEST_SIZE);
+                wc_Md5Final(md5, digest);
+            }
+
+            if (keyLeft) {
+                int store = min(keyLeft, MD5_DIGEST_SIZE);
+                XMEMCPY(&key[keyLen - keyLeft], digest, store);
+
+                keyOutput  += store;
+                keyLeft    -= store;
+                digestLeft -= store;
+            }
+
+            if (ivLeft && digestLeft) {
+                int store = min(ivLeft, digestLeft);
+                XMEMCPY(&iv[ivLen - ivLeft], &digest[MD5_DIGEST_SIZE -
+                                                    digestLeft], store);
+                keyOutput += store;
+                ivLeft    -= store;
+            }
+        }
+
+    #ifdef WOLFSSL_SMALL_STACK
+        XFREE(md5, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    #endif
+
+        return keyOutput == (keyLen + ivLen) ? keyOutput : 0;
+    }
+
+#endif /* NO_MD5 */
+
+#endif /* OPENSSL_EXTRA || HAVE_WEBSERVER */
+
+
+#ifdef OPENSSL_EXTRA
+
+    unsigned long wolfSSLeay(void)
+    {
+        return SSLEAY_VERSION_NUMBER;
+    }
+
+
+    const char* wolfSSLeay_version(int type)
+    {
+        static const char* version = "SSLeay wolfSSL compatibility";
+        (void)type;
+        return version;
+    }
+
+
+#ifndef NO_MD5
+    void wolfSSL_MD5_Init(WOLFSSL_MD5_CTX* md5)
+    {
+        typedef char md5_test[sizeof(MD5_CTX) >= sizeof(Md5) ? 1 : -1];
+        (void)sizeof(md5_test);
+
+        WOLFSSL_ENTER("MD5_Init");
+        wc_InitMd5((Md5*)md5);
+    }
+
+
+    void wolfSSL_MD5_Update(WOLFSSL_MD5_CTX* md5, const void* input,
+                           unsigned long sz)
+    {
+        WOLFSSL_ENTER("wolfSSL_MD5_Update");
+        wc_Md5Update((Md5*)md5, (const byte*)input, (word32)sz);
+    }
+
+
+    void wolfSSL_MD5_Final(byte* input, WOLFSSL_MD5_CTX* md5)
+    {
+        WOLFSSL_ENTER("MD5_Final");
+        wc_Md5Final((Md5*)md5, input);
+    }
+#endif /* NO_MD5 */
+
+
+#ifndef NO_SHA
+    void wolfSSL_SHA_Init(WOLFSSL_SHA_CTX* sha)
+    {
+        typedef char sha_test[sizeof(SHA_CTX) >= sizeof(Sha) ? 1 : -1];
+        (void)sizeof(sha_test);
+
+        WOLFSSL_ENTER("SHA_Init");
+        wc_InitSha((Sha*)sha);  /* OpenSSL compat, no ret */
+    }
+
+
+    void wolfSSL_SHA_Update(WOLFSSL_SHA_CTX* sha, const void* input,
+                           unsigned long sz)
+    {
+        WOLFSSL_ENTER("SHA_Update");
+        wc_ShaUpdate((Sha*)sha, (const byte*)input, (word32)sz);
+    }
+
+
+    void wolfSSL_SHA_Final(byte* input, WOLFSSL_SHA_CTX* sha)
+    {
+        WOLFSSL_ENTER("SHA_Final");
+        wc_ShaFinal((Sha*)sha, input);
+    }
+
+
+    void wolfSSL_SHA1_Init(WOLFSSL_SHA_CTX* sha)
+    {
+        WOLFSSL_ENTER("SHA1_Init");
+        SHA_Init(sha);
+    }
+
+
+    void wolfSSL_SHA1_Update(WOLFSSL_SHA_CTX* sha, const void* input,
+                            unsigned long sz)
+    {
+        WOLFSSL_ENTER("SHA1_Update");
+        SHA_Update(sha, input, sz);
+    }
+
+
+    void wolfSSL_SHA1_Final(byte* input, WOLFSSL_SHA_CTX* sha)
+    {
+        WOLFSSL_ENTER("SHA1_Final");
+        SHA_Final(input, sha);
+    }
+#endif /* NO_SHA */
+
+
+    void wolfSSL_SHA256_Init(WOLFSSL_SHA256_CTX* sha256)
+    {
+        typedef char sha_test[sizeof(SHA256_CTX) >= sizeof(Sha256) ? 1 : -1];
+        (void)sizeof(sha_test);
+
+        WOLFSSL_ENTER("SHA256_Init");
+        wc_InitSha256((Sha256*)sha256);  /* OpenSSL compat, no error */
+    }
+
+
+    void wolfSSL_SHA256_Update(WOLFSSL_SHA256_CTX* sha, const void* input,
+                              unsigned long sz)
+    {
+        WOLFSSL_ENTER("SHA256_Update");
+        wc_Sha256Update((Sha256*)sha, (const byte*)input, (word32)sz);
+        /* OpenSSL compat, no error */
+    }
+
+
+    void wolfSSL_SHA256_Final(byte* input, WOLFSSL_SHA256_CTX* sha)
+    {
+        WOLFSSL_ENTER("SHA256_Final");
+        wc_Sha256Final((Sha256*)sha, input);
+        /* OpenSSL compat, no error */
+    }
+
+
+    #ifdef WOLFSSL_SHA384
+
+    void wolfSSL_SHA384_Init(WOLFSSL_SHA384_CTX* sha)
+    {
+        typedef char sha_test[sizeof(SHA384_CTX) >= sizeof(Sha384) ? 1 : -1];
+        (void)sizeof(sha_test);
+
+        WOLFSSL_ENTER("SHA384_Init");
+        wc_InitSha384((Sha384*)sha);   /* OpenSSL compat, no error */
+    }
+
+
+    void wolfSSL_SHA384_Update(WOLFSSL_SHA384_CTX* sha, const void* input,
+                           unsigned long sz)
+    {
+        WOLFSSL_ENTER("SHA384_Update");
+        wc_Sha384Update((Sha384*)sha, (const byte*)input, (word32)sz);
+        /* OpenSSL compat, no error */
+    }
+
+
+    void wolfSSL_SHA384_Final(byte* input, WOLFSSL_SHA384_CTX* sha)
+    {
+        WOLFSSL_ENTER("SHA384_Final");
+        wc_Sha384Final((Sha384*)sha, input);
+        /* OpenSSL compat, no error */
+    }
+
+    #endif /* WOLFSSL_SHA384 */
+
+
+   #ifdef WOLFSSL_SHA512
+
+    void wolfSSL_SHA512_Init(WOLFSSL_SHA512_CTX* sha)
+    {
+        typedef char sha_test[sizeof(SHA512_CTX) >= sizeof(Sha512) ? 1 : -1];
+        (void)sizeof(sha_test);
+
+        WOLFSSL_ENTER("SHA512_Init");
+        wc_InitSha512((Sha512*)sha);  /* OpenSSL compat, no error */
+    }
+
+
+    void wolfSSL_SHA512_Update(WOLFSSL_SHA512_CTX* sha, const void* input,
+                           unsigned long sz)
+    {
+        WOLFSSL_ENTER("SHA512_Update");
+        wc_Sha512Update((Sha512*)sha, (const byte*)input, (word32)sz);
+        /* OpenSSL compat, no error */
+    }
+
+
+    void wolfSSL_SHA512_Final(byte* input, WOLFSSL_SHA512_CTX* sha)
+    {
+        WOLFSSL_ENTER("SHA512_Final");
+        wc_Sha512Final((Sha512*)sha, input);
+        /* OpenSSL compat, no error */
+    }
+
+    #endif /* WOLFSSL_SHA512 */
+
+
+    #ifndef NO_MD5
+
+    const WOLFSSL_EVP_MD* wolfSSL_EVP_md5(void)
+    {
+        static const char* type = "MD5";
+        WOLFSSL_ENTER("EVP_md5");
+        return type;
+    }
+
+    #endif /* NO_MD5 */
+
+
+#ifndef NO_SHA
+    const WOLFSSL_EVP_MD* wolfSSL_EVP_sha1(void)
+    {
+        static const char* type = "SHA";
+        WOLFSSL_ENTER("EVP_sha1");
+        return type;
+    }
+#endif /* NO_SHA */
+
+
+    const WOLFSSL_EVP_MD* wolfSSL_EVP_sha256(void)
+    {
+        static const char* type = "SHA256";
+        WOLFSSL_ENTER("EVP_sha256");
+        return type;
+    }
+
+    #ifdef WOLFSSL_SHA384
+
+    const WOLFSSL_EVP_MD* wolfSSL_EVP_sha384(void)
+    {
+        static const char* type = "SHA384";
+        WOLFSSL_ENTER("EVP_sha384");
+        return type;
+    }
+
+    #endif /* WOLFSSL_SHA384 */
+
+    #ifdef WOLFSSL_SHA512
+
+    const WOLFSSL_EVP_MD* wolfSSL_EVP_sha512(void)
+    {
+        static const char* type = "SHA512";
+        WOLFSSL_ENTER("EVP_sha512");
+        return type;
+    }
+
+    #endif /* WOLFSSL_SHA512 */
+
+
+    void wolfSSL_EVP_MD_CTX_init(WOLFSSL_EVP_MD_CTX* ctx)
+    {
+        WOLFSSL_ENTER("EVP_CIPHER_MD_CTX_init");
+        (void)ctx;
+        /* do nothing */
+    }
+
+
+    const WOLFSSL_EVP_CIPHER* wolfSSL_EVP_aes_128_cbc(void)
+    {
+        static const char* type = "AES128-CBC";
+        WOLFSSL_ENTER("wolfSSL_EVP_aes_128_cbc");
+        return type;
+    }
+
+
+    const WOLFSSL_EVP_CIPHER* wolfSSL_EVP_aes_192_cbc(void)
+    {
+        static const char* type = "AES192-CBC";
+        WOLFSSL_ENTER("wolfSSL_EVP_aes_192_cbc");
+        return type;
+    }
+
+
+    const WOLFSSL_EVP_CIPHER* wolfSSL_EVP_aes_256_cbc(void)
+    {
+        static const char* type = "AES256-CBC";
+        WOLFSSL_ENTER("wolfSSL_EVP_aes_256_cbc");
+        return type;
+    }
+
+
+    const WOLFSSL_EVP_CIPHER* wolfSSL_EVP_aes_128_ctr(void)
+    {
+        static const char* type = "AES128-CTR";
+        WOLFSSL_ENTER("wolfSSL_EVP_aes_128_ctr");
+        return type;
+    }
+
+
+    const WOLFSSL_EVP_CIPHER* wolfSSL_EVP_aes_192_ctr(void)
+    {
+        static const char* type = "AES192-CTR";
+        WOLFSSL_ENTER("wolfSSL_EVP_aes_192_ctr");
+        return type;
+    }
+
+
+    const WOLFSSL_EVP_CIPHER* wolfSSL_EVP_aes_256_ctr(void)
+    {
+        static const char* type = "AES256-CTR";
+        WOLFSSL_ENTER("wolfSSL_EVP_aes_256_ctr");
+        return type;
+    }
+
+
+    const WOLFSSL_EVP_CIPHER* wolfSSL_EVP_des_cbc(void)
+    {
+        static const char* type = "DES-CBC";
+        WOLFSSL_ENTER("wolfSSL_EVP_des_cbc");
+        return type;
+    }
+
+
+    const WOLFSSL_EVP_CIPHER* wolfSSL_EVP_des_ede3_cbc(void)
+    {
+        static const char* type = "DES-EDE3-CBC";
+        WOLFSSL_ENTER("wolfSSL_EVP_des_ede3_cbc");
+        return type;
+    }
+
+
+    const WOLFSSL_EVP_CIPHER* wolfSSL_EVP_rc4(void)
+    {
+        static const char* type = "ARC4";
+        WOLFSSL_ENTER("wolfSSL_EVP_rc4");
+        return type;
+    }
+
+
+    const WOLFSSL_EVP_CIPHER* wolfSSL_EVP_enc_null(void)
+    {
+        static const char* type = "NULL";
+        WOLFSSL_ENTER("wolfSSL_EVP_enc_null");
+        return type;
+    }
+
+
+    int wolfSSL_EVP_MD_CTX_cleanup(WOLFSSL_EVP_MD_CTX* ctx)
+    {
+        WOLFSSL_ENTER("EVP_MD_CTX_cleanup");
+        (void)ctx;
+        return 0;
+    }
+
+
+
+    void wolfSSL_EVP_CIPHER_CTX_init(WOLFSSL_EVP_CIPHER_CTX* ctx)
+    {
+        WOLFSSL_ENTER("EVP_CIPHER_CTX_init");
+        if (ctx) {
+            ctx->cipherType = 0xff;   /* no init */
+            ctx->keyLen     = 0;
+            ctx->enc        = 1;      /* start in encrypt mode */
+        }
+    }
+
+
+    /* SSL_SUCCESS on ok */
+    int wolfSSL_EVP_CIPHER_CTX_cleanup(WOLFSSL_EVP_CIPHER_CTX* ctx)
+    {
+        WOLFSSL_ENTER("EVP_CIPHER_CTX_cleanup");
+        if (ctx) {
+            ctx->cipherType = 0xff;  /* no more init */
+            ctx->keyLen     = 0;
+        }
+
+        return SSL_SUCCESS;
+    }
+
+
+    /* SSL_SUCCESS on ok */
+    int  wolfSSL_EVP_CipherInit(WOLFSSL_EVP_CIPHER_CTX* ctx,
+                               const WOLFSSL_EVP_CIPHER* type, byte* key,
+                               byte* iv, int enc)
+    {
+#if defined(NO_AES) && defined(NO_DES3)
+        (void)iv;
+        (void)enc;
+#else
+        int ret = 0;
+#endif
+
+        WOLFSSL_ENTER("wolfSSL_EVP_CipherInit");
+        if (ctx == NULL) {
+            WOLFSSL_MSG("no ctx");
+            return 0;   /* failure */
+        }
+
+        if (type == NULL && ctx->cipherType == 0xff) {
+            WOLFSSL_MSG("no type set");
+            return 0;   /* failure */
+        }
+
+#ifndef NO_AES
+        if (ctx->cipherType == AES_128_CBC_TYPE || (type &&
+                                       XSTRNCMP(type, "AES128-CBC", 10) == 0)) {
+            WOLFSSL_MSG("AES-128-CBC");
+            ctx->cipherType = AES_128_CBC_TYPE;
+            ctx->keyLen     = 16;
+            if (enc == 0 || enc == 1)
+                ctx->enc = enc ? 1 : 0;
+            if (key) {
+                ret = wc_AesSetKey(&ctx->cipher.aes, key, ctx->keyLen, iv,
+                                ctx->enc ? AES_ENCRYPTION : AES_DECRYPTION);
+                if (ret != 0)
+                    return ret;
+            }
+            if (iv && key == NULL) {
+                ret = wc_AesSetIV(&ctx->cipher.aes, iv);
+                if (ret != 0)
+                    return ret;
+            }
+        }
+        else if (ctx->cipherType == AES_192_CBC_TYPE || (type &&
+                                       XSTRNCMP(type, "AES192-CBC", 10) == 0)) {
+            WOLFSSL_MSG("AES-192-CBC");
+            ctx->cipherType = AES_192_CBC_TYPE;
+            ctx->keyLen     = 24;
+            if (enc == 0 || enc == 1)
+                ctx->enc = enc ? 1 : 0;
+            if (key) {
+                ret = wc_AesSetKey(&ctx->cipher.aes, key, ctx->keyLen, iv,
+                                ctx->enc ? AES_ENCRYPTION : AES_DECRYPTION);
+                if (ret != 0)
+                    return ret;
+            }
+            if (iv && key == NULL) {
+                ret = wc_AesSetIV(&ctx->cipher.aes, iv);
+                if (ret != 0)
+                    return ret;
+            }
+        }
+        else if (ctx->cipherType == AES_256_CBC_TYPE || (type &&
+                                       XSTRNCMP(type, "AES256-CBC", 10) == 0)) {
+            WOLFSSL_MSG("AES-256-CBC");
+            ctx->cipherType = AES_256_CBC_TYPE;
+            ctx->keyLen     = 32;
+            if (enc == 0 || enc == 1)
+                ctx->enc = enc ? 1 : 0;
+            if (key) {
+                ret = wc_AesSetKey(&ctx->cipher.aes, key, ctx->keyLen, iv,
+                                ctx->enc ? AES_ENCRYPTION : AES_DECRYPTION);
+                if (ret != 0)
+                    return ret;
+            }
+            if (iv && key == NULL) {
+                ret = wc_AesSetIV(&ctx->cipher.aes, iv);
+                if (ret != 0)
+                    return ret;
+            }
+        }
+#ifdef WOLFSSL_AES_COUNTER
+        else if (ctx->cipherType == AES_128_CTR_TYPE || (type &&
+                                       XSTRNCMP(type, "AES128-CTR", 10) == 0)) {
+            WOLFSSL_MSG("AES-128-CTR");
+            ctx->cipherType = AES_128_CTR_TYPE;
+            ctx->keyLen     = 16;
+            if (enc == 0 || enc == 1)
+                ctx->enc = enc ? 1 : 0;
+            if (key) {
+                ret = wc_AesSetKey(&ctx->cipher.aes, key, ctx->keyLen, iv,
+                                AES_ENCRYPTION);
+                if (ret != 0)
+                    return ret;
+            }
+            if (iv && key == NULL) {
+                ret = wc_AesSetIV(&ctx->cipher.aes, iv);
+                if (ret != 0)
+                    return ret;
+            }
+        }
+        else if (ctx->cipherType == AES_192_CTR_TYPE || (type &&
+                                       XSTRNCMP(type, "AES192-CTR", 10) == 0)) {
+            WOLFSSL_MSG("AES-192-CTR");
+            ctx->cipherType = AES_192_CTR_TYPE;
+            ctx->keyLen     = 24;
+            if (enc == 0 || enc == 1)
+                ctx->enc = enc ? 1 : 0;
+            if (key) {
+                ret = wc_AesSetKey(&ctx->cipher.aes, key, ctx->keyLen, iv,
+                                AES_ENCRYPTION);
+                if (ret != 0)
+                    return ret;
+            }
+            if (iv && key == NULL) {
+                ret = wc_AesSetIV(&ctx->cipher.aes, iv);
+                if (ret != 0)
+                    return ret;
+            }
+        }
+        else if (ctx->cipherType == AES_256_CTR_TYPE || (type &&
+                                       XSTRNCMP(type, "AES256-CTR", 10) == 0)) {
+            WOLFSSL_MSG("AES-256-CTR");
+            ctx->cipherType = AES_256_CTR_TYPE;
+            ctx->keyLen     = 32;
+            if (enc == 0 || enc == 1)
+                ctx->enc = enc ? 1 : 0;
+            if (key) {
+                ret = wc_AesSetKey(&ctx->cipher.aes, key, ctx->keyLen, iv,
+                                AES_ENCRYPTION);
+                if (ret != 0)
+                    return ret;
+            }
+            if (iv && key == NULL) {
+                ret = wc_AesSetIV(&ctx->cipher.aes, iv);
+                if (ret != 0)
+                    return ret;
+            }
+        }
+#endif /* WOLFSSL_AES_CTR */
+#endif /* NO_AES */
+
+#ifndef NO_DES3
+        else if (ctx->cipherType == DES_CBC_TYPE || (type &&
+                                       XSTRNCMP(type, "DES-CBC", 7) == 0)) {
+            WOLFSSL_MSG("DES-CBC");
+            ctx->cipherType = DES_CBC_TYPE;
+            ctx->keyLen     = 8;
+            if (enc == 0 || enc == 1)
+                ctx->enc = enc ? 1 : 0;
+            if (key) {
+                ret = wc_Des_SetKey(&ctx->cipher.des, key, iv,
+                          ctx->enc ? DES_ENCRYPTION : DES_DECRYPTION);
+                if (ret != 0)
+                    return ret;
+            }
+
+            if (iv && key == NULL)
+                wc_Des_SetIV(&ctx->cipher.des, iv);
+        }
+        else if (ctx->cipherType == DES_EDE3_CBC_TYPE || (type &&
+                                     XSTRNCMP(type, "DES-EDE3-CBC", 11) == 0)) {
+            WOLFSSL_MSG("DES-EDE3-CBC");
+            ctx->cipherType = DES_EDE3_CBC_TYPE;
+            ctx->keyLen     = 24;
+            if (enc == 0 || enc == 1)
+                ctx->enc = enc ? 1 : 0;
+            if (key) {
+                ret = wc_Des3_SetKey(&ctx->cipher.des3, key, iv,
+                          ctx->enc ? DES_ENCRYPTION : DES_DECRYPTION);
+                if (ret != 0)
+                    return ret;
+            }
+
+            if (iv && key == NULL) {
+                ret = wc_Des3_SetIV(&ctx->cipher.des3, iv);
+                if (ret != 0)
+                    return ret;
+            }
+        }
+#endif /* NO_DES3 */
+#ifndef NO_RC4
+        else if (ctx->cipherType == ARC4_TYPE || (type &&
+                                     XSTRNCMP(type, "ARC4", 4) == 0)) {
+            WOLFSSL_MSG("ARC4");
+            ctx->cipherType = ARC4_TYPE;
+            if (ctx->keyLen == 0)  /* user may have already set */
+                ctx->keyLen = 16;  /* default to 128 */
+            if (key)
+                wc_Arc4SetKey(&ctx->cipher.arc4, key, ctx->keyLen);
+        }
+#endif /* NO_RC4 */
+        else if (ctx->cipherType == NULL_CIPHER_TYPE || (type &&
+                                     XSTRNCMP(type, "NULL", 4) == 0)) {
+            WOLFSSL_MSG("NULL cipher");
+            ctx->cipherType = NULL_CIPHER_TYPE;
+            ctx->keyLen = 0;
+        }
+        else
+            return 0;   /* failure */
+
+
+        return SSL_SUCCESS;
+    }
+
+
+    /* SSL_SUCCESS on ok */
+    int wolfSSL_EVP_CIPHER_CTX_key_length(WOLFSSL_EVP_CIPHER_CTX* ctx)
+    {
+        WOLFSSL_ENTER("wolfSSL_EVP_CIPHER_CTX_key_length");
+        if (ctx)
+            return ctx->keyLen;
+
+        return 0;   /* failure */
+    }
+
+
+    /* SSL_SUCCESS on ok */
+    int wolfSSL_EVP_CIPHER_CTX_set_key_length(WOLFSSL_EVP_CIPHER_CTX* ctx,
+                                             int keylen)
+    {
+        WOLFSSL_ENTER("wolfSSL_EVP_CIPHER_CTX_set_key_length");
+        if (ctx)
+            ctx->keyLen = keylen;
+        else
+            return 0;  /* failure */
+
+        return SSL_SUCCESS;
+    }
+
+
+    /* SSL_SUCCESS on ok */
+    int wolfSSL_EVP_Cipher(WOLFSSL_EVP_CIPHER_CTX* ctx, byte* dst, byte* src,
+                          word32 len)
+    {
+        int ret = 0;
+        WOLFSSL_ENTER("wolfSSL_EVP_Cipher");
+
+        if (ctx == NULL || dst == NULL || src == NULL) {
+            WOLFSSL_MSG("Bad function argument");
+            return 0;  /* failure */
+        }
+
+        if (ctx->cipherType == 0xff) {
+            WOLFSSL_MSG("no init");
+            return 0;  /* failure */
+        }
+
+        switch (ctx->cipherType) {
+
+#ifndef NO_AES
+            case AES_128_CBC_TYPE :
+            case AES_192_CBC_TYPE :
+            case AES_256_CBC_TYPE :
+                WOLFSSL_MSG("AES CBC");
+                if (ctx->enc)
+                    ret = wc_AesCbcEncrypt(&ctx->cipher.aes, dst, src, len);
+                else
+                    ret = wc_AesCbcDecrypt(&ctx->cipher.aes, dst, src, len);
+                break;
+
+#ifdef WOLFSSL_AES_COUNTER
+            case AES_128_CTR_TYPE :
+            case AES_192_CTR_TYPE :
+            case AES_256_CTR_TYPE :
+                    WOLFSSL_MSG("AES CTR");
+                    wc_AesCtrEncrypt(&ctx->cipher.aes, dst, src, len);
+                break;
+#endif
+#endif /* NO_AES */
+
+#ifndef NO_DES3
+            case DES_CBC_TYPE :
+                if (ctx->enc)
+                    wc_Des_CbcEncrypt(&ctx->cipher.des, dst, src, len);
+                else
+                    wc_Des_CbcDecrypt(&ctx->cipher.des, dst, src, len);
+                break;
+
+            case DES_EDE3_CBC_TYPE :
+                if (ctx->enc)
+                    ret = wc_Des3_CbcEncrypt(&ctx->cipher.des3, dst, src, len);
+                else
+                    ret = wc_Des3_CbcDecrypt(&ctx->cipher.des3, dst, src, len);
+                break;
+#endif
+
+#ifndef NO_RC4
+            case ARC4_TYPE :
+                wc_Arc4Process(&ctx->cipher.arc4, dst, src, len);
+                break;
+#endif
+
+            case NULL_CIPHER_TYPE :
+                XMEMCPY(dst, src, len);
+                break;
+
+            default: {
+                WOLFSSL_MSG("bad type");
+                return 0;  /* failure */
+            }
+        }
+
+        if (ret != 0) {
+            WOLFSSL_MSG("wolfSSL_EVP_Cipher failure");
+            return 0;  /* failuer */
+        }
+
+        WOLFSSL_MSG("wolfSSL_EVP_Cipher success");
+        return SSL_SUCCESS;  /* success */
+    }
+
+
+    /* store for external read of iv, SSL_SUCCESS on success */
+    int  wolfSSL_StoreExternalIV(WOLFSSL_EVP_CIPHER_CTX* ctx)
+    {
+        WOLFSSL_ENTER("wolfSSL_StoreExternalIV");
+
+        if (ctx == NULL) {
+            WOLFSSL_MSG("Bad function argument");
+            return SSL_FATAL_ERROR;
+        }
+
+        switch (ctx->cipherType) {
+
+#ifndef NO_AES
+            case AES_128_CBC_TYPE :
+            case AES_192_CBC_TYPE :
+            case AES_256_CBC_TYPE :
+                WOLFSSL_MSG("AES CBC");
+                memcpy(ctx->iv, &ctx->cipher.aes.reg, AES_BLOCK_SIZE);
+                break;
+
+#ifdef WOLFSSL_AES_COUNTER
+            case AES_128_CTR_TYPE :
+            case AES_192_CTR_TYPE :
+            case AES_256_CTR_TYPE :
+                WOLFSSL_MSG("AES CTR");
+                memcpy(ctx->iv, &ctx->cipher.aes.reg, AES_BLOCK_SIZE);
+                break;
+#endif /* WOLFSSL_AES_COUNTER */
+
+#endif /* NO_AES */
+
+#ifndef NO_DES3
+            case DES_CBC_TYPE :
+                WOLFSSL_MSG("DES CBC");
+                memcpy(ctx->iv, &ctx->cipher.des.reg, DES_BLOCK_SIZE);
+                break;
+
+            case DES_EDE3_CBC_TYPE :
+                WOLFSSL_MSG("DES EDE3 CBC");
+                memcpy(ctx->iv, &ctx->cipher.des3.reg, DES_BLOCK_SIZE);
+                break;
+#endif
+
+            case ARC4_TYPE :
+                WOLFSSL_MSG("ARC4");
+                break;
+
+            case NULL_CIPHER_TYPE :
+                WOLFSSL_MSG("NULL");
+                break;
+
+            default: {
+                WOLFSSL_MSG("bad type");
+                return SSL_FATAL_ERROR;
+            }
+        }
+        return SSL_SUCCESS;
+    }
+
+
+    /* set internal IV from external, SSL_SUCCESS on success */
+    int  wolfSSL_SetInternalIV(WOLFSSL_EVP_CIPHER_CTX* ctx)
+    {
+
+        WOLFSSL_ENTER("wolfSSL_SetInternalIV");
+
+        if (ctx == NULL) {
+            WOLFSSL_MSG("Bad function argument");
+            return SSL_FATAL_ERROR;
+        }
+
+        switch (ctx->cipherType) {
+
+#ifndef NO_AES
+            case AES_128_CBC_TYPE :
+            case AES_192_CBC_TYPE :
+            case AES_256_CBC_TYPE :
+                WOLFSSL_MSG("AES CBC");
+                memcpy(&ctx->cipher.aes.reg, ctx->iv, AES_BLOCK_SIZE);
+                break;
+
+#ifdef WOLFSSL_AES_COUNTER
+            case AES_128_CTR_TYPE :
+            case AES_192_CTR_TYPE :
+            case AES_256_CTR_TYPE :
+                WOLFSSL_MSG("AES CTR");
+                memcpy(&ctx->cipher.aes.reg, ctx->iv, AES_BLOCK_SIZE);
+                break;
+#endif
+
+#endif /* NO_AES */
+
+#ifndef NO_DES3
+            case DES_CBC_TYPE :
+                WOLFSSL_MSG("DES CBC");
+                memcpy(&ctx->cipher.des.reg, ctx->iv, DES_BLOCK_SIZE);
+                break;
+
+            case DES_EDE3_CBC_TYPE :
+                WOLFSSL_MSG("DES EDE3 CBC");
+                memcpy(&ctx->cipher.des3.reg, ctx->iv, DES_BLOCK_SIZE);
+                break;
+#endif
+
+            case ARC4_TYPE :
+                WOLFSSL_MSG("ARC4");
+                break;
+
+            case NULL_CIPHER_TYPE :
+                WOLFSSL_MSG("NULL");
+                break;
+
+            default: {
+                WOLFSSL_MSG("bad type");
+                return SSL_FATAL_ERROR;
+            }
+        }
+        return SSL_SUCCESS;
+    }
+
+
+    /* SSL_SUCCESS on ok */
+    int wolfSSL_EVP_DigestInit(WOLFSSL_EVP_MD_CTX* ctx, const WOLFSSL_EVP_MD* type)
+    {
+        WOLFSSL_ENTER("EVP_DigestInit");
+        if (XSTRNCMP(type, "SHA256", 6) == 0) {
+             ctx->macType = SHA256;
+             wolfSSL_SHA256_Init((SHA256_CTX*)&ctx->hash);
+        }
+    #ifdef WOLFSSL_SHA384
+        else if (XSTRNCMP(type, "SHA384", 6) == 0) {
+             ctx->macType = SHA384;
+             wolfSSL_SHA384_Init((SHA384_CTX*)&ctx->hash);
+        }
+    #endif
+    #ifdef WOLFSSL_SHA512
+        else if (XSTRNCMP(type, "SHA512", 6) == 0) {
+             ctx->macType = SHA512;
+             wolfSSL_SHA512_Init((SHA512_CTX*)&ctx->hash);
+        }
+    #endif
+    #ifndef NO_MD5
+        else if (XSTRNCMP(type, "MD5", 3) == 0) {
+            ctx->macType = MD5;
+            wolfSSL_MD5_Init((MD5_CTX*)&ctx->hash);
+        }
+    #endif
+    #ifndef NO_SHA
+        /* has to be last since would pick or 256, 384, or 512 too */
+        else if (XSTRNCMP(type, "SHA", 3) == 0) {
+             ctx->macType = SHA;
+             wolfSSL_SHA_Init((SHA_CTX*)&ctx->hash);
+        }
+    #endif /* NO_SHA */
+        else
+             return BAD_FUNC_ARG;
+
+        return SSL_SUCCESS;
+    }
+
+
+    /* SSL_SUCCESS on ok */
+    int wolfSSL_EVP_DigestUpdate(WOLFSSL_EVP_MD_CTX* ctx, const void* data,
+                                unsigned long sz)
+    {
+        WOLFSSL_ENTER("EVP_DigestUpdate");
+
+        switch (ctx->macType) {
+#ifndef NO_MD5
+            case MD5:
+                wolfSSL_MD5_Update((MD5_CTX*)&ctx->hash, data,
+                                  (unsigned long)sz);
+                break;
+#endif
+#ifndef NO_SHA
+            case SHA:
+                wolfSSL_SHA_Update((SHA_CTX*)&ctx->hash, data,
+                                  (unsigned long)sz);
+                break;
+#endif
+#ifndef NO_SHA256
+            case SHA256:
+                wolfSSL_SHA256_Update((SHA256_CTX*)&ctx->hash, data,
+                                     (unsigned long)sz);
+                break;
+#endif
+#ifdef WOLFSSL_SHA384
+            case SHA384:
+                wolfSSL_SHA384_Update((SHA384_CTX*)&ctx->hash, data,
+                                     (unsigned long)sz);
+                break;
+#endif
+#ifdef WOLFSSL_SHA512
+            case SHA512:
+                wolfSSL_SHA512_Update((SHA512_CTX*)&ctx->hash, data,
+                                     (unsigned long)sz);
+                break;
+#endif
+            default:
+                return BAD_FUNC_ARG;
+        }
+
+        return SSL_SUCCESS;
+    }
+
+
+    /* SSL_SUCCESS on ok */
+    int wolfSSL_EVP_DigestFinal(WOLFSSL_EVP_MD_CTX* ctx, unsigned char* md,
+                               unsigned int* s)
+    {
+        WOLFSSL_ENTER("EVP_DigestFinal");
+        switch (ctx->macType) {
+#ifndef NO_MD5
+            case MD5:
+                wolfSSL_MD5_Final(md, (MD5_CTX*)&ctx->hash);
+                if (s) *s = MD5_DIGEST_SIZE;
+                break;
+#endif
+#ifndef NO_SHA
+            case SHA:
+                wolfSSL_SHA_Final(md, (SHA_CTX*)&ctx->hash);
+                if (s) *s = SHA_DIGEST_SIZE;
+                break;
+#endif
+#ifndef NO_SHA256
+            case SHA256:
+                wolfSSL_SHA256_Final(md, (SHA256_CTX*)&ctx->hash);
+                if (s) *s = SHA256_DIGEST_SIZE;
+                break;
+#endif
+#ifdef WOLFSSL_SHA384
+            case SHA384:
+                wolfSSL_SHA384_Final(md, (SHA384_CTX*)&ctx->hash);
+                if (s) *s = SHA384_DIGEST_SIZE;
+                break;
+#endif
+#ifdef WOLFSSL_SHA512
+            case SHA512:
+                wolfSSL_SHA512_Final(md, (SHA512_CTX*)&ctx->hash);
+                if (s) *s = SHA512_DIGEST_SIZE;
+                break;
+#endif
+            default:
+                return BAD_FUNC_ARG;
+        }
+
+        return SSL_SUCCESS;
+    }
+
+
+    /* SSL_SUCCESS on ok */
+    int wolfSSL_EVP_DigestFinal_ex(WOLFSSL_EVP_MD_CTX* ctx, unsigned char* md,
+                                  unsigned int* s)
+    {
+        WOLFSSL_ENTER("EVP_DigestFinal_ex");
+        return EVP_DigestFinal(ctx, md, s);
+    }
+
+
+    unsigned char* wolfSSL_HMAC(const WOLFSSL_EVP_MD* evp_md, const void* key,
+                               int key_len, const unsigned char* d, int n,
+                               unsigned char* md, unsigned int* md_len)
+    {
+        int type;
+        unsigned char* ret = NULL;
+#ifdef WOLFSSL_SMALL_STACK
+        Hmac* hmac = NULL;
+#else
+        Hmac  hmac[1];
+#endif
+
+        WOLFSSL_ENTER("HMAC");
+        if (!md)
+            return NULL;  /* no static buffer support */
+
+        if (XSTRNCMP(evp_md, "MD5", 3) == 0)
+            type = MD5;
+        else if (XSTRNCMP(evp_md, "SHA", 3) == 0)
+            type = SHA;
+        else
+            return NULL;
+
+    #ifdef WOLFSSL_SMALL_STACK
+        hmac = (Hmac*)XMALLOC(sizeof(Hmac), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (hmac == NULL)
+            return NULL;
+    #endif
+
+        if (wc_HmacSetKey(hmac, type, (const byte*)key, key_len) == 0)
+            if (wc_HmacUpdate(hmac, d, n) == 0)
+                if (wc_HmacFinal(hmac, md) == 0) {
+                    if (md_len)
+                        *md_len = (type == MD5) ? (int)MD5_DIGEST_SIZE
+                                                : (int)SHA_DIGEST_SIZE;
+                    ret = md;
+                }
+
+    #ifdef WOLFSSL_SMALL_STACK
+        XFREE(hmac, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    #endif
+
+        return ret;
+    }
+
+    void wolfSSL_ERR_clear_error(void)
+    {
+        /* TODO: */
+    }
+
+
+    int wolfSSL_RAND_status(void)
+    {
+        return SSL_SUCCESS;  /* wolfCrypt provides enough seed internally */
+    }
+
+
+
+    void wolfSSL_RAND_add(const void* add, int len, double entropy)
+    {
+        (void)add;
+        (void)len;
+        (void)entropy;
+
+        /* wolfSSL seeds/adds internally, use explicit RNG if you want
+           to take control */
+    }
+
+
+#ifndef NO_DES3
+    /* SSL_SUCCESS on ok */
+    int wolfSSL_DES_key_sched(WOLFSSL_const_DES_cblock* key,
+                             WOLFSSL_DES_key_schedule* schedule)
+    {
+        WOLFSSL_ENTER("DES_key_sched");
+        XMEMCPY(schedule, key, sizeof(const_DES_cblock));
+        return SSL_SUCCESS;
+    }
+
+
+    void wolfSSL_DES_cbc_encrypt(const unsigned char* input,
+                     unsigned char* output, long length,
+                     WOLFSSL_DES_key_schedule* schedule, WOLFSSL_DES_cblock* ivec,
+                     int enc)
+    {
+        Des myDes;
+
+        WOLFSSL_ENTER("DES_cbc_encrypt");
+
+        /* OpenSSL compat, no ret */
+        wc_Des_SetKey(&myDes, (const byte*)schedule, (const byte*)ivec, !enc);
+
+        if (enc)
+            wc_Des_CbcEncrypt(&myDes, output, input, (word32)length);
+        else
+            wc_Des_CbcDecrypt(&myDes, output, input, (word32)length);
+    }
+
+
+    /* correctly sets ivec for next call */
+    void wolfSSL_DES_ncbc_encrypt(const unsigned char* input,
+                     unsigned char* output, long length,
+                     WOLFSSL_DES_key_schedule* schedule, WOLFSSL_DES_cblock* ivec,
+                     int enc)
+    {
+        Des myDes;
+
+        WOLFSSL_ENTER("DES_ncbc_encrypt");
+
+        /* OpenSSL compat, no ret */
+        wc_Des_SetKey(&myDes, (const byte*)schedule, (const byte*)ivec, !enc);
+
+        if (enc)
+            wc_Des_CbcEncrypt(&myDes, output, input, (word32)length);
+        else
+            wc_Des_CbcDecrypt(&myDes, output, input, (word32)length);
+
+        XMEMCPY(ivec, output + length - sizeof(DES_cblock), sizeof(DES_cblock));
+    }
+
+#endif /* NO_DES3 */
+
+
+    void wolfSSL_ERR_free_strings(void)
+    {
+        /* handled internally */
+    }
+
+
+    void wolfSSL_ERR_remove_state(unsigned long state)
+    {
+        /* TODO: GetErrors().Remove(); */
+        (void)state;
+    }
+
+
+    void wolfSSL_EVP_cleanup(void)
+    {
+        /* nothing to do here */
+    }
+
+
+    void wolfSSL_cleanup_all_ex_data(void)
+    {
+        /* nothing to do here */
+    }
+
+
+    int wolfSSL_clear(WOLFSSL* ssl)
+    {
+        (void)ssl;
+        /* TODO: GetErrors().Remove(); */
+        return SSL_SUCCESS;
+    }
+
+
+    long wolfSSL_SSL_SESSION_set_timeout(WOLFSSL_SESSION* ses, long t)
+    {
+        word32 tmptime;
+        if (!ses || t < 0)
+            return BAD_FUNC_ARG;
+
+        tmptime = t & 0xFFFFFFFF;
+
+        ses->timeout = tmptime;
+
+        return SSL_SUCCESS;
+    }
+
+
+    long wolfSSL_CTX_set_mode(WOLFSSL_CTX* ctx, long mode)
+    {
+        /* SSL_MODE_ACCEPT_MOVING_WRITE_BUFFER is wolfSSL default mode */
+
+        WOLFSSL_ENTER("SSL_CTX_set_mode");
+        if (mode == SSL_MODE_ENABLE_PARTIAL_WRITE)
+            ctx->partialWrite = 1;
+
+        return mode;
+    }
+
+
+    long wolfSSL_SSL_get_mode(WOLFSSL* ssl)
+    {
+        /* TODO: */
+        (void)ssl;
+        return 0;
+    }
+
+
+    long wolfSSL_CTX_get_mode(WOLFSSL_CTX* ctx)
+    {
+        /* TODO: */
+        (void)ctx;
+        return 0;
+    }
+
+
+    void wolfSSL_CTX_set_default_read_ahead(WOLFSSL_CTX* ctx, int m)
+    {
+        /* TODO: maybe? */
+        (void)ctx;
+        (void)m;
+    }
+
+
+    int wolfSSL_CTX_set_session_id_context(WOLFSSL_CTX* ctx,
+                                       const unsigned char* sid_ctx,
+                                       unsigned int sid_ctx_len)
+    {
+        /* No application specific context needed for wolfSSL */
+        (void)ctx;
+        (void)sid_ctx;
+        (void)sid_ctx_len;
+        return SSL_SUCCESS;
+    }
+
+
+    long wolfSSL_CTX_sess_get_cache_size(WOLFSSL_CTX* ctx)
+    {
+        /* TODO: maybe? */
+        (void)ctx;
+        return (~0);
+    }
+
+    unsigned long wolfSSL_ERR_get_error_line_data(const char** file, int* line,
+                                          const char** data, int *flags)
+    {
+        /* Not implemented */
+        (void)file;
+        (void)line;
+        (void)data;
+        (void)flags;
+        return 0;
+    }
+
+#endif /* OPENSSL_EXTRA */
+
+
+#if defined(KEEP_PEER_CERT)
+
+    WOLFSSL_X509* wolfSSL_get_peer_certificate(WOLFSSL* ssl)
+    {
+        WOLFSSL_ENTER("SSL_get_peer_certificate");
+        if (ssl->peerCert.issuer.sz)
+            return &ssl->peerCert;
+        else
+            return 0;
+    }
+
+#endif /* KEEP_PEER_CERT */
+
+
+#if defined(KEEP_PEER_CERT) || defined(SESSION_CERTS)
+
+    void wolfSSL_FreeX509(WOLFSSL_X509* x509)
+    {
+        WOLFSSL_ENTER("wolfSSL_FreeX509");
+        FreeX509(x509);
+    }
+
+
+    /* return the next, if any, altname from the peer cert */
+    char* wolfSSL_X509_get_next_altname(WOLFSSL_X509* cert)
+    {
+        char* ret = NULL;
+        WOLFSSL_ENTER("wolfSSL_X509_get_next_altname");
+
+        /* don't have any to work with */
+        if (cert == NULL || cert->altNames == NULL)
+            return NULL;
+
+        /* already went through them */
+        if (cert->altNamesNext == NULL)
+            return NULL;
+
+        ret = cert->altNamesNext->name;
+        cert->altNamesNext = cert->altNamesNext->next;
+
+        return ret;
+    }
+
+
+    WOLFSSL_X509_NAME* wolfSSL_X509_get_issuer_name(WOLFSSL_X509* cert)
+    {
+        WOLFSSL_ENTER("X509_get_issuer_name");
+        return &cert->issuer;
+    }
+
+
+    WOLFSSL_X509_NAME* wolfSSL_X509_get_subject_name(WOLFSSL_X509* cert)
+    {
+        WOLFSSL_ENTER("X509_get_subject_name");
+        return &cert->subject;
+    }
+
+
+    int wolfSSL_X509_get_isCA(WOLFSSL_X509* x509)
+    {
+        int isCA = 0;
+
+        WOLFSSL_ENTER("wolfSSL_X509_get_isCA");
+
+        if (x509 != NULL)
+            isCA = x509->isCa;
+
+        WOLFSSL_LEAVE("wolfSSL_X509_get_isCA", isCA);
+
+        return isCA;
+    }
+
+
+#ifdef OPENSSL_EXTRA
+    int wolfSSL_X509_ext_isSet_by_NID(WOLFSSL_X509* x509, int nid)
+    {
+        int isSet = 0;
+
+        WOLFSSL_ENTER("wolfSSL_X509_ext_isSet_by_NID");
+
+        if (x509 != NULL) {
+            switch (nid) {
+                case BASIC_CA_OID: isSet = x509->basicConstSet; break;
+                case ALT_NAMES_OID: isSet = x509->subjAltNameSet; break;
+                case AUTH_KEY_OID: isSet = x509->authKeyIdSet; break;
+                case SUBJ_KEY_OID: isSet = x509->subjKeyIdSet; break;
+                case KEY_USAGE_OID: isSet = x509->keyUsageSet; break;
+                #ifdef WOLFSSL_SEP
+                    case CERT_POLICY_OID: isSet = x509->certPolicySet; break;
+                #endif /* WOLFSSL_SEP */
+            }
+        }
+
+        WOLFSSL_LEAVE("wolfSSL_X509_ext_isSet_by_NID", isSet);
+
+        return isSet;
+    }
+
+
+    int wolfSSL_X509_ext_get_critical_by_NID(WOLFSSL_X509* x509, int nid)
+    {
+        int crit = 0;
+
+        WOLFSSL_ENTER("wolfSSL_X509_ext_get_critical_by_NID");
+
+        if (x509 != NULL) {
+            switch (nid) {
+                case BASIC_CA_OID: crit = x509->basicConstCrit; break;
+                case ALT_NAMES_OID: crit = x509->subjAltNameCrit; break;
+                case AUTH_KEY_OID: crit = x509->authKeyIdCrit; break;
+                case SUBJ_KEY_OID: crit = x509->subjKeyIdCrit; break;
+                case KEY_USAGE_OID: crit = x509->keyUsageCrit; break;
+                #ifdef WOLFSSL_SEP
+                    case CERT_POLICY_OID: crit = x509->certPolicyCrit; break;
+                #endif /* WOLFSSL_SEP */
+            }
+        }
+
+        WOLFSSL_LEAVE("wolfSSL_X509_ext_get_critical_by_NID", crit);
+
+        return crit;
+    }
+
+
+    int wolfSSL_X509_get_isSet_pathLength(WOLFSSL_X509* x509)
+    {
+        int isSet = 0;
+
+        WOLFSSL_ENTER("wolfSSL_X509_get_isSet_pathLength");
+
+        if (x509 != NULL)
+            isSet = x509->basicConstPlSet;
+
+        WOLFSSL_LEAVE("wolfSSL_X509_get_isSet_pathLength", isSet);
+
+        return isSet;
+    }
+
+
+    word32 wolfSSL_X509_get_pathLength(WOLFSSL_X509* x509)
+    {
+        word32 pathLength = 0;
+
+        WOLFSSL_ENTER("wolfSSL_X509_get_pathLength");
+
+        if (x509 != NULL)
+            pathLength = x509->pathLength;
+
+        WOLFSSL_LEAVE("wolfSSL_X509_get_pathLength", pathLength);
+
+        return pathLength;
+    }
+
+
+    unsigned int wolfSSL_X509_get_keyUsage(WOLFSSL_X509* x509)
+    {
+        word16 usage = 0;
+
+        WOLFSSL_ENTER("wolfSSL_X509_get_keyUsage");
+
+        if (x509 != NULL)
+            usage = x509->keyUsage;
+
+        WOLFSSL_LEAVE("wolfSSL_X509_get_keyUsage", usage);
+
+        return usage;
+    }
+
+
+    byte* wolfSSL_X509_get_authorityKeyID(
+                                      WOLFSSL_X509* x509, byte* dst, int* dstLen)
+    {
+        byte *id = NULL;
+        int copySz = 0;
+
+        WOLFSSL_ENTER("wolfSSL_X509_get_authorityKeyID");
+
+        if (x509 != NULL) {
+            if (x509->authKeyIdSet) {
+                copySz = min(dstLen != NULL ? *dstLen : 0,
+                                                        (int)x509->authKeyIdSz);
+                id = x509->authKeyId;
+            }
+
+            if (dst != NULL && dstLen != NULL && id != NULL && copySz > 0) {
+                XMEMCPY(dst, id, copySz);
+                id = dst;
+                *dstLen = copySz;
+            }
+        }
+
+        WOLFSSL_LEAVE("wolfSSL_X509_get_authorityKeyID", copySz);
+
+        return id;
+    }
+
+
+    byte* wolfSSL_X509_get_subjectKeyID(
+                                      WOLFSSL_X509* x509, byte* dst, int* dstLen)
+    {
+        byte *id = NULL;
+        int copySz = 0;
+
+        WOLFSSL_ENTER("wolfSSL_X509_get_subjectKeyID");
+
+        if (x509 != NULL) {
+            if (x509->subjKeyIdSet) {
+                copySz = min(dstLen != NULL ? *dstLen : 0,
+                                                        (int)x509->subjKeyIdSz);
+                id = x509->subjKeyId;
+            }
+
+            if (dst != NULL && dstLen != NULL && id != NULL && copySz > 0) {
+                XMEMCPY(dst, id, copySz);
+                id = dst;
+                *dstLen = copySz;
+            }
+        }
+
+        WOLFSSL_LEAVE("wolfSSL_X509_get_subjectKeyID", copySz);
+
+        return id;
+    }
+
+
+    int wolfSSL_X509_NAME_entry_count(WOLFSSL_X509_NAME* name)
+    {
+        int count = 0;
+
+        WOLFSSL_ENTER("wolfSSL_X509_NAME_entry_count");
+
+        if (name != NULL)
+            count = name->fullName.entryCount;
+
+        WOLFSSL_LEAVE("wolfSSL_X509_NAME_entry_count", count);
+        return count;
+    }
+
+
+    int wolfSSL_X509_NAME_get_text_by_NID(WOLFSSL_X509_NAME* name,
+                                                    int nid, char* buf, int len)
+    {
+        char *text = NULL;
+        int textSz = 0;
+
+        WOLFSSL_ENTER("wolfSSL_X509_NAME_get_text_by_NID");
+
+        switch (nid) {
+            case ASN_COMMON_NAME:
+                text = name->fullName.fullName + name->fullName.cnIdx;
+                textSz = name->fullName.cnLen;
+                break;
+            case ASN_SUR_NAME:
+                text = name->fullName.fullName + name->fullName.snIdx;
+                textSz = name->fullName.snLen;
+                break;
+            case ASN_SERIAL_NUMBER:
+                text = name->fullName.fullName + name->fullName.serialIdx;
+                textSz = name->fullName.serialLen;
+                break;
+            case ASN_COUNTRY_NAME:
+                text = name->fullName.fullName + name->fullName.cIdx;
+                textSz = name->fullName.cLen;
+                break;
+            case ASN_LOCALITY_NAME:
+                text = name->fullName.fullName + name->fullName.lIdx;
+                textSz = name->fullName.lLen;
+                break;
+            case ASN_STATE_NAME:
+                text = name->fullName.fullName + name->fullName.stIdx;
+                textSz = name->fullName.stLen;
+                break;
+            case ASN_ORG_NAME:
+                text = name->fullName.fullName + name->fullName.oIdx;
+                textSz = name->fullName.oLen;
+                break;
+            case ASN_ORGUNIT_NAME:
+                text = name->fullName.fullName + name->fullName.ouIdx;
+                textSz = name->fullName.ouLen;
+                break;
+            default:
+                break;
+        }
+
+        if (buf != NULL && text != NULL) {
+            textSz = min(textSz, len);
+            XMEMCPY(buf, text, textSz);
+            buf[textSz] = '\0';
+        }
+
+        WOLFSSL_LEAVE("wolfSSL_X509_NAME_get_text_by_NID", textSz);
+        return textSz;
+    }
+#endif
+
+
+    /* copy name into in buffer, at most sz bytes, if buffer is null will
+       malloc buffer, call responsible for freeing                     */
+    char* wolfSSL_X509_NAME_oneline(WOLFSSL_X509_NAME* name, char* in, int sz)
+    {
+        int copySz = min(sz, name->sz);
+
+        WOLFSSL_ENTER("wolfSSL_X509_NAME_oneline");
+        if (!name->sz) return in;
+
+        if (!in) {
+            in = (char*)XMALLOC(name->sz, 0, DYNAMIC_TYPE_OPENSSL);
+            if (!in ) return in;
+            copySz = name->sz;
+        }
+
+        if (copySz == 0)
+            return in;
+
+        XMEMCPY(in, name->name, copySz - 1);
+        in[copySz - 1] = 0;
+
+        return in;
+    }
+
+
+    int wolfSSL_X509_get_signature_type(WOLFSSL_X509* x509)
+    {
+        int type = 0;
+
+        WOLFSSL_ENTER("wolfSSL_X509_get_signature_type");
+
+        if (x509 != NULL)
+            type = x509->sigOID;
+
+        return type;
+    }
+
+
+    int wolfSSL_X509_get_signature(WOLFSSL_X509* x509,
+                                                 unsigned char* buf, int* bufSz)
+    {
+        WOLFSSL_ENTER("wolfSSL_X509_get_signature");
+        if (x509 == NULL || bufSz == NULL || *bufSz < (int)x509->sig.length)
+            return SSL_FATAL_ERROR;
+
+        if (buf != NULL)
+            XMEMCPY(buf, x509->sig.buffer, x509->sig.length);
+        *bufSz = x509->sig.length;
+
+        return SSL_SUCCESS;
+    }
+
+
+    /* write X509 serial number in unsigned binary to buffer
+       buffer needs to be at least EXTERNAL_SERIAL_SIZE (32) for all cases
+       return SSL_SUCCESS on success */
+    int wolfSSL_X509_get_serial_number(WOLFSSL_X509* x509, byte* in, int* inOutSz)
+    {
+        WOLFSSL_ENTER("wolfSSL_X509_get_serial_number");
+        if (x509 == NULL || in == NULL ||
+                                   inOutSz == NULL || *inOutSz < x509->serialSz)
+            return BAD_FUNC_ARG;
+
+        XMEMCPY(in, x509->serial, x509->serialSz);
+        *inOutSz = x509->serialSz;
+
+        return SSL_SUCCESS;
+    }
+
+
+    const byte* wolfSSL_X509_get_der(WOLFSSL_X509* x509, int* outSz)
+    {
+        WOLFSSL_ENTER("wolfSSL_X509_get_der");
+
+        if (x509 == NULL || outSz == NULL)
+            return NULL;
+
+        *outSz = (int)x509->derCert.length;
+        return x509->derCert.buffer;
+    }
+
+
+    int wolfSSL_X509_version(WOLFSSL_X509* x509)
+    {
+        WOLFSSL_ENTER("wolfSSL_X509_version");
+
+        if (x509 == NULL)
+            return 0;
+
+        return x509->version;
+    }
+
+
+    const byte* wolfSSL_X509_notBefore(WOLFSSL_X509* x509)
+    {
+        WOLFSSL_ENTER("wolfSSL_X509_notBefore");
+
+        if (x509 == NULL)
+            return NULL;
+
+        return x509->notBefore;
+    }
+
+
+    const byte* wolfSSL_X509_notAfter(WOLFSSL_X509* x509)
+    {
+        WOLFSSL_ENTER("wolfSSL_X509_notAfter");
+
+        if (x509 == NULL)
+            return NULL;
+
+        return x509->notAfter;
+    }
+
+
+#ifdef WOLFSSL_SEP
+
+/* copy oid into in buffer, at most *inOutSz bytes, if buffer is null will
+   malloc buffer, call responsible for freeing. Actual size returned in
+   *inOutSz. Requires inOutSz be non-null */
+byte* wolfSSL_X509_get_device_type(WOLFSSL_X509* x509, byte* in, int *inOutSz)
+{
+    int copySz;
+
+    WOLFSSL_ENTER("wolfSSL_X509_get_dev_type");
+    if (inOutSz == NULL) return NULL;
+    if (!x509->deviceTypeSz) return in;
+
+    copySz = min(*inOutSz, x509->deviceTypeSz);
+
+    if (!in) {
+        in = (byte*)XMALLOC(x509->deviceTypeSz, 0, DYNAMIC_TYPE_OPENSSL);
+        if (!in) return in;
+        copySz = x509->deviceTypeSz;
+    }
+
+    XMEMCPY(in, x509->deviceType, copySz);
+    *inOutSz = copySz;
+
+    return in;
+}
+
+
+byte* wolfSSL_X509_get_hw_type(WOLFSSL_X509* x509, byte* in, int* inOutSz)
+{
+    int copySz;
+
+    WOLFSSL_ENTER("wolfSSL_X509_get_hw_type");
+    if (inOutSz == NULL) return NULL;
+    if (!x509->hwTypeSz) return in;
+
+    copySz = min(*inOutSz, x509->hwTypeSz);
+
+    if (!in) {
+        in = (byte*)XMALLOC(x509->hwTypeSz, 0, DYNAMIC_TYPE_OPENSSL);
+        if (!in) return in;
+        copySz = x509->hwTypeSz;
+    }
+
+    XMEMCPY(in, x509->hwType, copySz);
+    *inOutSz = copySz;
+
+    return in;
+}
+
+
+byte* wolfSSL_X509_get_hw_serial_number(WOLFSSL_X509* x509,byte* in,int* inOutSz)
+{
+    int copySz;
+
+    WOLFSSL_ENTER("wolfSSL_X509_get_hw_serial_number");
+    if (inOutSz == NULL) return NULL;
+    if (!x509->hwTypeSz) return in;
+
+    copySz = min(*inOutSz, x509->hwSerialNumSz);
+
+    if (!in) {
+        in = (byte*)XMALLOC(x509->hwSerialNumSz, 0, DYNAMIC_TYPE_OPENSSL);
+        if (!in) return in;
+        copySz = x509->hwSerialNumSz;
+    }
+
+    XMEMCPY(in, x509->hwSerialNum, copySz);
+    *inOutSz = copySz;
+
+    return in;
+}
+
+#endif /* WOLFSSL_SEP */
+
+
+WOLFSSL_X509* wolfSSL_X509_d2i(WOLFSSL_X509** x509, const byte* in, int len)
+{
+    WOLFSSL_X509 *newX509 = NULL;
+
+    WOLFSSL_ENTER("wolfSSL_X509_d2i");
+
+    if (in != NULL && len != 0) {
+    #ifdef WOLFSSL_SMALL_STACK
+        DecodedCert* cert = NULL;
+    #else
+        DecodedCert  cert[1];
+    #endif
+
+    #ifdef WOLFSSL_SMALL_STACK
+        cert = (DecodedCert*)XMALLOC(sizeof(DecodedCert), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+        if (cert == NULL)
+            return NULL;
+    #endif
+
+        InitDecodedCert(cert, (byte*)in, len, NULL);
+        if (ParseCertRelative(cert, CERT_TYPE, 0, NULL) == 0) {
+            newX509 = (WOLFSSL_X509*)XMALLOC(sizeof(WOLFSSL_X509),
+                                                       NULL, DYNAMIC_TYPE_X509);
+            if (newX509 != NULL) {
+                InitX509(newX509, 1);
+                if (CopyDecodedToX509(newX509, cert) != 0) {
+                    XFREE(newX509, NULL, DYNAMIC_TYPE_X509);
+                    newX509 = NULL;
+                }
+            }
+        }
+        FreeDecodedCert(cert);
+    #ifdef WOLFSSL_SMALL_STACK
+        XFREE(cert, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    #endif
+    }
+
+    if (x509 != NULL)
+        *x509 = newX509;
+
+    return newX509;
+}
+
+
+#ifndef NO_FILESYSTEM
+
+#ifndef NO_STDIO_FILESYSTEM
+
+WOLFSSL_X509* wolfSSL_X509_d2i_fp(WOLFSSL_X509** x509, XFILE file)
+{
+    WOLFSSL_X509* newX509 = NULL;
+
+    WOLFSSL_ENTER("wolfSSL_X509_d2i_fp");
+
+    if (file != XBADFILE) {
+        byte* fileBuffer = NULL;
+        long sz = 0;
+
+        XFSEEK(file, 0, XSEEK_END);
+        sz = XFTELL(file);
+        XREWIND(file);
+
+        if (sz < 0) {
+            WOLFSSL_MSG("Bad tell on FILE");
+            return NULL;
+        }
+
+        fileBuffer = (byte*)XMALLOC(sz, NULL, DYNAMIC_TYPE_FILE);
+        if (fileBuffer != NULL) {
+            int ret = (int)XFREAD(fileBuffer, sz, 1, file);
+            if (ret > 0) {
+                newX509 = wolfSSL_X509_d2i(NULL, fileBuffer, (int)sz);
+            }
+            XFREE(fileBuffer, NULL, DYNAMIC_TYPE_FILE);
+        }
+    }
+
+    if (x509 != NULL)
+        *x509 = newX509;
+
+    return newX509;
+}
+
+#endif /* NO_STDIO_FILESYSTEM */
+
+WOLFSSL_X509* wolfSSL_X509_load_certificate_file(const char* fname, int format)
+{
+#ifdef WOLFSSL_SMALL_STACK
+    byte  staticBuffer[1]; /* force heap usage */
+#else
+    byte  staticBuffer[FILE_BUFFER_SIZE];
+#endif
+    byte* fileBuffer = staticBuffer;
+    int   dynamic = 0;
+    int   ret;
+    long  sz = 0;
+    XFILE file;
+
+    WOLFSSL_X509* x509 = NULL;
+    buffer der;
+
+    WOLFSSL_ENTER("wolfSSL_X509_load_certificate");
+
+    /* Check the inputs */
+    if ((fname == NULL) ||
+        (format != SSL_FILETYPE_ASN1 && format != SSL_FILETYPE_PEM))
+        return NULL;
+
+    file = XFOPEN(fname, "rb");
+    if (file == XBADFILE)
+        return NULL;
+
+    XFSEEK(file, 0, XSEEK_END);
+    sz = XFTELL(file);
+    XREWIND(file);
+
+    if (sz > (long)sizeof(staticBuffer)) {
+        fileBuffer = (byte*)XMALLOC(sz, NULL, DYNAMIC_TYPE_FILE);
+        if (fileBuffer == NULL) {
+            XFCLOSE(file);
+            return NULL;
+        }
+        dynamic = 1;
+    }
+    else if (sz < 0) {
+        XFCLOSE(file);
+        return NULL;
+    }
+
+    ret = (int)XFREAD(fileBuffer, sz, 1, file);
+    if (ret < 0) {
+        XFCLOSE(file);
+        if (dynamic)
+            XFREE(fileBuffer, NULL, DYNAMIC_TYPE_FILE);
+        return NULL;
+    }
+
+    XFCLOSE(file);
+
+    der.buffer = NULL;
+    der.length = 0;
+
+    if (format == SSL_FILETYPE_PEM) {
+        int ecc = 0;
+    #ifdef WOLFSSL_SMALL_STACK
+        EncryptedInfo* info = NULL;
+    #else
+        EncryptedInfo  info[1];
+    #endif
+
+    #ifdef WOLFSSL_SMALL_STACK
+        info = (EncryptedInfo*)XMALLOC(sizeof(EncryptedInfo), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+        if (info == NULL) {
+            if (dynamic)
+                XFREE(fileBuffer, NULL, DYNAMIC_TYPE_FILE);
+
+            return NULL;
+        }
+    #endif
+
+        info->set = 0;
+        info->ctx = NULL;
+        info->consumed = 0;
+
+        if (PemToDer(fileBuffer, sz, CERT_TYPE, &der, NULL, info, &ecc) != 0)
+        {
+            /* Only time this should fail, and leave `der` with a buffer
+               is when the Base64 Decode fails. Release `der.buffer` in
+               that case. */
+            if (der.buffer != NULL) {
+                XFREE(der.buffer, NULL, DYNAMIC_TYPE_CERT);
+                der.buffer = NULL;
+            }
+        }
+
+    #ifdef WOLFSSL_SMALL_STACK
+        XFREE(info, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    #endif
+    }
+    else {
+        der.buffer = (byte*)XMALLOC(sz, NULL, DYNAMIC_TYPE_CERT);
+        if (der.buffer != NULL) {
+            XMEMCPY(der.buffer, fileBuffer, sz);
+            der.length = (word32)sz;
+        }
+    }
+
+    if (dynamic)
+        XFREE(fileBuffer, NULL, DYNAMIC_TYPE_FILE);
+
+    /* At this point we want `der` to have the certificate in DER format */
+    /* ready to be decoded. */
+    if (der.buffer != NULL) {
+    #ifdef WOLFSSL_SMALL_STACK
+        DecodedCert* cert = NULL;
+    #else
+        DecodedCert  cert[1];
+    #endif
+
+    #ifdef WOLFSSL_SMALL_STACK
+        cert = (DecodedCert*)XMALLOC(sizeof(DecodedCert), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+        if (cert != NULL)
+    #endif
+        {
+            InitDecodedCert(cert, der.buffer, der.length, NULL);
+            if (ParseCertRelative(cert, CERT_TYPE, 0, NULL) == 0) {
+                x509 = (WOLFSSL_X509*)XMALLOC(sizeof(WOLFSSL_X509), NULL,
+                                                             DYNAMIC_TYPE_X509);
+                if (x509 != NULL) {
+                    InitX509(x509, 1);
+                    if (CopyDecodedToX509(x509, cert) != 0) {
+                        XFREE(x509, NULL, DYNAMIC_TYPE_X509);
+                        x509 = NULL;
+                    }
+                }
+            }
+
+            FreeDecodedCert(cert);
+        #ifdef WOLFSSL_SMALL_STACK
+            XFREE(cert, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        #endif
+        }
+
+        XFREE(der.buffer, NULL, DYNAMIC_TYPE_CERT);
+    }
+
+    return x509;
+}
+
+#endif /* NO_FILESYSTEM */
+
+#endif /* KEEP_PEER_CERT || SESSION_CERTS */
+
+
+#ifdef OPENSSL_EXTRA
+int wolfSSL_set_ex_data(WOLFSSL* ssl, int idx, void* data)
+{
+#ifdef FORTRESS
+    if (ssl != NULL && idx < MAX_EX_DATA)
+    {
+        ssl->ex_data[idx] = data;
+        return SSL_SUCCESS;
+    }
+#else
+    (void)ssl;
+    (void)idx;
+    (void)data;
+#endif
+    return SSL_FAILURE;
+}
+
+
+int wolfSSL_set_session_id_context(WOLFSSL* ssl, const unsigned char* id,
+                               unsigned int len)
+{
+    (void)ssl;
+    (void)id;
+    (void)len;
+    return 0;
+}
+
+
+void wolfSSL_set_connect_state(WOLFSSL* ssl)
+{
+    (void)ssl;
+    /* client by default */
+}
+#endif
+
+int wolfSSL_get_shutdown(const WOLFSSL* ssl)
+{
+    return (ssl->options.isClosed  ||
+            ssl->options.connReset ||
+            ssl->options.sentNotify);
+}
+
+
+int wolfSSL_session_reused(WOLFSSL* ssl)
+{
+    return ssl->options.resuming;
+}
+
+#ifdef OPENSSL_EXTRA
+void wolfSSL_SESSION_free(WOLFSSL_SESSION* session)
+{
+    (void)session;
+}
+#endif
+
+const char* wolfSSL_get_version(WOLFSSL* ssl)
+{
+    WOLFSSL_ENTER("SSL_get_version");
+    if (ssl->version.major == SSLv3_MAJOR) {
+        switch (ssl->version.minor) {
+            case SSLv3_MINOR :
+                return "SSLv3";
+            case TLSv1_MINOR :
+                return "TLSv1";
+            case TLSv1_1_MINOR :
+                return "TLSv1.1";
+            case TLSv1_2_MINOR :
+                return "TLSv1.2";
+            default:
+                return "unknown";
+        }
+    }
+    else if (ssl->version.major == DTLS_MAJOR) {
+        switch (ssl->version.minor) {
+            case DTLS_MINOR :
+                return "DTLS";
+            case DTLSv1_2_MINOR :
+                return "DTLSv1.2";
+            default:
+                return "unknown";
+        }
+    }
+    return "unknown";
+}
+
+
+/* current library version */
+const char* wolfSSL_lib_version(void)
+{
+    return LIBWOLFSSL_VERSION_STRING;
+}
+
+
+/* current library version in hex */
+word32 wolfSSL_lib_version_hex(void)
+{
+    return LIBWOLFSSL_VERSION_HEX;
+}
+
+
+int wolfSSL_get_current_cipher_suite(WOLFSSL* ssl)
+{
+    WOLFSSL_ENTER("SSL_get_current_cipher_suite");
+    if (ssl)
+        return (ssl->options.cipherSuite0 << 8) | ssl->options.cipherSuite;
+    return 0;
+}
+
+WOLFSSL_CIPHER* wolfSSL_get_current_cipher(WOLFSSL* ssl)
+{
+    WOLFSSL_ENTER("SSL_get_current_cipher");
+    if (ssl)
+        return &ssl->cipher;
+    else
+        return NULL;
+}
+
+
+const char* wolfSSL_CIPHER_get_name(const WOLFSSL_CIPHER* cipher)
+{
+    (void)cipher;
+
+    WOLFSSL_ENTER("SSL_CIPHER_get_name");
+#ifndef NO_ERROR_STRINGS
+    if (cipher) {
+#if defined(HAVE_CHACHA)
+        if (cipher->ssl->options.cipherSuite0 == CHACHA_BYTE) {
+        /* ChaCha suites */
+        switch (cipher->ssl->options.cipherSuite) {
+#ifdef HAVE_CHACHA
+#ifndef NO_RSA
+            case TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256 :
+                return "TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256";
+
+            case TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256 :
+                return "TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256";
+#endif
+            case TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256 :
+                return "TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256";
+#endif
+            }
+        }
+#endif
+
+#if defined(HAVE_ECC) || defined(HAVE_AESCCM)
+        /* Awkwardly, the ECC cipher suites use the ECC_BYTE as expected,
+         * but the AES-CCM cipher suites also use it, even the ones that
+         * aren't ECC. */
+        if (cipher->ssl->options.cipherSuite0 == ECC_BYTE) {
+        /* ECC suites */
+        switch (cipher->ssl->options.cipherSuite) {
+#ifdef HAVE_ECC
+#ifndef NO_RSA
+            case TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 :
+                return "TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256";
+#endif
+            case TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 :
+                return "TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256";
+#ifndef NO_RSA
+            case TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256 :
+                return "TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256";
+#endif
+            case TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256 :
+                return "TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256";
+#ifndef NO_RSA
+            case TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384 :
+                return "TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384";
+#endif
+            case TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384 :
+                return "TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384";
+#ifndef NO_RSA
+            case TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384 :
+                return "TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384";
+#endif
+            case TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384 :
+                return "TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384";
+#ifndef NO_SHA
+#ifndef NO_RSA
+            case TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA :
+                return "TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA";
+            case TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA :
+                return "TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA";
+#endif
+            case TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA :
+                return "TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA";
+            case TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA :
+                return "TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA";
+#ifndef NO_RC4
+    #ifndef NO_RSA
+            case TLS_ECDHE_RSA_WITH_RC4_128_SHA :
+                return "TLS_ECDHE_RSA_WITH_RC4_128_SHA";
+    #endif
+            case TLS_ECDHE_ECDSA_WITH_RC4_128_SHA :
+                return "TLS_ECDHE_ECDSA_WITH_RC4_128_SHA";
+#endif
+#ifndef NO_DES3
+    #ifndef NO_RSA
+            case TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA :
+                return "TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA";
+    #endif
+            case TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA :
+                return "TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA";
+#endif
+
+#ifndef NO_RSA
+            case TLS_ECDH_RSA_WITH_AES_128_CBC_SHA :
+                return "TLS_ECDH_RSA_WITH_AES_128_CBC_SHA";
+            case TLS_ECDH_RSA_WITH_AES_256_CBC_SHA :
+                return "TLS_ECDH_RSA_WITH_AES_256_CBC_SHA";
+#endif
+            case TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA :
+                return "TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA";
+            case TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA :
+                return "TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA";
+#ifndef NO_RC4
+    #ifndef NO_RSA
+            case TLS_ECDH_RSA_WITH_RC4_128_SHA :
+                return "TLS_ECDH_RSA_WITH_RC4_128_SHA";
+    #endif
+            case TLS_ECDH_ECDSA_WITH_RC4_128_SHA :
+                return "TLS_ECDH_ECDSA_WITH_RC4_128_SHA";
+#endif
+#ifndef NO_DES3
+    #ifndef NO_RSA
+            case TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA :
+                return "TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA";
+    #endif
+            case TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA :
+                return "TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA";
+#endif
+#endif /* NO_SHA */
+
+#ifdef HAVE_AESGCM
+#ifndef NO_RSA
+            case TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 :
+                return "TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256";
+            case TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 :
+                return "TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384";
+#endif
+            case TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 :
+                return "TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256";
+            case TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 :
+                return "TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384";
+#ifndef NO_RSA
+            case TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256 :
+                return "TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256";
+            case TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384 :
+                return "TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384";
+#endif
+            case TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256 :
+                return "TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256";
+            case TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384 :
+                return "TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384";
+#endif
+#endif /* HAVE_ECC */
+
+#ifdef HAVE_AESCCM
+#ifndef NO_RSA
+            case TLS_RSA_WITH_AES_128_CCM_8 :
+                return "TLS_RSA_WITH_AES_128_CCM_8";
+            case TLS_RSA_WITH_AES_256_CCM_8 :
+                return "TLS_RSA_WITH_AES_256_CCM_8";
+#endif
+#ifndef NO_PSK
+            case TLS_PSK_WITH_AES_128_CCM_8 :
+                return "TLS_PSK_WITH_AES_128_CCM_8";
+            case TLS_PSK_WITH_AES_256_CCM_8 :
+                return "TLS_PSK_WITH_AES_256_CCM_8";
+            case TLS_PSK_WITH_AES_128_CCM :
+                return "TLS_PSK_WITH_AES_128_CCM";
+            case TLS_PSK_WITH_AES_256_CCM :
+                return "TLS_PSK_WITH_AES_256_CCM";
+            case TLS_DHE_PSK_WITH_AES_128_CCM :
+                return "TLS_DHE_PSK_WITH_AES_128_CCM";
+            case TLS_DHE_PSK_WITH_AES_256_CCM :
+                return "TLS_DHE_PSK_WITH_AES_256_CCM";
+#endif
+#ifdef HAVE_ECC
+            case TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8:
+                return "TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8";
+            case TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8 :
+                return "TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8";
+#endif
+#endif
+
+            default:
+                return "NONE";
+        }
+        }
+#endif  /* ECC */
+        if (cipher->ssl->options.cipherSuite0 != ECC_BYTE &&
+            cipher->ssl->options.cipherSuite0 != CHACHA_BYTE) {
+
+            /* normal suites */
+        switch (cipher->ssl->options.cipherSuite) {
+#ifndef NO_RSA
+#ifndef NO_RC4
+    #ifndef NO_SHA
+            case SSL_RSA_WITH_RC4_128_SHA :
+                return "SSL_RSA_WITH_RC4_128_SHA";
+    #endif
+    #ifndef NO_MD5
+            case SSL_RSA_WITH_RC4_128_MD5 :
+                return "SSL_RSA_WITH_RC4_128_MD5";
+    #endif
+#endif
+#ifndef NO_SHA
+    #ifndef NO_DES3
+            case SSL_RSA_WITH_3DES_EDE_CBC_SHA :
+                return "SSL_RSA_WITH_3DES_EDE_CBC_SHA";
+    #endif
+            case TLS_RSA_WITH_AES_128_CBC_SHA :
+                return "TLS_RSA_WITH_AES_128_CBC_SHA";
+            case TLS_RSA_WITH_AES_256_CBC_SHA :
+                return "TLS_RSA_WITH_AES_256_CBC_SHA";
+#endif
+            case TLS_RSA_WITH_AES_128_CBC_SHA256 :
+                return "TLS_RSA_WITH_AES_128_CBC_SHA256";
+            case TLS_RSA_WITH_AES_256_CBC_SHA256 :
+                return "TLS_RSA_WITH_AES_256_CBC_SHA256";
+    #ifdef HAVE_BLAKE2
+            case TLS_RSA_WITH_AES_128_CBC_B2B256:
+                return "TLS_RSA_WITH_AES_128_CBC_B2B256";
+            case TLS_RSA_WITH_AES_256_CBC_B2B256:
+                return "TLS_RSA_WITH_AES_256_CBC_B2B256";
+    #endif
+#ifndef NO_SHA
+            case TLS_RSA_WITH_NULL_SHA :
+                return "TLS_RSA_WITH_NULL_SHA";
+#endif
+            case TLS_RSA_WITH_NULL_SHA256 :
+                return "TLS_RSA_WITH_NULL_SHA256";
+#endif /* NO_RSA */
+#ifndef NO_PSK
+#ifndef NO_SHA
+            case TLS_PSK_WITH_AES_128_CBC_SHA :
+                return "TLS_PSK_WITH_AES_128_CBC_SHA";
+            case TLS_PSK_WITH_AES_256_CBC_SHA :
+                return "TLS_PSK_WITH_AES_256_CBC_SHA";
+#endif
+#ifndef NO_SHA256
+            case TLS_PSK_WITH_AES_128_CBC_SHA256 :
+                return "TLS_PSK_WITH_AES_128_CBC_SHA256";
+            case TLS_PSK_WITH_NULL_SHA256 :
+                return "TLS_PSK_WITH_NULL_SHA256";
+            case TLS_DHE_PSK_WITH_AES_128_CBC_SHA256 :
+                return "TLS_DHE_PSK_WITH_AES_128_CBC_SHA256";
+            case TLS_DHE_PSK_WITH_NULL_SHA256 :
+                return "TLS_DHE_PSK_WITH_NULL_SHA256";
+    #ifdef HAVE_AESGCM
+            case TLS_PSK_WITH_AES_128_GCM_SHA256 :
+                return "TLS_PSK_WITH_AES_128_GCM_SHA256";
+            case TLS_DHE_PSK_WITH_AES_128_GCM_SHA256 :
+                return "TLS_DHE_PSK_WITH_AES_128_GCM_SHA256";
+    #endif
+#endif
+#ifdef WOLFSSL_SHA384
+            case TLS_PSK_WITH_AES_256_CBC_SHA384 :
+                return "TLS_PSK_WITH_AES_256_CBC_SHA384";
+            case TLS_PSK_WITH_NULL_SHA384 :
+                return "TLS_PSK_WITH_NULL_SHA384";
+            case TLS_DHE_PSK_WITH_AES_256_CBC_SHA384 :
+                return "TLS_DHE_PSK_WITH_AES_256_CBC_SHA384";
+            case TLS_DHE_PSK_WITH_NULL_SHA384 :
+                return "TLS_DHE_PSK_WITH_NULL_SHA384";
+    #ifdef HAVE_AESGCM
+            case TLS_PSK_WITH_AES_256_GCM_SHA384 :
+                return "TLS_PSK_WITH_AES_256_GCM_SHA384";
+            case TLS_DHE_PSK_WITH_AES_256_GCM_SHA384 :
+                return "TLS_DHE_PSK_WITH_AES_256_GCM_SHA384";
+    #endif
+#endif
+#ifndef NO_SHA
+            case TLS_PSK_WITH_NULL_SHA :
+                return "TLS_PSK_WITH_NULL_SHA";
+#endif
+#endif /* NO_PSK */
+#ifndef NO_RSA
+            case TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 :
+                return "TLS_DHE_RSA_WITH_AES_128_CBC_SHA256";
+            case TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 :
+                return "TLS_DHE_RSA_WITH_AES_256_CBC_SHA256";
+#ifndef NO_SHA
+            case TLS_DHE_RSA_WITH_AES_128_CBC_SHA :
+                return "TLS_DHE_RSA_WITH_AES_128_CBC_SHA";
+            case TLS_DHE_RSA_WITH_AES_256_CBC_SHA :
+                return "TLS_DHE_RSA_WITH_AES_256_CBC_SHA";
+#endif
+#ifndef NO_HC128
+    #ifndef NO_MD5
+            case TLS_RSA_WITH_HC_128_MD5 :
+                return "TLS_RSA_WITH_HC_128_MD5";
+    #endif
+    #ifndef NO_SHA
+            case TLS_RSA_WITH_HC_128_SHA :
+                return "TLS_RSA_WITH_HC_128_SHA";
+    #endif
+    #ifdef HAVE_BLAKE2
+            case TLS_RSA_WITH_HC_128_B2B256:
+                return "TLS_RSA_WITH_HC_128_B2B256";
+    #endif
+#endif /* NO_HC128 */
+#ifndef NO_SHA
+    #ifndef NO_RABBIT
+            case TLS_RSA_WITH_RABBIT_SHA :
+                return "TLS_RSA_WITH_RABBIT_SHA";
+    #endif
+    #ifdef HAVE_NTRU
+        #ifndef NO_RC4
+            case TLS_NTRU_RSA_WITH_RC4_128_SHA :
+                return "TLS_NTRU_RSA_WITH_RC4_128_SHA";
+        #endif
+        #ifndef NO_DES3
+            case TLS_NTRU_RSA_WITH_3DES_EDE_CBC_SHA :
+                return "TLS_NTRU_RSA_WITH_3DES_EDE_CBC_SHA";
+        #endif
+            case TLS_NTRU_RSA_WITH_AES_128_CBC_SHA :
+                return "TLS_NTRU_RSA_WITH_AES_128_CBC_SHA";
+            case TLS_NTRU_RSA_WITH_AES_256_CBC_SHA :
+                return "TLS_NTRU_RSA_WITH_AES_256_CBC_SHA";
+    #endif /* HAVE_NTRU */
+#endif /* NO_SHA */
+            case TLS_RSA_WITH_AES_128_GCM_SHA256 :
+                return "TLS_RSA_WITH_AES_128_GCM_SHA256";
+            case TLS_RSA_WITH_AES_256_GCM_SHA384 :
+                return "TLS_RSA_WITH_AES_256_GCM_SHA384";
+            case TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 :
+                return "TLS_DHE_RSA_WITH_AES_128_GCM_SHA256";
+            case TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 :
+                return "TLS_DHE_RSA_WITH_AES_256_GCM_SHA384";
+#ifndef NO_SHA
+            case TLS_RSA_WITH_CAMELLIA_128_CBC_SHA :
+                return "TLS_RSA_WITH_CAMELLIA_128_CBC_SHA";
+            case TLS_RSA_WITH_CAMELLIA_256_CBC_SHA :
+                return "TLS_RSA_WITH_CAMELLIA_256_CBC_SHA";
+#endif
+            case TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256 :
+                return "TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256";
+            case TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256 :
+                return "TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256";
+#ifndef NO_SHA
+            case TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA :
+                return "TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA";
+            case TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA :
+                return "TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA";
+#endif
+            case TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 :
+                return "TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256";
+            case TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256 :
+                return "TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256";
+#endif /* NO_RSA */
+#ifdef BUILD_TLS_DH_anon_WITH_AES_128_CBC_SHA
+            case TLS_DH_anon_WITH_AES_128_CBC_SHA :
+                return "TLS_DH_anon_WITH_AES_128_CBC_SHA";
+#endif
+            default:
+                return "NONE";
+        }  /* switch */
+        }  /* normal / ECC */
+    }
+#endif /* NO_ERROR_STRINGS */
+    return "NONE";
+}
+
+
+const char* wolfSSL_get_cipher(WOLFSSL* ssl)
+{
+    WOLFSSL_ENTER("wolfSSL_get_cipher");
+    return wolfSSL_CIPHER_get_name(wolfSSL_get_current_cipher(ssl));
+}
+
+#ifdef OPENSSL_EXTRA
+
+
+
+char* wolfSSL_CIPHER_description(WOLFSSL_CIPHER* cipher, char* in, int len)
+{
+    (void)cipher;
+    (void)in;
+    (void)len;
+    return 0;
+}
+
+
+WOLFSSL_SESSION* wolfSSL_get1_session(WOLFSSL* ssl)  /* what's ref count */
+{
+    (void)ssl;
+    return 0;
+}
+
+
+void wolfSSL_X509_free(WOLFSSL_X509* buf)
+{
+    FreeX509(buf);
+}
+
+
+/* was do nothing */
+/*
+void OPENSSL_free(void* buf)
+{
+    (void)buf;
+}
+*/
+
+
+int wolfSSL_OCSP_parse_url(char* url, char** host, char** port, char** path,
+                   int* ssl)
+{
+    (void)url;
+    (void)host;
+    (void)port;
+    (void)path;
+    (void)ssl;
+    return 0;
+}
+
+
+WOLFSSL_METHOD* wolfSSLv2_client_method(void)
+{
+    return 0;
+}
+
+
+WOLFSSL_METHOD* wolfSSLv2_server_method(void)
+{
+    return 0;
+}
+
+
+#ifndef NO_MD4
+
+void wolfSSL_MD4_Init(WOLFSSL_MD4_CTX* md4)
+{
+    /* make sure we have a big enough buffer */
+    typedef char ok[sizeof(md4->buffer) >= sizeof(Md4) ? 1 : -1];
+    (void) sizeof(ok);
+
+    WOLFSSL_ENTER("MD4_Init");
+    wc_InitMd4((Md4*)md4);
+}
+
+
+void wolfSSL_MD4_Update(WOLFSSL_MD4_CTX* md4, const void* data,
+                       unsigned long len)
+{
+    WOLFSSL_ENTER("MD4_Update");
+    wc_Md4Update((Md4*)md4, (const byte*)data, (word32)len);
+}
+
+
+void wolfSSL_MD4_Final(unsigned char* digest, WOLFSSL_MD4_CTX* md4)
+{
+    WOLFSSL_ENTER("MD4_Final");
+    wc_Md4Final((Md4*)md4, digest);
+}
+
+#endif /* NO_MD4 */
+
+
+WOLFSSL_BIO* wolfSSL_BIO_pop(WOLFSSL_BIO* top)
+{
+    (void)top;
+    return 0;
+}
+
+
+int wolfSSL_BIO_pending(WOLFSSL_BIO* bio)
+{
+    (void)bio;
+    return 0;
+}
+
+
+
+WOLFSSL_BIO_METHOD* wolfSSL_BIO_s_mem(void)
+{
+    static WOLFSSL_BIO_METHOD meth;
+
+    WOLFSSL_ENTER("BIO_s_mem");
+    meth.type = BIO_MEMORY;
+
+    return &meth;
+}
+
+
+WOLFSSL_BIO_METHOD* wolfSSL_BIO_f_base64(void)
+{
+    return 0;
+}
+
+
+void wolfSSL_BIO_set_flags(WOLFSSL_BIO* bio, int flags)
+{
+    (void)bio;
+    (void)flags;
+}
+
+
+
+void wolfSSL_RAND_screen(void)
+{
+
+}
+
+
+const char* wolfSSL_RAND_file_name(char* fname, unsigned long len)
+{
+    (void)fname;
+    (void)len;
+    return 0;
+}
+
+
+int wolfSSL_RAND_write_file(const char* fname)
+{
+    (void)fname;
+    return 0;
+}
+
+
+int wolfSSL_RAND_load_file(const char* fname, long len)
+{
+    (void)fname;
+    /* wolfCrypt provides enough entropy internally or will report error */
+    if (len == -1)
+        return 1024;
+    else
+        return (int)len;
+}
+
+
+int wolfSSL_RAND_egd(const char* path)
+{
+    (void)path;
+    return 0;
+}
+
+
+
+WOLFSSL_COMP_METHOD* wolfSSL_COMP_zlib(void)
+{
+    return 0;
+}
+
+
+WOLFSSL_COMP_METHOD* wolfSSL_COMP_rle(void)
+{
+    return 0;
+}
+
+
+int wolfSSL_COMP_add_compression_method(int method, void* data)
+{
+    (void)method;
+    (void)data;
+    return 0;
+}
+
+
+
+int wolfSSL_get_ex_new_index(long idx, void* data, void* cb1, void* cb2,
+                         void* cb3)
+{
+    (void)idx;
+    (void)data;
+    (void)cb1;
+    (void)cb2;
+    (void)cb3;
+    return 0;
+}
+
+
+void wolfSSL_set_dynlock_create_callback(WOLFSSL_dynlock_value* (*f)(
+                                                          const char*, int))
+{
+    (void)f;
+}
+
+
+void wolfSSL_set_dynlock_lock_callback(
+             void (*f)(int, WOLFSSL_dynlock_value*, const char*, int))
+{
+    (void)f;
+}
+
+
+void wolfSSL_set_dynlock_destroy_callback(
+                  void (*f)(WOLFSSL_dynlock_value*, const char*, int))
+{
+    (void)f;
+}
+
+
+
+const char* wolfSSL_X509_verify_cert_error_string(long err)
+{
+    (void)err;
+    return 0;
+}
+
+
+
+int wolfSSL_X509_LOOKUP_add_dir(WOLFSSL_X509_LOOKUP* lookup, const char* dir,
+                               long len)
+{
+    (void)lookup;
+    (void)dir;
+    (void)len;
+    return 0;
+}
+
+
+int wolfSSL_X509_LOOKUP_load_file(WOLFSSL_X509_LOOKUP* lookup,
+                                 const char* file, long len)
+{
+    (void)lookup;
+    (void)file;
+    (void)len;
+    return 0;
+}
+
+
+WOLFSSL_X509_LOOKUP_METHOD* wolfSSL_X509_LOOKUP_hash_dir(void)
+{
+    return 0;
+}
+
+
+WOLFSSL_X509_LOOKUP_METHOD* wolfSSL_X509_LOOKUP_file(void)
+{
+    return 0;
+}
+
+
+
+WOLFSSL_X509_LOOKUP* wolfSSL_X509_STORE_add_lookup(WOLFSSL_X509_STORE* store,
+                                               WOLFSSL_X509_LOOKUP_METHOD* m)
+{
+    (void)store;
+    (void)m;
+    return 0;
+}
+
+
+int wolfSSL_X509_STORE_add_cert(WOLFSSL_X509_STORE* store, WOLFSSL_X509* x509)
+{
+    int result = SSL_FATAL_ERROR;
+
+    WOLFSSL_ENTER("wolfSSL_X509_STORE_add_cert");
+    if (store != NULL && store->cm != NULL && x509 != NULL) {
+        buffer derCert;
+        derCert.buffer = (byte*)XMALLOC(x509->derCert.length,
+                                                   NULL, DYNAMIC_TYPE_CERT);
+        if (derCert.buffer != NULL) {
+            derCert.length = x509->derCert.length;
+                /* AddCA() frees the buffer. */
+            XMEMCPY(derCert.buffer,
+                                x509->derCert.buffer, x509->derCert.length);
+            result = AddCA(store->cm, derCert, WOLFSSL_USER_CA, 1);
+            if (result != SSL_SUCCESS) result = SSL_FATAL_ERROR;
+        }
+    }
+
+    WOLFSSL_LEAVE("wolfSSL_X509_STORE_add_cert", result);
+    return result;
+}
+
+
+WOLFSSL_X509_STORE* wolfSSL_X509_STORE_new(void)
+{
+    WOLFSSL_X509_STORE* store = NULL;
+
+    store = (WOLFSSL_X509_STORE*)XMALLOC(sizeof(WOLFSSL_X509_STORE), NULL, 0);
+    if (store != NULL) {
+        store->cm = wolfSSL_CertManagerNew();
+        if (store->cm == NULL) {
+            XFREE(store, NULL, 0);
+            store = NULL;
+        }
+    }
+
+    return store;
+}
+
+
+void wolfSSL_X509_STORE_free(WOLFSSL_X509_STORE* store)
+{
+    if (store != NULL) {
+        if (store->cm != NULL)
+        wolfSSL_CertManagerFree(store->cm);
+        XFREE(store, NULL, 0);
+    }
+}
+
+
+int wolfSSL_X509_STORE_set_default_paths(WOLFSSL_X509_STORE* store)
+{
+    (void)store;
+    return SSL_SUCCESS;
+}
+
+
+int wolfSSL_X509_STORE_get_by_subject(WOLFSSL_X509_STORE_CTX* ctx, int idx,
+                            WOLFSSL_X509_NAME* name, WOLFSSL_X509_OBJECT* obj)
+{
+    (void)ctx;
+    (void)idx;
+    (void)name;
+    (void)obj;
+    return 0;
+}
+
+
+WOLFSSL_X509_STORE_CTX* wolfSSL_X509_STORE_CTX_new(void)
+{
+    WOLFSSL_X509_STORE_CTX* ctx = (WOLFSSL_X509_STORE_CTX*)XMALLOC(
+                                    sizeof(WOLFSSL_X509_STORE_CTX), NULL, 0);
+
+    if (ctx != NULL)
+        wolfSSL_X509_STORE_CTX_init(ctx, NULL, NULL, NULL);
+
+    return ctx;
+}
+
+
+int wolfSSL_X509_STORE_CTX_init(WOLFSSL_X509_STORE_CTX* ctx,
+     WOLFSSL_X509_STORE* store, WOLFSSL_X509* x509, STACK_OF(WOLFSSL_X509)* sk)
+{
+    (void)sk;
+    if (ctx != NULL) {
+        ctx->store = store;
+        ctx->current_cert = x509;
+        ctx->domain = NULL;
+        ctx->ex_data = NULL;
+        ctx->userCtx = NULL;
+        ctx->error = 0;
+        ctx->error_depth = 0;
+        ctx->discardSessionCerts = 0;
+        return SSL_SUCCESS;
+    }
+    return SSL_FATAL_ERROR;
+}
+
+
+void wolfSSL_X509_STORE_CTX_free(WOLFSSL_X509_STORE_CTX* ctx)
+{
+    if (ctx != NULL) {
+        if (ctx->store != NULL)
+            wolfSSL_X509_STORE_free(ctx->store);
+        if (ctx->current_cert != NULL)
+            wolfSSL_FreeX509(ctx->current_cert);
+        XFREE(ctx, NULL, 0);
+    }
+}
+
+
+void wolfSSL_X509_STORE_CTX_cleanup(WOLFSSL_X509_STORE_CTX* ctx)
+{
+    (void)ctx;
+}
+
+
+int wolfSSL_X509_verify_cert(WOLFSSL_X509_STORE_CTX* ctx)
+{
+    if (ctx != NULL && ctx->store != NULL && ctx->store->cm != NULL
+                                             && ctx->current_cert != NULL) {
+        return wolfSSL_CertManagerVerifyBuffer(ctx->store->cm,
+                    ctx->current_cert->derCert.buffer,
+                    ctx->current_cert->derCert.length,
+                    SSL_FILETYPE_ASN1);
+    }
+    return SSL_FATAL_ERROR;
+}
+
+
+WOLFSSL_ASN1_TIME* wolfSSL_X509_CRL_get_lastUpdate(WOLFSSL_X509_CRL* crl)
+{
+    (void)crl;
+    return 0;
+}
+
+
+WOLFSSL_ASN1_TIME* wolfSSL_X509_CRL_get_nextUpdate(WOLFSSL_X509_CRL* crl)
+{
+    (void)crl;
+    return 0;
+}
+
+
+
+WOLFSSL_EVP_PKEY* wolfSSL_X509_get_pubkey(WOLFSSL_X509* x509)
+{
+    WOLFSSL_EVP_PKEY* key = NULL;
+    if (x509 != NULL) {
+        key = (WOLFSSL_EVP_PKEY*)XMALLOC(
+                    sizeof(WOLFSSL_EVP_PKEY), NULL, DYNAMIC_TYPE_PUBLIC_KEY);
+        if (key != NULL) {
+            key->type = x509->pubKeyOID;
+            key->save_type = 0;
+            key->pkey.ptr = (char*)XMALLOC(
+                        x509->pubKey.length, NULL, DYNAMIC_TYPE_PUBLIC_KEY);
+            if (key->pkey.ptr == NULL) {
+                XFREE(key, NULL, DYNAMIC_TYPE_PUBLIC_KEY);
+                return NULL;
+            }
+            XMEMCPY(key->pkey.ptr,
+                                  x509->pubKey.buffer, x509->pubKey.length);
+            key->pkey_sz = x509->pubKey.length;
+            #ifdef HAVE_ECC
+                key->pkey_curve = (int)x509->pkCurveOID;
+            #endif /* HAVE_ECC */
+        }
+    }
+    return key;
+}
+
+
+int wolfSSL_X509_CRL_verify(WOLFSSL_X509_CRL* crl, WOLFSSL_EVP_PKEY* key)
+{
+    (void)crl;
+    (void)key;
+    return 0;
+}
+
+
+void wolfSSL_X509_STORE_CTX_set_error(WOLFSSL_X509_STORE_CTX* ctx, int err)
+{
+    (void)ctx;
+    (void)err;
+}
+
+
+void wolfSSL_X509_OBJECT_free_contents(WOLFSSL_X509_OBJECT* obj)
+{
+    (void)obj;
+}
+
+
+void wolfSSL_EVP_PKEY_free(WOLFSSL_EVP_PKEY* key)
+{
+    if (key != NULL) {
+        if (key->pkey.ptr != NULL)
+            XFREE(key->pkey.ptr, NULL, 0);
+        XFREE(key, NULL, 0);
+    }
+}
+
+
+int wolfSSL_X509_cmp_current_time(const WOLFSSL_ASN1_TIME* asnTime)
+{
+    (void)asnTime;
+    return 0;
+}
+
+
+int wolfSSL_sk_X509_REVOKED_num(WOLFSSL_X509_REVOKED* revoked)
+{
+    (void)revoked;
+    return 0;
+}
+
+
+
+WOLFSSL_X509_REVOKED* wolfSSL_X509_CRL_get_REVOKED(WOLFSSL_X509_CRL* crl)
+{
+    (void)crl;
+    return 0;
+}
+
+
+WOLFSSL_X509_REVOKED* wolfSSL_sk_X509_REVOKED_value(
+                                    WOLFSSL_X509_REVOKED* revoked, int value)
+{
+    (void)revoked;
+    (void)value;
+    return 0;
+}
+
+
+
+WOLFSSL_ASN1_INTEGER* wolfSSL_X509_get_serialNumber(WOLFSSL_X509* x509)
+{
+    (void)x509;
+    return 0;
+}
+
+
+int wolfSSL_ASN1_TIME_print(WOLFSSL_BIO* bio, const WOLFSSL_ASN1_TIME* asnTime)
+{
+    (void)bio;
+    (void)asnTime;
+    return 0;
+}
+
+
+
+int wolfSSL_ASN1_INTEGER_cmp(const WOLFSSL_ASN1_INTEGER* a,
+                            const WOLFSSL_ASN1_INTEGER* b)
+{
+    (void)a;
+    (void)b;
+    return 0;
+}
+
+
+long wolfSSL_ASN1_INTEGER_get(const WOLFSSL_ASN1_INTEGER* i)
+{
+    (void)i;
+    return 0;
+}
+
+
+
+void* wolfSSL_X509_STORE_CTX_get_ex_data(WOLFSSL_X509_STORE_CTX* ctx, int idx)
+{
+#ifdef FORTRESS
+    if (ctx != NULL && idx == 0)
+        return ctx->ex_data;
+#else
+    (void)ctx;
+    (void)idx;
+#endif
+    return 0;
+}
+
+
+int wolfSSL_get_ex_data_X509_STORE_CTX_idx(void)
+{
+    return 0;
+}
+
+
+void* wolfSSL_get_ex_data(const WOLFSSL* ssl, int idx)
+{
+#ifdef FORTRESS
+    if (ssl != NULL && idx < MAX_EX_DATA)
+        return ssl->ex_data[idx];
+#else
+    (void)ssl;
+    (void)idx;
+#endif
+    return 0;
+}
+
+
+void wolfSSL_CTX_set_info_callback(WOLFSSL_CTX* ctx, void (*f)(void))
+{
+    (void)ctx;
+    (void)f;
+}
+
+
+unsigned long wolfSSL_ERR_peek_error(void)
+{
+    return 0;
+}
+
+
+int wolfSSL_ERR_GET_REASON(int err)
+{
+    (void)err;
+    return 0;
+}
+
+
+char* wolfSSL_alert_type_string_long(int alertID)
+{
+    (void)alertID;
+    return 0;
+}
+
+
+char* wolfSSL_alert_desc_string_long(int alertID)
+{
+    (void)alertID;
+    return 0;
+}
+
+
+char* wolfSSL_state_string_long(WOLFSSL* ssl)
+{
+    (void)ssl;
+    return 0;
+}
+
+
+int wolfSSL_PEM_def_callback(char* name, int num, int w, void* key)
+{
+    (void)name;
+    (void)num;
+    (void)w;
+    (void)key;
+    return 0;
+}
+
+
+long wolfSSL_CTX_sess_accept(WOLFSSL_CTX* ctx)
+{
+    (void)ctx;
+    return 0;
+}
+
+
+long wolfSSL_CTX_sess_connect(WOLFSSL_CTX* ctx)
+{
+    (void)ctx;
+    return 0;
+}
+
+
+long wolfSSL_CTX_sess_accept_good(WOLFSSL_CTX* ctx)
+{
+    (void)ctx;
+    return 0;
+}
+
+
+long wolfSSL_CTX_sess_connect_good(WOLFSSL_CTX* ctx)
+{
+    (void)ctx;
+    return 0;
+}
+
+
+long wolfSSL_CTX_sess_accept_renegotiate(WOLFSSL_CTX* ctx)
+{
+    (void)ctx;
+    return 0;
+}
+
+
+long wolfSSL_CTX_sess_connect_renegotiate(WOLFSSL_CTX* ctx)
+{
+    (void)ctx;
+    return 0;
+}
+
+
+long wolfSSL_CTX_sess_hits(WOLFSSL_CTX* ctx)
+{
+    (void)ctx;
+    return 0;
+}
+
+
+long wolfSSL_CTX_sess_cb_hits(WOLFSSL_CTX* ctx)
+{
+    (void)ctx;
+    return 0;
+}
+
+
+long wolfSSL_CTX_sess_cache_full(WOLFSSL_CTX* ctx)
+{
+    (void)ctx;
+    return 0;
+}
+
+
+long wolfSSL_CTX_sess_misses(WOLFSSL_CTX* ctx)
+{
+    (void)ctx;
+    return 0;
+}
+
+
+long wolfSSL_CTX_sess_timeouts(WOLFSSL_CTX* ctx)
+{
+    (void)ctx;
+    return 0;
+}
+
+
+long wolfSSL_CTX_sess_number(WOLFSSL_CTX* ctx)
+{
+    (void)ctx;
+    return 0;
+}
+
+#ifndef NO_DES3
+
+void wolfSSL_DES_set_key_unchecked(WOLFSSL_const_DES_cblock* myDes,
+                                               WOLFSSL_DES_key_schedule* key)
+{
+    (void)myDes;
+    (void)key;
+}
+
+
+void wolfSSL_DES_set_odd_parity(WOLFSSL_DES_cblock* myDes)
+{
+    (void)myDes;
+}
+
+
+void wolfSSL_DES_ecb_encrypt(WOLFSSL_DES_cblock* desa,
+             WOLFSSL_DES_cblock* desb, WOLFSSL_DES_key_schedule* key, int len)
+{
+    (void)desa;
+    (void)desb;
+    (void)key;
+    (void)len;
+}
+
+#endif /* NO_DES3 */
+
+int wolfSSL_BIO_printf(WOLFSSL_BIO* bio, const char* format, ...)
+{
+    (void)bio;
+    (void)format;
+    return 0;
+}
+
+
+int wolfSSL_ASN1_UTCTIME_print(WOLFSSL_BIO* bio, const WOLFSSL_ASN1_UTCTIME* a)
+{
+    (void)bio;
+    (void)a;
+    return 0;
+}
+
+
+int  wolfSSL_sk_num(WOLFSSL_X509_REVOKED* rev)
+{
+    (void)rev;
+    return 0;
+}
+
+
+void* wolfSSL_sk_value(WOLFSSL_X509_REVOKED* rev, int i)
+{
+    (void)rev;
+    (void)i;
+    return 0;
+}
+
+
+/* stunnel 4.28 needs */
+void* wolfSSL_CTX_get_ex_data(const WOLFSSL_CTX* ctx, int d)
+{
+    (void)ctx;
+    (void)d;
+    return 0;
+}
+
+
+int wolfSSL_CTX_set_ex_data(WOLFSSL_CTX* ctx, int d, void* p)
+{
+    (void)ctx;
+    (void)d;
+    (void)p;
+    return SSL_SUCCESS;
+}
+
+
+void wolfSSL_CTX_sess_set_get_cb(WOLFSSL_CTX* ctx,
+                    WOLFSSL_SESSION*(*f)(WOLFSSL*, unsigned char*, int, int*))
+{
+    (void)ctx;
+    (void)f;
+}
+
+
+void wolfSSL_CTX_sess_set_new_cb(WOLFSSL_CTX* ctx,
+                             int (*f)(WOLFSSL*, WOLFSSL_SESSION*))
+{
+    (void)ctx;
+    (void)f;
+}
+
+
+void wolfSSL_CTX_sess_set_remove_cb(WOLFSSL_CTX* ctx, void (*f)(WOLFSSL_CTX*,
+                                                        WOLFSSL_SESSION*))
+{
+    (void)ctx;
+    (void)f;
+}
+
+
+int wolfSSL_i2d_SSL_SESSION(WOLFSSL_SESSION* sess, unsigned char** p)
+{
+    (void)sess;
+    (void)p;
+    return sizeof(WOLFSSL_SESSION);
+}
+
+
+WOLFSSL_SESSION* wolfSSL_d2i_SSL_SESSION(WOLFSSL_SESSION** sess,
+                                const unsigned char** p, long i)
+{
+    (void)p;
+    (void)i;
+    if (sess)
+        return *sess;
+    return NULL;
+}
+
+
+long wolfSSL_SESSION_get_timeout(const WOLFSSL_SESSION* sess)
+{
+    WOLFSSL_ENTER("wolfSSL_SESSION_get_timeout");
+    return sess->timeout;
+}
+
+
+long wolfSSL_SESSION_get_time(const WOLFSSL_SESSION* sess)
+{
+    WOLFSSL_ENTER("wolfSSL_SESSION_get_time");
+    return sess->bornOn;
+}
+
+
+int wolfSSL_CTX_get_ex_new_index(long idx, void* arg, void* a, void* b,
+                                void* c)
+{
+    (void)idx;
+    (void)arg;
+    (void)a;
+    (void)b;
+    (void)c;
+    return 0;
+}
+
+#endif /* OPENSSL_EXTRA */
+
+
+#ifdef KEEP_PEER_CERT
+char*  wolfSSL_X509_get_subjectCN(WOLFSSL_X509* x509)
+{
+    if (x509 == NULL)
+        return NULL;
+
+    return x509->subjectCN;
+}
+#endif /* KEEP_PEER_CERT */
+
+#ifdef OPENSSL_EXTRA
+
+#ifdef FORTRESS
+int wolfSSL_cmp_peer_cert_to_file(WOLFSSL* ssl, const char *fname)
+{
+    int ret = SSL_FATAL_ERROR;
+
+    WOLFSSL_ENTER("wolfSSL_cmp_peer_cert_to_file");
+    if (ssl != NULL && fname != NULL)
+    {
+    #ifdef WOLFSSL_SMALL_STACK
+        EncryptedInfo* info = NULL;
+        byte           staticBuffer[1]; /* force heap usage */
+    #else
+        EncryptedInfo  info[1];
+        byte           staticBuffer[FILE_BUFFER_SIZE];
+    #endif
+        byte*          myBuffer  = staticBuffer;
+        int            dynamic   = 0;
+        XFILE          file      = XBADFILE;
+        long           sz        = 0;
+        int            eccKey    = 0;
+        WOLFSSL_CTX*    ctx       = ssl->ctx;
+        WOLFSSL_X509*   peer_cert = &ssl->peerCert;
+        buffer         fileDer;
+
+        file = XFOPEN(fname, "rb");
+        if (file == XBADFILE)
+            return SSL_BAD_FILE;
+
+        XFSEEK(file, 0, XSEEK_END);
+        sz = XFTELL(file);
+        XREWIND(file);
+
+        if (sz > (long)sizeof(staticBuffer)) {
+            WOLFSSL_MSG("Getting dynamic buffer");
+            myBuffer = (byte*)XMALLOC(sz, ctx->heap, DYNAMIC_TYPE_FILE);
+            dynamic = 1;
+        }
+
+    #ifdef WOLFSSL_SMALL_STACK
+        info = (EncryptedInfo*)XMALLOC(sizeof(EncryptedInfo), NULL,
+                                                   DYNAMIC_TYPE_TMP_BUFFER);
+        if (info == NULL)
+            ret = MEMORY_E;
+        else
+    #endif
+        {
+            info->set = 0;
+            info->ctx = ctx;
+            info->consumed = 0;
+            fileDer.buffer = 0;
+
+            if ((myBuffer != NULL) &&
+                (sz > 0) &&
+                (XFREAD(myBuffer, sz, 1, file) > 0) &&
+                (PemToDer(myBuffer, sz, CERT_TYPE,
+                          &fileDer, ctx->heap, info, &eccKey) == 0) &&
+                (fileDer.length != 0) &&
+                (fileDer.length == peer_cert->derCert.length) &&
+                (XMEMCMP(peer_cert->derCert.buffer, fileDer.buffer,
+                                                    fileDer.length) == 0))
+            {
+                ret = 0;
+            }
+
+        #ifdef WOLFSSL_SMALL_STACK
+            XFREE(info, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        #endif
+        }
+
+        XFREE(fileDer.buffer, ctx->heap, DYNAMIC_TYPE_CERT);
+        if (dynamic)
+            XFREE(myBuffer, ctx->heap, DYNAMIC_TYPE_FILE);
+
+        XFCLOSE(file);
+    }
+
+    return ret;
+}
+#endif
+
+
+static RNG globalRNG;
+static int initGlobalRNG = 0;
+
+/* SSL_SUCCESS on ok */
+int wolfSSL_RAND_seed(const void* seed, int len)
+{
+
+    WOLFSSL_MSG("wolfSSL_RAND_seed");
+
+    (void)seed;
+    (void)len;
+
+    if (initGlobalRNG == 0) {
+        if (wc_InitRng(&globalRNG) < 0) {
+            WOLFSSL_MSG("wolfSSL Init Global RNG failed");
+            return 0;
+        }
+        initGlobalRNG = 1;
+    }
+
+    return SSL_SUCCESS;
+}
+
+
+/* SSL_SUCCESS on ok */
+int wolfSSL_RAND_bytes(unsigned char* buf, int num)
+{
+    int    ret = 0;
+    int    initTmpRng = 0;
+    RNG*   rng = NULL;
+#ifdef WOLFSSL_SMALL_STACK
+    RNG*   tmpRNG = NULL;
+#else
+    RNG    tmpRNG[1];
+#endif
+
+    WOLFSSL_ENTER("RAND_bytes");
+
+#ifdef WOLFSSL_SMALL_STACK
+    tmpRNG = (RNG*)XMALLOC(sizeof(RNG), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (tmpRNG == NULL)
+        return ret;
+#endif
+
+    if (wc_InitRng(tmpRNG) == 0) {
+        rng = tmpRNG;
+        initTmpRng = 1;
+    }
+    else if (initGlobalRNG)
+        rng = &globalRNG;
+
+    if (rng) {
+        if (wc_RNG_GenerateBlock(rng, buf, num) != 0)
+            WOLFSSL_MSG("Bad wc_RNG_GenerateBlock");
+        else
+            ret = SSL_SUCCESS;
+    }
+
+    if (initTmpRng)
+        wc_FreeRng(tmpRNG);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(tmpRNG, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+WOLFSSL_BN_CTX* wolfSSL_BN_CTX_new(void)
+{
+    static int ctx;  /* wolfcrypt doesn't now need ctx */
+
+    WOLFSSL_MSG("wolfSSL_BN_CTX_new");
+
+    return (WOLFSSL_BN_CTX*)&ctx;
+}
+
+void wolfSSL_BN_CTX_init(WOLFSSL_BN_CTX* ctx)
+{
+    (void)ctx;
+    WOLFSSL_MSG("wolfSSL_BN_CTX_init");
+}
+
+
+void wolfSSL_BN_CTX_free(WOLFSSL_BN_CTX* ctx)
+{
+    (void)ctx;
+    WOLFSSL_MSG("wolfSSL_BN_CTX_free");
+
+    /* do free since static ctx that does nothing */
+}
+
+
+static void InitwolfSSL_BigNum(WOLFSSL_BIGNUM* bn)
+{
+    WOLFSSL_MSG("InitwolfSSL_BigNum");
+    if (bn) {
+        bn->neg      = 0;
+        bn->internal = NULL;
+    }
+}
+
+
+WOLFSSL_BIGNUM* wolfSSL_BN_new(void)
+{
+    WOLFSSL_BIGNUM* external;
+    mp_int*        mpi;
+
+    WOLFSSL_MSG("wolfSSL_BN_new");
+
+    mpi = (mp_int*) XMALLOC(sizeof(mp_int), NULL, DYNAMIC_TYPE_BIGINT);
+    if (mpi == NULL) {
+        WOLFSSL_MSG("wolfSSL_BN_new malloc mpi failure");
+        return NULL;
+    }
+
+    external = (WOLFSSL_BIGNUM*) XMALLOC(sizeof(WOLFSSL_BIGNUM), NULL,
+                                        DYNAMIC_TYPE_BIGINT);
+    if (external == NULL) {
+        WOLFSSL_MSG("wolfSSL_BN_new malloc WOLFSSL_BIGNUM failure");
+        XFREE(mpi, NULL, DYNAMIC_TYPE_BIGINT);
+        return NULL;
+    }
+
+    InitwolfSSL_BigNum(external);
+    external->internal = mpi;
+    if (mp_init(mpi) != MP_OKAY) {
+        wolfSSL_BN_free(external);
+        return NULL;
+    }
+
+    return external;
+}
+
+
+void wolfSSL_BN_free(WOLFSSL_BIGNUM* bn)
+{
+    WOLFSSL_MSG("wolfSSL_BN_free");
+    if (bn) {
+        if (bn->internal) {
+            mp_clear((mp_int*)bn->internal);
+            XFREE(bn->internal, NULL, DYNAMIC_TYPE_BIGINT);
+            bn->internal = NULL;
+        }
+        XFREE(bn, NULL, DYNAMIC_TYPE_BIGINT);
+    }
+}
+
+
+void wolfSSL_BN_clear_free(WOLFSSL_BIGNUM* bn)
+{
+    WOLFSSL_MSG("wolfSSL_BN_clear_free");
+
+    wolfSSL_BN_free(bn);
+}
+
+
+/* SSL_SUCCESS on ok */
+int wolfSSL_BN_sub(WOLFSSL_BIGNUM* r, const WOLFSSL_BIGNUM* a,
+                  const WOLFSSL_BIGNUM* b)
+{
+    WOLFSSL_MSG("wolfSSL_BN_sub");
+
+    if (r == NULL || a == NULL || b == NULL)
+        return 0;
+
+    if (mp_sub((mp_int*)a->internal,(mp_int*)b->internal,
+               (mp_int*)r->internal) == MP_OKAY)
+        return SSL_SUCCESS;
+
+    WOLFSSL_MSG("wolfSSL_BN_sub mp_sub failed");
+    return 0;
+}
+
+
+/* SSL_SUCCESS on ok */
+int wolfSSL_BN_mod(WOLFSSL_BIGNUM* r, const WOLFSSL_BIGNUM* a,
+                  const WOLFSSL_BIGNUM* b, const WOLFSSL_BN_CTX* c)
+{
+    (void)c;
+    WOLFSSL_MSG("wolfSSL_BN_mod");
+
+    if (r == NULL || a == NULL || b == NULL)
+        return 0;
+
+    if (mp_mod((mp_int*)a->internal,(mp_int*)b->internal,
+               (mp_int*)r->internal) == MP_OKAY)
+        return SSL_SUCCESS;
+
+    WOLFSSL_MSG("wolfSSL_BN_mod mp_mod failed");
+    return 0;
+}
+
+
+const WOLFSSL_BIGNUM* wolfSSL_BN_value_one(void)
+{
+    static WOLFSSL_BIGNUM* bn_one = NULL;
+
+    WOLFSSL_MSG("wolfSSL_BN_value_one");
+
+    if (bn_one == NULL) {
+        bn_one = wolfSSL_BN_new();
+        if (bn_one)
+            mp_set_int((mp_int*)bn_one->internal, 1);
+    }
+
+    return bn_one;
+}
+
+
+int wolfSSL_BN_num_bytes(const WOLFSSL_BIGNUM* bn)
+{
+    WOLFSSL_MSG("wolfSSL_BN_num_bytes");
+
+    if (bn == NULL || bn->internal == NULL)
+        return 0;
+
+    return mp_unsigned_bin_size((mp_int*)bn->internal);
+}
+
+
+int wolfSSL_BN_num_bits(const WOLFSSL_BIGNUM* bn)
+{
+    WOLFSSL_MSG("wolfSSL_BN_num_bits");
+
+    if (bn == NULL || bn->internal == NULL)
+        return 0;
+
+    return mp_count_bits((mp_int*)bn->internal);
+}
+
+
+int wolfSSL_BN_is_zero(const WOLFSSL_BIGNUM* bn)
+{
+    WOLFSSL_MSG("wolfSSL_BN_is_zero");
+
+    if (bn == NULL || bn->internal == NULL)
+        return 0;
+
+    return mp_iszero((mp_int*)bn->internal);
+}
+
+
+int wolfSSL_BN_is_one(const WOLFSSL_BIGNUM* bn)
+{
+    WOLFSSL_MSG("wolfSSL_BN_is_one");
+
+    if (bn == NULL || bn->internal == NULL)
+        return 0;
+
+    if (mp_cmp_d((mp_int*)bn->internal, 1) == 0)
+        return 1;
+
+    return 0;
+}
+
+
+int wolfSSL_BN_is_odd(const WOLFSSL_BIGNUM* bn)
+{
+    WOLFSSL_MSG("wolfSSL_BN_is_odd");
+
+    if (bn == NULL || bn->internal == NULL)
+        return 0;
+
+    return mp_isodd((mp_int*)bn->internal);
+}
+
+
+int wolfSSL_BN_cmp(const WOLFSSL_BIGNUM* a, const WOLFSSL_BIGNUM* b)
+{
+    WOLFSSL_MSG("wolfSSL_BN_cmp");
+
+    if (a == NULL || a->internal == NULL || b == NULL || b->internal ==NULL)
+        return 0;
+
+    return mp_cmp((mp_int*)a->internal, (mp_int*)b->internal);
+}
+
+
+int wolfSSL_BN_bn2bin(const WOLFSSL_BIGNUM* bn, unsigned char* r)
+{
+    WOLFSSL_MSG("wolfSSL_BN_bn2bin");
+
+    if (bn == NULL || bn->internal == NULL) {
+        WOLFSSL_MSG("NULL bn error");
+        return SSL_FATAL_ERROR;
+    }
+
+    if (r == NULL)
+        return mp_unsigned_bin_size((mp_int*)bn->internal);
+
+    if (mp_to_unsigned_bin((mp_int*)bn->internal, r) != MP_OKAY) {
+        WOLFSSL_MSG("mp_to_unsigned_bin error");
+        return SSL_FATAL_ERROR;
+    }
+
+    return mp_unsigned_bin_size((mp_int*)bn->internal);
+}
+
+
+WOLFSSL_BIGNUM* wolfSSL_BN_bin2bn(const unsigned char* str, int len,
+                            WOLFSSL_BIGNUM* ret)
+{
+    WOLFSSL_MSG("wolfSSL_BN_bin2bn");
+
+    if (ret && ret->internal) {
+        if (mp_read_unsigned_bin((mp_int*)ret->internal, str, len) != 0) {
+            WOLFSSL_MSG("mp_read_unsigned_bin failure");
+            return NULL;
+        }
+    }
+    else {
+        WOLFSSL_MSG("wolfSSL_BN_bin2bn wants return bignum");
+    }
+
+    return ret;
+}
+
+
+int wolfSSL_mask_bits(WOLFSSL_BIGNUM* bn, int n)
+{
+    (void)bn;
+    (void)n;
+    WOLFSSL_MSG("wolfSSL_BN_mask_bits");
+
+    return SSL_FATAL_ERROR;
+}
+
+
+/* SSL_SUCCESS on ok */
+int wolfSSL_BN_rand(WOLFSSL_BIGNUM* bn, int bits, int top, int bottom)
+{
+    int           ret    = 0;
+    int           len    = bits / 8;
+    int           initTmpRng = 0;
+    RNG*          rng    = NULL;
+#ifdef WOLFSSL_SMALL_STACK
+    RNG*          tmpRNG = NULL;
+    byte*         buff   = NULL;
+#else
+    RNG           tmpRNG[1];
+    byte          buff[1024];
+#endif
+
+    (void)top;
+    (void)bottom;
+    WOLFSSL_MSG("wolfSSL_BN_rand");
+
+    if (bits % 8)
+        len++;
+
+#ifdef WOLFSSL_SMALL_STACK
+    buff   = (byte*)XMALLOC(1024,        NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    tmpRNG = (RNG*) XMALLOC(sizeof(RNG), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (buff == NULL || tmpRNG == NULL) {
+        XFREE(buff,   NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(tmpRNG, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        return ret;
+    }
+#endif
+
+    if (bn == NULL || bn->internal == NULL)
+        WOLFSSL_MSG("Bad function arguments");
+    else if (wc_InitRng(tmpRNG) == 0) {
+        rng = tmpRNG;
+        initTmpRng = 1;
+    }
+    else if (initGlobalRNG)
+        rng = &globalRNG;
+
+    if (rng) {
+        if (wc_RNG_GenerateBlock(rng, buff, len) != 0)
+            WOLFSSL_MSG("Bad wc_RNG_GenerateBlock");
+        else {
+            buff[0]     |= 0x80 | 0x40;
+            buff[len-1] |= 0x01;
+
+            if (mp_read_unsigned_bin((mp_int*)bn->internal,buff,len) != MP_OKAY)
+                WOLFSSL_MSG("mp read bin failed");
+            else
+                ret = SSL_SUCCESS;
+        }
+    }
+
+    if (initTmpRng)
+        wc_FreeRng(tmpRNG);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(buff,   NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(tmpRNG, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+
+int wolfSSL_BN_is_bit_set(const WOLFSSL_BIGNUM* bn, int n)
+{
+    (void)bn;
+    (void)n;
+
+    WOLFSSL_MSG("wolfSSL_BN_is_bit_set");
+
+    return 0;
+}
+
+
+/* SSL_SUCCESS on ok */
+int wolfSSL_BN_hex2bn(WOLFSSL_BIGNUM** bn, const char* str)
+{
+    int     ret     = 0;
+    word32  decSz   = 1024;
+#ifdef WOLFSSL_SMALL_STACK
+    byte*   decoded = NULL;
+#else
+    byte    decoded[1024];
+#endif
+
+    WOLFSSL_MSG("wolfSSL_BN_hex2bn");
+
+#ifdef WOLFSSL_SMALL_STACK
+    decoded = (byte*)XMALLOC(decSz, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (decoded == NULL)
+        return ret;
+#endif
+
+    if (str == NULL)
+        WOLFSSL_MSG("Bad function argument");
+    else if (Base16_Decode((byte*)str, (int)XSTRLEN(str), decoded, &decSz) < 0)
+        WOLFSSL_MSG("Bad Base16_Decode error");
+    else if (bn == NULL)
+        ret = decSz;
+    else {
+        if (*bn == NULL)
+            *bn = wolfSSL_BN_new();
+
+        if (*bn == NULL)
+            WOLFSSL_MSG("BN new failed");
+        else if (wolfSSL_BN_bin2bn(decoded, decSz, *bn) == NULL)
+            WOLFSSL_MSG("Bad bin2bn error");
+        else
+            ret = SSL_SUCCESS;
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(decoded, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+
+WOLFSSL_BIGNUM* wolfSSL_BN_dup(const WOLFSSL_BIGNUM* bn)
+{
+    WOLFSSL_BIGNUM* ret;
+
+    WOLFSSL_MSG("wolfSSL_BN_dup");
+
+    if (bn == NULL || bn->internal == NULL) {
+        WOLFSSL_MSG("bn NULL error");
+        return NULL;
+    }
+
+    ret = wolfSSL_BN_new();
+    if (ret == NULL) {
+        WOLFSSL_MSG("bn new error");
+        return NULL;
+    }
+
+    if (mp_copy((mp_int*)bn->internal, (mp_int*)ret->internal) != MP_OKAY) {
+        WOLFSSL_MSG("mp_copy error");
+        wolfSSL_BN_free(ret);
+        return NULL;
+    }
+
+    return ret;
+}
+
+
+WOLFSSL_BIGNUM* wolfSSL_BN_copy(WOLFSSL_BIGNUM* r, const WOLFSSL_BIGNUM* bn)
+{
+    (void)r;
+    (void)bn;
+
+    WOLFSSL_MSG("wolfSSL_BN_copy");
+
+    return NULL;
+}
+
+
+int wolfSSL_BN_set_word(WOLFSSL_BIGNUM* bn, unsigned long w)
+{
+    (void)bn;
+    (void)w;
+
+    WOLFSSL_MSG("wolfSSL_BN_set_word");
+
+    return SSL_FATAL_ERROR;
+}
+
+
+int wolfSSL_BN_dec2bn(WOLFSSL_BIGNUM** bn, const char* str)
+{
+    (void)bn;
+    (void)str;
+
+    WOLFSSL_MSG("wolfSSL_BN_dec2bn");
+
+    return SSL_FATAL_ERROR;
+}
+
+
+char* wolfSSL_BN_bn2dec(const WOLFSSL_BIGNUM* bn)
+{
+    (void)bn;
+
+    WOLFSSL_MSG("wolfSSL_BN_bn2dec");
+
+    return NULL;
+}
+
+
+#ifndef NO_DH
+
+static void InitwolfSSL_DH(WOLFSSL_DH* dh)
+{
+    if (dh) {
+        dh->p        = NULL;
+        dh->g        = NULL;
+        dh->pub_key  = NULL;
+        dh->priv_key = NULL;
+        dh->internal = NULL;
+        dh->inSet    = 0;
+        dh->exSet    = 0;
+    }
+}
+
+
+WOLFSSL_DH* wolfSSL_DH_new(void)
+{
+    WOLFSSL_DH* external;
+    DhKey*     key;
+
+    WOLFSSL_MSG("wolfSSL_DH_new");
+
+    key = (DhKey*) XMALLOC(sizeof(DhKey), NULL, DYNAMIC_TYPE_DH);
+    if (key == NULL) {
+        WOLFSSL_MSG("wolfSSL_DH_new malloc DhKey failure");
+        return NULL;
+    }
+
+    external = (WOLFSSL_DH*) XMALLOC(sizeof(WOLFSSL_DH), NULL,
+                                    DYNAMIC_TYPE_DH);
+    if (external == NULL) {
+        WOLFSSL_MSG("wolfSSL_DH_new malloc WOLFSSL_DH failure");
+        XFREE(key, NULL, DYNAMIC_TYPE_DH);
+        return NULL;
+    }
+
+    InitwolfSSL_DH(external);
+    wc_InitDhKey(key);
+    external->internal = key;
+
+    return external;
+}
+
+
+void wolfSSL_DH_free(WOLFSSL_DH* dh)
+{
+    WOLFSSL_MSG("wolfSSL_DH_free");
+
+    if (dh) {
+        if (dh->internal) {
+            wc_FreeDhKey((DhKey*)dh->internal);
+            XFREE(dh->internal, NULL, DYNAMIC_TYPE_DH);
+            dh->internal = NULL;
+        }
+        wolfSSL_BN_free(dh->priv_key);
+        wolfSSL_BN_free(dh->pub_key);
+        wolfSSL_BN_free(dh->g);
+        wolfSSL_BN_free(dh->p);
+        InitwolfSSL_DH(dh);  /* set back to NULLs for safety */
+
+        XFREE(dh, NULL, DYNAMIC_TYPE_DH);
+    }
+}
+
+
+static int SetDhInternal(WOLFSSL_DH* dh)
+{
+    int            ret = SSL_FATAL_ERROR;
+    int            pSz = 1024;
+    int            gSz = 1024;
+#ifdef WOLFSSL_SMALL_STACK
+    unsigned char* p   = NULL;
+    unsigned char* g   = NULL;
+#else
+    unsigned char  p[1024];
+    unsigned char  g[1024];
+#endif
+
+    WOLFSSL_ENTER("SetDhInternal");
+
+    if (dh == NULL || dh->p == NULL || dh->g == NULL)
+        WOLFSSL_MSG("Bad function arguments");
+    else if (wolfSSL_BN_bn2bin(dh->p, NULL) > pSz)
+        WOLFSSL_MSG("Bad p internal size");
+    else if (wolfSSL_BN_bn2bin(dh->g, NULL) > gSz)
+        WOLFSSL_MSG("Bad g internal size");
+    else {
+    #ifdef WOLFSSL_SMALL_STACK
+        p = (unsigned char*)XMALLOC(pSz, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        g = (unsigned char*)XMALLOC(gSz, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+
+        if (p == NULL || g == NULL) {
+            XFREE(p, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            XFREE(g, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            return ret;
+        }
+    #endif
+
+        pSz = wolfSSL_BN_bn2bin(dh->p, p);
+        gSz = wolfSSL_BN_bn2bin(dh->g, g);
+
+        if (pSz <= 0 || gSz <= 0)
+            WOLFSSL_MSG("Bad BN2bin set");
+        else if (wc_DhSetKey((DhKey*)dh->internal, p, pSz, g, gSz) < 0)
+            WOLFSSL_MSG("Bad DH SetKey");
+        else {
+            dh->inSet = 1;
+            ret = 0;
+        }
+
+    #ifdef WOLFSSL_SMALL_STACK
+        XFREE(p, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(g, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    #endif
+    }
+
+
+    return ret;
+}
+
+
+int wolfSSL_DH_size(WOLFSSL_DH* dh)
+{
+    WOLFSSL_MSG("wolfSSL_DH_size");
+
+    if (dh == NULL)
+        return 0;
+
+    return wolfSSL_BN_num_bytes(dh->p);
+}
+
+
+/* return SSL_SUCCESS on ok, else 0 */
+int wolfSSL_DH_generate_key(WOLFSSL_DH* dh)
+{
+    int            ret    = 0;
+    word32         pubSz  = 768;
+    word32         privSz = 768;
+    int            initTmpRng = 0;
+    RNG*           rng    = NULL;
+#ifdef WOLFSSL_SMALL_STACK
+    unsigned char* pub    = NULL;
+    unsigned char* priv   = NULL;
+    RNG*           tmpRNG = NULL;
+#else
+    unsigned char  pub [768];
+    unsigned char  priv[768];
+    RNG            tmpRNG[1];
+#endif
+
+    WOLFSSL_MSG("wolfSSL_DH_generate_key");
+
+#ifdef WOLFSSL_SMALL_STACK
+    tmpRNG = (RNG*)XMALLOC(sizeof(RNG),      NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    pub    = (unsigned char*)XMALLOC(pubSz,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    priv   = (unsigned char*)XMALLOC(privSz, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+
+    if (tmpRNG == NULL || pub == NULL || priv == NULL) {
+        XFREE(tmpRNG, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(pub,    NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(priv,   NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        return ret;
+    }
+#endif
+
+    if (dh == NULL || dh->p == NULL || dh->g == NULL)
+        WOLFSSL_MSG("Bad function arguments");
+    else if (dh->inSet == 0 && SetDhInternal(dh) < 0)
+            WOLFSSL_MSG("Bad DH set internal");
+    else if (wc_InitRng(tmpRNG) == 0) {
+        rng = tmpRNG;
+        initTmpRng = 1;
+    }
+    else {
+        WOLFSSL_MSG("Bad RNG Init, trying global");
+        if (initGlobalRNG == 0)
+            WOLFSSL_MSG("Global RNG no Init");
+        else
+            rng = &globalRNG;
+    }
+
+    if (rng) {
+       if (wc_DhGenerateKeyPair((DhKey*)dh->internal, rng, priv, &privSz,
+                                                               pub, &pubSz) < 0)
+            WOLFSSL_MSG("Bad wc_DhGenerateKeyPair");
+       else {
+            if (dh->pub_key)
+                wolfSSL_BN_free(dh->pub_key);
+   
+            dh->pub_key = wolfSSL_BN_new();
+            if (dh->pub_key == NULL) {
+                WOLFSSL_MSG("Bad DH new pub");
+            }
+            if (dh->priv_key)
+                wolfSSL_BN_free(dh->priv_key);
+
+            dh->priv_key = wolfSSL_BN_new();
+
+            if (dh->priv_key == NULL) {
+                WOLFSSL_MSG("Bad DH new priv");
+            }
+
+            if (dh->pub_key && dh->priv_key) {
+               if (wolfSSL_BN_bin2bn(pub, pubSz, dh->pub_key) == NULL)
+                   WOLFSSL_MSG("Bad DH bn2bin error pub");
+               else if (wolfSSL_BN_bin2bn(priv, privSz, dh->priv_key) == NULL)
+                   WOLFSSL_MSG("Bad DH bn2bin error priv");
+               else
+                   ret = SSL_SUCCESS;
+            }
+        }
+    }
+
+    if (initTmpRng)
+        wc_FreeRng(tmpRNG);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(tmpRNG, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(pub,    NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(priv,   NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+
+/* return key size on ok, 0 otherwise */
+int wolfSSL_DH_compute_key(unsigned char* key, WOLFSSL_BIGNUM* otherPub,
+                          WOLFSSL_DH* dh)
+{
+    int            ret    = 0;
+    word32         keySz  = 0;
+    word32         pubSz  = 1024;
+    word32         privSz = 1024;
+#ifdef WOLFSSL_SMALL_STACK
+    unsigned char* pub    = NULL;
+    unsigned char* priv   = NULL;
+#else
+    unsigned char  pub [1024];
+    unsigned char  priv[1024];
+#endif
+
+    WOLFSSL_MSG("wolfSSL_DH_compute_key");
+
+#ifdef WOLFSSL_SMALL_STACK
+    pub = (unsigned char*)XMALLOC(pubSz, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (pub == NULL)
+        return ret;
+
+    priv = (unsigned char*)XMALLOC(privSz, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (priv == NULL) {
+        XFREE(pub, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        return 0;
+    }
+#endif
+
+    if (dh == NULL || dh->priv_key == NULL || otherPub == NULL)
+        WOLFSSL_MSG("Bad function arguments");
+    else if ((keySz = (word32)DH_size(dh)) == 0)
+        WOLFSSL_MSG("Bad DH_size");
+    else if (wolfSSL_BN_bn2bin(dh->priv_key, NULL) > (int)privSz)
+        WOLFSSL_MSG("Bad priv internal size");
+    else if (wolfSSL_BN_bn2bin(otherPub, NULL) > (int)pubSz)
+        WOLFSSL_MSG("Bad otherPub size");
+    else {
+        privSz = wolfSSL_BN_bn2bin(dh->priv_key, priv);
+        pubSz  = wolfSSL_BN_bn2bin(otherPub, pub);
+
+        if (privSz <= 0 || pubSz <= 0)
+            WOLFSSL_MSG("Bad BN2bin set");
+        else if (wc_DhAgree((DhKey*)dh->internal, key, &keySz, priv, privSz, pub,
+                                                                     pubSz) < 0)
+            WOLFSSL_MSG("wc_DhAgree failed");
+        else
+            ret = (int)keySz;
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(pub,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(priv, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+#endif /* NO_DH */
+
+
+#ifndef NO_DSA
+static void InitwolfSSL_DSA(WOLFSSL_DSA* dsa)
+{
+    if (dsa) {
+        dsa->p        = NULL;
+        dsa->q        = NULL;
+        dsa->g        = NULL;
+        dsa->pub_key  = NULL;
+        dsa->priv_key = NULL;
+        dsa->internal = NULL;
+        dsa->inSet    = 0;
+        dsa->exSet    = 0;
+    }
+}
+
+
+WOLFSSL_DSA* wolfSSL_DSA_new(void)
+{
+    WOLFSSL_DSA* external;
+    DsaKey*     key;
+
+    WOLFSSL_MSG("wolfSSL_DSA_new");
+
+    key = (DsaKey*) XMALLOC(sizeof(DsaKey), NULL, DYNAMIC_TYPE_DSA);
+    if (key == NULL) {
+        WOLFSSL_MSG("wolfSSL_DSA_new malloc DsaKey failure");
+        return NULL;
+    }
+
+    external = (WOLFSSL_DSA*) XMALLOC(sizeof(WOLFSSL_DSA), NULL,
+                                    DYNAMIC_TYPE_DSA);
+    if (external == NULL) {
+        WOLFSSL_MSG("wolfSSL_DSA_new malloc WOLFSSL_DSA failure");
+        XFREE(key, NULL, DYNAMIC_TYPE_DSA);
+        return NULL;
+    }
+
+    InitwolfSSL_DSA(external);
+    InitDsaKey(key);
+    external->internal = key;
+
+    return external;
+}
+
+
+void wolfSSL_DSA_free(WOLFSSL_DSA* dsa)
+{
+    WOLFSSL_MSG("wolfSSL_DSA_free");
+
+    if (dsa) {
+        if (dsa->internal) {
+            FreeDsaKey((DsaKey*)dsa->internal);
+            XFREE(dsa->internal, NULL, DYNAMIC_TYPE_DSA);
+            dsa->internal = NULL;
+        }
+        wolfSSL_BN_free(dsa->priv_key);
+        wolfSSL_BN_free(dsa->pub_key);
+        wolfSSL_BN_free(dsa->g);
+        wolfSSL_BN_free(dsa->q);
+        wolfSSL_BN_free(dsa->p);
+        InitwolfSSL_DSA(dsa);  /* set back to NULLs for safety */
+
+        XFREE(dsa, NULL, DYNAMIC_TYPE_DSA);
+    }
+}
+
+
+int wolfSSL_DSA_generate_key(WOLFSSL_DSA* dsa)
+{
+    (void)dsa;
+
+    WOLFSSL_MSG("wolfSSL_DSA_generate_key");
+
+    return 0;  /* key gen not needed by server */
+}
+
+
+int wolfSSL_DSA_generate_parameters_ex(WOLFSSL_DSA* dsa, int bits,
+               unsigned char* seed, int seedLen, int* counterRet,
+               unsigned long* hRet, void* cb)
+{
+    (void)dsa;
+    (void)bits;
+    (void)seed;
+    (void)seedLen;
+    (void)counterRet;
+    (void)hRet;
+    (void)cb;
+
+    WOLFSSL_MSG("wolfSSL_DSA_generate_parameters_ex");
+
+    return 0;  /* key gen not needed by server */
+}
+#endif /* NO_DSA */
+
+#ifndef NO_RSA
+static void InitwolfSSL_Rsa(WOLFSSL_RSA* rsa)
+{
+    if (rsa) {
+        rsa->n        = NULL;
+        rsa->e        = NULL;
+        rsa->d        = NULL;
+        rsa->p        = NULL;
+        rsa->q        = NULL;
+        rsa->dmp1     = NULL;
+        rsa->dmq1     = NULL;
+        rsa->iqmp     = NULL;
+        rsa->internal = NULL;
+        rsa->inSet    = 0;
+        rsa->exSet    = 0;
+    }
+}
+
+
+WOLFSSL_RSA* wolfSSL_RSA_new(void)
+{
+    WOLFSSL_RSA* external;
+    RsaKey*     key;
+
+    WOLFSSL_MSG("wolfSSL_RSA_new");
+
+    key = (RsaKey*) XMALLOC(sizeof(RsaKey), NULL, DYNAMIC_TYPE_RSA);
+    if (key == NULL) {
+        WOLFSSL_MSG("wolfSSL_RSA_new malloc RsaKey failure");
+        return NULL;
+    }
+
+    external = (WOLFSSL_RSA*) XMALLOC(sizeof(WOLFSSL_RSA), NULL,
+                                     DYNAMIC_TYPE_RSA);
+    if (external == NULL) {
+        WOLFSSL_MSG("wolfSSL_RSA_new malloc WOLFSSL_RSA failure");
+        XFREE(key, NULL, DYNAMIC_TYPE_RSA);
+        return NULL;
+    }
+
+    InitwolfSSL_Rsa(external);
+    if (wc_InitRsaKey(key, NULL) != 0) {
+        WOLFSSL_MSG("InitRsaKey WOLFSSL_RSA failure");
+        XFREE(external, NULL, DYNAMIC_TYPE_RSA);
+        XFREE(key, NULL, DYNAMIC_TYPE_RSA);
+        return NULL;
+    }
+    external->internal = key;
+
+    return external;
+}
+
+
+void wolfSSL_RSA_free(WOLFSSL_RSA* rsa)
+{
+    WOLFSSL_MSG("wolfSSL_RSA_free");
+
+    if (rsa) {
+        if (rsa->internal) {
+            wc_FreeRsaKey((RsaKey*)rsa->internal);
+            XFREE(rsa->internal, NULL, DYNAMIC_TYPE_RSA);
+            rsa->internal = NULL;
+        }
+        wolfSSL_BN_free(rsa->iqmp);
+        wolfSSL_BN_free(rsa->dmq1);
+        wolfSSL_BN_free(rsa->dmp1);
+        wolfSSL_BN_free(rsa->q);
+        wolfSSL_BN_free(rsa->p);
+        wolfSSL_BN_free(rsa->d);
+        wolfSSL_BN_free(rsa->e);
+        wolfSSL_BN_free(rsa->n);
+        InitwolfSSL_Rsa(rsa);  /* set back to NULLs for safety */
+
+        XFREE(rsa, NULL, DYNAMIC_TYPE_RSA);
+    }
+}
+#endif /* NO_RSA */
+
+
+#if !defined(NO_RSA) || !defined(NO_DSA)
+static int SetIndividualExternal(WOLFSSL_BIGNUM** bn, mp_int* mpi)
+{
+    WOLFSSL_MSG("Entering SetIndividualExternal");
+
+    if (mpi == NULL) {
+        WOLFSSL_MSG("mpi NULL error");
+        return SSL_FATAL_ERROR;
+    }
+
+    if (*bn == NULL) {
+        *bn = wolfSSL_BN_new();
+        if (*bn == NULL) {
+            WOLFSSL_MSG("SetIndividualExternal alloc failed");
+            return SSL_FATAL_ERROR;
+        }
+    }
+
+    if (mp_copy(mpi, (mp_int*)((*bn)->internal)) != MP_OKAY) {
+        WOLFSSL_MSG("mp_copy error");
+        return SSL_FATAL_ERROR;
+    }
+
+    return 0;
+}
+#endif /* !NO_RSA && !NO_DSA */
+
+
+#ifndef NO_DSA
+static int SetDsaExternal(WOLFSSL_DSA* dsa)
+{
+    DsaKey* key;
+    WOLFSSL_MSG("Entering SetDsaExternal");
+
+    if (dsa == NULL || dsa->internal == NULL) {
+        WOLFSSL_MSG("dsa key NULL error");
+        return SSL_FATAL_ERROR;
+    }
+
+    key = (DsaKey*)dsa->internal;
+
+    if (SetIndividualExternal(&dsa->p, &key->p) < 0) {
+        WOLFSSL_MSG("dsa p key error");
+        return SSL_FATAL_ERROR;
+    }
+
+    if (SetIndividualExternal(&dsa->q, &key->q) < 0) {
+        WOLFSSL_MSG("dsa q key error");
+        return SSL_FATAL_ERROR;
+    }
+
+    if (SetIndividualExternal(&dsa->g, &key->g) < 0) {
+        WOLFSSL_MSG("dsa g key error");
+        return SSL_FATAL_ERROR;
+    }
+
+    if (SetIndividualExternal(&dsa->pub_key, &key->y) < 0) {
+        WOLFSSL_MSG("dsa y key error");
+        return SSL_FATAL_ERROR;
+    }
+
+    if (SetIndividualExternal(&dsa->priv_key, &key->x) < 0) {
+        WOLFSSL_MSG("dsa x key error");
+        return SSL_FATAL_ERROR;
+    }
+
+    dsa->exSet = 1;
+
+    return 0;
+}
+#endif /* NO_DSA */
+
+
+#ifndef NO_RSA
+static int SetRsaExternal(WOLFSSL_RSA* rsa)
+{
+    RsaKey* key;
+    WOLFSSL_MSG("Entering SetRsaExternal");
+
+    if (rsa == NULL || rsa->internal == NULL) {
+        WOLFSSL_MSG("rsa key NULL error");
+        return SSL_FATAL_ERROR;
+    }
+
+    key = (RsaKey*)rsa->internal;
+
+    if (SetIndividualExternal(&rsa->n, &key->n) < 0) {
+        WOLFSSL_MSG("rsa n key error");
+        return SSL_FATAL_ERROR;
+    }
+
+    if (SetIndividualExternal(&rsa->e, &key->e) < 0) {
+        WOLFSSL_MSG("rsa e key error");
+        return SSL_FATAL_ERROR;
+    }
+
+    if (SetIndividualExternal(&rsa->d, &key->d) < 0) {
+        WOLFSSL_MSG("rsa d key error");
+        return SSL_FATAL_ERROR;
+    }
+
+    if (SetIndividualExternal(&rsa->p, &key->p) < 0) {
+        WOLFSSL_MSG("rsa p key error");
+        return SSL_FATAL_ERROR;
+    }
+
+    if (SetIndividualExternal(&rsa->q, &key->q) < 0) {
+        WOLFSSL_MSG("rsa q key error");
+        return SSL_FATAL_ERROR;
+    }
+
+    if (SetIndividualExternal(&rsa->dmp1, &key->dP) < 0) {
+        WOLFSSL_MSG("rsa dP key error");
+        return SSL_FATAL_ERROR;
+    }
+
+    if (SetIndividualExternal(&rsa->dmq1, &key->dQ) < 0) {
+        WOLFSSL_MSG("rsa dQ key error");
+        return SSL_FATAL_ERROR;
+    }
+
+    if (SetIndividualExternal(&rsa->iqmp, &key->u) < 0) {
+        WOLFSSL_MSG("rsa u key error");
+        return SSL_FATAL_ERROR;
+    }
+
+    rsa->exSet = 1;
+
+    return 0;
+}
+
+
+/* SSL_SUCCESS on ok */
+int wolfSSL_RSA_generate_key_ex(WOLFSSL_RSA* rsa, int bits, WOLFSSL_BIGNUM* bn,
+                               void* cb)
+{
+    int ret = SSL_FATAL_ERROR;
+
+    WOLFSSL_MSG("wolfSSL_RSA_generate_key_ex");
+
+    (void)rsa;
+    (void)bits;
+    (void)cb;
+    (void)bn;
+
+#ifdef WOLFSSL_KEY_GEN
+    {
+    #ifdef WOLFSSL_SMALL_STACK
+        RNG* rng = NULL;
+    #else
+        RNG  rng[1];
+    #endif
+
+    #ifdef WOLFSSL_SMALL_STACK
+        rng = (RNG*)XMALLOC(sizeof(RNG), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (rng == NULL)
+            return SSL_FATAL_ERROR;
+    #endif
+
+        if (wc_InitRng(rng) < 0)
+            WOLFSSL_MSG("RNG init failed");
+        else if (wc_MakeRsaKey((RsaKey*)rsa->internal, bits, 65537, rng) < 0)
+            WOLFSSL_MSG("wc_MakeRsaKey failed");
+        else if (SetRsaExternal(rsa) < 0)
+            WOLFSSL_MSG("SetRsaExternal failed");
+        else {
+            rsa->inSet = 1;
+            ret = SSL_SUCCESS;
+        }
+
+        wc_FreeRng(rng);
+    #ifdef WOLFSSL_SMALL_STACK
+        XFREE(rng, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    #endif
+    }
+#else
+    WOLFSSL_MSG("No Key Gen built in");
+#endif
+    return ret;
+}
+
+
+/* SSL_SUCCESS on ok */
+int wolfSSL_RSA_blinding_on(WOLFSSL_RSA* rsa, WOLFSSL_BN_CTX* bn)
+{
+    (void)rsa;
+    (void)bn;
+
+    WOLFSSL_MSG("wolfSSL_RSA_blinding_on");
+
+    return SSL_SUCCESS;  /* on by default */
+}
+
+
+int wolfSSL_RSA_public_encrypt(int len, unsigned char* fr,
+                            unsigned char* to, WOLFSSL_RSA* rsa, int padding)
+{
+    (void)len;
+    (void)fr;
+    (void)to;
+    (void)rsa;
+    (void)padding;
+
+    WOLFSSL_MSG("wolfSSL_RSA_public_encrypt");
+
+    return SSL_FATAL_ERROR;
+}
+
+
+int wolfSSL_RSA_private_decrypt(int len, unsigned char* fr,
+                            unsigned char* to, WOLFSSL_RSA* rsa, int padding)
+{
+    (void)len;
+    (void)fr;
+    (void)to;
+    (void)rsa;
+    (void)padding;
+
+    WOLFSSL_MSG("wolfSSL_RSA_private_decrypt");
+
+    return SSL_FATAL_ERROR;
+}
+
+
+int wolfSSL_RSA_size(const WOLFSSL_RSA* rsa)
+{
+    WOLFSSL_MSG("wolfSSL_RSA_size");
+
+    if (rsa == NULL)
+        return 0;
+
+    return wolfSSL_BN_num_bytes(rsa->n);
+}
+#endif /* NO_RSA */
+
+
+#ifndef NO_DSA
+/* return SSL_SUCCESS on success, < 0 otherwise */
+int wolfSSL_DSA_do_sign(const unsigned char* d, unsigned char* sigRet,
+                       WOLFSSL_DSA* dsa)
+{
+    int    ret = SSL_FATAL_ERROR;
+    int    initTmpRng = 0;
+    RNG*   rng = NULL;
+#ifdef WOLFSSL_SMALL_STACK
+    RNG*   tmpRNG = NULL;
+#else
+    RNG    tmpRNG[1];
+#endif
+
+    WOLFSSL_MSG("wolfSSL_DSA_do_sign");
+
+    if (d == NULL || sigRet == NULL || dsa == NULL)
+        WOLFSSL_MSG("Bad function arguments");
+    else if (dsa->inSet == 0)
+        WOLFSSL_MSG("No DSA internal set");
+    else {
+    #ifdef WOLFSSL_SMALL_STACK
+        tmpRNG = (RNG*)XMALLOC(sizeof(RNG), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (tmpRNG == NULL)
+            return SSL_FATAL_ERROR;
+    #endif
+
+        if (wc_InitRng(tmpRNG) == 0) {
+            rng = tmpRNG;
+            initTmpRng = 1;
+        }
+        else {
+            WOLFSSL_MSG("Bad RNG Init, trying global");
+            if (initGlobalRNG == 0)
+                WOLFSSL_MSG("Global RNG no Init");
+            else
+                rng = &globalRNG;
+        }
+
+        if (rng) {
+            if (DsaSign(d, sigRet, (DsaKey*)dsa->internal, rng) < 0)
+                WOLFSSL_MSG("DsaSign failed");
+            else
+                ret = SSL_SUCCESS;
+        }
+
+        if (initTmpRng)
+            wc_FreeRng(tmpRNG);
+    #ifdef WOLFSSL_SMALL_STACK
+        XFREE(tmpRNG, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    #endif
+    }
+
+    return ret;
+}
+#endif /* NO_DSA */
+
+
+#ifndef NO_RSA
+/* return SSL_SUCCES on ok, 0 otherwise */
+int wolfSSL_RSA_sign(int type, const unsigned char* m,
+                           unsigned int mLen, unsigned char* sigRet,
+                           unsigned int* sigLen, WOLFSSL_RSA* rsa)
+{
+    word32 outLen;    
+    word32 signSz;
+    int    initTmpRng = 0;
+    RNG*   rng        = NULL;
+    int    ret        = 0;
+#ifdef WOLFSSL_SMALL_STACK
+    RNG*   tmpRNG     = NULL;
+    byte*  encodedSig = NULL;
+#else
+    RNG    tmpRNG[1];
+    byte   encodedSig[MAX_ENCODED_SIG_SZ];
+#endif
+
+    WOLFSSL_MSG("wolfSSL_RSA_sign");
+
+    if (m == NULL || sigRet == NULL || sigLen == NULL || rsa == NULL)
+        WOLFSSL_MSG("Bad function arguments");
+    else if (rsa->inSet == 0)
+        WOLFSSL_MSG("No RSA internal set");
+    else if (type != NID_md5 && type != NID_sha1)
+        WOLFSSL_MSG("Bad md type");
+    else {
+        outLen = (word32)wolfSSL_BN_num_bytes(rsa->n);
+
+    #ifdef WOLFSSL_SMALL_STACK
+        tmpRNG = (RNG*)XMALLOC(sizeof(RNG), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (tmpRNG == NULL)
+            return 0;
+
+        encodedSig = (byte*)XMALLOC(MAX_ENCODED_SIG_SZ, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+        if (encodedSig == NULL) {
+            XFREE(tmpRNG, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            return 0;
+        }
+    #endif
+
+        if (outLen == 0)
+            WOLFSSL_MSG("Bad RSA size");
+        else if (wc_InitRng(tmpRNG) == 0) {
+            rng = tmpRNG;
+            initTmpRng = 1;
+        }
+        else {
+            WOLFSSL_MSG("Bad RNG Init, trying global");
+
+            if (initGlobalRNG == 0)
+                WOLFSSL_MSG("Global RNG no Init");
+            else
+                rng = &globalRNG;
+        }
+    }
+
+    if (rng) {
+        type = (type == NID_md5) ? MD5h : SHAh;
+
+        signSz = wc_EncodeSignature(encodedSig, m, mLen, type);
+        if (signSz == 0) {
+            WOLFSSL_MSG("Bad Encode Signature");
+        }
+        else {
+            *sigLen = wc_RsaSSL_Sign(encodedSig, signSz, sigRet, outLen,
+                                  (RsaKey*)rsa->internal, rng);
+            if (*sigLen <= 0)
+                WOLFSSL_MSG("Bad Rsa Sign");
+            else
+                ret = SSL_SUCCESS;
+        }
+
+    }
+
+    if (initTmpRng)
+        wc_FreeRng(tmpRNG);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(tmpRNG,     NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(encodedSig, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    WOLFSSL_MSG("wolfSSL_RSA_sign success");
+    return ret;
+}
+
+
+int wolfSSL_RSA_public_decrypt(int flen, unsigned char* from,
+                          unsigned char* to, WOLFSSL_RSA* rsa, int padding)
+{
+    (void)flen;
+    (void)from;
+    (void)to;
+    (void)rsa;
+    (void)padding;
+
+    WOLFSSL_MSG("wolfSSL_RSA_public_decrypt");
+
+    return SSL_FATAL_ERROR;
+}
+
+
+/* generate p-1 and q-1, SSL_SUCCESS on ok */
+int wolfSSL_RSA_GenAdd(WOLFSSL_RSA* rsa)
+{
+    int    err;
+    mp_int tmp;
+
+    WOLFSSL_MSG("wolfSSL_RsaGenAdd");
+
+    if (rsa == NULL || rsa->p == NULL || rsa->q == NULL || rsa->d == NULL ||
+                       rsa->dmp1 == NULL || rsa->dmq1 == NULL) {
+        WOLFSSL_MSG("rsa no init error");
+        return SSL_FATAL_ERROR;
+    }
+
+    if (mp_init(&tmp) != MP_OKAY) {
+        WOLFSSL_MSG("mp_init error");
+        return SSL_FATAL_ERROR;
+    }
+
+    err = mp_sub_d((mp_int*)rsa->p->internal, 1, &tmp);
+    if (err != MP_OKAY) {
+        WOLFSSL_MSG("mp_sub_d error");
+    }
+    else
+        err = mp_mod((mp_int*)rsa->d->internal, &tmp,
+                     (mp_int*)rsa->dmp1->internal);
+
+    if (err != MP_OKAY) {
+        WOLFSSL_MSG("mp_mod error");
+    }
+    else
+        err = mp_sub_d((mp_int*)rsa->q->internal, 1, &tmp);
+    if (err != MP_OKAY) {
+        WOLFSSL_MSG("mp_sub_d error");
+    }
+    else
+        err = mp_mod((mp_int*)rsa->d->internal, &tmp,
+                     (mp_int*)rsa->dmq1->internal);
+
+    mp_clear(&tmp);
+
+    if (err == MP_OKAY)
+        return SSL_SUCCESS;
+    else
+        return SSL_FATAL_ERROR;
+}
+#endif /* NO_RSA */
+
+
+void wolfSSL_HMAC_Init(WOLFSSL_HMAC_CTX* ctx, const void* key, int keylen,
+                  const EVP_MD* type)
+{
+    WOLFSSL_MSG("wolfSSL_HMAC_Init");
+
+    if (ctx == NULL) {
+        WOLFSSL_MSG("no ctx on init");
+        return;
+    }
+
+    if (type) {
+        WOLFSSL_MSG("init has type");
+
+        if (XSTRNCMP(type, "MD5", 3) == 0) {
+            WOLFSSL_MSG("md5 hmac");
+            ctx->type = MD5;
+        }
+        else if (XSTRNCMP(type, "SHA256", 6) == 0) {
+            WOLFSSL_MSG("sha256 hmac");
+            ctx->type = SHA256;
+        }
+
+        /* has to be last since would pick or 256, 384, or 512 too */
+        else if (XSTRNCMP(type, "SHA", 3) == 0) {
+            WOLFSSL_MSG("sha hmac");
+            ctx->type = SHA;
+        }
+        else {
+            WOLFSSL_MSG("bad init type");
+        }
+    }
+
+    if (key && keylen) {
+        WOLFSSL_MSG("keying hmac");
+        wc_HmacSetKey(&ctx->hmac, ctx->type, (const byte*)key, (word32)keylen);
+        /* OpenSSL compat, no error */
+    }
+}
+
+
+void wolfSSL_HMAC_Update(WOLFSSL_HMAC_CTX* ctx, const unsigned char* data,
+                    int len)
+{
+    WOLFSSL_MSG("wolfSSL_HMAC_Update");
+
+    if (ctx && data) {
+        WOLFSSL_MSG("updating hmac");
+        wc_HmacUpdate(&ctx->hmac, data, (word32)len);
+        /* OpenSSL compat, no error */
+    }
+}
+
+
+void wolfSSL_HMAC_Final(WOLFSSL_HMAC_CTX* ctx, unsigned char* hash,
+                   unsigned int* len)
+{
+    WOLFSSL_MSG("wolfSSL_HMAC_Final");
+
+    if (ctx && hash) {
+        WOLFSSL_MSG("final hmac");
+        wc_HmacFinal(&ctx->hmac, hash);
+        /* OpenSSL compat, no error */
+
+        if (len) {
+            WOLFSSL_MSG("setting output len");
+            switch (ctx->type) {
+                case MD5:
+                    *len = MD5_DIGEST_SIZE;
+                    break;
+
+                case SHA:
+                    *len = SHA_DIGEST_SIZE;
+                    break;
+
+                case SHA256:
+                    *len = SHA256_DIGEST_SIZE;
+                    break;
+
+                default:
+                    WOLFSSL_MSG("bad hmac type");
+            }
+        }
+    }
+}
+
+
+void wolfSSL_HMAC_cleanup(WOLFSSL_HMAC_CTX* ctx)
+{
+    (void)ctx;
+
+    WOLFSSL_MSG("wolfSSL_HMAC_cleanup");
+}
+
+
+const WOLFSSL_EVP_MD* wolfSSL_EVP_get_digestbynid(int id)
+{
+    WOLFSSL_MSG("wolfSSL_get_digestbynid");
+
+    switch(id) {
+#ifndef NO_MD5
+        case NID_md5:
+            return wolfSSL_EVP_md5();
+#endif
+#ifndef NO_SHA
+        case NID_sha1:
+            return wolfSSL_EVP_sha1();
+#endif
+        default:
+            WOLFSSL_MSG("Bad digest id value");
+    }
+
+    return NULL;
+}
+
+
+WOLFSSL_RSA* wolfSSL_EVP_PKEY_get1_RSA(WOLFSSL_EVP_PKEY* key)
+{
+    (void)key;
+    WOLFSSL_MSG("wolfSSL_EVP_PKEY_get1_RSA");
+
+    return NULL;
+}
+
+
+WOLFSSL_DSA* wolfSSL_EVP_PKEY_get1_DSA(WOLFSSL_EVP_PKEY* key)
+{
+    (void)key;
+    WOLFSSL_MSG("wolfSSL_EVP_PKEY_get1_DSA");
+
+    return NULL;
+}
+
+
+void* wolfSSL_EVP_X_STATE(const WOLFSSL_EVP_CIPHER_CTX* ctx)
+{
+    WOLFSSL_MSG("wolfSSL_EVP_X_STATE");
+
+    if (ctx) {
+        switch (ctx->cipherType) {
+            case ARC4_TYPE:
+                WOLFSSL_MSG("returning arc4 state");
+                return (void*)&ctx->cipher.arc4.x;
+
+            default:
+                WOLFSSL_MSG("bad x state type");
+                return 0;
+        }
+    }
+
+    return NULL;
+}
+
+
+int wolfSSL_EVP_X_STATE_LEN(const WOLFSSL_EVP_CIPHER_CTX* ctx)
+{
+    WOLFSSL_MSG("wolfSSL_EVP_X_STATE_LEN");
+
+    if (ctx) {
+        switch (ctx->cipherType) {
+            case ARC4_TYPE:
+                WOLFSSL_MSG("returning arc4 state size");
+                return sizeof(Arc4);
+
+            default:
+                WOLFSSL_MSG("bad x state type");
+                return 0;
+        }
+    }
+
+    return 0;
+}
+
+
+#ifndef NO_DES3
+
+void wolfSSL_3des_iv(WOLFSSL_EVP_CIPHER_CTX* ctx, int doset,
+                            unsigned char* iv, int len)
+{
+    (void)len;
+
+    WOLFSSL_MSG("wolfSSL_3des_iv");
+
+    if (ctx == NULL || iv == NULL) {
+        WOLFSSL_MSG("Bad function argument");
+        return;
+    }
+
+    if (doset)
+        wc_Des3_SetIV(&ctx->cipher.des3, iv);  /* OpenSSL compat, no ret */
+    else
+        memcpy(iv, &ctx->cipher.des3.reg, DES_BLOCK_SIZE);
+}
+
+#endif /* NO_DES3 */
+
+
+#ifndef NO_AES
+
+void wolfSSL_aes_ctr_iv(WOLFSSL_EVP_CIPHER_CTX* ctx, int doset,
+                      unsigned char* iv, int len)
+{
+    (void)len;
+
+    WOLFSSL_MSG("wolfSSL_aes_ctr_iv");
+
+    if (ctx == NULL || iv == NULL) {
+        WOLFSSL_MSG("Bad function argument");
+        return;
+    }
+
+    if (doset)
+        wc_AesSetIV(&ctx->cipher.aes, iv);  /* OpenSSL compat, no ret */
+    else
+        memcpy(iv, &ctx->cipher.aes.reg, AES_BLOCK_SIZE);
+}
+
+#endif /* NO_AES */
+
+
+const WOLFSSL_EVP_MD* wolfSSL_EVP_ripemd160(void)
+{
+    WOLFSSL_MSG("wolfSSL_ripemd160");
+
+    return NULL;
+}
+
+
+int wolfSSL_EVP_MD_size(const WOLFSSL_EVP_MD* type)
+{
+    WOLFSSL_MSG("wolfSSL_EVP_MD_size");
+
+    if (type == NULL) {
+        WOLFSSL_MSG("No md type arg");
+        return BAD_FUNC_ARG;
+    }
+
+    if (XSTRNCMP(type, "SHA256", 6) == 0) {
+        return SHA256_DIGEST_SIZE;
+    }
+#ifndef NO_MD5
+    else if (XSTRNCMP(type, "MD5", 3) == 0) {
+        return MD5_DIGEST_SIZE;
+    }
+#endif
+#ifdef WOLFSSL_SHA384
+    else if (XSTRNCMP(type, "SHA384", 6) == 0) {
+        return SHA384_DIGEST_SIZE;
+    }
+#endif
+#ifdef WOLFSSL_SHA512
+    else if (XSTRNCMP(type, "SHA512", 6) == 0) {
+        return SHA512_DIGEST_SIZE;
+    }
+#endif
+#ifndef NO_SHA
+    /* has to be last since would pick or 256, 384, or 512 too */
+    else if (XSTRNCMP(type, "SHA", 3) == 0) {
+        return SHA_DIGEST_SIZE;
+    }
+#endif
+
+    return BAD_FUNC_ARG;
+}
+
+
+int wolfSSL_EVP_CIPHER_CTX_iv_length(const WOLFSSL_EVP_CIPHER_CTX* ctx)
+{
+    WOLFSSL_MSG("wolfSSL_EVP_CIPHER_CTX_iv_length");
+
+    switch (ctx->cipherType) {
+
+        case AES_128_CBC_TYPE :
+        case AES_192_CBC_TYPE :
+        case AES_256_CBC_TYPE :
+            WOLFSSL_MSG("AES CBC");
+            return AES_BLOCK_SIZE;
+
+#ifdef WOLFSSL_AES_COUNTER
+        case AES_128_CTR_TYPE :
+        case AES_192_CTR_TYPE :
+        case AES_256_CTR_TYPE :
+            WOLFSSL_MSG("AES CTR");
+            return AES_BLOCK_SIZE;
+#endif
+
+        case DES_CBC_TYPE :
+            WOLFSSL_MSG("DES CBC");
+            return DES_BLOCK_SIZE;
+
+        case DES_EDE3_CBC_TYPE :
+            WOLFSSL_MSG("DES EDE3 CBC");
+            return DES_BLOCK_SIZE;
+
+        case ARC4_TYPE :
+            WOLFSSL_MSG("ARC4");
+            return 0;
+
+        case NULL_CIPHER_TYPE :
+            WOLFSSL_MSG("NULL");
+            return 0;
+
+        default: {
+            WOLFSSL_MSG("bad type");
+        }
+    }
+    return 0;
+}
+
+
+void wolfSSL_OPENSSL_free(void* p)
+{
+    WOLFSSL_MSG("wolfSSL_OPENSSL_free");
+
+    XFREE(p, NULL, 0);
+}
+
+
+int wolfSSL_PEM_write_bio_RSAPrivateKey(WOLFSSL_BIO* bio, RSA* rsa,
+                                  const EVP_CIPHER* cipher,
+                                  unsigned char* passwd, int len,
+                                  pem_password_cb cb, void* arg)
+{
+    (void)bio;
+    (void)rsa;
+    (void)cipher;
+    (void)passwd;
+    (void)len;
+    (void)cb;
+    (void)arg;
+
+    WOLFSSL_MSG("wolfSSL_PEM_write_bio_RSAPrivateKey");
+
+    return SSL_FATAL_ERROR;
+}
+
+
+
+int wolfSSL_PEM_write_bio_DSAPrivateKey(WOLFSSL_BIO* bio, DSA* rsa,
+                                  const EVP_CIPHER* cipher,
+                                  unsigned char* passwd, int len,
+                                  pem_password_cb cb, void* arg)
+{
+    (void)bio;
+    (void)rsa;
+    (void)cipher;
+    (void)passwd;
+    (void)len;
+    (void)cb;
+    (void)arg;
+
+    WOLFSSL_MSG("wolfSSL_PEM_write_bio_DSAPrivateKey");
+
+    return SSL_FATAL_ERROR;
+}
+
+
+
+WOLFSSL_EVP_PKEY* wolfSSL_PEM_read_bio_PrivateKey(WOLFSSL_BIO* bio,
+                    WOLFSSL_EVP_PKEY** key, pem_password_cb cb, void* arg)
+{
+    (void)bio;
+    (void)key;
+    (void)cb;
+    (void)arg;
+
+    WOLFSSL_MSG("wolfSSL_PEM_read_bio_PrivateKey");
+
+    return NULL;
+}
+
+
+
+#ifndef NO_RSA
+/* Load RSA from Der, SSL_SUCCESS on success < 0 on error */
+int wolfSSL_RSA_LoadDer(WOLFSSL_RSA* rsa, const unsigned char* der,  int derSz)
+{
+    word32 idx = 0;
+    int    ret;
+
+    WOLFSSL_ENTER("wolfSSL_RSA_LoadDer");
+
+    if (rsa == NULL || rsa->internal == NULL || der == NULL || derSz <= 0) {
+        WOLFSSL_MSG("Bad function arguments");
+        return BAD_FUNC_ARG;
+    }
+
+    ret = wc_RsaPrivateKeyDecode(der, &idx, (RsaKey*)rsa->internal, derSz);
+    if (ret < 0) {
+        WOLFSSL_MSG("RsaPrivateKeyDecode failed");
+        return ret;
+    }
+
+    if (SetRsaExternal(rsa) < 0) {
+        WOLFSSL_MSG("SetRsaExternal failed");
+        return SSL_FATAL_ERROR;
+    }
+
+    rsa->inSet = 1;
+
+    return SSL_SUCCESS;
+}
+#endif /* NO_RSA */
+
+
+#ifndef NO_DSA
+/* Load DSA from Der, SSL_SUCCESS on success < 0 on error */
+int wolfSSL_DSA_LoadDer(WOLFSSL_DSA* dsa, const unsigned char* der,  int derSz)
+{
+    word32 idx = 0;
+    int    ret;
+
+    WOLFSSL_ENTER("wolfSSL_DSA_LoadDer");
+
+    if (dsa == NULL || dsa->internal == NULL || der == NULL || derSz <= 0) {
+        WOLFSSL_MSG("Bad function arguments");
+        return BAD_FUNC_ARG;
+    }
+
+    ret = DsaPrivateKeyDecode(der, &idx, (DsaKey*)dsa->internal, derSz);
+    if (ret < 0) {
+        WOLFSSL_MSG("DsaPrivateKeyDecode failed");
+        return ret;
+    }
+
+    if (SetDsaExternal(dsa) < 0) {
+        WOLFSSL_MSG("SetDsaExternal failed");
+        return SSL_FATAL_ERROR;
+    }
+
+    dsa->inSet = 1;
+
+    return SSL_SUCCESS;
+}
+#endif /* NO_DSA */
+
+
+
+
+#endif /* OPENSSL_EXTRA */
+
+
+#ifdef SESSION_CERTS
+
+
+/* Get peer's certificate chain */
+WOLFSSL_X509_CHAIN* wolfSSL_get_peer_chain(WOLFSSL* ssl)
+{
+    WOLFSSL_ENTER("wolfSSL_get_peer_chain");
+    if (ssl)
+        return &ssl->session.chain;
+
+    return 0;
+}
+
+
+/* Get peer's certificate chain total count */
+int wolfSSL_get_chain_count(WOLFSSL_X509_CHAIN* chain)
+{
+    WOLFSSL_ENTER("wolfSSL_get_chain_count");
+    if (chain)
+        return chain->count;
+
+    return 0;
+}
+
+
+/* Get peer's ASN.1 DER ceritifcate at index (idx) length in bytes */
+int wolfSSL_get_chain_length(WOLFSSL_X509_CHAIN* chain, int idx)
+{
+    WOLFSSL_ENTER("wolfSSL_get_chain_length");
+    if (chain)
+        return chain->certs[idx].length;
+
+    return 0;
+}
+
+
+/* Get peer's ASN.1 DER ceritifcate at index (idx) */
+byte* wolfSSL_get_chain_cert(WOLFSSL_X509_CHAIN* chain, int idx)
+{
+    WOLFSSL_ENTER("wolfSSL_get_chain_cert");
+    if (chain)
+        return chain->certs[idx].buffer;
+
+    return 0;
+}
+
+
+/* Get peer's wolfSSL X509 ceritifcate at index (idx) */
+WOLFSSL_X509* wolfSSL_get_chain_X509(WOLFSSL_X509_CHAIN* chain, int idx)
+{
+    int          ret;
+    WOLFSSL_X509* x509 = NULL;
+#ifdef WOLFSSL_SMALL_STACK
+    DecodedCert* cert = NULL;
+#else
+    DecodedCert  cert[1];
+#endif
+
+    WOLFSSL_ENTER("wolfSSL_get_chain_X509");
+    if (chain != NULL) {
+    #ifdef WOLFSSL_SMALL_STACK
+        cert = (DecodedCert*)XMALLOC(sizeof(DecodedCert), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+        if (cert != NULL)
+    #endif
+        {
+            InitDecodedCert(cert, chain->certs[idx].buffer,
+                                  chain->certs[idx].length, NULL);
+
+            if ((ret = ParseCertRelative(cert, CERT_TYPE, 0, NULL)) != 0)
+                WOLFSSL_MSG("Failed to parse cert");
+            else {
+                x509 = (WOLFSSL_X509*)XMALLOC(sizeof(WOLFSSL_X509), NULL,
+                                                             DYNAMIC_TYPE_X509);
+                if (x509 == NULL) {
+                    WOLFSSL_MSG("Failed alloc X509");
+                }
+                else {
+                    InitX509(x509, 1);
+
+                    if ((ret = CopyDecodedToX509(x509, cert)) != 0) {
+                        WOLFSSL_MSG("Failed to copy decoded");
+                        XFREE(x509, NULL, DYNAMIC_TYPE_X509);
+                        x509 = NULL;
+                    }
+                }
+            }
+
+            FreeDecodedCert(cert);
+        #ifdef WOLFSSL_SMALL_STACK
+            XFREE(cert, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        #endif
+        }
+    }
+
+    return x509;
+}
+
+
+/* Get peer's PEM ceritifcate at index (idx), output to buffer if inLen big
+   enough else return error (-1), output length is in *outLen
+   SSL_SUCCESS on ok */
+int  wolfSSL_get_chain_cert_pem(WOLFSSL_X509_CHAIN* chain, int idx,
+                               unsigned char* buf, int inLen, int* outLen)
+{
+    const char header[] = "-----BEGIN CERTIFICATE-----\n";
+    const char footer[] = "-----END CERTIFICATE-----\n";
+
+    int headerLen = sizeof(header) - 1;
+    int footerLen = sizeof(footer) - 1;
+    int i;
+    int err;
+
+    WOLFSSL_ENTER("wolfSSL_get_chain_cert_pem");
+    if (!chain || !outLen || !buf)
+        return BAD_FUNC_ARG;
+
+    /* don't even try if inLen too short */
+    if (inLen < headerLen + footerLen + chain->certs[idx].length)
+        return BAD_FUNC_ARG;
+
+    /* header */
+    XMEMCPY(buf, header, headerLen);
+    i = headerLen;
+
+    /* body */
+    *outLen = inLen;  /* input to Base64_Encode */
+    if ( (err = Base64_Encode(chain->certs[idx].buffer,
+                       chain->certs[idx].length, buf + i, (word32*)outLen)) < 0)
+        return err;
+    i += *outLen;
+
+    /* footer */
+    if ( (i + footerLen) > inLen)
+        return BAD_FUNC_ARG;
+    XMEMCPY(buf + i, footer, footerLen);
+    *outLen += headerLen + footerLen;
+
+    return SSL_SUCCESS;
+}
+
+
+/* get session ID */
+const byte* wolfSSL_get_sessionID(const WOLFSSL_SESSION* session)
+{
+    WOLFSSL_ENTER("wolfSSL_get_sessionID");
+    if (session)
+        return session->sessionID;
+
+    return NULL;
+}
+
+
+#endif /* SESSION_CERTS */
+
+#ifdef HAVE_FUZZER
+void wolfSSL_SetFuzzerCb(WOLFSSL* ssl, CallbackFuzzer cbf, void* fCtx)
+{
+    if (ssl) {
+        ssl->fuzzerCb  = cbf;
+        ssl->fuzzerCtx = fCtx;
+    }
+}
+#endif
+
+#ifndef NO_CERTS
+#ifdef  HAVE_PK_CALLBACKS
+
+#ifdef HAVE_ECC
+
+void  wolfSSL_CTX_SetEccSignCb(WOLFSSL_CTX* ctx, CallbackEccSign cb)
+{
+    if (ctx)
+        ctx->EccSignCb = cb;
+}
+
+
+void  wolfSSL_SetEccSignCtx(WOLFSSL* ssl, void *ctx)
+{
+    if (ssl)
+        ssl->EccSignCtx = ctx;
+}
+
+
+void* wolfSSL_GetEccSignCtx(WOLFSSL* ssl)
+{
+    if (ssl)
+        return ssl->EccSignCtx;
+
+    return NULL;
+}
+
+
+void  wolfSSL_CTX_SetEccVerifyCb(WOLFSSL_CTX* ctx, CallbackEccVerify cb)
+{
+    if (ctx)
+        ctx->EccVerifyCb = cb;
+}
+
+
+void  wolfSSL_SetEccVerifyCtx(WOLFSSL* ssl, void *ctx)
+{
+    if (ssl)
+        ssl->EccVerifyCtx = ctx;
+}
+
+
+void* wolfSSL_GetEccVerifyCtx(WOLFSSL* ssl)
+{
+    if (ssl)
+        return ssl->EccVerifyCtx;
+
+    return NULL;
+}
+
+#endif /* HAVE_ECC */
+
+#ifndef NO_RSA
+
+void  wolfSSL_CTX_SetRsaSignCb(WOLFSSL_CTX* ctx, CallbackRsaSign cb)
+{
+    if (ctx)
+        ctx->RsaSignCb = cb;
+}
+
+
+void  wolfSSL_SetRsaSignCtx(WOLFSSL* ssl, void *ctx)
+{
+    if (ssl)
+        ssl->RsaSignCtx = ctx;
+}
+
+
+void* wolfSSL_GetRsaSignCtx(WOLFSSL* ssl)
+{
+    if (ssl)
+        return ssl->RsaSignCtx;
+
+    return NULL;
+}
+
+
+void  wolfSSL_CTX_SetRsaVerifyCb(WOLFSSL_CTX* ctx, CallbackRsaVerify cb)
+{
+    if (ctx)
+        ctx->RsaVerifyCb = cb;
+}
+
+
+void  wolfSSL_SetRsaVerifyCtx(WOLFSSL* ssl, void *ctx)
+{
+    if (ssl)
+        ssl->RsaVerifyCtx = ctx;
+}
+
+
+void* wolfSSL_GetRsaVerifyCtx(WOLFSSL* ssl)
+{
+    if (ssl)
+        return ssl->RsaVerifyCtx;
+
+    return NULL;
+}
+
+void  wolfSSL_CTX_SetRsaEncCb(WOLFSSL_CTX* ctx, CallbackRsaEnc cb)
+{
+    if (ctx)
+        ctx->RsaEncCb = cb;
+}
+
+
+void  wolfSSL_SetRsaEncCtx(WOLFSSL* ssl, void *ctx)
+{
+    if (ssl)
+        ssl->RsaEncCtx = ctx;
+}
+
+
+void* wolfSSL_GetRsaEncCtx(WOLFSSL* ssl)
+{
+    if (ssl)
+        return ssl->RsaEncCtx;
+
+    return NULL;
+}
+
+void  wolfSSL_CTX_SetRsaDecCb(WOLFSSL_CTX* ctx, CallbackRsaDec cb)
+{
+    if (ctx)
+        ctx->RsaDecCb = cb;
+}
+
+
+void  wolfSSL_SetRsaDecCtx(WOLFSSL* ssl, void *ctx)
+{
+    if (ssl)
+        ssl->RsaDecCtx = ctx;
+}
+
+
+void* wolfSSL_GetRsaDecCtx(WOLFSSL* ssl)
+{
+    if (ssl)
+        return ssl->RsaDecCtx;
+
+    return NULL;
+}
+
+
+#endif /* NO_RSA */
+
+#endif /* HAVE_PK_CALLBACKS */
+#endif /* NO_CERTS */
+
+
+#ifdef WOLFSSL_HAVE_WOLFSCEP
+    /* Used by autoconf to see if wolfSCEP is available */
+    void wolfSSL_wolfSCEP(void) {}
+#endif
+
+
+#ifdef WOLFSSL_HAVE_CERT_SERVICE
+    /* Used by autoconf to see if cert service is available */
+    void wolfSSL_cert_service(void) {}
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/tls.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/tls.c
new file mode 100644
index 0000000..f4c76d7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/src/tls.c
@@ -0,0 +1,2446 @@
+/* tls.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+
+
+#ifndef NO_TLS
+
+
+#ifndef WOLFSSL_HAVE_MIN
+#define WOLFSSL_HAVE_MIN
+
+    static INLINE word32 min(word32 a, word32 b)
+    {
+        return a > b ? b : a;
+    }
+
+#endif /* WOLFSSL_HAVE_MIN */
+
+
+#ifdef WOLFSSL_SHA384
+    #define P_HASH_MAX_SIZE SHA384_DIGEST_SIZE
+#else
+    #define P_HASH_MAX_SIZE SHA256_DIGEST_SIZE
+#endif
+
+/* compute p_hash for MD5, SHA-1, SHA-256, or SHA-384 for TLSv1 PRF */
+static int p_hash(byte* result, word32 resLen, const byte* secret,
+                   word32 secLen, const byte* seed, word32 seedLen, int hash)
+{
+    word32 len = P_HASH_MAX_SIZE;
+    word32 times;
+    word32 lastLen;
+    word32 lastTime;
+    word32 i;
+    word32 idx = 0;
+    int    ret = 0;
+#ifdef WOLFSSL_SMALL_STACK
+    byte*  previous;
+    byte*  current;
+    Hmac*  hmac;
+#else
+    byte   previous[P_HASH_MAX_SIZE];  /* max size */
+    byte   current[P_HASH_MAX_SIZE];   /* max size */
+    Hmac   hmac[1];
+#endif
+
+#ifdef WOLFSSL_SMALL_STACK
+    previous = (byte*)XMALLOC(P_HASH_MAX_SIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    current  = (byte*)XMALLOC(P_HASH_MAX_SIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    hmac     = (Hmac*)XMALLOC(sizeof(Hmac),    NULL, DYNAMIC_TYPE_TMP_BUFFER);
+
+    if (previous == NULL || current == NULL || hmac == NULL) {
+        if (previous) XFREE(previous, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (current)  XFREE(current,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (hmac)     XFREE(hmac,     NULL, DYNAMIC_TYPE_TMP_BUFFER);
+
+        return MEMORY_E;
+    }
+#endif
+
+    switch (hash) {
+        #ifndef NO_MD5
+            case md5_mac:
+                hash = MD5;
+                len  = MD5_DIGEST_SIZE;
+            break;
+        #endif
+
+        #ifndef NO_SHA256
+            case sha256_mac:
+                hash = SHA256;
+                len  = SHA256_DIGEST_SIZE;
+            break;
+        #endif
+
+        #ifdef WOLFSSL_SHA384
+            case sha384_mac:
+                hash = SHA384;
+                len  = SHA384_DIGEST_SIZE;
+            break;
+        #endif
+
+        #ifndef NO_SHA
+            case sha_mac:
+            default:
+                hash = SHA;
+                len  = SHA_DIGEST_SIZE;
+            break;
+        #endif
+    }
+
+    times   = resLen / len;
+    lastLen = resLen % len;
+
+    if (lastLen)
+        times += 1;
+
+    lastTime = times - 1;
+
+    if ((ret = wc_HmacSetKey(hmac, hash, secret, secLen)) == 0) {
+        if ((ret = wc_HmacUpdate(hmac, seed, seedLen)) == 0) { /* A0 = seed */
+            if ((ret = wc_HmacFinal(hmac, previous)) == 0) {   /* A1 */
+                for (i = 0; i < times; i++) {
+                    ret = wc_HmacUpdate(hmac, previous, len);
+                    if (ret != 0)
+                        break;
+                    ret = wc_HmacUpdate(hmac, seed, seedLen);
+                    if (ret != 0)
+                        break;
+                    ret = wc_HmacFinal(hmac, current);
+                    if (ret != 0)
+                        break;
+
+                    if ((i == lastTime) && lastLen)
+                        XMEMCPY(&result[idx], current,
+                                                 min(lastLen, P_HASH_MAX_SIZE));
+                    else {
+                        XMEMCPY(&result[idx], current, len);
+                        idx += len;
+                        ret = wc_HmacUpdate(hmac, previous, len);
+                        if (ret != 0)
+                            break;
+                        ret = wc_HmacFinal(hmac, previous);
+                        if (ret != 0)
+                            break;
+                    }
+                }
+            }
+        }
+    }
+
+    ForceZero(previous,  P_HASH_MAX_SIZE);
+    ForceZero(current,   P_HASH_MAX_SIZE);
+    ForceZero(hmac,      sizeof(Hmac));
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(previous, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(current,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(hmac,     NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+#undef P_HASH_MAX_SIZE
+
+
+#ifndef NO_OLD_TLS
+
+/* calculate XOR for TLSv1 PRF */
+static INLINE void get_xor(byte *digest, word32 digLen, byte* md5, byte* sha)
+{
+    word32 i;
+
+    for (i = 0; i < digLen; i++)
+        digest[i] = md5[i] ^ sha[i];
+}
+
+
+/* compute TLSv1 PRF (pseudo random function using HMAC) */
+static int doPRF(byte* digest, word32 digLen, const byte* secret,word32 secLen,
+                 const byte* label, word32 labLen, const byte* seed,
+                 word32 seedLen)
+{
+    int    ret  = 0;
+    word32 half = (secLen + 1) / 2;
+
+#ifdef WOLFSSL_SMALL_STACK
+    byte* md5_half;
+    byte* sha_half;
+    byte* labelSeed;
+    byte* md5_result;
+    byte* sha_result;
+#else
+    byte  md5_half[MAX_PRF_HALF];     /* half is real size */
+    byte  sha_half[MAX_PRF_HALF];     /* half is real size */
+    byte  labelSeed[MAX_PRF_LABSEED]; /* labLen + seedLen is real size */
+    byte  md5_result[MAX_PRF_DIG];    /* digLen is real size */
+    byte  sha_result[MAX_PRF_DIG];    /* digLen is real size */
+#endif
+
+    if (half > MAX_PRF_HALF)
+        return BUFFER_E;
+    if (labLen + seedLen > MAX_PRF_LABSEED)
+        return BUFFER_E;
+    if (digLen > MAX_PRF_DIG)
+        return BUFFER_E;
+
+#ifdef WOLFSSL_SMALL_STACK
+    md5_half   = (byte*)XMALLOC(MAX_PRF_HALF,    NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    sha_half   = (byte*)XMALLOC(MAX_PRF_HALF,    NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    labelSeed  = (byte*)XMALLOC(MAX_PRF_LABSEED, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    md5_result = (byte*)XMALLOC(MAX_PRF_DIG,     NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    sha_result = (byte*)XMALLOC(MAX_PRF_DIG,     NULL, DYNAMIC_TYPE_TMP_BUFFER);
+
+    if (md5_half == NULL || sha_half == NULL || labelSeed == NULL ||
+                                     md5_result == NULL || sha_result == NULL) {
+        if (md5_half)   XFREE(md5_half,   NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (sha_half)   XFREE(sha_half,   NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (labelSeed)  XFREE(labelSeed,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (md5_result) XFREE(md5_result, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (sha_result) XFREE(sha_result, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+
+        return MEMORY_E;
+    }
+#endif
+
+    XMEMSET(md5_result, 0, digLen);
+    XMEMSET(sha_result, 0, digLen);
+
+    XMEMCPY(md5_half, secret, half);
+    XMEMCPY(sha_half, secret + half - secLen % 2, half);
+
+    XMEMCPY(labelSeed, label, labLen);
+    XMEMCPY(labelSeed + labLen, seed, seedLen);
+
+    if ((ret = p_hash(md5_result, digLen, md5_half, half, labelSeed,
+                                             labLen + seedLen, md5_mac)) == 0) {
+        if ((ret = p_hash(sha_result, digLen, sha_half, half, labelSeed,
+                                             labLen + seedLen, sha_mac)) == 0) {
+            get_xor(digest, digLen, md5_result, sha_result);
+        }
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(md5_half,   NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(sha_half,   NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(labelSeed,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(md5_result, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(sha_result, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+#endif
+
+
+/* Wrapper to call straight thru to p_hash in TSL 1.2 cases to remove stack
+   use */
+static int PRF(byte* digest, word32 digLen, const byte* secret, word32 secLen,
+            const byte* label, word32 labLen, const byte* seed, word32 seedLen,
+            int useAtLeastSha256, int hash_type)
+{
+    int ret = 0;
+
+    if (useAtLeastSha256) {
+#ifdef WOLFSSL_SMALL_STACK
+        byte* labelSeed;
+#else
+        byte labelSeed[MAX_PRF_LABSEED]; /* labLen + seedLen is real size */
+#endif
+
+        if (labLen + seedLen > MAX_PRF_LABSEED)
+            return BUFFER_E;
+
+#ifdef WOLFSSL_SMALL_STACK
+        labelSeed = (byte*)XMALLOC(MAX_PRF_LABSEED, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+        if (labelSeed == NULL)
+           return MEMORY_E;
+#endif
+
+        XMEMCPY(labelSeed, label, labLen);
+        XMEMCPY(labelSeed + labLen, seed, seedLen);
+
+        /* If a cipher suite wants an algorithm better than sha256, it
+         * should use better. */
+        if (hash_type < sha256_mac)
+            hash_type = sha256_mac;
+        ret = p_hash(digest, digLen, secret, secLen, labelSeed,
+                     labLen + seedLen, hash_type);
+
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(labelSeed, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+    }
+#ifndef NO_OLD_TLS
+    else {
+        ret = doPRF(digest, digLen, secret, secLen, label, labLen, seed,
+                    seedLen);
+    }
+#endif
+
+    return ret;
+}
+
+
+#ifdef WOLFSSL_SHA384
+    #define HSHASH_SZ SHA384_DIGEST_SIZE
+#else
+    #define HSHASH_SZ FINISHED_SZ
+#endif
+
+
+int BuildTlsFinished(WOLFSSL* ssl, Hashes* hashes, const byte* sender)
+{
+    const byte* side;
+    byte        handshake_hash[HSHASH_SZ];
+    word32      hashSz = FINISHED_SZ;
+
+#ifndef NO_OLD_TLS
+    wc_Md5GetHash(&ssl->hsHashes->hashMd5, handshake_hash);
+    wc_ShaGetHash(&ssl->hsHashes->hashSha, &handshake_hash[MD5_DIGEST_SIZE]);
+#endif
+
+    if (IsAtLeastTLSv1_2(ssl)) {
+#ifndef NO_SHA256
+        if (ssl->specs.mac_algorithm <= sha256_mac) {
+            int ret = wc_Sha256GetHash(&ssl->hsHashes->hashSha256,handshake_hash);
+
+            if (ret != 0)
+                return ret;
+
+            hashSz = SHA256_DIGEST_SIZE;
+        }
+#endif
+#ifdef WOLFSSL_SHA384
+        if (ssl->specs.mac_algorithm == sha384_mac) {
+            int ret = wc_Sha384Final(&ssl->hsHashes->hashSha384,handshake_hash);
+
+            if (ret != 0)
+                return ret;
+
+            hashSz = SHA384_DIGEST_SIZE;
+        }
+#endif
+    }
+
+    if ( XSTRNCMP((const char*)sender, (const char*)client, SIZEOF_SENDER) == 0)
+        side = tls_client;
+    else
+        side = tls_server;
+
+    return PRF((byte*)hashes, TLS_FINISHED_SZ, ssl->arrays->masterSecret,
+               SECRET_LEN, side, FINISHED_LABEL_SZ, handshake_hash, hashSz,
+               IsAtLeastTLSv1_2(ssl), ssl->specs.mac_algorithm);
+}
+
+
+#ifndef NO_OLD_TLS
+
+ProtocolVersion MakeTLSv1(void)
+{
+    ProtocolVersion pv;
+    pv.major = SSLv3_MAJOR;
+    pv.minor = TLSv1_MINOR;
+
+    return pv;
+}
+
+
+ProtocolVersion MakeTLSv1_1(void)
+{
+    ProtocolVersion pv;
+    pv.major = SSLv3_MAJOR;
+    pv.minor = TLSv1_1_MINOR;
+
+    return pv;
+}
+
+#endif
+
+
+ProtocolVersion MakeTLSv1_2(void)
+{
+    ProtocolVersion pv;
+    pv.major = SSLv3_MAJOR;
+    pv.minor = TLSv1_2_MINOR;
+
+    return pv;
+}
+
+
+static const byte master_label[MASTER_LABEL_SZ + 1] = "master secret";
+static const byte key_label   [KEY_LABEL_SZ + 1]    = "key expansion";
+
+
+/* External facing wrapper so user can call as well, 0 on success */
+int wolfSSL_DeriveTlsKeys(byte* key_data, word32 keyLen,
+                         const byte* ms, word32 msLen,
+                         const byte* sr, const byte* cr,
+                         int tls1_2, int hash_type)
+{
+    byte  seed[SEED_LEN];
+
+    XMEMCPY(seed,           sr, RAN_LEN);
+    XMEMCPY(seed + RAN_LEN, cr, RAN_LEN);
+
+    return PRF(key_data, keyLen, ms, msLen, key_label, KEY_LABEL_SZ,
+               seed, SEED_LEN, tls1_2, hash_type);
+}
+
+
+int DeriveTlsKeys(WOLFSSL* ssl)
+{
+    int   ret;
+    int   length = 2 * ssl->specs.hash_size +
+                   2 * ssl->specs.key_size  +
+                   2 * ssl->specs.iv_size;
+#ifdef WOLFSSL_SMALL_STACK
+    byte* key_data;
+#else
+    byte  key_data[MAX_PRF_DIG];
+#endif
+
+#ifdef WOLFSSL_SMALL_STACK
+    key_data = (byte*)XMALLOC(MAX_PRF_DIG, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (key_data == NULL) {
+        return MEMORY_E;
+    }
+#endif
+
+    ret = wolfSSL_DeriveTlsKeys(key_data, length,
+                           ssl->arrays->masterSecret, SECRET_LEN,
+                           ssl->arrays->serverRandom, ssl->arrays->clientRandom,
+                           IsAtLeastTLSv1_2(ssl), ssl->specs.mac_algorithm);
+    if (ret == 0)
+        ret = StoreKeys(ssl, key_data);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(key_data, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+
+/* External facing wrapper so user can call as well, 0 on success */
+int wolfSSL_MakeTlsMasterSecret(byte* ms, word32 msLen,
+                               const byte* pms, word32 pmsLen,
+                               const byte* cr, const byte* sr,
+                               int tls1_2, int hash_type)
+{
+    byte  seed[SEED_LEN];
+
+    XMEMCPY(seed,           cr, RAN_LEN);
+    XMEMCPY(seed + RAN_LEN, sr, RAN_LEN);
+
+    return PRF(ms, msLen, pms, pmsLen, master_label, MASTER_LABEL_SZ,
+               seed, SEED_LEN, tls1_2, hash_type);
+}
+
+
+int MakeTlsMasterSecret(WOLFSSL* ssl)
+{
+    int   ret;
+
+    ret = wolfSSL_MakeTlsMasterSecret(ssl->arrays->masterSecret, SECRET_LEN,
+              ssl->arrays->preMasterSecret, ssl->arrays->preMasterSz,
+              ssl->arrays->clientRandom, ssl->arrays->serverRandom,
+              IsAtLeastTLSv1_2(ssl), ssl->specs.mac_algorithm);
+
+    if (ret == 0) {
+    #ifdef SHOW_SECRETS
+        int i;
+
+        printf("master secret: ");
+        for (i = 0; i < SECRET_LEN; i++)
+            printf("%02x", ssl->arrays->masterSecret[i]);
+        printf("\n");
+    #endif
+
+        ret = DeriveTlsKeys(ssl);
+    }
+
+    return ret;
+}
+
+
+/* Used by EAP-TLS and EAP-TTLS to derive keying material from
+ * the master_secret. */
+int wolfSSL_make_eap_keys(WOLFSSL* ssl, void* msk, unsigned int len,
+                                                              const char* label)
+{
+    int   ret;
+#ifdef WOLFSSL_SMALL_STACK
+    byte* seed;
+#else
+    byte  seed[SEED_LEN];
+#endif
+
+#ifdef WOLFSSL_SMALL_STACK
+    seed = (byte*)XMALLOC(SEED_LEN, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (seed == NULL)
+        return MEMORY_E;
+#endif
+
+    /*
+     * As per RFC-5281, the order of the client and server randoms is reversed
+     * from that used by the TLS protocol to derive keys.
+     */
+    XMEMCPY(seed,           ssl->arrays->clientRandom, RAN_LEN);
+    XMEMCPY(seed + RAN_LEN, ssl->arrays->serverRandom, RAN_LEN);
+
+    ret = PRF((byte*)msk, len, ssl->arrays->masterSecret, SECRET_LEN,
+              (const byte *)label, (word32)strlen(label), seed, SEED_LEN,
+              IsAtLeastTLSv1_2(ssl), ssl->specs.mac_algorithm);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(seed, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+
+/*** next for static INLINE s copied internal.c ***/
+
+/* convert 16 bit integer to opaque */
+static INLINE void c16toa(word16 u16, byte* c)
+{
+    c[0] = (u16 >> 8) & 0xff;
+    c[1] =  u16 & 0xff;
+}
+
+#ifdef HAVE_TLS_EXTENSIONS
+/* convert opaque to 16 bit integer */
+static INLINE void ato16(const byte* c, word16* u16)
+{
+    *u16 = (c[0] << 8) | (c[1]);
+}
+
+#ifdef HAVE_SNI
+/* convert a 24 bit integer into a 32 bit one */
+static INLINE void c24to32(const word24 u24, word32* u32)
+{
+    *u32 = (u24[0] << 16) | (u24[1] << 8) | u24[2];
+}
+#endif
+#endif
+
+/* convert 32 bit integer to opaque */
+static INLINE void c32toa(word32 u32, byte* c)
+{
+    c[0] = (u32 >> 24) & 0xff;
+    c[1] = (u32 >> 16) & 0xff;
+    c[2] = (u32 >>  8) & 0xff;
+    c[3] =  u32 & 0xff;
+}
+
+
+static INLINE word32 GetSEQIncrement(WOLFSSL* ssl, int verify)
+{
+#ifdef WOLFSSL_DTLS
+    if (ssl->options.dtls) {
+        if (verify)
+            return ssl->keys.dtls_state.curSeq; /* explicit from peer */
+        else
+            return ssl->keys.dtls_sequence_number - 1; /* already incremented */
+    }
+#endif
+    if (verify)
+        return ssl->keys.peer_sequence_number++;
+    else
+        return ssl->keys.sequence_number++;
+}
+
+
+#ifdef WOLFSSL_DTLS
+
+static INLINE word32 GetEpoch(WOLFSSL* ssl, int verify)
+{
+    if (verify)
+        return ssl->keys.dtls_state.curEpoch;
+    else
+        return ssl->keys.dtls_epoch;
+}
+
+#endif /* WOLFSSL_DTLS */
+
+
+/*** end copy ***/
+
+
+/* return HMAC digest type in wolfSSL format */
+int wolfSSL_GetHmacType(WOLFSSL* ssl)
+{
+    if (ssl == NULL)
+        return BAD_FUNC_ARG;
+
+    switch (ssl->specs.mac_algorithm) {
+        #ifndef NO_MD5
+        case md5_mac:
+        {
+            return MD5;
+        }
+        #endif
+        #ifndef NO_SHA256
+        case sha256_mac:
+        {
+            return SHA256;
+        }
+        #endif
+        #ifdef WOLFSSL_SHA384
+        case sha384_mac:
+        {
+            return SHA384;
+        }
+
+        #endif
+        #ifndef NO_SHA
+        case sha_mac:
+        {
+            return SHA;
+        }
+        #endif
+        #ifdef HAVE_BLAKE2
+        case blake2b_mac:
+        {
+            return BLAKE2B_ID;
+        }
+        #endif
+        default:
+        {
+            return SSL_FATAL_ERROR;
+        }
+    }
+}
+
+
+int wolfSSL_SetTlsHmacInner(WOLFSSL* ssl, byte* inner, word32 sz, int content,
+                           int verify)
+{
+    if (ssl == NULL || inner == NULL)
+        return BAD_FUNC_ARG;
+
+    XMEMSET(inner, 0, WOLFSSL_TLS_HMAC_INNER_SZ);
+
+#ifdef WOLFSSL_DTLS
+    if (ssl->options.dtls)
+        c16toa((word16)GetEpoch(ssl, verify), inner);
+#endif
+    c32toa(GetSEQIncrement(ssl, verify), &inner[sizeof(word32)]);
+    inner[SEQ_SZ] = (byte)content;
+    inner[SEQ_SZ + ENUM_LEN]            = ssl->version.major;
+    inner[SEQ_SZ + ENUM_LEN + ENUM_LEN] = ssl->version.minor;
+    c16toa((word16)sz, inner + SEQ_SZ + ENUM_LEN + VERSION_SZ);
+
+    return 0;
+}
+
+
+/* TLS type HMAC */
+int TLS_hmac(WOLFSSL* ssl, byte* digest, const byte* in, word32 sz,
+              int content, int verify)
+{
+    Hmac hmac;
+    int  ret;
+    byte myInner[WOLFSSL_TLS_HMAC_INNER_SZ];
+
+    if (ssl == NULL)
+        return BAD_FUNC_ARG;
+
+#ifdef HAVE_FUZZER
+    if (ssl->fuzzerCb)
+        ssl->fuzzerCb(ssl, in, sz, FUZZ_HMAC, ssl->fuzzerCtx);
+#endif
+
+    wolfSSL_SetTlsHmacInner(ssl, myInner, sz, content, verify);
+
+    ret = wc_HmacSetKey(&hmac, wolfSSL_GetHmacType(ssl),
+                     wolfSSL_GetMacSecret(ssl, verify), ssl->specs.hash_size);
+    if (ret != 0)
+        return ret;
+    ret = wc_HmacUpdate(&hmac, myInner, sizeof(myInner));
+    if (ret != 0)
+        return ret;
+    ret = wc_HmacUpdate(&hmac, in, sz);                                /* content */
+    if (ret != 0)
+        return ret;
+    ret = wc_HmacFinal(&hmac, digest);
+    if (ret != 0)
+        return ret;
+
+    return 0;
+}
+
+#ifdef HAVE_TLS_EXTENSIONS
+
+
+/** Supports up to 64 flags. Update as needed. */
+#define SEMAPHORE_SIZE 8
+
+
+static INLINE word16 TLSX_ToSemaphore(word16 type)
+{
+    switch (type) {
+        case SECURE_RENEGOTIATION:
+            return 63;
+
+        default:
+            if (type > 62) {
+                /* This message SHOULD only happens during the adding of
+                   new TLS extensions in which its IANA number overflows
+                   the current semaphore's range, or if its number already
+                   is assigned to be used by another extension.
+                   Use this check value for the new extension and decrement
+                   the check value by one. */
+                WOLFSSL_MSG("### TLSX semaphore colision or overflow detected!");
+            }
+    }
+
+    return type;
+}
+
+
+#define IS_OFF(semaphore, light) \
+    ((semaphore)[(light) / 8] ^  (byte) (0x01 << ((light) % 8)))
+
+
+#define TURN_ON(semaphore, light) \
+    ((semaphore)[(light) / 8] |= (byte) (0x01 << ((light) % 8)))
+
+
+static int TLSX_Push(TLSX** list, TLSX_Type type, void* data)
+{
+    TLSX* extension;
+
+    extension = (TLSX*)XMALLOC(sizeof(TLSX), 0, DYNAMIC_TYPE_TLSX);
+    if (extension == NULL)
+        return MEMORY_E;
+
+    extension->type = type;
+    extension->data = data;
+    extension->resp = 0;
+    extension->next = *list;
+    *list = extension;
+
+    /* remove duplicated extensions, there should be only one of each type. */
+    do {
+        if (extension->next && extension->next->type == type) {
+            TLSX *next = extension->next;
+
+            extension->next = next->next;
+            next->next = NULL;
+
+            TLSX_FreeAll(next);
+
+            /* there is no way to occur more than */
+            /* two extensions of the same type.   */
+            break;
+        }
+    } while ((extension = extension->next));
+
+    return 0;
+}
+
+
+#ifndef NO_WOLFSSL_SERVER
+
+void TLSX_SetResponse(WOLFSSL* ssl, TLSX_Type type);
+
+void TLSX_SetResponse(WOLFSSL* ssl, TLSX_Type type)
+{
+    TLSX *ext = TLSX_Find(ssl->extensions, type);
+
+    if (ext)
+        ext->resp = 1;
+}
+
+#endif
+
+/* SNI - Server Name Indication */
+
+#ifdef HAVE_SNI
+
+static void TLSX_SNI_Free(SNI* sni)
+{
+    if (sni) {
+        switch (sni->type) {
+            case WOLFSSL_SNI_HOST_NAME:
+                XFREE(sni->data.host_name, 0, DYNAMIC_TYPE_TLSX);
+            break;
+        }
+
+        XFREE(sni, 0, DYNAMIC_TYPE_TLSX);
+    }
+}
+
+static void TLSX_SNI_FreeAll(SNI* list)
+{
+    SNI* sni;
+
+    while ((sni = list)) {
+        list = sni->next;
+        TLSX_SNI_Free(sni);
+    }
+}
+
+static int TLSX_SNI_Append(SNI** list, byte type, const void* data, word16 size)
+{
+    SNI* sni;
+
+    if (list == NULL)
+        return BAD_FUNC_ARG;
+
+    if ((sni = XMALLOC(sizeof(SNI), 0, DYNAMIC_TYPE_TLSX)) == NULL)
+        return MEMORY_E;
+
+    switch (type) {
+        case WOLFSSL_SNI_HOST_NAME: {
+            sni->data.host_name = XMALLOC(size + 1, 0, DYNAMIC_TYPE_TLSX);
+
+            if (sni->data.host_name) {
+                XSTRNCPY(sni->data.host_name, (const char*)data, size);
+                sni->data.host_name[size] = 0;
+            } else {
+                XFREE(sni, 0, DYNAMIC_TYPE_TLSX);
+                return MEMORY_E;
+            }
+        }
+        break;
+
+        default: /* invalid type */
+            XFREE(sni, 0, DYNAMIC_TYPE_TLSX);
+            return BAD_FUNC_ARG;
+    }
+
+    sni->type = type;
+    sni->next = *list;
+
+#ifndef NO_WOLFSSL_SERVER
+    sni->options = 0;
+    sni->status  = WOLFSSL_SNI_NO_MATCH;
+#endif
+
+    *list = sni;
+
+    return 0;
+}
+
+static word16 TLSX_SNI_GetSize(SNI* list)
+{
+    SNI* sni;
+    word16 length = OPAQUE16_LEN; /* list length */
+
+    while ((sni = list)) {
+        list = sni->next;
+
+        length += ENUM_LEN + OPAQUE16_LEN; /* sni type + sni length */
+
+        switch (sni->type) {
+            case WOLFSSL_SNI_HOST_NAME:
+                length += XSTRLEN((char*)sni->data.host_name);
+            break;
+        }
+    }
+
+    return length;
+}
+
+static word16 TLSX_SNI_Write(SNI* list, byte* output)
+{
+    SNI* sni;
+    word16 length = 0;
+    word16 offset = OPAQUE16_LEN; /* list length offset */
+
+    while ((sni = list)) {
+        list = sni->next;
+
+        output[offset++] = sni->type; /* sni type */
+
+        switch (sni->type) {
+            case WOLFSSL_SNI_HOST_NAME:
+                length = XSTRLEN((char*)sni->data.host_name);
+
+                c16toa(length, output + offset); /* sni length */
+                offset += OPAQUE16_LEN;
+
+                XMEMCPY(output + offset, sni->data.host_name, length);
+
+                offset += length;
+            break;
+        }
+    }
+
+    c16toa(offset - OPAQUE16_LEN, output); /* writing list length */
+
+    return offset;
+}
+
+static SNI* TLSX_SNI_Find(SNI *list, byte type)
+{
+    SNI *sni = list;
+
+    while (sni && sni->type != type)
+        sni = sni->next;
+
+    return sni;
+}
+
+#ifndef NO_WOLFSSL_SERVER
+static void TLSX_SNI_SetStatus(TLSX* extensions, byte type, byte status)
+{
+    TLSX* extension = TLSX_Find(extensions, SERVER_NAME_INDICATION);
+    SNI* sni = TLSX_SNI_Find(extension ? extension->data : NULL, type);
+
+    if (sni) {
+        sni->status = status;
+        WOLFSSL_MSG("SNI did match!");
+    }
+}
+
+byte TLSX_SNI_Status(TLSX* extensions, byte type)
+{
+    TLSX* extension = TLSX_Find(extensions, SERVER_NAME_INDICATION);
+    SNI* sni = TLSX_SNI_Find(extension ? extension->data : NULL, type);
+
+    if (sni)
+        return sni->status;
+
+    return 0;
+}
+#endif
+
+static int TLSX_SNI_Parse(WOLFSSL* ssl, byte* input, word16 length,
+                                                                 byte isRequest)
+{
+#ifndef NO_WOLFSSL_SERVER
+    word16 size = 0;
+    word16 offset = 0;
+#endif
+
+    TLSX *extension = TLSX_Find(ssl->extensions, SERVER_NAME_INDICATION);
+
+    if (!extension)
+        extension = TLSX_Find(ssl->ctx->extensions, SERVER_NAME_INDICATION);
+
+    if (!extension || !extension->data)
+        return isRequest ? 0 : BUFFER_ERROR; /* not using SNI OR unexpected
+                                                SNI response from server. */
+
+    if (!isRequest)
+        return length ? BUFFER_ERROR : 0; /* SNI response must be empty!
+                                             Nothing else to do. */
+
+#ifndef NO_WOLFSSL_SERVER
+
+    if (OPAQUE16_LEN > length)
+        return BUFFER_ERROR;
+
+    ato16(input, &size);
+    offset += OPAQUE16_LEN;
+
+    /* validating sni list length */
+    if (length != OPAQUE16_LEN + size)
+        return BUFFER_ERROR;
+
+    for (size = 0; offset < length; offset += size) {
+        SNI *sni;
+        byte type = input[offset++];
+
+        if (offset + OPAQUE16_LEN > length)
+            return BUFFER_ERROR;
+
+        ato16(input + offset, &size);
+        offset += OPAQUE16_LEN;
+
+        if (offset + size > length)
+            return BUFFER_ERROR;
+
+        if (!(sni = TLSX_SNI_Find((SNI*)extension->data, type))) {
+            continue; /* not using this SNI type */
+        }
+
+        switch(type) {
+            case WOLFSSL_SNI_HOST_NAME: {
+                byte matched = (XSTRLEN(sni->data.host_name) == size)
+                            && (XSTRNCMP(sni->data.host_name,
+                                       (const char*)input + offset, size) == 0);
+
+                if (matched || sni->options & WOLFSSL_SNI_ANSWER_ON_MISMATCH) {
+                    int r = TLSX_UseSNI(&ssl->extensions,
+                                                    type, input + offset, size);
+
+                    if (r != SSL_SUCCESS) return r; /* throw error */
+
+                    TLSX_SNI_SetStatus(ssl->extensions, type,
+                      matched ? WOLFSSL_SNI_REAL_MATCH : WOLFSSL_SNI_FAKE_MATCH);
+
+                } else if (!(sni->options & WOLFSSL_SNI_CONTINUE_ON_MISMATCH)) {
+                    SendAlert(ssl, alert_fatal, unrecognized_name);
+
+                    return UNKNOWN_SNI_HOST_NAME_E;
+                }
+                break;
+            }
+        }
+
+        TLSX_SetResponse(ssl, SERVER_NAME_INDICATION);
+    }
+
+#endif
+
+    return 0;
+}
+
+int TLSX_UseSNI(TLSX** extensions, byte type, const void* data, word16 size)
+{
+    TLSX* extension = TLSX_Find(*extensions, SERVER_NAME_INDICATION);
+    SNI*  sni       = NULL;
+    int   ret       = 0;
+
+    if (extensions == NULL || data == NULL)
+        return BAD_FUNC_ARG;
+
+    if ((ret = TLSX_SNI_Append(&sni, type, data, size)) != 0)
+        return ret;
+
+    if (!extension) {
+        if ((ret = TLSX_Push(extensions, SERVER_NAME_INDICATION, (void*)sni))
+                                                                         != 0) {
+            TLSX_SNI_Free(sni);
+            return ret;
+        }
+    }
+    else {
+        /* push new SNI object to extension data. */
+        sni->next = (SNI*)extension->data;
+        extension->data = (void*)sni;
+
+        /* look for another server name of the same type to remove */
+        do {
+            if (sni->next && sni->next->type == type) {
+                SNI *next = sni->next;
+
+                sni->next = next->next;
+                TLSX_SNI_Free(next);
+
+                break;
+            }
+        } while ((sni = sni->next));
+    }
+
+    return SSL_SUCCESS;
+}
+
+#ifndef NO_WOLFSSL_SERVER
+word16 TLSX_SNI_GetRequest(TLSX* extensions, byte type, void** data)
+{
+    TLSX* extension = TLSX_Find(extensions, SERVER_NAME_INDICATION);
+    SNI* sni = TLSX_SNI_Find(extension ? extension->data : NULL, type);
+
+    if (sni && sni->status != WOLFSSL_SNI_NO_MATCH) {
+        switch (sni->type) {
+            case WOLFSSL_SNI_HOST_NAME:
+                *data = sni->data.host_name;
+                return XSTRLEN(*data);
+        }
+    }
+
+    return 0;
+}
+
+void TLSX_SNI_SetOptions(TLSX* extensions, byte type, byte options)
+{
+    TLSX* extension = TLSX_Find(extensions, SERVER_NAME_INDICATION);
+    SNI* sni = TLSX_SNI_Find(extension ? extension->data : NULL, type);
+
+    if (sni)
+        sni->options = options;
+}
+
+int TLSX_SNI_GetFromBuffer(const byte* clientHello, word32 helloSz,
+                           byte type, byte* sni, word32* inOutSz)
+{
+    word32 offset = 0;
+    word32 len32  = 0;
+    word16 len16  = 0;
+
+    if (helloSz < RECORD_HEADER_SZ + HANDSHAKE_HEADER_SZ + CLIENT_HELLO_FIRST)
+        return INCOMPLETE_DATA;
+
+    /* TLS record header */
+    if ((enum ContentType) clientHello[offset++] != handshake)
+        return BUFFER_ERROR;
+
+    if (clientHello[offset++] != SSLv3_MAJOR)
+        return BUFFER_ERROR;
+
+    if (clientHello[offset++] < TLSv1_MINOR)
+        return SNI_UNSUPPORTED;
+
+    ato16(clientHello + offset, &len16);
+    offset += OPAQUE16_LEN;
+
+    if (offset + len16 > helloSz)
+        return INCOMPLETE_DATA;
+
+    /* Handshake header */
+    if ((enum HandShakeType) clientHello[offset] != client_hello)
+        return BUFFER_ERROR;
+
+    c24to32(clientHello + offset + 1, &len32);
+    offset += HANDSHAKE_HEADER_SZ;
+
+    if (offset + len32 > helloSz)
+        return BUFFER_ERROR;
+
+    /* client hello */
+    offset += VERSION_SZ + RAN_LEN; /* version, random */
+
+    if (helloSz < offset + clientHello[offset])
+        return BUFFER_ERROR;
+
+    offset += ENUM_LEN + clientHello[offset]; /* skip session id */
+
+    /* cypher suites */
+    if (helloSz < offset + OPAQUE16_LEN)
+        return BUFFER_ERROR;
+
+    ato16(clientHello + offset, &len16);
+    offset += OPAQUE16_LEN;
+
+    if (helloSz < offset + len16)
+        return BUFFER_ERROR;
+
+    offset += len16; /* skip cypher suites */
+
+    /* compression methods */
+    if (helloSz < offset + 1)
+        return BUFFER_ERROR;
+
+    if (helloSz < offset + clientHello[offset])
+        return BUFFER_ERROR;
+
+    offset += ENUM_LEN + clientHello[offset]; /* skip compression methods */
+
+    /* extensions */
+    if (helloSz < offset + OPAQUE16_LEN)
+        return 0; /* no extensions in client hello. */
+
+    ato16(clientHello + offset, &len16);
+    offset += OPAQUE16_LEN;
+
+    if (helloSz < offset + len16)
+        return BUFFER_ERROR;
+
+    while (len16 >= OPAQUE16_LEN + OPAQUE16_LEN) {
+        word16 extType;
+        word16 extLen;
+
+        ato16(clientHello + offset, &extType);
+        offset += OPAQUE16_LEN;
+
+        ato16(clientHello + offset, &extLen);
+        offset += OPAQUE16_LEN;
+
+        if (helloSz < offset + extLen)
+            return BUFFER_ERROR;
+
+        if (extType != SERVER_NAME_INDICATION) {
+            offset += extLen; /* skip extension */
+        } else {
+            word16 listLen;
+
+            ato16(clientHello + offset, &listLen);
+            offset += OPAQUE16_LEN;
+
+            if (helloSz < offset + listLen)
+                return BUFFER_ERROR;
+
+            while (listLen > ENUM_LEN + OPAQUE16_LEN) {
+                byte   sniType = clientHello[offset++];
+                word16 sniLen;
+
+                ato16(clientHello + offset, &sniLen);
+                offset += OPAQUE16_LEN;
+
+                if (helloSz < offset + sniLen)
+                    return BUFFER_ERROR;
+
+                if (sniType != type) {
+                    offset  += sniLen;
+                    listLen -= min(ENUM_LEN + OPAQUE16_LEN + sniLen, listLen);
+                    continue;
+                }
+
+                *inOutSz = min(sniLen, *inOutSz);
+                XMEMCPY(sni, clientHello + offset, *inOutSz);
+
+                return SSL_SUCCESS;
+            }
+        }
+
+        len16 -= min(2 * OPAQUE16_LEN + extLen, len16);
+    }
+
+    return len16 ? BUFFER_ERROR : 0;
+}
+
+#endif
+
+#define SNI_FREE_ALL TLSX_SNI_FreeAll
+#define SNI_GET_SIZE TLSX_SNI_GetSize
+#define SNI_WRITE    TLSX_SNI_Write
+#define SNI_PARSE    TLSX_SNI_Parse
+
+#else
+
+#define SNI_FREE_ALL(list)
+#define SNI_GET_SIZE(list)    0
+#define SNI_WRITE(a, b)       0
+#define SNI_PARSE(a, b, c, d) 0
+
+#endif /* HAVE_SNI */
+
+#ifdef HAVE_MAX_FRAGMENT
+
+static word16 TLSX_MFL_Write(byte* data, byte* output)
+{
+    output[0] = data[0];
+
+    return ENUM_LEN;
+}
+
+static int TLSX_MFL_Parse(WOLFSSL* ssl, byte* input, word16 length,
+                                                                 byte isRequest)
+{
+    if (length != ENUM_LEN)
+        return BUFFER_ERROR;
+
+    switch (*input) {
+        case WOLFSSL_MFL_2_9 : ssl->max_fragment =  512; break;
+        case WOLFSSL_MFL_2_10: ssl->max_fragment = 1024; break;
+        case WOLFSSL_MFL_2_11: ssl->max_fragment = 2048; break;
+        case WOLFSSL_MFL_2_12: ssl->max_fragment = 4096; break;
+        case WOLFSSL_MFL_2_13: ssl->max_fragment = 8192; break;
+
+        default:
+            SendAlert(ssl, alert_fatal, illegal_parameter);
+
+            return UNKNOWN_MAX_FRAG_LEN_E;
+    }
+
+#ifndef NO_WOLFSSL_SERVER
+    if (isRequest) {
+        int r = TLSX_UseMaxFragment(&ssl->extensions, *input);
+
+        if (r != SSL_SUCCESS) return r; /* throw error */
+
+        TLSX_SetResponse(ssl, MAX_FRAGMENT_LENGTH);
+    }
+#endif
+
+    return 0;
+}
+
+int TLSX_UseMaxFragment(TLSX** extensions, byte mfl)
+{
+    byte* data = NULL;
+    int   ret  = 0;
+
+    if (extensions == NULL)
+        return BAD_FUNC_ARG;
+
+    if (mfl < WOLFSSL_MFL_2_9 || WOLFSSL_MFL_2_13 < mfl)
+        return BAD_FUNC_ARG;
+
+    if ((data = XMALLOC(ENUM_LEN, 0, DYNAMIC_TYPE_TLSX)) == NULL)
+        return MEMORY_E;
+
+    data[0] = mfl;
+
+    /* push new MFL extension. */
+    if ((ret = TLSX_Push(extensions, MAX_FRAGMENT_LENGTH, data)) != 0) {
+        XFREE(data, 0, DYNAMIC_TYPE_TLSX);
+        return ret;
+    }
+
+    return SSL_SUCCESS;
+}
+
+
+#define MFL_FREE_ALL(data) XFREE(data, 0, DYNAMIC_TYPE_TLSX)
+#define MFL_GET_SIZE(data) ENUM_LEN
+#define MFL_WRITE          TLSX_MFL_Write
+#define MFL_PARSE          TLSX_MFL_Parse
+
+#else
+
+#define MFL_FREE_ALL(a)
+#define MFL_GET_SIZE(a)       0
+#define MFL_WRITE(a, b)       0
+#define MFL_PARSE(a, b, c, d) 0
+
+#endif /* HAVE_MAX_FRAGMENT */
+
+#ifdef HAVE_TRUNCATED_HMAC
+
+static int TLSX_THM_Parse(WOLFSSL* ssl, byte* input, word16 length,
+                                                                 byte isRequest)
+{
+    if (length != 0 || input == NULL)
+        return BUFFER_ERROR;
+
+#ifndef NO_WOLFSSL_SERVER
+    if (isRequest) {
+        int r = TLSX_UseTruncatedHMAC(&ssl->extensions);
+
+        if (r != SSL_SUCCESS) return r; /* throw error */
+
+        TLSX_SetResponse(ssl, TRUNCATED_HMAC);
+    }
+#endif
+
+    ssl->truncated_hmac = 1;
+
+    return 0;
+}
+
+int TLSX_UseTruncatedHMAC(TLSX** extensions)
+{
+    int ret = 0;
+
+    if (extensions == NULL)
+        return BAD_FUNC_ARG;
+
+    if ((ret = TLSX_Push(extensions, TRUNCATED_HMAC, NULL)) != 0)
+        return ret;
+
+    return SSL_SUCCESS;
+}
+
+#define THM_PARSE TLSX_THM_Parse
+
+#else
+
+#define THM_PARSE(a, b, c, d) 0
+
+#endif /* HAVE_TRUNCATED_HMAC */
+
+#ifdef HAVE_SUPPORTED_CURVES
+
+#ifndef HAVE_ECC
+#error Elliptic Curves Extension requires Elliptic Curve Cryptography. \
+       Use --enable-ecc in the configure script or define HAVE_ECC.
+#endif
+
+static void TLSX_EllipticCurve_FreeAll(EllipticCurve* list)
+{
+    EllipticCurve* curve;
+
+    while ((curve = list)) {
+        list = curve->next;
+        XFREE(curve, 0, DYNAMIC_TYPE_TLSX);
+    }
+}
+
+static int TLSX_EllipticCurve_Append(EllipticCurve** list, word16 name)
+{
+    EllipticCurve* curve;
+
+    if (list == NULL)
+        return BAD_FUNC_ARG;
+
+    if ((curve = XMALLOC(sizeof(EllipticCurve), 0, DYNAMIC_TYPE_TLSX)) == NULL)
+        return MEMORY_E;
+
+    curve->name = name;
+    curve->next = *list;
+
+    *list = curve;
+
+    return 0;
+}
+
+#ifndef NO_WOLFSSL_CLIENT
+
+static void TLSX_EllipticCurve_ValidateRequest(WOLFSSL* ssl, byte* semaphore)
+{
+    int i;
+
+    for (i = 0; i < ssl->suites->suiteSz; i+= 2)
+        if (ssl->suites->suites[i] == ECC_BYTE)
+            return;
+
+    /* No elliptic curve suite found */
+    TURN_ON(semaphore, TLSX_ToSemaphore(ELLIPTIC_CURVES));
+}
+
+static word16 TLSX_EllipticCurve_GetSize(EllipticCurve* list)
+{
+    EllipticCurve* curve;
+    word16 length = OPAQUE16_LEN; /* list length */
+
+    while ((curve = list)) {
+        list = curve->next;
+        length += OPAQUE16_LEN; /* curve length */
+    }
+
+    return length;
+}
+
+static word16 TLSX_EllipticCurve_WriteR(EllipticCurve* curve, byte* output);
+static word16 TLSX_EllipticCurve_WriteR(EllipticCurve* curve, byte* output)
+{
+    word16 offset = 0;
+
+    if (!curve)
+        return offset;
+
+    offset = TLSX_EllipticCurve_WriteR(curve->next, output);
+    c16toa(curve->name, output + offset);
+
+    return OPAQUE16_LEN + offset;
+}
+
+static word16 TLSX_EllipticCurve_Write(EllipticCurve* list, byte* output)
+{
+    word16 length = TLSX_EllipticCurve_WriteR(list, output + OPAQUE16_LEN);
+
+    c16toa(length, output); /* writing list length */
+
+    return OPAQUE16_LEN + length;
+}
+
+#endif /* NO_WOLFSSL_CLIENT */
+#ifndef NO_WOLFSSL_SERVER
+
+static int TLSX_EllipticCurve_Parse(WOLFSSL* ssl, byte* input, word16 length,
+                                                                 byte isRequest)
+{
+    word16 offset;
+    word16 name;
+    int r;
+
+    (void) isRequest; /* shut up compiler! */
+
+    if (OPAQUE16_LEN > length || length % OPAQUE16_LEN)
+        return BUFFER_ERROR;
+
+    ato16(input, &offset);
+
+    /* validating curve list length */
+    if (length != OPAQUE16_LEN + offset)
+        return BUFFER_ERROR;
+
+    while (offset) {
+        ato16(input + offset, &name);
+        offset -= OPAQUE16_LEN;
+
+        r = TLSX_UseSupportedCurve(&ssl->extensions, name);
+
+        if (r != SSL_SUCCESS) return r; /* throw error */
+    }
+
+    return 0;
+}
+
+int TLSX_ValidateEllipticCurves(WOLFSSL* ssl, byte first, byte second) {
+    TLSX*          extension = (first == ECC_BYTE)
+                             ? TLSX_Find(ssl->extensions, ELLIPTIC_CURVES)
+                             : NULL;
+    EllipticCurve* curve     = NULL;
+    word32         oid       = 0;
+    word16         octets    = 0; /* acording to 'ecc_set_type ecc_sets[];' */
+    int            sig       = 0; /* valitade signature */
+    int            key       = 0; /* validate key       */
+
+    (void)oid;
+    (void)octets;
+
+    if (!extension)
+        return 1; /* no suite restriction */
+
+    for (curve = extension->data; curve && !(sig && key); curve = curve->next) {
+
+        switch (curve->name) {
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC160)
+            case WOLFSSL_ECC_SECP160R1: oid = ECC_160R1; octets = 20; break;
+#endif
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC192)
+            case WOLFSSL_ECC_SECP192R1: oid = ECC_192R1; octets = 24; break;
+#endif
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC224)
+            case WOLFSSL_ECC_SECP224R1: oid = ECC_224R1; octets = 28; break;
+#endif
+#if defined(HAVE_ALL_CURVES) || !defined(NO_ECC256)
+            case WOLFSSL_ECC_SECP256R1: oid = ECC_256R1; octets = 32; break;
+#endif
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC384)
+            case WOLFSSL_ECC_SECP384R1: oid = ECC_384R1; octets = 48; break;
+#endif
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC521)
+            case WOLFSSL_ECC_SECP521R1: oid = ECC_521R1; octets = 66; break;
+#endif
+            default: continue; /* unsupported curve */
+        }
+
+        switch (second) {
+#ifndef NO_DSA
+            /* ECDHE_ECDSA */
+            case TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA:
+            case TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA:
+            case TLS_ECDHE_ECDSA_WITH_RC4_128_SHA:
+            case TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA:
+            case TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256:
+            case TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384:
+            case TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256:
+            case TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384:
+            case TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8:
+            case TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8:
+                sig |= ssl->pkCurveOID == oid;
+                key |= ssl->eccTempKeySz == octets;
+            break;
+
+            /* ECDH_ECDSA */
+            case TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA:
+            case TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA:
+            case TLS_ECDH_ECDSA_WITH_RC4_128_SHA:
+            case TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA:
+            case TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256:
+            case TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384:
+            case TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256:
+            case TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384:
+                sig |= ssl->pkCurveOID == oid;
+                key |= ssl->pkCurveOID == oid;
+            break;
+#endif
+#ifndef NO_RSA
+            /* ECDHE_RSA */
+            case TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA:
+            case TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA:
+            case TLS_ECDHE_RSA_WITH_RC4_128_SHA:
+            case TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA:
+            case TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256:
+            case TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384:
+            case TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256:
+            case TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384:
+                sig = 1;
+                key |= ssl->eccTempKeySz == octets;
+            break;
+
+            /* ECDH_RSA */
+            case TLS_ECDH_RSA_WITH_AES_256_CBC_SHA:
+            case TLS_ECDH_RSA_WITH_AES_128_CBC_SHA:
+            case TLS_ECDH_RSA_WITH_RC4_128_SHA:
+            case TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA:
+            case TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256:
+            case TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384:
+            case TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256:
+            case TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384:
+                sig = 1;
+                key |= ssl->pkCurveOID == oid;
+            break;
+#endif
+            default:
+                sig = 1;
+                key = 1;
+            break;
+        }
+    }
+
+    return sig && key;
+}
+
+#endif /* NO_WOLFSSL_SERVER */
+
+int TLSX_UseSupportedCurve(TLSX** extensions, word16 name)
+{
+    TLSX*          extension = TLSX_Find(*extensions, ELLIPTIC_CURVES);
+    EllipticCurve* curve     = NULL;
+    int            ret       = 0;
+
+    if (extensions == NULL)
+        return BAD_FUNC_ARG;
+
+    if ((ret = TLSX_EllipticCurve_Append(&curve, name)) != 0)
+        return ret;
+
+    if (!extension) {
+        if ((ret = TLSX_Push(extensions, ELLIPTIC_CURVES, curve)) != 0) {
+            XFREE(curve, 0, DYNAMIC_TYPE_TLSX);
+            return ret;
+        }
+    }
+    else {
+        /* push new EllipticCurve object to extension data. */
+        curve->next = (EllipticCurve*)extension->data;
+        extension->data = (void*)curve;
+
+        /* look for another curve of the same name to remove (replacement) */
+        do {
+            if (curve->next && curve->next->name == name) {
+                EllipticCurve *next = curve->next;
+
+                curve->next = next->next;
+                XFREE(next, 0, DYNAMIC_TYPE_TLSX);
+
+                break;
+            }
+        } while ((curve = curve->next));
+    }
+
+    return SSL_SUCCESS;
+}
+
+#define EC_FREE_ALL         TLSX_EllipticCurve_FreeAll
+#define EC_VALIDATE_REQUEST TLSX_EllipticCurve_ValidateRequest
+
+#ifndef NO_WOLFSSL_CLIENT
+#define EC_GET_SIZE TLSX_EllipticCurve_GetSize
+#define EC_WRITE    TLSX_EllipticCurve_Write
+#else
+#define EC_GET_SIZE(list)         0
+#define EC_WRITE(a, b)            0
+#endif
+
+#ifndef NO_WOLFSSL_SERVER
+#define EC_PARSE TLSX_EllipticCurve_Parse
+#else
+#define EC_PARSE(a, b, c, d)      0
+#endif
+
+#else
+
+#define EC_FREE_ALL(list)
+#define EC_GET_SIZE(list)         0
+#define EC_WRITE(a, b)            0
+#define EC_PARSE(a, b, c, d)      0
+#define EC_VALIDATE_REQUEST(a, b)
+
+#endif /* HAVE_SUPPORTED_CURVES */
+
+#ifdef HAVE_SECURE_RENEGOTIATION
+
+static byte TLSX_SecureRenegotiation_GetSize(SecureRenegotiation* data,
+                                                                  int isRequest)
+{
+    byte length = OPAQUE8_LEN; /* empty info length */
+
+    if (data->enabled) {
+        /* client sends client_verify_data only */
+        length += TLS_FINISHED_SZ;
+
+        /* server also sends server_verify_data */
+        if (!isRequest)
+            length += TLS_FINISHED_SZ;
+    }
+
+    return length;
+}
+
+static word16 TLSX_SecureRenegotiation_Write(SecureRenegotiation* data,
+                                                    byte* output, int isRequest)
+{
+    word16 offset = OPAQUE8_LEN; /* RenegotiationInfo length */
+
+    if (data->enabled) {
+        /* client sends client_verify_data only */
+        XMEMCPY(output + offset, data->client_verify_data, TLS_FINISHED_SZ);
+        offset += TLS_FINISHED_SZ;
+
+        /* server also sends server_verify_data */
+        if (!isRequest) {
+            XMEMCPY(output + offset, data->server_verify_data, TLS_FINISHED_SZ);
+            offset += TLS_FINISHED_SZ;
+        }
+    }
+
+    output[0] = offset - 1;  /* info length - self */
+
+    return offset;
+}
+
+static int TLSX_SecureRenegotiation_Parse(WOLFSSL* ssl, byte* input,
+                                                  word16 length, byte isRequest)
+{
+    int ret = SECURE_RENEGOTIATION_E;
+
+    if (length >= OPAQUE8_LEN) {
+        if (ssl->secure_renegotiation == NULL) {
+        #ifndef NO_WOLFSSL_SERVER
+            if (isRequest && *input == 0) {
+                ret = 0;  /* don't reply, user didn't enable */
+            }
+        #endif
+        }
+        else if (isRequest) {
+        #ifndef NO_WOLFSSL_SERVER
+            if (*input == TLS_FINISHED_SZ) {
+                /* TODO compare client_verify_data */
+                ret = 0;
+            }
+        #endif
+        }
+        else {
+        #ifndef NO_WOLFSSL_CLIENT
+            if (!ssl->secure_renegotiation->enabled) {
+                if (*input == 0) {
+                    ssl->secure_renegotiation->enabled = 1;
+                    ret = 0;
+                }
+            }
+            else if (*input == 2 * TLS_FINISHED_SZ) {
+                /* TODO compare client_verify_data and server_verify_data */
+                ret = 0;
+            }
+        #endif
+        }
+    }
+
+    if (ret != 0) {
+        /* TODO: turn on fatal error at ssl level too */
+        SendAlert(ssl, alert_fatal, handshake_failure);
+    }
+
+    return ret;
+}
+
+int TLSX_UseSecureRenegotiation(TLSX** extensions)
+{
+    int ret = 0;
+    SecureRenegotiation* data = NULL;
+
+    data = (SecureRenegotiation*)XMALLOC(sizeof(SecureRenegotiation), NULL,
+                                                             DYNAMIC_TYPE_TLSX);
+    if (data == NULL)
+        return MEMORY_E;
+
+    XMEMSET(data, 0, sizeof(SecureRenegotiation));
+
+    ret = TLSX_Push(extensions, SECURE_RENEGOTIATION, data);
+    if (ret != 0) {
+        XFREE(data, 0, DYNAMIC_TYPE_TLSX);
+        return ret;
+    }
+
+    return SSL_SUCCESS;
+}
+
+
+#define SCR_FREE_ALL(data) XFREE(data, NULL, DYNAMIC_TYPE_TLSX)
+#define SCR_GET_SIZE       TLSX_SecureRenegotiation_GetSize
+#define SCR_WRITE          TLSX_SecureRenegotiation_Write
+#define SCR_PARSE          TLSX_SecureRenegotiation_Parse
+
+#else
+
+#define SCR_FREE_ALL(a)
+#define SCR_GET_SIZE(a, b)    0
+#define SCR_WRITE(a, b, c)    0
+#define SCR_PARSE(a, b, c, d) 0
+
+#endif /* HAVE_SECURE_RENEGOTIATION */
+
+#ifdef HAVE_SESSION_TICKET
+
+static void TLSX_SessionTicket_ValidateRequest(WOLFSSL* ssl)
+{
+    TLSX*          extension = TLSX_Find(ssl->extensions, SESSION_TICKET);
+    SessionTicket* ticket    = extension ? extension->data : NULL;
+
+    if (ticket) {
+        /* TODO validate ticket timeout here! */
+        if (ticket->lifetime == 0xfffffff) {
+            /* send empty ticket on timeout */
+            TLSX_UseSessionTicket(&ssl->extensions, NULL);
+        }
+    }
+}
+
+
+static word16 TLSX_SessionTicket_GetSize(SessionTicket* ticket, int isRequest)
+{
+    (void)isRequest;
+    return ticket ? ticket->size : 0;
+}
+
+static word16 TLSX_SessionTicket_Write(SessionTicket* ticket, byte* output,
+                                                                  int isRequest)
+{
+    word16 offset = 0; /* empty ticket */
+
+    if (isRequest && ticket) {
+        XMEMCPY(output + offset, ticket->data, ticket->size);
+        offset += ticket->size;
+    }
+
+    return offset;
+}
+
+
+static int TLSX_SessionTicket_Parse(WOLFSSL* ssl, byte* input, word16 length,
+                                                                 byte isRequest)
+{
+    int ret = 0;
+
+    if (!isRequest) {
+        /* client side */
+        if (length != 0)
+            return BUFFER_ERROR;
+
+        ssl->expect_session_ticket = 1;
+    }
+#ifndef NO_WOLFSSL_SERVER
+    else {
+        /* server side */
+        if (ssl->ctx->ticketEncCb == NULL) {
+            WOLFSSL_MSG("Client sent session ticket, server has no callback");
+            return 0;
+        }
+
+        if (length == 0) {
+            /* blank ticket */
+            ret = TLSX_UseSessionTicket(&ssl->extensions, NULL);
+            if (ret == SSL_SUCCESS) {
+                ret = 0;
+                TLSX_SetResponse(ssl, SESSION_TICKET);  /* send blank ticket */
+                ssl->options.createTicket = 1;  /* will send ticket msg */
+                ssl->options.useTicket    = 1;
+            }
+        } else {
+            /* got actual ticket from client */
+            ret = DoClientTicket(ssl, input, length);
+            if (ret == WOLFSSL_TICKET_RET_OK) {    /* use ticket to resume */
+                WOLFSSL_MSG("Using exisitng client ticket");
+                ssl->options.useTicket = 1;
+                ssl->options.resuming  = 1;
+            } else if (ret == WOLFSSL_TICKET_RET_CREATE) {
+                WOLFSSL_MSG("Using existing client ticket, creating new one");
+                ret = TLSX_UseSessionTicket(&ssl->extensions, NULL);
+                if (ret == SSL_SUCCESS) {
+                    ret = 0;
+                    TLSX_SetResponse(ssl, SESSION_TICKET);
+                                                    /* send blank ticket */
+                    ssl->options.createTicket = 1;  /* will send ticket msg */
+                    ssl->options.useTicket    = 1;
+                    ssl->options.resuming     = 1;
+                }
+            } else if (ret == WOLFSSL_TICKET_RET_REJECT) {
+                WOLFSSL_MSG("Process client ticket rejected, not using");
+                ret = 0;  /* not fatal */
+            } else if (ret == WOLFSSL_TICKET_RET_FATAL || ret < 0) {
+                WOLFSSL_MSG("Process client ticket fatal error, not using");
+            }
+        }
+    }
+#endif /* NO_WOLFSSL_SERVER */
+
+    return ret;
+}
+
+WOLFSSL_LOCAL SessionTicket* TLSX_SessionTicket_Create(word32 lifetime,
+                                                       byte* data, word16 size)
+{
+    SessionTicket* ticket = (SessionTicket*)XMALLOC(sizeof(SessionTicket),
+                                                       NULL, DYNAMIC_TYPE_TLSX);
+    if (ticket) {
+        ticket->data = (byte*)XMALLOC(size, NULL, DYNAMIC_TYPE_TLSX);
+        if (ticket->data == NULL) {
+            XFREE(ticket, NULL, DYNAMIC_TYPE_TLSX);
+            return NULL;
+        }
+
+        XMEMCPY(ticket->data, data, size);
+        ticket->size     = size;
+        ticket->lifetime = lifetime;
+    }
+
+    return ticket;
+}
+WOLFSSL_LOCAL void TLSX_SessionTicket_Free(SessionTicket* ticket)
+{
+    if (ticket) {
+        XFREE(ticket->data, NULL, DYNAMIC_TYPE_TLSX);
+        XFREE(ticket,       NULL, DYNAMIC_TYPE_TLSX);
+    }
+}
+
+int TLSX_UseSessionTicket(TLSX** extensions, SessionTicket* ticket)
+{
+    int ret = 0;
+
+    if (extensions == NULL)
+        return BAD_FUNC_ARG;
+
+    /* If the ticket is NULL, the client will request a new ticket from the
+       server. Otherwise, the client will use it in the next client hello. */
+    if ((ret = TLSX_Push(extensions, SESSION_TICKET, (void*)ticket)) != 0)
+        return ret;
+
+    return SSL_SUCCESS;
+}
+
+#define STK_VALIDATE_REQUEST TLSX_SessionTicket_ValidateRequest
+#define STK_GET_SIZE         TLSX_SessionTicket_GetSize
+#define STK_WRITE            TLSX_SessionTicket_Write
+#define STK_PARSE            TLSX_SessionTicket_Parse
+
+#else
+
+#define STK_VALIDATE_REQUEST(a)
+#define STK_GET_SIZE(a, b)      0
+#define STK_WRITE(a, b, c)      0
+#define STK_PARSE(a, b, c, d)   0
+
+#endif /* HAVE_SESSION_TICKET */
+
+
+TLSX* TLSX_Find(TLSX* list, TLSX_Type type)
+{
+    TLSX* extension = list;
+
+    while (extension && extension->type != type)
+        extension = extension->next;
+
+    return extension;
+}
+
+void TLSX_FreeAll(TLSX* list)
+{
+    TLSX* extension;
+
+    while ((extension = list)) {
+        list = extension->next;
+
+        switch (extension->type) {
+            case SERVER_NAME_INDICATION:
+                SNI_FREE_ALL((SNI*)extension->data);
+                break;
+
+            case MAX_FRAGMENT_LENGTH:
+                MFL_FREE_ALL(extension->data);
+                break;
+
+            case TRUNCATED_HMAC:
+                /* Nothing to do. */
+                break;
+
+            case ELLIPTIC_CURVES:
+                EC_FREE_ALL(extension->data);
+                break;
+
+            case SECURE_RENEGOTIATION:
+                SCR_FREE_ALL(extension->data);
+                break;
+
+            case SESSION_TICKET:
+                /* Nothing to do. */
+                break;
+        }
+
+        XFREE(extension, 0, DYNAMIC_TYPE_TLSX);
+    }
+}
+
+int TLSX_SupportExtensions(WOLFSSL* ssl) {
+    return ssl && (IsTLS(ssl) || ssl->version.major == DTLS_MAJOR);
+}
+
+static word16 TLSX_GetSize(TLSX* list, byte* semaphore, byte isRequest)
+{
+    TLSX* extension;
+    word16 length = 0;
+
+    while ((extension = list)) {
+        list = extension->next;
+
+        if (!isRequest && !extension->resp)
+            continue; /* skip! */
+
+        if (!IS_OFF(semaphore, TLSX_ToSemaphore(extension->type)))
+            continue; /* skip! */
+
+        /* type + data length */
+        length += HELLO_EXT_TYPE_SZ + OPAQUE16_LEN;
+
+        switch (extension->type) {
+            case SERVER_NAME_INDICATION:
+                if (isRequest)
+                    length += SNI_GET_SIZE(extension->data);
+                break;
+            case MAX_FRAGMENT_LENGTH:
+                length += MFL_GET_SIZE(extension->data);
+                break;
+
+            case TRUNCATED_HMAC:
+                /* empty extension. */
+                break;
+
+            case ELLIPTIC_CURVES:
+                length += EC_GET_SIZE(extension->data);
+                break;
+
+            case SECURE_RENEGOTIATION:
+                length += SCR_GET_SIZE(extension->data, isRequest);
+                break;
+
+            case SESSION_TICKET:
+                length += STK_GET_SIZE(extension->data, isRequest);
+                break;
+        }
+
+        TURN_ON(semaphore, TLSX_ToSemaphore(extension->type));
+    }
+
+    return length;
+}
+
+static word16 TLSX_Write(TLSX* list, byte* output, byte* semaphore,
+                                                                 byte isRequest)
+{
+    TLSX* extension;
+    word16 offset = 0;
+    word16 length_offset = 0;
+
+    while ((extension = list)) {
+        list = extension->next;
+
+        if (!isRequest && !extension->resp)
+            continue; /* skip! */
+
+        if (!IS_OFF(semaphore, TLSX_ToSemaphore(extension->type)))
+            continue; /* skip! */
+
+        /* extension type */
+        c16toa(extension->type, output + offset);
+        offset += HELLO_EXT_TYPE_SZ + OPAQUE16_LEN;
+        length_offset = offset;
+
+        /* extension data should be written internally */
+        switch (extension->type) {
+            case SERVER_NAME_INDICATION:
+                if (isRequest)
+                    offset += SNI_WRITE(extension->data, output + offset);
+                break;
+
+            case MAX_FRAGMENT_LENGTH:
+                offset += MFL_WRITE(extension->data, output + offset);
+                break;
+
+            case TRUNCATED_HMAC:
+                /* empty extension. */
+                break;
+
+            case ELLIPTIC_CURVES:
+                offset += EC_WRITE(extension->data, output + offset);
+                break;
+
+            case SECURE_RENEGOTIATION:
+                offset += SCR_WRITE(extension->data, output + offset,
+                                                                     isRequest);
+                break;
+
+            case SESSION_TICKET:
+                offset += STK_WRITE(extension->data, output + offset,
+                                                                     isRequest);
+                break;
+        }
+
+        /* writing extension data length */
+        c16toa(offset - length_offset, output + length_offset - OPAQUE16_LEN);
+
+        TURN_ON(semaphore, TLSX_ToSemaphore(extension->type));
+    }
+
+    return offset;
+}
+
+#ifndef NO_WOLFSSL_CLIENT
+
+word16 TLSX_GetRequestSize(WOLFSSL* ssl)
+{
+    word16 length = 0;
+
+    if (TLSX_SupportExtensions(ssl)) {
+        byte semaphore[SEMAPHORE_SIZE] = {0};
+
+        EC_VALIDATE_REQUEST(ssl, semaphore);
+        STK_VALIDATE_REQUEST(ssl);
+
+        if (ssl->extensions)
+            length += TLSX_GetSize(ssl->extensions, semaphore, 1);
+
+        if (ssl->ctx && ssl->ctx->extensions)
+            length += TLSX_GetSize(ssl->ctx->extensions, semaphore, 1);
+
+        if (IsAtLeastTLSv1_2(ssl) && ssl->suites->hashSigAlgoSz)
+            length += ssl->suites->hashSigAlgoSz + HELLO_EXT_LEN;
+    }
+
+    if (length)
+        length += OPAQUE16_LEN; /* for total length storage */
+
+    return length;
+}
+
+word16 TLSX_WriteRequest(WOLFSSL* ssl, byte* output)
+{
+    word16 offset = 0;
+
+    if (TLSX_SupportExtensions(ssl) && output) {
+        byte semaphore[SEMAPHORE_SIZE] = {0};
+
+        offset += OPAQUE16_LEN; /* extensions length */
+
+        EC_VALIDATE_REQUEST(ssl, semaphore);
+
+        if (ssl->extensions)
+            offset += TLSX_Write(ssl->extensions, output + offset,
+                                                                  semaphore, 1);
+
+        if (ssl->ctx && ssl->ctx->extensions)
+            offset += TLSX_Write(ssl->ctx->extensions, output + offset,
+                                                                  semaphore, 1);
+
+        if (IsAtLeastTLSv1_2(ssl) && ssl->suites->hashSigAlgoSz)
+        {
+            int i;
+            /* extension type */
+            c16toa(HELLO_EXT_SIG_ALGO, output + offset);
+            offset += HELLO_EXT_TYPE_SZ;
+
+            /* extension data length */
+            c16toa(OPAQUE16_LEN + ssl->suites->hashSigAlgoSz, output + offset);
+            offset += OPAQUE16_LEN;
+
+            /* sig algos length */
+            c16toa(ssl->suites->hashSigAlgoSz, output + offset);
+            offset += OPAQUE16_LEN;
+
+            /* sig algos */
+            for (i = 0; i < ssl->suites->hashSigAlgoSz; i++, offset++)
+                output[offset] = ssl->suites->hashSigAlgo[i];
+        }
+
+        if (offset > OPAQUE16_LEN)
+            c16toa(offset - OPAQUE16_LEN, output); /* extensions length */
+    }
+
+    return offset;
+}
+
+#endif /* NO_WOLFSSL_CLIENT */
+
+#ifndef NO_WOLFSSL_SERVER
+
+word16 TLSX_GetResponseSize(WOLFSSL* ssl)
+{
+    word16 length = 0;
+    byte semaphore[SEMAPHORE_SIZE] = {0};
+
+    if (TLSX_SupportExtensions(ssl))
+        length += TLSX_GetSize(ssl->extensions, semaphore, 0);
+
+    /* All the response data is set at the ssl object only, so no ctx here. */
+
+    if (length)
+        length += OPAQUE16_LEN; /* for total length storage */
+
+    return length;
+}
+
+word16 TLSX_WriteResponse(WOLFSSL *ssl, byte* output)
+{
+    word16 offset = 0;
+
+    if (TLSX_SupportExtensions(ssl) && output) {
+        byte semaphore[SEMAPHORE_SIZE] = {0};
+
+        offset += OPAQUE16_LEN; /* extensions length */
+
+        offset += TLSX_Write(ssl->extensions, output + offset, semaphore, 0);
+
+        if (offset > OPAQUE16_LEN)
+            c16toa(offset - OPAQUE16_LEN, output); /* extensions length */
+    }
+
+    return offset;
+}
+
+#endif /* NO_WOLFSSL_SERVER */
+
+int TLSX_Parse(WOLFSSL* ssl, byte* input, word16 length, byte isRequest,
+                                                                 Suites *suites)
+{
+    int ret = 0;
+    word16 offset = 0;
+
+    if (!ssl || !input || (isRequest && !suites))
+        return BAD_FUNC_ARG;
+
+    while (ret == 0 && offset < length) {
+        word16 type;
+        word16 size;
+
+        if (length - offset < HELLO_EXT_TYPE_SZ + OPAQUE16_LEN)
+            return BUFFER_ERROR;
+
+        ato16(input + offset, &type);
+        offset += HELLO_EXT_TYPE_SZ;
+
+        ato16(input + offset, &size);
+        offset += OPAQUE16_LEN;
+
+        if (offset + size > length)
+            return BUFFER_ERROR;
+
+        switch (type) {
+            case SERVER_NAME_INDICATION:
+                WOLFSSL_MSG("SNI extension received");
+
+                ret = SNI_PARSE(ssl, input + offset, size, isRequest);
+                break;
+
+            case MAX_FRAGMENT_LENGTH:
+                WOLFSSL_MSG("Max Fragment Length extension received");
+
+                ret = MFL_PARSE(ssl, input + offset, size, isRequest);
+                break;
+
+            case TRUNCATED_HMAC:
+                WOLFSSL_MSG("Truncated HMAC extension received");
+
+                ret = THM_PARSE(ssl, input + offset, size, isRequest);
+                break;
+
+            case ELLIPTIC_CURVES:
+                WOLFSSL_MSG("Elliptic Curves extension received");
+
+                ret = EC_PARSE(ssl, input + offset, size, isRequest);
+                break;
+
+            case SECURE_RENEGOTIATION:
+                WOLFSSL_MSG("Secure Renegotiation extension received");
+
+                ret = SCR_PARSE(ssl, input + offset, size, isRequest);
+                break;
+
+            case SESSION_TICKET:
+                WOLFSSL_MSG("Session Ticket extension received");
+
+                ret = STK_PARSE(ssl, input + offset, size, isRequest);
+                break;
+
+            case HELLO_EXT_SIG_ALGO:
+                if (isRequest) {
+                    /* do not mess with offset inside the switch! */
+                    if (IsAtLeastTLSv1_2(ssl)) {
+                        ato16(input + offset, &suites->hashSigAlgoSz);
+
+                        if (suites->hashSigAlgoSz > size - OPAQUE16_LEN)
+                            return BUFFER_ERROR;
+
+                        XMEMCPY(suites->hashSigAlgo,
+                                input + offset + OPAQUE16_LEN,
+                                min(suites->hashSigAlgoSz,
+                                                        HELLO_EXT_SIGALGO_MAX));
+                    }
+                } else {
+                    WOLFSSL_MSG("Servers MUST NOT send SIG ALGO extension.");
+                }
+
+                break;
+        }
+
+        /* offset should be updated here! */
+        offset += size;
+    }
+
+    return ret;
+}
+
+/* undefining semaphore macros */
+#undef IS_OFF
+#undef TURN_ON
+#undef SEMAPHORE_SIZE
+
+#endif
+
+
+#ifndef NO_WOLFSSL_CLIENT
+
+#ifndef NO_OLD_TLS
+
+    WOLFSSL_METHOD* wolfTLSv1_client_method(void)
+    {
+        WOLFSSL_METHOD* method =
+                             (WOLFSSL_METHOD*) XMALLOC(sizeof(WOLFSSL_METHOD), 0,
+                                                      DYNAMIC_TYPE_METHOD);
+        if (method)
+            InitSSL_Method(method, MakeTLSv1());
+        return method;
+    }
+
+
+    WOLFSSL_METHOD* wolfTLSv1_1_client_method(void)
+    {
+        WOLFSSL_METHOD* method =
+                              (WOLFSSL_METHOD*) XMALLOC(sizeof(WOLFSSL_METHOD), 0,
+                                                       DYNAMIC_TYPE_METHOD);
+        if (method)
+            InitSSL_Method(method, MakeTLSv1_1());
+        return method;
+    }
+
+#endif /* !NO_OLD_TLS */
+
+#ifndef NO_SHA256   /* can't use without SHA256 */
+
+    WOLFSSL_METHOD* wolfTLSv1_2_client_method(void)
+    {
+        WOLFSSL_METHOD* method =
+                              (WOLFSSL_METHOD*) XMALLOC(sizeof(WOLFSSL_METHOD), 0,
+                                                       DYNAMIC_TYPE_METHOD);
+        if (method)
+            InitSSL_Method(method, MakeTLSv1_2());
+        return method;
+    }
+
+#endif
+
+
+    WOLFSSL_METHOD* wolfSSLv23_client_method(void)
+    {
+        WOLFSSL_METHOD* method =
+                              (WOLFSSL_METHOD*) XMALLOC(sizeof(WOLFSSL_METHOD), 0,
+                                                       DYNAMIC_TYPE_METHOD);
+        if (method) {
+#ifndef NO_SHA256         /* 1.2 requires SHA256 */
+            InitSSL_Method(method, MakeTLSv1_2());
+#else
+            InitSSL_Method(method, MakeTLSv1_1());
+#endif
+#ifndef NO_OLD_TLS
+            method->downgrade = 1;
+#endif
+        }
+        return method;
+    }
+
+
+#endif /* NO_WOLFSSL_CLIENT */
+
+
+
+#ifndef NO_WOLFSSL_SERVER
+
+#ifndef NO_OLD_TLS
+
+    WOLFSSL_METHOD* wolfTLSv1_server_method(void)
+    {
+        WOLFSSL_METHOD* method =
+                              (WOLFSSL_METHOD*) XMALLOC(sizeof(WOLFSSL_METHOD), 0,
+                                                       DYNAMIC_TYPE_METHOD);
+        if (method) {
+            InitSSL_Method(method, MakeTLSv1());
+            method->side = WOLFSSL_SERVER_END;
+        }
+        return method;
+    }
+
+
+    WOLFSSL_METHOD* wolfTLSv1_1_server_method(void)
+    {
+        WOLFSSL_METHOD* method =
+                              (WOLFSSL_METHOD*) XMALLOC(sizeof(WOLFSSL_METHOD), 0,
+                                                       DYNAMIC_TYPE_METHOD);
+        if (method) {
+            InitSSL_Method(method, MakeTLSv1_1());
+            method->side = WOLFSSL_SERVER_END;
+        }
+        return method;
+    }
+
+#endif /* !NO_OLD_TLS */
+
+#ifndef NO_SHA256   /* can't use without SHA256 */
+
+    WOLFSSL_METHOD* wolfTLSv1_2_server_method(void)
+    {
+        WOLFSSL_METHOD* method =
+                              (WOLFSSL_METHOD*) XMALLOC(sizeof(WOLFSSL_METHOD), 0,
+                                                       DYNAMIC_TYPE_METHOD);
+        if (method) {
+            InitSSL_Method(method, MakeTLSv1_2());
+            method->side = WOLFSSL_SERVER_END;
+        }
+        return method;
+    }
+
+#endif
+
+
+    WOLFSSL_METHOD* wolfSSLv23_server_method(void)
+    {
+        WOLFSSL_METHOD* method =
+                              (WOLFSSL_METHOD*) XMALLOC(sizeof(WOLFSSL_METHOD), 0,
+                                                       DYNAMIC_TYPE_METHOD);
+        if (method) {
+#ifndef NO_SHA256         /* 1.2 requires SHA256 */
+            InitSSL_Method(method, MakeTLSv1_2());
+#else
+            InitSSL_Method(method, MakeTLSv1_1());
+#endif
+            method->side      = WOLFSSL_SERVER_END;
+#ifndef NO_OLD_TLS
+            method->downgrade = 1;
+#endif /* !NO_OLD_TLS */
+        }
+        return method;
+    }
+
+
+
+#endif /* NO_WOLFSSL_SERVER */
+#endif /* NO_TLS */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/sslSniffer/sslSniffer.vcproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/sslSniffer/sslSniffer.vcproj
new file mode 100644
index 0000000..f485e87
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/sslSniffer/sslSniffer.vcproj
@@ -0,0 +1,206 @@
+
+
+	
+		
+	
+	
+	
+	
+		
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+		
+		
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+		
+	
+	
+	
+	
+		
+			
+			
+		
+		
+			
+			
+		
+		
+			
+			
+		
+	
+	
+	
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/sslSniffer/sslSniffer.vcxproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/sslSniffer/sslSniffer.vcxproj
new file mode 100644
index 0000000..56404e9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/sslSniffer/sslSniffer.vcxproj
@@ -0,0 +1,187 @@
+
+
+  
+    
+      Debug
+      Win32
+    
+    
+      Debug
+      x64
+    
+    
+      Release
+      Win32
+    
+    
+      Release
+      x64
+    
+  
+  
+    {34FAE5A6-2B0F-4B55-86FE-0C43E4810F4D}
+    sslSniffer
+    Win32Proj
+  
+  
+  
+    DynamicLibrary
+    v110
+    Unicode
+    true
+  
+  
+    DynamicLibrary
+    v110
+    Unicode
+    true
+  
+  
+    DynamicLibrary
+    v110
+    Unicode
+  
+  
+    DynamicLibrary
+    v110
+    Unicode
+  
+  
+  
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+  
+    <_ProjectFileVersion>11.0.61030.0
+  
+  
+    $(SolutionDir)$(Configuration)\
+    $(Configuration)\obj\
+    true
+  
+  
+    true
+    $(SolutionDir)$(Platform)\$(Configuration)\
+    $(Platform)\$(Configuration)\obj\
+  
+  
+    $(SolutionDir)$(Configuration)\
+    $(Configuration)\obj\
+    false
+  
+  
+    false
+    $(SolutionDir)$(Platform)\$(Configuration)\
+    $(Platform)\$(Configuration)\obj\
+  
+  
+    
+      Disabled
+      ../;%(AdditionalIncludeDirectories)
+      OPENSSL_EXTRA;WOLFSSL_RIPEMD;WOLFSSL_SHA512;NO_PSK;WOLFSSL_SNIFFER;SSL_SNIFFER_EXPORTS;%(PreprocessorDefinitions)
+      true
+      EnableFastChecks
+      MultiThreadedDebugDLL
+      
+      Level3
+      EditAndContinue
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Windows
+      MachineX86
+      false
+    
+  
+  
+    
+      Disabled
+      ../;%(AdditionalIncludeDirectories)
+      OPENSSL_EXTRA;WOLFSSL_RIPEMD;WOLFSSL_SHA512;NO_PSK;WOLFSSL_SNIFFER;SSL_SNIFFER_EXPORTS;%(PreprocessorDefinitions)
+      EnableFastChecks
+      MultiThreadedDebugDLL
+      
+      
+      Level3
+      ProgramDatabase
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Windows
+    
+  
+  
+    
+      MaxSpeed
+      true
+      ../;%(AdditionalIncludeDirectories)
+      OPENSSL_EXTRA;WOLFSSL_RIPEMD;WOLFSSL_SHA512;NO_PSK;WOLFSSL_SNIFFER;SSL_SNIFFER_EXPORTS;%(PreprocessorDefinitions)
+      MultiThreadedDLL
+      true
+      
+      Level3
+      ProgramDatabase
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Windows
+      true
+      true
+      MachineX86
+      false
+    
+  
+  
+    
+      MaxSpeed
+      true
+      ../;%(AdditionalIncludeDirectories)
+      OPENSSL_EXTRA;WOLFSSL_RIPEMD;WOLFSSL_SHA512;NO_PSK;WOLFSSL_SNIFFER;SSL_SNIFFER_EXPORTS;%(PreprocessorDefinitions)
+      MultiThreadedDLL
+      true
+      
+      
+      Level3
+      ProgramDatabase
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Windows
+      true
+      true
+    
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+    
+      {73973223-5ee8-41ca-8e88-1d60e89a237b}
+      false
+    
+  
+  
+  
+  
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/sslSniffer/sslSnifferTest/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/sslSniffer/sslSnifferTest/include.am
new file mode 100644
index 0000000..222777c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/sslSniffer/sslSnifferTest/include.am
@@ -0,0 +1,14 @@
+# vim:ft=automake
+# included from Top Level Makefile.am
+# All paths should be given relative to the root
+
+if BUILD_SNIFFTEST
+noinst_PROGRAMS += sslSniffer/sslSnifferTest/snifftest
+sslSniffer_sslSnifferTest_snifftest_SOURCES = sslSniffer/sslSnifferTest/snifftest.c
+sslSniffer_sslSnifferTest_snifftest_LDADD        = src/libwolfssl.la -lpcap
+sslSniffer_sslSnifferTest_snifftest_DEPENDENCIES = src/libwolfssl.la
+endif
+EXTRA_DIST += sslSniffer/sslSniffer.vcproj
+EXTRA_DIST += sslSniffer/sslSniffer.vcxproj
+EXTRA_DIST += sslSniffer/sslSnifferTest/sslSniffTest.vcproj
+DISTCLEANFILES+= sslSniffer/sslSnifferTest/.libs/snifftest
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/sslSniffer/sslSnifferTest/snifftest.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/sslSniffer/sslSnifferTest/snifftest.c
new file mode 100644
index 0000000..8ffe24d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/sslSniffer/sslSnifferTest/snifftest.c
@@ -0,0 +1,324 @@
+/* snifftest.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifdef _WIN32
+    #define WOLFSSL_SNIFFER
+#endif
+
+#ifndef WOLFSSL_SNIFFER
+
+/* blank build */
+#include 
+#include 
+int main(void)
+{
+    printf("do ./configure --enable-sniffer to enable build support\n");
+    return EXIT_SUCCESS;
+}
+
+#else
+/* do a full build */
+
+#ifdef _MSC_VER
+	/* builds on *nix too, for scanf device and port */
+	#define _CRT_SECURE_NO_WARNINGS
+#endif
+
+#include      /* pcap stuff */
+#include          /* printf */
+#include         /* EXIT_SUCCESS */
+#include         /* strcmp */
+#include         /* signal */
+
+#include 
+
+
+#ifndef _WIN32
+    #include     /* AF_INET */
+    #include 
+#endif
+
+typedef unsigned char byte;
+
+enum {
+    ETHER_IF_FRAME_LEN = 14,   /* ethernet interface frame length */
+    NULL_IF_FRAME_LEN =   4,   /* no link interface frame length  */
+};
+
+
+pcap_t* pcap = NULL;
+pcap_if_t* alldevs = NULL;
+
+
+static void FreeAll(void)
+{
+    if (pcap)
+        pcap_close(pcap);
+    if (alldevs)
+        pcap_freealldevs(alldevs);
+#ifndef _WIN32
+    ssl_FreeSniffer();
+#endif
+}
+
+static void sig_handler(const int sig) 
+{
+    printf("SIGINT handled = %d.\n", sig);
+    FreeAll();
+    if (sig)
+        exit(EXIT_SUCCESS);
+}
+
+
+static void err_sys(const char* msg)
+{
+	fprintf(stderr, "%s\n", msg);
+    if (msg)
+	    exit(EXIT_FAILURE);
+}
+
+
+#ifdef _WIN32
+	#define SNPRINTF _snprintf
+#else
+	#define SNPRINTF snprintf
+#endif
+
+
+static char* iptos(unsigned int addr)
+{
+	static char    output[32];
+	byte *p = (byte*)&addr;
+
+	SNPRINTF(output, sizeof(output), "%d.%d.%d.%d", p[0], p[1], p[2], p[3]);
+
+	return output;
+}
+
+
+int main(int argc, char** argv)
+{
+    int          ret = 0;
+    int          hadBadPacket = 0;
+	int		     inum;
+	int		     port;
+    int          saveFile = 0;
+	int		     i = 0;
+    int          frame = ETHER_IF_FRAME_LEN; 
+    char         err[PCAP_ERRBUF_SIZE];
+	char         filter[32];
+	const char  *server = NULL;
+	struct       bpf_program fp;
+	pcap_if_t   *d;
+	pcap_addr_t *a;
+
+    signal(SIGINT, sig_handler);
+
+#ifndef _WIN32
+    ssl_InitSniffer();   /* dll load on Windows */
+#endif
+    ssl_Trace("./tracefile.txt", err);
+
+    if (argc == 1) {
+        /* normal case, user chooses device and port */
+
+	    if (pcap_findalldevs(&alldevs, err) == -1)
+		    err_sys("Error in pcap_findalldevs");
+
+	    for (d = alldevs; d; d=d->next) {
+		    printf("%d. %s", ++i, d->name);
+		    if (d->description)
+			    printf(" (%s)\n", d->description);
+		    else
+			    printf(" (No description available)\n");
+	    }
+
+	    if (i == 0)
+		    err_sys("No interfaces found! Make sure pcap or WinPcap is"
+                    " installed correctly and you have sufficient permissions");
+
+	    printf("Enter the interface number (1-%d): ", i);
+	    ret = scanf("%d", &inum);
+        if (ret != 1)
+            printf("scanf port failed\n");
+
+	    if (inum < 1 || inum > i)
+		    err_sys("Interface number out of range");
+
+	    /* Jump to the selected adapter */
+	    for (d = alldevs, i = 0; i < inum - 1; d = d->next, i++);
+
+	    pcap = pcap_create(d->name, err);
+
+        if (pcap == NULL) printf("pcap_create failed %s\n", err);
+
+	    /* get an IPv4 address */
+	    for (a = d->addresses; a; a = a->next) {
+		    switch(a->addr->sa_family)
+		    {
+			    case AF_INET:
+				    server = 
+                        iptos(((struct sockaddr_in *)a->addr)->sin_addr.s_addr);
+				    printf("server = %s\n", server);
+				    break;
+
+                default:
+                    break;
+		    }
+	    }
+	    if (server == NULL)
+		    err_sys("Unable to get device IPv4 address");
+
+        ret = pcap_set_snaplen(pcap, 65536);
+        if (ret != 0) printf("pcap_set_snaplen failed %s\n", pcap_geterr(pcap));
+
+        ret = pcap_set_timeout(pcap, 1000); 
+        if (ret != 0) printf("pcap_set_timeout failed %s\n", pcap_geterr(pcap));
+
+        ret = pcap_set_buffer_size(pcap, 1000000); 
+        if (ret != 0)
+		    printf("pcap_set_buffer_size failed %s\n", pcap_geterr(pcap));
+
+        ret = pcap_set_promisc(pcap, 1); 
+        if (ret != 0) printf("pcap_set_promisc failed %s\n", pcap_geterr(pcap));
+
+
+        ret = pcap_activate(pcap);
+        if (ret != 0) printf("pcap_activate failed %s\n", pcap_geterr(pcap));
+
+	    printf("Enter the port to scan: ");
+	    ret = scanf("%d", &port);
+        if (ret != 1)
+            printf("scanf port failed\n");
+
+	    SNPRINTF(filter, sizeof(filter), "tcp and port %d", port);
+
+	    ret = pcap_compile(pcap, &fp, filter, 0, 0);
+        if (ret != 0) printf("pcap_compile failed %s\n", pcap_geterr(pcap));
+
+        ret = pcap_setfilter(pcap, &fp);
+        if (ret != 0) printf("pcap_setfilter failed %s\n", pcap_geterr(pcap));
+
+        ret = ssl_SetPrivateKey(server, port, "../../certs/server-key.pem",
+                               FILETYPE_PEM, NULL, err);
+        if (ret != 0) {
+            printf("Please run directly from sslSniffer/sslSnifferTest dir\n");
+        }
+
+#ifdef HAVE_SNI
+        {
+            char altName[128];
+
+            printf("Enter alternate SNI: ");
+            ret = scanf("%s", altName);
+
+            if (strnlen(altName, 128) > 0) {
+                ret = ssl_SetNamedPrivateKey(altName,
+                                   server, port, "../../certs/server-key.pem",
+                                   FILETYPE_PEM, NULL, err);
+                if (ret != 0) {
+                    printf("Please run directly from "
+                           "sslSniffer/sslSnifferTest dir\n");
+                }
+            }
+        }
+#endif
+    }
+    else if (argc >= 3) {
+        saveFile = 1;
+        pcap = pcap_open_offline(argv[1], err);
+        if (pcap == NULL) {
+            printf("pcap_open_offline failed %s\n", err);
+            ret = -1;
+        }
+        else {
+            const char* passwd = NULL;
+            /* defaults for server and port */
+            port = 443;
+            server = "127.0.0.1";
+
+            if (argc >= 4)
+                server = argv[3];
+
+            if (argc >= 5)
+                port = atoi(argv[4]);
+
+            if (argc >= 6)
+                passwd = argv[5];
+
+            ret = ssl_SetPrivateKey(server, port, argv[2],
+                                    FILETYPE_PEM, passwd, err);
+        }
+    }
+    else {
+        /* usage error */
+        printf( "usage: ./snifftest or ./snifftest dump pemKey"
+                " [server] [port] [password]\n");
+        exit(EXIT_FAILURE);
+    }
+
+    if (ret != 0)
+        err_sys(err);
+
+    if (pcap_datalink(pcap) == DLT_NULL) 
+        frame = NULL_IF_FRAME_LEN;
+
+    while (1) {
+        static int packetNumber = 0;
+        struct pcap_pkthdr header;
+        const unsigned char* packet = pcap_next(pcap, &header);
+        packetNumber++;
+        if (packet) {
+
+            byte data[65535+16384];  /* may have a partial 16k record cached */
+
+            if (header.caplen > 40)  { /* min ip(20) + min tcp(20) */
+				packet        += frame;
+				header.caplen -= frame;					
+            }
+            else
+                continue;
+
+            ret = ssl_DecodePacket(packet, header.caplen, data, err);
+            if (ret < 0) {
+                printf("ssl_Decode ret = %d, %s\n", ret, err);
+                hadBadPacket = 1;
+            }
+            if (ret > 0) {
+                data[ret] = 0;
+				printf("SSL App Data(%d:%d):%s\n", packetNumber, ret, data);
+            }
+        }
+        else if (saveFile)
+            break;      /* we're done reading file */
+    }
+    FreeAll();
+
+    return hadBadPacket ? EXIT_FAILURE : EXIT_SUCCESS;
+}
+
+#endif /* full build */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/sslSniffer/sslSnifferTest/sslSniffTest.vcproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/sslSniffer/sslSnifferTest/sslSniffTest.vcproj
new file mode 100644
index 0000000..ff9977f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/sslSniffer/sslSnifferTest/sslSniffTest.vcproj
@@ -0,0 +1,199 @@
+
+
+	
+		
+	
+	
+	
+	
+		
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+		
+		
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+		
+	
+	
+	
+	
+		
+			
+			
+		
+		
+		
+		
+		
+	
+	
+	
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/stamp-h.in b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/stamp-h.in
new file mode 100644
index 0000000..e69de29
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/support/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/support/include.am
new file mode 100644
index 0000000..db3ed73
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/support/include.am
@@ -0,0 +1,10 @@
+# vim:ft=automake
+# All paths should be given relative to the root
+#
+
+EXTRA_DIST += support/wolfssl.pc
+
+pkgconfigdir = $(libdir)/pkgconfig
+pkgconfig_DATA = support/wolfssl.pc
+	     
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/support/wolfssl.pc b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/support/wolfssl.pc
new file mode 100644
index 0000000..277eb17
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/support/wolfssl.pc
@@ -0,0 +1,10 @@
+prefix=/usr/local
+exec_prefix=${prefix}
+libdir=${exec_prefix}/lib
+includedir=${prefix}/include
+
+Name: wolfssl
+Description: wolfssl C library.
+Version: 3.6.0
+Libs: -L${libdir} -lwolfssl
+Cflags: -I${includedir}
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/support/wolfssl.pc.in b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/support/wolfssl.pc.in
new file mode 100644
index 0000000..e8cb694
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/support/wolfssl.pc.in
@@ -0,0 +1,10 @@
+prefix=@prefix@
+exec_prefix=@exec_prefix@
+libdir=@libdir@
+includedir=@includedir@
+
+Name: wolfssl
+Description: wolfssl C library.
+Version: @VERSION@
+Libs: -L${libdir} -lwolfssl
+Cflags: -I${includedir}
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/PythonBuild.sh b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/PythonBuild.sh
new file mode 100644
index 0000000..ae4ac45
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/PythonBuild.sh
@@ -0,0 +1,9 @@
+#!/bin/bash
+echo
+swig -python wolfssl.i
+pythonIncludes=`python-config --includes`
+pythonLibs=`python-config --libs`
+gcc -c -fpic wolfssl_wrap.c -I$pythonIncludes
+gcc -c -fpic wolfssl_adds.c 
+gcc -shared -flat_namespace  wolfssl_adds.o  wolfssl_wrap.o -lwolfssl $pythonLibs -o _wolfssl.so
+python runme.py
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/README b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/README
new file mode 100644
index 0000000..d71cdb2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/README
@@ -0,0 +1,44 @@
+
+
+Initial swig interface file
+
+Please send questions to support@wolfssl.com
+
+
+
+**Python Support**
+
+    For Linux, OS X, or *nix
+
+1) build wolfSSL with fpic on Linux, not needed on OS X
+    ./configure --disable-shared CFLAGS=-fpic
+    make
+    sudo make install
+
+
+2) start the example server from the root directory
+    ./examples/server/server -d
+
+3) run ./PythonBuild.sh from this directory it will
+    a) build the swig wrapper file
+    b) compile the swig wrapper and wolfssl wrapper files
+    c) place them into a wolfssl shared library for python
+    d) run runme.py which will connect to the wolfSSL server, write a
+       string, then read the result and output it
+
+
+    Windows only
+
+1) Make sure the install path to wolfssl doesn't have any spaces anywhere in the
+   directory path because swig doesn't like that
+2) Have python for Windows installed, note install directory
+3) Have swigwin installed, note install directory
+4) Make sure swigwin install direcotry is added to PATH env. variable
+5) Make sure env. variables PYTHON_INCLUDE and PYTHON_LIB are set correctly e.g.
+    PYTHON_INCLUE="c:\Python26\include"
+    PYTHON_LIB="c:\Python26\libs\python26.lib"
+6) Build python_wolfssl in Release mode only, Debug build fails to find a debug
+    python library that isn't included by default
+7) The outputs _wolfssl.pyd and wolfssl.py are the wolfssl import library
+8) Can now run python runme.py from the swig directory
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/include.am
new file mode 100644
index 0000000..3bd4c09
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/include.am
@@ -0,0 +1,12 @@
+# vim:ft=automake
+# All paths should be given relative to the root
+
+EXTRA_DIST+= \
+	     swig/PythonBuild.sh \
+	     swig/README \
+	     swig/wolfssl.i \
+	     swig/wolfssl_adds.c \
+	     swig/python_wolfssl.vcproj \
+	     swig/rsasign.py \
+	     swig/runme.py
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/python_wolfssl.vcproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/python_wolfssl.vcproj
new file mode 100644
index 0000000..6af2d36
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/python_wolfssl.vcproj
@@ -0,0 +1,225 @@
+
+
+	
+		
+	
+	
+	
+	
+		
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+		
+		
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+		
+	
+	
+	
+	
+		
+			
+			
+			
+			
+		
+		
+		
+		
+		
+		
+			
+				
+			
+			
+				
+			
+		
+	
+	
+	
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/rsasign.py b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/rsasign.py
new file mode 100644
index 0000000..c1c69d0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/rsasign.py
@@ -0,0 +1,35 @@
+# file: rsasign.py
+
+import wolfssl
+
+
+# start Random Number Generator
+rng = wolfssl.GetRng()
+if rng == None:
+    print "Couldn't get an RNG"
+    exit(-1)
+
+# load RSA private key in DER format
+key = wolfssl.GetRsaPrivateKey("../certs/client-key.der")
+if key == None:
+    print "Couldn't load DER private key file"
+    exit(-1)
+
+# Make byte Arrays and fill input
+signOutput = wolfssl.byteArray(128)   # 128 allows 1024 bit private key
+signStr    = wolfssl.byteArray(25)    # input can't be larger then key size
+                                     # 64 for 512 bit 128 for 1024 bit
+wolfssl.FillSignStr(signStr, "Everybody gets Friday off", 25)
+
+# Do RSA Sign
+signedSize = wolfssl.RsaSSL_Sign(signStr, 25, signOutput, 128, key, rng)
+
+# Show output
+print "Signed Size = ", signedSize, " signed array = ", wolfssl.cdata(signOutput, signedSize)
+
+# let's verify this worked
+signVerify = wolfssl.byteArray(signedSize)
+verifySize = wolfssl.RsaSSL_Verify(signOutput, signedSize, signVerify, signedSize, key)
+
+print "Verify Size = ", verifySize, " verify array = ", wolfssl.cdata(signVerify, verifySize)
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/runme.py b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/runme.py
new file mode 100644
index 0000000..90fc431
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/runme.py
@@ -0,0 +1,43 @@
+# file: runme.py
+
+import wolfssl
+
+print ""
+print "Trying to connect to the example server -d..."
+
+wolfssl.wolfSSL_Init()
+#wolfssl.wolfSSL_Debugging_ON()
+ctx = wolfssl.wolfSSL_CTX_new(wolfssl.wolfTLSv1_2_client_method())
+if ctx == None:
+    print "Couldn't get SSL CTX for TLSv1.2"
+    exit(-1)
+
+ret = wolfssl.wolfSSL_CTX_load_verify_locations(ctx, "../certs/ca-cert.pem", None)
+if ret != wolfssl.SSL_SUCCESS:
+    print "Couldn't do SSL_CTX_load_verify_locations "
+    print "error string = ", ret
+    exit(-1)
+
+ssl = wolfssl.wolfSSL_new(ctx)
+ret = wolfssl.wolfSSL_swig_connect(ssl, "localhost", 11111)
+
+if ret != wolfssl.SSL_SUCCESS:
+    print "Couldn't do SSL connect"
+    err    = wolfssl.wolfSSL_get_error(ssl, 0)
+    if ret == -2:
+        print "tcp error, is example server running?"
+    else:
+        print "error string = ", wolfssl.wolfSSL_error_string(err)
+    exit(-1)
+
+print "...Connected"
+written = wolfssl.wolfSSL_write(ssl, "hello from python\r\n", 19)
+
+if written > 0:
+    print "Wrote ", written, " bytes"
+
+byteArray = wolfssl.byteArray(100)
+readBytes = wolfssl.wolfSSL_read(ssl, byteArray, 100)
+
+print "server reply: ", wolfssl.cdata(byteArray, readBytes)
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/wolfssl.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/wolfssl.i
new file mode 100644
index 0000000..a03e79c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/wolfssl.i
@@ -0,0 +1,63 @@
+/* wolfssl.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+%module wolfssl
+%{
+    #include 
+    #include 
+
+    /* defn adds */
+    char* wolfSSL_error_string(int err);
+    int   wolfSSL_swig_connect(WOLFSSL*, const char* server, int port);
+    RNG*  GetRng(void);
+    RsaKey* GetRsaPrivateKey(const char* file);
+    void    FillSignStr(unsigned char*, const char*, int);
+%}
+
+
+WOLFSSL_METHOD* wolfTLSv1_2_client_method(void);
+WOLFSSL_CTX*    wolfSSL_CTX_new(WOLFSSL_METHOD*);
+int             wolfSSL_CTX_load_verify_locations(WOLFSSL_CTX*, const char*, const char*);
+WOLFSSL*        wolfSSL_new(WOLFSSL_CTX*);
+int             wolfSSL_get_error(WOLFSSL*, int);
+int             wolfSSL_write(WOLFSSL*, const char*, int);
+int             wolfSSL_Debugging_ON(void);
+int             wolfSSL_Init(void);
+char*           wolfSSL_error_string(int);
+int             wolfSSL_swig_connect(WOLFSSL*, const char* server, int port);
+
+int         wc_RsaSSL_Sign(const unsigned char* in, int inLen, unsigned char* out, int outLen, RsaKey* key, RNG* rng);
+
+int         wc_RsaSSL_Verify(const unsigned char* in, int inLen, unsigned char* out, int outLen, RsaKey* key);
+
+RNG* GetRng(void);
+RsaKey* GetRsaPrivateKey(const char* file);
+void    FillSignStr(unsigned char*, const char*, int);
+
+%include carrays.i
+%include cdata.i
+%array_class(unsigned char, byteArray);
+int         wolfSSL_read(WOLFSSL*, unsigned char*, int);
+
+
+#define    SSL_FAILURE      0
+#define    SSL_SUCCESS      1
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/wolfssl_adds.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/wolfssl_adds.c
new file mode 100644
index 0000000..e12ccac
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/swig/wolfssl_adds.c
@@ -0,0 +1,234 @@
+/* wolfssl_adds.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifndef _WIN32
+    #define HAVE_CONFIG_H
+#endif
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#ifdef _WIN32
+    #include 
+    #include 
+    #ifdef TEST_IPV6            /* don't require newer SDK for IPV4 */
+	    #include 
+        #include 
+    #endif
+    #define SOCKET_T int
+#else
+    #include 
+    #include 
+    #include 
+    #include 
+    #include 
+    #include 
+    #include 
+    #include 
+    #include 
+    #include 
+    #ifdef NON_BLOCKING
+        #include 
+    #endif
+    #ifdef TEST_IPV6
+        #include 
+    #endif
+    #define SOCKET_T unsigned int
+#endif /* _WIN32 */
+
+#ifdef _MSC_VER
+    /* disable conversion warning */
+    /* 4996 warning to use MS extensions e.g., strcpy_s instead of strncpy */
+    #pragma warning(disable:4244 4996)
+#endif
+
+#if defined(__MACH__) || defined(_WIN32)
+    #ifndef _SOCKLEN_T
+        typedef int socklen_t;
+    #endif
+#endif
+
+
+/* HPUX doesn't use socklent_t for third parameter to accept */
+#if !defined(__hpux__)
+    typedef socklen_t* ACCEPT_THIRD_T;
+#else
+    typedef int*       ACCEPT_THIRD_T;
+#endif
+
+
+#ifdef _WIN32
+    #define CloseSocket(s) closesocket(s)
+    #define StartTCP() { WSADATA wsd; WSAStartup(0x0002, &wsd); }
+#else
+    #define CloseSocket(s) close(s)
+    #define StartTCP()
+#endif
+
+
+#ifdef TEST_IPV6
+    typedef struct sockaddr_in6 SOCKADDR_IN_T;
+    #define AF_INET_V    AF_INET6
+#else
+    typedef struct sockaddr_in  SOCKADDR_IN_T;
+    #define AF_INET_V    AF_INET
+#endif
+
+
+enum {
+    SSL_BLOCKING    = 2,
+    SSL_NONBLOCKING = 4
+};
+
+
+static int tcp_socket(SOCKET_T* sockfd, SOCKADDR_IN_T* addr, const char* peer,
+                       short port)
+{
+    const char* host = peer;
+
+    /* peer could be in human readable form */
+    if (isalpha(peer[0])) {
+        struct hostent* entry = gethostbyname(peer);
+
+        if (entry) {
+            struct sockaddr_in tmp;
+            memset(&tmp, 0, sizeof(struct sockaddr_in));
+            memcpy(&tmp.sin_addr.s_addr, entry->h_addr_list[0],entry->h_length);
+            host = inet_ntoa(tmp.sin_addr);
+        }
+        else
+            return -1;   /* no entry for host */
+    }
+
+    *sockfd = socket(AF_INET, SOCK_STREAM, 0);
+    memset(addr, 0, sizeof(SOCKADDR_IN_T));
+
+    addr->sin_family = AF_INET;
+    addr->sin_port = htons(port);
+    addr->sin_addr.s_addr = inet_addr(host);
+
+#ifdef SO_NOSIGPIPE
+    {
+        int on = 1;
+        socklen_t len = sizeof(on);
+        setsockopt(*sockfd, SOL_SOCKET, SO_NOSIGPIPE, &on, len);
+    }
+#endif
+
+    return 0;
+}
+
+
+static int tcp_connect(SOCKET_T* sockfd, const char* ip, short port)
+{
+    SOCKADDR_IN_T addr;
+    int ret = tcp_socket(sockfd, &addr, ip, port);
+    if (ret != 0) return ret;
+
+    if (connect(*sockfd, (const struct sockaddr*)&addr, sizeof(addr)) != 0)
+        return -2; /* can't connect */
+
+    return 0;
+}
+
+
+int wolfSSL_swig_connect(WOLFSSL* ssl, const char* server, int port)
+{
+    SOCKET_T sockfd;
+    int ret = tcp_connect(&sockfd, server, port);
+    if (ret != 0) return ret;
+
+    wolfSSL_set_fd(ssl, sockfd);
+
+    return wolfSSL_connect(ssl);
+}
+
+
+char* wolfSSL_error_string(int err)
+{
+    static char buffer[WOLFSSL_MAX_ERROR_SZ];
+
+    return wolfSSL_ERR_error_string(err, buffer);
+}
+
+
+RNG* GetRng(void)
+{
+    RNG* rng = (RNG*)malloc(sizeof(RNG));
+
+    if (rng)
+        if (wc_InitRng(rng) != 0) {
+            free(rng);
+            rng = 0;
+        }
+
+    return rng;
+}
+
+
+RsaKey* GetRsaPrivateKey(const char* keyFile)
+{
+    RsaKey* key = (RsaKey*)malloc(sizeof(RsaKey));
+
+    if (key) {
+        byte   tmp[1024];
+        size_t bytes;
+        int    ret;
+        word32 idx = 0;
+        FILE*  file = fopen(keyFile, "rb");
+
+        if (!file) {
+            free(key);
+            return 0;
+        }
+
+        bytes = fread(tmp, 1, sizeof(tmp), file);
+        fclose(file);
+        wc_InitRsaKey(key, 0);
+
+        ret = wc_RsaPrivateKeyDecode(tmp, &idx, key, (word32)bytes);
+        if (ret != 0) {
+            wc_FreeRsaKey(key);
+            free(key);
+            return 0;
+        }
+    }
+    return key;
+}
+
+
+void FillSignStr(unsigned char* dst, const char* src, int size)
+{
+    memcpy(dst, src, size);
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/api.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/api.c
new file mode 100644
index 0000000..216a9ad
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/api.c
@@ -0,0 +1,1176 @@
+/* api.c API unit tests
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+/*----------------------------------------------------------------------------*
+ | Includes
+ *----------------------------------------------------------------------------*/
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+#ifdef HAVE_ECC
+    #include    /* wc_ecc_fp_free */
+#endif
+#include 
+
+#include 
+#include   /* compatibility layer */
+#include 
+#include 
+
+/*----------------------------------------------------------------------------*
+ | Constants
+ *----------------------------------------------------------------------------*/
+
+#define TEST_SUCCESS    (1)
+#define TEST_FAIL       (0)
+
+#define testingFmt "   %s:"
+#define resultFmt  " %s\n"
+static const char* passed = "passed";
+static const char* failed = "failed";
+
+#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS)
+static const char* bogusFile  = "/dev/null";
+#endif
+
+/*----------------------------------------------------------------------------*
+ | Setup
+ *----------------------------------------------------------------------------*/
+
+static int test_wolfSSL_Init(void)
+{
+    int result;
+
+    printf(testingFmt, "wolfSSL_Init()");
+    result = wolfSSL_Init();
+    printf(resultFmt, result == SSL_SUCCESS ? passed : failed);
+
+    return result;
+}
+
+
+static int test_wolfSSL_Cleanup(void)
+{
+    int result;
+
+    printf(testingFmt, "wolfSSL_Cleanup()");
+    result = wolfSSL_Cleanup();
+    printf(resultFmt, result == SSL_SUCCESS ? passed : failed);
+
+    return result;
+}
+
+/*----------------------------------------------------------------------------*
+ | Method Allocators
+ *----------------------------------------------------------------------------*/
+
+static void test_wolfSSL_Method_Allocators(void)
+{
+    #define TEST_METHOD_ALLOCATOR(allocator, condition) \
+        do {                                            \
+            WOLFSSL_METHOD *method;                      \
+            condition(method = allocator());            \
+            XFREE(method, 0, DYNAMIC_TYPE_METHOD);      \
+        } while(0)
+
+    #define TEST_VALID_METHOD_ALLOCATOR(a) \
+            TEST_METHOD_ALLOCATOR(a, AssertNotNull)
+
+    #define TEST_INVALID_METHOD_ALLOCATOR(a) \
+            TEST_METHOD_ALLOCATOR(a, AssertNull)
+
+#ifndef NO_OLD_TLS
+    TEST_VALID_METHOD_ALLOCATOR(wolfSSLv3_server_method);
+    TEST_VALID_METHOD_ALLOCATOR(wolfSSLv3_client_method);
+    TEST_VALID_METHOD_ALLOCATOR(wolfTLSv1_server_method);
+    TEST_VALID_METHOD_ALLOCATOR(wolfTLSv1_client_method);
+    TEST_VALID_METHOD_ALLOCATOR(wolfTLSv1_1_server_method);
+    TEST_VALID_METHOD_ALLOCATOR(wolfTLSv1_1_client_method);
+#endif
+    TEST_VALID_METHOD_ALLOCATOR(wolfTLSv1_2_server_method);
+    TEST_VALID_METHOD_ALLOCATOR(wolfTLSv1_2_client_method);
+    TEST_VALID_METHOD_ALLOCATOR(wolfSSLv23_client_method);
+
+#ifdef WOLFSSL_DTLS
+    #ifndef NO_OLD_TLS
+        TEST_VALID_METHOD_ALLOCATOR(wolfDTLSv1_server_method);
+        TEST_VALID_METHOD_ALLOCATOR(wolfDTLSv1_client_method);
+    #endif
+    TEST_VALID_METHOD_ALLOCATOR(wolfDTLSv1_2_server_method);
+    TEST_VALID_METHOD_ALLOCATOR(wolfDTLSv1_2_client_method);
+#endif
+
+#ifdef OPENSSL_EXTRA
+    TEST_INVALID_METHOD_ALLOCATOR(wolfSSLv2_server_method);
+    TEST_INVALID_METHOD_ALLOCATOR(wolfSSLv2_client_method);
+#endif
+}
+
+/*----------------------------------------------------------------------------*
+ | Context
+ *----------------------------------------------------------------------------*/
+
+static void test_wolfSSL_CTX_new(WOLFSSL_METHOD *method)
+{
+    WOLFSSL_CTX *ctx;
+    
+    AssertNull(ctx = wolfSSL_CTX_new(NULL));
+    
+    AssertNotNull(method);
+    AssertNotNull(ctx = wolfSSL_CTX_new(method));
+
+    wolfSSL_CTX_free(ctx);
+}
+
+
+static void test_wolfSSL_CTX_use_certificate_file(void)
+{
+#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS)
+    WOLFSSL_CTX *ctx;
+
+    AssertNotNull(ctx = wolfSSL_CTX_new(wolfSSLv23_server_method()));
+
+    /* invalid context */
+    AssertFalse(wolfSSL_CTX_use_certificate_file(NULL, svrCert, 
+                                                             SSL_FILETYPE_PEM));
+    /* invalid cert file */
+    AssertFalse(wolfSSL_CTX_use_certificate_file(ctx, bogusFile, 
+                                                             SSL_FILETYPE_PEM));
+    /* invalid cert type */
+    AssertFalse(wolfSSL_CTX_use_certificate_file(ctx, svrCert, 9999));
+
+#ifdef NO_RSA
+    /* rsa needed */
+    AssertFalse(wolfSSL_CTX_use_certificate_file(ctx, svrCert,SSL_FILETYPE_PEM));
+#else
+    /* success */
+    AssertTrue(wolfSSL_CTX_use_certificate_file(ctx, svrCert, SSL_FILETYPE_PEM));
+#endif
+
+    wolfSSL_CTX_free(ctx);
+#endif
+}
+
+
+static void test_wolfSSL_CTX_use_PrivateKey_file(void)
+{
+#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS)
+    WOLFSSL_CTX *ctx;
+
+    AssertNotNull(ctx = wolfSSL_CTX_new(wolfSSLv23_server_method()));
+
+    /* invalid context */
+    AssertFalse(wolfSSL_CTX_use_PrivateKey_file(NULL, svrKey, 
+                                                             SSL_FILETYPE_PEM));
+    /* invalid key file */
+    AssertFalse(wolfSSL_CTX_use_PrivateKey_file(ctx, bogusFile, 
+                                                             SSL_FILETYPE_PEM));
+    /* invalid key type */
+    AssertFalse(wolfSSL_CTX_use_PrivateKey_file(ctx, svrKey, 9999));
+
+    /* success */
+#ifdef NO_RSA
+    /* rsa needed */
+    AssertFalse(wolfSSL_CTX_use_PrivateKey_file(ctx, svrKey, SSL_FILETYPE_PEM));
+#else
+    /* success */
+    AssertTrue(wolfSSL_CTX_use_PrivateKey_file(ctx, svrKey, SSL_FILETYPE_PEM));
+#endif
+
+    wolfSSL_CTX_free(ctx);
+#endif
+}
+
+
+static void test_wolfSSL_CTX_load_verify_locations(void)
+{
+#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS)
+    WOLFSSL_CTX *ctx;
+
+    AssertNotNull(ctx = wolfSSL_CTX_new(wolfSSLv23_client_method()));
+    
+    /* invalid context */
+    AssertFalse(wolfSSL_CTX_load_verify_locations(NULL, caCert, 0));
+
+    /* invalid ca file */
+    AssertFalse(wolfSSL_CTX_load_verify_locations(ctx, NULL,      0));
+    AssertFalse(wolfSSL_CTX_load_verify_locations(ctx, bogusFile, 0));
+
+#ifndef WOLFSSL_TIRTOS
+    /* invalid path */
+    /* not working... investigate! */
+    /* AssertFalse(wolfSSL_CTX_load_verify_locations(ctx, caCert, bogusFile)); */
+#endif
+
+    /* success */
+    AssertTrue(wolfSSL_CTX_load_verify_locations(ctx, caCert, 0));
+
+    wolfSSL_CTX_free(ctx);
+#endif
+}
+
+/*----------------------------------------------------------------------------*
+ | SSL
+ *----------------------------------------------------------------------------*/
+
+static void test_server_wolfSSL_new(void)
+{
+#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS) && !defined(NO_RSA)
+    WOLFSSL_CTX *ctx;
+    WOLFSSL_CTX *ctx_nocert;
+    WOLFSSL *ssl;
+
+    AssertNotNull(ctx_nocert = wolfSSL_CTX_new(wolfSSLv23_server_method()));
+    AssertNotNull(ctx        = wolfSSL_CTX_new(wolfSSLv23_server_method()));
+
+    AssertTrue(wolfSSL_CTX_use_certificate_file(ctx, svrCert, SSL_FILETYPE_PEM));
+    AssertTrue(wolfSSL_CTX_use_PrivateKey_file(ctx, svrKey, SSL_FILETYPE_PEM));
+
+    /* invalid context */
+    AssertNull(ssl = wolfSSL_new(NULL));
+    AssertNull(ssl = wolfSSL_new(ctx_nocert));
+
+    /* success */
+    AssertNotNull(ssl = wolfSSL_new(ctx));
+
+    wolfSSL_free(ssl);
+    wolfSSL_CTX_free(ctx);
+    wolfSSL_CTX_free(ctx_nocert);
+#endif
+}
+
+
+static void test_client_wolfSSL_new(void)
+{
+#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS) && !defined(NO_RSA)
+    WOLFSSL_CTX *ctx;
+    WOLFSSL_CTX *ctx_nocert;
+    WOLFSSL *ssl;
+
+    AssertNotNull(ctx_nocert = wolfSSL_CTX_new(wolfSSLv23_client_method()));
+    AssertNotNull(ctx        = wolfSSL_CTX_new(wolfSSLv23_client_method()));
+
+    AssertTrue(wolfSSL_CTX_load_verify_locations(ctx, caCert, 0));
+    
+    /* invalid context */
+    AssertNull(ssl = wolfSSL_new(NULL));
+
+    /* success */
+    AssertNotNull(ssl = wolfSSL_new(ctx_nocert));
+    wolfSSL_free(ssl);
+    
+    /* success */
+    AssertNotNull(ssl = wolfSSL_new(ctx));
+    wolfSSL_free(ssl);
+    
+    wolfSSL_CTX_free(ctx);
+    wolfSSL_CTX_free(ctx_nocert);
+#endif
+}
+
+/*----------------------------------------------------------------------------*
+ | IO
+ *----------------------------------------------------------------------------*/
+#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS) && \
+    !defined(NO_RSA)        && !defined(SINGLE_THREADED)
+#define HAVE_IO_TESTS_DEPENDENCIES
+#endif
+
+/* helper functions */
+#ifdef HAVE_IO_TESTS_DEPENDENCIES
+static THREAD_RETURN WOLFSSL_THREAD test_server_nofail(void* args)
+{
+    SOCKET_T sockfd = 0;
+    SOCKET_T clientfd = 0;
+    word16 port = wolfSSLPort;
+
+    WOLFSSL_METHOD* method = 0;
+    WOLFSSL_CTX* ctx = 0;
+    WOLFSSL* ssl = 0;
+
+    char msg[] = "I hear you fa shizzle!";
+    char input[1024];
+    int idx;
+
+#ifdef WOLFSSL_TIRTOS
+    fdOpenSession(Task_self());
+#endif
+
+    ((func_args*)args)->return_code = TEST_FAIL;
+    method = wolfSSLv23_server_method();
+    ctx = wolfSSL_CTX_new(method);
+
+#if defined(NO_MAIN_DRIVER) && !defined(USE_WINDOWS_API) && \
+   !defined(WOLFSSL_SNIFFER) && !defined(WOLFSSL_MDK_SHELL) && \
+   !defined(WOLFSSL_TIRTOS)
+    port = 0;
+#endif
+
+    wolfSSL_CTX_set_verify(ctx,
+                          SSL_VERIFY_PEER | SSL_VERIFY_FAIL_IF_NO_PEER_CERT, 0);
+
+#ifdef OPENSSL_EXTRA
+    wolfSSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack);
+#endif
+
+    if (wolfSSL_CTX_load_verify_locations(ctx, cliCert, 0) != SSL_SUCCESS)
+    {
+        /*err_sys("can't load ca file, Please run from wolfSSL home dir");*/
+        goto done;
+    }
+    if (wolfSSL_CTX_use_certificate_file(ctx, svrCert, SSL_FILETYPE_PEM)
+            != SSL_SUCCESS)
+    {
+        /*err_sys("can't load server cert chain file, "
+                "Please run from wolfSSL home dir");*/
+        goto done;
+    }
+    if (wolfSSL_CTX_use_PrivateKey_file(ctx, svrKey, SSL_FILETYPE_PEM)
+            != SSL_SUCCESS)
+    {
+        /*err_sys("can't load server key file, "
+                "Please run from wolfSSL home dir");*/
+        goto done;
+    }
+    
+    ssl = wolfSSL_new(ctx);
+    tcp_accept(&sockfd, &clientfd, (func_args*)args, port, 0, 0, 0);
+    CloseSocket(sockfd);
+
+    wolfSSL_set_fd(ssl, clientfd);
+
+#ifdef NO_PSK
+    #if !defined(NO_FILESYSTEM) && !defined(NO_DH)
+        wolfSSL_SetTmpDH_file(ssl, dhParam, SSL_FILETYPE_PEM);
+    #elif !defined(NO_DH)
+        SetDH(ssl);  /* will repick suites with DHE, higher priority than PSK */
+    #endif
+#endif
+
+    if (wolfSSL_accept(ssl) != SSL_SUCCESS)
+    {
+        int err = wolfSSL_get_error(ssl, 0);
+        char buffer[WOLFSSL_MAX_ERROR_SZ];
+        printf("error = %d, %s\n", err, wolfSSL_ERR_error_string(err, buffer));
+        /*err_sys("SSL_accept failed");*/
+        goto done;
+    }
+
+    idx = wolfSSL_read(ssl, input, sizeof(input)-1);
+    if (idx > 0) {
+        input[idx] = 0;
+        printf("Client message: %s\n", input);
+    }
+    
+    if (wolfSSL_write(ssl, msg, sizeof(msg)) != sizeof(msg))
+    {
+        /*err_sys("SSL_write failed");*/
+#ifdef WOLFSSL_TIRTOS
+        return;
+#else
+        return 0;
+#endif
+    }
+
+#ifdef WOLFSSL_TIRTOS
+    Task_yield();
+#endif
+
+done:
+    wolfSSL_shutdown(ssl);
+    wolfSSL_free(ssl);
+    wolfSSL_CTX_free(ctx);
+    
+    CloseSocket(clientfd);
+    ((func_args*)args)->return_code = TEST_SUCCESS;
+
+#ifdef WOLFSSL_TIRTOS
+    fdCloseSession(Task_self());
+#endif
+
+#if defined(NO_MAIN_DRIVER) && defined(HAVE_ECC) && defined(FP_ECC) \
+                            && defined(HAVE_THREAD_LS)
+    wc_ecc_fp_free();  /* free per thread cache */
+#endif
+
+#ifndef WOLFSSL_TIRTOS
+    return 0;
+#endif
+}
+
+
+static void test_client_nofail(void* args)
+{
+    SOCKET_T sockfd = 0;
+
+    WOLFSSL_METHOD*  method  = 0;
+    WOLFSSL_CTX*     ctx     = 0;
+    WOLFSSL*         ssl     = 0;
+
+    char msg[64] = "hello wolfssl!";
+    char reply[1024];
+    int  input;
+    int  msgSz = (int)strlen(msg);
+
+#ifdef WOLFSSL_TIRTOS
+    fdOpenSession(Task_self());
+#endif
+
+    ((func_args*)args)->return_code = TEST_FAIL;
+    method = wolfSSLv23_client_method();
+    ctx = wolfSSL_CTX_new(method);
+
+#ifdef OPENSSL_EXTRA
+    wolfSSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack);
+#endif
+
+    if (wolfSSL_CTX_load_verify_locations(ctx, caCert, 0) != SSL_SUCCESS)
+    {
+        /* err_sys("can't load ca file, Please run from wolfSSL home dir");*/
+        goto done2;
+    }
+    if (wolfSSL_CTX_use_certificate_file(ctx, cliCert, SSL_FILETYPE_PEM)
+            != SSL_SUCCESS)
+    {
+        /*err_sys("can't load client cert file, "
+                "Please run from wolfSSL home dir");*/
+        goto done2;
+    }
+    if (wolfSSL_CTX_use_PrivateKey_file(ctx, cliKey, SSL_FILETYPE_PEM)
+            != SSL_SUCCESS)
+    {
+        /*err_sys("can't load client key file, "
+                "Please run from wolfSSL home dir");*/
+        goto done2;
+    }
+
+    tcp_connect(&sockfd, wolfSSLIP, ((func_args*)args)->signal->port, 0);
+
+    ssl = wolfSSL_new(ctx);
+    wolfSSL_set_fd(ssl, sockfd);
+    if (wolfSSL_connect(ssl) != SSL_SUCCESS)
+    {
+        int  err = wolfSSL_get_error(ssl, 0);
+        char buffer[WOLFSSL_MAX_ERROR_SZ];
+        printf("err = %d, %s\n", err, wolfSSL_ERR_error_string(err, buffer));
+        /*printf("SSL_connect failed");*/
+        goto done2;
+    }
+
+    if (wolfSSL_write(ssl, msg, msgSz) != msgSz)
+    {
+        /*err_sys("SSL_write failed");*/
+        goto done2;
+    }
+
+    input = wolfSSL_read(ssl, reply, sizeof(reply)-1);
+    if (input > 0)
+    {
+        reply[input] = 0;
+        printf("Server response: %s\n", reply);
+    }
+
+done2:
+    wolfSSL_free(ssl);
+    wolfSSL_CTX_free(ctx);
+    
+    CloseSocket(sockfd);
+    ((func_args*)args)->return_code = TEST_SUCCESS;
+
+#ifdef WOLFSSL_TIRTOS
+    fdCloseSession(Task_self());
+#endif
+
+    return;
+}
+
+/* SNI helper functions */
+#ifdef HAVE_SNI
+
+static THREAD_RETURN WOLFSSL_THREAD run_wolfssl_server(void* args)
+{
+    callback_functions* callbacks = ((func_args*)args)->callbacks;
+
+    WOLFSSL_CTX* ctx = wolfSSL_CTX_new(callbacks->method());
+    WOLFSSL*     ssl = NULL;
+    SOCKET_T    sfd = 0;
+    SOCKET_T    cfd = 0;
+    word16      port = wolfSSLPort;
+
+    char msg[] = "I hear you fa shizzle!";
+    int  len   = (int) XSTRLEN(msg);
+    char input[1024];
+    int  idx;
+
+#ifdef WOLFSSL_TIRTOS
+    fdOpenSession(Task_self());
+#endif
+    ((func_args*)args)->return_code = TEST_FAIL;
+
+#if defined(NO_MAIN_DRIVER) && !defined(USE_WINDOWS_API) && \
+   !defined(WOLFSSL_SNIFFER) && !defined(WOLFSSL_MDK_SHELL) && \
+   !defined(WOLFSSL_TIRTOS)
+    port = 0;
+#endif
+
+    wolfSSL_CTX_set_verify(ctx,
+                          SSL_VERIFY_PEER | SSL_VERIFY_FAIL_IF_NO_PEER_CERT, 0);
+
+#ifdef OPENSSL_EXTRA
+    wolfSSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack);
+#endif
+
+
+    AssertIntEQ(SSL_SUCCESS, wolfSSL_CTX_load_verify_locations(ctx, cliCert, 0));
+
+    AssertIntEQ(SSL_SUCCESS,
+               wolfSSL_CTX_use_certificate_file(ctx, svrCert, SSL_FILETYPE_PEM));
+
+    AssertIntEQ(SSL_SUCCESS,
+                 wolfSSL_CTX_use_PrivateKey_file(ctx, svrKey, SSL_FILETYPE_PEM));
+
+    if (callbacks->ctx_ready)
+        callbacks->ctx_ready(ctx);
+
+    ssl = wolfSSL_new(ctx);
+
+    tcp_accept(&sfd, &cfd, (func_args*)args, port, 0, 0, 0);
+    CloseSocket(sfd);
+
+    wolfSSL_set_fd(ssl, cfd);
+
+#ifdef NO_PSK
+    #if !defined(NO_FILESYSTEM) && !defined(NO_DH)
+        wolfSSL_SetTmpDH_file(ssl, dhParam, SSL_FILETYPE_PEM);
+    #elif !defined(NO_DH)
+        SetDH(ssl);  /* will repick suites with DHE, higher priority than PSK */
+    #endif
+#endif
+
+    if (callbacks->ssl_ready)
+        callbacks->ssl_ready(ssl);
+
+    /* AssertIntEQ(SSL_SUCCESS, wolfSSL_accept(ssl)); */
+    if (wolfSSL_accept(ssl) != SSL_SUCCESS) {
+        int err = wolfSSL_get_error(ssl, 0);
+        char buffer[WOLFSSL_MAX_ERROR_SZ];
+        printf("error = %d, %s\n", err, wolfSSL_ERR_error_string(err, buffer));
+
+    } else {
+        if (0 < (idx = wolfSSL_read(ssl, input, sizeof(input)-1))) {
+            input[idx] = 0;
+            printf("Client message: %s\n", input);
+        }
+
+        AssertIntEQ(len, wolfSSL_write(ssl, msg, len));
+#ifdef WOLFSSL_TIRTOS
+        Task_yield();
+#endif
+        wolfSSL_shutdown(ssl);
+    }
+
+    if (callbacks->on_result)
+        callbacks->on_result(ssl);
+
+    wolfSSL_free(ssl);
+    wolfSSL_CTX_free(ctx);
+    CloseSocket(cfd);
+
+    ((func_args*)args)->return_code = TEST_SUCCESS;
+
+#ifdef WOLFSSL_TIRTOS
+    fdCloseSession(Task_self());
+#endif
+
+#if defined(NO_MAIN_DRIVER) && defined(HAVE_ECC) && defined(FP_ECC) \
+                            && defined(HAVE_THREAD_LS)
+    wc_ecc_fp_free();  /* free per thread cache */
+#endif
+
+#ifndef WOLFSSL_TIRTOS
+    return 0;
+#endif
+}
+
+
+static void run_wolfssl_client(void* args)
+{
+    callback_functions* callbacks = ((func_args*)args)->callbacks;
+
+    WOLFSSL_CTX* ctx = wolfSSL_CTX_new(callbacks->method());
+    WOLFSSL*     ssl = NULL;
+    SOCKET_T    sfd = 0;
+
+    char msg[] = "hello wolfssl server!";
+    int  len   = (int) XSTRLEN(msg);
+    char input[1024];
+    int  idx;
+
+#ifdef WOLFSSL_TIRTOS
+    fdOpenSession(Task_self());
+#endif
+
+    ((func_args*)args)->return_code = TEST_FAIL;
+
+#ifdef OPENSSL_EXTRA
+    wolfSSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack);
+#endif
+
+    AssertIntEQ(SSL_SUCCESS, wolfSSL_CTX_load_verify_locations(ctx, caCert, 0));
+
+    AssertIntEQ(SSL_SUCCESS,
+               wolfSSL_CTX_use_certificate_file(ctx, cliCert, SSL_FILETYPE_PEM));
+
+    AssertIntEQ(SSL_SUCCESS,
+                 wolfSSL_CTX_use_PrivateKey_file(ctx, cliKey, SSL_FILETYPE_PEM));
+
+    if (callbacks->ctx_ready)
+        callbacks->ctx_ready(ctx);
+
+    tcp_connect(&sfd, wolfSSLIP, ((func_args*)args)->signal->port, 0);
+
+    ssl = wolfSSL_new(ctx);
+    wolfSSL_set_fd(ssl, sfd);
+
+    if (callbacks->ssl_ready)
+        callbacks->ssl_ready(ssl);
+
+    if (wolfSSL_connect(ssl) != SSL_SUCCESS) {
+        int err = wolfSSL_get_error(ssl, 0);
+        char buffer[WOLFSSL_MAX_ERROR_SZ];
+        printf("error = %d, %s\n", err, wolfSSL_ERR_error_string(err, buffer));
+
+    } else {
+        AssertIntEQ(len, wolfSSL_write(ssl, msg, len));
+
+        if (0 < (idx = wolfSSL_read(ssl, input, sizeof(input)-1))) {
+            input[idx] = 0;
+            printf("Server response: %s\n", input);
+        }
+    }
+
+    if (callbacks->on_result)
+        callbacks->on_result(ssl);
+
+    wolfSSL_free(ssl);
+    wolfSSL_CTX_free(ctx);
+    CloseSocket(sfd);
+    ((func_args*)args)->return_code = TEST_SUCCESS;
+
+#ifdef WOLFSSL_TIRTOS
+    fdCloseSession(Task_self());
+#endif
+}
+
+#endif /* HAVE_SNI */
+#endif /* io tests dependencies */
+
+
+static void test_wolfSSL_read_write(void)
+{
+#ifdef HAVE_IO_TESTS_DEPENDENCIES
+    /* The unit testing for read and write shall happen simutaneously, since
+     * one can't do anything with one without the other. (Except for a failure
+     * test case.) This function will call all the others that will set up,
+     * execute, and report their test findings.
+     *
+     * Set up the success case first. This function will become the template
+     * for the other tests. This should eventually be renamed
+     *
+     * The success case isn't interesting, how can this fail?
+     * - Do not give the client context a CA certificate. The connect should
+     *   fail. Do not need server for this?
+     * - Using NULL for the ssl object on server. Do not need client for this.
+     * - Using NULL for the ssl object on client. Do not need server for this.
+     * - Good ssl objects for client and server. Client write() without server
+     *   read().
+     * - Good ssl objects for client and server. Server write() without client
+     *   read().
+     * - Forgetting the password callback?
+    */
+    tcp_ready ready;
+    func_args client_args;
+    func_args server_args;
+    THREAD_TYPE serverThread;
+
+#ifdef WOLFSSL_TIRTOS
+    fdOpenSession(Task_self());
+#endif
+
+    StartTCP();
+    InitTcpReady(&ready);
+    
+    server_args.signal = &ready;
+    client_args.signal = &ready;
+    
+    start_thread(test_server_nofail, &server_args, &serverThread);
+    wait_tcp_ready(&server_args);
+    test_client_nofail(&client_args);
+    join_thread(serverThread);
+
+    AssertTrue(client_args.return_code);
+    AssertTrue(server_args.return_code);
+
+    FreeTcpReady(&ready);
+
+#ifdef WOLFSSL_TIRTOS
+    fdOpenSession(Task_self());
+#endif
+
+#endif
+}
+
+/*----------------------------------------------------------------------------*
+ | TLS extensions tests
+ *----------------------------------------------------------------------------*/
+
+#ifdef HAVE_SNI
+static void use_SNI_at_ctx(WOLFSSL_CTX* ctx)
+{
+    byte type = WOLFSSL_SNI_HOST_NAME;
+    char name[] = "www.yassl.com";
+
+    AssertIntEQ(SSL_SUCCESS,
+                    wolfSSL_CTX_UseSNI(ctx, type, (void *) name, XSTRLEN(name)));
+}
+
+static void use_SNI_at_ssl(WOLFSSL* ssl)
+{
+    byte type = WOLFSSL_SNI_HOST_NAME;
+    char name[] = "www.yassl.com";
+
+    AssertIntEQ(SSL_SUCCESS,
+                        wolfSSL_UseSNI(ssl, type, (void *) name, XSTRLEN(name)));
+}
+
+static void different_SNI_at_ssl(WOLFSSL* ssl)
+{
+    byte type = WOLFSSL_SNI_HOST_NAME;
+    char name[] = "ww2.yassl.com";
+
+    AssertIntEQ(SSL_SUCCESS,
+                        wolfSSL_UseSNI(ssl, type, (void *) name, XSTRLEN(name)));
+}
+
+static void use_SNI_WITH_CONTINUE_at_ssl(WOLFSSL* ssl)
+{
+    byte type = WOLFSSL_SNI_HOST_NAME;
+
+    use_SNI_at_ssl(ssl);
+
+    wolfSSL_SNI_SetOptions(ssl, type, WOLFSSL_SNI_CONTINUE_ON_MISMATCH);
+}
+
+static void use_SNI_WITH_FAKE_ANSWER_at_ssl(WOLFSSL* ssl)
+{
+    byte type = WOLFSSL_SNI_HOST_NAME;
+
+    use_SNI_at_ssl(ssl);
+
+    wolfSSL_SNI_SetOptions(ssl, type, WOLFSSL_SNI_ANSWER_ON_MISMATCH);
+}
+
+static void verify_SNI_abort_on_client(WOLFSSL* ssl)
+{
+    AssertIntEQ(FATAL_ERROR, wolfSSL_get_error(ssl, 0));
+}
+
+static void verify_SNI_abort_on_server(WOLFSSL* ssl)
+{
+    AssertIntEQ(UNKNOWN_SNI_HOST_NAME_E, wolfSSL_get_error(ssl, 0));
+}
+
+static void verify_SNI_no_matching(WOLFSSL* ssl)
+{
+    byte  type    = WOLFSSL_SNI_HOST_NAME;
+    char* request = (char*) &type; /* to be overwriten */
+
+    AssertIntEQ(WOLFSSL_SNI_NO_MATCH, wolfSSL_SNI_Status(ssl, type));
+
+    AssertNotNull(request);
+    AssertIntEQ(0, wolfSSL_SNI_GetRequest(ssl, type, (void**) &request));
+    AssertNull(request);
+}
+
+static void verify_SNI_real_matching(WOLFSSL* ssl)
+{
+    byte   type    = WOLFSSL_SNI_HOST_NAME;
+    char*  request = NULL;
+    char   name[]  = "www.yassl.com";
+    word16 length  = XSTRLEN(name);
+
+    AssertIntEQ(WOLFSSL_SNI_REAL_MATCH, wolfSSL_SNI_Status(ssl, type));
+
+    AssertIntEQ(length, wolfSSL_SNI_GetRequest(ssl, type, (void**) &request));
+    AssertNotNull(request);
+    AssertStrEQ(name, request);
+}
+
+static void verify_SNI_fake_matching(WOLFSSL* ssl)
+{
+    byte   type    = WOLFSSL_SNI_HOST_NAME;
+    char*  request = NULL;
+    char   name[]  = "ww2.yassl.com";
+    word16 length  = XSTRLEN(name);
+
+    AssertIntEQ(WOLFSSL_SNI_FAKE_MATCH, wolfSSL_SNI_Status(ssl, type));
+
+    AssertIntEQ(length, wolfSSL_SNI_GetRequest(ssl, type, (void**) &request));
+    AssertNotNull(request);
+    AssertStrEQ(name, request);
+}
+
+static void test_wolfSSL_SNI_GetFromBuffer(void)
+{
+    byte buffer[] = { /* www.paypal.com */
+        0x00, 0x00, 0x00, 0x00, 0xff, 0x01, 0x00, 0x00, 0x60, 0x03, 0x03, 0x5c,
+        0xc4, 0xb3, 0x8c, 0x87, 0xef, 0xa4, 0x09, 0xe0, 0x02, 0xab, 0x86, 0xca,
+        0x76, 0xf0, 0x9e, 0x01, 0x65, 0xf6, 0xa6, 0x06, 0x13, 0x1d, 0x0f, 0xa5,
+        0x79, 0xb0, 0xd4, 0x77, 0x22, 0xeb, 0x1a, 0x00, 0x00, 0x16, 0x00, 0x6b,
+        0x00, 0x67, 0x00, 0x39, 0x00, 0x33, 0x00, 0x3d, 0x00, 0x3c, 0x00, 0x35,
+        0x00, 0x2f, 0x00, 0x05, 0x00, 0x04, 0x00, 0x0a, 0x01, 0x00, 0x00, 0x21,
+        0x00, 0x00, 0x00, 0x13, 0x00, 0x11, 0x00, 0x00, 0x0e, 0x77, 0x77, 0x77,
+        0x2e, 0x70, 0x61, 0x79, 0x70, 0x61, 0x6c, 0x2e, 0x63, 0x6f, 0x6d, 0x00,
+        0x0d, 0x00, 0x06, 0x00, 0x04, 0x04, 0x01, 0x02, 0x01
+    };
+
+    byte buffer2[] = { /* api.textmate.org */
+        0x16, 0x03, 0x01, 0x00, 0xc6, 0x01, 0x00, 0x00, 0xc2, 0x03, 0x03, 0x52,
+        0x8b, 0x7b, 0xca, 0x69, 0xec, 0x97, 0xd5, 0x08, 0x03, 0x50, 0xfe, 0x3b,
+        0x99, 0xc3, 0x20, 0xce, 0xa5, 0xf6, 0x99, 0xa5, 0x71, 0xf9, 0x57, 0x7f,
+        0x04, 0x38, 0xf6, 0x11, 0x0b, 0xb8, 0xd3, 0x00, 0x00, 0x5e, 0x00, 0xff,
+        0xc0, 0x24, 0xc0, 0x23, 0xc0, 0x0a, 0xc0, 0x09, 0xc0, 0x07, 0xc0, 0x08,
+        0xc0, 0x28, 0xc0, 0x27, 0xc0, 0x14, 0xc0, 0x13, 0xc0, 0x11, 0xc0, 0x12,
+        0xc0, 0x26, 0xc0, 0x25, 0xc0, 0x2a, 0xc0, 0x29, 0xc0, 0x05, 0xc0, 0x04,
+        0xc0, 0x02, 0xc0, 0x03, 0xc0, 0x0f, 0xc0, 0x0e, 0xc0, 0x0c, 0xc0, 0x0d,
+        0x00, 0x3d, 0x00, 0x3c, 0x00, 0x2f, 0x00, 0x05, 0x00, 0x04, 0x00, 0x35,
+        0x00, 0x0a, 0x00, 0x67, 0x00, 0x6b, 0x00, 0x33, 0x00, 0x39, 0x00, 0x16,
+        0x00, 0xaf, 0x00, 0xae, 0x00, 0x8d, 0x00, 0x8c, 0x00, 0x8a, 0x00, 0x8b,
+        0x00, 0xb1, 0x00, 0xb0, 0x00, 0x2c, 0x00, 0x3b, 0x01, 0x00, 0x00, 0x3b,
+        0x00, 0x00, 0x00, 0x15, 0x00, 0x13, 0x00, 0x00, 0x10, 0x61, 0x70, 0x69,
+        0x2e, 0x74, 0x65, 0x78, 0x74, 0x6d, 0x61, 0x74, 0x65, 0x2e, 0x6f, 0x72,
+        0x67, 0x00, 0x0a, 0x00, 0x08, 0x00, 0x06, 0x00, 0x17, 0x00, 0x18, 0x00,
+        0x19, 0x00, 0x0b, 0x00, 0x02, 0x01, 0x00, 0x00, 0x0d, 0x00, 0x0c, 0x00,
+        0x0a, 0x05, 0x01, 0x04, 0x01, 0x02, 0x01, 0x04, 0x03, 0x02, 0x03
+    };
+
+    byte buffer3[] = { /* no sni extension */
+        0x16, 0x03, 0x03, 0x00, 0x4d, 0x01, 0x00, 0x00, 0x49, 0x03, 0x03, 0xea,
+        0xa1, 0x9f, 0x60, 0xdd, 0x52, 0x12, 0x13, 0xbd, 0x84, 0x34, 0xd5, 0x1c,
+        0x38, 0x25, 0xa8, 0x97, 0xd2, 0xd5, 0xc6, 0x45, 0xaf, 0x1b, 0x08, 0xe4,
+        0x1e, 0xbb, 0xdf, 0x9d, 0x39, 0xf0, 0x65, 0x00, 0x00, 0x16, 0x00, 0x6b,
+        0x00, 0x67, 0x00, 0x39, 0x00, 0x33, 0x00, 0x3d, 0x00, 0x3c, 0x00, 0x35,
+        0x00, 0x2f, 0x00, 0x05, 0x00, 0x04, 0x00, 0x0a, 0x01, 0x00, 0x00, 0x0a,
+        0x00, 0x0d, 0x00, 0x06, 0x00, 0x04, 0x04, 0x01, 0x02, 0x01
+    };
+
+    byte buffer4[] = { /* last extension has zero size */
+        0x16, 0x03, 0x01, 0x00, 0xba, 0x01, 0x00, 0x00,
+        0xb6, 0x03, 0x03, 0x83, 0xa3, 0xe6, 0xdc, 0x16, 0xa1, 0x43, 0xe9, 0x45,
+        0x15, 0xbd, 0x64, 0xa9, 0xb6, 0x07, 0xb4, 0x50, 0xc6, 0xdd, 0xff, 0xc2,
+        0xd3, 0x0d, 0x4f, 0x36, 0xb4, 0x41, 0x51, 0x61, 0xc1, 0xa5, 0x9e, 0x00,
+        0x00, 0x28, 0xcc, 0x14, 0xcc, 0x13, 0xc0, 0x2b, 0xc0, 0x2f, 0x00, 0x9e,
+        0xc0, 0x0a, 0xc0, 0x09, 0xc0, 0x13, 0xc0, 0x14, 0xc0, 0x07, 0xc0, 0x11,
+        0x00, 0x33, 0x00, 0x32, 0x00, 0x39, 0x00, 0x9c, 0x00, 0x2f, 0x00, 0x35,
+        0x00, 0x0a, 0x00, 0x05, 0x00, 0x04, 0x01, 0x00, 0x00, 0x65, 0xff, 0x01,
+        0x00, 0x01, 0x00, 0x00, 0x0a, 0x00, 0x08, 0x00, 0x06, 0x00, 0x17, 0x00,
+        0x18, 0x00, 0x19, 0x00, 0x0b, 0x00, 0x02, 0x01, 0x00, 0x00, 0x23, 0x00,
+        0x00, 0x33, 0x74, 0x00, 0x00, 0x00, 0x10, 0x00, 0x1b, 0x00, 0x19, 0x06,
+        0x73, 0x70, 0x64, 0x79, 0x2f, 0x33, 0x08, 0x73, 0x70, 0x64, 0x79, 0x2f,
+        0x33, 0x2e, 0x31, 0x08, 0x68, 0x74, 0x74, 0x70, 0x2f, 0x31, 0x2e, 0x31,
+        0x75, 0x50, 0x00, 0x00, 0x00, 0x05, 0x00, 0x05, 0x01, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x0d, 0x00, 0x12, 0x00, 0x10, 0x04, 0x01, 0x05, 0x01, 0x02,
+        0x01, 0x04, 0x03, 0x05, 0x03, 0x02, 0x03, 0x04, 0x02, 0x02, 0x02, 0x00,
+        0x12, 0x00, 0x00
+    };
+
+    byte result[32] = {0};
+    word32 length   = 32;
+
+    AssertIntEQ(0, wolfSSL_SNI_GetFromBuffer(buffer4, sizeof(buffer4),
+                                                           0, result, &length));
+
+    AssertIntEQ(0, wolfSSL_SNI_GetFromBuffer(buffer3, sizeof(buffer3),
+                                                           0, result, &length));
+
+    AssertIntEQ(0, wolfSSL_SNI_GetFromBuffer(buffer2, sizeof(buffer2),
+                                                           1, result, &length));
+
+    AssertIntEQ(BUFFER_ERROR, wolfSSL_SNI_GetFromBuffer(buffer, sizeof(buffer),
+                                                           0, result, &length));
+    buffer[0] = 0x16;
+
+    AssertIntEQ(BUFFER_ERROR, wolfSSL_SNI_GetFromBuffer(buffer, sizeof(buffer),
+                                                           0, result, &length));
+    buffer[1] = 0x03;
+
+    AssertIntEQ(SNI_UNSUPPORTED, wolfSSL_SNI_GetFromBuffer(buffer, 
+                                           sizeof(buffer), 0, result, &length));
+    buffer[2] = 0x03;
+
+    AssertIntEQ(INCOMPLETE_DATA, wolfSSL_SNI_GetFromBuffer(buffer,
+                                           sizeof(buffer), 0, result, &length));
+    buffer[4] = 0x64;
+
+    AssertIntEQ(SSL_SUCCESS, wolfSSL_SNI_GetFromBuffer(buffer, sizeof(buffer),
+                                                           0, result, &length));
+    result[length] = 0;
+    AssertStrEQ("www.paypal.com", (const char*) result);
+
+    length = 32;
+
+    AssertIntEQ(SSL_SUCCESS, wolfSSL_SNI_GetFromBuffer(buffer2, sizeof(buffer2),
+                                                           0, result, &length));
+    result[length] = 0;
+    AssertStrEQ("api.textmate.org", (const char*) result);
+}
+
+static void test_wolfSSL_client_server(callback_functions* client_callbacks,
+                                      callback_functions* server_callbacks)
+{
+#ifdef HAVE_IO_TESTS_DEPENDENCIES
+    tcp_ready ready;
+    func_args client_args;
+    func_args server_args;
+    THREAD_TYPE serverThread;
+
+    StartTCP();
+
+    client_args.callbacks = client_callbacks;
+    server_args.callbacks = server_callbacks;
+
+#ifdef WOLFSSL_TIRTOS
+    fdOpenSession(Task_self());
+#endif
+
+    /* RUN Server side */
+    InitTcpReady(&ready);
+    server_args.signal = &ready;
+    client_args.signal = &ready;
+    start_thread(run_wolfssl_server, &server_args, &serverThread);
+    wait_tcp_ready(&server_args);
+
+    /* RUN Client side */
+    run_wolfssl_client(&client_args);
+    join_thread(serverThread);
+
+    FreeTcpReady(&ready);
+#ifdef WOLFSSL_TIRTOS
+    fdCloseSession(Task_self());
+#endif
+    
+#else
+    (void)client_callbacks;
+    (void)server_callbacks;
+#endif
+}
+
+#endif /* HAVE_SNI */
+
+static void test_wolfSSL_UseSNI(void)
+{
+#ifdef HAVE_SNI
+    callback_functions client_callbacks = {wolfSSLv23_client_method, 0, 0, 0};
+    callback_functions server_callbacks = {wolfSSLv23_server_method, 0, 0, 0};
+
+    WOLFSSL_CTX *ctx = wolfSSL_CTX_new(wolfSSLv23_client_method());
+    WOLFSSL     *ssl = wolfSSL_new(ctx);
+
+    AssertNotNull(ctx);
+    AssertNotNull(ssl);
+
+    /* error cases */
+    AssertIntNE(SSL_SUCCESS,
+                    wolfSSL_CTX_UseSNI(NULL, 0, (void *) "ctx", XSTRLEN("ctx")));
+    AssertIntNE(SSL_SUCCESS,
+                    wolfSSL_UseSNI(    NULL, 0, (void *) "ssl", XSTRLEN("ssl")));
+    AssertIntNE(SSL_SUCCESS,
+                    wolfSSL_CTX_UseSNI(ctx, -1, (void *) "ctx", XSTRLEN("ctx")));
+    AssertIntNE(SSL_SUCCESS,
+                    wolfSSL_UseSNI(    ssl, -1, (void *) "ssl", XSTRLEN("ssl")));
+    AssertIntNE(SSL_SUCCESS,
+                    wolfSSL_CTX_UseSNI(ctx,  0, (void *) NULL,  XSTRLEN("ctx")));
+    AssertIntNE(SSL_SUCCESS,
+                    wolfSSL_UseSNI(    ssl,  0, (void *) NULL,  XSTRLEN("ssl")));
+
+    /* success case */
+    AssertIntEQ(SSL_SUCCESS,
+                    wolfSSL_CTX_UseSNI(ctx,  0, (void *) "ctx", XSTRLEN("ctx")));
+    AssertIntEQ(SSL_SUCCESS,
+                    wolfSSL_UseSNI(    ssl,  0, (void *) "ssl", XSTRLEN("ssl")));
+
+    wolfSSL_free(ssl);
+    wolfSSL_CTX_free(ctx);
+
+    /* Testing success case at ctx */
+    client_callbacks.ctx_ready = server_callbacks.ctx_ready = use_SNI_at_ctx;
+    server_callbacks.on_result = verify_SNI_real_matching;
+
+    test_wolfSSL_client_server(&client_callbacks, &server_callbacks);
+
+    /* Testing success case at ssl */
+    client_callbacks.ctx_ready = server_callbacks.ctx_ready = NULL;
+    client_callbacks.ssl_ready = server_callbacks.ssl_ready = use_SNI_at_ssl;
+
+    test_wolfSSL_client_server(&client_callbacks, &server_callbacks);
+
+    /* Testing default mismatch behaviour */
+    client_callbacks.ssl_ready = different_SNI_at_ssl;
+    client_callbacks.on_result = verify_SNI_abort_on_client;
+    server_callbacks.on_result = verify_SNI_abort_on_server;
+
+    test_wolfSSL_client_server(&client_callbacks, &server_callbacks);
+    client_callbacks.on_result = NULL;
+
+    /* Testing continue on mismatch */
+    client_callbacks.ssl_ready = different_SNI_at_ssl;
+    server_callbacks.ssl_ready = use_SNI_WITH_CONTINUE_at_ssl;
+    server_callbacks.on_result = verify_SNI_no_matching;
+
+    test_wolfSSL_client_server(&client_callbacks, &server_callbacks);
+
+    /* Testing fake answer on mismatch */
+    server_callbacks.ssl_ready = use_SNI_WITH_FAKE_ANSWER_at_ssl;
+    server_callbacks.on_result = verify_SNI_fake_matching;
+
+    test_wolfSSL_client_server(&client_callbacks, &server_callbacks);
+
+    test_wolfSSL_SNI_GetFromBuffer();
+#endif
+}
+
+static void test_wolfSSL_UseMaxFragment(void)
+{
+#ifdef HAVE_MAX_FRAGMENT
+    WOLFSSL_CTX *ctx = wolfSSL_CTX_new(wolfSSLv23_client_method());
+    WOLFSSL     *ssl = wolfSSL_new(ctx);
+
+    AssertNotNull(ctx);
+    AssertNotNull(ssl);
+
+    /* error cases */
+    AssertIntNE(SSL_SUCCESS, wolfSSL_CTX_UseMaxFragment(NULL, WOLFSSL_MFL_2_9));
+    AssertIntNE(SSL_SUCCESS, wolfSSL_UseMaxFragment(    NULL, WOLFSSL_MFL_2_9));
+    AssertIntNE(SSL_SUCCESS, wolfSSL_CTX_UseMaxFragment(ctx, 0));
+    AssertIntNE(SSL_SUCCESS, wolfSSL_CTX_UseMaxFragment(ctx, 6));
+    AssertIntNE(SSL_SUCCESS, wolfSSL_UseMaxFragment(ssl, 0));
+    AssertIntNE(SSL_SUCCESS, wolfSSL_UseMaxFragment(ssl, 6));
+
+    /* success case */
+    AssertIntEQ(SSL_SUCCESS, wolfSSL_CTX_UseMaxFragment(ctx,  WOLFSSL_MFL_2_9));
+    AssertIntEQ(SSL_SUCCESS, wolfSSL_CTX_UseMaxFragment(ctx,  WOLFSSL_MFL_2_10));
+    AssertIntEQ(SSL_SUCCESS, wolfSSL_CTX_UseMaxFragment(ctx,  WOLFSSL_MFL_2_11));
+    AssertIntEQ(SSL_SUCCESS, wolfSSL_CTX_UseMaxFragment(ctx,  WOLFSSL_MFL_2_12));
+    AssertIntEQ(SSL_SUCCESS, wolfSSL_CTX_UseMaxFragment(ctx,  WOLFSSL_MFL_2_13));
+    AssertIntEQ(SSL_SUCCESS, wolfSSL_UseMaxFragment(    ssl,  WOLFSSL_MFL_2_9));
+    AssertIntEQ(SSL_SUCCESS, wolfSSL_UseMaxFragment(    ssl,  WOLFSSL_MFL_2_10));
+    AssertIntEQ(SSL_SUCCESS, wolfSSL_UseMaxFragment(    ssl,  WOLFSSL_MFL_2_11));
+    AssertIntEQ(SSL_SUCCESS, wolfSSL_UseMaxFragment(    ssl,  WOLFSSL_MFL_2_12));
+    AssertIntEQ(SSL_SUCCESS, wolfSSL_UseMaxFragment(    ssl,  WOLFSSL_MFL_2_13));
+
+    wolfSSL_free(ssl);
+    wolfSSL_CTX_free(ctx);
+#endif
+}
+
+static void test_wolfSSL_UseTruncatedHMAC(void)
+{
+#ifdef HAVE_TRUNCATED_HMAC
+    WOLFSSL_CTX *ctx = wolfSSL_CTX_new(wolfSSLv23_client_method());
+    WOLFSSL     *ssl = wolfSSL_new(ctx);
+
+    AssertNotNull(ctx);
+    AssertNotNull(ssl);
+
+    /* error cases */
+    AssertIntNE(SSL_SUCCESS, wolfSSL_CTX_UseTruncatedHMAC(NULL));
+    AssertIntNE(SSL_SUCCESS, wolfSSL_UseTruncatedHMAC(NULL));
+
+    /* success case */
+    AssertIntEQ(SSL_SUCCESS, wolfSSL_CTX_UseTruncatedHMAC(ctx));
+    AssertIntEQ(SSL_SUCCESS, wolfSSL_UseTruncatedHMAC(ssl));
+
+    wolfSSL_free(ssl);
+    wolfSSL_CTX_free(ctx);
+#endif
+}
+
+static void test_wolfSSL_UseSupportedCurve(void)
+{
+#ifdef HAVE_SUPPORTED_CURVES
+    WOLFSSL_CTX *ctx = wolfSSL_CTX_new(wolfSSLv23_client_method());
+    WOLFSSL     *ssl = wolfSSL_new(ctx);
+
+    AssertNotNull(ctx);
+    AssertNotNull(ssl);
+
+#ifndef NO_WOLFSSL_CLIENT
+    /* error cases */
+    AssertIntNE(SSL_SUCCESS,
+                      wolfSSL_CTX_UseSupportedCurve(NULL, WOLFSSL_ECC_SECP256R1));
+    AssertIntNE(SSL_SUCCESS, wolfSSL_CTX_UseSupportedCurve(ctx,  0));
+
+    AssertIntNE(SSL_SUCCESS,
+                          wolfSSL_UseSupportedCurve(NULL, WOLFSSL_ECC_SECP256R1));
+    AssertIntNE(SSL_SUCCESS, wolfSSL_UseSupportedCurve(ssl,  0));
+
+    /* success case */
+    AssertIntEQ(SSL_SUCCESS,
+                       wolfSSL_CTX_UseSupportedCurve(ctx, WOLFSSL_ECC_SECP256R1));
+    AssertIntEQ(SSL_SUCCESS,
+                           wolfSSL_UseSupportedCurve(ssl, WOLFSSL_ECC_SECP256R1));
+#endif
+
+    wolfSSL_free(ssl);
+    wolfSSL_CTX_free(ctx);
+#endif
+}
+
+/*----------------------------------------------------------------------------*
+ | Main
+ *----------------------------------------------------------------------------*/
+
+void ApiTest(void)
+{
+    printf(" Begin API Tests\n");
+    test_wolfSSL_Init();
+
+    test_wolfSSL_Method_Allocators();
+    test_wolfSSL_CTX_new(wolfSSLv23_server_method());
+    test_wolfSSL_CTX_use_certificate_file();
+    test_wolfSSL_CTX_use_PrivateKey_file();
+    test_wolfSSL_CTX_load_verify_locations();
+    test_server_wolfSSL_new();
+    test_client_wolfSSL_new();
+    test_wolfSSL_read_write();
+
+    /* TLS extensions tests */
+    test_wolfSSL_UseSNI();
+    test_wolfSSL_UseMaxFragment();
+    test_wolfSSL_UseTruncatedHMAC();
+    test_wolfSSL_UseSupportedCurve();
+
+    test_wolfSSL_Cleanup();
+    printf(" End API Tests\n");
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/hash.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/hash.c
new file mode 100644
index 0000000..e28a71a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/hash.c
@@ -0,0 +1,855 @@
+/* hash.c has unit tests
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+typedef struct testVector {
+    const char*  input;
+    const char*  output; 
+    size_t inLen;
+    size_t outLen;
+} testVector;
+
+int  md4_test(void);
+int  md5_test(void);
+int  sha_test(void);
+int  sha256_test(void);
+int  sha512_test(void);
+int  sha384_test(void);
+int  ripemd_test(void);
+int  hmac_md5_test(void);
+int  hmac_sha_test(void);
+int  hmac_sha256_test(void);
+int  hmac_sha384_test(void);
+
+int HashTest(void)
+{
+    int ret = 0;
+
+    printf(" Begin HASH Tests\n");
+
+#ifndef NO_MD4
+    if ( (ret = md4_test()) ) {
+        printf( "   MD4      test failed!\n");
+        return ret; 
+    } else
+        printf( "   MD4      test passed!\n");
+#endif
+
+#ifndef NO_MD5
+    if ( (ret = md5_test()) ) {
+        printf( "   MD5      test failed!\n");
+        return ret; 
+    } else
+        printf( "   MD5      test passed!\n");
+#endif
+    
+#ifndef NO_SHA
+    if ( (ret = sha_test()) ) {
+        printf( "   SHA      test failed!\n");
+        return ret; 
+    } else
+        printf( "   SHA      test passed!\n");
+#endif
+    
+#ifndef NO_SHA256
+    if ( (ret = sha256_test()) ) {
+        printf( "   SHA-256  test failed!\n");
+        return ret; 
+    } else
+        printf( "   SHA-256  test passed!\n");
+#endif
+
+#ifdef WOLFSSL_SHA512
+    if ( (ret = sha512_test()) ) {
+        printf( "   SHA-512  test failed!\n");
+        return ret; 
+    } else
+        printf( "   SHA-512  test passed!\n");
+#endif
+
+#ifdef WOLFSSL_SHA384
+    if ( (ret = sha384_test()) ) {
+        printf( "   SHA-384  test failed!\n");
+        return ret; 
+    } else
+        printf( "   SHA-384  test passed!\n");
+#endif
+
+#ifdef WOLFSSL_RIPEMD
+    if ( (ret = ripemd_test()) ) {
+        printf( "   RIPEMD   test failed!\n");
+        return ret; 
+    } else
+        printf( "   RIPEMD   test passed!\n");
+#endif
+
+#ifndef NO_HMAC
+    #ifndef NO_MD5
+        if ( (ret = hmac_md5_test()) ) {
+            printf( "   HMAC-MD5 test failed!\n");
+            return ret; 
+        } else
+            printf( "   HMAC-MD5 test passed!\n");
+    #endif
+
+    #ifndef NO_SHA
+    if ( (ret = hmac_sha_test()) ) 
+        printf( "   HMAC-SHA test failed!\n");
+    else
+        printf( "   HMAC-SHA test passed!\n");
+    #endif
+
+    #ifndef NO_SHA256
+        if ( (ret = hmac_sha256_test()) ) 
+            printf( "   HMAC-SHA256 test failed!\n");
+        else
+            printf( "   HMAC-SHA256 test passed!\n");
+    #endif
+
+    #ifdef WOLFSSL_SHA384
+        if ( (ret = hmac_sha384_test()) ) 
+            printf( "   HMAC-SHA384 test failed!\n");
+        else
+            printf( "   HMAC-SHA384 test passed!\n");
+    #endif
+#endif
+
+    printf(" End HASH Tests\n");
+    
+    return 0;
+}
+
+#ifndef NO_MD4
+
+int md4_test(void)
+{
+    Md4  md4;
+    byte hash[MD4_DIGEST_SIZE];
+
+    testVector a, b, c, d, e, f, g;
+    testVector test_md4[7];
+    int times = sizeof(test_md4) / sizeof(testVector), i;
+
+    a.input  = "";
+    a.output = "\x31\xd6\xcf\xe0\xd1\x6a\xe9\x31\xb7\x3c\x59\xd7\xe0\xc0\x89" 
+               "\xc0";
+    a.inLen  = strlen(a.input);
+    a.outLen = strlen(a.output);
+
+    b.input  = "a";
+    b.output = "\xbd\xe5\x2c\xb3\x1d\xe3\x3e\x46\x24\x5e\x05\xfb\xdb\xd6\xfb" 
+               "\x24";
+    b.inLen  = strlen(b.input);
+    b.outLen = strlen(b.output);
+
+    c.input  = "abc";
+    c.output = "\xa4\x48\x01\x7a\xaf\x21\xd8\x52\x5f\xc1\x0a\xe8\x7a\xa6\x72" 
+               "\x9d";
+    c.inLen  = strlen(c.input);
+    c.outLen = strlen(c.output);
+
+    d.input  = "message digest";
+    d.output = "\xd9\x13\x0a\x81\x64\x54\x9f\xe8\x18\x87\x48\x06\xe1\xc7\x01" 
+               "\x4b";
+    d.inLen  = strlen(d.input);
+    d.outLen = strlen(d.output);
+
+    e.input  = "abcdefghijklmnopqrstuvwxyz";
+    e.output = "\xd7\x9e\x1c\x30\x8a\xa5\xbb\xcd\xee\xa8\xed\x63\xdf\x41\x2d" 
+               "\xa9";
+    e.inLen  = strlen(e.input);
+    e.outLen = strlen(e.output);
+
+    f.input  = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz012345"
+               "6789";
+    f.output = "\x04\x3f\x85\x82\xf2\x41\xdb\x35\x1c\xe6\x27\xe1\x53\xe7\xf0" 
+               "\xe4";
+    f.inLen  = strlen(f.input);
+    f.outLen = strlen(f.output);
+
+    g.input  = "1234567890123456789012345678901234567890123456789012345678"
+               "9012345678901234567890";
+    g.output = "\xe3\x3b\x4d\xdc\x9c\x38\xf2\x19\x9c\x3e\x7b\x16\x4f\xcc\x05" 
+               "\x36";
+    g.inLen  = strlen(g.input);
+    g.outLen = strlen(g.output);
+
+    test_md4[0] = a;
+    test_md4[1] = b;
+    test_md4[2] = c;
+    test_md4[3] = d;
+    test_md4[4] = e;
+    test_md4[5] = f;
+    test_md4[6] = g;
+
+    wc_InitMd4(&md4);
+
+    for (i = 0; i < times; ++i) {
+        wc_Md4Update(&md4, (byte*)test_md4[i].input, (word32)test_md4[i].inLen);
+        wc_Md4Final(&md4, hash);
+
+        if (memcmp(hash, test_md4[i].output, MD4_DIGEST_SIZE) != 0)
+            return -205 - i;
+    }
+
+    return 0;
+}
+
+#endif /* NO_MD4 */
+
+#ifndef NO_MD5
+
+int md5_test(void)
+{
+    Md5  md5;
+    byte hash[MD5_DIGEST_SIZE];
+
+    testVector a, b, c, d, e;
+    testVector test_md5[5];
+    int times = sizeof(test_md5) / sizeof(testVector), i;
+
+    a.input  = "abc";
+    a.output = "\x90\x01\x50\x98\x3c\xd2\x4f\xb0\xd6\x96\x3f\x7d\x28\xe1\x7f"
+               "\x72";
+    a.inLen  = strlen(a.input);
+    a.outLen = strlen(a.output);
+
+    b.input  = "message digest";
+    b.output = "\xf9\x6b\x69\x7d\x7c\xb7\x93\x8d\x52\x5a\x2f\x31\xaa\xf1\x61"
+               "\xd0";
+    b.inLen  = strlen(b.input);
+    b.outLen = strlen(b.output);
+
+    c.input  = "abcdefghijklmnopqrstuvwxyz";
+    c.output = "\xc3\xfc\xd3\xd7\x61\x92\xe4\x00\x7d\xfb\x49\x6c\xca\x67\xe1"
+               "\x3b";
+    c.inLen  = strlen(c.input);
+    c.outLen = strlen(c.output);
+
+    d.input  = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz012345"
+               "6789";
+    d.output = "\xd1\x74\xab\x98\xd2\x77\xd9\xf5\xa5\x61\x1c\x2c\x9f\x41\x9d"
+               "\x9f";
+    d.inLen  = strlen(d.input);
+    d.outLen = strlen(d.output);
+
+    e.input  = "1234567890123456789012345678901234567890123456789012345678"
+               "9012345678901234567890";
+    e.output = "\x57\xed\xf4\xa2\x2b\xe3\xc9\x55\xac\x49\xda\x2e\x21\x07\xb6"
+               "\x7a";
+    e.inLen  = strlen(e.input);
+    e.outLen = strlen(e.output);
+
+    test_md5[0] = a;
+    test_md5[1] = b;
+    test_md5[2] = c;
+    test_md5[3] = d;
+    test_md5[4] = e;
+
+    wc_InitMd5(&md5);
+
+    for (i = 0; i < times; ++i) {
+        wc_Md5Update(&md5, (byte*)test_md5[i].input, (word32)test_md5[i].inLen);
+        wc_Md5Final(&md5, hash);
+
+        if (memcmp(hash, test_md5[i].output, MD5_DIGEST_SIZE) != 0)
+            return -5 - i;
+    }
+
+    return 0;
+}
+
+#endif /* NO_MD5 */
+
+#ifndef NO_SHA
+int sha_test(void)
+{
+    Sha  sha;
+    byte hash[SHA_DIGEST_SIZE];
+
+    testVector a, b, c, d;
+    testVector test_sha[4];
+    int ret   = 0;
+    int times = sizeof(test_sha) / sizeof(struct testVector), i;
+
+    a.input  = "abc";
+    a.output = "\xA9\x99\x3E\x36\x47\x06\x81\x6A\xBA\x3E\x25\x71\x78\x50\xC2"
+               "\x6C\x9C\xD0\xD8\x9D";
+    a.inLen  = strlen(a.input);
+    a.outLen = strlen(a.output);
+
+    b.input  = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq";
+    b.output = "\x84\x98\x3E\x44\x1C\x3B\xD2\x6E\xBA\xAE\x4A\xA1\xF9\x51\x29"
+               "\xE5\xE5\x46\x70\xF1";
+    b.inLen  = strlen(b.input);
+    b.outLen = strlen(b.output);
+
+    c.input  = "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa"
+               "aaaaaa";
+    c.output = "\x00\x98\xBA\x82\x4B\x5C\x16\x42\x7B\xD7\xA1\x12\x2A\x5A\x44"
+               "\x2A\x25\xEC\x64\x4D";
+    c.inLen  = strlen(c.input);
+    c.outLen = strlen(c.output);
+
+    d.input  = "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa"
+               "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa"
+               "aaaaaaaaaa";
+    d.output = "\xAD\x5B\x3F\xDB\xCB\x52\x67\x78\xC2\x83\x9D\x2F\x15\x1E\xA7"
+               "\x53\x99\x5E\x26\xA0";
+    d.inLen  = strlen(d.input);
+    d.outLen = strlen(d.output);
+
+    test_sha[0] = a;
+    test_sha[1] = b;
+    test_sha[2] = c;
+    test_sha[3] = d;
+
+    ret = wc_InitSha(&sha);
+    if (ret != 0)
+        return ret;
+
+    for (i = 0; i < times; ++i) {
+        wc_ShaUpdate(&sha, (byte*)test_sha[i].input, (word32)test_sha[i].inLen);
+        wc_ShaFinal(&sha, hash);
+
+        if (memcmp(hash, test_sha[i].output, SHA_DIGEST_SIZE) != 0)
+            return -10 - i;
+    }
+
+    return 0;
+}
+#endif /* NO_SHA */
+
+#ifndef NO_SHA256
+int sha256_test(void)
+{
+    Sha256 sha;
+    byte   hash[SHA256_DIGEST_SIZE];
+
+    testVector a, b;
+    testVector test_sha[2];
+    int ret;
+    int times = sizeof(test_sha) / sizeof(struct testVector), i;
+
+    a.input  = "abc";
+    a.output = "\xBA\x78\x16\xBF\x8F\x01\xCF\xEA\x41\x41\x40\xDE\x5D\xAE\x22"
+               "\x23\xB0\x03\x61\xA3\x96\x17\x7A\x9C\xB4\x10\xFF\x61\xF2\x00"
+               "\x15\xAD";
+    a.inLen  = strlen(a.input);
+    a.outLen = strlen(a.output);
+
+    b.input  = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq";
+    b.output = "\x24\x8D\x6A\x61\xD2\x06\x38\xB8\xE5\xC0\x26\x93\x0C\x3E\x60"
+               "\x39\xA3\x3C\xE4\x59\x64\xFF\x21\x67\xF6\xEC\xED\xD4\x19\xDB"
+               "\x06\xC1";
+    b.inLen  = strlen(b.input);
+    b.outLen = strlen(b.output);
+
+    test_sha[0] = a;
+    test_sha[1] = b;
+
+    ret = wc_InitSha256(&sha);
+    if (ret != 0)
+        return ret;
+
+    for (i = 0; i < times; ++i) {
+        ret = wc_Sha256Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen);
+        if (ret != 0)
+            return ret;
+
+        ret = wc_Sha256Final(&sha, hash);
+        if (ret != 0)
+            return ret;
+
+        if (memcmp(hash, test_sha[i].output, SHA256_DIGEST_SIZE) != 0)
+            return -10 - i;
+    }
+
+    return 0;
+}
+#endif
+
+#ifdef WOLFSSL_SHA512
+int sha512_test(void)
+{
+    Sha512 sha;
+    byte   hash[SHA512_DIGEST_SIZE];
+
+    testVector a, b;
+    testVector test_sha[2];
+    int times = sizeof(test_sha) / sizeof(struct testVector), i;
+    int ret;
+
+    a.input  = "abc";
+    a.output = "\xdd\xaf\x35\xa1\x93\x61\x7a\xba\xcc\x41\x73\x49\xae\x20\x41"
+               "\x31\x12\xe6\xfa\x4e\x89\xa9\x7e\xa2\x0a\x9e\xee\xe6\x4b\x55"
+               "\xd3\x9a\x21\x92\x99\x2a\x27\x4f\xc1\xa8\x36\xba\x3c\x23\xa3"
+               "\xfe\xeb\xbd\x45\x4d\x44\x23\x64\x3c\xe8\x0e\x2a\x9a\xc9\x4f"
+               "\xa5\x4c\xa4\x9f";
+    a.inLen  = strlen(a.input);
+    a.outLen = strlen(a.output);
+
+    b.input  = "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmnhi"
+               "jklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu";
+    b.output = "\x8e\x95\x9b\x75\xda\xe3\x13\xda\x8c\xf4\xf7\x28\x14\xfc\x14"
+               "\x3f\x8f\x77\x79\xc6\xeb\x9f\x7f\xa1\x72\x99\xae\xad\xb6\x88"
+               "\x90\x18\x50\x1d\x28\x9e\x49\x00\xf7\xe4\x33\x1b\x99\xde\xc4"
+               "\xb5\x43\x3a\xc7\xd3\x29\xee\xb6\xdd\x26\x54\x5e\x96\xe5\x5b"
+               "\x87\x4b\xe9\x09"; 
+    b.inLen  = strlen(b.input);
+    b.outLen = strlen(b.output);
+
+    test_sha[0] = a;
+    test_sha[1] = b;
+
+    ret = wc_InitSha512(&sha);
+    if (ret != 0)
+        return ret;
+
+    for (i = 0; i < times; ++i) {
+        ret = wc_Sha512Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen);
+        if (ret != 0)
+            return ret;
+
+        ret = wc_Sha512Final(&sha, hash);
+        if (ret != 0)
+            return ret;
+
+        if (memcmp(hash, test_sha[i].output, SHA512_DIGEST_SIZE) != 0)
+            return -10 - i;
+    }
+
+    return 0;
+}
+#endif
+
+#ifdef WOLFSSL_SHA384
+int sha384_test()
+{
+    Sha384 sha;
+    byte   hash[SHA384_DIGEST_SIZE];
+
+    testVector a, b;
+    testVector test_sha[2];
+    int times = sizeof(test_sha) / sizeof(struct testVector), i;
+    int ret;
+
+    a.input  = "abc";
+    a.output = "\xcb\x00\x75\x3f\x45\xa3\x5e\x8b\xb5\xa0\x3d\x69\x9a\xc6\x50"
+               "\x07\x27\x2c\x32\xab\x0e\xde\xd1\x63\x1a\x8b\x60\x5a\x43\xff"
+               "\x5b\xed\x80\x86\x07\x2b\xa1\xe7\xcc\x23\x58\xba\xec\xa1\x34"
+               "\xc8\x25\xa7";
+    a.inLen  = strlen(a.input);
+    a.outLen = strlen(a.output);
+
+    b.input  = "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmnhi"
+               "jklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu";
+    b.output = "\x09\x33\x0c\x33\xf7\x11\x47\xe8\x3d\x19\x2f\xc7\x82\xcd\x1b"
+               "\x47\x53\x11\x1b\x17\x3b\x3b\x05\xd2\x2f\xa0\x80\x86\xe3\xb0"
+               "\xf7\x12\xfc\xc7\xc7\x1a\x55\x7e\x2d\xb9\x66\xc3\xe9\xfa\x91"
+               "\x74\x60\x39";
+    b.inLen  = strlen(b.input);
+    b.outLen = strlen(b.output);
+
+    test_sha[0] = a;
+    test_sha[1] = b;
+
+    ret = wc_InitSha384(&sha);
+    if (ret != 0)
+        return ret;
+
+    for (i = 0; i < times; ++i) {
+        ret = wc_Sha384Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen);
+        if (ret != 0)
+            return ret;
+
+        ret = wc_Sha384Final(&sha, hash);
+        if (ret != 0)
+            return ret;
+
+        if (memcmp(hash, test_sha[i].output, SHA384_DIGEST_SIZE) != 0)
+            return -10 - i;
+    }
+
+    return 0;
+}
+#endif
+
+#ifdef WOLFSSL_RIPEMD
+int ripemd_test(void)
+{
+    RipeMd  ripemd;
+    byte hash[RIPEMD_DIGEST_SIZE];
+
+    testVector a, b, c, d;
+    testVector test_ripemd[4];
+    int times = sizeof(test_ripemd) / sizeof(struct testVector), i;
+
+    a.input  = "abc";
+    a.output = "\x8e\xb2\x08\xf7\xe0\x5d\x98\x7a\x9b\x04\x4a\x8e\x98\xc6"
+               "\xb0\x87\xf1\x5a\x0b\xfc";
+    a.inLen  = strlen(a.input);
+    a.outLen = strlen(a.output);
+
+    b.input  = "message digest";
+    b.output = "\x5d\x06\x89\xef\x49\xd2\xfa\xe5\x72\xb8\x81\xb1\x23\xa8"
+               "\x5f\xfa\x21\x59\x5f\x36";
+    b.inLen  = strlen(b.input);
+    b.outLen = strlen(b.output);
+
+    c.input  = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"; 
+    c.output = "\x12\xa0\x53\x38\x4a\x9c\x0c\x88\xe4\x05\xa0\x6c\x27\xdc"
+               "\xf4\x9a\xda\x62\xeb\x2b";
+    c.inLen  = strlen(c.input);
+    c.outLen = strlen(c.output);
+
+    d.input  = "12345678901234567890123456789012345678901234567890123456"
+               "789012345678901234567890";
+    d.output = "\x9b\x75\x2e\x45\x57\x3d\x4b\x39\xf4\xdb\xd3\x32\x3c\xab"
+               "\x82\xbf\x63\x32\x6b\xfb"; 
+    d.inLen  = strlen(d.input);
+    d.outLen = strlen(d.output);
+
+    test_ripemd[0] = a;
+    test_ripemd[1] = b;
+    test_ripemd[2] = c;
+    test_ripemd[3] = d;
+
+    wc_InitRipeMd(&ripemd);
+
+    for (i = 0; i < times; ++i) {
+        wc_RipeMdUpdate(&ripemd, (byte*)test_ripemd[i].input,
+                     (word32)test_ripemd[i].inLen);
+        wc_RipeMdFinal(&ripemd, hash);
+
+        if (memcmp(hash, test_ripemd[i].output, RIPEMD_DIGEST_SIZE) != 0)
+            return -10 - i;
+    }
+
+    return 0;
+}
+#endif /* WOLFSSL_RIPEMD */
+
+#if !defined(NO_HMAC) && !defined(NO_MD5)
+int hmac_md5_test(void)
+{
+    Hmac hmac;
+    byte hash[MD5_DIGEST_SIZE];
+
+    const char* keys[]=
+    {
+        "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b",
+        "Jefe",
+        "\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA"
+    };
+
+    testVector a, b, c;
+    testVector test_hmac[3];
+
+    int ret;
+    int times = sizeof(test_hmac) / sizeof(testVector), i;
+
+    a.input  = "Hi There";
+    a.output = "\x92\x94\x72\x7a\x36\x38\xbb\x1c\x13\xf4\x8e\xf8\x15\x8b\xfc"
+               "\x9d";
+    a.inLen  = strlen(a.input);
+    a.outLen = strlen(a.output);
+
+    b.input  = "what do ya want for nothing?";
+    b.output = "\x75\x0c\x78\x3e\x6a\xb0\xb5\x03\xea\xa8\x6e\x31\x0a\x5d\xb7"
+               "\x38";
+    b.inLen  = strlen(b.input);
+    b.outLen = strlen(b.output);
+
+    c.input  = "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD";
+    c.output = "\x56\xbe\x34\x52\x1d\x14\x4c\x88\xdb\xb8\xc7\x33\xf0\xe8\xb3"
+               "\xf6";
+    c.inLen  = strlen(c.input);
+    c.outLen = strlen(c.output);
+
+    test_hmac[0] = a;
+    test_hmac[1] = b;
+    test_hmac[2] = c;
+
+    for (i = 0; i < times; ++i) {
+#if defined(HAVE_FIPS)
+        if (i == 1)
+            continue; /* fips not allowed */
+#endif
+        ret = wc_HmacSetKey(&hmac, MD5, (byte*)keys[i], (word32)strlen(keys[i]));
+        if (ret != 0)
+            return -4014;
+        ret = wc_HmacUpdate(&hmac, (byte*)test_hmac[i].input,
+                   (word32)test_hmac[i].inLen);
+        if (ret != 0)
+            return -4015;
+        ret = wc_HmacFinal(&hmac, hash);
+        if (ret != 0)
+            return -4016;
+
+        if (memcmp(hash, test_hmac[i].output, MD5_DIGEST_SIZE) != 0)
+            return -20 - i;
+    }
+
+    return 0;
+}
+#endif
+
+#if !defined(NO_HMAC) && !defined(NO_SHA)
+int hmac_sha_test(void)
+{
+    Hmac hmac;
+    byte hash[SHA_DIGEST_SIZE];
+
+    const char* keys[]=
+    {
+        "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+                                                                "\x0b\x0b\x0b",
+        "Jefe",
+        "\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA"
+                                                                "\xAA\xAA\xAA"
+    };
+
+    testVector a, b, c;
+    testVector test_hmac[3];
+
+    int ret;
+    int times = sizeof(test_hmac) / sizeof(testVector), i;
+
+    a.input  = "Hi There";
+    a.output = "\xb6\x17\x31\x86\x55\x05\x72\x64\xe2\x8b\xc0\xb6\xfb\x37\x8c"
+               "\x8e\xf1\x46\xbe\x00";
+    a.inLen  = strlen(a.input);
+    a.outLen = strlen(a.output);
+
+    b.input  = "what do ya want for nothing?";
+    b.output = "\xef\xfc\xdf\x6a\xe5\xeb\x2f\xa2\xd2\x74\x16\xd5\xf1\x84\xdf"
+               "\x9c\x25\x9a\x7c\x79";
+    b.inLen  = strlen(b.input);
+    b.outLen = strlen(b.output);
+
+    c.input  = "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD";
+    c.output = "\x12\x5d\x73\x42\xb9\xac\x11\xcd\x91\xa3\x9a\xf4\x8a\xa1\x7b"
+               "\x4f\x63\xf1\x75\xd3";
+    c.inLen  = strlen(c.input);
+    c.outLen = strlen(c.output);
+
+    test_hmac[0] = a;
+    test_hmac[1] = b;
+    test_hmac[2] = c;
+
+    for (i = 0; i < times; ++i) {
+#if defined(HAVE_FIPS)
+        if (i == 1)
+            continue; /* fips not allowed */
+#endif
+        ret = wc_HmacSetKey(&hmac, SHA, (byte*)keys[i], (word32)strlen(keys[i]));
+        if (ret != 0)
+            return -4017;
+        ret = wc_HmacUpdate(&hmac, (byte*)test_hmac[i].input,
+                   (word32)test_hmac[i].inLen);
+        if (ret != 0)
+            return -4018;
+        ret = wc_HmacFinal(&hmac, hash);
+        if (ret != 0)
+            return -4019;
+
+        if (memcmp(hash, test_hmac[i].output, SHA_DIGEST_SIZE) != 0)
+            return -20 - i;
+    }
+
+    return 0;
+}
+#endif
+
+#if !defined(NO_HMAC) && !defined(NO_SHA256)
+int hmac_sha256_test(void)
+{
+    Hmac hmac;
+    byte hash[SHA256_DIGEST_SIZE];
+
+    const char* keys[]=
+    {
+        "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+                                                                "\x0b\x0b\x0b",
+        "Jefe",
+        "\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA"
+                                                                "\xAA\xAA\xAA"
+    };
+
+    testVector a, b, c;
+    testVector test_hmac[3];
+
+    int ret;
+    int times = sizeof(test_hmac) / sizeof(testVector), i;
+
+    a.input  = "Hi There";
+    a.output = "\xb0\x34\x4c\x61\xd8\xdb\x38\x53\x5c\xa8\xaf\xce\xaf\x0b\xf1"
+               "\x2b\x88\x1d\xc2\x00\xc9\x83\x3d\xa7\x26\xe9\x37\x6c\x2e\x32"
+               "\xcf\xf7";
+    a.inLen  = strlen(a.input);
+    a.outLen = strlen(a.output);
+
+    b.input  = "what do ya want for nothing?";
+    b.output = "\x5b\xdc\xc1\x46\xbf\x60\x75\x4e\x6a\x04\x24\x26\x08\x95\x75"
+               "\xc7\x5a\x00\x3f\x08\x9d\x27\x39\x83\x9d\xec\x58\xb9\x64\xec"
+               "\x38\x43";
+    b.inLen  = strlen(b.input);
+    b.outLen = strlen(b.output);
+
+    c.input  = "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD";
+    c.output = "\x77\x3e\xa9\x1e\x36\x80\x0e\x46\x85\x4d\xb8\xeb\xd0\x91\x81"
+               "\xa7\x29\x59\x09\x8b\x3e\xf8\xc1\x22\xd9\x63\x55\x14\xce\xd5"
+               "\x65\xfe";
+    c.inLen  = strlen(c.input);
+    c.outLen = strlen(c.output);
+
+    test_hmac[0] = a;
+    test_hmac[1] = b;
+    test_hmac[2] = c;
+
+    for (i = 0; i < times; ++i) {
+#if defined(HAVE_FIPS)
+        if (i == 1)
+            continue; /* fips not allowed */
+#endif
+        ret = wc_HmacSetKey(&hmac,SHA256, (byte*)keys[i], (word32)strlen(keys[i]));
+        if (ret != 0)
+            return -4020;
+        ret = wc_HmacUpdate(&hmac, (byte*)test_hmac[i].input,
+                   (word32)test_hmac[i].inLen);
+        if (ret != 0)
+            return -4021;
+        ret = wc_HmacFinal(&hmac, hash);
+        if (ret != 0)
+            return -4022;
+
+        if (memcmp(hash, test_hmac[i].output, SHA256_DIGEST_SIZE) != 0)
+            return -20 - i;
+    }
+
+    return 0;
+}
+#endif
+
+
+#if !defined(NO_HMAC) && defined(WOLFSSL_SHA384)
+int hmac_sha384_test(void)
+{
+    Hmac hmac;
+    byte hash[SHA384_DIGEST_SIZE];
+
+    const char* keys[]=
+    {
+        "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+                                                                "\x0b\x0b\x0b",
+        "Jefe",
+        "\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA"
+                                                                "\xAA\xAA\xAA"
+    };
+
+    testVector a, b, c;
+    testVector test_hmac[3];
+
+    int ret;
+    int times = sizeof(test_hmac) / sizeof(testVector), i;
+
+    a.input  = "Hi There";
+    a.output = "\xaf\xd0\x39\x44\xd8\x48\x95\x62\x6b\x08\x25\xf4\xab\x46\x90"
+               "\x7f\x15\xf9\xda\xdb\xe4\x10\x1e\xc6\x82\xaa\x03\x4c\x7c\xeb"
+               "\xc5\x9c\xfa\xea\x9e\xa9\x07\x6e\xde\x7f\x4a\xf1\x52\xe8\xb2"
+               "\xfa\x9c\xb6";
+    a.inLen  = strlen(a.input);
+    a.outLen = strlen(a.output);
+
+    b.input  = "what do ya want for nothing?";
+    b.output = "\xaf\x45\xd2\xe3\x76\x48\x40\x31\x61\x7f\x78\xd2\xb5\x8a\x6b"
+               "\x1b\x9c\x7e\xf4\x64\xf5\xa0\x1b\x47\xe4\x2e\xc3\x73\x63\x22"
+               "\x44\x5e\x8e\x22\x40\xca\x5e\x69\xe2\xc7\x8b\x32\x39\xec\xfa"
+               "\xb2\x16\x49";
+    b.inLen  = strlen(b.input);
+    b.outLen = strlen(b.output);
+
+    c.input  = "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD";
+    c.output = "\x88\x06\x26\x08\xd3\xe6\xad\x8a\x0a\xa2\xac\xe0\x14\xc8\xa8"
+               "\x6f\x0a\xa6\x35\xd9\x47\xac\x9f\xeb\xe8\x3e\xf4\xe5\x59\x66"
+               "\x14\x4b\x2a\x5a\xb3\x9d\xc1\x38\x14\xb9\x4e\x3a\xb6\xe1\x01"
+               "\xa3\x4f\x27";
+    c.inLen  = strlen(c.input);
+    c.outLen = strlen(c.output);
+
+    test_hmac[0] = a;
+    test_hmac[1] = b;
+    test_hmac[2] = c;
+
+    for (i = 0; i < times; ++i) {
+#if defined(HAVE_FIPS)
+        if (i == 1)
+            continue; /* fips not allowed */
+#endif
+        ret = wc_HmacSetKey(&hmac,SHA384, (byte*)keys[i], (word32)strlen(keys[i]));
+        if (ret != 0)
+            return -4023;
+        ret = wc_HmacUpdate(&hmac, (byte*)test_hmac[i].input,
+                   (word32)test_hmac[i].inLen);
+        if (ret != 0)
+            return -4024;
+        ret = wc_HmacFinal(&hmac, hash);
+        if (ret != 0)
+            return -4025;
+
+        if (memcmp(hash, test_hmac[i].output, SHA384_DIGEST_SIZE) != 0)
+            return -20 - i;
+    }
+
+    return 0;
+}
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/include.am
new file mode 100644
index 0000000..0064585
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/include.am
@@ -0,0 +1,23 @@
+# vim:ft=automake
+# included from Top Level Makefile.am
+# All paths should be given relative to the root
+
+
+if BUILD_EXAMPLES
+check_PROGRAMS += tests/unit.test
+noinst_PROGRAMS += tests/unit.test
+tests_unit_test_SOURCES = \
+                  tests/unit.c \
+                  tests/api.c \
+                  tests/suites.c \
+                  tests/hash.c \
+                  examples/client/client.c \
+                  examples/server/server.c
+tests_unit_test_CFLAGS       = -DNO_MAIN_DRIVER $(AM_CFLAGS)
+tests_unit_test_LDADD        = src/libwolfssl.la
+tests_unit_test_DEPENDENCIES = src/libwolfssl.la
+endif
+EXTRA_DIST += tests/unit.h
+EXTRA_DIST += tests/test.conf \
+              tests/test-dtls.conf
+DISTCLEANFILES+= tests/.libs/unit.test
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/suites.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/suites.c
new file mode 100644
index 0000000..d1abc19
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/suites.c
@@ -0,0 +1,468 @@
+/* suites.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+#define MAX_ARGS 40
+#define MAX_COMMAND_SZ 240
+#define MAX_SUITE_SZ 80 
+#define NOT_BUILT_IN -123
+#ifdef NO_OLD_TLS
+    #define VERSION_TOO_OLD -124
+#endif
+
+#include "examples/client/client.h"
+#include "examples/server/server.h"
+
+
+static WOLFSSL_CTX* cipherSuiteCtx = NULL;
+static char nonblockFlag[] = "-N";
+static char noVerifyFlag[] = "-d";
+static char portFlag[] = "-p";
+static char flagSep[] = " ";
+static char svrPort[] = "0";
+
+
+#ifdef NO_OLD_TLS
+/* if the protocol version is less than tls 1.2 return 1, else 0 */
+static int IsOldTlsVersion(const char* line)
+{
+    const char* find = "-v ";
+    char* begin = strstr(line, find);
+
+    if (begin) {
+        int version = -1;
+
+        begin += 3;
+
+        version = atoi(begin);
+
+        if (version < 3)
+            return 1;
+    }
+
+    return 0;
+} 
+#endif /* NO_OLD_TLS */
+
+
+/* if the cipher suite on line is valid store in suite and return 1, else 0 */
+static int IsValidCipherSuite(const char* line, char* suite)
+{
+    int  found = 0;
+    int  valid = 0;
+
+    const char* find = "-l ";
+    const char* begin = strstr(line, find);
+    const char* end;
+
+    suite[0] = '\0';
+
+    if (begin) {
+        begin += 3;
+
+        end = strstr(begin, " ");
+
+        if (end) {
+            long len = end - begin;
+            if (len > MAX_SUITE_SZ) {
+                printf("suite too long!\n");
+                return 0;
+            }
+            memcpy(suite, begin, len);
+            suite[len] = '\0';
+        }
+        else
+            strncpy(suite, begin, MAX_SUITE_SZ);
+
+        suite[MAX_SUITE_SZ] = '\0';
+        found = 1;
+    }
+
+    if (found) {
+        if (wolfSSL_CTX_set_cipher_list(cipherSuiteCtx, suite) == SSL_SUCCESS)
+            valid = 1;
+    }
+
+    return valid;
+}
+
+
+static int execute_test_case(int svr_argc, char** svr_argv,
+                              int cli_argc, char** cli_argv,
+                              int addNoVerify, int addNonBlocking)
+{
+#ifdef WOLFSSL_TIRTOS
+    func_args cliArgs = {0};
+    func_args svrArgs = {0};
+    cliArgs.argc = cli_argc;
+    cliArgs.argv = cli_argv;
+    svrArgs.argc = svr_argc;
+    svrArgs.argv = svr_argv;
+#else
+    func_args cliArgs = {cli_argc, cli_argv, 0, NULL, NULL};
+    func_args svrArgs = {svr_argc, svr_argv, 0, NULL, NULL};
+#endif
+
+    tcp_ready   ready;
+    THREAD_TYPE serverThread;
+    char        commandLine[MAX_COMMAND_SZ];
+    char        cipherSuite[MAX_SUITE_SZ+1];
+    int         i;
+    size_t      added = 0;
+    static      int tests = 1;
+
+    commandLine[0] = '\0';
+    for (i = 0; i < svr_argc; i++) {
+        added += strlen(svr_argv[i]) + 2;
+        if (added >= MAX_COMMAND_SZ) {
+            printf("server command line too long\n"); 
+            break;
+        }
+        strcat(commandLine, svr_argv[i]);
+        strcat(commandLine, flagSep);
+    }
+
+    if (IsValidCipherSuite(commandLine, cipherSuite) == 0) {
+        #ifdef DEBUG_SUITE_TESTS
+            printf("cipher suite %s not supported in build\n", cipherSuite);
+        #endif
+        return NOT_BUILT_IN;
+    }
+
+#ifdef NO_OLD_TLS
+    if (IsOldTlsVersion(commandLine) == 1) {
+        #ifdef DEBUG_SUITE_TESTS
+            printf("protocol version on line %s is too old\n", commandLine);
+        #endif
+        return VERSION_TOO_OLD;
+    }
+#endif
+
+    if (addNoVerify) {
+        printf("repeating test with client cert request off\n"); 
+        added += 4;   /* -d plus space plus terminator */
+        if (added >= MAX_COMMAND_SZ || svr_argc >= MAX_ARGS)
+            printf("server command line too long\n");
+        else {
+            svr_argv[svr_argc++] = noVerifyFlag;
+            svrArgs.argc = svr_argc;
+            strcat(commandLine, noVerifyFlag);
+            strcat(commandLine, flagSep);
+        }
+    }
+    if (addNonBlocking) {
+        printf("repeating test with non blocking on\n"); 
+        added += 4;   /* -N plus terminator */
+        if (added >= MAX_COMMAND_SZ || svr_argc >= MAX_ARGS)
+            printf("server command line too long\n");
+        else {
+            svr_argv[svr_argc++] = nonblockFlag;
+            svrArgs.argc = svr_argc;
+            strcat(commandLine, nonblockFlag);
+            strcat(commandLine, flagSep);
+        }
+    }
+    #if !defined(USE_WINDOWS_API) && !defined(WOLFSSL_TIRTOS)
+        /* add port 0 */
+        if (svr_argc + 2 > MAX_ARGS)
+            printf("cannot add the magic port number flag to server\n");
+        else
+        {
+            svr_argv[svr_argc++] = portFlag;
+            svr_argv[svr_argc++] = svrPort;
+            svrArgs.argc = svr_argc;
+        }
+    #endif
+    printf("trying server command line[%d]: %s\n", tests, commandLine);
+
+    commandLine[0] = '\0';
+    added = 0;
+    for (i = 0; i < cli_argc; i++) {
+        added += strlen(cli_argv[i]) + 2;
+        if (added >= MAX_COMMAND_SZ) {
+            printf("client command line too long\n"); 
+            break;
+        }
+        strcat(commandLine, cli_argv[i]);
+        strcat(commandLine, flagSep);
+    }
+    if (addNonBlocking) {
+        added += 4;   /* -N plus space plus terminator  */
+        if (added >= MAX_COMMAND_SZ)
+            printf("client command line too long\n");
+        else  {
+            cli_argv[cli_argc++] = nonblockFlag;
+            strcat(commandLine, nonblockFlag);
+            strcat(commandLine, flagSep);
+            cliArgs.argc = cli_argc;
+        }
+    }
+    printf("trying client command line[%d]: %s\n", tests++, commandLine);
+
+    InitTcpReady(&ready);
+
+#ifdef WOLFSSL_TIRTOS
+    fdOpenSession(Task_self());
+#endif
+
+    /* start server */
+    svrArgs.signal = &ready;
+    start_thread(server_test, &svrArgs, &serverThread);
+    wait_tcp_ready(&svrArgs);
+    #if !defined(USE_WINDOWS_API) && !defined(WOLFSSL_TIRTOS)
+        if (ready.port != 0)
+        {
+            if (cli_argc + 2 > MAX_ARGS)
+                printf("cannot add the magic port number flag to client\n");
+            else {
+                char portNumber[8];
+                snprintf(portNumber, sizeof(portNumber), "%d", ready.port);
+                cli_argv[cli_argc++] = portFlag;
+                cli_argv[cli_argc++] = portNumber;
+                cliArgs.argc = cli_argc;
+            }
+        }
+    #endif
+    /* start client */
+    client_test(&cliArgs);
+
+    /* verify results */ 
+    if (cliArgs.return_code != 0) {
+        printf("client_test failed\n");
+        exit(EXIT_FAILURE);
+    }
+
+    join_thread(serverThread);
+    if (svrArgs.return_code != 0) { 
+        printf("server_test failed\n");
+        exit(EXIT_FAILURE);
+    }
+
+#ifdef WOLFSSL_TIRTOS
+    fdCloseSession(Task_self());
+#endif
+    FreeTcpReady(&ready);
+    
+    return 0;
+}
+
+static void test_harness(void* vargs)
+{
+    func_args* args = (func_args*)vargs;
+    char* script;
+    long  sz, len;
+    int   cliMode = 0;   /* server or client command flag, server first */
+    int   ret;
+    FILE* file;
+    char* svrArgs[MAX_ARGS];
+    int   svrArgsSz;
+    char* cliArgs[MAX_ARGS];
+    int   cliArgsSz;
+    char* cursor;
+    char* comment;
+    const char* fname = "tests/test.conf";
+
+    if (args->argc == 1) {
+        printf("notice: using default file %s\n", fname);
+    }
+    else if(args->argc != 2) {
+        printf("usage: harness [FILE]\n");
+        args->return_code = 1;
+        return;
+    }
+    else {
+        fname = args->argv[1];
+    }
+
+    file = fopen(fname, "r");
+    if (file == NULL) {
+        fprintf(stderr, "unable to open %s\n", fname);
+        args->return_code = 1;
+        return;
+    }
+    fseek(file, 0, SEEK_END);
+    sz = ftell(file);
+    rewind(file);
+    if (sz <= 0) {
+        fprintf(stderr, "%s is empty\n", fname);
+        fclose(file);
+        args->return_code = 1;
+        return;
+    }
+
+    script = (char*)malloc(sz+1);
+    if (script == 0) {
+        fprintf(stderr, "unable to allocte script buffer\n");
+        fclose(file);
+        args->return_code = 1;
+        return;
+    }
+
+    len = fread(script, 1, sz, file);
+    if (len != sz) {
+        fprintf(stderr, "read error\n");
+        fclose(file);
+        free(script);
+        args->return_code = 1;
+        return;
+    }
+    
+    fclose(file);
+    script[sz] = 0;
+
+    cursor = script;
+    svrArgsSz = 1;
+    svrArgs[0] = args->argv[0];
+    cliArgsSz = 1;
+    cliArgs[0] = args->argv[0];
+
+    while (*cursor != 0) {
+        int do_it = 0;
+
+        switch (*cursor) {
+            case '\n':
+                /* A blank line triggers test case execution or switches
+                   to client mode if we don't have the client command yet */
+                if (cliMode == 0)
+                    cliMode = 1;  /* switch to client mode processing */
+                else
+                    do_it = 1;    /* Do It, we have server and client */
+                cursor++;
+                break;
+            case '#':
+                /* Ignore lines that start with a #. */
+                comment = strsep(&cursor, "\n");
+#ifdef DEBUG_SUITE_TESTS
+                printf("%s\n", comment);
+#else
+                (void)comment;
+#endif
+                break;
+            case '-':
+                /* Parameters start with a -. They end in either a newline
+                 * or a space. Capture until either, save in Args list. */
+                if (cliMode)
+                    cliArgs[cliArgsSz++] = strsep(&cursor, " \n");
+                else
+                    svrArgs[svrArgsSz++] = strsep(&cursor, " \n");
+                break;
+            default:
+                /* Anything from cursor until end of line that isn't the above
+                 * is data for a paramter. Just up until the next newline in
+                 * the Args list. */
+                if (cliMode)
+                    cliArgs[cliArgsSz++] = strsep(&cursor, "\n");
+                else
+                    svrArgs[svrArgsSz++] = strsep(&cursor, "\n");
+                if (*cursor == 0)  /* eof */
+                    do_it = 1; 
+        }
+
+        if (svrArgsSz == MAX_ARGS || cliArgsSz == MAX_ARGS) {
+            fprintf(stderr, "too many arguments, forcing test run\n");
+            do_it = 1;
+        }
+
+        if (do_it) {
+            ret = execute_test_case(svrArgsSz, svrArgs, cliArgsSz, cliArgs,0,0);
+            /* don't repeat if not supported in build */
+            if (ret == 0) {
+                execute_test_case(svrArgsSz, svrArgs, cliArgsSz, cliArgs, 0, 1);
+                execute_test_case(svrArgsSz, svrArgs, cliArgsSz, cliArgs, 1, 0);
+                execute_test_case(svrArgsSz, svrArgs, cliArgsSz, cliArgs, 1, 1);
+            }
+            svrArgsSz = 1;
+            cliArgsSz = 1;
+            cliMode   = 0;
+        }
+    }
+
+    free(script);
+    args->return_code = 0;
+}
+
+
+int SuiteTest(void)
+{
+    func_args args;
+    char argv0[2][80];
+    char* myArgv[2];
+
+    printf(" Begin Cipher Suite Tests\n");
+
+    /* setup */
+    myArgv[0] = argv0[0];
+    myArgv[1] = argv0[1];
+    args.argv = myArgv;
+    strcpy(argv0[0], "SuiteTest");
+
+    (void)test_harness;
+
+    cipherSuiteCtx = wolfSSL_CTX_new(wolfTLSv1_2_client_method());
+    if (cipherSuiteCtx == NULL) {
+        printf("can't get cipher suite ctx\n");
+        exit(EXIT_FAILURE);  
+    }
+
+    /* default case */
+    args.argc = 1;
+    printf("starting default cipher suite tests\n");
+    test_harness(&args);
+    if (args.return_code != 0) {
+        printf("error from script %d\n", args.return_code);
+        exit(EXIT_FAILURE);  
+    }
+
+    /* any extra cases will need another argument */
+    args.argc = 2;
+
+#ifdef WOLFSSL_DTLS 
+    /* add dtls extra suites */
+    strcpy(argv0[1], "tests/test-dtls.conf");
+    printf("starting dtls extra cipher suite tests\n");
+    test_harness(&args);
+    if (args.return_code != 0) {
+        printf("error from script %d\n", args.return_code);
+        exit(EXIT_FAILURE);  
+    }
+#endif
+
+    printf(" End Cipher Suite Tests\n");
+
+    wolfSSL_CTX_free(cipherSuiteCtx);
+    wolfSSL_Cleanup();
+
+    return args.return_code;
+}
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/test-dtls.conf b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/test-dtls.conf
new file mode 100644
index 0000000..7a9c041
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/test-dtls.conf
@@ -0,0 +1,908 @@
+# server DTLSv1 DHE-RSA-CHACHA20-POLY1305
+-u
+-v 2
+-l DHE-RSA-CHACHA20-POLY1305
+
+# client DTLSv1 DHE-RSA-CHACHA20-POLY1305
+-u
+-v 2
+-l DHE-RSA-CHACHA20-POLY1305
+
+# server DTLSv1 ECDHE-RSA-CHACHA20-POLY1305
+-u
+-v 2 
+-l ECDHE-RSA-CHACHA20-POLY1305
+
+# client DTLSv1 ECDHE-RSA-CHACHA20-POLY1305
+-u
+-v 2
+-l ECDHE-RSA-CHACHA20-POLY1305
+
+# server DTLSv1 ECDHE-EDCSA-CHACHA20-POLY1305
+-u
+-v 2
+-l ECDHE-ECDSA-CHACHA20-POLY1305
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1 ECDHE-ECDSA-CHACHA20-POLY1305
+-u
+-v 2
+-l ECDHE-ECDSA-CHACHA20-POLY1305
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.2 DHE-RSA-CHACHA20-POLY1305
+-u
+-v 3
+-l DHE-RSA-CHACHA20-POLY1305
+
+# client DTLSv1.2 DHE-RSA-CHACHA20-POLY1305
+-u
+-v 3
+-l DHE-RSA-CHACHA20-POLY1305
+
+# server DTLSv1.2 ECDHE-RSA-CHACHA20-POLY1305
+-u
+-v 3 
+-l ECDHE-RSA-CHACHA20-POLY1305
+
+# client DTLSv1.2 ECDHE-RSA-CHACHA20-POLY1305
+-u
+-v 3
+-l ECDHE-RSA-CHACHA20-POLY1305
+
+# server DTLSv1.2 ECDHE-EDCSA-CHACHA20-POLY1305
+-u
+-v 3
+-l ECDHE-ECDSA-CHACHA20-POLY1305
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDHE-ECDSA-CHACHA20-POLY1305
+-u
+-v 3
+-l ECDHE-ECDSA-CHACHA20-POLY1305
+-A ./certs/server-ecc.pem
+
+# server DTLSv1 RC4-SHA
+-u
+-v 2
+-l RC4-SHA
+
+# client DTLSv1 RC4-SHA
+-u
+-v 2
+-l RC4-SHA
+
+# server DTLSv1.2 RC4-SHA
+-u
+-v 3
+-l RC4-SHA
+
+# client DTLSv1.2 RC4-SHA
+-u
+-v 3
+-l RC4-SHA
+
+# server DTLSv1 DES-CBC3-SHA
+-u
+-v 2
+-l DES-CBC3-SHA
+
+# client DTLSv1 DES-CBC3-SHA
+-u
+-v 2
+-l DES-CBC3-SHA
+
+# server DTLSv1.2 DES-CBC3-SHA
+-u
+-v 3
+-l DES-CBC3-SHA
+
+# client DTLSv1.2 DES-CBC3-SHA
+-u
+-v 3
+-l DES-CBC3-SHA
+
+# server DTLSv1 AES128-SHA
+-u
+-v 2
+-l AES128-SHA
+
+# client DTLSv1 AES128-SHA
+-u
+-v 2
+-l AES128-SHA
+
+# server DTLSv1.2 AES128-SHA
+-u
+-v 3
+-l AES128-SHA
+
+# client DTLSv1.2 AES128-SHA
+-u
+-v 3
+-l AES128-SHA
+
+# server DTLSv1 AES256-SHA
+-u
+-v 2
+-l AES256-SHA
+
+# client DTLSv1 AES256-SHA
+-u
+-v 2
+-l AES256-SHA
+
+# server DTLSv1.2 AES256-SHA
+-u
+-v 3
+-l AES256-SHA
+
+# client DTLSv1.2 AES256-SHA
+-u
+-v 3
+-l AES256-SHA
+
+# server DTLSv1 AES128-SHA256
+-u
+-v 2
+-l AES128-SHA256
+
+# client DTLSv1 AES128-SHA256
+-u
+-v 2
+-l AES128-SHA256
+
+# server DTLSv1.2 AES128-SHA256
+-u
+-v 3
+-l AES128-SHA256
+
+# client DTLSv1.2 AES128-SHA256
+-u
+-v 3
+-l AES128-SHA256
+
+# server DTLSv1 AES256-SHA256
+-u
+-v 2
+-l AES256-SHA256
+
+# client DTLSv1 AES256-SHA256
+-u
+-v 2
+-l AES256-SHA256
+
+# server DTLSv1.2 AES256-SHA256
+-u
+-v 3
+-l AES256-SHA256
+
+# client DTLSv1.2 AES256-SHA256
+-u
+-v 3
+-l AES256-SHA256
+
+# server DTLSv1 ECDHE-RSA-RC4
+-u
+-v 2
+-l ECDHE-RSA-RC4-SHA
+
+# client DTLSv1 ECDHE-RSA-RC4
+-u
+-v 2
+-l ECDHE-RSA-RC4-SHA
+
+# server DTLSv1.1 ECDHE-RSA-DES3
+-u
+-v 2
+-l ECDHE-RSA-DES-CBC3-SHA
+
+# client DTLSv1.1 ECDHE-RSA-DES3
+-u
+-v 2
+-l ECDHE-RSA-DES-CBC3-SHA
+
+# server DTLSv1.1 ECDHE-RSA-AES128 
+-u
+-v 2
+-l ECDHE-RSA-AES128-SHA
+
+# client DTLSv1.1 ECDHE-RSA-AES128 
+-u
+-v 2
+-l ECDHE-RSA-AES128-SHA
+
+# server DTLSv1.1 ECDHE-RSA-AES256
+-u
+-v 2
+-l ECDHE-RSA-AES256-SHA
+
+# client DTLSv1.1 ECDHE-RSA-AES256
+-u
+-v 2
+-l ECDHE-RSA-AES256-SHA
+
+# server DTLSv1.2 ECDHE-RSA-RC4
+-u
+-v 3
+-l ECDHE-RSA-RC4-SHA
+
+# client DTLSv1.2 ECDHE-RSA-RC4
+-u
+-v 3
+-l ECDHE-RSA-RC4-SHA
+
+# server DTLSv1.2 ECDHE-RSA-DES3
+-u
+-v 3
+-l ECDHE-RSA-DES-CBC3-SHA
+
+# client DTLSv1.2 ECDHE-RSA-DES3
+-u
+-v 3
+-l ECDHE-RSA-DES-CBC3-SHA
+
+# server DTLSv1.2 ECDHE-RSA-AES128 
+-u
+-v 3
+-l ECDHE-RSA-AES128-SHA
+
+# client DTLSv1.2 ECDHE-RSA-AES128 
+-u
+-v 3
+-l ECDHE-RSA-AES128-SHA
+
+# server DTLSv1.2 ECDHE-RSA-AES128-SHA256
+-u
+-v 3
+-l ECDHE-RSA-AES128-SHA256
+
+# client DTLSv1.2 ECDHE-RSA-AES128-SHA256 
+-u
+-v 3
+-l ECDHE-RSA-AES128-SHA256
+
+# server DTLSv1.2 ECDHE-RSA-AES256
+-u
+-v 3
+-l ECDHE-RSA-AES256-SHA
+
+# client DTLSv1.2 ECDHE-RSA-AES256
+-u
+-v 3
+-l ECDHE-RSA-AES256-SHA
+
+# server DTLSv1.1 ECDHE-EDCSA-RC4
+-u
+-v 2
+-l ECDHE-ECDSA-RC4-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.1 ECDHE-ECDSA-RC4
+-u
+-v 2
+-l ECDHE-ECDSA-RC4-SHA
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.1 ECDHE-ECDSA-DES3
+-u
+-v 2
+-l ECDHE-ECDSA-DES-CBC3-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.1 ECDHE-ECDSA-DES3
+-u
+-v 2
+-l ECDHE-ECDSA-DES-CBC3-SHA
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.1 ECDHE-ECDSA-AES128 
+-u
+-v 2
+-l ECDHE-ECDSA-AES128-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.1 ECDHE-ECDSA-AES128 
+-u
+-v 2
+-l ECDHE-ECDSA-AES128-SHA
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.1 ECDHE-ECDSA-AES256
+-u
+-v 2
+-l ECDHE-ECDSA-AES256-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.1 ECDHE-ECDSA-AES256
+-u
+-v 2
+-l ECDHE-ECDSA-AES256-SHA
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.2 ECDHE-ECDSA-RC4
+-u
+-v 3
+-l ECDHE-ECDSA-RC4-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDHE-ECDSA-RC4
+-u
+-v 3
+-l ECDHE-ECDSA-RC4-SHA
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.2 ECDHE-ECDSA-DES3
+-u
+-v 3
+-l ECDHE-ECDSA-DES-CBC3-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDHE-ECDSA-DES3
+-u
+-v 3
+-l ECDHE-ECDSA-DES-CBC3-SHA
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.2 ECDHE-ECDSA-AES128 
+-u
+-v 3
+-l ECDHE-ECDSA-AES128-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDHE-ECDSA-AES128 
+-u
+-v 3
+-l ECDHE-ECDSA-AES128-SHA
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.2 ECDHE-ECDSA-AES128-SHA256
+-u
+-v 3
+-l ECDHE-ECDSA-AES128-SHA256
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDHE-ECDSA-AES128-SHA256
+-u
+-v 3
+-l ECDHE-ECDSA-AES128-SHA256
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.2 ECDHE-ECDSA-AES256
+-u
+-v 3
+-l ECDHE-ECDSA-AES256-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDHE-ECDSA-AES256
+-u
+-v 3
+-l ECDHE-ECDSA-AES256-SHA
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.1 ECDH-RSA-RC4
+-u
+-v 2
+-l ECDH-RSA-RC4-SHA
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.1 ECDH-RSA-RC4
+-u
+-v 2
+-l ECDH-RSA-RC4-SHA
+
+# server DTLSv1.1 ECDH-RSA-DES3
+-u
+-v 2
+-l ECDH-RSA-DES-CBC3-SHA
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.1 ECDH-RSA-DES3
+-u
+-v 2
+-l ECDH-RSA-DES-CBC3-SHA
+
+# server DTLSv1.1 ECDH-RSA-AES128 
+-u
+-v 2
+-l ECDH-RSA-AES128-SHA
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.1 ECDH-RSA-AES128 
+-u
+-v 2
+-l ECDH-RSA-AES128-SHA
+
+# server DTLSv1.1 ECDH-RSA-AES256
+-u
+-v 2
+-l ECDH-RSA-AES256-SHA
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.1 ECDH-RSA-AES256
+-u
+-v 2
+-l ECDH-RSA-AES256-SHA
+
+# server DTLSv1.2 ECDH-RSA-RC4
+-u
+-v 3
+-l ECDH-RSA-RC4-SHA
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDH-RSA-RC4
+-u
+-v 3
+-l ECDH-RSA-RC4-SHA
+
+# server DTLSv1.2 ECDH-RSA-DES3
+-u
+-v 3
+-l ECDH-RSA-DES-CBC3-SHA
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDH-RSA-DES3
+-u
+-v 3
+-l ECDH-RSA-DES-CBC3-SHA
+
+# server DTLSv1.2 ECDH-RSA-AES128 
+-u
+-v 3
+-l ECDH-RSA-AES128-SHA
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDH-RSA-AES128 
+-u
+-v 3
+-l ECDH-RSA-AES128-SHA
+
+# server DTLSv1.2 ECDH-RSA-AES128-SHA256 
+-u
+-v 3
+-l ECDH-RSA-AES128-SHA256
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDH-RSA-AES128-SHA256 
+-u
+-v 3
+-l ECDH-RSA-AES128-SHA256
+
+# server DTLSv1.2 ECDH-RSA-AES256
+-u
+-v 3
+-l ECDH-RSA-AES256-SHA
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDH-RSA-AES256
+-u
+-v 3
+-l ECDH-RSA-AES256-SHA
+
+# server DTLSv1.1 ECDH-EDCSA-RC4
+-u
+-v 2
+-l ECDH-ECDSA-RC4-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.1 ECDH-ECDSA-RC4
+-u
+-v 2
+-l ECDH-ECDSA-RC4-SHA
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.1 ECDH-ECDSA-DES3
+-u
+-v 2
+-l ECDH-ECDSA-DES-CBC3-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.1 ECDH-ECDSA-DES3
+-u
+-v 2
+-l ECDH-ECDSA-DES-CBC3-SHA
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.1 ECDH-ECDSA-AES128 
+-u
+-v 2
+-l ECDH-ECDSA-AES128-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.1 ECDH-ECDSA-AES128 
+-u
+-v 2
+-l ECDH-ECDSA-AES128-SHA
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.1 ECDH-ECDSA-AES256
+-u
+-v 2
+-l ECDH-ECDSA-AES256-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.1 ECDH-ECDSA-AES256
+-u
+-v 2
+-l ECDH-ECDSA-AES256-SHA
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.2 ECDHE-ECDSA-RC4
+-u
+-v 3
+-l ECDH-ECDSA-RC4-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDH-ECDSA-RC4
+-u
+-v 3
+-l ECDH-ECDSA-RC4-SHA
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.2 ECDH-ECDSA-DES3
+-u
+-v 3
+-l ECDH-ECDSA-DES-CBC3-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDH-ECDSA-DES3
+-u
+-v 3
+-l ECDH-ECDSA-DES-CBC3-SHA
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.2 ECDH-ECDSA-AES128 
+-u
+-v 3
+-l ECDH-ECDSA-AES128-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDH-ECDSA-AES128 
+-u
+-v 3
+-l ECDH-ECDSA-AES128-SHA
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.2 ECDH-ECDSA-AES128-SHA256
+-u
+-v 3
+-l ECDH-ECDSA-AES128-SHA256
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDH-ECDSA-AES128-SHA256 
+-u
+-v 3
+-l ECDH-ECDSA-AES128-SHA256
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.2 ECDH-ECDSA-AES256
+-u
+-v 3
+-l ECDH-ECDSA-AES256-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDH-ECDSA-AES256
+-u
+-v 3
+-l ECDH-ECDSA-AES256-SHA
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.2 ECDHE-RSA-AES256-SHA384 
+-u
+-v 3
+-l ECDHE-RSA-AES256-SHA384
+
+# client DTLSv1.2 ECDHE-RSA-AES256-SHA384 
+-u
+-v 3
+-l ECDHE-RSA-AES256-SHA384
+
+# server DTLSv1.2 ECDHE-ECDSA-AES256-SHA384
+-u
+-v 3
+-l ECDHE-ECDSA-AES256-SHA384
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDHE-ECDSA-AES256-SHA384
+-u
+-v 3
+-l ECDHE-ECDSA-AES256-SHA384
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.2 ECDH-RSA-AES256-SHA384 
+-u
+-v 3
+-l ECDH-RSA-AES256-SHA384
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDH-RSA-AES256-SHA384 
+-u
+-v 3
+-l ECDH-RSA-AES256-SHA384
+
+# server DTLSv1.2 ECDH-ECDSA-AES256-SHA384
+-u
+-v 3
+-l ECDH-ECDSA-AES256-SHA384
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDH-ECDSA-AES256-SHA384 
+-u
+-v 3
+-l ECDH-ECDSA-AES256-SHA384
+-A ./certs/server-ecc.pem
+
+# server DTLSv1 PSK-AES128
+-s
+-u
+-v 2
+-l PSK-AES128-CBC-SHA
+
+# client DTLSv1 PSK-AES128
+-s
+-u
+-v 2
+-l PSK-AES128-CBC-SHA
+
+# server DTLSv1 PSK-AES256
+-s
+-u
+-v 2
+-l PSK-AES256-CBC-SHA
+
+# client DTLSv1 PSK-AES256
+-s
+-u
+-v 2
+-l PSK-AES256-CBC-SHA
+
+# server DTLSv1.2 PSK-AES128
+-s
+-u
+-v 3
+-l PSK-AES128-CBC-SHA
+
+# client DTLSv1.2 PSK-AES128
+-s
+-u
+-v 3
+-l PSK-AES128-CBC-SHA
+
+# server DTLSv1.2 PSK-AES256
+-s
+-u
+-v 3
+-l PSK-AES256-CBC-SHA
+
+# client DTLSv1.2 PSK-AES256
+-s
+-u
+-v 3
+-l PSK-AES256-CBC-SHA
+
+# server DTLSv1.2 PSK-AES128-SHA256
+-s
+-u
+-v 3
+-l PSK-AES128-CBC-SHA256
+
+# client DTLSv1.2 PSK-AES128-SHA256
+-s
+-u
+-v 3
+-l PSK-AES128-CBC-SHA256
+
+# server DTLSv1.2 PSK-AES256-SHA384
+-s
+-u
+-v 3
+-l PSK-AES256-CBC-SHA384
+
+# client DTLSv1.2 PSK-AES256-SHA384
+-s
+-u
+-v 3
+-l PSK-AES256-CBC-SHA384
+
+# server DTLSv1.2 ECDHE-ECDSA-AES128-GCM-SHA256 
+-u
+-v 3
+-l ECDHE-ECDSA-AES128-GCM-SHA256
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDHE-ECDSA-AES128-GCM-SHA256 
+-u
+-v 3
+-l ECDHE-ECDSA-AES128-GCM-SHA256
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.2 ECDHE-ECDSA-AES256-GCM-SHA384
+-u
+-v 3
+-l ECDHE-ECDSA-AES256-GCM-SHA384
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDHE-ECDSA-AES256-GCM-SHA384
+-u
+-v 3
+-l ECDHE-ECDSA-AES256-GCM-SHA384
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.2 ECDH-ECDSA-AES128-GCM-SHA256 
+-u
+-v 3
+-l ECDH-ECDSA-AES128-GCM-SHA256
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDH-ECDSA-AES128-GCM-SHA256 
+-u
+-v 3
+-l ECDH-ECDSA-AES128-GCM-SHA256
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.2 ECDH-ECDSA-AES256-GCM-SHA384
+-u
+-v 3
+-l ECDH-ECDSA-AES256-GCM-SHA384
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDH-ECDSA-AES256-GCM-SHA384
+-u
+-v 3
+-l ECDH-ECDSA-AES256-GCM-SHA384
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.2 ECDHE-RSA-AES128-GCM-SHA256 
+-u
+-v 3
+-l ECDHE-RSA-AES128-GCM-SHA256
+
+# client DTLSv1.2 ECDHE-RSA-AES128-GCM-SHA256 
+-u
+-v 3
+-l ECDHE-RSA-AES128-GCM-SHA256
+
+# server DTLSv1.2 ECDHE-RSA-AES256-GCM-SHA384
+-u
+-v 3
+-l ECDHE-RSA-AES256-GCM-SHA384
+
+# client DTLSv1.2 ECDHE-RSA-AES256-GCM-SHA384
+-u
+-v 3
+-l ECDHE-RSA-AES256-GCM-SHA384
+
+# server DTLSv1.2 ECDH-RSA-AES128-GCM-SHA256 
+-u
+-v 3
+-l ECDH-RSA-AES128-GCM-SHA256
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDH-RSA-AES128-GCM-SHA256 
+-u
+-v 3
+-l ECDH-RSA-AES128-GCM-SHA256
+
+# server DTLSv1.2 ECDH-RSA-AES256-GCM-SHA384
+-u
+-v 3
+-l ECDH-RSA-AES256-GCM-SHA384
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDH-RSA-AES256-GCM-SHA384
+-u
+-v 3
+-l ECDH-RSA-AES256-GCM-SHA384
+
+# server DTLSv1.2 PSK-AES128-GCM-SHA256
+-u
+-s
+-v 3
+-l PSK-AES128-GCM-SHA256
+
+# client DTLSv1.2 PSK-AES128-GCM-SHA256
+-u
+-s
+-v 3
+-l PSK-AES128-GCM-SHA256
+
+# server DTLSv1.2 PSK-AES256-GCM-SHA384
+-u
+-s
+-v 3
+-l PSK-AES256-GCM-SHA384
+
+# client DTLSv1.2 PSK-AES256-GCM-SHA384
+-u
+-s
+-v 3
+-l PSK-AES256-GCM-SHA384
+
+# server DTLSv1.2 ECDHE-ECDSA-AES128-CCM-8
+-u
+-v 3
+-l ECDHE-ECDSA-AES128-CCM-8
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDHE-ECDSA-AES128-CCM-8
+-u
+-v 3
+-l ECDHE-ECDSA-AES128-CCM-8
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.2 ECDHE-ECDSA-AES256-CCM-8
+-u
+-v 3
+-l ECDHE-ECDSA-AES256-CCM-8
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client DTLSv1.2 ECDHE-ECDSA-AES256-CCM-8
+-u
+-v 3
+-l ECDHE-ECDSA-AES256-CCM-8
+-A ./certs/server-ecc.pem
+
+# server DTLSv1.2 ADH-AES128-SHA
+-u
+-a
+-v 3
+-l ADH-AES128-SHA
+
+# client DTLSv1.2 ADH-AES128-SHA
+-u
+-a
+-v 3
+-l ADH-AES128-SHA
+
+# server DTLSv1.0 ADH-AES128-SHA
+-u
+-a
+-v 2
+-l ADH-AES128-SHA
+
+# client DTLSv1.0 ADH-AES128-SHA
+-u
+-a
+-v 2
+-l ADH-AES128-SHA
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/test.conf b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/test.conf
new file mode 100644
index 0000000..c949c20
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/test.conf
@@ -0,0 +1,2035 @@
+# server TLSv1 DHE-RSA-CHACHA20-POLY1305
+-v 1
+-l DHE-RSA-CHACHA20-POLY1305
+
+# client TLSv1 DHE-RSA-CHACHA20-POLY1305
+-v 1
+-l DHE-RSA-CHACHA20-POLY1305
+
+# server TLSv1 ECDHE-EDCSA-CHACHA20-POLY1305
+-v 1
+-l ECDHE-ECDSA-CHACHA20-POLY1305
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1 ECDHE-ECDSA-CHACHA20-POLY1305
+-v 1
+-l ECDHE-ECDSA-CHACHA20-POLY1305
+-A ./certs/server-ecc.pem
+
+# server TLSv1 ECDHE-RSA-CHACHA20-POLY1305
+-v 1 
+-l ECDHE-RSA-CHACHA20-POLY1305
+
+# client TLSv1 ECDHE-RSA-CHACHA20-POLY1305
+-v 1
+-l ECDHE-RSA-CHACHA20-POLY1305
+
+# server TLSv1.1 DHE-RSA-CHACHA20-POLY1305
+-v 2
+-l DHE-RSA-CHACHA20-POLY1305
+
+# client TLSv1.1 DHE-RSA-CHACHA20-POLY1305
+-v 2
+-l DHE-RSA-CHACHA20-POLY1305
+
+# server TLSv1.1 ECDHE-RSA-CHACHA20-POLY1305
+-v 2 
+-l ECDHE-RSA-CHACHA20-POLY1305
+
+# client TLSv1.1 ECDHE-RSA-CHACHA20-POLY1305
+-v 2
+-l ECDHE-RSA-CHACHA20-POLY1305
+
+# server TLSv1.1 ECDHE-EDCSA-CHACHA20-POLY1305
+-v 2
+-l ECDHE-ECDSA-CHACHA20-POLY1305
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.1 ECDHE-ECDSA-CHACHA20-POLY1305
+-v 2
+-l ECDHE-ECDSA-CHACHA20-POLY1305
+-A ./certs/server-ecc.pem
+
+# server TLSv1.2 DHE-RSA-CHACHA20-POLY1305
+-v 3
+-l DHE-RSA-CHACHA20-POLY1305
+
+# client TLSv1.2 DHE-RSA-CHACHA20-POLY1305
+-v 3
+-l DHE-RSA-CHACHA20-POLY1305
+
+# server TLSv1.2 ECDHE-RSA-CHACHA20-POLY1305
+-v 3 
+-l ECDHE-RSA-CHACHA20-POLY1305
+
+# client TLSv1.2 ECDHE-RSA-CHACHA20-POLY1305
+-v 3
+-l ECDHE-RSA-CHACHA20-POLY1305
+
+# server TLSv1.2 ECDHE-EDCSA-CHACHA20-POLY1305
+-v 3
+-l ECDHE-ECDSA-CHACHA20-POLY1305
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDHE-ECDSA-CHACHA20-POLY1305
+-v 3
+-l ECDHE-ECDSA-CHACHA20-POLY1305
+-A ./certs/server-ecc.pem
+
+# server SSLv3 RC4-SHA
+-v 0
+-l RC4-SHA
+
+# client SSLv3 RC4-SHA
+-v 0
+-l RC4-SHA
+
+# server SSLv3 RC4-MD5
+-v 0
+-l RC4-MD5
+
+# client SSLv3 RC4-MD5
+-v 0
+-l RC4-MD5
+
+# server SSLv3 DES-CBC3-SHA
+-v 0
+-l DES-CBC3-SHA
+
+# client SSLv3 DES-CBC3-SHA
+-v 0
+-l DES-CBC3-SHA
+
+# server TLSv1 RC4-SHA
+-v 1
+-l RC4-SHA
+
+# client TLSv1 RC4-SHA
+-v 1
+-l RC4-SHA
+
+# server TLSv1 RC4-MD5
+-v 1
+-l RC4-MD5
+
+# client TLSv1 RC4-MD5
+-v 1
+-l RC4-MD5
+
+# server TLSv1 DES-CBC3-SHA
+-v 1
+-l DES-CBC3-SHA
+
+# client TLSv1 DES-CBC3-SHA
+-v 1
+-l DES-CBC3-SHA
+
+# server TLSv1 AES128-SHA
+-v 1
+-l AES128-SHA
+
+# client TLSv1 AES128-SHA
+-v 1
+-l AES128-SHA
+
+# server TLSv1 AES256-SHA
+-v 1
+-l AES256-SHA
+
+# client TLSv1 AES256-SHA
+-v 1
+-l AES256-SHA
+
+# server TLSv1 AES128-SHA256
+-v 1
+-l AES128-SHA256
+
+# client TLSv1 AES128-SHA256
+-v 1
+-l AES128-SHA256
+
+# server TLSv1 AES256-SHA256
+-v 1
+-l AES256-SHA256
+
+# client TLSv1 AES256-SHA256
+-v 1
+-l AES256-SHA256
+
+# server TLSv1.1 RC4-SHA
+-v 2
+-l RC4-SHA
+
+# client TLSv1.1 RC4-SHA
+-v 2
+-l RC4-SHA
+
+# server TLSv1.1 RC4-MD5
+-v 2
+-l RC4-MD5
+
+# client TLSv1.1 RC4-MD5
+-v 2
+-l RC4-MD5
+
+# server TLSv1.1 DES-CBC3-SHA
+-v 2
+-l DES-CBC3-SHA
+
+# client TLSv1.1 DES-CBC3-SHA
+-v 2
+-l DES-CBC3-SHA
+
+# server TLSv1.1 AES128-SHA
+-v 2
+-l AES128-SHA
+
+# client TLSv1.1 AES128-SHA
+-v 2
+-l AES128-SHA
+
+# server TLSv1.1 AES256-SHA
+-v 2
+-l AES256-SHA
+
+# client TLSv1.1 AES256-SHA
+-v 2
+-l AES256-SHA
+
+# server TLSv1.1 AES128-SHA256
+-v 2
+-l AES128-SHA256
+
+# client TLSv1.1 AES128-SHA256
+-v 2
+-l AES128-SHA256
+
+# server TLSv1.1 AES256-SHA256
+-v 2
+-l AES256-SHA256
+
+# client TLSv1.1 AES256-SHA256
+-v 2
+-l AES256-SHA256
+
+# server TLSv1.2 RC4-SHA
+-v 3
+-l RC4-SHA
+
+# client TLSv1.2 RC4-SHA
+-v 3
+-l RC4-SHA
+
+# server TLSv1.2 RC4-MD5
+-v 3
+-l RC4-MD5
+
+# client TLSv1.2 RC4-MD5
+-v 3
+-l RC4-MD5
+
+# server TLSv1.2 DES-CBC3-SHA
+-v 3
+-l DES-CBC3-SHA
+
+# client TLSv1.2 DES-CBC3-SHA
+-v 3
+-l DES-CBC3-SHA
+
+# server TLSv1.2 AES128-SHA
+-v 3
+-l AES128-SHA
+
+# client TLSv1.2 AES128-SHA
+-v 3
+-l AES128-SHA
+
+# server TLSv1.2 AES256-SHA
+-v 3
+-l AES256-SHA
+
+# client TLSv1.2 AES256-SHA
+-v 3
+-l AES256-SHA
+
+# server TLSv1.2 AES128-SHA256
+-v 3
+-l AES128-SHA256
+
+# client TLSv1.2 AES128-SHA256
+-v 3
+-l AES128-SHA256
+
+# server TLSv1.2 AES256-SHA256
+-v 3
+-l AES256-SHA256
+
+# client TLSv1.2 AES256-SHA256
+-v 3
+-l AES256-SHA256
+
+# server TLSv1 ECDHE-RSA-RC4
+-v 1
+-l ECDHE-RSA-RC4-SHA
+
+# client TLSv1 ECDHE-RSA-RC4
+-v 1
+-l ECDHE-RSA-RC4-SHA
+
+# server TLSv1 ECDHE-RSA-DES3
+-v 1
+-l ECDHE-RSA-DES-CBC3-SHA
+
+# client TLSv1 ECDHE-RSA-DES3
+-v 1
+-l ECDHE-RSA-DES-CBC3-SHA
+
+# server TLSv1 ECDHE-RSA-AES128 
+-v 1
+-l ECDHE-RSA-AES128-SHA
+
+# client TLSv1 ECDHE-RSA-AES128 
+-v 1
+-l ECDHE-RSA-AES128-SHA
+
+# server TLSv1 ECDHE-RSA-AES256
+-v 1
+-l ECDHE-RSA-AES256-SHA
+
+# client TLSv1 ECDHE-RSA-AES256
+-v 1
+-l ECDHE-RSA-AES256-SHA
+
+# server TLSv1.1 ECDHE-RSA-RC4
+-v 2
+-l ECDHE-RSA-RC4-SHA
+
+# client TLSv1.1 ECDHE-RSA-RC4
+-v 2
+-l ECDHE-RSA-RC4-SHA
+
+# server TLSv1.1 ECDHE-RSA-DES3
+-v 2
+-l ECDHE-RSA-DES-CBC3-SHA
+
+# client TLSv1.1 ECDHE-RSA-DES3
+-v 2
+-l ECDHE-RSA-DES-CBC3-SHA
+
+# server TLSv1.1 ECDHE-RSA-AES128 
+-v 2
+-l ECDHE-RSA-AES128-SHA
+
+# client TLSv1.1 ECDHE-RSA-AES128 
+-v 2
+-l ECDHE-RSA-AES128-SHA
+
+# server TLSv1.1 ECDHE-RSA-AES256
+-v 2
+-l ECDHE-RSA-AES256-SHA
+
+# client TLSv1.1 ECDHE-RSA-AES256
+-v 2
+-l ECDHE-RSA-AES256-SHA
+
+# server TLSv1.2 ECDHE-RSA-RC4
+-v 3
+-l ECDHE-RSA-RC4-SHA
+
+# client TLSv1.2 ECDHE-RSA-RC4
+-v 3
+-l ECDHE-RSA-RC4-SHA
+
+# server TLSv1.2 ECDHE-RSA-DES3
+-v 3
+-l ECDHE-RSA-DES-CBC3-SHA
+
+# client TLSv1.2 ECDHE-RSA-DES3
+-v 3
+-l ECDHE-RSA-DES-CBC3-SHA
+
+# server TLSv1.2 ECDHE-RSA-AES128 
+-v 3
+-l ECDHE-RSA-AES128-SHA
+
+# client TLSv1.2 ECDHE-RSA-AES128 
+-v 3
+-l ECDHE-RSA-AES128-SHA
+
+# server TLSv1.2 ECDHE-RSA-AES128-SHA256
+-v 3
+-l ECDHE-RSA-AES128-SHA256
+
+# client TLSv1.2 ECDHE-RSA-AES128-SHA256 
+-v 3
+-l ECDHE-RSA-AES128-SHA256
+
+# server TLSv1.2 ECDHE-RSA-AES256
+-v 3
+-l ECDHE-RSA-AES256-SHA
+
+# client TLSv1.2 ECDHE-RSA-AES256
+-v 3
+-l ECDHE-RSA-AES256-SHA
+
+# server TLSv1 ECDHE-ECDSA-RC4
+-v 1
+-l ECDHE-ECDSA-RC4-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1 ECDHE-ECDSA-RC4
+-v 1
+-l ECDHE-ECDSA-RC4-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1 ECDHE-ECDSA-DES3
+-v 1
+-l ECDHE-ECDSA-DES-CBC3-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1 ECDHE-ECDSA-DES3
+-v 1
+-l ECDHE-ECDSA-DES-CBC3-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1 ECDHE-ECDSA-AES128 
+-v 1
+-l ECDHE-ECDSA-AES128-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1 ECDHE-ECDSA-AES128 
+-v 1
+-l ECDHE-ECDSA-AES128-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1 ECDHE-ECDSA-AES256
+-v 1
+-l ECDHE-ECDSA-AES256-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1 ECDHE-ECDSA-AES256
+-v 1
+-l ECDHE-ECDSA-AES256-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1.1 ECDHE-EDCSA-RC4
+-v 2
+-l ECDHE-ECDSA-RC4-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.1 ECDHE-ECDSA-RC4
+-v 2
+-l ECDHE-ECDSA-RC4-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1.1 ECDHE-ECDSA-DES3
+-v 2
+-l ECDHE-ECDSA-DES-CBC3-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.1 ECDHE-ECDSA-DES3
+-v 2
+-l ECDHE-ECDSA-DES-CBC3-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1.1 ECDHE-ECDSA-AES128 
+-v 2
+-l ECDHE-ECDSA-AES128-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.1 ECDHE-ECDSA-AES128 
+-v 2
+-l ECDHE-ECDSA-AES128-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1.1 ECDHE-ECDSA-AES256
+-v 2
+-l ECDHE-ECDSA-AES256-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.1 ECDHE-ECDSA-AES256
+-v 2
+-l ECDHE-ECDSA-AES256-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1.2 ECDHE-ECDSA-RC4
+-v 3
+-l ECDHE-ECDSA-RC4-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDHE-ECDSA-RC4
+-v 3
+-l ECDHE-ECDSA-RC4-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1.2 ECDHE-ECDSA-DES3
+-v 3
+-l ECDHE-ECDSA-DES-CBC3-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDHE-ECDSA-DES3
+-v 3
+-l ECDHE-ECDSA-DES-CBC3-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1.2 ECDHE-ECDSA-AES128 
+-v 3
+-l ECDHE-ECDSA-AES128-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDHE-ECDSA-AES128 
+-v 3
+-l ECDHE-ECDSA-AES128-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1.2 ECDHE-ECDSA-AES128-SHA256
+-v 3
+-l ECDHE-ECDSA-AES128-SHA256
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDHE-ECDSA-AES128-SHA256
+-v 3
+-l ECDHE-ECDSA-AES128-SHA256
+-A ./certs/server-ecc.pem
+
+# server TLSv1.2 ECDHE-ECDSA-AES256
+-v 3
+-l ECDHE-ECDSA-AES256-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDHE-ECDSA-AES256
+-v 3
+-l ECDHE-ECDSA-AES256-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1 ECDH-RSA-RC4
+-v 1
+-l ECDH-RSA-RC4-SHA
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1 ECDH-RSA-RC4
+-v 1
+-l ECDH-RSA-RC4-SHA
+
+# server TLSv1 ECDH-RSA-DES3
+-v 1
+-l ECDH-RSA-DES-CBC3-SHA
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1 ECDH-RSA-DES3
+-v 1
+-l ECDH-RSA-DES-CBC3-SHA
+
+# server TLSv1 ECDH-RSA-AES128 
+-v 1
+-l ECDH-RSA-AES128-SHA
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1 ECDH-RSA-AES128 
+-v 1
+-l ECDH-RSA-AES128-SHA
+
+# server TLSv1 ECDH-RSA-AES256
+-v 1
+-l ECDH-RSA-AES256-SHA
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1 ECDH-RSA-AES256
+-v 1
+-l ECDH-RSA-AES256-SHA
+
+# server TLSv1.1 ECDH-RSA-RC4
+-v 2
+-l ECDH-RSA-RC4-SHA
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.1 ECDH-RSA-RC4
+-v 2
+-l ECDH-RSA-RC4-SHA
+
+# server TLSv1.1 ECDH-RSA-DES3
+-v 2
+-l ECDH-RSA-DES-CBC3-SHA
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.1 ECDH-RSA-DES3
+-v 2
+-l ECDH-RSA-DES-CBC3-SHA
+
+# server TLSv1.1 ECDH-RSA-AES128 
+-v 2
+-l ECDH-RSA-AES128-SHA
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.1 ECDH-RSA-AES128 
+-v 2
+-l ECDH-RSA-AES128-SHA
+
+# server TLSv1.1 ECDH-RSA-AES256
+-v 2
+-l ECDH-RSA-AES256-SHA
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.1 ECDH-RSA-AES256
+-v 2
+-l ECDH-RSA-AES256-SHA
+
+# server TLSv1.2 ECDH-RSA-RC4
+-v 3
+-l ECDH-RSA-RC4-SHA
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDH-RSA-RC4
+-v 3
+-l ECDH-RSA-RC4-SHA
+
+# server TLSv1.2 ECDH-RSA-DES3
+-v 3
+-l ECDH-RSA-DES-CBC3-SHA
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDH-RSA-DES3
+-v 3
+-l ECDH-RSA-DES-CBC3-SHA
+
+# server TLSv1.2 ECDH-RSA-AES128 
+-v 3
+-l ECDH-RSA-AES128-SHA
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDH-RSA-AES128 
+-v 3
+-l ECDH-RSA-AES128-SHA
+
+# server TLSv1.2 ECDH-RSA-AES128-SHA256 
+-v 3
+-l ECDH-RSA-AES128-SHA256
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDH-RSA-AES128-SHA256 
+-v 3
+-l ECDH-RSA-AES128-SHA256
+
+# server TLSv1.2 ECDH-RSA-AES256
+-v 3
+-l ECDH-RSA-AES256-SHA
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDH-RSA-AES256
+-v 3
+-l ECDH-RSA-AES256-SHA
+
+# server TLSv1 ECDH-ECDSA-RC4
+-v 1
+-l ECDH-ECDSA-RC4-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1 ECDH-ECDSA-RC4
+-v 1
+-l ECDH-ECDSA-RC4-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1 ECDH-ECDSA-DES3
+-v 1
+-l ECDH-ECDSA-DES-CBC3-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1 ECDH-ECDSA-DES3
+-v 1
+-l ECDH-ECDSA-DES-CBC3-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1 ECDH-ECDSA-AES128 
+-v 1
+-l ECDH-ECDSA-AES128-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1 ECDH-ECDSA-AES128 
+-v 1
+-l ECDH-ECDSA-AES128-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1 ECDH-ECDSA-AES256
+-v 1
+-l ECDH-ECDSA-AES256-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1 ECDH-ECDSA-AES256
+-v 1
+-l ECDH-ECDSA-AES256-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1.1 ECDH-EDCSA-RC4
+-v 2
+-l ECDH-ECDSA-RC4-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.1 ECDH-ECDSA-RC4
+-v 2
+-l ECDH-ECDSA-RC4-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1.1 ECDH-ECDSA-DES3
+-v 2
+-l ECDH-ECDSA-DES-CBC3-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.1 ECDH-ECDSA-DES3
+-v 2
+-l ECDH-ECDSA-DES-CBC3-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1.1 ECDH-ECDSA-AES128 
+-v 2
+-l ECDH-ECDSA-AES128-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.1 ECDH-ECDSA-AES128 
+-v 2
+-l ECDH-ECDSA-AES128-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1.1 ECDH-ECDSA-AES256
+-v 2
+-l ECDH-ECDSA-AES256-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.1 ECDH-ECDSA-AES256
+-v 2
+-l ECDH-ECDSA-AES256-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1.2 ECDHE-ECDSA-RC4
+-v 3
+-l ECDH-ECDSA-RC4-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDH-ECDSA-RC4
+-v 3
+-l ECDH-ECDSA-RC4-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1.2 ECDH-ECDSA-DES3
+-v 3
+-l ECDH-ECDSA-DES-CBC3-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDH-ECDSA-DES3
+-v 3
+-l ECDH-ECDSA-DES-CBC3-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1.2 ECDH-ECDSA-AES128 
+-v 3
+-l ECDH-ECDSA-AES128-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDH-ECDSA-AES128 
+-v 3
+-l ECDH-ECDSA-AES128-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1.2 ECDH-ECDSA-AES128-SHA256
+-v 3
+-l ECDH-ECDSA-AES128-SHA256
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDH-ECDSA-AES128-SHA256 
+-v 3
+-l ECDH-ECDSA-AES128-SHA256
+-A ./certs/server-ecc.pem
+
+# server TLSv1.2 ECDH-ECDSA-AES256
+-v 3
+-l ECDH-ECDSA-AES256-SHA
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDH-ECDSA-AES256
+-v 3
+-l ECDH-ECDSA-AES256-SHA
+-A ./certs/server-ecc.pem
+
+# server TLSv1.2 ECDHE-RSA-AES256-SHA384
+-v 3
+-l ECDHE-RSA-AES256-SHA384
+
+# client TLSv1.2 ECDHE-RSA-AES256-SHA384 
+-v 3
+-l ECDHE-RSA-AES256-SHA384
+
+# server TLSv1.2 ECDHE-ECDSA-AES256-SHA384
+-v 3
+-l ECDHE-ECDSA-AES256-SHA384
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDHE-ECDSA-AES256-SHA384
+-v 3
+-l ECDHE-ECDSA-AES256-SHA384
+-A ./certs/server-ecc.pem
+
+# server TLSv1.2 ECDH-RSA-AES256-SHA384 
+-v 3
+-l ECDH-RSA-AES256-SHA384
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDH-RSA-AES256-SHA384 
+-v 3
+-l ECDH-RSA-AES256-SHA384
+
+# server TLSv1.2 ECDH-ECDSA-AES256-SHA384
+-v 3
+-l ECDH-ECDSA-AES256-SHA384
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDH-ECDSA-AES256-SHA384 
+-v 3
+-l ECDH-ECDSA-AES256-SHA384
+-A ./certs/server-ecc.pem
+
+# server TLSv1 HC128-SHA
+-v 1
+-l HC128-SHA
+
+# client TLSv1 HC128-SHA
+-v 1
+-l HC128-SHA
+
+# server TLSv1 HC128-MD5
+-v 1
+-l HC128-MD5
+
+# client TLSv1 HC128-MD5
+-v 1
+-l HC128-MD5
+
+# server TLSv1 HC128-B2B256
+-v 1
+-l HC128-B2B256
+
+# client TLSv1 HC128-B2B256
+-v 1
+-l HC128-B2B256
+
+# server TLSv1 AES128-B2B256
+-v 1
+-l AES128-B2B256
+
+# client TLSv1 AES128-B2B256
+-v 1
+-l AES128-B2B256
+
+# server TLSv1 AES256-B2B256
+-v 1
+-l AES256-B2B256
+
+# client TLSv1 AES256-B2B256
+-v 1
+-l AES256-B2B256
+
+# server TLSv1.1 HC128-SHA
+-v 2
+-l HC128-SHA
+
+# client TLSv1.1 HC128-SHA
+-v 2
+-l HC128-SHA
+
+# server TLSv1.1 HC128-MD5
+-v 2
+-l HC128-MD5
+
+# client TLSv1.1 HC128-MD5
+-v 2
+-l HC128-MD5
+
+# server TLSv1.1 HC128-B2B256
+-v 2
+-l HC128-B2B256
+
+# client TLSv1.1 HC128-B2B256
+-v 2
+-l HC128-B2B256
+
+# server TLSv1.1 AES128-B2B256
+-v 2
+-l AES128-B2B256
+
+# client TLSv1.1 AES128-B2B256
+-v 2
+-l AES128-B2B256
+
+# server TLSv1.1 AES256-B2B256
+-v 2
+-l AES256-B2B256
+
+# client TLSv1.1 AES256-B2B256
+-v 2
+-l AES256-B2B256
+
+# server TLSv1.2 HC128-SHA
+-v 3
+-l HC128-SHA
+
+# client TLSv1.2 HC128-SHA
+-v 3
+-l HC128-SHA
+
+# server TLSv1.2 HC128-MD5
+-v 3
+-l HC128-MD5
+
+# client TLSv1.2 HC128-MD5
+-v 3
+-l HC128-MD5
+
+# server TLSv1.2 HC128-B2B256
+-v 3
+-l HC128-B2B256
+
+# client TLSv1.2 HC128-B2B256
+-v 3
+-l HC128-B2B256
+
+# server TLSv1.2 AES128-B2B256
+-v 3
+-l AES128-B2B256
+
+# client TLSv1.2 AES128-B2B256
+-v 3
+-l AES128-B2B256
+
+# server TLSv1.2 AES256-B2B256
+-v 3
+-l AES256-B2B256
+
+# client TLSv1.2 AES256-B2B256
+-v 3
+-l AES256-B2B256
+
+# server TLSv1 RABBIT-SHA
+-v 1
+-l RABBIT-SHA
+
+# client TLSv1 RABBIT-SHA
+-v 1
+-l RABBIT-SHA
+
+# server TLSv1.1 RABBIT-SHA
+-v 2
+-l RABBIT-SHA
+
+# client TLSv1.1 RABBIT-SHA
+-v 2
+-l RABBIT-SHA
+
+# server TLSv1.2 RABBIT-SHA
+-v 3
+-l RABBIT-SHA
+
+# client TLSv1.2 RABBIT-SHA
+-v 3
+-l RABBIT-SHA
+
+# server TLSv1 NTRU_RC4
+-v 1
+-l NTRU-RC4-SHA
+-n
+-c ./certs/ntru-cert.pem
+-k ./certs/ntru-key.raw
+
+# client TLSv1 NTRU_RC4
+-v 1
+-l NTRU-RC4-SHA
+
+# server TLSv1 NTRU_DES3
+-v 1
+-l NTRU-DES-CBC3-SHA
+-n
+-c ./certs/ntru-cert.pem
+-k ./certs/ntru-key.raw
+
+# client TLSv1 NTRU_DES3
+-v 1
+-l NTRU-DES-CBC3-SHA
+
+# server TLSv1 NTRU_AES128
+-v 1
+-l NTRU-AES128-SHA
+-n
+-c ./certs/ntru-cert.pem
+-k ./certs/ntru-key.raw
+
+# client TLSv1 NTRU_AES128
+-v 1
+-l NTRU-AES128-SHA
+
+# server TLSv1 NTRU_AES256
+-v 1
+-l NTRU-AES256-SHA
+-n
+-c ./certs/ntru-cert.pem
+-k ./certs/ntru-key.raw
+
+# client TLSv1 NTRU_AES256
+-v 1
+-l NTRU-AES256-SHA
+
+# server TLSv1.1 NTRU_RC4
+-v 2
+-l NTRU-RC4-SHA
+-n
+-c ./certs/ntru-cert.pem
+-k ./certs/ntru-key.raw
+
+# client TLSv1.1 NTRU_RC4
+-v 2
+-l NTRU-RC4-SHA
+
+# server TLSv1.1 NTRU_DES3
+-v 2
+-l NTRU-DES-CBC3-SHA
+-n
+-c ./certs/ntru-cert.pem
+-k ./certs/ntru-key.raw
+
+# client TLSv1.1 NTRU_DES3
+-v 2
+-l NTRU-DES-CBC3-SHA
+
+# server TLSv1.1 NTRU_AES128
+-v 2
+-l NTRU-AES128-SHA
+-n
+-c ./certs/ntru-cert.pem
+-k ./certs/ntru-key.raw
+
+# client TLSv1.1 NTRU_AES128
+-v 2
+-l NTRU-AES128-SHA
+
+# server TLSv1.1 NTRU_AES256
+-v 2
+-l NTRU-AES256-SHA
+-n
+-c ./certs/ntru-cert.pem
+-k ./certs/ntru-key.raw
+
+# client TLSv1.1 NTRU_AES256
+-v 2
+-l NTRU-AES256-SHA
+
+# server TLSv1.2 NTRU_RC4
+-v 3
+-l NTRU-RC4-SHA
+-n
+-c ./certs/ntru-cert.pem
+-k ./certs/ntru-key.raw
+
+# client TLSv1.2 NTRU_RC4
+-v 3
+-l NTRU-RC4-SHA
+
+# server TLSv1.2 NTRU_DES3
+-v 3
+-l NTRU-DES-CBC3-SHA
+-n
+-c ./certs/ntru-cert.pem
+-k ./certs/ntru-key.raw
+
+# client TLSv1.2 NTRU_DES3
+-v 3
+-l NTRU-DES-CBC3-SHA
+
+# server TLSv1.2 NTRU_AES128
+-v 3
+-l NTRU-AES128-SHA
+-n
+-c ./certs/ntru-cert.pem
+-k ./certs/ntru-key.raw
+
+# client TLSv1.2 NTRU_AES128
+-v 3
+-l NTRU-AES128-SHA
+
+# server TLSv1.2 NTRU_AES256
+-v 3
+-l NTRU-AES256-SHA
+-n
+-c ./certs/ntru-cert.pem
+-k ./certs/ntru-key.raw
+
+# client TLSv1.2 NTRU_AES256
+-v 3
+-l NTRU-AES256-SHA
+
+# server TLSv1 DHE AES128
+-v 1
+-l DHE-RSA-AES128-SHA
+
+# client TLSv1 DHE AES128
+-v 1
+-l DHE-RSA-AES128-SHA
+
+# server TLSv1 DHE AES256
+-v 1
+-l DHE-RSA-AES256-SHA
+
+# client TLSv1 DHE AES256
+-v 1
+-l DHE-RSA-AES256-SHA
+
+# server TLSv1 DHE AES128-SHA256
+-v 1
+-l DHE-RSA-AES128-SHA256
+
+# client TLSv1 DHE AES128-SHA256
+-v 1
+-l DHE-RSA-AES128-SHA256
+
+# server TLSv1 DHE AES256-SHA256
+-v 1
+-l DHE-RSA-AES256-SHA256
+
+# client TLSv1 DHE AES256-SHA256
+-v 1
+-l DHE-RSA-AES256-SHA256
+
+# server TLSv1.1 DHE AES128
+-v 2
+-l DHE-RSA-AES128-SHA
+
+# client TLSv1.1 DHE AES128
+-v 2
+-l DHE-RSA-AES128-SHA
+
+# server TLSv1.1 DHE AES256
+-v 2
+-l DHE-RSA-AES256-SHA
+
+# client TLSv1.1 DHE AES256
+-v 2
+-l DHE-RSA-AES256-SHA
+
+# server TLSv1.1 DHE AES128-SHA256
+-v 2
+-l DHE-RSA-AES128-SHA256
+
+# client TLSv1.1 DHE AES128-SHA256
+-v 2
+-l DHE-RSA-AES128-SHA256
+
+# server TLSv1.1 DHE AES256-SHA256
+-v 2
+-l DHE-RSA-AES256-SHA256
+
+# client TLSv1.1 DHE AES256-SHA256
+-v 2
+-l DHE-RSA-AES256-SHA256
+
+# server TLSv1.2 DHE AES128
+-v 3
+-l DHE-RSA-AES128-SHA
+
+# client TLSv1.2 DHE AES128
+-v 3
+-l DHE-RSA-AES128-SHA
+
+# server TLSv1.2 DHE AES256
+-v 3
+-l DHE-RSA-AES256-SHA
+
+# client TLSv1.2 DHE AES256
+-v 3
+-l DHE-RSA-AES256-SHA
+
+# server TLSv1.2 DHE AES128-SHA256
+-v 3
+-l DHE-RSA-AES128-SHA256
+
+# client TLSv1.2 DHE AES128-SHA256
+-v 3
+-l DHE-RSA-AES128-SHA256
+
+# server TLSv1.2 DHE AES256-SHA256
+-v 3
+-l DHE-RSA-AES256-SHA256
+
+# client TLSv1.2 DHE AES256-SHA256
+-v 3
+-l DHE-RSA-AES256-SHA256
+
+# server TLSv1 PSK-AES128
+-s
+-v 1
+-l PSK-AES128-CBC-SHA
+
+# client TLSv1 PSK-AES128
+-s
+-v 1
+-l PSK-AES128-CBC-SHA
+
+# server TLSv1 PSK-AES256
+-s
+-v 1
+-l PSK-AES256-CBC-SHA
+
+# client TLSv1 PSK-AES256
+-s
+-v 1
+-l PSK-AES256-CBC-SHA
+
+# server TLSv1.1 PSK-AES128
+-s
+-v 2
+-l PSK-AES128-CBC-SHA
+
+# client TLSv1.1 PSK-AES128
+-s
+-v 2
+-l PSK-AES128-CBC-SHA
+
+# server TLSv1.1 PSK-AES256
+-s
+-v 2
+-l PSK-AES256-CBC-SHA
+
+# client TLSv1.1 PSK-AES256
+-s
+-v 2
+-l PSK-AES256-CBC-SHA
+
+# server TLSv1.2 PSK-AES128
+-s
+-v 3
+-l PSK-AES128-CBC-SHA
+
+# client TLSv1.2 PSK-AES128
+-s
+-v 3
+-l PSK-AES128-CBC-SHA
+
+# server TLSv1.2 PSK-AES256
+-s
+-v 3
+-l PSK-AES256-CBC-SHA
+
+# client TLSv1.2 PSK-AES256
+-s
+-v 3
+-l PSK-AES256-CBC-SHA
+
+# server TLSv1.0 PSK-AES128-SHA256
+-s
+-v 1
+-l PSK-AES128-CBC-SHA256
+
+# client TLSv1.0 PSK-AES128-SHA256
+-s
+-v 1
+-l PSK-AES128-CBC-SHA256
+
+# server TLSv1.1 PSK-AES128-SHA256
+-s
+-v 2
+-l PSK-AES128-CBC-SHA256
+
+# client TLSv1.1 PSK-AES128-SHA256
+-s
+-v 2
+-l PSK-AES128-CBC-SHA256
+
+# server TLSv1.2 PSK-AES128-SHA256
+-s
+-v 3
+-l PSK-AES128-CBC-SHA256
+
+# client TLSv1.2 PSK-AES128-SHA256
+-s
+-v 3
+-l PSK-AES128-CBC-SHA256
+
+# server TLSv1.0 PSK-AES256-SHA384
+-s
+-v 1
+-l PSK-AES256-CBC-SHA384
+
+# client TLSv1.0 PSK-AES256-SHA384
+-s
+-v 1
+-l PSK-AES256-CBC-SHA384
+
+# server TLSv1.1 PSK-AES256-SHA384
+-s
+-v 2
+-l PSK-AES256-CBC-SHA384
+
+# client TLSv1.1 PSK-AES256-SHA384
+-s
+-v 2
+-l PSK-AES256-CBC-SHA384
+
+# server TLSv1.2 PSK-AES256-SHA384
+-s
+-v 3
+-l PSK-AES256-CBC-SHA384
+
+# client TLSv1.2 PSK-AES256-SHA384
+-s
+-v 3
+-l PSK-AES256-CBC-SHA384
+
+# server TLSv1.0 PSK-NULL
+-s
+-v 1
+-l PSK-NULL-SHA
+
+# client TLSv1.0 PSK-NULL
+-s
+-v 1
+-l PSK-NULL-SHA
+
+# server TLSv1.1 PSK-NULL
+-s
+-v 2
+-l PSK-NULL-SHA
+
+# client TLSv1.1 PSK-NULL
+-s
+-v 2
+-l PSK-NULL-SHA
+
+# server TLSv1.2 PSK-NULL
+-s
+-v 3
+-l PSK-NULL-SHA
+
+# client TLSv1.2 PSK-NULL
+-s
+-v 3
+-l PSK-NULL-SHA
+
+# server TLSv1.2 PSK-NULL-SHA256
+-s
+-v 3
+-l PSK-NULL-SHA256
+
+# client TLSv1.2 PSK-NULL-SHA256
+-s
+-v 3
+-l PSK-NULL-SHA256
+
+# server TLSv1.2 PSK-NULL-SHA384
+-s
+-v 3
+-l PSK-NULL-SHA384
+
+# client TLSv1.2 PSK-NULL-SHA384
+-s
+-v 3
+-l PSK-NULL-SHA384
+
+# server TLSv1.2 PSK-NULL
+-s
+-v 3
+-l PSK-NULL-SHA
+
+# client TLSv1.2 PSK-NULL
+-s
+-v 3
+-l PSK-NULL-SHA
+
+# server TLSv1.2 PSK-NULL-SHA256
+-s
+-v 3
+-l PSK-NULL-SHA256
+
+# client TLSv1.2 PSK-NULL-SHA256
+-s
+-v 3
+-l PSK-NULL-SHA256
+
+# server TLSv1.0 RSA-NULL-SHA
+-v 1
+-l NULL-SHA
+
+# client TLSv1.0 RSA-NULL-SHA
+-v 1
+-l NULL-SHA
+
+# server TLSv1.1 RSA-NULL-SHA
+-v 2
+-l NULL-SHA
+
+# client TLSv1.1 RSA-NULL-SHA
+-v 2
+-l NULL-SHA
+
+# server TLSv1.2 RSA-NULL-SHA
+-v 3
+-l NULL-SHA
+
+# client TLSv1.2 RSA-NULL-SHA
+-v 3
+-l NULL-SHA
+
+# server TLSv1.0 RSA-NULL-SHA256
+-v 1
+-l NULL-SHA256
+
+# client TLSv1.0 RSA-NULL-SHA256
+-v 1
+-l NULL-SHA256
+
+# server TLSv1.1 RSA-NULL-SHA256
+-v 2
+-l NULL-SHA256
+
+# client TLSv1.1 RSA-NULL-SHA256
+-v 2
+-l NULL-SHA256
+
+# server TLSv1.2 RSA-NULL-SHA256
+-v 3
+-l NULL-SHA256
+
+# client TLSv1.2 RSA-NULL-SHA256
+-v 3
+-l NULL-SHA256
+
+# server TLSv1 CAMELLIA128-SHA
+-v 1
+-l CAMELLIA128-SHA
+
+# client TLSv1 CAMELLIA128-SHA
+-v 1
+-l CAMELLIA128-SHA
+
+# server TLSv1 CAMELLIA256-SHA
+-v 1
+-l CAMELLIA256-SHA
+
+# client TLSv1 CAMELLIA256-SHA
+-v 1
+-l CAMELLIA256-SHA
+
+# server TLSv1 CAMELLIA128-SHA256
+-v 1
+-l CAMELLIA128-SHA256
+
+# client TLSv1 CAMELLIA128-SHA256
+-v 1
+-l CAMELLIA128-SHA256
+
+# server TLSv1 CAMELLIA256-SHA256
+-v 1
+-l CAMELLIA256-SHA256
+
+# client TLSv1 CAMELLIA256-SHA256
+-v 1
+-l CAMELLIA256-SHA256
+
+# server TLSv1.1 CAMELLIA128-SHA
+-v 2
+-l CAMELLIA128-SHA
+
+# client TLSv1.1 CAMELLIA128-SHA
+-v 2
+-l CAMELLIA128-SHA
+
+# server TLSv1.1 CAMELLIA256-SHA
+-v 2
+-l CAMELLIA256-SHA
+
+# client TLSv1.1 CAMELLIA256-SHA
+-v 2
+-l CAMELLIA256-SHA
+
+# server TLSv1.1 CAMELLIA128-SHA256
+-v 2
+-l CAMELLIA128-SHA256
+
+# client TLSv1.1 CAMELLIA128-SHA256
+-v 2
+-l CAMELLIA128-SHA256
+
+# server TLSv1.1 CAMELLIA256-SHA256
+-v 2
+-l CAMELLIA256-SHA256
+
+# client TLSv1.1 CAMELLIA256-SHA256
+-v 2
+-l CAMELLIA256-SHA256
+
+# server TLSv1.2 CAMELLIA128-SHA
+-v 3
+-l CAMELLIA128-SHA
+
+# client TLSv1.2 CAMELLIA128-SHA
+-v 3
+-l CAMELLIA128-SHA
+
+# server TLSv1.2 CAMELLIA256-SHA
+-v 3
+-l CAMELLIA256-SHA
+
+# client TLSv1.2 CAMELLIA256-SHA
+-v 3
+-l CAMELLIA256-SHA
+
+# server TLSv1.2 CAMELLIA128-SHA256
+-v 3
+-l CAMELLIA128-SHA256
+
+# client TLSv1.2 CAMELLIA128-SHA256
+-v 3
+-l CAMELLIA128-SHA256
+
+# server TLSv1.2 CAMELLIA256-SHA256
+-v 3
+-l CAMELLIA256-SHA256
+
+# client TLSv1.2 CAMELLIA256-SHA256
+-v 3
+-l CAMELLIA256-SHA256
+
+# server TLSv1 DHE-RSA-CAMELLIA128-SHA
+-v 1
+-l DHE-RSA-CAMELLIA128-SHA
+
+# client TLSv1 DHE-RSA-CAMELLIA128-SHA
+-v 1
+-l DHE-RSA-CAMELLIA128-SHA
+
+# server TLSv1 DHE-RSA-CAMELLIA256-SHA
+-v 1
+-l DHE-RSA-CAMELLIA256-SHA
+
+# client TLSv1 DHE-RSA-CAMELLIA256-SHA
+-v 1
+-l DHE-RSA-CAMELLIA256-SHA
+
+# server TLSv1 DHE-RSA-CAMELLIA128-SHA256
+-v 1
+-l DHE-RSA-CAMELLIA128-SHA256
+
+# client TLSv1 DHE-RSA-CAMELLIA128-SHA256
+-v 1
+-l DHE-RSA-CAMELLIA128-SHA256
+
+# server TLSv1 DHE-RSA-CAMELLIA256-SHA256
+-v 1
+-l DHE-RSA-CAMELLIA256-SHA256
+
+# client TLSv1 DHE-RSA-CAMELLIA256-SHA256
+-v 1
+-l DHE-RSA-CAMELLIA256-SHA256
+
+# server TLSv1.1 DHE-RSA-CAMELLIA128-SHA
+-v 2
+-l DHE-RSA-CAMELLIA128-SHA
+
+# client TLSv1.1 DHE-RSA-CAMELLIA128-SHA
+-v 2
+-l DHE-RSA-CAMELLIA128-SHA
+
+# server TLSv1.1 DHE-RSA-CAMELLIA256-SHA
+-v 2
+-l DHE-RSA-CAMELLIA256-SHA
+
+# client TLSv1.1 DHE-RSA-CAMELLIA256-SHA
+-v 2
+-l DHE-RSA-CAMELLIA256-SHA
+
+# server TLSv1.1 DHE-RSA-CAMELLIA128-SHA256
+-v 2
+-l DHE-RSA-CAMELLIA128-SHA256
+
+# client TLSv1.1 DHE-RSA-CAMELLIA128-SHA256
+-v 2
+-l DHE-RSA-CAMELLIA128-SHA256
+
+# server TLSv1.1 DHE-RSA-CAMELLIA256-SHA256
+-v 2
+-l DHE-RSA-CAMELLIA256-SHA256
+
+# client TLSv1.1 DHE-RSA-CAMELLIA256-SHA256
+-v 2
+-l DHE-RSA-CAMELLIA256-SHA256
+
+# server TLSv1.2 DHE-RSA-CAMELLIA128-SHA
+-v 3
+-l DHE-RSA-CAMELLIA128-SHA
+
+# client TLSv1.2 DHE-RSA-CAMELLIA128-SHA
+-v 3
+-l DHE-RSA-CAMELLIA128-SHA
+
+# server TLSv1.2 DHE-RSA-CAMELLIA256-SHA
+-v 3
+-l DHE-RSA-CAMELLIA256-SHA
+
+# client TLSv1.2 DHE-RSA-CAMELLIA256-SHA
+-v 3
+-l DHE-RSA-CAMELLIA256-SHA
+
+# server TLSv1.2 DHE-RSA-CAMELLIA128-SHA256
+-v 3
+-l DHE-RSA-CAMELLIA128-SHA256
+
+# client TLSv1.2 DHE-RSA-CAMELLIA128-SHA256
+-v 3
+-l DHE-RSA-CAMELLIA128-SHA256
+
+# server TLSv1.2 DHE-RSA-CAMELLIA256-SHA256
+-v 3
+-l DHE-RSA-CAMELLIA256-SHA256
+
+# client TLSv1.2 DHE-RSA-CAMELLIA256-SHA256
+-v 3
+-l DHE-RSA-CAMELLIA256-SHA256
+
+# server TLSv1.2 RSA-AES128-GCM-SHA256 
+-v 3
+-l AES128-GCM-SHA256
+
+# client TLSv1.2 RSA-AES128-GCM-SHA256 
+-v 3
+-l AES128-GCM-SHA256
+
+# server TLSv1.2 RSA-AES256-GCM-SHA384
+-v 3
+-l AES256-GCM-SHA384
+
+# client TLSv1.2 RSA-AES256-GCM-SHA384
+-v 3
+-l AES256-GCM-SHA384
+
+# server TLSv1.2 ECDHE-ECDSA-AES128-GCM-SHA256 
+-v 3
+-l ECDHE-ECDSA-AES128-GCM-SHA256
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDHE-ECDSA-AES128-GCM-SHA256 
+-v 3
+-l ECDHE-ECDSA-AES128-GCM-SHA256
+-A ./certs/server-ecc.pem
+
+# server TLSv1.2 ECDHE-ECDSA-AES256-GCM-SHA384
+-v 3
+-l ECDHE-ECDSA-AES256-GCM-SHA384
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDHE-ECDSA-AES256-GCM-SHA384
+-v 3
+-l ECDHE-ECDSA-AES256-GCM-SHA384
+-A ./certs/server-ecc.pem
+
+# server TLSv1.2 ECDH-ECDSA-AES128-GCM-SHA256 
+-v 3
+-l ECDH-ECDSA-AES128-GCM-SHA256
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDH-ECDSA-AES128-GCM-SHA256 
+-v 3
+-l ECDH-ECDSA-AES128-GCM-SHA256
+-A ./certs/server-ecc.pem
+
+# server TLSv1.2 ECDH-ECDSA-AES256-GCM-SHA384
+-v 3
+-l ECDH-ECDSA-AES256-GCM-SHA384
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDH-ECDSA-AES256-GCM-SHA384
+-v 3
+-l ECDH-ECDSA-AES256-GCM-SHA384
+-A ./certs/server-ecc.pem
+
+# server TLSv1.2 ECDHE-RSA-AES128-GCM-SHA256 
+-v 3
+-l ECDHE-RSA-AES128-GCM-SHA256
+
+# client TLSv1.2 ECDHE-RSA-AES128-GCM-SHA256 
+-v 3
+-l ECDHE-RSA-AES128-GCM-SHA256
+
+# server TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384
+-v 3
+-l ECDHE-RSA-AES256-GCM-SHA384
+
+# client TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384
+-v 3
+-l ECDHE-RSA-AES256-GCM-SHA384
+
+# server TLSv1.2 ECDH-RSA-AES128-GCM-SHA256 
+-v 3
+-l ECDH-RSA-AES128-GCM-SHA256
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDH-RSA-AES128-GCM-SHA256 
+-v 3
+-l ECDH-RSA-AES128-GCM-SHA256
+
+# server TLSv1.2 ECDH-RSA-AES256-GCM-SHA384
+-v 3
+-l ECDH-RSA-AES256-GCM-SHA384
+-c ./certs/server-ecc-rsa.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDH-RSA-AES256-GCM-SHA384
+-v 3
+-l ECDH-RSA-AES256-GCM-SHA384
+
+# server TLSv1.2 DHE-RSA-AES128-GCM-SHA256 
+-v 3
+-l DHE-RSA-AES128-GCM-SHA256
+
+# client TLSv1.2 DHE-RSA-AES128-GCM-SHA256 
+-v 3
+-l DHE-RSA-AES128-GCM-SHA256
+
+# server TLSv1.2 DHE-RSA-AES256-GCM-SHA384
+-v 3
+-l DHE-RSA-AES256-GCM-SHA384
+
+# client TLSv1.2 DHE-RSA-AES256-GCM-SHA384
+-v 3
+-l DHE-RSA-AES256-GCM-SHA384
+
+# server TLSv1.2 PSK-AES128-GCM-SHA256
+-s
+-v 3
+-l PSK-AES128-GCM-SHA256
+
+# client TLSv1.2 PSK-AES128-GCM-SHA256
+-s
+-v 3
+-l PSK-AES128-GCM-SHA256
+
+# server TLSv1.2 PSK-AES256-GCM-SHA384
+-s
+-v 3
+-l PSK-AES256-GCM-SHA384
+
+# client TLSv1.2 PSK-AES256-GCM-SHA384
+-s
+-v 3
+-l PSK-AES256-GCM-SHA384
+
+# server TLSv1.2 AES128-CCM-8
+-v 3
+-l AES128-CCM-8
+
+# client TLSv1.2 AES128-CCM-8
+-v 3
+-l AES128-CCM-8
+
+# server TLSv1.2 AES256-CCM-8
+-v 3
+-l AES256-CCM-8
+
+# client TLSv1.2 AES256-CCM-8
+-v 3
+-l AES256-CCM-8
+
+# server TLSv1.2 ECDHE-ECDSA-AES128-CCM-8
+-v 3
+-l ECDHE-ECDSA-AES128-CCM-8
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDHE-ECDSA-AES128-CCM-8
+-v 3
+-l ECDHE-ECDSA-AES128-CCM-8
+-A ./certs/server-ecc.pem
+
+# server TLSv1.2 ECDHE-ECDSA-AES256-CCM-8
+-v 3
+-l ECDHE-ECDSA-AES256-CCM-8
+-c ./certs/server-ecc.pem
+-k ./certs/ecc-key.pem
+
+# client TLSv1.2 ECDHE-ECDSA-AES256-CCM-8
+-v 3
+-l ECDHE-ECDSA-AES256-CCM-8
+-A ./certs/server-ecc.pem
+
+# server TLSv1.2 PSK-AES128-CCM
+-s
+-v 3
+-l PSK-AES128-CCM
+
+# client TLSv1.2 PSK-AES128-CCM
+-s
+-v 3
+-l PSK-AES128-CCM
+
+# server TLSv1.2 PSK-AES256-CCM
+-s
+-v 3
+-l PSK-AES256-CCM
+
+# client TLSv1.2 PSK-AES256-CCM
+-s
+-v 3
+-l PSK-AES256-CCM
+
+# server TLSv1.2 PSK-AES128-CCM-8
+-s
+-v 3
+-l PSK-AES128-CCM-8
+
+# client TLSv1.2 PSK-AES128-CCM-8
+-s
+-v 3
+-l PSK-AES128-CCM-8
+
+# server TLSv1.2 PSK-AES256-CCM-8
+-s
+-v 3
+-l PSK-AES256-CCM-8
+
+# client TLSv1.2 PSK-AES256-CCM-8
+-s
+-v 3
+-l PSK-AES256-CCM-8
+
+# server TLSv1.0 DHE-PSK-AES128-CBC-SHA256
+-s
+-v 1
+-l DHE-PSK-AES128-CBC-SHA256
+
+# client TLSv1.0 DHE-PSK-AES128-CBC-SHA256
+-s
+-v 1
+-l DHE-PSK-AES128-CBC-SHA256
+
+# server TLSv1.1 DHE-PSK-AES128-CBC-SHA256
+-s
+-v 2
+-l DHE-PSK-AES128-CBC-SHA256
+
+# client TLSv1.1 DHE-PSK-AES128-CBC-SHA256
+-s
+-v 2
+-l DHE-PSK-AES128-CBC-SHA256
+
+# server TLSv1.2 DHE-PSK-AES128-CBC-SHA256
+-s
+-v 3
+-l DHE-PSK-AES128-CBC-SHA256
+
+# client TLSv1.2 DHE-PSK-AES128-CBC-SHA256
+-s
+-v 3
+-l DHE-PSK-AES128-CBC-SHA256
+
+# server TLSv1.0 DHE-PSK-AES256-CBC-SHA384
+-s
+-v 1
+-l DHE-PSK-AES256-CBC-SHA384
+
+# client TLSv1.0 DHE-PSK-AES256-CBC-SHA384
+-s
+-v 1
+-l DHE-PSK-AES256-CBC-SHA384
+
+# server TLSv1.1 DHE-PSK-AES256-CBC-SHA384
+-s
+-v 2
+-l DHE-PSK-AES256-CBC-SHA384
+
+# client TLSv1.1 DHE-PSK-AES256-CBC-SHA384
+-s
+-v 2
+-l DHE-PSK-AES256-CBC-SHA384
+
+# server TLSv1.2 DHE-PSK-AES256-CBC-SHA384
+-s
+-v 3
+-l DHE-PSK-AES256-CBC-SHA384
+
+# client TLSv1.2 DHE-PSK-AES256-CBC-SHA384
+-s
+-v 3
+-l DHE-PSK-AES256-CBC-SHA384
+
+# server TLSv1.0 DHE-PSK-NULL-SHA256
+-s
+-v 1
+-l DHE-PSK-NULL-SHA256
+
+# client TLSv1.0 DHE-PSK-NULL-SHA256
+-s
+-v 1
+-l DHE-PSK-NULL-SHA256
+
+# server TLSv1.1 DHE-PSK-NULL-SHA256
+-s
+-v 2
+-l DHE-PSK-NULL-SHA256
+
+# client TLSv1.1 DHE-PSK-NULL-SHA256
+-s
+-v 2
+-l DHE-PSK-NULL-SHA256
+
+# server TLSv1.2 DHE-PSK-NULL-SHA256
+-s
+-v 3
+-l DHE-PSK-NULL-SHA256
+
+# client TLSv1.2 DHE-PSK-NULL-SHA256
+-s
+-v 3
+-l DHE-PSK-NULL-SHA256
+
+# server TLSv1.0 DHE-PSK-NULL-SHA384
+-s
+-v 1
+-l DHE-PSK-NULL-SHA384
+
+# client TLSv1.0 DHE-PSK-NULL-SHA384
+-s
+-v 1
+-l DHE-PSK-NULL-SHA384
+
+# server TLSv1.1 DHE-PSK-NULL-SHA384
+-s
+-v 2
+-l DHE-PSK-NULL-SHA384
+
+# client TLSv1.1 DHE-PSK-NULL-SHA384
+-s
+-v 2
+-l DHE-PSK-NULL-SHA384
+
+# server TLSv1.2 DHE-PSK-NULL-SHA384
+-s
+-v 3
+-l DHE-PSK-NULL-SHA384
+
+# client TLSv1.2 DHE-PSK-NULL-SHA384
+-s
+-v 3
+-l DHE-PSK-NULL-SHA384
+
+# server TLSv1.2 DHE-PSK-AES128-GCM-SHA256
+-s
+-v 3
+-l DHE-PSK-AES128-GCM-SHA256
+
+# client TLSv1.2 DHE-PSK-AES128-GCM-SHA256
+-s
+-v 3
+-l DHE-PSK-AES128-GCM-SHA256
+
+# server TLSv1.2 DHE-PSK-AES256-GCM-SHA384
+-s
+-v 3
+-l DHE-PSK-AES256-GCM-SHA384
+
+# client TLSv1.2 DHE-PSK-AES256-GCM-SHA384
+-s
+-v 3
+-l DHE-PSK-AES256-GCM-SHA384
+
+# server TLSv1.2 DHE-PSK-AES128-CCM
+-s
+-v 3
+-l DHE-PSK-AES128-CCM
+
+# client TLSv1.2 DHE-PSK-AES128-CCM
+-s
+-v 3
+-l DHE-PSK-AES128-CCM
+
+# server TLSv1.2 DHE-PSK-AES256-CCM
+-s
+-v 3
+-l DHE-PSK-AES256-CCM
+
+# client TLSv1.2 DHE-PSK-AES256-CCM
+-s
+-v 3
+-l DHE-PSK-AES256-CCM
+
+# server TLSv1.2 ADH-AES128-SHA
+-a
+-v 3
+-l ADH-AES128-SHA
+
+# client TLSv1.2 ADH-AES128-SHA
+-a
+-v 3
+-l ADH-AES128-SHA
+
+# server TLSv1.1 ADH-AES128-SHA
+-a
+-v 2
+-l ADH-AES128-SHA
+
+# client TLSv1.1 ADH-AES128-SHA
+-a
+-v 2
+-l ADH-AES128-SHA
+
+# server TLSv1.0 ADH-AES128-SHA
+-a
+-v 1
+-l ADH-AES128-SHA
+
+# client TLSv1.0 ADH-AES128-SHA
+-a
+-v 1
+-l ADH-AES128-SHA
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/unit.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/unit.c
new file mode 100644
index 0000000..d66f84c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/unit.c
@@ -0,0 +1,160 @@
+/* unit.c unit tests driver */
+
+/* Name change compatibility layer no longer need to be included here */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#include 
+#include 
+
+
+int myoptind = 0;
+char* myoptarg = NULL;
+int unit_test(int argc, char** argv);
+
+#ifndef NO_TESTSUITE_MAIN_DRIVER
+int main(int argc, char** argv)
+{
+    return unit_test(argc, argv);
+}
+#endif
+
+int unit_test(int argc, char** argv)
+{
+    int ret;
+
+    (void)argc;
+    (void)argv;
+    printf("starting unit tests...\n");
+
+#ifdef HAVE_CAVIUM
+    ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID);
+    if (ret != 0)
+        err_sys("Cavium OpenNitroxDevice failed");
+#endif /* HAVE_CAVIUM */
+
+#ifndef WOLFSSL_TIRTOS
+    if (CurrentDir("tests") || CurrentDir("_build"))
+        ChangeDirBack(1);
+    else if (CurrentDir("Debug") || CurrentDir("Release"))
+        ChangeDirBack(3);
+#endif
+
+    ApiTest();
+
+    if ( (ret = HashTest()) != 0){
+        printf("hash test failed with %d\n", ret);
+        return ret;
+    }
+
+#ifndef SINGLE_THREADED
+    if ( (ret = SuiteTest()) != 0){
+        printf("suite test failed with %d\n", ret);
+        return ret;
+    }
+#endif
+
+#ifdef HAVE_CAVIUM
+        CspShutdown(CAVIUM_DEV_ID);
+#endif
+
+    return 0;
+}
+
+
+
+void wait_tcp_ready(func_args* args)
+{
+#ifdef SINGLE_THREADED
+    (void)args;
+#elif defined(_POSIX_THREADS) && !defined(__MINGW32__)
+    pthread_mutex_lock(&args->signal->mutex);
+    
+    if (!args->signal->ready)
+        pthread_cond_wait(&args->signal->cond, &args->signal->mutex);
+    args->signal->ready = 0; /* reset */
+
+    pthread_mutex_unlock(&args->signal->mutex);
+#else
+    (void)args;
+#endif
+}
+
+
+void start_thread(THREAD_FUNC fun, func_args* args, THREAD_TYPE* thread)
+{
+#ifdef SINGLE_THREADED
+    (void)fun;
+    (void)args;
+    (void)thread;
+#elif defined(_POSIX_THREADS) && !defined(__MINGW32__)
+    pthread_create(thread, 0, fun, args);
+    return;
+#elif defined (WOLFSSL_TIRTOS)
+    /* Initialize the defaults and set the parameters. */
+    Task_Params taskParams;
+    Task_Params_init(&taskParams);
+    taskParams.arg0 = (UArg)args;
+    taskParams.stackSize = 65535;
+    *thread = Task_create((Task_FuncPtr)fun, &taskParams, NULL);
+    if (*thread == NULL) {
+        printf("Failed to create new Task\n");
+    }
+    Task_yield();
+#else
+    *thread = (THREAD_TYPE)_beginthreadex(0, 0, fun, args, 0, 0);
+#endif
+}
+
+
+void join_thread(THREAD_TYPE thread)
+{
+#ifdef SINGLE_THREADED
+    (void)thread;
+#elif defined(_POSIX_THREADS) && !defined(__MINGW32__)
+    pthread_join(thread, 0);
+#elif defined (WOLFSSL_TIRTOS)
+    while(1) {
+        if (Task_getMode(thread) == Task_Mode_TERMINATED) {
+            Task_sleep(5);
+            break;
+        }
+        Task_yield();
+    }
+#else
+    int res = WaitForSingleObject((HANDLE)thread, INFINITE);
+    assert(res == WAIT_OBJECT_0);
+    res = CloseHandle((HANDLE)thread);
+    assert(res);
+#endif
+}
+
+
+void InitTcpReady(tcp_ready* ready)
+{
+    ready->ready = 0;
+    ready->port = 0;
+#ifdef SINGLE_THREADED
+#elif defined(_POSIX_THREADS) && !defined(__MINGW32__)
+      pthread_mutex_init(&ready->mutex, 0);
+      pthread_cond_init(&ready->cond, 0);
+#endif
+}
+
+
+void FreeTcpReady(tcp_ready* ready)
+{
+#ifdef SINGLE_THREADED
+    (void)ready;
+#elif defined(_POSIX_THREADS) && !defined(__MINGW32__)
+    pthread_mutex_destroy(&ready->mutex);
+    pthread_cond_destroy(&ready->cond);
+#else
+    (void)ready;
+#endif
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/unit.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/unit.h
new file mode 100644
index 0000000..ab8fbc2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/tests/unit.h
@@ -0,0 +1,65 @@
+/* unit.h unit tests driver */
+
+#ifndef CyaSSL_UNIT_H
+#define CyaSSL_UNIT_H
+
+#include 
+#include     /* thread and tcp stuff */
+
+#define Fail(description, result) do {                                         \
+    printf("\nERROR - %s line %d failed with:", __FILE__, __LINE__);           \
+    printf("\n\n    test:   "); printf description;                            \
+    printf("\n\n    result: "); printf result;                                 \
+    abort();                                                                   \
+} while(0)
+
+#define Assert(test, description, result) if (!(test)) Fail(description, result)
+
+#define AssertTrue(x)    Assert( (x), ("%s is true",     #x), (#x " => FALSE"))
+#define AssertFalse(x)   Assert(!(x), ("%s is false",    #x), (#x " => TRUE"))
+#define AssertNotNull(x) Assert( (x), ("%s is not null", #x), (#x " => NULL"))
+
+#define AssertNull(x) do {                                                     \
+    void* _x = (void *) (x);                                                   \
+                                                                               \
+    Assert(!_x, ("%s is null", #x), (#x " => %p", _x));                        \
+} while(0)
+
+#define AssertInt(x, y, op, er) do {                                           \
+    int _x = x;                                                                \
+    int _y = y;                                                                \
+                                                                               \
+    Assert(_x op _y, ("%s " #op " %s", #x, #y), ("%d " #er " %d", _x, _y));    \
+} while(0)
+
+#define AssertIntEQ(x, y) AssertInt(x, y, ==, !=)
+#define AssertIntNE(x, y) AssertInt(x, y, !=, ==)
+#define AssertIntGT(x, y) AssertInt(x, y,  >, <=)
+#define AssertIntLT(x, y) AssertInt(x, y,  <, >=)
+#define AssertIntGE(x, y) AssertInt(x, y, >=,  <)
+#define AssertIntLE(x, y) AssertInt(x, y, <=,  >)
+
+#define AssertStr(x, y, op, er) do {                                           \
+    const char* _x = x;                                                        \
+    const char* _y = y;                                                        \
+    int   _z = strcmp(_x, _y);                                                 \
+                                                                               \
+    Assert(_z op 0, ("%s " #op " %s", #x, #y),                                 \
+                                            ("\"%s\" " #er " \"%s\"", _x, _y));\
+} while(0)
+
+#define AssertStrEQ(x, y) AssertStr(x, y, ==, !=)
+#define AssertStrNE(x, y) AssertStr(x, y, !=, ==)
+#define AssertStrGT(x, y) AssertStr(x, y,  >, <=)
+#define AssertStrLT(x, y) AssertStr(x, y,  <, >=)
+#define AssertStrGE(x, y) AssertStr(x, y, >=,  <)
+#define AssertStrLE(x, y) AssertStr(x, y, <=,  >)
+
+
+void ApiTest(void);
+int SuiteTest(void);
+int HashTest(void);
+
+
+#endif /* CyaSSL_UNIT_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/testsuite/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/testsuite/include.am
new file mode 100644
index 0000000..62edb4a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/testsuite/include.am
@@ -0,0 +1,26 @@
+# vim:ft=automake
+# included from Top Level Makefile.am
+# All paths should be given relative to the root
+
+
+if BUILD_EXAMPLES
+check_PROGRAMS += testsuite/testsuite.test
+noinst_PROGRAMS += testsuite/testsuite.test
+testsuite_testsuite_test_SOURCES = \
+			      wolfcrypt/test/test.c \
+			      examples/client/client.c \
+			      examples/echoclient/echoclient.c \
+			      examples/echoserver/echoserver.c \
+			      examples/server/server.c \
+			      testsuite/testsuite.c
+testsuite_testsuite_test_CFLAGS       = -DNO_MAIN_DRIVER $(AM_CFLAGS)
+testsuite_testsuite_test_LDADD        = src/libwolfssl.la
+testsuite_testsuite_test_DEPENDENCIES = src/libwolfssl.la
+endif
+EXTRA_DIST += testsuite/testsuite.sln
+EXTRA_DIST += testsuite/testsuite-ntru.vcproj
+EXTRA_DIST += testsuite/testsuite.vcproj
+EXTRA_DIST += testsuite/testsuite.vcxproj
+EXTRA_DIST += input
+EXTRA_DIST += quit
+DISTCLEANFILES+= testsuite/.libs/testsuite.test
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/testsuite/testsuite-ntru.vcproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/testsuite/testsuite-ntru.vcproj
new file mode 100644
index 0000000..a6fc7be
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/testsuite/testsuite-ntru.vcproj
@@ -0,0 +1,219 @@
+
+
+	
+		
+	
+	
+	
+	
+		
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+		
+		
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+		
+	
+	
+	
+	
+		
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+		
+		
+		
+		
+		
+	
+	
+	
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/testsuite/testsuite.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/testsuite/testsuite.c
new file mode 100644
index 0000000..4146878
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/testsuite/testsuite.c
@@ -0,0 +1,445 @@
+/* testsuite.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#include 
+#include 
+#include "wolfcrypt/test/test.h"
+
+#ifndef SINGLE_THREADED
+
+#include 
+#include 
+
+#include "examples/echoclient/echoclient.h"
+#include "examples/echoserver/echoserver.h"
+#include "examples/server/server.h"
+#include "examples/client/client.h"
+
+
+void file_test(const char* file, byte* hash);
+
+void simple_test(func_args*);
+
+enum {
+    NUMARGS = 3
+};
+
+static const char *outputName;
+
+int myoptind = 0;
+char* myoptarg = NULL;
+
+
+#ifndef NO_TESTSUITE_MAIN_DRIVER
+
+    static int testsuite_test(int argc, char** argv);
+
+    int main(int argc, char** argv)
+    {
+        return testsuite_test(argc, argv);
+    }
+
+#endif /* NO_TESTSUITE_MAIN_DRIVER */
+
+
+int testsuite_test(int argc, char** argv)
+{
+    func_args server_args;
+
+    tcp_ready ready;
+    THREAD_TYPE serverThread;
+
+#ifndef USE_WINDOWS_API
+    char tempName[] = "/tmp/output-XXXXXX";
+    int len = 18;
+    int num = 6;
+#else
+    char tempName[] = "fnXXXXXX";
+    int len = 8;
+    int num = 6;
+#endif
+
+#ifdef HAVE_CAVIUM
+        int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID);
+        if (ret != 0)
+            err_sys("Cavium OpenNitroxDevice failed");
+#endif /* HAVE_CAVIUM */
+
+    StartTCP();
+
+    server_args.argc = argc;
+    server_args.argv = argv;
+
+    wolfSSL_Init();
+#if defined(DEBUG_WOLFSSL) && !defined(HAVE_VALGRIND)
+    wolfSSL_Debugging_ON();
+#endif
+
+#if !defined(WOLFSSL_TIRTOS)
+    if (CurrentDir("testsuite") || CurrentDir("_build"))
+        ChangeDirBack(1);
+    else if (CurrentDir("Debug") || CurrentDir("Release"))
+        ChangeDirBack(3);          /* Xcode->Preferences->Locations->Locations*/
+                                   /* Derived Data Advanced -> Custom  */
+                                   /* Relative to Workspace, Build/Products */
+                                   /* Debug or Release */
+#endif
+
+#ifdef WOLFSSL_TIRTOS
+    fdOpenSession(Task_self());
+#endif
+
+    server_args.signal = &ready;
+    InitTcpReady(&ready);
+
+    /* wc_ test */
+    wolfcrypt_test(&server_args);
+    if (server_args.return_code != 0) return server_args.return_code;
+ 
+    /* Simple wolfSSL client server test */
+    simple_test(&server_args);
+    if (server_args.return_code != 0) return server_args.return_code;
+
+    /* Echo input wolfSSL client server test */
+    start_thread(echoserver_test, &server_args, &serverThread);
+    wait_tcp_ready(&server_args);
+    {
+        func_args echo_args;
+        char* myArgv[NUMARGS];
+
+        char argc0[32];
+        char argc1[32];
+        char argc2[32];
+
+        myArgv[0] = argc0;
+        myArgv[1] = argc1;
+        myArgv[2] = argc2;
+
+        echo_args.argc = 3;
+        echo_args.argv = myArgv;
+
+        /* Create unique file name */
+        outputName = mymktemp(tempName, len, num);
+        if (outputName == NULL) {
+            printf("Could not create unique file name");
+            return EXIT_FAILURE;
+        }
+
+        strcpy(echo_args.argv[0], "echoclient");
+        strcpy(echo_args.argv[1], "input");
+        strcpy(echo_args.argv[2], outputName);
+
+        /* Share the signal, it has the new port number in it. */
+        echo_args.signal = server_args.signal;
+
+        /* make sure OK */
+        echoclient_test(&echo_args);
+        if (echo_args.return_code != 0) return echo_args.return_code;
+
+#ifdef WOLFSSL_DTLS
+        wait_tcp_ready(&server_args);
+#endif
+        /* send quit to echoserver */
+        echo_args.argc = 2;
+        strcpy(echo_args.argv[1], "quit");
+
+        echoclient_test(&echo_args);
+        if (echo_args.return_code != 0) return echo_args.return_code;
+        join_thread(serverThread);
+        if (server_args.return_code != 0) return server_args.return_code;
+    }
+
+    /* show ciphers */
+    {
+        char ciphers[1024];
+        XMEMSET(ciphers, 0, sizeof(ciphers));
+        wolfSSL_get_ciphers(ciphers, sizeof(ciphers)-1);
+        printf("ciphers = %s\n", ciphers);
+    }
+
+    /* validate output equals input */
+    {
+        byte input[SHA256_DIGEST_SIZE];
+        byte output[SHA256_DIGEST_SIZE];
+
+        file_test("input",  input);
+        file_test(outputName, output);
+        remove(outputName);
+        if (memcmp(input, output, sizeof(input)) != 0)
+            return EXIT_FAILURE;
+    }
+
+    wolfSSL_Cleanup();
+    FreeTcpReady(&ready);
+
+#ifdef WOLFSSL_TIRTOS
+    fdCloseSession(Task_self());
+#endif
+
+#ifdef HAVE_CAVIUM
+        CspShutdown(CAVIUM_DEV_ID);
+#endif
+    printf("\nAll tests passed!\n");
+    return EXIT_SUCCESS;
+}
+
+void simple_test(func_args* args)
+{
+    THREAD_TYPE serverThread;
+
+    func_args svrArgs;
+    char *svrArgv[9];
+    char argc0s[32];
+    char argc1s[32];
+    char argc2s[32];
+    char argc3s[32];
+    char argc4s[32];
+    char argc5s[32];
+    char argc6s[32];
+    char argc7s[32];
+    char argc8s[32];
+
+    func_args cliArgs;
+    char *cliArgv[NUMARGS];
+    char argc0c[32];
+    char argc1c[32];
+    char argc2c[32];
+
+    svrArgv[0] = argc0s;
+    svrArgv[1] = argc1s;
+    svrArgv[2] = argc2s;
+    svrArgv[3] = argc3s;
+    svrArgv[4] = argc4s;
+    svrArgv[5] = argc5s;
+    svrArgv[6] = argc6s;
+    svrArgv[7] = argc7s;
+    svrArgv[8] = argc8s;
+    cliArgv[0] = argc0c;
+    cliArgv[1] = argc1c;
+    cliArgv[2] = argc2c;
+
+    svrArgs.argc = 1;
+    svrArgs.argv = svrArgv;
+    svrArgs.return_code = 0;
+    cliArgs.argc = 1;
+    cliArgs.argv = cliArgv;
+    cliArgs.return_code = 0;
+
+    strcpy(svrArgs.argv[0], "SimpleServer");
+    #if !defined(USE_WINDOWS_API) && !defined(WOLFSSL_SNIFFER)  && \
+                                     !defined(WOLFSSL_TIRTOS)
+        strcpy(svrArgs.argv[svrArgs.argc++], "-p");
+        strcpy(svrArgs.argv[svrArgs.argc++], "0");
+    #endif
+    #ifdef HAVE_NTRU
+        strcpy(svrArgs.argv[svrArgs.argc++], "-d");
+        strcpy(svrArgs.argv[svrArgs.argc++], "-n");
+        strcpy(svrArgs.argv[svrArgs.argc++], "-c");
+        strcpy(svrArgs.argv[svrArgs.argc++], "./certs/ntru-cert.pem");
+        strcpy(svrArgs.argv[svrArgs.argc++], "-k");
+        strcpy(svrArgs.argv[svrArgs.argc++], "./certs/ntru-key.raw");
+    #endif
+    /* Set the last arg later, when it is known. */
+
+    args->return_code = 0;
+    svrArgs.signal = args->signal;
+    start_thread(server_test, &svrArgs, &serverThread);
+    wait_tcp_ready(&svrArgs);
+
+    /* Setting the actual port number. */
+    strcpy(cliArgs.argv[0], "SimpleClient");
+    #ifndef USE_WINDOWS_API
+        cliArgs.argc = NUMARGS;
+        strcpy(cliArgs.argv[1], "-p");
+        snprintf(cliArgs.argv[2], sizeof(argc2c), "%d", svrArgs.signal->port);
+    #endif
+
+    client_test(&cliArgs);
+    if (cliArgs.return_code != 0) {
+        args->return_code = cliArgs.return_code;
+        return;
+    }
+    join_thread(serverThread);
+    if (svrArgs.return_code != 0) args->return_code = svrArgs.return_code;
+}
+
+
+void wait_tcp_ready(func_args* args)
+{
+#if defined(_POSIX_THREADS) && !defined(__MINGW32__)
+    pthread_mutex_lock(&args->signal->mutex);
+
+    if (!args->signal->ready)
+        pthread_cond_wait(&args->signal->cond, &args->signal->mutex);
+    args->signal->ready = 0; /* reset */
+
+    pthread_mutex_unlock(&args->signal->mutex);
+#else
+    (void)args;
+#endif
+}
+
+
+void start_thread(THREAD_FUNC fun, func_args* args, THREAD_TYPE* thread)
+{
+#if defined(_POSIX_THREADS) && !defined(__MINGW32__)
+    pthread_create(thread, 0, fun, args);
+    return;
+#elif defined(WOLFSSL_TIRTOS)
+    /* Initialize the defaults and set the parameters. */
+    Task_Params taskParams;
+    Task_Params_init(&taskParams);
+    taskParams.arg0 = (UArg)args;
+    taskParams.stackSize = 65535;
+    *thread = Task_create((Task_FuncPtr)fun, &taskParams, NULL);
+    if (*thread == NULL) {
+        printf("Failed to create new Task\n");
+    }
+    Task_yield();
+#else
+    *thread = (THREAD_TYPE)_beginthreadex(0, 0, fun, args, 0, 0);
+#endif
+}
+
+
+void join_thread(THREAD_TYPE thread)
+{
+#if defined(_POSIX_THREADS) && !defined(__MINGW32__)
+    pthread_join(thread, 0);
+#elif defined(WOLFSSL_TIRTOS)
+    while(1) {
+        if (Task_getMode(thread) == Task_Mode_TERMINATED) {
+		    Task_sleep(5);
+            break;
+        }
+        Task_yield();
+    }
+#else
+    int res = WaitForSingleObject((HANDLE)thread, INFINITE);
+    assert(res == WAIT_OBJECT_0);
+    res = CloseHandle((HANDLE)thread);
+    assert(res);
+#endif
+}
+
+
+void InitTcpReady(tcp_ready* ready)
+{
+    ready->ready = 0;
+    ready->port = 0;
+#if defined(_POSIX_THREADS) && !defined(__MINGW32__)
+      pthread_mutex_init(&ready->mutex, 0);
+      pthread_cond_init(&ready->cond, 0);
+#endif
+}
+
+
+void FreeTcpReady(tcp_ready* ready)
+{
+#if defined(_POSIX_THREADS) && !defined(__MINGW32__)
+    pthread_mutex_destroy(&ready->mutex);
+    pthread_cond_destroy(&ready->cond);
+#else
+    (void)ready;
+#endif
+}
+
+
+void file_test(const char* file, byte* check)
+{
+    FILE* f;
+    int   i = 0, j, ret;
+    Sha256   sha256;
+    byte  buf[1024];
+    byte  shasum[SHA256_DIGEST_SIZE];
+
+    ret = wc_InitSha256(&sha256);
+    if (ret != 0) {
+        printf("Can't wc_InitSha256 %d\n", ret);
+        return;
+    }
+    if( !( f = fopen( file, "rb" ) )) {
+        printf("Can't open %s\n", file);
+        return;
+    }
+    while( ( i = (int)fread(buf, 1, sizeof(buf), f )) > 0 ) {
+        ret = wc_Sha256Update(&sha256, buf, i);
+        if (ret != 0) {
+            printf("Can't wc_Sha256Update %d\n", ret);
+            return;
+        }
+    }
+
+    ret = wc_Sha256Final(&sha256, shasum);
+    if (ret != 0) {
+        printf("Can't wc_Sha256Final %d\n", ret);
+        return;
+    }
+
+    memcpy(check, shasum, sizeof(shasum));
+
+    for(j = 0; j < SHA256_DIGEST_SIZE; ++j )
+        printf( "%02x", shasum[j] );
+
+    printf("  %s\n", file);
+
+    fclose(f);
+}
+
+
+#else /* SINGLE_THREADED */
+
+
+int myoptind = 0;
+char* myoptarg = NULL;
+
+
+int main(int argc, char** argv)
+{
+    func_args server_args;
+
+    server_args.argc = argc;
+    server_args.argv = argv;
+
+    if (CurrentDir("testsuite") || CurrentDir("_build"))
+        ChangeDirBack(1);
+    else if (CurrentDir("Debug") || CurrentDir("Release"))
+        ChangeDirBack(3);          /* Xcode->Preferences->Locations->Locations*/
+                                   /* Derived Data Advanced -> Custom  */
+                                   /* Relative to Workspace, Build/Products */
+                                   /* Debug or Release */
+
+    wolfcrypt_test(&server_args);
+    if (server_args.return_code != 0) return server_args.return_code;
+
+    printf("\nAll tests passed!\n");
+    return EXIT_SUCCESS;
+}
+
+
+#endif /* SINGLE_THREADED */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/testsuite/testsuite.sln b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/testsuite/testsuite.sln
new file mode 100644
index 0000000..b89dcc1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/testsuite/testsuite.sln
@@ -0,0 +1,20 @@
+
+Microsoft Visual Studio Solution File, Format Version 9.00
+# Visual C++ Express 2005
+Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "testsuite", "testsuite.vcproj", "{9D4D8446-CE91-4F7A-AFF2-90D0B5DCD717}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|Win32 = Debug|Win32
+		Release|Win32 = Release|Win32
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{9D4D8446-CE91-4F7A-AFF2-90D0B5DCD717}.Debug|Win32.ActiveCfg = Debug|Win32
+		{9D4D8446-CE91-4F7A-AFF2-90D0B5DCD717}.Debug|Win32.Build.0 = Debug|Win32
+		{9D4D8446-CE91-4F7A-AFF2-90D0B5DCD717}.Release|Win32.ActiveCfg = Release|Win32
+		{9D4D8446-CE91-4F7A-AFF2-90D0B5DCD717}.Release|Win32.Build.0 = Release|Win32
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/testsuite/testsuite.vcproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/testsuite/testsuite.vcproj
new file mode 100644
index 0000000..ce71e14
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/testsuite/testsuite.vcproj
@@ -0,0 +1,217 @@
+
+
+	
+		
+	
+	
+	
+	
+		
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+		
+		
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+		
+	
+	
+	
+	
+		
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+		
+		
+		
+		
+		
+	
+	
+	
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/testsuite/testsuite.vcxproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/testsuite/testsuite.vcxproj
new file mode 100644
index 0000000..484a875
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/testsuite/testsuite.vcxproj
@@ -0,0 +1,337 @@
+
+
+  
+    
+      Debug
+      Win32
+    
+    
+      Debug
+      x64
+    
+    
+      DLL Debug
+      Win32
+    
+    
+      DLL Debug
+      x64
+    
+    
+      DLL Release
+      Win32
+    
+    
+      DLL Release
+      x64
+    
+    
+      Release
+      Win32
+    
+    
+      Release
+      x64
+    
+  
+  
+    {611E8971-46E0-4D0A-B5A1-632C3B00CB80}
+    testsuite
+    Win32Proj
+  
+  
+  
+    Application
+    v110
+    Unicode
+    true
+  
+  
+    Application
+    v110
+    Unicode
+    true
+  
+  
+    Application
+    v110
+    Unicode
+    true
+  
+  
+    Application
+    v110
+    Unicode
+    true
+  
+  
+    Application
+    v110
+    Unicode
+  
+  
+    Application
+    v110
+    Unicode
+  
+  
+    Application
+    v110
+    Unicode
+  
+  
+    Application
+    v110
+    Unicode
+  
+  
+  
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+    
+  
+  
+  
+    <_ProjectFileVersion>11.0.61030.0
+  
+  
+    $(SolutionDir)$(Configuration)\
+    $(Configuration)\obj\
+    true
+  
+  
+    $(SolutionDir)$(Configuration)\
+    $(Configuration)\obj\
+    true
+  
+  
+    true
+    $(SolutionDir)$(Platform)\$(Configuration)\
+    $(Platform)\$(Configuration)\obj\
+  
+  
+    true
+    $(SolutionDir)$(Platform)\$(Configuration)\
+    $(Platform)\$(Configuration)\obj\
+  
+  
+    $(SolutionDir)$(Configuration)\
+    $(Configuration)\obj\
+    false
+  
+  
+    $(SolutionDir)$(Configuration)\
+    $(Configuration)\obj\
+    false
+  
+  
+    false
+    $(SolutionDir)$(Platform)\$(Configuration)\
+    $(Platform)\$(Configuration)\obj\
+  
+  
+    false
+    $(SolutionDir)$(Platform)\$(Configuration)\
+    $(Platform)\$(Configuration)\obj\
+  
+  
+    
+      Disabled
+      ../;%(AdditionalIncludeDirectories)
+      NO_MAIN_DRIVER;WOLFSSL_RIPEMD;WOLFSSL_SHA512;OPENSSL_EXTRA;NO_PSK;%(PreprocessorDefinitions)
+      true
+      EnableFastChecks
+      MultiThreadedDebugDLL
+      
+      Level3
+      EditAndContinue
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+      MachineX86
+    false
+    
+  
+  
+    
+      Disabled
+      ../;%(AdditionalIncludeDirectories)
+      NO_MAIN_DRIVER;WOLFSSL_RIPEMD;WOLFSSL_SHA512;OPENSSL_EXTRA;NO_PSK;WOLFSSL_DLL;%(PreprocessorDefinitions)
+      true
+      EnableFastChecks
+      MultiThreadedDebugDLL
+      
+      
+      Level3
+      EditAndContinue
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+      MachineX86
+    
+  
+  
+    
+      Disabled
+      ../;%(AdditionalIncludeDirectories)
+      NO_MAIN_DRIVER;WOLFSSL_RIPEMD;WOLFSSL_SHA512;OPENSSL_EXTRA;NO_PSK;%(PreprocessorDefinitions)
+      EnableFastChecks
+      MultiThreadedDebugDLL
+      
+      
+      Level3
+      ProgramDatabase
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+    
+  
+  
+    
+      Disabled
+      ../;%(AdditionalIncludeDirectories)
+      NO_MAIN_DRIVER;WOLFSSL_RIPEMD;WOLFSSL_SHA512;OPENSSL_EXTRA;NO_PSK;WOLFSSL_DLL;%(PreprocessorDefinitions)
+      EnableFastChecks
+      MultiThreadedDebugDLL
+      
+      
+      Level3
+      ProgramDatabase
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+    
+  
+  
+    
+      MaxSpeed
+      true
+      ../;%(AdditionalIncludeDirectories)
+      NO_MAIN_DRIVER;WOLFSSL_RIPEMD;WOLFSSL_SHA512;OPENSSL_EXTRA;NO_PSK;%(PreprocessorDefinitions)
+      MultiThreadedDLL
+      true
+      
+      Level3
+      ProgramDatabase
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+      true
+      true
+      MachineX86
+      false
+    
+  
+  
+    
+      MaxSpeed
+      true
+      ../;%(AdditionalIncludeDirectories)
+      NO_MAIN_DRIVER;WOLFSSL_RIPEMD;WOLFSSL_SHA512;OPENSSL_EXTRA;NO_PSK;WOLFSSL_DLL;%(PreprocessorDefinitions)
+      MultiThreadedDLL
+      true
+      
+      
+      Level3
+      ProgramDatabase
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+      true
+      true
+      MachineX86
+    
+  
+  
+    
+      MaxSpeed
+      true
+      ../;%(AdditionalIncludeDirectories)
+      NO_MAIN_DRIVER;WOLFSSL_RIPEMD;WOLFSSL_SHA512;OPENSSL_EXTRA;NO_PSK;%(PreprocessorDefinitions)
+      MultiThreadedDLL
+      true
+      
+      
+      Level3
+      ProgramDatabase
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+      true
+      true
+    
+  
+  
+    
+      MaxSpeed
+      true
+      ../;%(AdditionalIncludeDirectories)
+      NO_MAIN_DRIVER;WOLFSSL_RIPEMD;WOLFSSL_SHA512;OPENSSL_EXTRA;NO_PSK;WOLFSSL_DLL;%(PreprocessorDefinitions)
+      MultiThreadedDLL
+      true
+      
+      
+      Level3
+      ProgramDatabase
+    
+    
+      Ws2_32.lib;%(AdditionalDependencies)
+      true
+      Console
+      true
+      true
+    
+  
+  
+    
+    
+    
+    
+    
+    
+  
+  
+    
+      {73973223-5ee8-41ca-8e88-1d60e89a237b}
+      false
+    
+  
+  
+  
+  
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/valgrind-error.sh b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/valgrind-error.sh
new file mode 100644
index 0000000..7f7441c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/valgrind-error.sh
@@ -0,0 +1,22 @@
+#!/bin/sh
+#
+#
+# Our valgrind "error" wrapper.
+
+valgrind --leak-check=full -q "$@" 2> valgrind.tmp
+
+result="$?"
+
+# verify no errors
+
+output="`cat valgrind.tmp`"
+
+if [ "$output" != "" ]; then
+    cat valgrind.tmp >&2
+    result=1
+fi
+
+rm valgrind.tmp
+
+exit $result
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/benchmark/benchmark.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/benchmark/benchmark.c
new file mode 100644
index 0000000..f284774
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/benchmark/benchmark.c
@@ -0,0 +1,1910 @@
+/* benchmark.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+/* wolfCrypt benchmark */
+
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#include 
+
+#ifdef FREESCALE_MQX
+    #include 
+    #include 
+#else
+    #include 
+#endif
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#ifdef HAVE_ECC
+    #include 
+#endif
+#ifdef HAVE_CURVE25519
+    #include 
+#endif
+#ifdef HAVE_ED25519
+    #include 
+#endif
+
+#include 
+#ifdef HAVE_CAVIUM
+    #include "cavium_sysdep.h"
+    #include "cavium_common.h"
+    #include "cavium_ioctl.h"
+#endif
+#ifdef HAVE_NTRU
+    #include "ntru_crypto.h"
+#endif
+
+#if defined(WOLFSSL_MDK_ARM)
+    extern FILE * wolfSSL_fopen(const char *fname, const char *mode) ;
+    #define fopen wolfSSL_fopen
+#endif
+
+#if defined(__GNUC__) && defined(__x86_64__) && !defined(NO_ASM)
+    #define HAVE_GET_CYCLES
+    static INLINE word64 get_intel_cycles(void);
+    static word64 total_cycles;
+    #define BEGIN_INTEL_CYCLES total_cycles = get_intel_cycles();
+    #define END_INTEL_CYCLES   total_cycles = get_intel_cycles() - total_cycles;
+    #define SHOW_INTEL_CYCLES  printf(" Cycles per byte = %6.2f", \
+                               (float)total_cycles / (numBlocks*sizeof(plain)));
+#else
+    #define BEGIN_INTEL_CYCLES
+    #define END_INTEL_CYCLES
+    #define SHOW_INTEL_CYCLES
+#endif
+
+/* let's use buffers, we have them */
+#if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048)
+    #define USE_CERT_BUFFERS_2048
+#endif
+
+#if defined(USE_CERT_BUFFERS_1024) || defined(USE_CERT_BUFFERS_2048) \
+                                   || !defined(NO_DH)
+    /* include test cert and key buffers for use with NO_FILESYSTEM */
+    #if defined(WOLFSSL_MDK_ARM)
+        #include "cert_data.h" /* use certs_test.c for initial data, 
+                                      so other commands can share the data. */
+    #else
+        #include 
+    #endif
+#endif
+
+
+#ifdef HAVE_BLAKE2
+    #include 
+    void bench_blake2(void);
+#endif
+
+#ifdef _MSC_VER
+    /* 4996 warning to use MS extensions e.g., strcpy_s instead of strncpy */
+    #pragma warning(disable: 4996)
+#endif
+
+
+void bench_des(void);
+void bench_arc4(void);
+void bench_hc128(void);
+void bench_rabbit(void);
+void bench_chacha(void);
+void bench_chacha20_poly1305_aead(void);
+void bench_aes(int);
+void bench_aesgcm(void);
+void bench_aesccm(void);
+void bench_aesctr(void);
+void bench_poly1305(void);
+void bench_camellia(void);
+
+void bench_md5(void);
+void bench_sha(void);
+void bench_sha256(void);
+void bench_sha384(void);
+void bench_sha512(void);
+void bench_ripemd(void);
+
+void bench_rsa(void);
+void bench_rsaKeyGen(void);
+void bench_dh(void);
+#ifdef HAVE_ECC
+void bench_eccKeyGen(void);
+void bench_eccKeyAgree(void);
+#endif
+#ifdef HAVE_CURVE25519
+void bench_curve25519KeyGen(void);
+void bench_curve25519KeyAgree(void);
+#endif
+#ifdef HAVE_ED25519
+void bench_ed25519KeyGen(void);
+void bench_ed25519KeySign(void);
+#endif
+#ifdef HAVE_NTRU
+void bench_ntru(void);
+void bench_ntruKeyGen(void);
+#endif
+
+double current_time(int);
+
+
+#ifdef HAVE_CAVIUM
+
+static int OpenNitroxDevice(int dma_mode,int dev_id)
+{
+   Csp1CoreAssignment core_assign;
+   Uint32             device;
+
+   if (CspInitialize(CAVIUM_DIRECT,CAVIUM_DEV_ID))
+      return -1;
+   if (Csp1GetDevType(&device))
+      return -1;
+   if (device != NPX_DEVICE) {
+      if (ioctl(gpkpdev_hdlr[CAVIUM_DEV_ID], IOCTL_CSP1_GET_CORE_ASSIGNMENT,
+                (Uint32 *)&core_assign)!= 0)
+         return -1;
+   }
+   CspShutdown(CAVIUM_DEV_ID);
+
+   return CspInitialize(dma_mode, dev_id);
+}
+
+#endif
+
+#if defined(DEBUG_WOLFSSL) && !defined(HAVE_VALGRIND)
+    WOLFSSL_API int wolfSSL_Debugging_ON();
+#endif
+
+#if !defined(NO_RSA) || !defined(NO_DH) \
+                                || defined(WOLFSSL_KEYGEN) || defined(HAVE_ECC)
+    #define HAVE_LOCAL_RNG
+    static RNG rng;
+#endif
+
+/* use kB instead of mB for embedded benchmarking */
+#ifdef BENCH_EMBEDDED
+    static byte plain [1024];
+#else
+    static byte plain [1024*1024];
+#endif
+
+
+/* use kB instead of mB for embedded benchmarking */
+#ifdef BENCH_EMBEDDED
+    static byte cipher[1024];
+#else
+    static byte cipher[1024*1024];
+#endif
+
+
+static const XGEN_ALIGN byte key[] =
+{
+    0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef,
+    0xfe,0xde,0xba,0x98,0x76,0x54,0x32,0x10,
+    0x89,0xab,0xcd,0xef,0x01,0x23,0x45,0x67
+};
+
+static const XGEN_ALIGN byte iv[] =
+{
+    0x12,0x34,0x56,0x78,0x90,0xab,0xcd,0xef,
+    0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
+    0x11,0x21,0x31,0x41,0x51,0x61,0x71,0x81
+};
+
+
+/* so embedded projects can pull in tests on their own */
+#if !defined(NO_MAIN_DRIVER)
+
+int main(int argc, char** argv)
+
+{
+  (void)argc;
+  (void)argv;
+#else
+int benchmark_test(void *args) 
+{
+#endif
+
+    #if defined(DEBUG_WOLFSSL) && !defined(HAVE_VALGRIND)
+        wolfSSL_Debugging_ON();
+    #endif
+
+    (void)plain;
+    (void)cipher;
+    (void)key;
+    (void)iv;
+
+	#ifdef HAVE_CAVIUM
+    int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID);
+    if (ret != 0) {
+        printf("Cavium OpenNitroxDevice failed\n");
+        exit(-1);
+    }
+#endif /* HAVE_CAVIUM */
+
+#if defined(HAVE_LOCAL_RNG)
+    {
+        int rngRet = wc_InitRng(&rng);
+        if (rngRet < 0) {
+            printf("InitRNG failed\n");
+            return rngRet;
+        }
+    }
+#endif
+
+#ifndef NO_AES
+    bench_aes(0);
+    bench_aes(1);
+#endif
+#ifdef HAVE_AESGCM
+    bench_aesgcm();
+#endif
+
+#ifdef WOLFSSL_AES_COUNTER
+    bench_aesctr();
+#endif
+
+#ifdef HAVE_AESCCM
+    bench_aesccm();
+#endif
+#ifdef HAVE_CAMELLIA
+    bench_camellia();
+#endif
+#ifndef NO_RC4
+    bench_arc4();
+#endif
+#ifdef HAVE_HC128
+    bench_hc128();
+#endif
+#ifndef NO_RABBIT
+    bench_rabbit();
+#endif
+#ifdef HAVE_CHACHA
+    bench_chacha();
+#endif
+#if defined(HAVE_CHACHA) && defined(HAVE_POLY1305)
+    bench_chacha20_poly1305_aead();
+#endif
+#ifndef NO_DES3
+    bench_des();
+#endif
+    
+    printf("\n");
+
+#ifndef NO_MD5
+    bench_md5();
+#endif
+#ifdef HAVE_POLY1305
+    bench_poly1305();
+#endif
+#ifndef NO_SHA
+    bench_sha();
+#endif
+#ifndef NO_SHA256
+    bench_sha256();
+#endif
+#ifdef WOLFSSL_SHA384
+    bench_sha384();
+#endif
+#ifdef WOLFSSL_SHA512
+    bench_sha512();
+#endif
+#ifdef WOLFSSL_RIPEMD
+    bench_ripemd();
+#endif
+#ifdef HAVE_BLAKE2
+    bench_blake2();
+#endif
+
+    printf("\n");
+
+#ifndef NO_RSA
+    bench_rsa();
+#endif
+
+#ifdef HAVE_NTRU
+    bench_ntru();
+#endif
+
+#ifndef NO_DH
+    bench_dh();
+#endif
+
+#if defined(WOLFSSL_KEY_GEN) && !defined(NO_RSA)
+    bench_rsaKeyGen();
+#endif
+
+#ifdef HAVE_NTRU
+    bench_ntruKeyGen();
+#endif
+
+#ifdef HAVE_ECC
+    bench_eccKeyGen();
+    bench_eccKeyAgree();
+    #if defined(FP_ECC)
+        wc_ecc_fp_free();
+    #endif
+#endif
+
+#ifdef HAVE_CURVE25519
+    bench_curve25519KeyGen();
+    bench_curve25519KeyAgree();
+#endif
+
+#ifdef HAVE_ED25519
+    bench_ed25519KeyGen();
+    bench_ed25519KeySign();
+#endif
+
+#if defined(HAVE_LOCAL_RNG)
+    wc_FreeRng(&rng);
+#endif
+
+    return 0;
+}
+
+
+#ifdef BENCH_EMBEDDED
+enum BenchmarkBounds {
+    numBlocks  = 25, /* how many kB to test (en/de)cryption */
+    ntimes     = 1,
+    genTimes   = 5,  /* public key iterations */
+    agreeTimes = 5
+};
+static const char blockType[] = "kB";   /* used in printf output */
+#else
+enum BenchmarkBounds {
+    numBlocks  = 50,  /* how many megs to test (en/de)cryption */
+    ntimes     = 100,
+    genTimes   = 100,
+    agreeTimes = 100
+};
+static const char blockType[] = "megs"; /* used in printf output */
+#endif
+
+
+#ifndef NO_AES
+
+void bench_aes(int show)
+{
+    Aes    enc;
+    double start, total, persec;
+    int    i;
+    int    ret;
+
+#ifdef HAVE_CAVIUM
+    if (wc_AesInitCavium(&enc, CAVIUM_DEV_ID) != 0) {
+        printf("aes init cavium failed\n");
+        return;
+    }
+#endif
+
+    ret = wc_AesSetKey(&enc, key, 16, iv, AES_ENCRYPTION);
+    if (ret != 0) {
+        printf("AesSetKey failed, ret = %d\n", ret);
+        return;
+    }
+    start = current_time(1);
+    BEGIN_INTEL_CYCLES
+
+    for(i = 0; i < numBlocks; i++)
+        wc_AesCbcEncrypt(&enc, plain, cipher, sizeof(plain));
+
+    END_INTEL_CYCLES
+    total = current_time(0) - start;
+
+    persec = 1 / total * numBlocks;
+#ifdef BENCH_EMBEDDED
+    /* since using kB, convert to MB/s */
+    persec = persec / 1024;
+#endif
+
+    if (show) {
+        printf("AES      %d %s took %5.3f seconds, %8.3f MB/s", numBlocks,
+                                                  blockType, total, persec);
+        SHOW_INTEL_CYCLES
+        printf("\n");
+    }
+#ifdef HAVE_CAVIUM
+    wc_AesFreeCavium(&enc);
+#endif
+}
+#endif
+
+
+#if defined(HAVE_AESGCM) || defined(HAVE_AESCCM)
+    static byte additional[13];
+    static byte tag[16];
+#endif
+
+
+#ifdef HAVE_AESGCM
+void bench_aesgcm(void)
+{
+    Aes    enc;
+    double start, total, persec;
+    int    i;
+
+    wc_AesGcmSetKey(&enc, key, 16);
+    start = current_time(1);
+    BEGIN_INTEL_CYCLES
+
+    for(i = 0; i < numBlocks; i++)
+        wc_AesGcmEncrypt(&enc, cipher, plain, sizeof(plain), iv, 12,
+                        tag, 16, additional, 13);
+
+    END_INTEL_CYCLES
+    total = current_time(0) - start;
+
+    persec = 1 / total * numBlocks;
+#ifdef BENCH_EMBEDDED
+    /* since using kB, convert to MB/s */
+    persec = persec / 1024;
+#endif
+
+    printf("AES-GCM  %d %s took %5.3f seconds, %8.3f MB/s", numBlocks,
+                                              blockType, total, persec);
+    SHOW_INTEL_CYCLES
+    printf("\n");
+}
+#endif
+
+#ifdef WOLFSSL_AES_COUNTER
+void bench_aesctr(void)
+{
+    Aes    enc;
+    double start, total, persec;
+    int    i;
+
+    wc_AesSetKeyDirect(&enc, key, AES_BLOCK_SIZE, iv, AES_ENCRYPTION);
+    start = current_time(1);
+    BEGIN_INTEL_CYCLES
+
+    for(i = 0; i < numBlocks; i++)
+        wc_AesCtrEncrypt(&enc, plain, cipher, sizeof(plain));
+
+    END_INTEL_CYCLES
+    total = current_time(0) - start;
+
+    persec = 1 / total * numBlocks;
+#ifdef BENCH_EMBEDDED
+    /* since using kB, convert to MB/s */
+    persec = persec / 1024;
+#endif
+
+    printf("AES-CTR  %d %s took %5.3f seconds, %8.3f MB/s", numBlocks,
+                                              blockType, total, persec);
+    SHOW_INTEL_CYCLES
+    printf("\n");
+}
+#endif
+
+
+
+#ifdef HAVE_AESCCM
+void bench_aesccm(void)
+{
+    Aes    enc;
+    double start, total, persec;
+    int    i;
+
+    wc_AesCcmSetKey(&enc, key, 16);
+    start = current_time(1);
+    BEGIN_INTEL_CYCLES
+
+    for(i = 0; i < numBlocks; i++)
+        wc_AesCcmEncrypt(&enc, cipher, plain, sizeof(plain), iv, 12,
+                        tag, 16, additional, 13);
+
+    END_INTEL_CYCLES
+    total = current_time(0) - start;
+
+    persec = 1 / total * numBlocks;
+#ifdef BENCH_EMBEDDED
+    /* since using kB, convert to MB/s */
+    persec = persec / 1024;
+#endif
+
+    printf("AES-CCM  %d %s took %5.3f seconds, %8.3f MB/s", numBlocks,
+                                              blockType, total, persec);
+    SHOW_INTEL_CYCLES
+    printf("\n");
+}
+#endif
+
+
+#ifdef HAVE_POLY1305
+void bench_poly1305()
+{
+    Poly1305    enc;
+    byte   mac[16];
+    double start, total, persec;
+    int    i;
+    int    ret;
+
+
+    ret = wc_Poly1305SetKey(&enc, key, 32);
+    if (ret != 0) {
+        printf("Poly1305SetKey failed, ret = %d\n", ret);
+        return;
+    }
+    start = current_time(1);
+    BEGIN_INTEL_CYCLES
+
+    for(i = 0; i < numBlocks; i++)
+        wc_Poly1305Update(&enc, plain, sizeof(plain));
+
+    wc_Poly1305Final(&enc, mac);
+    END_INTEL_CYCLES
+    total = current_time(0) - start;
+
+    persec = 1 / total * numBlocks;
+#ifdef BENCH_EMBEDDED
+    /* since using kB, convert to MB/s */
+    persec = persec / 1024;
+#endif
+
+    printf("POLY1305 %d %s took %5.3f seconds, %8.3f MB/s", numBlocks,
+                                                  blockType, total, persec);
+    SHOW_INTEL_CYCLES
+    printf("\n");
+}
+#endif /* HAVE_POLY1305 */
+
+
+#ifdef HAVE_CAMELLIA
+void bench_camellia(void)
+{
+    Camellia cam;
+    double start, total, persec;
+    int    i, ret;
+
+    ret = wc_CamelliaSetKey(&cam, key, 16, iv);
+    if (ret != 0) {
+        printf("CamelliaSetKey failed, ret = %d\n", ret);
+        return;
+    }
+    start = current_time(1);
+    BEGIN_INTEL_CYCLES
+
+    for(i = 0; i < numBlocks; i++)
+        wc_CamelliaCbcEncrypt(&cam, plain, cipher, sizeof(plain));
+
+    END_INTEL_CYCLES
+    total = current_time(0) - start;
+
+    persec = 1 / total * numBlocks;
+#ifdef BENCH_EMBEDDED
+    /* since using kB, convert to MB/s */
+    persec = persec / 1024;
+#endif
+
+    printf("Camellia %d %s took %5.3f seconds, %8.3f MB/s", numBlocks,
+                                              blockType, total, persec);
+    SHOW_INTEL_CYCLES
+    printf("\n");
+}
+#endif
+
+
+#ifndef NO_DES3
+void bench_des(void)
+{
+    Des3   enc;
+    double start, total, persec;
+    int    i, ret;
+
+#ifdef HAVE_CAVIUM
+    if (wc_Des3_InitCavium(&enc, CAVIUM_DEV_ID) != 0)
+        printf("des3 init cavium failed\n");
+#endif
+    ret = wc_Des3_SetKey(&enc, key, iv, DES_ENCRYPTION);
+    if (ret != 0) {
+        printf("Des3_SetKey failed, ret = %d\n", ret);
+        return;
+    }
+    start = current_time(1);
+    BEGIN_INTEL_CYCLES
+
+    for(i = 0; i < numBlocks; i++)
+        wc_Des3_CbcEncrypt(&enc, plain, cipher, sizeof(plain));
+
+    END_INTEL_CYCLES
+    total = current_time(0) - start;
+
+    persec = 1 / total * numBlocks;
+#ifdef BENCH_EMBEDDED
+    /* since using kB, convert to MB/s */
+    persec = persec / 1024;
+#endif
+
+    printf("3DES     %d %s took %5.3f seconds, %8.3f MB/s", numBlocks,
+                                              blockType, total, persec);
+    SHOW_INTEL_CYCLES
+    printf("\n");
+#ifdef HAVE_CAVIUM
+    wc_Des3_FreeCavium(&enc);
+#endif
+}
+#endif
+
+
+#ifndef NO_RC4
+void bench_arc4(void)
+{
+    Arc4   enc;
+    double start, total, persec;
+    int    i;
+    
+#ifdef HAVE_CAVIUM
+    if (wc_Arc4InitCavium(&enc, CAVIUM_DEV_ID) != 0)
+        printf("arc4 init cavium failed\n");
+#endif
+
+    wc_Arc4SetKey(&enc, key, 16);
+    start = current_time(1);
+    BEGIN_INTEL_CYCLES
+
+    for(i = 0; i < numBlocks; i++)
+        wc_Arc4Process(&enc, cipher, plain, sizeof(plain));
+
+    END_INTEL_CYCLES
+    total = current_time(0) - start;
+    persec = 1 / total * numBlocks;
+#ifdef BENCH_EMBEDDED
+    /* since using kB, convert to MB/s */
+    persec = persec / 1024;
+#endif
+
+    printf("ARC4     %d %s took %5.3f seconds, %8.3f MB/s", numBlocks,
+                                              blockType, total, persec);
+    SHOW_INTEL_CYCLES
+    printf("\n");
+#ifdef HAVE_CAVIUM
+    wc_Arc4FreeCavium(&enc);
+#endif
+}
+#endif
+
+
+#ifdef HAVE_HC128
+void bench_hc128(void)
+{
+    HC128  enc;
+    double start, total, persec;
+    int    i;
+    
+    wc_Hc128_SetKey(&enc, key, iv);
+    start = current_time(1);
+    BEGIN_INTEL_CYCLES
+
+    for(i = 0; i < numBlocks; i++)
+        wc_Hc128_Process(&enc, cipher, plain, sizeof(plain));
+
+    END_INTEL_CYCLES
+    total = current_time(0) - start;
+    persec = 1 / total * numBlocks;
+#ifdef BENCH_EMBEDDED
+    /* since using kB, convert to MB/s */
+    persec = persec / 1024;
+#endif
+
+    printf("HC128    %d %s took %5.3f seconds, %8.3f MB/s", numBlocks,
+                                              blockType, total, persec);
+    SHOW_INTEL_CYCLES
+    printf("\n");
+}
+#endif /* HAVE_HC128 */
+
+
+#ifndef NO_RABBIT
+void bench_rabbit(void)
+{
+    Rabbit  enc;
+    double start, total, persec;
+    int    i;
+    
+    wc_RabbitSetKey(&enc, key, iv);
+    start = current_time(1);
+    BEGIN_INTEL_CYCLES
+
+    for(i = 0; i < numBlocks; i++)
+        wc_RabbitProcess(&enc, cipher, plain, sizeof(plain));
+
+    END_INTEL_CYCLES
+    total = current_time(0) - start;
+    persec = 1 / total * numBlocks;
+#ifdef BENCH_EMBEDDED
+    /* since using kB, convert to MB/s */
+    persec = persec / 1024;
+#endif
+
+    printf("RABBIT   %d %s took %5.3f seconds, %8.3f MB/s", numBlocks,
+                                              blockType, total, persec);
+    SHOW_INTEL_CYCLES
+    printf("\n");
+}
+#endif /* NO_RABBIT */
+
+
+#ifdef HAVE_CHACHA
+void bench_chacha(void)
+{
+    ChaCha enc;
+    double start, total, persec;
+    int    i;
+
+    wc_Chacha_SetKey(&enc, key, 16);
+    start = current_time(1);
+    BEGIN_INTEL_CYCLES
+
+    for (i = 0; i < numBlocks; i++) {
+        wc_Chacha_SetIV(&enc, iv, 0);
+        wc_Chacha_Process(&enc, cipher, plain, sizeof(plain));
+    }
+
+    END_INTEL_CYCLES
+    total = current_time(0) - start;
+    persec = 1 / total * numBlocks;
+#ifdef BENCH_EMBEDDED
+    /* since using kB, convert to MB/s */
+    persec = persec / 1024;
+#endif
+
+    printf("CHACHA   %d %s took %5.3f seconds, %8.3f MB/s", numBlocks, blockType, total, persec);
+    SHOW_INTEL_CYCLES
+    printf("\n");
+
+}
+#endif /* HAVE_CHACHA*/
+
+#if( defined( HAVE_CHACHA ) && defined( HAVE_POLY1305 ) )
+void bench_chacha20_poly1305_aead(void)
+{
+    double start, total, persec;
+    int    i;
+
+    byte authTag[CHACHA20_POLY1305_AEAD_AUTHTAG_SIZE];
+    XMEMSET( authTag, 0, sizeof( authTag ) );
+
+    start = current_time(1);
+    BEGIN_INTEL_CYCLES
+
+    for (i = 0; i < numBlocks; i++)
+    {
+        wc_ChaCha20Poly1305_Encrypt(key, iv, NULL, 0, plain, sizeof(plain),
+                                    cipher, authTag );
+    }
+
+    END_INTEL_CYCLES
+    total = current_time(0) - start;
+    persec = 1 / total * numBlocks;
+#ifdef BENCH_EMBEDDED
+    /* since using kB, convert to MB/s */
+    persec = persec / 1024;
+#endif
+
+    printf("CHA-POLY %d %s took %5.3f seconds, %8.3f MB/s",
+           numBlocks, blockType, total, persec);
+    SHOW_INTEL_CYCLES
+    printf("\n");
+
+}
+#endif /* HAVE_CHACHA && HAVE_POLY1305 */
+
+
+#ifndef NO_MD5
+void bench_md5(void)
+{
+    Md5    hash;
+    byte   digest[MD5_DIGEST_SIZE];
+    double start, total, persec;
+    int    i;
+
+    wc_InitMd5(&hash);
+    start = current_time(1);
+    BEGIN_INTEL_CYCLES
+
+    for(i = 0; i < numBlocks; i++)
+        wc_Md5Update(&hash, plain, sizeof(plain));
+   
+    wc_Md5Final(&hash, digest);
+
+    END_INTEL_CYCLES
+    total = current_time(0) - start;
+    persec = 1 / total * numBlocks;
+#ifdef BENCH_EMBEDDED
+    /* since using kB, convert to MB/s */
+    persec = persec / 1024;
+#endif
+
+    printf("MD5      %d %s took %5.3f seconds, %8.3f MB/s", numBlocks,
+                                              blockType, total, persec);
+    SHOW_INTEL_CYCLES
+    printf("\n");
+}
+#endif /* NO_MD5 */
+
+
+#ifndef NO_SHA
+void bench_sha(void)
+{
+    Sha    hash;
+    byte   digest[SHA_DIGEST_SIZE];
+    double start, total, persec;
+    int    i, ret;
+        
+    ret = wc_InitSha(&hash);
+    if (ret != 0) {
+        printf("InitSha failed, ret = %d\n", ret);
+        return;
+    }
+    start = current_time(1);
+    BEGIN_INTEL_CYCLES
+    
+    for(i = 0; i < numBlocks; i++)
+        wc_ShaUpdate(&hash, plain, sizeof(plain));
+   
+    wc_ShaFinal(&hash, digest);
+
+    END_INTEL_CYCLES
+    total = current_time(0) - start;
+    persec = 1 / total * numBlocks;
+#ifdef BENCH_EMBEDDED
+    /* since using kB, convert to MB/s */
+    persec = persec / 1024;
+#endif
+
+    printf("SHA      %d %s took %5.3f seconds, %8.3f MB/s", numBlocks,
+                                              blockType, total, persec);
+    SHOW_INTEL_CYCLES
+    printf("\n");
+}
+#endif /* NO_SHA */
+
+
+#ifndef NO_SHA256
+void bench_sha256(void)
+{
+    Sha256 hash;
+    byte   digest[SHA256_DIGEST_SIZE];
+    double start, total, persec;
+    int    i, ret;
+
+    ret = wc_InitSha256(&hash);
+    if (ret != 0) {
+        printf("InitSha256 failed, ret = %d\n", ret);
+        return;
+    }
+    start = current_time(1);
+    BEGIN_INTEL_CYCLES
+
+    for(i = 0; i < numBlocks; i++) {
+        ret = wc_Sha256Update(&hash, plain, sizeof(plain));
+        if (ret != 0) {
+            printf("Sha256Update failed, ret = %d\n", ret);
+            return;
+        }
+    }
+
+    ret = wc_Sha256Final(&hash, digest);
+    if (ret != 0) {
+        printf("Sha256Final failed, ret = %d\n", ret);
+        return;
+    }
+
+    END_INTEL_CYCLES
+    total = current_time(0) - start;
+    persec = 1 / total * numBlocks;
+#ifdef BENCH_EMBEDDED
+    /* since using kB, convert to MB/s */
+    persec = persec / 1024;
+#endif
+
+    printf("SHA-256  %d %s took %5.3f seconds, %8.3f MB/s", numBlocks,
+                                              blockType, total, persec);
+    SHOW_INTEL_CYCLES
+    printf("\n");
+}
+#endif
+
+#ifdef WOLFSSL_SHA384
+void bench_sha384(void)
+{
+    Sha384 hash;
+    byte   digest[SHA384_DIGEST_SIZE];
+    double start, total, persec;
+    int    i, ret;
+
+    ret = wc_InitSha384(&hash);
+    if (ret != 0) {
+        printf("InitSha384 failed, ret = %d\n", ret);
+        return;
+    }
+    start = current_time(1);
+    BEGIN_INTEL_CYCLES
+
+    for(i = 0; i < numBlocks; i++) {
+        ret = wc_Sha384Update(&hash, plain, sizeof(plain));
+        if (ret != 0) {
+            printf("Sha384Update failed, ret = %d\n", ret);
+            return;
+        }
+    }
+
+    ret = wc_Sha384Final(&hash, digest);
+    if (ret != 0) {
+        printf("Sha384Final failed, ret = %d\n", ret);
+        return;
+    }
+
+    END_INTEL_CYCLES
+    total = current_time(0) - start;
+    persec = 1 / total * numBlocks;
+#ifdef BENCH_EMBEDDED
+    /* since using kB, convert to MB/s */
+    persec = persec / 1024;
+#endif
+
+    printf("SHA-384  %d %s took %5.3f seconds, %8.3f MB/s", numBlocks,
+                                              blockType, total, persec);
+    SHOW_INTEL_CYCLES
+    printf("\n");
+}
+#endif
+
+#ifdef WOLFSSL_SHA512
+void bench_sha512(void)
+{
+    Sha512 hash;
+    byte   digest[SHA512_DIGEST_SIZE];
+    double start, total, persec;
+    int    i, ret;
+        
+    ret = wc_InitSha512(&hash);
+    if (ret != 0) {
+        printf("InitSha512 failed, ret = %d\n", ret);
+        return;
+    }
+    start = current_time(1);
+    BEGIN_INTEL_CYCLES
+    
+    for(i = 0; i < numBlocks; i++) {
+        ret = wc_Sha512Update(&hash, plain, sizeof(plain));
+        if (ret != 0) {
+            printf("Sha512Update failed, ret = %d\n", ret);
+            return;
+        }
+    }
+
+    ret = wc_Sha512Final(&hash, digest);
+    if (ret != 0) {
+        printf("Sha512Final failed, ret = %d\n", ret);
+        return;
+    }
+
+    END_INTEL_CYCLES
+    total = current_time(0) - start;
+    persec = 1 / total * numBlocks;
+#ifdef BENCH_EMBEDDED
+    /* since using kB, convert to MB/s */
+    persec = persec / 1024;
+#endif
+
+    printf("SHA-512  %d %s took %5.3f seconds, %8.3f MB/s", numBlocks,
+                                              blockType, total, persec);
+    SHOW_INTEL_CYCLES
+    printf("\n");
+}
+#endif
+
+#ifdef WOLFSSL_RIPEMD
+void bench_ripemd(void)
+{
+    RipeMd hash;
+    byte   digest[RIPEMD_DIGEST_SIZE];
+    double start, total, persec;
+    int    i;
+        
+    wc_InitRipeMd(&hash);
+    start = current_time(1);
+    BEGIN_INTEL_CYCLES
+    
+    for(i = 0; i < numBlocks; i++)
+        wc_RipeMdUpdate(&hash, plain, sizeof(plain));
+   
+    wc_RipeMdFinal(&hash, digest);
+
+    END_INTEL_CYCLES
+    total = current_time(0) - start;
+    persec = 1 / total * numBlocks;
+#ifdef BENCH_EMBEDDED
+    /* since using kB, convert to MB/s */
+    persec = persec / 1024;
+#endif
+
+    printf("RIPEMD   %d %s took %5.3f seconds, %8.3f MB/s", numBlocks,
+                                              blockType, total, persec);
+    SHOW_INTEL_CYCLES
+    printf("\n");
+}
+#endif
+
+
+#ifdef HAVE_BLAKE2
+void bench_blake2(void)
+{
+    Blake2b b2b;
+    byte    digest[64];
+    double  start, total, persec;
+    int     i, ret;
+       
+    ret = wc_InitBlake2b(&b2b, 64);
+    if (ret != 0) {
+        printf("InitBlake2b failed, ret = %d\n", ret);
+        return;
+    }
+    start = current_time(1);
+    BEGIN_INTEL_CYCLES
+    
+    for(i = 0; i < numBlocks; i++) {
+        ret = wc_Blake2bUpdate(&b2b, plain, sizeof(plain));
+        if (ret != 0) {
+            printf("Blake2bUpdate failed, ret = %d\n", ret);
+            return;
+        }
+    }
+   
+    ret = wc_Blake2bFinal(&b2b, digest, 64);
+    if (ret != 0) {
+        printf("Blake2bFinal failed, ret = %d\n", ret);
+        return;
+    }
+
+    END_INTEL_CYCLES
+    total = current_time(0) - start;
+    persec = 1 / total * numBlocks;
+#ifdef BENCH_EMBEDDED
+    /* since using kB, convert to MB/s */
+    persec = persec / 1024;
+#endif
+
+    printf("BLAKE2b  %d %s took %5.3f seconds, %8.3f MB/s", numBlocks,
+                                              blockType, total, persec);
+    SHOW_INTEL_CYCLES
+    printf("\n");
+}
+#endif
+
+
+#ifndef NO_RSA
+
+
+#if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048)
+    #if defined(WOLFSSL_MDK_SHELL)
+        static char *certRSAname = "certs/rsa2048.der";
+        /* set by shell command */
+        static void set_Bench_RSA_File(char * cert) { certRSAname = cert ; }
+    #elif defined(FREESCALE_MQX)
+        static char *certRSAname = "a:\\certs\\rsa2048.der";
+    #else
+        static const char *certRSAname = "certs/rsa2048.der";
+    #endif
+#endif
+
+void bench_rsa(void)
+{
+    int    i;
+    int    ret;
+    size_t bytes;
+    word32 idx = 0;
+    const byte* tmp;
+
+    byte      message[] = "Everyone gets Friday off.";
+    byte      enc[256];  /* for up to 2048 bit */
+    const int len = (int)strlen((char*)message);
+    double    start, total, each, milliEach;
+
+    RsaKey rsaKey;
+    int    rsaKeySz = 2048; /* used in printf */
+
+#ifdef USE_CERT_BUFFERS_1024
+    tmp = rsa_key_der_1024;
+    bytes = sizeof_rsa_key_der_1024;
+    rsaKeySz = 1024;
+#elif defined(USE_CERT_BUFFERS_2048)
+    tmp = rsa_key_der_2048;
+    bytes = sizeof_rsa_key_der_2048;
+#else
+    #error "need a cert buffer size"
+#endif /* USE_CERT_BUFFERS */
+
+
+#ifdef HAVE_CAVIUM
+    if (wc_RsaInitCavium(&rsaKey, CAVIUM_DEV_ID) != 0)
+        printf("RSA init cavium failed\n");
+#endif
+    ret = wc_InitRsaKey(&rsaKey, 0);
+    if (ret < 0) {
+        printf("InitRsaKey failed\n");
+        return;
+    }
+    ret = wc_RsaPrivateKeyDecode(tmp, &idx, &rsaKey, (word32)bytes);
+
+    start = current_time(1);
+
+    for (i = 0; i < ntimes; i++)
+        ret = wc_RsaPublicEncrypt(message,len,enc,sizeof(enc), &rsaKey, &rng);
+
+    total = current_time(0) - start;
+    each  = total / ntimes;   /* per second   */
+    milliEach = each * 1000; /* milliseconds */
+
+    printf("RSA %d encryption took %6.3f milliseconds, avg over %d"
+           " iterations\n", rsaKeySz, milliEach, ntimes);
+
+    if (ret < 0) {
+        printf("Rsa Public Encrypt failed\n");
+        return;
+    }
+
+    start = current_time(1);
+
+    for (i = 0; i < ntimes; i++) {
+         byte  out[256];  /* for up to 2048 bit */
+         wc_RsaPrivateDecrypt(enc, (word32)ret, out, sizeof(out), &rsaKey);
+    }
+
+    total = current_time(0) - start;
+    each  = total / ntimes;   /* per second   */
+    milliEach = each * 1000; /* milliseconds */
+
+    printf("RSA %d decryption took %6.3f milliseconds, avg over %d"
+           " iterations\n", rsaKeySz, milliEach, ntimes);
+
+    wc_FreeRsaKey(&rsaKey);
+#ifdef HAVE_CAVIUM
+    wc_RsaFreeCavium(&rsaKey);
+#endif
+}
+#endif
+
+
+#ifndef NO_DH
+
+
+#if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048)
+    #if defined(WOLFSSL_MDK_SHELL)
+        static char *certDHname = "certs/dh2048.der";
+        /* set by shell command */
+        void set_Bench_DH_File(char * cert) { certDHname = cert ; }
+    #elif defined(FREESCALE_MQX)
+        static char *certDHname = "a:\\certs\\dh2048.der";
+    #elif defined(NO_ASN)
+        /* do nothing, but don't need a file */
+    #else
+        static const char *certDHname = "certs/dh2048.der";
+    #endif
+#endif
+
+void bench_dh(void)
+{
+    int    i ;
+    size_t bytes;
+    word32 idx = 0, pubSz, privSz = 0, pubSz2, privSz2, agreeSz;
+    const byte* tmp;
+
+    byte   pub[256];    /* for 2048 bit */
+    byte   pub2[256];   /* for 2048 bit */
+    byte   agree[256];  /* for 2048 bit */
+    byte   priv[32];    /* for 2048 bit */
+    byte   priv2[32];   /* for 2048 bit */
+
+    double start, total, each, milliEach;
+    DhKey  dhKey;
+    int    dhKeySz = 2048; /* used in printf */
+
+    (void)idx;
+    (void)tmp;
+
+
+#ifdef USE_CERT_BUFFERS_1024
+    tmp = dh_key_der_1024;
+    bytes = sizeof_dh_key_der_1024;
+    dhKeySz = 1024;
+#elif defined(USE_CERT_BUFFERS_2048)
+    tmp = dh_key_der_2048;
+    bytes = sizeof_dh_key_der_2048;
+#elif defined(NO_ASN)
+    dhKeySz = 1024;
+    /* do nothing, but don't use default FILE */
+#else
+    #error "need to define a cert buffer size"
+#endif /* USE_CERT_BUFFERS */
+
+		
+    wc_InitDhKey(&dhKey);
+#ifdef NO_ASN
+    bytes = wc_DhSetKey(&dhKey, dh_p, sizeof(dh_p), dh_g, sizeof(dh_g));
+#else
+    bytes = wc_DhKeyDecode(tmp, &idx, &dhKey, (word32)bytes);
+#endif
+    if (bytes != 0) {
+        printf("dhekydecode failed, can't benchmark\n");
+        return;
+    }
+
+    start = current_time(1);
+
+    for (i = 0; i < ntimes; i++)
+        wc_DhGenerateKeyPair(&dhKey, &rng, priv, &privSz, pub, &pubSz);
+
+    total = current_time(0) - start;
+    each  = total / ntimes;   /* per second   */
+    milliEach = each * 1000; /* milliseconds */
+
+    printf("DH  %d key generation  %6.3f milliseconds, avg over %d"
+           " iterations\n", dhKeySz, milliEach, ntimes);
+
+    wc_DhGenerateKeyPair(&dhKey, &rng, priv2, &privSz2, pub2, &pubSz2);
+    start = current_time(1);
+
+    for (i = 0; i < ntimes; i++)
+        wc_DhAgree(&dhKey, agree, &agreeSz, priv, privSz, pub2, pubSz2);
+
+    total = current_time(0) - start;
+    each  = total / ntimes;   /* per second   */
+    milliEach = each * 1000; /* milliseconds */
+
+    printf("DH  %d key agreement   %6.3f milliseconds, avg over %d"
+           " iterations\n", dhKeySz, milliEach, ntimes);
+
+    wc_FreeDhKey(&dhKey);
+}
+#endif
+
+#if defined(WOLFSSL_KEY_GEN) && !defined(NO_RSA)
+void bench_rsaKeyGen(void)
+{
+    RsaKey genKey;
+    double start, total, each, milliEach;
+    int    i;
+  
+    /* 1024 bit */ 
+    start = current_time(1);
+
+    for(i = 0; i < genTimes; i++) {
+        wc_InitRsaKey(&genKey, 0); 
+        wc_MakeRsaKey(&genKey, 1024, 65537, &rng);
+        wc_FreeRsaKey(&genKey);
+    }
+
+    total = current_time(0) - start;
+    each  = total / genTimes;  /* per second  */
+    milliEach = each * 1000;   /* millisconds */
+    printf("\n");
+    printf("RSA 1024 key generation  %6.3f milliseconds, avg over %d"
+           " iterations\n", milliEach, genTimes);
+
+    /* 2048 bit */
+    start = current_time(1);
+
+    for(i = 0; i < genTimes; i++) {
+        wc_InitRsaKey(&genKey, 0); 
+        wc_MakeRsaKey(&genKey, 2048, 65537, &rng);
+        wc_FreeRsaKey(&genKey);
+    }
+
+    total = current_time(0) - start;
+    each  = total / genTimes;  /* per second  */
+    milliEach = each * 1000;   /* millisconds */
+    printf("RSA 2048 key generation  %6.3f milliseconds, avg over %d"
+           " iterations\n", milliEach, genTimes);
+}
+#endif /* WOLFSSL_KEY_GEN */
+#ifdef HAVE_NTRU
+byte GetEntropy(ENTROPY_CMD cmd, byte* out);
+
+byte GetEntropy(ENTROPY_CMD cmd, byte* out)
+{
+    if (cmd == INIT)
+        return (wc_InitRng(&rng) == 0) ? 1 : 0;
+
+    if (out == NULL)
+        return 0;
+
+    if (cmd == GET_BYTE_OF_ENTROPY)
+        return (wc_RNG_GenerateBlock(&rng, out, 1) == 0) ? 1 : 0;
+
+    if (cmd == GET_NUM_BYTES_PER_BYTE_OF_ENTROPY) {
+        *out = 1;
+        return 1;
+    }
+
+    return 0;
+}
+
+void bench_ntru(void)
+{
+    int    i;
+    double start, total, each, milliEach;
+
+    byte   public_key[557];
+    word16 public_key_len = sizeof(public_key);
+    byte   private_key[607];
+    word16 private_key_len = sizeof(private_key);
+
+    byte ciphertext[552];
+    word16 ciphertext_len;
+    byte plaintext[16];
+    word16 plaintext_len;
+
+    DRBG_HANDLE drbg;
+    static byte const aes_key[] = {
+        0xf3, 0xe9, 0x87, 0xbb, 0x18, 0x08, 0x3c, 0xaa,
+        0x7b, 0x12, 0x49, 0x88, 0xaf, 0xb3, 0x22, 0xd8
+    };
+
+    static byte const cyasslStr[] = {
+        'C', 'y', 'a', 'S', 'S', 'L', ' ', 'N', 'T', 'R', 'U'
+    };
+
+    word32 rc = ntru_crypto_drbg_instantiate(112, cyasslStr, sizeof(cyasslStr),
+                                            (ENTROPY_FN) GetEntropy, &drbg);
+    if(rc != DRBG_OK) {
+        printf("NTRU drbg instantiate failed\n");
+        return;
+    }
+
+    rc = ntru_crypto_ntru_encrypt_keygen(drbg, NTRU_EES401EP2, 
+        &public_key_len, NULL, &private_key_len, NULL);
+    if (rc != NTRU_OK) {
+        ntru_crypto_drbg_uninstantiate(drbg);
+        printf("NTRU failed to get key lengths\n");
+        return;
+    }
+
+    rc = ntru_crypto_ntru_encrypt_keygen(drbg, NTRU_EES401EP2, &public_key_len,
+                                     public_key, &private_key_len, 
+                                     private_key);
+
+    ntru_crypto_drbg_uninstantiate(drbg);
+
+    if (rc != NTRU_OK) {
+        ntru_crypto_drbg_uninstantiate(drbg);
+        printf("NTRU keygen failed\n");
+        return;
+    }
+
+    rc = ntru_crypto_drbg_instantiate(112, NULL, 0, (ENTROPY_FN)GetEntropy,
+                                      &drbg);
+    if (rc != DRBG_OK) {
+        printf("NTRU error occurred during DRBG instantiation\n");
+        return;
+    }
+
+    rc = ntru_crypto_ntru_encrypt(drbg, public_key_len, public_key, sizeof(
+        aes_key), aes_key, &ciphertext_len, NULL);
+
+    if (rc != NTRU_OK) {
+        printf("NTRU error occurred requesting the buffer size needed\n");
+        return;
+    }
+    start = current_time(1);
+
+    for (i = 0; i < ntimes; i++) {
+
+        rc = ntru_crypto_ntru_encrypt(drbg, public_key_len, public_key, sizeof(
+            aes_key), aes_key, &ciphertext_len, ciphertext);
+
+        if (rc != NTRU_OK) {
+            printf("NTRU encrypt error\n");
+            return;
+        }
+
+    }
+    rc = ntru_crypto_drbg_uninstantiate(drbg);
+
+    if (rc != DRBG_OK) {
+        printf("NTRU error occurred uninstantiating the DRBG\n");
+        return;
+    }
+
+    total = current_time(0) - start;
+    each  = total / ntimes;   /* per second   */
+    milliEach = each * 1000; /* milliseconds */
+
+    printf("NTRU 112 encryption took %6.3f milliseconds, avg over %d"
+           " iterations\n", milliEach, ntimes);
+
+
+    rc = ntru_crypto_ntru_decrypt(private_key_len, private_key, ciphertext_len,
+                                  ciphertext, &plaintext_len, NULL);
+
+    if (rc != NTRU_OK) {
+        printf("NTRU decrypt error occurred getting the buffer size needed\n");
+        return;
+    }
+
+    plaintext_len = sizeof(plaintext);
+    start = current_time(1);
+
+    for (i = 0; i < ntimes; i++) {
+        rc = ntru_crypto_ntru_decrypt(private_key_len, private_key,
+                                      ciphertext_len, ciphertext,
+                                      &plaintext_len, plaintext);
+
+        if (rc != NTRU_OK) {
+            printf("NTRU error occurred decrypting the key\n");
+            return;
+        }
+    }
+
+    total = current_time(0) - start;
+    each  = total / ntimes;   /* per second   */
+    milliEach = each * 1000; /* milliseconds */
+
+    printf("NTRU 112 decryption took %6.3f milliseconds, avg over %d"
+           " iterations\n", milliEach, ntimes);
+}
+
+void bench_ntruKeyGen(void)
+{
+    double start, total, each, milliEach;
+    int    i;
+
+    byte   public_key[557]; /* 2048 key equivalent to rsa */
+    word16 public_key_len = sizeof(public_key);
+    byte   private_key[607];
+    word16 private_key_len = sizeof(private_key);
+
+    DRBG_HANDLE drbg;
+    static uint8_t const pers_str[] = {
+                'C', 'y', 'a', 'S', 'S', 'L', ' ', 't', 'e', 's', 't'
+    };
+
+    word32 rc = ntru_crypto_drbg_instantiate(112, pers_str, sizeof(pers_str),
+                                             GetEntropy, &drbg);
+    if(rc != DRBG_OK) {
+        printf("NTRU drbg instantiate failed\n");
+        return;
+    }
+
+    start = current_time(1);
+
+    for(i = 0; i < genTimes; i++) {
+        ntru_crypto_ntru_encrypt_keygen(drbg, NTRU_EES401EP2, &public_key_len,
+                                     public_key, &private_key_len, 
+                                     private_key);
+    }
+
+    total = current_time(0) - start;
+
+    rc = ntru_crypto_drbg_uninstantiate(drbg);
+
+    if (rc != NTRU_OK) {
+        printf("NTRU drbg uninstantiate failed\n");
+        return;
+    }
+
+    each = total / genTimes;
+    milliEach = each * 1000;
+
+    printf("\n");
+    printf("NTRU 112 key generation  %6.3f milliseconds, avg over %d"
+        " iterations\n", milliEach, genTimes);
+
+}
+#endif
+
+#ifdef HAVE_ECC 
+void bench_eccKeyGen(void)
+{
+    ecc_key genKey;
+    double start, total, each, milliEach;
+    int    i;
+  
+    /* 256 bit */ 
+    start = current_time(1);
+
+    for(i = 0; i < genTimes; i++) {
+        wc_ecc_init(&genKey);
+        wc_ecc_make_key(&rng, 32, &genKey);
+        wc_ecc_free(&genKey);
+    }
+
+    total = current_time(0) - start;
+    each  = total / genTimes;  /* per second  */
+    milliEach = each * 1000;   /* millisconds */
+    printf("\n");
+    printf("ECC  256 key generation  %6.3f milliseconds, avg over %d"
+           " iterations\n", milliEach, genTimes);
+}
+
+
+void bench_eccKeyAgree(void)
+{
+    ecc_key genKey, genKey2;
+    double start, total, each, milliEach;
+    int    i, ret;
+    byte   shared[32];
+    byte   sig[64+16];  /* der encoding too */
+    byte   digest[32];
+    word32 x = 0;
+
+    wc_ecc_init(&genKey);
+    wc_ecc_init(&genKey2);
+
+    ret = wc_ecc_make_key(&rng, 32, &genKey);
+    if (ret != 0) {
+        printf("ecc_make_key failed\n");
+        return;
+    }
+    ret = wc_ecc_make_key(&rng, 32, &genKey2);
+    if (ret != 0) {
+        printf("ecc_make_key failed\n");
+        return;
+    }
+
+    /* 256 bit */
+    start = current_time(1);
+
+    for(i = 0; i < agreeTimes; i++) {
+        x = sizeof(shared);
+        ret = wc_ecc_shared_secret(&genKey, &genKey2, shared, &x);
+        if (ret != 0) {
+            printf("ecc_shared_secret failed\n");
+            return;
+        }
+    }
+
+    total = current_time(0) - start;
+    each  = total / agreeTimes;  /* per second  */
+    milliEach = each * 1000;   /* millisconds */
+    printf("EC-DHE   key agreement   %6.3f milliseconds, avg over %d"
+           " iterations\n", milliEach, agreeTimes);
+
+    /* make dummy digest */
+    for (i = 0; i < (int)sizeof(digest); i++)
+        digest[i] = (byte)i;
+
+
+    start = current_time(1);
+
+    for(i = 0; i < agreeTimes; i++) {
+        x = sizeof(sig);
+        ret = wc_ecc_sign_hash(digest, sizeof(digest), sig, &x, &rng, &genKey);
+        if (ret != 0) {
+            printf("ecc_sign_hash failed\n");
+            return; 
+        }
+    }
+
+    total = current_time(0) - start;
+    each  = total / agreeTimes;  /* per second  */
+    milliEach = each * 1000;   /* millisconds */
+    printf("EC-DSA   sign   time     %6.3f milliseconds, avg over %d"
+           " iterations\n", milliEach, agreeTimes);
+
+    start = current_time(1);
+
+    for(i = 0; i < agreeTimes; i++) {
+        int verify = 0;
+        ret = wc_ecc_verify_hash(sig, x, digest, sizeof(digest), &verify, &genKey);
+        if (ret != 0) {
+            printf("ecc_verify_hash failed\n");
+            return; 
+        }
+    }
+
+    total = current_time(0) - start;
+    each  = total / agreeTimes;  /* per second  */
+    milliEach = each * 1000;     /* millisconds */
+    printf("EC-DSA   verify time     %6.3f milliseconds, avg over %d"
+           " iterations\n", milliEach, agreeTimes);
+
+    wc_ecc_free(&genKey2);
+    wc_ecc_free(&genKey);
+}
+#endif /* HAVE_ECC */
+
+#ifdef HAVE_CURVE25519
+void bench_curve25519KeyGen(void)
+{
+    curve25519_key genKey;
+    double start, total, each, milliEach;
+    int    i;
+
+    /* 256 bit */
+    start = current_time(1);
+
+    for(i = 0; i < genTimes; i++) {
+        wc_curve25519_make_key(&rng, 32, &genKey);
+        wc_curve25519_free(&genKey);
+    }
+
+    total = current_time(0) - start;
+    each  = total / genTimes;  /* per second  */
+    milliEach = each * 1000;   /* millisconds */
+    printf("\n");
+    printf("CURVE25519 256 key generation %6.3f milliseconds, avg over %d"
+           " iterations\n", milliEach, genTimes);
+}
+
+
+void bench_curve25519KeyAgree(void)
+{
+    curve25519_key genKey, genKey2;
+    double start, total, each, milliEach;
+    int    i, ret;
+    byte   shared[32];
+    word32 x = 0;
+
+    wc_curve25519_init(&genKey);
+    wc_curve25519_init(&genKey2);
+
+    ret = wc_curve25519_make_key(&rng, 32, &genKey);
+    if (ret != 0) {
+        printf("curve25519_make_key failed\n");
+        return;
+    }
+    ret = wc_curve25519_make_key(&rng, 32, &genKey2);
+    if (ret != 0) {
+        printf("curve25519_make_key failed\n");
+        return;
+    }
+
+    /* 256 bit */
+    start = current_time(1);
+
+    for(i = 0; i < agreeTimes; i++) {
+        x = sizeof(shared);
+        ret = wc_curve25519_shared_secret(&genKey, &genKey2, shared, &x);
+        if (ret != 0) {
+            printf("curve25519_shared_secret failed\n");
+            return;
+        }
+    }
+
+    total = current_time(0) - start;
+    each  = total / agreeTimes;  /* per second  */
+    milliEach = each * 1000;   /* millisconds */
+    printf("CURVE25519 key agreement      %6.3f milliseconds, avg over %d"
+           " iterations\n", milliEach, agreeTimes);
+
+    wc_curve25519_free(&genKey2);
+    wc_curve25519_free(&genKey);
+}
+#endif /* HAVE_CURVE25519 */
+
+#ifdef HAVE_ED25519
+void bench_ed25519KeyGen(void)
+{
+    ed25519_key genKey;
+    double start, total, each, milliEach;
+    int    i;
+
+    /* 256 bit */
+    start = current_time(1);
+
+    for(i = 0; i < genTimes; i++) {
+        wc_ed25519_init(&genKey);
+        wc_ed25519_make_key(&rng, 32, &genKey);
+        wc_ed25519_free(&genKey);
+    }
+
+    total = current_time(0) - start;
+    each  = total / genTimes;  /* per second  */
+    milliEach = each * 1000;   /* millisconds */
+    printf("\n");
+    printf("ED25519  key generation  %6.3f milliseconds, avg over %d"
+           " iterations\n", milliEach, genTimes);
+}
+
+
+void bench_ed25519KeySign(void)
+{
+    ed25519_key genKey;
+    double start, total, each, milliEach;
+    int    i, ret;
+    byte   sig[ED25519_SIG_SIZE];
+    byte   msg[512];
+    word32 x = 0;
+
+    wc_ed25519_init(&genKey);
+
+    ret = wc_ed25519_make_key(&rng, ED25519_KEY_SIZE, &genKey);
+    if (ret != 0) {
+        printf("ed25519_make_key failed\n");
+        return;
+    }
+    /* make dummy msg */
+    for (i = 0; i < (int)sizeof(msg); i++)
+        msg[i] = (byte)i;
+
+
+    start = current_time(1);
+
+    for(i = 0; i < agreeTimes; i++) {
+        x = sizeof(sig);
+        ret = wc_ed25519_sign_msg(msg, sizeof(msg), sig, &x, &genKey);
+        if (ret != 0) {
+            printf("ed25519_sign_msg failed\n");
+            return;
+        }
+    }
+
+    total = current_time(0) - start;
+    each  = total / agreeTimes;  /* per second  */
+    milliEach = each * 1000;   /* millisconds */
+    printf("ED25519  sign   time     %6.3f milliseconds, avg over %d"
+           " iterations\n", milliEach, agreeTimes);
+
+    start = current_time(1);
+
+    for(i = 0; i < agreeTimes; i++) {
+        int verify = 0;
+        ret = wc_ed25519_verify_msg(sig, x, msg, sizeof(msg), &verify,
+                                    &genKey);
+        if (ret != 0 || verify != 1) {
+            printf("ed25519_verify_msg failed\n");
+            return;
+        }
+    }
+
+    total = current_time(0) - start;
+    each  = total / agreeTimes;  /* per second  */
+    milliEach = each * 1000;     /* millisconds */
+    printf("ED25519  verify time     %6.3f milliseconds, avg over %d"
+           " iterations\n", milliEach, agreeTimes);
+
+    wc_ed25519_free(&genKey);
+}
+#endif /* HAVE_ED25519 */
+
+
+#ifdef _WIN32
+
+    #define WIN32_LEAN_AND_MEAN
+    #include 
+
+    double current_time(int reset)
+    {
+        static int init = 0;
+        static LARGE_INTEGER freq;
+    
+        LARGE_INTEGER count;
+
+        (void)reset;
+
+        if (!init) {
+            QueryPerformanceFrequency(&freq);
+            init = 1;
+        }
+
+        QueryPerformanceCounter(&count);
+
+        return (double)count.QuadPart / freq.QuadPart;
+    }
+
+#elif defined MICROCHIP_PIC32
+    #if defined(WOLFSSL_MICROCHIP_PIC32MZ)
+        #define CLOCK 80000000.0
+    #else
+        #include 
+        #define CLOCK 40000000.0
+    #endif
+
+    double current_time(int reset)
+    {
+        unsigned int ns;
+
+        if (reset) {
+            WriteCoreTimer(0);
+        }
+
+        /* get timer in ns */
+        ns = ReadCoreTimer();
+
+        /* return seconds as a double */
+        return ( ns / CLOCK * 2.0);
+    }
+
+#elif defined(WOLFSSL_IAR_ARM_TIME) || defined (WOLFSSL_MDK_ARM) || defined(WOLFSSL_USER_CURRTIME)
+    extern   double current_time(int reset);
+    
+#elif defined FREERTOS
+
+    double current_time(int reset)
+    {
+        portTickType tickCount;
+
+        (void) reset;
+
+        /* tick count == ms, if configTICK_RATE_HZ is set to 1000 */
+        tickCount = xTaskGetTickCount();
+        return (double)tickCount / 1000;
+    }
+
+#elif defined (WOLFSSL_TIRTOS)
+
+    extern double current_time(int reset);
+
+#elif defined(FREESCALE_MQX)
+
+    double current_time(int reset)
+    {
+        TIME_STRUCT tv;
+        _time_get(&tv);
+
+        return (double)tv.SECONDS + (double)tv.MILLISECONDS / 1000;
+    }
+
+#else
+
+    #include 
+
+    double current_time(int reset)
+    {
+        struct timeval tv;
+
+        (void)reset;
+
+        gettimeofday(&tv, 0);
+
+        return (double)tv.tv_sec + (double)tv.tv_usec / 1000000;
+    }
+
+#endif /* _WIN32 */
+
+#ifdef HAVE_GET_CYCLES
+
+static INLINE word64 get_intel_cycles(void)
+{
+    unsigned int lo_c, hi_c;
+    __asm__ __volatile__ (
+        "cpuid\n\t"
+        "rdtsc"
+            : "=a"(lo_c), "=d"(hi_c)   /* out */
+            : "a"(0)                   /* in */
+            : "%ebx", "%ecx");         /* clobber */
+    return ((word64)lo_c) | (((word64)hi_c) << 32);
+}
+
+#endif /* HAVE_GET_CYCLES */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/benchmark/benchmark.sln b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/benchmark/benchmark.sln
new file mode 100644
index 0000000..e3e9483
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/benchmark/benchmark.sln
@@ -0,0 +1,20 @@
+
+Microsoft Visual Studio Solution File, Format Version 9.00
+# Visual C++ Express 2005
+Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "benchmark", "benchmark.vcproj", "{615AEC46-5595-4DEA-9490-DBD5DE0F8772}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|Win32 = Debug|Win32
+		Release|Win32 = Release|Win32
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{615AEC46-5595-4DEA-9490-DBD5DE0F8772}.Debug|Win32.ActiveCfg = Debug|Win32
+		{615AEC46-5595-4DEA-9490-DBD5DE0F8772}.Debug|Win32.Build.0 = Debug|Win32
+		{615AEC46-5595-4DEA-9490-DBD5DE0F8772}.Release|Win32.ActiveCfg = Release|Win32
+		{615AEC46-5595-4DEA-9490-DBD5DE0F8772}.Release|Win32.Build.0 = Release|Win32
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/benchmark/benchmark.vcproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/benchmark/benchmark.vcproj
new file mode 100644
index 0000000..5db23c3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/benchmark/benchmark.vcproj
@@ -0,0 +1,195 @@
+
+
+	
+		
+	
+	
+	
+	
+		
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+		
+		
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+		
+	
+	
+	
+	
+		
+		
+		
+		
+		
+			
+			
+		
+	
+	
+	
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/benchmark/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/benchmark/include.am
new file mode 100644
index 0000000..db70ba7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/benchmark/include.am
@@ -0,0 +1,10 @@
+# vim:ft=automake
+# All paths should be given relative to the root
+
+noinst_PROGRAMS += wolfcrypt/benchmark/benchmark
+wolfcrypt_benchmark_benchmark_SOURCES      = wolfcrypt/benchmark/benchmark.c
+wolfcrypt_benchmark_benchmark_LDADD        = src/libwolfssl.la
+wolfcrypt_benchmark_benchmark_DEPENDENCIES = src/libwolfssl.la
+EXTRA_DIST += wolfcrypt/benchmark/benchmark.sln 
+EXTRA_DIST += wolfcrypt/benchmark/benchmark.vcproj
+DISTCLEANFILES+= wolfcrypt/benchmark/.libs/benchmark
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/aes.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/aes.c
new file mode 100644
index 0000000..85f01a0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/aes.c
@@ -0,0 +1,3897 @@
+/* aes.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifndef NO_AES
+
+#include 
+
+#ifdef HAVE_FIPS
+int wc_AesSetKey(Aes* aes, const byte* key, word32 len, const byte* iv,
+                          int dir)
+{
+    return AesSetKey_fips(aes, key, len, iv, dir);
+}
+
+
+int wc_AesSetIV(Aes* aes, const byte* iv)
+{
+    return AesSetIV_fips(aes, iv);
+}
+
+
+int wc_AesCbcEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
+{
+    return AesCbcEncrypt_fips(aes, out, in, sz);
+}
+
+
+int wc_AesCbcDecrypt(Aes* aes, byte* out, const byte* in, word32 sz)
+{
+    return AesCbcDecrypt_fips(aes, out, in, sz);
+}
+
+
+int wc_AesCbcDecryptWithKey(byte* out, const byte* in, word32 inSz,
+                                 const byte* key, word32 keySz, const byte* iv)
+{
+    return AesCbcDecryptWithKey(out, in, inSz, key, keySz, iv);
+}
+
+
+/* AES-CTR */
+#ifdef WOLFSSL_AES_COUNTER
+void wc_AesCtrEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
+{
+    AesCtrEncrypt(aes, out, in, sz);
+}
+#endif
+
+/* AES-DIRECT */
+#if defined(WOLFSSL_AES_DIRECT)
+void wc_AesEncryptDirect(Aes* aes, byte* out, const byte* in)
+{
+    AesEncryptDirect(aes, out, in);
+}
+
+
+void wc_AesDecryptDirect(Aes* aes, byte* out, const byte* in)
+{
+    AesDecryptDirect(aes, out, in);
+}
+
+
+int wc_AesSetKeyDirect(Aes* aes, const byte* key, word32 len,
+                                const byte* iv, int dir)
+{
+    return AesSetKeyDirect(aes, key, len, iv, dir);
+}
+#endif
+
+
+#ifdef HAVE_AESGCM
+int wc_AesGcmSetKey(Aes* aes, const byte* key, word32 len)
+{
+    return AesGcmSetKey_fips(aes, key, len);
+}
+
+
+int wc_AesGcmEncrypt(Aes* aes, byte* out, const byte* in, word32 sz,
+                              const byte* iv, word32 ivSz,
+                              byte* authTag, word32 authTagSz,
+                              const byte* authIn, word32 authInSz)
+{
+    return AesGcmEncrypt_fips(aes, out, in, sz, iv, ivSz, authTag, authTagSz,
+                              authIn, authInSz);
+}
+
+
+int wc_AesGcmDecrypt(Aes* aes, byte* out, const byte* in, word32 sz,
+                              const byte* iv, word32 ivSz,
+                              const byte* authTag, word32 authTagSz,
+                              const byte* authIn, word32 authInSz)
+{
+    return AesGcmDecrypt_fips(aes, out, in, sz, iv, ivSz, authTag, authTagSz,
+                              authIn, authInSz);
+}
+
+
+int wc_GmacSetKey(Gmac* gmac, const byte* key, word32 len)
+{
+    return GmacSetKey(gmac, key, len);
+}
+
+
+int wc_GmacUpdate(Gmac* gmac, const byte* iv, word32 ivSz,
+                              const byte* authIn, word32 authInSz,
+                              byte* authTag, word32 authTagSz)
+{
+    return GmacUpdate(gmac, iv, ivSz, authIn, authInSz,
+                      authTag, authTagSz);
+}
+
+#endif /* HAVE_AESGCM */
+#ifdef HAVE_AESCCM
+void wc_AesCcmSetKey(Aes* aes, const byte* key, word32 keySz)
+{
+    AesCcmSetKey(aes, key, keySz);
+}
+
+
+void wc_AesCcmEncrypt(Aes* aes, byte* out, const byte* in, word32 inSz,
+                              const byte* nonce, word32 nonceSz,
+                              byte* authTag, word32 authTagSz,
+                              const byte* authIn, word32 authInSz)
+{
+    AesCcmEncrypt(aes, out, in, inSz, nonce, nonceSz, authTag, authTagSz,
+                  authIn, authInSz);
+}
+
+
+int  wc_AesCcmDecrypt(Aes* aes, byte* out, const byte* in, word32 inSz,
+                              const byte* nonce, word32 nonceSz,
+                              const byte* authTag, word32 authTagSz,
+                              const byte* authIn, word32 authInSz)
+{
+    return AesCcmDecrypt(aes, out, in, inSz, nonce, nonceSz, authTag, authTagSz,
+                         authIn, authInSz);
+}
+#endif /* HAVE_AESCCM */
+
+#ifdef HAVE_CAVIUM
+int  wc_AesInitCavium(Aes* aes, int i)
+{
+    return AesInitCavium(aes, i);
+}
+
+
+void wc_AesFreeCavium(Aes* aes)
+{
+    AesFreeCavium(aes);
+}
+#endif
+#else /* HAVE_FIPS */
+
+#ifdef WOLFSSL_TI_CRYPT
+#include 
+#else
+
+#include 
+#include 
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+#ifdef DEBUG_AESNI
+    #include 
+#endif
+
+
+#ifdef _MSC_VER
+    /* 4127 warning constant while(1)  */
+    #pragma warning(disable: 4127)
+#endif
+
+
+#if defined(STM32F2_CRYPTO)
+     /* STM32F2 hardware AES support for CBC, CTR modes through the STM32F2
+      * Standard Peripheral Library. Documentation located in STM32F2xx
+      * Standard Peripheral Library document (See note in README).
+      * NOTE: no support for AES-GCM/CCM/Direct */
+    #include "stm32f2xx.h"
+    #include "stm32f2xx_cryp.h"
+#elif defined(HAVE_COLDFIRE_SEC)
+    /* Freescale Coldfire SEC support for CBC mode.
+     * NOTE: no support for AES-CTR/GCM/CCM/Direct */
+    #include 
+    #include "sec.h"
+    #include "mcf5475_sec.h"
+    #include "mcf5475_siu.h"
+#elif defined(FREESCALE_MMCAU)
+    /* Freescale mmCAU hardware AES support for Direct, CBC, CCM, GCM modes
+     * through the CAU/mmCAU library. Documentation located in
+     * ColdFire/ColdFire+ CAU and Kinetis mmCAU Software Library User
+     * Guide (See note in README).
+     * NOTE: no support for AES-CTR */
+    #include "cau_api.h"
+#elif defined(WOLFSSL_PIC32MZ_CRYPT)
+    /* NOTE: no support for AES-CCM/Direct */
+    #define DEBUG_WOLFSSL
+    #include "wolfssl/wolfcrypt/port/pic32/pic32mz-crypt.h"
+#elif defined(HAVE_CAVIUM)
+    #include 
+    #include "cavium_common.h"
+
+    /* still leave SW crypto available */
+    #define NEED_AES_TABLES
+
+    static int  wc_AesCaviumSetKey(Aes* aes, const byte* key, word32 length,
+                                const byte* iv);
+    static int  wc_AesCaviumCbcEncrypt(Aes* aes, byte* out, const byte* in,
+                                    word32 length);
+    static int  wc_AesCaviumCbcDecrypt(Aes* aes, byte* out, const byte* in,
+                                    word32 length);
+#else
+    /* using CTaoCrypt software AES implementation */
+    #define NEED_AES_TABLES
+#endif /* STM32F2_CRYPTO */
+
+
+#ifdef NEED_AES_TABLES
+
+static const word32 rcon[] = {
+    0x01000000, 0x02000000, 0x04000000, 0x08000000,
+    0x10000000, 0x20000000, 0x40000000, 0x80000000,
+    0x1B000000, 0x36000000,
+    /* for 128-bit blocks, Rijndael never uses more than 10 rcon values */
+};
+
+static const word32 Te[5][256] = {
+{
+    0xc66363a5U, 0xf87c7c84U, 0xee777799U, 0xf67b7b8dU,
+    0xfff2f20dU, 0xd66b6bbdU, 0xde6f6fb1U, 0x91c5c554U,
+    0x60303050U, 0x02010103U, 0xce6767a9U, 0x562b2b7dU,
+    0xe7fefe19U, 0xb5d7d762U, 0x4dababe6U, 0xec76769aU,
+    0x8fcaca45U, 0x1f82829dU, 0x89c9c940U, 0xfa7d7d87U,
+    0xeffafa15U, 0xb25959ebU, 0x8e4747c9U, 0xfbf0f00bU,
+    0x41adadecU, 0xb3d4d467U, 0x5fa2a2fdU, 0x45afafeaU,
+    0x239c9cbfU, 0x53a4a4f7U, 0xe4727296U, 0x9bc0c05bU,
+    0x75b7b7c2U, 0xe1fdfd1cU, 0x3d9393aeU, 0x4c26266aU,
+    0x6c36365aU, 0x7e3f3f41U, 0xf5f7f702U, 0x83cccc4fU,
+    0x6834345cU, 0x51a5a5f4U, 0xd1e5e534U, 0xf9f1f108U,
+    0xe2717193U, 0xabd8d873U, 0x62313153U, 0x2a15153fU,
+    0x0804040cU, 0x95c7c752U, 0x46232365U, 0x9dc3c35eU,
+    0x30181828U, 0x379696a1U, 0x0a05050fU, 0x2f9a9ab5U,
+    0x0e070709U, 0x24121236U, 0x1b80809bU, 0xdfe2e23dU,
+    0xcdebeb26U, 0x4e272769U, 0x7fb2b2cdU, 0xea75759fU,
+    0x1209091bU, 0x1d83839eU, 0x582c2c74U, 0x341a1a2eU,
+    0x361b1b2dU, 0xdc6e6eb2U, 0xb45a5aeeU, 0x5ba0a0fbU,
+    0xa45252f6U, 0x763b3b4dU, 0xb7d6d661U, 0x7db3b3ceU,
+    0x5229297bU, 0xdde3e33eU, 0x5e2f2f71U, 0x13848497U,
+    0xa65353f5U, 0xb9d1d168U, 0x00000000U, 0xc1eded2cU,
+    0x40202060U, 0xe3fcfc1fU, 0x79b1b1c8U, 0xb65b5bedU,
+    0xd46a6abeU, 0x8dcbcb46U, 0x67bebed9U, 0x7239394bU,
+    0x944a4adeU, 0x984c4cd4U, 0xb05858e8U, 0x85cfcf4aU,
+    0xbbd0d06bU, 0xc5efef2aU, 0x4faaaae5U, 0xedfbfb16U,
+    0x864343c5U, 0x9a4d4dd7U, 0x66333355U, 0x11858594U,
+    0x8a4545cfU, 0xe9f9f910U, 0x04020206U, 0xfe7f7f81U,
+    0xa05050f0U, 0x783c3c44U, 0x259f9fbaU, 0x4ba8a8e3U,
+    0xa25151f3U, 0x5da3a3feU, 0x804040c0U, 0x058f8f8aU,
+    0x3f9292adU, 0x219d9dbcU, 0x70383848U, 0xf1f5f504U,
+    0x63bcbcdfU, 0x77b6b6c1U, 0xafdada75U, 0x42212163U,
+    0x20101030U, 0xe5ffff1aU, 0xfdf3f30eU, 0xbfd2d26dU,
+    0x81cdcd4cU, 0x180c0c14U, 0x26131335U, 0xc3ecec2fU,
+    0xbe5f5fe1U, 0x359797a2U, 0x884444ccU, 0x2e171739U,
+    0x93c4c457U, 0x55a7a7f2U, 0xfc7e7e82U, 0x7a3d3d47U,
+    0xc86464acU, 0xba5d5de7U, 0x3219192bU, 0xe6737395U,
+    0xc06060a0U, 0x19818198U, 0x9e4f4fd1U, 0xa3dcdc7fU,
+    0x44222266U, 0x542a2a7eU, 0x3b9090abU, 0x0b888883U,
+    0x8c4646caU, 0xc7eeee29U, 0x6bb8b8d3U, 0x2814143cU,
+    0xa7dede79U, 0xbc5e5ee2U, 0x160b0b1dU, 0xaddbdb76U,
+    0xdbe0e03bU, 0x64323256U, 0x743a3a4eU, 0x140a0a1eU,
+    0x924949dbU, 0x0c06060aU, 0x4824246cU, 0xb85c5ce4U,
+    0x9fc2c25dU, 0xbdd3d36eU, 0x43acacefU, 0xc46262a6U,
+    0x399191a8U, 0x319595a4U, 0xd3e4e437U, 0xf279798bU,
+    0xd5e7e732U, 0x8bc8c843U, 0x6e373759U, 0xda6d6db7U,
+    0x018d8d8cU, 0xb1d5d564U, 0x9c4e4ed2U, 0x49a9a9e0U,
+    0xd86c6cb4U, 0xac5656faU, 0xf3f4f407U, 0xcfeaea25U,
+    0xca6565afU, 0xf47a7a8eU, 0x47aeaee9U, 0x10080818U,
+    0x6fbabad5U, 0xf0787888U, 0x4a25256fU, 0x5c2e2e72U,
+    0x381c1c24U, 0x57a6a6f1U, 0x73b4b4c7U, 0x97c6c651U,
+    0xcbe8e823U, 0xa1dddd7cU, 0xe874749cU, 0x3e1f1f21U,
+    0x964b4bddU, 0x61bdbddcU, 0x0d8b8b86U, 0x0f8a8a85U,
+    0xe0707090U, 0x7c3e3e42U, 0x71b5b5c4U, 0xcc6666aaU,
+    0x904848d8U, 0x06030305U, 0xf7f6f601U, 0x1c0e0e12U,
+    0xc26161a3U, 0x6a35355fU, 0xae5757f9U, 0x69b9b9d0U,
+    0x17868691U, 0x99c1c158U, 0x3a1d1d27U, 0x279e9eb9U,
+    0xd9e1e138U, 0xebf8f813U, 0x2b9898b3U, 0x22111133U,
+    0xd26969bbU, 0xa9d9d970U, 0x078e8e89U, 0x339494a7U,
+    0x2d9b9bb6U, 0x3c1e1e22U, 0x15878792U, 0xc9e9e920U,
+    0x87cece49U, 0xaa5555ffU, 0x50282878U, 0xa5dfdf7aU,
+    0x038c8c8fU, 0x59a1a1f8U, 0x09898980U, 0x1a0d0d17U,
+    0x65bfbfdaU, 0xd7e6e631U, 0x844242c6U, 0xd06868b8U,
+    0x824141c3U, 0x299999b0U, 0x5a2d2d77U, 0x1e0f0f11U,
+    0x7bb0b0cbU, 0xa85454fcU, 0x6dbbbbd6U, 0x2c16163aU,
+},
+{
+    0xa5c66363U, 0x84f87c7cU, 0x99ee7777U, 0x8df67b7bU,
+    0x0dfff2f2U, 0xbdd66b6bU, 0xb1de6f6fU, 0x5491c5c5U,
+    0x50603030U, 0x03020101U, 0xa9ce6767U, 0x7d562b2bU,
+    0x19e7fefeU, 0x62b5d7d7U, 0xe64dababU, 0x9aec7676U,
+    0x458fcacaU, 0x9d1f8282U, 0x4089c9c9U, 0x87fa7d7dU,
+    0x15effafaU, 0xebb25959U, 0xc98e4747U, 0x0bfbf0f0U,
+    0xec41adadU, 0x67b3d4d4U, 0xfd5fa2a2U, 0xea45afafU,
+    0xbf239c9cU, 0xf753a4a4U, 0x96e47272U, 0x5b9bc0c0U,
+    0xc275b7b7U, 0x1ce1fdfdU, 0xae3d9393U, 0x6a4c2626U,
+    0x5a6c3636U, 0x417e3f3fU, 0x02f5f7f7U, 0x4f83ccccU,
+    0x5c683434U, 0xf451a5a5U, 0x34d1e5e5U, 0x08f9f1f1U,
+    0x93e27171U, 0x73abd8d8U, 0x53623131U, 0x3f2a1515U,
+    0x0c080404U, 0x5295c7c7U, 0x65462323U, 0x5e9dc3c3U,
+    0x28301818U, 0xa1379696U, 0x0f0a0505U, 0xb52f9a9aU,
+    0x090e0707U, 0x36241212U, 0x9b1b8080U, 0x3ddfe2e2U,
+    0x26cdebebU, 0x694e2727U, 0xcd7fb2b2U, 0x9fea7575U,
+    0x1b120909U, 0x9e1d8383U, 0x74582c2cU, 0x2e341a1aU,
+    0x2d361b1bU, 0xb2dc6e6eU, 0xeeb45a5aU, 0xfb5ba0a0U,
+    0xf6a45252U, 0x4d763b3bU, 0x61b7d6d6U, 0xce7db3b3U,
+    0x7b522929U, 0x3edde3e3U, 0x715e2f2fU, 0x97138484U,
+    0xf5a65353U, 0x68b9d1d1U, 0x00000000U, 0x2cc1ededU,
+    0x60402020U, 0x1fe3fcfcU, 0xc879b1b1U, 0xedb65b5bU,
+    0xbed46a6aU, 0x468dcbcbU, 0xd967bebeU, 0x4b723939U,
+    0xde944a4aU, 0xd4984c4cU, 0xe8b05858U, 0x4a85cfcfU,
+    0x6bbbd0d0U, 0x2ac5efefU, 0xe54faaaaU, 0x16edfbfbU,
+    0xc5864343U, 0xd79a4d4dU, 0x55663333U, 0x94118585U,
+    0xcf8a4545U, 0x10e9f9f9U, 0x06040202U, 0x81fe7f7fU,
+    0xf0a05050U, 0x44783c3cU, 0xba259f9fU, 0xe34ba8a8U,
+    0xf3a25151U, 0xfe5da3a3U, 0xc0804040U, 0x8a058f8fU,
+    0xad3f9292U, 0xbc219d9dU, 0x48703838U, 0x04f1f5f5U,
+    0xdf63bcbcU, 0xc177b6b6U, 0x75afdadaU, 0x63422121U,
+    0x30201010U, 0x1ae5ffffU, 0x0efdf3f3U, 0x6dbfd2d2U,
+    0x4c81cdcdU, 0x14180c0cU, 0x35261313U, 0x2fc3ececU,
+    0xe1be5f5fU, 0xa2359797U, 0xcc884444U, 0x392e1717U,
+    0x5793c4c4U, 0xf255a7a7U, 0x82fc7e7eU, 0x477a3d3dU,
+    0xacc86464U, 0xe7ba5d5dU, 0x2b321919U, 0x95e67373U,
+    0xa0c06060U, 0x98198181U, 0xd19e4f4fU, 0x7fa3dcdcU,
+    0x66442222U, 0x7e542a2aU, 0xab3b9090U, 0x830b8888U,
+    0xca8c4646U, 0x29c7eeeeU, 0xd36bb8b8U, 0x3c281414U,
+    0x79a7dedeU, 0xe2bc5e5eU, 0x1d160b0bU, 0x76addbdbU,
+    0x3bdbe0e0U, 0x56643232U, 0x4e743a3aU, 0x1e140a0aU,
+    0xdb924949U, 0x0a0c0606U, 0x6c482424U, 0xe4b85c5cU,
+    0x5d9fc2c2U, 0x6ebdd3d3U, 0xef43acacU, 0xa6c46262U,
+    0xa8399191U, 0xa4319595U, 0x37d3e4e4U, 0x8bf27979U,
+    0x32d5e7e7U, 0x438bc8c8U, 0x596e3737U, 0xb7da6d6dU,
+    0x8c018d8dU, 0x64b1d5d5U, 0xd29c4e4eU, 0xe049a9a9U,
+    0xb4d86c6cU, 0xfaac5656U, 0x07f3f4f4U, 0x25cfeaeaU,
+    0xafca6565U, 0x8ef47a7aU, 0xe947aeaeU, 0x18100808U,
+    0xd56fbabaU, 0x88f07878U, 0x6f4a2525U, 0x725c2e2eU,
+    0x24381c1cU, 0xf157a6a6U, 0xc773b4b4U, 0x5197c6c6U,
+    0x23cbe8e8U, 0x7ca1ddddU, 0x9ce87474U, 0x213e1f1fU,
+    0xdd964b4bU, 0xdc61bdbdU, 0x860d8b8bU, 0x850f8a8aU,
+    0x90e07070U, 0x427c3e3eU, 0xc471b5b5U, 0xaacc6666U,
+    0xd8904848U, 0x05060303U, 0x01f7f6f6U, 0x121c0e0eU,
+    0xa3c26161U, 0x5f6a3535U, 0xf9ae5757U, 0xd069b9b9U,
+    0x91178686U, 0x5899c1c1U, 0x273a1d1dU, 0xb9279e9eU,
+    0x38d9e1e1U, 0x13ebf8f8U, 0xb32b9898U, 0x33221111U,
+    0xbbd26969U, 0x70a9d9d9U, 0x89078e8eU, 0xa7339494U,
+    0xb62d9b9bU, 0x223c1e1eU, 0x92158787U, 0x20c9e9e9U,
+    0x4987ceceU, 0xffaa5555U, 0x78502828U, 0x7aa5dfdfU,
+    0x8f038c8cU, 0xf859a1a1U, 0x80098989U, 0x171a0d0dU,
+    0xda65bfbfU, 0x31d7e6e6U, 0xc6844242U, 0xb8d06868U,
+    0xc3824141U, 0xb0299999U, 0x775a2d2dU, 0x111e0f0fU,
+    0xcb7bb0b0U, 0xfca85454U, 0xd66dbbbbU, 0x3a2c1616U,
+},
+{
+    0x63a5c663U, 0x7c84f87cU, 0x7799ee77U, 0x7b8df67bU,
+    0xf20dfff2U, 0x6bbdd66bU, 0x6fb1de6fU, 0xc55491c5U,
+    0x30506030U, 0x01030201U, 0x67a9ce67U, 0x2b7d562bU,
+    0xfe19e7feU, 0xd762b5d7U, 0xabe64dabU, 0x769aec76U,
+    0xca458fcaU, 0x829d1f82U, 0xc94089c9U, 0x7d87fa7dU,
+    0xfa15effaU, 0x59ebb259U, 0x47c98e47U, 0xf00bfbf0U,
+    0xadec41adU, 0xd467b3d4U, 0xa2fd5fa2U, 0xafea45afU,
+    0x9cbf239cU, 0xa4f753a4U, 0x7296e472U, 0xc05b9bc0U,
+    0xb7c275b7U, 0xfd1ce1fdU, 0x93ae3d93U, 0x266a4c26U,
+    0x365a6c36U, 0x3f417e3fU, 0xf702f5f7U, 0xcc4f83ccU,
+    0x345c6834U, 0xa5f451a5U, 0xe534d1e5U, 0xf108f9f1U,
+    0x7193e271U, 0xd873abd8U, 0x31536231U, 0x153f2a15U,
+    0x040c0804U, 0xc75295c7U, 0x23654623U, 0xc35e9dc3U,
+    0x18283018U, 0x96a13796U, 0x050f0a05U, 0x9ab52f9aU,
+    0x07090e07U, 0x12362412U, 0x809b1b80U, 0xe23ddfe2U,
+    0xeb26cdebU, 0x27694e27U, 0xb2cd7fb2U, 0x759fea75U,
+    0x091b1209U, 0x839e1d83U, 0x2c74582cU, 0x1a2e341aU,
+    0x1b2d361bU, 0x6eb2dc6eU, 0x5aeeb45aU, 0xa0fb5ba0U,
+    0x52f6a452U, 0x3b4d763bU, 0xd661b7d6U, 0xb3ce7db3U,
+    0x297b5229U, 0xe33edde3U, 0x2f715e2fU, 0x84971384U,
+    0x53f5a653U, 0xd168b9d1U, 0x00000000U, 0xed2cc1edU,
+    0x20604020U, 0xfc1fe3fcU, 0xb1c879b1U, 0x5bedb65bU,
+    0x6abed46aU, 0xcb468dcbU, 0xbed967beU, 0x394b7239U,
+    0x4ade944aU, 0x4cd4984cU, 0x58e8b058U, 0xcf4a85cfU,
+    0xd06bbbd0U, 0xef2ac5efU, 0xaae54faaU, 0xfb16edfbU,
+    0x43c58643U, 0x4dd79a4dU, 0x33556633U, 0x85941185U,
+    0x45cf8a45U, 0xf910e9f9U, 0x02060402U, 0x7f81fe7fU,
+    0x50f0a050U, 0x3c44783cU, 0x9fba259fU, 0xa8e34ba8U,
+    0x51f3a251U, 0xa3fe5da3U, 0x40c08040U, 0x8f8a058fU,
+    0x92ad3f92U, 0x9dbc219dU, 0x38487038U, 0xf504f1f5U,
+    0xbcdf63bcU, 0xb6c177b6U, 0xda75afdaU, 0x21634221U,
+    0x10302010U, 0xff1ae5ffU, 0xf30efdf3U, 0xd26dbfd2U,
+    0xcd4c81cdU, 0x0c14180cU, 0x13352613U, 0xec2fc3ecU,
+    0x5fe1be5fU, 0x97a23597U, 0x44cc8844U, 0x17392e17U,
+    0xc45793c4U, 0xa7f255a7U, 0x7e82fc7eU, 0x3d477a3dU,
+    0x64acc864U, 0x5de7ba5dU, 0x192b3219U, 0x7395e673U,
+    0x60a0c060U, 0x81981981U, 0x4fd19e4fU, 0xdc7fa3dcU,
+    0x22664422U, 0x2a7e542aU, 0x90ab3b90U, 0x88830b88U,
+    0x46ca8c46U, 0xee29c7eeU, 0xb8d36bb8U, 0x143c2814U,
+    0xde79a7deU, 0x5ee2bc5eU, 0x0b1d160bU, 0xdb76addbU,
+    0xe03bdbe0U, 0x32566432U, 0x3a4e743aU, 0x0a1e140aU,
+    0x49db9249U, 0x060a0c06U, 0x246c4824U, 0x5ce4b85cU,
+    0xc25d9fc2U, 0xd36ebdd3U, 0xacef43acU, 0x62a6c462U,
+    0x91a83991U, 0x95a43195U, 0xe437d3e4U, 0x798bf279U,
+    0xe732d5e7U, 0xc8438bc8U, 0x37596e37U, 0x6db7da6dU,
+    0x8d8c018dU, 0xd564b1d5U, 0x4ed29c4eU, 0xa9e049a9U,
+    0x6cb4d86cU, 0x56faac56U, 0xf407f3f4U, 0xea25cfeaU,
+    0x65afca65U, 0x7a8ef47aU, 0xaee947aeU, 0x08181008U,
+    0xbad56fbaU, 0x7888f078U, 0x256f4a25U, 0x2e725c2eU,
+    0x1c24381cU, 0xa6f157a6U, 0xb4c773b4U, 0xc65197c6U,
+    0xe823cbe8U, 0xdd7ca1ddU, 0x749ce874U, 0x1f213e1fU,
+    0x4bdd964bU, 0xbddc61bdU, 0x8b860d8bU, 0x8a850f8aU,
+    0x7090e070U, 0x3e427c3eU, 0xb5c471b5U, 0x66aacc66U,
+    0x48d89048U, 0x03050603U, 0xf601f7f6U, 0x0e121c0eU,
+    0x61a3c261U, 0x355f6a35U, 0x57f9ae57U, 0xb9d069b9U,
+    0x86911786U, 0xc15899c1U, 0x1d273a1dU, 0x9eb9279eU,
+    0xe138d9e1U, 0xf813ebf8U, 0x98b32b98U, 0x11332211U,
+    0x69bbd269U, 0xd970a9d9U, 0x8e89078eU, 0x94a73394U,
+    0x9bb62d9bU, 0x1e223c1eU, 0x87921587U, 0xe920c9e9U,
+    0xce4987ceU, 0x55ffaa55U, 0x28785028U, 0xdf7aa5dfU,
+    0x8c8f038cU, 0xa1f859a1U, 0x89800989U, 0x0d171a0dU,
+    0xbfda65bfU, 0xe631d7e6U, 0x42c68442U, 0x68b8d068U,
+    0x41c38241U, 0x99b02999U, 0x2d775a2dU, 0x0f111e0fU,
+    0xb0cb7bb0U, 0x54fca854U, 0xbbd66dbbU, 0x163a2c16U,
+},
+{
+    0x6363a5c6U, 0x7c7c84f8U, 0x777799eeU, 0x7b7b8df6U,
+    0xf2f20dffU, 0x6b6bbdd6U, 0x6f6fb1deU, 0xc5c55491U,
+    0x30305060U, 0x01010302U, 0x6767a9ceU, 0x2b2b7d56U,
+    0xfefe19e7U, 0xd7d762b5U, 0xababe64dU, 0x76769aecU,
+    0xcaca458fU, 0x82829d1fU, 0xc9c94089U, 0x7d7d87faU,
+    0xfafa15efU, 0x5959ebb2U, 0x4747c98eU, 0xf0f00bfbU,
+    0xadadec41U, 0xd4d467b3U, 0xa2a2fd5fU, 0xafafea45U,
+    0x9c9cbf23U, 0xa4a4f753U, 0x727296e4U, 0xc0c05b9bU,
+    0xb7b7c275U, 0xfdfd1ce1U, 0x9393ae3dU, 0x26266a4cU,
+    0x36365a6cU, 0x3f3f417eU, 0xf7f702f5U, 0xcccc4f83U,
+    0x34345c68U, 0xa5a5f451U, 0xe5e534d1U, 0xf1f108f9U,
+    0x717193e2U, 0xd8d873abU, 0x31315362U, 0x15153f2aU,
+    0x04040c08U, 0xc7c75295U, 0x23236546U, 0xc3c35e9dU,
+    0x18182830U, 0x9696a137U, 0x05050f0aU, 0x9a9ab52fU,
+    0x0707090eU, 0x12123624U, 0x80809b1bU, 0xe2e23ddfU,
+    0xebeb26cdU, 0x2727694eU, 0xb2b2cd7fU, 0x75759feaU,
+    0x09091b12U, 0x83839e1dU, 0x2c2c7458U, 0x1a1a2e34U,
+    0x1b1b2d36U, 0x6e6eb2dcU, 0x5a5aeeb4U, 0xa0a0fb5bU,
+    0x5252f6a4U, 0x3b3b4d76U, 0xd6d661b7U, 0xb3b3ce7dU,
+    0x29297b52U, 0xe3e33eddU, 0x2f2f715eU, 0x84849713U,
+    0x5353f5a6U, 0xd1d168b9U, 0x00000000U, 0xeded2cc1U,
+    0x20206040U, 0xfcfc1fe3U, 0xb1b1c879U, 0x5b5bedb6U,
+    0x6a6abed4U, 0xcbcb468dU, 0xbebed967U, 0x39394b72U,
+    0x4a4ade94U, 0x4c4cd498U, 0x5858e8b0U, 0xcfcf4a85U,
+    0xd0d06bbbU, 0xefef2ac5U, 0xaaaae54fU, 0xfbfb16edU,
+    0x4343c586U, 0x4d4dd79aU, 0x33335566U, 0x85859411U,
+    0x4545cf8aU, 0xf9f910e9U, 0x02020604U, 0x7f7f81feU,
+    0x5050f0a0U, 0x3c3c4478U, 0x9f9fba25U, 0xa8a8e34bU,
+    0x5151f3a2U, 0xa3a3fe5dU, 0x4040c080U, 0x8f8f8a05U,
+    0x9292ad3fU, 0x9d9dbc21U, 0x38384870U, 0xf5f504f1U,
+    0xbcbcdf63U, 0xb6b6c177U, 0xdada75afU, 0x21216342U,
+    0x10103020U, 0xffff1ae5U, 0xf3f30efdU, 0xd2d26dbfU,
+    0xcdcd4c81U, 0x0c0c1418U, 0x13133526U, 0xecec2fc3U,
+    0x5f5fe1beU, 0x9797a235U, 0x4444cc88U, 0x1717392eU,
+    0xc4c45793U, 0xa7a7f255U, 0x7e7e82fcU, 0x3d3d477aU,
+    0x6464acc8U, 0x5d5de7baU, 0x19192b32U, 0x737395e6U,
+    0x6060a0c0U, 0x81819819U, 0x4f4fd19eU, 0xdcdc7fa3U,
+    0x22226644U, 0x2a2a7e54U, 0x9090ab3bU, 0x8888830bU,
+    0x4646ca8cU, 0xeeee29c7U, 0xb8b8d36bU, 0x14143c28U,
+    0xdede79a7U, 0x5e5ee2bcU, 0x0b0b1d16U, 0xdbdb76adU,
+    0xe0e03bdbU, 0x32325664U, 0x3a3a4e74U, 0x0a0a1e14U,
+    0x4949db92U, 0x06060a0cU, 0x24246c48U, 0x5c5ce4b8U,
+    0xc2c25d9fU, 0xd3d36ebdU, 0xacacef43U, 0x6262a6c4U,
+    0x9191a839U, 0x9595a431U, 0xe4e437d3U, 0x79798bf2U,
+    0xe7e732d5U, 0xc8c8438bU, 0x3737596eU, 0x6d6db7daU,
+    0x8d8d8c01U, 0xd5d564b1U, 0x4e4ed29cU, 0xa9a9e049U,
+    0x6c6cb4d8U, 0x5656faacU, 0xf4f407f3U, 0xeaea25cfU,
+    0x6565afcaU, 0x7a7a8ef4U, 0xaeaee947U, 0x08081810U,
+    0xbabad56fU, 0x787888f0U, 0x25256f4aU, 0x2e2e725cU,
+    0x1c1c2438U, 0xa6a6f157U, 0xb4b4c773U, 0xc6c65197U,
+    0xe8e823cbU, 0xdddd7ca1U, 0x74749ce8U, 0x1f1f213eU,
+    0x4b4bdd96U, 0xbdbddc61U, 0x8b8b860dU, 0x8a8a850fU,
+    0x707090e0U, 0x3e3e427cU, 0xb5b5c471U, 0x6666aaccU,
+    0x4848d890U, 0x03030506U, 0xf6f601f7U, 0x0e0e121cU,
+    0x6161a3c2U, 0x35355f6aU, 0x5757f9aeU, 0xb9b9d069U,
+    0x86869117U, 0xc1c15899U, 0x1d1d273aU, 0x9e9eb927U,
+    0xe1e138d9U, 0xf8f813ebU, 0x9898b32bU, 0x11113322U,
+    0x6969bbd2U, 0xd9d970a9U, 0x8e8e8907U, 0x9494a733U,
+    0x9b9bb62dU, 0x1e1e223cU, 0x87879215U, 0xe9e920c9U,
+    0xcece4987U, 0x5555ffaaU, 0x28287850U, 0xdfdf7aa5U,
+    0x8c8c8f03U, 0xa1a1f859U, 0x89898009U, 0x0d0d171aU,
+    0xbfbfda65U, 0xe6e631d7U, 0x4242c684U, 0x6868b8d0U,
+    0x4141c382U, 0x9999b029U, 0x2d2d775aU, 0x0f0f111eU,
+    0xb0b0cb7bU, 0x5454fca8U, 0xbbbbd66dU, 0x16163a2cU,
+},
+{
+    0x63636363U, 0x7c7c7c7cU, 0x77777777U, 0x7b7b7b7bU,
+    0xf2f2f2f2U, 0x6b6b6b6bU, 0x6f6f6f6fU, 0xc5c5c5c5U,
+    0x30303030U, 0x01010101U, 0x67676767U, 0x2b2b2b2bU,
+    0xfefefefeU, 0xd7d7d7d7U, 0xababababU, 0x76767676U,
+    0xcacacacaU, 0x82828282U, 0xc9c9c9c9U, 0x7d7d7d7dU,
+    0xfafafafaU, 0x59595959U, 0x47474747U, 0xf0f0f0f0U,
+    0xadadadadU, 0xd4d4d4d4U, 0xa2a2a2a2U, 0xafafafafU,
+    0x9c9c9c9cU, 0xa4a4a4a4U, 0x72727272U, 0xc0c0c0c0U,
+    0xb7b7b7b7U, 0xfdfdfdfdU, 0x93939393U, 0x26262626U,
+    0x36363636U, 0x3f3f3f3fU, 0xf7f7f7f7U, 0xccccccccU,
+    0x34343434U, 0xa5a5a5a5U, 0xe5e5e5e5U, 0xf1f1f1f1U,
+    0x71717171U, 0xd8d8d8d8U, 0x31313131U, 0x15151515U,
+    0x04040404U, 0xc7c7c7c7U, 0x23232323U, 0xc3c3c3c3U,
+    0x18181818U, 0x96969696U, 0x05050505U, 0x9a9a9a9aU,
+    0x07070707U, 0x12121212U, 0x80808080U, 0xe2e2e2e2U,
+    0xebebebebU, 0x27272727U, 0xb2b2b2b2U, 0x75757575U,
+    0x09090909U, 0x83838383U, 0x2c2c2c2cU, 0x1a1a1a1aU,
+    0x1b1b1b1bU, 0x6e6e6e6eU, 0x5a5a5a5aU, 0xa0a0a0a0U,
+    0x52525252U, 0x3b3b3b3bU, 0xd6d6d6d6U, 0xb3b3b3b3U,
+    0x29292929U, 0xe3e3e3e3U, 0x2f2f2f2fU, 0x84848484U,
+    0x53535353U, 0xd1d1d1d1U, 0x00000000U, 0xededededU,
+    0x20202020U, 0xfcfcfcfcU, 0xb1b1b1b1U, 0x5b5b5b5bU,
+    0x6a6a6a6aU, 0xcbcbcbcbU, 0xbebebebeU, 0x39393939U,
+    0x4a4a4a4aU, 0x4c4c4c4cU, 0x58585858U, 0xcfcfcfcfU,
+    0xd0d0d0d0U, 0xefefefefU, 0xaaaaaaaaU, 0xfbfbfbfbU,
+    0x43434343U, 0x4d4d4d4dU, 0x33333333U, 0x85858585U,
+    0x45454545U, 0xf9f9f9f9U, 0x02020202U, 0x7f7f7f7fU,
+    0x50505050U, 0x3c3c3c3cU, 0x9f9f9f9fU, 0xa8a8a8a8U,
+    0x51515151U, 0xa3a3a3a3U, 0x40404040U, 0x8f8f8f8fU,
+    0x92929292U, 0x9d9d9d9dU, 0x38383838U, 0xf5f5f5f5U,
+    0xbcbcbcbcU, 0xb6b6b6b6U, 0xdadadadaU, 0x21212121U,
+    0x10101010U, 0xffffffffU, 0xf3f3f3f3U, 0xd2d2d2d2U,
+    0xcdcdcdcdU, 0x0c0c0c0cU, 0x13131313U, 0xececececU,
+    0x5f5f5f5fU, 0x97979797U, 0x44444444U, 0x17171717U,
+    0xc4c4c4c4U, 0xa7a7a7a7U, 0x7e7e7e7eU, 0x3d3d3d3dU,
+    0x64646464U, 0x5d5d5d5dU, 0x19191919U, 0x73737373U,
+    0x60606060U, 0x81818181U, 0x4f4f4f4fU, 0xdcdcdcdcU,
+    0x22222222U, 0x2a2a2a2aU, 0x90909090U, 0x88888888U,
+    0x46464646U, 0xeeeeeeeeU, 0xb8b8b8b8U, 0x14141414U,
+    0xdedededeU, 0x5e5e5e5eU, 0x0b0b0b0bU, 0xdbdbdbdbU,
+    0xe0e0e0e0U, 0x32323232U, 0x3a3a3a3aU, 0x0a0a0a0aU,
+    0x49494949U, 0x06060606U, 0x24242424U, 0x5c5c5c5cU,
+    0xc2c2c2c2U, 0xd3d3d3d3U, 0xacacacacU, 0x62626262U,
+    0x91919191U, 0x95959595U, 0xe4e4e4e4U, 0x79797979U,
+    0xe7e7e7e7U, 0xc8c8c8c8U, 0x37373737U, 0x6d6d6d6dU,
+    0x8d8d8d8dU, 0xd5d5d5d5U, 0x4e4e4e4eU, 0xa9a9a9a9U,
+    0x6c6c6c6cU, 0x56565656U, 0xf4f4f4f4U, 0xeaeaeaeaU,
+    0x65656565U, 0x7a7a7a7aU, 0xaeaeaeaeU, 0x08080808U,
+    0xbabababaU, 0x78787878U, 0x25252525U, 0x2e2e2e2eU,
+    0x1c1c1c1cU, 0xa6a6a6a6U, 0xb4b4b4b4U, 0xc6c6c6c6U,
+    0xe8e8e8e8U, 0xddddddddU, 0x74747474U, 0x1f1f1f1fU,
+    0x4b4b4b4bU, 0xbdbdbdbdU, 0x8b8b8b8bU, 0x8a8a8a8aU,
+    0x70707070U, 0x3e3e3e3eU, 0xb5b5b5b5U, 0x66666666U,
+    0x48484848U, 0x03030303U, 0xf6f6f6f6U, 0x0e0e0e0eU,
+    0x61616161U, 0x35353535U, 0x57575757U, 0xb9b9b9b9U,
+    0x86868686U, 0xc1c1c1c1U, 0x1d1d1d1dU, 0x9e9e9e9eU,
+    0xe1e1e1e1U, 0xf8f8f8f8U, 0x98989898U, 0x11111111U,
+    0x69696969U, 0xd9d9d9d9U, 0x8e8e8e8eU, 0x94949494U,
+    0x9b9b9b9bU, 0x1e1e1e1eU, 0x87878787U, 0xe9e9e9e9U,
+    0xcecececeU, 0x55555555U, 0x28282828U, 0xdfdfdfdfU,
+    0x8c8c8c8cU, 0xa1a1a1a1U, 0x89898989U, 0x0d0d0d0dU,
+    0xbfbfbfbfU, 0xe6e6e6e6U, 0x42424242U, 0x68686868U,
+    0x41414141U, 0x99999999U, 0x2d2d2d2dU, 0x0f0f0f0fU,
+    0xb0b0b0b0U, 0x54545454U, 0xbbbbbbbbU, 0x16161616U,
+}
+};
+
+static const word32 Td[5][256] = {
+{
+    0x51f4a750U, 0x7e416553U, 0x1a17a4c3U, 0x3a275e96U,
+    0x3bab6bcbU, 0x1f9d45f1U, 0xacfa58abU, 0x4be30393U,
+    0x2030fa55U, 0xad766df6U, 0x88cc7691U, 0xf5024c25U,
+    0x4fe5d7fcU, 0xc52acbd7U, 0x26354480U, 0xb562a38fU,
+    0xdeb15a49U, 0x25ba1b67U, 0x45ea0e98U, 0x5dfec0e1U,
+    0xc32f7502U, 0x814cf012U, 0x8d4697a3U, 0x6bd3f9c6U,
+    0x038f5fe7U, 0x15929c95U, 0xbf6d7aebU, 0x955259daU,
+    0xd4be832dU, 0x587421d3U, 0x49e06929U, 0x8ec9c844U,
+    0x75c2896aU, 0xf48e7978U, 0x99583e6bU, 0x27b971ddU,
+    0xbee14fb6U, 0xf088ad17U, 0xc920ac66U, 0x7dce3ab4U,
+    0x63df4a18U, 0xe51a3182U, 0x97513360U, 0x62537f45U,
+    0xb16477e0U, 0xbb6bae84U, 0xfe81a01cU, 0xf9082b94U,
+    0x70486858U, 0x8f45fd19U, 0x94de6c87U, 0x527bf8b7U,
+    0xab73d323U, 0x724b02e2U, 0xe31f8f57U, 0x6655ab2aU,
+    0xb2eb2807U, 0x2fb5c203U, 0x86c57b9aU, 0xd33708a5U,
+    0x302887f2U, 0x23bfa5b2U, 0x02036abaU, 0xed16825cU,
+    0x8acf1c2bU, 0xa779b492U, 0xf307f2f0U, 0x4e69e2a1U,
+    0x65daf4cdU, 0x0605bed5U, 0xd134621fU, 0xc4a6fe8aU,
+    0x342e539dU, 0xa2f355a0U, 0x058ae132U, 0xa4f6eb75U,
+    0x0b83ec39U, 0x4060efaaU, 0x5e719f06U, 0xbd6e1051U,
+    0x3e218af9U, 0x96dd063dU, 0xdd3e05aeU, 0x4de6bd46U,
+    0x91548db5U, 0x71c45d05U, 0x0406d46fU, 0x605015ffU,
+    0x1998fb24U, 0xd6bde997U, 0x894043ccU, 0x67d99e77U,
+    0xb0e842bdU, 0x07898b88U, 0xe7195b38U, 0x79c8eedbU,
+    0xa17c0a47U, 0x7c420fe9U, 0xf8841ec9U, 0x00000000U,
+    0x09808683U, 0x322bed48U, 0x1e1170acU, 0x6c5a724eU,
+    0xfd0efffbU, 0x0f853856U, 0x3daed51eU, 0x362d3927U,
+    0x0a0fd964U, 0x685ca621U, 0x9b5b54d1U, 0x24362e3aU,
+    0x0c0a67b1U, 0x9357e70fU, 0xb4ee96d2U, 0x1b9b919eU,
+    0x80c0c54fU, 0x61dc20a2U, 0x5a774b69U, 0x1c121a16U,
+    0xe293ba0aU, 0xc0a02ae5U, 0x3c22e043U, 0x121b171dU,
+    0x0e090d0bU, 0xf28bc7adU, 0x2db6a8b9U, 0x141ea9c8U,
+    0x57f11985U, 0xaf75074cU, 0xee99ddbbU, 0xa37f60fdU,
+    0xf701269fU, 0x5c72f5bcU, 0x44663bc5U, 0x5bfb7e34U,
+    0x8b432976U, 0xcb23c6dcU, 0xb6edfc68U, 0xb8e4f163U,
+    0xd731dccaU, 0x42638510U, 0x13972240U, 0x84c61120U,
+    0x854a247dU, 0xd2bb3df8U, 0xaef93211U, 0xc729a16dU,
+    0x1d9e2f4bU, 0xdcb230f3U, 0x0d8652ecU, 0x77c1e3d0U,
+    0x2bb3166cU, 0xa970b999U, 0x119448faU, 0x47e96422U,
+    0xa8fc8cc4U, 0xa0f03f1aU, 0x567d2cd8U, 0x223390efU,
+    0x87494ec7U, 0xd938d1c1U, 0x8ccaa2feU, 0x98d40b36U,
+    0xa6f581cfU, 0xa57ade28U, 0xdab78e26U, 0x3fadbfa4U,
+    0x2c3a9de4U, 0x5078920dU, 0x6a5fcc9bU, 0x547e4662U,
+    0xf68d13c2U, 0x90d8b8e8U, 0x2e39f75eU, 0x82c3aff5U,
+    0x9f5d80beU, 0x69d0937cU, 0x6fd52da9U, 0xcf2512b3U,
+    0xc8ac993bU, 0x10187da7U, 0xe89c636eU, 0xdb3bbb7bU,
+    0xcd267809U, 0x6e5918f4U, 0xec9ab701U, 0x834f9aa8U,
+    0xe6956e65U, 0xaaffe67eU, 0x21bccf08U, 0xef15e8e6U,
+    0xbae79bd9U, 0x4a6f36ceU, 0xea9f09d4U, 0x29b07cd6U,
+    0x31a4b2afU, 0x2a3f2331U, 0xc6a59430U, 0x35a266c0U,
+    0x744ebc37U, 0xfc82caa6U, 0xe090d0b0U, 0x33a7d815U,
+    0xf104984aU, 0x41ecdaf7U, 0x7fcd500eU, 0x1791f62fU,
+    0x764dd68dU, 0x43efb04dU, 0xccaa4d54U, 0xe49604dfU,
+    0x9ed1b5e3U, 0x4c6a881bU, 0xc12c1fb8U, 0x4665517fU,
+    0x9d5eea04U, 0x018c355dU, 0xfa877473U, 0xfb0b412eU,
+    0xb3671d5aU, 0x92dbd252U, 0xe9105633U, 0x6dd64713U,
+    0x9ad7618cU, 0x37a10c7aU, 0x59f8148eU, 0xeb133c89U,
+    0xcea927eeU, 0xb761c935U, 0xe11ce5edU, 0x7a47b13cU,
+    0x9cd2df59U, 0x55f2733fU, 0x1814ce79U, 0x73c737bfU,
+    0x53f7cdeaU, 0x5ffdaa5bU, 0xdf3d6f14U, 0x7844db86U,
+    0xcaaff381U, 0xb968c43eU, 0x3824342cU, 0xc2a3405fU,
+    0x161dc372U, 0xbce2250cU, 0x283c498bU, 0xff0d9541U,
+    0x39a80171U, 0x080cb3deU, 0xd8b4e49cU, 0x6456c190U,
+    0x7bcb8461U, 0xd532b670U, 0x486c5c74U, 0xd0b85742U,
+},
+{
+    0x5051f4a7U, 0x537e4165U, 0xc31a17a4U, 0x963a275eU,
+    0xcb3bab6bU, 0xf11f9d45U, 0xabacfa58U, 0x934be303U,
+    0x552030faU, 0xf6ad766dU, 0x9188cc76U, 0x25f5024cU,
+    0xfc4fe5d7U, 0xd7c52acbU, 0x80263544U, 0x8fb562a3U,
+    0x49deb15aU, 0x6725ba1bU, 0x9845ea0eU, 0xe15dfec0U,
+    0x02c32f75U, 0x12814cf0U, 0xa38d4697U, 0xc66bd3f9U,
+    0xe7038f5fU, 0x9515929cU, 0xebbf6d7aU, 0xda955259U,
+    0x2dd4be83U, 0xd3587421U, 0x2949e069U, 0x448ec9c8U,
+    0x6a75c289U, 0x78f48e79U, 0x6b99583eU, 0xdd27b971U,
+    0xb6bee14fU, 0x17f088adU, 0x66c920acU, 0xb47dce3aU,
+    0x1863df4aU, 0x82e51a31U, 0x60975133U, 0x4562537fU,
+    0xe0b16477U, 0x84bb6baeU, 0x1cfe81a0U, 0x94f9082bU,
+    0x58704868U, 0x198f45fdU, 0x8794de6cU, 0xb7527bf8U,
+    0x23ab73d3U, 0xe2724b02U, 0x57e31f8fU, 0x2a6655abU,
+    0x07b2eb28U, 0x032fb5c2U, 0x9a86c57bU, 0xa5d33708U,
+    0xf2302887U, 0xb223bfa5U, 0xba02036aU, 0x5ced1682U,
+    0x2b8acf1cU, 0x92a779b4U, 0xf0f307f2U, 0xa14e69e2U,
+    0xcd65daf4U, 0xd50605beU, 0x1fd13462U, 0x8ac4a6feU,
+    0x9d342e53U, 0xa0a2f355U, 0x32058ae1U, 0x75a4f6ebU,
+    0x390b83ecU, 0xaa4060efU, 0x065e719fU, 0x51bd6e10U,
+    0xf93e218aU, 0x3d96dd06U, 0xaedd3e05U, 0x464de6bdU,
+    0xb591548dU, 0x0571c45dU, 0x6f0406d4U, 0xff605015U,
+    0x241998fbU, 0x97d6bde9U, 0xcc894043U, 0x7767d99eU,
+    0xbdb0e842U, 0x8807898bU, 0x38e7195bU, 0xdb79c8eeU,
+    0x47a17c0aU, 0xe97c420fU, 0xc9f8841eU, 0x00000000U,
+    0x83098086U, 0x48322bedU, 0xac1e1170U, 0x4e6c5a72U,
+    0xfbfd0effU, 0x560f8538U, 0x1e3daed5U, 0x27362d39U,
+    0x640a0fd9U, 0x21685ca6U, 0xd19b5b54U, 0x3a24362eU,
+    0xb10c0a67U, 0x0f9357e7U, 0xd2b4ee96U, 0x9e1b9b91U,
+    0x4f80c0c5U, 0xa261dc20U, 0x695a774bU, 0x161c121aU,
+    0x0ae293baU, 0xe5c0a02aU, 0x433c22e0U, 0x1d121b17U,
+    0x0b0e090dU, 0xadf28bc7U, 0xb92db6a8U, 0xc8141ea9U,
+    0x8557f119U, 0x4caf7507U, 0xbbee99ddU, 0xfda37f60U,
+    0x9ff70126U, 0xbc5c72f5U, 0xc544663bU, 0x345bfb7eU,
+    0x768b4329U, 0xdccb23c6U, 0x68b6edfcU, 0x63b8e4f1U,
+    0xcad731dcU, 0x10426385U, 0x40139722U, 0x2084c611U,
+    0x7d854a24U, 0xf8d2bb3dU, 0x11aef932U, 0x6dc729a1U,
+    0x4b1d9e2fU, 0xf3dcb230U, 0xec0d8652U, 0xd077c1e3U,
+    0x6c2bb316U, 0x99a970b9U, 0xfa119448U, 0x2247e964U,
+    0xc4a8fc8cU, 0x1aa0f03fU, 0xd8567d2cU, 0xef223390U,
+    0xc787494eU, 0xc1d938d1U, 0xfe8ccaa2U, 0x3698d40bU,
+    0xcfa6f581U, 0x28a57adeU, 0x26dab78eU, 0xa43fadbfU,
+    0xe42c3a9dU, 0x0d507892U, 0x9b6a5fccU, 0x62547e46U,
+    0xc2f68d13U, 0xe890d8b8U, 0x5e2e39f7U, 0xf582c3afU,
+    0xbe9f5d80U, 0x7c69d093U, 0xa96fd52dU, 0xb3cf2512U,
+    0x3bc8ac99U, 0xa710187dU, 0x6ee89c63U, 0x7bdb3bbbU,
+    0x09cd2678U, 0xf46e5918U, 0x01ec9ab7U, 0xa8834f9aU,
+    0x65e6956eU, 0x7eaaffe6U, 0x0821bccfU, 0xe6ef15e8U,
+    0xd9bae79bU, 0xce4a6f36U, 0xd4ea9f09U, 0xd629b07cU,
+    0xaf31a4b2U, 0x312a3f23U, 0x30c6a594U, 0xc035a266U,
+    0x37744ebcU, 0xa6fc82caU, 0xb0e090d0U, 0x1533a7d8U,
+    0x4af10498U, 0xf741ecdaU, 0x0e7fcd50U, 0x2f1791f6U,
+    0x8d764dd6U, 0x4d43efb0U, 0x54ccaa4dU, 0xdfe49604U,
+    0xe39ed1b5U, 0x1b4c6a88U, 0xb8c12c1fU, 0x7f466551U,
+    0x049d5eeaU, 0x5d018c35U, 0x73fa8774U, 0x2efb0b41U,
+    0x5ab3671dU, 0x5292dbd2U, 0x33e91056U, 0x136dd647U,
+    0x8c9ad761U, 0x7a37a10cU, 0x8e59f814U, 0x89eb133cU,
+    0xeecea927U, 0x35b761c9U, 0xede11ce5U, 0x3c7a47b1U,
+    0x599cd2dfU, 0x3f55f273U, 0x791814ceU, 0xbf73c737U,
+    0xea53f7cdU, 0x5b5ffdaaU, 0x14df3d6fU, 0x867844dbU,
+    0x81caaff3U, 0x3eb968c4U, 0x2c382434U, 0x5fc2a340U,
+    0x72161dc3U, 0x0cbce225U, 0x8b283c49U, 0x41ff0d95U,
+    0x7139a801U, 0xde080cb3U, 0x9cd8b4e4U, 0x906456c1U,
+    0x617bcb84U, 0x70d532b6U, 0x74486c5cU, 0x42d0b857U,
+},
+{
+    0xa75051f4U, 0x65537e41U, 0xa4c31a17U, 0x5e963a27U,
+    0x6bcb3babU, 0x45f11f9dU, 0x58abacfaU, 0x03934be3U,
+    0xfa552030U, 0x6df6ad76U, 0x769188ccU, 0x4c25f502U,
+    0xd7fc4fe5U, 0xcbd7c52aU, 0x44802635U, 0xa38fb562U,
+    0x5a49deb1U, 0x1b6725baU, 0x0e9845eaU, 0xc0e15dfeU,
+    0x7502c32fU, 0xf012814cU, 0x97a38d46U, 0xf9c66bd3U,
+    0x5fe7038fU, 0x9c951592U, 0x7aebbf6dU, 0x59da9552U,
+    0x832dd4beU, 0x21d35874U, 0x692949e0U, 0xc8448ec9U,
+    0x896a75c2U, 0x7978f48eU, 0x3e6b9958U, 0x71dd27b9U,
+    0x4fb6bee1U, 0xad17f088U, 0xac66c920U, 0x3ab47dceU,
+    0x4a1863dfU, 0x3182e51aU, 0x33609751U, 0x7f456253U,
+    0x77e0b164U, 0xae84bb6bU, 0xa01cfe81U, 0x2b94f908U,
+    0x68587048U, 0xfd198f45U, 0x6c8794deU, 0xf8b7527bU,
+    0xd323ab73U, 0x02e2724bU, 0x8f57e31fU, 0xab2a6655U,
+    0x2807b2ebU, 0xc2032fb5U, 0x7b9a86c5U, 0x08a5d337U,
+    0x87f23028U, 0xa5b223bfU, 0x6aba0203U, 0x825ced16U,
+    0x1c2b8acfU, 0xb492a779U, 0xf2f0f307U, 0xe2a14e69U,
+    0xf4cd65daU, 0xbed50605U, 0x621fd134U, 0xfe8ac4a6U,
+    0x539d342eU, 0x55a0a2f3U, 0xe132058aU, 0xeb75a4f6U,
+    0xec390b83U, 0xefaa4060U, 0x9f065e71U, 0x1051bd6eU,
+
+    0x8af93e21U, 0x063d96ddU, 0x05aedd3eU, 0xbd464de6U,
+    0x8db59154U, 0x5d0571c4U, 0xd46f0406U, 0x15ff6050U,
+    0xfb241998U, 0xe997d6bdU, 0x43cc8940U, 0x9e7767d9U,
+    0x42bdb0e8U, 0x8b880789U, 0x5b38e719U, 0xeedb79c8U,
+    0x0a47a17cU, 0x0fe97c42U, 0x1ec9f884U, 0x00000000U,
+    0x86830980U, 0xed48322bU, 0x70ac1e11U, 0x724e6c5aU,
+    0xfffbfd0eU, 0x38560f85U, 0xd51e3daeU, 0x3927362dU,
+    0xd9640a0fU, 0xa621685cU, 0x54d19b5bU, 0x2e3a2436U,
+    0x67b10c0aU, 0xe70f9357U, 0x96d2b4eeU, 0x919e1b9bU,
+    0xc54f80c0U, 0x20a261dcU, 0x4b695a77U, 0x1a161c12U,
+    0xba0ae293U, 0x2ae5c0a0U, 0xe0433c22U, 0x171d121bU,
+    0x0d0b0e09U, 0xc7adf28bU, 0xa8b92db6U, 0xa9c8141eU,
+    0x198557f1U, 0x074caf75U, 0xddbbee99U, 0x60fda37fU,
+    0x269ff701U, 0xf5bc5c72U, 0x3bc54466U, 0x7e345bfbU,
+    0x29768b43U, 0xc6dccb23U, 0xfc68b6edU, 0xf163b8e4U,
+    0xdccad731U, 0x85104263U, 0x22401397U, 0x112084c6U,
+    0x247d854aU, 0x3df8d2bbU, 0x3211aef9U, 0xa16dc729U,
+    0x2f4b1d9eU, 0x30f3dcb2U, 0x52ec0d86U, 0xe3d077c1U,
+    0x166c2bb3U, 0xb999a970U, 0x48fa1194U, 0x642247e9U,
+    0x8cc4a8fcU, 0x3f1aa0f0U, 0x2cd8567dU, 0x90ef2233U,
+    0x4ec78749U, 0xd1c1d938U, 0xa2fe8ccaU, 0x0b3698d4U,
+    0x81cfa6f5U, 0xde28a57aU, 0x8e26dab7U, 0xbfa43fadU,
+    0x9de42c3aU, 0x920d5078U, 0xcc9b6a5fU, 0x4662547eU,
+    0x13c2f68dU, 0xb8e890d8U, 0xf75e2e39U, 0xaff582c3U,
+    0x80be9f5dU, 0x937c69d0U, 0x2da96fd5U, 0x12b3cf25U,
+    0x993bc8acU, 0x7da71018U, 0x636ee89cU, 0xbb7bdb3bU,
+    0x7809cd26U, 0x18f46e59U, 0xb701ec9aU, 0x9aa8834fU,
+    0x6e65e695U, 0xe67eaaffU, 0xcf0821bcU, 0xe8e6ef15U,
+    0x9bd9bae7U, 0x36ce4a6fU, 0x09d4ea9fU, 0x7cd629b0U,
+    0xb2af31a4U, 0x23312a3fU, 0x9430c6a5U, 0x66c035a2U,
+    0xbc37744eU, 0xcaa6fc82U, 0xd0b0e090U, 0xd81533a7U,
+    0x984af104U, 0xdaf741ecU, 0x500e7fcdU, 0xf62f1791U,
+    0xd68d764dU, 0xb04d43efU, 0x4d54ccaaU, 0x04dfe496U,
+    0xb5e39ed1U, 0x881b4c6aU, 0x1fb8c12cU, 0x517f4665U,
+    0xea049d5eU, 0x355d018cU, 0x7473fa87U, 0x412efb0bU,
+    0x1d5ab367U, 0xd25292dbU, 0x5633e910U, 0x47136dd6U,
+    0x618c9ad7U, 0x0c7a37a1U, 0x148e59f8U, 0x3c89eb13U,
+    0x27eecea9U, 0xc935b761U, 0xe5ede11cU, 0xb13c7a47U,
+    0xdf599cd2U, 0x733f55f2U, 0xce791814U, 0x37bf73c7U,
+    0xcdea53f7U, 0xaa5b5ffdU, 0x6f14df3dU, 0xdb867844U,
+    0xf381caafU, 0xc43eb968U, 0x342c3824U, 0x405fc2a3U,
+    0xc372161dU, 0x250cbce2U, 0x498b283cU, 0x9541ff0dU,
+    0x017139a8U, 0xb3de080cU, 0xe49cd8b4U, 0xc1906456U,
+    0x84617bcbU, 0xb670d532U, 0x5c74486cU, 0x5742d0b8U,
+},
+{
+    0xf4a75051U, 0x4165537eU, 0x17a4c31aU, 0x275e963aU,
+    0xab6bcb3bU, 0x9d45f11fU, 0xfa58abacU, 0xe303934bU,
+    0x30fa5520U, 0x766df6adU, 0xcc769188U, 0x024c25f5U,
+    0xe5d7fc4fU, 0x2acbd7c5U, 0x35448026U, 0x62a38fb5U,
+    0xb15a49deU, 0xba1b6725U, 0xea0e9845U, 0xfec0e15dU,
+    0x2f7502c3U, 0x4cf01281U, 0x4697a38dU, 0xd3f9c66bU,
+    0x8f5fe703U, 0x929c9515U, 0x6d7aebbfU, 0x5259da95U,
+    0xbe832dd4U, 0x7421d358U, 0xe0692949U, 0xc9c8448eU,
+    0xc2896a75U, 0x8e7978f4U, 0x583e6b99U, 0xb971dd27U,
+    0xe14fb6beU, 0x88ad17f0U, 0x20ac66c9U, 0xce3ab47dU,
+    0xdf4a1863U, 0x1a3182e5U, 0x51336097U, 0x537f4562U,
+    0x6477e0b1U, 0x6bae84bbU, 0x81a01cfeU, 0x082b94f9U,
+    0x48685870U, 0x45fd198fU, 0xde6c8794U, 0x7bf8b752U,
+    0x73d323abU, 0x4b02e272U, 0x1f8f57e3U, 0x55ab2a66U,
+    0xeb2807b2U, 0xb5c2032fU, 0xc57b9a86U, 0x3708a5d3U,
+    0x2887f230U, 0xbfa5b223U, 0x036aba02U, 0x16825cedU,
+    0xcf1c2b8aU, 0x79b492a7U, 0x07f2f0f3U, 0x69e2a14eU,
+    0xdaf4cd65U, 0x05bed506U, 0x34621fd1U, 0xa6fe8ac4U,
+    0x2e539d34U, 0xf355a0a2U, 0x8ae13205U, 0xf6eb75a4U,
+    0x83ec390bU, 0x60efaa40U, 0x719f065eU, 0x6e1051bdU,
+    0x218af93eU, 0xdd063d96U, 0x3e05aeddU, 0xe6bd464dU,
+    0x548db591U, 0xc45d0571U, 0x06d46f04U, 0x5015ff60U,
+    0x98fb2419U, 0xbde997d6U, 0x4043cc89U, 0xd99e7767U,
+    0xe842bdb0U, 0x898b8807U, 0x195b38e7U, 0xc8eedb79U,
+    0x7c0a47a1U, 0x420fe97cU, 0x841ec9f8U, 0x00000000U,
+    0x80868309U, 0x2bed4832U, 0x1170ac1eU, 0x5a724e6cU,
+    0x0efffbfdU, 0x8538560fU, 0xaed51e3dU, 0x2d392736U,
+    0x0fd9640aU, 0x5ca62168U, 0x5b54d19bU, 0x362e3a24U,
+    0x0a67b10cU, 0x57e70f93U, 0xee96d2b4U, 0x9b919e1bU,
+    0xc0c54f80U, 0xdc20a261U, 0x774b695aU, 0x121a161cU,
+    0x93ba0ae2U, 0xa02ae5c0U, 0x22e0433cU, 0x1b171d12U,
+    0x090d0b0eU, 0x8bc7adf2U, 0xb6a8b92dU, 0x1ea9c814U,
+    0xf1198557U, 0x75074cafU, 0x99ddbbeeU, 0x7f60fda3U,
+    0x01269ff7U, 0x72f5bc5cU, 0x663bc544U, 0xfb7e345bU,
+    0x4329768bU, 0x23c6dccbU, 0xedfc68b6U, 0xe4f163b8U,
+    0x31dccad7U, 0x63851042U, 0x97224013U, 0xc6112084U,
+    0x4a247d85U, 0xbb3df8d2U, 0xf93211aeU, 0x29a16dc7U,
+    0x9e2f4b1dU, 0xb230f3dcU, 0x8652ec0dU, 0xc1e3d077U,
+    0xb3166c2bU, 0x70b999a9U, 0x9448fa11U, 0xe9642247U,
+    0xfc8cc4a8U, 0xf03f1aa0U, 0x7d2cd856U, 0x3390ef22U,
+    0x494ec787U, 0x38d1c1d9U, 0xcaa2fe8cU, 0xd40b3698U,
+    0xf581cfa6U, 0x7ade28a5U, 0xb78e26daU, 0xadbfa43fU,
+    0x3a9de42cU, 0x78920d50U, 0x5fcc9b6aU, 0x7e466254U,
+    0x8d13c2f6U, 0xd8b8e890U, 0x39f75e2eU, 0xc3aff582U,
+    0x5d80be9fU, 0xd0937c69U, 0xd52da96fU, 0x2512b3cfU,
+    0xac993bc8U, 0x187da710U, 0x9c636ee8U, 0x3bbb7bdbU,
+    0x267809cdU, 0x5918f46eU, 0x9ab701ecU, 0x4f9aa883U,
+    0x956e65e6U, 0xffe67eaaU, 0xbccf0821U, 0x15e8e6efU,
+    0xe79bd9baU, 0x6f36ce4aU, 0x9f09d4eaU, 0xb07cd629U,
+    0xa4b2af31U, 0x3f23312aU, 0xa59430c6U, 0xa266c035U,
+    0x4ebc3774U, 0x82caa6fcU, 0x90d0b0e0U, 0xa7d81533U,
+    0x04984af1U, 0xecdaf741U, 0xcd500e7fU, 0x91f62f17U,
+    0x4dd68d76U, 0xefb04d43U, 0xaa4d54ccU, 0x9604dfe4U,
+    0xd1b5e39eU, 0x6a881b4cU, 0x2c1fb8c1U, 0x65517f46U,
+    0x5eea049dU, 0x8c355d01U, 0x877473faU, 0x0b412efbU,
+    0x671d5ab3U, 0xdbd25292U, 0x105633e9U, 0xd647136dU,
+    0xd7618c9aU, 0xa10c7a37U, 0xf8148e59U, 0x133c89ebU,
+    0xa927eeceU, 0x61c935b7U, 0x1ce5ede1U, 0x47b13c7aU,
+    0xd2df599cU, 0xf2733f55U, 0x14ce7918U, 0xc737bf73U,
+    0xf7cdea53U, 0xfdaa5b5fU, 0x3d6f14dfU, 0x44db8678U,
+    0xaff381caU, 0x68c43eb9U, 0x24342c38U, 0xa3405fc2U,
+    0x1dc37216U, 0xe2250cbcU, 0x3c498b28U, 0x0d9541ffU,
+    0xa8017139U, 0x0cb3de08U, 0xb4e49cd8U, 0x56c19064U,
+    0xcb84617bU, 0x32b670d5U, 0x6c5c7448U, 0xb85742d0U,
+},
+{
+    0x52525252U, 0x09090909U, 0x6a6a6a6aU, 0xd5d5d5d5U,
+    0x30303030U, 0x36363636U, 0xa5a5a5a5U, 0x38383838U,
+    0xbfbfbfbfU, 0x40404040U, 0xa3a3a3a3U, 0x9e9e9e9eU,
+    0x81818181U, 0xf3f3f3f3U, 0xd7d7d7d7U, 0xfbfbfbfbU,
+    0x7c7c7c7cU, 0xe3e3e3e3U, 0x39393939U, 0x82828282U,
+    0x9b9b9b9bU, 0x2f2f2f2fU, 0xffffffffU, 0x87878787U,
+    0x34343434U, 0x8e8e8e8eU, 0x43434343U, 0x44444444U,
+    0xc4c4c4c4U, 0xdedededeU, 0xe9e9e9e9U, 0xcbcbcbcbU,
+    0x54545454U, 0x7b7b7b7bU, 0x94949494U, 0x32323232U,
+    0xa6a6a6a6U, 0xc2c2c2c2U, 0x23232323U, 0x3d3d3d3dU,
+    0xeeeeeeeeU, 0x4c4c4c4cU, 0x95959595U, 0x0b0b0b0bU,
+    0x42424242U, 0xfafafafaU, 0xc3c3c3c3U, 0x4e4e4e4eU,
+    0x08080808U, 0x2e2e2e2eU, 0xa1a1a1a1U, 0x66666666U,
+    0x28282828U, 0xd9d9d9d9U, 0x24242424U, 0xb2b2b2b2U,
+    0x76767676U, 0x5b5b5b5bU, 0xa2a2a2a2U, 0x49494949U,
+    0x6d6d6d6dU, 0x8b8b8b8bU, 0xd1d1d1d1U, 0x25252525U,
+    0x72727272U, 0xf8f8f8f8U, 0xf6f6f6f6U, 0x64646464U,
+    0x86868686U, 0x68686868U, 0x98989898U, 0x16161616U,
+    0xd4d4d4d4U, 0xa4a4a4a4U, 0x5c5c5c5cU, 0xccccccccU,
+    0x5d5d5d5dU, 0x65656565U, 0xb6b6b6b6U, 0x92929292U,
+    0x6c6c6c6cU, 0x70707070U, 0x48484848U, 0x50505050U,
+    0xfdfdfdfdU, 0xededededU, 0xb9b9b9b9U, 0xdadadadaU,
+    0x5e5e5e5eU, 0x15151515U, 0x46464646U, 0x57575757U,
+    0xa7a7a7a7U, 0x8d8d8d8dU, 0x9d9d9d9dU, 0x84848484U,
+    0x90909090U, 0xd8d8d8d8U, 0xababababU, 0x00000000U,
+    0x8c8c8c8cU, 0xbcbcbcbcU, 0xd3d3d3d3U, 0x0a0a0a0aU,
+    0xf7f7f7f7U, 0xe4e4e4e4U, 0x58585858U, 0x05050505U,
+    0xb8b8b8b8U, 0xb3b3b3b3U, 0x45454545U, 0x06060606U,
+    0xd0d0d0d0U, 0x2c2c2c2cU, 0x1e1e1e1eU, 0x8f8f8f8fU,
+    0xcacacacaU, 0x3f3f3f3fU, 0x0f0f0f0fU, 0x02020202U,
+    0xc1c1c1c1U, 0xafafafafU, 0xbdbdbdbdU, 0x03030303U,
+    0x01010101U, 0x13131313U, 0x8a8a8a8aU, 0x6b6b6b6bU,
+    0x3a3a3a3aU, 0x91919191U, 0x11111111U, 0x41414141U,
+    0x4f4f4f4fU, 0x67676767U, 0xdcdcdcdcU, 0xeaeaeaeaU,
+    0x97979797U, 0xf2f2f2f2U, 0xcfcfcfcfU, 0xcecececeU,
+    0xf0f0f0f0U, 0xb4b4b4b4U, 0xe6e6e6e6U, 0x73737373U,
+    0x96969696U, 0xacacacacU, 0x74747474U, 0x22222222U,
+    0xe7e7e7e7U, 0xadadadadU, 0x35353535U, 0x85858585U,
+    0xe2e2e2e2U, 0xf9f9f9f9U, 0x37373737U, 0xe8e8e8e8U,
+    0x1c1c1c1cU, 0x75757575U, 0xdfdfdfdfU, 0x6e6e6e6eU,
+    0x47474747U, 0xf1f1f1f1U, 0x1a1a1a1aU, 0x71717171U,
+    0x1d1d1d1dU, 0x29292929U, 0xc5c5c5c5U, 0x89898989U,
+    0x6f6f6f6fU, 0xb7b7b7b7U, 0x62626262U, 0x0e0e0e0eU,
+    0xaaaaaaaaU, 0x18181818U, 0xbebebebeU, 0x1b1b1b1bU,
+    0xfcfcfcfcU, 0x56565656U, 0x3e3e3e3eU, 0x4b4b4b4bU,
+    0xc6c6c6c6U, 0xd2d2d2d2U, 0x79797979U, 0x20202020U,
+    0x9a9a9a9aU, 0xdbdbdbdbU, 0xc0c0c0c0U, 0xfefefefeU,
+    0x78787878U, 0xcdcdcdcdU, 0x5a5a5a5aU, 0xf4f4f4f4U,
+    0x1f1f1f1fU, 0xddddddddU, 0xa8a8a8a8U, 0x33333333U,
+    0x88888888U, 0x07070707U, 0xc7c7c7c7U, 0x31313131U,
+    0xb1b1b1b1U, 0x12121212U, 0x10101010U, 0x59595959U,
+    0x27272727U, 0x80808080U, 0xececececU, 0x5f5f5f5fU,
+    0x60606060U, 0x51515151U, 0x7f7f7f7fU, 0xa9a9a9a9U,
+    0x19191919U, 0xb5b5b5b5U, 0x4a4a4a4aU, 0x0d0d0d0dU,
+    0x2d2d2d2dU, 0xe5e5e5e5U, 0x7a7a7a7aU, 0x9f9f9f9fU,
+    0x93939393U, 0xc9c9c9c9U, 0x9c9c9c9cU, 0xefefefefU,
+    0xa0a0a0a0U, 0xe0e0e0e0U, 0x3b3b3b3bU, 0x4d4d4d4dU,
+    0xaeaeaeaeU, 0x2a2a2a2aU, 0xf5f5f5f5U, 0xb0b0b0b0U,
+    0xc8c8c8c8U, 0xebebebebU, 0xbbbbbbbbU, 0x3c3c3c3cU,
+    0x83838383U, 0x53535353U, 0x99999999U, 0x61616161U,
+    0x17171717U, 0x2b2b2b2bU, 0x04040404U, 0x7e7e7e7eU,
+    0xbabababaU, 0x77777777U, 0xd6d6d6d6U, 0x26262626U,
+    0xe1e1e1e1U, 0x69696969U, 0x14141414U, 0x63636363U,
+    0x55555555U, 0x21212121U, 0x0c0c0c0cU, 0x7d7d7d7dU,
+}
+};
+
+#define GETBYTE(x, y) (word32)((byte)((x) >> (8 * (y))))
+
+#ifdef WOLFSSL_AESNI
+
+/* Each platform needs to query info type 1 from cpuid to see if aesni is
+ * supported. Also, let's setup a macro for proper linkage w/o ABI conflicts
+ */
+
+#ifndef _MSC_VER
+
+    #define cpuid(reg, func)\
+        __asm__ __volatile__ ("cpuid":\
+             "=a" (reg[0]), "=b" (reg[1]), "=c" (reg[2]), "=d" (reg[3]) :\
+             "a" (func));
+
+    #define XASM_LINK(f) asm(f)
+#else
+
+    #include 
+    #define cpuid(a,b) __cpuid((int*)a,b)
+
+    #define XASM_LINK(f)
+
+#endif /* _MSC_VER */
+
+
+static int Check_CPU_support_AES(void)
+{
+    unsigned int reg[4];  /* put a,b,c,d into 0,1,2,3 */
+    cpuid(reg, 1);        /* query info 1 */
+
+    if (reg[2] & 0x2000000)
+        return 1;
+
+    return 0;
+}
+
+static int checkAESNI = 0;
+static int haveAESNI  = 0;
+
+
+/* tell C compiler these are asm functions in case any mix up of ABI underscore
+   prefix between clang/gcc/llvm etc */
+void AES_CBC_encrypt(const unsigned char* in, unsigned char* out,
+                     unsigned char* ivec, unsigned long length,
+                     const unsigned char* KS, int nr)
+                     XASM_LINK("AES_CBC_encrypt");
+
+
+void AES_CBC_decrypt(const unsigned char* in, unsigned char* out,
+                     unsigned char* ivec, unsigned long length,
+                     const unsigned char* KS, int nr)
+                     XASM_LINK("AES_CBC_decrypt");
+
+void AES_ECB_encrypt(const unsigned char* in, unsigned char* out,
+                     unsigned long length, const unsigned char* KS, int nr)
+                     XASM_LINK("AES_ECB_encrypt");
+
+
+void AES_ECB_decrypt(const unsigned char* in, unsigned char* out,
+                     unsigned long length, const unsigned char* KS, int nr)
+                     XASM_LINK("AES_ECB_decrypt");
+
+void AES_128_Key_Expansion(const unsigned char* userkey,
+                           unsigned char* key_schedule)
+                           XASM_LINK("AES_128_Key_Expansion");
+
+void AES_192_Key_Expansion(const unsigned char* userkey,
+                           unsigned char* key_schedule)
+                           XASM_LINK("AES_192_Key_Expansion");
+
+void AES_256_Key_Expansion(const unsigned char* userkey,
+                           unsigned char* key_schedule)
+                           XASM_LINK("AES_256_Key_Expansion");
+
+
+static int AES_set_encrypt_key(const unsigned char *userKey, const int bits,
+                               Aes* aes)
+{
+    if (!userKey || !aes)
+        return BAD_FUNC_ARG;
+
+    if (bits == 128) {
+       AES_128_Key_Expansion (userKey,(byte*)aes->key); aes->rounds = 10;
+       return 0;
+    }
+    else if (bits == 192) {
+       AES_192_Key_Expansion (userKey,(byte*)aes->key); aes->rounds = 12;
+       return 0;
+    }
+    else if (bits == 256) {
+       AES_256_Key_Expansion (userKey,(byte*)aes->key); aes->rounds = 14;
+       return 0;
+    }
+    return BAD_FUNC_ARG;
+}
+
+
+static int AES_set_decrypt_key(const unsigned char* userKey, const int bits,
+                               Aes* aes)
+{
+    int nr;
+    Aes temp_key;
+    __m128i *Key_Schedule = (__m128i*)aes->key;
+    __m128i *Temp_Key_Schedule = (__m128i*)temp_key.key;
+
+    if (!userKey || !aes)
+        return BAD_FUNC_ARG;
+
+    if (AES_set_encrypt_key(userKey,bits,&temp_key) == BAD_FUNC_ARG)
+        return BAD_FUNC_ARG;
+
+    nr = temp_key.rounds;
+    aes->rounds = nr;
+
+    Key_Schedule[nr] = Temp_Key_Schedule[0];
+    Key_Schedule[nr-1] = _mm_aesimc_si128(Temp_Key_Schedule[1]);
+    Key_Schedule[nr-2] = _mm_aesimc_si128(Temp_Key_Schedule[2]);
+    Key_Schedule[nr-3] = _mm_aesimc_si128(Temp_Key_Schedule[3]);
+    Key_Schedule[nr-4] = _mm_aesimc_si128(Temp_Key_Schedule[4]);
+    Key_Schedule[nr-5] = _mm_aesimc_si128(Temp_Key_Schedule[5]);
+    Key_Schedule[nr-6] = _mm_aesimc_si128(Temp_Key_Schedule[6]);
+    Key_Schedule[nr-7] = _mm_aesimc_si128(Temp_Key_Schedule[7]);
+    Key_Schedule[nr-8] = _mm_aesimc_si128(Temp_Key_Schedule[8]);
+    Key_Schedule[nr-9] = _mm_aesimc_si128(Temp_Key_Schedule[9]);
+
+    if(nr>10) {
+        Key_Schedule[nr-10] = _mm_aesimc_si128(Temp_Key_Schedule[10]);
+        Key_Schedule[nr-11] = _mm_aesimc_si128(Temp_Key_Schedule[11]);
+    }
+
+    if(nr>12) {
+        Key_Schedule[nr-12] = _mm_aesimc_si128(Temp_Key_Schedule[12]);
+        Key_Schedule[nr-13] = _mm_aesimc_si128(Temp_Key_Schedule[13]);
+    }
+
+    Key_Schedule[0] = Temp_Key_Schedule[nr];
+
+    return 0;
+}
+
+
+
+#endif /* WOLFSSL_AESNI */
+
+
+static void wc_AesEncrypt(Aes* aes, const byte* inBlock, byte* outBlock)
+{
+    word32 s0, s1, s2, s3;
+    word32 t0, t1, t2, t3;
+    word32 r = aes->rounds >> 1;
+
+    const word32* rk = aes->key;
+    if (r > 7 || r == 0) {
+        WOLFSSL_MSG("AesEncrypt encountered improper key, set it up");
+        return;  /* stop instead of segfaulting, set up your keys! */
+    }
+#ifdef WOLFSSL_AESNI
+    if (haveAESNI && aes->use_aesni) {
+        #ifdef DEBUG_AESNI
+            printf("about to aes encrypt\n");
+            printf("in  = %p\n", inBlock);
+            printf("out = %p\n", outBlock);
+            printf("aes->key = %p\n", aes->key);
+            printf("aes->rounds = %d\n", aes->rounds);
+            printf("sz = %d\n", AES_BLOCK_SIZE);
+        #endif
+
+        /* check alignment, decrypt doesn't need alignment */
+        if ((wolfssl_word)inBlock % 16) {
+        #ifndef NO_WOLFSSL_ALLOC_ALIGN
+            byte* tmp = (byte*)XMALLOC(AES_BLOCK_SIZE, NULL,
+                                                      DYNAMIC_TYPE_TMP_BUFFER);
+            if (tmp == NULL) return;
+
+            XMEMCPY(tmp, inBlock, AES_BLOCK_SIZE);
+            AES_ECB_encrypt(tmp, tmp, AES_BLOCK_SIZE, (byte*)aes->key,
+                            aes->rounds);
+            XMEMCPY(outBlock, tmp, AES_BLOCK_SIZE);
+            XFREE(tmp, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            return;
+        #else
+            WOLFSSL_MSG("AES-ECB encrypt with bad alignment");
+            return;
+        #endif
+        }
+
+        AES_ECB_encrypt(inBlock, outBlock, AES_BLOCK_SIZE, (byte*)aes->key,
+                        aes->rounds);
+
+        return;
+    }
+    else {
+        #ifdef DEBUG_AESNI
+            printf("Skipping AES-NI\n");
+        #endif
+    }
+#endif
+
+    /*
+     * map byte array block to cipher state
+     * and add initial round key:
+     */
+    XMEMCPY(&s0, inBlock,                  sizeof(s0));
+    XMEMCPY(&s1, inBlock + sizeof(s0),     sizeof(s1));
+    XMEMCPY(&s2, inBlock + 2 * sizeof(s0), sizeof(s2));
+    XMEMCPY(&s3, inBlock + 3 * sizeof(s0), sizeof(s3));
+
+    #ifdef LITTLE_ENDIAN_ORDER
+        s0 = ByteReverseWord32(s0);
+        s1 = ByteReverseWord32(s1);
+        s2 = ByteReverseWord32(s2);
+        s3 = ByteReverseWord32(s3);
+    #endif
+
+    s0 ^= rk[0];
+    s1 ^= rk[1];
+    s2 ^= rk[2];
+    s3 ^= rk[3];
+
+    /*
+     * Nr - 1 full rounds:
+     */
+
+    for (;;) {
+        t0 =
+            Te[0][GETBYTE(s0, 3)]  ^
+            Te[1][GETBYTE(s1, 2)]  ^
+            Te[2][GETBYTE(s2, 1)]  ^
+            Te[3][GETBYTE(s3, 0)]  ^
+            rk[4];
+        t1 =
+            Te[0][GETBYTE(s1, 3)]  ^
+            Te[1][GETBYTE(s2, 2)]  ^
+            Te[2][GETBYTE(s3, 1)]  ^
+            Te[3][GETBYTE(s0, 0)]  ^
+            rk[5];
+        t2 =
+            Te[0][GETBYTE(s2, 3)] ^
+            Te[1][GETBYTE(s3, 2)]  ^
+            Te[2][GETBYTE(s0, 1)]  ^
+            Te[3][GETBYTE(s1, 0)]  ^
+            rk[6];
+        t3 =
+            Te[0][GETBYTE(s3, 3)] ^
+            Te[1][GETBYTE(s0, 2)]  ^
+            Te[2][GETBYTE(s1, 1)]  ^
+            Te[3][GETBYTE(s2, 0)]  ^
+            rk[7];
+
+        rk += 8;
+        if (--r == 0) {
+            break;
+        }
+
+        s0 =
+            Te[0][GETBYTE(t0, 3)] ^
+            Te[1][GETBYTE(t1, 2)] ^
+            Te[2][GETBYTE(t2, 1)] ^
+            Te[3][GETBYTE(t3, 0)] ^
+            rk[0];
+        s1 =
+            Te[0][GETBYTE(t1, 3)] ^
+            Te[1][GETBYTE(t2, 2)] ^
+            Te[2][GETBYTE(t3, 1)] ^
+            Te[3][GETBYTE(t0, 0)] ^
+            rk[1];
+        s2 =
+            Te[0][GETBYTE(t2, 3)] ^
+            Te[1][GETBYTE(t3, 2)] ^
+            Te[2][GETBYTE(t0, 1)] ^
+            Te[3][GETBYTE(t1, 0)] ^
+            rk[2];
+        s3 =
+            Te[0][GETBYTE(t3, 3)] ^
+            Te[1][GETBYTE(t0, 2)] ^
+            Te[2][GETBYTE(t1, 1)] ^
+            Te[3][GETBYTE(t2, 0)] ^
+            rk[3];
+    }
+
+    /*
+     * apply last round and
+     * map cipher state to byte array block:
+     */
+
+    s0 =
+        (Te[4][GETBYTE(t0, 3)] & 0xff000000) ^
+        (Te[4][GETBYTE(t1, 2)] & 0x00ff0000) ^
+        (Te[4][GETBYTE(t2, 1)] & 0x0000ff00) ^
+        (Te[4][GETBYTE(t3, 0)] & 0x000000ff) ^
+        rk[0];
+    s1 =
+        (Te[4][GETBYTE(t1, 3)] & 0xff000000) ^
+        (Te[4][GETBYTE(t2, 2)] & 0x00ff0000) ^
+        (Te[4][GETBYTE(t3, 1)] & 0x0000ff00) ^
+        (Te[4][GETBYTE(t0, 0)] & 0x000000ff) ^
+        rk[1];
+    s2 =
+        (Te[4][GETBYTE(t2, 3)] & 0xff000000) ^
+        (Te[4][GETBYTE(t3, 2)] & 0x00ff0000) ^
+        (Te[4][GETBYTE(t0, 1)] & 0x0000ff00) ^
+        (Te[4][GETBYTE(t1, 0)] & 0x000000ff) ^
+        rk[2];
+    s3 =
+        (Te[4][GETBYTE(t3, 3)] & 0xff000000) ^
+        (Te[4][GETBYTE(t0, 2)] & 0x00ff0000) ^
+        (Te[4][GETBYTE(t1, 1)] & 0x0000ff00) ^
+        (Te[4][GETBYTE(t2, 0)] & 0x000000ff) ^
+        rk[3];
+
+    /* write out */
+    #ifdef LITTLE_ENDIAN_ORDER
+        s0 = ByteReverseWord32(s0);
+        s1 = ByteReverseWord32(s1);
+        s2 = ByteReverseWord32(s2);
+        s3 = ByteReverseWord32(s3);
+    #endif
+
+    XMEMCPY(outBlock,                  &s0, sizeof(s0));
+    XMEMCPY(outBlock + sizeof(s0),     &s1, sizeof(s1));
+    XMEMCPY(outBlock + 2 * sizeof(s0), &s2, sizeof(s2));
+    XMEMCPY(outBlock + 3 * sizeof(s0), &s3, sizeof(s3));
+}
+
+static void wc_AesDecrypt(Aes* aes, const byte* inBlock, byte* outBlock)
+{
+    word32 s0, s1, s2, s3;
+    word32 t0, t1, t2, t3;
+    word32 r = aes->rounds >> 1;
+
+    const word32* rk = aes->key;
+    if (r > 7 || r == 0) {
+        WOLFSSL_MSG("AesDecrypt encountered improper key, set it up");
+        return;  /* stop instead of segfaulting, set up your keys! */
+    }
+#ifdef WOLFSSL_AESNI
+    if (haveAESNI && aes->use_aesni) {
+        #ifdef DEBUG_AESNI
+            printf("about to aes decrypt\n");
+            printf("in  = %p\n", inBlock);
+            printf("out = %p\n", outBlock);
+            printf("aes->key = %p\n", aes->key);
+            printf("aes->rounds = %d\n", aes->rounds);
+            printf("sz = %d\n", AES_BLOCK_SIZE);
+        #endif
+
+        /* if input and output same will overwrite input iv */
+        XMEMCPY(aes->tmp, inBlock, AES_BLOCK_SIZE);
+        AES_ECB_decrypt(inBlock, outBlock, AES_BLOCK_SIZE, (byte*)aes->key,
+                        aes->rounds);
+        return;
+    }
+    else {
+        #ifdef DEBUG_AESNI
+            printf("Skipping AES-NI\n");
+        #endif
+    }
+#endif
+
+    /*
+     * map byte array block to cipher state
+     * and add initial round key:
+     */
+    XMEMCPY(&s0, inBlock,                  sizeof(s0));
+    XMEMCPY(&s1, inBlock + sizeof(s0),     sizeof(s1));
+    XMEMCPY(&s2, inBlock + 2 * sizeof(s0), sizeof(s2));
+    XMEMCPY(&s3, inBlock + 3 * sizeof(s0), sizeof(s3));
+
+    #ifdef LITTLE_ENDIAN_ORDER
+        s0 = ByteReverseWord32(s0);
+        s1 = ByteReverseWord32(s1);
+        s2 = ByteReverseWord32(s2);
+        s3 = ByteReverseWord32(s3);
+    #endif
+
+    s0 ^= rk[0];
+    s1 ^= rk[1];
+    s2 ^= rk[2];
+    s3 ^= rk[3];
+
+    /*
+     * Nr - 1 full rounds:
+     */
+
+    for (;;) {
+        t0 =
+            Td[0][GETBYTE(s0, 3)] ^
+            Td[1][GETBYTE(s3, 2)] ^
+            Td[2][GETBYTE(s2, 1)] ^
+            Td[3][GETBYTE(s1, 0)] ^
+            rk[4];
+        t1 =
+            Td[0][GETBYTE(s1, 3)] ^
+            Td[1][GETBYTE(s0, 2)] ^
+            Td[2][GETBYTE(s3, 1)] ^
+            Td[3][GETBYTE(s2, 0)] ^
+            rk[5];
+        t2 =
+            Td[0][GETBYTE(s2, 3)] ^
+            Td[1][GETBYTE(s1, 2)] ^
+            Td[2][GETBYTE(s0, 1)] ^
+            Td[3][GETBYTE(s3, 0)] ^
+            rk[6];
+        t3 =
+            Td[0][GETBYTE(s3, 3)] ^
+            Td[1][GETBYTE(s2, 2)] ^
+            Td[2][GETBYTE(s1, 1)] ^
+            Td[3][GETBYTE(s0, 0)] ^
+            rk[7];
+
+        rk += 8;
+        if (--r == 0) {
+            break;
+        }
+
+        s0 =
+            Td[0][GETBYTE(t0, 3)] ^
+            Td[1][GETBYTE(t3, 2)] ^
+            Td[2][GETBYTE(t2, 1)] ^
+            Td[3][GETBYTE(t1, 0)] ^
+            rk[0];
+        s1 =
+            Td[0][GETBYTE(t1, 3)] ^
+            Td[1][GETBYTE(t0, 2)] ^
+            Td[2][GETBYTE(t3, 1)] ^
+            Td[3][GETBYTE(t2, 0)] ^
+            rk[1];
+        s2 =
+            Td[0][GETBYTE(t2, 3)] ^
+            Td[1][GETBYTE(t1, 2)] ^
+            Td[2][GETBYTE(t0, 1)] ^
+            Td[3][GETBYTE(t3, 0)] ^
+            rk[2];
+        s3 =
+            Td[0][GETBYTE(t3, 3)] ^
+            Td[1][GETBYTE(t2, 2)] ^
+            Td[2][GETBYTE(t1, 1)] ^
+            Td[3][GETBYTE(t0, 0)] ^
+            rk[3];
+    }
+    /*
+     * apply last round and
+     * map cipher state to byte array block:
+     */
+    s0 =
+        (Td[4][GETBYTE(t0, 3)] & 0xff000000) ^
+        (Td[4][GETBYTE(t3, 2)] & 0x00ff0000) ^
+        (Td[4][GETBYTE(t2, 1)] & 0x0000ff00) ^
+        (Td[4][GETBYTE(t1, 0)] & 0x000000ff) ^
+        rk[0];
+    s1 =
+        (Td[4][GETBYTE(t1, 3)] & 0xff000000) ^
+        (Td[4][GETBYTE(t0, 2)] & 0x00ff0000) ^
+        (Td[4][GETBYTE(t3, 1)] & 0x0000ff00) ^
+        (Td[4][GETBYTE(t2, 0)] & 0x000000ff) ^
+        rk[1];
+    s2 =
+        (Td[4][GETBYTE(t2, 3)] & 0xff000000) ^
+        (Td[4][GETBYTE(t1, 2)] & 0x00ff0000) ^
+        (Td[4][GETBYTE(t0, 1)] & 0x0000ff00) ^
+        (Td[4][GETBYTE(t3, 0)] & 0x000000ff) ^
+        rk[2];
+    s3 =
+        (Td[4][GETBYTE(t3, 3)] & 0xff000000) ^
+        (Td[4][GETBYTE(t2, 2)] & 0x00ff0000) ^
+        (Td[4][GETBYTE(t1, 1)] & 0x0000ff00) ^
+        (Td[4][GETBYTE(t0, 0)] & 0x000000ff) ^
+        rk[3];
+
+    /* write out */
+    #ifdef LITTLE_ENDIAN_ORDER
+        s0 = ByteReverseWord32(s0);
+        s1 = ByteReverseWord32(s1);
+        s2 = ByteReverseWord32(s2);
+        s3 = ByteReverseWord32(s3);
+    #endif
+
+    XMEMCPY(outBlock,                  &s0, sizeof(s0));
+    XMEMCPY(outBlock + sizeof(s0),     &s1, sizeof(s1));
+    XMEMCPY(outBlock + 2 * sizeof(s0), &s2, sizeof(s2));
+    XMEMCPY(outBlock + 3 * sizeof(s0), &s3, sizeof(s3));
+}
+
+#endif /* NEED_AES_TABLES */
+
+
+/* wc_AesSetKey */
+#ifdef STM32F2_CRYPTO
+    int wc_AesSetKey(Aes* aes, const byte* userKey, word32 keylen, const byte* iv,
+                  int dir)
+    {
+        word32 *rk = aes->key;
+
+        if (!((keylen == 16) || (keylen == 24) || (keylen == 32)))
+            return BAD_FUNC_ARG;
+
+        aes->rounds = keylen/4 + 6;
+        XMEMCPY(rk, userKey, keylen);
+        ByteReverseWords(rk, rk, keylen);
+
+        return wc_AesSetIV(aes, iv);
+    }
+
+    int wc_AesSetKeyDirect(Aes* aes, const byte* userKey, word32 keylen,
+                        const byte* iv, int dir)
+    {
+        return wc_AesSetKey(aes, userKey, keylen, iv, dir);
+    }
+
+#elif defined(HAVE_COLDFIRE_SEC)
+    #if defined (HAVE_THREADX)
+        #include "memory_pools.h"
+        extern TX_BYTE_POOL mp_ncached;  /* Non Cached memory pool */
+    #endif
+
+    #define AES_BUFFER_SIZE (AES_BLOCK_SIZE * 64)
+    static unsigned char *AESBuffIn = NULL;
+    static unsigned char *AESBuffOut = NULL;
+    static byte *secReg;
+    static byte *secKey;
+    static volatile SECdescriptorType *secDesc;
+
+    static wolfSSL_Mutex Mutex_AesSEC;
+
+    #define SEC_DESC_AES_CBC_ENCRYPT 0x60300010
+    #define SEC_DESC_AES_CBC_DECRYPT 0x60200010
+
+    extern volatile unsigned char __MBAR[];
+
+    int wc_AesSetKey(Aes* aes, const byte* userKey, word32 keylen, const byte* iv,
+                  int dir)
+    {
+        if (AESBuffIn == NULL) {
+            #if defined (HAVE_THREADX)
+			    int s1, s2, s3, s4, s5 ;
+                s5 = tx_byte_allocate(&mp_ncached,(void *)&secDesc,
+                                      sizeof(SECdescriptorType), TX_NO_WAIT);
+                s1 = tx_byte_allocate(&mp_ncached, (void *)&AESBuffIn,
+                                      AES_BUFFER_SIZE, TX_NO_WAIT);
+                s2 = tx_byte_allocate(&mp_ncached, (void *)&AESBuffOut,
+                                      AES_BUFFER_SIZE, TX_NO_WAIT);
+                s3 = tx_byte_allocate(&mp_ncached, (void *)&secKey,
+                                      AES_BLOCK_SIZE*2, TX_NO_WAIT);
+                s4 = tx_byte_allocate(&mp_ncached, (void *)&secReg,
+                                      AES_BLOCK_SIZE, TX_NO_WAIT);
+
+                if(s1 || s2 || s3 || s4 || s5)
+                    return BAD_FUNC_ARG;
+            #else
+                #warning "Allocate non-Cache buffers"
+            #endif
+
+            InitMutex(&Mutex_AesSEC);
+        }
+
+        if (!((keylen == 16) || (keylen == 24) || (keylen == 32)))
+            return BAD_FUNC_ARG;
+
+        if (aes == NULL)
+            return BAD_FUNC_ARG;
+
+        aes->rounds = keylen/4 + 6;
+        XMEMCPY(aes->key, userKey, keylen);
+
+        if (iv)
+            XMEMCPY(aes->reg, iv, AES_BLOCK_SIZE);
+
+        return 0;
+    }
+#elif defined(FREESCALE_MMCAU)
+    int wc_AesSetKey(Aes* aes, const byte* userKey, word32 keylen, const byte* iv,
+                  int dir)
+    {
+        byte *rk = (byte*)aes->key;
+
+        if (!((keylen == 16) || (keylen == 24) || (keylen == 32)))
+            return BAD_FUNC_ARG;
+
+        if (rk == NULL)
+            return BAD_FUNC_ARG;
+
+        aes->rounds = keylen/4 + 6;
+        cau_aes_set_key(userKey, keylen*8, rk);
+
+        return wc_AesSetIV(aes, iv);
+    }
+
+    int wc_AesSetKeyDirect(Aes* aes, const byte* userKey, word32 keylen,
+                        const byte* iv, int dir)
+    {
+        return wc_AesSetKey(aes, userKey, keylen, iv, dir);
+    }
+#else
+    static int wc_AesSetKeyLocal(Aes* aes, const byte* userKey, word32 keylen,
+                const byte* iv, int dir)
+    {
+        word32 temp, *rk = aes->key;
+        unsigned int i = 0;
+
+        #ifdef WOLFSSL_AESNI
+            aes->use_aesni = 0;
+        #endif /* WOLFSSL_AESNI */
+        #ifdef WOLFSSL_AES_COUNTER
+            aes->left = 0;
+        #endif /* WOLFSSL_AES_COUNTER */
+
+        aes->rounds = keylen/4 + 6;
+
+        XMEMCPY(rk, userKey, keylen);
+        #ifdef LITTLE_ENDIAN_ORDER
+            ByteReverseWords(rk, rk, keylen);
+        #endif
+
+        #ifdef WOLFSSL_PIC32MZ_CRYPT
+        {
+            word32 *akey1 = aes->key_ce;
+            word32 *areg = aes->iv_ce ;
+            aes->keylen = keylen ;
+            XMEMCPY(akey1, userKey, keylen);
+            if (iv)
+                XMEMCPY(areg, iv, AES_BLOCK_SIZE);
+            else
+                XMEMSET(areg,  0, AES_BLOCK_SIZE);
+        }
+        #endif
+
+        switch(keylen)
+        {
+        case 16:
+            while (1)
+            {
+                temp  = rk[3];
+                rk[4] = rk[0] ^
+                    (Te[4][GETBYTE(temp, 2)] & 0xff000000) ^
+                    (Te[4][GETBYTE(temp, 1)] & 0x00ff0000) ^
+                    (Te[4][GETBYTE(temp, 0)] & 0x0000ff00) ^
+                    (Te[4][GETBYTE(temp, 3)] & 0x000000ff) ^
+                    rcon[i];
+                rk[5] = rk[1] ^ rk[4];
+                rk[6] = rk[2] ^ rk[5];
+                rk[7] = rk[3] ^ rk[6];
+                if (++i == 10)
+                    break;
+                rk += 4;
+            }
+            break;
+
+        case 24:
+            /* for (;;) here triggers a bug in VC60 SP4 w/ Pro Pack */
+            while (1)
+            {
+                temp = rk[ 5];
+                rk[ 6] = rk[ 0] ^
+                    (Te[4][GETBYTE(temp, 2)] & 0xff000000) ^
+                    (Te[4][GETBYTE(temp, 1)] & 0x00ff0000) ^
+                    (Te[4][GETBYTE(temp, 0)] & 0x0000ff00) ^
+                    (Te[4][GETBYTE(temp, 3)] & 0x000000ff) ^
+                    rcon[i];
+                rk[ 7] = rk[ 1] ^ rk[ 6];
+                rk[ 8] = rk[ 2] ^ rk[ 7];
+                rk[ 9] = rk[ 3] ^ rk[ 8];
+                if (++i == 8)
+                    break;
+                rk[10] = rk[ 4] ^ rk[ 9];
+                rk[11] = rk[ 5] ^ rk[10];
+                rk += 6;
+            }
+            break;
+
+        case 32:
+            while (1)
+            {
+                temp = rk[ 7];
+                rk[ 8] = rk[ 0] ^
+                    (Te[4][GETBYTE(temp, 2)] & 0xff000000) ^
+                    (Te[4][GETBYTE(temp, 1)] & 0x00ff0000) ^
+                    (Te[4][GETBYTE(temp, 0)] & 0x0000ff00) ^
+                    (Te[4][GETBYTE(temp, 3)] & 0x000000ff) ^
+                    rcon[i];
+                rk[ 9] = rk[ 1] ^ rk[ 8];
+                rk[10] = rk[ 2] ^ rk[ 9];
+                rk[11] = rk[ 3] ^ rk[10];
+                if (++i == 7)
+                    break;
+                temp = rk[11];
+                rk[12] = rk[ 4] ^
+                    (Te[4][GETBYTE(temp, 3)] & 0xff000000) ^
+                    (Te[4][GETBYTE(temp, 2)] & 0x00ff0000) ^
+                    (Te[4][GETBYTE(temp, 1)] & 0x0000ff00) ^
+                    (Te[4][GETBYTE(temp, 0)] & 0x000000ff);
+                rk[13] = rk[ 5] ^ rk[12];
+                rk[14] = rk[ 6] ^ rk[13];
+                rk[15] = rk[ 7] ^ rk[14];
+
+                rk += 8;
+            }
+            break;
+
+        default:
+            return BAD_FUNC_ARG;
+        }
+
+        if (dir == AES_DECRYPTION)
+        {
+            unsigned int j;
+            rk = aes->key;
+
+            /* invert the order of the round keys: */
+            for (i = 0, j = 4* aes->rounds; i < j; i += 4, j -= 4) {
+                temp = rk[i    ]; rk[i    ] = rk[j    ]; rk[j    ] = temp;
+                temp = rk[i + 1]; rk[i + 1] = rk[j + 1]; rk[j + 1] = temp;
+                temp = rk[i + 2]; rk[i + 2] = rk[j + 2]; rk[j + 2] = temp;
+                temp = rk[i + 3]; rk[i + 3] = rk[j + 3]; rk[j + 3] = temp;
+            }
+            /* apply the inverse MixColumn transform to all round keys but the
+               first and the last: */
+            for (i = 1; i < aes->rounds; i++) {
+                rk += 4;
+                rk[0] =
+                    Td[0][Te[4][GETBYTE(rk[0], 3)] & 0xff] ^
+                    Td[1][Te[4][GETBYTE(rk[0], 2)] & 0xff] ^
+                    Td[2][Te[4][GETBYTE(rk[0], 1)] & 0xff] ^
+                    Td[3][Te[4][GETBYTE(rk[0], 0)] & 0xff];
+                rk[1] =
+                    Td[0][Te[4][GETBYTE(rk[1], 3)] & 0xff] ^
+                    Td[1][Te[4][GETBYTE(rk[1], 2)] & 0xff] ^
+                    Td[2][Te[4][GETBYTE(rk[1], 1)] & 0xff] ^
+                    Td[3][Te[4][GETBYTE(rk[1], 0)] & 0xff];
+                rk[2] =
+                    Td[0][Te[4][GETBYTE(rk[2], 3)] & 0xff] ^
+                    Td[1][Te[4][GETBYTE(rk[2], 2)] & 0xff] ^
+                    Td[2][Te[4][GETBYTE(rk[2], 1)] & 0xff] ^
+                    Td[3][Te[4][GETBYTE(rk[2], 0)] & 0xff];
+                rk[3] =
+                    Td[0][Te[4][GETBYTE(rk[3], 3)] & 0xff] ^
+                    Td[1][Te[4][GETBYTE(rk[3], 2)] & 0xff] ^
+                    Td[2][Te[4][GETBYTE(rk[3], 1)] & 0xff] ^
+                    Td[3][Te[4][GETBYTE(rk[3], 0)] & 0xff];
+            }
+        }
+
+        return wc_AesSetIV(aes, iv);
+    }
+
+    int wc_AesSetKey(Aes* aes, const byte* userKey, word32 keylen, const byte* iv,
+                  int dir)
+    {
+
+        if (!((keylen == 16) || (keylen == 24) || (keylen == 32)))
+            return BAD_FUNC_ARG;
+
+        #ifdef HAVE_CAVIUM
+        if (aes->magic == WOLFSSL_AES_CAVIUM_MAGIC)
+            return wc_AesCaviumSetKey(aes, userKey, keylen, iv);
+        #endif
+
+        #ifdef WOLFSSL_AESNI
+        if (checkAESNI == 0) {
+            haveAESNI  = Check_CPU_support_AES();
+            checkAESNI = 1;
+        }
+        if (haveAESNI) {
+            aes->use_aesni = 1;
+            if (iv)
+                XMEMCPY(aes->reg, iv, AES_BLOCK_SIZE);
+            if (dir == AES_ENCRYPTION)
+                return AES_set_encrypt_key(userKey, keylen * 8, aes);
+            else
+                return AES_set_decrypt_key(userKey, keylen * 8, aes);
+        }
+        #endif /* WOLFSSL_AESNI */
+
+        return wc_AesSetKeyLocal(aes, userKey, keylen, iv, dir);
+    }
+
+    #if defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER)
+
+    /* AES-CTR and AES-DIRECT need to use this for key setup, no aesni yet */
+    int wc_AesSetKeyDirect(Aes* aes, const byte* userKey, word32 keylen,
+                        const byte* iv, int dir)
+    {
+        return wc_AesSetKeyLocal(aes, userKey, keylen, iv, dir);
+    }
+
+    #endif /* WOLFSSL_AES_DIRECT || WOLFSSL_AES_COUNTER */
+#endif /* STM32F2_CRYPTO, wc_AesSetKey block */
+
+
+/* wc_AesSetIV is shared between software and hardware */
+int wc_AesSetIV(Aes* aes, const byte* iv)
+{
+    if (aes == NULL)
+        return BAD_FUNC_ARG;
+
+    if (iv)
+        XMEMCPY(aes->reg, iv, AES_BLOCK_SIZE);
+    else
+        XMEMSET(aes->reg,  0, AES_BLOCK_SIZE);
+
+    return 0;
+}
+
+
+int wc_AesCbcDecryptWithKey(byte* out, const byte* in, word32 inSz,
+                                  const byte* key, word32 keySz, const byte* iv)
+{
+    int  ret = 0;
+#ifdef WOLFSSL_SMALL_STACK
+    Aes* aes = NULL;
+#else
+    Aes  aes[1];
+#endif
+
+#ifdef WOLFSSL_SMALL_STACK
+    aes = (Aes*)XMALLOC(sizeof(Aes), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (aes == NULL)
+        return MEMORY_E;
+#endif
+
+    ret = wc_AesSetKey(aes, key, keySz, iv, AES_DECRYPTION);
+    if (ret == 0)
+        ret = wc_AesCbcDecrypt(aes, out, in, inSz); 
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(aes, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+
+/* AES-DIRECT */
+#if defined(WOLFSSL_AES_DIRECT)
+    #if defined(FREESCALE_MMCAU)
+
+        /* Allow direct access to one block encrypt */
+        void wc_AesEncryptDirect(Aes* aes, byte* out, const byte* in)
+        {
+            byte* key;
+            key = (byte*)aes->key;
+
+            return cau_aes_encrypt(in, key, aes->rounds, out);
+        }
+
+        /* Allow direct access to one block decrypt */
+        void wc_AesDecryptDirect(Aes* aes, byte* out, const byte* in)
+        {
+            byte* key;
+            key = (byte*)aes->key;
+
+            return cau_aes_decrypt(in, key, aes->rounds, out);
+        }
+
+    #elif defined(STM32F2_CRYPTO)
+        #error "STM32F2 crypto doesn't yet support AES direct"
+
+    #elif defined(HAVE_COLDFIRE_SEC)
+        #error "Coldfire SEC doesn't yet support AES direct"
+
+    #elif defined(WOLFSSL_PIC32MZ_CRYPT)
+        #error "PIC32MZ doesn't yet support AES direct"
+
+    #else
+        /* Allow direct access to one block encrypt */
+        void wc_AesEncryptDirect(Aes* aes, byte* out, const byte* in)
+        {
+            wc_AesEncrypt(aes, in, out);
+        }
+
+        /* Allow direct access to one block decrypt */
+        void wc_AesDecryptDirect(Aes* aes, byte* out, const byte* in)
+        {
+            wc_AesDecrypt(aes, in, out);
+        }
+
+    #endif /* FREESCALE_MMCAU, AES direct block */
+#endif /* WOLFSSL_AES_DIRECT */
+
+
+/* AES-CBC */
+#ifdef STM32F2_CRYPTO
+    int wc_AesCbcEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
+    {
+        word32 *enc_key, *iv;
+        CRYP_InitTypeDef AES_CRYP_InitStructure;
+        CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
+        CRYP_IVInitTypeDef AES_CRYP_IVInitStructure;
+
+        enc_key = aes->key;
+        iv = aes->reg;
+
+        /* crypto structure initialization */
+        CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure);
+        CRYP_StructInit(&AES_CRYP_InitStructure);
+        CRYP_IVStructInit(&AES_CRYP_IVInitStructure);
+
+        /* reset registers to their default values */
+        CRYP_DeInit();
+
+        /* load key into correct registers */
+        switch(aes->rounds)
+        {
+            case 10: /* 128-bit key */
+                AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
+                AES_CRYP_KeyInitStructure.CRYP_Key2Left  = enc_key[0];
+                AES_CRYP_KeyInitStructure.CRYP_Key2Right = enc_key[1];
+                AES_CRYP_KeyInitStructure.CRYP_Key3Left  = enc_key[2];
+                AES_CRYP_KeyInitStructure.CRYP_Key3Right = enc_key[3];
+                break;
+
+            case 12: /* 192-bit key */
+                AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b;
+                AES_CRYP_KeyInitStructure.CRYP_Key1Left  = enc_key[0];
+                AES_CRYP_KeyInitStructure.CRYP_Key1Right = enc_key[1];
+                AES_CRYP_KeyInitStructure.CRYP_Key2Left  = enc_key[2];
+                AES_CRYP_KeyInitStructure.CRYP_Key2Right = enc_key[3];
+                AES_CRYP_KeyInitStructure.CRYP_Key3Left  = enc_key[4];
+                AES_CRYP_KeyInitStructure.CRYP_Key3Right = enc_key[5];
+                break;
+
+            case 14: /* 256-bit key */
+                AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b;
+                AES_CRYP_KeyInitStructure.CRYP_Key0Left  = enc_key[0];
+                AES_CRYP_KeyInitStructure.CRYP_Key0Right = enc_key[1];
+                AES_CRYP_KeyInitStructure.CRYP_Key1Left  = enc_key[2];
+                AES_CRYP_KeyInitStructure.CRYP_Key1Right = enc_key[3];
+                AES_CRYP_KeyInitStructure.CRYP_Key2Left  = enc_key[4];
+                AES_CRYP_KeyInitStructure.CRYP_Key2Right = enc_key[5];
+                AES_CRYP_KeyInitStructure.CRYP_Key3Left  = enc_key[6];
+                AES_CRYP_KeyInitStructure.CRYP_Key3Right = enc_key[7];
+                break;
+
+            default:
+                break;
+        }
+        CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
+
+        /* set iv */
+        ByteReverseWords(iv, iv, AES_BLOCK_SIZE);
+        AES_CRYP_IVInitStructure.CRYP_IV0Left  = iv[0];
+        AES_CRYP_IVInitStructure.CRYP_IV0Right = iv[1];
+        AES_CRYP_IVInitStructure.CRYP_IV1Left  = iv[2];
+        AES_CRYP_IVInitStructure.CRYP_IV1Right = iv[3];
+        CRYP_IVInit(&AES_CRYP_IVInitStructure);
+
+        /* set direction, mode, and datatype */
+        AES_CRYP_InitStructure.CRYP_AlgoDir  = CRYP_AlgoDir_Encrypt;
+        AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CBC;
+        AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
+        CRYP_Init(&AES_CRYP_InitStructure);
+
+        /* enable crypto processor */
+        CRYP_Cmd(ENABLE);
+
+        while (sz > 0)
+        {
+            /* flush IN/OUT FIFOs */
+            CRYP_FIFOFlush();
+
+            CRYP_DataIn(*(uint32_t*)&in[0]);
+            CRYP_DataIn(*(uint32_t*)&in[4]);
+            CRYP_DataIn(*(uint32_t*)&in[8]);
+            CRYP_DataIn(*(uint32_t*)&in[12]);
+
+            /* wait until the complete message has been processed */
+            while(CRYP_GetFlagStatus(CRYP_FLAG_BUSY) != RESET) {}
+
+            *(uint32_t*)&out[0]  = CRYP_DataOut();
+            *(uint32_t*)&out[4]  = CRYP_DataOut();
+            *(uint32_t*)&out[8]  = CRYP_DataOut();
+            *(uint32_t*)&out[12] = CRYP_DataOut();
+
+            /* store iv for next call */
+            XMEMCPY(aes->reg, out + sz - AES_BLOCK_SIZE, AES_BLOCK_SIZE);
+
+            sz  -= 16;
+            in  += 16;
+            out += 16;
+        }
+
+        /* disable crypto processor */
+        CRYP_Cmd(DISABLE);
+
+        return 0;
+    }
+
+    int wc_AesCbcDecrypt(Aes* aes, byte* out, const byte* in, word32 sz)
+    {
+        word32 *dec_key, *iv;
+        CRYP_InitTypeDef AES_CRYP_InitStructure;
+        CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
+        CRYP_IVInitTypeDef AES_CRYP_IVInitStructure;
+
+        dec_key = aes->key;
+        iv = aes->reg;
+
+        /* crypto structure initialization */
+        CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure);
+        CRYP_StructInit(&AES_CRYP_InitStructure);
+        CRYP_IVStructInit(&AES_CRYP_IVInitStructure);
+
+        /* if input and output same will overwrite input iv */
+        XMEMCPY(aes->tmp, in + sz - AES_BLOCK_SIZE, AES_BLOCK_SIZE);
+
+        /* reset registers to their default values */
+        CRYP_DeInit();
+
+        /* load key into correct registers */
+        switch(aes->rounds)
+        {
+            case 10: /* 128-bit key */
+                AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
+                AES_CRYP_KeyInitStructure.CRYP_Key2Left  = dec_key[0];
+                AES_CRYP_KeyInitStructure.CRYP_Key2Right = dec_key[1];
+                AES_CRYP_KeyInitStructure.CRYP_Key3Left  = dec_key[2];
+                AES_CRYP_KeyInitStructure.CRYP_Key3Right = dec_key[3];
+                break;
+
+            case 12: /* 192-bit key */
+                AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b;
+                AES_CRYP_KeyInitStructure.CRYP_Key1Left  = dec_key[0];
+                AES_CRYP_KeyInitStructure.CRYP_Key1Right = dec_key[1];
+                AES_CRYP_KeyInitStructure.CRYP_Key2Left  = dec_key[2];
+                AES_CRYP_KeyInitStructure.CRYP_Key2Right = dec_key[3];
+                AES_CRYP_KeyInitStructure.CRYP_Key3Left  = dec_key[4];
+                AES_CRYP_KeyInitStructure.CRYP_Key3Right = dec_key[5];
+                break;
+
+            case 14: /* 256-bit key */
+                AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b;
+                AES_CRYP_KeyInitStructure.CRYP_Key0Left  = dec_key[0];
+                AES_CRYP_KeyInitStructure.CRYP_Key0Right = dec_key[1];
+                AES_CRYP_KeyInitStructure.CRYP_Key1Left  = dec_key[2];
+                AES_CRYP_KeyInitStructure.CRYP_Key1Right = dec_key[3];
+                AES_CRYP_KeyInitStructure.CRYP_Key2Left  = dec_key[4];
+                AES_CRYP_KeyInitStructure.CRYP_Key2Right = dec_key[5];
+                AES_CRYP_KeyInitStructure.CRYP_Key3Left  = dec_key[6];
+                AES_CRYP_KeyInitStructure.CRYP_Key3Right = dec_key[7];
+                break;
+
+            default:
+                break;
+        }
+
+        /* set direction, mode, and datatype for key preparation */
+        AES_CRYP_InitStructure.CRYP_AlgoDir  = CRYP_AlgoDir_Decrypt;
+        AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_Key;
+        AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b;
+        CRYP_Init(&AES_CRYP_InitStructure);
+        CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
+
+        /* enable crypto processor */
+        CRYP_Cmd(ENABLE);
+
+        /* wait until key has been prepared */
+        while(CRYP_GetFlagStatus(CRYP_FLAG_BUSY) != RESET) {}
+
+        /* set direction, mode, and datatype for decryption */
+        AES_CRYP_InitStructure.CRYP_AlgoDir  = CRYP_AlgoDir_Decrypt;
+        AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CBC;
+        AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
+        CRYP_Init(&AES_CRYP_InitStructure);
+
+        /* set iv */
+        ByteReverseWords(iv, iv, AES_BLOCK_SIZE);
+
+        AES_CRYP_IVInitStructure.CRYP_IV0Left  = iv[0];
+        AES_CRYP_IVInitStructure.CRYP_IV0Right = iv[1];
+        AES_CRYP_IVInitStructure.CRYP_IV1Left  = iv[2];
+        AES_CRYP_IVInitStructure.CRYP_IV1Right = iv[3];
+        CRYP_IVInit(&AES_CRYP_IVInitStructure);
+
+        /* enable crypto processor */
+        CRYP_Cmd(ENABLE);
+
+        while (sz > 0)
+        {
+            /* flush IN/OUT FIFOs */
+            CRYP_FIFOFlush();
+
+            CRYP_DataIn(*(uint32_t*)&in[0]);
+            CRYP_DataIn(*(uint32_t*)&in[4]);
+            CRYP_DataIn(*(uint32_t*)&in[8]);
+            CRYP_DataIn(*(uint32_t*)&in[12]);
+
+            /* wait until the complete message has been processed */
+            while(CRYP_GetFlagStatus(CRYP_FLAG_BUSY) != RESET) {}
+
+            *(uint32_t*)&out[0]  = CRYP_DataOut();
+            *(uint32_t*)&out[4]  = CRYP_DataOut();
+            *(uint32_t*)&out[8]  = CRYP_DataOut();
+            *(uint32_t*)&out[12] = CRYP_DataOut();
+
+            /* store iv for next call */
+            XMEMCPY(aes->reg, aes->tmp, AES_BLOCK_SIZE);
+
+            sz -= 16;
+            in += 16;
+            out += 16;
+        }
+
+        /* disable crypto processor */
+        CRYP_Cmd(DISABLE);
+
+        return 0;
+    }
+
+#elif defined(HAVE_COLDFIRE_SEC)
+    static int wc_AesCbcCrypt(Aes* aes, byte* po, const byte* pi, word32 sz,
+                           word32 descHeader)
+    {
+        #ifdef DEBUG_WOLFSSL
+            int i; int stat1, stat2; int ret;
+	    #endif
+
+        int size;
+        volatile int v;
+
+        if ((pi == NULL) || (po == NULL))
+            return BAD_FUNC_ARG;    /*wrong pointer*/
+
+        LockMutex(&Mutex_AesSEC);
+
+        /* Set descriptor for SEC */
+        secDesc->length1 = 0x0;
+        secDesc->pointer1 = NULL;
+
+        secDesc->length2 = AES_BLOCK_SIZE;
+        secDesc->pointer2 = (byte *)secReg; /* Initial Vector */
+
+        switch(aes->rounds) {
+            case 10: secDesc->length3 = 16 ; break ;
+            case 12: secDesc->length3 = 24 ; break ;
+            case 14: secDesc->length3 = 32 ; break ;
+        }
+        XMEMCPY(secKey, aes->key, secDesc->length3);
+
+        secDesc->pointer3 = (byte *)secKey;
+        secDesc->pointer4 = AESBuffIn;
+        secDesc->pointer5 = AESBuffOut;
+        secDesc->length6 = 0x0;
+        secDesc->pointer6 = NULL;
+        secDesc->length7 = 0x0;
+        secDesc->pointer7 = NULL;
+        secDesc->nextDescriptorPtr = NULL;
+
+        while (sz) {
+            secDesc->header = descHeader;
+            XMEMCPY(secReg, aes->reg, AES_BLOCK_SIZE);
+            if ((sz % AES_BUFFER_SIZE) == sz) {
+                size = sz;
+                sz = 0;
+            } else {
+                size = AES_BUFFER_SIZE;
+                sz -= AES_BUFFER_SIZE;
+            }
+            secDesc->length4 = size;
+            secDesc->length5 = size;
+
+            XMEMCPY(AESBuffIn, pi, size);
+            if(descHeader == SEC_DESC_AES_CBC_DECRYPT) {
+                XMEMCPY((void*)aes->tmp, (void*)&(pi[size-AES_BLOCK_SIZE]),
+                        AES_BLOCK_SIZE);
+            }
+
+            /* Point SEC to the location of the descriptor */
+            MCF_SEC_FR0 = (uint32)secDesc;
+            /* Initialize SEC and wait for encryption to complete */
+            MCF_SEC_CCCR0 = 0x0000001a;
+            /* poll SISR to determine when channel is complete */
+            v=0;
+
+            while ((secDesc->header>> 24) != 0xff) v++;
+
+            #ifdef DEBUG_WOLFSSL
+                ret = MCF_SEC_SISRH;
+                stat1 = MCF_SEC_AESSR;
+                stat2 = MCF_SEC_AESISR;
+                if (ret & 0xe0000000) {
+                    db_printf("Aes_Cbc(i=%d):ISRH=%08x, AESSR=%08x, "
+                              "AESISR=%08x\n", i, ret, stat1, stat2);
+                }
+            #endif
+
+            XMEMCPY(po, AESBuffOut, size);
+
+            if (descHeader == SEC_DESC_AES_CBC_ENCRYPT) {
+                XMEMCPY((void*)aes->reg, (void*)&(po[size-AES_BLOCK_SIZE]),
+                        AES_BLOCK_SIZE);
+            } else {
+                XMEMCPY((void*)aes->reg, (void*)aes->tmp, AES_BLOCK_SIZE);
+            }
+
+            pi += size;
+            po += size;
+        }
+
+        UnLockMutex(&Mutex_AesSEC);
+        return 0;
+    }
+
+    int wc_AesCbcEncrypt(Aes* aes, byte* po, const byte* pi, word32 sz)
+    {
+        return (wc_AesCbcCrypt(aes, po, pi, sz, SEC_DESC_AES_CBC_ENCRYPT));
+    }
+
+    int wc_AesCbcDecrypt(Aes* aes, byte* po, const byte* pi, word32 sz)
+    {
+        return (wc_AesCbcCrypt(aes, po, pi, sz, SEC_DESC_AES_CBC_DECRYPT));
+    }
+
+#elif defined(FREESCALE_MMCAU)
+    int wc_AesCbcEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
+    {
+        int i;
+        int offset = 0;
+        int len = sz;
+
+        byte *iv, *enc_key;
+        byte temp_block[AES_BLOCK_SIZE];
+
+        iv      = (byte*)aes->reg;
+        enc_key = (byte*)aes->key;
+
+        if ((wolfssl_word)out % WOLFSSL_MMCAU_ALIGNMENT) {
+            WOLFSSL_MSG("Bad cau_aes_encrypt alignment");
+            return BAD_ALIGN_E;
+        }
+
+        while (len > 0)
+        {
+            XMEMCPY(temp_block, in + offset, AES_BLOCK_SIZE);
+
+            /* XOR block with IV for CBC */
+            for (i = 0; i < AES_BLOCK_SIZE; i++)
+                temp_block[i] ^= iv[i];
+
+            cau_aes_encrypt(temp_block, enc_key, aes->rounds, out + offset);
+
+            len    -= AES_BLOCK_SIZE;
+            offset += AES_BLOCK_SIZE;
+
+            /* store IV for next block */
+            XMEMCPY(iv, out + offset - AES_BLOCK_SIZE, AES_BLOCK_SIZE);
+        }
+
+        return 0;
+    }
+
+    int wc_AesCbcDecrypt(Aes* aes, byte* out, const byte* in, word32 sz)
+    {
+        int i;
+        int offset = 0;
+        int len = sz;
+
+        byte* iv, *dec_key;
+        byte temp_block[AES_BLOCK_SIZE];
+
+        iv      = (byte*)aes->reg;
+        dec_key = (byte*)aes->key;
+
+        if ((wolfssl_word)out % WOLFSSL_MMCAU_ALIGNMENT) {
+            WOLFSSL_MSG("Bad cau_aes_decrypt alignment");
+            return BAD_ALIGN_E;
+        }
+
+        while (len > 0)
+        {
+            XMEMCPY(temp_block, in + offset, AES_BLOCK_SIZE);
+
+            cau_aes_decrypt(in + offset, dec_key, aes->rounds, out + offset);
+
+            /* XOR block with IV for CBC */
+            for (i = 0; i < AES_BLOCK_SIZE; i++)
+                (out + offset)[i] ^= iv[i];
+
+            /* store IV for next block */
+            XMEMCPY(iv, temp_block, AES_BLOCK_SIZE);
+
+            len    -= AES_BLOCK_SIZE;
+            offset += AES_BLOCK_SIZE;
+        }
+
+        return 0;
+    }
+
+#elif defined(WOLFSSL_PIC32MZ_CRYPT)
+    /* core hardware crypt engine driver */
+    static void wc_AesCrypt(Aes *aes, byte* out, const byte* in, word32 sz,
+                                            int dir, int algo, int cryptoalgo)
+    {
+        securityAssociation *sa_p ;
+        bufferDescriptor *bd_p ;
+
+        volatile securityAssociation sa __attribute__((aligned (8)));
+        volatile bufferDescriptor bd __attribute__((aligned (8)));
+        volatile int k ;
+
+        /* get uncached address */
+        sa_p = KVA0_TO_KVA1(&sa) ;
+        bd_p = KVA0_TO_KVA1(&bd) ;
+
+        /* Sync cache and physical memory */
+        if(PIC32MZ_IF_RAM(in)) {
+            XMEMCPY((void *)KVA0_TO_KVA1(in), (void *)in, sz);
+        }
+        XMEMSET((void *)KVA0_TO_KVA1(out), 0, sz);
+        /* Set up the Security Association */
+        XMEMSET((byte *)KVA0_TO_KVA1(&sa), 0, sizeof(sa));
+        sa_p->SA_CTRL.ALGO = algo ; /* AES */
+        sa_p->SA_CTRL.LNC = 1;
+        sa_p->SA_CTRL.LOADIV = 1;
+        sa_p->SA_CTRL.FB = 1;
+        sa_p->SA_CTRL.ENCTYPE = dir ; /* Encryption/Decryption */
+        sa_p->SA_CTRL.CRYPTOALGO = cryptoalgo;
+
+        if(cryptoalgo == PIC32_CRYPTOALGO_AES_GCM){
+            switch(aes->keylen) {
+            case 32:
+                sa_p->SA_CTRL.KEYSIZE = PIC32_AES_KEYSIZE_256 ;
+                break ;
+            case 24:
+                sa_p->SA_CTRL.KEYSIZE = PIC32_AES_KEYSIZE_192 ;
+                break ;
+            case 16:
+                sa_p->SA_CTRL.KEYSIZE = PIC32_AES_KEYSIZE_128 ;
+                break ;
+            }
+        } else
+            sa_p->SA_CTRL.KEYSIZE = PIC32_AES_KEYSIZE_128 ;
+
+        ByteReverseWords(
+        (word32 *)KVA0_TO_KVA1(sa.SA_ENCKEY + 8 - aes->keylen/sizeof(word32)),
+                         (word32 *)aes->key_ce, aes->keylen);
+        ByteReverseWords(
+        (word32*)KVA0_TO_KVA1(sa.SA_ENCIV), (word32 *)aes->iv_ce, 16);
+
+        XMEMSET((byte *)KVA0_TO_KVA1(&bd), 0, sizeof(bd));
+        /* Set up the Buffer Descriptor */
+        bd_p->BD_CTRL.BUFLEN = sz;
+        if(cryptoalgo == PIC32_CRYPTOALGO_AES_GCM) {
+            if(sz % 0x10)
+                bd_p->BD_CTRL.BUFLEN = (sz/0x10 + 1) * 0x10 ;
+        }
+        bd_p->BD_CTRL.LIFM = 1;
+        bd_p->BD_CTRL.SA_FETCH_EN = 1;
+        bd_p->BD_CTRL.LAST_BD = 1;
+        bd_p->BD_CTRL.DESC_EN = 1;
+
+        bd_p->SA_ADDR = (unsigned int)KVA_TO_PA(&sa) ;
+        bd_p->SRCADDR = (unsigned int)KVA_TO_PA(in) ;
+        bd_p->DSTADDR = (unsigned int)KVA_TO_PA(out);
+        bd_p->MSGLEN = sz ;
+
+        CECON = 1 << 6;
+        while (CECON);
+
+        /* Run the engine */
+        CEBDPADDR = (unsigned int)KVA_TO_PA(&bd) ;
+        CEINTEN = 0x07;
+        CECON = 0x27;
+
+        WAIT_ENGINE ;
+
+        if((cryptoalgo == PIC32_CRYPTOALGO_CBC) ||
+           (cryptoalgo == PIC32_CRYPTOALGO_TCBC)||
+           (cryptoalgo == PIC32_CRYPTOALGO_RCBC)) {
+            /* set iv for the next call */
+            if(dir == PIC32_ENCRYPTION) {
+                XMEMCPY((void *)aes->iv_ce,
+                        (void*)KVA0_TO_KVA1(out + sz - AES_BLOCK_SIZE),
+                        AES_BLOCK_SIZE) ;
+            } else {
+                ByteReverseWords((word32*)aes->iv_ce,
+                        (word32 *)KVA0_TO_KVA1(in + sz - AES_BLOCK_SIZE),
+                        AES_BLOCK_SIZE);
+            }
+        }
+        XMEMCPY((byte *)out, (byte *)KVA0_TO_KVA1(out), sz) ;
+        ByteReverseWords((word32*)out, (word32 *)out, sz);
+    }
+
+    int wc_AesCbcEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
+    {
+        wc_AesCrypt(aes, out, in, sz, PIC32_ENCRYPTION, PIC32_ALGO_AES,
+                                                      PIC32_CRYPTOALGO_RCBC );
+        return 0 ;
+    }
+
+    int wc_AesCbcDecrypt(Aes* aes, byte* out, const byte* in, word32 sz)
+    {
+        wc_AesCrypt(aes, out, in, sz, PIC32_DECRYPTION, PIC32_ALGO_AES,
+                                                      PIC32_CRYPTOALGO_RCBC);
+        return 0 ;
+    }
+
+#else
+    int wc_AesCbcEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
+    {
+        word32 blocks = sz / AES_BLOCK_SIZE;
+
+    #ifdef HAVE_CAVIUM
+        if (aes->magic == WOLFSSL_AES_CAVIUM_MAGIC)
+            return wc_AesCaviumCbcEncrypt(aes, out, in, sz);
+    #endif
+
+    #ifdef WOLFSSL_AESNI
+        if (haveAESNI) {
+            #ifdef DEBUG_AESNI
+                printf("about to aes cbc encrypt\n");
+                printf("in  = %p\n", in);
+                printf("out = %p\n", out);
+                printf("aes->key = %p\n", aes->key);
+                printf("aes->reg = %p\n", aes->reg);
+                printf("aes->rounds = %d\n", aes->rounds);
+                printf("sz = %d\n", sz);
+            #endif
+
+            /* check alignment, decrypt doesn't need alignment */
+            if ((wolfssl_word)in % 16) {
+            #ifndef NO_WOLFSSL_ALLOC_ALIGN
+                byte* tmp = (byte*)XMALLOC(sz, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                WOLFSSL_MSG("AES-CBC encrypt with bad alignment");
+                if (tmp == NULL) return MEMORY_E;
+
+                XMEMCPY(tmp, in, sz);
+                AES_CBC_encrypt(tmp, tmp, (byte*)aes->reg, sz, (byte*)aes->key,
+                            aes->rounds);
+                /* store iv for next call */
+                XMEMCPY(aes->reg, tmp + sz - AES_BLOCK_SIZE, AES_BLOCK_SIZE);
+
+                XMEMCPY(out, tmp, sz);
+                XFREE(tmp, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                return 0;
+            #else
+                return BAD_ALIGN_E;
+            #endif
+            }
+
+            AES_CBC_encrypt(in, out, (byte*)aes->reg, sz, (byte*)aes->key,
+                            aes->rounds);
+            /* store iv for next call */
+            XMEMCPY(aes->reg, out + sz - AES_BLOCK_SIZE, AES_BLOCK_SIZE);
+
+            return 0;
+        }
+    #endif
+
+        while (blocks--) {
+            xorbuf((byte*)aes->reg, in, AES_BLOCK_SIZE);
+            wc_AesEncrypt(aes, (byte*)aes->reg, (byte*)aes->reg);
+            XMEMCPY(out, aes->reg, AES_BLOCK_SIZE);
+
+            out += AES_BLOCK_SIZE;
+            in  += AES_BLOCK_SIZE;
+        }
+
+        return 0;
+    }
+
+    int wc_AesCbcDecrypt(Aes* aes, byte* out, const byte* in, word32 sz)
+    {
+        word32 blocks = sz / AES_BLOCK_SIZE;
+
+    #ifdef HAVE_CAVIUM
+        if (aes->magic == WOLFSSL_AES_CAVIUM_MAGIC)
+            return wc_AesCaviumCbcDecrypt(aes, out, in, sz);
+    #endif
+
+    #ifdef WOLFSSL_AESNI
+        if (haveAESNI) {
+            #ifdef DEBUG_AESNI
+                printf("about to aes cbc decrypt\n");
+                printf("in  = %p\n", in);
+                printf("out = %p\n", out);
+                printf("aes->key = %p\n", aes->key);
+                printf("aes->reg = %p\n", aes->reg);
+                printf("aes->rounds = %d\n", aes->rounds);
+                printf("sz = %d\n", sz);
+            #endif
+
+            /* if input and output same will overwrite input iv */
+            XMEMCPY(aes->tmp, in + sz - AES_BLOCK_SIZE, AES_BLOCK_SIZE);
+            AES_CBC_decrypt(in, out, (byte*)aes->reg, sz, (byte*)aes->key,
+                            aes->rounds);
+            /* store iv for next call */
+            XMEMCPY(aes->reg, aes->tmp, AES_BLOCK_SIZE);
+            return 0;
+        }
+    #endif
+
+        while (blocks--) {
+            XMEMCPY(aes->tmp, in, AES_BLOCK_SIZE);
+            wc_AesDecrypt(aes, (byte*)aes->tmp, out);
+            xorbuf(out, (byte*)aes->reg, AES_BLOCK_SIZE);
+            XMEMCPY(aes->reg, aes->tmp, AES_BLOCK_SIZE);
+
+            out += AES_BLOCK_SIZE;
+            in  += AES_BLOCK_SIZE;
+        }
+
+        return 0;
+    }
+
+#endif /* STM32F2_CRYPTO, AES-CBC block */
+
+/* AES-CTR */
+#ifdef WOLFSSL_AES_COUNTER
+
+    #ifdef STM32F2_CRYPTO
+        void wc_AesCtrEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
+        {
+            word32 *enc_key, *iv;
+            CRYP_InitTypeDef AES_CRYP_InitStructure;
+            CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
+            CRYP_IVInitTypeDef AES_CRYP_IVInitStructure;
+
+            enc_key = aes->key;
+            iv = aes->reg;
+
+            /* crypto structure initialization */
+            CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure);
+            CRYP_StructInit(&AES_CRYP_InitStructure);
+            CRYP_IVStructInit(&AES_CRYP_IVInitStructure);
+
+            /* reset registers to their default values */
+            CRYP_DeInit();
+
+            /* load key into correct registers */
+            switch(aes->rounds)
+            {
+                case 10: /* 128-bit key */
+                    AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
+                    AES_CRYP_KeyInitStructure.CRYP_Key2Left  = enc_key[0];
+                    AES_CRYP_KeyInitStructure.CRYP_Key2Right = enc_key[1];
+                    AES_CRYP_KeyInitStructure.CRYP_Key3Left  = enc_key[2];
+                    AES_CRYP_KeyInitStructure.CRYP_Key3Right = enc_key[3];
+                    break;
+
+                case 12: /* 192-bit key */
+                    AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b;
+                    AES_CRYP_KeyInitStructure.CRYP_Key1Left  = enc_key[0];
+                    AES_CRYP_KeyInitStructure.CRYP_Key1Right = enc_key[1];
+                    AES_CRYP_KeyInitStructure.CRYP_Key2Left  = enc_key[2];
+                    AES_CRYP_KeyInitStructure.CRYP_Key2Right = enc_key[3];
+                    AES_CRYP_KeyInitStructure.CRYP_Key3Left  = enc_key[4];
+                    AES_CRYP_KeyInitStructure.CRYP_Key3Right = enc_key[5];
+                    break;
+
+                case 14: /* 256-bit key */
+                    AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b;
+                    AES_CRYP_KeyInitStructure.CRYP_Key0Left  = enc_key[0];
+                    AES_CRYP_KeyInitStructure.CRYP_Key0Right = enc_key[1];
+                    AES_CRYP_KeyInitStructure.CRYP_Key1Left  = enc_key[2];
+                    AES_CRYP_KeyInitStructure.CRYP_Key1Right = enc_key[3];
+                    AES_CRYP_KeyInitStructure.CRYP_Key2Left  = enc_key[4];
+                    AES_CRYP_KeyInitStructure.CRYP_Key2Right = enc_key[5];
+                    AES_CRYP_KeyInitStructure.CRYP_Key3Left  = enc_key[6];
+                    AES_CRYP_KeyInitStructure.CRYP_Key3Right = enc_key[7];
+                    break;
+
+                default:
+                    break;
+            }
+            CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
+
+            /* set iv */
+            ByteReverseWords(iv, iv, AES_BLOCK_SIZE);
+            AES_CRYP_IVInitStructure.CRYP_IV0Left  = iv[0];
+            AES_CRYP_IVInitStructure.CRYP_IV0Right = iv[1];
+            AES_CRYP_IVInitStructure.CRYP_IV1Left  = iv[2];
+            AES_CRYP_IVInitStructure.CRYP_IV1Right = iv[3];
+            CRYP_IVInit(&AES_CRYP_IVInitStructure);
+
+            /* set direction, mode, and datatype */
+            AES_CRYP_InitStructure.CRYP_AlgoDir  = CRYP_AlgoDir_Encrypt;
+            AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CTR;
+            AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
+            CRYP_Init(&AES_CRYP_InitStructure);
+
+            /* enable crypto processor */
+            CRYP_Cmd(ENABLE);
+
+            while (sz > 0)
+            {
+                /* flush IN/OUT FIFOs */
+                CRYP_FIFOFlush();
+
+                CRYP_DataIn(*(uint32_t*)&in[0]);
+                CRYP_DataIn(*(uint32_t*)&in[4]);
+                CRYP_DataIn(*(uint32_t*)&in[8]);
+                CRYP_DataIn(*(uint32_t*)&in[12]);
+
+                /* wait until the complete message has been processed */
+                while(CRYP_GetFlagStatus(CRYP_FLAG_BUSY) != RESET) {}
+
+                *(uint32_t*)&out[0]  = CRYP_DataOut();
+                *(uint32_t*)&out[4]  = CRYP_DataOut();
+                *(uint32_t*)&out[8]  = CRYP_DataOut();
+                *(uint32_t*)&out[12] = CRYP_DataOut();
+
+                /* store iv for next call */
+                XMEMCPY(aes->reg, out + sz - AES_BLOCK_SIZE, AES_BLOCK_SIZE);
+
+                sz  -= 16;
+                in  += 16;
+                out += 16;
+            }
+
+            /* disable crypto processor */
+            CRYP_Cmd(DISABLE);
+        }
+
+    #elif defined(WOLFSSL_PIC32MZ_CRYPT)
+        void wc_AesCtrEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
+        {
+            int i ;
+            char out_block[AES_BLOCK_SIZE] ;
+            int odd ;
+            int even ;
+            char *tmp ; /* (char *)aes->tmp, for short */
+
+            tmp = (char *)aes->tmp ;
+            if(aes->left) {
+                if((aes->left + sz) >= AES_BLOCK_SIZE){
+                    odd = AES_BLOCK_SIZE - aes->left ;
+                } else {
+                    odd = sz ;
+                }
+                XMEMCPY(tmp+aes->left, in, odd) ;
+                if((odd+aes->left) == AES_BLOCK_SIZE){
+                    wc_AesCrypt(aes, out_block, tmp, AES_BLOCK_SIZE,
+                        PIC32_ENCRYPTION, PIC32_ALGO_AES, PIC32_CRYPTOALGO_RCTR);
+                    XMEMCPY(out, out_block+aes->left, odd) ;
+                    aes->left = 0 ;
+                    XMEMSET(tmp, 0x0, AES_BLOCK_SIZE) ;
+                    /* Increment IV */
+                    for (i = AES_BLOCK_SIZE - 1; i >= 0; i--) {
+                        if (++((byte *)aes->iv_ce)[i])
+                            break ;
+                    }
+                }
+                in += odd ;
+                out+= odd ;
+                sz -= odd ;
+            }
+            odd = sz % AES_BLOCK_SIZE ;  /* if there is tail flagment */
+            if(sz / AES_BLOCK_SIZE) {
+                even = (sz/AES_BLOCK_SIZE)*AES_BLOCK_SIZE ;
+                wc_AesCrypt(aes, out, in, even, PIC32_ENCRYPTION, PIC32_ALGO_AES,
+                                                        PIC32_CRYPTOALGO_RCTR);
+                out += even ;
+                in  += even ;
+                do {  /* Increment IV */
+                    for (i = AES_BLOCK_SIZE - 1; i >= 0; i--) {
+                        if (++((byte *)aes->iv_ce)[i])
+                            break ;
+                    }
+                    even -= AES_BLOCK_SIZE ;
+                } while((int)even > 0) ;
+            }
+            if(odd) {
+                XMEMSET(tmp+aes->left, 0x0, AES_BLOCK_SIZE - aes->left) ;
+                XMEMCPY(tmp+aes->left, in, odd) ;
+                wc_AesCrypt(aes, out_block, tmp, AES_BLOCK_SIZE,
+                        PIC32_ENCRYPTION, PIC32_ALGO_AES, PIC32_CRYPTOALGO_RCTR);
+                XMEMCPY(out, out_block+aes->left,odd) ;
+                aes->left += odd ;
+            }
+        }
+
+    #elif defined(HAVE_COLDFIRE_SEC)
+        #error "Coldfire SEC doesn't currently support AES-CTR mode"
+
+    #elif defined(FREESCALE_MMCAU)
+        #error "Freescale mmCAU doesn't currently support AES-CTR mode"
+
+    #else
+        /* Increment AES counter */
+        static INLINE void IncrementAesCounter(byte* inOutCtr)
+        {
+            int i;
+
+            /* in network byte order so start at end and work back */
+            for (i = AES_BLOCK_SIZE - 1; i >= 0; i--) {
+                if (++inOutCtr[i])  /* we're done unless we overflow */
+                    return;
+            }
+        }
+
+        void wc_AesCtrEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
+        {
+            byte* tmp = (byte*)aes->tmp + AES_BLOCK_SIZE - aes->left;
+
+            /* consume any unused bytes left in aes->tmp */
+            while (aes->left && sz) {
+               *(out++) = *(in++) ^ *(tmp++);
+               aes->left--;
+               sz--;
+            }
+
+            /* do as many block size ops as possible */
+            while (sz >= AES_BLOCK_SIZE) {
+                wc_AesEncrypt(aes, (byte*)aes->reg, out);
+                IncrementAesCounter((byte*)aes->reg);
+                xorbuf(out, in, AES_BLOCK_SIZE);
+
+                out += AES_BLOCK_SIZE;
+                in  += AES_BLOCK_SIZE;
+                sz  -= AES_BLOCK_SIZE;
+                aes->left = 0;
+            }
+
+            /* handle non block size remaining and sotre unused byte count in left */
+            if (sz) {
+                wc_AesEncrypt(aes, (byte*)aes->reg, (byte*)aes->tmp);
+                IncrementAesCounter((byte*)aes->reg);
+
+                aes->left = AES_BLOCK_SIZE;
+                tmp = (byte*)aes->tmp;
+
+                while (sz--) {
+                    *(out++) = *(in++) ^ *(tmp++);
+                    aes->left--;
+                }
+            }
+        }
+
+    #endif /* STM32F2_CRYPTO, AES-CTR block */
+
+#endif /* WOLFSSL_AES_COUNTER */
+
+#ifdef HAVE_AESGCM
+
+/*
+ * The IV for AES GCM, stored in struct Aes's member reg, is comprised of
+ * three parts in order:
+ *   1. The implicit IV. This is generated from the PRF using the shared
+ *      secrets between endpoints. It is 4 bytes long.
+ *   2. The explicit IV. This is set by the user of the AES. It needs to be
+ *      unique for each call to encrypt. The explicit IV is shared with the
+ *      other end of the transaction in the clear.
+ *   3. The counter. Each block of data is encrypted with its own sequence
+ *      number counter.
+ */
+
+#ifdef STM32F2_CRYPTO
+    #error "STM32F2 crypto doesn't currently support AES-GCM mode"
+
+#elif defined(HAVE_COLDFIRE_SEC)
+    #error "Coldfire SEC doesn't currently support AES-GCM mode"
+
+#endif
+
+enum {
+    CTR_SZ = 4
+};
+
+
+static INLINE void InitGcmCounter(byte* inOutCtr)
+{
+    inOutCtr[AES_BLOCK_SIZE - 4] = 0;
+    inOutCtr[AES_BLOCK_SIZE - 3] = 0;
+    inOutCtr[AES_BLOCK_SIZE - 2] = 0;
+    inOutCtr[AES_BLOCK_SIZE - 1] = 1;
+}
+
+
+static INLINE void IncrementGcmCounter(byte* inOutCtr)
+{
+    int i;
+
+    /* in network byte order so start at end and work back */
+    for (i = AES_BLOCK_SIZE - 1; i >= AES_BLOCK_SIZE - CTR_SZ; i--) {
+        if (++inOutCtr[i])  /* we're done unless we overflow */
+            return;
+    }
+}
+
+
+#if defined(GCM_SMALL) || defined(GCM_TABLE)
+
+static INLINE void FlattenSzInBits(byte* buf, word32 sz)
+{
+    /* Multiply the sz by 8 */
+    word32 szHi = (sz >> (8*sizeof(sz) - 3));
+    sz <<= 3;
+
+    /* copy over the words of the sz into the destination buffer */
+    buf[0] = (szHi >> 24) & 0xff;
+    buf[1] = (szHi >> 16) & 0xff;
+    buf[2] = (szHi >>  8) & 0xff;
+    buf[3] = szHi & 0xff;
+    buf[4] = (sz >> 24) & 0xff;
+    buf[5] = (sz >> 16) & 0xff;
+    buf[6] = (sz >>  8) & 0xff;
+    buf[7] = sz & 0xff;
+}
+
+
+static INLINE void RIGHTSHIFTX(byte* x)
+{
+    int i;
+    int carryOut = 0;
+    int carryIn = 0;
+    int borrow = x[15] & 0x01;
+
+    for (i = 0; i < AES_BLOCK_SIZE; i++) {
+        carryOut = x[i] & 0x01;
+        x[i] = (x[i] >> 1) | (carryIn ? 0x80 : 0);
+        carryIn = carryOut;
+    }
+    if (borrow) x[0] ^= 0xE1;
+}
+
+#endif /* defined(GCM_SMALL) || defined(GCM_TABLE) */
+
+
+#ifdef GCM_TABLE
+
+static void GenerateM0(Aes* aes)
+{
+    int i, j;
+    byte (*m)[AES_BLOCK_SIZE] = aes->M0;
+
+    XMEMCPY(m[128], aes->H, AES_BLOCK_SIZE);
+
+    for (i = 64; i > 0; i /= 2) {
+        XMEMCPY(m[i], m[i*2], AES_BLOCK_SIZE);
+        RIGHTSHIFTX(m[i]);
+    }
+
+    for (i = 2; i < 256; i *= 2) {
+        for (j = 1; j < i; j++) {
+            XMEMCPY(m[i+j], m[i], AES_BLOCK_SIZE);
+            xorbuf(m[i+j], m[j], AES_BLOCK_SIZE);
+        }
+    }
+
+    XMEMSET(m[0], 0, AES_BLOCK_SIZE);
+}
+
+#endif /* GCM_TABLE */
+
+
+int wc_AesGcmSetKey(Aes* aes, const byte* key, word32 len)
+{
+    int  ret;
+    byte iv[AES_BLOCK_SIZE];
+
+    #ifdef FREESCALE_MMCAU
+        byte* rk = (byte*)aes->key;
+    #endif
+
+    if (!((len == 16) || (len == 24) || (len == 32)))
+        return BAD_FUNC_ARG;
+
+    XMEMSET(iv, 0, AES_BLOCK_SIZE);
+    ret = wc_AesSetKey(aes, key, len, iv, AES_ENCRYPTION);
+
+    if (ret == 0) {
+    #ifdef FREESCALE_MMCAU
+        cau_aes_encrypt(iv, rk, aes->rounds, aes->H);
+    #else
+        wc_AesEncrypt(aes, iv, aes->H);
+    #endif
+    #ifdef GCM_TABLE
+        GenerateM0(aes);
+    #endif /* GCM_TABLE */
+    }
+
+    return ret;
+}
+
+
+#if defined(GCM_SMALL)
+
+static void GMULT(byte* X, byte* Y)
+{
+    byte Z[AES_BLOCK_SIZE];
+    byte V[AES_BLOCK_SIZE];
+    int i, j;
+
+    XMEMSET(Z, 0, AES_BLOCK_SIZE);
+    XMEMCPY(V, X, AES_BLOCK_SIZE);
+    for (i = 0; i < AES_BLOCK_SIZE; i++)
+    {
+        byte y = Y[i];
+        for (j = 0; j < 8; j++)
+        {
+            if (y & 0x80) {
+                xorbuf(Z, V, AES_BLOCK_SIZE);
+            }
+
+            RIGHTSHIFTX(V);
+            y = y << 1;
+        }
+    }
+    XMEMCPY(X, Z, AES_BLOCK_SIZE);
+}
+
+
+static void GHASH(Aes* aes, const byte* a, word32 aSz,
+                                const byte* c, word32 cSz, byte* s, word32 sSz)
+{
+    byte x[AES_BLOCK_SIZE];
+    byte scratch[AES_BLOCK_SIZE];
+    word32 blocks, partial;
+    byte* h = aes->H;
+
+    XMEMSET(x, 0, AES_BLOCK_SIZE);
+
+    /* Hash in A, the Additional Authentication Data */
+    if (aSz != 0 && a != NULL) {
+        blocks = aSz / AES_BLOCK_SIZE;
+        partial = aSz % AES_BLOCK_SIZE;
+        while (blocks--) {
+            xorbuf(x, a, AES_BLOCK_SIZE);
+            GMULT(x, h);
+            a += AES_BLOCK_SIZE;
+        }
+        if (partial != 0) {
+            XMEMSET(scratch, 0, AES_BLOCK_SIZE);
+            XMEMCPY(scratch, a, partial);
+            xorbuf(x, scratch, AES_BLOCK_SIZE);
+            GMULT(x, h);
+        }
+    }
+
+    /* Hash in C, the Ciphertext */
+    if (cSz != 0 && c != NULL) {
+        blocks = cSz / AES_BLOCK_SIZE;
+        partial = cSz % AES_BLOCK_SIZE;
+        while (blocks--) {
+            xorbuf(x, c, AES_BLOCK_SIZE);
+            GMULT(x, h);
+            c += AES_BLOCK_SIZE;
+        }
+        if (partial != 0) {
+            XMEMSET(scratch, 0, AES_BLOCK_SIZE);
+            XMEMCPY(scratch, c, partial);
+            xorbuf(x, scratch, AES_BLOCK_SIZE);
+            GMULT(x, h);
+        }
+    }
+
+    /* Hash in the lengths of A and C in bits */
+    FlattenSzInBits(&scratch[0], aSz);
+    FlattenSzInBits(&scratch[8], cSz);
+    xorbuf(x, scratch, AES_BLOCK_SIZE);
+    GMULT(x, h);
+
+    /* Copy the result into s. */
+    XMEMCPY(s, x, sSz);
+}
+
+/* end GCM_SMALL */
+#elif defined(GCM_TABLE)
+
+static const byte R[256][2] = {
+    {0x00, 0x00}, {0x01, 0xc2}, {0x03, 0x84}, {0x02, 0x46},
+    {0x07, 0x08}, {0x06, 0xca}, {0x04, 0x8c}, {0x05, 0x4e},
+    {0x0e, 0x10}, {0x0f, 0xd2}, {0x0d, 0x94}, {0x0c, 0x56},
+    {0x09, 0x18}, {0x08, 0xda}, {0x0a, 0x9c}, {0x0b, 0x5e},
+    {0x1c, 0x20}, {0x1d, 0xe2}, {0x1f, 0xa4}, {0x1e, 0x66},
+    {0x1b, 0x28}, {0x1a, 0xea}, {0x18, 0xac}, {0x19, 0x6e},
+    {0x12, 0x30}, {0x13, 0xf2}, {0x11, 0xb4}, {0x10, 0x76},
+    {0x15, 0x38}, {0x14, 0xfa}, {0x16, 0xbc}, {0x17, 0x7e},
+    {0x38, 0x40}, {0x39, 0x82}, {0x3b, 0xc4}, {0x3a, 0x06},
+    {0x3f, 0x48}, {0x3e, 0x8a}, {0x3c, 0xcc}, {0x3d, 0x0e},
+    {0x36, 0x50}, {0x37, 0x92}, {0x35, 0xd4}, {0x34, 0x16},
+    {0x31, 0x58}, {0x30, 0x9a}, {0x32, 0xdc}, {0x33, 0x1e},
+    {0x24, 0x60}, {0x25, 0xa2}, {0x27, 0xe4}, {0x26, 0x26},
+    {0x23, 0x68}, {0x22, 0xaa}, {0x20, 0xec}, {0x21, 0x2e},
+    {0x2a, 0x70}, {0x2b, 0xb2}, {0x29, 0xf4}, {0x28, 0x36},
+    {0x2d, 0x78}, {0x2c, 0xba}, {0x2e, 0xfc}, {0x2f, 0x3e},
+    {0x70, 0x80}, {0x71, 0x42}, {0x73, 0x04}, {0x72, 0xc6},
+    {0x77, 0x88}, {0x76, 0x4a}, {0x74, 0x0c}, {0x75, 0xce},
+    {0x7e, 0x90}, {0x7f, 0x52}, {0x7d, 0x14}, {0x7c, 0xd6},
+    {0x79, 0x98}, {0x78, 0x5a}, {0x7a, 0x1c}, {0x7b, 0xde},
+    {0x6c, 0xa0}, {0x6d, 0x62}, {0x6f, 0x24}, {0x6e, 0xe6},
+    {0x6b, 0xa8}, {0x6a, 0x6a}, {0x68, 0x2c}, {0x69, 0xee},
+    {0x62, 0xb0}, {0x63, 0x72}, {0x61, 0x34}, {0x60, 0xf6},
+    {0x65, 0xb8}, {0x64, 0x7a}, {0x66, 0x3c}, {0x67, 0xfe},
+    {0x48, 0xc0}, {0x49, 0x02}, {0x4b, 0x44}, {0x4a, 0x86},
+    {0x4f, 0xc8}, {0x4e, 0x0a}, {0x4c, 0x4c}, {0x4d, 0x8e},
+    {0x46, 0xd0}, {0x47, 0x12}, {0x45, 0x54}, {0x44, 0x96},
+    {0x41, 0xd8}, {0x40, 0x1a}, {0x42, 0x5c}, {0x43, 0x9e},
+    {0x54, 0xe0}, {0x55, 0x22}, {0x57, 0x64}, {0x56, 0xa6},
+    {0x53, 0xe8}, {0x52, 0x2a}, {0x50, 0x6c}, {0x51, 0xae},
+    {0x5a, 0xf0}, {0x5b, 0x32}, {0x59, 0x74}, {0x58, 0xb6},
+    {0x5d, 0xf8}, {0x5c, 0x3a}, {0x5e, 0x7c}, {0x5f, 0xbe},
+    {0xe1, 0x00}, {0xe0, 0xc2}, {0xe2, 0x84}, {0xe3, 0x46},
+    {0xe6, 0x08}, {0xe7, 0xca}, {0xe5, 0x8c}, {0xe4, 0x4e},
+    {0xef, 0x10}, {0xee, 0xd2}, {0xec, 0x94}, {0xed, 0x56},
+    {0xe8, 0x18}, {0xe9, 0xda}, {0xeb, 0x9c}, {0xea, 0x5e},
+    {0xfd, 0x20}, {0xfc, 0xe2}, {0xfe, 0xa4}, {0xff, 0x66},
+    {0xfa, 0x28}, {0xfb, 0xea}, {0xf9, 0xac}, {0xf8, 0x6e},
+    {0xf3, 0x30}, {0xf2, 0xf2}, {0xf0, 0xb4}, {0xf1, 0x76},
+    {0xf4, 0x38}, {0xf5, 0xfa}, {0xf7, 0xbc}, {0xf6, 0x7e},
+    {0xd9, 0x40}, {0xd8, 0x82}, {0xda, 0xc4}, {0xdb, 0x06},
+    {0xde, 0x48}, {0xdf, 0x8a}, {0xdd, 0xcc}, {0xdc, 0x0e},
+    {0xd7, 0x50}, {0xd6, 0x92}, {0xd4, 0xd4}, {0xd5, 0x16},
+    {0xd0, 0x58}, {0xd1, 0x9a}, {0xd3, 0xdc}, {0xd2, 0x1e},
+    {0xc5, 0x60}, {0xc4, 0xa2}, {0xc6, 0xe4}, {0xc7, 0x26},
+    {0xc2, 0x68}, {0xc3, 0xaa}, {0xc1, 0xec}, {0xc0, 0x2e},
+    {0xcb, 0x70}, {0xca, 0xb2}, {0xc8, 0xf4}, {0xc9, 0x36},
+    {0xcc, 0x78}, {0xcd, 0xba}, {0xcf, 0xfc}, {0xce, 0x3e},
+    {0x91, 0x80}, {0x90, 0x42}, {0x92, 0x04}, {0x93, 0xc6},
+    {0x96, 0x88}, {0x97, 0x4a}, {0x95, 0x0c}, {0x94, 0xce},
+    {0x9f, 0x90}, {0x9e, 0x52}, {0x9c, 0x14}, {0x9d, 0xd6},
+    {0x98, 0x98}, {0x99, 0x5a}, {0x9b, 0x1c}, {0x9a, 0xde},
+    {0x8d, 0xa0}, {0x8c, 0x62}, {0x8e, 0x24}, {0x8f, 0xe6},
+    {0x8a, 0xa8}, {0x8b, 0x6a}, {0x89, 0x2c}, {0x88, 0xee},
+    {0x83, 0xb0}, {0x82, 0x72}, {0x80, 0x34}, {0x81, 0xf6},
+    {0x84, 0xb8}, {0x85, 0x7a}, {0x87, 0x3c}, {0x86, 0xfe},
+    {0xa9, 0xc0}, {0xa8, 0x02}, {0xaa, 0x44}, {0xab, 0x86},
+    {0xae, 0xc8}, {0xaf, 0x0a}, {0xad, 0x4c}, {0xac, 0x8e},
+    {0xa7, 0xd0}, {0xa6, 0x12}, {0xa4, 0x54}, {0xa5, 0x96},
+    {0xa0, 0xd8}, {0xa1, 0x1a}, {0xa3, 0x5c}, {0xa2, 0x9e},
+    {0xb5, 0xe0}, {0xb4, 0x22}, {0xb6, 0x64}, {0xb7, 0xa6},
+    {0xb2, 0xe8}, {0xb3, 0x2a}, {0xb1, 0x6c}, {0xb0, 0xae},
+    {0xbb, 0xf0}, {0xba, 0x32}, {0xb8, 0x74}, {0xb9, 0xb6},
+    {0xbc, 0xf8}, {0xbd, 0x3a}, {0xbf, 0x7c}, {0xbe, 0xbe} };
+
+
+static void GMULT(byte *x, byte m[256][AES_BLOCK_SIZE])
+{
+    int i, j;
+    byte Z[AES_BLOCK_SIZE];
+    byte a;
+
+    XMEMSET(Z, 0, sizeof(Z));
+
+    for (i = 15; i > 0; i--) {
+        xorbuf(Z, m[x[i]], AES_BLOCK_SIZE);
+        a = Z[15];
+
+        for (j = 15; j > 0; j--) {
+            Z[j] = Z[j-1];
+        }
+
+        Z[0] = R[a][0];
+        Z[1] ^= R[a][1];
+    }
+    xorbuf(Z, m[x[0]], AES_BLOCK_SIZE);
+
+    XMEMCPY(x, Z, AES_BLOCK_SIZE);
+}
+
+
+static void GHASH(Aes* aes, const byte* a, word32 aSz,
+                                const byte* c, word32 cSz, byte* s, word32 sSz)
+{
+    byte x[AES_BLOCK_SIZE];
+    byte scratch[AES_BLOCK_SIZE];
+    word32 blocks, partial;
+
+    XMEMSET(x, 0, AES_BLOCK_SIZE);
+
+    /* Hash in A, the Additional Authentication Data */
+    if (aSz != 0 && a != NULL) {
+        blocks = aSz / AES_BLOCK_SIZE;
+        partial = aSz % AES_BLOCK_SIZE;
+        while (blocks--) {
+            xorbuf(x, a, AES_BLOCK_SIZE);
+            GMULT(x, aes->M0);
+            a += AES_BLOCK_SIZE;
+        }
+        if (partial != 0) {
+            XMEMSET(scratch, 0, AES_BLOCK_SIZE);
+            XMEMCPY(scratch, a, partial);
+            xorbuf(x, scratch, AES_BLOCK_SIZE);
+            GMULT(x, aes->M0);
+        }
+    }
+
+    /* Hash in C, the Ciphertext */
+    if (cSz != 0 && c != NULL) {
+        blocks = cSz / AES_BLOCK_SIZE;
+        partial = cSz % AES_BLOCK_SIZE;
+        while (blocks--) {
+            xorbuf(x, c, AES_BLOCK_SIZE);
+            GMULT(x, aes->M0);
+            c += AES_BLOCK_SIZE;
+        }
+        if (partial != 0) {
+            XMEMSET(scratch, 0, AES_BLOCK_SIZE);
+            XMEMCPY(scratch, c, partial);
+            xorbuf(x, scratch, AES_BLOCK_SIZE);
+            GMULT(x, aes->M0);
+        }
+    }
+
+    /* Hash in the lengths of A and C in bits */
+    FlattenSzInBits(&scratch[0], aSz);
+    FlattenSzInBits(&scratch[8], cSz);
+    xorbuf(x, scratch, AES_BLOCK_SIZE);
+    GMULT(x, aes->M0);
+
+    /* Copy the result into s. */
+    XMEMCPY(s, x, sSz);
+}
+
+/* end GCM_TABLE */
+#elif defined(WORD64_AVAILABLE) && !defined(GCM_WORD32)
+
+static void GMULT(word64* X, word64* Y)
+{
+    word64 Z[2] = {0,0};
+    word64 V[2] ; 
+    int i, j;
+    V[0] = X[0] ;  V[1] = X[1] ;
+
+    for (i = 0; i < 2; i++)
+    {
+        word64 y = Y[i];
+        for (j = 0; j < 64; j++)
+        {
+            if (y & 0x8000000000000000ULL) {
+                Z[0] ^= V[0];
+                Z[1] ^= V[1];
+            }
+
+            if (V[1] & 0x0000000000000001) {
+                V[1] >>= 1;
+                V[1] |= ((V[0] & 0x0000000000000001) ? 0x8000000000000000ULL : 0);
+                V[0] >>= 1;
+                V[0] ^= 0xE100000000000000ULL;
+            }
+            else {
+                V[1] >>= 1;
+                V[1] |= ((V[0] & 0x0000000000000001) ? 0x8000000000000000ULL : 0);
+                V[0] >>= 1;
+            }
+            y <<= 1;
+        }
+    }
+    X[0] = Z[0];
+    X[1] = Z[1];
+}
+
+
+static void GHASH(Aes* aes, const byte* a, word32 aSz,
+                                const byte* c, word32 cSz, byte* s, word32 sSz)
+{
+    word64 x[2] = {0,0};
+    word32 blocks, partial;
+    word64 bigH[2];
+
+    XMEMCPY(bigH, aes->H, AES_BLOCK_SIZE);
+    #ifdef LITTLE_ENDIAN_ORDER
+        ByteReverseWords64(bigH, bigH, AES_BLOCK_SIZE); 
+    #endif
+
+    /* Hash in A, the Additional Authentication Data */
+    if (aSz != 0 && a != NULL) {
+        word64 bigA[2];
+        blocks = aSz / AES_BLOCK_SIZE;
+        partial = aSz % AES_BLOCK_SIZE;
+        while (blocks--) {
+            XMEMCPY(bigA, a, AES_BLOCK_SIZE);
+            #ifdef LITTLE_ENDIAN_ORDER
+                ByteReverseWords64(bigA, bigA, AES_BLOCK_SIZE);
+            #endif
+            x[0] ^= bigA[0];
+            x[1] ^= bigA[1];
+            GMULT(x, bigH);
+            a += AES_BLOCK_SIZE;
+        }
+        if (partial != 0) {
+            XMEMSET(bigA, 0, AES_BLOCK_SIZE);
+            XMEMCPY(bigA, a, partial);
+            #ifdef LITTLE_ENDIAN_ORDER
+                ByteReverseWords64(bigA, bigA, AES_BLOCK_SIZE);
+            #endif
+            x[0] ^= bigA[0];
+            x[1] ^= bigA[1];
+            GMULT(x, bigH);
+        }
+    }
+
+    /* Hash in C, the Ciphertext */
+    if (cSz != 0 && c != NULL) {
+        word64 bigC[2];
+        blocks = cSz / AES_BLOCK_SIZE;
+        partial = cSz % AES_BLOCK_SIZE;
+        while (blocks--) {
+            XMEMCPY(bigC, c, AES_BLOCK_SIZE);
+            #ifdef LITTLE_ENDIAN_ORDER
+                ByteReverseWords64(bigC, bigC, AES_BLOCK_SIZE);
+            #endif
+            x[0] ^= bigC[0];
+            x[1] ^= bigC[1];
+            GMULT(x, bigH);
+            c += AES_BLOCK_SIZE;
+        }
+        if (partial != 0) {
+            XMEMSET(bigC, 0, AES_BLOCK_SIZE);
+            XMEMCPY(bigC, c, partial);
+            #ifdef LITTLE_ENDIAN_ORDER
+                ByteReverseWords64(bigC, bigC, AES_BLOCK_SIZE);
+            #endif
+            x[0] ^= bigC[0];
+            x[1] ^= bigC[1];
+            GMULT(x, bigH);
+        }
+    }
+
+    /* Hash in the lengths in bits of A and C */
+    {
+        word64 len[2] ; 
+        len[0] = aSz ; len[1] = cSz;
+
+        /* Lengths are in bytes. Convert to bits. */
+        len[0] *= 8;
+        len[1] *= 8;
+
+        x[0] ^= len[0];
+        x[1] ^= len[1];
+        GMULT(x, bigH);
+    }
+    #ifdef LITTLE_ENDIAN_ORDER
+        ByteReverseWords64(x, x, AES_BLOCK_SIZE);
+    #endif
+    XMEMCPY(s, x, sSz);
+}
+
+/* end defined(WORD64_AVAILABLE) && !defined(GCM_WORD32) */
+#else /* GCM_WORD32 */
+
+static void GMULT(word32* X, word32* Y)
+{
+    word32 Z[4] = {0,0,0,0};
+    word32 V[4] ;
+    int i, j;
+
+    V[0] = X[0];  V[1] = X[1]; V[2] =  X[2]; V[3] =  X[3];
+
+    for (i = 0; i < 4; i++)
+    {
+        word32 y = Y[i];
+        for (j = 0; j < 32; j++)
+        {
+            if (y & 0x80000000) {
+                Z[0] ^= V[0];
+                Z[1] ^= V[1];
+                Z[2] ^= V[2];
+                Z[3] ^= V[3];
+            }
+
+            if (V[3] & 0x00000001) {
+                V[3] >>= 1;
+                V[3] |= ((V[2] & 0x00000001) ? 0x80000000 : 0);
+                V[2] >>= 1;
+                V[2] |= ((V[1] & 0x00000001) ? 0x80000000 : 0);
+                V[1] >>= 1;
+                V[1] |= ((V[0] & 0x00000001) ? 0x80000000 : 0);
+                V[0] >>= 1;
+                V[0] ^= 0xE1000000;
+            } else {
+                V[3] >>= 1;
+                V[3] |= ((V[2] & 0x00000001) ? 0x80000000 : 0);
+                V[2] >>= 1;
+                V[2] |= ((V[1] & 0x00000001) ? 0x80000000 : 0);
+                V[1] >>= 1;
+                V[1] |= ((V[0] & 0x00000001) ? 0x80000000 : 0);
+                V[0] >>= 1;
+            }
+            y <<= 1;
+        }
+    }
+    X[0] = Z[0];
+    X[1] = Z[1];
+    X[2] = Z[2];
+    X[3] = Z[3];
+}
+
+
+static void GHASH(Aes* aes, const byte* a, word32 aSz,
+                                const byte* c, word32 cSz, byte* s, word32 sSz)
+{
+    word32 x[4] = {0,0,0,0};
+    word32 blocks, partial;
+    word32 bigH[4];
+
+    XMEMCPY(bigH, aes->H, AES_BLOCK_SIZE);
+    #ifdef LITTLE_ENDIAN_ORDER
+        ByteReverseWords(bigH, bigH, AES_BLOCK_SIZE);
+    #endif
+
+    /* Hash in A, the Additional Authentication Data */
+    if (aSz != 0 && a != NULL) {
+        word32 bigA[4];
+        blocks = aSz / AES_BLOCK_SIZE;
+        partial = aSz % AES_BLOCK_SIZE;
+        while (blocks--) {
+            XMEMCPY(bigA, a, AES_BLOCK_SIZE);
+            #ifdef LITTLE_ENDIAN_ORDER
+                ByteReverseWords(bigA, bigA, AES_BLOCK_SIZE);
+            #endif
+            x[0] ^= bigA[0];
+            x[1] ^= bigA[1];
+            x[2] ^= bigA[2];
+            x[3] ^= bigA[3];
+            GMULT(x, bigH);
+            a += AES_BLOCK_SIZE;
+        }
+        if (partial != 0) {
+            XMEMSET(bigA, 0, AES_BLOCK_SIZE);
+            XMEMCPY(bigA, a, partial);
+            #ifdef LITTLE_ENDIAN_ORDER
+                ByteReverseWords(bigA, bigA, AES_BLOCK_SIZE);
+            #endif
+            x[0] ^= bigA[0];
+            x[1] ^= bigA[1];
+            x[2] ^= bigA[2];
+            x[3] ^= bigA[3];
+            GMULT(x, bigH);
+        }
+    }
+
+    /* Hash in C, the Ciphertext */
+    if (cSz != 0 && c != NULL) {
+        word32 bigC[4];
+        blocks = cSz / AES_BLOCK_SIZE;
+        partial = cSz % AES_BLOCK_SIZE;
+        while (blocks--) {
+            XMEMCPY(bigC, c, AES_BLOCK_SIZE);
+            #ifdef LITTLE_ENDIAN_ORDER
+                ByteReverseWords(bigC, bigC, AES_BLOCK_SIZE);
+            #endif
+            x[0] ^= bigC[0];
+            x[1] ^= bigC[1];
+            x[2] ^= bigC[2];
+            x[3] ^= bigC[3];
+            GMULT(x, bigH);
+            c += AES_BLOCK_SIZE;
+        }
+        if (partial != 0) {
+            XMEMSET(bigC, 0, AES_BLOCK_SIZE);
+            XMEMCPY(bigC, c, partial);
+            #ifdef LITTLE_ENDIAN_ORDER
+                ByteReverseWords(bigC, bigC, AES_BLOCK_SIZE);
+            #endif
+            x[0] ^= bigC[0];
+            x[1] ^= bigC[1];
+            x[2] ^= bigC[2];
+            x[3] ^= bigC[3];
+            GMULT(x, bigH);
+        }
+    }
+
+    /* Hash in the lengths in bits of A and C */
+    {
+        word32 len[4];
+
+        /* Lengths are in bytes. Convert to bits. */
+        len[0] = (aSz >> (8*sizeof(aSz) - 3));
+        len[1] = aSz << 3;
+        len[2] = (cSz >> (8*sizeof(cSz) - 3));
+        len[3] = cSz << 3;
+
+        x[0] ^= len[0];
+        x[1] ^= len[1];
+        x[2] ^= len[2];
+        x[3] ^= len[3];
+        GMULT(x, bigH);
+    }
+    #ifdef LITTLE_ENDIAN_ORDER
+        ByteReverseWords(x, x, AES_BLOCK_SIZE);
+    #endif
+    XMEMCPY(s, x, sSz);
+}
+
+#endif /* end GCM_WORD32 */
+
+
+int wc_AesGcmEncrypt(Aes* aes, byte* out, const byte* in, word32 sz,
+                   const byte* iv, word32 ivSz,
+                   byte* authTag, word32 authTagSz,
+                   const byte* authIn, word32 authInSz)
+{
+    word32 blocks = sz / AES_BLOCK_SIZE;
+    word32 partial = sz % AES_BLOCK_SIZE;
+    const byte* p = in;
+    byte* c = out;
+    byte counter[AES_BLOCK_SIZE];
+    byte *ctr ;
+    byte scratch[AES_BLOCK_SIZE];
+
+#ifdef FREESCALE_MMCAU
+    byte* key = (byte*)aes->key;
+#endif
+
+    WOLFSSL_ENTER("AesGcmEncrypt");
+
+#ifdef WOLFSSL_PIC32MZ_CRYPT
+    ctr = (char *)aes->iv_ce ;
+#else
+    ctr = counter ;
+#endif
+
+    XMEMSET(ctr, 0, AES_BLOCK_SIZE);
+    XMEMCPY(ctr, iv, ivSz);
+    InitGcmCounter(ctr);
+
+#ifdef WOLFSSL_PIC32MZ_CRYPT
+    if(blocks)
+        wc_AesCrypt(aes, out, in, blocks*AES_BLOCK_SIZE,
+             PIC32_ENCRYPTION, PIC32_ALGO_AES, PIC32_CRYPTOALGO_AES_GCM );
+#endif
+    while (blocks--) {
+        IncrementGcmCounter(ctr);
+        #ifndef WOLFSSL_PIC32MZ_CRYPT
+            #ifdef FREESCALE_MMCAU
+                cau_aes_encrypt(ctr, key, aes->rounds, scratch);
+            #else
+                wc_AesEncrypt(aes, ctr, scratch);
+            #endif
+        xorbuf(scratch, p, AES_BLOCK_SIZE);
+        XMEMCPY(c, scratch, AES_BLOCK_SIZE);
+        #endif
+        p += AES_BLOCK_SIZE;
+        c += AES_BLOCK_SIZE;
+    }
+
+    if (partial != 0) {
+        IncrementGcmCounter(ctr);
+        #ifdef FREESCALE_MMCAU
+            cau_aes_encrypt(ctr, key, aes->rounds, scratch);
+        #else
+            wc_AesEncrypt(aes, ctr, scratch);
+        #endif
+        xorbuf(scratch, p, partial);
+        XMEMCPY(c, scratch, partial);
+
+    }
+
+    GHASH(aes, authIn, authInSz, out, sz, authTag, authTagSz);
+    InitGcmCounter(ctr);
+    #ifdef FREESCALE_MMCAU
+        cau_aes_encrypt(ctr, key, aes->rounds, scratch);
+    #else
+        wc_AesEncrypt(aes, ctr, scratch);
+    #endif
+    xorbuf(authTag, scratch, authTagSz);
+
+    return 0;
+}
+
+
+int  wc_AesGcmDecrypt(Aes* aes, byte* out, const byte* in, word32 sz,
+                   const byte* iv, word32 ivSz,
+                   const byte* authTag, word32 authTagSz,
+                   const byte* authIn, word32 authInSz)
+{
+    word32 blocks = sz / AES_BLOCK_SIZE;
+    word32 partial = sz % AES_BLOCK_SIZE;
+    const byte* c = in;
+    byte* p = out;
+    byte counter[AES_BLOCK_SIZE];
+    byte *ctr ;
+    byte scratch[AES_BLOCK_SIZE];
+
+#ifdef FREESCALE_MMCAU
+    byte* key = (byte*)aes->key;
+#endif
+
+    WOLFSSL_ENTER("AesGcmDecrypt");
+
+#ifdef WOLFSSL_PIC32MZ_CRYPT
+    ctr = (char *)aes->iv_ce ;
+#else
+    ctr = counter ;
+#endif
+
+    XMEMSET(ctr, 0, AES_BLOCK_SIZE);
+    XMEMCPY(ctr, iv, ivSz);
+    InitGcmCounter(ctr);
+
+    /* Calculate the authTag again using the received auth data and the
+     * cipher text. */
+    {
+        byte Tprime[AES_BLOCK_SIZE];
+        byte EKY0[AES_BLOCK_SIZE];
+
+        GHASH(aes, authIn, authInSz, in, sz, Tprime, sizeof(Tprime));
+        #ifdef FREESCALE_MMCAU
+            cau_aes_encrypt(ctr, key, aes->rounds, EKY0);
+        #else
+            wc_AesEncrypt(aes, ctr, EKY0);
+        #endif
+        xorbuf(Tprime, EKY0, sizeof(Tprime));
+
+        if (ConstantCompare(authTag, Tprime, authTagSz) != 0) {
+            return AES_GCM_AUTH_E;
+        }
+    }
+
+#ifdef WOLFSSL_PIC32MZ_CRYPT
+    if(blocks)
+        wc_AesCrypt(aes, out, in, blocks*AES_BLOCK_SIZE,
+             PIC32_DECRYPTION, PIC32_ALGO_AES, PIC32_CRYPTOALGO_AES_GCM );
+#endif
+
+    while (blocks--) {
+        IncrementGcmCounter(ctr);
+        #ifndef WOLFSSL_PIC32MZ_CRYPT
+            #ifdef FREESCALE_MMCAU
+                cau_aes_encrypt(ctr, key, aes->rounds, scratch);
+            #else
+                wc_AesEncrypt(aes, ctr, scratch);
+            #endif
+        xorbuf(scratch, c, AES_BLOCK_SIZE);
+        XMEMCPY(p, scratch, AES_BLOCK_SIZE);
+        #endif
+        p += AES_BLOCK_SIZE;
+        c += AES_BLOCK_SIZE;
+    }
+    if (partial != 0) {
+        IncrementGcmCounter(ctr);
+        #ifdef FREESCALE_MMCAU
+            cau_aes_encrypt(ctr, key, aes->rounds, scratch);
+        #else
+            wc_AesEncrypt(aes, ctr, scratch);
+        #endif
+        xorbuf(scratch, c, partial);
+        XMEMCPY(p, scratch, partial);
+    }
+    return 0;
+}
+
+
+
+WOLFSSL_API int wc_GmacSetKey(Gmac* gmac, const byte* key, word32 len)
+{
+    return wc_AesGcmSetKey(&gmac->aes, key, len);
+}
+
+
+WOLFSSL_API int wc_GmacUpdate(Gmac* gmac, const byte* iv, word32 ivSz,
+                              const byte* authIn, word32 authInSz,
+                              byte* authTag, word32 authTagSz)
+{
+    return wc_AesGcmEncrypt(&gmac->aes, NULL, NULL, 0, iv, ivSz,
+                                         authTag, authTagSz, authIn, authInSz);
+}
+
+#endif /* HAVE_AESGCM */
+
+
+#ifdef HAVE_AESCCM
+
+#ifdef STM32F2_CRYPTO
+    #error "STM32F2 crypto doesn't currently support AES-CCM mode"
+
+#elif defined(HAVE_COLDFIRE_SEC)
+    #error "Coldfire SEC doesn't currently support AES-CCM mode"
+
+#elif defined(WOLFSSL_PIC32MZ_CRYPT)
+    #error "PIC32MZ doesn't currently support AES-CCM mode"
+
+#endif
+
+void wc_AesCcmSetKey(Aes* aes, const byte* key, word32 keySz)
+{
+    byte nonce[AES_BLOCK_SIZE];
+
+    if (!((keySz == 16) || (keySz == 24) || (keySz == 32)))
+        return;
+
+    XMEMSET(nonce, 0, sizeof(nonce));
+    wc_AesSetKey(aes, key, keySz, nonce, AES_ENCRYPTION);
+}
+
+
+static void roll_x(Aes* aes, const byte* in, word32 inSz, byte* out)
+{
+    #ifdef FREESCALE_MMCAU
+        byte* key = (byte*)aes->key;
+    #endif
+
+    /* process the bulk of the data */
+    while (inSz >= AES_BLOCK_SIZE) {
+        xorbuf(out, in, AES_BLOCK_SIZE);
+        in += AES_BLOCK_SIZE;
+        inSz -= AES_BLOCK_SIZE;
+
+        #ifdef FREESCALE_MMCAU
+            cau_aes_encrypt(out, key, aes->rounds, out);
+        #else
+            wc_AesEncrypt(aes, out, out);
+        #endif
+    }
+
+    /* process remainder of the data */
+    if (inSz > 0) {
+        xorbuf(out, in, inSz);
+        #ifdef FREESCALE_MMCAU
+            cau_aes_encrypt(out, key, aes->rounds, out);
+        #else
+            wc_AesEncrypt(aes, out, out);
+        #endif
+    }
+}
+
+
+static void roll_auth(Aes* aes, const byte* in, word32 inSz, byte* out)
+{
+    word32 authLenSz;
+    word32 remainder;
+
+    #ifdef FREESCALE_MMCAU
+        byte* key = (byte*)aes->key;
+    #endif
+
+    /* encode the length in */
+    if (inSz <= 0xFEFF) {
+        authLenSz = 2;
+        out[0] ^= ((inSz & 0xFF00) >> 8);
+        out[1] ^=  (inSz & 0x00FF);
+    }
+    else if (inSz <= 0xFFFFFFFF) {
+        authLenSz = 6;
+        out[0] ^= 0xFF; out[1] ^= 0xFE;
+        out[2] ^= ((inSz & 0xFF000000) >> 24);
+        out[3] ^= ((inSz & 0x00FF0000) >> 16);
+        out[4] ^= ((inSz & 0x0000FF00) >>  8);
+        out[5] ^=  (inSz & 0x000000FF);
+    }
+    /* Note, the protocol handles auth data up to 2^64, but we are
+     * using 32-bit sizes right now, so the bigger data isn't handled
+     * else if (inSz <= 0xFFFFFFFFFFFFFFFF) {} */
+    else
+        return;
+
+    /* start fill out the rest of the first block */
+    remainder = AES_BLOCK_SIZE - authLenSz;
+    if (inSz >= remainder) {
+        /* plenty of bulk data to fill the remainder of this block */
+        xorbuf(out + authLenSz, in, remainder);
+        inSz -= remainder;
+        in += remainder;
+    }
+    else {
+        /* not enough bulk data, copy what is available, and pad zero */
+        xorbuf(out + authLenSz, in, inSz);
+        inSz = 0;
+    }
+    #ifdef FREESCALE_MMCAU
+        cau_aes_encrypt(out, key, aes->rounds, out);
+    #else
+        wc_AesEncrypt(aes, out, out);
+    #endif
+
+    if (inSz > 0)
+        roll_x(aes, in, inSz, out);
+}
+
+
+static INLINE void AesCcmCtrInc(byte* B, word32 lenSz)
+{
+    word32 i;
+
+    for (i = 0; i < lenSz; i++) {
+        if (++B[AES_BLOCK_SIZE - 1 - i] != 0) return;
+    }
+}
+
+
+void wc_AesCcmEncrypt(Aes* aes, byte* out, const byte* in, word32 inSz,
+                   const byte* nonce, word32 nonceSz,
+                   byte* authTag, word32 authTagSz,
+                   const byte* authIn, word32 authInSz)
+{
+    byte A[AES_BLOCK_SIZE];
+    byte B[AES_BLOCK_SIZE];
+    byte lenSz;
+    word32 i;
+
+    #ifdef FREESCALE_MMCAU
+        byte* key = (byte*)aes->key;
+    #endif
+
+    XMEMCPY(B+1, nonce, nonceSz);
+    lenSz = AES_BLOCK_SIZE - 1 - (byte)nonceSz;
+    B[0] = (authInSz > 0 ? 64 : 0)
+         + (8 * (((byte)authTagSz - 2) / 2))
+         + (lenSz - 1);
+    for (i = 0; i < lenSz; i++)
+        B[AES_BLOCK_SIZE - 1 - i] = (inSz >> (8 * i)) & 0xFF;
+
+    #ifdef FREESCALE_MMCAU
+        cau_aes_encrypt(B, key, aes->rounds, A);
+    #else
+        wc_AesEncrypt(aes, B, A);
+    #endif
+    if (authInSz > 0)
+        roll_auth(aes, authIn, authInSz, A);
+    if (inSz > 0)
+        roll_x(aes, in, inSz, A);
+    XMEMCPY(authTag, A, authTagSz);
+
+    B[0] = lenSz - 1;
+    for (i = 0; i < lenSz; i++)
+        B[AES_BLOCK_SIZE - 1 - i] = 0;
+    #ifdef FREESCALE_MMCAU
+        cau_aes_encrypt(B, key, aes->rounds, A);
+    #else
+        wc_AesEncrypt(aes, B, A);
+    #endif
+    xorbuf(authTag, A, authTagSz);
+
+    B[15] = 1;
+    while (inSz >= AES_BLOCK_SIZE) {
+        #ifdef FREESCALE_MMCAU
+            cau_aes_encrypt(B, key, aes->rounds, A);
+        #else
+            wc_AesEncrypt(aes, B, A);
+        #endif
+        xorbuf(A, in, AES_BLOCK_SIZE);
+        XMEMCPY(out, A, AES_BLOCK_SIZE);
+
+        AesCcmCtrInc(B, lenSz);
+        inSz -= AES_BLOCK_SIZE;
+        in += AES_BLOCK_SIZE;
+        out += AES_BLOCK_SIZE;
+    }
+    if (inSz > 0) {
+        #ifdef FREESCALE_MMCAU
+            cau_aes_encrypt(B, key, aes->rounds, A);
+        #else
+            wc_AesEncrypt(aes, B, A);
+        #endif
+        xorbuf(A, in, inSz);
+        XMEMCPY(out, A, inSz);
+    }
+
+    ForceZero(A, AES_BLOCK_SIZE);
+    ForceZero(B, AES_BLOCK_SIZE);
+}
+
+
+int  wc_AesCcmDecrypt(Aes* aes, byte* out, const byte* in, word32 inSz,
+                   const byte* nonce, word32 nonceSz,
+                   const byte* authTag, word32 authTagSz,
+                   const byte* authIn, word32 authInSz)
+{
+    byte A[AES_BLOCK_SIZE];
+    byte B[AES_BLOCK_SIZE];
+    byte* o;
+    byte lenSz;
+    word32 i, oSz;
+    int result = 0;
+
+    #ifdef FREESCALE_MMCAU
+        byte* key = (byte*)aes->key;
+    #endif
+
+    o = out;
+    oSz = inSz;
+    XMEMCPY(B+1, nonce, nonceSz);
+    lenSz = AES_BLOCK_SIZE - 1 - (byte)nonceSz;
+
+    B[0] = lenSz - 1;
+    for (i = 0; i < lenSz; i++)
+        B[AES_BLOCK_SIZE - 1 - i] = 0;
+    B[15] = 1;
+
+    while (oSz >= AES_BLOCK_SIZE) {
+        #ifdef FREESCALE_MMCAU
+            cau_aes_encrypt(B, key, aes->rounds, A);
+        #else
+            wc_AesEncrypt(aes, B, A);
+        #endif
+        xorbuf(A, in, AES_BLOCK_SIZE);
+        XMEMCPY(o, A, AES_BLOCK_SIZE);
+
+        AesCcmCtrInc(B, lenSz);
+        oSz -= AES_BLOCK_SIZE;
+        in += AES_BLOCK_SIZE;
+        o += AES_BLOCK_SIZE;
+    }
+    if (inSz > 0) {
+        #ifdef FREESCALE_MMCAU
+            cau_aes_encrypt(B, key, aes->rounds, A);
+        #else
+            wc_AesEncrypt(aes, B, A);
+        #endif
+        xorbuf(A, in, oSz);
+        XMEMCPY(o, A, oSz);
+    }
+
+    for (i = 0; i < lenSz; i++)
+        B[AES_BLOCK_SIZE - 1 - i] = 0;
+    #ifdef FREESCALE_MMCAU
+        cau_aes_encrypt(B, key, aes->rounds, A);
+    #else
+        wc_AesEncrypt(aes, B, A);
+    #endif
+
+    o = out;
+    oSz = inSz;
+
+    B[0] = (authInSz > 0 ? 64 : 0)
+         + (8 * (((byte)authTagSz - 2) / 2))
+         + (lenSz - 1);
+    for (i = 0; i < lenSz; i++)
+        B[AES_BLOCK_SIZE - 1 - i] = (inSz >> (8 * i)) & 0xFF;
+
+    #ifdef FREESCALE_MMCAU
+        cau_aes_encrypt(B, key, aes->rounds, A);
+    #else
+        wc_AesEncrypt(aes, B, A);
+    #endif
+    if (authInSz > 0)
+        roll_auth(aes, authIn, authInSz, A);
+    if (inSz > 0)
+        roll_x(aes, o, oSz, A);
+
+    B[0] = lenSz - 1;
+    for (i = 0; i < lenSz; i++)
+        B[AES_BLOCK_SIZE - 1 - i] = 0;
+    #ifdef FREESCALE_MMCAU
+        cau_aes_encrypt(B, key, aes->rounds, B);
+    #else
+        wc_AesEncrypt(aes, B, B);
+    #endif
+    xorbuf(A, B, authTagSz);
+
+    if (ConstantCompare(A, authTag, authTagSz) != 0) {
+        /* If the authTag check fails, don't keep the decrypted data.
+         * Unfortunately, you need the decrypted data to calculate the
+         * check value. */
+        XMEMSET(out, 0, inSz);
+        result = AES_CCM_AUTH_E;
+    }
+
+    ForceZero(A, AES_BLOCK_SIZE);
+    ForceZero(B, AES_BLOCK_SIZE);
+    o = NULL;
+
+    return result;
+}
+
+#endif /* HAVE_AESCCM */
+
+
+#ifdef HAVE_CAVIUM
+
+#include 
+#include "cavium_common.h"
+
+/* Initiliaze Aes for use with Nitrox device */
+int wc_AesInitCavium(Aes* aes, int devId)
+{
+    if (aes == NULL)
+        return -1;
+
+    if (CspAllocContext(CONTEXT_SSL, &aes->contextHandle, devId) != 0)
+        return -1;
+
+    aes->devId = devId;
+    aes->magic = WOLFSSL_AES_CAVIUM_MAGIC;
+
+    return 0;
+}
+
+
+/* Free Aes from use with Nitrox device */
+void wc_AesFreeCavium(Aes* aes)
+{
+    if (aes == NULL)
+        return;
+
+    if (aes->magic != WOLFSSL_AES_CAVIUM_MAGIC)
+        return;
+
+    CspFreeContext(CONTEXT_SSL, aes->contextHandle, aes->devId);
+    aes->magic = 0;
+}
+
+
+static int wc_AesCaviumSetKey(Aes* aes, const byte* key, word32 length,
+                           const byte* iv)
+{
+    if (aes == NULL)
+        return -1;
+
+    XMEMCPY(aes->key, key, length);   /* key still holds key, iv still in reg */
+    if (length == 16)
+        aes->type = AES_128;
+    else if (length == 24)
+        aes->type = AES_192;
+    else if (length == 32)
+        aes->type = AES_256;
+
+    return wc_AesSetIV(aes, iv);
+}
+
+
+static int AesCaviumCbcEncrypt(Aes* aes, byte* out, const byte* in,
+                               word32 length)
+{
+    wolfssl_word offset = 0;
+    word32 requestId;
+
+    while (length > WOLFSSL_MAX_16BIT) {
+        word16 slen = (word16)WOLFSSL_MAX_16BIT;
+        if (CspEncryptAes(CAVIUM_BLOCKING, aes->contextHandle, CAVIUM_NO_UPDATE,
+                          aes->type, slen, (byte*)in + offset, out + offset,
+                          (byte*)aes->reg, (byte*)aes->key, &requestId,
+                          aes->devId) != 0) {
+            WOLFSSL_MSG("Bad Cavium Aes Encrypt");
+            return -1;
+        }
+        length -= WOLFSSL_MAX_16BIT;
+        offset += WOLFSSL_MAX_16BIT;
+        XMEMCPY(aes->reg, out + offset - AES_BLOCK_SIZE, AES_BLOCK_SIZE);
+    }
+    if (length) {
+        word16 slen = (word16)length;
+        if (CspEncryptAes(CAVIUM_BLOCKING, aes->contextHandle, CAVIUM_NO_UPDATE,
+                          aes->type, slen, (byte*)in + offset, out + offset,
+                          (byte*)aes->reg, (byte*)aes->key, &requestId,
+                          aes->devId) != 0) {
+            WOLFSSL_MSG("Bad Cavium Aes Encrypt");
+            return -1;
+        }
+        XMEMCPY(aes->reg, out + offset+length - AES_BLOCK_SIZE, AES_BLOCK_SIZE);
+    }
+    return 0;
+}
+
+static int AesCaviumCbcDecrypt(Aes* aes, byte* out, const byte* in,
+                               word32 length)
+{
+    word32 requestId;
+    wolfssl_word offset = 0;
+
+    while (length > WOLFSSL_MAX_16BIT) {
+        word16 slen = (word16)WOLFSSL_MAX_16BIT;
+        XMEMCPY(aes->tmp, in + offset + slen - AES_BLOCK_SIZE, AES_BLOCK_SIZE);
+        if (CspDecryptAes(CAVIUM_BLOCKING, aes->contextHandle, CAVIUM_NO_UPDATE,
+                          aes->type, slen, (byte*)in + offset, out + offset,
+                          (byte*)aes->reg, (byte*)aes->key, &requestId,
+                          aes->devId) != 0) {
+            WOLFSSL_MSG("Bad Cavium Aes Decrypt");
+            return -1;
+        }
+        length -= WOLFSSL_MAX_16BIT;
+        offset += WOLFSSL_MAX_16BIT;
+        XMEMCPY(aes->reg, aes->tmp, AES_BLOCK_SIZE);
+    }
+    if (length) {
+        word16 slen = (word16)length;
+        XMEMCPY(aes->tmp, in + offset + slen - AES_BLOCK_SIZE, AES_BLOCK_SIZE);
+        if (CspDecryptAes(CAVIUM_BLOCKING, aes->contextHandle, CAVIUM_NO_UPDATE,
+                          aes->type, slen, (byte*)in + offset, out + offset,
+                          (byte*)aes->reg, (byte*)aes->key, &requestId,
+                          aes->devId) != 0) {
+            WOLFSSL_MSG("Bad Cavium Aes Decrypt");
+            return -1;
+        }
+        XMEMCPY(aes->reg, aes->tmp, AES_BLOCK_SIZE);
+    }
+    return 0;
+}
+
+#endif /* HAVE_CAVIUM */
+
+#endif /* WOLFSSL_TI_CRYPT */
+
+#endif /* HAVE_FIPS */
+
+#endif /* NO_AES */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/aes_asm.asm b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/aes_asm.asm
new file mode 100644
index 0000000..1e3d2d9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/aes_asm.asm
@@ -0,0 +1,972 @@
+;	/*aes_asm . asm
+;	*
+;	*Copyright[C]2006	-2014	wolfSSL	Inc	.
+;	*
+;	*This	file	is	part	of	wolfssl. (formerly known as CyaSSL)
+;	*
+;	*wolfSSL	is	free	software/ you can redistribute it and/or modify
+;	*it	under	the	terms	of	the	GNU	General	Public	License	as	published	by
+;	*the	Free	Software	Foundation/ either version 2 of the License, or
+;	*[at	your	option]any	later	version	.
+;	*
+;	*wolfSSL	,is	distributed	in	the	hope	that	it	will	be	useful
+;	*but	WITHOUT	ANY	WARRANTY/ without even the implied warranty of
+;	*MERCHANTABILITY	or	FITNESS	FOR	A	PARTICULAR	PURPOSE	.	See	the
+;	*GNU	General	Public	License	for	more	details	.
+;	*
+;	*You	should	have	received	a	copy	of	the	GNU	General	Public	License
+;	*along	with	this	program/ if not, write to the Free Software
+;	*Foundation,Inc	.,51	Franklin	Street,Fifth	Floor,Boston,MA	02110-1301,USA
+;	*/
+;
+;
+;	/*See	IntelA	dvanced	Encryption	Standard[AES]Instructions	Set	White	Paper
+;	*by	Israel,Intel	Mobility	Group	Development	Center,Israel	Shay	Gueron
+;	*/
+;
+;   /* This file is in intel asm syntax, see .s for at&t syntax */
+;
+;	/*
+;	AES_CBC_encrypt[const	,unsigned	char*in
+;	unsigned	,char*out
+;	unsigned	,char	ivec+16
+;	unsigned	,long	length
+;	const	,unsigned	char*KS
+;	int	nr]
+;	*/
+_text SEGMENT
+AES_CBC_encrypt PROC
+;#	parameter	1:	rdi
+;#	parameter	2:	rsi
+;#	parameter	3:	rdx
+;#	parameter	4:	rcx
+;#	parameter	5:	r8
+;#	parameter	6:	r9d
+
+; save rdi and rsi to rax and r11, restore before ret
+	mov rax,rdi
+	mov r11,rsi
+
+; convert to what we had for att&t convention
+	mov rdi,rcx
+	mov rsi,rdx
+	mov rdx,r8
+	mov rcx,r9
+	mov r8,[rsp+40]
+	mov r9d,[rsp+48]
+
+	mov	r10,rcx
+	shr	rcx,4
+	shl	r10,60
+	je	NO_PARTS
+	add	rcx,1
+NO_PARTS:
+	sub	rsi,16
+	movdqa	xmm1,[rdx]
+LOOP_1:
+	pxor	xmm1,[rdi]
+	pxor	xmm1,[r8]
+	add	rsi,16
+	add	rdi,16
+	cmp	r9d,12
+	aesenc	xmm1,16[r8]
+	aesenc	xmm1,32[r8]
+	aesenc	xmm1,48[r8]
+	aesenc	xmm1,64[r8]
+	aesenc	xmm1,80[r8]
+	aesenc	xmm1,96[r8]
+	aesenc	xmm1,112[r8]
+	aesenc	xmm1,128[r8]
+	aesenc	xmm1,144[r8]
+	movdqa	xmm2,160[r8]
+	jb	LAST
+	cmp	r9d,14
+
+	aesenc	xmm1,160[r8]
+	aesenc	xmm1,176[r8]
+	movdqa	xmm2,192[r8]
+	jb	LAST
+	aesenc	xmm1,192[r8]
+	aesenc	xmm1,208[r8]
+	movdqa	xmm2,224[r8]
+LAST:
+	dec	rcx
+	aesenclast	xmm1,xmm2
+	movdqu	[rsi],xmm1
+	jne	LOOP_1
+	; restore non volatile rdi,rsi
+	mov rdi,rax
+	mov rsi,r11
+	ret
+AES_CBC_encrypt ENDP
+
+
+
+;	/*
+;	AES_CBC_decrypt[const	,unsigned	char*in
+;	unsigned	,char*out
+;	unsigned	,char	ivec+16
+;	unsigned	,long	length
+;	const	,unsigned	char*KS
+;	int	nr]
+;	*/
+;	.	globl	AES_CBC_decrypt
+AES_CBC_decrypt PROC
+;#	parameter	1:	rdi
+;#	parameter	2:	rsi
+;#	parameter	3:	rdx
+;#	parameter	4:	rcx
+;#	parameter	5:	r8
+;#	parameter	6:	r9d
+
+; save rdi and rsi to rax and r11, restore before ret
+	mov rax,rdi
+	mov r11,rsi
+
+; convert to what we had for att&t convention
+	mov rdi,rcx
+	mov rsi,rdx
+	mov rdx,r8
+	mov rcx,r9
+	mov r8,[rsp+40]
+	mov r9d,[rsp+48]
+
+; on microsoft xmm6-xmm15 are non volaitle, let's save on stack and restore at end
+	sub rsp,8+8*16  ; 8 = align stack , 8 xmm6-12,15 16 bytes each
+	movdqa [rsp+0], xmm6
+	movdqa [rsp+16], xmm7
+	movdqa [rsp+32], xmm8
+	movdqa [rsp+48], xmm9
+	movdqa [rsp+64], xmm10
+	movdqa [rsp+80], xmm11
+	movdqa [rsp+96], xmm12
+	movdqa [rsp+112], xmm15
+
+	mov	r10,rcx
+	shr	rcx,4
+	shl	r10,60
+	je	DNO_PARTS_4
+	add	rcx,1
+DNO_PARTS_4:
+	mov	r10,rcx
+	shl	r10,62
+	shr	r10,62
+	shr	rcx,2
+	movdqu xmm5,[rdx]
+	je	DREMAINDER_4
+	sub	rsi,64
+DLOOP_4:
+	movdqu  xmm1,[rdi]
+	movdqu	xmm2,16[rdi]
+	movdqu	xmm3,32[rdi]
+	movdqu	xmm4,48[rdi]
+	movdqa	xmm6,xmm1
+	movdqa	xmm7,xmm2
+	movdqa	xmm8,xmm3
+	movdqa	xmm15,xmm4
+	movdqa  xmm9,[r8]
+	movdqa	xmm10,16[r8]
+	movdqa	xmm11,32[r8]
+	movdqa	xmm12,48[r8]
+	pxor	xmm1,xmm9
+	pxor	xmm2,xmm9
+	pxor	xmm3,xmm9
+
+	pxor	xmm4,xmm9
+	aesdec	xmm1,xmm10
+	aesdec	xmm2,xmm10
+	aesdec	xmm3,xmm10
+	aesdec	xmm4,xmm10
+	aesdec	xmm1,xmm11
+	aesdec	xmm2,xmm11
+	aesdec	xmm3,xmm11
+	aesdec	xmm4,xmm11
+	aesdec	xmm1,xmm12
+	aesdec	xmm2,xmm12
+	aesdec	xmm3,xmm12
+	aesdec	xmm4,xmm12
+	movdqa	xmm9,64[r8]
+	movdqa	xmm10,80[r8]
+	movdqa	xmm11,96[r8]
+	movdqa	xmm12,112[r8]
+	aesdec	xmm1,xmm9
+	aesdec	xmm2,xmm9
+	aesdec	xmm3,xmm9
+	aesdec	xmm4,xmm9
+	aesdec	xmm1,xmm10
+	aesdec	xmm2,xmm10
+	aesdec	xmm3,xmm10
+	aesdec	xmm4,xmm10
+	aesdec	xmm1,xmm11
+	aesdec	xmm2,xmm11
+	aesdec	xmm3,xmm11
+	aesdec	xmm4,xmm11
+	aesdec	xmm1,xmm12
+	aesdec	xmm2,xmm12
+	aesdec	xmm3,xmm12
+	aesdec	xmm4,xmm12
+	movdqa	xmm9,128[r8]
+	movdqa	xmm10,144[r8]
+	movdqa	xmm11,160[r8]
+	cmp	r9d,12
+	aesdec	xmm1,xmm9
+	aesdec	xmm2,xmm9
+	aesdec	xmm3,xmm9
+	aesdec	xmm4,xmm9
+	aesdec	xmm1,xmm10
+	aesdec	xmm2,xmm10
+	aesdec	xmm3,xmm10
+	aesdec	xmm4,xmm10
+	jb	DLAST_4
+	movdqa	xmm9,160[r8]
+	movdqa	xmm10,176[r8]
+	movdqa	xmm11,192[r8]
+	cmp	r9d,14
+	aesdec	xmm1,xmm9
+	aesdec	xmm2,xmm9
+	aesdec	xmm3,xmm9
+	aesdec	xmm4,xmm9
+	aesdec	xmm1,xmm10
+	aesdec	xmm2,xmm10
+	aesdec	xmm3,xmm10
+	aesdec	xmm4,xmm10
+	jb	DLAST_4
+
+	movdqa	xmm9,192[r8]
+	movdqa	xmm10,208[r8]
+	movdqa	xmm11,224[r8]
+	aesdec	xmm1,xmm9
+	aesdec	xmm2,xmm9
+	aesdec	xmm3,xmm9
+	aesdec	xmm4,xmm9
+	aesdec	xmm1,xmm10
+	aesdec	xmm2,xmm10
+	aesdec	xmm3,xmm10
+	aesdec	xmm4,xmm10
+DLAST_4:
+	add	rdi,64
+	add	rsi,64
+	dec	rcx
+	aesdeclast	xmm1,xmm11
+	aesdeclast	xmm2,xmm11
+	aesdeclast	xmm3,xmm11
+	aesdeclast	xmm4,xmm11
+	pxor	xmm1,xmm5
+	pxor	xmm2,xmm6
+	pxor	xmm3,xmm7
+	pxor	xmm4,xmm8
+	movdqu	[rsi],xmm1
+	movdqu	16[rsi],xmm2
+	movdqu	32[rsi],xmm3
+	movdqu	48[rsi],xmm4
+	movdqa	xmm5,xmm15
+	jne	DLOOP_4
+	add	rsi,64
+DREMAINDER_4:
+	cmp	r10,0
+	je	DEND_4
+DLOOP_4_2:
+	movdqu  xmm1,[rdi]
+	movdqa	xmm15,xmm1
+	add	rdi,16
+	pxor	xmm1,[r8]
+	movdqu	xmm2,160[r8]
+	cmp	r9d,12
+	aesdec	xmm1,16[r8]
+	aesdec	xmm1,32[r8]
+	aesdec	xmm1,48[r8]
+	aesdec	xmm1,64[r8]
+	aesdec	xmm1,80[r8]
+	aesdec	xmm1,96[r8]
+	aesdec	xmm1,112[r8]
+	aesdec	xmm1,128[r8]
+	aesdec	xmm1,144[r8]
+	jb	DLAST_4_2
+	movdqu	xmm2,192[r8]
+	cmp	r9d,14
+	aesdec	xmm1,160[r8]
+	aesdec	xmm1,176[r8]
+	jb	DLAST_4_2
+	movdqu	xmm2,224[r8]
+	aesdec	xmm1,192[r8]
+	aesdec	xmm1,208[r8]
+DLAST_4_2:
+	aesdeclast	xmm1,xmm2
+	pxor	xmm1,xmm5
+	movdqa	xmm5,xmm15
+	movdqu	[rsi],xmm1
+
+	add	rsi,16
+	dec	r10
+	jne	DLOOP_4_2
+DEND_4:
+	; restore non volatile rdi,rsi
+	mov rdi,rax
+	mov rsi,r11
+	; restore non volatile xmms from stack
+	movdqa xmm6, [rsp+0]
+	movdqa xmm7, [rsp+16]
+	movdqa xmm8, [rsp+32]
+	movdqa xmm9, [rsp+48]
+	movdqa xmm10, [rsp+64]
+	movdqa xmm11, [rsp+80]
+	movdqa xmm12, [rsp+96]
+	movdqa xmm15, [rsp+112]
+	add rsp,8+8*16 ; 8 = align stack , 8 xmm6-12,15 16 bytes each
+	ret
+AES_CBC_decrypt ENDP
+
+;	/*
+;	AES_ECB_encrypt[const	,unsigned	char*in
+;	unsigned	,char*out
+;	unsigned	,long	length
+;	const	,unsigned	char*KS
+;	int	nr]
+;	*/
+;	.	globl	AES_ECB_encrypt
+AES_ECB_encrypt PROC
+;#	parameter	1:	rdi
+;#	parameter	2:	rsi
+;#	parameter	3:	rdx
+;#	parameter	4:	rcx
+;#	parameter	5:	r8d
+
+; save rdi and rsi to rax and r11, restore before ret
+	mov rax,rdi
+	mov r11,rsi
+
+; convert to what we had for att&t convention
+    mov rdi,rcx
+	mov rsi,rdx
+	mov rdx,r8
+	mov rcx,r9
+	mov r8d,[rsp+40]
+
+; on microsoft xmm6-xmm15 are non volaitle, let's save on stack and restore at end
+	sub rsp,8+4*16  ; 8 = align stack , 4 xmm9-12, 16 bytes each
+	movdqa [rsp+0], xmm9
+	movdqa [rsp+16], xmm10
+	movdqa [rsp+32], xmm11
+	movdqa [rsp+48], xmm12
+
+
+	mov	r10,rdx
+	shr	rdx,4
+	shl	r10,60
+	je	EECB_NO_PARTS_4
+	add	rdx,1
+EECB_NO_PARTS_4:
+	mov	r10,rdx
+	shl	r10,62
+	shr	r10,62
+	shr	rdx,2
+	je	EECB_REMAINDER_4
+	sub	rsi,64
+EECB_LOOP_4:
+	movdqu  xmm1,[rdi]
+	movdqu	xmm2,16[rdi]
+	movdqu	xmm3,32[rdi]
+	movdqu	xmm4,48[rdi]
+	movdqa  xmm9,[rcx]
+	movdqa	xmm10,16[rcx]
+	movdqa	xmm11,32[rcx]
+	movdqa	xmm12,48[rcx]
+	pxor	xmm1,xmm9
+	pxor	xmm2,xmm9
+	pxor	xmm3,xmm9
+	pxor	xmm4,xmm9
+	aesenc	xmm1,xmm10
+	aesenc	xmm2,xmm10
+	aesenc	xmm3,xmm10
+	aesenc	xmm4,xmm10
+	aesenc	xmm1,xmm11
+	aesenc	xmm2,xmm11
+	aesenc	xmm3,xmm11
+	aesenc	xmm4,xmm11
+	aesenc	xmm1,xmm12
+	aesenc	xmm2,xmm12
+	aesenc	xmm3,xmm12
+	aesenc	xmm4,xmm12
+	movdqa	xmm9,64[rcx]
+	movdqa	xmm10,80[rcx]
+	movdqa	xmm11,96[rcx]
+	movdqa	xmm12,112[rcx]
+	aesenc	xmm1,xmm9
+	aesenc	xmm2,xmm9
+	aesenc	xmm3,xmm9
+	aesenc	xmm4,xmm9
+	aesenc	xmm1,xmm10
+	aesenc	xmm2,xmm10
+	aesenc	xmm3,xmm10
+	aesenc	xmm4,xmm10
+	aesenc	xmm1,xmm11
+	aesenc	xmm2,xmm11
+	aesenc	xmm3,xmm11
+	aesenc	xmm4,xmm11
+	aesenc	xmm1,xmm12
+	aesenc	xmm2,xmm12
+	aesenc	xmm3,xmm12
+	aesenc	xmm4,xmm12
+	movdqa	xmm9,128[rcx]
+	movdqa	xmm10,144[rcx]
+	movdqa	xmm11,160[rcx]
+	cmp	r8d,12
+	aesenc	xmm1,xmm9
+	aesenc	xmm2,xmm9
+	aesenc	xmm3,xmm9
+	aesenc	xmm4,xmm9
+	aesenc	xmm1,xmm10
+	aesenc	xmm2,xmm10
+	aesenc	xmm3,xmm10
+	aesenc	xmm4,xmm10
+	jb	EECB_LAST_4
+	movdqa	xmm9,160[rcx]
+	movdqa	xmm10,176[rcx]
+	movdqa	xmm11,192[rcx]
+	cmp	r8d,14
+	aesenc	xmm1,xmm9
+	aesenc	xmm2,xmm9
+	aesenc	xmm3,xmm9
+	aesenc	xmm4,xmm9
+	aesenc	xmm1,xmm10
+	aesenc	xmm2,xmm10
+	aesenc	xmm3,xmm10
+	aesenc	xmm4,xmm10
+	jb	EECB_LAST_4
+	movdqa	xmm9,192[rcx]
+	movdqa	xmm10,208[rcx]
+	movdqa	xmm11,224[rcx]
+	aesenc	xmm1,xmm9
+	aesenc	xmm2,xmm9
+	aesenc	xmm3,xmm9
+	aesenc	xmm4,xmm9
+	aesenc	xmm1,xmm10
+	aesenc	xmm2,xmm10
+	aesenc	xmm3,xmm10
+	aesenc	xmm4,xmm10
+EECB_LAST_4:
+	add	rdi,64
+	add	rsi,64
+	dec	rdx
+	aesenclast	xmm1,xmm11
+	aesenclast	xmm2,xmm11
+	aesenclast	xmm3,xmm11
+	aesenclast	xmm4,xmm11
+	movdqu	[rsi],xmm1
+	movdqu	16[rsi],xmm2
+	movdqu	32[rsi],xmm3
+	movdqu	48[rsi],xmm4
+	jne	EECB_LOOP_4
+	add	rsi,64
+EECB_REMAINDER_4:
+	cmp	r10,0
+	je	EECB_END_4
+EECB_LOOP_4_2:
+	movdqu  xmm1,[rdi]
+	add	rdi,16
+	pxor	xmm1,[rcx]
+	movdqu	xmm2,160[rcx]
+	aesenc	xmm1,16[rcx]
+	aesenc	xmm1,32[rcx]
+	aesenc	xmm1,48[rcx]
+	aesenc	xmm1,64[rcx]
+	aesenc	xmm1,80[rcx]
+	aesenc	xmm1,96[rcx]
+	aesenc	xmm1,112[rcx]
+	aesenc	xmm1,128[rcx]
+	aesenc	xmm1,144[rcx]
+	cmp	r8d,12
+	jb	EECB_LAST_4_2
+	movdqu	xmm2,192[rcx]
+	aesenc	xmm1,160[rcx]
+	aesenc	xmm1,176[rcx]
+	cmp	r8d,14
+	jb	EECB_LAST_4_2
+	movdqu	xmm2,224[rcx]
+	aesenc	xmm1,192[rcx]
+	aesenc	xmm1,208[rcx]
+EECB_LAST_4_2:
+	aesenclast	xmm1,xmm2
+	movdqu	[rsi],xmm1
+	add	rsi,16
+	dec	r10
+	jne	EECB_LOOP_4_2
+EECB_END_4:
+	; restore non volatile rdi,rsi
+	mov rdi,rax
+	mov rsi,r11
+	; restore non volatile xmms from stack
+	movdqa xmm9, [rsp+0]
+	movdqa xmm10, [rsp+16]
+	movdqa xmm11, [rsp+32]
+	movdqa xmm12, [rsp+48]
+	add rsp,8+4*16 ; 8 = align stack , 4 xmm9-12 16 bytes each
+	ret
+AES_ECB_encrypt ENDP
+
+;	/*
+;	AES_ECB_decrypt[const	,unsigned	char*in
+;	unsigned	,char*out
+;	unsigned	,long	length
+;	const	,unsigned	char*KS
+;	int	nr]
+;	*/
+;	.	globl	AES_ECB_decrypt
+AES_ECB_decrypt PROC
+;#	parameter	1:	rdi
+;#	parameter	2:	rsi
+;#	parameter	3:	rdx
+;#	parameter	4:	rcx
+;#	parameter	5:	r8d
+
+; save rdi and rsi to rax and r11, restore before ret
+	mov rax,rdi
+	mov r11,rsi
+
+; convert to what we had for att&t convention
+	mov rdi,rcx
+	mov rsi,rdx
+	mov rdx,r8
+	mov rcx,r9
+	mov r8d,[rsp+40]
+
+; on microsoft xmm6-xmm15 are non volaitle, let's save on stack and restore at end
+	sub rsp,8+4*16  ; 8 = align stack , 4 xmm9-12, 16 bytes each
+	movdqa [rsp+0], xmm9
+	movdqa [rsp+16], xmm10
+	movdqa [rsp+32], xmm11
+	movdqa [rsp+48], xmm12
+
+	mov	r10,rdx
+	shr	rdx,4
+	shl	r10,60
+	je	DECB_NO_PARTS_4
+	add	rdx,1
+DECB_NO_PARTS_4:
+	mov	r10,rdx
+	shl	r10,62
+	shr	r10,62
+	shr	rdx,2
+	je	DECB_REMAINDER_4
+	sub	rsi,64
+DECB_LOOP_4:
+	movdqu  xmm1,[rdi]
+	movdqu	xmm2,16[rdi]
+	movdqu	xmm3,32[rdi]
+	movdqu	xmm4,48[rdi]
+	movdqa  xmm9,[rcx]
+	movdqa	xmm10,16[rcx]
+	movdqa	xmm11,32[rcx]
+	movdqa	xmm12,48[rcx]
+	pxor	xmm1,xmm9
+	pxor	xmm2,xmm9
+	pxor	xmm3,xmm9
+	pxor	xmm4,xmm9
+	aesdec	xmm1,xmm10
+	aesdec	xmm2,xmm10
+	aesdec	xmm3,xmm10
+	aesdec	xmm4,xmm10
+	aesdec	xmm1,xmm11
+	aesdec	xmm2,xmm11
+	aesdec	xmm3,xmm11
+	aesdec	xmm4,xmm11
+	aesdec	xmm1,xmm12
+	aesdec	xmm2,xmm12
+	aesdec	xmm3,xmm12
+	aesdec	xmm4,xmm12
+	movdqa	xmm9,64[rcx]
+	movdqa	xmm10,80[rcx]
+	movdqa	xmm11,96[rcx]
+	movdqa	xmm12,112[rcx]
+	aesdec	xmm1,xmm9
+	aesdec	xmm2,xmm9
+	aesdec	xmm3,xmm9
+	aesdec	xmm4,xmm9
+	aesdec	xmm1,xmm10
+	aesdec	xmm2,xmm10
+	aesdec	xmm3,xmm10
+	aesdec	xmm4,xmm10
+	aesdec	xmm1,xmm11
+	aesdec	xmm2,xmm11
+	aesdec	xmm3,xmm11
+	aesdec	xmm4,xmm11
+	aesdec	xmm1,xmm12
+	aesdec	xmm2,xmm12
+	aesdec	xmm3,xmm12
+	aesdec	xmm4,xmm12
+	movdqa	xmm9,128[rcx]
+	movdqa	xmm10,144[rcx]
+	movdqa	xmm11,160[rcx]
+	cmp	r8d,12
+	aesdec	xmm1,xmm9
+	aesdec	xmm2,xmm9
+	aesdec	xmm3,xmm9
+	aesdec	xmm4,xmm9
+	aesdec	xmm1,xmm10
+	aesdec	xmm2,xmm10
+	aesdec	xmm3,xmm10
+	aesdec	xmm4,xmm10
+	jb	DECB_LAST_4
+	movdqa	xmm9,160[rcx]
+	movdqa	xmm10,176[rcx]
+	movdqa	xmm11,192[rcx]
+	cmp	r8d,14
+	aesdec	xmm1,xmm9
+	aesdec	xmm2,xmm9
+	aesdec	xmm3,xmm9
+	aesdec	xmm4,xmm9
+	aesdec	xmm1,xmm10
+	aesdec	xmm2,xmm10
+	aesdec	xmm3,xmm10
+	aesdec	xmm4,xmm10
+	jb	DECB_LAST_4
+	movdqa	xmm9,192[rcx]
+	movdqa	xmm10,208[rcx]
+	movdqa	xmm11,224[rcx]
+	aesdec	xmm1,xmm9
+	aesdec	xmm2,xmm9
+	aesdec	xmm3,xmm9
+	aesdec	xmm4,xmm9
+	aesdec	xmm1,xmm10
+	aesdec	xmm2,xmm10
+	aesdec	xmm3,xmm10
+	aesdec	xmm4,xmm10
+DECB_LAST_4:
+	add	rdi,64
+	add	rsi,64
+	dec	rdx
+	aesdeclast	xmm1,xmm11
+	aesdeclast	xmm2,xmm11
+	aesdeclast	xmm3,xmm11
+	aesdeclast	xmm4,xmm11
+	movdqu	[rsi],xmm1
+	movdqu	16[rsi],xmm2
+	movdqu	32[rsi],xmm3
+	movdqu	48[rsi],xmm4
+	jne	DECB_LOOP_4
+	add	rsi,64
+DECB_REMAINDER_4:
+	cmp	r10,0
+	je	DECB_END_4
+DECB_LOOP_4_2:
+	movdqu  xmm1,[rdi]
+	add	rdi,16
+	pxor	xmm1,[rcx]
+	movdqu	xmm2,160[rcx]
+	cmp	r8d,12
+	aesdec	xmm1,16[rcx]
+	aesdec	xmm1,32[rcx]
+	aesdec	xmm1,48[rcx]
+	aesdec	xmm1,64[rcx]
+	aesdec	xmm1,80[rcx]
+	aesdec	xmm1,96[rcx]
+	aesdec	xmm1,112[rcx]
+	aesdec	xmm1,128[rcx]
+	aesdec	xmm1,144[rcx]
+	jb	DECB_LAST_4_2
+	cmp	r8d,14
+	movdqu	xmm2,192[rcx]
+	aesdec	xmm1,160[rcx]
+	aesdec	xmm1,176[rcx]
+	jb	DECB_LAST_4_2
+	movdqu	xmm2,224[rcx]
+	aesdec	xmm1,192[rcx]
+	aesdec	xmm1,208[rcx]
+DECB_LAST_4_2:
+	aesdeclast	xmm1,xmm2
+	movdqu	[rsi],xmm1
+	add	rsi,16
+	dec	r10
+	jne	DECB_LOOP_4_2
+DECB_END_4:
+	; restore non volatile rdi,rsi
+	mov rdi,rax
+	mov rsi,r11
+	; restore non volatile xmms from stack
+	movdqa xmm9, [rsp+0]
+	movdqa xmm10, [rsp+16]
+	movdqa xmm11, [rsp+32]
+	movdqa xmm12, [rsp+48]
+	add rsp,8+4*16 ; 8 = align stack , 4 xmm9-12 16 bytes each
+	ret
+AES_ECB_decrypt ENDP
+
+
+
+;	/*
+;	void	,AES_128_Key_Expansion[const	unsigned	char*userkey
+;	unsigned	char*key_schedule]/
+;	*/
+;	.	align	16,0x90
+;	.	globl	AES_128_Key_Expansion
+AES_128_Key_Expansion PROC
+;#	parameter	1:	rdi
+;#	parameter	2:	rsi
+
+; save rdi and rsi to rax and r11, restore before ret
+	mov rax,rdi
+	mov r11,rsi
+
+; convert to what we had for att&t convention
+	mov rdi,rcx
+	mov rsi,rdx
+
+	mov	dword ptr 240[rsi],10
+
+	movdqu	xmm1,[rdi]
+	movdqa	[rsi],xmm1
+
+
+ASSISTS:
+	aeskeygenassist	xmm2,xmm1,1
+	call	PREPARE_ROUNDKEY_128
+	movdqa	16[rsi],xmm1
+
+	aeskeygenassist	xmm2,xmm1,2
+	call	PREPARE_ROUNDKEY_128
+	movdqa	32[rsi],xmm1
+
+	aeskeygenassist	xmm2,xmm1,4
+	call	PREPARE_ROUNDKEY_128
+	movdqa	48[rsi],xmm1
+
+	aeskeygenassist	xmm2,xmm1,8
+	call	PREPARE_ROUNDKEY_128
+	movdqa	64[rsi],xmm1
+
+	aeskeygenassist	xmm2,xmm1,16
+	call	PREPARE_ROUNDKEY_128
+	movdqa	80[rsi],xmm1
+
+	aeskeygenassist	xmm2,xmm1,32
+	call	PREPARE_ROUNDKEY_128
+	movdqa	96[rsi],xmm1
+
+	aeskeygenassist	xmm2,xmm1,64
+	call	PREPARE_ROUNDKEY_128
+	movdqa	112[rsi],xmm1
+	aeskeygenassist	xmm2,xmm1,80h
+	call	PREPARE_ROUNDKEY_128
+	movdqa	128[rsi],xmm1
+	aeskeygenassist	xmm2,xmm1,1bh
+	call	PREPARE_ROUNDKEY_128
+	movdqa	144[rsi],xmm1
+	aeskeygenassist	xmm2,xmm1,36h
+	call	PREPARE_ROUNDKEY_128
+	movdqa	160[rsi],xmm1
+	; restore non volatile rdi,rsi
+	mov rdi,rax
+	mov rsi,r11
+	ret
+
+PREPARE_ROUNDKEY_128:
+	pshufd	xmm2,xmm2,255
+	movdqa	xmm3,xmm1
+	pslldq	xmm3,4
+	pxor	xmm1,xmm3
+	pslldq	xmm3,4
+	pxor	xmm1,xmm3
+	pslldq	xmm3,4
+	pxor	xmm1,xmm3
+	pxor	xmm1,xmm2
+	ret
+AES_128_Key_Expansion ENDP
+
+;	/*
+;	void	,AES_192_Key_Expansion[const	unsigned	char*userkey
+;	unsigned	char*key]
+;	*/
+;	.	globl	AES_192_Key_Expansion
+AES_192_Key_Expansion PROC
+;#	parameter	1:	rdi
+;#	parameter	2:	rsi
+
+; save rdi and rsi to rax and r11, restore before ret
+	mov rax,rdi
+	mov r11,rsi
+
+; convert to what we had for att&t convention
+    mov rdi,rcx
+	mov rsi,rdx
+
+; on microsoft xmm6-xmm15 are non volaitle, let's save on stack and restore at end
+	sub rsp,8+1*16  ; 8 = align stack , 1 xmm6, 16 bytes each
+	movdqa [rsp+0], xmm6
+
+	movdqu  xmm1,[rdi]
+	movdqu	xmm3,16[rdi]
+	movdqa	[rsi],xmm1
+	movdqa	xmm5,xmm3
+
+	aeskeygenassist	xmm2,xmm3,1h
+	call	PREPARE_ROUNDKEY_192
+	shufpd	xmm5,xmm1,0
+	movdqa	16[rsi],xmm5
+	movdqa	xmm6,xmm1
+	shufpd	xmm6,xmm3,1
+	movdqa	32[rsi],xmm6
+
+	aeskeygenassist	xmm2,xmm3,2h
+	call	PREPARE_ROUNDKEY_192
+	movdqa	48[rsi],xmm1
+	movdqa	xmm5,xmm3
+
+	aeskeygenassist	xmm2,xmm3,4h
+	call	PREPARE_ROUNDKEY_192
+	shufpd	xmm5,xmm1,0
+	movdqa	64[rsi],xmm5
+	movdqa	xmm6,xmm1
+	shufpd	xmm6,xmm3,1
+	movdqa	80[rsi],xmm6
+
+	aeskeygenassist	xmm2,xmm3,8h
+	call	PREPARE_ROUNDKEY_192
+	movdqa	96[rsi],xmm1
+	movdqa	xmm5,xmm3
+
+	aeskeygenassist	xmm2,xmm3,10h
+	call	PREPARE_ROUNDKEY_192
+	shufpd	xmm5,xmm1,0
+	movdqa	112[rsi],xmm5
+	movdqa	xmm6,xmm1
+	shufpd	xmm6,xmm3,1
+	movdqa	128[rsi],xmm6
+
+	aeskeygenassist	xmm2,xmm3,20h
+	call	PREPARE_ROUNDKEY_192
+	movdqa	144[rsi],xmm1
+	movdqa	xmm5,xmm3
+
+	aeskeygenassist	xmm2,xmm3,40h
+	call	PREPARE_ROUNDKEY_192
+	shufpd	xmm5,xmm1,0
+	movdqa	160[rsi],xmm5
+	movdqa	xmm6,xmm1
+	shufpd	xmm6,xmm3,1
+	movdqa	176[rsi],xmm6
+
+	aeskeygenassist	xmm2,xmm3,80h
+	call	PREPARE_ROUNDKEY_192
+	movdqa	192[rsi],xmm1
+	movdqa	208[rsi],xmm3
+	; restore non volatile rdi,rsi
+	mov rdi,rax
+	mov rsi,r11
+; restore non volatile xmms from stack
+	movdqa xmm6, [rsp+0]
+	add rsp,8+1*16 ; 8 = align stack , 1 xmm6 16 bytes each
+	ret
+
+PREPARE_ROUNDKEY_192:
+	pshufd	xmm2,xmm2,55h
+	movdqu	xmm4,xmm1
+	pslldq	xmm4,4
+	pxor	xmm1,xmm4
+
+	pslldq	xmm4,4
+	pxor	xmm1,xmm4
+	pslldq	xmm4,4
+	pxor	xmm1,xmm4
+	pxor	xmm1,xmm2
+	pshufd	xmm2,xmm1,0ffh
+	movdqu	xmm4,xmm3
+	pslldq	xmm4,4
+	pxor	xmm3,xmm4
+	pxor	xmm3,xmm2
+	ret
+AES_192_Key_Expansion ENDP
+
+;	/*
+;	void	,AES_256_Key_Expansion[const	unsigned	char*userkey
+;	unsigned	char*key]
+;	*/
+;	.	globl	AES_256_Key_Expansion
+AES_256_Key_Expansion PROC
+;#	parameter	1:	rdi
+;#	parameter	2:	rsi
+
+; save rdi and rsi to rax and r11, restore before ret
+	mov rax,rdi
+	mov r11,rsi
+
+; convert to what we had for att&t convention
+    mov rdi,rcx
+	mov rsi,rdx
+
+	movdqu  xmm1,[rdi]
+	movdqu	xmm3,16[rdi]
+	movdqa	[rsi],xmm1
+	movdqa	16[rsi],xmm3
+
+	aeskeygenassist	xmm2,xmm3,1h
+	call	MAKE_RK256_a
+	movdqa	32[rsi],xmm1
+	aeskeygenassist	xmm2,xmm1,0h
+	call	MAKE_RK256_b
+	movdqa	48[rsi],xmm3
+	aeskeygenassist	xmm2,xmm3,2h
+	call	MAKE_RK256_a
+	movdqa	64[rsi],xmm1
+	aeskeygenassist	xmm2,xmm1,0h
+	call	MAKE_RK256_b
+	movdqa	80[rsi],xmm3
+	aeskeygenassist	xmm2,xmm3,4h
+	call	MAKE_RK256_a
+	movdqa	96[rsi],xmm1
+	aeskeygenassist	xmm2,xmm1,0h
+	call	MAKE_RK256_b
+	movdqa	112[rsi],xmm3
+	aeskeygenassist	xmm2,xmm3,8h
+	call	MAKE_RK256_a
+	movdqa	128[rsi],xmm1
+	aeskeygenassist	xmm2,xmm1,0h
+	call	MAKE_RK256_b
+	movdqa	144[rsi],xmm3
+	aeskeygenassist	xmm2,xmm3,10h
+	call	MAKE_RK256_a
+	movdqa	160[rsi],xmm1
+	aeskeygenassist	xmm2,xmm1,0h
+	call	MAKE_RK256_b
+	movdqa	176[rsi],xmm3
+	aeskeygenassist	xmm2,xmm3,20h
+	call	MAKE_RK256_a
+	movdqa	192[rsi],xmm1
+
+	aeskeygenassist	xmm2,xmm1,0h
+	call	MAKE_RK256_b
+	movdqa	208[rsi],xmm3
+	aeskeygenassist	xmm2,xmm3,40h
+	call	MAKE_RK256_a
+	movdqa	224[rsi],xmm1
+
+	; restore non volatile rdi,rsi
+	mov rdi,rax
+	mov rsi,r11
+	ret
+AES_256_Key_Expansion ENDP
+
+MAKE_RK256_a:
+	pshufd	xmm2,xmm2,0ffh
+	movdqa	xmm4,xmm1
+	pslldq	xmm4,4
+	pxor	xmm1,xmm4
+	pslldq	xmm4,4
+	pxor	xmm1,xmm4
+	pslldq	xmm4,4
+	pxor	xmm1,xmm4
+	pxor	xmm1,xmm2
+	ret
+
+MAKE_RK256_b:
+	pshufd	xmm2,xmm2,0aah
+	movdqa	xmm4,xmm3
+	pslldq	xmm4,4
+	pxor	xmm3,xmm4
+	pslldq	xmm4,4
+	pxor	xmm3,xmm4
+	pslldq	xmm4,4
+	pxor	xmm3,xmm4
+	pxor	xmm3,xmm2
+	ret
+
+END
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/aes_asm.s b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/aes_asm.s
new file mode 100644
index 0000000..b50c7ff
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/aes_asm.s
@@ -0,0 +1,816 @@
+/* aes_asm.s
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+/* See Intel® Advanced Encryption Standard (AES) Instructions Set White Paper
+ * by Intel Mobility Group, Israel Development Center, Israel Shay Gueron
+ */
+
+/* This file is in at&t asm syntax, see .asm for intel syntax */
+
+
+/*
+AES_CBC_encrypt (const unsigned char *in,
+	unsigned char *out,
+	unsigned char ivec[16],
+	unsigned long length,
+	const unsigned char *KS,
+	int nr)
+*/
+.globl AES_CBC_encrypt
+AES_CBC_encrypt:
+# parameter 1: %rdi
+# parameter 2: %rsi
+# parameter 3: %rdx
+# parameter 4: %rcx
+# parameter 5: %r8
+# parameter 6: %r9d
+movq	%rcx, %r10
+shrq	$4, %rcx
+shlq	$60, %r10
+je	NO_PARTS
+addq	$1, %rcx
+NO_PARTS:
+subq	$16, %rsi
+movdqa	(%rdx), %xmm1
+LOOP:
+pxor	(%rdi), %xmm1
+pxor	(%r8), %xmm1
+addq	$16,%rsi
+addq	$16,%rdi
+cmpl	$12, %r9d
+aesenc	16(%r8),%xmm1
+aesenc	32(%r8),%xmm1
+aesenc	48(%r8),%xmm1
+aesenc	64(%r8),%xmm1
+aesenc	80(%r8),%xmm1
+aesenc	96(%r8),%xmm1
+aesenc	112(%r8),%xmm1
+aesenc	128(%r8),%xmm1
+aesenc	144(%r8),%xmm1
+movdqa	160(%r8),%xmm2
+jb	LAST
+cmpl	$14, %r9d
+
+aesenc	160(%r8),%xmm1
+aesenc	176(%r8),%xmm1
+movdqa	192(%r8),%xmm2
+jb	LAST
+aesenc	192(%r8),%xmm1
+aesenc	208(%r8),%xmm1
+movdqa	224(%r8),%xmm2
+LAST:
+decq	%rcx
+aesenclast %xmm2,%xmm1
+movdqu	%xmm1,(%rsi)
+jne	LOOP
+ret
+
+
+
+
+/*
+AES_CBC_decrypt (const unsigned char *in,
+  unsigned char *out,
+  unsigned char ivec[16],
+  unsigned long length,
+  const unsigned char *KS,
+  int nr)
+*/
+.globl AES_CBC_decrypt
+AES_CBC_decrypt:
+# parameter 1: %rdi
+# parameter 2: %rsi
+# parameter 3: %rdx
+# parameter 4: %rcx
+# parameter 5: %r8
+# parameter 6: %r9d
+
+movq    %rcx, %r10
+shrq $4, %rcx
+shlq   $60, %r10
+je    DNO_PARTS_4
+addq    $1, %rcx
+DNO_PARTS_4:
+movq   %rcx, %r10
+shlq    $62, %r10
+shrq  $62, %r10
+shrq  $2, %rcx
+movdqu (%rdx),%xmm5
+je DREMAINDER_4
+subq   $64, %rsi
+DLOOP_4:
+movdqu (%rdi), %xmm1
+movdqu  16(%rdi), %xmm2
+movdqu  32(%rdi), %xmm3
+movdqu  48(%rdi), %xmm4
+movdqa  %xmm1, %xmm6
+movdqa %xmm2, %xmm7
+movdqa %xmm3, %xmm8
+movdqa %xmm4, %xmm15
+movdqa    (%r8), %xmm9
+movdqa 16(%r8), %xmm10
+movdqa  32(%r8), %xmm11
+movdqa  48(%r8), %xmm12
+pxor    %xmm9, %xmm1
+pxor   %xmm9, %xmm2
+pxor   %xmm9, %xmm3
+
+pxor    %xmm9, %xmm4
+aesdec %xmm10, %xmm1
+aesdec    %xmm10, %xmm2
+aesdec    %xmm10, %xmm3
+aesdec    %xmm10, %xmm4
+aesdec    %xmm11, %xmm1
+aesdec    %xmm11, %xmm2
+aesdec    %xmm11, %xmm3
+aesdec    %xmm11, %xmm4
+aesdec    %xmm12, %xmm1
+aesdec    %xmm12, %xmm2
+aesdec    %xmm12, %xmm3
+aesdec    %xmm12, %xmm4
+movdqa    64(%r8), %xmm9
+movdqa   80(%r8), %xmm10
+movdqa  96(%r8), %xmm11
+movdqa  112(%r8), %xmm12
+aesdec %xmm9, %xmm1
+aesdec %xmm9, %xmm2
+aesdec %xmm9, %xmm3
+aesdec %xmm9, %xmm4
+aesdec %xmm10, %xmm1
+aesdec    %xmm10, %xmm2
+aesdec    %xmm10, %xmm3
+aesdec    %xmm10, %xmm4
+aesdec    %xmm11, %xmm1
+aesdec    %xmm11, %xmm2
+aesdec    %xmm11, %xmm3
+aesdec    %xmm11, %xmm4
+aesdec    %xmm12, %xmm1
+aesdec    %xmm12, %xmm2
+aesdec    %xmm12, %xmm3
+aesdec    %xmm12, %xmm4
+movdqa    128(%r8), %xmm9
+movdqa  144(%r8), %xmm10
+movdqa 160(%r8), %xmm11
+cmpl   $12, %r9d
+aesdec  %xmm9, %xmm1
+aesdec %xmm9, %xmm2
+aesdec %xmm9, %xmm3
+aesdec %xmm9, %xmm4
+aesdec %xmm10, %xmm1
+aesdec    %xmm10, %xmm2
+aesdec    %xmm10, %xmm3
+aesdec    %xmm10, %xmm4
+jb    DLAST_4
+movdqa  160(%r8), %xmm9
+movdqa  176(%r8), %xmm10
+movdqa 192(%r8), %xmm11
+cmpl   $14, %r9d
+aesdec  %xmm9, %xmm1
+aesdec %xmm9, %xmm2
+aesdec %xmm9, %xmm3
+aesdec %xmm9, %xmm4
+aesdec %xmm10, %xmm1
+aesdec    %xmm10, %xmm2
+aesdec    %xmm10, %xmm3
+aesdec    %xmm10, %xmm4
+jb    DLAST_4
+
+movdqa  192(%r8), %xmm9
+movdqa  208(%r8), %xmm10
+movdqa 224(%r8), %xmm11
+aesdec %xmm9, %xmm1
+aesdec %xmm9, %xmm2
+aesdec %xmm9, %xmm3
+aesdec %xmm9, %xmm4
+aesdec %xmm10, %xmm1
+aesdec    %xmm10, %xmm2
+aesdec    %xmm10, %xmm3
+aesdec    %xmm10, %xmm4
+DLAST_4:
+addq   $64, %rdi
+addq    $64, %rsi
+decq  %rcx
+aesdeclast %xmm11, %xmm1
+aesdeclast %xmm11, %xmm2
+aesdeclast %xmm11, %xmm3
+aesdeclast %xmm11, %xmm4
+pxor   %xmm5 ,%xmm1
+pxor    %xmm6 ,%xmm2
+pxor   %xmm7 ,%xmm3
+pxor   %xmm8 ,%xmm4
+movdqu %xmm1, (%rsi)
+movdqu    %xmm2, 16(%rsi)
+movdqu  %xmm3, 32(%rsi)
+movdqu  %xmm4, 48(%rsi)
+movdqa  %xmm15,%xmm5
+jne    DLOOP_4
+addq    $64, %rsi
+DREMAINDER_4:
+cmpq    $0, %r10
+je  DEND_4
+DLOOP_4_2:
+movdqu  (%rdi), %xmm1
+movdqa    %xmm1 ,%xmm15
+addq  $16, %rdi
+pxor  (%r8), %xmm1
+movdqu 160(%r8), %xmm2
+cmpl    $12, %r9d
+aesdec    16(%r8), %xmm1
+aesdec   32(%r8), %xmm1
+aesdec   48(%r8), %xmm1
+aesdec   64(%r8), %xmm1
+aesdec   80(%r8), %xmm1
+aesdec   96(%r8), %xmm1
+aesdec   112(%r8), %xmm1
+aesdec  128(%r8), %xmm1
+aesdec  144(%r8), %xmm1
+jb  DLAST_4_2
+movdqu    192(%r8), %xmm2
+cmpl    $14, %r9d
+aesdec    160(%r8), %xmm1
+aesdec  176(%r8), %xmm1
+jb  DLAST_4_2
+movdqu    224(%r8), %xmm2
+aesdec  192(%r8), %xmm1
+aesdec  208(%r8), %xmm1
+DLAST_4_2:
+aesdeclast %xmm2, %xmm1
+pxor    %xmm5, %xmm1
+movdqa %xmm15, %xmm5
+movdqu    %xmm1, (%rsi)
+
+addq    $16, %rsi
+decq    %r10
+jne DLOOP_4_2
+DEND_4:
+ret
+
+
+/*
+AES_ECB_encrypt (const unsigned char *in,
+	unsigned char *out,
+	unsigned long length,
+	const unsigned char *KS,
+	int nr)
+*/
+.globl AES_ECB_encrypt
+AES_ECB_encrypt:
+# parameter 1: %rdi
+# parameter 2: %rsi
+# parameter 3: %rdx
+# parameter 4: %rcx
+# parameter 5: %r8d
+        movq    %rdx, %r10
+        shrq    $4, %rdx
+        shlq    $60, %r10
+        je      EECB_NO_PARTS_4
+        addq    $1, %rdx
+EECB_NO_PARTS_4:
+        movq    %rdx, %r10
+        shlq    $62, %r10
+        shrq    $62, %r10
+        shrq    $2, %rdx
+        je      EECB_REMAINDER_4
+        subq    $64, %rsi
+EECB_LOOP_4:
+        movdqu  (%rdi), %xmm1
+        movdqu  16(%rdi), %xmm2
+        movdqu  32(%rdi), %xmm3
+        movdqu  48(%rdi), %xmm4
+        movdqa  (%rcx), %xmm9
+        movdqa  16(%rcx), %xmm10
+        movdqa  32(%rcx), %xmm11
+        movdqa  48(%rcx), %xmm12
+        pxor    %xmm9, %xmm1
+        pxor    %xmm9, %xmm2
+        pxor    %xmm9, %xmm3
+        pxor    %xmm9, %xmm4
+        aesenc  %xmm10, %xmm1
+        aesenc  %xmm10, %xmm2
+        aesenc  %xmm10, %xmm3
+        aesenc  %xmm10, %xmm4
+        aesenc  %xmm11, %xmm1
+        aesenc  %xmm11, %xmm2
+        aesenc  %xmm11, %xmm3
+        aesenc  %xmm11, %xmm4
+        aesenc  %xmm12, %xmm1
+        aesenc  %xmm12, %xmm2
+        aesenc  %xmm12, %xmm3
+        aesenc  %xmm12, %xmm4
+        movdqa  64(%rcx), %xmm9
+        movdqa  80(%rcx), %xmm10
+        movdqa  96(%rcx), %xmm11
+        movdqa  112(%rcx), %xmm12
+        aesenc  %xmm9, %xmm1
+        aesenc  %xmm9, %xmm2
+        aesenc  %xmm9, %xmm3
+        aesenc  %xmm9, %xmm4
+        aesenc  %xmm10, %xmm1
+        aesenc  %xmm10, %xmm2
+        aesenc  %xmm10, %xmm3
+        aesenc  %xmm10, %xmm4
+        aesenc  %xmm11, %xmm1
+        aesenc  %xmm11, %xmm2
+        aesenc  %xmm11, %xmm3
+        aesenc  %xmm11, %xmm4
+        aesenc  %xmm12, %xmm1
+        aesenc  %xmm12, %xmm2
+        aesenc  %xmm12, %xmm3
+        aesenc  %xmm12, %xmm4
+        movdqa  128(%rcx), %xmm9
+        movdqa  144(%rcx), %xmm10
+        movdqa  160(%rcx), %xmm11
+        cmpl    $12, %r8d
+        aesenc  %xmm9, %xmm1
+        aesenc  %xmm9, %xmm2
+        aesenc  %xmm9, %xmm3
+        aesenc  %xmm9, %xmm4
+        aesenc  %xmm10, %xmm1
+        aesenc  %xmm10, %xmm2
+        aesenc  %xmm10, %xmm3
+        aesenc  %xmm10, %xmm4
+        jb      EECB_LAST_4
+        movdqa  160(%rcx), %xmm9
+        movdqa  176(%rcx), %xmm10
+        movdqa  192(%rcx), %xmm11
+        cmpl    $14, %r8d
+        aesenc  %xmm9, %xmm1
+        aesenc  %xmm9, %xmm2
+        aesenc  %xmm9, %xmm3
+        aesenc  %xmm9, %xmm4
+        aesenc  %xmm10, %xmm1
+        aesenc  %xmm10, %xmm2
+        aesenc  %xmm10, %xmm3
+        aesenc  %xmm10, %xmm4
+        jb      EECB_LAST_4
+        movdqa  192(%rcx), %xmm9
+        movdqa  208(%rcx), %xmm10
+        movdqa  224(%rcx), %xmm11
+        aesenc  %xmm9, %xmm1
+        aesenc  %xmm9, %xmm2
+        aesenc  %xmm9, %xmm3
+        aesenc  %xmm9, %xmm4
+        aesenc  %xmm10, %xmm1
+        aesenc  %xmm10, %xmm2
+        aesenc  %xmm10, %xmm3
+        aesenc  %xmm10, %xmm4
+EECB_LAST_4:
+        addq    $64, %rdi
+        addq    $64, %rsi
+        decq    %rdx
+        aesenclast %xmm11, %xmm1
+        aesenclast %xmm11, %xmm2
+        aesenclast %xmm11, %xmm3
+        aesenclast %xmm11, %xmm4
+        movdqu  %xmm1, (%rsi)
+        movdqu  %xmm2, 16(%rsi)
+        movdqu  %xmm3, 32(%rsi)
+        movdqu  %xmm4, 48(%rsi)
+        jne     EECB_LOOP_4
+        addq    $64, %rsi
+EECB_REMAINDER_4:
+        cmpq    $0, %r10
+        je      EECB_END_4
+EECB_LOOP_4_2:
+        movdqu  (%rdi), %xmm1
+        addq    $16, %rdi
+        pxor    (%rcx), %xmm1
+        movdqu  160(%rcx), %xmm2
+        aesenc  16(%rcx), %xmm1
+        aesenc  32(%rcx), %xmm1
+        aesenc  48(%rcx), %xmm1
+        aesenc  64(%rcx), %xmm1
+        aesenc  80(%rcx), %xmm1
+        aesenc  96(%rcx), %xmm1
+        aesenc  112(%rcx), %xmm1
+        aesenc  128(%rcx), %xmm1
+        aesenc  144(%rcx), %xmm1
+        cmpl    $12, %r8d
+        jb      EECB_LAST_4_2
+        movdqu  192(%rcx), %xmm2
+        aesenc  160(%rcx), %xmm1
+        aesenc  176(%rcx), %xmm1
+        cmpl    $14, %r8d
+        jb      EECB_LAST_4_2
+        movdqu  224(%rcx), %xmm2
+        aesenc  192(%rcx), %xmm1
+        aesenc  208(%rcx), %xmm1
+EECB_LAST_4_2:
+        aesenclast %xmm2, %xmm1
+        movdqu  %xmm1, (%rsi)
+        addq    $16, %rsi
+        decq    %r10
+        jne     EECB_LOOP_4_2
+EECB_END_4:
+        ret
+
+
+/*
+AES_ECB_decrypt (const unsigned char *in,
+  unsigned char *out,
+  unsigned long length,
+  const unsigned char *KS,
+  int nr)
+*/
+.globl AES_ECB_decrypt
+AES_ECB_decrypt:
+# parameter 1: %rdi
+# parameter 2: %rsi
+# parameter 3: %rdx
+# parameter 4: %rcx
+# parameter 5: %r8d
+
+        movq    %rdx, %r10
+        shrq    $4, %rdx
+        shlq    $60, %r10
+        je      DECB_NO_PARTS_4
+        addq    $1, %rdx
+DECB_NO_PARTS_4:
+        movq    %rdx, %r10
+        shlq    $62, %r10
+        shrq    $62, %r10
+        shrq    $2, %rdx
+        je      DECB_REMAINDER_4
+        subq    $64, %rsi
+DECB_LOOP_4:
+        movdqu  (%rdi), %xmm1
+        movdqu  16(%rdi), %xmm2
+        movdqu  32(%rdi), %xmm3
+        movdqu  48(%rdi), %xmm4
+        movdqa  (%rcx), %xmm9
+        movdqa  16(%rcx), %xmm10
+        movdqa  32(%rcx), %xmm11
+        movdqa  48(%rcx), %xmm12
+        pxor    %xmm9, %xmm1
+        pxor    %xmm9, %xmm2
+        pxor    %xmm9, %xmm3
+        pxor    %xmm9, %xmm4
+        aesdec  %xmm10, %xmm1
+        aesdec  %xmm10, %xmm2
+        aesdec  %xmm10, %xmm3
+        aesdec  %xmm10, %xmm4
+        aesdec  %xmm11, %xmm1
+        aesdec  %xmm11, %xmm2
+        aesdec  %xmm11, %xmm3
+        aesdec  %xmm11, %xmm4
+        aesdec  %xmm12, %xmm1
+        aesdec  %xmm12, %xmm2
+        aesdec  %xmm12, %xmm3
+        aesdec  %xmm12, %xmm4
+        movdqa  64(%rcx), %xmm9
+        movdqa  80(%rcx), %xmm10
+        movdqa  96(%rcx), %xmm11
+        movdqa  112(%rcx), %xmm12
+        aesdec  %xmm9, %xmm1
+        aesdec  %xmm9, %xmm2
+        aesdec  %xmm9, %xmm3
+        aesdec  %xmm9, %xmm4
+        aesdec  %xmm10, %xmm1
+        aesdec  %xmm10, %xmm2
+        aesdec  %xmm10, %xmm3
+        aesdec  %xmm10, %xmm4
+        aesdec  %xmm11, %xmm1
+        aesdec  %xmm11, %xmm2
+        aesdec  %xmm11, %xmm3
+        aesdec  %xmm11, %xmm4
+        aesdec  %xmm12, %xmm1
+        aesdec  %xmm12, %xmm2
+        aesdec  %xmm12, %xmm3
+        aesdec  %xmm12, %xmm4
+        movdqa  128(%rcx), %xmm9
+        movdqa  144(%rcx), %xmm10
+        movdqa  160(%rcx), %xmm11
+        cmpl    $12, %r8d
+        aesdec  %xmm9, %xmm1
+        aesdec  %xmm9, %xmm2
+        aesdec  %xmm9, %xmm3
+        aesdec  %xmm9, %xmm4
+        aesdec  %xmm10, %xmm1
+        aesdec  %xmm10, %xmm2
+        aesdec  %xmm10, %xmm3
+        aesdec  %xmm10, %xmm4
+        jb      DECB_LAST_4
+        movdqa  160(%rcx), %xmm9
+        movdqa  176(%rcx), %xmm10
+        movdqa  192(%rcx), %xmm11
+        cmpl    $14, %r8d
+        aesdec  %xmm9, %xmm1
+        aesdec  %xmm9, %xmm2
+        aesdec  %xmm9, %xmm3
+        aesdec  %xmm9, %xmm4
+        aesdec  %xmm10, %xmm1
+        aesdec  %xmm10, %xmm2
+        aesdec  %xmm10, %xmm3
+        aesdec  %xmm10, %xmm4
+        jb      DECB_LAST_4
+        movdqa  192(%rcx), %xmm9
+        movdqa  208(%rcx), %xmm10
+        movdqa  224(%rcx), %xmm11
+        aesdec  %xmm9, %xmm1
+        aesdec  %xmm9, %xmm2
+        aesdec  %xmm9, %xmm3
+        aesdec  %xmm9, %xmm4
+        aesdec  %xmm10, %xmm1
+        aesdec  %xmm10, %xmm2
+        aesdec  %xmm10, %xmm3
+        aesdec  %xmm10, %xmm4
+DECB_LAST_4:
+        addq    $64, %rdi
+        addq    $64, %rsi
+        decq    %rdx
+        aesdeclast %xmm11, %xmm1
+        aesdeclast %xmm11, %xmm2
+        aesdeclast %xmm11, %xmm3
+        aesdeclast %xmm11, %xmm4
+        movdqu  %xmm1, (%rsi)
+        movdqu  %xmm2, 16(%rsi)
+        movdqu  %xmm3, 32(%rsi)
+        movdqu  %xmm4, 48(%rsi)
+        jne     DECB_LOOP_4
+        addq    $64, %rsi
+DECB_REMAINDER_4:
+        cmpq    $0, %r10
+        je      DECB_END_4
+DECB_LOOP_4_2:
+        movdqu  (%rdi), %xmm1
+        addq    $16, %rdi
+        pxor    (%rcx), %xmm1
+        movdqu  160(%rcx), %xmm2
+        cmpl    $12, %r8d
+        aesdec  16(%rcx), %xmm1
+        aesdec  32(%rcx), %xmm1
+        aesdec  48(%rcx), %xmm1
+        aesdec  64(%rcx), %xmm1
+        aesdec  80(%rcx), %xmm1
+        aesdec  96(%rcx), %xmm1
+        aesdec  112(%rcx), %xmm1
+        aesdec  128(%rcx), %xmm1
+        aesdec  144(%rcx), %xmm1
+        jb      DECB_LAST_4_2
+        cmpl    $14, %r8d
+        movdqu  192(%rcx), %xmm2
+        aesdec  160(%rcx), %xmm1
+        aesdec  176(%rcx), %xmm1
+        jb      DECB_LAST_4_2
+        movdqu  224(%rcx), %xmm2
+        aesdec  192(%rcx), %xmm1
+        aesdec  208(%rcx), %xmm1
+DECB_LAST_4_2:
+        aesdeclast %xmm2, %xmm1
+        movdqu  %xmm1, (%rsi)
+        addq    $16, %rsi
+        decq    %r10
+        jne     DECB_LOOP_4_2
+DECB_END_4:
+        ret
+
+
+
+
+/*
+void AES_128_Key_Expansion(const unsigned char* userkey,
+   unsigned char* key_schedule);
+*/
+.align  16,0x90
+.globl AES_128_Key_Expansion
+AES_128_Key_Expansion:
+# parameter 1: %rdi
+# parameter 2: %rsi
+movl    $10, 240(%rsi)
+
+movdqu  (%rdi), %xmm1
+movdqa    %xmm1, (%rsi)
+
+
+ASSISTS:
+aeskeygenassist $1, %xmm1, %xmm2
+call PREPARE_ROUNDKEY_128
+movdqa %xmm1, 16(%rsi)
+aeskeygenassist $2, %xmm1, %xmm2
+call PREPARE_ROUNDKEY_128
+movdqa %xmm1, 32(%rsi)
+aeskeygenassist $4, %xmm1, %xmm2
+call PREPARE_ROUNDKEY_128
+movdqa %xmm1, 48(%rsi)
+aeskeygenassist $8, %xmm1, %xmm2
+call PREPARE_ROUNDKEY_128
+movdqa %xmm1, 64(%rsi)
+aeskeygenassist $16, %xmm1, %xmm2
+call PREPARE_ROUNDKEY_128
+movdqa %xmm1, 80(%rsi)
+aeskeygenassist $32, %xmm1, %xmm2
+call PREPARE_ROUNDKEY_128
+movdqa %xmm1, 96(%rsi)
+aeskeygenassist $64, %xmm1, %xmm2
+call PREPARE_ROUNDKEY_128
+movdqa %xmm1, 112(%rsi)
+aeskeygenassist $0x80, %xmm1, %xmm2
+call PREPARE_ROUNDKEY_128
+movdqa %xmm1, 128(%rsi)
+aeskeygenassist $0x1b, %xmm1, %xmm2
+call PREPARE_ROUNDKEY_128
+movdqa %xmm1, 144(%rsi)
+aeskeygenassist $0x36, %xmm1, %xmm2
+call PREPARE_ROUNDKEY_128
+movdqa %xmm1, 160(%rsi)
+ret
+
+PREPARE_ROUNDKEY_128:
+pshufd $255, %xmm2, %xmm2
+movdqa %xmm1, %xmm3
+pslldq $4, %xmm3
+pxor %xmm3, %xmm1
+pslldq $4, %xmm3
+pxor %xmm3, %xmm1
+pslldq $4, %xmm3
+pxor %xmm3, %xmm1
+pxor %xmm2, %xmm1
+ret
+
+
+/*
+void AES_192_Key_Expansion (const unsigned char *userkey,
+  unsigned char *key)
+*/
+.globl AES_192_Key_Expansion
+AES_192_Key_Expansion:
+# parameter 1: %rdi
+# parameter 2: %rsi
+
+movdqu (%rdi), %xmm1
+movdqu 16(%rdi), %xmm3
+movdqa %xmm1, (%rsi)
+movdqa %xmm3, %xmm5
+
+aeskeygenassist $0x1, %xmm3, %xmm2
+call PREPARE_ROUNDKEY_192
+shufpd $0, %xmm1, %xmm5
+movdqa %xmm5, 16(%rsi)
+movdqa %xmm1, %xmm6
+shufpd $1, %xmm3, %xmm6
+movdqa %xmm6, 32(%rsi)
+
+aeskeygenassist $0x2, %xmm3, %xmm2
+call PREPARE_ROUNDKEY_192
+movdqa %xmm1, 48(%rsi)
+movdqa %xmm3, %xmm5
+
+aeskeygenassist $0x4, %xmm3, %xmm2
+call PREPARE_ROUNDKEY_192
+shufpd $0, %xmm1, %xmm5
+movdqa %xmm5, 64(%rsi)
+movdqa %xmm1, %xmm6
+shufpd $1, %xmm3, %xmm6
+movdqa %xmm6, 80(%rsi)
+
+aeskeygenassist $0x8, %xmm3, %xmm2
+call PREPARE_ROUNDKEY_192
+movdqa %xmm1, 96(%rsi)
+movdqa %xmm3, %xmm5
+
+aeskeygenassist $0x10, %xmm3, %xmm2
+call PREPARE_ROUNDKEY_192
+shufpd $0, %xmm1, %xmm5
+movdqa %xmm5, 112(%rsi)
+movdqa %xmm1, %xmm6
+shufpd $1, %xmm3, %xmm6
+movdqa %xmm6, 128(%rsi)
+
+aeskeygenassist $0x20, %xmm3, %xmm2
+call PREPARE_ROUNDKEY_192
+movdqa %xmm1, 144(%rsi)
+movdqa %xmm3, %xmm5
+
+aeskeygenassist $0x40, %xmm3, %xmm2
+call PREPARE_ROUNDKEY_192
+shufpd $0, %xmm1, %xmm5
+movdqa %xmm5, 160(%rsi)
+movdqa %xmm1, %xmm6
+shufpd $1, %xmm3, %xmm6
+movdqa %xmm6, 176(%rsi)
+
+aeskeygenassist $0x80, %xmm3, %xmm2
+call PREPARE_ROUNDKEY_192
+movdqa %xmm1, 192(%rsi)
+movdqa %xmm3, 208(%rsi)
+ret
+
+PREPARE_ROUNDKEY_192:
+pshufd $0x55, %xmm2, %xmm2
+movdqu %xmm1, %xmm4
+pslldq $4, %xmm4
+pxor   %xmm4, %xmm1
+
+pslldq $4, %xmm4
+pxor   %xmm4, %xmm1
+pslldq $4, %xmm4
+pxor  %xmm4, %xmm1
+pxor   %xmm2, %xmm1
+pshufd $0xff, %xmm1, %xmm2
+movdqu %xmm3, %xmm4
+pslldq $4, %xmm4
+pxor   %xmm4, %xmm3
+pxor   %xmm2, %xmm3
+ret
+ 
+
+/*
+void AES_256_Key_Expansion (const unsigned char *userkey,
+  unsigned char *key)
+*/
+.globl AES_256_Key_Expansion
+AES_256_Key_Expansion:
+# parameter 1: %rdi
+# parameter 2: %rsi
+
+movdqu (%rdi), %xmm1
+movdqu 16(%rdi), %xmm3
+movdqa %xmm1, (%rsi)
+movdqa %xmm3, 16(%rsi)
+
+aeskeygenassist $0x1, %xmm3, %xmm2
+call MAKE_RK256_a
+movdqa %xmm1, 32(%rsi)
+aeskeygenassist $0x0, %xmm1, %xmm2
+call MAKE_RK256_b
+movdqa %xmm3, 48(%rsi)
+aeskeygenassist $0x2, %xmm3, %xmm2
+call MAKE_RK256_a
+movdqa %xmm1, 64(%rsi)
+aeskeygenassist $0x0, %xmm1, %xmm2
+call MAKE_RK256_b
+movdqa %xmm3, 80(%rsi)
+aeskeygenassist $0x4, %xmm3, %xmm2
+call MAKE_RK256_a
+movdqa %xmm1, 96(%rsi)
+aeskeygenassist $0x0, %xmm1, %xmm2
+call MAKE_RK256_b
+movdqa %xmm3, 112(%rsi)
+aeskeygenassist $0x8, %xmm3, %xmm2
+call MAKE_RK256_a
+movdqa %xmm1, 128(%rsi)
+aeskeygenassist $0x0, %xmm1, %xmm2
+call MAKE_RK256_b
+movdqa %xmm3, 144(%rsi)
+aeskeygenassist $0x10, %xmm3, %xmm2
+call MAKE_RK256_a
+movdqa %xmm1, 160(%rsi)
+aeskeygenassist $0x0, %xmm1, %xmm2
+call MAKE_RK256_b
+movdqa %xmm3, 176(%rsi)
+aeskeygenassist $0x20, %xmm3, %xmm2
+call MAKE_RK256_a
+movdqa %xmm1, 192(%rsi)
+
+aeskeygenassist $0x0, %xmm1, %xmm2
+call MAKE_RK256_b
+movdqa %xmm3, 208(%rsi)
+aeskeygenassist $0x40, %xmm3, %xmm2
+call MAKE_RK256_a
+movdqa %xmm1, 224(%rsi)
+
+ret
+
+MAKE_RK256_a:
+pshufd $0xff, %xmm2, %xmm2
+movdqa %xmm1, %xmm4
+pslldq $4, %xmm4
+pxor   %xmm4, %xmm1
+pslldq $4, %xmm4
+pxor  %xmm4, %xmm1
+pslldq $4, %xmm4
+pxor  %xmm4, %xmm1
+pxor   %xmm2, %xmm1
+ret
+
+MAKE_RK256_b:
+pshufd $0xaa, %xmm2, %xmm2
+movdqa %xmm3, %xmm4
+pslldq $4, %xmm4
+pxor   %xmm4, %xmm3
+pslldq $4, %xmm4
+pxor  %xmm4, %xmm3
+pslldq $4, %xmm4
+pxor  %xmm4, %xmm3
+pxor   %xmm2, %xmm3
+ret
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/arc4.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/arc4.c
new file mode 100644
index 0000000..21ed2e7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/arc4.c
@@ -0,0 +1,178 @@
+/* arc4.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifndef NO_RC4
+
+#include 
+
+#ifdef HAVE_CAVIUM
+    static void wc_Arc4CaviumSetKey(Arc4* arc4, const byte* key, word32 length);
+    static void wc_Arc4CaviumProcess(Arc4* arc4, byte* out, const byte* in,
+                                  word32 length);
+#endif
+
+
+void wc_Arc4SetKey(Arc4* arc4, const byte* key, word32 length)
+{
+    word32 i;
+    word32 keyIndex = 0, stateIndex = 0;
+
+#ifdef HAVE_CAVIUM
+    if (arc4->magic == WOLFSSL_ARC4_CAVIUM_MAGIC)
+        return wc_Arc4CaviumSetKey(arc4, key, length);
+#endif
+
+    arc4->x = 1;
+    arc4->y = 0;
+
+    for (i = 0; i < ARC4_STATE_SIZE; i++)
+        arc4->state[i] = (byte)i;
+
+    for (i = 0; i < ARC4_STATE_SIZE; i++) {
+        word32 a = arc4->state[i];
+        stateIndex += key[keyIndex] + a;
+        stateIndex &= 0xFF;
+        arc4->state[i] = arc4->state[stateIndex];
+        arc4->state[stateIndex] = (byte)a;
+
+        if (++keyIndex >= length)
+            keyIndex = 0;
+    }
+}
+
+
+static INLINE byte MakeByte(word32* x, word32* y, byte* s)
+{
+    word32 a = s[*x], b;
+    *y = (*y+a) & 0xff;
+
+    b = s[*y];
+    s[*x] = (byte)b;
+    s[*y] = (byte)a;
+    *x = (*x+1) & 0xff;
+
+    return s[(a+b) & 0xff];
+}
+
+
+void wc_Arc4Process(Arc4* arc4, byte* out, const byte* in, word32 length)
+{
+    word32 x;
+    word32 y;
+
+#ifdef HAVE_CAVIUM
+    if (arc4->magic == WOLFSSL_ARC4_CAVIUM_MAGIC)
+        return wc_Arc4CaviumProcess(arc4, out, in, length);
+#endif
+
+    x = arc4->x;
+    y = arc4->y;
+
+    while(length--)
+        *out++ = *in++ ^ MakeByte(&x, &y, arc4->state);
+
+    arc4->x = (byte)x;
+    arc4->y = (byte)y;
+}
+
+
+#ifdef HAVE_CAVIUM
+
+#include 
+#include "cavium_common.h"
+
+/* Initiliaze Arc4 for use with Nitrox device */
+int wc_Arc4InitCavium(Arc4* arc4, int devId)
+{
+    if (arc4 == NULL)
+        return -1;
+
+    if (CspAllocContext(CONTEXT_SSL, &arc4->contextHandle, devId) != 0)
+        return -1;
+
+    arc4->devId = devId;
+    arc4->magic = WOLFSSL_ARC4_CAVIUM_MAGIC;
+
+    return 0;
+}
+
+
+/* Free Arc4 from use with Nitrox device */
+void wc_Arc4FreeCavium(Arc4* arc4)
+{
+    if (arc4 == NULL)
+        return;
+
+    if (arc4->magic != WOLFSSL_ARC4_CAVIUM_MAGIC)
+        return;
+
+    CspFreeContext(CONTEXT_SSL, arc4->contextHandle, arc4->devId);
+    arc4->magic = 0;
+}
+
+
+static void wc_Arc4CaviumSetKey(Arc4* arc4, const byte* key, word32 length)
+{
+    word32 requestId;
+
+    if (CspInitializeRc4(CAVIUM_BLOCKING, arc4->contextHandle, length,
+                         (byte*)key, &requestId, arc4->devId) != 0) {
+        WOLFSSL_MSG("Bad Cavium Arc4 Init");
+    }
+}
+
+
+static void wc_Arc4CaviumProcess(Arc4* arc4, byte* out, const byte* in,
+                              word32 length)
+{
+    wolfssl_word offset = 0;
+    word32 requestId;
+
+    while (length > WOLFSSL_MAX_16BIT) {
+        word16 slen = (word16)WOLFSSL_MAX_16BIT;
+        if (CspEncryptRc4(CAVIUM_BLOCKING, arc4->contextHandle,CAVIUM_UPDATE,
+                          slen, (byte*)in + offset, out + offset, &requestId,
+                          arc4->devId) != 0) {
+            WOLFSSL_MSG("Bad Cavium Arc4 Encrypt");
+        }
+        length -= WOLFSSL_MAX_16BIT;
+        offset += WOLFSSL_MAX_16BIT;
+    }
+    if (length) {
+        word16 slen = (word16)length;
+        if (CspEncryptRc4(CAVIUM_BLOCKING, arc4->contextHandle,CAVIUM_UPDATE,
+                          slen, (byte*)in + offset, out + offset, &requestId,
+                          arc4->devId) != 0) {
+            WOLFSSL_MSG("Bad Cavium Arc4 Encrypt");
+        }
+    }
+}
+
+#endif /* HAVE_CAVIUM */
+
+#endif /* NO_RC4 */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/asm.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/asm.c
new file mode 100644
index 0000000..9f84585
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/asm.c
@@ -0,0 +1,1618 @@
+/* asm.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+/*
+ * Based on public domain TomsFastMath 0.10 by Tom St Denis, tomstdenis@iahu.ca,
+ * http://math.libtomcrypt.com
+ */
+
+
+/******************************************************************/
+/* fp_montgomery_reduce.c asm or generic */
+
+
+/* Each platform needs to query info type 1 from cpuid to see if aesni is
+ * supported. Also, let's setup a macro for proper linkage w/o ABI conflicts
+ */
+
+#if defined(HAVE_INTEL_MULX)
+#ifndef _MSC_VER
+    #define cpuid(reg, leaf, sub)\
+            __asm__ __volatile__ ("cpuid":\
+             "=a" (reg[0]), "=b" (reg[1]), "=c" (reg[2]), "=d" (reg[3]) :\
+             "a" (leaf), "c"(sub));
+
+    #define XASM_LINK(f) asm(f)
+#else
+
+    #include 
+    #define cpuid(a,b) __cpuid((int*)a,b)
+
+    #define XASM_LINK(f)
+
+#endif /* _MSC_VER */
+
+#define EAX 0
+#define EBX 1
+#define ECX 2 
+#define EDX 3
+    
+#define CPUID_AVX1   0x1
+#define CPUID_AVX2   0x2
+#define CPUID_RDRAND 0x4
+#define CPUID_RDSEED 0x8
+#define CPUID_BMI2   0x10   /* MULX, RORX */
+#define CPUID_ADX    0x20   /* ADCX, ADOX */
+
+#define IS_INTEL_AVX1       (cpuid_flags&CPUID_AVX1)
+#define IS_INTEL_AVX2       (cpuid_flags&CPUID_AVX2)
+#define IS_INTEL_BMI2       (cpuid_flags&CPUID_BMI2)
+#define IS_INTEL_ADX        (cpuid_flags&CPUID_ADX)
+#define IS_INTEL_RDRAND     (cpuid_flags&CPUID_RDRAND)
+#define IS_INTEL_RDSEED     (cpuid_flags&CPUID_RDSEED)
+#define SET_FLAGS         
+
+static word32 cpuid_check = 0 ;
+static word32 cpuid_flags = 0 ;
+
+static word32 cpuid_flag(word32 leaf, word32 sub, word32 num, word32 bit) {
+    int got_intel_cpu=0;
+    unsigned int reg[5]; 
+    
+    reg[4] = '\0' ;
+    cpuid(reg, 0, 0);  
+    if(memcmp((char *)&(reg[EBX]), "Genu", 4) == 0 &&  
+                memcmp((char *)&(reg[EDX]), "ineI", 4) == 0 &&  
+                memcmp((char *)&(reg[ECX]), "ntel", 4) == 0) {  
+        got_intel_cpu = 1;  
+    }    
+    if (got_intel_cpu) {
+        cpuid(reg, leaf, sub);
+        return((reg[num]>>bit)&0x1) ;
+    }
+    return 0 ;
+}
+
+INLINE static int set_cpuid_flags(void) {  
+    if(cpuid_check == 0) {
+        if(cpuid_flag(7, 0, EBX, 8)){  cpuid_flags |= CPUID_BMI2 ; }
+        if(cpuid_flag(7, 0, EBX,19)){  cpuid_flags |= CPUID_ADX  ; }
+		cpuid_check = 1 ;
+		return 0 ;
+    }
+    return 1 ;
+}
+
+#define RETURN return
+#define IF_HAVE_INTEL_MULX(func, ret)    \
+   if(cpuid_check==0)set_cpuid_flags() ; \
+   if(IS_INTEL_BMI2 && IS_INTEL_ADX){  func;  ret ;  }
+
+#else
+    #define IF_HAVE_INTEL_MULX(func, ret)
+#endif
+
+#if defined(TFM_X86) && !defined(TFM_SSE2) 
+/* x86-32 code */
+
+#define MONT_START 
+#define MONT_FINI
+#define LOOP_END
+#define LOOP_START \
+   mu = c[x] * mp
+
+#define INNERMUL                                          \
+__asm__(                                                      \
+   "movl %5,%%eax \n\t"                                   \
+   "mull %4       \n\t"                                   \
+   "addl %1,%%eax \n\t"                                   \
+   "adcl $0,%%edx \n\t"                                   \
+   "addl %%eax,%0 \n\t"                                   \
+   "adcl $0,%%edx \n\t"                                   \
+   "movl %%edx,%1 \n\t"                                   \
+:"=g"(_c[LO]), "=r"(cy)                                   \
+:"0"(_c[LO]), "1"(cy), "g"(mu), "g"(*tmpm++)              \
+: "%eax", "%edx", "cc")
+
+#define PROPCARRY                           \
+__asm__(                                        \
+   "addl   %1,%0    \n\t"                   \
+   "setb   %%al     \n\t"                   \
+   "movzbl %%al,%1 \n\t"                    \
+:"=g"(_c[LO]), "=r"(cy)                     \
+:"0"(_c[LO]), "1"(cy)                       \
+: "%eax", "cc")
+
+/******************************************************************/
+#elif defined(TFM_X86_64)
+/* x86-64 code */
+
+#define MONT_START 
+#define MONT_FINI
+#define LOOP_END
+#define LOOP_START \
+   mu = c[x] * mp;
+
+#define INNERMUL                                          \
+__asm__(                                                      \
+   "movq %5,%%rax \n\t"                                   \
+   "mulq %4       \n\t"                                   \
+   "addq %1,%%rax \n\t"                                   \
+   "adcq $0,%%rdx \n\t"                                   \
+   "addq %%rax,%0 \n\t"                                   \
+   "adcq $0,%%rdx \n\t"                                   \
+   "movq %%rdx,%1 \n\t"                                   \
+:"=g"(_c[LO]), "=r"(cy)                                   \
+:"0"(_c[LO]), "1"(cy), "r"(mu), "r"(*tmpm++)              \
+: "%rax", "%rdx", "cc")
+
+#if defined(HAVE_INTEL_MULX)
+#define MULX_INIT(a0, c0, cy)\
+    __asm__ volatile(                                     \
+             "xorq  %%r10, %%r10\n\t"                     \
+             "movq  %1,%%rdx\n\t"                         \
+             "addq  %2, %0\n\t"       /* c0+=cy; Set CF, OF */ \
+             "adoxq %%r10, %%r10\n\t" /* Reset   OF */    \
+             :"+m"(c0):"r"(a0),"r"(cy):"%r8","%r9", "%r10","%r11","%r12","%rdx") ; \
+
+#define MULX_INNERMUL_R1(c0, c1, pre, rdx)\
+   {                                                      \
+    __asm__  volatile (                                   \
+         "movq  %3, %%rdx\n\t"                            \
+         "mulx  %%r11,%%r9, %%r8 \n\t"                    \
+         "movq  %2, %%r12\n\t"                            \
+         "adoxq  %%r9,%0     \n\t"                        \
+         "adcxq  %%r8,%1     \n\t"                        \
+         :"+r"(c0),"+r"(c1):"m"(pre),"r"(rdx):"%r8","%r9", "%r10", "%r11","%r12","%rdx"    \
+    ); }
+    
+
+#define MULX_INNERMUL_R2(c0, c1, pre, rdx)\
+   {                                                      \
+    __asm__  volatile (                                   \
+         "movq  %3, %%rdx\n\t"                            \
+         "mulx  %%r12,%%r9, %%r8 \n\t"                    \
+         "movq  %2, %%r11\n\t"                            \
+         "adoxq  %%r9,%0     \n\t"                        \
+         "adcxq  %%r8,%1     \n\t"                        \
+         :"+r"(c0),"+r"(c1):"m"(pre),"r"(rdx):"%r8","%r9", "%r10", "%r11","%r12","%rdx"    \
+    ); }
+
+#define MULX_LOAD_R1(val)\
+    __asm__  volatile (                                   \
+        "movq %0, %%r11\n\t"\
+        ::"m"(val):"%r8","%r9", "%r10", "%r11","%r12","%rdx"\
+) ;
+
+#define MULX_INNERMUL_LAST(c0, c1, rdx)\
+   {                                                      \
+    __asm__  volatile (                                   \
+         "movq   %2, %%rdx\n\t"                           \
+         "mulx   %%r12,%%r9, %%r8 \n\t"                   \
+         "movq   $0, %%r10      \n\t"                     \
+         "adoxq  %%r10, %%r9   \n\t"                      \
+         "adcq   $0,%%r8       \n\t"                      \
+         "addq   %%r9,%0       \n\t"                      \
+         "adcq   $0,%%r8       \n\t"                      \
+         "movq   %%r8,%1       \n\t"                      \
+         :"+m"(c0),"=m"(c1):"r"(rdx):"%r8","%r9","%r10", "%r11", "%r12","%rdx"\
+    ); }
+
+#define MULX_INNERMUL8(x,y,z,cy)\
+{       word64 rdx = y ;\
+        MULX_LOAD_R1(x[0]) ;\
+        MULX_INIT(y, _c0, cy) ; /* rdx=y; z0+=cy; */ \
+        MULX_INNERMUL_R1(_c0, _c1, x[1], rdx) ;\
+        MULX_INNERMUL_R2(_c1, _c2, x[2], rdx) ;\
+        MULX_INNERMUL_R1(_c2, _c3, x[3], rdx) ;\
+        MULX_INNERMUL_R2(_c3, _c4, x[4], rdx) ;\
+        MULX_INNERMUL_R1(_c4, _c5, x[5], rdx) ;\
+        MULX_INNERMUL_R2(_c5, _c6, x[6], rdx) ;\
+        MULX_INNERMUL_R1(_c6, _c7, x[7], rdx) ;\
+        MULX_INNERMUL_LAST(_c7, cy, rdx) ;\
+}
+#define INNERMUL8_MULX \
+{\
+    MULX_INNERMUL8(tmpm, mu, _c, cy);\
+}
+#endif
+
+#define INNERMUL8 \
+ __asm__(                  \
+ "movq 0(%5),%%rax    \n\t"  \
+ "movq 0(%2),%%r10    \n\t"  \
+ "movq 0x8(%5),%%r11  \n\t"  \
+ "mulq %4             \n\t"  \
+ "addq %%r10,%%rax    \n\t"  \
+ "adcq $0,%%rdx       \n\t"  \
+ "movq 0x8(%2),%%r10  \n\t"  \
+ "addq %3,%%rax       \n\t"  \
+ "adcq $0,%%rdx       \n\t"  \
+ "movq %%rax,0(%0)    \n\t"  \
+ "movq %%rdx,%1       \n\t"  \
+ \
+ "movq %%r11,%%rax    \n\t"  \
+ "movq 0x10(%5),%%r11 \n\t"  \
+ "mulq %4             \n\t"  \
+ "addq %%r10,%%rax    \n\t"  \
+ "adcq $0,%%rdx       \n\t"  \
+ "movq 0x10(%2),%%r10 \n\t"  \
+ "addq %3,%%rax       \n\t"  \
+ "adcq $0,%%rdx       \n\t"  \
+ "movq %%rax,0x8(%0)  \n\t"  \
+ "movq %%rdx,%1       \n\t"  \
+ \
+ "movq %%r11,%%rax    \n\t"  \
+ "movq 0x18(%5),%%r11 \n\t"  \
+ "mulq %4             \n\t"  \
+ "addq %%r10,%%rax    \n\t"  \
+ "adcq $0,%%rdx       \n\t"  \
+ "movq 0x18(%2),%%r10 \n\t"  \
+ "addq %3,%%rax       \n\t"  \
+ "adcq $0,%%rdx       \n\t"  \
+ "movq %%rax,0x10(%0) \n\t"  \
+ "movq %%rdx,%1       \n\t"  \
+ \
+ "movq %%r11,%%rax    \n\t"  \
+ "movq 0x20(%5),%%r11 \n\t"  \
+ "mulq %4             \n\t"  \
+ "addq %%r10,%%rax    \n\t"  \
+ "adcq $0,%%rdx       \n\t"  \
+ "movq 0x20(%2),%%r10 \n\t"  \
+ "addq %3,%%rax       \n\t"  \
+ "adcq $0,%%rdx       \n\t"  \
+ "movq %%rax,0x18(%0) \n\t"  \
+ "movq %%rdx,%1       \n\t"  \
+ \
+ "movq %%r11,%%rax    \n\t"  \
+ "movq 0x28(%5),%%r11 \n\t"  \
+ "mulq %4             \n\t"  \
+ "addq %%r10,%%rax    \n\t"  \
+ "adcq $0,%%rdx       \n\t"  \
+ "movq 0x28(%2),%%r10 \n\t"  \
+ "addq %3,%%rax       \n\t"  \
+ "adcq $0,%%rdx       \n\t"  \
+ "movq %%rax,0x20(%0) \n\t"  \
+ "movq %%rdx,%1       \n\t"  \
+ \
+ "movq %%r11,%%rax    \n\t"  \
+ "movq 0x30(%5),%%r11 \n\t"  \
+ "mulq %4             \n\t"  \
+ "addq %%r10,%%rax    \n\t"  \
+ "adcq $0,%%rdx       \n\t"  \
+ "movq 0x30(%2),%%r10 \n\t"  \
+ "addq %3,%%rax       \n\t"  \
+ "adcq $0,%%rdx       \n\t"  \
+ "movq %%rax,0x28(%0) \n\t"  \
+ "movq %%rdx,%1       \n\t"  \
+ \
+ "movq %%r11,%%rax    \n\t"  \
+ "movq 0x38(%5),%%r11 \n\t"  \
+ "mulq %4             \n\t"  \
+ "addq %%r10,%%rax    \n\t"  \
+ "adcq $0,%%rdx       \n\t"  \
+ "movq 0x38(%2),%%r10 \n\t"  \
+ "addq %3,%%rax       \n\t"  \
+ "adcq $0,%%rdx       \n\t"  \
+ "movq %%rax,0x30(%0) \n\t"  \
+ "movq %%rdx,%1       \n\t"  \
+ \
+ "movq %%r11,%%rax    \n\t"  \
+ "mulq %4             \n\t"  \
+ "addq %%r10,%%rax    \n\t"  \
+ "adcq $0,%%rdx       \n\t"  \
+ "addq %3,%%rax       \n\t"  \
+ "adcq $0,%%rdx       \n\t"  \
+ "movq %%rax,0x38(%0) \n\t"  \
+ "movq %%rdx,%1       \n\t"  \
+ \
+:"=r"(_c), "=r"(cy)                    \
+: "0"(_c),  "1"(cy), "g"(mu), "r"(tmpm)\
+: "%rax", "%rdx", "%r10", "%r11", "cc")\
+
+#define PROPCARRY                           \
+__asm__(                                        \
+   "addq   %1,%0    \n\t"                   \
+   "setb   %%al     \n\t"                   \
+   "movzbq %%al,%1 \n\t"                    \
+:"=g"(_c[LO]), "=r"(cy)                     \
+:"0"(_c[LO]), "1"(cy)                       \
+: "%rax", "cc")
+
+/******************************************************************/
+#elif defined(TFM_SSE2)  
+/* SSE2 code (assumes 32-bit fp_digits) */
+/* XMM register assignments:
+ * xmm0  *tmpm++, then Mu * (*tmpm++)
+ * xmm1  c[x], then Mu
+ * xmm2  mp
+ * xmm3  cy
+ * xmm4  _c[LO]
+ */
+
+#define MONT_START \
+   __asm__("movd %0,%%mm2"::"g"(mp))
+
+#define MONT_FINI \
+   __asm__("emms")
+
+#define LOOP_START          \
+__asm__(                        \
+"movd %0,%%mm1        \n\t" \
+"pxor %%mm3,%%mm3     \n\t" \
+"pmuludq %%mm2,%%mm1  \n\t" \
+:: "g"(c[x]))
+
+/* pmuludq on mmx registers does a 32x32->64 multiply. */
+#define INNERMUL               \
+__asm__(                           \
+   "movd %1,%%mm4        \n\t" \
+   "movd %2,%%mm0        \n\t" \
+   "paddq %%mm4,%%mm3    \n\t" \
+   "pmuludq %%mm1,%%mm0  \n\t" \
+   "paddq %%mm0,%%mm3    \n\t" \
+   "movd %%mm3,%0        \n\t" \
+   "psrlq $32, %%mm3     \n\t" \
+:"=g"(_c[LO]) : "0"(_c[LO]), "g"(*tmpm++) );
+
+#define INNERMUL8 \
+__asm__(                           \
+   "movd 0(%1),%%mm4     \n\t" \
+   "movd 0(%2),%%mm0     \n\t" \
+   "paddq %%mm4,%%mm3    \n\t" \
+   "pmuludq %%mm1,%%mm0  \n\t" \
+   "movd 4(%2),%%mm5     \n\t" \
+   "paddq %%mm0,%%mm3    \n\t" \
+   "movd 4(%1),%%mm6     \n\t" \
+   "movd %%mm3,0(%0)     \n\t" \
+   "psrlq $32, %%mm3     \n\t" \
+\
+   "paddq %%mm6,%%mm3    \n\t" \
+   "pmuludq %%mm1,%%mm5  \n\t" \
+   "movd 8(%2),%%mm6     \n\t" \
+   "paddq %%mm5,%%mm3    \n\t" \
+   "movd 8(%1),%%mm7     \n\t" \
+   "movd %%mm3,4(%0)     \n\t" \
+   "psrlq $32, %%mm3     \n\t" \
+\
+   "paddq %%mm7,%%mm3    \n\t" \
+   "pmuludq %%mm1,%%mm6  \n\t" \
+   "movd 12(%2),%%mm7    \n\t" \
+   "paddq %%mm6,%%mm3    \n\t" \
+   "movd 12(%1),%%mm5     \n\t" \
+   "movd %%mm3,8(%0)     \n\t" \
+   "psrlq $32, %%mm3     \n\t" \
+\
+   "paddq %%mm5,%%mm3    \n\t" \
+   "pmuludq %%mm1,%%mm7  \n\t" \
+   "movd 16(%2),%%mm5    \n\t" \
+   "paddq %%mm7,%%mm3    \n\t" \
+   "movd 16(%1),%%mm6    \n\t" \
+   "movd %%mm3,12(%0)    \n\t" \
+   "psrlq $32, %%mm3     \n\t" \
+\
+   "paddq %%mm6,%%mm3    \n\t" \
+   "pmuludq %%mm1,%%mm5  \n\t" \
+   "movd 20(%2),%%mm6    \n\t" \
+   "paddq %%mm5,%%mm3    \n\t" \
+   "movd 20(%1),%%mm7    \n\t" \
+   "movd %%mm3,16(%0)    \n\t" \
+   "psrlq $32, %%mm3     \n\t" \
+\
+   "paddq %%mm7,%%mm3    \n\t" \
+   "pmuludq %%mm1,%%mm6  \n\t" \
+   "movd 24(%2),%%mm7    \n\t" \
+   "paddq %%mm6,%%mm3    \n\t" \
+   "movd 24(%1),%%mm5     \n\t" \
+   "movd %%mm3,20(%0)    \n\t" \
+   "psrlq $32, %%mm3     \n\t" \
+\
+   "paddq %%mm5,%%mm3    \n\t" \
+   "pmuludq %%mm1,%%mm7  \n\t" \
+   "movd 28(%2),%%mm5    \n\t" \
+   "paddq %%mm7,%%mm3    \n\t" \
+   "movd 28(%1),%%mm6    \n\t" \
+   "movd %%mm3,24(%0)    \n\t" \
+   "psrlq $32, %%mm3     \n\t" \
+\
+   "paddq %%mm6,%%mm3    \n\t" \
+   "pmuludq %%mm1,%%mm5  \n\t" \
+   "paddq %%mm5,%%mm3    \n\t" \
+   "movd %%mm3,28(%0)    \n\t" \
+   "psrlq $32, %%mm3     \n\t" \
+:"=r"(_c) : "0"(_c), "r"(tmpm) );
+
+/* TAO switched tmpm from "g" to "r" after gcc tried to index the indexed stack
+   pointer */
+
+#define LOOP_END \
+__asm__( "movd %%mm3,%0  \n" :"=r"(cy))
+
+#define PROPCARRY                           \
+__asm__(                                        \
+   "addl   %1,%0    \n\t"                   \
+   "setb   %%al     \n\t"                   \
+   "movzbl %%al,%1 \n\t"                    \
+:"=g"(_c[LO]), "=r"(cy)                     \
+:"0"(_c[LO]), "1"(cy)                       \
+: "%eax", "cc")
+
+/******************************************************************/
+#elif defined(TFM_ARM)
+   /* ARMv4 code */
+
+#define MONT_START 
+#define MONT_FINI
+#define LOOP_END
+#define LOOP_START \
+   mu = c[x] * mp
+
+
+#ifdef __thumb__
+
+#define INNERMUL                    \
+__asm__(                                \
+    " LDR    r0,%1            \n\t" \
+    " ADDS   r0,r0,%0         \n\t" \
+    " ITE    CS               \n\t" \
+    " MOVCS  %0,#1            \n\t" \
+    " MOVCC  %0,#0            \n\t" \
+    " UMLAL  r0,%0,%3,%4      \n\t" \
+    " STR    r0,%1            \n\t" \
+:"=r"(cy),"=m"(_c[0]):"0"(cy),"r"(mu),"r"(*tmpm++),"m"(_c[0]):"r0","cc");
+
+#define PROPCARRY                  \
+__asm__(                               \
+    " LDR   r0,%1            \n\t" \
+    " ADDS  r0,r0,%0         \n\t" \
+    " STR   r0,%1            \n\t" \
+    " ITE   CS               \n\t" \
+    " MOVCS %0,#1            \n\t" \
+    " MOVCC %0,#0            \n\t" \
+:"=r"(cy),"=m"(_c[0]):"0"(cy),"m"(_c[0]):"r0","cc");
+
+
+/* TAO thumb mode uses ite (if then else) to detect carry directly
+ * fixed unmatched constraint warning by changing 1 to m  */
+
+#else  /* __thumb__ */
+
+#define INNERMUL                    \
+__asm__(                                \
+    " LDR    r0,%1            \n\t" \
+    " ADDS   r0,r0,%0         \n\t" \
+    " MOVCS  %0,#1            \n\t" \
+    " MOVCC  %0,#0            \n\t" \
+    " UMLAL  r0,%0,%3,%4      \n\t" \
+    " STR    r0,%1            \n\t" \
+:"=r"(cy),"=m"(_c[0]):"0"(cy),"r"(mu),"r"(*tmpm++),"1"(_c[0]):"r0","cc");
+
+#define PROPCARRY                  \
+__asm__(                               \
+    " LDR   r0,%1            \n\t" \
+    " ADDS  r0,r0,%0         \n\t" \
+    " STR   r0,%1            \n\t" \
+    " MOVCS %0,#1            \n\t" \
+    " MOVCC %0,#0            \n\t" \
+:"=r"(cy),"=m"(_c[0]):"0"(cy),"1"(_c[0]):"r0","cc");
+
+#endif /* __thumb__ */
+
+#elif defined(TFM_PPC32)
+
+/* PPC32 */
+#define MONT_START 
+#define MONT_FINI
+#define LOOP_END
+#define LOOP_START \
+   mu = c[x] * mp
+
+#define INNERMUL                     \
+__asm__(                                 \
+   " mullw    16,%3,%4       \n\t"   \
+   " mulhwu   17,%3,%4       \n\t"   \
+   " addc     16,16,%0       \n\t"   \
+   " addze    17,17          \n\t"   \
+   " lwz      18,%1          \n\t"   \
+   " addc     16,16,18       \n\t"   \
+   " addze    %0,17          \n\t"   \
+   " stw      16,%1          \n\t"   \
+:"=r"(cy),"=m"(_c[0]):"0"(cy),"r"(mu),"r"(tmpm[0]),"1"(_c[0]):"16", "17", "18","cc"); ++tmpm;
+
+#define PROPCARRY                    \
+__asm__(                                 \
+   " lwz      16,%1         \n\t"    \
+   " addc     16,16,%0      \n\t"    \
+   " stw      16,%1         \n\t"    \
+   " xor      %0,%0,%0      \n\t"    \
+   " addze    %0,%0         \n\t"    \
+:"=r"(cy),"=m"(_c[0]):"0"(cy),"1"(_c[0]):"16","cc");
+
+#elif defined(TFM_PPC64)
+
+/* PPC64 */
+#define MONT_START 
+#define MONT_FINI
+#define LOOP_END
+#define LOOP_START \
+   mu = c[x] * mp
+
+#define INNERMUL                     \
+__asm__(                                 \
+   " mulld    16,%3,%4       \n\t"   \
+   " mulhdu   17,%3,%4       \n\t"   \
+   " addc     16,16,%0       \n\t"   \
+   " addze    17,17          \n\t"   \
+   " ldx      18,0,%1        \n\t"   \
+   " addc     16,16,18       \n\t"   \
+   " addze    %0,17          \n\t"   \
+   " sdx      16,0,%1        \n\t"   \
+:"=r"(cy),"=m"(_c[0]):"0"(cy),"r"(mu),"r"(tmpm[0]),"1"(_c[0]):"16", "17", "18","cc"); ++tmpm;
+
+#define PROPCARRY                    \
+__asm__(                                 \
+   " ldx      16,0,%1       \n\t"    \
+   " addc     16,16,%0      \n\t"    \
+   " sdx      16,0,%1       \n\t"    \
+   " xor      %0,%0,%0      \n\t"    \
+   " addze    %0,%0         \n\t"    \
+:"=r"(cy),"=m"(_c[0]):"0"(cy),"1"(_c[0]):"16","cc");
+
+/******************************************************************/
+
+#elif defined(TFM_AVR32)
+
+/* AVR32 */
+#define MONT_START 
+#define MONT_FINI
+#define LOOP_END
+#define LOOP_START \
+   mu = c[x] * mp
+
+#define INNERMUL                    \
+__asm__(                                \
+    " ld.w   r2,%1            \n\t" \
+    " add    r2,%0            \n\t" \
+    " eor    r3,r3            \n\t" \
+    " acr    r3               \n\t" \
+    " macu.d r2,%3,%4         \n\t" \
+    " st.w   %1,r2            \n\t" \
+    " mov    %0,r3            \n\t" \
+:"=r"(cy),"=r"(_c):"0"(cy),"r"(mu),"r"(*tmpm++),"1"(_c):"r2","r3");
+
+#define PROPCARRY                    \
+__asm__(                                 \
+   " ld.w     r2,%1         \n\t"    \
+   " add      r2,%0         \n\t"    \
+   " st.w     %1,r2         \n\t"    \
+   " eor      %0,%0         \n\t"    \
+   " acr      %0            \n\t"    \
+:"=r"(cy),"=r"(&_c[0]):"0"(cy),"1"(&_c[0]):"r2","cc");
+
+#else
+
+/* ISO C code */
+#define MONT_START 
+#define MONT_FINI
+#define LOOP_END
+#define LOOP_START \
+   mu = c[x] * mp
+
+#define INNERMUL                                      \
+   do { fp_word t;                                    \
+   t  = ((fp_word)_c[0] + (fp_word)cy) +              \
+                (((fp_word)mu) * ((fp_word)*tmpm++)); \
+   _c[0] = (fp_digit)t;                               \
+   cy = (fp_digit)(t >> DIGIT_BIT);                   \
+   } while (0)
+
+#define PROPCARRY \
+   do { fp_digit t = _c[0] += cy; cy = (t < cy); } while (0)
+
+#endif
+/******************************************************************/
+
+
+#define LO  0
+/* end fp_montogomery_reduce.c asm */
+
+
+/* start fp_sqr_comba.c asm */
+#if defined(TFM_X86)
+
+/* x86-32 optimized */
+
+#define COMBA_START
+
+#define CLEAR_CARRY \
+   c0 = c1 = c2 = 0;
+
+#define COMBA_STORE(x) \
+   x = c0;
+
+#define COMBA_STORE2(x) \
+   x = c1;
+
+#define CARRY_FORWARD \
+   do { c0 = c1; c1 = c2; c2 = 0; } while (0);
+
+#define COMBA_FINI
+
+#define SQRADD(i, j)                                      \
+__asm__(                                            \
+     "movl  %6,%%eax     \n\t"                            \
+     "mull  %%eax        \n\t"                            \
+     "addl  %%eax,%0     \n\t"                            \
+     "adcl  %%edx,%1     \n\t"                            \
+     "adcl  $0,%2        \n\t"                            \
+     :"=r"(c0), "=r"(c1), "=r"(c2): "0"(c0), "1"(c1), "2"(c2), "m"(i) :"%eax","%edx","cc");
+
+#define SQRADD2(i, j)                                     \
+__asm__(                                            \
+     "movl  %6,%%eax     \n\t"                            \
+     "mull  %7           \n\t"                            \
+     "addl  %%eax,%0     \n\t"                            \
+     "adcl  %%edx,%1     \n\t"                            \
+     "adcl  $0,%2        \n\t"                            \
+     "addl  %%eax,%0     \n\t"                            \
+     "adcl  %%edx,%1     \n\t"                            \
+     "adcl  $0,%2        \n\t"                            \
+     :"=r"(c0), "=r"(c1), "=r"(c2): "0"(c0), "1"(c1), "2"(c2), "m"(i), "m"(j)  :"%eax","%edx", "cc");
+
+#define SQRADDSC(i, j)                                    \
+__asm__(                                                     \
+     "movl  %3,%%eax     \n\t"                            \
+     "mull  %4           \n\t"                            \
+     "movl  %%eax,%0     \n\t"                            \
+     "movl  %%edx,%1     \n\t"                            \
+     "xorl  %2,%2        \n\t"                            \
+     :"=r"(sc0), "=r"(sc1), "=r"(sc2): "g"(i), "g"(j) :"%eax","%edx","cc");
+
+/* TAO removed sc0,1,2 as input to remove warning so %6,%7 become %3,%4 */
+
+#define SQRADDAC(i, j)                                    \
+__asm__(                                                     \
+     "movl  %6,%%eax     \n\t"                            \
+     "mull  %7           \n\t"                            \
+     "addl  %%eax,%0     \n\t"                            \
+     "adcl  %%edx,%1     \n\t"                            \
+     "adcl  $0,%2        \n\t"                            \
+     :"=r"(sc0), "=r"(sc1), "=r"(sc2): "0"(sc0), "1"(sc1), "2"(sc2), "g"(i), "g"(j) :"%eax","%edx","cc");
+
+#define SQRADDDB                                          \
+__asm__(                                                     \
+     "addl %6,%0         \n\t"                            \
+     "adcl %7,%1         \n\t"                            \
+     "adcl %8,%2         \n\t"                            \
+     "addl %6,%0         \n\t"                            \
+     "adcl %7,%1         \n\t"                            \
+     "adcl %8,%2         \n\t"                            \
+     :"=r"(c0), "=r"(c1), "=r"(c2) : "0"(c0), "1"(c1), "2"(c2), "r"(sc0), "r"(sc1), "r"(sc2) : "cc");
+
+#elif defined(TFM_X86_64)
+/* x86-64 optimized */
+
+#define COMBA_START
+
+#define CLEAR_CARRY \
+   c0 = c1 = c2 = 0;
+
+#define COMBA_STORE(x) \
+   x = c0;
+
+#define COMBA_STORE2(x) \
+   x = c1;
+
+#define CARRY_FORWARD \
+   do { c0 = c1; c1 = c2; c2 = 0; } while (0);
+
+#define COMBA_FINI
+
+#define SQRADD(i, j)                                      \
+__asm__(                                                     \
+     "movq  %6,%%rax     \n\t"                            \
+     "mulq  %%rax        \n\t"                            \
+     "addq  %%rax,%0     \n\t"                            \
+     "adcq  %%rdx,%1     \n\t"                            \
+     "adcq  $0,%2        \n\t"                            \
+     :"=r"(c0), "=r"(c1), "=r"(c2): "0"(c0), "1"(c1), "2"(c2), "g"(i) :"%rax","%rdx","cc");
+
+#define SQRADD2(i, j)                                     \
+__asm__(                                                     \
+     "movq  %6,%%rax     \n\t"                            \
+     "mulq  %7           \n\t"                            \
+     "addq  %%rax,%0     \n\t"                            \
+     "adcq  %%rdx,%1     \n\t"                            \
+     "adcq  $0,%2        \n\t"                            \
+     "addq  %%rax,%0     \n\t"                            \
+     "adcq  %%rdx,%1     \n\t"                            \
+     "adcq  $0,%2        \n\t"                            \
+     :"=r"(c0), "=r"(c1), "=r"(c2): "0"(c0), "1"(c1), "2"(c2), "g"(i), "g"(j)  :"%rax","%rdx","cc");
+
+#define SQRADDSC(i, j)                                    \
+__asm__(                                                     \
+     "movq  %3,%%rax     \n\t"                            \
+     "mulq  %4           \n\t"                            \
+     "movq  %%rax,%0     \n\t"                            \
+     "movq  %%rdx,%1     \n\t"                            \
+     "xorq  %2,%2        \n\t"                            \
+     :"=r"(sc0), "=r"(sc1), "=r"(sc2): "g"(i), "g"(j) :"%rax","%rdx","cc");
+
+/* TAO removed sc0,1,2 as input to remove warning so %6,%7 become %3,%4 */
+
+#define SQRADDAC(i, j)                                                         \
+__asm__(                                                     \
+     "movq  %6,%%rax     \n\t"                            \
+     "mulq  %7           \n\t"                            \
+     "addq  %%rax,%0     \n\t"                            \
+     "adcq  %%rdx,%1     \n\t"                            \
+     "adcq  $0,%2        \n\t"                            \
+     :"=r"(sc0), "=r"(sc1), "=r"(sc2): "0"(sc0), "1"(sc1), "2"(sc2), "g"(i), "g"(j) :"%rax","%rdx","cc");
+
+#define SQRADDDB                                          \
+__asm__(                                                     \
+     "addq %6,%0         \n\t"                            \
+     "adcq %7,%1         \n\t"                            \
+     "adcq %8,%2         \n\t"                            \
+     "addq %6,%0         \n\t"                            \
+     "adcq %7,%1         \n\t"                            \
+     "adcq %8,%2         \n\t"                            \
+     :"=r"(c0), "=r"(c1), "=r"(c2) : "0"(c0), "1"(c1), "2"(c2), "r"(sc0), "r"(sc1), "r"(sc2) : "cc");
+
+#elif defined(TFM_SSE2)
+
+/* SSE2 Optimized */
+#define COMBA_START
+
+#define CLEAR_CARRY \
+   c0 = c1 = c2 = 0;
+
+#define COMBA_STORE(x) \
+   x = c0;
+
+#define COMBA_STORE2(x) \
+   x = c1;
+
+#define CARRY_FORWARD \
+   do { c0 = c1; c1 = c2; c2 = 0; } while (0);
+
+#define COMBA_FINI \
+   __asm__("emms");
+
+#define SQRADD(i, j)                                      \
+__asm__(                                            \
+     "movd  %6,%%mm0     \n\t"                            \
+     "pmuludq %%mm0,%%mm0\n\t"                            \
+     "movd  %%mm0,%%eax  \n\t"                            \
+     "psrlq $32,%%mm0    \n\t"                            \
+     "addl  %%eax,%0     \n\t"                            \
+     "movd  %%mm0,%%eax  \n\t"                            \
+     "adcl  %%eax,%1     \n\t"                            \
+     "adcl  $0,%2        \n\t"                            \
+     :"=r"(c0), "=r"(c1), "=r"(c2): "0"(c0), "1"(c1), "2"(c2), "m"(i) :"%eax","cc");
+
+#define SQRADD2(i, j)                                     \
+__asm__(                                            \
+     "movd  %6,%%mm0     \n\t"                            \
+     "movd  %7,%%mm1     \n\t"                            \
+     "pmuludq %%mm1,%%mm0\n\t"                            \
+     "movd  %%mm0,%%eax  \n\t"                            \
+     "psrlq $32,%%mm0    \n\t"                            \
+     "movd  %%mm0,%%edx  \n\t"                            \
+     "addl  %%eax,%0     \n\t"                            \
+     "adcl  %%edx,%1     \n\t"                            \
+     "adcl  $0,%2        \n\t"                            \
+     "addl  %%eax,%0     \n\t"                            \
+     "adcl  %%edx,%1     \n\t"                            \
+     "adcl  $0,%2        \n\t"                            \
+     :"=r"(c0), "=r"(c1), "=r"(c2): "0"(c0), "1"(c1), "2"(c2), "m"(i), "m"(j)  :"%eax","%edx","cc");
+
+#define SQRADDSC(i, j)                                                         \
+__asm__(                                            \
+     "movd  %3,%%mm0     \n\t"                            \
+     "movd  %4,%%mm1     \n\t"                            \
+     "pmuludq %%mm1,%%mm0\n\t"                            \
+     "movd  %%mm0,%0     \n\t"                            \
+     "psrlq $32,%%mm0    \n\t"                            \
+     "movd  %%mm0,%1     \n\t"                            \
+     "xorl  %2,%2        \n\t"                            \
+     :"=r"(sc0), "=r"(sc1), "=r"(sc2): "m"(i), "m"(j));
+
+/* TAO removed sc0,1,2 as input to remove warning so %6,%7 become %3,%4 */
+
+#define SQRADDAC(i, j)                                                         \
+__asm__(                                            \
+     "movd  %6,%%mm0     \n\t"                            \
+     "movd  %7,%%mm1     \n\t"                            \
+     "pmuludq %%mm1,%%mm0\n\t"                            \
+     "movd  %%mm0,%%eax  \n\t"                            \
+     "psrlq $32,%%mm0    \n\t"                            \
+     "movd  %%mm0,%%edx  \n\t"                            \
+     "addl  %%eax,%0     \n\t"                            \
+     "adcl  %%edx,%1     \n\t"                            \
+     "adcl  $0,%2        \n\t"                            \
+     :"=r"(sc0), "=r"(sc1), "=r"(sc2): "0"(sc0), "1"(sc1), "2"(sc2), "m"(i), "m"(j)  :"%eax","%edx","cc");
+
+#define SQRADDDB                                          \
+__asm__(                                                     \
+     "addl %6,%0         \n\t"                            \
+     "adcl %7,%1         \n\t"                            \
+     "adcl %8,%2         \n\t"                            \
+     "addl %6,%0         \n\t"                            \
+     "adcl %7,%1         \n\t"                            \
+     "adcl %8,%2         \n\t"                            \
+     :"=r"(c0), "=r"(c1), "=r"(c2) : "0"(c0), "1"(c1), "2"(c2), "r"(sc0), "r"(sc1), "r"(sc2) : "cc");
+
+#elif defined(TFM_ARM)
+
+/* ARM code */
+
+#define COMBA_START
+
+#define CLEAR_CARRY \
+   c0 = c1 = c2 = 0;
+
+#define COMBA_STORE(x) \
+   x = c0;
+
+#define COMBA_STORE2(x) \
+   x = c1;
+
+#define CARRY_FORWARD \
+   do { c0 = c1; c1 = c2; c2 = 0; } while (0);
+
+#define COMBA_FINI
+
+/* multiplies point i and j, updates carry "c1" and digit c2 */
+#define SQRADD(i, j)                                             \
+__asm__(                                                             \
+"  UMULL  r0,r1,%6,%6              \n\t"                         \
+"  ADDS   %0,%0,r0                 \n\t"                         \
+"  ADCS   %1,%1,r1                 \n\t"                         \
+"  ADC    %2,%2,#0                 \n\t"                         \
+:"=r"(c0), "=r"(c1), "=r"(c2) : "0"(c0), "1"(c1), "2"(c2), "r"(i) : "r0", "r1", "cc");
+	
+/* for squaring some of the terms are doubled... */
+#define SQRADD2(i, j)                                            \
+__asm__(                                                             \
+"  UMULL  r0,r1,%6,%7              \n\t"                         \
+"  ADDS   %0,%0,r0                 \n\t"                         \
+"  ADCS   %1,%1,r1                 \n\t"                         \
+"  ADC    %2,%2,#0                 \n\t"                         \
+"  ADDS   %0,%0,r0                 \n\t"                         \
+"  ADCS   %1,%1,r1                 \n\t"                         \
+"  ADC    %2,%2,#0                 \n\t"                         \
+:"=r"(c0), "=r"(c1), "=r"(c2) : "0"(c0), "1"(c1), "2"(c2), "r"(i), "r"(j) : "r0", "r1", "cc");
+
+#define SQRADDSC(i, j)                                           \
+__asm__(                                                             \
+"  UMULL  %0,%1,%3,%4              \n\t"                         \
+"  SUB    %2,%2,%2                 \n\t"                         \
+:"=r"(sc0), "=r"(sc1), "=r"(sc2) : "r"(i), "r"(j) : "cc");
+
+/* TAO removed sc0,1,2 as input to remove warning so %6,%7 become %3,%4 */
+
+#define SQRADDAC(i, j)                                           \
+__asm__(                                                             \
+"  UMULL  r0,r1,%6,%7              \n\t"                         \
+"  ADDS   %0,%0,r0                 \n\t"                         \
+"  ADCS   %1,%1,r1                 \n\t"                         \
+"  ADC    %2,%2,#0                 \n\t"                         \
+:"=r"(sc0), "=r"(sc1), "=r"(sc2) : "0"(sc0), "1"(sc1), "2"(sc2), "r"(i), "r"(j) : "r0", "r1", "cc");
+
+#define SQRADDDB                                                 \
+__asm__(                                                             \
+"  ADDS  %0,%0,%3                     \n\t"                      \
+"  ADCS  %1,%1,%4                     \n\t"                      \
+"  ADC   %2,%2,%5                     \n\t"                      \
+"  ADDS  %0,%0,%3                     \n\t"                      \
+"  ADCS  %1,%1,%4                     \n\t"                      \
+"  ADC   %2,%2,%5                     \n\t"                      \
+:"=r"(c0), "=r"(c1), "=r"(c2) : "r"(sc0), "r"(sc1), "r"(sc2), "0"(c0), "1"(c1), "2"(c2) : "cc");
+
+#elif defined(TFM_PPC32)
+
+/* PPC32 */
+
+#define COMBA_START
+
+#define CLEAR_CARRY \
+   c0 = c1 = c2 = 0;
+
+#define COMBA_STORE(x) \
+   x = c0;
+
+#define COMBA_STORE2(x) \
+   x = c1;
+
+#define CARRY_FORWARD \
+   do { c0 = c1; c1 = c2; c2 = 0; } while (0);
+
+#define COMBA_FINI
+
+/* multiplies point i and j, updates carry "c1" and digit c2 */
+#define SQRADD(i, j)             \
+__asm__(                             \
+   " mullw  16,%6,%6       \n\t" \
+   " addc   %0,%0,16       \n\t" \
+   " mulhwu 16,%6,%6       \n\t" \
+   " adde   %1,%1,16       \n\t" \
+   " addze  %2,%2          \n\t" \
+:"=r"(c0), "=r"(c1), "=r"(c2):"0"(c0), "1"(c1), "2"(c2), "r"(i):"16","cc");
+
+/* for squaring some of the terms are doubled... */
+#define SQRADD2(i, j)            \
+__asm__(                             \
+   " mullw  16,%6,%7       \n\t" \
+   " mulhwu 17,%6,%7       \n\t" \
+   " addc   %0,%0,16       \n\t" \
+   " adde   %1,%1,17       \n\t" \
+   " addze  %2,%2          \n\t" \
+   " addc   %0,%0,16       \n\t" \
+   " adde   %1,%1,17       \n\t" \
+   " addze  %2,%2          \n\t" \
+:"=r"(c0), "=r"(c1), "=r"(c2):"0"(c0), "1"(c1), "2"(c2), "r"(i), "r"(j):"16", "17","cc");
+
+#define SQRADDSC(i, j)            \
+__asm__(                              \
+   " mullw  %0,%6,%7        \n\t" \
+   " mulhwu %1,%6,%7        \n\t" \
+   " xor    %2,%2,%2        \n\t" \
+:"=r"(sc0), "=r"(sc1), "=r"(sc2):"0"(sc0), "1"(sc1), "2"(sc2), "r"(i),"r"(j) : "cc");
+
+#define SQRADDAC(i, j)           \
+__asm__(                             \
+   " mullw  16,%6,%7       \n\t" \
+   " addc   %0,%0,16       \n\t" \
+   " mulhwu 16,%6,%7       \n\t" \
+   " adde   %1,%1,16       \n\t" \
+   " addze  %2,%2          \n\t" \
+:"=r"(sc0), "=r"(sc1), "=r"(sc2):"0"(sc0), "1"(sc1), "2"(sc2), "r"(i), "r"(j):"16", "cc");
+
+#define SQRADDDB                  \
+__asm__(                              \
+   " addc   %0,%0,%3        \n\t" \
+   " adde   %1,%1,%4        \n\t" \
+   " adde   %2,%2,%5        \n\t" \
+   " addc   %0,%0,%3        \n\t" \
+   " adde   %1,%1,%4        \n\t" \
+   " adde   %2,%2,%5        \n\t" \
+:"=r"(c0), "=r"(c1), "=r"(c2) : "r"(sc0), "r"(sc1), "r"(sc2), "0"(c0), "1"(c1), "2"(c2) : "cc");
+
+#elif defined(TFM_PPC64)
+/* PPC64 */
+
+#define COMBA_START
+
+#define CLEAR_CARRY \
+   c0 = c1 = c2 = 0;
+
+#define COMBA_STORE(x) \
+   x = c0;
+
+#define COMBA_STORE2(x) \
+   x = c1;
+
+#define CARRY_FORWARD \
+   do { c0 = c1; c1 = c2; c2 = 0; } while (0);
+
+#define COMBA_FINI
+
+/* multiplies point i and j, updates carry "c1" and digit c2 */
+#define SQRADD(i, j)             \
+__asm__(                             \
+   " mulld  16,%6,%6       \n\t" \
+   " addc   %0,%0,16       \n\t" \
+   " mulhdu 16,%6,%6       \n\t" \
+   " adde   %1,%1,16       \n\t" \
+   " addze  %2,%2          \n\t" \
+:"=r"(c0), "=r"(c1), "=r"(c2):"0"(c0), "1"(c1), "2"(c2), "r"(i):"16","cc");
+
+/* for squaring some of the terms are doubled... */
+#define SQRADD2(i, j)            \
+__asm__(                             \
+   " mulld  16,%6,%7       \n\t" \
+   " mulhdu 17,%6,%7       \n\t" \
+   " addc   %0,%0,16       \n\t" \
+   " adde   %1,%1,17       \n\t" \
+   " addze  %2,%2          \n\t" \
+   " addc   %0,%0,16       \n\t" \
+   " adde   %1,%1,17       \n\t" \
+   " addze  %2,%2          \n\t" \
+:"=r"(c0), "=r"(c1), "=r"(c2):"0"(c0), "1"(c1), "2"(c2), "r"(i), "r"(j):"16", "17","cc");
+
+#define SQRADDSC(i, j)            \
+__asm__(                              \
+   " mulld  %0,%6,%7        \n\t" \
+   " mulhdu %1,%6,%7        \n\t" \
+   " xor    %2,%2,%2        \n\t" \
+:"=r"(sc0), "=r"(sc1), "=r"(sc2):"0"(sc0), "1"(sc1), "2"(sc2), "r"(i),"r"(j) : "cc");
+
+#define SQRADDAC(i, j)           \
+__asm__(                             \
+   " mulld  16,%6,%7       \n\t" \
+   " addc   %0,%0,16       \n\t" \
+   " mulhdu 16,%6,%7       \n\t" \
+   " adde   %1,%1,16       \n\t" \
+   " addze  %2,%2          \n\t" \
+:"=r"(sc0), "=r"(sc1), "=r"(sc2):"0"(sc0), "1"(sc1), "2"(sc2), "r"(i), "r"(j):"16", "cc");
+
+#define SQRADDDB                  \
+__asm__(                              \
+   " addc   %0,%0,%3        \n\t" \
+   " adde   %1,%1,%4        \n\t" \
+   " adde   %2,%2,%5        \n\t" \
+   " addc   %0,%0,%3        \n\t" \
+   " adde   %1,%1,%4        \n\t" \
+   " adde   %2,%2,%5        \n\t" \
+:"=r"(c0), "=r"(c1), "=r"(c2) : "r"(sc0), "r"(sc1), "r"(sc2), "0"(c0), "1"(c1), "2"(c2) : "cc");
+
+
+#elif defined(TFM_AVR32)
+
+/* AVR32 */
+
+#define COMBA_START
+
+#define CLEAR_CARRY \
+   c0 = c1 = c2 = 0;
+
+#define COMBA_STORE(x) \
+   x = c0;
+
+#define COMBA_STORE2(x) \
+   x = c1;
+
+#define CARRY_FORWARD \
+   do { c0 = c1; c1 = c2; c2 = 0; } while (0);
+
+#define COMBA_FINI
+
+/* multiplies point i and j, updates carry "c1" and digit c2 */
+#define SQRADD(i, j)             \
+__asm__(                             \
+   " mulu.d r2,%6,%6       \n\t" \
+   " add    %0,%0,r2       \n\t" \
+   " adc    %1,%1,r3       \n\t" \
+   " acr    %2             \n\t" \
+:"=r"(c0), "=r"(c1), "=r"(c2):"0"(c0), "1"(c1), "2"(c2), "r"(i):"r2","r3");
+
+/* for squaring some of the terms are doubled... */
+#define SQRADD2(i, j)            \
+__asm__(                             \
+   " mulu.d r2,%6,%7       \n\t" \
+   " add    %0,%0,r2       \n\t" \
+   " adc    %1,%1,r3       \n\t" \
+   " acr    %2,            \n\t" \
+   " add    %0,%0,r2       \n\t" \
+   " adc    %1,%1,r3       \n\t" \
+   " acr    %2,            \n\t" \
+:"=r"(c0), "=r"(c1), "=r"(c2):"0"(c0), "1"(c1), "2"(c2), "r"(i), "r"(j):"r2", "r3");
+
+#define SQRADDSC(i, j)            \
+__asm__(                              \
+   " mulu.d r2,%6,%7        \n\t" \
+   " mov    %0,r2           \n\t" \
+   " mov    %1,r3           \n\t" \
+   " eor    %2,%2           \n\t" \
+:"=r"(sc0), "=r"(sc1), "=r"(sc2):"0"(sc0), "1"(sc1), "2"(sc2), "r"(i),"r"(j) : "r2", "r3");
+
+#define SQRADDAC(i, j)           \
+__asm__(                             \
+   " mulu.d r2,%6,%7       \n\t" \
+   " add    %0,%0,r2       \n\t" \
+   " adc    %1,%1,r3       \n\t" \
+   " acr    %2             \n\t" \
+:"=r"(sc0), "=r"(sc1), "=r"(sc2):"0"(sc0), "1"(sc1), "2"(sc2), "r"(i), "r"(j):"r2", "r3");
+
+#define SQRADDDB                  \
+__asm__(                              \
+   " add    %0,%0,%3        \n\t" \
+   " adc    %1,%1,%4        \n\t" \
+   " adc    %2,%2,%5        \n\t" \
+   " add    %0,%0,%3        \n\t" \
+   " adc    %1,%1,%4        \n\t" \
+   " adc    %2,%2,%5        \n\t" \
+:"=r"(c0), "=r"(c1), "=r"(c2) : "r"(sc0), "r"(sc1), "r"(sc2), "0"(c0), "1"(c1), "2"(c2) : "cc");
+
+
+#else
+
+#define TFM_ISO
+
+/* ISO C portable code */
+
+#define COMBA_START
+
+#define CLEAR_CARRY \
+   c0 = c1 = c2 = 0;
+
+#define COMBA_STORE(x) \
+   x = c0;
+
+#define COMBA_STORE2(x) \
+   x = c1;
+
+#define CARRY_FORWARD \
+   do { c0 = c1; c1 = c2; c2 = 0; } while (0);
+
+#define COMBA_FINI
+
+/* multiplies point i and j, updates carry "c1" and digit c2 */
+#define SQRADD(i, j)                                 \
+   do { fp_word t;                                   \
+   t = c0 + ((fp_word)i) * ((fp_word)j);  c0 = (fp_digit)t;    \
+   t = c1 + (t >> DIGIT_BIT);             c1 = (fp_digit)t;    \
+                                          c2 +=(fp_digit) (t >> DIGIT_BIT); \
+   } while (0);
+  
+
+/* for squaring some of the terms are doubled... */
+#define SQRADD2(i, j)                                                 \
+   do { fp_word t;                                                    \
+   t  = ((fp_word)i) * ((fp_word)j);                                  \
+   tt = (fp_word)c0 + t;                 c0 = (fp_digit)tt;           \
+   tt = (fp_word)c1 + (tt >> DIGIT_BIT); c1 = (fp_digit)tt;           \
+                                         c2 +=(fp_digit)( tt >> DIGIT_BIT);    \
+   tt = (fp_word)c0 + t;                 c0 = (fp_digit)tt;                    \
+   tt = (fp_word)c1 + (tt >> DIGIT_BIT); c1 = (fp_digit)tt;            \
+                                         c2 +=(fp_digit) (tt >> DIGIT_BIT);    \
+   } while (0);
+
+#define SQRADDSC(i, j)                                                         \
+   do { fp_word t;                                                             \
+      t =  ((fp_word)i) * ((fp_word)j);                                        \
+      sc0 = (fp_digit)t; sc1 = (t >> DIGIT_BIT); sc2 = 0;                      \
+   } while (0);
+
+#define SQRADDAC(i, j)                                                         \
+   do { fp_word t;                                                             \
+   t = sc0 + ((fp_word)i) * ((fp_word)j);  sc0 =  (fp_digit)t;                 \
+   t = sc1 + (t >> DIGIT_BIT);             sc1 =  (fp_digit)t;                 \
+                                           sc2 += (fp_digit)(t >> DIGIT_BIT);  \
+   } while (0);
+
+#define SQRADDDB                                                               \
+   do { fp_word t;                                                             \
+   t = ((fp_word)sc0) + ((fp_word)sc0) + c0; c0 = (fp_digit)t;                 \
+   t = ((fp_word)sc1) + ((fp_word)sc1) + c1 + (t >> DIGIT_BIT);                \
+                                             c1 = (fp_digit)t;                 \
+   c2 = c2 + (fp_digit)(((fp_word)sc2) + ((fp_word)sc2) + (t >> DIGIT_BIT));   \
+   } while (0);
+
+#endif
+
+#ifdef TFM_SMALL_SET
+    #include "fp_sqr_comba_small_set.i"
+#endif
+
+#if defined(TFM_SQR3)
+    #include "fp_sqr_comba_3.i"
+#endif
+#if defined(TFM_SQR4)
+    #include "fp_sqr_comba_4.i"
+#endif
+#if defined(TFM_SQR6)
+    #include "fp_sqr_comba_6.i"
+#endif
+#if defined(TFM_SQR7)
+    #include "fp_sqr_comba_7.i"
+#endif
+#if defined(TFM_SQR8)
+    #include "fp_sqr_comba_8.i"
+#endif
+#if defined(TFM_SQR9)
+    #include "fp_sqr_comba_9.i"
+#endif
+#if defined(TFM_SQR12)
+    #include "fp_sqr_comba_12.i"
+#endif
+#if defined(TFM_SQR17)
+    #include "fp_sqr_comba_17.i"
+#endif
+#if defined(TFM_SQR20)
+    #include "fp_sqr_comba_20.i"
+#endif
+#if defined(TFM_SQR24)
+    #include "fp_sqr_comba_24.i"
+#endif
+#if defined(TFM_SQR28)
+    #include "fp_sqr_comba_28.i"
+#endif
+#if defined(TFM_SQR32)
+    #include "fp_sqr_comba_32.i"
+#endif
+#if defined(TFM_SQR48)
+    #include "fp_sqr_comba_48.i"
+#endif
+#if defined(TFM_SQR64)
+    #include "fp_sqr_comba_64.i"
+#endif
+/* end fp_sqr_comba.c asm */
+
+/* start fp_mul_comba.c asm */
+/* these are the combas.  Worship them. */
+#if defined(TFM_X86)
+/* Generic x86 optimized code */
+
+/* anything you need at the start */
+#define COMBA_START
+
+/* clear the chaining variables */
+#define COMBA_CLEAR \
+   c0 = c1 = c2 = 0;
+
+/* forward the carry to the next digit */
+#define COMBA_FORWARD \
+   do { c0 = c1; c1 = c2; c2 = 0; } while (0);
+
+/* store the first sum */
+#define COMBA_STORE(x) \
+   x = c0;
+
+/* store the second sum [carry] */
+#define COMBA_STORE2(x) \
+   x = c1;
+
+/* anything you need at the end */
+#define COMBA_FINI
+
+/* this should multiply i and j  */
+#define MULADD(i, j)                                      \
+__asm__(                                                      \
+     "movl  %6,%%eax     \n\t"                            \
+     "mull  %7           \n\t"                            \
+     "addl  %%eax,%0     \n\t"                            \
+     "adcl  %%edx,%1     \n\t"                            \
+     "adcl  $0,%2        \n\t"                            \
+     :"=r"(c0), "=r"(c1), "=r"(c2): "0"(c0), "1"(c1), "2"(c2), "m"(i), "m"(j)  :"%eax","%edx","cc");
+
+#elif defined(TFM_X86_64)
+/* x86-64 optimized */
+
+/* anything you need at the start */
+#define COMBA_START
+
+/* clear the chaining variables */
+#define COMBA_CLEAR \
+   c0 = c1 = c2 = 0;
+
+/* forward the carry to the next digit */
+#define COMBA_FORWARD \
+   do { c0 = c1; c1 = c2; c2 = 0; } while (0);
+
+/* store the first sum */
+#define COMBA_STORE(x) \
+   x = c0;
+
+/* store the second sum [carry] */
+#define COMBA_STORE2(x) \
+   x = c1;
+
+/* anything you need at the end */
+#define COMBA_FINI
+
+/* this should multiply i and j  */
+#define MULADD(i, j)                                      \
+__asm__  (                                                    \
+     "movq  %6,%%rax     \n\t"                            \
+     "mulq  %7           \n\t"                            \
+     "addq  %%rax,%0     \n\t"                            \
+     "adcq  %%rdx,%1     \n\t"                            \
+     "adcq  $0,%2        \n\t"                            \
+     :"=r"(c0), "=r"(c1), "=r"(c2): "0"(c0), "1"(c1), "2"(c2), "g"(i), "g"(j)  :"%rax","%rdx","cc");
+
+
+#if defined(HAVE_INTEL_MULX)
+#define MULADD_MULX(b0, c0, c1, rdx)\
+    __asm__  volatile (                                   \
+         "movq   %3, %%rdx\n\t"                           \
+         "mulx  %2,%%r9, %%r8 \n\t"                       \
+         "adoxq  %%r9,%0     \n\t"                        \
+         "adcxq  %%r8,%1     \n\t"                        \
+         :"+r"(c0),"+r"(c1):"r"(b0), "r"(rdx):"%r8","%r9","%r10","%rdx"\
+    )
+
+
+#define MULADD_MULX_ADD_CARRY(c0, c1)\
+    __asm__ volatile(\
+    "mov $0, %%r10\n\t"\
+    "movq %1, %%r8\n\t"\
+    "adox %%r10, %0\n\t"\
+    "adcx %%r10, %1\n\t"\
+    :"+r"(c0),"+r"(c1)::"%r8","%r9","%r10","%rdx") ;
+
+#define MULADD_SET_A(a0)\
+    __asm__ volatile("add $0, %%r8\n\t"                   \
+             "movq  %0,%%rdx\n\t"                         \
+             ::"r"(a0):"%r8","%r9","%r10","%rdx") ;
+
+#define MULADD_BODY(a,b,c)\
+    {   word64 rdx = a->dp[ix] ;      \
+        cp = &(c->dp[iz]) ;           \
+        c0 = cp[0] ; c1 = cp[1];      \
+        MULADD_SET_A(rdx) ;           \
+        MULADD_MULX(b0, c0, c1, rdx) ;\
+        cp[0]=c0; c0=cp[2];           \
+        MULADD_MULX(b1, c1, c0, rdx) ;\
+        cp[1]=c1; c1=cp[3];           \
+        MULADD_MULX(b2, c0, c1, rdx) ;\
+        cp[2]=c0; c0=cp[4];           \
+        MULADD_MULX(b3, c1, c0, rdx) ;\
+        cp[3]=c1; c1=cp[5];           \
+        MULADD_MULX_ADD_CARRY(c0, c1);\
+        cp[4]=c0; cp[5]=c1;           \
+    }
+
+#define TFM_INTEL_MUL_COMBA(a, b, c)\
+  for(ix=0; ixdp[ix]=0 ; \
+  for(iy=0; (iyused); iy+=4) {    \
+    fp_digit *bp ;                    \
+    bp = &(b->dp[iy+0]) ;             \
+    fp_digit b0 = bp[0] , b1= bp[1],  \
+             b2= bp[2], b3= bp[3];    \
+    ix=0, iz=iy;                      \
+    while(ixused) {               \
+        fp_digit c0, c1;              \
+        fp_digit *cp ;                \
+        MULADD_BODY(a,b,c);           \
+        ix++ ; iz++ ;                 \
+    }                                 \
+};
+#endif
+
+#elif defined(TFM_SSE2)
+/* use SSE2 optimizations */
+
+/* anything you need at the start */
+#define COMBA_START
+
+/* clear the chaining variables */
+#define COMBA_CLEAR \
+   c0 = c1 = c2 = 0;
+
+/* forward the carry to the next digit */
+#define COMBA_FORWARD \
+   do { c0 = c1; c1 = c2; c2 = 0; } while (0);
+
+/* store the first sum */
+#define COMBA_STORE(x) \
+   x = c0;
+
+/* store the second sum [carry] */
+#define COMBA_STORE2(x) \
+   x = c1;
+
+/* anything you need at the end */
+#define COMBA_FINI \
+   __asm__("emms");
+
+/* this should multiply i and j  */
+#define MULADD(i, j)                                     \
+__asm__(                                                     \
+    "movd  %6,%%mm0     \n\t"                            \
+    "movd  %7,%%mm1     \n\t"                            \
+    "pmuludq %%mm1,%%mm0\n\t"                            \
+    "movd  %%mm0,%%eax  \n\t"                            \
+    "psrlq $32,%%mm0    \n\t"                            \
+    "addl  %%eax,%0     \n\t"                            \
+    "movd  %%mm0,%%eax  \n\t"                            \
+    "adcl  %%eax,%1     \n\t"                            \
+    "adcl  $0,%2        \n\t"                            \
+    :"=r"(c0), "=r"(c1), "=r"(c2): "0"(c0), "1"(c1), "2"(c2), "m"(i), "m"(j)  :"%eax","cc");
+
+#elif defined(TFM_ARM)
+/* ARM code */
+
+#define COMBA_START 
+
+#define COMBA_CLEAR \
+   c0 = c1 = c2 = 0;
+
+#define COMBA_FORWARD \
+   do { c0 = c1; c1 = c2; c2 = 0; } while (0);
+
+#define COMBA_STORE(x) \
+   x = c0;
+
+#define COMBA_STORE2(x) \
+   x = c1;
+
+#define COMBA_FINI
+
+#define MULADD(i, j)                                          \
+__asm__(                                                          \
+"  UMULL  r0,r1,%6,%7           \n\t"                         \
+"  ADDS   %0,%0,r0              \n\t"                         \
+"  ADCS   %1,%1,r1              \n\t"                         \
+"  ADC    %2,%2,#0              \n\t"                         \
+:"=r"(c0), "=r"(c1), "=r"(c2) : "0"(c0), "1"(c1), "2"(c2), "r"(i), "r"(j) : "r0", "r1", "cc");
+
+#elif defined(TFM_PPC32)
+/* For 32-bit PPC */
+
+#define COMBA_START
+
+#define COMBA_CLEAR \
+   c0 = c1 = c2 = 0;
+
+#define COMBA_FORWARD \
+   do { c0 = c1; c1 = c2; c2 = 0; } while (0);
+
+#define COMBA_STORE(x) \
+   x = c0;
+
+#define COMBA_STORE2(x) \
+   x = c1;
+
+#define COMBA_FINI 
+   
+/* untested: will mulhwu change the flags?  Docs say no */
+#define MULADD(i, j)              \
+__asm__(                              \
+   " mullw  16,%6,%7       \n\t" \
+   " addc   %0,%0,16       \n\t" \
+   " mulhwu 16,%6,%7       \n\t" \
+   " adde   %1,%1,16       \n\t" \
+   " addze  %2,%2          \n\t" \
+:"=r"(c0), "=r"(c1), "=r"(c2):"0"(c0), "1"(c1), "2"(c2), "r"(i), "r"(j):"16");
+
+#elif defined(TFM_PPC64)
+/* For 64-bit PPC */
+
+#define COMBA_START
+
+#define COMBA_CLEAR \
+   c0 = c1 = c2 = 0;
+
+#define COMBA_FORWARD \
+   do { c0 = c1; c1 = c2; c2 = 0; } while (0);
+
+#define COMBA_STORE(x) \
+   x = c0;
+
+#define COMBA_STORE2(x) \
+   x = c1;
+
+#define COMBA_FINI 
+   
+/* untested: will mulhwu change the flags?  Docs say no */
+#define MULADD(i, j)              \
+____asm__(                              \
+   " mulld  16,%6,%7       \n\t" \
+   " addc   %0,%0,16       \n\t" \
+   " mulhdu 16,%6,%7       \n\t" \
+   " adde   %1,%1,16       \n\t" \
+   " addze  %2,%2          \n\t" \
+:"=r"(c0), "=r"(c1), "=r"(c2):"0"(c0), "1"(c1), "2"(c2), "r"(i), "r"(j):"16");
+
+#elif defined(TFM_AVR32)
+
+/* ISO C code */
+
+#define COMBA_START
+
+#define COMBA_CLEAR \
+   c0 = c1 = c2 = 0;
+
+#define COMBA_FORWARD \
+   do { c0 = c1; c1 = c2; c2 = 0; } while (0);
+
+#define COMBA_STORE(x) \
+   x = c0;
+
+#define COMBA_STORE2(x) \
+   x = c1;
+
+#define COMBA_FINI 
+   
+#define MULADD(i, j)             \
+____asm__(                             \
+   " mulu.d r2,%6,%7        \n\t"\
+   " add    %0,r2           \n\t"\
+   " adc    %1,%1,r3        \n\t"\
+   " acr    %2              \n\t"\
+:"=r"(c0), "=r"(c1), "=r"(c2):"0"(c0), "1"(c1), "2"(c2), "r"(i), "r"(j):"r2","r3");
+
+#else
+/* ISO C code */
+
+#define COMBA_START
+
+#define COMBA_CLEAR \
+   c0 = c1 = c2 = 0;
+
+#define COMBA_FORWARD \
+   do { c0 = c1; c1 = c2; c2 = 0; } while (0);
+
+#define COMBA_STORE(x) \
+   x = c0;
+
+#define COMBA_STORE2(x) \
+   x = c1;
+
+#define COMBA_FINI 
+   
+#define MULADD(i, j)                                                                                                                                  \
+   do { fp_word t;                                                    \
+   t = (fp_word)c0 + ((fp_word)i) * ((fp_word)j); c0 = (fp_digit)t;   \
+   t = (fp_word)c1 + (t >> DIGIT_BIT);                                \
+   c1 = (fp_digit)t; c2 += (fp_digit)(t >> DIGIT_BIT);                \
+   } while (0);
+
+#endif
+
+
+#ifdef TFM_SMALL_SET
+    #include "fp_mul_comba_small_set.i"
+#endif
+
+#if defined(TFM_MUL3)
+    #include "fp_mul_comba_3.i"
+#endif
+#if defined(TFM_MUL4)
+    #include "fp_mul_comba_4.i"
+#endif
+#if defined(TFM_MUL6)
+    #include "fp_mul_comba_6.i"
+#endif
+#if defined(TFM_MUL7)
+    #include "fp_mul_comba_7.i"
+#endif
+#if defined(TFM_MUL8)
+    #include "fp_mul_comba_8.i"
+#endif
+#if defined(TFM_MUL9)
+    #include "fp_mul_comba_9.i"
+#endif
+#if defined(TFM_MUL12)
+    #include "fp_mul_comba_12.i"
+#endif
+#if defined(TFM_MUL17)
+    #include "fp_mul_comba_17.i"
+#endif
+#if defined(TFM_MUL20)
+    #include "fp_mul_comba_20.i"
+#endif
+#if defined(TFM_MUL24)
+    #include "fp_mul_comba_24.i"
+#endif
+#if defined(TFM_MUL28)
+    #include "fp_mul_comba_28.i"
+#endif
+#if defined(TFM_MUL32)
+    #include "fp_mul_comba_32.i"
+#endif
+#if defined(TFM_MUL48)
+    #include "fp_mul_comba_48.i"
+#endif
+#if defined(TFM_MUL64)
+    #include "fp_mul_comba_64.i"
+#endif
+
+/* end fp_mul_comba.c asm */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/asn.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/asn.c
new file mode 100644
index 0000000..e3d9ff4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/asn.c
@@ -0,0 +1,7795 @@
+/* asn.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifndef NO_ASN
+
+#ifdef HAVE_RTP_SYS
+    #include "os.h"           /* dc_rtc_api needs    */
+    #include "dc_rtc_api.h"   /* to get current time */
+#endif
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+
+#ifndef NO_RC4
+    #include 
+#endif
+
+#ifdef HAVE_NTRU
+    #include "ntru_crypto.h"
+#endif
+
+#if defined(WOLFSSL_SHA512) || defined(WOLFSSL_SHA384)
+    #include 
+#endif
+
+#ifndef NO_SHA256
+    #include 
+#endif
+
+#ifdef HAVE_ECC
+    #include 
+#endif
+
+#ifdef WOLFSSL_DEBUG_ENCODING
+    #ifdef FREESCALE_MQX
+        #include 
+    #else
+        #include 
+    #endif
+#endif
+
+#ifdef _MSC_VER
+    /* 4996 warning to use MS extensions e.g., strcpy_s instead of XSTRNCPY */
+    #pragma warning(disable: 4996)
+#endif
+
+
+#ifndef TRUE
+    #define TRUE  1
+#endif
+#ifndef FALSE
+    #define FALSE 0
+#endif
+
+
+#ifdef HAVE_RTP_SYS
+    /* uses parital  structures */
+    #define XTIME(tl)  (0)
+    #define XGMTIME(c, t) my_gmtime((c))
+    #define XVALIDATE_DATE(d, f, t) ValidateDate((d), (f), (t))
+#elif defined(MICRIUM)
+    #if (NET_SECURE_MGR_CFG_EN == DEF_ENABLED)
+        #define XVALIDATE_DATE(d,f,t) NetSecure_ValidateDateHandler((d),(f),(t))
+    #else
+        #define XVALIDATE_DATE(d, f, t) (0)
+    #endif
+    #define NO_TIME_H
+    /* since Micrium not defining XTIME or XGMTIME, CERT_GEN not available */
+#elif defined(MICROCHIP_TCPIP_V5) || defined(MICROCHIP_TCPIP)
+    #include 
+    #define XTIME(t1) pic32_time((t1))
+    #define XGMTIME(c, t) gmtime((c))
+    #define XVALIDATE_DATE(d, f, t) ValidateDate((d), (f), (t))
+#elif defined(FREESCALE_MQX)
+    #define XTIME(t1)  mqx_time((t1))
+    #define XGMTIME(c, t) mqx_gmtime((c), (t))
+    #define XVALIDATE_DATE(d, f, t) ValidateDate((d), (f), (t))
+#elif defined(WOLFSSL_MDK_ARM)
+    #if defined(WOLFSSL_MDK5)
+        #include "cmsis_os.h"
+    #else
+        #include 
+    #endif
+    #undef RNG
+    #include "wolfssl_MDK_ARM.h"
+    #undef RNG
+    #define RNG wolfSSL_RNG /*for avoiding name conflict in "stm32f2xx.h" */
+    #define XTIME(tl)  (0)
+    #define XGMTIME(c, t) wolfssl_MDK_gmtime((c))
+    #define XVALIDATE_DATE(d, f, t)  ValidateDate((d), (f), (t))
+#elif defined(USER_TIME)
+    /* user time, and gmtime compatible functions, there is a gmtime 
+       implementation here that WINCE uses, so really just need some ticks
+       since the EPOCH 
+    */
+
+    struct tm {
+    int tm_sec;     /* seconds after the minute [0-60] */
+    int tm_min;     /* minutes after the hour [0-59] */
+    int tm_hour;    /* hours since midnight [0-23] */
+    int tm_mday;    /* day of the month [1-31] */
+    int tm_mon;     /* months since January [0-11] */
+    int tm_year;    /* years since 1900 */
+    int tm_wday;    /* days since Sunday [0-6] */
+    int tm_yday;    /* days since January 1 [0-365] */
+    int tm_isdst;   /* Daylight Savings Time flag */
+    long    tm_gmtoff;  /* offset from CUT in seconds */
+    char    *tm_zone;   /* timezone abbreviation */
+    };
+    typedef long time_t;
+
+    /* forward declaration */
+    struct tm* gmtime(const time_t* timer);
+    extern time_t XTIME(time_t * timer);
+
+    #define XGMTIME(c, t) gmtime((c))
+    #define XVALIDATE_DATE(d, f, t) ValidateDate((d), (f), (t))
+
+    #ifdef STACK_TRAP
+        /* for stack trap tracking, don't call os gmtime on OS X/linux,
+           uses a lot of stack spce */
+        extern time_t time(time_t * timer);
+        #define XTIME(tl)  time((tl))
+    #endif /* STACK_TRAP */
+
+#elif defined(TIME_OVERRIDES)
+    /* user would like to override time() and gmtime() functionality */
+
+    #ifndef HAVE_TIME_T_TYPE
+        typedef long time_t;
+    #endif
+    extern time_t XTIME(time_t * timer);
+
+    #ifndef HAVE_TM_TYPE
+        struct tm {
+            int  tm_sec;     /* seconds after the minute [0-60] */
+            int  tm_min;     /* minutes after the hour [0-59] */
+            int  tm_hour;    /* hours since midnight [0-23] */
+            int  tm_mday;    /* day of the month [1-31] */
+            int  tm_mon;     /* months since January [0-11] */
+            int  tm_year;    /* years since 1900 */
+            int  tm_wday;    /* days since Sunday [0-6] */
+            int  tm_yday;    /* days since January 1 [0-365] */
+            int  tm_isdst;   /* Daylight Savings Time flag */
+            long tm_gmtoff;  /* offset from CUT in seconds */
+            char *tm_zone;   /* timezone abbreviation */
+        };
+    #endif
+    extern struct tm* XGMTIME(const time_t* timer, struct tm* tmp);
+
+    #ifndef HAVE_VALIDATE_DATE
+        #define XVALIDATE_DATE(d, f, t) ValidateDate((d), (f), (t))
+    #endif
+#else
+    /* default */
+    /* uses complete  facility */
+    #include 
+    #define XTIME(tl)     time((tl))
+    #define XGMTIME(c, t) gmtime((c))
+    #define XVALIDATE_DATE(d, f, t) ValidateDate((d), (f), (t))
+#endif
+
+
+#ifdef _WIN32_WCE
+/* no time() or gmtime() even though in time.h header?? */
+
+#include 
+
+
+time_t time(time_t* timer)
+{
+    SYSTEMTIME     sysTime;
+    FILETIME       fTime;
+    ULARGE_INTEGER intTime;
+    time_t         localTime;
+
+    if (timer == NULL)
+        timer = &localTime;
+
+    GetSystemTime(&sysTime);
+    SystemTimeToFileTime(&sysTime, &fTime);
+
+    XMEMCPY(&intTime, &fTime, sizeof(FILETIME));
+    /* subtract EPOCH */
+    intTime.QuadPart -= 0x19db1ded53e8000;
+    /* to secs */
+    intTime.QuadPart /= 10000000;
+    *timer = (time_t)intTime.QuadPart;
+
+    return *timer;
+}
+
+#endif /*  _WIN32_WCE */
+#if defined( _WIN32_WCE ) || defined( USER_TIME )
+
+struct tm* gmtime(const time_t* timer)
+{
+    #define YEAR0          1900
+    #define EPOCH_YEAR     1970
+    #define SECS_DAY       (24L * 60L * 60L)
+    #define LEAPYEAR(year) (!((year) % 4) && (((year) % 100) || !((year) %400)))
+    #define YEARSIZE(year) (LEAPYEAR(year) ? 366 : 365)
+
+    static const int _ytab[2][12] =
+    {
+        {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31},
+        {31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}
+    };
+
+    static struct tm st_time;
+    struct tm* ret = &st_time;
+    time_t secs = *timer;
+    unsigned long dayclock, dayno;
+    int year = EPOCH_YEAR;
+
+    dayclock = (unsigned long)secs % SECS_DAY;
+    dayno    = (unsigned long)secs / SECS_DAY;
+
+    ret->tm_sec  = (int) dayclock % 60;
+    ret->tm_min  = (int)(dayclock % 3600) / 60;
+    ret->tm_hour = (int) dayclock / 3600;
+    ret->tm_wday = (int) (dayno + 4) % 7;        /* day 0 a Thursday */
+
+    while(dayno >= (unsigned long)YEARSIZE(year)) {
+        dayno -= YEARSIZE(year);
+        year++;
+    }
+
+    ret->tm_year = year - YEAR0;
+    ret->tm_yday = (int)dayno;
+    ret->tm_mon  = 0;
+
+    while(dayno >= (unsigned long)_ytab[LEAPYEAR(year)][ret->tm_mon]) {
+        dayno -= _ytab[LEAPYEAR(year)][ret->tm_mon];
+        ret->tm_mon++;
+    }
+
+    ret->tm_mday  = (int)++dayno;
+    ret->tm_isdst = 0;
+
+    return ret;
+}
+
+#endif /* _WIN32_WCE  || USER_TIME */
+
+
+#ifdef HAVE_RTP_SYS
+
+#define YEAR0          1900
+
+struct tm* my_gmtime(const time_t* timer)       /* has a gmtime() but hangs */
+{
+    static struct tm st_time;
+    struct tm* ret = &st_time;
+
+    DC_RTC_CALENDAR cal;
+    dc_rtc_time_get(&cal, TRUE);
+
+    ret->tm_year  = cal.year - YEAR0;       /* gm starts at 1900 */
+    ret->tm_mon   = cal.month - 1;          /* gm starts at 0 */
+    ret->tm_mday  = cal.day;
+    ret->tm_hour  = cal.hour;
+    ret->tm_min   = cal.minute;
+    ret->tm_sec   = cal.second;
+
+    return ret;
+}
+
+#endif /* HAVE_RTP_SYS */
+
+
+#if defined(MICROCHIP_TCPIP_V5) || defined(MICROCHIP_TCPIP)
+
+/*
+ * time() is just a stub in Microchip libraries. We need our own
+ * implementation. Use SNTP client to get seconds since epoch.
+ */
+time_t pic32_time(time_t* timer)
+{
+#ifdef MICROCHIP_TCPIP_V5
+    DWORD sec = 0;
+#else
+    uint32_t sec = 0;
+#endif
+    time_t localTime;
+
+    if (timer == NULL)
+        timer = &localTime;
+
+#ifdef MICROCHIP_MPLAB_HARMONY
+    sec = TCPIP_SNTP_UTCSecondsGet();
+#else
+    sec = SNTPGetUTCSeconds();
+#endif
+    *timer = (time_t) sec;
+
+    return *timer;
+}
+
+#endif /* MICROCHIP_TCPIP */
+
+
+#ifdef FREESCALE_MQX
+
+time_t mqx_time(time_t* timer)
+{
+    time_t localTime;
+    TIME_STRUCT time_s;
+
+    if (timer == NULL)
+        timer = &localTime;
+
+    _time_get(&time_s);
+    *timer = (time_t) time_s.SECONDS;
+
+    return *timer;
+}
+
+/* CodeWarrior GCC toolchain only has gmtime_r(), no gmtime() */
+struct tm* mqx_gmtime(const time_t* clock, struct tm* tmpTime)
+{
+    return gmtime_r(clock, tmpTime);
+}
+
+#endif /* FREESCALE_MQX */
+
+#ifdef WOLFSSL_TIRTOS
+
+time_t XTIME(time_t * timer)
+{
+    time_t sec = 0;
+
+    sec = (time_t) Seconds_get();
+
+    if (timer != NULL)
+        *timer = sec;
+
+    return sec;
+}
+
+#endif /* WOLFSSL_TIRTOS */
+
+static INLINE word32 btoi(byte b)
+{
+    return b - 0x30;
+}
+
+
+/* two byte date/time, add to value */
+static INLINE void GetTime(int* value, const byte* date, int* idx)
+{
+    int i = *idx;
+
+    *value += btoi(date[i++]) * 10;
+    *value += btoi(date[i++]);
+
+    *idx = i;
+}
+
+
+#if defined(MICRIUM)
+
+CPU_INT32S NetSecure_ValidateDateHandler(CPU_INT08U *date, CPU_INT08U format,
+                                         CPU_INT08U dateType)
+{
+    CPU_BOOLEAN  rtn_code;
+    CPU_INT32S   i;
+    CPU_INT32S   val;    
+    CPU_INT16U   year;
+    CPU_INT08U   month;
+    CPU_INT16U   day;
+    CPU_INT08U   hour;
+    CPU_INT08U   min;
+    CPU_INT08U   sec;
+
+    i    = 0;
+    year = 0u;
+
+    if (format == ASN_UTC_TIME) {
+        if (btoi(date[0]) >= 5)
+            year = 1900;
+        else
+            year = 2000;
+    }
+    else  { /* format == GENERALIZED_TIME */
+        year += btoi(date[i++]) * 1000;
+        year += btoi(date[i++]) * 100;
+    }    
+
+    val = year;
+    GetTime(&val, date, &i);
+    year = (CPU_INT16U)val;
+
+    val = 0;
+    GetTime(&val, date, &i);   
+    month = (CPU_INT08U)val;   
+
+    val = 0;
+    GetTime(&val, date, &i);  
+    day = (CPU_INT16U)val;
+
+    val = 0;
+    GetTime(&val, date, &i);  
+    hour = (CPU_INT08U)val;
+
+    val = 0;
+    GetTime(&val, date, &i);  
+    min = (CPU_INT08U)val;
+
+    val = 0;
+    GetTime(&val, date, &i);  
+    sec = (CPU_INT08U)val;
+
+    return NetSecure_ValidateDate(year, month, day, hour, min, sec, dateType); 
+}
+
+#endif /* MICRIUM */
+
+
+WOLFSSL_LOCAL int GetLength(const byte* input, word32* inOutIdx, int* len,
+                           word32 maxIdx)
+{
+    int     length = 0;
+    word32  i = *inOutIdx;
+    byte    b;
+
+    *len = 0;    /* default length */
+
+    if ( (i+1) > maxIdx) {   /* for first read */
+        WOLFSSL_MSG("GetLength bad index on input");
+        return BUFFER_E;
+    }
+
+    b = input[i++];
+    if (b >= ASN_LONG_LENGTH) {        
+        word32 bytes = b & 0x7F;
+
+        if ( (i+bytes) > maxIdx) {   /* for reading bytes */
+            WOLFSSL_MSG("GetLength bad long length");
+            return BUFFER_E;
+        }
+
+        while (bytes--) {
+            b = input[i++];
+            length = (length << 8) | b;
+        }
+    }
+    else
+        length = b;
+    
+    if ( (i+length) > maxIdx) {   /* for user of length */
+        WOLFSSL_MSG("GetLength value exceeds buffer length");
+        return BUFFER_E;
+    }
+
+    *inOutIdx = i;
+    if (length > 0)
+        *len = length;
+
+    return length;
+}
+
+
+WOLFSSL_LOCAL int GetSequence(const byte* input, word32* inOutIdx, int* len,
+                           word32 maxIdx)
+{
+    int    length = -1;
+    word32 idx    = *inOutIdx;
+
+    if (input[idx++] != (ASN_SEQUENCE | ASN_CONSTRUCTED) ||
+            GetLength(input, &idx, &length, maxIdx) < 0)
+        return ASN_PARSE_E;
+
+    *len      = length;
+    *inOutIdx = idx;
+
+    return length;
+}
+
+
+WOLFSSL_LOCAL int GetSet(const byte* input, word32* inOutIdx, int* len,
+                        word32 maxIdx)
+{
+    int    length = -1;
+    word32 idx    = *inOutIdx;
+
+    if (input[idx++] != (ASN_SET | ASN_CONSTRUCTED) ||
+            GetLength(input, &idx, &length, maxIdx) < 0)
+        return ASN_PARSE_E;
+
+    *len      = length;
+    *inOutIdx = idx;
+
+    return length;
+}
+
+
+/* winodws header clash for WinCE using GetVersion */
+WOLFSSL_LOCAL int GetMyVersion(const byte* input, word32* inOutIdx, int* version)
+{
+    word32 idx = *inOutIdx;
+
+    WOLFSSL_ENTER("GetMyVersion");
+
+    if (input[idx++] != ASN_INTEGER)
+        return ASN_PARSE_E;
+
+    if (input[idx++] != 0x01)
+        return ASN_VERSION_E;
+
+    *version  = input[idx++];
+    *inOutIdx = idx;
+
+    return *version;
+}
+
+
+#ifndef NO_PWDBASED
+/* Get small count integer, 32 bits or less */
+static int GetShortInt(const byte* input, word32* inOutIdx, int* number)
+{
+    word32 idx = *inOutIdx;
+    word32 len;
+
+    *number = 0;
+
+    if (input[idx++] != ASN_INTEGER)
+        return ASN_PARSE_E;
+
+    len = input[idx++];
+    if (len > 4)
+        return ASN_PARSE_E;
+
+    while (len--) {
+        *number  = *number << 8 | input[idx++];
+    }
+
+    *inOutIdx = idx;
+
+    return *number;
+}
+#endif /* !NO_PWDBASED */
+
+
+/* May not have one, not an error */
+static int GetExplicitVersion(const byte* input, word32* inOutIdx, int* version)
+{
+    word32 idx = *inOutIdx;
+
+    WOLFSSL_ENTER("GetExplicitVersion");
+    if (input[idx++] == (ASN_CONTEXT_SPECIFIC | ASN_CONSTRUCTED)) {
+        *inOutIdx = ++idx;  /* eat header */
+        return GetMyVersion(input, inOutIdx, version);
+    }
+
+    /* go back as is */
+    *version = 0;
+
+    return 0;
+}
+
+
+WOLFSSL_LOCAL int GetInt(mp_int* mpi, const byte* input, word32* inOutIdx,
+                  word32 maxIdx)
+{
+    word32 i = *inOutIdx;
+    byte   b = input[i++];
+    int    length;
+
+    if (b != ASN_INTEGER)
+        return ASN_PARSE_E;
+
+    if (GetLength(input, &i, &length, maxIdx) < 0)
+        return ASN_PARSE_E;
+
+    if ( (b = input[i++]) == 0x00)
+        length--;
+    else
+        i--;
+
+    if (mp_init(mpi) != MP_OKAY)
+        return MP_INIT_E;
+
+    if (mp_read_unsigned_bin(mpi, (byte*)input + i, length) != 0) {
+        mp_clear(mpi);
+        return ASN_GETINT_E;
+    }
+
+    *inOutIdx = i + length;
+    return 0;
+}
+
+
+static int GetObjectId(const byte* input, word32* inOutIdx, word32* oid,
+                     word32 maxIdx)
+{
+    int    length;
+    word32 i = *inOutIdx;
+    byte   b;
+    *oid = 0;
+    
+    b = input[i++];
+    if (b != ASN_OBJECT_ID) 
+        return ASN_OBJECT_ID_E;
+    
+    if (GetLength(input, &i, &length, maxIdx) < 0)
+        return ASN_PARSE_E;
+    
+    while(length--)
+        *oid += input[i++];
+    /* just sum it up for now */
+    
+    *inOutIdx = i;
+    
+    return 0;
+}
+
+
+WOLFSSL_LOCAL int GetAlgoId(const byte* input, word32* inOutIdx, word32* oid,
+                     word32 maxIdx)
+{
+    int    length;
+    word32 i = *inOutIdx;
+    byte   b;
+    *oid = 0;
+   
+    WOLFSSL_ENTER("GetAlgoId");
+
+    if (GetSequence(input, &i, &length, maxIdx) < 0)
+        return ASN_PARSE_E;
+    
+    b = input[i++];
+    if (b != ASN_OBJECT_ID) 
+        return ASN_OBJECT_ID_E;
+    
+    if (GetLength(input, &i, &length, maxIdx) < 0)
+        return ASN_PARSE_E;
+    
+    while(length--) {
+        /* odd HC08 compiler behavior here when input[i++] */
+        *oid += input[i];
+        i++;
+    }
+    /* just sum it up for now */
+    
+    /* could have NULL tag and 0 terminator, but may not */
+    b = input[i++];
+    
+    if (b == ASN_TAG_NULL) {
+        b = input[i++];
+        if (b != 0)
+            return ASN_EXPECT_0_E;
+    }
+    else
+    /* go back, didn't have it */
+        i--;
+    
+    *inOutIdx = i;
+    
+    return 0;
+}
+
+#ifndef NO_RSA
+
+
+#ifdef HAVE_CAVIUM
+
+static int GetCaviumInt(byte** buff, word16* buffSz, const byte* input,
+                        word32* inOutIdx, word32 maxIdx, void* heap)
+{
+    word32 i = *inOutIdx;
+    byte   b = input[i++];
+    int    length;
+
+    if (b != ASN_INTEGER)
+        return ASN_PARSE_E;
+
+    if (GetLength(input, &i, &length, maxIdx) < 0)
+        return ASN_PARSE_E;
+
+    if ( (b = input[i++]) == 0x00)
+        length--;
+    else
+        i--;
+
+    *buffSz = (word16)length;
+    *buff   = XMALLOC(*buffSz, heap, DYNAMIC_TYPE_CAVIUM_RSA);
+    if (*buff == NULL)
+        return MEMORY_E;
+
+    XMEMCPY(*buff, input + i, *buffSz);
+
+    *inOutIdx = i + length;
+    return 0;
+}
+
+static int CaviumRsaPrivateKeyDecode(const byte* input, word32* inOutIdx,
+                                     RsaKey* key, word32 inSz)
+{
+    int   version, length;
+    void* h = key->heap;
+
+    if (GetSequence(input, inOutIdx, &length, inSz) < 0)
+        return ASN_PARSE_E;
+
+    if (GetMyVersion(input, inOutIdx, &version) < 0)
+        return ASN_PARSE_E;
+
+    key->type = RSA_PRIVATE;
+
+    if (GetCaviumInt(&key->c_n,  &key->c_nSz,   input, inOutIdx, inSz, h) < 0 ||
+        GetCaviumInt(&key->c_e,  &key->c_eSz,   input, inOutIdx, inSz, h) < 0 ||
+        GetCaviumInt(&key->c_d,  &key->c_dSz,   input, inOutIdx, inSz, h) < 0 ||
+        GetCaviumInt(&key->c_p,  &key->c_pSz,   input, inOutIdx, inSz, h) < 0 ||
+        GetCaviumInt(&key->c_q,  &key->c_qSz,   input, inOutIdx, inSz, h) < 0 ||
+        GetCaviumInt(&key->c_dP, &key->c_dP_Sz, input, inOutIdx, inSz, h) < 0 ||
+        GetCaviumInt(&key->c_dQ, &key->c_dQ_Sz, input, inOutIdx, inSz, h) < 0 ||
+        GetCaviumInt(&key->c_u,  &key->c_uSz,   input, inOutIdx, inSz, h) < 0 )
+            return ASN_RSA_KEY_E;
+
+    return 0;
+}
+
+
+#endif /* HAVE_CAVIUM */
+
+int wc_RsaPrivateKeyDecode(const byte* input, word32* inOutIdx, RsaKey* key,
+                        word32 inSz)
+{
+    int    version, length;
+
+#ifdef HAVE_CAVIUM
+    if (key->magic == WOLFSSL_RSA_CAVIUM_MAGIC)
+        return CaviumRsaPrivateKeyDecode(input, inOutIdx, key, inSz);
+#endif
+
+    if (GetSequence(input, inOutIdx, &length, inSz) < 0)
+        return ASN_PARSE_E;
+
+    if (GetMyVersion(input, inOutIdx, &version) < 0)
+        return ASN_PARSE_E;
+
+    key->type = RSA_PRIVATE;
+
+    if (GetInt(&key->n,  input, inOutIdx, inSz) < 0 ||
+        GetInt(&key->e,  input, inOutIdx, inSz) < 0 ||
+        GetInt(&key->d,  input, inOutIdx, inSz) < 0 ||
+        GetInt(&key->p,  input, inOutIdx, inSz) < 0 ||
+        GetInt(&key->q,  input, inOutIdx, inSz) < 0 ||
+        GetInt(&key->dP, input, inOutIdx, inSz) < 0 ||
+        GetInt(&key->dQ, input, inOutIdx, inSz) < 0 ||
+        GetInt(&key->u,  input, inOutIdx, inSz) < 0 )  return ASN_RSA_KEY_E;
+
+    return 0;
+}
+
+#endif /* NO_RSA */
+
+/* Remove PKCS8 header, move beginning of traditional to beginning of input */
+int ToTraditional(byte* input, word32 sz)
+{
+    word32 inOutIdx = 0, oid;
+    int    version, length;
+
+    if (GetSequence(input, &inOutIdx, &length, sz) < 0)
+        return ASN_PARSE_E;
+
+    if (GetMyVersion(input, &inOutIdx, &version) < 0)
+        return ASN_PARSE_E;
+
+    if (GetAlgoId(input, &inOutIdx, &oid, sz) < 0)
+        return ASN_PARSE_E;
+
+    if (input[inOutIdx] == ASN_OBJECT_ID) {
+        /* pkcs8 ecc uses slightly different format */
+        inOutIdx++;  /* past id */
+        if (GetLength(input, &inOutIdx, &length, sz) < 0)
+            return ASN_PARSE_E;
+        inOutIdx += length;  /* over sub id, key input will verify */
+    }
+
+    if (input[inOutIdx++] != ASN_OCTET_STRING)
+        return ASN_PARSE_E;
+
+    if (GetLength(input, &inOutIdx, &length, sz) < 0)
+        return ASN_PARSE_E;
+
+    XMEMMOVE(input, input + inOutIdx, length);
+
+    return length;
+}
+
+
+#ifndef NO_PWDBASED
+
+/* Check To see if PKCS version algo is supported, set id if it is return 0
+   < 0 on error */
+static int CheckAlgo(int first, int second, int* id, int* version)
+{
+    *id      = ALGO_ID_E;
+    *version = PKCS5;   /* default */
+
+    if (first == 1) {
+        switch (second) {
+        case 1:
+            *id = PBE_SHA1_RC4_128;
+            *version = PKCS12;
+            return 0;
+        case 3:
+            *id = PBE_SHA1_DES3;
+            *version = PKCS12;
+            return 0;
+        default:
+            return ALGO_ID_E;
+        }
+    }
+
+    if (first != PKCS5)
+        return ASN_INPUT_E;  /* VERSION ERROR */
+
+    if (second == PBES2) {
+        *version = PKCS5v2;
+        return 0;
+    }
+
+    switch (second) {
+    case 3:                   /* see RFC 2898 for ids */
+        *id = PBE_MD5_DES;
+        return 0;
+    case 10:
+        *id = PBE_SHA1_DES;
+        return 0;
+    default:
+        return ALGO_ID_E;
+
+    }
+}
+
+
+/* Check To see if PKCS v2 algo is supported, set id if it is return 0
+   < 0 on error */
+static int CheckAlgoV2(int oid, int* id)
+{
+    switch (oid) {
+    case 69:
+        *id = PBE_SHA1_DES;
+        return 0;
+    case 652:
+        *id = PBE_SHA1_DES3;
+        return 0;
+    default:
+        return ALGO_ID_E;
+
+    }
+}
+
+
+/* Decrypt intput in place from parameters based on id */
+static int DecryptKey(const char* password, int passwordSz, byte* salt,
+                      int saltSz, int iterations, int id, byte* input,
+                      int length, int version, byte* cbcIv)
+{
+    int typeH;
+    int derivedLen;
+    int decryptionType;
+    int ret = 0;
+#ifdef WOLFSSL_SMALL_STACK
+    byte* key;
+#else
+    byte key[MAX_KEY_SIZE];
+#endif
+
+    switch (id) {
+        case PBE_MD5_DES:
+            typeH = MD5;
+            derivedLen = 16;           /* may need iv for v1.5 */
+            decryptionType = DES_TYPE;
+            break;
+
+        case PBE_SHA1_DES:
+            typeH = SHA;
+            derivedLen = 16;           /* may need iv for v1.5 */
+            decryptionType = DES_TYPE;
+            break;
+
+        case PBE_SHA1_DES3:
+            typeH = SHA;
+            derivedLen = 32;           /* may need iv for v1.5 */
+            decryptionType = DES3_TYPE;
+            break;
+
+        case PBE_SHA1_RC4_128:
+            typeH = SHA;
+            derivedLen = 16;
+            decryptionType = RC4_TYPE;
+            break;
+
+        default:
+            return ALGO_ID_E;
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    key = (byte*)XMALLOC(MAX_KEY_SIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (key == NULL)
+        return MEMORY_E;
+#endif
+
+    if (version == PKCS5v2)
+        ret = wc_PBKDF2(key, (byte*)password, passwordSz, salt, saltSz, iterations,
+               derivedLen, typeH);
+#ifndef NO_SHA
+    else if (version == PKCS5)
+        ret = wc_PBKDF1(key, (byte*)password, passwordSz, salt, saltSz, iterations,
+               derivedLen, typeH);
+#endif
+    else if (version == PKCS12) {
+        int  i, idx = 0;
+        byte unicodePasswd[MAX_UNICODE_SZ];
+
+        if ( (passwordSz * 2 + 2) > (int)sizeof(unicodePasswd)) {
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(key, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return UNICODE_SIZE_E; 
+        }
+
+        for (i = 0; i < passwordSz; i++) {
+            unicodePasswd[idx++] = 0x00;
+            unicodePasswd[idx++] = (byte)password[i];
+        }
+        /* add trailing NULL */
+        unicodePasswd[idx++] = 0x00;
+        unicodePasswd[idx++] = 0x00;
+
+        ret =  wc_PKCS12_PBKDF(key, unicodePasswd, idx, salt, saltSz,
+                            iterations, derivedLen, typeH, 1);
+        if (decryptionType != RC4_TYPE)
+            ret += wc_PKCS12_PBKDF(cbcIv, unicodePasswd, idx, salt, saltSz,
+                                iterations, 8, typeH, 2);
+    }
+    else {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(key, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return ALGO_ID_E;
+    }
+
+    if (ret != 0) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(key, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return ret;
+    }
+
+    switch (decryptionType) {
+#ifndef NO_DES3
+        case DES_TYPE:
+        {
+            Des    dec;
+            byte*  desIv = key + 8;
+
+            if (version == PKCS5v2 || version == PKCS12)
+                desIv = cbcIv;
+
+            ret = wc_Des_SetKey(&dec, key, desIv, DES_DECRYPTION);
+            if (ret != 0) {
+#ifdef WOLFSSL_SMALL_STACK
+                XFREE(key, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+                return ret;
+            }
+
+            wc_Des_CbcDecrypt(&dec, input, input, length);
+            break;
+        }
+
+        case DES3_TYPE:
+        {
+            Des3   dec;
+            byte*  desIv = key + 24;
+
+            if (version == PKCS5v2 || version == PKCS12)
+                desIv = cbcIv;
+            ret = wc_Des3_SetKey(&dec, key, desIv, DES_DECRYPTION);
+            if (ret != 0) {
+#ifdef WOLFSSL_SMALL_STACK
+                XFREE(key, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+                return ret;
+            }
+            ret = wc_Des3_CbcDecrypt(&dec, input, input, length);
+            if (ret != 0) {
+#ifdef WOLFSSL_SMALL_STACK
+                XFREE(key, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+                return ret;
+            }
+            break;
+        }
+#endif
+#ifndef NO_RC4
+        case RC4_TYPE:
+        {
+            Arc4    dec;
+
+            wc_Arc4SetKey(&dec, key, derivedLen);
+            wc_Arc4Process(&dec, input, input, length);
+            break;
+        }
+#endif
+
+        default:
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(key, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return ALGO_ID_E; 
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(key, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return 0;
+}
+
+
+/* Remove Encrypted PKCS8 header, move beginning of traditional to beginning
+   of input */
+int ToTraditionalEnc(byte* input, word32 sz,const char* password,int passwordSz)
+{
+    word32 inOutIdx = 0, oid;
+    int    first, second, length, version, saltSz, id;
+    int    iterations = 0;
+#ifdef WOLFSSL_SMALL_STACK
+    byte*  salt = NULL;
+    byte*  cbcIv = NULL;
+#else
+    byte   salt[MAX_SALT_SIZE];
+    byte   cbcIv[MAX_IV_SIZE];
+#endif
+    
+    if (GetSequence(input, &inOutIdx, &length, sz) < 0)
+        return ASN_PARSE_E;
+
+    if (GetAlgoId(input, &inOutIdx, &oid, sz) < 0)
+        return ASN_PARSE_E;
+    
+    first  = input[inOutIdx - 2];   /* PKCS version alwyas 2nd to last byte */
+    second = input[inOutIdx - 1];   /* version.algo, algo id last byte */
+
+    if (CheckAlgo(first, second, &id, &version) < 0)
+        return ASN_INPUT_E;  /* Algo ID error */
+
+    if (version == PKCS5v2) {
+
+        if (GetSequence(input, &inOutIdx, &length, sz) < 0)
+            return ASN_PARSE_E;
+
+        if (GetAlgoId(input, &inOutIdx, &oid, sz) < 0)
+            return ASN_PARSE_E;
+
+        if (oid != PBKDF2_OID)
+            return ASN_PARSE_E;
+    }
+
+    if (GetSequence(input, &inOutIdx, &length, sz) < 0)
+        return ASN_PARSE_E;
+
+    if (input[inOutIdx++] != ASN_OCTET_STRING)
+        return ASN_PARSE_E;
+    
+    if (GetLength(input, &inOutIdx, &saltSz, sz) < 0)
+        return ASN_PARSE_E;
+
+    if (saltSz > MAX_SALT_SIZE)
+        return ASN_PARSE_E;
+     
+#ifdef WOLFSSL_SMALL_STACK
+    salt = (byte*)XMALLOC(MAX_SALT_SIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (salt == NULL)
+        return MEMORY_E;
+#endif
+
+    XMEMCPY(salt, &input[inOutIdx], saltSz);
+    inOutIdx += saltSz;
+
+    if (GetShortInt(input, &inOutIdx, &iterations) < 0) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(salt,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return ASN_PARSE_E;
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    cbcIv = (byte*)XMALLOC(MAX_IV_SIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (cbcIv == NULL) {
+        XFREE(salt,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        return MEMORY_E;
+    }
+#endif
+
+    if (version == PKCS5v2) {
+        /* get encryption algo */
+        if (GetAlgoId(input, &inOutIdx, &oid, sz) < 0) {
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(salt,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            XFREE(cbcIv, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return ASN_PARSE_E;
+        }
+
+        if (CheckAlgoV2(oid, &id) < 0) {
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(salt,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            XFREE(cbcIv, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return ASN_PARSE_E;  /* PKCS v2 algo id error */
+        }
+
+        if (input[inOutIdx++] != ASN_OCTET_STRING) {
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(salt,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            XFREE(cbcIv, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return ASN_PARSE_E;
+        }
+    
+        if (GetLength(input, &inOutIdx, &length, sz) < 0) {
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(salt,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            XFREE(cbcIv, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return ASN_PARSE_E;
+        }
+
+        XMEMCPY(cbcIv, &input[inOutIdx], length);
+        inOutIdx += length;
+    }
+
+    if (input[inOutIdx++] != ASN_OCTET_STRING) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(salt,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(cbcIv, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return ASN_PARSE_E;
+    }
+
+    if (GetLength(input, &inOutIdx, &length, sz) < 0) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(salt,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(cbcIv, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return ASN_PARSE_E;
+    }
+
+    if (DecryptKey(password, passwordSz, salt, saltSz, iterations, id,
+                   input + inOutIdx, length, version, cbcIv) < 0) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(salt,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(cbcIv, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return ASN_INPUT_E;  /* decrypt failure */
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(salt,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(cbcIv, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    XMEMMOVE(input, input + inOutIdx, length);
+    return ToTraditional(input, length);
+}
+
+#endif /* NO_PWDBASED */
+
+#ifndef NO_RSA
+
+int wc_RsaPublicKeyDecode(const byte* input, word32* inOutIdx, RsaKey* key,
+                       word32 inSz)
+{
+    int    length;
+
+    if (GetSequence(input, inOutIdx, &length, inSz) < 0)
+        return ASN_PARSE_E;
+
+    key->type = RSA_PUBLIC;
+
+#if defined(OPENSSL_EXTRA) || defined(RSA_DECODE_EXTRA)
+    {
+    byte b = input[*inOutIdx];
+    if (b != ASN_INTEGER) {
+        /* not from decoded cert, will have algo id, skip past */
+        if (GetSequence(input, inOutIdx, &length, inSz) < 0)
+            return ASN_PARSE_E;
+        
+        b = input[(*inOutIdx)++];
+        if (b != ASN_OBJECT_ID) 
+            return ASN_OBJECT_ID_E;
+        
+        if (GetLength(input, inOutIdx, &length, inSz) < 0)
+            return ASN_PARSE_E;
+        
+        *inOutIdx += length;   /* skip past */
+        
+        /* could have NULL tag and 0 terminator, but may not */
+        b = input[(*inOutIdx)++];
+        
+        if (b == ASN_TAG_NULL) {
+            b = input[(*inOutIdx)++];
+            if (b != 0) 
+                return ASN_EXPECT_0_E;
+        }
+        else
+        /* go back, didn't have it */
+            (*inOutIdx)--;
+        
+        /* should have bit tag length and seq next */
+        b = input[(*inOutIdx)++];
+        if (b != ASN_BIT_STRING)
+            return ASN_BITSTR_E;
+        
+        if (GetLength(input, inOutIdx, &length, inSz) < 0)
+            return ASN_PARSE_E;
+        
+        /* could have 0 */
+        b = input[(*inOutIdx)++];
+        if (b != 0)
+            (*inOutIdx)--;
+        
+        if (GetSequence(input, inOutIdx, &length, inSz) < 0)
+            return ASN_PARSE_E;
+    }  /* end if */
+    }  /* openssl var block */
+#endif /* OPENSSL_EXTRA */
+
+    if (GetInt(&key->n,  input, inOutIdx, inSz) < 0 ||
+        GetInt(&key->e,  input, inOutIdx, inSz) < 0 )  return ASN_RSA_KEY_E;
+
+    return 0;
+}
+
+/* import RSA public key elements (n, e) into RsaKey structure (key) */
+int wc_RsaPublicKeyDecodeRaw(const byte* n, word32 nSz, const byte* e,
+                             word32 eSz, RsaKey* key)
+{
+    if (n == NULL || e == NULL || key == NULL)
+        return BAD_FUNC_ARG;
+
+    key->type = RSA_PUBLIC;
+
+    if (mp_init(&key->n) != MP_OKAY)
+        return MP_INIT_E;
+
+    if (mp_read_unsigned_bin(&key->n, n, nSz) != 0) {
+        mp_clear(&key->n);
+        return ASN_GETINT_E;
+    }
+
+    if (mp_init(&key->e) != MP_OKAY) {
+        mp_clear(&key->n);
+        return MP_INIT_E;
+    }
+
+    if (mp_read_unsigned_bin(&key->e, e, eSz) != 0) {
+        mp_clear(&key->n);
+        mp_clear(&key->e);
+        return ASN_GETINT_E;
+    }
+
+    return 0;
+}
+
+#endif
+
+#ifndef NO_DH
+
+int wc_DhKeyDecode(const byte* input, word32* inOutIdx, DhKey* key, word32 inSz)
+{
+    int    length;
+
+    if (GetSequence(input, inOutIdx, &length, inSz) < 0)
+        return ASN_PARSE_E;
+
+    if (GetInt(&key->p,  input, inOutIdx, inSz) < 0 ||
+        GetInt(&key->g,  input, inOutIdx, inSz) < 0 )  return ASN_DH_KEY_E;
+
+    return 0;
+}
+
+
+int wc_DhParamsLoad(const byte* input, word32 inSz, byte* p, word32* pInOutSz,
+                 byte* g, word32* gInOutSz)
+{
+    word32 i = 0;
+    byte   b;
+    int    length;
+
+    if (GetSequence(input, &i, &length, inSz) < 0)
+        return ASN_PARSE_E;
+
+    b = input[i++];
+    if (b != ASN_INTEGER)
+        return ASN_PARSE_E;
+
+    if (GetLength(input, &i, &length, inSz) < 0)
+        return ASN_PARSE_E;
+
+    if ( (b = input[i++]) == 0x00)
+        length--;
+    else
+        i--;
+
+    if (length <= (int)*pInOutSz) {
+        XMEMCPY(p, &input[i], length);
+        *pInOutSz = length;
+    }
+    else
+        return BUFFER_E;
+
+    i += length;
+
+    b = input[i++];
+    if (b != ASN_INTEGER)
+        return ASN_PARSE_E;
+
+    if (GetLength(input, &i, &length, inSz) < 0)
+        return ASN_PARSE_E;
+
+    if (length <= (int)*gInOutSz) {
+        XMEMCPY(g, &input[i], length);
+        *gInOutSz = length;
+    }
+    else
+        return BUFFER_E;
+
+    return 0;
+}
+
+#endif /* NO_DH */
+
+
+#ifndef NO_DSA
+
+int DsaPublicKeyDecode(const byte* input, word32* inOutIdx, DsaKey* key,
+                        word32 inSz)
+{
+    int    length;
+
+    if (GetSequence(input, inOutIdx, &length, inSz) < 0)
+        return ASN_PARSE_E;
+
+    if (GetInt(&key->p,  input, inOutIdx, inSz) < 0 ||
+        GetInt(&key->q,  input, inOutIdx, inSz) < 0 ||
+        GetInt(&key->g,  input, inOutIdx, inSz) < 0 ||
+        GetInt(&key->y,  input, inOutIdx, inSz) < 0 )  return ASN_DH_KEY_E;
+
+    key->type = DSA_PUBLIC;
+    return 0;
+}
+
+
+int DsaPrivateKeyDecode(const byte* input, word32* inOutIdx, DsaKey* key,
+                        word32 inSz)
+{
+    int    length, version;
+
+    if (GetSequence(input, inOutIdx, &length, inSz) < 0)
+        return ASN_PARSE_E;
+
+    if (GetMyVersion(input, inOutIdx, &version) < 0)
+        return ASN_PARSE_E;
+
+    if (GetInt(&key->p,  input, inOutIdx, inSz) < 0 ||
+        GetInt(&key->q,  input, inOutIdx, inSz) < 0 ||
+        GetInt(&key->g,  input, inOutIdx, inSz) < 0 ||
+        GetInt(&key->y,  input, inOutIdx, inSz) < 0 ||
+        GetInt(&key->x,  input, inOutIdx, inSz) < 0 )  return ASN_DH_KEY_E;
+
+    key->type = DSA_PRIVATE;
+    return 0;
+}
+
+#endif /* NO_DSA */
+
+
+void InitDecodedCert(DecodedCert* cert, byte* source, word32 inSz, void* heap)
+{
+    cert->publicKey       = 0;
+    cert->pubKeySize      = 0;
+    cert->pubKeyStored    = 0;
+    cert->version         = 0;
+    cert->signature       = 0;
+    cert->subjectCN       = 0;
+    cert->subjectCNLen    = 0;
+    cert->subjectCNEnc    = CTC_UTF8;
+    cert->subjectCNStored = 0;
+    cert->weOwnAltNames   = 0;
+    cert->altNames        = NULL;
+#ifndef IGNORE_NAME_CONSTRAINTS
+    cert->altEmailNames   = NULL;
+    cert->permittedNames  = NULL;
+    cert->excludedNames   = NULL;
+#endif /* IGNORE_NAME_CONSTRAINTS */
+    cert->issuer[0]       = '\0';
+    cert->subject[0]      = '\0';
+    cert->source          = source;  /* don't own */
+    cert->srcIdx          = 0;
+    cert->maxIdx          = inSz;    /* can't go over this index */
+    cert->heap            = heap;
+    XMEMSET(cert->serial, 0, EXTERNAL_SERIAL_SIZE);
+    cert->serialSz        = 0;
+    cert->extensions      = 0;
+    cert->extensionsSz    = 0;
+    cert->extensionsIdx   = 0;
+    cert->extAuthInfo     = NULL;
+    cert->extAuthInfoSz   = 0;
+    cert->extCrlInfo      = NULL;
+    cert->extCrlInfoSz    = 0;
+    XMEMSET(cert->extSubjKeyId, 0, KEYID_SIZE);
+    cert->extSubjKeyIdSet = 0;
+    XMEMSET(cert->extAuthKeyId, 0, KEYID_SIZE);
+    cert->extAuthKeyIdSet = 0;
+    cert->extKeyUsageSet  = 0;
+    cert->extKeyUsage     = 0;
+    cert->extExtKeyUsageSet = 0;
+    cert->extExtKeyUsage    = 0;
+    cert->isCA            = 0;
+#ifdef HAVE_PKCS7
+    cert->issuerRaw       = NULL;
+    cert->issuerRawLen    = 0;
+#endif
+#ifdef WOLFSSL_CERT_GEN
+    cert->subjectSN       = 0;
+    cert->subjectSNLen    = 0;
+    cert->subjectSNEnc    = CTC_UTF8;
+    cert->subjectC        = 0;
+    cert->subjectCLen     = 0;
+    cert->subjectCEnc     = CTC_PRINTABLE;
+    cert->subjectL        = 0;
+    cert->subjectLLen     = 0;
+    cert->subjectLEnc     = CTC_UTF8;
+    cert->subjectST       = 0;
+    cert->subjectSTLen    = 0;
+    cert->subjectSTEnc    = CTC_UTF8;
+    cert->subjectO        = 0;
+    cert->subjectOLen     = 0;
+    cert->subjectOEnc     = CTC_UTF8;
+    cert->subjectOU       = 0;
+    cert->subjectOULen    = 0;
+    cert->subjectOUEnc    = CTC_UTF8;
+    cert->subjectEmail    = 0;
+    cert->subjectEmailLen = 0;
+#endif /* WOLFSSL_CERT_GEN */
+    cert->beforeDate      = NULL;
+    cert->beforeDateLen   = 0;
+    cert->afterDate       = NULL;
+    cert->afterDateLen    = 0;
+#ifdef OPENSSL_EXTRA
+    XMEMSET(&cert->issuerName, 0, sizeof(DecodedName));
+    XMEMSET(&cert->subjectName, 0, sizeof(DecodedName));
+    cert->extBasicConstSet = 0;
+    cert->extBasicConstCrit = 0;
+    cert->extBasicConstPlSet = 0;
+    cert->pathLength = 0;
+    cert->extSubjAltNameSet = 0;
+    cert->extSubjAltNameCrit = 0;
+    cert->extAuthKeyIdCrit = 0;
+    cert->extSubjKeyIdCrit = 0;
+    cert->extKeyUsageCrit = 0;
+    cert->extExtKeyUsageCrit = 0;
+    cert->extExtKeyUsageSrc = NULL;
+    cert->extExtKeyUsageSz = 0;
+    cert->extExtKeyUsageCount = 0;
+    cert->extAuthKeyIdSrc = NULL;
+    cert->extAuthKeyIdSz = 0;
+    cert->extSubjKeyIdSrc = NULL;
+    cert->extSubjKeyIdSz = 0;
+#endif /* OPENSSL_EXTRA */
+#if defined(OPENSSL_EXTRA) || !defined(IGNORE_NAME_CONSTRAINTS)
+    cert->extNameConstraintSet = 0;
+#endif /* OPENSSL_EXTRA || !IGNORE_NAME_CONSTRAINTS */
+#ifdef HAVE_ECC
+    cert->pkCurveOID = 0;
+#endif /* HAVE_ECC */
+#ifdef WOLFSSL_SEP
+    cert->deviceTypeSz = 0;
+    cert->deviceType = NULL;
+    cert->hwTypeSz = 0;
+    cert->hwType = NULL;
+    cert->hwSerialNumSz = 0;
+    cert->hwSerialNum = NULL;
+    #ifdef OPENSSL_EXTRA
+        cert->extCertPolicySet = 0;
+        cert->extCertPolicyCrit = 0;
+    #endif /* OPENSSL_EXTRA */
+#endif /* WOLFSSL_SEP */
+}
+
+
+void FreeAltNames(DNS_entry* altNames, void* heap)
+{
+    (void)heap;
+
+    while (altNames) {
+        DNS_entry* tmp = altNames->next;
+
+        XFREE(altNames->name, heap, DYNAMIC_TYPE_ALTNAME);
+        XFREE(altNames,       heap, DYNAMIC_TYPE_ALTNAME);
+        altNames = tmp;
+    }
+}
+
+#ifndef IGNORE_NAME_CONSTRAINTS
+
+void FreeNameSubtrees(Base_entry* names, void* heap)
+{
+    (void)heap;
+
+    while (names) {
+        Base_entry* tmp = names->next;
+
+        XFREE(names->name, heap, DYNAMIC_TYPE_ALTNAME);
+        XFREE(names,       heap, DYNAMIC_TYPE_ALTNAME);
+        names = tmp;
+    }
+}
+
+#endif /* IGNORE_NAME_CONSTRAINTS */
+
+void FreeDecodedCert(DecodedCert* cert)
+{
+    if (cert->subjectCNStored == 1)
+        XFREE(cert->subjectCN, cert->heap, DYNAMIC_TYPE_SUBJECT_CN);
+    if (cert->pubKeyStored == 1)
+        XFREE(cert->publicKey, cert->heap, DYNAMIC_TYPE_PUBLIC_KEY);
+    if (cert->weOwnAltNames && cert->altNames)
+        FreeAltNames(cert->altNames, cert->heap);
+#ifndef IGNORE_NAME_CONSTRAINTS
+    if (cert->altEmailNames)
+        FreeAltNames(cert->altEmailNames, cert->heap);
+    if (cert->permittedNames)
+        FreeNameSubtrees(cert->permittedNames, cert->heap);
+    if (cert->excludedNames)
+        FreeNameSubtrees(cert->excludedNames, cert->heap);
+#endif /* IGNORE_NAME_CONSTRAINTS */
+#ifdef WOLFSSL_SEP
+    XFREE(cert->deviceType, cert->heap, 0);
+    XFREE(cert->hwType, cert->heap, 0);
+    XFREE(cert->hwSerialNum, cert->heap, 0);
+#endif /* WOLFSSL_SEP */
+#ifdef OPENSSL_EXTRA
+    if (cert->issuerName.fullName != NULL)
+        XFREE(cert->issuerName.fullName, NULL, DYNAMIC_TYPE_X509);
+    if (cert->subjectName.fullName != NULL)
+        XFREE(cert->subjectName.fullName, NULL, DYNAMIC_TYPE_X509);
+#endif /* OPENSSL_EXTRA */
+}
+
+
+static int GetCertHeader(DecodedCert* cert)
+{
+    int ret = 0, len;
+    byte serialTmp[EXTERNAL_SERIAL_SIZE];
+#if defined(WOLFSSL_SMALL_STACK) && defined(USE_FAST_MATH)
+    mp_int* mpi = NULL;
+#else
+    mp_int stack_mpi;
+    mp_int* mpi = &stack_mpi;
+#endif
+
+    if (GetSequence(cert->source, &cert->srcIdx, &len, cert->maxIdx) < 0)
+        return ASN_PARSE_E;
+
+    cert->certBegin = cert->srcIdx;
+
+    if (GetSequence(cert->source, &cert->srcIdx, &len, cert->maxIdx) < 0)
+        return ASN_PARSE_E;
+    cert->sigIndex = len + cert->srcIdx;
+
+    if (GetExplicitVersion(cert->source, &cert->srcIdx, &cert->version) < 0)
+        return ASN_PARSE_E;
+
+#if defined(WOLFSSL_SMALL_STACK) && defined(USE_FAST_MATH)
+    mpi = (mp_int*)XMALLOC(sizeof(mp_int), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (mpi == NULL)
+        return MEMORY_E;
+#endif
+
+    if (GetInt(mpi, cert->source, &cert->srcIdx, cert->maxIdx) < 0) {
+#if defined(WOLFSSL_SMALL_STACK) && defined(USE_FAST_MATH)
+        XFREE(mpi, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return ASN_PARSE_E;
+    }
+
+    len = mp_unsigned_bin_size(mpi);
+    if (len < (int)sizeof(serialTmp)) {
+        if ( (ret = mp_to_unsigned_bin(mpi, serialTmp)) == MP_OKAY) {
+            XMEMCPY(cert->serial, serialTmp, len);
+            cert->serialSz = len;
+        }
+    }
+    mp_clear(mpi);
+
+#if defined(WOLFSSL_SMALL_STACK) && defined(USE_FAST_MATH)
+    XFREE(mpi, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+#if !defined(NO_RSA)
+/* Store Rsa Key, may save later, Dsa could use in future */
+static int StoreRsaKey(DecodedCert* cert)
+{
+    int    length;
+    word32 recvd = cert->srcIdx;
+
+    if (GetSequence(cert->source, &cert->srcIdx, &length, cert->maxIdx) < 0)
+        return ASN_PARSE_E;
+   
+    recvd = cert->srcIdx - recvd;
+    length += recvd;
+
+    while (recvd--)
+       cert->srcIdx--;
+
+    cert->pubKeySize = length;
+    cert->publicKey = cert->source + cert->srcIdx;
+    cert->srcIdx += length;
+
+    return 0;
+}
+#endif
+
+
+#ifdef HAVE_ECC
+
+    /* return 0 on sucess if the ECC curve oid sum is supported */
+    static int CheckCurve(word32 oid)
+    {
+        int ret = 0;
+
+        switch (oid) {
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC160)
+            case ECC_160R1:
+#endif
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC192)
+            case ECC_192R1:
+#endif
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC224)
+            case ECC_224R1:
+#endif
+#if defined(HAVE_ALL_CURVES) || !defined(NO_ECC256)
+            case ECC_256R1:
+#endif
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC384)
+            case ECC_384R1:
+#endif
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC521)
+            case ECC_521R1:
+#endif
+                break;
+
+            default:
+                ret = ALGO_ID_E;
+        }
+
+        return ret;
+    }
+
+#endif /* HAVE_ECC */
+
+
+static int GetKey(DecodedCert* cert)
+{
+    int length;
+#ifdef HAVE_NTRU
+    int tmpIdx = cert->srcIdx;
+#endif
+
+    if (GetSequence(cert->source, &cert->srcIdx, &length, cert->maxIdx) < 0)
+        return ASN_PARSE_E;
+   
+    if (GetAlgoId(cert->source, &cert->srcIdx, &cert->keyOID, cert->maxIdx) < 0)
+        return ASN_PARSE_E;
+
+    switch (cert->keyOID) {
+   #ifndef NO_RSA
+        case RSAk:
+        {
+            byte b = cert->source[cert->srcIdx++];
+            if (b != ASN_BIT_STRING)
+                return ASN_BITSTR_E;
+
+            if (GetLength(cert->source,&cert->srcIdx,&length,cert->maxIdx) < 0)
+                return ASN_PARSE_E;
+            b = cert->source[cert->srcIdx++];
+            if (b != 0x00)
+                return ASN_EXPECT_0_E;
+    
+            return StoreRsaKey(cert);
+        }
+
+    #endif /* NO_RSA */
+    #ifdef HAVE_NTRU
+        case NTRUk:
+        {
+            const byte* key = &cert->source[tmpIdx];
+            byte*       next = (byte*)key;
+            word16      keyLen;
+            word32      rc;
+            word32      remaining = cert->maxIdx - cert->srcIdx;
+#ifdef WOLFSSL_SMALL_STACK
+            byte*       keyBlob = NULL;
+#else
+            byte        keyBlob[MAX_NTRU_KEY_SZ];
+#endif
+            rc = ntru_crypto_ntru_encrypt_subjectPublicKeyInfo2PublicKey(key,
+                                &keyLen, NULL, &next, &remaining);
+            if (rc != NTRU_OK)
+                return ASN_NTRU_KEY_E;
+            if (keyLen > MAX_NTRU_KEY_SZ)
+                return ASN_NTRU_KEY_E;
+
+#ifdef WOLFSSL_SMALL_STACK
+            keyBlob = (byte*)XMALLOC(MAX_NTRU_KEY_SZ, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+            if (keyBlob == NULL)
+                return MEMORY_E;
+#endif
+
+            rc = ntru_crypto_ntru_encrypt_subjectPublicKeyInfo2PublicKey(key,
+                                &keyLen, keyBlob, &next, &remaining);
+            if (rc != NTRU_OK) {
+#ifdef WOLFSSL_SMALL_STACK
+                XFREE(keyBlob, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+                return ASN_NTRU_KEY_E;
+            }
+
+            if ( (next - key) < 0) {
+#ifdef WOLFSSL_SMALL_STACK
+                XFREE(keyBlob, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+                return ASN_NTRU_KEY_E;
+            }
+
+            cert->srcIdx = tmpIdx + (int)(next - key);
+
+            cert->publicKey = (byte*) XMALLOC(keyLen, cert->heap,
+                                              DYNAMIC_TYPE_PUBLIC_KEY);
+            if (cert->publicKey == NULL) {
+#ifdef WOLFSSL_SMALL_STACK
+                XFREE(keyBlob, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+                return MEMORY_E;
+            }
+            XMEMCPY(cert->publicKey, keyBlob, keyLen);
+            cert->pubKeyStored = 1;
+            cert->pubKeySize   = keyLen;
+
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(keyBlob, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+            return 0;
+        }
+    #endif /* HAVE_NTRU */
+    #ifdef HAVE_ECC
+        case ECDSAk:
+        {
+            int    oidSz = 0;
+            byte   b = cert->source[cert->srcIdx++];
+        
+            if (b != ASN_OBJECT_ID) 
+                return ASN_OBJECT_ID_E;
+
+            if (GetLength(cert->source,&cert->srcIdx,&oidSz,cert->maxIdx) < 0)
+                return ASN_PARSE_E;
+
+            while(oidSz--)
+                cert->pkCurveOID += cert->source[cert->srcIdx++];
+
+            if (CheckCurve(cert->pkCurveOID) < 0)
+                return ECC_CURVE_OID_E;
+
+            /* key header */
+            b = cert->source[cert->srcIdx++];
+            if (b != ASN_BIT_STRING)
+                return ASN_BITSTR_E;
+
+            if (GetLength(cert->source,&cert->srcIdx,&length,cert->maxIdx) < 0)
+                return ASN_PARSE_E;
+            b = cert->source[cert->srcIdx++];
+            if (b != 0x00)
+                return ASN_EXPECT_0_E;
+
+            /* actual key, use length - 1 since ate preceding 0 */
+            length -= 1;
+
+            cert->publicKey = (byte*) XMALLOC(length, cert->heap,
+                                              DYNAMIC_TYPE_PUBLIC_KEY);
+            if (cert->publicKey == NULL)
+                return MEMORY_E;
+            XMEMCPY(cert->publicKey, &cert->source[cert->srcIdx], length);
+            cert->pubKeyStored = 1;
+            cert->pubKeySize   = length;
+
+            cert->srcIdx += length;
+
+            return 0;
+        }
+    #endif /* HAVE_ECC */
+        default:
+            return ASN_UNKNOWN_OID_E;
+    }
+}
+
+
+/* process NAME, either issuer or subject */
+static int GetName(DecodedCert* cert, int nameType)
+{
+    int    length;  /* length of all distinguished names */
+    int    dummy;
+    int    ret;
+    char*  full;
+    byte*  hash;
+    word32 idx;
+    #ifdef OPENSSL_EXTRA
+        DecodedName* dName =
+                  (nameType == ISSUER) ? &cert->issuerName : &cert->subjectName;
+    #endif /* OPENSSL_EXTRA */
+
+    WOLFSSL_MSG("Getting Cert Name");
+
+    if (nameType == ISSUER) {
+        full = cert->issuer;
+        hash = cert->issuerHash;
+    }
+    else {
+        full = cert->subject;
+        hash = cert->subjectHash;
+    }
+
+    if (cert->source[cert->srcIdx] == ASN_OBJECT_ID) {
+        WOLFSSL_MSG("Trying optional prefix...");
+
+        if (GetLength(cert->source, &cert->srcIdx, &length, cert->maxIdx) < 0)
+            return ASN_PARSE_E;
+
+        cert->srcIdx += length;
+        WOLFSSL_MSG("Got optional prefix");
+    }
+
+    /* For OCSP, RFC2560 section 4.1.1 states the issuer hash should be
+     * calculated over the entire DER encoding of the Name field, including
+     * the tag and length. */
+    idx = cert->srcIdx;
+    if (GetSequence(cert->source, &cert->srcIdx, &length, cert->maxIdx) < 0)
+        return ASN_PARSE_E;
+
+#ifdef NO_SHA
+    ret = wc_Sha256Hash(&cert->source[idx], length + cert->srcIdx - idx, hash);
+#else
+    ret = wc_ShaHash(&cert->source[idx], length + cert->srcIdx - idx, hash);
+#endif
+    if (ret != 0)
+        return ret;
+
+    length += cert->srcIdx;
+    idx = 0;
+
+#ifdef HAVE_PKCS7
+    /* store pointer to raw issuer */
+    if (nameType == ISSUER) {
+        cert->issuerRaw = &cert->source[cert->srcIdx];
+        cert->issuerRawLen = length - cert->srcIdx;
+    }
+#endif
+#ifndef IGNORE_NAME_CONSTRAINTS
+    if (nameType == SUBJECT) {
+        cert->subjectRaw = &cert->source[cert->srcIdx];
+        cert->subjectRawLen = length - cert->srcIdx;
+    }
+#endif
+
+    while (cert->srcIdx < (word32)length) {
+        byte   b;
+        byte   joint[2];
+        byte   tooBig = FALSE;
+        int    oidSz;
+
+        if (GetSet(cert->source, &cert->srcIdx, &dummy, cert->maxIdx) < 0) {
+            WOLFSSL_MSG("Cert name lacks set header, trying sequence");
+        }
+
+        if (GetSequence(cert->source, &cert->srcIdx, &dummy, cert->maxIdx) < 0)
+            return ASN_PARSE_E;
+
+        b = cert->source[cert->srcIdx++];
+        if (b != ASN_OBJECT_ID) 
+            return ASN_OBJECT_ID_E;
+
+        if (GetLength(cert->source, &cert->srcIdx, &oidSz, cert->maxIdx) < 0)
+            return ASN_PARSE_E;
+
+        XMEMCPY(joint, &cert->source[cert->srcIdx], sizeof(joint));
+
+        /* v1 name types */
+        if (joint[0] == 0x55 && joint[1] == 0x04) {
+            byte   id;
+            byte   copy = FALSE;
+            int    strLen;
+
+            cert->srcIdx += 2;
+            id = cert->source[cert->srcIdx++]; 
+            b  = cert->source[cert->srcIdx++]; /* encoding */
+
+            if (GetLength(cert->source, &cert->srcIdx, &strLen,
+                          cert->maxIdx) < 0)
+                return ASN_PARSE_E;
+
+            if ( (strLen + 14) > (int)(ASN_NAME_MAX - idx)) {
+                /* include biggest pre fix header too 4 = "/serialNumber=" */
+                WOLFSSL_MSG("ASN Name too big, skipping");
+                tooBig = TRUE;
+            }
+
+            if (id == ASN_COMMON_NAME) {
+                if (nameType == SUBJECT) {
+                    cert->subjectCN = (char *)&cert->source[cert->srcIdx];
+                    cert->subjectCNLen = strLen;
+                    cert->subjectCNEnc = b;
+                }
+
+                if (!tooBig) {
+                    XMEMCPY(&full[idx], "/CN=", 4);
+                    idx += 4;
+                    copy = TRUE;
+                }
+                #ifdef OPENSSL_EXTRA
+                    dName->cnIdx = cert->srcIdx;
+                    dName->cnLen = strLen;
+                #endif /* OPENSSL_EXTRA */
+            }
+            else if (id == ASN_SUR_NAME) {
+                if (!tooBig) {
+                    XMEMCPY(&full[idx], "/SN=", 4);
+                    idx += 4;
+                    copy = TRUE;
+                }
+                #ifdef WOLFSSL_CERT_GEN
+                    if (nameType == SUBJECT) {
+                        cert->subjectSN = (char*)&cert->source[cert->srcIdx];
+                        cert->subjectSNLen = strLen;
+                        cert->subjectSNEnc = b;
+                    }
+                #endif /* WOLFSSL_CERT_GEN */
+                #ifdef OPENSSL_EXTRA
+                    dName->snIdx = cert->srcIdx;
+                    dName->snLen = strLen;
+                #endif /* OPENSSL_EXTRA */
+            }
+            else if (id == ASN_COUNTRY_NAME) {
+                if (!tooBig) {
+                    XMEMCPY(&full[idx], "/C=", 3);
+                    idx += 3;
+                    copy = TRUE;
+                }
+                #ifdef WOLFSSL_CERT_GEN
+                    if (nameType == SUBJECT) {
+                        cert->subjectC = (char*)&cert->source[cert->srcIdx];
+                        cert->subjectCLen = strLen;
+                        cert->subjectCEnc = b;
+                    }
+                #endif /* WOLFSSL_CERT_GEN */
+                #ifdef OPENSSL_EXTRA
+                    dName->cIdx = cert->srcIdx;
+                    dName->cLen = strLen;
+                #endif /* OPENSSL_EXTRA */
+            }
+            else if (id == ASN_LOCALITY_NAME) {
+                if (!tooBig) {
+                    XMEMCPY(&full[idx], "/L=", 3);
+                    idx += 3;
+                    copy = TRUE;
+                }
+                #ifdef WOLFSSL_CERT_GEN
+                    if (nameType == SUBJECT) {
+                        cert->subjectL = (char*)&cert->source[cert->srcIdx];
+                        cert->subjectLLen = strLen;
+                        cert->subjectLEnc = b;
+                    }
+                #endif /* WOLFSSL_CERT_GEN */
+                #ifdef OPENSSL_EXTRA
+                    dName->lIdx = cert->srcIdx;
+                    dName->lLen = strLen;
+                #endif /* OPENSSL_EXTRA */
+            }
+            else if (id == ASN_STATE_NAME) {
+                if (!tooBig) {
+                    XMEMCPY(&full[idx], "/ST=", 4);
+                    idx += 4;
+                    copy = TRUE;
+                }
+                #ifdef WOLFSSL_CERT_GEN
+                    if (nameType == SUBJECT) {
+                        cert->subjectST = (char*)&cert->source[cert->srcIdx];
+                        cert->subjectSTLen = strLen;
+                        cert->subjectSTEnc = b;
+                    }
+                #endif /* WOLFSSL_CERT_GEN */
+                #ifdef OPENSSL_EXTRA
+                    dName->stIdx = cert->srcIdx;
+                    dName->stLen = strLen;
+                #endif /* OPENSSL_EXTRA */
+            }
+            else if (id == ASN_ORG_NAME) {
+                if (!tooBig) {
+                    XMEMCPY(&full[idx], "/O=", 3);
+                    idx += 3;
+                    copy = TRUE;
+                }
+                #ifdef WOLFSSL_CERT_GEN
+                    if (nameType == SUBJECT) {
+                        cert->subjectO = (char*)&cert->source[cert->srcIdx];
+                        cert->subjectOLen = strLen;
+                        cert->subjectOEnc = b;
+                    }
+                #endif /* WOLFSSL_CERT_GEN */
+                #ifdef OPENSSL_EXTRA
+                    dName->oIdx = cert->srcIdx;
+                    dName->oLen = strLen;
+                #endif /* OPENSSL_EXTRA */
+            }
+            else if (id == ASN_ORGUNIT_NAME) {
+                if (!tooBig) {
+                    XMEMCPY(&full[idx], "/OU=", 4);
+                    idx += 4;
+                    copy = TRUE;
+                }
+                #ifdef WOLFSSL_CERT_GEN
+                    if (nameType == SUBJECT) {
+                        cert->subjectOU = (char*)&cert->source[cert->srcIdx];
+                        cert->subjectOULen = strLen;
+                        cert->subjectOUEnc = b;
+                    }
+                #endif /* WOLFSSL_CERT_GEN */
+                #ifdef OPENSSL_EXTRA
+                    dName->ouIdx = cert->srcIdx;
+                    dName->ouLen = strLen;
+                #endif /* OPENSSL_EXTRA */
+            }
+            else if (id == ASN_SERIAL_NUMBER) {
+                if (!tooBig) {
+                   XMEMCPY(&full[idx], "/serialNumber=", 14);
+                   idx += 14;
+                   copy = TRUE;
+                }
+                #ifdef OPENSSL_EXTRA
+                    dName->snIdx = cert->srcIdx;
+                    dName->snLen = strLen;
+                #endif /* OPENSSL_EXTRA */
+            }
+
+            if (copy && !tooBig) {
+                XMEMCPY(&full[idx], &cert->source[cert->srcIdx], strLen);
+                idx += strLen;
+            }
+
+            cert->srcIdx += strLen;
+        }
+        else {
+            /* skip */
+            byte email = FALSE;
+            byte uid   = FALSE;
+            int  adv;
+
+            if (joint[0] == 0x2a && joint[1] == 0x86)  /* email id hdr */
+                email = TRUE;
+
+            if (joint[0] == 0x9  && joint[1] == 0x92)  /* uid id hdr */
+                uid = TRUE;
+
+            cert->srcIdx += oidSz + 1;
+
+            if (GetLength(cert->source, &cert->srcIdx, &adv, cert->maxIdx) < 0)
+                return ASN_PARSE_E;
+
+            if (adv > (int)(ASN_NAME_MAX - idx)) {
+                WOLFSSL_MSG("ASN name too big, skipping");
+                tooBig = TRUE;
+            }
+
+            if (email) {
+                if ( (14 + adv) > (int)(ASN_NAME_MAX - idx)) {
+                    WOLFSSL_MSG("ASN name too big, skipping");
+                    tooBig = TRUE;
+                }
+                if (!tooBig) {
+                    XMEMCPY(&full[idx], "/emailAddress=", 14);
+                    idx += 14;
+                }
+
+                #ifdef WOLFSSL_CERT_GEN
+                    if (nameType == SUBJECT) {
+                        cert->subjectEmail = (char*)&cert->source[cert->srcIdx];
+                        cert->subjectEmailLen = adv;
+                    }
+                #endif /* WOLFSSL_CERT_GEN */
+                #ifdef OPENSSL_EXTRA
+                    dName->emailIdx = cert->srcIdx;
+                    dName->emailLen = adv;
+                #endif /* OPENSSL_EXTRA */
+                #ifndef IGNORE_NAME_CONSTRAINTS
+                    {
+                        DNS_entry* emailName = NULL;
+
+                        emailName = (DNS_entry*)XMALLOC(sizeof(DNS_entry),
+                                              cert->heap, DYNAMIC_TYPE_ALTNAME);
+                        if (emailName == NULL) {
+                            WOLFSSL_MSG("\tOut of Memory");
+                            return MEMORY_E;
+                        }
+                        emailName->name = (char*)XMALLOC(adv + 1,
+                                              cert->heap, DYNAMIC_TYPE_ALTNAME);
+                        if (emailName->name == NULL) {
+                            WOLFSSL_MSG("\tOut of Memory");
+                            return MEMORY_E;
+                        }
+                        XMEMCPY(emailName->name,
+                                              &cert->source[cert->srcIdx], adv);
+                        emailName->name[adv] = 0;
+
+                        emailName->next = cert->altEmailNames;
+                        cert->altEmailNames = emailName;
+                    }
+                #endif /* IGNORE_NAME_CONSTRAINTS */
+                if (!tooBig) {
+                    XMEMCPY(&full[idx], &cert->source[cert->srcIdx], adv);
+                    idx += adv;
+                }
+            }
+
+            if (uid) {
+                if ( (5 + adv) > (int)(ASN_NAME_MAX - idx)) {
+                    WOLFSSL_MSG("ASN name too big, skipping");
+                    tooBig = TRUE;
+                }
+                if (!tooBig) {
+                    XMEMCPY(&full[idx], "/UID=", 5);
+                    idx += 5;
+
+                    XMEMCPY(&full[idx], &cert->source[cert->srcIdx], adv);
+                    idx += adv;
+                }
+                #ifdef OPENSSL_EXTRA
+                    dName->uidIdx = cert->srcIdx;
+                    dName->uidLen = adv;
+                #endif /* OPENSSL_EXTRA */
+            }
+
+            cert->srcIdx += adv;
+        }
+    }
+    full[idx++] = 0;
+
+    #ifdef OPENSSL_EXTRA
+    {
+        int totalLen = 0;
+
+        if (dName->cnLen != 0)
+            totalLen += dName->cnLen + 4;
+        if (dName->snLen != 0)
+            totalLen += dName->snLen + 4;
+        if (dName->cLen != 0)
+            totalLen += dName->cLen + 3;
+        if (dName->lLen != 0)
+            totalLen += dName->lLen + 3;
+        if (dName->stLen != 0)
+            totalLen += dName->stLen + 4;
+        if (dName->oLen != 0)
+            totalLen += dName->oLen + 3;
+        if (dName->ouLen != 0)
+            totalLen += dName->ouLen + 4;
+        if (dName->emailLen != 0)
+            totalLen += dName->emailLen + 14;
+        if (dName->uidLen != 0)
+            totalLen += dName->uidLen + 5;
+        if (dName->serialLen != 0)
+            totalLen += dName->serialLen + 14;
+
+        dName->fullName = (char*)XMALLOC(totalLen + 1, NULL, DYNAMIC_TYPE_X509);
+        if (dName->fullName != NULL) {
+            idx = 0;
+
+            if (dName->cnLen != 0) {
+                dName->entryCount++;
+                XMEMCPY(&dName->fullName[idx], "/CN=", 4);
+                idx += 4;
+                XMEMCPY(&dName->fullName[idx],
+                                     &cert->source[dName->cnIdx], dName->cnLen);
+                dName->cnIdx = idx;
+                idx += dName->cnLen;
+            }
+            if (dName->snLen != 0) {
+                dName->entryCount++;
+                XMEMCPY(&dName->fullName[idx], "/SN=", 4);
+                idx += 4;
+                XMEMCPY(&dName->fullName[idx],
+                                     &cert->source[dName->snIdx], dName->snLen);
+                dName->snIdx = idx;
+                idx += dName->snLen;
+            }
+            if (dName->cLen != 0) {
+                dName->entryCount++;
+                XMEMCPY(&dName->fullName[idx], "/C=", 3);
+                idx += 3;
+                XMEMCPY(&dName->fullName[idx],
+                                       &cert->source[dName->cIdx], dName->cLen);
+                dName->cIdx = idx;
+                idx += dName->cLen;
+            }
+            if (dName->lLen != 0) {
+                dName->entryCount++;
+                XMEMCPY(&dName->fullName[idx], "/L=", 3);
+                idx += 3;
+                XMEMCPY(&dName->fullName[idx],
+                                       &cert->source[dName->lIdx], dName->lLen);
+                dName->lIdx = idx;
+                idx += dName->lLen;
+            }
+            if (dName->stLen != 0) {
+                dName->entryCount++;
+                XMEMCPY(&dName->fullName[idx], "/ST=", 4);
+                idx += 4;
+                XMEMCPY(&dName->fullName[idx],
+                                     &cert->source[dName->stIdx], dName->stLen);
+                dName->stIdx = idx;
+                idx += dName->stLen;
+            }
+            if (dName->oLen != 0) {
+                dName->entryCount++;
+                XMEMCPY(&dName->fullName[idx], "/O=", 3);
+                idx += 3;
+                XMEMCPY(&dName->fullName[idx],
+                                       &cert->source[dName->oIdx], dName->oLen);
+                dName->oIdx = idx;
+                idx += dName->oLen;
+            }
+            if (dName->ouLen != 0) {
+                dName->entryCount++;
+                XMEMCPY(&dName->fullName[idx], "/OU=", 4);
+                idx += 4;
+                XMEMCPY(&dName->fullName[idx],
+                                     &cert->source[dName->ouIdx], dName->ouLen);
+                dName->ouIdx = idx;
+                idx += dName->ouLen;
+            }
+            if (dName->emailLen != 0) {
+                dName->entryCount++;
+                XMEMCPY(&dName->fullName[idx], "/emailAddress=", 14);
+                idx += 14;
+                XMEMCPY(&dName->fullName[idx],
+                               &cert->source[dName->emailIdx], dName->emailLen);
+                dName->emailIdx = idx;
+                idx += dName->emailLen;
+            }
+            if (dName->uidLen != 0) {
+                dName->entryCount++;
+                XMEMCPY(&dName->fullName[idx], "/UID=", 5);
+                idx += 5;
+                XMEMCPY(&dName->fullName[idx],
+                                   &cert->source[dName->uidIdx], dName->uidLen);
+                dName->uidIdx = idx;
+                idx += dName->uidLen;
+            }
+            if (dName->serialLen != 0) {
+                dName->entryCount++;
+                XMEMCPY(&dName->fullName[idx], "/serialNumber=", 14);
+                idx += 14;
+                XMEMCPY(&dName->fullName[idx],
+                             &cert->source[dName->serialIdx], dName->serialLen);
+                dName->serialIdx = idx;
+                idx += dName->serialLen;
+            }
+            dName->fullName[idx] = '\0';
+            dName->fullNameLen = totalLen;
+        }
+    }
+    #endif /* OPENSSL_EXTRA */
+
+    return 0;
+}
+
+
+#ifndef NO_TIME_H
+
+/* to the second */
+static int DateGreaterThan(const struct tm* a, const struct tm* b)
+{
+    if (a->tm_year > b->tm_year)
+        return 1;
+
+    if (a->tm_year == b->tm_year && a->tm_mon > b->tm_mon)
+        return 1;
+    
+    if (a->tm_year == b->tm_year && a->tm_mon == b->tm_mon &&
+           a->tm_mday > b->tm_mday)
+        return 1;
+
+    if (a->tm_year == b->tm_year && a->tm_mon == b->tm_mon &&
+        a->tm_mday == b->tm_mday && a->tm_hour > b->tm_hour)
+        return 1;
+
+    if (a->tm_year == b->tm_year && a->tm_mon == b->tm_mon &&
+        a->tm_mday == b->tm_mday && a->tm_hour == b->tm_hour &&
+        a->tm_min > b->tm_min)
+        return 1;
+
+    if (a->tm_year == b->tm_year && a->tm_mon == b->tm_mon &&
+        a->tm_mday == b->tm_mday && a->tm_hour == b->tm_hour &&
+        a->tm_min  == b->tm_min  && a->tm_sec > b->tm_sec)
+        return 1;
+
+    return 0; /* false */
+}
+
+
+static INLINE int DateLessThan(const struct tm* a, const struct tm* b)
+{
+    return DateGreaterThan(b,a);
+}
+
+
+/* like atoi but only use first byte */
+/* Make sure before and after dates are valid */
+int ValidateDate(const byte* date, byte format, int dateType)
+{
+    time_t ltime;
+    struct tm  certTime;
+    struct tm* localTime;
+    struct tm* tmpTime = NULL;
+    int    i = 0;
+
+#if defined(FREESCALE_MQX) || defined(TIME_OVERRIDES)
+    struct tm tmpTimeStorage;
+    tmpTime = &tmpTimeStorage;
+#else
+    (void)tmpTime;
+#endif
+
+    ltime = XTIME(0);
+    XMEMSET(&certTime, 0, sizeof(certTime));
+
+    if (format == ASN_UTC_TIME) {
+        if (btoi(date[0]) >= 5)
+            certTime.tm_year = 1900;
+        else
+            certTime.tm_year = 2000;
+    }
+    else  { /* format == GENERALIZED_TIME */
+        certTime.tm_year += btoi(date[i++]) * 1000;
+        certTime.tm_year += btoi(date[i++]) * 100;
+    }
+
+    /* adjust tm_year, tm_mon */
+    GetTime((int*)&certTime.tm_year, date, &i); certTime.tm_year -= 1900;
+    GetTime((int*)&certTime.tm_mon,  date, &i); certTime.tm_mon  -= 1;
+    GetTime((int*)&certTime.tm_mday, date, &i);
+    GetTime((int*)&certTime.tm_hour, date, &i);
+    GetTime((int*)&certTime.tm_min,  date, &i);
+    GetTime((int*)&certTime.tm_sec,  date, &i);
+
+        if (date[i] != 'Z') {     /* only Zulu supported for this profile */
+        WOLFSSL_MSG("Only Zulu time supported for this profile");
+        return 0;
+    }
+
+    localTime = XGMTIME(<ime, tmpTime);
+
+    if (dateType == BEFORE) {
+        if (DateLessThan(localTime, &certTime))
+            return 0;
+    }
+    else
+        if (DateGreaterThan(localTime, &certTime))
+            return 0;
+
+    return 1;
+}
+
+#endif /* NO_TIME_H */
+
+
+static int GetDate(DecodedCert* cert, int dateType)
+{
+    int    length;
+    byte   date[MAX_DATE_SIZE];
+    byte   b;
+    word32 startIdx = 0;
+
+    if (dateType == BEFORE)
+        cert->beforeDate = &cert->source[cert->srcIdx];
+    else
+        cert->afterDate = &cert->source[cert->srcIdx];
+    startIdx = cert->srcIdx;
+
+    b = cert->source[cert->srcIdx++];
+    if (b != ASN_UTC_TIME && b != ASN_GENERALIZED_TIME)
+        return ASN_TIME_E;
+
+    if (GetLength(cert->source, &cert->srcIdx, &length, cert->maxIdx) < 0)
+        return ASN_PARSE_E;
+
+    if (length > MAX_DATE_SIZE || length < MIN_DATE_SIZE)
+        return ASN_DATE_SZ_E;
+
+    XMEMCPY(date, &cert->source[cert->srcIdx], length);
+    cert->srcIdx += length;
+
+    if (dateType == BEFORE)
+        cert->beforeDateLen = cert->srcIdx - startIdx;
+    else
+        cert->afterDateLen  = cert->srcIdx - startIdx;
+
+    if (!XVALIDATE_DATE(date, b, dateType)) {
+        if (dateType == BEFORE)
+            return ASN_BEFORE_DATE_E;
+        else
+            return ASN_AFTER_DATE_E;
+    }
+
+    return 0;
+}
+
+
+static int GetValidity(DecodedCert* cert, int verify)
+{
+    int length;
+    int badDate = 0;
+
+    if (GetSequence(cert->source, &cert->srcIdx, &length, cert->maxIdx) < 0)
+        return ASN_PARSE_E;
+
+    if (GetDate(cert, BEFORE) < 0 && verify)
+        badDate = ASN_BEFORE_DATE_E;           /* continue parsing */
+    
+    if (GetDate(cert, AFTER) < 0 && verify)
+        return ASN_AFTER_DATE_E;
+   
+    if (badDate != 0)
+        return badDate;
+
+    return 0;
+}
+
+
+int DecodeToKey(DecodedCert* cert, int verify)
+{
+    int badDate = 0;
+    int ret;
+
+    if ( (ret = GetCertHeader(cert)) < 0)
+        return ret;
+
+    WOLFSSL_MSG("Got Cert Header");
+
+    if ( (ret = GetAlgoId(cert->source, &cert->srcIdx, &cert->signatureOID,
+                          cert->maxIdx)) < 0)
+        return ret;
+
+    WOLFSSL_MSG("Got Algo ID");
+
+    if ( (ret = GetName(cert, ISSUER)) < 0)
+        return ret;
+
+    if ( (ret = GetValidity(cert, verify)) < 0)
+        badDate = ret;
+
+    if ( (ret = GetName(cert, SUBJECT)) < 0)
+        return ret;
+
+    WOLFSSL_MSG("Got Subject Name");
+
+    if ( (ret = GetKey(cert)) < 0)
+        return ret;
+
+    WOLFSSL_MSG("Got Key");
+
+    if (badDate != 0)
+        return badDate;
+
+    return ret;
+}
+
+
+static int GetSignature(DecodedCert* cert)
+{
+    int    length;
+    byte   b = cert->source[cert->srcIdx++];
+
+    if (b != ASN_BIT_STRING)
+        return ASN_BITSTR_E;
+
+    if (GetLength(cert->source, &cert->srcIdx, &length, cert->maxIdx) < 0)
+        return ASN_PARSE_E;
+
+    cert->sigLength = length;
+
+    b = cert->source[cert->srcIdx++];
+    if (b != 0x00)
+        return ASN_EXPECT_0_E;
+
+    cert->sigLength--;
+    cert->signature = &cert->source[cert->srcIdx];
+    cert->srcIdx += cert->sigLength;
+
+    return 0;
+}
+
+
+static word32 SetDigest(const byte* digest, word32 digSz, byte* output)
+{
+    output[0] = ASN_OCTET_STRING;
+    output[1] = (byte)digSz;
+    XMEMCPY(&output[2], digest, digSz);
+
+    return digSz + 2;
+} 
+
+
+static word32 BytePrecision(word32 value)
+{
+    word32 i;
+    for (i = sizeof(value); i; --i)
+        if (value >> ((i - 1) * WOLFSSL_BIT_SIZE))
+            break;
+
+    return i;
+}
+
+
+WOLFSSL_LOCAL word32 SetLength(word32 length, byte* output)
+{
+    word32 i = 0, j;
+
+    if (length < ASN_LONG_LENGTH)
+        output[i++] = (byte)length;
+    else {
+        output[i++] = (byte)(BytePrecision(length) | ASN_LONG_LENGTH);
+      
+        for (j = BytePrecision(length); j; --j) {
+            output[i] = (byte)(length >> ((j - 1) * WOLFSSL_BIT_SIZE));
+            i++;
+        }
+    }
+
+    return i;
+}
+
+
+WOLFSSL_LOCAL word32 SetSequence(word32 len, byte* output)
+{
+    output[0] = ASN_SEQUENCE | ASN_CONSTRUCTED;
+    return SetLength(len, output + 1) + 1;
+}
+
+WOLFSSL_LOCAL word32 SetOctetString(word32 len, byte* output)
+{
+    output[0] = ASN_OCTET_STRING;
+    return SetLength(len, output + 1) + 1;
+}
+
+/* Write a set header to output */
+WOLFSSL_LOCAL word32 SetSet(word32 len, byte* output)
+{
+    output[0] = ASN_SET | ASN_CONSTRUCTED;
+    return SetLength(len, output + 1) + 1;
+}
+
+WOLFSSL_LOCAL word32 SetImplicit(byte tag, byte number, word32 len, byte* output)
+{
+
+    output[0] = ((tag == ASN_SEQUENCE || tag == ASN_SET) ? ASN_CONSTRUCTED : 0)
+                    | ASN_CONTEXT_SPECIFIC | number;
+    return SetLength(len, output + 1) + 1;
+}
+
+WOLFSSL_LOCAL word32 SetExplicit(byte number, word32 len, byte* output)
+{
+    output[0] = ASN_CONSTRUCTED | ASN_CONTEXT_SPECIFIC | number;
+    return SetLength(len, output + 1) + 1;
+}
+
+
+#if defined(HAVE_ECC) && (defined(WOLFSSL_CERT_GEN) || defined(WOLFSSL_KEY_GEN))
+
+static word32 SetCurve(ecc_key* key, byte* output)
+{
+
+    /* curve types */
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC192)
+    static const byte ECC_192v1_AlgoID[] = { 0x2a, 0x86, 0x48, 0xCE, 0x3d,
+                                             0x03, 0x01, 0x01};
+#endif
+#if defined(HAVE_ALL_CURVES) || !defined(NO_ECC256)
+    static const byte ECC_256v1_AlgoID[] = { 0x2a, 0x86, 0x48, 0xCE, 0x3d,
+                                            0x03, 0x01, 0x07};
+#endif
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC160)
+    static const byte ECC_160r1_AlgoID[] = { 0x2b, 0x81, 0x04, 0x00,
+                                             0x02};
+#endif
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC224)
+    static const byte ECC_224r1_AlgoID[] = { 0x2b, 0x81, 0x04, 0x00,
+                                             0x21};
+#endif
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC384)
+    static const byte ECC_384r1_AlgoID[] = { 0x2b, 0x81, 0x04, 0x00,
+                                             0x22};
+#endif
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC521)
+    static const byte ECC_521r1_AlgoID[] = { 0x2b, 0x81, 0x04, 0x00,
+                                             0x23};
+#endif
+
+    int    oidSz = 0;
+    int    idx = 0;
+    int    lenSz = 0;
+    const  byte* oid = 0;
+
+    output[0] = ASN_OBJECT_ID;
+    idx++;
+
+    switch (key->dp->size) {
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC160)
+        case 20:
+            oidSz = sizeof(ECC_160r1_AlgoID);
+            oid   =        ECC_160r1_AlgoID;
+            break;
+#endif
+
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC192)
+        case 24:
+            oidSz = sizeof(ECC_192v1_AlgoID);
+            oid   =        ECC_192v1_AlgoID;
+            break;
+#endif
+
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC224)
+        case 28:
+            oidSz = sizeof(ECC_224r1_AlgoID);
+            oid   =        ECC_224r1_AlgoID;
+            break;
+#endif
+
+#if defined(HAVE_ALL_CURVES) || !defined(NO_ECC256)
+        case 32:
+            oidSz = sizeof(ECC_256v1_AlgoID);
+            oid   =        ECC_256v1_AlgoID;
+            break;
+#endif
+
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC384)
+        case 48:
+            oidSz = sizeof(ECC_384r1_AlgoID);
+            oid   =        ECC_384r1_AlgoID;
+            break;
+#endif
+
+#if defined(HAVE_ALL_CURVES) || defined(HAVE_ECC521)
+        case 66:
+            oidSz = sizeof(ECC_521r1_AlgoID);
+            oid   =        ECC_521r1_AlgoID;
+            break;
+#endif
+
+        default:
+            return ASN_UNKNOWN_OID_E;
+    }
+    lenSz = SetLength(oidSz, output+idx);
+    idx += lenSz;
+
+    XMEMCPY(output+idx, oid, oidSz);
+    idx += oidSz;
+
+    return idx;
+}
+
+#endif /* HAVE_ECC && WOLFSSL_CERT_GEN */
+
+
+WOLFSSL_LOCAL word32 SetAlgoID(int algoOID, byte* output, int type, int curveSz)
+{
+    /* adding TAG_NULL and 0 to end */
+    
+    /* hashTypes */
+    static const byte shaAlgoID[]    = { 0x2b, 0x0e, 0x03, 0x02, 0x1a,
+                                         0x05, 0x00 };
+    static const byte sha256AlgoID[] = { 0x60, 0x86, 0x48, 0x01, 0x65, 0x03,
+                                         0x04, 0x02, 0x01, 0x05, 0x00 };
+    static const byte sha384AlgoID[] = { 0x60, 0x86, 0x48, 0x01, 0x65, 0x03,
+                                         0x04, 0x02, 0x02, 0x05, 0x00 };
+    static const byte sha512AlgoID[] = { 0x60, 0x86, 0x48, 0x01, 0x65, 0x03,
+                                         0x04, 0x02, 0x03, 0x05, 0x00 };
+    static const byte md5AlgoID[]    = { 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d,
+                                         0x02, 0x05, 0x05, 0x00  };
+    static const byte md2AlgoID[]    = { 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d,
+                                         0x02, 0x02, 0x05, 0x00};
+
+    /* blkTypes, no NULL tags because IV is there instead */
+    static const byte desCbcAlgoID[]  = { 0x2B, 0x0E, 0x03, 0x02, 0x07 };
+    static const byte des3CbcAlgoID[] = { 0x2A, 0x86, 0x48, 0x86, 0xF7,
+                                          0x0D, 0x03, 0x07 };
+
+    /* RSA sigTypes */
+    #ifndef NO_RSA
+        static const byte md5wRSA_AlgoID[] = { 0x2a, 0x86, 0x48, 0x86, 0xf7,
+                                            0x0d, 0x01, 0x01, 0x04, 0x05, 0x00};
+        static const byte shawRSA_AlgoID[] = { 0x2a, 0x86, 0x48, 0x86, 0xf7,
+                                            0x0d, 0x01, 0x01, 0x05, 0x05, 0x00};
+        static const byte sha256wRSA_AlgoID[] = { 0x2a, 0x86, 0x48, 0x86, 0xf7,
+                                            0x0d, 0x01, 0x01, 0x0b, 0x05, 0x00};
+        static const byte sha384wRSA_AlgoID[] = {0x2a, 0x86, 0x48, 0x86, 0xf7,
+                                            0x0d, 0x01, 0x01, 0x0c, 0x05, 0x00};
+        static const byte sha512wRSA_AlgoID[] = {0x2a, 0x86, 0x48, 0x86, 0xf7,
+                                            0x0d, 0x01, 0x01, 0x0d, 0x05, 0x00};
+    #endif /* NO_RSA */
+ 
+    /* ECDSA sigTypes */
+    #ifdef HAVE_ECC 
+        static const byte shawECDSA_AlgoID[] = { 0x2a, 0x86, 0x48, 0xCE, 0x3d,
+                                                 0x04, 0x01, 0x05, 0x00};
+        static const byte sha256wECDSA_AlgoID[] = { 0x2a, 0x86, 0x48, 0xCE,0x3d,
+                                                 0x04, 0x03, 0x02, 0x05, 0x00};
+        static const byte sha384wECDSA_AlgoID[] = { 0x2a, 0x86, 0x48, 0xCE,0x3d,
+                                                 0x04, 0x03, 0x03, 0x05, 0x00};
+        static const byte sha512wECDSA_AlgoID[] = { 0x2a, 0x86, 0x48, 0xCE,0x3d,
+                                                 0x04, 0x03, 0x04, 0x05, 0x00};
+    #endif /* HAVE_ECC */
+ 
+    /* RSA keyType */
+    #ifndef NO_RSA
+        static const byte RSA_AlgoID[] = { 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d,
+                                            0x01, 0x01, 0x01, 0x05, 0x00};
+    #endif /* NO_RSA */
+
+    #ifdef HAVE_ECC 
+        /* ECC keyType */
+        /* no tags, so set tagSz smaller later */
+        static const byte ECC_AlgoID[] = { 0x2a, 0x86, 0x48, 0xCE, 0x3d,
+                                           0x02, 0x01};
+    #endif /* HAVE_ECC */
+
+    int    algoSz = 0;
+    int    tagSz  = 2;   /* tag null and terminator */
+    word32 idSz, seqSz;
+    const  byte* algoName = 0;
+    byte ID_Length[MAX_LENGTH_SZ];
+    byte seqArray[MAX_SEQ_SZ + 1];  /* add object_id to end */
+
+    if (type == hashType) {
+        switch (algoOID) {
+        case SHAh:
+            algoSz = sizeof(shaAlgoID);
+            algoName = shaAlgoID;
+            break;
+
+        case SHA256h:
+            algoSz = sizeof(sha256AlgoID);
+            algoName = sha256AlgoID;
+            break;
+
+        case SHA384h:
+            algoSz = sizeof(sha384AlgoID);
+            algoName = sha384AlgoID;
+            break;
+
+        case SHA512h:
+            algoSz = sizeof(sha512AlgoID);
+            algoName = sha512AlgoID;
+            break;
+
+        case MD2h:
+            algoSz = sizeof(md2AlgoID);
+            algoName = md2AlgoID;
+            break;
+
+        case MD5h:
+            algoSz = sizeof(md5AlgoID);
+            algoName = md5AlgoID;
+            break;
+
+        default:
+            WOLFSSL_MSG("Unknown Hash Algo");
+            return 0;  /* UNKOWN_HASH_E; */
+        }
+    }
+    else if (type == blkType) {
+        switch (algoOID) {
+        case DESb:
+            algoSz = sizeof(desCbcAlgoID);
+            algoName = desCbcAlgoID;
+            tagSz = 0;
+            break;
+        case DES3b:
+            algoSz = sizeof(des3CbcAlgoID);
+            algoName = des3CbcAlgoID;
+            tagSz = 0;
+            break;
+        default:
+            WOLFSSL_MSG("Unknown Block Algo");
+            return 0;
+        }
+    }
+    else if (type == sigType) {    /* sigType */
+        switch (algoOID) {
+        #ifndef NO_RSA
+            case CTC_MD5wRSA:
+                algoSz = sizeof(md5wRSA_AlgoID);
+                algoName = md5wRSA_AlgoID;
+                break;
+
+            case CTC_SHAwRSA:
+                algoSz = sizeof(shawRSA_AlgoID);
+                algoName = shawRSA_AlgoID;
+                break;
+
+            case CTC_SHA256wRSA:
+                algoSz = sizeof(sha256wRSA_AlgoID);
+                algoName = sha256wRSA_AlgoID;
+                break;
+
+            case CTC_SHA384wRSA:
+                algoSz = sizeof(sha384wRSA_AlgoID);
+                algoName = sha384wRSA_AlgoID;
+                break;
+
+            case CTC_SHA512wRSA:
+                algoSz = sizeof(sha512wRSA_AlgoID);
+                algoName = sha512wRSA_AlgoID;
+                break;
+        #endif /* NO_RSA */
+        #ifdef HAVE_ECC 
+            case CTC_SHAwECDSA:
+                algoSz = sizeof(shawECDSA_AlgoID);
+                algoName = shawECDSA_AlgoID;
+                break;
+
+            case CTC_SHA256wECDSA:
+                algoSz = sizeof(sha256wECDSA_AlgoID);
+                algoName = sha256wECDSA_AlgoID;
+                break;
+
+            case CTC_SHA384wECDSA:
+                algoSz = sizeof(sha384wECDSA_AlgoID);
+                algoName = sha384wECDSA_AlgoID;
+                break;
+
+            case CTC_SHA512wECDSA:
+                algoSz = sizeof(sha512wECDSA_AlgoID);
+                algoName = sha512wECDSA_AlgoID;
+                break;
+        #endif /* HAVE_ECC */
+        default:
+            WOLFSSL_MSG("Unknown Signature Algo");
+            return 0;
+        }
+    }
+    else if (type == keyType) {    /* keyType */
+        switch (algoOID) {
+        #ifndef NO_RSA
+            case RSAk:
+                algoSz = sizeof(RSA_AlgoID);
+                algoName = RSA_AlgoID;
+                break;
+        #endif /* NO_RSA */
+        #ifdef HAVE_ECC 
+            case ECDSAk:
+                algoSz = sizeof(ECC_AlgoID);
+                algoName = ECC_AlgoID;
+                tagSz = 0;
+                break;
+        #endif /* HAVE_ECC */
+        default:
+            WOLFSSL_MSG("Unknown Key Algo");
+            return 0;
+        }
+    }
+    else {
+        WOLFSSL_MSG("Unknown Algo type");
+        return 0;
+    }
+
+    idSz  = SetLength(algoSz - tagSz, ID_Length); /* don't include tags */
+    seqSz = SetSequence(idSz + algoSz + 1 + curveSz, seqArray); 
+                 /* +1 for object id, curveID of curveSz follows for ecc */
+    seqArray[seqSz++] = ASN_OBJECT_ID;
+
+    XMEMCPY(output, seqArray, seqSz);
+    XMEMCPY(output + seqSz, ID_Length, idSz);
+    XMEMCPY(output + seqSz + idSz, algoName, algoSz);
+
+    return seqSz + idSz + algoSz;
+
+}
+
+
+word32 wc_EncodeSignature(byte* out, const byte* digest, word32 digSz,
+                          int hashOID)
+{
+    byte digArray[MAX_ENCODED_DIG_SZ];
+    byte algoArray[MAX_ALGO_SZ];
+    byte seqArray[MAX_SEQ_SZ];
+    word32 encDigSz, algoSz, seqSz;
+
+    encDigSz = SetDigest(digest, digSz, digArray);
+    algoSz   = SetAlgoID(hashOID, algoArray, hashType, 0);
+    seqSz    = SetSequence(encDigSz + algoSz, seqArray);
+
+    XMEMCPY(out, seqArray, seqSz);
+    XMEMCPY(out + seqSz, algoArray, algoSz);
+    XMEMCPY(out + seqSz + algoSz, digArray, encDigSz);
+
+    return encDigSz + algoSz + seqSz;
+}
+
+
+int wc_GetCTC_HashOID(int type)
+{
+    switch (type) {
+#ifdef WOLFSSL_MD2
+        case MD2:
+            return MD2h;
+#endif
+#ifndef NO_MD5
+        case MD5:
+            return MD5h;
+#endif
+#ifndef NO_SHA
+        case SHA:
+            return SHAh;
+#endif
+#ifndef NO_SHA256
+        case SHA256:
+            return SHA256h;
+#endif
+#ifdef WOLFSSL_SHA384
+        case SHA384:
+            return SHA384h;
+#endif
+#ifdef WOLFSSL_SHA512
+        case SHA512:
+            return SHA512h;
+#endif
+        default:
+            return 0;
+    };
+}
+
+
+/* return true (1) or false (0) for Confirmation */
+static int ConfirmSignature(const byte* buf, word32 bufSz,
+    const byte* key, word32 keySz, word32 keyOID,
+    const byte* sig, word32 sigSz, word32 sigOID,
+    void* heap)
+{
+    int  typeH = 0, digestSz = 0, ret = 0;
+#ifdef WOLFSSL_SMALL_STACK
+    byte* digest;
+#else
+    byte digest[MAX_DIGEST_SIZE];
+#endif
+
+#ifdef WOLFSSL_SMALL_STACK
+    digest = (byte*)XMALLOC(MAX_DIGEST_SIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (digest == NULL)
+        return 0; /* not confirmed */
+#endif
+
+    (void)key;
+    (void)keySz;
+    (void)sig;
+    (void)sigSz;
+    (void)heap;
+
+    switch (sigOID) {
+    #ifndef NO_MD5
+        case CTC_MD5wRSA:
+        if (wc_Md5Hash(buf, bufSz, digest) == 0) {
+            typeH    = MD5h;
+            digestSz = MD5_DIGEST_SIZE;
+        }
+        break;
+    #endif
+    #if defined(WOLFSSL_MD2)
+        case CTC_MD2wRSA:
+        if (wc_Md2Hash(buf, bufSz, digest) == 0) {
+            typeH    = MD2h;
+            digestSz = MD2_DIGEST_SIZE;
+        }
+        break;
+    #endif
+    #ifndef NO_SHA
+        case CTC_SHAwRSA:
+        case CTC_SHAwDSA:
+        case CTC_SHAwECDSA:
+        if (wc_ShaHash(buf, bufSz, digest) == 0) {    
+            typeH    = SHAh;
+            digestSz = SHA_DIGEST_SIZE;                
+        }
+        break;
+    #endif
+    #ifndef NO_SHA256
+        case CTC_SHA256wRSA:
+        case CTC_SHA256wECDSA:
+        if (wc_Sha256Hash(buf, bufSz, digest) == 0) {    
+            typeH    = SHA256h;
+            digestSz = SHA256_DIGEST_SIZE;
+        }
+        break;
+    #endif
+    #ifdef WOLFSSL_SHA512
+        case CTC_SHA512wRSA:
+        case CTC_SHA512wECDSA:
+        if (wc_Sha512Hash(buf, bufSz, digest) == 0) {    
+            typeH    = SHA512h;
+            digestSz = SHA512_DIGEST_SIZE;
+        }
+        break;
+    #endif
+    #ifdef WOLFSSL_SHA384
+        case CTC_SHA384wRSA:
+        case CTC_SHA384wECDSA:
+        if (wc_Sha384Hash(buf, bufSz, digest) == 0) {    
+            typeH    = SHA384h;
+            digestSz = SHA384_DIGEST_SIZE;
+        }            
+        break;
+    #endif
+        default:
+            WOLFSSL_MSG("Verify Signautre has unsupported type");
+    }
+    
+    if (typeH == 0) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(digest, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return 0; /* not confirmed */
+    }
+
+    switch (keyOID) {
+    #ifndef NO_RSA
+        case RSAk:
+        {
+            word32 idx = 0;
+            int    encodedSigSz, verifySz;
+            byte*  out;
+#ifdef WOLFSSL_SMALL_STACK
+            RsaKey* pubKey;
+            byte* plain;
+            byte* encodedSig;
+#else
+            RsaKey pubKey[1];
+            byte plain[MAX_ENCODED_SIG_SZ];
+            byte encodedSig[MAX_ENCODED_SIG_SZ];
+#endif
+
+#ifdef WOLFSSL_SMALL_STACK
+            pubKey = (RsaKey*)XMALLOC(sizeof(RsaKey), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+            plain = (byte*)XMALLOC(MAX_ENCODED_SIG_SZ, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+            encodedSig = (byte*)XMALLOC(MAX_ENCODED_SIG_SZ, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+            
+            if (pubKey == NULL || plain == NULL || encodedSig == NULL) {
+                WOLFSSL_MSG("Failed to allocate memory at ConfirmSignature");
+                
+                if (pubKey)
+                    XFREE(pubKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                if (plain)
+                    XFREE(plain, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                if (encodedSig)
+                    XFREE(encodedSig, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                
+                break; /* not confirmed */
+            }
+#endif
+
+            if (sigSz > MAX_ENCODED_SIG_SZ) {
+                WOLFSSL_MSG("Verify Signautre is too big");
+            }
+            else if (wc_InitRsaKey(pubKey, heap) != 0) {
+                WOLFSSL_MSG("InitRsaKey failed");
+            }
+            else if (wc_RsaPublicKeyDecode(key, &idx, pubKey, keySz) < 0) {
+                WOLFSSL_MSG("ASN Key decode error RSA");
+            }
+            else {
+                XMEMCPY(plain, sig, sigSz);
+
+                if ((verifySz = wc_RsaSSL_VerifyInline(plain, sigSz, &out,
+                                                                 pubKey)) < 0) {
+                    WOLFSSL_MSG("Rsa SSL verify error");
+                }
+                else {
+                    /* make sure we're right justified */
+                    encodedSigSz =
+                        wc_EncodeSignature(encodedSig, digest, digestSz, typeH);
+                    if (encodedSigSz != verifySz ||
+                                XMEMCMP(out, encodedSig, encodedSigSz) != 0) {
+                        WOLFSSL_MSG("Rsa SSL verify match encode error");
+                    }
+                    else
+                        ret = 1; /* match */
+
+                    #ifdef WOLFSSL_DEBUG_ENCODING
+                    {
+                        int x;
+
+                        printf("wolfssl encodedSig:\n");
+
+                        for (x = 0; x < encodedSigSz; x++) {
+                            printf("%02x ", encodedSig[x]);
+                            if ( (x % 16) == 15)
+                                printf("\n");
+                        }
+
+                        printf("\n");
+                        printf("actual digest:\n");
+
+                        for (x = 0; x < verifySz; x++) {
+                            printf("%02x ", out[x]);
+                            if ( (x % 16) == 15)
+                                printf("\n");
+                        }
+
+                        printf("\n");
+                    }
+                    #endif /* WOLFSSL_DEBUG_ENCODING */
+
+                }
+
+            }
+
+            wc_FreeRsaKey(pubKey);
+
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(pubKey,     NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            XFREE(plain,      NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            XFREE(encodedSig, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            break;
+        }
+
+    #endif /* NO_RSA */
+    #ifdef HAVE_ECC
+        case ECDSAk:
+        {
+            int verify = 0;
+#ifdef WOLFSSL_SMALL_STACK
+            ecc_key* pubKey;
+#else
+            ecc_key pubKey[1];
+#endif
+
+#ifdef WOLFSSL_SMALL_STACK
+            pubKey = (ecc_key*)XMALLOC(sizeof(ecc_key), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+            if (pubKey == NULL) {
+                WOLFSSL_MSG("Failed to allocate pubKey");
+                break; /* not confirmed */
+            }
+#endif
+
+            if (wc_ecc_init(pubKey) < 0) {
+                WOLFSSL_MSG("Failed to initialize key");
+                break; /* not confirmed */
+            }
+            if (wc_ecc_import_x963(key, keySz, pubKey) < 0) {
+                WOLFSSL_MSG("ASN Key import error ECC");
+            }
+            else {   
+                if (wc_ecc_verify_hash(sig, sigSz, digest, digestSz, &verify,
+                                                                pubKey) != 0) {
+                    WOLFSSL_MSG("ECC verify hash error");
+                }
+                else if (1 != verify) {
+                    WOLFSSL_MSG("ECC Verify didn't match");
+                } else
+                    ret = 1; /* match */
+
+            }
+            wc_ecc_free(pubKey);
+
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(pubKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            break;
+        }
+    #endif /* HAVE_ECC */
+        default:
+            WOLFSSL_MSG("Verify Key type unknown");
+    }
+    
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(digest, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+
+#ifndef IGNORE_NAME_CONSTRAINTS
+
+static int MatchBaseName(int type, const char* name, int nameSz,
+                                                   const char* base, int baseSz)
+{
+    if (base == NULL || baseSz <= 0 || name == NULL || nameSz <= 0 ||
+            name[0] == '.' || nameSz < baseSz ||
+            (type != ASN_RFC822_TYPE && type != ASN_DNS_TYPE))
+        return 0;
+
+    /* If an email type, handle special cases where the base is only
+     * a domain, or is an email address itself. */
+    if (type == ASN_RFC822_TYPE) {
+        const char* p = NULL;
+        int count = 0;
+
+        if (base[0] != '.') {
+            p = base;
+            count = 0;
+
+            /* find the '@' in the base */
+            while (*p != '@' && count < baseSz) {
+                count++;
+                p++;
+            }
+
+            /* No '@' in base, reset p to NULL */
+            if (count >= baseSz)
+                p = NULL;
+        }
+
+        if (p == NULL) {
+            /* Base isn't an email address, it is a domain name,
+             * wind the name forward one character past its '@'. */
+            p = name;
+            count = 0;
+            while (*p != '@' && count < baseSz) {
+                count++;
+                p++;
+            }
+
+            if (count < baseSz && *p == '@') {
+                name = p + 1;
+                nameSz -= count + 1;
+            }
+        }
+    }
+
+    if ((type == ASN_DNS_TYPE || type == ASN_RFC822_TYPE) && base[0] == '.') {
+        int szAdjust = nameSz - baseSz;
+        name += szAdjust;
+        nameSz -= szAdjust;
+    }
+
+    while (nameSz > 0) {
+        if (XTOLOWER((unsigned char)*name++) != 
+                                               XTOLOWER((unsigned char)*base++))
+            return 0;
+        nameSz--;
+    }
+
+    return 1;
+}
+
+
+static int ConfirmNameConstraints(Signer* signer, DecodedCert* cert)
+{
+    if (signer == NULL || cert == NULL)
+        return 0;
+
+    /* Check against the excluded list */
+    if (signer->excludedNames) {
+        Base_entry* base = signer->excludedNames;
+
+        while (base != NULL) {
+            if (base->type == ASN_DNS_TYPE) {
+                DNS_entry* name = cert->altNames;
+                while (name != NULL) {
+                    if (MatchBaseName(ASN_DNS_TYPE,
+                                          name->name, (int)XSTRLEN(name->name),
+                                          base->name, base->nameSz))
+                        return 0;
+                    name = name->next;
+                }
+            }
+            else if (base->type == ASN_RFC822_TYPE) {
+                DNS_entry* name = cert->altEmailNames;
+                while (name != NULL) {
+                    if (MatchBaseName(ASN_RFC822_TYPE,
+                                          name->name, (int)XSTRLEN(name->name),
+                                          base->name, base->nameSz))
+                        return 0;
+
+                    name = name->next;
+                }
+            }
+            else if (base->type == ASN_DIR_TYPE) {
+                if (cert->subjectRawLen == base->nameSz &&
+                    XMEMCMP(cert->subjectRaw, base->name, base->nameSz) == 0) {
+
+                    return 0;
+                }
+            }
+            base = base->next;
+        }
+    }
+
+    /* Check against the permitted list */
+    if (signer->permittedNames != NULL) {
+        int needDns = 0;
+        int matchDns = 0;
+        int needEmail = 0;
+        int matchEmail = 0;
+        int needDir = 0;
+        int matchDir = 0;
+        Base_entry* base = signer->permittedNames;
+
+        while (base != NULL) {
+            if (base->type == ASN_DNS_TYPE) {
+                DNS_entry* name = cert->altNames;
+
+                if (name != NULL)
+                    needDns = 1;
+
+                while (name != NULL) {
+                    matchDns = MatchBaseName(ASN_DNS_TYPE,
+                                          name->name, (int)XSTRLEN(name->name),
+                                          base->name, base->nameSz);
+                    name = name->next;
+                }
+            }
+            else if (base->type == ASN_RFC822_TYPE) {
+                DNS_entry* name = cert->altEmailNames;
+
+                if (name != NULL)
+                    needEmail = 1;
+
+                while (name != NULL) {
+                    matchEmail = MatchBaseName(ASN_DNS_TYPE,
+                                          name->name, (int)XSTRLEN(name->name),
+                                          base->name, base->nameSz);
+                    name = name->next;
+                }
+            }
+            else if (base->type == ASN_DIR_TYPE) {
+                needDir = 1;
+                if (cert->subjectRaw != NULL &&
+                    cert->subjectRawLen == base->nameSz &&
+                    XMEMCMP(cert->subjectRaw, base->name, base->nameSz) == 0) {
+
+                    matchDir = 1;
+                }
+            }
+            base = base->next;
+        }
+
+        if ((needDns && !matchDns) || (needEmail && !matchEmail) ||
+            (needDir && !matchDir)) {
+
+            return 0;
+        }
+    }
+
+    return 1;
+}
+
+#endif /* IGNORE_NAME_CONSTRAINTS */
+
+
+static int DecodeAltNames(byte* input, int sz, DecodedCert* cert)
+{
+    word32 idx = 0;
+    int length = 0;
+
+    WOLFSSL_ENTER("DecodeAltNames");
+
+    if (GetSequence(input, &idx, &length, sz) < 0) {
+        WOLFSSL_MSG("\tBad Sequence");
+        return ASN_PARSE_E;
+    }
+
+    cert->weOwnAltNames = 1;
+
+    while (length > 0) {
+        byte       b = input[idx++];
+
+        length--;
+
+        /* Save DNS Type names in the altNames list. */
+        /* Save Other Type names in the cert's OidMap */
+        if (b == (ASN_CONTEXT_SPECIFIC | ASN_DNS_TYPE)) {
+            DNS_entry* dnsEntry;
+            int strLen;
+            word32 lenStartIdx = idx;
+
+            if (GetLength(input, &idx, &strLen, sz) < 0) {
+                WOLFSSL_MSG("\tfail: str length");
+                return ASN_PARSE_E;
+            }
+            length -= (idx - lenStartIdx);
+
+            dnsEntry = (DNS_entry*)XMALLOC(sizeof(DNS_entry), cert->heap,
+                                        DYNAMIC_TYPE_ALTNAME);
+            if (dnsEntry == NULL) {
+                WOLFSSL_MSG("\tOut of Memory");
+                return ASN_PARSE_E;
+            }
+
+            dnsEntry->name = (char*)XMALLOC(strLen + 1, cert->heap,
+                                         DYNAMIC_TYPE_ALTNAME);
+            if (dnsEntry->name == NULL) {
+                WOLFSSL_MSG("\tOut of Memory");
+                XFREE(dnsEntry, cert->heap, DYNAMIC_TYPE_ALTNAME);
+                return ASN_PARSE_E;
+            }
+
+            XMEMCPY(dnsEntry->name, &input[idx], strLen);
+            dnsEntry->name[strLen] = '\0';
+
+            dnsEntry->next = cert->altNames;
+            cert->altNames = dnsEntry;
+
+            length -= strLen;
+            idx    += strLen;
+        }
+#ifndef IGNORE_NAME_CONSTRAINTS
+        else if (b == (ASN_CONTEXT_SPECIFIC | ASN_RFC822_TYPE)) {
+            DNS_entry* emailEntry;
+            int strLen;
+            word32 lenStartIdx = idx;
+
+            if (GetLength(input, &idx, &strLen, sz) < 0) {
+                WOLFSSL_MSG("\tfail: str length");
+                return ASN_PARSE_E;
+            }
+            length -= (idx - lenStartIdx);
+
+            emailEntry = (DNS_entry*)XMALLOC(sizeof(DNS_entry), cert->heap,
+                                        DYNAMIC_TYPE_ALTNAME);
+            if (emailEntry == NULL) {
+                WOLFSSL_MSG("\tOut of Memory");
+                return ASN_PARSE_E;
+            }
+
+            emailEntry->name = (char*)XMALLOC(strLen + 1, cert->heap,
+                                         DYNAMIC_TYPE_ALTNAME);
+            if (emailEntry->name == NULL) {
+                WOLFSSL_MSG("\tOut of Memory");
+                XFREE(emailEntry, cert->heap, DYNAMIC_TYPE_ALTNAME);
+                return ASN_PARSE_E;
+            }
+
+            XMEMCPY(emailEntry->name, &input[idx], strLen);
+            emailEntry->name[strLen] = '\0';
+
+            emailEntry->next = cert->altEmailNames;
+            cert->altEmailNames = emailEntry;
+
+            length -= strLen;
+            idx    += strLen;
+        }
+#endif /* IGNORE_NAME_CONSTRAINTS */
+#ifdef WOLFSSL_SEP
+        else if (b == (ASN_CONTEXT_SPECIFIC | ASN_CONSTRUCTED | ASN_OTHER_TYPE))
+        {
+            int strLen;
+            word32 lenStartIdx = idx;
+            word32 oid = 0;
+
+            if (GetLength(input, &idx, &strLen, sz) < 0) {
+                WOLFSSL_MSG("\tfail: other name length");
+                return ASN_PARSE_E;
+            }
+            /* Consume the rest of this sequence. */
+            length -= (strLen + idx - lenStartIdx);
+
+            if (GetObjectId(input, &idx, &oid, sz) < 0) {
+                WOLFSSL_MSG("\tbad OID");
+                return ASN_PARSE_E;
+            }
+
+            if (oid != HW_NAME_OID) {
+                WOLFSSL_MSG("\tincorrect OID");
+                return ASN_PARSE_E;
+            }
+
+            if (input[idx++] != (ASN_CONTEXT_SPECIFIC | ASN_CONSTRUCTED)) {
+                WOLFSSL_MSG("\twrong type");
+                return ASN_PARSE_E;
+            }
+
+            if (GetLength(input, &idx, &strLen, sz) < 0) {
+                WOLFSSL_MSG("\tfail: str len");
+                return ASN_PARSE_E;
+            }
+
+            if (GetSequence(input, &idx, &strLen, sz) < 0) {
+                WOLFSSL_MSG("\tBad Sequence");
+                return ASN_PARSE_E;
+            }
+
+            if (input[idx++] != ASN_OBJECT_ID) {
+                WOLFSSL_MSG("\texpected OID");
+                return ASN_PARSE_E;
+            }
+
+            if (GetLength(input, &idx, &strLen, sz) < 0) {
+                WOLFSSL_MSG("\tfailed: str len");
+                return ASN_PARSE_E;
+            }
+
+            cert->hwType = (byte*)XMALLOC(strLen, cert->heap, 0);
+            if (cert->hwType == NULL) {
+                WOLFSSL_MSG("\tOut of Memory");
+                return MEMORY_E;
+            }
+
+            XMEMCPY(cert->hwType, &input[idx], strLen);
+            cert->hwTypeSz = strLen;
+            idx += strLen;
+
+            if (input[idx++] != ASN_OCTET_STRING) {
+                WOLFSSL_MSG("\texpected Octet String");
+                return ASN_PARSE_E;
+            }
+
+            if (GetLength(input, &idx, &strLen, sz) < 0) {
+                WOLFSSL_MSG("\tfailed: str len");
+                return ASN_PARSE_E;
+            }
+
+            cert->hwSerialNum = (byte*)XMALLOC(strLen + 1, cert->heap, 0);
+            if (cert->hwSerialNum == NULL) {
+                WOLFSSL_MSG("\tOut of Memory");
+                return MEMORY_E;
+            }
+
+            XMEMCPY(cert->hwSerialNum, &input[idx], strLen);
+            cert->hwSerialNum[strLen] = '\0';
+            cert->hwSerialNumSz = strLen;
+            idx += strLen;
+        }
+#endif /* WOLFSSL_SEP */
+        else {
+            int strLen;
+            word32 lenStartIdx = idx;
+
+            WOLFSSL_MSG("\tUnsupported name type, skipping");
+
+            if (GetLength(input, &idx, &strLen, sz) < 0) {
+                WOLFSSL_MSG("\tfail: unsupported name length");
+                return ASN_PARSE_E;
+            }
+            length -= (strLen + idx - lenStartIdx);
+            idx += strLen;
+        }
+    }
+    return 0;
+}
+
+
+static int DecodeBasicCaConstraint(byte* input, int sz, DecodedCert* cert)
+{
+    word32 idx = 0;
+    int length = 0;
+
+    WOLFSSL_ENTER("DecodeBasicCaConstraint");
+    if (GetSequence(input, &idx, &length, sz) < 0) {
+        WOLFSSL_MSG("\tfail: bad SEQUENCE");
+        return ASN_PARSE_E;
+    }
+
+    if (length == 0)
+        return 0;
+
+    /* If the basic ca constraint is false, this extension may be named, but
+     * left empty. So, if the length is 0, just return. */
+
+    if (input[idx++] != ASN_BOOLEAN)
+    {
+        WOLFSSL_MSG("\tfail: constraint not BOOLEAN");
+        return ASN_PARSE_E;
+    }
+
+    if (GetLength(input, &idx, &length, sz) < 0)
+    {
+        WOLFSSL_MSG("\tfail: length");
+        return ASN_PARSE_E;
+    }
+
+    if (input[idx++])
+        cert->isCA = 1;
+
+    #ifdef OPENSSL_EXTRA
+        /* If there isn't any more data, return. */
+        if (idx >= (word32)sz)
+            return 0;
+
+        /* Anything left should be the optional pathlength */
+        if (input[idx++] != ASN_INTEGER) {
+            WOLFSSL_MSG("\tfail: pathlen not INTEGER");
+            return ASN_PARSE_E;
+        }
+
+        if (input[idx++] != 1) {
+            WOLFSSL_MSG("\tfail: pathlen too long");
+            return ASN_PARSE_E;
+        }
+
+        cert->pathLength = input[idx];
+        cert->extBasicConstPlSet = 1;
+    #endif /* OPENSSL_EXTRA */
+
+    return 0;
+}
+
+
+#define CRLDP_FULL_NAME 0
+    /* From RFC3280 SS4.2.1.14, Distribution Point Name*/
+#define GENERALNAME_URI 6
+    /* From RFC3280 SS4.2.1.7, GeneralName */
+
+static int DecodeCrlDist(byte* input, int sz, DecodedCert* cert)
+{
+    word32 idx = 0;
+    int length = 0;
+
+    WOLFSSL_ENTER("DecodeCrlDist");
+
+    /* Unwrap the list of Distribution Points*/
+    if (GetSequence(input, &idx, &length, sz) < 0)
+        return ASN_PARSE_E;
+
+    /* Unwrap a single Distribution Point */
+    if (GetSequence(input, &idx, &length, sz) < 0)
+        return ASN_PARSE_E;
+
+    /* The Distribution Point has three explicit optional members
+     *  First check for a DistributionPointName
+     */
+    if (input[idx] == (ASN_CONSTRUCTED | ASN_CONTEXT_SPECIFIC | 0))
+    {
+        idx++;
+        if (GetLength(input, &idx, &length, sz) < 0)
+            return ASN_PARSE_E;
+
+        if (input[idx] == 
+                    (ASN_CONTEXT_SPECIFIC | ASN_CONSTRUCTED | CRLDP_FULL_NAME))
+        {
+            idx++;
+            if (GetLength(input, &idx, &length, sz) < 0)
+                return ASN_PARSE_E;
+
+            if (input[idx] == (ASN_CONTEXT_SPECIFIC | GENERALNAME_URI))
+            {
+                idx++;
+                if (GetLength(input, &idx, &length, sz) < 0)
+                    return ASN_PARSE_E;
+
+                cert->extCrlInfoSz = length;
+                cert->extCrlInfo = input + idx;
+                idx += length;
+            }
+            else
+                /* This isn't a URI, skip it. */
+                idx += length;
+        }
+        else
+            /* This isn't a FULLNAME, skip it. */
+            idx += length;
+    }
+
+    /* Check for reasonFlags */
+    if (idx < (word32)sz &&
+        input[idx] == (ASN_CONSTRUCTED | ASN_CONTEXT_SPECIFIC | 1))
+    {
+        idx++;
+        if (GetLength(input, &idx, &length, sz) < 0)
+            return ASN_PARSE_E;
+        idx += length;
+    }
+
+    /* Check for cRLIssuer */
+    if (idx < (word32)sz &&
+        input[idx] == (ASN_CONSTRUCTED | ASN_CONTEXT_SPECIFIC | 2))
+    {
+        idx++;
+        if (GetLength(input, &idx, &length, sz) < 0)
+            return ASN_PARSE_E;
+        idx += length;
+    }
+
+    if (idx < (word32)sz)
+    {
+        WOLFSSL_MSG("\tThere are more CRL Distribution Point records, "
+                   "but we only use the first one.");
+    }
+
+    return 0;
+}
+
+
+static int DecodeAuthInfo(byte* input, int sz, DecodedCert* cert)
+/*
+ *  Read the first of the Authority Information Access records. If there are
+ *  any issues, return without saving the record.
+ */
+{
+    word32 idx = 0;
+    int length = 0;
+    byte b;
+    word32 oid;
+
+    WOLFSSL_ENTER("DecodeAuthInfo");
+
+    /* Unwrap the list of AIAs */
+    if (GetSequence(input, &idx, &length, sz) < 0)
+        return ASN_PARSE_E;
+
+    while (idx < (word32)sz) {
+        /* Unwrap a single AIA */
+        if (GetSequence(input, &idx, &length, sz) < 0)
+            return ASN_PARSE_E;
+
+        oid = 0;
+        if (GetObjectId(input, &idx, &oid, sz) < 0)
+            return ASN_PARSE_E;
+
+        /* Only supporting URIs right now. */
+        b = input[idx++];
+        if (GetLength(input, &idx, &length, sz) < 0)
+            return ASN_PARSE_E;
+
+        if (b == (ASN_CONTEXT_SPECIFIC | GENERALNAME_URI) &&
+            oid == AIA_OCSP_OID)
+        {
+            cert->extAuthInfoSz = length;
+            cert->extAuthInfo = input + idx;
+            break;
+        }
+        idx += length;
+    }
+
+    return 0;
+}
+
+
+static int DecodeAuthKeyId(byte* input, int sz, DecodedCert* cert)
+{
+    word32 idx = 0;
+    int length = 0, ret = 0;
+
+    WOLFSSL_ENTER("DecodeAuthKeyId");
+
+    if (GetSequence(input, &idx, &length, sz) < 0) {
+        WOLFSSL_MSG("\tfail: should be a SEQUENCE\n");
+        return ASN_PARSE_E;
+    }
+
+    if (input[idx++] != (ASN_CONTEXT_SPECIFIC | 0)) {
+        WOLFSSL_MSG("\tinfo: OPTIONAL item 0, not available\n");
+        return 0;
+    }
+
+    if (GetLength(input, &idx, &length, sz) < 0) {
+        WOLFSSL_MSG("\tfail: extension data length");
+        return ASN_PARSE_E;
+    }
+
+    #ifdef OPENSSL_EXTRA
+        cert->extAuthKeyIdSrc = &input[idx];
+        cert->extAuthKeyIdSz = length;
+    #endif /* OPENSSL_EXTRA */
+
+    if (length == KEYID_SIZE) {
+        XMEMCPY(cert->extAuthKeyId, input + idx, length);
+    }
+    else {
+    #ifdef NO_SHA
+        ret = wc_Sha256Hash(input + idx, length, cert->extAuthKeyId);
+    #else
+        ret = wc_ShaHash(input + idx, length, cert->extAuthKeyId);
+    #endif
+    }
+
+    return ret;
+}
+
+
+static int DecodeSubjKeyId(byte* input, int sz, DecodedCert* cert)
+{
+    word32 idx = 0;
+    int length = 0, ret = 0;
+
+    WOLFSSL_ENTER("DecodeSubjKeyId");
+
+    if (input[idx++] != ASN_OCTET_STRING) {
+        WOLFSSL_MSG("\tfail: should be an OCTET STRING");
+        return ASN_PARSE_E;
+    }
+
+    if (GetLength(input, &idx, &length, sz) < 0) {
+        WOLFSSL_MSG("\tfail: extension data length");
+        return ASN_PARSE_E;
+    }
+
+    #ifdef OPENSSL_EXTRA
+        cert->extSubjKeyIdSrc = &input[idx];
+        cert->extSubjKeyIdSz = length;
+    #endif /* OPENSSL_EXTRA */
+
+    if (length == SIGNER_DIGEST_SIZE) {
+        XMEMCPY(cert->extSubjKeyId, input + idx, length);
+    }
+    else {
+    #ifdef NO_SHA
+        ret = wc_Sha256Hash(input + idx, length, cert->extSubjKeyId);
+    #else
+        ret = wc_ShaHash(input + idx, length, cert->extSubjKeyId);
+    #endif
+    }
+
+    return ret;
+}
+
+
+static int DecodeKeyUsage(byte* input, int sz, DecodedCert* cert)
+{
+    word32 idx = 0;
+    int length;
+    byte unusedBits;
+    WOLFSSL_ENTER("DecodeKeyUsage");
+
+    if (input[idx++] != ASN_BIT_STRING) {
+        WOLFSSL_MSG("\tfail: key usage expected bit string");
+        return ASN_PARSE_E;
+    }
+
+    if (GetLength(input, &idx, &length, sz) < 0) {
+        WOLFSSL_MSG("\tfail: key usage bad length");
+        return ASN_PARSE_E;
+    }
+
+    unusedBits = input[idx++];
+    length--;
+
+    if (length == 2) {
+        cert->extKeyUsage = (word16)((input[idx] << 8) | input[idx+1]);
+        cert->extKeyUsage >>= unusedBits;
+    }
+    else if (length == 1)
+        cert->extKeyUsage = (word16)(input[idx] << 1);
+
+    return 0;
+}
+
+
+static int DecodeExtKeyUsage(byte* input, int sz, DecodedCert* cert)
+{
+    word32 idx = 0, oid;
+    int length;
+
+    WOLFSSL_ENTER("DecodeExtKeyUsage");
+
+    if (GetSequence(input, &idx, &length, sz) < 0) {
+        WOLFSSL_MSG("\tfail: should be a SEQUENCE");
+        return ASN_PARSE_E;
+    }
+
+    #ifdef OPENSSL_EXTRA
+        cert->extExtKeyUsageSrc = input + idx;
+        cert->extExtKeyUsageSz = length;
+    #endif
+
+    while (idx < (word32)sz) {
+        if (GetObjectId(input, &idx, &oid, sz) < 0)
+            return ASN_PARSE_E;
+
+        switch (oid) {
+            case EKU_ANY_OID:
+                cert->extExtKeyUsage |= EXTKEYUSE_ANY;
+                break;
+            case EKU_SERVER_AUTH_OID:
+                cert->extExtKeyUsage |= EXTKEYUSE_SERVER_AUTH;
+                break;
+            case EKU_CLIENT_AUTH_OID:
+                cert->extExtKeyUsage |= EXTKEYUSE_CLIENT_AUTH;
+                break;
+            case EKU_OCSP_SIGN_OID:
+                cert->extExtKeyUsage |= EXTKEYUSE_OCSP_SIGN;
+                break;
+        }
+
+        #ifdef OPENSSL_EXTRA
+            cert->extExtKeyUsageCount++;
+        #endif
+    }
+
+    return 0;
+}
+
+
+#ifndef IGNORE_NAME_CONSTRAINTS
+static int DecodeSubtree(byte* input, int sz, Base_entry** head, void* heap)
+{
+    word32 idx = 0;
+
+    (void)heap;
+
+    while (idx < (word32)sz) {
+        int seqLength, strLength;
+        word32 nameIdx;
+        byte b;
+
+        if (GetSequence(input, &idx, &seqLength, sz) < 0) {
+            WOLFSSL_MSG("\tfail: should be a SEQUENCE");
+            return ASN_PARSE_E;
+        }
+
+        nameIdx = idx;
+        b = input[nameIdx++];
+        if (GetLength(input, &nameIdx, &strLength, sz) <= 0) {
+            WOLFSSL_MSG("\tinvalid length");
+            return ASN_PARSE_E;
+        }
+
+        if (b == (ASN_CONTEXT_SPECIFIC | ASN_DNS_TYPE) ||
+            b == (ASN_CONTEXT_SPECIFIC | ASN_RFC822_TYPE) ||
+            b == (ASN_CONTEXT_SPECIFIC | ASN_CONSTRUCTED | ASN_DIR_TYPE)) {
+
+            Base_entry* entry = (Base_entry*)XMALLOC(sizeof(Base_entry),
+                                                    heap, DYNAMIC_TYPE_ALTNAME);
+
+            if (entry == NULL) {
+                WOLFSSL_MSG("allocate error");
+                return MEMORY_E;
+            }
+
+            entry->name = (char*)XMALLOC(strLength, heap, DYNAMIC_TYPE_ALTNAME);
+            if (entry->name == NULL) {
+                WOLFSSL_MSG("allocate error");
+                return MEMORY_E;
+            }
+
+            XMEMCPY(entry->name, &input[nameIdx], strLength);
+            entry->nameSz = strLength;
+            entry->type = b & 0x0F;
+
+            entry->next = *head;
+            *head = entry;
+        }
+
+        idx += seqLength;
+    }
+
+    return 0;
+}
+
+
+static int DecodeNameConstraints(byte* input, int sz, DecodedCert* cert)
+{
+    word32 idx = 0;
+    int length = 0;
+
+    WOLFSSL_ENTER("DecodeNameConstraints");
+
+    if (GetSequence(input, &idx, &length, sz) < 0) {
+        WOLFSSL_MSG("\tfail: should be a SEQUENCE");
+        return ASN_PARSE_E;
+    }
+
+    while (idx < (word32)sz) {
+        byte b = input[idx++];
+        Base_entry** subtree = NULL;
+
+        if (GetLength(input, &idx, &length, sz) <= 0) {
+            WOLFSSL_MSG("\tinvalid length");
+            return ASN_PARSE_E;
+        }
+
+        if (b == (ASN_CONTEXT_SPECIFIC | ASN_CONSTRUCTED | 0))
+            subtree = &cert->permittedNames;
+        else if (b == (ASN_CONTEXT_SPECIFIC | ASN_CONSTRUCTED | 1))
+            subtree = &cert->excludedNames;
+        else {
+            WOLFSSL_MSG("\tinvalid subtree");
+            return ASN_PARSE_E;
+        }
+
+        DecodeSubtree(input + idx, length, subtree, cert->heap);
+
+        idx += length;
+    }
+
+    return 0;
+}
+#endif /* IGNORE_NAME_CONSTRAINTS */
+
+
+#ifdef WOLFSSL_SEP
+    static int DecodeCertPolicy(byte* input, int sz, DecodedCert* cert)
+    {
+        word32 idx = 0;
+        int length = 0;
+
+        WOLFSSL_ENTER("DecodeCertPolicy");
+
+        /* Unwrap certificatePolicies */
+        if (GetSequence(input, &idx, &length, sz) < 0) {
+            WOLFSSL_MSG("\tdeviceType isn't OID");
+            return ASN_PARSE_E;
+        }
+
+        if (GetSequence(input, &idx, &length, sz) < 0) {
+            WOLFSSL_MSG("\tdeviceType isn't OID");
+            return ASN_PARSE_E;
+        }
+
+        if (input[idx++] != ASN_OBJECT_ID) {
+            WOLFSSL_MSG("\tdeviceType isn't OID");
+            return ASN_PARSE_E;
+        }
+
+        if (GetLength(input, &idx, &length, sz) < 0) {
+            WOLFSSL_MSG("\tCouldn't read length of deviceType");
+            return ASN_PARSE_E;
+        }
+
+        if (length > 0) {
+            cert->deviceType = (byte*)XMALLOC(length, cert->heap, 0);
+            if (cert->deviceType == NULL) {
+                WOLFSSL_MSG("\tCouldn't alloc memory for deviceType");
+                return MEMORY_E;
+            }
+            cert->deviceTypeSz = length;
+            XMEMCPY(cert->deviceType, input + idx, length);
+        }
+
+        WOLFSSL_LEAVE("DecodeCertPolicy", 0);
+        return 0;
+    }
+#endif /* WOLFSSL_SEP */
+
+
+static int DecodeCertExtensions(DecodedCert* cert)
+/*
+ *  Processing the Certificate Extensions. This does not modify the current
+ *  index. It is works starting with the recorded extensions pointer.
+ */
+{
+    word32 idx = 0;
+    int sz = cert->extensionsSz;
+    byte* input = cert->extensions;
+    int length;
+    word32 oid;
+    byte critical = 0;
+    byte criticalFail = 0;
+
+    WOLFSSL_ENTER("DecodeCertExtensions");
+
+    if (input == NULL || sz == 0)
+        return BAD_FUNC_ARG;
+
+    if (input[idx++] != ASN_EXTENSIONS)
+        return ASN_PARSE_E;
+
+    if (GetLength(input, &idx, &length, sz) < 0)
+        return ASN_PARSE_E;
+
+    if (GetSequence(input, &idx, &length, sz) < 0)
+        return ASN_PARSE_E;
+    
+    while (idx < (word32)sz) {
+        if (GetSequence(input, &idx, &length, sz) < 0) {
+            WOLFSSL_MSG("\tfail: should be a SEQUENCE");
+            return ASN_PARSE_E;
+        }
+
+        oid = 0;
+        if (GetObjectId(input, &idx, &oid, sz) < 0) {
+            WOLFSSL_MSG("\tfail: OBJECT ID");
+            return ASN_PARSE_E;
+        }
+
+        /* check for critical flag */
+        critical = 0;
+        if (input[idx] == ASN_BOOLEAN) {
+            int boolLength = 0;
+            idx++;
+            if (GetLength(input, &idx, &boolLength, sz) < 0) {
+                WOLFSSL_MSG("\tfail: critical boolean length");
+                return ASN_PARSE_E;
+            }
+            if (input[idx++])
+                critical = 1;
+        }
+
+        /* process the extension based on the OID */
+        if (input[idx++] != ASN_OCTET_STRING) {
+            WOLFSSL_MSG("\tfail: should be an OCTET STRING");
+            return ASN_PARSE_E;
+        }
+
+        if (GetLength(input, &idx, &length, sz) < 0) {
+            WOLFSSL_MSG("\tfail: extension data length");
+            return ASN_PARSE_E;
+        }
+
+        switch (oid) {
+            case BASIC_CA_OID:
+                #ifdef OPENSSL_EXTRA
+                    cert->extBasicConstSet = 1;
+                    cert->extBasicConstCrit = critical;
+                #endif
+                if (DecodeBasicCaConstraint(&input[idx], length, cert) < 0)
+                    return ASN_PARSE_E;
+                break;
+
+            case CRL_DIST_OID:
+                if (DecodeCrlDist(&input[idx], length, cert) < 0)
+                    return ASN_PARSE_E;
+                break;
+
+            case AUTH_INFO_OID:
+                if (DecodeAuthInfo(&input[idx], length, cert) < 0)
+                    return ASN_PARSE_E;
+                break;
+
+            case ALT_NAMES_OID:
+                #ifdef OPENSSL_EXTRA
+                    cert->extSubjAltNameSet = 1;
+                    cert->extSubjAltNameCrit = critical;
+                #endif
+                if (DecodeAltNames(&input[idx], length, cert) < 0)
+                    return ASN_PARSE_E;
+                break;
+
+            case AUTH_KEY_OID:
+                cert->extAuthKeyIdSet = 1;
+                #ifdef OPENSSL_EXTRA
+                    cert->extAuthKeyIdCrit = critical;
+                #endif
+                if (DecodeAuthKeyId(&input[idx], length, cert) < 0)
+                    return ASN_PARSE_E;
+                break;
+
+            case SUBJ_KEY_OID:
+                cert->extSubjKeyIdSet = 1;
+                #ifdef OPENSSL_EXTRA
+                    cert->extSubjKeyIdCrit = critical;
+                #endif
+                if (DecodeSubjKeyId(&input[idx], length, cert) < 0)
+                    return ASN_PARSE_E;
+                break;
+
+            case CERT_POLICY_OID:
+                WOLFSSL_MSG("Certificate Policy extension not supported yet.");
+                #ifdef WOLFSSL_SEP
+                    #ifdef OPENSSL_EXTRA
+                        cert->extCertPolicySet = 1;
+                        cert->extCertPolicyCrit = critical;
+                    #endif
+                    if (DecodeCertPolicy(&input[idx], length, cert) < 0)
+                        return ASN_PARSE_E;
+                #endif
+                break;
+
+            case KEY_USAGE_OID:
+                cert->extKeyUsageSet = 1;
+                #ifdef OPENSSL_EXTRA
+                    cert->extKeyUsageCrit = critical;
+                #endif
+                if (DecodeKeyUsage(&input[idx], length, cert) < 0)
+                    return ASN_PARSE_E;
+                break;
+
+            case EXT_KEY_USAGE_OID:
+                cert->extExtKeyUsageSet = 1;
+                #ifdef OPENSSL_EXTRA
+                    cert->extExtKeyUsageCrit = critical;
+                #endif
+                if (DecodeExtKeyUsage(&input[idx], length, cert) < 0)
+                    return ASN_PARSE_E;
+                break;
+
+            #ifndef IGNORE_NAME_CONSTRAINTS
+            case NAME_CONS_OID:
+                cert->extNameConstraintSet = 1;
+                #ifdef OPENSSL_EXTRA
+                    cert->extNameConstraintCrit = critical;
+                #endif
+                if (DecodeNameConstraints(&input[idx], length, cert) < 0)
+                    return ASN_PARSE_E;
+                break;
+            #endif /* IGNORE_NAME_CONSTRAINTS */
+
+            case INHIBIT_ANY_OID:
+                WOLFSSL_MSG("Inhibit anyPolicy extension not supported yet.");
+                break;
+
+            default:
+                /* While it is a failure to not support critical extensions,
+                 * still parse the certificate ignoring the unsupported
+                 * extention to allow caller to accept it with the verify
+                 * callback. */
+                if (critical)
+                    criticalFail = 1;
+                break;
+        }
+        idx += length;
+    }
+
+    return criticalFail ? ASN_CRIT_EXT_E : 0;
+}
+
+
+int ParseCert(DecodedCert* cert, int type, int verify, void* cm)
+{
+    int   ret;
+    char* ptr;
+
+    ret = ParseCertRelative(cert, type, verify, cm);
+    if (ret < 0)
+        return ret;
+
+    if (cert->subjectCNLen > 0) {
+        ptr = (char*) XMALLOC(cert->subjectCNLen + 1, cert->heap,
+                              DYNAMIC_TYPE_SUBJECT_CN);
+        if (ptr == NULL)
+            return MEMORY_E;
+        XMEMCPY(ptr, cert->subjectCN, cert->subjectCNLen);
+        ptr[cert->subjectCNLen] = '\0';
+        cert->subjectCN = ptr;
+        cert->subjectCNStored = 1;
+    }
+
+    if (cert->keyOID == RSAk &&
+                          cert->publicKey != NULL  && cert->pubKeySize > 0) {
+        ptr = (char*) XMALLOC(cert->pubKeySize, cert->heap,
+                              DYNAMIC_TYPE_PUBLIC_KEY);
+        if (ptr == NULL)
+            return MEMORY_E;
+        XMEMCPY(ptr, cert->publicKey, cert->pubKeySize);
+        cert->publicKey = (byte *)ptr;
+        cert->pubKeyStored = 1;
+    }
+
+    return ret;
+}
+
+
+/* from SSL proper, for locking can't do find here anymore */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+    WOLFSSL_LOCAL Signer* GetCA(void* signers, byte* hash);
+    #ifndef NO_SKID
+        WOLFSSL_LOCAL Signer* GetCAByName(void* signers, byte* hash);
+    #endif
+#ifdef __cplusplus
+    } 
+#endif
+
+
+int ParseCertRelative(DecodedCert* cert, int type, int verify, void* cm)
+{
+    word32 confirmOID;
+    int    ret;
+    int    badDate     = 0;
+    int    criticalExt = 0;
+
+    if ((ret = DecodeToKey(cert, verify)) < 0) {
+        if (ret == ASN_BEFORE_DATE_E || ret == ASN_AFTER_DATE_E)
+            badDate = ret;
+        else
+            return ret;
+    }
+
+    WOLFSSL_MSG("Parsed Past Key");
+
+    if (cert->srcIdx < cert->sigIndex) {
+        #ifndef ALLOW_V1_EXTENSIONS
+            if (cert->version < 2) {
+                WOLFSSL_MSG("    v1 and v2 certs not allowed extensions");
+                return ASN_VERSION_E;
+            }
+        #endif
+        /* save extensions */
+        cert->extensions    = &cert->source[cert->srcIdx];
+        cert->extensionsSz  =  cert->sigIndex - cert->srcIdx;
+        cert->extensionsIdx = cert->srcIdx;   /* for potential later use */
+
+        if ((ret = DecodeCertExtensions(cert)) < 0) {
+            if (ret == ASN_CRIT_EXT_E)
+                criticalExt = ret;
+            else
+                return ret;
+        }
+
+        /* advance past extensions */
+        cert->srcIdx =  cert->sigIndex;
+    }
+
+    if ((ret = GetAlgoId(cert->source, &cert->srcIdx, &confirmOID,
+                         cert->maxIdx)) < 0)
+        return ret;
+
+    if ((ret = GetSignature(cert)) < 0)
+        return ret;
+
+    if (confirmOID != cert->signatureOID)
+        return ASN_SIG_OID_E;
+
+    #ifndef NO_SKID
+        if (cert->extSubjKeyIdSet == 0
+                          && cert->publicKey != NULL && cert->pubKeySize > 0) {
+        #ifdef NO_SHA
+            ret = wc_Sha256Hash(cert->publicKey, cert->pubKeySize,
+                                                            cert->extSubjKeyId);
+        #else
+            ret = wc_ShaHash(cert->publicKey, cert->pubKeySize,
+                                                            cert->extSubjKeyId);
+        #endif
+            if (ret != 0)
+                return ret;
+        }
+    #endif
+
+    if (verify && type != CA_TYPE) {
+        Signer* ca = NULL;
+        #ifndef NO_SKID
+            if (cert->extAuthKeyIdSet)
+                ca = GetCA(cm, cert->extAuthKeyId);
+            if (ca == NULL)
+                ca = GetCAByName(cm, cert->issuerHash);
+        #else /* NO_SKID */
+            ca = GetCA(cm, cert->issuerHash);
+        #endif /* NO SKID */
+        WOLFSSL_MSG("About to verify certificate signature");
+ 
+        if (ca) {
+#ifdef HAVE_OCSP
+            /* Need the ca's public key hash for OCSP */
+    #ifdef NO_SHA
+            ret = wc_Sha256Hash(ca->publicKey, ca->pubKeySize,
+                                cert->issuerKeyHash);
+    #else /* NO_SHA */
+            ret = wc_ShaHash(ca->publicKey, ca->pubKeySize,
+                                cert->issuerKeyHash);
+    #endif /* NO_SHA */
+            if (ret != 0)
+                return ret;
+#endif /* HAVE_OCSP */
+            /* try to confirm/verify signature */
+            if (!ConfirmSignature(cert->source + cert->certBegin,
+                        cert->sigIndex - cert->certBegin,
+                    ca->publicKey, ca->pubKeySize, ca->keyOID,
+                    cert->signature, cert->sigLength, cert->signatureOID,
+                    cert->heap)) {
+                WOLFSSL_MSG("Confirm signature failed");
+                return ASN_SIG_CONFIRM_E;
+            }
+#ifndef IGNORE_NAME_CONSTRAINTS
+            /* check that this cert's name is permitted by the signer's
+             * name constraints */
+            if (!ConfirmNameConstraints(ca, cert)) {
+                WOLFSSL_MSG("Confirm name constraint failed");
+                return ASN_NAME_INVALID_E;
+            }
+#endif /* IGNORE_NAME_CONSTRAINTS */
+        }
+        else {
+            /* no signer */
+            WOLFSSL_MSG("No CA signer to verify with");
+            return ASN_NO_SIGNER_E;
+        }
+    }
+
+    if (badDate != 0)
+        return badDate;
+
+    if (criticalExt != 0)
+        return criticalExt;
+
+    return 0;
+}
+
+
+/* Create and init an new signer */
+Signer* MakeSigner(void* heap)
+{
+    Signer* signer = (Signer*) XMALLOC(sizeof(Signer), heap,
+                                       DYNAMIC_TYPE_SIGNER);
+    if (signer) {
+        signer->pubKeySize = 0;
+        signer->keyOID     = 0;
+        signer->publicKey  = NULL;
+        signer->nameLen    = 0;
+        signer->name       = NULL;
+        #ifndef IGNORE_NAME_CONSTRAINTS
+            signer->permittedNames = NULL;
+            signer->excludedNames = NULL;
+        #endif /* IGNORE_NAME_CONSTRAINTS */
+        signer->next       = NULL;
+    }
+    (void)heap;
+
+    return signer;
+}
+
+
+/* Free an individual signer */
+void FreeSigner(Signer* signer, void* heap)
+{
+    XFREE(signer->name, heap, DYNAMIC_TYPE_SUBJECT_CN);
+    XFREE(signer->publicKey, heap, DYNAMIC_TYPE_PUBLIC_KEY);
+    #ifndef IGNORE_NAME_CONSTRAINTS
+        if (signer->permittedNames)
+            FreeNameSubtrees(signer->permittedNames, heap);
+        if (signer->excludedNames)
+            FreeNameSubtrees(signer->excludedNames, heap);
+    #endif
+    XFREE(signer, heap, DYNAMIC_TYPE_SIGNER);
+
+    (void)heap;
+}
+
+
+/* Free the whole singer table with number of rows */
+void FreeSignerTable(Signer** table, int rows, void* heap)
+{
+    int i;
+
+    for (i = 0; i < rows; i++) {
+        Signer* signer = table[i];
+        while (signer) {
+            Signer* next = signer->next;
+            FreeSigner(signer, heap);
+            signer = next;
+        }
+        table[i] = NULL;
+    }
+}
+
+
+WOLFSSL_LOCAL int SetMyVersion(word32 version, byte* output, int header)
+{
+    int i = 0;
+
+    if (header) {
+        output[i++] = ASN_CONTEXT_SPECIFIC | ASN_CONSTRUCTED;
+        output[i++] = ASN_BIT_STRING;
+    }
+    output[i++] = ASN_INTEGER;
+    output[i++] = 0x01;
+    output[i++] = (byte)version;
+
+    return i;
+}
+
+
+WOLFSSL_LOCAL int SetSerialNumber(const byte* sn, word32 snSz, byte* output)
+{
+    int result = 0;
+
+    WOLFSSL_ENTER("SetSerialNumber");
+
+    if (snSz <= EXTERNAL_SERIAL_SIZE) {
+        output[0] = ASN_INTEGER;
+        /* The serial number is always positive. When encoding the
+         * INTEGER, if the MSB is 1, add a padding zero to keep the
+         * number positive. */
+        if (sn[0] & 0x80) {
+            output[1] = (byte)snSz + 1;
+            output[2] = 0;
+            XMEMCPY(&output[3], sn, snSz);
+            result = snSz + 3;
+        }
+        else {
+            output[1] = (byte)snSz;
+            XMEMCPY(&output[2], sn, snSz);
+            result = snSz + 2;
+        }
+    }
+    return result;
+}
+
+
+
+
+#if defined(WOLFSSL_KEY_GEN) || defined(WOLFSSL_CERT_GEN)
+
+/* convert der buffer to pem into output, can't do inplace, der and output
+   need to be different */
+int wc_DerToPem(const byte* der, word32 derSz, byte* output, word32 outSz,
+             int type)
+{
+#ifdef WOLFSSL_SMALL_STACK
+    char* header = NULL;
+    char* footer = NULL;
+#else
+    char header[80];
+    char footer[80];
+#endif
+
+    int headerLen = 80;
+    int footerLen = 80;
+    int i;
+    int err;
+    int outLen;   /* return length or error */
+
+    if (der == output)      /* no in place conversion */
+        return BAD_FUNC_ARG;
+
+#ifdef WOLFSSL_SMALL_STACK
+    header = (char*)XMALLOC(headerLen, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (header == NULL)
+        return MEMORY_E;
+    
+    footer = (char*)XMALLOC(footerLen, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (footer == NULL) {
+        XFREE(header, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        return MEMORY_E;
+    }
+#endif
+
+    if (type == CERT_TYPE) {
+        XSTRNCPY(header, "-----BEGIN CERTIFICATE-----\n", headerLen);
+        XSTRNCPY(footer, "-----END CERTIFICATE-----\n",   footerLen);
+    }
+    else if (type == PRIVATEKEY_TYPE) {
+        XSTRNCPY(header, "-----BEGIN RSA PRIVATE KEY-----\n", headerLen);
+        XSTRNCPY(footer, "-----END RSA PRIVATE KEY-----\n",   footerLen);
+    }
+    #ifdef HAVE_ECC
+    else if (type == ECC_PRIVATEKEY_TYPE) {
+        XSTRNCPY(header, "-----BEGIN EC PRIVATE KEY-----\n", headerLen);
+        XSTRNCPY(footer, "-----END EC PRIVATE KEY-----\n",   footerLen);
+    }
+    #endif
+    #ifdef WOLFSSL_CERT_REQ
+    else if (type == CERTREQ_TYPE)
+    {
+        XSTRNCPY(header,
+                       "-----BEGIN CERTIFICATE REQUEST-----\n", headerLen);
+        XSTRNCPY(footer, "-----END CERTIFICATE REQUEST-----\n", footerLen);
+    }
+    #endif
+    else {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(header, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(footer, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return BAD_FUNC_ARG;
+    }
+
+    headerLen = (int)XSTRLEN(header);
+    footerLen = (int)XSTRLEN(footer);
+
+    if (!der || !output) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(header, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(footer, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return BAD_FUNC_ARG;
+    }
+
+    /* don't even try if outSz too short */
+    if (outSz < headerLen + footerLen + derSz) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(header, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(footer, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return BAD_FUNC_ARG;
+    }
+
+    /* header */
+    XMEMCPY(output, header, headerLen);
+    i = headerLen;
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(header, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    /* body */
+    outLen = outSz - (headerLen + footerLen);  /* input to Base64_Encode */
+    if ( (err = Base64_Encode(der, derSz, output + i, (word32*)&outLen)) < 0) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(footer, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return err;
+    }
+    i += outLen;
+
+    /* footer */
+    if ( (i + footerLen) > (int)outSz) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(footer, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return BAD_FUNC_ARG;
+    }
+    XMEMCPY(output + i, footer, footerLen);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(footer, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return outLen + headerLen + footerLen;
+}
+
+
+#endif /* WOLFSSL_KEY_GEN || WOLFSSL_CERT_GEN */
+
+
+#if defined(WOLFSSL_KEY_GEN) && !defined(NO_RSA)
+
+
+static mp_int* GetRsaInt(RsaKey* key, int idx)
+{
+    if (idx == 0)
+        return &key->n;
+    if (idx == 1)
+        return &key->e;
+    if (idx == 2)
+        return &key->d;
+    if (idx == 3)
+        return &key->p;
+    if (idx == 4)
+        return &key->q;
+    if (idx == 5)
+        return &key->dP;
+    if (idx == 6)
+        return &key->dQ;
+    if (idx == 7)
+        return &key->u;
+
+    return NULL;
+}
+
+
+/* Release Tmp RSA resources */
+static INLINE void FreeTmpRsas(byte** tmps, void* heap)
+{
+    int i;
+
+    (void)heap;
+
+    for (i = 0; i < RSA_INTS; i++) 
+        XFREE(tmps[i], heap, DYNAMIC_TYPE_RSA);
+}
+
+
+/* Convert RsaKey key to DER format, write to output (inLen), return bytes
+   written */
+int wc_RsaKeyToDer(RsaKey* key, byte* output, word32 inLen)
+{
+    word32 seqSz, verSz, rawLen, intTotalLen = 0;
+    word32 sizes[RSA_INTS];
+    int    i, j, outLen, ret = 0;
+
+    byte  seq[MAX_SEQ_SZ];
+    byte  ver[MAX_VERSION_SZ];
+    byte* tmps[RSA_INTS];
+
+    if (!key || !output)
+        return BAD_FUNC_ARG;
+
+    if (key->type != RSA_PRIVATE)
+        return BAD_FUNC_ARG;
+
+    for (i = 0; i < RSA_INTS; i++)
+        tmps[i] = NULL;
+
+    /* write all big ints from key to DER tmps */
+    for (i = 0; i < RSA_INTS; i++) {
+        mp_int* keyInt = GetRsaInt(key, i);
+        rawLen = mp_unsigned_bin_size(keyInt);
+        tmps[i] = (byte*)XMALLOC(rawLen + MAX_SEQ_SZ, key->heap,
+                                 DYNAMIC_TYPE_RSA);
+        if (tmps[i] == NULL) {
+            ret = MEMORY_E;
+            break;
+        }
+
+        tmps[i][0] = ASN_INTEGER;
+        sizes[i] = SetLength(rawLen, tmps[i] + 1) + 1;  /* int tag */
+
+        if (sizes[i] <= MAX_SEQ_SZ) {
+            int err = mp_to_unsigned_bin(keyInt, tmps[i] + sizes[i]);
+            if (err == MP_OKAY) {
+                sizes[i] += rawLen;
+                intTotalLen += sizes[i];
+            }
+            else {
+                ret = err;
+                break;
+            }
+        }
+        else {
+            ret = ASN_INPUT_E;
+            break;
+        }
+    }
+
+    if (ret != 0) {
+        FreeTmpRsas(tmps, key->heap);
+        return ret;
+    }
+
+    /* make headers */
+    verSz = SetMyVersion(0, ver, FALSE);
+    seqSz = SetSequence(verSz + intTotalLen, seq);
+
+    outLen = seqSz + verSz + intTotalLen;
+    if (outLen > (int)inLen)
+        return BAD_FUNC_ARG;
+
+    /* write to output */
+    XMEMCPY(output, seq, seqSz);
+    j = seqSz;
+    XMEMCPY(output + j, ver, verSz);
+    j += verSz;
+
+    for (i = 0; i < RSA_INTS; i++) {
+        XMEMCPY(output + j, tmps[i], sizes[i]);
+        j += sizes[i];
+    }
+    FreeTmpRsas(tmps, key->heap);
+
+    return outLen;
+}
+
+#endif /* WOLFSSL_KEY_GEN && !NO_RSA */
+
+
+#if defined(WOLFSSL_CERT_GEN) && !defined(NO_RSA)
+
+
+#ifndef WOLFSSL_HAVE_MIN
+#define WOLFSSL_HAVE_MIN
+
+    static INLINE word32 min(word32 a, word32 b)
+    {
+        return a > b ? b : a;
+    }
+
+#endif /* WOLFSSL_HAVE_MIN */
+
+
+/* Initialize and Set Certficate defaults:
+   version    = 3 (0x2)
+   serial     = 0
+   sigType    = SHA_WITH_RSA
+   issuer     = blank
+   daysValid  = 500
+   selfSigned = 1 (true) use subject as issuer
+   subject    = blank
+*/
+void wc_InitCert(Cert* cert)
+{
+    cert->version    = 2;   /* version 3 is hex 2 */
+    cert->sigType    = CTC_SHAwRSA;
+    cert->daysValid  = 500;
+    cert->selfSigned = 1;
+    cert->isCA       = 0;
+    cert->bodySz     = 0;
+#ifdef WOLFSSL_ALT_NAMES
+    cert->altNamesSz   = 0;
+    cert->beforeDateSz = 0;
+    cert->afterDateSz  = 0;
+#endif
+    cert->keyType    = RSA_KEY;
+    XMEMSET(cert->serial, 0, CTC_SERIAL_SIZE);
+
+    cert->issuer.country[0] = '\0';
+    cert->issuer.countryEnc = CTC_PRINTABLE;
+    cert->issuer.state[0] = '\0';
+    cert->issuer.stateEnc = CTC_UTF8;
+    cert->issuer.locality[0] = '\0';
+    cert->issuer.localityEnc = CTC_UTF8;
+    cert->issuer.sur[0] = '\0';
+    cert->issuer.surEnc = CTC_UTF8;
+    cert->issuer.org[0] = '\0';
+    cert->issuer.orgEnc = CTC_UTF8;
+    cert->issuer.unit[0] = '\0';
+    cert->issuer.unitEnc = CTC_UTF8;
+    cert->issuer.commonName[0] = '\0';
+    cert->issuer.commonNameEnc = CTC_UTF8;
+    cert->issuer.email[0] = '\0';
+
+    cert->subject.country[0] = '\0';
+    cert->subject.countryEnc = CTC_PRINTABLE;
+    cert->subject.state[0] = '\0';
+    cert->subject.stateEnc = CTC_UTF8;
+    cert->subject.locality[0] = '\0';
+    cert->subject.localityEnc = CTC_UTF8;
+    cert->subject.sur[0] = '\0';
+    cert->subject.surEnc = CTC_UTF8;
+    cert->subject.org[0] = '\0';
+    cert->subject.orgEnc = CTC_UTF8;
+    cert->subject.unit[0] = '\0';
+    cert->subject.unitEnc = CTC_UTF8;
+    cert->subject.commonName[0] = '\0';
+    cert->subject.commonNameEnc = CTC_UTF8;
+    cert->subject.email[0] = '\0';
+
+#ifdef WOLFSSL_CERT_REQ
+    cert->challengePw[0] ='\0';
+#endif
+}
+
+
+/* DER encoded x509 Certificate */
+typedef struct DerCert {
+    byte size[MAX_LENGTH_SZ];          /* length encoded */
+    byte version[MAX_VERSION_SZ];      /* version encoded */
+    byte serial[CTC_SERIAL_SIZE + MAX_LENGTH_SZ]; /* serial number encoded */
+    byte sigAlgo[MAX_ALGO_SZ];         /* signature algo encoded */
+    byte issuer[ASN_NAME_MAX];         /* issuer  encoded */
+    byte subject[ASN_NAME_MAX];        /* subject encoded */
+    byte validity[MAX_DATE_SIZE*2 + MAX_SEQ_SZ*2];  /* before and after dates */
+    byte publicKey[MAX_PUBLIC_KEY_SZ]; /* rsa / ntru public key encoded */
+    byte ca[MAX_CA_SZ];                /* basic constraint CA true size */
+    byte extensions[MAX_EXTENSIONS_SZ];  /* all extensions */
+#ifdef WOLFSSL_CERT_REQ
+    byte attrib[MAX_ATTRIB_SZ];        /* Cert req attributes encoded */
+#endif
+    int  sizeSz;                       /* encoded size length */
+    int  versionSz;                    /* encoded version length */
+    int  serialSz;                     /* encoded serial length */
+    int  sigAlgoSz;                    /* enocded sig alog length */
+    int  issuerSz;                     /* encoded issuer length */
+    int  subjectSz;                    /* encoded subject length */
+    int  validitySz;                   /* encoded validity length */
+    int  publicKeySz;                  /* encoded public key length */
+    int  caSz;                         /* encoded CA extension length */
+    int  extensionsSz;                 /* encoded extensions total length */
+    int  total;                        /* total encoded lengths */
+#ifdef WOLFSSL_CERT_REQ
+    int  attribSz;
+#endif
+} DerCert;
+
+
+#ifdef WOLFSSL_CERT_REQ
+
+/* Write a set header to output */
+static word32 SetUTF8String(word32 len, byte* output)
+{
+    output[0] = ASN_UTF8STRING;
+    return SetLength(len, output + 1) + 1;
+}
+
+#endif /* WOLFSSL_CERT_REQ */
+
+
+/* Write a serial number to output */
+static int SetSerial(const byte* serial, byte* output)
+{
+    int length = 0;
+
+    output[length++] = ASN_INTEGER;
+    length += SetLength(CTC_SERIAL_SIZE, &output[length]);
+    XMEMCPY(&output[length], serial, CTC_SERIAL_SIZE);
+
+    return length + CTC_SERIAL_SIZE;
+}
+
+
+#ifdef HAVE_ECC 
+
+
+/* Write a public ECC key to output */
+static int SetEccPublicKey(byte* output, ecc_key* key)
+{
+    byte len[MAX_LENGTH_SZ + 1];  /* trailing 0 */
+    int  algoSz;
+    int  curveSz;
+    int  lenSz;
+    int  idx;
+    word32 pubSz = ECC_BUFSIZE;
+#ifdef WOLFSSL_SMALL_STACK
+    byte* algo = NULL;
+    byte* curve = NULL;
+    byte* pub = NULL;
+#else
+    byte algo[MAX_ALGO_SZ];
+    byte curve[MAX_ALGO_SZ];
+    byte pub[ECC_BUFSIZE];
+#endif
+
+#ifdef WOLFSSL_SMALL_STACK
+    pub = (byte*)XMALLOC(ECC_BUFSIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (pub == NULL)
+        return MEMORY_E;
+#endif
+
+    int ret = wc_ecc_export_x963(key, pub, &pubSz);
+    if (ret != 0) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(pub, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return ret;
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    curve = (byte*)XMALLOC(MAX_ALGO_SZ, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (curve == NULL) {
+        XFREE(pub, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        return MEMORY_E;
+    }
+#endif
+
+    /* headers */
+    curveSz = SetCurve(key, curve);
+    if (curveSz <= 0) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(curve, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(pub,   NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return curveSz;
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    algo = (byte*)XMALLOC(MAX_ALGO_SZ, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (algo == NULL) {
+        XFREE(curve, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(pub,   NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        return MEMORY_E;
+    }
+#endif
+
+    algoSz  = SetAlgoID(ECDSAk, algo, keyType, curveSz);
+    lenSz   = SetLength(pubSz + 1, len);
+    len[lenSz++] = 0;   /* trailing 0 */
+
+    /* write */
+    idx = SetSequence(pubSz + curveSz + lenSz + 1 + algoSz, output);
+        /* 1 is for ASN_BIT_STRING */
+    /* algo */
+    XMEMCPY(output + idx, algo, algoSz);
+    idx += algoSz;
+    /* curve */
+    XMEMCPY(output + idx, curve, curveSz);
+    idx += curveSz;
+    /* bit string */
+    output[idx++] = ASN_BIT_STRING;
+    /* length */
+    XMEMCPY(output + idx, len, lenSz);
+    idx += lenSz;
+    /* pub */
+    XMEMCPY(output + idx, pub, pubSz);
+    idx += pubSz;
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(algo,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(curve, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(pub,   NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return idx;
+}
+
+
+#endif /* HAVE_ECC */
+
+
+/* Write a public RSA key to output */
+static int SetRsaPublicKey(byte* output, RsaKey* key)
+{
+#ifdef WOLFSSL_SMALL_STACK
+    byte* n = NULL;
+    byte* e = NULL;
+    byte* algo = NULL;
+#else
+    byte n[MAX_RSA_INT_SZ];
+    byte e[MAX_RSA_E_SZ];
+    byte algo[MAX_ALGO_SZ];
+#endif
+    byte seq[MAX_SEQ_SZ];
+    byte len[MAX_LENGTH_SZ + 1];  /* trailing 0 */
+    int  nSz;
+    int  eSz;
+    int  algoSz;
+    int  seqSz;
+    int  lenSz;
+    int  idx;
+    int  rawLen;
+    int  leadingBit;
+    int  err;
+
+    /* n */
+#ifdef WOLFSSL_SMALL_STACK
+    n = (byte*)XMALLOC(MAX_RSA_INT_SZ, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (n == NULL)
+        return MEMORY_E;
+#endif
+
+    leadingBit = mp_leading_bit(&key->n);
+    rawLen = mp_unsigned_bin_size(&key->n) + leadingBit;
+    n[0] = ASN_INTEGER;
+    nSz  = SetLength(rawLen, n + 1) + 1;  /* int tag */
+
+    if ( (nSz + rawLen) < MAX_RSA_INT_SZ) {
+        if (leadingBit)
+            n[nSz] = 0;
+        err = mp_to_unsigned_bin(&key->n, n + nSz + leadingBit);
+        if (err == MP_OKAY)
+            nSz += rawLen;
+        else {
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(n, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return MP_TO_E;
+        }
+    }
+    else {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(n, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return BUFFER_E;
+    }
+
+    /* e */
+#ifdef WOLFSSL_SMALL_STACK
+    e = (byte*)XMALLOC(MAX_RSA_E_SZ, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (e == NULL) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(n, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return MEMORY_E;
+    }
+#endif
+
+    leadingBit = mp_leading_bit(&key->e);
+    rawLen = mp_unsigned_bin_size(&key->e) + leadingBit;
+    e[0] = ASN_INTEGER;
+    eSz  = SetLength(rawLen, e + 1) + 1;  /* int tag */
+
+    if ( (eSz + rawLen) < MAX_RSA_E_SZ) {
+        if (leadingBit)
+            e[eSz] = 0;
+        err = mp_to_unsigned_bin(&key->e, e + eSz + leadingBit);
+        if (err == MP_OKAY)
+            eSz += rawLen;
+        else {
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(n, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            XFREE(e, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return MP_TO_E;
+        }
+    }
+    else {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(n, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(e, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return BUFFER_E;
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    algo = (byte*)XMALLOC(MAX_ALGO_SZ, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (algo == NULL) {
+        XFREE(n, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(e, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        return MEMORY_E;
+    }
+#endif
+
+    /* headers */
+    algoSz = SetAlgoID(RSAk, algo, keyType, 0);
+    seqSz  = SetSequence(nSz + eSz, seq);
+    lenSz  = SetLength(seqSz + nSz + eSz + 1, len);
+    len[lenSz++] = 0;   /* trailing 0 */
+
+    /* write */
+    idx = SetSequence(nSz + eSz + seqSz + lenSz + 1 + algoSz, output);
+        /* 1 is for ASN_BIT_STRING */
+    /* algo */
+    XMEMCPY(output + idx, algo, algoSz);
+    idx += algoSz;
+    /* bit string */
+    output[idx++] = ASN_BIT_STRING;
+    /* length */
+    XMEMCPY(output + idx, len, lenSz);
+    idx += lenSz;
+    /* seq */
+    XMEMCPY(output + idx, seq, seqSz);
+    idx += seqSz;
+    /* n */
+    XMEMCPY(output + idx, n, nSz);
+    idx += nSz;
+    /* e */
+    XMEMCPY(output + idx, e, eSz);
+    idx += eSz;
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(n,    NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(e,    NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(algo, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return idx;
+}
+
+
+static INLINE byte itob(int number)
+{
+    return (byte)number + 0x30;
+}
+
+
+/* write time to output, format */
+static void SetTime(struct tm* date, byte* output)
+{
+    int i = 0;
+
+    output[i++] = itob((date->tm_year % 10000) / 1000);
+    output[i++] = itob((date->tm_year % 1000)  /  100);
+    output[i++] = itob((date->tm_year % 100)   /   10);
+    output[i++] = itob( date->tm_year % 10);
+
+    output[i++] = itob(date->tm_mon / 10);
+    output[i++] = itob(date->tm_mon % 10);
+
+    output[i++] = itob(date->tm_mday / 10);
+    output[i++] = itob(date->tm_mday % 10);
+
+    output[i++] = itob(date->tm_hour / 10);
+    output[i++] = itob(date->tm_hour % 10);
+
+    output[i++] = itob(date->tm_min / 10);
+    output[i++] = itob(date->tm_min % 10);
+
+    output[i++] = itob(date->tm_sec / 10);
+    output[i++] = itob(date->tm_sec % 10);
+    
+    output[i] = 'Z';  /* Zulu profile */
+}
+
+
+#ifdef WOLFSSL_ALT_NAMES
+
+/* Copy Dates from cert, return bytes written */
+static int CopyValidity(byte* output, Cert* cert)
+{
+    int seqSz;
+
+    WOLFSSL_ENTER("CopyValidity");
+
+    /* headers and output */
+    seqSz = SetSequence(cert->beforeDateSz + cert->afterDateSz, output);
+    XMEMCPY(output + seqSz, cert->beforeDate, cert->beforeDateSz);
+    XMEMCPY(output + seqSz + cert->beforeDateSz, cert->afterDate,
+                                                 cert->afterDateSz);
+    return seqSz + cert->beforeDateSz + cert->afterDateSz;
+}
+
+#endif
+
+
+/* for systems where mktime() doesn't normalize fully */
+static void RebuildTime(time_t* in, struct tm* out)
+{
+    #ifdef FREESCALE_MQX
+        out = localtime_r(in, out);
+    #else
+        (void)in;
+        (void)out;
+    #endif
+}
+
+
+/* Set Date validity from now until now + daysValid */
+static int SetValidity(byte* output, int daysValid)
+{
+    byte before[MAX_DATE_SIZE];
+    byte  after[MAX_DATE_SIZE];
+
+    int beforeSz;
+    int afterSz;
+    int seqSz;
+
+    time_t     ticks;
+    time_t     normalTime;
+    struct tm* now;
+    struct tm* tmpTime = NULL;
+    struct tm  local;
+
+#if defined(FREESCALE_MQX) || defined(TIME_OVERRIDES)
+    /* for use with gmtime_r */
+    struct tm tmpTimeStorage;
+    tmpTime = &tmpTimeStorage;
+#else
+    (void)tmpTime;
+#endif
+
+    ticks = XTIME(0);
+    now   = XGMTIME(&ticks, tmpTime);
+
+    /* before now */
+    local = *now;
+    before[0] = ASN_GENERALIZED_TIME;
+    beforeSz  = SetLength(ASN_GEN_TIME_SZ, before + 1) + 1;  /* gen tag */
+
+    /* subtract 1 day for more compliance */
+    local.tm_mday -= 1;
+    normalTime = mktime(&local);
+    RebuildTime(&normalTime, &local);
+
+    /* adjust */
+    local.tm_year += 1900;
+    local.tm_mon  +=    1;
+
+    SetTime(&local, before + beforeSz);
+    beforeSz += ASN_GEN_TIME_SZ;
+
+    /* after now + daysValid */
+    local = *now;
+    after[0] = ASN_GENERALIZED_TIME;
+    afterSz  = SetLength(ASN_GEN_TIME_SZ, after + 1) + 1;  /* gen tag */
+
+    /* add daysValid */
+    local.tm_mday += daysValid;
+    normalTime = mktime(&local);
+    RebuildTime(&normalTime, &local);
+
+    /* adjust */
+    local.tm_year += 1900;
+    local.tm_mon  +=    1;
+
+    SetTime(&local, after + afterSz);
+    afterSz += ASN_GEN_TIME_SZ;
+
+    /* headers and output */
+    seqSz = SetSequence(beforeSz + afterSz, output);
+    XMEMCPY(output + seqSz, before, beforeSz);
+    XMEMCPY(output + seqSz + beforeSz, after, afterSz);
+
+    return seqSz + beforeSz + afterSz;
+}
+
+
+/* ASN Encoded Name field */
+typedef struct EncodedName {
+    int  nameLen;                /* actual string value length */
+    int  totalLen;               /* total encoded length */
+    int  type;                   /* type of name */
+    int  used;                   /* are we actually using this one */
+    byte encoded[CTC_NAME_SIZE * 2]; /* encoding */
+} EncodedName;
+
+
+/* Get Which Name from index */
+static const char* GetOneName(CertName* name, int idx)
+{
+    switch (idx) {
+    case 0:
+       return name->country;
+
+    case 1:
+       return name->state;
+
+    case 2:
+       return name->locality;
+
+    case 3:
+       return name->sur;
+
+    case 4:
+       return name->org;
+
+    case 5:
+       return name->unit;
+
+    case 6:
+       return name->commonName;
+
+    case 7:
+       return name->email;
+
+    default:
+       return 0;
+    }
+}
+
+
+/* Get Which Name Encoding from index */
+static char GetNameType(CertName* name, int idx)
+{
+    switch (idx) {
+    case 0:
+       return name->countryEnc;
+
+    case 1:
+       return name->stateEnc;
+
+    case 2:
+       return name->localityEnc;
+
+    case 3:
+       return name->surEnc;
+
+    case 4:
+       return name->orgEnc;
+
+    case 5:
+       return name->unitEnc;
+
+    case 6:
+       return name->commonNameEnc;
+
+    default:
+       return 0;
+    }
+}
+
+
+/* Get ASN Name from index */
+static byte GetNameId(int idx)
+{
+    switch (idx) {
+    case 0:
+       return ASN_COUNTRY_NAME;
+
+    case 1:
+       return ASN_STATE_NAME;
+
+    case 2:
+       return ASN_LOCALITY_NAME;
+
+    case 3:
+       return ASN_SUR_NAME;
+
+    case 4:
+       return ASN_ORG_NAME;
+
+    case 5:
+       return ASN_ORGUNIT_NAME;
+
+    case 6:
+       return ASN_COMMON_NAME;
+
+    case 7:
+       /* email uses different id type */
+       return 0;
+
+    default:
+       return 0;
+    }
+}
+
+
+/* encode all extensions, return total bytes written */
+static int SetExtensions(byte* output, const byte* ext, int extSz, int header)
+{
+    byte sequence[MAX_SEQ_SZ];
+    byte len[MAX_LENGTH_SZ];
+
+    int sz = 0;
+    int seqSz = SetSequence(extSz, sequence);
+
+    if (header) {
+        int lenSz = SetLength(seqSz + extSz, len);
+        output[0] = ASN_EXTENSIONS; /* extensions id */
+        sz++;
+        XMEMCPY(&output[sz], len, lenSz);  /* length */
+        sz += lenSz;
+    }
+    XMEMCPY(&output[sz], sequence, seqSz);  /* sequence */
+    sz += seqSz;
+    XMEMCPY(&output[sz], ext, extSz);  /* extensions */
+    sz += extSz;
+
+    return sz;
+}
+
+
+/* encode CA basic constraint true, return total bytes written */
+static int SetCa(byte* output)
+{
+    static const byte ca[] = { 0x30, 0x0c, 0x06, 0x03, 0x55, 0x1d, 0x13, 0x04,
+                               0x05, 0x30, 0x03, 0x01, 0x01, 0xff };
+    
+    XMEMCPY(output, ca, sizeof(ca));
+
+    return (int)sizeof(ca);
+}
+
+
+/* encode CertName into output, return total bytes written */
+static int SetName(byte* output, CertName* name)
+{
+    int          totalBytes = 0, i, idx;
+#ifdef WOLFSSL_SMALL_STACK
+    EncodedName* names = NULL;
+#else
+    EncodedName  names[NAME_ENTRIES];
+#endif
+
+#ifdef WOLFSSL_SMALL_STACK
+    names = (EncodedName*)XMALLOC(sizeof(EncodedName) * NAME_ENTRIES, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+    if (names == NULL)
+        return MEMORY_E;
+#endif
+
+    for (i = 0; i < NAME_ENTRIES; i++) {
+        const char* nameStr = GetOneName(name, i);
+        if (nameStr) {
+            /* bottom up */
+            byte firstLen[MAX_LENGTH_SZ];
+            byte secondLen[MAX_LENGTH_SZ];
+            byte sequence[MAX_SEQ_SZ];
+            byte set[MAX_SET_SZ];
+
+            int email = i == (NAME_ENTRIES - 1) ? 1 : 0;
+            int strLen  = (int)XSTRLEN(nameStr);
+            int thisLen = strLen;
+            int firstSz, secondSz, seqSz, setSz;
+
+            if (strLen == 0) { /* no user data for this item */
+                names[i].used = 0;
+                continue;
+            }
+
+            secondSz = SetLength(strLen, secondLen);
+            thisLen += secondSz;
+            if (email) {
+                thisLen += EMAIL_JOINT_LEN;
+                thisLen ++;                               /* id type */
+                firstSz  = SetLength(EMAIL_JOINT_LEN, firstLen);
+            }
+            else {
+                thisLen++;                                 /* str type */
+                thisLen++;                                 /* id  type */
+                thisLen += JOINT_LEN;    
+                firstSz = SetLength(JOINT_LEN + 1, firstLen);
+            }
+            thisLen += firstSz;
+            thisLen++;                                /* object id */
+
+            seqSz = SetSequence(thisLen, sequence);
+            thisLen += seqSz;
+            setSz = SetSet(thisLen, set);
+            thisLen += setSz;
+
+            if (thisLen > (int)sizeof(names[i].encoded)) {
+#ifdef WOLFSSL_SMALL_STACK
+                XFREE(names, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+                return BUFFER_E;
+            }
+
+            /* store it */
+            idx = 0;
+            /* set */
+            XMEMCPY(names[i].encoded, set, setSz);
+            idx += setSz;
+            /* seq */
+            XMEMCPY(names[i].encoded + idx, sequence, seqSz);
+            idx += seqSz;
+            /* asn object id */
+            names[i].encoded[idx++] = ASN_OBJECT_ID;
+            /* first length */
+            XMEMCPY(names[i].encoded + idx, firstLen, firstSz);
+            idx += firstSz;
+            if (email) {
+                const byte EMAIL_OID[] = { 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d,
+                                           0x01, 0x09, 0x01, 0x16 };
+                /* email joint id */
+                XMEMCPY(names[i].encoded + idx, EMAIL_OID, sizeof(EMAIL_OID));
+                idx += (int)sizeof(EMAIL_OID);
+            }
+            else {
+                /* joint id */
+                byte bType = GetNameId(i);
+                names[i].encoded[idx++] = 0x55;
+                names[i].encoded[idx++] = 0x04;
+                /* id type */
+                names[i].encoded[idx++] = bType; 
+                /* str type */
+                names[i].encoded[idx++] = GetNameType(name, i);
+            }
+            /* second length */
+            XMEMCPY(names[i].encoded + idx, secondLen, secondSz);
+            idx += secondSz;
+            /* str value */
+            XMEMCPY(names[i].encoded + idx, nameStr, strLen);
+            idx += strLen;
+
+            totalBytes += idx;
+            names[i].totalLen = idx;
+            names[i].used = 1;
+        }
+        else
+            names[i].used = 0;
+    }
+
+    /* header */
+    idx = SetSequence(totalBytes, output);
+    totalBytes += idx;
+    if (totalBytes > ASN_NAME_MAX) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(names, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return BUFFER_E;
+    }
+
+    for (i = 0; i < NAME_ENTRIES; i++) {
+        if (names[i].used) {
+            XMEMCPY(output + idx, names[i].encoded, names[i].totalLen);
+            idx += names[i].totalLen;
+        }
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(names, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return totalBytes;
+}
+
+/* encode info from cert into DER encoded format */
+static int EncodeCert(Cert* cert, DerCert* der, RsaKey* rsaKey, ecc_key* eccKey,
+                      RNG* rng, const byte* ntruKey, word16 ntruSz)
+{
+    int ret;
+
+    (void)eccKey;
+    (void)ntruKey;
+    (void)ntruSz;
+
+    /* init */
+    XMEMSET(der, 0, sizeof(DerCert));
+
+    /* version */
+    der->versionSz = SetMyVersion(cert->version, der->version, TRUE);
+
+    /* serial number */
+    ret = wc_RNG_GenerateBlock(rng, cert->serial, CTC_SERIAL_SIZE);
+    if (ret != 0)
+        return ret;
+
+    cert->serial[0] = 0x01;   /* ensure positive */
+    der->serialSz  = SetSerial(cert->serial, der->serial);
+
+    /* signature algo */
+    der->sigAlgoSz = SetAlgoID(cert->sigType, der->sigAlgo, sigType, 0);
+    if (der->sigAlgoSz == 0)
+        return ALGO_ID_E;
+
+    /* public key */
+    if (cert->keyType == RSA_KEY) {
+        if (rsaKey == NULL)
+            return PUBLIC_KEY_E;
+        der->publicKeySz = SetRsaPublicKey(der->publicKey, rsaKey);
+        if (der->publicKeySz <= 0)
+            return PUBLIC_KEY_E;
+    }
+
+#ifdef HAVE_ECC
+    if (cert->keyType == ECC_KEY) {
+        if (eccKey == NULL)
+            return PUBLIC_KEY_E;
+        der->publicKeySz = SetEccPublicKey(der->publicKey, eccKey);
+        if (der->publicKeySz <= 0)
+            return PUBLIC_KEY_E;
+    }
+#endif /* HAVE_ECC */
+
+#ifdef HAVE_NTRU
+    if (cert->keyType == NTRU_KEY) {
+        word32 rc;
+        word16 encodedSz;
+
+        rc  = ntru_crypto_ntru_encrypt_publicKey2SubjectPublicKeyInfo( ntruSz,
+                                                   ntruKey, &encodedSz, NULL);
+        if (rc != NTRU_OK)
+            return PUBLIC_KEY_E;
+        if (encodedSz > MAX_PUBLIC_KEY_SZ)
+            return PUBLIC_KEY_E;
+
+        rc  = ntru_crypto_ntru_encrypt_publicKey2SubjectPublicKeyInfo( ntruSz,
+                                         ntruKey, &encodedSz, der->publicKey);
+        if (rc != NTRU_OK)
+            return PUBLIC_KEY_E;
+
+        der->publicKeySz = encodedSz;
+    }
+#endif /* HAVE_NTRU */
+
+    der->validitySz = 0;
+#ifdef WOLFSSL_ALT_NAMES
+    /* date validity copy ? */
+    if (cert->beforeDateSz && cert->afterDateSz) {
+        der->validitySz = CopyValidity(der->validity, cert);
+        if (der->validitySz == 0)
+            return DATE_E;
+    }
+#endif
+
+    /* date validity */
+    if (der->validitySz == 0) {
+        der->validitySz = SetValidity(der->validity, cert->daysValid);
+        if (der->validitySz == 0)
+            return DATE_E;
+    }
+
+    /* subject name */
+    der->subjectSz = SetName(der->subject, &cert->subject);
+    if (der->subjectSz == 0)
+        return SUBJECT_E;
+
+    /* issuer name */
+    der->issuerSz = SetName(der->issuer, cert->selfSigned ?
+             &cert->subject : &cert->issuer);
+    if (der->issuerSz == 0)
+        return ISSUER_E;
+
+    /* CA */
+    if (cert->isCA) {
+        der->caSz = SetCa(der->ca);
+        if (der->caSz == 0)
+            return CA_TRUE_E;
+    }
+    else
+        der->caSz = 0;
+
+    /* extensions, just CA now */
+    if (cert->isCA) {
+        der->extensionsSz = SetExtensions(der->extensions,
+                                          der->ca, der->caSz, TRUE);
+        if (der->extensionsSz == 0)
+            return EXTENSIONS_E;
+    }
+    else
+        der->extensionsSz = 0;
+
+#ifdef WOLFSSL_ALT_NAMES
+    if (der->extensionsSz == 0 && cert->altNamesSz) {
+        der->extensionsSz = SetExtensions(der->extensions, cert->altNames,
+                                          cert->altNamesSz, TRUE);
+        if (der->extensionsSz == 0)
+            return EXTENSIONS_E;
+    }
+#endif
+
+    der->total = der->versionSz + der->serialSz + der->sigAlgoSz +
+        der->publicKeySz + der->validitySz + der->subjectSz + der->issuerSz +
+        der->extensionsSz;
+
+    return 0;
+}
+
+
+/* write DER encoded cert to buffer, size already checked */
+static int WriteCertBody(DerCert* der, byte* buffer)
+{
+    int idx;
+
+    /* signed part header */
+    idx = SetSequence(der->total, buffer);
+    /* version */
+    XMEMCPY(buffer + idx, der->version, der->versionSz);
+    idx += der->versionSz;
+    /* serial */
+    XMEMCPY(buffer + idx, der->serial, der->serialSz);
+    idx += der->serialSz;
+    /* sig algo */
+    XMEMCPY(buffer + idx, der->sigAlgo, der->sigAlgoSz);
+    idx += der->sigAlgoSz;
+    /* issuer */
+    XMEMCPY(buffer + idx, der->issuer, der->issuerSz);
+    idx += der->issuerSz;
+    /* validity */
+    XMEMCPY(buffer + idx, der->validity, der->validitySz);
+    idx += der->validitySz;
+    /* subject */
+    XMEMCPY(buffer + idx, der->subject, der->subjectSz);
+    idx += der->subjectSz;
+    /* public key */
+    XMEMCPY(buffer + idx, der->publicKey, der->publicKeySz);
+    idx += der->publicKeySz;
+    if (der->extensionsSz) {
+        /* extensions */
+        XMEMCPY(buffer + idx, der->extensions, min(der->extensionsSz,
+                                                   sizeof(der->extensions)));
+        idx += der->extensionsSz;
+    }
+
+    return idx;
+}
+
+
+/* Make RSA signature from buffer (sz), write to sig (sigSz) */
+static int MakeSignature(const byte* buffer, int sz, byte* sig, int sigSz,
+                         RsaKey* rsaKey, ecc_key* eccKey, RNG* rng,
+                         int sigAlgoType)
+{
+    int encSigSz, digestSz, typeH = 0, ret = 0;
+    byte digest[SHA256_DIGEST_SIZE]; /* max size */
+#ifdef WOLFSSL_SMALL_STACK
+    byte* encSig;
+#else
+    byte encSig[MAX_ENCODED_DIG_SZ + MAX_ALGO_SZ + MAX_SEQ_SZ];
+#endif
+
+    (void)digest;
+    (void)digestSz;
+    (void)encSig;
+    (void)encSigSz;
+    (void)typeH;
+
+    (void)buffer;
+    (void)sz;
+    (void)sig;
+    (void)sigSz;
+    (void)rsaKey;
+    (void)eccKey;
+    (void)rng;
+
+    switch (sigAlgoType) {
+    #ifndef NO_MD5
+        case CTC_MD5wRSA:
+        if ((ret = wc_Md5Hash(buffer, sz, digest)) == 0) {
+            typeH    = MD5h;
+            digestSz = MD5_DIGEST_SIZE;
+        }
+        break;
+    #endif
+    #ifndef NO_SHA
+        case CTC_SHAwRSA:
+        case CTC_SHAwECDSA:
+        if ((ret = wc_ShaHash(buffer, sz, digest)) == 0) {
+            typeH    = SHAh;
+            digestSz = SHA_DIGEST_SIZE;          
+        }
+        break;
+    #endif
+    #ifndef NO_SHA256
+        case CTC_SHA256wRSA:
+        case CTC_SHA256wECDSA:
+        if ((ret = wc_Sha256Hash(buffer, sz, digest)) == 0) {
+            typeH    = SHA256h;
+            digestSz = SHA256_DIGEST_SIZE;
+        }
+        break;
+    #endif
+        default:
+            WOLFSSL_MSG("MakeSignautre called with unsupported type");
+            ret = ALGO_ID_E;
+    }
+    
+    if (ret != 0)
+        return ret;
+    
+#ifdef WOLFSSL_SMALL_STACK
+    encSig = (byte*)XMALLOC(MAX_ENCODED_DIG_SZ + MAX_ALGO_SZ + MAX_SEQ_SZ,
+                                                 NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (encSig == NULL)
+        return MEMORY_E;
+#endif
+    
+    ret = ALGO_ID_E;
+    
+#ifndef NO_RSA
+    if (rsaKey) {
+        /* signature */
+        encSigSz = wc_EncodeSignature(encSig, digest, digestSz, typeH);
+        ret = wc_RsaSSL_Sign(encSig, encSigSz, sig, sigSz, rsaKey, rng);
+    }
+#endif
+    
+#ifdef HAVE_ECC
+    if (!rsaKey && eccKey) {
+        word32 outSz = sigSz;
+        ret = wc_ecc_sign_hash(digest, digestSz, sig, &outSz, rng, eccKey);
+
+        if (ret == 0)
+            ret = outSz;
+    }
+#endif
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(encSig, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+
+/* add signature to end of buffer, size of buffer assumed checked, return
+   new length */
+static int AddSignature(byte* buffer, int bodySz, const byte* sig, int sigSz,
+                        int sigAlgoType)
+{
+    byte seq[MAX_SEQ_SZ];
+    int  idx = bodySz, seqSz;
+
+    /* algo */
+    idx += SetAlgoID(sigAlgoType, buffer + idx, sigType, 0);
+    /* bit string */
+    buffer[idx++] = ASN_BIT_STRING;
+    /* length */
+    idx += SetLength(sigSz + 1, buffer + idx);
+    buffer[idx++] = 0;   /* trailing 0 */
+    /* signature */
+    XMEMCPY(buffer + idx, sig, sigSz);
+    idx += sigSz;
+
+    /* make room for overall header */
+    seqSz = SetSequence(idx, seq);
+    XMEMMOVE(buffer + seqSz, buffer, idx);
+    XMEMCPY(buffer, seq, seqSz);
+
+    return idx + seqSz;
+}
+
+
+/* Make an x509 Certificate v3 any key type from cert input, write to buffer */
+static int MakeAnyCert(Cert* cert, byte* derBuffer, word32 derSz,
+                       RsaKey* rsaKey, ecc_key* eccKey, RNG* rng,
+                       const byte* ntruKey, word16 ntruSz)
+{
+    int ret;
+#ifdef WOLFSSL_SMALL_STACK
+    DerCert* der;
+#else
+    DerCert der[1];
+#endif
+
+    cert->keyType = eccKey ? ECC_KEY : (rsaKey ? RSA_KEY : NTRU_KEY);
+
+#ifdef WOLFSSL_SMALL_STACK
+    der = (DerCert*)XMALLOC(sizeof(DerCert), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (der == NULL)
+        return MEMORY_E;
+#endif
+
+    ret = EncodeCert(cert, der, rsaKey, eccKey, rng, ntruKey, ntruSz);
+
+    if (ret == 0) {
+        if (der->total + MAX_SEQ_SZ * 2 > (int)derSz)
+            ret = BUFFER_E;
+        else
+            ret = cert->bodySz = WriteCertBody(der, derBuffer);
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(der, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+
+/* Make an x509 Certificate v3 RSA or ECC from cert input, write to buffer */
+int wc_MakeCert(Cert* cert, byte* derBuffer, word32 derSz, RsaKey* rsaKey,
+             ecc_key* eccKey, RNG* rng)
+{
+    return MakeAnyCert(cert, derBuffer, derSz, rsaKey, eccKey, rng, NULL, 0);
+}
+
+
+#ifdef HAVE_NTRU
+
+int wc_MakeNtruCert(Cert* cert, byte* derBuffer, word32 derSz,
+                  const byte* ntruKey, word16 keySz, RNG* rng)
+{
+    return MakeAnyCert(cert, derBuffer, derSz, NULL, NULL, rng, ntruKey, keySz);
+}
+
+#endif /* HAVE_NTRU */
+
+
+#ifdef WOLFSSL_CERT_REQ
+
+static int SetReqAttrib(byte* output, char* pw, int extSz)
+{
+    static const byte cpOid[] =
+        { ASN_OBJECT_ID, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01,
+                         0x09, 0x07 };
+    static const byte erOid[] =
+        { ASN_OBJECT_ID, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01,
+                         0x09, 0x0e };
+
+    int sz      = 0; /* overall size */
+    int cpSz    = 0; /* Challenge Password section size */
+    int cpSeqSz = 0;
+    int cpSetSz = 0;
+    int cpStrSz = 0;
+    int pwSz    = 0;
+    int erSz    = 0; /* Extension Request section size */
+    int erSeqSz = 0;
+    int erSetSz = 0;
+    byte cpSeq[MAX_SEQ_SZ];
+    byte cpSet[MAX_SET_SZ];
+    byte cpStr[MAX_PRSTR_SZ];
+    byte erSeq[MAX_SEQ_SZ];
+    byte erSet[MAX_SET_SZ];
+
+    output[0] = 0xa0;
+    sz++;
+
+    if (pw && pw[0]) {
+        pwSz = (int)XSTRLEN(pw);
+        cpStrSz = SetUTF8String(pwSz, cpStr);
+        cpSetSz = SetSet(cpStrSz + pwSz, cpSet);
+        cpSeqSz = SetSequence(sizeof(cpOid) + cpSetSz + cpStrSz + pwSz, cpSeq);
+        cpSz = cpSeqSz + sizeof(cpOid) + cpSetSz + cpStrSz + pwSz;
+    }
+
+    if (extSz) {
+        erSetSz = SetSet(extSz, erSet);
+        erSeqSz = SetSequence(erSetSz + sizeof(erOid) + extSz, erSeq);
+        erSz = extSz + erSetSz + erSeqSz + sizeof(erOid);
+    }
+
+    /* Put the pieces together. */
+    sz += SetLength(cpSz + erSz, &output[sz]);
+
+    if (cpSz) {
+        XMEMCPY(&output[sz], cpSeq, cpSeqSz);
+        sz += cpSeqSz;
+        XMEMCPY(&output[sz], cpOid, sizeof(cpOid));
+        sz += sizeof(cpOid);
+        XMEMCPY(&output[sz], cpSet, cpSetSz);
+        sz += cpSetSz;
+        XMEMCPY(&output[sz], cpStr, cpStrSz);
+        sz += cpStrSz;
+        XMEMCPY(&output[sz], pw, pwSz);
+        sz += pwSz;
+    }
+
+    if (erSz) {
+        XMEMCPY(&output[sz], erSeq, erSeqSz);
+        sz += erSeqSz;
+        XMEMCPY(&output[sz], erOid, sizeof(erOid));
+        sz += sizeof(erOid);
+        XMEMCPY(&output[sz], erSet, erSetSz);
+        sz += erSetSz;
+        /* The actual extension data will be tacked onto the output later. */
+    }
+
+    return sz;
+}
+
+
+/* encode info from cert into DER encoded format */
+static int EncodeCertReq(Cert* cert, DerCert* der,
+                         RsaKey* rsaKey, ecc_key* eccKey)
+{
+    (void)eccKey;
+
+    /* init */
+    XMEMSET(der, 0, sizeof(DerCert));
+
+    /* version */
+    der->versionSz = SetMyVersion(cert->version, der->version, FALSE);
+
+    /* subject name */
+    der->subjectSz = SetName(der->subject, &cert->subject);
+    if (der->subjectSz == 0)
+        return SUBJECT_E;
+
+    /* public key */
+    if (cert->keyType == RSA_KEY) {
+        if (rsaKey == NULL)
+            return PUBLIC_KEY_E;
+        der->publicKeySz = SetRsaPublicKey(der->publicKey, rsaKey);
+        if (der->publicKeySz <= 0)
+            return PUBLIC_KEY_E;
+    }
+
+#ifdef HAVE_ECC
+    if (cert->keyType == ECC_KEY) {
+        if (eccKey == NULL)
+            return PUBLIC_KEY_E;
+        der->publicKeySz = SetEccPublicKey(der->publicKey, eccKey);
+        if (der->publicKeySz <= 0)
+            return PUBLIC_KEY_E;
+    }
+#endif /* HAVE_ECC */
+
+    /* CA */
+    if (cert->isCA) {
+        der->caSz = SetCa(der->ca);
+        if (der->caSz == 0)
+            return CA_TRUE_E;
+    }
+    else
+        der->caSz = 0;
+
+    /* extensions, just CA now */
+    if (cert->isCA) {
+        der->extensionsSz = SetExtensions(der->extensions,
+                                          der->ca, der->caSz, FALSE);
+        if (der->extensionsSz == 0)
+            return EXTENSIONS_E;
+    }
+    else
+        der->extensionsSz = 0;
+
+    der->attribSz = SetReqAttrib(der->attrib,
+                                 cert->challengePw, der->extensionsSz);
+    if (der->attribSz == 0)
+        return REQ_ATTRIBUTE_E;
+
+    der->total = der->versionSz + der->subjectSz + der->publicKeySz +
+        der->extensionsSz + der->attribSz;
+
+    return 0;
+}
+
+
+/* write DER encoded cert req to buffer, size already checked */
+static int WriteCertReqBody(DerCert* der, byte* buffer)
+{
+    int idx;
+
+    /* signed part header */
+    idx = SetSequence(der->total, buffer);
+    /* version */
+    XMEMCPY(buffer + idx, der->version, der->versionSz);
+    idx += der->versionSz;
+    /* subject */
+    XMEMCPY(buffer + idx, der->subject, der->subjectSz);
+    idx += der->subjectSz;
+    /* public key */
+    XMEMCPY(buffer + idx, der->publicKey, der->publicKeySz);
+    idx += der->publicKeySz;
+    /* attributes */
+    XMEMCPY(buffer + idx, der->attrib, der->attribSz);
+    idx += der->attribSz;
+    /* extensions */
+    if (der->extensionsSz) {
+        XMEMCPY(buffer + idx, der->extensions, min(der->extensionsSz,
+                                                   sizeof(der->extensions)));
+        idx += der->extensionsSz;
+    }
+
+    return idx;
+}
+
+
+int wc_MakeCertReq(Cert* cert, byte* derBuffer, word32 derSz,
+                RsaKey* rsaKey, ecc_key* eccKey)
+{
+    int ret;
+#ifdef WOLFSSL_SMALL_STACK
+    DerCert* der;
+#else
+    DerCert der[1];
+#endif
+
+    cert->keyType = eccKey ? ECC_KEY : RSA_KEY;
+
+#ifdef WOLFSSL_SMALL_STACK
+    der = (DerCert*)XMALLOC(sizeof(DerCert), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (der == NULL)
+        return MEMORY_E;
+#endif
+
+    ret = EncodeCertReq(cert, der, rsaKey, eccKey);
+
+    if (ret == 0) {
+        if (der->total + MAX_SEQ_SZ * 2 > (int)derSz)
+            ret = BUFFER_E;
+        else
+            ret = cert->bodySz = WriteCertReqBody(der, derBuffer);
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(der, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+#endif /* WOLFSSL_CERT_REQ */
+
+
+int wc_SignCert(int requestSz, int sType, byte* buffer, word32 buffSz,
+             RsaKey* rsaKey, ecc_key* eccKey, RNG* rng)
+{
+    int sigSz;
+#ifdef WOLFSSL_SMALL_STACK
+    byte* sig;
+#else
+    byte sig[MAX_ENCODED_SIG_SZ];
+#endif
+
+    if (requestSz < 0)
+        return requestSz;
+
+#ifdef WOLFSSL_SMALL_STACK
+    sig = (byte*)XMALLOC(MAX_ENCODED_SIG_SZ, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (sig == NULL)
+        return MEMORY_E;
+#endif
+
+    sigSz = MakeSignature(buffer, requestSz, sig, MAX_ENCODED_SIG_SZ, rsaKey,
+                          eccKey, rng, sType);
+
+    if (sigSz >= 0) {
+        if (requestSz + MAX_SEQ_SZ * 2 + sigSz > (int)buffSz)
+            sigSz = BUFFER_E;
+        else
+            sigSz = AddSignature(buffer, requestSz, sig, sigSz, sType);
+    }
+    
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(sig, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return sigSz;
+}
+
+
+int wc_MakeSelfCert(Cert* cert, byte* buffer, word32 buffSz, RsaKey* key, RNG* rng)
+{
+    int ret = wc_MakeCert(cert, buffer, buffSz, key, NULL, rng);
+
+    if (ret < 0)
+        return ret;
+
+    return wc_SignCert(cert->bodySz, cert->sigType, buffer, buffSz, key, NULL,rng);
+}
+
+
+#ifdef WOLFSSL_ALT_NAMES 
+
+/* Set Alt Names from der cert, return 0 on success */
+static int SetAltNamesFromCert(Cert* cert, const byte* der, int derSz)
+{
+    int ret;
+#ifdef WOLFSSL_SMALL_STACK
+    DecodedCert* decoded;
+#else
+    DecodedCert decoded[1];
+#endif
+
+    if (derSz < 0)
+        return derSz;
+
+#ifdef WOLFSSL_SMALL_STACK
+    decoded = (DecodedCert*)XMALLOC(sizeof(DecodedCert), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+    if (decoded == NULL)
+        return MEMORY_E;
+#endif
+    
+    InitDecodedCert(decoded, (byte*)der, derSz, 0);
+    ret = ParseCertRelative(decoded, CA_TYPE, NO_VERIFY, 0);
+
+    if (ret < 0) {
+        WOLFSSL_MSG("ParseCertRelative error");
+    }
+    else if (decoded->extensions) {
+        byte   b;
+        int    length;
+        word32 maxExtensionsIdx;
+
+        decoded->srcIdx = decoded->extensionsIdx;
+        b = decoded->source[decoded->srcIdx++];
+        
+        if (b != ASN_EXTENSIONS) {
+            ret = ASN_PARSE_E;
+        }
+        else if (GetLength(decoded->source, &decoded->srcIdx, &length,
+                                                         decoded->maxIdx) < 0) {
+            ret = ASN_PARSE_E;
+        }
+        else if (GetSequence(decoded->source, &decoded->srcIdx, &length,
+                                                         decoded->maxIdx) < 0) {
+            ret = ASN_PARSE_E;
+        }
+        else {
+            maxExtensionsIdx = decoded->srcIdx + length;
+
+            while (decoded->srcIdx < maxExtensionsIdx) {
+                word32 oid;
+                word32 startIdx = decoded->srcIdx;
+                word32 tmpIdx;
+
+                if (GetSequence(decoded->source, &decoded->srcIdx, &length,
+                            decoded->maxIdx) < 0) {
+                    ret = ASN_PARSE_E;
+                    break;
+                }
+
+                tmpIdx = decoded->srcIdx;
+                decoded->srcIdx = startIdx;
+
+                if (GetAlgoId(decoded->source, &decoded->srcIdx, &oid,
+                              decoded->maxIdx) < 0) {
+                    ret = ASN_PARSE_E;
+                    break;
+                }
+
+                if (oid == ALT_NAMES_OID) {
+                    cert->altNamesSz = length + (tmpIdx - startIdx);
+
+                    if (cert->altNamesSz < (int)sizeof(cert->altNames))
+                        XMEMCPY(cert->altNames, &decoded->source[startIdx],
+                                cert->altNamesSz);
+                    else {
+                        cert->altNamesSz = 0;
+                        WOLFSSL_MSG("AltNames extensions too big");
+                        ret = ALT_NAME_E;
+                        break;
+                    }
+                }
+                decoded->srcIdx = tmpIdx + length;
+            }
+        }
+    }
+
+    FreeDecodedCert(decoded);
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(decoded, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret < 0 ? ret : 0;
+}
+
+
+/* Set Dates from der cert, return 0 on success */
+static int SetDatesFromCert(Cert* cert, const byte* der, int derSz)
+{
+    int ret;
+#ifdef WOLFSSL_SMALL_STACK
+    DecodedCert* decoded;
+#else
+    DecodedCert decoded[1];
+#endif
+
+    WOLFSSL_ENTER("SetDatesFromCert");
+    if (derSz < 0)
+        return derSz;
+    
+#ifdef WOLFSSL_SMALL_STACK
+    decoded = (DecodedCert*)XMALLOC(sizeof(DecodedCert), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+    if (decoded == NULL)
+        return MEMORY_E;
+#endif
+
+    InitDecodedCert(decoded, (byte*)der, derSz, 0);
+    ret = ParseCertRelative(decoded, CA_TYPE, NO_VERIFY, 0);
+
+    if (ret < 0) {
+        WOLFSSL_MSG("ParseCertRelative error");
+    }
+    else if (decoded->beforeDate == NULL || decoded->afterDate == NULL) {
+        WOLFSSL_MSG("Couldn't extract dates");
+        ret = -1;
+    }
+    else if (decoded->beforeDateLen > MAX_DATE_SIZE || 
+                                        decoded->afterDateLen > MAX_DATE_SIZE) {
+        WOLFSSL_MSG("Bad date size");
+        ret = -1;
+    }
+    else {
+        XMEMCPY(cert->beforeDate, decoded->beforeDate, decoded->beforeDateLen);
+        XMEMCPY(cert->afterDate,  decoded->afterDate,  decoded->afterDateLen);
+
+        cert->beforeDateSz = decoded->beforeDateLen;
+        cert->afterDateSz  = decoded->afterDateLen;
+    }
+
+    FreeDecodedCert(decoded);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(decoded, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret < 0 ? ret : 0;
+}
+
+
+#endif /* WOLFSSL_ALT_NAMES && !NO_RSA */
+
+
+/* Set cn name from der buffer, return 0 on success */
+static int SetNameFromCert(CertName* cn, const byte* der, int derSz)
+{
+    int ret, sz;
+#ifdef WOLFSSL_SMALL_STACK
+    DecodedCert* decoded;
+#else
+    DecodedCert decoded[1];
+#endif
+
+    if (derSz < 0)
+        return derSz;
+
+#ifdef WOLFSSL_SMALL_STACK
+    decoded = (DecodedCert*)XMALLOC(sizeof(DecodedCert), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+    if (decoded == NULL)
+        return MEMORY_E;
+#endif
+
+    InitDecodedCert(decoded, (byte*)der, derSz, 0);
+    ret = ParseCertRelative(decoded, CA_TYPE, NO_VERIFY, 0);
+
+    if (ret < 0) {
+        WOLFSSL_MSG("ParseCertRelative error");
+    }
+    else {
+        if (decoded->subjectCN) {
+            sz = (decoded->subjectCNLen < CTC_NAME_SIZE) ? decoded->subjectCNLen
+                                                         : CTC_NAME_SIZE - 1;
+            strncpy(cn->commonName, decoded->subjectCN, CTC_NAME_SIZE);
+            cn->commonName[sz] = 0;
+            cn->commonNameEnc = decoded->subjectCNEnc;
+        }
+        if (decoded->subjectC) {
+            sz = (decoded->subjectCLen < CTC_NAME_SIZE) ? decoded->subjectCLen
+                                                        : CTC_NAME_SIZE - 1;
+            strncpy(cn->country, decoded->subjectC, CTC_NAME_SIZE);
+            cn->country[sz] = 0;
+            cn->countryEnc = decoded->subjectCEnc;
+        }
+        if (decoded->subjectST) {
+            sz = (decoded->subjectSTLen < CTC_NAME_SIZE) ? decoded->subjectSTLen
+                                                         : CTC_NAME_SIZE - 1;
+            strncpy(cn->state, decoded->subjectST, CTC_NAME_SIZE);
+            cn->state[sz] = 0;
+            cn->stateEnc = decoded->subjectSTEnc;
+        }
+        if (decoded->subjectL) {
+            sz = (decoded->subjectLLen < CTC_NAME_SIZE) ? decoded->subjectLLen
+                                                        : CTC_NAME_SIZE - 1;
+            strncpy(cn->locality, decoded->subjectL, CTC_NAME_SIZE);
+            cn->locality[sz] = 0;
+            cn->localityEnc = decoded->subjectLEnc;
+        }
+        if (decoded->subjectO) {
+            sz = (decoded->subjectOLen < CTC_NAME_SIZE) ? decoded->subjectOLen
+                                                        : CTC_NAME_SIZE - 1;
+            strncpy(cn->org, decoded->subjectO, CTC_NAME_SIZE);
+            cn->org[sz] = 0;
+            cn->orgEnc = decoded->subjectOEnc;
+        }
+        if (decoded->subjectOU) {
+            sz = (decoded->subjectOULen < CTC_NAME_SIZE) ? decoded->subjectOULen
+                                                         : CTC_NAME_SIZE - 1;
+            strncpy(cn->unit, decoded->subjectOU, CTC_NAME_SIZE);
+            cn->unit[sz] = 0;
+            cn->unitEnc = decoded->subjectOUEnc;
+        }
+        if (decoded->subjectSN) {
+            sz = (decoded->subjectSNLen < CTC_NAME_SIZE) ? decoded->subjectSNLen
+                                                         : CTC_NAME_SIZE - 1;
+            strncpy(cn->sur, decoded->subjectSN, CTC_NAME_SIZE);
+            cn->sur[sz] = 0;
+            cn->surEnc = decoded->subjectSNEnc;
+        }
+        if (decoded->subjectEmail) {
+            sz = (decoded->subjectEmailLen < CTC_NAME_SIZE)
+               ?  decoded->subjectEmailLen : CTC_NAME_SIZE - 1;
+            strncpy(cn->email, decoded->subjectEmail, CTC_NAME_SIZE);
+            cn->email[sz] = 0;
+        }
+    }
+
+    FreeDecodedCert(decoded);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(decoded, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret < 0 ? ret : 0;
+}
+
+
+#ifndef NO_FILESYSTEM
+
+/* Set cert issuer from issuerFile in PEM */
+int wc_SetIssuer(Cert* cert, const char* issuerFile)
+{
+    int         ret;
+    int         derSz;
+    byte*       der = (byte*)XMALLOC(EIGHTK_BUF, NULL, DYNAMIC_TYPE_CERT);
+
+    if (der == NULL) {
+        WOLFSSL_MSG("wc_SetIssuer OOF Problem");
+        return MEMORY_E;
+    }
+    derSz = wolfSSL_PemCertToDer(issuerFile, der, EIGHTK_BUF);
+    cert->selfSigned = 0;
+    ret = SetNameFromCert(&cert->issuer, der, derSz);
+    XFREE(der, NULL, DYNAMIC_TYPE_CERT);
+
+    return ret;
+}
+
+
+/* Set cert subject from subjectFile in PEM */
+int wc_SetSubject(Cert* cert, const char* subjectFile)
+{
+    int         ret;
+    int         derSz;
+    byte*       der = (byte*)XMALLOC(EIGHTK_BUF, NULL, DYNAMIC_TYPE_CERT);
+
+    if (der == NULL) {
+        WOLFSSL_MSG("wc_SetSubject OOF Problem");
+        return MEMORY_E;
+    }
+    derSz = wolfSSL_PemCertToDer(subjectFile, der, EIGHTK_BUF);
+    ret = SetNameFromCert(&cert->subject, der, derSz);
+    XFREE(der, NULL, DYNAMIC_TYPE_CERT);
+
+    return ret;
+}
+
+
+#ifdef WOLFSSL_ALT_NAMES
+
+/* Set atl names from file in PEM */
+int wc_SetAltNames(Cert* cert, const char* file)
+{
+    int         ret;
+    int         derSz;
+    byte*       der = (byte*)XMALLOC(EIGHTK_BUF, NULL, DYNAMIC_TYPE_CERT);
+
+    if (der == NULL) {
+        WOLFSSL_MSG("wc_SetAltNames OOF Problem");
+        return MEMORY_E;
+    }
+    derSz = wolfSSL_PemCertToDer(file, der, EIGHTK_BUF);
+    ret = SetAltNamesFromCert(cert, der, derSz);
+    XFREE(der, NULL, DYNAMIC_TYPE_CERT);
+
+    return ret;
+}
+
+#endif /* WOLFSSL_ALT_NAMES */
+
+#endif /* NO_FILESYSTEM */
+
+/* Set cert issuer from DER buffer */
+int wc_SetIssuerBuffer(Cert* cert, const byte* der, int derSz)
+{
+    cert->selfSigned = 0;
+    return SetNameFromCert(&cert->issuer, der, derSz);
+}
+
+
+/* Set cert subject from DER buffer */
+int wc_SetSubjectBuffer(Cert* cert, const byte* der, int derSz)
+{
+    return SetNameFromCert(&cert->subject, der, derSz);
+}
+
+
+#ifdef WOLFSSL_ALT_NAMES
+
+/* Set cert alt names from DER buffer */
+int wc_SetAltNamesBuffer(Cert* cert, const byte* der, int derSz)
+{
+    return SetAltNamesFromCert(cert, der, derSz);
+}
+
+/* Set cert dates from DER buffer */
+int wc_SetDatesBuffer(Cert* cert, const byte* der, int derSz)
+{
+    return SetDatesFromCert(cert, der, derSz);
+}
+
+#endif /* WOLFSSL_ALT_NAMES */
+
+#endif /* WOLFSSL_CERT_GEN */
+
+
+#ifdef HAVE_ECC
+
+/* Der Encode r & s ints into out, outLen is (in/out) size */
+int StoreECC_DSA_Sig(byte* out, word32* outLen, mp_int* r, mp_int* s)
+{
+    word32 idx = 0;
+    word32 rSz;                           /* encoding size */
+    word32 sSz;
+    word32 headerSz = 4;   /* 2*ASN_TAG + 2*LEN(ENUM) */
+
+    /* If the leading bit on the INTEGER is a 1, add a leading zero */
+    int rLeadingZero = mp_leading_bit(r);
+    int sLeadingZero = mp_leading_bit(s);
+    int rLen = mp_unsigned_bin_size(r);   /* big int size */
+    int sLen = mp_unsigned_bin_size(s);
+    int err;
+
+    if (*outLen < (rLen + rLeadingZero + sLen + sLeadingZero +
+                   headerSz + 2))  /* SEQ_TAG + LEN(ENUM) */
+        return BAD_FUNC_ARG;
+
+    idx = SetSequence(rLen+rLeadingZero+sLen+sLeadingZero+headerSz, out);
+
+    /* store r */
+    out[idx++] = ASN_INTEGER;
+    rSz = SetLength(rLen + rLeadingZero, &out[idx]);
+    idx += rSz;
+    if (rLeadingZero)
+        out[idx++] = 0;
+    err = mp_to_unsigned_bin(r, &out[idx]);
+    if (err != MP_OKAY) return err;
+    idx += rLen;
+
+    /* store s */
+    out[idx++] = ASN_INTEGER;
+    sSz = SetLength(sLen + sLeadingZero, &out[idx]);
+    idx += sSz;
+    if (sLeadingZero)
+        out[idx++] = 0;
+    err = mp_to_unsigned_bin(s, &out[idx]);
+    if (err != MP_OKAY) return err;
+    idx += sLen;
+
+    *outLen = idx;
+
+    return 0;
+}
+
+
+/* Der Decode ECC-DSA Signautre, r & s stored as big ints */
+int DecodeECC_DSA_Sig(const byte* sig, word32 sigLen, mp_int* r, mp_int* s)
+{
+    word32 idx = 0;
+    int    len = 0;
+
+    if (GetSequence(sig, &idx, &len, sigLen) < 0)
+        return ASN_ECC_KEY_E;
+
+    if ((word32)len > (sigLen - idx))
+        return ASN_ECC_KEY_E;
+
+    if (GetInt(r, sig, &idx, sigLen) < 0)
+        return ASN_ECC_KEY_E;
+
+    if (GetInt(s, sig, &idx, sigLen) < 0)
+        return ASN_ECC_KEY_E;
+
+    return 0;
+}
+
+
+int wc_EccPrivateKeyDecode(const byte* input, word32* inOutIdx, ecc_key* key,
+                        word32 inSz)
+{
+    word32 oid = 0;
+    int    version, length;
+    int    privSz, pubSz;
+    byte   b;
+    int    ret = 0;
+#ifdef WOLFSSL_SMALL_STACK
+    byte* priv;
+    byte* pub;
+#else
+    byte priv[ECC_MAXSIZE];
+    byte pub[ECC_MAXSIZE * 2 + 1]; /* public key has two parts plus header */
+#endif
+
+    if (input == NULL || inOutIdx == NULL || key == NULL || inSz == 0)
+        return BAD_FUNC_ARG;
+
+    if (GetSequence(input, inOutIdx, &length, inSz) < 0)
+        return ASN_PARSE_E;
+
+    if (GetMyVersion(input, inOutIdx, &version) < 0)
+        return ASN_PARSE_E;
+
+    b = input[*inOutIdx];
+    *inOutIdx += 1;
+
+    /* priv type */
+    if (b != 4 && b != 6 && b != 7) 
+        return ASN_PARSE_E;
+
+    if (GetLength(input, inOutIdx, &length, inSz) < 0)
+        return ASN_PARSE_E;
+
+    if (length > ECC_MAXSIZE)
+        return BUFFER_E;
+
+#ifdef WOLFSSL_SMALL_STACK
+    priv = (byte*)XMALLOC(ECC_MAXSIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (priv == NULL)
+        return MEMORY_E;
+    
+    pub = (byte*)XMALLOC(ECC_MAXSIZE * 2 + 1, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (pub == NULL) {
+        XFREE(priv, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        return MEMORY_E;
+    }
+#endif
+
+    /* priv key */
+    privSz = length;
+    XMEMCPY(priv, &input[*inOutIdx], privSz);
+    *inOutIdx += length;
+
+    /* prefix 0, may have */
+    b = input[*inOutIdx];
+    if (b == ECC_PREFIX_0) {
+        *inOutIdx += 1;
+
+        if (GetLength(input, inOutIdx, &length, inSz) < 0)
+            ret = ASN_PARSE_E;
+        else {
+            /* object id */
+            b = input[*inOutIdx];
+            *inOutIdx += 1;
+
+            if (b != ASN_OBJECT_ID) {
+                ret = ASN_OBJECT_ID_E;
+            }
+            else if (GetLength(input, inOutIdx, &length, inSz) < 0) {
+                ret = ASN_PARSE_E;
+            }
+            else {
+                while(length--) {
+                    oid += input[*inOutIdx];
+                    *inOutIdx += 1;
+                }
+                if (CheckCurve(oid) < 0)
+                    ret = ECC_CURVE_OID_E;
+            }
+        }
+    }
+
+    if (ret == 0) {
+        /* prefix 1 */
+        b = input[*inOutIdx];
+        *inOutIdx += 1;
+
+        if (b != ECC_PREFIX_1) {
+            ret = ASN_ECC_KEY_E;
+        }
+        else if (GetLength(input, inOutIdx, &length, inSz) < 0) {
+            ret = ASN_PARSE_E;
+        }
+        else {
+            /* key header */
+            b = input[*inOutIdx];
+            *inOutIdx += 1;
+            
+            if (b != ASN_BIT_STRING) {
+                ret = ASN_BITSTR_E;
+            }
+            else if (GetLength(input, inOutIdx, &length, inSz) < 0) {
+                ret = ASN_PARSE_E;
+            }
+            else {
+                b = input[*inOutIdx];
+                *inOutIdx += 1;
+
+                if (b != 0x00) {
+                    ret = ASN_EXPECT_0_E;
+                }
+                else {
+                    /* pub key */
+                    pubSz = length - 1;  /* null prefix */
+                    if (pubSz < (ECC_MAXSIZE*2 + 1)) {
+                        XMEMCPY(pub, &input[*inOutIdx], pubSz);
+                        *inOutIdx += length;
+                        ret = wc_ecc_import_private_key(priv, privSz, pub, pubSz,
+                                                     key);
+                    } else
+                        ret = BUFFER_E;
+                }
+            }
+        }
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(priv, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(pub,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+
+#ifdef WOLFSSL_KEY_GEN
+
+/* Write a Private ecc key to DER format, length on success else < 0 */
+int wc_EccKeyToDer(ecc_key* key, byte* output, word32 inLen)
+{
+    byte   curve[MAX_ALGO_SZ];
+    byte   ver[MAX_VERSION_SZ];
+    byte   seq[MAX_SEQ_SZ];
+    int    ret;
+    int    curveSz;
+    int    verSz;
+    int    privHdrSz  = ASN_ECC_HEADER_SZ;
+    int    pubHdrSz   = ASN_ECC_CONTEXT_SZ + ASN_ECC_HEADER_SZ;
+    int    curveHdrSz = ASN_ECC_CONTEXT_SZ;
+    word32 seqSz;
+    word32 idx = 0;
+    word32 pubSz = ECC_BUFSIZE;
+    word32 privSz;
+    word32 totalSz;
+
+    if (key == NULL || output == NULL || inLen == 0)
+        return BAD_FUNC_ARG;
+
+    ret = wc_ecc_export_x963(key, NULL, &pubSz);
+    if (ret != LENGTH_ONLY_E) {
+        return ret;
+    }
+    curveSz = SetCurve(key, curve);
+    if (curveSz < 0) {
+        return curveSz;
+    }
+
+    privSz = key->dp->size;
+
+    verSz = SetMyVersion(1, ver, FALSE);
+    if (verSz < 0) {
+        return verSz;
+    }
+
+    totalSz = verSz + privSz + privHdrSz + curveSz + curveHdrSz +
+              pubSz + pubHdrSz + 1;  /* plus null byte b4 public */
+    seqSz = SetSequence(totalSz, seq);
+    totalSz += seqSz;
+
+    if (totalSz > inLen) {
+        return BUFFER_E;
+    }
+
+    /* write it out */
+    /* seq */
+    XMEMCPY(output + idx, seq, seqSz);
+    idx += seqSz;
+
+   /* ver */
+    XMEMCPY(output + idx, ver, verSz);
+    idx += verSz;
+
+    /* private */
+    output[idx++] = ASN_OCTET_STRING;
+    output[idx++] = (byte)privSz;
+    ret = wc_ecc_export_private_only(key, output + idx, &privSz);
+    if (ret < 0) {
+        return ret;
+    }
+    idx += privSz;
+
+    /* curve */
+    output[idx++] = ECC_PREFIX_0;
+    output[idx++] = (byte)curveSz;
+    XMEMCPY(output + idx, curve, curveSz);
+    idx += curveSz;
+
+    /* public */
+    output[idx++] = ECC_PREFIX_1;
+    output[idx++] = (byte)pubSz + ASN_ECC_CONTEXT_SZ + 1;  /* plus null byte */
+    output[idx++] = ASN_BIT_STRING;
+    output[idx++] = (byte)pubSz + 1;  /* plus null byte */
+    output[idx++] = (byte)0;          /* null byte */
+    ret = wc_ecc_export_x963(key, output + idx, &pubSz);
+    if (ret != 0) {
+        return ret;
+    }
+    /* idx += pubSz if do more later */
+
+    return totalSz;
+}
+
+#endif /* WOLFSSL_KEY_GEN */
+
+#endif  /* HAVE_ECC */
+
+
+#if defined(HAVE_OCSP) || defined(HAVE_CRL)
+
+/* Get raw Date only, no processing, 0 on success */
+static int GetBasicDate(const byte* source, word32* idx, byte* date,
+                        byte* format, int maxIdx)
+{
+    int    length;
+
+    WOLFSSL_ENTER("GetBasicDate");
+
+    *format = source[*idx];
+    *idx += 1;
+    if (*format != ASN_UTC_TIME && *format != ASN_GENERALIZED_TIME)
+        return ASN_TIME_E;
+
+    if (GetLength(source, idx, &length, maxIdx) < 0)
+        return ASN_PARSE_E;
+
+    if (length > MAX_DATE_SIZE || length < MIN_DATE_SIZE)
+        return ASN_DATE_SZ_E;
+
+    XMEMCPY(date, &source[*idx], length);
+    *idx += length;
+
+    return 0;
+}
+
+#endif
+
+
+#ifdef HAVE_OCSP
+
+static int GetEnumerated(const byte* input, word32* inOutIdx, int *value)
+{
+    word32 idx = *inOutIdx;
+    word32 len;
+
+    WOLFSSL_ENTER("GetEnumerated");
+
+    *value = 0;
+
+    if (input[idx++] != ASN_ENUMERATED)
+        return ASN_PARSE_E;
+
+    len = input[idx++];
+    if (len > 4)
+        return ASN_PARSE_E;
+
+    while (len--) {
+        *value  = *value << 8 | input[idx++];
+    }
+
+    *inOutIdx = idx;
+
+    return *value;
+}
+
+
+static int DecodeSingleResponse(byte* source,
+                            word32* ioIndex, OcspResponse* resp, word32 size)
+{
+    word32 idx = *ioIndex, prevIndex, oid;
+    int length, wrapperSz;
+    CertStatus* cs = resp->status;
+
+    WOLFSSL_ENTER("DecodeSingleResponse");
+
+    /* Outer wrapper of the SEQUENCE OF Single Responses. */
+    if (GetSequence(source, &idx, &wrapperSz, size) < 0)
+        return ASN_PARSE_E;
+
+    prevIndex = idx;
+
+    /* When making a request, we only request one status on one certificate
+     * at a time. There should only be one SingleResponse */
+
+    /* Wrapper around the Single Response */
+    if (GetSequence(source, &idx, &length, size) < 0)
+        return ASN_PARSE_E;
+
+    /* Wrapper around the CertID */
+    if (GetSequence(source, &idx, &length, size) < 0)
+        return ASN_PARSE_E;
+    /* Skip the hash algorithm */
+    if (GetAlgoId(source, &idx, &oid, size) < 0)
+        return ASN_PARSE_E;
+    /* Save reference to the hash of CN */
+    if (source[idx++] != ASN_OCTET_STRING)
+        return ASN_PARSE_E;
+    if (GetLength(source, &idx, &length, size) < 0)
+        return ASN_PARSE_E;
+    resp->issuerHash = source + idx;
+    idx += length;
+    /* Save reference to the hash of the issuer public key */
+    if (source[idx++] != ASN_OCTET_STRING)
+        return ASN_PARSE_E;
+    if (GetLength(source, &idx, &length, size) < 0)
+        return ASN_PARSE_E;
+    resp->issuerKeyHash = source + idx;
+    idx += length;
+
+    /* Read the serial number, it is handled as a string, not as a 
+     * proper number. Just XMEMCPY the data over, rather than load it
+     * as an mp_int. */
+    if (source[idx++] != ASN_INTEGER)
+        return ASN_PARSE_E;
+    if (GetLength(source, &idx, &length, size) < 0)
+        return ASN_PARSE_E;
+    if (length <= EXTERNAL_SERIAL_SIZE)
+    {
+        if (source[idx] == 0)
+        {
+            idx++;
+            length--;
+        }
+        XMEMCPY(cs->serial, source + idx, length);
+        cs->serialSz = length;
+    }
+    else
+    {
+        return ASN_GETINT_E;
+    }
+    idx += length;
+
+    /* CertStatus */
+    switch (source[idx++])
+    {
+        case (ASN_CONTEXT_SPECIFIC | CERT_GOOD):
+            cs->status = CERT_GOOD;
+            idx++;
+            break;
+        case (ASN_CONTEXT_SPECIFIC | ASN_CONSTRUCTED | CERT_REVOKED):
+            cs->status = CERT_REVOKED;
+            if (GetLength(source, &idx, &length, size) < 0)
+                return ASN_PARSE_E;
+            idx += length;
+            break;
+        case (ASN_CONTEXT_SPECIFIC | CERT_UNKNOWN):
+            cs->status = CERT_UNKNOWN;
+            idx++;
+            break;
+        default:
+            return ASN_PARSE_E;
+    }
+
+    if (GetBasicDate(source, &idx, cs->thisDate,
+                                                &cs->thisDateFormat, size) < 0)
+        return ASN_PARSE_E;
+    if (!XVALIDATE_DATE(cs->thisDate, cs->thisDateFormat, BEFORE))
+        return ASN_BEFORE_DATE_E;
+    
+    /* The following items are optional. Only check for them if there is more
+     * unprocessed data in the singleResponse wrapper. */
+    
+    if (((int)(idx - prevIndex) < wrapperSz) &&
+        (source[idx] == (ASN_CONSTRUCTED | ASN_CONTEXT_SPECIFIC | 0)))
+    {
+        idx++;
+        if (GetLength(source, &idx, &length, size) < 0)
+            return ASN_PARSE_E;
+        if (GetBasicDate(source, &idx, cs->nextDate,
+                                                &cs->nextDateFormat, size) < 0)
+            return ASN_PARSE_E;
+    }
+    if (((int)(idx - prevIndex) < wrapperSz) &&
+        (source[idx] == (ASN_CONSTRUCTED | ASN_CONTEXT_SPECIFIC | 1)))
+    {
+        idx++;
+        if (GetLength(source, &idx, &length, size) < 0)
+            return ASN_PARSE_E;
+        idx += length;
+    }
+
+    *ioIndex = idx;
+
+    return 0;
+}
+
+static int DecodeOcspRespExtensions(byte* source,
+                            word32* ioIndex, OcspResponse* resp, word32 sz)
+{
+    word32 idx = *ioIndex;
+    int length;
+    int ext_bound; /* boundary index for the sequence of extensions */
+    word32 oid;
+
+    WOLFSSL_ENTER("DecodeOcspRespExtensions");
+
+    if (source[idx++] != (ASN_CONSTRUCTED | ASN_CONTEXT_SPECIFIC | 1))
+        return ASN_PARSE_E;
+
+    if (GetLength(source, &idx, &length, sz) < 0) return ASN_PARSE_E;
+
+    if (GetSequence(source, &idx, &length, sz) < 0) return ASN_PARSE_E;
+   
+    ext_bound = idx + length;
+
+    while (idx < (word32)ext_bound) {
+        if (GetSequence(source, &idx, &length, sz) < 0) {
+            WOLFSSL_MSG("\tfail: should be a SEQUENCE");
+            return ASN_PARSE_E;
+        }
+
+        oid = 0;
+        if (GetObjectId(source, &idx, &oid, sz) < 0) {
+            WOLFSSL_MSG("\tfail: OBJECT ID");
+            return ASN_PARSE_E;
+        }
+
+        /* check for critical flag */
+        if (source[idx] == ASN_BOOLEAN) {
+            WOLFSSL_MSG("\tfound optional critical flag, moving past");
+            idx += (ASN_BOOL_SIZE + 1);
+        }
+
+        /* process the extension based on the OID */
+        if (source[idx++] != ASN_OCTET_STRING) {
+            WOLFSSL_MSG("\tfail: should be an OCTET STRING");
+            return ASN_PARSE_E;
+        }
+
+        if (GetLength(source, &idx, &length, sz) < 0) {
+            WOLFSSL_MSG("\tfail: extension data length");
+            return ASN_PARSE_E;
+        }
+
+        if (oid == OCSP_NONCE_OID) {
+            resp->nonce = source + idx;
+            resp->nonceSz = length;
+        }
+
+        idx += length;
+    }
+
+    *ioIndex = idx;
+    return 0;
+}
+
+
+static int DecodeResponseData(byte* source,
+                            word32* ioIndex, OcspResponse* resp, word32 size)
+{
+    word32 idx = *ioIndex, prev_idx;
+    int length;
+    int version;
+    word32 responderId = 0;
+
+    WOLFSSL_ENTER("DecodeResponseData");
+
+    resp->response = source + idx;
+    prev_idx = idx;
+    if (GetSequence(source, &idx, &length, size) < 0)
+        return ASN_PARSE_E;
+    resp->responseSz = length + idx - prev_idx;
+
+    /* Get version. It is an EXPLICIT[0] DEFAULT(0) value. If this
+     * item isn't an EXPLICIT[0], then set version to zero and move
+     * onto the next item.
+     */
+    if (source[idx] == (ASN_CONTEXT_SPECIFIC | ASN_CONSTRUCTED))
+    {    
+        idx += 2; /* Eat the value and length */
+        if (GetMyVersion(source, &idx, &version) < 0)
+            return ASN_PARSE_E;
+    } else
+        version = 0;
+
+    responderId = source[idx++];
+    if ((responderId == (ASN_CONTEXT_SPECIFIC | ASN_CONSTRUCTED | 1)) ||
+        (responderId == (ASN_CONTEXT_SPECIFIC | ASN_CONSTRUCTED | 2)))
+    {
+        if (GetLength(source, &idx, &length, size) < 0)
+            return ASN_PARSE_E;
+        idx += length;
+    }
+    else
+        return ASN_PARSE_E;
+    
+    /* save pointer to the producedAt time */
+    if (GetBasicDate(source, &idx, resp->producedDate,
+                                        &resp->producedDateFormat, size) < 0)
+        return ASN_PARSE_E;
+
+    if (DecodeSingleResponse(source, &idx, resp, size) < 0)
+        return ASN_PARSE_E;
+
+    if (DecodeOcspRespExtensions(source, &idx, resp, size) < 0)
+        return ASN_PARSE_E;
+
+    *ioIndex = idx;
+    return 0;
+}
+
+
+static int DecodeCerts(byte* source,
+                            word32* ioIndex, OcspResponse* resp, word32 size)
+{
+    word32 idx = *ioIndex;
+
+    WOLFSSL_ENTER("DecodeCerts");
+
+    if (source[idx++] == (ASN_CONSTRUCTED | ASN_CONTEXT_SPECIFIC))
+    {
+        int length;
+
+        if (GetLength(source, &idx, &length, size) < 0)
+            return ASN_PARSE_E;
+
+        if (GetSequence(source, &idx, &length, size) < 0)
+            return ASN_PARSE_E;
+
+        resp->cert = source + idx;
+        resp->certSz = length;
+
+        idx += length;
+    }
+    *ioIndex = idx;
+    return 0;
+}
+
+static int DecodeBasicOcspResponse(byte* source,
+                            word32* ioIndex, OcspResponse* resp, word32 size)
+{
+    int length;
+    word32 idx = *ioIndex;
+    word32 end_index;
+
+    WOLFSSL_ENTER("DecodeBasicOcspResponse");
+
+    if (GetSequence(source, &idx, &length, size) < 0)
+        return ASN_PARSE_E;
+
+    if (idx + length > size)
+        return ASN_INPUT_E;
+    end_index = idx + length;
+
+    if (DecodeResponseData(source, &idx, resp, size) < 0)
+        return ASN_PARSE_E;
+    
+    /* Get the signature algorithm */
+    if (GetAlgoId(source, &idx, &resp->sigOID, size) < 0)
+        return ASN_PARSE_E;
+
+    /* Obtain pointer to the start of the signature, and save the size */
+    if (source[idx++] == ASN_BIT_STRING)
+    {
+        int sigLength = 0;
+        if (GetLength(source, &idx, &sigLength, size) < 0)
+            return ASN_PARSE_E;
+        resp->sigSz = sigLength;
+        resp->sig = source + idx;
+        idx += sigLength;
+    }
+
+    /*
+     * Check the length of the BasicOcspResponse against the current index to
+     * see if there are certificates, they are optional.
+     */
+    if (idx < end_index)
+    {
+        DecodedCert cert;
+        int ret;
+
+        if (DecodeCerts(source, &idx, resp, size) < 0)
+            return ASN_PARSE_E;
+
+        InitDecodedCert(&cert, resp->cert, resp->certSz, 0);
+        ret = ParseCertRelative(&cert, CA_TYPE, NO_VERIFY, 0);
+        if (ret < 0)
+            return ret;
+
+        ret = ConfirmSignature(resp->response, resp->responseSz,
+                            cert.publicKey, cert.pubKeySize, cert.keyOID,
+                            resp->sig, resp->sigSz, resp->sigOID, NULL);
+        FreeDecodedCert(&cert);
+
+        if (ret == 0)
+        {
+            WOLFSSL_MSG("\tOCSP Confirm signature failed");
+            return ASN_OCSP_CONFIRM_E;
+        }
+    }
+
+    *ioIndex = idx;
+    return 0;
+}
+
+
+void InitOcspResponse(OcspResponse* resp, CertStatus* status,
+                                                    byte* source, word32 inSz)
+{
+    WOLFSSL_ENTER("InitOcspResponse");
+
+    resp->responseStatus = -1;
+    resp->response = NULL;
+    resp->responseSz = 0;
+    resp->producedDateFormat = 0;
+    resp->issuerHash = NULL;
+    resp->issuerKeyHash = NULL;
+    resp->sig = NULL;
+    resp->sigSz = 0;
+    resp->sigOID = 0;
+    resp->status = status;
+    resp->nonce = NULL;
+    resp->nonceSz = 0;
+    resp->source = source;
+    resp->maxIdx = inSz;
+}
+
+
+int OcspResponseDecode(OcspResponse* resp)
+{
+    int length = 0;
+    word32 idx = 0;
+    byte* source = resp->source;
+    word32 size = resp->maxIdx;
+    word32 oid;
+
+    WOLFSSL_ENTER("OcspResponseDecode");
+
+    /* peel the outer SEQUENCE wrapper */
+    if (GetSequence(source, &idx, &length, size) < 0)
+        return ASN_PARSE_E;
+    
+    /* First get the responseStatus, an ENUMERATED */
+    if (GetEnumerated(source, &idx, &resp->responseStatus) < 0)
+        return ASN_PARSE_E;
+
+    if (resp->responseStatus != OCSP_SUCCESSFUL)
+        return 0;
+
+    /* Next is an EXPLICIT record called ResponseBytes, OPTIONAL */
+    if (idx >= size)
+        return ASN_INPUT_E;
+    if (source[idx++] != (ASN_CONSTRUCTED | ASN_CONTEXT_SPECIFIC))
+        return ASN_PARSE_E;
+    if (GetLength(source, &idx, &length, size) < 0)
+        return ASN_PARSE_E;
+
+    /* Get the responseBytes SEQUENCE */
+    if (GetSequence(source, &idx, &length, size) < 0)
+        return ASN_PARSE_E;
+
+    /* Check ObjectID for the resposeBytes */
+    if (GetObjectId(source, &idx, &oid, size) < 0)
+        return ASN_PARSE_E;
+    if (oid != OCSP_BASIC_OID)
+        return ASN_PARSE_E;
+    if (source[idx++] != ASN_OCTET_STRING)
+        return ASN_PARSE_E;
+
+    if (GetLength(source, &idx, &length, size) < 0)
+        return ASN_PARSE_E;
+
+    if (DecodeBasicOcspResponse(source, &idx, resp, size) < 0)
+        return ASN_PARSE_E;
+    
+    return 0;
+}
+
+
+static word32 SetOcspReqExtensions(word32 extSz, byte* output,
+                                            const byte* nonce, word32 nonceSz)
+{
+    static const byte NonceObjId[] = { 0x2b, 0x06, 0x01, 0x05, 0x05, 0x07,
+                                       0x30, 0x01, 0x02 };
+    byte seqArray[5][MAX_SEQ_SZ];
+    word32 seqSz[5], totalSz;
+
+    WOLFSSL_ENTER("SetOcspReqExtensions");
+
+    if (nonce == NULL || nonceSz == 0) return 0;
+    
+    seqArray[0][0] = ASN_OCTET_STRING;
+    seqSz[0] = 1 + SetLength(nonceSz, &seqArray[0][1]);
+
+    seqArray[1][0] = ASN_OBJECT_ID;
+    seqSz[1] = 1 + SetLength(sizeof(NonceObjId), &seqArray[1][1]);
+
+    totalSz = seqSz[0] + seqSz[1] + nonceSz + (word32)sizeof(NonceObjId);
+
+    seqSz[2] = SetSequence(totalSz, seqArray[2]);
+    totalSz += seqSz[2];
+
+    seqSz[3] = SetSequence(totalSz, seqArray[3]);
+    totalSz += seqSz[3];
+
+    seqArray[4][0] = (ASN_CONSTRUCTED | ASN_CONTEXT_SPECIFIC | 2);
+    seqSz[4] = 1 + SetLength(totalSz, &seqArray[4][1]);
+    totalSz += seqSz[4];
+
+    if (totalSz < extSz)
+    {
+        totalSz = 0;
+        XMEMCPY(output + totalSz, seqArray[4], seqSz[4]);
+        totalSz += seqSz[4];
+        XMEMCPY(output + totalSz, seqArray[3], seqSz[3]);
+        totalSz += seqSz[3];
+        XMEMCPY(output + totalSz, seqArray[2], seqSz[2]);
+        totalSz += seqSz[2];
+        XMEMCPY(output + totalSz, seqArray[1], seqSz[1]);
+        totalSz += seqSz[1];
+        XMEMCPY(output + totalSz, NonceObjId, sizeof(NonceObjId));
+        totalSz += (word32)sizeof(NonceObjId);
+        XMEMCPY(output + totalSz, seqArray[0], seqSz[0]);
+        totalSz += seqSz[0];
+        XMEMCPY(output + totalSz, nonce, nonceSz);
+        totalSz += nonceSz;
+    }
+
+    return totalSz;
+}
+
+
+int EncodeOcspRequest(OcspRequest* req)
+{
+    byte seqArray[5][MAX_SEQ_SZ];
+    /* The ASN.1 of the OCSP Request is an onion of sequences */
+    byte algoArray[MAX_ALGO_SZ];
+    byte issuerArray[MAX_ENCODED_DIG_SZ];
+    byte issuerKeyArray[MAX_ENCODED_DIG_SZ];
+    byte snArray[MAX_SN_SZ];
+    byte extArray[MAX_OCSP_EXT_SZ];
+    byte* output = req->dest;
+    word32 seqSz[5], algoSz, issuerSz, issuerKeySz, snSz, extSz, totalSz;
+    int i;
+
+    WOLFSSL_ENTER("EncodeOcspRequest");
+
+#ifdef NO_SHA
+    algoSz = SetAlgoID(SHA256h, algoArray, hashType, 0);
+#else
+    algoSz = SetAlgoID(SHAh, algoArray, hashType, 0);
+#endif
+
+    req->issuerHash = req->cert->issuerHash;
+    issuerSz = SetDigest(req->cert->issuerHash, KEYID_SIZE, issuerArray);
+
+    req->issuerKeyHash = req->cert->issuerKeyHash;
+    issuerKeySz = SetDigest(req->cert->issuerKeyHash,
+                                                    KEYID_SIZE, issuerKeyArray);
+
+    req->serial = req->cert->serial;
+    req->serialSz = req->cert->serialSz;
+    snSz = SetSerialNumber(req->cert->serial, req->cert->serialSz, snArray);
+
+    extSz = 0;
+    if (req->useNonce) {
+        RNG rng;
+        if (wc_InitRng(&rng) != 0) {
+            WOLFSSL_MSG("\tCannot initialize RNG. Skipping the OSCP Nonce.");
+        } else {
+            if (wc_RNG_GenerateBlock(&rng, req->nonce, MAX_OCSP_NONCE_SZ) != 0)
+                WOLFSSL_MSG("\tCannot run RNG. Skipping the OSCP Nonce.");
+            else {
+                req->nonceSz = MAX_OCSP_NONCE_SZ;
+                extSz = SetOcspReqExtensions(MAX_OCSP_EXT_SZ, extArray,
+                                                      req->nonce, req->nonceSz);
+            }
+            wc_FreeRng(&rng);
+        }
+    }
+
+    totalSz = algoSz + issuerSz + issuerKeySz + snSz;
+
+    for (i = 4; i >= 0; i--) {
+        seqSz[i] = SetSequence(totalSz, seqArray[i]);
+        totalSz += seqSz[i];
+        if (i == 2) totalSz += extSz;
+    }
+    totalSz = 0;
+    for (i = 0; i < 5; i++) {
+        XMEMCPY(output + totalSz, seqArray[i], seqSz[i]);
+        totalSz += seqSz[i];
+    }
+    XMEMCPY(output + totalSz, algoArray, algoSz);
+    totalSz += algoSz;
+    XMEMCPY(output + totalSz, issuerArray, issuerSz);
+    totalSz += issuerSz;
+    XMEMCPY(output + totalSz, issuerKeyArray, issuerKeySz);
+    totalSz += issuerKeySz;
+    XMEMCPY(output + totalSz, snArray, snSz);
+    totalSz += snSz;
+    if (extSz != 0) {
+        XMEMCPY(output + totalSz, extArray, extSz);
+        totalSz += extSz;
+    }
+
+    return totalSz;
+}
+
+
+void InitOcspRequest(OcspRequest* req, DecodedCert* cert, byte useNonce,
+                                                    byte* dest, word32 destSz)
+{
+    WOLFSSL_ENTER("InitOcspRequest");
+
+    req->cert = cert;
+    req->useNonce = useNonce;
+    req->nonceSz = 0;
+    req->issuerHash = NULL;
+    req->issuerKeyHash = NULL;
+    req->serial = NULL;
+    req->dest = dest;
+    req->destSz = destSz;
+}
+
+
+int CompareOcspReqResp(OcspRequest* req, OcspResponse* resp)
+{
+    int cmp;
+
+    WOLFSSL_ENTER("CompareOcspReqResp");
+
+    if (req == NULL)
+    {
+        WOLFSSL_MSG("\tReq missing");
+        return -1;
+    }
+
+    if (resp == NULL)
+    {
+        WOLFSSL_MSG("\tResp missing");
+        return 1;
+    }
+
+    /* Nonces are not critical. The responder may not necessarily add
+     * the nonce to the response. */
+    if (req->useNonce && resp->nonceSz != 0) {
+        cmp = req->nonceSz - resp->nonceSz;
+        if (cmp != 0)
+        {
+            WOLFSSL_MSG("\tnonceSz mismatch");
+            return cmp;
+        }
+    
+        cmp = XMEMCMP(req->nonce, resp->nonce, req->nonceSz);
+        if (cmp != 0)
+        {
+            WOLFSSL_MSG("\tnonce mismatch");
+            return cmp;
+        }
+    }
+
+    cmp = XMEMCMP(req->issuerHash, resp->issuerHash, KEYID_SIZE);
+    if (cmp != 0)
+    {
+        WOLFSSL_MSG("\tissuerHash mismatch");
+        return cmp;
+    }
+
+    cmp = XMEMCMP(req->issuerKeyHash, resp->issuerKeyHash, KEYID_SIZE);
+    if (cmp != 0)
+    {
+        WOLFSSL_MSG("\tissuerKeyHash mismatch");
+        return cmp;
+    }
+
+    cmp = req->serialSz - resp->status->serialSz;
+    if (cmp != 0)
+    {
+        WOLFSSL_MSG("\tserialSz mismatch");
+        return cmp;
+    }
+
+    cmp = XMEMCMP(req->serial, resp->status->serial, req->serialSz);
+    if (cmp != 0)
+    {
+        WOLFSSL_MSG("\tserial mismatch");
+        return cmp;
+    }
+
+    return 0;
+}
+
+#endif
+
+
+/* store SHA hash of NAME */
+WOLFSSL_LOCAL int GetNameHash(const byte* source, word32* idx, byte* hash,
+                             int maxIdx)
+{
+    int    length;  /* length of all distinguished names */
+    int    ret;
+    word32 dummy;
+
+    WOLFSSL_ENTER("GetNameHash");
+
+    if (source[*idx] == ASN_OBJECT_ID) {
+        WOLFSSL_MSG("Trying optional prefix...");
+
+        if (GetLength(source, idx, &length, maxIdx) < 0)
+            return ASN_PARSE_E;
+
+        *idx += length;
+        WOLFSSL_MSG("Got optional prefix");
+    }
+
+    /* For OCSP, RFC2560 section 4.1.1 states the issuer hash should be
+     * calculated over the entire DER encoding of the Name field, including
+     * the tag and length. */
+    dummy = *idx;
+    if (GetSequence(source, idx, &length, maxIdx) < 0)
+        return ASN_PARSE_E;
+
+#ifdef NO_SHA
+    ret = wc_Sha256Hash(source + dummy, length + *idx - dummy, hash);
+#else
+    ret = wc_ShaHash(source + dummy, length + *idx - dummy, hash);
+#endif
+
+    *idx += length;
+
+    return ret;
+}
+
+
+#ifdef HAVE_CRL
+
+/* initialize decoded CRL */
+void InitDecodedCRL(DecodedCRL* dcrl)
+{
+    WOLFSSL_MSG("InitDecodedCRL");
+
+    dcrl->certBegin    = 0;
+    dcrl->sigIndex     = 0;
+    dcrl->sigLength    = 0;
+    dcrl->signatureOID = 0;
+    dcrl->certs        = NULL;
+    dcrl->totalCerts   = 0;
+}
+
+
+/* free decoded CRL resources */
+void FreeDecodedCRL(DecodedCRL* dcrl)
+{
+    RevokedCert* tmp = dcrl->certs;
+
+    WOLFSSL_MSG("FreeDecodedCRL");
+
+    while(tmp) {
+        RevokedCert* next = tmp->next;
+        XFREE(tmp, NULL, DYNAMIC_TYPE_REVOKED);
+        tmp = next;
+    }
+}
+
+
+/* Get Revoked Cert list, 0 on success */
+static int GetRevoked(const byte* buff, word32* idx, DecodedCRL* dcrl,
+                      int maxIdx)
+{
+    int    len;
+    word32 end;
+    byte   b;
+    RevokedCert* rc;
+
+    WOLFSSL_ENTER("GetRevoked");
+
+    if (GetSequence(buff, idx, &len, maxIdx) < 0)
+        return ASN_PARSE_E;
+
+    end = *idx + len;
+
+    /* get serial number */
+    b = buff[*idx];
+    *idx += 1;
+
+    if (b != ASN_INTEGER) {
+        WOLFSSL_MSG("Expecting Integer");
+        return ASN_PARSE_E;
+    }
+
+    if (GetLength(buff, idx, &len, maxIdx) < 0)
+        return ASN_PARSE_E;
+
+    if (len > EXTERNAL_SERIAL_SIZE) {
+        WOLFSSL_MSG("Serial Size too big");
+        return ASN_PARSE_E;
+    }
+
+    rc = (RevokedCert*)XMALLOC(sizeof(RevokedCert), NULL, DYNAMIC_TYPE_CRL);
+    if (rc == NULL) {
+        WOLFSSL_MSG("Alloc Revoked Cert failed");
+        return MEMORY_E;
+    }
+
+    XMEMCPY(rc->serialNumber, &buff[*idx], len);
+    rc->serialSz = len;
+
+    /* add to list */
+    rc->next = dcrl->certs;
+    dcrl->certs = rc;
+    dcrl->totalCerts++;
+
+    *idx += len;
+
+    /* get date */
+    b = buff[*idx];
+    *idx += 1;
+
+    if (b != ASN_UTC_TIME && b != ASN_GENERALIZED_TIME) {
+        WOLFSSL_MSG("Expecting Date");
+        return ASN_PARSE_E;
+    }
+
+    if (GetLength(buff, idx, &len, maxIdx) < 0)
+        return ASN_PARSE_E;
+
+    /* skip for now */
+    *idx += len;
+
+    if (*idx != end)  /* skip extensions */
+        *idx = end;
+
+    return 0;
+}
+
+
+/* Get CRL Signature, 0 on success */
+static int GetCRL_Signature(const byte* source, word32* idx, DecodedCRL* dcrl,
+                            int maxIdx)
+{
+    int    length;
+    byte   b;
+
+    WOLFSSL_ENTER("GetCRL_Signature");
+
+    b = source[*idx];
+    *idx += 1;
+    if (b != ASN_BIT_STRING)
+        return ASN_BITSTR_E;
+
+    if (GetLength(source, idx, &length, maxIdx) < 0)
+        return ASN_PARSE_E;
+
+    dcrl->sigLength = length;
+
+    b = source[*idx];
+    *idx += 1;
+    if (b != 0x00)
+        return ASN_EXPECT_0_E;
+
+    dcrl->sigLength--;
+    dcrl->signature = (byte*)&source[*idx];
+
+    *idx += dcrl->sigLength;
+
+    return 0;
+}
+
+
+/* prase crl buffer into decoded state, 0 on success */
+int ParseCRL(DecodedCRL* dcrl, const byte* buff, word32 sz, void* cm)
+{
+    int     version, len;
+    word32  oid, idx = 0;
+    Signer* ca = NULL;
+
+    WOLFSSL_MSG("ParseCRL");
+
+    /* raw crl hash */
+    /* hash here if needed for optimized comparisons
+     * Sha     sha;
+     * wc_InitSha(&sha);
+     * wc_ShaUpdate(&sha, buff, sz);
+     * wc_ShaFinal(&sha, dcrl->crlHash); */
+
+    if (GetSequence(buff, &idx, &len, sz) < 0)
+        return ASN_PARSE_E;
+
+    dcrl->certBegin = idx;
+
+    if (GetSequence(buff, &idx, &len, sz) < 0)
+        return ASN_PARSE_E;
+    dcrl->sigIndex = len + idx;
+
+    /* may have version */
+    if (buff[idx] == ASN_INTEGER) {
+        if (GetMyVersion(buff, &idx, &version) < 0)
+            return ASN_PARSE_E;
+    }
+
+    if (GetAlgoId(buff, &idx, &oid, sz) < 0)
+        return ASN_PARSE_E;
+
+    if (GetNameHash(buff, &idx, dcrl->issuerHash, sz) < 0)
+        return ASN_PARSE_E;
+
+    if (GetBasicDate(buff, &idx, dcrl->lastDate, &dcrl->lastDateFormat, sz) < 0)
+        return ASN_PARSE_E;
+
+    if (GetBasicDate(buff, &idx, dcrl->nextDate, &dcrl->nextDateFormat, sz) < 0)
+        return ASN_PARSE_E;
+
+    if (!XVALIDATE_DATE(dcrl->nextDate, dcrl->nextDateFormat, AFTER)) {
+        WOLFSSL_MSG("CRL after date is no longer valid");
+        return ASN_AFTER_DATE_E;
+    }
+
+    if (idx != dcrl->sigIndex && buff[idx] != CRL_EXTENSIONS) {
+        if (GetSequence(buff, &idx, &len, sz) < 0)
+            return ASN_PARSE_E;
+
+        len += idx;
+
+        while (idx < (word32)len) {
+            if (GetRevoked(buff, &idx, dcrl, sz) < 0)
+                return ASN_PARSE_E;
+        }
+    }
+
+    if (idx != dcrl->sigIndex)
+        idx = dcrl->sigIndex;   /* skip extensions */
+
+    if (GetAlgoId(buff, &idx, &dcrl->signatureOID, sz) < 0)
+        return ASN_PARSE_E;
+
+    if (GetCRL_Signature(buff, &idx, dcrl, sz) < 0)
+        return ASN_PARSE_E;
+
+    /* openssl doesn't add skid by default for CRLs cause firefox chokes
+       we're not assuming it's available yet */
+    #if !defined(NO_SKID) && defined(CRL_SKID_READY)
+        if (dcrl->extAuthKeyIdSet)
+            ca = GetCA(cm, dcrl->extAuthKeyId);
+        if (ca == NULL)
+            ca = GetCAByName(cm, dcrl->issuerHash);
+    #else /* NO_SKID */
+        ca = GetCA(cm, dcrl->issuerHash);
+    #endif /* NO_SKID */
+    WOLFSSL_MSG("About to verify CRL signature");
+
+    if (ca) {
+        WOLFSSL_MSG("Found CRL issuer CA");
+        /* try to confirm/verify signature */
+        #ifndef IGNORE_KEY_EXTENSIONS
+            if ((ca->keyUsage & KEYUSE_CRL_SIGN) == 0) {
+                WOLFSSL_MSG("CA cannot sign CRLs");
+                return ASN_CRL_NO_SIGNER_E;
+            }
+        #endif /* IGNORE_KEY_EXTENSIONS */
+        if (!ConfirmSignature(buff + dcrl->certBegin,
+                dcrl->sigIndex - dcrl->certBegin,
+                ca->publicKey, ca->pubKeySize, ca->keyOID,
+                dcrl->signature, dcrl->sigLength, dcrl->signatureOID, NULL)) {
+            WOLFSSL_MSG("CRL Confirm signature failed");
+            return ASN_CRL_CONFIRM_E;
+        }
+    }
+    else {
+        WOLFSSL_MSG("Did NOT find CRL issuer CA");
+        return ASN_CRL_NO_SIGNER_E;
+    }
+
+    return 0;
+}
+
+#endif /* HAVE_CRL */
+#endif
+
+#ifdef WOLFSSL_SEP
+
+
+
+#endif /* WOLFSSL_SEP */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/blake2b.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/blake2b.c
new file mode 100644
index 0000000..6ae5afd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/blake2b.c
@@ -0,0 +1,433 @@
+/*
+   BLAKE2 reference source code package - reference C implementations
+
+   Written in 2012 by Samuel Neves 
+
+   To the extent possible under law, the author(s) have dedicated all copyright
+   and related and neighboring rights to this software to the public domain
+   worldwide. This software is distributed without any warranty.
+
+   You should have received a copy of the CC0 Public Domain Dedication along with
+   this software. If not, see .
+*/
+/* blake2b.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifdef HAVE_BLAKE2
+
+#include 
+#include 
+
+
+static const word64 blake2b_IV[8] =
+{
+  0x6a09e667f3bcc908ULL, 0xbb67ae8584caa73bULL,
+  0x3c6ef372fe94f82bULL, 0xa54ff53a5f1d36f1ULL,
+  0x510e527fade682d1ULL, 0x9b05688c2b3e6c1fULL,
+  0x1f83d9abfb41bd6bULL, 0x5be0cd19137e2179ULL
+};
+
+static const byte blake2b_sigma[12][16] =
+{
+  {  0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15 } ,
+  { 14, 10,  4,  8,  9, 15, 13,  6,  1, 12,  0,  2, 11,  7,  5,  3 } ,
+  { 11,  8, 12,  0,  5,  2, 15, 13, 10, 14,  3,  6,  7,  1,  9,  4 } ,
+  {  7,  9,  3,  1, 13, 12, 11, 14,  2,  6,  5, 10,  4,  0, 15,  8 } ,
+  {  9,  0,  5,  7,  2,  4, 10, 15, 14,  1, 11, 12,  6,  8,  3, 13 } ,
+  {  2, 12,  6, 10,  0, 11,  8,  3,  4, 13,  7,  5, 15, 14,  1,  9 } ,
+  { 12,  5,  1, 15, 14, 13,  4, 10,  0,  7,  6,  3,  9,  2,  8, 11 } ,
+  { 13, 11,  7, 14, 12,  1,  3,  9,  5,  0, 15,  4,  8,  6,  2, 10 } ,
+  {  6, 15, 14,  9, 11,  3,  0,  8, 12,  2, 13,  7,  1,  4, 10,  5 } ,
+  { 10,  2,  8,  4,  7,  6,  1,  5, 15, 11,  9, 14,  3, 12, 13 , 0 } ,
+  {  0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15 } ,
+  { 14, 10,  4,  8,  9, 15, 13,  6,  1, 12,  0,  2, 11,  7,  5,  3 }
+};
+
+
+static INLINE int blake2b_set_lastnode( blake2b_state *S )
+{
+  S->f[1] = ~0ULL;
+  return 0;
+}
+
+/* Some helper functions, not necessarily useful */
+static INLINE int blake2b_set_lastblock( blake2b_state *S )
+{
+  if( S->last_node ) blake2b_set_lastnode( S );
+
+  S->f[0] = ~0ULL;
+  return 0;
+}
+
+static INLINE int blake2b_increment_counter( blake2b_state *S, const word64
+                                             inc )
+{
+  S->t[0] += inc;
+  S->t[1] += ( S->t[0] < inc );
+  return 0;
+}
+
+static INLINE int blake2b_init0( blake2b_state *S )
+{
+  int i;
+  XMEMSET( S, 0, sizeof( blake2b_state ) );
+
+  for( i = 0; i < 8; ++i ) S->h[i] = blake2b_IV[i];
+
+  return 0;
+}
+
+/* init xors IV with input parameter block */
+int blake2b_init_param( blake2b_state *S, const blake2b_param *P )
+{
+  word32 i;
+  blake2b_init0( S );
+  byte *p = ( byte * )( P );
+
+  /* IV XOR ParamBlock */
+  for( i = 0; i < 8; ++i )
+    S->h[i] ^= load64( p + sizeof( S->h[i] ) * i );
+
+  return 0;
+}
+
+
+
+int blake2b_init( blake2b_state *S, const byte outlen )
+{
+  blake2b_param P[1];
+
+  if ( ( !outlen ) || ( outlen > BLAKE2B_OUTBYTES ) ) return -1;
+
+  P->digest_length = outlen;
+  P->key_length    = 0;
+  P->fanout        = 1;
+  P->depth         = 1;
+  store32( &P->leaf_length, 0 );
+  store64( &P->node_offset, 0 );
+  P->node_depth    = 0;
+  P->inner_length  = 0;
+  XMEMSET( P->reserved, 0, sizeof( P->reserved ) );
+  XMEMSET( P->salt,     0, sizeof( P->salt ) );
+  XMEMSET( P->personal, 0, sizeof( P->personal ) );
+  return blake2b_init_param( S, P );
+}
+
+
+int blake2b_init_key( blake2b_state *S, const byte outlen, const void *key,
+                      const byte keylen )
+{
+  blake2b_param P[1];
+
+  if ( ( !outlen ) || ( outlen > BLAKE2B_OUTBYTES ) ) return -1;
+
+  if ( !key || !keylen || keylen > BLAKE2B_KEYBYTES ) return -1;
+
+  P->digest_length = outlen;
+  P->key_length    = keylen;
+  P->fanout        = 1;
+  P->depth         = 1;
+  store32( &P->leaf_length, 0 );
+  store64( &P->node_offset, 0 );
+  P->node_depth    = 0;
+  P->inner_length  = 0;
+  XMEMSET( P->reserved, 0, sizeof( P->reserved ) );
+  XMEMSET( P->salt,     0, sizeof( P->salt ) );
+  XMEMSET( P->personal, 0, sizeof( P->personal ) );
+
+  if( blake2b_init_param( S, P ) < 0 ) return -1;
+
+  {
+#ifdef WOLFSSL_SMALL_STACK
+    byte* block;
+
+    block = (byte*)XMALLOC(BLAKE2B_BLOCKBYTES, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+
+    if ( block == NULL ) return -1;
+#else
+    byte block[BLAKE2B_BLOCKBYTES];
+#endif
+
+    XMEMSET( block, 0, BLAKE2B_BLOCKBYTES );
+    XMEMCPY( block, key, keylen );
+    blake2b_update( S, block, BLAKE2B_BLOCKBYTES );
+    secure_zero_memory( block, BLAKE2B_BLOCKBYTES ); /* Burn the key from */
+                                                     /* memory */
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(block, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+  }
+  return 0;
+}
+
+static int blake2b_compress( blake2b_state *S,
+                             const byte block[BLAKE2B_BLOCKBYTES] )
+{
+  int i;
+
+#ifdef WOLFSSL_SMALL_STACK
+  word64* m;
+  word64* v;
+
+  m = (word64*)XMALLOC(sizeof(word64) * 16, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+
+  if ( m == NULL ) return -1;
+
+  v = (word64*)XMALLOC(sizeof(word64) * 16, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+
+  if ( v == NULL )
+  {
+    XFREE(m, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    return -1;
+  }
+#else
+  word64 m[16];
+  word64 v[16];
+#endif
+
+  for( i = 0; i < 16; ++i )
+    m[i] = load64( block + i * sizeof( m[i] ) );
+
+  for( i = 0; i < 8; ++i )
+    v[i] = S->h[i];
+
+  v[ 8] = blake2b_IV[0];
+  v[ 9] = blake2b_IV[1];
+  v[10] = blake2b_IV[2];
+  v[11] = blake2b_IV[3];
+  v[12] = S->t[0] ^ blake2b_IV[4];
+  v[13] = S->t[1] ^ blake2b_IV[5];
+  v[14] = S->f[0] ^ blake2b_IV[6];
+  v[15] = S->f[1] ^ blake2b_IV[7];
+#define G(r,i,a,b,c,d) \
+  do { \
+    a = a + b + m[blake2b_sigma[r][2*i+0]]; \
+    d = rotr64(d ^ a, 32); \
+    c = c + d; \
+    b = rotr64(b ^ c, 24); \
+    a = a + b + m[blake2b_sigma[r][2*i+1]]; \
+    d = rotr64(d ^ a, 16); \
+    c = c + d; \
+    b = rotr64(b ^ c, 63); \
+  } while(0)
+#define ROUND(r)  \
+  do { \
+    G(r,0,v[ 0],v[ 4],v[ 8],v[12]); \
+    G(r,1,v[ 1],v[ 5],v[ 9],v[13]); \
+    G(r,2,v[ 2],v[ 6],v[10],v[14]); \
+    G(r,3,v[ 3],v[ 7],v[11],v[15]); \
+    G(r,4,v[ 0],v[ 5],v[10],v[15]); \
+    G(r,5,v[ 1],v[ 6],v[11],v[12]); \
+    G(r,6,v[ 2],v[ 7],v[ 8],v[13]); \
+    G(r,7,v[ 3],v[ 4],v[ 9],v[14]); \
+  } while(0)
+  ROUND( 0 );
+  ROUND( 1 );
+  ROUND( 2 );
+  ROUND( 3 );
+  ROUND( 4 );
+  ROUND( 5 );
+  ROUND( 6 );
+  ROUND( 7 );
+  ROUND( 8 );
+  ROUND( 9 );
+  ROUND( 10 );
+  ROUND( 11 );
+
+  for( i = 0; i < 8; ++i )
+    S->h[i] = S->h[i] ^ v[i] ^ v[i + 8];
+
+#undef G
+#undef ROUND
+
+#ifdef WOLFSSL_SMALL_STACK
+  XFREE(m, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+  XFREE(v, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+  return 0;
+}
+
+/* inlen now in bytes */
+int blake2b_update( blake2b_state *S, const byte *in, word64 inlen )
+{
+  while( inlen > 0 )
+  {
+    word64 left = S->buflen;
+    word64 fill = 2 * BLAKE2B_BLOCKBYTES - left;
+
+    if( inlen > fill )
+    {
+      XMEMCPY( S->buf + left, in, (wolfssl_word)fill ); /* Fill buffer */
+      S->buflen += fill;
+      blake2b_increment_counter( S, BLAKE2B_BLOCKBYTES );
+
+      if ( blake2b_compress( S, S->buf ) < 0 ) return -1; /* Compress */
+
+      XMEMCPY( S->buf, S->buf + BLAKE2B_BLOCKBYTES, BLAKE2B_BLOCKBYTES );
+              /* Shift buffer left */
+      S->buflen -= BLAKE2B_BLOCKBYTES;
+      in += fill;
+      inlen -= fill;
+    }
+    else /* inlen <= fill */
+    {
+      XMEMCPY( S->buf + left, in, (wolfssl_word)inlen );
+      S->buflen += inlen; /* Be lazy, do not compress */
+      in += inlen;
+      inlen -= inlen;
+    }
+  }
+
+  return 0;
+}
+
+/* Is this correct? */
+int blake2b_final( blake2b_state *S, byte *out, byte outlen )
+{
+  byte buffer[BLAKE2B_OUTBYTES];
+  int     i;
+
+  if( S->buflen > BLAKE2B_BLOCKBYTES )
+  {
+    blake2b_increment_counter( S, BLAKE2B_BLOCKBYTES );
+
+    if ( blake2b_compress( S, S->buf ) < 0 ) return -1;
+
+    S->buflen -= BLAKE2B_BLOCKBYTES;
+    XMEMCPY( S->buf, S->buf + BLAKE2B_BLOCKBYTES, (wolfssl_word)S->buflen );
+  }
+
+  blake2b_increment_counter( S, S->buflen );
+  blake2b_set_lastblock( S );
+  XMEMSET( S->buf + S->buflen, 0, (wolfssl_word)(2 * BLAKE2B_BLOCKBYTES - S->buflen) );
+         /* Padding */
+  if ( blake2b_compress( S, S->buf ) < 0 ) return -1;
+
+  for( i = 0; i < 8; ++i ) /* Output full hash to temp buffer */
+    store64( buffer + sizeof( S->h[i] ) * i, S->h[i] );
+
+  XMEMCPY( out, buffer, outlen );
+  return 0;
+}
+
+/* inlen, at least, should be word64. Others can be size_t. */
+int blake2b( byte *out, const void *in, const void *key, const byte outlen,
+             const word64 inlen, byte keylen )
+{
+  blake2b_state S[1];
+
+  /* Verify parameters */
+  if ( NULL == in ) return -1;
+
+  if ( NULL == out ) return -1;
+
+  if( NULL == key ) keylen = 0;
+
+  if( keylen > 0 )
+  {
+    if( blake2b_init_key( S, outlen, key, keylen ) < 0 ) return -1;
+  }
+  else
+  {
+    if( blake2b_init( S, outlen ) < 0 ) return -1;
+  }
+
+  if ( blake2b_update( S, ( byte * )in, inlen ) < 0) return -1;
+
+  return blake2b_final( S, out, outlen );
+}
+
+#if defined(BLAKE2B_SELFTEST)
+#include 
+#include "blake2-kat.h"
+int main( int argc, char **argv )
+{
+  byte key[BLAKE2B_KEYBYTES];
+  byte buf[KAT_LENGTH];
+
+  for( word32 i = 0; i < BLAKE2B_KEYBYTES; ++i )
+    key[i] = ( byte )i;
+
+  for( word32 i = 0; i < KAT_LENGTH; ++i )
+    buf[i] = ( byte )i;
+
+  for( word32 i = 0; i < KAT_LENGTH; ++i )
+  {
+    byte hash[BLAKE2B_OUTBYTES];
+    if ( blake2b( hash, buf, key, BLAKE2B_OUTBYTES, i, BLAKE2B_KEYBYTES ) < 0 )
+    {
+      puts( "error" );
+      return -1;
+    }
+
+    if( 0 != memcmp( hash, blake2b_keyed_kat[i], BLAKE2B_OUTBYTES ) )
+    {
+      puts( "error" );
+      return -1;
+    }
+  }
+
+  puts( "ok" );
+  return 0;
+}
+#endif
+
+
+/* wolfCrypt API */
+
+/* Init Blake2b digest, track size incase final doesn't want to "remember" */
+int wc_InitBlake2b(Blake2b* b2b, word32 digestSz)
+{
+    b2b->digestSz = digestSz;
+
+    return blake2b_init(b2b->S, (byte)digestSz);
+}
+
+
+/* Blake2b Update */
+int wc_Blake2bUpdate(Blake2b* b2b, const byte* data, word32 sz)
+{
+    return blake2b_update(b2b->S, data, sz);
+}
+
+
+/* Blake2b Final, if pass in zero size we use init digestSz */
+int wc_Blake2bFinal(Blake2b* b2b, byte* final, word32 requestSz)
+{
+    word32 sz = requestSz ? requestSz : b2b->digestSz;
+
+    return blake2b_final(b2b->S, final, (byte)sz);
+}
+
+
+/* end CTaoCrypt API */
+
+#endif  /* HAVE_BLAKE2 */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/camellia.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/camellia.c
new file mode 100644
index 0000000..071019c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/camellia.c
@@ -0,0 +1,1620 @@
+/* camellia.c ver 1.2.0
+ *
+ * Copyright (c) 2006,2007
+ * NTT (Nippon Telegraph and Telephone Corporation) . All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer as
+ *   the first lines of this file unmodified.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NTT ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL NTT BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* camellia.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+/*
+ * Algorithm Specification 
+ *  http://info.isl.ntt.co.jp/crypt/eng/camellia/specifications.html
+ */
+
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifdef HAVE_CAMELLIA
+
+#include 
+#include 
+#include 
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+/* u32 must be 32bit word */
+typedef unsigned int u32;
+typedef unsigned char u8;
+
+/* key constants */
+
+#define CAMELLIA_SIGMA1L ((u32)0xA09E667FL)
+#define CAMELLIA_SIGMA1R ((u32)0x3BCC908BL)
+#define CAMELLIA_SIGMA2L ((u32)0xB67AE858L)
+#define CAMELLIA_SIGMA2R ((u32)0x4CAA73B2L)
+#define CAMELLIA_SIGMA3L ((u32)0xC6EF372FL)
+#define CAMELLIA_SIGMA3R ((u32)0xE94F82BEL)
+#define CAMELLIA_SIGMA4L ((u32)0x54FF53A5L)
+#define CAMELLIA_SIGMA4R ((u32)0xF1D36F1CL)
+#define CAMELLIA_SIGMA5L ((u32)0x10E527FAL)
+#define CAMELLIA_SIGMA5R ((u32)0xDE682D1DL)
+#define CAMELLIA_SIGMA6L ((u32)0xB05688C2L)
+#define CAMELLIA_SIGMA6R ((u32)0xB3E6C1FDL)
+
+/*
+ *  macros
+ */
+
+
+#if defined(_MSC_VER)
+
+# define SWAP(x) (_lrotl(x, 8) & 0x00ff00ff | _lrotr(x, 8) & 0xff00ff00)
+# define GETU32(p) SWAP(*((u32 *)(p)))
+# define PUTU32(ct, st) {*((u32 *)(ct)) = SWAP((st));}
+
+#else /* not MS-VC */
+
+# define GETU32(pt)				\
+    (((u32)(pt)[0] << 24)			\
+     ^ ((u32)(pt)[1] << 16)			\
+     ^ ((u32)(pt)[2] <<  8)			\
+     ^ ((u32)(pt)[3]))
+
+# define PUTU32(ct, st)  {			\
+	(ct)[0] = (u8)((st) >> 24);		\
+	(ct)[1] = (u8)((st) >> 16);		\
+	(ct)[2] = (u8)((st) >>  8);		\
+	(ct)[3] = (u8)(st); }
+
+#endif
+
+#define CamelliaSubkeyL(INDEX) (subkey[(INDEX)*2])
+#define CamelliaSubkeyR(INDEX) (subkey[(INDEX)*2 + 1])
+
+/* rotation right shift 1byte */
+#define CAMELLIA_RR8(x) (((x) >> 8) + ((x) << 24))
+/* rotation left shift 1bit */
+#define CAMELLIA_RL1(x) (((x) << 1) + ((x) >> 31))
+/* rotation left shift 1byte */
+#define CAMELLIA_RL8(x) (((x) << 8) + ((x) >> 24))
+
+#define CAMELLIA_ROLDQ(ll, lr, rl, rr, w0, w1, bits)	\
+    do {						\
+	w0 = ll;					\
+	ll = (ll << bits) + (lr >> (32 - bits));	\
+	lr = (lr << bits) + (rl >> (32 - bits));	\
+	rl = (rl << bits) + (rr >> (32 - bits));	\
+	rr = (rr << bits) + (w0 >> (32 - bits));	\
+    } while(0)
+
+#define CAMELLIA_ROLDQo32(ll, lr, rl, rr, w0, w1, bits)	\
+    do {						\
+	w0 = ll;					\
+	w1 = lr;					\
+	ll = (lr << (bits - 32)) + (rl >> (64 - bits));	\
+	lr = (rl << (bits - 32)) + (rr >> (64 - bits));	\
+	rl = (rr << (bits - 32)) + (w0 >> (64 - bits));	\
+	rr = (w0 << (bits - 32)) + (w1 >> (64 - bits));	\
+    } while(0)
+
+#define CAMELLIA_SP1110(INDEX) (camellia_sp1110[(INDEX)])
+#define CAMELLIA_SP0222(INDEX) (camellia_sp0222[(INDEX)])
+#define CAMELLIA_SP3033(INDEX) (camellia_sp3033[(INDEX)])
+#define CAMELLIA_SP4404(INDEX) (camellia_sp4404[(INDEX)])
+
+#define CAMELLIA_F(xl, xr, kl, kr, yl, yr, il, ir, t0, t1)	\
+    do {							\
+	il = xl ^ kl;						\
+	ir = xr ^ kr;						\
+	t0 = il >> 16;						\
+	t1 = ir >> 16;						\
+	yl = CAMELLIA_SP1110(ir & 0xff)				\
+	    ^ CAMELLIA_SP0222((t1 >> 8) & 0xff)			\
+	    ^ CAMELLIA_SP3033(t1 & 0xff)			\
+	    ^ CAMELLIA_SP4404((ir >> 8) & 0xff);		\
+	yr = CAMELLIA_SP1110((t0 >> 8) & 0xff)			\
+	    ^ CAMELLIA_SP0222(t0 & 0xff)			\
+	    ^ CAMELLIA_SP3033((il >> 8) & 0xff)			\
+	    ^ CAMELLIA_SP4404(il & 0xff);			\
+	yl ^= yr;						\
+	yr = CAMELLIA_RR8(yr);					\
+	yr ^= yl;						\
+    } while(0)
+
+
+/*
+ * for speed up
+ *
+ */
+#define CAMELLIA_FLS(ll, lr, rl, rr, kll, klr, krl, krr, t0, t1, t2, t3) \
+    do {								\
+	t0 = kll;							\
+	t0 &= ll;							\
+	lr ^= CAMELLIA_RL1(t0);						\
+	t1 = klr;							\
+	t1 |= lr;							\
+	ll ^= t1;							\
+									\
+	t2 = krr;							\
+	t2 |= rr;							\
+	rl ^= t2;							\
+	t3 = krl;							\
+	t3 &= rl;							\
+	rr ^= CAMELLIA_RL1(t3);						\
+    } while(0)
+
+#define CAMELLIA_ROUNDSM(xl, xr, kl, kr, yl, yr, il, ir, t0, t1)	\
+    do {								\
+	ir = CAMELLIA_SP1110(xr & 0xff)					\
+	    ^ CAMELLIA_SP0222((xr >> 24) & 0xff)			\
+	    ^ CAMELLIA_SP3033((xr >> 16) & 0xff)			\
+	    ^ CAMELLIA_SP4404((xr >> 8) & 0xff);			\
+	il = CAMELLIA_SP1110((xl >> 24) & 0xff)				\
+	    ^ CAMELLIA_SP0222((xl >> 16) & 0xff)			\
+	    ^ CAMELLIA_SP3033((xl >> 8) & 0xff)				\
+	    ^ CAMELLIA_SP4404(xl & 0xff);				\
+	il ^= kl;							\
+	ir ^= kr;							\
+	ir ^= il;							\
+	il = CAMELLIA_RR8(il);						\
+	il ^= ir;							\
+	yl ^= ir;							\
+	yr ^= il;							\
+    } while(0)
+
+
+static const u32 camellia_sp1110[256] = {
+    0x70707000,0x82828200,0x2c2c2c00,0xececec00,
+    0xb3b3b300,0x27272700,0xc0c0c000,0xe5e5e500,
+    0xe4e4e400,0x85858500,0x57575700,0x35353500,
+    0xeaeaea00,0x0c0c0c00,0xaeaeae00,0x41414100,
+    0x23232300,0xefefef00,0x6b6b6b00,0x93939300,
+    0x45454500,0x19191900,0xa5a5a500,0x21212100,
+    0xededed00,0x0e0e0e00,0x4f4f4f00,0x4e4e4e00,
+    0x1d1d1d00,0x65656500,0x92929200,0xbdbdbd00,
+    0x86868600,0xb8b8b800,0xafafaf00,0x8f8f8f00,
+    0x7c7c7c00,0xebebeb00,0x1f1f1f00,0xcecece00,
+    0x3e3e3e00,0x30303000,0xdcdcdc00,0x5f5f5f00,
+    0x5e5e5e00,0xc5c5c500,0x0b0b0b00,0x1a1a1a00,
+    0xa6a6a600,0xe1e1e100,0x39393900,0xcacaca00,
+    0xd5d5d500,0x47474700,0x5d5d5d00,0x3d3d3d00,
+    0xd9d9d900,0x01010100,0x5a5a5a00,0xd6d6d600,
+    0x51515100,0x56565600,0x6c6c6c00,0x4d4d4d00,
+    0x8b8b8b00,0x0d0d0d00,0x9a9a9a00,0x66666600,
+    0xfbfbfb00,0xcccccc00,0xb0b0b000,0x2d2d2d00,
+    0x74747400,0x12121200,0x2b2b2b00,0x20202000,
+    0xf0f0f000,0xb1b1b100,0x84848400,0x99999900,
+    0xdfdfdf00,0x4c4c4c00,0xcbcbcb00,0xc2c2c200,
+    0x34343400,0x7e7e7e00,0x76767600,0x05050500,
+    0x6d6d6d00,0xb7b7b700,0xa9a9a900,0x31313100,
+    0xd1d1d100,0x17171700,0x04040400,0xd7d7d700,
+    0x14141400,0x58585800,0x3a3a3a00,0x61616100,
+    0xdedede00,0x1b1b1b00,0x11111100,0x1c1c1c00,
+    0x32323200,0x0f0f0f00,0x9c9c9c00,0x16161600,
+    0x53535300,0x18181800,0xf2f2f200,0x22222200,
+    0xfefefe00,0x44444400,0xcfcfcf00,0xb2b2b200,
+    0xc3c3c300,0xb5b5b500,0x7a7a7a00,0x91919100,
+    0x24242400,0x08080800,0xe8e8e800,0xa8a8a800,
+    0x60606000,0xfcfcfc00,0x69696900,0x50505000,
+    0xaaaaaa00,0xd0d0d000,0xa0a0a000,0x7d7d7d00,
+    0xa1a1a100,0x89898900,0x62626200,0x97979700,
+    0x54545400,0x5b5b5b00,0x1e1e1e00,0x95959500,
+    0xe0e0e000,0xffffff00,0x64646400,0xd2d2d200,
+    0x10101000,0xc4c4c400,0x00000000,0x48484800,
+    0xa3a3a300,0xf7f7f700,0x75757500,0xdbdbdb00,
+    0x8a8a8a00,0x03030300,0xe6e6e600,0xdadada00,
+    0x09090900,0x3f3f3f00,0xdddddd00,0x94949400,
+    0x87878700,0x5c5c5c00,0x83838300,0x02020200,
+    0xcdcdcd00,0x4a4a4a00,0x90909000,0x33333300,
+    0x73737300,0x67676700,0xf6f6f600,0xf3f3f300,
+    0x9d9d9d00,0x7f7f7f00,0xbfbfbf00,0xe2e2e200,
+    0x52525200,0x9b9b9b00,0xd8d8d800,0x26262600,
+    0xc8c8c800,0x37373700,0xc6c6c600,0x3b3b3b00,
+    0x81818100,0x96969600,0x6f6f6f00,0x4b4b4b00,
+    0x13131300,0xbebebe00,0x63636300,0x2e2e2e00,
+    0xe9e9e900,0x79797900,0xa7a7a700,0x8c8c8c00,
+    0x9f9f9f00,0x6e6e6e00,0xbcbcbc00,0x8e8e8e00,
+    0x29292900,0xf5f5f500,0xf9f9f900,0xb6b6b600,
+    0x2f2f2f00,0xfdfdfd00,0xb4b4b400,0x59595900,
+    0x78787800,0x98989800,0x06060600,0x6a6a6a00,
+    0xe7e7e700,0x46464600,0x71717100,0xbababa00,
+    0xd4d4d400,0x25252500,0xababab00,0x42424200,
+    0x88888800,0xa2a2a200,0x8d8d8d00,0xfafafa00,
+    0x72727200,0x07070700,0xb9b9b900,0x55555500,
+    0xf8f8f800,0xeeeeee00,0xacacac00,0x0a0a0a00,
+    0x36363600,0x49494900,0x2a2a2a00,0x68686800,
+    0x3c3c3c00,0x38383800,0xf1f1f100,0xa4a4a400,
+    0x40404000,0x28282800,0xd3d3d300,0x7b7b7b00,
+    0xbbbbbb00,0xc9c9c900,0x43434300,0xc1c1c100,
+    0x15151500,0xe3e3e300,0xadadad00,0xf4f4f400,
+    0x77777700,0xc7c7c700,0x80808000,0x9e9e9e00,
+};
+
+static const u32 camellia_sp0222[256] = {
+    0x00e0e0e0,0x00050505,0x00585858,0x00d9d9d9,
+    0x00676767,0x004e4e4e,0x00818181,0x00cbcbcb,
+    0x00c9c9c9,0x000b0b0b,0x00aeaeae,0x006a6a6a,
+    0x00d5d5d5,0x00181818,0x005d5d5d,0x00828282,
+    0x00464646,0x00dfdfdf,0x00d6d6d6,0x00272727,
+    0x008a8a8a,0x00323232,0x004b4b4b,0x00424242,
+    0x00dbdbdb,0x001c1c1c,0x009e9e9e,0x009c9c9c,
+    0x003a3a3a,0x00cacaca,0x00252525,0x007b7b7b,
+    0x000d0d0d,0x00717171,0x005f5f5f,0x001f1f1f,
+    0x00f8f8f8,0x00d7d7d7,0x003e3e3e,0x009d9d9d,
+    0x007c7c7c,0x00606060,0x00b9b9b9,0x00bebebe,
+    0x00bcbcbc,0x008b8b8b,0x00161616,0x00343434,
+    0x004d4d4d,0x00c3c3c3,0x00727272,0x00959595,
+    0x00ababab,0x008e8e8e,0x00bababa,0x007a7a7a,
+    0x00b3b3b3,0x00020202,0x00b4b4b4,0x00adadad,
+    0x00a2a2a2,0x00acacac,0x00d8d8d8,0x009a9a9a,
+    0x00171717,0x001a1a1a,0x00353535,0x00cccccc,
+    0x00f7f7f7,0x00999999,0x00616161,0x005a5a5a,
+    0x00e8e8e8,0x00242424,0x00565656,0x00404040,
+    0x00e1e1e1,0x00636363,0x00090909,0x00333333,
+    0x00bfbfbf,0x00989898,0x00979797,0x00858585,
+    0x00686868,0x00fcfcfc,0x00ececec,0x000a0a0a,
+    0x00dadada,0x006f6f6f,0x00535353,0x00626262,
+    0x00a3a3a3,0x002e2e2e,0x00080808,0x00afafaf,
+    0x00282828,0x00b0b0b0,0x00747474,0x00c2c2c2,
+    0x00bdbdbd,0x00363636,0x00222222,0x00383838,
+    0x00646464,0x001e1e1e,0x00393939,0x002c2c2c,
+    0x00a6a6a6,0x00303030,0x00e5e5e5,0x00444444,
+    0x00fdfdfd,0x00888888,0x009f9f9f,0x00656565,
+    0x00878787,0x006b6b6b,0x00f4f4f4,0x00232323,
+    0x00484848,0x00101010,0x00d1d1d1,0x00515151,
+    0x00c0c0c0,0x00f9f9f9,0x00d2d2d2,0x00a0a0a0,
+    0x00555555,0x00a1a1a1,0x00414141,0x00fafafa,
+    0x00434343,0x00131313,0x00c4c4c4,0x002f2f2f,
+    0x00a8a8a8,0x00b6b6b6,0x003c3c3c,0x002b2b2b,
+    0x00c1c1c1,0x00ffffff,0x00c8c8c8,0x00a5a5a5,
+    0x00202020,0x00898989,0x00000000,0x00909090,
+    0x00474747,0x00efefef,0x00eaeaea,0x00b7b7b7,
+    0x00151515,0x00060606,0x00cdcdcd,0x00b5b5b5,
+    0x00121212,0x007e7e7e,0x00bbbbbb,0x00292929,
+    0x000f0f0f,0x00b8b8b8,0x00070707,0x00040404,
+    0x009b9b9b,0x00949494,0x00212121,0x00666666,
+    0x00e6e6e6,0x00cecece,0x00ededed,0x00e7e7e7,
+    0x003b3b3b,0x00fefefe,0x007f7f7f,0x00c5c5c5,
+    0x00a4a4a4,0x00373737,0x00b1b1b1,0x004c4c4c,
+    0x00919191,0x006e6e6e,0x008d8d8d,0x00767676,
+    0x00030303,0x002d2d2d,0x00dedede,0x00969696,
+    0x00262626,0x007d7d7d,0x00c6c6c6,0x005c5c5c,
+    0x00d3d3d3,0x00f2f2f2,0x004f4f4f,0x00191919,
+    0x003f3f3f,0x00dcdcdc,0x00797979,0x001d1d1d,
+    0x00525252,0x00ebebeb,0x00f3f3f3,0x006d6d6d,
+    0x005e5e5e,0x00fbfbfb,0x00696969,0x00b2b2b2,
+    0x00f0f0f0,0x00313131,0x000c0c0c,0x00d4d4d4,
+    0x00cfcfcf,0x008c8c8c,0x00e2e2e2,0x00757575,
+    0x00a9a9a9,0x004a4a4a,0x00575757,0x00848484,
+    0x00111111,0x00454545,0x001b1b1b,0x00f5f5f5,
+    0x00e4e4e4,0x000e0e0e,0x00737373,0x00aaaaaa,
+    0x00f1f1f1,0x00dddddd,0x00595959,0x00141414,
+    0x006c6c6c,0x00929292,0x00545454,0x00d0d0d0,
+    0x00787878,0x00707070,0x00e3e3e3,0x00494949,
+    0x00808080,0x00505050,0x00a7a7a7,0x00f6f6f6,
+    0x00777777,0x00939393,0x00868686,0x00838383,
+    0x002a2a2a,0x00c7c7c7,0x005b5b5b,0x00e9e9e9,
+    0x00eeeeee,0x008f8f8f,0x00010101,0x003d3d3d,
+};
+
+static const u32 camellia_sp3033[256] = {
+    0x38003838,0x41004141,0x16001616,0x76007676,
+    0xd900d9d9,0x93009393,0x60006060,0xf200f2f2,
+    0x72007272,0xc200c2c2,0xab00abab,0x9a009a9a,
+    0x75007575,0x06000606,0x57005757,0xa000a0a0,
+    0x91009191,0xf700f7f7,0xb500b5b5,0xc900c9c9,
+    0xa200a2a2,0x8c008c8c,0xd200d2d2,0x90009090,
+    0xf600f6f6,0x07000707,0xa700a7a7,0x27002727,
+    0x8e008e8e,0xb200b2b2,0x49004949,0xde00dede,
+    0x43004343,0x5c005c5c,0xd700d7d7,0xc700c7c7,
+    0x3e003e3e,0xf500f5f5,0x8f008f8f,0x67006767,
+    0x1f001f1f,0x18001818,0x6e006e6e,0xaf00afaf,
+    0x2f002f2f,0xe200e2e2,0x85008585,0x0d000d0d,
+    0x53005353,0xf000f0f0,0x9c009c9c,0x65006565,
+    0xea00eaea,0xa300a3a3,0xae00aeae,0x9e009e9e,
+    0xec00ecec,0x80008080,0x2d002d2d,0x6b006b6b,
+    0xa800a8a8,0x2b002b2b,0x36003636,0xa600a6a6,
+    0xc500c5c5,0x86008686,0x4d004d4d,0x33003333,
+    0xfd00fdfd,0x66006666,0x58005858,0x96009696,
+    0x3a003a3a,0x09000909,0x95009595,0x10001010,
+    0x78007878,0xd800d8d8,0x42004242,0xcc00cccc,
+    0xef00efef,0x26002626,0xe500e5e5,0x61006161,
+    0x1a001a1a,0x3f003f3f,0x3b003b3b,0x82008282,
+    0xb600b6b6,0xdb00dbdb,0xd400d4d4,0x98009898,
+    0xe800e8e8,0x8b008b8b,0x02000202,0xeb00ebeb,
+    0x0a000a0a,0x2c002c2c,0x1d001d1d,0xb000b0b0,
+    0x6f006f6f,0x8d008d8d,0x88008888,0x0e000e0e,
+    0x19001919,0x87008787,0x4e004e4e,0x0b000b0b,
+    0xa900a9a9,0x0c000c0c,0x79007979,0x11001111,
+    0x7f007f7f,0x22002222,0xe700e7e7,0x59005959,
+    0xe100e1e1,0xda00dada,0x3d003d3d,0xc800c8c8,
+    0x12001212,0x04000404,0x74007474,0x54005454,
+    0x30003030,0x7e007e7e,0xb400b4b4,0x28002828,
+    0x55005555,0x68006868,0x50005050,0xbe00bebe,
+    0xd000d0d0,0xc400c4c4,0x31003131,0xcb00cbcb,
+    0x2a002a2a,0xad00adad,0x0f000f0f,0xca00caca,
+    0x70007070,0xff00ffff,0x32003232,0x69006969,
+    0x08000808,0x62006262,0x00000000,0x24002424,
+    0xd100d1d1,0xfb00fbfb,0xba00baba,0xed00eded,
+    0x45004545,0x81008181,0x73007373,0x6d006d6d,
+    0x84008484,0x9f009f9f,0xee00eeee,0x4a004a4a,
+    0xc300c3c3,0x2e002e2e,0xc100c1c1,0x01000101,
+    0xe600e6e6,0x25002525,0x48004848,0x99009999,
+    0xb900b9b9,0xb300b3b3,0x7b007b7b,0xf900f9f9,
+    0xce00cece,0xbf00bfbf,0xdf00dfdf,0x71007171,
+    0x29002929,0xcd00cdcd,0x6c006c6c,0x13001313,
+    0x64006464,0x9b009b9b,0x63006363,0x9d009d9d,
+    0xc000c0c0,0x4b004b4b,0xb700b7b7,0xa500a5a5,
+    0x89008989,0x5f005f5f,0xb100b1b1,0x17001717,
+    0xf400f4f4,0xbc00bcbc,0xd300d3d3,0x46004646,
+    0xcf00cfcf,0x37003737,0x5e005e5e,0x47004747,
+    0x94009494,0xfa00fafa,0xfc00fcfc,0x5b005b5b,
+    0x97009797,0xfe00fefe,0x5a005a5a,0xac00acac,
+    0x3c003c3c,0x4c004c4c,0x03000303,0x35003535,
+    0xf300f3f3,0x23002323,0xb800b8b8,0x5d005d5d,
+    0x6a006a6a,0x92009292,0xd500d5d5,0x21002121,
+    0x44004444,0x51005151,0xc600c6c6,0x7d007d7d,
+    0x39003939,0x83008383,0xdc00dcdc,0xaa00aaaa,
+    0x7c007c7c,0x77007777,0x56005656,0x05000505,
+    0x1b001b1b,0xa400a4a4,0x15001515,0x34003434,
+    0x1e001e1e,0x1c001c1c,0xf800f8f8,0x52005252,
+    0x20002020,0x14001414,0xe900e9e9,0xbd00bdbd,
+    0xdd00dddd,0xe400e4e4,0xa100a1a1,0xe000e0e0,
+    0x8a008a8a,0xf100f1f1,0xd600d6d6,0x7a007a7a,
+    0xbb00bbbb,0xe300e3e3,0x40004040,0x4f004f4f,
+};
+
+static const u32 camellia_sp4404[256] = {
+    0x70700070,0x2c2c002c,0xb3b300b3,0xc0c000c0,
+    0xe4e400e4,0x57570057,0xeaea00ea,0xaeae00ae,
+    0x23230023,0x6b6b006b,0x45450045,0xa5a500a5,
+    0xeded00ed,0x4f4f004f,0x1d1d001d,0x92920092,
+    0x86860086,0xafaf00af,0x7c7c007c,0x1f1f001f,
+    0x3e3e003e,0xdcdc00dc,0x5e5e005e,0x0b0b000b,
+    0xa6a600a6,0x39390039,0xd5d500d5,0x5d5d005d,
+    0xd9d900d9,0x5a5a005a,0x51510051,0x6c6c006c,
+    0x8b8b008b,0x9a9a009a,0xfbfb00fb,0xb0b000b0,
+    0x74740074,0x2b2b002b,0xf0f000f0,0x84840084,
+    0xdfdf00df,0xcbcb00cb,0x34340034,0x76760076,
+    0x6d6d006d,0xa9a900a9,0xd1d100d1,0x04040004,
+    0x14140014,0x3a3a003a,0xdede00de,0x11110011,
+    0x32320032,0x9c9c009c,0x53530053,0xf2f200f2,
+    0xfefe00fe,0xcfcf00cf,0xc3c300c3,0x7a7a007a,
+    0x24240024,0xe8e800e8,0x60600060,0x69690069,
+    0xaaaa00aa,0xa0a000a0,0xa1a100a1,0x62620062,
+    0x54540054,0x1e1e001e,0xe0e000e0,0x64640064,
+    0x10100010,0x00000000,0xa3a300a3,0x75750075,
+    0x8a8a008a,0xe6e600e6,0x09090009,0xdddd00dd,
+    0x87870087,0x83830083,0xcdcd00cd,0x90900090,
+    0x73730073,0xf6f600f6,0x9d9d009d,0xbfbf00bf,
+    0x52520052,0xd8d800d8,0xc8c800c8,0xc6c600c6,
+    0x81810081,0x6f6f006f,0x13130013,0x63630063,
+    0xe9e900e9,0xa7a700a7,0x9f9f009f,0xbcbc00bc,
+    0x29290029,0xf9f900f9,0x2f2f002f,0xb4b400b4,
+    0x78780078,0x06060006,0xe7e700e7,0x71710071,
+    0xd4d400d4,0xabab00ab,0x88880088,0x8d8d008d,
+    0x72720072,0xb9b900b9,0xf8f800f8,0xacac00ac,
+    0x36360036,0x2a2a002a,0x3c3c003c,0xf1f100f1,
+    0x40400040,0xd3d300d3,0xbbbb00bb,0x43430043,
+    0x15150015,0xadad00ad,0x77770077,0x80800080,
+    0x82820082,0xecec00ec,0x27270027,0xe5e500e5,
+    0x85850085,0x35350035,0x0c0c000c,0x41410041,
+    0xefef00ef,0x93930093,0x19190019,0x21210021,
+    0x0e0e000e,0x4e4e004e,0x65650065,0xbdbd00bd,
+    0xb8b800b8,0x8f8f008f,0xebeb00eb,0xcece00ce,
+    0x30300030,0x5f5f005f,0xc5c500c5,0x1a1a001a,
+    0xe1e100e1,0xcaca00ca,0x47470047,0x3d3d003d,
+    0x01010001,0xd6d600d6,0x56560056,0x4d4d004d,
+    0x0d0d000d,0x66660066,0xcccc00cc,0x2d2d002d,
+    0x12120012,0x20200020,0xb1b100b1,0x99990099,
+    0x4c4c004c,0xc2c200c2,0x7e7e007e,0x05050005,
+    0xb7b700b7,0x31310031,0x17170017,0xd7d700d7,
+    0x58580058,0x61610061,0x1b1b001b,0x1c1c001c,
+    0x0f0f000f,0x16160016,0x18180018,0x22220022,
+    0x44440044,0xb2b200b2,0xb5b500b5,0x91910091,
+    0x08080008,0xa8a800a8,0xfcfc00fc,0x50500050,
+    0xd0d000d0,0x7d7d007d,0x89890089,0x97970097,
+    0x5b5b005b,0x95950095,0xffff00ff,0xd2d200d2,
+    0xc4c400c4,0x48480048,0xf7f700f7,0xdbdb00db,
+    0x03030003,0xdada00da,0x3f3f003f,0x94940094,
+    0x5c5c005c,0x02020002,0x4a4a004a,0x33330033,
+    0x67670067,0xf3f300f3,0x7f7f007f,0xe2e200e2,
+    0x9b9b009b,0x26260026,0x37370037,0x3b3b003b,
+    0x96960096,0x4b4b004b,0xbebe00be,0x2e2e002e,
+    0x79790079,0x8c8c008c,0x6e6e006e,0x8e8e008e,
+    0xf5f500f5,0xb6b600b6,0xfdfd00fd,0x59590059,
+    0x98980098,0x6a6a006a,0x46460046,0xbaba00ba,
+    0x25250025,0x42420042,0xa2a200a2,0xfafa00fa,
+    0x07070007,0x55550055,0xeeee00ee,0x0a0a000a,
+    0x49490049,0x68680068,0x38380038,0xa4a400a4,
+    0x28280028,0x7b7b007b,0xc9c900c9,0xc1c100c1,
+    0xe3e300e3,0xf4f400f4,0xc7c700c7,0x9e9e009e,
+};
+
+
+/**
+ * Stuff related to the Camellia key schedule
+ */
+#define subl(x) subL[(x)]
+#define subr(x) subR[(x)]
+
+static int camellia_setup128(const unsigned char *key, u32 *subkey)
+{
+    u32 kll, klr, krl, krr;
+    u32 il, ir, t0, t1, w0, w1;
+    u32 kw4l, kw4r, dw, tl, tr;
+
+#ifdef WOLFSSL_SMALL_STACK
+    u32* subL;
+    u32* subR;
+
+    subL = (u32*) XMALLOC(sizeof(u32) * 26, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (subL == NULL)
+        return MEMORY_E;
+
+    subR = (u32*) XMALLOC(sizeof(u32) * 26, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (subR == NULL) {
+        XFREE(subL, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        return MEMORY_E;
+    }
+#else
+    u32 subL[26];
+    u32 subR[26];
+#endif
+
+    /**
+     *  k == kll || klr || krl || krr (|| is concatination)
+     */
+    kll = GETU32(key     );
+    klr = GETU32(key +  4);
+    krl = GETU32(key +  8);
+    krr = GETU32(key + 12);
+    /**
+     * generate KL dependent subkeys
+     */
+    subl(0) = kll; subr(0) = klr;
+    subl(1) = krl; subr(1) = krr;
+    CAMELLIA_ROLDQ(kll, klr, krl, krr, w0, w1, 15);
+    subl(4) = kll; subr(4) = klr;
+    subl(5) = krl; subr(5) = krr;
+    CAMELLIA_ROLDQ(kll, klr, krl, krr, w0, w1, 30);
+    subl(10) = kll; subr(10) = klr;
+    subl(11) = krl; subr(11) = krr;
+    CAMELLIA_ROLDQ(kll, klr, krl, krr, w0, w1, 15);
+    subl(13) = krl; subr(13) = krr;
+    CAMELLIA_ROLDQ(kll, klr, krl, krr, w0, w1, 17);
+    subl(16) = kll; subr(16) = klr;
+    subl(17) = krl; subr(17) = krr;
+    CAMELLIA_ROLDQ(kll, klr, krl, krr, w0, w1, 17);
+    subl(18) = kll; subr(18) = klr;
+    subl(19) = krl; subr(19) = krr;
+    CAMELLIA_ROLDQ(kll, klr, krl, krr, w0, w1, 17);
+    subl(22) = kll; subr(22) = klr;
+    subl(23) = krl; subr(23) = krr;
+
+    /* generate KA */
+    kll = subl(0); klr = subr(0);
+    krl = subl(1); krr = subr(1);
+    CAMELLIA_F(kll, klr,
+	       CAMELLIA_SIGMA1L, CAMELLIA_SIGMA1R,
+	       w0, w1, il, ir, t0, t1);
+    krl ^= w0; krr ^= w1;
+    CAMELLIA_F(krl, krr,
+	       CAMELLIA_SIGMA2L, CAMELLIA_SIGMA2R,
+	       kll, klr, il, ir, t0, t1);
+    CAMELLIA_F(kll, klr,
+	       CAMELLIA_SIGMA3L, CAMELLIA_SIGMA3R,
+	       krl, krr, il, ir, t0, t1);
+    krl ^= w0; krr ^= w1;
+    CAMELLIA_F(krl, krr,
+	       CAMELLIA_SIGMA4L, CAMELLIA_SIGMA4R,
+	       w0, w1, il, ir, t0, t1);
+    kll ^= w0; klr ^= w1;
+
+    /* generate KA dependent subkeys */
+    subl(2) = kll; subr(2) = klr;
+    subl(3) = krl; subr(3) = krr;
+    CAMELLIA_ROLDQ(kll, klr, krl, krr, w0, w1, 15);
+    subl(6) = kll; subr(6) = klr;
+    subl(7) = krl; subr(7) = krr;
+    CAMELLIA_ROLDQ(kll, klr, krl, krr, w0, w1, 15);
+    subl(8) = kll; subr(8) = klr;
+    subl(9) = krl; subr(9) = krr;
+    CAMELLIA_ROLDQ(kll, klr, krl, krr, w0, w1, 15);
+    subl(12) = kll; subr(12) = klr;
+    CAMELLIA_ROLDQ(kll, klr, krl, krr, w0, w1, 15);
+    subl(14) = kll; subr(14) = klr;
+    subl(15) = krl; subr(15) = krr;
+    CAMELLIA_ROLDQo32(kll, klr, krl, krr, w0, w1, 34);
+    subl(20) = kll; subr(20) = klr;
+    subl(21) = krl; subr(21) = krr;
+    CAMELLIA_ROLDQ(kll, klr, krl, krr, w0, w1, 17);
+    subl(24) = kll; subr(24) = klr;
+    subl(25) = krl; subr(25) = krr;
+
+
+    /* absorb kw2 to other subkeys */
+    subl(3) ^= subl(1); subr(3) ^= subr(1);
+    subl(5) ^= subl(1); subr(5) ^= subr(1);
+    subl(7) ^= subl(1); subr(7) ^= subr(1);
+    subl(1) ^= subr(1) & ~subr(9);
+    dw = subl(1) & subl(9), subr(1) ^= CAMELLIA_RL1(dw);
+    subl(11) ^= subl(1); subr(11) ^= subr(1);
+    subl(13) ^= subl(1); subr(13) ^= subr(1);
+    subl(15) ^= subl(1); subr(15) ^= subr(1);
+    subl(1) ^= subr(1) & ~subr(17);
+    dw = subl(1) & subl(17), subr(1) ^= CAMELLIA_RL1(dw);
+    subl(19) ^= subl(1); subr(19) ^= subr(1);
+    subl(21) ^= subl(1); subr(21) ^= subr(1);
+    subl(23) ^= subl(1); subr(23) ^= subr(1);
+    subl(24) ^= subl(1); subr(24) ^= subr(1);
+
+    /* absorb kw4 to other subkeys */
+    kw4l = subl(25); kw4r = subr(25);
+    subl(22) ^= kw4l; subr(22) ^= kw4r;
+    subl(20) ^= kw4l; subr(20) ^= kw4r;
+    subl(18) ^= kw4l; subr(18) ^= kw4r;
+    kw4l ^= kw4r & ~subr(16);
+    dw = kw4l & subl(16), kw4r ^= CAMELLIA_RL1(dw);
+    subl(14) ^= kw4l; subr(14) ^= kw4r;
+    subl(12) ^= kw4l; subr(12) ^= kw4r;
+    subl(10) ^= kw4l; subr(10) ^= kw4r;
+    kw4l ^= kw4r & ~subr(8);
+    dw = kw4l & subl(8), kw4r ^= CAMELLIA_RL1(dw);
+    subl(6) ^= kw4l; subr(6) ^= kw4r;
+    subl(4) ^= kw4l; subr(4) ^= kw4r;
+    subl(2) ^= kw4l; subr(2) ^= kw4r;
+    subl(0) ^= kw4l; subr(0) ^= kw4r;
+
+    /* key XOR is end of F-function */
+    CamelliaSubkeyL(0) = subl(0) ^ subl(2);
+    CamelliaSubkeyR(0) = subr(0) ^ subr(2);
+    CamelliaSubkeyL(2) = subl(3);
+    CamelliaSubkeyR(2) = subr(3);
+    CamelliaSubkeyL(3) = subl(2) ^ subl(4);
+    CamelliaSubkeyR(3) = subr(2) ^ subr(4);
+    CamelliaSubkeyL(4) = subl(3) ^ subl(5);
+    CamelliaSubkeyR(4) = subr(3) ^ subr(5);
+    CamelliaSubkeyL(5) = subl(4) ^ subl(6);
+    CamelliaSubkeyR(5) = subr(4) ^ subr(6);
+    CamelliaSubkeyL(6) = subl(5) ^ subl(7);
+    CamelliaSubkeyR(6) = subr(5) ^ subr(7);
+    tl = subl(10) ^ (subr(10) & ~subr(8));
+    dw = tl & subl(8), tr = subr(10) ^ CAMELLIA_RL1(dw);
+    CamelliaSubkeyL(7) = subl(6) ^ tl;
+    CamelliaSubkeyR(7) = subr(6) ^ tr;
+    CamelliaSubkeyL(8) = subl(8);
+    CamelliaSubkeyR(8) = subr(8);
+    CamelliaSubkeyL(9) = subl(9);
+    CamelliaSubkeyR(9) = subr(9);
+    tl = subl(7) ^ (subr(7) & ~subr(9));
+    dw = tl & subl(9), tr = subr(7) ^ CAMELLIA_RL1(dw);
+    CamelliaSubkeyL(10) = tl ^ subl(11);
+    CamelliaSubkeyR(10) = tr ^ subr(11);
+    CamelliaSubkeyL(11) = subl(10) ^ subl(12);
+    CamelliaSubkeyR(11) = subr(10) ^ subr(12);
+    CamelliaSubkeyL(12) = subl(11) ^ subl(13);
+    CamelliaSubkeyR(12) = subr(11) ^ subr(13);
+    CamelliaSubkeyL(13) = subl(12) ^ subl(14);
+    CamelliaSubkeyR(13) = subr(12) ^ subr(14);
+    CamelliaSubkeyL(14) = subl(13) ^ subl(15);
+    CamelliaSubkeyR(14) = subr(13) ^ subr(15);
+    tl = subl(18) ^ (subr(18) & ~subr(16));
+    dw = tl & subl(16),	tr = subr(18) ^ CAMELLIA_RL1(dw);
+    CamelliaSubkeyL(15) = subl(14) ^ tl;
+    CamelliaSubkeyR(15) = subr(14) ^ tr;
+    CamelliaSubkeyL(16) = subl(16);
+    CamelliaSubkeyR(16) = subr(16);
+    CamelliaSubkeyL(17) = subl(17);
+    CamelliaSubkeyR(17) = subr(17);
+    tl = subl(15) ^ (subr(15) & ~subr(17));
+    dw = tl & subl(17),	tr = subr(15) ^ CAMELLIA_RL1(dw);
+    CamelliaSubkeyL(18) = tl ^ subl(19);
+    CamelliaSubkeyR(18) = tr ^ subr(19);
+    CamelliaSubkeyL(19) = subl(18) ^ subl(20);
+    CamelliaSubkeyR(19) = subr(18) ^ subr(20);
+    CamelliaSubkeyL(20) = subl(19) ^ subl(21);
+    CamelliaSubkeyR(20) = subr(19) ^ subr(21);
+    CamelliaSubkeyL(21) = subl(20) ^ subl(22);
+    CamelliaSubkeyR(21) = subr(20) ^ subr(22);
+    CamelliaSubkeyL(22) = subl(21) ^ subl(23);
+    CamelliaSubkeyR(22) = subr(21) ^ subr(23);
+    CamelliaSubkeyL(23) = subl(22);
+    CamelliaSubkeyR(23) = subr(22);
+    CamelliaSubkeyL(24) = subl(24) ^ subl(23);
+    CamelliaSubkeyR(24) = subr(24) ^ subr(23);
+
+    /* apply the inverse of the last half of P-function */
+    dw = CamelliaSubkeyL(2) ^ CamelliaSubkeyR(2), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(2) = CamelliaSubkeyL(2) ^ dw, CamelliaSubkeyL(2) = dw;
+    dw = CamelliaSubkeyL(3) ^ CamelliaSubkeyR(3), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(3) = CamelliaSubkeyL(3) ^ dw, CamelliaSubkeyL(3) = dw;
+    dw = CamelliaSubkeyL(4) ^ CamelliaSubkeyR(4), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(4) = CamelliaSubkeyL(4) ^ dw, CamelliaSubkeyL(4) = dw;
+    dw = CamelliaSubkeyL(5) ^ CamelliaSubkeyR(5), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(5) = CamelliaSubkeyL(5) ^ dw, CamelliaSubkeyL(5) = dw;
+    dw = CamelliaSubkeyL(6) ^ CamelliaSubkeyR(6), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(6) = CamelliaSubkeyL(6) ^ dw, CamelliaSubkeyL(6) = dw;
+    dw = CamelliaSubkeyL(7) ^ CamelliaSubkeyR(7), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(7) = CamelliaSubkeyL(7) ^ dw, CamelliaSubkeyL(7) = dw;
+    dw = CamelliaSubkeyL(10) ^ CamelliaSubkeyR(10), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(10) = CamelliaSubkeyL(10) ^ dw, CamelliaSubkeyL(10) = dw;
+    dw = CamelliaSubkeyL(11) ^ CamelliaSubkeyR(11), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(11) = CamelliaSubkeyL(11) ^ dw, CamelliaSubkeyL(11) = dw;
+    dw = CamelliaSubkeyL(12) ^ CamelliaSubkeyR(12), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(12) = CamelliaSubkeyL(12) ^ dw, CamelliaSubkeyL(12) = dw;
+    dw = CamelliaSubkeyL(13) ^ CamelliaSubkeyR(13), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(13) = CamelliaSubkeyL(13) ^ dw, CamelliaSubkeyL(13) = dw;
+    dw = CamelliaSubkeyL(14) ^ CamelliaSubkeyR(14), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(14) = CamelliaSubkeyL(14) ^ dw, CamelliaSubkeyL(14) = dw;
+    dw = CamelliaSubkeyL(15) ^ CamelliaSubkeyR(15), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(15) = CamelliaSubkeyL(15) ^ dw, CamelliaSubkeyL(15) = dw;
+    dw = CamelliaSubkeyL(18) ^ CamelliaSubkeyR(18), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(18) = CamelliaSubkeyL(18) ^ dw, CamelliaSubkeyL(18) = dw;
+    dw = CamelliaSubkeyL(19) ^ CamelliaSubkeyR(19), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(19) = CamelliaSubkeyL(19) ^ dw, CamelliaSubkeyL(19) = dw;
+    dw = CamelliaSubkeyL(20) ^ CamelliaSubkeyR(20), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(20) = CamelliaSubkeyL(20) ^ dw, CamelliaSubkeyL(20) = dw;
+    dw = CamelliaSubkeyL(21) ^ CamelliaSubkeyR(21), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(21) = CamelliaSubkeyL(21) ^ dw, CamelliaSubkeyL(21) = dw;
+    dw = CamelliaSubkeyL(22) ^ CamelliaSubkeyR(22), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(22) = CamelliaSubkeyL(22) ^ dw, CamelliaSubkeyL(22) = dw;
+    dw = CamelliaSubkeyL(23) ^ CamelliaSubkeyR(23), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(23) = CamelliaSubkeyL(23) ^ dw, CamelliaSubkeyL(23) = dw;
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(subL, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(subR, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return 0;
+}
+
+static int camellia_setup256(const unsigned char *key, u32 *subkey)
+{
+    u32 kll,klr,krl,krr;           /* left half of key */
+    u32 krll,krlr,krrl,krrr;       /* right half of key */
+    u32 il, ir, t0, t1, w0, w1;    /* temporary variables */
+    u32 kw4l, kw4r, dw, tl, tr;
+
+#ifdef WOLFSSL_SMALL_STACK
+    u32* subL;
+    u32* subR;
+
+    subL = (u32*) XMALLOC(sizeof(u32) * 34, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (subL == NULL)
+        return MEMORY_E;
+
+    subR = (u32*) XMALLOC(sizeof(u32) * 34, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (subR == NULL) {
+        XFREE(subL, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        return MEMORY_E;
+    }
+#else
+    u32 subL[34];
+    u32 subR[34];
+#endif
+
+    /**
+     *  key = (kll || klr || krl || krr || krll || krlr || krrl || krrr)
+     *  (|| is concatination)
+     */
+
+    kll  = GETU32(key     );
+    klr  = GETU32(key +  4);
+    krl  = GETU32(key +  8);
+    krr  = GETU32(key + 12);
+    krll = GETU32(key + 16);
+    krlr = GETU32(key + 20);
+    krrl = GETU32(key + 24);
+    krrr = GETU32(key + 28);
+
+    /* generate KL dependent subkeys */
+    subl(0) = kll; subr(0) = klr;
+    subl(1) = krl; subr(1) = krr;
+    CAMELLIA_ROLDQo32(kll, klr, krl, krr, w0, w1, 45);
+    subl(12) = kll; subr(12) = klr;
+    subl(13) = krl; subr(13) = krr;
+    CAMELLIA_ROLDQ(kll, klr, krl, krr, w0, w1, 15);
+    subl(16) = kll; subr(16) = klr;
+    subl(17) = krl; subr(17) = krr;
+    CAMELLIA_ROLDQ(kll, klr, krl, krr, w0, w1, 17);
+    subl(22) = kll; subr(22) = klr;
+    subl(23) = krl; subr(23) = krr;
+    CAMELLIA_ROLDQo32(kll, klr, krl, krr, w0, w1, 34);
+    subl(30) = kll; subr(30) = klr;
+    subl(31) = krl; subr(31) = krr;
+
+    /* generate KR dependent subkeys */
+    CAMELLIA_ROLDQ(krll, krlr, krrl, krrr, w0, w1, 15);
+    subl(4) = krll; subr(4) = krlr;
+    subl(5) = krrl; subr(5) = krrr;
+    CAMELLIA_ROLDQ(krll, krlr, krrl, krrr, w0, w1, 15);
+    subl(8) = krll; subr(8) = krlr;
+    subl(9) = krrl; subr(9) = krrr;
+    CAMELLIA_ROLDQ(krll, krlr, krrl, krrr, w0, w1, 30);
+    subl(18) = krll; subr(18) = krlr;
+    subl(19) = krrl; subr(19) = krrr;
+    CAMELLIA_ROLDQo32(krll, krlr, krrl, krrr, w0, w1, 34);
+    subl(26) = krll; subr(26) = krlr;
+    subl(27) = krrl; subr(27) = krrr;
+    CAMELLIA_ROLDQo32(krll, krlr, krrl, krrr, w0, w1, 34);
+
+    /* generate KA */
+    kll = subl(0) ^ krll; klr = subr(0) ^ krlr;
+    krl = subl(1) ^ krrl; krr = subr(1) ^ krrr;
+    CAMELLIA_F(kll, klr,
+	       CAMELLIA_SIGMA1L, CAMELLIA_SIGMA1R,
+	       w0, w1, il, ir, t0, t1);
+    krl ^= w0; krr ^= w1;
+    CAMELLIA_F(krl, krr,
+	       CAMELLIA_SIGMA2L, CAMELLIA_SIGMA2R,
+	       kll, klr, il, ir, t0, t1);
+    kll ^= krll; klr ^= krlr;
+    CAMELLIA_F(kll, klr,
+	       CAMELLIA_SIGMA3L, CAMELLIA_SIGMA3R,
+	       krl, krr, il, ir, t0, t1);
+    krl ^= w0 ^ krrl; krr ^= w1 ^ krrr;
+    CAMELLIA_F(krl, krr,
+	       CAMELLIA_SIGMA4L, CAMELLIA_SIGMA4R,
+	       w0, w1, il, ir, t0, t1);
+    kll ^= w0; klr ^= w1;
+
+    /* generate KB */
+    krll ^= kll; krlr ^= klr;
+    krrl ^= krl; krrr ^= krr;
+    CAMELLIA_F(krll, krlr,
+	       CAMELLIA_SIGMA5L, CAMELLIA_SIGMA5R,
+	       w0, w1, il, ir, t0, t1);
+    krrl ^= w0; krrr ^= w1;
+    CAMELLIA_F(krrl, krrr,
+	       CAMELLIA_SIGMA6L, CAMELLIA_SIGMA6R,
+	       w0, w1, il, ir, t0, t1);
+    krll ^= w0; krlr ^= w1;
+
+    /* generate KA dependent subkeys */
+    CAMELLIA_ROLDQ(kll, klr, krl, krr, w0, w1, 15);
+    subl(6) = kll; subr(6) = klr;
+    subl(7) = krl; subr(7) = krr;
+    CAMELLIA_ROLDQ(kll, klr, krl, krr, w0, w1, 30);
+    subl(14) = kll; subr(14) = klr;
+    subl(15) = krl; subr(15) = krr;
+    subl(24) = klr; subr(24) = krl;
+    subl(25) = krr; subr(25) = kll;
+    CAMELLIA_ROLDQo32(kll, klr, krl, krr, w0, w1, 49);
+    subl(28) = kll; subr(28) = klr;
+    subl(29) = krl; subr(29) = krr;
+
+    /* generate KB dependent subkeys */
+    subl(2) = krll; subr(2) = krlr;
+    subl(3) = krrl; subr(3) = krrr;
+    CAMELLIA_ROLDQ(krll, krlr, krrl, krrr, w0, w1, 30);
+    subl(10) = krll; subr(10) = krlr;
+    subl(11) = krrl; subr(11) = krrr;
+    CAMELLIA_ROLDQ(krll, krlr, krrl, krrr, w0, w1, 30);
+    subl(20) = krll; subr(20) = krlr;
+    subl(21) = krrl; subr(21) = krrr;
+    CAMELLIA_ROLDQo32(krll, krlr, krrl, krrr, w0, w1, 51);
+    subl(32) = krll; subr(32) = krlr;
+    subl(33) = krrl; subr(33) = krrr;
+
+    /* absorb kw2 to other subkeys */
+    subl(3) ^= subl(1); subr(3) ^= subr(1);
+    subl(5) ^= subl(1); subr(5) ^= subr(1);
+    subl(7) ^= subl(1); subr(7) ^= subr(1);
+    subl(1) ^= subr(1) & ~subr(9);
+    dw = subl(1) & subl(9), subr(1) ^= CAMELLIA_RL1(dw);
+    subl(11) ^= subl(1); subr(11) ^= subr(1);
+    subl(13) ^= subl(1); subr(13) ^= subr(1);
+    subl(15) ^= subl(1); subr(15) ^= subr(1);
+    subl(1) ^= subr(1) & ~subr(17);
+    dw = subl(1) & subl(17), subr(1) ^= CAMELLIA_RL1(dw);
+    subl(19) ^= subl(1); subr(19) ^= subr(1);
+    subl(21) ^= subl(1); subr(21) ^= subr(1);
+    subl(23) ^= subl(1); subr(23) ^= subr(1);
+    subl(1) ^= subr(1) & ~subr(25);
+    dw = subl(1) & subl(25), subr(1) ^= CAMELLIA_RL1(dw);
+    subl(27) ^= subl(1); subr(27) ^= subr(1);
+    subl(29) ^= subl(1); subr(29) ^= subr(1);
+    subl(31) ^= subl(1); subr(31) ^= subr(1);
+    subl(32) ^= subl(1); subr(32) ^= subr(1);
+
+    /* absorb kw4 to other subkeys */
+    kw4l = subl(33); kw4r = subr(33);
+    subl(30) ^= kw4l; subr(30) ^= kw4r;
+    subl(28) ^= kw4l; subr(28) ^= kw4r;
+    subl(26) ^= kw4l; subr(26) ^= kw4r;
+    kw4l ^= kw4r & ~subr(24);
+    dw = kw4l & subl(24), kw4r ^= CAMELLIA_RL1(dw);
+    subl(22) ^= kw4l; subr(22) ^= kw4r;
+    subl(20) ^= kw4l; subr(20) ^= kw4r;
+    subl(18) ^= kw4l; subr(18) ^= kw4r;
+    kw4l ^= kw4r & ~subr(16);
+    dw = kw4l & subl(16), kw4r ^= CAMELLIA_RL1(dw);
+    subl(14) ^= kw4l; subr(14) ^= kw4r;
+    subl(12) ^= kw4l; subr(12) ^= kw4r;
+    subl(10) ^= kw4l; subr(10) ^= kw4r;
+    kw4l ^= kw4r & ~subr(8);
+    dw = kw4l & subl(8), kw4r ^= CAMELLIA_RL1(dw);
+    subl(6) ^= kw4l; subr(6) ^= kw4r;
+    subl(4) ^= kw4l; subr(4) ^= kw4r;
+    subl(2) ^= kw4l; subr(2) ^= kw4r;
+    subl(0) ^= kw4l; subr(0) ^= kw4r;
+
+    /* key XOR is end of F-function */
+    CamelliaSubkeyL(0) = subl(0) ^ subl(2);
+    CamelliaSubkeyR(0) = subr(0) ^ subr(2);
+    CamelliaSubkeyL(2) = subl(3);
+    CamelliaSubkeyR(2) = subr(3);
+    CamelliaSubkeyL(3) = subl(2) ^ subl(4);
+    CamelliaSubkeyR(3) = subr(2) ^ subr(4);
+    CamelliaSubkeyL(4) = subl(3) ^ subl(5);
+    CamelliaSubkeyR(4) = subr(3) ^ subr(5);
+    CamelliaSubkeyL(5) = subl(4) ^ subl(6);
+    CamelliaSubkeyR(5) = subr(4) ^ subr(6);
+    CamelliaSubkeyL(6) = subl(5) ^ subl(7);
+    CamelliaSubkeyR(6) = subr(5) ^ subr(7);
+    tl = subl(10) ^ (subr(10) & ~subr(8));
+    dw = tl & subl(8), tr = subr(10) ^ CAMELLIA_RL1(dw);
+    CamelliaSubkeyL(7) = subl(6) ^ tl;
+    CamelliaSubkeyR(7) = subr(6) ^ tr;
+    CamelliaSubkeyL(8) = subl(8);
+    CamelliaSubkeyR(8) = subr(8);
+    CamelliaSubkeyL(9) = subl(9);
+    CamelliaSubkeyR(9) = subr(9);
+    tl = subl(7) ^ (subr(7) & ~subr(9));
+    dw = tl & subl(9), tr = subr(7) ^ CAMELLIA_RL1(dw);
+    CamelliaSubkeyL(10) = tl ^ subl(11);
+    CamelliaSubkeyR(10) = tr ^ subr(11);
+    CamelliaSubkeyL(11) = subl(10) ^ subl(12);
+    CamelliaSubkeyR(11) = subr(10) ^ subr(12);
+    CamelliaSubkeyL(12) = subl(11) ^ subl(13);
+    CamelliaSubkeyR(12) = subr(11) ^ subr(13);
+    CamelliaSubkeyL(13) = subl(12) ^ subl(14);
+    CamelliaSubkeyR(13) = subr(12) ^ subr(14);
+    CamelliaSubkeyL(14) = subl(13) ^ subl(15);
+    CamelliaSubkeyR(14) = subr(13) ^ subr(15);
+    tl = subl(18) ^ (subr(18) & ~subr(16));
+    dw = tl & subl(16), tr = subr(18) ^ CAMELLIA_RL1(dw);
+    CamelliaSubkeyL(15) = subl(14) ^ tl;
+    CamelliaSubkeyR(15) = subr(14) ^ tr;
+    CamelliaSubkeyL(16) = subl(16);
+    CamelliaSubkeyR(16) = subr(16);
+    CamelliaSubkeyL(17) = subl(17);
+    CamelliaSubkeyR(17) = subr(17);
+    tl = subl(15) ^ (subr(15) & ~subr(17));
+    dw = tl & subl(17), tr = subr(15) ^ CAMELLIA_RL1(dw);
+    CamelliaSubkeyL(18) = tl ^ subl(19);
+    CamelliaSubkeyR(18) = tr ^ subr(19);
+    CamelliaSubkeyL(19) = subl(18) ^ subl(20);
+    CamelliaSubkeyR(19) = subr(18) ^ subr(20);
+    CamelliaSubkeyL(20) = subl(19) ^ subl(21);
+    CamelliaSubkeyR(20) = subr(19) ^ subr(21);
+    CamelliaSubkeyL(21) = subl(20) ^ subl(22);
+    CamelliaSubkeyR(21) = subr(20) ^ subr(22);
+    CamelliaSubkeyL(22) = subl(21) ^ subl(23);
+    CamelliaSubkeyR(22) = subr(21) ^ subr(23);
+    tl = subl(26) ^ (subr(26) & ~subr(24));
+    dw = tl & subl(24), tr = subr(26) ^ CAMELLIA_RL1(dw);
+    CamelliaSubkeyL(23) = subl(22) ^ tl;
+    CamelliaSubkeyR(23) = subr(22) ^ tr;
+    CamelliaSubkeyL(24) = subl(24);
+    CamelliaSubkeyR(24) = subr(24);
+    CamelliaSubkeyL(25) = subl(25);
+    CamelliaSubkeyR(25) = subr(25);
+    tl = subl(23) ^ (subr(23) &  ~subr(25));
+    dw = tl & subl(25), tr = subr(23) ^ CAMELLIA_RL1(dw);
+    CamelliaSubkeyL(26) = tl ^ subl(27);
+    CamelliaSubkeyR(26) = tr ^ subr(27);
+    CamelliaSubkeyL(27) = subl(26) ^ subl(28);
+    CamelliaSubkeyR(27) = subr(26) ^ subr(28);
+    CamelliaSubkeyL(28) = subl(27) ^ subl(29);
+    CamelliaSubkeyR(28) = subr(27) ^ subr(29);
+    CamelliaSubkeyL(29) = subl(28) ^ subl(30);
+    CamelliaSubkeyR(29) = subr(28) ^ subr(30);
+    CamelliaSubkeyL(30) = subl(29) ^ subl(31);
+    CamelliaSubkeyR(30) = subr(29) ^ subr(31);
+    CamelliaSubkeyL(31) = subl(30);
+    CamelliaSubkeyR(31) = subr(30);
+    CamelliaSubkeyL(32) = subl(32) ^ subl(31);
+    CamelliaSubkeyR(32) = subr(32) ^ subr(31);
+
+    /* apply the inverse of the last half of P-function */
+    dw = CamelliaSubkeyL(2) ^ CamelliaSubkeyR(2), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(2) = CamelliaSubkeyL(2) ^ dw, CamelliaSubkeyL(2) = dw;
+    dw = CamelliaSubkeyL(3) ^ CamelliaSubkeyR(3), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(3) = CamelliaSubkeyL(3) ^ dw, CamelliaSubkeyL(3) = dw;
+    dw = CamelliaSubkeyL(4) ^ CamelliaSubkeyR(4), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(4) = CamelliaSubkeyL(4) ^ dw, CamelliaSubkeyL(4) = dw;
+    dw = CamelliaSubkeyL(5) ^ CamelliaSubkeyR(5), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(5) = CamelliaSubkeyL(5) ^ dw, CamelliaSubkeyL(5) = dw;
+    dw = CamelliaSubkeyL(6) ^ CamelliaSubkeyR(6), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(6) = CamelliaSubkeyL(6) ^ dw, CamelliaSubkeyL(6) = dw;
+    dw = CamelliaSubkeyL(7) ^ CamelliaSubkeyR(7), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(7) = CamelliaSubkeyL(7) ^ dw, CamelliaSubkeyL(7) = dw;
+    dw = CamelliaSubkeyL(10) ^ CamelliaSubkeyR(10), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(10) = CamelliaSubkeyL(10) ^ dw, CamelliaSubkeyL(10) = dw;
+    dw = CamelliaSubkeyL(11) ^ CamelliaSubkeyR(11), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(11) = CamelliaSubkeyL(11) ^ dw, CamelliaSubkeyL(11) = dw;
+    dw = CamelliaSubkeyL(12) ^ CamelliaSubkeyR(12), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(12) = CamelliaSubkeyL(12) ^ dw, CamelliaSubkeyL(12) = dw;
+    dw = CamelliaSubkeyL(13) ^ CamelliaSubkeyR(13), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(13) = CamelliaSubkeyL(13) ^ dw, CamelliaSubkeyL(13) = dw;
+    dw = CamelliaSubkeyL(14) ^ CamelliaSubkeyR(14), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(14) = CamelliaSubkeyL(14) ^ dw, CamelliaSubkeyL(14) = dw;
+    dw = CamelliaSubkeyL(15) ^ CamelliaSubkeyR(15), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(15) = CamelliaSubkeyL(15) ^ dw, CamelliaSubkeyL(15) = dw;
+    dw = CamelliaSubkeyL(18) ^ CamelliaSubkeyR(18), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(18) = CamelliaSubkeyL(18) ^ dw, CamelliaSubkeyL(18) = dw;
+    dw = CamelliaSubkeyL(19) ^ CamelliaSubkeyR(19), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(19) = CamelliaSubkeyL(19) ^ dw, CamelliaSubkeyL(19) = dw;
+    dw = CamelliaSubkeyL(20) ^ CamelliaSubkeyR(20), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(20) = CamelliaSubkeyL(20) ^ dw, CamelliaSubkeyL(20) = dw;
+    dw = CamelliaSubkeyL(21) ^ CamelliaSubkeyR(21), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(21) = CamelliaSubkeyL(21) ^ dw, CamelliaSubkeyL(21) = dw;
+    dw = CamelliaSubkeyL(22) ^ CamelliaSubkeyR(22), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(22) = CamelliaSubkeyL(22) ^ dw, CamelliaSubkeyL(22) = dw;
+    dw = CamelliaSubkeyL(23) ^ CamelliaSubkeyR(23), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(23) = CamelliaSubkeyL(23) ^ dw, CamelliaSubkeyL(23) = dw;
+    dw = CamelliaSubkeyL(26) ^ CamelliaSubkeyR(26), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(26) = CamelliaSubkeyL(26) ^ dw, CamelliaSubkeyL(26) = dw;
+    dw = CamelliaSubkeyL(27) ^ CamelliaSubkeyR(27), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(27) = CamelliaSubkeyL(27) ^ dw, CamelliaSubkeyL(27) = dw;
+    dw = CamelliaSubkeyL(28) ^ CamelliaSubkeyR(28), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(28) = CamelliaSubkeyL(28) ^ dw, CamelliaSubkeyL(28) = dw;
+    dw = CamelliaSubkeyL(29) ^ CamelliaSubkeyR(29), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(29) = CamelliaSubkeyL(29) ^ dw, CamelliaSubkeyL(29) = dw;
+    dw = CamelliaSubkeyL(30) ^ CamelliaSubkeyR(30), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(30) = CamelliaSubkeyL(30) ^ dw, CamelliaSubkeyL(30) = dw;
+    dw = CamelliaSubkeyL(31) ^ CamelliaSubkeyR(31), dw = CAMELLIA_RL8(dw);
+    CamelliaSubkeyR(31) = CamelliaSubkeyL(31) ^ dw,CamelliaSubkeyL(31) = dw;
+    
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(subL, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(subR, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return 0;
+}
+
+static int camellia_setup192(const unsigned char *key, u32 *subkey)
+{
+    unsigned char kk[32];
+    u32 krll, krlr, krrl,krrr;
+
+    memcpy(kk, key, 24);
+    memcpy((unsigned char *)&krll, key+16,4);
+    memcpy((unsigned char *)&krlr, key+20,4);
+    krrl = ~krll;
+    krrr = ~krlr;
+    memcpy(kk+24, (unsigned char *)&krrl, 4);
+    memcpy(kk+28, (unsigned char *)&krrr, 4);
+
+    return camellia_setup256(kk, subkey);
+}
+
+
+/**
+ * Stuff related to camellia encryption/decryption
+ *
+ * "io" must be 4byte aligned and big-endian data.
+ */
+static void camellia_encrypt128(const u32 *subkey, u32 *io)
+{
+    u32 il, ir, t0, t1;
+
+    /* pre whitening but absorb kw2*/
+    io[0] ^= CamelliaSubkeyL(0);
+    io[1] ^= CamelliaSubkeyR(0);
+    /* main iteration */
+
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(2),CamelliaSubkeyR(2),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(3),CamelliaSubkeyR(3),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(4),CamelliaSubkeyR(4),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(5),CamelliaSubkeyR(5),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(6),CamelliaSubkeyR(6),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(7),CamelliaSubkeyR(7),
+		     io[0],io[1],il,ir,t0,t1);
+
+    CAMELLIA_FLS(io[0],io[1],io[2],io[3],
+		 CamelliaSubkeyL(8),CamelliaSubkeyR(8),
+		 CamelliaSubkeyL(9),CamelliaSubkeyR(9),
+		 t0,t1,il,ir);
+
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(10),CamelliaSubkeyR(10),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(11),CamelliaSubkeyR(11),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(12),CamelliaSubkeyR(12),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(13),CamelliaSubkeyR(13),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(14),CamelliaSubkeyR(14),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(15),CamelliaSubkeyR(15),
+		     io[0],io[1],il,ir,t0,t1);
+
+    CAMELLIA_FLS(io[0],io[1],io[2],io[3],
+		 CamelliaSubkeyL(16),CamelliaSubkeyR(16),
+		 CamelliaSubkeyL(17),CamelliaSubkeyR(17),
+		 t0,t1,il,ir);
+
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(18),CamelliaSubkeyR(18),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(19),CamelliaSubkeyR(19),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(20),CamelliaSubkeyR(20),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(21),CamelliaSubkeyR(21),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(22),CamelliaSubkeyR(22),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(23),CamelliaSubkeyR(23),
+		     io[0],io[1],il,ir,t0,t1);
+
+    /* post whitening but kw4 */
+    io[2] ^= CamelliaSubkeyL(24);
+    io[3] ^= CamelliaSubkeyR(24);
+
+    t0 = io[0];
+    t1 = io[1];
+    io[0] = io[2];
+    io[1] = io[3];
+    io[2] = t0;
+    io[3] = t1;
+	
+    return;
+}
+
+static void camellia_decrypt128(const u32 *subkey, u32 *io)
+{
+    u32 il,ir,t0,t1;               /* temporary valiables */
+    
+    /* pre whitening but absorb kw2*/
+    io[0] ^= CamelliaSubkeyL(24);
+    io[1] ^= CamelliaSubkeyR(24);
+
+    /* main iteration */
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(23),CamelliaSubkeyR(23),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(22),CamelliaSubkeyR(22),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(21),CamelliaSubkeyR(21),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(20),CamelliaSubkeyR(20),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(19),CamelliaSubkeyR(19),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(18),CamelliaSubkeyR(18),
+		     io[0],io[1],il,ir,t0,t1);
+
+    CAMELLIA_FLS(io[0],io[1],io[2],io[3],
+		 CamelliaSubkeyL(17),CamelliaSubkeyR(17),
+		 CamelliaSubkeyL(16),CamelliaSubkeyR(16),
+		 t0,t1,il,ir);
+
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(15),CamelliaSubkeyR(15),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(14),CamelliaSubkeyR(14),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(13),CamelliaSubkeyR(13),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(12),CamelliaSubkeyR(12),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(11),CamelliaSubkeyR(11),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(10),CamelliaSubkeyR(10),
+		     io[0],io[1],il,ir,t0,t1);
+
+    CAMELLIA_FLS(io[0],io[1],io[2],io[3],
+		 CamelliaSubkeyL(9),CamelliaSubkeyR(9),
+		 CamelliaSubkeyL(8),CamelliaSubkeyR(8),
+		 t0,t1,il,ir);
+
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(7),CamelliaSubkeyR(7),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(6),CamelliaSubkeyR(6),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(5),CamelliaSubkeyR(5),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(4),CamelliaSubkeyR(4),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(3),CamelliaSubkeyR(3),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(2),CamelliaSubkeyR(2),
+		     io[0],io[1],il,ir,t0,t1);
+
+    /* post whitening but kw4 */
+    io[2] ^= CamelliaSubkeyL(0);
+    io[3] ^= CamelliaSubkeyR(0);
+
+    t0 = io[0];
+    t1 = io[1];
+    io[0] = io[2];
+    io[1] = io[3];
+    io[2] = t0;
+    io[3] = t1;
+
+    return;
+}
+
+/**
+ * stuff for 192 and 256bit encryption/decryption
+ */
+static void camellia_encrypt256(const u32 *subkey, u32 *io)
+{
+    u32 il,ir,t0,t1;           /* temporary valiables */
+
+    /* pre whitening but absorb kw2*/
+    io[0] ^= CamelliaSubkeyL(0);
+    io[1] ^= CamelliaSubkeyR(0);
+
+    /* main iteration */
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(2),CamelliaSubkeyR(2),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(3),CamelliaSubkeyR(3),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(4),CamelliaSubkeyR(4),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(5),CamelliaSubkeyR(5),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(6),CamelliaSubkeyR(6),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(7),CamelliaSubkeyR(7),
+		     io[0],io[1],il,ir,t0,t1);
+
+    CAMELLIA_FLS(io[0],io[1],io[2],io[3],
+		 CamelliaSubkeyL(8),CamelliaSubkeyR(8),
+		 CamelliaSubkeyL(9),CamelliaSubkeyR(9),
+		 t0,t1,il,ir);
+
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(10),CamelliaSubkeyR(10),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(11),CamelliaSubkeyR(11),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(12),CamelliaSubkeyR(12),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(13),CamelliaSubkeyR(13),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(14),CamelliaSubkeyR(14),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(15),CamelliaSubkeyR(15),
+		     io[0],io[1],il,ir,t0,t1);
+
+    CAMELLIA_FLS(io[0],io[1],io[2],io[3],
+		 CamelliaSubkeyL(16),CamelliaSubkeyR(16),
+		 CamelliaSubkeyL(17),CamelliaSubkeyR(17),
+		 t0,t1,il,ir);
+
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(18),CamelliaSubkeyR(18),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(19),CamelliaSubkeyR(19),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(20),CamelliaSubkeyR(20),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(21),CamelliaSubkeyR(21),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(22),CamelliaSubkeyR(22),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(23),CamelliaSubkeyR(23),
+		     io[0],io[1],il,ir,t0,t1);
+
+    CAMELLIA_FLS(io[0],io[1],io[2],io[3],
+		 CamelliaSubkeyL(24),CamelliaSubkeyR(24),
+		 CamelliaSubkeyL(25),CamelliaSubkeyR(25),
+		 t0,t1,il,ir);
+
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(26),CamelliaSubkeyR(26),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(27),CamelliaSubkeyR(27),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(28),CamelliaSubkeyR(28),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(29),CamelliaSubkeyR(29),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(30),CamelliaSubkeyR(30),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(31),CamelliaSubkeyR(31),
+		     io[0],io[1],il,ir,t0,t1);
+
+    /* post whitening but kw4 */
+    io[2] ^= CamelliaSubkeyL(32);
+    io[3] ^= CamelliaSubkeyR(32);
+
+    t0 = io[0];
+    t1 = io[1];
+    io[0] = io[2];
+    io[1] = io[3];
+    io[2] = t0;
+    io[3] = t1;
+
+    return;
+}
+
+static void camellia_decrypt256(const u32 *subkey, u32 *io)
+{
+    u32 il,ir,t0,t1;           /* temporary valiables */
+
+    /* pre whitening but absorb kw2*/
+    io[0] ^= CamelliaSubkeyL(32);
+    io[1] ^= CamelliaSubkeyR(32);
+	
+    /* main iteration */
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(31),CamelliaSubkeyR(31),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(30),CamelliaSubkeyR(30),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(29),CamelliaSubkeyR(29),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(28),CamelliaSubkeyR(28),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(27),CamelliaSubkeyR(27),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(26),CamelliaSubkeyR(26),
+		     io[0],io[1],il,ir,t0,t1);
+
+    CAMELLIA_FLS(io[0],io[1],io[2],io[3],
+		 CamelliaSubkeyL(25),CamelliaSubkeyR(25),
+		 CamelliaSubkeyL(24),CamelliaSubkeyR(24),
+		 t0,t1,il,ir);
+
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(23),CamelliaSubkeyR(23),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(22),CamelliaSubkeyR(22),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(21),CamelliaSubkeyR(21),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(20),CamelliaSubkeyR(20),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(19),CamelliaSubkeyR(19),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(18),CamelliaSubkeyR(18),
+		     io[0],io[1],il,ir,t0,t1);
+
+    CAMELLIA_FLS(io[0],io[1],io[2],io[3],
+		 CamelliaSubkeyL(17),CamelliaSubkeyR(17),
+		 CamelliaSubkeyL(16),CamelliaSubkeyR(16),
+		 t0,t1,il,ir);
+
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(15),CamelliaSubkeyR(15),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(14),CamelliaSubkeyR(14),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(13),CamelliaSubkeyR(13),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(12),CamelliaSubkeyR(12),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(11),CamelliaSubkeyR(11),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(10),CamelliaSubkeyR(10),
+		     io[0],io[1],il,ir,t0,t1);
+
+    CAMELLIA_FLS(io[0],io[1],io[2],io[3],
+		 CamelliaSubkeyL(9),CamelliaSubkeyR(9),
+		 CamelliaSubkeyL(8),CamelliaSubkeyR(8),
+		 t0,t1,il,ir);
+
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(7),CamelliaSubkeyR(7),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(6),CamelliaSubkeyR(6),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(5),CamelliaSubkeyR(5),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(4),CamelliaSubkeyR(4),
+		     io[0],io[1],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[0],io[1],
+		     CamelliaSubkeyL(3),CamelliaSubkeyR(3),
+		     io[2],io[3],il,ir,t0,t1);
+    CAMELLIA_ROUNDSM(io[2],io[3],
+		     CamelliaSubkeyL(2),CamelliaSubkeyR(2),
+		     io[0],io[1],il,ir,t0,t1);
+
+    /* post whitening but kw4 */
+    io[2] ^= CamelliaSubkeyL(0);
+    io[3] ^= CamelliaSubkeyR(0);
+
+    t0 = io[0];
+    t1 = io[1];
+    io[0] = io[2];
+    io[1] = io[3];
+    io[2] = t0;
+    io[3] = t1;
+
+    return;
+}
+
+/***
+ *
+ * API for compatibility
+ */
+
+static void Camellia_EncryptBlock(const int keyBitLength, 
+			   const unsigned char *plaintext, 
+			   const KEY_TABLE_TYPE keyTable, 
+			   unsigned char *ciphertext)
+{
+    u32 tmp[4];
+
+    tmp[0] = GETU32(plaintext);
+    tmp[1] = GETU32(plaintext + 4);
+    tmp[2] = GETU32(plaintext + 8);
+    tmp[3] = GETU32(plaintext + 12);
+
+    switch (keyBitLength) {
+    case 128:
+	camellia_encrypt128(keyTable, tmp);
+	break;
+    case 192:
+	/* fall through */
+    case 256:
+	camellia_encrypt256(keyTable, tmp);
+	break;
+    default:
+	break;
+    }
+
+    PUTU32(ciphertext, tmp[0]);
+    PUTU32(ciphertext + 4, tmp[1]);
+    PUTU32(ciphertext + 8, tmp[2]);
+    PUTU32(ciphertext + 12, tmp[3]);
+}
+
+static void Camellia_DecryptBlock(const int keyBitLength, 
+			   const unsigned char *ciphertext, 
+			   const KEY_TABLE_TYPE keyTable, 
+			   unsigned char *plaintext)
+{
+    u32 tmp[4];
+
+    tmp[0] = GETU32(ciphertext);
+    tmp[1] = GETU32(ciphertext + 4);
+    tmp[2] = GETU32(ciphertext + 8);
+    tmp[3] = GETU32(ciphertext + 12);
+
+    switch (keyBitLength) {
+    case 128:
+	camellia_decrypt128(keyTable, tmp);
+	break;
+    case 192:
+	/* fall through */
+    case 256:
+	camellia_decrypt256(keyTable, tmp);
+	break;
+    default:
+	break;
+    }
+    PUTU32(plaintext, tmp[0]);
+    PUTU32(plaintext + 4, tmp[1]);
+    PUTU32(plaintext + 8, tmp[2]);
+    PUTU32(plaintext + 12, tmp[3]);
+}
+
+
+
+/* wolfCrypt wrappers to the Camellia code */
+
+int wc_CamelliaSetKey(Camellia* cam, const byte* key, word32 len, const byte* iv)
+{
+    int ret = 0;
+
+    if (cam == NULL) return BAD_FUNC_ARG;
+
+    XMEMSET(cam->key, 0, sizeof(KEY_TABLE_TYPE));
+
+    switch (len) {
+        case 16:
+        	ret = camellia_setup128(key, cam->key);
+            break;
+        case 24:
+        	ret = camellia_setup192(key, cam->key);
+            break;
+        case 32:
+            ret = camellia_setup256(key, cam->key);
+            break;
+        default:
+            return BAD_FUNC_ARG;
+    }
+
+    if (ret != 0)
+        return ret;
+
+    cam->keySz = len * 8;
+
+    return wc_CamelliaSetIV(cam, iv);
+}
+
+
+int wc_CamelliaSetIV(Camellia* cam, const byte* iv)
+{
+    if (cam == NULL)
+        return BAD_FUNC_ARG;
+
+    if (iv)
+        XMEMCPY(cam->reg, iv, CAMELLIA_BLOCK_SIZE);
+    else
+        XMEMSET(cam->reg,  0, CAMELLIA_BLOCK_SIZE);
+
+    return 0;
+}
+
+
+void wc_CamelliaEncryptDirect(Camellia* cam, byte* out, const byte* in)
+{
+    Camellia_EncryptBlock(cam->keySz, in, cam->key, out);
+}
+
+
+void wc_CamelliaDecryptDirect(Camellia* cam, byte* out, const byte* in)
+{
+    Camellia_DecryptBlock(cam->keySz, in, cam->key, out);
+}
+
+
+void wc_CamelliaCbcEncrypt(Camellia* cam, byte* out, const byte* in, word32 sz)
+{
+    word32 blocks = sz / CAMELLIA_BLOCK_SIZE;
+
+    while (blocks--) {
+        xorbuf((byte*)cam->reg, in, CAMELLIA_BLOCK_SIZE);
+        Camellia_EncryptBlock(cam->keySz, (byte*)cam->reg,
+                                                     cam->key, (byte*)cam->reg);
+        XMEMCPY(out, cam->reg, CAMELLIA_BLOCK_SIZE);
+
+        out += CAMELLIA_BLOCK_SIZE;
+        in  += CAMELLIA_BLOCK_SIZE;
+    }
+}
+
+
+void wc_CamelliaCbcDecrypt(Camellia* cam, byte* out, const byte* in, word32 sz)
+{
+    word32 blocks = sz / CAMELLIA_BLOCK_SIZE;
+
+    while (blocks--) {
+        XMEMCPY(cam->tmp, in, CAMELLIA_BLOCK_SIZE);
+        Camellia_DecryptBlock(cam->keySz, (byte*)cam->tmp, cam->key, out);
+        xorbuf(out, (byte*)cam->reg, CAMELLIA_BLOCK_SIZE);
+        XMEMCPY(cam->reg, cam->tmp, CAMELLIA_BLOCK_SIZE);
+
+        out += CAMELLIA_BLOCK_SIZE;
+        in  += CAMELLIA_BLOCK_SIZE;
+    }
+}
+
+
+#endif /* HAVE_CAMELLIA */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/chacha.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/chacha.c
new file mode 100644
index 0000000..4e95bdb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/chacha.c
@@ -0,0 +1,251 @@
+/* chacha.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ *
+ *  based from
+ *  chacha-ref.c version 20080118
+ *  D. J. Bernstein
+ *  Public domain.
+ */
+
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifdef HAVE_CHACHA
+
+#include 
+#include 
+#include 
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+#ifdef CHACHA_AEAD_TEST
+    #include 
+#endif
+
+#ifdef BIG_ENDIAN_ORDER
+    #define LITTLE32(x) ByteReverseWord32(x)
+#else
+    #define LITTLE32(x) (x)
+#endif
+
+/* Number of rounds */
+#define ROUNDS  20
+
+#define U32C(v) (v##U)
+#define U32V(v) ((word32)(v) & U32C(0xFFFFFFFF))
+#define U8TO32_LITTLE(p) LITTLE32(((word32*)(p))[0])
+
+#define ROTATE(v,c) rotlFixed(v, c)
+#define XOR(v,w)    ((v) ^ (w))
+#define PLUS(v,w)   (U32V((v) + (w)))
+#define PLUSONE(v)  (PLUS((v),1))
+
+#define QUARTERROUND(a,b,c,d) \
+  x[a] = PLUS(x[a],x[b]); x[d] = ROTATE(XOR(x[d],x[a]),16); \
+  x[c] = PLUS(x[c],x[d]); x[b] = ROTATE(XOR(x[b],x[c]),12); \
+  x[a] = PLUS(x[a],x[b]); x[d] = ROTATE(XOR(x[d],x[a]), 8); \
+  x[c] = PLUS(x[c],x[d]); x[b] = ROTATE(XOR(x[b],x[c]), 7);
+
+
+/**
+  * Set up iv(nonce). Earlier versions used 64 bits instead of 96, this version
+  * uses the typical AEAD 96 bit nonce and can do record sizes of 256 GB.
+  */
+int wc_Chacha_SetIV(ChaCha* ctx, const byte* inIv, word32 counter)
+{
+    word32 temp[3];       /* used for alignment of memory */
+
+#ifdef CHACHA_AEAD_TEST
+    word32 i;
+    printf("NONCE : ");
+    for (i = 0; i < 12; i++) {
+        printf("%02x", inIv[i]);
+    }
+    printf("\n\n");
+#endif
+
+    if (ctx == NULL)
+        return BAD_FUNC_ARG;
+
+    XMEMCPY(temp, inIv, 12);
+
+    ctx->X[12] = LITTLE32(counter); /* block counter */
+    ctx->X[13] = LITTLE32(temp[0]); /* fixed variable from nonce */
+    ctx->X[14] = LITTLE32(temp[1]); /* counter from nonce */
+    ctx->X[15] = LITTLE32(temp[2]); /* counter from nonce */
+
+    return 0;
+}
+
+/* "expand 32-byte k" as unsigned 32 byte */
+static const word32 sigma[4] = {0x61707865, 0x3320646e, 0x79622d32, 0x6b206574};
+/* "expand 16-byte k" as unsigned 16 byte */
+static const word32 tau[4] = {0x61707865, 0x3120646e, 0x79622d36, 0x6b206574};
+
+/**
+  * Key setup. 8 word iv (nonce)
+  */
+int wc_Chacha_SetKey(ChaCha* ctx, const byte* key, word32 keySz)
+{
+    const word32* constants;
+    const byte*   k;
+
+#ifdef XSTREAM_ALIGN
+    word32 alignKey[8];
+#endif
+
+    if (ctx == NULL)
+        return BAD_FUNC_ARG;
+
+    if (keySz != 16 && keySz != 32)
+        return BAD_FUNC_ARG;
+
+#ifdef XSTREAM_ALIGN
+    if ((wolfssl_word)key % 4) {
+        WOLFSSL_MSG("wc_ChachaSetKey unaligned key");
+        XMEMCPY(alignKey, key, keySz);
+        k = (byte*)alignKey;
+    }
+    else {
+        k = key;
+    }
+#else
+    k = key;
+#endif /* XSTREAM_ALIGN */
+
+#ifdef CHACHA_AEAD_TEST
+    word32 i;
+    printf("ChaCha key used :\n");
+    for (i = 0; i < keySz; i++) {
+        printf("%02x", key[i]);
+        if ((i + 1) % 8 == 0)
+           printf("\n");
+    }
+    printf("\n\n");
+#endif
+
+    ctx->X[4] = U8TO32_LITTLE(k +  0);
+    ctx->X[5] = U8TO32_LITTLE(k +  4);
+    ctx->X[6] = U8TO32_LITTLE(k +  8);
+    ctx->X[7] = U8TO32_LITTLE(k + 12);
+    if (keySz == 32) {
+        k += 16;
+        constants = sigma;
+    }
+    else {
+        constants = tau;
+    }
+    ctx->X[ 8] = U8TO32_LITTLE(k +  0);
+    ctx->X[ 9] = U8TO32_LITTLE(k +  4);
+    ctx->X[10] = U8TO32_LITTLE(k +  8);
+    ctx->X[11] = U8TO32_LITTLE(k + 12);
+    ctx->X[ 0] = constants[0];
+    ctx->X[ 1] = constants[1];
+    ctx->X[ 2] = constants[2];
+    ctx->X[ 3] = constants[3];
+
+    return 0;
+}
+
+/**
+  * Converts word into bytes with rotations having been done.
+  */
+static INLINE void wc_Chacha_wordtobyte(word32 output[16], const word32 input[16])
+{
+    word32 x[16];
+    word32 i;
+
+    for (i = 0; i < 16; i++) {
+        x[i] = input[i];
+    }
+
+    for (i = (ROUNDS); i > 0; i -= 2) {
+        QUARTERROUND(0, 4,  8, 12)
+        QUARTERROUND(1, 5,  9, 13)
+        QUARTERROUND(2, 6, 10, 14)
+        QUARTERROUND(3, 7, 11, 15)
+        QUARTERROUND(0, 5, 10, 15)
+        QUARTERROUND(1, 6, 11, 12)
+        QUARTERROUND(2, 7,  8, 13)
+        QUARTERROUND(3, 4,  9, 14)
+    }
+
+    for (i = 0; i < 16; i++) {
+        x[i] = PLUS(x[i], input[i]);
+    }
+
+    for (i = 0; i < 16; i++) {
+        output[i] = LITTLE32(x[i]);
+    }
+}
+
+/**
+  * Encrypt a stream of bytes
+  */
+static void wc_Chacha_encrypt_bytes(ChaCha* ctx, const byte* m, byte* c,
+                                 word32 bytes)
+{
+    byte*  output;
+    word32 temp[16]; /* used to make sure aligned */
+    word32 i;
+
+    output = (byte*)temp;
+
+    if (!bytes) return;
+    for (;;) {
+        wc_Chacha_wordtobyte(temp, ctx->X);
+        ctx->X[12] = PLUSONE(ctx->X[12]);
+        if (bytes <= 64) {
+            for (i = 0; i < bytes; ++i) {
+                c[i] = m[i] ^ output[i];
+            }
+            return;
+        }
+        for (i = 0; i < 64; ++i) {
+            c[i] = m[i] ^ output[i];
+        }
+        bytes -= 64;
+        c += 64;
+        m += 64;
+    }
+}
+
+/**
+  * API to encrypt/decrypt a message of any size.
+  */
+int wc_Chacha_Process(ChaCha* ctx, byte* output, const byte* input, word32 msglen)
+{
+    if (ctx == NULL)
+        return BAD_FUNC_ARG;
+
+    wc_Chacha_encrypt_bytes(ctx, input, output, msglen);
+
+    return 0;
+}
+
+#endif /* HAVE_CHACHA*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/chacha20_poly1305.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/chacha20_poly1305.c
new file mode 100644
index 0000000..4a2b1be
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/chacha20_poly1305.c
@@ -0,0 +1,274 @@
+/* chacha.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#if defined(HAVE_CHACHA) && defined(HAVE_POLY1305)
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifdef NO_INLINE
+#include 
+#else
+#include 
+#endif
+
+#ifdef CHACHA_AEAD_TEST
+#include 
+#endif
+
+#define CHACHA20_POLY1305_AEAD_INITIAL_COUNTER  0
+#define CHACHA20_POLY1305_MAC_PADDING_ALIGNMENT 16
+
+static void word32ToLittle64(const word32 inLittle32, byte outLittle64[8]);
+static int calculateAuthTag(
+                  const byte inAuthKey[CHACHA20_POLY1305_AEAD_KEYSIZE],
+                  const byte* inAAD, const word32 inAADLen,
+                  const byte *inCiphertext, const word32 inCiphertextLen,
+                  byte outAuthTag[CHACHA20_POLY1305_AEAD_AUTHTAG_SIZE]);
+
+int wc_ChaCha20Poly1305_Encrypt(
+                const byte inKey[CHACHA20_POLY1305_AEAD_KEYSIZE],
+                const byte inIV[CHACHA20_POLY1305_AEAD_IV_SIZE],
+                const byte* inAAD, const word32 inAADLen,
+                const byte* inPlaintext, const word32 inPlaintextLen,
+                byte* outCiphertext,
+                byte outAuthTag[CHACHA20_POLY1305_AEAD_AUTHTAG_SIZE])
+{
+    int err;
+    byte poly1305Key[CHACHA20_POLY1305_AEAD_KEYSIZE];
+    ChaCha chaChaCtx;
+
+    /* Validate function arguments */
+
+    if (!inKey || !inIV ||
+        !inPlaintext || !inPlaintextLen ||
+        !outCiphertext ||
+        !outAuthTag)
+    {
+        return BAD_FUNC_ARG;
+    }
+
+    XMEMSET(poly1305Key, 0, sizeof(poly1305Key));
+
+    /* Create the Poly1305 key */
+    err = wc_Chacha_SetKey(&chaChaCtx, inKey, CHACHA20_POLY1305_AEAD_KEYSIZE);
+    if (err != 0) return err;
+
+    err = wc_Chacha_SetIV(&chaChaCtx, inIV,
+                           CHACHA20_POLY1305_AEAD_INITIAL_COUNTER);
+    if (err != 0) return err;
+
+    err = wc_Chacha_Process(&chaChaCtx, poly1305Key, poly1305Key,
+                             CHACHA20_POLY1305_AEAD_KEYSIZE);
+    if (err != 0) return err;
+
+    /* Encrypt the plaintext using ChaCha20 */
+    err = wc_Chacha_Process(&chaChaCtx, outCiphertext, inPlaintext,
+                            inPlaintextLen);
+    /* Calculate the Poly1305 auth tag */
+    if (err == 0)
+        err = calculateAuthTag(poly1305Key,
+                               inAAD, inAADLen,
+                               outCiphertext, inPlaintextLen,
+                               outAuthTag);
+    ForceZero(poly1305Key, sizeof(poly1305Key));
+
+    return err;
+}
+
+
+int wc_ChaCha20Poly1305_Decrypt(
+                const byte inKey[CHACHA20_POLY1305_AEAD_KEYSIZE],
+                const byte inIV[CHACHA20_POLY1305_AEAD_IV_SIZE],
+                const byte* inAAD, const word32 inAADLen,
+                const byte* inCiphertext, const word32 inCiphertextLen,
+                const byte inAuthTag[CHACHA20_POLY1305_AEAD_AUTHTAG_SIZE],
+                byte* outPlaintext)
+{
+    int err;
+    byte poly1305Key[CHACHA20_POLY1305_AEAD_KEYSIZE];
+    ChaCha chaChaCtx;
+    byte calculatedAuthTag[CHACHA20_POLY1305_AEAD_AUTHTAG_SIZE];
+
+    /* Validate function arguments */
+
+    if (!inKey || !inIV ||
+        !inCiphertext || !inCiphertextLen ||
+        !inAuthTag ||
+        !outPlaintext)
+    {
+        return BAD_FUNC_ARG;
+    }
+
+    XMEMSET(calculatedAuthTag, 0, sizeof(calculatedAuthTag));
+    XMEMSET(poly1305Key, 0, sizeof(poly1305Key));
+
+    /* Create the Poly1305 key */
+    err = wc_Chacha_SetKey(&chaChaCtx, inKey, CHACHA20_POLY1305_AEAD_KEYSIZE);
+    if (err != 0) return err;
+
+    err = wc_Chacha_SetIV(&chaChaCtx, inIV,
+                           CHACHA20_POLY1305_AEAD_INITIAL_COUNTER);
+    if (err != 0) return err;
+
+    err = wc_Chacha_Process(&chaChaCtx, poly1305Key, poly1305Key,
+                             CHACHA20_POLY1305_AEAD_KEYSIZE);
+    if (err != 0) return err;
+
+    /* Calculate the Poly1305 auth tag */
+    err = calculateAuthTag(poly1305Key,
+                           inAAD, inAADLen,
+                           inCiphertext, inCiphertextLen,
+                           calculatedAuthTag);
+
+    /* Compare the calculated auth tag with the received one */
+    if (err == 0 && ConstantCompare(inAuthTag, calculatedAuthTag,
+                                    CHACHA20_POLY1305_AEAD_AUTHTAG_SIZE) != 0)
+    {
+        err = MAC_CMP_FAILED_E;
+    }
+
+    /* Decrypt the received ciphertext */
+    if (err == 0)
+        err = wc_Chacha_Process(&chaChaCtx, outPlaintext, inCiphertext,
+                                inCiphertextLen);
+    ForceZero(poly1305Key, sizeof(poly1305Key));
+
+    return err;
+}
+
+
+static int calculateAuthTag(
+                const byte inAuthKey[CHACHA20_POLY1305_AEAD_KEYSIZE],
+                const byte *inAAD, const word32 inAADLen,
+                const byte *inCiphertext, const word32 inCiphertextLen,
+                 byte outAuthTag[CHACHA20_POLY1305_AEAD_AUTHTAG_SIZE])
+{
+    int err;
+    Poly1305 poly1305Ctx;
+    byte padding[CHACHA20_POLY1305_MAC_PADDING_ALIGNMENT - 1];
+    word32 paddingLen;
+    byte little64[8];
+
+    XMEMSET(padding, 0, sizeof(padding));
+
+    /* Initialize Poly1305 */
+
+    err = wc_Poly1305SetKey(&poly1305Ctx, inAuthKey,
+                            CHACHA20_POLY1305_AEAD_KEYSIZE);
+    if (err)
+    {
+        return err;
+    }
+
+    /* Create the authTag by MAC'ing the following items: */
+
+    /* -- AAD */
+
+    if (inAAD && inAADLen)
+    {
+        err = wc_Poly1305Update(&poly1305Ctx, inAAD, inAADLen);
+
+        /* -- padding1: pad the AAD to 16 bytes */
+
+        paddingLen = -inAADLen & (CHACHA20_POLY1305_MAC_PADDING_ALIGNMENT - 1);
+        if (paddingLen)
+        {
+            err += wc_Poly1305Update(&poly1305Ctx, padding, paddingLen);
+        }
+
+        if (err)
+        {
+            return err;
+        }
+    }
+
+    /* -- Ciphertext */
+
+    err = wc_Poly1305Update(&poly1305Ctx, inCiphertext, inCiphertextLen);
+    if (err)
+    {
+        return err;
+    }
+
+    /* -- padding2: pad the ciphertext to 16 bytes */
+
+    paddingLen = -inCiphertextLen &
+                                  (CHACHA20_POLY1305_MAC_PADDING_ALIGNMENT - 1);
+    if (paddingLen)
+    {
+        err = wc_Poly1305Update(&poly1305Ctx, padding, paddingLen);
+        if (err)
+        {
+            return err;
+        }
+    }
+
+    /* -- AAD length as a 64-bit little endian integer */
+
+    word32ToLittle64(inAADLen, little64);
+
+    err = wc_Poly1305Update(&poly1305Ctx, little64, sizeof(little64));
+    if (err)
+    {
+        return err;
+    }
+
+    /* -- Ciphertext length as a 64-bit little endian integer */
+
+    word32ToLittle64(inCiphertextLen, little64);
+
+    err = wc_Poly1305Update(&poly1305Ctx, little64, sizeof(little64));
+    if (err)
+    {
+        return err;
+    }
+
+    /* Finalize the auth tag */
+
+    err = wc_Poly1305Final(&poly1305Ctx, outAuthTag);
+
+    return err;
+}
+
+
+static void word32ToLittle64(const word32 inLittle32, byte outLittle64[8])
+{
+    XMEMSET(outLittle64, 0, 8);
+
+    outLittle64[0] = (inLittle32 & 0x000000FF);
+    outLittle64[1] = (inLittle32 & 0x0000FF00) >> 8;
+    outLittle64[2] = (inLittle32 & 0x00FF0000) >> 16;
+    outLittle64[3] = (inLittle32 & 0xFF000000) >> 24;
+}
+
+
+#endif /* HAVE_CHACHA && HAVE_POLY1305 */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/coding.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/coding.c
new file mode 100644
index 0000000..6ead79c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/coding.c
@@ -0,0 +1,399 @@
+/* coding.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifndef NO_CODING
+
+#include 
+#include 
+#include 
+
+
+enum {
+    BAD         = 0xFF,  /* invalid encoding */
+    PAD         = '=',
+    PEM_LINE_SZ = 64
+};
+
+
+static
+const byte base64Decode[] = { 62, BAD, BAD, BAD, 63,   /* + starts at 0x2B */
+                              52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
+                              BAD, BAD, BAD, BAD, BAD, BAD, BAD,
+                              0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
+                              10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
+                              20, 21, 22, 23, 24, 25,
+                              BAD, BAD, BAD, BAD, BAD, BAD,
+                              26, 27, 28, 29, 30, 31, 32, 33, 34, 35,
+                              36, 37, 38, 39, 40, 41, 42, 43, 44, 45,
+                              46, 47, 48, 49, 50, 51
+                            };
+
+
+int Base64_Decode(const byte* in, word32 inLen, byte* out, word32* outLen)
+{
+    word32 i = 0;
+    word32 j = 0;
+    word32 plainSz = inLen - ((inLen + (PEM_LINE_SZ - 1)) / PEM_LINE_SZ );
+    const byte maxIdx = (byte)sizeof(base64Decode) + 0x2B - 1;
+
+    plainSz = (plainSz * 3 + 3) / 4;
+    if (plainSz > *outLen) return BAD_FUNC_ARG;
+
+    while (inLen > 3) {
+        byte b1, b2, b3;
+        byte e1 = in[j++];
+        byte e2 = in[j++];
+        byte e3 = in[j++];
+        byte e4 = in[j++];
+
+        int pad3 = 0;
+        int pad4 = 0;
+
+        if (e1 == 0)            /* end file 0's */
+            break;
+        if (e3 == PAD)
+            pad3 = 1;
+        if (e4 == PAD)
+            pad4 = 1;
+
+        if (e1 < 0x2B || e2 < 0x2B || e3 < 0x2B || e4 < 0x2B) {
+            WOLFSSL_MSG("Bad Base64 Decode data, too small");
+            return ASN_INPUT_E;
+        }
+
+        if (e1 > maxIdx || e2 > maxIdx || e3 > maxIdx || e4 > maxIdx) {
+            WOLFSSL_MSG("Bad Base64 Decode data, too big");
+            return ASN_INPUT_E;
+        }
+
+        e1 = base64Decode[e1 - 0x2B];
+        e2 = base64Decode[e2 - 0x2B];
+        e3 = (e3 == PAD) ? 0 : base64Decode[e3 - 0x2B];
+        e4 = (e4 == PAD) ? 0 : base64Decode[e4 - 0x2B];
+
+        b1 = (byte)((e1 << 2) | (e2 >> 4));
+        b2 = (byte)(((e2 & 0xF) << 4) | (e3 >> 2));
+        b3 = (byte)(((e3 & 0x3) << 6) | e4);
+
+        out[i++] = b1;
+        if (!pad3)
+            out[i++] = b2;
+        if (!pad4)
+            out[i++] = b3;
+        else
+            break;
+
+        inLen -= 4;
+        if (inLen && (in[j] == ' ' || in[j] == '\r' || in[j] == '\n')) {
+            byte endLine = in[j++];
+            inLen--;
+            while (inLen && endLine == ' ') {   /* allow trailing whitespace */
+                endLine = in[j++];
+                inLen--;
+            }
+            if (endLine == '\r') {
+                if (inLen) {
+                    endLine = in[j++];
+                    inLen--;
+                }
+            }
+            if (endLine != '\n') {
+                WOLFSSL_MSG("Bad end of line in Base64 Decode");
+                return ASN_INPUT_E;
+            }
+        }
+    }
+    *outLen = i;
+
+    return 0;
+}
+
+
+#if defined(WOLFSSL_BASE64_ENCODE)
+
+static
+const byte base64Encode[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J',
+                              'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T',
+                              'U', 'V', 'W', 'X', 'Y', 'Z',
+                              'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j',
+                              'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't',
+                              'u', 'v', 'w', 'x', 'y', 'z',
+                              '0', '1', '2', '3', '4', '5', '6', '7', '8', '9',
+                              '+', '/'
+                            };
+
+
+/* make sure *i (idx) won't exceed max, store and possibly escape to out,
+ * raw means use e w/o decode,  0 on success */
+static int CEscape(int escaped, byte e, byte* out, word32* i, word32 max,
+                  int raw)
+{
+    int    doEscape = 0;
+    word32 needed = 1;
+    word32 idx = *i;
+
+    byte basic;
+    byte plus    = 0;
+    byte equals  = 0;
+    byte newline = 0;
+
+    if (raw)
+        basic = e;
+    else
+        basic = base64Encode[e];
+
+    /* check whether to escape */
+    if (escaped) {
+        switch ((char)basic) {
+            case '+' :
+                plus     = 1;
+                doEscape = 1;
+                needed  += 2;
+                break;
+            case '=' :
+                equals   = 1;
+                doEscape = 1;
+                needed  += 2;
+                break;
+            case '\n' :
+                newline  = 1;
+                doEscape = 1;
+                needed  += 2;
+                break;
+            default:
+                /* do nothing */
+                break;
+        }
+    }
+
+    /* check size */
+    if ( (idx+needed) > max) {
+        WOLFSSL_MSG("Escape buffer max too small");
+        return BUFFER_E;
+    }
+
+    /* store it */
+    if (doEscape == 0) {
+        out[idx++] = basic;
+    }
+    else {
+        out[idx++] = '%';  /* start escape */
+
+        if (plus) {
+            out[idx++] = '2';
+            out[idx++] = 'B';
+        }
+        else if (equals) {
+            out[idx++] = '3';
+            out[idx++] = 'D';
+        }
+        else if (newline) {
+            out[idx++] = '0';
+            out[idx++] = 'A';
+        }
+
+    }
+    *i = idx;
+
+    return 0;
+}
+
+
+/* internal worker, handles both escaped and normal line endings */
+static int DoBase64_Encode(const byte* in, word32 inLen, byte* out,
+                           word32* outLen, int escaped)
+{
+    int    ret = 0;
+    word32 i = 0,
+           j = 0,
+           n = 0;   /* new line counter */
+
+    word32 outSz = (inLen + 3 - 1) / 3 * 4;
+    word32 addSz = (outSz + PEM_LINE_SZ - 1) / PEM_LINE_SZ;  /* new lines */
+
+    if (escaped)
+        addSz *= 3;   /* instead of just \n, we're doing %0A triplet */
+
+    outSz += addSz;
+
+    /* if escaped we can't predetermine size for one pass encoding, but
+     * make sure we have enough if no escapes are in input */
+    if (outSz > *outLen) return BAD_FUNC_ARG;
+    
+    while (inLen > 2) {
+        byte b1 = in[j++];
+        byte b2 = in[j++];
+        byte b3 = in[j++];
+
+        /* encoded idx */
+        byte e1 = b1 >> 2;
+        byte e2 = (byte)(((b1 & 0x3) << 4) | (b2 >> 4));
+        byte e3 = (byte)(((b2 & 0xF) << 2) | (b3 >> 6));
+        byte e4 = b3 & 0x3F;
+
+        /* store */
+        ret = CEscape(escaped, e1, out, &i, *outLen, 0);
+        if (ret != 0) break;
+        ret = CEscape(escaped, e2, out, &i, *outLen, 0);
+        if (ret != 0) break;
+        ret = CEscape(escaped, e3, out, &i, *outLen, 0);
+        if (ret != 0) break;
+        ret = CEscape(escaped, e4, out, &i, *outLen, 0);
+        if (ret != 0) break;
+
+        inLen -= 3;
+
+        if ((++n % (PEM_LINE_SZ / 4)) == 0 && inLen) {
+            ret = CEscape(escaped, '\n', out, &i, *outLen, 1);
+            if (ret != 0) break;
+        }
+    }
+
+    /* last integral */
+    if (inLen && ret == 0) {
+        int twoBytes = (inLen == 2);
+
+        byte b1 = in[j++];
+        byte b2 = (twoBytes) ? in[j++] : 0;
+
+        byte e1 = b1 >> 2;
+        byte e2 = (byte)(((b1 & 0x3) << 4) | (b2 >> 4));
+        byte e3 = (byte)((b2 & 0xF) << 2);
+
+        ret = CEscape(escaped, e1, out, &i, *outLen, 0);
+        if (ret == 0) 
+            ret = CEscape(escaped, e2, out, &i, *outLen, 0);
+        if (ret == 0) {
+            /* third */
+            if (twoBytes)
+                ret = CEscape(escaped, e3, out, &i, *outLen, 0);
+            else 
+                ret = CEscape(escaped, '=', out, &i, *outLen, 1);
+        }
+        /* fourth always pad */
+        if (ret == 0)
+            ret = CEscape(escaped, '=', out, &i, *outLen, 1);
+    } 
+
+    if (ret == 0) 
+        ret = CEscape(escaped, '\n', out, &i, *outLen, 1);
+
+    if (i != outSz && escaped == 0 && ret == 0)
+        return ASN_INPUT_E; 
+
+    *outLen = i;
+    return ret; 
+}
+
+
+/* Base64 Encode, PEM style, with \n line endings */
+int Base64_Encode(const byte* in, word32 inLen, byte* out, word32* outLen)
+{
+    return DoBase64_Encode(in, inLen, out, outLen, 0);
+}
+
+
+/* Base64 Encode, with %0A esacped line endings instead of \n */
+int Base64_EncodeEsc(const byte* in, word32 inLen, byte* out, word32* outLen)
+{
+    return DoBase64_Encode(in, inLen, out, outLen, 1);
+}
+
+
+#endif  /* defined(WOLFSSL_BASE64_ENCODE) */
+
+
+#if defined(OPENSSL_EXTRA) || defined(HAVE_WEBSERVER) || defined(HAVE_FIPS)
+
+static
+const byte hexDecode[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
+                           BAD, BAD, BAD, BAD, BAD, BAD, BAD,
+                           10, 11, 12, 13, 14, 15,  /* upper case A-F */
+                           BAD, BAD, BAD, BAD, BAD, BAD, BAD, BAD,
+                           BAD, BAD, BAD, BAD, BAD, BAD, BAD, BAD,
+                           BAD, BAD, BAD, BAD, BAD, BAD, BAD, BAD,
+                           BAD, BAD,  /* G - ` */
+                           10, 11, 12, 13, 14, 15   /* lower case a-f */
+                         };  /* A starts at 0x41 not 0x3A */
+
+int Base16_Decode(const byte* in, word32 inLen, byte* out, word32* outLen)
+{
+    word32 inIdx  = 0;
+    word32 outIdx = 0;
+
+    if (inLen == 1 && *outLen && in) {
+        byte b = in[inIdx++] - 0x30;  /* 0 starts at 0x30 */
+
+        /* sanity check */
+        if (b >=  sizeof(hexDecode)/sizeof(hexDecode[0]))
+            return ASN_INPUT_E;
+
+        b  = hexDecode[b];
+
+        if (b == BAD)
+            return ASN_INPUT_E;
+        
+        out[outIdx++] = b;
+
+        *outLen = outIdx;
+        return 0;
+    }
+
+    if (inLen % 2)
+        return BAD_FUNC_ARG;
+
+    if (*outLen < (inLen / 2))
+        return BAD_FUNC_ARG;
+
+    while (inLen) {
+        byte b  = in[inIdx++] - 0x30;  /* 0 starts at 0x30 */
+        byte b2 = in[inIdx++] - 0x30;
+
+        /* sanity checks */
+        if (b >=  sizeof(hexDecode)/sizeof(hexDecode[0]))
+            return ASN_INPUT_E;
+        if (b2 >= sizeof(hexDecode)/sizeof(hexDecode[0]))
+            return ASN_INPUT_E;
+
+        b  = hexDecode[b];
+        b2 = hexDecode[b2];
+
+        if (b == BAD || b2 == BAD)
+            return ASN_INPUT_E;
+        
+        out[outIdx++] = (byte)((b << 4) | b2);
+        inLen -= 2;
+    }
+
+    *outLen = outIdx;
+    return 0;
+}
+
+
+#endif /* (OPENSSL_EXTRA) || (HAVE_WEBSERVER) || (HAVE_FIPS) */
+
+#endif /* NO_CODING */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/compress.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/compress.c
new file mode 100644
index 0000000..a01c071
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/compress.c
@@ -0,0 +1,169 @@
+/* compress.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ wc_*
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifdef HAVE_LIBZ
+
+
+#include 
+#include 
+#include 
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+#include 
+
+
+/* alloc user allocs to work with zlib */
+static void* myAlloc(void* opaque, unsigned int item, unsigned int size)
+{
+    (void)opaque;
+    return XMALLOC(item * size, opaque, DYNAMIC_TYPE_LIBZ);
+}
+
+
+static void myFree(void* opaque, void* memory)
+{
+    (void)opaque;
+    XFREE(memory, opaque, DYNAMIC_TYPE_LIBZ);
+}
+
+
+#ifdef HAVE_MCAPI
+    #define DEFLATE_DEFAULT_WINDOWBITS  11
+    #define DEFLATE_DEFAULT_MEMLEVEL     1
+#else
+    #define DEFLATE_DEFAULT_WINDOWBITS 15
+    #define DEFLATE_DEFAULT_MEMLEVEL    8
+#endif
+
+
+int wc_Compress(byte* out, word32 outSz, const byte* in, word32 inSz, word32 flags)
+/*
+ * out - pointer to destination buffer
+ * outSz - size of destination buffer
+ * in - pointer to source buffer to compress
+ * inSz - size of source to compress
+ * flags - flags to control how compress operates 
+ *
+ * return:
+ *    negative - error code
+ *    positive - bytes stored in out buffer
+ * 
+ * Note, the output buffer still needs to be larger than the input buffer.
+ * The right chunk of data won't compress at all, and the lookup table will
+ * add to the size of the output. The libz code says the compressed
+ * buffer should be srcSz + 0.1% + 12.
+ */
+{
+    z_stream stream;
+    int result = 0;
+
+    stream.next_in = (Bytef*)in;
+    stream.avail_in = (uInt)inSz;
+#ifdef MAXSEG_64K
+    /* Check for source > 64K on 16-bit machine: */
+    if ((uLong)stream.avail_in != inSz) return COMPRESS_INIT_E;
+#endif
+    stream.next_out = out;
+    stream.avail_out = (uInt)outSz;
+    if ((uLong)stream.avail_out != outSz) return COMPRESS_INIT_E;
+
+    stream.zalloc = (alloc_func)myAlloc;
+    stream.zfree = (free_func)myFree;
+    stream.opaque = (voidpf)0;
+
+    if (deflateInit2(&stream, Z_DEFAULT_COMPRESSION, Z_DEFLATED,
+                     DEFLATE_DEFAULT_WINDOWBITS, DEFLATE_DEFAULT_MEMLEVEL,
+                     flags ? Z_FIXED : Z_DEFAULT_STRATEGY) != Z_OK)
+        return COMPRESS_INIT_E;
+
+    if (deflate(&stream, Z_FINISH) != Z_STREAM_END) {
+        deflateEnd(&stream);
+        return COMPRESS_E;
+    }
+
+    result = (int)stream.total_out;
+
+    if (deflateEnd(&stream) != Z_OK)
+        result = COMPRESS_E;
+
+    return result;
+}
+
+
+int wc_DeCompress(byte* out, word32 outSz, const byte* in, word32 inSz)
+/*
+ * out - pointer to destination buffer
+ * outSz - size of destination buffer
+ * in - pointer to source buffer to compress
+ * inSz - size of source to compress
+ * flags - flags to control how compress operates 
+ *
+ * return:
+ *    negative - error code
+ *    positive - bytes stored in out buffer
+ */ 
+{
+    z_stream stream;
+    int result = 0;
+
+    stream.next_in = (Bytef*)in;
+    stream.avail_in = (uInt)inSz;
+    /* Check for source > 64K on 16-bit machine: */
+    if ((uLong)stream.avail_in != inSz) return DECOMPRESS_INIT_E;
+
+    stream.next_out = out;
+    stream.avail_out = (uInt)outSz;
+    if ((uLong)stream.avail_out != outSz) return DECOMPRESS_INIT_E;
+
+    stream.zalloc = (alloc_func)myAlloc;
+    stream.zfree = (free_func)myFree;
+    stream.opaque = (voidpf)0;
+
+    if (inflateInit2(&stream, DEFLATE_DEFAULT_WINDOWBITS) != Z_OK)
+        return DECOMPRESS_INIT_E;
+
+    if (inflate(&stream, Z_FINISH) != Z_STREAM_END) {
+        inflateEnd(&stream);
+        return DECOMPRESS_E;
+    }
+    
+    result = (int)stream.total_out;
+
+    if (inflateEnd(&stream) != Z_OK)
+        result = DECOMPRESS_E;
+
+    return result;
+}
+
+
+#endif /* HAVE_LIBZ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/curve25519.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/curve25519.c
new file mode 100644
index 0000000..b745a04
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/curve25519.c
@@ -0,0 +1,260 @@
+/* curve25519.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+ /* Based On Daniel J Bernstein's curve25519 Public Domain ref10 work. */
+
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifdef HAVE_CURVE25519
+
+#include 
+#include 
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+const curve25519_set_type curve25519_sets[] = {
+{
+        32,
+        "CURVE25519",
+}
+};
+
+
+
+int wc_curve25519_make_key(RNG* rng, int keysize, curve25519_key* key)
+{
+  unsigned char basepoint[CURVE25519_KEYSIZE] = {9};
+  unsigned char n[CURVE25519_KEYSIZE];
+  unsigned char p[CURVE25519_KEYSIZE];
+  int  i;
+  int  ret;
+
+  if (key == NULL || rng == NULL)
+      return ECC_BAD_ARG_E;
+
+  /* currently only a key size of 32 bytes is used */
+  if (keysize != CURVE25519_KEYSIZE)
+      return ECC_BAD_ARG_E;
+
+  /* get random number from RNG */
+  ret = wc_RNG_GenerateBlock(rng, n, keysize);
+  if (ret != 0)
+      return ret;
+
+  for (i = 0; i < keysize; ++i) key->k.point[i] = n[i];
+  key->k.point[ 0] &= 248;
+  key->k.point[31] &= 127;
+  key->k.point[31] |= 64;
+
+  /* compute public key */
+  ret = curve25519(p, key->k.point, basepoint);
+
+  /* store keys in big endian format */
+  for (i = 0; i < keysize; ++i) n[i] = key->k.point[i];
+  for (i = 0; i < keysize; ++i) {
+      key->p.point[keysize - i - 1] = p[i];
+      key->k.point[keysize - i - 1] = n[i];
+  }
+
+  ForceZero(n, keysize);
+  ForceZero(p, keysize);
+
+  return ret;
+}
+
+
+int wc_curve25519_shared_secret(curve25519_key* private_key,
+                                curve25519_key* public_key,
+                                byte* out, word32* outlen)
+{
+    unsigned char k[CURVE25519_KEYSIZE];
+    unsigned char p[CURVE25519_KEYSIZE];
+    unsigned char o[CURVE25519_KEYSIZE];
+    int ret = 0;
+    int i;
+
+    /* sanity check */
+    if (private_key == NULL || public_key == NULL || out == NULL ||
+            outlen == NULL)
+        return BAD_FUNC_ARG;
+
+    /* avoid implementation fingerprinting */
+    if (public_key->p.point[0] > 0x7F)
+        return ECC_BAD_ARG_E;
+
+    XMEMSET(p,   0, sizeof(p));
+    XMEMSET(k,   0, sizeof(k));
+    XMEMSET(out, 0, CURVE25519_KEYSIZE);
+
+    for (i = 0; i < CURVE25519_KEYSIZE; ++i) {
+        p[i] = public_key->p.point [CURVE25519_KEYSIZE - i - 1];
+        k[i] = private_key->k.point[CURVE25519_KEYSIZE - i - 1];
+    }
+
+    ret     = curve25519(o , k, p);
+    *outlen = CURVE25519_KEYSIZE;
+
+    for (i = 0; i < CURVE25519_KEYSIZE; ++i) {
+        out[i] = o[CURVE25519_KEYSIZE - i -1];
+    }
+
+    ForceZero(p, sizeof(p));
+    ForceZero(k, sizeof(k));
+    ForceZero(o, sizeof(o));
+
+    return ret;
+}
+
+
+/* curve25519 uses a serialized string for key representation */
+int wc_curve25519_export_public(curve25519_key* key, byte* out, word32* outLen)
+{
+    word32 keySz;
+
+    if (key == NULL || out == NULL || outLen == NULL)
+        return BAD_FUNC_ARG;
+
+    /* check size of outgoing key */
+    keySz  = wc_curve25519_size(key);
+
+    /* copy in public key */
+    XMEMCPY(out, key->p.point, keySz);
+    *outLen = keySz;
+
+    return 0;
+}
+
+/* import curve25519 public key
+   return 0 on success */
+int wc_curve25519_import_public(const byte* in, word32 inLen,
+                                curve25519_key* key)
+{
+    word32 keySz;
+
+    /* sanity check */
+    if (key == NULL || in == NULL)
+        return ECC_BAD_ARG_E;
+
+    /* check size of incoming keys */
+    keySz = wc_curve25519_size(key);
+    if (inLen != keySz)
+       return ECC_BAD_ARG_E;
+
+    XMEMCPY(key->p.point, in, inLen);
+
+    key->dp = &curve25519_sets[0];
+
+    return 0;
+}
+
+
+/* export curve25519 private key only raw, outLen is in/out size
+   return 0 on success */
+int wc_curve25519_export_private_raw(curve25519_key* key, byte* out,
+                                     word32* outLen)
+{
+    word32 keySz;
+
+    /* sanity check */
+    if (key == NULL || out == NULL || outLen == NULL)
+        return ECC_BAD_ARG_E;
+
+    keySz = wc_curve25519_size(key);
+    *outLen = keySz;
+    XMEMSET(out, 0, keySz);
+    XMEMCPY(out, key->k.point, keySz);
+
+    return 0;
+}
+
+
+/* curve25519 private key import.
+   Public key to match private key needs to be imported too */
+int wc_curve25519_import_private_raw(const byte* priv, word32 privSz,
+                             const byte* pub, word32 pubSz, curve25519_key* key)
+{
+    int ret = 0;
+    word32 keySz;
+
+    /* sanity check */
+    if (key == NULL || priv == NULL || pub == NULL)
+        return ECC_BAD_ARG_E;
+
+    /* check size of incoming keys */
+    keySz = wc_curve25519_size(key);
+    if (privSz != keySz || pubSz != keySz)
+       return ECC_BAD_ARG_E;
+
+    XMEMCPY(key->k.point, priv, privSz);
+    XMEMCPY(key->p.point, pub, pubSz);
+
+    return ret;
+}
+
+
+int wc_curve25519_init(curve25519_key* key)
+{
+    word32 keySz;
+
+    if (key == NULL)
+       return ECC_BAD_ARG_E;
+
+    /* currently the format for curve25519 */
+    key->dp = &curve25519_sets[0];
+    keySz   = key->dp->size;
+
+    XMEMSET(key->k.point, 0, keySz);
+    XMEMSET(key->p.point, 0, keySz);
+
+    return 0;
+}
+
+
+/* Clean the memory of a key */
+void wc_curve25519_free(curve25519_key* key)
+{
+   if (key == NULL)
+       return;
+
+   key->dp = NULL;
+   ForceZero(key->p.point, sizeof(key->p.point));
+   ForceZero(key->k.point, sizeof(key->k.point));
+}
+
+
+/* get key size */
+int wc_curve25519_size(curve25519_key* key)
+{
+    if (key == NULL) return 0;
+
+    return key->dp->size;
+}
+
+#endif /*HAVE_CURVE25519*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/des3.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/des3.c
new file mode 100644
index 0000000..f886ecd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/des3.c
@@ -0,0 +1,1678 @@
+/* des3.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifndef NO_DES3
+
+#include 
+
+#ifdef HAVE_FIPS
+#ifdef HAVE_CAVIUM
+    static int wc_Des3_CaviumSetKey(Des3* des3, const byte* key, const byte* iv);
+    static int wc_Des3_CaviumCbcEncrypt(Des3* des3, byte* out, const byte* in,
+                                      word32 length);
+    static int wc_Des3_CaviumCbcDecrypt(Des3* des3, byte* out, const byte* in,
+                                      word32 length);
+#endif
+
+int wc_Des_SetKey(Des* des, const byte* key, const byte* iv, int dir)
+{
+    return Des_SetKey(des, key, iv, dir);
+}
+
+
+int wc_Des3_SetKey(Des3* des, const byte* key, const byte* iv, int dir)
+{
+    return Des3_SetKey_fips(des, key, iv, dir);
+}
+
+
+int wc_Des_CbcEncrypt(Des* des, byte* out, const byte* in, word32 sz)
+{
+    return Des_CbcEncrypt(des, out, in, sz);
+}
+
+
+int wc_Des_CbcDecrypt(Des* des, byte* out, const byte* in, word32 sz)
+{
+    return Des_CbcDecrypt(des, out, in, sz);
+}
+
+
+int wc_Des3_CbcEncrypt(Des3* des, byte* out, const byte* in, word32 sz)
+{
+    return Des3_CbcEncrypt_fips(des, out, in, sz);
+}
+
+
+int wc_Des3_CbcDecrypt(Des3* des, byte* out, const byte* in, word32 sz)
+{
+    return Des3_CbcDecrypt_fips(des, out, in, sz);
+}
+
+
+#ifdef WOLFSSL_DES_ECB
+
+/* One block, compatibility only */
+int wc_Des_EcbEncrypt(Des* des, byte* out, const byte* in, word32 sz)
+{
+    return Des_EcbEncrypt(des, out, in, sz);
+}
+
+#endif /* WOLFSSL_DES_ECB */
+
+
+void wc_Des_SetIV(Des* des, const byte* iv)
+{
+    Des_SetIV(des, iv);
+}
+
+
+int wc_Des_CbcDecryptWithKey(byte* out, const byte* in, word32 sz,
+                                                const byte* key, const byte* iv)
+{
+    return Des_CbcDecryptWithKey(out, in, sz, key, iv);
+}
+
+
+int wc_Des3_SetIV(Des3* des, const byte* iv)
+{
+    return Des3_SetIV_fips(des, iv);
+}
+
+
+int wc_Des3_CbcDecryptWithKey(byte* out, const byte* in, word32 sz,
+                                                const byte* key, const byte* iv)
+{
+    return Des3_CbcDecryptWithKey(out, in, sz, key, iv);
+}
+
+
+#ifdef HAVE_CAVIUM
+
+/* Initiliaze Des3 for use with Nitrox device */
+int wc_Des3_InitCavium(Des3* des3, int devId)
+{
+    return Des3_InitCavium(des3, devId);
+}
+
+
+/* Free Des3 from use with Nitrox device */
+void wc_Des3_FreeCavium(Des3* des3)
+{
+    Des3_FreeCavium(des3);
+}
+
+
+#endif /* HAVE_CAVIUM */
+#else /* build without fips */
+
+#if defined(WOLFSSL_TI_CRYPT)
+    #include 
+#else
+
+#include 
+#include 
+
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+
+#ifdef HAVE_CAVIUM
+    static int wc_Des3_CaviumSetKey(Des3* des3, const byte* key, const byte* iv);
+    static int wc_Des3_CaviumCbcEncrypt(Des3* des3, byte* out, const byte* in,
+                                      word32 length);
+    static int wc_Des3_CaviumCbcDecrypt(Des3* des3, byte* out, const byte* in,
+                                      word32 length);
+#endif
+
+
+
+
+#ifdef STM32F2_CRYPTO
+    /*
+     * STM32F2 hardware DES/3DES support through the STM32F2 standard
+     * peripheral library. Documentation located in STM32F2xx Standard
+     * Peripheral Library document (See note in README).
+     */
+    #include "stm32f2xx.h"
+		#include "stm32f2xx_cryp.h"
+
+    int wc_Des_SetKey(Des* des, const byte* key, const byte* iv, int dir)
+    {
+        word32 *dkey = des->key;
+
+        XMEMCPY(dkey, key, 8);
+        ByteReverseWords(dkey, dkey, 8);
+
+        wc_Des_SetIV(des, iv);
+
+        return 0;
+    }
+
+    int wc_Des3_SetKey(Des3* des, const byte* key, const byte* iv, int dir)
+    {
+        word32 *dkey1 = des->key[0];
+        word32 *dkey2 = des->key[1];
+        word32 *dkey3 = des->key[2];
+
+        XMEMCPY(dkey1, key, 8);         /* set key 1 */
+        XMEMCPY(dkey2, key + 8, 8);     /* set key 2 */
+        XMEMCPY(dkey3, key + 16, 8);    /* set key 3 */
+
+        ByteReverseWords(dkey1, dkey1, 8);
+        ByteReverseWords(dkey2, dkey2, 8);
+        ByteReverseWords(dkey3, dkey3, 8);
+
+        return wc_Des3_SetIV(des, iv);
+    }
+
+    void DesCrypt(Des* des, byte* out, const byte* in, word32 sz,
+                  int dir, int mode)
+    {
+        word32 *dkey, *iv;
+        CRYP_InitTypeDef DES_CRYP_InitStructure;
+        CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure;
+        CRYP_IVInitTypeDef DES_CRYP_IVInitStructure;
+
+        dkey = des->key;
+        iv = des->reg;
+
+        /* crypto structure initialization */
+        CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure);
+        CRYP_StructInit(&DES_CRYP_InitStructure);
+        CRYP_IVStructInit(&DES_CRYP_IVInitStructure);
+
+        /* reset registers to their default values */
+        CRYP_DeInit();
+
+        /* set direction, mode, and datatype */
+        if (dir == DES_ENCRYPTION) {
+            DES_CRYP_InitStructure.CRYP_AlgoDir  = CRYP_AlgoDir_Encrypt;
+        } else { /* DES_DECRYPTION */
+            DES_CRYP_InitStructure.CRYP_AlgoDir  = CRYP_AlgoDir_Decrypt;
+        }
+
+        if (mode == DES_CBC) {
+            DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_CBC;
+        } else { /* DES_ECB */
+            DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_ECB;
+        }
+
+        DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
+        CRYP_Init(&DES_CRYP_InitStructure);
+
+        /* load key into correct registers */
+        DES_CRYP_KeyInitStructure.CRYP_Key1Left  = dkey[0];
+        DES_CRYP_KeyInitStructure.CRYP_Key1Right = dkey[1];
+        CRYP_KeyInit(&DES_CRYP_KeyInitStructure);
+
+        /* set iv */
+        ByteReverseWords(iv, iv, DES_BLOCK_SIZE);
+        DES_CRYP_IVInitStructure.CRYP_IV0Left  = iv[0];
+        DES_CRYP_IVInitStructure.CRYP_IV0Right = iv[1];
+        CRYP_IVInit(&DES_CRYP_IVInitStructure);
+
+        /* enable crypto processor */
+        CRYP_Cmd(ENABLE);
+
+        while (sz > 0)
+        {
+            /* flush IN/OUT FIFOs */
+            CRYP_FIFOFlush();
+
+            /* if input and output same will overwrite input iv */
+            XMEMCPY(des->tmp, in + sz - DES_BLOCK_SIZE, DES_BLOCK_SIZE);
+
+            CRYP_DataIn(*(uint32_t*)&in[0]);
+            CRYP_DataIn(*(uint32_t*)&in[4]);
+
+            /* wait until the complete message has been processed */
+            while(CRYP_GetFlagStatus(CRYP_FLAG_BUSY) != RESET) {}
+
+            *(uint32_t*)&out[0]  = CRYP_DataOut();
+            *(uint32_t*)&out[4]  = CRYP_DataOut();
+
+            /* store iv for next call */
+            XMEMCPY(des->reg, des->tmp, DES_BLOCK_SIZE);
+
+            sz  -= DES_BLOCK_SIZE;
+            in  += DES_BLOCK_SIZE;
+            out += DES_BLOCK_SIZE;
+        }
+
+        /* disable crypto processor */
+        CRYP_Cmd(DISABLE);
+    }
+
+    int wc_Des_CbcEncrypt(Des* des, byte* out, const byte* in, word32 sz)
+    {
+        DesCrypt(des, out, in, sz, DES_ENCRYPTION, DES_CBC);
+        return 0;
+    }
+
+    int wc_Des_CbcDecrypt(Des* des, byte* out, const byte* in, word32 sz)
+    {
+        DesCrypt(des, out, in, sz, DES_DECRYPTION, DES_CBC);
+        return 0;
+    }
+
+    int wc_Des_EcbEncrypt(Des* des, byte* out, const byte* in, word32 sz)
+    {
+        DesCrypt(des, out, in, sz, DES_ENCRYPTION, DES_ECB);
+        return 0;
+    }
+
+    void Des3Crypt(Des3* des, byte* out, const byte* in, word32 sz,
+                   int dir)
+    {
+        word32 *dkey1, *dkey2, *dkey3, *iv;
+        CRYP_InitTypeDef DES3_CRYP_InitStructure;
+        CRYP_KeyInitTypeDef DES3_CRYP_KeyInitStructure;
+        CRYP_IVInitTypeDef DES3_CRYP_IVInitStructure;
+
+        dkey1 = des->key[0];
+        dkey2 = des->key[1];
+        dkey3 = des->key[2];
+        iv = des->reg;
+
+        /* crypto structure initialization */
+        CRYP_KeyStructInit(&DES3_CRYP_KeyInitStructure);
+        CRYP_StructInit(&DES3_CRYP_InitStructure);
+        CRYP_IVStructInit(&DES3_CRYP_IVInitStructure);
+
+        /* reset registers to their default values */
+        CRYP_DeInit();
+
+        /* set direction, mode, and datatype */
+        if (dir == DES_ENCRYPTION) {
+            DES3_CRYP_InitStructure.CRYP_AlgoDir  = CRYP_AlgoDir_Encrypt;
+        } else {
+            DES3_CRYP_InitStructure.CRYP_AlgoDir  = CRYP_AlgoDir_Decrypt;
+        }
+
+        DES3_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_CBC;
+        DES3_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
+        CRYP_Init(&DES3_CRYP_InitStructure);
+
+        /* load key into correct registers */
+        DES3_CRYP_KeyInitStructure.CRYP_Key1Left  = dkey1[0];
+        DES3_CRYP_KeyInitStructure.CRYP_Key1Right = dkey1[1];
+        DES3_CRYP_KeyInitStructure.CRYP_Key2Left  = dkey2[0];
+        DES3_CRYP_KeyInitStructure.CRYP_Key2Right = dkey2[1];
+        DES3_CRYP_KeyInitStructure.CRYP_Key3Left  = dkey3[0];
+        DES3_CRYP_KeyInitStructure.CRYP_Key3Right = dkey3[1];
+        CRYP_KeyInit(&DES3_CRYP_KeyInitStructure);
+
+        /* set iv */
+        ByteReverseWords(iv, iv, DES_BLOCK_SIZE);
+        DES3_CRYP_IVInitStructure.CRYP_IV0Left  = iv[0];
+        DES3_CRYP_IVInitStructure.CRYP_IV0Right = iv[1];
+        CRYP_IVInit(&DES3_CRYP_IVInitStructure);
+
+        /* enable crypto processor */
+        CRYP_Cmd(ENABLE);
+
+        while (sz > 0)
+        {
+            /* flush IN/OUT FIFOs */
+            CRYP_FIFOFlush();
+
+            CRYP_DataIn(*(uint32_t*)&in[0]);
+            CRYP_DataIn(*(uint32_t*)&in[4]);
+
+            /* wait until the complete message has been processed */
+            while(CRYP_GetFlagStatus(CRYP_FLAG_BUSY) != RESET) {}
+
+            *(uint32_t*)&out[0]  = CRYP_DataOut();
+            *(uint32_t*)&out[4]  = CRYP_DataOut();
+
+            /* store iv for next call */
+            XMEMCPY(des->reg, out + sz - DES_BLOCK_SIZE, DES_BLOCK_SIZE);
+
+            sz  -= DES_BLOCK_SIZE;
+            in  += DES_BLOCK_SIZE;
+            out += DES_BLOCK_SIZE;
+        }
+
+        /* disable crypto processor */
+        CRYP_Cmd(DISABLE);
+
+    }
+
+    int wc_Des3_CbcEncrypt(Des3* des, byte* out, const byte* in, word32 sz)
+    {
+        Des3Crypt(des, out, in, sz, DES_ENCRYPTION);
+        return 0;
+    }
+
+    int wc_Des3_CbcDecrypt(Des3* des, byte* out, const byte* in, word32 sz)
+    {
+        Des3Crypt(des, out, in, sz, DES_DECRYPTION);
+        return 0;
+    }
+
+#elif defined(HAVE_COLDFIRE_SEC)
+
+#include 
+
+#include "sec.h"
+#include "mcf5475_sec.h"
+#include "mcf5475_siu.h"
+
+#if defined (HAVE_THREADX)
+#include "memory_pools.h"
+extern TX_BYTE_POOL mp_ncached;  /* Non Cached memory pool */
+#endif
+
+#define DES_BUFFER_SIZE (DES_BLOCK_SIZE * 64)
+static unsigned char *desBuffIn = NULL ;
+static unsigned char *desBuffOut = NULL ;
+static byte *secIV ; 
+static byte *secKey ; 
+static volatile SECdescriptorType *secDesc ;
+
+static wolfSSL_Mutex Mutex_DesSEC ;
+
+#define SEC_DESC_DES_CBC_ENCRYPT  0x20500010
+#define SEC_DESC_DES_CBC_DECRYPT  0x20400010
+#define SEC_DESC_DES3_CBC_ENCRYPT 0x20700010
+#define SEC_DESC_DES3_CBC_DECRYPT 0x20600010
+
+#define DES_IVLEN 8
+#define DES_KEYLEN 8
+#define DES3_IVLEN 8
+#define DES3_KEYLEN 24
+
+extern volatile unsigned char __MBAR[];
+
+static void wc_Des_Cbc(byte* out, const byte* in, word32 sz, 
+                    byte *key, byte *iv, word32 desc)
+{
+    #ifdef DEBUG_WOLFSSL
+    int ret ;  int stat1,stat2 ; 
+	  #endif
+    int size ;
+    volatile int v ;
+ 
+    LockMutex(&Mutex_DesSEC) ;
+    
+    secDesc->length1 = 0x0;
+    secDesc->pointer1 = NULL;
+    if((desc==SEC_DESC_DES_CBC_ENCRYPT)||(desc==SEC_DESC_DES_CBC_DECRYPT)){
+        secDesc->length2 = DES_IVLEN ;  
+        secDesc->length3 = DES_KEYLEN ;
+    } else {
+        secDesc->length2 = DES3_IVLEN ; 
+        secDesc->length3 = DES3_KEYLEN ;
+    }
+    secDesc->pointer2 = secIV ;
+    secDesc->pointer3 = secKey;
+    secDesc->pointer4 = desBuffIn ;
+    secDesc->pointer5 = desBuffOut ;
+    secDesc->length6 = 0; 
+    secDesc->pointer6 = NULL; 
+    secDesc->length7 = 0x0;
+    secDesc->pointer7 = NULL;
+    secDesc->nextDescriptorPtr = NULL ; 
+    
+    while(sz) {
+        XMEMCPY(secIV, iv, secDesc->length2) ;
+        if((sz%DES_BUFFER_SIZE) == sz) {
+            size = sz ;
+            sz = 0 ;
+        } else {
+            size = DES_BUFFER_SIZE ;
+            sz -= DES_BUFFER_SIZE ;
+        }
+        
+        XMEMCPY(desBuffIn, in, size) ;
+        XMEMCPY(secKey, key, secDesc->length3) ;
+        
+        secDesc->header = desc ;
+        secDesc->length4 = size;
+        secDesc->length5 = size;
+        /* Point SEC to the location of the descriptor */
+        MCF_SEC_FR0 = (uint32)secDesc;
+        /* Initialize SEC and wait for encryption to complete */
+        MCF_SEC_CCCR0 = 0x0000001a;
+        /* poll SISR to determine when channel is complete */
+        v=0 ;
+        while((secDesc->header>> 24) != 0xff) {
+            if(v++ > 1000)break ;
+        }
+				
+#ifdef DEBUG_WOLFSSL
+        ret = MCF_SEC_SISRH;
+        stat1 = MCF_SEC_DSR ; 
+        stat2 = MCF_SEC_DISR ; 
+        if(ret & 0xe0000000) {
+            /* db_printf("Des_Cbc(%x):ISRH=%08x, DSR=%08x, DISR=%08x\n", desc, ret, stat1, stat2) ; */
+        }
+#endif
+				
+        XMEMCPY(out, desBuffOut, size) ;
+
+        if((desc==SEC_DESC_DES3_CBC_ENCRYPT)||(desc==SEC_DESC_DES_CBC_ENCRYPT)) {
+            XMEMCPY((void*)iv, (void*)&(out[size-secDesc->length2]), secDesc->length2) ;
+        } else {
+            XMEMCPY((void*)iv, (void*)&(in[size-secDesc->length2]), secDesc->length2) ;
+        }
+        
+        in  += size ;   
+        out += size ;
+                
+    }
+    UnLockMutex(&Mutex_DesSEC) ;
+    
+}
+
+
+int wc_Des_CbcEncrypt(Des* des, byte* out, const byte* in, word32 sz)
+{
+    wc_Des_Cbc(out, in, sz,  (byte *)des->key,  (byte *)des->reg, SEC_DESC_DES_CBC_ENCRYPT) ;
+    return 0;
+}
+
+int wc_Des_CbcDecrypt(Des* des, byte* out, const byte* in, word32 sz)
+{
+    wc_Des_Cbc(out, in, sz,   (byte *)des->key,  (byte *)des->reg, SEC_DESC_DES_CBC_DECRYPT) ;
+    return 0;
+}
+
+int wc_Des3_CbcEncrypt(Des3* des3, byte* out, const byte* in, word32 sz)
+{
+    wc_Des_Cbc(out, in, sz,  (byte *)des3->key,  (byte *)des3->reg, SEC_DESC_DES3_CBC_ENCRYPT) ;
+	  return 0;
+}
+
+
+int wc_Des3_CbcDecrypt(Des3* des3, byte* out, const byte* in, word32 sz)
+{
+    wc_Des_Cbc(out, in, sz,   (byte *)des3->key,  (byte *)des3->reg, SEC_DESC_DES3_CBC_DECRYPT) ;
+	  return 0;
+}
+
+static void setParity(byte *buf, int len) 
+{
+    int i, j ;
+    byte v ;
+    int bits ;
+
+    for(i=0; i> 1 ;
+        buf[i] = v << 1 ;
+        bits = 0 ;
+        for(j=0; j<7; j++)
+        {
+            bits += (v&0x1) ;
+            v = v >> 1 ;
+        }
+        buf[i] |= (1 - (bits&0x1)) ;
+    }
+    
+}
+
+
+int wc_Des_SetKey(Des* des, const byte* key, const byte* iv, int dir)
+{
+    if(desBuffIn == NULL) {
+        #if defined (HAVE_THREADX)
+			  int s1, s2, s3, s4, s5 ;
+        s5 = tx_byte_allocate(&mp_ncached,(void *)&secDesc, 
+                                                     sizeof(SECdescriptorType), TX_NO_WAIT);
+        s1 = tx_byte_allocate(&mp_ncached,(void *)&desBuffIn,  DES_BUFFER_SIZE, TX_NO_WAIT);
+        s2 = tx_byte_allocate(&mp_ncached,(void *)&desBuffOut, DES_BUFFER_SIZE, TX_NO_WAIT);
+        /* Don't know des or des3 to be used. Allocate larger buffers */
+        s3 = tx_byte_allocate(&mp_ncached,(void *)&secKey,     DES3_KEYLEN,TX_NO_WAIT);
+        s4 = tx_byte_allocate(&mp_ncached,(void *)&secIV,      DES3_IVLEN,  TX_NO_WAIT);              
+        #else
+        #warning "Allocate non-Cache buffers"
+        #endif
+        
+        InitMutex(&Mutex_DesSEC) ;
+    }
+     
+    XMEMCPY(des->key, key, DES_KEYLEN);  
+    setParity((byte *)des->key, DES_KEYLEN) ;  
+		
+    if (iv) {
+        XMEMCPY(des->reg, iv, DES_IVLEN);
+    }   else {
+        XMEMSET(des->reg, 0x0, DES_IVLEN) ;
+    }
+		return 0;
+}
+
+int wc_Des3_SetKey(Des3* des3, const byte* key, const byte* iv, int dir)
+{
+    
+    if(desBuffIn == NULL) {
+        #if defined (HAVE_THREADX)
+			  int s1, s2, s3, s4, s5 ;
+        s5 = tx_byte_allocate(&mp_ncached,(void *)&secDesc, 
+                                                     sizeof(SECdescriptorType), TX_NO_WAIT);
+        s1 = tx_byte_allocate(&mp_ncached,(void *)&desBuffIn,  DES_BUFFER_SIZE, TX_NO_WAIT);
+        s2 = tx_byte_allocate(&mp_ncached,(void *)&desBuffOut, DES_BUFFER_SIZE, TX_NO_WAIT);
+        s3 = tx_byte_allocate(&mp_ncached,(void *)&secKey,     DES3_KEYLEN,TX_NO_WAIT);
+        s4 = tx_byte_allocate(&mp_ncached,(void *)&secIV,      DES3_IVLEN,  TX_NO_WAIT);              
+        #else
+        #warning "Allocate non-Cache buffers"
+        #endif
+        
+        InitMutex(&Mutex_DesSEC) ;
+    }
+    
+    XMEMCPY(des3->key[0], key, DES3_KEYLEN); 
+    setParity((byte *)des3->key[0], DES3_KEYLEN) ;  
+		
+    if (iv) {
+        XMEMCPY(des3->reg, iv, DES3_IVLEN);
+    }   else {
+        XMEMSET(des3->reg, 0x0, DES3_IVLEN) ;
+    }
+    return 0;
+
+}
+
+#elif defined FREESCALE_MMCAU
+    /*
+     * Freescale mmCAU hardware DES/3DES support through the CAU/mmCAU library.
+     * Documentation located in ColdFire/ColdFire+ CAU and Kinetis mmCAU
+     * Software Library User Guide (See note in README).
+     */
+    #include "cau_api.h"
+
+    const unsigned char parityLookup[128] =
+    {
+        1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,
+        0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,
+        0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,
+        1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0
+     };
+
+    int wc_Des_SetKey(Des* des, const byte* key, const byte* iv, int dir)
+    {
+        int i = 0;
+        byte* dkey = (byte*)des->key;
+
+        XMEMCPY(dkey, key, 8);
+
+        wc_Des_SetIV(des, iv);
+
+        /* fix key parity, if needed */
+        for (i = 0; i < 8; i++) {
+            dkey[i] = ((dkey[i] & 0xFE) | parityLookup[dkey[i] >> 1]);
+        }
+
+        return 0;
+    }
+
+    int wc_Des3_SetKey(Des3* des, const byte* key, const byte* iv, int dir)
+    {
+        int i = 0, ret = 0;
+        byte* dkey1 = (byte*)des->key[0];
+        byte* dkey2 = (byte*)des->key[1];
+        byte* dkey3 = (byte*)des->key[2];
+
+        XMEMCPY(dkey1, key, 8);         /* set key 1 */
+        XMEMCPY(dkey2, key + 8, 8);     /* set key 2 */
+        XMEMCPY(dkey3, key + 16, 8);    /* set key 3 */
+
+        ret = wc_Des3_SetIV(des, iv);
+        if (ret != 0)
+            return ret;
+
+        /* fix key parity if needed */
+        for (i = 0; i < 8; i++)
+           dkey1[i] = ((dkey1[i] & 0xFE) | parityLookup[dkey1[i] >> 1]);
+
+        for (i = 0; i < 8; i++)
+           dkey2[i] = ((dkey2[i] & 0xFE) | parityLookup[dkey2[i] >> 1]);
+
+        for (i = 0; i < 8; i++)
+           dkey3[i] = ((dkey3[i] & 0xFE) | parityLookup[dkey3[i] >> 1]);
+
+        return ret;
+    }
+
+    int wc_Des_CbcEncrypt(Des* des, byte* out, const byte* in, word32 sz)
+    {
+        int i;
+        int offset = 0;
+        int len = sz;
+        byte *iv;
+        byte temp_block[DES_BLOCK_SIZE];
+
+        iv = (byte*)des->reg;
+
+        if ((wolfssl_word)out % WOLFSSL_MMCAU_ALIGNMENT) {
+            WOLFSSL_MSG("Bad cau_des_encrypt alignment"); 
+            return BAD_ALIGN_E;
+        }
+
+        while (len > 0)
+        {
+            XMEMCPY(temp_block, in + offset, DES_BLOCK_SIZE);
+
+            /* XOR block with IV for CBC */
+            for (i = 0; i < DES_BLOCK_SIZE; i++)
+                temp_block[i] ^= iv[i];
+
+            cau_des_encrypt(temp_block, (byte*)des->key, out + offset);
+
+            len    -= DES_BLOCK_SIZE;
+            offset += DES_BLOCK_SIZE;
+
+            /* store IV for next block */
+            XMEMCPY(iv, out + offset - DES_BLOCK_SIZE, DES_BLOCK_SIZE);
+        }
+
+        return 0;
+    }
+
+    int wc_Des_CbcDecrypt(Des* des, byte* out, const byte* in, word32 sz)
+    {
+        int i;
+        int offset = 0;
+        int len = sz;
+        byte* iv;
+        byte temp_block[DES_BLOCK_SIZE];
+
+        iv = (byte*)des->reg;
+
+        if ((wolfssl_word)out % WOLFSSL_MMCAU_ALIGNMENT) {
+            WOLFSSL_MSG("Bad cau_des_decrypt alignment"); 
+            return BAD_ALIGN_E;
+        }
+
+        while (len > 0)
+        {
+            XMEMCPY(temp_block, in + offset, DES_BLOCK_SIZE);
+
+            cau_des_decrypt(in + offset, (byte*)des->key, out + offset);
+
+            /* XOR block with IV for CBC */
+            for (i = 0; i < DES_BLOCK_SIZE; i++)
+                (out + offset)[i] ^= iv[i];
+
+            /* store IV for next block */
+            XMEMCPY(iv, temp_block, DES_BLOCK_SIZE);
+
+            len     -= DES_BLOCK_SIZE;
+            offset += DES_BLOCK_SIZE;
+        }
+
+        return 0;
+    }
+
+    int wc_Des3_CbcEncrypt(Des3* des, byte* out, const byte* in, word32 sz)
+    {
+        int i;
+        int offset = 0;
+        int len = sz;
+
+        byte *iv;
+        byte temp_block[DES_BLOCK_SIZE];
+
+        iv = (byte*)des->reg;
+
+        if ((wolfssl_word)out % WOLFSSL_MMCAU_ALIGNMENT) {
+            WOLFSSL_MSG("Bad 3ede cau_des_encrypt alignment"); 
+            return BAD_ALIGN_E;
+        }
+
+        while (len > 0)
+        {
+            XMEMCPY(temp_block, in + offset, DES_BLOCK_SIZE);
+
+            /* XOR block with IV for CBC */
+            for (i = 0; i < DES_BLOCK_SIZE; i++)
+                temp_block[i] ^= iv[i];
+
+            cau_des_encrypt(temp_block  , (byte*)des->key[0], out + offset);
+            cau_des_decrypt(out + offset, (byte*)des->key[1], out + offset);
+            cau_des_encrypt(out + offset, (byte*)des->key[2], out + offset);
+
+            len    -= DES_BLOCK_SIZE;
+            offset += DES_BLOCK_SIZE;
+
+            /* store IV for next block */
+            XMEMCPY(iv, out + offset - DES_BLOCK_SIZE, DES_BLOCK_SIZE);
+        }
+
+        return 0;
+    }
+
+    int wc_Des3_CbcDecrypt(Des3* des, byte* out, const byte* in, word32 sz)
+    {
+        int i;
+        int offset = 0;
+        int len = sz;
+
+        byte* iv;
+        byte temp_block[DES_BLOCK_SIZE];
+
+        iv = (byte*)des->reg;
+
+        if ((wolfssl_word)out % WOLFSSL_MMCAU_ALIGNMENT) {
+            WOLFSSL_MSG("Bad 3ede cau_des_decrypt alignment"); 
+            return BAD_ALIGN_E;
+        }
+
+        while (len > 0)
+        {
+            XMEMCPY(temp_block, in + offset, DES_BLOCK_SIZE);
+
+            cau_des_decrypt(in + offset , (byte*)des->key[2], out + offset);
+            cau_des_encrypt(out + offset, (byte*)des->key[1], out + offset);
+            cau_des_decrypt(out + offset, (byte*)des->key[0], out + offset);
+
+            /* XOR block with IV for CBC */
+            for (i = 0; i < DES_BLOCK_SIZE; i++)
+                (out + offset)[i] ^= iv[i];
+
+            /* store IV for next block */
+            XMEMCPY(iv, temp_block, DES_BLOCK_SIZE);
+
+            len    -= DES_BLOCK_SIZE;
+            offset += DES_BLOCK_SIZE;
+        }
+
+        return 0;
+    }
+
+
+#elif defined(WOLFSSL_PIC32MZ_CRYPT)
+
+    #include "wolfssl/wolfcrypt/port/pic32/pic32mz-crypt.h"
+
+void wc_Des_SetIV(Des* des, const byte* iv);
+int  wc_Des3_SetIV(Des3* des, const byte* iv);
+
+    int wc_Des_SetKey(Des* des, const byte* key, const byte* iv, int dir)
+    {
+        word32 *dkey = des->key ;
+        word32 *dreg = des->reg ;
+
+        XMEMCPY((byte *)dkey, (byte *)key, 8);
+        ByteReverseWords(dkey, dkey, 8);
+        XMEMCPY((byte *)dreg, (byte *)iv, 8);
+        ByteReverseWords(dreg, dreg, 8);
+
+        return 0;
+    }
+
+    int wc_Des3_SetKey(Des3* des, const byte* key, const byte* iv, int dir)
+    {
+        word32 *dkey1 = des->key[0];
+        word32 *dreg = des->reg ;
+
+        XMEMCPY(dkey1, key, 24);
+        ByteReverseWords(dkey1, dkey1, 24);
+        XMEMCPY(dreg, iv, 8);
+        ByteReverseWords(dreg, dreg, 8) ;
+
+        return 0;
+    }
+
+    void DesCrypt(word32 *key, word32 *iv, byte* out, const byte* in, word32 sz,
+                  int dir, int algo, int cryptoalgo)
+    {
+        securityAssociation *sa_p ;
+        bufferDescriptor *bd_p ;
+        const byte *in_p, *in_l ;
+        byte *out_p, *out_l ;
+        volatile securityAssociation sa __attribute__((aligned (8)));
+        volatile bufferDescriptor bd __attribute__((aligned (8)));
+        volatile int k ;
+        
+        /* get uncached address */
+
+        in_l = in;
+        out_l = out ;
+        sa_p = KVA0_TO_KVA1(&sa) ; 
+        bd_p = KVA0_TO_KVA1(&bd) ;
+        in_p = KVA0_TO_KVA1(in_l) ;
+        out_p= KVA0_TO_KVA1(out_l);
+        
+        if(PIC32MZ_IF_RAM(in_p))
+            XMEMCPY((void *)in_p, (void *)in, sz);
+        XMEMSET((void *)out_p, 0, sz);
+
+        /* Set up the Security Association */
+        XMEMSET((byte *)KVA0_TO_KVA1(&sa), 0, sizeof(sa));
+        sa_p->SA_CTRL.ALGO = algo ; 
+        sa_p->SA_CTRL.LNC = 1;
+        sa_p->SA_CTRL.LOADIV = 1;
+        sa_p->SA_CTRL.FB = 1;
+        sa_p->SA_CTRL.ENCTYPE = dir ; /* Encryption/Decryption */
+        sa_p->SA_CTRL.CRYPTOALGO = cryptoalgo;
+        sa_p->SA_CTRL.KEYSIZE = 1 ; /* KEY is 192 bits */
+        XMEMCPY((byte *)KVA0_TO_KVA1(&sa.SA_ENCKEY[algo==PIC32_ALGO_TDES ? 2 : 6]),
+                (byte *)key, algo==PIC32_ALGO_TDES ? 24 : 8);
+        XMEMCPY((byte *)KVA0_TO_KVA1(&sa.SA_ENCIV[2]), (byte *)iv, 8);
+
+        XMEMSET((byte *)KVA0_TO_KVA1(&bd), 0, sizeof(bd));
+        /* Set up the Buffer Descriptor */
+        bd_p->BD_CTRL.BUFLEN = sz;
+        bd_p->BD_CTRL.LIFM = 1;
+        bd_p->BD_CTRL.SA_FETCH_EN = 1;
+        bd_p->BD_CTRL.LAST_BD = 1;
+        bd_p->BD_CTRL.DESC_EN = 1;
+    
+        bd_p->SA_ADDR = (unsigned int)KVA_TO_PA(&sa) ; /* (unsigned int)sa_p; */
+        bd_p->SRCADDR = (unsigned int)KVA_TO_PA(in) ; /* (unsigned int)in_p; */
+        bd_p->DSTADDR = (unsigned int)KVA_TO_PA(out); /* (unsigned int)out_p; */
+        bd_p->NXTPTR = (unsigned int)KVA_TO_PA(&bd);
+        bd_p->MSGLEN = sz ;
+        
+        /* Fire in the hole! */
+        CECON = 1 << 6;
+        while (CECON);
+        
+        /* Run the engine */
+        CEBDPADDR = (unsigned int)KVA_TO_PA(&bd) ; /* (unsigned int)bd_p ; */
+        CEINTEN = 0x07;
+        CECON = 0x27;
+
+        WAIT_ENGINE ;
+
+        if((cryptoalgo == PIC32_CRYPTOALGO_CBC) ||
+           (cryptoalgo == PIC32_CRYPTOALGO_TCBC)||
+           (cryptoalgo == PIC32_CRYPTOALGO_RCBC)) {
+            /* set iv for the next call */
+            if(dir == PIC32_ENCRYPTION) {
+	        XMEMCPY((void *)iv, (void*)&(out_p[sz-DES_IVLEN]), DES_IVLEN) ;
+	        } else {
+                ByteReverseWords((word32*)iv, (word32 *)&(in_p[sz-DES_IVLEN]),
+                                 DES_IVLEN);
+	        }
+
+        }
+
+        ByteReverseWords((word32*)out, (word32 *)KVA0_TO_KVA1(out), sz);
+    }
+
+    int wc_Des_CbcEncrypt(Des* des, byte* out, const byte* in, word32 sz)
+    {
+        DesCrypt(des->key, des->reg, out, in, sz, 
+                PIC32_ENCRYPTION, PIC32_ALGO_DES, PIC32_CRYPTOALGO_CBC );
+        return 0;
+    }
+
+    int wc_Des_CbcDecrypt(Des* des, byte* out, const byte* in, word32 sz)
+    {
+        DesCrypt(des->key, des->reg, out, in, sz, 
+                PIC32_DECRYPTION, PIC32_ALGO_DES, PIC32_CRYPTOALGO_CBC);
+        return 0;
+    }
+
+    int wc_Des3_CbcEncrypt(Des3* des, byte* out, const byte* in, word32 sz)
+    {
+        DesCrypt(des->key[0], des->reg, out, in, sz, 
+                PIC32_ENCRYPTION, PIC32_ALGO_TDES, PIC32_CRYPTOALGO_TCBC);
+        return 0;
+    }
+
+    int wc_Des3_CbcDecrypt(Des3* des, byte* out, const byte* in, word32 sz)
+    {
+        DesCrypt(des->key[0], des->reg, out, in, sz, 
+                PIC32_DECRYPTION, PIC32_ALGO_TDES, PIC32_CRYPTOALGO_TCBC);
+        return 0;
+    }
+    
+#else /* CTaoCrypt software implementation */
+
+/* permuted choice table (key) */
+static const byte pc1[] = {
+       57, 49, 41, 33, 25, 17,  9,
+        1, 58, 50, 42, 34, 26, 18,
+       10,  2, 59, 51, 43, 35, 27,
+       19, 11,  3, 60, 52, 44, 36,
+
+       63, 55, 47, 39, 31, 23, 15,
+        7, 62, 54, 46, 38, 30, 22,
+       14,  6, 61, 53, 45, 37, 29,
+       21, 13,  5, 28, 20, 12,  4
+};
+
+/* number left rotations of pc1 */
+static const byte totrot[] = {
+       1,2,4,6,8,10,12,14,15,17,19,21,23,25,27,28
+};
+
+/* permuted choice key (table) */
+static const byte pc2[] = {
+       14, 17, 11, 24,  1,  5,
+        3, 28, 15,  6, 21, 10,
+       23, 19, 12,  4, 26,  8,
+       16,  7, 27, 20, 13,  2,
+       41, 52, 31, 37, 47, 55,
+       30, 40, 51, 45, 33, 48,
+       44, 49, 39, 56, 34, 53,
+       46, 42, 50, 36, 29, 32
+};
+
+/* End of DES-defined tables */
+
+/* bit 0 is left-most in byte */
+static const int bytebit[] = {
+       0200,0100,040,020,010,04,02,01
+};
+
+static const word32 Spbox[8][64] = {
+{
+0x01010400,0x00000000,0x00010000,0x01010404,
+0x01010004,0x00010404,0x00000004,0x00010000,
+0x00000400,0x01010400,0x01010404,0x00000400,
+0x01000404,0x01010004,0x01000000,0x00000004,
+0x00000404,0x01000400,0x01000400,0x00010400,
+0x00010400,0x01010000,0x01010000,0x01000404,
+0x00010004,0x01000004,0x01000004,0x00010004,
+0x00000000,0x00000404,0x00010404,0x01000000,
+0x00010000,0x01010404,0x00000004,0x01010000,
+0x01010400,0x01000000,0x01000000,0x00000400,
+0x01010004,0x00010000,0x00010400,0x01000004,
+0x00000400,0x00000004,0x01000404,0x00010404,
+0x01010404,0x00010004,0x01010000,0x01000404,
+0x01000004,0x00000404,0x00010404,0x01010400,
+0x00000404,0x01000400,0x01000400,0x00000000,
+0x00010004,0x00010400,0x00000000,0x01010004},
+{
+0x80108020,0x80008000,0x00008000,0x00108020,
+0x00100000,0x00000020,0x80100020,0x80008020,
+0x80000020,0x80108020,0x80108000,0x80000000,
+0x80008000,0x00100000,0x00000020,0x80100020,
+0x00108000,0x00100020,0x80008020,0x00000000,
+0x80000000,0x00008000,0x00108020,0x80100000,
+0x00100020,0x80000020,0x00000000,0x00108000,
+0x00008020,0x80108000,0x80100000,0x00008020,
+0x00000000,0x00108020,0x80100020,0x00100000,
+0x80008020,0x80100000,0x80108000,0x00008000,
+0x80100000,0x80008000,0x00000020,0x80108020,
+0x00108020,0x00000020,0x00008000,0x80000000,
+0x00008020,0x80108000,0x00100000,0x80000020,
+0x00100020,0x80008020,0x80000020,0x00100020,
+0x00108000,0x00000000,0x80008000,0x00008020,
+0x80000000,0x80100020,0x80108020,0x00108000},
+{
+0x00000208,0x08020200,0x00000000,0x08020008,
+0x08000200,0x00000000,0x00020208,0x08000200,
+0x00020008,0x08000008,0x08000008,0x00020000,
+0x08020208,0x00020008,0x08020000,0x00000208,
+0x08000000,0x00000008,0x08020200,0x00000200,
+0x00020200,0x08020000,0x08020008,0x00020208,
+0x08000208,0x00020200,0x00020000,0x08000208,
+0x00000008,0x08020208,0x00000200,0x08000000,
+0x08020200,0x08000000,0x00020008,0x00000208,
+0x00020000,0x08020200,0x08000200,0x00000000,
+0x00000200,0x00020008,0x08020208,0x08000200,
+0x08000008,0x00000200,0x00000000,0x08020008,
+0x08000208,0x00020000,0x08000000,0x08020208,
+0x00000008,0x00020208,0x00020200,0x08000008,
+0x08020000,0x08000208,0x00000208,0x08020000,
+0x00020208,0x00000008,0x08020008,0x00020200},
+{
+0x00802001,0x00002081,0x00002081,0x00000080,
+0x00802080,0x00800081,0x00800001,0x00002001,
+0x00000000,0x00802000,0x00802000,0x00802081,
+0x00000081,0x00000000,0x00800080,0x00800001,
+0x00000001,0x00002000,0x00800000,0x00802001,
+0x00000080,0x00800000,0x00002001,0x00002080,
+0x00800081,0x00000001,0x00002080,0x00800080,
+0x00002000,0x00802080,0x00802081,0x00000081,
+0x00800080,0x00800001,0x00802000,0x00802081,
+0x00000081,0x00000000,0x00000000,0x00802000,
+0x00002080,0x00800080,0x00800081,0x00000001,
+0x00802001,0x00002081,0x00002081,0x00000080,
+0x00802081,0x00000081,0x00000001,0x00002000,
+0x00800001,0x00002001,0x00802080,0x00800081,
+0x00002001,0x00002080,0x00800000,0x00802001,
+0x00000080,0x00800000,0x00002000,0x00802080},
+{
+0x00000100,0x02080100,0x02080000,0x42000100,
+0x00080000,0x00000100,0x40000000,0x02080000,
+0x40080100,0x00080000,0x02000100,0x40080100,
+0x42000100,0x42080000,0x00080100,0x40000000,
+0x02000000,0x40080000,0x40080000,0x00000000,
+0x40000100,0x42080100,0x42080100,0x02000100,
+0x42080000,0x40000100,0x00000000,0x42000000,
+0x02080100,0x02000000,0x42000000,0x00080100,
+0x00080000,0x42000100,0x00000100,0x02000000,
+0x40000000,0x02080000,0x42000100,0x40080100,
+0x02000100,0x40000000,0x42080000,0x02080100,
+0x40080100,0x00000100,0x02000000,0x42080000,
+0x42080100,0x00080100,0x42000000,0x42080100,
+0x02080000,0x00000000,0x40080000,0x42000000,
+0x00080100,0x02000100,0x40000100,0x00080000,
+0x00000000,0x40080000,0x02080100,0x40000100},
+{
+0x20000010,0x20400000,0x00004000,0x20404010,
+0x20400000,0x00000010,0x20404010,0x00400000,
+0x20004000,0x00404010,0x00400000,0x20000010,
+0x00400010,0x20004000,0x20000000,0x00004010,
+0x00000000,0x00400010,0x20004010,0x00004000,
+0x00404000,0x20004010,0x00000010,0x20400010,
+0x20400010,0x00000000,0x00404010,0x20404000,
+0x00004010,0x00404000,0x20404000,0x20000000,
+0x20004000,0x00000010,0x20400010,0x00404000,
+0x20404010,0x00400000,0x00004010,0x20000010,
+0x00400000,0x20004000,0x20000000,0x00004010,
+0x20000010,0x20404010,0x00404000,0x20400000,
+0x00404010,0x20404000,0x00000000,0x20400010,
+0x00000010,0x00004000,0x20400000,0x00404010,
+0x00004000,0x00400010,0x20004010,0x00000000,
+0x20404000,0x20000000,0x00400010,0x20004010},
+{
+0x00200000,0x04200002,0x04000802,0x00000000,
+0x00000800,0x04000802,0x00200802,0x04200800,
+0x04200802,0x00200000,0x00000000,0x04000002,
+0x00000002,0x04000000,0x04200002,0x00000802,
+0x04000800,0x00200802,0x00200002,0x04000800,
+0x04000002,0x04200000,0x04200800,0x00200002,
+0x04200000,0x00000800,0x00000802,0x04200802,
+0x00200800,0x00000002,0x04000000,0x00200800,
+0x04000000,0x00200800,0x00200000,0x04000802,
+0x04000802,0x04200002,0x04200002,0x00000002,
+0x00200002,0x04000000,0x04000800,0x00200000,
+0x04200800,0x00000802,0x00200802,0x04200800,
+0x00000802,0x04000002,0x04200802,0x04200000,
+0x00200800,0x00000000,0x00000002,0x04200802,
+0x00000000,0x00200802,0x04200000,0x00000800,
+0x04000002,0x04000800,0x00000800,0x00200002},
+{
+0x10001040,0x00001000,0x00040000,0x10041040,
+0x10000000,0x10001040,0x00000040,0x10000000,
+0x00040040,0x10040000,0x10041040,0x00041000,
+0x10041000,0x00041040,0x00001000,0x00000040,
+0x10040000,0x10000040,0x10001000,0x00001040,
+0x00041000,0x00040040,0x10040040,0x10041000,
+0x00001040,0x00000000,0x00000000,0x10040040,
+0x10000040,0x10001000,0x00041040,0x00040000,
+0x00041040,0x00040000,0x10041000,0x00001000,
+0x00000040,0x10040040,0x00001000,0x00041040,
+0x10001000,0x00000040,0x10000040,0x10040000,
+0x10040040,0x10000000,0x00040000,0x10001040,
+0x00000000,0x10041040,0x00040040,0x10000040,
+0x10040000,0x10001000,0x10001040,0x00000000,
+0x10041040,0x00041000,0x00041000,0x00001040,
+0x00001040,0x00040040,0x10000000,0x10041000}
+};
+
+
+static INLINE void IPERM(word32* left, word32* right)
+{
+    word32 work;
+
+    *right = rotlFixed(*right, 4U);
+    work = (*left ^ *right) & 0xf0f0f0f0;
+    *left ^= work;
+
+    *right = rotrFixed(*right^work, 20U);
+    work = (*left ^ *right) & 0xffff0000;
+    *left ^= work;
+
+    *right = rotrFixed(*right^work, 18U);
+    work = (*left ^ *right) & 0x33333333;
+    *left ^= work;
+
+    *right = rotrFixed(*right^work, 6U);
+    work = (*left ^ *right) & 0x00ff00ff;
+    *left ^= work;
+
+    *right = rotlFixed(*right^work, 9U);
+    work = (*left ^ *right) & 0xaaaaaaaa;
+    *left = rotlFixed(*left^work, 1U);
+    *right ^= work;
+}
+
+
+static INLINE void FPERM(word32* left, word32* right)
+{
+    word32 work;
+
+    *right = rotrFixed(*right, 1U);
+    work = (*left ^ *right) & 0xaaaaaaaa;
+    *right ^= work;
+
+    *left = rotrFixed(*left^work, 9U);
+    work = (*left ^ *right) & 0x00ff00ff;
+    *right ^= work;
+
+    *left = rotlFixed(*left^work, 6U);
+    work = (*left ^ *right) & 0x33333333;
+    *right ^= work;
+
+    *left = rotlFixed(*left^work, 18U);
+    work = (*left ^ *right) & 0xffff0000;
+    *right ^= work;
+
+    *left = rotlFixed(*left^work, 20U);
+    work = (*left ^ *right) & 0xf0f0f0f0;
+    *right ^= work;
+
+    *left = rotrFixed(*left^work, 4U);
+}
+
+
+static int DesSetKey(const byte* key, int dir, word32* out)
+{
+#ifdef WOLFSSL_SMALL_STACK
+    byte* buffer = (byte*)XMALLOC(56+56+8, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+
+    if (buffer == NULL)
+        return MEMORY_E;
+#else
+    byte buffer[56+56+8];
+#endif
+
+    {
+        byte* const  pc1m = buffer;               /* place to modify pc1 into */
+        byte* const  pcr  = pc1m + 56;            /* place to rotate pc1 into */
+        byte* const  ks   = pcr  + 56;
+        register int i, j, l;
+        int          m;
+
+        for (j = 0; j < 56; j++) {             /* convert pc1 to bits of key  */
+            l = pc1[j] - 1;                    /* integer bit location        */
+            m = l & 07;                        /* find bit                    */
+            pc1m[j] = (key[l >> 3] &           /* find which key byte l is in */
+                bytebit[m])                    /* and which bit of that byte  */
+                ? 1 : 0;                       /* and store 1-bit result      */
+        }
+
+        for (i = 0; i < 16; i++) {            /* key chunk for each iteration */
+            XMEMSET(ks, 0, 8);                /* Clear key schedule */
+
+            for (j = 0; j < 56; j++)          /* rotate pc1 the right amount  */
+                pcr[j] =
+                      pc1m[(l = j + totrot[i]) < (j < 28 ? 28 : 56) ? l : l-28];
+
+            /* rotate left and right halves independently */
+            for (j = 0; j < 48; j++) {        /* select bits individually     */
+                if (pcr[pc2[j] - 1]) {        /* check bit that goes to ks[j] */
+                    l= j % 6;                 /* mask it in if it's there     */
+                    ks[j/6] |= bytebit[l] >> 2;
+                }
+            }
+
+            /* Now convert to odd/even interleaved form for use in F */
+            out[2*i] = ((word32) ks[0] << 24)
+                     | ((word32) ks[2] << 16)
+                     | ((word32) ks[4] << 8)
+                     | ((word32) ks[6]);
+
+            out[2*i + 1] = ((word32) ks[1] << 24)
+                         | ((word32) ks[3] << 16)
+                         | ((word32) ks[5] << 8)
+                         | ((word32) ks[7]);
+        }
+
+        /* reverse key schedule order */
+        if (dir == DES_DECRYPTION) {
+            for (i = 0; i < 16; i += 2) {
+                word32 swap = out[i];
+                out[i] = out[DES_KS_SIZE - 2 - i];
+                out[DES_KS_SIZE - 2 - i] = swap;
+    
+                swap = out[i + 1];
+                out[i + 1] = out[DES_KS_SIZE - 1 - i];
+                out[DES_KS_SIZE - 1 - i] = swap;
+            }
+        }
+
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(buffer, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+    }
+
+    return 0;
+}
+
+
+static INLINE int Reverse(int dir)
+{
+    return !dir;
+}
+
+
+int wc_Des_SetKey(Des* des, const byte* key, const byte* iv, int dir)
+{
+    wc_Des_SetIV(des, iv);
+
+    return DesSetKey(key, dir, des->key);
+}
+
+
+int wc_Des3_SetKey(Des3* des, const byte* key, const byte* iv, int dir)
+{
+    int ret;
+
+#ifdef HAVE_CAVIUM
+    if (des->magic == WOLFSSL_3DES_CAVIUM_MAGIC)
+        return wc_Des3_CaviumSetKey(des, key, iv);
+#endif
+
+    ret = DesSetKey(key + (dir == DES_ENCRYPTION ? 0:16), dir, des->key[0]);
+    if (ret != 0)
+        return ret;
+
+    ret = DesSetKey(key + 8, Reverse(dir), des->key[1]);
+    if (ret != 0)
+        return ret;
+
+    ret = DesSetKey(key + (dir == DES_DECRYPTION ? 0:16), dir, des->key[2]);
+    if (ret != 0)
+        return ret;
+
+    return wc_Des3_SetIV(des, iv);
+}
+
+
+static void DesRawProcessBlock(word32* lIn, word32* rIn, const word32* kptr)
+{
+    word32 l = *lIn, r = *rIn, i;
+
+    for (i=0; i<8; i++)
+    {
+        word32 work = rotrFixed(r, 4U) ^ kptr[4*i+0];
+        l ^= Spbox[6][(work) & 0x3f]
+          ^  Spbox[4][(work >> 8) & 0x3f]
+          ^  Spbox[2][(work >> 16) & 0x3f]
+          ^  Spbox[0][(work >> 24) & 0x3f];
+        work = r ^ kptr[4*i+1];
+        l ^= Spbox[7][(work) & 0x3f]
+          ^  Spbox[5][(work >> 8) & 0x3f]
+          ^  Spbox[3][(work >> 16) & 0x3f]
+          ^  Spbox[1][(work >> 24) & 0x3f];
+
+        work = rotrFixed(l, 4U) ^ kptr[4*i+2];
+        r ^= Spbox[6][(work) & 0x3f]
+          ^  Spbox[4][(work >> 8) & 0x3f]
+          ^  Spbox[2][(work >> 16) & 0x3f]
+          ^  Spbox[0][(work >> 24) & 0x3f];
+        work = l ^ kptr[4*i+3];
+        r ^= Spbox[7][(work) & 0x3f]
+          ^  Spbox[5][(work >> 8) & 0x3f]
+          ^  Spbox[3][(work >> 16) & 0x3f]
+          ^  Spbox[1][(work >> 24) & 0x3f];
+    }
+
+    *lIn = l; *rIn = r;
+}
+
+
+static void DesProcessBlock(Des* des, const byte* in, byte* out)
+{
+    word32 l, r;
+
+    XMEMCPY(&l, in, sizeof(l));
+    XMEMCPY(&r, in + sizeof(l), sizeof(r));
+    #ifdef LITTLE_ENDIAN_ORDER
+        l = ByteReverseWord32(l);
+        r = ByteReverseWord32(r);
+    #endif
+    IPERM(&l,&r);
+    
+    DesRawProcessBlock(&l, &r, des->key);   
+
+    FPERM(&l,&r);
+    #ifdef LITTLE_ENDIAN_ORDER
+        l = ByteReverseWord32(l);
+        r = ByteReverseWord32(r);
+    #endif
+    XMEMCPY(out, &r, sizeof(r));
+    XMEMCPY(out + sizeof(r), &l, sizeof(l));
+}
+
+
+static void Des3ProcessBlock(Des3* des, const byte* in, byte* out)
+{
+    word32 l, r;
+
+    XMEMCPY(&l, in, sizeof(l));
+    XMEMCPY(&r, in + sizeof(l), sizeof(r));
+    #ifdef LITTLE_ENDIAN_ORDER
+        l = ByteReverseWord32(l);
+        r = ByteReverseWord32(r);
+    #endif
+    IPERM(&l,&r);
+    
+    DesRawProcessBlock(&l, &r, des->key[0]);   
+    DesRawProcessBlock(&r, &l, des->key[1]);   
+    DesRawProcessBlock(&l, &r, des->key[2]);   
+
+    FPERM(&l,&r);
+    #ifdef LITTLE_ENDIAN_ORDER
+        l = ByteReverseWord32(l);
+        r = ByteReverseWord32(r);
+    #endif
+    XMEMCPY(out, &r, sizeof(r));
+    XMEMCPY(out + sizeof(r), &l, sizeof(l));
+}
+
+
+int wc_Des_CbcEncrypt(Des* des, byte* out, const byte* in, word32 sz)
+{
+    word32 blocks = sz / DES_BLOCK_SIZE;
+
+    while (blocks--) {
+        xorbuf((byte*)des->reg, in, DES_BLOCK_SIZE);
+        DesProcessBlock(des, (byte*)des->reg, (byte*)des->reg);
+        XMEMCPY(out, des->reg, DES_BLOCK_SIZE);
+
+        out += DES_BLOCK_SIZE;
+        in  += DES_BLOCK_SIZE; 
+    }
+    return 0;
+}
+
+
+int wc_Des_CbcDecrypt(Des* des, byte* out, const byte* in, word32 sz)
+{
+    word32 blocks = sz / DES_BLOCK_SIZE;
+    byte   hold[DES_BLOCK_SIZE];
+
+    while (blocks--) {
+        XMEMCPY(des->tmp, in, DES_BLOCK_SIZE);
+        DesProcessBlock(des, (byte*)des->tmp, out);
+        xorbuf(out, (byte*)des->reg, DES_BLOCK_SIZE);
+
+        XMEMCPY(hold, des->reg, DES_BLOCK_SIZE);
+        XMEMCPY(des->reg, des->tmp, DES_BLOCK_SIZE);
+        XMEMCPY(des->tmp, hold, DES_BLOCK_SIZE);
+
+        out += DES_BLOCK_SIZE;
+        in  += DES_BLOCK_SIZE; 
+    }
+    return 0;
+}
+
+
+int wc_Des3_CbcEncrypt(Des3* des, byte* out, const byte* in, word32 sz)
+{
+    word32 blocks;
+
+#ifdef HAVE_CAVIUM
+    if (des->magic == WOLFSSL_3DES_CAVIUM_MAGIC)
+        return wc_Des3_CaviumCbcEncrypt(des, out, in, sz);
+#endif
+
+    blocks = sz / DES_BLOCK_SIZE;
+    while (blocks--) {
+        xorbuf((byte*)des->reg, in, DES_BLOCK_SIZE);
+        Des3ProcessBlock(des, (byte*)des->reg, (byte*)des->reg);
+        XMEMCPY(out, des->reg, DES_BLOCK_SIZE);
+
+        out += DES_BLOCK_SIZE;
+        in  += DES_BLOCK_SIZE; 
+    }
+    return 0;
+}
+
+
+int wc_Des3_CbcDecrypt(Des3* des, byte* out, const byte* in, word32 sz)
+{
+    word32 blocks;
+
+#ifdef HAVE_CAVIUM
+    if (des->magic == WOLFSSL_3DES_CAVIUM_MAGIC)
+        return wc_Des3_CaviumCbcDecrypt(des, out, in, sz);
+#endif
+
+    blocks = sz / DES_BLOCK_SIZE;
+    while (blocks--) {
+        XMEMCPY(des->tmp, in, DES_BLOCK_SIZE);
+        Des3ProcessBlock(des, (byte*)des->tmp, out);
+        xorbuf(out, (byte*)des->reg, DES_BLOCK_SIZE);
+        XMEMCPY(des->reg, des->tmp, DES_BLOCK_SIZE);
+
+        out += DES_BLOCK_SIZE;
+        in  += DES_BLOCK_SIZE; 
+    }
+    return 0;
+}
+
+#ifdef WOLFSSL_DES_ECB
+
+/* One block, compatibility only */
+int wc_Des_EcbEncrypt(Des* des, byte* out, const byte* in, word32 sz)
+{
+    word32 blocks = sz / DES_BLOCK_SIZE;
+
+    while (blocks--) {
+        DesProcessBlock(des, in, out);
+
+        out += DES_BLOCK_SIZE;
+        in  += DES_BLOCK_SIZE; 
+    }
+    return 0;
+}
+
+#endif /* WOLFSSL_DES_ECB */
+
+#endif /* STM32F2_CRYPTO */
+
+void wc_Des_SetIV(Des* des, const byte* iv)
+{
+    if (des && iv)
+        XMEMCPY(des->reg, iv, DES_BLOCK_SIZE);
+    else if (des)
+        XMEMSET(des->reg,  0, DES_BLOCK_SIZE);
+}
+
+
+int wc_Des_CbcDecryptWithKey(byte* out, const byte* in, word32 sz,
+                                                const byte* key, const byte* iv)
+{
+    int ret  = 0;
+#ifdef WOLFSSL_SMALL_STACK
+    Des* des = NULL;
+#else
+    Des  des[1];
+#endif
+
+#ifdef WOLFSSL_SMALL_STACK
+    des = (Des*)XMALLOC(sizeof(Des), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (des == NULL)
+        return MEMORY_E;
+#endif
+
+    ret = wc_Des_SetKey(des, key, iv, DES_DECRYPTION);
+    if (ret == 0)
+        ret = wc_Des_CbcDecrypt(des, out, in, sz); 
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(des, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+
+int wc_Des3_SetIV(Des3* des, const byte* iv)
+{
+    if (des && iv)
+        XMEMCPY(des->reg, iv, DES_BLOCK_SIZE);
+    else if (des)
+        XMEMSET(des->reg,  0, DES_BLOCK_SIZE);
+
+    return 0;
+}
+
+
+int wc_Des3_CbcDecryptWithKey(byte* out, const byte* in, word32 sz,
+                                                const byte* key, const byte* iv)
+{
+    int ret    = 0;
+#ifdef WOLFSSL_SMALL_STACK
+    Des3* des3 = NULL;
+#else
+    Des3  des3[1];
+#endif
+
+#ifdef WOLFSSL_SMALL_STACK
+    des3 = (Des3*)XMALLOC(sizeof(Des3), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (des3 == NULL)
+        return MEMORY_E;
+#endif
+
+    ret = wc_Des3_SetKey(des3, key, iv, DES_DECRYPTION);
+    if (ret == 0)
+        ret = wc_Des3_CbcDecrypt(des3, out, in, sz); 
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(des3, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+
+#ifdef HAVE_CAVIUM
+
+#include "cavium_common.h"
+
+/* Initiliaze Des3 for use with Nitrox device */
+int wc_Des3_InitCavium(Des3* des3, int devId)
+{
+    if (des3 == NULL)
+        return -1;
+
+    if (CspAllocContext(CONTEXT_SSL, &des3->contextHandle, devId) != 0)
+        return -1;
+
+    des3->devId = devId;
+    des3->magic = WOLFSSL_3DES_CAVIUM_MAGIC;
+   
+    return 0;
+}
+
+
+/* Free Des3 from use with Nitrox device */
+void wc_Des3_FreeCavium(Des3* des3)
+{
+    if (des3 == NULL)
+        return;
+
+    if (des3->magic != WOLFSSL_3DES_CAVIUM_MAGIC)
+        return;
+
+    CspFreeContext(CONTEXT_SSL, des3->contextHandle, des3->devId);
+    des3->magic = 0;
+}
+
+
+static int wc_Des3_CaviumSetKey(Des3* des3, const byte* key, const byte* iv)
+{
+    if (des3 == NULL)
+        return -1;
+
+    /* key[0] holds key, iv in reg */
+    XMEMCPY(des3->key[0], key, DES_BLOCK_SIZE*3);
+
+    return wc_Des3_SetIV(des3, iv);
+}
+
+
+static int wc_Des3_CaviumCbcEncrypt(Des3* des3, byte* out, const byte* in,
+                                  word32 length)
+{
+    wolfssl_word offset = 0;
+    word32 requestId;
+   
+    while (length > WOLFSSL_MAX_16BIT) {
+        word16 slen = (word16)WOLFSSL_MAX_16BIT;
+        if (CspEncrypt3Des(CAVIUM_BLOCKING, des3->contextHandle,
+                           CAVIUM_NO_UPDATE, slen, (byte*)in + offset,
+                           out + offset, (byte*)des3->reg, (byte*)des3->key[0],
+                           &requestId, des3->devId) != 0) {
+            WOLFSSL_MSG("Bad Cavium 3DES Cbc Encrypt");
+            return -1;
+        }
+        length -= WOLFSSL_MAX_16BIT;
+        offset += WOLFSSL_MAX_16BIT;
+        XMEMCPY(des3->reg, out + offset - DES_BLOCK_SIZE, DES_BLOCK_SIZE);
+    }
+    if (length) {
+        word16 slen = (word16)length;
+
+        if (CspEncrypt3Des(CAVIUM_BLOCKING, des3->contextHandle,
+                           CAVIUM_NO_UPDATE, slen, (byte*)in + offset,
+                           out + offset, (byte*)des3->reg, (byte*)des3->key[0],
+                           &requestId, des3->devId) != 0) {
+            WOLFSSL_MSG("Bad Cavium 3DES Cbc Encrypt");
+            return -1;
+        }
+        XMEMCPY(des3->reg, out+offset+length - DES_BLOCK_SIZE, DES_BLOCK_SIZE);
+    }
+    return 0;
+}
+
+static int wc_Des3_CaviumCbcDecrypt(Des3* des3, byte* out, const byte* in,
+                                 word32 length)
+{
+    word32 requestId;
+    wolfssl_word offset = 0;
+
+    while (length > WOLFSSL_MAX_16BIT) {
+        word16 slen = (word16)WOLFSSL_MAX_16BIT;
+        XMEMCPY(des3->tmp, in + offset + slen - DES_BLOCK_SIZE, DES_BLOCK_SIZE);
+        if (CspDecrypt3Des(CAVIUM_BLOCKING, des3->contextHandle,
+                           CAVIUM_NO_UPDATE, slen, (byte*)in+offset, out+offset,
+                           (byte*)des3->reg, (byte*)des3->key[0], &requestId,
+                           des3->devId) != 0) {
+            WOLFSSL_MSG("Bad Cavium 3Des Decrypt");
+            return -1;
+        }
+        length -= WOLFSSL_MAX_16BIT;
+        offset += WOLFSSL_MAX_16BIT;
+        XMEMCPY(des3->reg, des3->tmp, DES_BLOCK_SIZE);
+    }
+    if (length) {
+        word16 slen = (word16)length;
+        XMEMCPY(des3->tmp, in + offset + slen - DES_BLOCK_SIZE,DES_BLOCK_SIZE);
+        if (CspDecrypt3Des(CAVIUM_BLOCKING, des3->contextHandle,
+                           CAVIUM_NO_UPDATE, slen, (byte*)in+offset, out+offset,
+                           (byte*)des3->reg, (byte*)des3->key[0], &requestId,
+                           des3->devId) != 0) {
+            WOLFSSL_MSG("Bad Cavium 3Des Decrypt");
+            return -1;
+        }
+        XMEMCPY(des3->reg, des3->tmp, DES_BLOCK_SIZE);
+    }
+    return 0;
+}
+
+#endif /* HAVE_CAVIUM */
+#endif /* WOLFSSL_TI_CRYPT */
+#endif /* HAVE_FIPS */
+#endif /* NO_DES3 */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/dh.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/dh.c
new file mode 100644
index 0000000..bc4ce11
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/dh.c
@@ -0,0 +1,216 @@
+/* dh.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifndef NO_DH
+
+#include 
+#include 
+
+#ifndef USER_MATH_LIB
+    #include 
+    #define XPOW(x,y) pow((x),(y))
+    #define XLOG(x)   log((x))
+#else
+    /* user's own math lib */
+#endif
+
+
+#ifndef WOLFSSL_HAVE_MIN
+#define WOLFSSL_HAVE_MIN
+
+    static INLINE word32 min(word32 a, word32 b)
+    {
+        return a > b ? b : a;
+    }
+
+#endif /* WOLFSSL_HAVE_MIN */
+
+
+void wc_InitDhKey(DhKey* key)
+{
+    (void)key;
+/* TomsFastMath doesn't use memory allocation */
+#ifndef USE_FAST_MATH
+    key->p.dp = 0;
+    key->g.dp = 0;
+#endif
+}
+
+
+void wc_FreeDhKey(DhKey* key)
+{
+    (void)key;
+/* TomsFastMath doesn't use memory allocation */
+#ifndef USE_FAST_MATH
+    mp_clear(&key->p);
+    mp_clear(&key->g);
+#endif
+}
+
+
+static word32 DiscreteLogWorkFactor(word32 n)
+{
+    /* assuming discrete log takes about the same time as factoring */
+    if (n<5)
+        return 0;
+    else
+        return (word32)(2.4 * XPOW((double)n, 1.0/3.0) *
+                XPOW(XLOG((double)n), 2.0/3.0) - 5);
+}
+
+
+static int GeneratePrivate(DhKey* key, RNG* rng, byte* priv, word32* privSz)
+{
+    int ret;
+    word32 sz = mp_unsigned_bin_size(&key->p);
+    sz = min(sz, 2 * DiscreteLogWorkFactor(sz * WOLFSSL_BIT_SIZE) /
+                                           WOLFSSL_BIT_SIZE + 1);
+
+    ret = wc_RNG_GenerateBlock(rng, priv, sz);
+    if (ret != 0)
+        return ret;
+
+    priv[0] |= 0x0C;
+
+    *privSz = sz;
+
+    return 0;
+}
+
+
+static int GeneratePublic(DhKey* key, const byte* priv, word32 privSz,
+                          byte* pub, word32* pubSz)
+{
+    int ret = 0;
+
+    mp_int x; 
+    mp_int y;
+
+    if (mp_init_multi(&x, &y, 0, 0, 0, 0) != MP_OKAY)
+        return MP_INIT_E;
+
+    if (mp_read_unsigned_bin(&x, priv, privSz) != MP_OKAY)
+        ret = MP_READ_E;
+
+    if (ret == 0 && mp_exptmod(&key->g, &x, &key->p, &y) != MP_OKAY)
+        ret = MP_EXPTMOD_E;
+
+    if (ret == 0 && mp_to_unsigned_bin(&y, pub) != MP_OKAY)
+        ret = MP_TO_E;
+
+    if (ret == 0)
+        *pubSz = mp_unsigned_bin_size(&y);
+
+    mp_clear(&y);
+    mp_clear(&x);
+
+    return ret;
+}
+
+
+int wc_DhGenerateKeyPair(DhKey* key, RNG* rng, byte* priv, word32* privSz,
+                      byte* pub, word32* pubSz)
+{
+    int ret = GeneratePrivate(key, rng, priv, privSz);
+
+    return (ret != 0) ? ret : GeneratePublic(key, priv, *privSz, pub, pubSz);
+}
+
+int wc_DhAgree(DhKey* key, byte* agree, word32* agreeSz, const byte* priv,
+            word32 privSz, const byte* otherPub, word32 pubSz)
+{
+    int ret = 0;
+
+    mp_int x; 
+    mp_int y;
+    mp_int z;
+
+    if (mp_init_multi(&x, &y, &z, 0, 0, 0) != MP_OKAY)
+        return MP_INIT_E;
+
+    if (mp_read_unsigned_bin(&x, priv, privSz) != MP_OKAY)
+        ret = MP_READ_E;
+
+    if (ret == 0 && mp_read_unsigned_bin(&y, otherPub, pubSz) != MP_OKAY)
+        ret = MP_READ_E;
+
+    if (ret == 0 && mp_exptmod(&y, &x, &key->p, &z) != MP_OKAY)
+        ret = MP_EXPTMOD_E;
+
+    if (ret == 0 && mp_to_unsigned_bin(&z, agree) != MP_OKAY)
+        ret = MP_TO_E;
+
+    if (ret == 0)
+        *agreeSz = mp_unsigned_bin_size(&z);
+
+    mp_clear(&z);
+    mp_clear(&y);
+    mp_clear(&x);
+
+    return ret;
+}
+
+
+/* not in asn anymore since no actual asn types used */
+int wc_DhSetKey(DhKey* key, const byte* p, word32 pSz, const byte* g,
+                word32 gSz)
+{
+    if (key == NULL || p == NULL || g == NULL || pSz == 0 || gSz == 0)
+        return BAD_FUNC_ARG;
+
+    /* may have leading 0 */
+    if (p[0] == 0) {
+        pSz--; p++;
+    }
+
+    if (g[0] == 0) {
+        gSz--; g++;
+    }
+
+    if (mp_init(&key->p) != MP_OKAY)
+        return MP_INIT_E;
+    if (mp_read_unsigned_bin(&key->p, p, pSz) != 0) {
+        mp_clear(&key->p);
+        return ASN_DH_KEY_E;
+    }
+
+    if (mp_init(&key->g) != MP_OKAY) {
+        mp_clear(&key->p);
+        return MP_INIT_E;
+    }
+    if (mp_read_unsigned_bin(&key->g, g, gSz) != 0) {
+        mp_clear(&key->g);
+        mp_clear(&key->p);
+        return ASN_DH_KEY_E;
+    }
+
+    return 0;
+}
+
+
+#endif /* NO_DH */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/dsa.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/dsa.c
new file mode 100644
index 0000000..f2124b1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/dsa.c
@@ -0,0 +1,232 @@
+/* dsa.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifndef NO_DSA
+
+#include 
+#include 
+#include 
+#include 
+
+
+enum {
+    DSA_HALF_SIZE = 20,   /* r and s size  */
+    DSA_SIG_SIZE  = 40    /* signature size */
+};
+
+
+#ifndef WOLFSSL_HAVE_MIN
+#define WOLFSSL_HAVE_MIN
+
+    static INLINE word32 min(word32 a, word32 b)
+    {
+        return a > b ? b : a;
+    }
+
+#endif /* WOLFSSL_HAVE_MIN */
+
+
+void wc_InitDsaKey(DsaKey* key)
+{
+    key->type = -1;  /* haven't decided yet */
+
+/* TomsFastMath doesn't use memory allocation */
+#ifndef USE_FAST_MATH
+    key->p.dp = 0;   /* public  alloc parts */
+    key->q.dp = 0;    
+    key->g.dp = 0;    
+    key->y.dp = 0;    
+
+    key->x.dp = 0;   /* private alloc parts */
+#endif
+}
+
+
+void wc_FreeDsaKey(DsaKey* key)
+{
+    (void)key;
+/* TomsFastMath doesn't use memory allocation */
+#ifndef USE_FAST_MATH
+    if (key->type == DSA_PRIVATE)
+        mp_clear(&key->x);
+    mp_clear(&key->y);
+    mp_clear(&key->g);
+    mp_clear(&key->q);
+    mp_clear(&key->p);
+#endif
+}
+
+
+int wc_DsaSign(const byte* digest, byte* out, DsaKey* key, RNG* rng)
+{
+    mp_int k, kInv, r, s, H;
+    int    ret, sz;
+    byte   buffer[DSA_HALF_SIZE];
+
+    sz = min(sizeof(buffer), mp_unsigned_bin_size(&key->q));
+
+    /* generate k */
+    ret = wc_RNG_GenerateBlock(rng, buffer, sz);
+    if (ret != 0)
+        return ret;
+
+    buffer[0] |= 0x0C;
+
+    if (mp_init_multi(&k, &kInv, &r, &s, &H, 0) != MP_OKAY)
+        return MP_INIT_E;
+
+    if (mp_read_unsigned_bin(&k, buffer, sz) != MP_OKAY)
+        ret = MP_READ_E;
+
+    if (ret == 0 && mp_cmp_d(&k, 1) != MP_GT)
+        ret = MP_CMP_E;
+
+    /* inverse k mod q */
+    if (ret == 0 && mp_invmod(&k, &key->q, &kInv) != MP_OKAY)
+        ret = MP_INVMOD_E;
+
+    /* generate r, r = (g exp k mod p) mod q */
+    if (ret == 0 && mp_exptmod(&key->g, &k, &key->p, &r) != MP_OKAY)
+        ret = MP_EXPTMOD_E;
+
+    if (ret == 0 && mp_mod(&r, &key->q, &r) != MP_OKAY)
+        ret = MP_MOD_E;
+
+    /* generate H from sha digest */
+    if (ret == 0 && mp_read_unsigned_bin(&H, digest,SHA_DIGEST_SIZE) != MP_OKAY)
+        ret = MP_READ_E;
+
+    /* generate s, s = (kInv * (H + x*r)) % q */
+    if (ret == 0 && mp_mul(&key->x, &r, &s) != MP_OKAY)
+        ret = MP_MUL_E;
+
+    if (ret == 0 && mp_add(&s, &H, &s) != MP_OKAY)
+        ret = MP_ADD_E;
+
+    if (ret == 0 && mp_mulmod(&s, &kInv, &key->q, &s) != MP_OKAY)
+        ret = MP_MULMOD_E;
+
+    /* write out */
+    if (ret == 0)  {
+        int rSz = mp_unsigned_bin_size(&r);
+        int sSz = mp_unsigned_bin_size(&s);
+
+        if (rSz == DSA_HALF_SIZE - 1) {
+            out[0] = 0;
+            out++;
+        }
+
+        if (mp_to_unsigned_bin(&r, out) != MP_OKAY)
+            ret = MP_TO_E;
+        else {
+            if (sSz == DSA_HALF_SIZE - 1) {
+                out[rSz] = 0;
+                out++;
+            }    
+            ret = mp_to_unsigned_bin(&s, out + rSz);
+        }
+    }
+
+    mp_clear(&H);
+    mp_clear(&s);
+    mp_clear(&r);
+    mp_clear(&kInv);
+    mp_clear(&k);
+
+    return ret;
+}
+
+
+int wc_DsaVerify(const byte* digest, const byte* sig, DsaKey* key, int* answer)
+{
+    mp_int w, u1, u2, v, r, s;
+    int    ret = 0;
+
+    if (mp_init_multi(&w, &u1, &u2, &v, &r, &s) != MP_OKAY)
+        return MP_INIT_E;
+
+    /* set r and s from signature */
+    if (mp_read_unsigned_bin(&r, sig, DSA_HALF_SIZE) != MP_OKAY ||
+        mp_read_unsigned_bin(&s, sig + DSA_HALF_SIZE, DSA_HALF_SIZE) != MP_OKAY)
+        ret = MP_READ_E;
+
+    /* sanity checks */
+    if (ret == 0) {
+        if (mp_iszero(&r) == MP_YES || mp_iszero(&s) == MP_YES ||
+                mp_cmp(&r, &key->q) != MP_LT || mp_cmp(&s, &key->q) != MP_LT) {
+            ret = MP_ZERO_E;
+        }
+    }
+
+    /* put H into u1 from sha digest */
+    if (ret == 0 && mp_read_unsigned_bin(&u1,digest,SHA_DIGEST_SIZE) != MP_OKAY)
+        ret = MP_READ_E;
+
+    /* w = s invmod q */
+    if (ret == 0 && mp_invmod(&s, &key->q, &w) != MP_OKAY)
+        ret = MP_INVMOD_E;
+
+    /* u1 = (H * w) % q */
+    if (ret == 0 && mp_mulmod(&u1, &w, &key->q, &u1) != MP_OKAY)
+        ret = MP_MULMOD_E;
+
+    /* u2 = (r * w) % q */
+    if (ret == 0 && mp_mulmod(&r, &w, &key->q, &u2) != MP_OKAY)
+        ret = MP_MULMOD_E;
+
+    /* verify v = ((g^u1 * y^u2) mod p) mod q */
+    if (ret == 0 && mp_exptmod(&key->g, &u1, &key->p, &u1) != MP_OKAY)
+        ret = MP_EXPTMOD_E;
+
+    if (ret == 0 && mp_exptmod(&key->y, &u2, &key->p, &u2) != MP_OKAY)
+        ret = MP_EXPTMOD_E;
+
+    if (ret == 0 && mp_mulmod(&u1, &u2, &key->p, &v) != MP_OKAY)
+        ret = MP_MULMOD_E;
+
+    if (ret == 0 && mp_mod(&v, &key->q, &v) != MP_OKAY)
+        ret = MP_MULMOD_E;
+
+    /* do they match */
+    if (ret == 0 && mp_cmp(&r, &v) == MP_EQ)
+        *answer = 1;
+    else
+        *answer = 0;
+
+    mp_clear(&s);
+    mp_clear(&r);
+    mp_clear(&u1);
+    mp_clear(&u2);
+    mp_clear(&w);
+    mp_clear(&v);
+
+    return ret;
+}
+
+
+#endif /* NO_DSA */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/ecc.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/ecc.c
new file mode 100644
index 0000000..897d46a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/ecc.c
@@ -0,0 +1,5186 @@
+/* ecc.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+/* in case user set HAVE_ECC there */
+#include 
+
+#ifdef HAVE_ECC
+
+#include 
+#include 
+#include 
+
+#ifdef HAVE_ECC_ENCRYPT
+    #include 
+    #include 
+#endif
+
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+/* map
+
+   ptmul -> mulmod
+
+*/
+
+
+/* p256 curve on by default whether user curves or not */
+#if defined(HAVE_ECC112) || defined(HAVE_ALL_CURVES)
+    #define ECC112
+#endif
+#if defined(HAVE_ECC128) || defined(HAVE_ALL_CURVES)
+    #define ECC128
+#endif
+#if defined(HAVE_ECC160) || defined(HAVE_ALL_CURVES)
+    #define ECC160
+#endif
+#if defined(HAVE_ECC192) || defined(HAVE_ALL_CURVES)
+    #define ECC192
+#endif
+#if defined(HAVE_ECC224) || defined(HAVE_ALL_CURVES)
+    #define ECC224
+#endif
+#if !defined(NO_ECC256)  || defined(HAVE_ALL_CURVES)
+    #define ECC256
+#endif
+#if defined(HAVE_ECC384) || defined(HAVE_ALL_CURVES)
+    #define ECC384
+#endif
+#if defined(HAVE_ECC521) || defined(HAVE_ALL_CURVES)
+    #define ECC521
+#endif
+
+
+
+/* This holds the key settings.  ***MUST*** be organized by size from
+   smallest to largest. */
+
+const ecc_set_type ecc_sets[] = {
+#ifdef ECC112
+{
+        14,
+        "SECP112R1",
+        "DB7C2ABF62E35E668076BEAD208B",
+        "DB7C2ABF62E35E668076BEAD2088",
+        "659EF8BA043916EEDE8911702B22",
+        "DB7C2ABF62E35E7628DFAC6561C5",
+        "09487239995A5EE76B55F9C2F098",
+        "A89CE5AF8724C0A23E0E0FF77500"
+},
+#endif
+#ifdef ECC128
+{
+        16,
+        "SECP128R1",
+        "FFFFFFFDFFFFFFFFFFFFFFFFFFFFFFFF",
+        "FFFFFFFDFFFFFFFFFFFFFFFFFFFFFFFC",
+        "E87579C11079F43DD824993C2CEE5ED3",
+        "FFFFFFFE0000000075A30D1B9038A115",
+        "161FF7528B899B2D0C28607CA52C5B86",
+        "CF5AC8395BAFEB13C02DA292DDED7A83",
+},
+#endif
+#ifdef ECC160
+{
+        20,
+        "SECP160R1",
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FFFFFFF",
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FFFFFFC",
+        "1C97BEFC54BD7A8B65ACF89F81D4D4ADC565FA45",
+        "0100000000000000000001F4C8F927AED3CA752257",
+        "4A96B5688EF573284664698968C38BB913CBFC82",
+        "23A628553168947D59DCC912042351377AC5FB32",
+},
+#endif
+#ifdef ECC192
+{
+        24,
+        "ECC-192",
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFF",
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFC",
+        "64210519E59C80E70FA7E9AB72243049FEB8DEECC146B9B1",
+        "FFFFFFFFFFFFFFFFFFFFFFFF99DEF836146BC9B1B4D22831",
+        "188DA80EB03090F67CBF20EB43A18800F4FF0AFD82FF1012",
+        "7192B95FFC8DA78631011ED6B24CDD573F977A11E794811",
+},
+#endif
+#ifdef ECC224
+{
+        28,
+        "ECC-224",
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001",
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFE",
+        "B4050A850C04B3ABF54132565044B0B7D7BFD8BA270B39432355FFB4",
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFF16A2E0B8F03E13DD29455C5C2A3D",
+        "B70E0CBD6BB4BF7F321390B94A03C1D356C21122343280D6115C1D21",
+        "BD376388B5F723FB4C22DFE6CD4375A05A07476444D5819985007E34",
+},
+#endif
+#ifdef ECC256
+{
+        32,
+        "ECC-256",
+        "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFF",
+        "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFC",
+        "5AC635D8AA3A93E7B3EBBD55769886BC651D06B0CC53B0F63BCE3C3E27D2604B",
+        "FFFFFFFF00000000FFFFFFFFFFFFFFFFBCE6FAADA7179E84F3B9CAC2FC632551",
+        "6B17D1F2E12C4247F8BCE6E563A440F277037D812DEB33A0F4A13945D898C296",
+        "4FE342E2FE1A7F9B8EE7EB4A7C0F9E162BCE33576B315ECECBB6406837BF51F5",
+},
+#endif
+#ifdef ECC384
+{
+        48,
+        "ECC-384",
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFF",
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFC",
+        "B3312FA7E23EE7E4988E056BE3F82D19181D9C6EFE8141120314088F5013875AC656398D8A2ED19D2A85C8EDD3EC2AEF",
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC7634D81F4372DDF581A0DB248B0A77AECEC196ACCC52973",
+        "AA87CA22BE8B05378EB1C71EF320AD746E1D3B628BA79B9859F741E082542A385502F25DBF55296C3A545E3872760AB7",
+        "3617DE4A96262C6F5D9E98BF9292DC29F8F41DBD289A147CE9DA3113B5F0B8C00A60B1CE1D7E819D7A431D7C90EA0E5F",
+},
+#endif
+#ifdef ECC521
+{
+        66,
+        "ECC-521",
+        "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
+        "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC",
+        "51953EB9618E1C9A1F929A21A0B68540EEA2DA725B99B315F3B8B489918EF109E156193951EC7E937B1652C0BD3BB1BF073573DF883D2C34F1EF451FD46B503F00",
+        "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA51868783BF2F966B7FCC0148F709A5D03BB5C9B8899C47AEBB6FB71E91386409",
+        "C6858E06B70404E9CD9E3ECB662395B4429C648139053FB521F828AF606B4D3DBAA14B5E77EFE75928FE1DC127A2FFA8DE3348B3C1856A429BF97E7E31C2E5BD66",
+        "11839296A789A3BC0045C8A5FB42C7D1BD998F54449579B446817AFBD17273E662C97EE72995EF42640C550B9013FAD0761353C7086A272C24088BE94769FD16650",
+},
+#endif
+{
+   0,
+   NULL, NULL, NULL, NULL, NULL, NULL, NULL
+}
+};
+
+
+ecc_point* ecc_new_point(void);
+void ecc_del_point(ecc_point* p);
+int  ecc_map(ecc_point*, mp_int*, mp_digit*);
+int  ecc_projective_add_point(ecc_point* P, ecc_point* Q, ecc_point* R,
+                              mp_int* modulus, mp_digit* mp);
+int  ecc_projective_dbl_point(ecc_point* P, ecc_point* R, mp_int* modulus,
+                              mp_digit* mp);
+static int ecc_mulmod(mp_int* k, ecc_point *G, ecc_point *R, mp_int* modulus,
+                      int map);
+static int ecc_check_pubkey_order(ecc_key* key, mp_int* prime, mp_int* order);
+#ifdef ECC_SHAMIR
+static int ecc_mul2add(ecc_point* A, mp_int* kA, ecc_point* B, mp_int* kB,
+                       ecc_point* C, mp_int* modulus);
+#endif
+
+int mp_jacobi(mp_int* a, mp_int* p, int* c);
+int mp_sqrtmod_prime(mp_int* n, mp_int* prime, mp_int* ret);
+int mp_submod(mp_int* a, mp_int* b, mp_int* c, mp_int* d);
+
+#ifdef HAVE_COMP_KEY
+static int wc_ecc_export_x963_compressed(ecc_key*, byte* out, word32* outLen);
+#endif
+
+/* helper for either lib */
+static int get_digit_count(mp_int* a)
+{
+    if (a == NULL)
+        return 0;
+
+    return a->used;
+}
+
+/* helper for either lib */
+static mp_digit get_digit(mp_int* a, int n)
+{
+    if (a == NULL)
+        return 0;
+
+    return (n >= a->used || n < 0) ? 0 : a->dp[n];
+}
+
+
+#if defined(USE_FAST_MATH)
+
+/* fast math accelerated version, but not for fp ecc yet */
+
+/**
+   Add two ECC points
+   P        The point to add
+   Q        The point to add
+   R        [out] The destination of the double
+   modulus  The modulus of the field the ECC curve is in
+   mp       The "b" value from montgomery_setup()
+   return   MP_OKAY on success
+*/
+int ecc_projective_add_point(ecc_point *P, ecc_point *Q, ecc_point *R,
+                             mp_int* modulus, mp_digit* mp)
+{
+   fp_int t1, t2, x, y, z;
+   int    err;
+
+   if (P == NULL || Q == NULL || R == NULL || modulus == NULL || mp == NULL)
+       return ECC_BAD_ARG_E;
+
+   if ((err = mp_init_multi(&t1, &t2, &x, &y, &z, NULL)) != MP_OKAY) {
+      return err;
+   }
+
+   /* should we dbl instead? */
+   fp_sub(modulus, Q->y, &t1);
+   if ( (fp_cmp(P->x, Q->x) == FP_EQ) && 
+        (get_digit_count(Q->z) && fp_cmp(P->z, Q->z) == FP_EQ) &&
+        (fp_cmp(P->y, Q->y) == FP_EQ || fp_cmp(P->y, &t1) == FP_EQ)) {
+        return ecc_projective_dbl_point(P, R, modulus, mp);
+   }
+
+   fp_copy(P->x, &x);
+   fp_copy(P->y, &y);
+   fp_copy(P->z, &z);
+
+   /* if Z is one then these are no-operations */
+   if (get_digit_count(Q->z)) {
+      /* T1 = Z' * Z' */
+      fp_sqr(Q->z, &t1);
+      fp_montgomery_reduce(&t1, modulus, *mp);
+      /* X = X * T1 */
+      fp_mul(&t1, &x, &x);
+      fp_montgomery_reduce(&x, modulus, *mp);
+      /* T1 = Z' * T1 */
+      fp_mul(Q->z, &t1, &t1);
+      fp_montgomery_reduce(&t1, modulus, *mp);
+      /* Y = Y * T1 */
+      fp_mul(&t1, &y, &y);
+      fp_montgomery_reduce(&y, modulus, *mp);
+   }
+
+   /* T1 = Z*Z */
+   fp_sqr(&z, &t1);
+   fp_montgomery_reduce(&t1, modulus, *mp);
+   /* T2 = X' * T1 */
+   fp_mul(Q->x, &t1, &t2);
+   fp_montgomery_reduce(&t2, modulus, *mp);
+   /* T1 = Z * T1 */
+   fp_mul(&z, &t1, &t1);
+   fp_montgomery_reduce(&t1, modulus, *mp);
+   /* T1 = Y' * T1 */
+   fp_mul(Q->y, &t1, &t1);
+   fp_montgomery_reduce(&t1, modulus, *mp);
+
+   /* Y = Y - T1 */
+   fp_sub(&y, &t1, &y);
+   if (fp_cmp_d(&y, 0) == FP_LT) {
+      fp_add(&y, modulus, &y);
+   }
+   /* T1 = 2T1 */
+   fp_add(&t1, &t1, &t1);
+   if (fp_cmp(&t1, modulus) != FP_LT) {
+      fp_sub(&t1, modulus, &t1);
+   }
+   /* T1 = Y + T1 */
+   fp_add(&t1, &y, &t1);
+   if (fp_cmp(&t1, modulus) != FP_LT) {
+      fp_sub(&t1, modulus, &t1);
+   }
+   /* X = X - T2 */
+   fp_sub(&x, &t2, &x);
+   if (fp_cmp_d(&x, 0) == FP_LT) {
+      fp_add(&x, modulus, &x);
+   }
+   /* T2 = 2T2 */
+   fp_add(&t2, &t2, &t2);
+   if (fp_cmp(&t2, modulus) != FP_LT) {
+      fp_sub(&t2, modulus, &t2);
+   }
+   /* T2 = X + T2 */
+   fp_add(&t2, &x, &t2);
+   if (fp_cmp(&t2, modulus) != FP_LT) {
+      fp_sub(&t2, modulus, &t2);
+   }
+
+   /* if Z' != 1 */
+   if (get_digit_count(Q->z)) {
+      /* Z = Z * Z' */
+      fp_mul(&z, Q->z, &z);
+      fp_montgomery_reduce(&z, modulus, *mp);
+   }
+
+   /* Z = Z * X */
+   fp_mul(&z, &x, &z);
+   fp_montgomery_reduce(&z, modulus, *mp);
+
+   /* T1 = T1 * X  */
+   fp_mul(&t1, &x, &t1);
+   fp_montgomery_reduce(&t1, modulus, *mp);
+   /* X = X * X */
+   fp_sqr(&x, &x);
+   fp_montgomery_reduce(&x, modulus, *mp);
+   /* T2 = T2 * x */
+   fp_mul(&t2, &x, &t2);
+   fp_montgomery_reduce(&t2, modulus, *mp);
+   /* T1 = T1 * X  */
+   fp_mul(&t1, &x, &t1);
+   fp_montgomery_reduce(&t1, modulus, *mp);
+ 
+   /* X = Y*Y */
+   fp_sqr(&y, &x);
+   fp_montgomery_reduce(&x, modulus, *mp);
+   /* X = X - T2 */
+   fp_sub(&x, &t2, &x);
+   if (fp_cmp_d(&x, 0) == FP_LT) {
+      fp_add(&x, modulus, &x);
+   }
+
+   /* T2 = T2 - X */
+   fp_sub(&t2, &x, &t2);
+   if (fp_cmp_d(&t2, 0) == FP_LT) {
+      fp_add(&t2, modulus, &t2);
+   } 
+   /* T2 = T2 - X */
+   fp_sub(&t2, &x, &t2);
+   if (fp_cmp_d(&t2, 0) == FP_LT) {
+      fp_add(&t2, modulus, &t2);
+   }
+   /* T2 = T2 * Y */
+   fp_mul(&t2, &y, &t2);
+   fp_montgomery_reduce(&t2, modulus, *mp);
+   /* Y = T2 - T1 */
+   fp_sub(&t2, &t1, &y);
+   if (fp_cmp_d(&y, 0) == FP_LT) {
+      fp_add(&y, modulus, &y);
+   }
+   /* Y = Y/2 */
+   if (fp_isodd(&y)) {
+      fp_add(&y, modulus, &y);
+   }
+   fp_div_2(&y, &y);
+
+   fp_copy(&x, R->x);
+   fp_copy(&y, R->y);
+   fp_copy(&z, R->z);
+   
+   return MP_OKAY;
+}
+
+
+/**
+   Double an ECC point
+   P   The point to double
+   R   [out] The destination of the double
+   modulus  The modulus of the field the ECC curve is in
+   mp       The "b" value from montgomery_setup()
+   return   MP_OKAY on success
+*/
+int ecc_projective_dbl_point(ecc_point *P, ecc_point *R, mp_int* modulus,
+                             mp_digit* mp)
+{
+   fp_int   t1, t2;
+   int      err;
+
+   if (P == NULL || R == NULL || modulus == NULL || mp == NULL)
+       return ECC_BAD_ARG_E;
+
+   if (P != R) {
+      fp_copy(P->x, R->x);
+      fp_copy(P->y, R->y);
+      fp_copy(P->z, R->z);
+   }
+
+   if ((err = mp_init_multi(&t1, &t2, NULL, NULL, NULL, NULL)) != MP_OKAY) {
+      return err;
+   }
+
+   /* t1 = Z * Z */
+   fp_sqr(R->z, &t1);
+   fp_montgomery_reduce(&t1, modulus, *mp);
+   /* Z = Y * Z */
+   fp_mul(R->z, R->y, R->z);
+   fp_montgomery_reduce(R->z, modulus, *mp);
+   /* Z = 2Z */
+   fp_add(R->z, R->z, R->z);
+   if (fp_cmp(R->z, modulus) != FP_LT) {
+      fp_sub(R->z, modulus, R->z);
+   }
+   
+   /* &t2 = X - T1 */
+   fp_sub(R->x, &t1, &t2);
+   if (fp_cmp_d(&t2, 0) == FP_LT) {
+      fp_add(&t2, modulus, &t2);
+   }
+   /* T1 = X + T1 */
+   fp_add(&t1, R->x, &t1);
+   if (fp_cmp(&t1, modulus) != FP_LT) {
+      fp_sub(&t1, modulus, &t1);
+   }
+   /* T2 = T1 * T2 */
+   fp_mul(&t1, &t2, &t2);
+   fp_montgomery_reduce(&t2, modulus, *mp);
+   /* T1 = 2T2 */
+   fp_add(&t2, &t2, &t1);
+   if (fp_cmp(&t1, modulus) != FP_LT) {
+      fp_sub(&t1, modulus, &t1);
+   }
+   /* T1 = T1 + T2 */
+   fp_add(&t1, &t2, &t1);
+   if (fp_cmp(&t1, modulus) != FP_LT) {
+      fp_sub(&t1, modulus, &t1);
+   }
+
+   /* Y = 2Y */
+   fp_add(R->y, R->y, R->y);
+   if (fp_cmp(R->y, modulus) != FP_LT) {
+      fp_sub(R->y, modulus, R->y);
+   }
+   /* Y = Y * Y */
+   fp_sqr(R->y, R->y);
+   fp_montgomery_reduce(R->y, modulus, *mp);
+   /* T2 = Y * Y */
+   fp_sqr(R->y, &t2);
+   fp_montgomery_reduce(&t2, modulus, *mp);
+   /* T2 = T2/2 */
+   if (fp_isodd(&t2)) {
+      fp_add(&t2, modulus, &t2);
+   }
+   fp_div_2(&t2, &t2);
+   /* Y = Y * X */
+   fp_mul(R->y, R->x, R->y);
+   fp_montgomery_reduce(R->y, modulus, *mp);
+
+   /* X  = T1 * T1 */
+   fp_sqr(&t1, R->x);
+   fp_montgomery_reduce(R->x, modulus, *mp);
+   /* X = X - Y */
+   fp_sub(R->x, R->y, R->x);
+   if (fp_cmp_d(R->x, 0) == FP_LT) {
+      fp_add(R->x, modulus, R->x);
+   }
+   /* X = X - Y */
+   fp_sub(R->x, R->y, R->x);
+   if (fp_cmp_d(R->x, 0) == FP_LT) {
+      fp_add(R->x, modulus, R->x);
+   }
+
+   /* Y = Y - X */     
+   fp_sub(R->y, R->x, R->y);
+   if (fp_cmp_d(R->y, 0) == FP_LT) {
+      fp_add(R->y, modulus, R->y);
+   }
+   /* Y = Y * T1 */
+   fp_mul(R->y, &t1, R->y);
+   fp_montgomery_reduce(R->y, modulus, *mp);
+   /* Y = Y - T2 */
+   fp_sub(R->y, &t2, R->y);
+   if (fp_cmp_d(R->y, 0) == FP_LT) {
+      fp_add(R->y, modulus, R->y);
+   }
+ 
+   return MP_OKAY;
+}
+
+#else /* USE_FAST_MATH */
+
+/**
+   Add two ECC points
+   P        The point to add
+   Q        The point to add
+   R        [out] The destination of the double
+   modulus  The modulus of the field the ECC curve is in
+   mp       The "b" value from montgomery_setup()
+   return   MP_OKAY on success
+*/
+int ecc_projective_add_point(ecc_point* P, ecc_point* Q, ecc_point* R,
+                             mp_int* modulus, mp_digit* mp)
+{
+   mp_int t1;
+   mp_int t2;
+   mp_int x;
+   mp_int y;
+   mp_int z;
+   int    err;
+
+   if (P == NULL || Q == NULL || R == NULL || modulus == NULL || mp == NULL)
+       return ECC_BAD_ARG_E;
+
+   if ((err = mp_init_multi(&t1, &t2, &x, &y, &z, NULL)) != MP_OKAY) {
+      return err;
+   }
+   
+   /* should we dbl instead? */
+   err = mp_sub(modulus, Q->y, &t1);
+
+   if (err == MP_OKAY) {
+       if ( (mp_cmp(P->x, Q->x) == MP_EQ) && 
+            (get_digit_count(Q->z) && mp_cmp(P->z, Q->z) == MP_EQ) &&
+            (mp_cmp(P->y, Q->y) == MP_EQ || mp_cmp(P->y, &t1) == MP_EQ)) {
+                mp_clear(&t1);
+                mp_clear(&t2);
+                mp_clear(&x);
+                mp_clear(&y);
+                mp_clear(&z);
+
+                return ecc_projective_dbl_point(P, R, modulus, mp);
+       }
+   }
+
+   if (err == MP_OKAY)
+       err = mp_copy(P->x, &x);
+   if (err == MP_OKAY)
+       err = mp_copy(P->y, &y);
+   if (err == MP_OKAY)
+       err = mp_copy(P->z, &z);
+
+   /* if Z is one then these are no-operations */
+   if (err == MP_OKAY) {
+       if (get_digit_count(Q->z)) {
+           /* T1 = Z' * Z' */
+           err = mp_sqr(Q->z, &t1);
+           if (err == MP_OKAY)
+               err = mp_montgomery_reduce(&t1, modulus, *mp);
+
+           /* X = X * T1 */
+           if (err == MP_OKAY)
+               err = mp_mul(&t1, &x, &x);
+           if (err == MP_OKAY)
+               err = mp_montgomery_reduce(&x, modulus, *mp);
+
+           /* T1 = Z' * T1 */
+           if (err == MP_OKAY)
+               err = mp_mul(Q->z, &t1, &t1);
+           if (err == MP_OKAY)
+               err = mp_montgomery_reduce(&t1, modulus, *mp);
+
+           /* Y = Y * T1 */
+           if (err == MP_OKAY)
+               err = mp_mul(&t1, &y, &y);
+           if (err == MP_OKAY)
+               err = mp_montgomery_reduce(&y, modulus, *mp);
+       }
+   }
+
+   /* T1 = Z*Z */
+   if (err == MP_OKAY)
+       err = mp_sqr(&z, &t1);
+   if (err == MP_OKAY)
+       err = mp_montgomery_reduce(&t1, modulus, *mp);
+
+   /* T2 = X' * T1 */
+   if (err == MP_OKAY)
+       err = mp_mul(Q->x, &t1, &t2);
+   if (err == MP_OKAY)
+       err = mp_montgomery_reduce(&t2, modulus, *mp);
+
+   /* T1 = Z * T1 */
+   if (err == MP_OKAY)
+       err = mp_mul(&z, &t1, &t1);
+   if (err == MP_OKAY)
+       err = mp_montgomery_reduce(&t1, modulus, *mp);
+
+   /* T1 = Y' * T1 */
+   if (err == MP_OKAY)
+       err = mp_mul(Q->y, &t1, &t1);
+   if (err == MP_OKAY)
+       err = mp_montgomery_reduce(&t1, modulus, *mp);
+
+   /* Y = Y - T1 */
+   if (err == MP_OKAY)
+       err = mp_sub(&y, &t1, &y);
+   if (err == MP_OKAY) {
+       if (mp_cmp_d(&y, 0) == MP_LT)
+           err = mp_add(&y, modulus, &y);
+   }
+   /* T1 = 2T1 */
+   if (err == MP_OKAY)
+       err = mp_add(&t1, &t1, &t1);
+   if (err == MP_OKAY) {
+       if (mp_cmp(&t1, modulus) != MP_LT)
+           err = mp_sub(&t1, modulus, &t1);
+   }
+   /* T1 = Y + T1 */
+   if (err == MP_OKAY)
+       err = mp_add(&t1, &y, &t1);
+   if (err == MP_OKAY) {
+       if (mp_cmp(&t1, modulus) != MP_LT)
+           err = mp_sub(&t1, modulus, &t1);
+   }
+   /* X = X - T2 */
+   if (err == MP_OKAY)
+       err = mp_sub(&x, &t2, &x);
+   if (err == MP_OKAY) {
+       if (mp_cmp_d(&x, 0) == MP_LT)
+           err = mp_add(&x, modulus, &x);
+   }
+   /* T2 = 2T2 */
+   if (err == MP_OKAY)
+       err = mp_add(&t2, &t2, &t2);
+   if (err == MP_OKAY) {
+       if (mp_cmp(&t2, modulus) != MP_LT)
+           err = mp_sub(&t2, modulus, &t2);
+   }
+   /* T2 = X + T2 */
+   if (err == MP_OKAY)
+       err = mp_add(&t2, &x, &t2);
+   if (err == MP_OKAY) {
+       if (mp_cmp(&t2, modulus) != MP_LT)
+           err = mp_sub(&t2, modulus, &t2);
+   }
+
+   if (err == MP_OKAY) {
+       if (get_digit_count(Q->z)) {
+           /* Z = Z * Z' */
+           err = mp_mul(&z, Q->z, &z);
+           if (err == MP_OKAY)
+               err = mp_montgomery_reduce(&z, modulus, *mp);
+       }
+   }
+
+   /* Z = Z * X */
+   if (err == MP_OKAY)
+       err = mp_mul(&z, &x, &z);
+   if (err == MP_OKAY)
+       err = mp_montgomery_reduce(&z, modulus, *mp);
+
+   /* T1 = T1 * X  */
+   if (err == MP_OKAY)
+       err = mp_mul(&t1, &x, &t1);
+   if (err == MP_OKAY)
+       err = mp_montgomery_reduce(&t1, modulus, *mp);
+
+   /* X = X * X */
+   if (err == MP_OKAY)
+       err = mp_sqr(&x, &x);
+   if (err == MP_OKAY)
+       err = mp_montgomery_reduce(&x, modulus, *mp);
+   
+   /* T2 = T2 * x */
+   if (err == MP_OKAY)
+       err = mp_mul(&t2, &x, &t2);
+   if (err == MP_OKAY)
+       err = mp_montgomery_reduce(&t2, modulus, *mp);
+
+   /* T1 = T1 * X  */
+   if (err == MP_OKAY)
+       err = mp_mul(&t1, &x, &t1);
+   if (err == MP_OKAY)
+       err = mp_montgomery_reduce(&t1, modulus, *mp);
+ 
+   /* X = Y*Y */
+   if (err == MP_OKAY)
+       err = mp_sqr(&y, &x);
+   if (err == MP_OKAY)
+       err = mp_montgomery_reduce(&x, modulus, *mp);
+
+   /* X = X - T2 */
+   if (err == MP_OKAY)
+       err = mp_sub(&x, &t2, &x);
+   if (err == MP_OKAY) {
+       if (mp_cmp_d(&x, 0) == MP_LT)
+           err = mp_add(&x, modulus, &x);
+   }
+   /* T2 = T2 - X */
+   if (err == MP_OKAY)
+       err = mp_sub(&t2, &x, &t2);
+   if (err == MP_OKAY) {
+       if (mp_cmp_d(&t2, 0) == MP_LT)
+           err = mp_add(&t2, modulus, &t2);
+   } 
+   /* T2 = T2 - X */
+   if (err == MP_OKAY)
+       err = mp_sub(&t2, &x, &t2);
+   if (err == MP_OKAY) {
+       if (mp_cmp_d(&t2, 0) == MP_LT)
+           err = mp_add(&t2, modulus, &t2);
+   }
+   /* T2 = T2 * Y */
+   if (err == MP_OKAY)
+       err = mp_mul(&t2, &y, &t2);
+   if (err == MP_OKAY)
+       err = mp_montgomery_reduce(&t2, modulus, *mp);
+
+   /* Y = T2 - T1 */
+   if (err == MP_OKAY)
+       err = mp_sub(&t2, &t1, &y);
+   if (err == MP_OKAY) {
+       if (mp_cmp_d(&y, 0) == MP_LT)
+           err = mp_add(&y, modulus, &y);
+   }
+   /* Y = Y/2 */
+   if (err == MP_OKAY) {
+       if (mp_isodd(&y))
+           err = mp_add(&y, modulus, &y);
+   }
+   if (err == MP_OKAY)
+       err = mp_div_2(&y, &y);
+
+   if (err == MP_OKAY)
+       err = mp_copy(&x, R->x);
+   if (err == MP_OKAY)
+       err = mp_copy(&y, R->y);
+   if (err == MP_OKAY)
+       err = mp_copy(&z, R->z);
+
+   /* clean up */
+   mp_clear(&t1);
+   mp_clear(&t2);
+   mp_clear(&x);
+   mp_clear(&y);
+   mp_clear(&z);
+
+   return err;
+}
+
+
+/**
+   Double an ECC point
+   P   The point to double
+   R   [out] The destination of the double
+   modulus  The modulus of the field the ECC curve is in
+   mp       The "b" value from montgomery_setup()
+   return   MP_OKAY on success
+*/
+int ecc_projective_dbl_point(ecc_point *P, ecc_point *R, mp_int* modulus,
+                             mp_digit* mp)
+{
+   mp_int t1;
+   mp_int t2;
+   int    err;
+
+   if (P == NULL || R == NULL || modulus == NULL || mp == NULL)
+       return ECC_BAD_ARG_E;
+
+   if ((err = mp_init_multi(&t1, &t2, NULL, NULL, NULL, NULL)) != MP_OKAY) {
+      return err;
+   }
+
+   if (P != R) {
+      err = mp_copy(P->x, R->x);
+      if (err == MP_OKAY)
+          err = mp_copy(P->y, R->y);
+      if (err == MP_OKAY)
+          err = mp_copy(P->z, R->z);
+   }
+
+   /* t1 = Z * Z */
+   if (err == MP_OKAY)
+       err = mp_sqr(R->z, &t1);
+   if (err == MP_OKAY)
+       err = mp_montgomery_reduce(&t1, modulus, *mp);
+
+   /* Z = Y * Z */
+   if (err == MP_OKAY)
+       err = mp_mul(R->z, R->y, R->z);
+   if (err == MP_OKAY)
+       err = mp_montgomery_reduce(R->z, modulus, *mp);
+
+   /* Z = 2Z */
+   if (err == MP_OKAY)
+       err = mp_add(R->z, R->z, R->z);
+   if (err == MP_OKAY) {
+       if (mp_cmp(R->z, modulus) != MP_LT)
+           err = mp_sub(R->z, modulus, R->z);
+   }
+
+   /* T2 = X - T1 */
+   if (err == MP_OKAY)
+       err = mp_sub(R->x, &t1, &t2);
+   if (err == MP_OKAY) {
+       if (mp_cmp_d(&t2, 0) == MP_LT)
+           err = mp_add(&t2, modulus, &t2);
+   }
+   /* T1 = X + T1 */
+   if (err == MP_OKAY)
+       err = mp_add(&t1, R->x, &t1);
+   if (err == MP_OKAY) {
+       if (mp_cmp(&t1, modulus) != MP_LT)
+           err = mp_sub(&t1, modulus, &t1);
+   }
+   /* T2 = T1 * T2 */
+   if (err == MP_OKAY)
+       err = mp_mul(&t1, &t2, &t2);
+   if (err == MP_OKAY)
+       err = mp_montgomery_reduce(&t2, modulus, *mp);
+
+   /* T1 = 2T2 */
+   if (err == MP_OKAY)
+       err = mp_add(&t2, &t2, &t1);
+   if (err == MP_OKAY) {
+       if (mp_cmp(&t1, modulus) != MP_LT)
+           err = mp_sub(&t1, modulus, &t1);
+   }
+   /* T1 = T1 + T2 */
+   if (err == MP_OKAY)
+       err = mp_add(&t1, &t2, &t1);
+   if (err == MP_OKAY) {
+       if (mp_cmp(&t1, modulus) != MP_LT)
+           err = mp_sub(&t1, modulus, &t1);
+   }
+   /* Y = 2Y */
+   if (err == MP_OKAY)
+       err = mp_add(R->y, R->y, R->y);
+   if (err == MP_OKAY) {
+       if (mp_cmp(R->y, modulus) != MP_LT)
+           err = mp_sub(R->y, modulus, R->y);
+   }
+   /* Y = Y * Y */
+   if (err == MP_OKAY)
+       err = mp_sqr(R->y, R->y);
+   if (err == MP_OKAY)
+       err = mp_montgomery_reduce(R->y, modulus, *mp);
+   
+   /* T2 = Y * Y */
+   if (err == MP_OKAY)
+       err = mp_sqr(R->y, &t2);
+   if (err == MP_OKAY)
+       err = mp_montgomery_reduce(&t2, modulus, *mp);
+
+   /* T2 = T2/2 */
+   if (err == MP_OKAY) {
+       if (mp_isodd(&t2))
+           err = mp_add(&t2, modulus, &t2);
+   }
+   if (err == MP_OKAY)
+       err = mp_div_2(&t2, &t2);
+   
+   /* Y = Y * X */
+   if (err == MP_OKAY)
+       err = mp_mul(R->y, R->x, R->y);
+   if (err == MP_OKAY)
+       err = mp_montgomery_reduce(R->y, modulus, *mp);
+
+   /* X  = T1 * T1 */
+   if (err == MP_OKAY)
+       err = mp_sqr(&t1, R->x);
+   if (err == MP_OKAY)
+       err = mp_montgomery_reduce(R->x, modulus, *mp);
+
+   /* X = X - Y */
+   if (err == MP_OKAY)
+       err = mp_sub(R->x, R->y, R->x);
+   if (err == MP_OKAY) {
+       if (mp_cmp_d(R->x, 0) == MP_LT)
+           err = mp_add(R->x, modulus, R->x);
+   }
+   /* X = X - Y */
+   if (err == MP_OKAY)
+       err = mp_sub(R->x, R->y, R->x);
+   if (err == MP_OKAY) {
+       if (mp_cmp_d(R->x, 0) == MP_LT)
+           err = mp_add(R->x, modulus, R->x);
+   }
+   /* Y = Y - X */     
+   if (err == MP_OKAY)
+       err = mp_sub(R->y, R->x, R->y);
+   if (err == MP_OKAY) {
+       if (mp_cmp_d(R->y, 0) == MP_LT)
+           err = mp_add(R->y, modulus, R->y);
+   }
+   /* Y = Y * T1 */
+   if (err == MP_OKAY)
+       err = mp_mul(R->y, &t1, R->y);
+   if (err == MP_OKAY)
+       err = mp_montgomery_reduce(R->y, modulus, *mp);
+
+   /* Y = Y - T2 */
+   if (err == MP_OKAY)
+       err = mp_sub(R->y, &t2, R->y);
+   if (err == MP_OKAY) {
+       if (mp_cmp_d(R->y, 0) == MP_LT)
+           err = mp_add(R->y, modulus, R->y);
+   }
+
+   /* clean up */ 
+   mp_clear(&t1);
+   mp_clear(&t2);
+
+   return err;
+}
+
+#endif /* USE_FAST_MATH */
+
+/**
+  Map a projective jacbobian point back to affine space
+  P        [in/out] The point to map
+  modulus  The modulus of the field the ECC curve is in
+  mp       The "b" value from montgomery_setup()
+  return   MP_OKAY on success
+*/
+int ecc_map(ecc_point* P, mp_int* modulus, mp_digit* mp)
+{
+   mp_int t1;
+   mp_int t2;
+   int    err;
+
+   if (P == NULL || mp == NULL || modulus == NULL)
+       return ECC_BAD_ARG_E;
+
+   /* special case for point at infinity */
+   if (mp_cmp_d(P->z, 0) == MP_EQ) {
+       mp_set(P->x, 0);
+       mp_set(P->y, 0);
+       mp_set(P->z, 1);
+       return MP_OKAY;
+   }
+
+   if ((err = mp_init_multi(&t1, &t2, NULL, NULL, NULL, NULL)) != MP_OKAY) {
+      return MEMORY_E;
+   }
+
+   /* first map z back to normal */
+   err = mp_montgomery_reduce(P->z, modulus, *mp);
+
+   /* get 1/z */
+   if (err == MP_OKAY)
+       err = mp_invmod(P->z, modulus, &t1);
+ 
+   /* get 1/z^2 and 1/z^3 */
+   if (err == MP_OKAY)
+       err = mp_sqr(&t1, &t2);
+   if (err == MP_OKAY)
+       err = mp_mod(&t2, modulus, &t2);
+   if (err == MP_OKAY)
+       err = mp_mul(&t1, &t2, &t1);
+   if (err == MP_OKAY)
+       err = mp_mod(&t1, modulus, &t1);
+
+   /* multiply against x/y */
+   if (err == MP_OKAY)
+       err = mp_mul(P->x, &t2, P->x);
+   if (err == MP_OKAY)
+       err = mp_montgomery_reduce(P->x, modulus, *mp);
+   if (err == MP_OKAY)
+       err = mp_mul(P->y, &t1, P->y);
+   if (err == MP_OKAY)
+       err = mp_montgomery_reduce(P->y, modulus, *mp);
+   
+   if (err == MP_OKAY)
+       mp_set(P->z, 1);
+
+   /* clean up */
+   mp_clear(&t1);
+   mp_clear(&t2);
+
+   return err;
+}
+
+
+#ifndef ECC_TIMING_RESISTANT
+
+/* size of sliding window, don't change this! */
+#define WINSIZE 4
+
+/**
+   Perform a point multiplication 
+   k    The scalar to multiply by
+   G    The base point
+   R    [out] Destination for kG
+   modulus  The modulus of the field the ECC curve is in
+   map      Boolean whether to map back to affine or not
+                (1==map, 0 == leave in projective)
+   return MP_OKAY on success
+*/
+#ifdef FP_ECC
+static int normal_ecc_mulmod(mp_int* k, ecc_point *G, ecc_point *R,
+                             mp_int* modulus, int map)
+#else
+static int ecc_mulmod(mp_int* k, ecc_point *G, ecc_point *R, mp_int* modulus,
+                      int map)
+#endif
+{
+   ecc_point *tG, *M[8];
+   int           i, j, err;
+   mp_int        mu;
+   mp_digit      mp;
+   mp_digit      buf;
+   int           first = 1, bitbuf = 0, bitcpy = 0, bitcnt = 0, mode = 0,
+                 digidx = 0;
+
+   if (k == NULL || G == NULL || R == NULL || modulus == NULL)
+       return ECC_BAD_ARG_E;
+
+   /* init montgomery reduction */
+   if ((err = mp_montgomery_setup(modulus, &mp)) != MP_OKAY) {
+      return err;
+   }
+   if ((err = mp_init(&mu)) != MP_OKAY) {
+      return err;
+   }
+   if ((err = mp_montgomery_calc_normalization(&mu, modulus)) != MP_OKAY) {
+      mp_clear(&mu);
+      return err;
+   }
+  
+  /* alloc ram for window temps */
+  for (i = 0; i < 8; i++) {
+      M[i] = ecc_new_point();
+      if (M[i] == NULL) {
+         for (j = 0; j < i; j++) {
+             ecc_del_point(M[j]);
+         }
+         mp_clear(&mu);
+         return MEMORY_E;
+      }
+  }
+
+   /* make a copy of G incase R==G */
+   tG = ecc_new_point();
+   if (tG == NULL)
+       err = MEMORY_E;
+
+   /* tG = G  and convert to montgomery */
+   if (err == MP_OKAY) {
+       if (mp_cmp_d(&mu, 1) == MP_EQ) {
+           err = mp_copy(G->x, tG->x);
+           if (err == MP_OKAY)
+               err = mp_copy(G->y, tG->y);
+           if (err == MP_OKAY)
+               err = mp_copy(G->z, tG->z);
+       } else {
+           err = mp_mulmod(G->x, &mu, modulus, tG->x);
+           if (err == MP_OKAY)
+               err = mp_mulmod(G->y, &mu, modulus, tG->y);
+           if (err == MP_OKAY)
+               err = mp_mulmod(G->z, &mu, modulus, tG->z);
+       }
+   }
+   mp_clear(&mu);
+   
+   /* calc the M tab, which holds kG for k==8..15 */
+   /* M[0] == 8G */
+   if (err == MP_OKAY)
+       err = ecc_projective_dbl_point(tG, M[0], modulus, &mp);
+   if (err == MP_OKAY)
+       err = ecc_projective_dbl_point(M[0], M[0], modulus, &mp);
+   if (err == MP_OKAY)
+       err = ecc_projective_dbl_point(M[0], M[0], modulus, &mp);
+
+   /* now find (8+k)G for k=1..7 */
+   if (err == MP_OKAY)
+       for (j = 9; j < 16; j++) {
+           err = ecc_projective_add_point(M[j-9], tG, M[j-8], modulus, &mp);
+           if (err != MP_OKAY) break;
+       }
+
+   /* setup sliding window */
+   if (err == MP_OKAY) {
+       mode   = 0;
+       bitcnt = 1;
+       buf    = 0;
+       digidx = get_digit_count(k) - 1;
+       bitcpy = bitbuf = 0;
+       first  = 1;
+
+       /* perform ops */
+       for (;;) {
+           /* grab next digit as required */
+           if (--bitcnt == 0) {
+               if (digidx == -1) {
+                   break;
+               }
+               buf    = get_digit(k, digidx);
+               bitcnt = (int) DIGIT_BIT; 
+               --digidx;
+           }
+
+           /* grab the next msb from the ltiplicand */
+           i = (int)(buf >> (DIGIT_BIT - 1)) & 1;
+           buf <<= 1;
+
+           /* skip leading zero bits */
+           if (mode == 0 && i == 0)
+               continue;
+
+           /* if the bit is zero and mode == 1 then we double */
+           if (mode == 1 && i == 0) {
+               err = ecc_projective_dbl_point(R, R, modulus, &mp);
+               if (err != MP_OKAY) break;
+               continue;
+           }
+
+           /* else we add it to the window */
+           bitbuf |= (i << (WINSIZE - ++bitcpy));
+           mode = 2;
+
+           if (bitcpy == WINSIZE) {
+               /* if this is the first window we do a simple copy */
+               if (first == 1) {
+                   /* R = kG [k = first window] */
+                   err = mp_copy(M[bitbuf-8]->x, R->x);
+                   if (err != MP_OKAY) break;
+
+                   err = mp_copy(M[bitbuf-8]->y, R->y);
+                   if (err != MP_OKAY) break;
+
+                   err = mp_copy(M[bitbuf-8]->z, R->z);
+                   first = 0;
+               } else {
+                   /* normal window */
+                   /* ok window is filled so double as required and add  */
+                   /* double first */
+                   for (j = 0; j < WINSIZE; j++) {
+                       err = ecc_projective_dbl_point(R, R, modulus, &mp);
+                       if (err != MP_OKAY) break;
+                   }
+                   if (err != MP_OKAY) break;  /* out of first for(;;) */
+
+                   /* then add, bitbuf will be 8..15 [8..2^WINSIZE] guaranted */
+                   err = ecc_projective_add_point(R,M[bitbuf-8],R,modulus,&mp);
+               }
+               if (err != MP_OKAY) break;
+               /* empty window and reset */
+               bitcpy = bitbuf = 0;
+               mode = 1;
+           }
+       }
+   }
+
+   /* if bits remain then double/add */
+   if (err == MP_OKAY) {
+       if (mode == 2 && bitcpy > 0) {
+           /* double then add */
+           for (j = 0; j < bitcpy; j++) {
+               /* only double if we have had at least one add first */
+               if (first == 0) {
+                   err = ecc_projective_dbl_point(R, R, modulus, &mp);
+                   if (err != MP_OKAY) break;
+               }
+
+               bitbuf <<= 1;
+               if ((bitbuf & (1 << WINSIZE)) != 0) {
+                   if (first == 1) {
+                       /* first add, so copy */
+                       err = mp_copy(tG->x, R->x);
+                       if (err != MP_OKAY) break;
+
+                       err = mp_copy(tG->y, R->y);
+                       if (err != MP_OKAY) break;
+
+                       err = mp_copy(tG->z, R->z);
+                       if (err != MP_OKAY) break;
+                       first = 0;
+                   } else {
+                       /* then add */
+                       err = ecc_projective_add_point(R, tG, R, modulus, &mp);
+                       if (err != MP_OKAY) break;
+                   }
+               }
+           }
+       }
+   }
+
+   /* map R back from projective space */
+   if (err == MP_OKAY && map)
+       err = ecc_map(R, modulus, &mp);
+
+   mp_clear(&mu);
+   ecc_del_point(tG);
+   for (i = 0; i < 8; i++) {
+       ecc_del_point(M[i]);
+   }
+   return err;
+}
+
+#undef WINSIZE
+
+#else /* ECC_TIMING_RESISTANT */
+
+/**
+   Perform a point multiplication  (timing resistant)
+   k    The scalar to multiply by
+   G    The base point
+   R    [out] Destination for kG
+   modulus  The modulus of the field the ECC curve is in
+   map      Boolean whether to map back to affine or not
+            (1==map, 0 == leave in projective)
+   return MP_OKAY on success
+*/
+#ifdef FP_ECC
+static int normal_ecc_mulmod(mp_int* k, ecc_point *G, ecc_point *R,
+                             mp_int* modulus, int map)
+#else
+static int ecc_mulmod(mp_int* k, ecc_point *G, ecc_point *R, mp_int* modulus,
+                      int map)
+#endif
+{
+   ecc_point    *tG, *M[3];
+   int           i, j, err;
+   mp_int        mu;
+   mp_digit      mp;
+   mp_digit      buf;
+   int           bitcnt = 0, mode = 0, digidx = 0;
+
+   if (k == NULL || G == NULL || R == NULL || modulus == NULL)
+       return ECC_BAD_ARG_E;
+
+   /* init montgomery reduction */
+   if ((err = mp_montgomery_setup(modulus, &mp)) != MP_OKAY) {
+      return err;
+   }
+   if ((err = mp_init(&mu)) != MP_OKAY) {
+      return err;
+   }
+   if ((err = mp_montgomery_calc_normalization(&mu, modulus)) != MP_OKAY) {
+      mp_clear(&mu);
+      return err;
+   }
+
+  /* alloc ram for window temps */
+  for (i = 0; i < 3; i++) {
+      M[i] = ecc_new_point();
+      if (M[i] == NULL) {
+         for (j = 0; j < i; j++) {
+             ecc_del_point(M[j]);
+         }
+         mp_clear(&mu);
+         return MEMORY_E;
+      }
+  }
+
+   /* make a copy of G incase R==G */
+   tG = ecc_new_point();
+   if (tG == NULL)
+       err = MEMORY_E;
+
+   /* tG = G  and convert to montgomery */
+   if (err == MP_OKAY) {
+       err = mp_mulmod(G->x, &mu, modulus, tG->x);
+       if (err == MP_OKAY)
+           err = mp_mulmod(G->y, &mu, modulus, tG->y);
+       if (err == MP_OKAY)
+           err = mp_mulmod(G->z, &mu, modulus, tG->z);
+   }
+   mp_clear(&mu);
+
+   /* calc the M tab */
+   /* M[0] == G */
+   if (err == MP_OKAY)
+       err = mp_copy(tG->x, M[0]->x);
+   if (err == MP_OKAY)
+       err = mp_copy(tG->y, M[0]->y);
+   if (err == MP_OKAY)
+       err = mp_copy(tG->z, M[0]->z);
+
+   /* M[1] == 2G */
+   if (err == MP_OKAY)
+       err = ecc_projective_dbl_point(tG, M[1], modulus, &mp);
+
+   /* setup sliding window */
+   mode   = 0;
+   bitcnt = 1;
+   buf    = 0;
+   digidx = get_digit_count(k) - 1;
+
+   /* perform ops */
+   if (err == MP_OKAY) {
+       for (;;) {
+           /* grab next digit as required */
+           if (--bitcnt == 0) {
+               if (digidx == -1) {
+                   break;
+               }
+               buf = get_digit(k, digidx);
+               bitcnt = (int) DIGIT_BIT;
+               --digidx;
+           }
+
+           /* grab the next msb from the ltiplicand */
+           i = (buf >> (DIGIT_BIT - 1)) & 1;
+           buf <<= 1;
+
+           if (mode == 0 && i == 0) {
+               /* dummy operations */
+               if (err == MP_OKAY)
+                   err = ecc_projective_add_point(M[0], M[1], M[2], modulus,
+                                                  &mp);
+               if (err == MP_OKAY)
+                   err = ecc_projective_dbl_point(M[1], M[2], modulus, &mp);
+               if (err == MP_OKAY)
+                   continue;
+           }
+
+           if (mode == 0 && i == 1) {
+               mode = 1;
+               /* dummy operations */
+               if (err == MP_OKAY)
+                   err = ecc_projective_add_point(M[0], M[1], M[2], modulus,
+                                                  &mp);
+               if (err == MP_OKAY)
+                   err = ecc_projective_dbl_point(M[1], M[2], modulus, &mp);
+               if (err == MP_OKAY)
+                   continue;
+           }
+
+           if (err == MP_OKAY)
+               err = ecc_projective_add_point(M[0], M[1], M[i^1], modulus, &mp);
+           if (err == MP_OKAY)
+               err = ecc_projective_dbl_point(M[i], M[i], modulus, &mp);
+           if (err != MP_OKAY)
+               break;
+       } /* end for */
+   }
+
+   /* copy result out */
+   if (err == MP_OKAY)
+       err = mp_copy(M[0]->x, R->x);
+   if (err == MP_OKAY)
+       err = mp_copy(M[0]->y, R->y);
+   if (err == MP_OKAY)
+       err = mp_copy(M[0]->z, R->z);
+
+   /* map R back from projective space */
+   if (err == MP_OKAY && map)
+      err = ecc_map(R, modulus, &mp);
+
+   /* done */
+   mp_clear(&mu);
+   ecc_del_point(tG);
+   for (i = 0; i < 3; i++) {
+       ecc_del_point(M[i]);
+   }
+   return err;
+}
+
+#endif /* ECC_TIMING_RESISTANT */
+
+
+#ifdef ALT_ECC_SIZE
+
+static void alt_fp_init(fp_int* a)
+{
+    a->size = FP_SIZE_ECC;
+    fp_zero(a);
+}
+
+#endif /* ALT_ECC_SIZE */
+
+
+/**
+   Allocate a new ECC point
+   return A newly allocated point or NULL on error 
+*/
+ecc_point* ecc_new_point(void)
+{
+   ecc_point* p;
+
+   p = (ecc_point*)XMALLOC(sizeof(ecc_point), 0, DYNAMIC_TYPE_ECC);
+   if (p == NULL) {
+      return NULL;
+   }
+   XMEMSET(p, 0, sizeof(ecc_point));
+
+#ifndef USE_FAST_MATH
+   p->x->dp = NULL;
+   p->y->dp = NULL;
+   p->z->dp = NULL;
+#endif
+
+#ifndef ALT_ECC_SIZE
+   if (mp_init_multi(p->x, p->y, p->z, NULL, NULL, NULL) != MP_OKAY) {
+      XFREE(p, 0, DYNAMIC_TYPE_ECC);
+      return NULL;
+   }
+#else
+   p->x = (mp_int*)&p->xyz[0];
+   p->y = (mp_int*)&p->xyz[1];
+   p->z = (mp_int*)&p->xyz[2];
+   alt_fp_init(p->x);
+   alt_fp_init(p->y);
+   alt_fp_init(p->z);
+#endif
+
+   return p;
+}
+
+/** Free an ECC point from memory
+  p   The point to free
+*/
+void ecc_del_point(ecc_point* p)
+{
+   /* prevents free'ing null arguments */
+   if (p != NULL) {
+      mp_clear(p->x);
+      mp_clear(p->y);
+      mp_clear(p->z);
+      XFREE(p, 0, DYNAMIC_TYPE_ECC);
+   }
+}
+
+
+/** Returns whether an ECC idx is valid or not
+  n      The idx number to check
+  return 1 if valid, 0 if not
+*/  
+static int ecc_is_valid_idx(int n)
+{
+   int x;
+
+   for (x = 0; ecc_sets[x].size != 0; x++)
+       ;
+   /* -1 is a valid index --- indicating that the domain params
+      were supplied by the user */
+   if ((n >= -1) && (n < x)) {
+      return 1;
+   }
+   return 0;
+}
+
+
+/**
+  Create an ECC shared secret between two keys
+  private_key      The private ECC key
+  public_key       The public key
+  out              [out] Destination of the shared secret
+                   Conforms to EC-DH from ANSI X9.63
+  outlen           [in/out] The max size and resulting size of the shared secret
+  return           MP_OKAY if successful
+*/
+int wc_ecc_shared_secret(ecc_key* private_key, ecc_key* public_key, byte* out,
+                      word32* outlen)
+{
+   word32         x = 0;
+   ecc_point*     result;
+   mp_int         prime;
+   int            err;
+
+   if (private_key == NULL || public_key == NULL || out == NULL ||
+                                                    outlen == NULL)
+       return BAD_FUNC_ARG;
+
+   /* type valid? */
+   if (private_key->type != ECC_PRIVATEKEY) {
+      return ECC_BAD_ARG_E;
+   }
+
+   if (ecc_is_valid_idx(private_key->idx) == 0 ||
+       ecc_is_valid_idx(public_key->idx)  == 0)
+      return ECC_BAD_ARG_E;
+
+   if (XSTRNCMP(private_key->dp->name, public_key->dp->name, ECC_MAXNAME) != 0)
+      return ECC_BAD_ARG_E;
+
+   /* make new point */
+   result = ecc_new_point();
+   if (result == NULL) {
+      return MEMORY_E;
+   }
+
+   if ((err = mp_init(&prime)) != MP_OKAY) {
+      ecc_del_point(result);
+      return err;
+   }
+
+   err = mp_read_radix(&prime, (char *)private_key->dp->prime, 16);
+
+   if (err == MP_OKAY)
+       err = ecc_mulmod(&private_key->k, &public_key->pubkey, result, &prime,1);
+
+   if (err == MP_OKAY) {
+       x = mp_unsigned_bin_size(&prime);
+       if (*outlen < x)
+          err = BUFFER_E;
+   }
+
+   if (err == MP_OKAY) {
+       XMEMSET(out, 0, x);
+       err = mp_to_unsigned_bin(result->x,out + (x -
+                                              mp_unsigned_bin_size(result->x)));
+       *outlen = x;
+   }
+
+   mp_clear(&prime);
+   ecc_del_point(result);
+
+   return err;
+}
+
+
+/* return 1 if point is at infinity, 0 if not, < 0 on error */
+static int ecc_point_is_at_infinity(ecc_point* p)
+{
+    if (p == NULL)
+        return BAD_FUNC_ARG;
+
+    if (get_digit_count(p->x) == 0 && get_digit_count(p->y) == 0)
+        return 1;
+
+    return 0;
+}
+
+
+int wc_ecc_make_key_ex(RNG* rng, ecc_key* key, const ecc_set_type* dp);
+
+/**
+  Make a new ECC key 
+  rng          An active RNG state
+  keysize      The keysize for the new key (in octets from 20 to 65 bytes)
+  key          [out] Destination of the newly created key
+  return       MP_OKAY if successful,
+                       upon error all allocated memory will be freed
+*/
+int wc_ecc_make_key(RNG* rng, int keysize, ecc_key* key)
+{
+   int x, err;
+
+   if (key == NULL || rng == NULL)
+       return ECC_BAD_ARG_E;
+
+   /* find key size */
+   for (x = 0; (keysize > ecc_sets[x].size) && (ecc_sets[x].size != 0); x++)
+       ;
+   keysize = ecc_sets[x].size;
+
+   if (keysize > ECC_MAXSIZE || ecc_sets[x].size == 0) {
+      return BAD_FUNC_ARG;
+   }
+   err = wc_ecc_make_key_ex(rng, key, &ecc_sets[x]);
+   key->idx = x;
+
+   return err;
+}
+
+int wc_ecc_make_key_ex(RNG* rng, ecc_key* key, const ecc_set_type* dp)
+{
+   int            err;
+   ecc_point*     base;
+   mp_int         prime;
+   mp_int         order;
+#ifdef WOLFSSL_SMALL_STACK
+   byte*          buf;
+#else
+   byte           buf[ECC_MAXSIZE];
+#endif
+   int            keysize;
+   int            po_init = 0;  /* prime order Init flag for clear */
+
+   if (key == NULL || rng == NULL || dp == NULL)
+       return ECC_BAD_ARG_E;
+
+#ifdef WOLFSSL_SMALL_STACK
+   buf = (byte*)XMALLOC(ECC_MAXSIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+   if (buf == NULL)
+       return MEMORY_E;
+#endif
+
+   key->idx = -1;
+   key->dp  = dp;
+   keysize  = dp->size;
+
+   /* allocate ram */
+   base = NULL;
+
+   /* make up random string */
+   err = wc_RNG_GenerateBlock(rng, buf, keysize);
+   if (err == 0)
+       buf[0] |= 0x0c;
+
+   /* setup the key variables */
+   if (err == 0) {
+#ifndef ALT_ECC_SIZE
+       err = mp_init_multi(key->pubkey.x, key->pubkey.y, key->pubkey.z,
+                            &key->k, &prime, &order);
+#else
+       key->pubkey.x = (mp_int*)&key->pubkey.xyz[0];
+       key->pubkey.y = (mp_int*)&key->pubkey.xyz[1];
+       key->pubkey.z = (mp_int*)&key->pubkey.xyz[2];
+       alt_fp_init(key->pubkey.x);
+       alt_fp_init(key->pubkey.y);
+       alt_fp_init(key->pubkey.z);
+       err = mp_init_multi(&key->k, &prime, &order, NULL, NULL, NULL);
+#endif
+       if (err != MP_OKAY)
+           err = MEMORY_E;
+       else
+           po_init = 1;
+   }
+
+   if (err == MP_OKAY) {
+       base = ecc_new_point();
+       if (base == NULL)
+           err = MEMORY_E;
+   }
+
+   /* read in the specs for this key */
+   if (err == MP_OKAY) 
+       err = mp_read_radix(&prime,   (char *)key->dp->prime, 16);
+   if (err == MP_OKAY) 
+       err = mp_read_radix(&order,   (char *)key->dp->order, 16);
+   if (err == MP_OKAY) 
+       err = mp_read_radix(base->x, (char *)key->dp->Gx, 16);
+   if (err == MP_OKAY) 
+       err = mp_read_radix(base->y, (char *)key->dp->Gy, 16);
+   
+   if (err == MP_OKAY) 
+       mp_set(base->z, 1);
+   if (err == MP_OKAY) 
+       err = mp_read_unsigned_bin(&key->k, (byte*)buf, keysize);
+
+   /* the key should be smaller than the order of base point */
+   if (err == MP_OKAY) { 
+       if (mp_cmp(&key->k, &order) != MP_LT)
+           err = mp_mod(&key->k, &order, &key->k);
+   }
+   /* make the public key */
+   if (err == MP_OKAY)
+       err = ecc_mulmod(&key->k, base, &key->pubkey, &prime, 1);
+
+#ifdef WOLFSSL_VALIDATE_ECC_KEYGEN
+   /* validate the public key, order * pubkey = point at infinity */
+   if (err == MP_OKAY)
+       err = ecc_check_pubkey_order(key, &prime, &order);
+#endif /* WOLFSSL_VALIDATE_KEYGEN */
+
+   if (err == MP_OKAY)
+       key->type = ECC_PRIVATEKEY;
+
+   if (err != MP_OKAY) {
+       /* clean up */
+       mp_clear(key->pubkey.x);
+       mp_clear(key->pubkey.y);
+       mp_clear(key->pubkey.z);
+       mp_clear(&key->k);
+   }
+   ecc_del_point(base);
+   if (po_init) {
+       mp_clear(&prime);
+       mp_clear(&order);
+   }
+
+   ForceZero(buf, ECC_MAXSIZE);
+#ifdef WOLFSSL_SMALL_STACK
+   XFREE(buf, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+   return err;
+}
+
+
+/* Setup dynamic pointers is using normal math for proper freeing */
+int wc_ecc_init(ecc_key* key)
+{
+    (void)key;
+
+#ifndef USE_FAST_MATH
+    key->pubkey.x->dp = NULL;
+    key->pubkey.y->dp = NULL;
+    key->pubkey.z->dp = NULL;
+
+    key->k.dp = NULL;
+#endif
+
+#ifdef ALT_ECC_SIZE
+    if (mp_init(&key->k) != MP_OKAY)
+        return MEMORY_E;
+
+    key->pubkey.x = (mp_int*)&key->pubkey.xyz[0];
+    key->pubkey.y = (mp_int*)&key->pubkey.xyz[1];
+    key->pubkey.z = (mp_int*)&key->pubkey.xyz[2];
+    alt_fp_init(key->pubkey.x);
+    alt_fp_init(key->pubkey.y);
+    alt_fp_init(key->pubkey.z);
+#endif
+
+    return 0;
+}
+
+
+/**
+  Sign a message digest
+  in        The message digest to sign
+  inlen     The length of the digest
+  out       [out] The destination for the signature
+  outlen    [in/out] The max size and resulting size of the signature
+  key       A private ECC key
+  return    MP_OKAY if successful
+*/
+int wc_ecc_sign_hash(const byte* in, word32 inlen, byte* out, word32 *outlen, 
+                  RNG* rng, ecc_key* key)
+{
+   mp_int        r;
+   mp_int        s;
+   mp_int        e;
+   mp_int        p;
+   int           err;
+
+   if (in == NULL || out == NULL || outlen == NULL || key == NULL || rng ==NULL)
+       return ECC_BAD_ARG_E;
+
+   /* is this a private key? */
+   if (key->type != ECC_PRIVATEKEY) {
+      return ECC_BAD_ARG_E;
+   }
+   
+   /* is the IDX valid ?  */
+   if (ecc_is_valid_idx(key->idx) != 1) {
+      return ECC_BAD_ARG_E;
+   }
+
+   /* get the hash and load it as a bignum into 'e' */
+   /* init the bignums */
+   if ((err = mp_init_multi(&r, &s, &p, &e, NULL, NULL)) != MP_OKAY) { 
+      return err;
+   }
+   err = mp_read_radix(&p, (char *)key->dp->order, 16);
+
+   if (err == MP_OKAY) {
+       /* we may need to truncate if hash is longer than key size */
+       word32 orderBits = mp_count_bits(&p);
+
+       /* truncate down to byte size, may be all that's needed */
+       if ( (WOLFSSL_BIT_SIZE * inlen) > orderBits)
+           inlen = (orderBits + WOLFSSL_BIT_SIZE - 1)/WOLFSSL_BIT_SIZE;
+       err = mp_read_unsigned_bin(&e, (byte*)in, inlen);
+
+       /* may still need bit truncation too */
+       if (err == MP_OKAY && (WOLFSSL_BIT_SIZE * inlen) > orderBits)
+           mp_rshb(&e, WOLFSSL_BIT_SIZE - (orderBits & 0x7));
+   }
+
+   /* make up a key and export the public copy */
+   if (err == MP_OKAY) {
+       int loop_check = 0;
+       ecc_key pubkey;
+       wc_ecc_init(&pubkey);
+       for (;;) {
+           if (++loop_check > 64) {
+                err = RNG_FAILURE_E;
+                break;
+           }
+           err = wc_ecc_make_key_ex(rng, &pubkey, key->dp);
+           if (err != MP_OKAY) break;
+
+           /* find r = x1 mod n */
+           err = mp_mod(pubkey.pubkey.x, &p, &r);
+           if (err != MP_OKAY) break;
+
+           if (mp_iszero(&r) == MP_YES) {
+               mp_clear(pubkey.pubkey.x);
+               mp_clear(pubkey.pubkey.y);
+               mp_clear(pubkey.pubkey.z);
+               mp_clear(&pubkey.k);
+           }
+           else { 
+               /* find s = (e + xr)/k */
+               err = mp_invmod(&pubkey.k, &p, &pubkey.k);
+               if (err != MP_OKAY) break;
+
+               err = mp_mulmod(&key->k, &r, &p, &s);   /* s = xr */
+               if (err != MP_OKAY) break;
+           
+               err = mp_add(&e, &s, &s);               /* s = e +  xr */
+               if (err != MP_OKAY) break;
+
+               err = mp_mod(&s, &p, &s);               /* s = e +  xr */
+               if (err != MP_OKAY) break;
+
+               err = mp_mulmod(&s, &pubkey.k, &p, &s); /* s = (e + xr)/k */
+               if (err != MP_OKAY) break;
+
+               if (mp_iszero(&s) == MP_NO)
+                   break;
+            }
+       }
+       wc_ecc_free(&pubkey);
+   }
+
+   /* store as SEQUENCE { r, s -- integer } */
+   if (err == MP_OKAY)
+       err = StoreECC_DSA_Sig(out, outlen, &r, &s);
+
+   mp_clear(&r);
+   mp_clear(&s);
+   mp_clear(&p);
+   mp_clear(&e);
+
+   return err;
+}
+
+
+/**
+  Free an ECC key from memory
+  key   The key you wish to free
+*/
+void wc_ecc_free(ecc_key* key)
+{
+   if (key == NULL)
+       return;
+
+   mp_clear(key->pubkey.x);
+   mp_clear(key->pubkey.y);
+   mp_clear(key->pubkey.z);
+   mp_clear(&key->k);
+}
+
+
+#ifdef USE_FAST_MATH
+    #define GEN_MEM_ERR FP_MEM
+#else
+    #define GEN_MEM_ERR MP_MEM
+#endif
+
+#ifdef ECC_SHAMIR
+
+/** Computes kA*A + kB*B = C using Shamir's Trick
+  A        First point to multiply
+  kA       What to multiple A by
+  B        Second point to multiply
+  kB       What to multiple B by
+  C        [out] Destination point (can overlap with A or B)
+  modulus  Modulus for curve 
+  return MP_OKAY on success
+*/
+#ifdef FP_ECC
+static int normal_ecc_mul2add(ecc_point* A, mp_int* kA,
+                             ecc_point* B, mp_int* kB,
+                             ecc_point* C, mp_int* modulus)
+#else
+static int ecc_mul2add(ecc_point* A, mp_int* kA,
+                    ecc_point* B, mp_int* kB,
+                    ecc_point* C, mp_int* modulus)
+#endif
+{
+  ecc_point*     precomp[16];
+  unsigned       bitbufA, bitbufB, lenA, lenB, len, x, y, nA, nB, nibble;
+  unsigned char* tA;
+  unsigned char* tB;
+  int            err = MP_OKAY, first;
+  int            muInit    = 0;
+  int            tableInit = 0;
+  mp_digit mp;
+  mp_int   mu;
+ 
+  /* argchks */
+  if (A == NULL || kA == NULL || B == NULL || kB == NULL || C == NULL || 
+                   modulus == NULL)
+    return ECC_BAD_ARG_E;
+
+
+  /* allocate memory */
+  tA = (unsigned char*)XMALLOC(ECC_BUFSIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+  if (tA == NULL) {
+     return GEN_MEM_ERR;
+  }
+  tB = (unsigned char*)XMALLOC(ECC_BUFSIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+  if (tB == NULL) {
+     XFREE(tA, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+     return GEN_MEM_ERR;
+  }
+  XMEMSET(tA, 0, ECC_BUFSIZE);
+  XMEMSET(tB, 0, ECC_BUFSIZE);
+
+  /* get sizes */
+  lenA = mp_unsigned_bin_size(kA);
+  lenB = mp_unsigned_bin_size(kB);
+  len  = MAX(lenA, lenB);
+
+  /* sanity check */
+  if ((lenA > ECC_BUFSIZE) || (lenB > ECC_BUFSIZE)) {
+     err = BAD_FUNC_ARG;
+  }
+
+  if (err == MP_OKAY) {
+    /* extract and justify kA */
+    err = mp_to_unsigned_bin(kA, (len - lenA) + tA);
+
+    /* extract and justify kB */
+    if (err == MP_OKAY)
+        err = mp_to_unsigned_bin(kB, (len - lenB) + tB);
+
+    /* allocate the table */
+    if (err == MP_OKAY) {
+        for (x = 0; x < 16; x++) {
+            precomp[x] = ecc_new_point();
+            if (precomp[x] == NULL) {
+                for (y = 0; y < x; ++y) {
+                    ecc_del_point(precomp[y]);
+                }
+                err = GEN_MEM_ERR;
+                break;
+            }
+        }
+    }
+  }
+
+  if (err == MP_OKAY)
+    tableInit = 1;
+
+  if (err == MP_OKAY)
+   /* init montgomery reduction */
+   err = mp_montgomery_setup(modulus, &mp);
+
+  if (err == MP_OKAY)
+    err = mp_init(&mu);
+  if (err == MP_OKAY)
+    muInit = 1;
+
+  if (err == MP_OKAY)
+    err = mp_montgomery_calc_normalization(&mu, modulus);
+
+  if (err == MP_OKAY)
+    /* copy ones ... */
+    err = mp_mulmod(A->x, &mu, modulus, precomp[1]->x);
+
+  if (err == MP_OKAY)
+    err = mp_mulmod(A->y, &mu, modulus, precomp[1]->y);
+  if (err == MP_OKAY)
+    err = mp_mulmod(A->z, &mu, modulus, precomp[1]->z);
+
+  if (err == MP_OKAY)
+    err = mp_mulmod(B->x, &mu, modulus, precomp[1<<2]->x);
+  if (err == MP_OKAY)
+    err = mp_mulmod(B->y, &mu, modulus, precomp[1<<2]->y);
+  if (err == MP_OKAY)
+    err = mp_mulmod(B->z, &mu, modulus, precomp[1<<2]->z);
+
+  if (err == MP_OKAY)
+    /* precomp [i,0](A + B) table */
+    err = ecc_projective_dbl_point(precomp[1], precomp[2], modulus, &mp);
+
+  if (err == MP_OKAY)
+    err = ecc_projective_add_point(precomp[1], precomp[2], precomp[3],
+                                   modulus, &mp);
+  if (err == MP_OKAY)
+    /* precomp [0,i](A + B) table */
+    err = ecc_projective_dbl_point(precomp[1<<2], precomp[2<<2], modulus, &mp);
+
+  if (err == MP_OKAY)
+    err = ecc_projective_add_point(precomp[1<<2], precomp[2<<2], precomp[3<<2],
+                                   modulus, &mp);
+
+  if (err == MP_OKAY) {
+    /* precomp [i,j](A + B) table (i != 0, j != 0) */
+    for (x = 1; x < 4; x++) {
+        for (y = 1; y < 4; y++) {
+            if (err == MP_OKAY)
+                err = ecc_projective_add_point(precomp[x], precomp[(y<<2)],
+                                               precomp[x+(y<<2)], modulus, &mp);
+        }
+    } 
+  }  
+
+  if (err == MP_OKAY) {
+    nibble  = 3;
+    first   = 1;
+    bitbufA = tA[0];
+    bitbufB = tB[0];
+
+    /* for every byte of the multiplicands */
+    for (x = -1;; ) {
+        /* grab a nibble */
+        if (++nibble == 4) {
+            ++x; if (x == len) break;
+            bitbufA = tA[x];
+            bitbufB = tB[x];
+            nibble  = 0;
+        }
+
+        /* extract two bits from both, shift/update */
+        nA = (bitbufA >> 6) & 0x03;
+        nB = (bitbufB >> 6) & 0x03;
+        bitbufA = (bitbufA << 2) & 0xFF;   
+        bitbufB = (bitbufB << 2) & 0xFF;   
+
+        /* if both zero, if first, continue */
+        if ((nA == 0) && (nB == 0) && (first == 1)) {
+            continue;
+        }
+
+        /* double twice, only if this isn't the first */
+        if (first == 0) {
+            /* double twice */
+            if (err == MP_OKAY)
+                err = ecc_projective_dbl_point(C, C, modulus, &mp);
+            if (err == MP_OKAY)
+                err = ecc_projective_dbl_point(C, C, modulus, &mp);
+            else
+                break;
+        }
+
+        /* if not both zero */
+        if ((nA != 0) || (nB != 0)) {
+            if (first == 1) {
+                /* if first, copy from table */
+                first = 0;
+                if (err == MP_OKAY)
+                    err = mp_copy(precomp[nA + (nB<<2)]->x, C->x);
+
+                if (err == MP_OKAY)
+                    err = mp_copy(precomp[nA + (nB<<2)]->y, C->y);
+
+                if (err == MP_OKAY)
+                    err = mp_copy(precomp[nA + (nB<<2)]->z, C->z);
+                else
+                    break;
+            } else {
+                /* if not first, add from table */
+                if (err == MP_OKAY)
+                    err = ecc_projective_add_point(C, precomp[nA + (nB<<2)], C,
+                                                   modulus, &mp);
+                else
+                    break;
+            }
+        }
+    }
+  }
+
+  if (err == MP_OKAY)
+    /* reduce to affine */
+    err = ecc_map(C, modulus, &mp);
+
+  /* clean up */
+  if (muInit)
+    mp_clear(&mu);
+
+  if (tableInit) {
+    for (x = 0; x < 16; x++) {
+       ecc_del_point(precomp[x]);
+    }
+  }
+   ForceZero(tA, ECC_BUFSIZE);
+   ForceZero(tB, ECC_BUFSIZE);
+   XFREE(tA, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+   XFREE(tB, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+
+   return err;
+}
+
+
+#endif /* ECC_SHAMIR */
+
+
+
+/* verify 
+ *
+ * w  = s^-1 mod n
+ * u1 = xw 
+ * u2 = rw
+ * X = u1*G + u2*Q
+ * v = X_x1 mod n
+ * accept if v == r
+ */
+
+/**
+   Verify an ECC signature
+   sig         The signature to verify
+   siglen      The length of the signature (octets)
+   hash        The hash (message digest) that was signed
+   hashlen     The length of the hash (octets)
+   stat        Result of signature, 1==valid, 0==invalid
+   key         The corresponding public ECC key
+   return      MP_OKAY if successful (even if the signature is not valid)
+*/
+int wc_ecc_verify_hash(const byte* sig, word32 siglen, const byte* hash,
+                    word32 hashlen, int* stat, ecc_key* key)
+{
+   ecc_point    *mG, *mQ;
+   mp_int        r;
+   mp_int        s;
+   mp_int        v;
+   mp_int        w;
+   mp_int        u1;
+   mp_int        u2;
+   mp_int        e;
+   mp_int        p;
+   mp_int        m;
+   int           err;
+
+   if (sig == NULL || hash == NULL || stat == NULL || key == NULL)
+       return ECC_BAD_ARG_E; 
+
+   /* default to invalid signature */
+   *stat = 0;
+
+   /* is the IDX valid ?  */
+   if (ecc_is_valid_idx(key->idx) != 1) {
+      return ECC_BAD_ARG_E;
+   }
+
+   /* allocate ints */
+   if ((err = mp_init_multi(&v, &w, &u1, &u2, &p, &e)) != MP_OKAY) {
+      return MEMORY_E;
+   }
+
+   if ((err = mp_init(&m)) != MP_OKAY) {
+      mp_clear(&v);
+      mp_clear(&w);
+      mp_clear(&u1);
+      mp_clear(&u2);
+      mp_clear(&p);
+      mp_clear(&e);
+      return MEMORY_E;
+   }
+
+   /* allocate points */
+   mG = ecc_new_point();
+   mQ = ecc_new_point();
+   if (mQ  == NULL || mG == NULL)
+      err = MEMORY_E;
+
+   /* Note, DecodeECC_DSA_Sig() calls mp_init() on r and s.
+    * If either of those don't allocate correctly, none of
+    * the rest of this function will execute, and everything
+    * gets cleaned up at the end. */
+   XMEMSET(&r, 0, sizeof(r));
+   XMEMSET(&s, 0, sizeof(s));
+   if (err == MP_OKAY)
+       err = DecodeECC_DSA_Sig(sig, siglen, &r, &s);
+
+   /* get the order */
+   if (err == MP_OKAY)
+       err = mp_read_radix(&p, (char *)key->dp->order, 16);
+
+   /* get the modulus */
+   if (err == MP_OKAY)
+       err = mp_read_radix(&m, (char *)key->dp->prime, 16);
+
+   /* check for zero */
+   if (err == MP_OKAY) {
+       if (mp_iszero(&r) || mp_iszero(&s) || mp_cmp(&r, &p) != MP_LT ||
+                                             mp_cmp(&s, &p) != MP_LT)
+           err = MP_ZERO_E; 
+   }
+   /* read hash */
+   if (err == MP_OKAY) {
+       /* we may need to truncate if hash is longer than key size */
+       unsigned int orderBits = mp_count_bits(&p);
+
+       /* truncate down to byte size, may be all that's needed */
+       if ( (WOLFSSL_BIT_SIZE * hashlen) > orderBits)
+           hashlen = (orderBits + WOLFSSL_BIT_SIZE - 1)/WOLFSSL_BIT_SIZE;
+       err = mp_read_unsigned_bin(&e, hash, hashlen);
+
+       /* may still need bit truncation too */
+       if (err == MP_OKAY && (WOLFSSL_BIT_SIZE * hashlen) > orderBits)
+           mp_rshb(&e, WOLFSSL_BIT_SIZE - (orderBits & 0x7));
+   }
+
+   /*  w  = s^-1 mod n */
+   if (err == MP_OKAY)
+       err = mp_invmod(&s, &p, &w);
+
+   /* u1 = ew */
+   if (err == MP_OKAY)
+       err = mp_mulmod(&e, &w, &p, &u1);
+
+   /* u2 = rw */
+   if (err == MP_OKAY)
+       err = mp_mulmod(&r, &w, &p, &u2);
+
+   /* find mG and mQ */
+   if (err == MP_OKAY)
+       err = mp_read_radix(mG->x, (char *)key->dp->Gx, 16);
+
+   if (err == MP_OKAY)
+       err = mp_read_radix(mG->y, (char *)key->dp->Gy, 16);
+   if (err == MP_OKAY)
+       mp_set(mG->z, 1);
+
+   if (err == MP_OKAY)
+       err = mp_copy(key->pubkey.x, mQ->x);
+   if (err == MP_OKAY)
+       err = mp_copy(key->pubkey.y, mQ->y);
+   if (err == MP_OKAY)
+       err = mp_copy(key->pubkey.z, mQ->z);
+
+#ifndef ECC_SHAMIR
+    {
+       mp_digit      mp;
+
+       /* compute u1*mG + u2*mQ = mG */
+       if (err == MP_OKAY)
+           err = ecc_mulmod(&u1, mG, mG, &m, 0);
+       if (err == MP_OKAY)
+           err = ecc_mulmod(&u2, mQ, mQ, &m, 0);
+  
+       /* find the montgomery mp */
+       if (err == MP_OKAY)
+           err = mp_montgomery_setup(&m, &mp);
+
+       /* add them */
+       if (err == MP_OKAY)
+           err = ecc_projective_add_point(mQ, mG, mG, &m, &mp);
+   
+       /* reduce */
+       if (err == MP_OKAY)
+           err = ecc_map(mG, &m, &mp);
+    }
+#else
+       /* use Shamir's trick to compute u1*mG + u2*mQ using half the doubles */
+       if (err == MP_OKAY)
+           err = ecc_mul2add(mG, &u1, mQ, &u2, mG, &m);
+#endif /* ECC_SHAMIR */ 
+
+   /* v = X_x1 mod n */
+   if (err == MP_OKAY)
+       err = mp_mod(mG->x, &p, &v);
+
+   /* does v == r */
+   if (err == MP_OKAY) {
+       if (mp_cmp(&v, &r) == MP_EQ)
+           *stat = 1;
+   }
+
+   ecc_del_point(mG);
+   ecc_del_point(mQ);
+
+   mp_clear(&r);
+   mp_clear(&s);
+   mp_clear(&v);
+   mp_clear(&w);
+   mp_clear(&u1);
+   mp_clear(&u2);
+   mp_clear(&p);
+   mp_clear(&e);
+   mp_clear(&m);
+
+   return err;
+}
+
+
+/* export public ECC key in ANSI X9.63 format */
+int wc_ecc_export_x963(ecc_key* key, byte* out, word32* outLen)
+{
+#ifdef WOLFSSL_SMALL_STACK
+   byte*  buf;
+#else
+   byte   buf[ECC_BUFSIZE];
+#endif
+   word32 numlen;
+   int    ret = MP_OKAY;
+
+   /* return length needed only */
+   if (key != NULL && out == NULL && outLen != NULL) {
+      numlen = key->dp->size;
+      *outLen = 1 + 2*numlen;
+      return LENGTH_ONLY_E;
+   }
+
+   if (key == NULL || out == NULL || outLen == NULL)
+      return ECC_BAD_ARG_E;
+
+   if (ecc_is_valid_idx(key->idx) == 0) {
+      return ECC_BAD_ARG_E;
+   }
+   numlen = key->dp->size;
+
+   if (*outLen < (1 + 2*numlen)) {
+      *outLen = 1 + 2*numlen;
+      return BUFFER_E;
+   }
+
+   /* store byte 0x04 */
+   out[0] = 0x04;
+
+#ifdef WOLFSSL_SMALL_STACK
+   buf = (byte*)XMALLOC(ECC_BUFSIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+   if (buf == NULL)
+      return MEMORY_E;
+#endif
+
+   do {
+      /* pad and store x */
+      XMEMSET(buf, 0, ECC_BUFSIZE);
+      ret = mp_to_unsigned_bin(key->pubkey.x,
+                         buf + (numlen - mp_unsigned_bin_size(key->pubkey.x)));
+      if (ret != MP_OKAY)
+         break;
+      XMEMCPY(out+1, buf, numlen);
+
+      /* pad and store y */
+      XMEMSET(buf, 0, ECC_BUFSIZE);
+      ret = mp_to_unsigned_bin(key->pubkey.y,
+                         buf + (numlen - mp_unsigned_bin_size(key->pubkey.y)));
+      if (ret != MP_OKAY)
+         break;
+      XMEMCPY(out+1+numlen, buf, numlen);
+
+      *outLen = 1 + 2*numlen;
+   } while (0);
+
+#ifdef WOLFSSL_SMALL_STACK
+   XFREE(buf, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+   return ret;
+}
+
+
+/* export public ECC key in ANSI X9.63 format, extended with
+ * compression option */
+int wc_ecc_export_x963_ex(ecc_key* key, byte* out, word32* outLen, int compressed)
+{
+    if (compressed == 0)
+        return wc_ecc_export_x963(key, out, outLen);
+#ifdef HAVE_COMP_KEY
+    else
+        return wc_ecc_export_x963_compressed(key, out, outLen);
+#endif
+
+    return NOT_COMPILED_IN;
+}
+
+
+/* is ec point on curve descriped by dp ? */
+static int ecc_is_point(const ecc_set_type* dp, ecc_point* ecp, mp_int* prime)
+{
+   mp_int b, t1, t2;
+   int err;
+
+   if ((err = mp_init_multi(&b, &t1, &t2, NULL, NULL, NULL)) != MP_OKAY) {
+      return err;
+   }
+
+   /* load  b */
+   err = mp_read_radix(&b, dp->Bf, 16);
+
+   /* compute y^2 */
+   if (err == MP_OKAY)
+       err = mp_sqr(ecp->y, &t1);
+
+   /* compute x^3 */
+   if (err == MP_OKAY)
+       err = mp_sqr(ecp->x, &t2);
+   if (err == MP_OKAY)
+       err = mp_mod(&t2, prime, &t2);
+   if (err == MP_OKAY)
+       err = mp_mul(ecp->x, &t2, &t2);
+
+   /* compute y^2 - x^3 */
+   if (err == MP_OKAY)
+       err = mp_sub(&t1, &t2, &t1);
+
+   /* compute y^2 - x^3 + 3x */
+   if (err == MP_OKAY)
+       err = mp_add(&t1, ecp->x, &t1);
+   if (err == MP_OKAY)
+       err = mp_add(&t1, ecp->x, &t1);
+   if (err == MP_OKAY)
+       err = mp_add(&t1, ecp->x, &t1);
+   if (err == MP_OKAY)
+       err = mp_mod(&t1, prime, &t1);
+
+   while (err == MP_OKAY && mp_cmp_d(&t1, 0) == MP_LT) {
+      err = mp_add(&t1, prime, &t1);
+   }
+   while (err == MP_OKAY && mp_cmp(&t1, prime) != MP_LT) {
+      err = mp_sub(&t1, prime, &t1);
+   }
+
+   /* compare to b */
+   if (err == MP_OKAY) {
+       if (mp_cmp(&t1, &b) != MP_EQ) {
+          err = MP_VAL;
+       } else {
+          err = MP_OKAY;
+       }
+   }
+
+   mp_clear(&b);
+   mp_clear(&t1);
+   mp_clear(&t2);
+
+   return err;
+}
+
+
+/* validate privkey * generator == pubkey, 0 on success */
+static int ecc_check_privkey_gen(ecc_key* key, mp_int* prime)
+{
+    ecc_point* base = NULL;
+    ecc_point* res  = NULL;
+    int        err;
+
+    if (key == NULL)
+        return BAD_FUNC_ARG;
+
+    base = ecc_new_point();
+    if (base == NULL)
+        return MEMORY_E;
+
+    /* set up base generator */
+    err = mp_read_radix(base->x, (char*)key->dp->Gx, 16);
+    if (err == MP_OKAY)
+        err = mp_read_radix(base->y, (char*)key->dp->Gy, 16);
+    if (err == MP_OKAY)
+        mp_set(base->z, 1);
+
+    if (err == MP_OKAY) {
+        res = ecc_new_point();
+        if (res == NULL)
+            err = MEMORY_E;
+        else {
+            err = ecc_mulmod(&key->k, base, res, prime, 1);
+            if (err == MP_OKAY) {
+                /* compare result to public key */
+                if (mp_cmp(res->x, key->pubkey.x) != MP_EQ ||
+                    mp_cmp(res->y, key->pubkey.y) != MP_EQ ||
+                    mp_cmp(res->z, key->pubkey.z) != MP_EQ) {
+                    /* didn't match */
+                    err = ECC_PRIV_KEY_E;
+                }
+            }
+        }
+    }
+
+    ecc_del_point(res);
+    ecc_del_point(base);
+
+    return err;
+}
+
+
+#ifdef WOLFSSL_VALIDATE_ECC_IMPORT
+
+/* check privkey generator helper, creates prime needed */
+static int ecc_check_privkey_gen_helper(ecc_key* key)
+{
+    mp_int prime;
+    int    err;
+
+    if (key == NULL)
+        return BAD_FUNC_ARG;
+
+    err = mp_init(&prime);
+    if (err != MP_OKAY)
+        return err;
+
+    err = mp_read_radix(&prime, (char*)key->dp->prime, 16);
+
+    if (err == MP_OKAY);
+        err = ecc_check_privkey_gen(key, &prime);
+
+    mp_clear(&prime);
+
+    return err;
+}
+
+#endif /* WOLFSSL_VALIDATE_ECC_IMPORT */
+
+
+/* validate order * pubkey = point at infinity, 0 on success */
+static int ecc_check_pubkey_order(ecc_key* key, mp_int* prime, mp_int* order)
+{
+    ecc_point* inf = NULL;
+    int        err;
+
+    if (key == NULL)
+        return BAD_FUNC_ARG;
+
+    inf = ecc_new_point();
+    if (inf == NULL)
+        err = MEMORY_E;
+    else {
+        err = ecc_mulmod(order, &key->pubkey, inf, prime, 1);
+        if (err == MP_OKAY && !ecc_point_is_at_infinity(inf))
+            err = ECC_INF_E;
+    }
+
+    ecc_del_point(inf);
+
+    return err;
+}
+
+
+/* perform sanity checks on ec key validity, 0 on success */
+int wc_ecc_check_key(ecc_key* key)
+{
+    mp_int prime;  /* used by multiple calls so let's cache */
+    mp_int order;  /* other callers have, so let's gen here */
+    int    err;
+
+    if (key == NULL)
+        return BAD_FUNC_ARG;
+
+    /* pubkey point cannot be at inifinity */
+    if (ecc_point_is_at_infinity(&key->pubkey))
+        return ECC_INF_E;
+
+    err = mp_init_multi(&prime, &order, NULL, NULL, NULL, NULL);
+    if (err != MP_OKAY)
+        return err;
+
+    err = mp_read_radix(&prime, (char*)key->dp->prime, 16);
+
+    /* make sure point is actually on curve */
+    if (err == MP_OKAY)
+        err = ecc_is_point(key->dp, &key->pubkey, &prime);
+
+    if (err == MP_OKAY)
+        err = mp_read_radix(&order, (char*)key->dp->order, 16);
+
+    /* pubkey * order must be at infinity */
+    if (err == MP_OKAY)
+        err = ecc_check_pubkey_order(key, &prime, &order);
+
+    /* private * base generator must equal pubkey */
+    if (err == MP_OKAY && key->type == ECC_PRIVATEKEY)
+        err = ecc_check_privkey_gen(key, &prime);
+
+    mp_clear(&order);
+    mp_clear(&prime);
+
+    return err;
+}
+
+
+/* import public ECC key in ANSI X9.63 format */
+int wc_ecc_import_x963(const byte* in, word32 inLen, ecc_key* key)
+{
+   int x, err;
+   int compressed = 0;
+   
+   if (in == NULL || key == NULL)
+       return ECC_BAD_ARG_E;
+
+   /* must be odd */
+   if ((inLen & 1) == 0) {
+      return ECC_BAD_ARG_E;
+   }
+
+   /* init key */
+#ifdef ALT_ECC_SIZE
+   key->pubkey.x = (mp_int*)&key->pubkey.xyz[0];
+   key->pubkey.y = (mp_int*)&key->pubkey.xyz[1];
+   key->pubkey.z = (mp_int*)&key->pubkey.xyz[2];
+   alt_fp_init(key->pubkey.x);
+   alt_fp_init(key->pubkey.y);
+   alt_fp_init(key->pubkey.z);
+   err = mp_init(&key->k);
+#else
+   err = mp_init_multi(key->pubkey.x, key->pubkey.y, key->pubkey.z, &key->k,
+                     NULL, NULL);
+#endif
+   if (err != MP_OKAY)
+      return MEMORY_E;
+
+   /* check for 4, 2, or 3 */
+   if (in[0] != 0x04 && in[0] != 0x02 && in[0] != 0x03) {
+      err = ASN_PARSE_E;
+   }
+
+   if (in[0] == 0x02 || in[0] == 0x03) {
+#ifdef HAVE_COMP_KEY
+       compressed = 1;
+#else
+       err = NOT_COMPILED_IN;
+#endif
+   }
+
+   if (err == MP_OKAY) {
+      /* determine the idx */
+
+      if (compressed)
+          inLen = (inLen-1)*2 + 1;  /* used uncompressed len */
+
+      for (x = 0; ecc_sets[x].size != 0; x++) {
+         if ((unsigned)ecc_sets[x].size >= ((inLen-1)>>1)) {
+            break;
+         }
+      }
+      if (ecc_sets[x].size == 0) {
+         err = ASN_PARSE_E;
+      } else {
+          /* set the idx */
+          key->idx  = x;
+          key->dp = &ecc_sets[x];
+          key->type = ECC_PUBLICKEY;
+      }
+   }
+
+   /* read data */
+   if (err == MP_OKAY)
+       err = mp_read_unsigned_bin(key->pubkey.x, (byte*)in+1, (inLen-1)>>1);
+
+#ifdef HAVE_COMP_KEY
+   if (err == MP_OKAY && compressed == 1) {   /* build y */
+        mp_int t1, t2, prime, a, b;
+
+        if (mp_init_multi(&t1, &t2, &prime, &a, &b, NULL) != MP_OKAY)
+            err = MEMORY_E;
+
+        /* load prime */
+        if (err == MP_OKAY)
+            err = mp_read_radix(&prime, (char *)key->dp->prime, 16);
+
+        /* load a */
+        if (err == MP_OKAY)
+            err = mp_read_radix(&a, (char *)key->dp->Af, 16);
+
+        /* load b */
+        if (err == MP_OKAY)
+            err = mp_read_radix(&b, (char *)key->dp->Bf, 16);
+
+        /* compute x^3 */
+        if (err == MP_OKAY)
+            err = mp_sqr(key->pubkey.x, &t1);
+
+        if (err == MP_OKAY)
+            err = mp_mulmod(&t1, key->pubkey.x, &prime, &t1);
+
+        /* compute x^3 + a*x */
+        if (err == MP_OKAY)
+            err = mp_mulmod(&a, key->pubkey.x, &prime, &t2);
+
+        if (err == MP_OKAY)
+            err = mp_add(&t1, &t2, &t1);
+
+        /* compute x^3 + a*x + b */
+        if (err == MP_OKAY)
+            err = mp_add(&t1, &b, &t1);
+
+        /* compute sqrt(x^3 + a*x + b) */
+        if (err == MP_OKAY)
+            err = mp_sqrtmod_prime(&t1, &prime, &t2);
+
+        /* adjust y */
+        if (err == MP_OKAY) {
+            if ((mp_isodd(&t2) && in[0] == 0x03) ||
+               (!mp_isodd(&t2) && in[0] == 0x02)) {
+                err = mp_mod(&t2, &prime, key->pubkey.y);
+            }
+            else {
+                err = mp_submod(&prime, &t2, &prime, key->pubkey.y);
+            }
+        }
+
+        mp_clear(&a);
+        mp_clear(&b);
+        mp_clear(&prime);
+        mp_clear(&t2);
+        mp_clear(&t1);
+   }
+#endif
+
+   if (err == MP_OKAY && compressed == 0)
+       err = mp_read_unsigned_bin(key->pubkey.y, (byte*)in+1+((inLen-1)>>1),
+                                  (inLen-1)>>1);
+   if (err == MP_OKAY)
+       mp_set(key->pubkey.z, 1);
+
+#ifdef WOLFSSL_VALIDATE_ECC_IMPORT
+   if (err == MP_OKAY)
+       err = wc_ecc_check_key(key);
+#endif
+
+   if (err != MP_OKAY) {
+       mp_clear(key->pubkey.x);
+       mp_clear(key->pubkey.y);
+       mp_clear(key->pubkey.z);
+       mp_clear(&key->k);
+   }
+
+   return err;
+}
+
+
+/* export ecc private key only raw, outLen is in/out size 
+   return MP_OKAY on success */
+int wc_ecc_export_private_only(ecc_key* key, byte* out, word32* outLen)
+{
+   word32 numlen;
+
+   if (key == NULL || out == NULL || outLen == NULL)
+       return ECC_BAD_ARG_E;
+
+   if (ecc_is_valid_idx(key->idx) == 0) {
+      return ECC_BAD_ARG_E;
+   }
+   numlen = key->dp->size;
+
+   if (*outLen < numlen) {
+      *outLen = numlen;
+      return BUFFER_E;
+   }
+   *outLen = numlen; 
+   XMEMSET(out, 0, *outLen);
+   return mp_to_unsigned_bin(&key->k, out + (numlen -
+                                             mp_unsigned_bin_size(&key->k)));
+}
+
+
+/* ecc private key import, public key in ANSI X9.63 format, private raw */
+int wc_ecc_import_private_key(const byte* priv, word32 privSz, const byte* pub,
+                           word32 pubSz, ecc_key* key)
+{
+    int ret = wc_ecc_import_x963(pub, pubSz, key);
+    if (ret != 0)
+        return ret;
+
+    key->type = ECC_PRIVATEKEY;
+
+    ret = mp_read_unsigned_bin(&key->k, priv, privSz);
+
+#ifdef WOLFSSL_VALIDATE_ECC_IMPORT
+    if (ret == MP_OKAY)
+        ret = ecc_check_privkey_gen_helper(key);
+#endif
+
+    return ret;
+}
+
+/**
+   Convert ECC R,S to signature
+   r       R component of signature
+   s       S component of signature
+   out     DER-encoded ECDSA signature
+   outlen  [in/out] output buffer size, output signature size
+   return  MP_OKAY on success
+*/
+int wc_ecc_rs_to_sig(const char* r, const char* s, byte* out, word32* outlen)
+{
+    int err;
+    mp_int rtmp;
+    mp_int stmp;
+
+    if (r == NULL || s == NULL || out == NULL || outlen == NULL)
+        return ECC_BAD_ARG_E;
+
+    err = mp_init_multi(&rtmp, &stmp, NULL, NULL, NULL, NULL);
+    if (err != MP_OKAY)
+        return err;
+
+    err = mp_read_radix(&rtmp, r, 16);
+    if (err == MP_OKAY)
+        err = mp_read_radix(&stmp, s, 16);
+
+    /* convert mp_ints to ECDSA sig, initializes rtmp and stmp internally */
+    if (err == MP_OKAY)
+        err = StoreECC_DSA_Sig(out, outlen, &rtmp, &stmp);
+
+    if (err == MP_OKAY) {
+        if (mp_iszero(&rtmp) || mp_iszero(&stmp))
+            err = MP_ZERO_E;
+    }
+
+    mp_clear(&rtmp);
+    mp_clear(&stmp);
+
+    return err;
+}
+
+/**
+   Import raw ECC key
+   key       The destination ecc_key structure
+   qx        x component of base point, as ASCII hex string
+   qy        y component of base point, as ASCII hex string
+   d         private key, as ASCII hex string
+   curveName ECC curve name, from ecc_sets[]
+   return    MP_OKAY on success
+*/
+int wc_ecc_import_raw(ecc_key* key, const char* qx, const char* qy,
+                   const char* d, const char* curveName)
+{
+    int err, x;
+
+    if (key == NULL || qx == NULL || qy == NULL || d == NULL ||
+        curveName == NULL)
+        return ECC_BAD_ARG_E;
+
+    /* init key */
+#ifdef ALT_ECC_SIZE
+    key->pubkey.x = (mp_int*)&key->pubkey.xyz[0];
+    key->pubkey.y = (mp_int*)&key->pubkey.xyz[1];
+    key->pubkey.z = (mp_int*)&key->pubkey.xyz[2];
+    alt_fp_init(key->pubkey.x);
+    alt_fp_init(key->pubkey.y);
+    alt_fp_init(key->pubkey.z);
+    err = mp_init(&key->k);
+#else
+    err = mp_init_multi(key->pubkey.x, key->pubkey.y, key->pubkey.z, &key->k,
+                      NULL, NULL);
+#endif
+    if (err != MP_OKAY)
+        return MEMORY_E;
+
+    /* read Qx */
+    if (err == MP_OKAY)
+        err = mp_read_radix(key->pubkey.x, qx, 16);
+
+    /* read Qy */
+    if (err == MP_OKAY)
+        err = mp_read_radix(key->pubkey.y, qy, 16);
+
+    if (err == MP_OKAY)
+        mp_set(key->pubkey.z, 1);
+
+    /* read and set the curve */
+    if (err == MP_OKAY) {
+        for (x = 0; ecc_sets[x].size != 0; x++) {
+            if (XSTRNCMP(ecc_sets[x].name, curveName,
+                         XSTRLEN(curveName)) == 0) {
+                break;
+            }
+        }
+        if (ecc_sets[x].size == 0) {
+            err = ASN_PARSE_E;
+        } else {
+            /* set the curve */
+            key->idx = x;
+            key->dp = &ecc_sets[x];
+            key->type = ECC_PUBLICKEY;
+        }
+    }
+
+    /* import private key */
+    if (err == MP_OKAY) {
+        key->type = ECC_PRIVATEKEY;
+        err = mp_read_radix(&key->k, d, 16);
+    }
+
+#ifdef WOLFSSL_VALIDATE_ECC_IMPORT
+    if (err == MP_OKAY)
+        err = wc_ecc_check_key(key);
+#endif
+
+    if (err != MP_OKAY) {
+        mp_clear(key->pubkey.x);
+        mp_clear(key->pubkey.y);
+        mp_clear(key->pubkey.z);
+        mp_clear(&key->k);
+    }
+
+    return err;
+}
+
+
+/* key size in octets */
+int wc_ecc_size(ecc_key* key)
+{
+    if (key == NULL) return 0;
+
+    return key->dp->size;
+}
+
+
+/* worst case estimate, check actual return from wc_ecc_sign_hash for actual value
+   of signature size in octets */
+int wc_ecc_sig_size(ecc_key* key)
+{
+    int sz = wc_ecc_size(key);
+    if (sz <= 0)
+        return sz;
+
+    return sz * 2 + SIG_HEADER_SZ + 4;  /* (4) worst case estimate */
+}
+
+
+#ifdef FP_ECC
+
+/* fixed point ECC cache */
+/* number of entries in the cache */
+#ifndef FP_ENTRIES
+    #define FP_ENTRIES 16
+#endif
+
+/* number of bits in LUT */
+#ifndef FP_LUT
+    #define FP_LUT     8U
+#endif
+
+#ifdef ECC_SHAMIR
+    /* Sharmir requires a bigger LUT, TAO */
+    #if (FP_LUT > 12) || (FP_LUT < 4)
+        #error FP_LUT must be between 4 and 12 inclusively
+    #endif
+#else
+    #if (FP_LUT > 12) || (FP_LUT < 2)
+        #error FP_LUT must be between 2 and 12 inclusively
+    #endif
+#endif
+
+
+/** Our FP cache */
+typedef struct {
+   ecc_point* g;               /* cached COPY of base point */
+   ecc_point* LUT[1U< 6
+   { 1, 0, 0 }, { 2, 1, 64 }, { 2, 2, 64 }, { 3, 3, 64 }, { 2, 4, 64 }, { 3, 5, 64 }, { 3, 6, 64 }, { 4, 7, 64 }, 
+   { 2, 8, 64 }, { 3, 9, 64 }, { 3, 10, 64 }, { 4, 11, 64 }, { 3, 12, 64 }, { 4, 13, 64 }, { 4, 14, 64 }, { 5, 15, 64 }, 
+   { 2, 16, 64 }, { 3, 17, 64 }, { 3, 18, 64 }, { 4, 19, 64 }, { 3, 20, 64 }, { 4, 21, 64 }, { 4, 22, 64 }, { 5, 23, 64 }, 
+   { 3, 24, 64 }, { 4, 25, 64 }, { 4, 26, 64 }, { 5, 27, 64 }, { 4, 28, 64 }, { 5, 29, 64 }, { 5, 30, 64 }, { 6, 31, 64 }, 
+   { 2, 32, 64 }, { 3, 33, 64 }, { 3, 34, 64 }, { 4, 35, 64 }, { 3, 36, 64 }, { 4, 37, 64 }, { 4, 38, 64 }, { 5, 39, 64 }, 
+   { 3, 40, 64 }, { 4, 41, 64 }, { 4, 42, 64 }, { 5, 43, 64 }, { 4, 44, 64 }, { 5, 45, 64 }, { 5, 46, 64 }, { 6, 47, 64 }, 
+   { 3, 48, 64 }, { 4, 49, 64 }, { 4, 50, 64 }, { 5, 51, 64 }, { 4, 52, 64 }, { 5, 53, 64 }, { 5, 54, 64 }, { 6, 55, 64 }, 
+   { 4, 56, 64 }, { 5, 57, 64 }, { 5, 58, 64 }, { 6, 59, 64 }, { 5, 60, 64 }, { 6, 61, 64 }, { 6, 62, 64 }, { 7, 63, 64 }, 
+#if FP_LUT > 7
+   { 1, 0, 0 }, { 2, 1, 128 }, { 2, 2, 128 }, { 3, 3, 128 }, { 2, 4, 128 }, { 3, 5, 128 }, { 3, 6, 128 }, { 4, 7, 128 }, 
+   { 2, 8, 128 }, { 3, 9, 128 }, { 3, 10, 128 }, { 4, 11, 128 }, { 3, 12, 128 }, { 4, 13, 128 }, { 4, 14, 128 }, { 5, 15, 128 }, 
+   { 2, 16, 128 }, { 3, 17, 128 }, { 3, 18, 128 }, { 4, 19, 128 }, { 3, 20, 128 }, { 4, 21, 128 }, { 4, 22, 128 }, { 5, 23, 128 }, 
+   { 3, 24, 128 }, { 4, 25, 128 }, { 4, 26, 128 }, { 5, 27, 128 }, { 4, 28, 128 }, { 5, 29, 128 }, { 5, 30, 128 }, { 6, 31, 128 }, 
+   { 2, 32, 128 }, { 3, 33, 128 }, { 3, 34, 128 }, { 4, 35, 128 }, { 3, 36, 128 }, { 4, 37, 128 }, { 4, 38, 128 }, { 5, 39, 128 }, 
+   { 3, 40, 128 }, { 4, 41, 128 }, { 4, 42, 128 }, { 5, 43, 128 }, { 4, 44, 128 }, { 5, 45, 128 }, { 5, 46, 128 }, { 6, 47, 128 }, 
+   { 3, 48, 128 }, { 4, 49, 128 }, { 4, 50, 128 }, { 5, 51, 128 }, { 4, 52, 128 }, { 5, 53, 128 }, { 5, 54, 128 }, { 6, 55, 128 }, 
+   { 4, 56, 128 }, { 5, 57, 128 }, { 5, 58, 128 }, { 6, 59, 128 }, { 5, 60, 128 }, { 6, 61, 128 }, { 6, 62, 128 }, { 7, 63, 128 }, 
+   { 2, 64, 128 }, { 3, 65, 128 }, { 3, 66, 128 }, { 4, 67, 128 }, { 3, 68, 128 }, { 4, 69, 128 }, { 4, 70, 128 }, { 5, 71, 128 }, 
+   { 3, 72, 128 }, { 4, 73, 128 }, { 4, 74, 128 }, { 5, 75, 128 }, { 4, 76, 128 }, { 5, 77, 128 }, { 5, 78, 128 }, { 6, 79, 128 }, 
+   { 3, 80, 128 }, { 4, 81, 128 }, { 4, 82, 128 }, { 5, 83, 128 }, { 4, 84, 128 }, { 5, 85, 128 }, { 5, 86, 128 }, { 6, 87, 128 }, 
+   { 4, 88, 128 }, { 5, 89, 128 }, { 5, 90, 128 }, { 6, 91, 128 }, { 5, 92, 128 }, { 6, 93, 128 }, { 6, 94, 128 }, { 7, 95, 128 }, 
+   { 3, 96, 128 }, { 4, 97, 128 }, { 4, 98, 128 }, { 5, 99, 128 }, { 4, 100, 128 }, { 5, 101, 128 }, { 5, 102, 128 }, { 6, 103, 128 }, 
+   { 4, 104, 128 }, { 5, 105, 128 }, { 5, 106, 128 }, { 6, 107, 128 }, { 5, 108, 128 }, { 6, 109, 128 }, { 6, 110, 128 }, { 7, 111, 128 }, 
+   { 4, 112, 128 }, { 5, 113, 128 }, { 5, 114, 128 }, { 6, 115, 128 }, { 5, 116, 128 }, { 6, 117, 128 }, { 6, 118, 128 }, { 7, 119, 128 }, 
+   { 5, 120, 128 }, { 6, 121, 128 }, { 6, 122, 128 }, { 7, 123, 128 }, { 6, 124, 128 }, { 7, 125, 128 }, { 7, 126, 128 }, { 8, 127, 128 }, 
+#if FP_LUT > 8
+   { 1, 0, 0 }, { 2, 1, 256 }, { 2, 2, 256 }, { 3, 3, 256 }, { 2, 4, 256 }, { 3, 5, 256 }, { 3, 6, 256 }, { 4, 7, 256 }, 
+   { 2, 8, 256 }, { 3, 9, 256 }, { 3, 10, 256 }, { 4, 11, 256 }, { 3, 12, 256 }, { 4, 13, 256 }, { 4, 14, 256 }, { 5, 15, 256 }, 
+   { 2, 16, 256 }, { 3, 17, 256 }, { 3, 18, 256 }, { 4, 19, 256 }, { 3, 20, 256 }, { 4, 21, 256 }, { 4, 22, 256 }, { 5, 23, 256 }, 
+   { 3, 24, 256 }, { 4, 25, 256 }, { 4, 26, 256 }, { 5, 27, 256 }, { 4, 28, 256 }, { 5, 29, 256 }, { 5, 30, 256 }, { 6, 31, 256 }, 
+   { 2, 32, 256 }, { 3, 33, 256 }, { 3, 34, 256 }, { 4, 35, 256 }, { 3, 36, 256 }, { 4, 37, 256 }, { 4, 38, 256 }, { 5, 39, 256 }, 
+   { 3, 40, 256 }, { 4, 41, 256 }, { 4, 42, 256 }, { 5, 43, 256 }, { 4, 44, 256 }, { 5, 45, 256 }, { 5, 46, 256 }, { 6, 47, 256 }, 
+   { 3, 48, 256 }, { 4, 49, 256 }, { 4, 50, 256 }, { 5, 51, 256 }, { 4, 52, 256 }, { 5, 53, 256 }, { 5, 54, 256 }, { 6, 55, 256 }, 
+   { 4, 56, 256 }, { 5, 57, 256 }, { 5, 58, 256 }, { 6, 59, 256 }, { 5, 60, 256 }, { 6, 61, 256 }, { 6, 62, 256 }, { 7, 63, 256 }, 
+   { 2, 64, 256 }, { 3, 65, 256 }, { 3, 66, 256 }, { 4, 67, 256 }, { 3, 68, 256 }, { 4, 69, 256 }, { 4, 70, 256 }, { 5, 71, 256 }, 
+   { 3, 72, 256 }, { 4, 73, 256 }, { 4, 74, 256 }, { 5, 75, 256 }, { 4, 76, 256 }, { 5, 77, 256 }, { 5, 78, 256 }, { 6, 79, 256 }, 
+   { 3, 80, 256 }, { 4, 81, 256 }, { 4, 82, 256 }, { 5, 83, 256 }, { 4, 84, 256 }, { 5, 85, 256 }, { 5, 86, 256 }, { 6, 87, 256 }, 
+   { 4, 88, 256 }, { 5, 89, 256 }, { 5, 90, 256 }, { 6, 91, 256 }, { 5, 92, 256 }, { 6, 93, 256 }, { 6, 94, 256 }, { 7, 95, 256 }, 
+   { 3, 96, 256 }, { 4, 97, 256 }, { 4, 98, 256 }, { 5, 99, 256 }, { 4, 100, 256 }, { 5, 101, 256 }, { 5, 102, 256 }, { 6, 103, 256 }, 
+   { 4, 104, 256 }, { 5, 105, 256 }, { 5, 106, 256 }, { 6, 107, 256 }, { 5, 108, 256 }, { 6, 109, 256 }, { 6, 110, 256 }, { 7, 111, 256 }, 
+   { 4, 112, 256 }, { 5, 113, 256 }, { 5, 114, 256 }, { 6, 115, 256 }, { 5, 116, 256 }, { 6, 117, 256 }, { 6, 118, 256 }, { 7, 119, 256 }, 
+   { 5, 120, 256 }, { 6, 121, 256 }, { 6, 122, 256 }, { 7, 123, 256 }, { 6, 124, 256 }, { 7, 125, 256 }, { 7, 126, 256 }, { 8, 127, 256 }, 
+   { 2, 128, 256 }, { 3, 129, 256 }, { 3, 130, 256 }, { 4, 131, 256 }, { 3, 132, 256 }, { 4, 133, 256 }, { 4, 134, 256 }, { 5, 135, 256 }, 
+   { 3, 136, 256 }, { 4, 137, 256 }, { 4, 138, 256 }, { 5, 139, 256 }, { 4, 140, 256 }, { 5, 141, 256 }, { 5, 142, 256 }, { 6, 143, 256 }, 
+   { 3, 144, 256 }, { 4, 145, 256 }, { 4, 146, 256 }, { 5, 147, 256 }, { 4, 148, 256 }, { 5, 149, 256 }, { 5, 150, 256 }, { 6, 151, 256 }, 
+   { 4, 152, 256 }, { 5, 153, 256 }, { 5, 154, 256 }, { 6, 155, 256 }, { 5, 156, 256 }, { 6, 157, 256 }, { 6, 158, 256 }, { 7, 159, 256 }, 
+   { 3, 160, 256 }, { 4, 161, 256 }, { 4, 162, 256 }, { 5, 163, 256 }, { 4, 164, 256 }, { 5, 165, 256 }, { 5, 166, 256 }, { 6, 167, 256 }, 
+   { 4, 168, 256 }, { 5, 169, 256 }, { 5, 170, 256 }, { 6, 171, 256 }, { 5, 172, 256 }, { 6, 173, 256 }, { 6, 174, 256 }, { 7, 175, 256 }, 
+   { 4, 176, 256 }, { 5, 177, 256 }, { 5, 178, 256 }, { 6, 179, 256 }, { 5, 180, 256 }, { 6, 181, 256 }, { 6, 182, 256 }, { 7, 183, 256 }, 
+   { 5, 184, 256 }, { 6, 185, 256 }, { 6, 186, 256 }, { 7, 187, 256 }, { 6, 188, 256 }, { 7, 189, 256 }, { 7, 190, 256 }, { 8, 191, 256 }, 
+   { 3, 192, 256 }, { 4, 193, 256 }, { 4, 194, 256 }, { 5, 195, 256 }, { 4, 196, 256 }, { 5, 197, 256 }, { 5, 198, 256 }, { 6, 199, 256 }, 
+   { 4, 200, 256 }, { 5, 201, 256 }, { 5, 202, 256 }, { 6, 203, 256 }, { 5, 204, 256 }, { 6, 205, 256 }, { 6, 206, 256 }, { 7, 207, 256 }, 
+   { 4, 208, 256 }, { 5, 209, 256 }, { 5, 210, 256 }, { 6, 211, 256 }, { 5, 212, 256 }, { 6, 213, 256 }, { 6, 214, 256 }, { 7, 215, 256 }, 
+   { 5, 216, 256 }, { 6, 217, 256 }, { 6, 218, 256 }, { 7, 219, 256 }, { 6, 220, 256 }, { 7, 221, 256 }, { 7, 222, 256 }, { 8, 223, 256 }, 
+   { 4, 224, 256 }, { 5, 225, 256 }, { 5, 226, 256 }, { 6, 227, 256 }, { 5, 228, 256 }, { 6, 229, 256 }, { 6, 230, 256 }, { 7, 231, 256 }, 
+   { 5, 232, 256 }, { 6, 233, 256 }, { 6, 234, 256 }, { 7, 235, 256 }, { 6, 236, 256 }, { 7, 237, 256 }, { 7, 238, 256 }, { 8, 239, 256 }, 
+   { 5, 240, 256 }, { 6, 241, 256 }, { 6, 242, 256 }, { 7, 243, 256 }, { 6, 244, 256 }, { 7, 245, 256 }, { 7, 246, 256 }, { 8, 247, 256 }, 
+   { 6, 248, 256 }, { 7, 249, 256 }, { 7, 250, 256 }, { 8, 251, 256 }, { 7, 252, 256 }, { 8, 253, 256 }, { 8, 254, 256 }, { 9, 255, 256 }, 
+#if FP_LUT > 9
+   { 1, 0, 0 }, { 2, 1, 512 }, { 2, 2, 512 }, { 3, 3, 512 }, { 2, 4, 512 }, { 3, 5, 512 }, { 3, 6, 512 }, { 4, 7, 512 }, 
+   { 2, 8, 512 }, { 3, 9, 512 }, { 3, 10, 512 }, { 4, 11, 512 }, { 3, 12, 512 }, { 4, 13, 512 }, { 4, 14, 512 }, { 5, 15, 512 }, 
+   { 2, 16, 512 }, { 3, 17, 512 }, { 3, 18, 512 }, { 4, 19, 512 }, { 3, 20, 512 }, { 4, 21, 512 }, { 4, 22, 512 }, { 5, 23, 512 }, 
+   { 3, 24, 512 }, { 4, 25, 512 }, { 4, 26, 512 }, { 5, 27, 512 }, { 4, 28, 512 }, { 5, 29, 512 }, { 5, 30, 512 }, { 6, 31, 512 }, 
+   { 2, 32, 512 }, { 3, 33, 512 }, { 3, 34, 512 }, { 4, 35, 512 }, { 3, 36, 512 }, { 4, 37, 512 }, { 4, 38, 512 }, { 5, 39, 512 }, 
+   { 3, 40, 512 }, { 4, 41, 512 }, { 4, 42, 512 }, { 5, 43, 512 }, { 4, 44, 512 }, { 5, 45, 512 }, { 5, 46, 512 }, { 6, 47, 512 }, 
+   { 3, 48, 512 }, { 4, 49, 512 }, { 4, 50, 512 }, { 5, 51, 512 }, { 4, 52, 512 }, { 5, 53, 512 }, { 5, 54, 512 }, { 6, 55, 512 }, 
+   { 4, 56, 512 }, { 5, 57, 512 }, { 5, 58, 512 }, { 6, 59, 512 }, { 5, 60, 512 }, { 6, 61, 512 }, { 6, 62, 512 }, { 7, 63, 512 }, 
+   { 2, 64, 512 }, { 3, 65, 512 }, { 3, 66, 512 }, { 4, 67, 512 }, { 3, 68, 512 }, { 4, 69, 512 }, { 4, 70, 512 }, { 5, 71, 512 }, 
+   { 3, 72, 512 }, { 4, 73, 512 }, { 4, 74, 512 }, { 5, 75, 512 }, { 4, 76, 512 }, { 5, 77, 512 }, { 5, 78, 512 }, { 6, 79, 512 }, 
+   { 3, 80, 512 }, { 4, 81, 512 }, { 4, 82, 512 }, { 5, 83, 512 }, { 4, 84, 512 }, { 5, 85, 512 }, { 5, 86, 512 }, { 6, 87, 512 }, 
+   { 4, 88, 512 }, { 5, 89, 512 }, { 5, 90, 512 }, { 6, 91, 512 }, { 5, 92, 512 }, { 6, 93, 512 }, { 6, 94, 512 }, { 7, 95, 512 }, 
+   { 3, 96, 512 }, { 4, 97, 512 }, { 4, 98, 512 }, { 5, 99, 512 }, { 4, 100, 512 }, { 5, 101, 512 }, { 5, 102, 512 }, { 6, 103, 512 }, 
+   { 4, 104, 512 }, { 5, 105, 512 }, { 5, 106, 512 }, { 6, 107, 512 }, { 5, 108, 512 }, { 6, 109, 512 }, { 6, 110, 512 }, { 7, 111, 512 }, 
+   { 4, 112, 512 }, { 5, 113, 512 }, { 5, 114, 512 }, { 6, 115, 512 }, { 5, 116, 512 }, { 6, 117, 512 }, { 6, 118, 512 }, { 7, 119, 512 }, 
+   { 5, 120, 512 }, { 6, 121, 512 }, { 6, 122, 512 }, { 7, 123, 512 }, { 6, 124, 512 }, { 7, 125, 512 }, { 7, 126, 512 }, { 8, 127, 512 }, 
+   { 2, 128, 512 }, { 3, 129, 512 }, { 3, 130, 512 }, { 4, 131, 512 }, { 3, 132, 512 }, { 4, 133, 512 }, { 4, 134, 512 }, { 5, 135, 512 }, 
+   { 3, 136, 512 }, { 4, 137, 512 }, { 4, 138, 512 }, { 5, 139, 512 }, { 4, 140, 512 }, { 5, 141, 512 }, { 5, 142, 512 }, { 6, 143, 512 }, 
+   { 3, 144, 512 }, { 4, 145, 512 }, { 4, 146, 512 }, { 5, 147, 512 }, { 4, 148, 512 }, { 5, 149, 512 }, { 5, 150, 512 }, { 6, 151, 512 }, 
+   { 4, 152, 512 }, { 5, 153, 512 }, { 5, 154, 512 }, { 6, 155, 512 }, { 5, 156, 512 }, { 6, 157, 512 }, { 6, 158, 512 }, { 7, 159, 512 }, 
+   { 3, 160, 512 }, { 4, 161, 512 }, { 4, 162, 512 }, { 5, 163, 512 }, { 4, 164, 512 }, { 5, 165, 512 }, { 5, 166, 512 }, { 6, 167, 512 }, 
+   { 4, 168, 512 }, { 5, 169, 512 }, { 5, 170, 512 }, { 6, 171, 512 }, { 5, 172, 512 }, { 6, 173, 512 }, { 6, 174, 512 }, { 7, 175, 512 }, 
+   { 4, 176, 512 }, { 5, 177, 512 }, { 5, 178, 512 }, { 6, 179, 512 }, { 5, 180, 512 }, { 6, 181, 512 }, { 6, 182, 512 }, { 7, 183, 512 }, 
+   { 5, 184, 512 }, { 6, 185, 512 }, { 6, 186, 512 }, { 7, 187, 512 }, { 6, 188, 512 }, { 7, 189, 512 }, { 7, 190, 512 }, { 8, 191, 512 }, 
+   { 3, 192, 512 }, { 4, 193, 512 }, { 4, 194, 512 }, { 5, 195, 512 }, { 4, 196, 512 }, { 5, 197, 512 }, { 5, 198, 512 }, { 6, 199, 512 }, 
+   { 4, 200, 512 }, { 5, 201, 512 }, { 5, 202, 512 }, { 6, 203, 512 }, { 5, 204, 512 }, { 6, 205, 512 }, { 6, 206, 512 }, { 7, 207, 512 }, 
+   { 4, 208, 512 }, { 5, 209, 512 }, { 5, 210, 512 }, { 6, 211, 512 }, { 5, 212, 512 }, { 6, 213, 512 }, { 6, 214, 512 }, { 7, 215, 512 }, 
+   { 5, 216, 512 }, { 6, 217, 512 }, { 6, 218, 512 }, { 7, 219, 512 }, { 6, 220, 512 }, { 7, 221, 512 }, { 7, 222, 512 }, { 8, 223, 512 }, 
+   { 4, 224, 512 }, { 5, 225, 512 }, { 5, 226, 512 }, { 6, 227, 512 }, { 5, 228, 512 }, { 6, 229, 512 }, { 6, 230, 512 }, { 7, 231, 512 }, 
+   { 5, 232, 512 }, { 6, 233, 512 }, { 6, 234, 512 }, { 7, 235, 512 }, { 6, 236, 512 }, { 7, 237, 512 }, { 7, 238, 512 }, { 8, 239, 512 }, 
+   { 5, 240, 512 }, { 6, 241, 512 }, { 6, 242, 512 }, { 7, 243, 512 }, { 6, 244, 512 }, { 7, 245, 512 }, { 7, 246, 512 }, { 8, 247, 512 }, 
+   { 6, 248, 512 }, { 7, 249, 512 }, { 7, 250, 512 }, { 8, 251, 512 }, { 7, 252, 512 }, { 8, 253, 512 }, { 8, 254, 512 }, { 9, 255, 512 }, 
+   { 2, 256, 512 }, { 3, 257, 512 }, { 3, 258, 512 }, { 4, 259, 512 }, { 3, 260, 512 }, { 4, 261, 512 }, { 4, 262, 512 }, { 5, 263, 512 }, 
+   { 3, 264, 512 }, { 4, 265, 512 }, { 4, 266, 512 }, { 5, 267, 512 }, { 4, 268, 512 }, { 5, 269, 512 }, { 5, 270, 512 }, { 6, 271, 512 }, 
+   { 3, 272, 512 }, { 4, 273, 512 }, { 4, 274, 512 }, { 5, 275, 512 }, { 4, 276, 512 }, { 5, 277, 512 }, { 5, 278, 512 }, { 6, 279, 512 }, 
+   { 4, 280, 512 }, { 5, 281, 512 }, { 5, 282, 512 }, { 6, 283, 512 }, { 5, 284, 512 }, { 6, 285, 512 }, { 6, 286, 512 }, { 7, 287, 512 }, 
+   { 3, 288, 512 }, { 4, 289, 512 }, { 4, 290, 512 }, { 5, 291, 512 }, { 4, 292, 512 }, { 5, 293, 512 }, { 5, 294, 512 }, { 6, 295, 512 }, 
+   { 4, 296, 512 }, { 5, 297, 512 }, { 5, 298, 512 }, { 6, 299, 512 }, { 5, 300, 512 }, { 6, 301, 512 }, { 6, 302, 512 }, { 7, 303, 512 }, 
+   { 4, 304, 512 }, { 5, 305, 512 }, { 5, 306, 512 }, { 6, 307, 512 }, { 5, 308, 512 }, { 6, 309, 512 }, { 6, 310, 512 }, { 7, 311, 512 }, 
+   { 5, 312, 512 }, { 6, 313, 512 }, { 6, 314, 512 }, { 7, 315, 512 }, { 6, 316, 512 }, { 7, 317, 512 }, { 7, 318, 512 }, { 8, 319, 512 }, 
+   { 3, 320, 512 }, { 4, 321, 512 }, { 4, 322, 512 }, { 5, 323, 512 }, { 4, 324, 512 }, { 5, 325, 512 }, { 5, 326, 512 }, { 6, 327, 512 }, 
+   { 4, 328, 512 }, { 5, 329, 512 }, { 5, 330, 512 }, { 6, 331, 512 }, { 5, 332, 512 }, { 6, 333, 512 }, { 6, 334, 512 }, { 7, 335, 512 }, 
+   { 4, 336, 512 }, { 5, 337, 512 }, { 5, 338, 512 }, { 6, 339, 512 }, { 5, 340, 512 }, { 6, 341, 512 }, { 6, 342, 512 }, { 7, 343, 512 }, 
+   { 5, 344, 512 }, { 6, 345, 512 }, { 6, 346, 512 }, { 7, 347, 512 }, { 6, 348, 512 }, { 7, 349, 512 }, { 7, 350, 512 }, { 8, 351, 512 }, 
+   { 4, 352, 512 }, { 5, 353, 512 }, { 5, 354, 512 }, { 6, 355, 512 }, { 5, 356, 512 }, { 6, 357, 512 }, { 6, 358, 512 }, { 7, 359, 512 }, 
+   { 5, 360, 512 }, { 6, 361, 512 }, { 6, 362, 512 }, { 7, 363, 512 }, { 6, 364, 512 }, { 7, 365, 512 }, { 7, 366, 512 }, { 8, 367, 512 }, 
+   { 5, 368, 512 }, { 6, 369, 512 }, { 6, 370, 512 }, { 7, 371, 512 }, { 6, 372, 512 }, { 7, 373, 512 }, { 7, 374, 512 }, { 8, 375, 512 }, 
+   { 6, 376, 512 }, { 7, 377, 512 }, { 7, 378, 512 }, { 8, 379, 512 }, { 7, 380, 512 }, { 8, 381, 512 }, { 8, 382, 512 }, { 9, 383, 512 }, 
+   { 3, 384, 512 }, { 4, 385, 512 }, { 4, 386, 512 }, { 5, 387, 512 }, { 4, 388, 512 }, { 5, 389, 512 }, { 5, 390, 512 }, { 6, 391, 512 }, 
+   { 4, 392, 512 }, { 5, 393, 512 }, { 5, 394, 512 }, { 6, 395, 512 }, { 5, 396, 512 }, { 6, 397, 512 }, { 6, 398, 512 }, { 7, 399, 512 }, 
+   { 4, 400, 512 }, { 5, 401, 512 }, { 5, 402, 512 }, { 6, 403, 512 }, { 5, 404, 512 }, { 6, 405, 512 }, { 6, 406, 512 }, { 7, 407, 512 }, 
+   { 5, 408, 512 }, { 6, 409, 512 }, { 6, 410, 512 }, { 7, 411, 512 }, { 6, 412, 512 }, { 7, 413, 512 }, { 7, 414, 512 }, { 8, 415, 512 }, 
+   { 4, 416, 512 }, { 5, 417, 512 }, { 5, 418, 512 }, { 6, 419, 512 }, { 5, 420, 512 }, { 6, 421, 512 }, { 6, 422, 512 }, { 7, 423, 512 }, 
+   { 5, 424, 512 }, { 6, 425, 512 }, { 6, 426, 512 }, { 7, 427, 512 }, { 6, 428, 512 }, { 7, 429, 512 }, { 7, 430, 512 }, { 8, 431, 512 }, 
+   { 5, 432, 512 }, { 6, 433, 512 }, { 6, 434, 512 }, { 7, 435, 512 }, { 6, 436, 512 }, { 7, 437, 512 }, { 7, 438, 512 }, { 8, 439, 512 }, 
+   { 6, 440, 512 }, { 7, 441, 512 }, { 7, 442, 512 }, { 8, 443, 512 }, { 7, 444, 512 }, { 8, 445, 512 }, { 8, 446, 512 }, { 9, 447, 512 }, 
+   { 4, 448, 512 }, { 5, 449, 512 }, { 5, 450, 512 }, { 6, 451, 512 }, { 5, 452, 512 }, { 6, 453, 512 }, { 6, 454, 512 }, { 7, 455, 512 }, 
+   { 5, 456, 512 }, { 6, 457, 512 }, { 6, 458, 512 }, { 7, 459, 512 }, { 6, 460, 512 }, { 7, 461, 512 }, { 7, 462, 512 }, { 8, 463, 512 }, 
+   { 5, 464, 512 }, { 6, 465, 512 }, { 6, 466, 512 }, { 7, 467, 512 }, { 6, 468, 512 }, { 7, 469, 512 }, { 7, 470, 512 }, { 8, 471, 512 }, 
+   { 6, 472, 512 }, { 7, 473, 512 }, { 7, 474, 512 }, { 8, 475, 512 }, { 7, 476, 512 }, { 8, 477, 512 }, { 8, 478, 512 }, { 9, 479, 512 }, 
+   { 5, 480, 512 }, { 6, 481, 512 }, { 6, 482, 512 }, { 7, 483, 512 }, { 6, 484, 512 }, { 7, 485, 512 }, { 7, 486, 512 }, { 8, 487, 512 }, 
+   { 6, 488, 512 }, { 7, 489, 512 }, { 7, 490, 512 }, { 8, 491, 512 }, { 7, 492, 512 }, { 8, 493, 512 }, { 8, 494, 512 }, { 9, 495, 512 }, 
+   { 6, 496, 512 }, { 7, 497, 512 }, { 7, 498, 512 }, { 8, 499, 512 }, { 7, 500, 512 }, { 8, 501, 512 }, { 8, 502, 512 }, { 9, 503, 512 }, 
+   { 7, 504, 512 }, { 8, 505, 512 }, { 8, 506, 512 }, { 9, 507, 512 }, { 8, 508, 512 }, { 9, 509, 512 }, { 9, 510, 512 }, { 10, 511, 512 }, 
+#if FP_LUT > 10
+   { 1, 0, 0 }, { 2, 1, 1024 }, { 2, 2, 1024 }, { 3, 3, 1024 }, { 2, 4, 1024 }, { 3, 5, 1024 }, { 3, 6, 1024 }, { 4, 7, 1024 }, 
+   { 2, 8, 1024 }, { 3, 9, 1024 }, { 3, 10, 1024 }, { 4, 11, 1024 }, { 3, 12, 1024 }, { 4, 13, 1024 }, { 4, 14, 1024 }, { 5, 15, 1024 }, 
+   { 2, 16, 1024 }, { 3, 17, 1024 }, { 3, 18, 1024 }, { 4, 19, 1024 }, { 3, 20, 1024 }, { 4, 21, 1024 }, { 4, 22, 1024 }, { 5, 23, 1024 }, 
+   { 3, 24, 1024 }, { 4, 25, 1024 }, { 4, 26, 1024 }, { 5, 27, 1024 }, { 4, 28, 1024 }, { 5, 29, 1024 }, { 5, 30, 1024 }, { 6, 31, 1024 }, 
+   { 2, 32, 1024 }, { 3, 33, 1024 }, { 3, 34, 1024 }, { 4, 35, 1024 }, { 3, 36, 1024 }, { 4, 37, 1024 }, { 4, 38, 1024 }, { 5, 39, 1024 }, 
+   { 3, 40, 1024 }, { 4, 41, 1024 }, { 4, 42, 1024 }, { 5, 43, 1024 }, { 4, 44, 1024 }, { 5, 45, 1024 }, { 5, 46, 1024 }, { 6, 47, 1024 }, 
+   { 3, 48, 1024 }, { 4, 49, 1024 }, { 4, 50, 1024 }, { 5, 51, 1024 }, { 4, 52, 1024 }, { 5, 53, 1024 }, { 5, 54, 1024 }, { 6, 55, 1024 }, 
+   { 4, 56, 1024 }, { 5, 57, 1024 }, { 5, 58, 1024 }, { 6, 59, 1024 }, { 5, 60, 1024 }, { 6, 61, 1024 }, { 6, 62, 1024 }, { 7, 63, 1024 }, 
+   { 2, 64, 1024 }, { 3, 65, 1024 }, { 3, 66, 1024 }, { 4, 67, 1024 }, { 3, 68, 1024 }, { 4, 69, 1024 }, { 4, 70, 1024 }, { 5, 71, 1024 }, 
+   { 3, 72, 1024 }, { 4, 73, 1024 }, { 4, 74, 1024 }, { 5, 75, 1024 }, { 4, 76, 1024 }, { 5, 77, 1024 }, { 5, 78, 1024 }, { 6, 79, 1024 }, 
+   { 3, 80, 1024 }, { 4, 81, 1024 }, { 4, 82, 1024 }, { 5, 83, 1024 }, { 4, 84, 1024 }, { 5, 85, 1024 }, { 5, 86, 1024 }, { 6, 87, 1024 }, 
+   { 4, 88, 1024 }, { 5, 89, 1024 }, { 5, 90, 1024 }, { 6, 91, 1024 }, { 5, 92, 1024 }, { 6, 93, 1024 }, { 6, 94, 1024 }, { 7, 95, 1024 }, 
+   { 3, 96, 1024 }, { 4, 97, 1024 }, { 4, 98, 1024 }, { 5, 99, 1024 }, { 4, 100, 1024 }, { 5, 101, 1024 }, { 5, 102, 1024 }, { 6, 103, 1024 }, 
+   { 4, 104, 1024 }, { 5, 105, 1024 }, { 5, 106, 1024 }, { 6, 107, 1024 }, { 5, 108, 1024 }, { 6, 109, 1024 }, { 6, 110, 1024 }, { 7, 111, 1024 }, 
+   { 4, 112, 1024 }, { 5, 113, 1024 }, { 5, 114, 1024 }, { 6, 115, 1024 }, { 5, 116, 1024 }, { 6, 117, 1024 }, { 6, 118, 1024 }, { 7, 119, 1024 }, 
+   { 5, 120, 1024 }, { 6, 121, 1024 }, { 6, 122, 1024 }, { 7, 123, 1024 }, { 6, 124, 1024 }, { 7, 125, 1024 }, { 7, 126, 1024 }, { 8, 127, 1024 }, 
+   { 2, 128, 1024 }, { 3, 129, 1024 }, { 3, 130, 1024 }, { 4, 131, 1024 }, { 3, 132, 1024 }, { 4, 133, 1024 }, { 4, 134, 1024 }, { 5, 135, 1024 }, 
+   { 3, 136, 1024 }, { 4, 137, 1024 }, { 4, 138, 1024 }, { 5, 139, 1024 }, { 4, 140, 1024 }, { 5, 141, 1024 }, { 5, 142, 1024 }, { 6, 143, 1024 }, 
+   { 3, 144, 1024 }, { 4, 145, 1024 }, { 4, 146, 1024 }, { 5, 147, 1024 }, { 4, 148, 1024 }, { 5, 149, 1024 }, { 5, 150, 1024 }, { 6, 151, 1024 }, 
+   { 4, 152, 1024 }, { 5, 153, 1024 }, { 5, 154, 1024 }, { 6, 155, 1024 }, { 5, 156, 1024 }, { 6, 157, 1024 }, { 6, 158, 1024 }, { 7, 159, 1024 }, 
+   { 3, 160, 1024 }, { 4, 161, 1024 }, { 4, 162, 1024 }, { 5, 163, 1024 }, { 4, 164, 1024 }, { 5, 165, 1024 }, { 5, 166, 1024 }, { 6, 167, 1024 }, 
+   { 4, 168, 1024 }, { 5, 169, 1024 }, { 5, 170, 1024 }, { 6, 171, 1024 }, { 5, 172, 1024 }, { 6, 173, 1024 }, { 6, 174, 1024 }, { 7, 175, 1024 }, 
+   { 4, 176, 1024 }, { 5, 177, 1024 }, { 5, 178, 1024 }, { 6, 179, 1024 }, { 5, 180, 1024 }, { 6, 181, 1024 }, { 6, 182, 1024 }, { 7, 183, 1024 }, 
+   { 5, 184, 1024 }, { 6, 185, 1024 }, { 6, 186, 1024 }, { 7, 187, 1024 }, { 6, 188, 1024 }, { 7, 189, 1024 }, { 7, 190, 1024 }, { 8, 191, 1024 }, 
+   { 3, 192, 1024 }, { 4, 193, 1024 }, { 4, 194, 1024 }, { 5, 195, 1024 }, { 4, 196, 1024 }, { 5, 197, 1024 }, { 5, 198, 1024 }, { 6, 199, 1024 }, 
+   { 4, 200, 1024 }, { 5, 201, 1024 }, { 5, 202, 1024 }, { 6, 203, 1024 }, { 5, 204, 1024 }, { 6, 205, 1024 }, { 6, 206, 1024 }, { 7, 207, 1024 }, 
+   { 4, 208, 1024 }, { 5, 209, 1024 }, { 5, 210, 1024 }, { 6, 211, 1024 }, { 5, 212, 1024 }, { 6, 213, 1024 }, { 6, 214, 1024 }, { 7, 215, 1024 }, 
+   { 5, 216, 1024 }, { 6, 217, 1024 }, { 6, 218, 1024 }, { 7, 219, 1024 }, { 6, 220, 1024 }, { 7, 221, 1024 }, { 7, 222, 1024 }, { 8, 223, 1024 }, 
+   { 4, 224, 1024 }, { 5, 225, 1024 }, { 5, 226, 1024 }, { 6, 227, 1024 }, { 5, 228, 1024 }, { 6, 229, 1024 }, { 6, 230, 1024 }, { 7, 231, 1024 }, 
+   { 5, 232, 1024 }, { 6, 233, 1024 }, { 6, 234, 1024 }, { 7, 235, 1024 }, { 6, 236, 1024 }, { 7, 237, 1024 }, { 7, 238, 1024 }, { 8, 239, 1024 }, 
+   { 5, 240, 1024 }, { 6, 241, 1024 }, { 6, 242, 1024 }, { 7, 243, 1024 }, { 6, 244, 1024 }, { 7, 245, 1024 }, { 7, 246, 1024 }, { 8, 247, 1024 }, 
+   { 6, 248, 1024 }, { 7, 249, 1024 }, { 7, 250, 1024 }, { 8, 251, 1024 }, { 7, 252, 1024 }, { 8, 253, 1024 }, { 8, 254, 1024 }, { 9, 255, 1024 }, 
+   { 2, 256, 1024 }, { 3, 257, 1024 }, { 3, 258, 1024 }, { 4, 259, 1024 }, { 3, 260, 1024 }, { 4, 261, 1024 }, { 4, 262, 1024 }, { 5, 263, 1024 }, 
+   { 3, 264, 1024 }, { 4, 265, 1024 }, { 4, 266, 1024 }, { 5, 267, 1024 }, { 4, 268, 1024 }, { 5, 269, 1024 }, { 5, 270, 1024 }, { 6, 271, 1024 }, 
+   { 3, 272, 1024 }, { 4, 273, 1024 }, { 4, 274, 1024 }, { 5, 275, 1024 }, { 4, 276, 1024 }, { 5, 277, 1024 }, { 5, 278, 1024 }, { 6, 279, 1024 }, 
+   { 4, 280, 1024 }, { 5, 281, 1024 }, { 5, 282, 1024 }, { 6, 283, 1024 }, { 5, 284, 1024 }, { 6, 285, 1024 }, { 6, 286, 1024 }, { 7, 287, 1024 }, 
+   { 3, 288, 1024 }, { 4, 289, 1024 }, { 4, 290, 1024 }, { 5, 291, 1024 }, { 4, 292, 1024 }, { 5, 293, 1024 }, { 5, 294, 1024 }, { 6, 295, 1024 }, 
+   { 4, 296, 1024 }, { 5, 297, 1024 }, { 5, 298, 1024 }, { 6, 299, 1024 }, { 5, 300, 1024 }, { 6, 301, 1024 }, { 6, 302, 1024 }, { 7, 303, 1024 }, 
+   { 4, 304, 1024 }, { 5, 305, 1024 }, { 5, 306, 1024 }, { 6, 307, 1024 }, { 5, 308, 1024 }, { 6, 309, 1024 }, { 6, 310, 1024 }, { 7, 311, 1024 }, 
+   { 5, 312, 1024 }, { 6, 313, 1024 }, { 6, 314, 1024 }, { 7, 315, 1024 }, { 6, 316, 1024 }, { 7, 317, 1024 }, { 7, 318, 1024 }, { 8, 319, 1024 }, 
+   { 3, 320, 1024 }, { 4, 321, 1024 }, { 4, 322, 1024 }, { 5, 323, 1024 }, { 4, 324, 1024 }, { 5, 325, 1024 }, { 5, 326, 1024 }, { 6, 327, 1024 }, 
+   { 4, 328, 1024 }, { 5, 329, 1024 }, { 5, 330, 1024 }, { 6, 331, 1024 }, { 5, 332, 1024 }, { 6, 333, 1024 }, { 6, 334, 1024 }, { 7, 335, 1024 }, 
+   { 4, 336, 1024 }, { 5, 337, 1024 }, { 5, 338, 1024 }, { 6, 339, 1024 }, { 5, 340, 1024 }, { 6, 341, 1024 }, { 6, 342, 1024 }, { 7, 343, 1024 }, 
+   { 5, 344, 1024 }, { 6, 345, 1024 }, { 6, 346, 1024 }, { 7, 347, 1024 }, { 6, 348, 1024 }, { 7, 349, 1024 }, { 7, 350, 1024 }, { 8, 351, 1024 }, 
+   { 4, 352, 1024 }, { 5, 353, 1024 }, { 5, 354, 1024 }, { 6, 355, 1024 }, { 5, 356, 1024 }, { 6, 357, 1024 }, { 6, 358, 1024 }, { 7, 359, 1024 }, 
+   { 5, 360, 1024 }, { 6, 361, 1024 }, { 6, 362, 1024 }, { 7, 363, 1024 }, { 6, 364, 1024 }, { 7, 365, 1024 }, { 7, 366, 1024 }, { 8, 367, 1024 }, 
+   { 5, 368, 1024 }, { 6, 369, 1024 }, { 6, 370, 1024 }, { 7, 371, 1024 }, { 6, 372, 1024 }, { 7, 373, 1024 }, { 7, 374, 1024 }, { 8, 375, 1024 }, 
+   { 6, 376, 1024 }, { 7, 377, 1024 }, { 7, 378, 1024 }, { 8, 379, 1024 }, { 7, 380, 1024 }, { 8, 381, 1024 }, { 8, 382, 1024 }, { 9, 383, 1024 }, 
+   { 3, 384, 1024 }, { 4, 385, 1024 }, { 4, 386, 1024 }, { 5, 387, 1024 }, { 4, 388, 1024 }, { 5, 389, 1024 }, { 5, 390, 1024 }, { 6, 391, 1024 }, 
+   { 4, 392, 1024 }, { 5, 393, 1024 }, { 5, 394, 1024 }, { 6, 395, 1024 }, { 5, 396, 1024 }, { 6, 397, 1024 }, { 6, 398, 1024 }, { 7, 399, 1024 }, 
+   { 4, 400, 1024 }, { 5, 401, 1024 }, { 5, 402, 1024 }, { 6, 403, 1024 }, { 5, 404, 1024 }, { 6, 405, 1024 }, { 6, 406, 1024 }, { 7, 407, 1024 }, 
+   { 5, 408, 1024 }, { 6, 409, 1024 }, { 6, 410, 1024 }, { 7, 411, 1024 }, { 6, 412, 1024 }, { 7, 413, 1024 }, { 7, 414, 1024 }, { 8, 415, 1024 }, 
+   { 4, 416, 1024 }, { 5, 417, 1024 }, { 5, 418, 1024 }, { 6, 419, 1024 }, { 5, 420, 1024 }, { 6, 421, 1024 }, { 6, 422, 1024 }, { 7, 423, 1024 }, 
+   { 5, 424, 1024 }, { 6, 425, 1024 }, { 6, 426, 1024 }, { 7, 427, 1024 }, { 6, 428, 1024 }, { 7, 429, 1024 }, { 7, 430, 1024 }, { 8, 431, 1024 }, 
+   { 5, 432, 1024 }, { 6, 433, 1024 }, { 6, 434, 1024 }, { 7, 435, 1024 }, { 6, 436, 1024 }, { 7, 437, 1024 }, { 7, 438, 1024 }, { 8, 439, 1024 }, 
+   { 6, 440, 1024 }, { 7, 441, 1024 }, { 7, 442, 1024 }, { 8, 443, 1024 }, { 7, 444, 1024 }, { 8, 445, 1024 }, { 8, 446, 1024 }, { 9, 447, 1024 }, 
+   { 4, 448, 1024 }, { 5, 449, 1024 }, { 5, 450, 1024 }, { 6, 451, 1024 }, { 5, 452, 1024 }, { 6, 453, 1024 }, { 6, 454, 1024 }, { 7, 455, 1024 }, 
+   { 5, 456, 1024 }, { 6, 457, 1024 }, { 6, 458, 1024 }, { 7, 459, 1024 }, { 6, 460, 1024 }, { 7, 461, 1024 }, { 7, 462, 1024 }, { 8, 463, 1024 }, 
+   { 5, 464, 1024 }, { 6, 465, 1024 }, { 6, 466, 1024 }, { 7, 467, 1024 }, { 6, 468, 1024 }, { 7, 469, 1024 }, { 7, 470, 1024 }, { 8, 471, 1024 }, 
+   { 6, 472, 1024 }, { 7, 473, 1024 }, { 7, 474, 1024 }, { 8, 475, 1024 }, { 7, 476, 1024 }, { 8, 477, 1024 }, { 8, 478, 1024 }, { 9, 479, 1024 }, 
+   { 5, 480, 1024 }, { 6, 481, 1024 }, { 6, 482, 1024 }, { 7, 483, 1024 }, { 6, 484, 1024 }, { 7, 485, 1024 }, { 7, 486, 1024 }, { 8, 487, 1024 }, 
+   { 6, 488, 1024 }, { 7, 489, 1024 }, { 7, 490, 1024 }, { 8, 491, 1024 }, { 7, 492, 1024 }, { 8, 493, 1024 }, { 8, 494, 1024 }, { 9, 495, 1024 }, 
+   { 6, 496, 1024 }, { 7, 497, 1024 }, { 7, 498, 1024 }, { 8, 499, 1024 }, { 7, 500, 1024 }, { 8, 501, 1024 }, { 8, 502, 1024 }, { 9, 503, 1024 }, 
+   { 7, 504, 1024 }, { 8, 505, 1024 }, { 8, 506, 1024 }, { 9, 507, 1024 }, { 8, 508, 1024 }, { 9, 509, 1024 }, { 9, 510, 1024 }, { 10, 511, 1024 }, 
+   { 2, 512, 1024 }, { 3, 513, 1024 }, { 3, 514, 1024 }, { 4, 515, 1024 }, { 3, 516, 1024 }, { 4, 517, 1024 }, { 4, 518, 1024 }, { 5, 519, 1024 }, 
+   { 3, 520, 1024 }, { 4, 521, 1024 }, { 4, 522, 1024 }, { 5, 523, 1024 }, { 4, 524, 1024 }, { 5, 525, 1024 }, { 5, 526, 1024 }, { 6, 527, 1024 }, 
+   { 3, 528, 1024 }, { 4, 529, 1024 }, { 4, 530, 1024 }, { 5, 531, 1024 }, { 4, 532, 1024 }, { 5, 533, 1024 }, { 5, 534, 1024 }, { 6, 535, 1024 }, 
+   { 4, 536, 1024 }, { 5, 537, 1024 }, { 5, 538, 1024 }, { 6, 539, 1024 }, { 5, 540, 1024 }, { 6, 541, 1024 }, { 6, 542, 1024 }, { 7, 543, 1024 }, 
+   { 3, 544, 1024 }, { 4, 545, 1024 }, { 4, 546, 1024 }, { 5, 547, 1024 }, { 4, 548, 1024 }, { 5, 549, 1024 }, { 5, 550, 1024 }, { 6, 551, 1024 }, 
+   { 4, 552, 1024 }, { 5, 553, 1024 }, { 5, 554, 1024 }, { 6, 555, 1024 }, { 5, 556, 1024 }, { 6, 557, 1024 }, { 6, 558, 1024 }, { 7, 559, 1024 }, 
+   { 4, 560, 1024 }, { 5, 561, 1024 }, { 5, 562, 1024 }, { 6, 563, 1024 }, { 5, 564, 1024 }, { 6, 565, 1024 }, { 6, 566, 1024 }, { 7, 567, 1024 }, 
+   { 5, 568, 1024 }, { 6, 569, 1024 }, { 6, 570, 1024 }, { 7, 571, 1024 }, { 6, 572, 1024 }, { 7, 573, 1024 }, { 7, 574, 1024 }, { 8, 575, 1024 }, 
+   { 3, 576, 1024 }, { 4, 577, 1024 }, { 4, 578, 1024 }, { 5, 579, 1024 }, { 4, 580, 1024 }, { 5, 581, 1024 }, { 5, 582, 1024 }, { 6, 583, 1024 }, 
+   { 4, 584, 1024 }, { 5, 585, 1024 }, { 5, 586, 1024 }, { 6, 587, 1024 }, { 5, 588, 1024 }, { 6, 589, 1024 }, { 6, 590, 1024 }, { 7, 591, 1024 }, 
+   { 4, 592, 1024 }, { 5, 593, 1024 }, { 5, 594, 1024 }, { 6, 595, 1024 }, { 5, 596, 1024 }, { 6, 597, 1024 }, { 6, 598, 1024 }, { 7, 599, 1024 }, 
+   { 5, 600, 1024 }, { 6, 601, 1024 }, { 6, 602, 1024 }, { 7, 603, 1024 }, { 6, 604, 1024 }, { 7, 605, 1024 }, { 7, 606, 1024 }, { 8, 607, 1024 }, 
+   { 4, 608, 1024 }, { 5, 609, 1024 }, { 5, 610, 1024 }, { 6, 611, 1024 }, { 5, 612, 1024 }, { 6, 613, 1024 }, { 6, 614, 1024 }, { 7, 615, 1024 }, 
+   { 5, 616, 1024 }, { 6, 617, 1024 }, { 6, 618, 1024 }, { 7, 619, 1024 }, { 6, 620, 1024 }, { 7, 621, 1024 }, { 7, 622, 1024 }, { 8, 623, 1024 }, 
+   { 5, 624, 1024 }, { 6, 625, 1024 }, { 6, 626, 1024 }, { 7, 627, 1024 }, { 6, 628, 1024 }, { 7, 629, 1024 }, { 7, 630, 1024 }, { 8, 631, 1024 }, 
+   { 6, 632, 1024 }, { 7, 633, 1024 }, { 7, 634, 1024 }, { 8, 635, 1024 }, { 7, 636, 1024 }, { 8, 637, 1024 }, { 8, 638, 1024 }, { 9, 639, 1024 }, 
+   { 3, 640, 1024 }, { 4, 641, 1024 }, { 4, 642, 1024 }, { 5, 643, 1024 }, { 4, 644, 1024 }, { 5, 645, 1024 }, { 5, 646, 1024 }, { 6, 647, 1024 }, 
+   { 4, 648, 1024 }, { 5, 649, 1024 }, { 5, 650, 1024 }, { 6, 651, 1024 }, { 5, 652, 1024 }, { 6, 653, 1024 }, { 6, 654, 1024 }, { 7, 655, 1024 }, 
+   { 4, 656, 1024 }, { 5, 657, 1024 }, { 5, 658, 1024 }, { 6, 659, 1024 }, { 5, 660, 1024 }, { 6, 661, 1024 }, { 6, 662, 1024 }, { 7, 663, 1024 }, 
+   { 5, 664, 1024 }, { 6, 665, 1024 }, { 6, 666, 1024 }, { 7, 667, 1024 }, { 6, 668, 1024 }, { 7, 669, 1024 }, { 7, 670, 1024 }, { 8, 671, 1024 }, 
+   { 4, 672, 1024 }, { 5, 673, 1024 }, { 5, 674, 1024 }, { 6, 675, 1024 }, { 5, 676, 1024 }, { 6, 677, 1024 }, { 6, 678, 1024 }, { 7, 679, 1024 }, 
+   { 5, 680, 1024 }, { 6, 681, 1024 }, { 6, 682, 1024 }, { 7, 683, 1024 }, { 6, 684, 1024 }, { 7, 685, 1024 }, { 7, 686, 1024 }, { 8, 687, 1024 }, 
+   { 5, 688, 1024 }, { 6, 689, 1024 }, { 6, 690, 1024 }, { 7, 691, 1024 }, { 6, 692, 1024 }, { 7, 693, 1024 }, { 7, 694, 1024 }, { 8, 695, 1024 }, 
+   { 6, 696, 1024 }, { 7, 697, 1024 }, { 7, 698, 1024 }, { 8, 699, 1024 }, { 7, 700, 1024 }, { 8, 701, 1024 }, { 8, 702, 1024 }, { 9, 703, 1024 }, 
+   { 4, 704, 1024 }, { 5, 705, 1024 }, { 5, 706, 1024 }, { 6, 707, 1024 }, { 5, 708, 1024 }, { 6, 709, 1024 }, { 6, 710, 1024 }, { 7, 711, 1024 }, 
+   { 5, 712, 1024 }, { 6, 713, 1024 }, { 6, 714, 1024 }, { 7, 715, 1024 }, { 6, 716, 1024 }, { 7, 717, 1024 }, { 7, 718, 1024 }, { 8, 719, 1024 }, 
+   { 5, 720, 1024 }, { 6, 721, 1024 }, { 6, 722, 1024 }, { 7, 723, 1024 }, { 6, 724, 1024 }, { 7, 725, 1024 }, { 7, 726, 1024 }, { 8, 727, 1024 }, 
+   { 6, 728, 1024 }, { 7, 729, 1024 }, { 7, 730, 1024 }, { 8, 731, 1024 }, { 7, 732, 1024 }, { 8, 733, 1024 }, { 8, 734, 1024 }, { 9, 735, 1024 }, 
+   { 5, 736, 1024 }, { 6, 737, 1024 }, { 6, 738, 1024 }, { 7, 739, 1024 }, { 6, 740, 1024 }, { 7, 741, 1024 }, { 7, 742, 1024 }, { 8, 743, 1024 }, 
+   { 6, 744, 1024 }, { 7, 745, 1024 }, { 7, 746, 1024 }, { 8, 747, 1024 }, { 7, 748, 1024 }, { 8, 749, 1024 }, { 8, 750, 1024 }, { 9, 751, 1024 }, 
+   { 6, 752, 1024 }, { 7, 753, 1024 }, { 7, 754, 1024 }, { 8, 755, 1024 }, { 7, 756, 1024 }, { 8, 757, 1024 }, { 8, 758, 1024 }, { 9, 759, 1024 }, 
+   { 7, 760, 1024 }, { 8, 761, 1024 }, { 8, 762, 1024 }, { 9, 763, 1024 }, { 8, 764, 1024 }, { 9, 765, 1024 }, { 9, 766, 1024 }, { 10, 767, 1024 }, 
+   { 3, 768, 1024 }, { 4, 769, 1024 }, { 4, 770, 1024 }, { 5, 771, 1024 }, { 4, 772, 1024 }, { 5, 773, 1024 }, { 5, 774, 1024 }, { 6, 775, 1024 }, 
+   { 4, 776, 1024 }, { 5, 777, 1024 }, { 5, 778, 1024 }, { 6, 779, 1024 }, { 5, 780, 1024 }, { 6, 781, 1024 }, { 6, 782, 1024 }, { 7, 783, 1024 }, 
+   { 4, 784, 1024 }, { 5, 785, 1024 }, { 5, 786, 1024 }, { 6, 787, 1024 }, { 5, 788, 1024 }, { 6, 789, 1024 }, { 6, 790, 1024 }, { 7, 791, 1024 }, 
+   { 5, 792, 1024 }, { 6, 793, 1024 }, { 6, 794, 1024 }, { 7, 795, 1024 }, { 6, 796, 1024 }, { 7, 797, 1024 }, { 7, 798, 1024 }, { 8, 799, 1024 }, 
+   { 4, 800, 1024 }, { 5, 801, 1024 }, { 5, 802, 1024 }, { 6, 803, 1024 }, { 5, 804, 1024 }, { 6, 805, 1024 }, { 6, 806, 1024 }, { 7, 807, 1024 }, 
+   { 5, 808, 1024 }, { 6, 809, 1024 }, { 6, 810, 1024 }, { 7, 811, 1024 }, { 6, 812, 1024 }, { 7, 813, 1024 }, { 7, 814, 1024 }, { 8, 815, 1024 }, 
+   { 5, 816, 1024 }, { 6, 817, 1024 }, { 6, 818, 1024 }, { 7, 819, 1024 }, { 6, 820, 1024 }, { 7, 821, 1024 }, { 7, 822, 1024 }, { 8, 823, 1024 }, 
+   { 6, 824, 1024 }, { 7, 825, 1024 }, { 7, 826, 1024 }, { 8, 827, 1024 }, { 7, 828, 1024 }, { 8, 829, 1024 }, { 8, 830, 1024 }, { 9, 831, 1024 }, 
+   { 4, 832, 1024 }, { 5, 833, 1024 }, { 5, 834, 1024 }, { 6, 835, 1024 }, { 5, 836, 1024 }, { 6, 837, 1024 }, { 6, 838, 1024 }, { 7, 839, 1024 }, 
+   { 5, 840, 1024 }, { 6, 841, 1024 }, { 6, 842, 1024 }, { 7, 843, 1024 }, { 6, 844, 1024 }, { 7, 845, 1024 }, { 7, 846, 1024 }, { 8, 847, 1024 }, 
+   { 5, 848, 1024 }, { 6, 849, 1024 }, { 6, 850, 1024 }, { 7, 851, 1024 }, { 6, 852, 1024 }, { 7, 853, 1024 }, { 7, 854, 1024 }, { 8, 855, 1024 }, 
+   { 6, 856, 1024 }, { 7, 857, 1024 }, { 7, 858, 1024 }, { 8, 859, 1024 }, { 7, 860, 1024 }, { 8, 861, 1024 }, { 8, 862, 1024 }, { 9, 863, 1024 }, 
+   { 5, 864, 1024 }, { 6, 865, 1024 }, { 6, 866, 1024 }, { 7, 867, 1024 }, { 6, 868, 1024 }, { 7, 869, 1024 }, { 7, 870, 1024 }, { 8, 871, 1024 }, 
+   { 6, 872, 1024 }, { 7, 873, 1024 }, { 7, 874, 1024 }, { 8, 875, 1024 }, { 7, 876, 1024 }, { 8, 877, 1024 }, { 8, 878, 1024 }, { 9, 879, 1024 }, 
+   { 6, 880, 1024 }, { 7, 881, 1024 }, { 7, 882, 1024 }, { 8, 883, 1024 }, { 7, 884, 1024 }, { 8, 885, 1024 }, { 8, 886, 1024 }, { 9, 887, 1024 }, 
+   { 7, 888, 1024 }, { 8, 889, 1024 }, { 8, 890, 1024 }, { 9, 891, 1024 }, { 8, 892, 1024 }, { 9, 893, 1024 }, { 9, 894, 1024 }, { 10, 895, 1024 }, 
+   { 4, 896, 1024 }, { 5, 897, 1024 }, { 5, 898, 1024 }, { 6, 899, 1024 }, { 5, 900, 1024 }, { 6, 901, 1024 }, { 6, 902, 1024 }, { 7, 903, 1024 }, 
+   { 5, 904, 1024 }, { 6, 905, 1024 }, { 6, 906, 1024 }, { 7, 907, 1024 }, { 6, 908, 1024 }, { 7, 909, 1024 }, { 7, 910, 1024 }, { 8, 911, 1024 }, 
+   { 5, 912, 1024 }, { 6, 913, 1024 }, { 6, 914, 1024 }, { 7, 915, 1024 }, { 6, 916, 1024 }, { 7, 917, 1024 }, { 7, 918, 1024 }, { 8, 919, 1024 }, 
+   { 6, 920, 1024 }, { 7, 921, 1024 }, { 7, 922, 1024 }, { 8, 923, 1024 }, { 7, 924, 1024 }, { 8, 925, 1024 }, { 8, 926, 1024 }, { 9, 927, 1024 }, 
+   { 5, 928, 1024 }, { 6, 929, 1024 }, { 6, 930, 1024 }, { 7, 931, 1024 }, { 6, 932, 1024 }, { 7, 933, 1024 }, { 7, 934, 1024 }, { 8, 935, 1024 }, 
+   { 6, 936, 1024 }, { 7, 937, 1024 }, { 7, 938, 1024 }, { 8, 939, 1024 }, { 7, 940, 1024 }, { 8, 941, 1024 }, { 8, 942, 1024 }, { 9, 943, 1024 }, 
+   { 6, 944, 1024 }, { 7, 945, 1024 }, { 7, 946, 1024 }, { 8, 947, 1024 }, { 7, 948, 1024 }, { 8, 949, 1024 }, { 8, 950, 1024 }, { 9, 951, 1024 }, 
+   { 7, 952, 1024 }, { 8, 953, 1024 }, { 8, 954, 1024 }, { 9, 955, 1024 }, { 8, 956, 1024 }, { 9, 957, 1024 }, { 9, 958, 1024 }, { 10, 959, 1024 }, 
+   { 5, 960, 1024 }, { 6, 961, 1024 }, { 6, 962, 1024 }, { 7, 963, 1024 }, { 6, 964, 1024 }, { 7, 965, 1024 }, { 7, 966, 1024 }, { 8, 967, 1024 }, 
+   { 6, 968, 1024 }, { 7, 969, 1024 }, { 7, 970, 1024 }, { 8, 971, 1024 }, { 7, 972, 1024 }, { 8, 973, 1024 }, { 8, 974, 1024 }, { 9, 975, 1024 }, 
+   { 6, 976, 1024 }, { 7, 977, 1024 }, { 7, 978, 1024 }, { 8, 979, 1024 }, { 7, 980, 1024 }, { 8, 981, 1024 }, { 8, 982, 1024 }, { 9, 983, 1024 }, 
+   { 7, 984, 1024 }, { 8, 985, 1024 }, { 8, 986, 1024 }, { 9, 987, 1024 }, { 8, 988, 1024 }, { 9, 989, 1024 }, { 9, 990, 1024 }, { 10, 991, 1024 }, 
+   { 6, 992, 1024 }, { 7, 993, 1024 }, { 7, 994, 1024 }, { 8, 995, 1024 }, { 7, 996, 1024 }, { 8, 997, 1024 }, { 8, 998, 1024 }, { 9, 999, 1024 }, 
+   { 7, 1000, 1024 }, { 8, 1001, 1024 }, { 8, 1002, 1024 }, { 9, 1003, 1024 }, { 8, 1004, 1024 }, { 9, 1005, 1024 }, { 9, 1006, 1024 }, { 10, 1007, 1024 }, 
+   { 7, 1008, 1024 }, { 8, 1009, 1024 }, { 8, 1010, 1024 }, { 9, 1011, 1024 }, { 8, 1012, 1024 }, { 9, 1013, 1024 }, { 9, 1014, 1024 }, { 10, 1015, 1024 }, 
+   { 8, 1016, 1024 }, { 9, 1017, 1024 }, { 9, 1018, 1024 }, { 10, 1019, 1024 }, { 9, 1020, 1024 }, { 10, 1021, 1024 }, { 10, 1022, 1024 }, { 11, 1023, 1024 }, 
+#if FP_LUT > 11
+   { 1, 0, 0 }, { 2, 1, 2048 }, { 2, 2, 2048 }, { 3, 3, 2048 }, { 2, 4, 2048 }, { 3, 5, 2048 }, { 3, 6, 2048 }, { 4, 7, 2048 }, 
+   { 2, 8, 2048 }, { 3, 9, 2048 }, { 3, 10, 2048 }, { 4, 11, 2048 }, { 3, 12, 2048 }, { 4, 13, 2048 }, { 4, 14, 2048 }, { 5, 15, 2048 }, 
+   { 2, 16, 2048 }, { 3, 17, 2048 }, { 3, 18, 2048 }, { 4, 19, 2048 }, { 3, 20, 2048 }, { 4, 21, 2048 }, { 4, 22, 2048 }, { 5, 23, 2048 }, 
+   { 3, 24, 2048 }, { 4, 25, 2048 }, { 4, 26, 2048 }, { 5, 27, 2048 }, { 4, 28, 2048 }, { 5, 29, 2048 }, { 5, 30, 2048 }, { 6, 31, 2048 }, 
+   { 2, 32, 2048 }, { 3, 33, 2048 }, { 3, 34, 2048 }, { 4, 35, 2048 }, { 3, 36, 2048 }, { 4, 37, 2048 }, { 4, 38, 2048 }, { 5, 39, 2048 }, 
+   { 3, 40, 2048 }, { 4, 41, 2048 }, { 4, 42, 2048 }, { 5, 43, 2048 }, { 4, 44, 2048 }, { 5, 45, 2048 }, { 5, 46, 2048 }, { 6, 47, 2048 }, 
+   { 3, 48, 2048 }, { 4, 49, 2048 }, { 4, 50, 2048 }, { 5, 51, 2048 }, { 4, 52, 2048 }, { 5, 53, 2048 }, { 5, 54, 2048 }, { 6, 55, 2048 }, 
+   { 4, 56, 2048 }, { 5, 57, 2048 }, { 5, 58, 2048 }, { 6, 59, 2048 }, { 5, 60, 2048 }, { 6, 61, 2048 }, { 6, 62, 2048 }, { 7, 63, 2048 }, 
+   { 2, 64, 2048 }, { 3, 65, 2048 }, { 3, 66, 2048 }, { 4, 67, 2048 }, { 3, 68, 2048 }, { 4, 69, 2048 }, { 4, 70, 2048 }, { 5, 71, 2048 }, 
+   { 3, 72, 2048 }, { 4, 73, 2048 }, { 4, 74, 2048 }, { 5, 75, 2048 }, { 4, 76, 2048 }, { 5, 77, 2048 }, { 5, 78, 2048 }, { 6, 79, 2048 }, 
+   { 3, 80, 2048 }, { 4, 81, 2048 }, { 4, 82, 2048 }, { 5, 83, 2048 }, { 4, 84, 2048 }, { 5, 85, 2048 }, { 5, 86, 2048 }, { 6, 87, 2048 }, 
+   { 4, 88, 2048 }, { 5, 89, 2048 }, { 5, 90, 2048 }, { 6, 91, 2048 }, { 5, 92, 2048 }, { 6, 93, 2048 }, { 6, 94, 2048 }, { 7, 95, 2048 }, 
+   { 3, 96, 2048 }, { 4, 97, 2048 }, { 4, 98, 2048 }, { 5, 99, 2048 }, { 4, 100, 2048 }, { 5, 101, 2048 }, { 5, 102, 2048 }, { 6, 103, 2048 }, 
+   { 4, 104, 2048 }, { 5, 105, 2048 }, { 5, 106, 2048 }, { 6, 107, 2048 }, { 5, 108, 2048 }, { 6, 109, 2048 }, { 6, 110, 2048 }, { 7, 111, 2048 }, 
+   { 4, 112, 2048 }, { 5, 113, 2048 }, { 5, 114, 2048 }, { 6, 115, 2048 }, { 5, 116, 2048 }, { 6, 117, 2048 }, { 6, 118, 2048 }, { 7, 119, 2048 }, 
+   { 5, 120, 2048 }, { 6, 121, 2048 }, { 6, 122, 2048 }, { 7, 123, 2048 }, { 6, 124, 2048 }, { 7, 125, 2048 }, { 7, 126, 2048 }, { 8, 127, 2048 }, 
+   { 2, 128, 2048 }, { 3, 129, 2048 }, { 3, 130, 2048 }, { 4, 131, 2048 }, { 3, 132, 2048 }, { 4, 133, 2048 }, { 4, 134, 2048 }, { 5, 135, 2048 }, 
+   { 3, 136, 2048 }, { 4, 137, 2048 }, { 4, 138, 2048 }, { 5, 139, 2048 }, { 4, 140, 2048 }, { 5, 141, 2048 }, { 5, 142, 2048 }, { 6, 143, 2048 }, 
+   { 3, 144, 2048 }, { 4, 145, 2048 }, { 4, 146, 2048 }, { 5, 147, 2048 }, { 4, 148, 2048 }, { 5, 149, 2048 }, { 5, 150, 2048 }, { 6, 151, 2048 }, 
+   { 4, 152, 2048 }, { 5, 153, 2048 }, { 5, 154, 2048 }, { 6, 155, 2048 }, { 5, 156, 2048 }, { 6, 157, 2048 }, { 6, 158, 2048 }, { 7, 159, 2048 }, 
+   { 3, 160, 2048 }, { 4, 161, 2048 }, { 4, 162, 2048 }, { 5, 163, 2048 }, { 4, 164, 2048 }, { 5, 165, 2048 }, { 5, 166, 2048 }, { 6, 167, 2048 }, 
+   { 4, 168, 2048 }, { 5, 169, 2048 }, { 5, 170, 2048 }, { 6, 171, 2048 }, { 5, 172, 2048 }, { 6, 173, 2048 }, { 6, 174, 2048 }, { 7, 175, 2048 }, 
+   { 4, 176, 2048 }, { 5, 177, 2048 }, { 5, 178, 2048 }, { 6, 179, 2048 }, { 5, 180, 2048 }, { 6, 181, 2048 }, { 6, 182, 2048 }, { 7, 183, 2048 }, 
+   { 5, 184, 2048 }, { 6, 185, 2048 }, { 6, 186, 2048 }, { 7, 187, 2048 }, { 6, 188, 2048 }, { 7, 189, 2048 }, { 7, 190, 2048 }, { 8, 191, 2048 }, 
+   { 3, 192, 2048 }, { 4, 193, 2048 }, { 4, 194, 2048 }, { 5, 195, 2048 }, { 4, 196, 2048 }, { 5, 197, 2048 }, { 5, 198, 2048 }, { 6, 199, 2048 }, 
+   { 4, 200, 2048 }, { 5, 201, 2048 }, { 5, 202, 2048 }, { 6, 203, 2048 }, { 5, 204, 2048 }, { 6, 205, 2048 }, { 6, 206, 2048 }, { 7, 207, 2048 }, 
+   { 4, 208, 2048 }, { 5, 209, 2048 }, { 5, 210, 2048 }, { 6, 211, 2048 }, { 5, 212, 2048 }, { 6, 213, 2048 }, { 6, 214, 2048 }, { 7, 215, 2048 }, 
+   { 5, 216, 2048 }, { 6, 217, 2048 }, { 6, 218, 2048 }, { 7, 219, 2048 }, { 6, 220, 2048 }, { 7, 221, 2048 }, { 7, 222, 2048 }, { 8, 223, 2048 }, 
+   { 4, 224, 2048 }, { 5, 225, 2048 }, { 5, 226, 2048 }, { 6, 227, 2048 }, { 5, 228, 2048 }, { 6, 229, 2048 }, { 6, 230, 2048 }, { 7, 231, 2048 }, 
+   { 5, 232, 2048 }, { 6, 233, 2048 }, { 6, 234, 2048 }, { 7, 235, 2048 }, { 6, 236, 2048 }, { 7, 237, 2048 }, { 7, 238, 2048 }, { 8, 239, 2048 }, 
+   { 5, 240, 2048 }, { 6, 241, 2048 }, { 6, 242, 2048 }, { 7, 243, 2048 }, { 6, 244, 2048 }, { 7, 245, 2048 }, { 7, 246, 2048 }, { 8, 247, 2048 }, 
+   { 6, 248, 2048 }, { 7, 249, 2048 }, { 7, 250, 2048 }, { 8, 251, 2048 }, { 7, 252, 2048 }, { 8, 253, 2048 }, { 8, 254, 2048 }, { 9, 255, 2048 }, 
+   { 2, 256, 2048 }, { 3, 257, 2048 }, { 3, 258, 2048 }, { 4, 259, 2048 }, { 3, 260, 2048 }, { 4, 261, 2048 }, { 4, 262, 2048 }, { 5, 263, 2048 }, 
+   { 3, 264, 2048 }, { 4, 265, 2048 }, { 4, 266, 2048 }, { 5, 267, 2048 }, { 4, 268, 2048 }, { 5, 269, 2048 }, { 5, 270, 2048 }, { 6, 271, 2048 }, 
+   { 3, 272, 2048 }, { 4, 273, 2048 }, { 4, 274, 2048 }, { 5, 275, 2048 }, { 4, 276, 2048 }, { 5, 277, 2048 }, { 5, 278, 2048 }, { 6, 279, 2048 }, 
+   { 4, 280, 2048 }, { 5, 281, 2048 }, { 5, 282, 2048 }, { 6, 283, 2048 }, { 5, 284, 2048 }, { 6, 285, 2048 }, { 6, 286, 2048 }, { 7, 287, 2048 }, 
+   { 3, 288, 2048 }, { 4, 289, 2048 }, { 4, 290, 2048 }, { 5, 291, 2048 }, { 4, 292, 2048 }, { 5, 293, 2048 }, { 5, 294, 2048 }, { 6, 295, 2048 }, 
+   { 4, 296, 2048 }, { 5, 297, 2048 }, { 5, 298, 2048 }, { 6, 299, 2048 }, { 5, 300, 2048 }, { 6, 301, 2048 }, { 6, 302, 2048 }, { 7, 303, 2048 }, 
+   { 4, 304, 2048 }, { 5, 305, 2048 }, { 5, 306, 2048 }, { 6, 307, 2048 }, { 5, 308, 2048 }, { 6, 309, 2048 }, { 6, 310, 2048 }, { 7, 311, 2048 }, 
+   { 5, 312, 2048 }, { 6, 313, 2048 }, { 6, 314, 2048 }, { 7, 315, 2048 }, { 6, 316, 2048 }, { 7, 317, 2048 }, { 7, 318, 2048 }, { 8, 319, 2048 }, 
+   { 3, 320, 2048 }, { 4, 321, 2048 }, { 4, 322, 2048 }, { 5, 323, 2048 }, { 4, 324, 2048 }, { 5, 325, 2048 }, { 5, 326, 2048 }, { 6, 327, 2048 }, 
+   { 4, 328, 2048 }, { 5, 329, 2048 }, { 5, 330, 2048 }, { 6, 331, 2048 }, { 5, 332, 2048 }, { 6, 333, 2048 }, { 6, 334, 2048 }, { 7, 335, 2048 }, 
+   { 4, 336, 2048 }, { 5, 337, 2048 }, { 5, 338, 2048 }, { 6, 339, 2048 }, { 5, 340, 2048 }, { 6, 341, 2048 }, { 6, 342, 2048 }, { 7, 343, 2048 }, 
+   { 5, 344, 2048 }, { 6, 345, 2048 }, { 6, 346, 2048 }, { 7, 347, 2048 }, { 6, 348, 2048 }, { 7, 349, 2048 }, { 7, 350, 2048 }, { 8, 351, 2048 }, 
+   { 4, 352, 2048 }, { 5, 353, 2048 }, { 5, 354, 2048 }, { 6, 355, 2048 }, { 5, 356, 2048 }, { 6, 357, 2048 }, { 6, 358, 2048 }, { 7, 359, 2048 }, 
+   { 5, 360, 2048 }, { 6, 361, 2048 }, { 6, 362, 2048 }, { 7, 363, 2048 }, { 6, 364, 2048 }, { 7, 365, 2048 }, { 7, 366, 2048 }, { 8, 367, 2048 }, 
+   { 5, 368, 2048 }, { 6, 369, 2048 }, { 6, 370, 2048 }, { 7, 371, 2048 }, { 6, 372, 2048 }, { 7, 373, 2048 }, { 7, 374, 2048 }, { 8, 375, 2048 }, 
+   { 6, 376, 2048 }, { 7, 377, 2048 }, { 7, 378, 2048 }, { 8, 379, 2048 }, { 7, 380, 2048 }, { 8, 381, 2048 }, { 8, 382, 2048 }, { 9, 383, 2048 }, 
+   { 3, 384, 2048 }, { 4, 385, 2048 }, { 4, 386, 2048 }, { 5, 387, 2048 }, { 4, 388, 2048 }, { 5, 389, 2048 }, { 5, 390, 2048 }, { 6, 391, 2048 }, 
+   { 4, 392, 2048 }, { 5, 393, 2048 }, { 5, 394, 2048 }, { 6, 395, 2048 }, { 5, 396, 2048 }, { 6, 397, 2048 }, { 6, 398, 2048 }, { 7, 399, 2048 }, 
+   { 4, 400, 2048 }, { 5, 401, 2048 }, { 5, 402, 2048 }, { 6, 403, 2048 }, { 5, 404, 2048 }, { 6, 405, 2048 }, { 6, 406, 2048 }, { 7, 407, 2048 }, 
+   { 5, 408, 2048 }, { 6, 409, 2048 }, { 6, 410, 2048 }, { 7, 411, 2048 }, { 6, 412, 2048 }, { 7, 413, 2048 }, { 7, 414, 2048 }, { 8, 415, 2048 }, 
+   { 4, 416, 2048 }, { 5, 417, 2048 }, { 5, 418, 2048 }, { 6, 419, 2048 }, { 5, 420, 2048 }, { 6, 421, 2048 }, { 6, 422, 2048 }, { 7, 423, 2048 }, 
+   { 5, 424, 2048 }, { 6, 425, 2048 }, { 6, 426, 2048 }, { 7, 427, 2048 }, { 6, 428, 2048 }, { 7, 429, 2048 }, { 7, 430, 2048 }, { 8, 431, 2048 }, 
+   { 5, 432, 2048 }, { 6, 433, 2048 }, { 6, 434, 2048 }, { 7, 435, 2048 }, { 6, 436, 2048 }, { 7, 437, 2048 }, { 7, 438, 2048 }, { 8, 439, 2048 }, 
+   { 6, 440, 2048 }, { 7, 441, 2048 }, { 7, 442, 2048 }, { 8, 443, 2048 }, { 7, 444, 2048 }, { 8, 445, 2048 }, { 8, 446, 2048 }, { 9, 447, 2048 }, 
+   { 4, 448, 2048 }, { 5, 449, 2048 }, { 5, 450, 2048 }, { 6, 451, 2048 }, { 5, 452, 2048 }, { 6, 453, 2048 }, { 6, 454, 2048 }, { 7, 455, 2048 }, 
+   { 5, 456, 2048 }, { 6, 457, 2048 }, { 6, 458, 2048 }, { 7, 459, 2048 }, { 6, 460, 2048 }, { 7, 461, 2048 }, { 7, 462, 2048 }, { 8, 463, 2048 }, 
+   { 5, 464, 2048 }, { 6, 465, 2048 }, { 6, 466, 2048 }, { 7, 467, 2048 }, { 6, 468, 2048 }, { 7, 469, 2048 }, { 7, 470, 2048 }, { 8, 471, 2048 }, 
+   { 6, 472, 2048 }, { 7, 473, 2048 }, { 7, 474, 2048 }, { 8, 475, 2048 }, { 7, 476, 2048 }, { 8, 477, 2048 }, { 8, 478, 2048 }, { 9, 479, 2048 }, 
+   { 5, 480, 2048 }, { 6, 481, 2048 }, { 6, 482, 2048 }, { 7, 483, 2048 }, { 6, 484, 2048 }, { 7, 485, 2048 }, { 7, 486, 2048 }, { 8, 487, 2048 }, 
+   { 6, 488, 2048 }, { 7, 489, 2048 }, { 7, 490, 2048 }, { 8, 491, 2048 }, { 7, 492, 2048 }, { 8, 493, 2048 }, { 8, 494, 2048 }, { 9, 495, 2048 }, 
+   { 6, 496, 2048 }, { 7, 497, 2048 }, { 7, 498, 2048 }, { 8, 499, 2048 }, { 7, 500, 2048 }, { 8, 501, 2048 }, { 8, 502, 2048 }, { 9, 503, 2048 }, 
+   { 7, 504, 2048 }, { 8, 505, 2048 }, { 8, 506, 2048 }, { 9, 507, 2048 }, { 8, 508, 2048 }, { 9, 509, 2048 }, { 9, 510, 2048 }, { 10, 511, 2048 }, 
+   { 2, 512, 2048 }, { 3, 513, 2048 }, { 3, 514, 2048 }, { 4, 515, 2048 }, { 3, 516, 2048 }, { 4, 517, 2048 }, { 4, 518, 2048 }, { 5, 519, 2048 }, 
+   { 3, 520, 2048 }, { 4, 521, 2048 }, { 4, 522, 2048 }, { 5, 523, 2048 }, { 4, 524, 2048 }, { 5, 525, 2048 }, { 5, 526, 2048 }, { 6, 527, 2048 }, 
+   { 3, 528, 2048 }, { 4, 529, 2048 }, { 4, 530, 2048 }, { 5, 531, 2048 }, { 4, 532, 2048 }, { 5, 533, 2048 }, { 5, 534, 2048 }, { 6, 535, 2048 }, 
+   { 4, 536, 2048 }, { 5, 537, 2048 }, { 5, 538, 2048 }, { 6, 539, 2048 }, { 5, 540, 2048 }, { 6, 541, 2048 }, { 6, 542, 2048 }, { 7, 543, 2048 }, 
+   { 3, 544, 2048 }, { 4, 545, 2048 }, { 4, 546, 2048 }, { 5, 547, 2048 }, { 4, 548, 2048 }, { 5, 549, 2048 }, { 5, 550, 2048 }, { 6, 551, 2048 }, 
+   { 4, 552, 2048 }, { 5, 553, 2048 }, { 5, 554, 2048 }, { 6, 555, 2048 }, { 5, 556, 2048 }, { 6, 557, 2048 }, { 6, 558, 2048 }, { 7, 559, 2048 }, 
+   { 4, 560, 2048 }, { 5, 561, 2048 }, { 5, 562, 2048 }, { 6, 563, 2048 }, { 5, 564, 2048 }, { 6, 565, 2048 }, { 6, 566, 2048 }, { 7, 567, 2048 }, 
+   { 5, 568, 2048 }, { 6, 569, 2048 }, { 6, 570, 2048 }, { 7, 571, 2048 }, { 6, 572, 2048 }, { 7, 573, 2048 }, { 7, 574, 2048 }, { 8, 575, 2048 }, 
+   { 3, 576, 2048 }, { 4, 577, 2048 }, { 4, 578, 2048 }, { 5, 579, 2048 }, { 4, 580, 2048 }, { 5, 581, 2048 }, { 5, 582, 2048 }, { 6, 583, 2048 }, 
+   { 4, 584, 2048 }, { 5, 585, 2048 }, { 5, 586, 2048 }, { 6, 587, 2048 }, { 5, 588, 2048 }, { 6, 589, 2048 }, { 6, 590, 2048 }, { 7, 591, 2048 }, 
+   { 4, 592, 2048 }, { 5, 593, 2048 }, { 5, 594, 2048 }, { 6, 595, 2048 }, { 5, 596, 2048 }, { 6, 597, 2048 }, { 6, 598, 2048 }, { 7, 599, 2048 }, 
+   { 5, 600, 2048 }, { 6, 601, 2048 }, { 6, 602, 2048 }, { 7, 603, 2048 }, { 6, 604, 2048 }, { 7, 605, 2048 }, { 7, 606, 2048 }, { 8, 607, 2048 }, 
+   { 4, 608, 2048 }, { 5, 609, 2048 }, { 5, 610, 2048 }, { 6, 611, 2048 }, { 5, 612, 2048 }, { 6, 613, 2048 }, { 6, 614, 2048 }, { 7, 615, 2048 }, 
+   { 5, 616, 2048 }, { 6, 617, 2048 }, { 6, 618, 2048 }, { 7, 619, 2048 }, { 6, 620, 2048 }, { 7, 621, 2048 }, { 7, 622, 2048 }, { 8, 623, 2048 }, 
+   { 5, 624, 2048 }, { 6, 625, 2048 }, { 6, 626, 2048 }, { 7, 627, 2048 }, { 6, 628, 2048 }, { 7, 629, 2048 }, { 7, 630, 2048 }, { 8, 631, 2048 }, 
+   { 6, 632, 2048 }, { 7, 633, 2048 }, { 7, 634, 2048 }, { 8, 635, 2048 }, { 7, 636, 2048 }, { 8, 637, 2048 }, { 8, 638, 2048 }, { 9, 639, 2048 }, 
+   { 3, 640, 2048 }, { 4, 641, 2048 }, { 4, 642, 2048 }, { 5, 643, 2048 }, { 4, 644, 2048 }, { 5, 645, 2048 }, { 5, 646, 2048 }, { 6, 647, 2048 }, 
+   { 4, 648, 2048 }, { 5, 649, 2048 }, { 5, 650, 2048 }, { 6, 651, 2048 }, { 5, 652, 2048 }, { 6, 653, 2048 }, { 6, 654, 2048 }, { 7, 655, 2048 }, 
+   { 4, 656, 2048 }, { 5, 657, 2048 }, { 5, 658, 2048 }, { 6, 659, 2048 }, { 5, 660, 2048 }, { 6, 661, 2048 }, { 6, 662, 2048 }, { 7, 663, 2048 }, 
+   { 5, 664, 2048 }, { 6, 665, 2048 }, { 6, 666, 2048 }, { 7, 667, 2048 }, { 6, 668, 2048 }, { 7, 669, 2048 }, { 7, 670, 2048 }, { 8, 671, 2048 }, 
+   { 4, 672, 2048 }, { 5, 673, 2048 }, { 5, 674, 2048 }, { 6, 675, 2048 }, { 5, 676, 2048 }, { 6, 677, 2048 }, { 6, 678, 2048 }, { 7, 679, 2048 }, 
+   { 5, 680, 2048 }, { 6, 681, 2048 }, { 6, 682, 2048 }, { 7, 683, 2048 }, { 6, 684, 2048 }, { 7, 685, 2048 }, { 7, 686, 2048 }, { 8, 687, 2048 }, 
+   { 5, 688, 2048 }, { 6, 689, 2048 }, { 6, 690, 2048 }, { 7, 691, 2048 }, { 6, 692, 2048 }, { 7, 693, 2048 }, { 7, 694, 2048 }, { 8, 695, 2048 }, 
+   { 6, 696, 2048 }, { 7, 697, 2048 }, { 7, 698, 2048 }, { 8, 699, 2048 }, { 7, 700, 2048 }, { 8, 701, 2048 }, { 8, 702, 2048 }, { 9, 703, 2048 }, 
+   { 4, 704, 2048 }, { 5, 705, 2048 }, { 5, 706, 2048 }, { 6, 707, 2048 }, { 5, 708, 2048 }, { 6, 709, 2048 }, { 6, 710, 2048 }, { 7, 711, 2048 }, 
+   { 5, 712, 2048 }, { 6, 713, 2048 }, { 6, 714, 2048 }, { 7, 715, 2048 }, { 6, 716, 2048 }, { 7, 717, 2048 }, { 7, 718, 2048 }, { 8, 719, 2048 }, 
+   { 5, 720, 2048 }, { 6, 721, 2048 }, { 6, 722, 2048 }, { 7, 723, 2048 }, { 6, 724, 2048 }, { 7, 725, 2048 }, { 7, 726, 2048 }, { 8, 727, 2048 }, 
+   { 6, 728, 2048 }, { 7, 729, 2048 }, { 7, 730, 2048 }, { 8, 731, 2048 }, { 7, 732, 2048 }, { 8, 733, 2048 }, { 8, 734, 2048 }, { 9, 735, 2048 }, 
+   { 5, 736, 2048 }, { 6, 737, 2048 }, { 6, 738, 2048 }, { 7, 739, 2048 }, { 6, 740, 2048 }, { 7, 741, 2048 }, { 7, 742, 2048 }, { 8, 743, 2048 }, 
+   { 6, 744, 2048 }, { 7, 745, 2048 }, { 7, 746, 2048 }, { 8, 747, 2048 }, { 7, 748, 2048 }, { 8, 749, 2048 }, { 8, 750, 2048 }, { 9, 751, 2048 }, 
+   { 6, 752, 2048 }, { 7, 753, 2048 }, { 7, 754, 2048 }, { 8, 755, 2048 }, { 7, 756, 2048 }, { 8, 757, 2048 }, { 8, 758, 2048 }, { 9, 759, 2048 }, 
+   { 7, 760, 2048 }, { 8, 761, 2048 }, { 8, 762, 2048 }, { 9, 763, 2048 }, { 8, 764, 2048 }, { 9, 765, 2048 }, { 9, 766, 2048 }, { 10, 767, 2048 }, 
+   { 3, 768, 2048 }, { 4, 769, 2048 }, { 4, 770, 2048 }, { 5, 771, 2048 }, { 4, 772, 2048 }, { 5, 773, 2048 }, { 5, 774, 2048 }, { 6, 775, 2048 }, 
+   { 4, 776, 2048 }, { 5, 777, 2048 }, { 5, 778, 2048 }, { 6, 779, 2048 }, { 5, 780, 2048 }, { 6, 781, 2048 }, { 6, 782, 2048 }, { 7, 783, 2048 }, 
+   { 4, 784, 2048 }, { 5, 785, 2048 }, { 5, 786, 2048 }, { 6, 787, 2048 }, { 5, 788, 2048 }, { 6, 789, 2048 }, { 6, 790, 2048 }, { 7, 791, 2048 }, 
+   { 5, 792, 2048 }, { 6, 793, 2048 }, { 6, 794, 2048 }, { 7, 795, 2048 }, { 6, 796, 2048 }, { 7, 797, 2048 }, { 7, 798, 2048 }, { 8, 799, 2048 }, 
+   { 4, 800, 2048 }, { 5, 801, 2048 }, { 5, 802, 2048 }, { 6, 803, 2048 }, { 5, 804, 2048 }, { 6, 805, 2048 }, { 6, 806, 2048 }, { 7, 807, 2048 }, 
+   { 5, 808, 2048 }, { 6, 809, 2048 }, { 6, 810, 2048 }, { 7, 811, 2048 }, { 6, 812, 2048 }, { 7, 813, 2048 }, { 7, 814, 2048 }, { 8, 815, 2048 }, 
+   { 5, 816, 2048 }, { 6, 817, 2048 }, { 6, 818, 2048 }, { 7, 819, 2048 }, { 6, 820, 2048 }, { 7, 821, 2048 }, { 7, 822, 2048 }, { 8, 823, 2048 }, 
+   { 6, 824, 2048 }, { 7, 825, 2048 }, { 7, 826, 2048 }, { 8, 827, 2048 }, { 7, 828, 2048 }, { 8, 829, 2048 }, { 8, 830, 2048 }, { 9, 831, 2048 }, 
+   { 4, 832, 2048 }, { 5, 833, 2048 }, { 5, 834, 2048 }, { 6, 835, 2048 }, { 5, 836, 2048 }, { 6, 837, 2048 }, { 6, 838, 2048 }, { 7, 839, 2048 }, 
+   { 5, 840, 2048 }, { 6, 841, 2048 }, { 6, 842, 2048 }, { 7, 843, 2048 }, { 6, 844, 2048 }, { 7, 845, 2048 }, { 7, 846, 2048 }, { 8, 847, 2048 }, 
+   { 5, 848, 2048 }, { 6, 849, 2048 }, { 6, 850, 2048 }, { 7, 851, 2048 }, { 6, 852, 2048 }, { 7, 853, 2048 }, { 7, 854, 2048 }, { 8, 855, 2048 }, 
+   { 6, 856, 2048 }, { 7, 857, 2048 }, { 7, 858, 2048 }, { 8, 859, 2048 }, { 7, 860, 2048 }, { 8, 861, 2048 }, { 8, 862, 2048 }, { 9, 863, 2048 }, 
+   { 5, 864, 2048 }, { 6, 865, 2048 }, { 6, 866, 2048 }, { 7, 867, 2048 }, { 6, 868, 2048 }, { 7, 869, 2048 }, { 7, 870, 2048 }, { 8, 871, 2048 }, 
+   { 6, 872, 2048 }, { 7, 873, 2048 }, { 7, 874, 2048 }, { 8, 875, 2048 }, { 7, 876, 2048 }, { 8, 877, 2048 }, { 8, 878, 2048 }, { 9, 879, 2048 }, 
+   { 6, 880, 2048 }, { 7, 881, 2048 }, { 7, 882, 2048 }, { 8, 883, 2048 }, { 7, 884, 2048 }, { 8, 885, 2048 }, { 8, 886, 2048 }, { 9, 887, 2048 }, 
+   { 7, 888, 2048 }, { 8, 889, 2048 }, { 8, 890, 2048 }, { 9, 891, 2048 }, { 8, 892, 2048 }, { 9, 893, 2048 }, { 9, 894, 2048 }, { 10, 895, 2048 }, 
+   { 4, 896, 2048 }, { 5, 897, 2048 }, { 5, 898, 2048 }, { 6, 899, 2048 }, { 5, 900, 2048 }, { 6, 901, 2048 }, { 6, 902, 2048 }, { 7, 903, 2048 }, 
+   { 5, 904, 2048 }, { 6, 905, 2048 }, { 6, 906, 2048 }, { 7, 907, 2048 }, { 6, 908, 2048 }, { 7, 909, 2048 }, { 7, 910, 2048 }, { 8, 911, 2048 }, 
+   { 5, 912, 2048 }, { 6, 913, 2048 }, { 6, 914, 2048 }, { 7, 915, 2048 }, { 6, 916, 2048 }, { 7, 917, 2048 }, { 7, 918, 2048 }, { 8, 919, 2048 }, 
+   { 6, 920, 2048 }, { 7, 921, 2048 }, { 7, 922, 2048 }, { 8, 923, 2048 }, { 7, 924, 2048 }, { 8, 925, 2048 }, { 8, 926, 2048 }, { 9, 927, 2048 }, 
+   { 5, 928, 2048 }, { 6, 929, 2048 }, { 6, 930, 2048 }, { 7, 931, 2048 }, { 6, 932, 2048 }, { 7, 933, 2048 }, { 7, 934, 2048 }, { 8, 935, 2048 }, 
+   { 6, 936, 2048 }, { 7, 937, 2048 }, { 7, 938, 2048 }, { 8, 939, 2048 }, { 7, 940, 2048 }, { 8, 941, 2048 }, { 8, 942, 2048 }, { 9, 943, 2048 }, 
+   { 6, 944, 2048 }, { 7, 945, 2048 }, { 7, 946, 2048 }, { 8, 947, 2048 }, { 7, 948, 2048 }, { 8, 949, 2048 }, { 8, 950, 2048 }, { 9, 951, 2048 }, 
+   { 7, 952, 2048 }, { 8, 953, 2048 }, { 8, 954, 2048 }, { 9, 955, 2048 }, { 8, 956, 2048 }, { 9, 957, 2048 }, { 9, 958, 2048 }, { 10, 959, 2048 }, 
+   { 5, 960, 2048 }, { 6, 961, 2048 }, { 6, 962, 2048 }, { 7, 963, 2048 }, { 6, 964, 2048 }, { 7, 965, 2048 }, { 7, 966, 2048 }, { 8, 967, 2048 }, 
+   { 6, 968, 2048 }, { 7, 969, 2048 }, { 7, 970, 2048 }, { 8, 971, 2048 }, { 7, 972, 2048 }, { 8, 973, 2048 }, { 8, 974, 2048 }, { 9, 975, 2048 }, 
+   { 6, 976, 2048 }, { 7, 977, 2048 }, { 7, 978, 2048 }, { 8, 979, 2048 }, { 7, 980, 2048 }, { 8, 981, 2048 }, { 8, 982, 2048 }, { 9, 983, 2048 }, 
+   { 7, 984, 2048 }, { 8, 985, 2048 }, { 8, 986, 2048 }, { 9, 987, 2048 }, { 8, 988, 2048 }, { 9, 989, 2048 }, { 9, 990, 2048 }, { 10, 991, 2048 }, 
+   { 6, 992, 2048 }, { 7, 993, 2048 }, { 7, 994, 2048 }, { 8, 995, 2048 }, { 7, 996, 2048 }, { 8, 997, 2048 }, { 8, 998, 2048 }, { 9, 999, 2048 }, 
+   { 7, 1000, 2048 }, { 8, 1001, 2048 }, { 8, 1002, 2048 }, { 9, 1003, 2048 }, { 8, 1004, 2048 }, { 9, 1005, 2048 }, { 9, 1006, 2048 }, { 10, 1007, 2048 }, 
+   { 7, 1008, 2048 }, { 8, 1009, 2048 }, { 8, 1010, 2048 }, { 9, 1011, 2048 }, { 8, 1012, 2048 }, { 9, 1013, 2048 }, { 9, 1014, 2048 }, { 10, 1015, 2048 }, 
+   { 8, 1016, 2048 }, { 9, 1017, 2048 }, { 9, 1018, 2048 }, { 10, 1019, 2048 }, { 9, 1020, 2048 }, { 10, 1021, 2048 }, { 10, 1022, 2048 }, { 11, 1023, 2048 }, 
+   { 2, 1024, 2048 }, { 3, 1025, 2048 }, { 3, 1026, 2048 }, { 4, 1027, 2048 }, { 3, 1028, 2048 }, { 4, 1029, 2048 }, { 4, 1030, 2048 }, { 5, 1031, 2048 }, 
+   { 3, 1032, 2048 }, { 4, 1033, 2048 }, { 4, 1034, 2048 }, { 5, 1035, 2048 }, { 4, 1036, 2048 }, { 5, 1037, 2048 }, { 5, 1038, 2048 }, { 6, 1039, 2048 }, 
+   { 3, 1040, 2048 }, { 4, 1041, 2048 }, { 4, 1042, 2048 }, { 5, 1043, 2048 }, { 4, 1044, 2048 }, { 5, 1045, 2048 }, { 5, 1046, 2048 }, { 6, 1047, 2048 }, 
+   { 4, 1048, 2048 }, { 5, 1049, 2048 }, { 5, 1050, 2048 }, { 6, 1051, 2048 }, { 5, 1052, 2048 }, { 6, 1053, 2048 }, { 6, 1054, 2048 }, { 7, 1055, 2048 }, 
+   { 3, 1056, 2048 }, { 4, 1057, 2048 }, { 4, 1058, 2048 }, { 5, 1059, 2048 }, { 4, 1060, 2048 }, { 5, 1061, 2048 }, { 5, 1062, 2048 }, { 6, 1063, 2048 }, 
+   { 4, 1064, 2048 }, { 5, 1065, 2048 }, { 5, 1066, 2048 }, { 6, 1067, 2048 }, { 5, 1068, 2048 }, { 6, 1069, 2048 }, { 6, 1070, 2048 }, { 7, 1071, 2048 }, 
+   { 4, 1072, 2048 }, { 5, 1073, 2048 }, { 5, 1074, 2048 }, { 6, 1075, 2048 }, { 5, 1076, 2048 }, { 6, 1077, 2048 }, { 6, 1078, 2048 }, { 7, 1079, 2048 }, 
+   { 5, 1080, 2048 }, { 6, 1081, 2048 }, { 6, 1082, 2048 }, { 7, 1083, 2048 }, { 6, 1084, 2048 }, { 7, 1085, 2048 }, { 7, 1086, 2048 }, { 8, 1087, 2048 }, 
+   { 3, 1088, 2048 }, { 4, 1089, 2048 }, { 4, 1090, 2048 }, { 5, 1091, 2048 }, { 4, 1092, 2048 }, { 5, 1093, 2048 }, { 5, 1094, 2048 }, { 6, 1095, 2048 }, 
+   { 4, 1096, 2048 }, { 5, 1097, 2048 }, { 5, 1098, 2048 }, { 6, 1099, 2048 }, { 5, 1100, 2048 }, { 6, 1101, 2048 }, { 6, 1102, 2048 }, { 7, 1103, 2048 }, 
+   { 4, 1104, 2048 }, { 5, 1105, 2048 }, { 5, 1106, 2048 }, { 6, 1107, 2048 }, { 5, 1108, 2048 }, { 6, 1109, 2048 }, { 6, 1110, 2048 }, { 7, 1111, 2048 }, 
+   { 5, 1112, 2048 }, { 6, 1113, 2048 }, { 6, 1114, 2048 }, { 7, 1115, 2048 }, { 6, 1116, 2048 }, { 7, 1117, 2048 }, { 7, 1118, 2048 }, { 8, 1119, 2048 }, 
+   { 4, 1120, 2048 }, { 5, 1121, 2048 }, { 5, 1122, 2048 }, { 6, 1123, 2048 }, { 5, 1124, 2048 }, { 6, 1125, 2048 }, { 6, 1126, 2048 }, { 7, 1127, 2048 }, 
+   { 5, 1128, 2048 }, { 6, 1129, 2048 }, { 6, 1130, 2048 }, { 7, 1131, 2048 }, { 6, 1132, 2048 }, { 7, 1133, 2048 }, { 7, 1134, 2048 }, { 8, 1135, 2048 }, 
+   { 5, 1136, 2048 }, { 6, 1137, 2048 }, { 6, 1138, 2048 }, { 7, 1139, 2048 }, { 6, 1140, 2048 }, { 7, 1141, 2048 }, { 7, 1142, 2048 }, { 8, 1143, 2048 }, 
+   { 6, 1144, 2048 }, { 7, 1145, 2048 }, { 7, 1146, 2048 }, { 8, 1147, 2048 }, { 7, 1148, 2048 }, { 8, 1149, 2048 }, { 8, 1150, 2048 }, { 9, 1151, 2048 }, 
+   { 3, 1152, 2048 }, { 4, 1153, 2048 }, { 4, 1154, 2048 }, { 5, 1155, 2048 }, { 4, 1156, 2048 }, { 5, 1157, 2048 }, { 5, 1158, 2048 }, { 6, 1159, 2048 }, 
+   { 4, 1160, 2048 }, { 5, 1161, 2048 }, { 5, 1162, 2048 }, { 6, 1163, 2048 }, { 5, 1164, 2048 }, { 6, 1165, 2048 }, { 6, 1166, 2048 }, { 7, 1167, 2048 }, 
+   { 4, 1168, 2048 }, { 5, 1169, 2048 }, { 5, 1170, 2048 }, { 6, 1171, 2048 }, { 5, 1172, 2048 }, { 6, 1173, 2048 }, { 6, 1174, 2048 }, { 7, 1175, 2048 }, 
+   { 5, 1176, 2048 }, { 6, 1177, 2048 }, { 6, 1178, 2048 }, { 7, 1179, 2048 }, { 6, 1180, 2048 }, { 7, 1181, 2048 }, { 7, 1182, 2048 }, { 8, 1183, 2048 }, 
+   { 4, 1184, 2048 }, { 5, 1185, 2048 }, { 5, 1186, 2048 }, { 6, 1187, 2048 }, { 5, 1188, 2048 }, { 6, 1189, 2048 }, { 6, 1190, 2048 }, { 7, 1191, 2048 }, 
+   { 5, 1192, 2048 }, { 6, 1193, 2048 }, { 6, 1194, 2048 }, { 7, 1195, 2048 }, { 6, 1196, 2048 }, { 7, 1197, 2048 }, { 7, 1198, 2048 }, { 8, 1199, 2048 }, 
+   { 5, 1200, 2048 }, { 6, 1201, 2048 }, { 6, 1202, 2048 }, { 7, 1203, 2048 }, { 6, 1204, 2048 }, { 7, 1205, 2048 }, { 7, 1206, 2048 }, { 8, 1207, 2048 }, 
+   { 6, 1208, 2048 }, { 7, 1209, 2048 }, { 7, 1210, 2048 }, { 8, 1211, 2048 }, { 7, 1212, 2048 }, { 8, 1213, 2048 }, { 8, 1214, 2048 }, { 9, 1215, 2048 }, 
+   { 4, 1216, 2048 }, { 5, 1217, 2048 }, { 5, 1218, 2048 }, { 6, 1219, 2048 }, { 5, 1220, 2048 }, { 6, 1221, 2048 }, { 6, 1222, 2048 }, { 7, 1223, 2048 }, 
+   { 5, 1224, 2048 }, { 6, 1225, 2048 }, { 6, 1226, 2048 }, { 7, 1227, 2048 }, { 6, 1228, 2048 }, { 7, 1229, 2048 }, { 7, 1230, 2048 }, { 8, 1231, 2048 }, 
+   { 5, 1232, 2048 }, { 6, 1233, 2048 }, { 6, 1234, 2048 }, { 7, 1235, 2048 }, { 6, 1236, 2048 }, { 7, 1237, 2048 }, { 7, 1238, 2048 }, { 8, 1239, 2048 }, 
+   { 6, 1240, 2048 }, { 7, 1241, 2048 }, { 7, 1242, 2048 }, { 8, 1243, 2048 }, { 7, 1244, 2048 }, { 8, 1245, 2048 }, { 8, 1246, 2048 }, { 9, 1247, 2048 }, 
+   { 5, 1248, 2048 }, { 6, 1249, 2048 }, { 6, 1250, 2048 }, { 7, 1251, 2048 }, { 6, 1252, 2048 }, { 7, 1253, 2048 }, { 7, 1254, 2048 }, { 8, 1255, 2048 }, 
+   { 6, 1256, 2048 }, { 7, 1257, 2048 }, { 7, 1258, 2048 }, { 8, 1259, 2048 }, { 7, 1260, 2048 }, { 8, 1261, 2048 }, { 8, 1262, 2048 }, { 9, 1263, 2048 }, 
+   { 6, 1264, 2048 }, { 7, 1265, 2048 }, { 7, 1266, 2048 }, { 8, 1267, 2048 }, { 7, 1268, 2048 }, { 8, 1269, 2048 }, { 8, 1270, 2048 }, { 9, 1271, 2048 }, 
+   { 7, 1272, 2048 }, { 8, 1273, 2048 }, { 8, 1274, 2048 }, { 9, 1275, 2048 }, { 8, 1276, 2048 }, { 9, 1277, 2048 }, { 9, 1278, 2048 }, { 10, 1279, 2048 }, 
+   { 3, 1280, 2048 }, { 4, 1281, 2048 }, { 4, 1282, 2048 }, { 5, 1283, 2048 }, { 4, 1284, 2048 }, { 5, 1285, 2048 }, { 5, 1286, 2048 }, { 6, 1287, 2048 }, 
+   { 4, 1288, 2048 }, { 5, 1289, 2048 }, { 5, 1290, 2048 }, { 6, 1291, 2048 }, { 5, 1292, 2048 }, { 6, 1293, 2048 }, { 6, 1294, 2048 }, { 7, 1295, 2048 }, 
+   { 4, 1296, 2048 }, { 5, 1297, 2048 }, { 5, 1298, 2048 }, { 6, 1299, 2048 }, { 5, 1300, 2048 }, { 6, 1301, 2048 }, { 6, 1302, 2048 }, { 7, 1303, 2048 }, 
+   { 5, 1304, 2048 }, { 6, 1305, 2048 }, { 6, 1306, 2048 }, { 7, 1307, 2048 }, { 6, 1308, 2048 }, { 7, 1309, 2048 }, { 7, 1310, 2048 }, { 8, 1311, 2048 }, 
+   { 4, 1312, 2048 }, { 5, 1313, 2048 }, { 5, 1314, 2048 }, { 6, 1315, 2048 }, { 5, 1316, 2048 }, { 6, 1317, 2048 }, { 6, 1318, 2048 }, { 7, 1319, 2048 }, 
+   { 5, 1320, 2048 }, { 6, 1321, 2048 }, { 6, 1322, 2048 }, { 7, 1323, 2048 }, { 6, 1324, 2048 }, { 7, 1325, 2048 }, { 7, 1326, 2048 }, { 8, 1327, 2048 }, 
+   { 5, 1328, 2048 }, { 6, 1329, 2048 }, { 6, 1330, 2048 }, { 7, 1331, 2048 }, { 6, 1332, 2048 }, { 7, 1333, 2048 }, { 7, 1334, 2048 }, { 8, 1335, 2048 }, 
+   { 6, 1336, 2048 }, { 7, 1337, 2048 }, { 7, 1338, 2048 }, { 8, 1339, 2048 }, { 7, 1340, 2048 }, { 8, 1341, 2048 }, { 8, 1342, 2048 }, { 9, 1343, 2048 }, 
+   { 4, 1344, 2048 }, { 5, 1345, 2048 }, { 5, 1346, 2048 }, { 6, 1347, 2048 }, { 5, 1348, 2048 }, { 6, 1349, 2048 }, { 6, 1350, 2048 }, { 7, 1351, 2048 }, 
+   { 5, 1352, 2048 }, { 6, 1353, 2048 }, { 6, 1354, 2048 }, { 7, 1355, 2048 }, { 6, 1356, 2048 }, { 7, 1357, 2048 }, { 7, 1358, 2048 }, { 8, 1359, 2048 }, 
+   { 5, 1360, 2048 }, { 6, 1361, 2048 }, { 6, 1362, 2048 }, { 7, 1363, 2048 }, { 6, 1364, 2048 }, { 7, 1365, 2048 }, { 7, 1366, 2048 }, { 8, 1367, 2048 }, 
+   { 6, 1368, 2048 }, { 7, 1369, 2048 }, { 7, 1370, 2048 }, { 8, 1371, 2048 }, { 7, 1372, 2048 }, { 8, 1373, 2048 }, { 8, 1374, 2048 }, { 9, 1375, 2048 }, 
+   { 5, 1376, 2048 }, { 6, 1377, 2048 }, { 6, 1378, 2048 }, { 7, 1379, 2048 }, { 6, 1380, 2048 }, { 7, 1381, 2048 }, { 7, 1382, 2048 }, { 8, 1383, 2048 }, 
+   { 6, 1384, 2048 }, { 7, 1385, 2048 }, { 7, 1386, 2048 }, { 8, 1387, 2048 }, { 7, 1388, 2048 }, { 8, 1389, 2048 }, { 8, 1390, 2048 }, { 9, 1391, 2048 }, 
+   { 6, 1392, 2048 }, { 7, 1393, 2048 }, { 7, 1394, 2048 }, { 8, 1395, 2048 }, { 7, 1396, 2048 }, { 8, 1397, 2048 }, { 8, 1398, 2048 }, { 9, 1399, 2048 }, 
+   { 7, 1400, 2048 }, { 8, 1401, 2048 }, { 8, 1402, 2048 }, { 9, 1403, 2048 }, { 8, 1404, 2048 }, { 9, 1405, 2048 }, { 9, 1406, 2048 }, { 10, 1407, 2048 }, 
+   { 4, 1408, 2048 }, { 5, 1409, 2048 }, { 5, 1410, 2048 }, { 6, 1411, 2048 }, { 5, 1412, 2048 }, { 6, 1413, 2048 }, { 6, 1414, 2048 }, { 7, 1415, 2048 }, 
+   { 5, 1416, 2048 }, { 6, 1417, 2048 }, { 6, 1418, 2048 }, { 7, 1419, 2048 }, { 6, 1420, 2048 }, { 7, 1421, 2048 }, { 7, 1422, 2048 }, { 8, 1423, 2048 }, 
+   { 5, 1424, 2048 }, { 6, 1425, 2048 }, { 6, 1426, 2048 }, { 7, 1427, 2048 }, { 6, 1428, 2048 }, { 7, 1429, 2048 }, { 7, 1430, 2048 }, { 8, 1431, 2048 }, 
+   { 6, 1432, 2048 }, { 7, 1433, 2048 }, { 7, 1434, 2048 }, { 8, 1435, 2048 }, { 7, 1436, 2048 }, { 8, 1437, 2048 }, { 8, 1438, 2048 }, { 9, 1439, 2048 }, 
+   { 5, 1440, 2048 }, { 6, 1441, 2048 }, { 6, 1442, 2048 }, { 7, 1443, 2048 }, { 6, 1444, 2048 }, { 7, 1445, 2048 }, { 7, 1446, 2048 }, { 8, 1447, 2048 }, 
+   { 6, 1448, 2048 }, { 7, 1449, 2048 }, { 7, 1450, 2048 }, { 8, 1451, 2048 }, { 7, 1452, 2048 }, { 8, 1453, 2048 }, { 8, 1454, 2048 }, { 9, 1455, 2048 }, 
+   { 6, 1456, 2048 }, { 7, 1457, 2048 }, { 7, 1458, 2048 }, { 8, 1459, 2048 }, { 7, 1460, 2048 }, { 8, 1461, 2048 }, { 8, 1462, 2048 }, { 9, 1463, 2048 }, 
+   { 7, 1464, 2048 }, { 8, 1465, 2048 }, { 8, 1466, 2048 }, { 9, 1467, 2048 }, { 8, 1468, 2048 }, { 9, 1469, 2048 }, { 9, 1470, 2048 }, { 10, 1471, 2048 }, 
+   { 5, 1472, 2048 }, { 6, 1473, 2048 }, { 6, 1474, 2048 }, { 7, 1475, 2048 }, { 6, 1476, 2048 }, { 7, 1477, 2048 }, { 7, 1478, 2048 }, { 8, 1479, 2048 }, 
+   { 6, 1480, 2048 }, { 7, 1481, 2048 }, { 7, 1482, 2048 }, { 8, 1483, 2048 }, { 7, 1484, 2048 }, { 8, 1485, 2048 }, { 8, 1486, 2048 }, { 9, 1487, 2048 }, 
+   { 6, 1488, 2048 }, { 7, 1489, 2048 }, { 7, 1490, 2048 }, { 8, 1491, 2048 }, { 7, 1492, 2048 }, { 8, 1493, 2048 }, { 8, 1494, 2048 }, { 9, 1495, 2048 }, 
+   { 7, 1496, 2048 }, { 8, 1497, 2048 }, { 8, 1498, 2048 }, { 9, 1499, 2048 }, { 8, 1500, 2048 }, { 9, 1501, 2048 }, { 9, 1502, 2048 }, { 10, 1503, 2048 }, 
+   { 6, 1504, 2048 }, { 7, 1505, 2048 }, { 7, 1506, 2048 }, { 8, 1507, 2048 }, { 7, 1508, 2048 }, { 8, 1509, 2048 }, { 8, 1510, 2048 }, { 9, 1511, 2048 }, 
+   { 7, 1512, 2048 }, { 8, 1513, 2048 }, { 8, 1514, 2048 }, { 9, 1515, 2048 }, { 8, 1516, 2048 }, { 9, 1517, 2048 }, { 9, 1518, 2048 }, { 10, 1519, 2048 }, 
+   { 7, 1520, 2048 }, { 8, 1521, 2048 }, { 8, 1522, 2048 }, { 9, 1523, 2048 }, { 8, 1524, 2048 }, { 9, 1525, 2048 }, { 9, 1526, 2048 }, { 10, 1527, 2048 }, 
+   { 8, 1528, 2048 }, { 9, 1529, 2048 }, { 9, 1530, 2048 }, { 10, 1531, 2048 }, { 9, 1532, 2048 }, { 10, 1533, 2048 }, { 10, 1534, 2048 }, { 11, 1535, 2048 }, 
+   { 3, 1536, 2048 }, { 4, 1537, 2048 }, { 4, 1538, 2048 }, { 5, 1539, 2048 }, { 4, 1540, 2048 }, { 5, 1541, 2048 }, { 5, 1542, 2048 }, { 6, 1543, 2048 }, 
+   { 4, 1544, 2048 }, { 5, 1545, 2048 }, { 5, 1546, 2048 }, { 6, 1547, 2048 }, { 5, 1548, 2048 }, { 6, 1549, 2048 }, { 6, 1550, 2048 }, { 7, 1551, 2048 }, 
+   { 4, 1552, 2048 }, { 5, 1553, 2048 }, { 5, 1554, 2048 }, { 6, 1555, 2048 }, { 5, 1556, 2048 }, { 6, 1557, 2048 }, { 6, 1558, 2048 }, { 7, 1559, 2048 }, 
+   { 5, 1560, 2048 }, { 6, 1561, 2048 }, { 6, 1562, 2048 }, { 7, 1563, 2048 }, { 6, 1564, 2048 }, { 7, 1565, 2048 }, { 7, 1566, 2048 }, { 8, 1567, 2048 }, 
+   { 4, 1568, 2048 }, { 5, 1569, 2048 }, { 5, 1570, 2048 }, { 6, 1571, 2048 }, { 5, 1572, 2048 }, { 6, 1573, 2048 }, { 6, 1574, 2048 }, { 7, 1575, 2048 }, 
+   { 5, 1576, 2048 }, { 6, 1577, 2048 }, { 6, 1578, 2048 }, { 7, 1579, 2048 }, { 6, 1580, 2048 }, { 7, 1581, 2048 }, { 7, 1582, 2048 }, { 8, 1583, 2048 }, 
+   { 5, 1584, 2048 }, { 6, 1585, 2048 }, { 6, 1586, 2048 }, { 7, 1587, 2048 }, { 6, 1588, 2048 }, { 7, 1589, 2048 }, { 7, 1590, 2048 }, { 8, 1591, 2048 }, 
+   { 6, 1592, 2048 }, { 7, 1593, 2048 }, { 7, 1594, 2048 }, { 8, 1595, 2048 }, { 7, 1596, 2048 }, { 8, 1597, 2048 }, { 8, 1598, 2048 }, { 9, 1599, 2048 }, 
+   { 4, 1600, 2048 }, { 5, 1601, 2048 }, { 5, 1602, 2048 }, { 6, 1603, 2048 }, { 5, 1604, 2048 }, { 6, 1605, 2048 }, { 6, 1606, 2048 }, { 7, 1607, 2048 }, 
+   { 5, 1608, 2048 }, { 6, 1609, 2048 }, { 6, 1610, 2048 }, { 7, 1611, 2048 }, { 6, 1612, 2048 }, { 7, 1613, 2048 }, { 7, 1614, 2048 }, { 8, 1615, 2048 }, 
+   { 5, 1616, 2048 }, { 6, 1617, 2048 }, { 6, 1618, 2048 }, { 7, 1619, 2048 }, { 6, 1620, 2048 }, { 7, 1621, 2048 }, { 7, 1622, 2048 }, { 8, 1623, 2048 }, 
+   { 6, 1624, 2048 }, { 7, 1625, 2048 }, { 7, 1626, 2048 }, { 8, 1627, 2048 }, { 7, 1628, 2048 }, { 8, 1629, 2048 }, { 8, 1630, 2048 }, { 9, 1631, 2048 }, 
+   { 5, 1632, 2048 }, { 6, 1633, 2048 }, { 6, 1634, 2048 }, { 7, 1635, 2048 }, { 6, 1636, 2048 }, { 7, 1637, 2048 }, { 7, 1638, 2048 }, { 8, 1639, 2048 }, 
+   { 6, 1640, 2048 }, { 7, 1641, 2048 }, { 7, 1642, 2048 }, { 8, 1643, 2048 }, { 7, 1644, 2048 }, { 8, 1645, 2048 }, { 8, 1646, 2048 }, { 9, 1647, 2048 }, 
+   { 6, 1648, 2048 }, { 7, 1649, 2048 }, { 7, 1650, 2048 }, { 8, 1651, 2048 }, { 7, 1652, 2048 }, { 8, 1653, 2048 }, { 8, 1654, 2048 }, { 9, 1655, 2048 }, 
+   { 7, 1656, 2048 }, { 8, 1657, 2048 }, { 8, 1658, 2048 }, { 9, 1659, 2048 }, { 8, 1660, 2048 }, { 9, 1661, 2048 }, { 9, 1662, 2048 }, { 10, 1663, 2048 }, 
+   { 4, 1664, 2048 }, { 5, 1665, 2048 }, { 5, 1666, 2048 }, { 6, 1667, 2048 }, { 5, 1668, 2048 }, { 6, 1669, 2048 }, { 6, 1670, 2048 }, { 7, 1671, 2048 }, 
+   { 5, 1672, 2048 }, { 6, 1673, 2048 }, { 6, 1674, 2048 }, { 7, 1675, 2048 }, { 6, 1676, 2048 }, { 7, 1677, 2048 }, { 7, 1678, 2048 }, { 8, 1679, 2048 }, 
+   { 5, 1680, 2048 }, { 6, 1681, 2048 }, { 6, 1682, 2048 }, { 7, 1683, 2048 }, { 6, 1684, 2048 }, { 7, 1685, 2048 }, { 7, 1686, 2048 }, { 8, 1687, 2048 }, 
+   { 6, 1688, 2048 }, { 7, 1689, 2048 }, { 7, 1690, 2048 }, { 8, 1691, 2048 }, { 7, 1692, 2048 }, { 8, 1693, 2048 }, { 8, 1694, 2048 }, { 9, 1695, 2048 }, 
+   { 5, 1696, 2048 }, { 6, 1697, 2048 }, { 6, 1698, 2048 }, { 7, 1699, 2048 }, { 6, 1700, 2048 }, { 7, 1701, 2048 }, { 7, 1702, 2048 }, { 8, 1703, 2048 }, 
+   { 6, 1704, 2048 }, { 7, 1705, 2048 }, { 7, 1706, 2048 }, { 8, 1707, 2048 }, { 7, 1708, 2048 }, { 8, 1709, 2048 }, { 8, 1710, 2048 }, { 9, 1711, 2048 }, 
+   { 6, 1712, 2048 }, { 7, 1713, 2048 }, { 7, 1714, 2048 }, { 8, 1715, 2048 }, { 7, 1716, 2048 }, { 8, 1717, 2048 }, { 8, 1718, 2048 }, { 9, 1719, 2048 }, 
+   { 7, 1720, 2048 }, { 8, 1721, 2048 }, { 8, 1722, 2048 }, { 9, 1723, 2048 }, { 8, 1724, 2048 }, { 9, 1725, 2048 }, { 9, 1726, 2048 }, { 10, 1727, 2048 }, 
+   { 5, 1728, 2048 }, { 6, 1729, 2048 }, { 6, 1730, 2048 }, { 7, 1731, 2048 }, { 6, 1732, 2048 }, { 7, 1733, 2048 }, { 7, 1734, 2048 }, { 8, 1735, 2048 }, 
+   { 6, 1736, 2048 }, { 7, 1737, 2048 }, { 7, 1738, 2048 }, { 8, 1739, 2048 }, { 7, 1740, 2048 }, { 8, 1741, 2048 }, { 8, 1742, 2048 }, { 9, 1743, 2048 }, 
+   { 6, 1744, 2048 }, { 7, 1745, 2048 }, { 7, 1746, 2048 }, { 8, 1747, 2048 }, { 7, 1748, 2048 }, { 8, 1749, 2048 }, { 8, 1750, 2048 }, { 9, 1751, 2048 }, 
+   { 7, 1752, 2048 }, { 8, 1753, 2048 }, { 8, 1754, 2048 }, { 9, 1755, 2048 }, { 8, 1756, 2048 }, { 9, 1757, 2048 }, { 9, 1758, 2048 }, { 10, 1759, 2048 }, 
+   { 6, 1760, 2048 }, { 7, 1761, 2048 }, { 7, 1762, 2048 }, { 8, 1763, 2048 }, { 7, 1764, 2048 }, { 8, 1765, 2048 }, { 8, 1766, 2048 }, { 9, 1767, 2048 }, 
+   { 7, 1768, 2048 }, { 8, 1769, 2048 }, { 8, 1770, 2048 }, { 9, 1771, 2048 }, { 8, 1772, 2048 }, { 9, 1773, 2048 }, { 9, 1774, 2048 }, { 10, 1775, 2048 }, 
+   { 7, 1776, 2048 }, { 8, 1777, 2048 }, { 8, 1778, 2048 }, { 9, 1779, 2048 }, { 8, 1780, 2048 }, { 9, 1781, 2048 }, { 9, 1782, 2048 }, { 10, 1783, 2048 }, 
+   { 8, 1784, 2048 }, { 9, 1785, 2048 }, { 9, 1786, 2048 }, { 10, 1787, 2048 }, { 9, 1788, 2048 }, { 10, 1789, 2048 }, { 10, 1790, 2048 }, { 11, 1791, 2048 }, 
+   { 4, 1792, 2048 }, { 5, 1793, 2048 }, { 5, 1794, 2048 }, { 6, 1795, 2048 }, { 5, 1796, 2048 }, { 6, 1797, 2048 }, { 6, 1798, 2048 }, { 7, 1799, 2048 }, 
+   { 5, 1800, 2048 }, { 6, 1801, 2048 }, { 6, 1802, 2048 }, { 7, 1803, 2048 }, { 6, 1804, 2048 }, { 7, 1805, 2048 }, { 7, 1806, 2048 }, { 8, 1807, 2048 }, 
+   { 5, 1808, 2048 }, { 6, 1809, 2048 }, { 6, 1810, 2048 }, { 7, 1811, 2048 }, { 6, 1812, 2048 }, { 7, 1813, 2048 }, { 7, 1814, 2048 }, { 8, 1815, 2048 }, 
+   { 6, 1816, 2048 }, { 7, 1817, 2048 }, { 7, 1818, 2048 }, { 8, 1819, 2048 }, { 7, 1820, 2048 }, { 8, 1821, 2048 }, { 8, 1822, 2048 }, { 9, 1823, 2048 }, 
+   { 5, 1824, 2048 }, { 6, 1825, 2048 }, { 6, 1826, 2048 }, { 7, 1827, 2048 }, { 6, 1828, 2048 }, { 7, 1829, 2048 }, { 7, 1830, 2048 }, { 8, 1831, 2048 }, 
+   { 6, 1832, 2048 }, { 7, 1833, 2048 }, { 7, 1834, 2048 }, { 8, 1835, 2048 }, { 7, 1836, 2048 }, { 8, 1837, 2048 }, { 8, 1838, 2048 }, { 9, 1839, 2048 }, 
+   { 6, 1840, 2048 }, { 7, 1841, 2048 }, { 7, 1842, 2048 }, { 8, 1843, 2048 }, { 7, 1844, 2048 }, { 8, 1845, 2048 }, { 8, 1846, 2048 }, { 9, 1847, 2048 }, 
+   { 7, 1848, 2048 }, { 8, 1849, 2048 }, { 8, 1850, 2048 }, { 9, 1851, 2048 }, { 8, 1852, 2048 }, { 9, 1853, 2048 }, { 9, 1854, 2048 }, { 10, 1855, 2048 }, 
+   { 5, 1856, 2048 }, { 6, 1857, 2048 }, { 6, 1858, 2048 }, { 7, 1859, 2048 }, { 6, 1860, 2048 }, { 7, 1861, 2048 }, { 7, 1862, 2048 }, { 8, 1863, 2048 }, 
+   { 6, 1864, 2048 }, { 7, 1865, 2048 }, { 7, 1866, 2048 }, { 8, 1867, 2048 }, { 7, 1868, 2048 }, { 8, 1869, 2048 }, { 8, 1870, 2048 }, { 9, 1871, 2048 }, 
+   { 6, 1872, 2048 }, { 7, 1873, 2048 }, { 7, 1874, 2048 }, { 8, 1875, 2048 }, { 7, 1876, 2048 }, { 8, 1877, 2048 }, { 8, 1878, 2048 }, { 9, 1879, 2048 }, 
+   { 7, 1880, 2048 }, { 8, 1881, 2048 }, { 8, 1882, 2048 }, { 9, 1883, 2048 }, { 8, 1884, 2048 }, { 9, 1885, 2048 }, { 9, 1886, 2048 }, { 10, 1887, 2048 }, 
+   { 6, 1888, 2048 }, { 7, 1889, 2048 }, { 7, 1890, 2048 }, { 8, 1891, 2048 }, { 7, 1892, 2048 }, { 8, 1893, 2048 }, { 8, 1894, 2048 }, { 9, 1895, 2048 }, 
+   { 7, 1896, 2048 }, { 8, 1897, 2048 }, { 8, 1898, 2048 }, { 9, 1899, 2048 }, { 8, 1900, 2048 }, { 9, 1901, 2048 }, { 9, 1902, 2048 }, { 10, 1903, 2048 }, 
+   { 7, 1904, 2048 }, { 8, 1905, 2048 }, { 8, 1906, 2048 }, { 9, 1907, 2048 }, { 8, 1908, 2048 }, { 9, 1909, 2048 }, { 9, 1910, 2048 }, { 10, 1911, 2048 }, 
+   { 8, 1912, 2048 }, { 9, 1913, 2048 }, { 9, 1914, 2048 }, { 10, 1915, 2048 }, { 9, 1916, 2048 }, { 10, 1917, 2048 }, { 10, 1918, 2048 }, { 11, 1919, 2048 }, 
+   { 5, 1920, 2048 }, { 6, 1921, 2048 }, { 6, 1922, 2048 }, { 7, 1923, 2048 }, { 6, 1924, 2048 }, { 7, 1925, 2048 }, { 7, 1926, 2048 }, { 8, 1927, 2048 }, 
+   { 6, 1928, 2048 }, { 7, 1929, 2048 }, { 7, 1930, 2048 }, { 8, 1931, 2048 }, { 7, 1932, 2048 }, { 8, 1933, 2048 }, { 8, 1934, 2048 }, { 9, 1935, 2048 }, 
+   { 6, 1936, 2048 }, { 7, 1937, 2048 }, { 7, 1938, 2048 }, { 8, 1939, 2048 }, { 7, 1940, 2048 }, { 8, 1941, 2048 }, { 8, 1942, 2048 }, { 9, 1943, 2048 }, 
+   { 7, 1944, 2048 }, { 8, 1945, 2048 }, { 8, 1946, 2048 }, { 9, 1947, 2048 }, { 8, 1948, 2048 }, { 9, 1949, 2048 }, { 9, 1950, 2048 }, { 10, 1951, 2048 }, 
+   { 6, 1952, 2048 }, { 7, 1953, 2048 }, { 7, 1954, 2048 }, { 8, 1955, 2048 }, { 7, 1956, 2048 }, { 8, 1957, 2048 }, { 8, 1958, 2048 }, { 9, 1959, 2048 }, 
+   { 7, 1960, 2048 }, { 8, 1961, 2048 }, { 8, 1962, 2048 }, { 9, 1963, 2048 }, { 8, 1964, 2048 }, { 9, 1965, 2048 }, { 9, 1966, 2048 }, { 10, 1967, 2048 }, 
+   { 7, 1968, 2048 }, { 8, 1969, 2048 }, { 8, 1970, 2048 }, { 9, 1971, 2048 }, { 8, 1972, 2048 }, { 9, 1973, 2048 }, { 9, 1974, 2048 }, { 10, 1975, 2048 }, 
+   { 8, 1976, 2048 }, { 9, 1977, 2048 }, { 9, 1978, 2048 }, { 10, 1979, 2048 }, { 9, 1980, 2048 }, { 10, 1981, 2048 }, { 10, 1982, 2048 }, { 11, 1983, 2048 }, 
+   { 6, 1984, 2048 }, { 7, 1985, 2048 }, { 7, 1986, 2048 }, { 8, 1987, 2048 }, { 7, 1988, 2048 }, { 8, 1989, 2048 }, { 8, 1990, 2048 }, { 9, 1991, 2048 }, 
+   { 7, 1992, 2048 }, { 8, 1993, 2048 }, { 8, 1994, 2048 }, { 9, 1995, 2048 }, { 8, 1996, 2048 }, { 9, 1997, 2048 }, { 9, 1998, 2048 }, { 10, 1999, 2048 }, 
+   { 7, 2000, 2048 }, { 8, 2001, 2048 }, { 8, 2002, 2048 }, { 9, 2003, 2048 }, { 8, 2004, 2048 }, { 9, 2005, 2048 }, { 9, 2006, 2048 }, { 10, 2007, 2048 }, 
+   { 8, 2008, 2048 }, { 9, 2009, 2048 }, { 9, 2010, 2048 }, { 10, 2011, 2048 }, { 9, 2012, 2048 }, { 10, 2013, 2048 }, { 10, 2014, 2048 }, { 11, 2015, 2048 }, 
+   { 7, 2016, 2048 }, { 8, 2017, 2048 }, { 8, 2018, 2048 }, { 9, 2019, 2048 }, { 8, 2020, 2048 }, { 9, 2021, 2048 }, { 9, 2022, 2048 }, { 10, 2023, 2048 }, 
+   { 8, 2024, 2048 }, { 9, 2025, 2048 }, { 9, 2026, 2048 }, { 10, 2027, 2048 }, { 9, 2028, 2048 }, { 10, 2029, 2048 }, { 10, 2030, 2048 }, { 11, 2031, 2048 }, 
+   { 8, 2032, 2048 }, { 9, 2033, 2048 }, { 9, 2034, 2048 }, { 10, 2035, 2048 }, { 9, 2036, 2048 }, { 10, 2037, 2048 }, { 10, 2038, 2048 }, { 11, 2039, 2048 }, 
+   { 9, 2040, 2048 }, { 10, 2041, 2048 }, { 10, 2042, 2048 }, { 11, 2043, 2048 }, { 10, 2044, 2048 }, { 11, 2045, 2048 }, { 11, 2046, 2048 }, { 12, 2047, 2048 }, 
+#endif
+#endif
+#endif
+#endif
+#endif
+#endif
+};
+
+/* find a hole and free as required, return -1 if no hole found */
+static int find_hole(void)
+{
+   unsigned x;
+   int      y, z;
+   for (z = -1, y = INT_MAX, x = 0; x < FP_ENTRIES; x++) {
+       if (fp_cache[x].lru_count < y && fp_cache[x].lock == 0) {
+          z = x;
+          y = fp_cache[x].lru_count;
+       }
+   }
+
+   /* decrease all */
+   for (x = 0; x < FP_ENTRIES; x++) {
+      if (fp_cache[x].lru_count > 3) {
+         --(fp_cache[x].lru_count);
+      }
+   }
+
+   /* free entry z */
+   if (z >= 0 && fp_cache[z].g) {
+      mp_clear(&fp_cache[z].mu);
+      ecc_del_point(fp_cache[z].g);
+      fp_cache[z].g  = NULL;
+      for (x = 0; x < (1U<x, g->x) == MP_EQ && 
+          mp_cmp(fp_cache[x].g->y, g->y) == MP_EQ && 
+          mp_cmp(fp_cache[x].g->z, g->z) == MP_EQ) {
+         break;
+      }
+   }
+   if (x == FP_ENTRIES) {
+      x = -1;
+   }
+   return x;
+}
+
+/* add a new base to the cache */
+static int add_entry(int idx, ecc_point *g)
+{
+   unsigned x, y;
+
+   /* allocate base and LUT */
+   fp_cache[idx].g = ecc_new_point();
+   if (fp_cache[idx].g == NULL) {
+      return GEN_MEM_ERR;
+   }
+
+   /* copy x and y */
+   if ((mp_copy(g->x, fp_cache[idx].g->x) != MP_OKAY) ||
+       (mp_copy(g->y, fp_cache[idx].g->y) != MP_OKAY) ||
+       (mp_copy(g->z, fp_cache[idx].g->z) != MP_OKAY)) {
+      ecc_del_point(fp_cache[idx].g);
+      fp_cache[idx].g = NULL;
+      return GEN_MEM_ERR;
+   }              
+
+   for (x = 0; x < (1U<x, mu, modulus,
+                  fp_cache[idx].LUT[1]->x) != MP_OKAY) || 
+         (mp_mulmod(fp_cache[idx].g->y, mu, modulus,
+                  fp_cache[idx].LUT[1]->y) != MP_OKAY) || 
+         (mp_mulmod(fp_cache[idx].g->z, mu, modulus,
+                  fp_cache[idx].LUT[1]->z) != MP_OKAY)) {
+       err = MP_MULMOD_E; 
+     }
+   }
+       
+   /* make all single bit entries */
+   for (x = 1; x < FP_LUT; x++) {
+      if (err != MP_OKAY)
+          break;
+      if ((mp_copy(fp_cache[idx].LUT[1<<(x-1)]->x,
+                   fp_cache[idx].LUT[1<x) != MP_OKAY) || 
+          (mp_copy(fp_cache[idx].LUT[1<<(x-1)]->y,
+                   fp_cache[idx].LUT[1<y) != MP_OKAY) || 
+          (mp_copy(fp_cache[idx].LUT[1<<(x-1)]->z,
+                   fp_cache[idx].LUT[1<z) != MP_OKAY)){
+          err = MP_INIT_E;
+          break;
+      } else {
+          
+         /* now double it bitlen/FP_LUT times */
+         for (y = 0; y < lut_gap; y++) {
+             if ((err = ecc_projective_dbl_point(fp_cache[idx].LUT[1<z, modulus, *mp);
+ 
+       /* invert it */
+       if (err == MP_OKAY)
+         err = mp_invmod(fp_cache[idx].LUT[x]->z, modulus,
+                         fp_cache[idx].LUT[x]->z);
+
+       if (err == MP_OKAY)
+         /* now square it */
+         err = mp_sqrmod(fp_cache[idx].LUT[x]->z, modulus, &tmp);
+       
+       if (err == MP_OKAY)
+         /* fix x */
+         err = mp_mulmod(fp_cache[idx].LUT[x]->x, &tmp, modulus,
+                         fp_cache[idx].LUT[x]->x);
+
+       if (err == MP_OKAY)
+         /* get 1/z^3 */
+         err = mp_mulmod(&tmp, fp_cache[idx].LUT[x]->z, modulus, &tmp);
+
+       if (err == MP_OKAY)
+         /* fix y */
+         err = mp_mulmod(fp_cache[idx].LUT[x]->y, &tmp, modulus,
+                         fp_cache[idx].LUT[x]->y);
+
+       if (err == MP_OKAY)
+         /* free z */
+         mp_clear(fp_cache[idx].LUT[x]->z);
+   }
+   mp_clear(&tmp);
+
+   if (err == MP_OKAY)
+     return MP_OKAY;
+
+   /* err cleanup */
+   for (y = 0; y < (1U< mp_unsigned_bin_size(modulus)) {
+      mp_int order;
+      if (mp_init(&order) != MP_OKAY) {
+        mp_clear(&tk);
+        return MP_INIT_E;
+      }
+
+      /* find order */
+      y = mp_unsigned_bin_size(modulus);
+      for (x = 0; ecc_sets[x].size; x++) {
+         if (y <= (unsigned)ecc_sets[x].size) break;
+      }
+   
+      /* back off if we are on the 521 bit curve */
+      if (y == 66) --x;
+      
+      if ((err = mp_read_radix(&order, ecc_sets[x].order, 16)) != MP_OKAY) {
+         mp_clear(&order);
+         mp_clear(&tk);
+         return err;
+      }
+
+      /* k must be less than modulus */
+      if (mp_cmp(k, &order) != MP_LT) {
+         if ((err = mp_mod(k, &order, &tk)) != MP_OKAY) {
+            mp_clear(&tk);
+            mp_clear(&order);
+            return err;
+         }
+      } else {
+         mp_copy(k, &tk);
+      }
+      mp_clear(&order);
+   } else {
+      mp_copy(k, &tk);
+   }       
+   
+   /* get bitlen and round up to next multiple of FP_LUT */
+   bitlen  = mp_unsigned_bin_size(modulus) << 3;
+   x       = bitlen % FP_LUT;
+   if (x) {
+      bitlen += FP_LUT - x;
+   }  
+   lut_gap = bitlen / FP_LUT;
+        
+   /* get the k value */
+   if (mp_unsigned_bin_size(&tk) > (int)(KB_SIZE - 2)) {
+      mp_clear(&tk);
+      return BUFFER_E;
+   }
+   
+   /* store k */
+#ifdef WOLFSSL_SMALL_STACK
+   kb = (unsigned char*)XMALLOC(KB_SIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+   if (kb == NULL)
+      return MEMORY_E;
+#endif
+
+   XMEMSET(kb, 0, KB_SIZE);
+   if ((err = mp_to_unsigned_bin(&tk, kb)) != MP_OKAY) {
+      mp_clear(&tk);
+   }
+   else {
+      /* let's reverse kb so it's little endian */
+      x = 0;
+      y = mp_unsigned_bin_size(&tk) - 1;
+      mp_clear(&tk);
+
+      while ((unsigned)x < y) {
+         z = kb[x]; kb[x] = kb[y]; kb[y] = z;
+         ++x; --y;
+      }
+
+      /* at this point we can start, yipee */
+      first = 1;
+      for (x = lut_gap-1; x >= 0; x--) {
+          /* extract FP_LUT bits from kb spread out by lut_gap bits and offset
+             by x bits from the start */
+          bitpos = x;
+          for (y = z = 0; y < FP_LUT; y++) {
+             z |= ((kb[bitpos>>3] >> (bitpos&7)) & 1) << y;
+             bitpos += lut_gap;  /* it's y*lut_gap + x, but here we can avoid
+                                    the mult in each loop */
+          }
+
+          /* double if not first */
+          if (!first) {
+             if ((err = ecc_projective_dbl_point(R, R, modulus,
+                                                              mp)) != MP_OKAY) {
+                break;
+             }
+          }
+
+          /* add if not first, otherwise copy */
+          if (!first && z) {
+             if ((err = ecc_projective_add_point(R, fp_cache[idx].LUT[z], R,
+                                                     modulus, mp)) != MP_OKAY) {
+                break;
+             }
+          } else if (z) {
+             if ((mp_copy(fp_cache[idx].LUT[z]->x, R->x) != MP_OKAY) ||
+                 (mp_copy(fp_cache[idx].LUT[z]->y, R->y) != MP_OKAY) ||
+                 (mp_copy(&fp_cache[idx].mu,       R->z) != MP_OKAY)) {
+                 err = GEN_MEM_ERR;
+                 break;
+             }
+                 first = 0;
+          }
+      }
+   }
+
+   if (err == MP_OKAY) {
+      z = 0;
+      ForceZero(kb, KB_SIZE);
+      /* map R back from projective space */
+      if (map) {
+         err = ecc_map(R, modulus, mp);
+      } else {
+         err = MP_OKAY;
+      }
+   }
+
+#ifdef WOLFSSL_SMALL_STACK
+   XFREE(kb, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+#undef KB_SIZE
+
+   return err;
+}
+
+#ifdef ECC_SHAMIR
+/* perform a fixed point ECC mulmod */
+static int accel_fp_mul2add(int idx1, int idx2, 
+                            mp_int* kA, mp_int* kB,
+                            ecc_point *R, mp_int* modulus, mp_digit* mp)
+{
+#define KB_SIZE 128
+
+#ifdef WOLFSSL_SMALL_STACK
+   unsigned char* kb[2];
+#else
+   unsigned char kb[2][128];
+#endif
+   int      x;
+   unsigned y, z, err, bitlen, bitpos, lut_gap, first, zA, zB;
+   mp_int tka;
+   mp_int tkb;
+   mp_int order;
+
+   if (mp_init_multi(&tka, &tkb, 0, 0, 0, 0) != MP_OKAY)
+       return MP_INIT_E;
+
+   /* if it's smaller than modulus we fine */
+   if (mp_unsigned_bin_size(kA) > mp_unsigned_bin_size(modulus)) {
+      /* find order */
+      y = mp_unsigned_bin_size(modulus);
+      for (x = 0; ecc_sets[x].size; x++) {
+         if (y <= (unsigned)ecc_sets[x].size) break;
+      }
+   
+      /* back off if we are on the 521 bit curve */
+      if (y == 66) --x;
+      
+      if ((err = mp_init(&order)) != MP_OKAY) {
+         mp_clear(&tkb);
+         mp_clear(&tka);
+         return err;
+      }      
+      if ((err = mp_read_radix(&order, ecc_sets[x].order, 16)) != MP_OKAY) {
+         mp_clear(&tkb);
+         mp_clear(&tka);
+         mp_clear(&order);
+         return err;
+      }
+
+      /* kA must be less than modulus */
+      if (mp_cmp(kA, &order) != MP_LT) {
+         if ((err = mp_mod(kA, &order, &tka)) != MP_OKAY) {
+            mp_clear(&tkb);
+            mp_clear(&tka);
+            mp_clear(&order);
+            return err;
+         }
+      } else {
+         mp_copy(kA, &tka);
+      }
+      mp_clear(&order);
+   } else {
+      mp_copy(kA, &tka);
+   }       
+
+   /* if it's smaller than modulus we fine */
+   if (mp_unsigned_bin_size(kB) > mp_unsigned_bin_size(modulus)) {
+      /* find order */
+      y = mp_unsigned_bin_size(modulus);
+      for (x = 0; ecc_sets[x].size; x++) {
+         if (y <= (unsigned)ecc_sets[x].size) break;
+      }
+   
+      /* back off if we are on the 521 bit curve */
+      if (y == 66) --x;
+      
+      if ((err = mp_init(&order)) != MP_OKAY) {
+         mp_clear(&tkb);
+         mp_clear(&tka);
+         return err;
+      }      
+      if ((err = mp_read_radix(&order, ecc_sets[x].order, 16)) != MP_OKAY) {
+         mp_clear(&tkb);
+         mp_clear(&tka);
+         mp_clear(&order);
+         return err;
+      }
+
+      /* kB must be less than modulus */
+      if (mp_cmp(kB, &order) != MP_LT) {
+         if ((err = mp_mod(kB, &order, &tkb)) != MP_OKAY) {
+            mp_clear(&tkb);
+            mp_clear(&tka);
+            mp_clear(&order);
+            return err;
+         }
+      } else {
+         mp_copy(kB, &tkb);
+      }
+      mp_clear(&order);
+   } else {
+      mp_copy(kB, &tkb);
+   }     
+
+   /* get bitlen and round up to next multiple of FP_LUT */
+   bitlen  = mp_unsigned_bin_size(modulus) << 3;
+   x       = bitlen % FP_LUT;
+   if (x) {
+      bitlen += FP_LUT - x;
+   }  
+   lut_gap = bitlen / FP_LUT;
+        
+   /* get the k value */
+   if ((mp_unsigned_bin_size(&tka) > (int)(KB_SIZE - 2)) ||
+       (mp_unsigned_bin_size(&tkb) > (int)(KB_SIZE - 2))  ) {
+      mp_clear(&tka);
+      mp_clear(&tkb);
+      return BUFFER_E;
+   }
+   
+   /* store k */
+#ifdef WOLFSSL_SMALL_STACK
+   kb[0] = (unsigned char*)XMALLOC(KB_SIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+   if (kb[0] == NULL)
+      return MEMORY_E;
+#endif
+
+   XMEMSET(kb[0], 0, KB_SIZE);
+   if ((err = mp_to_unsigned_bin(&tka, kb[0])) != MP_OKAY) {
+      mp_clear(&tka);
+      mp_clear(&tkb);
+      XFREE(kb[0], NULL, DYNAMIC_TYPE_TMP_BUFFER);
+      return err;
+   }
+   
+   /* let's reverse kb so it's little endian */
+   x = 0;
+   y = mp_unsigned_bin_size(&tka) - 1;
+   mp_clear(&tka);
+   while ((unsigned)x < y) {
+      z = kb[0][x]; kb[0][x] = kb[0][y]; kb[0][y] = z;
+      ++x; --y;
+   }      
+   
+   /* store b */
+#ifdef WOLFSSL_SMALL_STACK
+   kb[1] = (unsigned char*)XMALLOC(KB_SIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+   if (kb[1] == NULL) {
+      XFREE(kb[0], NULL, DYNAMIC_TYPE_TMP_BUFFER);
+      return MEMORY_E;
+   }
+#endif
+
+   XMEMSET(kb[1], 0, KB_SIZE);
+   if ((err = mp_to_unsigned_bin(&tkb, kb[1])) != MP_OKAY) {
+      mp_clear(&tkb);
+   }
+   else {
+      x = 0;
+      y = mp_unsigned_bin_size(&tkb) - 1;
+      mp_clear(&tkb);
+      while ((unsigned)x < y) {
+         z = kb[1][x]; kb[1][x] = kb[1][y]; kb[1][y] = z;
+         ++x; --y;
+      }
+
+      /* at this point we can start, yipee */
+      first = 1;
+      for (x = lut_gap-1; x >= 0; x--) {
+          /* extract FP_LUT bits from kb spread out by lut_gap bits and
+             offset by x bits from the start */
+          bitpos = x;
+          for (y = zA = zB = 0; y < FP_LUT; y++) {
+             zA |= ((kb[0][bitpos>>3] >> (bitpos&7)) & 1) << y;
+             zB |= ((kb[1][bitpos>>3] >> (bitpos&7)) & 1) << y;
+             bitpos += lut_gap;    /* it's y*lut_gap + x, but here we can avoid
+                                      the mult in each loop */
+          }
+
+          /* double if not first */
+          if (!first) {
+             if ((err = ecc_projective_dbl_point(R, R, modulus,
+                                                              mp)) != MP_OKAY) {
+                break;
+             }
+          }
+
+          /* add if not first, otherwise copy */
+          if (!first) {
+             if (zA) {
+                if ((err = ecc_projective_add_point(R, fp_cache[idx1].LUT[zA],
+                                                  R, modulus, mp)) != MP_OKAY) {
+                   break;
+                }
+             }
+             if (zB) {
+                if ((err = ecc_projective_add_point(R, fp_cache[idx2].LUT[zB],
+                                                  R, modulus, mp)) != MP_OKAY) {
+                   break;
+                }
+             }
+          } else {
+             if (zA) {
+                 if ((mp_copy(fp_cache[idx1].LUT[zA]->x, R->x) != MP_OKAY) ||
+                    (mp_copy(fp_cache[idx1].LUT[zA]->y,  R->y) != MP_OKAY) ||
+                    (mp_copy(&fp_cache[idx1].mu,         R->z) != MP_OKAY)) {
+                     err = GEN_MEM_ERR;
+                     break;
+                 }
+                    first = 0;
+             }
+             if (zB && first == 0) {
+                if (zB) {
+                   if ((err = ecc_projective_add_point(R,
+                           fp_cache[idx2].LUT[zB], R, modulus, mp)) != MP_OKAY){
+                      break;
+                   }
+                }
+             } else if (zB && first == 1) {
+                 if ((mp_copy(fp_cache[idx2].LUT[zB]->x, R->x) != MP_OKAY) ||
+                    (mp_copy(fp_cache[idx2].LUT[zB]->y, R->y) != MP_OKAY) ||
+                    (mp_copy(&fp_cache[idx2].mu,        R->z) != MP_OKAY)) {
+                     err = GEN_MEM_ERR;
+                     break;
+                 }
+                    first = 0;
+             }
+          }
+      }
+   }
+
+   ForceZero(kb[0], KB_SIZE);
+   ForceZero(kb[1], KB_SIZE);
+
+#ifdef WOLFSSL_SMALL_STACK
+   XFREE(kb[0], NULL, DYNAMIC_TYPE_TMP_BUFFER);
+   XFREE(kb[1], NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+#undef KB_SIZE
+
+   return ecc_map(R, modulus, mp);
+}
+
+/** ECC Fixed Point mulmod global
+  Computes kA*A + kB*B = C using Shamir's Trick
+  A        First point to multiply
+  kA       What to multiple A by
+  B        Second point to multiply
+  kB       What to multiple B by
+  C        [out] Destination point (can overlap with A or B)
+  modulus  Modulus for curve 
+  return MP_OKAY on success
+*/ 
+int ecc_mul2add(ecc_point* A, mp_int* kA,
+                ecc_point* B, mp_int* kB,
+                ecc_point* C, mp_int* modulus)
+{
+   int  idx1 = -1, idx2 = -1, err = MP_OKAY, mpInit = 0;
+   mp_digit mp;
+   mp_int   mu;
+  
+   err = mp_init(&mu);
+   if (err != MP_OKAY)
+       return err;
+
+#ifndef HAVE_THREAD_LS
+   if (initMutex == 0) {
+        InitMutex(&ecc_fp_lock);
+        initMutex = 1;
+   }
+   if (LockMutex(&ecc_fp_lock) != 0)
+      return BAD_MUTEX_E;
+#endif /* HAVE_THREAD_LS */
+
+      /* find point */
+      idx1 = find_base(A);
+
+      /* no entry? */
+      if (idx1 == -1) {
+         /* find hole and add it */
+         if ((idx1 = find_hole()) >= 0) {
+            err = add_entry(idx1, A);
+         }
+      }
+      if (err == MP_OKAY && idx1 != -1) {
+         /* increment LRU */
+         ++(fp_cache[idx1].lru_count);
+      }
+
+      if (err == MP_OKAY)
+        /* find point */
+        idx2 = find_base(B);
+
+      if (err == MP_OKAY) {
+        /* no entry? */
+        if (idx2 == -1) {
+           /* find hole and add it */
+           if ((idx2 = find_hole()) >= 0)
+              err = add_entry(idx2, B);
+         }
+      }
+
+      if (err == MP_OKAY && idx2 != -1) {
+         /* increment LRU */
+         ++(fp_cache[idx2].lru_count);
+      }
+
+      if (err == MP_OKAY) {
+        /* if it's 2 build the LUT, if it's higher just use the LUT */
+        if (idx1 >= 0 && fp_cache[idx1].lru_count == 2) {
+           /* compute mp */
+           err = mp_montgomery_setup(modulus, &mp);
+
+           if (err == MP_OKAY) {
+             mpInit = 1;
+             err = mp_montgomery_calc_normalization(&mu, modulus);
+           }
+                 
+           if (err == MP_OKAY)
+             /* build the LUT */
+               err = build_lut(idx1, modulus, &mp, &mu);
+        }
+      }
+
+      if (err == MP_OKAY) {
+        /* if it's 2 build the LUT, if it's higher just use the LUT */
+        if (idx2 >= 0 && fp_cache[idx2].lru_count == 2) {
+           if (mpInit == 0) {
+                /* compute mp */
+                err = mp_montgomery_setup(modulus, &mp);
+                if (err == MP_OKAY) {
+                    mpInit = 1;
+                    err = mp_montgomery_calc_normalization(&mu, modulus);
+                }
+            }
+                 
+            if (err == MP_OKAY) 
+            /* build the LUT */
+              err = build_lut(idx2, modulus, &mp, &mu);
+        }
+      }
+
+
+      if (err == MP_OKAY) {
+        if (idx1 >=0 && idx2 >= 0 && fp_cache[idx1].lru_count >= 2 &&
+                                     fp_cache[idx2].lru_count >= 2) {
+           if (mpInit == 0) {
+              /* compute mp */
+              err = mp_montgomery_setup(modulus, &mp);
+           }
+           if (err == MP_OKAY)
+             err = accel_fp_mul2add(idx1, idx2, kA, kB, C, modulus, &mp);
+        } else {
+           err = normal_ecc_mul2add(A, kA, B, kB, C, modulus);
+        }
+    }
+
+#ifndef HAVE_THREAD_LS
+    UnLockMutex(&ecc_fp_lock);
+#endif /* HAVE_THREAD_LS */
+    mp_clear(&mu);
+
+    return err;
+}
+#endif
+
+/** ECC Fixed Point mulmod global
+    k        The multiplicand
+    G        Base point to multiply
+    R        [out] Destination of product
+    modulus  The modulus for the curve
+    map      [boolean] If non-zero maps the point back to affine co-ordinates,
+             otherwise it's left in jacobian-montgomery form
+    return MP_OKAY if successful
+*/   
+int ecc_mulmod(mp_int* k, ecc_point *G, ecc_point *R, mp_int* modulus,
+               int map)
+{
+   int   idx, err = MP_OKAY;
+   mp_digit mp;
+   mp_int   mu;
+   int      mpSetup = 0;
+
+   if (mp_init(&mu) != MP_OKAY)
+       return MP_INIT_E;
+   
+#ifndef HAVE_THREAD_LS
+   if (initMutex == 0) {
+        InitMutex(&ecc_fp_lock);
+        initMutex = 1;
+   }
+   
+   if (LockMutex(&ecc_fp_lock) != 0)
+      return BAD_MUTEX_E;
+#endif /* HAVE_THREAD_LS */
+
+      /* find point */
+      idx = find_base(G);
+
+      /* no entry? */
+      if (idx == -1) {
+         /* find hole and add it */
+         idx = find_hole();
+
+         if (idx >= 0)
+            err = add_entry(idx, G);
+      }
+      if (err == MP_OKAY && idx >= 0) {
+         /* increment LRU */
+         ++(fp_cache[idx].lru_count);
+      }
+
+
+      if (err == MP_OKAY) { 
+        /* if it's 2 build the LUT, if it's higher just use the LUT */
+        if (idx >= 0 && fp_cache[idx].lru_count == 2) {
+           /* compute mp */
+           err = mp_montgomery_setup(modulus, &mp);
+
+           if (err == MP_OKAY) {
+             /* compute mu */
+             mpSetup = 1;
+             err = mp_montgomery_calc_normalization(&mu, modulus);
+           }
+                 
+           if (err == MP_OKAY) 
+             /* build the LUT */
+             err = build_lut(idx, modulus, &mp, &mu);
+        }
+      }
+
+      if (err == MP_OKAY) { 
+        if (idx >= 0 && fp_cache[idx].lru_count >= 2) {
+           if (mpSetup == 0) {
+              /* compute mp */
+              err = mp_montgomery_setup(modulus, &mp);
+           }
+           if (err == MP_OKAY)
+             err = accel_fp_mul(idx, k, R, modulus, &mp, map);
+        } else {
+           err = normal_ecc_mulmod(k, G, R, modulus, map);
+        }
+     }
+
+#ifndef HAVE_THREAD_LS
+    UnLockMutex(&ecc_fp_lock);
+#endif /* HAVE_THREAD_LS */
+    mp_clear(&mu);
+
+    return err;
+}
+
+/* helper function for freeing the cache ...
+   must be called with the cache mutex locked */
+static void wc_ecc_fp_free_cache(void)
+{
+   unsigned x, y;
+   for (x = 0; x < FP_ENTRIES; x++) {
+      if (fp_cache[x].g != NULL) {
+         for (y = 0; y < (1U<protocol == 0)
+        return NULL;
+
+    if (ctx->protocol == REQ_RESP_CLIENT) {
+        if (ctx->cliSt == ecCLI_INIT) {
+            ctx->cliSt =  ecCLI_SALT_GET;
+            return ctx->clientSalt;
+        }
+        else {
+            ctx->cliSt = ecCLI_BAD_STATE;
+            return NULL;
+        }
+    }
+    else if (ctx->protocol == REQ_RESP_SERVER) {
+        if (ctx->srvSt == ecSRV_INIT) {
+            ctx->srvSt =  ecSRV_SALT_GET;
+            return ctx->serverSalt;
+        }
+        else {
+            ctx->srvSt = ecSRV_BAD_STATE;
+            return NULL;
+        }
+    }
+
+    return NULL;
+}
+
+
+/* optional set info, can be called before or after set_peer_salt */
+int wc_ecc_ctx_set_info(ecEncCtx* ctx, const byte* info, int sz)
+{
+    if (ctx == NULL || info == 0 || sz < 0)
+        return BAD_FUNC_ARG;
+
+    ctx->kdfInfo   = info;
+    ctx->kdfInfoSz = sz;
+
+    return 0;
+}
+
+
+static const char* exchange_info = "Secure Message Exchange";
+
+int wc_ecc_ctx_set_peer_salt(ecEncCtx* ctx, const byte* salt)
+{
+    byte tmp[EXCHANGE_SALT_SZ/2];
+    int  halfSz = EXCHANGE_SALT_SZ/2;
+
+    if (ctx == NULL || ctx->protocol == 0 || salt == NULL)
+        return BAD_FUNC_ARG;
+
+    if (ctx->protocol == REQ_RESP_CLIENT) {
+        XMEMCPY(ctx->serverSalt, salt, EXCHANGE_SALT_SZ);
+        if (ctx->cliSt == ecCLI_SALT_GET)
+            ctx->cliSt =  ecCLI_SALT_SET;
+        else {
+            ctx->cliSt =  ecCLI_BAD_STATE;
+            return BAD_ENC_STATE_E;
+        }
+    }
+    else {
+        XMEMCPY(ctx->clientSalt, salt, EXCHANGE_SALT_SZ);
+        if (ctx->srvSt == ecSRV_SALT_GET)
+            ctx->srvSt =  ecSRV_SALT_SET;
+        else {
+            ctx->srvSt =  ecSRV_BAD_STATE;
+            return BAD_ENC_STATE_E;
+        }
+    }
+
+    /* mix half and half */
+    /* tmp stores 2nd half of client before overwrite */
+    XMEMCPY(tmp, ctx->clientSalt + halfSz, halfSz);
+    XMEMCPY(ctx->clientSalt + halfSz, ctx->serverSalt, halfSz);
+    XMEMCPY(ctx->serverSalt, tmp, halfSz);
+
+    ctx->kdfSalt   = ctx->clientSalt;
+    ctx->kdfSaltSz = EXCHANGE_SALT_SZ;
+
+    ctx->macSalt   = ctx->serverSalt;
+    ctx->macSaltSz = EXCHANGE_SALT_SZ;
+
+    if (ctx->kdfInfo == NULL) {
+        /* default info */
+        ctx->kdfInfo   = (const byte*)exchange_info;
+        ctx->kdfInfoSz = EXCHANGE_INFO_SZ;
+    }
+
+    return 0;
+}
+
+
+static int ecc_ctx_set_salt(ecEncCtx* ctx, int flags, RNG* rng)
+{
+    byte* saltBuffer = NULL;
+
+    if (ctx == NULL || rng == NULL || flags == 0) 
+        return BAD_FUNC_ARG;
+
+    saltBuffer = (flags == REQ_RESP_CLIENT) ? ctx->clientSalt : ctx->serverSalt;
+
+    return wc_RNG_GenerateBlock(rng, saltBuffer, EXCHANGE_SALT_SZ);
+}
+
+
+static void ecc_ctx_init(ecEncCtx* ctx, int flags)
+{
+    if (ctx) {
+        XMEMSET(ctx, 0, sizeof(ecEncCtx));
+
+        ctx->encAlgo  = ecAES_128_CBC;
+        ctx->kdfAlgo  = ecHKDF_SHA256;
+        ctx->macAlgo  = ecHMAC_SHA256;
+        ctx->protocol = (byte)flags;
+
+        if (flags == REQ_RESP_CLIENT)
+            ctx->cliSt = ecCLI_INIT;
+        if (flags == REQ_RESP_SERVER)
+            ctx->srvSt = ecSRV_INIT;
+    }
+}
+
+
+/* allow ecc context reset so user doesn't have to init/free for resue */
+int wc_ecc_ctx_reset(ecEncCtx* ctx, RNG* rng)
+{
+    if (ctx == NULL || rng == NULL)
+        return BAD_FUNC_ARG;
+
+    ecc_ctx_init(ctx, ctx->protocol);
+    return ecc_ctx_set_salt(ctx, ctx->protocol, rng);
+}
+
+
+/* alloc/init and set defaults, return new Context  */
+ecEncCtx* wc_ecc_ctx_new(int flags, RNG* rng)
+{
+    int       ret = 0;
+    ecEncCtx* ctx = (ecEncCtx*)XMALLOC(sizeof(ecEncCtx), 0, DYNAMIC_TYPE_ECC);
+
+    if (ctx)
+        ctx->protocol = (byte)flags;
+
+    ret = wc_ecc_ctx_reset(ctx, rng);
+    if (ret != 0) {
+        wc_ecc_ctx_free(ctx);
+        ctx = NULL;
+    }
+
+    return ctx;
+}
+
+
+/* free any resources, clear any keys */
+void wc_ecc_ctx_free(ecEncCtx* ctx)
+{
+    if (ctx) {
+        ForceZero(ctx, sizeof(ecEncCtx));
+        XFREE(ctx, 0, DYNAMIC_TYPE_ECC);
+    }
+}
+
+
+static int ecc_get_key_sizes(ecEncCtx* ctx, int* encKeySz, int* ivSz,
+                             int* keysLen, word32* digestSz, word32* blockSz)
+{
+    if (ctx) {
+        switch (ctx->encAlgo) {
+            case ecAES_128_CBC:
+                *encKeySz = KEY_SIZE_128;
+                *ivSz     = IV_SIZE_64;
+                *blockSz  = AES_BLOCK_SIZE;
+                break;
+            default:
+                return BAD_FUNC_ARG;
+        }
+
+        switch (ctx->macAlgo) {
+            case ecHMAC_SHA256:
+                *digestSz = SHA256_DIGEST_SIZE;
+                break;
+            default:
+                return BAD_FUNC_ARG;
+        }
+    } else
+        return BAD_FUNC_ARG;
+
+    *keysLen  = *encKeySz + *ivSz + *digestSz;
+
+    return 0;
+}
+
+
+/* ecc encrypt with shared secret run through kdf
+   ctx holds non default algos and inputs
+   msgSz should be the right size for encAlgo, i.e., already padded 
+   return 0 on success */
+int wc_ecc_encrypt(ecc_key* privKey, ecc_key* pubKey, const byte* msg,
+                word32 msgSz, byte* out, word32* outSz, ecEncCtx* ctx)
+{
+    int          ret;
+    word32       blockSz;
+    word32       digestSz;
+    ecEncCtx     localCtx;
+#ifdef WOLFSSL_SMALL_STACK
+    byte*        sharedSecret;
+    byte*        keys;
+#else
+    byte         sharedSecret[ECC_MAXSIZE];  /* 521 max size */
+    byte         keys[ECC_BUFSIZE];         /* max size */
+#endif
+    word32       sharedSz = ECC_MAXSIZE;
+    int          keysLen;
+    int          encKeySz;
+    int          ivSz;
+    int          offset = 0;         /* keys offset if doing msg exchange */
+    byte*        encKey;
+    byte*        encIv;
+    byte*        macKey;
+
+    if (privKey == NULL || pubKey == NULL || msg == NULL || out == NULL ||
+                           outSz  == NULL)
+        return BAD_FUNC_ARG;
+
+    if (ctx == NULL) {  /* use defaults */
+        ecc_ctx_init(&localCtx, 0);
+        ctx = &localCtx;  
+    }
+        
+    ret = ecc_get_key_sizes(ctx, &encKeySz, &ivSz, &keysLen, &digestSz,
+                            &blockSz);
+    if (ret != 0)
+        return ret;
+
+    if (ctx->protocol == REQ_RESP_SERVER) {
+        offset = keysLen;
+        keysLen *= 2;
+
+        if (ctx->srvSt != ecSRV_RECV_REQ)
+            return BAD_ENC_STATE_E;
+
+        ctx->srvSt = ecSRV_BAD_STATE; /* we're done no more ops allowed */
+    }
+    else if (ctx->protocol == REQ_RESP_CLIENT) {
+        if (ctx->cliSt != ecCLI_SALT_SET)
+            return BAD_ENC_STATE_E;
+
+        ctx->cliSt = ecCLI_SENT_REQ; /* only do this once */
+    }
+        
+    if (keysLen > ECC_BUFSIZE) /* keys size */
+        return BUFFER_E;
+        
+    if ( (msgSz%blockSz) != 0)
+        return BAD_PADDING_E;
+
+    if (*outSz < (msgSz + digestSz))
+        return BUFFER_E;
+
+#ifdef WOLFSSL_SMALL_STACK
+    sharedSecret = (byte*)XMALLOC(ECC_MAXSIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (sharedSecret == NULL)
+        return MEMORY_E;
+
+    keys = (byte*)XMALLOC(ECC_BUFSIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (keys == NULL) {
+        XFREE(sharedSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        return MEMORY_E;
+    }
+#endif
+
+    ret = wc_ecc_shared_secret(privKey, pubKey, sharedSecret, &sharedSz);
+
+    if (ret == 0) {
+       switch (ctx->kdfAlgo) {
+           case ecHKDF_SHA256 :
+               ret = wc_HKDF(SHA256, sharedSecret, sharedSz, ctx->kdfSalt,
+                          ctx->kdfSaltSz, ctx->kdfInfo, ctx->kdfInfoSz,
+                          keys, keysLen);
+               break;
+
+           default:
+               ret = BAD_FUNC_ARG;
+               break;
+       }
+    }
+
+    if (ret == 0) {
+       encKey = keys + offset;
+       encIv  = encKey + encKeySz;
+       macKey = encKey + encKeySz + ivSz;
+
+       switch (ctx->encAlgo) {
+           case ecAES_128_CBC:
+               {
+                   Aes aes;
+                   ret = wc_AesSetKey(&aes, encKey, KEY_SIZE_128, encIv,
+                                                                AES_ENCRYPTION);
+                   if (ret != 0)
+                       break;
+                   ret = wc_AesCbcEncrypt(&aes, out, msg, msgSz);
+               }
+               break;
+
+           default:
+               ret = BAD_FUNC_ARG;
+               break;
+       }
+    }
+
+    if (ret == 0) {
+       switch (ctx->macAlgo) {
+           case ecHMAC_SHA256:
+               {
+                   Hmac hmac;
+                   ret = wc_HmacSetKey(&hmac, SHA256, macKey, SHA256_DIGEST_SIZE);
+                   if (ret != 0)
+                       break;
+                   ret = wc_HmacUpdate(&hmac, out, msgSz);
+                   if (ret != 0)
+                       break;
+                   ret = wc_HmacUpdate(&hmac, ctx->macSalt, ctx->macSaltSz);
+                   if (ret != 0)
+                       break;
+                   ret = wc_HmacFinal(&hmac, out+msgSz);
+               }
+               break;
+
+           default:
+               ret = BAD_FUNC_ARG;
+               break;
+       }
+    }
+
+    if (ret == 0)
+       *outSz = msgSz + digestSz;
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(sharedSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(keys, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+
+/* ecc decrypt with shared secret run through kdf
+   ctx holds non default algos and inputs
+   return 0 on success */
+int wc_ecc_decrypt(ecc_key* privKey, ecc_key* pubKey, const byte* msg,
+                word32 msgSz, byte* out, word32* outSz, ecEncCtx* ctx)
+{
+    int          ret;
+    word32       blockSz;
+    word32       digestSz;
+    ecEncCtx     localCtx;
+#ifdef WOLFSSL_SMALL_STACK
+    byte*        sharedSecret;
+    byte*        keys;
+#else
+    byte         sharedSecret[ECC_MAXSIZE];  /* 521 max size */
+    byte         keys[ECC_BUFSIZE];         /* max size */
+#endif
+    word32       sharedSz = ECC_MAXSIZE;
+    int          keysLen;
+    int          encKeySz;
+    int          ivSz;
+    int          offset = 0;       /* in case using msg exchange */
+    byte*        encKey;
+    byte*        encIv;
+    byte*        macKey;
+
+    if (privKey == NULL || pubKey == NULL || msg == NULL || out == NULL ||
+                           outSz  == NULL)
+        return BAD_FUNC_ARG;
+
+    if (ctx == NULL) {  /* use defaults */
+        ecc_ctx_init(&localCtx, 0);
+        ctx = &localCtx;  
+    }
+        
+    ret = ecc_get_key_sizes(ctx, &encKeySz, &ivSz, &keysLen, &digestSz,
+                            &blockSz);
+    if (ret != 0)
+        return ret;
+        
+    if (ctx->protocol == REQ_RESP_CLIENT) {
+        offset = keysLen;
+        keysLen *= 2;
+
+        if (ctx->cliSt != ecCLI_SENT_REQ)
+            return BAD_ENC_STATE_E;
+
+        ctx->cliSt = ecSRV_BAD_STATE; /* we're done no more ops allowed */
+    }
+    else if (ctx->protocol == REQ_RESP_SERVER) {
+        if (ctx->srvSt != ecSRV_SALT_SET)
+            return BAD_ENC_STATE_E;
+
+        ctx->srvSt = ecSRV_RECV_REQ; /* only do this once */
+    }
+        
+    if (keysLen > ECC_BUFSIZE) /* keys size */
+        return BUFFER_E;
+        
+    if ( ((msgSz-digestSz) % blockSz) != 0)
+        return BAD_PADDING_E;
+
+    if (*outSz < (msgSz - digestSz))
+        return BUFFER_E;
+
+#ifdef WOLFSSL_SMALL_STACK
+    sharedSecret = (byte*)XMALLOC(ECC_MAXSIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (sharedSecret == NULL)
+        return MEMORY_E;
+
+    keys = (byte*)XMALLOC(ECC_BUFSIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (keys == NULL) {
+        XFREE(sharedSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        return MEMORY_E;
+    }
+#endif
+
+    ret = wc_ecc_shared_secret(privKey, pubKey, sharedSecret, &sharedSz);
+
+    if (ret == 0) {
+       switch (ctx->kdfAlgo) {
+           case ecHKDF_SHA256 :
+               ret = wc_HKDF(SHA256, sharedSecret, sharedSz, ctx->kdfSalt,
+                          ctx->kdfSaltSz, ctx->kdfInfo, ctx->kdfInfoSz,
+                          keys, keysLen);
+               break;
+
+           default:
+               ret = BAD_FUNC_ARG;
+               break;
+       }
+    }
+
+    if (ret == 0) {
+       encKey = keys + offset;
+       encIv  = encKey + encKeySz;
+       macKey = encKey + encKeySz + ivSz;
+
+       switch (ctx->macAlgo) {
+           case ecHMAC_SHA256:
+               {
+                   byte verify[SHA256_DIGEST_SIZE];
+                   Hmac hmac;
+                   ret = wc_HmacSetKey(&hmac, SHA256, macKey, SHA256_DIGEST_SIZE);
+                   if (ret != 0)
+                       break;
+                   ret = wc_HmacUpdate(&hmac, msg, msgSz-digestSz);
+                   if (ret != 0)
+                       break;
+                   ret = wc_HmacUpdate(&hmac, ctx->macSalt, ctx->macSaltSz);
+                   if (ret != 0)
+                       break;
+                   ret = wc_HmacFinal(&hmac, verify);
+                   if (ret != 0)
+                       break;
+                   if (memcmp(verify, msg + msgSz - digestSz, digestSz) != 0)
+                       ret = -1;
+               }
+               break;
+
+           default:
+               ret = BAD_FUNC_ARG;
+               break;
+       }
+    }
+
+    if (ret == 0) {
+       switch (ctx->encAlgo) {
+           case ecAES_128_CBC:
+               {
+                   Aes aes;
+                   ret = wc_AesSetKey(&aes, encKey, KEY_SIZE_128, encIv,
+                                                                AES_DECRYPTION);
+                   if (ret != 0)
+                       break;
+                   ret = wc_AesCbcDecrypt(&aes, out, msg, msgSz-digestSz);
+               }
+               break;
+
+           default:
+               ret = BAD_FUNC_ARG;
+               break;
+       }
+    }
+
+    if (ret == 0)
+       *outSz = msgSz - digestSz;
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(sharedSecret, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(keys, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+
+#endif /* HAVE_ECC_ENCRYPT */
+
+
+#ifdef HAVE_COMP_KEY
+
+/* computes the jacobi c = (a | n) (or Legendre if n is prime)
+ * HAC pp. 73 Algorithm 2.149
+ */
+int mp_jacobi(mp_int* a, mp_int* p, int* c)
+{
+  mp_int   a1, p1;
+  int      k, s, r, res;
+  mp_digit residue;
+
+  /* if p <= 0 return MP_VAL */
+  if (mp_cmp_d(p, 0) != MP_GT) {
+     return MP_VAL;
+  }
+
+  /* step 1.  if a == 0, return 0 */
+  if (mp_iszero (a) == 1) {
+    *c = 0;
+    return MP_OKAY;
+  }
+
+  /* step 2.  if a == 1, return 1 */
+  if (mp_cmp_d (a, 1) == MP_EQ) {
+    *c = 1;
+    return MP_OKAY;
+  }
+
+  /* default */
+  s = 0;
+
+  /* step 3.  write a = a1 * 2**k  */
+  if ((res = mp_init_copy (&a1, a)) != MP_OKAY) {
+    return res;
+  }
+
+  if ((res = mp_init (&p1)) != MP_OKAY) {
+    mp_clear(&a1);
+    return res;
+  }
+
+  /* divide out larger power of two */
+  k = mp_cnt_lsb(&a1);
+  res = mp_div_2d(&a1, k, &a1, NULL);
+
+  if (res == MP_OKAY) {
+    /* step 4.  if e is even set s=1 */
+    if ((k & 1) == 0) {
+      s = 1;
+    } else {
+      /* else set s=1 if p = 1/7 (mod 8) or s=-1 if p = 3/5 (mod 8) */
+      residue = p->dp[0] & 7;
+
+      if (residue == 1 || residue == 7) {
+        s = 1;
+      } else if (residue == 3 || residue == 5) {
+        s = -1;
+      }
+    }
+
+    /* step 5.  if p == 3 (mod 4) *and* a1 == 3 (mod 4) then s = -s */
+    if ( ((p->dp[0] & 3) == 3) && ((a1.dp[0] & 3) == 3)) {
+      s = -s;
+    }
+  }
+
+  if (res == MP_OKAY) {
+    /* if a1 == 1 we're done */
+    if (mp_cmp_d (&a1, 1) == MP_EQ) {
+      *c = s;
+    } else {
+      /* n1 = n mod a1 */
+      res = mp_mod (p, &a1, &p1);
+      if (res == MP_OKAY)
+        res = mp_jacobi (&p1, &a1, &r);
+
+      if (res == MP_OKAY)
+      *c = s * r;
+    }
+  }
+
+  /* done */
+  mp_clear (&p1);
+  mp_clear (&a1);
+
+  return res;
+}
+
+
+int mp_sqrtmod_prime(mp_int* n, mp_int* prime, mp_int* ret)
+{
+  int res, legendre, done = 0;
+  mp_int t1, C, Q, S, Z, M, T, R, two;
+  mp_digit i;
+
+  /* first handle the simple cases */
+  if (mp_cmp_d(n, 0) == MP_EQ) {
+    mp_zero(ret);
+    return MP_OKAY;
+  }
+  if (mp_cmp_d(prime, 2) == MP_EQ)       return MP_VAL; /* prime must be odd */
+  /* TAO removed
+  if ((res = mp_jacobi(n, prime, &legendre)) != MP_OKAY)      return res;
+  if (legendre == -1)  return MP_VAL; */ /* quadratic non-residue mod prime */
+
+  if ((res = mp_init_multi(&t1, &C, &Q, &S, &Z, &M)) != MP_OKAY)
+    return res;
+
+  if ((res = mp_init_multi(&T, &R, &two, NULL, NULL, NULL))
+                          != MP_OKAY) {
+    mp_clear(&t1); mp_clear(&C); mp_clear(&Q); mp_clear(&S); mp_clear(&Z);
+    mp_clear(&M);
+    return res;
+  }
+
+  /* SPECIAL CASE: if prime mod 4 == 3
+   * compute directly: res = n^(prime+1)/4 mod prime
+   * Handbook of Applied Cryptography algorithm 3.36
+   */
+  res = mp_mod_d(prime, 4, &i);
+  if (res == MP_OKAY && i == 3) {
+    res = mp_add_d(prime, 1, &t1);
+
+    if (res == MP_OKAY)
+      res = mp_div_2(&t1, &t1);
+    if (res == MP_OKAY)
+      res = mp_div_2(&t1, &t1);
+    if (res == MP_OKAY)
+      res = mp_exptmod(n, &t1, prime, ret);
+
+    done = 1;
+  }
+
+  /* NOW: TonelliShanks algorithm */
+
+ if (res == MP_OKAY && done == 0) {
+
+   /* factor out powers of 2 from prime-1, defining Q and S
+    *                                      as: prime-1 = Q*2^S */
+    res = mp_copy(prime, &Q);
+    if (res == MP_OKAY)
+      res = mp_sub_d(&Q, 1, &Q);
+    /* Q = prime - 1 */
+    if (res == MP_OKAY)
+      mp_zero(&S);
+    /* S = 0 */
+    while (res == MP_OKAY && mp_iseven(&Q)) {
+      res = mp_div_2(&Q, &Q);
+      /* Q = Q / 2 */
+      if (res == MP_OKAY)
+        res = mp_add_d(&S, 1, &S);
+        /* S = S + 1 */
+    }
+
+    /* find a Z such that the Legendre symbol (Z|prime) == -1 */
+    if (res == MP_OKAY)
+      res = mp_set_int(&Z, 2);
+    /* Z = 2 */
+    while (res == MP_OKAY) {
+      res = mp_jacobi(&Z, prime, &legendre);
+      if (res == MP_OKAY && legendre == -1)
+        break;
+      if (res == MP_OKAY)
+        res = mp_add_d(&Z, 1, &Z);
+        /* Z = Z + 1 */
+    }
+
+    if (res == MP_OKAY)
+      res = mp_exptmod(&Z, &Q, prime, &C);
+      /* C = Z ^ Q mod prime */
+    if (res == MP_OKAY)
+      res = mp_add_d(&Q, 1, &t1);
+    if (res == MP_OKAY)
+      res = mp_div_2(&t1, &t1);
+      /* t1 = (Q + 1) / 2 */
+    if (res == MP_OKAY)
+      res = mp_exptmod(n, &t1, prime, &R);
+    /* R = n ^ ((Q + 1) / 2) mod prime */
+    if (res == MP_OKAY)
+      res = mp_exptmod(n, &Q, prime, &T);
+    /* T = n ^ Q mod prime */
+    if (res == MP_OKAY)
+      res = mp_copy(&S, &M);
+    /* M = S */
+    if (res == MP_OKAY)
+      res = mp_set_int(&two, 2);
+
+    while (res == MP_OKAY && done == 0) {
+      res = mp_copy(&T, &t1);
+      i = 0;
+      while (res == MP_OKAY) {
+        if (mp_cmp_d(&t1, 1) == MP_EQ)
+            break;
+        res = mp_exptmod(&t1, &two, prime, &t1);
+        if (res == MP_OKAY)
+          i++;
+      }
+      if (res == MP_OKAY && i == 0) {
+        mp_copy(&R, ret);
+        res = MP_OKAY;
+        done = 1;
+      }
+
+      if (done == 0) {
+        if (res == MP_OKAY)
+          res = mp_sub_d(&M, i, &t1);
+        if (res == MP_OKAY)
+          res = mp_sub_d(&t1, 1, &t1);
+        if (res == MP_OKAY)
+          res = mp_exptmod(&two, &t1, prime, &t1);
+        /* t1 = 2 ^ (M - i - 1) */
+        if (res == MP_OKAY)
+          res = mp_exptmod(&C, &t1, prime, &t1);
+        /* t1 = C ^ (2 ^ (M - i - 1)) mod prime */
+        if (res == MP_OKAY)
+          res = mp_sqrmod(&t1, prime, &C);
+        /* C = (t1 * t1) mod prime */
+        if (res == MP_OKAY)
+          res = mp_mulmod(&R, &t1, prime, &R);
+        /* R = (R * t1) mod prime */
+        if (res == MP_OKAY)
+          res = mp_mulmod(&T, &C, prime, &T);
+        /* T = (T * C) mod prime */
+        if (res == MP_OKAY)
+          mp_set(&M, i);
+        /* M = i */
+      }
+    }
+  }
+
+  /* done */
+  mp_clear(&t1);
+  mp_clear(&C);
+  mp_clear(&Q);
+  mp_clear(&S);
+  mp_clear(&Z);
+  mp_clear(&M);
+  mp_clear(&T);
+  mp_clear(&R);
+  mp_clear(&two);
+
+  return res;
+}
+
+
+/* export public ECC key in ANSI X9.63 format compressed */
+int wc_ecc_export_x963_compressed(ecc_key* key, byte* out, word32* outLen)
+{
+   word32 numlen;
+   int    ret = MP_OKAY;
+
+   if (key == NULL || out == NULL || outLen == NULL)
+       return ECC_BAD_ARG_E;
+
+   if (ecc_is_valid_idx(key->idx) == 0) {
+      return ECC_BAD_ARG_E;
+   }
+   numlen = key->dp->size;
+
+   if (*outLen < (1 + numlen)) {
+      *outLen = 1 + numlen;
+      return BUFFER_E;
+   }
+
+   /* store first byte */
+   out[0] = mp_isodd(key->pubkey.y) ? 0x03 : 0x02;
+
+   /* pad and store x */
+   XMEMSET(out+1, 0, numlen);
+   ret = mp_to_unsigned_bin(key->pubkey.x,
+                       out+1 + (numlen - mp_unsigned_bin_size(key->pubkey.x)));
+   *outLen = 1 + numlen;
+   return ret;
+}
+
+
+/* d = a - b (mod c) */
+int mp_submod(mp_int* a, mp_int* b, mp_int* c, mp_int* d)
+{
+  int     res;
+  mp_int  t;
+
+  if ((res = mp_init (&t)) != MP_OKAY) {
+    return res;
+  }
+
+  if ((res = mp_sub (a, b, &t)) != MP_OKAY) {
+    mp_clear (&t);
+    return res;
+  }
+  res = mp_mod (&t, c, d);
+  mp_clear (&t);
+
+  return res;
+}
+
+
+#endif /* HAVE_COMP_KEY */
+
+#endif /* HAVE_ECC */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/ecc_fp.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/ecc_fp.c
new file mode 100644
index 0000000..c8acf93
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/ecc_fp.c
@@ -0,0 +1 @@
+/* dummy ecc_fp.c for dist */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/ed25519.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/ed25519.c
new file mode 100644
index 0000000..ba0dcbe
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/ed25519.c
@@ -0,0 +1,370 @@
+/* ed25519.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+ /* Based On Daniel J Bernstein's ed25519 Public Domain ref10 work. */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+/* in case user set HAVE_ED25519 there */
+#include 
+
+#ifdef HAVE_ED25519
+
+#include 
+#include 
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+
+/*
+    generate an ed25519 key pair.
+    returns 0 on success
+ */
+int wc_ed25519_make_key(RNG* rng, int keySz, ed25519_key* key)
+{
+    byte  az[64];
+    int   ret;
+    ge_p3 A;
+
+    if (rng == NULL || key == NULL)
+        return BAD_FUNC_ARG;
+
+    /* ed25519 has 32 byte key sizes */
+    if (keySz != ED25519_KEY_SIZE)
+        return BAD_FUNC_ARG;
+
+    ret = 0;
+    ret |= wc_RNG_GenerateBlock(rng, key->k, 32);
+    ret |= wc_Sha512Hash(key->k, 32, az);
+    az[0] &= 248;
+    az[31] &= 63;
+    az[31] |= 64;
+
+    ge_scalarmult_base(&A, az);
+    ge_p3_tobytes(key->p, &A);
+    XMEMMOVE(key->k + 32, key->p, 32);
+
+    return ret;
+}
+
+
+/*
+    in     contains the message to sign
+    inlen  is the length of the message to sign
+    out    is the buffer to write the signature
+    outlen [in/out] input size of out buf
+                    output gets set as the final length of out
+    key    is the ed25519 key to use when signing
+    return 0 on success
+ */
+int wc_ed25519_sign_msg(const byte* in, word32 inlen, byte* out,
+                        word32 *outlen, ed25519_key* key)
+{
+    ge_p3  R;
+    byte   nonce[SHA512_DIGEST_SIZE];
+    byte   hram[SHA512_DIGEST_SIZE];
+    byte   az[64];
+    word32 sigSz;
+    Sha512 sha;
+    int    ret = 0;
+
+    /* sanity check on arguments */
+    if (in == NULL || out == NULL || outlen == NULL || key == NULL)
+        return BAD_FUNC_ARG;
+
+    /* check and set up out length */
+    ret   = 0;
+    sigSz = wc_ed25519_sig_size(key);
+    if (*outlen < sigSz)
+        return BAD_FUNC_ARG;
+    *outlen = sigSz;
+
+    /* step 1: create nonce to use where nonce is r in
+       r = H(h_b, ... ,h_2b-1,M) */
+    ret |= wc_Sha512Hash(key->k,32,az);
+    az[0]  &= 248;
+    az[31] &= 63;
+    az[31] |= 64;
+    ret |= wc_InitSha512(&sha);
+    ret |= wc_Sha512Update(&sha, az + 32, 32);
+    ret |= wc_Sha512Update(&sha, in, inlen);
+    ret |= wc_Sha512Final(&sha, nonce);
+    sc_reduce(nonce);
+
+    /* step 2: computing R = rB where rB is the scalar multiplication of
+       r and B */
+    ge_scalarmult_base(&R,nonce);
+    ge_p3_tobytes(out,&R);
+
+    /* step 3: hash R + public key + message getting H(R,A,M) then
+       creating S = (r + H(R,A,M)a) mod l */
+    ret |= wc_InitSha512(&sha);
+    ret |= wc_Sha512Update(&sha, out, 32);
+    ret |= wc_Sha512Update(&sha, key->p, 32);
+    ret |= wc_Sha512Update(&sha, in, inlen);
+    ret |= wc_Sha512Final(&sha, hram);
+    sc_reduce(hram);
+    sc_muladd(out + 32, hram, az, nonce);
+
+    return ret;
+}
+
+
+/*
+   sig     is array of bytes containing the signature
+   siglen  is the length of sig byte array
+   msg     the array of bytes containing the message
+   msglen  length of msg array
+   stat    will be 1 on successful verify and 0 on unsuccessful
+*/
+int wc_ed25519_verify_msg(byte* sig, word32 siglen, const byte* msg,
+                          word32 msglen, int* stat, ed25519_key* key)
+{
+    byte   rcheck[32];
+    byte   h[SHA512_DIGEST_SIZE];
+    ge_p3  A;
+    ge_p2  R;
+    word32 sigSz;
+    int    ret;
+    Sha512 sha;
+
+    /* sanity check on arguments */
+    if (sig == NULL || msg == NULL || stat == NULL || key == NULL)
+        return BAD_FUNC_ARG;
+
+    ret   = 0;
+    *stat = 0;
+    sigSz = wc_ed25519_size(key);
+
+    /* check on basics needed to verify signature */
+    if (siglen < sigSz)
+        return BAD_FUNC_ARG;
+    if (sig[63] & 224)
+        return BAD_FUNC_ARG;
+
+    /* uncompress A (public key), test if valid, and negate it */
+    if (ge_frombytes_negate_vartime(&A, key->p) != 0)
+        return BAD_FUNC_ARG;
+
+    /* find H(R,A,M) and store it as h */
+    ret |= wc_InitSha512(&sha);
+    ret |= wc_Sha512Update(&sha, sig,    32);
+    ret |= wc_Sha512Update(&sha, key->p, 32);
+    ret |= wc_Sha512Update(&sha, msg,    msglen);
+    ret |= wc_Sha512Final(&sha,  h);
+    sc_reduce(h);
+
+    /*
+       Uses a fast single-signature verification SB = R + H(R,A,M)A becomes
+       SB - H(R,A,M)A saving decompression of R
+    */
+    ret |= ge_double_scalarmult_vartime(&R, h, &A, sig + 32);
+    ge_tobytes(rcheck, &R);
+
+    /* comparison of R created to R in sig */
+    ret  |= ConstantCompare(rcheck, sig, 32);
+
+    *stat = (ret == 0)? 1: 0;
+
+    return ret;
+}
+
+
+/* initialize information and memory for key */
+int wc_ed25519_init(ed25519_key* key)
+{
+    if (key == NULL)
+        return BAD_FUNC_ARG;
+
+    XMEMSET(key, 0, sizeof(ed25519_key));
+
+    return 0;
+}
+
+
+/* clear memory of key */
+void wc_ed25519_free(ed25519_key* key)
+{
+    if (key == NULL)
+        return;
+
+    ForceZero(key, sizeof(ed25519_key));
+}
+
+
+/*
+    outLen should contain the size of out buffer when input. outLen is than set
+    to the final output length.
+    returns 0 on success
+ */
+int wc_ed25519_export_public(ed25519_key* key, byte* out, word32* outLen)
+{
+    word32 keySz;
+
+    /* sanity check on arguments */
+    if (key == NULL || out == NULL || outLen == NULL)
+        return BAD_FUNC_ARG;
+
+    keySz = wc_ed25519_size(key);
+    if (*outLen < keySz) {
+        *outLen = keySz;
+        return BUFFER_E;
+    }
+    *outLen = keySz;
+    XMEMCPY(out, key->p, keySz);
+
+    return 0;
+}
+
+
+/*
+    Imports a compressed/uncompressed public key.
+    in    the byte array containing the public key
+    inLen the length of the byte array being passed in
+    key   ed25519 key struct to put the public key in
+ */
+int wc_ed25519_import_public(const byte* in, word32 inLen, ed25519_key* key)
+{
+    word32 keySz;
+    int    ret;
+
+    /* sanity check on arguments */
+    if (in == NULL || key == NULL)
+        return BAD_FUNC_ARG;
+
+    keySz = wc_ed25519_size(key);
+
+    if (inLen < keySz)
+        return BAD_FUNC_ARG;
+
+    /* compressed prefix according to draft
+       http://www.ietf.org/id/draft-koch-eddsa-for-openpgp-02.txt */
+    if (in[0] == 0x40) {
+        /* key is stored in compressed format so just copy in */
+        XMEMCPY(key->p, (in + 1), keySz);
+        return 0;
+    }
+
+    /* importing uncompressed public key */
+    if (in[0] == 0x04) {
+        /* pass in (x,y) and store compressed key */
+        ret = ge_compress_key(key->p, (in+1), (in+1+keySz), keySz);
+        return ret;
+    }
+
+    /* if not specified compressed or uncompressed check key size
+       if key size is equal to compressed key size copy in key */
+    if (inLen == keySz) {
+        XMEMCPY(key->p, in, keySz);
+        return 0;
+    }
+
+    /* bad public key format */
+    return BAD_FUNC_ARG;
+}
+
+
+/*
+    For importing a private key and its associated public key.
+ */
+int wc_ed25519_import_private_key(const byte* priv, word32 privSz,
+                                const byte* pub, word32 pubSz, ed25519_key* key)
+{
+    word32 keySz;
+    int    ret;
+
+    /* sanity check on arguments */
+    if (priv == NULL || pub == NULL || key == NULL)
+        return BAD_FUNC_ARG;
+
+    keySz = wc_ed25519_size(key);
+
+    /* key size check */
+    if (privSz < keySz || pubSz < keySz)
+        return BAD_FUNC_ARG;
+
+    XMEMCPY(key->k, priv, keySz);
+    ret = wc_ed25519_import_public(pub, pubSz, key);
+    XMEMCPY((key->k + keySz), key->p, keySz);
+
+    return ret;
+}
+
+
+/*
+    outLen should contain the size of out buffer when input. outLen is than set
+    to the final output length.
+    returns 0 on success
+ */
+int wc_ed25519_export_private_only(ed25519_key* key, byte* out, word32* outLen)
+{
+    word32 keySz;
+
+    /* sanity checks on arguments */
+    if (key == NULL || out == NULL || outLen == NULL)
+        return BAD_FUNC_ARG;
+
+    keySz = wc_ed25519_size(key);
+    if (*outLen < keySz) {
+        *outLen = keySz;
+        return BUFFER_E;
+    }
+    *outLen = keySz;
+    XMEMCPY(out, key->k, keySz);
+
+    return 0;
+}
+
+
+/* is the compressed key size in bytes */
+int wc_ed25519_size(ed25519_key* key)
+{
+    word32 keySz;
+
+    if (key == NULL)
+        return BAD_FUNC_ARG;
+
+    keySz = ED25519_KEY_SIZE;
+
+    return keySz;
+}
+
+
+/* returns the size of signature in bytes */
+int wc_ed25519_sig_size(ed25519_key* key)
+{
+    word32 sigSz;
+
+    if (key == NULL)
+        return BAD_FUNC_ARG;
+
+    sigSz = ED25519_SIG_SIZE;
+
+    return sigSz;
+}
+
+#endif /* HAVE_ED25519 */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/error.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/error.c
new file mode 100644
index 0000000..7d1d5eb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/error.c
@@ -0,0 +1,343 @@
+/* error.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#include 
+
+#ifdef _MSC_VER
+    /* 4996 warning to use MS extensions e.g., strcpy_s instead of XSTRNCPY */
+    #pragma warning(disable: 4996)
+#endif
+
+const char* wc_GetErrorString(int error)
+{
+#ifdef NO_ERROR_STRINGS
+
+    (void)error;
+    return "no support for error strings built in";
+
+#else
+
+    switch (error) {
+
+    case OPEN_RAN_E :
+        return "opening random device error";
+
+    case READ_RAN_E :
+        return "reading random device error";
+
+    case WINCRYPT_E :
+        return "windows crypt init error";
+
+    case CRYPTGEN_E :
+        return "windows crypt generation error";
+
+    case RAN_BLOCK_E :
+        return "random device read would block error";
+
+    case BAD_MUTEX_E :
+        return "Bad mutex, operation failed";
+
+    case MP_INIT_E :
+        return "mp_init error state";
+
+    case MP_READ_E :
+        return "mp_read error state";
+
+    case MP_EXPTMOD_E :
+        return "mp_exptmod error state";
+
+    case MP_TO_E :
+        return "mp_to_xxx error state, can't convert";
+
+    case MP_SUB_E :
+        return "mp_sub error state, can't subtract";
+
+    case MP_ADD_E :
+        return "mp_add error state, can't add";
+
+    case MP_MUL_E :
+        return "mp_mul error state, can't multiply";
+
+    case MP_MULMOD_E :
+        return "mp_mulmod error state, can't multiply mod";
+
+    case MP_MOD_E :
+        return "mp_mod error state, can't mod";
+
+    case MP_INVMOD_E :
+        return "mp_invmod error state, can't inv mod";
+
+    case MP_CMP_E :
+        return "mp_cmp error state";
+
+    case MP_ZERO_E :
+        return "mp zero result, not expected";
+
+    case MEMORY_E :
+        return "out of memory error";
+
+    case RSA_WRONG_TYPE_E :
+        return "RSA wrong block type for RSA function";
+
+    case RSA_BUFFER_E :
+        return "RSA buffer error, output too small or input too big";
+
+    case BUFFER_E :
+        return "Buffer error, output too small or input too big";
+
+    case ALGO_ID_E :
+        return "Setting Cert AlogID error";
+
+    case PUBLIC_KEY_E :
+        return "Setting Cert Public Key error";
+
+    case DATE_E :
+        return "Setting Cert Date validity error";
+
+    case SUBJECT_E :
+        return "Setting Cert Subject name error";
+
+    case ISSUER_E :
+        return "Setting Cert Issuer name error";
+
+    case CA_TRUE_E :
+        return "Setting basic constraint CA true error";
+
+    case EXTENSIONS_E :
+        return "Setting extensions error";
+
+    case ASN_PARSE_E :
+        return "ASN parsing error, invalid input";
+
+    case ASN_VERSION_E :
+        return "ASN version error, invalid number";
+
+    case ASN_GETINT_E :
+        return "ASN get big int error, invalid data";
+
+    case ASN_RSA_KEY_E :
+        return "ASN key init error, invalid input";
+
+    case ASN_OBJECT_ID_E :
+        return "ASN object id error, invalid id";
+
+    case ASN_TAG_NULL_E :
+        return "ASN tag error, not null";
+
+    case ASN_EXPECT_0_E :
+        return "ASN expect error, not zero";
+
+    case ASN_BITSTR_E :
+        return "ASN bit string error, wrong id";
+
+    case ASN_UNKNOWN_OID_E :
+        return "ASN oid error, unknown sum id";
+
+    case ASN_DATE_SZ_E :
+        return "ASN date error, bad size";
+
+    case ASN_BEFORE_DATE_E :
+        return "ASN date error, current date before";
+
+    case ASN_AFTER_DATE_E :
+        return "ASN date error, current date after";
+
+    case ASN_SIG_OID_E :
+        return "ASN signature error, mismatched oid";
+
+    case ASN_TIME_E :
+        return "ASN time error, unkown time type";
+
+    case ASN_INPUT_E :
+        return "ASN input error, not enough data";
+
+    case ASN_SIG_CONFIRM_E :
+        return "ASN sig error, confirm failure";
+
+    case ASN_SIG_HASH_E :
+        return "ASN sig error, unsupported hash type";
+
+    case ASN_SIG_KEY_E :
+        return "ASN sig error, unsupported key type";
+
+    case ASN_DH_KEY_E :
+        return "ASN key init error, invalid input";
+
+    case ASN_NTRU_KEY_E :
+        return "ASN NTRU key decode error, invalid input";
+
+    case ASN_CRIT_EXT_E:
+        return "X.509 Critical extension ignored";
+
+    case ECC_BAD_ARG_E :
+        return "ECC input argument wrong type, invalid input";
+
+    case ASN_ECC_KEY_E :
+        return "ECC ASN1 bad key data, invalid input";
+
+    case ECC_CURVE_OID_E :
+        return "ECC curve sum OID unsupported, invalid input";
+
+    case BAD_FUNC_ARG :
+        return "Bad function argument";
+
+    case NOT_COMPILED_IN :
+        return "Feature not compiled in";
+
+    case UNICODE_SIZE_E :
+        return "Unicode password too big";
+
+    case NO_PASSWORD :
+        return "No password provided by user";
+
+    case ALT_NAME_E :
+        return "Alt Name problem, too big";
+
+    case AES_GCM_AUTH_E:
+        return "AES-GCM Authentication check fail";
+
+    case AES_CCM_AUTH_E:
+        return "AES-CCM Authentication check fail";
+
+    case CAVIUM_INIT_E:
+        return "Cavium Init type error";
+
+    case COMPRESS_INIT_E:
+        return "Compress Init error";
+
+    case COMPRESS_E:
+        return "Compress error";
+
+    case DECOMPRESS_INIT_E:
+        return "DeCompress Init error";
+
+    case DECOMPRESS_E:
+        return "DeCompress error";
+
+    case BAD_ALIGN_E:
+        return "Bad alignment error, no alloc help";
+
+    case ASN_NO_SIGNER_E :
+        return "ASN no signer error to confirm failure";
+
+    case ASN_CRL_CONFIRM_E :
+        return "ASN CRL sig error, confirm failure";
+
+    case ASN_CRL_NO_SIGNER_E :
+        return "ASN CRL no signer error to confirm failure";
+
+    case ASN_OCSP_CONFIRM_E :
+        return "ASN OCSP sig error, confirm failure";
+
+    case BAD_ENC_STATE_E:
+        return "Bad ecc encrypt state operation";
+
+    case BAD_PADDING_E:
+        return "Bad padding, message wrong length";
+
+    case REQ_ATTRIBUTE_E:
+        return "Setting cert request attributes error";
+
+    case PKCS7_OID_E:
+        return "PKCS#7 error: mismatched OID value";
+
+    case PKCS7_RECIP_E:
+        return "PKCS#7 error: no matching recipient found";
+
+    case FIPS_NOT_ALLOWED_E:
+        return "FIPS mode not allowed error";
+
+    case ASN_NAME_INVALID_E:
+        return "Name Constraint error";
+
+    case RNG_FAILURE_E:
+        return "Random Number Generator failed";
+
+    case HMAC_MIN_KEYLEN_E:
+        return "FIPS Mode HMAC Minimum Key Length error";
+
+    case RSA_PAD_E:
+        return "Rsa Padding error";
+
+    case LENGTH_ONLY_E:
+        return "Output length only set, not for other use error";
+
+    case IN_CORE_FIPS_E:
+        return "In Core Integrity check FIPS error";
+
+    case AES_KAT_FIPS_E:
+        return "AES Known Answer Test check FIPS error";
+
+    case DES3_KAT_FIPS_E:
+        return "DES3 Known Answer Test check FIPS error";
+
+    case HMAC_KAT_FIPS_E:
+        return "HMAC Known Answer Test check FIPS error";
+
+    case RSA_KAT_FIPS_E:
+        return "RSA Known Answer Test check FIPS error";
+
+    case DRBG_KAT_FIPS_E:
+        return "DRBG Known Answer Test check FIPS error";
+
+    case DRBG_CONT_FIPS_E:
+        return "DRBG Continuous Test FIPS error";
+
+    case AESGCM_KAT_FIPS_E:
+        return "AESGCM Known Answer Test check FIPS error";
+
+    case THREAD_STORE_KEY_E:
+        return "Thread Storage Key Create error";
+
+    case THREAD_STORE_SET_E:
+        return "Thread Storage Set error";
+
+    case MAC_CMP_FAILED_E:
+        return "MAC comparison failed";
+
+    case IS_POINT_E:
+        return "ECC is point on curve failed";
+
+    case ECC_INF_E:
+        return " ECC point at infinity error";
+
+    case ECC_PRIV_KEY_E:
+        return " ECC private key is not valid error";
+
+    default:
+        return "unknown error number";
+
+    }
+
+#endif /* NO_ERROR_STRINGS */
+
+}
+
+void wc_ErrorString(int error, char* buffer)
+{
+    XSTRNCPY(buffer, wc_GetErrorString(error), WOLFSSL_MAX_ERROR_SZ);
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fe_low_mem.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fe_low_mem.c
new file mode 100644
index 0000000..80834f5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fe_low_mem.c
@@ -0,0 +1,596 @@
+/* fe_low_mem.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+/* Based from Daniel Beer's public domain word. */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#if defined(HAVE_ED25519) || defined(HAVE_CURVE25519)
+
+#include 
+
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+
+void fprime_copy(byte *x, const byte *a)
+{
+    int i;
+    for (i = 0; i < F25519_SIZE; i++)
+        x[i] = a[i];
+}
+
+
+void fe_copy(fe x, const fe a)
+{
+    int i;
+    for (i = 0; i < F25519_SIZE; i++)
+        x[i] = a[i];
+}
+
+
+/* Double an X-coordinate */
+static void xc_double(byte *x3, byte *z3,
+		      const byte *x1, const byte *z1)
+{
+	/* Explicit formulas database: dbl-1987-m
+	 *
+	 * source 1987 Montgomery "Speeding the Pollard and elliptic
+	 *   curve methods of factorization", page 261, fourth display
+	 * compute X3 = (X1^2-Z1^2)^2
+	 * compute Z3 = 4 X1 Z1 (X1^2 + a X1 Z1 + Z1^2)
+	 */
+	byte x1sq[F25519_SIZE];
+	byte z1sq[F25519_SIZE];
+	byte x1z1[F25519_SIZE];
+	byte a[F25519_SIZE];
+
+	fe_mul__distinct(x1sq, x1, x1);
+	fe_mul__distinct(z1sq, z1, z1);
+	fe_mul__distinct(x1z1, x1, z1);
+
+	fe_sub(a, x1sq, z1sq);
+	fe_mul__distinct(x3, a, a);
+
+	fe_mul_c(a, x1z1, 486662);
+	fe_add(a, x1sq, a);
+	fe_add(a, z1sq, a);
+	fe_mul__distinct(x1sq, x1z1, a);
+	fe_mul_c(z3, x1sq, 4);
+}
+
+
+/* Differential addition */
+static void xc_diffadd(byte *x5, byte *z5,
+		       const byte *x1, const byte *z1,
+		       const byte *x2, const byte *z2,
+		       const byte *x3, const byte *z3)
+{
+	/* Explicit formulas database: dbl-1987-m3
+	 *
+	 * source 1987 Montgomery "Speeding the Pollard and elliptic curve
+	 *   methods of factorization", page 261, fifth display, plus
+	 *   common-subexpression elimination
+	 * compute A = X2+Z2
+	 * compute B = X2-Z2
+	 * compute C = X3+Z3
+	 * compute D = X3-Z3
+	 * compute DA = D A
+	 * compute CB = C B
+	 * compute X5 = Z1(DA+CB)^2
+	 * compute Z5 = X1(DA-CB)^2
+	 */
+	byte da[F25519_SIZE];
+	byte cb[F25519_SIZE];
+	byte a[F25519_SIZE];
+	byte b[F25519_SIZE];
+
+	fe_add(a, x2, z2);
+	fe_sub(b, x3, z3); /* D */
+	fe_mul__distinct(da, a, b);
+
+	fe_sub(b, x2, z2);
+	fe_add(a, x3, z3); /* C */
+	fe_mul__distinct(cb, a, b);
+
+	fe_add(a, da, cb);
+	fe_mul__distinct(b, a, a);
+	fe_mul__distinct(x5, z1, b);
+
+	fe_sub(a, da, cb);
+	fe_mul__distinct(b, a, a);
+	fe_mul__distinct(z5, x1, b);
+}
+
+
+int curve25519(byte *result, byte *e, byte *q)
+{
+	/* Current point: P_m */
+	byte xm[F25519_SIZE];
+	byte zm[F25519_SIZE] = {1};
+
+	/* Predecessor: P_(m-1) */
+	byte xm1[F25519_SIZE] = {1};
+	byte zm1[F25519_SIZE] = {0};
+
+	int i;
+
+	/* Note: bit 254 is assumed to be 1 */
+	fe_copy(xm, q);
+
+	for (i = 253; i >= 0; i--) {
+		const int bit = (e[i >> 3] >> (i & 7)) & 1;
+		byte xms[F25519_SIZE];
+		byte zms[F25519_SIZE];
+
+		/* From P_m and P_(m-1), compute P_(2m) and P_(2m-1) */
+		xc_diffadd(xm1, zm1, q, f25519_one, xm, zm, xm1, zm1);
+		xc_double(xm, zm, xm, zm);
+
+		/* Compute P_(2m+1) */
+		xc_diffadd(xms, zms, xm1, zm1, xm, zm, q, f25519_one);
+
+		/* Select:
+		 *   bit = 1 --> (P_(2m+1), P_(2m))
+		 *   bit = 0 --> (P_(2m), P_(2m-1))
+		 */
+		fe_select(xm1, xm1, xm, bit);
+		fe_select(zm1, zm1, zm, bit);
+		fe_select(xm, xm, xms, bit);
+		fe_select(zm, zm, zms, bit);
+	}
+
+	/* Freeze out of projective coordinates */
+	fe_inv__distinct(zm1, zm);
+	fe_mul__distinct(result, zm1, xm);
+	fe_normalize(result);
+    return 0;
+}
+
+
+static void raw_add(byte *x, const byte *p)
+{
+	word16 c = 0;
+	int i;
+
+	for (i = 0; i < F25519_SIZE; i++) {
+		c += ((word16)x[i]) + ((word16)p[i]);
+		x[i] = c;
+		c >>= 8;
+	}
+}
+
+
+static void raw_try_sub(byte *x, const byte *p)
+{
+	byte minusp[F25519_SIZE];
+	word16 c = 0;
+	int i;
+
+	for (i = 0; i < F25519_SIZE; i++) {
+		c = ((word16)x[i]) - ((word16)p[i]) - c;
+		minusp[i] = c;
+		c = (c >> 8) & 1;
+	}
+
+	fprime_select(x, minusp, x, c);
+}
+
+
+static int prime_msb(const byte *p)
+{
+    int i;
+    byte x;
+    int shift = 1;
+    int z     = F25519_SIZE - 1;
+
+   /*
+       Test for any hot bits.
+       As soon as one instance is incountered set shift to 0.
+    */
+	for (i = F25519_SIZE - 1; i >= 0; i--) {
+        shift &= ((shift ^ ((-p[i] | p[i]) >> 7)) & 1);
+        z -= shift;
+    }
+	x = p[z];
+	z <<= 3;
+    shift = 1;
+    for (i = 0; i < 8; i++) {
+        shift &= ((-(x >> i) | (x >> i)) >> (7 - i) & 1);
+        z += shift;
+    }
+
+	return z - 1;
+}
+
+
+void fprime_select(byte *dst, const byte *zero, const byte *one, byte condition)
+{
+	const byte mask = -condition;
+	int i;
+
+	for (i = 0; i < F25519_SIZE; i++)
+		dst[i] = zero[i] ^ (mask & (one[i] ^ zero[i]));
+}
+
+
+void fprime_add(byte *r, const byte *a, const byte *modulus)
+{
+	raw_add(r, a);
+	raw_try_sub(r, modulus);
+}
+
+
+void fprime_sub(byte *r, const byte *a, const byte *modulus)
+{
+	raw_add(r, modulus);
+	raw_try_sub(r, a);
+	raw_try_sub(r, modulus);
+}
+
+
+void fprime_mul(byte *r, const byte *a, const byte *b,
+		const byte *modulus)
+{
+	word16 c = 0;
+	int i,j;
+
+	XMEMSET(r, 0, F25519_SIZE);
+
+	for (i = prime_msb(modulus); i >= 0; i--) {
+		const byte bit = (b[i >> 3] >> (i & 7)) & 1;
+		byte plusa[F25519_SIZE];
+
+	    for (j = 0; j < F25519_SIZE; j++) {
+		    c |= ((word16)r[j]) << 1;
+		    r[j] = c;
+		    c >>= 8;
+	    }
+		raw_try_sub(r, modulus);
+
+		fprime_copy(plusa, r);
+		fprime_add(plusa, a, modulus);
+
+		fprime_select(r, r, plusa, bit);
+	}
+}
+
+
+void fe_load(byte *x, word32 c)
+{
+	word32 i;
+
+	for (i = 0; i < sizeof(c); i++) {
+		x[i] = c;
+		c >>= 8;
+	}
+
+	for (; i < F25519_SIZE; i++)
+		x[i] = 0;
+}
+
+
+void fe_normalize(byte *x)
+{
+	byte minusp[F25519_SIZE];
+	word16 c;
+	int i;
+
+	/* Reduce using 2^255 = 19 mod p */
+	c = (x[31] >> 7) * 19;
+	x[31] &= 127;
+
+	for (i = 0; i < F25519_SIZE; i++) {
+		c += x[i];
+		x[i] = c;
+		c >>= 8;
+	}
+
+	/* The number is now less than 2^255 + 18, and therefore less than
+	 * 2p. Try subtracting p, and conditionally load the subtracted
+	 * value if underflow did not occur.
+	 */
+	c = 19;
+
+	for (i = 0; i + 1 < F25519_SIZE; i++) {
+		c += x[i];
+		minusp[i] = c;
+		c >>= 8;
+	}
+
+	c += ((word16)x[i]) - 128;
+	minusp[31] = c;
+
+	/* Load x-p if no underflow */
+	fe_select(x, minusp, x, (c >> 15) & 1);
+}
+
+
+void fe_select(byte *dst,
+		   const byte *zero, const byte *one,
+		   byte condition)
+{
+	const byte mask = -condition;
+	int i;
+
+	for (i = 0; i < F25519_SIZE; i++)
+		dst[i] = zero[i] ^ (mask & (one[i] ^ zero[i]));
+}
+
+
+void fe_add(fe r, const fe a, const fe b)
+{
+	word16 c = 0;
+	int i;
+
+	/* Add */
+	for (i = 0; i < F25519_SIZE; i++) {
+		c >>= 8;
+		c += ((word16)a[i]) + ((word16)b[i]);
+		r[i] = c;
+	}
+
+	/* Reduce with 2^255 = 19 mod p */
+	r[31] &= 127;
+	c = (c >> 7) * 19;
+
+	for (i = 0; i < F25519_SIZE; i++) {
+		c += r[i];
+		r[i] = c;
+		c >>= 8;
+	}
+}
+
+
+void fe_sub(fe r, const fe a, const fe b)
+{
+	word32 c = 0;
+	int i;
+
+	/* Calculate a + 2p - b, to avoid underflow */
+	c = 218;
+	for (i = 0; i + 1 < F25519_SIZE; i++) {
+		c += 65280 + ((word32)a[i]) - ((word32)b[i]);
+		r[i] = c;
+		c >>= 8;
+	}
+
+	c += ((word32)a[31]) - ((word32)b[31]);
+	r[31] = c & 127;
+	c = (c >> 7) * 19;
+
+	for (i = 0; i < F25519_SIZE; i++) {
+		c += r[i];
+		r[i] = c;
+		c >>= 8;
+	}
+}
+
+
+void fe_neg(fe r, const fe a)
+{
+	word32 c = 0;
+	int i;
+
+	/* Calculate 2p - a, to avoid underflow */
+	c = 218;
+	for (i = 0; i + 1 < F25519_SIZE; i++) {
+		c += 65280 - ((word32)a[i]);
+		r[i] = c;
+		c >>= 8;
+	}
+
+	c -= ((word32)a[31]);
+	r[31] = c & 127;
+	c = (c >> 7) * 19;
+
+	for (i = 0; i < F25519_SIZE; i++) {
+		c += r[i];
+		r[i] = c;
+		c >>= 8;
+	}
+}
+
+
+void fe_mul__distinct(byte *r, const byte *a, const byte *b)
+{
+	word32 c = 0;
+	int i;
+
+	for (i = 0; i < F25519_SIZE; i++) {
+		int j;
+
+		c >>= 8;
+		for (j = 0; j <= i; j++)
+			c += ((word32)a[j]) * ((word32)b[i - j]);
+
+		for (; j < F25519_SIZE; j++)
+			c += ((word32)a[j]) *
+			     ((word32)b[i + F25519_SIZE - j]) * 38;
+
+		r[i] = c;
+	}
+
+	r[31] &= 127;
+	c = (c >> 7) * 19;
+
+	for (i = 0; i < F25519_SIZE; i++) {
+		c += r[i];
+		r[i] = c;
+		c >>= 8;
+	}
+}
+
+
+void fe_mul(fe r, const fe a, const fe b)
+{
+	byte tmp[F25519_SIZE];
+
+	fe_mul__distinct(tmp, a, b);
+	fe_copy(r, tmp);
+}
+
+
+void fe_mul_c(byte *r, const byte *a, word32 b)
+{
+	word32 c = 0;
+	int i;
+
+	for (i = 0; i < F25519_SIZE; i++) {
+		c >>= 8;
+		c += b * ((word32)a[i]);
+		r[i] = c;
+	}
+
+	r[31] &= 127;
+	c >>= 7;
+	c *= 19;
+
+	for (i = 0; i < F25519_SIZE; i++) {
+		c += r[i];
+		r[i] = c;
+		c >>= 8;
+	}
+}
+
+
+void fe_inv__distinct(byte *r, const byte *x)
+{
+	byte s[F25519_SIZE];
+	int i;
+
+	/* This is a prime field, so by Fermat's little theorem:
+	 *
+	 *     x^(p-1) = 1 mod p
+	 *
+	 * Therefore, raise to (p-2) = 2^255-21 to get a multiplicative
+	 * inverse.
+	 *
+	 * This is a 255-bit binary number with the digits:
+	 *
+	 *     11111111... 01011
+	 *
+	 * We compute the result by the usual binary chain, but
+	 * alternate between keeping the accumulator in r and s, so as
+	 * to avoid copying temporaries.
+	 */
+
+	/* 1 1 */
+	fe_mul__distinct(s, x, x);
+	fe_mul__distinct(r, s, x);
+
+	/* 1 x 248 */
+	for (i = 0; i < 248; i++) {
+		fe_mul__distinct(s, r, r);
+		fe_mul__distinct(r, s, x);
+	}
+
+	/* 0 */
+	fe_mul__distinct(s, r, r);
+
+	/* 1 */
+	fe_mul__distinct(r, s, s);
+	fe_mul__distinct(s, r, x);
+
+	/* 0 */
+	fe_mul__distinct(r, s, s);
+
+	/* 1 */
+	fe_mul__distinct(s, r, r);
+	fe_mul__distinct(r, s, x);
+
+	/* 1 */
+	fe_mul__distinct(s, r, r);
+	fe_mul__distinct(r, s, x);
+}
+
+
+void fe_invert(fe r, const fe x)
+{
+	byte tmp[F25519_SIZE];
+
+	fe_inv__distinct(tmp, x);
+	fe_copy(r, tmp);
+}
+
+
+/* Raise x to the power of (p-5)/8 = 2^252-3, using s for temporary
+ * storage.
+ */
+static void exp2523(byte *r, const byte *x, byte *s)
+{
+	int i;
+
+	/* This number is a 252-bit number with the binary expansion:
+	 *
+	 *     111111... 01
+	 */
+
+	/* 1 1 */
+	fe_mul__distinct(r, x, x);
+	fe_mul__distinct(s, r, x);
+
+	/* 1 x 248 */
+	for (i = 0; i < 248; i++) {
+		fe_mul__distinct(r, s, s);
+		fe_mul__distinct(s, r, x);
+	}
+
+	/* 0 */
+	fe_mul__distinct(r, s, s);
+
+	/* 1 */
+	fe_mul__distinct(s, r, r);
+	fe_mul__distinct(r, s, x);
+}
+
+
+void fe_sqrt(byte *r, const byte *a)
+{
+	byte v[F25519_SIZE];
+	byte i[F25519_SIZE];
+	byte x[F25519_SIZE];
+	byte y[F25519_SIZE];
+
+	/* v = (2a)^((p-5)/8) [x = 2a] */
+	fe_mul_c(x, a, 2);
+	exp2523(v, x, y);
+
+	/* i = 2av^2 - 1 */
+	fe_mul__distinct(y, v, v);
+	fe_mul__distinct(i, x, y);
+	fe_load(y, 1);
+	fe_sub(i, i, y);
+
+	/* r = avi */
+	fe_mul__distinct(x, v, a);
+	fe_mul__distinct(r, x, i);
+}
+
+#endif /* HAVE_CURVE25519 or HAVE_ED25519 */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fe_operations.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fe_operations.c
new file mode 100644
index 0000000..da07c95
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fe_operations.c
@@ -0,0 +1,1397 @@
+/* fe_operations.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+ /* Based On Daniel J Bernstein's curve25519 Public Domain ref10 work. */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#if defined(HAVE_ED25519) || defined(HAVE_CURVE25519)
+
+#include 
+#include 
+
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+/*
+fe means field element.
+Here the field is \Z/(2^255-19).
+An element t, entries t[0]...t[9], represents the integer
+t[0]+2^26 t[1]+2^51 t[2]+2^77 t[3]+2^102 t[4]+...+2^230 t[9].
+Bounds on each t[i] vary depending on context.
+*/
+
+uint64_t load_3(const unsigned char *in)
+{
+  uint64_t result;
+  result = (uint64_t) in[0];
+  result |= ((uint64_t) in[1]) << 8;
+  result |= ((uint64_t) in[2]) << 16;
+  return result;
+}
+
+
+uint64_t load_4(const unsigned char *in)
+{
+  uint64_t result;
+  result = (uint64_t) in[0];
+  result |= ((uint64_t) in[1]) << 8;
+  result |= ((uint64_t) in[2]) << 16;
+  result |= ((uint64_t) in[3]) << 24;
+  return result;
+}
+
+
+/*
+h = 1
+*/
+
+void fe_1(fe h)
+{
+  h[0] = 1;
+  h[1] = 0;
+  h[2] = 0;
+  h[3] = 0;
+  h[4] = 0;
+  h[5] = 0;
+  h[6] = 0;
+  h[7] = 0;
+  h[8] = 0;
+  h[9] = 0;
+}
+
+
+/*
+h = 0
+*/
+
+void fe_0(fe h)
+{
+  h[0] = 0;
+  h[1] = 0;
+  h[2] = 0;
+  h[3] = 0;
+  h[4] = 0;
+  h[5] = 0;
+  h[6] = 0;
+  h[7] = 0;
+  h[8] = 0;
+  h[9] = 0;
+}
+
+
+int curve25519(byte* q, byte* n, byte* p)
+{
+  unsigned char e[32];
+  unsigned int i;
+  fe x1;
+  fe x2;
+  fe z2;
+  fe x3;
+  fe z3;
+  fe tmp0;
+  fe tmp1;
+  int pos;
+  unsigned int swap;
+  unsigned int b;
+
+  for (i = 0;i < 32;++i) e[i] = n[i];
+  e[0] &= 248;
+  e[31] &= 127;
+  e[31] |= 64;
+
+  fe_frombytes(x1,p);
+  fe_1(x2);
+  fe_0(z2);
+  fe_copy(x3,x1);
+  fe_1(z3);
+
+  swap = 0;
+  for (pos = 254;pos >= 0;--pos) {
+    b = e[pos / 8] >> (pos & 7);
+    b &= 1;
+    swap ^= b;
+    fe_cswap(x2,x3,swap);
+    fe_cswap(z2,z3,swap);
+    swap = b;
+
+    /* montgomery */
+	fe_sub(tmp0,x3,z3);
+	fe_sub(tmp1,x2,z2);
+	fe_add(x2,x2,z2);
+	fe_add(z2,x3,z3);
+	fe_mul(z3,tmp0,x2);
+	fe_mul(z2,z2,tmp1);
+	fe_sq(tmp0,tmp1);
+	fe_sq(tmp1,x2);
+	fe_add(x3,z3,z2);
+	fe_sub(z2,z3,z2);
+	fe_mul(x2,tmp1,tmp0);
+	fe_sub(tmp1,tmp1,tmp0);
+	fe_sq(z2,z2);
+	fe_mul121666(z3,tmp1);
+	fe_sq(x3,x3);
+	fe_add(tmp0,tmp0,z3);
+	fe_mul(z3,x1,z2);
+	fe_mul(z2,tmp1,tmp0);
+  }
+  fe_cswap(x2,x3,swap);
+  fe_cswap(z2,z3,swap);
+
+  fe_invert(z2,z2);
+  fe_mul(x2,x2,z2);
+  fe_tobytes(q,x2);
+
+  return 0;
+}
+
+
+/*
+h = f * f
+Can overlap h with f.
+
+Preconditions:
+   |f| bounded by 1.65*2^26,1.65*2^25,1.65*2^26,1.65*2^25,etc.
+
+Postconditions:
+   |h| bounded by 1.01*2^25,1.01*2^24,1.01*2^25,1.01*2^24,etc.
+*/
+
+/*
+See fe_mul.c for discussion of implementation strategy.
+*/
+
+void fe_sq(fe h,const fe f)
+{
+  int32_t f0 = f[0];
+  int32_t f1 = f[1];
+  int32_t f2 = f[2];
+  int32_t f3 = f[3];
+  int32_t f4 = f[4];
+  int32_t f5 = f[5];
+  int32_t f6 = f[6];
+  int32_t f7 = f[7];
+  int32_t f8 = f[8];
+  int32_t f9 = f[9];
+  int32_t f0_2 = 2 * f0;
+  int32_t f1_2 = 2 * f1;
+  int32_t f2_2 = 2 * f2;
+  int32_t f3_2 = 2 * f3;
+  int32_t f4_2 = 2 * f4;
+  int32_t f5_2 = 2 * f5;
+  int32_t f6_2 = 2 * f6;
+  int32_t f7_2 = 2 * f7;
+  int32_t f5_38 = 38 * f5; /* 1.959375*2^30 */
+  int32_t f6_19 = 19 * f6; /* 1.959375*2^30 */
+  int32_t f7_38 = 38 * f7; /* 1.959375*2^30 */
+  int32_t f8_19 = 19 * f8; /* 1.959375*2^30 */
+  int32_t f9_38 = 38 * f9; /* 1.959375*2^30 */
+  int64_t f0f0    = f0   * (int64_t) f0;
+  int64_t f0f1_2  = f0_2 * (int64_t) f1;
+  int64_t f0f2_2  = f0_2 * (int64_t) f2;
+  int64_t f0f3_2  = f0_2 * (int64_t) f3;
+  int64_t f0f4_2  = f0_2 * (int64_t) f4;
+  int64_t f0f5_2  = f0_2 * (int64_t) f5;
+  int64_t f0f6_2  = f0_2 * (int64_t) f6;
+  int64_t f0f7_2  = f0_2 * (int64_t) f7;
+  int64_t f0f8_2  = f0_2 * (int64_t) f8;
+  int64_t f0f9_2  = f0_2 * (int64_t) f9;
+  int64_t f1f1_2  = f1_2 * (int64_t) f1;
+  int64_t f1f2_2  = f1_2 * (int64_t) f2;
+  int64_t f1f3_4  = f1_2 * (int64_t) f3_2;
+  int64_t f1f4_2  = f1_2 * (int64_t) f4;
+  int64_t f1f5_4  = f1_2 * (int64_t) f5_2;
+  int64_t f1f6_2  = f1_2 * (int64_t) f6;
+  int64_t f1f7_4  = f1_2 * (int64_t) f7_2;
+  int64_t f1f8_2  = f1_2 * (int64_t) f8;
+  int64_t f1f9_76 = f1_2 * (int64_t) f9_38;
+  int64_t f2f2    = f2   * (int64_t) f2;
+  int64_t f2f3_2  = f2_2 * (int64_t) f3;
+  int64_t f2f4_2  = f2_2 * (int64_t) f4;
+  int64_t f2f5_2  = f2_2 * (int64_t) f5;
+  int64_t f2f6_2  = f2_2 * (int64_t) f6;
+  int64_t f2f7_2  = f2_2 * (int64_t) f7;
+  int64_t f2f8_38 = f2_2 * (int64_t) f8_19;
+  int64_t f2f9_38 = f2   * (int64_t) f9_38;
+  int64_t f3f3_2  = f3_2 * (int64_t) f3;
+  int64_t f3f4_2  = f3_2 * (int64_t) f4;
+  int64_t f3f5_4  = f3_2 * (int64_t) f5_2;
+  int64_t f3f6_2  = f3_2 * (int64_t) f6;
+  int64_t f3f7_76 = f3_2 * (int64_t) f7_38;
+  int64_t f3f8_38 = f3_2 * (int64_t) f8_19;
+  int64_t f3f9_76 = f3_2 * (int64_t) f9_38;
+  int64_t f4f4    = f4   * (int64_t) f4;
+  int64_t f4f5_2  = f4_2 * (int64_t) f5;
+  int64_t f4f6_38 = f4_2 * (int64_t) f6_19;
+  int64_t f4f7_38 = f4   * (int64_t) f7_38;
+  int64_t f4f8_38 = f4_2 * (int64_t) f8_19;
+  int64_t f4f9_38 = f4   * (int64_t) f9_38;
+  int64_t f5f5_38 = f5   * (int64_t) f5_38;
+  int64_t f5f6_38 = f5_2 * (int64_t) f6_19;
+  int64_t f5f7_76 = f5_2 * (int64_t) f7_38;
+  int64_t f5f8_38 = f5_2 * (int64_t) f8_19;
+  int64_t f5f9_76 = f5_2 * (int64_t) f9_38;
+  int64_t f6f6_19 = f6   * (int64_t) f6_19;
+  int64_t f6f7_38 = f6   * (int64_t) f7_38;
+  int64_t f6f8_38 = f6_2 * (int64_t) f8_19;
+  int64_t f6f9_38 = f6   * (int64_t) f9_38;
+  int64_t f7f7_38 = f7   * (int64_t) f7_38;
+  int64_t f7f8_38 = f7_2 * (int64_t) f8_19;
+  int64_t f7f9_76 = f7_2 * (int64_t) f9_38;
+  int64_t f8f8_19 = f8   * (int64_t) f8_19;
+  int64_t f8f9_38 = f8   * (int64_t) f9_38;
+  int64_t f9f9_38 = f9   * (int64_t) f9_38;
+  int64_t h0 = f0f0  +f1f9_76+f2f8_38+f3f7_76+f4f6_38+f5f5_38;
+  int64_t h1 = f0f1_2+f2f9_38+f3f8_38+f4f7_38+f5f6_38;
+  int64_t h2 = f0f2_2+f1f1_2 +f3f9_76+f4f8_38+f5f7_76+f6f6_19;
+  int64_t h3 = f0f3_2+f1f2_2 +f4f9_38+f5f8_38+f6f7_38;
+  int64_t h4 = f0f4_2+f1f3_4 +f2f2   +f5f9_76+f6f8_38+f7f7_38;
+  int64_t h5 = f0f5_2+f1f4_2 +f2f3_2 +f6f9_38+f7f8_38;
+  int64_t h6 = f0f6_2+f1f5_4 +f2f4_2 +f3f3_2 +f7f9_76+f8f8_19;
+  int64_t h7 = f0f7_2+f1f6_2 +f2f5_2 +f3f4_2 +f8f9_38;
+  int64_t h8 = f0f8_2+f1f7_4 +f2f6_2 +f3f5_4 +f4f4   +f9f9_38;
+  int64_t h9 = f0f9_2+f1f8_2 +f2f7_2 +f3f6_2 +f4f5_2;
+  int64_t carry0;
+  int64_t carry1;
+  int64_t carry2;
+  int64_t carry3;
+  int64_t carry4;
+  int64_t carry5;
+  int64_t carry6;
+  int64_t carry7;
+  int64_t carry8;
+  int64_t carry9;
+
+  carry0 = (h0 + (int64_t) (1<<25)) >> 26; h1 += carry0; h0 -= carry0 << 26;
+  carry4 = (h4 + (int64_t) (1<<25)) >> 26; h5 += carry4; h4 -= carry4 << 26;
+
+  carry1 = (h1 + (int64_t) (1<<24)) >> 25; h2 += carry1; h1 -= carry1 << 25;
+  carry5 = (h5 + (int64_t) (1<<24)) >> 25; h6 += carry5; h5 -= carry5 << 25;
+
+  carry2 = (h2 + (int64_t) (1<<25)) >> 26; h3 += carry2; h2 -= carry2 << 26;
+  carry6 = (h6 + (int64_t) (1<<25)) >> 26; h7 += carry6; h6 -= carry6 << 26;
+
+  carry3 = (h3 + (int64_t) (1<<24)) >> 25; h4 += carry3; h3 -= carry3 << 25;
+  carry7 = (h7 + (int64_t) (1<<24)) >> 25; h8 += carry7; h7 -= carry7 << 25;
+
+  carry4 = (h4 + (int64_t) (1<<25)) >> 26; h5 += carry4; h4 -= carry4 << 26;
+  carry8 = (h8 + (int64_t) (1<<25)) >> 26; h9 += carry8; h8 -= carry8 << 26;
+
+  carry9 = (h9 + (int64_t) (1<<24)) >> 25; h0 += carry9 * 19; h9 -= carry9 << 25;
+
+  carry0 = (h0 + (int64_t) (1<<25)) >> 26; h1 += carry0; h0 -= carry0 << 26;
+
+  h[0] = (int32_t)h0;
+  h[1] = (int32_t)h1;
+  h[2] = (int32_t)h2;
+  h[3] = (int32_t)h3;
+  h[4] = (int32_t)h4;
+  h[5] = (int32_t)h5;
+  h[6] = (int32_t)h6;
+  h[7] = (int32_t)h7;
+  h[8] = (int32_t)h8;
+  h[9] = (int32_t)h9;
+}
+
+
+/*
+h = f + g
+Can overlap h with f or g.
+
+Preconditions:
+   |f| bounded by 1.1*2^25,1.1*2^24,1.1*2^25,1.1*2^24,etc.
+   |g| bounded by 1.1*2^25,1.1*2^24,1.1*2^25,1.1*2^24,etc.
+
+Postconditions:
+   |h| bounded by 1.1*2^26,1.1*2^25,1.1*2^26,1.1*2^25,etc.
+*/
+
+void fe_add(fe h,const fe f,const fe g)
+{
+  int32_t f0 = f[0];
+  int32_t f1 = f[1];
+  int32_t f2 = f[2];
+  int32_t f3 = f[3];
+  int32_t f4 = f[4];
+  int32_t f5 = f[5];
+  int32_t f6 = f[6];
+  int32_t f7 = f[7];
+  int32_t f8 = f[8];
+  int32_t f9 = f[9];
+  int32_t g0 = g[0];
+  int32_t g1 = g[1];
+  int32_t g2 = g[2];
+  int32_t g3 = g[3];
+  int32_t g4 = g[4];
+  int32_t g5 = g[5];
+  int32_t g6 = g[6];
+  int32_t g7 = g[7];
+  int32_t g8 = g[8];
+  int32_t g9 = g[9];
+  int32_t h0 = f0 + g0;
+  int32_t h1 = f1 + g1;
+  int32_t h2 = f2 + g2;
+  int32_t h3 = f3 + g3;
+  int32_t h4 = f4 + g4;
+  int32_t h5 = f5 + g5;
+  int32_t h6 = f6 + g6;
+  int32_t h7 = f7 + g7;
+  int32_t h8 = f8 + g8;
+  int32_t h9 = f9 + g9;
+  h[0] = h0;
+  h[1] = h1;
+  h[2] = h2;
+  h[3] = h3;
+  h[4] = h4;
+  h[5] = h5;
+  h[6] = h6;
+  h[7] = h7;
+  h[8] = h8;
+  h[9] = h9;
+}
+
+
+/*
+Preconditions:
+  |h| bounded by 1.1*2^26,1.1*2^25,1.1*2^26,1.1*2^25,etc.
+
+Write p=2^255-19; q=floor(h/p).
+Basic claim: q = floor(2^(-255)(h + 19 2^(-25)h9 + 2^(-1))).
+
+Proof:
+  Have |h|<=p so |q|<=1 so |19^2 2^(-255) q|<1/4.
+  Also have |h-2^230 h9|<2^231 so |19 2^(-255)(h-2^230 h9)|<1/4.
+
+  Write y=2^(-1)-19^2 2^(-255)q-19 2^(-255)(h-2^230 h9).
+  Then 0> 25;
+  q = (h0 + q) >> 26;
+  q = (h1 + q) >> 25;
+  q = (h2 + q) >> 26;
+  q = (h3 + q) >> 25;
+  q = (h4 + q) >> 26;
+  q = (h5 + q) >> 25;
+  q = (h6 + q) >> 26;
+  q = (h7 + q) >> 25;
+  q = (h8 + q) >> 26;
+  q = (h9 + q) >> 25;
+
+  /* Goal: Output h-(2^255-19)q, which is between 0 and 2^255-20. */
+  h0 += 19 * q;
+  /* Goal: Output h-2^255 q, which is between 0 and 2^255-20. */
+
+  carry0 = h0 >> 26; h1 += carry0; h0 -= carry0 << 26;
+  carry1 = h1 >> 25; h2 += carry1; h1 -= carry1 << 25;
+  carry2 = h2 >> 26; h3 += carry2; h2 -= carry2 << 26;
+  carry3 = h3 >> 25; h4 += carry3; h3 -= carry3 << 25;
+  carry4 = h4 >> 26; h5 += carry4; h4 -= carry4 << 26;
+  carry5 = h5 >> 25; h6 += carry5; h5 -= carry5 << 25;
+  carry6 = h6 >> 26; h7 += carry6; h6 -= carry6 << 26;
+  carry7 = h7 >> 25; h8 += carry7; h7 -= carry7 << 25;
+  carry8 = h8 >> 26; h9 += carry8; h8 -= carry8 << 26;
+  carry9 = h9 >> 25;               h9 -= carry9 << 25;
+                  /* h10 = carry9 */
+
+  /*
+  Goal: Output h0+...+2^255 h10-2^255 q, which is between 0 and 2^255-20.
+  Have h0+...+2^230 h9 between 0 and 2^255-1;
+  evidently 2^255 h10-2^255 q = 0.
+  Goal: Output h0+...+2^230 h9.
+  */
+
+  s[0] = h0 >> 0;
+  s[1] = h0 >> 8;
+  s[2] = h0 >> 16;
+  s[3] = (h0 >> 24) | (h1 << 2);
+  s[4] = h1 >> 6;
+  s[5] = h1 >> 14;
+  s[6] = (h1 >> 22) | (h2 << 3);
+  s[7] = h2 >> 5;
+  s[8] = h2 >> 13;
+  s[9] = (h2 >> 21) | (h3 << 5);
+  s[10] = h3 >> 3;
+  s[11] = h3 >> 11;
+  s[12] = (h3 >> 19) | (h4 << 6);
+  s[13] = h4 >> 2;
+  s[14] = h4 >> 10;
+  s[15] = h4 >> 18;
+  s[16] = h5 >> 0;
+  s[17] = h5 >> 8;
+  s[18] = h5 >> 16;
+  s[19] = (h5 >> 24) | (h6 << 1);
+  s[20] = h6 >> 7;
+  s[21] = h6 >> 15;
+  s[22] = (h6 >> 23) | (h7 << 3);
+  s[23] = h7 >> 5;
+  s[24] = h7 >> 13;
+  s[25] = (h7 >> 21) | (h8 << 4);
+  s[26] = h8 >> 4;
+  s[27] = h8 >> 12;
+  s[28] = (h8 >> 20) | (h9 << 6);
+  s[29] = h9 >> 2;
+  s[30] = h9 >> 10;
+  s[31] = h9 >> 18;
+}
+
+
+/*
+h = f - g
+Can overlap h with f or g.
+
+Preconditions:
+   |f| bounded by 1.1*2^25,1.1*2^24,1.1*2^25,1.1*2^24,etc.
+   |g| bounded by 1.1*2^25,1.1*2^24,1.1*2^25,1.1*2^24,etc.
+
+Postconditions:
+   |h| bounded by 1.1*2^26,1.1*2^25,1.1*2^26,1.1*2^25,etc.
+*/
+
+void fe_sub(fe h,const fe f,const fe g)
+{
+  int32_t f0 = f[0];
+  int32_t f1 = f[1];
+  int32_t f2 = f[2];
+  int32_t f3 = f[3];
+  int32_t f4 = f[4];
+  int32_t f5 = f[5];
+  int32_t f6 = f[6];
+  int32_t f7 = f[7];
+  int32_t f8 = f[8];
+  int32_t f9 = f[9];
+  int32_t g0 = g[0];
+  int32_t g1 = g[1];
+  int32_t g2 = g[2];
+  int32_t g3 = g[3];
+  int32_t g4 = g[4];
+  int32_t g5 = g[5];
+  int32_t g6 = g[6];
+  int32_t g7 = g[7];
+  int32_t g8 = g[8];
+  int32_t g9 = g[9];
+  int32_t h0 = f0 - g0;
+  int32_t h1 = f1 - g1;
+  int32_t h2 = f2 - g2;
+  int32_t h3 = f3 - g3;
+  int32_t h4 = f4 - g4;
+  int32_t h5 = f5 - g5;
+  int32_t h6 = f6 - g6;
+  int32_t h7 = f7 - g7;
+  int32_t h8 = f8 - g8;
+  int32_t h9 = f9 - g9;
+  h[0] = h0;
+  h[1] = h1;
+  h[2] = h2;
+  h[3] = h3;
+  h[4] = h4;
+  h[5] = h5;
+  h[6] = h6;
+  h[7] = h7;
+  h[8] = h8;
+  h[9] = h9;
+}
+
+
+/*
+Ignores top bit of h.
+*/
+
+void fe_frombytes(fe h,const unsigned char *s)
+{
+  int64_t h0 = load_4(s);
+  int64_t h1 = load_3(s + 4) << 6;
+  int64_t h2 = load_3(s + 7) << 5;
+  int64_t h3 = load_3(s + 10) << 3;
+  int64_t h4 = load_3(s + 13) << 2;
+  int64_t h5 = load_4(s + 16);
+  int64_t h6 = load_3(s + 20) << 7;
+  int64_t h7 = load_3(s + 23) << 5;
+  int64_t h8 = load_3(s + 26) << 4;
+  int64_t h9 = (load_3(s + 29) & 8388607) << 2;
+  int64_t carry0;
+  int64_t carry1;
+  int64_t carry2;
+  int64_t carry3;
+  int64_t carry4;
+  int64_t carry5;
+  int64_t carry6;
+  int64_t carry7;
+  int64_t carry8;
+  int64_t carry9;
+
+  carry9 = (h9 + (int64_t) (1<<24)) >> 25; h0 += carry9 * 19; h9 -= carry9 << 25;
+  carry1 = (h1 + (int64_t) (1<<24)) >> 25; h2 += carry1; h1 -= carry1 << 25;
+  carry3 = (h3 + (int64_t) (1<<24)) >> 25; h4 += carry3; h3 -= carry3 << 25;
+  carry5 = (h5 + (int64_t) (1<<24)) >> 25; h6 += carry5; h5 -= carry5 << 25;
+  carry7 = (h7 + (int64_t) (1<<24)) >> 25; h8 += carry7; h7 -= carry7 << 25;
+
+  carry0 = (h0 + (int64_t) (1<<25)) >> 26; h1 += carry0; h0 -= carry0 << 26;
+  carry2 = (h2 + (int64_t) (1<<25)) >> 26; h3 += carry2; h2 -= carry2 << 26;
+  carry4 = (h4 + (int64_t) (1<<25)) >> 26; h5 += carry4; h4 -= carry4 << 26;
+  carry6 = (h6 + (int64_t) (1<<25)) >> 26; h7 += carry6; h6 -= carry6 << 26;
+  carry8 = (h8 + (int64_t) (1<<25)) >> 26; h9 += carry8; h8 -= carry8 << 26;
+
+  h[0] = (int32_t)h0;
+  h[1] = (int32_t)h1;
+  h[2] = (int32_t)h2;
+  h[3] = (int32_t)h3;
+  h[4] = (int32_t)h4;
+  h[5] = (int32_t)h5;
+  h[6] = (int32_t)h6;
+  h[7] = (int32_t)h7;
+  h[8] = (int32_t)h8;
+  h[9] = (int32_t)h9;
+}
+
+
+void fe_invert(fe out,const fe z)
+{
+  fe t0;
+  fe t1;
+  fe t2;
+  fe t3;
+  int i;
+
+  /* pow225521 */
+  fe_sq(t0,z); for (i = 1;i < 1;++i) fe_sq(t0,t0);
+  fe_sq(t1,t0); for (i = 1;i < 2;++i) fe_sq(t1,t1);
+  fe_mul(t1,z,t1);
+  fe_mul(t0,t0,t1);
+  fe_sq(t2,t0); for (i = 1;i < 1;++i) fe_sq(t2,t2);
+  fe_mul(t1,t1,t2);
+  fe_sq(t2,t1); for (i = 1;i < 5;++i) fe_sq(t2,t2);
+  fe_mul(t1,t2,t1);
+  fe_sq(t2,t1); for (i = 1;i < 10;++i) fe_sq(t2,t2);
+  fe_mul(t2,t2,t1);
+  fe_sq(t3,t2); for (i = 1;i < 20;++i) fe_sq(t3,t3);
+  fe_mul(t2,t3,t2);
+  fe_sq(t2,t2); for (i = 1;i < 10;++i) fe_sq(t2,t2);
+  fe_mul(t1,t2,t1);
+  fe_sq(t2,t1); for (i = 1;i < 50;++i) fe_sq(t2,t2);
+  fe_mul(t2,t2,t1);
+  fe_sq(t3,t2); for (i = 1;i < 100;++i) fe_sq(t3,t3);
+  fe_mul(t2,t3,t2);
+  fe_sq(t2,t2); for (i = 1;i < 50;++i) fe_sq(t2,t2);
+  fe_mul(t1,t2,t1);
+  fe_sq(t1,t1); for (i = 1;i < 5;++i) fe_sq(t1,t1);
+  fe_mul(out,t1,t0);
+
+  return;
+}
+
+
+/*
+h = f
+*/
+
+void fe_copy(fe h,const fe f)
+{
+  int32_t f0 = f[0];
+  int32_t f1 = f[1];
+  int32_t f2 = f[2];
+  int32_t f3 = f[3];
+  int32_t f4 = f[4];
+  int32_t f5 = f[5];
+  int32_t f6 = f[6];
+  int32_t f7 = f[7];
+  int32_t f8 = f[8];
+  int32_t f9 = f[9];
+  h[0] = f0;
+  h[1] = f1;
+  h[2] = f2;
+  h[3] = f3;
+  h[4] = f4;
+  h[5] = f5;
+  h[6] = f6;
+  h[7] = f7;
+  h[8] = f8;
+  h[9] = f9;
+}
+
+
+/*
+h = f * g
+Can overlap h with f or g.
+
+Preconditions:
+   |f| bounded by 1.65*2^26,1.65*2^25,1.65*2^26,1.65*2^25,etc.
+   |g| bounded by 1.65*2^26,1.65*2^25,1.65*2^26,1.65*2^25,etc.
+
+Postconditions:
+   |h| bounded by 1.01*2^25,1.01*2^24,1.01*2^25,1.01*2^24,etc.
+*/
+
+/*
+Notes on implementation strategy:
+
+Using schoolbook multiplication.
+Karatsuba would save a little in some cost models.
+
+Most multiplications by 2 and 19 are 32-bit precomputations;
+cheaper than 64-bit postcomputations.
+
+There is one remaining multiplication by 19 in the carry chain;
+one *19 precomputation can be merged into this,
+but the resulting data flow is considerably less clean.
+
+There are 12 carries below.
+10 of them are 2-way parallelizable and vectorizable.
+Can get away with 11 carries, but then data flow is much deeper.
+
+With tighter constraints on inputs can squeeze carries into int32.
+*/
+
+void fe_mul(fe h,const fe f,const fe g)
+{
+  int32_t f0 = f[0];
+  int32_t f1 = f[1];
+  int32_t f2 = f[2];
+  int32_t f3 = f[3];
+  int32_t f4 = f[4];
+  int32_t f5 = f[5];
+  int32_t f6 = f[6];
+  int32_t f7 = f[7];
+  int32_t f8 = f[8];
+  int32_t f9 = f[9];
+  int32_t g0 = g[0];
+  int32_t g1 = g[1];
+  int32_t g2 = g[2];
+  int32_t g3 = g[3];
+  int32_t g4 = g[4];
+  int32_t g5 = g[5];
+  int32_t g6 = g[6];
+  int32_t g7 = g[7];
+  int32_t g8 = g[8];
+  int32_t g9 = g[9];
+  int32_t g1_19 = 19 * g1; /* 1.959375*2^29 */
+  int32_t g2_19 = 19 * g2; /* 1.959375*2^30; still ok */
+  int32_t g3_19 = 19 * g3;
+  int32_t g4_19 = 19 * g4;
+  int32_t g5_19 = 19 * g5;
+  int32_t g6_19 = 19 * g6;
+  int32_t g7_19 = 19 * g7;
+  int32_t g8_19 = 19 * g8;
+  int32_t g9_19 = 19 * g9;
+  int32_t f1_2 = 2 * f1;
+  int32_t f3_2 = 2 * f3;
+  int32_t f5_2 = 2 * f5;
+  int32_t f7_2 = 2 * f7;
+  int32_t f9_2 = 2 * f9;
+  int64_t f0g0    = f0   * (int64_t) g0;
+  int64_t f0g1    = f0   * (int64_t) g1;
+  int64_t f0g2    = f0   * (int64_t) g2;
+  int64_t f0g3    = f0   * (int64_t) g3;
+  int64_t f0g4    = f0   * (int64_t) g4;
+  int64_t f0g5    = f0   * (int64_t) g5;
+  int64_t f0g6    = f0   * (int64_t) g6;
+  int64_t f0g7    = f0   * (int64_t) g7;
+  int64_t f0g8    = f0   * (int64_t) g8;
+  int64_t f0g9    = f0   * (int64_t) g9;
+  int64_t f1g0    = f1   * (int64_t) g0;
+  int64_t f1g1_2  = f1_2 * (int64_t) g1;
+  int64_t f1g2    = f1   * (int64_t) g2;
+  int64_t f1g3_2  = f1_2 * (int64_t) g3;
+  int64_t f1g4    = f1   * (int64_t) g4;
+  int64_t f1g5_2  = f1_2 * (int64_t) g5;
+  int64_t f1g6    = f1   * (int64_t) g6;
+  int64_t f1g7_2  = f1_2 * (int64_t) g7;
+  int64_t f1g8    = f1   * (int64_t) g8;
+  int64_t f1g9_38 = f1_2 * (int64_t) g9_19;
+  int64_t f2g0    = f2   * (int64_t) g0;
+  int64_t f2g1    = f2   * (int64_t) g1;
+  int64_t f2g2    = f2   * (int64_t) g2;
+  int64_t f2g3    = f2   * (int64_t) g3;
+  int64_t f2g4    = f2   * (int64_t) g4;
+  int64_t f2g5    = f2   * (int64_t) g5;
+  int64_t f2g6    = f2   * (int64_t) g6;
+  int64_t f2g7    = f2   * (int64_t) g7;
+  int64_t f2g8_19 = f2   * (int64_t) g8_19;
+  int64_t f2g9_19 = f2   * (int64_t) g9_19;
+  int64_t f3g0    = f3   * (int64_t) g0;
+  int64_t f3g1_2  = f3_2 * (int64_t) g1;
+  int64_t f3g2    = f3   * (int64_t) g2;
+  int64_t f3g3_2  = f3_2 * (int64_t) g3;
+  int64_t f3g4    = f3   * (int64_t) g4;
+  int64_t f3g5_2  = f3_2 * (int64_t) g5;
+  int64_t f3g6    = f3   * (int64_t) g6;
+  int64_t f3g7_38 = f3_2 * (int64_t) g7_19;
+  int64_t f3g8_19 = f3   * (int64_t) g8_19;
+  int64_t f3g9_38 = f3_2 * (int64_t) g9_19;
+  int64_t f4g0    = f4   * (int64_t) g0;
+  int64_t f4g1    = f4   * (int64_t) g1;
+  int64_t f4g2    = f4   * (int64_t) g2;
+  int64_t f4g3    = f4   * (int64_t) g3;
+  int64_t f4g4    = f4   * (int64_t) g4;
+  int64_t f4g5    = f4   * (int64_t) g5;
+  int64_t f4g6_19 = f4   * (int64_t) g6_19;
+  int64_t f4g7_19 = f4   * (int64_t) g7_19;
+  int64_t f4g8_19 = f4   * (int64_t) g8_19;
+  int64_t f4g9_19 = f4   * (int64_t) g9_19;
+  int64_t f5g0    = f5   * (int64_t) g0;
+  int64_t f5g1_2  = f5_2 * (int64_t) g1;
+  int64_t f5g2    = f5   * (int64_t) g2;
+  int64_t f5g3_2  = f5_2 * (int64_t) g3;
+  int64_t f5g4    = f5   * (int64_t) g4;
+  int64_t f5g5_38 = f5_2 * (int64_t) g5_19;
+  int64_t f5g6_19 = f5   * (int64_t) g6_19;
+  int64_t f5g7_38 = f5_2 * (int64_t) g7_19;
+  int64_t f5g8_19 = f5   * (int64_t) g8_19;
+  int64_t f5g9_38 = f5_2 * (int64_t) g9_19;
+  int64_t f6g0    = f6   * (int64_t) g0;
+  int64_t f6g1    = f6   * (int64_t) g1;
+  int64_t f6g2    = f6   * (int64_t) g2;
+  int64_t f6g3    = f6   * (int64_t) g3;
+  int64_t f6g4_19 = f6   * (int64_t) g4_19;
+  int64_t f6g5_19 = f6   * (int64_t) g5_19;
+  int64_t f6g6_19 = f6   * (int64_t) g6_19;
+  int64_t f6g7_19 = f6   * (int64_t) g7_19;
+  int64_t f6g8_19 = f6   * (int64_t) g8_19;
+  int64_t f6g9_19 = f6   * (int64_t) g9_19;
+  int64_t f7g0    = f7   * (int64_t) g0;
+  int64_t f7g1_2  = f7_2 * (int64_t) g1;
+  int64_t f7g2    = f7   * (int64_t) g2;
+  int64_t f7g3_38 = f7_2 * (int64_t) g3_19;
+  int64_t f7g4_19 = f7   * (int64_t) g4_19;
+  int64_t f7g5_38 = f7_2 * (int64_t) g5_19;
+  int64_t f7g6_19 = f7   * (int64_t) g6_19;
+  int64_t f7g7_38 = f7_2 * (int64_t) g7_19;
+  int64_t f7g8_19 = f7   * (int64_t) g8_19;
+  int64_t f7g9_38 = f7_2 * (int64_t) g9_19;
+  int64_t f8g0    = f8   * (int64_t) g0;
+  int64_t f8g1    = f8   * (int64_t) g1;
+  int64_t f8g2_19 = f8   * (int64_t) g2_19;
+  int64_t f8g3_19 = f8   * (int64_t) g3_19;
+  int64_t f8g4_19 = f8   * (int64_t) g4_19;
+  int64_t f8g5_19 = f8   * (int64_t) g5_19;
+  int64_t f8g6_19 = f8   * (int64_t) g6_19;
+  int64_t f8g7_19 = f8   * (int64_t) g7_19;
+  int64_t f8g8_19 = f8   * (int64_t) g8_19;
+  int64_t f8g9_19 = f8   * (int64_t) g9_19;
+  int64_t f9g0    = f9   * (int64_t) g0;
+  int64_t f9g1_38 = f9_2 * (int64_t) g1_19;
+  int64_t f9g2_19 = f9   * (int64_t) g2_19;
+  int64_t f9g3_38 = f9_2 * (int64_t) g3_19;
+  int64_t f9g4_19 = f9   * (int64_t) g4_19;
+  int64_t f9g5_38 = f9_2 * (int64_t) g5_19;
+  int64_t f9g6_19 = f9   * (int64_t) g6_19;
+  int64_t f9g7_38 = f9_2 * (int64_t) g7_19;
+  int64_t f9g8_19 = f9   * (int64_t) g8_19;
+  int64_t f9g9_38 = f9_2 * (int64_t) g9_19;
+  int64_t h0 = f0g0+f1g9_38+f2g8_19+f3g7_38+f4g6_19+f5g5_38+f6g4_19+f7g3_38+f8g2_19+f9g1_38;
+  int64_t h1 = f0g1+f1g0   +f2g9_19+f3g8_19+f4g7_19+f5g6_19+f6g5_19+f7g4_19+f8g3_19+f9g2_19;
+  int64_t h2 = f0g2+f1g1_2 +f2g0   +f3g9_38+f4g8_19+f5g7_38+f6g6_19+f7g5_38+f8g4_19+f9g3_38;
+  int64_t h3 = f0g3+f1g2   +f2g1   +f3g0   +f4g9_19+f5g8_19+f6g7_19+f7g6_19+f8g5_19+f9g4_19;
+  int64_t h4 = f0g4+f1g3_2 +f2g2   +f3g1_2 +f4g0   +f5g9_38+f6g8_19+f7g7_38+f8g6_19+f9g5_38;
+  int64_t h5 = f0g5+f1g4   +f2g3   +f3g2   +f4g1   +f5g0   +f6g9_19+f7g8_19+f8g7_19+f9g6_19;
+  int64_t h6 = f0g6+f1g5_2 +f2g4   +f3g3_2 +f4g2   +f5g1_2 +f6g0   +f7g9_38+f8g8_19+f9g7_38;
+  int64_t h7 = f0g7+f1g6   +f2g5   +f3g4   +f4g3   +f5g2   +f6g1   +f7g0   +f8g9_19+f9g8_19;
+  int64_t h8 = f0g8+f1g7_2 +f2g6   +f3g5_2 +f4g4   +f5g3_2 +f6g2   +f7g1_2 +f8g0   +f9g9_38;
+  int64_t h9 = f0g9+f1g8   +f2g7   +f3g6   +f4g5   +f5g4   +f6g3   +f7g2   +f8g1   +f9g0   ;
+  int64_t carry0;
+  int64_t carry1;
+  int64_t carry2;
+  int64_t carry3;
+  int64_t carry4;
+  int64_t carry5;
+  int64_t carry6;
+  int64_t carry7;
+  int64_t carry8;
+  int64_t carry9;
+
+  /*
+  |h0| <= (1.65*1.65*2^52*(1+19+19+19+19)+1.65*1.65*2^50*(38+38+38+38+38))
+    i.e. |h0| <= 1.4*2^60; narrower ranges for h2, h4, h6, h8
+  |h1| <= (1.65*1.65*2^51*(1+1+19+19+19+19+19+19+19+19))
+    i.e. |h1| <= 1.7*2^59; narrower ranges for h3, h5, h7, h9
+  */
+
+  carry0 = (h0 + (int64_t) (1<<25)) >> 26; h1 += carry0; h0 -= carry0 << 26;
+  carry4 = (h4 + (int64_t) (1<<25)) >> 26; h5 += carry4; h4 -= carry4 << 26;
+  /* |h0| <= 2^25 */
+  /* |h4| <= 2^25 */
+  /* |h1| <= 1.71*2^59 */
+  /* |h5| <= 1.71*2^59 */
+
+  carry1 = (h1 + (int64_t) (1<<24)) >> 25; h2 += carry1; h1 -= carry1 << 25;
+  carry5 = (h5 + (int64_t) (1<<24)) >> 25; h6 += carry5; h5 -= carry5 << 25;
+  /* |h1| <= 2^24; from now on fits into int32 */
+  /* |h5| <= 2^24; from now on fits into int32 */
+  /* |h2| <= 1.41*2^60 */
+  /* |h6| <= 1.41*2^60 */
+
+  carry2 = (h2 + (int64_t) (1<<25)) >> 26; h3 += carry2; h2 -= carry2 << 26;
+  carry6 = (h6 + (int64_t) (1<<25)) >> 26; h7 += carry6; h6 -= carry6 << 26;
+  /* |h2| <= 2^25; from now on fits into int32 unchanged */
+  /* |h6| <= 2^25; from now on fits into int32 unchanged */
+  /* |h3| <= 1.71*2^59 */
+  /* |h7| <= 1.71*2^59 */
+
+  carry3 = (h3 + (int64_t) (1<<24)) >> 25; h4 += carry3; h3 -= carry3 << 25;
+  carry7 = (h7 + (int64_t) (1<<24)) >> 25; h8 += carry7; h7 -= carry7 << 25;
+  /* |h3| <= 2^24; from now on fits into int32 unchanged */
+  /* |h7| <= 2^24; from now on fits into int32 unchanged */
+  /* |h4| <= 1.72*2^34 */
+  /* |h8| <= 1.41*2^60 */
+
+  carry4 = (h4 + (int64_t) (1<<25)) >> 26; h5 += carry4; h4 -= carry4 << 26;
+  carry8 = (h8 + (int64_t) (1<<25)) >> 26; h9 += carry8; h8 -= carry8 << 26;
+  /* |h4| <= 2^25; from now on fits into int32 unchanged */
+  /* |h8| <= 2^25; from now on fits into int32 unchanged */
+  /* |h5| <= 1.01*2^24 */
+  /* |h9| <= 1.71*2^59 */
+
+  carry9 = (h9 + (int64_t) (1<<24)) >> 25; h0 += carry9 * 19; h9 -= carry9 << 25;
+  /* |h9| <= 2^24; from now on fits into int32 unchanged */
+  /* |h0| <= 1.1*2^39 */
+
+  carry0 = (h0 + (int64_t) (1<<25)) >> 26; h1 += carry0; h0 -= carry0 << 26;
+  /* |h0| <= 2^25; from now on fits into int32 unchanged */
+  /* |h1| <= 1.01*2^24 */
+
+  h[0] = (int32_t)h0;
+  h[1] = (int32_t)h1;
+  h[2] = (int32_t)h2;
+  h[3] = (int32_t)h3;
+  h[4] = (int32_t)h4;
+  h[5] = (int32_t)h5;
+  h[6] = (int32_t)h6;
+  h[7] = (int32_t)h7;
+  h[8] = (int32_t)h8;
+  h[9] = (int32_t)h9;
+}
+
+
+/*
+Replace (f,g) with (g,f) if b == 1;
+replace (f,g) with (f,g) if b == 0.
+
+Preconditions: b in {0,1}.
+*/
+
+void fe_cswap(fe f,fe g,unsigned int b)
+{
+  int32_t f0 = f[0];
+  int32_t f1 = f[1];
+  int32_t f2 = f[2];
+  int32_t f3 = f[3];
+  int32_t f4 = f[4];
+  int32_t f5 = f[5];
+  int32_t f6 = f[6];
+  int32_t f7 = f[7];
+  int32_t f8 = f[8];
+  int32_t f9 = f[9];
+  int32_t g0 = g[0];
+  int32_t g1 = g[1];
+  int32_t g2 = g[2];
+  int32_t g3 = g[3];
+  int32_t g4 = g[4];
+  int32_t g5 = g[5];
+  int32_t g6 = g[6];
+  int32_t g7 = g[7];
+  int32_t g8 = g[8];
+  int32_t g9 = g[9];
+  int32_t x0 = f0 ^ g0;
+  int32_t x1 = f1 ^ g1;
+  int32_t x2 = f2 ^ g2;
+  int32_t x3 = f3 ^ g3;
+  int32_t x4 = f4 ^ g4;
+  int32_t x5 = f5 ^ g5;
+  int32_t x6 = f6 ^ g6;
+  int32_t x7 = f7 ^ g7;
+  int32_t x8 = f8 ^ g8;
+  int32_t x9 = f9 ^ g9;
+  b = -b;
+  x0 &= b;
+  x1 &= b;
+  x2 &= b;
+  x3 &= b;
+  x4 &= b;
+  x5 &= b;
+  x6 &= b;
+  x7 &= b;
+  x8 &= b;
+  x9 &= b;
+  f[0] = f0 ^ x0;
+  f[1] = f1 ^ x1;
+  f[2] = f2 ^ x2;
+  f[3] = f3 ^ x3;
+  f[4] = f4 ^ x4;
+  f[5] = f5 ^ x5;
+  f[6] = f6 ^ x6;
+  f[7] = f7 ^ x7;
+  f[8] = f8 ^ x8;
+  f[9] = f9 ^ x9;
+  g[0] = g0 ^ x0;
+  g[1] = g1 ^ x1;
+  g[2] = g2 ^ x2;
+  g[3] = g3 ^ x3;
+  g[4] = g4 ^ x4;
+  g[5] = g5 ^ x5;
+  g[6] = g6 ^ x6;
+  g[7] = g7 ^ x7;
+  g[8] = g8 ^ x8;
+  g[9] = g9 ^ x9;
+}
+
+
+/*
+h = f * 121666
+Can overlap h with f.
+
+Preconditions:
+   |f| bounded by 1.1*2^26,1.1*2^25,1.1*2^26,1.1*2^25,etc.
+
+Postconditions:
+   |h| bounded by 1.1*2^25,1.1*2^24,1.1*2^25,1.1*2^24,etc.
+*/
+
+void fe_mul121666(fe h,fe f)
+{
+  int32_t f0 = f[0];
+  int32_t f1 = f[1];
+  int32_t f2 = f[2];
+  int32_t f3 = f[3];
+  int32_t f4 = f[4];
+  int32_t f5 = f[5];
+  int32_t f6 = f[6];
+  int32_t f7 = f[7];
+  int32_t f8 = f[8];
+  int32_t f9 = f[9];
+  int64_t h0 = f0 * (int64_t) 121666;
+  int64_t h1 = f1 * (int64_t) 121666;
+  int64_t h2 = f2 * (int64_t) 121666;
+  int64_t h3 = f3 * (int64_t) 121666;
+  int64_t h4 = f4 * (int64_t) 121666;
+  int64_t h5 = f5 * (int64_t) 121666;
+  int64_t h6 = f6 * (int64_t) 121666;
+  int64_t h7 = f7 * (int64_t) 121666;
+  int64_t h8 = f8 * (int64_t) 121666;
+  int64_t h9 = f9 * (int64_t) 121666;
+  int64_t carry0;
+  int64_t carry1;
+  int64_t carry2;
+  int64_t carry3;
+  int64_t carry4;
+  int64_t carry5;
+  int64_t carry6;
+  int64_t carry7;
+  int64_t carry8;
+  int64_t carry9;
+
+  carry9 = (h9 + (int64_t) (1<<24)) >> 25; h0 += carry9 * 19; h9 -= carry9 << 25;
+  carry1 = (h1 + (int64_t) (1<<24)) >> 25; h2 += carry1; h1 -= carry1 << 25;
+  carry3 = (h3 + (int64_t) (1<<24)) >> 25; h4 += carry3; h3 -= carry3 << 25;
+  carry5 = (h5 + (int64_t) (1<<24)) >> 25; h6 += carry5; h5 -= carry5 << 25;
+  carry7 = (h7 + (int64_t) (1<<24)) >> 25; h8 += carry7; h7 -= carry7 << 25;
+
+  carry0 = (h0 + (int64_t) (1<<25)) >> 26; h1 += carry0; h0 -= carry0 << 26;
+  carry2 = (h2 + (int64_t) (1<<25)) >> 26; h3 += carry2; h2 -= carry2 << 26;
+  carry4 = (h4 + (int64_t) (1<<25)) >> 26; h5 += carry4; h4 -= carry4 << 26;
+  carry6 = (h6 + (int64_t) (1<<25)) >> 26; h7 += carry6; h6 -= carry6 << 26;
+  carry8 = (h8 + (int64_t) (1<<25)) >> 26; h9 += carry8; h8 -= carry8 << 26;
+
+  h[0] = (int32_t)h0;
+  h[1] = (int32_t)h1;
+  h[2] = (int32_t)h2;
+  h[3] = (int32_t)h3;
+  h[4] = (int32_t)h4;
+  h[5] = (int32_t)h5;
+  h[6] = (int32_t)h6;
+  h[7] = (int32_t)h7;
+  h[8] = (int32_t)h8;
+  h[9] = (int32_t)h9;
+}
+
+
+/*
+h = 2 * f * f
+Can overlap h with f.
+
+Preconditions:
+   |f| bounded by 1.65*2^26,1.65*2^25,1.65*2^26,1.65*2^25,etc.
+
+Postconditions:
+   |h| bounded by 1.01*2^25,1.01*2^24,1.01*2^25,1.01*2^24,etc.
+*/
+
+/*
+See fe_mul.c for discussion of implementation strategy.
+*/
+
+void fe_sq2(fe h,const fe f)
+{
+  int32_t f0 = f[0];
+  int32_t f1 = f[1];
+  int32_t f2 = f[2];
+  int32_t f3 = f[3];
+  int32_t f4 = f[4];
+  int32_t f5 = f[5];
+  int32_t f6 = f[6];
+  int32_t f7 = f[7];
+  int32_t f8 = f[8];
+  int32_t f9 = f[9];
+  int32_t f0_2 = 2 * f0;
+  int32_t f1_2 = 2 * f1;
+  int32_t f2_2 = 2 * f2;
+  int32_t f3_2 = 2 * f3;
+  int32_t f4_2 = 2 * f4;
+  int32_t f5_2 = 2 * f5;
+  int32_t f6_2 = 2 * f6;
+  int32_t f7_2 = 2 * f7;
+  int32_t f5_38 = 38 * f5; /* 1.959375*2^30 */
+  int32_t f6_19 = 19 * f6; /* 1.959375*2^30 */
+  int32_t f7_38 = 38 * f7; /* 1.959375*2^30 */
+  int32_t f8_19 = 19 * f8; /* 1.959375*2^30 */
+  int32_t f9_38 = 38 * f9; /* 1.959375*2^30 */
+  int64_t f0f0    = f0   * (int64_t) f0;
+  int64_t f0f1_2  = f0_2 * (int64_t) f1;
+  int64_t f0f2_2  = f0_2 * (int64_t) f2;
+  int64_t f0f3_2  = f0_2 * (int64_t) f3;
+  int64_t f0f4_2  = f0_2 * (int64_t) f4;
+  int64_t f0f5_2  = f0_2 * (int64_t) f5;
+  int64_t f0f6_2  = f0_2 * (int64_t) f6;
+  int64_t f0f7_2  = f0_2 * (int64_t) f7;
+  int64_t f0f8_2  = f0_2 * (int64_t) f8;
+  int64_t f0f9_2  = f0_2 * (int64_t) f9;
+  int64_t f1f1_2  = f1_2 * (int64_t) f1;
+  int64_t f1f2_2  = f1_2 * (int64_t) f2;
+  int64_t f1f3_4  = f1_2 * (int64_t) f3_2;
+  int64_t f1f4_2  = f1_2 * (int64_t) f4;
+  int64_t f1f5_4  = f1_2 * (int64_t) f5_2;
+  int64_t f1f6_2  = f1_2 * (int64_t) f6;
+  int64_t f1f7_4  = f1_2 * (int64_t) f7_2;
+  int64_t f1f8_2  = f1_2 * (int64_t) f8;
+  int64_t f1f9_76 = f1_2 * (int64_t) f9_38;
+  int64_t f2f2    = f2   * (int64_t) f2;
+  int64_t f2f3_2  = f2_2 * (int64_t) f3;
+  int64_t f2f4_2  = f2_2 * (int64_t) f4;
+  int64_t f2f5_2  = f2_2 * (int64_t) f5;
+  int64_t f2f6_2  = f2_2 * (int64_t) f6;
+  int64_t f2f7_2  = f2_2 * (int64_t) f7;
+  int64_t f2f8_38 = f2_2 * (int64_t) f8_19;
+  int64_t f2f9_38 = f2   * (int64_t) f9_38;
+  int64_t f3f3_2  = f3_2 * (int64_t) f3;
+  int64_t f3f4_2  = f3_2 * (int64_t) f4;
+  int64_t f3f5_4  = f3_2 * (int64_t) f5_2;
+  int64_t f3f6_2  = f3_2 * (int64_t) f6;
+  int64_t f3f7_76 = f3_2 * (int64_t) f7_38;
+  int64_t f3f8_38 = f3_2 * (int64_t) f8_19;
+  int64_t f3f9_76 = f3_2 * (int64_t) f9_38;
+  int64_t f4f4    = f4   * (int64_t) f4;
+  int64_t f4f5_2  = f4_2 * (int64_t) f5;
+  int64_t f4f6_38 = f4_2 * (int64_t) f6_19;
+  int64_t f4f7_38 = f4   * (int64_t) f7_38;
+  int64_t f4f8_38 = f4_2 * (int64_t) f8_19;
+  int64_t f4f9_38 = f4   * (int64_t) f9_38;
+  int64_t f5f5_38 = f5   * (int64_t) f5_38;
+  int64_t f5f6_38 = f5_2 * (int64_t) f6_19;
+  int64_t f5f7_76 = f5_2 * (int64_t) f7_38;
+  int64_t f5f8_38 = f5_2 * (int64_t) f8_19;
+  int64_t f5f9_76 = f5_2 * (int64_t) f9_38;
+  int64_t f6f6_19 = f6   * (int64_t) f6_19;
+  int64_t f6f7_38 = f6   * (int64_t) f7_38;
+  int64_t f6f8_38 = f6_2 * (int64_t) f8_19;
+  int64_t f6f9_38 = f6   * (int64_t) f9_38;
+  int64_t f7f7_38 = f7   * (int64_t) f7_38;
+  int64_t f7f8_38 = f7_2 * (int64_t) f8_19;
+  int64_t f7f9_76 = f7_2 * (int64_t) f9_38;
+  int64_t f8f8_19 = f8   * (int64_t) f8_19;
+  int64_t f8f9_38 = f8   * (int64_t) f9_38;
+  int64_t f9f9_38 = f9   * (int64_t) f9_38;
+  int64_t h0 = f0f0  +f1f9_76+f2f8_38+f3f7_76+f4f6_38+f5f5_38;
+  int64_t h1 = f0f1_2+f2f9_38+f3f8_38+f4f7_38+f5f6_38;
+  int64_t h2 = f0f2_2+f1f1_2 +f3f9_76+f4f8_38+f5f7_76+f6f6_19;
+  int64_t h3 = f0f3_2+f1f2_2 +f4f9_38+f5f8_38+f6f7_38;
+  int64_t h4 = f0f4_2+f1f3_4 +f2f2   +f5f9_76+f6f8_38+f7f7_38;
+  int64_t h5 = f0f5_2+f1f4_2 +f2f3_2 +f6f9_38+f7f8_38;
+  int64_t h6 = f0f6_2+f1f5_4 +f2f4_2 +f3f3_2 +f7f9_76+f8f8_19;
+  int64_t h7 = f0f7_2+f1f6_2 +f2f5_2 +f3f4_2 +f8f9_38;
+  int64_t h8 = f0f8_2+f1f7_4 +f2f6_2 +f3f5_4 +f4f4   +f9f9_38;
+  int64_t h9 = f0f9_2+f1f8_2 +f2f7_2 +f3f6_2 +f4f5_2;
+  int64_t carry0;
+  int64_t carry1;
+  int64_t carry2;
+  int64_t carry3;
+  int64_t carry4;
+  int64_t carry5;
+  int64_t carry6;
+  int64_t carry7;
+  int64_t carry8;
+  int64_t carry9;
+
+  h0 += h0;
+  h1 += h1;
+  h2 += h2;
+  h3 += h3;
+  h4 += h4;
+  h5 += h5;
+  h6 += h6;
+  h7 += h7;
+  h8 += h8;
+  h9 += h9;
+
+  carry0 = (h0 + (int64_t) (1<<25)) >> 26; h1 += carry0; h0 -= carry0 << 26;
+  carry4 = (h4 + (int64_t) (1<<25)) >> 26; h5 += carry4; h4 -= carry4 << 26;
+
+  carry1 = (h1 + (int64_t) (1<<24)) >> 25; h2 += carry1; h1 -= carry1 << 25;
+  carry5 = (h5 + (int64_t) (1<<24)) >> 25; h6 += carry5; h5 -= carry5 << 25;
+
+  carry2 = (h2 + (int64_t) (1<<25)) >> 26; h3 += carry2; h2 -= carry2 << 26;
+  carry6 = (h6 + (int64_t) (1<<25)) >> 26; h7 += carry6; h6 -= carry6 << 26;
+
+  carry3 = (h3 + (int64_t) (1<<24)) >> 25; h4 += carry3; h3 -= carry3 << 25;
+  carry7 = (h7 + (int64_t) (1<<24)) >> 25; h8 += carry7; h7 -= carry7 << 25;
+
+  carry4 = (h4 + (int64_t) (1<<25)) >> 26; h5 += carry4; h4 -= carry4 << 26;
+  carry8 = (h8 + (int64_t) (1<<25)) >> 26; h9 += carry8; h8 -= carry8 << 26;
+
+  carry9 = (h9 + (int64_t) (1<<24)) >> 25; h0 += carry9 * 19; h9 -= carry9 << 25;
+
+  carry0 = (h0 + (int64_t) (1<<25)) >> 26; h1 += carry0; h0 -= carry0 << 26;
+
+  h[0] = (int32_t)h0;
+  h[1] = (int32_t)h1;
+  h[2] = (int32_t)h2;
+  h[3] = (int32_t)h3;
+  h[4] = (int32_t)h4;
+  h[5] = (int32_t)h5;
+  h[6] = (int32_t)h6;
+  h[7] = (int32_t)h7;
+  h[8] = (int32_t)h8;
+  h[9] = (int32_t)h9;
+}
+
+
+void fe_pow22523(fe out,const fe z)
+{
+  fe t0;
+  fe t1;
+  fe t2;
+  int i;
+
+  fe_sq(t0,z); for (i = 1;i < 1;++i) fe_sq(t0,t0);
+  fe_sq(t1,t0); for (i = 1;i < 2;++i) fe_sq(t1,t1);
+  fe_mul(t1,z,t1);
+  fe_mul(t0,t0,t1);
+  fe_sq(t0,t0); for (i = 1;i < 1;++i) fe_sq(t0,t0);
+  fe_mul(t0,t1,t0);
+  fe_sq(t1,t0); for (i = 1;i < 5;++i) fe_sq(t1,t1);
+  fe_mul(t0,t1,t0);
+  fe_sq(t1,t0); for (i = 1;i < 10;++i) fe_sq(t1,t1);
+  fe_mul(t1,t1,t0);
+  fe_sq(t2,t1); for (i = 1;i < 20;++i) fe_sq(t2,t2);
+  fe_mul(t1,t2,t1);
+  fe_sq(t1,t1); for (i = 1;i < 10;++i) fe_sq(t1,t1);
+  fe_mul(t0,t1,t0);
+  fe_sq(t1,t0); for (i = 1;i < 50;++i) fe_sq(t1,t1);
+  fe_mul(t1,t1,t0);
+  fe_sq(t2,t1); for (i = 1;i < 100;++i) fe_sq(t2,t2);
+  fe_mul(t1,t2,t1);
+  fe_sq(t1,t1); for (i = 1;i < 50;++i) fe_sq(t1,t1);
+  fe_mul(t0,t1,t0);
+  fe_sq(t0,t0); for (i = 1;i < 2;++i) fe_sq(t0,t0);
+  fe_mul(out,t0,z);
+
+  return;
+}
+
+
+/*
+h = -f
+
+Preconditions:
+   |f| bounded by 1.1*2^25,1.1*2^24,1.1*2^25,1.1*2^24,etc.
+
+Postconditions:
+   |h| bounded by 1.1*2^25,1.1*2^24,1.1*2^25,1.1*2^24,etc.
+*/
+
+void fe_neg(fe h,const fe f)
+{
+  int32_t f0 = f[0];
+  int32_t f1 = f[1];
+  int32_t f2 = f[2];
+  int32_t f3 = f[3];
+  int32_t f4 = f[4];
+  int32_t f5 = f[5];
+  int32_t f6 = f[6];
+  int32_t f7 = f[7];
+  int32_t f8 = f[8];
+  int32_t f9 = f[9];
+  int32_t h0 = -f0;
+  int32_t h1 = -f1;
+  int32_t h2 = -f2;
+  int32_t h3 = -f3;
+  int32_t h4 = -f4;
+  int32_t h5 = -f5;
+  int32_t h6 = -f6;
+  int32_t h7 = -f7;
+  int32_t h8 = -f8;
+  int32_t h9 = -f9;
+  h[0] = h0;
+  h[1] = h1;
+  h[2] = h2;
+  h[3] = h3;
+  h[4] = h4;
+  h[5] = h5;
+  h[6] = h6;
+  h[7] = h7;
+  h[8] = h8;
+  h[9] = h9;
+}
+
+
+/*
+Preconditions:
+   |f| bounded by 1.1*2^26,1.1*2^25,1.1*2^26,1.1*2^25,etc.
+*/
+
+static const unsigned char zero[32];
+
+int fe_isnonzero(const fe f)
+{
+  unsigned char s[32];
+  fe_tobytes(s,f);
+  return ConstantCompare(s,zero,32);
+}
+
+
+/*
+return 1 if f is in {1,3,5,...,q-2}
+return 0 if f is in {0,2,4,...,q-1}
+
+Preconditions:
+   |f| bounded by 1.1*2^26,1.1*2^25,1.1*2^26,1.1*2^25,etc.
+*/
+
+int fe_isnegative(const fe f)
+{
+  unsigned char s[32];
+  fe_tobytes(s,f);
+  return s[0] & 1;
+}
+
+
+/*
+Replace (f,g) with (g,g) if b == 1;
+replace (f,g) with (f,g) if b == 0.
+
+Preconditions: b in {0,1}.
+*/
+
+void fe_cmov(fe f,const fe g,unsigned int b)
+{
+  int32_t f0 = f[0];
+  int32_t f1 = f[1];
+  int32_t f2 = f[2];
+  int32_t f3 = f[3];
+  int32_t f4 = f[4];
+  int32_t f5 = f[5];
+  int32_t f6 = f[6];
+  int32_t f7 = f[7];
+  int32_t f8 = f[8];
+  int32_t f9 = f[9];
+  int32_t g0 = g[0];
+  int32_t g1 = g[1];
+  int32_t g2 = g[2];
+  int32_t g3 = g[3];
+  int32_t g4 = g[4];
+  int32_t g5 = g[5];
+  int32_t g6 = g[6];
+  int32_t g7 = g[7];
+  int32_t g8 = g[8];
+  int32_t g9 = g[9];
+  int32_t x0 = f0 ^ g0;
+  int32_t x1 = f1 ^ g1;
+  int32_t x2 = f2 ^ g2;
+  int32_t x3 = f3 ^ g3;
+  int32_t x4 = f4 ^ g4;
+  int32_t x5 = f5 ^ g5;
+  int32_t x6 = f6 ^ g6;
+  int32_t x7 = f7 ^ g7;
+  int32_t x8 = f8 ^ g8;
+  int32_t x9 = f9 ^ g9;
+  b = -b;
+  x0 &= b;
+  x1 &= b;
+  x2 &= b;
+  x3 &= b;
+  x4 &= b;
+  x5 &= b;
+  x6 &= b;
+  x7 &= b;
+  x8 &= b;
+  x9 &= b;
+  f[0] = f0 ^ x0;
+  f[1] = f1 ^ x1;
+  f[2] = f2 ^ x2;
+  f[3] = f3 ^ x3;
+  f[4] = f4 ^ x4;
+  f[5] = f5 ^ x5;
+  f[6] = f6 ^ x6;
+  f[7] = f7 ^ x7;
+  f[8] = f8 ^ x8;
+  f[9] = f9 ^ x9;
+}
+#endif /* HAVE ED25519 or CURVE25519 */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mont_small.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mont_small.i
new file mode 100644
index 0000000..c4a339b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mont_small.i
@@ -0,0 +1,3860 @@
+/* fp_mont_small.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_SMALL_MONT_SET
+/* computes x/R == x (mod N) via Montgomery Reduction */
+void fp_montgomery_reduce_small(fp_int *a, fp_int *m, fp_digit mp)
+{
+   fp_digit c[FP_SIZE], *_c, *tmpm, mu, cy;
+   int      oldused, x, y, pa;
+
+#if defined(USE_MEMSET)
+   /* now zero the buff */
+   memset(c, 0, sizeof c);
+#endif
+   pa = m->used;
+
+   /* copy the input */
+   oldused = a->used;
+   for (x = 0; x < oldused; x++) {
+       c[x] = a->dp[x];
+   }
+#if !defined(USE_MEMSET)
+   for (; x < 2*pa+3; x++) {
+       c[x] = 0;
+   }
+#endif
+   MONT_START;
+
+   switch (pa) {
+      case 1:
+            x = 0; cy   = 0;
+            LOOP_START;
+            _c   = c + 0;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+         break;
+      case 2:
+            x = 0; cy   = 0;
+            LOOP_START;
+            _c   = c + 0;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 1; cy   = 0;
+            LOOP_START;
+            _c   = c + 1;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+         break;
+      case 3:
+            x = 0; cy   = 0;
+            LOOP_START;
+            _c   = c + 0;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 1; cy   = 0;
+            LOOP_START;
+            _c   = c + 1;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 2; cy   = 0;
+            LOOP_START;
+            _c   = c + 2;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+         break;
+      case 4:
+            x = 0; cy   = 0;
+            LOOP_START;
+            _c   = c + 0;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 1; cy   = 0;
+            LOOP_START;
+            _c   = c + 1;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 2; cy   = 0;
+            LOOP_START;
+            _c   = c + 2;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 3; cy   = 0;
+            LOOP_START;
+            _c   = c + 3;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+         break;
+      case 5:
+            x = 0; cy   = 0;
+            LOOP_START;
+            _c   = c + 0;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 1; cy   = 0;
+            LOOP_START;
+            _c   = c + 1;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 2; cy   = 0;
+            LOOP_START;
+            _c   = c + 2;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 3; cy   = 0;
+            LOOP_START;
+            _c   = c + 3;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 4; cy   = 0;
+            LOOP_START;
+            _c   = c + 4;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+         break;
+      case 6:
+            x = 0; cy   = 0;
+            LOOP_START;
+            _c   = c + 0;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 1; cy   = 0;
+            LOOP_START;
+            _c   = c + 1;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 2; cy   = 0;
+            LOOP_START;
+            _c   = c + 2;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 3; cy   = 0;
+            LOOP_START;
+            _c   = c + 3;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 4; cy   = 0;
+            LOOP_START;
+            _c   = c + 4;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 5; cy   = 0;
+            LOOP_START;
+            _c   = c + 5;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+         break;
+      case 7:
+            x = 0; cy   = 0;
+            LOOP_START;
+            _c   = c + 0;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 1; cy   = 0;
+            LOOP_START;
+            _c   = c + 1;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 2; cy   = 0;
+            LOOP_START;
+            _c   = c + 2;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 3; cy   = 0;
+            LOOP_START;
+            _c   = c + 3;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 4; cy   = 0;
+            LOOP_START;
+            _c   = c + 4;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 5; cy   = 0;
+            LOOP_START;
+            _c   = c + 5;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 6; cy   = 0;
+            LOOP_START;
+            _c   = c + 6;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+         break;
+      case 8:
+            x = 0; cy   = 0;
+            LOOP_START;
+            _c   = c + 0;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 1; cy   = 0;
+            LOOP_START;
+            _c   = c + 1;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 2; cy   = 0;
+            LOOP_START;
+            _c   = c + 2;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 3; cy   = 0;
+            LOOP_START;
+            _c   = c + 3;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 4; cy   = 0;
+            LOOP_START;
+            _c   = c + 4;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 5; cy   = 0;
+            LOOP_START;
+            _c   = c + 5;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 6; cy   = 0;
+            LOOP_START;
+            _c   = c + 6;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 7; cy   = 0;
+            LOOP_START;
+            _c   = c + 7;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+         break;
+      case 9:
+            x = 0; cy   = 0;
+            LOOP_START;
+            _c   = c + 0;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 1; cy   = 0;
+            LOOP_START;
+            _c   = c + 1;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 2; cy   = 0;
+            LOOP_START;
+            _c   = c + 2;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 3; cy   = 0;
+            LOOP_START;
+            _c   = c + 3;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 4; cy   = 0;
+            LOOP_START;
+            _c   = c + 4;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 5; cy   = 0;
+            LOOP_START;
+            _c   = c + 5;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 6; cy   = 0;
+            LOOP_START;
+            _c   = c + 6;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 7; cy   = 0;
+            LOOP_START;
+            _c   = c + 7;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 8; cy   = 0;
+            LOOP_START;
+            _c   = c + 8;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+         break;
+      case 10:
+            x = 0; cy   = 0;
+            LOOP_START;
+            _c   = c + 0;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 1; cy   = 0;
+            LOOP_START;
+            _c   = c + 1;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 2; cy   = 0;
+            LOOP_START;
+            _c   = c + 2;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 3; cy   = 0;
+            LOOP_START;
+            _c   = c + 3;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 4; cy   = 0;
+            LOOP_START;
+            _c   = c + 4;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 5; cy   = 0;
+            LOOP_START;
+            _c   = c + 5;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 6; cy   = 0;
+            LOOP_START;
+            _c   = c + 6;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 7; cy   = 0;
+            LOOP_START;
+            _c   = c + 7;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 8; cy   = 0;
+            LOOP_START;
+            _c   = c + 8;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 9; cy   = 0;
+            LOOP_START;
+            _c   = c + 9;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+         break;
+      case 11:
+            x = 0; cy   = 0;
+            LOOP_START;
+            _c   = c + 0;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 1; cy   = 0;
+            LOOP_START;
+            _c   = c + 1;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 2; cy   = 0;
+            LOOP_START;
+            _c   = c + 2;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 3; cy   = 0;
+            LOOP_START;
+            _c   = c + 3;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 4; cy   = 0;
+            LOOP_START;
+            _c   = c + 4;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 5; cy   = 0;
+            LOOP_START;
+            _c   = c + 5;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 6; cy   = 0;
+            LOOP_START;
+            _c   = c + 6;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 7; cy   = 0;
+            LOOP_START;
+            _c   = c + 7;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 8; cy   = 0;
+            LOOP_START;
+            _c   = c + 8;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 9; cy   = 0;
+            LOOP_START;
+            _c   = c + 9;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 10; cy   = 0;
+            LOOP_START;
+            _c   = c + 10;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+         break;
+      case 12:
+            x = 0; cy   = 0;
+            LOOP_START;
+            _c   = c + 0;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 1; cy   = 0;
+            LOOP_START;
+            _c   = c + 1;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 2; cy   = 0;
+            LOOP_START;
+            _c   = c + 2;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 3; cy   = 0;
+            LOOP_START;
+            _c   = c + 3;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 4; cy   = 0;
+            LOOP_START;
+            _c   = c + 4;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 5; cy   = 0;
+            LOOP_START;
+            _c   = c + 5;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 6; cy   = 0;
+            LOOP_START;
+            _c   = c + 6;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 7; cy   = 0;
+            LOOP_START;
+            _c   = c + 7;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 8; cy   = 0;
+            LOOP_START;
+            _c   = c + 8;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 9; cy   = 0;
+            LOOP_START;
+            _c   = c + 9;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 10; cy   = 0;
+            LOOP_START;
+            _c   = c + 10;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 11; cy   = 0;
+            LOOP_START;
+            _c   = c + 11;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+         break;
+      case 13:
+            x = 0; cy   = 0;
+            LOOP_START;
+            _c   = c + 0;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 1; cy   = 0;
+            LOOP_START;
+            _c   = c + 1;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 2; cy   = 0;
+            LOOP_START;
+            _c   = c + 2;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 3; cy   = 0;
+            LOOP_START;
+            _c   = c + 3;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 4; cy   = 0;
+            LOOP_START;
+            _c   = c + 4;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 5; cy   = 0;
+            LOOP_START;
+            _c   = c + 5;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 6; cy   = 0;
+            LOOP_START;
+            _c   = c + 6;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 7; cy   = 0;
+            LOOP_START;
+            _c   = c + 7;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 8; cy   = 0;
+            LOOP_START;
+            _c   = c + 8;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 9; cy   = 0;
+            LOOP_START;
+            _c   = c + 9;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 10; cy   = 0;
+            LOOP_START;
+            _c   = c + 10;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 11; cy   = 0;
+            LOOP_START;
+            _c   = c + 11;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 12; cy   = 0;
+            LOOP_START;
+            _c   = c + 12;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+         break;
+      case 14:
+            x = 0; cy   = 0;
+            LOOP_START;
+            _c   = c + 0;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 1; cy   = 0;
+            LOOP_START;
+            _c   = c + 1;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 2; cy   = 0;
+            LOOP_START;
+            _c   = c + 2;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 3; cy   = 0;
+            LOOP_START;
+            _c   = c + 3;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 4; cy   = 0;
+            LOOP_START;
+            _c   = c + 4;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 5; cy   = 0;
+            LOOP_START;
+            _c   = c + 5;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 6; cy   = 0;
+            LOOP_START;
+            _c   = c + 6;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 7; cy   = 0;
+            LOOP_START;
+            _c   = c + 7;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 8; cy   = 0;
+            LOOP_START;
+            _c   = c + 8;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 9; cy   = 0;
+            LOOP_START;
+            _c   = c + 9;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 10; cy   = 0;
+            LOOP_START;
+            _c   = c + 10;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 11; cy   = 0;
+            LOOP_START;
+            _c   = c + 11;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 12; cy   = 0;
+            LOOP_START;
+            _c   = c + 12;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 13; cy   = 0;
+            LOOP_START;
+            _c   = c + 13;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+         break;
+      case 15:
+            x = 0; cy   = 0;
+            LOOP_START;
+            _c   = c + 0;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 1; cy   = 0;
+            LOOP_START;
+            _c   = c + 1;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 2; cy   = 0;
+            LOOP_START;
+            _c   = c + 2;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 3; cy   = 0;
+            LOOP_START;
+            _c   = c + 3;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 4; cy   = 0;
+            LOOP_START;
+            _c   = c + 4;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 5; cy   = 0;
+            LOOP_START;
+            _c   = c + 5;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 6; cy   = 0;
+            LOOP_START;
+            _c   = c + 6;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 7; cy   = 0;
+            LOOP_START;
+            _c   = c + 7;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 8; cy   = 0;
+            LOOP_START;
+            _c   = c + 8;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 9; cy   = 0;
+            LOOP_START;
+            _c   = c + 9;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 10; cy   = 0;
+            LOOP_START;
+            _c   = c + 10;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 11; cy   = 0;
+            LOOP_START;
+            _c   = c + 11;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 12; cy   = 0;
+            LOOP_START;
+            _c   = c + 12;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 13; cy   = 0;
+            LOOP_START;
+            _c   = c + 13;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 14; cy   = 0;
+            LOOP_START;
+            _c   = c + 14;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+         break;
+      case 16:
+            x = 0; cy   = 0;
+            LOOP_START;
+            _c   = c + 0;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 1; cy   = 0;
+            LOOP_START;
+            _c   = c + 1;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 2; cy   = 0;
+            LOOP_START;
+            _c   = c + 2;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 3; cy   = 0;
+            LOOP_START;
+            _c   = c + 3;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 4; cy   = 0;
+            LOOP_START;
+            _c   = c + 4;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 5; cy   = 0;
+            LOOP_START;
+            _c   = c + 5;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 6; cy   = 0;
+            LOOP_START;
+            _c   = c + 6;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 7; cy   = 0;
+            LOOP_START;
+            _c   = c + 7;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 8; cy   = 0;
+            LOOP_START;
+            _c   = c + 8;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 9; cy   = 0;
+            LOOP_START;
+            _c   = c + 9;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 10; cy   = 0;
+            LOOP_START;
+            _c   = c + 10;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 11; cy   = 0;
+            LOOP_START;
+            _c   = c + 11;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 12; cy   = 0;
+            LOOP_START;
+            _c   = c + 12;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 13; cy   = 0;
+            LOOP_START;
+            _c   = c + 13;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 14; cy   = 0;
+            LOOP_START;
+            _c   = c + 14;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+            x = 15; cy   = 0;
+            LOOP_START;
+            _c   = c + 15;
+            tmpm = m->dp;
+#ifdef INNERMUL8
+            INNERMUL8; _c += 8; tmpm += 8;
+            INNERMUL8; _c += 8; tmpm += 8;
+#else
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+            INNERMUL; ++_c;
+#endif
+            LOOP_END;
+            while (cy) {
+               PROPCARRY;
+               ++_c;
+            }
+         break;
+  }
+  /* now copy out */
+  _c   = c + pa;
+  tmpm = a->dp;
+  for (x = 0; x < pa+1; x++) {
+     *tmpm++ = *_c++;
+  }
+
+  for (; x < oldused; x++)   {
+     *tmpm++ = 0;
+  }
+
+  MONT_FINI;
+
+  a->used = pa+1;
+  fp_clamp(a);
+
+  /* if A >= m then A = A - m */
+  if (fp_cmp_mag (a, m) != FP_LT) {
+    s_fp_sub (a, m, a);
+  }
+}
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_12.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_12.i
new file mode 100644
index 0000000..b25ce5c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_12.i
@@ -0,0 +1,130 @@
+/* fp_mul_comba_12.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_MUL12
+void fp_mul_comba12(fp_int *A, fp_int *B, fp_int *C)
+{
+   fp_digit c0, c1, c2, at[24];
+
+   memcpy(at, A->dp, 12 * sizeof(fp_digit));
+   memcpy(at+12, B->dp, 12 * sizeof(fp_digit));
+   COMBA_START;
+
+   COMBA_CLEAR;
+   /* 0 */
+   MULADD(at[0], at[12]); 
+   COMBA_STORE(C->dp[0]);
+   /* 1 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[13]);    MULADD(at[1], at[12]); 
+   COMBA_STORE(C->dp[1]);
+   /* 2 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[14]);    MULADD(at[1], at[13]);    MULADD(at[2], at[12]); 
+   COMBA_STORE(C->dp[2]);
+   /* 3 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[15]);    MULADD(at[1], at[14]);    MULADD(at[2], at[13]);    MULADD(at[3], at[12]); 
+   COMBA_STORE(C->dp[3]);
+   /* 4 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[16]);    MULADD(at[1], at[15]);    MULADD(at[2], at[14]);    MULADD(at[3], at[13]);    MULADD(at[4], at[12]); 
+   COMBA_STORE(C->dp[4]);
+   /* 5 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[17]);    MULADD(at[1], at[16]);    MULADD(at[2], at[15]);    MULADD(at[3], at[14]);    MULADD(at[4], at[13]);    MULADD(at[5], at[12]); 
+   COMBA_STORE(C->dp[5]);
+   /* 6 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[18]);    MULADD(at[1], at[17]);    MULADD(at[2], at[16]);    MULADD(at[3], at[15]);    MULADD(at[4], at[14]);    MULADD(at[5], at[13]);    MULADD(at[6], at[12]); 
+   COMBA_STORE(C->dp[6]);
+   /* 7 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[19]);    MULADD(at[1], at[18]);    MULADD(at[2], at[17]);    MULADD(at[3], at[16]);    MULADD(at[4], at[15]);    MULADD(at[5], at[14]);    MULADD(at[6], at[13]);    MULADD(at[7], at[12]); 
+   COMBA_STORE(C->dp[7]);
+   /* 8 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[20]);    MULADD(at[1], at[19]);    MULADD(at[2], at[18]);    MULADD(at[3], at[17]);    MULADD(at[4], at[16]);    MULADD(at[5], at[15]);    MULADD(at[6], at[14]);    MULADD(at[7], at[13]);    MULADD(at[8], at[12]); 
+   COMBA_STORE(C->dp[8]);
+   /* 9 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[21]);    MULADD(at[1], at[20]);    MULADD(at[2], at[19]);    MULADD(at[3], at[18]);    MULADD(at[4], at[17]);    MULADD(at[5], at[16]);    MULADD(at[6], at[15]);    MULADD(at[7], at[14]);    MULADD(at[8], at[13]);    MULADD(at[9], at[12]); 
+   COMBA_STORE(C->dp[9]);
+   /* 10 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[22]);    MULADD(at[1], at[21]);    MULADD(at[2], at[20]);    MULADD(at[3], at[19]);    MULADD(at[4], at[18]);    MULADD(at[5], at[17]);    MULADD(at[6], at[16]);    MULADD(at[7], at[15]);    MULADD(at[8], at[14]);    MULADD(at[9], at[13]);    MULADD(at[10], at[12]); 
+   COMBA_STORE(C->dp[10]);
+   /* 11 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[23]);    MULADD(at[1], at[22]);    MULADD(at[2], at[21]);    MULADD(at[3], at[20]);    MULADD(at[4], at[19]);    MULADD(at[5], at[18]);    MULADD(at[6], at[17]);    MULADD(at[7], at[16]);    MULADD(at[8], at[15]);    MULADD(at[9], at[14]);    MULADD(at[10], at[13]);    MULADD(at[11], at[12]); 
+   COMBA_STORE(C->dp[11]);
+   /* 12 */
+   COMBA_FORWARD;
+   MULADD(at[1], at[23]);    MULADD(at[2], at[22]);    MULADD(at[3], at[21]);    MULADD(at[4], at[20]);    MULADD(at[5], at[19]);    MULADD(at[6], at[18]);    MULADD(at[7], at[17]);    MULADD(at[8], at[16]);    MULADD(at[9], at[15]);    MULADD(at[10], at[14]);    MULADD(at[11], at[13]); 
+   COMBA_STORE(C->dp[12]);
+   /* 13 */
+   COMBA_FORWARD;
+   MULADD(at[2], at[23]);    MULADD(at[3], at[22]);    MULADD(at[4], at[21]);    MULADD(at[5], at[20]);    MULADD(at[6], at[19]);    MULADD(at[7], at[18]);    MULADD(at[8], at[17]);    MULADD(at[9], at[16]);    MULADD(at[10], at[15]);    MULADD(at[11], at[14]); 
+   COMBA_STORE(C->dp[13]);
+   /* 14 */
+   COMBA_FORWARD;
+   MULADD(at[3], at[23]);    MULADD(at[4], at[22]);    MULADD(at[5], at[21]);    MULADD(at[6], at[20]);    MULADD(at[7], at[19]);    MULADD(at[8], at[18]);    MULADD(at[9], at[17]);    MULADD(at[10], at[16]);    MULADD(at[11], at[15]); 
+   COMBA_STORE(C->dp[14]);
+   /* 15 */
+   COMBA_FORWARD;
+   MULADD(at[4], at[23]);    MULADD(at[5], at[22]);    MULADD(at[6], at[21]);    MULADD(at[7], at[20]);    MULADD(at[8], at[19]);    MULADD(at[9], at[18]);    MULADD(at[10], at[17]);    MULADD(at[11], at[16]); 
+   COMBA_STORE(C->dp[15]);
+   /* 16 */
+   COMBA_FORWARD;
+   MULADD(at[5], at[23]);    MULADD(at[6], at[22]);    MULADD(at[7], at[21]);    MULADD(at[8], at[20]);    MULADD(at[9], at[19]);    MULADD(at[10], at[18]);    MULADD(at[11], at[17]); 
+   COMBA_STORE(C->dp[16]);
+   /* 17 */
+   COMBA_FORWARD;
+   MULADD(at[6], at[23]);    MULADD(at[7], at[22]);    MULADD(at[8], at[21]);    MULADD(at[9], at[20]);    MULADD(at[10], at[19]);    MULADD(at[11], at[18]); 
+   COMBA_STORE(C->dp[17]);
+   /* 18 */
+   COMBA_FORWARD;
+   MULADD(at[7], at[23]);    MULADD(at[8], at[22]);    MULADD(at[9], at[21]);    MULADD(at[10], at[20]);    MULADD(at[11], at[19]); 
+   COMBA_STORE(C->dp[18]);
+   /* 19 */
+   COMBA_FORWARD;
+   MULADD(at[8], at[23]);    MULADD(at[9], at[22]);    MULADD(at[10], at[21]);    MULADD(at[11], at[20]); 
+   COMBA_STORE(C->dp[19]);
+   /* 20 */
+   COMBA_FORWARD;
+   MULADD(at[9], at[23]);    MULADD(at[10], at[22]);    MULADD(at[11], at[21]); 
+   COMBA_STORE(C->dp[20]);
+   /* 21 */
+   COMBA_FORWARD;
+   MULADD(at[10], at[23]);    MULADD(at[11], at[22]); 
+   COMBA_STORE(C->dp[21]);
+   /* 22 */
+   COMBA_FORWARD;
+   MULADD(at[11], at[23]); 
+   COMBA_STORE(C->dp[22]);
+   COMBA_STORE2(C->dp[23]);
+   C->used = 24;
+   C->sign = A->sign ^ B->sign;
+   fp_clamp(C);
+   COMBA_FINI;
+}
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_17.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_17.i
new file mode 100644
index 0000000..fe12f06
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_17.i
@@ -0,0 +1,170 @@
+/* fp_mul_comba_17.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_MUL17
+void fp_mul_comba17(fp_int *A, fp_int *B, fp_int *C)
+{
+   fp_digit c0, c1, c2, at[34];
+
+   memcpy(at, A->dp, 17 * sizeof(fp_digit));
+   memcpy(at+17, B->dp, 17 * sizeof(fp_digit));
+   COMBA_START;
+
+   COMBA_CLEAR;
+   /* 0 */
+   MULADD(at[0], at[17]); 
+   COMBA_STORE(C->dp[0]);
+   /* 1 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[18]);    MULADD(at[1], at[17]); 
+   COMBA_STORE(C->dp[1]);
+   /* 2 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[19]);    MULADD(at[1], at[18]);    MULADD(at[2], at[17]); 
+   COMBA_STORE(C->dp[2]);
+   /* 3 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[20]);    MULADD(at[1], at[19]);    MULADD(at[2], at[18]);    MULADD(at[3], at[17]); 
+   COMBA_STORE(C->dp[3]);
+   /* 4 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[21]);    MULADD(at[1], at[20]);    MULADD(at[2], at[19]);    MULADD(at[3], at[18]);    MULADD(at[4], at[17]); 
+   COMBA_STORE(C->dp[4]);
+   /* 5 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[22]);    MULADD(at[1], at[21]);    MULADD(at[2], at[20]);    MULADD(at[3], at[19]);    MULADD(at[4], at[18]);    MULADD(at[5], at[17]); 
+   COMBA_STORE(C->dp[5]);
+   /* 6 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[23]);    MULADD(at[1], at[22]);    MULADD(at[2], at[21]);    MULADD(at[3], at[20]);    MULADD(at[4], at[19]);    MULADD(at[5], at[18]);    MULADD(at[6], at[17]); 
+   COMBA_STORE(C->dp[6]);
+   /* 7 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[24]);    MULADD(at[1], at[23]);    MULADD(at[2], at[22]);    MULADD(at[3], at[21]);    MULADD(at[4], at[20]);    MULADD(at[5], at[19]);    MULADD(at[6], at[18]);    MULADD(at[7], at[17]); 
+   COMBA_STORE(C->dp[7]);
+   /* 8 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[25]);    MULADD(at[1], at[24]);    MULADD(at[2], at[23]);    MULADD(at[3], at[22]);    MULADD(at[4], at[21]);    MULADD(at[5], at[20]);    MULADD(at[6], at[19]);    MULADD(at[7], at[18]);    MULADD(at[8], at[17]); 
+   COMBA_STORE(C->dp[8]);
+   /* 9 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[26]);    MULADD(at[1], at[25]);    MULADD(at[2], at[24]);    MULADD(at[3], at[23]);    MULADD(at[4], at[22]);    MULADD(at[5], at[21]);    MULADD(at[6], at[20]);    MULADD(at[7], at[19]);    MULADD(at[8], at[18]);    MULADD(at[9], at[17]); 
+   COMBA_STORE(C->dp[9]);
+   /* 10 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[27]);    MULADD(at[1], at[26]);    MULADD(at[2], at[25]);    MULADD(at[3], at[24]);    MULADD(at[4], at[23]);    MULADD(at[5], at[22]);    MULADD(at[6], at[21]);    MULADD(at[7], at[20]);    MULADD(at[8], at[19]);    MULADD(at[9], at[18]);    MULADD(at[10], at[17]); 
+   COMBA_STORE(C->dp[10]);
+   /* 11 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[28]);    MULADD(at[1], at[27]);    MULADD(at[2], at[26]);    MULADD(at[3], at[25]);    MULADD(at[4], at[24]);    MULADD(at[5], at[23]);    MULADD(at[6], at[22]);    MULADD(at[7], at[21]);    MULADD(at[8], at[20]);    MULADD(at[9], at[19]);    MULADD(at[10], at[18]);    MULADD(at[11], at[17]); 
+   COMBA_STORE(C->dp[11]);
+   /* 12 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[29]);    MULADD(at[1], at[28]);    MULADD(at[2], at[27]);    MULADD(at[3], at[26]);    MULADD(at[4], at[25]);    MULADD(at[5], at[24]);    MULADD(at[6], at[23]);    MULADD(at[7], at[22]);    MULADD(at[8], at[21]);    MULADD(at[9], at[20]);    MULADD(at[10], at[19]);    MULADD(at[11], at[18]);    MULADD(at[12], at[17]); 
+   COMBA_STORE(C->dp[12]);
+   /* 13 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[30]);    MULADD(at[1], at[29]);    MULADD(at[2], at[28]);    MULADD(at[3], at[27]);    MULADD(at[4], at[26]);    MULADD(at[5], at[25]);    MULADD(at[6], at[24]);    MULADD(at[7], at[23]);    MULADD(at[8], at[22]);    MULADD(at[9], at[21]);    MULADD(at[10], at[20]);    MULADD(at[11], at[19]);    MULADD(at[12], at[18]);    MULADD(at[13], at[17]); 
+   COMBA_STORE(C->dp[13]);
+   /* 14 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[31]);    MULADD(at[1], at[30]);    MULADD(at[2], at[29]);    MULADD(at[3], at[28]);    MULADD(at[4], at[27]);    MULADD(at[5], at[26]);    MULADD(at[6], at[25]);    MULADD(at[7], at[24]);    MULADD(at[8], at[23]);    MULADD(at[9], at[22]);    MULADD(at[10], at[21]);    MULADD(at[11], at[20]);    MULADD(at[12], at[19]);    MULADD(at[13], at[18]);    MULADD(at[14], at[17]); 
+   COMBA_STORE(C->dp[14]);
+   /* 15 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[32]);    MULADD(at[1], at[31]);    MULADD(at[2], at[30]);    MULADD(at[3], at[29]);    MULADD(at[4], at[28]);    MULADD(at[5], at[27]);    MULADD(at[6], at[26]);    MULADD(at[7], at[25]);    MULADD(at[8], at[24]);    MULADD(at[9], at[23]);    MULADD(at[10], at[22]);    MULADD(at[11], at[21]);    MULADD(at[12], at[20]);    MULADD(at[13], at[19]);    MULADD(at[14], at[18]);    MULADD(at[15], at[17]); 
+   COMBA_STORE(C->dp[15]);
+   /* 16 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[33]);    MULADD(at[1], at[32]);    MULADD(at[2], at[31]);    MULADD(at[3], at[30]);    MULADD(at[4], at[29]);    MULADD(at[5], at[28]);    MULADD(at[6], at[27]);    MULADD(at[7], at[26]);    MULADD(at[8], at[25]);    MULADD(at[9], at[24]);    MULADD(at[10], at[23]);    MULADD(at[11], at[22]);    MULADD(at[12], at[21]);    MULADD(at[13], at[20]);    MULADD(at[14], at[19]);    MULADD(at[15], at[18]);    MULADD(at[16], at[17]); 
+   COMBA_STORE(C->dp[16]);
+   /* 17 */
+   COMBA_FORWARD;
+   MULADD(at[1], at[33]);    MULADD(at[2], at[32]);    MULADD(at[3], at[31]);    MULADD(at[4], at[30]);    MULADD(at[5], at[29]);    MULADD(at[6], at[28]);    MULADD(at[7], at[27]);    MULADD(at[8], at[26]);    MULADD(at[9], at[25]);    MULADD(at[10], at[24]);    MULADD(at[11], at[23]);    MULADD(at[12], at[22]);    MULADD(at[13], at[21]);    MULADD(at[14], at[20]);    MULADD(at[15], at[19]);    MULADD(at[16], at[18]); 
+   COMBA_STORE(C->dp[17]);
+   /* 18 */
+   COMBA_FORWARD;
+   MULADD(at[2], at[33]);    MULADD(at[3], at[32]);    MULADD(at[4], at[31]);    MULADD(at[5], at[30]);    MULADD(at[6], at[29]);    MULADD(at[7], at[28]);    MULADD(at[8], at[27]);    MULADD(at[9], at[26]);    MULADD(at[10], at[25]);    MULADD(at[11], at[24]);    MULADD(at[12], at[23]);    MULADD(at[13], at[22]);    MULADD(at[14], at[21]);    MULADD(at[15], at[20]);    MULADD(at[16], at[19]); 
+   COMBA_STORE(C->dp[18]);
+   /* 19 */
+   COMBA_FORWARD;
+   MULADD(at[3], at[33]);    MULADD(at[4], at[32]);    MULADD(at[5], at[31]);    MULADD(at[6], at[30]);    MULADD(at[7], at[29]);    MULADD(at[8], at[28]);    MULADD(at[9], at[27]);    MULADD(at[10], at[26]);    MULADD(at[11], at[25]);    MULADD(at[12], at[24]);    MULADD(at[13], at[23]);    MULADD(at[14], at[22]);    MULADD(at[15], at[21]);    MULADD(at[16], at[20]); 
+   COMBA_STORE(C->dp[19]);
+   /* 20 */
+   COMBA_FORWARD;
+   MULADD(at[4], at[33]);    MULADD(at[5], at[32]);    MULADD(at[6], at[31]);    MULADD(at[7], at[30]);    MULADD(at[8], at[29]);    MULADD(at[9], at[28]);    MULADD(at[10], at[27]);    MULADD(at[11], at[26]);    MULADD(at[12], at[25]);    MULADD(at[13], at[24]);    MULADD(at[14], at[23]);    MULADD(at[15], at[22]);    MULADD(at[16], at[21]); 
+   COMBA_STORE(C->dp[20]);
+   /* 21 */
+   COMBA_FORWARD;
+   MULADD(at[5], at[33]);    MULADD(at[6], at[32]);    MULADD(at[7], at[31]);    MULADD(at[8], at[30]);    MULADD(at[9], at[29]);    MULADD(at[10], at[28]);    MULADD(at[11], at[27]);    MULADD(at[12], at[26]);    MULADD(at[13], at[25]);    MULADD(at[14], at[24]);    MULADD(at[15], at[23]);    MULADD(at[16], at[22]); 
+   COMBA_STORE(C->dp[21]);
+   /* 22 */
+   COMBA_FORWARD;
+   MULADD(at[6], at[33]);    MULADD(at[7], at[32]);    MULADD(at[8], at[31]);    MULADD(at[9], at[30]);    MULADD(at[10], at[29]);    MULADD(at[11], at[28]);    MULADD(at[12], at[27]);    MULADD(at[13], at[26]);    MULADD(at[14], at[25]);    MULADD(at[15], at[24]);    MULADD(at[16], at[23]); 
+   COMBA_STORE(C->dp[22]);
+   /* 23 */
+   COMBA_FORWARD;
+   MULADD(at[7], at[33]);    MULADD(at[8], at[32]);    MULADD(at[9], at[31]);    MULADD(at[10], at[30]);    MULADD(at[11], at[29]);    MULADD(at[12], at[28]);    MULADD(at[13], at[27]);    MULADD(at[14], at[26]);    MULADD(at[15], at[25]);    MULADD(at[16], at[24]); 
+   COMBA_STORE(C->dp[23]);
+   /* 24 */
+   COMBA_FORWARD;
+   MULADD(at[8], at[33]);    MULADD(at[9], at[32]);    MULADD(at[10], at[31]);    MULADD(at[11], at[30]);    MULADD(at[12], at[29]);    MULADD(at[13], at[28]);    MULADD(at[14], at[27]);    MULADD(at[15], at[26]);    MULADD(at[16], at[25]); 
+   COMBA_STORE(C->dp[24]);
+   /* 25 */
+   COMBA_FORWARD;
+   MULADD(at[9], at[33]);    MULADD(at[10], at[32]);    MULADD(at[11], at[31]);    MULADD(at[12], at[30]);    MULADD(at[13], at[29]);    MULADD(at[14], at[28]);    MULADD(at[15], at[27]);    MULADD(at[16], at[26]); 
+   COMBA_STORE(C->dp[25]);
+   /* 26 */
+   COMBA_FORWARD;
+   MULADD(at[10], at[33]);    MULADD(at[11], at[32]);    MULADD(at[12], at[31]);    MULADD(at[13], at[30]);    MULADD(at[14], at[29]);    MULADD(at[15], at[28]);    MULADD(at[16], at[27]); 
+   COMBA_STORE(C->dp[26]);
+   /* 27 */
+   COMBA_FORWARD;
+   MULADD(at[11], at[33]);    MULADD(at[12], at[32]);    MULADD(at[13], at[31]);    MULADD(at[14], at[30]);    MULADD(at[15], at[29]);    MULADD(at[16], at[28]); 
+   COMBA_STORE(C->dp[27]);
+   /* 28 */
+   COMBA_FORWARD;
+   MULADD(at[12], at[33]);    MULADD(at[13], at[32]);    MULADD(at[14], at[31]);    MULADD(at[15], at[30]);    MULADD(at[16], at[29]); 
+   COMBA_STORE(C->dp[28]);
+   /* 29 */
+   COMBA_FORWARD;
+   MULADD(at[13], at[33]);    MULADD(at[14], at[32]);    MULADD(at[15], at[31]);    MULADD(at[16], at[30]); 
+   COMBA_STORE(C->dp[29]);
+   /* 30 */
+   COMBA_FORWARD;
+   MULADD(at[14], at[33]);    MULADD(at[15], at[32]);    MULADD(at[16], at[31]); 
+   COMBA_STORE(C->dp[30]);
+   /* 31 */
+   COMBA_FORWARD;
+   MULADD(at[15], at[33]);    MULADD(at[16], at[32]); 
+   COMBA_STORE(C->dp[31]);
+   /* 32 */
+   COMBA_FORWARD;
+   MULADD(at[16], at[33]); 
+   COMBA_STORE(C->dp[32]);
+   COMBA_STORE2(C->dp[33]);
+   C->used = 34;
+   C->sign = A->sign ^ B->sign;
+   fp_clamp(C);
+   COMBA_FINI;
+}
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_20.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_20.i
new file mode 100644
index 0000000..cd07e5d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_20.i
@@ -0,0 +1,193 @@
+/* fp_mul_comba_20.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef TFM_MUL20
+void fp_mul_comba20(fp_int *A, fp_int *B, fp_int *C)
+{
+   fp_digit c0, c1, c2, at[40];
+   
+   memcpy(at, A->dp, 20 * sizeof(fp_digit));
+   memcpy(at+20, B->dp, 20 * sizeof(fp_digit));
+   COMBA_START;
+
+   COMBA_CLEAR;
+   /* 0 */
+   MULADD(at[0], at[20]); 
+   COMBA_STORE(C->dp[0]);
+   /* 1 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[21]);    MULADD(at[1], at[20]); 
+   COMBA_STORE(C->dp[1]);
+   /* 2 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[22]);    MULADD(at[1], at[21]);    MULADD(at[2], at[20]); 
+   COMBA_STORE(C->dp[2]);
+   /* 3 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[23]);    MULADD(at[1], at[22]);    MULADD(at[2], at[21]);    MULADD(at[3], at[20]); 
+   COMBA_STORE(C->dp[3]);
+   /* 4 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[24]);    MULADD(at[1], at[23]);    MULADD(at[2], at[22]);    MULADD(at[3], at[21]);    MULADD(at[4], at[20]); 
+   COMBA_STORE(C->dp[4]);
+   /* 5 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[25]);    MULADD(at[1], at[24]);    MULADD(at[2], at[23]);    MULADD(at[3], at[22]);    MULADD(at[4], at[21]);    MULADD(at[5], at[20]); 
+   COMBA_STORE(C->dp[5]);
+   /* 6 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[26]);    MULADD(at[1], at[25]);    MULADD(at[2], at[24]);    MULADD(at[3], at[23]);    MULADD(at[4], at[22]);    MULADD(at[5], at[21]);    MULADD(at[6], at[20]); 
+   COMBA_STORE(C->dp[6]);
+   /* 7 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[27]);    MULADD(at[1], at[26]);    MULADD(at[2], at[25]);    MULADD(at[3], at[24]);    MULADD(at[4], at[23]);    MULADD(at[5], at[22]);    MULADD(at[6], at[21]);    MULADD(at[7], at[20]); 
+   COMBA_STORE(C->dp[7]);
+   /* 8 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[28]);    MULADD(at[1], at[27]);    MULADD(at[2], at[26]);    MULADD(at[3], at[25]);    MULADD(at[4], at[24]);    MULADD(at[5], at[23]);    MULADD(at[6], at[22]);    MULADD(at[7], at[21]);    MULADD(at[8], at[20]); 
+   COMBA_STORE(C->dp[8]);
+   /* 9 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[29]);    MULADD(at[1], at[28]);    MULADD(at[2], at[27]);    MULADD(at[3], at[26]);    MULADD(at[4], at[25]);    MULADD(at[5], at[24]);    MULADD(at[6], at[23]);    MULADD(at[7], at[22]);    MULADD(at[8], at[21]);    MULADD(at[9], at[20]); 
+   COMBA_STORE(C->dp[9]);
+   /* 10 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[30]);    MULADD(at[1], at[29]);    MULADD(at[2], at[28]);    MULADD(at[3], at[27]);    MULADD(at[4], at[26]);    MULADD(at[5], at[25]);    MULADD(at[6], at[24]);    MULADD(at[7], at[23]);    MULADD(at[8], at[22]);    MULADD(at[9], at[21]);    MULADD(at[10], at[20]); 
+   COMBA_STORE(C->dp[10]);
+   /* 11 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[31]);    MULADD(at[1], at[30]);    MULADD(at[2], at[29]);    MULADD(at[3], at[28]);    MULADD(at[4], at[27]);    MULADD(at[5], at[26]);    MULADD(at[6], at[25]);    MULADD(at[7], at[24]);    MULADD(at[8], at[23]);    MULADD(at[9], at[22]);    MULADD(at[10], at[21]);    MULADD(at[11], at[20]); 
+   COMBA_STORE(C->dp[11]);
+   /* 12 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[32]);    MULADD(at[1], at[31]);    MULADD(at[2], at[30]);    MULADD(at[3], at[29]);    MULADD(at[4], at[28]);    MULADD(at[5], at[27]);    MULADD(at[6], at[26]);    MULADD(at[7], at[25]);    MULADD(at[8], at[24]);    MULADD(at[9], at[23]);    MULADD(at[10], at[22]);    MULADD(at[11], at[21]);    MULADD(at[12], at[20]); 
+   COMBA_STORE(C->dp[12]);
+   /* 13 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[33]);    MULADD(at[1], at[32]);    MULADD(at[2], at[31]);    MULADD(at[3], at[30]);    MULADD(at[4], at[29]);    MULADD(at[5], at[28]);    MULADD(at[6], at[27]);    MULADD(at[7], at[26]);    MULADD(at[8], at[25]);    MULADD(at[9], at[24]);    MULADD(at[10], at[23]);    MULADD(at[11], at[22]);    MULADD(at[12], at[21]);    MULADD(at[13], at[20]); 
+   COMBA_STORE(C->dp[13]);
+   /* 14 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[34]);    MULADD(at[1], at[33]);    MULADD(at[2], at[32]);    MULADD(at[3], at[31]);    MULADD(at[4], at[30]);    MULADD(at[5], at[29]);    MULADD(at[6], at[28]);    MULADD(at[7], at[27]);    MULADD(at[8], at[26]);    MULADD(at[9], at[25]);    MULADD(at[10], at[24]);    MULADD(at[11], at[23]);    MULADD(at[12], at[22]);    MULADD(at[13], at[21]);    MULADD(at[14], at[20]); 
+   COMBA_STORE(C->dp[14]);
+   /* 15 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[35]);    MULADD(at[1], at[34]);    MULADD(at[2], at[33]);    MULADD(at[3], at[32]);    MULADD(at[4], at[31]);    MULADD(at[5], at[30]);    MULADD(at[6], at[29]);    MULADD(at[7], at[28]);    MULADD(at[8], at[27]);    MULADD(at[9], at[26]);    MULADD(at[10], at[25]);    MULADD(at[11], at[24]);    MULADD(at[12], at[23]);    MULADD(at[13], at[22]);    MULADD(at[14], at[21]);    MULADD(at[15], at[20]); 
+   COMBA_STORE(C->dp[15]);
+   /* 16 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[36]);    MULADD(at[1], at[35]);    MULADD(at[2], at[34]);    MULADD(at[3], at[33]);    MULADD(at[4], at[32]);    MULADD(at[5], at[31]);    MULADD(at[6], at[30]);    MULADD(at[7], at[29]);    MULADD(at[8], at[28]);    MULADD(at[9], at[27]);    MULADD(at[10], at[26]);    MULADD(at[11], at[25]);    MULADD(at[12], at[24]);    MULADD(at[13], at[23]);    MULADD(at[14], at[22]);    MULADD(at[15], at[21]);    MULADD(at[16], at[20]); 
+   COMBA_STORE(C->dp[16]);
+   /* 17 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[37]);    MULADD(at[1], at[36]);    MULADD(at[2], at[35]);    MULADD(at[3], at[34]);    MULADD(at[4], at[33]);    MULADD(at[5], at[32]);    MULADD(at[6], at[31]);    MULADD(at[7], at[30]);    MULADD(at[8], at[29]);    MULADD(at[9], at[28]);    MULADD(at[10], at[27]);    MULADD(at[11], at[26]);    MULADD(at[12], at[25]);    MULADD(at[13], at[24]);    MULADD(at[14], at[23]);    MULADD(at[15], at[22]);    MULADD(at[16], at[21]);    MULADD(at[17], at[20]); 
+   COMBA_STORE(C->dp[17]);
+   /* 18 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[38]);    MULADD(at[1], at[37]);    MULADD(at[2], at[36]);    MULADD(at[3], at[35]);    MULADD(at[4], at[34]);    MULADD(at[5], at[33]);    MULADD(at[6], at[32]);    MULADD(at[7], at[31]);    MULADD(at[8], at[30]);    MULADD(at[9], at[29]);    MULADD(at[10], at[28]);    MULADD(at[11], at[27]);    MULADD(at[12], at[26]);    MULADD(at[13], at[25]);    MULADD(at[14], at[24]);    MULADD(at[15], at[23]);    MULADD(at[16], at[22]);    MULADD(at[17], at[21]);    MULADD(at[18], at[20]); 
+   COMBA_STORE(C->dp[18]);
+   /* 19 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[39]);    MULADD(at[1], at[38]);    MULADD(at[2], at[37]);    MULADD(at[3], at[36]);    MULADD(at[4], at[35]);    MULADD(at[5], at[34]);    MULADD(at[6], at[33]);    MULADD(at[7], at[32]);    MULADD(at[8], at[31]);    MULADD(at[9], at[30]);    MULADD(at[10], at[29]);    MULADD(at[11], at[28]);    MULADD(at[12], at[27]);    MULADD(at[13], at[26]);    MULADD(at[14], at[25]);    MULADD(at[15], at[24]);    MULADD(at[16], at[23]);    MULADD(at[17], at[22]);    MULADD(at[18], at[21]);    MULADD(at[19], at[20]); 
+   COMBA_STORE(C->dp[19]);
+   /* 20 */
+   COMBA_FORWARD;
+   MULADD(at[1], at[39]);    MULADD(at[2], at[38]);    MULADD(at[3], at[37]);    MULADD(at[4], at[36]);    MULADD(at[5], at[35]);    MULADD(at[6], at[34]);    MULADD(at[7], at[33]);    MULADD(at[8], at[32]);    MULADD(at[9], at[31]);    MULADD(at[10], at[30]);    MULADD(at[11], at[29]);    MULADD(at[12], at[28]);    MULADD(at[13], at[27]);    MULADD(at[14], at[26]);    MULADD(at[15], at[25]);    MULADD(at[16], at[24]);    MULADD(at[17], at[23]);    MULADD(at[18], at[22]);    MULADD(at[19], at[21]); 
+   COMBA_STORE(C->dp[20]);
+   /* 21 */
+   COMBA_FORWARD;
+   MULADD(at[2], at[39]);    MULADD(at[3], at[38]);    MULADD(at[4], at[37]);    MULADD(at[5], at[36]);    MULADD(at[6], at[35]);    MULADD(at[7], at[34]);    MULADD(at[8], at[33]);    MULADD(at[9], at[32]);    MULADD(at[10], at[31]);    MULADD(at[11], at[30]);    MULADD(at[12], at[29]);    MULADD(at[13], at[28]);    MULADD(at[14], at[27]);    MULADD(at[15], at[26]);    MULADD(at[16], at[25]);    MULADD(at[17], at[24]);    MULADD(at[18], at[23]);    MULADD(at[19], at[22]); 
+   COMBA_STORE(C->dp[21]);
+   /* 22 */
+   COMBA_FORWARD;
+   MULADD(at[3], at[39]);    MULADD(at[4], at[38]);    MULADD(at[5], at[37]);    MULADD(at[6], at[36]);    MULADD(at[7], at[35]);    MULADD(at[8], at[34]);    MULADD(at[9], at[33]);    MULADD(at[10], at[32]);    MULADD(at[11], at[31]);    MULADD(at[12], at[30]);    MULADD(at[13], at[29]);    MULADD(at[14], at[28]);    MULADD(at[15], at[27]);    MULADD(at[16], at[26]);    MULADD(at[17], at[25]);    MULADD(at[18], at[24]);    MULADD(at[19], at[23]); 
+   COMBA_STORE(C->dp[22]);
+   /* 23 */
+   COMBA_FORWARD;
+   MULADD(at[4], at[39]);    MULADD(at[5], at[38]);    MULADD(at[6], at[37]);    MULADD(at[7], at[36]);    MULADD(at[8], at[35]);    MULADD(at[9], at[34]);    MULADD(at[10], at[33]);    MULADD(at[11], at[32]);    MULADD(at[12], at[31]);    MULADD(at[13], at[30]);    MULADD(at[14], at[29]);    MULADD(at[15], at[28]);    MULADD(at[16], at[27]);    MULADD(at[17], at[26]);    MULADD(at[18], at[25]);    MULADD(at[19], at[24]); 
+   COMBA_STORE(C->dp[23]);
+   /* 24 */
+   COMBA_FORWARD;
+   MULADD(at[5], at[39]);    MULADD(at[6], at[38]);    MULADD(at[7], at[37]);    MULADD(at[8], at[36]);    MULADD(at[9], at[35]);    MULADD(at[10], at[34]);    MULADD(at[11], at[33]);    MULADD(at[12], at[32]);    MULADD(at[13], at[31]);    MULADD(at[14], at[30]);    MULADD(at[15], at[29]);    MULADD(at[16], at[28]);    MULADD(at[17], at[27]);    MULADD(at[18], at[26]);    MULADD(at[19], at[25]); 
+   COMBA_STORE(C->dp[24]);
+   /* 25 */
+   COMBA_FORWARD;
+   MULADD(at[6], at[39]);    MULADD(at[7], at[38]);    MULADD(at[8], at[37]);    MULADD(at[9], at[36]);    MULADD(at[10], at[35]);    MULADD(at[11], at[34]);    MULADD(at[12], at[33]);    MULADD(at[13], at[32]);    MULADD(at[14], at[31]);    MULADD(at[15], at[30]);    MULADD(at[16], at[29]);    MULADD(at[17], at[28]);    MULADD(at[18], at[27]);    MULADD(at[19], at[26]); 
+   COMBA_STORE(C->dp[25]);
+   /* 26 */
+   COMBA_FORWARD;
+   MULADD(at[7], at[39]);    MULADD(at[8], at[38]);    MULADD(at[9], at[37]);    MULADD(at[10], at[36]);    MULADD(at[11], at[35]);    MULADD(at[12], at[34]);    MULADD(at[13], at[33]);    MULADD(at[14], at[32]);    MULADD(at[15], at[31]);    MULADD(at[16], at[30]);    MULADD(at[17], at[29]);    MULADD(at[18], at[28]);    MULADD(at[19], at[27]); 
+   COMBA_STORE(C->dp[26]);
+   /* 27 */
+   COMBA_FORWARD;
+   MULADD(at[8], at[39]);    MULADD(at[9], at[38]);    MULADD(at[10], at[37]);    MULADD(at[11], at[36]);    MULADD(at[12], at[35]);    MULADD(at[13], at[34]);    MULADD(at[14], at[33]);    MULADD(at[15], at[32]);    MULADD(at[16], at[31]);    MULADD(at[17], at[30]);    MULADD(at[18], at[29]);    MULADD(at[19], at[28]); 
+   COMBA_STORE(C->dp[27]);
+   /* 28 */
+   COMBA_FORWARD;
+   MULADD(at[9], at[39]);    MULADD(at[10], at[38]);    MULADD(at[11], at[37]);    MULADD(at[12], at[36]);    MULADD(at[13], at[35]);    MULADD(at[14], at[34]);    MULADD(at[15], at[33]);    MULADD(at[16], at[32]);    MULADD(at[17], at[31]);    MULADD(at[18], at[30]);    MULADD(at[19], at[29]); 
+   COMBA_STORE(C->dp[28]);
+   /* 29 */
+   COMBA_FORWARD;
+   MULADD(at[10], at[39]);    MULADD(at[11], at[38]);    MULADD(at[12], at[37]);    MULADD(at[13], at[36]);    MULADD(at[14], at[35]);    MULADD(at[15], at[34]);    MULADD(at[16], at[33]);    MULADD(at[17], at[32]);    MULADD(at[18], at[31]);    MULADD(at[19], at[30]); 
+   COMBA_STORE(C->dp[29]);
+   /* 30 */
+   COMBA_FORWARD;
+   MULADD(at[11], at[39]);    MULADD(at[12], at[38]);    MULADD(at[13], at[37]);    MULADD(at[14], at[36]);    MULADD(at[15], at[35]);    MULADD(at[16], at[34]);    MULADD(at[17], at[33]);    MULADD(at[18], at[32]);    MULADD(at[19], at[31]); 
+   COMBA_STORE(C->dp[30]);
+   /* 31 */
+   COMBA_FORWARD;
+   MULADD(at[12], at[39]);    MULADD(at[13], at[38]);    MULADD(at[14], at[37]);    MULADD(at[15], at[36]);    MULADD(at[16], at[35]);    MULADD(at[17], at[34]);    MULADD(at[18], at[33]);    MULADD(at[19], at[32]); 
+   COMBA_STORE(C->dp[31]);
+   /* 32 */
+   COMBA_FORWARD;
+   MULADD(at[13], at[39]);    MULADD(at[14], at[38]);    MULADD(at[15], at[37]);    MULADD(at[16], at[36]);    MULADD(at[17], at[35]);    MULADD(at[18], at[34]);    MULADD(at[19], at[33]); 
+   COMBA_STORE(C->dp[32]);
+   /* 33 */
+   COMBA_FORWARD;
+   MULADD(at[14], at[39]);    MULADD(at[15], at[38]);    MULADD(at[16], at[37]);    MULADD(at[17], at[36]);    MULADD(at[18], at[35]);    MULADD(at[19], at[34]); 
+   COMBA_STORE(C->dp[33]);
+   /* 34 */
+   COMBA_FORWARD;
+   MULADD(at[15], at[39]);    MULADD(at[16], at[38]);    MULADD(at[17], at[37]);    MULADD(at[18], at[36]);    MULADD(at[19], at[35]); 
+   COMBA_STORE(C->dp[34]);
+   /* 35 */
+   COMBA_FORWARD;
+   MULADD(at[16], at[39]);    MULADD(at[17], at[38]);    MULADD(at[18], at[37]);    MULADD(at[19], at[36]); 
+   COMBA_STORE(C->dp[35]);
+   /* 36 */
+   COMBA_FORWARD;
+   MULADD(at[17], at[39]);    MULADD(at[18], at[38]);    MULADD(at[19], at[37]); 
+   COMBA_STORE(C->dp[36]);
+   /* 37 */
+   COMBA_FORWARD;
+   MULADD(at[18], at[39]);    MULADD(at[19], at[38]); 
+   COMBA_STORE(C->dp[37]);
+   /* 38 */
+   COMBA_FORWARD;
+   MULADD(at[19], at[39]); 
+   COMBA_STORE(C->dp[38]);
+   COMBA_STORE2(C->dp[39]);
+   C->used = 40;
+   C->sign = A->sign ^ B->sign;
+   fp_clamp(C);
+   COMBA_FINI;
+}
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_24.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_24.i
new file mode 100644
index 0000000..2576d27
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_24.i
@@ -0,0 +1,226 @@
+/* fp_mul_comba_24.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_MUL24
+void fp_mul_comba24(fp_int *A, fp_int *B, fp_int *C)
+{
+   fp_digit c0, c1, c2, at[48];
+
+   memcpy(at, A->dp, 24 * sizeof(fp_digit));
+   memcpy(at+24, B->dp, 24 * sizeof(fp_digit));
+   COMBA_START;
+
+   COMBA_CLEAR;
+   /* 0 */
+   MULADD(at[0], at[24]); 
+   COMBA_STORE(C->dp[0]);
+   /* 1 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[25]);    MULADD(at[1], at[24]); 
+   COMBA_STORE(C->dp[1]);
+   /* 2 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[26]);    MULADD(at[1], at[25]);    MULADD(at[2], at[24]); 
+   COMBA_STORE(C->dp[2]);
+   /* 3 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[27]);    MULADD(at[1], at[26]);    MULADD(at[2], at[25]);    MULADD(at[3], at[24]); 
+   COMBA_STORE(C->dp[3]);
+   /* 4 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[28]);    MULADD(at[1], at[27]);    MULADD(at[2], at[26]);    MULADD(at[3], at[25]);    MULADD(at[4], at[24]); 
+   COMBA_STORE(C->dp[4]);
+   /* 5 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[29]);    MULADD(at[1], at[28]);    MULADD(at[2], at[27]);    MULADD(at[3], at[26]);    MULADD(at[4], at[25]);    MULADD(at[5], at[24]); 
+   COMBA_STORE(C->dp[5]);
+   /* 6 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[30]);    MULADD(at[1], at[29]);    MULADD(at[2], at[28]);    MULADD(at[3], at[27]);    MULADD(at[4], at[26]);    MULADD(at[5], at[25]);    MULADD(at[6], at[24]); 
+   COMBA_STORE(C->dp[6]);
+   /* 7 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[31]);    MULADD(at[1], at[30]);    MULADD(at[2], at[29]);    MULADD(at[3], at[28]);    MULADD(at[4], at[27]);    MULADD(at[5], at[26]);    MULADD(at[6], at[25]);    MULADD(at[7], at[24]); 
+   COMBA_STORE(C->dp[7]);
+   /* 8 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[32]);    MULADD(at[1], at[31]);    MULADD(at[2], at[30]);    MULADD(at[3], at[29]);    MULADD(at[4], at[28]);    MULADD(at[5], at[27]);    MULADD(at[6], at[26]);    MULADD(at[7], at[25]);    MULADD(at[8], at[24]); 
+   COMBA_STORE(C->dp[8]);
+   /* 9 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[33]);    MULADD(at[1], at[32]);    MULADD(at[2], at[31]);    MULADD(at[3], at[30]);    MULADD(at[4], at[29]);    MULADD(at[5], at[28]);    MULADD(at[6], at[27]);    MULADD(at[7], at[26]);    MULADD(at[8], at[25]);    MULADD(at[9], at[24]); 
+   COMBA_STORE(C->dp[9]);
+   /* 10 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[34]);    MULADD(at[1], at[33]);    MULADD(at[2], at[32]);    MULADD(at[3], at[31]);    MULADD(at[4], at[30]);    MULADD(at[5], at[29]);    MULADD(at[6], at[28]);    MULADD(at[7], at[27]);    MULADD(at[8], at[26]);    MULADD(at[9], at[25]);    MULADD(at[10], at[24]); 
+   COMBA_STORE(C->dp[10]);
+   /* 11 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[35]);    MULADD(at[1], at[34]);    MULADD(at[2], at[33]);    MULADD(at[3], at[32]);    MULADD(at[4], at[31]);    MULADD(at[5], at[30]);    MULADD(at[6], at[29]);    MULADD(at[7], at[28]);    MULADD(at[8], at[27]);    MULADD(at[9], at[26]);    MULADD(at[10], at[25]);    MULADD(at[11], at[24]); 
+   COMBA_STORE(C->dp[11]);
+   /* 12 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[36]);    MULADD(at[1], at[35]);    MULADD(at[2], at[34]);    MULADD(at[3], at[33]);    MULADD(at[4], at[32]);    MULADD(at[5], at[31]);    MULADD(at[6], at[30]);    MULADD(at[7], at[29]);    MULADD(at[8], at[28]);    MULADD(at[9], at[27]);    MULADD(at[10], at[26]);    MULADD(at[11], at[25]);    MULADD(at[12], at[24]); 
+   COMBA_STORE(C->dp[12]);
+   /* 13 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[37]);    MULADD(at[1], at[36]);    MULADD(at[2], at[35]);    MULADD(at[3], at[34]);    MULADD(at[4], at[33]);    MULADD(at[5], at[32]);    MULADD(at[6], at[31]);    MULADD(at[7], at[30]);    MULADD(at[8], at[29]);    MULADD(at[9], at[28]);    MULADD(at[10], at[27]);    MULADD(at[11], at[26]);    MULADD(at[12], at[25]);    MULADD(at[13], at[24]); 
+   COMBA_STORE(C->dp[13]);
+   /* 14 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[38]);    MULADD(at[1], at[37]);    MULADD(at[2], at[36]);    MULADD(at[3], at[35]);    MULADD(at[4], at[34]);    MULADD(at[5], at[33]);    MULADD(at[6], at[32]);    MULADD(at[7], at[31]);    MULADD(at[8], at[30]);    MULADD(at[9], at[29]);    MULADD(at[10], at[28]);    MULADD(at[11], at[27]);    MULADD(at[12], at[26]);    MULADD(at[13], at[25]);    MULADD(at[14], at[24]); 
+   COMBA_STORE(C->dp[14]);
+   /* 15 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[39]);    MULADD(at[1], at[38]);    MULADD(at[2], at[37]);    MULADD(at[3], at[36]);    MULADD(at[4], at[35]);    MULADD(at[5], at[34]);    MULADD(at[6], at[33]);    MULADD(at[7], at[32]);    MULADD(at[8], at[31]);    MULADD(at[9], at[30]);    MULADD(at[10], at[29]);    MULADD(at[11], at[28]);    MULADD(at[12], at[27]);    MULADD(at[13], at[26]);    MULADD(at[14], at[25]);    MULADD(at[15], at[24]); 
+   COMBA_STORE(C->dp[15]);
+   /* 16 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[40]);    MULADD(at[1], at[39]);    MULADD(at[2], at[38]);    MULADD(at[3], at[37]);    MULADD(at[4], at[36]);    MULADD(at[5], at[35]);    MULADD(at[6], at[34]);    MULADD(at[7], at[33]);    MULADD(at[8], at[32]);    MULADD(at[9], at[31]);    MULADD(at[10], at[30]);    MULADD(at[11], at[29]);    MULADD(at[12], at[28]);    MULADD(at[13], at[27]);    MULADD(at[14], at[26]);    MULADD(at[15], at[25]);    MULADD(at[16], at[24]); 
+   COMBA_STORE(C->dp[16]);
+   /* 17 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[41]);    MULADD(at[1], at[40]);    MULADD(at[2], at[39]);    MULADD(at[3], at[38]);    MULADD(at[4], at[37]);    MULADD(at[5], at[36]);    MULADD(at[6], at[35]);    MULADD(at[7], at[34]);    MULADD(at[8], at[33]);    MULADD(at[9], at[32]);    MULADD(at[10], at[31]);    MULADD(at[11], at[30]);    MULADD(at[12], at[29]);    MULADD(at[13], at[28]);    MULADD(at[14], at[27]);    MULADD(at[15], at[26]);    MULADD(at[16], at[25]);    MULADD(at[17], at[24]); 
+   COMBA_STORE(C->dp[17]);
+   /* 18 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[42]);    MULADD(at[1], at[41]);    MULADD(at[2], at[40]);    MULADD(at[3], at[39]);    MULADD(at[4], at[38]);    MULADD(at[5], at[37]);    MULADD(at[6], at[36]);    MULADD(at[7], at[35]);    MULADD(at[8], at[34]);    MULADD(at[9], at[33]);    MULADD(at[10], at[32]);    MULADD(at[11], at[31]);    MULADD(at[12], at[30]);    MULADD(at[13], at[29]);    MULADD(at[14], at[28]);    MULADD(at[15], at[27]);    MULADD(at[16], at[26]);    MULADD(at[17], at[25]);    MULADD(at[18], at[24]); 
+   COMBA_STORE(C->dp[18]);
+   /* 19 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[43]);    MULADD(at[1], at[42]);    MULADD(at[2], at[41]);    MULADD(at[3], at[40]);    MULADD(at[4], at[39]);    MULADD(at[5], at[38]);    MULADD(at[6], at[37]);    MULADD(at[7], at[36]);    MULADD(at[8], at[35]);    MULADD(at[9], at[34]);    MULADD(at[10], at[33]);    MULADD(at[11], at[32]);    MULADD(at[12], at[31]);    MULADD(at[13], at[30]);    MULADD(at[14], at[29]);    MULADD(at[15], at[28]);    MULADD(at[16], at[27]);    MULADD(at[17], at[26]);    MULADD(at[18], at[25]);    MULADD(at[19], at[24]); 
+   COMBA_STORE(C->dp[19]);
+   /* 20 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[44]);    MULADD(at[1], at[43]);    MULADD(at[2], at[42]);    MULADD(at[3], at[41]);    MULADD(at[4], at[40]);    MULADD(at[5], at[39]);    MULADD(at[6], at[38]);    MULADD(at[7], at[37]);    MULADD(at[8], at[36]);    MULADD(at[9], at[35]);    MULADD(at[10], at[34]);    MULADD(at[11], at[33]);    MULADD(at[12], at[32]);    MULADD(at[13], at[31]);    MULADD(at[14], at[30]);    MULADD(at[15], at[29]);    MULADD(at[16], at[28]);    MULADD(at[17], at[27]);    MULADD(at[18], at[26]);    MULADD(at[19], at[25]);    MULADD(at[20], at[24]); 
+   COMBA_STORE(C->dp[20]);
+   /* 21 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[45]);    MULADD(at[1], at[44]);    MULADD(at[2], at[43]);    MULADD(at[3], at[42]);    MULADD(at[4], at[41]);    MULADD(at[5], at[40]);    MULADD(at[6], at[39]);    MULADD(at[7], at[38]);    MULADD(at[8], at[37]);    MULADD(at[9], at[36]);    MULADD(at[10], at[35]);    MULADD(at[11], at[34]);    MULADD(at[12], at[33]);    MULADD(at[13], at[32]);    MULADD(at[14], at[31]);    MULADD(at[15], at[30]);    MULADD(at[16], at[29]);    MULADD(at[17], at[28]);    MULADD(at[18], at[27]);    MULADD(at[19], at[26]);    MULADD(at[20], at[25]);    MULADD(at[21], at[24]); 
+   COMBA_STORE(C->dp[21]);
+   /* 22 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[46]);    MULADD(at[1], at[45]);    MULADD(at[2], at[44]);    MULADD(at[3], at[43]);    MULADD(at[4], at[42]);    MULADD(at[5], at[41]);    MULADD(at[6], at[40]);    MULADD(at[7], at[39]);    MULADD(at[8], at[38]);    MULADD(at[9], at[37]);    MULADD(at[10], at[36]);    MULADD(at[11], at[35]);    MULADD(at[12], at[34]);    MULADD(at[13], at[33]);    MULADD(at[14], at[32]);    MULADD(at[15], at[31]);    MULADD(at[16], at[30]);    MULADD(at[17], at[29]);    MULADD(at[18], at[28]);    MULADD(at[19], at[27]);    MULADD(at[20], at[26]);    MULADD(at[21], at[25]);    MULADD(at[22], at[24]); 
+   COMBA_STORE(C->dp[22]);
+   /* 23 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[47]);    MULADD(at[1], at[46]);    MULADD(at[2], at[45]);    MULADD(at[3], at[44]);    MULADD(at[4], at[43]);    MULADD(at[5], at[42]);    MULADD(at[6], at[41]);    MULADD(at[7], at[40]);    MULADD(at[8], at[39]);    MULADD(at[9], at[38]);    MULADD(at[10], at[37]);    MULADD(at[11], at[36]);    MULADD(at[12], at[35]);    MULADD(at[13], at[34]);    MULADD(at[14], at[33]);    MULADD(at[15], at[32]);    MULADD(at[16], at[31]);    MULADD(at[17], at[30]);    MULADD(at[18], at[29]);    MULADD(at[19], at[28]);    MULADD(at[20], at[27]);    MULADD(at[21], at[26]);    MULADD(at[22], at[25]);    MULADD(at[23], at[24]); 
+   COMBA_STORE(C->dp[23]);
+   /* 24 */
+   COMBA_FORWARD;
+   MULADD(at[1], at[47]);    MULADD(at[2], at[46]);    MULADD(at[3], at[45]);    MULADD(at[4], at[44]);    MULADD(at[5], at[43]);    MULADD(at[6], at[42]);    MULADD(at[7], at[41]);    MULADD(at[8], at[40]);    MULADD(at[9], at[39]);    MULADD(at[10], at[38]);    MULADD(at[11], at[37]);    MULADD(at[12], at[36]);    MULADD(at[13], at[35]);    MULADD(at[14], at[34]);    MULADD(at[15], at[33]);    MULADD(at[16], at[32]);    MULADD(at[17], at[31]);    MULADD(at[18], at[30]);    MULADD(at[19], at[29]);    MULADD(at[20], at[28]);    MULADD(at[21], at[27]);    MULADD(at[22], at[26]);    MULADD(at[23], at[25]); 
+   COMBA_STORE(C->dp[24]);
+   /* 25 */
+   COMBA_FORWARD;
+   MULADD(at[2], at[47]);    MULADD(at[3], at[46]);    MULADD(at[4], at[45]);    MULADD(at[5], at[44]);    MULADD(at[6], at[43]);    MULADD(at[7], at[42]);    MULADD(at[8], at[41]);    MULADD(at[9], at[40]);    MULADD(at[10], at[39]);    MULADD(at[11], at[38]);    MULADD(at[12], at[37]);    MULADD(at[13], at[36]);    MULADD(at[14], at[35]);    MULADD(at[15], at[34]);    MULADD(at[16], at[33]);    MULADD(at[17], at[32]);    MULADD(at[18], at[31]);    MULADD(at[19], at[30]);    MULADD(at[20], at[29]);    MULADD(at[21], at[28]);    MULADD(at[22], at[27]);    MULADD(at[23], at[26]); 
+   COMBA_STORE(C->dp[25]);
+   /* 26 */
+   COMBA_FORWARD;
+   MULADD(at[3], at[47]);    MULADD(at[4], at[46]);    MULADD(at[5], at[45]);    MULADD(at[6], at[44]);    MULADD(at[7], at[43]);    MULADD(at[8], at[42]);    MULADD(at[9], at[41]);    MULADD(at[10], at[40]);    MULADD(at[11], at[39]);    MULADD(at[12], at[38]);    MULADD(at[13], at[37]);    MULADD(at[14], at[36]);    MULADD(at[15], at[35]);    MULADD(at[16], at[34]);    MULADD(at[17], at[33]);    MULADD(at[18], at[32]);    MULADD(at[19], at[31]);    MULADD(at[20], at[30]);    MULADD(at[21], at[29]);    MULADD(at[22], at[28]);    MULADD(at[23], at[27]); 
+   COMBA_STORE(C->dp[26]);
+   /* 27 */
+   COMBA_FORWARD;
+   MULADD(at[4], at[47]);    MULADD(at[5], at[46]);    MULADD(at[6], at[45]);    MULADD(at[7], at[44]);    MULADD(at[8], at[43]);    MULADD(at[9], at[42]);    MULADD(at[10], at[41]);    MULADD(at[11], at[40]);    MULADD(at[12], at[39]);    MULADD(at[13], at[38]);    MULADD(at[14], at[37]);    MULADD(at[15], at[36]);    MULADD(at[16], at[35]);    MULADD(at[17], at[34]);    MULADD(at[18], at[33]);    MULADD(at[19], at[32]);    MULADD(at[20], at[31]);    MULADD(at[21], at[30]);    MULADD(at[22], at[29]);    MULADD(at[23], at[28]); 
+   COMBA_STORE(C->dp[27]);
+   /* 28 */
+   COMBA_FORWARD;
+   MULADD(at[5], at[47]);    MULADD(at[6], at[46]);    MULADD(at[7], at[45]);    MULADD(at[8], at[44]);    MULADD(at[9], at[43]);    MULADD(at[10], at[42]);    MULADD(at[11], at[41]);    MULADD(at[12], at[40]);    MULADD(at[13], at[39]);    MULADD(at[14], at[38]);    MULADD(at[15], at[37]);    MULADD(at[16], at[36]);    MULADD(at[17], at[35]);    MULADD(at[18], at[34]);    MULADD(at[19], at[33]);    MULADD(at[20], at[32]);    MULADD(at[21], at[31]);    MULADD(at[22], at[30]);    MULADD(at[23], at[29]); 
+   COMBA_STORE(C->dp[28]);
+   /* 29 */
+   COMBA_FORWARD;
+   MULADD(at[6], at[47]);    MULADD(at[7], at[46]);    MULADD(at[8], at[45]);    MULADD(at[9], at[44]);    MULADD(at[10], at[43]);    MULADD(at[11], at[42]);    MULADD(at[12], at[41]);    MULADD(at[13], at[40]);    MULADD(at[14], at[39]);    MULADD(at[15], at[38]);    MULADD(at[16], at[37]);    MULADD(at[17], at[36]);    MULADD(at[18], at[35]);    MULADD(at[19], at[34]);    MULADD(at[20], at[33]);    MULADD(at[21], at[32]);    MULADD(at[22], at[31]);    MULADD(at[23], at[30]); 
+   COMBA_STORE(C->dp[29]);
+   /* 30 */
+   COMBA_FORWARD;
+   MULADD(at[7], at[47]);    MULADD(at[8], at[46]);    MULADD(at[9], at[45]);    MULADD(at[10], at[44]);    MULADD(at[11], at[43]);    MULADD(at[12], at[42]);    MULADD(at[13], at[41]);    MULADD(at[14], at[40]);    MULADD(at[15], at[39]);    MULADD(at[16], at[38]);    MULADD(at[17], at[37]);    MULADD(at[18], at[36]);    MULADD(at[19], at[35]);    MULADD(at[20], at[34]);    MULADD(at[21], at[33]);    MULADD(at[22], at[32]);    MULADD(at[23], at[31]); 
+   COMBA_STORE(C->dp[30]);
+   /* 31 */
+   COMBA_FORWARD;
+   MULADD(at[8], at[47]);    MULADD(at[9], at[46]);    MULADD(at[10], at[45]);    MULADD(at[11], at[44]);    MULADD(at[12], at[43]);    MULADD(at[13], at[42]);    MULADD(at[14], at[41]);    MULADD(at[15], at[40]);    MULADD(at[16], at[39]);    MULADD(at[17], at[38]);    MULADD(at[18], at[37]);    MULADD(at[19], at[36]);    MULADD(at[20], at[35]);    MULADD(at[21], at[34]);    MULADD(at[22], at[33]);    MULADD(at[23], at[32]); 
+   COMBA_STORE(C->dp[31]);
+   /* 32 */
+   COMBA_FORWARD;
+   MULADD(at[9], at[47]);    MULADD(at[10], at[46]);    MULADD(at[11], at[45]);    MULADD(at[12], at[44]);    MULADD(at[13], at[43]);    MULADD(at[14], at[42]);    MULADD(at[15], at[41]);    MULADD(at[16], at[40]);    MULADD(at[17], at[39]);    MULADD(at[18], at[38]);    MULADD(at[19], at[37]);    MULADD(at[20], at[36]);    MULADD(at[21], at[35]);    MULADD(at[22], at[34]);    MULADD(at[23], at[33]); 
+   COMBA_STORE(C->dp[32]);
+   /* 33 */
+   COMBA_FORWARD;
+   MULADD(at[10], at[47]);    MULADD(at[11], at[46]);    MULADD(at[12], at[45]);    MULADD(at[13], at[44]);    MULADD(at[14], at[43]);    MULADD(at[15], at[42]);    MULADD(at[16], at[41]);    MULADD(at[17], at[40]);    MULADD(at[18], at[39]);    MULADD(at[19], at[38]);    MULADD(at[20], at[37]);    MULADD(at[21], at[36]);    MULADD(at[22], at[35]);    MULADD(at[23], at[34]); 
+   COMBA_STORE(C->dp[33]);
+   /* 34 */
+   COMBA_FORWARD;
+   MULADD(at[11], at[47]);    MULADD(at[12], at[46]);    MULADD(at[13], at[45]);    MULADD(at[14], at[44]);    MULADD(at[15], at[43]);    MULADD(at[16], at[42]);    MULADD(at[17], at[41]);    MULADD(at[18], at[40]);    MULADD(at[19], at[39]);    MULADD(at[20], at[38]);    MULADD(at[21], at[37]);    MULADD(at[22], at[36]);    MULADD(at[23], at[35]); 
+   COMBA_STORE(C->dp[34]);
+   /* 35 */
+   COMBA_FORWARD;
+   MULADD(at[12], at[47]);    MULADD(at[13], at[46]);    MULADD(at[14], at[45]);    MULADD(at[15], at[44]);    MULADD(at[16], at[43]);    MULADD(at[17], at[42]);    MULADD(at[18], at[41]);    MULADD(at[19], at[40]);    MULADD(at[20], at[39]);    MULADD(at[21], at[38]);    MULADD(at[22], at[37]);    MULADD(at[23], at[36]); 
+   COMBA_STORE(C->dp[35]);
+   /* 36 */
+   COMBA_FORWARD;
+   MULADD(at[13], at[47]);    MULADD(at[14], at[46]);    MULADD(at[15], at[45]);    MULADD(at[16], at[44]);    MULADD(at[17], at[43]);    MULADD(at[18], at[42]);    MULADD(at[19], at[41]);    MULADD(at[20], at[40]);    MULADD(at[21], at[39]);    MULADD(at[22], at[38]);    MULADD(at[23], at[37]); 
+   COMBA_STORE(C->dp[36]);
+   /* 37 */
+   COMBA_FORWARD;
+   MULADD(at[14], at[47]);    MULADD(at[15], at[46]);    MULADD(at[16], at[45]);    MULADD(at[17], at[44]);    MULADD(at[18], at[43]);    MULADD(at[19], at[42]);    MULADD(at[20], at[41]);    MULADD(at[21], at[40]);    MULADD(at[22], at[39]);    MULADD(at[23], at[38]); 
+   COMBA_STORE(C->dp[37]);
+   /* 38 */
+   COMBA_FORWARD;
+   MULADD(at[15], at[47]);    MULADD(at[16], at[46]);    MULADD(at[17], at[45]);    MULADD(at[18], at[44]);    MULADD(at[19], at[43]);    MULADD(at[20], at[42]);    MULADD(at[21], at[41]);    MULADD(at[22], at[40]);    MULADD(at[23], at[39]); 
+   COMBA_STORE(C->dp[38]);
+   /* 39 */
+   COMBA_FORWARD;
+   MULADD(at[16], at[47]);    MULADD(at[17], at[46]);    MULADD(at[18], at[45]);    MULADD(at[19], at[44]);    MULADD(at[20], at[43]);    MULADD(at[21], at[42]);    MULADD(at[22], at[41]);    MULADD(at[23], at[40]); 
+   COMBA_STORE(C->dp[39]);
+   /* 40 */
+   COMBA_FORWARD;
+   MULADD(at[17], at[47]);    MULADD(at[18], at[46]);    MULADD(at[19], at[45]);    MULADD(at[20], at[44]);    MULADD(at[21], at[43]);    MULADD(at[22], at[42]);    MULADD(at[23], at[41]); 
+   COMBA_STORE(C->dp[40]);
+   /* 41 */
+   COMBA_FORWARD;
+   MULADD(at[18], at[47]);    MULADD(at[19], at[46]);    MULADD(at[20], at[45]);    MULADD(at[21], at[44]);    MULADD(at[22], at[43]);    MULADD(at[23], at[42]); 
+   COMBA_STORE(C->dp[41]);
+   /* 42 */
+   COMBA_FORWARD;
+   MULADD(at[19], at[47]);    MULADD(at[20], at[46]);    MULADD(at[21], at[45]);    MULADD(at[22], at[44]);    MULADD(at[23], at[43]); 
+   COMBA_STORE(C->dp[42]);
+   /* 43 */
+   COMBA_FORWARD;
+   MULADD(at[20], at[47]);    MULADD(at[21], at[46]);    MULADD(at[22], at[45]);    MULADD(at[23], at[44]); 
+   COMBA_STORE(C->dp[43]);
+   /* 44 */
+   COMBA_FORWARD;
+   MULADD(at[21], at[47]);    MULADD(at[22], at[46]);    MULADD(at[23], at[45]); 
+   COMBA_STORE(C->dp[44]);
+   /* 45 */
+   COMBA_FORWARD;
+   MULADD(at[22], at[47]);    MULADD(at[23], at[46]); 
+   COMBA_STORE(C->dp[45]);
+   /* 46 */
+   COMBA_FORWARD;
+   MULADD(at[23], at[47]); 
+   COMBA_STORE(C->dp[46]);
+   COMBA_STORE2(C->dp[47]);
+   C->used = 48;
+   C->sign = A->sign ^ B->sign;
+   fp_clamp(C);
+   COMBA_FINI;
+}
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_28.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_28.i
new file mode 100644
index 0000000..822dd14
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_28.i
@@ -0,0 +1,258 @@
+/* fp_mul_comba_28.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_MUL28
+void fp_mul_comba28(fp_int *A, fp_int *B, fp_int *C)
+{
+   fp_digit c0, c1, c2, at[56];
+
+   memcpy(at, A->dp, 28 * sizeof(fp_digit));
+   memcpy(at+28, B->dp, 28 * sizeof(fp_digit));
+   COMBA_START;
+
+   COMBA_CLEAR;
+   /* 0 */
+   MULADD(at[0], at[28]); 
+   COMBA_STORE(C->dp[0]);
+   /* 1 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[29]);    MULADD(at[1], at[28]); 
+   COMBA_STORE(C->dp[1]);
+   /* 2 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[30]);    MULADD(at[1], at[29]);    MULADD(at[2], at[28]); 
+   COMBA_STORE(C->dp[2]);
+   /* 3 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[31]);    MULADD(at[1], at[30]);    MULADD(at[2], at[29]);    MULADD(at[3], at[28]); 
+   COMBA_STORE(C->dp[3]);
+   /* 4 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[32]);    MULADD(at[1], at[31]);    MULADD(at[2], at[30]);    MULADD(at[3], at[29]);    MULADD(at[4], at[28]); 
+   COMBA_STORE(C->dp[4]);
+   /* 5 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[33]);    MULADD(at[1], at[32]);    MULADD(at[2], at[31]);    MULADD(at[3], at[30]);    MULADD(at[4], at[29]);    MULADD(at[5], at[28]); 
+   COMBA_STORE(C->dp[5]);
+   /* 6 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[34]);    MULADD(at[1], at[33]);    MULADD(at[2], at[32]);    MULADD(at[3], at[31]);    MULADD(at[4], at[30]);    MULADD(at[5], at[29]);    MULADD(at[6], at[28]); 
+   COMBA_STORE(C->dp[6]);
+   /* 7 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[35]);    MULADD(at[1], at[34]);    MULADD(at[2], at[33]);    MULADD(at[3], at[32]);    MULADD(at[4], at[31]);    MULADD(at[5], at[30]);    MULADD(at[6], at[29]);    MULADD(at[7], at[28]); 
+   COMBA_STORE(C->dp[7]);
+   /* 8 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[36]);    MULADD(at[1], at[35]);    MULADD(at[2], at[34]);    MULADD(at[3], at[33]);    MULADD(at[4], at[32]);    MULADD(at[5], at[31]);    MULADD(at[6], at[30]);    MULADD(at[7], at[29]);    MULADD(at[8], at[28]); 
+   COMBA_STORE(C->dp[8]);
+   /* 9 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[37]);    MULADD(at[1], at[36]);    MULADD(at[2], at[35]);    MULADD(at[3], at[34]);    MULADD(at[4], at[33]);    MULADD(at[5], at[32]);    MULADD(at[6], at[31]);    MULADD(at[7], at[30]);    MULADD(at[8], at[29]);    MULADD(at[9], at[28]); 
+   COMBA_STORE(C->dp[9]);
+   /* 10 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[38]);    MULADD(at[1], at[37]);    MULADD(at[2], at[36]);    MULADD(at[3], at[35]);    MULADD(at[4], at[34]);    MULADD(at[5], at[33]);    MULADD(at[6], at[32]);    MULADD(at[7], at[31]);    MULADD(at[8], at[30]);    MULADD(at[9], at[29]);    MULADD(at[10], at[28]); 
+   COMBA_STORE(C->dp[10]);
+   /* 11 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[39]);    MULADD(at[1], at[38]);    MULADD(at[2], at[37]);    MULADD(at[3], at[36]);    MULADD(at[4], at[35]);    MULADD(at[5], at[34]);    MULADD(at[6], at[33]);    MULADD(at[7], at[32]);    MULADD(at[8], at[31]);    MULADD(at[9], at[30]);    MULADD(at[10], at[29]);    MULADD(at[11], at[28]); 
+   COMBA_STORE(C->dp[11]);
+   /* 12 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[40]);    MULADD(at[1], at[39]);    MULADD(at[2], at[38]);    MULADD(at[3], at[37]);    MULADD(at[4], at[36]);    MULADD(at[5], at[35]);    MULADD(at[6], at[34]);    MULADD(at[7], at[33]);    MULADD(at[8], at[32]);    MULADD(at[9], at[31]);    MULADD(at[10], at[30]);    MULADD(at[11], at[29]);    MULADD(at[12], at[28]); 
+   COMBA_STORE(C->dp[12]);
+   /* 13 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[41]);    MULADD(at[1], at[40]);    MULADD(at[2], at[39]);    MULADD(at[3], at[38]);    MULADD(at[4], at[37]);    MULADD(at[5], at[36]);    MULADD(at[6], at[35]);    MULADD(at[7], at[34]);    MULADD(at[8], at[33]);    MULADD(at[9], at[32]);    MULADD(at[10], at[31]);    MULADD(at[11], at[30]);    MULADD(at[12], at[29]);    MULADD(at[13], at[28]); 
+   COMBA_STORE(C->dp[13]);
+   /* 14 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[42]);    MULADD(at[1], at[41]);    MULADD(at[2], at[40]);    MULADD(at[3], at[39]);    MULADD(at[4], at[38]);    MULADD(at[5], at[37]);    MULADD(at[6], at[36]);    MULADD(at[7], at[35]);    MULADD(at[8], at[34]);    MULADD(at[9], at[33]);    MULADD(at[10], at[32]);    MULADD(at[11], at[31]);    MULADD(at[12], at[30]);    MULADD(at[13], at[29]);    MULADD(at[14], at[28]); 
+   COMBA_STORE(C->dp[14]);
+   /* 15 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[43]);    MULADD(at[1], at[42]);    MULADD(at[2], at[41]);    MULADD(at[3], at[40]);    MULADD(at[4], at[39]);    MULADD(at[5], at[38]);    MULADD(at[6], at[37]);    MULADD(at[7], at[36]);    MULADD(at[8], at[35]);    MULADD(at[9], at[34]);    MULADD(at[10], at[33]);    MULADD(at[11], at[32]);    MULADD(at[12], at[31]);    MULADD(at[13], at[30]);    MULADD(at[14], at[29]);    MULADD(at[15], at[28]); 
+   COMBA_STORE(C->dp[15]);
+   /* 16 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[44]);    MULADD(at[1], at[43]);    MULADD(at[2], at[42]);    MULADD(at[3], at[41]);    MULADD(at[4], at[40]);    MULADD(at[5], at[39]);    MULADD(at[6], at[38]);    MULADD(at[7], at[37]);    MULADD(at[8], at[36]);    MULADD(at[9], at[35]);    MULADD(at[10], at[34]);    MULADD(at[11], at[33]);    MULADD(at[12], at[32]);    MULADD(at[13], at[31]);    MULADD(at[14], at[30]);    MULADD(at[15], at[29]);    MULADD(at[16], at[28]); 
+   COMBA_STORE(C->dp[16]);
+   /* 17 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[45]);    MULADD(at[1], at[44]);    MULADD(at[2], at[43]);    MULADD(at[3], at[42]);    MULADD(at[4], at[41]);    MULADD(at[5], at[40]);    MULADD(at[6], at[39]);    MULADD(at[7], at[38]);    MULADD(at[8], at[37]);    MULADD(at[9], at[36]);    MULADD(at[10], at[35]);    MULADD(at[11], at[34]);    MULADD(at[12], at[33]);    MULADD(at[13], at[32]);    MULADD(at[14], at[31]);    MULADD(at[15], at[30]);    MULADD(at[16], at[29]);    MULADD(at[17], at[28]); 
+   COMBA_STORE(C->dp[17]);
+   /* 18 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[46]);    MULADD(at[1], at[45]);    MULADD(at[2], at[44]);    MULADD(at[3], at[43]);    MULADD(at[4], at[42]);    MULADD(at[5], at[41]);    MULADD(at[6], at[40]);    MULADD(at[7], at[39]);    MULADD(at[8], at[38]);    MULADD(at[9], at[37]);    MULADD(at[10], at[36]);    MULADD(at[11], at[35]);    MULADD(at[12], at[34]);    MULADD(at[13], at[33]);    MULADD(at[14], at[32]);    MULADD(at[15], at[31]);    MULADD(at[16], at[30]);    MULADD(at[17], at[29]);    MULADD(at[18], at[28]); 
+   COMBA_STORE(C->dp[18]);
+   /* 19 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[47]);    MULADD(at[1], at[46]);    MULADD(at[2], at[45]);    MULADD(at[3], at[44]);    MULADD(at[4], at[43]);    MULADD(at[5], at[42]);    MULADD(at[6], at[41]);    MULADD(at[7], at[40]);    MULADD(at[8], at[39]);    MULADD(at[9], at[38]);    MULADD(at[10], at[37]);    MULADD(at[11], at[36]);    MULADD(at[12], at[35]);    MULADD(at[13], at[34]);    MULADD(at[14], at[33]);    MULADD(at[15], at[32]);    MULADD(at[16], at[31]);    MULADD(at[17], at[30]);    MULADD(at[18], at[29]);    MULADD(at[19], at[28]); 
+   COMBA_STORE(C->dp[19]);
+   /* 20 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[48]);    MULADD(at[1], at[47]);    MULADD(at[2], at[46]);    MULADD(at[3], at[45]);    MULADD(at[4], at[44]);    MULADD(at[5], at[43]);    MULADD(at[6], at[42]);    MULADD(at[7], at[41]);    MULADD(at[8], at[40]);    MULADD(at[9], at[39]);    MULADD(at[10], at[38]);    MULADD(at[11], at[37]);    MULADD(at[12], at[36]);    MULADD(at[13], at[35]);    MULADD(at[14], at[34]);    MULADD(at[15], at[33]);    MULADD(at[16], at[32]);    MULADD(at[17], at[31]);    MULADD(at[18], at[30]);    MULADD(at[19], at[29]);    MULADD(at[20], at[28]); 
+   COMBA_STORE(C->dp[20]);
+   /* 21 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[49]);    MULADD(at[1], at[48]);    MULADD(at[2], at[47]);    MULADD(at[3], at[46]);    MULADD(at[4], at[45]);    MULADD(at[5], at[44]);    MULADD(at[6], at[43]);    MULADD(at[7], at[42]);    MULADD(at[8], at[41]);    MULADD(at[9], at[40]);    MULADD(at[10], at[39]);    MULADD(at[11], at[38]);    MULADD(at[12], at[37]);    MULADD(at[13], at[36]);    MULADD(at[14], at[35]);    MULADD(at[15], at[34]);    MULADD(at[16], at[33]);    MULADD(at[17], at[32]);    MULADD(at[18], at[31]);    MULADD(at[19], at[30]);    MULADD(at[20], at[29]);    MULADD(at[21], at[28]); 
+   COMBA_STORE(C->dp[21]);
+   /* 22 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[50]);    MULADD(at[1], at[49]);    MULADD(at[2], at[48]);    MULADD(at[3], at[47]);    MULADD(at[4], at[46]);    MULADD(at[5], at[45]);    MULADD(at[6], at[44]);    MULADD(at[7], at[43]);    MULADD(at[8], at[42]);    MULADD(at[9], at[41]);    MULADD(at[10], at[40]);    MULADD(at[11], at[39]);    MULADD(at[12], at[38]);    MULADD(at[13], at[37]);    MULADD(at[14], at[36]);    MULADD(at[15], at[35]);    MULADD(at[16], at[34]);    MULADD(at[17], at[33]);    MULADD(at[18], at[32]);    MULADD(at[19], at[31]);    MULADD(at[20], at[30]);    MULADD(at[21], at[29]);    MULADD(at[22], at[28]); 
+   COMBA_STORE(C->dp[22]);
+   /* 23 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[51]);    MULADD(at[1], at[50]);    MULADD(at[2], at[49]);    MULADD(at[3], at[48]);    MULADD(at[4], at[47]);    MULADD(at[5], at[46]);    MULADD(at[6], at[45]);    MULADD(at[7], at[44]);    MULADD(at[8], at[43]);    MULADD(at[9], at[42]);    MULADD(at[10], at[41]);    MULADD(at[11], at[40]);    MULADD(at[12], at[39]);    MULADD(at[13], at[38]);    MULADD(at[14], at[37]);    MULADD(at[15], at[36]);    MULADD(at[16], at[35]);    MULADD(at[17], at[34]);    MULADD(at[18], at[33]);    MULADD(at[19], at[32]);    MULADD(at[20], at[31]);    MULADD(at[21], at[30]);    MULADD(at[22], at[29]);    MULADD(at[23], at[28]); 
+   COMBA_STORE(C->dp[23]);
+   /* 24 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[52]);    MULADD(at[1], at[51]);    MULADD(at[2], at[50]);    MULADD(at[3], at[49]);    MULADD(at[4], at[48]);    MULADD(at[5], at[47]);    MULADD(at[6], at[46]);    MULADD(at[7], at[45]);    MULADD(at[8], at[44]);    MULADD(at[9], at[43]);    MULADD(at[10], at[42]);    MULADD(at[11], at[41]);    MULADD(at[12], at[40]);    MULADD(at[13], at[39]);    MULADD(at[14], at[38]);    MULADD(at[15], at[37]);    MULADD(at[16], at[36]);    MULADD(at[17], at[35]);    MULADD(at[18], at[34]);    MULADD(at[19], at[33]);    MULADD(at[20], at[32]);    MULADD(at[21], at[31]);    MULADD(at[22], at[30]);    MULADD(at[23], at[29]);    MULADD(at[24], at[28]); 
+   COMBA_STORE(C->dp[24]);
+   /* 25 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[53]);    MULADD(at[1], at[52]);    MULADD(at[2], at[51]);    MULADD(at[3], at[50]);    MULADD(at[4], at[49]);    MULADD(at[5], at[48]);    MULADD(at[6], at[47]);    MULADD(at[7], at[46]);    MULADD(at[8], at[45]);    MULADD(at[9], at[44]);    MULADD(at[10], at[43]);    MULADD(at[11], at[42]);    MULADD(at[12], at[41]);    MULADD(at[13], at[40]);    MULADD(at[14], at[39]);    MULADD(at[15], at[38]);    MULADD(at[16], at[37]);    MULADD(at[17], at[36]);    MULADD(at[18], at[35]);    MULADD(at[19], at[34]);    MULADD(at[20], at[33]);    MULADD(at[21], at[32]);    MULADD(at[22], at[31]);    MULADD(at[23], at[30]);    MULADD(at[24], at[29]);    MULADD(at[25], at[28]); 
+   COMBA_STORE(C->dp[25]);
+   /* 26 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[54]);    MULADD(at[1], at[53]);    MULADD(at[2], at[52]);    MULADD(at[3], at[51]);    MULADD(at[4], at[50]);    MULADD(at[5], at[49]);    MULADD(at[6], at[48]);    MULADD(at[7], at[47]);    MULADD(at[8], at[46]);    MULADD(at[9], at[45]);    MULADD(at[10], at[44]);    MULADD(at[11], at[43]);    MULADD(at[12], at[42]);    MULADD(at[13], at[41]);    MULADD(at[14], at[40]);    MULADD(at[15], at[39]);    MULADD(at[16], at[38]);    MULADD(at[17], at[37]);    MULADD(at[18], at[36]);    MULADD(at[19], at[35]);    MULADD(at[20], at[34]);    MULADD(at[21], at[33]);    MULADD(at[22], at[32]);    MULADD(at[23], at[31]);    MULADD(at[24], at[30]);    MULADD(at[25], at[29]);    MULADD(at[26], at[28]); 
+   COMBA_STORE(C->dp[26]);
+   /* 27 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[55]);    MULADD(at[1], at[54]);    MULADD(at[2], at[53]);    MULADD(at[3], at[52]);    MULADD(at[4], at[51]);    MULADD(at[5], at[50]);    MULADD(at[6], at[49]);    MULADD(at[7], at[48]);    MULADD(at[8], at[47]);    MULADD(at[9], at[46]);    MULADD(at[10], at[45]);    MULADD(at[11], at[44]);    MULADD(at[12], at[43]);    MULADD(at[13], at[42]);    MULADD(at[14], at[41]);    MULADD(at[15], at[40]);    MULADD(at[16], at[39]);    MULADD(at[17], at[38]);    MULADD(at[18], at[37]);    MULADD(at[19], at[36]);    MULADD(at[20], at[35]);    MULADD(at[21], at[34]);    MULADD(at[22], at[33]);    MULADD(at[23], at[32]);    MULADD(at[24], at[31]);    MULADD(at[25], at[30]);    MULADD(at[26], at[29]);    MULADD(at[27], at[28]); 
+   COMBA_STORE(C->dp[27]);
+   /* 28 */
+   COMBA_FORWARD;
+   MULADD(at[1], at[55]);    MULADD(at[2], at[54]);    MULADD(at[3], at[53]);    MULADD(at[4], at[52]);    MULADD(at[5], at[51]);    MULADD(at[6], at[50]);    MULADD(at[7], at[49]);    MULADD(at[8], at[48]);    MULADD(at[9], at[47]);    MULADD(at[10], at[46]);    MULADD(at[11], at[45]);    MULADD(at[12], at[44]);    MULADD(at[13], at[43]);    MULADD(at[14], at[42]);    MULADD(at[15], at[41]);    MULADD(at[16], at[40]);    MULADD(at[17], at[39]);    MULADD(at[18], at[38]);    MULADD(at[19], at[37]);    MULADD(at[20], at[36]);    MULADD(at[21], at[35]);    MULADD(at[22], at[34]);    MULADD(at[23], at[33]);    MULADD(at[24], at[32]);    MULADD(at[25], at[31]);    MULADD(at[26], at[30]);    MULADD(at[27], at[29]); 
+   COMBA_STORE(C->dp[28]);
+   /* 29 */
+   COMBA_FORWARD;
+   MULADD(at[2], at[55]);    MULADD(at[3], at[54]);    MULADD(at[4], at[53]);    MULADD(at[5], at[52]);    MULADD(at[6], at[51]);    MULADD(at[7], at[50]);    MULADD(at[8], at[49]);    MULADD(at[9], at[48]);    MULADD(at[10], at[47]);    MULADD(at[11], at[46]);    MULADD(at[12], at[45]);    MULADD(at[13], at[44]);    MULADD(at[14], at[43]);    MULADD(at[15], at[42]);    MULADD(at[16], at[41]);    MULADD(at[17], at[40]);    MULADD(at[18], at[39]);    MULADD(at[19], at[38]);    MULADD(at[20], at[37]);    MULADD(at[21], at[36]);    MULADD(at[22], at[35]);    MULADD(at[23], at[34]);    MULADD(at[24], at[33]);    MULADD(at[25], at[32]);    MULADD(at[26], at[31]);    MULADD(at[27], at[30]); 
+   COMBA_STORE(C->dp[29]);
+   /* 30 */
+   COMBA_FORWARD;
+   MULADD(at[3], at[55]);    MULADD(at[4], at[54]);    MULADD(at[5], at[53]);    MULADD(at[6], at[52]);    MULADD(at[7], at[51]);    MULADD(at[8], at[50]);    MULADD(at[9], at[49]);    MULADD(at[10], at[48]);    MULADD(at[11], at[47]);    MULADD(at[12], at[46]);    MULADD(at[13], at[45]);    MULADD(at[14], at[44]);    MULADD(at[15], at[43]);    MULADD(at[16], at[42]);    MULADD(at[17], at[41]);    MULADD(at[18], at[40]);    MULADD(at[19], at[39]);    MULADD(at[20], at[38]);    MULADD(at[21], at[37]);    MULADD(at[22], at[36]);    MULADD(at[23], at[35]);    MULADD(at[24], at[34]);    MULADD(at[25], at[33]);    MULADD(at[26], at[32]);    MULADD(at[27], at[31]); 
+   COMBA_STORE(C->dp[30]);
+   /* 31 */
+   COMBA_FORWARD;
+   MULADD(at[4], at[55]);    MULADD(at[5], at[54]);    MULADD(at[6], at[53]);    MULADD(at[7], at[52]);    MULADD(at[8], at[51]);    MULADD(at[9], at[50]);    MULADD(at[10], at[49]);    MULADD(at[11], at[48]);    MULADD(at[12], at[47]);    MULADD(at[13], at[46]);    MULADD(at[14], at[45]);    MULADD(at[15], at[44]);    MULADD(at[16], at[43]);    MULADD(at[17], at[42]);    MULADD(at[18], at[41]);    MULADD(at[19], at[40]);    MULADD(at[20], at[39]);    MULADD(at[21], at[38]);    MULADD(at[22], at[37]);    MULADD(at[23], at[36]);    MULADD(at[24], at[35]);    MULADD(at[25], at[34]);    MULADD(at[26], at[33]);    MULADD(at[27], at[32]); 
+   COMBA_STORE(C->dp[31]);
+   /* 32 */
+   COMBA_FORWARD;
+   MULADD(at[5], at[55]);    MULADD(at[6], at[54]);    MULADD(at[7], at[53]);    MULADD(at[8], at[52]);    MULADD(at[9], at[51]);    MULADD(at[10], at[50]);    MULADD(at[11], at[49]);    MULADD(at[12], at[48]);    MULADD(at[13], at[47]);    MULADD(at[14], at[46]);    MULADD(at[15], at[45]);    MULADD(at[16], at[44]);    MULADD(at[17], at[43]);    MULADD(at[18], at[42]);    MULADD(at[19], at[41]);    MULADD(at[20], at[40]);    MULADD(at[21], at[39]);    MULADD(at[22], at[38]);    MULADD(at[23], at[37]);    MULADD(at[24], at[36]);    MULADD(at[25], at[35]);    MULADD(at[26], at[34]);    MULADD(at[27], at[33]); 
+   COMBA_STORE(C->dp[32]);
+   /* 33 */
+   COMBA_FORWARD;
+   MULADD(at[6], at[55]);    MULADD(at[7], at[54]);    MULADD(at[8], at[53]);    MULADD(at[9], at[52]);    MULADD(at[10], at[51]);    MULADD(at[11], at[50]);    MULADD(at[12], at[49]);    MULADD(at[13], at[48]);    MULADD(at[14], at[47]);    MULADD(at[15], at[46]);    MULADD(at[16], at[45]);    MULADD(at[17], at[44]);    MULADD(at[18], at[43]);    MULADD(at[19], at[42]);    MULADD(at[20], at[41]);    MULADD(at[21], at[40]);    MULADD(at[22], at[39]);    MULADD(at[23], at[38]);    MULADD(at[24], at[37]);    MULADD(at[25], at[36]);    MULADD(at[26], at[35]);    MULADD(at[27], at[34]); 
+   COMBA_STORE(C->dp[33]);
+   /* 34 */
+   COMBA_FORWARD;
+   MULADD(at[7], at[55]);    MULADD(at[8], at[54]);    MULADD(at[9], at[53]);    MULADD(at[10], at[52]);    MULADD(at[11], at[51]);    MULADD(at[12], at[50]);    MULADD(at[13], at[49]);    MULADD(at[14], at[48]);    MULADD(at[15], at[47]);    MULADD(at[16], at[46]);    MULADD(at[17], at[45]);    MULADD(at[18], at[44]);    MULADD(at[19], at[43]);    MULADD(at[20], at[42]);    MULADD(at[21], at[41]);    MULADD(at[22], at[40]);    MULADD(at[23], at[39]);    MULADD(at[24], at[38]);    MULADD(at[25], at[37]);    MULADD(at[26], at[36]);    MULADD(at[27], at[35]); 
+   COMBA_STORE(C->dp[34]);
+   /* 35 */
+   COMBA_FORWARD;
+   MULADD(at[8], at[55]);    MULADD(at[9], at[54]);    MULADD(at[10], at[53]);    MULADD(at[11], at[52]);    MULADD(at[12], at[51]);    MULADD(at[13], at[50]);    MULADD(at[14], at[49]);    MULADD(at[15], at[48]);    MULADD(at[16], at[47]);    MULADD(at[17], at[46]);    MULADD(at[18], at[45]);    MULADD(at[19], at[44]);    MULADD(at[20], at[43]);    MULADD(at[21], at[42]);    MULADD(at[22], at[41]);    MULADD(at[23], at[40]);    MULADD(at[24], at[39]);    MULADD(at[25], at[38]);    MULADD(at[26], at[37]);    MULADD(at[27], at[36]); 
+   COMBA_STORE(C->dp[35]);
+   /* 36 */
+   COMBA_FORWARD;
+   MULADD(at[9], at[55]);    MULADD(at[10], at[54]);    MULADD(at[11], at[53]);    MULADD(at[12], at[52]);    MULADD(at[13], at[51]);    MULADD(at[14], at[50]);    MULADD(at[15], at[49]);    MULADD(at[16], at[48]);    MULADD(at[17], at[47]);    MULADD(at[18], at[46]);    MULADD(at[19], at[45]);    MULADD(at[20], at[44]);    MULADD(at[21], at[43]);    MULADD(at[22], at[42]);    MULADD(at[23], at[41]);    MULADD(at[24], at[40]);    MULADD(at[25], at[39]);    MULADD(at[26], at[38]);    MULADD(at[27], at[37]); 
+   COMBA_STORE(C->dp[36]);
+   /* 37 */
+   COMBA_FORWARD;
+   MULADD(at[10], at[55]);    MULADD(at[11], at[54]);    MULADD(at[12], at[53]);    MULADD(at[13], at[52]);    MULADD(at[14], at[51]);    MULADD(at[15], at[50]);    MULADD(at[16], at[49]);    MULADD(at[17], at[48]);    MULADD(at[18], at[47]);    MULADD(at[19], at[46]);    MULADD(at[20], at[45]);    MULADD(at[21], at[44]);    MULADD(at[22], at[43]);    MULADD(at[23], at[42]);    MULADD(at[24], at[41]);    MULADD(at[25], at[40]);    MULADD(at[26], at[39]);    MULADD(at[27], at[38]); 
+   COMBA_STORE(C->dp[37]);
+   /* 38 */
+   COMBA_FORWARD;
+   MULADD(at[11], at[55]);    MULADD(at[12], at[54]);    MULADD(at[13], at[53]);    MULADD(at[14], at[52]);    MULADD(at[15], at[51]);    MULADD(at[16], at[50]);    MULADD(at[17], at[49]);    MULADD(at[18], at[48]);    MULADD(at[19], at[47]);    MULADD(at[20], at[46]);    MULADD(at[21], at[45]);    MULADD(at[22], at[44]);    MULADD(at[23], at[43]);    MULADD(at[24], at[42]);    MULADD(at[25], at[41]);    MULADD(at[26], at[40]);    MULADD(at[27], at[39]); 
+   COMBA_STORE(C->dp[38]);
+   /* 39 */
+   COMBA_FORWARD;
+   MULADD(at[12], at[55]);    MULADD(at[13], at[54]);    MULADD(at[14], at[53]);    MULADD(at[15], at[52]);    MULADD(at[16], at[51]);    MULADD(at[17], at[50]);    MULADD(at[18], at[49]);    MULADD(at[19], at[48]);    MULADD(at[20], at[47]);    MULADD(at[21], at[46]);    MULADD(at[22], at[45]);    MULADD(at[23], at[44]);    MULADD(at[24], at[43]);    MULADD(at[25], at[42]);    MULADD(at[26], at[41]);    MULADD(at[27], at[40]); 
+   COMBA_STORE(C->dp[39]);
+   /* 40 */
+   COMBA_FORWARD;
+   MULADD(at[13], at[55]);    MULADD(at[14], at[54]);    MULADD(at[15], at[53]);    MULADD(at[16], at[52]);    MULADD(at[17], at[51]);    MULADD(at[18], at[50]);    MULADD(at[19], at[49]);    MULADD(at[20], at[48]);    MULADD(at[21], at[47]);    MULADD(at[22], at[46]);    MULADD(at[23], at[45]);    MULADD(at[24], at[44]);    MULADD(at[25], at[43]);    MULADD(at[26], at[42]);    MULADD(at[27], at[41]); 
+   COMBA_STORE(C->dp[40]);
+   /* 41 */
+   COMBA_FORWARD;
+   MULADD(at[14], at[55]);    MULADD(at[15], at[54]);    MULADD(at[16], at[53]);    MULADD(at[17], at[52]);    MULADD(at[18], at[51]);    MULADD(at[19], at[50]);    MULADD(at[20], at[49]);    MULADD(at[21], at[48]);    MULADD(at[22], at[47]);    MULADD(at[23], at[46]);    MULADD(at[24], at[45]);    MULADD(at[25], at[44]);    MULADD(at[26], at[43]);    MULADD(at[27], at[42]); 
+   COMBA_STORE(C->dp[41]);
+   /* 42 */
+   COMBA_FORWARD;
+   MULADD(at[15], at[55]);    MULADD(at[16], at[54]);    MULADD(at[17], at[53]);    MULADD(at[18], at[52]);    MULADD(at[19], at[51]);    MULADD(at[20], at[50]);    MULADD(at[21], at[49]);    MULADD(at[22], at[48]);    MULADD(at[23], at[47]);    MULADD(at[24], at[46]);    MULADD(at[25], at[45]);    MULADD(at[26], at[44]);    MULADD(at[27], at[43]); 
+   COMBA_STORE(C->dp[42]);
+   /* 43 */
+   COMBA_FORWARD;
+   MULADD(at[16], at[55]);    MULADD(at[17], at[54]);    MULADD(at[18], at[53]);    MULADD(at[19], at[52]);    MULADD(at[20], at[51]);    MULADD(at[21], at[50]);    MULADD(at[22], at[49]);    MULADD(at[23], at[48]);    MULADD(at[24], at[47]);    MULADD(at[25], at[46]);    MULADD(at[26], at[45]);    MULADD(at[27], at[44]); 
+   COMBA_STORE(C->dp[43]);
+   /* 44 */
+   COMBA_FORWARD;
+   MULADD(at[17], at[55]);    MULADD(at[18], at[54]);    MULADD(at[19], at[53]);    MULADD(at[20], at[52]);    MULADD(at[21], at[51]);    MULADD(at[22], at[50]);    MULADD(at[23], at[49]);    MULADD(at[24], at[48]);    MULADD(at[25], at[47]);    MULADD(at[26], at[46]);    MULADD(at[27], at[45]); 
+   COMBA_STORE(C->dp[44]);
+   /* 45 */
+   COMBA_FORWARD;
+   MULADD(at[18], at[55]);    MULADD(at[19], at[54]);    MULADD(at[20], at[53]);    MULADD(at[21], at[52]);    MULADD(at[22], at[51]);    MULADD(at[23], at[50]);    MULADD(at[24], at[49]);    MULADD(at[25], at[48]);    MULADD(at[26], at[47]);    MULADD(at[27], at[46]); 
+   COMBA_STORE(C->dp[45]);
+   /* 46 */
+   COMBA_FORWARD;
+   MULADD(at[19], at[55]);    MULADD(at[20], at[54]);    MULADD(at[21], at[53]);    MULADD(at[22], at[52]);    MULADD(at[23], at[51]);    MULADD(at[24], at[50]);    MULADD(at[25], at[49]);    MULADD(at[26], at[48]);    MULADD(at[27], at[47]); 
+   COMBA_STORE(C->dp[46]);
+   /* 47 */
+   COMBA_FORWARD;
+   MULADD(at[20], at[55]);    MULADD(at[21], at[54]);    MULADD(at[22], at[53]);    MULADD(at[23], at[52]);    MULADD(at[24], at[51]);    MULADD(at[25], at[50]);    MULADD(at[26], at[49]);    MULADD(at[27], at[48]); 
+   COMBA_STORE(C->dp[47]);
+   /* 48 */
+   COMBA_FORWARD;
+   MULADD(at[21], at[55]);    MULADD(at[22], at[54]);    MULADD(at[23], at[53]);    MULADD(at[24], at[52]);    MULADD(at[25], at[51]);    MULADD(at[26], at[50]);    MULADD(at[27], at[49]); 
+   COMBA_STORE(C->dp[48]);
+   /* 49 */
+   COMBA_FORWARD;
+   MULADD(at[22], at[55]);    MULADD(at[23], at[54]);    MULADD(at[24], at[53]);    MULADD(at[25], at[52]);    MULADD(at[26], at[51]);    MULADD(at[27], at[50]); 
+   COMBA_STORE(C->dp[49]);
+   /* 50 */
+   COMBA_FORWARD;
+   MULADD(at[23], at[55]);    MULADD(at[24], at[54]);    MULADD(at[25], at[53]);    MULADD(at[26], at[52]);    MULADD(at[27], at[51]); 
+   COMBA_STORE(C->dp[50]);
+   /* 51 */
+   COMBA_FORWARD;
+   MULADD(at[24], at[55]);    MULADD(at[25], at[54]);    MULADD(at[26], at[53]);    MULADD(at[27], at[52]); 
+   COMBA_STORE(C->dp[51]);
+   /* 52 */
+   COMBA_FORWARD;
+   MULADD(at[25], at[55]);    MULADD(at[26], at[54]);    MULADD(at[27], at[53]); 
+   COMBA_STORE(C->dp[52]);
+   /* 53 */
+   COMBA_FORWARD;
+   MULADD(at[26], at[55]);    MULADD(at[27], at[54]); 
+   COMBA_STORE(C->dp[53]);
+   /* 54 */
+   COMBA_FORWARD;
+   MULADD(at[27], at[55]); 
+   COMBA_STORE(C->dp[54]);
+   COMBA_STORE2(C->dp[55]);
+   C->used = 56;
+   C->sign = A->sign ^ B->sign;
+   fp_clamp(C);
+   COMBA_FINI;
+}
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_3.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_3.i
new file mode 100644
index 0000000..440291e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_3.i
@@ -0,0 +1,58 @@
+/* fp_mul_comba_3.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_MUL3
+void fp_mul_comba3(fp_int *A, fp_int *B, fp_int *C)
+{
+   fp_digit c0, c1, c2, at[6];
+
+   memcpy(at, A->dp, 3 * sizeof(fp_digit));
+   memcpy(at+3, B->dp, 3 * sizeof(fp_digit));
+   COMBA_START;
+
+   COMBA_CLEAR;
+   /* 0 */
+   MULADD(at[0], at[3]); 
+   COMBA_STORE(C->dp[0]);
+   /* 1 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[4]);    MULADD(at[1], at[3]); 
+   COMBA_STORE(C->dp[1]);
+   /* 2 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[5]);    MULADD(at[1], at[4]);    MULADD(at[2], at[3]); 
+   COMBA_STORE(C->dp[2]);
+   /* 3 */
+   COMBA_FORWARD;
+   MULADD(at[1], at[5]);    MULADD(at[2], at[4]); 
+   COMBA_STORE(C->dp[3]);
+   /* 4 */
+   COMBA_FORWARD;
+   MULADD(at[2], at[5]); 
+   COMBA_STORE(C->dp[4]);
+   COMBA_STORE2(C->dp[5]);
+   C->used = 6;
+   C->sign = A->sign ^ B->sign;
+   fp_clamp(C);
+   COMBA_FINI;
+}
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_32.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_32.i
new file mode 100644
index 0000000..905028d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_32.i
@@ -0,0 +1,304 @@
+/* fp_mul_comba_32.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_MUL32
+void fp_mul_comba32(fp_int *A, fp_int *B, fp_int *C)
+{
+   fp_digit c0, c1, c2, at[64];
+   int out_size;
+
+   out_size = A->used + B->used;
+   memcpy(at, A->dp, 32 * sizeof(fp_digit));
+   memcpy(at+32, B->dp, 32 * sizeof(fp_digit));
+   COMBA_START;
+
+   COMBA_CLEAR;
+   /* 0 */
+   MULADD(at[0], at[32]); 
+   COMBA_STORE(C->dp[0]);
+   /* 1 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[33]);    MULADD(at[1], at[32]); 
+   COMBA_STORE(C->dp[1]);
+   /* 2 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[34]);    MULADD(at[1], at[33]);    MULADD(at[2], at[32]); 
+   COMBA_STORE(C->dp[2]);
+   /* 3 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[35]);    MULADD(at[1], at[34]);    MULADD(at[2], at[33]);    MULADD(at[3], at[32]); 
+   COMBA_STORE(C->dp[3]);
+   /* 4 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[36]);    MULADD(at[1], at[35]);    MULADD(at[2], at[34]);    MULADD(at[3], at[33]);    MULADD(at[4], at[32]); 
+   COMBA_STORE(C->dp[4]);
+   /* 5 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[37]);    MULADD(at[1], at[36]);    MULADD(at[2], at[35]);    MULADD(at[3], at[34]);    MULADD(at[4], at[33]);    MULADD(at[5], at[32]); 
+   COMBA_STORE(C->dp[5]);
+   /* 6 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[38]);    MULADD(at[1], at[37]);    MULADD(at[2], at[36]);    MULADD(at[3], at[35]);    MULADD(at[4], at[34]);    MULADD(at[5], at[33]);    MULADD(at[6], at[32]); 
+   COMBA_STORE(C->dp[6]);
+   /* 7 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[39]);    MULADD(at[1], at[38]);    MULADD(at[2], at[37]);    MULADD(at[3], at[36]);    MULADD(at[4], at[35]);    MULADD(at[5], at[34]);    MULADD(at[6], at[33]);    MULADD(at[7], at[32]); 
+   COMBA_STORE(C->dp[7]);
+   /* 8 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[40]);    MULADD(at[1], at[39]);    MULADD(at[2], at[38]);    MULADD(at[3], at[37]);    MULADD(at[4], at[36]);    MULADD(at[5], at[35]);    MULADD(at[6], at[34]);    MULADD(at[7], at[33]);    MULADD(at[8], at[32]); 
+   COMBA_STORE(C->dp[8]);
+   /* 9 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[41]);    MULADD(at[1], at[40]);    MULADD(at[2], at[39]);    MULADD(at[3], at[38]);    MULADD(at[4], at[37]);    MULADD(at[5], at[36]);    MULADD(at[6], at[35]);    MULADD(at[7], at[34]);    MULADD(at[8], at[33]);    MULADD(at[9], at[32]); 
+   COMBA_STORE(C->dp[9]);
+   /* 10 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[42]);    MULADD(at[1], at[41]);    MULADD(at[2], at[40]);    MULADD(at[3], at[39]);    MULADD(at[4], at[38]);    MULADD(at[5], at[37]);    MULADD(at[6], at[36]);    MULADD(at[7], at[35]);    MULADD(at[8], at[34]);    MULADD(at[9], at[33]);    MULADD(at[10], at[32]); 
+   COMBA_STORE(C->dp[10]);
+   /* 11 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[43]);    MULADD(at[1], at[42]);    MULADD(at[2], at[41]);    MULADD(at[3], at[40]);    MULADD(at[4], at[39]);    MULADD(at[5], at[38]);    MULADD(at[6], at[37]);    MULADD(at[7], at[36]);    MULADD(at[8], at[35]);    MULADD(at[9], at[34]);    MULADD(at[10], at[33]);    MULADD(at[11], at[32]); 
+   COMBA_STORE(C->dp[11]);
+   /* 12 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[44]);    MULADD(at[1], at[43]);    MULADD(at[2], at[42]);    MULADD(at[3], at[41]);    MULADD(at[4], at[40]);    MULADD(at[5], at[39]);    MULADD(at[6], at[38]);    MULADD(at[7], at[37]);    MULADD(at[8], at[36]);    MULADD(at[9], at[35]);    MULADD(at[10], at[34]);    MULADD(at[11], at[33]);    MULADD(at[12], at[32]); 
+   COMBA_STORE(C->dp[12]);
+   /* 13 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[45]);    MULADD(at[1], at[44]);    MULADD(at[2], at[43]);    MULADD(at[3], at[42]);    MULADD(at[4], at[41]);    MULADD(at[5], at[40]);    MULADD(at[6], at[39]);    MULADD(at[7], at[38]);    MULADD(at[8], at[37]);    MULADD(at[9], at[36]);    MULADD(at[10], at[35]);    MULADD(at[11], at[34]);    MULADD(at[12], at[33]);    MULADD(at[13], at[32]); 
+   COMBA_STORE(C->dp[13]);
+   /* 14 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[46]);    MULADD(at[1], at[45]);    MULADD(at[2], at[44]);    MULADD(at[3], at[43]);    MULADD(at[4], at[42]);    MULADD(at[5], at[41]);    MULADD(at[6], at[40]);    MULADD(at[7], at[39]);    MULADD(at[8], at[38]);    MULADD(at[9], at[37]);    MULADD(at[10], at[36]);    MULADD(at[11], at[35]);    MULADD(at[12], at[34]);    MULADD(at[13], at[33]);    MULADD(at[14], at[32]); 
+   COMBA_STORE(C->dp[14]);
+   /* 15 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[47]);    MULADD(at[1], at[46]);    MULADD(at[2], at[45]);    MULADD(at[3], at[44]);    MULADD(at[4], at[43]);    MULADD(at[5], at[42]);    MULADD(at[6], at[41]);    MULADD(at[7], at[40]);    MULADD(at[8], at[39]);    MULADD(at[9], at[38]);    MULADD(at[10], at[37]);    MULADD(at[11], at[36]);    MULADD(at[12], at[35]);    MULADD(at[13], at[34]);    MULADD(at[14], at[33]);    MULADD(at[15], at[32]); 
+   COMBA_STORE(C->dp[15]);
+   /* 16 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[48]);    MULADD(at[1], at[47]);    MULADD(at[2], at[46]);    MULADD(at[3], at[45]);    MULADD(at[4], at[44]);    MULADD(at[5], at[43]);    MULADD(at[6], at[42]);    MULADD(at[7], at[41]);    MULADD(at[8], at[40]);    MULADD(at[9], at[39]);    MULADD(at[10], at[38]);    MULADD(at[11], at[37]);    MULADD(at[12], at[36]);    MULADD(at[13], at[35]);    MULADD(at[14], at[34]);    MULADD(at[15], at[33]);    MULADD(at[16], at[32]); 
+   COMBA_STORE(C->dp[16]);
+   /* 17 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[49]);    MULADD(at[1], at[48]);    MULADD(at[2], at[47]);    MULADD(at[3], at[46]);    MULADD(at[4], at[45]);    MULADD(at[5], at[44]);    MULADD(at[6], at[43]);    MULADD(at[7], at[42]);    MULADD(at[8], at[41]);    MULADD(at[9], at[40]);    MULADD(at[10], at[39]);    MULADD(at[11], at[38]);    MULADD(at[12], at[37]);    MULADD(at[13], at[36]);    MULADD(at[14], at[35]);    MULADD(at[15], at[34]);    MULADD(at[16], at[33]);    MULADD(at[17], at[32]); 
+   COMBA_STORE(C->dp[17]);
+   /* 18 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[50]);    MULADD(at[1], at[49]);    MULADD(at[2], at[48]);    MULADD(at[3], at[47]);    MULADD(at[4], at[46]);    MULADD(at[5], at[45]);    MULADD(at[6], at[44]);    MULADD(at[7], at[43]);    MULADD(at[8], at[42]);    MULADD(at[9], at[41]);    MULADD(at[10], at[40]);    MULADD(at[11], at[39]);    MULADD(at[12], at[38]);    MULADD(at[13], at[37]);    MULADD(at[14], at[36]);    MULADD(at[15], at[35]);    MULADD(at[16], at[34]);    MULADD(at[17], at[33]);    MULADD(at[18], at[32]); 
+   COMBA_STORE(C->dp[18]);
+   /* 19 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[51]);    MULADD(at[1], at[50]);    MULADD(at[2], at[49]);    MULADD(at[3], at[48]);    MULADD(at[4], at[47]);    MULADD(at[5], at[46]);    MULADD(at[6], at[45]);    MULADD(at[7], at[44]);    MULADD(at[8], at[43]);    MULADD(at[9], at[42]);    MULADD(at[10], at[41]);    MULADD(at[11], at[40]);    MULADD(at[12], at[39]);    MULADD(at[13], at[38]);    MULADD(at[14], at[37]);    MULADD(at[15], at[36]);    MULADD(at[16], at[35]);    MULADD(at[17], at[34]);    MULADD(at[18], at[33]);    MULADD(at[19], at[32]); 
+   COMBA_STORE(C->dp[19]);
+   /* 20 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[52]);    MULADD(at[1], at[51]);    MULADD(at[2], at[50]);    MULADD(at[3], at[49]);    MULADD(at[4], at[48]);    MULADD(at[5], at[47]);    MULADD(at[6], at[46]);    MULADD(at[7], at[45]);    MULADD(at[8], at[44]);    MULADD(at[9], at[43]);    MULADD(at[10], at[42]);    MULADD(at[11], at[41]);    MULADD(at[12], at[40]);    MULADD(at[13], at[39]);    MULADD(at[14], at[38]);    MULADD(at[15], at[37]);    MULADD(at[16], at[36]);    MULADD(at[17], at[35]);    MULADD(at[18], at[34]);    MULADD(at[19], at[33]);    MULADD(at[20], at[32]); 
+   COMBA_STORE(C->dp[20]);
+   /* 21 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[53]);    MULADD(at[1], at[52]);    MULADD(at[2], at[51]);    MULADD(at[3], at[50]);    MULADD(at[4], at[49]);    MULADD(at[5], at[48]);    MULADD(at[6], at[47]);    MULADD(at[7], at[46]);    MULADD(at[8], at[45]);    MULADD(at[9], at[44]);    MULADD(at[10], at[43]);    MULADD(at[11], at[42]);    MULADD(at[12], at[41]);    MULADD(at[13], at[40]);    MULADD(at[14], at[39]);    MULADD(at[15], at[38]);    MULADD(at[16], at[37]);    MULADD(at[17], at[36]);    MULADD(at[18], at[35]);    MULADD(at[19], at[34]);    MULADD(at[20], at[33]);    MULADD(at[21], at[32]); 
+   COMBA_STORE(C->dp[21]);
+   /* 22 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[54]);    MULADD(at[1], at[53]);    MULADD(at[2], at[52]);    MULADD(at[3], at[51]);    MULADD(at[4], at[50]);    MULADD(at[5], at[49]);    MULADD(at[6], at[48]);    MULADD(at[7], at[47]);    MULADD(at[8], at[46]);    MULADD(at[9], at[45]);    MULADD(at[10], at[44]);    MULADD(at[11], at[43]);    MULADD(at[12], at[42]);    MULADD(at[13], at[41]);    MULADD(at[14], at[40]);    MULADD(at[15], at[39]);    MULADD(at[16], at[38]);    MULADD(at[17], at[37]);    MULADD(at[18], at[36]);    MULADD(at[19], at[35]);    MULADD(at[20], at[34]);    MULADD(at[21], at[33]);    MULADD(at[22], at[32]); 
+   COMBA_STORE(C->dp[22]);
+   /* 23 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[55]);    MULADD(at[1], at[54]);    MULADD(at[2], at[53]);    MULADD(at[3], at[52]);    MULADD(at[4], at[51]);    MULADD(at[5], at[50]);    MULADD(at[6], at[49]);    MULADD(at[7], at[48]);    MULADD(at[8], at[47]);    MULADD(at[9], at[46]);    MULADD(at[10], at[45]);    MULADD(at[11], at[44]);    MULADD(at[12], at[43]);    MULADD(at[13], at[42]);    MULADD(at[14], at[41]);    MULADD(at[15], at[40]);    MULADD(at[16], at[39]);    MULADD(at[17], at[38]);    MULADD(at[18], at[37]);    MULADD(at[19], at[36]);    MULADD(at[20], at[35]);    MULADD(at[21], at[34]);    MULADD(at[22], at[33]);    MULADD(at[23], at[32]); 
+   COMBA_STORE(C->dp[23]);
+   /* 24 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[56]);    MULADD(at[1], at[55]);    MULADD(at[2], at[54]);    MULADD(at[3], at[53]);    MULADD(at[4], at[52]);    MULADD(at[5], at[51]);    MULADD(at[6], at[50]);    MULADD(at[7], at[49]);    MULADD(at[8], at[48]);    MULADD(at[9], at[47]);    MULADD(at[10], at[46]);    MULADD(at[11], at[45]);    MULADD(at[12], at[44]);    MULADD(at[13], at[43]);    MULADD(at[14], at[42]);    MULADD(at[15], at[41]);    MULADD(at[16], at[40]);    MULADD(at[17], at[39]);    MULADD(at[18], at[38]);    MULADD(at[19], at[37]);    MULADD(at[20], at[36]);    MULADD(at[21], at[35]);    MULADD(at[22], at[34]);    MULADD(at[23], at[33]);    MULADD(at[24], at[32]); 
+   COMBA_STORE(C->dp[24]);
+   /* 25 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[57]);    MULADD(at[1], at[56]);    MULADD(at[2], at[55]);    MULADD(at[3], at[54]);    MULADD(at[4], at[53]);    MULADD(at[5], at[52]);    MULADD(at[6], at[51]);    MULADD(at[7], at[50]);    MULADD(at[8], at[49]);    MULADD(at[9], at[48]);    MULADD(at[10], at[47]);    MULADD(at[11], at[46]);    MULADD(at[12], at[45]);    MULADD(at[13], at[44]);    MULADD(at[14], at[43]);    MULADD(at[15], at[42]);    MULADD(at[16], at[41]);    MULADD(at[17], at[40]);    MULADD(at[18], at[39]);    MULADD(at[19], at[38]);    MULADD(at[20], at[37]);    MULADD(at[21], at[36]);    MULADD(at[22], at[35]);    MULADD(at[23], at[34]);    MULADD(at[24], at[33]);    MULADD(at[25], at[32]); 
+   COMBA_STORE(C->dp[25]);
+   /* 26 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[58]);    MULADD(at[1], at[57]);    MULADD(at[2], at[56]);    MULADD(at[3], at[55]);    MULADD(at[4], at[54]);    MULADD(at[5], at[53]);    MULADD(at[6], at[52]);    MULADD(at[7], at[51]);    MULADD(at[8], at[50]);    MULADD(at[9], at[49]);    MULADD(at[10], at[48]);    MULADD(at[11], at[47]);    MULADD(at[12], at[46]);    MULADD(at[13], at[45]);    MULADD(at[14], at[44]);    MULADD(at[15], at[43]);    MULADD(at[16], at[42]);    MULADD(at[17], at[41]);    MULADD(at[18], at[40]);    MULADD(at[19], at[39]);    MULADD(at[20], at[38]);    MULADD(at[21], at[37]);    MULADD(at[22], at[36]);    MULADD(at[23], at[35]);    MULADD(at[24], at[34]);    MULADD(at[25], at[33]);    MULADD(at[26], at[32]); 
+   COMBA_STORE(C->dp[26]);
+   /* 27 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[59]);    MULADD(at[1], at[58]);    MULADD(at[2], at[57]);    MULADD(at[3], at[56]);    MULADD(at[4], at[55]);    MULADD(at[5], at[54]);    MULADD(at[6], at[53]);    MULADD(at[7], at[52]);    MULADD(at[8], at[51]);    MULADD(at[9], at[50]);    MULADD(at[10], at[49]);    MULADD(at[11], at[48]);    MULADD(at[12], at[47]);    MULADD(at[13], at[46]);    MULADD(at[14], at[45]);    MULADD(at[15], at[44]);    MULADD(at[16], at[43]);    MULADD(at[17], at[42]);    MULADD(at[18], at[41]);    MULADD(at[19], at[40]);    MULADD(at[20], at[39]);    MULADD(at[21], at[38]);    MULADD(at[22], at[37]);    MULADD(at[23], at[36]);    MULADD(at[24], at[35]);    MULADD(at[25], at[34]);    MULADD(at[26], at[33]);    MULADD(at[27], at[32]); 
+   COMBA_STORE(C->dp[27]);
+   /* 28 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[60]);    MULADD(at[1], at[59]);    MULADD(at[2], at[58]);    MULADD(at[3], at[57]);    MULADD(at[4], at[56]);    MULADD(at[5], at[55]);    MULADD(at[6], at[54]);    MULADD(at[7], at[53]);    MULADD(at[8], at[52]);    MULADD(at[9], at[51]);    MULADD(at[10], at[50]);    MULADD(at[11], at[49]);    MULADD(at[12], at[48]);    MULADD(at[13], at[47]);    MULADD(at[14], at[46]);    MULADD(at[15], at[45]);    MULADD(at[16], at[44]);    MULADD(at[17], at[43]);    MULADD(at[18], at[42]);    MULADD(at[19], at[41]);    MULADD(at[20], at[40]);    MULADD(at[21], at[39]);    MULADD(at[22], at[38]);    MULADD(at[23], at[37]);    MULADD(at[24], at[36]);    MULADD(at[25], at[35]);    MULADD(at[26], at[34]);    MULADD(at[27], at[33]);    MULADD(at[28], at[32]); 
+   COMBA_STORE(C->dp[28]);
+   /* 29 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[61]);    MULADD(at[1], at[60]);    MULADD(at[2], at[59]);    MULADD(at[3], at[58]);    MULADD(at[4], at[57]);    MULADD(at[5], at[56]);    MULADD(at[6], at[55]);    MULADD(at[7], at[54]);    MULADD(at[8], at[53]);    MULADD(at[9], at[52]);    MULADD(at[10], at[51]);    MULADD(at[11], at[50]);    MULADD(at[12], at[49]);    MULADD(at[13], at[48]);    MULADD(at[14], at[47]);    MULADD(at[15], at[46]);    MULADD(at[16], at[45]);    MULADD(at[17], at[44]);    MULADD(at[18], at[43]);    MULADD(at[19], at[42]);    MULADD(at[20], at[41]);    MULADD(at[21], at[40]);    MULADD(at[22], at[39]);    MULADD(at[23], at[38]);    MULADD(at[24], at[37]);    MULADD(at[25], at[36]);    MULADD(at[26], at[35]);    MULADD(at[27], at[34]);    MULADD(at[28], at[33]);    MULADD(at[29], at[32]); 
+   COMBA_STORE(C->dp[29]);
+   /* 30 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[62]);    MULADD(at[1], at[61]);    MULADD(at[2], at[60]);    MULADD(at[3], at[59]);    MULADD(at[4], at[58]);    MULADD(at[5], at[57]);    MULADD(at[6], at[56]);    MULADD(at[7], at[55]);    MULADD(at[8], at[54]);    MULADD(at[9], at[53]);    MULADD(at[10], at[52]);    MULADD(at[11], at[51]);    MULADD(at[12], at[50]);    MULADD(at[13], at[49]);    MULADD(at[14], at[48]);    MULADD(at[15], at[47]);    MULADD(at[16], at[46]);    MULADD(at[17], at[45]);    MULADD(at[18], at[44]);    MULADD(at[19], at[43]);    MULADD(at[20], at[42]);    MULADD(at[21], at[41]);    MULADD(at[22], at[40]);    MULADD(at[23], at[39]);    MULADD(at[24], at[38]);    MULADD(at[25], at[37]);    MULADD(at[26], at[36]);    MULADD(at[27], at[35]);    MULADD(at[28], at[34]);    MULADD(at[29], at[33]);    MULADD(at[30], at[32]); 
+   COMBA_STORE(C->dp[30]);
+   /* 31 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[63]);    MULADD(at[1], at[62]);    MULADD(at[2], at[61]);    MULADD(at[3], at[60]);    MULADD(at[4], at[59]);    MULADD(at[5], at[58]);    MULADD(at[6], at[57]);    MULADD(at[7], at[56]);    MULADD(at[8], at[55]);    MULADD(at[9], at[54]);    MULADD(at[10], at[53]);    MULADD(at[11], at[52]);    MULADD(at[12], at[51]);    MULADD(at[13], at[50]);    MULADD(at[14], at[49]);    MULADD(at[15], at[48]);    MULADD(at[16], at[47]);    MULADD(at[17], at[46]);    MULADD(at[18], at[45]);    MULADD(at[19], at[44]);    MULADD(at[20], at[43]);    MULADD(at[21], at[42]);    MULADD(at[22], at[41]);    MULADD(at[23], at[40]);    MULADD(at[24], at[39]);    MULADD(at[25], at[38]);    MULADD(at[26], at[37]);    MULADD(at[27], at[36]);    MULADD(at[28], at[35]);    MULADD(at[29], at[34]);    MULADD(at[30], at[33]);    MULADD(at[31], at[32]); 
+   COMBA_STORE(C->dp[31]);
+   /* 32 */
+   COMBA_FORWARD;
+   MULADD(at[1], at[63]);    MULADD(at[2], at[62]);    MULADD(at[3], at[61]);    MULADD(at[4], at[60]);    MULADD(at[5], at[59]);    MULADD(at[6], at[58]);    MULADD(at[7], at[57]);    MULADD(at[8], at[56]);    MULADD(at[9], at[55]);    MULADD(at[10], at[54]);    MULADD(at[11], at[53]);    MULADD(at[12], at[52]);    MULADD(at[13], at[51]);    MULADD(at[14], at[50]);    MULADD(at[15], at[49]);    MULADD(at[16], at[48]);    MULADD(at[17], at[47]);    MULADD(at[18], at[46]);    MULADD(at[19], at[45]);    MULADD(at[20], at[44]);    MULADD(at[21], at[43]);    MULADD(at[22], at[42]);    MULADD(at[23], at[41]);    MULADD(at[24], at[40]);    MULADD(at[25], at[39]);    MULADD(at[26], at[38]);    MULADD(at[27], at[37]);    MULADD(at[28], at[36]);    MULADD(at[29], at[35]);    MULADD(at[30], at[34]);    MULADD(at[31], at[33]); 
+   COMBA_STORE(C->dp[32]);
+   /* 33 */
+   COMBA_FORWARD;
+   MULADD(at[2], at[63]);    MULADD(at[3], at[62]);    MULADD(at[4], at[61]);    MULADD(at[5], at[60]);    MULADD(at[6], at[59]);    MULADD(at[7], at[58]);    MULADD(at[8], at[57]);    MULADD(at[9], at[56]);    MULADD(at[10], at[55]);    MULADD(at[11], at[54]);    MULADD(at[12], at[53]);    MULADD(at[13], at[52]);    MULADD(at[14], at[51]);    MULADD(at[15], at[50]);    MULADD(at[16], at[49]);    MULADD(at[17], at[48]);    MULADD(at[18], at[47]);    MULADD(at[19], at[46]);    MULADD(at[20], at[45]);    MULADD(at[21], at[44]);    MULADD(at[22], at[43]);    MULADD(at[23], at[42]);    MULADD(at[24], at[41]);    MULADD(at[25], at[40]);    MULADD(at[26], at[39]);    MULADD(at[27], at[38]);    MULADD(at[28], at[37]);    MULADD(at[29], at[36]);    MULADD(at[30], at[35]);    MULADD(at[31], at[34]); 
+   COMBA_STORE(C->dp[33]);
+   /* 34 */
+   COMBA_FORWARD;
+   MULADD(at[3], at[63]);    MULADD(at[4], at[62]);    MULADD(at[5], at[61]);    MULADD(at[6], at[60]);    MULADD(at[7], at[59]);    MULADD(at[8], at[58]);    MULADD(at[9], at[57]);    MULADD(at[10], at[56]);    MULADD(at[11], at[55]);    MULADD(at[12], at[54]);    MULADD(at[13], at[53]);    MULADD(at[14], at[52]);    MULADD(at[15], at[51]);    MULADD(at[16], at[50]);    MULADD(at[17], at[49]);    MULADD(at[18], at[48]);    MULADD(at[19], at[47]);    MULADD(at[20], at[46]);    MULADD(at[21], at[45]);    MULADD(at[22], at[44]);    MULADD(at[23], at[43]);    MULADD(at[24], at[42]);    MULADD(at[25], at[41]);    MULADD(at[26], at[40]);    MULADD(at[27], at[39]);    MULADD(at[28], at[38]);    MULADD(at[29], at[37]);    MULADD(at[30], at[36]);    MULADD(at[31], at[35]); 
+   COMBA_STORE(C->dp[34]);
+   /* 35 */
+   COMBA_FORWARD;
+   MULADD(at[4], at[63]);    MULADD(at[5], at[62]);    MULADD(at[6], at[61]);    MULADD(at[7], at[60]);    MULADD(at[8], at[59]);    MULADD(at[9], at[58]);    MULADD(at[10], at[57]);    MULADD(at[11], at[56]);    MULADD(at[12], at[55]);    MULADD(at[13], at[54]);    MULADD(at[14], at[53]);    MULADD(at[15], at[52]);    MULADD(at[16], at[51]);    MULADD(at[17], at[50]);    MULADD(at[18], at[49]);    MULADD(at[19], at[48]);    MULADD(at[20], at[47]);    MULADD(at[21], at[46]);    MULADD(at[22], at[45]);    MULADD(at[23], at[44]);    MULADD(at[24], at[43]);    MULADD(at[25], at[42]);    MULADD(at[26], at[41]);    MULADD(at[27], at[40]);    MULADD(at[28], at[39]);    MULADD(at[29], at[38]);    MULADD(at[30], at[37]);    MULADD(at[31], at[36]); 
+   COMBA_STORE(C->dp[35]);
+   /* 36 */
+   COMBA_FORWARD;
+   MULADD(at[5], at[63]);    MULADD(at[6], at[62]);    MULADD(at[7], at[61]);    MULADD(at[8], at[60]);    MULADD(at[9], at[59]);    MULADD(at[10], at[58]);    MULADD(at[11], at[57]);    MULADD(at[12], at[56]);    MULADD(at[13], at[55]);    MULADD(at[14], at[54]);    MULADD(at[15], at[53]);    MULADD(at[16], at[52]);    MULADD(at[17], at[51]);    MULADD(at[18], at[50]);    MULADD(at[19], at[49]);    MULADD(at[20], at[48]);    MULADD(at[21], at[47]);    MULADD(at[22], at[46]);    MULADD(at[23], at[45]);    MULADD(at[24], at[44]);    MULADD(at[25], at[43]);    MULADD(at[26], at[42]);    MULADD(at[27], at[41]);    MULADD(at[28], at[40]);    MULADD(at[29], at[39]);    MULADD(at[30], at[38]);    MULADD(at[31], at[37]); 
+   COMBA_STORE(C->dp[36]);
+   /* 37 */
+   COMBA_FORWARD;
+   MULADD(at[6], at[63]);    MULADD(at[7], at[62]);    MULADD(at[8], at[61]);    MULADD(at[9], at[60]);    MULADD(at[10], at[59]);    MULADD(at[11], at[58]);    MULADD(at[12], at[57]);    MULADD(at[13], at[56]);    MULADD(at[14], at[55]);    MULADD(at[15], at[54]);    MULADD(at[16], at[53]);    MULADD(at[17], at[52]);    MULADD(at[18], at[51]);    MULADD(at[19], at[50]);    MULADD(at[20], at[49]);    MULADD(at[21], at[48]);    MULADD(at[22], at[47]);    MULADD(at[23], at[46]);    MULADD(at[24], at[45]);    MULADD(at[25], at[44]);    MULADD(at[26], at[43]);    MULADD(at[27], at[42]);    MULADD(at[28], at[41]);    MULADD(at[29], at[40]);    MULADD(at[30], at[39]);    MULADD(at[31], at[38]); 
+   COMBA_STORE(C->dp[37]);
+   /* 38 */
+   COMBA_FORWARD;
+   MULADD(at[7], at[63]);    MULADD(at[8], at[62]);    MULADD(at[9], at[61]);    MULADD(at[10], at[60]);    MULADD(at[11], at[59]);    MULADD(at[12], at[58]);    MULADD(at[13], at[57]);    MULADD(at[14], at[56]);    MULADD(at[15], at[55]);    MULADD(at[16], at[54]);    MULADD(at[17], at[53]);    MULADD(at[18], at[52]);    MULADD(at[19], at[51]);    MULADD(at[20], at[50]);    MULADD(at[21], at[49]);    MULADD(at[22], at[48]);    MULADD(at[23], at[47]);    MULADD(at[24], at[46]);    MULADD(at[25], at[45]);    MULADD(at[26], at[44]);    MULADD(at[27], at[43]);    MULADD(at[28], at[42]);    MULADD(at[29], at[41]);    MULADD(at[30], at[40]);    MULADD(at[31], at[39]); 
+   COMBA_STORE(C->dp[38]);
+
+   /* early out at 40 digits, 40*32==1280, or two 640 bit operands */
+   if (out_size <= 40) { COMBA_STORE2(C->dp[39]); C->used = 40; C->sign = A->sign ^ B->sign; fp_clamp(C); COMBA_FINI; return; }
+
+   /* 39 */
+   COMBA_FORWARD;
+   MULADD(at[8], at[63]);    MULADD(at[9], at[62]);    MULADD(at[10], at[61]);    MULADD(at[11], at[60]);    MULADD(at[12], at[59]);    MULADD(at[13], at[58]);    MULADD(at[14], at[57]);    MULADD(at[15], at[56]);    MULADD(at[16], at[55]);    MULADD(at[17], at[54]);    MULADD(at[18], at[53]);    MULADD(at[19], at[52]);    MULADD(at[20], at[51]);    MULADD(at[21], at[50]);    MULADD(at[22], at[49]);    MULADD(at[23], at[48]);    MULADD(at[24], at[47]);    MULADD(at[25], at[46]);    MULADD(at[26], at[45]);    MULADD(at[27], at[44]);    MULADD(at[28], at[43]);    MULADD(at[29], at[42]);    MULADD(at[30], at[41]);    MULADD(at[31], at[40]); 
+   COMBA_STORE(C->dp[39]);
+   /* 40 */
+   COMBA_FORWARD;
+   MULADD(at[9], at[63]);    MULADD(at[10], at[62]);    MULADD(at[11], at[61]);    MULADD(at[12], at[60]);    MULADD(at[13], at[59]);    MULADD(at[14], at[58]);    MULADD(at[15], at[57]);    MULADD(at[16], at[56]);    MULADD(at[17], at[55]);    MULADD(at[18], at[54]);    MULADD(at[19], at[53]);    MULADD(at[20], at[52]);    MULADD(at[21], at[51]);    MULADD(at[22], at[50]);    MULADD(at[23], at[49]);    MULADD(at[24], at[48]);    MULADD(at[25], at[47]);    MULADD(at[26], at[46]);    MULADD(at[27], at[45]);    MULADD(at[28], at[44]);    MULADD(at[29], at[43]);    MULADD(at[30], at[42]);    MULADD(at[31], at[41]); 
+   COMBA_STORE(C->dp[40]);
+   /* 41 */
+   COMBA_FORWARD;
+   MULADD(at[10], at[63]);    MULADD(at[11], at[62]);    MULADD(at[12], at[61]);    MULADD(at[13], at[60]);    MULADD(at[14], at[59]);    MULADD(at[15], at[58]);    MULADD(at[16], at[57]);    MULADD(at[17], at[56]);    MULADD(at[18], at[55]);    MULADD(at[19], at[54]);    MULADD(at[20], at[53]);    MULADD(at[21], at[52]);    MULADD(at[22], at[51]);    MULADD(at[23], at[50]);    MULADD(at[24], at[49]);    MULADD(at[25], at[48]);    MULADD(at[26], at[47]);    MULADD(at[27], at[46]);    MULADD(at[28], at[45]);    MULADD(at[29], at[44]);    MULADD(at[30], at[43]);    MULADD(at[31], at[42]); 
+   COMBA_STORE(C->dp[41]);
+   /* 42 */
+   COMBA_FORWARD;
+   MULADD(at[11], at[63]);    MULADD(at[12], at[62]);    MULADD(at[13], at[61]);    MULADD(at[14], at[60]);    MULADD(at[15], at[59]);    MULADD(at[16], at[58]);    MULADD(at[17], at[57]);    MULADD(at[18], at[56]);    MULADD(at[19], at[55]);    MULADD(at[20], at[54]);    MULADD(at[21], at[53]);    MULADD(at[22], at[52]);    MULADD(at[23], at[51]);    MULADD(at[24], at[50]);    MULADD(at[25], at[49]);    MULADD(at[26], at[48]);    MULADD(at[27], at[47]);    MULADD(at[28], at[46]);    MULADD(at[29], at[45]);    MULADD(at[30], at[44]);    MULADD(at[31], at[43]); 
+   COMBA_STORE(C->dp[42]);
+   /* 43 */
+   COMBA_FORWARD;
+   MULADD(at[12], at[63]);    MULADD(at[13], at[62]);    MULADD(at[14], at[61]);    MULADD(at[15], at[60]);    MULADD(at[16], at[59]);    MULADD(at[17], at[58]);    MULADD(at[18], at[57]);    MULADD(at[19], at[56]);    MULADD(at[20], at[55]);    MULADD(at[21], at[54]);    MULADD(at[22], at[53]);    MULADD(at[23], at[52]);    MULADD(at[24], at[51]);    MULADD(at[25], at[50]);    MULADD(at[26], at[49]);    MULADD(at[27], at[48]);    MULADD(at[28], at[47]);    MULADD(at[29], at[46]);    MULADD(at[30], at[45]);    MULADD(at[31], at[44]); 
+   COMBA_STORE(C->dp[43]);
+   /* 44 */
+   COMBA_FORWARD;
+   MULADD(at[13], at[63]);    MULADD(at[14], at[62]);    MULADD(at[15], at[61]);    MULADD(at[16], at[60]);    MULADD(at[17], at[59]);    MULADD(at[18], at[58]);    MULADD(at[19], at[57]);    MULADD(at[20], at[56]);    MULADD(at[21], at[55]);    MULADD(at[22], at[54]);    MULADD(at[23], at[53]);    MULADD(at[24], at[52]);    MULADD(at[25], at[51]);    MULADD(at[26], at[50]);    MULADD(at[27], at[49]);    MULADD(at[28], at[48]);    MULADD(at[29], at[47]);    MULADD(at[30], at[46]);    MULADD(at[31], at[45]); 
+   COMBA_STORE(C->dp[44]);
+   /* 45 */
+   COMBA_FORWARD;
+   MULADD(at[14], at[63]);    MULADD(at[15], at[62]);    MULADD(at[16], at[61]);    MULADD(at[17], at[60]);    MULADD(at[18], at[59]);    MULADD(at[19], at[58]);    MULADD(at[20], at[57]);    MULADD(at[21], at[56]);    MULADD(at[22], at[55]);    MULADD(at[23], at[54]);    MULADD(at[24], at[53]);    MULADD(at[25], at[52]);    MULADD(at[26], at[51]);    MULADD(at[27], at[50]);    MULADD(at[28], at[49]);    MULADD(at[29], at[48]);    MULADD(at[30], at[47]);    MULADD(at[31], at[46]); 
+   COMBA_STORE(C->dp[45]);
+   /* 46 */
+   COMBA_FORWARD;
+   MULADD(at[15], at[63]);    MULADD(at[16], at[62]);    MULADD(at[17], at[61]);    MULADD(at[18], at[60]);    MULADD(at[19], at[59]);    MULADD(at[20], at[58]);    MULADD(at[21], at[57]);    MULADD(at[22], at[56]);    MULADD(at[23], at[55]);    MULADD(at[24], at[54]);    MULADD(at[25], at[53]);    MULADD(at[26], at[52]);    MULADD(at[27], at[51]);    MULADD(at[28], at[50]);    MULADD(at[29], at[49]);    MULADD(at[30], at[48]);    MULADD(at[31], at[47]); 
+   COMBA_STORE(C->dp[46]);
+
+   /* early out at 48 digits, 48*32==1536, or two 768 bit operands */
+   if (out_size <= 48) { COMBA_STORE2(C->dp[47]); C->used = 48; C->sign = A->sign ^ B->sign; fp_clamp(C); COMBA_FINI; return; }
+
+   /* 47 */
+   COMBA_FORWARD;
+   MULADD(at[16], at[63]);    MULADD(at[17], at[62]);    MULADD(at[18], at[61]);    MULADD(at[19], at[60]);    MULADD(at[20], at[59]);    MULADD(at[21], at[58]);    MULADD(at[22], at[57]);    MULADD(at[23], at[56]);    MULADD(at[24], at[55]);    MULADD(at[25], at[54]);    MULADD(at[26], at[53]);    MULADD(at[27], at[52]);    MULADD(at[28], at[51]);    MULADD(at[29], at[50]);    MULADD(at[30], at[49]);    MULADD(at[31], at[48]); 
+   COMBA_STORE(C->dp[47]);
+   /* 48 */
+   COMBA_FORWARD;
+   MULADD(at[17], at[63]);    MULADD(at[18], at[62]);    MULADD(at[19], at[61]);    MULADD(at[20], at[60]);    MULADD(at[21], at[59]);    MULADD(at[22], at[58]);    MULADD(at[23], at[57]);    MULADD(at[24], at[56]);    MULADD(at[25], at[55]);    MULADD(at[26], at[54]);    MULADD(at[27], at[53]);    MULADD(at[28], at[52]);    MULADD(at[29], at[51]);    MULADD(at[30], at[50]);    MULADD(at[31], at[49]); 
+   COMBA_STORE(C->dp[48]);
+   /* 49 */
+   COMBA_FORWARD;
+   MULADD(at[18], at[63]);    MULADD(at[19], at[62]);    MULADD(at[20], at[61]);    MULADD(at[21], at[60]);    MULADD(at[22], at[59]);    MULADD(at[23], at[58]);    MULADD(at[24], at[57]);    MULADD(at[25], at[56]);    MULADD(at[26], at[55]);    MULADD(at[27], at[54]);    MULADD(at[28], at[53]);    MULADD(at[29], at[52]);    MULADD(at[30], at[51]);    MULADD(at[31], at[50]); 
+   COMBA_STORE(C->dp[49]);
+   /* 50 */
+   COMBA_FORWARD;
+   MULADD(at[19], at[63]);    MULADD(at[20], at[62]);    MULADD(at[21], at[61]);    MULADD(at[22], at[60]);    MULADD(at[23], at[59]);    MULADD(at[24], at[58]);    MULADD(at[25], at[57]);    MULADD(at[26], at[56]);    MULADD(at[27], at[55]);    MULADD(at[28], at[54]);    MULADD(at[29], at[53]);    MULADD(at[30], at[52]);    MULADD(at[31], at[51]); 
+   COMBA_STORE(C->dp[50]);
+   /* 51 */
+   COMBA_FORWARD;
+   MULADD(at[20], at[63]);    MULADD(at[21], at[62]);    MULADD(at[22], at[61]);    MULADD(at[23], at[60]);    MULADD(at[24], at[59]);    MULADD(at[25], at[58]);    MULADD(at[26], at[57]);    MULADD(at[27], at[56]);    MULADD(at[28], at[55]);    MULADD(at[29], at[54]);    MULADD(at[30], at[53]);    MULADD(at[31], at[52]); 
+   COMBA_STORE(C->dp[51]);
+   /* 52 */
+   COMBA_FORWARD;
+   MULADD(at[21], at[63]);    MULADD(at[22], at[62]);    MULADD(at[23], at[61]);    MULADD(at[24], at[60]);    MULADD(at[25], at[59]);    MULADD(at[26], at[58]);    MULADD(at[27], at[57]);    MULADD(at[28], at[56]);    MULADD(at[29], at[55]);    MULADD(at[30], at[54]);    MULADD(at[31], at[53]); 
+   COMBA_STORE(C->dp[52]);
+   /* 53 */
+   COMBA_FORWARD;
+   MULADD(at[22], at[63]);    MULADD(at[23], at[62]);    MULADD(at[24], at[61]);    MULADD(at[25], at[60]);    MULADD(at[26], at[59]);    MULADD(at[27], at[58]);    MULADD(at[28], at[57]);    MULADD(at[29], at[56]);    MULADD(at[30], at[55]);    MULADD(at[31], at[54]); 
+   COMBA_STORE(C->dp[53]);
+   /* 54 */
+   COMBA_FORWARD;
+   MULADD(at[23], at[63]);    MULADD(at[24], at[62]);    MULADD(at[25], at[61]);    MULADD(at[26], at[60]);    MULADD(at[27], at[59]);    MULADD(at[28], at[58]);    MULADD(at[29], at[57]);    MULADD(at[30], at[56]);    MULADD(at[31], at[55]); 
+   COMBA_STORE(C->dp[54]);
+
+   /* early out at 56 digits, 56*32==1792, or two 896 bit operands */
+   if (out_size <= 56) { COMBA_STORE2(C->dp[55]); C->used = 56; C->sign = A->sign ^ B->sign; fp_clamp(C); COMBA_FINI; return; }
+
+   /* 55 */
+   COMBA_FORWARD;
+   MULADD(at[24], at[63]);    MULADD(at[25], at[62]);    MULADD(at[26], at[61]);    MULADD(at[27], at[60]);    MULADD(at[28], at[59]);    MULADD(at[29], at[58]);    MULADD(at[30], at[57]);    MULADD(at[31], at[56]); 
+   COMBA_STORE(C->dp[55]);
+   /* 56 */
+   COMBA_FORWARD;
+   MULADD(at[25], at[63]);    MULADD(at[26], at[62]);    MULADD(at[27], at[61]);    MULADD(at[28], at[60]);    MULADD(at[29], at[59]);    MULADD(at[30], at[58]);    MULADD(at[31], at[57]); 
+   COMBA_STORE(C->dp[56]);
+   /* 57 */
+   COMBA_FORWARD;
+   MULADD(at[26], at[63]);    MULADD(at[27], at[62]);    MULADD(at[28], at[61]);    MULADD(at[29], at[60]);    MULADD(at[30], at[59]);    MULADD(at[31], at[58]); 
+   COMBA_STORE(C->dp[57]);
+   /* 58 */
+   COMBA_FORWARD;
+   MULADD(at[27], at[63]);    MULADD(at[28], at[62]);    MULADD(at[29], at[61]);    MULADD(at[30], at[60]);    MULADD(at[31], at[59]); 
+   COMBA_STORE(C->dp[58]);
+   /* 59 */
+   COMBA_FORWARD;
+   MULADD(at[28], at[63]);    MULADD(at[29], at[62]);    MULADD(at[30], at[61]);    MULADD(at[31], at[60]); 
+   COMBA_STORE(C->dp[59]);
+   /* 60 */
+   COMBA_FORWARD;
+   MULADD(at[29], at[63]);    MULADD(at[30], at[62]);    MULADD(at[31], at[61]); 
+   COMBA_STORE(C->dp[60]);
+   /* 61 */
+   COMBA_FORWARD;
+   MULADD(at[30], at[63]);    MULADD(at[31], at[62]); 
+   COMBA_STORE(C->dp[61]);
+   /* 62 */
+   COMBA_FORWARD;
+   MULADD(at[31], at[63]); 
+   COMBA_STORE(C->dp[62]);
+   COMBA_STORE2(C->dp[63]);
+   C->used = 64;
+   C->sign = A->sign ^ B->sign;
+   fp_clamp(C);
+   COMBA_FINI;
+}
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_4.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_4.i
new file mode 100644
index 0000000..e981eb1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_4.i
@@ -0,0 +1,66 @@
+/* fp_mul_comba_4.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_MUL4
+void fp_mul_comba4(fp_int *A, fp_int *B, fp_int *C)
+{
+   fp_digit c0, c1, c2, at[8];
+
+   memcpy(at, A->dp, 4 * sizeof(fp_digit));
+   memcpy(at+4, B->dp, 4 * sizeof(fp_digit));
+   COMBA_START;
+
+   COMBA_CLEAR;
+   /* 0 */
+   MULADD(at[0], at[4]); 
+   COMBA_STORE(C->dp[0]);
+   /* 1 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[5]);    MULADD(at[1], at[4]); 
+   COMBA_STORE(C->dp[1]);
+   /* 2 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[6]);    MULADD(at[1], at[5]);    MULADD(at[2], at[4]); 
+   COMBA_STORE(C->dp[2]);
+   /* 3 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[7]);    MULADD(at[1], at[6]);    MULADD(at[2], at[5]);    MULADD(at[3], at[4]); 
+   COMBA_STORE(C->dp[3]);
+   /* 4 */
+   COMBA_FORWARD;
+   MULADD(at[1], at[7]);    MULADD(at[2], at[6]);    MULADD(at[3], at[5]); 
+   COMBA_STORE(C->dp[4]);
+   /* 5 */
+   COMBA_FORWARD;
+   MULADD(at[2], at[7]);    MULADD(at[3], at[6]); 
+   COMBA_STORE(C->dp[5]);
+   /* 6 */
+   COMBA_FORWARD;
+   MULADD(at[3], at[7]); 
+   COMBA_STORE(C->dp[6]);
+   COMBA_STORE2(C->dp[7]);
+   C->used = 8;
+   C->sign = A->sign ^ B->sign;
+   fp_clamp(C);
+   COMBA_FINI;
+}
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_48.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_48.i
new file mode 100644
index 0000000..79e43b8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_48.i
@@ -0,0 +1,418 @@
+/* fp_mul_comba_48.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_MUL48
+void fp_mul_comba48(fp_int *A, fp_int *B, fp_int *C)
+{
+   fp_digit c0, c1, c2, at[96];
+
+   memcpy(at, A->dp, 48 * sizeof(fp_digit));
+   memcpy(at+48, B->dp, 48 * sizeof(fp_digit));
+   COMBA_START;
+
+   COMBA_CLEAR;
+   /* 0 */
+   MULADD(at[0], at[48]); 
+   COMBA_STORE(C->dp[0]);
+   /* 1 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[49]);    MULADD(at[1], at[48]); 
+   COMBA_STORE(C->dp[1]);
+   /* 2 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[50]);    MULADD(at[1], at[49]);    MULADD(at[2], at[48]); 
+   COMBA_STORE(C->dp[2]);
+   /* 3 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[51]);    MULADD(at[1], at[50]);    MULADD(at[2], at[49]);    MULADD(at[3], at[48]); 
+   COMBA_STORE(C->dp[3]);
+   /* 4 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[52]);    MULADD(at[1], at[51]);    MULADD(at[2], at[50]);    MULADD(at[3], at[49]);    MULADD(at[4], at[48]); 
+   COMBA_STORE(C->dp[4]);
+   /* 5 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[53]);    MULADD(at[1], at[52]);    MULADD(at[2], at[51]);    MULADD(at[3], at[50]);    MULADD(at[4], at[49]);    MULADD(at[5], at[48]); 
+   COMBA_STORE(C->dp[5]);
+   /* 6 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[54]);    MULADD(at[1], at[53]);    MULADD(at[2], at[52]);    MULADD(at[3], at[51]);    MULADD(at[4], at[50]);    MULADD(at[5], at[49]);    MULADD(at[6], at[48]); 
+   COMBA_STORE(C->dp[6]);
+   /* 7 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[55]);    MULADD(at[1], at[54]);    MULADD(at[2], at[53]);    MULADD(at[3], at[52]);    MULADD(at[4], at[51]);    MULADD(at[5], at[50]);    MULADD(at[6], at[49]);    MULADD(at[7], at[48]); 
+   COMBA_STORE(C->dp[7]);
+   /* 8 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[56]);    MULADD(at[1], at[55]);    MULADD(at[2], at[54]);    MULADD(at[3], at[53]);    MULADD(at[4], at[52]);    MULADD(at[5], at[51]);    MULADD(at[6], at[50]);    MULADD(at[7], at[49]);    MULADD(at[8], at[48]); 
+   COMBA_STORE(C->dp[8]);
+   /* 9 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[57]);    MULADD(at[1], at[56]);    MULADD(at[2], at[55]);    MULADD(at[3], at[54]);    MULADD(at[4], at[53]);    MULADD(at[5], at[52]);    MULADD(at[6], at[51]);    MULADD(at[7], at[50]);    MULADD(at[8], at[49]);    MULADD(at[9], at[48]); 
+   COMBA_STORE(C->dp[9]);
+   /* 10 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[58]);    MULADD(at[1], at[57]);    MULADD(at[2], at[56]);    MULADD(at[3], at[55]);    MULADD(at[4], at[54]);    MULADD(at[5], at[53]);    MULADD(at[6], at[52]);    MULADD(at[7], at[51]);    MULADD(at[8], at[50]);    MULADD(at[9], at[49]);    MULADD(at[10], at[48]); 
+   COMBA_STORE(C->dp[10]);
+   /* 11 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[59]);    MULADD(at[1], at[58]);    MULADD(at[2], at[57]);    MULADD(at[3], at[56]);    MULADD(at[4], at[55]);    MULADD(at[5], at[54]);    MULADD(at[6], at[53]);    MULADD(at[7], at[52]);    MULADD(at[8], at[51]);    MULADD(at[9], at[50]);    MULADD(at[10], at[49]);    MULADD(at[11], at[48]); 
+   COMBA_STORE(C->dp[11]);
+   /* 12 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[60]);    MULADD(at[1], at[59]);    MULADD(at[2], at[58]);    MULADD(at[3], at[57]);    MULADD(at[4], at[56]);    MULADD(at[5], at[55]);    MULADD(at[6], at[54]);    MULADD(at[7], at[53]);    MULADD(at[8], at[52]);    MULADD(at[9], at[51]);    MULADD(at[10], at[50]);    MULADD(at[11], at[49]);    MULADD(at[12], at[48]); 
+   COMBA_STORE(C->dp[12]);
+   /* 13 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[61]);    MULADD(at[1], at[60]);    MULADD(at[2], at[59]);    MULADD(at[3], at[58]);    MULADD(at[4], at[57]);    MULADD(at[5], at[56]);    MULADD(at[6], at[55]);    MULADD(at[7], at[54]);    MULADD(at[8], at[53]);    MULADD(at[9], at[52]);    MULADD(at[10], at[51]);    MULADD(at[11], at[50]);    MULADD(at[12], at[49]);    MULADD(at[13], at[48]); 
+   COMBA_STORE(C->dp[13]);
+   /* 14 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[62]);    MULADD(at[1], at[61]);    MULADD(at[2], at[60]);    MULADD(at[3], at[59]);    MULADD(at[4], at[58]);    MULADD(at[5], at[57]);    MULADD(at[6], at[56]);    MULADD(at[7], at[55]);    MULADD(at[8], at[54]);    MULADD(at[9], at[53]);    MULADD(at[10], at[52]);    MULADD(at[11], at[51]);    MULADD(at[12], at[50]);    MULADD(at[13], at[49]);    MULADD(at[14], at[48]); 
+   COMBA_STORE(C->dp[14]);
+   /* 15 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[63]);    MULADD(at[1], at[62]);    MULADD(at[2], at[61]);    MULADD(at[3], at[60]);    MULADD(at[4], at[59]);    MULADD(at[5], at[58]);    MULADD(at[6], at[57]);    MULADD(at[7], at[56]);    MULADD(at[8], at[55]);    MULADD(at[9], at[54]);    MULADD(at[10], at[53]);    MULADD(at[11], at[52]);    MULADD(at[12], at[51]);    MULADD(at[13], at[50]);    MULADD(at[14], at[49]);    MULADD(at[15], at[48]); 
+   COMBA_STORE(C->dp[15]);
+   /* 16 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[64]);    MULADD(at[1], at[63]);    MULADD(at[2], at[62]);    MULADD(at[3], at[61]);    MULADD(at[4], at[60]);    MULADD(at[5], at[59]);    MULADD(at[6], at[58]);    MULADD(at[7], at[57]);    MULADD(at[8], at[56]);    MULADD(at[9], at[55]);    MULADD(at[10], at[54]);    MULADD(at[11], at[53]);    MULADD(at[12], at[52]);    MULADD(at[13], at[51]);    MULADD(at[14], at[50]);    MULADD(at[15], at[49]);    MULADD(at[16], at[48]); 
+   COMBA_STORE(C->dp[16]);
+   /* 17 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[65]);    MULADD(at[1], at[64]);    MULADD(at[2], at[63]);    MULADD(at[3], at[62]);    MULADD(at[4], at[61]);    MULADD(at[5], at[60]);    MULADD(at[6], at[59]);    MULADD(at[7], at[58]);    MULADD(at[8], at[57]);    MULADD(at[9], at[56]);    MULADD(at[10], at[55]);    MULADD(at[11], at[54]);    MULADD(at[12], at[53]);    MULADD(at[13], at[52]);    MULADD(at[14], at[51]);    MULADD(at[15], at[50]);    MULADD(at[16], at[49]);    MULADD(at[17], at[48]); 
+   COMBA_STORE(C->dp[17]);
+   /* 18 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[66]);    MULADD(at[1], at[65]);    MULADD(at[2], at[64]);    MULADD(at[3], at[63]);    MULADD(at[4], at[62]);    MULADD(at[5], at[61]);    MULADD(at[6], at[60]);    MULADD(at[7], at[59]);    MULADD(at[8], at[58]);    MULADD(at[9], at[57]);    MULADD(at[10], at[56]);    MULADD(at[11], at[55]);    MULADD(at[12], at[54]);    MULADD(at[13], at[53]);    MULADD(at[14], at[52]);    MULADD(at[15], at[51]);    MULADD(at[16], at[50]);    MULADD(at[17], at[49]);    MULADD(at[18], at[48]); 
+   COMBA_STORE(C->dp[18]);
+   /* 19 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[67]);    MULADD(at[1], at[66]);    MULADD(at[2], at[65]);    MULADD(at[3], at[64]);    MULADD(at[4], at[63]);    MULADD(at[5], at[62]);    MULADD(at[6], at[61]);    MULADD(at[7], at[60]);    MULADD(at[8], at[59]);    MULADD(at[9], at[58]);    MULADD(at[10], at[57]);    MULADD(at[11], at[56]);    MULADD(at[12], at[55]);    MULADD(at[13], at[54]);    MULADD(at[14], at[53]);    MULADD(at[15], at[52]);    MULADD(at[16], at[51]);    MULADD(at[17], at[50]);    MULADD(at[18], at[49]);    MULADD(at[19], at[48]); 
+   COMBA_STORE(C->dp[19]);
+   /* 20 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[68]);    MULADD(at[1], at[67]);    MULADD(at[2], at[66]);    MULADD(at[3], at[65]);    MULADD(at[4], at[64]);    MULADD(at[5], at[63]);    MULADD(at[6], at[62]);    MULADD(at[7], at[61]);    MULADD(at[8], at[60]);    MULADD(at[9], at[59]);    MULADD(at[10], at[58]);    MULADD(at[11], at[57]);    MULADD(at[12], at[56]);    MULADD(at[13], at[55]);    MULADD(at[14], at[54]);    MULADD(at[15], at[53]);    MULADD(at[16], at[52]);    MULADD(at[17], at[51]);    MULADD(at[18], at[50]);    MULADD(at[19], at[49]);    MULADD(at[20], at[48]); 
+   COMBA_STORE(C->dp[20]);
+   /* 21 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[69]);    MULADD(at[1], at[68]);    MULADD(at[2], at[67]);    MULADD(at[3], at[66]);    MULADD(at[4], at[65]);    MULADD(at[5], at[64]);    MULADD(at[6], at[63]);    MULADD(at[7], at[62]);    MULADD(at[8], at[61]);    MULADD(at[9], at[60]);    MULADD(at[10], at[59]);    MULADD(at[11], at[58]);    MULADD(at[12], at[57]);    MULADD(at[13], at[56]);    MULADD(at[14], at[55]);    MULADD(at[15], at[54]);    MULADD(at[16], at[53]);    MULADD(at[17], at[52]);    MULADD(at[18], at[51]);    MULADD(at[19], at[50]);    MULADD(at[20], at[49]);    MULADD(at[21], at[48]); 
+   COMBA_STORE(C->dp[21]);
+   /* 22 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[70]);    MULADD(at[1], at[69]);    MULADD(at[2], at[68]);    MULADD(at[3], at[67]);    MULADD(at[4], at[66]);    MULADD(at[5], at[65]);    MULADD(at[6], at[64]);    MULADD(at[7], at[63]);    MULADD(at[8], at[62]);    MULADD(at[9], at[61]);    MULADD(at[10], at[60]);    MULADD(at[11], at[59]);    MULADD(at[12], at[58]);    MULADD(at[13], at[57]);    MULADD(at[14], at[56]);    MULADD(at[15], at[55]);    MULADD(at[16], at[54]);    MULADD(at[17], at[53]);    MULADD(at[18], at[52]);    MULADD(at[19], at[51]);    MULADD(at[20], at[50]);    MULADD(at[21], at[49]);    MULADD(at[22], at[48]); 
+   COMBA_STORE(C->dp[22]);
+   /* 23 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[71]);    MULADD(at[1], at[70]);    MULADD(at[2], at[69]);    MULADD(at[3], at[68]);    MULADD(at[4], at[67]);    MULADD(at[5], at[66]);    MULADD(at[6], at[65]);    MULADD(at[7], at[64]);    MULADD(at[8], at[63]);    MULADD(at[9], at[62]);    MULADD(at[10], at[61]);    MULADD(at[11], at[60]);    MULADD(at[12], at[59]);    MULADD(at[13], at[58]);    MULADD(at[14], at[57]);    MULADD(at[15], at[56]);    MULADD(at[16], at[55]);    MULADD(at[17], at[54]);    MULADD(at[18], at[53]);    MULADD(at[19], at[52]);    MULADD(at[20], at[51]);    MULADD(at[21], at[50]);    MULADD(at[22], at[49]);    MULADD(at[23], at[48]); 
+   COMBA_STORE(C->dp[23]);
+   /* 24 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[72]);    MULADD(at[1], at[71]);    MULADD(at[2], at[70]);    MULADD(at[3], at[69]);    MULADD(at[4], at[68]);    MULADD(at[5], at[67]);    MULADD(at[6], at[66]);    MULADD(at[7], at[65]);    MULADD(at[8], at[64]);    MULADD(at[9], at[63]);    MULADD(at[10], at[62]);    MULADD(at[11], at[61]);    MULADD(at[12], at[60]);    MULADD(at[13], at[59]);    MULADD(at[14], at[58]);    MULADD(at[15], at[57]);    MULADD(at[16], at[56]);    MULADD(at[17], at[55]);    MULADD(at[18], at[54]);    MULADD(at[19], at[53]);    MULADD(at[20], at[52]);    MULADD(at[21], at[51]);    MULADD(at[22], at[50]);    MULADD(at[23], at[49]);    MULADD(at[24], at[48]); 
+   COMBA_STORE(C->dp[24]);
+   /* 25 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[73]);    MULADD(at[1], at[72]);    MULADD(at[2], at[71]);    MULADD(at[3], at[70]);    MULADD(at[4], at[69]);    MULADD(at[5], at[68]);    MULADD(at[6], at[67]);    MULADD(at[7], at[66]);    MULADD(at[8], at[65]);    MULADD(at[9], at[64]);    MULADD(at[10], at[63]);    MULADD(at[11], at[62]);    MULADD(at[12], at[61]);    MULADD(at[13], at[60]);    MULADD(at[14], at[59]);    MULADD(at[15], at[58]);    MULADD(at[16], at[57]);    MULADD(at[17], at[56]);    MULADD(at[18], at[55]);    MULADD(at[19], at[54]);    MULADD(at[20], at[53]);    MULADD(at[21], at[52]);    MULADD(at[22], at[51]);    MULADD(at[23], at[50]);    MULADD(at[24], at[49]);    MULADD(at[25], at[48]); 
+   COMBA_STORE(C->dp[25]);
+   /* 26 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[74]);    MULADD(at[1], at[73]);    MULADD(at[2], at[72]);    MULADD(at[3], at[71]);    MULADD(at[4], at[70]);    MULADD(at[5], at[69]);    MULADD(at[6], at[68]);    MULADD(at[7], at[67]);    MULADD(at[8], at[66]);    MULADD(at[9], at[65]);    MULADD(at[10], at[64]);    MULADD(at[11], at[63]);    MULADD(at[12], at[62]);    MULADD(at[13], at[61]);    MULADD(at[14], at[60]);    MULADD(at[15], at[59]);    MULADD(at[16], at[58]);    MULADD(at[17], at[57]);    MULADD(at[18], at[56]);    MULADD(at[19], at[55]);    MULADD(at[20], at[54]);    MULADD(at[21], at[53]);    MULADD(at[22], at[52]);    MULADD(at[23], at[51]);    MULADD(at[24], at[50]);    MULADD(at[25], at[49]);    MULADD(at[26], at[48]); 
+   COMBA_STORE(C->dp[26]);
+   /* 27 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[75]);    MULADD(at[1], at[74]);    MULADD(at[2], at[73]);    MULADD(at[3], at[72]);    MULADD(at[4], at[71]);    MULADD(at[5], at[70]);    MULADD(at[6], at[69]);    MULADD(at[7], at[68]);    MULADD(at[8], at[67]);    MULADD(at[9], at[66]);    MULADD(at[10], at[65]);    MULADD(at[11], at[64]);    MULADD(at[12], at[63]);    MULADD(at[13], at[62]);    MULADD(at[14], at[61]);    MULADD(at[15], at[60]);    MULADD(at[16], at[59]);    MULADD(at[17], at[58]);    MULADD(at[18], at[57]);    MULADD(at[19], at[56]);    MULADD(at[20], at[55]);    MULADD(at[21], at[54]);    MULADD(at[22], at[53]);    MULADD(at[23], at[52]);    MULADD(at[24], at[51]);    MULADD(at[25], at[50]);    MULADD(at[26], at[49]);    MULADD(at[27], at[48]); 
+   COMBA_STORE(C->dp[27]);
+   /* 28 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[76]);    MULADD(at[1], at[75]);    MULADD(at[2], at[74]);    MULADD(at[3], at[73]);    MULADD(at[4], at[72]);    MULADD(at[5], at[71]);    MULADD(at[6], at[70]);    MULADD(at[7], at[69]);    MULADD(at[8], at[68]);    MULADD(at[9], at[67]);    MULADD(at[10], at[66]);    MULADD(at[11], at[65]);    MULADD(at[12], at[64]);    MULADD(at[13], at[63]);    MULADD(at[14], at[62]);    MULADD(at[15], at[61]);    MULADD(at[16], at[60]);    MULADD(at[17], at[59]);    MULADD(at[18], at[58]);    MULADD(at[19], at[57]);    MULADD(at[20], at[56]);    MULADD(at[21], at[55]);    MULADD(at[22], at[54]);    MULADD(at[23], at[53]);    MULADD(at[24], at[52]);    MULADD(at[25], at[51]);    MULADD(at[26], at[50]);    MULADD(at[27], at[49]);    MULADD(at[28], at[48]); 
+   COMBA_STORE(C->dp[28]);
+   /* 29 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[77]);    MULADD(at[1], at[76]);    MULADD(at[2], at[75]);    MULADD(at[3], at[74]);    MULADD(at[4], at[73]);    MULADD(at[5], at[72]);    MULADD(at[6], at[71]);    MULADD(at[7], at[70]);    MULADD(at[8], at[69]);    MULADD(at[9], at[68]);    MULADD(at[10], at[67]);    MULADD(at[11], at[66]);    MULADD(at[12], at[65]);    MULADD(at[13], at[64]);    MULADD(at[14], at[63]);    MULADD(at[15], at[62]);    MULADD(at[16], at[61]);    MULADD(at[17], at[60]);    MULADD(at[18], at[59]);    MULADD(at[19], at[58]);    MULADD(at[20], at[57]);    MULADD(at[21], at[56]);    MULADD(at[22], at[55]);    MULADD(at[23], at[54]);    MULADD(at[24], at[53]);    MULADD(at[25], at[52]);    MULADD(at[26], at[51]);    MULADD(at[27], at[50]);    MULADD(at[28], at[49]);    MULADD(at[29], at[48]); 
+   COMBA_STORE(C->dp[29]);
+   /* 30 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[78]);    MULADD(at[1], at[77]);    MULADD(at[2], at[76]);    MULADD(at[3], at[75]);    MULADD(at[4], at[74]);    MULADD(at[5], at[73]);    MULADD(at[6], at[72]);    MULADD(at[7], at[71]);    MULADD(at[8], at[70]);    MULADD(at[9], at[69]);    MULADD(at[10], at[68]);    MULADD(at[11], at[67]);    MULADD(at[12], at[66]);    MULADD(at[13], at[65]);    MULADD(at[14], at[64]);    MULADD(at[15], at[63]);    MULADD(at[16], at[62]);    MULADD(at[17], at[61]);    MULADD(at[18], at[60]);    MULADD(at[19], at[59]);    MULADD(at[20], at[58]);    MULADD(at[21], at[57]);    MULADD(at[22], at[56]);    MULADD(at[23], at[55]);    MULADD(at[24], at[54]);    MULADD(at[25], at[53]);    MULADD(at[26], at[52]);    MULADD(at[27], at[51]);    MULADD(at[28], at[50]);    MULADD(at[29], at[49]);    MULADD(at[30], at[48]); 
+   COMBA_STORE(C->dp[30]);
+   /* 31 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[79]);    MULADD(at[1], at[78]);    MULADD(at[2], at[77]);    MULADD(at[3], at[76]);    MULADD(at[4], at[75]);    MULADD(at[5], at[74]);    MULADD(at[6], at[73]);    MULADD(at[7], at[72]);    MULADD(at[8], at[71]);    MULADD(at[9], at[70]);    MULADD(at[10], at[69]);    MULADD(at[11], at[68]);    MULADD(at[12], at[67]);    MULADD(at[13], at[66]);    MULADD(at[14], at[65]);    MULADD(at[15], at[64]);    MULADD(at[16], at[63]);    MULADD(at[17], at[62]);    MULADD(at[18], at[61]);    MULADD(at[19], at[60]);    MULADD(at[20], at[59]);    MULADD(at[21], at[58]);    MULADD(at[22], at[57]);    MULADD(at[23], at[56]);    MULADD(at[24], at[55]);    MULADD(at[25], at[54]);    MULADD(at[26], at[53]);    MULADD(at[27], at[52]);    MULADD(at[28], at[51]);    MULADD(at[29], at[50]);    MULADD(at[30], at[49]);    MULADD(at[31], at[48]); 
+   COMBA_STORE(C->dp[31]);
+   /* 32 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[80]);    MULADD(at[1], at[79]);    MULADD(at[2], at[78]);    MULADD(at[3], at[77]);    MULADD(at[4], at[76]);    MULADD(at[5], at[75]);    MULADD(at[6], at[74]);    MULADD(at[7], at[73]);    MULADD(at[8], at[72]);    MULADD(at[9], at[71]);    MULADD(at[10], at[70]);    MULADD(at[11], at[69]);    MULADD(at[12], at[68]);    MULADD(at[13], at[67]);    MULADD(at[14], at[66]);    MULADD(at[15], at[65]);    MULADD(at[16], at[64]);    MULADD(at[17], at[63]);    MULADD(at[18], at[62]);    MULADD(at[19], at[61]);    MULADD(at[20], at[60]);    MULADD(at[21], at[59]);    MULADD(at[22], at[58]);    MULADD(at[23], at[57]);    MULADD(at[24], at[56]);    MULADD(at[25], at[55]);    MULADD(at[26], at[54]);    MULADD(at[27], at[53]);    MULADD(at[28], at[52]);    MULADD(at[29], at[51]);    MULADD(at[30], at[50]);    MULADD(at[31], at[49]);    MULADD(at[32], at[48]); 
+   COMBA_STORE(C->dp[32]);
+   /* 33 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[81]);    MULADD(at[1], at[80]);    MULADD(at[2], at[79]);    MULADD(at[3], at[78]);    MULADD(at[4], at[77]);    MULADD(at[5], at[76]);    MULADD(at[6], at[75]);    MULADD(at[7], at[74]);    MULADD(at[8], at[73]);    MULADD(at[9], at[72]);    MULADD(at[10], at[71]);    MULADD(at[11], at[70]);    MULADD(at[12], at[69]);    MULADD(at[13], at[68]);    MULADD(at[14], at[67]);    MULADD(at[15], at[66]);    MULADD(at[16], at[65]);    MULADD(at[17], at[64]);    MULADD(at[18], at[63]);    MULADD(at[19], at[62]);    MULADD(at[20], at[61]);    MULADD(at[21], at[60]);    MULADD(at[22], at[59]);    MULADD(at[23], at[58]);    MULADD(at[24], at[57]);    MULADD(at[25], at[56]);    MULADD(at[26], at[55]);    MULADD(at[27], at[54]);    MULADD(at[28], at[53]);    MULADD(at[29], at[52]);    MULADD(at[30], at[51]);    MULADD(at[31], at[50]);    MULADD(at[32], at[49]);    MULADD(at[33], at[48]); 
+   COMBA_STORE(C->dp[33]);
+   /* 34 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[82]);    MULADD(at[1], at[81]);    MULADD(at[2], at[80]);    MULADD(at[3], at[79]);    MULADD(at[4], at[78]);    MULADD(at[5], at[77]);    MULADD(at[6], at[76]);    MULADD(at[7], at[75]);    MULADD(at[8], at[74]);    MULADD(at[9], at[73]);    MULADD(at[10], at[72]);    MULADD(at[11], at[71]);    MULADD(at[12], at[70]);    MULADD(at[13], at[69]);    MULADD(at[14], at[68]);    MULADD(at[15], at[67]);    MULADD(at[16], at[66]);    MULADD(at[17], at[65]);    MULADD(at[18], at[64]);    MULADD(at[19], at[63]);    MULADD(at[20], at[62]);    MULADD(at[21], at[61]);    MULADD(at[22], at[60]);    MULADD(at[23], at[59]);    MULADD(at[24], at[58]);    MULADD(at[25], at[57]);    MULADD(at[26], at[56]);    MULADD(at[27], at[55]);    MULADD(at[28], at[54]);    MULADD(at[29], at[53]);    MULADD(at[30], at[52]);    MULADD(at[31], at[51]);    MULADD(at[32], at[50]);    MULADD(at[33], at[49]);    MULADD(at[34], at[48]); 
+   COMBA_STORE(C->dp[34]);
+   /* 35 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[83]);    MULADD(at[1], at[82]);    MULADD(at[2], at[81]);    MULADD(at[3], at[80]);    MULADD(at[4], at[79]);    MULADD(at[5], at[78]);    MULADD(at[6], at[77]);    MULADD(at[7], at[76]);    MULADD(at[8], at[75]);    MULADD(at[9], at[74]);    MULADD(at[10], at[73]);    MULADD(at[11], at[72]);    MULADD(at[12], at[71]);    MULADD(at[13], at[70]);    MULADD(at[14], at[69]);    MULADD(at[15], at[68]);    MULADD(at[16], at[67]);    MULADD(at[17], at[66]);    MULADD(at[18], at[65]);    MULADD(at[19], at[64]);    MULADD(at[20], at[63]);    MULADD(at[21], at[62]);    MULADD(at[22], at[61]);    MULADD(at[23], at[60]);    MULADD(at[24], at[59]);    MULADD(at[25], at[58]);    MULADD(at[26], at[57]);    MULADD(at[27], at[56]);    MULADD(at[28], at[55]);    MULADD(at[29], at[54]);    MULADD(at[30], at[53]);    MULADD(at[31], at[52]);    MULADD(at[32], at[51]);    MULADD(at[33], at[50]);    MULADD(at[34], at[49]);    MULADD(at[35], at[48]); 
+   COMBA_STORE(C->dp[35]);
+   /* 36 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[84]);    MULADD(at[1], at[83]);    MULADD(at[2], at[82]);    MULADD(at[3], at[81]);    MULADD(at[4], at[80]);    MULADD(at[5], at[79]);    MULADD(at[6], at[78]);    MULADD(at[7], at[77]);    MULADD(at[8], at[76]);    MULADD(at[9], at[75]);    MULADD(at[10], at[74]);    MULADD(at[11], at[73]);    MULADD(at[12], at[72]);    MULADD(at[13], at[71]);    MULADD(at[14], at[70]);    MULADD(at[15], at[69]);    MULADD(at[16], at[68]);    MULADD(at[17], at[67]);    MULADD(at[18], at[66]);    MULADD(at[19], at[65]);    MULADD(at[20], at[64]);    MULADD(at[21], at[63]);    MULADD(at[22], at[62]);    MULADD(at[23], at[61]);    MULADD(at[24], at[60]);    MULADD(at[25], at[59]);    MULADD(at[26], at[58]);    MULADD(at[27], at[57]);    MULADD(at[28], at[56]);    MULADD(at[29], at[55]);    MULADD(at[30], at[54]);    MULADD(at[31], at[53]);    MULADD(at[32], at[52]);    MULADD(at[33], at[51]);    MULADD(at[34], at[50]);    MULADD(at[35], at[49]);    MULADD(at[36], at[48]); 
+   COMBA_STORE(C->dp[36]);
+   /* 37 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[85]);    MULADD(at[1], at[84]);    MULADD(at[2], at[83]);    MULADD(at[3], at[82]);    MULADD(at[4], at[81]);    MULADD(at[5], at[80]);    MULADD(at[6], at[79]);    MULADD(at[7], at[78]);    MULADD(at[8], at[77]);    MULADD(at[9], at[76]);    MULADD(at[10], at[75]);    MULADD(at[11], at[74]);    MULADD(at[12], at[73]);    MULADD(at[13], at[72]);    MULADD(at[14], at[71]);    MULADD(at[15], at[70]);    MULADD(at[16], at[69]);    MULADD(at[17], at[68]);    MULADD(at[18], at[67]);    MULADD(at[19], at[66]);    MULADD(at[20], at[65]);    MULADD(at[21], at[64]);    MULADD(at[22], at[63]);    MULADD(at[23], at[62]);    MULADD(at[24], at[61]);    MULADD(at[25], at[60]);    MULADD(at[26], at[59]);    MULADD(at[27], at[58]);    MULADD(at[28], at[57]);    MULADD(at[29], at[56]);    MULADD(at[30], at[55]);    MULADD(at[31], at[54]);    MULADD(at[32], at[53]);    MULADD(at[33], at[52]);    MULADD(at[34], at[51]);    MULADD(at[35], at[50]);    MULADD(at[36], at[49]);    MULADD(at[37], at[48]); 
+   COMBA_STORE(C->dp[37]);
+   /* 38 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[86]);    MULADD(at[1], at[85]);    MULADD(at[2], at[84]);    MULADD(at[3], at[83]);    MULADD(at[4], at[82]);    MULADD(at[5], at[81]);    MULADD(at[6], at[80]);    MULADD(at[7], at[79]);    MULADD(at[8], at[78]);    MULADD(at[9], at[77]);    MULADD(at[10], at[76]);    MULADD(at[11], at[75]);    MULADD(at[12], at[74]);    MULADD(at[13], at[73]);    MULADD(at[14], at[72]);    MULADD(at[15], at[71]);    MULADD(at[16], at[70]);    MULADD(at[17], at[69]);    MULADD(at[18], at[68]);    MULADD(at[19], at[67]);    MULADD(at[20], at[66]);    MULADD(at[21], at[65]);    MULADD(at[22], at[64]);    MULADD(at[23], at[63]);    MULADD(at[24], at[62]);    MULADD(at[25], at[61]);    MULADD(at[26], at[60]);    MULADD(at[27], at[59]);    MULADD(at[28], at[58]);    MULADD(at[29], at[57]);    MULADD(at[30], at[56]);    MULADD(at[31], at[55]);    MULADD(at[32], at[54]);    MULADD(at[33], at[53]);    MULADD(at[34], at[52]);    MULADD(at[35], at[51]);    MULADD(at[36], at[50]);    MULADD(at[37], at[49]);    MULADD(at[38], at[48]); 
+   COMBA_STORE(C->dp[38]);
+   /* 39 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[87]);    MULADD(at[1], at[86]);    MULADD(at[2], at[85]);    MULADD(at[3], at[84]);    MULADD(at[4], at[83]);    MULADD(at[5], at[82]);    MULADD(at[6], at[81]);    MULADD(at[7], at[80]);    MULADD(at[8], at[79]);    MULADD(at[9], at[78]);    MULADD(at[10], at[77]);    MULADD(at[11], at[76]);    MULADD(at[12], at[75]);    MULADD(at[13], at[74]);    MULADD(at[14], at[73]);    MULADD(at[15], at[72]);    MULADD(at[16], at[71]);    MULADD(at[17], at[70]);    MULADD(at[18], at[69]);    MULADD(at[19], at[68]);    MULADD(at[20], at[67]);    MULADD(at[21], at[66]);    MULADD(at[22], at[65]);    MULADD(at[23], at[64]);    MULADD(at[24], at[63]);    MULADD(at[25], at[62]);    MULADD(at[26], at[61]);    MULADD(at[27], at[60]);    MULADD(at[28], at[59]);    MULADD(at[29], at[58]);    MULADD(at[30], at[57]);    MULADD(at[31], at[56]);    MULADD(at[32], at[55]);    MULADD(at[33], at[54]);    MULADD(at[34], at[53]);    MULADD(at[35], at[52]);    MULADD(at[36], at[51]);    MULADD(at[37], at[50]);    MULADD(at[38], at[49]);    MULADD(at[39], at[48]); 
+   COMBA_STORE(C->dp[39]);
+   /* 40 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[88]);    MULADD(at[1], at[87]);    MULADD(at[2], at[86]);    MULADD(at[3], at[85]);    MULADD(at[4], at[84]);    MULADD(at[5], at[83]);    MULADD(at[6], at[82]);    MULADD(at[7], at[81]);    MULADD(at[8], at[80]);    MULADD(at[9], at[79]);    MULADD(at[10], at[78]);    MULADD(at[11], at[77]);    MULADD(at[12], at[76]);    MULADD(at[13], at[75]);    MULADD(at[14], at[74]);    MULADD(at[15], at[73]);    MULADD(at[16], at[72]);    MULADD(at[17], at[71]);    MULADD(at[18], at[70]);    MULADD(at[19], at[69]);    MULADD(at[20], at[68]);    MULADD(at[21], at[67]);    MULADD(at[22], at[66]);    MULADD(at[23], at[65]);    MULADD(at[24], at[64]);    MULADD(at[25], at[63]);    MULADD(at[26], at[62]);    MULADD(at[27], at[61]);    MULADD(at[28], at[60]);    MULADD(at[29], at[59]);    MULADD(at[30], at[58]);    MULADD(at[31], at[57]);    MULADD(at[32], at[56]);    MULADD(at[33], at[55]);    MULADD(at[34], at[54]);    MULADD(at[35], at[53]);    MULADD(at[36], at[52]);    MULADD(at[37], at[51]);    MULADD(at[38], at[50]);    MULADD(at[39], at[49]);    MULADD(at[40], at[48]); 
+   COMBA_STORE(C->dp[40]);
+   /* 41 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[89]);    MULADD(at[1], at[88]);    MULADD(at[2], at[87]);    MULADD(at[3], at[86]);    MULADD(at[4], at[85]);    MULADD(at[5], at[84]);    MULADD(at[6], at[83]);    MULADD(at[7], at[82]);    MULADD(at[8], at[81]);    MULADD(at[9], at[80]);    MULADD(at[10], at[79]);    MULADD(at[11], at[78]);    MULADD(at[12], at[77]);    MULADD(at[13], at[76]);    MULADD(at[14], at[75]);    MULADD(at[15], at[74]);    MULADD(at[16], at[73]);    MULADD(at[17], at[72]);    MULADD(at[18], at[71]);    MULADD(at[19], at[70]);    MULADD(at[20], at[69]);    MULADD(at[21], at[68]);    MULADD(at[22], at[67]);    MULADD(at[23], at[66]);    MULADD(at[24], at[65]);    MULADD(at[25], at[64]);    MULADD(at[26], at[63]);    MULADD(at[27], at[62]);    MULADD(at[28], at[61]);    MULADD(at[29], at[60]);    MULADD(at[30], at[59]);    MULADD(at[31], at[58]);    MULADD(at[32], at[57]);    MULADD(at[33], at[56]);    MULADD(at[34], at[55]);    MULADD(at[35], at[54]);    MULADD(at[36], at[53]);    MULADD(at[37], at[52]);    MULADD(at[38], at[51]);    MULADD(at[39], at[50]);    MULADD(at[40], at[49]);    MULADD(at[41], at[48]); 
+   COMBA_STORE(C->dp[41]);
+   /* 42 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[90]);    MULADD(at[1], at[89]);    MULADD(at[2], at[88]);    MULADD(at[3], at[87]);    MULADD(at[4], at[86]);    MULADD(at[5], at[85]);    MULADD(at[6], at[84]);    MULADD(at[7], at[83]);    MULADD(at[8], at[82]);    MULADD(at[9], at[81]);    MULADD(at[10], at[80]);    MULADD(at[11], at[79]);    MULADD(at[12], at[78]);    MULADD(at[13], at[77]);    MULADD(at[14], at[76]);    MULADD(at[15], at[75]);    MULADD(at[16], at[74]);    MULADD(at[17], at[73]);    MULADD(at[18], at[72]);    MULADD(at[19], at[71]);    MULADD(at[20], at[70]);    MULADD(at[21], at[69]);    MULADD(at[22], at[68]);    MULADD(at[23], at[67]);    MULADD(at[24], at[66]);    MULADD(at[25], at[65]);    MULADD(at[26], at[64]);    MULADD(at[27], at[63]);    MULADD(at[28], at[62]);    MULADD(at[29], at[61]);    MULADD(at[30], at[60]);    MULADD(at[31], at[59]);    MULADD(at[32], at[58]);    MULADD(at[33], at[57]);    MULADD(at[34], at[56]);    MULADD(at[35], at[55]);    MULADD(at[36], at[54]);    MULADD(at[37], at[53]);    MULADD(at[38], at[52]);    MULADD(at[39], at[51]);    MULADD(at[40], at[50]);    MULADD(at[41], at[49]);    MULADD(at[42], at[48]); 
+   COMBA_STORE(C->dp[42]);
+   /* 43 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[91]);    MULADD(at[1], at[90]);    MULADD(at[2], at[89]);    MULADD(at[3], at[88]);    MULADD(at[4], at[87]);    MULADD(at[5], at[86]);    MULADD(at[6], at[85]);    MULADD(at[7], at[84]);    MULADD(at[8], at[83]);    MULADD(at[9], at[82]);    MULADD(at[10], at[81]);    MULADD(at[11], at[80]);    MULADD(at[12], at[79]);    MULADD(at[13], at[78]);    MULADD(at[14], at[77]);    MULADD(at[15], at[76]);    MULADD(at[16], at[75]);    MULADD(at[17], at[74]);    MULADD(at[18], at[73]);    MULADD(at[19], at[72]);    MULADD(at[20], at[71]);    MULADD(at[21], at[70]);    MULADD(at[22], at[69]);    MULADD(at[23], at[68]);    MULADD(at[24], at[67]);    MULADD(at[25], at[66]);    MULADD(at[26], at[65]);    MULADD(at[27], at[64]);    MULADD(at[28], at[63]);    MULADD(at[29], at[62]);    MULADD(at[30], at[61]);    MULADD(at[31], at[60]);    MULADD(at[32], at[59]);    MULADD(at[33], at[58]);    MULADD(at[34], at[57]);    MULADD(at[35], at[56]);    MULADD(at[36], at[55]);    MULADD(at[37], at[54]);    MULADD(at[38], at[53]);    MULADD(at[39], at[52]);    MULADD(at[40], at[51]);    MULADD(at[41], at[50]);    MULADD(at[42], at[49]);    MULADD(at[43], at[48]); 
+   COMBA_STORE(C->dp[43]);
+   /* 44 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[92]);    MULADD(at[1], at[91]);    MULADD(at[2], at[90]);    MULADD(at[3], at[89]);    MULADD(at[4], at[88]);    MULADD(at[5], at[87]);    MULADD(at[6], at[86]);    MULADD(at[7], at[85]);    MULADD(at[8], at[84]);    MULADD(at[9], at[83]);    MULADD(at[10], at[82]);    MULADD(at[11], at[81]);    MULADD(at[12], at[80]);    MULADD(at[13], at[79]);    MULADD(at[14], at[78]);    MULADD(at[15], at[77]);    MULADD(at[16], at[76]);    MULADD(at[17], at[75]);    MULADD(at[18], at[74]);    MULADD(at[19], at[73]);    MULADD(at[20], at[72]);    MULADD(at[21], at[71]);    MULADD(at[22], at[70]);    MULADD(at[23], at[69]);    MULADD(at[24], at[68]);    MULADD(at[25], at[67]);    MULADD(at[26], at[66]);    MULADD(at[27], at[65]);    MULADD(at[28], at[64]);    MULADD(at[29], at[63]);    MULADD(at[30], at[62]);    MULADD(at[31], at[61]);    MULADD(at[32], at[60]);    MULADD(at[33], at[59]);    MULADD(at[34], at[58]);    MULADD(at[35], at[57]);    MULADD(at[36], at[56]);    MULADD(at[37], at[55]);    MULADD(at[38], at[54]);    MULADD(at[39], at[53]);    MULADD(at[40], at[52]);    MULADD(at[41], at[51]);    MULADD(at[42], at[50]);    MULADD(at[43], at[49]);    MULADD(at[44], at[48]); 
+   COMBA_STORE(C->dp[44]);
+   /* 45 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[93]);    MULADD(at[1], at[92]);    MULADD(at[2], at[91]);    MULADD(at[3], at[90]);    MULADD(at[4], at[89]);    MULADD(at[5], at[88]);    MULADD(at[6], at[87]);    MULADD(at[7], at[86]);    MULADD(at[8], at[85]);    MULADD(at[9], at[84]);    MULADD(at[10], at[83]);    MULADD(at[11], at[82]);    MULADD(at[12], at[81]);    MULADD(at[13], at[80]);    MULADD(at[14], at[79]);    MULADD(at[15], at[78]);    MULADD(at[16], at[77]);    MULADD(at[17], at[76]);    MULADD(at[18], at[75]);    MULADD(at[19], at[74]);    MULADD(at[20], at[73]);    MULADD(at[21], at[72]);    MULADD(at[22], at[71]);    MULADD(at[23], at[70]);    MULADD(at[24], at[69]);    MULADD(at[25], at[68]);    MULADD(at[26], at[67]);    MULADD(at[27], at[66]);    MULADD(at[28], at[65]);    MULADD(at[29], at[64]);    MULADD(at[30], at[63]);    MULADD(at[31], at[62]);    MULADD(at[32], at[61]);    MULADD(at[33], at[60]);    MULADD(at[34], at[59]);    MULADD(at[35], at[58]);    MULADD(at[36], at[57]);    MULADD(at[37], at[56]);    MULADD(at[38], at[55]);    MULADD(at[39], at[54]);    MULADD(at[40], at[53]);    MULADD(at[41], at[52]);    MULADD(at[42], at[51]);    MULADD(at[43], at[50]);    MULADD(at[44], at[49]);    MULADD(at[45], at[48]); 
+   COMBA_STORE(C->dp[45]);
+   /* 46 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[94]);    MULADD(at[1], at[93]);    MULADD(at[2], at[92]);    MULADD(at[3], at[91]);    MULADD(at[4], at[90]);    MULADD(at[5], at[89]);    MULADD(at[6], at[88]);    MULADD(at[7], at[87]);    MULADD(at[8], at[86]);    MULADD(at[9], at[85]);    MULADD(at[10], at[84]);    MULADD(at[11], at[83]);    MULADD(at[12], at[82]);    MULADD(at[13], at[81]);    MULADD(at[14], at[80]);    MULADD(at[15], at[79]);    MULADD(at[16], at[78]);    MULADD(at[17], at[77]);    MULADD(at[18], at[76]);    MULADD(at[19], at[75]);    MULADD(at[20], at[74]);    MULADD(at[21], at[73]);    MULADD(at[22], at[72]);    MULADD(at[23], at[71]);    MULADD(at[24], at[70]);    MULADD(at[25], at[69]);    MULADD(at[26], at[68]);    MULADD(at[27], at[67]);    MULADD(at[28], at[66]);    MULADD(at[29], at[65]);    MULADD(at[30], at[64]);    MULADD(at[31], at[63]);    MULADD(at[32], at[62]);    MULADD(at[33], at[61]);    MULADD(at[34], at[60]);    MULADD(at[35], at[59]);    MULADD(at[36], at[58]);    MULADD(at[37], at[57]);    MULADD(at[38], at[56]);    MULADD(at[39], at[55]);    MULADD(at[40], at[54]);    MULADD(at[41], at[53]);    MULADD(at[42], at[52]);    MULADD(at[43], at[51]);    MULADD(at[44], at[50]);    MULADD(at[45], at[49]);    MULADD(at[46], at[48]); 
+   COMBA_STORE(C->dp[46]);
+   /* 47 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[95]);    MULADD(at[1], at[94]);    MULADD(at[2], at[93]);    MULADD(at[3], at[92]);    MULADD(at[4], at[91]);    MULADD(at[5], at[90]);    MULADD(at[6], at[89]);    MULADD(at[7], at[88]);    MULADD(at[8], at[87]);    MULADD(at[9], at[86]);    MULADD(at[10], at[85]);    MULADD(at[11], at[84]);    MULADD(at[12], at[83]);    MULADD(at[13], at[82]);    MULADD(at[14], at[81]);    MULADD(at[15], at[80]);    MULADD(at[16], at[79]);    MULADD(at[17], at[78]);    MULADD(at[18], at[77]);    MULADD(at[19], at[76]);    MULADD(at[20], at[75]);    MULADD(at[21], at[74]);    MULADD(at[22], at[73]);    MULADD(at[23], at[72]);    MULADD(at[24], at[71]);    MULADD(at[25], at[70]);    MULADD(at[26], at[69]);    MULADD(at[27], at[68]);    MULADD(at[28], at[67]);    MULADD(at[29], at[66]);    MULADD(at[30], at[65]);    MULADD(at[31], at[64]);    MULADD(at[32], at[63]);    MULADD(at[33], at[62]);    MULADD(at[34], at[61]);    MULADD(at[35], at[60]);    MULADD(at[36], at[59]);    MULADD(at[37], at[58]);    MULADD(at[38], at[57]);    MULADD(at[39], at[56]);    MULADD(at[40], at[55]);    MULADD(at[41], at[54]);    MULADD(at[42], at[53]);    MULADD(at[43], at[52]);    MULADD(at[44], at[51]);    MULADD(at[45], at[50]);    MULADD(at[46], at[49]);    MULADD(at[47], at[48]); 
+   COMBA_STORE(C->dp[47]);
+   /* 48 */
+   COMBA_FORWARD;
+   MULADD(at[1], at[95]);    MULADD(at[2], at[94]);    MULADD(at[3], at[93]);    MULADD(at[4], at[92]);    MULADD(at[5], at[91]);    MULADD(at[6], at[90]);    MULADD(at[7], at[89]);    MULADD(at[8], at[88]);    MULADD(at[9], at[87]);    MULADD(at[10], at[86]);    MULADD(at[11], at[85]);    MULADD(at[12], at[84]);    MULADD(at[13], at[83]);    MULADD(at[14], at[82]);    MULADD(at[15], at[81]);    MULADD(at[16], at[80]);    MULADD(at[17], at[79]);    MULADD(at[18], at[78]);    MULADD(at[19], at[77]);    MULADD(at[20], at[76]);    MULADD(at[21], at[75]);    MULADD(at[22], at[74]);    MULADD(at[23], at[73]);    MULADD(at[24], at[72]);    MULADD(at[25], at[71]);    MULADD(at[26], at[70]);    MULADD(at[27], at[69]);    MULADD(at[28], at[68]);    MULADD(at[29], at[67]);    MULADD(at[30], at[66]);    MULADD(at[31], at[65]);    MULADD(at[32], at[64]);    MULADD(at[33], at[63]);    MULADD(at[34], at[62]);    MULADD(at[35], at[61]);    MULADD(at[36], at[60]);    MULADD(at[37], at[59]);    MULADD(at[38], at[58]);    MULADD(at[39], at[57]);    MULADD(at[40], at[56]);    MULADD(at[41], at[55]);    MULADD(at[42], at[54]);    MULADD(at[43], at[53]);    MULADD(at[44], at[52]);    MULADD(at[45], at[51]);    MULADD(at[46], at[50]);    MULADD(at[47], at[49]); 
+   COMBA_STORE(C->dp[48]);
+   /* 49 */
+   COMBA_FORWARD;
+   MULADD(at[2], at[95]);    MULADD(at[3], at[94]);    MULADD(at[4], at[93]);    MULADD(at[5], at[92]);    MULADD(at[6], at[91]);    MULADD(at[7], at[90]);    MULADD(at[8], at[89]);    MULADD(at[9], at[88]);    MULADD(at[10], at[87]);    MULADD(at[11], at[86]);    MULADD(at[12], at[85]);    MULADD(at[13], at[84]);    MULADD(at[14], at[83]);    MULADD(at[15], at[82]);    MULADD(at[16], at[81]);    MULADD(at[17], at[80]);    MULADD(at[18], at[79]);    MULADD(at[19], at[78]);    MULADD(at[20], at[77]);    MULADD(at[21], at[76]);    MULADD(at[22], at[75]);    MULADD(at[23], at[74]);    MULADD(at[24], at[73]);    MULADD(at[25], at[72]);    MULADD(at[26], at[71]);    MULADD(at[27], at[70]);    MULADD(at[28], at[69]);    MULADD(at[29], at[68]);    MULADD(at[30], at[67]);    MULADD(at[31], at[66]);    MULADD(at[32], at[65]);    MULADD(at[33], at[64]);    MULADD(at[34], at[63]);    MULADD(at[35], at[62]);    MULADD(at[36], at[61]);    MULADD(at[37], at[60]);    MULADD(at[38], at[59]);    MULADD(at[39], at[58]);    MULADD(at[40], at[57]);    MULADD(at[41], at[56]);    MULADD(at[42], at[55]);    MULADD(at[43], at[54]);    MULADD(at[44], at[53]);    MULADD(at[45], at[52]);    MULADD(at[46], at[51]);    MULADD(at[47], at[50]); 
+   COMBA_STORE(C->dp[49]);
+   /* 50 */
+   COMBA_FORWARD;
+   MULADD(at[3], at[95]);    MULADD(at[4], at[94]);    MULADD(at[5], at[93]);    MULADD(at[6], at[92]);    MULADD(at[7], at[91]);    MULADD(at[8], at[90]);    MULADD(at[9], at[89]);    MULADD(at[10], at[88]);    MULADD(at[11], at[87]);    MULADD(at[12], at[86]);    MULADD(at[13], at[85]);    MULADD(at[14], at[84]);    MULADD(at[15], at[83]);    MULADD(at[16], at[82]);    MULADD(at[17], at[81]);    MULADD(at[18], at[80]);    MULADD(at[19], at[79]);    MULADD(at[20], at[78]);    MULADD(at[21], at[77]);    MULADD(at[22], at[76]);    MULADD(at[23], at[75]);    MULADD(at[24], at[74]);    MULADD(at[25], at[73]);    MULADD(at[26], at[72]);    MULADD(at[27], at[71]);    MULADD(at[28], at[70]);    MULADD(at[29], at[69]);    MULADD(at[30], at[68]);    MULADD(at[31], at[67]);    MULADD(at[32], at[66]);    MULADD(at[33], at[65]);    MULADD(at[34], at[64]);    MULADD(at[35], at[63]);    MULADD(at[36], at[62]);    MULADD(at[37], at[61]);    MULADD(at[38], at[60]);    MULADD(at[39], at[59]);    MULADD(at[40], at[58]);    MULADD(at[41], at[57]);    MULADD(at[42], at[56]);    MULADD(at[43], at[55]);    MULADD(at[44], at[54]);    MULADD(at[45], at[53]);    MULADD(at[46], at[52]);    MULADD(at[47], at[51]); 
+   COMBA_STORE(C->dp[50]);
+   /* 51 */
+   COMBA_FORWARD;
+   MULADD(at[4], at[95]);    MULADD(at[5], at[94]);    MULADD(at[6], at[93]);    MULADD(at[7], at[92]);    MULADD(at[8], at[91]);    MULADD(at[9], at[90]);    MULADD(at[10], at[89]);    MULADD(at[11], at[88]);    MULADD(at[12], at[87]);    MULADD(at[13], at[86]);    MULADD(at[14], at[85]);    MULADD(at[15], at[84]);    MULADD(at[16], at[83]);    MULADD(at[17], at[82]);    MULADD(at[18], at[81]);    MULADD(at[19], at[80]);    MULADD(at[20], at[79]);    MULADD(at[21], at[78]);    MULADD(at[22], at[77]);    MULADD(at[23], at[76]);    MULADD(at[24], at[75]);    MULADD(at[25], at[74]);    MULADD(at[26], at[73]);    MULADD(at[27], at[72]);    MULADD(at[28], at[71]);    MULADD(at[29], at[70]);    MULADD(at[30], at[69]);    MULADD(at[31], at[68]);    MULADD(at[32], at[67]);    MULADD(at[33], at[66]);    MULADD(at[34], at[65]);    MULADD(at[35], at[64]);    MULADD(at[36], at[63]);    MULADD(at[37], at[62]);    MULADD(at[38], at[61]);    MULADD(at[39], at[60]);    MULADD(at[40], at[59]);    MULADD(at[41], at[58]);    MULADD(at[42], at[57]);    MULADD(at[43], at[56]);    MULADD(at[44], at[55]);    MULADD(at[45], at[54]);    MULADD(at[46], at[53]);    MULADD(at[47], at[52]); 
+   COMBA_STORE(C->dp[51]);
+   /* 52 */
+   COMBA_FORWARD;
+   MULADD(at[5], at[95]);    MULADD(at[6], at[94]);    MULADD(at[7], at[93]);    MULADD(at[8], at[92]);    MULADD(at[9], at[91]);    MULADD(at[10], at[90]);    MULADD(at[11], at[89]);    MULADD(at[12], at[88]);    MULADD(at[13], at[87]);    MULADD(at[14], at[86]);    MULADD(at[15], at[85]);    MULADD(at[16], at[84]);    MULADD(at[17], at[83]);    MULADD(at[18], at[82]);    MULADD(at[19], at[81]);    MULADD(at[20], at[80]);    MULADD(at[21], at[79]);    MULADD(at[22], at[78]);    MULADD(at[23], at[77]);    MULADD(at[24], at[76]);    MULADD(at[25], at[75]);    MULADD(at[26], at[74]);    MULADD(at[27], at[73]);    MULADD(at[28], at[72]);    MULADD(at[29], at[71]);    MULADD(at[30], at[70]);    MULADD(at[31], at[69]);    MULADD(at[32], at[68]);    MULADD(at[33], at[67]);    MULADD(at[34], at[66]);    MULADD(at[35], at[65]);    MULADD(at[36], at[64]);    MULADD(at[37], at[63]);    MULADD(at[38], at[62]);    MULADD(at[39], at[61]);    MULADD(at[40], at[60]);    MULADD(at[41], at[59]);    MULADD(at[42], at[58]);    MULADD(at[43], at[57]);    MULADD(at[44], at[56]);    MULADD(at[45], at[55]);    MULADD(at[46], at[54]);    MULADD(at[47], at[53]); 
+   COMBA_STORE(C->dp[52]);
+   /* 53 */
+   COMBA_FORWARD;
+   MULADD(at[6], at[95]);    MULADD(at[7], at[94]);    MULADD(at[8], at[93]);    MULADD(at[9], at[92]);    MULADD(at[10], at[91]);    MULADD(at[11], at[90]);    MULADD(at[12], at[89]);    MULADD(at[13], at[88]);    MULADD(at[14], at[87]);    MULADD(at[15], at[86]);    MULADD(at[16], at[85]);    MULADD(at[17], at[84]);    MULADD(at[18], at[83]);    MULADD(at[19], at[82]);    MULADD(at[20], at[81]);    MULADD(at[21], at[80]);    MULADD(at[22], at[79]);    MULADD(at[23], at[78]);    MULADD(at[24], at[77]);    MULADD(at[25], at[76]);    MULADD(at[26], at[75]);    MULADD(at[27], at[74]);    MULADD(at[28], at[73]);    MULADD(at[29], at[72]);    MULADD(at[30], at[71]);    MULADD(at[31], at[70]);    MULADD(at[32], at[69]);    MULADD(at[33], at[68]);    MULADD(at[34], at[67]);    MULADD(at[35], at[66]);    MULADD(at[36], at[65]);    MULADD(at[37], at[64]);    MULADD(at[38], at[63]);    MULADD(at[39], at[62]);    MULADD(at[40], at[61]);    MULADD(at[41], at[60]);    MULADD(at[42], at[59]);    MULADD(at[43], at[58]);    MULADD(at[44], at[57]);    MULADD(at[45], at[56]);    MULADD(at[46], at[55]);    MULADD(at[47], at[54]); 
+   COMBA_STORE(C->dp[53]);
+   /* 54 */
+   COMBA_FORWARD;
+   MULADD(at[7], at[95]);    MULADD(at[8], at[94]);    MULADD(at[9], at[93]);    MULADD(at[10], at[92]);    MULADD(at[11], at[91]);    MULADD(at[12], at[90]);    MULADD(at[13], at[89]);    MULADD(at[14], at[88]);    MULADD(at[15], at[87]);    MULADD(at[16], at[86]);    MULADD(at[17], at[85]);    MULADD(at[18], at[84]);    MULADD(at[19], at[83]);    MULADD(at[20], at[82]);    MULADD(at[21], at[81]);    MULADD(at[22], at[80]);    MULADD(at[23], at[79]);    MULADD(at[24], at[78]);    MULADD(at[25], at[77]);    MULADD(at[26], at[76]);    MULADD(at[27], at[75]);    MULADD(at[28], at[74]);    MULADD(at[29], at[73]);    MULADD(at[30], at[72]);    MULADD(at[31], at[71]);    MULADD(at[32], at[70]);    MULADD(at[33], at[69]);    MULADD(at[34], at[68]);    MULADD(at[35], at[67]);    MULADD(at[36], at[66]);    MULADD(at[37], at[65]);    MULADD(at[38], at[64]);    MULADD(at[39], at[63]);    MULADD(at[40], at[62]);    MULADD(at[41], at[61]);    MULADD(at[42], at[60]);    MULADD(at[43], at[59]);    MULADD(at[44], at[58]);    MULADD(at[45], at[57]);    MULADD(at[46], at[56]);    MULADD(at[47], at[55]); 
+   COMBA_STORE(C->dp[54]);
+   /* 55 */
+   COMBA_FORWARD;
+   MULADD(at[8], at[95]);    MULADD(at[9], at[94]);    MULADD(at[10], at[93]);    MULADD(at[11], at[92]);    MULADD(at[12], at[91]);    MULADD(at[13], at[90]);    MULADD(at[14], at[89]);    MULADD(at[15], at[88]);    MULADD(at[16], at[87]);    MULADD(at[17], at[86]);    MULADD(at[18], at[85]);    MULADD(at[19], at[84]);    MULADD(at[20], at[83]);    MULADD(at[21], at[82]);    MULADD(at[22], at[81]);    MULADD(at[23], at[80]);    MULADD(at[24], at[79]);    MULADD(at[25], at[78]);    MULADD(at[26], at[77]);    MULADD(at[27], at[76]);    MULADD(at[28], at[75]);    MULADD(at[29], at[74]);    MULADD(at[30], at[73]);    MULADD(at[31], at[72]);    MULADD(at[32], at[71]);    MULADD(at[33], at[70]);    MULADD(at[34], at[69]);    MULADD(at[35], at[68]);    MULADD(at[36], at[67]);    MULADD(at[37], at[66]);    MULADD(at[38], at[65]);    MULADD(at[39], at[64]);    MULADD(at[40], at[63]);    MULADD(at[41], at[62]);    MULADD(at[42], at[61]);    MULADD(at[43], at[60]);    MULADD(at[44], at[59]);    MULADD(at[45], at[58]);    MULADD(at[46], at[57]);    MULADD(at[47], at[56]); 
+   COMBA_STORE(C->dp[55]);
+   /* 56 */
+   COMBA_FORWARD;
+   MULADD(at[9], at[95]);    MULADD(at[10], at[94]);    MULADD(at[11], at[93]);    MULADD(at[12], at[92]);    MULADD(at[13], at[91]);    MULADD(at[14], at[90]);    MULADD(at[15], at[89]);    MULADD(at[16], at[88]);    MULADD(at[17], at[87]);    MULADD(at[18], at[86]);    MULADD(at[19], at[85]);    MULADD(at[20], at[84]);    MULADD(at[21], at[83]);    MULADD(at[22], at[82]);    MULADD(at[23], at[81]);    MULADD(at[24], at[80]);    MULADD(at[25], at[79]);    MULADD(at[26], at[78]);    MULADD(at[27], at[77]);    MULADD(at[28], at[76]);    MULADD(at[29], at[75]);    MULADD(at[30], at[74]);    MULADD(at[31], at[73]);    MULADD(at[32], at[72]);    MULADD(at[33], at[71]);    MULADD(at[34], at[70]);    MULADD(at[35], at[69]);    MULADD(at[36], at[68]);    MULADD(at[37], at[67]);    MULADD(at[38], at[66]);    MULADD(at[39], at[65]);    MULADD(at[40], at[64]);    MULADD(at[41], at[63]);    MULADD(at[42], at[62]);    MULADD(at[43], at[61]);    MULADD(at[44], at[60]);    MULADD(at[45], at[59]);    MULADD(at[46], at[58]);    MULADD(at[47], at[57]); 
+   COMBA_STORE(C->dp[56]);
+   /* 57 */
+   COMBA_FORWARD;
+   MULADD(at[10], at[95]);    MULADD(at[11], at[94]);    MULADD(at[12], at[93]);    MULADD(at[13], at[92]);    MULADD(at[14], at[91]);    MULADD(at[15], at[90]);    MULADD(at[16], at[89]);    MULADD(at[17], at[88]);    MULADD(at[18], at[87]);    MULADD(at[19], at[86]);    MULADD(at[20], at[85]);    MULADD(at[21], at[84]);    MULADD(at[22], at[83]);    MULADD(at[23], at[82]);    MULADD(at[24], at[81]);    MULADD(at[25], at[80]);    MULADD(at[26], at[79]);    MULADD(at[27], at[78]);    MULADD(at[28], at[77]);    MULADD(at[29], at[76]);    MULADD(at[30], at[75]);    MULADD(at[31], at[74]);    MULADD(at[32], at[73]);    MULADD(at[33], at[72]);    MULADD(at[34], at[71]);    MULADD(at[35], at[70]);    MULADD(at[36], at[69]);    MULADD(at[37], at[68]);    MULADD(at[38], at[67]);    MULADD(at[39], at[66]);    MULADD(at[40], at[65]);    MULADD(at[41], at[64]);    MULADD(at[42], at[63]);    MULADD(at[43], at[62]);    MULADD(at[44], at[61]);    MULADD(at[45], at[60]);    MULADD(at[46], at[59]);    MULADD(at[47], at[58]); 
+   COMBA_STORE(C->dp[57]);
+   /* 58 */
+   COMBA_FORWARD;
+   MULADD(at[11], at[95]);    MULADD(at[12], at[94]);    MULADD(at[13], at[93]);    MULADD(at[14], at[92]);    MULADD(at[15], at[91]);    MULADD(at[16], at[90]);    MULADD(at[17], at[89]);    MULADD(at[18], at[88]);    MULADD(at[19], at[87]);    MULADD(at[20], at[86]);    MULADD(at[21], at[85]);    MULADD(at[22], at[84]);    MULADD(at[23], at[83]);    MULADD(at[24], at[82]);    MULADD(at[25], at[81]);    MULADD(at[26], at[80]);    MULADD(at[27], at[79]);    MULADD(at[28], at[78]);    MULADD(at[29], at[77]);    MULADD(at[30], at[76]);    MULADD(at[31], at[75]);    MULADD(at[32], at[74]);    MULADD(at[33], at[73]);    MULADD(at[34], at[72]);    MULADD(at[35], at[71]);    MULADD(at[36], at[70]);    MULADD(at[37], at[69]);    MULADD(at[38], at[68]);    MULADD(at[39], at[67]);    MULADD(at[40], at[66]);    MULADD(at[41], at[65]);    MULADD(at[42], at[64]);    MULADD(at[43], at[63]);    MULADD(at[44], at[62]);    MULADD(at[45], at[61]);    MULADD(at[46], at[60]);    MULADD(at[47], at[59]); 
+   COMBA_STORE(C->dp[58]);
+   /* 59 */
+   COMBA_FORWARD;
+   MULADD(at[12], at[95]);    MULADD(at[13], at[94]);    MULADD(at[14], at[93]);    MULADD(at[15], at[92]);    MULADD(at[16], at[91]);    MULADD(at[17], at[90]);    MULADD(at[18], at[89]);    MULADD(at[19], at[88]);    MULADD(at[20], at[87]);    MULADD(at[21], at[86]);    MULADD(at[22], at[85]);    MULADD(at[23], at[84]);    MULADD(at[24], at[83]);    MULADD(at[25], at[82]);    MULADD(at[26], at[81]);    MULADD(at[27], at[80]);    MULADD(at[28], at[79]);    MULADD(at[29], at[78]);    MULADD(at[30], at[77]);    MULADD(at[31], at[76]);    MULADD(at[32], at[75]);    MULADD(at[33], at[74]);    MULADD(at[34], at[73]);    MULADD(at[35], at[72]);    MULADD(at[36], at[71]);    MULADD(at[37], at[70]);    MULADD(at[38], at[69]);    MULADD(at[39], at[68]);    MULADD(at[40], at[67]);    MULADD(at[41], at[66]);    MULADD(at[42], at[65]);    MULADD(at[43], at[64]);    MULADD(at[44], at[63]);    MULADD(at[45], at[62]);    MULADD(at[46], at[61]);    MULADD(at[47], at[60]); 
+   COMBA_STORE(C->dp[59]);
+   /* 60 */
+   COMBA_FORWARD;
+   MULADD(at[13], at[95]);    MULADD(at[14], at[94]);    MULADD(at[15], at[93]);    MULADD(at[16], at[92]);    MULADD(at[17], at[91]);    MULADD(at[18], at[90]);    MULADD(at[19], at[89]);    MULADD(at[20], at[88]);    MULADD(at[21], at[87]);    MULADD(at[22], at[86]);    MULADD(at[23], at[85]);    MULADD(at[24], at[84]);    MULADD(at[25], at[83]);    MULADD(at[26], at[82]);    MULADD(at[27], at[81]);    MULADD(at[28], at[80]);    MULADD(at[29], at[79]);    MULADD(at[30], at[78]);    MULADD(at[31], at[77]);    MULADD(at[32], at[76]);    MULADD(at[33], at[75]);    MULADD(at[34], at[74]);    MULADD(at[35], at[73]);    MULADD(at[36], at[72]);    MULADD(at[37], at[71]);    MULADD(at[38], at[70]);    MULADD(at[39], at[69]);    MULADD(at[40], at[68]);    MULADD(at[41], at[67]);    MULADD(at[42], at[66]);    MULADD(at[43], at[65]);    MULADD(at[44], at[64]);    MULADD(at[45], at[63]);    MULADD(at[46], at[62]);    MULADD(at[47], at[61]); 
+   COMBA_STORE(C->dp[60]);
+   /* 61 */
+   COMBA_FORWARD;
+   MULADD(at[14], at[95]);    MULADD(at[15], at[94]);    MULADD(at[16], at[93]);    MULADD(at[17], at[92]);    MULADD(at[18], at[91]);    MULADD(at[19], at[90]);    MULADD(at[20], at[89]);    MULADD(at[21], at[88]);    MULADD(at[22], at[87]);    MULADD(at[23], at[86]);    MULADD(at[24], at[85]);    MULADD(at[25], at[84]);    MULADD(at[26], at[83]);    MULADD(at[27], at[82]);    MULADD(at[28], at[81]);    MULADD(at[29], at[80]);    MULADD(at[30], at[79]);    MULADD(at[31], at[78]);    MULADD(at[32], at[77]);    MULADD(at[33], at[76]);    MULADD(at[34], at[75]);    MULADD(at[35], at[74]);    MULADD(at[36], at[73]);    MULADD(at[37], at[72]);    MULADD(at[38], at[71]);    MULADD(at[39], at[70]);    MULADD(at[40], at[69]);    MULADD(at[41], at[68]);    MULADD(at[42], at[67]);    MULADD(at[43], at[66]);    MULADD(at[44], at[65]);    MULADD(at[45], at[64]);    MULADD(at[46], at[63]);    MULADD(at[47], at[62]); 
+   COMBA_STORE(C->dp[61]);
+   /* 62 */
+   COMBA_FORWARD;
+   MULADD(at[15], at[95]);    MULADD(at[16], at[94]);    MULADD(at[17], at[93]);    MULADD(at[18], at[92]);    MULADD(at[19], at[91]);    MULADD(at[20], at[90]);    MULADD(at[21], at[89]);    MULADD(at[22], at[88]);    MULADD(at[23], at[87]);    MULADD(at[24], at[86]);    MULADD(at[25], at[85]);    MULADD(at[26], at[84]);    MULADD(at[27], at[83]);    MULADD(at[28], at[82]);    MULADD(at[29], at[81]);    MULADD(at[30], at[80]);    MULADD(at[31], at[79]);    MULADD(at[32], at[78]);    MULADD(at[33], at[77]);    MULADD(at[34], at[76]);    MULADD(at[35], at[75]);    MULADD(at[36], at[74]);    MULADD(at[37], at[73]);    MULADD(at[38], at[72]);    MULADD(at[39], at[71]);    MULADD(at[40], at[70]);    MULADD(at[41], at[69]);    MULADD(at[42], at[68]);    MULADD(at[43], at[67]);    MULADD(at[44], at[66]);    MULADD(at[45], at[65]);    MULADD(at[46], at[64]);    MULADD(at[47], at[63]); 
+   COMBA_STORE(C->dp[62]);
+   /* 63 */
+   COMBA_FORWARD;
+   MULADD(at[16], at[95]);    MULADD(at[17], at[94]);    MULADD(at[18], at[93]);    MULADD(at[19], at[92]);    MULADD(at[20], at[91]);    MULADD(at[21], at[90]);    MULADD(at[22], at[89]);    MULADD(at[23], at[88]);    MULADD(at[24], at[87]);    MULADD(at[25], at[86]);    MULADD(at[26], at[85]);    MULADD(at[27], at[84]);    MULADD(at[28], at[83]);    MULADD(at[29], at[82]);    MULADD(at[30], at[81]);    MULADD(at[31], at[80]);    MULADD(at[32], at[79]);    MULADD(at[33], at[78]);    MULADD(at[34], at[77]);    MULADD(at[35], at[76]);    MULADD(at[36], at[75]);    MULADD(at[37], at[74]);    MULADD(at[38], at[73]);    MULADD(at[39], at[72]);    MULADD(at[40], at[71]);    MULADD(at[41], at[70]);    MULADD(at[42], at[69]);    MULADD(at[43], at[68]);    MULADD(at[44], at[67]);    MULADD(at[45], at[66]);    MULADD(at[46], at[65]);    MULADD(at[47], at[64]); 
+   COMBA_STORE(C->dp[63]);
+   /* 64 */
+   COMBA_FORWARD;
+   MULADD(at[17], at[95]);    MULADD(at[18], at[94]);    MULADD(at[19], at[93]);    MULADD(at[20], at[92]);    MULADD(at[21], at[91]);    MULADD(at[22], at[90]);    MULADD(at[23], at[89]);    MULADD(at[24], at[88]);    MULADD(at[25], at[87]);    MULADD(at[26], at[86]);    MULADD(at[27], at[85]);    MULADD(at[28], at[84]);    MULADD(at[29], at[83]);    MULADD(at[30], at[82]);    MULADD(at[31], at[81]);    MULADD(at[32], at[80]);    MULADD(at[33], at[79]);    MULADD(at[34], at[78]);    MULADD(at[35], at[77]);    MULADD(at[36], at[76]);    MULADD(at[37], at[75]);    MULADD(at[38], at[74]);    MULADD(at[39], at[73]);    MULADD(at[40], at[72]);    MULADD(at[41], at[71]);    MULADD(at[42], at[70]);    MULADD(at[43], at[69]);    MULADD(at[44], at[68]);    MULADD(at[45], at[67]);    MULADD(at[46], at[66]);    MULADD(at[47], at[65]); 
+   COMBA_STORE(C->dp[64]);
+   /* 65 */
+   COMBA_FORWARD;
+   MULADD(at[18], at[95]);    MULADD(at[19], at[94]);    MULADD(at[20], at[93]);    MULADD(at[21], at[92]);    MULADD(at[22], at[91]);    MULADD(at[23], at[90]);    MULADD(at[24], at[89]);    MULADD(at[25], at[88]);    MULADD(at[26], at[87]);    MULADD(at[27], at[86]);    MULADD(at[28], at[85]);    MULADD(at[29], at[84]);    MULADD(at[30], at[83]);    MULADD(at[31], at[82]);    MULADD(at[32], at[81]);    MULADD(at[33], at[80]);    MULADD(at[34], at[79]);    MULADD(at[35], at[78]);    MULADD(at[36], at[77]);    MULADD(at[37], at[76]);    MULADD(at[38], at[75]);    MULADD(at[39], at[74]);    MULADD(at[40], at[73]);    MULADD(at[41], at[72]);    MULADD(at[42], at[71]);    MULADD(at[43], at[70]);    MULADD(at[44], at[69]);    MULADD(at[45], at[68]);    MULADD(at[46], at[67]);    MULADD(at[47], at[66]); 
+   COMBA_STORE(C->dp[65]);
+   /* 66 */
+   COMBA_FORWARD;
+   MULADD(at[19], at[95]);    MULADD(at[20], at[94]);    MULADD(at[21], at[93]);    MULADD(at[22], at[92]);    MULADD(at[23], at[91]);    MULADD(at[24], at[90]);    MULADD(at[25], at[89]);    MULADD(at[26], at[88]);    MULADD(at[27], at[87]);    MULADD(at[28], at[86]);    MULADD(at[29], at[85]);    MULADD(at[30], at[84]);    MULADD(at[31], at[83]);    MULADD(at[32], at[82]);    MULADD(at[33], at[81]);    MULADD(at[34], at[80]);    MULADD(at[35], at[79]);    MULADD(at[36], at[78]);    MULADD(at[37], at[77]);    MULADD(at[38], at[76]);    MULADD(at[39], at[75]);    MULADD(at[40], at[74]);    MULADD(at[41], at[73]);    MULADD(at[42], at[72]);    MULADD(at[43], at[71]);    MULADD(at[44], at[70]);    MULADD(at[45], at[69]);    MULADD(at[46], at[68]);    MULADD(at[47], at[67]); 
+   COMBA_STORE(C->dp[66]);
+   /* 67 */
+   COMBA_FORWARD;
+   MULADD(at[20], at[95]);    MULADD(at[21], at[94]);    MULADD(at[22], at[93]);    MULADD(at[23], at[92]);    MULADD(at[24], at[91]);    MULADD(at[25], at[90]);    MULADD(at[26], at[89]);    MULADD(at[27], at[88]);    MULADD(at[28], at[87]);    MULADD(at[29], at[86]);    MULADD(at[30], at[85]);    MULADD(at[31], at[84]);    MULADD(at[32], at[83]);    MULADD(at[33], at[82]);    MULADD(at[34], at[81]);    MULADD(at[35], at[80]);    MULADD(at[36], at[79]);    MULADD(at[37], at[78]);    MULADD(at[38], at[77]);    MULADD(at[39], at[76]);    MULADD(at[40], at[75]);    MULADD(at[41], at[74]);    MULADD(at[42], at[73]);    MULADD(at[43], at[72]);    MULADD(at[44], at[71]);    MULADD(at[45], at[70]);    MULADD(at[46], at[69]);    MULADD(at[47], at[68]); 
+   COMBA_STORE(C->dp[67]);
+   /* 68 */
+   COMBA_FORWARD;
+   MULADD(at[21], at[95]);    MULADD(at[22], at[94]);    MULADD(at[23], at[93]);    MULADD(at[24], at[92]);    MULADD(at[25], at[91]);    MULADD(at[26], at[90]);    MULADD(at[27], at[89]);    MULADD(at[28], at[88]);    MULADD(at[29], at[87]);    MULADD(at[30], at[86]);    MULADD(at[31], at[85]);    MULADD(at[32], at[84]);    MULADD(at[33], at[83]);    MULADD(at[34], at[82]);    MULADD(at[35], at[81]);    MULADD(at[36], at[80]);    MULADD(at[37], at[79]);    MULADD(at[38], at[78]);    MULADD(at[39], at[77]);    MULADD(at[40], at[76]);    MULADD(at[41], at[75]);    MULADD(at[42], at[74]);    MULADD(at[43], at[73]);    MULADD(at[44], at[72]);    MULADD(at[45], at[71]);    MULADD(at[46], at[70]);    MULADD(at[47], at[69]); 
+   COMBA_STORE(C->dp[68]);
+   /* 69 */
+   COMBA_FORWARD;
+   MULADD(at[22], at[95]);    MULADD(at[23], at[94]);    MULADD(at[24], at[93]);    MULADD(at[25], at[92]);    MULADD(at[26], at[91]);    MULADD(at[27], at[90]);    MULADD(at[28], at[89]);    MULADD(at[29], at[88]);    MULADD(at[30], at[87]);    MULADD(at[31], at[86]);    MULADD(at[32], at[85]);    MULADD(at[33], at[84]);    MULADD(at[34], at[83]);    MULADD(at[35], at[82]);    MULADD(at[36], at[81]);    MULADD(at[37], at[80]);    MULADD(at[38], at[79]);    MULADD(at[39], at[78]);    MULADD(at[40], at[77]);    MULADD(at[41], at[76]);    MULADD(at[42], at[75]);    MULADD(at[43], at[74]);    MULADD(at[44], at[73]);    MULADD(at[45], at[72]);    MULADD(at[46], at[71]);    MULADD(at[47], at[70]); 
+   COMBA_STORE(C->dp[69]);
+   /* 70 */
+   COMBA_FORWARD;
+   MULADD(at[23], at[95]);    MULADD(at[24], at[94]);    MULADD(at[25], at[93]);    MULADD(at[26], at[92]);    MULADD(at[27], at[91]);    MULADD(at[28], at[90]);    MULADD(at[29], at[89]);    MULADD(at[30], at[88]);    MULADD(at[31], at[87]);    MULADD(at[32], at[86]);    MULADD(at[33], at[85]);    MULADD(at[34], at[84]);    MULADD(at[35], at[83]);    MULADD(at[36], at[82]);    MULADD(at[37], at[81]);    MULADD(at[38], at[80]);    MULADD(at[39], at[79]);    MULADD(at[40], at[78]);    MULADD(at[41], at[77]);    MULADD(at[42], at[76]);    MULADD(at[43], at[75]);    MULADD(at[44], at[74]);    MULADD(at[45], at[73]);    MULADD(at[46], at[72]);    MULADD(at[47], at[71]); 
+   COMBA_STORE(C->dp[70]);
+   /* 71 */
+   COMBA_FORWARD;
+   MULADD(at[24], at[95]);    MULADD(at[25], at[94]);    MULADD(at[26], at[93]);    MULADD(at[27], at[92]);    MULADD(at[28], at[91]);    MULADD(at[29], at[90]);    MULADD(at[30], at[89]);    MULADD(at[31], at[88]);    MULADD(at[32], at[87]);    MULADD(at[33], at[86]);    MULADD(at[34], at[85]);    MULADD(at[35], at[84]);    MULADD(at[36], at[83]);    MULADD(at[37], at[82]);    MULADD(at[38], at[81]);    MULADD(at[39], at[80]);    MULADD(at[40], at[79]);    MULADD(at[41], at[78]);    MULADD(at[42], at[77]);    MULADD(at[43], at[76]);    MULADD(at[44], at[75]);    MULADD(at[45], at[74]);    MULADD(at[46], at[73]);    MULADD(at[47], at[72]); 
+   COMBA_STORE(C->dp[71]);
+   /* 72 */
+   COMBA_FORWARD;
+   MULADD(at[25], at[95]);    MULADD(at[26], at[94]);    MULADD(at[27], at[93]);    MULADD(at[28], at[92]);    MULADD(at[29], at[91]);    MULADD(at[30], at[90]);    MULADD(at[31], at[89]);    MULADD(at[32], at[88]);    MULADD(at[33], at[87]);    MULADD(at[34], at[86]);    MULADD(at[35], at[85]);    MULADD(at[36], at[84]);    MULADD(at[37], at[83]);    MULADD(at[38], at[82]);    MULADD(at[39], at[81]);    MULADD(at[40], at[80]);    MULADD(at[41], at[79]);    MULADD(at[42], at[78]);    MULADD(at[43], at[77]);    MULADD(at[44], at[76]);    MULADD(at[45], at[75]);    MULADD(at[46], at[74]);    MULADD(at[47], at[73]); 
+   COMBA_STORE(C->dp[72]);
+   /* 73 */
+   COMBA_FORWARD;
+   MULADD(at[26], at[95]);    MULADD(at[27], at[94]);    MULADD(at[28], at[93]);    MULADD(at[29], at[92]);    MULADD(at[30], at[91]);    MULADD(at[31], at[90]);    MULADD(at[32], at[89]);    MULADD(at[33], at[88]);    MULADD(at[34], at[87]);    MULADD(at[35], at[86]);    MULADD(at[36], at[85]);    MULADD(at[37], at[84]);    MULADD(at[38], at[83]);    MULADD(at[39], at[82]);    MULADD(at[40], at[81]);    MULADD(at[41], at[80]);    MULADD(at[42], at[79]);    MULADD(at[43], at[78]);    MULADD(at[44], at[77]);    MULADD(at[45], at[76]);    MULADD(at[46], at[75]);    MULADD(at[47], at[74]); 
+   COMBA_STORE(C->dp[73]);
+   /* 74 */
+   COMBA_FORWARD;
+   MULADD(at[27], at[95]);    MULADD(at[28], at[94]);    MULADD(at[29], at[93]);    MULADD(at[30], at[92]);    MULADD(at[31], at[91]);    MULADD(at[32], at[90]);    MULADD(at[33], at[89]);    MULADD(at[34], at[88]);    MULADD(at[35], at[87]);    MULADD(at[36], at[86]);    MULADD(at[37], at[85]);    MULADD(at[38], at[84]);    MULADD(at[39], at[83]);    MULADD(at[40], at[82]);    MULADD(at[41], at[81]);    MULADD(at[42], at[80]);    MULADD(at[43], at[79]);    MULADD(at[44], at[78]);    MULADD(at[45], at[77]);    MULADD(at[46], at[76]);    MULADD(at[47], at[75]); 
+   COMBA_STORE(C->dp[74]);
+   /* 75 */
+   COMBA_FORWARD;
+   MULADD(at[28], at[95]);    MULADD(at[29], at[94]);    MULADD(at[30], at[93]);    MULADD(at[31], at[92]);    MULADD(at[32], at[91]);    MULADD(at[33], at[90]);    MULADD(at[34], at[89]);    MULADD(at[35], at[88]);    MULADD(at[36], at[87]);    MULADD(at[37], at[86]);    MULADD(at[38], at[85]);    MULADD(at[39], at[84]);    MULADD(at[40], at[83]);    MULADD(at[41], at[82]);    MULADD(at[42], at[81]);    MULADD(at[43], at[80]);    MULADD(at[44], at[79]);    MULADD(at[45], at[78]);    MULADD(at[46], at[77]);    MULADD(at[47], at[76]); 
+   COMBA_STORE(C->dp[75]);
+   /* 76 */
+   COMBA_FORWARD;
+   MULADD(at[29], at[95]);    MULADD(at[30], at[94]);    MULADD(at[31], at[93]);    MULADD(at[32], at[92]);    MULADD(at[33], at[91]);    MULADD(at[34], at[90]);    MULADD(at[35], at[89]);    MULADD(at[36], at[88]);    MULADD(at[37], at[87]);    MULADD(at[38], at[86]);    MULADD(at[39], at[85]);    MULADD(at[40], at[84]);    MULADD(at[41], at[83]);    MULADD(at[42], at[82]);    MULADD(at[43], at[81]);    MULADD(at[44], at[80]);    MULADD(at[45], at[79]);    MULADD(at[46], at[78]);    MULADD(at[47], at[77]); 
+   COMBA_STORE(C->dp[76]);
+   /* 77 */
+   COMBA_FORWARD;
+   MULADD(at[30], at[95]);    MULADD(at[31], at[94]);    MULADD(at[32], at[93]);    MULADD(at[33], at[92]);    MULADD(at[34], at[91]);    MULADD(at[35], at[90]);    MULADD(at[36], at[89]);    MULADD(at[37], at[88]);    MULADD(at[38], at[87]);    MULADD(at[39], at[86]);    MULADD(at[40], at[85]);    MULADD(at[41], at[84]);    MULADD(at[42], at[83]);    MULADD(at[43], at[82]);    MULADD(at[44], at[81]);    MULADD(at[45], at[80]);    MULADD(at[46], at[79]);    MULADD(at[47], at[78]); 
+   COMBA_STORE(C->dp[77]);
+   /* 78 */
+   COMBA_FORWARD;
+   MULADD(at[31], at[95]);    MULADD(at[32], at[94]);    MULADD(at[33], at[93]);    MULADD(at[34], at[92]);    MULADD(at[35], at[91]);    MULADD(at[36], at[90]);    MULADD(at[37], at[89]);    MULADD(at[38], at[88]);    MULADD(at[39], at[87]);    MULADD(at[40], at[86]);    MULADD(at[41], at[85]);    MULADD(at[42], at[84]);    MULADD(at[43], at[83]);    MULADD(at[44], at[82]);    MULADD(at[45], at[81]);    MULADD(at[46], at[80]);    MULADD(at[47], at[79]); 
+   COMBA_STORE(C->dp[78]);
+   /* 79 */
+   COMBA_FORWARD;
+   MULADD(at[32], at[95]);    MULADD(at[33], at[94]);    MULADD(at[34], at[93]);    MULADD(at[35], at[92]);    MULADD(at[36], at[91]);    MULADD(at[37], at[90]);    MULADD(at[38], at[89]);    MULADD(at[39], at[88]);    MULADD(at[40], at[87]);    MULADD(at[41], at[86]);    MULADD(at[42], at[85]);    MULADD(at[43], at[84]);    MULADD(at[44], at[83]);    MULADD(at[45], at[82]);    MULADD(at[46], at[81]);    MULADD(at[47], at[80]); 
+   COMBA_STORE(C->dp[79]);
+   /* 80 */
+   COMBA_FORWARD;
+   MULADD(at[33], at[95]);    MULADD(at[34], at[94]);    MULADD(at[35], at[93]);    MULADD(at[36], at[92]);    MULADD(at[37], at[91]);    MULADD(at[38], at[90]);    MULADD(at[39], at[89]);    MULADD(at[40], at[88]);    MULADD(at[41], at[87]);    MULADD(at[42], at[86]);    MULADD(at[43], at[85]);    MULADD(at[44], at[84]);    MULADD(at[45], at[83]);    MULADD(at[46], at[82]);    MULADD(at[47], at[81]); 
+   COMBA_STORE(C->dp[80]);
+   /* 81 */
+   COMBA_FORWARD;
+   MULADD(at[34], at[95]);    MULADD(at[35], at[94]);    MULADD(at[36], at[93]);    MULADD(at[37], at[92]);    MULADD(at[38], at[91]);    MULADD(at[39], at[90]);    MULADD(at[40], at[89]);    MULADD(at[41], at[88]);    MULADD(at[42], at[87]);    MULADD(at[43], at[86]);    MULADD(at[44], at[85]);    MULADD(at[45], at[84]);    MULADD(at[46], at[83]);    MULADD(at[47], at[82]); 
+   COMBA_STORE(C->dp[81]);
+   /* 82 */
+   COMBA_FORWARD;
+   MULADD(at[35], at[95]);    MULADD(at[36], at[94]);    MULADD(at[37], at[93]);    MULADD(at[38], at[92]);    MULADD(at[39], at[91]);    MULADD(at[40], at[90]);    MULADD(at[41], at[89]);    MULADD(at[42], at[88]);    MULADD(at[43], at[87]);    MULADD(at[44], at[86]);    MULADD(at[45], at[85]);    MULADD(at[46], at[84]);    MULADD(at[47], at[83]); 
+   COMBA_STORE(C->dp[82]);
+   /* 83 */
+   COMBA_FORWARD;
+   MULADD(at[36], at[95]);    MULADD(at[37], at[94]);    MULADD(at[38], at[93]);    MULADD(at[39], at[92]);    MULADD(at[40], at[91]);    MULADD(at[41], at[90]);    MULADD(at[42], at[89]);    MULADD(at[43], at[88]);    MULADD(at[44], at[87]);    MULADD(at[45], at[86]);    MULADD(at[46], at[85]);    MULADD(at[47], at[84]); 
+   COMBA_STORE(C->dp[83]);
+   /* 84 */
+   COMBA_FORWARD;
+   MULADD(at[37], at[95]);    MULADD(at[38], at[94]);    MULADD(at[39], at[93]);    MULADD(at[40], at[92]);    MULADD(at[41], at[91]);    MULADD(at[42], at[90]);    MULADD(at[43], at[89]);    MULADD(at[44], at[88]);    MULADD(at[45], at[87]);    MULADD(at[46], at[86]);    MULADD(at[47], at[85]); 
+   COMBA_STORE(C->dp[84]);
+   /* 85 */
+   COMBA_FORWARD;
+   MULADD(at[38], at[95]);    MULADD(at[39], at[94]);    MULADD(at[40], at[93]);    MULADD(at[41], at[92]);    MULADD(at[42], at[91]);    MULADD(at[43], at[90]);    MULADD(at[44], at[89]);    MULADD(at[45], at[88]);    MULADD(at[46], at[87]);    MULADD(at[47], at[86]); 
+   COMBA_STORE(C->dp[85]);
+   /* 86 */
+   COMBA_FORWARD;
+   MULADD(at[39], at[95]);    MULADD(at[40], at[94]);    MULADD(at[41], at[93]);    MULADD(at[42], at[92]);    MULADD(at[43], at[91]);    MULADD(at[44], at[90]);    MULADD(at[45], at[89]);    MULADD(at[46], at[88]);    MULADD(at[47], at[87]); 
+   COMBA_STORE(C->dp[86]);
+   /* 87 */
+   COMBA_FORWARD;
+   MULADD(at[40], at[95]);    MULADD(at[41], at[94]);    MULADD(at[42], at[93]);    MULADD(at[43], at[92]);    MULADD(at[44], at[91]);    MULADD(at[45], at[90]);    MULADD(at[46], at[89]);    MULADD(at[47], at[88]); 
+   COMBA_STORE(C->dp[87]);
+   /* 88 */
+   COMBA_FORWARD;
+   MULADD(at[41], at[95]);    MULADD(at[42], at[94]);    MULADD(at[43], at[93]);    MULADD(at[44], at[92]);    MULADD(at[45], at[91]);    MULADD(at[46], at[90]);    MULADD(at[47], at[89]); 
+   COMBA_STORE(C->dp[88]);
+   /* 89 */
+   COMBA_FORWARD;
+   MULADD(at[42], at[95]);    MULADD(at[43], at[94]);    MULADD(at[44], at[93]);    MULADD(at[45], at[92]);    MULADD(at[46], at[91]);    MULADD(at[47], at[90]); 
+   COMBA_STORE(C->dp[89]);
+   /* 90 */
+   COMBA_FORWARD;
+   MULADD(at[43], at[95]);    MULADD(at[44], at[94]);    MULADD(at[45], at[93]);    MULADD(at[46], at[92]);    MULADD(at[47], at[91]); 
+   COMBA_STORE(C->dp[90]);
+   /* 91 */
+   COMBA_FORWARD;
+   MULADD(at[44], at[95]);    MULADD(at[45], at[94]);    MULADD(at[46], at[93]);    MULADD(at[47], at[92]); 
+   COMBA_STORE(C->dp[91]);
+   /* 92 */
+   COMBA_FORWARD;
+   MULADD(at[45], at[95]);    MULADD(at[46], at[94]);    MULADD(at[47], at[93]); 
+   COMBA_STORE(C->dp[92]);
+   /* 93 */
+   COMBA_FORWARD;
+   MULADD(at[46], at[95]);    MULADD(at[47], at[94]); 
+   COMBA_STORE(C->dp[93]);
+   /* 94 */
+   COMBA_FORWARD;
+   MULADD(at[47], at[95]); 
+   COMBA_STORE(C->dp[94]);
+   COMBA_STORE2(C->dp[95]);
+   C->used = 96;
+   C->sign = A->sign ^ B->sign;
+   fp_clamp(C);
+   COMBA_FINI;
+}
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_6.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_6.i
new file mode 100644
index 0000000..165c270
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_6.i
@@ -0,0 +1,82 @@
+/* fp_mul_comba_6.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_MUL6
+void fp_mul_comba6(fp_int *A, fp_int *B, fp_int *C)
+{
+   fp_digit c0, c1, c2, at[12];
+
+   memcpy(at, A->dp, 6 * sizeof(fp_digit));
+   memcpy(at+6, B->dp, 6 * sizeof(fp_digit));
+   COMBA_START;
+
+   COMBA_CLEAR;
+   /* 0 */
+   MULADD(at[0], at[6]); 
+   COMBA_STORE(C->dp[0]);
+   /* 1 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[7]);    MULADD(at[1], at[6]); 
+   COMBA_STORE(C->dp[1]);
+   /* 2 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[8]);    MULADD(at[1], at[7]);    MULADD(at[2], at[6]); 
+   COMBA_STORE(C->dp[2]);
+   /* 3 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[9]);    MULADD(at[1], at[8]);    MULADD(at[2], at[7]);    MULADD(at[3], at[6]); 
+   COMBA_STORE(C->dp[3]);
+   /* 4 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[10]);    MULADD(at[1], at[9]);    MULADD(at[2], at[8]);    MULADD(at[3], at[7]);    MULADD(at[4], at[6]); 
+   COMBA_STORE(C->dp[4]);
+   /* 5 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[11]);    MULADD(at[1], at[10]);    MULADD(at[2], at[9]);    MULADD(at[3], at[8]);    MULADD(at[4], at[7]);    MULADD(at[5], at[6]); 
+   COMBA_STORE(C->dp[5]);
+   /* 6 */
+   COMBA_FORWARD;
+   MULADD(at[1], at[11]);    MULADD(at[2], at[10]);    MULADD(at[3], at[9]);    MULADD(at[4], at[8]);    MULADD(at[5], at[7]); 
+   COMBA_STORE(C->dp[6]);
+   /* 7 */
+   COMBA_FORWARD;
+   MULADD(at[2], at[11]);    MULADD(at[3], at[10]);    MULADD(at[4], at[9]);    MULADD(at[5], at[8]); 
+   COMBA_STORE(C->dp[7]);
+   /* 8 */
+   COMBA_FORWARD;
+   MULADD(at[3], at[11]);    MULADD(at[4], at[10]);    MULADD(at[5], at[9]); 
+   COMBA_STORE(C->dp[8]);
+   /* 9 */
+   COMBA_FORWARD;
+   MULADD(at[4], at[11]);    MULADD(at[5], at[10]); 
+   COMBA_STORE(C->dp[9]);
+   /* 10 */
+   COMBA_FORWARD;
+   MULADD(at[5], at[11]); 
+   COMBA_STORE(C->dp[10]);
+   COMBA_STORE2(C->dp[11]);
+   C->used = 12;
+   C->sign = A->sign ^ B->sign;
+   fp_clamp(C);
+   COMBA_FINI;
+}
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_64.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_64.i
new file mode 100644
index 0000000..76d7c21
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_64.i
@@ -0,0 +1,546 @@
+/* fp_mul_comba_64.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_MUL64
+void fp_mul_comba64(fp_int *A, fp_int *B, fp_int *C)
+{
+   fp_digit c0, c1, c2, at[128];
+
+   memcpy(at, A->dp, 64 * sizeof(fp_digit));
+   memcpy(at+64, B->dp, 64 * sizeof(fp_digit));
+   COMBA_START;
+
+   COMBA_CLEAR;
+   /* 0 */
+   MULADD(at[0], at[64]); 
+   COMBA_STORE(C->dp[0]);
+   /* 1 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[65]);    MULADD(at[1], at[64]); 
+   COMBA_STORE(C->dp[1]);
+   /* 2 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[66]);    MULADD(at[1], at[65]);    MULADD(at[2], at[64]); 
+   COMBA_STORE(C->dp[2]);
+   /* 3 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[67]);    MULADD(at[1], at[66]);    MULADD(at[2], at[65]);    MULADD(at[3], at[64]); 
+   COMBA_STORE(C->dp[3]);
+   /* 4 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[68]);    MULADD(at[1], at[67]);    MULADD(at[2], at[66]);    MULADD(at[3], at[65]);    MULADD(at[4], at[64]); 
+   COMBA_STORE(C->dp[4]);
+   /* 5 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[69]);    MULADD(at[1], at[68]);    MULADD(at[2], at[67]);    MULADD(at[3], at[66]);    MULADD(at[4], at[65]);    MULADD(at[5], at[64]); 
+   COMBA_STORE(C->dp[5]);
+   /* 6 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[70]);    MULADD(at[1], at[69]);    MULADD(at[2], at[68]);    MULADD(at[3], at[67]);    MULADD(at[4], at[66]);    MULADD(at[5], at[65]);    MULADD(at[6], at[64]); 
+   COMBA_STORE(C->dp[6]);
+   /* 7 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[71]);    MULADD(at[1], at[70]);    MULADD(at[2], at[69]);    MULADD(at[3], at[68]);    MULADD(at[4], at[67]);    MULADD(at[5], at[66]);    MULADD(at[6], at[65]);    MULADD(at[7], at[64]); 
+   COMBA_STORE(C->dp[7]);
+   /* 8 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[72]);    MULADD(at[1], at[71]);    MULADD(at[2], at[70]);    MULADD(at[3], at[69]);    MULADD(at[4], at[68]);    MULADD(at[5], at[67]);    MULADD(at[6], at[66]);    MULADD(at[7], at[65]);    MULADD(at[8], at[64]); 
+   COMBA_STORE(C->dp[8]);
+   /* 9 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[73]);    MULADD(at[1], at[72]);    MULADD(at[2], at[71]);    MULADD(at[3], at[70]);    MULADD(at[4], at[69]);    MULADD(at[5], at[68]);    MULADD(at[6], at[67]);    MULADD(at[7], at[66]);    MULADD(at[8], at[65]);    MULADD(at[9], at[64]); 
+   COMBA_STORE(C->dp[9]);
+   /* 10 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[74]);    MULADD(at[1], at[73]);    MULADD(at[2], at[72]);    MULADD(at[3], at[71]);    MULADD(at[4], at[70]);    MULADD(at[5], at[69]);    MULADD(at[6], at[68]);    MULADD(at[7], at[67]);    MULADD(at[8], at[66]);    MULADD(at[9], at[65]);    MULADD(at[10], at[64]); 
+   COMBA_STORE(C->dp[10]);
+   /* 11 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[75]);    MULADD(at[1], at[74]);    MULADD(at[2], at[73]);    MULADD(at[3], at[72]);    MULADD(at[4], at[71]);    MULADD(at[5], at[70]);    MULADD(at[6], at[69]);    MULADD(at[7], at[68]);    MULADD(at[8], at[67]);    MULADD(at[9], at[66]);    MULADD(at[10], at[65]);    MULADD(at[11], at[64]); 
+   COMBA_STORE(C->dp[11]);
+   /* 12 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[76]);    MULADD(at[1], at[75]);    MULADD(at[2], at[74]);    MULADD(at[3], at[73]);    MULADD(at[4], at[72]);    MULADD(at[5], at[71]);    MULADD(at[6], at[70]);    MULADD(at[7], at[69]);    MULADD(at[8], at[68]);    MULADD(at[9], at[67]);    MULADD(at[10], at[66]);    MULADD(at[11], at[65]);    MULADD(at[12], at[64]); 
+   COMBA_STORE(C->dp[12]);
+   /* 13 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[77]);    MULADD(at[1], at[76]);    MULADD(at[2], at[75]);    MULADD(at[3], at[74]);    MULADD(at[4], at[73]);    MULADD(at[5], at[72]);    MULADD(at[6], at[71]);    MULADD(at[7], at[70]);    MULADD(at[8], at[69]);    MULADD(at[9], at[68]);    MULADD(at[10], at[67]);    MULADD(at[11], at[66]);    MULADD(at[12], at[65]);    MULADD(at[13], at[64]); 
+   COMBA_STORE(C->dp[13]);
+   /* 14 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[78]);    MULADD(at[1], at[77]);    MULADD(at[2], at[76]);    MULADD(at[3], at[75]);    MULADD(at[4], at[74]);    MULADD(at[5], at[73]);    MULADD(at[6], at[72]);    MULADD(at[7], at[71]);    MULADD(at[8], at[70]);    MULADD(at[9], at[69]);    MULADD(at[10], at[68]);    MULADD(at[11], at[67]);    MULADD(at[12], at[66]);    MULADD(at[13], at[65]);    MULADD(at[14], at[64]); 
+   COMBA_STORE(C->dp[14]);
+   /* 15 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[79]);    MULADD(at[1], at[78]);    MULADD(at[2], at[77]);    MULADD(at[3], at[76]);    MULADD(at[4], at[75]);    MULADD(at[5], at[74]);    MULADD(at[6], at[73]);    MULADD(at[7], at[72]);    MULADD(at[8], at[71]);    MULADD(at[9], at[70]);    MULADD(at[10], at[69]);    MULADD(at[11], at[68]);    MULADD(at[12], at[67]);    MULADD(at[13], at[66]);    MULADD(at[14], at[65]);    MULADD(at[15], at[64]); 
+   COMBA_STORE(C->dp[15]);
+   /* 16 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[80]);    MULADD(at[1], at[79]);    MULADD(at[2], at[78]);    MULADD(at[3], at[77]);    MULADD(at[4], at[76]);    MULADD(at[5], at[75]);    MULADD(at[6], at[74]);    MULADD(at[7], at[73]);    MULADD(at[8], at[72]);    MULADD(at[9], at[71]);    MULADD(at[10], at[70]);    MULADD(at[11], at[69]);    MULADD(at[12], at[68]);    MULADD(at[13], at[67]);    MULADD(at[14], at[66]);    MULADD(at[15], at[65]);    MULADD(at[16], at[64]); 
+   COMBA_STORE(C->dp[16]);
+   /* 17 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[81]);    MULADD(at[1], at[80]);    MULADD(at[2], at[79]);    MULADD(at[3], at[78]);    MULADD(at[4], at[77]);    MULADD(at[5], at[76]);    MULADD(at[6], at[75]);    MULADD(at[7], at[74]);    MULADD(at[8], at[73]);    MULADD(at[9], at[72]);    MULADD(at[10], at[71]);    MULADD(at[11], at[70]);    MULADD(at[12], at[69]);    MULADD(at[13], at[68]);    MULADD(at[14], at[67]);    MULADD(at[15], at[66]);    MULADD(at[16], at[65]);    MULADD(at[17], at[64]); 
+   COMBA_STORE(C->dp[17]);
+   /* 18 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[82]);    MULADD(at[1], at[81]);    MULADD(at[2], at[80]);    MULADD(at[3], at[79]);    MULADD(at[4], at[78]);    MULADD(at[5], at[77]);    MULADD(at[6], at[76]);    MULADD(at[7], at[75]);    MULADD(at[8], at[74]);    MULADD(at[9], at[73]);    MULADD(at[10], at[72]);    MULADD(at[11], at[71]);    MULADD(at[12], at[70]);    MULADD(at[13], at[69]);    MULADD(at[14], at[68]);    MULADD(at[15], at[67]);    MULADD(at[16], at[66]);    MULADD(at[17], at[65]);    MULADD(at[18], at[64]); 
+   COMBA_STORE(C->dp[18]);
+   /* 19 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[83]);    MULADD(at[1], at[82]);    MULADD(at[2], at[81]);    MULADD(at[3], at[80]);    MULADD(at[4], at[79]);    MULADD(at[5], at[78]);    MULADD(at[6], at[77]);    MULADD(at[7], at[76]);    MULADD(at[8], at[75]);    MULADD(at[9], at[74]);    MULADD(at[10], at[73]);    MULADD(at[11], at[72]);    MULADD(at[12], at[71]);    MULADD(at[13], at[70]);    MULADD(at[14], at[69]);    MULADD(at[15], at[68]);    MULADD(at[16], at[67]);    MULADD(at[17], at[66]);    MULADD(at[18], at[65]);    MULADD(at[19], at[64]); 
+   COMBA_STORE(C->dp[19]);
+   /* 20 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[84]);    MULADD(at[1], at[83]);    MULADD(at[2], at[82]);    MULADD(at[3], at[81]);    MULADD(at[4], at[80]);    MULADD(at[5], at[79]);    MULADD(at[6], at[78]);    MULADD(at[7], at[77]);    MULADD(at[8], at[76]);    MULADD(at[9], at[75]);    MULADD(at[10], at[74]);    MULADD(at[11], at[73]);    MULADD(at[12], at[72]);    MULADD(at[13], at[71]);    MULADD(at[14], at[70]);    MULADD(at[15], at[69]);    MULADD(at[16], at[68]);    MULADD(at[17], at[67]);    MULADD(at[18], at[66]);    MULADD(at[19], at[65]);    MULADD(at[20], at[64]); 
+   COMBA_STORE(C->dp[20]);
+   /* 21 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[85]);    MULADD(at[1], at[84]);    MULADD(at[2], at[83]);    MULADD(at[3], at[82]);    MULADD(at[4], at[81]);    MULADD(at[5], at[80]);    MULADD(at[6], at[79]);    MULADD(at[7], at[78]);    MULADD(at[8], at[77]);    MULADD(at[9], at[76]);    MULADD(at[10], at[75]);    MULADD(at[11], at[74]);    MULADD(at[12], at[73]);    MULADD(at[13], at[72]);    MULADD(at[14], at[71]);    MULADD(at[15], at[70]);    MULADD(at[16], at[69]);    MULADD(at[17], at[68]);    MULADD(at[18], at[67]);    MULADD(at[19], at[66]);    MULADD(at[20], at[65]);    MULADD(at[21], at[64]); 
+   COMBA_STORE(C->dp[21]);
+   /* 22 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[86]);    MULADD(at[1], at[85]);    MULADD(at[2], at[84]);    MULADD(at[3], at[83]);    MULADD(at[4], at[82]);    MULADD(at[5], at[81]);    MULADD(at[6], at[80]);    MULADD(at[7], at[79]);    MULADD(at[8], at[78]);    MULADD(at[9], at[77]);    MULADD(at[10], at[76]);    MULADD(at[11], at[75]);    MULADD(at[12], at[74]);    MULADD(at[13], at[73]);    MULADD(at[14], at[72]);    MULADD(at[15], at[71]);    MULADD(at[16], at[70]);    MULADD(at[17], at[69]);    MULADD(at[18], at[68]);    MULADD(at[19], at[67]);    MULADD(at[20], at[66]);    MULADD(at[21], at[65]);    MULADD(at[22], at[64]); 
+   COMBA_STORE(C->dp[22]);
+   /* 23 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[87]);    MULADD(at[1], at[86]);    MULADD(at[2], at[85]);    MULADD(at[3], at[84]);    MULADD(at[4], at[83]);    MULADD(at[5], at[82]);    MULADD(at[6], at[81]);    MULADD(at[7], at[80]);    MULADD(at[8], at[79]);    MULADD(at[9], at[78]);    MULADD(at[10], at[77]);    MULADD(at[11], at[76]);    MULADD(at[12], at[75]);    MULADD(at[13], at[74]);    MULADD(at[14], at[73]);    MULADD(at[15], at[72]);    MULADD(at[16], at[71]);    MULADD(at[17], at[70]);    MULADD(at[18], at[69]);    MULADD(at[19], at[68]);    MULADD(at[20], at[67]);    MULADD(at[21], at[66]);    MULADD(at[22], at[65]);    MULADD(at[23], at[64]); 
+   COMBA_STORE(C->dp[23]);
+   /* 24 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[88]);    MULADD(at[1], at[87]);    MULADD(at[2], at[86]);    MULADD(at[3], at[85]);    MULADD(at[4], at[84]);    MULADD(at[5], at[83]);    MULADD(at[6], at[82]);    MULADD(at[7], at[81]);    MULADD(at[8], at[80]);    MULADD(at[9], at[79]);    MULADD(at[10], at[78]);    MULADD(at[11], at[77]);    MULADD(at[12], at[76]);    MULADD(at[13], at[75]);    MULADD(at[14], at[74]);    MULADD(at[15], at[73]);    MULADD(at[16], at[72]);    MULADD(at[17], at[71]);    MULADD(at[18], at[70]);    MULADD(at[19], at[69]);    MULADD(at[20], at[68]);    MULADD(at[21], at[67]);    MULADD(at[22], at[66]);    MULADD(at[23], at[65]);    MULADD(at[24], at[64]); 
+   COMBA_STORE(C->dp[24]);
+   /* 25 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[89]);    MULADD(at[1], at[88]);    MULADD(at[2], at[87]);    MULADD(at[3], at[86]);    MULADD(at[4], at[85]);    MULADD(at[5], at[84]);    MULADD(at[6], at[83]);    MULADD(at[7], at[82]);    MULADD(at[8], at[81]);    MULADD(at[9], at[80]);    MULADD(at[10], at[79]);    MULADD(at[11], at[78]);    MULADD(at[12], at[77]);    MULADD(at[13], at[76]);    MULADD(at[14], at[75]);    MULADD(at[15], at[74]);    MULADD(at[16], at[73]);    MULADD(at[17], at[72]);    MULADD(at[18], at[71]);    MULADD(at[19], at[70]);    MULADD(at[20], at[69]);    MULADD(at[21], at[68]);    MULADD(at[22], at[67]);    MULADD(at[23], at[66]);    MULADD(at[24], at[65]);    MULADD(at[25], at[64]); 
+   COMBA_STORE(C->dp[25]);
+   /* 26 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[90]);    MULADD(at[1], at[89]);    MULADD(at[2], at[88]);    MULADD(at[3], at[87]);    MULADD(at[4], at[86]);    MULADD(at[5], at[85]);    MULADD(at[6], at[84]);    MULADD(at[7], at[83]);    MULADD(at[8], at[82]);    MULADD(at[9], at[81]);    MULADD(at[10], at[80]);    MULADD(at[11], at[79]);    MULADD(at[12], at[78]);    MULADD(at[13], at[77]);    MULADD(at[14], at[76]);    MULADD(at[15], at[75]);    MULADD(at[16], at[74]);    MULADD(at[17], at[73]);    MULADD(at[18], at[72]);    MULADD(at[19], at[71]);    MULADD(at[20], at[70]);    MULADD(at[21], at[69]);    MULADD(at[22], at[68]);    MULADD(at[23], at[67]);    MULADD(at[24], at[66]);    MULADD(at[25], at[65]);    MULADD(at[26], at[64]); 
+   COMBA_STORE(C->dp[26]);
+   /* 27 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[91]);    MULADD(at[1], at[90]);    MULADD(at[2], at[89]);    MULADD(at[3], at[88]);    MULADD(at[4], at[87]);    MULADD(at[5], at[86]);    MULADD(at[6], at[85]);    MULADD(at[7], at[84]);    MULADD(at[8], at[83]);    MULADD(at[9], at[82]);    MULADD(at[10], at[81]);    MULADD(at[11], at[80]);    MULADD(at[12], at[79]);    MULADD(at[13], at[78]);    MULADD(at[14], at[77]);    MULADD(at[15], at[76]);    MULADD(at[16], at[75]);    MULADD(at[17], at[74]);    MULADD(at[18], at[73]);    MULADD(at[19], at[72]);    MULADD(at[20], at[71]);    MULADD(at[21], at[70]);    MULADD(at[22], at[69]);    MULADD(at[23], at[68]);    MULADD(at[24], at[67]);    MULADD(at[25], at[66]);    MULADD(at[26], at[65]);    MULADD(at[27], at[64]); 
+   COMBA_STORE(C->dp[27]);
+   /* 28 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[92]);    MULADD(at[1], at[91]);    MULADD(at[2], at[90]);    MULADD(at[3], at[89]);    MULADD(at[4], at[88]);    MULADD(at[5], at[87]);    MULADD(at[6], at[86]);    MULADD(at[7], at[85]);    MULADD(at[8], at[84]);    MULADD(at[9], at[83]);    MULADD(at[10], at[82]);    MULADD(at[11], at[81]);    MULADD(at[12], at[80]);    MULADD(at[13], at[79]);    MULADD(at[14], at[78]);    MULADD(at[15], at[77]);    MULADD(at[16], at[76]);    MULADD(at[17], at[75]);    MULADD(at[18], at[74]);    MULADD(at[19], at[73]);    MULADD(at[20], at[72]);    MULADD(at[21], at[71]);    MULADD(at[22], at[70]);    MULADD(at[23], at[69]);    MULADD(at[24], at[68]);    MULADD(at[25], at[67]);    MULADD(at[26], at[66]);    MULADD(at[27], at[65]);    MULADD(at[28], at[64]); 
+   COMBA_STORE(C->dp[28]);
+   /* 29 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[93]);    MULADD(at[1], at[92]);    MULADD(at[2], at[91]);    MULADD(at[3], at[90]);    MULADD(at[4], at[89]);    MULADD(at[5], at[88]);    MULADD(at[6], at[87]);    MULADD(at[7], at[86]);    MULADD(at[8], at[85]);    MULADD(at[9], at[84]);    MULADD(at[10], at[83]);    MULADD(at[11], at[82]);    MULADD(at[12], at[81]);    MULADD(at[13], at[80]);    MULADD(at[14], at[79]);    MULADD(at[15], at[78]);    MULADD(at[16], at[77]);    MULADD(at[17], at[76]);    MULADD(at[18], at[75]);    MULADD(at[19], at[74]);    MULADD(at[20], at[73]);    MULADD(at[21], at[72]);    MULADD(at[22], at[71]);    MULADD(at[23], at[70]);    MULADD(at[24], at[69]);    MULADD(at[25], at[68]);    MULADD(at[26], at[67]);    MULADD(at[27], at[66]);    MULADD(at[28], at[65]);    MULADD(at[29], at[64]); 
+   COMBA_STORE(C->dp[29]);
+   /* 30 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[94]);    MULADD(at[1], at[93]);    MULADD(at[2], at[92]);    MULADD(at[3], at[91]);    MULADD(at[4], at[90]);    MULADD(at[5], at[89]);    MULADD(at[6], at[88]);    MULADD(at[7], at[87]);    MULADD(at[8], at[86]);    MULADD(at[9], at[85]);    MULADD(at[10], at[84]);    MULADD(at[11], at[83]);    MULADD(at[12], at[82]);    MULADD(at[13], at[81]);    MULADD(at[14], at[80]);    MULADD(at[15], at[79]);    MULADD(at[16], at[78]);    MULADD(at[17], at[77]);    MULADD(at[18], at[76]);    MULADD(at[19], at[75]);    MULADD(at[20], at[74]);    MULADD(at[21], at[73]);    MULADD(at[22], at[72]);    MULADD(at[23], at[71]);    MULADD(at[24], at[70]);    MULADD(at[25], at[69]);    MULADD(at[26], at[68]);    MULADD(at[27], at[67]);    MULADD(at[28], at[66]);    MULADD(at[29], at[65]);    MULADD(at[30], at[64]); 
+   COMBA_STORE(C->dp[30]);
+   /* 31 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[95]);    MULADD(at[1], at[94]);    MULADD(at[2], at[93]);    MULADD(at[3], at[92]);    MULADD(at[4], at[91]);    MULADD(at[5], at[90]);    MULADD(at[6], at[89]);    MULADD(at[7], at[88]);    MULADD(at[8], at[87]);    MULADD(at[9], at[86]);    MULADD(at[10], at[85]);    MULADD(at[11], at[84]);    MULADD(at[12], at[83]);    MULADD(at[13], at[82]);    MULADD(at[14], at[81]);    MULADD(at[15], at[80]);    MULADD(at[16], at[79]);    MULADD(at[17], at[78]);    MULADD(at[18], at[77]);    MULADD(at[19], at[76]);    MULADD(at[20], at[75]);    MULADD(at[21], at[74]);    MULADD(at[22], at[73]);    MULADD(at[23], at[72]);    MULADD(at[24], at[71]);    MULADD(at[25], at[70]);    MULADD(at[26], at[69]);    MULADD(at[27], at[68]);    MULADD(at[28], at[67]);    MULADD(at[29], at[66]);    MULADD(at[30], at[65]);    MULADD(at[31], at[64]); 
+   COMBA_STORE(C->dp[31]);
+   /* 32 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[96]);    MULADD(at[1], at[95]);    MULADD(at[2], at[94]);    MULADD(at[3], at[93]);    MULADD(at[4], at[92]);    MULADD(at[5], at[91]);    MULADD(at[6], at[90]);    MULADD(at[7], at[89]);    MULADD(at[8], at[88]);    MULADD(at[9], at[87]);    MULADD(at[10], at[86]);    MULADD(at[11], at[85]);    MULADD(at[12], at[84]);    MULADD(at[13], at[83]);    MULADD(at[14], at[82]);    MULADD(at[15], at[81]);    MULADD(at[16], at[80]);    MULADD(at[17], at[79]);    MULADD(at[18], at[78]);    MULADD(at[19], at[77]);    MULADD(at[20], at[76]);    MULADD(at[21], at[75]);    MULADD(at[22], at[74]);    MULADD(at[23], at[73]);    MULADD(at[24], at[72]);    MULADD(at[25], at[71]);    MULADD(at[26], at[70]);    MULADD(at[27], at[69]);    MULADD(at[28], at[68]);    MULADD(at[29], at[67]);    MULADD(at[30], at[66]);    MULADD(at[31], at[65]);    MULADD(at[32], at[64]); 
+   COMBA_STORE(C->dp[32]);
+   /* 33 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[97]);    MULADD(at[1], at[96]);    MULADD(at[2], at[95]);    MULADD(at[3], at[94]);    MULADD(at[4], at[93]);    MULADD(at[5], at[92]);    MULADD(at[6], at[91]);    MULADD(at[7], at[90]);    MULADD(at[8], at[89]);    MULADD(at[9], at[88]);    MULADD(at[10], at[87]);    MULADD(at[11], at[86]);    MULADD(at[12], at[85]);    MULADD(at[13], at[84]);    MULADD(at[14], at[83]);    MULADD(at[15], at[82]);    MULADD(at[16], at[81]);    MULADD(at[17], at[80]);    MULADD(at[18], at[79]);    MULADD(at[19], at[78]);    MULADD(at[20], at[77]);    MULADD(at[21], at[76]);    MULADD(at[22], at[75]);    MULADD(at[23], at[74]);    MULADD(at[24], at[73]);    MULADD(at[25], at[72]);    MULADD(at[26], at[71]);    MULADD(at[27], at[70]);    MULADD(at[28], at[69]);    MULADD(at[29], at[68]);    MULADD(at[30], at[67]);    MULADD(at[31], at[66]);    MULADD(at[32], at[65]);    MULADD(at[33], at[64]); 
+   COMBA_STORE(C->dp[33]);
+   /* 34 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[98]);    MULADD(at[1], at[97]);    MULADD(at[2], at[96]);    MULADD(at[3], at[95]);    MULADD(at[4], at[94]);    MULADD(at[5], at[93]);    MULADD(at[6], at[92]);    MULADD(at[7], at[91]);    MULADD(at[8], at[90]);    MULADD(at[9], at[89]);    MULADD(at[10], at[88]);    MULADD(at[11], at[87]);    MULADD(at[12], at[86]);    MULADD(at[13], at[85]);    MULADD(at[14], at[84]);    MULADD(at[15], at[83]);    MULADD(at[16], at[82]);    MULADD(at[17], at[81]);    MULADD(at[18], at[80]);    MULADD(at[19], at[79]);    MULADD(at[20], at[78]);    MULADD(at[21], at[77]);    MULADD(at[22], at[76]);    MULADD(at[23], at[75]);    MULADD(at[24], at[74]);    MULADD(at[25], at[73]);    MULADD(at[26], at[72]);    MULADD(at[27], at[71]);    MULADD(at[28], at[70]);    MULADD(at[29], at[69]);    MULADD(at[30], at[68]);    MULADD(at[31], at[67]);    MULADD(at[32], at[66]);    MULADD(at[33], at[65]);    MULADD(at[34], at[64]); 
+   COMBA_STORE(C->dp[34]);
+   /* 35 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[99]);    MULADD(at[1], at[98]);    MULADD(at[2], at[97]);    MULADD(at[3], at[96]);    MULADD(at[4], at[95]);    MULADD(at[5], at[94]);    MULADD(at[6], at[93]);    MULADD(at[7], at[92]);    MULADD(at[8], at[91]);    MULADD(at[9], at[90]);    MULADD(at[10], at[89]);    MULADD(at[11], at[88]);    MULADD(at[12], at[87]);    MULADD(at[13], at[86]);    MULADD(at[14], at[85]);    MULADD(at[15], at[84]);    MULADD(at[16], at[83]);    MULADD(at[17], at[82]);    MULADD(at[18], at[81]);    MULADD(at[19], at[80]);    MULADD(at[20], at[79]);    MULADD(at[21], at[78]);    MULADD(at[22], at[77]);    MULADD(at[23], at[76]);    MULADD(at[24], at[75]);    MULADD(at[25], at[74]);    MULADD(at[26], at[73]);    MULADD(at[27], at[72]);    MULADD(at[28], at[71]);    MULADD(at[29], at[70]);    MULADD(at[30], at[69]);    MULADD(at[31], at[68]);    MULADD(at[32], at[67]);    MULADD(at[33], at[66]);    MULADD(at[34], at[65]);    MULADD(at[35], at[64]); 
+   COMBA_STORE(C->dp[35]);
+   /* 36 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[100]);    MULADD(at[1], at[99]);    MULADD(at[2], at[98]);    MULADD(at[3], at[97]);    MULADD(at[4], at[96]);    MULADD(at[5], at[95]);    MULADD(at[6], at[94]);    MULADD(at[7], at[93]);    MULADD(at[8], at[92]);    MULADD(at[9], at[91]);    MULADD(at[10], at[90]);    MULADD(at[11], at[89]);    MULADD(at[12], at[88]);    MULADD(at[13], at[87]);    MULADD(at[14], at[86]);    MULADD(at[15], at[85]);    MULADD(at[16], at[84]);    MULADD(at[17], at[83]);    MULADD(at[18], at[82]);    MULADD(at[19], at[81]);    MULADD(at[20], at[80]);    MULADD(at[21], at[79]);    MULADD(at[22], at[78]);    MULADD(at[23], at[77]);    MULADD(at[24], at[76]);    MULADD(at[25], at[75]);    MULADD(at[26], at[74]);    MULADD(at[27], at[73]);    MULADD(at[28], at[72]);    MULADD(at[29], at[71]);    MULADD(at[30], at[70]);    MULADD(at[31], at[69]);    MULADD(at[32], at[68]);    MULADD(at[33], at[67]);    MULADD(at[34], at[66]);    MULADD(at[35], at[65]);    MULADD(at[36], at[64]); 
+   COMBA_STORE(C->dp[36]);
+   /* 37 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[101]);    MULADD(at[1], at[100]);    MULADD(at[2], at[99]);    MULADD(at[3], at[98]);    MULADD(at[4], at[97]);    MULADD(at[5], at[96]);    MULADD(at[6], at[95]);    MULADD(at[7], at[94]);    MULADD(at[8], at[93]);    MULADD(at[9], at[92]);    MULADD(at[10], at[91]);    MULADD(at[11], at[90]);    MULADD(at[12], at[89]);    MULADD(at[13], at[88]);    MULADD(at[14], at[87]);    MULADD(at[15], at[86]);    MULADD(at[16], at[85]);    MULADD(at[17], at[84]);    MULADD(at[18], at[83]);    MULADD(at[19], at[82]);    MULADD(at[20], at[81]);    MULADD(at[21], at[80]);    MULADD(at[22], at[79]);    MULADD(at[23], at[78]);    MULADD(at[24], at[77]);    MULADD(at[25], at[76]);    MULADD(at[26], at[75]);    MULADD(at[27], at[74]);    MULADD(at[28], at[73]);    MULADD(at[29], at[72]);    MULADD(at[30], at[71]);    MULADD(at[31], at[70]);    MULADD(at[32], at[69]);    MULADD(at[33], at[68]);    MULADD(at[34], at[67]);    MULADD(at[35], at[66]);    MULADD(at[36], at[65]);    MULADD(at[37], at[64]); 
+   COMBA_STORE(C->dp[37]);
+   /* 38 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[102]);    MULADD(at[1], at[101]);    MULADD(at[2], at[100]);    MULADD(at[3], at[99]);    MULADD(at[4], at[98]);    MULADD(at[5], at[97]);    MULADD(at[6], at[96]);    MULADD(at[7], at[95]);    MULADD(at[8], at[94]);    MULADD(at[9], at[93]);    MULADD(at[10], at[92]);    MULADD(at[11], at[91]);    MULADD(at[12], at[90]);    MULADD(at[13], at[89]);    MULADD(at[14], at[88]);    MULADD(at[15], at[87]);    MULADD(at[16], at[86]);    MULADD(at[17], at[85]);    MULADD(at[18], at[84]);    MULADD(at[19], at[83]);    MULADD(at[20], at[82]);    MULADD(at[21], at[81]);    MULADD(at[22], at[80]);    MULADD(at[23], at[79]);    MULADD(at[24], at[78]);    MULADD(at[25], at[77]);    MULADD(at[26], at[76]);    MULADD(at[27], at[75]);    MULADD(at[28], at[74]);    MULADD(at[29], at[73]);    MULADD(at[30], at[72]);    MULADD(at[31], at[71]);    MULADD(at[32], at[70]);    MULADD(at[33], at[69]);    MULADD(at[34], at[68]);    MULADD(at[35], at[67]);    MULADD(at[36], at[66]);    MULADD(at[37], at[65]);    MULADD(at[38], at[64]); 
+   COMBA_STORE(C->dp[38]);
+   /* 39 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[103]);    MULADD(at[1], at[102]);    MULADD(at[2], at[101]);    MULADD(at[3], at[100]);    MULADD(at[4], at[99]);    MULADD(at[5], at[98]);    MULADD(at[6], at[97]);    MULADD(at[7], at[96]);    MULADD(at[8], at[95]);    MULADD(at[9], at[94]);    MULADD(at[10], at[93]);    MULADD(at[11], at[92]);    MULADD(at[12], at[91]);    MULADD(at[13], at[90]);    MULADD(at[14], at[89]);    MULADD(at[15], at[88]);    MULADD(at[16], at[87]);    MULADD(at[17], at[86]);    MULADD(at[18], at[85]);    MULADD(at[19], at[84]);    MULADD(at[20], at[83]);    MULADD(at[21], at[82]);    MULADD(at[22], at[81]);    MULADD(at[23], at[80]);    MULADD(at[24], at[79]);    MULADD(at[25], at[78]);    MULADD(at[26], at[77]);    MULADD(at[27], at[76]);    MULADD(at[28], at[75]);    MULADD(at[29], at[74]);    MULADD(at[30], at[73]);    MULADD(at[31], at[72]);    MULADD(at[32], at[71]);    MULADD(at[33], at[70]);    MULADD(at[34], at[69]);    MULADD(at[35], at[68]);    MULADD(at[36], at[67]);    MULADD(at[37], at[66]);    MULADD(at[38], at[65]);    MULADD(at[39], at[64]); 
+   COMBA_STORE(C->dp[39]);
+   /* 40 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[104]);    MULADD(at[1], at[103]);    MULADD(at[2], at[102]);    MULADD(at[3], at[101]);    MULADD(at[4], at[100]);    MULADD(at[5], at[99]);    MULADD(at[6], at[98]);    MULADD(at[7], at[97]);    MULADD(at[8], at[96]);    MULADD(at[9], at[95]);    MULADD(at[10], at[94]);    MULADD(at[11], at[93]);    MULADD(at[12], at[92]);    MULADD(at[13], at[91]);    MULADD(at[14], at[90]);    MULADD(at[15], at[89]);    MULADD(at[16], at[88]);    MULADD(at[17], at[87]);    MULADD(at[18], at[86]);    MULADD(at[19], at[85]);    MULADD(at[20], at[84]);    MULADD(at[21], at[83]);    MULADD(at[22], at[82]);    MULADD(at[23], at[81]);    MULADD(at[24], at[80]);    MULADD(at[25], at[79]);    MULADD(at[26], at[78]);    MULADD(at[27], at[77]);    MULADD(at[28], at[76]);    MULADD(at[29], at[75]);    MULADD(at[30], at[74]);    MULADD(at[31], at[73]);    MULADD(at[32], at[72]);    MULADD(at[33], at[71]);    MULADD(at[34], at[70]);    MULADD(at[35], at[69]);    MULADD(at[36], at[68]);    MULADD(at[37], at[67]);    MULADD(at[38], at[66]);    MULADD(at[39], at[65]);    MULADD(at[40], at[64]); 
+   COMBA_STORE(C->dp[40]);
+   /* 41 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[105]);    MULADD(at[1], at[104]);    MULADD(at[2], at[103]);    MULADD(at[3], at[102]);    MULADD(at[4], at[101]);    MULADD(at[5], at[100]);    MULADD(at[6], at[99]);    MULADD(at[7], at[98]);    MULADD(at[8], at[97]);    MULADD(at[9], at[96]);    MULADD(at[10], at[95]);    MULADD(at[11], at[94]);    MULADD(at[12], at[93]);    MULADD(at[13], at[92]);    MULADD(at[14], at[91]);    MULADD(at[15], at[90]);    MULADD(at[16], at[89]);    MULADD(at[17], at[88]);    MULADD(at[18], at[87]);    MULADD(at[19], at[86]);    MULADD(at[20], at[85]);    MULADD(at[21], at[84]);    MULADD(at[22], at[83]);    MULADD(at[23], at[82]);    MULADD(at[24], at[81]);    MULADD(at[25], at[80]);    MULADD(at[26], at[79]);    MULADD(at[27], at[78]);    MULADD(at[28], at[77]);    MULADD(at[29], at[76]);    MULADD(at[30], at[75]);    MULADD(at[31], at[74]);    MULADD(at[32], at[73]);    MULADD(at[33], at[72]);    MULADD(at[34], at[71]);    MULADD(at[35], at[70]);    MULADD(at[36], at[69]);    MULADD(at[37], at[68]);    MULADD(at[38], at[67]);    MULADD(at[39], at[66]);    MULADD(at[40], at[65]);    MULADD(at[41], at[64]); 
+   COMBA_STORE(C->dp[41]);
+   /* 42 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[106]);    MULADD(at[1], at[105]);    MULADD(at[2], at[104]);    MULADD(at[3], at[103]);    MULADD(at[4], at[102]);    MULADD(at[5], at[101]);    MULADD(at[6], at[100]);    MULADD(at[7], at[99]);    MULADD(at[8], at[98]);    MULADD(at[9], at[97]);    MULADD(at[10], at[96]);    MULADD(at[11], at[95]);    MULADD(at[12], at[94]);    MULADD(at[13], at[93]);    MULADD(at[14], at[92]);    MULADD(at[15], at[91]);    MULADD(at[16], at[90]);    MULADD(at[17], at[89]);    MULADD(at[18], at[88]);    MULADD(at[19], at[87]);    MULADD(at[20], at[86]);    MULADD(at[21], at[85]);    MULADD(at[22], at[84]);    MULADD(at[23], at[83]);    MULADD(at[24], at[82]);    MULADD(at[25], at[81]);    MULADD(at[26], at[80]);    MULADD(at[27], at[79]);    MULADD(at[28], at[78]);    MULADD(at[29], at[77]);    MULADD(at[30], at[76]);    MULADD(at[31], at[75]);    MULADD(at[32], at[74]);    MULADD(at[33], at[73]);    MULADD(at[34], at[72]);    MULADD(at[35], at[71]);    MULADD(at[36], at[70]);    MULADD(at[37], at[69]);    MULADD(at[38], at[68]);    MULADD(at[39], at[67]);    MULADD(at[40], at[66]);    MULADD(at[41], at[65]);    MULADD(at[42], at[64]); 
+   COMBA_STORE(C->dp[42]);
+   /* 43 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[107]);    MULADD(at[1], at[106]);    MULADD(at[2], at[105]);    MULADD(at[3], at[104]);    MULADD(at[4], at[103]);    MULADD(at[5], at[102]);    MULADD(at[6], at[101]);    MULADD(at[7], at[100]);    MULADD(at[8], at[99]);    MULADD(at[9], at[98]);    MULADD(at[10], at[97]);    MULADD(at[11], at[96]);    MULADD(at[12], at[95]);    MULADD(at[13], at[94]);    MULADD(at[14], at[93]);    MULADD(at[15], at[92]);    MULADD(at[16], at[91]);    MULADD(at[17], at[90]);    MULADD(at[18], at[89]);    MULADD(at[19], at[88]);    MULADD(at[20], at[87]);    MULADD(at[21], at[86]);    MULADD(at[22], at[85]);    MULADD(at[23], at[84]);    MULADD(at[24], at[83]);    MULADD(at[25], at[82]);    MULADD(at[26], at[81]);    MULADD(at[27], at[80]);    MULADD(at[28], at[79]);    MULADD(at[29], at[78]);    MULADD(at[30], at[77]);    MULADD(at[31], at[76]);    MULADD(at[32], at[75]);    MULADD(at[33], at[74]);    MULADD(at[34], at[73]);    MULADD(at[35], at[72]);    MULADD(at[36], at[71]);    MULADD(at[37], at[70]);    MULADD(at[38], at[69]);    MULADD(at[39], at[68]);    MULADD(at[40], at[67]);    MULADD(at[41], at[66]);    MULADD(at[42], at[65]);    MULADD(at[43], at[64]); 
+   COMBA_STORE(C->dp[43]);
+   /* 44 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[108]);    MULADD(at[1], at[107]);    MULADD(at[2], at[106]);    MULADD(at[3], at[105]);    MULADD(at[4], at[104]);    MULADD(at[5], at[103]);    MULADD(at[6], at[102]);    MULADD(at[7], at[101]);    MULADD(at[8], at[100]);    MULADD(at[9], at[99]);    MULADD(at[10], at[98]);    MULADD(at[11], at[97]);    MULADD(at[12], at[96]);    MULADD(at[13], at[95]);    MULADD(at[14], at[94]);    MULADD(at[15], at[93]);    MULADD(at[16], at[92]);    MULADD(at[17], at[91]);    MULADD(at[18], at[90]);    MULADD(at[19], at[89]);    MULADD(at[20], at[88]);    MULADD(at[21], at[87]);    MULADD(at[22], at[86]);    MULADD(at[23], at[85]);    MULADD(at[24], at[84]);    MULADD(at[25], at[83]);    MULADD(at[26], at[82]);    MULADD(at[27], at[81]);    MULADD(at[28], at[80]);    MULADD(at[29], at[79]);    MULADD(at[30], at[78]);    MULADD(at[31], at[77]);    MULADD(at[32], at[76]);    MULADD(at[33], at[75]);    MULADD(at[34], at[74]);    MULADD(at[35], at[73]);    MULADD(at[36], at[72]);    MULADD(at[37], at[71]);    MULADD(at[38], at[70]);    MULADD(at[39], at[69]);    MULADD(at[40], at[68]);    MULADD(at[41], at[67]);    MULADD(at[42], at[66]);    MULADD(at[43], at[65]);    MULADD(at[44], at[64]); 
+   COMBA_STORE(C->dp[44]);
+   /* 45 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[109]);    MULADD(at[1], at[108]);    MULADD(at[2], at[107]);    MULADD(at[3], at[106]);    MULADD(at[4], at[105]);    MULADD(at[5], at[104]);    MULADD(at[6], at[103]);    MULADD(at[7], at[102]);    MULADD(at[8], at[101]);    MULADD(at[9], at[100]);    MULADD(at[10], at[99]);    MULADD(at[11], at[98]);    MULADD(at[12], at[97]);    MULADD(at[13], at[96]);    MULADD(at[14], at[95]);    MULADD(at[15], at[94]);    MULADD(at[16], at[93]);    MULADD(at[17], at[92]);    MULADD(at[18], at[91]);    MULADD(at[19], at[90]);    MULADD(at[20], at[89]);    MULADD(at[21], at[88]);    MULADD(at[22], at[87]);    MULADD(at[23], at[86]);    MULADD(at[24], at[85]);    MULADD(at[25], at[84]);    MULADD(at[26], at[83]);    MULADD(at[27], at[82]);    MULADD(at[28], at[81]);    MULADD(at[29], at[80]);    MULADD(at[30], at[79]);    MULADD(at[31], at[78]);    MULADD(at[32], at[77]);    MULADD(at[33], at[76]);    MULADD(at[34], at[75]);    MULADD(at[35], at[74]);    MULADD(at[36], at[73]);    MULADD(at[37], at[72]);    MULADD(at[38], at[71]);    MULADD(at[39], at[70]);    MULADD(at[40], at[69]);    MULADD(at[41], at[68]);    MULADD(at[42], at[67]);    MULADD(at[43], at[66]);    MULADD(at[44], at[65]);    MULADD(at[45], at[64]); 
+   COMBA_STORE(C->dp[45]);
+   /* 46 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[110]);    MULADD(at[1], at[109]);    MULADD(at[2], at[108]);    MULADD(at[3], at[107]);    MULADD(at[4], at[106]);    MULADD(at[5], at[105]);    MULADD(at[6], at[104]);    MULADD(at[7], at[103]);    MULADD(at[8], at[102]);    MULADD(at[9], at[101]);    MULADD(at[10], at[100]);    MULADD(at[11], at[99]);    MULADD(at[12], at[98]);    MULADD(at[13], at[97]);    MULADD(at[14], at[96]);    MULADD(at[15], at[95]);    MULADD(at[16], at[94]);    MULADD(at[17], at[93]);    MULADD(at[18], at[92]);    MULADD(at[19], at[91]);    MULADD(at[20], at[90]);    MULADD(at[21], at[89]);    MULADD(at[22], at[88]);    MULADD(at[23], at[87]);    MULADD(at[24], at[86]);    MULADD(at[25], at[85]);    MULADD(at[26], at[84]);    MULADD(at[27], at[83]);    MULADD(at[28], at[82]);    MULADD(at[29], at[81]);    MULADD(at[30], at[80]);    MULADD(at[31], at[79]);    MULADD(at[32], at[78]);    MULADD(at[33], at[77]);    MULADD(at[34], at[76]);    MULADD(at[35], at[75]);    MULADD(at[36], at[74]);    MULADD(at[37], at[73]);    MULADD(at[38], at[72]);    MULADD(at[39], at[71]);    MULADD(at[40], at[70]);    MULADD(at[41], at[69]);    MULADD(at[42], at[68]);    MULADD(at[43], at[67]);    MULADD(at[44], at[66]);    MULADD(at[45], at[65]);    MULADD(at[46], at[64]); 
+   COMBA_STORE(C->dp[46]);
+   /* 47 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[111]);    MULADD(at[1], at[110]);    MULADD(at[2], at[109]);    MULADD(at[3], at[108]);    MULADD(at[4], at[107]);    MULADD(at[5], at[106]);    MULADD(at[6], at[105]);    MULADD(at[7], at[104]);    MULADD(at[8], at[103]);    MULADD(at[9], at[102]);    MULADD(at[10], at[101]);    MULADD(at[11], at[100]);    MULADD(at[12], at[99]);    MULADD(at[13], at[98]);    MULADD(at[14], at[97]);    MULADD(at[15], at[96]);    MULADD(at[16], at[95]);    MULADD(at[17], at[94]);    MULADD(at[18], at[93]);    MULADD(at[19], at[92]);    MULADD(at[20], at[91]);    MULADD(at[21], at[90]);    MULADD(at[22], at[89]);    MULADD(at[23], at[88]);    MULADD(at[24], at[87]);    MULADD(at[25], at[86]);    MULADD(at[26], at[85]);    MULADD(at[27], at[84]);    MULADD(at[28], at[83]);    MULADD(at[29], at[82]);    MULADD(at[30], at[81]);    MULADD(at[31], at[80]);    MULADD(at[32], at[79]);    MULADD(at[33], at[78]);    MULADD(at[34], at[77]);    MULADD(at[35], at[76]);    MULADD(at[36], at[75]);    MULADD(at[37], at[74]);    MULADD(at[38], at[73]);    MULADD(at[39], at[72]);    MULADD(at[40], at[71]);    MULADD(at[41], at[70]);    MULADD(at[42], at[69]);    MULADD(at[43], at[68]);    MULADD(at[44], at[67]);    MULADD(at[45], at[66]);    MULADD(at[46], at[65]);    MULADD(at[47], at[64]); 
+   COMBA_STORE(C->dp[47]);
+   /* 48 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[112]);    MULADD(at[1], at[111]);    MULADD(at[2], at[110]);    MULADD(at[3], at[109]);    MULADD(at[4], at[108]);    MULADD(at[5], at[107]);    MULADD(at[6], at[106]);    MULADD(at[7], at[105]);    MULADD(at[8], at[104]);    MULADD(at[9], at[103]);    MULADD(at[10], at[102]);    MULADD(at[11], at[101]);    MULADD(at[12], at[100]);    MULADD(at[13], at[99]);    MULADD(at[14], at[98]);    MULADD(at[15], at[97]);    MULADD(at[16], at[96]);    MULADD(at[17], at[95]);    MULADD(at[18], at[94]);    MULADD(at[19], at[93]);    MULADD(at[20], at[92]);    MULADD(at[21], at[91]);    MULADD(at[22], at[90]);    MULADD(at[23], at[89]);    MULADD(at[24], at[88]);    MULADD(at[25], at[87]);    MULADD(at[26], at[86]);    MULADD(at[27], at[85]);    MULADD(at[28], at[84]);    MULADD(at[29], at[83]);    MULADD(at[30], at[82]);    MULADD(at[31], at[81]);    MULADD(at[32], at[80]);    MULADD(at[33], at[79]);    MULADD(at[34], at[78]);    MULADD(at[35], at[77]);    MULADD(at[36], at[76]);    MULADD(at[37], at[75]);    MULADD(at[38], at[74]);    MULADD(at[39], at[73]);    MULADD(at[40], at[72]);    MULADD(at[41], at[71]);    MULADD(at[42], at[70]);    MULADD(at[43], at[69]);    MULADD(at[44], at[68]);    MULADD(at[45], at[67]);    MULADD(at[46], at[66]);    MULADD(at[47], at[65]);    MULADD(at[48], at[64]); 
+   COMBA_STORE(C->dp[48]);
+   /* 49 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[113]);    MULADD(at[1], at[112]);    MULADD(at[2], at[111]);    MULADD(at[3], at[110]);    MULADD(at[4], at[109]);    MULADD(at[5], at[108]);    MULADD(at[6], at[107]);    MULADD(at[7], at[106]);    MULADD(at[8], at[105]);    MULADD(at[9], at[104]);    MULADD(at[10], at[103]);    MULADD(at[11], at[102]);    MULADD(at[12], at[101]);    MULADD(at[13], at[100]);    MULADD(at[14], at[99]);    MULADD(at[15], at[98]);    MULADD(at[16], at[97]);    MULADD(at[17], at[96]);    MULADD(at[18], at[95]);    MULADD(at[19], at[94]);    MULADD(at[20], at[93]);    MULADD(at[21], at[92]);    MULADD(at[22], at[91]);    MULADD(at[23], at[90]);    MULADD(at[24], at[89]);    MULADD(at[25], at[88]);    MULADD(at[26], at[87]);    MULADD(at[27], at[86]);    MULADD(at[28], at[85]);    MULADD(at[29], at[84]);    MULADD(at[30], at[83]);    MULADD(at[31], at[82]);    MULADD(at[32], at[81]);    MULADD(at[33], at[80]);    MULADD(at[34], at[79]);    MULADD(at[35], at[78]);    MULADD(at[36], at[77]);    MULADD(at[37], at[76]);    MULADD(at[38], at[75]);    MULADD(at[39], at[74]);    MULADD(at[40], at[73]);    MULADD(at[41], at[72]);    MULADD(at[42], at[71]);    MULADD(at[43], at[70]);    MULADD(at[44], at[69]);    MULADD(at[45], at[68]);    MULADD(at[46], at[67]);    MULADD(at[47], at[66]);    MULADD(at[48], at[65]);    MULADD(at[49], at[64]); 
+   COMBA_STORE(C->dp[49]);
+   /* 50 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[114]);    MULADD(at[1], at[113]);    MULADD(at[2], at[112]);    MULADD(at[3], at[111]);    MULADD(at[4], at[110]);    MULADD(at[5], at[109]);    MULADD(at[6], at[108]);    MULADD(at[7], at[107]);    MULADD(at[8], at[106]);    MULADD(at[9], at[105]);    MULADD(at[10], at[104]);    MULADD(at[11], at[103]);    MULADD(at[12], at[102]);    MULADD(at[13], at[101]);    MULADD(at[14], at[100]);    MULADD(at[15], at[99]);    MULADD(at[16], at[98]);    MULADD(at[17], at[97]);    MULADD(at[18], at[96]);    MULADD(at[19], at[95]);    MULADD(at[20], at[94]);    MULADD(at[21], at[93]);    MULADD(at[22], at[92]);    MULADD(at[23], at[91]);    MULADD(at[24], at[90]);    MULADD(at[25], at[89]);    MULADD(at[26], at[88]);    MULADD(at[27], at[87]);    MULADD(at[28], at[86]);    MULADD(at[29], at[85]);    MULADD(at[30], at[84]);    MULADD(at[31], at[83]);    MULADD(at[32], at[82]);    MULADD(at[33], at[81]);    MULADD(at[34], at[80]);    MULADD(at[35], at[79]);    MULADD(at[36], at[78]);    MULADD(at[37], at[77]);    MULADD(at[38], at[76]);    MULADD(at[39], at[75]);    MULADD(at[40], at[74]);    MULADD(at[41], at[73]);    MULADD(at[42], at[72]);    MULADD(at[43], at[71]);    MULADD(at[44], at[70]);    MULADD(at[45], at[69]);    MULADD(at[46], at[68]);    MULADD(at[47], at[67]);    MULADD(at[48], at[66]);    MULADD(at[49], at[65]);    MULADD(at[50], at[64]); 
+   COMBA_STORE(C->dp[50]);
+   /* 51 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[115]);    MULADD(at[1], at[114]);    MULADD(at[2], at[113]);    MULADD(at[3], at[112]);    MULADD(at[4], at[111]);    MULADD(at[5], at[110]);    MULADD(at[6], at[109]);    MULADD(at[7], at[108]);    MULADD(at[8], at[107]);    MULADD(at[9], at[106]);    MULADD(at[10], at[105]);    MULADD(at[11], at[104]);    MULADD(at[12], at[103]);    MULADD(at[13], at[102]);    MULADD(at[14], at[101]);    MULADD(at[15], at[100]);    MULADD(at[16], at[99]);    MULADD(at[17], at[98]);    MULADD(at[18], at[97]);    MULADD(at[19], at[96]);    MULADD(at[20], at[95]);    MULADD(at[21], at[94]);    MULADD(at[22], at[93]);    MULADD(at[23], at[92]);    MULADD(at[24], at[91]);    MULADD(at[25], at[90]);    MULADD(at[26], at[89]);    MULADD(at[27], at[88]);    MULADD(at[28], at[87]);    MULADD(at[29], at[86]);    MULADD(at[30], at[85]);    MULADD(at[31], at[84]);    MULADD(at[32], at[83]);    MULADD(at[33], at[82]);    MULADD(at[34], at[81]);    MULADD(at[35], at[80]);    MULADD(at[36], at[79]);    MULADD(at[37], at[78]);    MULADD(at[38], at[77]);    MULADD(at[39], at[76]);    MULADD(at[40], at[75]);    MULADD(at[41], at[74]);    MULADD(at[42], at[73]);    MULADD(at[43], at[72]);    MULADD(at[44], at[71]);    MULADD(at[45], at[70]);    MULADD(at[46], at[69]);    MULADD(at[47], at[68]);    MULADD(at[48], at[67]);    MULADD(at[49], at[66]);    MULADD(at[50], at[65]);    MULADD(at[51], at[64]); 
+   COMBA_STORE(C->dp[51]);
+   /* 52 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[116]);    MULADD(at[1], at[115]);    MULADD(at[2], at[114]);    MULADD(at[3], at[113]);    MULADD(at[4], at[112]);    MULADD(at[5], at[111]);    MULADD(at[6], at[110]);    MULADD(at[7], at[109]);    MULADD(at[8], at[108]);    MULADD(at[9], at[107]);    MULADD(at[10], at[106]);    MULADD(at[11], at[105]);    MULADD(at[12], at[104]);    MULADD(at[13], at[103]);    MULADD(at[14], at[102]);    MULADD(at[15], at[101]);    MULADD(at[16], at[100]);    MULADD(at[17], at[99]);    MULADD(at[18], at[98]);    MULADD(at[19], at[97]);    MULADD(at[20], at[96]);    MULADD(at[21], at[95]);    MULADD(at[22], at[94]);    MULADD(at[23], at[93]);    MULADD(at[24], at[92]);    MULADD(at[25], at[91]);    MULADD(at[26], at[90]);    MULADD(at[27], at[89]);    MULADD(at[28], at[88]);    MULADD(at[29], at[87]);    MULADD(at[30], at[86]);    MULADD(at[31], at[85]);    MULADD(at[32], at[84]);    MULADD(at[33], at[83]);    MULADD(at[34], at[82]);    MULADD(at[35], at[81]);    MULADD(at[36], at[80]);    MULADD(at[37], at[79]);    MULADD(at[38], at[78]);    MULADD(at[39], at[77]);    MULADD(at[40], at[76]);    MULADD(at[41], at[75]);    MULADD(at[42], at[74]);    MULADD(at[43], at[73]);    MULADD(at[44], at[72]);    MULADD(at[45], at[71]);    MULADD(at[46], at[70]);    MULADD(at[47], at[69]);    MULADD(at[48], at[68]);    MULADD(at[49], at[67]);    MULADD(at[50], at[66]);    MULADD(at[51], at[65]);    MULADD(at[52], at[64]); 
+   COMBA_STORE(C->dp[52]);
+   /* 53 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[117]);    MULADD(at[1], at[116]);    MULADD(at[2], at[115]);    MULADD(at[3], at[114]);    MULADD(at[4], at[113]);    MULADD(at[5], at[112]);    MULADD(at[6], at[111]);    MULADD(at[7], at[110]);    MULADD(at[8], at[109]);    MULADD(at[9], at[108]);    MULADD(at[10], at[107]);    MULADD(at[11], at[106]);    MULADD(at[12], at[105]);    MULADD(at[13], at[104]);    MULADD(at[14], at[103]);    MULADD(at[15], at[102]);    MULADD(at[16], at[101]);    MULADD(at[17], at[100]);    MULADD(at[18], at[99]);    MULADD(at[19], at[98]);    MULADD(at[20], at[97]);    MULADD(at[21], at[96]);    MULADD(at[22], at[95]);    MULADD(at[23], at[94]);    MULADD(at[24], at[93]);    MULADD(at[25], at[92]);    MULADD(at[26], at[91]);    MULADD(at[27], at[90]);    MULADD(at[28], at[89]);    MULADD(at[29], at[88]);    MULADD(at[30], at[87]);    MULADD(at[31], at[86]);    MULADD(at[32], at[85]);    MULADD(at[33], at[84]);    MULADD(at[34], at[83]);    MULADD(at[35], at[82]);    MULADD(at[36], at[81]);    MULADD(at[37], at[80]);    MULADD(at[38], at[79]);    MULADD(at[39], at[78]);    MULADD(at[40], at[77]);    MULADD(at[41], at[76]);    MULADD(at[42], at[75]);    MULADD(at[43], at[74]);    MULADD(at[44], at[73]);    MULADD(at[45], at[72]);    MULADD(at[46], at[71]);    MULADD(at[47], at[70]);    MULADD(at[48], at[69]);    MULADD(at[49], at[68]);    MULADD(at[50], at[67]);    MULADD(at[51], at[66]);    MULADD(at[52], at[65]);    MULADD(at[53], at[64]); 
+   COMBA_STORE(C->dp[53]);
+   /* 54 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[118]);    MULADD(at[1], at[117]);    MULADD(at[2], at[116]);    MULADD(at[3], at[115]);    MULADD(at[4], at[114]);    MULADD(at[5], at[113]);    MULADD(at[6], at[112]);    MULADD(at[7], at[111]);    MULADD(at[8], at[110]);    MULADD(at[9], at[109]);    MULADD(at[10], at[108]);    MULADD(at[11], at[107]);    MULADD(at[12], at[106]);    MULADD(at[13], at[105]);    MULADD(at[14], at[104]);    MULADD(at[15], at[103]);    MULADD(at[16], at[102]);    MULADD(at[17], at[101]);    MULADD(at[18], at[100]);    MULADD(at[19], at[99]);    MULADD(at[20], at[98]);    MULADD(at[21], at[97]);    MULADD(at[22], at[96]);    MULADD(at[23], at[95]);    MULADD(at[24], at[94]);    MULADD(at[25], at[93]);    MULADD(at[26], at[92]);    MULADD(at[27], at[91]);    MULADD(at[28], at[90]);    MULADD(at[29], at[89]);    MULADD(at[30], at[88]);    MULADD(at[31], at[87]);    MULADD(at[32], at[86]);    MULADD(at[33], at[85]);    MULADD(at[34], at[84]);    MULADD(at[35], at[83]);    MULADD(at[36], at[82]);    MULADD(at[37], at[81]);    MULADD(at[38], at[80]);    MULADD(at[39], at[79]);    MULADD(at[40], at[78]);    MULADD(at[41], at[77]);    MULADD(at[42], at[76]);    MULADD(at[43], at[75]);    MULADD(at[44], at[74]);    MULADD(at[45], at[73]);    MULADD(at[46], at[72]);    MULADD(at[47], at[71]);    MULADD(at[48], at[70]);    MULADD(at[49], at[69]);    MULADD(at[50], at[68]);    MULADD(at[51], at[67]);    MULADD(at[52], at[66]);    MULADD(at[53], at[65]);    MULADD(at[54], at[64]); 
+   COMBA_STORE(C->dp[54]);
+   /* 55 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[119]);    MULADD(at[1], at[118]);    MULADD(at[2], at[117]);    MULADD(at[3], at[116]);    MULADD(at[4], at[115]);    MULADD(at[5], at[114]);    MULADD(at[6], at[113]);    MULADD(at[7], at[112]);    MULADD(at[8], at[111]);    MULADD(at[9], at[110]);    MULADD(at[10], at[109]);    MULADD(at[11], at[108]);    MULADD(at[12], at[107]);    MULADD(at[13], at[106]);    MULADD(at[14], at[105]);    MULADD(at[15], at[104]);    MULADD(at[16], at[103]);    MULADD(at[17], at[102]);    MULADD(at[18], at[101]);    MULADD(at[19], at[100]);    MULADD(at[20], at[99]);    MULADD(at[21], at[98]);    MULADD(at[22], at[97]);    MULADD(at[23], at[96]);    MULADD(at[24], at[95]);    MULADD(at[25], at[94]);    MULADD(at[26], at[93]);    MULADD(at[27], at[92]);    MULADD(at[28], at[91]);    MULADD(at[29], at[90]);    MULADD(at[30], at[89]);    MULADD(at[31], at[88]);    MULADD(at[32], at[87]);    MULADD(at[33], at[86]);    MULADD(at[34], at[85]);    MULADD(at[35], at[84]);    MULADD(at[36], at[83]);    MULADD(at[37], at[82]);    MULADD(at[38], at[81]);    MULADD(at[39], at[80]);    MULADD(at[40], at[79]);    MULADD(at[41], at[78]);    MULADD(at[42], at[77]);    MULADD(at[43], at[76]);    MULADD(at[44], at[75]);    MULADD(at[45], at[74]);    MULADD(at[46], at[73]);    MULADD(at[47], at[72]);    MULADD(at[48], at[71]);    MULADD(at[49], at[70]);    MULADD(at[50], at[69]);    MULADD(at[51], at[68]);    MULADD(at[52], at[67]);    MULADD(at[53], at[66]);    MULADD(at[54], at[65]);    MULADD(at[55], at[64]); 
+   COMBA_STORE(C->dp[55]);
+   /* 56 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[120]);    MULADD(at[1], at[119]);    MULADD(at[2], at[118]);    MULADD(at[3], at[117]);    MULADD(at[4], at[116]);    MULADD(at[5], at[115]);    MULADD(at[6], at[114]);    MULADD(at[7], at[113]);    MULADD(at[8], at[112]);    MULADD(at[9], at[111]);    MULADD(at[10], at[110]);    MULADD(at[11], at[109]);    MULADD(at[12], at[108]);    MULADD(at[13], at[107]);    MULADD(at[14], at[106]);    MULADD(at[15], at[105]);    MULADD(at[16], at[104]);    MULADD(at[17], at[103]);    MULADD(at[18], at[102]);    MULADD(at[19], at[101]);    MULADD(at[20], at[100]);    MULADD(at[21], at[99]);    MULADD(at[22], at[98]);    MULADD(at[23], at[97]);    MULADD(at[24], at[96]);    MULADD(at[25], at[95]);    MULADD(at[26], at[94]);    MULADD(at[27], at[93]);    MULADD(at[28], at[92]);    MULADD(at[29], at[91]);    MULADD(at[30], at[90]);    MULADD(at[31], at[89]);    MULADD(at[32], at[88]);    MULADD(at[33], at[87]);    MULADD(at[34], at[86]);    MULADD(at[35], at[85]);    MULADD(at[36], at[84]);    MULADD(at[37], at[83]);    MULADD(at[38], at[82]);    MULADD(at[39], at[81]);    MULADD(at[40], at[80]);    MULADD(at[41], at[79]);    MULADD(at[42], at[78]);    MULADD(at[43], at[77]);    MULADD(at[44], at[76]);    MULADD(at[45], at[75]);    MULADD(at[46], at[74]);    MULADD(at[47], at[73]);    MULADD(at[48], at[72]);    MULADD(at[49], at[71]);    MULADD(at[50], at[70]);    MULADD(at[51], at[69]);    MULADD(at[52], at[68]);    MULADD(at[53], at[67]);    MULADD(at[54], at[66]);    MULADD(at[55], at[65]);    MULADD(at[56], at[64]); 
+   COMBA_STORE(C->dp[56]);
+   /* 57 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[121]);    MULADD(at[1], at[120]);    MULADD(at[2], at[119]);    MULADD(at[3], at[118]);    MULADD(at[4], at[117]);    MULADD(at[5], at[116]);    MULADD(at[6], at[115]);    MULADD(at[7], at[114]);    MULADD(at[8], at[113]);    MULADD(at[9], at[112]);    MULADD(at[10], at[111]);    MULADD(at[11], at[110]);    MULADD(at[12], at[109]);    MULADD(at[13], at[108]);    MULADD(at[14], at[107]);    MULADD(at[15], at[106]);    MULADD(at[16], at[105]);    MULADD(at[17], at[104]);    MULADD(at[18], at[103]);    MULADD(at[19], at[102]);    MULADD(at[20], at[101]);    MULADD(at[21], at[100]);    MULADD(at[22], at[99]);    MULADD(at[23], at[98]);    MULADD(at[24], at[97]);    MULADD(at[25], at[96]);    MULADD(at[26], at[95]);    MULADD(at[27], at[94]);    MULADD(at[28], at[93]);    MULADD(at[29], at[92]);    MULADD(at[30], at[91]);    MULADD(at[31], at[90]);    MULADD(at[32], at[89]);    MULADD(at[33], at[88]);    MULADD(at[34], at[87]);    MULADD(at[35], at[86]);    MULADD(at[36], at[85]);    MULADD(at[37], at[84]);    MULADD(at[38], at[83]);    MULADD(at[39], at[82]);    MULADD(at[40], at[81]);    MULADD(at[41], at[80]);    MULADD(at[42], at[79]);    MULADD(at[43], at[78]);    MULADD(at[44], at[77]);    MULADD(at[45], at[76]);    MULADD(at[46], at[75]);    MULADD(at[47], at[74]);    MULADD(at[48], at[73]);    MULADD(at[49], at[72]);    MULADD(at[50], at[71]);    MULADD(at[51], at[70]);    MULADD(at[52], at[69]);    MULADD(at[53], at[68]);    MULADD(at[54], at[67]);    MULADD(at[55], at[66]);    MULADD(at[56], at[65]);    MULADD(at[57], at[64]); 
+   COMBA_STORE(C->dp[57]);
+   /* 58 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[122]);    MULADD(at[1], at[121]);    MULADD(at[2], at[120]);    MULADD(at[3], at[119]);    MULADD(at[4], at[118]);    MULADD(at[5], at[117]);    MULADD(at[6], at[116]);    MULADD(at[7], at[115]);    MULADD(at[8], at[114]);    MULADD(at[9], at[113]);    MULADD(at[10], at[112]);    MULADD(at[11], at[111]);    MULADD(at[12], at[110]);    MULADD(at[13], at[109]);    MULADD(at[14], at[108]);    MULADD(at[15], at[107]);    MULADD(at[16], at[106]);    MULADD(at[17], at[105]);    MULADD(at[18], at[104]);    MULADD(at[19], at[103]);    MULADD(at[20], at[102]);    MULADD(at[21], at[101]);    MULADD(at[22], at[100]);    MULADD(at[23], at[99]);    MULADD(at[24], at[98]);    MULADD(at[25], at[97]);    MULADD(at[26], at[96]);    MULADD(at[27], at[95]);    MULADD(at[28], at[94]);    MULADD(at[29], at[93]);    MULADD(at[30], at[92]);    MULADD(at[31], at[91]);    MULADD(at[32], at[90]);    MULADD(at[33], at[89]);    MULADD(at[34], at[88]);    MULADD(at[35], at[87]);    MULADD(at[36], at[86]);    MULADD(at[37], at[85]);    MULADD(at[38], at[84]);    MULADD(at[39], at[83]);    MULADD(at[40], at[82]);    MULADD(at[41], at[81]);    MULADD(at[42], at[80]);    MULADD(at[43], at[79]);    MULADD(at[44], at[78]);    MULADD(at[45], at[77]);    MULADD(at[46], at[76]);    MULADD(at[47], at[75]);    MULADD(at[48], at[74]);    MULADD(at[49], at[73]);    MULADD(at[50], at[72]);    MULADD(at[51], at[71]);    MULADD(at[52], at[70]);    MULADD(at[53], at[69]);    MULADD(at[54], at[68]);    MULADD(at[55], at[67]);    MULADD(at[56], at[66]);    MULADD(at[57], at[65]);    MULADD(at[58], at[64]); 
+   COMBA_STORE(C->dp[58]);
+   /* 59 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[123]);    MULADD(at[1], at[122]);    MULADD(at[2], at[121]);    MULADD(at[3], at[120]);    MULADD(at[4], at[119]);    MULADD(at[5], at[118]);    MULADD(at[6], at[117]);    MULADD(at[7], at[116]);    MULADD(at[8], at[115]);    MULADD(at[9], at[114]);    MULADD(at[10], at[113]);    MULADD(at[11], at[112]);    MULADD(at[12], at[111]);    MULADD(at[13], at[110]);    MULADD(at[14], at[109]);    MULADD(at[15], at[108]);    MULADD(at[16], at[107]);    MULADD(at[17], at[106]);    MULADD(at[18], at[105]);    MULADD(at[19], at[104]);    MULADD(at[20], at[103]);    MULADD(at[21], at[102]);    MULADD(at[22], at[101]);    MULADD(at[23], at[100]);    MULADD(at[24], at[99]);    MULADD(at[25], at[98]);    MULADD(at[26], at[97]);    MULADD(at[27], at[96]);    MULADD(at[28], at[95]);    MULADD(at[29], at[94]);    MULADD(at[30], at[93]);    MULADD(at[31], at[92]);    MULADD(at[32], at[91]);    MULADD(at[33], at[90]);    MULADD(at[34], at[89]);    MULADD(at[35], at[88]);    MULADD(at[36], at[87]);    MULADD(at[37], at[86]);    MULADD(at[38], at[85]);    MULADD(at[39], at[84]);    MULADD(at[40], at[83]);    MULADD(at[41], at[82]);    MULADD(at[42], at[81]);    MULADD(at[43], at[80]);    MULADD(at[44], at[79]);    MULADD(at[45], at[78]);    MULADD(at[46], at[77]);    MULADD(at[47], at[76]);    MULADD(at[48], at[75]);    MULADD(at[49], at[74]);    MULADD(at[50], at[73]);    MULADD(at[51], at[72]);    MULADD(at[52], at[71]);    MULADD(at[53], at[70]);    MULADD(at[54], at[69]);    MULADD(at[55], at[68]);    MULADD(at[56], at[67]);    MULADD(at[57], at[66]);    MULADD(at[58], at[65]);    MULADD(at[59], at[64]); 
+   COMBA_STORE(C->dp[59]);
+   /* 60 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[124]);    MULADD(at[1], at[123]);    MULADD(at[2], at[122]);    MULADD(at[3], at[121]);    MULADD(at[4], at[120]);    MULADD(at[5], at[119]);    MULADD(at[6], at[118]);    MULADD(at[7], at[117]);    MULADD(at[8], at[116]);    MULADD(at[9], at[115]);    MULADD(at[10], at[114]);    MULADD(at[11], at[113]);    MULADD(at[12], at[112]);    MULADD(at[13], at[111]);    MULADD(at[14], at[110]);    MULADD(at[15], at[109]);    MULADD(at[16], at[108]);    MULADD(at[17], at[107]);    MULADD(at[18], at[106]);    MULADD(at[19], at[105]);    MULADD(at[20], at[104]);    MULADD(at[21], at[103]);    MULADD(at[22], at[102]);    MULADD(at[23], at[101]);    MULADD(at[24], at[100]);    MULADD(at[25], at[99]);    MULADD(at[26], at[98]);    MULADD(at[27], at[97]);    MULADD(at[28], at[96]);    MULADD(at[29], at[95]);    MULADD(at[30], at[94]);    MULADD(at[31], at[93]);    MULADD(at[32], at[92]);    MULADD(at[33], at[91]);    MULADD(at[34], at[90]);    MULADD(at[35], at[89]);    MULADD(at[36], at[88]);    MULADD(at[37], at[87]);    MULADD(at[38], at[86]);    MULADD(at[39], at[85]);    MULADD(at[40], at[84]);    MULADD(at[41], at[83]);    MULADD(at[42], at[82]);    MULADD(at[43], at[81]);    MULADD(at[44], at[80]);    MULADD(at[45], at[79]);    MULADD(at[46], at[78]);    MULADD(at[47], at[77]);    MULADD(at[48], at[76]);    MULADD(at[49], at[75]);    MULADD(at[50], at[74]);    MULADD(at[51], at[73]);    MULADD(at[52], at[72]);    MULADD(at[53], at[71]);    MULADD(at[54], at[70]);    MULADD(at[55], at[69]);    MULADD(at[56], at[68]);    MULADD(at[57], at[67]);    MULADD(at[58], at[66]);    MULADD(at[59], at[65]);    MULADD(at[60], at[64]); 
+   COMBA_STORE(C->dp[60]);
+   /* 61 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[125]);    MULADD(at[1], at[124]);    MULADD(at[2], at[123]);    MULADD(at[3], at[122]);    MULADD(at[4], at[121]);    MULADD(at[5], at[120]);    MULADD(at[6], at[119]);    MULADD(at[7], at[118]);    MULADD(at[8], at[117]);    MULADD(at[9], at[116]);    MULADD(at[10], at[115]);    MULADD(at[11], at[114]);    MULADD(at[12], at[113]);    MULADD(at[13], at[112]);    MULADD(at[14], at[111]);    MULADD(at[15], at[110]);    MULADD(at[16], at[109]);    MULADD(at[17], at[108]);    MULADD(at[18], at[107]);    MULADD(at[19], at[106]);    MULADD(at[20], at[105]);    MULADD(at[21], at[104]);    MULADD(at[22], at[103]);    MULADD(at[23], at[102]);    MULADD(at[24], at[101]);    MULADD(at[25], at[100]);    MULADD(at[26], at[99]);    MULADD(at[27], at[98]);    MULADD(at[28], at[97]);    MULADD(at[29], at[96]);    MULADD(at[30], at[95]);    MULADD(at[31], at[94]);    MULADD(at[32], at[93]);    MULADD(at[33], at[92]);    MULADD(at[34], at[91]);    MULADD(at[35], at[90]);    MULADD(at[36], at[89]);    MULADD(at[37], at[88]);    MULADD(at[38], at[87]);    MULADD(at[39], at[86]);    MULADD(at[40], at[85]);    MULADD(at[41], at[84]);    MULADD(at[42], at[83]);    MULADD(at[43], at[82]);    MULADD(at[44], at[81]);    MULADD(at[45], at[80]);    MULADD(at[46], at[79]);    MULADD(at[47], at[78]);    MULADD(at[48], at[77]);    MULADD(at[49], at[76]);    MULADD(at[50], at[75]);    MULADD(at[51], at[74]);    MULADD(at[52], at[73]);    MULADD(at[53], at[72]);    MULADD(at[54], at[71]);    MULADD(at[55], at[70]);    MULADD(at[56], at[69]);    MULADD(at[57], at[68]);    MULADD(at[58], at[67]);    MULADD(at[59], at[66]);    MULADD(at[60], at[65]);    MULADD(at[61], at[64]); 
+   COMBA_STORE(C->dp[61]);
+   /* 62 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[126]);    MULADD(at[1], at[125]);    MULADD(at[2], at[124]);    MULADD(at[3], at[123]);    MULADD(at[4], at[122]);    MULADD(at[5], at[121]);    MULADD(at[6], at[120]);    MULADD(at[7], at[119]);    MULADD(at[8], at[118]);    MULADD(at[9], at[117]);    MULADD(at[10], at[116]);    MULADD(at[11], at[115]);    MULADD(at[12], at[114]);    MULADD(at[13], at[113]);    MULADD(at[14], at[112]);    MULADD(at[15], at[111]);    MULADD(at[16], at[110]);    MULADD(at[17], at[109]);    MULADD(at[18], at[108]);    MULADD(at[19], at[107]);    MULADD(at[20], at[106]);    MULADD(at[21], at[105]);    MULADD(at[22], at[104]);    MULADD(at[23], at[103]);    MULADD(at[24], at[102]);    MULADD(at[25], at[101]);    MULADD(at[26], at[100]);    MULADD(at[27], at[99]);    MULADD(at[28], at[98]);    MULADD(at[29], at[97]);    MULADD(at[30], at[96]);    MULADD(at[31], at[95]);    MULADD(at[32], at[94]);    MULADD(at[33], at[93]);    MULADD(at[34], at[92]);    MULADD(at[35], at[91]);    MULADD(at[36], at[90]);    MULADD(at[37], at[89]);    MULADD(at[38], at[88]);    MULADD(at[39], at[87]);    MULADD(at[40], at[86]);    MULADD(at[41], at[85]);    MULADD(at[42], at[84]);    MULADD(at[43], at[83]);    MULADD(at[44], at[82]);    MULADD(at[45], at[81]);    MULADD(at[46], at[80]);    MULADD(at[47], at[79]);    MULADD(at[48], at[78]);    MULADD(at[49], at[77]);    MULADD(at[50], at[76]);    MULADD(at[51], at[75]);    MULADD(at[52], at[74]);    MULADD(at[53], at[73]);    MULADD(at[54], at[72]);    MULADD(at[55], at[71]);    MULADD(at[56], at[70]);    MULADD(at[57], at[69]);    MULADD(at[58], at[68]);    MULADD(at[59], at[67]);    MULADD(at[60], at[66]);    MULADD(at[61], at[65]);    MULADD(at[62], at[64]); 
+   COMBA_STORE(C->dp[62]);
+   /* 63 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[127]);    MULADD(at[1], at[126]);    MULADD(at[2], at[125]);    MULADD(at[3], at[124]);    MULADD(at[4], at[123]);    MULADD(at[5], at[122]);    MULADD(at[6], at[121]);    MULADD(at[7], at[120]);    MULADD(at[8], at[119]);    MULADD(at[9], at[118]);    MULADD(at[10], at[117]);    MULADD(at[11], at[116]);    MULADD(at[12], at[115]);    MULADD(at[13], at[114]);    MULADD(at[14], at[113]);    MULADD(at[15], at[112]);    MULADD(at[16], at[111]);    MULADD(at[17], at[110]);    MULADD(at[18], at[109]);    MULADD(at[19], at[108]);    MULADD(at[20], at[107]);    MULADD(at[21], at[106]);    MULADD(at[22], at[105]);    MULADD(at[23], at[104]);    MULADD(at[24], at[103]);    MULADD(at[25], at[102]);    MULADD(at[26], at[101]);    MULADD(at[27], at[100]);    MULADD(at[28], at[99]);    MULADD(at[29], at[98]);    MULADD(at[30], at[97]);    MULADD(at[31], at[96]);    MULADD(at[32], at[95]);    MULADD(at[33], at[94]);    MULADD(at[34], at[93]);    MULADD(at[35], at[92]);    MULADD(at[36], at[91]);    MULADD(at[37], at[90]);    MULADD(at[38], at[89]);    MULADD(at[39], at[88]);    MULADD(at[40], at[87]);    MULADD(at[41], at[86]);    MULADD(at[42], at[85]);    MULADD(at[43], at[84]);    MULADD(at[44], at[83]);    MULADD(at[45], at[82]);    MULADD(at[46], at[81]);    MULADD(at[47], at[80]);    MULADD(at[48], at[79]);    MULADD(at[49], at[78]);    MULADD(at[50], at[77]);    MULADD(at[51], at[76]);    MULADD(at[52], at[75]);    MULADD(at[53], at[74]);    MULADD(at[54], at[73]);    MULADD(at[55], at[72]);    MULADD(at[56], at[71]);    MULADD(at[57], at[70]);    MULADD(at[58], at[69]);    MULADD(at[59], at[68]);    MULADD(at[60], at[67]);    MULADD(at[61], at[66]);    MULADD(at[62], at[65]);    MULADD(at[63], at[64]); 
+   COMBA_STORE(C->dp[63]);
+   /* 64 */
+   COMBA_FORWARD;
+   MULADD(at[1], at[127]);    MULADD(at[2], at[126]);    MULADD(at[3], at[125]);    MULADD(at[4], at[124]);    MULADD(at[5], at[123]);    MULADD(at[6], at[122]);    MULADD(at[7], at[121]);    MULADD(at[8], at[120]);    MULADD(at[9], at[119]);    MULADD(at[10], at[118]);    MULADD(at[11], at[117]);    MULADD(at[12], at[116]);    MULADD(at[13], at[115]);    MULADD(at[14], at[114]);    MULADD(at[15], at[113]);    MULADD(at[16], at[112]);    MULADD(at[17], at[111]);    MULADD(at[18], at[110]);    MULADD(at[19], at[109]);    MULADD(at[20], at[108]);    MULADD(at[21], at[107]);    MULADD(at[22], at[106]);    MULADD(at[23], at[105]);    MULADD(at[24], at[104]);    MULADD(at[25], at[103]);    MULADD(at[26], at[102]);    MULADD(at[27], at[101]);    MULADD(at[28], at[100]);    MULADD(at[29], at[99]);    MULADD(at[30], at[98]);    MULADD(at[31], at[97]);    MULADD(at[32], at[96]);    MULADD(at[33], at[95]);    MULADD(at[34], at[94]);    MULADD(at[35], at[93]);    MULADD(at[36], at[92]);    MULADD(at[37], at[91]);    MULADD(at[38], at[90]);    MULADD(at[39], at[89]);    MULADD(at[40], at[88]);    MULADD(at[41], at[87]);    MULADD(at[42], at[86]);    MULADD(at[43], at[85]);    MULADD(at[44], at[84]);    MULADD(at[45], at[83]);    MULADD(at[46], at[82]);    MULADD(at[47], at[81]);    MULADD(at[48], at[80]);    MULADD(at[49], at[79]);    MULADD(at[50], at[78]);    MULADD(at[51], at[77]);    MULADD(at[52], at[76]);    MULADD(at[53], at[75]);    MULADD(at[54], at[74]);    MULADD(at[55], at[73]);    MULADD(at[56], at[72]);    MULADD(at[57], at[71]);    MULADD(at[58], at[70]);    MULADD(at[59], at[69]);    MULADD(at[60], at[68]);    MULADD(at[61], at[67]);    MULADD(at[62], at[66]);    MULADD(at[63], at[65]); 
+   COMBA_STORE(C->dp[64]);
+   /* 65 */
+   COMBA_FORWARD;
+   MULADD(at[2], at[127]);    MULADD(at[3], at[126]);    MULADD(at[4], at[125]);    MULADD(at[5], at[124]);    MULADD(at[6], at[123]);    MULADD(at[7], at[122]);    MULADD(at[8], at[121]);    MULADD(at[9], at[120]);    MULADD(at[10], at[119]);    MULADD(at[11], at[118]);    MULADD(at[12], at[117]);    MULADD(at[13], at[116]);    MULADD(at[14], at[115]);    MULADD(at[15], at[114]);    MULADD(at[16], at[113]);    MULADD(at[17], at[112]);    MULADD(at[18], at[111]);    MULADD(at[19], at[110]);    MULADD(at[20], at[109]);    MULADD(at[21], at[108]);    MULADD(at[22], at[107]);    MULADD(at[23], at[106]);    MULADD(at[24], at[105]);    MULADD(at[25], at[104]);    MULADD(at[26], at[103]);    MULADD(at[27], at[102]);    MULADD(at[28], at[101]);    MULADD(at[29], at[100]);    MULADD(at[30], at[99]);    MULADD(at[31], at[98]);    MULADD(at[32], at[97]);    MULADD(at[33], at[96]);    MULADD(at[34], at[95]);    MULADD(at[35], at[94]);    MULADD(at[36], at[93]);    MULADD(at[37], at[92]);    MULADD(at[38], at[91]);    MULADD(at[39], at[90]);    MULADD(at[40], at[89]);    MULADD(at[41], at[88]);    MULADD(at[42], at[87]);    MULADD(at[43], at[86]);    MULADD(at[44], at[85]);    MULADD(at[45], at[84]);    MULADD(at[46], at[83]);    MULADD(at[47], at[82]);    MULADD(at[48], at[81]);    MULADD(at[49], at[80]);    MULADD(at[50], at[79]);    MULADD(at[51], at[78]);    MULADD(at[52], at[77]);    MULADD(at[53], at[76]);    MULADD(at[54], at[75]);    MULADD(at[55], at[74]);    MULADD(at[56], at[73]);    MULADD(at[57], at[72]);    MULADD(at[58], at[71]);    MULADD(at[59], at[70]);    MULADD(at[60], at[69]);    MULADD(at[61], at[68]);    MULADD(at[62], at[67]);    MULADD(at[63], at[66]); 
+   COMBA_STORE(C->dp[65]);
+   /* 66 */
+   COMBA_FORWARD;
+   MULADD(at[3], at[127]);    MULADD(at[4], at[126]);    MULADD(at[5], at[125]);    MULADD(at[6], at[124]);    MULADD(at[7], at[123]);    MULADD(at[8], at[122]);    MULADD(at[9], at[121]);    MULADD(at[10], at[120]);    MULADD(at[11], at[119]);    MULADD(at[12], at[118]);    MULADD(at[13], at[117]);    MULADD(at[14], at[116]);    MULADD(at[15], at[115]);    MULADD(at[16], at[114]);    MULADD(at[17], at[113]);    MULADD(at[18], at[112]);    MULADD(at[19], at[111]);    MULADD(at[20], at[110]);    MULADD(at[21], at[109]);    MULADD(at[22], at[108]);    MULADD(at[23], at[107]);    MULADD(at[24], at[106]);    MULADD(at[25], at[105]);    MULADD(at[26], at[104]);    MULADD(at[27], at[103]);    MULADD(at[28], at[102]);    MULADD(at[29], at[101]);    MULADD(at[30], at[100]);    MULADD(at[31], at[99]);    MULADD(at[32], at[98]);    MULADD(at[33], at[97]);    MULADD(at[34], at[96]);    MULADD(at[35], at[95]);    MULADD(at[36], at[94]);    MULADD(at[37], at[93]);    MULADD(at[38], at[92]);    MULADD(at[39], at[91]);    MULADD(at[40], at[90]);    MULADD(at[41], at[89]);    MULADD(at[42], at[88]);    MULADD(at[43], at[87]);    MULADD(at[44], at[86]);    MULADD(at[45], at[85]);    MULADD(at[46], at[84]);    MULADD(at[47], at[83]);    MULADD(at[48], at[82]);    MULADD(at[49], at[81]);    MULADD(at[50], at[80]);    MULADD(at[51], at[79]);    MULADD(at[52], at[78]);    MULADD(at[53], at[77]);    MULADD(at[54], at[76]);    MULADD(at[55], at[75]);    MULADD(at[56], at[74]);    MULADD(at[57], at[73]);    MULADD(at[58], at[72]);    MULADD(at[59], at[71]);    MULADD(at[60], at[70]);    MULADD(at[61], at[69]);    MULADD(at[62], at[68]);    MULADD(at[63], at[67]); 
+   COMBA_STORE(C->dp[66]);
+   /* 67 */
+   COMBA_FORWARD;
+   MULADD(at[4], at[127]);    MULADD(at[5], at[126]);    MULADD(at[6], at[125]);    MULADD(at[7], at[124]);    MULADD(at[8], at[123]);    MULADD(at[9], at[122]);    MULADD(at[10], at[121]);    MULADD(at[11], at[120]);    MULADD(at[12], at[119]);    MULADD(at[13], at[118]);    MULADD(at[14], at[117]);    MULADD(at[15], at[116]);    MULADD(at[16], at[115]);    MULADD(at[17], at[114]);    MULADD(at[18], at[113]);    MULADD(at[19], at[112]);    MULADD(at[20], at[111]);    MULADD(at[21], at[110]);    MULADD(at[22], at[109]);    MULADD(at[23], at[108]);    MULADD(at[24], at[107]);    MULADD(at[25], at[106]);    MULADD(at[26], at[105]);    MULADD(at[27], at[104]);    MULADD(at[28], at[103]);    MULADD(at[29], at[102]);    MULADD(at[30], at[101]);    MULADD(at[31], at[100]);    MULADD(at[32], at[99]);    MULADD(at[33], at[98]);    MULADD(at[34], at[97]);    MULADD(at[35], at[96]);    MULADD(at[36], at[95]);    MULADD(at[37], at[94]);    MULADD(at[38], at[93]);    MULADD(at[39], at[92]);    MULADD(at[40], at[91]);    MULADD(at[41], at[90]);    MULADD(at[42], at[89]);    MULADD(at[43], at[88]);    MULADD(at[44], at[87]);    MULADD(at[45], at[86]);    MULADD(at[46], at[85]);    MULADD(at[47], at[84]);    MULADD(at[48], at[83]);    MULADD(at[49], at[82]);    MULADD(at[50], at[81]);    MULADD(at[51], at[80]);    MULADD(at[52], at[79]);    MULADD(at[53], at[78]);    MULADD(at[54], at[77]);    MULADD(at[55], at[76]);    MULADD(at[56], at[75]);    MULADD(at[57], at[74]);    MULADD(at[58], at[73]);    MULADD(at[59], at[72]);    MULADD(at[60], at[71]);    MULADD(at[61], at[70]);    MULADD(at[62], at[69]);    MULADD(at[63], at[68]); 
+   COMBA_STORE(C->dp[67]);
+   /* 68 */
+   COMBA_FORWARD;
+   MULADD(at[5], at[127]);    MULADD(at[6], at[126]);    MULADD(at[7], at[125]);    MULADD(at[8], at[124]);    MULADD(at[9], at[123]);    MULADD(at[10], at[122]);    MULADD(at[11], at[121]);    MULADD(at[12], at[120]);    MULADD(at[13], at[119]);    MULADD(at[14], at[118]);    MULADD(at[15], at[117]);    MULADD(at[16], at[116]);    MULADD(at[17], at[115]);    MULADD(at[18], at[114]);    MULADD(at[19], at[113]);    MULADD(at[20], at[112]);    MULADD(at[21], at[111]);    MULADD(at[22], at[110]);    MULADD(at[23], at[109]);    MULADD(at[24], at[108]);    MULADD(at[25], at[107]);    MULADD(at[26], at[106]);    MULADD(at[27], at[105]);    MULADD(at[28], at[104]);    MULADD(at[29], at[103]);    MULADD(at[30], at[102]);    MULADD(at[31], at[101]);    MULADD(at[32], at[100]);    MULADD(at[33], at[99]);    MULADD(at[34], at[98]);    MULADD(at[35], at[97]);    MULADD(at[36], at[96]);    MULADD(at[37], at[95]);    MULADD(at[38], at[94]);    MULADD(at[39], at[93]);    MULADD(at[40], at[92]);    MULADD(at[41], at[91]);    MULADD(at[42], at[90]);    MULADD(at[43], at[89]);    MULADD(at[44], at[88]);    MULADD(at[45], at[87]);    MULADD(at[46], at[86]);    MULADD(at[47], at[85]);    MULADD(at[48], at[84]);    MULADD(at[49], at[83]);    MULADD(at[50], at[82]);    MULADD(at[51], at[81]);    MULADD(at[52], at[80]);    MULADD(at[53], at[79]);    MULADD(at[54], at[78]);    MULADD(at[55], at[77]);    MULADD(at[56], at[76]);    MULADD(at[57], at[75]);    MULADD(at[58], at[74]);    MULADD(at[59], at[73]);    MULADD(at[60], at[72]);    MULADD(at[61], at[71]);    MULADD(at[62], at[70]);    MULADD(at[63], at[69]); 
+   COMBA_STORE(C->dp[68]);
+   /* 69 */
+   COMBA_FORWARD;
+   MULADD(at[6], at[127]);    MULADD(at[7], at[126]);    MULADD(at[8], at[125]);    MULADD(at[9], at[124]);    MULADD(at[10], at[123]);    MULADD(at[11], at[122]);    MULADD(at[12], at[121]);    MULADD(at[13], at[120]);    MULADD(at[14], at[119]);    MULADD(at[15], at[118]);    MULADD(at[16], at[117]);    MULADD(at[17], at[116]);    MULADD(at[18], at[115]);    MULADD(at[19], at[114]);    MULADD(at[20], at[113]);    MULADD(at[21], at[112]);    MULADD(at[22], at[111]);    MULADD(at[23], at[110]);    MULADD(at[24], at[109]);    MULADD(at[25], at[108]);    MULADD(at[26], at[107]);    MULADD(at[27], at[106]);    MULADD(at[28], at[105]);    MULADD(at[29], at[104]);    MULADD(at[30], at[103]);    MULADD(at[31], at[102]);    MULADD(at[32], at[101]);    MULADD(at[33], at[100]);    MULADD(at[34], at[99]);    MULADD(at[35], at[98]);    MULADD(at[36], at[97]);    MULADD(at[37], at[96]);    MULADD(at[38], at[95]);    MULADD(at[39], at[94]);    MULADD(at[40], at[93]);    MULADD(at[41], at[92]);    MULADD(at[42], at[91]);    MULADD(at[43], at[90]);    MULADD(at[44], at[89]);    MULADD(at[45], at[88]);    MULADD(at[46], at[87]);    MULADD(at[47], at[86]);    MULADD(at[48], at[85]);    MULADD(at[49], at[84]);    MULADD(at[50], at[83]);    MULADD(at[51], at[82]);    MULADD(at[52], at[81]);    MULADD(at[53], at[80]);    MULADD(at[54], at[79]);    MULADD(at[55], at[78]);    MULADD(at[56], at[77]);    MULADD(at[57], at[76]);    MULADD(at[58], at[75]);    MULADD(at[59], at[74]);    MULADD(at[60], at[73]);    MULADD(at[61], at[72]);    MULADD(at[62], at[71]);    MULADD(at[63], at[70]); 
+   COMBA_STORE(C->dp[69]);
+   /* 70 */
+   COMBA_FORWARD;
+   MULADD(at[7], at[127]);    MULADD(at[8], at[126]);    MULADD(at[9], at[125]);    MULADD(at[10], at[124]);    MULADD(at[11], at[123]);    MULADD(at[12], at[122]);    MULADD(at[13], at[121]);    MULADD(at[14], at[120]);    MULADD(at[15], at[119]);    MULADD(at[16], at[118]);    MULADD(at[17], at[117]);    MULADD(at[18], at[116]);    MULADD(at[19], at[115]);    MULADD(at[20], at[114]);    MULADD(at[21], at[113]);    MULADD(at[22], at[112]);    MULADD(at[23], at[111]);    MULADD(at[24], at[110]);    MULADD(at[25], at[109]);    MULADD(at[26], at[108]);    MULADD(at[27], at[107]);    MULADD(at[28], at[106]);    MULADD(at[29], at[105]);    MULADD(at[30], at[104]);    MULADD(at[31], at[103]);    MULADD(at[32], at[102]);    MULADD(at[33], at[101]);    MULADD(at[34], at[100]);    MULADD(at[35], at[99]);    MULADD(at[36], at[98]);    MULADD(at[37], at[97]);    MULADD(at[38], at[96]);    MULADD(at[39], at[95]);    MULADD(at[40], at[94]);    MULADD(at[41], at[93]);    MULADD(at[42], at[92]);    MULADD(at[43], at[91]);    MULADD(at[44], at[90]);    MULADD(at[45], at[89]);    MULADD(at[46], at[88]);    MULADD(at[47], at[87]);    MULADD(at[48], at[86]);    MULADD(at[49], at[85]);    MULADD(at[50], at[84]);    MULADD(at[51], at[83]);    MULADD(at[52], at[82]);    MULADD(at[53], at[81]);    MULADD(at[54], at[80]);    MULADD(at[55], at[79]);    MULADD(at[56], at[78]);    MULADD(at[57], at[77]);    MULADD(at[58], at[76]);    MULADD(at[59], at[75]);    MULADD(at[60], at[74]);    MULADD(at[61], at[73]);    MULADD(at[62], at[72]);    MULADD(at[63], at[71]); 
+   COMBA_STORE(C->dp[70]);
+   /* 71 */
+   COMBA_FORWARD;
+   MULADD(at[8], at[127]);    MULADD(at[9], at[126]);    MULADD(at[10], at[125]);    MULADD(at[11], at[124]);    MULADD(at[12], at[123]);    MULADD(at[13], at[122]);    MULADD(at[14], at[121]);    MULADD(at[15], at[120]);    MULADD(at[16], at[119]);    MULADD(at[17], at[118]);    MULADD(at[18], at[117]);    MULADD(at[19], at[116]);    MULADD(at[20], at[115]);    MULADD(at[21], at[114]);    MULADD(at[22], at[113]);    MULADD(at[23], at[112]);    MULADD(at[24], at[111]);    MULADD(at[25], at[110]);    MULADD(at[26], at[109]);    MULADD(at[27], at[108]);    MULADD(at[28], at[107]);    MULADD(at[29], at[106]);    MULADD(at[30], at[105]);    MULADD(at[31], at[104]);    MULADD(at[32], at[103]);    MULADD(at[33], at[102]);    MULADD(at[34], at[101]);    MULADD(at[35], at[100]);    MULADD(at[36], at[99]);    MULADD(at[37], at[98]);    MULADD(at[38], at[97]);    MULADD(at[39], at[96]);    MULADD(at[40], at[95]);    MULADD(at[41], at[94]);    MULADD(at[42], at[93]);    MULADD(at[43], at[92]);    MULADD(at[44], at[91]);    MULADD(at[45], at[90]);    MULADD(at[46], at[89]);    MULADD(at[47], at[88]);    MULADD(at[48], at[87]);    MULADD(at[49], at[86]);    MULADD(at[50], at[85]);    MULADD(at[51], at[84]);    MULADD(at[52], at[83]);    MULADD(at[53], at[82]);    MULADD(at[54], at[81]);    MULADD(at[55], at[80]);    MULADD(at[56], at[79]);    MULADD(at[57], at[78]);    MULADD(at[58], at[77]);    MULADD(at[59], at[76]);    MULADD(at[60], at[75]);    MULADD(at[61], at[74]);    MULADD(at[62], at[73]);    MULADD(at[63], at[72]); 
+   COMBA_STORE(C->dp[71]);
+   /* 72 */
+   COMBA_FORWARD;
+   MULADD(at[9], at[127]);    MULADD(at[10], at[126]);    MULADD(at[11], at[125]);    MULADD(at[12], at[124]);    MULADD(at[13], at[123]);    MULADD(at[14], at[122]);    MULADD(at[15], at[121]);    MULADD(at[16], at[120]);    MULADD(at[17], at[119]);    MULADD(at[18], at[118]);    MULADD(at[19], at[117]);    MULADD(at[20], at[116]);    MULADD(at[21], at[115]);    MULADD(at[22], at[114]);    MULADD(at[23], at[113]);    MULADD(at[24], at[112]);    MULADD(at[25], at[111]);    MULADD(at[26], at[110]);    MULADD(at[27], at[109]);    MULADD(at[28], at[108]);    MULADD(at[29], at[107]);    MULADD(at[30], at[106]);    MULADD(at[31], at[105]);    MULADD(at[32], at[104]);    MULADD(at[33], at[103]);    MULADD(at[34], at[102]);    MULADD(at[35], at[101]);    MULADD(at[36], at[100]);    MULADD(at[37], at[99]);    MULADD(at[38], at[98]);    MULADD(at[39], at[97]);    MULADD(at[40], at[96]);    MULADD(at[41], at[95]);    MULADD(at[42], at[94]);    MULADD(at[43], at[93]);    MULADD(at[44], at[92]);    MULADD(at[45], at[91]);    MULADD(at[46], at[90]);    MULADD(at[47], at[89]);    MULADD(at[48], at[88]);    MULADD(at[49], at[87]);    MULADD(at[50], at[86]);    MULADD(at[51], at[85]);    MULADD(at[52], at[84]);    MULADD(at[53], at[83]);    MULADD(at[54], at[82]);    MULADD(at[55], at[81]);    MULADD(at[56], at[80]);    MULADD(at[57], at[79]);    MULADD(at[58], at[78]);    MULADD(at[59], at[77]);    MULADD(at[60], at[76]);    MULADD(at[61], at[75]);    MULADD(at[62], at[74]);    MULADD(at[63], at[73]); 
+   COMBA_STORE(C->dp[72]);
+   /* 73 */
+   COMBA_FORWARD;
+   MULADD(at[10], at[127]);    MULADD(at[11], at[126]);    MULADD(at[12], at[125]);    MULADD(at[13], at[124]);    MULADD(at[14], at[123]);    MULADD(at[15], at[122]);    MULADD(at[16], at[121]);    MULADD(at[17], at[120]);    MULADD(at[18], at[119]);    MULADD(at[19], at[118]);    MULADD(at[20], at[117]);    MULADD(at[21], at[116]);    MULADD(at[22], at[115]);    MULADD(at[23], at[114]);    MULADD(at[24], at[113]);    MULADD(at[25], at[112]);    MULADD(at[26], at[111]);    MULADD(at[27], at[110]);    MULADD(at[28], at[109]);    MULADD(at[29], at[108]);    MULADD(at[30], at[107]);    MULADD(at[31], at[106]);    MULADD(at[32], at[105]);    MULADD(at[33], at[104]);    MULADD(at[34], at[103]);    MULADD(at[35], at[102]);    MULADD(at[36], at[101]);    MULADD(at[37], at[100]);    MULADD(at[38], at[99]);    MULADD(at[39], at[98]);    MULADD(at[40], at[97]);    MULADD(at[41], at[96]);    MULADD(at[42], at[95]);    MULADD(at[43], at[94]);    MULADD(at[44], at[93]);    MULADD(at[45], at[92]);    MULADD(at[46], at[91]);    MULADD(at[47], at[90]);    MULADD(at[48], at[89]);    MULADD(at[49], at[88]);    MULADD(at[50], at[87]);    MULADD(at[51], at[86]);    MULADD(at[52], at[85]);    MULADD(at[53], at[84]);    MULADD(at[54], at[83]);    MULADD(at[55], at[82]);    MULADD(at[56], at[81]);    MULADD(at[57], at[80]);    MULADD(at[58], at[79]);    MULADD(at[59], at[78]);    MULADD(at[60], at[77]);    MULADD(at[61], at[76]);    MULADD(at[62], at[75]);    MULADD(at[63], at[74]); 
+   COMBA_STORE(C->dp[73]);
+   /* 74 */
+   COMBA_FORWARD;
+   MULADD(at[11], at[127]);    MULADD(at[12], at[126]);    MULADD(at[13], at[125]);    MULADD(at[14], at[124]);    MULADD(at[15], at[123]);    MULADD(at[16], at[122]);    MULADD(at[17], at[121]);    MULADD(at[18], at[120]);    MULADD(at[19], at[119]);    MULADD(at[20], at[118]);    MULADD(at[21], at[117]);    MULADD(at[22], at[116]);    MULADD(at[23], at[115]);    MULADD(at[24], at[114]);    MULADD(at[25], at[113]);    MULADD(at[26], at[112]);    MULADD(at[27], at[111]);    MULADD(at[28], at[110]);    MULADD(at[29], at[109]);    MULADD(at[30], at[108]);    MULADD(at[31], at[107]);    MULADD(at[32], at[106]);    MULADD(at[33], at[105]);    MULADD(at[34], at[104]);    MULADD(at[35], at[103]);    MULADD(at[36], at[102]);    MULADD(at[37], at[101]);    MULADD(at[38], at[100]);    MULADD(at[39], at[99]);    MULADD(at[40], at[98]);    MULADD(at[41], at[97]);    MULADD(at[42], at[96]);    MULADD(at[43], at[95]);    MULADD(at[44], at[94]);    MULADD(at[45], at[93]);    MULADD(at[46], at[92]);    MULADD(at[47], at[91]);    MULADD(at[48], at[90]);    MULADD(at[49], at[89]);    MULADD(at[50], at[88]);    MULADD(at[51], at[87]);    MULADD(at[52], at[86]);    MULADD(at[53], at[85]);    MULADD(at[54], at[84]);    MULADD(at[55], at[83]);    MULADD(at[56], at[82]);    MULADD(at[57], at[81]);    MULADD(at[58], at[80]);    MULADD(at[59], at[79]);    MULADD(at[60], at[78]);    MULADD(at[61], at[77]);    MULADD(at[62], at[76]);    MULADD(at[63], at[75]); 
+   COMBA_STORE(C->dp[74]);
+   /* 75 */
+   COMBA_FORWARD;
+   MULADD(at[12], at[127]);    MULADD(at[13], at[126]);    MULADD(at[14], at[125]);    MULADD(at[15], at[124]);    MULADD(at[16], at[123]);    MULADD(at[17], at[122]);    MULADD(at[18], at[121]);    MULADD(at[19], at[120]);    MULADD(at[20], at[119]);    MULADD(at[21], at[118]);    MULADD(at[22], at[117]);    MULADD(at[23], at[116]);    MULADD(at[24], at[115]);    MULADD(at[25], at[114]);    MULADD(at[26], at[113]);    MULADD(at[27], at[112]);    MULADD(at[28], at[111]);    MULADD(at[29], at[110]);    MULADD(at[30], at[109]);    MULADD(at[31], at[108]);    MULADD(at[32], at[107]);    MULADD(at[33], at[106]);    MULADD(at[34], at[105]);    MULADD(at[35], at[104]);    MULADD(at[36], at[103]);    MULADD(at[37], at[102]);    MULADD(at[38], at[101]);    MULADD(at[39], at[100]);    MULADD(at[40], at[99]);    MULADD(at[41], at[98]);    MULADD(at[42], at[97]);    MULADD(at[43], at[96]);    MULADD(at[44], at[95]);    MULADD(at[45], at[94]);    MULADD(at[46], at[93]);    MULADD(at[47], at[92]);    MULADD(at[48], at[91]);    MULADD(at[49], at[90]);    MULADD(at[50], at[89]);    MULADD(at[51], at[88]);    MULADD(at[52], at[87]);    MULADD(at[53], at[86]);    MULADD(at[54], at[85]);    MULADD(at[55], at[84]);    MULADD(at[56], at[83]);    MULADD(at[57], at[82]);    MULADD(at[58], at[81]);    MULADD(at[59], at[80]);    MULADD(at[60], at[79]);    MULADD(at[61], at[78]);    MULADD(at[62], at[77]);    MULADD(at[63], at[76]); 
+   COMBA_STORE(C->dp[75]);
+   /* 76 */
+   COMBA_FORWARD;
+   MULADD(at[13], at[127]);    MULADD(at[14], at[126]);    MULADD(at[15], at[125]);    MULADD(at[16], at[124]);    MULADD(at[17], at[123]);    MULADD(at[18], at[122]);    MULADD(at[19], at[121]);    MULADD(at[20], at[120]);    MULADD(at[21], at[119]);    MULADD(at[22], at[118]);    MULADD(at[23], at[117]);    MULADD(at[24], at[116]);    MULADD(at[25], at[115]);    MULADD(at[26], at[114]);    MULADD(at[27], at[113]);    MULADD(at[28], at[112]);    MULADD(at[29], at[111]);    MULADD(at[30], at[110]);    MULADD(at[31], at[109]);    MULADD(at[32], at[108]);    MULADD(at[33], at[107]);    MULADD(at[34], at[106]);    MULADD(at[35], at[105]);    MULADD(at[36], at[104]);    MULADD(at[37], at[103]);    MULADD(at[38], at[102]);    MULADD(at[39], at[101]);    MULADD(at[40], at[100]);    MULADD(at[41], at[99]);    MULADD(at[42], at[98]);    MULADD(at[43], at[97]);    MULADD(at[44], at[96]);    MULADD(at[45], at[95]);    MULADD(at[46], at[94]);    MULADD(at[47], at[93]);    MULADD(at[48], at[92]);    MULADD(at[49], at[91]);    MULADD(at[50], at[90]);    MULADD(at[51], at[89]);    MULADD(at[52], at[88]);    MULADD(at[53], at[87]);    MULADD(at[54], at[86]);    MULADD(at[55], at[85]);    MULADD(at[56], at[84]);    MULADD(at[57], at[83]);    MULADD(at[58], at[82]);    MULADD(at[59], at[81]);    MULADD(at[60], at[80]);    MULADD(at[61], at[79]);    MULADD(at[62], at[78]);    MULADD(at[63], at[77]); 
+   COMBA_STORE(C->dp[76]);
+   /* 77 */
+   COMBA_FORWARD;
+   MULADD(at[14], at[127]);    MULADD(at[15], at[126]);    MULADD(at[16], at[125]);    MULADD(at[17], at[124]);    MULADD(at[18], at[123]);    MULADD(at[19], at[122]);    MULADD(at[20], at[121]);    MULADD(at[21], at[120]);    MULADD(at[22], at[119]);    MULADD(at[23], at[118]);    MULADD(at[24], at[117]);    MULADD(at[25], at[116]);    MULADD(at[26], at[115]);    MULADD(at[27], at[114]);    MULADD(at[28], at[113]);    MULADD(at[29], at[112]);    MULADD(at[30], at[111]);    MULADD(at[31], at[110]);    MULADD(at[32], at[109]);    MULADD(at[33], at[108]);    MULADD(at[34], at[107]);    MULADD(at[35], at[106]);    MULADD(at[36], at[105]);    MULADD(at[37], at[104]);    MULADD(at[38], at[103]);    MULADD(at[39], at[102]);    MULADD(at[40], at[101]);    MULADD(at[41], at[100]);    MULADD(at[42], at[99]);    MULADD(at[43], at[98]);    MULADD(at[44], at[97]);    MULADD(at[45], at[96]);    MULADD(at[46], at[95]);    MULADD(at[47], at[94]);    MULADD(at[48], at[93]);    MULADD(at[49], at[92]);    MULADD(at[50], at[91]);    MULADD(at[51], at[90]);    MULADD(at[52], at[89]);    MULADD(at[53], at[88]);    MULADD(at[54], at[87]);    MULADD(at[55], at[86]);    MULADD(at[56], at[85]);    MULADD(at[57], at[84]);    MULADD(at[58], at[83]);    MULADD(at[59], at[82]);    MULADD(at[60], at[81]);    MULADD(at[61], at[80]);    MULADD(at[62], at[79]);    MULADD(at[63], at[78]); 
+   COMBA_STORE(C->dp[77]);
+   /* 78 */
+   COMBA_FORWARD;
+   MULADD(at[15], at[127]);    MULADD(at[16], at[126]);    MULADD(at[17], at[125]);    MULADD(at[18], at[124]);    MULADD(at[19], at[123]);    MULADD(at[20], at[122]);    MULADD(at[21], at[121]);    MULADD(at[22], at[120]);    MULADD(at[23], at[119]);    MULADD(at[24], at[118]);    MULADD(at[25], at[117]);    MULADD(at[26], at[116]);    MULADD(at[27], at[115]);    MULADD(at[28], at[114]);    MULADD(at[29], at[113]);    MULADD(at[30], at[112]);    MULADD(at[31], at[111]);    MULADD(at[32], at[110]);    MULADD(at[33], at[109]);    MULADD(at[34], at[108]);    MULADD(at[35], at[107]);    MULADD(at[36], at[106]);    MULADD(at[37], at[105]);    MULADD(at[38], at[104]);    MULADD(at[39], at[103]);    MULADD(at[40], at[102]);    MULADD(at[41], at[101]);    MULADD(at[42], at[100]);    MULADD(at[43], at[99]);    MULADD(at[44], at[98]);    MULADD(at[45], at[97]);    MULADD(at[46], at[96]);    MULADD(at[47], at[95]);    MULADD(at[48], at[94]);    MULADD(at[49], at[93]);    MULADD(at[50], at[92]);    MULADD(at[51], at[91]);    MULADD(at[52], at[90]);    MULADD(at[53], at[89]);    MULADD(at[54], at[88]);    MULADD(at[55], at[87]);    MULADD(at[56], at[86]);    MULADD(at[57], at[85]);    MULADD(at[58], at[84]);    MULADD(at[59], at[83]);    MULADD(at[60], at[82]);    MULADD(at[61], at[81]);    MULADD(at[62], at[80]);    MULADD(at[63], at[79]); 
+   COMBA_STORE(C->dp[78]);
+   /* 79 */
+   COMBA_FORWARD;
+   MULADD(at[16], at[127]);    MULADD(at[17], at[126]);    MULADD(at[18], at[125]);    MULADD(at[19], at[124]);    MULADD(at[20], at[123]);    MULADD(at[21], at[122]);    MULADD(at[22], at[121]);    MULADD(at[23], at[120]);    MULADD(at[24], at[119]);    MULADD(at[25], at[118]);    MULADD(at[26], at[117]);    MULADD(at[27], at[116]);    MULADD(at[28], at[115]);    MULADD(at[29], at[114]);    MULADD(at[30], at[113]);    MULADD(at[31], at[112]);    MULADD(at[32], at[111]);    MULADD(at[33], at[110]);    MULADD(at[34], at[109]);    MULADD(at[35], at[108]);    MULADD(at[36], at[107]);    MULADD(at[37], at[106]);    MULADD(at[38], at[105]);    MULADD(at[39], at[104]);    MULADD(at[40], at[103]);    MULADD(at[41], at[102]);    MULADD(at[42], at[101]);    MULADD(at[43], at[100]);    MULADD(at[44], at[99]);    MULADD(at[45], at[98]);    MULADD(at[46], at[97]);    MULADD(at[47], at[96]);    MULADD(at[48], at[95]);    MULADD(at[49], at[94]);    MULADD(at[50], at[93]);    MULADD(at[51], at[92]);    MULADD(at[52], at[91]);    MULADD(at[53], at[90]);    MULADD(at[54], at[89]);    MULADD(at[55], at[88]);    MULADD(at[56], at[87]);    MULADD(at[57], at[86]);    MULADD(at[58], at[85]);    MULADD(at[59], at[84]);    MULADD(at[60], at[83]);    MULADD(at[61], at[82]);    MULADD(at[62], at[81]);    MULADD(at[63], at[80]); 
+   COMBA_STORE(C->dp[79]);
+   /* 80 */
+   COMBA_FORWARD;
+   MULADD(at[17], at[127]);    MULADD(at[18], at[126]);    MULADD(at[19], at[125]);    MULADD(at[20], at[124]);    MULADD(at[21], at[123]);    MULADD(at[22], at[122]);    MULADD(at[23], at[121]);    MULADD(at[24], at[120]);    MULADD(at[25], at[119]);    MULADD(at[26], at[118]);    MULADD(at[27], at[117]);    MULADD(at[28], at[116]);    MULADD(at[29], at[115]);    MULADD(at[30], at[114]);    MULADD(at[31], at[113]);    MULADD(at[32], at[112]);    MULADD(at[33], at[111]);    MULADD(at[34], at[110]);    MULADD(at[35], at[109]);    MULADD(at[36], at[108]);    MULADD(at[37], at[107]);    MULADD(at[38], at[106]);    MULADD(at[39], at[105]);    MULADD(at[40], at[104]);    MULADD(at[41], at[103]);    MULADD(at[42], at[102]);    MULADD(at[43], at[101]);    MULADD(at[44], at[100]);    MULADD(at[45], at[99]);    MULADD(at[46], at[98]);    MULADD(at[47], at[97]);    MULADD(at[48], at[96]);    MULADD(at[49], at[95]);    MULADD(at[50], at[94]);    MULADD(at[51], at[93]);    MULADD(at[52], at[92]);    MULADD(at[53], at[91]);    MULADD(at[54], at[90]);    MULADD(at[55], at[89]);    MULADD(at[56], at[88]);    MULADD(at[57], at[87]);    MULADD(at[58], at[86]);    MULADD(at[59], at[85]);    MULADD(at[60], at[84]);    MULADD(at[61], at[83]);    MULADD(at[62], at[82]);    MULADD(at[63], at[81]); 
+   COMBA_STORE(C->dp[80]);
+   /* 81 */
+   COMBA_FORWARD;
+   MULADD(at[18], at[127]);    MULADD(at[19], at[126]);    MULADD(at[20], at[125]);    MULADD(at[21], at[124]);    MULADD(at[22], at[123]);    MULADD(at[23], at[122]);    MULADD(at[24], at[121]);    MULADD(at[25], at[120]);    MULADD(at[26], at[119]);    MULADD(at[27], at[118]);    MULADD(at[28], at[117]);    MULADD(at[29], at[116]);    MULADD(at[30], at[115]);    MULADD(at[31], at[114]);    MULADD(at[32], at[113]);    MULADD(at[33], at[112]);    MULADD(at[34], at[111]);    MULADD(at[35], at[110]);    MULADD(at[36], at[109]);    MULADD(at[37], at[108]);    MULADD(at[38], at[107]);    MULADD(at[39], at[106]);    MULADD(at[40], at[105]);    MULADD(at[41], at[104]);    MULADD(at[42], at[103]);    MULADD(at[43], at[102]);    MULADD(at[44], at[101]);    MULADD(at[45], at[100]);    MULADD(at[46], at[99]);    MULADD(at[47], at[98]);    MULADD(at[48], at[97]);    MULADD(at[49], at[96]);    MULADD(at[50], at[95]);    MULADD(at[51], at[94]);    MULADD(at[52], at[93]);    MULADD(at[53], at[92]);    MULADD(at[54], at[91]);    MULADD(at[55], at[90]);    MULADD(at[56], at[89]);    MULADD(at[57], at[88]);    MULADD(at[58], at[87]);    MULADD(at[59], at[86]);    MULADD(at[60], at[85]);    MULADD(at[61], at[84]);    MULADD(at[62], at[83]);    MULADD(at[63], at[82]); 
+   COMBA_STORE(C->dp[81]);
+   /* 82 */
+   COMBA_FORWARD;
+   MULADD(at[19], at[127]);    MULADD(at[20], at[126]);    MULADD(at[21], at[125]);    MULADD(at[22], at[124]);    MULADD(at[23], at[123]);    MULADD(at[24], at[122]);    MULADD(at[25], at[121]);    MULADD(at[26], at[120]);    MULADD(at[27], at[119]);    MULADD(at[28], at[118]);    MULADD(at[29], at[117]);    MULADD(at[30], at[116]);    MULADD(at[31], at[115]);    MULADD(at[32], at[114]);    MULADD(at[33], at[113]);    MULADD(at[34], at[112]);    MULADD(at[35], at[111]);    MULADD(at[36], at[110]);    MULADD(at[37], at[109]);    MULADD(at[38], at[108]);    MULADD(at[39], at[107]);    MULADD(at[40], at[106]);    MULADD(at[41], at[105]);    MULADD(at[42], at[104]);    MULADD(at[43], at[103]);    MULADD(at[44], at[102]);    MULADD(at[45], at[101]);    MULADD(at[46], at[100]);    MULADD(at[47], at[99]);    MULADD(at[48], at[98]);    MULADD(at[49], at[97]);    MULADD(at[50], at[96]);    MULADD(at[51], at[95]);    MULADD(at[52], at[94]);    MULADD(at[53], at[93]);    MULADD(at[54], at[92]);    MULADD(at[55], at[91]);    MULADD(at[56], at[90]);    MULADD(at[57], at[89]);    MULADD(at[58], at[88]);    MULADD(at[59], at[87]);    MULADD(at[60], at[86]);    MULADD(at[61], at[85]);    MULADD(at[62], at[84]);    MULADD(at[63], at[83]); 
+   COMBA_STORE(C->dp[82]);
+   /* 83 */
+   COMBA_FORWARD;
+   MULADD(at[20], at[127]);    MULADD(at[21], at[126]);    MULADD(at[22], at[125]);    MULADD(at[23], at[124]);    MULADD(at[24], at[123]);    MULADD(at[25], at[122]);    MULADD(at[26], at[121]);    MULADD(at[27], at[120]);    MULADD(at[28], at[119]);    MULADD(at[29], at[118]);    MULADD(at[30], at[117]);    MULADD(at[31], at[116]);    MULADD(at[32], at[115]);    MULADD(at[33], at[114]);    MULADD(at[34], at[113]);    MULADD(at[35], at[112]);    MULADD(at[36], at[111]);    MULADD(at[37], at[110]);    MULADD(at[38], at[109]);    MULADD(at[39], at[108]);    MULADD(at[40], at[107]);    MULADD(at[41], at[106]);    MULADD(at[42], at[105]);    MULADD(at[43], at[104]);    MULADD(at[44], at[103]);    MULADD(at[45], at[102]);    MULADD(at[46], at[101]);    MULADD(at[47], at[100]);    MULADD(at[48], at[99]);    MULADD(at[49], at[98]);    MULADD(at[50], at[97]);    MULADD(at[51], at[96]);    MULADD(at[52], at[95]);    MULADD(at[53], at[94]);    MULADD(at[54], at[93]);    MULADD(at[55], at[92]);    MULADD(at[56], at[91]);    MULADD(at[57], at[90]);    MULADD(at[58], at[89]);    MULADD(at[59], at[88]);    MULADD(at[60], at[87]);    MULADD(at[61], at[86]);    MULADD(at[62], at[85]);    MULADD(at[63], at[84]); 
+   COMBA_STORE(C->dp[83]);
+   /* 84 */
+   COMBA_FORWARD;
+   MULADD(at[21], at[127]);    MULADD(at[22], at[126]);    MULADD(at[23], at[125]);    MULADD(at[24], at[124]);    MULADD(at[25], at[123]);    MULADD(at[26], at[122]);    MULADD(at[27], at[121]);    MULADD(at[28], at[120]);    MULADD(at[29], at[119]);    MULADD(at[30], at[118]);    MULADD(at[31], at[117]);    MULADD(at[32], at[116]);    MULADD(at[33], at[115]);    MULADD(at[34], at[114]);    MULADD(at[35], at[113]);    MULADD(at[36], at[112]);    MULADD(at[37], at[111]);    MULADD(at[38], at[110]);    MULADD(at[39], at[109]);    MULADD(at[40], at[108]);    MULADD(at[41], at[107]);    MULADD(at[42], at[106]);    MULADD(at[43], at[105]);    MULADD(at[44], at[104]);    MULADD(at[45], at[103]);    MULADD(at[46], at[102]);    MULADD(at[47], at[101]);    MULADD(at[48], at[100]);    MULADD(at[49], at[99]);    MULADD(at[50], at[98]);    MULADD(at[51], at[97]);    MULADD(at[52], at[96]);    MULADD(at[53], at[95]);    MULADD(at[54], at[94]);    MULADD(at[55], at[93]);    MULADD(at[56], at[92]);    MULADD(at[57], at[91]);    MULADD(at[58], at[90]);    MULADD(at[59], at[89]);    MULADD(at[60], at[88]);    MULADD(at[61], at[87]);    MULADD(at[62], at[86]);    MULADD(at[63], at[85]); 
+   COMBA_STORE(C->dp[84]);
+   /* 85 */
+   COMBA_FORWARD;
+   MULADD(at[22], at[127]);    MULADD(at[23], at[126]);    MULADD(at[24], at[125]);    MULADD(at[25], at[124]);    MULADD(at[26], at[123]);    MULADD(at[27], at[122]);    MULADD(at[28], at[121]);    MULADD(at[29], at[120]);    MULADD(at[30], at[119]);    MULADD(at[31], at[118]);    MULADD(at[32], at[117]);    MULADD(at[33], at[116]);    MULADD(at[34], at[115]);    MULADD(at[35], at[114]);    MULADD(at[36], at[113]);    MULADD(at[37], at[112]);    MULADD(at[38], at[111]);    MULADD(at[39], at[110]);    MULADD(at[40], at[109]);    MULADD(at[41], at[108]);    MULADD(at[42], at[107]);    MULADD(at[43], at[106]);    MULADD(at[44], at[105]);    MULADD(at[45], at[104]);    MULADD(at[46], at[103]);    MULADD(at[47], at[102]);    MULADD(at[48], at[101]);    MULADD(at[49], at[100]);    MULADD(at[50], at[99]);    MULADD(at[51], at[98]);    MULADD(at[52], at[97]);    MULADD(at[53], at[96]);    MULADD(at[54], at[95]);    MULADD(at[55], at[94]);    MULADD(at[56], at[93]);    MULADD(at[57], at[92]);    MULADD(at[58], at[91]);    MULADD(at[59], at[90]);    MULADD(at[60], at[89]);    MULADD(at[61], at[88]);    MULADD(at[62], at[87]);    MULADD(at[63], at[86]); 
+   COMBA_STORE(C->dp[85]);
+   /* 86 */
+   COMBA_FORWARD;
+   MULADD(at[23], at[127]);    MULADD(at[24], at[126]);    MULADD(at[25], at[125]);    MULADD(at[26], at[124]);    MULADD(at[27], at[123]);    MULADD(at[28], at[122]);    MULADD(at[29], at[121]);    MULADD(at[30], at[120]);    MULADD(at[31], at[119]);    MULADD(at[32], at[118]);    MULADD(at[33], at[117]);    MULADD(at[34], at[116]);    MULADD(at[35], at[115]);    MULADD(at[36], at[114]);    MULADD(at[37], at[113]);    MULADD(at[38], at[112]);    MULADD(at[39], at[111]);    MULADD(at[40], at[110]);    MULADD(at[41], at[109]);    MULADD(at[42], at[108]);    MULADD(at[43], at[107]);    MULADD(at[44], at[106]);    MULADD(at[45], at[105]);    MULADD(at[46], at[104]);    MULADD(at[47], at[103]);    MULADD(at[48], at[102]);    MULADD(at[49], at[101]);    MULADD(at[50], at[100]);    MULADD(at[51], at[99]);    MULADD(at[52], at[98]);    MULADD(at[53], at[97]);    MULADD(at[54], at[96]);    MULADD(at[55], at[95]);    MULADD(at[56], at[94]);    MULADD(at[57], at[93]);    MULADD(at[58], at[92]);    MULADD(at[59], at[91]);    MULADD(at[60], at[90]);    MULADD(at[61], at[89]);    MULADD(at[62], at[88]);    MULADD(at[63], at[87]); 
+   COMBA_STORE(C->dp[86]);
+   /* 87 */
+   COMBA_FORWARD;
+   MULADD(at[24], at[127]);    MULADD(at[25], at[126]);    MULADD(at[26], at[125]);    MULADD(at[27], at[124]);    MULADD(at[28], at[123]);    MULADD(at[29], at[122]);    MULADD(at[30], at[121]);    MULADD(at[31], at[120]);    MULADD(at[32], at[119]);    MULADD(at[33], at[118]);    MULADD(at[34], at[117]);    MULADD(at[35], at[116]);    MULADD(at[36], at[115]);    MULADD(at[37], at[114]);    MULADD(at[38], at[113]);    MULADD(at[39], at[112]);    MULADD(at[40], at[111]);    MULADD(at[41], at[110]);    MULADD(at[42], at[109]);    MULADD(at[43], at[108]);    MULADD(at[44], at[107]);    MULADD(at[45], at[106]);    MULADD(at[46], at[105]);    MULADD(at[47], at[104]);    MULADD(at[48], at[103]);    MULADD(at[49], at[102]);    MULADD(at[50], at[101]);    MULADD(at[51], at[100]);    MULADD(at[52], at[99]);    MULADD(at[53], at[98]);    MULADD(at[54], at[97]);    MULADD(at[55], at[96]);    MULADD(at[56], at[95]);    MULADD(at[57], at[94]);    MULADD(at[58], at[93]);    MULADD(at[59], at[92]);    MULADD(at[60], at[91]);    MULADD(at[61], at[90]);    MULADD(at[62], at[89]);    MULADD(at[63], at[88]); 
+   COMBA_STORE(C->dp[87]);
+   /* 88 */
+   COMBA_FORWARD;
+   MULADD(at[25], at[127]);    MULADD(at[26], at[126]);    MULADD(at[27], at[125]);    MULADD(at[28], at[124]);    MULADD(at[29], at[123]);    MULADD(at[30], at[122]);    MULADD(at[31], at[121]);    MULADD(at[32], at[120]);    MULADD(at[33], at[119]);    MULADD(at[34], at[118]);    MULADD(at[35], at[117]);    MULADD(at[36], at[116]);    MULADD(at[37], at[115]);    MULADD(at[38], at[114]);    MULADD(at[39], at[113]);    MULADD(at[40], at[112]);    MULADD(at[41], at[111]);    MULADD(at[42], at[110]);    MULADD(at[43], at[109]);    MULADD(at[44], at[108]);    MULADD(at[45], at[107]);    MULADD(at[46], at[106]);    MULADD(at[47], at[105]);    MULADD(at[48], at[104]);    MULADD(at[49], at[103]);    MULADD(at[50], at[102]);    MULADD(at[51], at[101]);    MULADD(at[52], at[100]);    MULADD(at[53], at[99]);    MULADD(at[54], at[98]);    MULADD(at[55], at[97]);    MULADD(at[56], at[96]);    MULADD(at[57], at[95]);    MULADD(at[58], at[94]);    MULADD(at[59], at[93]);    MULADD(at[60], at[92]);    MULADD(at[61], at[91]);    MULADD(at[62], at[90]);    MULADD(at[63], at[89]); 
+   COMBA_STORE(C->dp[88]);
+   /* 89 */
+   COMBA_FORWARD;
+   MULADD(at[26], at[127]);    MULADD(at[27], at[126]);    MULADD(at[28], at[125]);    MULADD(at[29], at[124]);    MULADD(at[30], at[123]);    MULADD(at[31], at[122]);    MULADD(at[32], at[121]);    MULADD(at[33], at[120]);    MULADD(at[34], at[119]);    MULADD(at[35], at[118]);    MULADD(at[36], at[117]);    MULADD(at[37], at[116]);    MULADD(at[38], at[115]);    MULADD(at[39], at[114]);    MULADD(at[40], at[113]);    MULADD(at[41], at[112]);    MULADD(at[42], at[111]);    MULADD(at[43], at[110]);    MULADD(at[44], at[109]);    MULADD(at[45], at[108]);    MULADD(at[46], at[107]);    MULADD(at[47], at[106]);    MULADD(at[48], at[105]);    MULADD(at[49], at[104]);    MULADD(at[50], at[103]);    MULADD(at[51], at[102]);    MULADD(at[52], at[101]);    MULADD(at[53], at[100]);    MULADD(at[54], at[99]);    MULADD(at[55], at[98]);    MULADD(at[56], at[97]);    MULADD(at[57], at[96]);    MULADD(at[58], at[95]);    MULADD(at[59], at[94]);    MULADD(at[60], at[93]);    MULADD(at[61], at[92]);    MULADD(at[62], at[91]);    MULADD(at[63], at[90]); 
+   COMBA_STORE(C->dp[89]);
+   /* 90 */
+   COMBA_FORWARD;
+   MULADD(at[27], at[127]);    MULADD(at[28], at[126]);    MULADD(at[29], at[125]);    MULADD(at[30], at[124]);    MULADD(at[31], at[123]);    MULADD(at[32], at[122]);    MULADD(at[33], at[121]);    MULADD(at[34], at[120]);    MULADD(at[35], at[119]);    MULADD(at[36], at[118]);    MULADD(at[37], at[117]);    MULADD(at[38], at[116]);    MULADD(at[39], at[115]);    MULADD(at[40], at[114]);    MULADD(at[41], at[113]);    MULADD(at[42], at[112]);    MULADD(at[43], at[111]);    MULADD(at[44], at[110]);    MULADD(at[45], at[109]);    MULADD(at[46], at[108]);    MULADD(at[47], at[107]);    MULADD(at[48], at[106]);    MULADD(at[49], at[105]);    MULADD(at[50], at[104]);    MULADD(at[51], at[103]);    MULADD(at[52], at[102]);    MULADD(at[53], at[101]);    MULADD(at[54], at[100]);    MULADD(at[55], at[99]);    MULADD(at[56], at[98]);    MULADD(at[57], at[97]);    MULADD(at[58], at[96]);    MULADD(at[59], at[95]);    MULADD(at[60], at[94]);    MULADD(at[61], at[93]);    MULADD(at[62], at[92]);    MULADD(at[63], at[91]); 
+   COMBA_STORE(C->dp[90]);
+   /* 91 */
+   COMBA_FORWARD;
+   MULADD(at[28], at[127]);    MULADD(at[29], at[126]);    MULADD(at[30], at[125]);    MULADD(at[31], at[124]);    MULADD(at[32], at[123]);    MULADD(at[33], at[122]);    MULADD(at[34], at[121]);    MULADD(at[35], at[120]);    MULADD(at[36], at[119]);    MULADD(at[37], at[118]);    MULADD(at[38], at[117]);    MULADD(at[39], at[116]);    MULADD(at[40], at[115]);    MULADD(at[41], at[114]);    MULADD(at[42], at[113]);    MULADD(at[43], at[112]);    MULADD(at[44], at[111]);    MULADD(at[45], at[110]);    MULADD(at[46], at[109]);    MULADD(at[47], at[108]);    MULADD(at[48], at[107]);    MULADD(at[49], at[106]);    MULADD(at[50], at[105]);    MULADD(at[51], at[104]);    MULADD(at[52], at[103]);    MULADD(at[53], at[102]);    MULADD(at[54], at[101]);    MULADD(at[55], at[100]);    MULADD(at[56], at[99]);    MULADD(at[57], at[98]);    MULADD(at[58], at[97]);    MULADD(at[59], at[96]);    MULADD(at[60], at[95]);    MULADD(at[61], at[94]);    MULADD(at[62], at[93]);    MULADD(at[63], at[92]); 
+   COMBA_STORE(C->dp[91]);
+   /* 92 */
+   COMBA_FORWARD;
+   MULADD(at[29], at[127]);    MULADD(at[30], at[126]);    MULADD(at[31], at[125]);    MULADD(at[32], at[124]);    MULADD(at[33], at[123]);    MULADD(at[34], at[122]);    MULADD(at[35], at[121]);    MULADD(at[36], at[120]);    MULADD(at[37], at[119]);    MULADD(at[38], at[118]);    MULADD(at[39], at[117]);    MULADD(at[40], at[116]);    MULADD(at[41], at[115]);    MULADD(at[42], at[114]);    MULADD(at[43], at[113]);    MULADD(at[44], at[112]);    MULADD(at[45], at[111]);    MULADD(at[46], at[110]);    MULADD(at[47], at[109]);    MULADD(at[48], at[108]);    MULADD(at[49], at[107]);    MULADD(at[50], at[106]);    MULADD(at[51], at[105]);    MULADD(at[52], at[104]);    MULADD(at[53], at[103]);    MULADD(at[54], at[102]);    MULADD(at[55], at[101]);    MULADD(at[56], at[100]);    MULADD(at[57], at[99]);    MULADD(at[58], at[98]);    MULADD(at[59], at[97]);    MULADD(at[60], at[96]);    MULADD(at[61], at[95]);    MULADD(at[62], at[94]);    MULADD(at[63], at[93]); 
+   COMBA_STORE(C->dp[92]);
+   /* 93 */
+   COMBA_FORWARD;
+   MULADD(at[30], at[127]);    MULADD(at[31], at[126]);    MULADD(at[32], at[125]);    MULADD(at[33], at[124]);    MULADD(at[34], at[123]);    MULADD(at[35], at[122]);    MULADD(at[36], at[121]);    MULADD(at[37], at[120]);    MULADD(at[38], at[119]);    MULADD(at[39], at[118]);    MULADD(at[40], at[117]);    MULADD(at[41], at[116]);    MULADD(at[42], at[115]);    MULADD(at[43], at[114]);    MULADD(at[44], at[113]);    MULADD(at[45], at[112]);    MULADD(at[46], at[111]);    MULADD(at[47], at[110]);    MULADD(at[48], at[109]);    MULADD(at[49], at[108]);    MULADD(at[50], at[107]);    MULADD(at[51], at[106]);    MULADD(at[52], at[105]);    MULADD(at[53], at[104]);    MULADD(at[54], at[103]);    MULADD(at[55], at[102]);    MULADD(at[56], at[101]);    MULADD(at[57], at[100]);    MULADD(at[58], at[99]);    MULADD(at[59], at[98]);    MULADD(at[60], at[97]);    MULADD(at[61], at[96]);    MULADD(at[62], at[95]);    MULADD(at[63], at[94]); 
+   COMBA_STORE(C->dp[93]);
+   /* 94 */
+   COMBA_FORWARD;
+   MULADD(at[31], at[127]);    MULADD(at[32], at[126]);    MULADD(at[33], at[125]);    MULADD(at[34], at[124]);    MULADD(at[35], at[123]);    MULADD(at[36], at[122]);    MULADD(at[37], at[121]);    MULADD(at[38], at[120]);    MULADD(at[39], at[119]);    MULADD(at[40], at[118]);    MULADD(at[41], at[117]);    MULADD(at[42], at[116]);    MULADD(at[43], at[115]);    MULADD(at[44], at[114]);    MULADD(at[45], at[113]);    MULADD(at[46], at[112]);    MULADD(at[47], at[111]);    MULADD(at[48], at[110]);    MULADD(at[49], at[109]);    MULADD(at[50], at[108]);    MULADD(at[51], at[107]);    MULADD(at[52], at[106]);    MULADD(at[53], at[105]);    MULADD(at[54], at[104]);    MULADD(at[55], at[103]);    MULADD(at[56], at[102]);    MULADD(at[57], at[101]);    MULADD(at[58], at[100]);    MULADD(at[59], at[99]);    MULADD(at[60], at[98]);    MULADD(at[61], at[97]);    MULADD(at[62], at[96]);    MULADD(at[63], at[95]); 
+   COMBA_STORE(C->dp[94]);
+   /* 95 */
+   COMBA_FORWARD;
+   MULADD(at[32], at[127]);    MULADD(at[33], at[126]);    MULADD(at[34], at[125]);    MULADD(at[35], at[124]);    MULADD(at[36], at[123]);    MULADD(at[37], at[122]);    MULADD(at[38], at[121]);    MULADD(at[39], at[120]);    MULADD(at[40], at[119]);    MULADD(at[41], at[118]);    MULADD(at[42], at[117]);    MULADD(at[43], at[116]);    MULADD(at[44], at[115]);    MULADD(at[45], at[114]);    MULADD(at[46], at[113]);    MULADD(at[47], at[112]);    MULADD(at[48], at[111]);    MULADD(at[49], at[110]);    MULADD(at[50], at[109]);    MULADD(at[51], at[108]);    MULADD(at[52], at[107]);    MULADD(at[53], at[106]);    MULADD(at[54], at[105]);    MULADD(at[55], at[104]);    MULADD(at[56], at[103]);    MULADD(at[57], at[102]);    MULADD(at[58], at[101]);    MULADD(at[59], at[100]);    MULADD(at[60], at[99]);    MULADD(at[61], at[98]);    MULADD(at[62], at[97]);    MULADD(at[63], at[96]); 
+   COMBA_STORE(C->dp[95]);
+   /* 96 */
+   COMBA_FORWARD;
+   MULADD(at[33], at[127]);    MULADD(at[34], at[126]);    MULADD(at[35], at[125]);    MULADD(at[36], at[124]);    MULADD(at[37], at[123]);    MULADD(at[38], at[122]);    MULADD(at[39], at[121]);    MULADD(at[40], at[120]);    MULADD(at[41], at[119]);    MULADD(at[42], at[118]);    MULADD(at[43], at[117]);    MULADD(at[44], at[116]);    MULADD(at[45], at[115]);    MULADD(at[46], at[114]);    MULADD(at[47], at[113]);    MULADD(at[48], at[112]);    MULADD(at[49], at[111]);    MULADD(at[50], at[110]);    MULADD(at[51], at[109]);    MULADD(at[52], at[108]);    MULADD(at[53], at[107]);    MULADD(at[54], at[106]);    MULADD(at[55], at[105]);    MULADD(at[56], at[104]);    MULADD(at[57], at[103]);    MULADD(at[58], at[102]);    MULADD(at[59], at[101]);    MULADD(at[60], at[100]);    MULADD(at[61], at[99]);    MULADD(at[62], at[98]);    MULADD(at[63], at[97]); 
+   COMBA_STORE(C->dp[96]);
+   /* 97 */
+   COMBA_FORWARD;
+   MULADD(at[34], at[127]);    MULADD(at[35], at[126]);    MULADD(at[36], at[125]);    MULADD(at[37], at[124]);    MULADD(at[38], at[123]);    MULADD(at[39], at[122]);    MULADD(at[40], at[121]);    MULADD(at[41], at[120]);    MULADD(at[42], at[119]);    MULADD(at[43], at[118]);    MULADD(at[44], at[117]);    MULADD(at[45], at[116]);    MULADD(at[46], at[115]);    MULADD(at[47], at[114]);    MULADD(at[48], at[113]);    MULADD(at[49], at[112]);    MULADD(at[50], at[111]);    MULADD(at[51], at[110]);    MULADD(at[52], at[109]);    MULADD(at[53], at[108]);    MULADD(at[54], at[107]);    MULADD(at[55], at[106]);    MULADD(at[56], at[105]);    MULADD(at[57], at[104]);    MULADD(at[58], at[103]);    MULADD(at[59], at[102]);    MULADD(at[60], at[101]);    MULADD(at[61], at[100]);    MULADD(at[62], at[99]);    MULADD(at[63], at[98]); 
+   COMBA_STORE(C->dp[97]);
+   /* 98 */
+   COMBA_FORWARD;
+   MULADD(at[35], at[127]);    MULADD(at[36], at[126]);    MULADD(at[37], at[125]);    MULADD(at[38], at[124]);    MULADD(at[39], at[123]);    MULADD(at[40], at[122]);    MULADD(at[41], at[121]);    MULADD(at[42], at[120]);    MULADD(at[43], at[119]);    MULADD(at[44], at[118]);    MULADD(at[45], at[117]);    MULADD(at[46], at[116]);    MULADD(at[47], at[115]);    MULADD(at[48], at[114]);    MULADD(at[49], at[113]);    MULADD(at[50], at[112]);    MULADD(at[51], at[111]);    MULADD(at[52], at[110]);    MULADD(at[53], at[109]);    MULADD(at[54], at[108]);    MULADD(at[55], at[107]);    MULADD(at[56], at[106]);    MULADD(at[57], at[105]);    MULADD(at[58], at[104]);    MULADD(at[59], at[103]);    MULADD(at[60], at[102]);    MULADD(at[61], at[101]);    MULADD(at[62], at[100]);    MULADD(at[63], at[99]); 
+   COMBA_STORE(C->dp[98]);
+   /* 99 */
+   COMBA_FORWARD;
+   MULADD(at[36], at[127]);    MULADD(at[37], at[126]);    MULADD(at[38], at[125]);    MULADD(at[39], at[124]);    MULADD(at[40], at[123]);    MULADD(at[41], at[122]);    MULADD(at[42], at[121]);    MULADD(at[43], at[120]);    MULADD(at[44], at[119]);    MULADD(at[45], at[118]);    MULADD(at[46], at[117]);    MULADD(at[47], at[116]);    MULADD(at[48], at[115]);    MULADD(at[49], at[114]);    MULADD(at[50], at[113]);    MULADD(at[51], at[112]);    MULADD(at[52], at[111]);    MULADD(at[53], at[110]);    MULADD(at[54], at[109]);    MULADD(at[55], at[108]);    MULADD(at[56], at[107]);    MULADD(at[57], at[106]);    MULADD(at[58], at[105]);    MULADD(at[59], at[104]);    MULADD(at[60], at[103]);    MULADD(at[61], at[102]);    MULADD(at[62], at[101]);    MULADD(at[63], at[100]); 
+   COMBA_STORE(C->dp[99]);
+   /* 100 */
+   COMBA_FORWARD;
+   MULADD(at[37], at[127]);    MULADD(at[38], at[126]);    MULADD(at[39], at[125]);    MULADD(at[40], at[124]);    MULADD(at[41], at[123]);    MULADD(at[42], at[122]);    MULADD(at[43], at[121]);    MULADD(at[44], at[120]);    MULADD(at[45], at[119]);    MULADD(at[46], at[118]);    MULADD(at[47], at[117]);    MULADD(at[48], at[116]);    MULADD(at[49], at[115]);    MULADD(at[50], at[114]);    MULADD(at[51], at[113]);    MULADD(at[52], at[112]);    MULADD(at[53], at[111]);    MULADD(at[54], at[110]);    MULADD(at[55], at[109]);    MULADD(at[56], at[108]);    MULADD(at[57], at[107]);    MULADD(at[58], at[106]);    MULADD(at[59], at[105]);    MULADD(at[60], at[104]);    MULADD(at[61], at[103]);    MULADD(at[62], at[102]);    MULADD(at[63], at[101]); 
+   COMBA_STORE(C->dp[100]);
+   /* 101 */
+   COMBA_FORWARD;
+   MULADD(at[38], at[127]);    MULADD(at[39], at[126]);    MULADD(at[40], at[125]);    MULADD(at[41], at[124]);    MULADD(at[42], at[123]);    MULADD(at[43], at[122]);    MULADD(at[44], at[121]);    MULADD(at[45], at[120]);    MULADD(at[46], at[119]);    MULADD(at[47], at[118]);    MULADD(at[48], at[117]);    MULADD(at[49], at[116]);    MULADD(at[50], at[115]);    MULADD(at[51], at[114]);    MULADD(at[52], at[113]);    MULADD(at[53], at[112]);    MULADD(at[54], at[111]);    MULADD(at[55], at[110]);    MULADD(at[56], at[109]);    MULADD(at[57], at[108]);    MULADD(at[58], at[107]);    MULADD(at[59], at[106]);    MULADD(at[60], at[105]);    MULADD(at[61], at[104]);    MULADD(at[62], at[103]);    MULADD(at[63], at[102]); 
+   COMBA_STORE(C->dp[101]);
+   /* 102 */
+   COMBA_FORWARD;
+   MULADD(at[39], at[127]);    MULADD(at[40], at[126]);    MULADD(at[41], at[125]);    MULADD(at[42], at[124]);    MULADD(at[43], at[123]);    MULADD(at[44], at[122]);    MULADD(at[45], at[121]);    MULADD(at[46], at[120]);    MULADD(at[47], at[119]);    MULADD(at[48], at[118]);    MULADD(at[49], at[117]);    MULADD(at[50], at[116]);    MULADD(at[51], at[115]);    MULADD(at[52], at[114]);    MULADD(at[53], at[113]);    MULADD(at[54], at[112]);    MULADD(at[55], at[111]);    MULADD(at[56], at[110]);    MULADD(at[57], at[109]);    MULADD(at[58], at[108]);    MULADD(at[59], at[107]);    MULADD(at[60], at[106]);    MULADD(at[61], at[105]);    MULADD(at[62], at[104]);    MULADD(at[63], at[103]); 
+   COMBA_STORE(C->dp[102]);
+   /* 103 */
+   COMBA_FORWARD;
+   MULADD(at[40], at[127]);    MULADD(at[41], at[126]);    MULADD(at[42], at[125]);    MULADD(at[43], at[124]);    MULADD(at[44], at[123]);    MULADD(at[45], at[122]);    MULADD(at[46], at[121]);    MULADD(at[47], at[120]);    MULADD(at[48], at[119]);    MULADD(at[49], at[118]);    MULADD(at[50], at[117]);    MULADD(at[51], at[116]);    MULADD(at[52], at[115]);    MULADD(at[53], at[114]);    MULADD(at[54], at[113]);    MULADD(at[55], at[112]);    MULADD(at[56], at[111]);    MULADD(at[57], at[110]);    MULADD(at[58], at[109]);    MULADD(at[59], at[108]);    MULADD(at[60], at[107]);    MULADD(at[61], at[106]);    MULADD(at[62], at[105]);    MULADD(at[63], at[104]); 
+   COMBA_STORE(C->dp[103]);
+   /* 104 */
+   COMBA_FORWARD;
+   MULADD(at[41], at[127]);    MULADD(at[42], at[126]);    MULADD(at[43], at[125]);    MULADD(at[44], at[124]);    MULADD(at[45], at[123]);    MULADD(at[46], at[122]);    MULADD(at[47], at[121]);    MULADD(at[48], at[120]);    MULADD(at[49], at[119]);    MULADD(at[50], at[118]);    MULADD(at[51], at[117]);    MULADD(at[52], at[116]);    MULADD(at[53], at[115]);    MULADD(at[54], at[114]);    MULADD(at[55], at[113]);    MULADD(at[56], at[112]);    MULADD(at[57], at[111]);    MULADD(at[58], at[110]);    MULADD(at[59], at[109]);    MULADD(at[60], at[108]);    MULADD(at[61], at[107]);    MULADD(at[62], at[106]);    MULADD(at[63], at[105]); 
+   COMBA_STORE(C->dp[104]);
+   /* 105 */
+   COMBA_FORWARD;
+   MULADD(at[42], at[127]);    MULADD(at[43], at[126]);    MULADD(at[44], at[125]);    MULADD(at[45], at[124]);    MULADD(at[46], at[123]);    MULADD(at[47], at[122]);    MULADD(at[48], at[121]);    MULADD(at[49], at[120]);    MULADD(at[50], at[119]);    MULADD(at[51], at[118]);    MULADD(at[52], at[117]);    MULADD(at[53], at[116]);    MULADD(at[54], at[115]);    MULADD(at[55], at[114]);    MULADD(at[56], at[113]);    MULADD(at[57], at[112]);    MULADD(at[58], at[111]);    MULADD(at[59], at[110]);    MULADD(at[60], at[109]);    MULADD(at[61], at[108]);    MULADD(at[62], at[107]);    MULADD(at[63], at[106]); 
+   COMBA_STORE(C->dp[105]);
+   /* 106 */
+   COMBA_FORWARD;
+   MULADD(at[43], at[127]);    MULADD(at[44], at[126]);    MULADD(at[45], at[125]);    MULADD(at[46], at[124]);    MULADD(at[47], at[123]);    MULADD(at[48], at[122]);    MULADD(at[49], at[121]);    MULADD(at[50], at[120]);    MULADD(at[51], at[119]);    MULADD(at[52], at[118]);    MULADD(at[53], at[117]);    MULADD(at[54], at[116]);    MULADD(at[55], at[115]);    MULADD(at[56], at[114]);    MULADD(at[57], at[113]);    MULADD(at[58], at[112]);    MULADD(at[59], at[111]);    MULADD(at[60], at[110]);    MULADD(at[61], at[109]);    MULADD(at[62], at[108]);    MULADD(at[63], at[107]); 
+   COMBA_STORE(C->dp[106]);
+   /* 107 */
+   COMBA_FORWARD;
+   MULADD(at[44], at[127]);    MULADD(at[45], at[126]);    MULADD(at[46], at[125]);    MULADD(at[47], at[124]);    MULADD(at[48], at[123]);    MULADD(at[49], at[122]);    MULADD(at[50], at[121]);    MULADD(at[51], at[120]);    MULADD(at[52], at[119]);    MULADD(at[53], at[118]);    MULADD(at[54], at[117]);    MULADD(at[55], at[116]);    MULADD(at[56], at[115]);    MULADD(at[57], at[114]);    MULADD(at[58], at[113]);    MULADD(at[59], at[112]);    MULADD(at[60], at[111]);    MULADD(at[61], at[110]);    MULADD(at[62], at[109]);    MULADD(at[63], at[108]); 
+   COMBA_STORE(C->dp[107]);
+   /* 108 */
+   COMBA_FORWARD;
+   MULADD(at[45], at[127]);    MULADD(at[46], at[126]);    MULADD(at[47], at[125]);    MULADD(at[48], at[124]);    MULADD(at[49], at[123]);    MULADD(at[50], at[122]);    MULADD(at[51], at[121]);    MULADD(at[52], at[120]);    MULADD(at[53], at[119]);    MULADD(at[54], at[118]);    MULADD(at[55], at[117]);    MULADD(at[56], at[116]);    MULADD(at[57], at[115]);    MULADD(at[58], at[114]);    MULADD(at[59], at[113]);    MULADD(at[60], at[112]);    MULADD(at[61], at[111]);    MULADD(at[62], at[110]);    MULADD(at[63], at[109]); 
+   COMBA_STORE(C->dp[108]);
+   /* 109 */
+   COMBA_FORWARD;
+   MULADD(at[46], at[127]);    MULADD(at[47], at[126]);    MULADD(at[48], at[125]);    MULADD(at[49], at[124]);    MULADD(at[50], at[123]);    MULADD(at[51], at[122]);    MULADD(at[52], at[121]);    MULADD(at[53], at[120]);    MULADD(at[54], at[119]);    MULADD(at[55], at[118]);    MULADD(at[56], at[117]);    MULADD(at[57], at[116]);    MULADD(at[58], at[115]);    MULADD(at[59], at[114]);    MULADD(at[60], at[113]);    MULADD(at[61], at[112]);    MULADD(at[62], at[111]);    MULADD(at[63], at[110]); 
+   COMBA_STORE(C->dp[109]);
+   /* 110 */
+   COMBA_FORWARD;
+   MULADD(at[47], at[127]);    MULADD(at[48], at[126]);    MULADD(at[49], at[125]);    MULADD(at[50], at[124]);    MULADD(at[51], at[123]);    MULADD(at[52], at[122]);    MULADD(at[53], at[121]);    MULADD(at[54], at[120]);    MULADD(at[55], at[119]);    MULADD(at[56], at[118]);    MULADD(at[57], at[117]);    MULADD(at[58], at[116]);    MULADD(at[59], at[115]);    MULADD(at[60], at[114]);    MULADD(at[61], at[113]);    MULADD(at[62], at[112]);    MULADD(at[63], at[111]); 
+   COMBA_STORE(C->dp[110]);
+   /* 111 */
+   COMBA_FORWARD;
+   MULADD(at[48], at[127]);    MULADD(at[49], at[126]);    MULADD(at[50], at[125]);    MULADD(at[51], at[124]);    MULADD(at[52], at[123]);    MULADD(at[53], at[122]);    MULADD(at[54], at[121]);    MULADD(at[55], at[120]);    MULADD(at[56], at[119]);    MULADD(at[57], at[118]);    MULADD(at[58], at[117]);    MULADD(at[59], at[116]);    MULADD(at[60], at[115]);    MULADD(at[61], at[114]);    MULADD(at[62], at[113]);    MULADD(at[63], at[112]); 
+   COMBA_STORE(C->dp[111]);
+   /* 112 */
+   COMBA_FORWARD;
+   MULADD(at[49], at[127]);    MULADD(at[50], at[126]);    MULADD(at[51], at[125]);    MULADD(at[52], at[124]);    MULADD(at[53], at[123]);    MULADD(at[54], at[122]);    MULADD(at[55], at[121]);    MULADD(at[56], at[120]);    MULADD(at[57], at[119]);    MULADD(at[58], at[118]);    MULADD(at[59], at[117]);    MULADD(at[60], at[116]);    MULADD(at[61], at[115]);    MULADD(at[62], at[114]);    MULADD(at[63], at[113]); 
+   COMBA_STORE(C->dp[112]);
+   /* 113 */
+   COMBA_FORWARD;
+   MULADD(at[50], at[127]);    MULADD(at[51], at[126]);    MULADD(at[52], at[125]);    MULADD(at[53], at[124]);    MULADD(at[54], at[123]);    MULADD(at[55], at[122]);    MULADD(at[56], at[121]);    MULADD(at[57], at[120]);    MULADD(at[58], at[119]);    MULADD(at[59], at[118]);    MULADD(at[60], at[117]);    MULADD(at[61], at[116]);    MULADD(at[62], at[115]);    MULADD(at[63], at[114]); 
+   COMBA_STORE(C->dp[113]);
+   /* 114 */
+   COMBA_FORWARD;
+   MULADD(at[51], at[127]);    MULADD(at[52], at[126]);    MULADD(at[53], at[125]);    MULADD(at[54], at[124]);    MULADD(at[55], at[123]);    MULADD(at[56], at[122]);    MULADD(at[57], at[121]);    MULADD(at[58], at[120]);    MULADD(at[59], at[119]);    MULADD(at[60], at[118]);    MULADD(at[61], at[117]);    MULADD(at[62], at[116]);    MULADD(at[63], at[115]); 
+   COMBA_STORE(C->dp[114]);
+   /* 115 */
+   COMBA_FORWARD;
+   MULADD(at[52], at[127]);    MULADD(at[53], at[126]);    MULADD(at[54], at[125]);    MULADD(at[55], at[124]);    MULADD(at[56], at[123]);    MULADD(at[57], at[122]);    MULADD(at[58], at[121]);    MULADD(at[59], at[120]);    MULADD(at[60], at[119]);    MULADD(at[61], at[118]);    MULADD(at[62], at[117]);    MULADD(at[63], at[116]); 
+   COMBA_STORE(C->dp[115]);
+   /* 116 */
+   COMBA_FORWARD;
+   MULADD(at[53], at[127]);    MULADD(at[54], at[126]);    MULADD(at[55], at[125]);    MULADD(at[56], at[124]);    MULADD(at[57], at[123]);    MULADD(at[58], at[122]);    MULADD(at[59], at[121]);    MULADD(at[60], at[120]);    MULADD(at[61], at[119]);    MULADD(at[62], at[118]);    MULADD(at[63], at[117]); 
+   COMBA_STORE(C->dp[116]);
+   /* 117 */
+   COMBA_FORWARD;
+   MULADD(at[54], at[127]);    MULADD(at[55], at[126]);    MULADD(at[56], at[125]);    MULADD(at[57], at[124]);    MULADD(at[58], at[123]);    MULADD(at[59], at[122]);    MULADD(at[60], at[121]);    MULADD(at[61], at[120]);    MULADD(at[62], at[119]);    MULADD(at[63], at[118]); 
+   COMBA_STORE(C->dp[117]);
+   /* 118 */
+   COMBA_FORWARD;
+   MULADD(at[55], at[127]);    MULADD(at[56], at[126]);    MULADD(at[57], at[125]);    MULADD(at[58], at[124]);    MULADD(at[59], at[123]);    MULADD(at[60], at[122]);    MULADD(at[61], at[121]);    MULADD(at[62], at[120]);    MULADD(at[63], at[119]); 
+   COMBA_STORE(C->dp[118]);
+   /* 119 */
+   COMBA_FORWARD;
+   MULADD(at[56], at[127]);    MULADD(at[57], at[126]);    MULADD(at[58], at[125]);    MULADD(at[59], at[124]);    MULADD(at[60], at[123]);    MULADD(at[61], at[122]);    MULADD(at[62], at[121]);    MULADD(at[63], at[120]); 
+   COMBA_STORE(C->dp[119]);
+   /* 120 */
+   COMBA_FORWARD;
+   MULADD(at[57], at[127]);    MULADD(at[58], at[126]);    MULADD(at[59], at[125]);    MULADD(at[60], at[124]);    MULADD(at[61], at[123]);    MULADD(at[62], at[122]);    MULADD(at[63], at[121]); 
+   COMBA_STORE(C->dp[120]);
+   /* 121 */
+   COMBA_FORWARD;
+   MULADD(at[58], at[127]);    MULADD(at[59], at[126]);    MULADD(at[60], at[125]);    MULADD(at[61], at[124]);    MULADD(at[62], at[123]);    MULADD(at[63], at[122]); 
+   COMBA_STORE(C->dp[121]);
+   /* 122 */
+   COMBA_FORWARD;
+   MULADD(at[59], at[127]);    MULADD(at[60], at[126]);    MULADD(at[61], at[125]);    MULADD(at[62], at[124]);    MULADD(at[63], at[123]); 
+   COMBA_STORE(C->dp[122]);
+   /* 123 */
+   COMBA_FORWARD;
+   MULADD(at[60], at[127]);    MULADD(at[61], at[126]);    MULADD(at[62], at[125]);    MULADD(at[63], at[124]); 
+   COMBA_STORE(C->dp[123]);
+   /* 124 */
+   COMBA_FORWARD;
+   MULADD(at[61], at[127]);    MULADD(at[62], at[126]);    MULADD(at[63], at[125]); 
+   COMBA_STORE(C->dp[124]);
+   /* 125 */
+   COMBA_FORWARD;
+   MULADD(at[62], at[127]);    MULADD(at[63], at[126]); 
+   COMBA_STORE(C->dp[125]);
+   /* 126 */
+   COMBA_FORWARD;
+   MULADD(at[63], at[127]); 
+   COMBA_STORE(C->dp[126]);
+   COMBA_STORE2(C->dp[127]);
+   C->used = 128;
+   C->sign = A->sign ^ B->sign;
+   fp_clamp(C);
+   COMBA_FINI;
+}
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_7.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_7.i
new file mode 100644
index 0000000..eed8863
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_7.i
@@ -0,0 +1,90 @@
+/* fp_mul_comba_7.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_MUL7
+void fp_mul_comba7(fp_int *A, fp_int *B, fp_int *C)
+{
+   fp_digit c0, c1, c2, at[14];
+
+   memcpy(at, A->dp, 7 * sizeof(fp_digit));
+   memcpy(at+7, B->dp, 7 * sizeof(fp_digit));
+   COMBA_START;
+
+   COMBA_CLEAR;
+   /* 0 */
+   MULADD(at[0], at[7]); 
+   COMBA_STORE(C->dp[0]);
+   /* 1 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[8]);    MULADD(at[1], at[7]); 
+   COMBA_STORE(C->dp[1]);
+   /* 2 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[9]);    MULADD(at[1], at[8]);    MULADD(at[2], at[7]); 
+   COMBA_STORE(C->dp[2]);
+   /* 3 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[10]);    MULADD(at[1], at[9]);    MULADD(at[2], at[8]);    MULADD(at[3], at[7]); 
+   COMBA_STORE(C->dp[3]);
+   /* 4 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[11]);    MULADD(at[1], at[10]);    MULADD(at[2], at[9]);    MULADD(at[3], at[8]);    MULADD(at[4], at[7]); 
+   COMBA_STORE(C->dp[4]);
+   /* 5 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[12]);    MULADD(at[1], at[11]);    MULADD(at[2], at[10]);    MULADD(at[3], at[9]);    MULADD(at[4], at[8]);    MULADD(at[5], at[7]); 
+   COMBA_STORE(C->dp[5]);
+   /* 6 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[13]);    MULADD(at[1], at[12]);    MULADD(at[2], at[11]);    MULADD(at[3], at[10]);    MULADD(at[4], at[9]);    MULADD(at[5], at[8]);    MULADD(at[6], at[7]); 
+   COMBA_STORE(C->dp[6]);
+   /* 7 */
+   COMBA_FORWARD;
+   MULADD(at[1], at[13]);    MULADD(at[2], at[12]);    MULADD(at[3], at[11]);    MULADD(at[4], at[10]);    MULADD(at[5], at[9]);    MULADD(at[6], at[8]); 
+   COMBA_STORE(C->dp[7]);
+   /* 8 */
+   COMBA_FORWARD;
+   MULADD(at[2], at[13]);    MULADD(at[3], at[12]);    MULADD(at[4], at[11]);    MULADD(at[5], at[10]);    MULADD(at[6], at[9]); 
+   COMBA_STORE(C->dp[8]);
+   /* 9 */
+   COMBA_FORWARD;
+   MULADD(at[3], at[13]);    MULADD(at[4], at[12]);    MULADD(at[5], at[11]);    MULADD(at[6], at[10]); 
+   COMBA_STORE(C->dp[9]);
+   /* 10 */
+   COMBA_FORWARD;
+   MULADD(at[4], at[13]);    MULADD(at[5], at[12]);    MULADD(at[6], at[11]); 
+   COMBA_STORE(C->dp[10]);
+   /* 11 */
+   COMBA_FORWARD;
+   MULADD(at[5], at[13]);    MULADD(at[6], at[12]); 
+   COMBA_STORE(C->dp[11]);
+   /* 12 */
+   COMBA_FORWARD;
+   MULADD(at[6], at[13]); 
+   COMBA_STORE(C->dp[12]);
+   COMBA_STORE2(C->dp[13]);
+   C->used = 14;
+   C->sign = A->sign ^ B->sign;
+   fp_clamp(C);
+   COMBA_FINI;
+}
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_8.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_8.i
new file mode 100644
index 0000000..fa578a8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_8.i
@@ -0,0 +1,98 @@
+/* fp_mul_comba_8.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_MUL8
+void fp_mul_comba8(fp_int *A, fp_int *B, fp_int *C)
+{
+   fp_digit c0, c1, c2, at[16];
+
+   memcpy(at, A->dp, 8 * sizeof(fp_digit));
+   memcpy(at+8, B->dp, 8 * sizeof(fp_digit));
+   COMBA_START;
+
+   COMBA_CLEAR;
+   /* 0 */
+   MULADD(at[0], at[8]); 
+   COMBA_STORE(C->dp[0]);
+   /* 1 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[9]);    MULADD(at[1], at[8]); 
+   COMBA_STORE(C->dp[1]);
+   /* 2 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[10]);    MULADD(at[1], at[9]);    MULADD(at[2], at[8]); 
+   COMBA_STORE(C->dp[2]);
+   /* 3 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[11]);    MULADD(at[1], at[10]);    MULADD(at[2], at[9]);    MULADD(at[3], at[8]); 
+   COMBA_STORE(C->dp[3]);
+   /* 4 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[12]);    MULADD(at[1], at[11]);    MULADD(at[2], at[10]);    MULADD(at[3], at[9]);    MULADD(at[4], at[8]); 
+   COMBA_STORE(C->dp[4]);
+   /* 5 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[13]);    MULADD(at[1], at[12]);    MULADD(at[2], at[11]);    MULADD(at[3], at[10]);    MULADD(at[4], at[9]);    MULADD(at[5], at[8]); 
+   COMBA_STORE(C->dp[5]);
+   /* 6 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[14]);    MULADD(at[1], at[13]);    MULADD(at[2], at[12]);    MULADD(at[3], at[11]);    MULADD(at[4], at[10]);    MULADD(at[5], at[9]);    MULADD(at[6], at[8]); 
+   COMBA_STORE(C->dp[6]);
+   /* 7 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[15]);    MULADD(at[1], at[14]);    MULADD(at[2], at[13]);    MULADD(at[3], at[12]);    MULADD(at[4], at[11]);    MULADD(at[5], at[10]);    MULADD(at[6], at[9]);    MULADD(at[7], at[8]); 
+   COMBA_STORE(C->dp[7]);
+   /* 8 */
+   COMBA_FORWARD;
+   MULADD(at[1], at[15]);    MULADD(at[2], at[14]);    MULADD(at[3], at[13]);    MULADD(at[4], at[12]);    MULADD(at[5], at[11]);    MULADD(at[6], at[10]);    MULADD(at[7], at[9]); 
+   COMBA_STORE(C->dp[8]);
+   /* 9 */
+   COMBA_FORWARD;
+   MULADD(at[2], at[15]);    MULADD(at[3], at[14]);    MULADD(at[4], at[13]);    MULADD(at[5], at[12]);    MULADD(at[6], at[11]);    MULADD(at[7], at[10]); 
+   COMBA_STORE(C->dp[9]);
+   /* 10 */
+   COMBA_FORWARD;
+   MULADD(at[3], at[15]);    MULADD(at[4], at[14]);    MULADD(at[5], at[13]);    MULADD(at[6], at[12]);    MULADD(at[7], at[11]); 
+   COMBA_STORE(C->dp[10]);
+   /* 11 */
+   COMBA_FORWARD;
+   MULADD(at[4], at[15]);    MULADD(at[5], at[14]);    MULADD(at[6], at[13]);    MULADD(at[7], at[12]); 
+   COMBA_STORE(C->dp[11]);
+   /* 12 */
+   COMBA_FORWARD;
+   MULADD(at[5], at[15]);    MULADD(at[6], at[14]);    MULADD(at[7], at[13]); 
+   COMBA_STORE(C->dp[12]);
+   /* 13 */
+   COMBA_FORWARD;
+   MULADD(at[6], at[15]);    MULADD(at[7], at[14]); 
+   COMBA_STORE(C->dp[13]);
+   /* 14 */
+   COMBA_FORWARD;
+   MULADD(at[7], at[15]); 
+   COMBA_STORE(C->dp[14]);
+   COMBA_STORE2(C->dp[15]);
+   C->used = 16;
+   C->sign = A->sign ^ B->sign;
+   fp_clamp(C);
+   COMBA_FINI;
+}
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_9.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_9.i
new file mode 100644
index 0000000..755067f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_9.i
@@ -0,0 +1,106 @@
+/* fp_mul_comba_9.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_MUL9
+void fp_mul_comba9(fp_int *A, fp_int *B, fp_int *C)
+{
+   fp_digit c0, c1, c2, at[18];
+
+   memcpy(at, A->dp, 9 * sizeof(fp_digit));
+   memcpy(at+9, B->dp, 9 * sizeof(fp_digit));
+   COMBA_START;
+
+   COMBA_CLEAR;
+   /* 0 */
+   MULADD(at[0], at[9]); 
+   COMBA_STORE(C->dp[0]);
+   /* 1 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[10]);    MULADD(at[1], at[9]); 
+   COMBA_STORE(C->dp[1]);
+   /* 2 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[11]);    MULADD(at[1], at[10]);    MULADD(at[2], at[9]); 
+   COMBA_STORE(C->dp[2]);
+   /* 3 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[12]);    MULADD(at[1], at[11]);    MULADD(at[2], at[10]);    MULADD(at[3], at[9]); 
+   COMBA_STORE(C->dp[3]);
+   /* 4 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[13]);    MULADD(at[1], at[12]);    MULADD(at[2], at[11]);    MULADD(at[3], at[10]);    MULADD(at[4], at[9]); 
+   COMBA_STORE(C->dp[4]);
+   /* 5 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[14]);    MULADD(at[1], at[13]);    MULADD(at[2], at[12]);    MULADD(at[3], at[11]);    MULADD(at[4], at[10]);    MULADD(at[5], at[9]); 
+   COMBA_STORE(C->dp[5]);
+   /* 6 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[15]);    MULADD(at[1], at[14]);    MULADD(at[2], at[13]);    MULADD(at[3], at[12]);    MULADD(at[4], at[11]);    MULADD(at[5], at[10]);    MULADD(at[6], at[9]); 
+   COMBA_STORE(C->dp[6]);
+   /* 7 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[16]);    MULADD(at[1], at[15]);    MULADD(at[2], at[14]);    MULADD(at[3], at[13]);    MULADD(at[4], at[12]);    MULADD(at[5], at[11]);    MULADD(at[6], at[10]);    MULADD(at[7], at[9]); 
+   COMBA_STORE(C->dp[7]);
+   /* 8 */
+   COMBA_FORWARD;
+   MULADD(at[0], at[17]);    MULADD(at[1], at[16]);    MULADD(at[2], at[15]);    MULADD(at[3], at[14]);    MULADD(at[4], at[13]);    MULADD(at[5], at[12]);    MULADD(at[6], at[11]);    MULADD(at[7], at[10]);    MULADD(at[8], at[9]); 
+   COMBA_STORE(C->dp[8]);
+   /* 9 */
+   COMBA_FORWARD;
+   MULADD(at[1], at[17]);    MULADD(at[2], at[16]);    MULADD(at[3], at[15]);    MULADD(at[4], at[14]);    MULADD(at[5], at[13]);    MULADD(at[6], at[12]);    MULADD(at[7], at[11]);    MULADD(at[8], at[10]); 
+   COMBA_STORE(C->dp[9]);
+   /* 10 */
+   COMBA_FORWARD;
+   MULADD(at[2], at[17]);    MULADD(at[3], at[16]);    MULADD(at[4], at[15]);    MULADD(at[5], at[14]);    MULADD(at[6], at[13]);    MULADD(at[7], at[12]);    MULADD(at[8], at[11]); 
+   COMBA_STORE(C->dp[10]);
+   /* 11 */
+   COMBA_FORWARD;
+   MULADD(at[3], at[17]);    MULADD(at[4], at[16]);    MULADD(at[5], at[15]);    MULADD(at[6], at[14]);    MULADD(at[7], at[13]);    MULADD(at[8], at[12]); 
+   COMBA_STORE(C->dp[11]);
+   /* 12 */
+   COMBA_FORWARD;
+   MULADD(at[4], at[17]);    MULADD(at[5], at[16]);    MULADD(at[6], at[15]);    MULADD(at[7], at[14]);    MULADD(at[8], at[13]); 
+   COMBA_STORE(C->dp[12]);
+   /* 13 */
+   COMBA_FORWARD;
+   MULADD(at[5], at[17]);    MULADD(at[6], at[16]);    MULADD(at[7], at[15]);    MULADD(at[8], at[14]); 
+   COMBA_STORE(C->dp[13]);
+   /* 14 */
+   COMBA_FORWARD;
+   MULADD(at[6], at[17]);    MULADD(at[7], at[16]);    MULADD(at[8], at[15]); 
+   COMBA_STORE(C->dp[14]);
+   /* 15 */
+   COMBA_FORWARD;
+   MULADD(at[7], at[17]);    MULADD(at[8], at[16]); 
+   COMBA_STORE(C->dp[15]);
+   /* 16 */
+   COMBA_FORWARD;
+   MULADD(at[8], at[17]); 
+   COMBA_STORE(C->dp[16]);
+   COMBA_STORE2(C->dp[17]);
+   C->used = 18;
+   C->sign = A->sign ^ B->sign;
+   fp_clamp(C);
+   COMBA_FINI;
+}
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_small_set.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_small_set.i
new file mode 100644
index 0000000..deea593
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_mul_comba_small_set.i
@@ -0,0 +1,1250 @@
+/* fp_mul_comba_small_set.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#if defined(TFM_SMALL_SET)
+void fp_mul_comba_small(fp_int *A, fp_int *B, fp_int *C)
+{
+   fp_digit c0, c1, c2, at[32];
+   switch (MAX(A->used, B->used)) { 
+
+   case 1:
+      memcpy(at, A->dp, 1 * sizeof(fp_digit));
+      memcpy(at+1, B->dp, 1 * sizeof(fp_digit));
+      COMBA_START;
+
+      COMBA_CLEAR;
+      /* 0 */
+      MULADD(at[0], at[1]); 
+      COMBA_STORE(C->dp[0]);
+      COMBA_STORE2(C->dp[1]);
+      C->used = 2;
+      C->sign = A->sign ^ B->sign;
+      fp_clamp(C);
+      COMBA_FINI;
+      break;
+
+   case 2:
+      memcpy(at, A->dp, 2 * sizeof(fp_digit));
+      memcpy(at+2, B->dp, 2 * sizeof(fp_digit));
+      COMBA_START;
+
+      COMBA_CLEAR;
+      /* 0 */
+      MULADD(at[0], at[2]); 
+      COMBA_STORE(C->dp[0]);
+      /* 1 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[3]);       MULADD(at[1], at[2]); 
+      COMBA_STORE(C->dp[1]);
+      /* 2 */
+      COMBA_FORWARD;
+      MULADD(at[1], at[3]); 
+      COMBA_STORE(C->dp[2]);
+      COMBA_STORE2(C->dp[3]);
+      C->used = 4;
+      C->sign = A->sign ^ B->sign;
+      fp_clamp(C);
+      COMBA_FINI;
+      break;
+
+   case 3:
+      memcpy(at, A->dp, 3 * sizeof(fp_digit));
+      memcpy(at+3, B->dp, 3 * sizeof(fp_digit));
+      COMBA_START;
+
+      COMBA_CLEAR;
+      /* 0 */
+      MULADD(at[0], at[3]); 
+      COMBA_STORE(C->dp[0]);
+      /* 1 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[4]);       MULADD(at[1], at[3]); 
+      COMBA_STORE(C->dp[1]);
+      /* 2 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[5]);       MULADD(at[1], at[4]);       MULADD(at[2], at[3]); 
+      COMBA_STORE(C->dp[2]);
+      /* 3 */
+      COMBA_FORWARD;
+      MULADD(at[1], at[5]);       MULADD(at[2], at[4]); 
+      COMBA_STORE(C->dp[3]);
+      /* 4 */
+      COMBA_FORWARD;
+      MULADD(at[2], at[5]); 
+      COMBA_STORE(C->dp[4]);
+      COMBA_STORE2(C->dp[5]);
+      C->used = 6;
+      C->sign = A->sign ^ B->sign;
+      fp_clamp(C);
+      COMBA_FINI;
+      break;
+
+   case 4:
+      memcpy(at, A->dp, 4 * sizeof(fp_digit));
+      memcpy(at+4, B->dp, 4 * sizeof(fp_digit));
+      COMBA_START;
+
+      COMBA_CLEAR;
+      /* 0 */
+      MULADD(at[0], at[4]); 
+      COMBA_STORE(C->dp[0]);
+      /* 1 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[5]);       MULADD(at[1], at[4]); 
+      COMBA_STORE(C->dp[1]);
+      /* 2 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[6]);       MULADD(at[1], at[5]);       MULADD(at[2], at[4]); 
+      COMBA_STORE(C->dp[2]);
+      /* 3 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[7]);       MULADD(at[1], at[6]);       MULADD(at[2], at[5]);       MULADD(at[3], at[4]); 
+      COMBA_STORE(C->dp[3]);
+      /* 4 */
+      COMBA_FORWARD;
+      MULADD(at[1], at[7]);       MULADD(at[2], at[6]);       MULADD(at[3], at[5]); 
+      COMBA_STORE(C->dp[4]);
+      /* 5 */
+      COMBA_FORWARD;
+      MULADD(at[2], at[7]);       MULADD(at[3], at[6]); 
+      COMBA_STORE(C->dp[5]);
+      /* 6 */
+      COMBA_FORWARD;
+      MULADD(at[3], at[7]); 
+      COMBA_STORE(C->dp[6]);
+      COMBA_STORE2(C->dp[7]);
+      C->used = 8;
+      C->sign = A->sign ^ B->sign;
+      fp_clamp(C);
+      COMBA_FINI;
+      break;
+
+   case 5:
+      memcpy(at, A->dp, 5 * sizeof(fp_digit));
+      memcpy(at+5, B->dp, 5 * sizeof(fp_digit));
+      COMBA_START;
+
+      COMBA_CLEAR;
+      /* 0 */
+      MULADD(at[0], at[5]); 
+      COMBA_STORE(C->dp[0]);
+      /* 1 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[6]);       MULADD(at[1], at[5]); 
+      COMBA_STORE(C->dp[1]);
+      /* 2 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[7]);       MULADD(at[1], at[6]);       MULADD(at[2], at[5]); 
+      COMBA_STORE(C->dp[2]);
+      /* 3 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[8]);       MULADD(at[1], at[7]);       MULADD(at[2], at[6]);       MULADD(at[3], at[5]); 
+      COMBA_STORE(C->dp[3]);
+      /* 4 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[9]);       MULADD(at[1], at[8]);       MULADD(at[2], at[7]);       MULADD(at[3], at[6]);       MULADD(at[4], at[5]); 
+      COMBA_STORE(C->dp[4]);
+      /* 5 */
+      COMBA_FORWARD;
+      MULADD(at[1], at[9]);       MULADD(at[2], at[8]);       MULADD(at[3], at[7]);       MULADD(at[4], at[6]); 
+      COMBA_STORE(C->dp[5]);
+      /* 6 */
+      COMBA_FORWARD;
+      MULADD(at[2], at[9]);       MULADD(at[3], at[8]);       MULADD(at[4], at[7]); 
+      COMBA_STORE(C->dp[6]);
+      /* 7 */
+      COMBA_FORWARD;
+      MULADD(at[3], at[9]);       MULADD(at[4], at[8]); 
+      COMBA_STORE(C->dp[7]);
+      /* 8 */
+      COMBA_FORWARD;
+      MULADD(at[4], at[9]); 
+      COMBA_STORE(C->dp[8]);
+      COMBA_STORE2(C->dp[9]);
+      C->used = 10;
+      C->sign = A->sign ^ B->sign;
+      fp_clamp(C);
+      COMBA_FINI;
+      break;
+
+   case 6:
+      memcpy(at, A->dp, 6 * sizeof(fp_digit));
+      memcpy(at+6, B->dp, 6 * sizeof(fp_digit));
+      COMBA_START;
+
+      COMBA_CLEAR;
+      /* 0 */
+      MULADD(at[0], at[6]); 
+      COMBA_STORE(C->dp[0]);
+      /* 1 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[7]);       MULADD(at[1], at[6]); 
+      COMBA_STORE(C->dp[1]);
+      /* 2 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[8]);       MULADD(at[1], at[7]);       MULADD(at[2], at[6]); 
+      COMBA_STORE(C->dp[2]);
+      /* 3 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[9]);       MULADD(at[1], at[8]);       MULADD(at[2], at[7]);       MULADD(at[3], at[6]); 
+      COMBA_STORE(C->dp[3]);
+      /* 4 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[10]);       MULADD(at[1], at[9]);       MULADD(at[2], at[8]);       MULADD(at[3], at[7]);       MULADD(at[4], at[6]); 
+      COMBA_STORE(C->dp[4]);
+      /* 5 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[11]);       MULADD(at[1], at[10]);       MULADD(at[2], at[9]);       MULADD(at[3], at[8]);       MULADD(at[4], at[7]);       MULADD(at[5], at[6]); 
+      COMBA_STORE(C->dp[5]);
+      /* 6 */
+      COMBA_FORWARD;
+      MULADD(at[1], at[11]);       MULADD(at[2], at[10]);       MULADD(at[3], at[9]);       MULADD(at[4], at[8]);       MULADD(at[5], at[7]); 
+      COMBA_STORE(C->dp[6]);
+      /* 7 */
+      COMBA_FORWARD;
+      MULADD(at[2], at[11]);       MULADD(at[3], at[10]);       MULADD(at[4], at[9]);       MULADD(at[5], at[8]); 
+      COMBA_STORE(C->dp[7]);
+      /* 8 */
+      COMBA_FORWARD;
+      MULADD(at[3], at[11]);       MULADD(at[4], at[10]);       MULADD(at[5], at[9]); 
+      COMBA_STORE(C->dp[8]);
+      /* 9 */
+      COMBA_FORWARD;
+      MULADD(at[4], at[11]);       MULADD(at[5], at[10]); 
+      COMBA_STORE(C->dp[9]);
+      /* 10 */
+      COMBA_FORWARD;
+      MULADD(at[5], at[11]); 
+      COMBA_STORE(C->dp[10]);
+      COMBA_STORE2(C->dp[11]);
+      C->used = 12;
+      C->sign = A->sign ^ B->sign;
+      fp_clamp(C);
+      COMBA_FINI;
+      break;
+
+   case 7:
+      memcpy(at, A->dp, 7 * sizeof(fp_digit));
+      memcpy(at+7, B->dp, 7 * sizeof(fp_digit));
+      COMBA_START;
+
+      COMBA_CLEAR;
+      /* 0 */
+      MULADD(at[0], at[7]); 
+      COMBA_STORE(C->dp[0]);
+      /* 1 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[8]);       MULADD(at[1], at[7]); 
+      COMBA_STORE(C->dp[1]);
+      /* 2 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[9]);       MULADD(at[1], at[8]);       MULADD(at[2], at[7]); 
+      COMBA_STORE(C->dp[2]);
+      /* 3 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[10]);       MULADD(at[1], at[9]);       MULADD(at[2], at[8]);       MULADD(at[3], at[7]); 
+      COMBA_STORE(C->dp[3]);
+      /* 4 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[11]);       MULADD(at[1], at[10]);       MULADD(at[2], at[9]);       MULADD(at[3], at[8]);       MULADD(at[4], at[7]); 
+      COMBA_STORE(C->dp[4]);
+      /* 5 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[12]);       MULADD(at[1], at[11]);       MULADD(at[2], at[10]);       MULADD(at[3], at[9]);       MULADD(at[4], at[8]);       MULADD(at[5], at[7]); 
+      COMBA_STORE(C->dp[5]);
+      /* 6 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[13]);       MULADD(at[1], at[12]);       MULADD(at[2], at[11]);       MULADD(at[3], at[10]);       MULADD(at[4], at[9]);       MULADD(at[5], at[8]);       MULADD(at[6], at[7]); 
+      COMBA_STORE(C->dp[6]);
+      /* 7 */
+      COMBA_FORWARD;
+      MULADD(at[1], at[13]);       MULADD(at[2], at[12]);       MULADD(at[3], at[11]);       MULADD(at[4], at[10]);       MULADD(at[5], at[9]);       MULADD(at[6], at[8]); 
+      COMBA_STORE(C->dp[7]);
+      /* 8 */
+      COMBA_FORWARD;
+      MULADD(at[2], at[13]);       MULADD(at[3], at[12]);       MULADD(at[4], at[11]);       MULADD(at[5], at[10]);       MULADD(at[6], at[9]); 
+      COMBA_STORE(C->dp[8]);
+      /* 9 */
+      COMBA_FORWARD;
+      MULADD(at[3], at[13]);       MULADD(at[4], at[12]);       MULADD(at[5], at[11]);       MULADD(at[6], at[10]); 
+      COMBA_STORE(C->dp[9]);
+      /* 10 */
+      COMBA_FORWARD;
+      MULADD(at[4], at[13]);       MULADD(at[5], at[12]);       MULADD(at[6], at[11]); 
+      COMBA_STORE(C->dp[10]);
+      /* 11 */
+      COMBA_FORWARD;
+      MULADD(at[5], at[13]);       MULADD(at[6], at[12]); 
+      COMBA_STORE(C->dp[11]);
+      /* 12 */
+      COMBA_FORWARD;
+      MULADD(at[6], at[13]); 
+      COMBA_STORE(C->dp[12]);
+      COMBA_STORE2(C->dp[13]);
+      C->used = 14;
+      C->sign = A->sign ^ B->sign;
+      fp_clamp(C);
+      COMBA_FINI;
+      break;
+
+   case 8:
+      memcpy(at, A->dp, 8 * sizeof(fp_digit));
+      memcpy(at+8, B->dp, 8 * sizeof(fp_digit));
+      COMBA_START;
+
+      COMBA_CLEAR;
+      /* 0 */
+      MULADD(at[0], at[8]); 
+      COMBA_STORE(C->dp[0]);
+      /* 1 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[9]);       MULADD(at[1], at[8]); 
+      COMBA_STORE(C->dp[1]);
+      /* 2 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[10]);       MULADD(at[1], at[9]);       MULADD(at[2], at[8]); 
+      COMBA_STORE(C->dp[2]);
+      /* 3 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[11]);       MULADD(at[1], at[10]);       MULADD(at[2], at[9]);       MULADD(at[3], at[8]); 
+      COMBA_STORE(C->dp[3]);
+      /* 4 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[12]);       MULADD(at[1], at[11]);       MULADD(at[2], at[10]);       MULADD(at[3], at[9]);       MULADD(at[4], at[8]); 
+      COMBA_STORE(C->dp[4]);
+      /* 5 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[13]);       MULADD(at[1], at[12]);       MULADD(at[2], at[11]);       MULADD(at[3], at[10]);       MULADD(at[4], at[9]);       MULADD(at[5], at[8]); 
+      COMBA_STORE(C->dp[5]);
+      /* 6 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[14]);       MULADD(at[1], at[13]);       MULADD(at[2], at[12]);       MULADD(at[3], at[11]);       MULADD(at[4], at[10]);       MULADD(at[5], at[9]);       MULADD(at[6], at[8]); 
+      COMBA_STORE(C->dp[6]);
+      /* 7 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[15]);       MULADD(at[1], at[14]);       MULADD(at[2], at[13]);       MULADD(at[3], at[12]);       MULADD(at[4], at[11]);       MULADD(at[5], at[10]);       MULADD(at[6], at[9]);       MULADD(at[7], at[8]); 
+      COMBA_STORE(C->dp[7]);
+      /* 8 */
+      COMBA_FORWARD;
+      MULADD(at[1], at[15]);       MULADD(at[2], at[14]);       MULADD(at[3], at[13]);       MULADD(at[4], at[12]);       MULADD(at[5], at[11]);       MULADD(at[6], at[10]);       MULADD(at[7], at[9]); 
+      COMBA_STORE(C->dp[8]);
+      /* 9 */
+      COMBA_FORWARD;
+      MULADD(at[2], at[15]);       MULADD(at[3], at[14]);       MULADD(at[4], at[13]);       MULADD(at[5], at[12]);       MULADD(at[6], at[11]);       MULADD(at[7], at[10]); 
+      COMBA_STORE(C->dp[9]);
+      /* 10 */
+      COMBA_FORWARD;
+      MULADD(at[3], at[15]);       MULADD(at[4], at[14]);       MULADD(at[5], at[13]);       MULADD(at[6], at[12]);       MULADD(at[7], at[11]); 
+      COMBA_STORE(C->dp[10]);
+      /* 11 */
+      COMBA_FORWARD;
+      MULADD(at[4], at[15]);       MULADD(at[5], at[14]);       MULADD(at[6], at[13]);       MULADD(at[7], at[12]); 
+      COMBA_STORE(C->dp[11]);
+      /* 12 */
+      COMBA_FORWARD;
+      MULADD(at[5], at[15]);       MULADD(at[6], at[14]);       MULADD(at[7], at[13]); 
+      COMBA_STORE(C->dp[12]);
+      /* 13 */
+      COMBA_FORWARD;
+      MULADD(at[6], at[15]);       MULADD(at[7], at[14]); 
+      COMBA_STORE(C->dp[13]);
+      /* 14 */
+      COMBA_FORWARD;
+      MULADD(at[7], at[15]); 
+      COMBA_STORE(C->dp[14]);
+      COMBA_STORE2(C->dp[15]);
+      C->used = 16;
+      C->sign = A->sign ^ B->sign;
+      fp_clamp(C);
+      COMBA_FINI;
+      break;
+
+   case 9:
+      memcpy(at, A->dp, 9 * sizeof(fp_digit));
+      memcpy(at+9, B->dp, 9 * sizeof(fp_digit));
+      COMBA_START;
+
+      COMBA_CLEAR;
+      /* 0 */
+      MULADD(at[0], at[9]); 
+      COMBA_STORE(C->dp[0]);
+      /* 1 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[10]);       MULADD(at[1], at[9]); 
+      COMBA_STORE(C->dp[1]);
+      /* 2 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[11]);       MULADD(at[1], at[10]);       MULADD(at[2], at[9]); 
+      COMBA_STORE(C->dp[2]);
+      /* 3 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[12]);       MULADD(at[1], at[11]);       MULADD(at[2], at[10]);       MULADD(at[3], at[9]); 
+      COMBA_STORE(C->dp[3]);
+      /* 4 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[13]);       MULADD(at[1], at[12]);       MULADD(at[2], at[11]);       MULADD(at[3], at[10]);       MULADD(at[4], at[9]); 
+      COMBA_STORE(C->dp[4]);
+      /* 5 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[14]);       MULADD(at[1], at[13]);       MULADD(at[2], at[12]);       MULADD(at[3], at[11]);       MULADD(at[4], at[10]);       MULADD(at[5], at[9]); 
+      COMBA_STORE(C->dp[5]);
+      /* 6 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[15]);       MULADD(at[1], at[14]);       MULADD(at[2], at[13]);       MULADD(at[3], at[12]);       MULADD(at[4], at[11]);       MULADD(at[5], at[10]);       MULADD(at[6], at[9]); 
+      COMBA_STORE(C->dp[6]);
+      /* 7 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[16]);       MULADD(at[1], at[15]);       MULADD(at[2], at[14]);       MULADD(at[3], at[13]);       MULADD(at[4], at[12]);       MULADD(at[5], at[11]);       MULADD(at[6], at[10]);       MULADD(at[7], at[9]); 
+      COMBA_STORE(C->dp[7]);
+      /* 8 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[17]);       MULADD(at[1], at[16]);       MULADD(at[2], at[15]);       MULADD(at[3], at[14]);       MULADD(at[4], at[13]);       MULADD(at[5], at[12]);       MULADD(at[6], at[11]);       MULADD(at[7], at[10]);       MULADD(at[8], at[9]); 
+      COMBA_STORE(C->dp[8]);
+      /* 9 */
+      COMBA_FORWARD;
+      MULADD(at[1], at[17]);       MULADD(at[2], at[16]);       MULADD(at[3], at[15]);       MULADD(at[4], at[14]);       MULADD(at[5], at[13]);       MULADD(at[6], at[12]);       MULADD(at[7], at[11]);       MULADD(at[8], at[10]); 
+      COMBA_STORE(C->dp[9]);
+      /* 10 */
+      COMBA_FORWARD;
+      MULADD(at[2], at[17]);       MULADD(at[3], at[16]);       MULADD(at[4], at[15]);       MULADD(at[5], at[14]);       MULADD(at[6], at[13]);       MULADD(at[7], at[12]);       MULADD(at[8], at[11]); 
+      COMBA_STORE(C->dp[10]);
+      /* 11 */
+      COMBA_FORWARD;
+      MULADD(at[3], at[17]);       MULADD(at[4], at[16]);       MULADD(at[5], at[15]);       MULADD(at[6], at[14]);       MULADD(at[7], at[13]);       MULADD(at[8], at[12]); 
+      COMBA_STORE(C->dp[11]);
+      /* 12 */
+      COMBA_FORWARD;
+      MULADD(at[4], at[17]);       MULADD(at[5], at[16]);       MULADD(at[6], at[15]);       MULADD(at[7], at[14]);       MULADD(at[8], at[13]); 
+      COMBA_STORE(C->dp[12]);
+      /* 13 */
+      COMBA_FORWARD;
+      MULADD(at[5], at[17]);       MULADD(at[6], at[16]);       MULADD(at[7], at[15]);       MULADD(at[8], at[14]); 
+      COMBA_STORE(C->dp[13]);
+      /* 14 */
+      COMBA_FORWARD;
+      MULADD(at[6], at[17]);       MULADD(at[7], at[16]);       MULADD(at[8], at[15]); 
+      COMBA_STORE(C->dp[14]);
+      /* 15 */
+      COMBA_FORWARD;
+      MULADD(at[7], at[17]);       MULADD(at[8], at[16]); 
+      COMBA_STORE(C->dp[15]);
+      /* 16 */
+      COMBA_FORWARD;
+      MULADD(at[8], at[17]); 
+      COMBA_STORE(C->dp[16]);
+      COMBA_STORE2(C->dp[17]);
+      C->used = 18;
+      C->sign = A->sign ^ B->sign;
+      fp_clamp(C);
+      COMBA_FINI;
+      break;
+
+   case 10:
+      memcpy(at, A->dp, 10 * sizeof(fp_digit));
+      memcpy(at+10, B->dp, 10 * sizeof(fp_digit));
+      COMBA_START;
+
+      COMBA_CLEAR;
+      /* 0 */
+      MULADD(at[0], at[10]); 
+      COMBA_STORE(C->dp[0]);
+      /* 1 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[11]);       MULADD(at[1], at[10]); 
+      COMBA_STORE(C->dp[1]);
+      /* 2 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[12]);       MULADD(at[1], at[11]);       MULADD(at[2], at[10]); 
+      COMBA_STORE(C->dp[2]);
+      /* 3 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[13]);       MULADD(at[1], at[12]);       MULADD(at[2], at[11]);       MULADD(at[3], at[10]); 
+      COMBA_STORE(C->dp[3]);
+      /* 4 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[14]);       MULADD(at[1], at[13]);       MULADD(at[2], at[12]);       MULADD(at[3], at[11]);       MULADD(at[4], at[10]); 
+      COMBA_STORE(C->dp[4]);
+      /* 5 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[15]);       MULADD(at[1], at[14]);       MULADD(at[2], at[13]);       MULADD(at[3], at[12]);       MULADD(at[4], at[11]);       MULADD(at[5], at[10]); 
+      COMBA_STORE(C->dp[5]);
+      /* 6 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[16]);       MULADD(at[1], at[15]);       MULADD(at[2], at[14]);       MULADD(at[3], at[13]);       MULADD(at[4], at[12]);       MULADD(at[5], at[11]);       MULADD(at[6], at[10]); 
+      COMBA_STORE(C->dp[6]);
+      /* 7 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[17]);       MULADD(at[1], at[16]);       MULADD(at[2], at[15]);       MULADD(at[3], at[14]);       MULADD(at[4], at[13]);       MULADD(at[5], at[12]);       MULADD(at[6], at[11]);       MULADD(at[7], at[10]); 
+      COMBA_STORE(C->dp[7]);
+      /* 8 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[18]);       MULADD(at[1], at[17]);       MULADD(at[2], at[16]);       MULADD(at[3], at[15]);       MULADD(at[4], at[14]);       MULADD(at[5], at[13]);       MULADD(at[6], at[12]);       MULADD(at[7], at[11]);       MULADD(at[8], at[10]); 
+      COMBA_STORE(C->dp[8]);
+      /* 9 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[19]);       MULADD(at[1], at[18]);       MULADD(at[2], at[17]);       MULADD(at[3], at[16]);       MULADD(at[4], at[15]);       MULADD(at[5], at[14]);       MULADD(at[6], at[13]);       MULADD(at[7], at[12]);       MULADD(at[8], at[11]);       MULADD(at[9], at[10]); 
+      COMBA_STORE(C->dp[9]);
+      /* 10 */
+      COMBA_FORWARD;
+      MULADD(at[1], at[19]);       MULADD(at[2], at[18]);       MULADD(at[3], at[17]);       MULADD(at[4], at[16]);       MULADD(at[5], at[15]);       MULADD(at[6], at[14]);       MULADD(at[7], at[13]);       MULADD(at[8], at[12]);       MULADD(at[9], at[11]); 
+      COMBA_STORE(C->dp[10]);
+      /* 11 */
+      COMBA_FORWARD;
+      MULADD(at[2], at[19]);       MULADD(at[3], at[18]);       MULADD(at[4], at[17]);       MULADD(at[5], at[16]);       MULADD(at[6], at[15]);       MULADD(at[7], at[14]);       MULADD(at[8], at[13]);       MULADD(at[9], at[12]); 
+      COMBA_STORE(C->dp[11]);
+      /* 12 */
+      COMBA_FORWARD;
+      MULADD(at[3], at[19]);       MULADD(at[4], at[18]);       MULADD(at[5], at[17]);       MULADD(at[6], at[16]);       MULADD(at[7], at[15]);       MULADD(at[8], at[14]);       MULADD(at[9], at[13]); 
+      COMBA_STORE(C->dp[12]);
+      /* 13 */
+      COMBA_FORWARD;
+      MULADD(at[4], at[19]);       MULADD(at[5], at[18]);       MULADD(at[6], at[17]);       MULADD(at[7], at[16]);       MULADD(at[8], at[15]);       MULADD(at[9], at[14]); 
+      COMBA_STORE(C->dp[13]);
+      /* 14 */
+      COMBA_FORWARD;
+      MULADD(at[5], at[19]);       MULADD(at[6], at[18]);       MULADD(at[7], at[17]);       MULADD(at[8], at[16]);       MULADD(at[9], at[15]); 
+      COMBA_STORE(C->dp[14]);
+      /* 15 */
+      COMBA_FORWARD;
+      MULADD(at[6], at[19]);       MULADD(at[7], at[18]);       MULADD(at[8], at[17]);       MULADD(at[9], at[16]); 
+      COMBA_STORE(C->dp[15]);
+      /* 16 */
+      COMBA_FORWARD;
+      MULADD(at[7], at[19]);       MULADD(at[8], at[18]);       MULADD(at[9], at[17]); 
+      COMBA_STORE(C->dp[16]);
+      /* 17 */
+      COMBA_FORWARD;
+      MULADD(at[8], at[19]);       MULADD(at[9], at[18]); 
+      COMBA_STORE(C->dp[17]);
+      /* 18 */
+      COMBA_FORWARD;
+      MULADD(at[9], at[19]); 
+      COMBA_STORE(C->dp[18]);
+      COMBA_STORE2(C->dp[19]);
+      C->used = 20;
+      C->sign = A->sign ^ B->sign;
+      fp_clamp(C);
+      COMBA_FINI;
+      break;
+
+   case 11:
+      memcpy(at, A->dp, 11 * sizeof(fp_digit));
+      memcpy(at+11, B->dp, 11 * sizeof(fp_digit));
+      COMBA_START;
+
+      COMBA_CLEAR;
+      /* 0 */
+      MULADD(at[0], at[11]); 
+      COMBA_STORE(C->dp[0]);
+      /* 1 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[12]);       MULADD(at[1], at[11]); 
+      COMBA_STORE(C->dp[1]);
+      /* 2 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[13]);       MULADD(at[1], at[12]);       MULADD(at[2], at[11]); 
+      COMBA_STORE(C->dp[2]);
+      /* 3 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[14]);       MULADD(at[1], at[13]);       MULADD(at[2], at[12]);       MULADD(at[3], at[11]); 
+      COMBA_STORE(C->dp[3]);
+      /* 4 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[15]);       MULADD(at[1], at[14]);       MULADD(at[2], at[13]);       MULADD(at[3], at[12]);       MULADD(at[4], at[11]); 
+      COMBA_STORE(C->dp[4]);
+      /* 5 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[16]);       MULADD(at[1], at[15]);       MULADD(at[2], at[14]);       MULADD(at[3], at[13]);       MULADD(at[4], at[12]);       MULADD(at[5], at[11]); 
+      COMBA_STORE(C->dp[5]);
+      /* 6 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[17]);       MULADD(at[1], at[16]);       MULADD(at[2], at[15]);       MULADD(at[3], at[14]);       MULADD(at[4], at[13]);       MULADD(at[5], at[12]);       MULADD(at[6], at[11]); 
+      COMBA_STORE(C->dp[6]);
+      /* 7 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[18]);       MULADD(at[1], at[17]);       MULADD(at[2], at[16]);       MULADD(at[3], at[15]);       MULADD(at[4], at[14]);       MULADD(at[5], at[13]);       MULADD(at[6], at[12]);       MULADD(at[7], at[11]); 
+      COMBA_STORE(C->dp[7]);
+      /* 8 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[19]);       MULADD(at[1], at[18]);       MULADD(at[2], at[17]);       MULADD(at[3], at[16]);       MULADD(at[4], at[15]);       MULADD(at[5], at[14]);       MULADD(at[6], at[13]);       MULADD(at[7], at[12]);       MULADD(at[8], at[11]); 
+      COMBA_STORE(C->dp[8]);
+      /* 9 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[20]);       MULADD(at[1], at[19]);       MULADD(at[2], at[18]);       MULADD(at[3], at[17]);       MULADD(at[4], at[16]);       MULADD(at[5], at[15]);       MULADD(at[6], at[14]);       MULADD(at[7], at[13]);       MULADD(at[8], at[12]);       MULADD(at[9], at[11]); 
+      COMBA_STORE(C->dp[9]);
+      /* 10 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[21]);       MULADD(at[1], at[20]);       MULADD(at[2], at[19]);       MULADD(at[3], at[18]);       MULADD(at[4], at[17]);       MULADD(at[5], at[16]);       MULADD(at[6], at[15]);       MULADD(at[7], at[14]);       MULADD(at[8], at[13]);       MULADD(at[9], at[12]);       MULADD(at[10], at[11]); 
+      COMBA_STORE(C->dp[10]);
+      /* 11 */
+      COMBA_FORWARD;
+      MULADD(at[1], at[21]);       MULADD(at[2], at[20]);       MULADD(at[3], at[19]);       MULADD(at[4], at[18]);       MULADD(at[5], at[17]);       MULADD(at[6], at[16]);       MULADD(at[7], at[15]);       MULADD(at[8], at[14]);       MULADD(at[9], at[13]);       MULADD(at[10], at[12]); 
+      COMBA_STORE(C->dp[11]);
+      /* 12 */
+      COMBA_FORWARD;
+      MULADD(at[2], at[21]);       MULADD(at[3], at[20]);       MULADD(at[4], at[19]);       MULADD(at[5], at[18]);       MULADD(at[6], at[17]);       MULADD(at[7], at[16]);       MULADD(at[8], at[15]);       MULADD(at[9], at[14]);       MULADD(at[10], at[13]); 
+      COMBA_STORE(C->dp[12]);
+      /* 13 */
+      COMBA_FORWARD;
+      MULADD(at[3], at[21]);       MULADD(at[4], at[20]);       MULADD(at[5], at[19]);       MULADD(at[6], at[18]);       MULADD(at[7], at[17]);       MULADD(at[8], at[16]);       MULADD(at[9], at[15]);       MULADD(at[10], at[14]); 
+      COMBA_STORE(C->dp[13]);
+      /* 14 */
+      COMBA_FORWARD;
+      MULADD(at[4], at[21]);       MULADD(at[5], at[20]);       MULADD(at[6], at[19]);       MULADD(at[7], at[18]);       MULADD(at[8], at[17]);       MULADD(at[9], at[16]);       MULADD(at[10], at[15]); 
+      COMBA_STORE(C->dp[14]);
+      /* 15 */
+      COMBA_FORWARD;
+      MULADD(at[5], at[21]);       MULADD(at[6], at[20]);       MULADD(at[7], at[19]);       MULADD(at[8], at[18]);       MULADD(at[9], at[17]);       MULADD(at[10], at[16]); 
+      COMBA_STORE(C->dp[15]);
+      /* 16 */
+      COMBA_FORWARD;
+      MULADD(at[6], at[21]);       MULADD(at[7], at[20]);       MULADD(at[8], at[19]);       MULADD(at[9], at[18]);       MULADD(at[10], at[17]); 
+      COMBA_STORE(C->dp[16]);
+      /* 17 */
+      COMBA_FORWARD;
+      MULADD(at[7], at[21]);       MULADD(at[8], at[20]);       MULADD(at[9], at[19]);       MULADD(at[10], at[18]); 
+      COMBA_STORE(C->dp[17]);
+      /* 18 */
+      COMBA_FORWARD;
+      MULADD(at[8], at[21]);       MULADD(at[9], at[20]);       MULADD(at[10], at[19]); 
+      COMBA_STORE(C->dp[18]);
+      /* 19 */
+      COMBA_FORWARD;
+      MULADD(at[9], at[21]);       MULADD(at[10], at[20]); 
+      COMBA_STORE(C->dp[19]);
+      /* 20 */
+      COMBA_FORWARD;
+      MULADD(at[10], at[21]); 
+      COMBA_STORE(C->dp[20]);
+      COMBA_STORE2(C->dp[21]);
+      C->used = 22;
+      C->sign = A->sign ^ B->sign;
+      fp_clamp(C);
+      COMBA_FINI;
+      break;
+
+   case 12:
+      memcpy(at, A->dp, 12 * sizeof(fp_digit));
+      memcpy(at+12, B->dp, 12 * sizeof(fp_digit));
+      COMBA_START;
+
+      COMBA_CLEAR;
+      /* 0 */
+      MULADD(at[0], at[12]); 
+      COMBA_STORE(C->dp[0]);
+      /* 1 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[13]);       MULADD(at[1], at[12]); 
+      COMBA_STORE(C->dp[1]);
+      /* 2 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[14]);       MULADD(at[1], at[13]);       MULADD(at[2], at[12]); 
+      COMBA_STORE(C->dp[2]);
+      /* 3 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[15]);       MULADD(at[1], at[14]);       MULADD(at[2], at[13]);       MULADD(at[3], at[12]); 
+      COMBA_STORE(C->dp[3]);
+      /* 4 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[16]);       MULADD(at[1], at[15]);       MULADD(at[2], at[14]);       MULADD(at[3], at[13]);       MULADD(at[4], at[12]); 
+      COMBA_STORE(C->dp[4]);
+      /* 5 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[17]);       MULADD(at[1], at[16]);       MULADD(at[2], at[15]);       MULADD(at[3], at[14]);       MULADD(at[4], at[13]);       MULADD(at[5], at[12]); 
+      COMBA_STORE(C->dp[5]);
+      /* 6 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[18]);       MULADD(at[1], at[17]);       MULADD(at[2], at[16]);       MULADD(at[3], at[15]);       MULADD(at[4], at[14]);       MULADD(at[5], at[13]);       MULADD(at[6], at[12]); 
+      COMBA_STORE(C->dp[6]);
+      /* 7 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[19]);       MULADD(at[1], at[18]);       MULADD(at[2], at[17]);       MULADD(at[3], at[16]);       MULADD(at[4], at[15]);       MULADD(at[5], at[14]);       MULADD(at[6], at[13]);       MULADD(at[7], at[12]); 
+      COMBA_STORE(C->dp[7]);
+      /* 8 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[20]);       MULADD(at[1], at[19]);       MULADD(at[2], at[18]);       MULADD(at[3], at[17]);       MULADD(at[4], at[16]);       MULADD(at[5], at[15]);       MULADD(at[6], at[14]);       MULADD(at[7], at[13]);       MULADD(at[8], at[12]); 
+      COMBA_STORE(C->dp[8]);
+      /* 9 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[21]);       MULADD(at[1], at[20]);       MULADD(at[2], at[19]);       MULADD(at[3], at[18]);       MULADD(at[4], at[17]);       MULADD(at[5], at[16]);       MULADD(at[6], at[15]);       MULADD(at[7], at[14]);       MULADD(at[8], at[13]);       MULADD(at[9], at[12]); 
+      COMBA_STORE(C->dp[9]);
+      /* 10 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[22]);       MULADD(at[1], at[21]);       MULADD(at[2], at[20]);       MULADD(at[3], at[19]);       MULADD(at[4], at[18]);       MULADD(at[5], at[17]);       MULADD(at[6], at[16]);       MULADD(at[7], at[15]);       MULADD(at[8], at[14]);       MULADD(at[9], at[13]);       MULADD(at[10], at[12]); 
+      COMBA_STORE(C->dp[10]);
+      /* 11 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[23]);       MULADD(at[1], at[22]);       MULADD(at[2], at[21]);       MULADD(at[3], at[20]);       MULADD(at[4], at[19]);       MULADD(at[5], at[18]);       MULADD(at[6], at[17]);       MULADD(at[7], at[16]);       MULADD(at[8], at[15]);       MULADD(at[9], at[14]);       MULADD(at[10], at[13]);       MULADD(at[11], at[12]); 
+      COMBA_STORE(C->dp[11]);
+      /* 12 */
+      COMBA_FORWARD;
+      MULADD(at[1], at[23]);       MULADD(at[2], at[22]);       MULADD(at[3], at[21]);       MULADD(at[4], at[20]);       MULADD(at[5], at[19]);       MULADD(at[6], at[18]);       MULADD(at[7], at[17]);       MULADD(at[8], at[16]);       MULADD(at[9], at[15]);       MULADD(at[10], at[14]);       MULADD(at[11], at[13]); 
+      COMBA_STORE(C->dp[12]);
+      /* 13 */
+      COMBA_FORWARD;
+      MULADD(at[2], at[23]);       MULADD(at[3], at[22]);       MULADD(at[4], at[21]);       MULADD(at[5], at[20]);       MULADD(at[6], at[19]);       MULADD(at[7], at[18]);       MULADD(at[8], at[17]);       MULADD(at[9], at[16]);       MULADD(at[10], at[15]);       MULADD(at[11], at[14]); 
+      COMBA_STORE(C->dp[13]);
+      /* 14 */
+      COMBA_FORWARD;
+      MULADD(at[3], at[23]);       MULADD(at[4], at[22]);       MULADD(at[5], at[21]);       MULADD(at[6], at[20]);       MULADD(at[7], at[19]);       MULADD(at[8], at[18]);       MULADD(at[9], at[17]);       MULADD(at[10], at[16]);       MULADD(at[11], at[15]); 
+      COMBA_STORE(C->dp[14]);
+      /* 15 */
+      COMBA_FORWARD;
+      MULADD(at[4], at[23]);       MULADD(at[5], at[22]);       MULADD(at[6], at[21]);       MULADD(at[7], at[20]);       MULADD(at[8], at[19]);       MULADD(at[9], at[18]);       MULADD(at[10], at[17]);       MULADD(at[11], at[16]); 
+      COMBA_STORE(C->dp[15]);
+      /* 16 */
+      COMBA_FORWARD;
+      MULADD(at[5], at[23]);       MULADD(at[6], at[22]);       MULADD(at[7], at[21]);       MULADD(at[8], at[20]);       MULADD(at[9], at[19]);       MULADD(at[10], at[18]);       MULADD(at[11], at[17]); 
+      COMBA_STORE(C->dp[16]);
+      /* 17 */
+      COMBA_FORWARD;
+      MULADD(at[6], at[23]);       MULADD(at[7], at[22]);       MULADD(at[8], at[21]);       MULADD(at[9], at[20]);       MULADD(at[10], at[19]);       MULADD(at[11], at[18]); 
+      COMBA_STORE(C->dp[17]);
+      /* 18 */
+      COMBA_FORWARD;
+      MULADD(at[7], at[23]);       MULADD(at[8], at[22]);       MULADD(at[9], at[21]);       MULADD(at[10], at[20]);       MULADD(at[11], at[19]); 
+      COMBA_STORE(C->dp[18]);
+      /* 19 */
+      COMBA_FORWARD;
+      MULADD(at[8], at[23]);       MULADD(at[9], at[22]);       MULADD(at[10], at[21]);       MULADD(at[11], at[20]); 
+      COMBA_STORE(C->dp[19]);
+      /* 20 */
+      COMBA_FORWARD;
+      MULADD(at[9], at[23]);       MULADD(at[10], at[22]);       MULADD(at[11], at[21]); 
+      COMBA_STORE(C->dp[20]);
+      /* 21 */
+      COMBA_FORWARD;
+      MULADD(at[10], at[23]);       MULADD(at[11], at[22]); 
+      COMBA_STORE(C->dp[21]);
+      /* 22 */
+      COMBA_FORWARD;
+      MULADD(at[11], at[23]); 
+      COMBA_STORE(C->dp[22]);
+      COMBA_STORE2(C->dp[23]);
+      C->used = 24;
+      C->sign = A->sign ^ B->sign;
+      fp_clamp(C);
+      COMBA_FINI;
+      break;
+
+   case 13:
+      memcpy(at, A->dp, 13 * sizeof(fp_digit));
+      memcpy(at+13, B->dp, 13 * sizeof(fp_digit));
+      COMBA_START;
+
+      COMBA_CLEAR;
+      /* 0 */
+      MULADD(at[0], at[13]); 
+      COMBA_STORE(C->dp[0]);
+      /* 1 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[14]);       MULADD(at[1], at[13]); 
+      COMBA_STORE(C->dp[1]);
+      /* 2 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[15]);       MULADD(at[1], at[14]);       MULADD(at[2], at[13]); 
+      COMBA_STORE(C->dp[2]);
+      /* 3 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[16]);       MULADD(at[1], at[15]);       MULADD(at[2], at[14]);       MULADD(at[3], at[13]); 
+      COMBA_STORE(C->dp[3]);
+      /* 4 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[17]);       MULADD(at[1], at[16]);       MULADD(at[2], at[15]);       MULADD(at[3], at[14]);       MULADD(at[4], at[13]); 
+      COMBA_STORE(C->dp[4]);
+      /* 5 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[18]);       MULADD(at[1], at[17]);       MULADD(at[2], at[16]);       MULADD(at[3], at[15]);       MULADD(at[4], at[14]);       MULADD(at[5], at[13]); 
+      COMBA_STORE(C->dp[5]);
+      /* 6 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[19]);       MULADD(at[1], at[18]);       MULADD(at[2], at[17]);       MULADD(at[3], at[16]);       MULADD(at[4], at[15]);       MULADD(at[5], at[14]);       MULADD(at[6], at[13]); 
+      COMBA_STORE(C->dp[6]);
+      /* 7 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[20]);       MULADD(at[1], at[19]);       MULADD(at[2], at[18]);       MULADD(at[3], at[17]);       MULADD(at[4], at[16]);       MULADD(at[5], at[15]);       MULADD(at[6], at[14]);       MULADD(at[7], at[13]); 
+      COMBA_STORE(C->dp[7]);
+      /* 8 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[21]);       MULADD(at[1], at[20]);       MULADD(at[2], at[19]);       MULADD(at[3], at[18]);       MULADD(at[4], at[17]);       MULADD(at[5], at[16]);       MULADD(at[6], at[15]);       MULADD(at[7], at[14]);       MULADD(at[8], at[13]); 
+      COMBA_STORE(C->dp[8]);
+      /* 9 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[22]);       MULADD(at[1], at[21]);       MULADD(at[2], at[20]);       MULADD(at[3], at[19]);       MULADD(at[4], at[18]);       MULADD(at[5], at[17]);       MULADD(at[6], at[16]);       MULADD(at[7], at[15]);       MULADD(at[8], at[14]);       MULADD(at[9], at[13]); 
+      COMBA_STORE(C->dp[9]);
+      /* 10 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[23]);       MULADD(at[1], at[22]);       MULADD(at[2], at[21]);       MULADD(at[3], at[20]);       MULADD(at[4], at[19]);       MULADD(at[5], at[18]);       MULADD(at[6], at[17]);       MULADD(at[7], at[16]);       MULADD(at[8], at[15]);       MULADD(at[9], at[14]);       MULADD(at[10], at[13]); 
+      COMBA_STORE(C->dp[10]);
+      /* 11 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[24]);       MULADD(at[1], at[23]);       MULADD(at[2], at[22]);       MULADD(at[3], at[21]);       MULADD(at[4], at[20]);       MULADD(at[5], at[19]);       MULADD(at[6], at[18]);       MULADD(at[7], at[17]);       MULADD(at[8], at[16]);       MULADD(at[9], at[15]);       MULADD(at[10], at[14]);       MULADD(at[11], at[13]); 
+      COMBA_STORE(C->dp[11]);
+      /* 12 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[25]);       MULADD(at[1], at[24]);       MULADD(at[2], at[23]);       MULADD(at[3], at[22]);       MULADD(at[4], at[21]);       MULADD(at[5], at[20]);       MULADD(at[6], at[19]);       MULADD(at[7], at[18]);       MULADD(at[8], at[17]);       MULADD(at[9], at[16]);       MULADD(at[10], at[15]);       MULADD(at[11], at[14]);       MULADD(at[12], at[13]); 
+      COMBA_STORE(C->dp[12]);
+      /* 13 */
+      COMBA_FORWARD;
+      MULADD(at[1], at[25]);       MULADD(at[2], at[24]);       MULADD(at[3], at[23]);       MULADD(at[4], at[22]);       MULADD(at[5], at[21]);       MULADD(at[6], at[20]);       MULADD(at[7], at[19]);       MULADD(at[8], at[18]);       MULADD(at[9], at[17]);       MULADD(at[10], at[16]);       MULADD(at[11], at[15]);       MULADD(at[12], at[14]); 
+      COMBA_STORE(C->dp[13]);
+      /* 14 */
+      COMBA_FORWARD;
+      MULADD(at[2], at[25]);       MULADD(at[3], at[24]);       MULADD(at[4], at[23]);       MULADD(at[5], at[22]);       MULADD(at[6], at[21]);       MULADD(at[7], at[20]);       MULADD(at[8], at[19]);       MULADD(at[9], at[18]);       MULADD(at[10], at[17]);       MULADD(at[11], at[16]);       MULADD(at[12], at[15]); 
+      COMBA_STORE(C->dp[14]);
+      /* 15 */
+      COMBA_FORWARD;
+      MULADD(at[3], at[25]);       MULADD(at[4], at[24]);       MULADD(at[5], at[23]);       MULADD(at[6], at[22]);       MULADD(at[7], at[21]);       MULADD(at[8], at[20]);       MULADD(at[9], at[19]);       MULADD(at[10], at[18]);       MULADD(at[11], at[17]);       MULADD(at[12], at[16]); 
+      COMBA_STORE(C->dp[15]);
+      /* 16 */
+      COMBA_FORWARD;
+      MULADD(at[4], at[25]);       MULADD(at[5], at[24]);       MULADD(at[6], at[23]);       MULADD(at[7], at[22]);       MULADD(at[8], at[21]);       MULADD(at[9], at[20]);       MULADD(at[10], at[19]);       MULADD(at[11], at[18]);       MULADD(at[12], at[17]); 
+      COMBA_STORE(C->dp[16]);
+      /* 17 */
+      COMBA_FORWARD;
+      MULADD(at[5], at[25]);       MULADD(at[6], at[24]);       MULADD(at[7], at[23]);       MULADD(at[8], at[22]);       MULADD(at[9], at[21]);       MULADD(at[10], at[20]);       MULADD(at[11], at[19]);       MULADD(at[12], at[18]); 
+      COMBA_STORE(C->dp[17]);
+      /* 18 */
+      COMBA_FORWARD;
+      MULADD(at[6], at[25]);       MULADD(at[7], at[24]);       MULADD(at[8], at[23]);       MULADD(at[9], at[22]);       MULADD(at[10], at[21]);       MULADD(at[11], at[20]);       MULADD(at[12], at[19]); 
+      COMBA_STORE(C->dp[18]);
+      /* 19 */
+      COMBA_FORWARD;
+      MULADD(at[7], at[25]);       MULADD(at[8], at[24]);       MULADD(at[9], at[23]);       MULADD(at[10], at[22]);       MULADD(at[11], at[21]);       MULADD(at[12], at[20]); 
+      COMBA_STORE(C->dp[19]);
+      /* 20 */
+      COMBA_FORWARD;
+      MULADD(at[8], at[25]);       MULADD(at[9], at[24]);       MULADD(at[10], at[23]);       MULADD(at[11], at[22]);       MULADD(at[12], at[21]); 
+      COMBA_STORE(C->dp[20]);
+      /* 21 */
+      COMBA_FORWARD;
+      MULADD(at[9], at[25]);       MULADD(at[10], at[24]);       MULADD(at[11], at[23]);       MULADD(at[12], at[22]); 
+      COMBA_STORE(C->dp[21]);
+      /* 22 */
+      COMBA_FORWARD;
+      MULADD(at[10], at[25]);       MULADD(at[11], at[24]);       MULADD(at[12], at[23]); 
+      COMBA_STORE(C->dp[22]);
+      /* 23 */
+      COMBA_FORWARD;
+      MULADD(at[11], at[25]);       MULADD(at[12], at[24]); 
+      COMBA_STORE(C->dp[23]);
+      /* 24 */
+      COMBA_FORWARD;
+      MULADD(at[12], at[25]); 
+      COMBA_STORE(C->dp[24]);
+      COMBA_STORE2(C->dp[25]);
+      C->used = 26;
+      C->sign = A->sign ^ B->sign;
+      fp_clamp(C);
+      COMBA_FINI;
+      break;
+
+   case 14:
+      memcpy(at, A->dp, 14 * sizeof(fp_digit));
+      memcpy(at+14, B->dp, 14 * sizeof(fp_digit));
+      COMBA_START;
+
+      COMBA_CLEAR;
+      /* 0 */
+      MULADD(at[0], at[14]); 
+      COMBA_STORE(C->dp[0]);
+      /* 1 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[15]);       MULADD(at[1], at[14]); 
+      COMBA_STORE(C->dp[1]);
+      /* 2 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[16]);       MULADD(at[1], at[15]);       MULADD(at[2], at[14]); 
+      COMBA_STORE(C->dp[2]);
+      /* 3 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[17]);       MULADD(at[1], at[16]);       MULADD(at[2], at[15]);       MULADD(at[3], at[14]); 
+      COMBA_STORE(C->dp[3]);
+      /* 4 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[18]);       MULADD(at[1], at[17]);       MULADD(at[2], at[16]);       MULADD(at[3], at[15]);       MULADD(at[4], at[14]); 
+      COMBA_STORE(C->dp[4]);
+      /* 5 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[19]);       MULADD(at[1], at[18]);       MULADD(at[2], at[17]);       MULADD(at[3], at[16]);       MULADD(at[4], at[15]);       MULADD(at[5], at[14]); 
+      COMBA_STORE(C->dp[5]);
+      /* 6 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[20]);       MULADD(at[1], at[19]);       MULADD(at[2], at[18]);       MULADD(at[3], at[17]);       MULADD(at[4], at[16]);       MULADD(at[5], at[15]);       MULADD(at[6], at[14]); 
+      COMBA_STORE(C->dp[6]);
+      /* 7 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[21]);       MULADD(at[1], at[20]);       MULADD(at[2], at[19]);       MULADD(at[3], at[18]);       MULADD(at[4], at[17]);       MULADD(at[5], at[16]);       MULADD(at[6], at[15]);       MULADD(at[7], at[14]); 
+      COMBA_STORE(C->dp[7]);
+      /* 8 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[22]);       MULADD(at[1], at[21]);       MULADD(at[2], at[20]);       MULADD(at[3], at[19]);       MULADD(at[4], at[18]);       MULADD(at[5], at[17]);       MULADD(at[6], at[16]);       MULADD(at[7], at[15]);       MULADD(at[8], at[14]); 
+      COMBA_STORE(C->dp[8]);
+      /* 9 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[23]);       MULADD(at[1], at[22]);       MULADD(at[2], at[21]);       MULADD(at[3], at[20]);       MULADD(at[4], at[19]);       MULADD(at[5], at[18]);       MULADD(at[6], at[17]);       MULADD(at[7], at[16]);       MULADD(at[8], at[15]);       MULADD(at[9], at[14]); 
+      COMBA_STORE(C->dp[9]);
+      /* 10 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[24]);       MULADD(at[1], at[23]);       MULADD(at[2], at[22]);       MULADD(at[3], at[21]);       MULADD(at[4], at[20]);       MULADD(at[5], at[19]);       MULADD(at[6], at[18]);       MULADD(at[7], at[17]);       MULADD(at[8], at[16]);       MULADD(at[9], at[15]);       MULADD(at[10], at[14]); 
+      COMBA_STORE(C->dp[10]);
+      /* 11 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[25]);       MULADD(at[1], at[24]);       MULADD(at[2], at[23]);       MULADD(at[3], at[22]);       MULADD(at[4], at[21]);       MULADD(at[5], at[20]);       MULADD(at[6], at[19]);       MULADD(at[7], at[18]);       MULADD(at[8], at[17]);       MULADD(at[9], at[16]);       MULADD(at[10], at[15]);       MULADD(at[11], at[14]); 
+      COMBA_STORE(C->dp[11]);
+      /* 12 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[26]);       MULADD(at[1], at[25]);       MULADD(at[2], at[24]);       MULADD(at[3], at[23]);       MULADD(at[4], at[22]);       MULADD(at[5], at[21]);       MULADD(at[6], at[20]);       MULADD(at[7], at[19]);       MULADD(at[8], at[18]);       MULADD(at[9], at[17]);       MULADD(at[10], at[16]);       MULADD(at[11], at[15]);       MULADD(at[12], at[14]); 
+      COMBA_STORE(C->dp[12]);
+      /* 13 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[27]);       MULADD(at[1], at[26]);       MULADD(at[2], at[25]);       MULADD(at[3], at[24]);       MULADD(at[4], at[23]);       MULADD(at[5], at[22]);       MULADD(at[6], at[21]);       MULADD(at[7], at[20]);       MULADD(at[8], at[19]);       MULADD(at[9], at[18]);       MULADD(at[10], at[17]);       MULADD(at[11], at[16]);       MULADD(at[12], at[15]);       MULADD(at[13], at[14]); 
+      COMBA_STORE(C->dp[13]);
+      /* 14 */
+      COMBA_FORWARD;
+      MULADD(at[1], at[27]);       MULADD(at[2], at[26]);       MULADD(at[3], at[25]);       MULADD(at[4], at[24]);       MULADD(at[5], at[23]);       MULADD(at[6], at[22]);       MULADD(at[7], at[21]);       MULADD(at[8], at[20]);       MULADD(at[9], at[19]);       MULADD(at[10], at[18]);       MULADD(at[11], at[17]);       MULADD(at[12], at[16]);       MULADD(at[13], at[15]); 
+      COMBA_STORE(C->dp[14]);
+      /* 15 */
+      COMBA_FORWARD;
+      MULADD(at[2], at[27]);       MULADD(at[3], at[26]);       MULADD(at[4], at[25]);       MULADD(at[5], at[24]);       MULADD(at[6], at[23]);       MULADD(at[7], at[22]);       MULADD(at[8], at[21]);       MULADD(at[9], at[20]);       MULADD(at[10], at[19]);       MULADD(at[11], at[18]);       MULADD(at[12], at[17]);       MULADD(at[13], at[16]); 
+      COMBA_STORE(C->dp[15]);
+      /* 16 */
+      COMBA_FORWARD;
+      MULADD(at[3], at[27]);       MULADD(at[4], at[26]);       MULADD(at[5], at[25]);       MULADD(at[6], at[24]);       MULADD(at[7], at[23]);       MULADD(at[8], at[22]);       MULADD(at[9], at[21]);       MULADD(at[10], at[20]);       MULADD(at[11], at[19]);       MULADD(at[12], at[18]);       MULADD(at[13], at[17]); 
+      COMBA_STORE(C->dp[16]);
+      /* 17 */
+      COMBA_FORWARD;
+      MULADD(at[4], at[27]);       MULADD(at[5], at[26]);       MULADD(at[6], at[25]);       MULADD(at[7], at[24]);       MULADD(at[8], at[23]);       MULADD(at[9], at[22]);       MULADD(at[10], at[21]);       MULADD(at[11], at[20]);       MULADD(at[12], at[19]);       MULADD(at[13], at[18]); 
+      COMBA_STORE(C->dp[17]);
+      /* 18 */
+      COMBA_FORWARD;
+      MULADD(at[5], at[27]);       MULADD(at[6], at[26]);       MULADD(at[7], at[25]);       MULADD(at[8], at[24]);       MULADD(at[9], at[23]);       MULADD(at[10], at[22]);       MULADD(at[11], at[21]);       MULADD(at[12], at[20]);       MULADD(at[13], at[19]); 
+      COMBA_STORE(C->dp[18]);
+      /* 19 */
+      COMBA_FORWARD;
+      MULADD(at[6], at[27]);       MULADD(at[7], at[26]);       MULADD(at[8], at[25]);       MULADD(at[9], at[24]);       MULADD(at[10], at[23]);       MULADD(at[11], at[22]);       MULADD(at[12], at[21]);       MULADD(at[13], at[20]); 
+      COMBA_STORE(C->dp[19]);
+      /* 20 */
+      COMBA_FORWARD;
+      MULADD(at[7], at[27]);       MULADD(at[8], at[26]);       MULADD(at[9], at[25]);       MULADD(at[10], at[24]);       MULADD(at[11], at[23]);       MULADD(at[12], at[22]);       MULADD(at[13], at[21]); 
+      COMBA_STORE(C->dp[20]);
+      /* 21 */
+      COMBA_FORWARD;
+      MULADD(at[8], at[27]);       MULADD(at[9], at[26]);       MULADD(at[10], at[25]);       MULADD(at[11], at[24]);       MULADD(at[12], at[23]);       MULADD(at[13], at[22]); 
+      COMBA_STORE(C->dp[21]);
+      /* 22 */
+      COMBA_FORWARD;
+      MULADD(at[9], at[27]);       MULADD(at[10], at[26]);       MULADD(at[11], at[25]);       MULADD(at[12], at[24]);       MULADD(at[13], at[23]); 
+      COMBA_STORE(C->dp[22]);
+      /* 23 */
+      COMBA_FORWARD;
+      MULADD(at[10], at[27]);       MULADD(at[11], at[26]);       MULADD(at[12], at[25]);       MULADD(at[13], at[24]); 
+      COMBA_STORE(C->dp[23]);
+      /* 24 */
+      COMBA_FORWARD;
+      MULADD(at[11], at[27]);       MULADD(at[12], at[26]);       MULADD(at[13], at[25]); 
+      COMBA_STORE(C->dp[24]);
+      /* 25 */
+      COMBA_FORWARD;
+      MULADD(at[12], at[27]);       MULADD(at[13], at[26]); 
+      COMBA_STORE(C->dp[25]);
+      /* 26 */
+      COMBA_FORWARD;
+      MULADD(at[13], at[27]); 
+      COMBA_STORE(C->dp[26]);
+      COMBA_STORE2(C->dp[27]);
+      C->used = 28;
+      C->sign = A->sign ^ B->sign;
+      fp_clamp(C);
+      COMBA_FINI;
+      break;
+
+   case 15:
+      memcpy(at, A->dp, 15 * sizeof(fp_digit));
+      memcpy(at+15, B->dp, 15 * sizeof(fp_digit));
+      COMBA_START;
+
+      COMBA_CLEAR;
+      /* 0 */
+      MULADD(at[0], at[15]); 
+      COMBA_STORE(C->dp[0]);
+      /* 1 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[16]);       MULADD(at[1], at[15]); 
+      COMBA_STORE(C->dp[1]);
+      /* 2 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[17]);       MULADD(at[1], at[16]);       MULADD(at[2], at[15]); 
+      COMBA_STORE(C->dp[2]);
+      /* 3 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[18]);       MULADD(at[1], at[17]);       MULADD(at[2], at[16]);       MULADD(at[3], at[15]); 
+      COMBA_STORE(C->dp[3]);
+      /* 4 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[19]);       MULADD(at[1], at[18]);       MULADD(at[2], at[17]);       MULADD(at[3], at[16]);       MULADD(at[4], at[15]); 
+      COMBA_STORE(C->dp[4]);
+      /* 5 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[20]);       MULADD(at[1], at[19]);       MULADD(at[2], at[18]);       MULADD(at[3], at[17]);       MULADD(at[4], at[16]);       MULADD(at[5], at[15]); 
+      COMBA_STORE(C->dp[5]);
+      /* 6 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[21]);       MULADD(at[1], at[20]);       MULADD(at[2], at[19]);       MULADD(at[3], at[18]);       MULADD(at[4], at[17]);       MULADD(at[5], at[16]);       MULADD(at[6], at[15]); 
+      COMBA_STORE(C->dp[6]);
+      /* 7 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[22]);       MULADD(at[1], at[21]);       MULADD(at[2], at[20]);       MULADD(at[3], at[19]);       MULADD(at[4], at[18]);       MULADD(at[5], at[17]);       MULADD(at[6], at[16]);       MULADD(at[7], at[15]); 
+      COMBA_STORE(C->dp[7]);
+      /* 8 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[23]);       MULADD(at[1], at[22]);       MULADD(at[2], at[21]);       MULADD(at[3], at[20]);       MULADD(at[4], at[19]);       MULADD(at[5], at[18]);       MULADD(at[6], at[17]);       MULADD(at[7], at[16]);       MULADD(at[8], at[15]); 
+      COMBA_STORE(C->dp[8]);
+      /* 9 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[24]);       MULADD(at[1], at[23]);       MULADD(at[2], at[22]);       MULADD(at[3], at[21]);       MULADD(at[4], at[20]);       MULADD(at[5], at[19]);       MULADD(at[6], at[18]);       MULADD(at[7], at[17]);       MULADD(at[8], at[16]);       MULADD(at[9], at[15]); 
+      COMBA_STORE(C->dp[9]);
+      /* 10 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[25]);       MULADD(at[1], at[24]);       MULADD(at[2], at[23]);       MULADD(at[3], at[22]);       MULADD(at[4], at[21]);       MULADD(at[5], at[20]);       MULADD(at[6], at[19]);       MULADD(at[7], at[18]);       MULADD(at[8], at[17]);       MULADD(at[9], at[16]);       MULADD(at[10], at[15]); 
+      COMBA_STORE(C->dp[10]);
+      /* 11 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[26]);       MULADD(at[1], at[25]);       MULADD(at[2], at[24]);       MULADD(at[3], at[23]);       MULADD(at[4], at[22]);       MULADD(at[5], at[21]);       MULADD(at[6], at[20]);       MULADD(at[7], at[19]);       MULADD(at[8], at[18]);       MULADD(at[9], at[17]);       MULADD(at[10], at[16]);       MULADD(at[11], at[15]); 
+      COMBA_STORE(C->dp[11]);
+      /* 12 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[27]);       MULADD(at[1], at[26]);       MULADD(at[2], at[25]);       MULADD(at[3], at[24]);       MULADD(at[4], at[23]);       MULADD(at[5], at[22]);       MULADD(at[6], at[21]);       MULADD(at[7], at[20]);       MULADD(at[8], at[19]);       MULADD(at[9], at[18]);       MULADD(at[10], at[17]);       MULADD(at[11], at[16]);       MULADD(at[12], at[15]); 
+      COMBA_STORE(C->dp[12]);
+      /* 13 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[28]);       MULADD(at[1], at[27]);       MULADD(at[2], at[26]);       MULADD(at[3], at[25]);       MULADD(at[4], at[24]);       MULADD(at[5], at[23]);       MULADD(at[6], at[22]);       MULADD(at[7], at[21]);       MULADD(at[8], at[20]);       MULADD(at[9], at[19]);       MULADD(at[10], at[18]);       MULADD(at[11], at[17]);       MULADD(at[12], at[16]);       MULADD(at[13], at[15]); 
+      COMBA_STORE(C->dp[13]);
+      /* 14 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[29]);       MULADD(at[1], at[28]);       MULADD(at[2], at[27]);       MULADD(at[3], at[26]);       MULADD(at[4], at[25]);       MULADD(at[5], at[24]);       MULADD(at[6], at[23]);       MULADD(at[7], at[22]);       MULADD(at[8], at[21]);       MULADD(at[9], at[20]);       MULADD(at[10], at[19]);       MULADD(at[11], at[18]);       MULADD(at[12], at[17]);       MULADD(at[13], at[16]);       MULADD(at[14], at[15]); 
+      COMBA_STORE(C->dp[14]);
+      /* 15 */
+      COMBA_FORWARD;
+      MULADD(at[1], at[29]);       MULADD(at[2], at[28]);       MULADD(at[3], at[27]);       MULADD(at[4], at[26]);       MULADD(at[5], at[25]);       MULADD(at[6], at[24]);       MULADD(at[7], at[23]);       MULADD(at[8], at[22]);       MULADD(at[9], at[21]);       MULADD(at[10], at[20]);       MULADD(at[11], at[19]);       MULADD(at[12], at[18]);       MULADD(at[13], at[17]);       MULADD(at[14], at[16]); 
+      COMBA_STORE(C->dp[15]);
+      /* 16 */
+      COMBA_FORWARD;
+      MULADD(at[2], at[29]);       MULADD(at[3], at[28]);       MULADD(at[4], at[27]);       MULADD(at[5], at[26]);       MULADD(at[6], at[25]);       MULADD(at[7], at[24]);       MULADD(at[8], at[23]);       MULADD(at[9], at[22]);       MULADD(at[10], at[21]);       MULADD(at[11], at[20]);       MULADD(at[12], at[19]);       MULADD(at[13], at[18]);       MULADD(at[14], at[17]); 
+      COMBA_STORE(C->dp[16]);
+      /* 17 */
+      COMBA_FORWARD;
+      MULADD(at[3], at[29]);       MULADD(at[4], at[28]);       MULADD(at[5], at[27]);       MULADD(at[6], at[26]);       MULADD(at[7], at[25]);       MULADD(at[8], at[24]);       MULADD(at[9], at[23]);       MULADD(at[10], at[22]);       MULADD(at[11], at[21]);       MULADD(at[12], at[20]);       MULADD(at[13], at[19]);       MULADD(at[14], at[18]); 
+      COMBA_STORE(C->dp[17]);
+      /* 18 */
+      COMBA_FORWARD;
+      MULADD(at[4], at[29]);       MULADD(at[5], at[28]);       MULADD(at[6], at[27]);       MULADD(at[7], at[26]);       MULADD(at[8], at[25]);       MULADD(at[9], at[24]);       MULADD(at[10], at[23]);       MULADD(at[11], at[22]);       MULADD(at[12], at[21]);       MULADD(at[13], at[20]);       MULADD(at[14], at[19]); 
+      COMBA_STORE(C->dp[18]);
+      /* 19 */
+      COMBA_FORWARD;
+      MULADD(at[5], at[29]);       MULADD(at[6], at[28]);       MULADD(at[7], at[27]);       MULADD(at[8], at[26]);       MULADD(at[9], at[25]);       MULADD(at[10], at[24]);       MULADD(at[11], at[23]);       MULADD(at[12], at[22]);       MULADD(at[13], at[21]);       MULADD(at[14], at[20]); 
+      COMBA_STORE(C->dp[19]);
+      /* 20 */
+      COMBA_FORWARD;
+      MULADD(at[6], at[29]);       MULADD(at[7], at[28]);       MULADD(at[8], at[27]);       MULADD(at[9], at[26]);       MULADD(at[10], at[25]);       MULADD(at[11], at[24]);       MULADD(at[12], at[23]);       MULADD(at[13], at[22]);       MULADD(at[14], at[21]); 
+      COMBA_STORE(C->dp[20]);
+      /* 21 */
+      COMBA_FORWARD;
+      MULADD(at[7], at[29]);       MULADD(at[8], at[28]);       MULADD(at[9], at[27]);       MULADD(at[10], at[26]);       MULADD(at[11], at[25]);       MULADD(at[12], at[24]);       MULADD(at[13], at[23]);       MULADD(at[14], at[22]); 
+      COMBA_STORE(C->dp[21]);
+      /* 22 */
+      COMBA_FORWARD;
+      MULADD(at[8], at[29]);       MULADD(at[9], at[28]);       MULADD(at[10], at[27]);       MULADD(at[11], at[26]);       MULADD(at[12], at[25]);       MULADD(at[13], at[24]);       MULADD(at[14], at[23]); 
+      COMBA_STORE(C->dp[22]);
+      /* 23 */
+      COMBA_FORWARD;
+      MULADD(at[9], at[29]);       MULADD(at[10], at[28]);       MULADD(at[11], at[27]);       MULADD(at[12], at[26]);       MULADD(at[13], at[25]);       MULADD(at[14], at[24]); 
+      COMBA_STORE(C->dp[23]);
+      /* 24 */
+      COMBA_FORWARD;
+      MULADD(at[10], at[29]);       MULADD(at[11], at[28]);       MULADD(at[12], at[27]);       MULADD(at[13], at[26]);       MULADD(at[14], at[25]); 
+      COMBA_STORE(C->dp[24]);
+      /* 25 */
+      COMBA_FORWARD;
+      MULADD(at[11], at[29]);       MULADD(at[12], at[28]);       MULADD(at[13], at[27]);       MULADD(at[14], at[26]); 
+      COMBA_STORE(C->dp[25]);
+      /* 26 */
+      COMBA_FORWARD;
+      MULADD(at[12], at[29]);       MULADD(at[13], at[28]);       MULADD(at[14], at[27]); 
+      COMBA_STORE(C->dp[26]);
+      /* 27 */
+      COMBA_FORWARD;
+      MULADD(at[13], at[29]);       MULADD(at[14], at[28]); 
+      COMBA_STORE(C->dp[27]);
+      /* 28 */
+      COMBA_FORWARD;
+      MULADD(at[14], at[29]); 
+      COMBA_STORE(C->dp[28]);
+      COMBA_STORE2(C->dp[29]);
+      C->used = 30;
+      C->sign = A->sign ^ B->sign;
+      fp_clamp(C);
+      COMBA_FINI;
+      break;
+
+   case 16:
+      memcpy(at, A->dp, 16 * sizeof(fp_digit));
+      memcpy(at+16, B->dp, 16 * sizeof(fp_digit));
+      COMBA_START;
+
+      COMBA_CLEAR;
+      /* 0 */
+      MULADD(at[0], at[16]); 
+      COMBA_STORE(C->dp[0]);
+      /* 1 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[17]);       MULADD(at[1], at[16]); 
+      COMBA_STORE(C->dp[1]);
+      /* 2 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[18]);       MULADD(at[1], at[17]);       MULADD(at[2], at[16]); 
+      COMBA_STORE(C->dp[2]);
+      /* 3 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[19]);       MULADD(at[1], at[18]);       MULADD(at[2], at[17]);       MULADD(at[3], at[16]); 
+      COMBA_STORE(C->dp[3]);
+      /* 4 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[20]);       MULADD(at[1], at[19]);       MULADD(at[2], at[18]);       MULADD(at[3], at[17]);       MULADD(at[4], at[16]); 
+      COMBA_STORE(C->dp[4]);
+      /* 5 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[21]);       MULADD(at[1], at[20]);       MULADD(at[2], at[19]);       MULADD(at[3], at[18]);       MULADD(at[4], at[17]);       MULADD(at[5], at[16]); 
+      COMBA_STORE(C->dp[5]);
+      /* 6 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[22]);       MULADD(at[1], at[21]);       MULADD(at[2], at[20]);       MULADD(at[3], at[19]);       MULADD(at[4], at[18]);       MULADD(at[5], at[17]);       MULADD(at[6], at[16]); 
+      COMBA_STORE(C->dp[6]);
+      /* 7 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[23]);       MULADD(at[1], at[22]);       MULADD(at[2], at[21]);       MULADD(at[3], at[20]);       MULADD(at[4], at[19]);       MULADD(at[5], at[18]);       MULADD(at[6], at[17]);       MULADD(at[7], at[16]); 
+      COMBA_STORE(C->dp[7]);
+      /* 8 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[24]);       MULADD(at[1], at[23]);       MULADD(at[2], at[22]);       MULADD(at[3], at[21]);       MULADD(at[4], at[20]);       MULADD(at[5], at[19]);       MULADD(at[6], at[18]);       MULADD(at[7], at[17]);       MULADD(at[8], at[16]); 
+      COMBA_STORE(C->dp[8]);
+      /* 9 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[25]);       MULADD(at[1], at[24]);       MULADD(at[2], at[23]);       MULADD(at[3], at[22]);       MULADD(at[4], at[21]);       MULADD(at[5], at[20]);       MULADD(at[6], at[19]);       MULADD(at[7], at[18]);       MULADD(at[8], at[17]);       MULADD(at[9], at[16]); 
+      COMBA_STORE(C->dp[9]);
+      /* 10 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[26]);       MULADD(at[1], at[25]);       MULADD(at[2], at[24]);       MULADD(at[3], at[23]);       MULADD(at[4], at[22]);       MULADD(at[5], at[21]);       MULADD(at[6], at[20]);       MULADD(at[7], at[19]);       MULADD(at[8], at[18]);       MULADD(at[9], at[17]);       MULADD(at[10], at[16]); 
+      COMBA_STORE(C->dp[10]);
+      /* 11 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[27]);       MULADD(at[1], at[26]);       MULADD(at[2], at[25]);       MULADD(at[3], at[24]);       MULADD(at[4], at[23]);       MULADD(at[5], at[22]);       MULADD(at[6], at[21]);       MULADD(at[7], at[20]);       MULADD(at[8], at[19]);       MULADD(at[9], at[18]);       MULADD(at[10], at[17]);       MULADD(at[11], at[16]); 
+      COMBA_STORE(C->dp[11]);
+      /* 12 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[28]);       MULADD(at[1], at[27]);       MULADD(at[2], at[26]);       MULADD(at[3], at[25]);       MULADD(at[4], at[24]);       MULADD(at[5], at[23]);       MULADD(at[6], at[22]);       MULADD(at[7], at[21]);       MULADD(at[8], at[20]);       MULADD(at[9], at[19]);       MULADD(at[10], at[18]);       MULADD(at[11], at[17]);       MULADD(at[12], at[16]); 
+      COMBA_STORE(C->dp[12]);
+      /* 13 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[29]);       MULADD(at[1], at[28]);       MULADD(at[2], at[27]);       MULADD(at[3], at[26]);       MULADD(at[4], at[25]);       MULADD(at[5], at[24]);       MULADD(at[6], at[23]);       MULADD(at[7], at[22]);       MULADD(at[8], at[21]);       MULADD(at[9], at[20]);       MULADD(at[10], at[19]);       MULADD(at[11], at[18]);       MULADD(at[12], at[17]);       MULADD(at[13], at[16]); 
+      COMBA_STORE(C->dp[13]);
+      /* 14 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[30]);       MULADD(at[1], at[29]);       MULADD(at[2], at[28]);       MULADD(at[3], at[27]);       MULADD(at[4], at[26]);       MULADD(at[5], at[25]);       MULADD(at[6], at[24]);       MULADD(at[7], at[23]);       MULADD(at[8], at[22]);       MULADD(at[9], at[21]);       MULADD(at[10], at[20]);       MULADD(at[11], at[19]);       MULADD(at[12], at[18]);       MULADD(at[13], at[17]);       MULADD(at[14], at[16]); 
+      COMBA_STORE(C->dp[14]);
+      /* 15 */
+      COMBA_FORWARD;
+      MULADD(at[0], at[31]);       MULADD(at[1], at[30]);       MULADD(at[2], at[29]);       MULADD(at[3], at[28]);       MULADD(at[4], at[27]);       MULADD(at[5], at[26]);       MULADD(at[6], at[25]);       MULADD(at[7], at[24]);       MULADD(at[8], at[23]);       MULADD(at[9], at[22]);       MULADD(at[10], at[21]);       MULADD(at[11], at[20]);       MULADD(at[12], at[19]);       MULADD(at[13], at[18]);       MULADD(at[14], at[17]);       MULADD(at[15], at[16]); 
+      COMBA_STORE(C->dp[15]);
+      /* 16 */
+      COMBA_FORWARD;
+      MULADD(at[1], at[31]);       MULADD(at[2], at[30]);       MULADD(at[3], at[29]);       MULADD(at[4], at[28]);       MULADD(at[5], at[27]);       MULADD(at[6], at[26]);       MULADD(at[7], at[25]);       MULADD(at[8], at[24]);       MULADD(at[9], at[23]);       MULADD(at[10], at[22]);       MULADD(at[11], at[21]);       MULADD(at[12], at[20]);       MULADD(at[13], at[19]);       MULADD(at[14], at[18]);       MULADD(at[15], at[17]); 
+      COMBA_STORE(C->dp[16]);
+      /* 17 */
+      COMBA_FORWARD;
+      MULADD(at[2], at[31]);       MULADD(at[3], at[30]);       MULADD(at[4], at[29]);       MULADD(at[5], at[28]);       MULADD(at[6], at[27]);       MULADD(at[7], at[26]);       MULADD(at[8], at[25]);       MULADD(at[9], at[24]);       MULADD(at[10], at[23]);       MULADD(at[11], at[22]);       MULADD(at[12], at[21]);       MULADD(at[13], at[20]);       MULADD(at[14], at[19]);       MULADD(at[15], at[18]); 
+      COMBA_STORE(C->dp[17]);
+      /* 18 */
+      COMBA_FORWARD;
+      MULADD(at[3], at[31]);       MULADD(at[4], at[30]);       MULADD(at[5], at[29]);       MULADD(at[6], at[28]);       MULADD(at[7], at[27]);       MULADD(at[8], at[26]);       MULADD(at[9], at[25]);       MULADD(at[10], at[24]);       MULADD(at[11], at[23]);       MULADD(at[12], at[22]);       MULADD(at[13], at[21]);       MULADD(at[14], at[20]);       MULADD(at[15], at[19]); 
+      COMBA_STORE(C->dp[18]);
+      /* 19 */
+      COMBA_FORWARD;
+      MULADD(at[4], at[31]);       MULADD(at[5], at[30]);       MULADD(at[6], at[29]);       MULADD(at[7], at[28]);       MULADD(at[8], at[27]);       MULADD(at[9], at[26]);       MULADD(at[10], at[25]);       MULADD(at[11], at[24]);       MULADD(at[12], at[23]);       MULADD(at[13], at[22]);       MULADD(at[14], at[21]);       MULADD(at[15], at[20]); 
+      COMBA_STORE(C->dp[19]);
+      /* 20 */
+      COMBA_FORWARD;
+      MULADD(at[5], at[31]);       MULADD(at[6], at[30]);       MULADD(at[7], at[29]);       MULADD(at[8], at[28]);       MULADD(at[9], at[27]);       MULADD(at[10], at[26]);       MULADD(at[11], at[25]);       MULADD(at[12], at[24]);       MULADD(at[13], at[23]);       MULADD(at[14], at[22]);       MULADD(at[15], at[21]); 
+      COMBA_STORE(C->dp[20]);
+      /* 21 */
+      COMBA_FORWARD;
+      MULADD(at[6], at[31]);       MULADD(at[7], at[30]);       MULADD(at[8], at[29]);       MULADD(at[9], at[28]);       MULADD(at[10], at[27]);       MULADD(at[11], at[26]);       MULADD(at[12], at[25]);       MULADD(at[13], at[24]);       MULADD(at[14], at[23]);       MULADD(at[15], at[22]); 
+      COMBA_STORE(C->dp[21]);
+      /* 22 */
+      COMBA_FORWARD;
+      MULADD(at[7], at[31]);       MULADD(at[8], at[30]);       MULADD(at[9], at[29]);       MULADD(at[10], at[28]);       MULADD(at[11], at[27]);       MULADD(at[12], at[26]);       MULADD(at[13], at[25]);       MULADD(at[14], at[24]);       MULADD(at[15], at[23]); 
+      COMBA_STORE(C->dp[22]);
+      /* 23 */
+      COMBA_FORWARD;
+      MULADD(at[8], at[31]);       MULADD(at[9], at[30]);       MULADD(at[10], at[29]);       MULADD(at[11], at[28]);       MULADD(at[12], at[27]);       MULADD(at[13], at[26]);       MULADD(at[14], at[25]);       MULADD(at[15], at[24]); 
+      COMBA_STORE(C->dp[23]);
+      /* 24 */
+      COMBA_FORWARD;
+      MULADD(at[9], at[31]);       MULADD(at[10], at[30]);       MULADD(at[11], at[29]);       MULADD(at[12], at[28]);       MULADD(at[13], at[27]);       MULADD(at[14], at[26]);       MULADD(at[15], at[25]); 
+      COMBA_STORE(C->dp[24]);
+      /* 25 */
+      COMBA_FORWARD;
+      MULADD(at[10], at[31]);       MULADD(at[11], at[30]);       MULADD(at[12], at[29]);       MULADD(at[13], at[28]);       MULADD(at[14], at[27]);       MULADD(at[15], at[26]); 
+      COMBA_STORE(C->dp[25]);
+      /* 26 */
+      COMBA_FORWARD;
+      MULADD(at[11], at[31]);       MULADD(at[12], at[30]);       MULADD(at[13], at[29]);       MULADD(at[14], at[28]);       MULADD(at[15], at[27]); 
+      COMBA_STORE(C->dp[26]);
+      /* 27 */
+      COMBA_FORWARD;
+      MULADD(at[12], at[31]);       MULADD(at[13], at[30]);       MULADD(at[14], at[29]);       MULADD(at[15], at[28]); 
+      COMBA_STORE(C->dp[27]);
+      /* 28 */
+      COMBA_FORWARD;
+      MULADD(at[13], at[31]);       MULADD(at[14], at[30]);       MULADD(at[15], at[29]); 
+      COMBA_STORE(C->dp[28]);
+      /* 29 */
+      COMBA_FORWARD;
+      MULADD(at[14], at[31]);       MULADD(at[15], at[30]); 
+      COMBA_STORE(C->dp[29]);
+      /* 30 */
+      COMBA_FORWARD;
+      MULADD(at[15], at[31]); 
+      COMBA_STORE(C->dp[30]);
+      COMBA_STORE2(C->dp[31]);
+      C->used = 32;
+      C->sign = A->sign ^ B->sign;
+      fp_clamp(C);
+      COMBA_FINI;
+      break;
+
+   default:
+      break;
+   }
+}
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_12.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_12.i
new file mode 100644
index 0000000..078b898
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_12.i
@@ -0,0 +1,159 @@
+/* fp_sqr_comba_12.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_SQR12
+void fp_sqr_comba12(fp_int *A, fp_int *B)
+{
+   fp_digit *a, b[24], c0, c1, c2, sc0, sc1, sc2;
+#ifdef TFM_ISO
+   fp_word tt;
+#endif
+   a = A->dp;
+   COMBA_START; 
+
+   /* clear carries */
+   CLEAR_CARRY;
+
+   /* output 0 */
+   SQRADD(a[0],a[0]);
+   COMBA_STORE(b[0]);
+
+   /* output 1 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[1]); 
+   COMBA_STORE(b[1]);
+
+   /* output 2 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[2]); SQRADD(a[1], a[1]); 
+   COMBA_STORE(b[2]);
+
+   /* output 3 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[3]); SQRADD2(a[1], a[2]); 
+   COMBA_STORE(b[3]);
+
+   /* output 4 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[4]); SQRADD2(a[1], a[3]); SQRADD(a[2], a[2]); 
+   COMBA_STORE(b[4]);
+
+   /* output 5 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[5]); SQRADDAC(a[1], a[4]); SQRADDAC(a[2], a[3]); SQRADDDB; 
+   COMBA_STORE(b[5]);
+
+   /* output 6 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[6]); SQRADDAC(a[1], a[5]); SQRADDAC(a[2], a[4]); SQRADDDB; SQRADD(a[3], a[3]); 
+   COMBA_STORE(b[6]);
+
+   /* output 7 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[7]); SQRADDAC(a[1], a[6]); SQRADDAC(a[2], a[5]); SQRADDAC(a[3], a[4]); SQRADDDB; 
+   COMBA_STORE(b[7]);
+
+   /* output 8 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[8]); SQRADDAC(a[1], a[7]); SQRADDAC(a[2], a[6]); SQRADDAC(a[3], a[5]); SQRADDDB; SQRADD(a[4], a[4]); 
+   COMBA_STORE(b[8]);
+
+   /* output 9 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[9]); SQRADDAC(a[1], a[8]); SQRADDAC(a[2], a[7]); SQRADDAC(a[3], a[6]); SQRADDAC(a[4], a[5]); SQRADDDB; 
+   COMBA_STORE(b[9]);
+
+   /* output 10 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[10]); SQRADDAC(a[1], a[9]); SQRADDAC(a[2], a[8]); SQRADDAC(a[3], a[7]); SQRADDAC(a[4], a[6]); SQRADDDB; SQRADD(a[5], a[5]); 
+   COMBA_STORE(b[10]);
+
+   /* output 11 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[11]); SQRADDAC(a[1], a[10]); SQRADDAC(a[2], a[9]); SQRADDAC(a[3], a[8]); SQRADDAC(a[4], a[7]); SQRADDAC(a[5], a[6]); SQRADDDB; 
+   COMBA_STORE(b[11]);
+
+   /* output 12 */
+   CARRY_FORWARD;
+   SQRADDSC(a[1], a[11]); SQRADDAC(a[2], a[10]); SQRADDAC(a[3], a[9]); SQRADDAC(a[4], a[8]); SQRADDAC(a[5], a[7]); SQRADDDB; SQRADD(a[6], a[6]); 
+   COMBA_STORE(b[12]);
+
+   /* output 13 */
+   CARRY_FORWARD;
+   SQRADDSC(a[2], a[11]); SQRADDAC(a[3], a[10]); SQRADDAC(a[4], a[9]); SQRADDAC(a[5], a[8]); SQRADDAC(a[6], a[7]); SQRADDDB; 
+   COMBA_STORE(b[13]);
+
+   /* output 14 */
+   CARRY_FORWARD;
+   SQRADDSC(a[3], a[11]); SQRADDAC(a[4], a[10]); SQRADDAC(a[5], a[9]); SQRADDAC(a[6], a[8]); SQRADDDB; SQRADD(a[7], a[7]); 
+   COMBA_STORE(b[14]);
+
+   /* output 15 */
+   CARRY_FORWARD;
+   SQRADDSC(a[4], a[11]); SQRADDAC(a[5], a[10]); SQRADDAC(a[6], a[9]); SQRADDAC(a[7], a[8]); SQRADDDB; 
+   COMBA_STORE(b[15]);
+
+   /* output 16 */
+   CARRY_FORWARD;
+   SQRADDSC(a[5], a[11]); SQRADDAC(a[6], a[10]); SQRADDAC(a[7], a[9]); SQRADDDB; SQRADD(a[8], a[8]); 
+   COMBA_STORE(b[16]);
+
+   /* output 17 */
+   CARRY_FORWARD;
+   SQRADDSC(a[6], a[11]); SQRADDAC(a[7], a[10]); SQRADDAC(a[8], a[9]); SQRADDDB; 
+   COMBA_STORE(b[17]);
+
+   /* output 18 */
+   CARRY_FORWARD;
+   SQRADD2(a[7], a[11]); SQRADD2(a[8], a[10]); SQRADD(a[9], a[9]); 
+   COMBA_STORE(b[18]);
+
+   /* output 19 */
+   CARRY_FORWARD;
+   SQRADD2(a[8], a[11]); SQRADD2(a[9], a[10]); 
+   COMBA_STORE(b[19]);
+
+   /* output 20 */
+   CARRY_FORWARD;
+   SQRADD2(a[9], a[11]); SQRADD(a[10], a[10]); 
+   COMBA_STORE(b[20]);
+
+   /* output 21 */
+   CARRY_FORWARD;
+   SQRADD2(a[10], a[11]); 
+   COMBA_STORE(b[21]);
+
+   /* output 22 */
+   CARRY_FORWARD;
+   SQRADD(a[11], a[11]); 
+   COMBA_STORE(b[22]);
+   COMBA_STORE2(b[23]);
+   COMBA_FINI;
+
+   B->used = 24;
+   B->sign = FP_ZPOS;
+   memcpy(B->dp, b, 24 * sizeof(fp_digit));
+   fp_clamp(B);
+}
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_17.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_17.i
new file mode 100644
index 0000000..d5f4674
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_17.i
@@ -0,0 +1,210 @@
+/* fp_sqr_comba_17.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_SQR17
+void fp_sqr_comba17(fp_int *A, fp_int *B)
+{
+   fp_digit *a, b[34], c0, c1, c2, sc0, sc1, sc2;
+#ifdef TFM_ISO
+   fp_word tt;
+#endif
+
+   a = A->dp;
+   COMBA_START; 
+
+   /* clear carries */
+   CLEAR_CARRY;
+
+   /* output 0 */
+   SQRADD(a[0],a[0]);
+   COMBA_STORE(b[0]);
+
+   /* output 1 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[1]); 
+   COMBA_STORE(b[1]);
+
+   /* output 2 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[2]); SQRADD(a[1], a[1]); 
+   COMBA_STORE(b[2]);
+
+   /* output 3 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[3]); SQRADD2(a[1], a[2]); 
+   COMBA_STORE(b[3]);
+
+   /* output 4 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[4]); SQRADD2(a[1], a[3]); SQRADD(a[2], a[2]); 
+   COMBA_STORE(b[4]);
+
+   /* output 5 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[5]); SQRADDAC(a[1], a[4]); SQRADDAC(a[2], a[3]); SQRADDDB; 
+   COMBA_STORE(b[5]);
+
+   /* output 6 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[6]); SQRADDAC(a[1], a[5]); SQRADDAC(a[2], a[4]); SQRADDDB; SQRADD(a[3], a[3]); 
+   COMBA_STORE(b[6]);
+
+   /* output 7 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[7]); SQRADDAC(a[1], a[6]); SQRADDAC(a[2], a[5]); SQRADDAC(a[3], a[4]); SQRADDDB; 
+   COMBA_STORE(b[7]);
+
+   /* output 8 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[8]); SQRADDAC(a[1], a[7]); SQRADDAC(a[2], a[6]); SQRADDAC(a[3], a[5]); SQRADDDB; SQRADD(a[4], a[4]); 
+   COMBA_STORE(b[8]);
+
+   /* output 9 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[9]); SQRADDAC(a[1], a[8]); SQRADDAC(a[2], a[7]); SQRADDAC(a[3], a[6]); SQRADDAC(a[4], a[5]); SQRADDDB; 
+   COMBA_STORE(b[9]);
+
+   /* output 10 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[10]); SQRADDAC(a[1], a[9]); SQRADDAC(a[2], a[8]); SQRADDAC(a[3], a[7]); SQRADDAC(a[4], a[6]); SQRADDDB; SQRADD(a[5], a[5]); 
+   COMBA_STORE(b[10]);
+
+   /* output 11 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[11]); SQRADDAC(a[1], a[10]); SQRADDAC(a[2], a[9]); SQRADDAC(a[3], a[8]); SQRADDAC(a[4], a[7]); SQRADDAC(a[5], a[6]); SQRADDDB; 
+   COMBA_STORE(b[11]);
+
+   /* output 12 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[12]); SQRADDAC(a[1], a[11]); SQRADDAC(a[2], a[10]); SQRADDAC(a[3], a[9]); SQRADDAC(a[4], a[8]); SQRADDAC(a[5], a[7]); SQRADDDB; SQRADD(a[6], a[6]); 
+   COMBA_STORE(b[12]);
+
+   /* output 13 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[13]); SQRADDAC(a[1], a[12]); SQRADDAC(a[2], a[11]); SQRADDAC(a[3], a[10]); SQRADDAC(a[4], a[9]); SQRADDAC(a[5], a[8]); SQRADDAC(a[6], a[7]); SQRADDDB; 
+   COMBA_STORE(b[13]);
+
+   /* output 14 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[14]); SQRADDAC(a[1], a[13]); SQRADDAC(a[2], a[12]); SQRADDAC(a[3], a[11]); SQRADDAC(a[4], a[10]); SQRADDAC(a[5], a[9]); SQRADDAC(a[6], a[8]); SQRADDDB; SQRADD(a[7], a[7]); 
+   COMBA_STORE(b[14]);
+
+   /* output 15 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[15]); SQRADDAC(a[1], a[14]); SQRADDAC(a[2], a[13]); SQRADDAC(a[3], a[12]); SQRADDAC(a[4], a[11]); SQRADDAC(a[5], a[10]); SQRADDAC(a[6], a[9]); SQRADDAC(a[7], a[8]); SQRADDDB; 
+   COMBA_STORE(b[15]);
+
+   /* output 16 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[16]); SQRADDAC(a[1], a[15]); SQRADDAC(a[2], a[14]); SQRADDAC(a[3], a[13]); SQRADDAC(a[4], a[12]); SQRADDAC(a[5], a[11]); SQRADDAC(a[6], a[10]); SQRADDAC(a[7], a[9]); SQRADDDB; SQRADD(a[8], a[8]); 
+   COMBA_STORE(b[16]);
+
+   /* output 17 */
+   CARRY_FORWARD;
+   SQRADDSC(a[1], a[16]); SQRADDAC(a[2], a[15]); SQRADDAC(a[3], a[14]); SQRADDAC(a[4], a[13]); SQRADDAC(a[5], a[12]); SQRADDAC(a[6], a[11]); SQRADDAC(a[7], a[10]); SQRADDAC(a[8], a[9]); SQRADDDB; 
+   COMBA_STORE(b[17]);
+
+   /* output 18 */
+   CARRY_FORWARD;
+   SQRADDSC(a[2], a[16]); SQRADDAC(a[3], a[15]); SQRADDAC(a[4], a[14]); SQRADDAC(a[5], a[13]); SQRADDAC(a[6], a[12]); SQRADDAC(a[7], a[11]); SQRADDAC(a[8], a[10]); SQRADDDB; SQRADD(a[9], a[9]); 
+   COMBA_STORE(b[18]);
+
+   /* output 19 */
+   CARRY_FORWARD;
+   SQRADDSC(a[3], a[16]); SQRADDAC(a[4], a[15]); SQRADDAC(a[5], a[14]); SQRADDAC(a[6], a[13]); SQRADDAC(a[7], a[12]); SQRADDAC(a[8], a[11]); SQRADDAC(a[9], a[10]); SQRADDDB; 
+   COMBA_STORE(b[19]);
+
+   /* output 20 */
+   CARRY_FORWARD;
+   SQRADDSC(a[4], a[16]); SQRADDAC(a[5], a[15]); SQRADDAC(a[6], a[14]); SQRADDAC(a[7], a[13]); SQRADDAC(a[8], a[12]); SQRADDAC(a[9], a[11]); SQRADDDB; SQRADD(a[10], a[10]); 
+   COMBA_STORE(b[20]);
+
+   /* output 21 */
+   CARRY_FORWARD;
+   SQRADDSC(a[5], a[16]); SQRADDAC(a[6], a[15]); SQRADDAC(a[7], a[14]); SQRADDAC(a[8], a[13]); SQRADDAC(a[9], a[12]); SQRADDAC(a[10], a[11]); SQRADDDB; 
+   COMBA_STORE(b[21]);
+
+   /* output 22 */
+   CARRY_FORWARD;
+   SQRADDSC(a[6], a[16]); SQRADDAC(a[7], a[15]); SQRADDAC(a[8], a[14]); SQRADDAC(a[9], a[13]); SQRADDAC(a[10], a[12]); SQRADDDB; SQRADD(a[11], a[11]); 
+   COMBA_STORE(b[22]);
+
+   /* output 23 */
+   CARRY_FORWARD;
+   SQRADDSC(a[7], a[16]); SQRADDAC(a[8], a[15]); SQRADDAC(a[9], a[14]); SQRADDAC(a[10], a[13]); SQRADDAC(a[11], a[12]); SQRADDDB; 
+   COMBA_STORE(b[23]);
+
+   /* output 24 */
+   CARRY_FORWARD;
+   SQRADDSC(a[8], a[16]); SQRADDAC(a[9], a[15]); SQRADDAC(a[10], a[14]); SQRADDAC(a[11], a[13]); SQRADDDB; SQRADD(a[12], a[12]); 
+   COMBA_STORE(b[24]);
+
+   /* output 25 */
+   CARRY_FORWARD;
+   SQRADDSC(a[9], a[16]); SQRADDAC(a[10], a[15]); SQRADDAC(a[11], a[14]); SQRADDAC(a[12], a[13]); SQRADDDB; 
+   COMBA_STORE(b[25]);
+
+   /* output 26 */
+   CARRY_FORWARD;
+   SQRADDSC(a[10], a[16]); SQRADDAC(a[11], a[15]); SQRADDAC(a[12], a[14]); SQRADDDB; SQRADD(a[13], a[13]); 
+   COMBA_STORE(b[26]);
+
+   /* output 27 */
+   CARRY_FORWARD;
+   SQRADDSC(a[11], a[16]); SQRADDAC(a[12], a[15]); SQRADDAC(a[13], a[14]); SQRADDDB; 
+   COMBA_STORE(b[27]);
+
+   /* output 28 */
+   CARRY_FORWARD;
+   SQRADD2(a[12], a[16]); SQRADD2(a[13], a[15]); SQRADD(a[14], a[14]); 
+   COMBA_STORE(b[28]);
+
+   /* output 29 */
+   CARRY_FORWARD;
+   SQRADD2(a[13], a[16]); SQRADD2(a[14], a[15]); 
+   COMBA_STORE(b[29]);
+
+   /* output 30 */
+   CARRY_FORWARD;
+   SQRADD2(a[14], a[16]); SQRADD(a[15], a[15]); 
+   COMBA_STORE(b[30]);
+
+   /* output 31 */
+   CARRY_FORWARD;
+   SQRADD2(a[15], a[16]); 
+   COMBA_STORE(b[31]);
+
+   /* output 32 */
+   CARRY_FORWARD;
+   SQRADD(a[16], a[16]); 
+   COMBA_STORE(b[32]);
+   COMBA_STORE2(b[33]);
+   COMBA_FINI;
+
+   B->used = 34;
+   B->sign = FP_ZPOS;
+   memcpy(B->dp, b, 34 * sizeof(fp_digit));
+   fp_clamp(B);
+}
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_20.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_20.i
new file mode 100644
index 0000000..dcd9f31
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_20.i
@@ -0,0 +1,240 @@
+/* fp_sqr_comba_20.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_SQR20
+void fp_sqr_comba20(fp_int *A, fp_int *B)
+{
+   fp_digit *a, b[40], c0, c1, c2, sc0, sc1, sc2;
+#ifdef TFM_ISO
+   fp_word   tt;   
+#endif   
+
+   a = A->dp;
+   COMBA_START; 
+
+   /* clear carries */
+   CLEAR_CARRY;
+
+   /* output 0 */
+   SQRADD(a[0],a[0]);
+   COMBA_STORE(b[0]);
+
+   /* output 1 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[1]); 
+   COMBA_STORE(b[1]);
+
+   /* output 2 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[2]); SQRADD(a[1], a[1]); 
+   COMBA_STORE(b[2]);
+
+   /* output 3 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[3]); SQRADD2(a[1], a[2]); 
+   COMBA_STORE(b[3]);
+
+   /* output 4 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[4]); SQRADD2(a[1], a[3]); SQRADD(a[2], a[2]); 
+   COMBA_STORE(b[4]);
+
+   /* output 5 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[5]); SQRADDAC(a[1], a[4]); SQRADDAC(a[2], a[3]); SQRADDDB; 
+   COMBA_STORE(b[5]);
+
+   /* output 6 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[6]); SQRADDAC(a[1], a[5]); SQRADDAC(a[2], a[4]); SQRADDDB; SQRADD(a[3], a[3]); 
+   COMBA_STORE(b[6]);
+
+   /* output 7 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[7]); SQRADDAC(a[1], a[6]); SQRADDAC(a[2], a[5]); SQRADDAC(a[3], a[4]); SQRADDDB; 
+   COMBA_STORE(b[7]);
+
+   /* output 8 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[8]); SQRADDAC(a[1], a[7]); SQRADDAC(a[2], a[6]); SQRADDAC(a[3], a[5]); SQRADDDB; SQRADD(a[4], a[4]); 
+   COMBA_STORE(b[8]);
+
+   /* output 9 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[9]); SQRADDAC(a[1], a[8]); SQRADDAC(a[2], a[7]); SQRADDAC(a[3], a[6]); SQRADDAC(a[4], a[5]); SQRADDDB; 
+   COMBA_STORE(b[9]);
+
+   /* output 10 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[10]); SQRADDAC(a[1], a[9]); SQRADDAC(a[2], a[8]); SQRADDAC(a[3], a[7]); SQRADDAC(a[4], a[6]); SQRADDDB; SQRADD(a[5], a[5]); 
+   COMBA_STORE(b[10]);
+
+   /* output 11 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[11]); SQRADDAC(a[1], a[10]); SQRADDAC(a[2], a[9]); SQRADDAC(a[3], a[8]); SQRADDAC(a[4], a[7]); SQRADDAC(a[5], a[6]); SQRADDDB; 
+   COMBA_STORE(b[11]);
+
+   /* output 12 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[12]); SQRADDAC(a[1], a[11]); SQRADDAC(a[2], a[10]); SQRADDAC(a[3], a[9]); SQRADDAC(a[4], a[8]); SQRADDAC(a[5], a[7]); SQRADDDB; SQRADD(a[6], a[6]); 
+   COMBA_STORE(b[12]);
+
+   /* output 13 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[13]); SQRADDAC(a[1], a[12]); SQRADDAC(a[2], a[11]); SQRADDAC(a[3], a[10]); SQRADDAC(a[4], a[9]); SQRADDAC(a[5], a[8]); SQRADDAC(a[6], a[7]); SQRADDDB; 
+   COMBA_STORE(b[13]);
+
+   /* output 14 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[14]); SQRADDAC(a[1], a[13]); SQRADDAC(a[2], a[12]); SQRADDAC(a[3], a[11]); SQRADDAC(a[4], a[10]); SQRADDAC(a[5], a[9]); SQRADDAC(a[6], a[8]); SQRADDDB; SQRADD(a[7], a[7]); 
+   COMBA_STORE(b[14]);
+
+   /* output 15 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[15]); SQRADDAC(a[1], a[14]); SQRADDAC(a[2], a[13]); SQRADDAC(a[3], a[12]); SQRADDAC(a[4], a[11]); SQRADDAC(a[5], a[10]); SQRADDAC(a[6], a[9]); SQRADDAC(a[7], a[8]); SQRADDDB; 
+   COMBA_STORE(b[15]);
+
+   /* output 16 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[16]); SQRADDAC(a[1], a[15]); SQRADDAC(a[2], a[14]); SQRADDAC(a[3], a[13]); SQRADDAC(a[4], a[12]); SQRADDAC(a[5], a[11]); SQRADDAC(a[6], a[10]); SQRADDAC(a[7], a[9]); SQRADDDB; SQRADD(a[8], a[8]); 
+   COMBA_STORE(b[16]);
+
+   /* output 17 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[17]); SQRADDAC(a[1], a[16]); SQRADDAC(a[2], a[15]); SQRADDAC(a[3], a[14]); SQRADDAC(a[4], a[13]); SQRADDAC(a[5], a[12]); SQRADDAC(a[6], a[11]); SQRADDAC(a[7], a[10]); SQRADDAC(a[8], a[9]); SQRADDDB; 
+   COMBA_STORE(b[17]);
+
+   /* output 18 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[18]); SQRADDAC(a[1], a[17]); SQRADDAC(a[2], a[16]); SQRADDAC(a[3], a[15]); SQRADDAC(a[4], a[14]); SQRADDAC(a[5], a[13]); SQRADDAC(a[6], a[12]); SQRADDAC(a[7], a[11]); SQRADDAC(a[8], a[10]); SQRADDDB; SQRADD(a[9], a[9]); 
+   COMBA_STORE(b[18]);
+
+   /* output 19 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[19]); SQRADDAC(a[1], a[18]); SQRADDAC(a[2], a[17]); SQRADDAC(a[3], a[16]); SQRADDAC(a[4], a[15]); SQRADDAC(a[5], a[14]); SQRADDAC(a[6], a[13]); SQRADDAC(a[7], a[12]); SQRADDAC(a[8], a[11]); SQRADDAC(a[9], a[10]); SQRADDDB; 
+   COMBA_STORE(b[19]);
+
+   /* output 20 */
+   CARRY_FORWARD;
+   SQRADDSC(a[1], a[19]); SQRADDAC(a[2], a[18]); SQRADDAC(a[3], a[17]); SQRADDAC(a[4], a[16]); SQRADDAC(a[5], a[15]); SQRADDAC(a[6], a[14]); SQRADDAC(a[7], a[13]); SQRADDAC(a[8], a[12]); SQRADDAC(a[9], a[11]); SQRADDDB; SQRADD(a[10], a[10]); 
+   COMBA_STORE(b[20]);
+
+   /* output 21 */
+   CARRY_FORWARD;
+   SQRADDSC(a[2], a[19]); SQRADDAC(a[3], a[18]); SQRADDAC(a[4], a[17]); SQRADDAC(a[5], a[16]); SQRADDAC(a[6], a[15]); SQRADDAC(a[7], a[14]); SQRADDAC(a[8], a[13]); SQRADDAC(a[9], a[12]); SQRADDAC(a[10], a[11]); SQRADDDB; 
+   COMBA_STORE(b[21]);
+
+   /* output 22 */
+   CARRY_FORWARD;
+   SQRADDSC(a[3], a[19]); SQRADDAC(a[4], a[18]); SQRADDAC(a[5], a[17]); SQRADDAC(a[6], a[16]); SQRADDAC(a[7], a[15]); SQRADDAC(a[8], a[14]); SQRADDAC(a[9], a[13]); SQRADDAC(a[10], a[12]); SQRADDDB; SQRADD(a[11], a[11]); 
+   COMBA_STORE(b[22]);
+
+   /* output 23 */
+   CARRY_FORWARD;
+   SQRADDSC(a[4], a[19]); SQRADDAC(a[5], a[18]); SQRADDAC(a[6], a[17]); SQRADDAC(a[7], a[16]); SQRADDAC(a[8], a[15]); SQRADDAC(a[9], a[14]); SQRADDAC(a[10], a[13]); SQRADDAC(a[11], a[12]); SQRADDDB; 
+   COMBA_STORE(b[23]);
+
+   /* output 24 */
+   CARRY_FORWARD;
+   SQRADDSC(a[5], a[19]); SQRADDAC(a[6], a[18]); SQRADDAC(a[7], a[17]); SQRADDAC(a[8], a[16]); SQRADDAC(a[9], a[15]); SQRADDAC(a[10], a[14]); SQRADDAC(a[11], a[13]); SQRADDDB; SQRADD(a[12], a[12]); 
+   COMBA_STORE(b[24]);
+
+   /* output 25 */
+   CARRY_FORWARD;
+   SQRADDSC(a[6], a[19]); SQRADDAC(a[7], a[18]); SQRADDAC(a[8], a[17]); SQRADDAC(a[9], a[16]); SQRADDAC(a[10], a[15]); SQRADDAC(a[11], a[14]); SQRADDAC(a[12], a[13]); SQRADDDB; 
+   COMBA_STORE(b[25]);
+
+   /* output 26 */
+   CARRY_FORWARD;
+   SQRADDSC(a[7], a[19]); SQRADDAC(a[8], a[18]); SQRADDAC(a[9], a[17]); SQRADDAC(a[10], a[16]); SQRADDAC(a[11], a[15]); SQRADDAC(a[12], a[14]); SQRADDDB; SQRADD(a[13], a[13]); 
+   COMBA_STORE(b[26]);
+
+   /* output 27 */
+   CARRY_FORWARD;
+   SQRADDSC(a[8], a[19]); SQRADDAC(a[9], a[18]); SQRADDAC(a[10], a[17]); SQRADDAC(a[11], a[16]); SQRADDAC(a[12], a[15]); SQRADDAC(a[13], a[14]); SQRADDDB; 
+   COMBA_STORE(b[27]);
+
+   /* output 28 */
+   CARRY_FORWARD;
+   SQRADDSC(a[9], a[19]); SQRADDAC(a[10], a[18]); SQRADDAC(a[11], a[17]); SQRADDAC(a[12], a[16]); SQRADDAC(a[13], a[15]); SQRADDDB; SQRADD(a[14], a[14]); 
+   COMBA_STORE(b[28]);
+
+   /* output 29 */
+   CARRY_FORWARD;
+   SQRADDSC(a[10], a[19]); SQRADDAC(a[11], a[18]); SQRADDAC(a[12], a[17]); SQRADDAC(a[13], a[16]); SQRADDAC(a[14], a[15]); SQRADDDB; 
+   COMBA_STORE(b[29]);
+
+   /* output 30 */
+   CARRY_FORWARD;
+   SQRADDSC(a[11], a[19]); SQRADDAC(a[12], a[18]); SQRADDAC(a[13], a[17]); SQRADDAC(a[14], a[16]); SQRADDDB; SQRADD(a[15], a[15]); 
+   COMBA_STORE(b[30]);
+
+   /* output 31 */
+   CARRY_FORWARD;
+   SQRADDSC(a[12], a[19]); SQRADDAC(a[13], a[18]); SQRADDAC(a[14], a[17]); SQRADDAC(a[15], a[16]); SQRADDDB; 
+   COMBA_STORE(b[31]);
+
+   /* output 32 */
+   CARRY_FORWARD;
+   SQRADDSC(a[13], a[19]); SQRADDAC(a[14], a[18]); SQRADDAC(a[15], a[17]); SQRADDDB; SQRADD(a[16], a[16]); 
+   COMBA_STORE(b[32]);
+
+   /* output 33 */
+   CARRY_FORWARD;
+   SQRADDSC(a[14], a[19]); SQRADDAC(a[15], a[18]); SQRADDAC(a[16], a[17]); SQRADDDB; 
+   COMBA_STORE(b[33]);
+
+   /* output 34 */
+   CARRY_FORWARD;
+   SQRADD2(a[15], a[19]); SQRADD2(a[16], a[18]); SQRADD(a[17], a[17]); 
+   COMBA_STORE(b[34]);
+
+   /* output 35 */
+   CARRY_FORWARD;
+   SQRADD2(a[16], a[19]); SQRADD2(a[17], a[18]); 
+   COMBA_STORE(b[35]);
+
+   /* output 36 */
+   CARRY_FORWARD;
+   SQRADD2(a[17], a[19]); SQRADD(a[18], a[18]); 
+   COMBA_STORE(b[36]);
+
+   /* output 37 */
+   CARRY_FORWARD;
+   SQRADD2(a[18], a[19]); 
+   COMBA_STORE(b[37]);
+
+   /* output 38 */
+   CARRY_FORWARD;
+   SQRADD(a[19], a[19]); 
+   COMBA_STORE(b[38]);
+   COMBA_STORE2(b[39]);
+   COMBA_FINI;
+
+   B->used = 40;
+   B->sign = FP_ZPOS;
+   memcpy(B->dp, b, 40 * sizeof(fp_digit));
+   fp_clamp(B);
+}
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_24.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_24.i
new file mode 100644
index 0000000..cf512e3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_24.i
@@ -0,0 +1,280 @@
+/* fp_sqr_comba_24.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_SQR24
+void fp_sqr_comba24(fp_int *A, fp_int *B)
+{
+   fp_digit *a, b[48], c0, c1, c2, sc0, sc1, sc2;
+#ifdef TFM_ISO
+   fp_word   tt;   
+#endif   
+
+   a = A->dp;
+   COMBA_START; 
+
+   /* clear carries */
+   CLEAR_CARRY;
+
+   /* output 0 */
+   SQRADD(a[0],a[0]);
+   COMBA_STORE(b[0]);
+
+   /* output 1 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[1]); 
+   COMBA_STORE(b[1]);
+
+   /* output 2 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[2]); SQRADD(a[1], a[1]); 
+   COMBA_STORE(b[2]);
+
+   /* output 3 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[3]); SQRADD2(a[1], a[2]); 
+   COMBA_STORE(b[3]);
+
+   /* output 4 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[4]); SQRADD2(a[1], a[3]); SQRADD(a[2], a[2]); 
+   COMBA_STORE(b[4]);
+
+   /* output 5 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[5]); SQRADDAC(a[1], a[4]); SQRADDAC(a[2], a[3]); SQRADDDB; 
+   COMBA_STORE(b[5]);
+
+   /* output 6 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[6]); SQRADDAC(a[1], a[5]); SQRADDAC(a[2], a[4]); SQRADDDB; SQRADD(a[3], a[3]); 
+   COMBA_STORE(b[6]);
+
+   /* output 7 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[7]); SQRADDAC(a[1], a[6]); SQRADDAC(a[2], a[5]); SQRADDAC(a[3], a[4]); SQRADDDB; 
+   COMBA_STORE(b[7]);
+
+   /* output 8 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[8]); SQRADDAC(a[1], a[7]); SQRADDAC(a[2], a[6]); SQRADDAC(a[3], a[5]); SQRADDDB; SQRADD(a[4], a[4]); 
+   COMBA_STORE(b[8]);
+
+   /* output 9 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[9]); SQRADDAC(a[1], a[8]); SQRADDAC(a[2], a[7]); SQRADDAC(a[3], a[6]); SQRADDAC(a[4], a[5]); SQRADDDB; 
+   COMBA_STORE(b[9]);
+
+   /* output 10 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[10]); SQRADDAC(a[1], a[9]); SQRADDAC(a[2], a[8]); SQRADDAC(a[3], a[7]); SQRADDAC(a[4], a[6]); SQRADDDB; SQRADD(a[5], a[5]); 
+   COMBA_STORE(b[10]);
+
+   /* output 11 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[11]); SQRADDAC(a[1], a[10]); SQRADDAC(a[2], a[9]); SQRADDAC(a[3], a[8]); SQRADDAC(a[4], a[7]); SQRADDAC(a[5], a[6]); SQRADDDB; 
+   COMBA_STORE(b[11]);
+
+   /* output 12 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[12]); SQRADDAC(a[1], a[11]); SQRADDAC(a[2], a[10]); SQRADDAC(a[3], a[9]); SQRADDAC(a[4], a[8]); SQRADDAC(a[5], a[7]); SQRADDDB; SQRADD(a[6], a[6]); 
+   COMBA_STORE(b[12]);
+
+   /* output 13 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[13]); SQRADDAC(a[1], a[12]); SQRADDAC(a[2], a[11]); SQRADDAC(a[3], a[10]); SQRADDAC(a[4], a[9]); SQRADDAC(a[5], a[8]); SQRADDAC(a[6], a[7]); SQRADDDB; 
+   COMBA_STORE(b[13]);
+
+   /* output 14 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[14]); SQRADDAC(a[1], a[13]); SQRADDAC(a[2], a[12]); SQRADDAC(a[3], a[11]); SQRADDAC(a[4], a[10]); SQRADDAC(a[5], a[9]); SQRADDAC(a[6], a[8]); SQRADDDB; SQRADD(a[7], a[7]); 
+   COMBA_STORE(b[14]);
+
+   /* output 15 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[15]); SQRADDAC(a[1], a[14]); SQRADDAC(a[2], a[13]); SQRADDAC(a[3], a[12]); SQRADDAC(a[4], a[11]); SQRADDAC(a[5], a[10]); SQRADDAC(a[6], a[9]); SQRADDAC(a[7], a[8]); SQRADDDB; 
+   COMBA_STORE(b[15]);
+
+   /* output 16 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[16]); SQRADDAC(a[1], a[15]); SQRADDAC(a[2], a[14]); SQRADDAC(a[3], a[13]); SQRADDAC(a[4], a[12]); SQRADDAC(a[5], a[11]); SQRADDAC(a[6], a[10]); SQRADDAC(a[7], a[9]); SQRADDDB; SQRADD(a[8], a[8]); 
+   COMBA_STORE(b[16]);
+
+   /* output 17 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[17]); SQRADDAC(a[1], a[16]); SQRADDAC(a[2], a[15]); SQRADDAC(a[3], a[14]); SQRADDAC(a[4], a[13]); SQRADDAC(a[5], a[12]); SQRADDAC(a[6], a[11]); SQRADDAC(a[7], a[10]); SQRADDAC(a[8], a[9]); SQRADDDB; 
+   COMBA_STORE(b[17]);
+
+   /* output 18 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[18]); SQRADDAC(a[1], a[17]); SQRADDAC(a[2], a[16]); SQRADDAC(a[3], a[15]); SQRADDAC(a[4], a[14]); SQRADDAC(a[5], a[13]); SQRADDAC(a[6], a[12]); SQRADDAC(a[7], a[11]); SQRADDAC(a[8], a[10]); SQRADDDB; SQRADD(a[9], a[9]); 
+   COMBA_STORE(b[18]);
+
+   /* output 19 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[19]); SQRADDAC(a[1], a[18]); SQRADDAC(a[2], a[17]); SQRADDAC(a[3], a[16]); SQRADDAC(a[4], a[15]); SQRADDAC(a[5], a[14]); SQRADDAC(a[6], a[13]); SQRADDAC(a[7], a[12]); SQRADDAC(a[8], a[11]); SQRADDAC(a[9], a[10]); SQRADDDB; 
+   COMBA_STORE(b[19]);
+
+   /* output 20 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[20]); SQRADDAC(a[1], a[19]); SQRADDAC(a[2], a[18]); SQRADDAC(a[3], a[17]); SQRADDAC(a[4], a[16]); SQRADDAC(a[5], a[15]); SQRADDAC(a[6], a[14]); SQRADDAC(a[7], a[13]); SQRADDAC(a[8], a[12]); SQRADDAC(a[9], a[11]); SQRADDDB; SQRADD(a[10], a[10]); 
+   COMBA_STORE(b[20]);
+
+   /* output 21 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[21]); SQRADDAC(a[1], a[20]); SQRADDAC(a[2], a[19]); SQRADDAC(a[3], a[18]); SQRADDAC(a[4], a[17]); SQRADDAC(a[5], a[16]); SQRADDAC(a[6], a[15]); SQRADDAC(a[7], a[14]); SQRADDAC(a[8], a[13]); SQRADDAC(a[9], a[12]); SQRADDAC(a[10], a[11]); SQRADDDB; 
+   COMBA_STORE(b[21]);
+
+   /* output 22 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[22]); SQRADDAC(a[1], a[21]); SQRADDAC(a[2], a[20]); SQRADDAC(a[3], a[19]); SQRADDAC(a[4], a[18]); SQRADDAC(a[5], a[17]); SQRADDAC(a[6], a[16]); SQRADDAC(a[7], a[15]); SQRADDAC(a[8], a[14]); SQRADDAC(a[9], a[13]); SQRADDAC(a[10], a[12]); SQRADDDB; SQRADD(a[11], a[11]); 
+   COMBA_STORE(b[22]);
+
+   /* output 23 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[23]); SQRADDAC(a[1], a[22]); SQRADDAC(a[2], a[21]); SQRADDAC(a[3], a[20]); SQRADDAC(a[4], a[19]); SQRADDAC(a[5], a[18]); SQRADDAC(a[6], a[17]); SQRADDAC(a[7], a[16]); SQRADDAC(a[8], a[15]); SQRADDAC(a[9], a[14]); SQRADDAC(a[10], a[13]); SQRADDAC(a[11], a[12]); SQRADDDB; 
+   COMBA_STORE(b[23]);
+
+   /* output 24 */
+   CARRY_FORWARD;
+   SQRADDSC(a[1], a[23]); SQRADDAC(a[2], a[22]); SQRADDAC(a[3], a[21]); SQRADDAC(a[4], a[20]); SQRADDAC(a[5], a[19]); SQRADDAC(a[6], a[18]); SQRADDAC(a[7], a[17]); SQRADDAC(a[8], a[16]); SQRADDAC(a[9], a[15]); SQRADDAC(a[10], a[14]); SQRADDAC(a[11], a[13]); SQRADDDB; SQRADD(a[12], a[12]); 
+   COMBA_STORE(b[24]);
+
+   /* output 25 */
+   CARRY_FORWARD;
+   SQRADDSC(a[2], a[23]); SQRADDAC(a[3], a[22]); SQRADDAC(a[4], a[21]); SQRADDAC(a[5], a[20]); SQRADDAC(a[6], a[19]); SQRADDAC(a[7], a[18]); SQRADDAC(a[8], a[17]); SQRADDAC(a[9], a[16]); SQRADDAC(a[10], a[15]); SQRADDAC(a[11], a[14]); SQRADDAC(a[12], a[13]); SQRADDDB; 
+   COMBA_STORE(b[25]);
+
+   /* output 26 */
+   CARRY_FORWARD;
+   SQRADDSC(a[3], a[23]); SQRADDAC(a[4], a[22]); SQRADDAC(a[5], a[21]); SQRADDAC(a[6], a[20]); SQRADDAC(a[7], a[19]); SQRADDAC(a[8], a[18]); SQRADDAC(a[9], a[17]); SQRADDAC(a[10], a[16]); SQRADDAC(a[11], a[15]); SQRADDAC(a[12], a[14]); SQRADDDB; SQRADD(a[13], a[13]); 
+   COMBA_STORE(b[26]);
+
+   /* output 27 */
+   CARRY_FORWARD;
+   SQRADDSC(a[4], a[23]); SQRADDAC(a[5], a[22]); SQRADDAC(a[6], a[21]); SQRADDAC(a[7], a[20]); SQRADDAC(a[8], a[19]); SQRADDAC(a[9], a[18]); SQRADDAC(a[10], a[17]); SQRADDAC(a[11], a[16]); SQRADDAC(a[12], a[15]); SQRADDAC(a[13], a[14]); SQRADDDB; 
+   COMBA_STORE(b[27]);
+
+   /* output 28 */
+   CARRY_FORWARD;
+   SQRADDSC(a[5], a[23]); SQRADDAC(a[6], a[22]); SQRADDAC(a[7], a[21]); SQRADDAC(a[8], a[20]); SQRADDAC(a[9], a[19]); SQRADDAC(a[10], a[18]); SQRADDAC(a[11], a[17]); SQRADDAC(a[12], a[16]); SQRADDAC(a[13], a[15]); SQRADDDB; SQRADD(a[14], a[14]); 
+   COMBA_STORE(b[28]);
+
+   /* output 29 */
+   CARRY_FORWARD;
+   SQRADDSC(a[6], a[23]); SQRADDAC(a[7], a[22]); SQRADDAC(a[8], a[21]); SQRADDAC(a[9], a[20]); SQRADDAC(a[10], a[19]); SQRADDAC(a[11], a[18]); SQRADDAC(a[12], a[17]); SQRADDAC(a[13], a[16]); SQRADDAC(a[14], a[15]); SQRADDDB; 
+   COMBA_STORE(b[29]);
+
+   /* output 30 */
+   CARRY_FORWARD;
+   SQRADDSC(a[7], a[23]); SQRADDAC(a[8], a[22]); SQRADDAC(a[9], a[21]); SQRADDAC(a[10], a[20]); SQRADDAC(a[11], a[19]); SQRADDAC(a[12], a[18]); SQRADDAC(a[13], a[17]); SQRADDAC(a[14], a[16]); SQRADDDB; SQRADD(a[15], a[15]); 
+   COMBA_STORE(b[30]);
+
+   /* output 31 */
+   CARRY_FORWARD;
+   SQRADDSC(a[8], a[23]); SQRADDAC(a[9], a[22]); SQRADDAC(a[10], a[21]); SQRADDAC(a[11], a[20]); SQRADDAC(a[12], a[19]); SQRADDAC(a[13], a[18]); SQRADDAC(a[14], a[17]); SQRADDAC(a[15], a[16]); SQRADDDB; 
+   COMBA_STORE(b[31]);
+
+   /* output 32 */
+   CARRY_FORWARD;
+   SQRADDSC(a[9], a[23]); SQRADDAC(a[10], a[22]); SQRADDAC(a[11], a[21]); SQRADDAC(a[12], a[20]); SQRADDAC(a[13], a[19]); SQRADDAC(a[14], a[18]); SQRADDAC(a[15], a[17]); SQRADDDB; SQRADD(a[16], a[16]); 
+   COMBA_STORE(b[32]);
+
+   /* output 33 */
+   CARRY_FORWARD;
+   SQRADDSC(a[10], a[23]); SQRADDAC(a[11], a[22]); SQRADDAC(a[12], a[21]); SQRADDAC(a[13], a[20]); SQRADDAC(a[14], a[19]); SQRADDAC(a[15], a[18]); SQRADDAC(a[16], a[17]); SQRADDDB; 
+   COMBA_STORE(b[33]);
+
+   /* output 34 */
+   CARRY_FORWARD;
+   SQRADDSC(a[11], a[23]); SQRADDAC(a[12], a[22]); SQRADDAC(a[13], a[21]); SQRADDAC(a[14], a[20]); SQRADDAC(a[15], a[19]); SQRADDAC(a[16], a[18]); SQRADDDB; SQRADD(a[17], a[17]); 
+   COMBA_STORE(b[34]);
+
+   /* output 35 */
+   CARRY_FORWARD;
+   SQRADDSC(a[12], a[23]); SQRADDAC(a[13], a[22]); SQRADDAC(a[14], a[21]); SQRADDAC(a[15], a[20]); SQRADDAC(a[16], a[19]); SQRADDAC(a[17], a[18]); SQRADDDB; 
+   COMBA_STORE(b[35]);
+
+   /* output 36 */
+   CARRY_FORWARD;
+   SQRADDSC(a[13], a[23]); SQRADDAC(a[14], a[22]); SQRADDAC(a[15], a[21]); SQRADDAC(a[16], a[20]); SQRADDAC(a[17], a[19]); SQRADDDB; SQRADD(a[18], a[18]); 
+   COMBA_STORE(b[36]);
+
+   /* output 37 */
+   CARRY_FORWARD;
+   SQRADDSC(a[14], a[23]); SQRADDAC(a[15], a[22]); SQRADDAC(a[16], a[21]); SQRADDAC(a[17], a[20]); SQRADDAC(a[18], a[19]); SQRADDDB; 
+   COMBA_STORE(b[37]);
+
+   /* output 38 */
+   CARRY_FORWARD;
+   SQRADDSC(a[15], a[23]); SQRADDAC(a[16], a[22]); SQRADDAC(a[17], a[21]); SQRADDAC(a[18], a[20]); SQRADDDB; SQRADD(a[19], a[19]); 
+   COMBA_STORE(b[38]);
+
+   /* output 39 */
+   CARRY_FORWARD;
+   SQRADDSC(a[16], a[23]); SQRADDAC(a[17], a[22]); SQRADDAC(a[18], a[21]); SQRADDAC(a[19], a[20]); SQRADDDB; 
+   COMBA_STORE(b[39]);
+
+   /* output 40 */
+   CARRY_FORWARD;
+   SQRADDSC(a[17], a[23]); SQRADDAC(a[18], a[22]); SQRADDAC(a[19], a[21]); SQRADDDB; SQRADD(a[20], a[20]); 
+   COMBA_STORE(b[40]);
+
+   /* output 41 */
+   CARRY_FORWARD;
+   SQRADDSC(a[18], a[23]); SQRADDAC(a[19], a[22]); SQRADDAC(a[20], a[21]); SQRADDDB; 
+   COMBA_STORE(b[41]);
+
+   /* output 42 */
+   CARRY_FORWARD;
+   SQRADD2(a[19], a[23]); SQRADD2(a[20], a[22]); SQRADD(a[21], a[21]); 
+   COMBA_STORE(b[42]);
+
+   /* output 43 */
+   CARRY_FORWARD;
+   SQRADD2(a[20], a[23]); SQRADD2(a[21], a[22]); 
+   COMBA_STORE(b[43]);
+
+   /* output 44 */
+   CARRY_FORWARD;
+   SQRADD2(a[21], a[23]); SQRADD(a[22], a[22]); 
+   COMBA_STORE(b[44]);
+
+   /* output 45 */
+   CARRY_FORWARD;
+   SQRADD2(a[22], a[23]); 
+   COMBA_STORE(b[45]);
+
+   /* output 46 */
+   CARRY_FORWARD;
+   SQRADD(a[23], a[23]); 
+   COMBA_STORE(b[46]);
+   COMBA_STORE2(b[47]);
+   COMBA_FINI;
+
+   B->used = 48;
+   B->sign = FP_ZPOS;
+   memcpy(B->dp, b, 48 * sizeof(fp_digit));
+   fp_clamp(B);
+}
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_28.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_28.i
new file mode 100644
index 0000000..08e9bc4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_28.i
@@ -0,0 +1,320 @@
+/* fp_sqr_comba_28.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_SQR28
+void fp_sqr_comba28(fp_int *A, fp_int *B)
+{
+   fp_digit *a, b[56], c0, c1, c2, sc0, sc1, sc2;
+#ifdef TFM_ISO
+   fp_word   tt;   
+#endif   
+
+   a = A->dp;
+   COMBA_START; 
+
+   /* clear carries */
+   CLEAR_CARRY;
+
+   /* output 0 */
+   SQRADD(a[0],a[0]);
+   COMBA_STORE(b[0]);
+
+   /* output 1 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[1]); 
+   COMBA_STORE(b[1]);
+
+   /* output 2 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[2]); SQRADD(a[1], a[1]); 
+   COMBA_STORE(b[2]);
+
+   /* output 3 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[3]); SQRADD2(a[1], a[2]); 
+   COMBA_STORE(b[3]);
+
+   /* output 4 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[4]); SQRADD2(a[1], a[3]); SQRADD(a[2], a[2]); 
+   COMBA_STORE(b[4]);
+
+   /* output 5 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[5]); SQRADDAC(a[1], a[4]); SQRADDAC(a[2], a[3]); SQRADDDB; 
+   COMBA_STORE(b[5]);
+
+   /* output 6 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[6]); SQRADDAC(a[1], a[5]); SQRADDAC(a[2], a[4]); SQRADDDB; SQRADD(a[3], a[3]); 
+   COMBA_STORE(b[6]);
+
+   /* output 7 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[7]); SQRADDAC(a[1], a[6]); SQRADDAC(a[2], a[5]); SQRADDAC(a[3], a[4]); SQRADDDB; 
+   COMBA_STORE(b[7]);
+
+   /* output 8 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[8]); SQRADDAC(a[1], a[7]); SQRADDAC(a[2], a[6]); SQRADDAC(a[3], a[5]); SQRADDDB; SQRADD(a[4], a[4]); 
+   COMBA_STORE(b[8]);
+
+   /* output 9 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[9]); SQRADDAC(a[1], a[8]); SQRADDAC(a[2], a[7]); SQRADDAC(a[3], a[6]); SQRADDAC(a[4], a[5]); SQRADDDB; 
+   COMBA_STORE(b[9]);
+
+   /* output 10 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[10]); SQRADDAC(a[1], a[9]); SQRADDAC(a[2], a[8]); SQRADDAC(a[3], a[7]); SQRADDAC(a[4], a[6]); SQRADDDB; SQRADD(a[5], a[5]); 
+   COMBA_STORE(b[10]);
+
+   /* output 11 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[11]); SQRADDAC(a[1], a[10]); SQRADDAC(a[2], a[9]); SQRADDAC(a[3], a[8]); SQRADDAC(a[4], a[7]); SQRADDAC(a[5], a[6]); SQRADDDB; 
+   COMBA_STORE(b[11]);
+
+   /* output 12 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[12]); SQRADDAC(a[1], a[11]); SQRADDAC(a[2], a[10]); SQRADDAC(a[3], a[9]); SQRADDAC(a[4], a[8]); SQRADDAC(a[5], a[7]); SQRADDDB; SQRADD(a[6], a[6]); 
+   COMBA_STORE(b[12]);
+
+   /* output 13 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[13]); SQRADDAC(a[1], a[12]); SQRADDAC(a[2], a[11]); SQRADDAC(a[3], a[10]); SQRADDAC(a[4], a[9]); SQRADDAC(a[5], a[8]); SQRADDAC(a[6], a[7]); SQRADDDB; 
+   COMBA_STORE(b[13]);
+
+   /* output 14 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[14]); SQRADDAC(a[1], a[13]); SQRADDAC(a[2], a[12]); SQRADDAC(a[3], a[11]); SQRADDAC(a[4], a[10]); SQRADDAC(a[5], a[9]); SQRADDAC(a[6], a[8]); SQRADDDB; SQRADD(a[7], a[7]); 
+   COMBA_STORE(b[14]);
+
+   /* output 15 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[15]); SQRADDAC(a[1], a[14]); SQRADDAC(a[2], a[13]); SQRADDAC(a[3], a[12]); SQRADDAC(a[4], a[11]); SQRADDAC(a[5], a[10]); SQRADDAC(a[6], a[9]); SQRADDAC(a[7], a[8]); SQRADDDB; 
+   COMBA_STORE(b[15]);
+
+   /* output 16 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[16]); SQRADDAC(a[1], a[15]); SQRADDAC(a[2], a[14]); SQRADDAC(a[3], a[13]); SQRADDAC(a[4], a[12]); SQRADDAC(a[5], a[11]); SQRADDAC(a[6], a[10]); SQRADDAC(a[7], a[9]); SQRADDDB; SQRADD(a[8], a[8]); 
+   COMBA_STORE(b[16]);
+
+   /* output 17 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[17]); SQRADDAC(a[1], a[16]); SQRADDAC(a[2], a[15]); SQRADDAC(a[3], a[14]); SQRADDAC(a[4], a[13]); SQRADDAC(a[5], a[12]); SQRADDAC(a[6], a[11]); SQRADDAC(a[7], a[10]); SQRADDAC(a[8], a[9]); SQRADDDB; 
+   COMBA_STORE(b[17]);
+
+   /* output 18 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[18]); SQRADDAC(a[1], a[17]); SQRADDAC(a[2], a[16]); SQRADDAC(a[3], a[15]); SQRADDAC(a[4], a[14]); SQRADDAC(a[5], a[13]); SQRADDAC(a[6], a[12]); SQRADDAC(a[7], a[11]); SQRADDAC(a[8], a[10]); SQRADDDB; SQRADD(a[9], a[9]); 
+   COMBA_STORE(b[18]);
+
+   /* output 19 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[19]); SQRADDAC(a[1], a[18]); SQRADDAC(a[2], a[17]); SQRADDAC(a[3], a[16]); SQRADDAC(a[4], a[15]); SQRADDAC(a[5], a[14]); SQRADDAC(a[6], a[13]); SQRADDAC(a[7], a[12]); SQRADDAC(a[8], a[11]); SQRADDAC(a[9], a[10]); SQRADDDB; 
+   COMBA_STORE(b[19]);
+
+   /* output 20 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[20]); SQRADDAC(a[1], a[19]); SQRADDAC(a[2], a[18]); SQRADDAC(a[3], a[17]); SQRADDAC(a[4], a[16]); SQRADDAC(a[5], a[15]); SQRADDAC(a[6], a[14]); SQRADDAC(a[7], a[13]); SQRADDAC(a[8], a[12]); SQRADDAC(a[9], a[11]); SQRADDDB; SQRADD(a[10], a[10]); 
+   COMBA_STORE(b[20]);
+
+   /* output 21 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[21]); SQRADDAC(a[1], a[20]); SQRADDAC(a[2], a[19]); SQRADDAC(a[3], a[18]); SQRADDAC(a[4], a[17]); SQRADDAC(a[5], a[16]); SQRADDAC(a[6], a[15]); SQRADDAC(a[7], a[14]); SQRADDAC(a[8], a[13]); SQRADDAC(a[9], a[12]); SQRADDAC(a[10], a[11]); SQRADDDB; 
+   COMBA_STORE(b[21]);
+
+   /* output 22 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[22]); SQRADDAC(a[1], a[21]); SQRADDAC(a[2], a[20]); SQRADDAC(a[3], a[19]); SQRADDAC(a[4], a[18]); SQRADDAC(a[5], a[17]); SQRADDAC(a[6], a[16]); SQRADDAC(a[7], a[15]); SQRADDAC(a[8], a[14]); SQRADDAC(a[9], a[13]); SQRADDAC(a[10], a[12]); SQRADDDB; SQRADD(a[11], a[11]); 
+   COMBA_STORE(b[22]);
+
+   /* output 23 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[23]); SQRADDAC(a[1], a[22]); SQRADDAC(a[2], a[21]); SQRADDAC(a[3], a[20]); SQRADDAC(a[4], a[19]); SQRADDAC(a[5], a[18]); SQRADDAC(a[6], a[17]); SQRADDAC(a[7], a[16]); SQRADDAC(a[8], a[15]); SQRADDAC(a[9], a[14]); SQRADDAC(a[10], a[13]); SQRADDAC(a[11], a[12]); SQRADDDB; 
+   COMBA_STORE(b[23]);
+
+   /* output 24 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[24]); SQRADDAC(a[1], a[23]); SQRADDAC(a[2], a[22]); SQRADDAC(a[3], a[21]); SQRADDAC(a[4], a[20]); SQRADDAC(a[5], a[19]); SQRADDAC(a[6], a[18]); SQRADDAC(a[7], a[17]); SQRADDAC(a[8], a[16]); SQRADDAC(a[9], a[15]); SQRADDAC(a[10], a[14]); SQRADDAC(a[11], a[13]); SQRADDDB; SQRADD(a[12], a[12]); 
+   COMBA_STORE(b[24]);
+
+   /* output 25 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[25]); SQRADDAC(a[1], a[24]); SQRADDAC(a[2], a[23]); SQRADDAC(a[3], a[22]); SQRADDAC(a[4], a[21]); SQRADDAC(a[5], a[20]); SQRADDAC(a[6], a[19]); SQRADDAC(a[7], a[18]); SQRADDAC(a[8], a[17]); SQRADDAC(a[9], a[16]); SQRADDAC(a[10], a[15]); SQRADDAC(a[11], a[14]); SQRADDAC(a[12], a[13]); SQRADDDB; 
+   COMBA_STORE(b[25]);
+
+   /* output 26 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[26]); SQRADDAC(a[1], a[25]); SQRADDAC(a[2], a[24]); SQRADDAC(a[3], a[23]); SQRADDAC(a[4], a[22]); SQRADDAC(a[5], a[21]); SQRADDAC(a[6], a[20]); SQRADDAC(a[7], a[19]); SQRADDAC(a[8], a[18]); SQRADDAC(a[9], a[17]); SQRADDAC(a[10], a[16]); SQRADDAC(a[11], a[15]); SQRADDAC(a[12], a[14]); SQRADDDB; SQRADD(a[13], a[13]); 
+   COMBA_STORE(b[26]);
+
+   /* output 27 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[27]); SQRADDAC(a[1], a[26]); SQRADDAC(a[2], a[25]); SQRADDAC(a[3], a[24]); SQRADDAC(a[4], a[23]); SQRADDAC(a[5], a[22]); SQRADDAC(a[6], a[21]); SQRADDAC(a[7], a[20]); SQRADDAC(a[8], a[19]); SQRADDAC(a[9], a[18]); SQRADDAC(a[10], a[17]); SQRADDAC(a[11], a[16]); SQRADDAC(a[12], a[15]); SQRADDAC(a[13], a[14]); SQRADDDB; 
+   COMBA_STORE(b[27]);
+
+   /* output 28 */
+   CARRY_FORWARD;
+   SQRADDSC(a[1], a[27]); SQRADDAC(a[2], a[26]); SQRADDAC(a[3], a[25]); SQRADDAC(a[4], a[24]); SQRADDAC(a[5], a[23]); SQRADDAC(a[6], a[22]); SQRADDAC(a[7], a[21]); SQRADDAC(a[8], a[20]); SQRADDAC(a[9], a[19]); SQRADDAC(a[10], a[18]); SQRADDAC(a[11], a[17]); SQRADDAC(a[12], a[16]); SQRADDAC(a[13], a[15]); SQRADDDB; SQRADD(a[14], a[14]); 
+   COMBA_STORE(b[28]);
+
+   /* output 29 */
+   CARRY_FORWARD;
+   SQRADDSC(a[2], a[27]); SQRADDAC(a[3], a[26]); SQRADDAC(a[4], a[25]); SQRADDAC(a[5], a[24]); SQRADDAC(a[6], a[23]); SQRADDAC(a[7], a[22]); SQRADDAC(a[8], a[21]); SQRADDAC(a[9], a[20]); SQRADDAC(a[10], a[19]); SQRADDAC(a[11], a[18]); SQRADDAC(a[12], a[17]); SQRADDAC(a[13], a[16]); SQRADDAC(a[14], a[15]); SQRADDDB; 
+   COMBA_STORE(b[29]);
+
+   /* output 30 */
+   CARRY_FORWARD;
+   SQRADDSC(a[3], a[27]); SQRADDAC(a[4], a[26]); SQRADDAC(a[5], a[25]); SQRADDAC(a[6], a[24]); SQRADDAC(a[7], a[23]); SQRADDAC(a[8], a[22]); SQRADDAC(a[9], a[21]); SQRADDAC(a[10], a[20]); SQRADDAC(a[11], a[19]); SQRADDAC(a[12], a[18]); SQRADDAC(a[13], a[17]); SQRADDAC(a[14], a[16]); SQRADDDB; SQRADD(a[15], a[15]); 
+   COMBA_STORE(b[30]);
+
+   /* output 31 */
+   CARRY_FORWARD;
+   SQRADDSC(a[4], a[27]); SQRADDAC(a[5], a[26]); SQRADDAC(a[6], a[25]); SQRADDAC(a[7], a[24]); SQRADDAC(a[8], a[23]); SQRADDAC(a[9], a[22]); SQRADDAC(a[10], a[21]); SQRADDAC(a[11], a[20]); SQRADDAC(a[12], a[19]); SQRADDAC(a[13], a[18]); SQRADDAC(a[14], a[17]); SQRADDAC(a[15], a[16]); SQRADDDB; 
+   COMBA_STORE(b[31]);
+
+   /* output 32 */
+   CARRY_FORWARD;
+   SQRADDSC(a[5], a[27]); SQRADDAC(a[6], a[26]); SQRADDAC(a[7], a[25]); SQRADDAC(a[8], a[24]); SQRADDAC(a[9], a[23]); SQRADDAC(a[10], a[22]); SQRADDAC(a[11], a[21]); SQRADDAC(a[12], a[20]); SQRADDAC(a[13], a[19]); SQRADDAC(a[14], a[18]); SQRADDAC(a[15], a[17]); SQRADDDB; SQRADD(a[16], a[16]); 
+   COMBA_STORE(b[32]);
+
+   /* output 33 */
+   CARRY_FORWARD;
+   SQRADDSC(a[6], a[27]); SQRADDAC(a[7], a[26]); SQRADDAC(a[8], a[25]); SQRADDAC(a[9], a[24]); SQRADDAC(a[10], a[23]); SQRADDAC(a[11], a[22]); SQRADDAC(a[12], a[21]); SQRADDAC(a[13], a[20]); SQRADDAC(a[14], a[19]); SQRADDAC(a[15], a[18]); SQRADDAC(a[16], a[17]); SQRADDDB; 
+   COMBA_STORE(b[33]);
+
+   /* output 34 */
+   CARRY_FORWARD;
+   SQRADDSC(a[7], a[27]); SQRADDAC(a[8], a[26]); SQRADDAC(a[9], a[25]); SQRADDAC(a[10], a[24]); SQRADDAC(a[11], a[23]); SQRADDAC(a[12], a[22]); SQRADDAC(a[13], a[21]); SQRADDAC(a[14], a[20]); SQRADDAC(a[15], a[19]); SQRADDAC(a[16], a[18]); SQRADDDB; SQRADD(a[17], a[17]); 
+   COMBA_STORE(b[34]);
+
+   /* output 35 */
+   CARRY_FORWARD;
+   SQRADDSC(a[8], a[27]); SQRADDAC(a[9], a[26]); SQRADDAC(a[10], a[25]); SQRADDAC(a[11], a[24]); SQRADDAC(a[12], a[23]); SQRADDAC(a[13], a[22]); SQRADDAC(a[14], a[21]); SQRADDAC(a[15], a[20]); SQRADDAC(a[16], a[19]); SQRADDAC(a[17], a[18]); SQRADDDB; 
+   COMBA_STORE(b[35]);
+
+   /* output 36 */
+   CARRY_FORWARD;
+   SQRADDSC(a[9], a[27]); SQRADDAC(a[10], a[26]); SQRADDAC(a[11], a[25]); SQRADDAC(a[12], a[24]); SQRADDAC(a[13], a[23]); SQRADDAC(a[14], a[22]); SQRADDAC(a[15], a[21]); SQRADDAC(a[16], a[20]); SQRADDAC(a[17], a[19]); SQRADDDB; SQRADD(a[18], a[18]); 
+   COMBA_STORE(b[36]);
+
+   /* output 37 */
+   CARRY_FORWARD;
+   SQRADDSC(a[10], a[27]); SQRADDAC(a[11], a[26]); SQRADDAC(a[12], a[25]); SQRADDAC(a[13], a[24]); SQRADDAC(a[14], a[23]); SQRADDAC(a[15], a[22]); SQRADDAC(a[16], a[21]); SQRADDAC(a[17], a[20]); SQRADDAC(a[18], a[19]); SQRADDDB; 
+   COMBA_STORE(b[37]);
+
+   /* output 38 */
+   CARRY_FORWARD;
+   SQRADDSC(a[11], a[27]); SQRADDAC(a[12], a[26]); SQRADDAC(a[13], a[25]); SQRADDAC(a[14], a[24]); SQRADDAC(a[15], a[23]); SQRADDAC(a[16], a[22]); SQRADDAC(a[17], a[21]); SQRADDAC(a[18], a[20]); SQRADDDB; SQRADD(a[19], a[19]); 
+   COMBA_STORE(b[38]);
+
+   /* output 39 */
+   CARRY_FORWARD;
+   SQRADDSC(a[12], a[27]); SQRADDAC(a[13], a[26]); SQRADDAC(a[14], a[25]); SQRADDAC(a[15], a[24]); SQRADDAC(a[16], a[23]); SQRADDAC(a[17], a[22]); SQRADDAC(a[18], a[21]); SQRADDAC(a[19], a[20]); SQRADDDB; 
+   COMBA_STORE(b[39]);
+
+   /* output 40 */
+   CARRY_FORWARD;
+   SQRADDSC(a[13], a[27]); SQRADDAC(a[14], a[26]); SQRADDAC(a[15], a[25]); SQRADDAC(a[16], a[24]); SQRADDAC(a[17], a[23]); SQRADDAC(a[18], a[22]); SQRADDAC(a[19], a[21]); SQRADDDB; SQRADD(a[20], a[20]); 
+   COMBA_STORE(b[40]);
+
+   /* output 41 */
+   CARRY_FORWARD;
+   SQRADDSC(a[14], a[27]); SQRADDAC(a[15], a[26]); SQRADDAC(a[16], a[25]); SQRADDAC(a[17], a[24]); SQRADDAC(a[18], a[23]); SQRADDAC(a[19], a[22]); SQRADDAC(a[20], a[21]); SQRADDDB; 
+   COMBA_STORE(b[41]);
+
+   /* output 42 */
+   CARRY_FORWARD;
+   SQRADDSC(a[15], a[27]); SQRADDAC(a[16], a[26]); SQRADDAC(a[17], a[25]); SQRADDAC(a[18], a[24]); SQRADDAC(a[19], a[23]); SQRADDAC(a[20], a[22]); SQRADDDB; SQRADD(a[21], a[21]); 
+   COMBA_STORE(b[42]);
+
+   /* output 43 */
+   CARRY_FORWARD;
+   SQRADDSC(a[16], a[27]); SQRADDAC(a[17], a[26]); SQRADDAC(a[18], a[25]); SQRADDAC(a[19], a[24]); SQRADDAC(a[20], a[23]); SQRADDAC(a[21], a[22]); SQRADDDB; 
+   COMBA_STORE(b[43]);
+
+   /* output 44 */
+   CARRY_FORWARD;
+   SQRADDSC(a[17], a[27]); SQRADDAC(a[18], a[26]); SQRADDAC(a[19], a[25]); SQRADDAC(a[20], a[24]); SQRADDAC(a[21], a[23]); SQRADDDB; SQRADD(a[22], a[22]); 
+   COMBA_STORE(b[44]);
+
+   /* output 45 */
+   CARRY_FORWARD;
+   SQRADDSC(a[18], a[27]); SQRADDAC(a[19], a[26]); SQRADDAC(a[20], a[25]); SQRADDAC(a[21], a[24]); SQRADDAC(a[22], a[23]); SQRADDDB; 
+   COMBA_STORE(b[45]);
+
+   /* output 46 */
+   CARRY_FORWARD;
+   SQRADDSC(a[19], a[27]); SQRADDAC(a[20], a[26]); SQRADDAC(a[21], a[25]); SQRADDAC(a[22], a[24]); SQRADDDB; SQRADD(a[23], a[23]); 
+   COMBA_STORE(b[46]);
+
+   /* output 47 */
+   CARRY_FORWARD;
+   SQRADDSC(a[20], a[27]); SQRADDAC(a[21], a[26]); SQRADDAC(a[22], a[25]); SQRADDAC(a[23], a[24]); SQRADDDB; 
+   COMBA_STORE(b[47]);
+
+   /* output 48 */
+   CARRY_FORWARD;
+   SQRADDSC(a[21], a[27]); SQRADDAC(a[22], a[26]); SQRADDAC(a[23], a[25]); SQRADDDB; SQRADD(a[24], a[24]); 
+   COMBA_STORE(b[48]);
+
+   /* output 49 */
+   CARRY_FORWARD;
+   SQRADDSC(a[22], a[27]); SQRADDAC(a[23], a[26]); SQRADDAC(a[24], a[25]); SQRADDDB; 
+   COMBA_STORE(b[49]);
+
+   /* output 50 */
+   CARRY_FORWARD;
+   SQRADD2(a[23], a[27]); SQRADD2(a[24], a[26]); SQRADD(a[25], a[25]); 
+   COMBA_STORE(b[50]);
+
+   /* output 51 */
+   CARRY_FORWARD;
+   SQRADD2(a[24], a[27]); SQRADD2(a[25], a[26]); 
+   COMBA_STORE(b[51]);
+
+   /* output 52 */
+   CARRY_FORWARD;
+   SQRADD2(a[25], a[27]); SQRADD(a[26], a[26]); 
+   COMBA_STORE(b[52]);
+
+   /* output 53 */
+   CARRY_FORWARD;
+   SQRADD2(a[26], a[27]); 
+   COMBA_STORE(b[53]);
+
+   /* output 54 */
+   CARRY_FORWARD;
+   SQRADD(a[27], a[27]); 
+   COMBA_STORE(b[54]);
+   COMBA_STORE2(b[55]);
+   COMBA_FINI;
+
+   B->used = 56;
+   B->sign = FP_ZPOS;
+   memcpy(B->dp, b, 56 * sizeof(fp_digit));
+   fp_clamp(B);
+}
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_3.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_3.i
new file mode 100644
index 0000000..b475409
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_3.i
@@ -0,0 +1,70 @@
+/* fp_sqr_comba_3.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_SQR3
+void fp_sqr_comba3(fp_int *A, fp_int *B)
+{
+   fp_digit *a, b[6], c0, c1, c2;
+#ifdef TFM_ISO
+   fp_word tt;
+#endif
+
+   a = A->dp;
+   COMBA_START; 
+
+   /* clear carries */
+   CLEAR_CARRY;
+
+   /* output 0 */
+   SQRADD(a[0],a[0]);
+   COMBA_STORE(b[0]);
+
+   /* output 1 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[1]); 
+   COMBA_STORE(b[1]);
+
+   /* output 2 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[2]); SQRADD(a[1], a[1]); 
+   COMBA_STORE(b[2]);
+
+   /* output 3 */
+   CARRY_FORWARD;
+   SQRADD2(a[1], a[2]); 
+   COMBA_STORE(b[3]);
+
+   /* output 4 */
+   CARRY_FORWARD;
+   SQRADD(a[2], a[2]); 
+   COMBA_STORE(b[4]);
+   COMBA_STORE2(b[5]);
+   COMBA_FINI;
+
+   B->used = 6;
+   B->sign = FP_ZPOS;
+   memcpy(B->dp, b, 6 * sizeof(fp_digit));
+   fp_clamp(B);
+}
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_32.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_32.i
new file mode 100644
index 0000000..4a35d74
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_32.i
@@ -0,0 +1,360 @@
+/* fp_sqr_comba_32.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_SQR32
+void fp_sqr_comba32(fp_int *A, fp_int *B)
+{
+   fp_digit *a, b[64], c0, c1, c2, sc0, sc1, sc2;
+#ifdef TFM_ISO
+   fp_word   tt;   
+#endif   
+
+   a = A->dp;
+   COMBA_START; 
+
+   /* clear carries */
+   CLEAR_CARRY;
+
+   /* output 0 */
+   SQRADD(a[0],a[0]);
+   COMBA_STORE(b[0]);
+
+   /* output 1 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[1]); 
+   COMBA_STORE(b[1]);
+
+   /* output 2 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[2]); SQRADD(a[1], a[1]); 
+   COMBA_STORE(b[2]);
+
+   /* output 3 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[3]); SQRADD2(a[1], a[2]); 
+   COMBA_STORE(b[3]);
+
+   /* output 4 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[4]); SQRADD2(a[1], a[3]); SQRADD(a[2], a[2]); 
+   COMBA_STORE(b[4]);
+
+   /* output 5 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[5]); SQRADDAC(a[1], a[4]); SQRADDAC(a[2], a[3]); SQRADDDB; 
+   COMBA_STORE(b[5]);
+
+   /* output 6 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[6]); SQRADDAC(a[1], a[5]); SQRADDAC(a[2], a[4]); SQRADDDB; SQRADD(a[3], a[3]); 
+   COMBA_STORE(b[6]);
+
+   /* output 7 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[7]); SQRADDAC(a[1], a[6]); SQRADDAC(a[2], a[5]); SQRADDAC(a[3], a[4]); SQRADDDB; 
+   COMBA_STORE(b[7]);
+
+   /* output 8 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[8]); SQRADDAC(a[1], a[7]); SQRADDAC(a[2], a[6]); SQRADDAC(a[3], a[5]); SQRADDDB; SQRADD(a[4], a[4]); 
+   COMBA_STORE(b[8]);
+
+   /* output 9 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[9]); SQRADDAC(a[1], a[8]); SQRADDAC(a[2], a[7]); SQRADDAC(a[3], a[6]); SQRADDAC(a[4], a[5]); SQRADDDB; 
+   COMBA_STORE(b[9]);
+
+   /* output 10 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[10]); SQRADDAC(a[1], a[9]); SQRADDAC(a[2], a[8]); SQRADDAC(a[3], a[7]); SQRADDAC(a[4], a[6]); SQRADDDB; SQRADD(a[5], a[5]); 
+   COMBA_STORE(b[10]);
+
+   /* output 11 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[11]); SQRADDAC(a[1], a[10]); SQRADDAC(a[2], a[9]); SQRADDAC(a[3], a[8]); SQRADDAC(a[4], a[7]); SQRADDAC(a[5], a[6]); SQRADDDB; 
+   COMBA_STORE(b[11]);
+
+   /* output 12 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[12]); SQRADDAC(a[1], a[11]); SQRADDAC(a[2], a[10]); SQRADDAC(a[3], a[9]); SQRADDAC(a[4], a[8]); SQRADDAC(a[5], a[7]); SQRADDDB; SQRADD(a[6], a[6]); 
+   COMBA_STORE(b[12]);
+
+   /* output 13 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[13]); SQRADDAC(a[1], a[12]); SQRADDAC(a[2], a[11]); SQRADDAC(a[3], a[10]); SQRADDAC(a[4], a[9]); SQRADDAC(a[5], a[8]); SQRADDAC(a[6], a[7]); SQRADDDB; 
+   COMBA_STORE(b[13]);
+
+   /* output 14 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[14]); SQRADDAC(a[1], a[13]); SQRADDAC(a[2], a[12]); SQRADDAC(a[3], a[11]); SQRADDAC(a[4], a[10]); SQRADDAC(a[5], a[9]); SQRADDAC(a[6], a[8]); SQRADDDB; SQRADD(a[7], a[7]); 
+   COMBA_STORE(b[14]);
+
+   /* output 15 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[15]); SQRADDAC(a[1], a[14]); SQRADDAC(a[2], a[13]); SQRADDAC(a[3], a[12]); SQRADDAC(a[4], a[11]); SQRADDAC(a[5], a[10]); SQRADDAC(a[6], a[9]); SQRADDAC(a[7], a[8]); SQRADDDB; 
+   COMBA_STORE(b[15]);
+
+   /* output 16 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[16]); SQRADDAC(a[1], a[15]); SQRADDAC(a[2], a[14]); SQRADDAC(a[3], a[13]); SQRADDAC(a[4], a[12]); SQRADDAC(a[5], a[11]); SQRADDAC(a[6], a[10]); SQRADDAC(a[7], a[9]); SQRADDDB; SQRADD(a[8], a[8]); 
+   COMBA_STORE(b[16]);
+
+   /* output 17 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[17]); SQRADDAC(a[1], a[16]); SQRADDAC(a[2], a[15]); SQRADDAC(a[3], a[14]); SQRADDAC(a[4], a[13]); SQRADDAC(a[5], a[12]); SQRADDAC(a[6], a[11]); SQRADDAC(a[7], a[10]); SQRADDAC(a[8], a[9]); SQRADDDB; 
+   COMBA_STORE(b[17]);
+
+   /* output 18 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[18]); SQRADDAC(a[1], a[17]); SQRADDAC(a[2], a[16]); SQRADDAC(a[3], a[15]); SQRADDAC(a[4], a[14]); SQRADDAC(a[5], a[13]); SQRADDAC(a[6], a[12]); SQRADDAC(a[7], a[11]); SQRADDAC(a[8], a[10]); SQRADDDB; SQRADD(a[9], a[9]); 
+   COMBA_STORE(b[18]);
+
+   /* output 19 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[19]); SQRADDAC(a[1], a[18]); SQRADDAC(a[2], a[17]); SQRADDAC(a[3], a[16]); SQRADDAC(a[4], a[15]); SQRADDAC(a[5], a[14]); SQRADDAC(a[6], a[13]); SQRADDAC(a[7], a[12]); SQRADDAC(a[8], a[11]); SQRADDAC(a[9], a[10]); SQRADDDB; 
+   COMBA_STORE(b[19]);
+
+   /* output 20 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[20]); SQRADDAC(a[1], a[19]); SQRADDAC(a[2], a[18]); SQRADDAC(a[3], a[17]); SQRADDAC(a[4], a[16]); SQRADDAC(a[5], a[15]); SQRADDAC(a[6], a[14]); SQRADDAC(a[7], a[13]); SQRADDAC(a[8], a[12]); SQRADDAC(a[9], a[11]); SQRADDDB; SQRADD(a[10], a[10]); 
+   COMBA_STORE(b[20]);
+
+   /* output 21 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[21]); SQRADDAC(a[1], a[20]); SQRADDAC(a[2], a[19]); SQRADDAC(a[3], a[18]); SQRADDAC(a[4], a[17]); SQRADDAC(a[5], a[16]); SQRADDAC(a[6], a[15]); SQRADDAC(a[7], a[14]); SQRADDAC(a[8], a[13]); SQRADDAC(a[9], a[12]); SQRADDAC(a[10], a[11]); SQRADDDB; 
+   COMBA_STORE(b[21]);
+
+   /* output 22 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[22]); SQRADDAC(a[1], a[21]); SQRADDAC(a[2], a[20]); SQRADDAC(a[3], a[19]); SQRADDAC(a[4], a[18]); SQRADDAC(a[5], a[17]); SQRADDAC(a[6], a[16]); SQRADDAC(a[7], a[15]); SQRADDAC(a[8], a[14]); SQRADDAC(a[9], a[13]); SQRADDAC(a[10], a[12]); SQRADDDB; SQRADD(a[11], a[11]); 
+   COMBA_STORE(b[22]);
+
+   /* output 23 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[23]); SQRADDAC(a[1], a[22]); SQRADDAC(a[2], a[21]); SQRADDAC(a[3], a[20]); SQRADDAC(a[4], a[19]); SQRADDAC(a[5], a[18]); SQRADDAC(a[6], a[17]); SQRADDAC(a[7], a[16]); SQRADDAC(a[8], a[15]); SQRADDAC(a[9], a[14]); SQRADDAC(a[10], a[13]); SQRADDAC(a[11], a[12]); SQRADDDB; 
+   COMBA_STORE(b[23]);
+
+   /* output 24 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[24]); SQRADDAC(a[1], a[23]); SQRADDAC(a[2], a[22]); SQRADDAC(a[3], a[21]); SQRADDAC(a[4], a[20]); SQRADDAC(a[5], a[19]); SQRADDAC(a[6], a[18]); SQRADDAC(a[7], a[17]); SQRADDAC(a[8], a[16]); SQRADDAC(a[9], a[15]); SQRADDAC(a[10], a[14]); SQRADDAC(a[11], a[13]); SQRADDDB; SQRADD(a[12], a[12]); 
+   COMBA_STORE(b[24]);
+
+   /* output 25 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[25]); SQRADDAC(a[1], a[24]); SQRADDAC(a[2], a[23]); SQRADDAC(a[3], a[22]); SQRADDAC(a[4], a[21]); SQRADDAC(a[5], a[20]); SQRADDAC(a[6], a[19]); SQRADDAC(a[7], a[18]); SQRADDAC(a[8], a[17]); SQRADDAC(a[9], a[16]); SQRADDAC(a[10], a[15]); SQRADDAC(a[11], a[14]); SQRADDAC(a[12], a[13]); SQRADDDB; 
+   COMBA_STORE(b[25]);
+
+   /* output 26 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[26]); SQRADDAC(a[1], a[25]); SQRADDAC(a[2], a[24]); SQRADDAC(a[3], a[23]); SQRADDAC(a[4], a[22]); SQRADDAC(a[5], a[21]); SQRADDAC(a[6], a[20]); SQRADDAC(a[7], a[19]); SQRADDAC(a[8], a[18]); SQRADDAC(a[9], a[17]); SQRADDAC(a[10], a[16]); SQRADDAC(a[11], a[15]); SQRADDAC(a[12], a[14]); SQRADDDB; SQRADD(a[13], a[13]); 
+   COMBA_STORE(b[26]);
+
+   /* output 27 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[27]); SQRADDAC(a[1], a[26]); SQRADDAC(a[2], a[25]); SQRADDAC(a[3], a[24]); SQRADDAC(a[4], a[23]); SQRADDAC(a[5], a[22]); SQRADDAC(a[6], a[21]); SQRADDAC(a[7], a[20]); SQRADDAC(a[8], a[19]); SQRADDAC(a[9], a[18]); SQRADDAC(a[10], a[17]); SQRADDAC(a[11], a[16]); SQRADDAC(a[12], a[15]); SQRADDAC(a[13], a[14]); SQRADDDB; 
+   COMBA_STORE(b[27]);
+
+   /* output 28 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[28]); SQRADDAC(a[1], a[27]); SQRADDAC(a[2], a[26]); SQRADDAC(a[3], a[25]); SQRADDAC(a[4], a[24]); SQRADDAC(a[5], a[23]); SQRADDAC(a[6], a[22]); SQRADDAC(a[7], a[21]); SQRADDAC(a[8], a[20]); SQRADDAC(a[9], a[19]); SQRADDAC(a[10], a[18]); SQRADDAC(a[11], a[17]); SQRADDAC(a[12], a[16]); SQRADDAC(a[13], a[15]); SQRADDDB; SQRADD(a[14], a[14]); 
+   COMBA_STORE(b[28]);
+
+   /* output 29 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[29]); SQRADDAC(a[1], a[28]); SQRADDAC(a[2], a[27]); SQRADDAC(a[3], a[26]); SQRADDAC(a[4], a[25]); SQRADDAC(a[5], a[24]); SQRADDAC(a[6], a[23]); SQRADDAC(a[7], a[22]); SQRADDAC(a[8], a[21]); SQRADDAC(a[9], a[20]); SQRADDAC(a[10], a[19]); SQRADDAC(a[11], a[18]); SQRADDAC(a[12], a[17]); SQRADDAC(a[13], a[16]); SQRADDAC(a[14], a[15]); SQRADDDB; 
+   COMBA_STORE(b[29]);
+
+   /* output 30 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[30]); SQRADDAC(a[1], a[29]); SQRADDAC(a[2], a[28]); SQRADDAC(a[3], a[27]); SQRADDAC(a[4], a[26]); SQRADDAC(a[5], a[25]); SQRADDAC(a[6], a[24]); SQRADDAC(a[7], a[23]); SQRADDAC(a[8], a[22]); SQRADDAC(a[9], a[21]); SQRADDAC(a[10], a[20]); SQRADDAC(a[11], a[19]); SQRADDAC(a[12], a[18]); SQRADDAC(a[13], a[17]); SQRADDAC(a[14], a[16]); SQRADDDB; SQRADD(a[15], a[15]); 
+   COMBA_STORE(b[30]);
+
+   /* output 31 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[31]); SQRADDAC(a[1], a[30]); SQRADDAC(a[2], a[29]); SQRADDAC(a[3], a[28]); SQRADDAC(a[4], a[27]); SQRADDAC(a[5], a[26]); SQRADDAC(a[6], a[25]); SQRADDAC(a[7], a[24]); SQRADDAC(a[8], a[23]); SQRADDAC(a[9], a[22]); SQRADDAC(a[10], a[21]); SQRADDAC(a[11], a[20]); SQRADDAC(a[12], a[19]); SQRADDAC(a[13], a[18]); SQRADDAC(a[14], a[17]); SQRADDAC(a[15], a[16]); SQRADDDB; 
+   COMBA_STORE(b[31]);
+
+   /* output 32 */
+   CARRY_FORWARD;
+   SQRADDSC(a[1], a[31]); SQRADDAC(a[2], a[30]); SQRADDAC(a[3], a[29]); SQRADDAC(a[4], a[28]); SQRADDAC(a[5], a[27]); SQRADDAC(a[6], a[26]); SQRADDAC(a[7], a[25]); SQRADDAC(a[8], a[24]); SQRADDAC(a[9], a[23]); SQRADDAC(a[10], a[22]); SQRADDAC(a[11], a[21]); SQRADDAC(a[12], a[20]); SQRADDAC(a[13], a[19]); SQRADDAC(a[14], a[18]); SQRADDAC(a[15], a[17]); SQRADDDB; SQRADD(a[16], a[16]); 
+   COMBA_STORE(b[32]);
+
+   /* output 33 */
+   CARRY_FORWARD;
+   SQRADDSC(a[2], a[31]); SQRADDAC(a[3], a[30]); SQRADDAC(a[4], a[29]); SQRADDAC(a[5], a[28]); SQRADDAC(a[6], a[27]); SQRADDAC(a[7], a[26]); SQRADDAC(a[8], a[25]); SQRADDAC(a[9], a[24]); SQRADDAC(a[10], a[23]); SQRADDAC(a[11], a[22]); SQRADDAC(a[12], a[21]); SQRADDAC(a[13], a[20]); SQRADDAC(a[14], a[19]); SQRADDAC(a[15], a[18]); SQRADDAC(a[16], a[17]); SQRADDDB; 
+   COMBA_STORE(b[33]);
+
+   /* output 34 */
+   CARRY_FORWARD;
+   SQRADDSC(a[3], a[31]); SQRADDAC(a[4], a[30]); SQRADDAC(a[5], a[29]); SQRADDAC(a[6], a[28]); SQRADDAC(a[7], a[27]); SQRADDAC(a[8], a[26]); SQRADDAC(a[9], a[25]); SQRADDAC(a[10], a[24]); SQRADDAC(a[11], a[23]); SQRADDAC(a[12], a[22]); SQRADDAC(a[13], a[21]); SQRADDAC(a[14], a[20]); SQRADDAC(a[15], a[19]); SQRADDAC(a[16], a[18]); SQRADDDB; SQRADD(a[17], a[17]); 
+   COMBA_STORE(b[34]);
+
+   /* output 35 */
+   CARRY_FORWARD;
+   SQRADDSC(a[4], a[31]); SQRADDAC(a[5], a[30]); SQRADDAC(a[6], a[29]); SQRADDAC(a[7], a[28]); SQRADDAC(a[8], a[27]); SQRADDAC(a[9], a[26]); SQRADDAC(a[10], a[25]); SQRADDAC(a[11], a[24]); SQRADDAC(a[12], a[23]); SQRADDAC(a[13], a[22]); SQRADDAC(a[14], a[21]); SQRADDAC(a[15], a[20]); SQRADDAC(a[16], a[19]); SQRADDAC(a[17], a[18]); SQRADDDB; 
+   COMBA_STORE(b[35]);
+
+   /* output 36 */
+   CARRY_FORWARD;
+   SQRADDSC(a[5], a[31]); SQRADDAC(a[6], a[30]); SQRADDAC(a[7], a[29]); SQRADDAC(a[8], a[28]); SQRADDAC(a[9], a[27]); SQRADDAC(a[10], a[26]); SQRADDAC(a[11], a[25]); SQRADDAC(a[12], a[24]); SQRADDAC(a[13], a[23]); SQRADDAC(a[14], a[22]); SQRADDAC(a[15], a[21]); SQRADDAC(a[16], a[20]); SQRADDAC(a[17], a[19]); SQRADDDB; SQRADD(a[18], a[18]); 
+   COMBA_STORE(b[36]);
+
+   /* output 37 */
+   CARRY_FORWARD;
+   SQRADDSC(a[6], a[31]); SQRADDAC(a[7], a[30]); SQRADDAC(a[8], a[29]); SQRADDAC(a[9], a[28]); SQRADDAC(a[10], a[27]); SQRADDAC(a[11], a[26]); SQRADDAC(a[12], a[25]); SQRADDAC(a[13], a[24]); SQRADDAC(a[14], a[23]); SQRADDAC(a[15], a[22]); SQRADDAC(a[16], a[21]); SQRADDAC(a[17], a[20]); SQRADDAC(a[18], a[19]); SQRADDDB; 
+   COMBA_STORE(b[37]);
+
+   /* output 38 */
+   CARRY_FORWARD;
+   SQRADDSC(a[7], a[31]); SQRADDAC(a[8], a[30]); SQRADDAC(a[9], a[29]); SQRADDAC(a[10], a[28]); SQRADDAC(a[11], a[27]); SQRADDAC(a[12], a[26]); SQRADDAC(a[13], a[25]); SQRADDAC(a[14], a[24]); SQRADDAC(a[15], a[23]); SQRADDAC(a[16], a[22]); SQRADDAC(a[17], a[21]); SQRADDAC(a[18], a[20]); SQRADDDB; SQRADD(a[19], a[19]); 
+   COMBA_STORE(b[38]);
+
+   /* output 39 */
+   CARRY_FORWARD;
+   SQRADDSC(a[8], a[31]); SQRADDAC(a[9], a[30]); SQRADDAC(a[10], a[29]); SQRADDAC(a[11], a[28]); SQRADDAC(a[12], a[27]); SQRADDAC(a[13], a[26]); SQRADDAC(a[14], a[25]); SQRADDAC(a[15], a[24]); SQRADDAC(a[16], a[23]); SQRADDAC(a[17], a[22]); SQRADDAC(a[18], a[21]); SQRADDAC(a[19], a[20]); SQRADDDB; 
+   COMBA_STORE(b[39]);
+
+   /* output 40 */
+   CARRY_FORWARD;
+   SQRADDSC(a[9], a[31]); SQRADDAC(a[10], a[30]); SQRADDAC(a[11], a[29]); SQRADDAC(a[12], a[28]); SQRADDAC(a[13], a[27]); SQRADDAC(a[14], a[26]); SQRADDAC(a[15], a[25]); SQRADDAC(a[16], a[24]); SQRADDAC(a[17], a[23]); SQRADDAC(a[18], a[22]); SQRADDAC(a[19], a[21]); SQRADDDB; SQRADD(a[20], a[20]); 
+   COMBA_STORE(b[40]);
+
+   /* output 41 */
+   CARRY_FORWARD;
+   SQRADDSC(a[10], a[31]); SQRADDAC(a[11], a[30]); SQRADDAC(a[12], a[29]); SQRADDAC(a[13], a[28]); SQRADDAC(a[14], a[27]); SQRADDAC(a[15], a[26]); SQRADDAC(a[16], a[25]); SQRADDAC(a[17], a[24]); SQRADDAC(a[18], a[23]); SQRADDAC(a[19], a[22]); SQRADDAC(a[20], a[21]); SQRADDDB; 
+   COMBA_STORE(b[41]);
+
+   /* output 42 */
+   CARRY_FORWARD;
+   SQRADDSC(a[11], a[31]); SQRADDAC(a[12], a[30]); SQRADDAC(a[13], a[29]); SQRADDAC(a[14], a[28]); SQRADDAC(a[15], a[27]); SQRADDAC(a[16], a[26]); SQRADDAC(a[17], a[25]); SQRADDAC(a[18], a[24]); SQRADDAC(a[19], a[23]); SQRADDAC(a[20], a[22]); SQRADDDB; SQRADD(a[21], a[21]); 
+   COMBA_STORE(b[42]);
+
+   /* output 43 */
+   CARRY_FORWARD;
+   SQRADDSC(a[12], a[31]); SQRADDAC(a[13], a[30]); SQRADDAC(a[14], a[29]); SQRADDAC(a[15], a[28]); SQRADDAC(a[16], a[27]); SQRADDAC(a[17], a[26]); SQRADDAC(a[18], a[25]); SQRADDAC(a[19], a[24]); SQRADDAC(a[20], a[23]); SQRADDAC(a[21], a[22]); SQRADDDB; 
+   COMBA_STORE(b[43]);
+
+   /* output 44 */
+   CARRY_FORWARD;
+   SQRADDSC(a[13], a[31]); SQRADDAC(a[14], a[30]); SQRADDAC(a[15], a[29]); SQRADDAC(a[16], a[28]); SQRADDAC(a[17], a[27]); SQRADDAC(a[18], a[26]); SQRADDAC(a[19], a[25]); SQRADDAC(a[20], a[24]); SQRADDAC(a[21], a[23]); SQRADDDB; SQRADD(a[22], a[22]); 
+   COMBA_STORE(b[44]);
+
+   /* output 45 */
+   CARRY_FORWARD;
+   SQRADDSC(a[14], a[31]); SQRADDAC(a[15], a[30]); SQRADDAC(a[16], a[29]); SQRADDAC(a[17], a[28]); SQRADDAC(a[18], a[27]); SQRADDAC(a[19], a[26]); SQRADDAC(a[20], a[25]); SQRADDAC(a[21], a[24]); SQRADDAC(a[22], a[23]); SQRADDDB; 
+   COMBA_STORE(b[45]);
+
+   /* output 46 */
+   CARRY_FORWARD;
+   SQRADDSC(a[15], a[31]); SQRADDAC(a[16], a[30]); SQRADDAC(a[17], a[29]); SQRADDAC(a[18], a[28]); SQRADDAC(a[19], a[27]); SQRADDAC(a[20], a[26]); SQRADDAC(a[21], a[25]); SQRADDAC(a[22], a[24]); SQRADDDB; SQRADD(a[23], a[23]); 
+   COMBA_STORE(b[46]);
+
+   /* output 47 */
+   CARRY_FORWARD;
+   SQRADDSC(a[16], a[31]); SQRADDAC(a[17], a[30]); SQRADDAC(a[18], a[29]); SQRADDAC(a[19], a[28]); SQRADDAC(a[20], a[27]); SQRADDAC(a[21], a[26]); SQRADDAC(a[22], a[25]); SQRADDAC(a[23], a[24]); SQRADDDB; 
+   COMBA_STORE(b[47]);
+
+   /* output 48 */
+   CARRY_FORWARD;
+   SQRADDSC(a[17], a[31]); SQRADDAC(a[18], a[30]); SQRADDAC(a[19], a[29]); SQRADDAC(a[20], a[28]); SQRADDAC(a[21], a[27]); SQRADDAC(a[22], a[26]); SQRADDAC(a[23], a[25]); SQRADDDB; SQRADD(a[24], a[24]); 
+   COMBA_STORE(b[48]);
+
+   /* output 49 */
+   CARRY_FORWARD;
+   SQRADDSC(a[18], a[31]); SQRADDAC(a[19], a[30]); SQRADDAC(a[20], a[29]); SQRADDAC(a[21], a[28]); SQRADDAC(a[22], a[27]); SQRADDAC(a[23], a[26]); SQRADDAC(a[24], a[25]); SQRADDDB; 
+   COMBA_STORE(b[49]);
+
+   /* output 50 */
+   CARRY_FORWARD;
+   SQRADDSC(a[19], a[31]); SQRADDAC(a[20], a[30]); SQRADDAC(a[21], a[29]); SQRADDAC(a[22], a[28]); SQRADDAC(a[23], a[27]); SQRADDAC(a[24], a[26]); SQRADDDB; SQRADD(a[25], a[25]); 
+   COMBA_STORE(b[50]);
+
+   /* output 51 */
+   CARRY_FORWARD;
+   SQRADDSC(a[20], a[31]); SQRADDAC(a[21], a[30]); SQRADDAC(a[22], a[29]); SQRADDAC(a[23], a[28]); SQRADDAC(a[24], a[27]); SQRADDAC(a[25], a[26]); SQRADDDB; 
+   COMBA_STORE(b[51]);
+
+   /* output 52 */
+   CARRY_FORWARD;
+   SQRADDSC(a[21], a[31]); SQRADDAC(a[22], a[30]); SQRADDAC(a[23], a[29]); SQRADDAC(a[24], a[28]); SQRADDAC(a[25], a[27]); SQRADDDB; SQRADD(a[26], a[26]); 
+   COMBA_STORE(b[52]);
+
+   /* output 53 */
+   CARRY_FORWARD;
+   SQRADDSC(a[22], a[31]); SQRADDAC(a[23], a[30]); SQRADDAC(a[24], a[29]); SQRADDAC(a[25], a[28]); SQRADDAC(a[26], a[27]); SQRADDDB; 
+   COMBA_STORE(b[53]);
+
+   /* output 54 */
+   CARRY_FORWARD;
+   SQRADDSC(a[23], a[31]); SQRADDAC(a[24], a[30]); SQRADDAC(a[25], a[29]); SQRADDAC(a[26], a[28]); SQRADDDB; SQRADD(a[27], a[27]); 
+   COMBA_STORE(b[54]);
+
+   /* output 55 */
+   CARRY_FORWARD;
+   SQRADDSC(a[24], a[31]); SQRADDAC(a[25], a[30]); SQRADDAC(a[26], a[29]); SQRADDAC(a[27], a[28]); SQRADDDB; 
+   COMBA_STORE(b[55]);
+
+   /* output 56 */
+   CARRY_FORWARD;
+   SQRADDSC(a[25], a[31]); SQRADDAC(a[26], a[30]); SQRADDAC(a[27], a[29]); SQRADDDB; SQRADD(a[28], a[28]); 
+   COMBA_STORE(b[56]);
+
+   /* output 57 */
+   CARRY_FORWARD;
+   SQRADDSC(a[26], a[31]); SQRADDAC(a[27], a[30]); SQRADDAC(a[28], a[29]); SQRADDDB; 
+   COMBA_STORE(b[57]);
+
+   /* output 58 */
+   CARRY_FORWARD;
+   SQRADD2(a[27], a[31]); SQRADD2(a[28], a[30]); SQRADD(a[29], a[29]); 
+   COMBA_STORE(b[58]);
+
+   /* output 59 */
+   CARRY_FORWARD;
+   SQRADD2(a[28], a[31]); SQRADD2(a[29], a[30]); 
+   COMBA_STORE(b[59]);
+
+   /* output 60 */
+   CARRY_FORWARD;
+   SQRADD2(a[29], a[31]); SQRADD(a[30], a[30]); 
+   COMBA_STORE(b[60]);
+
+   /* output 61 */
+   CARRY_FORWARD;
+   SQRADD2(a[30], a[31]); 
+   COMBA_STORE(b[61]);
+
+   /* output 62 */
+   CARRY_FORWARD;
+   SQRADD(a[31], a[31]); 
+   COMBA_STORE(b[62]);
+   COMBA_STORE2(b[63]);
+   COMBA_FINI;
+
+   B->used = 64;
+   B->sign = FP_ZPOS;
+   memcpy(B->dp, b, 64 * sizeof(fp_digit));
+   fp_clamp(B);
+}
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_4.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_4.i
new file mode 100644
index 0000000..bb09dc8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_4.i
@@ -0,0 +1,80 @@
+/* fp_sqr_comba_4.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_SQR4
+void fp_sqr_comba4(fp_int *A, fp_int *B)
+{
+   fp_digit *a, b[8], c0, c1, c2;
+#ifdef TFM_ISO
+   fp_word tt;
+#endif
+
+   a = A->dp;
+   COMBA_START; 
+
+   /* clear carries */
+   CLEAR_CARRY;
+
+   /* output 0 */
+   SQRADD(a[0],a[0]);
+   COMBA_STORE(b[0]);
+
+   /* output 1 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[1]); 
+   COMBA_STORE(b[1]);
+
+   /* output 2 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[2]); SQRADD(a[1], a[1]); 
+   COMBA_STORE(b[2]);
+
+   /* output 3 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[3]); SQRADD2(a[1], a[2]); 
+   COMBA_STORE(b[3]);
+
+   /* output 4 */
+   CARRY_FORWARD;
+   SQRADD2(a[1], a[3]); SQRADD(a[2], a[2]); 
+   COMBA_STORE(b[4]);
+
+   /* output 5 */
+   CARRY_FORWARD;
+   SQRADD2(a[2], a[3]); 
+   COMBA_STORE(b[5]);
+
+   /* output 6 */
+   CARRY_FORWARD;
+   SQRADD(a[3], a[3]); 
+   COMBA_STORE(b[6]);
+   COMBA_STORE2(b[7]);
+   COMBA_FINI;
+
+   B->used = 8;
+   B->sign = FP_ZPOS;
+   memcpy(B->dp, b, 8 * sizeof(fp_digit));
+   fp_clamp(B);
+}
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_48.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_48.i
new file mode 100644
index 0000000..cbaac02
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_48.i
@@ -0,0 +1,520 @@
+/* fp_sqr_comba_48.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_SQR48
+void fp_sqr_comba48(fp_int *A, fp_int *B)
+{
+   fp_digit *a, b[96], c0, c1, c2, sc0, sc1, sc2;
+#ifdef TFM_ISO
+   fp_word   tt;   
+#endif   
+
+   a = A->dp;
+   COMBA_START; 
+
+   /* clear carries */
+   CLEAR_CARRY;
+
+   /* output 0 */
+   SQRADD(a[0],a[0]);
+   COMBA_STORE(b[0]);
+
+   /* output 1 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[1]); 
+   COMBA_STORE(b[1]);
+
+   /* output 2 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[2]); SQRADD(a[1], a[1]); 
+   COMBA_STORE(b[2]);
+
+   /* output 3 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[3]); SQRADD2(a[1], a[2]); 
+   COMBA_STORE(b[3]);
+
+   /* output 4 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[4]); SQRADD2(a[1], a[3]); SQRADD(a[2], a[2]); 
+   COMBA_STORE(b[4]);
+
+   /* output 5 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[5]); SQRADDAC(a[1], a[4]); SQRADDAC(a[2], a[3]); SQRADDDB; 
+   COMBA_STORE(b[5]);
+
+   /* output 6 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[6]); SQRADDAC(a[1], a[5]); SQRADDAC(a[2], a[4]); SQRADDDB; SQRADD(a[3], a[3]); 
+   COMBA_STORE(b[6]);
+
+   /* output 7 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[7]); SQRADDAC(a[1], a[6]); SQRADDAC(a[2], a[5]); SQRADDAC(a[3], a[4]); SQRADDDB; 
+   COMBA_STORE(b[7]);
+
+   /* output 8 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[8]); SQRADDAC(a[1], a[7]); SQRADDAC(a[2], a[6]); SQRADDAC(a[3], a[5]); SQRADDDB; SQRADD(a[4], a[4]); 
+   COMBA_STORE(b[8]);
+
+   /* output 9 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[9]); SQRADDAC(a[1], a[8]); SQRADDAC(a[2], a[7]); SQRADDAC(a[3], a[6]); SQRADDAC(a[4], a[5]); SQRADDDB; 
+   COMBA_STORE(b[9]);
+
+   /* output 10 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[10]); SQRADDAC(a[1], a[9]); SQRADDAC(a[2], a[8]); SQRADDAC(a[3], a[7]); SQRADDAC(a[4], a[6]); SQRADDDB; SQRADD(a[5], a[5]); 
+   COMBA_STORE(b[10]);
+
+   /* output 11 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[11]); SQRADDAC(a[1], a[10]); SQRADDAC(a[2], a[9]); SQRADDAC(a[3], a[8]); SQRADDAC(a[4], a[7]); SQRADDAC(a[5], a[6]); SQRADDDB; 
+   COMBA_STORE(b[11]);
+
+   /* output 12 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[12]); SQRADDAC(a[1], a[11]); SQRADDAC(a[2], a[10]); SQRADDAC(a[3], a[9]); SQRADDAC(a[4], a[8]); SQRADDAC(a[5], a[7]); SQRADDDB; SQRADD(a[6], a[6]); 
+   COMBA_STORE(b[12]);
+
+   /* output 13 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[13]); SQRADDAC(a[1], a[12]); SQRADDAC(a[2], a[11]); SQRADDAC(a[3], a[10]); SQRADDAC(a[4], a[9]); SQRADDAC(a[5], a[8]); SQRADDAC(a[6], a[7]); SQRADDDB; 
+   COMBA_STORE(b[13]);
+
+   /* output 14 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[14]); SQRADDAC(a[1], a[13]); SQRADDAC(a[2], a[12]); SQRADDAC(a[3], a[11]); SQRADDAC(a[4], a[10]); SQRADDAC(a[5], a[9]); SQRADDAC(a[6], a[8]); SQRADDDB; SQRADD(a[7], a[7]); 
+   COMBA_STORE(b[14]);
+
+   /* output 15 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[15]); SQRADDAC(a[1], a[14]); SQRADDAC(a[2], a[13]); SQRADDAC(a[3], a[12]); SQRADDAC(a[4], a[11]); SQRADDAC(a[5], a[10]); SQRADDAC(a[6], a[9]); SQRADDAC(a[7], a[8]); SQRADDDB; 
+   COMBA_STORE(b[15]);
+
+   /* output 16 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[16]); SQRADDAC(a[1], a[15]); SQRADDAC(a[2], a[14]); SQRADDAC(a[3], a[13]); SQRADDAC(a[4], a[12]); SQRADDAC(a[5], a[11]); SQRADDAC(a[6], a[10]); SQRADDAC(a[7], a[9]); SQRADDDB; SQRADD(a[8], a[8]); 
+   COMBA_STORE(b[16]);
+
+   /* output 17 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[17]); SQRADDAC(a[1], a[16]); SQRADDAC(a[2], a[15]); SQRADDAC(a[3], a[14]); SQRADDAC(a[4], a[13]); SQRADDAC(a[5], a[12]); SQRADDAC(a[6], a[11]); SQRADDAC(a[7], a[10]); SQRADDAC(a[8], a[9]); SQRADDDB; 
+   COMBA_STORE(b[17]);
+
+   /* output 18 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[18]); SQRADDAC(a[1], a[17]); SQRADDAC(a[2], a[16]); SQRADDAC(a[3], a[15]); SQRADDAC(a[4], a[14]); SQRADDAC(a[5], a[13]); SQRADDAC(a[6], a[12]); SQRADDAC(a[7], a[11]); SQRADDAC(a[8], a[10]); SQRADDDB; SQRADD(a[9], a[9]); 
+   COMBA_STORE(b[18]);
+
+   /* output 19 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[19]); SQRADDAC(a[1], a[18]); SQRADDAC(a[2], a[17]); SQRADDAC(a[3], a[16]); SQRADDAC(a[4], a[15]); SQRADDAC(a[5], a[14]); SQRADDAC(a[6], a[13]); SQRADDAC(a[7], a[12]); SQRADDAC(a[8], a[11]); SQRADDAC(a[9], a[10]); SQRADDDB; 
+   COMBA_STORE(b[19]);
+
+   /* output 20 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[20]); SQRADDAC(a[1], a[19]); SQRADDAC(a[2], a[18]); SQRADDAC(a[3], a[17]); SQRADDAC(a[4], a[16]); SQRADDAC(a[5], a[15]); SQRADDAC(a[6], a[14]); SQRADDAC(a[7], a[13]); SQRADDAC(a[8], a[12]); SQRADDAC(a[9], a[11]); SQRADDDB; SQRADD(a[10], a[10]); 
+   COMBA_STORE(b[20]);
+
+   /* output 21 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[21]); SQRADDAC(a[1], a[20]); SQRADDAC(a[2], a[19]); SQRADDAC(a[3], a[18]); SQRADDAC(a[4], a[17]); SQRADDAC(a[5], a[16]); SQRADDAC(a[6], a[15]); SQRADDAC(a[7], a[14]); SQRADDAC(a[8], a[13]); SQRADDAC(a[9], a[12]); SQRADDAC(a[10], a[11]); SQRADDDB; 
+   COMBA_STORE(b[21]);
+
+   /* output 22 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[22]); SQRADDAC(a[1], a[21]); SQRADDAC(a[2], a[20]); SQRADDAC(a[3], a[19]); SQRADDAC(a[4], a[18]); SQRADDAC(a[5], a[17]); SQRADDAC(a[6], a[16]); SQRADDAC(a[7], a[15]); SQRADDAC(a[8], a[14]); SQRADDAC(a[9], a[13]); SQRADDAC(a[10], a[12]); SQRADDDB; SQRADD(a[11], a[11]); 
+   COMBA_STORE(b[22]);
+
+   /* output 23 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[23]); SQRADDAC(a[1], a[22]); SQRADDAC(a[2], a[21]); SQRADDAC(a[3], a[20]); SQRADDAC(a[4], a[19]); SQRADDAC(a[5], a[18]); SQRADDAC(a[6], a[17]); SQRADDAC(a[7], a[16]); SQRADDAC(a[8], a[15]); SQRADDAC(a[9], a[14]); SQRADDAC(a[10], a[13]); SQRADDAC(a[11], a[12]); SQRADDDB; 
+   COMBA_STORE(b[23]);
+
+   /* output 24 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[24]); SQRADDAC(a[1], a[23]); SQRADDAC(a[2], a[22]); SQRADDAC(a[3], a[21]); SQRADDAC(a[4], a[20]); SQRADDAC(a[5], a[19]); SQRADDAC(a[6], a[18]); SQRADDAC(a[7], a[17]); SQRADDAC(a[8], a[16]); SQRADDAC(a[9], a[15]); SQRADDAC(a[10], a[14]); SQRADDAC(a[11], a[13]); SQRADDDB; SQRADD(a[12], a[12]); 
+   COMBA_STORE(b[24]);
+
+   /* output 25 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[25]); SQRADDAC(a[1], a[24]); SQRADDAC(a[2], a[23]); SQRADDAC(a[3], a[22]); SQRADDAC(a[4], a[21]); SQRADDAC(a[5], a[20]); SQRADDAC(a[6], a[19]); SQRADDAC(a[7], a[18]); SQRADDAC(a[8], a[17]); SQRADDAC(a[9], a[16]); SQRADDAC(a[10], a[15]); SQRADDAC(a[11], a[14]); SQRADDAC(a[12], a[13]); SQRADDDB; 
+   COMBA_STORE(b[25]);
+
+   /* output 26 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[26]); SQRADDAC(a[1], a[25]); SQRADDAC(a[2], a[24]); SQRADDAC(a[3], a[23]); SQRADDAC(a[4], a[22]); SQRADDAC(a[5], a[21]); SQRADDAC(a[6], a[20]); SQRADDAC(a[7], a[19]); SQRADDAC(a[8], a[18]); SQRADDAC(a[9], a[17]); SQRADDAC(a[10], a[16]); SQRADDAC(a[11], a[15]); SQRADDAC(a[12], a[14]); SQRADDDB; SQRADD(a[13], a[13]); 
+   COMBA_STORE(b[26]);
+
+   /* output 27 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[27]); SQRADDAC(a[1], a[26]); SQRADDAC(a[2], a[25]); SQRADDAC(a[3], a[24]); SQRADDAC(a[4], a[23]); SQRADDAC(a[5], a[22]); SQRADDAC(a[6], a[21]); SQRADDAC(a[7], a[20]); SQRADDAC(a[8], a[19]); SQRADDAC(a[9], a[18]); SQRADDAC(a[10], a[17]); SQRADDAC(a[11], a[16]); SQRADDAC(a[12], a[15]); SQRADDAC(a[13], a[14]); SQRADDDB; 
+   COMBA_STORE(b[27]);
+
+   /* output 28 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[28]); SQRADDAC(a[1], a[27]); SQRADDAC(a[2], a[26]); SQRADDAC(a[3], a[25]); SQRADDAC(a[4], a[24]); SQRADDAC(a[5], a[23]); SQRADDAC(a[6], a[22]); SQRADDAC(a[7], a[21]); SQRADDAC(a[8], a[20]); SQRADDAC(a[9], a[19]); SQRADDAC(a[10], a[18]); SQRADDAC(a[11], a[17]); SQRADDAC(a[12], a[16]); SQRADDAC(a[13], a[15]); SQRADDDB; SQRADD(a[14], a[14]); 
+   COMBA_STORE(b[28]);
+
+   /* output 29 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[29]); SQRADDAC(a[1], a[28]); SQRADDAC(a[2], a[27]); SQRADDAC(a[3], a[26]); SQRADDAC(a[4], a[25]); SQRADDAC(a[5], a[24]); SQRADDAC(a[6], a[23]); SQRADDAC(a[7], a[22]); SQRADDAC(a[8], a[21]); SQRADDAC(a[9], a[20]); SQRADDAC(a[10], a[19]); SQRADDAC(a[11], a[18]); SQRADDAC(a[12], a[17]); SQRADDAC(a[13], a[16]); SQRADDAC(a[14], a[15]); SQRADDDB; 
+   COMBA_STORE(b[29]);
+
+   /* output 30 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[30]); SQRADDAC(a[1], a[29]); SQRADDAC(a[2], a[28]); SQRADDAC(a[3], a[27]); SQRADDAC(a[4], a[26]); SQRADDAC(a[5], a[25]); SQRADDAC(a[6], a[24]); SQRADDAC(a[7], a[23]); SQRADDAC(a[8], a[22]); SQRADDAC(a[9], a[21]); SQRADDAC(a[10], a[20]); SQRADDAC(a[11], a[19]); SQRADDAC(a[12], a[18]); SQRADDAC(a[13], a[17]); SQRADDAC(a[14], a[16]); SQRADDDB; SQRADD(a[15], a[15]); 
+   COMBA_STORE(b[30]);
+
+   /* output 31 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[31]); SQRADDAC(a[1], a[30]); SQRADDAC(a[2], a[29]); SQRADDAC(a[3], a[28]); SQRADDAC(a[4], a[27]); SQRADDAC(a[5], a[26]); SQRADDAC(a[6], a[25]); SQRADDAC(a[7], a[24]); SQRADDAC(a[8], a[23]); SQRADDAC(a[9], a[22]); SQRADDAC(a[10], a[21]); SQRADDAC(a[11], a[20]); SQRADDAC(a[12], a[19]); SQRADDAC(a[13], a[18]); SQRADDAC(a[14], a[17]); SQRADDAC(a[15], a[16]); SQRADDDB; 
+   COMBA_STORE(b[31]);
+
+   /* output 32 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[32]); SQRADDAC(a[1], a[31]); SQRADDAC(a[2], a[30]); SQRADDAC(a[3], a[29]); SQRADDAC(a[4], a[28]); SQRADDAC(a[5], a[27]); SQRADDAC(a[6], a[26]); SQRADDAC(a[7], a[25]); SQRADDAC(a[8], a[24]); SQRADDAC(a[9], a[23]); SQRADDAC(a[10], a[22]); SQRADDAC(a[11], a[21]); SQRADDAC(a[12], a[20]); SQRADDAC(a[13], a[19]); SQRADDAC(a[14], a[18]); SQRADDAC(a[15], a[17]); SQRADDDB; SQRADD(a[16], a[16]); 
+   COMBA_STORE(b[32]);
+
+   /* output 33 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[33]); SQRADDAC(a[1], a[32]); SQRADDAC(a[2], a[31]); SQRADDAC(a[3], a[30]); SQRADDAC(a[4], a[29]); SQRADDAC(a[5], a[28]); SQRADDAC(a[6], a[27]); SQRADDAC(a[7], a[26]); SQRADDAC(a[8], a[25]); SQRADDAC(a[9], a[24]); SQRADDAC(a[10], a[23]); SQRADDAC(a[11], a[22]); SQRADDAC(a[12], a[21]); SQRADDAC(a[13], a[20]); SQRADDAC(a[14], a[19]); SQRADDAC(a[15], a[18]); SQRADDAC(a[16], a[17]); SQRADDDB; 
+   COMBA_STORE(b[33]);
+
+   /* output 34 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[34]); SQRADDAC(a[1], a[33]); SQRADDAC(a[2], a[32]); SQRADDAC(a[3], a[31]); SQRADDAC(a[4], a[30]); SQRADDAC(a[5], a[29]); SQRADDAC(a[6], a[28]); SQRADDAC(a[7], a[27]); SQRADDAC(a[8], a[26]); SQRADDAC(a[9], a[25]); SQRADDAC(a[10], a[24]); SQRADDAC(a[11], a[23]); SQRADDAC(a[12], a[22]); SQRADDAC(a[13], a[21]); SQRADDAC(a[14], a[20]); SQRADDAC(a[15], a[19]); SQRADDAC(a[16], a[18]); SQRADDDB; SQRADD(a[17], a[17]); 
+   COMBA_STORE(b[34]);
+
+   /* output 35 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[35]); SQRADDAC(a[1], a[34]); SQRADDAC(a[2], a[33]); SQRADDAC(a[3], a[32]); SQRADDAC(a[4], a[31]); SQRADDAC(a[5], a[30]); SQRADDAC(a[6], a[29]); SQRADDAC(a[7], a[28]); SQRADDAC(a[8], a[27]); SQRADDAC(a[9], a[26]); SQRADDAC(a[10], a[25]); SQRADDAC(a[11], a[24]); SQRADDAC(a[12], a[23]); SQRADDAC(a[13], a[22]); SQRADDAC(a[14], a[21]); SQRADDAC(a[15], a[20]); SQRADDAC(a[16], a[19]); SQRADDAC(a[17], a[18]); SQRADDDB; 
+   COMBA_STORE(b[35]);
+
+   /* output 36 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[36]); SQRADDAC(a[1], a[35]); SQRADDAC(a[2], a[34]); SQRADDAC(a[3], a[33]); SQRADDAC(a[4], a[32]); SQRADDAC(a[5], a[31]); SQRADDAC(a[6], a[30]); SQRADDAC(a[7], a[29]); SQRADDAC(a[8], a[28]); SQRADDAC(a[9], a[27]); SQRADDAC(a[10], a[26]); SQRADDAC(a[11], a[25]); SQRADDAC(a[12], a[24]); SQRADDAC(a[13], a[23]); SQRADDAC(a[14], a[22]); SQRADDAC(a[15], a[21]); SQRADDAC(a[16], a[20]); SQRADDAC(a[17], a[19]); SQRADDDB; SQRADD(a[18], a[18]); 
+   COMBA_STORE(b[36]);
+
+   /* output 37 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[37]); SQRADDAC(a[1], a[36]); SQRADDAC(a[2], a[35]); SQRADDAC(a[3], a[34]); SQRADDAC(a[4], a[33]); SQRADDAC(a[5], a[32]); SQRADDAC(a[6], a[31]); SQRADDAC(a[7], a[30]); SQRADDAC(a[8], a[29]); SQRADDAC(a[9], a[28]); SQRADDAC(a[10], a[27]); SQRADDAC(a[11], a[26]); SQRADDAC(a[12], a[25]); SQRADDAC(a[13], a[24]); SQRADDAC(a[14], a[23]); SQRADDAC(a[15], a[22]); SQRADDAC(a[16], a[21]); SQRADDAC(a[17], a[20]); SQRADDAC(a[18], a[19]); SQRADDDB; 
+   COMBA_STORE(b[37]);
+
+   /* output 38 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[38]); SQRADDAC(a[1], a[37]); SQRADDAC(a[2], a[36]); SQRADDAC(a[3], a[35]); SQRADDAC(a[4], a[34]); SQRADDAC(a[5], a[33]); SQRADDAC(a[6], a[32]); SQRADDAC(a[7], a[31]); SQRADDAC(a[8], a[30]); SQRADDAC(a[9], a[29]); SQRADDAC(a[10], a[28]); SQRADDAC(a[11], a[27]); SQRADDAC(a[12], a[26]); SQRADDAC(a[13], a[25]); SQRADDAC(a[14], a[24]); SQRADDAC(a[15], a[23]); SQRADDAC(a[16], a[22]); SQRADDAC(a[17], a[21]); SQRADDAC(a[18], a[20]); SQRADDDB; SQRADD(a[19], a[19]); 
+   COMBA_STORE(b[38]);
+
+   /* output 39 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[39]); SQRADDAC(a[1], a[38]); SQRADDAC(a[2], a[37]); SQRADDAC(a[3], a[36]); SQRADDAC(a[4], a[35]); SQRADDAC(a[5], a[34]); SQRADDAC(a[6], a[33]); SQRADDAC(a[7], a[32]); SQRADDAC(a[8], a[31]); SQRADDAC(a[9], a[30]); SQRADDAC(a[10], a[29]); SQRADDAC(a[11], a[28]); SQRADDAC(a[12], a[27]); SQRADDAC(a[13], a[26]); SQRADDAC(a[14], a[25]); SQRADDAC(a[15], a[24]); SQRADDAC(a[16], a[23]); SQRADDAC(a[17], a[22]); SQRADDAC(a[18], a[21]); SQRADDAC(a[19], a[20]); SQRADDDB; 
+   COMBA_STORE(b[39]);
+
+   /* output 40 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[40]); SQRADDAC(a[1], a[39]); SQRADDAC(a[2], a[38]); SQRADDAC(a[3], a[37]); SQRADDAC(a[4], a[36]); SQRADDAC(a[5], a[35]); SQRADDAC(a[6], a[34]); SQRADDAC(a[7], a[33]); SQRADDAC(a[8], a[32]); SQRADDAC(a[9], a[31]); SQRADDAC(a[10], a[30]); SQRADDAC(a[11], a[29]); SQRADDAC(a[12], a[28]); SQRADDAC(a[13], a[27]); SQRADDAC(a[14], a[26]); SQRADDAC(a[15], a[25]); SQRADDAC(a[16], a[24]); SQRADDAC(a[17], a[23]); SQRADDAC(a[18], a[22]); SQRADDAC(a[19], a[21]); SQRADDDB; SQRADD(a[20], a[20]); 
+   COMBA_STORE(b[40]);
+
+   /* output 41 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[41]); SQRADDAC(a[1], a[40]); SQRADDAC(a[2], a[39]); SQRADDAC(a[3], a[38]); SQRADDAC(a[4], a[37]); SQRADDAC(a[5], a[36]); SQRADDAC(a[6], a[35]); SQRADDAC(a[7], a[34]); SQRADDAC(a[8], a[33]); SQRADDAC(a[9], a[32]); SQRADDAC(a[10], a[31]); SQRADDAC(a[11], a[30]); SQRADDAC(a[12], a[29]); SQRADDAC(a[13], a[28]); SQRADDAC(a[14], a[27]); SQRADDAC(a[15], a[26]); SQRADDAC(a[16], a[25]); SQRADDAC(a[17], a[24]); SQRADDAC(a[18], a[23]); SQRADDAC(a[19], a[22]); SQRADDAC(a[20], a[21]); SQRADDDB; 
+   COMBA_STORE(b[41]);
+
+   /* output 42 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[42]); SQRADDAC(a[1], a[41]); SQRADDAC(a[2], a[40]); SQRADDAC(a[3], a[39]); SQRADDAC(a[4], a[38]); SQRADDAC(a[5], a[37]); SQRADDAC(a[6], a[36]); SQRADDAC(a[7], a[35]); SQRADDAC(a[8], a[34]); SQRADDAC(a[9], a[33]); SQRADDAC(a[10], a[32]); SQRADDAC(a[11], a[31]); SQRADDAC(a[12], a[30]); SQRADDAC(a[13], a[29]); SQRADDAC(a[14], a[28]); SQRADDAC(a[15], a[27]); SQRADDAC(a[16], a[26]); SQRADDAC(a[17], a[25]); SQRADDAC(a[18], a[24]); SQRADDAC(a[19], a[23]); SQRADDAC(a[20], a[22]); SQRADDDB; SQRADD(a[21], a[21]); 
+   COMBA_STORE(b[42]);
+
+   /* output 43 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[43]); SQRADDAC(a[1], a[42]); SQRADDAC(a[2], a[41]); SQRADDAC(a[3], a[40]); SQRADDAC(a[4], a[39]); SQRADDAC(a[5], a[38]); SQRADDAC(a[6], a[37]); SQRADDAC(a[7], a[36]); SQRADDAC(a[8], a[35]); SQRADDAC(a[9], a[34]); SQRADDAC(a[10], a[33]); SQRADDAC(a[11], a[32]); SQRADDAC(a[12], a[31]); SQRADDAC(a[13], a[30]); SQRADDAC(a[14], a[29]); SQRADDAC(a[15], a[28]); SQRADDAC(a[16], a[27]); SQRADDAC(a[17], a[26]); SQRADDAC(a[18], a[25]); SQRADDAC(a[19], a[24]); SQRADDAC(a[20], a[23]); SQRADDAC(a[21], a[22]); SQRADDDB; 
+   COMBA_STORE(b[43]);
+
+   /* output 44 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[44]); SQRADDAC(a[1], a[43]); SQRADDAC(a[2], a[42]); SQRADDAC(a[3], a[41]); SQRADDAC(a[4], a[40]); SQRADDAC(a[5], a[39]); SQRADDAC(a[6], a[38]); SQRADDAC(a[7], a[37]); SQRADDAC(a[8], a[36]); SQRADDAC(a[9], a[35]); SQRADDAC(a[10], a[34]); SQRADDAC(a[11], a[33]); SQRADDAC(a[12], a[32]); SQRADDAC(a[13], a[31]); SQRADDAC(a[14], a[30]); SQRADDAC(a[15], a[29]); SQRADDAC(a[16], a[28]); SQRADDAC(a[17], a[27]); SQRADDAC(a[18], a[26]); SQRADDAC(a[19], a[25]); SQRADDAC(a[20], a[24]); SQRADDAC(a[21], a[23]); SQRADDDB; SQRADD(a[22], a[22]); 
+   COMBA_STORE(b[44]);
+
+   /* output 45 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[45]); SQRADDAC(a[1], a[44]); SQRADDAC(a[2], a[43]); SQRADDAC(a[3], a[42]); SQRADDAC(a[4], a[41]); SQRADDAC(a[5], a[40]); SQRADDAC(a[6], a[39]); SQRADDAC(a[7], a[38]); SQRADDAC(a[8], a[37]); SQRADDAC(a[9], a[36]); SQRADDAC(a[10], a[35]); SQRADDAC(a[11], a[34]); SQRADDAC(a[12], a[33]); SQRADDAC(a[13], a[32]); SQRADDAC(a[14], a[31]); SQRADDAC(a[15], a[30]); SQRADDAC(a[16], a[29]); SQRADDAC(a[17], a[28]); SQRADDAC(a[18], a[27]); SQRADDAC(a[19], a[26]); SQRADDAC(a[20], a[25]); SQRADDAC(a[21], a[24]); SQRADDAC(a[22], a[23]); SQRADDDB; 
+   COMBA_STORE(b[45]);
+
+   /* output 46 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[46]); SQRADDAC(a[1], a[45]); SQRADDAC(a[2], a[44]); SQRADDAC(a[3], a[43]); SQRADDAC(a[4], a[42]); SQRADDAC(a[5], a[41]); SQRADDAC(a[6], a[40]); SQRADDAC(a[7], a[39]); SQRADDAC(a[8], a[38]); SQRADDAC(a[9], a[37]); SQRADDAC(a[10], a[36]); SQRADDAC(a[11], a[35]); SQRADDAC(a[12], a[34]); SQRADDAC(a[13], a[33]); SQRADDAC(a[14], a[32]); SQRADDAC(a[15], a[31]); SQRADDAC(a[16], a[30]); SQRADDAC(a[17], a[29]); SQRADDAC(a[18], a[28]); SQRADDAC(a[19], a[27]); SQRADDAC(a[20], a[26]); SQRADDAC(a[21], a[25]); SQRADDAC(a[22], a[24]); SQRADDDB; SQRADD(a[23], a[23]); 
+   COMBA_STORE(b[46]);
+
+   /* output 47 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[47]); SQRADDAC(a[1], a[46]); SQRADDAC(a[2], a[45]); SQRADDAC(a[3], a[44]); SQRADDAC(a[4], a[43]); SQRADDAC(a[5], a[42]); SQRADDAC(a[6], a[41]); SQRADDAC(a[7], a[40]); SQRADDAC(a[8], a[39]); SQRADDAC(a[9], a[38]); SQRADDAC(a[10], a[37]); SQRADDAC(a[11], a[36]); SQRADDAC(a[12], a[35]); SQRADDAC(a[13], a[34]); SQRADDAC(a[14], a[33]); SQRADDAC(a[15], a[32]); SQRADDAC(a[16], a[31]); SQRADDAC(a[17], a[30]); SQRADDAC(a[18], a[29]); SQRADDAC(a[19], a[28]); SQRADDAC(a[20], a[27]); SQRADDAC(a[21], a[26]); SQRADDAC(a[22], a[25]); SQRADDAC(a[23], a[24]); SQRADDDB; 
+   COMBA_STORE(b[47]);
+
+   /* output 48 */
+   CARRY_FORWARD;
+   SQRADDSC(a[1], a[47]); SQRADDAC(a[2], a[46]); SQRADDAC(a[3], a[45]); SQRADDAC(a[4], a[44]); SQRADDAC(a[5], a[43]); SQRADDAC(a[6], a[42]); SQRADDAC(a[7], a[41]); SQRADDAC(a[8], a[40]); SQRADDAC(a[9], a[39]); SQRADDAC(a[10], a[38]); SQRADDAC(a[11], a[37]); SQRADDAC(a[12], a[36]); SQRADDAC(a[13], a[35]); SQRADDAC(a[14], a[34]); SQRADDAC(a[15], a[33]); SQRADDAC(a[16], a[32]); SQRADDAC(a[17], a[31]); SQRADDAC(a[18], a[30]); SQRADDAC(a[19], a[29]); SQRADDAC(a[20], a[28]); SQRADDAC(a[21], a[27]); SQRADDAC(a[22], a[26]); SQRADDAC(a[23], a[25]); SQRADDDB; SQRADD(a[24], a[24]); 
+   COMBA_STORE(b[48]);
+
+   /* output 49 */
+   CARRY_FORWARD;
+   SQRADDSC(a[2], a[47]); SQRADDAC(a[3], a[46]); SQRADDAC(a[4], a[45]); SQRADDAC(a[5], a[44]); SQRADDAC(a[6], a[43]); SQRADDAC(a[7], a[42]); SQRADDAC(a[8], a[41]); SQRADDAC(a[9], a[40]); SQRADDAC(a[10], a[39]); SQRADDAC(a[11], a[38]); SQRADDAC(a[12], a[37]); SQRADDAC(a[13], a[36]); SQRADDAC(a[14], a[35]); SQRADDAC(a[15], a[34]); SQRADDAC(a[16], a[33]); SQRADDAC(a[17], a[32]); SQRADDAC(a[18], a[31]); SQRADDAC(a[19], a[30]); SQRADDAC(a[20], a[29]); SQRADDAC(a[21], a[28]); SQRADDAC(a[22], a[27]); SQRADDAC(a[23], a[26]); SQRADDAC(a[24], a[25]); SQRADDDB; 
+   COMBA_STORE(b[49]);
+
+   /* output 50 */
+   CARRY_FORWARD;
+   SQRADDSC(a[3], a[47]); SQRADDAC(a[4], a[46]); SQRADDAC(a[5], a[45]); SQRADDAC(a[6], a[44]); SQRADDAC(a[7], a[43]); SQRADDAC(a[8], a[42]); SQRADDAC(a[9], a[41]); SQRADDAC(a[10], a[40]); SQRADDAC(a[11], a[39]); SQRADDAC(a[12], a[38]); SQRADDAC(a[13], a[37]); SQRADDAC(a[14], a[36]); SQRADDAC(a[15], a[35]); SQRADDAC(a[16], a[34]); SQRADDAC(a[17], a[33]); SQRADDAC(a[18], a[32]); SQRADDAC(a[19], a[31]); SQRADDAC(a[20], a[30]); SQRADDAC(a[21], a[29]); SQRADDAC(a[22], a[28]); SQRADDAC(a[23], a[27]); SQRADDAC(a[24], a[26]); SQRADDDB; SQRADD(a[25], a[25]); 
+   COMBA_STORE(b[50]);
+
+   /* output 51 */
+   CARRY_FORWARD;
+   SQRADDSC(a[4], a[47]); SQRADDAC(a[5], a[46]); SQRADDAC(a[6], a[45]); SQRADDAC(a[7], a[44]); SQRADDAC(a[8], a[43]); SQRADDAC(a[9], a[42]); SQRADDAC(a[10], a[41]); SQRADDAC(a[11], a[40]); SQRADDAC(a[12], a[39]); SQRADDAC(a[13], a[38]); SQRADDAC(a[14], a[37]); SQRADDAC(a[15], a[36]); SQRADDAC(a[16], a[35]); SQRADDAC(a[17], a[34]); SQRADDAC(a[18], a[33]); SQRADDAC(a[19], a[32]); SQRADDAC(a[20], a[31]); SQRADDAC(a[21], a[30]); SQRADDAC(a[22], a[29]); SQRADDAC(a[23], a[28]); SQRADDAC(a[24], a[27]); SQRADDAC(a[25], a[26]); SQRADDDB; 
+   COMBA_STORE(b[51]);
+
+   /* output 52 */
+   CARRY_FORWARD;
+   SQRADDSC(a[5], a[47]); SQRADDAC(a[6], a[46]); SQRADDAC(a[7], a[45]); SQRADDAC(a[8], a[44]); SQRADDAC(a[9], a[43]); SQRADDAC(a[10], a[42]); SQRADDAC(a[11], a[41]); SQRADDAC(a[12], a[40]); SQRADDAC(a[13], a[39]); SQRADDAC(a[14], a[38]); SQRADDAC(a[15], a[37]); SQRADDAC(a[16], a[36]); SQRADDAC(a[17], a[35]); SQRADDAC(a[18], a[34]); SQRADDAC(a[19], a[33]); SQRADDAC(a[20], a[32]); SQRADDAC(a[21], a[31]); SQRADDAC(a[22], a[30]); SQRADDAC(a[23], a[29]); SQRADDAC(a[24], a[28]); SQRADDAC(a[25], a[27]); SQRADDDB; SQRADD(a[26], a[26]); 
+   COMBA_STORE(b[52]);
+
+   /* output 53 */
+   CARRY_FORWARD;
+   SQRADDSC(a[6], a[47]); SQRADDAC(a[7], a[46]); SQRADDAC(a[8], a[45]); SQRADDAC(a[9], a[44]); SQRADDAC(a[10], a[43]); SQRADDAC(a[11], a[42]); SQRADDAC(a[12], a[41]); SQRADDAC(a[13], a[40]); SQRADDAC(a[14], a[39]); SQRADDAC(a[15], a[38]); SQRADDAC(a[16], a[37]); SQRADDAC(a[17], a[36]); SQRADDAC(a[18], a[35]); SQRADDAC(a[19], a[34]); SQRADDAC(a[20], a[33]); SQRADDAC(a[21], a[32]); SQRADDAC(a[22], a[31]); SQRADDAC(a[23], a[30]); SQRADDAC(a[24], a[29]); SQRADDAC(a[25], a[28]); SQRADDAC(a[26], a[27]); SQRADDDB; 
+   COMBA_STORE(b[53]);
+
+   /* output 54 */
+   CARRY_FORWARD;
+   SQRADDSC(a[7], a[47]); SQRADDAC(a[8], a[46]); SQRADDAC(a[9], a[45]); SQRADDAC(a[10], a[44]); SQRADDAC(a[11], a[43]); SQRADDAC(a[12], a[42]); SQRADDAC(a[13], a[41]); SQRADDAC(a[14], a[40]); SQRADDAC(a[15], a[39]); SQRADDAC(a[16], a[38]); SQRADDAC(a[17], a[37]); SQRADDAC(a[18], a[36]); SQRADDAC(a[19], a[35]); SQRADDAC(a[20], a[34]); SQRADDAC(a[21], a[33]); SQRADDAC(a[22], a[32]); SQRADDAC(a[23], a[31]); SQRADDAC(a[24], a[30]); SQRADDAC(a[25], a[29]); SQRADDAC(a[26], a[28]); SQRADDDB; SQRADD(a[27], a[27]); 
+   COMBA_STORE(b[54]);
+
+   /* output 55 */
+   CARRY_FORWARD;
+   SQRADDSC(a[8], a[47]); SQRADDAC(a[9], a[46]); SQRADDAC(a[10], a[45]); SQRADDAC(a[11], a[44]); SQRADDAC(a[12], a[43]); SQRADDAC(a[13], a[42]); SQRADDAC(a[14], a[41]); SQRADDAC(a[15], a[40]); SQRADDAC(a[16], a[39]); SQRADDAC(a[17], a[38]); SQRADDAC(a[18], a[37]); SQRADDAC(a[19], a[36]); SQRADDAC(a[20], a[35]); SQRADDAC(a[21], a[34]); SQRADDAC(a[22], a[33]); SQRADDAC(a[23], a[32]); SQRADDAC(a[24], a[31]); SQRADDAC(a[25], a[30]); SQRADDAC(a[26], a[29]); SQRADDAC(a[27], a[28]); SQRADDDB; 
+   COMBA_STORE(b[55]);
+
+   /* output 56 */
+   CARRY_FORWARD;
+   SQRADDSC(a[9], a[47]); SQRADDAC(a[10], a[46]); SQRADDAC(a[11], a[45]); SQRADDAC(a[12], a[44]); SQRADDAC(a[13], a[43]); SQRADDAC(a[14], a[42]); SQRADDAC(a[15], a[41]); SQRADDAC(a[16], a[40]); SQRADDAC(a[17], a[39]); SQRADDAC(a[18], a[38]); SQRADDAC(a[19], a[37]); SQRADDAC(a[20], a[36]); SQRADDAC(a[21], a[35]); SQRADDAC(a[22], a[34]); SQRADDAC(a[23], a[33]); SQRADDAC(a[24], a[32]); SQRADDAC(a[25], a[31]); SQRADDAC(a[26], a[30]); SQRADDAC(a[27], a[29]); SQRADDDB; SQRADD(a[28], a[28]); 
+   COMBA_STORE(b[56]);
+
+   /* output 57 */
+   CARRY_FORWARD;
+   SQRADDSC(a[10], a[47]); SQRADDAC(a[11], a[46]); SQRADDAC(a[12], a[45]); SQRADDAC(a[13], a[44]); SQRADDAC(a[14], a[43]); SQRADDAC(a[15], a[42]); SQRADDAC(a[16], a[41]); SQRADDAC(a[17], a[40]); SQRADDAC(a[18], a[39]); SQRADDAC(a[19], a[38]); SQRADDAC(a[20], a[37]); SQRADDAC(a[21], a[36]); SQRADDAC(a[22], a[35]); SQRADDAC(a[23], a[34]); SQRADDAC(a[24], a[33]); SQRADDAC(a[25], a[32]); SQRADDAC(a[26], a[31]); SQRADDAC(a[27], a[30]); SQRADDAC(a[28], a[29]); SQRADDDB; 
+   COMBA_STORE(b[57]);
+
+   /* output 58 */
+   CARRY_FORWARD;
+   SQRADDSC(a[11], a[47]); SQRADDAC(a[12], a[46]); SQRADDAC(a[13], a[45]); SQRADDAC(a[14], a[44]); SQRADDAC(a[15], a[43]); SQRADDAC(a[16], a[42]); SQRADDAC(a[17], a[41]); SQRADDAC(a[18], a[40]); SQRADDAC(a[19], a[39]); SQRADDAC(a[20], a[38]); SQRADDAC(a[21], a[37]); SQRADDAC(a[22], a[36]); SQRADDAC(a[23], a[35]); SQRADDAC(a[24], a[34]); SQRADDAC(a[25], a[33]); SQRADDAC(a[26], a[32]); SQRADDAC(a[27], a[31]); SQRADDAC(a[28], a[30]); SQRADDDB; SQRADD(a[29], a[29]); 
+   COMBA_STORE(b[58]);
+
+   /* output 59 */
+   CARRY_FORWARD;
+   SQRADDSC(a[12], a[47]); SQRADDAC(a[13], a[46]); SQRADDAC(a[14], a[45]); SQRADDAC(a[15], a[44]); SQRADDAC(a[16], a[43]); SQRADDAC(a[17], a[42]); SQRADDAC(a[18], a[41]); SQRADDAC(a[19], a[40]); SQRADDAC(a[20], a[39]); SQRADDAC(a[21], a[38]); SQRADDAC(a[22], a[37]); SQRADDAC(a[23], a[36]); SQRADDAC(a[24], a[35]); SQRADDAC(a[25], a[34]); SQRADDAC(a[26], a[33]); SQRADDAC(a[27], a[32]); SQRADDAC(a[28], a[31]); SQRADDAC(a[29], a[30]); SQRADDDB; 
+   COMBA_STORE(b[59]);
+
+   /* output 60 */
+   CARRY_FORWARD;
+   SQRADDSC(a[13], a[47]); SQRADDAC(a[14], a[46]); SQRADDAC(a[15], a[45]); SQRADDAC(a[16], a[44]); SQRADDAC(a[17], a[43]); SQRADDAC(a[18], a[42]); SQRADDAC(a[19], a[41]); SQRADDAC(a[20], a[40]); SQRADDAC(a[21], a[39]); SQRADDAC(a[22], a[38]); SQRADDAC(a[23], a[37]); SQRADDAC(a[24], a[36]); SQRADDAC(a[25], a[35]); SQRADDAC(a[26], a[34]); SQRADDAC(a[27], a[33]); SQRADDAC(a[28], a[32]); SQRADDAC(a[29], a[31]); SQRADDDB; SQRADD(a[30], a[30]); 
+   COMBA_STORE(b[60]);
+
+   /* output 61 */
+   CARRY_FORWARD;
+   SQRADDSC(a[14], a[47]); SQRADDAC(a[15], a[46]); SQRADDAC(a[16], a[45]); SQRADDAC(a[17], a[44]); SQRADDAC(a[18], a[43]); SQRADDAC(a[19], a[42]); SQRADDAC(a[20], a[41]); SQRADDAC(a[21], a[40]); SQRADDAC(a[22], a[39]); SQRADDAC(a[23], a[38]); SQRADDAC(a[24], a[37]); SQRADDAC(a[25], a[36]); SQRADDAC(a[26], a[35]); SQRADDAC(a[27], a[34]); SQRADDAC(a[28], a[33]); SQRADDAC(a[29], a[32]); SQRADDAC(a[30], a[31]); SQRADDDB; 
+   COMBA_STORE(b[61]);
+
+   /* output 62 */
+   CARRY_FORWARD;
+   SQRADDSC(a[15], a[47]); SQRADDAC(a[16], a[46]); SQRADDAC(a[17], a[45]); SQRADDAC(a[18], a[44]); SQRADDAC(a[19], a[43]); SQRADDAC(a[20], a[42]); SQRADDAC(a[21], a[41]); SQRADDAC(a[22], a[40]); SQRADDAC(a[23], a[39]); SQRADDAC(a[24], a[38]); SQRADDAC(a[25], a[37]); SQRADDAC(a[26], a[36]); SQRADDAC(a[27], a[35]); SQRADDAC(a[28], a[34]); SQRADDAC(a[29], a[33]); SQRADDAC(a[30], a[32]); SQRADDDB; SQRADD(a[31], a[31]); 
+   COMBA_STORE(b[62]);
+
+   /* output 63 */
+   CARRY_FORWARD;
+   SQRADDSC(a[16], a[47]); SQRADDAC(a[17], a[46]); SQRADDAC(a[18], a[45]); SQRADDAC(a[19], a[44]); SQRADDAC(a[20], a[43]); SQRADDAC(a[21], a[42]); SQRADDAC(a[22], a[41]); SQRADDAC(a[23], a[40]); SQRADDAC(a[24], a[39]); SQRADDAC(a[25], a[38]); SQRADDAC(a[26], a[37]); SQRADDAC(a[27], a[36]); SQRADDAC(a[28], a[35]); SQRADDAC(a[29], a[34]); SQRADDAC(a[30], a[33]); SQRADDAC(a[31], a[32]); SQRADDDB; 
+   COMBA_STORE(b[63]);
+
+   /* output 64 */
+   CARRY_FORWARD;
+   SQRADDSC(a[17], a[47]); SQRADDAC(a[18], a[46]); SQRADDAC(a[19], a[45]); SQRADDAC(a[20], a[44]); SQRADDAC(a[21], a[43]); SQRADDAC(a[22], a[42]); SQRADDAC(a[23], a[41]); SQRADDAC(a[24], a[40]); SQRADDAC(a[25], a[39]); SQRADDAC(a[26], a[38]); SQRADDAC(a[27], a[37]); SQRADDAC(a[28], a[36]); SQRADDAC(a[29], a[35]); SQRADDAC(a[30], a[34]); SQRADDAC(a[31], a[33]); SQRADDDB; SQRADD(a[32], a[32]); 
+   COMBA_STORE(b[64]);
+
+   /* output 65 */
+   CARRY_FORWARD;
+   SQRADDSC(a[18], a[47]); SQRADDAC(a[19], a[46]); SQRADDAC(a[20], a[45]); SQRADDAC(a[21], a[44]); SQRADDAC(a[22], a[43]); SQRADDAC(a[23], a[42]); SQRADDAC(a[24], a[41]); SQRADDAC(a[25], a[40]); SQRADDAC(a[26], a[39]); SQRADDAC(a[27], a[38]); SQRADDAC(a[28], a[37]); SQRADDAC(a[29], a[36]); SQRADDAC(a[30], a[35]); SQRADDAC(a[31], a[34]); SQRADDAC(a[32], a[33]); SQRADDDB; 
+   COMBA_STORE(b[65]);
+
+   /* output 66 */
+   CARRY_FORWARD;
+   SQRADDSC(a[19], a[47]); SQRADDAC(a[20], a[46]); SQRADDAC(a[21], a[45]); SQRADDAC(a[22], a[44]); SQRADDAC(a[23], a[43]); SQRADDAC(a[24], a[42]); SQRADDAC(a[25], a[41]); SQRADDAC(a[26], a[40]); SQRADDAC(a[27], a[39]); SQRADDAC(a[28], a[38]); SQRADDAC(a[29], a[37]); SQRADDAC(a[30], a[36]); SQRADDAC(a[31], a[35]); SQRADDAC(a[32], a[34]); SQRADDDB; SQRADD(a[33], a[33]); 
+   COMBA_STORE(b[66]);
+
+   /* output 67 */
+   CARRY_FORWARD;
+   SQRADDSC(a[20], a[47]); SQRADDAC(a[21], a[46]); SQRADDAC(a[22], a[45]); SQRADDAC(a[23], a[44]); SQRADDAC(a[24], a[43]); SQRADDAC(a[25], a[42]); SQRADDAC(a[26], a[41]); SQRADDAC(a[27], a[40]); SQRADDAC(a[28], a[39]); SQRADDAC(a[29], a[38]); SQRADDAC(a[30], a[37]); SQRADDAC(a[31], a[36]); SQRADDAC(a[32], a[35]); SQRADDAC(a[33], a[34]); SQRADDDB; 
+   COMBA_STORE(b[67]);
+
+   /* output 68 */
+   CARRY_FORWARD;
+   SQRADDSC(a[21], a[47]); SQRADDAC(a[22], a[46]); SQRADDAC(a[23], a[45]); SQRADDAC(a[24], a[44]); SQRADDAC(a[25], a[43]); SQRADDAC(a[26], a[42]); SQRADDAC(a[27], a[41]); SQRADDAC(a[28], a[40]); SQRADDAC(a[29], a[39]); SQRADDAC(a[30], a[38]); SQRADDAC(a[31], a[37]); SQRADDAC(a[32], a[36]); SQRADDAC(a[33], a[35]); SQRADDDB; SQRADD(a[34], a[34]); 
+   COMBA_STORE(b[68]);
+
+   /* output 69 */
+   CARRY_FORWARD;
+   SQRADDSC(a[22], a[47]); SQRADDAC(a[23], a[46]); SQRADDAC(a[24], a[45]); SQRADDAC(a[25], a[44]); SQRADDAC(a[26], a[43]); SQRADDAC(a[27], a[42]); SQRADDAC(a[28], a[41]); SQRADDAC(a[29], a[40]); SQRADDAC(a[30], a[39]); SQRADDAC(a[31], a[38]); SQRADDAC(a[32], a[37]); SQRADDAC(a[33], a[36]); SQRADDAC(a[34], a[35]); SQRADDDB; 
+   COMBA_STORE(b[69]);
+
+   /* output 70 */
+   CARRY_FORWARD;
+   SQRADDSC(a[23], a[47]); SQRADDAC(a[24], a[46]); SQRADDAC(a[25], a[45]); SQRADDAC(a[26], a[44]); SQRADDAC(a[27], a[43]); SQRADDAC(a[28], a[42]); SQRADDAC(a[29], a[41]); SQRADDAC(a[30], a[40]); SQRADDAC(a[31], a[39]); SQRADDAC(a[32], a[38]); SQRADDAC(a[33], a[37]); SQRADDAC(a[34], a[36]); SQRADDDB; SQRADD(a[35], a[35]); 
+   COMBA_STORE(b[70]);
+
+   /* output 71 */
+   CARRY_FORWARD;
+   SQRADDSC(a[24], a[47]); SQRADDAC(a[25], a[46]); SQRADDAC(a[26], a[45]); SQRADDAC(a[27], a[44]); SQRADDAC(a[28], a[43]); SQRADDAC(a[29], a[42]); SQRADDAC(a[30], a[41]); SQRADDAC(a[31], a[40]); SQRADDAC(a[32], a[39]); SQRADDAC(a[33], a[38]); SQRADDAC(a[34], a[37]); SQRADDAC(a[35], a[36]); SQRADDDB; 
+   COMBA_STORE(b[71]);
+
+   /* output 72 */
+   CARRY_FORWARD;
+   SQRADDSC(a[25], a[47]); SQRADDAC(a[26], a[46]); SQRADDAC(a[27], a[45]); SQRADDAC(a[28], a[44]); SQRADDAC(a[29], a[43]); SQRADDAC(a[30], a[42]); SQRADDAC(a[31], a[41]); SQRADDAC(a[32], a[40]); SQRADDAC(a[33], a[39]); SQRADDAC(a[34], a[38]); SQRADDAC(a[35], a[37]); SQRADDDB; SQRADD(a[36], a[36]); 
+   COMBA_STORE(b[72]);
+
+   /* output 73 */
+   CARRY_FORWARD;
+   SQRADDSC(a[26], a[47]); SQRADDAC(a[27], a[46]); SQRADDAC(a[28], a[45]); SQRADDAC(a[29], a[44]); SQRADDAC(a[30], a[43]); SQRADDAC(a[31], a[42]); SQRADDAC(a[32], a[41]); SQRADDAC(a[33], a[40]); SQRADDAC(a[34], a[39]); SQRADDAC(a[35], a[38]); SQRADDAC(a[36], a[37]); SQRADDDB; 
+   COMBA_STORE(b[73]);
+
+   /* output 74 */
+   CARRY_FORWARD;
+   SQRADDSC(a[27], a[47]); SQRADDAC(a[28], a[46]); SQRADDAC(a[29], a[45]); SQRADDAC(a[30], a[44]); SQRADDAC(a[31], a[43]); SQRADDAC(a[32], a[42]); SQRADDAC(a[33], a[41]); SQRADDAC(a[34], a[40]); SQRADDAC(a[35], a[39]); SQRADDAC(a[36], a[38]); SQRADDDB; SQRADD(a[37], a[37]); 
+   COMBA_STORE(b[74]);
+
+   /* output 75 */
+   CARRY_FORWARD;
+   SQRADDSC(a[28], a[47]); SQRADDAC(a[29], a[46]); SQRADDAC(a[30], a[45]); SQRADDAC(a[31], a[44]); SQRADDAC(a[32], a[43]); SQRADDAC(a[33], a[42]); SQRADDAC(a[34], a[41]); SQRADDAC(a[35], a[40]); SQRADDAC(a[36], a[39]); SQRADDAC(a[37], a[38]); SQRADDDB; 
+   COMBA_STORE(b[75]);
+
+   /* output 76 */
+   CARRY_FORWARD;
+   SQRADDSC(a[29], a[47]); SQRADDAC(a[30], a[46]); SQRADDAC(a[31], a[45]); SQRADDAC(a[32], a[44]); SQRADDAC(a[33], a[43]); SQRADDAC(a[34], a[42]); SQRADDAC(a[35], a[41]); SQRADDAC(a[36], a[40]); SQRADDAC(a[37], a[39]); SQRADDDB; SQRADD(a[38], a[38]); 
+   COMBA_STORE(b[76]);
+
+   /* output 77 */
+   CARRY_FORWARD;
+   SQRADDSC(a[30], a[47]); SQRADDAC(a[31], a[46]); SQRADDAC(a[32], a[45]); SQRADDAC(a[33], a[44]); SQRADDAC(a[34], a[43]); SQRADDAC(a[35], a[42]); SQRADDAC(a[36], a[41]); SQRADDAC(a[37], a[40]); SQRADDAC(a[38], a[39]); SQRADDDB; 
+   COMBA_STORE(b[77]);
+
+   /* output 78 */
+   CARRY_FORWARD;
+   SQRADDSC(a[31], a[47]); SQRADDAC(a[32], a[46]); SQRADDAC(a[33], a[45]); SQRADDAC(a[34], a[44]); SQRADDAC(a[35], a[43]); SQRADDAC(a[36], a[42]); SQRADDAC(a[37], a[41]); SQRADDAC(a[38], a[40]); SQRADDDB; SQRADD(a[39], a[39]); 
+   COMBA_STORE(b[78]);
+
+   /* output 79 */
+   CARRY_FORWARD;
+   SQRADDSC(a[32], a[47]); SQRADDAC(a[33], a[46]); SQRADDAC(a[34], a[45]); SQRADDAC(a[35], a[44]); SQRADDAC(a[36], a[43]); SQRADDAC(a[37], a[42]); SQRADDAC(a[38], a[41]); SQRADDAC(a[39], a[40]); SQRADDDB; 
+   COMBA_STORE(b[79]);
+
+   /* output 80 */
+   CARRY_FORWARD;
+   SQRADDSC(a[33], a[47]); SQRADDAC(a[34], a[46]); SQRADDAC(a[35], a[45]); SQRADDAC(a[36], a[44]); SQRADDAC(a[37], a[43]); SQRADDAC(a[38], a[42]); SQRADDAC(a[39], a[41]); SQRADDDB; SQRADD(a[40], a[40]); 
+   COMBA_STORE(b[80]);
+
+   /* output 81 */
+   CARRY_FORWARD;
+   SQRADDSC(a[34], a[47]); SQRADDAC(a[35], a[46]); SQRADDAC(a[36], a[45]); SQRADDAC(a[37], a[44]); SQRADDAC(a[38], a[43]); SQRADDAC(a[39], a[42]); SQRADDAC(a[40], a[41]); SQRADDDB; 
+   COMBA_STORE(b[81]);
+
+   /* output 82 */
+   CARRY_FORWARD;
+   SQRADDSC(a[35], a[47]); SQRADDAC(a[36], a[46]); SQRADDAC(a[37], a[45]); SQRADDAC(a[38], a[44]); SQRADDAC(a[39], a[43]); SQRADDAC(a[40], a[42]); SQRADDDB; SQRADD(a[41], a[41]); 
+   COMBA_STORE(b[82]);
+
+   /* output 83 */
+   CARRY_FORWARD;
+   SQRADDSC(a[36], a[47]); SQRADDAC(a[37], a[46]); SQRADDAC(a[38], a[45]); SQRADDAC(a[39], a[44]); SQRADDAC(a[40], a[43]); SQRADDAC(a[41], a[42]); SQRADDDB; 
+   COMBA_STORE(b[83]);
+
+   /* output 84 */
+   CARRY_FORWARD;
+   SQRADDSC(a[37], a[47]); SQRADDAC(a[38], a[46]); SQRADDAC(a[39], a[45]); SQRADDAC(a[40], a[44]); SQRADDAC(a[41], a[43]); SQRADDDB; SQRADD(a[42], a[42]); 
+   COMBA_STORE(b[84]);
+
+   /* output 85 */
+   CARRY_FORWARD;
+   SQRADDSC(a[38], a[47]); SQRADDAC(a[39], a[46]); SQRADDAC(a[40], a[45]); SQRADDAC(a[41], a[44]); SQRADDAC(a[42], a[43]); SQRADDDB; 
+   COMBA_STORE(b[85]);
+
+   /* output 86 */
+   CARRY_FORWARD;
+   SQRADDSC(a[39], a[47]); SQRADDAC(a[40], a[46]); SQRADDAC(a[41], a[45]); SQRADDAC(a[42], a[44]); SQRADDDB; SQRADD(a[43], a[43]); 
+   COMBA_STORE(b[86]);
+
+   /* output 87 */
+   CARRY_FORWARD;
+   SQRADDSC(a[40], a[47]); SQRADDAC(a[41], a[46]); SQRADDAC(a[42], a[45]); SQRADDAC(a[43], a[44]); SQRADDDB; 
+   COMBA_STORE(b[87]);
+
+   /* output 88 */
+   CARRY_FORWARD;
+   SQRADDSC(a[41], a[47]); SQRADDAC(a[42], a[46]); SQRADDAC(a[43], a[45]); SQRADDDB; SQRADD(a[44], a[44]); 
+   COMBA_STORE(b[88]);
+
+   /* output 89 */
+   CARRY_FORWARD;
+   SQRADDSC(a[42], a[47]); SQRADDAC(a[43], a[46]); SQRADDAC(a[44], a[45]); SQRADDDB; 
+   COMBA_STORE(b[89]);
+
+   /* output 90 */
+   CARRY_FORWARD;
+   SQRADD2(a[43], a[47]); SQRADD2(a[44], a[46]); SQRADD(a[45], a[45]); 
+   COMBA_STORE(b[90]);
+
+   /* output 91 */
+   CARRY_FORWARD;
+   SQRADD2(a[44], a[47]); SQRADD2(a[45], a[46]); 
+   COMBA_STORE(b[91]);
+
+   /* output 92 */
+   CARRY_FORWARD;
+   SQRADD2(a[45], a[47]); SQRADD(a[46], a[46]); 
+   COMBA_STORE(b[92]);
+
+   /* output 93 */
+   CARRY_FORWARD;
+   SQRADD2(a[46], a[47]); 
+   COMBA_STORE(b[93]);
+
+   /* output 94 */
+   CARRY_FORWARD;
+   SQRADD(a[47], a[47]); 
+   COMBA_STORE(b[94]);
+   COMBA_STORE2(b[95]);
+   COMBA_FINI;
+
+   B->used = 96;
+   B->sign = FP_ZPOS;
+   memcpy(B->dp, b, 96 * sizeof(fp_digit));
+   fp_clamp(B);
+}
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_6.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_6.i
new file mode 100644
index 0000000..bb2fd74
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_6.i
@@ -0,0 +1,100 @@
+/* fp_sqr_comba_6.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_SQR6
+void fp_sqr_comba6(fp_int *A, fp_int *B)
+{
+   fp_digit *a, b[12], c0, c1, c2, sc0, sc1, sc2;
+#ifdef TFM_ISO
+   fp_word tt;
+#endif
+
+   a = A->dp;
+   COMBA_START; 
+
+   /* clear carries */
+   CLEAR_CARRY;
+
+   /* output 0 */
+   SQRADD(a[0],a[0]);
+   COMBA_STORE(b[0]);
+
+   /* output 1 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[1]); 
+   COMBA_STORE(b[1]);
+
+   /* output 2 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[2]); SQRADD(a[1], a[1]); 
+   COMBA_STORE(b[2]);
+
+   /* output 3 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[3]); SQRADD2(a[1], a[2]); 
+   COMBA_STORE(b[3]);
+
+   /* output 4 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[4]); SQRADD2(a[1], a[3]); SQRADD(a[2], a[2]); 
+   COMBA_STORE(b[4]);
+
+   /* output 5 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[5]); SQRADDAC(a[1], a[4]); SQRADDAC(a[2], a[3]); SQRADDDB; 
+   COMBA_STORE(b[5]);
+
+   /* output 6 */
+   CARRY_FORWARD;
+   SQRADD2(a[1], a[5]); SQRADD2(a[2], a[4]); SQRADD(a[3], a[3]); 
+   COMBA_STORE(b[6]);
+
+   /* output 7 */
+   CARRY_FORWARD;
+   SQRADD2(a[2], a[5]); SQRADD2(a[3], a[4]); 
+   COMBA_STORE(b[7]);
+
+   /* output 8 */
+   CARRY_FORWARD;
+   SQRADD2(a[3], a[5]); SQRADD(a[4], a[4]); 
+   COMBA_STORE(b[8]);
+
+   /* output 9 */
+   CARRY_FORWARD;
+   SQRADD2(a[4], a[5]); 
+   COMBA_STORE(b[9]);
+
+   /* output 10 */
+   CARRY_FORWARD;
+   SQRADD(a[5], a[5]); 
+   COMBA_STORE(b[10]);
+   COMBA_STORE2(b[11]);
+   COMBA_FINI;
+
+   B->used = 12;
+   B->sign = FP_ZPOS;
+   memcpy(B->dp, b, 12 * sizeof(fp_digit));
+   fp_clamp(B);
+}
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_64.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_64.i
new file mode 100644
index 0000000..b74367a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_64.i
@@ -0,0 +1,680 @@
+/* fp_sqr_comba_64.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_SQR64
+void fp_sqr_comba64(fp_int *A, fp_int *B)
+{
+   fp_digit *a, b[128], c0, c1, c2, sc0, sc1, sc2;
+#ifdef TFM_ISO
+   fp_word   tt;   
+#endif   
+
+   a = A->dp;
+   COMBA_START; 
+
+   /* clear carries */
+   CLEAR_CARRY;
+
+   /* output 0 */
+   SQRADD(a[0],a[0]);
+   COMBA_STORE(b[0]);
+
+   /* output 1 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[1]); 
+   COMBA_STORE(b[1]);
+
+   /* output 2 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[2]); SQRADD(a[1], a[1]); 
+   COMBA_STORE(b[2]);
+
+   /* output 3 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[3]); SQRADD2(a[1], a[2]); 
+   COMBA_STORE(b[3]);
+
+   /* output 4 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[4]); SQRADD2(a[1], a[3]); SQRADD(a[2], a[2]); 
+   COMBA_STORE(b[4]);
+
+   /* output 5 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[5]); SQRADDAC(a[1], a[4]); SQRADDAC(a[2], a[3]); SQRADDDB; 
+   COMBA_STORE(b[5]);
+
+   /* output 6 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[6]); SQRADDAC(a[1], a[5]); SQRADDAC(a[2], a[4]); SQRADDDB; SQRADD(a[3], a[3]); 
+   COMBA_STORE(b[6]);
+
+   /* output 7 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[7]); SQRADDAC(a[1], a[6]); SQRADDAC(a[2], a[5]); SQRADDAC(a[3], a[4]); SQRADDDB; 
+   COMBA_STORE(b[7]);
+
+   /* output 8 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[8]); SQRADDAC(a[1], a[7]); SQRADDAC(a[2], a[6]); SQRADDAC(a[3], a[5]); SQRADDDB; SQRADD(a[4], a[4]); 
+   COMBA_STORE(b[8]);
+
+   /* output 9 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[9]); SQRADDAC(a[1], a[8]); SQRADDAC(a[2], a[7]); SQRADDAC(a[3], a[6]); SQRADDAC(a[4], a[5]); SQRADDDB; 
+   COMBA_STORE(b[9]);
+
+   /* output 10 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[10]); SQRADDAC(a[1], a[9]); SQRADDAC(a[2], a[8]); SQRADDAC(a[3], a[7]); SQRADDAC(a[4], a[6]); SQRADDDB; SQRADD(a[5], a[5]); 
+   COMBA_STORE(b[10]);
+
+   /* output 11 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[11]); SQRADDAC(a[1], a[10]); SQRADDAC(a[2], a[9]); SQRADDAC(a[3], a[8]); SQRADDAC(a[4], a[7]); SQRADDAC(a[5], a[6]); SQRADDDB; 
+   COMBA_STORE(b[11]);
+
+   /* output 12 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[12]); SQRADDAC(a[1], a[11]); SQRADDAC(a[2], a[10]); SQRADDAC(a[3], a[9]); SQRADDAC(a[4], a[8]); SQRADDAC(a[5], a[7]); SQRADDDB; SQRADD(a[6], a[6]); 
+   COMBA_STORE(b[12]);
+
+   /* output 13 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[13]); SQRADDAC(a[1], a[12]); SQRADDAC(a[2], a[11]); SQRADDAC(a[3], a[10]); SQRADDAC(a[4], a[9]); SQRADDAC(a[5], a[8]); SQRADDAC(a[6], a[7]); SQRADDDB; 
+   COMBA_STORE(b[13]);
+
+   /* output 14 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[14]); SQRADDAC(a[1], a[13]); SQRADDAC(a[2], a[12]); SQRADDAC(a[3], a[11]); SQRADDAC(a[4], a[10]); SQRADDAC(a[5], a[9]); SQRADDAC(a[6], a[8]); SQRADDDB; SQRADD(a[7], a[7]); 
+   COMBA_STORE(b[14]);
+
+   /* output 15 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[15]); SQRADDAC(a[1], a[14]); SQRADDAC(a[2], a[13]); SQRADDAC(a[3], a[12]); SQRADDAC(a[4], a[11]); SQRADDAC(a[5], a[10]); SQRADDAC(a[6], a[9]); SQRADDAC(a[7], a[8]); SQRADDDB; 
+   COMBA_STORE(b[15]);
+
+   /* output 16 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[16]); SQRADDAC(a[1], a[15]); SQRADDAC(a[2], a[14]); SQRADDAC(a[3], a[13]); SQRADDAC(a[4], a[12]); SQRADDAC(a[5], a[11]); SQRADDAC(a[6], a[10]); SQRADDAC(a[7], a[9]); SQRADDDB; SQRADD(a[8], a[8]); 
+   COMBA_STORE(b[16]);
+
+   /* output 17 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[17]); SQRADDAC(a[1], a[16]); SQRADDAC(a[2], a[15]); SQRADDAC(a[3], a[14]); SQRADDAC(a[4], a[13]); SQRADDAC(a[5], a[12]); SQRADDAC(a[6], a[11]); SQRADDAC(a[7], a[10]); SQRADDAC(a[8], a[9]); SQRADDDB; 
+   COMBA_STORE(b[17]);
+
+   /* output 18 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[18]); SQRADDAC(a[1], a[17]); SQRADDAC(a[2], a[16]); SQRADDAC(a[3], a[15]); SQRADDAC(a[4], a[14]); SQRADDAC(a[5], a[13]); SQRADDAC(a[6], a[12]); SQRADDAC(a[7], a[11]); SQRADDAC(a[8], a[10]); SQRADDDB; SQRADD(a[9], a[9]); 
+   COMBA_STORE(b[18]);
+
+   /* output 19 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[19]); SQRADDAC(a[1], a[18]); SQRADDAC(a[2], a[17]); SQRADDAC(a[3], a[16]); SQRADDAC(a[4], a[15]); SQRADDAC(a[5], a[14]); SQRADDAC(a[6], a[13]); SQRADDAC(a[7], a[12]); SQRADDAC(a[8], a[11]); SQRADDAC(a[9], a[10]); SQRADDDB; 
+   COMBA_STORE(b[19]);
+
+   /* output 20 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[20]); SQRADDAC(a[1], a[19]); SQRADDAC(a[2], a[18]); SQRADDAC(a[3], a[17]); SQRADDAC(a[4], a[16]); SQRADDAC(a[5], a[15]); SQRADDAC(a[6], a[14]); SQRADDAC(a[7], a[13]); SQRADDAC(a[8], a[12]); SQRADDAC(a[9], a[11]); SQRADDDB; SQRADD(a[10], a[10]); 
+   COMBA_STORE(b[20]);
+
+   /* output 21 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[21]); SQRADDAC(a[1], a[20]); SQRADDAC(a[2], a[19]); SQRADDAC(a[3], a[18]); SQRADDAC(a[4], a[17]); SQRADDAC(a[5], a[16]); SQRADDAC(a[6], a[15]); SQRADDAC(a[7], a[14]); SQRADDAC(a[8], a[13]); SQRADDAC(a[9], a[12]); SQRADDAC(a[10], a[11]); SQRADDDB; 
+   COMBA_STORE(b[21]);
+
+   /* output 22 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[22]); SQRADDAC(a[1], a[21]); SQRADDAC(a[2], a[20]); SQRADDAC(a[3], a[19]); SQRADDAC(a[4], a[18]); SQRADDAC(a[5], a[17]); SQRADDAC(a[6], a[16]); SQRADDAC(a[7], a[15]); SQRADDAC(a[8], a[14]); SQRADDAC(a[9], a[13]); SQRADDAC(a[10], a[12]); SQRADDDB; SQRADD(a[11], a[11]); 
+   COMBA_STORE(b[22]);
+
+   /* output 23 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[23]); SQRADDAC(a[1], a[22]); SQRADDAC(a[2], a[21]); SQRADDAC(a[3], a[20]); SQRADDAC(a[4], a[19]); SQRADDAC(a[5], a[18]); SQRADDAC(a[6], a[17]); SQRADDAC(a[7], a[16]); SQRADDAC(a[8], a[15]); SQRADDAC(a[9], a[14]); SQRADDAC(a[10], a[13]); SQRADDAC(a[11], a[12]); SQRADDDB; 
+   COMBA_STORE(b[23]);
+
+   /* output 24 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[24]); SQRADDAC(a[1], a[23]); SQRADDAC(a[2], a[22]); SQRADDAC(a[3], a[21]); SQRADDAC(a[4], a[20]); SQRADDAC(a[5], a[19]); SQRADDAC(a[6], a[18]); SQRADDAC(a[7], a[17]); SQRADDAC(a[8], a[16]); SQRADDAC(a[9], a[15]); SQRADDAC(a[10], a[14]); SQRADDAC(a[11], a[13]); SQRADDDB; SQRADD(a[12], a[12]); 
+   COMBA_STORE(b[24]);
+
+   /* output 25 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[25]); SQRADDAC(a[1], a[24]); SQRADDAC(a[2], a[23]); SQRADDAC(a[3], a[22]); SQRADDAC(a[4], a[21]); SQRADDAC(a[5], a[20]); SQRADDAC(a[6], a[19]); SQRADDAC(a[7], a[18]); SQRADDAC(a[8], a[17]); SQRADDAC(a[9], a[16]); SQRADDAC(a[10], a[15]); SQRADDAC(a[11], a[14]); SQRADDAC(a[12], a[13]); SQRADDDB; 
+   COMBA_STORE(b[25]);
+
+   /* output 26 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[26]); SQRADDAC(a[1], a[25]); SQRADDAC(a[2], a[24]); SQRADDAC(a[3], a[23]); SQRADDAC(a[4], a[22]); SQRADDAC(a[5], a[21]); SQRADDAC(a[6], a[20]); SQRADDAC(a[7], a[19]); SQRADDAC(a[8], a[18]); SQRADDAC(a[9], a[17]); SQRADDAC(a[10], a[16]); SQRADDAC(a[11], a[15]); SQRADDAC(a[12], a[14]); SQRADDDB; SQRADD(a[13], a[13]); 
+   COMBA_STORE(b[26]);
+
+   /* output 27 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[27]); SQRADDAC(a[1], a[26]); SQRADDAC(a[2], a[25]); SQRADDAC(a[3], a[24]); SQRADDAC(a[4], a[23]); SQRADDAC(a[5], a[22]); SQRADDAC(a[6], a[21]); SQRADDAC(a[7], a[20]); SQRADDAC(a[8], a[19]); SQRADDAC(a[9], a[18]); SQRADDAC(a[10], a[17]); SQRADDAC(a[11], a[16]); SQRADDAC(a[12], a[15]); SQRADDAC(a[13], a[14]); SQRADDDB; 
+   COMBA_STORE(b[27]);
+
+   /* output 28 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[28]); SQRADDAC(a[1], a[27]); SQRADDAC(a[2], a[26]); SQRADDAC(a[3], a[25]); SQRADDAC(a[4], a[24]); SQRADDAC(a[5], a[23]); SQRADDAC(a[6], a[22]); SQRADDAC(a[7], a[21]); SQRADDAC(a[8], a[20]); SQRADDAC(a[9], a[19]); SQRADDAC(a[10], a[18]); SQRADDAC(a[11], a[17]); SQRADDAC(a[12], a[16]); SQRADDAC(a[13], a[15]); SQRADDDB; SQRADD(a[14], a[14]); 
+   COMBA_STORE(b[28]);
+
+   /* output 29 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[29]); SQRADDAC(a[1], a[28]); SQRADDAC(a[2], a[27]); SQRADDAC(a[3], a[26]); SQRADDAC(a[4], a[25]); SQRADDAC(a[5], a[24]); SQRADDAC(a[6], a[23]); SQRADDAC(a[7], a[22]); SQRADDAC(a[8], a[21]); SQRADDAC(a[9], a[20]); SQRADDAC(a[10], a[19]); SQRADDAC(a[11], a[18]); SQRADDAC(a[12], a[17]); SQRADDAC(a[13], a[16]); SQRADDAC(a[14], a[15]); SQRADDDB; 
+   COMBA_STORE(b[29]);
+
+   /* output 30 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[30]); SQRADDAC(a[1], a[29]); SQRADDAC(a[2], a[28]); SQRADDAC(a[3], a[27]); SQRADDAC(a[4], a[26]); SQRADDAC(a[5], a[25]); SQRADDAC(a[6], a[24]); SQRADDAC(a[7], a[23]); SQRADDAC(a[8], a[22]); SQRADDAC(a[9], a[21]); SQRADDAC(a[10], a[20]); SQRADDAC(a[11], a[19]); SQRADDAC(a[12], a[18]); SQRADDAC(a[13], a[17]); SQRADDAC(a[14], a[16]); SQRADDDB; SQRADD(a[15], a[15]); 
+   COMBA_STORE(b[30]);
+
+   /* output 31 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[31]); SQRADDAC(a[1], a[30]); SQRADDAC(a[2], a[29]); SQRADDAC(a[3], a[28]); SQRADDAC(a[4], a[27]); SQRADDAC(a[5], a[26]); SQRADDAC(a[6], a[25]); SQRADDAC(a[7], a[24]); SQRADDAC(a[8], a[23]); SQRADDAC(a[9], a[22]); SQRADDAC(a[10], a[21]); SQRADDAC(a[11], a[20]); SQRADDAC(a[12], a[19]); SQRADDAC(a[13], a[18]); SQRADDAC(a[14], a[17]); SQRADDAC(a[15], a[16]); SQRADDDB; 
+   COMBA_STORE(b[31]);
+
+   /* output 32 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[32]); SQRADDAC(a[1], a[31]); SQRADDAC(a[2], a[30]); SQRADDAC(a[3], a[29]); SQRADDAC(a[4], a[28]); SQRADDAC(a[5], a[27]); SQRADDAC(a[6], a[26]); SQRADDAC(a[7], a[25]); SQRADDAC(a[8], a[24]); SQRADDAC(a[9], a[23]); SQRADDAC(a[10], a[22]); SQRADDAC(a[11], a[21]); SQRADDAC(a[12], a[20]); SQRADDAC(a[13], a[19]); SQRADDAC(a[14], a[18]); SQRADDAC(a[15], a[17]); SQRADDDB; SQRADD(a[16], a[16]); 
+   COMBA_STORE(b[32]);
+
+   /* output 33 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[33]); SQRADDAC(a[1], a[32]); SQRADDAC(a[2], a[31]); SQRADDAC(a[3], a[30]); SQRADDAC(a[4], a[29]); SQRADDAC(a[5], a[28]); SQRADDAC(a[6], a[27]); SQRADDAC(a[7], a[26]); SQRADDAC(a[8], a[25]); SQRADDAC(a[9], a[24]); SQRADDAC(a[10], a[23]); SQRADDAC(a[11], a[22]); SQRADDAC(a[12], a[21]); SQRADDAC(a[13], a[20]); SQRADDAC(a[14], a[19]); SQRADDAC(a[15], a[18]); SQRADDAC(a[16], a[17]); SQRADDDB; 
+   COMBA_STORE(b[33]);
+
+   /* output 34 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[34]); SQRADDAC(a[1], a[33]); SQRADDAC(a[2], a[32]); SQRADDAC(a[3], a[31]); SQRADDAC(a[4], a[30]); SQRADDAC(a[5], a[29]); SQRADDAC(a[6], a[28]); SQRADDAC(a[7], a[27]); SQRADDAC(a[8], a[26]); SQRADDAC(a[9], a[25]); SQRADDAC(a[10], a[24]); SQRADDAC(a[11], a[23]); SQRADDAC(a[12], a[22]); SQRADDAC(a[13], a[21]); SQRADDAC(a[14], a[20]); SQRADDAC(a[15], a[19]); SQRADDAC(a[16], a[18]); SQRADDDB; SQRADD(a[17], a[17]); 
+   COMBA_STORE(b[34]);
+
+   /* output 35 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[35]); SQRADDAC(a[1], a[34]); SQRADDAC(a[2], a[33]); SQRADDAC(a[3], a[32]); SQRADDAC(a[4], a[31]); SQRADDAC(a[5], a[30]); SQRADDAC(a[6], a[29]); SQRADDAC(a[7], a[28]); SQRADDAC(a[8], a[27]); SQRADDAC(a[9], a[26]); SQRADDAC(a[10], a[25]); SQRADDAC(a[11], a[24]); SQRADDAC(a[12], a[23]); SQRADDAC(a[13], a[22]); SQRADDAC(a[14], a[21]); SQRADDAC(a[15], a[20]); SQRADDAC(a[16], a[19]); SQRADDAC(a[17], a[18]); SQRADDDB; 
+   COMBA_STORE(b[35]);
+
+   /* output 36 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[36]); SQRADDAC(a[1], a[35]); SQRADDAC(a[2], a[34]); SQRADDAC(a[3], a[33]); SQRADDAC(a[4], a[32]); SQRADDAC(a[5], a[31]); SQRADDAC(a[6], a[30]); SQRADDAC(a[7], a[29]); SQRADDAC(a[8], a[28]); SQRADDAC(a[9], a[27]); SQRADDAC(a[10], a[26]); SQRADDAC(a[11], a[25]); SQRADDAC(a[12], a[24]); SQRADDAC(a[13], a[23]); SQRADDAC(a[14], a[22]); SQRADDAC(a[15], a[21]); SQRADDAC(a[16], a[20]); SQRADDAC(a[17], a[19]); SQRADDDB; SQRADD(a[18], a[18]); 
+   COMBA_STORE(b[36]);
+
+   /* output 37 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[37]); SQRADDAC(a[1], a[36]); SQRADDAC(a[2], a[35]); SQRADDAC(a[3], a[34]); SQRADDAC(a[4], a[33]); SQRADDAC(a[5], a[32]); SQRADDAC(a[6], a[31]); SQRADDAC(a[7], a[30]); SQRADDAC(a[8], a[29]); SQRADDAC(a[9], a[28]); SQRADDAC(a[10], a[27]); SQRADDAC(a[11], a[26]); SQRADDAC(a[12], a[25]); SQRADDAC(a[13], a[24]); SQRADDAC(a[14], a[23]); SQRADDAC(a[15], a[22]); SQRADDAC(a[16], a[21]); SQRADDAC(a[17], a[20]); SQRADDAC(a[18], a[19]); SQRADDDB; 
+   COMBA_STORE(b[37]);
+
+   /* output 38 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[38]); SQRADDAC(a[1], a[37]); SQRADDAC(a[2], a[36]); SQRADDAC(a[3], a[35]); SQRADDAC(a[4], a[34]); SQRADDAC(a[5], a[33]); SQRADDAC(a[6], a[32]); SQRADDAC(a[7], a[31]); SQRADDAC(a[8], a[30]); SQRADDAC(a[9], a[29]); SQRADDAC(a[10], a[28]); SQRADDAC(a[11], a[27]); SQRADDAC(a[12], a[26]); SQRADDAC(a[13], a[25]); SQRADDAC(a[14], a[24]); SQRADDAC(a[15], a[23]); SQRADDAC(a[16], a[22]); SQRADDAC(a[17], a[21]); SQRADDAC(a[18], a[20]); SQRADDDB; SQRADD(a[19], a[19]); 
+   COMBA_STORE(b[38]);
+
+   /* output 39 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[39]); SQRADDAC(a[1], a[38]); SQRADDAC(a[2], a[37]); SQRADDAC(a[3], a[36]); SQRADDAC(a[4], a[35]); SQRADDAC(a[5], a[34]); SQRADDAC(a[6], a[33]); SQRADDAC(a[7], a[32]); SQRADDAC(a[8], a[31]); SQRADDAC(a[9], a[30]); SQRADDAC(a[10], a[29]); SQRADDAC(a[11], a[28]); SQRADDAC(a[12], a[27]); SQRADDAC(a[13], a[26]); SQRADDAC(a[14], a[25]); SQRADDAC(a[15], a[24]); SQRADDAC(a[16], a[23]); SQRADDAC(a[17], a[22]); SQRADDAC(a[18], a[21]); SQRADDAC(a[19], a[20]); SQRADDDB; 
+   COMBA_STORE(b[39]);
+
+   /* output 40 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[40]); SQRADDAC(a[1], a[39]); SQRADDAC(a[2], a[38]); SQRADDAC(a[3], a[37]); SQRADDAC(a[4], a[36]); SQRADDAC(a[5], a[35]); SQRADDAC(a[6], a[34]); SQRADDAC(a[7], a[33]); SQRADDAC(a[8], a[32]); SQRADDAC(a[9], a[31]); SQRADDAC(a[10], a[30]); SQRADDAC(a[11], a[29]); SQRADDAC(a[12], a[28]); SQRADDAC(a[13], a[27]); SQRADDAC(a[14], a[26]); SQRADDAC(a[15], a[25]); SQRADDAC(a[16], a[24]); SQRADDAC(a[17], a[23]); SQRADDAC(a[18], a[22]); SQRADDAC(a[19], a[21]); SQRADDDB; SQRADD(a[20], a[20]); 
+   COMBA_STORE(b[40]);
+
+   /* output 41 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[41]); SQRADDAC(a[1], a[40]); SQRADDAC(a[2], a[39]); SQRADDAC(a[3], a[38]); SQRADDAC(a[4], a[37]); SQRADDAC(a[5], a[36]); SQRADDAC(a[6], a[35]); SQRADDAC(a[7], a[34]); SQRADDAC(a[8], a[33]); SQRADDAC(a[9], a[32]); SQRADDAC(a[10], a[31]); SQRADDAC(a[11], a[30]); SQRADDAC(a[12], a[29]); SQRADDAC(a[13], a[28]); SQRADDAC(a[14], a[27]); SQRADDAC(a[15], a[26]); SQRADDAC(a[16], a[25]); SQRADDAC(a[17], a[24]); SQRADDAC(a[18], a[23]); SQRADDAC(a[19], a[22]); SQRADDAC(a[20], a[21]); SQRADDDB; 
+   COMBA_STORE(b[41]);
+
+   /* output 42 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[42]); SQRADDAC(a[1], a[41]); SQRADDAC(a[2], a[40]); SQRADDAC(a[3], a[39]); SQRADDAC(a[4], a[38]); SQRADDAC(a[5], a[37]); SQRADDAC(a[6], a[36]); SQRADDAC(a[7], a[35]); SQRADDAC(a[8], a[34]); SQRADDAC(a[9], a[33]); SQRADDAC(a[10], a[32]); SQRADDAC(a[11], a[31]); SQRADDAC(a[12], a[30]); SQRADDAC(a[13], a[29]); SQRADDAC(a[14], a[28]); SQRADDAC(a[15], a[27]); SQRADDAC(a[16], a[26]); SQRADDAC(a[17], a[25]); SQRADDAC(a[18], a[24]); SQRADDAC(a[19], a[23]); SQRADDAC(a[20], a[22]); SQRADDDB; SQRADD(a[21], a[21]); 
+   COMBA_STORE(b[42]);
+
+   /* output 43 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[43]); SQRADDAC(a[1], a[42]); SQRADDAC(a[2], a[41]); SQRADDAC(a[3], a[40]); SQRADDAC(a[4], a[39]); SQRADDAC(a[5], a[38]); SQRADDAC(a[6], a[37]); SQRADDAC(a[7], a[36]); SQRADDAC(a[8], a[35]); SQRADDAC(a[9], a[34]); SQRADDAC(a[10], a[33]); SQRADDAC(a[11], a[32]); SQRADDAC(a[12], a[31]); SQRADDAC(a[13], a[30]); SQRADDAC(a[14], a[29]); SQRADDAC(a[15], a[28]); SQRADDAC(a[16], a[27]); SQRADDAC(a[17], a[26]); SQRADDAC(a[18], a[25]); SQRADDAC(a[19], a[24]); SQRADDAC(a[20], a[23]); SQRADDAC(a[21], a[22]); SQRADDDB; 
+   COMBA_STORE(b[43]);
+
+   /* output 44 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[44]); SQRADDAC(a[1], a[43]); SQRADDAC(a[2], a[42]); SQRADDAC(a[3], a[41]); SQRADDAC(a[4], a[40]); SQRADDAC(a[5], a[39]); SQRADDAC(a[6], a[38]); SQRADDAC(a[7], a[37]); SQRADDAC(a[8], a[36]); SQRADDAC(a[9], a[35]); SQRADDAC(a[10], a[34]); SQRADDAC(a[11], a[33]); SQRADDAC(a[12], a[32]); SQRADDAC(a[13], a[31]); SQRADDAC(a[14], a[30]); SQRADDAC(a[15], a[29]); SQRADDAC(a[16], a[28]); SQRADDAC(a[17], a[27]); SQRADDAC(a[18], a[26]); SQRADDAC(a[19], a[25]); SQRADDAC(a[20], a[24]); SQRADDAC(a[21], a[23]); SQRADDDB; SQRADD(a[22], a[22]); 
+   COMBA_STORE(b[44]);
+
+   /* output 45 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[45]); SQRADDAC(a[1], a[44]); SQRADDAC(a[2], a[43]); SQRADDAC(a[3], a[42]); SQRADDAC(a[4], a[41]); SQRADDAC(a[5], a[40]); SQRADDAC(a[6], a[39]); SQRADDAC(a[7], a[38]); SQRADDAC(a[8], a[37]); SQRADDAC(a[9], a[36]); SQRADDAC(a[10], a[35]); SQRADDAC(a[11], a[34]); SQRADDAC(a[12], a[33]); SQRADDAC(a[13], a[32]); SQRADDAC(a[14], a[31]); SQRADDAC(a[15], a[30]); SQRADDAC(a[16], a[29]); SQRADDAC(a[17], a[28]); SQRADDAC(a[18], a[27]); SQRADDAC(a[19], a[26]); SQRADDAC(a[20], a[25]); SQRADDAC(a[21], a[24]); SQRADDAC(a[22], a[23]); SQRADDDB; 
+   COMBA_STORE(b[45]);
+
+   /* output 46 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[46]); SQRADDAC(a[1], a[45]); SQRADDAC(a[2], a[44]); SQRADDAC(a[3], a[43]); SQRADDAC(a[4], a[42]); SQRADDAC(a[5], a[41]); SQRADDAC(a[6], a[40]); SQRADDAC(a[7], a[39]); SQRADDAC(a[8], a[38]); SQRADDAC(a[9], a[37]); SQRADDAC(a[10], a[36]); SQRADDAC(a[11], a[35]); SQRADDAC(a[12], a[34]); SQRADDAC(a[13], a[33]); SQRADDAC(a[14], a[32]); SQRADDAC(a[15], a[31]); SQRADDAC(a[16], a[30]); SQRADDAC(a[17], a[29]); SQRADDAC(a[18], a[28]); SQRADDAC(a[19], a[27]); SQRADDAC(a[20], a[26]); SQRADDAC(a[21], a[25]); SQRADDAC(a[22], a[24]); SQRADDDB; SQRADD(a[23], a[23]); 
+   COMBA_STORE(b[46]);
+
+   /* output 47 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[47]); SQRADDAC(a[1], a[46]); SQRADDAC(a[2], a[45]); SQRADDAC(a[3], a[44]); SQRADDAC(a[4], a[43]); SQRADDAC(a[5], a[42]); SQRADDAC(a[6], a[41]); SQRADDAC(a[7], a[40]); SQRADDAC(a[8], a[39]); SQRADDAC(a[9], a[38]); SQRADDAC(a[10], a[37]); SQRADDAC(a[11], a[36]); SQRADDAC(a[12], a[35]); SQRADDAC(a[13], a[34]); SQRADDAC(a[14], a[33]); SQRADDAC(a[15], a[32]); SQRADDAC(a[16], a[31]); SQRADDAC(a[17], a[30]); SQRADDAC(a[18], a[29]); SQRADDAC(a[19], a[28]); SQRADDAC(a[20], a[27]); SQRADDAC(a[21], a[26]); SQRADDAC(a[22], a[25]); SQRADDAC(a[23], a[24]); SQRADDDB; 
+   COMBA_STORE(b[47]);
+
+   /* output 48 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[48]); SQRADDAC(a[1], a[47]); SQRADDAC(a[2], a[46]); SQRADDAC(a[3], a[45]); SQRADDAC(a[4], a[44]); SQRADDAC(a[5], a[43]); SQRADDAC(a[6], a[42]); SQRADDAC(a[7], a[41]); SQRADDAC(a[8], a[40]); SQRADDAC(a[9], a[39]); SQRADDAC(a[10], a[38]); SQRADDAC(a[11], a[37]); SQRADDAC(a[12], a[36]); SQRADDAC(a[13], a[35]); SQRADDAC(a[14], a[34]); SQRADDAC(a[15], a[33]); SQRADDAC(a[16], a[32]); SQRADDAC(a[17], a[31]); SQRADDAC(a[18], a[30]); SQRADDAC(a[19], a[29]); SQRADDAC(a[20], a[28]); SQRADDAC(a[21], a[27]); SQRADDAC(a[22], a[26]); SQRADDAC(a[23], a[25]); SQRADDDB; SQRADD(a[24], a[24]); 
+   COMBA_STORE(b[48]);
+
+   /* output 49 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[49]); SQRADDAC(a[1], a[48]); SQRADDAC(a[2], a[47]); SQRADDAC(a[3], a[46]); SQRADDAC(a[4], a[45]); SQRADDAC(a[5], a[44]); SQRADDAC(a[6], a[43]); SQRADDAC(a[7], a[42]); SQRADDAC(a[8], a[41]); SQRADDAC(a[9], a[40]); SQRADDAC(a[10], a[39]); SQRADDAC(a[11], a[38]); SQRADDAC(a[12], a[37]); SQRADDAC(a[13], a[36]); SQRADDAC(a[14], a[35]); SQRADDAC(a[15], a[34]); SQRADDAC(a[16], a[33]); SQRADDAC(a[17], a[32]); SQRADDAC(a[18], a[31]); SQRADDAC(a[19], a[30]); SQRADDAC(a[20], a[29]); SQRADDAC(a[21], a[28]); SQRADDAC(a[22], a[27]); SQRADDAC(a[23], a[26]); SQRADDAC(a[24], a[25]); SQRADDDB; 
+   COMBA_STORE(b[49]);
+
+   /* output 50 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[50]); SQRADDAC(a[1], a[49]); SQRADDAC(a[2], a[48]); SQRADDAC(a[3], a[47]); SQRADDAC(a[4], a[46]); SQRADDAC(a[5], a[45]); SQRADDAC(a[6], a[44]); SQRADDAC(a[7], a[43]); SQRADDAC(a[8], a[42]); SQRADDAC(a[9], a[41]); SQRADDAC(a[10], a[40]); SQRADDAC(a[11], a[39]); SQRADDAC(a[12], a[38]); SQRADDAC(a[13], a[37]); SQRADDAC(a[14], a[36]); SQRADDAC(a[15], a[35]); SQRADDAC(a[16], a[34]); SQRADDAC(a[17], a[33]); SQRADDAC(a[18], a[32]); SQRADDAC(a[19], a[31]); SQRADDAC(a[20], a[30]); SQRADDAC(a[21], a[29]); SQRADDAC(a[22], a[28]); SQRADDAC(a[23], a[27]); SQRADDAC(a[24], a[26]); SQRADDDB; SQRADD(a[25], a[25]); 
+   COMBA_STORE(b[50]);
+
+   /* output 51 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[51]); SQRADDAC(a[1], a[50]); SQRADDAC(a[2], a[49]); SQRADDAC(a[3], a[48]); SQRADDAC(a[4], a[47]); SQRADDAC(a[5], a[46]); SQRADDAC(a[6], a[45]); SQRADDAC(a[7], a[44]); SQRADDAC(a[8], a[43]); SQRADDAC(a[9], a[42]); SQRADDAC(a[10], a[41]); SQRADDAC(a[11], a[40]); SQRADDAC(a[12], a[39]); SQRADDAC(a[13], a[38]); SQRADDAC(a[14], a[37]); SQRADDAC(a[15], a[36]); SQRADDAC(a[16], a[35]); SQRADDAC(a[17], a[34]); SQRADDAC(a[18], a[33]); SQRADDAC(a[19], a[32]); SQRADDAC(a[20], a[31]); SQRADDAC(a[21], a[30]); SQRADDAC(a[22], a[29]); SQRADDAC(a[23], a[28]); SQRADDAC(a[24], a[27]); SQRADDAC(a[25], a[26]); SQRADDDB; 
+   COMBA_STORE(b[51]);
+
+   /* output 52 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[52]); SQRADDAC(a[1], a[51]); SQRADDAC(a[2], a[50]); SQRADDAC(a[3], a[49]); SQRADDAC(a[4], a[48]); SQRADDAC(a[5], a[47]); SQRADDAC(a[6], a[46]); SQRADDAC(a[7], a[45]); SQRADDAC(a[8], a[44]); SQRADDAC(a[9], a[43]); SQRADDAC(a[10], a[42]); SQRADDAC(a[11], a[41]); SQRADDAC(a[12], a[40]); SQRADDAC(a[13], a[39]); SQRADDAC(a[14], a[38]); SQRADDAC(a[15], a[37]); SQRADDAC(a[16], a[36]); SQRADDAC(a[17], a[35]); SQRADDAC(a[18], a[34]); SQRADDAC(a[19], a[33]); SQRADDAC(a[20], a[32]); SQRADDAC(a[21], a[31]); SQRADDAC(a[22], a[30]); SQRADDAC(a[23], a[29]); SQRADDAC(a[24], a[28]); SQRADDAC(a[25], a[27]); SQRADDDB; SQRADD(a[26], a[26]); 
+   COMBA_STORE(b[52]);
+
+   /* output 53 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[53]); SQRADDAC(a[1], a[52]); SQRADDAC(a[2], a[51]); SQRADDAC(a[3], a[50]); SQRADDAC(a[4], a[49]); SQRADDAC(a[5], a[48]); SQRADDAC(a[6], a[47]); SQRADDAC(a[7], a[46]); SQRADDAC(a[8], a[45]); SQRADDAC(a[9], a[44]); SQRADDAC(a[10], a[43]); SQRADDAC(a[11], a[42]); SQRADDAC(a[12], a[41]); SQRADDAC(a[13], a[40]); SQRADDAC(a[14], a[39]); SQRADDAC(a[15], a[38]); SQRADDAC(a[16], a[37]); SQRADDAC(a[17], a[36]); SQRADDAC(a[18], a[35]); SQRADDAC(a[19], a[34]); SQRADDAC(a[20], a[33]); SQRADDAC(a[21], a[32]); SQRADDAC(a[22], a[31]); SQRADDAC(a[23], a[30]); SQRADDAC(a[24], a[29]); SQRADDAC(a[25], a[28]); SQRADDAC(a[26], a[27]); SQRADDDB; 
+   COMBA_STORE(b[53]);
+
+   /* output 54 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[54]); SQRADDAC(a[1], a[53]); SQRADDAC(a[2], a[52]); SQRADDAC(a[3], a[51]); SQRADDAC(a[4], a[50]); SQRADDAC(a[5], a[49]); SQRADDAC(a[6], a[48]); SQRADDAC(a[7], a[47]); SQRADDAC(a[8], a[46]); SQRADDAC(a[9], a[45]); SQRADDAC(a[10], a[44]); SQRADDAC(a[11], a[43]); SQRADDAC(a[12], a[42]); SQRADDAC(a[13], a[41]); SQRADDAC(a[14], a[40]); SQRADDAC(a[15], a[39]); SQRADDAC(a[16], a[38]); SQRADDAC(a[17], a[37]); SQRADDAC(a[18], a[36]); SQRADDAC(a[19], a[35]); SQRADDAC(a[20], a[34]); SQRADDAC(a[21], a[33]); SQRADDAC(a[22], a[32]); SQRADDAC(a[23], a[31]); SQRADDAC(a[24], a[30]); SQRADDAC(a[25], a[29]); SQRADDAC(a[26], a[28]); SQRADDDB; SQRADD(a[27], a[27]); 
+   COMBA_STORE(b[54]);
+
+   /* output 55 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[55]); SQRADDAC(a[1], a[54]); SQRADDAC(a[2], a[53]); SQRADDAC(a[3], a[52]); SQRADDAC(a[4], a[51]); SQRADDAC(a[5], a[50]); SQRADDAC(a[6], a[49]); SQRADDAC(a[7], a[48]); SQRADDAC(a[8], a[47]); SQRADDAC(a[9], a[46]); SQRADDAC(a[10], a[45]); SQRADDAC(a[11], a[44]); SQRADDAC(a[12], a[43]); SQRADDAC(a[13], a[42]); SQRADDAC(a[14], a[41]); SQRADDAC(a[15], a[40]); SQRADDAC(a[16], a[39]); SQRADDAC(a[17], a[38]); SQRADDAC(a[18], a[37]); SQRADDAC(a[19], a[36]); SQRADDAC(a[20], a[35]); SQRADDAC(a[21], a[34]); SQRADDAC(a[22], a[33]); SQRADDAC(a[23], a[32]); SQRADDAC(a[24], a[31]); SQRADDAC(a[25], a[30]); SQRADDAC(a[26], a[29]); SQRADDAC(a[27], a[28]); SQRADDDB; 
+   COMBA_STORE(b[55]);
+
+   /* output 56 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[56]); SQRADDAC(a[1], a[55]); SQRADDAC(a[2], a[54]); SQRADDAC(a[3], a[53]); SQRADDAC(a[4], a[52]); SQRADDAC(a[5], a[51]); SQRADDAC(a[6], a[50]); SQRADDAC(a[7], a[49]); SQRADDAC(a[8], a[48]); SQRADDAC(a[9], a[47]); SQRADDAC(a[10], a[46]); SQRADDAC(a[11], a[45]); SQRADDAC(a[12], a[44]); SQRADDAC(a[13], a[43]); SQRADDAC(a[14], a[42]); SQRADDAC(a[15], a[41]); SQRADDAC(a[16], a[40]); SQRADDAC(a[17], a[39]); SQRADDAC(a[18], a[38]); SQRADDAC(a[19], a[37]); SQRADDAC(a[20], a[36]); SQRADDAC(a[21], a[35]); SQRADDAC(a[22], a[34]); SQRADDAC(a[23], a[33]); SQRADDAC(a[24], a[32]); SQRADDAC(a[25], a[31]); SQRADDAC(a[26], a[30]); SQRADDAC(a[27], a[29]); SQRADDDB; SQRADD(a[28], a[28]); 
+   COMBA_STORE(b[56]);
+
+   /* output 57 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[57]); SQRADDAC(a[1], a[56]); SQRADDAC(a[2], a[55]); SQRADDAC(a[3], a[54]); SQRADDAC(a[4], a[53]); SQRADDAC(a[5], a[52]); SQRADDAC(a[6], a[51]); SQRADDAC(a[7], a[50]); SQRADDAC(a[8], a[49]); SQRADDAC(a[9], a[48]); SQRADDAC(a[10], a[47]); SQRADDAC(a[11], a[46]); SQRADDAC(a[12], a[45]); SQRADDAC(a[13], a[44]); SQRADDAC(a[14], a[43]); SQRADDAC(a[15], a[42]); SQRADDAC(a[16], a[41]); SQRADDAC(a[17], a[40]); SQRADDAC(a[18], a[39]); SQRADDAC(a[19], a[38]); SQRADDAC(a[20], a[37]); SQRADDAC(a[21], a[36]); SQRADDAC(a[22], a[35]); SQRADDAC(a[23], a[34]); SQRADDAC(a[24], a[33]); SQRADDAC(a[25], a[32]); SQRADDAC(a[26], a[31]); SQRADDAC(a[27], a[30]); SQRADDAC(a[28], a[29]); SQRADDDB; 
+   COMBA_STORE(b[57]);
+
+   /* output 58 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[58]); SQRADDAC(a[1], a[57]); SQRADDAC(a[2], a[56]); SQRADDAC(a[3], a[55]); SQRADDAC(a[4], a[54]); SQRADDAC(a[5], a[53]); SQRADDAC(a[6], a[52]); SQRADDAC(a[7], a[51]); SQRADDAC(a[8], a[50]); SQRADDAC(a[9], a[49]); SQRADDAC(a[10], a[48]); SQRADDAC(a[11], a[47]); SQRADDAC(a[12], a[46]); SQRADDAC(a[13], a[45]); SQRADDAC(a[14], a[44]); SQRADDAC(a[15], a[43]); SQRADDAC(a[16], a[42]); SQRADDAC(a[17], a[41]); SQRADDAC(a[18], a[40]); SQRADDAC(a[19], a[39]); SQRADDAC(a[20], a[38]); SQRADDAC(a[21], a[37]); SQRADDAC(a[22], a[36]); SQRADDAC(a[23], a[35]); SQRADDAC(a[24], a[34]); SQRADDAC(a[25], a[33]); SQRADDAC(a[26], a[32]); SQRADDAC(a[27], a[31]); SQRADDAC(a[28], a[30]); SQRADDDB; SQRADD(a[29], a[29]); 
+   COMBA_STORE(b[58]);
+
+   /* output 59 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[59]); SQRADDAC(a[1], a[58]); SQRADDAC(a[2], a[57]); SQRADDAC(a[3], a[56]); SQRADDAC(a[4], a[55]); SQRADDAC(a[5], a[54]); SQRADDAC(a[6], a[53]); SQRADDAC(a[7], a[52]); SQRADDAC(a[8], a[51]); SQRADDAC(a[9], a[50]); SQRADDAC(a[10], a[49]); SQRADDAC(a[11], a[48]); SQRADDAC(a[12], a[47]); SQRADDAC(a[13], a[46]); SQRADDAC(a[14], a[45]); SQRADDAC(a[15], a[44]); SQRADDAC(a[16], a[43]); SQRADDAC(a[17], a[42]); SQRADDAC(a[18], a[41]); SQRADDAC(a[19], a[40]); SQRADDAC(a[20], a[39]); SQRADDAC(a[21], a[38]); SQRADDAC(a[22], a[37]); SQRADDAC(a[23], a[36]); SQRADDAC(a[24], a[35]); SQRADDAC(a[25], a[34]); SQRADDAC(a[26], a[33]); SQRADDAC(a[27], a[32]); SQRADDAC(a[28], a[31]); SQRADDAC(a[29], a[30]); SQRADDDB; 
+   COMBA_STORE(b[59]);
+
+   /* output 60 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[60]); SQRADDAC(a[1], a[59]); SQRADDAC(a[2], a[58]); SQRADDAC(a[3], a[57]); SQRADDAC(a[4], a[56]); SQRADDAC(a[5], a[55]); SQRADDAC(a[6], a[54]); SQRADDAC(a[7], a[53]); SQRADDAC(a[8], a[52]); SQRADDAC(a[9], a[51]); SQRADDAC(a[10], a[50]); SQRADDAC(a[11], a[49]); SQRADDAC(a[12], a[48]); SQRADDAC(a[13], a[47]); SQRADDAC(a[14], a[46]); SQRADDAC(a[15], a[45]); SQRADDAC(a[16], a[44]); SQRADDAC(a[17], a[43]); SQRADDAC(a[18], a[42]); SQRADDAC(a[19], a[41]); SQRADDAC(a[20], a[40]); SQRADDAC(a[21], a[39]); SQRADDAC(a[22], a[38]); SQRADDAC(a[23], a[37]); SQRADDAC(a[24], a[36]); SQRADDAC(a[25], a[35]); SQRADDAC(a[26], a[34]); SQRADDAC(a[27], a[33]); SQRADDAC(a[28], a[32]); SQRADDAC(a[29], a[31]); SQRADDDB; SQRADD(a[30], a[30]); 
+   COMBA_STORE(b[60]);
+
+   /* output 61 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[61]); SQRADDAC(a[1], a[60]); SQRADDAC(a[2], a[59]); SQRADDAC(a[3], a[58]); SQRADDAC(a[4], a[57]); SQRADDAC(a[5], a[56]); SQRADDAC(a[6], a[55]); SQRADDAC(a[7], a[54]); SQRADDAC(a[8], a[53]); SQRADDAC(a[9], a[52]); SQRADDAC(a[10], a[51]); SQRADDAC(a[11], a[50]); SQRADDAC(a[12], a[49]); SQRADDAC(a[13], a[48]); SQRADDAC(a[14], a[47]); SQRADDAC(a[15], a[46]); SQRADDAC(a[16], a[45]); SQRADDAC(a[17], a[44]); SQRADDAC(a[18], a[43]); SQRADDAC(a[19], a[42]); SQRADDAC(a[20], a[41]); SQRADDAC(a[21], a[40]); SQRADDAC(a[22], a[39]); SQRADDAC(a[23], a[38]); SQRADDAC(a[24], a[37]); SQRADDAC(a[25], a[36]); SQRADDAC(a[26], a[35]); SQRADDAC(a[27], a[34]); SQRADDAC(a[28], a[33]); SQRADDAC(a[29], a[32]); SQRADDAC(a[30], a[31]); SQRADDDB; 
+   COMBA_STORE(b[61]);
+
+   /* output 62 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[62]); SQRADDAC(a[1], a[61]); SQRADDAC(a[2], a[60]); SQRADDAC(a[3], a[59]); SQRADDAC(a[4], a[58]); SQRADDAC(a[5], a[57]); SQRADDAC(a[6], a[56]); SQRADDAC(a[7], a[55]); SQRADDAC(a[8], a[54]); SQRADDAC(a[9], a[53]); SQRADDAC(a[10], a[52]); SQRADDAC(a[11], a[51]); SQRADDAC(a[12], a[50]); SQRADDAC(a[13], a[49]); SQRADDAC(a[14], a[48]); SQRADDAC(a[15], a[47]); SQRADDAC(a[16], a[46]); SQRADDAC(a[17], a[45]); SQRADDAC(a[18], a[44]); SQRADDAC(a[19], a[43]); SQRADDAC(a[20], a[42]); SQRADDAC(a[21], a[41]); SQRADDAC(a[22], a[40]); SQRADDAC(a[23], a[39]); SQRADDAC(a[24], a[38]); SQRADDAC(a[25], a[37]); SQRADDAC(a[26], a[36]); SQRADDAC(a[27], a[35]); SQRADDAC(a[28], a[34]); SQRADDAC(a[29], a[33]); SQRADDAC(a[30], a[32]); SQRADDDB; SQRADD(a[31], a[31]); 
+   COMBA_STORE(b[62]);
+
+   /* output 63 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[63]); SQRADDAC(a[1], a[62]); SQRADDAC(a[2], a[61]); SQRADDAC(a[3], a[60]); SQRADDAC(a[4], a[59]); SQRADDAC(a[5], a[58]); SQRADDAC(a[6], a[57]); SQRADDAC(a[7], a[56]); SQRADDAC(a[8], a[55]); SQRADDAC(a[9], a[54]); SQRADDAC(a[10], a[53]); SQRADDAC(a[11], a[52]); SQRADDAC(a[12], a[51]); SQRADDAC(a[13], a[50]); SQRADDAC(a[14], a[49]); SQRADDAC(a[15], a[48]); SQRADDAC(a[16], a[47]); SQRADDAC(a[17], a[46]); SQRADDAC(a[18], a[45]); SQRADDAC(a[19], a[44]); SQRADDAC(a[20], a[43]); SQRADDAC(a[21], a[42]); SQRADDAC(a[22], a[41]); SQRADDAC(a[23], a[40]); SQRADDAC(a[24], a[39]); SQRADDAC(a[25], a[38]); SQRADDAC(a[26], a[37]); SQRADDAC(a[27], a[36]); SQRADDAC(a[28], a[35]); SQRADDAC(a[29], a[34]); SQRADDAC(a[30], a[33]); SQRADDAC(a[31], a[32]); SQRADDDB; 
+   COMBA_STORE(b[63]);
+
+   /* output 64 */
+   CARRY_FORWARD;
+   SQRADDSC(a[1], a[63]); SQRADDAC(a[2], a[62]); SQRADDAC(a[3], a[61]); SQRADDAC(a[4], a[60]); SQRADDAC(a[5], a[59]); SQRADDAC(a[6], a[58]); SQRADDAC(a[7], a[57]); SQRADDAC(a[8], a[56]); SQRADDAC(a[9], a[55]); SQRADDAC(a[10], a[54]); SQRADDAC(a[11], a[53]); SQRADDAC(a[12], a[52]); SQRADDAC(a[13], a[51]); SQRADDAC(a[14], a[50]); SQRADDAC(a[15], a[49]); SQRADDAC(a[16], a[48]); SQRADDAC(a[17], a[47]); SQRADDAC(a[18], a[46]); SQRADDAC(a[19], a[45]); SQRADDAC(a[20], a[44]); SQRADDAC(a[21], a[43]); SQRADDAC(a[22], a[42]); SQRADDAC(a[23], a[41]); SQRADDAC(a[24], a[40]); SQRADDAC(a[25], a[39]); SQRADDAC(a[26], a[38]); SQRADDAC(a[27], a[37]); SQRADDAC(a[28], a[36]); SQRADDAC(a[29], a[35]); SQRADDAC(a[30], a[34]); SQRADDAC(a[31], a[33]); SQRADDDB; SQRADD(a[32], a[32]); 
+   COMBA_STORE(b[64]);
+
+   /* output 65 */
+   CARRY_FORWARD;
+   SQRADDSC(a[2], a[63]); SQRADDAC(a[3], a[62]); SQRADDAC(a[4], a[61]); SQRADDAC(a[5], a[60]); SQRADDAC(a[6], a[59]); SQRADDAC(a[7], a[58]); SQRADDAC(a[8], a[57]); SQRADDAC(a[9], a[56]); SQRADDAC(a[10], a[55]); SQRADDAC(a[11], a[54]); SQRADDAC(a[12], a[53]); SQRADDAC(a[13], a[52]); SQRADDAC(a[14], a[51]); SQRADDAC(a[15], a[50]); SQRADDAC(a[16], a[49]); SQRADDAC(a[17], a[48]); SQRADDAC(a[18], a[47]); SQRADDAC(a[19], a[46]); SQRADDAC(a[20], a[45]); SQRADDAC(a[21], a[44]); SQRADDAC(a[22], a[43]); SQRADDAC(a[23], a[42]); SQRADDAC(a[24], a[41]); SQRADDAC(a[25], a[40]); SQRADDAC(a[26], a[39]); SQRADDAC(a[27], a[38]); SQRADDAC(a[28], a[37]); SQRADDAC(a[29], a[36]); SQRADDAC(a[30], a[35]); SQRADDAC(a[31], a[34]); SQRADDAC(a[32], a[33]); SQRADDDB; 
+   COMBA_STORE(b[65]);
+
+   /* output 66 */
+   CARRY_FORWARD;
+   SQRADDSC(a[3], a[63]); SQRADDAC(a[4], a[62]); SQRADDAC(a[5], a[61]); SQRADDAC(a[6], a[60]); SQRADDAC(a[7], a[59]); SQRADDAC(a[8], a[58]); SQRADDAC(a[9], a[57]); SQRADDAC(a[10], a[56]); SQRADDAC(a[11], a[55]); SQRADDAC(a[12], a[54]); SQRADDAC(a[13], a[53]); SQRADDAC(a[14], a[52]); SQRADDAC(a[15], a[51]); SQRADDAC(a[16], a[50]); SQRADDAC(a[17], a[49]); SQRADDAC(a[18], a[48]); SQRADDAC(a[19], a[47]); SQRADDAC(a[20], a[46]); SQRADDAC(a[21], a[45]); SQRADDAC(a[22], a[44]); SQRADDAC(a[23], a[43]); SQRADDAC(a[24], a[42]); SQRADDAC(a[25], a[41]); SQRADDAC(a[26], a[40]); SQRADDAC(a[27], a[39]); SQRADDAC(a[28], a[38]); SQRADDAC(a[29], a[37]); SQRADDAC(a[30], a[36]); SQRADDAC(a[31], a[35]); SQRADDAC(a[32], a[34]); SQRADDDB; SQRADD(a[33], a[33]); 
+   COMBA_STORE(b[66]);
+
+   /* output 67 */
+   CARRY_FORWARD;
+   SQRADDSC(a[4], a[63]); SQRADDAC(a[5], a[62]); SQRADDAC(a[6], a[61]); SQRADDAC(a[7], a[60]); SQRADDAC(a[8], a[59]); SQRADDAC(a[9], a[58]); SQRADDAC(a[10], a[57]); SQRADDAC(a[11], a[56]); SQRADDAC(a[12], a[55]); SQRADDAC(a[13], a[54]); SQRADDAC(a[14], a[53]); SQRADDAC(a[15], a[52]); SQRADDAC(a[16], a[51]); SQRADDAC(a[17], a[50]); SQRADDAC(a[18], a[49]); SQRADDAC(a[19], a[48]); SQRADDAC(a[20], a[47]); SQRADDAC(a[21], a[46]); SQRADDAC(a[22], a[45]); SQRADDAC(a[23], a[44]); SQRADDAC(a[24], a[43]); SQRADDAC(a[25], a[42]); SQRADDAC(a[26], a[41]); SQRADDAC(a[27], a[40]); SQRADDAC(a[28], a[39]); SQRADDAC(a[29], a[38]); SQRADDAC(a[30], a[37]); SQRADDAC(a[31], a[36]); SQRADDAC(a[32], a[35]); SQRADDAC(a[33], a[34]); SQRADDDB; 
+   COMBA_STORE(b[67]);
+
+   /* output 68 */
+   CARRY_FORWARD;
+   SQRADDSC(a[5], a[63]); SQRADDAC(a[6], a[62]); SQRADDAC(a[7], a[61]); SQRADDAC(a[8], a[60]); SQRADDAC(a[9], a[59]); SQRADDAC(a[10], a[58]); SQRADDAC(a[11], a[57]); SQRADDAC(a[12], a[56]); SQRADDAC(a[13], a[55]); SQRADDAC(a[14], a[54]); SQRADDAC(a[15], a[53]); SQRADDAC(a[16], a[52]); SQRADDAC(a[17], a[51]); SQRADDAC(a[18], a[50]); SQRADDAC(a[19], a[49]); SQRADDAC(a[20], a[48]); SQRADDAC(a[21], a[47]); SQRADDAC(a[22], a[46]); SQRADDAC(a[23], a[45]); SQRADDAC(a[24], a[44]); SQRADDAC(a[25], a[43]); SQRADDAC(a[26], a[42]); SQRADDAC(a[27], a[41]); SQRADDAC(a[28], a[40]); SQRADDAC(a[29], a[39]); SQRADDAC(a[30], a[38]); SQRADDAC(a[31], a[37]); SQRADDAC(a[32], a[36]); SQRADDAC(a[33], a[35]); SQRADDDB; SQRADD(a[34], a[34]); 
+   COMBA_STORE(b[68]);
+
+   /* output 69 */
+   CARRY_FORWARD;
+   SQRADDSC(a[6], a[63]); SQRADDAC(a[7], a[62]); SQRADDAC(a[8], a[61]); SQRADDAC(a[9], a[60]); SQRADDAC(a[10], a[59]); SQRADDAC(a[11], a[58]); SQRADDAC(a[12], a[57]); SQRADDAC(a[13], a[56]); SQRADDAC(a[14], a[55]); SQRADDAC(a[15], a[54]); SQRADDAC(a[16], a[53]); SQRADDAC(a[17], a[52]); SQRADDAC(a[18], a[51]); SQRADDAC(a[19], a[50]); SQRADDAC(a[20], a[49]); SQRADDAC(a[21], a[48]); SQRADDAC(a[22], a[47]); SQRADDAC(a[23], a[46]); SQRADDAC(a[24], a[45]); SQRADDAC(a[25], a[44]); SQRADDAC(a[26], a[43]); SQRADDAC(a[27], a[42]); SQRADDAC(a[28], a[41]); SQRADDAC(a[29], a[40]); SQRADDAC(a[30], a[39]); SQRADDAC(a[31], a[38]); SQRADDAC(a[32], a[37]); SQRADDAC(a[33], a[36]); SQRADDAC(a[34], a[35]); SQRADDDB; 
+   COMBA_STORE(b[69]);
+
+   /* output 70 */
+   CARRY_FORWARD;
+   SQRADDSC(a[7], a[63]); SQRADDAC(a[8], a[62]); SQRADDAC(a[9], a[61]); SQRADDAC(a[10], a[60]); SQRADDAC(a[11], a[59]); SQRADDAC(a[12], a[58]); SQRADDAC(a[13], a[57]); SQRADDAC(a[14], a[56]); SQRADDAC(a[15], a[55]); SQRADDAC(a[16], a[54]); SQRADDAC(a[17], a[53]); SQRADDAC(a[18], a[52]); SQRADDAC(a[19], a[51]); SQRADDAC(a[20], a[50]); SQRADDAC(a[21], a[49]); SQRADDAC(a[22], a[48]); SQRADDAC(a[23], a[47]); SQRADDAC(a[24], a[46]); SQRADDAC(a[25], a[45]); SQRADDAC(a[26], a[44]); SQRADDAC(a[27], a[43]); SQRADDAC(a[28], a[42]); SQRADDAC(a[29], a[41]); SQRADDAC(a[30], a[40]); SQRADDAC(a[31], a[39]); SQRADDAC(a[32], a[38]); SQRADDAC(a[33], a[37]); SQRADDAC(a[34], a[36]); SQRADDDB; SQRADD(a[35], a[35]); 
+   COMBA_STORE(b[70]);
+
+   /* output 71 */
+   CARRY_FORWARD;
+   SQRADDSC(a[8], a[63]); SQRADDAC(a[9], a[62]); SQRADDAC(a[10], a[61]); SQRADDAC(a[11], a[60]); SQRADDAC(a[12], a[59]); SQRADDAC(a[13], a[58]); SQRADDAC(a[14], a[57]); SQRADDAC(a[15], a[56]); SQRADDAC(a[16], a[55]); SQRADDAC(a[17], a[54]); SQRADDAC(a[18], a[53]); SQRADDAC(a[19], a[52]); SQRADDAC(a[20], a[51]); SQRADDAC(a[21], a[50]); SQRADDAC(a[22], a[49]); SQRADDAC(a[23], a[48]); SQRADDAC(a[24], a[47]); SQRADDAC(a[25], a[46]); SQRADDAC(a[26], a[45]); SQRADDAC(a[27], a[44]); SQRADDAC(a[28], a[43]); SQRADDAC(a[29], a[42]); SQRADDAC(a[30], a[41]); SQRADDAC(a[31], a[40]); SQRADDAC(a[32], a[39]); SQRADDAC(a[33], a[38]); SQRADDAC(a[34], a[37]); SQRADDAC(a[35], a[36]); SQRADDDB; 
+   COMBA_STORE(b[71]);
+
+   /* output 72 */
+   CARRY_FORWARD;
+   SQRADDSC(a[9], a[63]); SQRADDAC(a[10], a[62]); SQRADDAC(a[11], a[61]); SQRADDAC(a[12], a[60]); SQRADDAC(a[13], a[59]); SQRADDAC(a[14], a[58]); SQRADDAC(a[15], a[57]); SQRADDAC(a[16], a[56]); SQRADDAC(a[17], a[55]); SQRADDAC(a[18], a[54]); SQRADDAC(a[19], a[53]); SQRADDAC(a[20], a[52]); SQRADDAC(a[21], a[51]); SQRADDAC(a[22], a[50]); SQRADDAC(a[23], a[49]); SQRADDAC(a[24], a[48]); SQRADDAC(a[25], a[47]); SQRADDAC(a[26], a[46]); SQRADDAC(a[27], a[45]); SQRADDAC(a[28], a[44]); SQRADDAC(a[29], a[43]); SQRADDAC(a[30], a[42]); SQRADDAC(a[31], a[41]); SQRADDAC(a[32], a[40]); SQRADDAC(a[33], a[39]); SQRADDAC(a[34], a[38]); SQRADDAC(a[35], a[37]); SQRADDDB; SQRADD(a[36], a[36]); 
+   COMBA_STORE(b[72]);
+
+   /* output 73 */
+   CARRY_FORWARD;
+   SQRADDSC(a[10], a[63]); SQRADDAC(a[11], a[62]); SQRADDAC(a[12], a[61]); SQRADDAC(a[13], a[60]); SQRADDAC(a[14], a[59]); SQRADDAC(a[15], a[58]); SQRADDAC(a[16], a[57]); SQRADDAC(a[17], a[56]); SQRADDAC(a[18], a[55]); SQRADDAC(a[19], a[54]); SQRADDAC(a[20], a[53]); SQRADDAC(a[21], a[52]); SQRADDAC(a[22], a[51]); SQRADDAC(a[23], a[50]); SQRADDAC(a[24], a[49]); SQRADDAC(a[25], a[48]); SQRADDAC(a[26], a[47]); SQRADDAC(a[27], a[46]); SQRADDAC(a[28], a[45]); SQRADDAC(a[29], a[44]); SQRADDAC(a[30], a[43]); SQRADDAC(a[31], a[42]); SQRADDAC(a[32], a[41]); SQRADDAC(a[33], a[40]); SQRADDAC(a[34], a[39]); SQRADDAC(a[35], a[38]); SQRADDAC(a[36], a[37]); SQRADDDB; 
+   COMBA_STORE(b[73]);
+
+   /* output 74 */
+   CARRY_FORWARD;
+   SQRADDSC(a[11], a[63]); SQRADDAC(a[12], a[62]); SQRADDAC(a[13], a[61]); SQRADDAC(a[14], a[60]); SQRADDAC(a[15], a[59]); SQRADDAC(a[16], a[58]); SQRADDAC(a[17], a[57]); SQRADDAC(a[18], a[56]); SQRADDAC(a[19], a[55]); SQRADDAC(a[20], a[54]); SQRADDAC(a[21], a[53]); SQRADDAC(a[22], a[52]); SQRADDAC(a[23], a[51]); SQRADDAC(a[24], a[50]); SQRADDAC(a[25], a[49]); SQRADDAC(a[26], a[48]); SQRADDAC(a[27], a[47]); SQRADDAC(a[28], a[46]); SQRADDAC(a[29], a[45]); SQRADDAC(a[30], a[44]); SQRADDAC(a[31], a[43]); SQRADDAC(a[32], a[42]); SQRADDAC(a[33], a[41]); SQRADDAC(a[34], a[40]); SQRADDAC(a[35], a[39]); SQRADDAC(a[36], a[38]); SQRADDDB; SQRADD(a[37], a[37]); 
+   COMBA_STORE(b[74]);
+
+   /* output 75 */
+   CARRY_FORWARD;
+   SQRADDSC(a[12], a[63]); SQRADDAC(a[13], a[62]); SQRADDAC(a[14], a[61]); SQRADDAC(a[15], a[60]); SQRADDAC(a[16], a[59]); SQRADDAC(a[17], a[58]); SQRADDAC(a[18], a[57]); SQRADDAC(a[19], a[56]); SQRADDAC(a[20], a[55]); SQRADDAC(a[21], a[54]); SQRADDAC(a[22], a[53]); SQRADDAC(a[23], a[52]); SQRADDAC(a[24], a[51]); SQRADDAC(a[25], a[50]); SQRADDAC(a[26], a[49]); SQRADDAC(a[27], a[48]); SQRADDAC(a[28], a[47]); SQRADDAC(a[29], a[46]); SQRADDAC(a[30], a[45]); SQRADDAC(a[31], a[44]); SQRADDAC(a[32], a[43]); SQRADDAC(a[33], a[42]); SQRADDAC(a[34], a[41]); SQRADDAC(a[35], a[40]); SQRADDAC(a[36], a[39]); SQRADDAC(a[37], a[38]); SQRADDDB; 
+   COMBA_STORE(b[75]);
+
+   /* output 76 */
+   CARRY_FORWARD;
+   SQRADDSC(a[13], a[63]); SQRADDAC(a[14], a[62]); SQRADDAC(a[15], a[61]); SQRADDAC(a[16], a[60]); SQRADDAC(a[17], a[59]); SQRADDAC(a[18], a[58]); SQRADDAC(a[19], a[57]); SQRADDAC(a[20], a[56]); SQRADDAC(a[21], a[55]); SQRADDAC(a[22], a[54]); SQRADDAC(a[23], a[53]); SQRADDAC(a[24], a[52]); SQRADDAC(a[25], a[51]); SQRADDAC(a[26], a[50]); SQRADDAC(a[27], a[49]); SQRADDAC(a[28], a[48]); SQRADDAC(a[29], a[47]); SQRADDAC(a[30], a[46]); SQRADDAC(a[31], a[45]); SQRADDAC(a[32], a[44]); SQRADDAC(a[33], a[43]); SQRADDAC(a[34], a[42]); SQRADDAC(a[35], a[41]); SQRADDAC(a[36], a[40]); SQRADDAC(a[37], a[39]); SQRADDDB; SQRADD(a[38], a[38]); 
+   COMBA_STORE(b[76]);
+
+   /* output 77 */
+   CARRY_FORWARD;
+   SQRADDSC(a[14], a[63]); SQRADDAC(a[15], a[62]); SQRADDAC(a[16], a[61]); SQRADDAC(a[17], a[60]); SQRADDAC(a[18], a[59]); SQRADDAC(a[19], a[58]); SQRADDAC(a[20], a[57]); SQRADDAC(a[21], a[56]); SQRADDAC(a[22], a[55]); SQRADDAC(a[23], a[54]); SQRADDAC(a[24], a[53]); SQRADDAC(a[25], a[52]); SQRADDAC(a[26], a[51]); SQRADDAC(a[27], a[50]); SQRADDAC(a[28], a[49]); SQRADDAC(a[29], a[48]); SQRADDAC(a[30], a[47]); SQRADDAC(a[31], a[46]); SQRADDAC(a[32], a[45]); SQRADDAC(a[33], a[44]); SQRADDAC(a[34], a[43]); SQRADDAC(a[35], a[42]); SQRADDAC(a[36], a[41]); SQRADDAC(a[37], a[40]); SQRADDAC(a[38], a[39]); SQRADDDB; 
+   COMBA_STORE(b[77]);
+
+   /* output 78 */
+   CARRY_FORWARD;
+   SQRADDSC(a[15], a[63]); SQRADDAC(a[16], a[62]); SQRADDAC(a[17], a[61]); SQRADDAC(a[18], a[60]); SQRADDAC(a[19], a[59]); SQRADDAC(a[20], a[58]); SQRADDAC(a[21], a[57]); SQRADDAC(a[22], a[56]); SQRADDAC(a[23], a[55]); SQRADDAC(a[24], a[54]); SQRADDAC(a[25], a[53]); SQRADDAC(a[26], a[52]); SQRADDAC(a[27], a[51]); SQRADDAC(a[28], a[50]); SQRADDAC(a[29], a[49]); SQRADDAC(a[30], a[48]); SQRADDAC(a[31], a[47]); SQRADDAC(a[32], a[46]); SQRADDAC(a[33], a[45]); SQRADDAC(a[34], a[44]); SQRADDAC(a[35], a[43]); SQRADDAC(a[36], a[42]); SQRADDAC(a[37], a[41]); SQRADDAC(a[38], a[40]); SQRADDDB; SQRADD(a[39], a[39]); 
+   COMBA_STORE(b[78]);
+
+   /* output 79 */
+   CARRY_FORWARD;
+   SQRADDSC(a[16], a[63]); SQRADDAC(a[17], a[62]); SQRADDAC(a[18], a[61]); SQRADDAC(a[19], a[60]); SQRADDAC(a[20], a[59]); SQRADDAC(a[21], a[58]); SQRADDAC(a[22], a[57]); SQRADDAC(a[23], a[56]); SQRADDAC(a[24], a[55]); SQRADDAC(a[25], a[54]); SQRADDAC(a[26], a[53]); SQRADDAC(a[27], a[52]); SQRADDAC(a[28], a[51]); SQRADDAC(a[29], a[50]); SQRADDAC(a[30], a[49]); SQRADDAC(a[31], a[48]); SQRADDAC(a[32], a[47]); SQRADDAC(a[33], a[46]); SQRADDAC(a[34], a[45]); SQRADDAC(a[35], a[44]); SQRADDAC(a[36], a[43]); SQRADDAC(a[37], a[42]); SQRADDAC(a[38], a[41]); SQRADDAC(a[39], a[40]); SQRADDDB; 
+   COMBA_STORE(b[79]);
+
+   /* output 80 */
+   CARRY_FORWARD;
+   SQRADDSC(a[17], a[63]); SQRADDAC(a[18], a[62]); SQRADDAC(a[19], a[61]); SQRADDAC(a[20], a[60]); SQRADDAC(a[21], a[59]); SQRADDAC(a[22], a[58]); SQRADDAC(a[23], a[57]); SQRADDAC(a[24], a[56]); SQRADDAC(a[25], a[55]); SQRADDAC(a[26], a[54]); SQRADDAC(a[27], a[53]); SQRADDAC(a[28], a[52]); SQRADDAC(a[29], a[51]); SQRADDAC(a[30], a[50]); SQRADDAC(a[31], a[49]); SQRADDAC(a[32], a[48]); SQRADDAC(a[33], a[47]); SQRADDAC(a[34], a[46]); SQRADDAC(a[35], a[45]); SQRADDAC(a[36], a[44]); SQRADDAC(a[37], a[43]); SQRADDAC(a[38], a[42]); SQRADDAC(a[39], a[41]); SQRADDDB; SQRADD(a[40], a[40]); 
+   COMBA_STORE(b[80]);
+
+   /* output 81 */
+   CARRY_FORWARD;
+   SQRADDSC(a[18], a[63]); SQRADDAC(a[19], a[62]); SQRADDAC(a[20], a[61]); SQRADDAC(a[21], a[60]); SQRADDAC(a[22], a[59]); SQRADDAC(a[23], a[58]); SQRADDAC(a[24], a[57]); SQRADDAC(a[25], a[56]); SQRADDAC(a[26], a[55]); SQRADDAC(a[27], a[54]); SQRADDAC(a[28], a[53]); SQRADDAC(a[29], a[52]); SQRADDAC(a[30], a[51]); SQRADDAC(a[31], a[50]); SQRADDAC(a[32], a[49]); SQRADDAC(a[33], a[48]); SQRADDAC(a[34], a[47]); SQRADDAC(a[35], a[46]); SQRADDAC(a[36], a[45]); SQRADDAC(a[37], a[44]); SQRADDAC(a[38], a[43]); SQRADDAC(a[39], a[42]); SQRADDAC(a[40], a[41]); SQRADDDB; 
+   COMBA_STORE(b[81]);
+
+   /* output 82 */
+   CARRY_FORWARD;
+   SQRADDSC(a[19], a[63]); SQRADDAC(a[20], a[62]); SQRADDAC(a[21], a[61]); SQRADDAC(a[22], a[60]); SQRADDAC(a[23], a[59]); SQRADDAC(a[24], a[58]); SQRADDAC(a[25], a[57]); SQRADDAC(a[26], a[56]); SQRADDAC(a[27], a[55]); SQRADDAC(a[28], a[54]); SQRADDAC(a[29], a[53]); SQRADDAC(a[30], a[52]); SQRADDAC(a[31], a[51]); SQRADDAC(a[32], a[50]); SQRADDAC(a[33], a[49]); SQRADDAC(a[34], a[48]); SQRADDAC(a[35], a[47]); SQRADDAC(a[36], a[46]); SQRADDAC(a[37], a[45]); SQRADDAC(a[38], a[44]); SQRADDAC(a[39], a[43]); SQRADDAC(a[40], a[42]); SQRADDDB; SQRADD(a[41], a[41]); 
+   COMBA_STORE(b[82]);
+
+   /* output 83 */
+   CARRY_FORWARD;
+   SQRADDSC(a[20], a[63]); SQRADDAC(a[21], a[62]); SQRADDAC(a[22], a[61]); SQRADDAC(a[23], a[60]); SQRADDAC(a[24], a[59]); SQRADDAC(a[25], a[58]); SQRADDAC(a[26], a[57]); SQRADDAC(a[27], a[56]); SQRADDAC(a[28], a[55]); SQRADDAC(a[29], a[54]); SQRADDAC(a[30], a[53]); SQRADDAC(a[31], a[52]); SQRADDAC(a[32], a[51]); SQRADDAC(a[33], a[50]); SQRADDAC(a[34], a[49]); SQRADDAC(a[35], a[48]); SQRADDAC(a[36], a[47]); SQRADDAC(a[37], a[46]); SQRADDAC(a[38], a[45]); SQRADDAC(a[39], a[44]); SQRADDAC(a[40], a[43]); SQRADDAC(a[41], a[42]); SQRADDDB; 
+   COMBA_STORE(b[83]);
+
+   /* output 84 */
+   CARRY_FORWARD;
+   SQRADDSC(a[21], a[63]); SQRADDAC(a[22], a[62]); SQRADDAC(a[23], a[61]); SQRADDAC(a[24], a[60]); SQRADDAC(a[25], a[59]); SQRADDAC(a[26], a[58]); SQRADDAC(a[27], a[57]); SQRADDAC(a[28], a[56]); SQRADDAC(a[29], a[55]); SQRADDAC(a[30], a[54]); SQRADDAC(a[31], a[53]); SQRADDAC(a[32], a[52]); SQRADDAC(a[33], a[51]); SQRADDAC(a[34], a[50]); SQRADDAC(a[35], a[49]); SQRADDAC(a[36], a[48]); SQRADDAC(a[37], a[47]); SQRADDAC(a[38], a[46]); SQRADDAC(a[39], a[45]); SQRADDAC(a[40], a[44]); SQRADDAC(a[41], a[43]); SQRADDDB; SQRADD(a[42], a[42]); 
+   COMBA_STORE(b[84]);
+
+   /* output 85 */
+   CARRY_FORWARD;
+   SQRADDSC(a[22], a[63]); SQRADDAC(a[23], a[62]); SQRADDAC(a[24], a[61]); SQRADDAC(a[25], a[60]); SQRADDAC(a[26], a[59]); SQRADDAC(a[27], a[58]); SQRADDAC(a[28], a[57]); SQRADDAC(a[29], a[56]); SQRADDAC(a[30], a[55]); SQRADDAC(a[31], a[54]); SQRADDAC(a[32], a[53]); SQRADDAC(a[33], a[52]); SQRADDAC(a[34], a[51]); SQRADDAC(a[35], a[50]); SQRADDAC(a[36], a[49]); SQRADDAC(a[37], a[48]); SQRADDAC(a[38], a[47]); SQRADDAC(a[39], a[46]); SQRADDAC(a[40], a[45]); SQRADDAC(a[41], a[44]); SQRADDAC(a[42], a[43]); SQRADDDB; 
+   COMBA_STORE(b[85]);
+
+   /* output 86 */
+   CARRY_FORWARD;
+   SQRADDSC(a[23], a[63]); SQRADDAC(a[24], a[62]); SQRADDAC(a[25], a[61]); SQRADDAC(a[26], a[60]); SQRADDAC(a[27], a[59]); SQRADDAC(a[28], a[58]); SQRADDAC(a[29], a[57]); SQRADDAC(a[30], a[56]); SQRADDAC(a[31], a[55]); SQRADDAC(a[32], a[54]); SQRADDAC(a[33], a[53]); SQRADDAC(a[34], a[52]); SQRADDAC(a[35], a[51]); SQRADDAC(a[36], a[50]); SQRADDAC(a[37], a[49]); SQRADDAC(a[38], a[48]); SQRADDAC(a[39], a[47]); SQRADDAC(a[40], a[46]); SQRADDAC(a[41], a[45]); SQRADDAC(a[42], a[44]); SQRADDDB; SQRADD(a[43], a[43]); 
+   COMBA_STORE(b[86]);
+
+   /* output 87 */
+   CARRY_FORWARD;
+   SQRADDSC(a[24], a[63]); SQRADDAC(a[25], a[62]); SQRADDAC(a[26], a[61]); SQRADDAC(a[27], a[60]); SQRADDAC(a[28], a[59]); SQRADDAC(a[29], a[58]); SQRADDAC(a[30], a[57]); SQRADDAC(a[31], a[56]); SQRADDAC(a[32], a[55]); SQRADDAC(a[33], a[54]); SQRADDAC(a[34], a[53]); SQRADDAC(a[35], a[52]); SQRADDAC(a[36], a[51]); SQRADDAC(a[37], a[50]); SQRADDAC(a[38], a[49]); SQRADDAC(a[39], a[48]); SQRADDAC(a[40], a[47]); SQRADDAC(a[41], a[46]); SQRADDAC(a[42], a[45]); SQRADDAC(a[43], a[44]); SQRADDDB; 
+   COMBA_STORE(b[87]);
+
+   /* output 88 */
+   CARRY_FORWARD;
+   SQRADDSC(a[25], a[63]); SQRADDAC(a[26], a[62]); SQRADDAC(a[27], a[61]); SQRADDAC(a[28], a[60]); SQRADDAC(a[29], a[59]); SQRADDAC(a[30], a[58]); SQRADDAC(a[31], a[57]); SQRADDAC(a[32], a[56]); SQRADDAC(a[33], a[55]); SQRADDAC(a[34], a[54]); SQRADDAC(a[35], a[53]); SQRADDAC(a[36], a[52]); SQRADDAC(a[37], a[51]); SQRADDAC(a[38], a[50]); SQRADDAC(a[39], a[49]); SQRADDAC(a[40], a[48]); SQRADDAC(a[41], a[47]); SQRADDAC(a[42], a[46]); SQRADDAC(a[43], a[45]); SQRADDDB; SQRADD(a[44], a[44]); 
+   COMBA_STORE(b[88]);
+
+   /* output 89 */
+   CARRY_FORWARD;
+   SQRADDSC(a[26], a[63]); SQRADDAC(a[27], a[62]); SQRADDAC(a[28], a[61]); SQRADDAC(a[29], a[60]); SQRADDAC(a[30], a[59]); SQRADDAC(a[31], a[58]); SQRADDAC(a[32], a[57]); SQRADDAC(a[33], a[56]); SQRADDAC(a[34], a[55]); SQRADDAC(a[35], a[54]); SQRADDAC(a[36], a[53]); SQRADDAC(a[37], a[52]); SQRADDAC(a[38], a[51]); SQRADDAC(a[39], a[50]); SQRADDAC(a[40], a[49]); SQRADDAC(a[41], a[48]); SQRADDAC(a[42], a[47]); SQRADDAC(a[43], a[46]); SQRADDAC(a[44], a[45]); SQRADDDB; 
+   COMBA_STORE(b[89]);
+
+   /* output 90 */
+   CARRY_FORWARD;
+   SQRADDSC(a[27], a[63]); SQRADDAC(a[28], a[62]); SQRADDAC(a[29], a[61]); SQRADDAC(a[30], a[60]); SQRADDAC(a[31], a[59]); SQRADDAC(a[32], a[58]); SQRADDAC(a[33], a[57]); SQRADDAC(a[34], a[56]); SQRADDAC(a[35], a[55]); SQRADDAC(a[36], a[54]); SQRADDAC(a[37], a[53]); SQRADDAC(a[38], a[52]); SQRADDAC(a[39], a[51]); SQRADDAC(a[40], a[50]); SQRADDAC(a[41], a[49]); SQRADDAC(a[42], a[48]); SQRADDAC(a[43], a[47]); SQRADDAC(a[44], a[46]); SQRADDDB; SQRADD(a[45], a[45]); 
+   COMBA_STORE(b[90]);
+
+   /* output 91 */
+   CARRY_FORWARD;
+   SQRADDSC(a[28], a[63]); SQRADDAC(a[29], a[62]); SQRADDAC(a[30], a[61]); SQRADDAC(a[31], a[60]); SQRADDAC(a[32], a[59]); SQRADDAC(a[33], a[58]); SQRADDAC(a[34], a[57]); SQRADDAC(a[35], a[56]); SQRADDAC(a[36], a[55]); SQRADDAC(a[37], a[54]); SQRADDAC(a[38], a[53]); SQRADDAC(a[39], a[52]); SQRADDAC(a[40], a[51]); SQRADDAC(a[41], a[50]); SQRADDAC(a[42], a[49]); SQRADDAC(a[43], a[48]); SQRADDAC(a[44], a[47]); SQRADDAC(a[45], a[46]); SQRADDDB; 
+   COMBA_STORE(b[91]);
+
+   /* output 92 */
+   CARRY_FORWARD;
+   SQRADDSC(a[29], a[63]); SQRADDAC(a[30], a[62]); SQRADDAC(a[31], a[61]); SQRADDAC(a[32], a[60]); SQRADDAC(a[33], a[59]); SQRADDAC(a[34], a[58]); SQRADDAC(a[35], a[57]); SQRADDAC(a[36], a[56]); SQRADDAC(a[37], a[55]); SQRADDAC(a[38], a[54]); SQRADDAC(a[39], a[53]); SQRADDAC(a[40], a[52]); SQRADDAC(a[41], a[51]); SQRADDAC(a[42], a[50]); SQRADDAC(a[43], a[49]); SQRADDAC(a[44], a[48]); SQRADDAC(a[45], a[47]); SQRADDDB; SQRADD(a[46], a[46]); 
+   COMBA_STORE(b[92]);
+
+   /* output 93 */
+   CARRY_FORWARD;
+   SQRADDSC(a[30], a[63]); SQRADDAC(a[31], a[62]); SQRADDAC(a[32], a[61]); SQRADDAC(a[33], a[60]); SQRADDAC(a[34], a[59]); SQRADDAC(a[35], a[58]); SQRADDAC(a[36], a[57]); SQRADDAC(a[37], a[56]); SQRADDAC(a[38], a[55]); SQRADDAC(a[39], a[54]); SQRADDAC(a[40], a[53]); SQRADDAC(a[41], a[52]); SQRADDAC(a[42], a[51]); SQRADDAC(a[43], a[50]); SQRADDAC(a[44], a[49]); SQRADDAC(a[45], a[48]); SQRADDAC(a[46], a[47]); SQRADDDB; 
+   COMBA_STORE(b[93]);
+
+   /* output 94 */
+   CARRY_FORWARD;
+   SQRADDSC(a[31], a[63]); SQRADDAC(a[32], a[62]); SQRADDAC(a[33], a[61]); SQRADDAC(a[34], a[60]); SQRADDAC(a[35], a[59]); SQRADDAC(a[36], a[58]); SQRADDAC(a[37], a[57]); SQRADDAC(a[38], a[56]); SQRADDAC(a[39], a[55]); SQRADDAC(a[40], a[54]); SQRADDAC(a[41], a[53]); SQRADDAC(a[42], a[52]); SQRADDAC(a[43], a[51]); SQRADDAC(a[44], a[50]); SQRADDAC(a[45], a[49]); SQRADDAC(a[46], a[48]); SQRADDDB; SQRADD(a[47], a[47]); 
+   COMBA_STORE(b[94]);
+
+   /* output 95 */
+   CARRY_FORWARD;
+   SQRADDSC(a[32], a[63]); SQRADDAC(a[33], a[62]); SQRADDAC(a[34], a[61]); SQRADDAC(a[35], a[60]); SQRADDAC(a[36], a[59]); SQRADDAC(a[37], a[58]); SQRADDAC(a[38], a[57]); SQRADDAC(a[39], a[56]); SQRADDAC(a[40], a[55]); SQRADDAC(a[41], a[54]); SQRADDAC(a[42], a[53]); SQRADDAC(a[43], a[52]); SQRADDAC(a[44], a[51]); SQRADDAC(a[45], a[50]); SQRADDAC(a[46], a[49]); SQRADDAC(a[47], a[48]); SQRADDDB; 
+   COMBA_STORE(b[95]);
+
+   /* output 96 */
+   CARRY_FORWARD;
+   SQRADDSC(a[33], a[63]); SQRADDAC(a[34], a[62]); SQRADDAC(a[35], a[61]); SQRADDAC(a[36], a[60]); SQRADDAC(a[37], a[59]); SQRADDAC(a[38], a[58]); SQRADDAC(a[39], a[57]); SQRADDAC(a[40], a[56]); SQRADDAC(a[41], a[55]); SQRADDAC(a[42], a[54]); SQRADDAC(a[43], a[53]); SQRADDAC(a[44], a[52]); SQRADDAC(a[45], a[51]); SQRADDAC(a[46], a[50]); SQRADDAC(a[47], a[49]); SQRADDDB; SQRADD(a[48], a[48]); 
+   COMBA_STORE(b[96]);
+
+   /* output 97 */
+   CARRY_FORWARD;
+   SQRADDSC(a[34], a[63]); SQRADDAC(a[35], a[62]); SQRADDAC(a[36], a[61]); SQRADDAC(a[37], a[60]); SQRADDAC(a[38], a[59]); SQRADDAC(a[39], a[58]); SQRADDAC(a[40], a[57]); SQRADDAC(a[41], a[56]); SQRADDAC(a[42], a[55]); SQRADDAC(a[43], a[54]); SQRADDAC(a[44], a[53]); SQRADDAC(a[45], a[52]); SQRADDAC(a[46], a[51]); SQRADDAC(a[47], a[50]); SQRADDAC(a[48], a[49]); SQRADDDB; 
+   COMBA_STORE(b[97]);
+
+   /* output 98 */
+   CARRY_FORWARD;
+   SQRADDSC(a[35], a[63]); SQRADDAC(a[36], a[62]); SQRADDAC(a[37], a[61]); SQRADDAC(a[38], a[60]); SQRADDAC(a[39], a[59]); SQRADDAC(a[40], a[58]); SQRADDAC(a[41], a[57]); SQRADDAC(a[42], a[56]); SQRADDAC(a[43], a[55]); SQRADDAC(a[44], a[54]); SQRADDAC(a[45], a[53]); SQRADDAC(a[46], a[52]); SQRADDAC(a[47], a[51]); SQRADDAC(a[48], a[50]); SQRADDDB; SQRADD(a[49], a[49]); 
+   COMBA_STORE(b[98]);
+
+   /* output 99 */
+   CARRY_FORWARD;
+   SQRADDSC(a[36], a[63]); SQRADDAC(a[37], a[62]); SQRADDAC(a[38], a[61]); SQRADDAC(a[39], a[60]); SQRADDAC(a[40], a[59]); SQRADDAC(a[41], a[58]); SQRADDAC(a[42], a[57]); SQRADDAC(a[43], a[56]); SQRADDAC(a[44], a[55]); SQRADDAC(a[45], a[54]); SQRADDAC(a[46], a[53]); SQRADDAC(a[47], a[52]); SQRADDAC(a[48], a[51]); SQRADDAC(a[49], a[50]); SQRADDDB; 
+   COMBA_STORE(b[99]);
+
+   /* output 100 */
+   CARRY_FORWARD;
+   SQRADDSC(a[37], a[63]); SQRADDAC(a[38], a[62]); SQRADDAC(a[39], a[61]); SQRADDAC(a[40], a[60]); SQRADDAC(a[41], a[59]); SQRADDAC(a[42], a[58]); SQRADDAC(a[43], a[57]); SQRADDAC(a[44], a[56]); SQRADDAC(a[45], a[55]); SQRADDAC(a[46], a[54]); SQRADDAC(a[47], a[53]); SQRADDAC(a[48], a[52]); SQRADDAC(a[49], a[51]); SQRADDDB; SQRADD(a[50], a[50]); 
+   COMBA_STORE(b[100]);
+
+   /* output 101 */
+   CARRY_FORWARD;
+   SQRADDSC(a[38], a[63]); SQRADDAC(a[39], a[62]); SQRADDAC(a[40], a[61]); SQRADDAC(a[41], a[60]); SQRADDAC(a[42], a[59]); SQRADDAC(a[43], a[58]); SQRADDAC(a[44], a[57]); SQRADDAC(a[45], a[56]); SQRADDAC(a[46], a[55]); SQRADDAC(a[47], a[54]); SQRADDAC(a[48], a[53]); SQRADDAC(a[49], a[52]); SQRADDAC(a[50], a[51]); SQRADDDB; 
+   COMBA_STORE(b[101]);
+
+   /* output 102 */
+   CARRY_FORWARD;
+   SQRADDSC(a[39], a[63]); SQRADDAC(a[40], a[62]); SQRADDAC(a[41], a[61]); SQRADDAC(a[42], a[60]); SQRADDAC(a[43], a[59]); SQRADDAC(a[44], a[58]); SQRADDAC(a[45], a[57]); SQRADDAC(a[46], a[56]); SQRADDAC(a[47], a[55]); SQRADDAC(a[48], a[54]); SQRADDAC(a[49], a[53]); SQRADDAC(a[50], a[52]); SQRADDDB; SQRADD(a[51], a[51]); 
+   COMBA_STORE(b[102]);
+
+   /* output 103 */
+   CARRY_FORWARD;
+   SQRADDSC(a[40], a[63]); SQRADDAC(a[41], a[62]); SQRADDAC(a[42], a[61]); SQRADDAC(a[43], a[60]); SQRADDAC(a[44], a[59]); SQRADDAC(a[45], a[58]); SQRADDAC(a[46], a[57]); SQRADDAC(a[47], a[56]); SQRADDAC(a[48], a[55]); SQRADDAC(a[49], a[54]); SQRADDAC(a[50], a[53]); SQRADDAC(a[51], a[52]); SQRADDDB; 
+   COMBA_STORE(b[103]);
+
+   /* output 104 */
+   CARRY_FORWARD;
+   SQRADDSC(a[41], a[63]); SQRADDAC(a[42], a[62]); SQRADDAC(a[43], a[61]); SQRADDAC(a[44], a[60]); SQRADDAC(a[45], a[59]); SQRADDAC(a[46], a[58]); SQRADDAC(a[47], a[57]); SQRADDAC(a[48], a[56]); SQRADDAC(a[49], a[55]); SQRADDAC(a[50], a[54]); SQRADDAC(a[51], a[53]); SQRADDDB; SQRADD(a[52], a[52]); 
+   COMBA_STORE(b[104]);
+
+   /* output 105 */
+   CARRY_FORWARD;
+   SQRADDSC(a[42], a[63]); SQRADDAC(a[43], a[62]); SQRADDAC(a[44], a[61]); SQRADDAC(a[45], a[60]); SQRADDAC(a[46], a[59]); SQRADDAC(a[47], a[58]); SQRADDAC(a[48], a[57]); SQRADDAC(a[49], a[56]); SQRADDAC(a[50], a[55]); SQRADDAC(a[51], a[54]); SQRADDAC(a[52], a[53]); SQRADDDB; 
+   COMBA_STORE(b[105]);
+
+   /* output 106 */
+   CARRY_FORWARD;
+   SQRADDSC(a[43], a[63]); SQRADDAC(a[44], a[62]); SQRADDAC(a[45], a[61]); SQRADDAC(a[46], a[60]); SQRADDAC(a[47], a[59]); SQRADDAC(a[48], a[58]); SQRADDAC(a[49], a[57]); SQRADDAC(a[50], a[56]); SQRADDAC(a[51], a[55]); SQRADDAC(a[52], a[54]); SQRADDDB; SQRADD(a[53], a[53]); 
+   COMBA_STORE(b[106]);
+
+   /* output 107 */
+   CARRY_FORWARD;
+   SQRADDSC(a[44], a[63]); SQRADDAC(a[45], a[62]); SQRADDAC(a[46], a[61]); SQRADDAC(a[47], a[60]); SQRADDAC(a[48], a[59]); SQRADDAC(a[49], a[58]); SQRADDAC(a[50], a[57]); SQRADDAC(a[51], a[56]); SQRADDAC(a[52], a[55]); SQRADDAC(a[53], a[54]); SQRADDDB; 
+   COMBA_STORE(b[107]);
+
+   /* output 108 */
+   CARRY_FORWARD;
+   SQRADDSC(a[45], a[63]); SQRADDAC(a[46], a[62]); SQRADDAC(a[47], a[61]); SQRADDAC(a[48], a[60]); SQRADDAC(a[49], a[59]); SQRADDAC(a[50], a[58]); SQRADDAC(a[51], a[57]); SQRADDAC(a[52], a[56]); SQRADDAC(a[53], a[55]); SQRADDDB; SQRADD(a[54], a[54]); 
+   COMBA_STORE(b[108]);
+
+   /* output 109 */
+   CARRY_FORWARD;
+   SQRADDSC(a[46], a[63]); SQRADDAC(a[47], a[62]); SQRADDAC(a[48], a[61]); SQRADDAC(a[49], a[60]); SQRADDAC(a[50], a[59]); SQRADDAC(a[51], a[58]); SQRADDAC(a[52], a[57]); SQRADDAC(a[53], a[56]); SQRADDAC(a[54], a[55]); SQRADDDB; 
+   COMBA_STORE(b[109]);
+
+   /* output 110 */
+   CARRY_FORWARD;
+   SQRADDSC(a[47], a[63]); SQRADDAC(a[48], a[62]); SQRADDAC(a[49], a[61]); SQRADDAC(a[50], a[60]); SQRADDAC(a[51], a[59]); SQRADDAC(a[52], a[58]); SQRADDAC(a[53], a[57]); SQRADDAC(a[54], a[56]); SQRADDDB; SQRADD(a[55], a[55]); 
+   COMBA_STORE(b[110]);
+
+   /* output 111 */
+   CARRY_FORWARD;
+   SQRADDSC(a[48], a[63]); SQRADDAC(a[49], a[62]); SQRADDAC(a[50], a[61]); SQRADDAC(a[51], a[60]); SQRADDAC(a[52], a[59]); SQRADDAC(a[53], a[58]); SQRADDAC(a[54], a[57]); SQRADDAC(a[55], a[56]); SQRADDDB; 
+   COMBA_STORE(b[111]);
+
+   /* output 112 */
+   CARRY_FORWARD;
+   SQRADDSC(a[49], a[63]); SQRADDAC(a[50], a[62]); SQRADDAC(a[51], a[61]); SQRADDAC(a[52], a[60]); SQRADDAC(a[53], a[59]); SQRADDAC(a[54], a[58]); SQRADDAC(a[55], a[57]); SQRADDDB; SQRADD(a[56], a[56]); 
+   COMBA_STORE(b[112]);
+
+   /* output 113 */
+   CARRY_FORWARD;
+   SQRADDSC(a[50], a[63]); SQRADDAC(a[51], a[62]); SQRADDAC(a[52], a[61]); SQRADDAC(a[53], a[60]); SQRADDAC(a[54], a[59]); SQRADDAC(a[55], a[58]); SQRADDAC(a[56], a[57]); SQRADDDB; 
+   COMBA_STORE(b[113]);
+
+   /* output 114 */
+   CARRY_FORWARD;
+   SQRADDSC(a[51], a[63]); SQRADDAC(a[52], a[62]); SQRADDAC(a[53], a[61]); SQRADDAC(a[54], a[60]); SQRADDAC(a[55], a[59]); SQRADDAC(a[56], a[58]); SQRADDDB; SQRADD(a[57], a[57]); 
+   COMBA_STORE(b[114]);
+
+   /* output 115 */
+   CARRY_FORWARD;
+   SQRADDSC(a[52], a[63]); SQRADDAC(a[53], a[62]); SQRADDAC(a[54], a[61]); SQRADDAC(a[55], a[60]); SQRADDAC(a[56], a[59]); SQRADDAC(a[57], a[58]); SQRADDDB; 
+   COMBA_STORE(b[115]);
+
+   /* output 116 */
+   CARRY_FORWARD;
+   SQRADDSC(a[53], a[63]); SQRADDAC(a[54], a[62]); SQRADDAC(a[55], a[61]); SQRADDAC(a[56], a[60]); SQRADDAC(a[57], a[59]); SQRADDDB; SQRADD(a[58], a[58]); 
+   COMBA_STORE(b[116]);
+
+   /* output 117 */
+   CARRY_FORWARD;
+   SQRADDSC(a[54], a[63]); SQRADDAC(a[55], a[62]); SQRADDAC(a[56], a[61]); SQRADDAC(a[57], a[60]); SQRADDAC(a[58], a[59]); SQRADDDB; 
+   COMBA_STORE(b[117]);
+
+   /* output 118 */
+   CARRY_FORWARD;
+   SQRADDSC(a[55], a[63]); SQRADDAC(a[56], a[62]); SQRADDAC(a[57], a[61]); SQRADDAC(a[58], a[60]); SQRADDDB; SQRADD(a[59], a[59]); 
+   COMBA_STORE(b[118]);
+
+   /* output 119 */
+   CARRY_FORWARD;
+   SQRADDSC(a[56], a[63]); SQRADDAC(a[57], a[62]); SQRADDAC(a[58], a[61]); SQRADDAC(a[59], a[60]); SQRADDDB; 
+   COMBA_STORE(b[119]);
+
+   /* output 120 */
+   CARRY_FORWARD;
+   SQRADDSC(a[57], a[63]); SQRADDAC(a[58], a[62]); SQRADDAC(a[59], a[61]); SQRADDDB; SQRADD(a[60], a[60]); 
+   COMBA_STORE(b[120]);
+
+   /* output 121 */
+   CARRY_FORWARD;
+   SQRADDSC(a[58], a[63]); SQRADDAC(a[59], a[62]); SQRADDAC(a[60], a[61]); SQRADDDB; 
+   COMBA_STORE(b[121]);
+
+   /* output 122 */
+   CARRY_FORWARD;
+   SQRADD2(a[59], a[63]); SQRADD2(a[60], a[62]); SQRADD(a[61], a[61]); 
+   COMBA_STORE(b[122]);
+
+   /* output 123 */
+   CARRY_FORWARD;
+   SQRADD2(a[60], a[63]); SQRADD2(a[61], a[62]); 
+   COMBA_STORE(b[123]);
+
+   /* output 124 */
+   CARRY_FORWARD;
+   SQRADD2(a[61], a[63]); SQRADD(a[62], a[62]); 
+   COMBA_STORE(b[124]);
+
+   /* output 125 */
+   CARRY_FORWARD;
+   SQRADD2(a[62], a[63]); 
+   COMBA_STORE(b[125]);
+
+   /* output 126 */
+   CARRY_FORWARD;
+   SQRADD(a[63], a[63]); 
+   COMBA_STORE(b[126]);
+   COMBA_STORE2(b[127]);
+   COMBA_FINI;
+
+   B->used = 128;
+   B->sign = FP_ZPOS;
+   memcpy(B->dp, b, 128 * sizeof(fp_digit));
+   fp_clamp(B);
+}
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_7.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_7.i
new file mode 100644
index 0000000..8ddef1a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_7.i
@@ -0,0 +1,110 @@
+/* fp_sqr_comba_7.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_SQR7
+void fp_sqr_comba7(fp_int *A, fp_int *B)
+{
+   fp_digit *a, b[14], c0, c1, c2, sc0, sc1, sc2;
+#ifdef TFM_ISO
+   fp_word tt;
+#endif
+
+   a = A->dp;
+   COMBA_START; 
+
+   /* clear carries */
+   CLEAR_CARRY;
+
+   /* output 0 */
+   SQRADD(a[0],a[0]);
+   COMBA_STORE(b[0]);
+
+   /* output 1 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[1]); 
+   COMBA_STORE(b[1]);
+
+   /* output 2 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[2]); SQRADD(a[1], a[1]); 
+   COMBA_STORE(b[2]);
+
+   /* output 3 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[3]); SQRADD2(a[1], a[2]); 
+   COMBA_STORE(b[3]);
+
+   /* output 4 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[4]); SQRADD2(a[1], a[3]); SQRADD(a[2], a[2]); 
+   COMBA_STORE(b[4]);
+
+   /* output 5 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[5]); SQRADDAC(a[1], a[4]); SQRADDAC(a[2], a[3]); SQRADDDB; 
+   COMBA_STORE(b[5]);
+
+   /* output 6 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[6]); SQRADDAC(a[1], a[5]); SQRADDAC(a[2], a[4]); SQRADDDB; SQRADD(a[3], a[3]); 
+   COMBA_STORE(b[6]);
+
+   /* output 7 */
+   CARRY_FORWARD;
+   SQRADDSC(a[1], a[6]); SQRADDAC(a[2], a[5]); SQRADDAC(a[3], a[4]); SQRADDDB; 
+   COMBA_STORE(b[7]);
+
+   /* output 8 */
+   CARRY_FORWARD;
+   SQRADD2(a[2], a[6]); SQRADD2(a[3], a[5]); SQRADD(a[4], a[4]); 
+   COMBA_STORE(b[8]);
+
+   /* output 9 */
+   CARRY_FORWARD;
+   SQRADD2(a[3], a[6]); SQRADD2(a[4], a[5]); 
+   COMBA_STORE(b[9]);
+
+   /* output 10 */
+   CARRY_FORWARD;
+   SQRADD2(a[4], a[6]); SQRADD(a[5], a[5]); 
+   COMBA_STORE(b[10]);
+
+   /* output 11 */
+   CARRY_FORWARD;
+   SQRADD2(a[5], a[6]); 
+   COMBA_STORE(b[11]);
+
+   /* output 12 */
+   CARRY_FORWARD;
+   SQRADD(a[6], a[6]); 
+   COMBA_STORE(b[12]);
+   COMBA_STORE2(b[13]);
+   COMBA_FINI;
+
+   B->used = 14;
+   B->sign = FP_ZPOS;
+   memcpy(B->dp, b, 14 * sizeof(fp_digit));
+   fp_clamp(B);
+}
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_8.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_8.i
new file mode 100644
index 0000000..f9a72bc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_8.i
@@ -0,0 +1,120 @@
+/* fp_sqr_comba_8.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_SQR8
+void fp_sqr_comba8(fp_int *A, fp_int *B)
+{
+   fp_digit *a, b[16], c0, c1, c2, sc0, sc1, sc2;
+#ifdef TFM_ISO
+   fp_word   tt;   
+#endif   
+
+   a = A->dp;
+   COMBA_START; 
+
+   /* clear carries */
+   CLEAR_CARRY;
+
+   /* output 0 */
+   SQRADD(a[0],a[0]);
+   COMBA_STORE(b[0]);
+
+   /* output 1 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[1]); 
+   COMBA_STORE(b[1]);
+
+   /* output 2 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[2]); SQRADD(a[1], a[1]); 
+   COMBA_STORE(b[2]);
+
+   /* output 3 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[3]); SQRADD2(a[1], a[2]); 
+   COMBA_STORE(b[3]);
+
+   /* output 4 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[4]); SQRADD2(a[1], a[3]); SQRADD(a[2], a[2]); 
+   COMBA_STORE(b[4]);
+
+   /* output 5 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[5]); SQRADDAC(a[1], a[4]); SQRADDAC(a[2], a[3]); SQRADDDB; 
+   COMBA_STORE(b[5]);
+
+   /* output 6 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[6]); SQRADDAC(a[1], a[5]); SQRADDAC(a[2], a[4]); SQRADDDB; SQRADD(a[3], a[3]); 
+   COMBA_STORE(b[6]);
+
+   /* output 7 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[7]); SQRADDAC(a[1], a[6]); SQRADDAC(a[2], a[5]); SQRADDAC(a[3], a[4]); SQRADDDB; 
+   COMBA_STORE(b[7]);
+
+   /* output 8 */
+   CARRY_FORWARD;
+   SQRADDSC(a[1], a[7]); SQRADDAC(a[2], a[6]); SQRADDAC(a[3], a[5]); SQRADDDB; SQRADD(a[4], a[4]); 
+   COMBA_STORE(b[8]);
+
+   /* output 9 */
+   CARRY_FORWARD;
+   SQRADDSC(a[2], a[7]); SQRADDAC(a[3], a[6]); SQRADDAC(a[4], a[5]); SQRADDDB; 
+   COMBA_STORE(b[9]);
+
+   /* output 10 */
+   CARRY_FORWARD;
+   SQRADD2(a[3], a[7]); SQRADD2(a[4], a[6]); SQRADD(a[5], a[5]); 
+   COMBA_STORE(b[10]);
+
+   /* output 11 */
+   CARRY_FORWARD;
+   SQRADD2(a[4], a[7]); SQRADD2(a[5], a[6]); 
+   COMBA_STORE(b[11]);
+
+   /* output 12 */
+   CARRY_FORWARD;
+   SQRADD2(a[5], a[7]); SQRADD(a[6], a[6]); 
+   COMBA_STORE(b[12]);
+
+   /* output 13 */
+   CARRY_FORWARD;
+   SQRADD2(a[6], a[7]); 
+   COMBA_STORE(b[13]);
+
+   /* output 14 */
+   CARRY_FORWARD;
+   SQRADD(a[7], a[7]); 
+   COMBA_STORE(b[14]);
+   COMBA_STORE2(b[15]);
+   COMBA_FINI;
+
+   B->used = 16;
+   B->sign = FP_ZPOS;
+   memcpy(B->dp, b, 16 * sizeof(fp_digit));
+   fp_clamp(B);
+}
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_9.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_9.i
new file mode 100644
index 0000000..94a5d2e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_9.i
@@ -0,0 +1,130 @@
+/* fp_sqr_comba_9.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef TFM_SQR9
+void fp_sqr_comba9(fp_int *A, fp_int *B)
+{
+   fp_digit *a, b[18], c0, c1, c2, sc0, sc1, sc2;
+#ifdef TFM_ISO
+   fp_word tt;
+#endif
+
+   a = A->dp;
+   COMBA_START; 
+
+   /* clear carries */
+   CLEAR_CARRY;
+
+   /* output 0 */
+   SQRADD(a[0],a[0]);
+   COMBA_STORE(b[0]);
+
+   /* output 1 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[1]); 
+   COMBA_STORE(b[1]);
+
+   /* output 2 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[2]); SQRADD(a[1], a[1]); 
+   COMBA_STORE(b[2]);
+
+   /* output 3 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[3]); SQRADD2(a[1], a[2]); 
+   COMBA_STORE(b[3]);
+
+   /* output 4 */
+   CARRY_FORWARD;
+   SQRADD2(a[0], a[4]); SQRADD2(a[1], a[3]); SQRADD(a[2], a[2]); 
+   COMBA_STORE(b[4]);
+
+   /* output 5 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[5]); SQRADDAC(a[1], a[4]); SQRADDAC(a[2], a[3]); SQRADDDB; 
+   COMBA_STORE(b[5]);
+
+   /* output 6 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[6]); SQRADDAC(a[1], a[5]); SQRADDAC(a[2], a[4]); SQRADDDB; SQRADD(a[3], a[3]); 
+   COMBA_STORE(b[6]);
+
+   /* output 7 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[7]); SQRADDAC(a[1], a[6]); SQRADDAC(a[2], a[5]); SQRADDAC(a[3], a[4]); SQRADDDB; 
+   COMBA_STORE(b[7]);
+
+   /* output 8 */
+   CARRY_FORWARD;
+   SQRADDSC(a[0], a[8]); SQRADDAC(a[1], a[7]); SQRADDAC(a[2], a[6]); SQRADDAC(a[3], a[5]); SQRADDDB; SQRADD(a[4], a[4]); 
+   COMBA_STORE(b[8]);
+
+   /* output 9 */
+   CARRY_FORWARD;
+   SQRADDSC(a[1], a[8]); SQRADDAC(a[2], a[7]); SQRADDAC(a[3], a[6]); SQRADDAC(a[4], a[5]); SQRADDDB; 
+   COMBA_STORE(b[9]);
+
+   /* output 10 */
+   CARRY_FORWARD;
+   SQRADDSC(a[2], a[8]); SQRADDAC(a[3], a[7]); SQRADDAC(a[4], a[6]); SQRADDDB; SQRADD(a[5], a[5]); 
+   COMBA_STORE(b[10]);
+
+   /* output 11 */
+   CARRY_FORWARD;
+   SQRADDSC(a[3], a[8]); SQRADDAC(a[4], a[7]); SQRADDAC(a[5], a[6]); SQRADDDB; 
+   COMBA_STORE(b[11]);
+
+   /* output 12 */
+   CARRY_FORWARD;
+   SQRADD2(a[4], a[8]); SQRADD2(a[5], a[7]); SQRADD(a[6], a[6]); 
+   COMBA_STORE(b[12]);
+
+   /* output 13 */
+   CARRY_FORWARD;
+   SQRADD2(a[5], a[8]); SQRADD2(a[6], a[7]); 
+   COMBA_STORE(b[13]);
+
+   /* output 14 */
+   CARRY_FORWARD;
+   SQRADD2(a[6], a[8]); SQRADD(a[7], a[7]); 
+   COMBA_STORE(b[14]);
+
+   /* output 15 */
+   CARRY_FORWARD;
+   SQRADD2(a[7], a[8]); 
+   COMBA_STORE(b[15]);
+
+   /* output 16 */
+   CARRY_FORWARD;
+   SQRADD(a[8], a[8]); 
+   COMBA_STORE(b[16]);
+   COMBA_STORE2(b[17]);
+   COMBA_FINI;
+
+   B->used = 18;
+   B->sign = FP_ZPOS;
+   memcpy(B->dp, b, 18 * sizeof(fp_digit));
+   fp_clamp(B);
+}
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_small_set.i b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_small_set.i
new file mode 100644
index 0000000..9918b2e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/fp_sqr_comba_small_set.i
@@ -0,0 +1,1540 @@
+/* fp_sqr_comba_small_set.i
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#if defined(TFM_SMALL_SET)
+void fp_sqr_comba_small(fp_int *A, fp_int *B)
+{
+   fp_digit *a, b[32], c0, c1, c2, sc0, sc1, sc2;
+#ifdef TFM_ISO
+   fp_word   tt;   
+#endif   
+   switch (A->used) { 
+   case 1:
+      a = A->dp;
+      COMBA_START; 
+
+      /* clear carries */
+      CLEAR_CARRY;
+
+      /* output 0 */
+      SQRADD(a[0],a[0]);
+      COMBA_STORE(b[0]);
+      COMBA_STORE2(b[1]);
+      COMBA_FINI;
+
+      B->used = 2;
+      B->sign = FP_ZPOS;
+      memcpy(B->dp, b, 2 * sizeof(fp_digit));
+      fp_clamp(B);
+      break;
+
+   case 2:
+      a = A->dp;
+      COMBA_START; 
+
+      /* clear carries */
+      CLEAR_CARRY;
+
+      /* output 0 */
+      SQRADD(a[0],a[0]);
+      COMBA_STORE(b[0]);
+
+      /* output 1 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[1]); 
+      COMBA_STORE(b[1]);
+
+      /* output 2 */
+      CARRY_FORWARD;
+      SQRADD(a[1], a[1]); 
+      COMBA_STORE(b[2]);
+      COMBA_STORE2(b[3]);
+      COMBA_FINI;
+
+      B->used = 4;
+      B->sign = FP_ZPOS;
+      memcpy(B->dp, b, 4 * sizeof(fp_digit));
+      fp_clamp(B);
+      break;
+
+   case 3:
+      a = A->dp;
+      COMBA_START; 
+
+      /* clear carries */
+      CLEAR_CARRY;
+
+      /* output 0 */
+      SQRADD(a[0],a[0]);
+      COMBA_STORE(b[0]);
+
+      /* output 1 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[1]); 
+      COMBA_STORE(b[1]);
+
+      /* output 2 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[2]);    SQRADD(a[1], a[1]); 
+      COMBA_STORE(b[2]);
+
+      /* output 3 */
+      CARRY_FORWARD;
+      SQRADD2(a[1], a[2]); 
+      COMBA_STORE(b[3]);
+
+      /* output 4 */
+      CARRY_FORWARD;
+      SQRADD(a[2], a[2]); 
+      COMBA_STORE(b[4]);
+      COMBA_STORE2(b[5]);
+      COMBA_FINI;
+
+      B->used = 6;
+      B->sign = FP_ZPOS;
+      memcpy(B->dp, b, 6 * sizeof(fp_digit));
+      fp_clamp(B);
+      break;
+
+   case 4:
+      a = A->dp;
+      COMBA_START; 
+
+      /* clear carries */
+      CLEAR_CARRY;
+
+      /* output 0 */
+      SQRADD(a[0],a[0]);
+      COMBA_STORE(b[0]);
+
+      /* output 1 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[1]); 
+      COMBA_STORE(b[1]);
+
+      /* output 2 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[2]);    SQRADD(a[1], a[1]); 
+      COMBA_STORE(b[2]);
+
+      /* output 3 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[3]);    SQRADD2(a[1], a[2]); 
+      COMBA_STORE(b[3]);
+
+      /* output 4 */
+      CARRY_FORWARD;
+      SQRADD2(a[1], a[3]);    SQRADD(a[2], a[2]); 
+      COMBA_STORE(b[4]);
+
+      /* output 5 */
+      CARRY_FORWARD;
+      SQRADD2(a[2], a[3]); 
+      COMBA_STORE(b[5]);
+
+      /* output 6 */
+      CARRY_FORWARD;
+      SQRADD(a[3], a[3]); 
+      COMBA_STORE(b[6]);
+      COMBA_STORE2(b[7]);
+      COMBA_FINI;
+
+      B->used = 8;
+      B->sign = FP_ZPOS;
+      memcpy(B->dp, b, 8 * sizeof(fp_digit));
+      fp_clamp(B);
+      break;
+
+   case 5:
+      a = A->dp;
+      COMBA_START; 
+
+      /* clear carries */
+      CLEAR_CARRY;
+
+      /* output 0 */
+      SQRADD(a[0],a[0]);
+      COMBA_STORE(b[0]);
+
+      /* output 1 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[1]); 
+      COMBA_STORE(b[1]);
+
+      /* output 2 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[2]);    SQRADD(a[1], a[1]); 
+      COMBA_STORE(b[2]);
+
+      /* output 3 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[3]);    SQRADD2(a[1], a[2]); 
+      COMBA_STORE(b[3]);
+
+      /* output 4 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[4]);    SQRADD2(a[1], a[3]);    SQRADD(a[2], a[2]); 
+      COMBA_STORE(b[4]);
+
+      /* output 5 */
+      CARRY_FORWARD;
+      SQRADD2(a[1], a[4]);    SQRADD2(a[2], a[3]); 
+      COMBA_STORE(b[5]);
+
+      /* output 6 */
+      CARRY_FORWARD;
+      SQRADD2(a[2], a[4]);    SQRADD(a[3], a[3]); 
+      COMBA_STORE(b[6]);
+
+      /* output 7 */
+      CARRY_FORWARD;
+      SQRADD2(a[3], a[4]); 
+      COMBA_STORE(b[7]);
+
+      /* output 8 */
+      CARRY_FORWARD;
+      SQRADD(a[4], a[4]); 
+      COMBA_STORE(b[8]);
+      COMBA_STORE2(b[9]);
+      COMBA_FINI;
+
+      B->used = 10;
+      B->sign = FP_ZPOS;
+      memcpy(B->dp, b, 10 * sizeof(fp_digit));
+      fp_clamp(B);
+      break;
+
+   case 6:
+      a = A->dp;
+      COMBA_START; 
+
+      /* clear carries */
+      CLEAR_CARRY;
+
+      /* output 0 */
+      SQRADD(a[0],a[0]);
+      COMBA_STORE(b[0]);
+
+      /* output 1 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[1]); 
+      COMBA_STORE(b[1]);
+
+      /* output 2 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[2]);    SQRADD(a[1], a[1]); 
+      COMBA_STORE(b[2]);
+
+      /* output 3 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[3]);    SQRADD2(a[1], a[2]); 
+      COMBA_STORE(b[3]);
+
+      /* output 4 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[4]);    SQRADD2(a[1], a[3]);    SQRADD(a[2], a[2]); 
+      COMBA_STORE(b[4]);
+
+      /* output 5 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[5]); SQRADDAC(a[1], a[4]); SQRADDAC(a[2], a[3]); SQRADDDB; 
+      COMBA_STORE(b[5]);
+
+      /* output 6 */
+      CARRY_FORWARD;
+      SQRADD2(a[1], a[5]);    SQRADD2(a[2], a[4]);    SQRADD(a[3], a[3]); 
+      COMBA_STORE(b[6]);
+
+      /* output 7 */
+      CARRY_FORWARD;
+      SQRADD2(a[2], a[5]);    SQRADD2(a[3], a[4]); 
+      COMBA_STORE(b[7]);
+
+      /* output 8 */
+      CARRY_FORWARD;
+      SQRADD2(a[3], a[5]);    SQRADD(a[4], a[4]); 
+      COMBA_STORE(b[8]);
+
+      /* output 9 */
+      CARRY_FORWARD;
+      SQRADD2(a[4], a[5]); 
+      COMBA_STORE(b[9]);
+
+      /* output 10 */
+      CARRY_FORWARD;
+      SQRADD(a[5], a[5]); 
+      COMBA_STORE(b[10]);
+      COMBA_STORE2(b[11]);
+      COMBA_FINI;
+
+      B->used = 12;
+      B->sign = FP_ZPOS;
+      memcpy(B->dp, b, 12 * sizeof(fp_digit));
+      fp_clamp(B);
+      break;
+
+   case 7:
+      a = A->dp;
+      COMBA_START; 
+
+      /* clear carries */
+      CLEAR_CARRY;
+
+      /* output 0 */
+      SQRADD(a[0],a[0]);
+      COMBA_STORE(b[0]);
+
+      /* output 1 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[1]); 
+      COMBA_STORE(b[1]);
+
+      /* output 2 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[2]);    SQRADD(a[1], a[1]); 
+      COMBA_STORE(b[2]);
+
+      /* output 3 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[3]);    SQRADD2(a[1], a[2]); 
+      COMBA_STORE(b[3]);
+
+      /* output 4 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[4]);    SQRADD2(a[1], a[3]);    SQRADD(a[2], a[2]); 
+      COMBA_STORE(b[4]);
+
+      /* output 5 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[5]); SQRADDAC(a[1], a[4]); SQRADDAC(a[2], a[3]); SQRADDDB; 
+      COMBA_STORE(b[5]);
+
+      /* output 6 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[6]); SQRADDAC(a[1], a[5]); SQRADDAC(a[2], a[4]); SQRADDDB; SQRADD(a[3], a[3]); 
+      COMBA_STORE(b[6]);
+
+      /* output 7 */
+      CARRY_FORWARD;
+   SQRADDSC(a[1], a[6]); SQRADDAC(a[2], a[5]); SQRADDAC(a[3], a[4]); SQRADDDB; 
+      COMBA_STORE(b[7]);
+
+      /* output 8 */
+      CARRY_FORWARD;
+      SQRADD2(a[2], a[6]);    SQRADD2(a[3], a[5]);    SQRADD(a[4], a[4]); 
+      COMBA_STORE(b[8]);
+
+      /* output 9 */
+      CARRY_FORWARD;
+      SQRADD2(a[3], a[6]);    SQRADD2(a[4], a[5]); 
+      COMBA_STORE(b[9]);
+
+      /* output 10 */
+      CARRY_FORWARD;
+      SQRADD2(a[4], a[6]);    SQRADD(a[5], a[5]); 
+      COMBA_STORE(b[10]);
+
+      /* output 11 */
+      CARRY_FORWARD;
+      SQRADD2(a[5], a[6]); 
+      COMBA_STORE(b[11]);
+
+      /* output 12 */
+      CARRY_FORWARD;
+      SQRADD(a[6], a[6]); 
+      COMBA_STORE(b[12]);
+      COMBA_STORE2(b[13]);
+      COMBA_FINI;
+
+      B->used = 14;
+      B->sign = FP_ZPOS;
+      memcpy(B->dp, b, 14 * sizeof(fp_digit));
+      fp_clamp(B);
+      break;
+
+   case 8:
+      a = A->dp;
+      COMBA_START; 
+
+      /* clear carries */
+      CLEAR_CARRY;
+
+      /* output 0 */
+      SQRADD(a[0],a[0]);
+      COMBA_STORE(b[0]);
+
+      /* output 1 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[1]); 
+      COMBA_STORE(b[1]);
+
+      /* output 2 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[2]);    SQRADD(a[1], a[1]); 
+      COMBA_STORE(b[2]);
+
+      /* output 3 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[3]);    SQRADD2(a[1], a[2]); 
+      COMBA_STORE(b[3]);
+
+      /* output 4 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[4]);    SQRADD2(a[1], a[3]);    SQRADD(a[2], a[2]); 
+      COMBA_STORE(b[4]);
+
+      /* output 5 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[5]); SQRADDAC(a[1], a[4]); SQRADDAC(a[2], a[3]); SQRADDDB; 
+      COMBA_STORE(b[5]);
+
+      /* output 6 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[6]); SQRADDAC(a[1], a[5]); SQRADDAC(a[2], a[4]); SQRADDDB; SQRADD(a[3], a[3]); 
+      COMBA_STORE(b[6]);
+
+      /* output 7 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[7]); SQRADDAC(a[1], a[6]); SQRADDAC(a[2], a[5]); SQRADDAC(a[3], a[4]); SQRADDDB; 
+      COMBA_STORE(b[7]);
+
+      /* output 8 */
+      CARRY_FORWARD;
+   SQRADDSC(a[1], a[7]); SQRADDAC(a[2], a[6]); SQRADDAC(a[3], a[5]); SQRADDDB; SQRADD(a[4], a[4]); 
+      COMBA_STORE(b[8]);
+
+      /* output 9 */
+      CARRY_FORWARD;
+   SQRADDSC(a[2], a[7]); SQRADDAC(a[3], a[6]); SQRADDAC(a[4], a[5]); SQRADDDB; 
+      COMBA_STORE(b[9]);
+
+      /* output 10 */
+      CARRY_FORWARD;
+      SQRADD2(a[3], a[7]);    SQRADD2(a[4], a[6]);    SQRADD(a[5], a[5]); 
+      COMBA_STORE(b[10]);
+
+      /* output 11 */
+      CARRY_FORWARD;
+      SQRADD2(a[4], a[7]);    SQRADD2(a[5], a[6]); 
+      COMBA_STORE(b[11]);
+
+      /* output 12 */
+      CARRY_FORWARD;
+      SQRADD2(a[5], a[7]);    SQRADD(a[6], a[6]); 
+      COMBA_STORE(b[12]);
+
+      /* output 13 */
+      CARRY_FORWARD;
+      SQRADD2(a[6], a[7]); 
+      COMBA_STORE(b[13]);
+
+      /* output 14 */
+      CARRY_FORWARD;
+      SQRADD(a[7], a[7]); 
+      COMBA_STORE(b[14]);
+      COMBA_STORE2(b[15]);
+      COMBA_FINI;
+
+      B->used = 16;
+      B->sign = FP_ZPOS;
+      memcpy(B->dp, b, 16 * sizeof(fp_digit));
+      fp_clamp(B);
+      break;
+
+   case 9:
+      a = A->dp;
+      COMBA_START; 
+
+      /* clear carries */
+      CLEAR_CARRY;
+
+      /* output 0 */
+      SQRADD(a[0],a[0]);
+      COMBA_STORE(b[0]);
+
+      /* output 1 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[1]); 
+      COMBA_STORE(b[1]);
+
+      /* output 2 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[2]);    SQRADD(a[1], a[1]); 
+      COMBA_STORE(b[2]);
+
+      /* output 3 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[3]);    SQRADD2(a[1], a[2]); 
+      COMBA_STORE(b[3]);
+
+      /* output 4 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[4]);    SQRADD2(a[1], a[3]);    SQRADD(a[2], a[2]); 
+      COMBA_STORE(b[4]);
+
+      /* output 5 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[5]); SQRADDAC(a[1], a[4]); SQRADDAC(a[2], a[3]); SQRADDDB; 
+      COMBA_STORE(b[5]);
+
+      /* output 6 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[6]); SQRADDAC(a[1], a[5]); SQRADDAC(a[2], a[4]); SQRADDDB; SQRADD(a[3], a[3]); 
+      COMBA_STORE(b[6]);
+
+      /* output 7 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[7]); SQRADDAC(a[1], a[6]); SQRADDAC(a[2], a[5]); SQRADDAC(a[3], a[4]); SQRADDDB; 
+      COMBA_STORE(b[7]);
+
+      /* output 8 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[8]); SQRADDAC(a[1], a[7]); SQRADDAC(a[2], a[6]); SQRADDAC(a[3], a[5]); SQRADDDB; SQRADD(a[4], a[4]); 
+      COMBA_STORE(b[8]);
+
+      /* output 9 */
+      CARRY_FORWARD;
+   SQRADDSC(a[1], a[8]); SQRADDAC(a[2], a[7]); SQRADDAC(a[3], a[6]); SQRADDAC(a[4], a[5]); SQRADDDB; 
+      COMBA_STORE(b[9]);
+
+      /* output 10 */
+      CARRY_FORWARD;
+   SQRADDSC(a[2], a[8]); SQRADDAC(a[3], a[7]); SQRADDAC(a[4], a[6]); SQRADDDB; SQRADD(a[5], a[5]); 
+      COMBA_STORE(b[10]);
+
+      /* output 11 */
+      CARRY_FORWARD;
+   SQRADDSC(a[3], a[8]); SQRADDAC(a[4], a[7]); SQRADDAC(a[5], a[6]); SQRADDDB; 
+      COMBA_STORE(b[11]);
+
+      /* output 12 */
+      CARRY_FORWARD;
+      SQRADD2(a[4], a[8]);    SQRADD2(a[5], a[7]);    SQRADD(a[6], a[6]); 
+      COMBA_STORE(b[12]);
+
+      /* output 13 */
+      CARRY_FORWARD;
+      SQRADD2(a[5], a[8]);    SQRADD2(a[6], a[7]); 
+      COMBA_STORE(b[13]);
+
+      /* output 14 */
+      CARRY_FORWARD;
+      SQRADD2(a[6], a[8]);    SQRADD(a[7], a[7]); 
+      COMBA_STORE(b[14]);
+
+      /* output 15 */
+      CARRY_FORWARD;
+      SQRADD2(a[7], a[8]); 
+      COMBA_STORE(b[15]);
+
+      /* output 16 */
+      CARRY_FORWARD;
+      SQRADD(a[8], a[8]); 
+      COMBA_STORE(b[16]);
+      COMBA_STORE2(b[17]);
+      COMBA_FINI;
+
+      B->used = 18;
+      B->sign = FP_ZPOS;
+      memcpy(B->dp, b, 18 * sizeof(fp_digit));
+      fp_clamp(B);
+      break;
+
+   case 10:
+      a = A->dp;
+      COMBA_START; 
+
+      /* clear carries */
+      CLEAR_CARRY;
+
+      /* output 0 */
+      SQRADD(a[0],a[0]);
+      COMBA_STORE(b[0]);
+
+      /* output 1 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[1]); 
+      COMBA_STORE(b[1]);
+
+      /* output 2 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[2]);    SQRADD(a[1], a[1]); 
+      COMBA_STORE(b[2]);
+
+      /* output 3 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[3]);    SQRADD2(a[1], a[2]); 
+      COMBA_STORE(b[3]);
+
+      /* output 4 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[4]);    SQRADD2(a[1], a[3]);    SQRADD(a[2], a[2]); 
+      COMBA_STORE(b[4]);
+
+      /* output 5 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[5]); SQRADDAC(a[1], a[4]); SQRADDAC(a[2], a[3]); SQRADDDB; 
+      COMBA_STORE(b[5]);
+
+      /* output 6 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[6]); SQRADDAC(a[1], a[5]); SQRADDAC(a[2], a[4]); SQRADDDB; SQRADD(a[3], a[3]); 
+      COMBA_STORE(b[6]);
+
+      /* output 7 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[7]); SQRADDAC(a[1], a[6]); SQRADDAC(a[2], a[5]); SQRADDAC(a[3], a[4]); SQRADDDB; 
+      COMBA_STORE(b[7]);
+
+      /* output 8 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[8]); SQRADDAC(a[1], a[7]); SQRADDAC(a[2], a[6]); SQRADDAC(a[3], a[5]); SQRADDDB; SQRADD(a[4], a[4]); 
+      COMBA_STORE(b[8]);
+
+      /* output 9 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[9]); SQRADDAC(a[1], a[8]); SQRADDAC(a[2], a[7]); SQRADDAC(a[3], a[6]); SQRADDAC(a[4], a[5]); SQRADDDB; 
+      COMBA_STORE(b[9]);
+
+      /* output 10 */
+      CARRY_FORWARD;
+   SQRADDSC(a[1], a[9]); SQRADDAC(a[2], a[8]); SQRADDAC(a[3], a[7]); SQRADDAC(a[4], a[6]); SQRADDDB; SQRADD(a[5], a[5]); 
+      COMBA_STORE(b[10]);
+
+      /* output 11 */
+      CARRY_FORWARD;
+   SQRADDSC(a[2], a[9]); SQRADDAC(a[3], a[8]); SQRADDAC(a[4], a[7]); SQRADDAC(a[5], a[6]); SQRADDDB; 
+      COMBA_STORE(b[11]);
+
+      /* output 12 */
+      CARRY_FORWARD;
+   SQRADDSC(a[3], a[9]); SQRADDAC(a[4], a[8]); SQRADDAC(a[5], a[7]); SQRADDDB; SQRADD(a[6], a[6]); 
+      COMBA_STORE(b[12]);
+
+      /* output 13 */
+      CARRY_FORWARD;
+   SQRADDSC(a[4], a[9]); SQRADDAC(a[5], a[8]); SQRADDAC(a[6], a[7]); SQRADDDB; 
+      COMBA_STORE(b[13]);
+
+      /* output 14 */
+      CARRY_FORWARD;
+      SQRADD2(a[5], a[9]);    SQRADD2(a[6], a[8]);    SQRADD(a[7], a[7]); 
+      COMBA_STORE(b[14]);
+
+      /* output 15 */
+      CARRY_FORWARD;
+      SQRADD2(a[6], a[9]);    SQRADD2(a[7], a[8]); 
+      COMBA_STORE(b[15]);
+
+      /* output 16 */
+      CARRY_FORWARD;
+      SQRADD2(a[7], a[9]);    SQRADD(a[8], a[8]); 
+      COMBA_STORE(b[16]);
+
+      /* output 17 */
+      CARRY_FORWARD;
+      SQRADD2(a[8], a[9]); 
+      COMBA_STORE(b[17]);
+
+      /* output 18 */
+      CARRY_FORWARD;
+      SQRADD(a[9], a[9]); 
+      COMBA_STORE(b[18]);
+      COMBA_STORE2(b[19]);
+      COMBA_FINI;
+
+      B->used = 20;
+      B->sign = FP_ZPOS;
+      memcpy(B->dp, b, 20 * sizeof(fp_digit));
+      fp_clamp(B);
+      break;
+
+   case 11:
+      a = A->dp;
+      COMBA_START; 
+
+      /* clear carries */
+      CLEAR_CARRY;
+
+      /* output 0 */
+      SQRADD(a[0],a[0]);
+      COMBA_STORE(b[0]);
+
+      /* output 1 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[1]); 
+      COMBA_STORE(b[1]);
+
+      /* output 2 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[2]);    SQRADD(a[1], a[1]); 
+      COMBA_STORE(b[2]);
+
+      /* output 3 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[3]);    SQRADD2(a[1], a[2]); 
+      COMBA_STORE(b[3]);
+
+      /* output 4 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[4]);    SQRADD2(a[1], a[3]);    SQRADD(a[2], a[2]); 
+      COMBA_STORE(b[4]);
+
+      /* output 5 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[5]); SQRADDAC(a[1], a[4]); SQRADDAC(a[2], a[3]); SQRADDDB; 
+      COMBA_STORE(b[5]);
+
+      /* output 6 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[6]); SQRADDAC(a[1], a[5]); SQRADDAC(a[2], a[4]); SQRADDDB; SQRADD(a[3], a[3]); 
+      COMBA_STORE(b[6]);
+
+      /* output 7 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[7]); SQRADDAC(a[1], a[6]); SQRADDAC(a[2], a[5]); SQRADDAC(a[3], a[4]); SQRADDDB; 
+      COMBA_STORE(b[7]);
+
+      /* output 8 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[8]); SQRADDAC(a[1], a[7]); SQRADDAC(a[2], a[6]); SQRADDAC(a[3], a[5]); SQRADDDB; SQRADD(a[4], a[4]); 
+      COMBA_STORE(b[8]);
+
+      /* output 9 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[9]); SQRADDAC(a[1], a[8]); SQRADDAC(a[2], a[7]); SQRADDAC(a[3], a[6]); SQRADDAC(a[4], a[5]); SQRADDDB; 
+      COMBA_STORE(b[9]);
+
+      /* output 10 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[10]); SQRADDAC(a[1], a[9]); SQRADDAC(a[2], a[8]); SQRADDAC(a[3], a[7]); SQRADDAC(a[4], a[6]); SQRADDDB; SQRADD(a[5], a[5]); 
+      COMBA_STORE(b[10]);
+
+      /* output 11 */
+      CARRY_FORWARD;
+   SQRADDSC(a[1], a[10]); SQRADDAC(a[2], a[9]); SQRADDAC(a[3], a[8]); SQRADDAC(a[4], a[7]); SQRADDAC(a[5], a[6]); SQRADDDB; 
+      COMBA_STORE(b[11]);
+
+      /* output 12 */
+      CARRY_FORWARD;
+   SQRADDSC(a[2], a[10]); SQRADDAC(a[3], a[9]); SQRADDAC(a[4], a[8]); SQRADDAC(a[5], a[7]); SQRADDDB; SQRADD(a[6], a[6]); 
+      COMBA_STORE(b[12]);
+
+      /* output 13 */
+      CARRY_FORWARD;
+   SQRADDSC(a[3], a[10]); SQRADDAC(a[4], a[9]); SQRADDAC(a[5], a[8]); SQRADDAC(a[6], a[7]); SQRADDDB; 
+      COMBA_STORE(b[13]);
+
+      /* output 14 */
+      CARRY_FORWARD;
+   SQRADDSC(a[4], a[10]); SQRADDAC(a[5], a[9]); SQRADDAC(a[6], a[8]); SQRADDDB; SQRADD(a[7], a[7]); 
+      COMBA_STORE(b[14]);
+
+      /* output 15 */
+      CARRY_FORWARD;
+   SQRADDSC(a[5], a[10]); SQRADDAC(a[6], a[9]); SQRADDAC(a[7], a[8]); SQRADDDB; 
+      COMBA_STORE(b[15]);
+
+      /* output 16 */
+      CARRY_FORWARD;
+      SQRADD2(a[6], a[10]);    SQRADD2(a[7], a[9]);    SQRADD(a[8], a[8]); 
+      COMBA_STORE(b[16]);
+
+      /* output 17 */
+      CARRY_FORWARD;
+      SQRADD2(a[7], a[10]);    SQRADD2(a[8], a[9]); 
+      COMBA_STORE(b[17]);
+
+      /* output 18 */
+      CARRY_FORWARD;
+      SQRADD2(a[8], a[10]);    SQRADD(a[9], a[9]); 
+      COMBA_STORE(b[18]);
+
+      /* output 19 */
+      CARRY_FORWARD;
+      SQRADD2(a[9], a[10]); 
+      COMBA_STORE(b[19]);
+
+      /* output 20 */
+      CARRY_FORWARD;
+      SQRADD(a[10], a[10]); 
+      COMBA_STORE(b[20]);
+      COMBA_STORE2(b[21]);
+      COMBA_FINI;
+
+      B->used = 22;
+      B->sign = FP_ZPOS;
+      memcpy(B->dp, b, 22 * sizeof(fp_digit));
+      fp_clamp(B);
+      break;
+
+   case 12:
+      a = A->dp;
+      COMBA_START; 
+
+      /* clear carries */
+      CLEAR_CARRY;
+
+      /* output 0 */
+      SQRADD(a[0],a[0]);
+      COMBA_STORE(b[0]);
+
+      /* output 1 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[1]); 
+      COMBA_STORE(b[1]);
+
+      /* output 2 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[2]);    SQRADD(a[1], a[1]); 
+      COMBA_STORE(b[2]);
+
+      /* output 3 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[3]);    SQRADD2(a[1], a[2]); 
+      COMBA_STORE(b[3]);
+
+      /* output 4 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[4]);    SQRADD2(a[1], a[3]);    SQRADD(a[2], a[2]); 
+      COMBA_STORE(b[4]);
+
+      /* output 5 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[5]); SQRADDAC(a[1], a[4]); SQRADDAC(a[2], a[3]); SQRADDDB; 
+      COMBA_STORE(b[5]);
+
+      /* output 6 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[6]); SQRADDAC(a[1], a[5]); SQRADDAC(a[2], a[4]); SQRADDDB; SQRADD(a[3], a[3]); 
+      COMBA_STORE(b[6]);
+
+      /* output 7 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[7]); SQRADDAC(a[1], a[6]); SQRADDAC(a[2], a[5]); SQRADDAC(a[3], a[4]); SQRADDDB; 
+      COMBA_STORE(b[7]);
+
+      /* output 8 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[8]); SQRADDAC(a[1], a[7]); SQRADDAC(a[2], a[6]); SQRADDAC(a[3], a[5]); SQRADDDB; SQRADD(a[4], a[4]); 
+      COMBA_STORE(b[8]);
+
+      /* output 9 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[9]); SQRADDAC(a[1], a[8]); SQRADDAC(a[2], a[7]); SQRADDAC(a[3], a[6]); SQRADDAC(a[4], a[5]); SQRADDDB; 
+      COMBA_STORE(b[9]);
+
+      /* output 10 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[10]); SQRADDAC(a[1], a[9]); SQRADDAC(a[2], a[8]); SQRADDAC(a[3], a[7]); SQRADDAC(a[4], a[6]); SQRADDDB; SQRADD(a[5], a[5]); 
+      COMBA_STORE(b[10]);
+
+      /* output 11 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[11]); SQRADDAC(a[1], a[10]); SQRADDAC(a[2], a[9]); SQRADDAC(a[3], a[8]); SQRADDAC(a[4], a[7]); SQRADDAC(a[5], a[6]); SQRADDDB; 
+      COMBA_STORE(b[11]);
+
+      /* output 12 */
+      CARRY_FORWARD;
+   SQRADDSC(a[1], a[11]); SQRADDAC(a[2], a[10]); SQRADDAC(a[3], a[9]); SQRADDAC(a[4], a[8]); SQRADDAC(a[5], a[7]); SQRADDDB; SQRADD(a[6], a[6]); 
+      COMBA_STORE(b[12]);
+
+      /* output 13 */
+      CARRY_FORWARD;
+   SQRADDSC(a[2], a[11]); SQRADDAC(a[3], a[10]); SQRADDAC(a[4], a[9]); SQRADDAC(a[5], a[8]); SQRADDAC(a[6], a[7]); SQRADDDB; 
+      COMBA_STORE(b[13]);
+
+      /* output 14 */
+      CARRY_FORWARD;
+   SQRADDSC(a[3], a[11]); SQRADDAC(a[4], a[10]); SQRADDAC(a[5], a[9]); SQRADDAC(a[6], a[8]); SQRADDDB; SQRADD(a[7], a[7]); 
+      COMBA_STORE(b[14]);
+
+      /* output 15 */
+      CARRY_FORWARD;
+   SQRADDSC(a[4], a[11]); SQRADDAC(a[5], a[10]); SQRADDAC(a[6], a[9]); SQRADDAC(a[7], a[8]); SQRADDDB; 
+      COMBA_STORE(b[15]);
+
+      /* output 16 */
+      CARRY_FORWARD;
+   SQRADDSC(a[5], a[11]); SQRADDAC(a[6], a[10]); SQRADDAC(a[7], a[9]); SQRADDDB; SQRADD(a[8], a[8]); 
+      COMBA_STORE(b[16]);
+
+      /* output 17 */
+      CARRY_FORWARD;
+   SQRADDSC(a[6], a[11]); SQRADDAC(a[7], a[10]); SQRADDAC(a[8], a[9]); SQRADDDB; 
+      COMBA_STORE(b[17]);
+
+      /* output 18 */
+      CARRY_FORWARD;
+      SQRADD2(a[7], a[11]);    SQRADD2(a[8], a[10]);    SQRADD(a[9], a[9]); 
+      COMBA_STORE(b[18]);
+
+      /* output 19 */
+      CARRY_FORWARD;
+      SQRADD2(a[8], a[11]);    SQRADD2(a[9], a[10]); 
+      COMBA_STORE(b[19]);
+
+      /* output 20 */
+      CARRY_FORWARD;
+      SQRADD2(a[9], a[11]);    SQRADD(a[10], a[10]); 
+      COMBA_STORE(b[20]);
+
+      /* output 21 */
+      CARRY_FORWARD;
+      SQRADD2(a[10], a[11]); 
+      COMBA_STORE(b[21]);
+
+      /* output 22 */
+      CARRY_FORWARD;
+      SQRADD(a[11], a[11]); 
+      COMBA_STORE(b[22]);
+      COMBA_STORE2(b[23]);
+      COMBA_FINI;
+
+      B->used = 24;
+      B->sign = FP_ZPOS;
+      memcpy(B->dp, b, 24 * sizeof(fp_digit));
+      fp_clamp(B);
+      break;
+
+   case 13:
+      a = A->dp;
+      COMBA_START; 
+
+      /* clear carries */
+      CLEAR_CARRY;
+
+      /* output 0 */
+      SQRADD(a[0],a[0]);
+      COMBA_STORE(b[0]);
+
+      /* output 1 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[1]); 
+      COMBA_STORE(b[1]);
+
+      /* output 2 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[2]);    SQRADD(a[1], a[1]); 
+      COMBA_STORE(b[2]);
+
+      /* output 3 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[3]);    SQRADD2(a[1], a[2]); 
+      COMBA_STORE(b[3]);
+
+      /* output 4 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[4]);    SQRADD2(a[1], a[3]);    SQRADD(a[2], a[2]); 
+      COMBA_STORE(b[4]);
+
+      /* output 5 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[5]); SQRADDAC(a[1], a[4]); SQRADDAC(a[2], a[3]); SQRADDDB; 
+      COMBA_STORE(b[5]);
+
+      /* output 6 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[6]); SQRADDAC(a[1], a[5]); SQRADDAC(a[2], a[4]); SQRADDDB; SQRADD(a[3], a[3]); 
+      COMBA_STORE(b[6]);
+
+      /* output 7 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[7]); SQRADDAC(a[1], a[6]); SQRADDAC(a[2], a[5]); SQRADDAC(a[3], a[4]); SQRADDDB; 
+      COMBA_STORE(b[7]);
+
+      /* output 8 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[8]); SQRADDAC(a[1], a[7]); SQRADDAC(a[2], a[6]); SQRADDAC(a[3], a[5]); SQRADDDB; SQRADD(a[4], a[4]); 
+      COMBA_STORE(b[8]);
+
+      /* output 9 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[9]); SQRADDAC(a[1], a[8]); SQRADDAC(a[2], a[7]); SQRADDAC(a[3], a[6]); SQRADDAC(a[4], a[5]); SQRADDDB; 
+      COMBA_STORE(b[9]);
+
+      /* output 10 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[10]); SQRADDAC(a[1], a[9]); SQRADDAC(a[2], a[8]); SQRADDAC(a[3], a[7]); SQRADDAC(a[4], a[6]); SQRADDDB; SQRADD(a[5], a[5]); 
+      COMBA_STORE(b[10]);
+
+      /* output 11 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[11]); SQRADDAC(a[1], a[10]); SQRADDAC(a[2], a[9]); SQRADDAC(a[3], a[8]); SQRADDAC(a[4], a[7]); SQRADDAC(a[5], a[6]); SQRADDDB; 
+      COMBA_STORE(b[11]);
+
+      /* output 12 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[12]); SQRADDAC(a[1], a[11]); SQRADDAC(a[2], a[10]); SQRADDAC(a[3], a[9]); SQRADDAC(a[4], a[8]); SQRADDAC(a[5], a[7]); SQRADDDB; SQRADD(a[6], a[6]); 
+      COMBA_STORE(b[12]);
+
+      /* output 13 */
+      CARRY_FORWARD;
+   SQRADDSC(a[1], a[12]); SQRADDAC(a[2], a[11]); SQRADDAC(a[3], a[10]); SQRADDAC(a[4], a[9]); SQRADDAC(a[5], a[8]); SQRADDAC(a[6], a[7]); SQRADDDB; 
+      COMBA_STORE(b[13]);
+
+      /* output 14 */
+      CARRY_FORWARD;
+   SQRADDSC(a[2], a[12]); SQRADDAC(a[3], a[11]); SQRADDAC(a[4], a[10]); SQRADDAC(a[5], a[9]); SQRADDAC(a[6], a[8]); SQRADDDB; SQRADD(a[7], a[7]); 
+      COMBA_STORE(b[14]);
+
+      /* output 15 */
+      CARRY_FORWARD;
+   SQRADDSC(a[3], a[12]); SQRADDAC(a[4], a[11]); SQRADDAC(a[5], a[10]); SQRADDAC(a[6], a[9]); SQRADDAC(a[7], a[8]); SQRADDDB; 
+      COMBA_STORE(b[15]);
+
+      /* output 16 */
+      CARRY_FORWARD;
+   SQRADDSC(a[4], a[12]); SQRADDAC(a[5], a[11]); SQRADDAC(a[6], a[10]); SQRADDAC(a[7], a[9]); SQRADDDB; SQRADD(a[8], a[8]); 
+      COMBA_STORE(b[16]);
+
+      /* output 17 */
+      CARRY_FORWARD;
+   SQRADDSC(a[5], a[12]); SQRADDAC(a[6], a[11]); SQRADDAC(a[7], a[10]); SQRADDAC(a[8], a[9]); SQRADDDB; 
+      COMBA_STORE(b[17]);
+
+      /* output 18 */
+      CARRY_FORWARD;
+   SQRADDSC(a[6], a[12]); SQRADDAC(a[7], a[11]); SQRADDAC(a[8], a[10]); SQRADDDB; SQRADD(a[9], a[9]); 
+      COMBA_STORE(b[18]);
+
+      /* output 19 */
+      CARRY_FORWARD;
+   SQRADDSC(a[7], a[12]); SQRADDAC(a[8], a[11]); SQRADDAC(a[9], a[10]); SQRADDDB; 
+      COMBA_STORE(b[19]);
+
+      /* output 20 */
+      CARRY_FORWARD;
+      SQRADD2(a[8], a[12]);    SQRADD2(a[9], a[11]);    SQRADD(a[10], a[10]); 
+      COMBA_STORE(b[20]);
+
+      /* output 21 */
+      CARRY_FORWARD;
+      SQRADD2(a[9], a[12]);    SQRADD2(a[10], a[11]); 
+      COMBA_STORE(b[21]);
+
+      /* output 22 */
+      CARRY_FORWARD;
+      SQRADD2(a[10], a[12]);    SQRADD(a[11], a[11]); 
+      COMBA_STORE(b[22]);
+
+      /* output 23 */
+      CARRY_FORWARD;
+      SQRADD2(a[11], a[12]); 
+      COMBA_STORE(b[23]);
+
+      /* output 24 */
+      CARRY_FORWARD;
+      SQRADD(a[12], a[12]); 
+      COMBA_STORE(b[24]);
+      COMBA_STORE2(b[25]);
+      COMBA_FINI;
+
+      B->used = 26;
+      B->sign = FP_ZPOS;
+      memcpy(B->dp, b, 26 * sizeof(fp_digit));
+      fp_clamp(B);
+      break;
+
+   case 14:
+      a = A->dp;
+      COMBA_START; 
+
+      /* clear carries */
+      CLEAR_CARRY;
+
+      /* output 0 */
+      SQRADD(a[0],a[0]);
+      COMBA_STORE(b[0]);
+
+      /* output 1 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[1]); 
+      COMBA_STORE(b[1]);
+
+      /* output 2 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[2]);    SQRADD(a[1], a[1]); 
+      COMBA_STORE(b[2]);
+
+      /* output 3 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[3]);    SQRADD2(a[1], a[2]); 
+      COMBA_STORE(b[3]);
+
+      /* output 4 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[4]);    SQRADD2(a[1], a[3]);    SQRADD(a[2], a[2]); 
+      COMBA_STORE(b[4]);
+
+      /* output 5 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[5]); SQRADDAC(a[1], a[4]); SQRADDAC(a[2], a[3]); SQRADDDB; 
+      COMBA_STORE(b[5]);
+
+      /* output 6 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[6]); SQRADDAC(a[1], a[5]); SQRADDAC(a[2], a[4]); SQRADDDB; SQRADD(a[3], a[3]); 
+      COMBA_STORE(b[6]);
+
+      /* output 7 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[7]); SQRADDAC(a[1], a[6]); SQRADDAC(a[2], a[5]); SQRADDAC(a[3], a[4]); SQRADDDB; 
+      COMBA_STORE(b[7]);
+
+      /* output 8 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[8]); SQRADDAC(a[1], a[7]); SQRADDAC(a[2], a[6]); SQRADDAC(a[3], a[5]); SQRADDDB; SQRADD(a[4], a[4]); 
+      COMBA_STORE(b[8]);
+
+      /* output 9 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[9]); SQRADDAC(a[1], a[8]); SQRADDAC(a[2], a[7]); SQRADDAC(a[3], a[6]); SQRADDAC(a[4], a[5]); SQRADDDB; 
+      COMBA_STORE(b[9]);
+
+      /* output 10 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[10]); SQRADDAC(a[1], a[9]); SQRADDAC(a[2], a[8]); SQRADDAC(a[3], a[7]); SQRADDAC(a[4], a[6]); SQRADDDB; SQRADD(a[5], a[5]); 
+      COMBA_STORE(b[10]);
+
+      /* output 11 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[11]); SQRADDAC(a[1], a[10]); SQRADDAC(a[2], a[9]); SQRADDAC(a[3], a[8]); SQRADDAC(a[4], a[7]); SQRADDAC(a[5], a[6]); SQRADDDB; 
+      COMBA_STORE(b[11]);
+
+      /* output 12 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[12]); SQRADDAC(a[1], a[11]); SQRADDAC(a[2], a[10]); SQRADDAC(a[3], a[9]); SQRADDAC(a[4], a[8]); SQRADDAC(a[5], a[7]); SQRADDDB; SQRADD(a[6], a[6]); 
+      COMBA_STORE(b[12]);
+
+      /* output 13 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[13]); SQRADDAC(a[1], a[12]); SQRADDAC(a[2], a[11]); SQRADDAC(a[3], a[10]); SQRADDAC(a[4], a[9]); SQRADDAC(a[5], a[8]); SQRADDAC(a[6], a[7]); SQRADDDB; 
+      COMBA_STORE(b[13]);
+
+      /* output 14 */
+      CARRY_FORWARD;
+   SQRADDSC(a[1], a[13]); SQRADDAC(a[2], a[12]); SQRADDAC(a[3], a[11]); SQRADDAC(a[4], a[10]); SQRADDAC(a[5], a[9]); SQRADDAC(a[6], a[8]); SQRADDDB; SQRADD(a[7], a[7]); 
+      COMBA_STORE(b[14]);
+
+      /* output 15 */
+      CARRY_FORWARD;
+   SQRADDSC(a[2], a[13]); SQRADDAC(a[3], a[12]); SQRADDAC(a[4], a[11]); SQRADDAC(a[5], a[10]); SQRADDAC(a[6], a[9]); SQRADDAC(a[7], a[8]); SQRADDDB; 
+      COMBA_STORE(b[15]);
+
+      /* output 16 */
+      CARRY_FORWARD;
+   SQRADDSC(a[3], a[13]); SQRADDAC(a[4], a[12]); SQRADDAC(a[5], a[11]); SQRADDAC(a[6], a[10]); SQRADDAC(a[7], a[9]); SQRADDDB; SQRADD(a[8], a[8]); 
+      COMBA_STORE(b[16]);
+
+      /* output 17 */
+      CARRY_FORWARD;
+   SQRADDSC(a[4], a[13]); SQRADDAC(a[5], a[12]); SQRADDAC(a[6], a[11]); SQRADDAC(a[7], a[10]); SQRADDAC(a[8], a[9]); SQRADDDB; 
+      COMBA_STORE(b[17]);
+
+      /* output 18 */
+      CARRY_FORWARD;
+   SQRADDSC(a[5], a[13]); SQRADDAC(a[6], a[12]); SQRADDAC(a[7], a[11]); SQRADDAC(a[8], a[10]); SQRADDDB; SQRADD(a[9], a[9]); 
+      COMBA_STORE(b[18]);
+
+      /* output 19 */
+      CARRY_FORWARD;
+   SQRADDSC(a[6], a[13]); SQRADDAC(a[7], a[12]); SQRADDAC(a[8], a[11]); SQRADDAC(a[9], a[10]); SQRADDDB; 
+      COMBA_STORE(b[19]);
+
+      /* output 20 */
+      CARRY_FORWARD;
+   SQRADDSC(a[7], a[13]); SQRADDAC(a[8], a[12]); SQRADDAC(a[9], a[11]); SQRADDDB; SQRADD(a[10], a[10]); 
+      COMBA_STORE(b[20]);
+
+      /* output 21 */
+      CARRY_FORWARD;
+   SQRADDSC(a[8], a[13]); SQRADDAC(a[9], a[12]); SQRADDAC(a[10], a[11]); SQRADDDB; 
+      COMBA_STORE(b[21]);
+
+      /* output 22 */
+      CARRY_FORWARD;
+      SQRADD2(a[9], a[13]);    SQRADD2(a[10], a[12]);    SQRADD(a[11], a[11]); 
+      COMBA_STORE(b[22]);
+
+      /* output 23 */
+      CARRY_FORWARD;
+      SQRADD2(a[10], a[13]);    SQRADD2(a[11], a[12]); 
+      COMBA_STORE(b[23]);
+
+      /* output 24 */
+      CARRY_FORWARD;
+      SQRADD2(a[11], a[13]);    SQRADD(a[12], a[12]); 
+      COMBA_STORE(b[24]);
+
+      /* output 25 */
+      CARRY_FORWARD;
+      SQRADD2(a[12], a[13]); 
+      COMBA_STORE(b[25]);
+
+      /* output 26 */
+      CARRY_FORWARD;
+      SQRADD(a[13], a[13]); 
+      COMBA_STORE(b[26]);
+      COMBA_STORE2(b[27]);
+      COMBA_FINI;
+
+      B->used = 28;
+      B->sign = FP_ZPOS;
+      memcpy(B->dp, b, 28 * sizeof(fp_digit));
+      fp_clamp(B);
+      break;
+
+   case 15:
+      a = A->dp;
+      COMBA_START; 
+
+      /* clear carries */
+      CLEAR_CARRY;
+
+      /* output 0 */
+      SQRADD(a[0],a[0]);
+      COMBA_STORE(b[0]);
+
+      /* output 1 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[1]); 
+      COMBA_STORE(b[1]);
+
+      /* output 2 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[2]);    SQRADD(a[1], a[1]); 
+      COMBA_STORE(b[2]);
+
+      /* output 3 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[3]);    SQRADD2(a[1], a[2]); 
+      COMBA_STORE(b[3]);
+
+      /* output 4 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[4]);    SQRADD2(a[1], a[3]);    SQRADD(a[2], a[2]); 
+      COMBA_STORE(b[4]);
+
+      /* output 5 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[5]); SQRADDAC(a[1], a[4]); SQRADDAC(a[2], a[3]); SQRADDDB; 
+      COMBA_STORE(b[5]);
+
+      /* output 6 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[6]); SQRADDAC(a[1], a[5]); SQRADDAC(a[2], a[4]); SQRADDDB; SQRADD(a[3], a[3]); 
+      COMBA_STORE(b[6]);
+
+      /* output 7 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[7]); SQRADDAC(a[1], a[6]); SQRADDAC(a[2], a[5]); SQRADDAC(a[3], a[4]); SQRADDDB; 
+      COMBA_STORE(b[7]);
+
+      /* output 8 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[8]); SQRADDAC(a[1], a[7]); SQRADDAC(a[2], a[6]); SQRADDAC(a[3], a[5]); SQRADDDB; SQRADD(a[4], a[4]); 
+      COMBA_STORE(b[8]);
+
+      /* output 9 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[9]); SQRADDAC(a[1], a[8]); SQRADDAC(a[2], a[7]); SQRADDAC(a[3], a[6]); SQRADDAC(a[4], a[5]); SQRADDDB; 
+      COMBA_STORE(b[9]);
+
+      /* output 10 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[10]); SQRADDAC(a[1], a[9]); SQRADDAC(a[2], a[8]); SQRADDAC(a[3], a[7]); SQRADDAC(a[4], a[6]); SQRADDDB; SQRADD(a[5], a[5]); 
+      COMBA_STORE(b[10]);
+
+      /* output 11 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[11]); SQRADDAC(a[1], a[10]); SQRADDAC(a[2], a[9]); SQRADDAC(a[3], a[8]); SQRADDAC(a[4], a[7]); SQRADDAC(a[5], a[6]); SQRADDDB; 
+      COMBA_STORE(b[11]);
+
+      /* output 12 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[12]); SQRADDAC(a[1], a[11]); SQRADDAC(a[2], a[10]); SQRADDAC(a[3], a[9]); SQRADDAC(a[4], a[8]); SQRADDAC(a[5], a[7]); SQRADDDB; SQRADD(a[6], a[6]); 
+      COMBA_STORE(b[12]);
+
+      /* output 13 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[13]); SQRADDAC(a[1], a[12]); SQRADDAC(a[2], a[11]); SQRADDAC(a[3], a[10]); SQRADDAC(a[4], a[9]); SQRADDAC(a[5], a[8]); SQRADDAC(a[6], a[7]); SQRADDDB; 
+      COMBA_STORE(b[13]);
+
+      /* output 14 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[14]); SQRADDAC(a[1], a[13]); SQRADDAC(a[2], a[12]); SQRADDAC(a[3], a[11]); SQRADDAC(a[4], a[10]); SQRADDAC(a[5], a[9]); SQRADDAC(a[6], a[8]); SQRADDDB; SQRADD(a[7], a[7]); 
+      COMBA_STORE(b[14]);
+
+      /* output 15 */
+      CARRY_FORWARD;
+   SQRADDSC(a[1], a[14]); SQRADDAC(a[2], a[13]); SQRADDAC(a[3], a[12]); SQRADDAC(a[4], a[11]); SQRADDAC(a[5], a[10]); SQRADDAC(a[6], a[9]); SQRADDAC(a[7], a[8]); SQRADDDB; 
+      COMBA_STORE(b[15]);
+
+      /* output 16 */
+      CARRY_FORWARD;
+   SQRADDSC(a[2], a[14]); SQRADDAC(a[3], a[13]); SQRADDAC(a[4], a[12]); SQRADDAC(a[5], a[11]); SQRADDAC(a[6], a[10]); SQRADDAC(a[7], a[9]); SQRADDDB; SQRADD(a[8], a[8]); 
+      COMBA_STORE(b[16]);
+
+      /* output 17 */
+      CARRY_FORWARD;
+   SQRADDSC(a[3], a[14]); SQRADDAC(a[4], a[13]); SQRADDAC(a[5], a[12]); SQRADDAC(a[6], a[11]); SQRADDAC(a[7], a[10]); SQRADDAC(a[8], a[9]); SQRADDDB; 
+      COMBA_STORE(b[17]);
+
+      /* output 18 */
+      CARRY_FORWARD;
+   SQRADDSC(a[4], a[14]); SQRADDAC(a[5], a[13]); SQRADDAC(a[6], a[12]); SQRADDAC(a[7], a[11]); SQRADDAC(a[8], a[10]); SQRADDDB; SQRADD(a[9], a[9]); 
+      COMBA_STORE(b[18]);
+
+      /* output 19 */
+      CARRY_FORWARD;
+   SQRADDSC(a[5], a[14]); SQRADDAC(a[6], a[13]); SQRADDAC(a[7], a[12]); SQRADDAC(a[8], a[11]); SQRADDAC(a[9], a[10]); SQRADDDB; 
+      COMBA_STORE(b[19]);
+
+      /* output 20 */
+      CARRY_FORWARD;
+   SQRADDSC(a[6], a[14]); SQRADDAC(a[7], a[13]); SQRADDAC(a[8], a[12]); SQRADDAC(a[9], a[11]); SQRADDDB; SQRADD(a[10], a[10]); 
+      COMBA_STORE(b[20]);
+
+      /* output 21 */
+      CARRY_FORWARD;
+   SQRADDSC(a[7], a[14]); SQRADDAC(a[8], a[13]); SQRADDAC(a[9], a[12]); SQRADDAC(a[10], a[11]); SQRADDDB; 
+      COMBA_STORE(b[21]);
+
+      /* output 22 */
+      CARRY_FORWARD;
+   SQRADDSC(a[8], a[14]); SQRADDAC(a[9], a[13]); SQRADDAC(a[10], a[12]); SQRADDDB; SQRADD(a[11], a[11]); 
+      COMBA_STORE(b[22]);
+
+      /* output 23 */
+      CARRY_FORWARD;
+   SQRADDSC(a[9], a[14]); SQRADDAC(a[10], a[13]); SQRADDAC(a[11], a[12]); SQRADDDB; 
+      COMBA_STORE(b[23]);
+
+      /* output 24 */
+      CARRY_FORWARD;
+      SQRADD2(a[10], a[14]);    SQRADD2(a[11], a[13]);    SQRADD(a[12], a[12]); 
+      COMBA_STORE(b[24]);
+
+      /* output 25 */
+      CARRY_FORWARD;
+      SQRADD2(a[11], a[14]);    SQRADD2(a[12], a[13]); 
+      COMBA_STORE(b[25]);
+
+      /* output 26 */
+      CARRY_FORWARD;
+      SQRADD2(a[12], a[14]);    SQRADD(a[13], a[13]); 
+      COMBA_STORE(b[26]);
+
+      /* output 27 */
+      CARRY_FORWARD;
+      SQRADD2(a[13], a[14]); 
+      COMBA_STORE(b[27]);
+
+      /* output 28 */
+      CARRY_FORWARD;
+      SQRADD(a[14], a[14]); 
+      COMBA_STORE(b[28]);
+      COMBA_STORE2(b[29]);
+      COMBA_FINI;
+
+      B->used = 30;
+      B->sign = FP_ZPOS;
+      memcpy(B->dp, b, 30 * sizeof(fp_digit));
+      fp_clamp(B);
+      break;
+
+   case 16:
+      a = A->dp;
+      COMBA_START; 
+
+      /* clear carries */
+      CLEAR_CARRY;
+
+      /* output 0 */
+      SQRADD(a[0],a[0]);
+      COMBA_STORE(b[0]);
+
+      /* output 1 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[1]); 
+      COMBA_STORE(b[1]);
+
+      /* output 2 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[2]);    SQRADD(a[1], a[1]); 
+      COMBA_STORE(b[2]);
+
+      /* output 3 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[3]);    SQRADD2(a[1], a[2]); 
+      COMBA_STORE(b[3]);
+
+      /* output 4 */
+      CARRY_FORWARD;
+      SQRADD2(a[0], a[4]);    SQRADD2(a[1], a[3]);    SQRADD(a[2], a[2]); 
+      COMBA_STORE(b[4]);
+
+      /* output 5 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[5]); SQRADDAC(a[1], a[4]); SQRADDAC(a[2], a[3]); SQRADDDB; 
+      COMBA_STORE(b[5]);
+
+      /* output 6 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[6]); SQRADDAC(a[1], a[5]); SQRADDAC(a[2], a[4]); SQRADDDB; SQRADD(a[3], a[3]); 
+      COMBA_STORE(b[6]);
+
+      /* output 7 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[7]); SQRADDAC(a[1], a[6]); SQRADDAC(a[2], a[5]); SQRADDAC(a[3], a[4]); SQRADDDB; 
+      COMBA_STORE(b[7]);
+
+      /* output 8 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[8]); SQRADDAC(a[1], a[7]); SQRADDAC(a[2], a[6]); SQRADDAC(a[3], a[5]); SQRADDDB; SQRADD(a[4], a[4]); 
+      COMBA_STORE(b[8]);
+
+      /* output 9 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[9]); SQRADDAC(a[1], a[8]); SQRADDAC(a[2], a[7]); SQRADDAC(a[3], a[6]); SQRADDAC(a[4], a[5]); SQRADDDB; 
+      COMBA_STORE(b[9]);
+
+      /* output 10 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[10]); SQRADDAC(a[1], a[9]); SQRADDAC(a[2], a[8]); SQRADDAC(a[3], a[7]); SQRADDAC(a[4], a[6]); SQRADDDB; SQRADD(a[5], a[5]); 
+      COMBA_STORE(b[10]);
+
+      /* output 11 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[11]); SQRADDAC(a[1], a[10]); SQRADDAC(a[2], a[9]); SQRADDAC(a[3], a[8]); SQRADDAC(a[4], a[7]); SQRADDAC(a[5], a[6]); SQRADDDB; 
+      COMBA_STORE(b[11]);
+
+      /* output 12 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[12]); SQRADDAC(a[1], a[11]); SQRADDAC(a[2], a[10]); SQRADDAC(a[3], a[9]); SQRADDAC(a[4], a[8]); SQRADDAC(a[5], a[7]); SQRADDDB; SQRADD(a[6], a[6]); 
+      COMBA_STORE(b[12]);
+
+      /* output 13 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[13]); SQRADDAC(a[1], a[12]); SQRADDAC(a[2], a[11]); SQRADDAC(a[3], a[10]); SQRADDAC(a[4], a[9]); SQRADDAC(a[5], a[8]); SQRADDAC(a[6], a[7]); SQRADDDB; 
+      COMBA_STORE(b[13]);
+
+      /* output 14 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[14]); SQRADDAC(a[1], a[13]); SQRADDAC(a[2], a[12]); SQRADDAC(a[3], a[11]); SQRADDAC(a[4], a[10]); SQRADDAC(a[5], a[9]); SQRADDAC(a[6], a[8]); SQRADDDB; SQRADD(a[7], a[7]); 
+      COMBA_STORE(b[14]);
+
+      /* output 15 */
+      CARRY_FORWARD;
+   SQRADDSC(a[0], a[15]); SQRADDAC(a[1], a[14]); SQRADDAC(a[2], a[13]); SQRADDAC(a[3], a[12]); SQRADDAC(a[4], a[11]); SQRADDAC(a[5], a[10]); SQRADDAC(a[6], a[9]); SQRADDAC(a[7], a[8]); SQRADDDB; 
+      COMBA_STORE(b[15]);
+
+      /* output 16 */
+      CARRY_FORWARD;
+   SQRADDSC(a[1], a[15]); SQRADDAC(a[2], a[14]); SQRADDAC(a[3], a[13]); SQRADDAC(a[4], a[12]); SQRADDAC(a[5], a[11]); SQRADDAC(a[6], a[10]); SQRADDAC(a[7], a[9]); SQRADDDB; SQRADD(a[8], a[8]); 
+      COMBA_STORE(b[16]);
+
+      /* output 17 */
+      CARRY_FORWARD;
+   SQRADDSC(a[2], a[15]); SQRADDAC(a[3], a[14]); SQRADDAC(a[4], a[13]); SQRADDAC(a[5], a[12]); SQRADDAC(a[6], a[11]); SQRADDAC(a[7], a[10]); SQRADDAC(a[8], a[9]); SQRADDDB; 
+      COMBA_STORE(b[17]);
+
+      /* output 18 */
+      CARRY_FORWARD;
+   SQRADDSC(a[3], a[15]); SQRADDAC(a[4], a[14]); SQRADDAC(a[5], a[13]); SQRADDAC(a[6], a[12]); SQRADDAC(a[7], a[11]); SQRADDAC(a[8], a[10]); SQRADDDB; SQRADD(a[9], a[9]); 
+      COMBA_STORE(b[18]);
+
+      /* output 19 */
+      CARRY_FORWARD;
+   SQRADDSC(a[4], a[15]); SQRADDAC(a[5], a[14]); SQRADDAC(a[6], a[13]); SQRADDAC(a[7], a[12]); SQRADDAC(a[8], a[11]); SQRADDAC(a[9], a[10]); SQRADDDB; 
+      COMBA_STORE(b[19]);
+
+      /* output 20 */
+      CARRY_FORWARD;
+   SQRADDSC(a[5], a[15]); SQRADDAC(a[6], a[14]); SQRADDAC(a[7], a[13]); SQRADDAC(a[8], a[12]); SQRADDAC(a[9], a[11]); SQRADDDB; SQRADD(a[10], a[10]); 
+      COMBA_STORE(b[20]);
+
+      /* output 21 */
+      CARRY_FORWARD;
+   SQRADDSC(a[6], a[15]); SQRADDAC(a[7], a[14]); SQRADDAC(a[8], a[13]); SQRADDAC(a[9], a[12]); SQRADDAC(a[10], a[11]); SQRADDDB; 
+      COMBA_STORE(b[21]);
+
+      /* output 22 */
+      CARRY_FORWARD;
+   SQRADDSC(a[7], a[15]); SQRADDAC(a[8], a[14]); SQRADDAC(a[9], a[13]); SQRADDAC(a[10], a[12]); SQRADDDB; SQRADD(a[11], a[11]); 
+      COMBA_STORE(b[22]);
+
+      /* output 23 */
+      CARRY_FORWARD;
+   SQRADDSC(a[8], a[15]); SQRADDAC(a[9], a[14]); SQRADDAC(a[10], a[13]); SQRADDAC(a[11], a[12]); SQRADDDB; 
+      COMBA_STORE(b[23]);
+
+      /* output 24 */
+      CARRY_FORWARD;
+   SQRADDSC(a[9], a[15]); SQRADDAC(a[10], a[14]); SQRADDAC(a[11], a[13]); SQRADDDB; SQRADD(a[12], a[12]); 
+      COMBA_STORE(b[24]);
+
+      /* output 25 */
+      CARRY_FORWARD;
+   SQRADDSC(a[10], a[15]); SQRADDAC(a[11], a[14]); SQRADDAC(a[12], a[13]); SQRADDDB; 
+      COMBA_STORE(b[25]);
+
+      /* output 26 */
+      CARRY_FORWARD;
+      SQRADD2(a[11], a[15]);    SQRADD2(a[12], a[14]);    SQRADD(a[13], a[13]); 
+      COMBA_STORE(b[26]);
+
+      /* output 27 */
+      CARRY_FORWARD;
+      SQRADD2(a[12], a[15]);    SQRADD2(a[13], a[14]); 
+      COMBA_STORE(b[27]);
+
+      /* output 28 */
+      CARRY_FORWARD;
+      SQRADD2(a[13], a[15]);    SQRADD(a[14], a[14]); 
+      COMBA_STORE(b[28]);
+
+      /* output 29 */
+      CARRY_FORWARD;
+      SQRADD2(a[14], a[15]); 
+      COMBA_STORE(b[29]);
+
+      /* output 30 */
+      CARRY_FORWARD;
+      SQRADD(a[15], a[15]); 
+      COMBA_STORE(b[30]);
+      COMBA_STORE2(b[31]);
+      COMBA_FINI;
+
+      B->used = 32;
+      B->sign = FP_ZPOS;
+      memcpy(B->dp, b, 32 * sizeof(fp_digit));
+      fp_clamp(B);
+      break;
+
+   default:
+      break;
+}
+}
+
+#endif /* TFM_SMALL_SET */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/ge_low_mem.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/ge_low_mem.c
new file mode 100644
index 0000000..43c533c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/ge_low_mem.c
@@ -0,0 +1,558 @@
+/* ge_low_mem.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+ /* Based from Daniel Beer's public domain work. */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifdef HAVE_ED25519
+
+#include 
+#include 
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+void ed25519_smult(ge_p3 *r, const ge_p3 *a, const byte *e);
+void ed25519_add(ge_p3 *r, const ge_p3 *a, const ge_p3 *b);
+void ed25519_double(ge_p3 *r, const ge_p3 *a);
+
+
+static const byte ed25519_order[F25519_SIZE] = {
+	0xed, 0xd3, 0xf5, 0x5c, 0x1a, 0x63, 0x12, 0x58,
+	0xd6, 0x9c, 0xf7, 0xa2, 0xde, 0xf9, 0xde, 0x14,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10
+};
+
+/*Arithmetic modulo the group order m = 2^252 +
+ 27742317777372353535851937790883648493 =
+ 7237005577332262213973186563042994240857116359379907606001950938285454250989 */
+
+static const word32 m[32] = {
+    0xED,0xD3,0xF5,0x5C,0x1A,0x63,0x12,0x58,0xD6,0x9C,0xF7,0xA2,0xDE,0xF9,
+    0xDE,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+    0x00,0x00,0x00,0x10
+};
+
+static const word32 mu[33] = {
+    0x1B,0x13,0x2C,0x0A,0xA3,0xE5,0x9C,0xED,0xA7,0x29,0x63,0x08,0x5D,0x21,
+    0x06,0x21,0xEB,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0x0F
+};
+
+
+int ge_compress_key(byte* out, const byte* xIn, const byte* yIn,
+                        word32 keySz)
+{
+	byte tmp[F25519_SIZE];
+	byte parity;
+    int     i;
+
+	fe_copy(tmp, xIn);
+	parity = (tmp[0] & 1) << 7;
+
+    byte pt[32];
+	fe_copy(pt, yIn);
+	pt[31] |= parity;
+
+    for(i = 0; i < 32; i++) {
+        out[32-i-1] = pt[i];
+    }
+    (void)keySz;
+    return 0;
+}
+
+
+static word32 lt(word32 a,word32 b) /* 16-bit inputs */
+{
+  unsigned int x = a;
+  x -= (unsigned int) b; /* 0..65535: no; 4294901761..4294967295: yes */
+  x >>= 31; /* 0: no; 1: yes */
+  return x;
+}
+
+
+/* Reduce coefficients of r before calling reduce_add_sub */
+static void reduce_add_sub(word32 *r)
+{
+  word32 pb = 0;
+  word32 b;
+  word32 mask;
+  int i;
+  unsigned char t[32];
+
+  for(i=0;i<32;i++)
+  {
+    pb += m[i];
+    b = lt(r[i],pb);
+    t[i] = r[i]-pb+(b<<8);
+    pb = b;
+  }
+  mask = b - 1;
+  for(i=0;i<32;i++)
+    r[i] ^= mask & (r[i] ^ t[i]);
+}
+
+
+/* Reduce coefficients of x before calling barrett_reduce */
+static void barrett_reduce(word32* r, word32 x[64])
+{
+  /* See HAC, Alg. 14.42 */
+  int i,j;
+  word32 q2[66];
+  word32 *q3 = q2 + 33;
+  word32 r1[33];
+  word32 r2[33];
+  word32 carry;
+  word32 pb = 0;
+  word32 b;
+
+  for (i = 0;i < 66;++i) q2[i] = 0;
+  for (i = 0;i < 33;++i) r2[i] = 0;
+
+  for(i=0;i<33;i++)
+    for(j=0;j<33;j++)
+      if(i+j >= 31) q2[i+j] += mu[i]*x[j+31];
+  carry = q2[31] >> 8;
+  q2[32] += carry;
+  carry = q2[32] >> 8;
+  q2[33] += carry;
+
+  for(i=0;i<33;i++)r1[i] = x[i];
+  for(i=0;i<32;i++)
+    for(j=0;j<33;j++)
+      if(i+j < 33) r2[i+j] += m[i]*q3[j];
+
+  for(i=0;i<32;i++)
+  {
+    carry = r2[i] >> 8;
+    r2[i+1] += carry;
+    r2[i] &= 0xff;
+  }
+
+  for(i=0;i<32;i++)
+  {
+    pb += r2[i];
+    b = lt(r1[i],pb);
+    r[i] = r1[i]-pb+(b<<8);
+    pb = b;
+  }
+
+  /* XXX: Can it really happen that r<0?, See HAC, Alg 14.42, Step 3
+   * r is an unsigned type.
+   * If so: Handle  it here!
+   */
+
+  reduce_add_sub(r);
+  reduce_add_sub(r);
+}
+
+
+void sc_reduce(unsigned char x[64])
+{
+  int i;
+  word32 t[64];
+  word32 r[32];
+  for(i=0;i<64;i++) t[i] = x[i];
+  barrett_reduce(r, t);
+  for(i=0;i<32;i++) x[i] = (r[i] & 0xFF);
+}
+
+
+void sc_muladd(byte* out, const byte* a, const byte* b, const byte* c)
+{
+
+	byte s[32];
+    byte e[64];
+
+    XMEMSET(e, 0, sizeof(e));
+    XMEMCPY(e, b, 32);
+
+	/* Obtain e */
+	sc_reduce(e);
+
+	/* Compute s = ze + k */
+	fprime_mul(s, a, e, ed25519_order);
+	fprime_add(s, c, ed25519_order);
+
+	XMEMCPY(out, s, 32);
+}
+
+
+/* Base point is (numbers wrapped):
+ *
+ *     x = 151122213495354007725011514095885315114
+ *         54012693041857206046113283949847762202
+ *     y = 463168356949264781694283940034751631413
+ *         07993866256225615783033603165251855960
+ *
+ * y is derived by transforming the original Montgomery base (u=9). x
+ * is the corresponding positive coordinate for the new curve equation.
+ * t is x*y.
+ */
+const ge_p3 ed25519_base = {
+	.X = {
+		0x1a, 0xd5, 0x25, 0x8f, 0x60, 0x2d, 0x56, 0xc9,
+		0xb2, 0xa7, 0x25, 0x95, 0x60, 0xc7, 0x2c, 0x69,
+		0x5c, 0xdc, 0xd6, 0xfd, 0x31, 0xe2, 0xa4, 0xc0,
+		0xfe, 0x53, 0x6e, 0xcd, 0xd3, 0x36, 0x69, 0x21
+	},
+	.Y = {
+		0x58, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66,
+		0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66,
+		0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66,
+		0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66
+	},
+	.T = {
+		0xa3, 0xdd, 0xb7, 0xa5, 0xb3, 0x8a, 0xde, 0x6d,
+		0xf5, 0x52, 0x51, 0x77, 0x80, 0x9f, 0xf0, 0x20,
+		0x7d, 0xe3, 0xab, 0x64, 0x8e, 0x4e, 0xea, 0x66,
+		0x65, 0x76, 0x8b, 0xd7, 0x0f, 0x5f, 0x87, 0x67
+	},
+	.Z = {1, 0}
+};
+
+
+const ge_p3 ed25519_neutral = {
+	.X = {0},
+	.Y = {1, 0},
+	.T = {0},
+	.Z = {1, 0}
+};
+
+
+static const byte ed25519_d[F25519_SIZE] = {
+	0xa3, 0x78, 0x59, 0x13, 0xca, 0x4d, 0xeb, 0x75,
+	0xab, 0xd8, 0x41, 0x41, 0x4d, 0x0a, 0x70, 0x00,
+	0x98, 0xe8, 0x79, 0x77, 0x79, 0x40, 0xc7, 0x8c,
+	0x73, 0xfe, 0x6f, 0x2b, 0xee, 0x6c, 0x03, 0x52
+};
+
+
+/* k = 2d */
+static const byte ed25519_k[F25519_SIZE] = {
+	0x59, 0xf1, 0xb2, 0x26, 0x94, 0x9b, 0xd6, 0xeb,
+	0x56, 0xb1, 0x83, 0x82, 0x9a, 0x14, 0xe0, 0x00,
+	0x30, 0xd1, 0xf3, 0xee, 0xf2, 0x80, 0x8e, 0x19,
+	0xe7, 0xfc, 0xdf, 0x56, 0xdc, 0xd9, 0x06, 0x24
+};
+
+
+void ed25519_add(ge_p3 *r,
+		 const ge_p3 *p1, const ge_p3 *p2)
+{
+	/* Explicit formulas database: add-2008-hwcd-3
+	 *
+	 * source 2008 Hisil--Wong--Carter--Dawson,
+	 *     http://eprint.iacr.org/2008/522, Section 3.1
+	 * appliesto extended-1
+	 * parameter k
+	 * assume k = 2 d
+	 * compute A = (Y1-X1)(Y2-X2)
+	 * compute B = (Y1+X1)(Y2+X2)
+	 * compute C = T1 k T2
+	 * compute D = Z1 2 Z2
+	 * compute E = B - A
+	 * compute F = D - C
+	 * compute G = D + C
+	 * compute H = B + A
+	 * compute X3 = E F
+	 * compute Y3 = G H
+	 * compute T3 = E H
+	 * compute Z3 = F G
+	 */
+	byte a[F25519_SIZE];
+	byte b[F25519_SIZE];
+	byte c[F25519_SIZE];
+	byte d[F25519_SIZE];
+	byte e[F25519_SIZE];
+	byte f[F25519_SIZE];
+	byte g[F25519_SIZE];
+	byte h[F25519_SIZE];
+
+	/* A = (Y1-X1)(Y2-X2) */
+	fe_sub(c, p1->Y, p1->X);
+	fe_sub(d, p2->Y, p2->X);
+	fe_mul__distinct(a, c, d);
+
+	/* B = (Y1+X1)(Y2+X2) */
+	fe_add(c, p1->Y, p1->X);
+	fe_add(d, p2->Y, p2->X);
+	fe_mul__distinct(b, c, d);
+
+	/* C = T1 k T2 */
+	fe_mul__distinct(d, p1->T, p2->T);
+	fe_mul__distinct(c, d, ed25519_k);
+
+	/* D = Z1 2 Z2 */
+	fe_mul__distinct(d, p1->Z, p2->Z);
+	fe_add(d, d, d);
+
+	/* E = B - A */
+	fe_sub(e, b, a);
+
+	/* F = D - C */
+	fe_sub(f, d, c);
+
+	/* G = D + C */
+	fe_add(g, d, c);
+
+	/* H = B + A */
+	fe_add(h, b, a);
+
+	/* X3 = E F */
+	fe_mul__distinct(r->X, e, f);
+
+	/* Y3 = G H */
+	fe_mul__distinct(r->Y, g, h);
+
+	/* T3 = E H */
+	fe_mul__distinct(r->T, e, h);
+
+	/* Z3 = F G */
+	fe_mul__distinct(r->Z, f, g);
+}
+
+
+void ed25519_double(ge_p3 *r, const ge_p3 *p)
+{
+	/* Explicit formulas database: dbl-2008-hwcd
+	 *
+	 * source 2008 Hisil--Wong--Carter--Dawson,
+	 *     http://eprint.iacr.org/2008/522, Section 3.3
+	 * compute A = X1^2
+	 * compute B = Y1^2
+	 * compute C = 2 Z1^2
+	 * compute D = a A
+	 * compute E = (X1+Y1)^2-A-B
+	 * compute G = D + B
+	 * compute F = G - C
+	 * compute H = D - B
+	 * compute X3 = E F
+	 * compute Y3 = G H
+	 * compute T3 = E H
+	 * compute Z3 = F G
+	 */
+	byte a[F25519_SIZE];
+	byte b[F25519_SIZE];
+	byte c[F25519_SIZE];
+	byte e[F25519_SIZE];
+	byte f[F25519_SIZE];
+	byte g[F25519_SIZE];
+	byte h[F25519_SIZE];
+
+	/* A = X1^2 */
+	fe_mul__distinct(a, p->X, p->X);
+
+	/* B = Y1^2 */
+	fe_mul__distinct(b, p->Y, p->Y);
+
+	/* C = 2 Z1^2 */
+	fe_mul__distinct(c, p->Z, p->Z);
+	fe_add(c, c, c);
+
+	/* D = a A (alter sign) */
+	/* E = (X1+Y1)^2-A-B */
+	fe_add(f, p->X, p->Y);
+	fe_mul__distinct(e, f, f);
+	fe_sub(e, e, a);
+	fe_sub(e, e, b);
+
+	/* G = D + B */
+	fe_sub(g, b, a);
+
+	/* F = G - C */
+	fe_sub(f, g, c);
+
+	/* H = D - B */
+	fe_neg(h, b);
+	fe_sub(h, h, a);
+
+	/* X3 = E F */
+	fe_mul__distinct(r->X, e, f);
+
+	/* Y3 = G H */
+	fe_mul__distinct(r->Y, g, h);
+
+	/* T3 = E H */
+	fe_mul__distinct(r->T, e, h);
+
+	/* Z3 = F G */
+	fe_mul__distinct(r->Z, f, g);
+}
+
+
+void ed25519_smult(ge_p3 *r_out, const ge_p3 *p, const byte *e)
+{
+	ge_p3 r;
+	int   i;
+
+    XMEMCPY(&r, &ed25519_neutral, sizeof(r));
+
+	for (i = 255; i >= 0; i--) {
+		const byte bit = (e[i >> 3] >> (i & 7)) & 1;
+		ge_p3 s;
+
+		ed25519_double(&r, &r);
+		ed25519_add(&s, &r, p);
+
+		fe_select(r.X, r.X, s.X, bit);
+		fe_select(r.Y, r.Y, s.Y, bit);
+		fe_select(r.Z, r.Z, s.Z, bit);
+		fe_select(r.T, r.T, s.T, bit);
+	}
+    XMEMCPY(r_out, &r, sizeof(r));
+}
+
+
+void ge_scalarmult_base(ge_p3 *R,const unsigned char *nonce)
+{
+	ed25519_smult(R, &ed25519_base, nonce);
+}
+
+
+/* pack the point h into array s */
+void ge_p3_tobytes(unsigned char *s,const ge_p3 *h)
+{
+	byte x[F25519_SIZE];
+	byte y[F25519_SIZE];
+	byte z1[F25519_SIZE];
+	byte parity;
+
+	fe_inv__distinct(z1, h->Z);
+	fe_mul__distinct(x, h->X, z1);
+	fe_mul__distinct(y, h->Y, z1);
+
+	fe_normalize(x);
+	fe_normalize(y);
+
+	parity = (x[0] & 1) << 7;
+	fe_copy(s, y);
+	fe_normalize(s);
+	s[31] |= parity;
+}
+
+
+/* pack the point h into array s */
+void ge_tobytes(unsigned char *s,const ge_p2 *h)
+{
+	byte x[F25519_SIZE];
+	byte y[F25519_SIZE];
+	byte z1[F25519_SIZE];
+	byte parity;
+
+	fe_inv__distinct(z1, h->Z);
+	fe_mul__distinct(x, h->X, z1);
+	fe_mul__distinct(y, h->Y, z1);
+
+	fe_normalize(x);
+	fe_normalize(y);
+
+	parity = (x[0] & 1) << 7;
+	fe_copy(s, y);
+	fe_normalize(s);
+	s[31] |= parity;
+}
+
+
+/*
+   Test if the public key can be uncommpressed and negate it (-X,Y,Z,-T)
+   return 0 on success
+ */
+int ge_frombytes_negate_vartime(ge_p3 *p,const unsigned char *s)
+{
+
+	byte parity;
+    byte x[F25519_SIZE];
+	byte y[F25519_SIZE];
+	byte a[F25519_SIZE];
+	byte b[F25519_SIZE];
+	byte c[F25519_SIZE];
+    int ret = 0;
+
+    /* unpack the key s */
+    parity = s[31] >> 7;
+    fe_copy(y, s);
+	y[31] &= 127;
+
+	fe_mul__distinct(c, y, y);
+    fe_mul__distinct(b, c, ed25519_d);
+	fe_add(a, b, f25519_one);
+	fe_inv__distinct(b, a);
+	fe_sub(a, c, f25519_one);
+	fe_mul__distinct(c, a, b);
+	fe_sqrt(a, c);
+	fe_neg(b, a);
+	fe_select(x, a, b, (a[0] ^ parity) & 1);
+
+    /* test that x^2 is equal to c */
+    fe_mul__distinct(a, x, x);
+	fe_normalize(a);
+	fe_normalize(c);
+	ret |= ConstantCompare(a, c, F25519_SIZE);
+
+    /* project the key s onto p */
+	fe_copy(p->X, x);
+	fe_copy(p->Y, y);
+	fe_load(p->Z, 1);
+	fe_mul__distinct(p->T, x, y);
+
+    /* negate, the point becomes (-X,Y,Z,-T) */
+    fe_neg(p->X,p->X);
+    fe_neg(p->T,p->T);
+
+    return ret;
+}
+
+
+int ge_double_scalarmult_vartime(ge_p2* R, const unsigned char *h,
+                                 const ge_p3 *inA,const unsigned char *sig)
+{
+    ge_p3 p, A;
+    int ret = 0;
+
+    XMEMCPY(&A, inA, sizeof(ge_p3));
+
+    /* find SB */
+    ed25519_smult(&p, &ed25519_base, sig);
+
+    /* find H(R,A,M) * -A */
+	ed25519_smult(&A, &A, h);
+
+    /* SB + -H(R,A,M)A */
+	ed25519_add(&A, &p, &A);
+
+    fe_copy(R->X, A.X);
+    fe_copy(R->Y, A.Y);
+    fe_copy(R->Z, A.Z);
+
+    return ret;
+}
+
+#endif /* HAVE_ED25519 */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/ge_operations.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/ge_operations.c
new file mode 100644
index 0000000..665cfe8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/ge_operations.c
@@ -0,0 +1,2603 @@
+/* ge_operations.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+ /* Based On Daniel J Bernstein's ed25519 Public Domain ref10 work. */
+
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifdef HAVE_ED25519
+
+#include 
+#include 
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+/*
+ge means group element.
+
+Here the group is the set of pairs (x,y) of field elements (see fe.h)
+satisfying -x^2 + y^2 = 1 + d x^2y^2
+where d = -121665/121666.
+
+Representations:
+  ge_p2 (projective): (X:Y:Z) satisfying x=X/Z, y=Y/Z
+  ge_p3 (extended): (X:Y:Z:T) satisfying x=X/Z, y=Y/Z, XY=ZT
+  ge_p1p1 (completed): ((X:Z),(Y:T)) satisfying x=X/Z, y=Y/T
+  ge_precomp (Duif): (y+x,y-x,2dxy)
+*/
+
+
+/*
+Input:
+  s[0]+256*s[1]+...+256^63*s[63] = s
+
+Output:
+  s[0]+256*s[1]+...+256^31*s[31] = s mod l
+  where l = 2^252 + 27742317777372353535851937790883648493.
+  Overwrites s in place.
+*/
+void sc_reduce(byte* s)
+{
+  int64_t s0 = 2097151 & load_3(s);
+  int64_t s1 = 2097151 & (load_4(s + 2) >> 5);
+  int64_t s2 = 2097151 & (load_3(s + 5) >> 2);
+  int64_t s3 = 2097151 & (load_4(s + 7) >> 7);
+  int64_t s4 = 2097151 & (load_4(s + 10) >> 4);
+  int64_t s5 = 2097151 & (load_3(s + 13) >> 1);
+  int64_t s6 = 2097151 & (load_4(s + 15) >> 6);
+  int64_t s7 = 2097151 & (load_3(s + 18) >> 3);
+  int64_t s8 = 2097151 & load_3(s + 21);
+  int64_t s9 = 2097151 & (load_4(s + 23) >> 5);
+  int64_t s10 = 2097151 & (load_3(s + 26) >> 2);
+  int64_t s11 = 2097151 & (load_4(s + 28) >> 7);
+  int64_t s12 = 2097151 & (load_4(s + 31) >> 4);
+  int64_t s13 = 2097151 & (load_3(s + 34) >> 1);
+  int64_t s14 = 2097151 & (load_4(s + 36) >> 6);
+  int64_t s15 = 2097151 & (load_3(s + 39) >> 3);
+  int64_t s16 = 2097151 & load_3(s + 42);
+  int64_t s17 = 2097151 & (load_4(s + 44) >> 5);
+  int64_t s18 = 2097151 & (load_3(s + 47) >> 2);
+  int64_t s19 = 2097151 & (load_4(s + 49) >> 7);
+  int64_t s20 = 2097151 & (load_4(s + 52) >> 4);
+  int64_t s21 = 2097151 & (load_3(s + 55) >> 1);
+  int64_t s22 = 2097151 & (load_4(s + 57) >> 6);
+  int64_t s23 = (load_4(s + 60) >> 3);
+  int64_t carry0;
+  int64_t carry1;
+  int64_t carry2;
+  int64_t carry3;
+  int64_t carry4;
+  int64_t carry5;
+  int64_t carry6;
+  int64_t carry7;
+  int64_t carry8;
+  int64_t carry9;
+  int64_t carry10;
+  int64_t carry11;
+  int64_t carry12;
+  int64_t carry13;
+  int64_t carry14;
+  int64_t carry15;
+  int64_t carry16;
+
+  s11 += s23 * 666643;
+  s12 += s23 * 470296;
+  s13 += s23 * 654183;
+  s14 -= s23 * 997805;
+  s15 += s23 * 136657;
+  s16 -= s23 * 683901;
+  s23 = 0;
+
+  s10 += s22 * 666643;
+  s11 += s22 * 470296;
+  s12 += s22 * 654183;
+  s13 -= s22 * 997805;
+  s14 += s22 * 136657;
+  s15 -= s22 * 683901;
+  s22 = 0;
+
+  s9 += s21 * 666643;
+  s10 += s21 * 470296;
+  s11 += s21 * 654183;
+  s12 -= s21 * 997805;
+  s13 += s21 * 136657;
+  s14 -= s21 * 683901;
+  s21 = 0;
+
+  s8 += s20 * 666643;
+  s9 += s20 * 470296;
+  s10 += s20 * 654183;
+  s11 -= s20 * 997805;
+  s12 += s20 * 136657;
+  s13 -= s20 * 683901;
+  s20 = 0;
+
+  s7 += s19 * 666643;
+  s8 += s19 * 470296;
+  s9 += s19 * 654183;
+  s10 -= s19 * 997805;
+  s11 += s19 * 136657;
+  s12 -= s19 * 683901;
+  s19 = 0;
+
+  s6 += s18 * 666643;
+  s7 += s18 * 470296;
+  s8 += s18 * 654183;
+  s9 -= s18 * 997805;
+  s10 += s18 * 136657;
+  s11 -= s18 * 683901;
+  s18 = 0;
+
+  carry6 = (s6 + (1<<20)) >> 21; s7 += carry6; s6 -= carry6 << 21;
+  carry8 = (s8 + (1<<20)) >> 21; s9 += carry8; s8 -= carry8 << 21;
+  carry10 = (s10 + (1<<20)) >> 21; s11 += carry10; s10 -= carry10 << 21;
+  carry12 = (s12 + (1<<20)) >> 21; s13 += carry12; s12 -= carry12 << 21;
+  carry14 = (s14 + (1<<20)) >> 21; s15 += carry14; s14 -= carry14 << 21;
+  carry16 = (s16 + (1<<20)) >> 21; s17 += carry16; s16 -= carry16 << 21;
+
+  carry7 = (s7 + (1<<20)) >> 21; s8 += carry7; s7 -= carry7 << 21;
+  carry9 = (s9 + (1<<20)) >> 21; s10 += carry9; s9 -= carry9 << 21;
+  carry11 = (s11 + (1<<20)) >> 21; s12 += carry11; s11 -= carry11 << 21;
+  carry13 = (s13 + (1<<20)) >> 21; s14 += carry13; s13 -= carry13 << 21;
+  carry15 = (s15 + (1<<20)) >> 21; s16 += carry15; s15 -= carry15 << 21;
+
+  s5 += s17 * 666643;
+  s6 += s17 * 470296;
+  s7 += s17 * 654183;
+  s8 -= s17 * 997805;
+  s9 += s17 * 136657;
+  s10 -= s17 * 683901;
+  s17 = 0;
+
+  s4 += s16 * 666643;
+  s5 += s16 * 470296;
+  s6 += s16 * 654183;
+  s7 -= s16 * 997805;
+  s8 += s16 * 136657;
+  s9 -= s16 * 683901;
+  s16 = 0;
+
+  s3 += s15 * 666643;
+  s4 += s15 * 470296;
+  s5 += s15 * 654183;
+  s6 -= s15 * 997805;
+  s7 += s15 * 136657;
+  s8 -= s15 * 683901;
+  s15 = 0;
+
+  s2 += s14 * 666643;
+  s3 += s14 * 470296;
+  s4 += s14 * 654183;
+  s5 -= s14 * 997805;
+  s6 += s14 * 136657;
+  s7 -= s14 * 683901;
+  s14 = 0;
+
+  s1 += s13 * 666643;
+  s2 += s13 * 470296;
+  s3 += s13 * 654183;
+  s4 -= s13 * 997805;
+  s5 += s13 * 136657;
+  s6 -= s13 * 683901;
+  s13 = 0;
+
+  s0 += s12 * 666643;
+  s1 += s12 * 470296;
+  s2 += s12 * 654183;
+  s3 -= s12 * 997805;
+  s4 += s12 * 136657;
+  s5 -= s12 * 683901;
+  s12 = 0;
+
+  carry0 = (s0 + (1<<20)) >> 21; s1 += carry0; s0 -= carry0 << 21;
+  carry2 = (s2 + (1<<20)) >> 21; s3 += carry2; s2 -= carry2 << 21;
+  carry4 = (s4 + (1<<20)) >> 21; s5 += carry4; s4 -= carry4 << 21;
+  carry6 = (s6 + (1<<20)) >> 21; s7 += carry6; s6 -= carry6 << 21;
+  carry8 = (s8 + (1<<20)) >> 21; s9 += carry8; s8 -= carry8 << 21;
+  carry10 = (s10 + (1<<20)) >> 21; s11 += carry10; s10 -= carry10 << 21;
+
+  carry1 = (s1 + (1<<20)) >> 21; s2 += carry1; s1 -= carry1 << 21;
+  carry3 = (s3 + (1<<20)) >> 21; s4 += carry3; s3 -= carry3 << 21;
+  carry5 = (s5 + (1<<20)) >> 21; s6 += carry5; s5 -= carry5 << 21;
+  carry7 = (s7 + (1<<20)) >> 21; s8 += carry7; s7 -= carry7 << 21;
+  carry9 = (s9 + (1<<20)) >> 21; s10 += carry9; s9 -= carry9 << 21;
+  carry11 = (s11 + (1<<20)) >> 21; s12 += carry11; s11 -= carry11 << 21;
+
+  s0 += s12 * 666643;
+  s1 += s12 * 470296;
+  s2 += s12 * 654183;
+  s3 -= s12 * 997805;
+  s4 += s12 * 136657;
+  s5 -= s12 * 683901;
+  s12 = 0;
+
+  carry0 = s0 >> 21; s1 += carry0; s0 -= carry0 << 21;
+  carry1 = s1 >> 21; s2 += carry1; s1 -= carry1 << 21;
+  carry2 = s2 >> 21; s3 += carry2; s2 -= carry2 << 21;
+  carry3 = s3 >> 21; s4 += carry3; s3 -= carry3 << 21;
+  carry4 = s4 >> 21; s5 += carry4; s4 -= carry4 << 21;
+  carry5 = s5 >> 21; s6 += carry5; s5 -= carry5 << 21;
+  carry6 = s6 >> 21; s7 += carry6; s6 -= carry6 << 21;
+  carry7 = s7 >> 21; s8 += carry7; s7 -= carry7 << 21;
+  carry8 = s8 >> 21; s9 += carry8; s8 -= carry8 << 21;
+  carry9 = s9 >> 21; s10 += carry9; s9 -= carry9 << 21;
+  carry10 = s10 >> 21; s11 += carry10; s10 -= carry10 << 21;
+  carry11 = s11 >> 21; s12 += carry11; s11 -= carry11 << 21;
+
+  s0 += s12 * 666643;
+  s1 += s12 * 470296;
+  s2 += s12 * 654183;
+  s3 -= s12 * 997805;
+  s4 += s12 * 136657;
+  s5 -= s12 * 683901;
+  s12 = 0;
+
+  carry0 = s0 >> 21; s1 += carry0; s0 -= carry0 << 21;
+  carry1 = s1 >> 21; s2 += carry1; s1 -= carry1 << 21;
+  carry2 = s2 >> 21; s3 += carry2; s2 -= carry2 << 21;
+  carry3 = s3 >> 21; s4 += carry3; s3 -= carry3 << 21;
+  carry4 = s4 >> 21; s5 += carry4; s4 -= carry4 << 21;
+  carry5 = s5 >> 21; s6 += carry5; s5 -= carry5 << 21;
+  carry6 = s6 >> 21; s7 += carry6; s6 -= carry6 << 21;
+  carry7 = s7 >> 21; s8 += carry7; s7 -= carry7 << 21;
+  carry8 = s8 >> 21; s9 += carry8; s8 -= carry8 << 21;
+  carry9 = s9 >> 21; s10 += carry9; s9 -= carry9 << 21;
+  carry10 = s10 >> 21; s11 += carry10; s10 -= carry10 << 21;
+
+  s[0] = s0 >> 0;
+  s[1] = s0 >> 8;
+  s[2] = (s0 >> 16) | (s1 << 5);
+  s[3] = s1 >> 3;
+  s[4] = s1 >> 11;
+  s[5] = (s1 >> 19) | (s2 << 2);
+  s[6] = s2 >> 6;
+  s[7] = (s2 >> 14) | (s3 << 7);
+  s[8] = s3 >> 1;
+  s[9] = s3 >> 9;
+  s[10] = (s3 >> 17) | (s4 << 4);
+  s[11] = s4 >> 4;
+  s[12] = s4 >> 12;
+  s[13] = (s4 >> 20) | (s5 << 1);
+  s[14] = s5 >> 7;
+  s[15] = (s5 >> 15) | (s6 << 6);
+  s[16] = s6 >> 2;
+  s[17] = s6 >> 10;
+  s[18] = (s6 >> 18) | (s7 << 3);
+  s[19] = s7 >> 5;
+  s[20] = s7 >> 13;
+  s[21] = s8 >> 0;
+  s[22] = s8 >> 8;
+  s[23] = (s8 >> 16) | (s9 << 5);
+  s[24] = s9 >> 3;
+  s[25] = s9 >> 11;
+  s[26] = (s9 >> 19) | (s10 << 2);
+  s[27] = s10 >> 6;
+  s[28] = (s10 >> 14) | (s11 << 7);
+  s[29] = s11 >> 1;
+  s[30] = s11 >> 9;
+  s[31] = s11 >> 17;
+
+  /* hush warnings after setting values to 0 */
+  (void)s12;
+  (void)s13;
+  (void)s14;
+  (void)s15;
+  (void)s16;
+  (void)s17;
+  (void)s18;
+  (void)s19;
+  (void)s20;
+  (void)s21;
+  (void)s22;
+  (void)s23;
+}
+
+
+/*
+Input:
+  a[0]+256*a[1]+...+256^31*a[31] = a
+  b[0]+256*b[1]+...+256^31*b[31] = b
+  c[0]+256*c[1]+...+256^31*c[31] = c
+
+Output:
+  s[0]+256*s[1]+...+256^31*s[31] = (ab+c) mod l
+  where l = 2^252 + 27742317777372353535851937790883648493.
+*/
+void sc_muladd(byte* s, const byte* a, const byte* b, const byte* c)
+{
+  int64_t a0 = 2097151 & load_3(a);
+  int64_t a1 = 2097151 & (load_4(a + 2) >> 5);
+  int64_t a2 = 2097151 & (load_3(a + 5) >> 2);
+  int64_t a3 = 2097151 & (load_4(a + 7) >> 7);
+  int64_t a4 = 2097151 & (load_4(a + 10) >> 4);
+  int64_t a5 = 2097151 & (load_3(a + 13) >> 1);
+  int64_t a6 = 2097151 & (load_4(a + 15) >> 6);
+  int64_t a7 = 2097151 & (load_3(a + 18) >> 3);
+  int64_t a8 = 2097151 & load_3(a + 21);
+  int64_t a9 = 2097151 & (load_4(a + 23) >> 5);
+  int64_t a10 = 2097151 & (load_3(a + 26) >> 2);
+  int64_t a11 = (load_4(a + 28) >> 7);
+  int64_t b0 = 2097151 & load_3(b);
+  int64_t b1 = 2097151 & (load_4(b + 2) >> 5);
+  int64_t b2 = 2097151 & (load_3(b + 5) >> 2);
+  int64_t b3 = 2097151 & (load_4(b + 7) >> 7);
+  int64_t b4 = 2097151 & (load_4(b + 10) >> 4);
+  int64_t b5 = 2097151 & (load_3(b + 13) >> 1);
+  int64_t b6 = 2097151 & (load_4(b + 15) >> 6);
+  int64_t b7 = 2097151 & (load_3(b + 18) >> 3);
+  int64_t b8 = 2097151 & load_3(b + 21);
+  int64_t b9 = 2097151 & (load_4(b + 23) >> 5);
+  int64_t b10 = 2097151 & (load_3(b + 26) >> 2);
+  int64_t b11 = (load_4(b + 28) >> 7);
+  int64_t c0 = 2097151 & load_3(c);
+  int64_t c1 = 2097151 & (load_4(c + 2) >> 5);
+  int64_t c2 = 2097151 & (load_3(c + 5) >> 2);
+  int64_t c3 = 2097151 & (load_4(c + 7) >> 7);
+  int64_t c4 = 2097151 & (load_4(c + 10) >> 4);
+  int64_t c5 = 2097151 & (load_3(c + 13) >> 1);
+  int64_t c6 = 2097151 & (load_4(c + 15) >> 6);
+  int64_t c7 = 2097151 & (load_3(c + 18) >> 3);
+  int64_t c8 = 2097151 & load_3(c + 21);
+  int64_t c9 = 2097151 & (load_4(c + 23) >> 5);
+  int64_t c10 = 2097151 & (load_3(c + 26) >> 2);
+  int64_t c11 = (load_4(c + 28) >> 7);
+  int64_t s0;
+  int64_t s1;
+  int64_t s2;
+  int64_t s3;
+  int64_t s4;
+  int64_t s5;
+  int64_t s6;
+  int64_t s7;
+  int64_t s8;
+  int64_t s9;
+  int64_t s10;
+  int64_t s11;
+  int64_t s12;
+  int64_t s13;
+  int64_t s14;
+  int64_t s15;
+  int64_t s16;
+  int64_t s17;
+  int64_t s18;
+  int64_t s19;
+  int64_t s20;
+  int64_t s21;
+  int64_t s22;
+  int64_t s23;
+  int64_t carry0;
+  int64_t carry1;
+  int64_t carry2;
+  int64_t carry3;
+  int64_t carry4;
+  int64_t carry5;
+  int64_t carry6;
+  int64_t carry7;
+  int64_t carry8;
+  int64_t carry9;
+  int64_t carry10;
+  int64_t carry11;
+  int64_t carry12;
+  int64_t carry13;
+  int64_t carry14;
+  int64_t carry15;
+  int64_t carry16;
+  int64_t carry17;
+  int64_t carry18;
+  int64_t carry19;
+  int64_t carry20;
+  int64_t carry21;
+  int64_t carry22;
+
+  s0 = c0 + a0*b0;
+  s1 = c1 + a0*b1 + a1*b0;
+  s2 = c2 + a0*b2 + a1*b1 + a2*b0;
+  s3 = c3 + a0*b3 + a1*b2 + a2*b1 + a3*b0;
+  s4 = c4 + a0*b4 + a1*b3 + a2*b2 + a3*b1 + a4*b0;
+  s5 = c5 + a0*b5 + a1*b4 + a2*b3 + a3*b2 + a4*b1 + a5*b0;
+  s6 = c6 + a0*b6 + a1*b5 + a2*b4 + a3*b3 + a4*b2 + a5*b1 + a6*b0;
+  s7 = c7 + a0*b7 + a1*b6 + a2*b5 + a3*b4 + a4*b3 + a5*b2 + a6*b1 + a7*b0;
+  s8 = c8 + a0*b8 + a1*b7 + a2*b6 + a3*b5 + a4*b4 + a5*b3 + a6*b2 + a7*b1
+          + a8*b0;
+  s9 = c9 + a0*b9 + a1*b8 + a2*b7 + a3*b6 + a4*b5 + a5*b4 + a6*b3 + a7*b2
+          + a8*b1 + a9*b0;
+  s10 = c10 + a0*b10 + a1*b9 + a2*b8 + a3*b7 + a4*b6 + a5*b5 + a6*b4 + a7*b3
+            + a8*b2 + a9*b1 + a10*b0;
+  s11 = c11 + a0*b11 + a1*b10 + a2*b9 + a3*b8 + a4*b7 + a5*b6 + a6*b5 + a7*b4
+            + a8*b3 + a9*b2 + a10*b1 + a11*b0;
+  s12 = a1*b11 + a2*b10 + a3*b9 + a4*b8 + a5*b7 + a6*b6 + a7*b5 + a8*b4 + a9*b3
+               + a10*b2 + a11*b1;
+  s13 = a2*b11 + a3*b10 + a4*b9 + a5*b8 + a6*b7 + a7*b6 + a8*b5 + a9*b4 + a10*b3
+               + a11*b2;
+  s14 = a3*b11 + a4*b10 + a5*b9 + a6*b8 + a7*b7 + a8*b6 + a9*b5 + a10*b4
+               + a11*b3;
+  s15 = a4*b11 + a5*b10 + a6*b9 + a7*b8 + a8*b7 + a9*b6 + a10*b5 + a11*b4;
+  s16 = a5*b11 + a6*b10 + a7*b9 + a8*b8 + a9*b7 + a10*b6 + a11*b5;
+  s17 = a6*b11 + a7*b10 + a8*b9 + a9*b8 + a10*b7 + a11*b6;
+  s18 = a7*b11 + a8*b10 + a9*b9 + a10*b8 + a11*b7;
+  s19 = a8*b11 + a9*b10 + a10*b9 + a11*b8;
+  s20 = a9*b11 + a10*b10 + a11*b9;
+  s21 = a10*b11 + a11*b10;
+  s22 = a11*b11;
+  s23 = 0;
+
+  carry0 = (s0 + (1<<20)) >> 21; s1 += carry0; s0 -= carry0 << 21;
+  carry2 = (s2 + (1<<20)) >> 21; s3 += carry2; s2 -= carry2 << 21;
+  carry4 = (s4 + (1<<20)) >> 21; s5 += carry4; s4 -= carry4 << 21;
+  carry6 = (s6 + (1<<20)) >> 21; s7 += carry6; s6 -= carry6 << 21;
+  carry8 = (s8 + (1<<20)) >> 21; s9 += carry8; s8 -= carry8 << 21;
+  carry10 = (s10 + (1<<20)) >> 21; s11 += carry10; s10 -= carry10 << 21;
+  carry12 = (s12 + (1<<20)) >> 21; s13 += carry12; s12 -= carry12 << 21;
+  carry14 = (s14 + (1<<20)) >> 21; s15 += carry14; s14 -= carry14 << 21;
+  carry16 = (s16 + (1<<20)) >> 21; s17 += carry16; s16 -= carry16 << 21;
+  carry18 = (s18 + (1<<20)) >> 21; s19 += carry18; s18 -= carry18 << 21;
+  carry20 = (s20 + (1<<20)) >> 21; s21 += carry20; s20 -= carry20 << 21;
+  carry22 = (s22 + (1<<20)) >> 21; s23 += carry22; s22 -= carry22 << 21;
+
+  carry1 = (s1 + (1<<20)) >> 21; s2 += carry1; s1 -= carry1 << 21;
+  carry3 = (s3 + (1<<20)) >> 21; s4 += carry3; s3 -= carry3 << 21;
+  carry5 = (s5 + (1<<20)) >> 21; s6 += carry5; s5 -= carry5 << 21;
+  carry7 = (s7 + (1<<20)) >> 21; s8 += carry7; s7 -= carry7 << 21;
+  carry9 = (s9 + (1<<20)) >> 21; s10 += carry9; s9 -= carry9 << 21;
+  carry11 = (s11 + (1<<20)) >> 21; s12 += carry11; s11 -= carry11 << 21;
+  carry13 = (s13 + (1<<20)) >> 21; s14 += carry13; s13 -= carry13 << 21;
+  carry15 = (s15 + (1<<20)) >> 21; s16 += carry15; s15 -= carry15 << 21;
+  carry17 = (s17 + (1<<20)) >> 21; s18 += carry17; s17 -= carry17 << 21;
+  carry19 = (s19 + (1<<20)) >> 21; s20 += carry19; s19 -= carry19 << 21;
+  carry21 = (s21 + (1<<20)) >> 21; s22 += carry21; s21 -= carry21 << 21;
+
+  s11 += s23 * 666643;
+  s12 += s23 * 470296;
+  s13 += s23 * 654183;
+  s14 -= s23 * 997805;
+  s15 += s23 * 136657;
+  s16 -= s23 * 683901;
+  s23 = 0;
+
+  s10 += s22 * 666643;
+  s11 += s22 * 470296;
+  s12 += s22 * 654183;
+  s13 -= s22 * 997805;
+  s14 += s22 * 136657;
+  s15 -= s22 * 683901;
+  s22 = 0;
+
+  s9 += s21 * 666643;
+  s10 += s21 * 470296;
+  s11 += s21 * 654183;
+  s12 -= s21 * 997805;
+  s13 += s21 * 136657;
+  s14 -= s21 * 683901;
+  s21 = 0;
+
+  s8 += s20 * 666643;
+  s9 += s20 * 470296;
+  s10 += s20 * 654183;
+  s11 -= s20 * 997805;
+  s12 += s20 * 136657;
+  s13 -= s20 * 683901;
+  s20 = 0;
+
+  s7 += s19 * 666643;
+  s8 += s19 * 470296;
+  s9 += s19 * 654183;
+  s10 -= s19 * 997805;
+  s11 += s19 * 136657;
+  s12 -= s19 * 683901;
+  s19 = 0;
+
+  s6 += s18 * 666643;
+  s7 += s18 * 470296;
+  s8 += s18 * 654183;
+  s9 -= s18 * 997805;
+  s10 += s18 * 136657;
+  s11 -= s18 * 683901;
+  s18 = 0;
+
+  carry6 = (s6 + (1<<20)) >> 21; s7 += carry6; s6 -= carry6 << 21;
+  carry8 = (s8 + (1<<20)) >> 21; s9 += carry8; s8 -= carry8 << 21;
+  carry10 = (s10 + (1<<20)) >> 21; s11 += carry10; s10 -= carry10 << 21;
+  carry12 = (s12 + (1<<20)) >> 21; s13 += carry12; s12 -= carry12 << 21;
+  carry14 = (s14 + (1<<20)) >> 21; s15 += carry14; s14 -= carry14 << 21;
+  carry16 = (s16 + (1<<20)) >> 21; s17 += carry16; s16 -= carry16 << 21;
+
+  carry7 = (s7 + (1<<20)) >> 21; s8 += carry7; s7 -= carry7 << 21;
+  carry9 = (s9 + (1<<20)) >> 21; s10 += carry9; s9 -= carry9 << 21;
+  carry11 = (s11 + (1<<20)) >> 21; s12 += carry11; s11 -= carry11 << 21;
+  carry13 = (s13 + (1<<20)) >> 21; s14 += carry13; s13 -= carry13 << 21;
+  carry15 = (s15 + (1<<20)) >> 21; s16 += carry15; s15 -= carry15 << 21;
+
+  s5 += s17 * 666643;
+  s6 += s17 * 470296;
+  s7 += s17 * 654183;
+  s8 -= s17 * 997805;
+  s9 += s17 * 136657;
+  s10 -= s17 * 683901;
+  s17 = 0;
+
+  s4 += s16 * 666643;
+  s5 += s16 * 470296;
+  s6 += s16 * 654183;
+  s7 -= s16 * 997805;
+  s8 += s16 * 136657;
+  s9 -= s16 * 683901;
+  s16 = 0;
+
+  s3 += s15 * 666643;
+  s4 += s15 * 470296;
+  s5 += s15 * 654183;
+  s6 -= s15 * 997805;
+  s7 += s15 * 136657;
+  s8 -= s15 * 683901;
+  s15 = 0;
+
+  s2 += s14 * 666643;
+  s3 += s14 * 470296;
+  s4 += s14 * 654183;
+  s5 -= s14 * 997805;
+  s6 += s14 * 136657;
+  s7 -= s14 * 683901;
+  s14 = 0;
+
+  s1 += s13 * 666643;
+  s2 += s13 * 470296;
+  s3 += s13 * 654183;
+  s4 -= s13 * 997805;
+  s5 += s13 * 136657;
+  s6 -= s13 * 683901;
+  s13 = 0;
+
+  s0 += s12 * 666643;
+  s1 += s12 * 470296;
+  s2 += s12 * 654183;
+  s3 -= s12 * 997805;
+  s4 += s12 * 136657;
+  s5 -= s12 * 683901;
+  s12 = 0;
+
+  carry0 = (s0 + (1<<20)) >> 21; s1 += carry0; s0 -= carry0 << 21;
+  carry2 = (s2 + (1<<20)) >> 21; s3 += carry2; s2 -= carry2 << 21;
+  carry4 = (s4 + (1<<20)) >> 21; s5 += carry4; s4 -= carry4 << 21;
+  carry6 = (s6 + (1<<20)) >> 21; s7 += carry6; s6 -= carry6 << 21;
+  carry8 = (s8 + (1<<20)) >> 21; s9 += carry8; s8 -= carry8 << 21;
+  carry10 = (s10 + (1<<20)) >> 21; s11 += carry10; s10 -= carry10 << 21;
+
+  carry1 = (s1 + (1<<20)) >> 21; s2 += carry1; s1 -= carry1 << 21;
+  carry3 = (s3 + (1<<20)) >> 21; s4 += carry3; s3 -= carry3 << 21;
+  carry5 = (s5 + (1<<20)) >> 21; s6 += carry5; s5 -= carry5 << 21;
+  carry7 = (s7 + (1<<20)) >> 21; s8 += carry7; s7 -= carry7 << 21;
+  carry9 = (s9 + (1<<20)) >> 21; s10 += carry9; s9 -= carry9 << 21;
+  carry11 = (s11 + (1<<20)) >> 21; s12 += carry11; s11 -= carry11 << 21;
+
+  s0 += s12 * 666643;
+  s1 += s12 * 470296;
+  s2 += s12 * 654183;
+  s3 -= s12 * 997805;
+  s4 += s12 * 136657;
+  s5 -= s12 * 683901;
+  s12 = 0;
+
+  carry0 = s0 >> 21; s1 += carry0; s0 -= carry0 << 21;
+  carry1 = s1 >> 21; s2 += carry1; s1 -= carry1 << 21;
+  carry2 = s2 >> 21; s3 += carry2; s2 -= carry2 << 21;
+  carry3 = s3 >> 21; s4 += carry3; s3 -= carry3 << 21;
+  carry4 = s4 >> 21; s5 += carry4; s4 -= carry4 << 21;
+  carry5 = s5 >> 21; s6 += carry5; s5 -= carry5 << 21;
+  carry6 = s6 >> 21; s7 += carry6; s6 -= carry6 << 21;
+  carry7 = s7 >> 21; s8 += carry7; s7 -= carry7 << 21;
+  carry8 = s8 >> 21; s9 += carry8; s8 -= carry8 << 21;
+  carry9 = s9 >> 21; s10 += carry9; s9 -= carry9 << 21;
+  carry10 = s10 >> 21; s11 += carry10; s10 -= carry10 << 21;
+  carry11 = s11 >> 21; s12 += carry11; s11 -= carry11 << 21;
+
+  s0 += s12 * 666643;
+  s1 += s12 * 470296;
+  s2 += s12 * 654183;
+  s3 -= s12 * 997805;
+  s4 += s12 * 136657;
+  s5 -= s12 * 683901;
+  s12 = 0;
+
+  carry0 = s0 >> 21; s1 += carry0; s0 -= carry0 << 21;
+  carry1 = s1 >> 21; s2 += carry1; s1 -= carry1 << 21;
+  carry2 = s2 >> 21; s3 += carry2; s2 -= carry2 << 21;
+  carry3 = s3 >> 21; s4 += carry3; s3 -= carry3 << 21;
+  carry4 = s4 >> 21; s5 += carry4; s4 -= carry4 << 21;
+  carry5 = s5 >> 21; s6 += carry5; s5 -= carry5 << 21;
+  carry6 = s6 >> 21; s7 += carry6; s6 -= carry6 << 21;
+  carry7 = s7 >> 21; s8 += carry7; s7 -= carry7 << 21;
+  carry8 = s8 >> 21; s9 += carry8; s8 -= carry8 << 21;
+  carry9 = s9 >> 21; s10 += carry9; s9 -= carry9 << 21;
+  carry10 = s10 >> 21; s11 += carry10; s10 -= carry10 << 21;
+
+  s[0] = s0 >> 0;
+  s[1] = s0 >> 8;
+  s[2] = (s0 >> 16) | (s1 << 5);
+  s[3] = s1 >> 3;
+  s[4] = s1 >> 11;
+  s[5] = (s1 >> 19) | (s2 << 2);
+  s[6] = s2 >> 6;
+  s[7] = (s2 >> 14) | (s3 << 7);
+  s[8] = s3 >> 1;
+  s[9] = s3 >> 9;
+  s[10] = (s3 >> 17) | (s4 << 4);
+  s[11] = s4 >> 4;
+  s[12] = s4 >> 12;
+  s[13] = (s4 >> 20) | (s5 << 1);
+  s[14] = s5 >> 7;
+  s[15] = (s5 >> 15) | (s6 << 6);
+  s[16] = s6 >> 2;
+  s[17] = s6 >> 10;
+  s[18] = (s6 >> 18) | (s7 << 3);
+  s[19] = s7 >> 5;
+  s[20] = s7 >> 13;
+  s[21] = s8 >> 0;
+  s[22] = s8 >> 8;
+  s[23] = (s8 >> 16) | (s9 << 5);
+  s[24] = s9 >> 3;
+  s[25] = s9 >> 11;
+  s[26] = (s9 >> 19) | (s10 << 2);
+  s[27] = s10 >> 6;
+  s[28] = (s10 >> 14) | (s11 << 7);
+  s[29] = s11 >> 1;
+  s[30] = s11 >> 9;
+  s[31] = s11 >> 17;
+
+  /* hush warnings after setting values to 0 */
+  (void)s12;
+  (void)s13;
+  (void)s14;
+  (void)s15;
+  (void)s16;
+  (void)s17;
+  (void)s18;
+  (void)s19;
+  (void)s20;
+  (void)s21;
+  (void)s22;
+  (void)s23;
+}
+
+
+int ge_compress_key(byte* out, const byte* xIn, const byte* yIn, word32 keySz)
+{
+    fe     x,y,z;
+    ge_p3  g;
+    byte   bArray[keySz];
+    word32 i;
+
+    fe_0(x);
+    fe_0(y);
+    fe_1(z);
+    fe_frombytes(x, xIn);
+    fe_frombytes(y, yIn);
+
+    fe_copy(g.X, x);
+    fe_copy(g.Y, y);
+    fe_copy(g.Z, z);
+
+    ge_p3_tobytes(bArray, &g);
+
+    for (i = 0; i < keySz; i++) {
+        out[keySz - 1 - i] = bArray[i];
+    }
+
+    return 0;
+}
+
+
+/*
+r = p + q
+*/
+void ge_add(ge_p1p1 *r,const ge_p3 *p,const ge_cached *q)
+{
+	fe t0;
+	fe_add(r->X,p->Y,p->X);
+	fe_sub(r->Y,p->Y,p->X);
+	fe_mul(r->Z,r->X,q->YplusX);
+	fe_mul(r->Y,r->Y,q->YminusX);
+	fe_mul(r->T,q->T2d,p->T);
+	fe_mul(r->X,p->Z,q->Z);
+	fe_add(t0,r->X,r->X);
+	fe_sub(r->X,r->Z,r->Y);
+	fe_add(r->Y,r->Z,r->Y);
+	fe_add(r->Z,t0,r->T);
+	fe_sub(r->T,t0,r->T);
+}
+
+
+/* ge_scalar mult base */
+static unsigned char equal(signed char b,signed char c)
+{
+  unsigned char ub = b;
+  unsigned char uc = c;
+  unsigned char x = ub ^ uc; /* 0: yes; 1..255: no */
+  uint32_t y = x; /* 0: yes; 1..255: no */
+  y -= 1; /* 4294967295: yes; 0..254: no */
+  y >>= 31; /* 1: yes; 0: no */
+  return y;
+}
+
+
+static unsigned char negative(signed char b)
+{
+  unsigned long long x = b; /* 18446744073709551361..18446744073709551615:
+                               yes; 0..255: no */
+  x >>= 63; /* 1: yes; 0: no */
+  return x;
+}
+
+
+static void cmov(ge_precomp *t,ge_precomp *u,unsigned char b)
+{
+  fe_cmov(t->yplusx,u->yplusx,b);
+  fe_cmov(t->yminusx,u->yminusx,b);
+  fe_cmov(t->xy2d,u->xy2d,b);
+}
+
+
+/* base[i][j] = (j+1)*256^i*B */
+static ge_precomp base[32][8] = {
+{
+ {
+  { 25967493,-14356035,29566456,3660896,-12694345,4014787,27544626,-11754271,-6079156,2047605 },
+  { -12545711,934262,-2722910,3049990,-727428,9406986,12720692,5043384,19500929,-15469378 },
+  { -8738181,4489570,9688441,-14785194,10184609,-12363380,29287919,11864899,-24514362,-4438546 },
+ },
+ {
+  { -12815894,-12976347,-21581243,11784320,-25355658,-2750717,-11717903,-3814571,-358445,-10211303 },
+  { -21703237,6903825,27185491,6451973,-29577724,-9554005,-15616551,11189268,-26829678,-5319081 },
+  { 26966642,11152617,32442495,15396054,14353839,-12752335,-3128826,-9541118,-15472047,-4166697 },
+ },
+ {
+  { 15636291,-9688557,24204773,-7912398,616977,-16685262,27787600,-14772189,28944400,-1550024 },
+  { 16568933,4717097,-11556148,-1102322,15682896,-11807043,16354577,-11775962,7689662,11199574 },
+  { 30464156,-5976125,-11779434,-15670865,23220365,15915852,7512774,10017326,-17749093,-9920357 },
+ },
+ {
+  { -17036878,13921892,10945806,-6033431,27105052,-16084379,-28926210,15006023,3284568,-6276540 },
+  { 23599295,-8306047,-11193664,-7687416,13236774,10506355,7464579,9656445,13059162,10374397 },
+  { 7798556,16710257,3033922,2874086,28997861,2835604,32406664,-3839045,-641708,-101325 },
+ },
+ {
+  { 10861363,11473154,27284546,1981175,-30064349,12577861,32867885,14515107,-15438304,10819380 },
+  { 4708026,6336745,20377586,9066809,-11272109,6594696,-25653668,12483688,-12668491,5581306 },
+  { 19563160,16186464,-29386857,4097519,10237984,-4348115,28542350,13850243,-23678021,-15815942 },
+ },
+ {
+  { -15371964,-12862754,32573250,4720197,-26436522,5875511,-19188627,-15224819,-9818940,-12085777 },
+  { -8549212,109983,15149363,2178705,22900618,4543417,3044240,-15689887,1762328,14866737 },
+  { -18199695,-15951423,-10473290,1707278,-17185920,3916101,-28236412,3959421,27914454,4383652 },
+ },
+ {
+  { 5153746,9909285,1723747,-2777874,30523605,5516873,19480852,5230134,-23952439,-15175766 },
+  { -30269007,-3463509,7665486,10083793,28475525,1649722,20654025,16520125,30598449,7715701 },
+  { 28881845,14381568,9657904,3680757,-20181635,7843316,-31400660,1370708,29794553,-1409300 },
+ },
+ {
+  { 14499471,-2729599,-33191113,-4254652,28494862,14271267,30290735,10876454,-33154098,2381726 },
+  { -7195431,-2655363,-14730155,462251,-27724326,3941372,-6236617,3696005,-32300832,15351955 },
+  { 27431194,8222322,16448760,-3907995,-18707002,11938355,-32961401,-2970515,29551813,10109425 },
+ },
+},
+{
+ {
+  { -13657040,-13155431,-31283750,11777098,21447386,6519384,-2378284,-1627556,10092783,-4764171 },
+  { 27939166,14210322,4677035,16277044,-22964462,-12398139,-32508754,12005538,-17810127,12803510 },
+  { 17228999,-15661624,-1233527,300140,-1224870,-11714777,30364213,-9038194,18016357,4397660 },
+ },
+ {
+  { -10958843,-7690207,4776341,-14954238,27850028,-15602212,-26619106,14544525,-17477504,982639 },
+  { 29253598,15796703,-2863982,-9908884,10057023,3163536,7332899,-4120128,-21047696,9934963 },
+  { 5793303,16271923,-24131614,-10116404,29188560,1206517,-14747930,4559895,-30123922,-10897950 },
+ },
+ {
+  { -27643952,-11493006,16282657,-11036493,28414021,-15012264,24191034,4541697,-13338309,5500568 },
+  { 12650548,-1497113,9052871,11355358,-17680037,-8400164,-17430592,12264343,10874051,13524335 },
+  { 25556948,-3045990,714651,2510400,23394682,-10415330,33119038,5080568,-22528059,5376628 },
+ },
+ {
+  { -26088264,-4011052,-17013699,-3537628,-6726793,1920897,-22321305,-9447443,4535768,1569007 },
+  { -2255422,14606630,-21692440,-8039818,28430649,8775819,-30494562,3044290,31848280,12543772 },
+  { -22028579,2943893,-31857513,6777306,13784462,-4292203,-27377195,-2062731,7718482,14474653 },
+ },
+ {
+  { 2385315,2454213,-22631320,46603,-4437935,-15680415,656965,-7236665,24316168,-5253567 },
+  { 13741529,10911568,-33233417,-8603737,-20177830,-1033297,33040651,-13424532,-20729456,8321686 },
+  { 21060490,-2212744,15712757,-4336099,1639040,10656336,23845965,-11874838,-9984458,608372 },
+ },
+ {
+  { -13672732,-15087586,-10889693,-7557059,-6036909,11305547,1123968,-6780577,27229399,23887 },
+  { -23244140,-294205,-11744728,14712571,-29465699,-2029617,12797024,-6440308,-1633405,16678954 },
+  { -29500620,4770662,-16054387,14001338,7830047,9564805,-1508144,-4795045,-17169265,4904953 },
+ },
+ {
+  { 24059557,14617003,19037157,-15039908,19766093,-14906429,5169211,16191880,2128236,-4326833 },
+  { -16981152,4124966,-8540610,-10653797,30336522,-14105247,-29806336,916033,-6882542,-2986532 },
+  { -22630907,12419372,-7134229,-7473371,-16478904,16739175,285431,2763829,15736322,4143876 },
+ },
+ {
+  { 2379352,11839345,-4110402,-5988665,11274298,794957,212801,-14594663,23527084,-16458268 },
+  { 33431127,-11130478,-17838966,-15626900,8909499,8376530,-32625340,4087881,-15188911,-14416214 },
+  { 1767683,7197987,-13205226,-2022635,-13091350,448826,5799055,4357868,-4774191,-16323038 },
+ },
+},
+{
+ {
+  { 6721966,13833823,-23523388,-1551314,26354293,-11863321,23365147,-3949732,7390890,2759800 },
+  { 4409041,2052381,23373853,10530217,7676779,-12885954,21302353,-4264057,1244380,-12919645 },
+  { -4421239,7169619,4982368,-2957590,30256825,-2777540,14086413,9208236,15886429,16489664 },
+ },
+ {
+  { 1996075,10375649,14346367,13311202,-6874135,-16438411,-13693198,398369,-30606455,-712933 },
+  { -25307465,9795880,-2777414,14878809,-33531835,14780363,13348553,12076947,-30836462,5113182 },
+  { -17770784,11797796,31950843,13929123,-25888302,12288344,-30341101,-7336386,13847711,5387222 },
+ },
+ {
+  { -18582163,-3416217,17824843,-2340966,22744343,-10442611,8763061,3617786,-19600662,10370991 },
+  { 20246567,-14369378,22358229,-543712,18507283,-10413996,14554437,-8746092,32232924,16763880 },
+  { 9648505,10094563,26416693,14745928,-30374318,-6472621,11094161,15689506,3140038,-16510092 },
+ },
+ {
+  { -16160072,5472695,31895588,4744994,8823515,10365685,-27224800,9448613,-28774454,366295 },
+  { 19153450,11523972,-11096490,-6503142,-24647631,5420647,28344573,8041113,719605,11671788 },
+  { 8678025,2694440,-6808014,2517372,4964326,11152271,-15432916,-15266516,27000813,-10195553 },
+ },
+ {
+  { -15157904,7134312,8639287,-2814877,-7235688,10421742,564065,5336097,6750977,-14521026 },
+  { 11836410,-3979488,26297894,16080799,23455045,15735944,1695823,-8819122,8169720,16220347 },
+  { -18115838,8653647,17578566,-6092619,-8025777,-16012763,-11144307,-2627664,-5990708,-14166033 },
+ },
+ {
+  { -23308498,-10968312,15213228,-10081214,-30853605,-11050004,27884329,2847284,2655861,1738395 },
+  { -27537433,-14253021,-25336301,-8002780,-9370762,8129821,21651608,-3239336,-19087449,-11005278 },
+  { 1533110,3437855,23735889,459276,29970501,11335377,26030092,5821408,10478196,8544890 },
+ },
+ {
+  { 32173121,-16129311,24896207,3921497,22579056,-3410854,19270449,12217473,17789017,-3395995 },
+  { -30552961,-2228401,-15578829,-10147201,13243889,517024,15479401,-3853233,30460520,1052596 },
+  { -11614875,13323618,32618793,8175907,-15230173,12596687,27491595,-4612359,3179268,-9478891 },
+ },
+ {
+  { 31947069,-14366651,-4640583,-15339921,-15125977,-6039709,-14756777,-16411740,19072640,-9511060 },
+  { 11685058,11822410,3158003,-13952594,33402194,-4165066,5977896,-5215017,473099,5040608 },
+  { -20290863,8198642,-27410132,11602123,1290375,-2799760,28326862,1721092,-19558642,-3131606 },
+ },
+},
+{
+ {
+  { 7881532,10687937,7578723,7738378,-18951012,-2553952,21820786,8076149,-27868496,11538389 },
+  { -19935666,3899861,18283497,-6801568,-15728660,-11249211,8754525,7446702,-5676054,5797016 },
+  { -11295600,-3793569,-15782110,-7964573,12708869,-8456199,2014099,-9050574,-2369172,-5877341 },
+ },
+ {
+  { -22472376,-11568741,-27682020,1146375,18956691,16640559,1192730,-3714199,15123619,10811505 },
+  { 14352098,-3419715,-18942044,10822655,32750596,4699007,-70363,15776356,-28886779,-11974553 },
+  { -28241164,-8072475,-4978962,-5315317,29416931,1847569,-20654173,-16484855,4714547,-9600655 },
+ },
+ {
+  { 15200332,8368572,19679101,15970074,-31872674,1959451,24611599,-4543832,-11745876,12340220 },
+  { 12876937,-10480056,33134381,6590940,-6307776,14872440,9613953,8241152,15370987,9608631 },
+  { -4143277,-12014408,8446281,-391603,4407738,13629032,-7724868,15866074,-28210621,-8814099 },
+ },
+ {
+  { 26660628,-15677655,8393734,358047,-7401291,992988,-23904233,858697,20571223,8420556 },
+  { 14620715,13067227,-15447274,8264467,14106269,15080814,33531827,12516406,-21574435,-12476749 },
+  { 236881,10476226,57258,-14677024,6472998,2466984,17258519,7256740,8791136,15069930 },
+ },
+ {
+  { 1276410,-9371918,22949635,-16322807,-23493039,-5702186,14711875,4874229,-30663140,-2331391 },
+  { 5855666,4990204,-13711848,7294284,-7804282,1924647,-1423175,-7912378,-33069337,9234253 },
+  { 20590503,-9018988,31529744,-7352666,-2706834,10650548,31559055,-11609587,18979186,13396066 },
+ },
+ {
+  { 24474287,4968103,22267082,4407354,24063882,-8325180,-18816887,13594782,33514650,7021958 },
+  { -11566906,-6565505,-21365085,15928892,-26158305,4315421,-25948728,-3916677,-21480480,12868082 },
+  { -28635013,13504661,19988037,-2132761,21078225,6443208,-21446107,2244500,-12455797,-8089383 },
+ },
+ {
+  { -30595528,13793479,-5852820,319136,-25723172,-6263899,33086546,8957937,-15233648,5540521 },
+  { -11630176,-11503902,-8119500,-7643073,2620056,1022908,-23710744,-1568984,-16128528,-14962807 },
+  { 23152971,775386,27395463,14006635,-9701118,4649512,1689819,892185,-11513277,-15205948 },
+ },
+ {
+  { 9770129,9586738,26496094,4324120,1556511,-3550024,27453819,4763127,-19179614,5867134 },
+  { -32765025,1927590,31726409,-4753295,23962434,-16019500,27846559,5931263,-29749703,-16108455 },
+  { 27461885,-2977536,22380810,1815854,-23033753,-3031938,7283490,-15148073,-19526700,7734629 },
+ },
+},
+{
+ {
+  { -8010264,-9590817,-11120403,6196038,29344158,-13430885,7585295,-3176626,18549497,15302069 },
+  { -32658337,-6171222,-7672793,-11051681,6258878,13504381,10458790,-6418461,-8872242,8424746 },
+  { 24687205,8613276,-30667046,-3233545,1863892,-1830544,19206234,7134917,-11284482,-828919 },
+ },
+ {
+  { 11334899,-9218022,8025293,12707519,17523892,-10476071,10243738,-14685461,-5066034,16498837 },
+  { 8911542,6887158,-9584260,-6958590,11145641,-9543680,17303925,-14124238,6536641,10543906 },
+  { -28946384,15479763,-17466835,568876,-1497683,11223454,-2669190,-16625574,-27235709,8876771 },
+ },
+ {
+  { -25742899,-12566864,-15649966,-846607,-33026686,-796288,-33481822,15824474,-604426,-9039817 },
+  { 10330056,70051,7957388,-9002667,9764902,15609756,27698697,-4890037,1657394,3084098 },
+  { 10477963,-7470260,12119566,-13250805,29016247,-5365589,31280319,14396151,-30233575,15272409 },
+ },
+ {
+  { -12288309,3169463,28813183,16658753,25116432,-5630466,-25173957,-12636138,-25014757,1950504 },
+  { -26180358,9489187,11053416,-14746161,-31053720,5825630,-8384306,-8767532,15341279,8373727 },
+  { 28685821,7759505,-14378516,-12002860,-31971820,4079242,298136,-10232602,-2878207,15190420 },
+ },
+ {
+  { -32932876,13806336,-14337485,-15794431,-24004620,10940928,8669718,2742393,-26033313,-6875003 },
+  { -1580388,-11729417,-25979658,-11445023,-17411874,-10912854,9291594,-16247779,-12154742,6048605 },
+  { -30305315,14843444,1539301,11864366,20201677,1900163,13934231,5128323,11213262,9168384 },
+ },
+ {
+  { -26280513,11007847,19408960,-940758,-18592965,-4328580,-5088060,-11105150,20470157,-16398701 },
+  { -23136053,9282192,14855179,-15390078,-7362815,-14408560,-22783952,14461608,14042978,5230683 },
+  { 29969567,-2741594,-16711867,-8552442,9175486,-2468974,21556951,3506042,-5933891,-12449708 },
+ },
+ {
+  { -3144746,8744661,19704003,4581278,-20430686,6830683,-21284170,8971513,-28539189,15326563 },
+  { -19464629,10110288,-17262528,-3503892,-23500387,1355669,-15523050,15300988,-20514118,9168260 },
+  { -5353335,4488613,-23803248,16314347,7780487,-15638939,-28948358,9601605,33087103,-9011387 },
+ },
+ {
+  { -19443170,-15512900,-20797467,-12445323,-29824447,10229461,-27444329,-15000531,-5996870,15664672 },
+  { 23294591,-16632613,-22650781,-8470978,27844204,11461195,13099750,-2460356,18151676,13417686 },
+  { -24722913,-4176517,-31150679,5988919,-26858785,6685065,1661597,-12551441,15271676,-15452665 },
+ },
+},
+{
+ {
+  { 11433042,-13228665,8239631,-5279517,-1985436,-725718,-18698764,2167544,-6921301,-13440182 },
+  { -31436171,15575146,30436815,12192228,-22463353,9395379,-9917708,-8638997,12215110,12028277 },
+  { 14098400,6555944,23007258,5757252,-15427832,-12950502,30123440,4617780,-16900089,-655628 },
+ },
+ {
+  { -4026201,-15240835,11893168,13718664,-14809462,1847385,-15819999,10154009,23973261,-12684474 },
+  { -26531820,-3695990,-1908898,2534301,-31870557,-16550355,18341390,-11419951,32013174,-10103539 },
+  { -25479301,10876443,-11771086,-14625140,-12369567,1838104,21911214,6354752,4425632,-837822 },
+ },
+ {
+  { -10433389,-14612966,22229858,-3091047,-13191166,776729,-17415375,-12020462,4725005,14044970 },
+  { 19268650,-7304421,1555349,8692754,-21474059,-9910664,6347390,-1411784,-19522291,-16109756 },
+  { -24864089,12986008,-10898878,-5558584,-11312371,-148526,19541418,8180106,9282262,10282508 },
+ },
+ {
+  { -26205082,4428547,-8661196,-13194263,4098402,-14165257,15522535,8372215,5542595,-10702683 },
+  { -10562541,14895633,26814552,-16673850,-17480754,-2489360,-2781891,6993761,-18093885,10114655 },
+  { -20107055,-929418,31422704,10427861,-7110749,6150669,-29091755,-11529146,25953725,-106158 },
+ },
+ {
+  { -4234397,-8039292,-9119125,3046000,2101609,-12607294,19390020,6094296,-3315279,12831125 },
+  { -15998678,7578152,5310217,14408357,-33548620,-224739,31575954,6326196,7381791,-2421839 },
+  { -20902779,3296811,24736065,-16328389,18374254,7318640,6295303,8082724,-15362489,12339664 },
+ },
+ {
+  { 27724736,2291157,6088201,-14184798,1792727,5857634,13848414,15768922,25091167,14856294 },
+  { -18866652,8331043,24373479,8541013,-701998,-9269457,12927300,-12695493,-22182473,-9012899 },
+  { -11423429,-5421590,11632845,3405020,30536730,-11674039,-27260765,13866390,30146206,9142070 },
+ },
+ {
+  { 3924129,-15307516,-13817122,-10054960,12291820,-668366,-27702774,9326384,-8237858,4171294 },
+  { -15921940,16037937,6713787,16606682,-21612135,2790944,26396185,3731949,345228,-5462949 },
+  { -21327538,13448259,25284571,1143661,20614966,-8849387,2031539,-12391231,-16253183,-13582083 },
+ },
+ {
+  { 31016211,-16722429,26371392,-14451233,-5027349,14854137,17477601,3842657,28012650,-16405420 },
+  { -5075835,9368966,-8562079,-4600902,-15249953,6970560,-9189873,16292057,-8867157,3507940 },
+  { 29439664,3537914,23333589,6997794,-17555561,-11018068,-15209202,-15051267,-9164929,6580396 },
+ },
+},
+{
+ {
+  { -12185861,-7679788,16438269,10826160,-8696817,-6235611,17860444,-9273846,-2095802,9304567 },
+  { 20714564,-4336911,29088195,7406487,11426967,-5095705,14792667,-14608617,5289421,-477127 },
+  { -16665533,-10650790,-6160345,-13305760,9192020,-1802462,17271490,12349094,26939669,-3752294 },
+ },
+ {
+  { -12889898,9373458,31595848,16374215,21471720,13221525,-27283495,-12348559,-3698806,117887 },
+  { 22263325,-6560050,3984570,-11174646,-15114008,-566785,28311253,5358056,-23319780,541964 },
+  { 16259219,3261970,2309254,-15534474,-16885711,-4581916,24134070,-16705829,-13337066,-13552195 },
+ },
+ {
+  { 9378160,-13140186,-22845982,-12745264,28198281,-7244098,-2399684,-717351,690426,14876244 },
+  { 24977353,-314384,-8223969,-13465086,28432343,-1176353,-13068804,-12297348,-22380984,6618999 },
+  { -1538174,11685646,12944378,13682314,-24389511,-14413193,8044829,-13817328,32239829,-5652762 },
+ },
+ {
+  { -18603066,4762990,-926250,8885304,-28412480,-3187315,9781647,-10350059,32779359,5095274 },
+  { -33008130,-5214506,-32264887,-3685216,9460461,-9327423,-24601656,14506724,21639561,-2630236 },
+  { -16400943,-13112215,25239338,15531969,3987758,-4499318,-1289502,-6863535,17874574,558605 },
+ },
+ {
+  { -13600129,10240081,9171883,16131053,-20869254,9599700,33499487,5080151,2085892,5119761 },
+  { -22205145,-2519528,-16381601,414691,-25019550,2170430,30634760,-8363614,-31999993,-5759884 },
+  { -6845704,15791202,8550074,-1312654,29928809,-12092256,27534430,-7192145,-22351378,12961482 },
+ },
+ {
+  { -24492060,-9570771,10368194,11582341,-23397293,-2245287,16533930,8206996,-30194652,-5159638 },
+  { -11121496,-3382234,2307366,6362031,-135455,8868177,-16835630,7031275,7589640,8945490 },
+  { -32152748,8917967,6661220,-11677616,-1192060,-15793393,7251489,-11182180,24099109,-14456170 },
+ },
+ {
+  { 5019558,-7907470,4244127,-14714356,-26933272,6453165,-19118182,-13289025,-6231896,-10280736 },
+  { 10853594,10721687,26480089,5861829,-22995819,1972175,-1866647,-10557898,-3363451,-6441124 },
+  { -17002408,5906790,221599,-6563147,7828208,-13248918,24362661,-2008168,-13866408,7421392 },
+ },
+ {
+  { 8139927,-6546497,32257646,-5890546,30375719,1886181,-21175108,15441252,28826358,-4123029 },
+  { 6267086,9695052,7709135,-16603597,-32869068,-1886135,14795160,-7840124,13746021,-1742048 },
+  { 28584902,7787108,-6732942,-15050729,22846041,-7571236,-3181936,-363524,4771362,-8419958 },
+ },
+},
+{
+ {
+  { 24949256,6376279,-27466481,-8174608,-18646154,-9930606,33543569,-12141695,3569627,11342593 },
+  { 26514989,4740088,27912651,3697550,19331575,-11472339,6809886,4608608,7325975,-14801071 },
+  { -11618399,-14554430,-24321212,7655128,-1369274,5214312,-27400540,10258390,-17646694,-8186692 },
+ },
+ {
+  { 11431204,15823007,26570245,14329124,18029990,4796082,-31446179,15580664,9280358,-3973687 },
+  { -160783,-10326257,-22855316,-4304997,-20861367,-13621002,-32810901,-11181622,-15545091,4387441 },
+  { -20799378,12194512,3937617,-5805892,-27154820,9340370,-24513992,8548137,20617071,-7482001 },
+ },
+ {
+  { -938825,-3930586,-8714311,16124718,24603125,-6225393,-13775352,-11875822,24345683,10325460 },
+  { -19855277,-1568885,-22202708,8714034,14007766,6928528,16318175,-1010689,4766743,3552007 },
+  { -21751364,-16730916,1351763,-803421,-4009670,3950935,3217514,14481909,10988822,-3994762 },
+ },
+ {
+  { 15564307,-14311570,3101243,5684148,30446780,-8051356,12677127,-6505343,-8295852,13296005 },
+  { -9442290,6624296,-30298964,-11913677,-4670981,-2057379,31521204,9614054,-30000824,12074674 },
+  { 4771191,-135239,14290749,-13089852,27992298,14998318,-1413936,-1556716,29832613,-16391035 },
+ },
+ {
+  { 7064884,-7541174,-19161962,-5067537,-18891269,-2912736,25825242,5293297,-27122660,13101590 },
+  { -2298563,2439670,-7466610,1719965,-27267541,-16328445,32512469,-5317593,-30356070,-4190957 },
+  { -30006540,10162316,-33180176,3981723,-16482138,-13070044,14413974,9515896,19568978,9628812 },
+ },
+ {
+  { 33053803,199357,15894591,1583059,27380243,-4580435,-17838894,-6106839,-6291786,3437740 },
+  { -18978877,3884493,19469877,12726490,15913552,13614290,-22961733,70104,7463304,4176122 },
+  { -27124001,10659917,11482427,-16070381,12771467,-6635117,-32719404,-5322751,24216882,5944158 },
+ },
+ {
+  { 8894125,7450974,-2664149,-9765752,-28080517,-12389115,19345746,14680796,11632993,5847885 },
+  { 26942781,-2315317,9129564,-4906607,26024105,11769399,-11518837,6367194,-9727230,4782140 },
+  { 19916461,-4828410,-22910704,-11414391,25606324,-5972441,33253853,8220911,6358847,-1873857 },
+ },
+ {
+  { 801428,-2081702,16569428,11065167,29875704,96627,7908388,-4480480,-13538503,1387155 },
+  { 19646058,5720633,-11416706,12814209,11607948,12749789,14147075,15156355,-21866831,11835260 },
+  { 19299512,1155910,28703737,14890794,2925026,7269399,26121523,15467869,-26560550,5052483 },
+ },
+},
+{
+ {
+  { -3017432,10058206,1980837,3964243,22160966,12322533,-6431123,-12618185,12228557,-7003677 },
+  { 32944382,14922211,-22844894,5188528,21913450,-8719943,4001465,13238564,-6114803,8653815 },
+  { 22865569,-4652735,27603668,-12545395,14348958,8234005,24808405,5719875,28483275,2841751 },
+ },
+ {
+  { -16420968,-1113305,-327719,-12107856,21886282,-15552774,-1887966,-315658,19932058,-12739203 },
+  { -11656086,10087521,-8864888,-5536143,-19278573,-3055912,3999228,13239134,-4777469,-13910208 },
+  { 1382174,-11694719,17266790,9194690,-13324356,9720081,20403944,11284705,-14013818,3093230 },
+ },
+ {
+  { 16650921,-11037932,-1064178,1570629,-8329746,7352753,-302424,16271225,-24049421,-6691850 },
+  { -21911077,-5927941,-4611316,-5560156,-31744103,-10785293,24123614,15193618,-21652117,-16739389 },
+  { -9935934,-4289447,-25279823,4372842,2087473,10399484,31870908,14690798,17361620,11864968 },
+ },
+ {
+  { -11307610,6210372,13206574,5806320,-29017692,-13967200,-12331205,-7486601,-25578460,-16240689 },
+  { 14668462,-12270235,26039039,15305210,25515617,4542480,10453892,6577524,9145645,-6443880 },
+  { 5974874,3053895,-9433049,-10385191,-31865124,3225009,-7972642,3936128,-5652273,-3050304 },
+ },
+ {
+  { 30625386,-4729400,-25555961,-12792866,-20484575,7695099,17097188,-16303496,-27999779,1803632 },
+  { -3553091,9865099,-5228566,4272701,-5673832,-16689700,14911344,12196514,-21405489,7047412 },
+  { 20093277,9920966,-11138194,-5343857,13161587,12044805,-32856851,4124601,-32343828,-10257566 },
+ },
+ {
+  { -20788824,14084654,-13531713,7842147,19119038,-13822605,4752377,-8714640,-21679658,2288038 },
+  { -26819236,-3283715,29965059,3039786,-14473765,2540457,29457502,14625692,-24819617,12570232 },
+  { -1063558,-11551823,16920318,12494842,1278292,-5869109,-21159943,-3498680,-11974704,4724943 },
+ },
+ {
+  { 17960970,-11775534,-4140968,-9702530,-8876562,-1410617,-12907383,-8659932,-29576300,1903856 },
+  { 23134274,-14279132,-10681997,-1611936,20684485,15770816,-12989750,3190296,26955097,14109738 },
+  { 15308788,5320727,-30113809,-14318877,22902008,7767164,29425325,-11277562,31960942,11934971 },
+ },
+ {
+  { -27395711,8435796,4109644,12222639,-24627868,14818669,20638173,4875028,10491392,1379718 },
+  { -13159415,9197841,3875503,-8936108,-1383712,-5879801,33518459,16176658,21432314,12180697 },
+  { -11787308,11500838,13787581,-13832590,-22430679,10140205,1465425,12689540,-10301319,-13872883 },
+ },
+},
+{
+ {
+  { 5414091,-15386041,-21007664,9643570,12834970,1186149,-2622916,-1342231,26128231,6032912 },
+  { -26337395,-13766162,32496025,-13653919,17847801,-12669156,3604025,8316894,-25875034,-10437358 },
+  { 3296484,6223048,24680646,-12246460,-23052020,5903205,-8862297,-4639164,12376617,3188849 },
+ },
+ {
+  { 29190488,-14659046,27549113,-1183516,3520066,-10697301,32049515,-7309113,-16109234,-9852307 },
+  { -14744486,-9309156,735818,-598978,-20407687,-5057904,25246078,-15795669,18640741,-960977 },
+  { -6928835,-16430795,10361374,5642961,4910474,12345252,-31638386,-494430,10530747,1053335 },
+ },
+ {
+  { -29265967,-14186805,-13538216,-12117373,-19457059,-10655384,-31462369,-2948985,24018831,15026644 },
+  { -22592535,-3145277,-2289276,5953843,-13440189,9425631,25310643,13003497,-2314791,-15145616 },
+  { -27419985,-603321,-8043984,-1669117,-26092265,13987819,-27297622,187899,-23166419,-2531735 },
+ },
+ {
+  { -21744398,-13810475,1844840,5021428,-10434399,-15911473,9716667,16266922,-5070217,726099 },
+  { 29370922,-6053998,7334071,-15342259,9385287,2247707,-13661962,-4839461,30007388,-15823341 },
+  { -936379,16086691,23751945,-543318,-1167538,-5189036,9137109,730663,9835848,4555336 },
+ },
+ {
+  { -23376435,1410446,-22253753,-12899614,30867635,15826977,17693930,544696,-11985298,12422646 },
+  { 31117226,-12215734,-13502838,6561947,-9876867,-12757670,-5118685,-4096706,29120153,13924425 },
+  { -17400879,-14233209,19675799,-2734756,-11006962,-5858820,-9383939,-11317700,7240931,-237388 },
+ },
+ {
+  { -31361739,-11346780,-15007447,-5856218,-22453340,-12152771,1222336,4389483,3293637,-15551743 },
+  { -16684801,-14444245,11038544,11054958,-13801175,-3338533,-24319580,7733547,12796905,-6335822 },
+  { -8759414,-10817836,-25418864,10783769,-30615557,-9746811,-28253339,3647836,3222231,-11160462 },
+ },
+ {
+  { 18606113,1693100,-25448386,-15170272,4112353,10045021,23603893,-2048234,-7550776,2484985 },
+  { 9255317,-3131197,-12156162,-1004256,13098013,-9214866,16377220,-2102812,-19802075,-3034702 },
+  { -22729289,7496160,-5742199,11329249,19991973,-3347502,-31718148,9936966,-30097688,-10618797 },
+ },
+ {
+  { 21878590,-5001297,4338336,13643897,-3036865,13160960,19708896,5415497,-7360503,-4109293 },
+  { 27736861,10103576,12500508,8502413,-3413016,-9633558,10436918,-1550276,-23659143,-8132100 },
+  { 19492550,-12104365,-29681976,-852630,-3208171,12403437,30066266,8367329,13243957,8709688 },
+ },
+},
+{
+ {
+  { 12015105,2801261,28198131,10151021,24818120,-4743133,-11194191,-5645734,5150968,7274186 },
+  { 2831366,-12492146,1478975,6122054,23825128,-12733586,31097299,6083058,31021603,-9793610 },
+  { -2529932,-2229646,445613,10720828,-13849527,-11505937,-23507731,16354465,15067285,-14147707 },
+ },
+ {
+  { 7840942,14037873,-33364863,15934016,-728213,-3642706,21403988,1057586,-19379462,-12403220 },
+  { 915865,-16469274,15608285,-8789130,-24357026,6060030,-17371319,8410997,-7220461,16527025 },
+  { 32922597,-556987,20336074,-16184568,10903705,-5384487,16957574,52992,23834301,6588044 },
+ },
+ {
+  { 32752030,11232950,3381995,-8714866,22652988,-10744103,17159699,16689107,-20314580,-1305992 },
+  { -4689649,9166776,-25710296,-10847306,11576752,12733943,7924251,-2752281,1976123,-7249027 },
+  { 21251222,16309901,-2983015,-6783122,30810597,12967303,156041,-3371252,12331345,-8237197 },
+ },
+ {
+  { 8651614,-4477032,-16085636,-4996994,13002507,2950805,29054427,-5106970,10008136,-4667901 },
+  { 31486080,15114593,-14261250,12951354,14369431,-7387845,16347321,-13662089,8684155,-10532952 },
+  { 19443825,11385320,24468943,-9659068,-23919258,2187569,-26263207,-6086921,31316348,14219878 },
+ },
+ {
+  { -28594490,1193785,32245219,11392485,31092169,15722801,27146014,6992409,29126555,9207390 },
+  { 32382935,1110093,18477781,11028262,-27411763,-7548111,-4980517,10843782,-7957600,-14435730 },
+  { 2814918,7836403,27519878,-7868156,-20894015,-11553689,-21494559,8550130,28346258,1994730 },
+ },
+ {
+  { -19578299,8085545,-14000519,-3948622,2785838,-16231307,-19516951,7174894,22628102,8115180 },
+  { -30405132,955511,-11133838,-15078069,-32447087,-13278079,-25651578,3317160,-9943017,930272 },
+  { -15303681,-6833769,28856490,1357446,23421993,1057177,24091212,-1388970,-22765376,-10650715 },
+ },
+ {
+  { -22751231,-5303997,-12907607,-12768866,-15811511,-7797053,-14839018,-16554220,-1867018,8398970 },
+  { -31969310,2106403,-4736360,1362501,12813763,16200670,22981545,-6291273,18009408,-15772772 },
+  { -17220923,-9545221,-27784654,14166835,29815394,7444469,29551787,-3727419,19288549,1325865 },
+ },
+ {
+  { 15100157,-15835752,-23923978,-1005098,-26450192,15509408,12376730,-3479146,33166107,-8042750 },
+  { 20909231,13023121,-9209752,16251778,-5778415,-8094914,12412151,10018715,2213263,-13878373 },
+  { 32529814,-11074689,30361439,-16689753,-9135940,1513226,22922121,6382134,-5766928,8371348 },
+ },
+},
+{
+ {
+  { 9923462,11271500,12616794,3544722,-29998368,-1721626,12891687,-8193132,-26442943,10486144 },
+  { -22597207,-7012665,8587003,-8257861,4084309,-12970062,361726,2610596,-23921530,-11455195 },
+  { 5408411,-1136691,-4969122,10561668,24145918,14240566,31319731,-4235541,19985175,-3436086 },
+ },
+ {
+  { -13994457,16616821,14549246,3341099,32155958,13648976,-17577068,8849297,65030,8370684 },
+  { -8320926,-12049626,31204563,5839400,-20627288,-1057277,-19442942,6922164,12743482,-9800518 },
+  { -2361371,12678785,28815050,4759974,-23893047,4884717,23783145,11038569,18800704,255233 },
+ },
+ {
+  { -5269658,-1773886,13957886,7990715,23132995,728773,13393847,9066957,19258688,-14753793 },
+  { -2936654,-10827535,-10432089,14516793,-3640786,4372541,-31934921,2209390,-1524053,2055794 },
+  { 580882,16705327,5468415,-2683018,-30926419,-14696000,-7203346,-8994389,-30021019,7394435 },
+ },
+ {
+  { 23838809,1822728,-15738443,15242727,8318092,-3733104,-21672180,-3492205,-4821741,14799921 },
+  { 13345610,9759151,3371034,-16137791,16353039,8577942,31129804,13496856,-9056018,7402518 },
+  { 2286874,-4435931,-20042458,-2008336,-13696227,5038122,11006906,-15760352,8205061,1607563 },
+ },
+ {
+  { 14414086,-8002132,3331830,-3208217,22249151,-5594188,18364661,-2906958,30019587,-9029278 },
+  { -27688051,1585953,-10775053,931069,-29120221,-11002319,-14410829,12029093,9944378,8024 },
+  { 4368715,-3709630,29874200,-15022983,-20230386,-11410704,-16114594,-999085,-8142388,5640030 },
+ },
+ {
+  { 10299610,13746483,11661824,16234854,7630238,5998374,9809887,-16694564,15219798,-14327783 },
+  { 27425505,-5719081,3055006,10660664,23458024,595578,-15398605,-1173195,-18342183,9742717 },
+  { 6744077,2427284,26042789,2720740,-847906,1118974,32324614,7406442,12420155,1994844 },
+ },
+ {
+  { 14012521,-5024720,-18384453,-9578469,-26485342,-3936439,-13033478,-10909803,24319929,-6446333 },
+  { 16412690,-4507367,10772641,15929391,-17068788,-4658621,10555945,-10484049,-30102368,-4739048 },
+  { 22397382,-7767684,-9293161,-12792868,17166287,-9755136,-27333065,6199366,21880021,-12250760 },
+ },
+ {
+  { -4283307,5368523,-31117018,8163389,-30323063,3209128,16557151,8890729,8840445,4957760 },
+  { -15447727,709327,-6919446,-10870178,-29777922,6522332,-21720181,12130072,-14796503,5005757 },
+  { -2114751,-14308128,23019042,15765735,-25269683,6002752,10183197,-13239326,-16395286,-2176112 },
+ },
+},
+{
+ {
+  { -19025756,1632005,13466291,-7995100,-23640451,16573537,-32013908,-3057104,22208662,2000468 },
+  { 3065073,-1412761,-25598674,-361432,-17683065,-5703415,-8164212,11248527,-3691214,-7414184 },
+  { 10379208,-6045554,8877319,1473647,-29291284,-12507580,16690915,2553332,-3132688,16400289 },
+ },
+ {
+  { 15716668,1254266,-18472690,7446274,-8448918,6344164,-22097271,-7285580,26894937,9132066 },
+  { 24158887,12938817,11085297,-8177598,-28063478,-4457083,-30576463,64452,-6817084,-2692882 },
+  { 13488534,7794716,22236231,5989356,25426474,-12578208,2350710,-3418511,-4688006,2364226 },
+ },
+ {
+  { 16335052,9132434,25640582,6678888,1725628,8517937,-11807024,-11697457,15445875,-7798101 },
+  { 29004207,-7867081,28661402,-640412,-12794003,-7943086,31863255,-4135540,-278050,-15759279 },
+  { -6122061,-14866665,-28614905,14569919,-10857999,-3591829,10343412,-6976290,-29828287,-10815811 },
+ },
+ {
+  { 27081650,3463984,14099042,-4517604,1616303,-6205604,29542636,15372179,17293797,960709 },
+  { 20263915,11434237,-5765435,11236810,13505955,-10857102,-16111345,6493122,-19384511,7639714 },
+  { -2830798,-14839232,25403038,-8215196,-8317012,-16173699,18006287,-16043750,29994677,-15808121 },
+ },
+ {
+  { 9769828,5202651,-24157398,-13631392,-28051003,-11561624,-24613141,-13860782,-31184575,709464 },
+  { 12286395,13076066,-21775189,-1176622,-25003198,4057652,-32018128,-8890874,16102007,13205847 },
+  { 13733362,5599946,10557076,3195751,-5557991,8536970,-25540170,8525972,10151379,10394400 },
+ },
+ {
+  { 4024660,-16137551,22436262,12276534,-9099015,-2686099,19698229,11743039,-33302334,8934414 },
+  { -15879800,-4525240,-8580747,-2934061,14634845,-698278,-9449077,3137094,-11536886,11721158 },
+  { 17555939,-5013938,8268606,2331751,-22738815,9761013,9319229,8835153,-9205489,-1280045 },
+ },
+ {
+  { -461409,-7830014,20614118,16688288,-7514766,-4807119,22300304,505429,6108462,-6183415 },
+  { -5070281,12367917,-30663534,3234473,32617080,-8422642,29880583,-13483331,-26898490,-7867459 },
+  { -31975283,5726539,26934134,10237677,-3173717,-605053,24199304,3795095,7592688,-14992079 },
+ },
+ {
+  { 21594432,-14964228,17466408,-4077222,32537084,2739898,6407723,12018833,-28256052,4298412 },
+  { -20650503,-11961496,-27236275,570498,3767144,-1717540,13891942,-1569194,13717174,10805743 },
+  { -14676630,-15644296,15287174,11927123,24177847,-8175568,-796431,14860609,-26938930,-5863836 },
+ },
+},
+{
+ {
+  { 12962541,5311799,-10060768,11658280,18855286,-7954201,13286263,-12808704,-4381056,9882022 },
+  { 18512079,11319350,-20123124,15090309,18818594,5271736,-22727904,3666879,-23967430,-3299429 },
+  { -6789020,-3146043,16192429,13241070,15898607,-14206114,-10084880,-6661110,-2403099,5276065 },
+ },
+ {
+  { 30169808,-5317648,26306206,-11750859,27814964,7069267,7152851,3684982,1449224,13082861 },
+  { 10342826,3098505,2119311,193222,25702612,12233820,23697382,15056736,-21016438,-8202000 },
+  { -33150110,3261608,22745853,7948688,19370557,-15177665,-26171976,6482814,-10300080,-11060101 },
+ },
+ {
+  { 32869458,-5408545,25609743,15678670,-10687769,-15471071,26112421,2521008,-22664288,6904815 },
+  { 29506923,4457497,3377935,-9796444,-30510046,12935080,1561737,3841096,-29003639,-6657642 },
+  { 10340844,-6630377,-18656632,-2278430,12621151,-13339055,30878497,-11824370,-25584551,5181966 },
+ },
+ {
+  { 25940115,-12658025,17324188,-10307374,-8671468,15029094,24396252,-16450922,-2322852,-12388574 },
+  { -21765684,9916823,-1300409,4079498,-1028346,11909559,1782390,12641087,20603771,-6561742 },
+  { -18882287,-11673380,24849422,11501709,13161720,-4768874,1925523,11914390,4662781,7820689 },
+ },
+ {
+  { 12241050,-425982,8132691,9393934,32846760,-1599620,29749456,12172924,16136752,15264020 },
+  { -10349955,-14680563,-8211979,2330220,-17662549,-14545780,10658213,6671822,19012087,3772772 },
+  { 3753511,-3421066,10617074,2028709,14841030,-6721664,28718732,-15762884,20527771,12988982 },
+ },
+ {
+  { -14822485,-5797269,-3707987,12689773,-898983,-10914866,-24183046,-10564943,3299665,-12424953 },
+  { -16777703,-15253301,-9642417,4978983,3308785,8755439,6943197,6461331,-25583147,8991218 },
+  { -17226263,1816362,-1673288,-6086439,31783888,-8175991,-32948145,7417950,-30242287,1507265 },
+ },
+ {
+  { 29692663,6829891,-10498800,4334896,20945975,-11906496,-28887608,8209391,14606362,-10647073 },
+  { -3481570,8707081,32188102,5672294,22096700,1711240,-33020695,9761487,4170404,-2085325 },
+  { -11587470,14855945,-4127778,-1531857,-26649089,15084046,22186522,16002000,-14276837,-8400798 },
+ },
+ {
+  { -4811456,13761029,-31703877,-2483919,-3312471,7869047,-7113572,-9620092,13240845,10965870 },
+  { -7742563,-8256762,-14768334,-13656260,-23232383,12387166,4498947,14147411,29514390,4302863 },
+  { -13413405,-12407859,20757302,-13801832,14785143,8976368,-5061276,-2144373,17846988,-13971927 },
+ },
+},
+{
+ {
+  { -2244452,-754728,-4597030,-1066309,-6247172,1455299,-21647728,-9214789,-5222701,12650267 },
+  { -9906797,-16070310,21134160,12198166,-27064575,708126,387813,13770293,-19134326,10958663 },
+  { 22470984,12369526,23446014,-5441109,-21520802,-9698723,-11772496,-11574455,-25083830,4271862 },
+ },
+ {
+  { -25169565,-10053642,-19909332,15361595,-5984358,2159192,75375,-4278529,-32526221,8469673 },
+  { 15854970,4148314,-8893890,7259002,11666551,13824734,-30531198,2697372,24154791,-9460943 },
+  { 15446137,-15806644,29759747,14019369,30811221,-9610191,-31582008,12840104,24913809,9815020 },
+ },
+ {
+  { -4709286,-5614269,-31841498,-12288893,-14443537,10799414,-9103676,13438769,18735128,9466238 },
+  { 11933045,9281483,5081055,-5183824,-2628162,-4905629,-7727821,-10896103,-22728655,16199064 },
+  { 14576810,379472,-26786533,-8317236,-29426508,-10812974,-102766,1876699,30801119,2164795 },
+ },
+ {
+  { 15995086,3199873,13672555,13712240,-19378835,-4647646,-13081610,-15496269,-13492807,1268052 },
+  { -10290614,-3659039,-3286592,10948818,23037027,3794475,-3470338,-12600221,-17055369,3565904 },
+  { 29210088,-9419337,-5919792,-4952785,10834811,-13327726,-16512102,-10820713,-27162222,-14030531 },
+ },
+ {
+  { -13161890,15508588,16663704,-8156150,-28349942,9019123,-29183421,-3769423,2244111,-14001979 },
+  { -5152875,-3800936,-9306475,-6071583,16243069,14684434,-25673088,-16180800,13491506,4641841 },
+  { 10813417,643330,-19188515,-728916,30292062,-16600078,27548447,-7721242,14476989,-12767431 },
+ },
+ {
+  { 10292079,9984945,6481436,8279905,-7251514,7032743,27282937,-1644259,-27912810,12651324 },
+  { -31185513,-813383,22271204,11835308,10201545,15351028,17099662,3988035,21721536,-3148940 },
+  { 10202177,-6545839,-31373232,-9574638,-32150642,-8119683,-12906320,3852694,13216206,14842320 },
+ },
+ {
+  { -15815640,-10601066,-6538952,-7258995,-6984659,-6581778,-31500847,13765824,-27434397,9900184 },
+  { 14465505,-13833331,-32133984,-14738873,-27443187,12990492,33046193,15796406,-7051866,-8040114 },
+  { 30924417,-8279620,6359016,-12816335,16508377,9071735,-25488601,15413635,9524356,-7018878 },
+ },
+ {
+  { 12274201,-13175547,32627641,-1785326,6736625,13267305,5237659,-5109483,15663516,4035784 },
+  { -2951309,8903985,17349946,601635,-16432815,-4612556,-13732739,-15889334,-22258478,4659091 },
+  { -16916263,-4952973,-30393711,-15158821,20774812,15897498,5736189,15026997,-2178256,-13455585 },
+ },
+},
+{
+ {
+  { -8858980,-2219056,28571666,-10155518,-474467,-10105698,-3801496,278095,23440562,-290208 },
+  { 10226241,-5928702,15139956,120818,-14867693,5218603,32937275,11551483,-16571960,-7442864 },
+  { 17932739,-12437276,-24039557,10749060,11316803,7535897,22503767,5561594,-3646624,3898661 },
+ },
+ {
+  { 7749907,-969567,-16339731,-16464,-25018111,15122143,-1573531,7152530,21831162,1245233 },
+  { 26958459,-14658026,4314586,8346991,-5677764,11960072,-32589295,-620035,-30402091,-16716212 },
+  { -12165896,9166947,33491384,13673479,29787085,13096535,6280834,14587357,-22338025,13987525 },
+ },
+ {
+  { -24349909,7778775,21116000,15572597,-4833266,-5357778,-4300898,-5124639,-7469781,-2858068 },
+  { 9681908,-6737123,-31951644,13591838,-6883821,386950,31622781,6439245,-14581012,4091397 },
+  { -8426427,1470727,-28109679,-1596990,3978627,-5123623,-19622683,12092163,29077877,-14741988 },
+ },
+ {
+  { 5269168,-6859726,-13230211,-8020715,25932563,1763552,-5606110,-5505881,-20017847,2357889 },
+  { 32264008,-15407652,-5387735,-1160093,-2091322,-3946900,23104804,-12869908,5727338,189038 },
+  { 14609123,-8954470,-6000566,-16622781,-14577387,-7743898,-26745169,10942115,-25888931,-14884697 },
+ },
+ {
+  { 20513500,5557931,-15604613,7829531,26413943,-2019404,-21378968,7471781,13913677,-5137875 },
+  { -25574376,11967826,29233242,12948236,-6754465,4713227,-8940970,14059180,12878652,8511905 },
+  { -25656801,3393631,-2955415,-7075526,-2250709,9366908,-30223418,6812974,5568676,-3127656 },
+ },
+ {
+  { 11630004,12144454,2116339,13606037,27378885,15676917,-17408753,-13504373,-14395196,8070818 },
+  { 27117696,-10007378,-31282771,-5570088,1127282,12772488,-29845906,10483306,-11552749,-1028714 },
+  { 10637467,-5688064,5674781,1072708,-26343588,-6982302,-1683975,9177853,-27493162,15431203 },
+ },
+ {
+  { 20525145,10892566,-12742472,12779443,-29493034,16150075,-28240519,14943142,-15056790,-7935931 },
+  { -30024462,5626926,-551567,-9981087,753598,11981191,25244767,-3239766,-3356550,9594024 },
+  { -23752644,2636870,-5163910,-10103818,585134,7877383,11345683,-6492290,13352335,-10977084 },
+ },
+ {
+  { -1931799,-5407458,3304649,-12884869,17015806,-4877091,-29783850,-7752482,-13215537,-319204 },
+  { 20239939,6607058,6203985,3483793,-18386976,-779229,-20723742,15077870,-22750759,14523817 },
+  { 27406042,-6041657,27423596,-4497394,4996214,10002360,-28842031,-4545494,-30172742,-4805667 },
+ },
+},
+{
+ {
+  { 11374242,12660715,17861383,-12540833,10935568,1099227,-13886076,-9091740,-27727044,11358504 },
+  { -12730809,10311867,1510375,10778093,-2119455,-9145702,32676003,11149336,-26123651,4985768 },
+  { -19096303,341147,-6197485,-239033,15756973,-8796662,-983043,13794114,-19414307,-15621255 },
+ },
+ {
+  { 6490081,11940286,25495923,-7726360,8668373,-8751316,3367603,6970005,-1691065,-9004790 },
+  { 1656497,13457317,15370807,6364910,13605745,8362338,-19174622,-5475723,-16796596,-5031438 },
+  { -22273315,-13524424,-64685,-4334223,-18605636,-10921968,-20571065,-7007978,-99853,-10237333 },
+ },
+ {
+  { 17747465,10039260,19368299,-4050591,-20630635,-16041286,31992683,-15857976,-29260363,-5511971 },
+  { 31932027,-4986141,-19612382,16366580,22023614,88450,11371999,-3744247,4882242,-10626905 },
+  { 29796507,37186,19818052,10115756,-11829032,3352736,18551198,3272828,-5190932,-4162409 },
+ },
+ {
+  { 12501286,4044383,-8612957,-13392385,-32430052,5136599,-19230378,-3529697,330070,-3659409 },
+  { 6384877,2899513,17807477,7663917,-2358888,12363165,25366522,-8573892,-271295,12071499 },
+  { -8365515,-4042521,25133448,-4517355,-6211027,2265927,-32769618,1936675,-5159697,3829363 },
+ },
+ {
+  { 28425966,-5835433,-577090,-4697198,-14217555,6870930,7921550,-6567787,26333140,14267664 },
+  { -11067219,11871231,27385719,-10559544,-4585914,-11189312,10004786,-8709488,-21761224,8930324 },
+  { -21197785,-16396035,25654216,-1725397,12282012,11008919,1541940,4757911,-26491501,-16408940 },
+ },
+ {
+  { 13537262,-7759490,-20604840,10961927,-5922820,-13218065,-13156584,6217254,-15943699,13814990 },
+  { -17422573,15157790,18705543,29619,24409717,-260476,27361681,9257833,-1956526,-1776914 },
+  { -25045300,-10191966,15366585,15166509,-13105086,8423556,-29171540,12361135,-18685978,4578290 },
+ },
+ {
+  { 24579768,3711570,1342322,-11180126,-27005135,14124956,-22544529,14074919,21964432,8235257 },
+  { -6528613,-2411497,9442966,-5925588,12025640,-1487420,-2981514,-1669206,13006806,2355433 },
+  { -16304899,-13605259,-6632427,-5142349,16974359,-10911083,27202044,1719366,1141648,-12796236 },
+ },
+ {
+  { -12863944,-13219986,-8318266,-11018091,-6810145,-4843894,13475066,-3133972,32674895,13715045 },
+  { 11423335,-5468059,32344216,8962751,24989809,9241752,-13265253,16086212,-28740881,-15642093 },
+  { -1409668,12530728,-6368726,10847387,19531186,-14132160,-11709148,7791794,-27245943,4383347 },
+ },
+},
+{
+ {
+  { -28970898,5271447,-1266009,-9736989,-12455236,16732599,-4862407,-4906449,27193557,6245191 },
+  { -15193956,5362278,-1783893,2695834,4960227,12840725,23061898,3260492,22510453,8577507 },
+  { -12632451,11257346,-32692994,13548177,-721004,10879011,31168030,13952092,-29571492,-3635906 },
+ },
+ {
+  { 3877321,-9572739,32416692,5405324,-11004407,-13656635,3759769,11935320,5611860,8164018 },
+  { -16275802,14667797,15906460,12155291,-22111149,-9039718,32003002,-8832289,5773085,-8422109 },
+  { -23788118,-8254300,1950875,8937633,18686727,16459170,-905725,12376320,31632953,190926 },
+ },
+ {
+  { -24593607,-16138885,-8423991,13378746,14162407,6901328,-8288749,4508564,-25341555,-3627528 },
+  { 8884438,-5884009,6023974,10104341,-6881569,-4941533,18722941,-14786005,-1672488,827625 },
+  { -32720583,-16289296,-32503547,7101210,13354605,2659080,-1800575,-14108036,-24878478,1541286 },
+ },
+ {
+  { 2901347,-1117687,3880376,-10059388,-17620940,-3612781,-21802117,-3567481,20456845,-1885033 },
+  { 27019610,12299467,-13658288,-1603234,-12861660,-4861471,-19540150,-5016058,29439641,15138866 },
+  { 21536104,-6626420,-32447818,-10690208,-22408077,5175814,-5420040,-16361163,7779328,109896 },
+ },
+ {
+  { 30279744,14648750,-8044871,6425558,13639621,-743509,28698390,12180118,23177719,-554075 },
+  { 26572847,3405927,-31701700,12890905,-19265668,5335866,-6493768,2378492,4439158,-13279347 },
+  { -22716706,3489070,-9225266,-332753,18875722,-1140095,14819434,-12731527,-17717757,-5461437 },
+ },
+ {
+  { -5056483,16566551,15953661,3767752,-10436499,15627060,-820954,2177225,8550082,-15114165 },
+  { -18473302,16596775,-381660,15663611,22860960,15585581,-27844109,-3582739,-23260460,-8428588 },
+  { -32480551,15707275,-8205912,-5652081,29464558,2713815,-22725137,15860482,-21902570,1494193 },
+ },
+ {
+  { -19562091,-14087393,-25583872,-9299552,13127842,759709,21923482,16529112,8742704,12967017 },
+  { -28464899,1553205,32536856,-10473729,-24691605,-406174,-8914625,-2933896,-29903758,15553883 },
+  { 21877909,3230008,9881174,10539357,-4797115,2841332,11543572,14513274,19375923,-12647961 },
+ },
+ {
+  { 8832269,-14495485,13253511,5137575,5037871,4078777,24880818,-6222716,2862653,9455043 },
+  { 29306751,5123106,20245049,-14149889,9592566,8447059,-2077124,-2990080,15511449,4789663 },
+  { -20679756,7004547,8824831,-9434977,-4045704,-3750736,-5754762,108893,23513200,16652362 },
+ },
+},
+{
+ {
+  { -33256173,4144782,-4476029,-6579123,10770039,-7155542,-6650416,-12936300,-18319198,10212860 },
+  { 2756081,8598110,7383731,-6859892,22312759,-1105012,21179801,2600940,-9988298,-12506466 },
+  { -24645692,13317462,-30449259,-15653928,21365574,-10869657,11344424,864440,-2499677,-16710063 },
+ },
+ {
+  { -26432803,6148329,-17184412,-14474154,18782929,-275997,-22561534,211300,2719757,4940997 },
+  { -1323882,3911313,-6948744,14759765,-30027150,7851207,21690126,8518463,26699843,5276295 },
+  { -13149873,-6429067,9396249,365013,24703301,-10488939,1321586,149635,-15452774,7159369 },
+ },
+ {
+  { 9987780,-3404759,17507962,9505530,9731535,-2165514,22356009,8312176,22477218,-8403385 },
+  { 18155857,-16504990,19744716,9006923,15154154,-10538976,24256460,-4864995,-22548173,9334109 },
+  { 2986088,-4911893,10776628,-3473844,10620590,-7083203,-21413845,14253545,-22587149,536906 },
+ },
+ {
+  { 4377756,8115836,24567078,15495314,11625074,13064599,7390551,10589625,10838060,-15420424 },
+  { -19342404,867880,9277171,-3218459,-14431572,-1986443,19295826,-15796950,6378260,699185 },
+  { 7895026,4057113,-7081772,-13077756,-17886831,-323126,-716039,15693155,-5045064,-13373962 },
+ },
+ {
+  { -7737563,-5869402,-14566319,-7406919,11385654,13201616,31730678,-10962840,-3918636,-9669325 },
+  { 10188286,-15770834,-7336361,13427543,22223443,14896287,30743455,7116568,-21786507,5427593 },
+  { 696102,13206899,27047647,-10632082,15285305,-9853179,10798490,-4578720,19236243,12477404 },
+ },
+ {
+  { -11229439,11243796,-17054270,-8040865,-788228,-8167967,-3897669,11180504,-23169516,7733644 },
+  { 17800790,-14036179,-27000429,-11766671,23887827,3149671,23466177,-10538171,10322027,15313801 },
+  { 26246234,11968874,32263343,-5468728,6830755,-13323031,-15794704,-101982,-24449242,10890804 },
+ },
+ {
+  { -31365647,10271363,-12660625,-6267268,16690207,-13062544,-14982212,16484931,25180797,-5334884 },
+  { -586574,10376444,-32586414,-11286356,19801893,10997610,2276632,9482883,316878,13820577 },
+  { -9882808,-4510367,-2115506,16457136,-11100081,11674996,30756178,-7515054,30696930,-3712849 },
+ },
+ {
+  { 32988917,-9603412,12499366,7910787,-10617257,-11931514,-7342816,-9985397,-32349517,7392473 },
+  { -8855661,15927861,9866406,-3649411,-2396914,-16655781,-30409476,-9134995,25112947,-2926644 },
+  { -2504044,-436966,25621774,-5678772,15085042,-5479877,-24884878,-13526194,5537438,-13914319 },
+ },
+},
+{
+ {
+  { -11225584,2320285,-9584280,10149187,-33444663,5808648,-14876251,-1729667,31234590,6090599 },
+  { -9633316,116426,26083934,2897444,-6364437,-2688086,609721,15878753,-6970405,-9034768 },
+  { -27757857,247744,-15194774,-9002551,23288161,-10011936,-23869595,6503646,20650474,1804084 },
+ },
+ {
+  { -27589786,15456424,8972517,8469608,15640622,4439847,3121995,-10329713,27842616,-202328 },
+  { -15306973,2839644,22530074,10026331,4602058,5048462,28248656,5031932,-11375082,12714369 },
+  { 20807691,-7270825,29286141,11421711,-27876523,-13868230,-21227475,1035546,-19733229,12796920 },
+ },
+ {
+  { 12076899,-14301286,-8785001,-11848922,-25012791,16400684,-17591495,-12899438,3480665,-15182815 },
+  { -32361549,5457597,28548107,7833186,7303070,-11953545,-24363064,-15921875,-33374054,2771025 },
+  { -21389266,421932,26597266,6860826,22486084,-6737172,-17137485,-4210226,-24552282,15673397 },
+ },
+ {
+  { -20184622,2338216,19788685,-9620956,-4001265,-8740893,-20271184,4733254,3727144,-12934448 },
+  { 6120119,814863,-11794402,-622716,6812205,-15747771,2019594,7975683,31123697,-10958981 },
+  { 30069250,-11435332,30434654,2958439,18399564,-976289,12296869,9204260,-16432438,9648165 },
+ },
+ {
+  { 32705432,-1550977,30705658,7451065,-11805606,9631813,3305266,5248604,-26008332,-11377501 },
+  { 17219865,2375039,-31570947,-5575615,-19459679,9219903,294711,15298639,2662509,-16297073 },
+  { -1172927,-7558695,-4366770,-4287744,-21346413,-8434326,32087529,-1222777,32247248,-14389861 },
+ },
+ {
+  { 14312628,1221556,17395390,-8700143,-4945741,-8684635,-28197744,-9637817,-16027623,-13378845 },
+  { -1428825,-9678990,-9235681,6549687,-7383069,-468664,23046502,9803137,17597934,2346211 },
+  { 18510800,15337574,26171504,981392,-22241552,7827556,-23491134,-11323352,3059833,-11782870 },
+ },
+ {
+  { 10141598,6082907,17829293,-1947643,9830092,13613136,-25556636,-5544586,-33502212,3592096 },
+  { 33114168,-15889352,-26525686,-13343397,33076705,8716171,1151462,1521897,-982665,-6837803 },
+  { -32939165,-4255815,23947181,-324178,-33072974,-12305637,-16637686,3891704,26353178,693168 },
+ },
+ {
+  { 30374239,1595580,-16884039,13186931,4600344,406904,9585294,-400668,31375464,14369965 },
+  { -14370654,-7772529,1510301,6434173,-18784789,-6262728,32732230,-13108839,17901441,16011505 },
+  { 18171223,-11934626,-12500402,15197122,-11038147,-15230035,-19172240,-16046376,8764035,12309598 },
+ },
+},
+{
+ {
+  { 5975908,-5243188,-19459362,-9681747,-11541277,14015782,-23665757,1228319,17544096,-10593782 },
+  { 5811932,-1715293,3442887,-2269310,-18367348,-8359541,-18044043,-15410127,-5565381,12348900 },
+  { -31399660,11407555,25755363,6891399,-3256938,14872274,-24849353,8141295,-10632534,-585479 },
+ },
+ {
+  { -12675304,694026,-5076145,13300344,14015258,-14451394,-9698672,-11329050,30944593,1130208 },
+  { 8247766,-6710942,-26562381,-7709309,-14401939,-14648910,4652152,2488540,23550156,-271232 },
+  { 17294316,-3788438,7026748,15626851,22990044,113481,2267737,-5908146,-408818,-137719 },
+ },
+ {
+  { 16091085,-16253926,18599252,7340678,2137637,-1221657,-3364161,14550936,3260525,-7166271 },
+  { -4910104,-13332887,18550887,10864893,-16459325,-7291596,-23028869,-13204905,-12748722,2701326 },
+  { -8574695,16099415,4629974,-16340524,-20786213,-6005432,-10018363,9276971,11329923,1862132 },
+ },
+ {
+  { 14763076,-15903608,-30918270,3689867,3511892,10313526,-21951088,12219231,-9037963,-940300 },
+  { 8894987,-3446094,6150753,3013931,301220,15693451,-31981216,-2909717,-15438168,11595570 },
+  { 15214962,3537601,-26238722,-14058872,4418657,-15230761,13947276,10730794,-13489462,-4363670 },
+ },
+ {
+  { -2538306,7682793,32759013,263109,-29984731,-7955452,-22332124,-10188635,977108,699994 },
+  { -12466472,4195084,-9211532,550904,-15565337,12917920,19118110,-439841,-30534533,-14337913 },
+  { 31788461,-14507657,4799989,7372237,8808585,-14747943,9408237,-10051775,12493932,-5409317 },
+ },
+ {
+  { -25680606,5260744,-19235809,-6284470,-3695942,16566087,27218280,2607121,29375955,6024730 },
+  { 842132,-2794693,-4763381,-8722815,26332018,-12405641,11831880,6985184,-9940361,2854096 },
+  { -4847262,-7969331,2516242,-5847713,9695691,-7221186,16512645,960770,12121869,16648078 },
+ },
+ {
+  { -15218652,14667096,-13336229,2013717,30598287,-464137,-31504922,-7882064,20237806,2838411 },
+  { -19288047,4453152,15298546,-16178388,22115043,-15972604,12544294,-13470457,1068881,-12499905 },
+  { -9558883,-16518835,33238498,13506958,30505848,-1114596,-8486907,-2630053,12521378,4845654 },
+ },
+ {
+  { -28198521,10744108,-2958380,10199664,7759311,-13088600,3409348,-873400,-6482306,-12885870 },
+  { -23561822,6230156,-20382013,10655314,-24040585,-11621172,10477734,-1240216,-3113227,13974498 },
+  { 12966261,15550616,-32038948,-1615346,21025980,-629444,5642325,7188737,18895762,12629579 },
+ },
+},
+{
+ {
+  { 14741879,-14946887,22177208,-11721237,1279741,8058600,11758140,789443,32195181,3895677 },
+  { 10758205,15755439,-4509950,9243698,-4879422,6879879,-2204575,-3566119,-8982069,4429647 },
+  { -2453894,15725973,-20436342,-10410672,-5803908,-11040220,-7135870,-11642895,18047436,-15281743 },
+ },
+ {
+  { -25173001,-11307165,29759956,11776784,-22262383,-15820455,10993114,-12850837,-17620701,-9408468 },
+  { 21987233,700364,-24505048,14972008,-7774265,-5718395,32155026,2581431,-29958985,8773375 },
+  { -25568350,454463,-13211935,16126715,25240068,8594567,20656846,12017935,-7874389,-13920155 },
+ },
+ {
+  { 6028182,6263078,-31011806,-11301710,-818919,2461772,-31841174,-5468042,-1721788,-2776725 },
+  { -12278994,16624277,987579,-5922598,32908203,1248608,7719845,-4166698,28408820,6816612 },
+  { -10358094,-8237829,19549651,-12169222,22082623,16147817,20613181,13982702,-10339570,5067943 },
+ },
+ {
+  { -30505967,-3821767,12074681,13582412,-19877972,2443951,-19719286,12746132,5331210,-10105944 },
+  { 30528811,3601899,-1957090,4619785,-27361822,-15436388,24180793,-12570394,27679908,-1648928 },
+  { 9402404,-13957065,32834043,10838634,-26580150,-13237195,26653274,-8685565,22611444,-12715406 },
+ },
+ {
+  { 22190590,1118029,22736441,15130463,-30460692,-5991321,19189625,-4648942,4854859,6622139 },
+  { -8310738,-2953450,-8262579,-3388049,-10401731,-271929,13424426,-3567227,26404409,13001963 },
+  { -31241838,-15415700,-2994250,8939346,11562230,-12840670,-26064365,-11621720,-15405155,11020693 },
+ },
+ {
+  { 1866042,-7949489,-7898649,-10301010,12483315,13477547,3175636,-12424163,28761762,1406734 },
+  { -448555,-1777666,13018551,3194501,-9580420,-11161737,24760585,-4347088,25577411,-13378680 },
+  { -24290378,4759345,-690653,-1852816,2066747,10693769,-29595790,9884936,-9368926,4745410 },
+ },
+ {
+  { -9141284,6049714,-19531061,-4341411,-31260798,9944276,-15462008,-11311852,10931924,-11931931 },
+  { -16561513,14112680,-8012645,4817318,-8040464,-11414606,-22853429,10856641,-20470770,13434654 },
+  { 22759489,-10073434,-16766264,-1871422,13637442,-10168091,1765144,-12654326,28445307,-5364710 },
+ },
+ {
+  { 29875063,12493613,2795536,-3786330,1710620,15181182,-10195717,-8788675,9074234,1167180 },
+  { -26205683,11014233,-9842651,-2635485,-26908120,7532294,-18716888,-9535498,3843903,9367684 },
+  { -10969595,-6403711,9591134,9582310,11349256,108879,16235123,8601684,-139197,4242895 },
+ },
+},
+{
+ {
+  { 22092954,-13191123,-2042793,-11968512,32186753,-11517388,-6574341,2470660,-27417366,16625501 },
+  { -11057722,3042016,13770083,-9257922,584236,-544855,-7770857,2602725,-27351616,14247413 },
+  { 6314175,-10264892,-32772502,15957557,-10157730,168750,-8618807,14290061,27108877,-1180880 },
+ },
+ {
+  { -8586597,-7170966,13241782,10960156,-32991015,-13794596,33547976,-11058889,-27148451,981874 },
+  { 22833440,9293594,-32649448,-13618667,-9136966,14756819,-22928859,-13970780,-10479804,-16197962 },
+  { -7768587,3326786,-28111797,10783824,19178761,14905060,22680049,13906969,-15933690,3797899 },
+ },
+ {
+  { 21721356,-4212746,-12206123,9310182,-3882239,-13653110,23740224,-2709232,20491983,-8042152 },
+  { 9209270,-15135055,-13256557,-6167798,-731016,15289673,25947805,15286587,30997318,-6703063 },
+  { 7392032,16618386,23946583,-8039892,-13265164,-1533858,-14197445,-2321576,17649998,-250080 },
+ },
+ {
+  { -9301088,-14193827,30609526,-3049543,-25175069,-1283752,-15241566,-9525724,-2233253,7662146 },
+  { -17558673,1763594,-33114336,15908610,-30040870,-12174295,7335080,-8472199,-3174674,3440183 },
+  { -19889700,-5977008,-24111293,-9688870,10799743,-16571957,40450,-4431835,4862400,1133 },
+ },
+ {
+  { -32856209,-7873957,-5422389,14860950,-16319031,7956142,7258061,311861,-30594991,-7379421 },
+  { -3773428,-1565936,28985340,7499440,24445838,9325937,29727763,16527196,18278453,15405622 },
+  { -4381906,8508652,-19898366,-3674424,-5984453,15149970,-13313598,843523,-21875062,13626197 },
+ },
+ {
+  { 2281448,-13487055,-10915418,-2609910,1879358,16164207,-10783882,3953792,13340839,15928663 },
+  { 31727126,-7179855,-18437503,-8283652,2875793,-16390330,-25269894,-7014826,-23452306,5964753 },
+  { 4100420,-5959452,-17179337,6017714,-18705837,12227141,-26684835,11344144,2538215,-7570755 },
+ },
+ {
+  { -9433605,6123113,11159803,-2156608,30016280,14966241,-20474983,1485421,-629256,-15958862 },
+  { -26804558,4260919,11851389,9658551,-32017107,16367492,-20205425,-13191288,11659922,-11115118 },
+  { 26180396,10015009,-30844224,-8581293,5418197,9480663,2231568,-10170080,33100372,-1306171 },
+ },
+ {
+  { 15121113,-5201871,-10389905,15427821,-27509937,-15992507,21670947,4486675,-5931810,-14466380 },
+  { 16166486,-9483733,-11104130,6023908,-31926798,-1364923,2340060,-16254968,-10735770,-10039824 },
+  { 28042865,-3557089,-12126526,12259706,-3717498,-6945899,6766453,-8689599,18036436,5803270 },
+ },
+},
+{
+ {
+  { -817581,6763912,11803561,1585585,10958447,-2671165,23855391,4598332,-6159431,-14117438 },
+  { -31031306,-14256194,17332029,-2383520,31312682,-5967183,696309,50292,-20095739,11763584 },
+  { -594563,-2514283,-32234153,12643980,12650761,14811489,665117,-12613632,-19773211,-10713562 },
+ },
+ {
+  { 30464590,-11262872,-4127476,-12734478,19835327,-7105613,-24396175,2075773,-17020157,992471 },
+  { 18357185,-6994433,7766382,16342475,-29324918,411174,14578841,8080033,-11574335,-10601610 },
+  { 19598397,10334610,12555054,2555664,18821899,-10339780,21873263,16014234,26224780,16452269 },
+ },
+ {
+  { -30223925,5145196,5944548,16385966,3976735,2009897,-11377804,-7618186,-20533829,3698650 },
+  { 14187449,3448569,-10636236,-10810935,-22663880,-3433596,7268410,-10890444,27394301,12015369 },
+  { 19695761,16087646,28032085,12999827,6817792,11427614,20244189,-1312777,-13259127,-3402461 },
+ },
+ {
+  { 30860103,12735208,-1888245,-4699734,-16974906,2256940,-8166013,12298312,-8550524,-10393462 },
+  { -5719826,-11245325,-1910649,15569035,26642876,-7587760,-5789354,-15118654,-4976164,12651793 },
+  { -2848395,9953421,11531313,-5282879,26895123,-12697089,-13118820,-16517902,9768698,-2533218 },
+ },
+ {
+  { -24719459,1894651,-287698,-4704085,15348719,-8156530,32767513,12765450,4940095,10678226 },
+  { 18860224,15980149,-18987240,-1562570,-26233012,-11071856,-7843882,13944024,-24372348,16582019 },
+  { -15504260,4970268,-29893044,4175593,-20993212,-2199756,-11704054,15444560,-11003761,7989037 },
+ },
+ {
+  { 31490452,5568061,-2412803,2182383,-32336847,4531686,-32078269,6200206,-19686113,-14800171 },
+  { -17308668,-15879940,-31522777,-2831,-32887382,16375549,8680158,-16371713,28550068,-6857132 },
+  { -28126887,-5688091,16837845,-1820458,-6850681,12700016,-30039981,4364038,1155602,5988841 },
+ },
+ {
+  { 21890435,-13272907,-12624011,12154349,-7831873,15300496,23148983,-4470481,24618407,8283181 },
+  { -33136107,-10512751,9975416,6841041,-31559793,16356536,3070187,-7025928,1466169,10740210 },
+  { -1509399,-15488185,-13503385,-10655916,32799044,909394,-13938903,-5779719,-32164649,-15327040 },
+ },
+ {
+  { 3960823,-14267803,-28026090,-15918051,-19404858,13146868,15567327,951507,-3260321,-573935 },
+  { 24740841,5052253,-30094131,8961361,25877428,6165135,-24368180,14397372,-7380369,-6144105 },
+  { -28888365,3510803,-28103278,-1158478,-11238128,-10631454,-15441463,-14453128,-1625486,-6494814 },
+ },
+},
+{
+ {
+  { 793299,-9230478,8836302,-6235707,-27360908,-2369593,33152843,-4885251,-9906200,-621852 },
+  { 5666233,525582,20782575,-8038419,-24538499,14657740,16099374,1468826,-6171428,-15186581 },
+  { -4859255,-3779343,-2917758,-6748019,7778750,11688288,-30404353,-9871238,-1558923,-9863646 },
+ },
+ {
+  { 10896332,-7719704,824275,472601,-19460308,3009587,25248958,14783338,-30581476,-15757844 },
+  { 10566929,12612572,-31944212,11118703,-12633376,12362879,21752402,8822496,24003793,14264025 },
+  { 27713862,-7355973,-11008240,9227530,27050101,2504721,23886875,-13117525,13958495,-5732453 },
+ },
+ {
+  { -23481610,4867226,-27247128,3900521,29838369,-8212291,-31889399,-10041781,7340521,-15410068 },
+  { 4646514,-8011124,-22766023,-11532654,23184553,8566613,31366726,-1381061,-15066784,-10375192 },
+  { -17270517,12723032,-16993061,14878794,21619651,-6197576,27584817,3093888,-8843694,3849921 },
+ },
+ {
+  { -9064912,2103172,25561640,-15125738,-5239824,9582958,32477045,-9017955,5002294,-15550259 },
+  { -12057553,-11177906,21115585,-13365155,8808712,-12030708,16489530,13378448,-25845716,12741426 },
+  { -5946367,10645103,-30911586,15390284,-3286982,-7118677,24306472,15852464,28834118,-7646072 },
+ },
+ {
+  { -17335748,-9107057,-24531279,9434953,-8472084,-583362,-13090771,455841,20461858,5491305 },
+  { 13669248,-16095482,-12481974,-10203039,-14569770,-11893198,-24995986,11293807,-28588204,-9421832 },
+  { 28497928,6272777,-33022994,14470570,8906179,-1225630,18504674,-14165166,29867745,-8795943 },
+ },
+ {
+  { -16207023,13517196,-27799630,-13697798,24009064,-6373891,-6367600,-13175392,22853429,-4012011 },
+  { 24191378,16712145,-13931797,15217831,14542237,1646131,18603514,-11037887,12876623,-2112447 },
+  { 17902668,4518229,-411702,-2829247,26878217,5258055,-12860753,608397,16031844,3723494 },
+ },
+ {
+  { -28632773,12763728,-20446446,7577504,33001348,-13017745,17558842,-7872890,23896954,-4314245 },
+  { -20005381,-12011952,31520464,605201,2543521,5991821,-2945064,7229064,-9919646,-8826859 },
+  { 28816045,298879,-28165016,-15920938,19000928,-1665890,-12680833,-2949325,-18051778,-2082915 },
+ },
+ {
+  { 16000882,-344896,3493092,-11447198,-29504595,-13159789,12577740,16041268,-19715240,7847707 },
+  { 10151868,10572098,27312476,7922682,14825339,4723128,-32855931,-6519018,-10020567,3852848 },
+  { -11430470,15697596,-21121557,-4420647,5386314,15063598,16514493,-15932110,29330899,-15076224 },
+ },
+},
+{
+ {
+  { -25499735,-4378794,-15222908,-6901211,16615731,2051784,3303702,15490,-27548796,12314391 },
+  { 15683520,-6003043,18109120,-9980648,15337968,-5997823,-16717435,15921866,16103996,-3731215 },
+  { -23169824,-10781249,13588192,-1628807,-3798557,-1074929,-19273607,5402699,-29815713,-9841101 },
+ },
+ {
+  { 23190676,2384583,-32714340,3462154,-29903655,-1529132,-11266856,8911517,-25205859,2739713 },
+  { 21374101,-3554250,-33524649,9874411,15377179,11831242,-33529904,6134907,4931255,11987849 },
+  { -7732,-2978858,-16223486,7277597,105524,-322051,-31480539,13861388,-30076310,10117930 },
+ },
+ {
+  { -29501170,-10744872,-26163768,13051539,-25625564,5089643,-6325503,6704079,12890019,15728940 },
+  { -21972360,-11771379,-951059,-4418840,14704840,2695116,903376,-10428139,12885167,8311031 },
+  { -17516482,5352194,10384213,-13811658,7506451,13453191,26423267,4384730,1888765,-5435404 },
+ },
+ {
+  { -25817338,-3107312,-13494599,-3182506,30896459,-13921729,-32251644,-12707869,-19464434,-3340243 },
+  { -23607977,-2665774,-526091,4651136,5765089,4618330,6092245,14845197,17151279,-9854116 },
+  { -24830458,-12733720,-15165978,10367250,-29530908,-265356,22825805,-7087279,-16866484,16176525 },
+ },
+ {
+  { -23583256,6564961,20063689,3798228,-4740178,7359225,2006182,-10363426,-28746253,-10197509 },
+  { -10626600,-4486402,-13320562,-5125317,3432136,-6393229,23632037,-1940610,32808310,1099883 },
+  { 15030977,5768825,-27451236,-2887299,-6427378,-15361371,-15277896,-6809350,2051441,-15225865 },
+ },
+ {
+  { -3362323,-7239372,7517890,9824992,23555850,295369,5148398,-14154188,-22686354,16633660 },
+  { 4577086,-16752288,13249841,-15304328,19958763,-14537274,18559670,-10759549,8402478,-9864273 },
+  { -28406330,-1051581,-26790155,-907698,-17212414,-11030789,9453451,-14980072,17983010,9967138 },
+ },
+ {
+  { -25762494,6524722,26585488,9969270,24709298,1220360,-1677990,7806337,17507396,3651560 },
+  { -10420457,-4118111,14584639,15971087,-15768321,8861010,26556809,-5574557,-18553322,-11357135 },
+  { 2839101,14284142,4029895,3472686,14402957,12689363,-26642121,8459447,-5605463,-7621941 },
+ },
+ {
+  { -4839289,-3535444,9744961,2871048,25113978,3187018,-25110813,-849066,17258084,-7977739 },
+  { 18164541,-10595176,-17154882,-1542417,19237078,-9745295,23357533,-15217008,26908270,12150756 },
+  { -30264870,-7647865,5112249,-7036672,-1499807,-6974257,43168,-5537701,-32302074,16215819 },
+ },
+},
+{
+ {
+  { -6898905,9824394,-12304779,-4401089,-31397141,-6276835,32574489,12532905,-7503072,-8675347 },
+  { -27343522,-16515468,-27151524,-10722951,946346,16291093,254968,7168080,21676107,-1943028 },
+  { 21260961,-8424752,-16831886,-11920822,-23677961,3968121,-3651949,-6215466,-3556191,-7913075 },
+ },
+ {
+  { 16544754,13250366,-16804428,15546242,-4583003,12757258,-2462308,-8680336,-18907032,-9662799 },
+  { -2415239,-15577728,18312303,4964443,-15272530,-12653564,26820651,16690659,25459437,-4564609 },
+  { -25144690,11425020,28423002,-11020557,-6144921,-15826224,9142795,-2391602,-6432418,-1644817 },
+ },
+ {
+  { -23104652,6253476,16964147,-3768872,-25113972,-12296437,-27457225,-16344658,6335692,7249989 },
+  { -30333227,13979675,7503222,-12368314,-11956721,-4621693,-30272269,2682242,25993170,-12478523 },
+  { 4364628,5930691,32304656,-10044554,-8054781,15091131,22857016,-10598955,31820368,15075278 },
+ },
+ {
+  { 31879134,-8918693,17258761,90626,-8041836,-4917709,24162788,-9650886,-17970238,12833045 },
+  { 19073683,14851414,-24403169,-11860168,7625278,11091125,-19619190,2074449,-9413939,14905377 },
+  { 24483667,-11935567,-2518866,-11547418,-1553130,15355506,-25282080,9253129,27628530,-7555480 },
+ },
+ {
+  { 17597607,8340603,19355617,552187,26198470,-3176583,4593324,-9157582,-14110875,15297016 },
+  { 510886,14337390,-31785257,16638632,6328095,2713355,-20217417,-11864220,8683221,2921426 },
+  { 18606791,11874196,27155355,-5281482,-24031742,6265446,-25178240,-1278924,4674690,13890525 },
+ },
+ {
+  { 13609624,13069022,-27372361,-13055908,24360586,9592974,14977157,9835105,4389687,288396 },
+  { 9922506,-519394,13613107,5883594,-18758345,-434263,-12304062,8317628,23388070,16052080 },
+  { 12720016,11937594,-31970060,-5028689,26900120,8561328,-20155687,-11632979,-14754271,-10812892 },
+ },
+ {
+  { 15961858,14150409,26716931,-665832,-22794328,13603569,11829573,7467844,-28822128,929275 },
+  { 11038231,-11582396,-27310482,-7316562,-10498527,-16307831,-23479533,-9371869,-21393143,2465074 },
+  { 20017163,-4323226,27915242,1529148,12396362,15675764,13817261,-9658066,2463391,-4622140 },
+ },
+ {
+  { -16358878,-12663911,-12065183,4996454,-1256422,1073572,9583558,12851107,4003896,12673717 },
+  { -1731589,-15155870,-3262930,16143082,19294135,13385325,14741514,-9103726,7903886,2348101 },
+  { 24536016,-16515207,12715592,-3862155,1511293,10047386,-3842346,-7129159,-28377538,10048127 },
+ },
+},
+{
+ {
+  { -12622226,-6204820,30718825,2591312,-10617028,12192840,18873298,-7297090,-32297756,15221632 },
+  { -26478122,-11103864,11546244,-1852483,9180880,7656409,-21343950,2095755,29769758,6593415 },
+  { -31994208,-2907461,4176912,3264766,12538965,-868111,26312345,-6118678,30958054,8292160 },
+ },
+ {
+  { 31429822,-13959116,29173532,15632448,12174511,-2760094,32808831,3977186,26143136,-3148876 },
+  { 22648901,1402143,-22799984,13746059,7936347,365344,-8668633,-1674433,-3758243,-2304625 },
+  { -15491917,8012313,-2514730,-12702462,-23965846,-10254029,-1612713,-1535569,-16664475,8194478 },
+ },
+ {
+  { 27338066,-7507420,-7414224,10140405,-19026427,-6589889,27277191,8855376,28572286,3005164 },
+  { 26287124,4821776,25476601,-4145903,-3764513,-15788984,-18008582,1182479,-26094821,-13079595 },
+  { -7171154,3178080,23970071,6201893,-17195577,-4489192,-21876275,-13982627,32208683,-1198248 },
+ },
+ {
+  { -16657702,2817643,-10286362,14811298,6024667,13349505,-27315504,-10497842,-27672585,-11539858 },
+  { 15941029,-9405932,-21367050,8062055,31876073,-238629,-15278393,-1444429,15397331,-4130193 },
+  { 8934485,-13485467,-23286397,-13423241,-32446090,14047986,31170398,-1441021,-27505566,15087184 },
+ },
+ {
+  { -18357243,-2156491,24524913,-16677868,15520427,-6360776,-15502406,11461896,16788528,-5868942 },
+  { -1947386,16013773,21750665,3714552,-17401782,-16055433,-3770287,-10323320,31322514,-11615635 },
+  { 21426655,-5650218,-13648287,-5347537,-28812189,-4920970,-18275391,-14621414,13040862,-12112948 },
+ },
+ {
+  { 11293895,12478086,-27136401,15083750,-29307421,14748872,14555558,-13417103,1613711,4896935 },
+  { -25894883,15323294,-8489791,-8057900,25967126,-13425460,2825960,-4897045,-23971776,-11267415 },
+  { -15924766,-5229880,-17443532,6410664,3622847,10243618,20615400,12405433,-23753030,-8436416 },
+ },
+ {
+  { -7091295,12556208,-20191352,9025187,-17072479,4333801,4378436,2432030,23097949,-566018 },
+  { 4565804,-16025654,20084412,-7842817,1724999,189254,24767264,10103221,-18512313,2424778 },
+  { 366633,-11976806,8173090,-6890119,30788634,5745705,-7168678,1344109,-3642553,12412659 },
+ },
+ {
+  { -24001791,7690286,14929416,-168257,-32210835,-13412986,24162697,-15326504,-3141501,11179385 },
+  { 18289522,-14724954,8056945,16430056,-21729724,7842514,-6001441,-1486897,-18684645,-11443503 },
+  { 476239,6601091,-6152790,-9723375,17503545,-4863900,27672959,13403813,11052904,5219329 },
+ },
+},
+{
+ {
+  { 20678546,-8375738,-32671898,8849123,-5009758,14574752,31186971,-3973730,9014762,-8579056 },
+  { -13644050,-10350239,-15962508,5075808,-1514661,-11534600,-33102500,9160280,8473550,-3256838 },
+  { 24900749,14435722,17209120,-15292541,-22592275,9878983,-7689309,-16335821,-24568481,11788948 },
+ },
+ {
+  { -3118155,-11395194,-13802089,14797441,9652448,-6845904,-20037437,10410733,-24568470,-1458691 },
+  { -15659161,16736706,-22467150,10215878,-9097177,7563911,11871841,-12505194,-18513325,8464118 },
+  { -23400612,8348507,-14585951,-861714,-3950205,-6373419,14325289,8628612,33313881,-8370517 },
+ },
+ {
+  { -20186973,-4967935,22367356,5271547,-1097117,-4788838,-24805667,-10236854,-8940735,-5818269 },
+  { -6948785,-1795212,-32625683,-16021179,32635414,-7374245,15989197,-12838188,28358192,-4253904 },
+  { -23561781,-2799059,-32351682,-1661963,-9147719,10429267,-16637684,4072016,-5351664,5596589 },
+ },
+ {
+  { -28236598,-3390048,12312896,6213178,3117142,16078565,29266239,2557221,1768301,15373193 },
+  { -7243358,-3246960,-4593467,-7553353,-127927,-912245,-1090902,-4504991,-24660491,3442910 },
+  { -30210571,5124043,14181784,8197961,18964734,-11939093,22597931,7176455,-18585478,13365930 },
+ },
+ {
+  { -7877390,-1499958,8324673,4690079,6261860,890446,24538107,-8570186,-9689599,-3031667 },
+  { 25008904,-10771599,-4305031,-9638010,16265036,15721635,683793,-11823784,15723479,-15163481 },
+  { -9660625,12374379,-27006999,-7026148,-7724114,-12314514,11879682,5400171,519526,-1235876 },
+ },
+ {
+  { 22258397,-16332233,-7869817,14613016,-22520255,-2950923,-20353881,7315967,16648397,7605640 },
+  { -8081308,-8464597,-8223311,9719710,19259459,-15348212,23994942,-5281555,-9468848,4763278 },
+  { -21699244,9220969,-15730624,1084137,-25476107,-2852390,31088447,-7764523,-11356529,728112 },
+ },
+ {
+  { 26047220,-11751471,-6900323,-16521798,24092068,9158119,-4273545,-12555558,-29365436,-5498272 },
+  { 17510331,-322857,5854289,8403524,17133918,-3112612,-28111007,12327945,10750447,10014012 },
+  { -10312768,3936952,9156313,-8897683,16498692,-994647,-27481051,-666732,3424691,7540221 },
+ },
+ {
+  { 30322361,-6964110,11361005,-4143317,7433304,4989748,-7071422,-16317219,-9244265,15258046 },
+  { 13054562,-2779497,19155474,469045,-12482797,4566042,5631406,2711395,1062915,-5136345 },
+  { -19240248,-11254599,-29509029,-7499965,-5835763,13005411,-6066489,12194497,32960380,1459310 },
+ },
+},
+{
+ {
+  { 19852034,7027924,23669353,10020366,8586503,-6657907,394197,-6101885,18638003,-11174937 },
+  { 31395534,15098109,26581030,8030562,-16527914,-5007134,9012486,-7584354,-6643087,-5442636 },
+  { -9192165,-2347377,-1997099,4529534,25766844,607986,-13222,9677543,-32294889,-6456008 },
+ },
+ {
+  { -2444496,-149937,29348902,8186665,1873760,12489863,-30934579,-7839692,-7852844,-8138429 },
+  { -15236356,-15433509,7766470,746860,26346930,-10221762,-27333451,10754588,-9431476,5203576 },
+  { 31834314,14135496,-770007,5159118,20917671,-16768096,-7467973,-7337524,31809243,7347066 },
+ },
+ {
+  { -9606723,-11874240,20414459,13033986,13716524,-11691881,19797970,-12211255,15192876,-2087490 },
+  { -12663563,-2181719,1168162,-3804809,26747877,-14138091,10609330,12694420,33473243,-13382104 },
+  { 33184999,11180355,15832085,-11385430,-1633671,225884,15089336,-11023903,-6135662,14480053 },
+ },
+ {
+  { 31308717,-5619998,31030840,-1897099,15674547,-6582883,5496208,13685227,27595050,8737275 },
+  { -20318852,-15150239,10933843,-16178022,8335352,-7546022,-31008351,-12610604,26498114,66511 },
+  { 22644454,-8761729,-16671776,4884562,-3105614,-13559366,30540766,-4286747,-13327787,-7515095 },
+ },
+ {
+  { -28017847,9834845,18617207,-2681312,-3401956,-13307506,8205540,13585437,-17127465,15115439 },
+  { 23711543,-672915,31206561,-8362711,6164647,-9709987,-33535882,-1426096,8236921,16492939 },
+  { -23910559,-13515526,-26299483,-4503841,25005590,-7687270,19574902,10071562,6708380,-6222424 },
+ },
+ {
+  { 2101391,-4930054,19702731,2367575,-15427167,1047675,5301017,9328700,29955601,-11678310 },
+  { 3096359,9271816,-21620864,-15521844,-14847996,-7592937,-25892142,-12635595,-9917575,6216608 },
+  { -32615849,338663,-25195611,2510422,-29213566,-13820213,24822830,-6146567,-26767480,7525079 },
+ },
+ {
+  { -23066649,-13985623,16133487,-7896178,-3389565,778788,-910336,-2782495,-19386633,11994101 },
+  { 21691500,-13624626,-641331,-14367021,3285881,-3483596,-25064666,9718258,-7477437,13381418 },
+  { 18445390,-4202236,14979846,11622458,-1727110,-3582980,23111648,-6375247,28535282,15779576 },
+ },
+ {
+  { 30098053,3089662,-9234387,16662135,-21306940,11308411,-14068454,12021730,9955285,-16303356 },
+  { 9734894,-14576830,-7473633,-9138735,2060392,11313496,-18426029,9924399,20194861,13380996 },
+  { -26378102,-7965207,-22167821,15789297,-18055342,-6168792,-1984914,15707771,26342023,10146099 },
+ },
+},
+{
+ {
+  { -26016874,-219943,21339191,-41388,19745256,-2878700,-29637280,2227040,21612326,-545728 },
+  { -13077387,1184228,23562814,-5970442,-20351244,-6348714,25764461,12243797,-20856566,11649658 },
+  { -10031494,11262626,27384172,2271902,26947504,-15997771,39944,6114064,33514190,2333242 },
+ },
+ {
+  { -21433588,-12421821,8119782,7219913,-21830522,-9016134,-6679750,-12670638,24350578,-13450001 },
+  { -4116307,-11271533,-23886186,4843615,-30088339,690623,-31536088,-10406836,8317860,12352766 },
+  { 18200138,-14475911,-33087759,-2696619,-23702521,-9102511,-23552096,-2287550,20712163,6719373 },
+ },
+ {
+  { 26656208,6075253,-7858556,1886072,-28344043,4262326,11117530,-3763210,26224235,-3297458 },
+  { -17168938,-14854097,-3395676,-16369877,-19954045,14050420,21728352,9493610,18620611,-16428628 },
+  { -13323321,13325349,11432106,5964811,18609221,6062965,-5269471,-9725556,-30701573,-16479657 },
+ },
+ {
+  { -23860538,-11233159,26961357,1640861,-32413112,-16737940,12248509,-5240639,13735342,1934062 },
+  { 25089769,6742589,17081145,-13406266,21909293,-16067981,-15136294,-3765346,-21277997,5473616 },
+  { 31883677,-7961101,1083432,-11572403,22828471,13290673,-7125085,12469656,29111212,-5451014 },
+ },
+ {
+  { 24244947,-15050407,-26262976,2791540,-14997599,16666678,24367466,6388839,-10295587,452383 },
+  { -25640782,-3417841,5217916,16224624,19987036,-4082269,-24236251,-5915248,15766062,8407814 },
+  { -20406999,13990231,15495425,16395525,5377168,15166495,-8917023,-4388953,-8067909,2276718 },
+ },
+ {
+  { 30157918,12924066,-17712050,9245753,19895028,3368142,-23827587,5096219,22740376,-7303417 },
+  { 2041139,-14256350,7783687,13876377,-25946985,-13352459,24051124,13742383,-15637599,13295222 },
+  { 33338237,-8505733,12532113,7977527,9106186,-1715251,-17720195,-4612972,-4451357,-14669444 },
+ },
+ {
+  { -20045281,5454097,-14346548,6447146,28862071,1883651,-2469266,-4141880,7770569,9620597 },
+  { 23208068,7979712,33071466,8149229,1758231,-10834995,30945528,-1694323,-33502340,-14767970 },
+  { 1439958,-16270480,-1079989,-793782,4625402,10647766,-5043801,1220118,30494170,-11440799 },
+ },
+ {
+  { -5037580,-13028295,-2970559,-3061767,15640974,-6701666,-26739026,926050,-1684339,-13333647 },
+  { 13908495,-3549272,30919928,-6273825,-21521863,7989039,9021034,9078865,3353509,4033511 },
+  { -29663431,-15113610,32259991,-344482,24295849,-12912123,23161163,8839127,27485041,7356032 },
+ },
+},
+{
+ {
+  { 9661027,705443,11980065,-5370154,-1628543,14661173,-6346142,2625015,28431036,-16771834 },
+  { -23839233,-8311415,-25945511,7480958,-17681669,-8354183,-22545972,14150565,15970762,4099461 },
+  { 29262576,16756590,26350592,-8793563,8529671,-11208050,13617293,-9937143,11465739,8317062 },
+ },
+ {
+  { -25493081,-6962928,32500200,-9419051,-23038724,-2302222,14898637,3848455,20969334,-5157516 },
+  { -20384450,-14347713,-18336405,13884722,-33039454,2842114,-21610826,-3649888,11177095,14989547 },
+  { -24496721,-11716016,16959896,2278463,12066309,10137771,13515641,2581286,-28487508,9930240 },
+ },
+ {
+  { -17751622,-2097826,16544300,-13009300,-15914807,-14949081,18345767,-13403753,16291481,-5314038 },
+  { -33229194,2553288,32678213,9875984,8534129,6889387,-9676774,6957617,4368891,9788741 },
+  { 16660756,7281060,-10830758,12911820,20108584,-8101676,-21722536,-8613148,16250552,-11111103 },
+ },
+ {
+  { -19765507,2390526,-16551031,14161980,1905286,6414907,4689584,10604807,-30190403,4782747 },
+  { -1354539,14736941,-7367442,-13292886,7710542,-14155590,-9981571,4383045,22546403,437323 },
+  { 31665577,-12180464,-16186830,1491339,-18368625,3294682,27343084,2786261,-30633590,-14097016 },
+ },
+ {
+  { -14467279,-683715,-33374107,7448552,19294360,14334329,-19690631,2355319,-19284671,-6114373 },
+  { 15121312,-15796162,6377020,-6031361,-10798111,-12957845,18952177,15496498,-29380133,11754228 },
+  { -2637277,-13483075,8488727,-14303896,12728761,-1622493,7141596,11724556,22761615,-10134141 },
+ },
+ {
+  { 16918416,11729663,-18083579,3022987,-31015732,-13339659,-28741185,-12227393,32851222,11717399 },
+  { 11166634,7338049,-6722523,4531520,-29468672,-7302055,31474879,3483633,-1193175,-4030831 },
+  { -185635,9921305,31456609,-13536438,-12013818,13348923,33142652,6546660,-19985279,-3948376 },
+ },
+ {
+  { -32460596,11266712,-11197107,-7899103,31703694,3855903,-8537131,-12833048,-30772034,-15486313 },
+  { -18006477,12709068,3991746,-6479188,-21491523,-10550425,-31135347,-16049879,10928917,3011958 },
+  { -6957757,-15594337,31696059,334240,29576716,14796075,-30831056,-12805180,18008031,10258577 },
+ },
+ {
+  { -22448644,15655569,7018479,-4410003,-30314266,-1201591,-1853465,1367120,25127874,6671743 },
+  { 29701166,-14373934,-10878120,9279288,-17568,13127210,21382910,11042292,25838796,4642684 },
+  { -20430234,14955537,-24126347,8124619,-5369288,-5990470,30468147,-13900640,18423289,4177476 },
+ },
+},
+} ;
+
+
+static void ge_select(ge_precomp *t,int pos,signed char b)
+{
+  ge_precomp minust;
+  unsigned char bnegative = negative(b);
+  unsigned char babs = b - (((-bnegative) & b) << 1);
+
+  ge_precomp_0(t);
+  cmov(t,&base[pos][0],equal(babs,1));
+  cmov(t,&base[pos][1],equal(babs,2));
+  cmov(t,&base[pos][2],equal(babs,3));
+  cmov(t,&base[pos][3],equal(babs,4));
+  cmov(t,&base[pos][4],equal(babs,5));
+  cmov(t,&base[pos][5],equal(babs,6));
+  cmov(t,&base[pos][6],equal(babs,7));
+  cmov(t,&base[pos][7],equal(babs,8));
+  fe_copy(minust.yplusx,t->yminusx);
+  fe_copy(minust.yminusx,t->yplusx);
+  fe_neg(minust.xy2d,t->xy2d);
+  cmov(t,&minust,bnegative);
+}
+
+
+/*
+h = a * B
+where a = a[0]+256*a[1]+...+256^31 a[31]
+B is the Ed25519 base point (x,4/5) with x positive.
+
+Preconditions:
+  a[31] <= 127
+*/
+void ge_scalarmult_base(ge_p3 *h,const unsigned char *a)
+{
+  signed char e[64];
+  signed char carry;
+  ge_p1p1 r;
+  ge_p2 s;
+  ge_precomp t;
+  int i;
+
+  for (i = 0;i < 32;++i) {
+    e[2 * i + 0] = (a[i] >> 0) & 15;
+    e[2 * i + 1] = (a[i] >> 4) & 15;
+  }
+  /* each e[i] is between 0 and 15 */
+  /* e[63] is between 0 and 7 */
+
+  carry = 0;
+  for (i = 0;i < 63;++i) {
+    e[i] += carry;
+    carry = e[i] + 8;
+    carry >>= 4;
+    e[i] -= carry << 4;
+  }
+  e[63] += carry;
+  /* each e[i] is between -8 and 8 */
+
+  ge_p3_0(h);
+  for (i = 1;i < 64;i += 2) {
+    ge_select(&t,i / 2,e[i]);
+    ge_madd(&r,h,&t); ge_p1p1_to_p3(h,&r);
+  }
+
+  ge_p3_dbl(&r,h);  ge_p1p1_to_p2(&s,&r);
+  ge_p2_dbl(&r,&s); ge_p1p1_to_p2(&s,&r);
+  ge_p2_dbl(&r,&s); ge_p1p1_to_p2(&s,&r);
+  ge_p2_dbl(&r,&s); ge_p1p1_to_p3(h,&r);
+
+  for (i = 0;i < 64;i += 2) {
+    ge_select(&t,i / 2,e[i]);
+    ge_madd(&r,h,&t); ge_p1p1_to_p3(h,&r);
+  }
+}
+
+
+/* ge double scalar mult */
+static void slide(signed char *r,const unsigned char *a)
+{
+  int i;
+  int b;
+  int k;
+
+  for (i = 0;i < 256;++i)
+    r[i] = 1 & (a[i >> 3] >> (i & 7));
+
+  for (i = 0;i < 256;++i)
+    if (r[i]) {
+      for (b = 1;b <= 6 && i + b < 256;++b) {
+        if (r[i + b]) {
+          if (r[i] + (r[i + b] << b) <= 15) {
+            r[i] += r[i + b] << b; r[i + b] = 0;
+          } else if (r[i] - (r[i + b] << b) >= -15) {
+            r[i] -= r[i + b] << b;
+            for (k = i + b;k < 256;++k) {
+              if (!r[k]) {
+                r[k] = 1;
+                break;
+              }
+              r[k] = 0;
+            }
+          } else
+            break;
+        }
+      }
+    }
+}
+
+
+static ge_precomp Bi[8] = {
+ {
+  { 25967493,-14356035,29566456,3660896,-12694345,4014787,27544626,-11754271,-6079156,2047605 },
+  { -12545711,934262,-2722910,3049990,-727428,9406986,12720692,5043384,19500929,-15469378 },
+  { -8738181,4489570,9688441,-14785194,10184609,-12363380,29287919,11864899,-24514362,-4438546 },
+ },
+ {
+  { 15636291,-9688557,24204773,-7912398,616977,-16685262,27787600,-14772189,28944400,-1550024 },
+  { 16568933,4717097,-11556148,-1102322,15682896,-11807043,16354577,-11775962,7689662,11199574 },
+  { 30464156,-5976125,-11779434,-15670865,23220365,15915852,7512774,10017326,-17749093,-9920357 },
+ },
+ {
+  { 10861363,11473154,27284546,1981175,-30064349,12577861,32867885,14515107,-15438304,10819380 },
+  { 4708026,6336745,20377586,9066809,-11272109,6594696,-25653668,12483688,-12668491,5581306 },
+  { 19563160,16186464,-29386857,4097519,10237984,-4348115,28542350,13850243,-23678021,-15815942 },
+ },
+ {
+  { 5153746,9909285,1723747,-2777874,30523605,5516873,19480852,5230134,-23952439,-15175766 },
+  { -30269007,-3463509,7665486,10083793,28475525,1649722,20654025,16520125,30598449,7715701 },
+  { 28881845,14381568,9657904,3680757,-20181635,7843316,-31400660,1370708,29794553,-1409300 },
+ },
+ {
+  { -22518993,-6692182,14201702,-8745502,-23510406,8844726,18474211,-1361450,-13062696,13821877 },
+  { -6455177,-7839871,3374702,-4740862,-27098617,-10571707,31655028,-7212327,18853322,-14220951 },
+  { 4566830,-12963868,-28974889,-12240689,-7602672,-2830569,-8514358,-10431137,2207753,-3209784 },
+ },
+ {
+  { -25154831,-4185821,29681144,7868801,-6854661,-9423865,-12437364,-663000,-31111463,-16132436 },
+  { 25576264,-2703214,7349804,-11814844,16472782,9300885,3844789,15725684,171356,6466918 },
+  { 23103977,13316479,9739013,-16149481,817875,-15038942,8965339,-14088058,-30714912,16193877 },
+ },
+ {
+  { -33521811,3180713,-2394130,14003687,-16903474,-16270840,17238398,4729455,-18074513,9256800 },
+  { -25182317,-4174131,32336398,5036987,-21236817,11360617,22616405,9761698,-19827198,630305 },
+  { -13720693,2639453,-24237460,-7406481,9494427,-5774029,-6554551,-15960994,-2449256,-14291300 },
+ },
+ {
+  { -3151181,-5046075,9282714,6866145,-31907062,-863023,-18940575,15033784,25105118,-7894876 },
+  { -24326370,15950226,-31801215,-14592823,-11662737,-5090925,1573892,-2625887,2198790,-15804619 },
+  { -3099351,10324967,-2241613,7453183,-5446979,-2735503,-13812022,-16236442,-32461234,-12290683 },
+ },
+} ;
+
+
+/*
+r = a * A + b * B
+where a = a[0]+256*a[1]+...+256^31 a[31].
+and b = b[0]+256*b[1]+...+256^31 b[31].
+B is the Ed25519 base point (x,4/5) with x positive.
+*/
+int ge_double_scalarmult_vartime(ge_p2 *r, const unsigned char *a, 
+                                 const ge_p3 *A, const unsigned char *b)
+{
+  signed char aslide[256];
+  signed char bslide[256];
+  ge_cached Ai[8]; /* A,3A,5A,7A,9A,11A,13A,15A */
+  ge_p1p1 t;
+  ge_p3 u;
+  ge_p3 A2;
+  int i;
+
+  slide(aslide,a);
+  slide(bslide,b);
+
+  ge_p3_to_cached(&Ai[0],A);
+  ge_p3_dbl(&t,A); ge_p1p1_to_p3(&A2,&t);
+  ge_add(&t,&A2,&Ai[0]); ge_p1p1_to_p3(&u,&t); ge_p3_to_cached(&Ai[1],&u);
+  ge_add(&t,&A2,&Ai[1]); ge_p1p1_to_p3(&u,&t); ge_p3_to_cached(&Ai[2],&u);
+  ge_add(&t,&A2,&Ai[2]); ge_p1p1_to_p3(&u,&t); ge_p3_to_cached(&Ai[3],&u);
+  ge_add(&t,&A2,&Ai[3]); ge_p1p1_to_p3(&u,&t); ge_p3_to_cached(&Ai[4],&u);
+  ge_add(&t,&A2,&Ai[4]); ge_p1p1_to_p3(&u,&t); ge_p3_to_cached(&Ai[5],&u);
+  ge_add(&t,&A2,&Ai[5]); ge_p1p1_to_p3(&u,&t); ge_p3_to_cached(&Ai[6],&u);
+  ge_add(&t,&A2,&Ai[6]); ge_p1p1_to_p3(&u,&t); ge_p3_to_cached(&Ai[7],&u);
+
+  ge_p2_0(r);
+
+  for (i = 255;i >= 0;--i) {
+    if (aslide[i] || bslide[i]) break;
+  }
+
+  for (;i >= 0;--i) {
+    ge_p2_dbl(&t,r);
+
+    if (aslide[i] > 0) {
+      ge_p1p1_to_p3(&u,&t);
+      ge_add(&t,&u,&Ai[aslide[i]/2]);
+    } else if (aslide[i] < 0) {
+      ge_p1p1_to_p3(&u,&t);
+      ge_sub(&t,&u,&Ai[(-aslide[i])/2]);
+    }
+
+    if (bslide[i] > 0) {
+      ge_p1p1_to_p3(&u,&t);
+      ge_madd(&t,&u,&Bi[bslide[i]/2]);
+    } else if (bslide[i] < 0) {
+      ge_p1p1_to_p3(&u,&t);
+      ge_msub(&t,&u,&Bi[(-bslide[i])/2]);
+    }
+
+    ge_p1p1_to_p2(r,&t);
+  }
+
+  return 0;
+}
+
+
+static const fe d = {
+-10913610,13857413,-15372611,6949391,114729,
+-8787816,-6275908,-3247719,-18696448,-12055116
+} ;
+
+
+static const fe sqrtm1 = {
+-32595792,-7943725,9377950,3500415,12389472,
+-272473,-25146209,-2005654,326686,11406482
+} ;
+
+
+int ge_frombytes_negate_vartime(ge_p3 *h,const unsigned char *s)
+{
+  fe u;
+  fe v;
+  fe v3;
+  fe vxx;
+  fe check;
+
+  fe_frombytes(h->Y,s);
+  fe_1(h->Z);
+  fe_sq(u,h->Y);
+  fe_mul(v,u,d);
+  fe_sub(u,u,h->Z);       /* u = y^2-1 */
+  fe_add(v,v,h->Z);       /* v = dy^2+1 */
+
+
+  fe_sq(v3,v);
+  fe_mul(v3,v3,v);        /* v3 = v^3 */
+  fe_sq(h->X,v3);
+  fe_mul(h->X,h->X,v);
+  fe_mul(h->X,h->X,u);    /* x = uv^7 */
+
+  fe_pow22523(h->X,h->X); /* x = (uv^7)^((q-5)/8) */
+  fe_mul(h->X,h->X,v3);
+  fe_mul(h->X,h->X,u);    /* x = uv^3(uv^7)^((q-5)/8) */
+
+  fe_sq(vxx,h->X);
+  fe_mul(vxx,vxx,v);
+  fe_sub(check,vxx,u);    /* vx^2-u */
+  if (fe_isnonzero(check)) {
+    fe_add(check,vxx,u);  /* vx^2+u */
+    if (fe_isnonzero(check)) return -1;
+    fe_mul(h->X,h->X,sqrtm1);
+  }
+
+  if (fe_isnegative(h->X) == (s[31] >> 7))
+    fe_neg(h->X,h->X);
+
+  fe_mul(h->T,h->X,h->Y);
+  return 0;
+}
+
+
+/* ge madd */
+/*
+r = p + q
+*/
+
+void ge_madd(ge_p1p1 *r,const ge_p3 *p,const ge_precomp *q)
+{
+	fe t0;
+	fe_add(r->X,p->Y,p->X);
+	fe_sub(r->Y,p->Y,p->X);
+	fe_mul(r->Z,r->X,q->yplusx);
+	fe_mul(r->Y,r->Y,q->yminusx);
+	fe_mul(r->T,q->xy2d,p->T);
+	fe_add(t0,p->Z,p->Z);
+	fe_sub(r->X,r->Z,r->Y);
+	fe_add(r->Y,r->Z,r->Y);
+	fe_add(r->Z,t0,r->T);
+	fe_sub(r->T,t0,r->T);
+}
+
+
+/* ge msub */
+
+/*
+r = p - q
+*/
+
+void ge_msub(ge_p1p1 *r,const ge_p3 *p,const ge_precomp *q)
+{
+	fe t0;
+	fe_add(r->X,p->Y,p->X);
+	fe_sub(r->Y,p->Y,p->X);
+	fe_mul(r->Z,r->X,q->yminusx);
+	fe_mul(r->Y,r->Y,q->yplusx);
+	fe_mul(r->T,q->xy2d,p->T);
+	fe_add(t0,p->Z,p->Z);
+	fe_sub(r->X,r->Z,r->Y);
+	fe_add(r->Y,r->Z,r->Y);
+	fe_sub(r->Z,t0,r->T);
+	fe_add(r->T,t0,r->T);
+}
+
+
+/* ge p1p1 to p2 */
+/*
+r = p
+*/
+
+extern void ge_p1p1_to_p2(ge_p2 *r,const ge_p1p1 *p)
+{
+  fe_mul(r->X,p->X,p->T);
+  fe_mul(r->Y,p->Y,p->Z);
+  fe_mul(r->Z,p->Z,p->T);
+}
+
+
+/* ge p1p1 to p3 */
+
+/*
+r = p
+*/
+
+extern void ge_p1p1_to_p3(ge_p3 *r,const ge_p1p1 *p)
+{
+  fe_mul(r->X,p->X,p->T);
+  fe_mul(r->Y,p->Y,p->Z);
+  fe_mul(r->Z,p->Z,p->T);
+  fe_mul(r->T,p->X,p->Y);
+}
+
+
+/* ge p2 0 */
+
+void ge_p2_0(ge_p2 *h)
+{
+  fe_0(h->X);
+  fe_1(h->Y);
+  fe_1(h->Z);
+}
+
+
+/* ge p2 dbl */
+
+/*
+r = 2 * p
+*/
+
+void ge_p2_dbl(ge_p1p1 *r,const ge_p2 *p)
+{
+	fe t0;
+	fe_sq(r->X,p->X);
+	fe_sq(r->Z,p->Y);
+	fe_sq2(r->T,p->Z);
+	fe_add(r->Y,p->X,p->Y);
+	fe_sq(t0,r->Y);
+	fe_add(r->Y,r->Z,r->X);
+	fe_sub(r->Z,r->Z,r->X);
+	fe_sub(r->X,t0,r->Y);
+	fe_sub(r->T,r->T,r->Z);
+}
+
+
+/* ge p3 0 */
+
+void ge_p3_0(ge_p3 *h)
+{
+  fe_0(h->X);
+  fe_1(h->Y);
+  fe_1(h->Z);
+  fe_0(h->T);
+}
+
+
+/* ge p3 dble */
+
+/*
+r = 2 * p
+*/
+
+void ge_p3_dbl(ge_p1p1 *r,const ge_p3 *p)
+{
+  ge_p2 q;
+  ge_p3_to_p2(&q,p);
+  ge_p2_dbl(r,&q);
+}
+
+
+/* ge p3 to cached */
+
+/*
+r = p
+*/
+
+static const fe d2 = {
+-21827239,-5839606,-30745221,13898782,229458,
+15978800,-12551817,-6495438,29715968,9444199
+} ;
+
+
+extern void ge_p3_to_cached(ge_cached *r,const ge_p3 *p)
+{
+  fe_add(r->YplusX,p->Y,p->X);
+  fe_sub(r->YminusX,p->Y,p->X);
+  fe_copy(r->Z,p->Z);
+  fe_mul(r->T2d,p->T,d2);
+}
+
+
+/* ge p3 to p2 */
+/*
+r = p
+*/
+
+extern void ge_p3_to_p2(ge_p2 *r,const ge_p3 *p)
+{
+  fe_copy(r->X,p->X);
+  fe_copy(r->Y,p->Y);
+  fe_copy(r->Z,p->Z);
+}
+
+
+/* ge p3 tobytes */
+void ge_p3_tobytes(unsigned char *s,const ge_p3 *h)
+{
+  fe recip;
+  fe x;
+  fe y;
+
+  fe_invert(recip,h->Z);
+  fe_mul(x,h->X,recip);
+  fe_mul(y,h->Y,recip);
+  fe_tobytes(s,y);
+  s[31] ^= fe_isnegative(x) << 7;
+}
+
+
+/* ge_precomp_0 */
+void ge_precomp_0(ge_precomp *h)
+{
+  fe_1(h->yplusx);
+  fe_1(h->yminusx);
+  fe_0(h->xy2d);
+}
+
+
+/* ge_sub */
+/*
+r = p - q
+*/
+
+void ge_sub(ge_p1p1 *r,const ge_p3 *p,const ge_cached *q)
+{
+	fe t0;
+	fe_add(r->X,p->Y,p->X);
+	fe_sub(r->Y,p->Y,p->X);
+	fe_mul(r->Z,r->X,q->YminusX);
+	fe_mul(r->Y,r->Y,q->YplusX);
+	fe_mul(r->T,q->T2d,p->T);
+	fe_mul(r->X,p->Z,q->Z);
+	fe_add(t0,r->X,r->X);
+	fe_sub(r->X,r->Z,r->Y);
+	fe_add(r->Y,r->Z,r->Y);
+	fe_sub(r->Z,t0,r->T);
+	fe_add(r->T,t0,r->T);
+}
+
+
+/* ge tobytes */
+void ge_tobytes(unsigned char *s,const ge_p2 *h)
+{
+  fe recip;
+  fe x;
+  fe y;
+
+  fe_invert(recip,h->Z);
+  fe_mul(x,h->X,recip);
+  fe_mul(y,h->Y,recip);
+  fe_tobytes(s,y);
+  s[31] ^= fe_isnegative(x) << 7;
+}
+#endif /* HAVE_ED25519 */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/hash.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/hash.c
new file mode 100644
index 0000000..55a1f6a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/hash.c
@@ -0,0 +1,76 @@
+/* hash.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#if !defined(WOLFSSL_TI_HASH)
+
+#include 
+
+#if !defined(NO_MD5)
+void wc_Md5GetHash(Md5* md5, byte* hash)
+{
+    Md5 save = *md5 ;
+    wc_Md5Final(md5, hash) ;
+    *md5 = save ;
+}
+
+WOLFSSL_API void wc_Md5RestorePos(Md5* m1, Md5* m2) {
+    *m1 = *m2 ;
+}
+#endif
+
+#if !defined(NO_SHA)
+int wc_ShaGetHash(Sha* sha, byte* hash)
+{
+    int ret ;
+    Sha save = *sha ;
+    ret = wc_ShaFinal(sha, hash) ;
+    *sha = save ;
+    return ret ;
+}
+
+WOLFSSL_API void wc_ShaRestorePos(Sha* s1, Sha* s2) {
+    *s1 = *s2 ;
+}
+#endif
+
+#if !defined(NO_SHA256)
+int wc_Sha256GetHash(Sha256* sha256, byte* hash)
+{
+    int ret ;
+    Sha256 save = *sha256 ;
+    ret = wc_Sha256Final(sha256, hash) ;
+    *sha256 = save ;
+    return ret ;
+}
+
+WOLFSSL_API void wc_Sha256RestorePos(Sha256* s1, Sha256* s2) {
+    *s1 = *s2 ;
+}
+#endif
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/hc128.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/hc128.c
new file mode 100644
index 0000000..bcfa148
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/hc128.c
@@ -0,0 +1,399 @@
+/* hc128.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifdef HAVE_HC128
+
+#include 
+#include 
+#include 
+#ifdef NO_INLINE
+    #include 
+		#include 
+#else
+    #include 
+#endif
+
+
+#ifdef BIG_ENDIAN_ORDER
+    #define LITTLE32(x) ByteReverseWord32(x)
+#else
+    #define LITTLE32(x) (x)
+#endif
+
+
+/*h1 function*/
+#define h1(ctx, x, y) {                         \
+     byte a,c;                                  \
+     a = (byte) (x);                            \
+     c = (byte) ((x) >> 16);                    \
+     y = (ctx->T[512+a])+(ctx->T[512+256+c]);   \
+}
+
+/*h2 function*/
+#define h2(ctx, x, y) {                         \
+     byte a,c;                                  \
+     a = (byte) (x);                            \
+     c = (byte) ((x) >> 16);                    \
+     y = (ctx->T[a])+(ctx->T[256+c]);           \
+}
+
+/*one step of HC-128, update P and generate 32 bits keystream*/
+#define step_P(ctx,u,v,a,b,c,d,n){              \
+     word32 tem0,tem1,tem2,tem3;                \
+     h1((ctx),(ctx->X[(d)]),tem3);              \
+     tem0 = rotrFixed((ctx->T[(v)]),23);        \
+     tem1 = rotrFixed((ctx->X[(c)]),10);        \
+     tem2 = rotrFixed((ctx->X[(b)]),8);         \
+     (ctx->T[(u)]) += tem2+(tem0 ^ tem1);       \
+     (ctx->X[(a)]) = (ctx->T[(u)]);             \
+     (n) = tem3 ^ (ctx->T[(u)]) ;               \
+}       
+
+/*one step of HC-128, update Q and generate 32 bits keystream*/
+#define step_Q(ctx,u,v,a,b,c,d,n){              \
+     word32 tem0,tem1,tem2,tem3;                \
+     h2((ctx),(ctx->Y[(d)]),tem3);              \
+     tem0 = rotrFixed((ctx->T[(v)]),(32-23));   \
+     tem1 = rotrFixed((ctx->Y[(c)]),(32-10));   \
+     tem2 = rotrFixed((ctx->Y[(b)]),(32-8));    \
+     (ctx->T[(u)]) += tem2 + (tem0 ^ tem1);     \
+     (ctx->Y[(a)]) = (ctx->T[(u)]);             \
+     (n) = tem3 ^ (ctx->T[(u)]) ;               \
+}   
+
+/*16 steps of HC-128, generate 512 bits keystream*/
+static void generate_keystream(HC128* ctx, word32* keystream)  
+{
+   word32 cc,dd;
+   cc = ctx->counter1024 & 0x1ff;
+   dd = (cc+16)&0x1ff;
+
+   if (ctx->counter1024 < 512)	
+   {   		
+      ctx->counter1024 = (ctx->counter1024 + 16) & 0x3ff;
+      step_P(ctx, cc+0, cc+1, 0, 6, 13,4, keystream[0]);
+      step_P(ctx, cc+1, cc+2, 1, 7, 14,5, keystream[1]);
+      step_P(ctx, cc+2, cc+3, 2, 8, 15,6, keystream[2]);
+      step_P(ctx, cc+3, cc+4, 3, 9, 0, 7, keystream[3]);
+      step_P(ctx, cc+4, cc+5, 4, 10,1, 8, keystream[4]);
+      step_P(ctx, cc+5, cc+6, 5, 11,2, 9, keystream[5]);
+      step_P(ctx, cc+6, cc+7, 6, 12,3, 10,keystream[6]);
+      step_P(ctx, cc+7, cc+8, 7, 13,4, 11,keystream[7]);
+      step_P(ctx, cc+8, cc+9, 8, 14,5, 12,keystream[8]);
+      step_P(ctx, cc+9, cc+10,9, 15,6, 13,keystream[9]);
+      step_P(ctx, cc+10,cc+11,10,0, 7, 14,keystream[10]);
+      step_P(ctx, cc+11,cc+12,11,1, 8, 15,keystream[11]);
+      step_P(ctx, cc+12,cc+13,12,2, 9, 0, keystream[12]);
+      step_P(ctx, cc+13,cc+14,13,3, 10,1, keystream[13]);
+      step_P(ctx, cc+14,cc+15,14,4, 11,2, keystream[14]);
+      step_P(ctx, cc+15,dd+0, 15,5, 12,3, keystream[15]);
+   }
+   else				    
+   {
+	  ctx->counter1024 = (ctx->counter1024 + 16) & 0x3ff;
+      step_Q(ctx, 512+cc+0, 512+cc+1, 0, 6, 13,4, keystream[0]);
+      step_Q(ctx, 512+cc+1, 512+cc+2, 1, 7, 14,5, keystream[1]);
+      step_Q(ctx, 512+cc+2, 512+cc+3, 2, 8, 15,6, keystream[2]);
+      step_Q(ctx, 512+cc+3, 512+cc+4, 3, 9, 0, 7, keystream[3]);
+      step_Q(ctx, 512+cc+4, 512+cc+5, 4, 10,1, 8, keystream[4]);
+      step_Q(ctx, 512+cc+5, 512+cc+6, 5, 11,2, 9, keystream[5]);
+      step_Q(ctx, 512+cc+6, 512+cc+7, 6, 12,3, 10,keystream[6]);
+      step_Q(ctx, 512+cc+7, 512+cc+8, 7, 13,4, 11,keystream[7]);
+      step_Q(ctx, 512+cc+8, 512+cc+9, 8, 14,5, 12,keystream[8]);
+      step_Q(ctx, 512+cc+9, 512+cc+10,9, 15,6, 13,keystream[9]);
+      step_Q(ctx, 512+cc+10,512+cc+11,10,0, 7, 14,keystream[10]);
+      step_Q(ctx, 512+cc+11,512+cc+12,11,1, 8, 15,keystream[11]);
+      step_Q(ctx, 512+cc+12,512+cc+13,12,2, 9, 0, keystream[12]);
+      step_Q(ctx, 512+cc+13,512+cc+14,13,3, 10,1, keystream[13]);
+      step_Q(ctx, 512+cc+14,512+cc+15,14,4, 11,2, keystream[14]);
+      step_Q(ctx, 512+cc+15,512+dd+0, 15,5, 12,3, keystream[15]);
+   }
+}
+
+
+/* The following defines the initialization functions */
+#define f1(x)  (rotrFixed((x),7)  ^ rotrFixed((x),18) ^ ((x) >> 3))
+#define f2(x)  (rotrFixed((x),17) ^ rotrFixed((x),19) ^ ((x) >> 10))
+
+/*update table P*/
+#define update_P(ctx,u,v,a,b,c,d){                  \
+     word32 tem0,tem1,tem2,tem3;                    \
+     tem0 = rotrFixed((ctx->T[(v)]),23);            \
+     tem1 = rotrFixed((ctx->X[(c)]),10);            \
+     tem2 = rotrFixed((ctx->X[(b)]),8);             \
+     h1((ctx),(ctx->X[(d)]),tem3);                  \
+     (ctx->T[(u)]) = ((ctx->T[(u)]) + tem2+(tem0^tem1)) ^ tem3;     \
+     (ctx->X[(a)]) = (ctx->T[(u)]);                 \
+}  
+
+/*update table Q*/
+#define update_Q(ctx,u,v,a,b,c,d){                  \
+     word32 tem0,tem1,tem2,tem3;                    \
+     tem0 = rotrFixed((ctx->T[(v)]),(32-23));       \
+     tem1 = rotrFixed((ctx->Y[(c)]),(32-10));       \
+     tem2 = rotrFixed((ctx->Y[(b)]),(32-8));        \
+     h2((ctx),(ctx->Y[(d)]),tem3);                  \
+     (ctx->T[(u)]) = ((ctx->T[(u)]) + tem2+(tem0^tem1)) ^ tem3;     \
+     (ctx->Y[(a)]) = (ctx->T[(u)]);                 \
+}     
+
+/*16 steps of HC-128, without generating keystream, */
+/*but use the outputs to update P and Q*/
+static void setup_update(HC128* ctx)  /*each time 16 steps*/
+{
+   word32 cc,dd;
+   cc = ctx->counter1024 & 0x1ff;
+   dd = (cc+16)&0x1ff;
+
+   if (ctx->counter1024 < 512)	
+   {   		
+      ctx->counter1024 = (ctx->counter1024 + 16) & 0x3ff;
+      update_P(ctx, cc+0, cc+1, 0, 6, 13, 4);
+      update_P(ctx, cc+1, cc+2, 1, 7, 14, 5);
+      update_P(ctx, cc+2, cc+3, 2, 8, 15, 6);
+      update_P(ctx, cc+3, cc+4, 3, 9, 0,  7);
+      update_P(ctx, cc+4, cc+5, 4, 10,1,  8);
+      update_P(ctx, cc+5, cc+6, 5, 11,2,  9);
+      update_P(ctx, cc+6, cc+7, 6, 12,3,  10);
+      update_P(ctx, cc+7, cc+8, 7, 13,4,  11);
+      update_P(ctx, cc+8, cc+9, 8, 14,5,  12);
+      update_P(ctx, cc+9, cc+10,9, 15,6,  13);
+      update_P(ctx, cc+10,cc+11,10,0, 7,  14);
+      update_P(ctx, cc+11,cc+12,11,1, 8,  15);
+      update_P(ctx, cc+12,cc+13,12,2, 9,  0);
+      update_P(ctx, cc+13,cc+14,13,3, 10, 1);
+      update_P(ctx, cc+14,cc+15,14,4, 11, 2);
+      update_P(ctx, cc+15,dd+0, 15,5, 12, 3);   
+   }
+   else				    
+   {
+      ctx->counter1024 = (ctx->counter1024 + 16) & 0x3ff;
+      update_Q(ctx, 512+cc+0, 512+cc+1, 0, 6, 13, 4);
+      update_Q(ctx, 512+cc+1, 512+cc+2, 1, 7, 14, 5);
+      update_Q(ctx, 512+cc+2, 512+cc+3, 2, 8, 15, 6);
+      update_Q(ctx, 512+cc+3, 512+cc+4, 3, 9, 0,  7);
+      update_Q(ctx, 512+cc+4, 512+cc+5, 4, 10,1,  8);
+      update_Q(ctx, 512+cc+5, 512+cc+6, 5, 11,2,  9);
+      update_Q(ctx, 512+cc+6, 512+cc+7, 6, 12,3,  10);
+      update_Q(ctx, 512+cc+7, 512+cc+8, 7, 13,4,  11);
+      update_Q(ctx, 512+cc+8, 512+cc+9, 8, 14,5,  12);
+      update_Q(ctx, 512+cc+9, 512+cc+10,9, 15,6,  13);
+      update_Q(ctx, 512+cc+10,512+cc+11,10,0, 7,  14);
+      update_Q(ctx, 512+cc+11,512+cc+12,11,1, 8,  15);
+      update_Q(ctx, 512+cc+12,512+cc+13,12,2, 9,  0);
+      update_Q(ctx, 512+cc+13,512+cc+14,13,3, 10, 1);
+      update_Q(ctx, 512+cc+14,512+cc+15,14,4, 11, 2);
+      update_Q(ctx, 512+cc+15,512+dd+0, 15,5, 12, 3); 
+   }       
+}
+
+
+/* for the 128-bit key:  key[0]...key[15]
+*  key[0] is the least significant byte of ctx->key[0] (K_0);
+*  key[3] is the most significant byte of ctx->key[0]  (K_0);
+*  ...
+*  key[12] is the least significant byte of ctx->key[3] (K_3)
+*  key[15] is the most significant byte of ctx->key[3]  (K_3)
+*
+*  for the 128-bit iv:  iv[0]...iv[15]
+*  iv[0] is the least significant byte of ctx->iv[0] (IV_0);
+*  iv[3] is the most significant byte of ctx->iv[0]  (IV_0);
+*  ...
+*  iv[12] is the least significant byte of ctx->iv[3] (IV_3)
+*  iv[15] is the most significant byte of ctx->iv[3]  (IV_3)
+*/
+
+
+
+static void Hc128_SetIV(HC128* ctx, const byte* inIv)
+{ 
+    word32 i;
+    word32 iv[4];
+
+    if (inIv)
+        XMEMCPY(iv, inIv, sizeof(iv));
+    else
+        XMEMSET(iv,    0, sizeof(iv));
+    
+	for (i = 0; i < (128 >> 5); i++)
+        ctx->iv[i] = LITTLE32(iv[i]);
+	
+    for (; i < 8; i++) ctx->iv[i] = ctx->iv[i-4];
+  
+    /* expand the key and IV into the table T */ 
+    /* (expand the key and IV into the table P and Q) */ 
+	
+	for (i = 0; i < 8;  i++)   ctx->T[i] = ctx->key[i];
+	for (i = 8; i < 16; i++)   ctx->T[i] = ctx->iv[i-8];
+
+    for (i = 16; i < (256+16); i++) 
+		ctx->T[i] = f2(ctx->T[i-2]) + ctx->T[i-7] + f1(ctx->T[i-15]) +
+                                                       ctx->T[i-16]+i;
+    
+	for (i = 0; i < 16;  i++)  ctx->T[i] = ctx->T[256+i];
+
+	for (i = 16; i < 1024; i++) 
+		ctx->T[i] = f2(ctx->T[i-2]) + ctx->T[i-7] + f1(ctx->T[i-15]) +
+                                                       ctx->T[i-16]+256+i;
+    
+    /* initialize counter1024, X and Y */
+	ctx->counter1024 = 0;
+	for (i = 0; i < 16; i++) ctx->X[i] = ctx->T[512-16+i];
+    for (i = 0; i < 16; i++) ctx->Y[i] = ctx->T[512+512-16+i];
+    
+    /* run the cipher 1024 steps before generating the output */
+	for (i = 0; i < 64; i++)  setup_update(ctx);  
+}
+
+
+static INLINE int DoKey(HC128* ctx, const byte* key, const byte* iv)
+{ 
+  word32 i;  
+
+  /* Key size in bits 128 */ 
+  for (i = 0; i < (128 >> 5); i++)
+      ctx->key[i] = LITTLE32(((word32*)key)[i]);
+ 
+  for ( ; i < 8 ; i++) ctx->key[i] = ctx->key[i-4];
+
+  Hc128_SetIV(ctx, iv);
+
+  return 0;
+}
+
+
+/* Key setup */
+int wc_Hc128_SetKey(HC128* ctx, const byte* key, const byte* iv)
+{
+#ifdef XSTREAM_ALIGN
+    if ((wolfssl_word)key % 4) {
+        int alignKey[4];
+
+        /* iv gets aligned in SetIV */
+        WOLFSSL_MSG("Hc128SetKey unaligned key");
+
+        XMEMCPY(alignKey, key, sizeof(alignKey));
+
+        return DoKey(ctx, (const byte*)alignKey, iv);
+    }
+#endif /* XSTREAM_ALIGN */
+
+    return DoKey(ctx, key, iv);
+}
+
+
+
+/* The following defines the encryption of data stream */
+static INLINE int DoProcess(HC128* ctx, byte* output, const byte* input,
+                            word32 msglen)
+{
+  word32 i, keystream[16];
+
+  for ( ; msglen >= 64; msglen -= 64, input += 64, output += 64)
+  {
+	  generate_keystream(ctx, keystream);
+
+      /* unroll loop */
+	  ((word32*)output)[0]  = ((word32*)input)[0]  ^ LITTLE32(keystream[0]);
+	  ((word32*)output)[1]  = ((word32*)input)[1]  ^ LITTLE32(keystream[1]);
+	  ((word32*)output)[2]  = ((word32*)input)[2]  ^ LITTLE32(keystream[2]);
+	  ((word32*)output)[3]  = ((word32*)input)[3]  ^ LITTLE32(keystream[3]);
+	  ((word32*)output)[4]  = ((word32*)input)[4]  ^ LITTLE32(keystream[4]);
+	  ((word32*)output)[5]  = ((word32*)input)[5]  ^ LITTLE32(keystream[5]);
+	  ((word32*)output)[6]  = ((word32*)input)[6]  ^ LITTLE32(keystream[6]);
+	  ((word32*)output)[7]  = ((word32*)input)[7]  ^ LITTLE32(keystream[7]);
+	  ((word32*)output)[8]  = ((word32*)input)[8]  ^ LITTLE32(keystream[8]);
+	  ((word32*)output)[9]  = ((word32*)input)[9]  ^ LITTLE32(keystream[9]);
+	  ((word32*)output)[10] = ((word32*)input)[10] ^ LITTLE32(keystream[10]);
+	  ((word32*)output)[11] = ((word32*)input)[11] ^ LITTLE32(keystream[11]);
+	  ((word32*)output)[12] = ((word32*)input)[12] ^ LITTLE32(keystream[12]);
+	  ((word32*)output)[13] = ((word32*)input)[13] ^ LITTLE32(keystream[13]);
+	  ((word32*)output)[14] = ((word32*)input)[14] ^ LITTLE32(keystream[14]);
+	  ((word32*)output)[15] = ((word32*)input)[15] ^ LITTLE32(keystream[15]);
+  }
+
+  if (msglen > 0)
+  {
+      XMEMSET(keystream, 0, sizeof(keystream)); /* hush the static analysis */
+      generate_keystream(ctx, keystream);
+
+#ifdef BIG_ENDIAN_ORDER
+      {
+          word32 wordsLeft = msglen / sizeof(word32);
+          if (msglen % sizeof(word32)) wordsLeft++;
+          
+          ByteReverseWords(keystream, keystream, wordsLeft * sizeof(word32));
+      }
+#endif
+
+      for (i = 0; i < msglen; i++)
+	      output[i] = input[i] ^ ((byte*)keystream)[i];
+  }
+
+  return 0;
+}
+
+
+/* Encrypt/decrypt a message of any size */
+int wc_Hc128_Process(HC128* ctx, byte* output, const byte* input, word32 msglen)
+{
+#ifdef XSTREAM_ALIGN
+    if ((wolfssl_word)input % 4 || (wolfssl_word)output % 4) {
+        #ifndef NO_WOLFSSL_ALLOC_ALIGN
+            byte* tmp;
+            WOLFSSL_MSG("Hc128Process unaligned");
+
+            tmp = (byte*)XMALLOC(msglen, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            if (tmp == NULL) return MEMORY_E;
+
+            XMEMCPY(tmp, input, msglen);
+            DoProcess(ctx, tmp, tmp, msglen);
+            XMEMCPY(output, tmp, msglen);
+
+            XFREE(tmp, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+
+            return 0;
+        #else
+            return BAD_ALIGN_E;
+        #endif
+    }
+#endif /* XSTREAM_ALIGN */
+
+    return DoProcess(ctx, output, input, msglen);
+}
+
+
+#else  /* HAVE_HC128 */
+
+
+#ifdef _MSC_VER
+    /* 4206 warning for blank file */
+    #pragma warning(disable: 4206)
+#endif
+
+
+#endif /* HAVE_HC128 */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/hmac.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/hmac.c
new file mode 100644
index 0000000..242adfa
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/hmac.c
@@ -0,0 +1,879 @@
+/* hmac.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifndef NO_HMAC
+
+#include 
+
+#ifdef HAVE_FIPS
+/* does init */
+int wc_HmacSetKey(Hmac* hmac, int type, const byte* key, word32 keySz)
+{
+    return HmacSetKey_fips(hmac, type, key, keySz);
+}
+
+
+int wc_HmacUpdate(Hmac* hmac, const byte* in, word32 sz)
+{
+    return HmacUpdate_fips(hmac, in, sz);
+}
+
+
+int wc_HmacFinal(Hmac* hmac, byte* out)
+{
+    return HmacFinal_fips(hmac, out);
+}
+
+
+#ifdef HAVE_CAVIUM
+    int  wc_HmacInitCavium(Hmac* hmac, int i)
+    {
+        return HmacInitCavium(hmac, i);
+    }
+
+
+    void wc_HmacFreeCavium(Hmac* hmac)
+    {
+        HmacFreeCavium(hmac);
+    }
+#endif
+
+int wolfSSL_GetHmacMaxSize(void)
+{
+    return CyaSSL_GetHmacMaxSize();
+}
+
+#ifdef HAVE_HKDF
+
+int wc_HKDF(int type, const byte* inKey, word32 inKeySz,
+                    const byte* salt, word32 saltSz,
+                    const byte* info, word32 infoSz,
+                    byte* out, word32 outSz)
+{
+    return HKDF(type, inKey, inKeySz, salt, saltSz, info, infoSz, out, outSz);
+}
+
+
+#endif /* HAVE_HKDF */
+#else /* else build without fips */
+#ifdef WOLFSSL_PIC32MZ_HASH
+
+#define wc_InitMd5   wc_InitMd5_sw
+#define wc_Md5Update wc_Md5Update_sw
+#define wc_Md5Final  wc_Md5Final_sw
+
+#define wc_InitSha   wc_InitSha_sw
+#define wc_ShaUpdate wc_ShaUpdate_sw
+#define wc_ShaFinal  wc_ShaFinal_sw
+
+#define wc_InitSha256   wc_InitSha256_sw
+#define wc_Sha256Update wc_Sha256Update_sw
+#define wc_Sha256Final  wc_Sha256Final_sw
+
+#endif
+
+#ifdef HAVE_FIPS
+    /* set NO_WRAPPERS before headers, use direct internal f()s not wrappers */
+    #define FIPS_NO_WRAPPERS
+#endif
+
+#include 
+
+
+#ifdef HAVE_CAVIUM
+    static void HmacCaviumFinal(Hmac* hmac, byte* hash);
+    static void HmacCaviumUpdate(Hmac* hmac, const byte* msg, word32 length);
+    static void HmacCaviumSetKey(Hmac* hmac, int type, const byte* key,
+                                 word32 length);
+#endif
+
+static int InitHmac(Hmac* hmac, int type)
+{
+    int ret = 0;
+
+    hmac->innerHashKeyed = 0;
+    hmac->macType = (byte)type;
+
+    if (!(type == MD5 || type == SHA    || type == SHA256 || type == SHA384
+                      || type == SHA512 || type == BLAKE2B_ID))
+        return BAD_FUNC_ARG;
+
+    switch (type) {
+        #ifndef NO_MD5
+        case MD5:
+            wc_InitMd5(&hmac->hash.md5);
+        break;
+        #endif
+
+        #ifndef NO_SHA
+        case SHA:
+            ret = wc_InitSha(&hmac->hash.sha);
+        break;
+        #endif
+        
+        #ifndef NO_SHA256
+        case SHA256:
+            ret = wc_InitSha256(&hmac->hash.sha256);
+        break;
+        #endif
+        
+        #ifdef WOLFSSL_SHA384
+        case SHA384:
+            ret = wc_InitSha384(&hmac->hash.sha384);
+        break;
+        #endif
+        
+        #ifdef WOLFSSL_SHA512
+        case SHA512:
+            ret = wc_InitSha512(&hmac->hash.sha512);
+        break;
+        #endif
+        
+        #ifdef HAVE_BLAKE2 
+        case BLAKE2B_ID:
+            ret = wc_InitBlake2b(&hmac->hash.blake2b, BLAKE2B_256);
+        break;
+        #endif
+        
+        default:
+            return BAD_FUNC_ARG;
+    }
+
+    return ret;
+}
+
+
+int wc_HmacSetKey(Hmac* hmac, int type, const byte* key, word32 length)
+{
+    byte*  ip = (byte*) hmac->ipad;
+    byte*  op = (byte*) hmac->opad;
+    word32 i, hmac_block_size = 0;
+    int    ret;
+
+#ifdef HAVE_CAVIUM
+    if (hmac->magic == WOLFSSL_HMAC_CAVIUM_MAGIC)
+        return HmacCaviumSetKey(hmac, type, key, length);
+#endif
+
+    ret = InitHmac(hmac, type);
+    if (ret != 0)
+        return ret;
+
+#ifdef HAVE_FIPS
+    if (length < HMAC_FIPS_MIN_KEY)
+        return HMAC_MIN_KEYLEN_E;
+#endif
+
+    switch (hmac->macType) {
+        #ifndef NO_MD5
+        case MD5:
+        {
+            hmac_block_size = MD5_BLOCK_SIZE;
+            if (length <= MD5_BLOCK_SIZE) {
+                XMEMCPY(ip, key, length);
+            }
+            else {
+                wc_Md5Update(&hmac->hash.md5, key, length);
+                wc_Md5Final(&hmac->hash.md5, ip);
+                length = MD5_DIGEST_SIZE;
+            }
+        }
+        break;
+        #endif
+
+        #ifndef NO_SHA
+        case SHA:
+        {
+            hmac_block_size = SHA_BLOCK_SIZE;
+            if (length <= SHA_BLOCK_SIZE) {
+                XMEMCPY(ip, key, length);
+            }
+            else {
+                wc_ShaUpdate(&hmac->hash.sha, key, length);
+                wc_ShaFinal(&hmac->hash.sha, ip);
+                length = SHA_DIGEST_SIZE;
+            }
+        }
+        break;
+        #endif
+
+        #ifndef NO_SHA256
+        case SHA256:
+        {
+    		hmac_block_size = SHA256_BLOCK_SIZE;
+            if (length <= SHA256_BLOCK_SIZE) {
+                XMEMCPY(ip, key, length);
+            }
+            else {
+                ret = wc_Sha256Update(&hmac->hash.sha256, key, length);
+                if (ret != 0)
+                    return ret;
+
+                ret = wc_Sha256Final(&hmac->hash.sha256, ip);
+                if (ret != 0)
+                    return ret;
+
+                length = SHA256_DIGEST_SIZE;
+            }
+        }
+        break;
+        #endif
+
+        #ifdef WOLFSSL_SHA384
+        case SHA384:
+        {
+            hmac_block_size = SHA384_BLOCK_SIZE;
+            if (length <= SHA384_BLOCK_SIZE) {
+                XMEMCPY(ip, key, length);
+            }
+            else {
+                ret = wc_Sha384Update(&hmac->hash.sha384, key, length);
+                if (ret != 0)
+                    return ret;
+
+                ret = wc_Sha384Final(&hmac->hash.sha384, ip);
+                if (ret != 0)
+                    return ret;
+
+                length = SHA384_DIGEST_SIZE;
+            }
+        }
+        break;
+        #endif
+
+        #ifdef WOLFSSL_SHA512
+        case SHA512:
+        {
+            hmac_block_size = SHA512_BLOCK_SIZE;
+            if (length <= SHA512_BLOCK_SIZE) {
+                XMEMCPY(ip, key, length);
+            }
+            else {
+                ret = wc_Sha512Update(&hmac->hash.sha512, key, length);
+                if (ret != 0)
+                    return ret;
+
+                ret = wc_Sha512Final(&hmac->hash.sha512, ip);
+                if (ret != 0)
+                    return ret;
+
+                length = SHA512_DIGEST_SIZE;
+            }
+        }
+        break;
+        #endif
+
+        #ifdef HAVE_BLAKE2 
+        case BLAKE2B_ID:
+        {
+            hmac_block_size = BLAKE2B_BLOCKBYTES;
+            if (length <= BLAKE2B_BLOCKBYTES) {
+                XMEMCPY(ip, key, length);
+            }
+            else {
+                ret = wc_Blake2bUpdate(&hmac->hash.blake2b, key, length);
+                if (ret != 0)
+                    return ret;
+
+                ret = wc_Blake2bFinal(&hmac->hash.blake2b, ip, BLAKE2B_256);
+                if (ret != 0)
+                    return ret;
+
+                length = BLAKE2B_256;
+            }
+        }
+        break;
+        #endif
+
+        default:
+            return BAD_FUNC_ARG;
+    }
+    if (length < hmac_block_size)
+        XMEMSET(ip + length, 0, hmac_block_size - length);
+
+    for(i = 0; i < hmac_block_size; i++) {
+        op[i] = ip[i] ^ OPAD;
+        ip[i] ^= IPAD;
+    }
+    return 0;
+}
+
+
+static int HmacKeyInnerHash(Hmac* hmac)
+{
+    int ret = 0;
+
+    switch (hmac->macType) {
+        #ifndef NO_MD5
+        case MD5:
+            wc_Md5Update(&hmac->hash.md5, (byte*) hmac->ipad, MD5_BLOCK_SIZE);
+        break;
+        #endif
+
+        #ifndef NO_SHA
+        case SHA:
+            wc_ShaUpdate(&hmac->hash.sha, (byte*) hmac->ipad, SHA_BLOCK_SIZE);
+        break;
+        #endif
+
+        #ifndef NO_SHA256
+        case SHA256:
+            ret = wc_Sha256Update(&hmac->hash.sha256,
+                                         (byte*) hmac->ipad, SHA256_BLOCK_SIZE);
+            if (ret != 0)
+                return ret;
+        break;
+        #endif
+
+        #ifdef WOLFSSL_SHA384
+        case SHA384:
+            ret = wc_Sha384Update(&hmac->hash.sha384,
+                                         (byte*) hmac->ipad, SHA384_BLOCK_SIZE);
+            if (ret != 0)
+                return ret;
+        break;
+        #endif
+
+        #ifdef WOLFSSL_SHA512
+        case SHA512:
+            ret = wc_Sha512Update(&hmac->hash.sha512,
+                                         (byte*) hmac->ipad, SHA512_BLOCK_SIZE);
+            if (ret != 0)
+                return ret;
+        break;
+        #endif
+
+        #ifdef HAVE_BLAKE2 
+        case BLAKE2B_ID:
+            ret = wc_Blake2bUpdate(&hmac->hash.blake2b,
+                                         (byte*) hmac->ipad,BLAKE2B_BLOCKBYTES);
+            if (ret != 0)
+                return ret;
+        break;
+        #endif
+
+        default:
+        break;
+    }
+
+    hmac->innerHashKeyed = 1;
+
+    return ret;
+}
+
+
+int wc_HmacUpdate(Hmac* hmac, const byte* msg, word32 length)
+{
+    int ret;
+
+#ifdef HAVE_CAVIUM
+    if (hmac->magic == WOLFSSL_HMAC_CAVIUM_MAGIC)
+        return HmacCaviumUpdate(hmac, msg, length);
+#endif
+
+    if (!hmac->innerHashKeyed) {
+        ret = HmacKeyInnerHash(hmac);
+        if (ret != 0)
+            return ret;
+    }
+
+    switch (hmac->macType) {
+        #ifndef NO_MD5
+        case MD5:
+            wc_Md5Update(&hmac->hash.md5, msg, length);
+        break;
+        #endif
+
+        #ifndef NO_SHA
+        case SHA:
+            wc_ShaUpdate(&hmac->hash.sha, msg, length);
+        break;
+        #endif
+
+        #ifndef NO_SHA256
+        case SHA256:
+            ret = wc_Sha256Update(&hmac->hash.sha256, msg, length);
+            if (ret != 0)
+                return ret;
+        break;
+        #endif
+
+        #ifdef WOLFSSL_SHA384
+        case SHA384:
+            ret = wc_Sha384Update(&hmac->hash.sha384, msg, length);
+            if (ret != 0)
+                return ret;
+        break;
+        #endif
+
+        #ifdef WOLFSSL_SHA512
+        case SHA512:
+            ret = wc_Sha512Update(&hmac->hash.sha512, msg, length);
+            if (ret != 0)
+                return ret;
+        break;
+        #endif
+
+        #ifdef HAVE_BLAKE2 
+        case BLAKE2B_ID:
+            ret = wc_Blake2bUpdate(&hmac->hash.blake2b, msg, length);
+            if (ret != 0)
+                return ret;
+        break;
+        #endif
+
+        default:
+        break;
+    }
+
+    return 0;
+}
+
+
+int wc_HmacFinal(Hmac* hmac, byte* hash)
+{
+    int ret;
+
+#ifdef HAVE_CAVIUM
+    if (hmac->magic == WOLFSSL_HMAC_CAVIUM_MAGIC)
+        return HmacCaviumFinal(hmac, hash);
+#endif
+
+    if (!hmac->innerHashKeyed) {
+        ret = HmacKeyInnerHash(hmac);
+        if (ret != 0)
+            return ret;
+    }
+
+    switch (hmac->macType) {
+        #ifndef NO_MD5
+        case MD5:
+        {
+            wc_Md5Final(&hmac->hash.md5, (byte*) hmac->innerHash);
+
+            wc_Md5Update(&hmac->hash.md5, (byte*) hmac->opad, MD5_BLOCK_SIZE);
+            wc_Md5Update(&hmac->hash.md5,
+                                     (byte*) hmac->innerHash, MD5_DIGEST_SIZE);
+
+            wc_Md5Final(&hmac->hash.md5, hash);
+        }
+        break;
+        #endif
+
+        #ifndef NO_SHA
+        case SHA:
+        {
+            wc_ShaFinal(&hmac->hash.sha, (byte*) hmac->innerHash);
+
+            wc_ShaUpdate(&hmac->hash.sha, (byte*) hmac->opad, SHA_BLOCK_SIZE);
+            wc_ShaUpdate(&hmac->hash.sha,
+                                     (byte*) hmac->innerHash, SHA_DIGEST_SIZE);
+
+            wc_ShaFinal(&hmac->hash.sha, hash);
+        }
+        break;
+        #endif
+
+        #ifndef NO_SHA256
+        case SHA256:
+        {
+            ret = wc_Sha256Final(&hmac->hash.sha256, (byte*) hmac->innerHash);
+            if (ret != 0)
+                return ret;
+
+            ret = wc_Sha256Update(&hmac->hash.sha256,
+                                (byte*) hmac->opad, SHA256_BLOCK_SIZE);
+            if (ret != 0)
+                return ret;
+
+            ret = wc_Sha256Update(&hmac->hash.sha256,
+                                (byte*) hmac->innerHash, SHA256_DIGEST_SIZE);
+            if (ret != 0)
+                return ret;
+
+            ret = wc_Sha256Final(&hmac->hash.sha256, hash);
+            if (ret != 0)
+                return ret;
+        }
+        break;
+        #endif
+
+        #ifdef WOLFSSL_SHA384
+        case SHA384:
+        {
+            ret = wc_Sha384Final(&hmac->hash.sha384, (byte*) hmac->innerHash);
+            if (ret != 0)
+                return ret;
+
+            ret = wc_Sha384Update(&hmac->hash.sha384,
+                                 (byte*) hmac->opad, SHA384_BLOCK_SIZE);
+            if (ret != 0)
+                return ret;
+
+            ret = wc_Sha384Update(&hmac->hash.sha384,
+                                 (byte*) hmac->innerHash, SHA384_DIGEST_SIZE);
+            if (ret != 0)
+                return ret;
+
+            ret = wc_Sha384Final(&hmac->hash.sha384, hash);
+            if (ret != 0)
+                return ret;
+        }
+        break;
+        #endif
+
+        #ifdef WOLFSSL_SHA512
+        case SHA512:
+        {
+            ret = wc_Sha512Final(&hmac->hash.sha512, (byte*) hmac->innerHash);
+            if (ret != 0)
+                return ret;
+
+            ret = wc_Sha512Update(&hmac->hash.sha512,
+                                 (byte*) hmac->opad, SHA512_BLOCK_SIZE);
+            if (ret != 0)
+                return ret;
+
+            ret = wc_Sha512Update(&hmac->hash.sha512,
+                                 (byte*) hmac->innerHash, SHA512_DIGEST_SIZE);
+            if (ret != 0)
+                return ret;
+
+            ret = wc_Sha512Final(&hmac->hash.sha512, hash);
+            if (ret != 0)
+                return ret;
+        }
+        break;
+        #endif
+
+        #ifdef HAVE_BLAKE2 
+        case BLAKE2B_ID:
+        {
+            ret = wc_Blake2bFinal(&hmac->hash.blake2b, (byte*) hmac->innerHash,
+                         BLAKE2B_256);
+            if (ret != 0)
+                return ret;
+
+            ret = wc_Blake2bUpdate(&hmac->hash.blake2b,
+                                 (byte*) hmac->opad, BLAKE2B_BLOCKBYTES);
+            if (ret != 0)
+                return ret;
+
+            ret = wc_Blake2bUpdate(&hmac->hash.blake2b,
+                                 (byte*) hmac->innerHash, BLAKE2B_256);
+            if (ret != 0)
+                return ret;
+
+            ret = wc_Blake2bFinal(&hmac->hash.blake2b, hash, BLAKE2B_256);
+            if (ret != 0)
+                return ret;
+        }
+        break;
+        #endif
+
+        default:
+        break;
+    }
+
+    hmac->innerHashKeyed = 0;
+
+    return 0;
+}
+
+
+#ifdef HAVE_CAVIUM
+
+/* Initiliaze Hmac for use with Nitrox device */
+int wc_HmacInitCavium(Hmac* hmac, int devId)
+{
+    if (hmac == NULL)
+        return -1;
+
+    if (CspAllocContext(CONTEXT_SSL, &hmac->contextHandle, devId) != 0)
+        return -1;
+
+    hmac->keyLen  = 0;
+    hmac->dataLen = 0;
+    hmac->type    = 0;
+    hmac->devId   = devId;
+    hmac->magic   = WOLFSSL_HMAC_CAVIUM_MAGIC;
+    hmac->data    = NULL;        /* buffered input data */
+   
+    hmac->innerHashKeyed = 0;
+
+    return 0;
+}
+
+
+/* Free Hmac from use with Nitrox device */
+void wc_HmacFreeCavium(Hmac* hmac)
+{
+    if (hmac == NULL)
+        return;
+
+    CspFreeContext(CONTEXT_SSL, hmac->contextHandle, hmac->devId);
+    hmac->magic = 0;
+    XFREE(hmac->data, NULL, DYNAMIC_TYPE_CAVIUM_TMP);
+    hmac->data = NULL;
+}
+
+
+static void HmacCaviumFinal(Hmac* hmac, byte* hash)
+{
+    word32 requestId;
+
+    if (CspHmac(CAVIUM_BLOCKING, hmac->type, NULL, hmac->keyLen,
+                (byte*)hmac->ipad, hmac->dataLen, hmac->data, hash, &requestId,
+                hmac->devId) != 0) {
+        WOLFSSL_MSG("Cavium Hmac failed");
+    } 
+    hmac->innerHashKeyed = 0;  /* tell update to start over if used again */
+}
+
+
+static void HmacCaviumUpdate(Hmac* hmac, const byte* msg, word32 length)
+{
+    word16 add = (word16)length;
+    word32 total;
+    byte*  tmp;
+
+    if (length > WOLFSSL_MAX_16BIT) {
+        WOLFSSL_MSG("Too big msg for cavium hmac");
+        return;
+    }
+
+    if (hmac->innerHashKeyed == 0) {  /* starting new */
+        hmac->dataLen        = 0;
+        hmac->innerHashKeyed = 1;
+    }
+
+    total = add + hmac->dataLen;
+    if (total > WOLFSSL_MAX_16BIT) {
+        WOLFSSL_MSG("Too big msg for cavium hmac");
+        return;
+    }
+
+    tmp = XMALLOC(hmac->dataLen + add, NULL,DYNAMIC_TYPE_CAVIUM_TMP);
+    if (tmp == NULL) {
+        WOLFSSL_MSG("Out of memory for cavium update");
+        return;
+    }
+    if (hmac->dataLen)
+        XMEMCPY(tmp, hmac->data,  hmac->dataLen);
+    XMEMCPY(tmp + hmac->dataLen, msg, add);
+        
+    hmac->dataLen += add;
+    XFREE(hmac->data, NULL, DYNAMIC_TYPE_CAVIUM_TMP);
+    hmac->data = tmp;
+}
+
+
+static void HmacCaviumSetKey(Hmac* hmac, int type, const byte* key,
+                             word32 length)
+{
+    hmac->macType = (byte)type;
+    if (type == MD5)
+        hmac->type = MD5_TYPE;
+    else if (type == SHA)
+        hmac->type = SHA1_TYPE;
+    else if (type == SHA256)
+        hmac->type = SHA256_TYPE;
+    else  {
+        WOLFSSL_MSG("unsupported cavium hmac type");
+    }
+
+    hmac->innerHashKeyed = 0;  /* should we key Startup flag */
+
+    hmac->keyLen = (word16)length;
+    /* store key in ipad */
+    XMEMCPY(hmac->ipad, key, length);
+}
+
+#endif /* HAVE_CAVIUM */
+
+int wolfSSL_GetHmacMaxSize(void)
+{
+    return MAX_DIGEST_SIZE;
+}
+
+#ifdef HAVE_HKDF
+
+#ifndef WOLFSSL_HAVE_MIN
+#define WOLFSSL_HAVE_MIN
+
+    static INLINE word32 min(word32 a, word32 b)
+    {
+        return a > b ? b : a;
+    }
+
+#endif /* WOLFSSL_HAVE_MIN */
+
+
+static INLINE int GetHashSizeByType(int type)
+{
+    if (!(type == MD5 || type == SHA    || type == SHA256 || type == SHA384
+                      || type == SHA512 || type == BLAKE2B_ID))
+        return BAD_FUNC_ARG;
+
+    switch (type) {
+        #ifndef NO_MD5
+        case MD5:
+            return MD5_DIGEST_SIZE;
+        break;
+        #endif
+
+        #ifndef NO_SHA
+        case SHA:
+            return SHA_DIGEST_SIZE;
+        break;
+        #endif
+        
+        #ifndef NO_SHA256
+        case SHA256:
+            return SHA256_DIGEST_SIZE;
+        break;
+        #endif
+        
+        #ifdef WOLFSSL_SHA384
+        case SHA384:
+            return SHA384_DIGEST_SIZE;
+        break;
+        #endif
+        
+        #ifdef WOLFSSL_SHA512
+        case SHA512:
+            return SHA512_DIGEST_SIZE;
+        break;
+        #endif
+        
+        #ifdef HAVE_BLAKE2 
+        case BLAKE2B_ID:
+            return BLAKE2B_OUTBYTES;
+        break;
+        #endif
+        
+        default:
+            return BAD_FUNC_ARG;
+        break;
+    }
+}
+
+
+/* HMAC-KDF with hash type, optional salt and info, return 0 on success */
+int wc_HKDF(int type, const byte* inKey, word32 inKeySz,
+                   const byte* salt,  word32 saltSz,
+                   const byte* info,  word32 infoSz,
+                   byte* out,         word32 outSz)
+{
+    Hmac   myHmac;
+#ifdef WOLFSSL_SMALL_STACK
+    byte* tmp;
+    byte* prk;
+#else
+    byte   tmp[MAX_DIGEST_SIZE]; /* localSalt helper and T */
+    byte   prk[MAX_DIGEST_SIZE];
+#endif
+    const  byte* localSalt;  /* either points to user input or tmp */
+    int    hashSz = GetHashSizeByType(type);
+    word32 outIdx = 0;
+    byte   n = 0x1;
+    int    ret;
+
+    if (hashSz < 0)
+        return BAD_FUNC_ARG;
+
+#ifdef WOLFSSL_SMALL_STACK
+    tmp = (byte*)XMALLOC(MAX_DIGEST_SIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (tmp == NULL)
+        return MEMORY_E;
+
+    prk = (byte*)XMALLOC(MAX_DIGEST_SIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (prk == NULL) {
+        XFREE(tmp, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        return MEMORY_E;
+    }
+#endif
+
+    localSalt = salt;
+    if (localSalt == NULL) {
+        XMEMSET(tmp, 0, hashSz);
+        localSalt = tmp;
+        saltSz    = hashSz;
+    }
+    
+    do {
+    ret = wc_HmacSetKey(&myHmac, type, localSalt, saltSz);
+    if (ret != 0)
+        break;
+    ret = wc_HmacUpdate(&myHmac, inKey, inKeySz);
+    if (ret != 0)
+        break;
+    ret = wc_HmacFinal(&myHmac,  prk);
+    } while (0);
+
+    if (ret == 0) {
+        while (outIdx < outSz) {
+            int    tmpSz = (n == 1) ? 0 : hashSz;
+            word32 left = outSz - outIdx;
+
+            ret = wc_HmacSetKey(&myHmac, type, prk, hashSz);
+            if (ret != 0)
+                break;
+            ret = wc_HmacUpdate(&myHmac, tmp, tmpSz);
+            if (ret != 0)
+                break;
+            ret = wc_HmacUpdate(&myHmac, info, infoSz);
+            if (ret != 0)
+                break;
+            ret = wc_HmacUpdate(&myHmac, &n, 1);
+            if (ret != 0)
+                break;
+            ret = wc_HmacFinal(&myHmac, tmp);
+            if (ret != 0)
+                break;
+
+            left = min(left, (word32)hashSz);
+            XMEMCPY(out+outIdx, tmp, left);
+
+            outIdx += hashSz;
+            n++;
+        }
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(tmp, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(prk, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+#endif /* HAVE_HKDF */
+
+#endif /* HAVE_FIPS */
+#endif /* NO_HMAC */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/include.am
new file mode 100644
index 0000000..2999215
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/include.am
@@ -0,0 +1,48 @@
+# vim:ft=automake
+# All paths should be given relative to the root
+
+EXTRA_DIST += wolfcrypt/src/misc.c
+EXTRA_DIST += wolfcrypt/src/asm.c
+EXTRA_DIST += wolfcrypt/src/aes_asm.asm
+
+EXTRA_DIST += \
+              wolfcrypt/src/ecc_fp.c \
+              wolfcrypt/src/fp_mont_small.i \
+              wolfcrypt/src/fp_mul_comba_12.i \
+              wolfcrypt/src/fp_mul_comba_17.i \
+              wolfcrypt/src/fp_mul_comba_20.i \
+              wolfcrypt/src/fp_mul_comba_24.i \
+              wolfcrypt/src/fp_mul_comba_28.i \
+              wolfcrypt/src/fp_mul_comba_32.i \
+              wolfcrypt/src/fp_mul_comba_3.i \
+              wolfcrypt/src/fp_mul_comba_48.i \
+              wolfcrypt/src/fp_mul_comba_4.i \
+              wolfcrypt/src/fp_mul_comba_64.i \
+              wolfcrypt/src/fp_mul_comba_6.i \
+              wolfcrypt/src/fp_mul_comba_7.i \
+              wolfcrypt/src/fp_mul_comba_8.i \
+              wolfcrypt/src/fp_mul_comba_9.i \
+              wolfcrypt/src/fp_mul_comba_small_set.i \
+              wolfcrypt/src/fp_sqr_comba_12.i \
+              wolfcrypt/src/fp_sqr_comba_17.i \
+              wolfcrypt/src/fp_sqr_comba_20.i \
+              wolfcrypt/src/fp_sqr_comba_24.i \
+              wolfcrypt/src/fp_sqr_comba_28.i \
+              wolfcrypt/src/fp_sqr_comba_32.i \
+              wolfcrypt/src/fp_sqr_comba_3.i \
+              wolfcrypt/src/fp_sqr_comba_48.i \
+              wolfcrypt/src/fp_sqr_comba_4.i \
+              wolfcrypt/src/fp_sqr_comba_64.i \
+              wolfcrypt/src/fp_sqr_comba_6.i \
+              wolfcrypt/src/fp_sqr_comba_7.i \
+              wolfcrypt/src/fp_sqr_comba_8.i \
+              wolfcrypt/src/fp_sqr_comba_9.i \
+              wolfcrypt/src/fp_sqr_comba_small_set.i
+
+EXTRA_DIST += wolfcrypt/src/port/ti/ti-aes.c \
+              wolfcrypt/src/port/ti/ti-des3.c \
+              wolfcrypt/src/port/ti/ti-hash.c \
+              wolfcrypt/src/port/ti/ti-ccm.c \
+              wolfcrypt/src/port/pic32/pic32mz-hash.c
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/integer.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/integer.c
new file mode 100644
index 0000000..b3ce420
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/integer.c
@@ -0,0 +1,4522 @@
+/* integer.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+/*
+ * Based on public domain LibTomMath 0.38 by Tom St Denis, tomstdenis@iahu.ca,
+ * http://math.libtomcrypt.com
+ */
+
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+/* in case user set USE_FAST_MATH there */
+#include 
+
+#ifndef NO_BIG_INT
+
+#ifndef USE_FAST_MATH
+
+#include 
+
+#ifndef NO_WOLFSSL_SMALL_STACK
+    #ifndef WOLFSSL_SMALL_STACK
+        #define WOLFSSL_SMALL_STACK
+    #endif
+#endif
+
+static void bn_reverse (unsigned char *s, int len);
+
+/* math settings check */
+word32 CheckRunTimeSettings(void)
+{
+    return CTC_SETTINGS;
+}
+
+
+/* handle up to 6 inits */
+int mp_init_multi(mp_int* a, mp_int* b, mp_int* c, mp_int* d, mp_int* e,
+                  mp_int* f)
+{
+    int res = MP_OKAY;
+
+    if (a && ((res = mp_init(a)) != MP_OKAY))
+        return res;
+
+    if (b && ((res = mp_init(b)) != MP_OKAY)) {
+        mp_clear(a);
+        return res;
+    }
+
+    if (c && ((res = mp_init(c)) != MP_OKAY)) {
+        mp_clear(a); mp_clear(b);
+        return res;
+    }
+
+    if (d && ((res = mp_init(d)) != MP_OKAY)) {
+        mp_clear(a); mp_clear(b); mp_clear(c);
+        return res;
+    }
+
+    if (e && ((res = mp_init(e)) != MP_OKAY)) {
+        mp_clear(a); mp_clear(b); mp_clear(c); mp_clear(d);
+        return res;
+    }
+
+    if (f && ((res = mp_init(f)) != MP_OKAY)) {
+        mp_clear(a); mp_clear(b); mp_clear(c); mp_clear(d); mp_clear(e);
+        return res;
+    }
+
+    return res;
+}
+
+
+/* init a new mp_int */
+int mp_init (mp_int * a)
+{
+  int i;
+
+  /* allocate memory required and clear it */
+  a->dp = OPT_CAST(mp_digit) XMALLOC (sizeof (mp_digit) * MP_PREC, 0,
+                                      DYNAMIC_TYPE_BIGINT);
+  if (a->dp == NULL) {
+    return MP_MEM;
+  }
+
+  /* set the digits to zero */
+  for (i = 0; i < MP_PREC; i++) {
+      a->dp[i] = 0;
+  }
+
+  /* set the used to zero, allocated digits to the default precision
+   * and sign to positive */
+  a->used  = 0;
+  a->alloc = MP_PREC;
+  a->sign  = MP_ZPOS;
+
+  return MP_OKAY;
+}
+
+
+/* clear one (frees)  */
+void
+mp_clear (mp_int * a)
+{
+  int i;
+
+  if (a == NULL)
+      return;
+
+  /* only do anything if a hasn't been freed previously */
+  if (a->dp != NULL) {
+    /* first zero the digits */
+    for (i = 0; i < a->used; i++) {
+        a->dp[i] = 0;
+    }
+
+    /* free ram */
+    XFREE(a->dp, 0, DYNAMIC_TYPE_BIGINT);
+
+    /* reset members to make debugging easier */
+    a->dp    = NULL;
+    a->alloc = a->used = 0;
+    a->sign  = MP_ZPOS;
+  }
+}
+
+
+/* get the size for an unsigned equivalent */
+int mp_unsigned_bin_size (mp_int * a)
+{
+  int     size = mp_count_bits (a);
+  return (size / 8 + ((size & 7) != 0 ? 1 : 0));
+}
+
+
+/* returns the number of bits in an int */
+int
+mp_count_bits (mp_int * a)
+{
+  int     r;
+  mp_digit q;
+
+  /* shortcut */
+  if (a->used == 0) {
+    return 0;
+  }
+
+  /* get number of digits and add that */
+  r = (a->used - 1) * DIGIT_BIT;
+
+  /* take the last digit and count the bits in it */
+  q = a->dp[a->used - 1];
+  while (q > ((mp_digit) 0)) {
+    ++r;
+    q >>= ((mp_digit) 1);
+  }
+  return r;
+}
+
+
+int mp_leading_bit (mp_int * a)
+{
+    int bit = 0;
+    mp_int t;
+
+    if (mp_init_copy(&t, a) != MP_OKAY)
+        return 0;
+
+    while (mp_iszero(&t) == 0) {
+#ifndef MP_8BIT
+        bit = (t.dp[0] & 0x80) != 0;
+#else
+        bit = (t.dp[0] | ((t.dp[1] & 0x01) << 7)) & 0x80 != 0;
+#endif
+        if (mp_div_2d (&t, 8, &t, NULL) != MP_OKAY)
+            break;
+    }
+    mp_clear(&t);
+    return bit;
+}
+
+
+/* store in unsigned [big endian] format */
+int mp_to_unsigned_bin (mp_int * a, unsigned char *b)
+{
+  int     x, res;
+  mp_int  t;
+
+  if ((res = mp_init_copy (&t, a)) != MP_OKAY) {
+    return res;
+  }
+
+  x = 0;
+  while (mp_iszero (&t) == 0) {
+#ifndef MP_8BIT
+      b[x++] = (unsigned char) (t.dp[0] & 255);
+#else
+      b[x++] = (unsigned char) (t.dp[0] | ((t.dp[1] & 0x01) << 7));
+#endif
+    if ((res = mp_div_2d (&t, 8, &t, NULL)) != MP_OKAY) {
+      mp_clear (&t);
+      return res;
+    }
+  }
+  bn_reverse (b, x);
+  mp_clear (&t);
+  return MP_OKAY;
+}
+
+
+/* creates "a" then copies b into it */
+int mp_init_copy (mp_int * a, mp_int * b)
+{
+  int     res;
+
+  if ((res = mp_init (a)) != MP_OKAY) {
+    return res;
+  }
+  return mp_copy (b, a);
+}
+
+
+/* copy, b = a */
+int
+mp_copy (mp_int * a, mp_int * b)
+{
+  int     res, n;
+
+  /* if dst == src do nothing */
+  if (a == b) {
+    return MP_OKAY;
+  }
+
+  /* grow dest */
+  if (b->alloc < a->used) {
+     if ((res = mp_grow (b, a->used)) != MP_OKAY) {
+        return res;
+     }
+  }
+
+  /* zero b and copy the parameters over */
+  {
+    register mp_digit *tmpa, *tmpb;
+
+    /* pointer aliases */
+
+    /* source */
+    tmpa = a->dp;
+
+    /* destination */
+    tmpb = b->dp;
+
+    /* copy all the digits */
+    for (n = 0; n < a->used; n++) {
+      *tmpb++ = *tmpa++;
+    }
+
+    /* clear high digits */
+    for (; n < b->used; n++) {
+      *tmpb++ = 0;
+    }
+  }
+
+  /* copy used count and sign */
+  b->used = a->used;
+  b->sign = a->sign;
+  return MP_OKAY;
+}
+
+
+/* grow as required */
+int mp_grow (mp_int * a, int size)
+{
+  int     i;
+  mp_digit *tmp;
+
+  /* if the alloc size is smaller alloc more ram */
+  if (a->alloc < size) {
+    /* ensure there are always at least MP_PREC digits extra on top */
+    size += (MP_PREC * 2) - (size % MP_PREC);
+
+    /* reallocate the array a->dp
+     *
+     * We store the return in a temporary variable
+     * in case the operation failed we don't want
+     * to overwrite the dp member of a.
+     */
+    tmp = OPT_CAST(mp_digit) XREALLOC (a->dp, sizeof (mp_digit) * size, 0,
+                                       DYNAMIC_TYPE_BIGINT);
+    if (tmp == NULL) {
+      /* reallocation failed but "a" is still valid [can be freed] */
+      return MP_MEM;
+    }
+
+    /* reallocation succeeded so set a->dp */
+    a->dp = tmp;
+
+    /* zero excess digits */
+    i        = a->alloc;
+    a->alloc = size;
+    for (; i < a->alloc; i++) {
+      a->dp[i] = 0;
+    }
+  }
+  return MP_OKAY;
+}
+
+
+/* reverse an array, used for radix code */
+void
+bn_reverse (unsigned char *s, int len)
+{
+  int     ix, iy;
+  unsigned char t;
+
+  ix = 0;
+  iy = len - 1;
+  while (ix < iy) {
+    t     = s[ix];
+    s[ix] = s[iy];
+    s[iy] = t;
+    ++ix;
+    --iy;
+  }
+}
+
+
+/* shift right by a certain bit count (store quotient in c, optional
+   remainder in d) */
+int mp_div_2d (mp_int * a, int b, mp_int * c, mp_int * d)
+{
+  int     D, res;
+  mp_int  t;
+
+
+  /* if the shift count is <= 0 then we do no work */
+  if (b <= 0) {
+    res = mp_copy (a, c);
+    if (d != NULL) {
+      mp_zero (d);
+    }
+    return res;
+  }
+
+  if ((res = mp_init (&t)) != MP_OKAY) {
+    return res;
+  }
+
+  /* get the remainder */
+  if (d != NULL) {
+    if ((res = mp_mod_2d (a, b, &t)) != MP_OKAY) {
+      mp_clear (&t);
+      return res;
+    }
+  }
+
+  /* copy */
+  if ((res = mp_copy (a, c)) != MP_OKAY) {
+    mp_clear (&t);
+    return res;
+  }
+
+  /* shift by as many digits in the bit count */
+  if (b >= (int)DIGIT_BIT) {
+    mp_rshd (c, b / DIGIT_BIT);
+  }
+
+  /* shift any bit count < DIGIT_BIT */
+  D = (b % DIGIT_BIT);
+  if (D != 0) {
+    mp_rshb(c, D);
+  }
+  mp_clamp (c);
+  if (d != NULL) {
+    mp_exch (&t, d);
+  }
+  mp_clear (&t);
+  return MP_OKAY;
+}
+
+
+/* set to zero */
+void mp_zero (mp_int * a)
+{
+  int       n;
+  mp_digit *tmp;
+
+  a->sign = MP_ZPOS;
+  a->used = 0;
+
+  tmp = a->dp;
+  for (n = 0; n < a->alloc; n++) {
+     *tmp++ = 0;
+  }
+}
+
+
+/* trim unused digits
+ *
+ * This is used to ensure that leading zero digits are
+ * trimed and the leading "used" digit will be non-zero
+ * Typically very fast.  Also fixes the sign if there
+ * are no more leading digits
+ */
+void
+mp_clamp (mp_int * a)
+{
+  /* decrease used while the most significant digit is
+   * zero.
+   */
+  while (a->used > 0 && a->dp[a->used - 1] == 0) {
+    --(a->used);
+  }
+
+  /* reset the sign flag if used == 0 */
+  if (a->used == 0) {
+    a->sign = MP_ZPOS;
+  }
+}
+
+
+/* swap the elements of two integers, for cases where you can't simply swap the
+ * mp_int pointers around
+ */
+void
+mp_exch (mp_int * a, mp_int * b)
+{
+  mp_int  t;
+
+  t  = *a;
+  *a = *b;
+  *b = t;
+}
+
+
+/* shift right a certain number of bits */
+void mp_rshb (mp_int *c, int x)
+{
+    register mp_digit *tmpc, mask, shift;
+    mp_digit r, rr;
+    mp_digit D = x;
+
+    /* mask */
+    mask = (((mp_digit)1) << D) - 1;
+
+    /* shift for lsb */
+    shift = DIGIT_BIT - D;
+
+    /* alias */
+    tmpc = c->dp + (c->used - 1);
+
+    /* carry */
+    r = 0;
+    for (x = c->used - 1; x >= 0; x--) {
+      /* get the lower  bits of this word in a temp */
+      rr = *tmpc & mask;
+
+      /* shift the current word and mix in the carry bits from previous word */
+      *tmpc = (*tmpc >> D) | (r << shift);
+      --tmpc;
+
+      /* set the carry to the carry bits of the current word found above */
+      r = rr;
+    }
+}
+
+
+/* shift right a certain amount of digits */
+void mp_rshd (mp_int * a, int b)
+{
+  int     x;
+
+  /* if b <= 0 then ignore it */
+  if (b <= 0) {
+    return;
+  }
+
+  /* if b > used then simply zero it and return */
+  if (a->used <= b) {
+    mp_zero (a);
+    return;
+  }
+
+  {
+    register mp_digit *bottom, *top;
+
+    /* shift the digits down */
+
+    /* bottom */
+    bottom = a->dp;
+
+    /* top [offset into digits] */
+    top = a->dp + b;
+
+    /* this is implemented as a sliding window where
+     * the window is b-digits long and digits from
+     * the top of the window are copied to the bottom
+     *
+     * e.g.
+
+     b-2 | b-1 | b0 | b1 | b2 | ... | bb |   ---->
+                 /\                   |      ---->
+                  \-------------------/      ---->
+     */
+    for (x = 0; x < (a->used - b); x++) {
+      *bottom++ = *top++;
+    }
+
+    /* zero the top digits */
+    for (; x < a->used; x++) {
+      *bottom++ = 0;
+    }
+  }
+
+  /* remove excess digits */
+  a->used -= b;
+}
+
+
+/* calc a value mod 2**b */
+int
+mp_mod_2d (mp_int * a, int b, mp_int * c)
+{
+  int     x, res;
+
+  /* if b is <= 0 then zero the int */
+  if (b <= 0) {
+    mp_zero (c);
+    return MP_OKAY;
+  }
+
+  /* if the modulus is larger than the value than return */
+  if (b >= (int) (a->used * DIGIT_BIT)) {
+    res = mp_copy (a, c);
+    return res;
+  }
+
+  /* copy */
+  if ((res = mp_copy (a, c)) != MP_OKAY) {
+    return res;
+  }
+
+  /* zero digits above the last digit of the modulus */
+  for (x = (b / DIGIT_BIT) + ((b % DIGIT_BIT) == 0 ? 0 : 1); x < c->used; x++) {
+    c->dp[x] = 0;
+  }
+  /* clear the digit that is not completely outside/inside the modulus */
+  c->dp[b / DIGIT_BIT] &= (mp_digit) ((((mp_digit) 1) <<
+              (((mp_digit) b) % DIGIT_BIT)) - ((mp_digit) 1));
+  mp_clamp (c);
+  return MP_OKAY;
+}
+
+
+/* reads a unsigned char array, assumes the msb is stored first [big endian] */
+int mp_read_unsigned_bin (mp_int * a, const unsigned char *b, int c)
+{
+  int     res;
+
+  /* make sure there are at least two digits */
+  if (a->alloc < 2) {
+     if ((res = mp_grow(a, 2)) != MP_OKAY) {
+        return res;
+     }
+  }
+
+  /* zero the int */
+  mp_zero (a);
+
+  /* read the bytes in */
+  while (c-- > 0) {
+    if ((res = mp_mul_2d (a, 8, a)) != MP_OKAY) {
+      return res;
+    }
+
+#ifndef MP_8BIT
+      a->dp[0] |= *b++;
+      a->used += 1;
+#else
+      a->dp[0] = (*b & MP_MASK);
+      a->dp[1] |= ((*b++ >> 7U) & 1);
+      a->used += 2;
+#endif
+  }
+  mp_clamp (a);
+  return MP_OKAY;
+}
+
+
+/* shift left by a certain bit count */
+int mp_mul_2d (mp_int * a, int b, mp_int * c)
+{
+  mp_digit d;
+  int      res;
+
+  /* copy */
+  if (a != c) {
+     if ((res = mp_copy (a, c)) != MP_OKAY) {
+       return res;
+     }
+  }
+
+  if (c->alloc < (int)(c->used + b/DIGIT_BIT + 1)) {
+     if ((res = mp_grow (c, c->used + b / DIGIT_BIT + 1)) != MP_OKAY) {
+       return res;
+     }
+  }
+
+  /* shift by as many digits in the bit count */
+  if (b >= (int)DIGIT_BIT) {
+    if ((res = mp_lshd (c, b / DIGIT_BIT)) != MP_OKAY) {
+      return res;
+    }
+  }
+
+  /* shift any bit count < DIGIT_BIT */
+  d = (mp_digit) (b % DIGIT_BIT);
+  if (d != 0) {
+    register mp_digit *tmpc, shift, mask, r, rr;
+    register int x;
+
+    /* bitmask for carries */
+    mask = (((mp_digit)1) << d) - 1;
+
+    /* shift for msbs */
+    shift = DIGIT_BIT - d;
+
+    /* alias */
+    tmpc = c->dp;
+
+    /* carry */
+    r    = 0;
+    for (x = 0; x < c->used; x++) {
+      /* get the higher bits of the current word */
+      rr = (*tmpc >> shift) & mask;
+
+      /* shift the current word and OR in the carry */
+      *tmpc = ((*tmpc << d) | r) & MP_MASK;
+      ++tmpc;
+
+      /* set the carry to the carry bits of the current word */
+      r = rr;
+    }
+
+    /* set final carry */
+    if (r != 0) {
+       c->dp[(c->used)++] = r;
+    }
+  }
+  mp_clamp (c);
+  return MP_OKAY;
+}
+
+
+/* shift left a certain amount of digits */
+int mp_lshd (mp_int * a, int b)
+{
+  int     x, res;
+
+  /* if its less than zero return */
+  if (b <= 0) {
+    return MP_OKAY;
+  }
+
+  /* grow to fit the new digits */
+  if (a->alloc < a->used + b) {
+     if ((res = mp_grow (a, a->used + b)) != MP_OKAY) {
+       return res;
+     }
+  }
+
+  {
+    register mp_digit *top, *bottom;
+
+    /* increment the used by the shift amount then copy upwards */
+    a->used += b;
+
+    /* top */
+    top = a->dp + a->used - 1;
+
+    /* base */
+    bottom = a->dp + a->used - 1 - b;
+
+    /* much like mp_rshd this is implemented using a sliding window
+     * except the window goes the otherway around.  Copying from
+     * the bottom to the top.  see bn_mp_rshd.c for more info.
+     */
+    for (x = a->used - 1; x >= b; x--) {
+      *top-- = *bottom--;
+    }
+
+    /* zero the lower digits */
+    top = a->dp;
+    for (x = 0; x < b; x++) {
+      *top++ = 0;
+    }
+  }
+  return MP_OKAY;
+}
+
+
+/* this is a shell function that calls either the normal or Montgomery
+ * exptmod functions.  Originally the call to the montgomery code was
+ * embedded in the normal function but that wasted alot of stack space
+ * for nothing (since 99% of the time the Montgomery code would be called)
+ */
+int mp_exptmod (mp_int * G, mp_int * X, mp_int * P, mp_int * Y)
+{
+  int dr;
+
+  /* modulus P must be positive */
+  if (P->sign == MP_NEG) {
+     return MP_VAL;
+  }
+
+  /* if exponent X is negative we have to recurse */
+  if (X->sign == MP_NEG) {
+#ifdef BN_MP_INVMOD_C
+     mp_int tmpG, tmpX;
+     int err;
+
+     /* first compute 1/G mod P */
+     if ((err = mp_init(&tmpG)) != MP_OKAY) {
+        return err;
+     }
+     if ((err = mp_invmod(G, P, &tmpG)) != MP_OKAY) {
+        mp_clear(&tmpG);
+        return err;
+     }
+
+     /* now get |X| */
+     if ((err = mp_init(&tmpX)) != MP_OKAY) {
+        mp_clear(&tmpG);
+        return err;
+     }
+     if ((err = mp_abs(X, &tmpX)) != MP_OKAY) {
+        mp_clear(&tmpG);
+        mp_clear(&tmpX);
+        return err;
+     }
+
+     /* and now compute (1/G)**|X| instead of G**X [X < 0] */
+     err = mp_exptmod(&tmpG, &tmpX, P, Y);
+     mp_clear(&tmpG);
+     mp_clear(&tmpX);
+     return err;
+#else
+     /* no invmod */
+     return MP_VAL;
+#endif
+  }
+
+/* modified diminished radix reduction */
+#if defined(BN_MP_REDUCE_IS_2K_L_C) && defined(BN_MP_REDUCE_2K_L_C) && \
+  defined(BN_S_MP_EXPTMOD_C)
+  if (mp_reduce_is_2k_l(P) == MP_YES) {
+     return s_mp_exptmod(G, X, P, Y, 1);
+  }
+#endif
+
+#ifdef BN_MP_DR_IS_MODULUS_C
+  /* is it a DR modulus? */
+  dr = mp_dr_is_modulus(P);
+#else
+  /* default to no */
+  dr = 0;
+#endif
+
+#ifdef BN_MP_REDUCE_IS_2K_C
+  /* if not, is it a unrestricted DR modulus? */
+  if (dr == 0) {
+     dr = mp_reduce_is_2k(P) << 1;
+  }
+#endif
+
+  /* if the modulus is odd or dr != 0 use the montgomery method */
+#ifdef BN_MP_EXPTMOD_FAST_C
+  if (mp_isodd (P) == 1 || dr !=  0) {
+    return mp_exptmod_fast (G, X, P, Y, dr);
+  } else {
+#endif
+#ifdef BN_S_MP_EXPTMOD_C
+    /* otherwise use the generic Barrett reduction technique */
+    return s_mp_exptmod (G, X, P, Y, 0);
+#else
+    /* no exptmod for evens */
+    return MP_VAL;
+#endif
+#ifdef BN_MP_EXPTMOD_FAST_C
+  }
+#endif
+}
+
+
+/* b = |a|
+ *
+ * Simple function copies the input and fixes the sign to positive
+ */
+int
+mp_abs (mp_int * a, mp_int * b)
+{
+  int     res;
+
+  /* copy a to b */
+  if (a != b) {
+     if ((res = mp_copy (a, b)) != MP_OKAY) {
+       return res;
+     }
+  }
+
+  /* force the sign of b to positive */
+  b->sign = MP_ZPOS;
+
+  return MP_OKAY;
+}
+
+
+/* hac 14.61, pp608 */
+int mp_invmod (mp_int * a, mp_int * b, mp_int * c)
+{
+  /* b cannot be negative */
+  if (b->sign == MP_NEG || mp_iszero(b) == 1) {
+    return MP_VAL;
+  }
+
+#ifdef BN_FAST_MP_INVMOD_C
+  /* if the modulus is odd we can use a faster routine instead */
+  if (mp_isodd (b) == 1) {
+    return fast_mp_invmod (a, b, c);
+  }
+#endif
+
+#ifdef BN_MP_INVMOD_SLOW_C
+  return mp_invmod_slow(a, b, c);
+#endif
+}
+
+
+/* computes the modular inverse via binary extended euclidean algorithm,
+ * that is c = 1/a mod b
+ *
+ * Based on slow invmod except this is optimized for the case where b is
+ * odd as per HAC Note 14.64 on pp. 610
+ */
+int fast_mp_invmod (mp_int * a, mp_int * b, mp_int * c)
+{
+  mp_int  x, y, u, v, B, D;
+  int     res, neg, loop_check = 0;
+
+  /* 2. [modified] b must be odd   */
+  if (mp_iseven (b) == 1) {
+    return MP_VAL;
+  }
+
+  /* init all our temps */
+  if ((res = mp_init_multi(&x, &y, &u, &v, &B, &D)) != MP_OKAY) {
+     return res;
+  }
+
+  /* x == modulus, y == value to invert */
+  if ((res = mp_copy (b, &x)) != MP_OKAY) {
+    goto LBL_ERR;
+  }
+
+  /* we need y = |a| */
+  if ((res = mp_mod (a, b, &y)) != MP_OKAY) {
+    goto LBL_ERR;
+  }
+
+  /* 3. u=x, v=y, A=1, B=0, C=0,D=1 */
+  if ((res = mp_copy (&x, &u)) != MP_OKAY) {
+    goto LBL_ERR;
+  }
+  if ((res = mp_copy (&y, &v)) != MP_OKAY) {
+    goto LBL_ERR;
+  }
+  mp_set (&D, 1);
+
+top:
+  /* 4.  while u is even do */
+  while (mp_iseven (&u) == 1) {
+    /* 4.1 u = u/2 */
+    if ((res = mp_div_2 (&u, &u)) != MP_OKAY) {
+      goto LBL_ERR;
+    }
+    /* 4.2 if B is odd then */
+    if (mp_isodd (&B) == 1) {
+      if ((res = mp_sub (&B, &x, &B)) != MP_OKAY) {
+        goto LBL_ERR;
+      }
+    }
+    /* B = B/2 */
+    if ((res = mp_div_2 (&B, &B)) != MP_OKAY) {
+      goto LBL_ERR;
+    }
+  }
+
+  /* 5.  while v is even do */
+  while (mp_iseven (&v) == 1) {
+    /* 5.1 v = v/2 */
+    if ((res = mp_div_2 (&v, &v)) != MP_OKAY) {
+      goto LBL_ERR;
+    }
+    /* 5.2 if D is odd then */
+    if (mp_isodd (&D) == 1) {
+      /* D = (D-x)/2 */
+      if ((res = mp_sub (&D, &x, &D)) != MP_OKAY) {
+        goto LBL_ERR;
+      }
+    }
+    /* D = D/2 */
+    if ((res = mp_div_2 (&D, &D)) != MP_OKAY) {
+      goto LBL_ERR;
+    }
+  }
+
+  /* 6.  if u >= v then */
+  if (mp_cmp (&u, &v) != MP_LT) {
+    /* u = u - v, B = B - D */
+    if ((res = mp_sub (&u, &v, &u)) != MP_OKAY) {
+      goto LBL_ERR;
+    }
+
+    if ((res = mp_sub (&B, &D, &B)) != MP_OKAY) {
+      goto LBL_ERR;
+    }
+  } else {
+    /* v - v - u, D = D - B */
+    if ((res = mp_sub (&v, &u, &v)) != MP_OKAY) {
+      goto LBL_ERR;
+    }
+
+    if ((res = mp_sub (&D, &B, &D)) != MP_OKAY) {
+      goto LBL_ERR;
+    }
+  }
+
+  /* if not zero goto step 4 */
+  if (mp_iszero (&u) == 0) {
+    if (++loop_check > 1024) {
+        res = MP_VAL;
+        goto LBL_ERR;
+    }
+    goto top;
+  }
+
+  /* now a = C, b = D, gcd == g*v */
+
+  /* if v != 1 then there is no inverse */
+  if (mp_cmp_d (&v, 1) != MP_EQ) {
+    res = MP_VAL;
+    goto LBL_ERR;
+  }
+
+  /* b is now the inverse */
+  neg = a->sign;
+  while (D.sign == MP_NEG) {
+    if ((res = mp_add (&D, b, &D)) != MP_OKAY) {
+      goto LBL_ERR;
+    }
+  }
+  mp_exch (&D, c);
+  c->sign = neg;
+  res = MP_OKAY;
+
+LBL_ERR:mp_clear(&x);
+        mp_clear(&y);
+        mp_clear(&u);
+        mp_clear(&v);
+        mp_clear(&B);
+        mp_clear(&D);
+  return res;
+}
+
+
+/* hac 14.61, pp608 */
+int mp_invmod_slow (mp_int * a, mp_int * b, mp_int * c)
+{
+  mp_int  x, y, u, v, A, B, C, D;
+  int     res;
+
+  /* b cannot be negative */
+  if (b->sign == MP_NEG || mp_iszero(b) == 1) {
+    return MP_VAL;
+  }
+
+  /* init temps */
+  if ((res = mp_init_multi(&x, &y, &u, &v,
+                           &A, &B)) != MP_OKAY) {
+     return res;
+  }
+
+  /* init rest of tmps temps */
+  if ((res = mp_init_multi(&C, &D, 0, 0, 0, 0)) != MP_OKAY) {
+     return res;
+  }
+
+  /* x = a, y = b */
+  if ((res = mp_mod(a, b, &x)) != MP_OKAY) {
+      goto LBL_ERR;
+  }
+  if ((res = mp_copy (b, &y)) != MP_OKAY) {
+    goto LBL_ERR;
+  }
+
+  /* 2. [modified] if x,y are both even then return an error! */
+  if (mp_iseven (&x) == 1 && mp_iseven (&y) == 1) {
+    res = MP_VAL;
+    goto LBL_ERR;
+  }
+
+  /* 3. u=x, v=y, A=1, B=0, C=0,D=1 */
+  if ((res = mp_copy (&x, &u)) != MP_OKAY) {
+    goto LBL_ERR;
+  }
+  if ((res = mp_copy (&y, &v)) != MP_OKAY) {
+    goto LBL_ERR;
+  }
+  mp_set (&A, 1);
+  mp_set (&D, 1);
+
+top:
+  /* 4.  while u is even do */
+  while (mp_iseven (&u) == 1) {
+    /* 4.1 u = u/2 */
+    if ((res = mp_div_2 (&u, &u)) != MP_OKAY) {
+      goto LBL_ERR;
+    }
+    /* 4.2 if A or B is odd then */
+    if (mp_isodd (&A) == 1 || mp_isodd (&B) == 1) {
+      /* A = (A+y)/2, B = (B-x)/2 */
+      if ((res = mp_add (&A, &y, &A)) != MP_OKAY) {
+         goto LBL_ERR;
+      }
+      if ((res = mp_sub (&B, &x, &B)) != MP_OKAY) {
+         goto LBL_ERR;
+      }
+    }
+    /* A = A/2, B = B/2 */
+    if ((res = mp_div_2 (&A, &A)) != MP_OKAY) {
+      goto LBL_ERR;
+    }
+    if ((res = mp_div_2 (&B, &B)) != MP_OKAY) {
+      goto LBL_ERR;
+    }
+  }
+
+  /* 5.  while v is even do */
+  while (mp_iseven (&v) == 1) {
+    /* 5.1 v = v/2 */
+    if ((res = mp_div_2 (&v, &v)) != MP_OKAY) {
+      goto LBL_ERR;
+    }
+    /* 5.2 if C or D is odd then */
+    if (mp_isodd (&C) == 1 || mp_isodd (&D) == 1) {
+      /* C = (C+y)/2, D = (D-x)/2 */
+      if ((res = mp_add (&C, &y, &C)) != MP_OKAY) {
+         goto LBL_ERR;
+      }
+      if ((res = mp_sub (&D, &x, &D)) != MP_OKAY) {
+         goto LBL_ERR;
+      }
+    }
+    /* C = C/2, D = D/2 */
+    if ((res = mp_div_2 (&C, &C)) != MP_OKAY) {
+      goto LBL_ERR;
+    }
+    if ((res = mp_div_2 (&D, &D)) != MP_OKAY) {
+      goto LBL_ERR;
+    }
+  }
+
+  /* 6.  if u >= v then */
+  if (mp_cmp (&u, &v) != MP_LT) {
+    /* u = u - v, A = A - C, B = B - D */
+    if ((res = mp_sub (&u, &v, &u)) != MP_OKAY) {
+      goto LBL_ERR;
+    }
+
+    if ((res = mp_sub (&A, &C, &A)) != MP_OKAY) {
+      goto LBL_ERR;
+    }
+
+    if ((res = mp_sub (&B, &D, &B)) != MP_OKAY) {
+      goto LBL_ERR;
+    }
+  } else {
+    /* v - v - u, C = C - A, D = D - B */
+    if ((res = mp_sub (&v, &u, &v)) != MP_OKAY) {
+      goto LBL_ERR;
+    }
+
+    if ((res = mp_sub (&C, &A, &C)) != MP_OKAY) {
+      goto LBL_ERR;
+    }
+
+    if ((res = mp_sub (&D, &B, &D)) != MP_OKAY) {
+      goto LBL_ERR;
+    }
+  }
+
+  /* if not zero goto step 4 */
+  if (mp_iszero (&u) == 0)
+    goto top;
+
+  /* now a = C, b = D, gcd == g*v */
+
+  /* if v != 1 then there is no inverse */
+  if (mp_cmp_d (&v, 1) != MP_EQ) {
+    res = MP_VAL;
+    goto LBL_ERR;
+  }
+
+  /* if its too low */
+  while (mp_cmp_d(&C, 0) == MP_LT) {
+      if ((res = mp_add(&C, b, &C)) != MP_OKAY) {
+         goto LBL_ERR;
+      }
+  }
+
+  /* too big */
+  while (mp_cmp_mag(&C, b) != MP_LT) {
+      if ((res = mp_sub(&C, b, &C)) != MP_OKAY) {
+         goto LBL_ERR;
+      }
+  }
+
+  /* C is now the inverse */
+  mp_exch (&C, c);
+  res = MP_OKAY;
+LBL_ERR:mp_clear(&x);
+        mp_clear(&y);
+        mp_clear(&u);
+        mp_clear(&v);
+        mp_clear(&A);
+        mp_clear(&B);
+        mp_clear(&C);
+        mp_clear(&D);
+  return res;
+}
+
+
+/* compare maginitude of two ints (unsigned) */
+int mp_cmp_mag (mp_int * a, mp_int * b)
+{
+  int     n;
+  mp_digit *tmpa, *tmpb;
+
+  /* compare based on # of non-zero digits */
+  if (a->used > b->used) {
+    return MP_GT;
+  }
+
+  if (a->used < b->used) {
+    return MP_LT;
+  }
+
+  /* alias for a */
+  tmpa = a->dp + (a->used - 1);
+
+  /* alias for b */
+  tmpb = b->dp + (a->used - 1);
+
+  /* compare based on digits  */
+  for (n = 0; n < a->used; ++n, --tmpa, --tmpb) {
+    if (*tmpa > *tmpb) {
+      return MP_GT;
+    }
+
+    if (*tmpa < *tmpb) {
+      return MP_LT;
+    }
+  }
+  return MP_EQ;
+}
+
+
+/* compare two ints (signed)*/
+int
+mp_cmp (mp_int * a, mp_int * b)
+{
+  /* compare based on sign */
+  if (a->sign != b->sign) {
+     if (a->sign == MP_NEG) {
+        return MP_LT;
+     } else {
+        return MP_GT;
+     }
+  }
+
+  /* compare digits */
+  if (a->sign == MP_NEG) {
+     /* if negative compare opposite direction */
+     return mp_cmp_mag(b, a);
+  } else {
+     return mp_cmp_mag(a, b);
+  }
+}
+
+
+/* compare a digit */
+int mp_cmp_d(mp_int * a, mp_digit b)
+{
+  /* compare based on sign */
+  if (a->sign == MP_NEG) {
+    return MP_LT;
+  }
+
+  /* compare based on magnitude */
+  if (a->used > 1) {
+    return MP_GT;
+  }
+
+  /* compare the only digit of a to b */
+  if (a->dp[0] > b) {
+    return MP_GT;
+  } else if (a->dp[0] < b) {
+    return MP_LT;
+  } else {
+    return MP_EQ;
+  }
+}
+
+
+/* set to a digit */
+void mp_set (mp_int * a, mp_digit b)
+{
+  mp_zero (a);
+  a->dp[0] = b & MP_MASK;
+  a->used  = (a->dp[0] != 0) ? 1 : 0;
+}
+
+
+/* c = a mod b, 0 <= c < b */
+int
+mp_mod (mp_int * a, mp_int * b, mp_int * c)
+{
+  mp_int  t;
+  int     res;
+
+  if ((res = mp_init (&t)) != MP_OKAY) {
+    return res;
+  }
+
+  if ((res = mp_div (a, b, NULL, &t)) != MP_OKAY) {
+    mp_clear (&t);
+    return res;
+  }
+
+  if (t.sign != b->sign) {
+    res = mp_add (b, &t, c);
+  } else {
+    res = MP_OKAY;
+    mp_exch (&t, c);
+  }
+
+  mp_clear (&t);
+  return res;
+}
+
+
+/* slower bit-bang division... also smaller */
+int mp_div(mp_int * a, mp_int * b, mp_int * c, mp_int * d)
+{
+   mp_int ta, tb, tq, q;
+   int    res, n, n2;
+
+  /* is divisor zero ? */
+  if (mp_iszero (b) == 1) {
+    return MP_VAL;
+  }
+
+  /* if a < b then q=0, r = a */
+  if (mp_cmp_mag (a, b) == MP_LT) {
+    if (d != NULL) {
+      res = mp_copy (a, d);
+    } else {
+      res = MP_OKAY;
+    }
+    if (c != NULL) {
+      mp_zero (c);
+    }
+    return res;
+  }
+
+  /* init our temps */
+  if ((res = mp_init_multi(&ta, &tb, &tq, &q, 0, 0)) != MP_OKAY) {
+     return res;
+  }
+
+
+  mp_set(&tq, 1);
+  n = mp_count_bits(a) - mp_count_bits(b);
+  if (((res = mp_abs(a, &ta)) != MP_OKAY) ||
+      ((res = mp_abs(b, &tb)) != MP_OKAY) ||
+      ((res = mp_mul_2d(&tb, n, &tb)) != MP_OKAY) ||
+      ((res = mp_mul_2d(&tq, n, &tq)) != MP_OKAY)) {
+      goto LBL_ERR;
+  }
+
+  while (n-- >= 0) {
+     if (mp_cmp(&tb, &ta) != MP_GT) {
+        if (((res = mp_sub(&ta, &tb, &ta)) != MP_OKAY) ||
+            ((res = mp_add(&q, &tq, &q)) != MP_OKAY)) {
+           goto LBL_ERR;
+        }
+     }
+     if (((res = mp_div_2d(&tb, 1, &tb, NULL)) != MP_OKAY) ||
+         ((res = mp_div_2d(&tq, 1, &tq, NULL)) != MP_OKAY)) {
+           goto LBL_ERR;
+     }
+  }
+
+  /* now q == quotient and ta == remainder */
+  n  = a->sign;
+  n2 = (a->sign == b->sign ? MP_ZPOS : MP_NEG);
+  if (c != NULL) {
+     mp_exch(c, &q);
+     c->sign  = (mp_iszero(c) == MP_YES) ? MP_ZPOS : n2;
+  }
+  if (d != NULL) {
+     mp_exch(d, &ta);
+     d->sign = (mp_iszero(d) == MP_YES) ? MP_ZPOS : n;
+  }
+LBL_ERR:
+   mp_clear(&ta);
+   mp_clear(&tb);
+   mp_clear(&tq);
+   mp_clear(&q);
+   return res;
+}
+
+
+/* b = a/2 */
+int mp_div_2(mp_int * a, mp_int * b)
+{
+  int     x, res, oldused;
+
+  /* copy */
+  if (b->alloc < a->used) {
+    if ((res = mp_grow (b, a->used)) != MP_OKAY) {
+      return res;
+    }
+  }
+
+  oldused = b->used;
+  b->used = a->used;
+  {
+    register mp_digit r, rr, *tmpa, *tmpb;
+
+    /* source alias */
+    tmpa = a->dp + b->used - 1;
+
+    /* dest alias */
+    tmpb = b->dp + b->used - 1;
+
+    /* carry */
+    r = 0;
+    for (x = b->used - 1; x >= 0; x--) {
+      /* get the carry for the next iteration */
+      rr = *tmpa & 1;
+
+      /* shift the current digit, add in carry and store */
+      *tmpb-- = (*tmpa-- >> 1) | (r << (DIGIT_BIT - 1));
+
+      /* forward carry to next iteration */
+      r = rr;
+    }
+
+    /* zero excess digits */
+    tmpb = b->dp + b->used;
+    for (x = b->used; x < oldused; x++) {
+      *tmpb++ = 0;
+    }
+  }
+  b->sign = a->sign;
+  mp_clamp (b);
+  return MP_OKAY;
+}
+
+
+/* high level addition (handles signs) */
+int mp_add (mp_int * a, mp_int * b, mp_int * c)
+{
+  int     sa, sb, res;
+
+  /* get sign of both inputs */
+  sa = a->sign;
+  sb = b->sign;
+
+  /* handle two cases, not four */
+  if (sa == sb) {
+    /* both positive or both negative */
+    /* add their magnitudes, copy the sign */
+    c->sign = sa;
+    res = s_mp_add (a, b, c);
+  } else {
+    /* one positive, the other negative */
+    /* subtract the one with the greater magnitude from */
+    /* the one of the lesser magnitude.  The result gets */
+    /* the sign of the one with the greater magnitude. */
+    if (mp_cmp_mag (a, b) == MP_LT) {
+      c->sign = sb;
+      res = s_mp_sub (b, a, c);
+    } else {
+      c->sign = sa;
+      res = s_mp_sub (a, b, c);
+    }
+  }
+  return res;
+}
+
+
+/* low level addition, based on HAC pp.594, Algorithm 14.7 */
+int
+s_mp_add (mp_int * a, mp_int * b, mp_int * c)
+{
+  mp_int *x;
+  int     olduse, res, min, max;
+
+  /* find sizes, we let |a| <= |b| which means we have to sort
+   * them.  "x" will point to the input with the most digits
+   */
+  if (a->used > b->used) {
+    min = b->used;
+    max = a->used;
+    x = a;
+  } else {
+    min = a->used;
+    max = b->used;
+    x = b;
+  }
+
+  /* init result */
+  if (c->alloc < max + 1) {
+    if ((res = mp_grow (c, max + 1)) != MP_OKAY) {
+      return res;
+    }
+  }
+
+  /* get old used digit count and set new one */
+  olduse = c->used;
+  c->used = max + 1;
+
+  {
+    register mp_digit u, *tmpa, *tmpb, *tmpc;
+    register int i;
+
+    /* alias for digit pointers */
+
+    /* first input */
+    tmpa = a->dp;
+
+    /* second input */
+    tmpb = b->dp;
+
+    /* destination */
+    tmpc = c->dp;
+
+    /* zero the carry */
+    u = 0;
+    for (i = 0; i < min; i++) {
+      /* Compute the sum at one digit, T[i] = A[i] + B[i] + U */
+      *tmpc = *tmpa++ + *tmpb++ + u;
+
+      /* U = carry bit of T[i] */
+      u = *tmpc >> ((mp_digit)DIGIT_BIT);
+
+      /* take away carry bit from T[i] */
+      *tmpc++ &= MP_MASK;
+    }
+
+    /* now copy higher words if any, that is in A+B
+     * if A or B has more digits add those in
+     */
+    if (min != max) {
+      for (; i < max; i++) {
+        /* T[i] = X[i] + U */
+        *tmpc = x->dp[i] + u;
+
+        /* U = carry bit of T[i] */
+        u = *tmpc >> ((mp_digit)DIGIT_BIT);
+
+        /* take away carry bit from T[i] */
+        *tmpc++ &= MP_MASK;
+      }
+    }
+
+    /* add carry */
+    *tmpc++ = u;
+
+    /* clear digits above oldused */
+    for (i = c->used; i < olduse; i++) {
+      *tmpc++ = 0;
+    }
+  }
+
+  mp_clamp (c);
+  return MP_OKAY;
+}
+
+
+/* low level subtraction (assumes |a| > |b|), HAC pp.595 Algorithm 14.9 */
+int
+s_mp_sub (mp_int * a, mp_int * b, mp_int * c)
+{
+  int     olduse, res, min, max;
+
+  /* find sizes */
+  min = b->used;
+  max = a->used;
+
+  /* init result */
+  if (c->alloc < max) {
+    if ((res = mp_grow (c, max)) != MP_OKAY) {
+      return res;
+    }
+  }
+  olduse = c->used;
+  c->used = max;
+
+  {
+    register mp_digit u, *tmpa, *tmpb, *tmpc;
+    register int i;
+
+    /* alias for digit pointers */
+    tmpa = a->dp;
+    tmpb = b->dp;
+    tmpc = c->dp;
+
+    /* set carry to zero */
+    u = 0;
+    for (i = 0; i < min; i++) {
+      /* T[i] = A[i] - B[i] - U */
+      *tmpc = *tmpa++ - *tmpb++ - u;
+
+      /* U = carry bit of T[i]
+       * Note this saves performing an AND operation since
+       * if a carry does occur it will propagate all the way to the
+       * MSB.  As a result a single shift is enough to get the carry
+       */
+      u = *tmpc >> ((mp_digit)(CHAR_BIT * sizeof (mp_digit) - 1));
+
+      /* Clear carry from T[i] */
+      *tmpc++ &= MP_MASK;
+    }
+
+    /* now copy higher words if any, e.g. if A has more digits than B  */
+    for (; i < max; i++) {
+      /* T[i] = A[i] - U */
+      *tmpc = *tmpa++ - u;
+
+      /* U = carry bit of T[i] */
+      u = *tmpc >> ((mp_digit)(CHAR_BIT * sizeof (mp_digit) - 1));
+
+      /* Clear carry from T[i] */
+      *tmpc++ &= MP_MASK;
+    }
+
+    /* clear digits above used (since we may not have grown result above) */
+    for (i = c->used; i < olduse; i++) {
+      *tmpc++ = 0;
+    }
+  }
+
+  mp_clamp (c);
+  return MP_OKAY;
+}
+
+
+/* high level subtraction (handles signs) */
+int
+mp_sub (mp_int * a, mp_int * b, mp_int * c)
+{
+  int     sa, sb, res;
+
+  sa = a->sign;
+  sb = b->sign;
+
+  if (sa != sb) {
+    /* subtract a negative from a positive, OR */
+    /* subtract a positive from a negative. */
+    /* In either case, ADD their magnitudes, */
+    /* and use the sign of the first number. */
+    c->sign = sa;
+    res = s_mp_add (a, b, c);
+  } else {
+    /* subtract a positive from a positive, OR */
+    /* subtract a negative from a negative. */
+    /* First, take the difference between their */
+    /* magnitudes, then... */
+    if (mp_cmp_mag (a, b) != MP_LT) {
+      /* Copy the sign from the first */
+      c->sign = sa;
+      /* The first has a larger or equal magnitude */
+      res = s_mp_sub (a, b, c);
+    } else {
+      /* The result has the *opposite* sign from */
+      /* the first number. */
+      c->sign = (sa == MP_ZPOS) ? MP_NEG : MP_ZPOS;
+      /* The second has a larger magnitude */
+      res = s_mp_sub (b, a, c);
+    }
+  }
+  return res;
+}
+
+
+/* determines if reduce_2k_l can be used */
+int mp_reduce_is_2k_l(mp_int *a)
+{
+   int ix, iy;
+
+   if (a->used == 0) {
+      return MP_NO;
+   } else if (a->used == 1) {
+      return MP_YES;
+   } else if (a->used > 1) {
+      /* if more than half of the digits are -1 we're sold */
+      for (iy = ix = 0; ix < a->used; ix++) {
+          if (a->dp[ix] == MP_MASK) {
+              ++iy;
+          }
+      }
+      return (iy >= (a->used/2)) ? MP_YES : MP_NO;
+
+   }
+   return MP_NO;
+}
+
+
+/* determines if mp_reduce_2k can be used */
+int mp_reduce_is_2k(mp_int *a)
+{
+   int ix, iy, iw;
+   mp_digit iz;
+
+   if (a->used == 0) {
+      return MP_NO;
+   } else if (a->used == 1) {
+      return MP_YES;
+   } else if (a->used > 1) {
+      iy = mp_count_bits(a);
+      iz = 1;
+      iw = 1;
+
+      /* Test every bit from the second digit up, must be 1 */
+      for (ix = DIGIT_BIT; ix < iy; ix++) {
+          if ((a->dp[iw] & iz) == 0) {
+             return MP_NO;
+          }
+          iz <<= 1;
+          if (iz > (mp_digit)MP_MASK) {
+             ++iw;
+             iz = 1;
+          }
+      }
+   }
+   return MP_YES;
+}
+
+
+/* determines if a number is a valid DR modulus */
+int mp_dr_is_modulus(mp_int *a)
+{
+   int ix;
+
+   /* must be at least two digits */
+   if (a->used < 2) {
+      return 0;
+   }
+
+   /* must be of the form b**k - a [a <= b] so all
+    * but the first digit must be equal to -1 (mod b).
+    */
+   for (ix = 1; ix < a->used; ix++) {
+       if (a->dp[ix] != MP_MASK) {
+          return 0;
+       }
+   }
+   return 1;
+}
+
+
+/* computes Y == G**X mod P, HAC pp.616, Algorithm 14.85
+ *
+ * Uses a left-to-right k-ary sliding window to compute the modular
+ * exponentiation.
+ * The value of k changes based on the size of the exponent.
+ *
+ * Uses Montgomery or Diminished Radix reduction [whichever appropriate]
+ */
+
+#ifdef MP_LOW_MEM
+   #define TAB_SIZE 32
+#else
+   #define TAB_SIZE 256
+#endif
+
+int mp_exptmod_fast (mp_int * G, mp_int * X, mp_int * P, mp_int * Y,
+                     int redmode)
+{
+  mp_int res;
+  mp_digit buf, mp;
+  int     err, bitbuf, bitcpy, bitcnt, mode, digidx, x, y, winsize;
+#ifdef WOLFSSL_SMALL_STACK
+  mp_int* M = NULL;
+#else
+  mp_int M[TAB_SIZE];
+#endif
+  /* use a pointer to the reduction algorithm.  This allows us to use
+   * one of many reduction algorithms without modding the guts of
+   * the code with if statements everywhere.
+   */
+  int     (*redux)(mp_int*,mp_int*,mp_digit);
+
+#ifdef WOLFSSL_SMALL_STACK
+  M = (mp_int*) XMALLOC(sizeof(mp_int) * TAB_SIZE, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+  if (M == NULL)
+    return MP_MEM;
+#endif
+
+  /* find window size */
+  x = mp_count_bits (X);
+  if (x <= 7) {
+    winsize = 2;
+  } else if (x <= 36) {
+    winsize = 3;
+  } else if (x <= 140) {
+    winsize = 4;
+  } else if (x <= 450) {
+    winsize = 5;
+  } else if (x <= 1303) {
+    winsize = 6;
+  } else if (x <= 3529) {
+    winsize = 7;
+  } else {
+    winsize = 8;
+  }
+
+#ifdef MP_LOW_MEM
+  if (winsize > 5) {
+     winsize = 5;
+  }
+#endif
+
+  /* init M array */
+  /* init first cell */
+  if ((err = mp_init(&M[1])) != MP_OKAY) {
+#ifdef WOLFSSL_SMALL_STACK
+  XFREE(M, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+     return err;
+  }
+
+  /* now init the second half of the array */
+  for (x = 1<<(winsize-1); x < (1 << winsize); x++) {
+    if ((err = mp_init(&M[x])) != MP_OKAY) {
+      for (y = 1<<(winsize-1); y < x; y++) {
+        mp_clear (&M[y]);
+      }
+      mp_clear(&M[1]);
+
+#ifdef WOLFSSL_SMALL_STACK
+      XFREE(M, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+      return err;
+    }
+  }
+
+  /* determine and setup reduction code */
+  if (redmode == 0) {
+#ifdef BN_MP_MONTGOMERY_SETUP_C
+     /* now setup montgomery  */
+     if ((err = mp_montgomery_setup (P, &mp)) != MP_OKAY) {
+        goto LBL_M;
+     }
+#else
+     err = MP_VAL;
+     goto LBL_M;
+#endif
+
+     /* automatically pick the comba one if available (saves quite a few
+        calls/ifs) */
+#ifdef BN_FAST_MP_MONTGOMERY_REDUCE_C
+     if (((P->used * 2 + 1) < MP_WARRAY) &&
+          P->used < (1 << ((CHAR_BIT * sizeof (mp_word)) - (2 * DIGIT_BIT)))) {
+        redux = fast_mp_montgomery_reduce;
+     } else
+#endif
+     {
+#ifdef BN_MP_MONTGOMERY_REDUCE_C
+        /* use slower baseline Montgomery method */
+        redux = mp_montgomery_reduce;
+#else
+        err = MP_VAL;
+        goto LBL_M;
+#endif
+     }
+  } else if (redmode == 1) {
+#if defined(BN_MP_DR_SETUP_C) && defined(BN_MP_DR_REDUCE_C)
+     /* setup DR reduction for moduli of the form B**k - b */
+     mp_dr_setup(P, &mp);
+     redux = mp_dr_reduce;
+#else
+     err = MP_VAL;
+     goto LBL_M;
+#endif
+  } else {
+#if defined(BN_MP_REDUCE_2K_SETUP_C) && defined(BN_MP_REDUCE_2K_C)
+     /* setup DR reduction for moduli of the form 2**k - b */
+     if ((err = mp_reduce_2k_setup(P, &mp)) != MP_OKAY) {
+        goto LBL_M;
+     }
+     redux = mp_reduce_2k;
+#else
+     err = MP_VAL;
+     goto LBL_M;
+#endif
+  }
+
+  /* setup result */
+  if ((err = mp_init (&res)) != MP_OKAY) {
+    goto LBL_M;
+  }
+
+  /* create M table
+   *
+
+   *
+   * The first half of the table is not computed though accept for M[0] and M[1]
+   */
+
+  if (redmode == 0) {
+#ifdef BN_MP_MONTGOMERY_CALC_NORMALIZATION_C
+     /* now we need R mod m */
+     if ((err = mp_montgomery_calc_normalization (&res, P)) != MP_OKAY) {
+       goto LBL_RES;
+     }
+#else
+     err = MP_VAL;
+     goto LBL_RES;
+#endif
+
+     /* now set M[1] to G * R mod m */
+     if ((err = mp_mulmod (G, &res, P, &M[1])) != MP_OKAY) {
+       goto LBL_RES;
+     }
+  } else {
+     mp_set(&res, 1);
+     if ((err = mp_mod(G, P, &M[1])) != MP_OKAY) {
+        goto LBL_RES;
+     }
+  }
+
+  /* compute the value at M[1<<(winsize-1)] by squaring M[1] (winsize-1) times*/
+  if ((err = mp_copy (&M[1], &M[(mp_digit)(1 << (winsize - 1))])) != MP_OKAY) {
+    goto LBL_RES;
+  }
+
+  for (x = 0; x < (winsize - 1); x++) {
+    if ((err = mp_sqr (&M[(mp_digit)(1 << (winsize - 1))], &M[(mp_digit)(1 << (winsize - 1))])) != MP_OKAY) {
+      goto LBL_RES;
+    }
+    if ((err = redux (&M[(mp_digit)(1 << (winsize - 1))], P, mp)) != MP_OKAY) {
+      goto LBL_RES;
+    }
+  }
+
+  /* create upper table */
+  for (x = (1 << (winsize - 1)) + 1; x < (1 << winsize); x++) {
+    if ((err = mp_mul (&M[x - 1], &M[1], &M[x])) != MP_OKAY) {
+      goto LBL_RES;
+    }
+    if ((err = redux (&M[x], P, mp)) != MP_OKAY) {
+      goto LBL_RES;
+    }
+  }
+
+  /* set initial mode and bit cnt */
+  mode   = 0;
+  bitcnt = 1;
+  buf    = 0;
+  digidx = X->used - 1;
+  bitcpy = 0;
+  bitbuf = 0;
+
+  for (;;) {
+    /* grab next digit as required */
+    if (--bitcnt == 0) {
+      /* if digidx == -1 we are out of digits so break */
+      if (digidx == -1) {
+        break;
+      }
+      /* read next digit and reset bitcnt */
+      buf    = X->dp[digidx--];
+      bitcnt = (int)DIGIT_BIT;
+    }
+
+    /* grab the next msb from the exponent */
+    y     = (int)(buf >> (DIGIT_BIT - 1)) & 1;
+    buf <<= (mp_digit)1;
+
+    /* if the bit is zero and mode == 0 then we ignore it
+     * These represent the leading zero bits before the first 1 bit
+     * in the exponent.  Technically this opt is not required but it
+     * does lower the # of trivial squaring/reductions used
+     */
+    if (mode == 0 && y == 0) {
+      continue;
+    }
+
+    /* if the bit is zero and mode == 1 then we square */
+    if (mode == 1 && y == 0) {
+      if ((err = mp_sqr (&res, &res)) != MP_OKAY) {
+        goto LBL_RES;
+      }
+      if ((err = redux (&res, P, mp)) != MP_OKAY) {
+        goto LBL_RES;
+      }
+      continue;
+    }
+
+    /* else we add it to the window */
+    bitbuf |= (y << (winsize - ++bitcpy));
+    mode    = 2;
+
+    if (bitcpy == winsize) {
+      /* ok window is filled so square as required and multiply  */
+      /* square first */
+      for (x = 0; x < winsize; x++) {
+        if ((err = mp_sqr (&res, &res)) != MP_OKAY) {
+          goto LBL_RES;
+        }
+        if ((err = redux (&res, P, mp)) != MP_OKAY) {
+          goto LBL_RES;
+        }
+      }
+
+      /* then multiply */
+      if ((err = mp_mul (&res, &M[bitbuf], &res)) != MP_OKAY) {
+        goto LBL_RES;
+      }
+      if ((err = redux (&res, P, mp)) != MP_OKAY) {
+        goto LBL_RES;
+      }
+
+      /* empty window and reset */
+      bitcpy = 0;
+      bitbuf = 0;
+      mode   = 1;
+    }
+  }
+
+  /* if bits remain then square/multiply */
+  if (mode == 2 && bitcpy > 0) {
+    /* square then multiply if the bit is set */
+    for (x = 0; x < bitcpy; x++) {
+      if ((err = mp_sqr (&res, &res)) != MP_OKAY) {
+        goto LBL_RES;
+      }
+      if ((err = redux (&res, P, mp)) != MP_OKAY) {
+        goto LBL_RES;
+      }
+
+      /* get next bit of the window */
+      bitbuf <<= 1;
+      if ((bitbuf & (1 << winsize)) != 0) {
+        /* then multiply */
+        if ((err = mp_mul (&res, &M[1], &res)) != MP_OKAY) {
+          goto LBL_RES;
+        }
+        if ((err = redux (&res, P, mp)) != MP_OKAY) {
+          goto LBL_RES;
+        }
+      }
+    }
+  }
+
+  if (redmode == 0) {
+     /* fixup result if Montgomery reduction is used
+      * recall that any value in a Montgomery system is
+      * actually multiplied by R mod n.  So we have
+      * to reduce one more time to cancel out the factor
+      * of R.
+      */
+     if ((err = redux(&res, P, mp)) != MP_OKAY) {
+       goto LBL_RES;
+     }
+  }
+
+  /* swap res with Y */
+  mp_exch (&res, Y);
+  err = MP_OKAY;
+LBL_RES:mp_clear (&res);
+LBL_M:
+  mp_clear(&M[1]);
+  for (x = 1<<(winsize-1); x < (1 << winsize); x++) {
+    mp_clear (&M[x]);
+  }
+
+#ifdef WOLFSSL_SMALL_STACK
+  XFREE(M, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+  return err;
+}
+
+
+/* setups the montgomery reduction stuff */
+int
+mp_montgomery_setup (mp_int * n, mp_digit * rho)
+{
+  mp_digit x, b;
+
+/* fast inversion mod 2**k
+ *
+ * Based on the fact that
+ *
+ * XA = 1 (mod 2**n)  =>  (X(2-XA)) A = 1 (mod 2**2n)
+ *                    =>  2*X*A - X*X*A*A = 1
+ *                    =>  2*(1) - (1)     = 1
+ */
+  b = n->dp[0];
+
+  if ((b & 1) == 0) {
+    return MP_VAL;
+  }
+
+  x = (((b + 2) & 4) << 1) + b; /* here x*a==1 mod 2**4 */
+  x *= 2 - b * x;               /* here x*a==1 mod 2**8 */
+#if !defined(MP_8BIT)
+  x *= 2 - b * x;               /* here x*a==1 mod 2**16 */
+#endif
+#if defined(MP_64BIT) || !(defined(MP_8BIT) || defined(MP_16BIT))
+  x *= 2 - b * x;               /* here x*a==1 mod 2**32 */
+#endif
+#ifdef MP_64BIT
+  x *= 2 - b * x;               /* here x*a==1 mod 2**64 */
+#endif
+
+  /* rho = -1/m mod b */
+  /* TAO, switched mp_word casts to mp_digit to shut up compiler */
+  *rho = (((mp_digit)1 << ((mp_digit) DIGIT_BIT)) - x) & MP_MASK;
+
+  return MP_OKAY;
+}
+
+
+/* computes xR**-1 == x (mod N) via Montgomery Reduction
+ *
+ * This is an optimized implementation of montgomery_reduce
+ * which uses the comba method to quickly calculate the columns of the
+ * reduction.
+ *
+ * Based on Algorithm 14.32 on pp.601 of HAC.
+*/
+int fast_mp_montgomery_reduce (mp_int * x, mp_int * n, mp_digit rho)
+{
+  int     ix, res, olduse;
+#ifdef WOLFSSL_SMALL_STACK
+  mp_word* W;    /* uses dynamic memory and slower */
+#else
+  mp_word W[MP_WARRAY];
+#endif
+
+  /* get old used count */
+  olduse = x->used;
+
+  /* grow a as required */
+  if (x->alloc < n->used + 1) {
+    if ((res = mp_grow (x, n->used + 1)) != MP_OKAY) {
+      return res;
+    }
+  }
+
+#ifdef WOLFSSL_SMALL_STACK
+  W = (mp_word*)XMALLOC(sizeof(mp_word) * MP_WARRAY, 0, DYNAMIC_TYPE_BIGINT);
+  if (W == NULL)
+    return MP_MEM;
+#endif
+
+  /* first we have to get the digits of the input into
+   * an array of double precision words W[...]
+   */
+  {
+    register mp_word *_W;
+    register mp_digit *tmpx;
+
+    /* alias for the W[] array */
+    _W   = W;
+
+    /* alias for the digits of  x*/
+    tmpx = x->dp;
+
+    /* copy the digits of a into W[0..a->used-1] */
+    for (ix = 0; ix < x->used; ix++) {
+      *_W++ = *tmpx++;
+    }
+
+    /* zero the high words of W[a->used..m->used*2] */
+    for (; ix < n->used * 2 + 1; ix++) {
+      *_W++ = 0;
+    }
+  }
+
+  /* now we proceed to zero successive digits
+   * from the least significant upwards
+   */
+  for (ix = 0; ix < n->used; ix++) {
+    /* mu = ai * m' mod b
+     *
+     * We avoid a double precision multiplication (which isn't required)
+     * by casting the value down to a mp_digit.  Note this requires
+     * that W[ix-1] have  the carry cleared (see after the inner loop)
+     */
+    register mp_digit mu;
+    mu = (mp_digit) (((W[ix] & MP_MASK) * rho) & MP_MASK);
+
+    /* a = a + mu * m * b**i
+     *
+     * This is computed in place and on the fly.  The multiplication
+     * by b**i is handled by offseting which columns the results
+     * are added to.
+     *
+     * Note the comba method normally doesn't handle carries in the
+     * inner loop In this case we fix the carry from the previous
+     * column since the Montgomery reduction requires digits of the
+     * result (so far) [see above] to work.  This is
+     * handled by fixing up one carry after the inner loop.  The
+     * carry fixups are done in order so after these loops the
+     * first m->used words of W[] have the carries fixed
+     */
+    {
+      register int iy;
+      register mp_digit *tmpn;
+      register mp_word *_W;
+
+      /* alias for the digits of the modulus */
+      tmpn = n->dp;
+
+      /* Alias for the columns set by an offset of ix */
+      _W = W + ix;
+
+      /* inner loop */
+      for (iy = 0; iy < n->used; iy++) {
+          *_W++ += ((mp_word)mu) * ((mp_word)*tmpn++);
+      }
+    }
+
+    /* now fix carry for next digit, W[ix+1] */
+    W[ix + 1] += W[ix] >> ((mp_word) DIGIT_BIT);
+  }
+
+  /* now we have to propagate the carries and
+   * shift the words downward [all those least
+   * significant digits we zeroed].
+   */
+  {
+    register mp_digit *tmpx;
+    register mp_word *_W, *_W1;
+
+    /* nox fix rest of carries */
+
+    /* alias for current word */
+    _W1 = W + ix;
+
+    /* alias for next word, where the carry goes */
+    _W = W + ++ix;
+
+    for (; ix <= n->used * 2 + 1; ix++) {
+      *_W++ += *_W1++ >> ((mp_word) DIGIT_BIT);
+    }
+
+    /* copy out, A = A/b**n
+     *
+     * The result is A/b**n but instead of converting from an
+     * array of mp_word to mp_digit than calling mp_rshd
+     * we just copy them in the right order
+     */
+
+    /* alias for destination word */
+    tmpx = x->dp;
+
+    /* alias for shifted double precision result */
+    _W = W + n->used;
+
+    for (ix = 0; ix < n->used + 1; ix++) {
+      *tmpx++ = (mp_digit)(*_W++ & ((mp_word) MP_MASK));
+    }
+
+    /* zero oldused digits, if the input a was larger than
+     * m->used+1 we'll have to clear the digits
+     */
+    for (; ix < olduse; ix++) {
+      *tmpx++ = 0;
+    }
+  }
+
+  /* set the max used and clamp */
+  x->used = n->used + 1;
+  mp_clamp (x);
+
+#ifdef WOLFSSL_SMALL_STACK
+  XFREE(W, 0, DYNAMIC_TYPE_BIGINT);
+#endif
+
+  /* if A >= m then A = A - m */
+  if (mp_cmp_mag (x, n) != MP_LT) {
+    return s_mp_sub (x, n, x);
+  }
+  return MP_OKAY;
+}
+
+
+/* computes xR**-1 == x (mod N) via Montgomery Reduction */
+int
+mp_montgomery_reduce (mp_int * x, mp_int * n, mp_digit rho)
+{
+  int     ix, res, digs;
+  mp_digit mu;
+
+  /* can the fast reduction [comba] method be used?
+   *
+   * Note that unlike in mul you're safely allowed *less*
+   * than the available columns [255 per default] since carries
+   * are fixed up in the inner loop.
+   */
+  digs = n->used * 2 + 1;
+  if ((digs < MP_WARRAY) &&
+      n->used <
+      (1 << ((CHAR_BIT * sizeof (mp_word)) - (2 * DIGIT_BIT)))) {
+    return fast_mp_montgomery_reduce (x, n, rho);
+  }
+
+  /* grow the input as required */
+  if (x->alloc < digs) {
+    if ((res = mp_grow (x, digs)) != MP_OKAY) {
+      return res;
+    }
+  }
+  x->used = digs;
+
+  for (ix = 0; ix < n->used; ix++) {
+    /* mu = ai * rho mod b
+     *
+     * The value of rho must be precalculated via
+     * montgomery_setup() such that
+     * it equals -1/n0 mod b this allows the
+     * following inner loop to reduce the
+     * input one digit at a time
+     */
+    mu = (mp_digit) (((mp_word)x->dp[ix]) * ((mp_word)rho) & MP_MASK);
+
+    /* a = a + mu * m * b**i */
+    {
+      register int iy;
+      register mp_digit *tmpn, *tmpx, u;
+      register mp_word r;
+
+      /* alias for digits of the modulus */
+      tmpn = n->dp;
+
+      /* alias for the digits of x [the input] */
+      tmpx = x->dp + ix;
+
+      /* set the carry to zero */
+      u = 0;
+
+      /* Multiply and add in place */
+      for (iy = 0; iy < n->used; iy++) {
+        /* compute product and sum */
+        r       = ((mp_word)mu) * ((mp_word)*tmpn++) +
+                  ((mp_word) u) + ((mp_word) * tmpx);
+
+        /* get carry */
+        u       = (mp_digit)(r >> ((mp_word) DIGIT_BIT));
+
+        /* fix digit */
+        *tmpx++ = (mp_digit)(r & ((mp_word) MP_MASK));
+      }
+      /* At this point the ix'th digit of x should be zero */
+
+
+      /* propagate carries upwards as required*/
+      while (u) {
+        *tmpx   += u;
+        u        = *tmpx >> DIGIT_BIT;
+        *tmpx++ &= MP_MASK;
+      }
+    }
+  }
+
+  /* at this point the n.used'th least
+   * significant digits of x are all zero
+   * which means we can shift x to the
+   * right by n.used digits and the
+   * residue is unchanged.
+   */
+
+  /* x = x/b**n.used */
+  mp_clamp(x);
+  mp_rshd (x, n->used);
+
+  /* if x >= n then x = x - n */
+  if (mp_cmp_mag (x, n) != MP_LT) {
+    return s_mp_sub (x, n, x);
+  }
+
+  return MP_OKAY;
+}
+
+
+/* determines the setup value */
+void mp_dr_setup(mp_int *a, mp_digit *d)
+{
+   /* the casts are required if DIGIT_BIT is one less than
+    * the number of bits in a mp_digit [e.g. DIGIT_BIT==31]
+    */
+   *d = (mp_digit)((((mp_word)1) << ((mp_word)DIGIT_BIT)) -
+        ((mp_word)a->dp[0]));
+}
+
+
+/* reduce "x" in place modulo "n" using the Diminished Radix algorithm.
+ *
+ * Based on algorithm from the paper
+ *
+ * "Generating Efficient Primes for Discrete Log Cryptosystems"
+ *                 Chae Hoon Lim, Pil Joong Lee,
+ *          POSTECH Information Research Laboratories
+ *
+ * The modulus must be of a special format [see manual]
+ *
+ * Has been modified to use algorithm 7.10 from the LTM book instead
+ *
+ * Input x must be in the range 0 <= x <= (n-1)**2
+ */
+int
+mp_dr_reduce (mp_int * x, mp_int * n, mp_digit k)
+{
+  int      err, i, m;
+  mp_word  r;
+  mp_digit mu, *tmpx1, *tmpx2;
+
+  /* m = digits in modulus */
+  m = n->used;
+
+  /* ensure that "x" has at least 2m digits */
+  if (x->alloc < m + m) {
+    if ((err = mp_grow (x, m + m)) != MP_OKAY) {
+      return err;
+    }
+  }
+
+/* top of loop, this is where the code resumes if
+ * another reduction pass is required.
+ */
+top:
+  /* aliases for digits */
+  /* alias for lower half of x */
+  tmpx1 = x->dp;
+
+  /* alias for upper half of x, or x/B**m */
+  tmpx2 = x->dp + m;
+
+  /* set carry to zero */
+  mu = 0;
+
+  /* compute (x mod B**m) + k * [x/B**m] inline and inplace */
+  for (i = 0; i < m; i++) {
+      r         = ((mp_word)*tmpx2++) * ((mp_word)k) + *tmpx1 + mu;
+      *tmpx1++  = (mp_digit)(r & MP_MASK);
+      mu        = (mp_digit)(r >> ((mp_word)DIGIT_BIT));
+  }
+
+  /* set final carry */
+  *tmpx1++ = mu;
+
+  /* zero words above m */
+  for (i = m + 1; i < x->used; i++) {
+      *tmpx1++ = 0;
+  }
+
+  /* clamp, sub and return */
+  mp_clamp (x);
+
+  /* if x >= n then subtract and reduce again
+   * Each successive "recursion" makes the input smaller and smaller.
+   */
+  if (mp_cmp_mag (x, n) != MP_LT) {
+    s_mp_sub(x, n, x);
+    goto top;
+  }
+  return MP_OKAY;
+}
+
+
+/* reduces a modulo n where n is of the form 2**p - d */
+int mp_reduce_2k(mp_int *a, mp_int *n, mp_digit d)
+{
+   mp_int q;
+   int    p, res;
+
+   if ((res = mp_init(&q)) != MP_OKAY) {
+      return res;
+   }
+
+   p = mp_count_bits(n);
+top:
+   /* q = a/2**p, a = a mod 2**p */
+   if ((res = mp_div_2d(a, p, &q, a)) != MP_OKAY) {
+      goto ERR;
+   }
+
+   if (d != 1) {
+      /* q = q * d */
+      if ((res = mp_mul_d(&q, d, &q)) != MP_OKAY) {
+         goto ERR;
+      }
+   }
+
+   /* a = a + q */
+   if ((res = s_mp_add(a, &q, a)) != MP_OKAY) {
+      goto ERR;
+   }
+
+   if (mp_cmp_mag(a, n) != MP_LT) {
+      s_mp_sub(a, n, a);
+      goto top;
+   }
+
+ERR:
+   mp_clear(&q);
+   return res;
+}
+
+
+/* determines the setup value */
+int mp_reduce_2k_setup(mp_int *a, mp_digit *d)
+{
+   int res, p;
+   mp_int tmp;
+
+   if ((res = mp_init(&tmp)) != MP_OKAY) {
+      return res;
+   }
+
+   p = mp_count_bits(a);
+   if ((res = mp_2expt(&tmp, p)) != MP_OKAY) {
+      mp_clear(&tmp);
+      return res;
+   }
+
+   if ((res = s_mp_sub(&tmp, a, &tmp)) != MP_OKAY) {
+      mp_clear(&tmp);
+      return res;
+   }
+
+   *d = tmp.dp[0];
+   mp_clear(&tmp);
+   return MP_OKAY;
+}
+
+
+/* computes a = 2**b
+ *
+ * Simple algorithm which zeroes the int, grows it then just sets one bit
+ * as required.
+ */
+int
+mp_2expt (mp_int * a, int b)
+{
+  int     res;
+
+  /* zero a as per default */
+  mp_zero (a);
+
+  /* grow a to accomodate the single bit */
+  if ((res = mp_grow (a, b / DIGIT_BIT + 1)) != MP_OKAY) {
+    return res;
+  }
+
+  /* set the used count of where the bit will go */
+  a->used = b / DIGIT_BIT + 1;
+
+  /* put the single bit in its place */
+  a->dp[b / DIGIT_BIT] = ((mp_digit)1) << (b % DIGIT_BIT);
+
+  return MP_OKAY;
+}
+
+
+/* multiply by a digit */
+int
+mp_mul_d (mp_int * a, mp_digit b, mp_int * c)
+{
+  mp_digit u, *tmpa, *tmpc;
+  mp_word  r;
+  int      ix, res, olduse;
+
+  /* make sure c is big enough to hold a*b */
+  if (c->alloc < a->used + 1) {
+    if ((res = mp_grow (c, a->used + 1)) != MP_OKAY) {
+      return res;
+    }
+  }
+
+  /* get the original destinations used count */
+  olduse = c->used;
+
+  /* set the sign */
+  c->sign = a->sign;
+
+  /* alias for a->dp [source] */
+  tmpa = a->dp;
+
+  /* alias for c->dp [dest] */
+  tmpc = c->dp;
+
+  /* zero carry */
+  u = 0;
+
+  /* compute columns */
+  for (ix = 0; ix < a->used; ix++) {
+    /* compute product and carry sum for this term */
+    r       = ((mp_word) u) + ((mp_word)*tmpa++) * ((mp_word)b);
+
+    /* mask off higher bits to get a single digit */
+    *tmpc++ = (mp_digit) (r & ((mp_word) MP_MASK));
+
+    /* send carry into next iteration */
+    u       = (mp_digit) (r >> ((mp_word) DIGIT_BIT));
+  }
+
+  /* store final carry [if any] and increment ix offset  */
+  *tmpc++ = u;
+  ++ix;
+
+  /* now zero digits above the top */
+  while (ix++ < olduse) {
+     *tmpc++ = 0;
+  }
+
+  /* set used count */
+  c->used = a->used + 1;
+  mp_clamp(c);
+
+  return MP_OKAY;
+}
+
+
+/* d = a * b (mod c) */
+int mp_mulmod (mp_int * a, mp_int * b, mp_int * c, mp_int * d)
+{
+  int     res;
+  mp_int  t;
+
+  if ((res = mp_init (&t)) != MP_OKAY) {
+    return res;
+  }
+
+  if ((res = mp_mul (a, b, &t)) != MP_OKAY) {
+    mp_clear (&t);
+    return res;
+  }
+  res = mp_mod (&t, c, d);
+  mp_clear (&t);
+  return res;
+}
+
+
+/* computes b = a*a */
+int
+mp_sqr (mp_int * a, mp_int * b)
+{
+  int     res;
+
+  {
+#ifdef BN_FAST_S_MP_SQR_C
+    /* can we use the fast comba multiplier? */
+    if ((a->used * 2 + 1) < MP_WARRAY &&
+         a->used <
+         (1 << (sizeof(mp_word) * CHAR_BIT - 2*DIGIT_BIT - 1))) {
+      res = fast_s_mp_sqr (a, b);
+    } else
+#endif
+#ifdef BN_S_MP_SQR_C
+      res = s_mp_sqr (a, b);
+#else
+      res = MP_VAL;
+#endif
+  }
+  b->sign = MP_ZPOS;
+  return res;
+}
+
+
+/* high level multiplication (handles sign) */
+int mp_mul (mp_int * a, mp_int * b, mp_int * c)
+{
+  int     res, neg;
+  neg = (a->sign == b->sign) ? MP_ZPOS : MP_NEG;
+
+  {
+    /* can we use the fast multiplier?
+     *
+     * The fast multiplier can be used if the output will
+     * have less than MP_WARRAY digits and the number of
+     * digits won't affect carry propagation
+     */
+    int     digs = a->used + b->used + 1;
+
+#ifdef BN_FAST_S_MP_MUL_DIGS_C
+    if ((digs < MP_WARRAY) &&
+        MIN(a->used, b->used) <=
+        (1 << ((CHAR_BIT * sizeof (mp_word)) - (2 * DIGIT_BIT)))) {
+      res = fast_s_mp_mul_digs (a, b, c, digs);
+    } else
+#endif
+#ifdef BN_S_MP_MUL_DIGS_C
+      res = s_mp_mul (a, b, c); /* uses s_mp_mul_digs */
+#else
+      res = MP_VAL;
+#endif
+
+  }
+  c->sign = (c->used > 0) ? neg : MP_ZPOS;
+  return res;
+}
+
+
+/* b = a*2 */
+int mp_mul_2(mp_int * a, mp_int * b)
+{
+  int     x, res, oldused;
+
+  /* grow to accomodate result */
+  if (b->alloc < a->used + 1) {
+    if ((res = mp_grow (b, a->used + 1)) != MP_OKAY) {
+      return res;
+    }
+  }
+
+  oldused = b->used;
+  b->used = a->used;
+
+  {
+    register mp_digit r, rr, *tmpa, *tmpb;
+
+    /* alias for source */
+    tmpa = a->dp;
+
+    /* alias for dest */
+    tmpb = b->dp;
+
+    /* carry */
+    r = 0;
+    for (x = 0; x < a->used; x++) {
+
+      /* get what will be the *next* carry bit from the
+       * MSB of the current digit
+       */
+      rr = *tmpa >> ((mp_digit)(DIGIT_BIT - 1));
+
+      /* now shift up this digit, add in the carry [from the previous] */
+      *tmpb++ = ((*tmpa++ << ((mp_digit)1)) | r) & MP_MASK;
+
+      /* copy the carry that would be from the source
+       * digit into the next iteration
+       */
+      r = rr;
+    }
+
+    /* new leading digit? */
+    if (r != 0) {
+      /* add a MSB which is always 1 at this point */
+      *tmpb = 1;
+      ++(b->used);
+    }
+
+    /* now zero any excess digits on the destination
+     * that we didn't write to
+     */
+    tmpb = b->dp + b->used;
+    for (x = b->used; x < oldused; x++) {
+      *tmpb++ = 0;
+    }
+  }
+  b->sign = a->sign;
+  return MP_OKAY;
+}
+
+
+/* divide by three (based on routine from MPI and the GMP manual) */
+int
+mp_div_3 (mp_int * a, mp_int *c, mp_digit * d)
+{
+  mp_int   q;
+  mp_word  w, t;
+  mp_digit b;
+  int      res, ix;
+
+  /* b = 2**DIGIT_BIT / 3 */
+  b = (mp_digit) ( (((mp_word)1) << ((mp_word)DIGIT_BIT)) / ((mp_word)3) );
+
+  if ((res = mp_init_size(&q, a->used)) != MP_OKAY) {
+     return res;
+  }
+
+  q.used = a->used;
+  q.sign = a->sign;
+  w = 0;
+  for (ix = a->used - 1; ix >= 0; ix--) {
+     w = (w << ((mp_word)DIGIT_BIT)) | ((mp_word)a->dp[ix]);
+
+     if (w >= 3) {
+        /* multiply w by [1/3] */
+        t = (w * ((mp_word)b)) >> ((mp_word)DIGIT_BIT);
+
+        /* now subtract 3 * [w/3] from w, to get the remainder */
+        w -= t+t+t;
+
+        /* fixup the remainder as required since
+         * the optimization is not exact.
+         */
+        while (w >= 3) {
+           t += 1;
+           w -= 3;
+        }
+      } else {
+        t = 0;
+      }
+      q.dp[ix] = (mp_digit)t;
+  }
+
+  /* [optional] store the remainder */
+  if (d != NULL) {
+     *d = (mp_digit)w;
+  }
+
+  /* [optional] store the quotient */
+  if (c != NULL) {
+     mp_clamp(&q);
+     mp_exch(&q, c);
+  }
+  mp_clear(&q);
+
+  return res;
+}
+
+
+/* init an mp_init for a given size */
+int mp_init_size (mp_int * a, int size)
+{
+  int x;
+
+  /* pad size so there are always extra digits */
+  size += (MP_PREC * 2) - (size % MP_PREC);
+
+  /* alloc mem */
+  a->dp = OPT_CAST(mp_digit) XMALLOC (sizeof (mp_digit) * size, 0,
+                                      DYNAMIC_TYPE_BIGINT);
+  if (a->dp == NULL) {
+    return MP_MEM;
+  }
+
+  /* set the members */
+  a->used  = 0;
+  a->alloc = size;
+  a->sign  = MP_ZPOS;
+
+  /* zero the digits */
+  for (x = 0; x < size; x++) {
+      a->dp[x] = 0;
+  }
+
+  return MP_OKAY;
+}
+
+
+/* the jist of squaring...
+ * you do like mult except the offset of the tmpx [one that
+ * starts closer to zero] can't equal the offset of tmpy.
+ * So basically you set up iy like before then you min it with
+ * (ty-tx) so that it never happens.  You double all those
+ * you add in the inner loop
+
+After that loop you do the squares and add them in.
+*/
+
+int fast_s_mp_sqr (mp_int * a, mp_int * b)
+{
+  int       olduse, res, pa, ix, iz;
+#ifdef WOLFSSL_SMALL_STACK
+  mp_digit* W;    /* uses dynamic memory and slower */
+#else
+  mp_digit W[MP_WARRAY];
+#endif
+  mp_digit  *tmpx;
+  mp_word   W1;
+
+  /* grow the destination as required */
+  pa = a->used + a->used;
+  if (b->alloc < pa) {
+    if ((res = mp_grow (b, pa)) != MP_OKAY) {
+      return res;
+    }
+  }
+
+  if (pa > MP_WARRAY)
+    return MP_RANGE;  /* TAO range check */
+
+#ifdef WOLFSSL_SMALL_STACK
+  W = (mp_digit*)XMALLOC(sizeof(mp_digit) * MP_WARRAY, 0, DYNAMIC_TYPE_BIGINT);
+  if (W == NULL)
+    return MP_MEM;
+#endif
+
+  /* number of output digits to produce */
+  W1 = 0;
+  for (ix = 0; ix < pa; ix++) {
+      int      tx, ty, iy;
+      mp_word  _W;
+      mp_digit *tmpy;
+
+      /* clear counter */
+      _W = 0;
+
+      /* get offsets into the two bignums */
+      ty = MIN(a->used-1, ix);
+      tx = ix - ty;
+
+      /* setup temp aliases */
+      tmpx = a->dp + tx;
+      tmpy = a->dp + ty;
+
+      /* this is the number of times the loop will iterrate, essentially
+         while (tx++ < a->used && ty-- >= 0) { ... }
+       */
+      iy = MIN(a->used-tx, ty+1);
+
+      /* now for squaring tx can never equal ty
+       * we halve the distance since they approach at a rate of 2x
+       * and we have to round because odd cases need to be executed
+       */
+      iy = MIN(iy, (ty-tx+1)>>1);
+
+      /* execute loop */
+      for (iz = 0; iz < iy; iz++) {
+         _W += ((mp_word)*tmpx++)*((mp_word)*tmpy--);
+      }
+
+      /* double the inner product and add carry */
+      _W = _W + _W + W1;
+
+      /* even columns have the square term in them */
+      if ((ix&1) == 0) {
+         _W += ((mp_word)a->dp[ix>>1])*((mp_word)a->dp[ix>>1]);
+      }
+
+      /* store it */
+      W[ix] = (mp_digit)(_W & MP_MASK);
+
+      /* make next carry */
+      W1 = _W >> ((mp_word)DIGIT_BIT);
+  }
+
+  /* setup dest */
+  olduse  = b->used;
+  b->used = a->used+a->used;
+
+  {
+    mp_digit *tmpb;
+    tmpb = b->dp;
+    for (ix = 0; ix < pa; ix++) {
+      *tmpb++ = W[ix] & MP_MASK;
+    }
+
+    /* clear unused digits [that existed in the old copy of c] */
+    for (; ix < olduse; ix++) {
+      *tmpb++ = 0;
+    }
+  }
+  mp_clamp (b);
+
+#ifdef WOLFSSL_SMALL_STACK
+  XFREE(W, 0, DYNAMIC_TYPE_BIGINT);
+#endif
+
+  return MP_OKAY;
+}
+
+
+/* Fast (comba) multiplier
+ *
+ * This is the fast column-array [comba] multiplier.  It is
+ * designed to compute the columns of the product first
+ * then handle the carries afterwards.  This has the effect
+ * of making the nested loops that compute the columns very
+ * simple and schedulable on super-scalar processors.
+ *
+ * This has been modified to produce a variable number of
+ * digits of output so if say only a half-product is required
+ * you don't have to compute the upper half (a feature
+ * required for fast Barrett reduction).
+ *
+ * Based on Algorithm 14.12 on pp.595 of HAC.
+ *
+ */
+int fast_s_mp_mul_digs (mp_int * a, mp_int * b, mp_int * c, int digs)
+{
+  int     olduse, res, pa, ix, iz;
+#ifdef WOLFSSL_SMALL_STACK
+  mp_digit* W;    /* uses dynamic memory and slower */
+#else
+  mp_digit W[MP_WARRAY];
+#endif
+  register mp_word  _W;
+
+  /* grow the destination as required */
+  if (c->alloc < digs) {
+    if ((res = mp_grow (c, digs)) != MP_OKAY) {
+      return res;
+    }
+  }
+
+  /* number of output digits to produce */
+  pa = MIN(digs, a->used + b->used);
+  if (pa > MP_WARRAY)
+    return MP_RANGE;  /* TAO range check */
+
+#ifdef WOLFSSL_SMALL_STACK
+  W = (mp_digit*)XMALLOC(sizeof(mp_digit) * MP_WARRAY, 0, DYNAMIC_TYPE_BIGINT);
+  if (W == NULL)
+    return MP_MEM;
+#endif
+
+  /* clear the carry */
+  _W = 0;
+  for (ix = 0; ix < pa; ix++) {
+      int      tx, ty;
+      int      iy;
+      mp_digit *tmpx, *tmpy;
+
+      /* get offsets into the two bignums */
+      ty = MIN(b->used-1, ix);
+      tx = ix - ty;
+
+      /* setup temp aliases */
+      tmpx = a->dp + tx;
+      tmpy = b->dp + ty;
+
+      /* this is the number of times the loop will iterrate, essentially
+         while (tx++ < a->used && ty-- >= 0) { ... }
+       */
+      iy = MIN(a->used-tx, ty+1);
+
+      /* execute loop */
+      for (iz = 0; iz < iy; ++iz) {
+         _W += ((mp_word)*tmpx++)*((mp_word)*tmpy--);
+
+      }
+
+      /* store term */
+      W[ix] = ((mp_digit)_W) & MP_MASK;
+
+      /* make next carry */
+      _W = _W >> ((mp_word)DIGIT_BIT);
+ }
+
+  /* setup dest */
+  olduse  = c->used;
+  c->used = pa;
+
+  {
+    register mp_digit *tmpc;
+    tmpc = c->dp;
+    for (ix = 0; ix < pa+1; ix++) {
+      /* now extract the previous digit [below the carry] */
+      *tmpc++ = W[ix];
+    }
+
+    /* clear unused digits [that existed in the old copy of c] */
+    for (; ix < olduse; ix++) {
+      *tmpc++ = 0;
+    }
+  }
+  mp_clamp (c);
+
+#ifdef WOLFSSL_SMALL_STACK
+  XFREE(W, 0, DYNAMIC_TYPE_BIGINT);
+#endif
+
+  return MP_OKAY;
+}
+
+
+/* low level squaring, b = a*a, HAC pp.596-597, Algorithm 14.16 */
+int s_mp_sqr (mp_int * a, mp_int * b)
+{
+  mp_int  t;
+  int     res, ix, iy, pa;
+  mp_word r;
+  mp_digit u, tmpx, *tmpt;
+
+  pa = a->used;
+  if ((res = mp_init_size (&t, 2*pa + 1)) != MP_OKAY) {
+    return res;
+  }
+
+  /* default used is maximum possible size */
+  t.used = 2*pa + 1;
+
+  for (ix = 0; ix < pa; ix++) {
+    /* first calculate the digit at 2*ix */
+    /* calculate double precision result */
+    r = ((mp_word) t.dp[2*ix]) +
+        ((mp_word)a->dp[ix])*((mp_word)a->dp[ix]);
+
+    /* store lower part in result */
+    t.dp[ix+ix] = (mp_digit) (r & ((mp_word) MP_MASK));
+
+    /* get the carry */
+    u           = (mp_digit)(r >> ((mp_word) DIGIT_BIT));
+
+    /* left hand side of A[ix] * A[iy] */
+    tmpx        = a->dp[ix];
+
+    /* alias for where to store the results */
+    tmpt        = t.dp + (2*ix + 1);
+
+    for (iy = ix + 1; iy < pa; iy++) {
+      /* first calculate the product */
+      r       = ((mp_word)tmpx) * ((mp_word)a->dp[iy]);
+
+      /* now calculate the double precision result, note we use
+       * addition instead of *2 since it's easier to optimize
+       */
+      r       = ((mp_word) *tmpt) + r + r + ((mp_word) u);
+
+      /* store lower part */
+      *tmpt++ = (mp_digit) (r & ((mp_word) MP_MASK));
+
+      /* get carry */
+      u       = (mp_digit)(r >> ((mp_word) DIGIT_BIT));
+    }
+    /* propagate upwards */
+    while (u != ((mp_digit) 0)) {
+      r       = ((mp_word) *tmpt) + ((mp_word) u);
+      *tmpt++ = (mp_digit) (r & ((mp_word) MP_MASK));
+      u       = (mp_digit)(r >> ((mp_word) DIGIT_BIT));
+    }
+  }
+
+  mp_clamp (&t);
+  mp_exch (&t, b);
+  mp_clear (&t);
+  return MP_OKAY;
+}
+
+
+/* multiplies |a| * |b| and only computes upto digs digits of result
+ * HAC pp. 595, Algorithm 14.12  Modified so you can control how
+ * many digits of output are created.
+ */
+int s_mp_mul_digs (mp_int * a, mp_int * b, mp_int * c, int digs)
+{
+  mp_int  t;
+  int     res, pa, pb, ix, iy;
+  mp_digit u;
+  mp_word r;
+  mp_digit tmpx, *tmpt, *tmpy;
+
+  /* can we use the fast multiplier? */
+  if (((digs) < MP_WARRAY) &&
+      MIN (a->used, b->used) <
+          (1 << ((CHAR_BIT * sizeof (mp_word)) - (2 * DIGIT_BIT)))) {
+    return fast_s_mp_mul_digs (a, b, c, digs);
+  }
+
+  if ((res = mp_init_size (&t, digs)) != MP_OKAY) {
+    return res;
+  }
+  t.used = digs;
+
+  /* compute the digits of the product directly */
+  pa = a->used;
+  for (ix = 0; ix < pa; ix++) {
+    /* set the carry to zero */
+    u = 0;
+
+    /* limit ourselves to making digs digits of output */
+    pb = MIN (b->used, digs - ix);
+
+    /* setup some aliases */
+    /* copy of the digit from a used within the nested loop */
+    tmpx = a->dp[ix];
+
+    /* an alias for the destination shifted ix places */
+    tmpt = t.dp + ix;
+
+    /* an alias for the digits of b */
+    tmpy = b->dp;
+
+    /* compute the columns of the output and propagate the carry */
+    for (iy = 0; iy < pb; iy++) {
+      /* compute the column as a mp_word */
+      r       = ((mp_word)*tmpt) +
+                ((mp_word)tmpx) * ((mp_word)*tmpy++) +
+                ((mp_word) u);
+
+      /* the new column is the lower part of the result */
+      *tmpt++ = (mp_digit) (r & ((mp_word) MP_MASK));
+
+      /* get the carry word from the result */
+      u       = (mp_digit) (r >> ((mp_word) DIGIT_BIT));
+    }
+    /* set carry if it is placed below digs */
+    if (ix + iy < digs) {
+      *tmpt = u;
+    }
+  }
+
+  mp_clamp (&t);
+  mp_exch (&t, c);
+
+  mp_clear (&t);
+  return MP_OKAY;
+}
+
+
+/*
+ * shifts with subtractions when the result is greater than b.
+ *
+ * The method is slightly modified to shift B unconditionally upto just under
+ * the leading bit of b.  This saves alot of multiple precision shifting.
+ */
+int mp_montgomery_calc_normalization (mp_int * a, mp_int * b)
+{
+  int     x, bits, res;
+
+  /* how many bits of last digit does b use */
+  bits = mp_count_bits (b) % DIGIT_BIT;
+
+  if (b->used > 1) {
+     if ((res = mp_2expt (a, (b->used - 1) * DIGIT_BIT + bits - 1)) != MP_OKAY) {
+        return res;
+     }
+  } else {
+     mp_set(a, 1);
+     bits = 1;
+  }
+
+
+  /* now compute C = A * B mod b */
+  for (x = bits - 1; x < (int)DIGIT_BIT; x++) {
+    if ((res = mp_mul_2 (a, a)) != MP_OKAY) {
+      return res;
+    }
+    if (mp_cmp_mag (a, b) != MP_LT) {
+      if ((res = s_mp_sub (a, b, a)) != MP_OKAY) {
+        return res;
+      }
+    }
+  }
+
+  return MP_OKAY;
+}
+
+
+#ifdef MP_LOW_MEM
+   #define TAB_SIZE 32
+#else
+   #define TAB_SIZE 256
+#endif
+
+int s_mp_exptmod (mp_int * G, mp_int * X, mp_int * P, mp_int * Y, int redmode)
+{
+  mp_int  M[TAB_SIZE], res, mu;
+  mp_digit buf;
+  int     err, bitbuf, bitcpy, bitcnt, mode, digidx, x, y, winsize;
+  int (*redux)(mp_int*,mp_int*,mp_int*);
+
+  /* find window size */
+  x = mp_count_bits (X);
+  if (x <= 7) {
+    winsize = 2;
+  } else if (x <= 36) {
+    winsize = 3;
+  } else if (x <= 140) {
+    winsize = 4;
+  } else if (x <= 450) {
+    winsize = 5;
+  } else if (x <= 1303) {
+    winsize = 6;
+  } else if (x <= 3529) {
+    winsize = 7;
+  } else {
+    winsize = 8;
+  }
+
+#ifdef MP_LOW_MEM
+    if (winsize > 5) {
+       winsize = 5;
+    }
+#endif
+
+  /* init M array */
+  /* init first cell */
+  if ((err = mp_init(&M[1])) != MP_OKAY) {
+     return err;
+  }
+
+  /* now init the second half of the array */
+  for (x = 1<<(winsize-1); x < (1 << winsize); x++) {
+    if ((err = mp_init(&M[x])) != MP_OKAY) {
+      for (y = 1<<(winsize-1); y < x; y++) {
+        mp_clear (&M[y]);
+      }
+      mp_clear(&M[1]);
+      return err;
+    }
+  }
+
+  /* create mu, used for Barrett reduction */
+  if ((err = mp_init (&mu)) != MP_OKAY) {
+    goto LBL_M;
+  }
+
+  if (redmode == 0) {
+     if ((err = mp_reduce_setup (&mu, P)) != MP_OKAY) {
+        goto LBL_MU;
+     }
+     redux = mp_reduce;
+  } else {
+     if ((err = mp_reduce_2k_setup_l (P, &mu)) != MP_OKAY) {
+        goto LBL_MU;
+     }
+     redux = mp_reduce_2k_l;
+  }
+
+  /* create M table
+   *
+   * The M table contains powers of the base,
+   * e.g. M[x] = G**x mod P
+   *
+   * The first half of the table is not
+   * computed though accept for M[0] and M[1]
+   */
+  if ((err = mp_mod (G, P, &M[1])) != MP_OKAY) {
+    goto LBL_MU;
+  }
+
+  /* compute the value at M[1<<(winsize-1)] by squaring
+   * M[1] (winsize-1) times
+   */
+  if ((err = mp_copy (&M[1], &M[(mp_digit)(1 << (winsize - 1))])) != MP_OKAY) {
+    goto LBL_MU;
+  }
+
+  for (x = 0; x < (winsize - 1); x++) {
+    /* square it */
+    if ((err = mp_sqr (&M[(mp_digit)(1 << (winsize - 1))],
+                       &M[(mp_digit)(1 << (winsize - 1))])) != MP_OKAY) {
+      goto LBL_MU;
+    }
+
+    /* reduce modulo P */
+    if ((err = redux (&M[(mp_digit)(1 << (winsize - 1))], P, &mu)) != MP_OKAY) {
+      goto LBL_MU;
+    }
+  }
+
+  /* create upper table, that is M[x] = M[x-1] * M[1] (mod P)
+   * for x = (2**(winsize - 1) + 1) to (2**winsize - 1)
+   */
+  for (x = (1 << (winsize - 1)) + 1; x < (1 << winsize); x++) {
+    if ((err = mp_mul (&M[x - 1], &M[1], &M[x])) != MP_OKAY) {
+      goto LBL_MU;
+    }
+    if ((err = redux (&M[x], P, &mu)) != MP_OKAY) {
+      goto LBL_MU;
+    }
+  }
+
+  /* setup result */
+  if ((err = mp_init (&res)) != MP_OKAY) {
+    goto LBL_MU;
+  }
+  mp_set (&res, 1);
+
+  /* set initial mode and bit cnt */
+  mode   = 0;
+  bitcnt = 1;
+  buf    = 0;
+  digidx = X->used - 1;
+  bitcpy = 0;
+  bitbuf = 0;
+
+  for (;;) {
+    /* grab next digit as required */
+    if (--bitcnt == 0) {
+      /* if digidx == -1 we are out of digits */
+      if (digidx == -1) {
+        break;
+      }
+      /* read next digit and reset the bitcnt */
+      buf    = X->dp[digidx--];
+      bitcnt = (int) DIGIT_BIT;
+    }
+
+    /* grab the next msb from the exponent */
+    y     = (int)(buf >> (mp_digit)(DIGIT_BIT - 1)) & 1;
+    buf <<= (mp_digit)1;
+
+    /* if the bit is zero and mode == 0 then we ignore it
+     * These represent the leading zero bits before the first 1 bit
+     * in the exponent.  Technically this opt is not required but it
+     * does lower the # of trivial squaring/reductions used
+     */
+    if (mode == 0 && y == 0) {
+      continue;
+    }
+
+    /* if the bit is zero and mode == 1 then we square */
+    if (mode == 1 && y == 0) {
+      if ((err = mp_sqr (&res, &res)) != MP_OKAY) {
+        goto LBL_RES;
+      }
+      if ((err = redux (&res, P, &mu)) != MP_OKAY) {
+        goto LBL_RES;
+      }
+      continue;
+    }
+
+    /* else we add it to the window */
+    bitbuf |= (y << (winsize - ++bitcpy));
+    mode    = 2;
+
+    if (bitcpy == winsize) {
+      /* ok window is filled so square as required and multiply  */
+      /* square first */
+      for (x = 0; x < winsize; x++) {
+        if ((err = mp_sqr (&res, &res)) != MP_OKAY) {
+          goto LBL_RES;
+        }
+        if ((err = redux (&res, P, &mu)) != MP_OKAY) {
+          goto LBL_RES;
+        }
+      }
+
+      /* then multiply */
+      if ((err = mp_mul (&res, &M[bitbuf], &res)) != MP_OKAY) {
+        goto LBL_RES;
+      }
+      if ((err = redux (&res, P, &mu)) != MP_OKAY) {
+        goto LBL_RES;
+      }
+
+      /* empty window and reset */
+      bitcpy = 0;
+      bitbuf = 0;
+      mode   = 1;
+    }
+  }
+
+  /* if bits remain then square/multiply */
+  if (mode == 2 && bitcpy > 0) {
+    /* square then multiply if the bit is set */
+    for (x = 0; x < bitcpy; x++) {
+      if ((err = mp_sqr (&res, &res)) != MP_OKAY) {
+        goto LBL_RES;
+      }
+      if ((err = redux (&res, P, &mu)) != MP_OKAY) {
+        goto LBL_RES;
+      }
+
+      bitbuf <<= 1;
+      if ((bitbuf & (1 << winsize)) != 0) {
+        /* then multiply */
+        if ((err = mp_mul (&res, &M[1], &res)) != MP_OKAY) {
+          goto LBL_RES;
+        }
+        if ((err = redux (&res, P, &mu)) != MP_OKAY) {
+          goto LBL_RES;
+        }
+      }
+    }
+  }
+
+  mp_exch (&res, Y);
+  err = MP_OKAY;
+LBL_RES:mp_clear (&res);
+LBL_MU:mp_clear (&mu);
+LBL_M:
+  mp_clear(&M[1]);
+  for (x = 1<<(winsize-1); x < (1 << winsize); x++) {
+    mp_clear (&M[x]);
+  }
+  return err;
+}
+
+
+/* pre-calculate the value required for Barrett reduction
+ * For a given modulus "b" it calulates the value required in "a"
+ */
+int mp_reduce_setup (mp_int * a, mp_int * b)
+{
+  int     res;
+
+  if ((res = mp_2expt (a, b->used * 2 * DIGIT_BIT)) != MP_OKAY) {
+    return res;
+  }
+  return mp_div (a, b, a, NULL);
+}
+
+
+/* reduces x mod m, assumes 0 < x < m**2, mu is
+ * precomputed via mp_reduce_setup.
+ * From HAC pp.604 Algorithm 14.42
+ */
+int mp_reduce (mp_int * x, mp_int * m, mp_int * mu)
+{
+  mp_int  q;
+  int     res, um = m->used;
+
+  /* q = x */
+  if ((res = mp_init_copy (&q, x)) != MP_OKAY) {
+    return res;
+  }
+
+  /* q1 = x / b**(k-1)  */
+  mp_rshd (&q, um - 1);
+
+  /* according to HAC this optimization is ok */
+  if (((mp_word) um) > (((mp_digit)1) << (DIGIT_BIT - 1))) {
+    if ((res = mp_mul (&q, mu, &q)) != MP_OKAY) {
+      goto CLEANUP;
+    }
+  } else {
+#ifdef BN_S_MP_MUL_HIGH_DIGS_C
+    if ((res = s_mp_mul_high_digs (&q, mu, &q, um)) != MP_OKAY) {
+      goto CLEANUP;
+    }
+#elif defined(BN_FAST_S_MP_MUL_HIGH_DIGS_C)
+    if ((res = fast_s_mp_mul_high_digs (&q, mu, &q, um)) != MP_OKAY) {
+      goto CLEANUP;
+    }
+#else
+    {
+      res = MP_VAL;
+      goto CLEANUP;
+    }
+#endif
+  }
+
+  /* q3 = q2 / b**(k+1) */
+  mp_rshd (&q, um + 1);
+
+  /* x = x mod b**(k+1), quick (no division) */
+  if ((res = mp_mod_2d (x, DIGIT_BIT * (um + 1), x)) != MP_OKAY) {
+    goto CLEANUP;
+  }
+
+  /* q = q * m mod b**(k+1), quick (no division) */
+  if ((res = s_mp_mul_digs (&q, m, &q, um + 1)) != MP_OKAY) {
+    goto CLEANUP;
+  }
+
+  /* x = x - q */
+  if ((res = mp_sub (x, &q, x)) != MP_OKAY) {
+    goto CLEANUP;
+  }
+
+  /* If x < 0, add b**(k+1) to it */
+  if (mp_cmp_d (x, 0) == MP_LT) {
+    mp_set (&q, 1);
+    if ((res = mp_lshd (&q, um + 1)) != MP_OKAY)
+      goto CLEANUP;
+    if ((res = mp_add (x, &q, x)) != MP_OKAY)
+      goto CLEANUP;
+  }
+
+  /* Back off if it's too big */
+  while (mp_cmp (x, m) != MP_LT) {
+    if ((res = s_mp_sub (x, m, x)) != MP_OKAY) {
+      goto CLEANUP;
+    }
+  }
+
+CLEANUP:
+  mp_clear (&q);
+
+  return res;
+}
+
+
+/* reduces a modulo n where n is of the form 2**p - d
+   This differs from reduce_2k since "d" can be larger
+   than a single digit.
+*/
+int mp_reduce_2k_l(mp_int *a, mp_int *n, mp_int *d)
+{
+   mp_int q;
+   int    p, res;
+
+   if ((res = mp_init(&q)) != MP_OKAY) {
+      return res;
+   }
+
+   p = mp_count_bits(n);
+top:
+   /* q = a/2**p, a = a mod 2**p */
+   if ((res = mp_div_2d(a, p, &q, a)) != MP_OKAY) {
+      goto ERR;
+   }
+
+   /* q = q * d */
+   if ((res = mp_mul(&q, d, &q)) != MP_OKAY) {
+      goto ERR;
+   }
+
+   /* a = a + q */
+   if ((res = s_mp_add(a, &q, a)) != MP_OKAY) {
+      goto ERR;
+   }
+
+   if (mp_cmp_mag(a, n) != MP_LT) {
+      s_mp_sub(a, n, a);
+      goto top;
+   }
+
+ERR:
+   mp_clear(&q);
+   return res;
+}
+
+
+/* determines the setup value */
+int mp_reduce_2k_setup_l(mp_int *a, mp_int *d)
+{
+   int    res;
+   mp_int tmp;
+
+   if ((res = mp_init(&tmp)) != MP_OKAY) {
+      return res;
+   }
+
+   if ((res = mp_2expt(&tmp, mp_count_bits(a))) != MP_OKAY) {
+      goto ERR;
+   }
+
+   if ((res = s_mp_sub(&tmp, a, d)) != MP_OKAY) {
+      goto ERR;
+   }
+
+ERR:
+   mp_clear(&tmp);
+   return res;
+}
+
+
+/* multiplies |a| * |b| and does not compute the lower digs digits
+ * [meant to get the higher part of the product]
+ */
+int
+s_mp_mul_high_digs (mp_int * a, mp_int * b, mp_int * c, int digs)
+{
+  mp_int  t;
+  int     res, pa, pb, ix, iy;
+  mp_digit u;
+  mp_word r;
+  mp_digit tmpx, *tmpt, *tmpy;
+
+  /* can we use the fast multiplier? */
+#ifdef BN_FAST_S_MP_MUL_HIGH_DIGS_C
+  if (((a->used + b->used + 1) < MP_WARRAY)
+      && MIN (a->used, b->used) < (1 << ((CHAR_BIT * sizeof (mp_word)) - (2 * DIGIT_BIT)))) {
+    return fast_s_mp_mul_high_digs (a, b, c, digs);
+  }
+#endif
+
+  if ((res = mp_init_size (&t, a->used + b->used + 1)) != MP_OKAY) {
+    return res;
+  }
+  t.used = a->used + b->used + 1;
+
+  pa = a->used;
+  pb = b->used;
+  for (ix = 0; ix < pa; ix++) {
+    /* clear the carry */
+    u = 0;
+
+    /* left hand side of A[ix] * B[iy] */
+    tmpx = a->dp[ix];
+
+    /* alias to the address of where the digits will be stored */
+    tmpt = &(t.dp[digs]);
+
+    /* alias for where to read the right hand side from */
+    tmpy = b->dp + (digs - ix);
+
+    for (iy = digs - ix; iy < pb; iy++) {
+      /* calculate the double precision result */
+      r       = ((mp_word)*tmpt) +
+                ((mp_word)tmpx) * ((mp_word)*tmpy++) +
+                ((mp_word) u);
+
+      /* get the lower part */
+      *tmpt++ = (mp_digit) (r & ((mp_word) MP_MASK));
+
+      /* carry the carry */
+      u       = (mp_digit) (r >> ((mp_word) DIGIT_BIT));
+    }
+    *tmpt = u;
+  }
+  mp_clamp (&t);
+  mp_exch (&t, c);
+  mp_clear (&t);
+  return MP_OKAY;
+}
+
+
+/* this is a modified version of fast_s_mul_digs that only produces
+ * output digits *above* digs.  See the comments for fast_s_mul_digs
+ * to see how it works.
+ *
+ * This is used in the Barrett reduction since for one of the multiplications
+ * only the higher digits were needed.  This essentially halves the work.
+ *
+ * Based on Algorithm 14.12 on pp.595 of HAC.
+ */
+int fast_s_mp_mul_high_digs (mp_int * a, mp_int * b, mp_int * c, int digs)
+{
+  int     olduse, res, pa, ix, iz;
+#ifdef WOLFSSL_SMALL_STACK
+  mp_digit* W;    /* uses dynamic memory and slower */
+#else
+  mp_digit W[MP_WARRAY];
+#endif
+  mp_word  _W;
+
+  /* grow the destination as required */
+  pa = a->used + b->used;
+  if (c->alloc < pa) {
+    if ((res = mp_grow (c, pa)) != MP_OKAY) {
+      return res;
+    }
+  }
+
+  if (pa > MP_WARRAY)
+    return MP_RANGE;  /* TAO range check */
+
+#ifdef WOLFSSL_SMALL_STACK
+  W = (mp_digit*)XMALLOC(sizeof(mp_digit) * MP_WARRAY, 0, DYNAMIC_TYPE_BIGINT);
+  if (W == NULL)
+    return MP_MEM;
+#endif
+
+  /* number of output digits to produce */
+  pa = a->used + b->used;
+  _W = 0;
+  for (ix = digs; ix < pa; ix++) {
+      int      tx, ty, iy;
+      mp_digit *tmpx, *tmpy;
+
+      /* get offsets into the two bignums */
+      ty = MIN(b->used-1, ix);
+      tx = ix - ty;
+
+      /* setup temp aliases */
+      tmpx = a->dp + tx;
+      tmpy = b->dp + ty;
+
+      /* this is the number of times the loop will iterrate, essentially its
+         while (tx++ < a->used && ty-- >= 0) { ... }
+       */
+      iy = MIN(a->used-tx, ty+1);
+
+      /* execute loop */
+      for (iz = 0; iz < iy; iz++) {
+         _W += ((mp_word)*tmpx++)*((mp_word)*tmpy--);
+      }
+
+      /* store term */
+      W[ix] = ((mp_digit)_W) & MP_MASK;
+
+      /* make next carry */
+      _W = _W >> ((mp_word)DIGIT_BIT);
+  }
+
+  /* setup dest */
+  olduse  = c->used;
+  c->used = pa;
+
+  {
+    register mp_digit *tmpc;
+
+    tmpc = c->dp + digs;
+    for (ix = digs; ix <= pa; ix++) {
+      /* now extract the previous digit [below the carry] */
+      *tmpc++ = W[ix];
+    }
+
+    /* clear unused digits [that existed in the old copy of c] */
+    for (; ix < olduse; ix++) {
+      *tmpc++ = 0;
+    }
+  }
+  mp_clamp (c);
+
+#ifdef WOLFSSL_SMALL_STACK
+  XFREE(W, 0, DYNAMIC_TYPE_BIGINT);
+#endif
+
+  return MP_OKAY;
+}
+
+
+/* set a 32-bit const */
+int mp_set_int (mp_int * a, unsigned long b)
+{
+  int     x, res;
+
+  mp_zero (a);
+
+  /* set four bits at a time */
+  for (x = 0; x < 8; x++) {
+    /* shift the number up four bits */
+    if ((res = mp_mul_2d (a, 4, a)) != MP_OKAY) {
+      return res;
+    }
+
+    /* OR in the top four bits of the source */
+    a->dp[0] |= (b >> 28) & 15;
+
+    /* shift the source up to the next four bits */
+    b <<= 4;
+
+    /* ensure that digits are not clamped off */
+    a->used += 1;
+  }
+  mp_clamp (a);
+  return MP_OKAY;
+}
+
+
+#if defined(WOLFSSL_KEY_GEN) || defined(HAVE_ECC)
+
+/* c = a * a (mod b) */
+int mp_sqrmod (mp_int * a, mp_int * b, mp_int * c)
+{
+  int     res;
+  mp_int  t;
+
+  if ((res = mp_init (&t)) != MP_OKAY) {
+    return res;
+  }
+
+  if ((res = mp_sqr (a, &t)) != MP_OKAY) {
+    mp_clear (&t);
+    return res;
+  }
+  res = mp_mod (&t, b, c);
+  mp_clear (&t);
+  return res;
+}
+
+#endif
+
+
+#if defined(HAVE_ECC) || !defined(NO_PWDBASED) || defined(WOLFSSL_SNIFFER) || defined(WOLFSSL_HAVE_WOLFSCEP) || defined(WOLFSSL_KEY_GEN)
+
+/* single digit addition */
+int mp_add_d (mp_int* a, mp_digit b, mp_int* c)
+{
+  int     res, ix, oldused;
+  mp_digit *tmpa, *tmpc, mu;
+
+  /* grow c as required */
+  if (c->alloc < a->used + 1) {
+     if ((res = mp_grow(c, a->used + 1)) != MP_OKAY) {
+        return res;
+     }
+  }
+
+  /* if a is negative and |a| >= b, call c = |a| - b */
+  if (a->sign == MP_NEG && (a->used > 1 || a->dp[0] >= b)) {
+     /* temporarily fix sign of a */
+     a->sign = MP_ZPOS;
+
+     /* c = |a| - b */
+     res = mp_sub_d(a, b, c);
+
+     /* fix sign  */
+     a->sign = c->sign = MP_NEG;
+
+     /* clamp */
+     mp_clamp(c);
+
+     return res;
+  }
+
+  /* old number of used digits in c */
+  oldused = c->used;
+
+  /* sign always positive */
+  c->sign = MP_ZPOS;
+
+  /* source alias */
+  tmpa    = a->dp;
+
+  /* destination alias */
+  tmpc    = c->dp;
+
+  /* if a is positive */
+  if (a->sign == MP_ZPOS) {
+     /* add digit, after this we're propagating
+      * the carry.
+      */
+     *tmpc   = *tmpa++ + b;
+     mu      = *tmpc >> DIGIT_BIT;
+     *tmpc++ &= MP_MASK;
+
+     /* now handle rest of the digits */
+     for (ix = 1; ix < a->used; ix++) {
+        *tmpc   = *tmpa++ + mu;
+        mu      = *tmpc >> DIGIT_BIT;
+        *tmpc++ &= MP_MASK;
+     }
+     /* set final carry */
+     if (mu != 0 && ix < c->alloc) {
+        ix++;
+        *tmpc++  = mu;
+     }
+
+     /* setup size */
+     c->used = a->used + 1;
+  } else {
+     /* a was negative and |a| < b */
+     c->used  = 1;
+
+     /* the result is a single digit */
+     if (a->used == 1) {
+        *tmpc++  =  b - a->dp[0];
+     } else {
+        *tmpc++  =  b;
+     }
+
+     /* setup count so the clearing of oldused
+      * can fall through correctly
+      */
+     ix       = 1;
+  }
+
+  /* now zero to oldused */
+  while (ix++ < oldused) {
+     *tmpc++ = 0;
+  }
+  mp_clamp(c);
+
+  return MP_OKAY;
+}
+
+
+/* single digit subtraction */
+int mp_sub_d (mp_int * a, mp_digit b, mp_int * c)
+{
+  mp_digit *tmpa, *tmpc, mu;
+  int       res, ix, oldused;
+
+  /* grow c as required */
+  if (c->alloc < a->used + 1) {
+     if ((res = mp_grow(c, a->used + 1)) != MP_OKAY) {
+        return res;
+     }
+  }
+
+  /* if a is negative just do an unsigned
+   * addition [with fudged signs]
+   */
+  if (a->sign == MP_NEG) {
+     a->sign = MP_ZPOS;
+     res     = mp_add_d(a, b, c);
+     a->sign = c->sign = MP_NEG;
+
+     /* clamp */
+     mp_clamp(c);
+
+     return res;
+  }
+
+  /* setup regs */
+  oldused = c->used;
+  tmpa    = a->dp;
+  tmpc    = c->dp;
+
+  /* if a <= b simply fix the single digit */
+  if ((a->used == 1 && a->dp[0] <= b) || a->used == 0) {
+     if (a->used == 1) {
+        *tmpc++ = b - *tmpa;
+     } else {
+        *tmpc++ = b;
+     }
+     ix      = 1;
+
+     /* negative/1digit */
+     c->sign = MP_NEG;
+     c->used = 1;
+  } else {
+     /* positive/size */
+     c->sign = MP_ZPOS;
+     c->used = a->used;
+
+     /* subtract first digit */
+     *tmpc    = *tmpa++ - b;
+     mu       = *tmpc >> (sizeof(mp_digit) * CHAR_BIT - 1);
+     *tmpc++ &= MP_MASK;
+
+     /* handle rest of the digits */
+     for (ix = 1; ix < a->used; ix++) {
+        *tmpc    = *tmpa++ - mu;
+        mu       = *tmpc >> (sizeof(mp_digit) * CHAR_BIT - 1);
+        *tmpc++ &= MP_MASK;
+     }
+  }
+
+  /* zero excess digits */
+  while (ix++ < oldused) {
+     *tmpc++ = 0;
+  }
+  mp_clamp(c);
+  return MP_OKAY;
+}
+
+#endif /* defined(HAVE_ECC) || !defined(NO_PWDBASED) */
+
+
+#if defined(WOLFSSL_KEY_GEN) || defined(HAVE_COMP_KEY)
+
+static const int lnz[16] = {
+   4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0
+};
+
+/* Counts the number of lsbs which are zero before the first zero bit */
+int mp_cnt_lsb(mp_int *a)
+{
+    int x;
+    mp_digit q, qq;
+
+    /* easy out */
+    if (mp_iszero(a) == 1) {
+        return 0;
+    }
+
+    /* scan lower digits until non-zero */
+    for (x = 0; x < a->used && a->dp[x] == 0; x++);
+    q = a->dp[x];
+    x *= DIGIT_BIT;
+
+    /* now scan this digit until a 1 is found */
+    if ((q & 1) == 0) {
+        do {
+            qq  = q & 15;
+            x  += lnz[qq];
+            q >>= 4;
+        } while (qq == 0);
+    }
+    return x;
+}
+
+
+
+
+static int s_is_power_of_two(mp_digit b, int *p)
+{
+   int x;
+
+   /* fast return if no power of two */
+   if ((b==0) || (b & (b-1))) {
+      return 0;
+   }
+
+   for (x = 0; x < DIGIT_BIT; x++) {
+      if (b == (((mp_digit)1)<dp[0] & ((((mp_digit)1)<used)) != MP_OKAY) {
+     return res;
+  }
+
+  q.used = a->used;
+  q.sign = a->sign;
+  w = 0;
+  for (ix = a->used - 1; ix >= 0; ix--) {
+     w = (w << ((mp_word)DIGIT_BIT)) | ((mp_word)a->dp[ix]);
+
+     if (w >= b) {
+        t = (mp_digit)(w / b);
+        w -= ((mp_word)t) * ((mp_word)b);
+      } else {
+        t = 0;
+      }
+      q.dp[ix] = (mp_digit)t;
+  }
+
+  if (d != NULL) {
+     *d = (mp_digit)w;
+  }
+
+  if (c != NULL) {
+     mp_clamp(&q);
+     mp_exch(&q, c);
+  }
+  mp_clear(&q);
+
+  return res;
+}
+
+
+int mp_mod_d (mp_int * a, mp_digit b, mp_digit * c)
+{
+  return mp_div_d(a, b, NULL, c);
+}
+
+#endif /* defined(WOLFSSL_KEY_GEN) || defined(HAVE_COMP_KEY) */
+
+#ifdef WOLFSSL_KEY_GEN
+
+const mp_digit ltm_prime_tab[] = {
+  0x0002, 0x0003, 0x0005, 0x0007, 0x000B, 0x000D, 0x0011, 0x0013,
+  0x0017, 0x001D, 0x001F, 0x0025, 0x0029, 0x002B, 0x002F, 0x0035,
+  0x003B, 0x003D, 0x0043, 0x0047, 0x0049, 0x004F, 0x0053, 0x0059,
+  0x0061, 0x0065, 0x0067, 0x006B, 0x006D, 0x0071, 0x007F,
+#ifndef MP_8BIT
+  0x0083,
+  0x0089, 0x008B, 0x0095, 0x0097, 0x009D, 0x00A3, 0x00A7, 0x00AD,
+  0x00B3, 0x00B5, 0x00BF, 0x00C1, 0x00C5, 0x00C7, 0x00D3, 0x00DF,
+  0x00E3, 0x00E5, 0x00E9, 0x00EF, 0x00F1, 0x00FB, 0x0101, 0x0107,
+  0x010D, 0x010F, 0x0115, 0x0119, 0x011B, 0x0125, 0x0133, 0x0137,
+
+  0x0139, 0x013D, 0x014B, 0x0151, 0x015B, 0x015D, 0x0161, 0x0167,
+  0x016F, 0x0175, 0x017B, 0x017F, 0x0185, 0x018D, 0x0191, 0x0199,
+  0x01A3, 0x01A5, 0x01AF, 0x01B1, 0x01B7, 0x01BB, 0x01C1, 0x01C9,
+  0x01CD, 0x01CF, 0x01D3, 0x01DF, 0x01E7, 0x01EB, 0x01F3, 0x01F7,
+  0x01FD, 0x0209, 0x020B, 0x021D, 0x0223, 0x022D, 0x0233, 0x0239,
+  0x023B, 0x0241, 0x024B, 0x0251, 0x0257, 0x0259, 0x025F, 0x0265,
+  0x0269, 0x026B, 0x0277, 0x0281, 0x0283, 0x0287, 0x028D, 0x0293,
+  0x0295, 0x02A1, 0x02A5, 0x02AB, 0x02B3, 0x02BD, 0x02C5, 0x02CF,
+
+  0x02D7, 0x02DD, 0x02E3, 0x02E7, 0x02EF, 0x02F5, 0x02F9, 0x0301,
+  0x0305, 0x0313, 0x031D, 0x0329, 0x032B, 0x0335, 0x0337, 0x033B,
+  0x033D, 0x0347, 0x0355, 0x0359, 0x035B, 0x035F, 0x036D, 0x0371,
+  0x0373, 0x0377, 0x038B, 0x038F, 0x0397, 0x03A1, 0x03A9, 0x03AD,
+  0x03B3, 0x03B9, 0x03C7, 0x03CB, 0x03D1, 0x03D7, 0x03DF, 0x03E5,
+  0x03F1, 0x03F5, 0x03FB, 0x03FD, 0x0407, 0x0409, 0x040F, 0x0419,
+  0x041B, 0x0425, 0x0427, 0x042D, 0x043F, 0x0443, 0x0445, 0x0449,
+  0x044F, 0x0455, 0x045D, 0x0463, 0x0469, 0x047F, 0x0481, 0x048B,
+
+  0x0493, 0x049D, 0x04A3, 0x04A9, 0x04B1, 0x04BD, 0x04C1, 0x04C7,
+  0x04CD, 0x04CF, 0x04D5, 0x04E1, 0x04EB, 0x04FD, 0x04FF, 0x0503,
+  0x0509, 0x050B, 0x0511, 0x0515, 0x0517, 0x051B, 0x0527, 0x0529,
+  0x052F, 0x0551, 0x0557, 0x055D, 0x0565, 0x0577, 0x0581, 0x058F,
+  0x0593, 0x0595, 0x0599, 0x059F, 0x05A7, 0x05AB, 0x05AD, 0x05B3,
+  0x05BF, 0x05C9, 0x05CB, 0x05CF, 0x05D1, 0x05D5, 0x05DB, 0x05E7,
+  0x05F3, 0x05FB, 0x0607, 0x060D, 0x0611, 0x0617, 0x061F, 0x0623,
+  0x062B, 0x062F, 0x063D, 0x0641, 0x0647, 0x0649, 0x064D, 0x0653
+#endif
+};
+
+
+/* Miller-Rabin test of "a" to the base of "b" as described in
+ * HAC pp. 139 Algorithm 4.24
+ *
+ * Sets result to 0 if definitely composite or 1 if probably prime.
+ * Randomly the chance of error is no more than 1/4 and often
+ * very much lower.
+ */
+static int mp_prime_miller_rabin (mp_int * a, mp_int * b, int *result)
+{
+  mp_int  n1, y, r;
+  int     s, j, err;
+
+  /* default */
+  *result = MP_NO;
+
+  /* ensure b > 1 */
+  if (mp_cmp_d(b, 1) != MP_GT) {
+     return MP_VAL;
+  }
+
+  /* get n1 = a - 1 */
+  if ((err = mp_init_copy (&n1, a)) != MP_OKAY) {
+    return err;
+  }
+  if ((err = mp_sub_d (&n1, 1, &n1)) != MP_OKAY) {
+    goto LBL_N1;
+  }
+
+  /* set 2**s * r = n1 */
+  if ((err = mp_init_copy (&r, &n1)) != MP_OKAY) {
+    goto LBL_N1;
+  }
+
+  /* count the number of least significant bits
+   * which are zero
+   */
+  s = mp_cnt_lsb(&r);
+
+  /* now divide n - 1 by 2**s */
+  if ((err = mp_div_2d (&r, s, &r, NULL)) != MP_OKAY) {
+    goto LBL_R;
+  }
+
+  /* compute y = b**r mod a */
+  if ((err = mp_init (&y)) != MP_OKAY) {
+    goto LBL_R;
+  }
+  if ((err = mp_exptmod (b, &r, a, &y)) != MP_OKAY) {
+    goto LBL_Y;
+  }
+
+  /* if y != 1 and y != n1 do */
+  if (mp_cmp_d (&y, 1) != MP_EQ && mp_cmp (&y, &n1) != MP_EQ) {
+    j = 1;
+    /* while j <= s-1 and y != n1 */
+    while ((j <= (s - 1)) && mp_cmp (&y, &n1) != MP_EQ) {
+      if ((err = mp_sqrmod (&y, a, &y)) != MP_OKAY) {
+         goto LBL_Y;
+      }
+
+      /* if y == 1 then composite */
+      if (mp_cmp_d (&y, 1) == MP_EQ) {
+         goto LBL_Y;
+      }
+
+      ++j;
+    }
+
+    /* if y != n1 then composite */
+    if (mp_cmp (&y, &n1) != MP_EQ) {
+      goto LBL_Y;
+    }
+  }
+
+  /* probably prime now */
+  *result = MP_YES;
+LBL_Y:mp_clear (&y);
+LBL_R:mp_clear (&r);
+LBL_N1:mp_clear (&n1);
+  return err;
+}
+
+
+/* determines if an integers is divisible by one
+ * of the first PRIME_SIZE primes or not
+ *
+ * sets result to 0 if not, 1 if yes
+ */
+static int mp_prime_is_divisible (mp_int * a, int *result)
+{
+  int     err, ix;
+  mp_digit res;
+
+  /* default to not */
+  *result = MP_NO;
+
+  for (ix = 0; ix < PRIME_SIZE; ix++) {
+    /* what is a mod LBL_prime_tab[ix] */
+    if ((err = mp_mod_d (a, ltm_prime_tab[ix], &res)) != MP_OKAY) {
+      return err;
+    }
+
+    /* is the residue zero? */
+    if (res == 0) {
+      *result = MP_YES;
+      return MP_OKAY;
+    }
+  }
+
+  return MP_OKAY;
+}
+
+
+/*
+ * Sets result to 1 if probably prime, 0 otherwise
+ */
+int mp_prime_is_prime (mp_int * a, int t, int *result)
+{
+  mp_int  b;
+  int     ix, err, res;
+
+  /* default to no */
+  *result = MP_NO;
+
+  /* valid value of t? */
+  if (t <= 0 || t > PRIME_SIZE) {
+    return MP_VAL;
+  }
+
+  /* is the input equal to one of the primes in the table? */
+  for (ix = 0; ix < PRIME_SIZE; ix++) {
+      if (mp_cmp_d(a, ltm_prime_tab[ix]) == MP_EQ) {
+         *result = 1;
+         return MP_OKAY;
+      }
+  }
+
+  /* first perform trial division */
+  if ((err = mp_prime_is_divisible (a, &res)) != MP_OKAY) {
+    return err;
+  }
+
+  /* return if it was trivially divisible */
+  if (res == MP_YES) {
+    return MP_OKAY;
+  }
+
+  /* now perform the miller-rabin rounds */
+  if ((err = mp_init (&b)) != MP_OKAY) {
+    return err;
+  }
+
+  for (ix = 0; ix < t; ix++) {
+    /* set the prime */
+    mp_set (&b, ltm_prime_tab[ix]);
+
+    if ((err = mp_prime_miller_rabin (a, &b, &res)) != MP_OKAY) {
+      goto LBL_B;
+    }
+
+    if (res == MP_NO) {
+      goto LBL_B;
+    }
+  }
+
+  /* passed the test */
+  *result = MP_YES;
+LBL_B:mp_clear (&b);
+  return err;
+}
+
+
+/* computes least common multiple as |a*b|/(a, b) */
+int mp_lcm (mp_int * a, mp_int * b, mp_int * c)
+{
+  int     res;
+  mp_int  t1, t2;
+
+
+  if ((res = mp_init_multi (&t1, &t2, NULL, NULL, NULL, NULL)) != MP_OKAY) {
+    return res;
+  }
+
+  /* t1 = get the GCD of the two inputs */
+  if ((res = mp_gcd (a, b, &t1)) != MP_OKAY) {
+    goto LBL_T;
+  }
+
+  /* divide the smallest by the GCD */
+  if (mp_cmp_mag(a, b) == MP_LT) {
+     /* store quotient in t2 such that t2 * b is the LCM */
+     if ((res = mp_div(a, &t1, &t2, NULL)) != MP_OKAY) {
+        goto LBL_T;
+     }
+     res = mp_mul(b, &t2, c);
+  } else {
+     /* store quotient in t2 such that t2 * a is the LCM */
+     if ((res = mp_div(b, &t1, &t2, NULL)) != MP_OKAY) {
+        goto LBL_T;
+     }
+     res = mp_mul(a, &t2, c);
+  }
+
+  /* fix the sign to positive */
+  c->sign = MP_ZPOS;
+
+LBL_T:
+  mp_clear(&t1);
+  mp_clear(&t2);
+  return res;
+}
+
+
+
+/* Greatest Common Divisor using the binary method */
+int mp_gcd (mp_int * a, mp_int * b, mp_int * c)
+{
+    mp_int  u, v;
+    int     k, u_lsb, v_lsb, res;
+
+    /* either zero than gcd is the largest */
+    if (mp_iszero (a) == MP_YES) {
+        return mp_abs (b, c);
+    }
+    if (mp_iszero (b) == MP_YES) {
+        return mp_abs (a, c);
+    }
+
+    /* get copies of a and b we can modify */
+    if ((res = mp_init_copy (&u, a)) != MP_OKAY) {
+        return res;
+    }
+
+    if ((res = mp_init_copy (&v, b)) != MP_OKAY) {
+        goto LBL_U;
+    }
+
+    /* must be positive for the remainder of the algorithm */
+    u.sign = v.sign = MP_ZPOS;
+
+    /* B1.  Find the common power of two for u and v */
+    u_lsb = mp_cnt_lsb(&u);
+    v_lsb = mp_cnt_lsb(&v);
+    k     = MIN(u_lsb, v_lsb);
+
+    if (k > 0) {
+        /* divide the power of two out */
+        if ((res = mp_div_2d(&u, k, &u, NULL)) != MP_OKAY) {
+            goto LBL_V;
+        }
+
+        if ((res = mp_div_2d(&v, k, &v, NULL)) != MP_OKAY) {
+            goto LBL_V;
+        }
+    }
+
+    /* divide any remaining factors of two out */
+    if (u_lsb != k) {
+        if ((res = mp_div_2d(&u, u_lsb - k, &u, NULL)) != MP_OKAY) {
+            goto LBL_V;
+        }
+    }
+
+    if (v_lsb != k) {
+        if ((res = mp_div_2d(&v, v_lsb - k, &v, NULL)) != MP_OKAY) {
+            goto LBL_V;
+        }
+    }
+
+    while (mp_iszero(&v) == 0) {
+        /* make sure v is the largest */
+        if (mp_cmp_mag(&u, &v) == MP_GT) {
+            /* swap u and v to make sure v is >= u */
+            mp_exch(&u, &v);
+        }
+
+        /* subtract smallest from largest */
+        if ((res = s_mp_sub(&v, &u, &v)) != MP_OKAY) {
+            goto LBL_V;
+        }
+
+        /* Divide out all factors of two */
+        if ((res = mp_div_2d(&v, mp_cnt_lsb(&v), &v, NULL)) != MP_OKAY) {
+            goto LBL_V;
+        }
+    }
+
+    /* multiply by 2**k which we divided out at the beginning */
+    if ((res = mp_mul_2d (&u, k, c)) != MP_OKAY) {
+        goto LBL_V;
+    }
+    c->sign = MP_ZPOS;
+    res = MP_OKAY;
+LBL_V:mp_clear (&u);
+LBL_U:mp_clear (&v);
+    return res;
+}
+
+
+
+#endif /* WOLFSSL_KEY_GEN */
+
+
+#ifdef HAVE_ECC
+
+/* chars used in radix conversions */
+const char *mp_s_rmap = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz+/";
+
+/* read a string [ASCII] in a given radix */
+int mp_read_radix (mp_int * a, const char *str, int radix)
+{
+  int     y, res, neg;
+  char    ch;
+
+  /* zero the digit bignum */
+  mp_zero(a);
+
+  /* make sure the radix is ok */
+  if (radix < 2 || radix > 64) {
+    return MP_VAL;
+  }
+
+  /* if the leading digit is a
+   * minus set the sign to negative.
+   */
+  if (*str == '-') {
+    ++str;
+    neg = MP_NEG;
+  } else {
+    neg = MP_ZPOS;
+  }
+
+  /* set the integer to the default of zero */
+  mp_zero (a);
+
+  /* process each digit of the string */
+  while (*str) {
+    /* if the radix < 36 the conversion is case insensitive
+     * this allows numbers like 1AB and 1ab to represent the same  value
+     * [e.g. in hex]
+     */
+    ch = (char) ((radix < 36) ? XTOUPPER((unsigned char)*str) : *str);
+    for (y = 0; y < 64; y++) {
+      if (ch == mp_s_rmap[y]) {
+         break;
+      }
+    }
+
+    /* if the char was found in the map
+     * and is less than the given radix add it
+     * to the number, otherwise exit the loop.
+     */
+    if (y < radix) {
+      if ((res = mp_mul_d (a, (mp_digit) radix, a)) != MP_OKAY) {
+         return res;
+      }
+      if ((res = mp_add_d (a, (mp_digit) y, a)) != MP_OKAY) {
+         return res;
+      }
+    } else {
+      break;
+    }
+    ++str;
+  }
+
+  /* set the sign only if a != 0 */
+  if (mp_iszero(a) != 1) {
+     a->sign = neg;
+  }
+  return MP_OKAY;
+}
+
+#endif /* HAVE_ECC */
+
+#endif /* USE_FAST_MATH */
+
+#endif /* NO_BIG_INT */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/logging.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/logging.c
new file mode 100644
index 0000000..3215306
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/logging.c
@@ -0,0 +1,162 @@
+/* logging.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+/* submitted by eof */
+
+#include 
+#include 
+
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+    WOLFSSL_API int  wolfSSL_Debugging_ON(void);
+    WOLFSSL_API void wolfSSL_Debugging_OFF(void);
+#ifdef __cplusplus
+    } 
+#endif
+
+
+#ifdef DEBUG_WOLFSSL
+
+/* Set these to default values initially. */
+static wolfSSL_Logging_cb log_function = 0;
+static int loggingEnabled = 0;
+
+#endif /* DEBUG_WOLFSSL */
+
+
+int wolfSSL_SetLoggingCb(wolfSSL_Logging_cb f)
+{
+#ifdef DEBUG_WOLFSSL
+    int res = 0;
+
+    if (f)
+        log_function = f;
+    else
+        res = BAD_FUNC_ARG;
+
+    return res;
+#else
+    (void)f;
+    return NOT_COMPILED_IN;
+#endif
+}
+
+
+int wolfSSL_Debugging_ON(void)
+{
+#ifdef DEBUG_WOLFSSL
+    loggingEnabled = 1;
+    return 0;
+#else
+    return NOT_COMPILED_IN;
+#endif
+}
+
+
+void wolfSSL_Debugging_OFF(void)
+{
+#ifdef DEBUG_WOLFSSL
+    loggingEnabled = 0;
+#endif
+}
+
+
+#ifdef DEBUG_WOLFSSL
+
+#ifdef FREESCALE_MQX
+    #include 
+#else
+    #include    /* for default printf stuff */
+#endif
+
+#ifdef THREADX
+    int dc_log_printf(char*, ...);
+#endif
+
+static void wolfssl_log(const int logLevel, const char *const logMessage)
+{
+    if (log_function)
+        log_function(logLevel, logMessage);
+    else {
+        if (loggingEnabled) {
+#ifdef THREADX
+            dc_log_printf("%s\n", logMessage);
+#elif defined(MICRIUM)
+        #if (NET_SECURE_MGR_CFG_EN == DEF_ENABLED)
+            NetSecure_TraceOut((CPU_CHAR *)logMessage);
+        #endif
+#elif defined(WOLFSSL_MDK_ARM)
+            fflush(stdout) ;
+            printf("%s\n", logMessage);
+            fflush(stdout) ;
+#else
+            fprintf(stderr, "%s\n", logMessage);
+#endif
+        }
+    }
+}
+
+
+void WOLFSSL_MSG(const char* msg)
+{
+    if (loggingEnabled)
+        wolfssl_log(INFO_LOG , msg);
+}
+
+
+void WOLFSSL_ENTER(const char* msg)
+{
+    if (loggingEnabled) {
+        char buffer[80];
+        sprintf(buffer, "wolfSSL Entering %s", msg);
+        wolfssl_log(ENTER_LOG , buffer);
+    }
+}
+
+
+void WOLFSSL_LEAVE(const char* msg, int ret)
+{
+    if (loggingEnabled) {
+        char buffer[80];
+        sprintf(buffer, "wolfSSL Leaving %s, return %d", msg, ret);
+        wolfssl_log(LEAVE_LOG , buffer);
+    }
+}
+
+
+void WOLFSSL_ERROR(int error)
+{
+    if (loggingEnabled) {
+        char buffer[80];
+        sprintf(buffer, "wolfSSL error occured, error = %d", error);
+        wolfssl_log(ERROR_LOG , buffer);
+    }
+}
+
+#endif  /* DEBUG_WOLFSSL */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/md2.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/md2.c
new file mode 100644
index 0000000..ce4e424
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/md2.c
@@ -0,0 +1,160 @@
+/* md2.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifdef WOLFSSL_MD2
+
+#include 
+#include 
+
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+
+void wc_InitMd2(Md2* md2)
+{
+    XMEMSET(md2->X, 0, MD2_X_SIZE);
+    XMEMSET(md2->C, 0, MD2_BLOCK_SIZE);
+    XMEMSET(md2->buffer, 0, MD2_BLOCK_SIZE);
+    md2->count = 0;
+}
+
+
+void wc_Md2Update(Md2* md2, const byte* data, word32 len)
+{
+    static const byte S[256] = 
+    {
+        41, 46, 67, 201, 162, 216, 124, 1, 61, 54, 84, 161, 236, 240, 6,
+        19, 98, 167, 5, 243, 192, 199, 115, 140, 152, 147, 43, 217, 188,
+        76, 130, 202, 30, 155, 87, 60, 253, 212, 224, 22, 103, 66, 111, 24,
+        138, 23, 229, 18, 190, 78, 196, 214, 218, 158, 222, 73, 160, 251,
+        245, 142, 187, 47, 238, 122, 169, 104, 121, 145, 21, 178, 7, 63,
+        148, 194, 16, 137, 11, 34, 95, 33, 128, 127, 93, 154, 90, 144, 50,
+        39, 53, 62, 204, 231, 191, 247, 151, 3, 255, 25, 48, 179, 72, 165,
+        181, 209, 215, 94, 146, 42, 172, 86, 170, 198, 79, 184, 56, 210,
+        150, 164, 125, 182, 118, 252, 107, 226, 156, 116, 4, 241, 69, 157,
+        112, 89, 100, 113, 135, 32, 134, 91, 207, 101, 230, 45, 168, 2, 27,
+        96, 37, 173, 174, 176, 185, 246, 28, 70, 97, 105, 52, 64, 126, 15,
+        85, 71, 163, 35, 221, 81, 175, 58, 195, 92, 249, 206, 186, 197,
+        234, 38, 44, 83, 13, 110, 133, 40, 132, 9, 211, 223, 205, 244, 65,
+        129, 77, 82, 106, 220, 55, 200, 108, 193, 171, 250, 36, 225, 123,
+        8, 12, 189, 177, 74, 120, 136, 149, 139, 227, 99, 232, 109, 233,
+        203, 213, 254, 59, 0, 29, 57, 242, 239, 183, 14, 102, 88, 208, 228,
+        166, 119, 114, 248, 235, 117, 75, 10, 49, 68, 80, 180, 143, 237,
+        31, 26, 219, 153, 141, 51, 159, 17, 131, 20
+    };
+
+    while (len) {
+        word32 L = (MD2_PAD_SIZE - md2->count) < len ?
+                   (MD2_PAD_SIZE - md2->count) : len;
+        XMEMCPY(md2->buffer + md2->count, data, L);
+        md2->count += L;
+        data += L;
+        len  -= L;
+
+        if (md2->count == MD2_PAD_SIZE) {
+            int  i;
+            byte t;
+
+            md2->count = 0;
+            XMEMCPY(md2->X + MD2_PAD_SIZE, md2->buffer, MD2_PAD_SIZE);
+            t = md2->C[15];
+
+            for(i = 0; i < MD2_PAD_SIZE; i++) {
+                md2->X[32 + i] = md2->X[MD2_PAD_SIZE + i] ^ md2->X[i];
+                t = md2->C[i] ^= S[md2->buffer[i] ^ t];
+            }
+
+            t=0;
+            for(i = 0; i < 18; i++) {
+                int j;
+                for(j = 0; j < MD2_X_SIZE; j += 8) {
+                    t = md2->X[j+0] ^= S[t];
+                    t = md2->X[j+1] ^= S[t];
+                    t = md2->X[j+2] ^= S[t];
+                    t = md2->X[j+3] ^= S[t];
+                    t = md2->X[j+4] ^= S[t];
+                    t = md2->X[j+5] ^= S[t];
+                    t = md2->X[j+6] ^= S[t];
+                    t = md2->X[j+7] ^= S[t];
+                }
+                t = (t + i) & 0xFF;
+            }
+        }
+    }
+}
+
+
+void wc_Md2Final(Md2* md2, byte* hash)
+{
+    byte   padding[MD2_BLOCK_SIZE];
+    word32 padLen = MD2_PAD_SIZE - md2->count;
+    word32 i;
+
+    for (i = 0; i < padLen; i++)
+        padding[i] = (byte)padLen;
+
+    wc_Md2Update(md2, padding, padLen);
+    wc_Md2Update(md2, md2->C, MD2_BLOCK_SIZE);
+
+    XMEMCPY(hash, md2->X, MD2_DIGEST_SIZE);
+
+    wc_InitMd2(md2);
+}
+
+
+int wc_Md2Hash(const byte* data, word32 len, byte* hash)
+{
+#ifdef WOLFSSL_SMALL_STACK
+    Md2* md2;
+#else
+    Md2 md2[1];
+#endif
+
+#ifdef WOLFSSL_SMALL_STACK
+    md2 = (Md2*)XMALLOC(sizeof(Md2), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (md2 == NULL)
+        return MEMORY_E;
+#endif
+
+    wc_InitMd2(md2);
+    wc_Md2Update(md2, data, len);
+    wc_Md2Final(md2, hash);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(md2, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return 0;
+}
+
+
+#endif /* WOLFSSL_MD2 */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/md4.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/md4.c
new file mode 100644
index 0000000..c428610
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/md4.c
@@ -0,0 +1,220 @@
+/* md4.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifndef NO_MD4
+
+#include 
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+
+#ifndef WOLFSSL_HAVE_MIN
+#define WOLFSSL_HAVE_MIN
+
+    static INLINE word32 min(word32 a, word32 b)
+    {
+        return a > b ? b : a;
+    }
+
+#endif /* WOLFSSL_HAVE_MIN */
+
+
+void wc_InitMd4(Md4* md4)
+{
+    md4->digest[0] = 0x67452301L;
+    md4->digest[1] = 0xefcdab89L;
+    md4->digest[2] = 0x98badcfeL;
+    md4->digest[3] = 0x10325476L;
+
+    md4->buffLen = 0;
+    md4->loLen   = 0;
+    md4->hiLen   = 0;
+}
+
+
+static void Transform(Md4* md4)
+{
+#define F(x, y, z) ((z) ^ ((x) & ((y) ^ (z))))
+#define G(x, y, z) (((x) & (y)) | ((x) & (z)) | ((y) & (z)))
+#define H(x, y, z) ((x) ^ (y) ^ (z))
+
+    /* Copy context->state[] to working vars  */
+    word32 A = md4->digest[0];
+    word32 B = md4->digest[1];
+    word32 C = md4->digest[2];
+    word32 D = md4->digest[3];
+
+#define function(a,b,c,d,k,s) a=rotlFixed(a+F(b,c,d)+md4->buffer[k],s);
+    function(A,B,C,D, 0, 3);
+    function(D,A,B,C, 1, 7);
+    function(C,D,A,B, 2,11);
+    function(B,C,D,A, 3,19);
+    function(A,B,C,D, 4, 3);
+    function(D,A,B,C, 5, 7);
+    function(C,D,A,B, 6,11);
+    function(B,C,D,A, 7,19);
+    function(A,B,C,D, 8, 3);
+    function(D,A,B,C, 9, 7);
+    function(C,D,A,B,10,11);
+    function(B,C,D,A,11,19);
+    function(A,B,C,D,12, 3);
+    function(D,A,B,C,13, 7);
+    function(C,D,A,B,14,11);
+    function(B,C,D,A,15,19);
+
+#undef function	  
+#define function(a,b,c,d,k,s) \
+    a=rotlFixed(a+G(b,c,d)+md4->buffer[k]+0x5a827999,s);
+
+    function(A,B,C,D, 0, 3);
+    function(D,A,B,C, 4, 5);
+    function(C,D,A,B, 8, 9);
+    function(B,C,D,A,12,13);
+    function(A,B,C,D, 1, 3);
+    function(D,A,B,C, 5, 5);
+    function(C,D,A,B, 9, 9);
+    function(B,C,D,A,13,13);
+    function(A,B,C,D, 2, 3);
+    function(D,A,B,C, 6, 5);
+    function(C,D,A,B,10, 9);
+    function(B,C,D,A,14,13);
+    function(A,B,C,D, 3, 3);
+    function(D,A,B,C, 7, 5);
+    function(C,D,A,B,11, 9);
+    function(B,C,D,A,15,13);
+
+#undef function	 
+#define function(a,b,c,d,k,s) \
+    a=rotlFixed(a+H(b,c,d)+md4->buffer[k]+0x6ed9eba1,s);
+
+    function(A,B,C,D, 0, 3);
+    function(D,A,B,C, 8, 9);
+    function(C,D,A,B, 4,11);
+    function(B,C,D,A,12,15);
+    function(A,B,C,D, 2, 3);
+    function(D,A,B,C,10, 9);
+    function(C,D,A,B, 6,11);
+    function(B,C,D,A,14,15);
+    function(A,B,C,D, 1, 3);
+    function(D,A,B,C, 9, 9);
+    function(C,D,A,B, 5,11);
+    function(B,C,D,A,13,15);
+    function(A,B,C,D, 3, 3);
+    function(D,A,B,C,11, 9);
+    function(C,D,A,B, 7,11);
+    function(B,C,D,A,15,15);
+    
+    /* Add the working vars back into digest state[]  */
+    md4->digest[0] += A;
+    md4->digest[1] += B;
+    md4->digest[2] += C;
+    md4->digest[3] += D;
+}
+
+
+static INLINE void AddLength(Md4* md4, word32 len)
+{
+    word32 tmp = md4->loLen;
+    if ( (md4->loLen += len) < tmp)
+        md4->hiLen++;                       /* carry low to high */
+}
+
+
+void wc_Md4Update(Md4* md4, const byte* data, word32 len)
+{
+    /* do block size increments */
+    byte* local = (byte*)md4->buffer;
+
+    while (len) {
+        word32 add = min(len, MD4_BLOCK_SIZE - md4->buffLen);
+        XMEMCPY(&local[md4->buffLen], data, add);
+
+        md4->buffLen += add;
+        data         += add;
+        len          -= add;
+
+        if (md4->buffLen == MD4_BLOCK_SIZE) {
+            #ifdef BIG_ENDIAN_ORDER
+                ByteReverseWords(md4->buffer, md4->buffer, MD4_BLOCK_SIZE);
+            #endif
+            Transform(md4);
+            AddLength(md4, MD4_BLOCK_SIZE);
+            md4->buffLen = 0;
+        }
+    }
+}
+
+
+void wc_Md4Final(Md4* md4, byte* hash)
+{
+    byte* local = (byte*)md4->buffer;
+
+    AddLength(md4, md4->buffLen);               /* before adding pads */
+
+    local[md4->buffLen++] = 0x80;  /* add 1 */
+
+    /* pad with zeros */
+    if (md4->buffLen > MD4_PAD_SIZE) {
+        XMEMSET(&local[md4->buffLen], 0, MD4_BLOCK_SIZE - md4->buffLen);
+        md4->buffLen += MD4_BLOCK_SIZE - md4->buffLen;
+
+        #ifdef BIG_ENDIAN_ORDER
+            ByteReverseWords(md4->buffer, md4->buffer, MD4_BLOCK_SIZE);
+        #endif
+        Transform(md4);
+        md4->buffLen = 0;
+    }
+    XMEMSET(&local[md4->buffLen], 0, MD4_PAD_SIZE - md4->buffLen);
+   
+    /* put lengths in bits */
+    md4->hiLen = (md4->loLen >> (8*sizeof(md4->loLen) - 3)) + 
+                 (md4->hiLen << 3);
+    md4->loLen = md4->loLen << 3;
+
+    /* store lengths */
+    #ifdef BIG_ENDIAN_ORDER
+        ByteReverseWords(md4->buffer, md4->buffer, MD4_BLOCK_SIZE);
+    #endif
+    /* ! length ordering dependent on digest endian type ! */
+    XMEMCPY(&local[MD4_PAD_SIZE], &md4->loLen, sizeof(word32));
+    XMEMCPY(&local[MD4_PAD_SIZE + sizeof(word32)], &md4->hiLen, sizeof(word32));
+
+    Transform(md4);
+    #ifdef BIG_ENDIAN_ORDER
+        ByteReverseWords(md4->digest, md4->digest, MD4_DIGEST_SIZE);
+    #endif
+    XMEMCPY(hash, md4->digest, MD4_DIGEST_SIZE);
+
+    wc_InitMd4(md4);  /* reset state */
+}
+
+
+#endif /* NO_MD4 */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/md5.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/md5.c
new file mode 100644
index 0000000..fbf732a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/md5.c
@@ -0,0 +1,397 @@
+/* md5.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#if !defined(NO_MD5)
+
+#if defined(WOLFSSL_TI_HASH)
+    /* #include  included by wc_port.c */
+#else
+
+#ifdef WOLFSSL_PIC32MZ_HASH
+#define wc_InitMd5   wc_InitMd5_sw
+#define wc_Md5Update wc_Md5Update_sw
+#define wc_Md5Final  wc_Md5Final_sw
+#endif
+
+#include 
+#include 
+
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+#ifdef FREESCALE_MMCAU
+    #include "cau_api.h"
+    #define XTRANSFORM(S,B)  cau_md5_hash_n((B), 1, (unsigned char*)(S)->digest)
+#else
+    #define XTRANSFORM(S,B)  Transform((S))
+#endif
+
+
+#ifdef STM32F2_HASH
+    /*
+     * STM32F2 hardware MD5 support through the STM32F2 standard peripheral
+     * library. Documentation located in STM32F2xx Standard Peripheral Library
+     * document (See note in README).
+     */
+    #include "stm32f2xx.h"
+
+    void wc_InitMd5(Md5* md5)
+    {
+        /* STM32F2 struct notes:
+         * md5->buffer  = first 4 bytes used to hold partial block if needed 
+         * md5->buffLen = num bytes currently stored in md5->buffer
+         * md5->loLen   = num bytes that have been written to STM32 FIFO
+         */
+        XMEMSET(md5->buffer, 0, MD5_REG_SIZE);
+			
+        md5->buffLen = 0;
+        md5->loLen = 0;
+
+        /* initialize HASH peripheral */
+        HASH_DeInit();
+
+        /* configure algo used, algo mode, datatype */
+        HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE);
+        HASH->CR |= (HASH_AlgoSelection_MD5 | HASH_AlgoMode_HASH 
+                 | HASH_DataType_8b);
+
+        /* reset HASH processor */
+        HASH->CR |= HASH_CR_INIT;
+    }
+
+    void wc_Md5Update(Md5* md5, const byte* data, word32 len)
+    {
+        word32 i = 0;
+        word32 fill = 0;
+        word32 diff = 0;
+
+        /* if saved partial block is available */
+        if (md5->buffLen > 0) {
+            fill = 4 - md5->buffLen;
+
+            /* if enough data to fill, fill and push to FIFO */
+            if (fill <= len) {
+                XMEMCPY((byte*)md5->buffer + md5->buffLen, data, fill);
+                HASH_DataIn(*(uint32_t*)md5->buffer);
+
+                data += fill;
+                len -= fill;
+                md5->loLen += 4;
+                md5->buffLen = 0;
+            } else {
+                /* append partial to existing stored block */
+                XMEMCPY((byte*)md5->buffer + md5->buffLen, data, len);
+                md5->buffLen += len;
+                return;
+            }
+        }
+
+        /* write input block in the IN FIFO */
+        for (i = 0; i < len; i += 4)
+        {
+            diff = len - i;
+            if (diff < 4) {
+                /* store incomplete last block, not yet in FIFO */
+                XMEMSET(md5->buffer, 0, MD5_REG_SIZE);
+                XMEMCPY((byte*)md5->buffer, data, diff);
+                md5->buffLen = diff;
+            } else {
+                HASH_DataIn(*(uint32_t*)data);
+                data+=4;
+            }
+        }
+
+        /* keep track of total data length thus far */
+        md5->loLen += (len - md5->buffLen);
+    }
+
+    void wc_Md5Final(Md5* md5, byte* hash)
+    {
+        __IO uint16_t nbvalidbitsdata = 0;
+
+        /* finish reading any trailing bytes into FIFO */
+        if (md5->buffLen > 0) {
+            HASH_DataIn(*(uint32_t*)md5->buffer);
+            md5->loLen += md5->buffLen;
+        }
+
+        /* calculate number of valid bits in last word of input data */
+        nbvalidbitsdata = 8 * (md5->loLen % MD5_REG_SIZE);
+
+        /* configure number of valid bits in last word of the data */
+        HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
+
+        /* start HASH processor */
+        HASH_StartDigest();
+
+        /* wait until Busy flag == RESET */
+        while (HASH_GetFlagStatus(HASH_FLAG_BUSY) != RESET) {}
+        
+        /* read message digest */
+        md5->digest[0] = HASH->HR[0];
+        md5->digest[1] = HASH->HR[1];
+        md5->digest[2] = HASH->HR[2];
+        md5->digest[3] = HASH->HR[3];
+
+        ByteReverseWords(md5->digest, md5->digest, MD5_DIGEST_SIZE);
+
+        XMEMCPY(hash, md5->digest, MD5_DIGEST_SIZE);
+
+        wc_InitMd5(md5);  /* reset state */
+    }
+
+#else /* CTaoCrypt software implementation */
+
+#ifndef WOLFSSL_HAVE_MIN
+#define WOLFSSL_HAVE_MIN
+
+    static INLINE word32 min(word32 a, word32 b)
+    {
+        return a > b ? b : a;
+    }
+
+#endif /* WOLFSSL_HAVE_MIN */
+
+void wc_InitMd5(Md5* md5)
+{
+    md5->digest[0] = 0x67452301L;
+    md5->digest[1] = 0xefcdab89L;
+    md5->digest[2] = 0x98badcfeL;
+    md5->digest[3] = 0x10325476L;
+
+    md5->buffLen = 0;
+    md5->loLen   = 0;
+    md5->hiLen   = 0;
+}
+
+#ifndef FREESCALE_MMCAU
+
+static void Transform(Md5* md5)
+{
+#define F1(x, y, z) (z ^ (x & (y ^ z)))
+#define F2(x, y, z) F1(z, x, y)
+#define F3(x, y, z) (x ^ y ^ z)
+#define F4(x, y, z) (y ^ (x | ~z))
+
+#define MD5STEP(f, w, x, y, z, data, s) \
+    w = rotlFixed(w + f(x, y, z) + data, s) + x
+
+    /* Copy context->state[] to working vars  */
+    word32 a = md5->digest[0];
+    word32 b = md5->digest[1];
+    word32 c = md5->digest[2];
+    word32 d = md5->digest[3];
+
+    MD5STEP(F1, a, b, c, d, md5->buffer[0]  + 0xd76aa478,  7);
+    MD5STEP(F1, d, a, b, c, md5->buffer[1]  + 0xe8c7b756, 12);
+    MD5STEP(F1, c, d, a, b, md5->buffer[2]  + 0x242070db, 17);
+    MD5STEP(F1, b, c, d, a, md5->buffer[3]  + 0xc1bdceee, 22);
+    MD5STEP(F1, a, b, c, d, md5->buffer[4]  + 0xf57c0faf,  7);
+    MD5STEP(F1, d, a, b, c, md5->buffer[5]  + 0x4787c62a, 12);
+    MD5STEP(F1, c, d, a, b, md5->buffer[6]  + 0xa8304613, 17);
+    MD5STEP(F1, b, c, d, a, md5->buffer[7]  + 0xfd469501, 22);
+    MD5STEP(F1, a, b, c, d, md5->buffer[8]  + 0x698098d8,  7);
+    MD5STEP(F1, d, a, b, c, md5->buffer[9]  + 0x8b44f7af, 12);
+    MD5STEP(F1, c, d, a, b, md5->buffer[10] + 0xffff5bb1, 17);
+    MD5STEP(F1, b, c, d, a, md5->buffer[11] + 0x895cd7be, 22);
+    MD5STEP(F1, a, b, c, d, md5->buffer[12] + 0x6b901122,  7);
+    MD5STEP(F1, d, a, b, c, md5->buffer[13] + 0xfd987193, 12);
+    MD5STEP(F1, c, d, a, b, md5->buffer[14] + 0xa679438e, 17);
+    MD5STEP(F1, b, c, d, a, md5->buffer[15] + 0x49b40821, 22);
+
+    MD5STEP(F2, a, b, c, d, md5->buffer[1]  + 0xf61e2562,  5);
+    MD5STEP(F2, d, a, b, c, md5->buffer[6]  + 0xc040b340,  9);
+    MD5STEP(F2, c, d, a, b, md5->buffer[11] + 0x265e5a51, 14);
+    MD5STEP(F2, b, c, d, a, md5->buffer[0]  + 0xe9b6c7aa, 20);
+    MD5STEP(F2, a, b, c, d, md5->buffer[5]  + 0xd62f105d,  5);
+    MD5STEP(F2, d, a, b, c, md5->buffer[10] + 0x02441453,  9);
+    MD5STEP(F2, c, d, a, b, md5->buffer[15] + 0xd8a1e681, 14);
+    MD5STEP(F2, b, c, d, a, md5->buffer[4]  + 0xe7d3fbc8, 20);
+    MD5STEP(F2, a, b, c, d, md5->buffer[9]  + 0x21e1cde6,  5);
+    MD5STEP(F2, d, a, b, c, md5->buffer[14] + 0xc33707d6,  9);
+    MD5STEP(F2, c, d, a, b, md5->buffer[3]  + 0xf4d50d87, 14);
+    MD5STEP(F2, b, c, d, a, md5->buffer[8]  + 0x455a14ed, 20);
+    MD5STEP(F2, a, b, c, d, md5->buffer[13] + 0xa9e3e905,  5);
+    MD5STEP(F2, d, a, b, c, md5->buffer[2]  + 0xfcefa3f8,  9);
+    MD5STEP(F2, c, d, a, b, md5->buffer[7]  + 0x676f02d9, 14);
+    MD5STEP(F2, b, c, d, a, md5->buffer[12] + 0x8d2a4c8a, 20);
+
+    MD5STEP(F3, a, b, c, d, md5->buffer[5]  + 0xfffa3942,  4);
+    MD5STEP(F3, d, a, b, c, md5->buffer[8]  + 0x8771f681, 11);
+    MD5STEP(F3, c, d, a, b, md5->buffer[11] + 0x6d9d6122, 16);
+    MD5STEP(F3, b, c, d, a, md5->buffer[14] + 0xfde5380c, 23);
+    MD5STEP(F3, a, b, c, d, md5->buffer[1]  + 0xa4beea44,  4);
+    MD5STEP(F3, d, a, b, c, md5->buffer[4]  + 0x4bdecfa9, 11);
+    MD5STEP(F3, c, d, a, b, md5->buffer[7]  + 0xf6bb4b60, 16);
+    MD5STEP(F3, b, c, d, a, md5->buffer[10] + 0xbebfbc70, 23);
+    MD5STEP(F3, a, b, c, d, md5->buffer[13] + 0x289b7ec6,  4);
+    MD5STEP(F3, d, a, b, c, md5->buffer[0]  + 0xeaa127fa, 11);
+    MD5STEP(F3, c, d, a, b, md5->buffer[3]  + 0xd4ef3085, 16);
+    MD5STEP(F3, b, c, d, a, md5->buffer[6]  + 0x04881d05, 23);
+    MD5STEP(F3, a, b, c, d, md5->buffer[9]  + 0xd9d4d039,  4);
+    MD5STEP(F3, d, a, b, c, md5->buffer[12] + 0xe6db99e5, 11);
+    MD5STEP(F3, c, d, a, b, md5->buffer[15] + 0x1fa27cf8, 16);
+    MD5STEP(F3, b, c, d, a, md5->buffer[2]  + 0xc4ac5665, 23);
+
+    MD5STEP(F4, a, b, c, d, md5->buffer[0]  + 0xf4292244,  6);
+    MD5STEP(F4, d, a, b, c, md5->buffer[7]  + 0x432aff97, 10);
+    MD5STEP(F4, c, d, a, b, md5->buffer[14] + 0xab9423a7, 15);
+    MD5STEP(F4, b, c, d, a, md5->buffer[5]  + 0xfc93a039, 21);
+    MD5STEP(F4, a, b, c, d, md5->buffer[12] + 0x655b59c3,  6);
+    MD5STEP(F4, d, a, b, c, md5->buffer[3]  + 0x8f0ccc92, 10);
+    MD5STEP(F4, c, d, a, b, md5->buffer[10] + 0xffeff47d, 15);
+    MD5STEP(F4, b, c, d, a, md5->buffer[1]  + 0x85845dd1, 21);
+    MD5STEP(F4, a, b, c, d, md5->buffer[8]  + 0x6fa87e4f,  6);
+    MD5STEP(F4, d, a, b, c, md5->buffer[15] + 0xfe2ce6e0, 10);
+    MD5STEP(F4, c, d, a, b, md5->buffer[6]  + 0xa3014314, 15);
+    MD5STEP(F4, b, c, d, a, md5->buffer[13] + 0x4e0811a1, 21);
+    MD5STEP(F4, a, b, c, d, md5->buffer[4]  + 0xf7537e82,  6);
+    MD5STEP(F4, d, a, b, c, md5->buffer[11] + 0xbd3af235, 10);
+    MD5STEP(F4, c, d, a, b, md5->buffer[2]  + 0x2ad7d2bb, 15);
+    MD5STEP(F4, b, c, d, a, md5->buffer[9]  + 0xeb86d391, 21);
+    
+    /* Add the working vars back into digest state[]  */
+    md5->digest[0] += a;
+    md5->digest[1] += b;
+    md5->digest[2] += c;
+    md5->digest[3] += d;
+}
+
+#endif /* FREESCALE_MMCAU */
+
+
+static INLINE void AddLength(Md5* md5, word32 len)
+{
+    word32 tmp = md5->loLen;
+    if ( (md5->loLen += len) < tmp)
+        md5->hiLen++;                       /* carry low to high */
+}
+
+
+void wc_Md5Update(Md5* md5, const byte* data, word32 len)
+{
+    /* do block size increments */
+    byte* local = (byte*)md5->buffer;
+
+    while (len) {
+        word32 add = min(len, MD5_BLOCK_SIZE - md5->buffLen);
+        XMEMCPY(&local[md5->buffLen], data, add);
+
+        md5->buffLen += add;
+        data         += add;
+        len          -= add;
+
+        if (md5->buffLen == MD5_BLOCK_SIZE) {
+            #if defined(BIG_ENDIAN_ORDER) && !defined(FREESCALE_MMCAU)
+                ByteReverseWords(md5->buffer, md5->buffer, MD5_BLOCK_SIZE);
+            #endif
+            XTRANSFORM(md5, local);
+            AddLength(md5, MD5_BLOCK_SIZE);
+            md5->buffLen = 0;
+        }
+    }
+}
+
+
+void wc_Md5Final(Md5* md5, byte* hash)
+{
+    byte* local = (byte*)md5->buffer;
+
+    AddLength(md5, md5->buffLen);  /* before adding pads */
+
+    local[md5->buffLen++] = 0x80;  /* add 1 */
+
+    /* pad with zeros */
+    if (md5->buffLen > MD5_PAD_SIZE) {
+        XMEMSET(&local[md5->buffLen], 0, MD5_BLOCK_SIZE - md5->buffLen);
+        md5->buffLen += MD5_BLOCK_SIZE - md5->buffLen;
+
+        #if defined(BIG_ENDIAN_ORDER) && !defined(FREESCALE_MMCAU)
+            ByteReverseWords(md5->buffer, md5->buffer, MD5_BLOCK_SIZE);
+        #endif
+        XTRANSFORM(md5, local);
+        md5->buffLen = 0;
+    }
+    XMEMSET(&local[md5->buffLen], 0, MD5_PAD_SIZE - md5->buffLen);
+   
+    /* put lengths in bits */
+    md5->hiLen = (md5->loLen >> (8*sizeof(md5->loLen) - 3)) + 
+                 (md5->hiLen << 3);
+    md5->loLen = md5->loLen << 3;
+
+    /* store lengths */
+    #if defined(BIG_ENDIAN_ORDER) && !defined(FREESCALE_MMCAU)
+        ByteReverseWords(md5->buffer, md5->buffer, MD5_BLOCK_SIZE);
+    #endif
+    /* ! length ordering dependent on digest endian type ! */
+    XMEMCPY(&local[MD5_PAD_SIZE], &md5->loLen, sizeof(word32));
+    XMEMCPY(&local[MD5_PAD_SIZE + sizeof(word32)], &md5->hiLen, sizeof(word32));
+
+    XTRANSFORM(md5, local);
+    #ifdef BIG_ENDIAN_ORDER
+        ByteReverseWords(md5->digest, md5->digest, MD5_DIGEST_SIZE);
+    #endif
+    XMEMCPY(hash, md5->digest, MD5_DIGEST_SIZE);
+
+    wc_InitMd5(md5);  /* reset state */
+}
+
+#endif /* STM32F2_HASH */
+
+
+int wc_Md5Hash(const byte* data, word32 len, byte* hash)
+{
+#ifdef WOLFSSL_SMALL_STACK
+    Md5* md5;
+#else
+    Md5 md5[1];
+#endif
+
+#ifdef WOLFSSL_SMALL_STACK
+    md5 = (Md5*)XMALLOC(sizeof(Md5), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (md5 == NULL)
+        return MEMORY_E;
+#endif
+
+    wc_InitMd5(md5);
+    wc_Md5Update(md5, data, len);
+    wc_Md5Final(md5, hash);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(md5, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return 0;
+}
+
+#endif /* WOLFSSL_TI_HASH */
+
+#endif /* NO_MD5 */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/memory.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/memory.c
new file mode 100644
index 0000000..dd92819
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/memory.c
@@ -0,0 +1,191 @@
+/* memory.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+/* check old macros @wc_fips */
+#if defined(USE_CYASSL_MEMORY) && !defined(USE_WOLFSSL_MEMORY)
+    #define USE_WOLFSSL_MEMORY
+#endif
+#if defined(CYASSL_MALLOC_CHECK) && !defined(WOLFSSL_MALLOC_CHECK)
+    #define WOLFSSL_MALLOC_CHECK
+#endif
+
+#ifdef USE_WOLFSSL_MEMORY
+
+#include 
+#include 
+
+#ifdef WOLFSSL_MALLOC_CHECK
+    #include 
+#endif
+
+/* Set these to default values initially. */
+static wolfSSL_Malloc_cb  malloc_function = 0;
+static wolfSSL_Free_cb    free_function = 0;
+static wolfSSL_Realloc_cb realloc_function = 0;
+
+int wolfSSL_SetAllocators(wolfSSL_Malloc_cb  mf,
+                          wolfSSL_Free_cb    ff,
+                          wolfSSL_Realloc_cb rf)
+{
+    int res = 0;
+
+    if (mf)
+        malloc_function = mf;
+    else
+        res = BAD_FUNC_ARG;
+
+    if (ff)
+        free_function = ff;
+    else
+        res = BAD_FUNC_ARG;
+
+    if (rf)
+        realloc_function = rf;
+    else
+        res = BAD_FUNC_ARG;
+
+    return res;
+}
+
+
+void* wolfSSL_Malloc(size_t size)
+{
+    void* res = 0;
+
+    if (malloc_function)
+        res = malloc_function(size);
+    else
+        res = malloc(size);
+
+    #ifdef WOLFSSL_MALLOC_CHECK
+        if (res == NULL)
+            puts("wolfSSL_malloc failed");
+    #endif
+                
+    return res;
+}
+
+void wolfSSL_Free(void *ptr)
+{
+    if (free_function)
+        free_function(ptr);
+    else
+        free(ptr);
+}
+
+void* wolfSSL_Realloc(void *ptr, size_t size)
+{
+    void* res = 0;
+
+    if (realloc_function)
+        res = realloc_function(ptr, size);
+    else
+        res = realloc(ptr, size);
+
+    return res;
+}
+
+#endif /* USE_WOLFSSL_MEMORY */
+
+
+#ifdef HAVE_IO_POOL
+
+/* Example for user io pool, shared build may need definitions in lib proper */
+
+#include 
+#include 
+
+#ifndef HAVE_THREAD_LS
+    #error "Oops, simple I/O pool example needs thread local storage"
+#endif
+
+
+/* allow simple per thread in and out pools */
+/* use 17k size sense max record size is 16k plus overhead */
+static THREAD_LS_T byte pool_in[17*1024];
+static THREAD_LS_T byte pool_out[17*1024];
+
+
+void* XMALLOC(size_t n, void* heap, int type)
+{
+    (void)heap;
+
+    if (type == DYNAMIC_TYPE_IN_BUFFER) {
+        if (n < sizeof(pool_in))
+            return pool_in;
+        else
+            return NULL;
+    }
+
+    if (type == DYNAMIC_TYPE_OUT_BUFFER) {
+        if (n < sizeof(pool_out))
+            return pool_out;
+        else
+            return NULL;
+    }
+
+    return malloc(n);
+}
+
+void* XREALLOC(void *p, size_t n, void* heap, int type)
+{
+    (void)heap;
+
+    if (type == DYNAMIC_TYPE_IN_BUFFER) {
+        if (n < sizeof(pool_in))
+            return pool_in;
+        else
+            return NULL;
+    }
+
+    if (type == DYNAMIC_TYPE_OUT_BUFFER) {
+        if (n < sizeof(pool_out))
+            return pool_out;
+        else
+            return NULL;
+    }
+
+    return realloc(p, n);
+}
+
+
+/* unit api calls, let's make sure visible with WOLFSSL_API */
+WOLFSSL_API void XFREE(void *p, void* heap, int type)
+{
+    (void)heap;
+
+    if (type == DYNAMIC_TYPE_IN_BUFFER)
+        return;  /* do nothing, static pool */
+
+    if (type == DYNAMIC_TYPE_OUT_BUFFER)
+        return;  /* do nothing, static pool */
+
+    free(p);
+}
+
+#endif /* HAVE_IO_POOL */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/misc.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/misc.c
new file mode 100644
index 0000000..8a79a4c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/misc.c
@@ -0,0 +1,201 @@
+/* misc.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifndef WOLF_CRYPT_MISC_C
+#define WOLF_CRYPT_MISC_C
+
+#include 
+
+/* inlining these functions is a huge speed increase and a small size decrease, 
+   because the functions are smaller than function call setup/cleanup, e.g.,
+   md5 benchmark is twice as fast with inline.  If you don't want it, then
+   define NO_INLINE and compile this file into wolfssl, otherwise it's used as
+   a source header
+ */
+
+#ifdef NO_INLINE
+    #define STATIC
+#else
+    #define STATIC static
+#endif
+
+
+#ifdef INTEL_INTRINSICS
+
+    #include       /* get intrinsic definitions */
+
+    /* for non visual studio probably need no long version, 32 bit only
+     * i.e., _rotl and _rotr */
+    #pragma intrinsic(_lrotl, _lrotr)
+
+    STATIC INLINE word32 rotlFixed(word32 x, word32 y)
+    {
+        return y ? _lrotl(x, y) : x;
+    }
+
+    STATIC INLINE word32 rotrFixed(word32 x, word32 y)
+    {
+        return y ? _lrotr(x, y) : x;
+    }
+
+#else /* generic */
+
+    STATIC INLINE word32 rotlFixed(word32 x, word32 y)
+    {
+        return (x << y) | (x >> (sizeof(y) * 8 - y));
+    }   
+
+
+    STATIC INLINE word32 rotrFixed(word32 x, word32 y)
+    {
+        return (x >> y) | (x << (sizeof(y) * 8 - y));
+    }
+
+#endif
+
+
+STATIC INLINE word32 ByteReverseWord32(word32 value)
+{
+#ifdef PPC_INTRINSICS
+    /* PPC: load reverse indexed instruction */
+    return (word32)__lwbrx(&value,0);
+#elif defined(KEIL_INTRINSICS)
+    return (word32)__rev(value);
+#elif defined(FAST_ROTATE)
+    /* 5 instructions with rotate instruction, 9 without */
+    return (rotrFixed(value, 8U) & 0xff00ff00) |
+           (rotlFixed(value, 8U) & 0x00ff00ff);
+#else
+    /* 6 instructions with rotate instruction, 8 without */
+    value = ((value & 0xFF00FF00) >> 8) | ((value & 0x00FF00FF) << 8);
+    return rotlFixed(value, 16U);
+#endif
+}
+
+
+STATIC INLINE void ByteReverseWords(word32* out, const word32* in,
+                                    word32 byteCount)
+{
+    word32 count = byteCount/(word32)sizeof(word32), i;
+
+    for (i = 0; i < count; i++)
+        out[i] = ByteReverseWord32(in[i]);
+
+}
+
+
+#ifdef WORD64_AVAILABLE
+
+
+STATIC INLINE word64 rotlFixed64(word64 x, word64 y)
+{
+    return (x << y) | (x >> (sizeof(y) * 8 - y));
+}  
+
+
+STATIC INLINE word64 rotrFixed64(word64 x, word64 y)
+{
+    return (x >> y) | (x << (sizeof(y) * 8 - y));
+}
+
+
+STATIC INLINE word64 ByteReverseWord64(word64 value)
+{
+#ifdef WOLFCRYPT_SLOW_WORD64
+	return (word64)(ByteReverseWord32((word32)value)) << 32 | 
+                    ByteReverseWord32((word32)(value>>32));
+#else
+	value = ((value & W64LIT(0xFF00FF00FF00FF00)) >> 8) |
+            ((value & W64LIT(0x00FF00FF00FF00FF)) << 8);
+	value = ((value & W64LIT(0xFFFF0000FFFF0000)) >> 16) |
+            ((value & W64LIT(0x0000FFFF0000FFFF)) << 16);
+	return rotlFixed64(value, 32U);
+#endif
+}
+
+
+STATIC INLINE void ByteReverseWords64(word64* out, const word64* in,
+                                      word32 byteCount)
+{
+    word32 count = byteCount/(word32)sizeof(word64), i;
+
+    for (i = 0; i < count; i++)
+        out[i] = ByteReverseWord64(in[i]);
+
+}
+
+#endif /* WORD64_AVAILABLE */
+
+
+STATIC INLINE void XorWords(wolfssl_word* r, const wolfssl_word* a, word32 n)
+{
+    word32 i;
+
+    for (i = 0; i < n; i++) r[i] ^= a[i];
+}
+
+
+STATIC INLINE void xorbuf(void* buf, const void* mask, word32 count)
+{
+    if (((wolfssl_word)buf | (wolfssl_word)mask | count) % WOLFSSL_WORD_SIZE == 0)
+        XorWords( (wolfssl_word*)buf,
+                  (const wolfssl_word*)mask, count / WOLFSSL_WORD_SIZE);
+    else {
+        word32 i;
+        byte*       b = (byte*)buf;
+        const byte* m = (const byte*)mask;
+
+        for (i = 0; i < count; i++) b[i] ^= m[i];
+    }
+}
+
+
+/* Make sure compiler doesn't skip */
+STATIC INLINE void ForceZero(const void* mem, word32 len)
+{
+    volatile byte* z = (volatile byte*)mem;
+
+    while (len--) *z++ = 0;
+}
+
+
+/* check all length bytes for equality, return 0 on success */
+STATIC INLINE int ConstantCompare(const byte* a, const byte* b, int length)
+{
+    int i;
+    int compareSum = 0;
+
+    for (i = 0; i < length; i++) {
+        compareSum |= a[i] ^ b[i];
+    }
+
+    return compareSum;
+}
+
+#undef STATIC
+
+#endif /* WOLF_CRYPT_MISC_C */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/pkcs7.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/pkcs7.c
new file mode 100644
index 0000000..2f66ea2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/pkcs7.c
@@ -0,0 +1,1858 @@
+/* pkcs7.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifdef HAVE_PKCS7
+
+#include 
+#include 
+#include 
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+#ifndef WOLFSSL_HAVE_MIN
+#define WOLFSSL_HAVE_MIN
+
+    static INLINE word32 min(word32 a, word32 b)
+    {
+        return a > b ? b : a;
+    }
+
+#endif /* WOLFSSL_HAVE_MIN */
+
+
+/* placed ASN.1 contentType OID into *output, return idx on success,
+ * 0 upon failure */
+WOLFSSL_LOCAL int wc_SetContentType(int pkcs7TypeOID, byte* output)
+{
+    /* PKCS#7 content types, RFC 2315, section 14 */
+    static const byte pkcs7[]              = { 0x2A, 0x86, 0x48, 0x86, 0xF7,
+                                               0x0D, 0x01, 0x07 };
+    static const byte data[]               = { 0x2A, 0x86, 0x48, 0x86, 0xF7,
+                                               0x0D, 0x01, 0x07, 0x01 };
+    static const byte signedData[]         = { 0x2A, 0x86, 0x48, 0x86, 0xF7,
+                                               0x0D, 0x01, 0x07, 0x02};
+    static const byte envelopedData[]      = { 0x2A, 0x86, 0x48, 0x86, 0xF7,
+                                               0x0D, 0x01, 0x07, 0x03 };
+    static const byte signedAndEnveloped[] = { 0x2A, 0x86, 0x48, 0x86, 0xF7,
+                                               0x0D, 0x01, 0x07, 0x04 };
+    static const byte digestedData[]       = { 0x2A, 0x86, 0x48, 0x86, 0xF7,
+                                               0x0D, 0x01, 0x07, 0x05 };
+    static const byte encryptedData[]      = { 0x2A, 0x86, 0x48, 0x86, 0xF7,
+                                               0x0D, 0x01, 0x07, 0x06 };
+
+    int idSz;
+    int typeSz = 0, idx = 0;
+    const byte* typeName = 0;
+    byte ID_Length[MAX_LENGTH_SZ];
+
+    switch (pkcs7TypeOID) {
+        case PKCS7_MSG:
+            typeSz = sizeof(pkcs7);
+            typeName = pkcs7;
+            break;
+
+        case DATA:
+            typeSz = sizeof(data);
+            typeName = data;
+            break;
+
+        case SIGNED_DATA:
+            typeSz = sizeof(signedData);
+            typeName = signedData;
+            break;
+        
+        case ENVELOPED_DATA:
+            typeSz = sizeof(envelopedData);
+            typeName = envelopedData;
+            break;
+
+        case SIGNED_AND_ENVELOPED_DATA:
+            typeSz = sizeof(signedAndEnveloped);
+            typeName = signedAndEnveloped;
+            break;
+
+        case DIGESTED_DATA:
+            typeSz = sizeof(digestedData);
+            typeName = digestedData;
+            break;
+
+        case ENCRYPTED_DATA:
+            typeSz = sizeof(encryptedData);
+            typeName = encryptedData;
+            break;
+
+        default:
+            WOLFSSL_MSG("Unknown PKCS#7 Type");
+            return 0;
+    };
+
+    idSz  = SetLength(typeSz, ID_Length);
+    output[idx++] = ASN_OBJECT_ID;
+    XMEMCPY(output + idx, ID_Length, idSz);
+    idx += idSz;
+    XMEMCPY(output + idx, typeName, typeSz);
+    idx += typeSz;
+
+    return idx;
+
+}
+
+
+/* get ASN.1 contentType OID sum, return 0 on success, <0 on failure */
+int wc_GetContentType(const byte* input, word32* inOutIdx, word32* oid,
+                   word32 maxIdx)
+{
+    int length;
+    word32 i = *inOutIdx;
+    byte b;
+    *oid = 0;
+
+    WOLFSSL_ENTER("wc_GetContentType");
+
+    b = input[i++];
+    if (b != ASN_OBJECT_ID)
+        return ASN_OBJECT_ID_E;
+
+    if (GetLength(input, &i, &length, maxIdx) < 0)
+        return ASN_PARSE_E;
+
+    while(length--) {
+        *oid += input[i];
+        i++;
+    }
+
+    *inOutIdx = i;
+
+    return 0;
+}
+
+
+/* init PKCS7 struct with recipient cert, decode into DecodedCert */
+int wc_PKCS7_InitWithCert(PKCS7* pkcs7, byte* cert, word32 certSz)
+{
+    int ret = 0;
+
+    XMEMSET(pkcs7, 0, sizeof(PKCS7));
+    if (cert != NULL && certSz > 0) {
+#ifdef WOLFSSL_SMALL_STACK
+        DecodedCert* dCert;
+
+        dCert = (DecodedCert*)XMALLOC(sizeof(DecodedCert), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+        if (dCert == NULL)
+            return MEMORY_E;
+#else
+        DecodedCert stack_dCert;
+        DecodedCert* dCert = &stack_dCert;
+#endif
+
+        pkcs7->singleCert = cert;
+        pkcs7->singleCertSz = certSz;
+        InitDecodedCert(dCert, cert, certSz, 0);
+
+        ret = ParseCert(dCert, CA_TYPE, NO_VERIFY, 0);
+        if (ret < 0) {
+            FreeDecodedCert(dCert);
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(dCert, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return ret;
+        }
+
+        XMEMCPY(pkcs7->publicKey, dCert->publicKey, dCert->pubKeySize);
+        pkcs7->publicKeySz = dCert->pubKeySize;
+        XMEMCPY(pkcs7->issuerHash, dCert->issuerHash, KEYID_SIZE);
+        pkcs7->issuer = dCert->issuerRaw;
+        pkcs7->issuerSz = dCert->issuerRawLen;
+        XMEMCPY(pkcs7->issuerSn, dCert->serial, dCert->serialSz);
+        pkcs7->issuerSnSz = dCert->serialSz;
+        FreeDecodedCert(dCert);
+
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(dCert, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+    }
+
+    return ret;
+}
+
+
+/* releases any memory allocated by a PKCS7 initializer */
+void wc_PKCS7_Free(PKCS7* pkcs7)
+{
+    (void)pkcs7;
+}
+
+
+/* build PKCS#7 data content type */
+int wc_PKCS7_EncodeData(PKCS7* pkcs7, byte* output, word32 outputSz)
+{
+    static const byte oid[] =
+        { ASN_OBJECT_ID, 0x09, 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01,
+                         0x07, 0x01 };
+    byte seq[MAX_SEQ_SZ];
+    byte octetStr[MAX_OCTET_STR_SZ];
+    word32 seqSz;
+    word32 octetStrSz;
+    word32 oidSz = (word32)sizeof(oid);
+    int idx = 0;
+
+    octetStrSz = SetOctetString(pkcs7->contentSz, octetStr);
+    seqSz = SetSequence(pkcs7->contentSz + octetStrSz + oidSz, seq);
+
+    if (outputSz < pkcs7->contentSz + octetStrSz + oidSz + seqSz)
+        return BUFFER_E;
+
+    XMEMCPY(output, seq, seqSz);
+    idx += seqSz;
+    XMEMCPY(output + idx, oid, oidSz);
+    idx += oidSz;
+    XMEMCPY(output + idx, octetStr, octetStrSz);
+    idx += octetStrSz;
+    XMEMCPY(output + idx, pkcs7->content, pkcs7->contentSz);
+    idx += pkcs7->contentSz;
+
+    return idx;
+}
+
+
+typedef struct EncodedAttrib {
+    byte valueSeq[MAX_SEQ_SZ];
+        const byte* oid;
+        byte valueSet[MAX_SET_SZ];
+        const byte* value;
+    word32 valueSeqSz, oidSz, idSz, valueSetSz, valueSz, totalSz;
+} EncodedAttrib;
+
+
+typedef struct ESD {
+    Sha sha;
+    byte contentDigest[SHA_DIGEST_SIZE + 2]; /* content only + ASN.1 heading */
+    byte contentAttribsDigest[SHA_DIGEST_SIZE];
+    byte encContentDigest[512];
+
+    byte outerSeq[MAX_SEQ_SZ];
+        byte outerContent[MAX_EXP_SZ];
+            byte innerSeq[MAX_SEQ_SZ];
+                byte version[MAX_VERSION_SZ];
+                byte digAlgoIdSet[MAX_SET_SZ];
+                    byte singleDigAlgoId[MAX_ALGO_SZ];
+
+                byte contentInfoSeq[MAX_SEQ_SZ];
+                    byte innerContSeq[MAX_EXP_SZ];
+                        byte innerOctets[MAX_OCTET_STR_SZ];
+
+                byte certsSet[MAX_SET_SZ];
+
+                byte signerInfoSet[MAX_SET_SZ];
+                    byte signerInfoSeq[MAX_SEQ_SZ];
+                        byte signerVersion[MAX_VERSION_SZ];
+                        byte issuerSnSeq[MAX_SEQ_SZ];
+                            byte issuerName[MAX_SEQ_SZ];
+                            byte issuerSn[MAX_SN_SZ];
+                        byte signerDigAlgoId[MAX_ALGO_SZ];
+                        byte digEncAlgoId[MAX_ALGO_SZ];
+                        byte signedAttribSet[MAX_SET_SZ];
+                            EncodedAttrib signedAttribs[6];
+                        byte signerDigest[MAX_OCTET_STR_SZ];
+    word32 innerOctetsSz, innerContSeqSz, contentInfoSeqSz;
+    word32 outerSeqSz, outerContentSz, innerSeqSz, versionSz, digAlgoIdSetSz,
+           singleDigAlgoIdSz, certsSetSz;
+    word32 signerInfoSetSz, signerInfoSeqSz, signerVersionSz,
+           issuerSnSeqSz, issuerNameSz, issuerSnSz,
+           signerDigAlgoIdSz, digEncAlgoIdSz, signerDigestSz;
+    word32 encContentDigestSz, signedAttribsSz, signedAttribsCount,
+           signedAttribSetSz;
+} ESD;
+
+
+static int EncodeAttributes(EncodedAttrib* ea, int eaSz,
+                                            PKCS7Attrib* attribs, int attribsSz)
+{
+    int i;
+    int maxSz = min(eaSz, attribsSz);
+    int allAttribsSz = 0;
+
+    for (i = 0; i < maxSz; i++)
+    {
+        int attribSz = 0;
+
+        ea[i].value = attribs[i].value;
+        ea[i].valueSz = attribs[i].valueSz;
+        attribSz += ea[i].valueSz;
+        ea[i].valueSetSz = SetSet(attribSz, ea[i].valueSet);
+        attribSz += ea[i].valueSetSz;
+        ea[i].oid = attribs[i].oid;
+        ea[i].oidSz = attribs[i].oidSz;
+        attribSz += ea[i].oidSz;
+        ea[i].valueSeqSz = SetSequence(attribSz, ea[i].valueSeq);
+        attribSz += ea[i].valueSeqSz;
+        ea[i].totalSz = attribSz;
+
+        allAttribsSz += attribSz;
+    }
+    return allAttribsSz;
+}
+
+
+static int FlattenAttributes(byte* output, EncodedAttrib* ea, int eaSz)
+{
+    int i, idx;
+
+    idx = 0;
+    for (i = 0; i < eaSz; i++) {
+        XMEMCPY(output + idx, ea[i].valueSeq, ea[i].valueSeqSz);
+        idx += ea[i].valueSeqSz;
+        XMEMCPY(output + idx, ea[i].oid, ea[i].oidSz);
+        idx += ea[i].oidSz;
+        XMEMCPY(output + idx, ea[i].valueSet, ea[i].valueSetSz);
+        idx += ea[i].valueSetSz;
+        XMEMCPY(output + idx, ea[i].value, ea[i].valueSz);
+        idx += ea[i].valueSz;
+    }
+    return 0;
+}
+
+
+/* build PKCS#7 signedData content type */
+int wc_PKCS7_EncodeSignedData(PKCS7* pkcs7, byte* output, word32 outputSz)
+{
+    static const byte outerOid[] =
+        { ASN_OBJECT_ID, 0x09, 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01,
+                         0x07, 0x02 };
+    static const byte innerOid[] =
+        { ASN_OBJECT_ID, 0x09, 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01,
+                         0x07, 0x01 };
+
+#ifdef WOLFSSL_SMALL_STACK
+    ESD* esd = NULL;
+#else
+    ESD stack_esd;
+    ESD* esd = &stack_esd;
+#endif
+
+    word32 signerInfoSz = 0;
+    word32 totalSz = 0;
+    int idx = 0, ret = 0;
+    byte* flatSignedAttribs = NULL;
+    word32 flatSignedAttribsSz = 0;
+    word32 innerOidSz = sizeof(innerOid);
+    word32 outerOidSz = sizeof(outerOid);
+
+    if (pkcs7 == NULL || pkcs7->content == NULL || pkcs7->contentSz == 0 ||
+        pkcs7->encryptOID == 0 || pkcs7->hashOID == 0 || pkcs7->rng == 0 ||
+        pkcs7->singleCert == NULL || pkcs7->singleCertSz == 0 ||
+        pkcs7->privateKey == NULL || pkcs7->privateKeySz == 0 ||
+        output == NULL || outputSz == 0)
+        return BAD_FUNC_ARG;
+
+#ifdef WOLFSSL_SMALL_STACK
+    esd = (ESD*)XMALLOC(sizeof(ESD), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (esd == NULL)
+        return MEMORY_E;
+#endif
+
+    XMEMSET(esd, 0, sizeof(ESD));
+    ret = wc_InitSha(&esd->sha);
+    if (ret != 0) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(esd, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return ret;
+    }
+
+    if (pkcs7->contentSz != 0)
+    {
+        wc_ShaUpdate(&esd->sha, pkcs7->content, pkcs7->contentSz);
+        esd->contentDigest[0] = ASN_OCTET_STRING;
+        esd->contentDigest[1] = SHA_DIGEST_SIZE;
+        wc_ShaFinal(&esd->sha, &esd->contentDigest[2]);
+    }
+
+    esd->innerOctetsSz = SetOctetString(pkcs7->contentSz, esd->innerOctets);
+    esd->innerContSeqSz = SetExplicit(0, esd->innerOctetsSz + pkcs7->contentSz,
+                                esd->innerContSeq);
+    esd->contentInfoSeqSz = SetSequence(pkcs7->contentSz + esd->innerOctetsSz +
+                                    innerOidSz + esd->innerContSeqSz,
+                                    esd->contentInfoSeq);
+
+    esd->issuerSnSz = SetSerialNumber(pkcs7->issuerSn, pkcs7->issuerSnSz,
+                                     esd->issuerSn);
+    signerInfoSz += esd->issuerSnSz;
+    esd->issuerNameSz = SetSequence(pkcs7->issuerSz, esd->issuerName);
+    signerInfoSz += esd->issuerNameSz + pkcs7->issuerSz;
+    esd->issuerSnSeqSz = SetSequence(signerInfoSz, esd->issuerSnSeq);
+    signerInfoSz += esd->issuerSnSeqSz;
+    esd->signerVersionSz = SetMyVersion(1, esd->signerVersion, 0);
+    signerInfoSz += esd->signerVersionSz;
+    esd->signerDigAlgoIdSz = SetAlgoID(pkcs7->hashOID, esd->signerDigAlgoId,
+                                      hashType, 0);
+    signerInfoSz += esd->signerDigAlgoIdSz;
+    esd->digEncAlgoIdSz = SetAlgoID(pkcs7->encryptOID, esd->digEncAlgoId,
+                                   keyType, 0);
+    signerInfoSz += esd->digEncAlgoIdSz;
+
+    if (pkcs7->signedAttribsSz != 0) {
+        byte contentTypeOid[] =
+                { ASN_OBJECT_ID, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xF7, 0x0d, 0x01,
+                                 0x09, 0x03 };
+        byte contentType[] =
+                { ASN_OBJECT_ID, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01,
+                                 0x07, 0x01 };
+        byte messageDigestOid[] =
+                { ASN_OBJECT_ID, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01,
+                                 0x09, 0x04 };
+
+        PKCS7Attrib cannedAttribs[2] =
+        {
+            { contentTypeOid, sizeof(contentTypeOid),
+                             contentType, sizeof(contentType) },
+            { messageDigestOid, sizeof(messageDigestOid),
+                             esd->contentDigest, sizeof(esd->contentDigest) }
+        };
+        word32 cannedAttribsCount = sizeof(cannedAttribs)/sizeof(PKCS7Attrib);
+
+        esd->signedAttribsCount += cannedAttribsCount;
+        esd->signedAttribsSz += EncodeAttributes(&esd->signedAttribs[0], 2,
+                                             cannedAttribs, cannedAttribsCount);
+
+        esd->signedAttribsCount += pkcs7->signedAttribsSz;
+        esd->signedAttribsSz += EncodeAttributes(&esd->signedAttribs[2], 4,
+                                  pkcs7->signedAttribs, pkcs7->signedAttribsSz);
+
+        flatSignedAttribs = (byte*)XMALLOC(esd->signedAttribsSz, 0, NULL);
+        flatSignedAttribsSz = esd->signedAttribsSz;
+        if (flatSignedAttribs == NULL) {
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(esd, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif   
+            return MEMORY_E;
+        }
+        FlattenAttributes(flatSignedAttribs,
+                                   esd->signedAttribs, esd->signedAttribsCount);
+        esd->signedAttribSetSz = SetImplicit(ASN_SET, 0, esd->signedAttribsSz,
+                                                          esd->signedAttribSet);
+    }
+    /* Calculate the final hash and encrypt it. */
+    {
+        int result;
+        word32 scratch = 0;
+
+#ifdef WOLFSSL_SMALL_STACK
+        byte* digestInfo;
+        RsaKey* privKey;
+#else
+        RsaKey stack_privKey;
+        RsaKey* privKey = &stack_privKey;
+        byte digestInfo[MAX_SEQ_SZ + MAX_ALGO_SZ +
+                        MAX_OCTET_STR_SZ + SHA_DIGEST_SIZE];
+#endif
+        byte digestInfoSeq[MAX_SEQ_SZ];
+        byte digestStr[MAX_OCTET_STR_SZ];
+        word32 digestInfoSeqSz, digestStrSz;
+        int digIdx = 0;
+
+        if (pkcs7->signedAttribsSz != 0) {
+            byte attribSet[MAX_SET_SZ];
+            word32 attribSetSz;
+
+            attribSetSz = SetSet(flatSignedAttribsSz, attribSet);
+
+            ret = wc_InitSha(&esd->sha);
+            if (ret < 0) {
+                XFREE(flatSignedAttribs, 0, NULL);
+#ifdef WOLFSSL_SMALL_STACK
+                XFREE(esd, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+                return ret;
+            }
+            wc_ShaUpdate(&esd->sha, attribSet, attribSetSz);
+            wc_ShaUpdate(&esd->sha, flatSignedAttribs, flatSignedAttribsSz);
+        }
+        wc_ShaFinal(&esd->sha, esd->contentAttribsDigest);
+
+        digestStrSz = SetOctetString(SHA_DIGEST_SIZE, digestStr);
+        digestInfoSeqSz = SetSequence(esd->signerDigAlgoIdSz +
+                                      digestStrSz + SHA_DIGEST_SIZE,
+                                      digestInfoSeq);
+
+#ifdef WOLFSSL_SMALL_STACK
+        digestInfo = (byte*)XMALLOC(MAX_SEQ_SZ + MAX_ALGO_SZ +
+                                    MAX_OCTET_STR_SZ + SHA_DIGEST_SIZE,
+                                    NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (digestInfo == NULL) {
+            if (pkcs7->signedAttribsSz != 0)
+                XFREE(flatSignedAttribs, 0, NULL);
+            XFREE(esd, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            return MEMORY_E;
+        }
+#endif
+
+        XMEMCPY(digestInfo + digIdx, digestInfoSeq, digestInfoSeqSz);
+        digIdx += digestInfoSeqSz;
+        XMEMCPY(digestInfo + digIdx,
+                                  esd->signerDigAlgoId, esd->signerDigAlgoIdSz);
+        digIdx += esd->signerDigAlgoIdSz;
+        XMEMCPY(digestInfo + digIdx, digestStr, digestStrSz);
+        digIdx += digestStrSz;
+        XMEMCPY(digestInfo + digIdx, esd->contentAttribsDigest,
+                                                               SHA_DIGEST_SIZE);
+        digIdx += SHA_DIGEST_SIZE;
+
+#ifdef WOLFSSL_SMALL_STACK
+        privKey = (RsaKey*)XMALLOC(sizeof(RsaKey), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+        if (privKey == NULL) {
+            if (pkcs7->signedAttribsSz != 0)
+                XFREE(flatSignedAttribs, 0, NULL);
+            XFREE(digestInfo, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            XFREE(esd,        NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            return MEMORY_E;
+        }
+#endif
+
+        result = wc_InitRsaKey(privKey, NULL);
+        if (result == 0)
+            result = wc_RsaPrivateKeyDecode(pkcs7->privateKey, &scratch, privKey,
+                                         pkcs7->privateKeySz);
+        if (result < 0) {
+            if (pkcs7->signedAttribsSz != 0)
+                XFREE(flatSignedAttribs, 0, NULL);
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(privKey,    NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            XFREE(digestInfo, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            XFREE(esd,        NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return PUBLIC_KEY_E;
+        }
+
+        result = wc_RsaSSL_Sign(digestInfo, digIdx,
+                             esd->encContentDigest,
+                             sizeof(esd->encContentDigest),
+                             privKey, pkcs7->rng);
+
+        wc_FreeRsaKey(privKey);
+
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(privKey,    NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(digestInfo, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+        if (result < 0) {
+            if (pkcs7->signedAttribsSz != 0)
+                XFREE(flatSignedAttribs, 0, NULL);
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(esd, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return result;
+        }
+        esd->encContentDigestSz = (word32)result;
+    }
+    signerInfoSz += flatSignedAttribsSz + esd->signedAttribSetSz;
+
+    esd->signerDigestSz = SetOctetString(esd->encContentDigestSz,
+                                                             esd->signerDigest);
+    signerInfoSz += esd->signerDigestSz + esd->encContentDigestSz;
+
+    esd->signerInfoSeqSz = SetSequence(signerInfoSz, esd->signerInfoSeq);
+    signerInfoSz += esd->signerInfoSeqSz;
+    esd->signerInfoSetSz = SetSet(signerInfoSz, esd->signerInfoSet);
+    signerInfoSz += esd->signerInfoSetSz;
+
+    esd->certsSetSz = SetImplicit(ASN_SET, 0, pkcs7->singleCertSz,
+                                                                 esd->certsSet);
+
+    esd->singleDigAlgoIdSz = SetAlgoID(pkcs7->hashOID, esd->singleDigAlgoId,
+                                      hashType, 0);
+    esd->digAlgoIdSetSz = SetSet(esd->singleDigAlgoIdSz, esd->digAlgoIdSet);
+
+
+    esd->versionSz = SetMyVersion(1, esd->version, 0);
+
+    totalSz = esd->versionSz + esd->singleDigAlgoIdSz + esd->digAlgoIdSetSz +
+              esd->contentInfoSeqSz + esd->certsSetSz + pkcs7->singleCertSz +
+              esd->innerOctetsSz + esd->innerContSeqSz +
+              innerOidSz + pkcs7->contentSz +
+              signerInfoSz;
+    esd->innerSeqSz = SetSequence(totalSz, esd->innerSeq);
+    totalSz += esd->innerSeqSz;
+    esd->outerContentSz = SetExplicit(0, totalSz, esd->outerContent);
+    totalSz += esd->outerContentSz + outerOidSz;
+    esd->outerSeqSz = SetSequence(totalSz, esd->outerSeq);
+    totalSz += esd->outerSeqSz;
+
+    if (outputSz < totalSz) {
+        if (pkcs7->signedAttribsSz != 0)
+            XFREE(flatSignedAttribs, 0, NULL);
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(esd, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return BUFFER_E;
+    }
+
+    idx = 0;
+    XMEMCPY(output + idx, esd->outerSeq, esd->outerSeqSz);
+    idx += esd->outerSeqSz;
+    XMEMCPY(output + idx, outerOid, outerOidSz);
+    idx += outerOidSz;
+    XMEMCPY(output + idx, esd->outerContent, esd->outerContentSz);
+    idx += esd->outerContentSz;
+    XMEMCPY(output + idx, esd->innerSeq, esd->innerSeqSz);
+    idx += esd->innerSeqSz;
+    XMEMCPY(output + idx, esd->version, esd->versionSz);
+    idx += esd->versionSz;
+    XMEMCPY(output + idx, esd->digAlgoIdSet, esd->digAlgoIdSetSz);
+    idx += esd->digAlgoIdSetSz;
+    XMEMCPY(output + idx, esd->singleDigAlgoId, esd->singleDigAlgoIdSz);
+    idx += esd->singleDigAlgoIdSz;
+    XMEMCPY(output + idx, esd->contentInfoSeq, esd->contentInfoSeqSz);
+    idx += esd->contentInfoSeqSz;
+    XMEMCPY(output + idx, innerOid, innerOidSz);
+    idx += innerOidSz;
+    XMEMCPY(output + idx, esd->innerContSeq, esd->innerContSeqSz);
+    idx += esd->innerContSeqSz;
+    XMEMCPY(output + idx, esd->innerOctets, esd->innerOctetsSz);
+    idx += esd->innerOctetsSz;
+    XMEMCPY(output + idx, pkcs7->content, pkcs7->contentSz);
+    idx += pkcs7->contentSz;
+    XMEMCPY(output + idx, esd->certsSet, esd->certsSetSz);
+    idx += esd->certsSetSz;
+    XMEMCPY(output + idx, pkcs7->singleCert, pkcs7->singleCertSz);
+    idx += pkcs7->singleCertSz;
+    XMEMCPY(output + idx, esd->signerInfoSet, esd->signerInfoSetSz);
+    idx += esd->signerInfoSetSz;
+    XMEMCPY(output + idx, esd->signerInfoSeq, esd->signerInfoSeqSz);
+    idx += esd->signerInfoSeqSz;
+    XMEMCPY(output + idx, esd->signerVersion, esd->signerVersionSz);
+    idx += esd->signerVersionSz;
+    XMEMCPY(output + idx, esd->issuerSnSeq, esd->issuerSnSeqSz);
+    idx += esd->issuerSnSeqSz;
+    XMEMCPY(output + idx, esd->issuerName, esd->issuerNameSz);
+    idx += esd->issuerNameSz;
+    XMEMCPY(output + idx, pkcs7->issuer, pkcs7->issuerSz);
+    idx += pkcs7->issuerSz;
+    XMEMCPY(output + idx, esd->issuerSn, esd->issuerSnSz);
+    idx += esd->issuerSnSz;
+    XMEMCPY(output + idx, esd->signerDigAlgoId, esd->signerDigAlgoIdSz);
+    idx += esd->signerDigAlgoIdSz;
+
+    /* SignerInfo:Attributes */
+    if (pkcs7->signedAttribsSz != 0) {
+        XMEMCPY(output + idx, esd->signedAttribSet, esd->signedAttribSetSz);
+        idx += esd->signedAttribSetSz;
+        XMEMCPY(output + idx, flatSignedAttribs, flatSignedAttribsSz);
+        idx += flatSignedAttribsSz;
+        XFREE(flatSignedAttribs, 0, NULL);
+    }
+
+    XMEMCPY(output + idx, esd->digEncAlgoId, esd->digEncAlgoIdSz);
+    idx += esd->digEncAlgoIdSz;
+    XMEMCPY(output + idx, esd->signerDigest, esd->signerDigestSz);
+    idx += esd->signerDigestSz;
+    XMEMCPY(output + idx, esd->encContentDigest, esd->encContentDigestSz);
+    idx += esd->encContentDigestSz;
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(esd, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return idx;
+}
+
+
+/* Finds the certificates in the message and saves it. */
+int wc_PKCS7_VerifySignedData(PKCS7* pkcs7, byte* pkiMsg, word32 pkiMsgSz)
+{
+    word32 idx, contentType;
+    int length, version, ret;
+    byte* content = NULL;
+    byte* sig = NULL;
+    byte* cert = NULL;
+    int contentSz = 0, sigSz = 0, certSz = 0;
+
+    if (pkcs7 == NULL || pkiMsg == NULL || pkiMsgSz == 0)
+        return BAD_FUNC_ARG;
+
+    idx = 0;
+
+    /* Get the contentInfo sequence */
+    if (GetSequence(pkiMsg, &idx, &length, pkiMsgSz) < 0)
+        return ASN_PARSE_E;
+
+    /* Get the contentInfo contentType */
+    if (wc_GetContentType(pkiMsg, &idx, &contentType, pkiMsgSz) < 0)
+        return ASN_PARSE_E;
+
+    if (contentType != SIGNED_DATA) {
+        WOLFSSL_MSG("PKCS#7 input not of type SignedData");
+        return PKCS7_OID_E;
+    }
+
+    /* get the ContentInfo content */
+    if (pkiMsg[idx++] != (ASN_CONSTRUCTED | ASN_CONTEXT_SPECIFIC | 0))
+        return ASN_PARSE_E;
+
+    if (GetLength(pkiMsg, &idx, &length, pkiMsgSz) < 0)
+        return ASN_PARSE_E;
+
+    /* Get the signedData sequence */
+    if (GetSequence(pkiMsg, &idx, &length, pkiMsgSz) < 0)
+        return ASN_PARSE_E;
+
+    /* Get the version */
+    if (GetMyVersion(pkiMsg, &idx, &version) < 0)
+        return ASN_PARSE_E;
+
+    if (version != 1) {
+        WOLFSSL_MSG("PKCS#7 signedData needs to be of version 1");
+        return ASN_VERSION_E;
+    }
+
+    /* Get the set of DigestAlgorithmIdentifiers */
+    if (GetSet(pkiMsg, &idx, &length, pkiMsgSz) < 0)
+        return ASN_PARSE_E;
+
+    /* Skip the set. */
+    idx += length;
+
+    /* Get the inner ContentInfo sequence */
+    if (GetSequence(pkiMsg, &idx, &length, pkiMsgSz) < 0)
+        return ASN_PARSE_E;
+
+    /* Get the inner ContentInfo contentType */
+    if (wc_GetContentType(pkiMsg, &idx, &contentType, pkiMsgSz) < 0)
+        return ASN_PARSE_E;
+
+    if (contentType != DATA) {
+        WOLFSSL_MSG("PKCS#7 inner input not of type Data");
+        return PKCS7_OID_E;
+    }
+
+    if (pkiMsg[idx++] != (ASN_CONSTRUCTED | ASN_CONTEXT_SPECIFIC | 0))
+        return ASN_PARSE_E;
+
+    if (GetLength(pkiMsg, &idx, &length, pkiMsgSz) < 0)
+        return ASN_PARSE_E;
+
+    if (pkiMsg[idx++] != ASN_OCTET_STRING)
+        return ASN_PARSE_E;
+
+    if (GetLength(pkiMsg, &idx, &length, pkiMsgSz) < 0)
+        return ASN_PARSE_E;
+
+    /* Save the inner data as the content. */
+    if (length > 0) {
+        /* Local pointer for calculating hashes later */
+        pkcs7->content = content = &pkiMsg[idx];
+        pkcs7->contentSz = contentSz = length;
+        idx += length;
+    }
+
+    /* Get the implicit[0] set of certificates */
+    if (pkiMsg[idx] == (ASN_CONSTRUCTED | ASN_CONTEXT_SPECIFIC | 0)) {
+        idx++;
+        if (GetLength(pkiMsg, &idx, &length, pkiMsgSz) < 0)
+            return ASN_PARSE_E;
+
+        if (length > 0) {
+            /* At this point, idx is at the first certificate in
+             * a set of certificates. There may be more than one,
+             * or none, or they may be a PKCS 6 extended
+             * certificate. We want to save the first cert if it
+             * is X.509. */
+
+            word32 certIdx = idx;
+
+            if (pkiMsg[certIdx++] == (ASN_CONSTRUCTED | ASN_SEQUENCE)) {
+                if (GetLength(pkiMsg, &certIdx, &certSz, pkiMsgSz) < 0)
+                    return ASN_PARSE_E;
+
+                cert = &pkiMsg[idx];
+                certSz += (certIdx - idx);
+            }
+            wc_PKCS7_InitWithCert(pkcs7, cert, certSz);
+        }
+        idx += length;
+    }
+
+    /* Get the implicit[1] set of crls */
+    if (pkiMsg[idx] == (ASN_CONSTRUCTED | ASN_CONTEXT_SPECIFIC | 1)) {
+        idx++;
+        if (GetLength(pkiMsg, &idx, &length, pkiMsgSz) < 0)
+            return ASN_PARSE_E;
+
+        /* Skip the set */
+        idx += length;
+    }
+
+    /* Get the set of signerInfos */
+    if (GetSet(pkiMsg, &idx, &length, pkiMsgSz) < 0)
+        return ASN_PARSE_E;
+
+    if (length > 0) {
+        /* Get the sequence of the first signerInfo */
+        if (GetSequence(pkiMsg, &idx, &length, pkiMsgSz) < 0)
+            return ASN_PARSE_E;
+
+        /* Get the version */
+        if (GetMyVersion(pkiMsg, &idx, &version) < 0)
+            return ASN_PARSE_E;
+
+        if (version != 1) {
+            WOLFSSL_MSG("PKCS#7 signerInfo needs to be of version 1");
+            return ASN_VERSION_E;
+        }
+
+        /* Get the sequence of IssuerAndSerialNumber */
+        if (GetSequence(pkiMsg, &idx, &length, pkiMsgSz) < 0)
+            return ASN_PARSE_E;
+
+        /* Skip it */
+        idx += length;
+
+        /* Get the sequence of digestAlgorithm */
+        if (GetSequence(pkiMsg, &idx, &length, pkiMsgSz) < 0)
+            return ASN_PARSE_E;
+
+        /* Skip it */
+        idx += length;
+
+        /* Get the IMPLICIT[0] SET OF signedAttributes */
+        if (pkiMsg[idx] == (ASN_CONSTRUCTED | ASN_CONTEXT_SPECIFIC | 0)) {
+            idx++;
+
+            if (GetLength(pkiMsg, &idx, &length, pkiMsgSz) < 0)
+                return ASN_PARSE_E;
+
+            idx += length;
+        }
+
+        /* Get the sequence of digestEncryptionAlgorithm */
+        if (GetSequence(pkiMsg, &idx, &length, pkiMsgSz) < 0)
+            return ASN_PARSE_E;
+
+        /* Skip it */
+        idx += length;
+
+        /* Get the signature */
+        if (pkiMsg[idx] == ASN_OCTET_STRING) {
+            idx++;
+
+            if (GetLength(pkiMsg, &idx, &length, pkiMsgSz) < 0)
+                return ASN_PARSE_E;
+
+            /* save pointer and length */
+            sig = &pkiMsg[idx];
+            sigSz = length;
+
+            idx += length;
+        }
+
+        pkcs7->content = content;
+        pkcs7->contentSz = contentSz;
+
+        {
+            word32 scratch = 0;
+            int plainSz = 0;
+            int digestSz = MAX_SEQ_SZ + MAX_ALGO_SZ +
+                           MAX_OCTET_STR_SZ + SHA_DIGEST_SIZE;
+
+#ifdef WOLFSSL_SMALL_STACK
+            byte* digest;
+            RsaKey* key;
+
+            digest = (byte*)XMALLOC(digestSz, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+
+            if (digest == NULL)
+                return MEMORY_E;
+
+            key = (RsaKey*)XMALLOC(sizeof(RsaKey), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+            if (key == NULL) {
+                XFREE(digest, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                return MEMORY_E;
+            }
+#else
+            byte digest[digestSz];
+            RsaKey stack_key;
+            RsaKey* key = &stack_key;
+#endif
+
+            XMEMSET(digest, 0, digestSz);
+
+            ret = wc_InitRsaKey(key, NULL);
+            if (ret != 0) {
+#ifdef WOLFSSL_SMALL_STACK
+                XFREE(digest, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                XFREE(key,    NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+                return ret;
+            }
+            if (wc_RsaPublicKeyDecode(pkcs7->publicKey, &scratch, key,
+                                   pkcs7->publicKeySz) < 0) {
+                WOLFSSL_MSG("ASN RSA key decode error");
+#ifdef WOLFSSL_SMALL_STACK
+                XFREE(digest, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+                XFREE(key,    NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+                return PUBLIC_KEY_E;
+            }
+
+            plainSz = wc_RsaSSL_Verify(sig, sigSz, digest, digestSz, key);
+            wc_FreeRsaKey(key);
+
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(digest, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            XFREE(key,    NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+            if (plainSz < 0)
+                return plainSz;
+        }
+    }
+
+    return 0;
+}
+
+
+/* create ASN.1 fomatted RecipientInfo structure, returns sequence size */
+WOLFSSL_LOCAL int wc_CreateRecipientInfo(const byte* cert, word32 certSz,
+                                     int keyEncAlgo, int blockKeySz,
+                                     RNG* rng, byte* contentKeyPlain,
+                                     byte* contentKeyEnc,
+                                     int* keyEncSz, byte* out, word32 outSz)
+{
+    word32 idx = 0;
+    int ret = 0, totalSz = 0;
+    int verSz, issuerSz, snSz, keyEncAlgSz;
+    int issuerSeqSz, recipSeqSz, issuerSerialSeqSz;
+    int encKeyOctetStrSz;
+
+    byte ver[MAX_VERSION_SZ];
+    byte issuerSerialSeq[MAX_SEQ_SZ];
+    byte recipSeq[MAX_SEQ_SZ];
+    byte issuerSeq[MAX_SEQ_SZ];
+    byte encKeyOctetStr[MAX_OCTET_STR_SZ];
+
+#ifdef WOLFSSL_SMALL_STACK
+    byte *serial;
+    byte *keyAlgArray;
+    
+    RsaKey* pubKey;
+    DecodedCert* decoded;
+
+    serial = (byte*)XMALLOC(MAX_SN_SZ, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    keyAlgArray = (byte*)XMALLOC(MAX_SN_SZ, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    decoded = (DecodedCert*)XMALLOC(sizeof(DecodedCert), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+
+    if (decoded == NULL || serial == NULL || keyAlgArray == NULL) {
+        if (serial)      XFREE(serial,      NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (keyAlgArray) XFREE(keyAlgArray, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (decoded)     XFREE(decoded,     NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        return MEMORY_E;
+    }
+    
+#else
+    byte serial[MAX_SN_SZ];
+    byte keyAlgArray[MAX_ALGO_SZ];
+    
+    RsaKey stack_pubKey;
+    RsaKey* pubKey = &stack_pubKey;
+    DecodedCert stack_decoded;
+    DecodedCert* decoded = &stack_decoded;
+#endif
+
+    InitDecodedCert(decoded, (byte*)cert, certSz, 0);
+    ret = ParseCert(decoded, CA_TYPE, NO_VERIFY, 0);
+    if (ret < 0) {
+        FreeDecodedCert(decoded);
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(serial,      NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(keyAlgArray, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(decoded,     NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return ret;
+    }
+
+    /* version */
+    verSz = SetMyVersion(0, ver, 0);
+
+    /* IssuerAndSerialNumber */
+    if (decoded->issuerRaw == NULL || decoded->issuerRawLen == 0) {
+        WOLFSSL_MSG("DecodedCert lacks raw issuer pointer and length");
+        FreeDecodedCert(decoded);
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(serial,      NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(keyAlgArray, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(decoded,     NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return -1;
+    }
+    issuerSz    = decoded->issuerRawLen;
+    issuerSeqSz = SetSequence(issuerSz, issuerSeq);
+
+    if (decoded->serialSz == 0) {
+        WOLFSSL_MSG("DecodedCert missing serial number");
+        FreeDecodedCert(decoded);
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(serial,      NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(keyAlgArray, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(decoded,     NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return -1;
+    }
+    snSz = SetSerialNumber(decoded->serial, decoded->serialSz, serial);
+
+    issuerSerialSeqSz = SetSequence(issuerSeqSz + issuerSz + snSz,
+                                    issuerSerialSeq);
+
+    /* KeyEncryptionAlgorithmIdentifier, only support RSA now */
+    if (keyEncAlgo != RSAk) {
+        FreeDecodedCert(decoded);
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(serial,      NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(keyAlgArray, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(decoded,     NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return ALGO_ID_E;
+    }
+
+    keyEncAlgSz = SetAlgoID(keyEncAlgo, keyAlgArray, keyType, 0);
+    if (keyEncAlgSz == 0) {
+        FreeDecodedCert(decoded);
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(serial,      NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(keyAlgArray, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(decoded,     NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return BAD_FUNC_ARG;
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    pubKey = (RsaKey*)XMALLOC(sizeof(RsaKey), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (pubKey == NULL) {
+        FreeDecodedCert(decoded);
+        XFREE(serial,      NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(keyAlgArray, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(decoded,     NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        return MEMORY_E;
+    }
+#endif
+
+    /* EncryptedKey */
+    ret = wc_InitRsaKey(pubKey, 0);
+    if (ret != 0) {
+        FreeDecodedCert(decoded);
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(pubKey,      NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(serial,      NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(keyAlgArray, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(decoded,     NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return ret;
+    }
+
+    if (wc_RsaPublicKeyDecode(decoded->publicKey, &idx, pubKey,
+                           decoded->pubKeySize) < 0) {
+        WOLFSSL_MSG("ASN RSA key decode error");
+        wc_FreeRsaKey(pubKey);
+        FreeDecodedCert(decoded);
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(pubKey,      NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(serial,      NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(keyAlgArray, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(decoded,     NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return PUBLIC_KEY_E;
+    }
+
+    *keyEncSz = wc_RsaPublicEncrypt(contentKeyPlain, blockKeySz, contentKeyEnc,
+                                 MAX_ENCRYPTED_KEY_SZ, pubKey, rng);
+    wc_FreeRsaKey(pubKey);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(pubKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    if (*keyEncSz < 0) {
+        WOLFSSL_MSG("RSA Public Encrypt failed");
+        FreeDecodedCert(decoded);
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(serial,      NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(keyAlgArray, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(decoded,     NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return *keyEncSz;
+    }
+
+    encKeyOctetStrSz = SetOctetString(*keyEncSz, encKeyOctetStr);
+
+    /* RecipientInfo */
+    recipSeqSz = SetSequence(verSz + issuerSerialSeqSz + issuerSeqSz +
+                             issuerSz + snSz + keyEncAlgSz + encKeyOctetStrSz +
+                             *keyEncSz, recipSeq);
+
+    if (recipSeqSz + verSz + issuerSerialSeqSz + issuerSeqSz + snSz +
+        keyEncAlgSz + encKeyOctetStrSz + *keyEncSz > (int)outSz) {
+        WOLFSSL_MSG("RecipientInfo output buffer too small");
+        FreeDecodedCert(decoded);
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(serial,      NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(keyAlgArray, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(decoded,     NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return BUFFER_E;
+    }
+
+    XMEMCPY(out + totalSz, recipSeq, recipSeqSz);
+    totalSz += recipSeqSz;
+    XMEMCPY(out + totalSz, ver, verSz);
+    totalSz += verSz;
+    XMEMCPY(out + totalSz, issuerSerialSeq, issuerSerialSeqSz);
+    totalSz += issuerSerialSeqSz;
+    XMEMCPY(out + totalSz, issuerSeq, issuerSeqSz);
+    totalSz += issuerSeqSz;
+    XMEMCPY(out + totalSz, decoded->issuerRaw, issuerSz);
+    totalSz += issuerSz;
+    XMEMCPY(out + totalSz, serial, snSz);
+    totalSz += snSz;
+    XMEMCPY(out + totalSz, keyAlgArray, keyEncAlgSz);
+    totalSz += keyEncAlgSz;
+    XMEMCPY(out + totalSz, encKeyOctetStr, encKeyOctetStrSz);
+    totalSz += encKeyOctetStrSz;
+    XMEMCPY(out + totalSz, contentKeyEnc, *keyEncSz);
+    totalSz += *keyEncSz;
+
+    FreeDecodedCert(decoded);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(serial,      NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(keyAlgArray, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(decoded,     NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return totalSz;
+}
+
+
+/* build PKCS#7 envelopedData content type, return enveloped size */
+int wc_PKCS7_EncodeEnvelopedData(PKCS7* pkcs7, byte* output, word32 outputSz)
+{
+    int i, ret = 0, idx = 0;
+    int totalSz = 0, padSz = 0, desOutSz = 0;
+
+    int contentInfoSeqSz, outerContentTypeSz, outerContentSz;
+    byte contentInfoSeq[MAX_SEQ_SZ];
+    byte outerContentType[MAX_ALGO_SZ];
+    byte outerContent[MAX_SEQ_SZ];
+
+    int envDataSeqSz, verSz;
+    byte envDataSeq[MAX_SEQ_SZ];
+    byte ver[MAX_VERSION_SZ];
+
+    RNG rng;
+    int contentKeyEncSz, blockKeySz;
+    int dynamicFlag = 0;
+    byte contentKeyPlain[MAX_CONTENT_KEY_LEN];
+#ifdef WOLFSSL_SMALL_STACK
+    byte* contentKeyEnc;
+#else
+    byte contentKeyEnc[MAX_ENCRYPTED_KEY_SZ];
+#endif
+    byte* plain;
+    byte* encryptedContent;
+
+    int recipSz, recipSetSz;
+#ifdef WOLFSSL_SMALL_STACK
+    byte* recip;
+#else
+    byte recip[MAX_RECIP_SZ];
+#endif
+    byte recipSet[MAX_SET_SZ];
+
+    int encContentOctetSz, encContentSeqSz, contentTypeSz;
+    int contentEncAlgoSz, ivOctetStringSz;
+    byte encContentSeq[MAX_SEQ_SZ];
+    byte contentType[MAX_ALGO_SZ];
+    byte contentEncAlgo[MAX_ALGO_SZ];
+    byte tmpIv[DES_BLOCK_SIZE];
+    byte ivOctetString[MAX_OCTET_STR_SZ];
+    byte encContentOctet[MAX_OCTET_STR_SZ];
+
+    if (pkcs7 == NULL || pkcs7->content == NULL || pkcs7->contentSz == 0 ||
+        pkcs7->encryptOID == 0 || pkcs7->singleCert == NULL)
+        return BAD_FUNC_ARG;
+
+    if (output == NULL || outputSz == 0)
+        return BAD_FUNC_ARG;
+
+    /* PKCS#7 only supports DES, 3DES for now */
+    switch (pkcs7->encryptOID) {
+        case DESb:
+            blockKeySz = DES_KEYLEN;
+            break;
+
+        case DES3b:
+            blockKeySz = DES3_KEYLEN;
+            break;
+
+        default:
+            WOLFSSL_MSG("Unsupported content cipher type");
+            return ALGO_ID_E;
+    };
+
+    /* outer content type */
+    outerContentTypeSz = wc_SetContentType(ENVELOPED_DATA, outerContentType);
+
+    /* version, defined as 0 in RFC 2315 */
+    verSz = SetMyVersion(0, ver, 0);
+
+    /* generate random content encryption key */
+    ret = wc_InitRng(&rng);
+    if (ret != 0)
+        return ret;
+
+    ret = wc_RNG_GenerateBlock(&rng, contentKeyPlain, blockKeySz);
+    if (ret != 0) {
+        wc_FreeRng(&rng);
+        return ret;
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    recip         = (byte*)XMALLOC(MAX_RECIP_SZ, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    contentKeyEnc = (byte*)XMALLOC(MAX_ENCRYPTED_KEY_SZ, NULL, 
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+    if (contentKeyEnc == NULL || recip == NULL) {
+        if (recip)         XFREE(recip,         NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (contentKeyEnc) XFREE(contentKeyEnc, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        wc_FreeRng(&rng);
+        return MEMORY_E;
+    }
+    
+#endif
+
+    /* build RecipientInfo, only handle 1 for now */
+    recipSz = wc_CreateRecipientInfo(pkcs7->singleCert, pkcs7->singleCertSz, RSAk,
+                                  blockKeySz, &rng, contentKeyPlain,
+                                  contentKeyEnc, &contentKeyEncSz, recip,
+                                  MAX_RECIP_SZ);
+                                                                      
+    ForceZero(contentKeyEnc, MAX_ENCRYPTED_KEY_SZ);
+    
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(contentKeyEnc, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    if (recipSz < 0) {
+        WOLFSSL_MSG("Failed to create RecipientInfo");
+        wc_FreeRng(&rng);
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(recip, NULL, DYNAMMIC_TYPE_TMP_BUFFER);
+#endif
+        return recipSz;
+    }
+    recipSetSz = SetSet(recipSz, recipSet);
+
+    /* generate IV for block cipher */
+    ret = wc_RNG_GenerateBlock(&rng, tmpIv, DES_BLOCK_SIZE);
+    wc_FreeRng(&rng);
+    if (ret != 0) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(recip, NULL, DYNAMMIC_TYPE_TMP_BUFFER);
+#endif
+        return ret;
+    }
+
+    /* EncryptedContentInfo */
+    contentTypeSz = wc_SetContentType(pkcs7->contentOID, contentType);
+    if (contentTypeSz == 0) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(recip, NULL, DYNAMMIC_TYPE_TMP_BUFFER);
+#endif
+        return BAD_FUNC_ARG;
+    }
+
+    /* allocate encrypted content buffer, pad if necessary, PKCS#7 padding */
+    padSz = DES_BLOCK_SIZE - (pkcs7->contentSz % DES_BLOCK_SIZE);
+    desOutSz = pkcs7->contentSz + padSz;
+
+    if (padSz != 0) {
+        plain = (byte*)XMALLOC(desOutSz, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (plain == NULL) {
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(recip, NULL, DYNAMMIC_TYPE_TMP_BUFFER);
+#endif
+            return MEMORY_E;
+        }
+        XMEMCPY(plain, pkcs7->content, pkcs7->contentSz);
+        dynamicFlag = 1;
+
+        for (i = 0; i < padSz; i++) {
+            plain[pkcs7->contentSz + i] = padSz;
+        }
+
+    } else {
+        plain = pkcs7->content;
+        desOutSz = pkcs7->contentSz;
+    }
+
+    encryptedContent = (byte*)XMALLOC(desOutSz, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (encryptedContent == NULL) {
+        if (dynamicFlag)
+            XFREE(plain, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(recip, NULL, DYNAMMIC_TYPE_TMP_BUFFER);
+#endif
+        return MEMORY_E;
+    }
+
+    /* put together IV OCTET STRING */
+    ivOctetStringSz = SetOctetString(DES_BLOCK_SIZE, ivOctetString);
+
+    /* build up our ContentEncryptionAlgorithmIdentifier sequence,
+     * adding (ivOctetStringSz + DES_BLOCK_SIZE) for IV OCTET STRING */
+    contentEncAlgoSz = SetAlgoID(pkcs7->encryptOID, contentEncAlgo,
+                                 blkType, ivOctetStringSz + DES_BLOCK_SIZE);
+
+    if (contentEncAlgoSz == 0) {
+        XFREE(encryptedContent, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (dynamicFlag)
+            XFREE(plain, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(recip, NULL, DYNAMMIC_TYPE_TMP_BUFFER);
+#endif
+        return BAD_FUNC_ARG;
+    }
+
+    /* encrypt content */
+    if (pkcs7->encryptOID == DESb) {
+        Des des;
+
+        ret = wc_Des_SetKey(&des, contentKeyPlain, tmpIv, DES_ENCRYPTION);
+
+        if (ret == 0)
+            wc_Des_CbcEncrypt(&des, encryptedContent, plain, desOutSz);
+
+        if (ret != 0) {
+            XFREE(encryptedContent, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            if (dynamicFlag)
+                XFREE(plain, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(recip, NULL, DYNAMMIC_TYPE_TMP_BUFFER);
+#endif
+            return ret;
+        }
+    }
+    else if (pkcs7->encryptOID == DES3b) {
+        Des3 des3;
+
+        ret = wc_Des3_SetKey(&des3, contentKeyPlain, tmpIv, DES_ENCRYPTION);
+
+        if (ret == 0)
+            ret = wc_Des3_CbcEncrypt(&des3, encryptedContent, plain, desOutSz);
+
+        if (ret != 0) {
+            XFREE(encryptedContent, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            if (dynamicFlag)
+                XFREE(plain, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(recip, NULL, DYNAMMIC_TYPE_TMP_BUFFER);
+#endif
+            return ret;
+        }
+    }
+
+    encContentOctetSz = SetImplicit(ASN_OCTET_STRING, 0,
+                                    desOutSz, encContentOctet);
+
+    encContentSeqSz = SetSequence(contentTypeSz + contentEncAlgoSz +
+                                  ivOctetStringSz + DES_BLOCK_SIZE +
+                                  encContentOctetSz + desOutSz, encContentSeq);
+
+    /* keep track of sizes for outer wrapper layering */
+    totalSz = verSz + recipSetSz + recipSz + encContentSeqSz + contentTypeSz +
+              contentEncAlgoSz + ivOctetStringSz + DES_BLOCK_SIZE +
+              encContentOctetSz + desOutSz;
+
+    /* EnvelopedData */
+    envDataSeqSz = SetSequence(totalSz, envDataSeq);
+    totalSz += envDataSeqSz;
+
+    /* outer content */
+    outerContentSz = SetExplicit(0, totalSz, outerContent);
+    totalSz += outerContentTypeSz;
+    totalSz += outerContentSz;
+
+    /* ContentInfo */
+    contentInfoSeqSz = SetSequence(totalSz, contentInfoSeq);
+    totalSz += contentInfoSeqSz;
+
+    if (totalSz > (int)outputSz) {
+        WOLFSSL_MSG("Pkcs7_encrypt output buffer too small");
+        XFREE(encryptedContent, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (dynamicFlag)
+            XFREE(plain, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(recip, NULL, DYNAMMIC_TYPE_TMP_BUFFER);
+#endif
+        return BUFFER_E;
+    }
+
+    XMEMCPY(output + idx, contentInfoSeq, contentInfoSeqSz);
+    idx += contentInfoSeqSz;
+    XMEMCPY(output + idx, outerContentType, outerContentTypeSz);
+    idx += outerContentTypeSz;
+    XMEMCPY(output + idx, outerContent, outerContentSz);
+    idx += outerContentSz;
+    XMEMCPY(output + idx, envDataSeq, envDataSeqSz);
+    idx += envDataSeqSz;
+    XMEMCPY(output + idx, ver, verSz);
+    idx += verSz;
+    XMEMCPY(output + idx, recipSet, recipSetSz);
+    idx += recipSetSz;
+    XMEMCPY(output + idx, recip, recipSz);
+    idx += recipSz;
+    XMEMCPY(output + idx, encContentSeq, encContentSeqSz);
+    idx += encContentSeqSz;
+    XMEMCPY(output + idx, contentType, contentTypeSz);
+    idx += contentTypeSz;
+    XMEMCPY(output + idx, contentEncAlgo, contentEncAlgoSz);
+    idx += contentEncAlgoSz;
+    XMEMCPY(output + idx, ivOctetString, ivOctetStringSz);
+    idx += ivOctetStringSz;
+    XMEMCPY(output + idx, tmpIv, DES_BLOCK_SIZE);
+    idx += DES_BLOCK_SIZE;
+    XMEMCPY(output + idx, encContentOctet, encContentOctetSz);
+    idx += encContentOctetSz;
+    XMEMCPY(output + idx, encryptedContent, desOutSz);
+    idx += desOutSz;
+
+    ForceZero(contentKeyPlain, MAX_CONTENT_KEY_LEN);
+
+    if (dynamicFlag)
+        XFREE(plain, NULL, DYNAMMIC_TYPE_TMP_BUFFER);
+    XFREE(encryptedContent, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(recip, NULL, DYNAMMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return idx;
+}
+
+/* unwrap and decrypt PKCS#7 envelopedData object, return decoded size */
+WOLFSSL_API int wc_PKCS7_DecodeEnvelopedData(PKCS7* pkcs7, byte* pkiMsg,
+                                         word32 pkiMsgSz, byte* output,
+                                         word32 outputSz)
+{
+    int recipFound = 0;
+    int ret, version, length;
+    word32 savedIdx = 0, idx = 0;
+    word32 contentType, encOID;
+    byte   issuerHash[SHA_DIGEST_SIZE];
+
+    int encryptedKeySz, keySz;
+    byte tmpIv[DES_BLOCK_SIZE];
+    byte* decryptedKey = NULL;
+
+#ifdef WOLFSSL_SMALL_STACK
+    mp_int* serialNum;
+    byte* encryptedKey;
+    RsaKey* privKey;
+#else
+    mp_int stack_serialNum;
+    mp_int* serialNum = &stack_serialNum;
+    byte encryptedKey[MAX_ENCRYPTED_KEY_SZ];
+    
+    RsaKey stack_privKey;
+    RsaKey* privKey = &stack_privKey;
+#endif
+    int encryptedContentSz;
+    byte padLen;
+    byte* encryptedContent = NULL;
+
+    if (pkcs7 == NULL || pkcs7->singleCert == NULL ||
+        pkcs7->singleCertSz == 0 || pkcs7->privateKey == NULL ||
+        pkcs7->privateKeySz == 0)
+        return BAD_FUNC_ARG;
+
+    if (pkiMsg == NULL || pkiMsgSz == 0 ||
+        output == NULL || outputSz == 0)
+        return BAD_FUNC_ARG;
+
+    /* read past ContentInfo, verify type is envelopedData */
+    if (GetSequence(pkiMsg, &idx, &length, pkiMsgSz) < 0)
+        return ASN_PARSE_E;
+
+    if (wc_GetContentType(pkiMsg, &idx, &contentType, pkiMsgSz) < 0)
+        return ASN_PARSE_E;
+
+    if (contentType != ENVELOPED_DATA) {
+        WOLFSSL_MSG("PKCS#7 input not of type EnvelopedData");
+        return PKCS7_OID_E;
+    }
+
+    if (pkiMsg[idx++] != (ASN_CONSTRUCTED | ASN_CONTEXT_SPECIFIC | 0))
+        return ASN_PARSE_E;
+
+    if (GetLength(pkiMsg, &idx, &length, pkiMsgSz) < 0)
+        return ASN_PARSE_E;
+
+    /* remove EnvelopedData and version */
+    if (GetSequence(pkiMsg, &idx, &length, pkiMsgSz) < 0)
+        return ASN_PARSE_E;
+
+    if (GetMyVersion(pkiMsg, &idx, &version) < 0)
+        return ASN_PARSE_E;
+
+    if (version != 0) {
+        WOLFSSL_MSG("PKCS#7 envelopedData needs to be of version 0");
+        return ASN_VERSION_E;
+    }
+
+    /* walk through RecipientInfo set, find correct recipient */
+    if (GetSet(pkiMsg, &idx, &length, pkiMsgSz) < 0)
+        return ASN_PARSE_E;
+    
+#ifdef WOLFSSL_SMALL_STACK
+    encryptedKey = (byte*)XMALLOC(MAX_ENCRYPTED_KEY_SZ, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+    if (encryptedKey == NULL)
+        return MEMORY_E;
+#endif
+    
+    savedIdx = idx;
+    recipFound = 0;
+
+    /* when looking for next recipient, use first sequence and version to
+     * indicate there is another, if not, move on */
+    while(recipFound == 0) {
+
+        /* remove RecipientInfo, if we don't have a SEQUENCE, back up idx to
+         * last good saved one */
+        if (GetSequence(pkiMsg, &idx, &length, pkiMsgSz) < 0) {
+            idx = savedIdx;
+            break;
+        }
+
+        if (GetMyVersion(pkiMsg, &idx, &version) < 0) {
+            idx = savedIdx;
+            break;
+        }
+
+        if (version != 0) {
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return ASN_VERSION_E;
+        }
+        
+        /* remove IssuerAndSerialNumber */
+        if (GetSequence(pkiMsg, &idx, &length, pkiMsgSz) < 0) {
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return ASN_PARSE_E;
+        }
+        
+        if (GetNameHash(pkiMsg, &idx, issuerHash, pkiMsgSz) < 0) {
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return ASN_PARSE_E;
+        }
+        
+        /* if we found correct recipient, issuer hashes will match */
+        if (XMEMCMP(issuerHash, pkcs7->issuerHash, SHA_DIGEST_SIZE) == 0) {
+            recipFound = 1;
+        }
+        
+#ifdef WOLFSSL_SMALL_STACK
+        serialNum = (mp_int*)XMALLOC(sizeof(mp_int), NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+        if (serialNum == NULL) {
+            XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            return MEMORY_E;
+        }
+#endif
+        
+        if (GetInt(serialNum, pkiMsg, &idx, pkiMsgSz) < 0) {
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            XFREE(serialNum,    NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return ASN_PARSE_E;
+        }
+        
+        mp_clear(serialNum);
+        
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(serialNum, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        
+        if (GetAlgoId(pkiMsg, &idx, &encOID, pkiMsgSz) < 0) {
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return ASN_PARSE_E;
+        }
+        
+        /* key encryption algorithm must be RSA for now */
+        if (encOID != RSAk) {
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return ALGO_ID_E;
+        }
+        
+        /* read encryptedKey */
+        if (pkiMsg[idx++] != ASN_OCTET_STRING) {
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return ASN_PARSE_E;
+        }
+        
+        if (GetLength(pkiMsg, &idx, &encryptedKeySz, pkiMsgSz) < 0) {
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return ASN_PARSE_E;
+        }
+          
+        if (recipFound == 1)
+            XMEMCPY(encryptedKey, &pkiMsg[idx], encryptedKeySz);
+        idx += encryptedKeySz;
+
+        /* update good idx */
+        savedIdx = idx;
+    }
+
+    if (recipFound == 0) {
+        WOLFSSL_MSG("No recipient found in envelopedData that matches input");
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return PKCS7_RECIP_E;
+    }
+
+    /* remove EncryptedContentInfo */
+    if (GetSequence(pkiMsg, &idx, &length, pkiMsgSz) < 0) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return ASN_PARSE_E;
+    }
+    
+    if (wc_GetContentType(pkiMsg, &idx, &contentType, pkiMsgSz) < 0) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return ASN_PARSE_E;
+    }
+
+    if (GetAlgoId(pkiMsg, &idx, &encOID, pkiMsgSz) < 0) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return ASN_PARSE_E;
+    }
+    
+    /* get block cipher IV, stored in OPTIONAL parameter of AlgoID */
+    if (pkiMsg[idx++] != ASN_OCTET_STRING) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return ASN_PARSE_E;
+    }
+    
+    if (GetLength(pkiMsg, &idx, &length, pkiMsgSz) < 0) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return ASN_PARSE_E;
+    }
+    
+    if (length != DES_BLOCK_SIZE) {
+        WOLFSSL_MSG("Incorrect IV length, must be of DES_BLOCK_SIZE");
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return ASN_PARSE_E;
+    }
+
+    XMEMCPY(tmpIv, &pkiMsg[idx], length);
+    idx += length;
+
+    /* read encryptedContent, cont[0] */
+    if (pkiMsg[idx++] != (ASN_CONTEXT_SPECIFIC | 0)) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return ASN_PARSE_E;
+    }
+
+    if (GetLength(pkiMsg, &idx, &encryptedContentSz, pkiMsgSz) < 0) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return ASN_PARSE_E;
+    }
+    
+    encryptedContent = (byte*)XMALLOC(encryptedContentSz, NULL,
+                                                       DYNAMIC_TYPE_TMP_BUFFER);
+    if (encryptedContent == NULL) {
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return MEMORY_E;
+    }
+
+    XMEMCPY(encryptedContent, &pkiMsg[idx], encryptedContentSz);
+
+    /* load private key */
+#ifdef WOLFSSL_SMALL_STACK
+    privKey = (RsaKey*)XMALLOC(sizeof(RsaKey), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (privKey == NULL) {
+        XFREE(encryptedContent, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(encryptedKey,     NULL, DYNAMIC_TYPE_TMP_BUFFER);        return MEMORY_E;
+    }
+#endif
+
+    ret = wc_InitRsaKey(privKey, 0);
+    if (ret != 0) {
+        XFREE(encryptedContent, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(privKey,      NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return ret;
+    }
+
+    idx = 0;
+
+    ret = wc_RsaPrivateKeyDecode(pkcs7->privateKey, &idx, privKey,
+                              pkcs7->privateKeySz);
+    if (ret != 0) {
+        WOLFSSL_MSG("Failed to decode RSA private key");
+        XFREE(encryptedContent, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(privKey,      NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return ret;
+    }
+
+    /* decrypt encryptedKey */
+    keySz = wc_RsaPrivateDecryptInline(encryptedKey, encryptedKeySz,
+                                    &decryptedKey, privKey);
+    wc_FreeRsaKey(privKey);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(privKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    if (keySz <= 0) {
+        XFREE(encryptedContent, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return keySz;
+    }
+
+    /* decrypt encryptedContent */
+    if (encOID == DESb) {
+        Des des;
+        ret = wc_Des_SetKey(&des, decryptedKey, tmpIv, DES_DECRYPTION);
+
+        if (ret == 0)
+            wc_Des_CbcDecrypt(&des, encryptedContent, encryptedContent,
+                                 encryptedContentSz);
+
+        if (ret != 0) {
+            XFREE(encryptedContent, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return ret;
+        }
+    }
+    else if (encOID == DES3b) {
+        Des3 des;
+        ret = wc_Des3_SetKey(&des, decryptedKey, tmpIv, DES_DECRYPTION);
+        if (ret == 0)
+            ret = wc_Des3_CbcDecrypt(&des, encryptedContent, encryptedContent,
+                                  encryptedContentSz);
+
+        if (ret != 0) {
+            XFREE(encryptedContent, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return ret;
+        }
+    } else {
+        WOLFSSL_MSG("Unsupported content encryption OID type");
+        XFREE(encryptedContent, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#ifdef WOLFSSL_SMALL_STACK
+        XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+        return ALGO_ID_E;
+    }
+
+    padLen = encryptedContent[encryptedContentSz-1];
+
+    /* copy plaintext to output */
+    XMEMCPY(output, encryptedContent, encryptedContentSz - padLen);
+
+    /* free memory, zero out keys */
+    ForceZero(encryptedKey, MAX_ENCRYPTED_KEY_SZ);
+    ForceZero(encryptedContent, encryptedContentSz);
+    XFREE(encryptedContent, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(encryptedKey, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+    
+    return encryptedContentSz - padLen;
+}
+
+
+#else  /* HAVE_PKCS7 */
+
+
+#ifdef _MSC_VER
+    /* 4206 warning for blank file */
+    #pragma warning(disable: 4206)
+#endif
+
+
+#endif /* HAVE_PKCS7 */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/poly1305.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/poly1305.c
new file mode 100644
index 0000000..3cc86e1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/poly1305.c
@@ -0,0 +1,554 @@
+/* poly1305.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ *
+ * Based off the public domain implementations by Andrew Moon 
+ * and Daniel J. Bernstein
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifdef HAVE_POLY1305
+#include 
+#include 
+#include 
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+#ifdef CHACHA_AEAD_TEST
+    #include 
+#endif
+
+#ifdef _MSC_VER
+    /* 4127 warning constant while(1)  */
+    #pragma warning(disable: 4127)
+#endif
+
+#if defined(POLY130564)
+	
+	#if defined(_MSC_VER)
+		#define POLY1305_NOINLINE __declspec(noinline)
+	#elif defined(__GNUC__)
+		#define POLY1305_NOINLINE __attribute__((noinline))
+	#else
+		#define POLY1305_NOINLINE
+	#endif
+	
+	#if defined(_MSC_VER)
+	    #include 
+		
+	    typedef struct word128 {
+			word64 lo;
+			word64 hi;
+		} word128;
+	
+		#define MUL(out, x, y) out.lo = _umul128((x), (y), &out.hi)
+		#define ADD(out, in) { word64 t = out.lo; out.lo += in.lo;
+	                           out.hi += (out.lo < t) + in.hi; }
+		#define ADDLO(out, in) { word64 t = out.lo; out.lo += in;
+	                             out.hi += (out.lo < t); }
+		#define SHR(in, shift) (__shiftright128(in.lo, in.hi, (shift)))
+		#define LO(in) (in.lo)
+	
+	#elif defined(__GNUC__)
+		#if defined(__SIZEOF_INT128__)
+			typedef unsigned __int128 word128;
+		#else
+			typedef unsigned word128 __attribute__((mode(TI)));
+		#endif
+	
+		#define MUL(out, x, y) out = ((word128)x * y)
+		#define ADD(out, in) out += in
+		#define ADDLO(out, in) out += in
+		#define SHR(in, shift) (word64)(in >> (shift))
+		#define LO(in) (word64)(in)
+	#endif
+	
+	static word64 U8TO64(const byte* p) {
+		return
+			(((word64)(p[0] & 0xff)      ) |
+		     ((word64)(p[1] & 0xff) <<  8) |
+	         ((word64)(p[2] & 0xff) << 16) |
+	         ((word64)(p[3] & 0xff) << 24) |
+			 ((word64)(p[4] & 0xff) << 32) |
+			 ((word64)(p[5] & 0xff) << 40) |
+			 ((word64)(p[6] & 0xff) << 48) |
+			 ((word64)(p[7] & 0xff) << 56));
+	}
+	
+	static void U64TO8(byte* p, word64 v) {
+		p[0] = (v      ) & 0xff;
+		p[1] = (v >>  8) & 0xff;
+		p[2] = (v >> 16) & 0xff;
+		p[3] = (v >> 24) & 0xff;
+		p[4] = (v >> 32) & 0xff;
+		p[5] = (v >> 40) & 0xff;
+		p[6] = (v >> 48) & 0xff;
+		p[7] = (v >> 56) & 0xff;
+	}
+
+#else /* if not 64 bit then use 32 bit */
+	
+	static word32 U8TO32(const byte *p) {
+		return
+			(((word32)(p[0] & 0xff)      ) |
+		     ((word32)(p[1] & 0xff) <<  8) |
+	         ((word32)(p[2] & 0xff) << 16) |
+	         ((word32)(p[3] & 0xff) << 24));
+	}
+	
+	static void U32TO8(byte *p, word32 v) {
+		p[0] = (v      ) & 0xff;
+		p[1] = (v >>  8) & 0xff;
+		p[2] = (v >> 16) & 0xff;
+		p[3] = (v >> 24) & 0xff;
+	}
+#endif
+
+static void poly1305_blocks(Poly1305* ctx, const unsigned char *m,
+                            size_t bytes) {
+
+#ifdef POLY130564
+
+	const word64 hibit = (ctx->final) ? 0 : ((word64)1 << 40); /* 1 << 128 */
+	word64 r0,r1,r2;
+	word64 s1,s2;
+	word64 h0,h1,h2;
+	word64 c;
+	word128 d0,d1,d2,d;
+
+#else
+
+    const word32 hibit = (ctx->final) ? 0 : (1 << 24); /* 1 << 128 */
+	word32 r0,r1,r2,r3,r4;
+	word32 s1,s2,s3,s4;
+	word32 h0,h1,h2,h3,h4;
+	word64 d0,d1,d2,d3,d4;
+	word32 c;
+
+#endif
+
+#ifdef POLY130564
+
+    r0 = ctx->r[0];
+	r1 = ctx->r[1];
+	r2 = ctx->r[2];
+
+	h0 = ctx->h[0];
+	h1 = ctx->h[1];
+	h2 = ctx->h[2];
+
+	s1 = r1 * (5 << 2);
+	s2 = r2 * (5 << 2);
+
+	while (bytes >= POLY1305_BLOCK_SIZE) {
+		word64 t0,t1;
+
+		/* h += m[i] */
+		t0 = U8TO64(&m[0]);
+		t1 = U8TO64(&m[8]);
+
+		h0 += (( t0                    ) & 0xfffffffffff);
+		h1 += (((t0 >> 44) | (t1 << 20)) & 0xfffffffffff);
+		h2 += (((t1 >> 24)             ) & 0x3ffffffffff) | hibit;
+
+		/* h *= r */
+		MUL(d0, h0, r0); MUL(d, h1, s2); ADD(d0, d); MUL(d, h2, s1); ADD(d0, d);
+		MUL(d1, h0, r1); MUL(d, h1, r0); ADD(d1, d); MUL(d, h2, s2); ADD(d1, d);
+		MUL(d2, h0, r2); MUL(d, h1, r1); ADD(d2, d); MUL(d, h2, r0); ADD(d2, d);
+
+		/* (partial) h %= p */
+		              c = SHR(d0, 44); h0 = LO(d0) & 0xfffffffffff;
+		ADDLO(d1, c); c = SHR(d1, 44); h1 = LO(d1) & 0xfffffffffff;
+		ADDLO(d2, c); c = SHR(d2, 42); h2 = LO(d2) & 0x3ffffffffff;
+		h0  += c * 5; c = (h0 >> 44);  h0 =    h0  & 0xfffffffffff;
+		h1  += c;
+
+		m += POLY1305_BLOCK_SIZE;
+		bytes -= POLY1305_BLOCK_SIZE;
+	}
+
+	ctx->h[0] = h0;
+	ctx->h[1] = h1;
+	ctx->h[2] = h2;
+
+#else /* if not 64 bit then use 32 bit */
+   
+	r0 = ctx->r[0];
+	r1 = ctx->r[1];
+	r2 = ctx->r[2];
+	r3 = ctx->r[3];
+	r4 = ctx->r[4];
+
+	s1 = r1 * 5;
+	s2 = r2 * 5;
+	s3 = r3 * 5;
+	s4 = r4 * 5;
+
+	h0 = ctx->h[0];
+	h1 = ctx->h[1];
+	h2 = ctx->h[2];
+	h3 = ctx->h[3];
+	h4 = ctx->h[4];
+
+	while (bytes >= POLY1305_BLOCK_SIZE) {
+		/* h += m[i] */
+		h0 += (U8TO32(m+ 0)     ) & 0x3ffffff;
+		h1 += (U8TO32(m+ 3) >> 2) & 0x3ffffff;
+		h2 += (U8TO32(m+ 6) >> 4) & 0x3ffffff;
+		h3 += (U8TO32(m+ 9) >> 6) & 0x3ffffff;
+		h4 += (U8TO32(m+12) >> 8) | hibit;
+
+		/* h *= r */
+		d0 = ((word64)h0 * r0) + ((word64)h1 * s4) + ((word64)h2 * s3) +
+             ((word64)h3 * s2) + ((word64)h4 * s1);
+		d1 = ((word64)h0 * r1) + ((word64)h1 * r0) + ((word64)h2 * s4) +
+             ((word64)h3 * s3) + ((word64)h4 * s2);
+		d2 = ((word64)h0 * r2) + ((word64)h1 * r1) + ((word64)h2 * r0) +
+             ((word64)h3 * s4) + ((word64)h4 * s3);
+		d3 = ((word64)h0 * r3) + ((word64)h1 * r2) + ((word64)h2 * r1) +
+             ((word64)h3 * r0) + ((word64)h4 * s4);
+		d4 = ((word64)h0 * r4) + ((word64)h1 * r3) + ((word64)h2 * r2) +
+             ((word64)h3 * r1) + ((word64)h4 * r0);
+
+		/* (partial) h %= p */
+		              c = (word32)(d0 >> 26); h0 = (word32)d0 & 0x3ffffff;
+		d1 += c;      c = (word32)(d1 >> 26); h1 = (word32)d1 & 0x3ffffff;
+		d2 += c;      c = (word32)(d2 >> 26); h2 = (word32)d2 & 0x3ffffff;
+		d3 += c;      c = (word32)(d3 >> 26); h3 = (word32)d3 & 0x3ffffff;
+		d4 += c;      c = (word32)(d4 >> 26); h4 = (word32)d4 & 0x3ffffff;
+		h0 += c * 5;  c =  (h0 >> 26); h0 =                h0 & 0x3ffffff;
+		h1 += c;
+
+		m += POLY1305_BLOCK_SIZE;
+		bytes -= POLY1305_BLOCK_SIZE;
+	}
+
+	ctx->h[0] = h0;
+	ctx->h[1] = h1;
+	ctx->h[2] = h2;
+	ctx->h[3] = h3;
+	ctx->h[4] = h4;
+
+#endif /* end of 64 bit cpu blocks or 32 bit cpu */
+}
+
+
+int wc_Poly1305SetKey(Poly1305* ctx, const byte* key, word32 keySz) {
+
+#if defined(POLY130564)
+    word64 t0,t1;
+#endif
+
+#ifdef CHACHA_AEAD_TEST
+    word32 k;
+    printf("Poly key used:\n");
+    for (k = 0; k < keySz; k++) {
+        printf("%02x", key[k]);
+        if ((k+1) % 8 == 0)
+            printf("\n");
+    }
+	printf("\n");
+#endif
+
+    if (keySz != 32 || ctx == NULL)
+        return BAD_FUNC_ARG;
+
+#if defined(POLY130564)
+
+	/* r &= 0xffffffc0ffffffc0ffffffc0fffffff */
+	t0 = U8TO64(key + 0);
+	t1 = U8TO64(key + 8);
+
+	ctx->r[0] = ( t0                    ) & 0xffc0fffffff;
+	ctx->r[1] = ((t0 >> 44) | (t1 << 20)) & 0xfffffc0ffff;
+	ctx->r[2] = ((t1 >> 24)             ) & 0x00ffffffc0f;
+
+	/* h (accumulator) = 0 */
+	ctx->h[0] = 0;
+	ctx->h[1] = 0;
+	ctx->h[2] = 0;
+
+	/* save pad for later */
+	ctx->pad[0] = U8TO64(key + 16);
+	ctx->pad[1] = U8TO64(key + 24);
+
+#else /* if not 64 bit then use 32 bit */
+	
+    /* r &= 0xffffffc0ffffffc0ffffffc0fffffff */
+	ctx->r[0] = (U8TO32(key +  0)     ) & 0x3ffffff;
+	ctx->r[1] = (U8TO32(key +  3) >> 2) & 0x3ffff03;
+	ctx->r[2] = (U8TO32(key +  6) >> 4) & 0x3ffc0ff;
+	ctx->r[3] = (U8TO32(key +  9) >> 6) & 0x3f03fff;
+	ctx->r[4] = (U8TO32(key + 12) >> 8) & 0x00fffff;
+
+	/* h = 0 */
+	ctx->h[0] = 0;
+	ctx->h[1] = 0;
+	ctx->h[2] = 0;
+	ctx->h[3] = 0;
+	ctx->h[4] = 0;
+
+	/* save pad for later */
+	ctx->pad[0] = U8TO32(key + 16);
+	ctx->pad[1] = U8TO32(key + 20);
+	ctx->pad[2] = U8TO32(key + 24);
+	ctx->pad[3] = U8TO32(key + 28);
+
+#endif
+
+	ctx->leftover = 0;
+	ctx->final = 0;
+
+    return 0;
+}
+
+
+int wc_Poly1305Final(Poly1305* ctx, byte* mac) {
+
+#if defined(POLY130564)
+
+    word64 h0,h1,h2,c;
+	word64 g0,g1,g2;
+	word64 t0,t1;
+
+#else
+
+    word32 h0,h1,h2,h3,h4,c;
+	word32 g0,g1,g2,g3,g4;
+	word64 f;
+	word32 mask;
+
+#endif
+
+    if (ctx == NULL)
+        return BAD_FUNC_ARG;
+
+#if defined(POLY130564)
+
+	/* process the remaining block */
+	if (ctx->leftover) {
+		size_t i = ctx->leftover;
+		ctx->buffer[i] = 1;
+		for (i = i + 1; i < POLY1305_BLOCK_SIZE; i++)
+			ctx->buffer[i] = 0;
+		ctx->final = 1;
+		poly1305_blocks(ctx, ctx->buffer, POLY1305_BLOCK_SIZE);
+	}
+
+	/* fully carry h */
+	h0 = ctx->h[0];
+	h1 = ctx->h[1];
+	h2 = ctx->h[2];
+
+	             c = (h1 >> 44); h1 &= 0xfffffffffff;
+	h2 += c;     c = (h2 >> 42); h2 &= 0x3ffffffffff;
+	h0 += c * 5; c = (h0 >> 44); h0 &= 0xfffffffffff;
+	h1 += c;	 c = (h1 >> 44); h1 &= 0xfffffffffff;
+	h2 += c;     c = (h2 >> 42); h2 &= 0x3ffffffffff;
+	h0 += c * 5; c = (h0 >> 44); h0 &= 0xfffffffffff;
+	h1 += c;
+
+	/* compute h + -p */
+	g0 = h0 + 5; c = (g0 >> 44); g0 &= 0xfffffffffff;
+	g1 = h1 + c; c = (g1 >> 44); g1 &= 0xfffffffffff;
+	g2 = h2 + c - ((word64)1 << 42);
+
+	/* select h if h < p, or h + -p if h >= p */
+	c = (g2 >> ((sizeof(word64) * 8) - 1)) - 1;
+	g0 &= c;
+	g1 &= c;
+	g2 &= c;
+	c = ~c;
+	h0 = (h0 & c) | g0;
+	h1 = (h1 & c) | g1;
+	h2 = (h2 & c) | g2;
+
+	/* h = (h + pad) */
+	t0 = ctx->pad[0];
+	t1 = ctx->pad[1];
+
+	h0 += (( t0                    ) & 0xfffffffffff)    ;
+    c = (h0 >> 44); h0 &= 0xfffffffffff;
+	h1 += (((t0 >> 44) | (t1 << 20)) & 0xfffffffffff) + c;
+    c = (h1 >> 44); h1 &= 0xfffffffffff;
+	h2 += (((t1 >> 24)             ) & 0x3ffffffffff) + c;
+    h2 &= 0x3ffffffffff;
+
+	/* mac = h % (2^128) */
+	h0 = ((h0      ) | (h1 << 44));
+	h1 = ((h1 >> 20) | (h2 << 24));
+
+	U64TO8(mac + 0, h0);
+	U64TO8(mac + 8, h1);
+
+	/* zero out the state */
+	ctx->h[0] = 0;
+	ctx->h[1] = 0;
+	ctx->h[2] = 0;
+	ctx->r[0] = 0;
+	ctx->r[1] = 0;
+	ctx->r[2] = 0;
+	ctx->pad[0] = 0;
+	ctx->pad[1] = 0;
+
+#else /* if not 64 bit then use 32 bit */
+    
+	/* process the remaining block */
+	if (ctx->leftover) {
+		size_t i = ctx->leftover;
+		ctx->buffer[i++] = 1;
+		for (; i < POLY1305_BLOCK_SIZE; i++)
+			ctx->buffer[i] = 0;
+		ctx->final = 1;
+		poly1305_blocks(ctx, ctx->buffer, POLY1305_BLOCK_SIZE);
+	}
+
+	/* fully carry h */
+	h0 = ctx->h[0];
+	h1 = ctx->h[1];
+	h2 = ctx->h[2];
+	h3 = ctx->h[3];
+	h4 = ctx->h[4];
+
+	             c = h1 >> 26; h1 = h1 & 0x3ffffff;
+	h2 +=     c; c = h2 >> 26; h2 = h2 & 0x3ffffff;
+	h3 +=     c; c = h3 >> 26; h3 = h3 & 0x3ffffff;
+	h4 +=     c; c = h4 >> 26; h4 = h4 & 0x3ffffff;
+	h0 += c * 5; c = h0 >> 26; h0 = h0 & 0x3ffffff;
+	h1 +=     c;
+
+	/* compute h + -p */
+	g0 = h0 + 5; c = g0 >> 26; g0 &= 0x3ffffff;
+	g1 = h1 + c; c = g1 >> 26; g1 &= 0x3ffffff;
+	g2 = h2 + c; c = g2 >> 26; g2 &= 0x3ffffff;
+	g3 = h3 + c; c = g3 >> 26; g3 &= 0x3ffffff;
+	g4 = h4 + c - (1 << 26);
+
+	/* select h if h < p, or h + -p if h >= p */
+	mask = (g4 >> ((sizeof(word32) * 8) - 1)) - 1;
+	g0 &= mask;
+	g1 &= mask;
+	g2 &= mask;
+	g3 &= mask;
+	g4 &= mask;
+	mask = ~mask;
+	h0 = (h0 & mask) | g0;
+	h1 = (h1 & mask) | g1;
+	h2 = (h2 & mask) | g2;
+	h3 = (h3 & mask) | g3;
+	h4 = (h4 & mask) | g4;
+
+	/* h = h % (2^128) */
+	h0 = ((h0      ) | (h1 << 26)) & 0xffffffff;
+	h1 = ((h1 >>  6) | (h2 << 20)) & 0xffffffff;
+	h2 = ((h2 >> 12) | (h3 << 14)) & 0xffffffff;
+	h3 = ((h3 >> 18) | (h4 <<  8)) & 0xffffffff;
+
+	/* mac = (h + pad) % (2^128) */
+	f = (word64)h0 + ctx->pad[0]            ; h0 = (word32)f;
+	f = (word64)h1 + ctx->pad[1] + (f >> 32); h1 = (word32)f;
+	f = (word64)h2 + ctx->pad[2] + (f >> 32); h2 = (word32)f;
+	f = (word64)h3 + ctx->pad[3] + (f >> 32); h3 = (word32)f;
+
+	U32TO8(mac + 0, h0);
+	U32TO8(mac + 4, h1);
+	U32TO8(mac + 8, h2);
+	U32TO8(mac + 12, h3);
+
+	/* zero out the state */
+	ctx->h[0] = 0;
+	ctx->h[1] = 0;
+	ctx->h[2] = 0;
+	ctx->h[3] = 0;
+	ctx->h[4] = 0;
+	ctx->r[0] = 0;
+	ctx->r[1] = 0;
+	ctx->r[2] = 0;
+	ctx->r[3] = 0;
+	ctx->r[4] = 0;
+	ctx->pad[0] = 0;
+	ctx->pad[1] = 0;
+	ctx->pad[2] = 0;
+	ctx->pad[3] = 0;
+
+#endif
+
+    return 0;
+}
+
+
+int wc_Poly1305Update(Poly1305* ctx, const byte* m, word32 bytes) {
+
+	size_t i;
+
+#ifdef CHACHA_AEAD_TEST
+    word32 k;
+    printf("Raw input to poly:\n");
+    for (k = 0; k < bytes; k++) {
+        printf("%02x", m[k]);
+        if ((k+1) % 16 == 0)
+            printf("\n");
+    }
+	printf("\n");
+#endif
+    
+    if (ctx == NULL)
+        return BAD_FUNC_ARG;
+
+	/* handle leftover */
+	if (ctx->leftover) {
+		size_t want = (POLY1305_BLOCK_SIZE - ctx->leftover);
+		if (want > bytes)
+			want = bytes;
+		for (i = 0; i < want; i++)
+			ctx->buffer[ctx->leftover + i] = m[i];
+		bytes -= want;
+		m += want;
+		ctx->leftover += want;
+		if (ctx->leftover < POLY1305_BLOCK_SIZE)
+			return 0;
+		poly1305_blocks(ctx, ctx->buffer, POLY1305_BLOCK_SIZE);
+		ctx->leftover = 0;
+	}
+
+	/* process full blocks */
+	if (bytes >= POLY1305_BLOCK_SIZE) {
+		size_t want = (bytes & ~(POLY1305_BLOCK_SIZE - 1));
+		poly1305_blocks(ctx, m, want);
+		m += want;
+		bytes -= want;
+	}
+
+	/* store leftover */
+	if (bytes) {
+		for (i = 0; i < bytes; i++)
+			ctx->buffer[ctx->leftover + i] = m[i];
+		ctx->leftover += bytes;
+	}
+    return 0;
+}
+#endif /* HAVE_POLY1305 */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/port/pic32/pic32mz-hash.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/port/pic32/pic32mz-hash.c
new file mode 100644
index 0000000..c293afa
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/port/pic32/pic32mz-hash.c
@@ -0,0 +1,371 @@
+/* pic32mz-hash.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifdef WOLFSSL_PIC32MZ_HASH
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#if !defined(NO_MD5) && !defined(NO_SHA) && !defined(NO_SHA256)
+
+static uint8_t dataBuffer[PIC32MZ_MAX_BD][PIC32_BLOCK_SIZE] __attribute__((aligned (4), coherent));
+
+static void reset_engine(pic32mz_desc *desc, int algo)
+{
+    int i;
+    pic32mz_desc* uc_desc = KVA0_TO_KVA1(desc);
+
+    CECON = 1 << 6;
+    while (CECON);
+
+    /* Make sure everything is clear first before we make settings. */
+    XMEMSET((void *)&uc_desc->sa, 0, sizeof(uc_desc->sa));
+
+    /* Set up the security association */
+    uc_desc->sa.SA_CTRL.ALGO = algo ;
+    uc_desc->sa.SA_CTRL.LNC = 1;
+    uc_desc->sa.SA_CTRL.FB = 1;
+    uc_desc->sa.SA_CTRL.ENCTYPE = 1;
+    uc_desc->sa.SA_CTRL.LOADIV = 1;
+
+    /* Set up the buffer descriptor */
+    uc_desc->err = 0 ;
+    for (i = 0; i < PIC32MZ_MAX_BD; i++)
+    {
+        XMEMSET((void *)&uc_desc->bd[i], 0, sizeof(uc_desc->bd[i]));
+        uc_desc->bd[i].BD_CTRL.LAST_BD = 1;
+        uc_desc->bd[i].BD_CTRL.LIFM = 1;
+        uc_desc->bd[i].BD_CTRL.PKT_INT_EN = 1;
+        uc_desc->bd[i].SA_ADDR = KVA_TO_PA(&uc_desc->sa);
+        uc_desc->bd[i].SRCADDR = KVA_TO_PA(&dataBuffer[i]);
+        if (PIC32MZ_MAX_BD > i+1)
+            uc_desc->bd[i].NXTPTR = KVA_TO_PA(&uc_desc->bd[i+1]);
+        else
+            uc_desc->bd[i].NXTPTR = KVA_TO_PA(&uc_desc->bd[0]);
+        XMEMSET((void *)&dataBuffer[i], 0, PIC32_BLOCK_SIZE);
+    }
+    uc_desc->bd[0].BD_CTRL.SA_FETCH_EN = 1; // Fetch the security association on the first BD
+    desc->dbPtr = 0;
+    desc->currBd = 0;
+    desc->msgSize = 0;
+    desc->processed = 0;
+    CEBDPADDR = KVA_TO_PA(&(desc->bd[0]));
+
+    CEPOLLCON = 10;
+
+    CECON = 0x27;
+}
+
+#define PIC32MZ_IF_RAM(addr) (KVA_TO_PA(addr) < 0x80000)
+
+static void update_data_size(pic32mz_desc *desc, word32 msgSize)
+{
+    desc->msgSize = msgSize;
+}
+
+static void update_engine(pic32mz_desc *desc, const char *input, word32 len,
+                    word32 *hash)
+{
+   int total ;
+    pic32mz_desc    *uc_desc = KVA0_TO_KVA1(desc);
+
+    uc_desc->bd[desc->currBd].UPDPTR = KVA_TO_PA(hash);
+    // Add the data to the current buffer. If the buffer fills, start processing it
+    // and fill the next one.
+    while (len)
+    {
+        // If the engine is processing the current BD, spin.
+//        if (uc_desc->bd[desc->currBd].BD_CTRL.DESC_EN)
+//            continue;
+        if (desc->msgSize)
+        {
+            // If we've been given the message size, we can process along the
+            // way.
+            // Enable the current buffer descriptor if it is full.
+            if (desc->dbPtr >= PIC32_BLOCK_SIZE)
+            {
+                // Wrap up the buffer descriptor and enable it so the engine can process
+                uc_desc->bd[desc->currBd].MSGLEN = desc->msgSize;
+                uc_desc->bd[desc->currBd].BD_CTRL.BUFLEN = desc->dbPtr;
+                uc_desc->bd[desc->currBd].BD_CTRL.LAST_BD = 0;
+                uc_desc->bd[desc->currBd].BD_CTRL.LIFM = 0;
+                //SYS_DEVCON_DataCacheClean((word32)desc, sizeof(pic32mz_desc));
+                uc_desc->bd[desc->currBd].BD_CTRL.DESC_EN = 1;
+                // Move to the next buffer descriptor, or wrap around.
+                desc->currBd++;
+                if (desc->currBd >= PIC32MZ_MAX_BD)
+                    desc->currBd = 0;
+                // Wait until the engine has processed the new BD.
+                while (uc_desc->bd[desc->currBd].BD_CTRL.DESC_EN);
+                uc_desc->bd[desc->currBd].UPDPTR = KVA_TO_PA(hash);
+                desc->dbPtr = 0;
+            }
+            if (!PIC32MZ_IF_RAM(input)) // If we're inputting from flash, let the BD have the address and max the buffer size
+            {
+                uc_desc->bd[desc->currBd].SRCADDR = KVA_TO_PA(input);
+                total = (len > PIC32MZ_MAX_BLOCK ? PIC32MZ_MAX_BLOCK : len);
+                desc->dbPtr = total;
+                len -= total;
+                input += total;
+            }
+            else
+            {
+                if (len > PIC32_BLOCK_SIZE - desc->dbPtr)
+                {
+                    // We have more data than can be put in the buffer. Fill what we can.
+                    total = PIC32_BLOCK_SIZE - desc->dbPtr;
+                    XMEMCPY(&dataBuffer[desc->currBd][desc->dbPtr], input, total);
+                    len -= total;
+                    desc->dbPtr = PIC32_BLOCK_SIZE;
+                    input += total;
+                }
+                else
+                {
+                    // Fill up what we have, but don't turn on the engine.
+                    XMEMCPY(&dataBuffer[desc->currBd][desc->dbPtr], input, len);
+                    desc->dbPtr += len;
+                    len = 0;
+                }
+            }
+        }
+        else
+        {
+            // We have to buffer everything and keep track of how much has been
+            // added in order to get a total size. If the buffer fills, we move
+            // to the next one. If we try to add more when the last buffer is
+            // full, we error out.
+            if (desc->dbPtr == PIC32_BLOCK_SIZE)
+            {
+                // We filled the last BD buffer, so move on to the next one
+                uc_desc->bd[desc->currBd].BD_CTRL.LAST_BD = 0;
+                uc_desc->bd[desc->currBd].BD_CTRL.LIFM = 0;
+                uc_desc->bd[desc->currBd].BD_CTRL.BUFLEN = PIC32_BLOCK_SIZE;
+                desc->currBd++;
+                uc_desc->bd[desc->currBd].UPDPTR = KVA_TO_PA(hash);
+                desc->dbPtr = 0;
+                if (desc->currBd >= PIC32MZ_MAX_BD)
+                {
+                    desc->err = 1;
+                }
+            }
+            if (len > PIC32_BLOCK_SIZE - desc->dbPtr)
+            {
+                // We have more data than can be put in the buffer. Fill what we can.
+                total = PIC32_BLOCK_SIZE - desc->dbPtr;
+                XMEMCPY(&dataBuffer[desc->currBd][desc->dbPtr], input, total);
+                len -= total;
+                desc->processed += total;
+                desc->dbPtr = PIC32_BLOCK_SIZE;
+                input += total;
+            }
+            else
+            {
+                // Fill up what we have
+                XMEMCPY(&dataBuffer[desc->currBd][desc->dbPtr], input, len);
+                desc->dbPtr += len;
+                desc->processed += len;
+                len = 0;
+            }
+        }
+    }
+}
+
+static void start_engine(pic32mz_desc *desc) {
+    // Wrap up the last buffer descriptor and enable it
+    int i ;
+    int bufferLen ;
+    pic32mz_desc *uc_desc = KVA0_TO_KVA1(desc);
+
+    bufferLen = desc->dbPtr;
+    if (bufferLen % 4)
+        bufferLen = (bufferLen + 4) - (bufferLen % 4);
+    uc_desc->bd[desc->currBd].BD_CTRL.BUFLEN = bufferLen;
+    uc_desc->bd[desc->currBd].BD_CTRL.LAST_BD = 1;
+    uc_desc->bd[desc->currBd].BD_CTRL.LIFM = 1;
+    if (desc->msgSize == 0)
+    {
+        // We were not given the size, so now we have to go through every BD
+        // and give it what will be processed, and enable them.
+        for (i = desc->currBd; i >= 0; i--)
+        {
+            uc_desc->bd[i].MSGLEN = desc->processed;
+            uc_desc->bd[i].BD_CTRL.DESC_EN = 1;
+        }
+    }
+    else
+    {
+        uc_desc->bd[desc->currBd].BD_CTRL.DESC_EN = 1;
+    }
+}
+
+void wait_engine(pic32mz_desc *desc, char *hash, int hash_sz) {
+    unsigned int i;
+    unsigned int *intptr;
+    pic32mz_desc *uc_desc = KVA0_TO_KVA1(desc);
+    enum {true = 1, false = 0} engineRunning = true;
+
+    while (engineRunning)
+    {
+        engineRunning = false;
+        for (i = 0; i < PIC32MZ_MAX_BD; i++)
+            engineRunning = engineRunning || uc_desc->bd[i].BD_CTRL.DESC_EN;
+    }
+    XMEMCPY(hash, KVA0_TO_KVA1(hash), hash_sz) ;
+
+    #ifdef DEBUG_CYASSL
+    print_mem(KVA0_TO_KVA1(hash), hash_sz) ;
+    print_mem(             hash , hash_sz) ;
+    #endif
+    for (i = 0, intptr = (unsigned int *)hash; i < hash_sz/sizeof(unsigned int);
+                                                                  i++, intptr++)
+    {
+        *intptr = ntohl(*intptr);
+    }
+}
+
+static int fillBuff(char *buff, int *bufflen, const char *data, int len, int blocksz)
+{
+    int room, copysz ;
+
+    room = blocksz - *bufflen ;
+    copysz = (len <= room) ? len : room ;
+    XMEMCPY(buff, data, copysz) ;
+    *bufflen += copysz ;
+    return (*bufflen == blocksz) ? 1 : 0 ;
+}
+
+#endif
+
+#ifndef NO_MD5
+void wc_InitMd5(Md5* md5)
+{
+    WOLFSSL_ENTER("InitMd5\n") ;
+    XMEMSET((void *)md5, 0xcc, sizeof(Md5)) ;
+    XMEMSET((void *)KVA0_TO_KVA1(md5), 0xcc, sizeof(Md5)) ;
+    reset_engine(&(md5->desc), PIC32_ALGO_MD5) ;
+
+}
+
+void wc_Md5Update(Md5* md5, const byte* data, word32 len)
+{
+     WOLFSSL_ENTER("Md5Update\n") ;
+     update_engine(&(md5->desc), data, len, md5->digest) ;
+}
+
+void wc_Md5Final(Md5* md5, byte* hash)
+{
+     WOLFSSL_ENTER("Md5Final\n") ;
+    start_engine(&(md5->desc)) ;
+    wait_engine(&(md5->desc), (char *)md5->digest, MD5_HASH_SIZE) ;
+    XMEMCPY(hash, md5->digest, MD5_HASH_SIZE) ;
+    wc_InitMd5(md5);  /* reset state */
+}
+
+void Md5SizeSet(Md5* md5, word32 len)
+{
+    WOLFSSL_ENTER("Md5SizeSet\n");
+    md5->desc.msgSize = len;
+}
+#endif
+
+#ifndef NO_SHA
+int wc_InitSha(Sha* sha)
+{
+    WOLFSSL_ENTER("InitSha\n") ;
+    XMEMSET((void *)sha, 0xcc, sizeof(Sha)) ;
+    XMEMSET((void *)KVA0_TO_KVA1(sha), 0xcc, sizeof(Sha)) ;
+    reset_engine(&(sha->desc), PIC32_ALGO_SHA1) ;
+    return 0;
+}
+
+int wc_ShaUpdate(Sha* sha, const byte* data, word32 len)
+{
+    WOLFSSL_ENTER("ShaUpdate\n") ;
+    update_engine(&(sha->desc), data, len, sha->digest) ;
+    return 0;
+}
+
+int wc_ShaFinal(Sha* sha, byte* hash)
+{
+    WOLFSSL_ENTER("ShaFinal\n") ;
+    start_engine(&(sha->desc)) ;
+    wait_engine(&(sha->desc), (char *)sha->digest, SHA1_HASH_SIZE) ;
+    XMEMCPY(hash, sha->digest, SHA1_HASH_SIZE) ;
+
+    wc_InitSha(sha);  /* reset state */
+    return 0;
+}
+
+void ShaSizeSet(Sha* sha, word32 len)
+{
+    sha->desc.msgSize = len;
+}
+#endif /* NO_SHA */
+
+#ifndef NO_SHA256
+int wc_InitSha256(Sha256* sha256)
+{
+    WOLFSSL_ENTER("InitSha256\n") ;
+    XMEMSET((void *)sha256, 0xcc, sizeof(Sha256)) ;
+    XMEMSET((void *)KVA0_TO_KVA1(sha256), 0xcc, sizeof(Sha256)) ;
+    reset_engine(&(sha256->desc), PIC32_ALGO_SHA256) ;
+    return 0;
+}
+
+int wc_Sha256Update(Sha256* sha256, const byte* data, word32 len)
+{
+    WOLFSSL_ENTER("Sha256Update\n") ;
+    update_engine(&(sha256->desc), data, len, sha256->digest) ;
+
+    return 0;
+}
+
+int wc_Sha256Final(Sha256* sha256, byte* hash)
+{
+    WOLFSSL_ENTER("Sha256Final\n") ;
+    start_engine(&(sha256->desc)) ;
+    wait_engine(&(sha256->desc), (char *)sha256->digest, SHA256_HASH_SIZE) ;
+    XMEMCPY(hash, sha256->digest, SHA256_HASH_SIZE) ;
+    wc_InitSha256(sha256);  /* reset state */
+
+    return 0;
+}
+
+void Sha256SizeSet(Sha256* sha256, word32 len)
+{
+    WOLFSSL_ENTER("Sha256SizeSet\n");
+    sha256->desc.msgSize = len;
+}
+
+#endif /* NO_SHA256 */
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/port/ti/ti-aes.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/port/ti/ti-aes.c
new file mode 100644
index 0000000..d38e7a3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/port/ti/ti-aes.c
@@ -0,0 +1,548 @@
+/* port/ti/ti-aes.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+ 
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifndef NO_AES
+
+
+#if defined(WOLFSSL_TI_CRYPT)
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include "inc/hw_aes.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_ints.h"
+#include "driverlib/aes.h"
+#include "driverlib/sysctl.h"
+#include "driverlib/rom_map.h"
+#include "driverlib/rom.h"
+
+static int  AesSetIV(Aes* aes, const byte* iv)
+{
+    if (aes == NULL)
+        return BAD_FUNC_ARG;
+
+    if (iv)
+        XMEMCPY(aes->reg, iv, AES_BLOCK_SIZE);
+    else
+        XMEMSET(aes->reg,  0, AES_BLOCK_SIZE);
+
+    return 0;
+}
+
+WOLFSSL_API int  wc_AesSetKey(Aes* aes, const byte* key, word32 len, const byte* iv,
+                          int dir)
+{
+    if(!wolfSSL_TI_CCMInit())return 1 ;
+    if ((aes == NULL) || (key == NULL) || (iv == NULL))
+        return BAD_FUNC_ARG;
+    if(!((dir == AES_ENCRYPTION) || (dir == AES_DECRYPTION)))
+        return BAD_FUNC_ARG;
+    
+    switch(len) {
+    case 16: aes->keylen = AES_CFG_KEY_SIZE_128BIT ; break ;
+    case 24: aes->keylen = AES_CFG_KEY_SIZE_192BIT ; break ;
+    case 32: aes->keylen = AES_CFG_KEY_SIZE_256BIT ; break ;
+    default: return BAD_FUNC_ARG;      
+    }
+    
+    XMEMCPY(aes->key, key, len) ;
+    #ifdef WOLFSSL_AES_COUNTER
+    aes->left = 0;
+    #endif /* WOLFSSL_AES_COUNTER */
+    return AesSetIV(aes, iv);
+}
+
+#define AES_CFG_MODE_CTR_NOCTR AES_CFG_MODE_CTR+100
+#define IS_ALIGN16(p) (((unsigned int)(p)&0xf) == 0)
+
+static int  AesAlign16(Aes* aes, byte* out, const byte* in, word32 sz, word32 dir, word32 mode)
+{   
+    wolfSSL_TI_lockCCM() ;
+    ROM_AESReset(AES_BASE);
+    ROM_AESConfigSet(AES_BASE, (aes->keylen | dir | 
+                     (mode==AES_CFG_MODE_CTR_NOCTR ? AES_CFG_MODE_CTR : mode)));
+    ROM_AESIVSet(AES_BASE, aes->reg);
+    ROM_AESKey1Set(AES_BASE, aes->key, aes->keylen);
+    if((dir == AES_CFG_DIR_DECRYPT)&& (mode == AES_CFG_MODE_CBC))
+        /* if input and output same will overwrite input iv */
+        XMEMCPY(aes->tmp, in + sz - AES_BLOCK_SIZE, AES_BLOCK_SIZE);
+    ROM_AESDataProcess(AES_BASE, (uint32_t *)in, (uint32_t *)out, sz);
+    wolfSSL_TI_unlockCCM() ;
+    
+    /* store iv for next call */
+    if(mode == AES_CFG_MODE_CBC){
+        if(dir == AES_CFG_DIR_ENCRYPT)
+            XMEMCPY(aes->reg, out + sz - AES_BLOCK_SIZE, AES_BLOCK_SIZE);
+        else
+            XMEMCPY(aes->reg, aes->tmp, AES_BLOCK_SIZE);
+    }
+
+    if(mode == AES_CFG_MODE_CTR) {
+        do {  
+            int i ;
+            for (i = AES_BLOCK_SIZE - 1; i >= 0; i--) {
+                 if (++((byte *)aes->reg)[i])
+                     break ;
+            }
+            sz -= AES_BLOCK_SIZE ;
+        } while((int)sz > 0) ;
+    }
+
+    return 0 ;
+}
+
+static int  AesProcess(Aes* aes, byte* out, const byte* in, word32 sz, word32 dir, word32 mode)
+{   
+    const byte * in_p ; byte * out_p ; 
+    word32 size ;
+    #define TI_BUFFSIZE 1024
+    byte buff[TI_BUFFSIZE] ;
+    
+    if ((aes == NULL) || (in == NULL) || (out == NULL))
+        return BAD_FUNC_ARG;
+    if(sz % AES_BLOCK_SIZE)
+        return BAD_FUNC_ARG;
+
+    while(sz > 0) {
+        size = sz ; in_p = in ; out_p = out ;
+        if(!IS_ALIGN16(in)){
+            size = sz>TI_BUFFSIZE ? TI_BUFFSIZE : sz ;
+            XMEMCPY(buff, in, size) ; 
+            in_p = (const byte *)buff ;
+        }
+        if(!IS_ALIGN16(out)){
+            size = sz>TI_BUFFSIZE ? TI_BUFFSIZE : sz ;
+            out_p = buff ;
+        }
+   
+        AesAlign16(aes, out_p, in_p, size, dir, mode) ;
+ 
+        if(!IS_ALIGN16(out)){
+            XMEMCPY(out, buff, size) ;
+        }
+        sz -= size ; in += size ; out += size ;
+    }
+
+    return 0 ;
+}
+
+WOLFSSL_API int  wc_AesCbcEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
+{   
+    return AesProcess(aes, out, in, sz, AES_CFG_DIR_ENCRYPT, AES_CFG_MODE_CBC) ;
+}
+
+WOLFSSL_API int  wc_AesCbcDecrypt(Aes* aes, byte* out, const byte* in, word32 sz)
+{   
+    return AesProcess(aes, out, in, sz, AES_CFG_DIR_DECRYPT, AES_CFG_MODE_CBC) ;
+}
+
+#ifdef WOLFSSL_AES_COUNTER
+WOLFSSL_API void wc_AesCtrEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
+{ 
+            char out_block[AES_BLOCK_SIZE] ;
+            int odd ;
+            int even ;
+            char *tmp ; /* (char *)aes->tmp, for short */
+
+            tmp = (char *)aes->tmp ;
+            if(aes->left) {
+                if((aes->left + sz) >= AES_BLOCK_SIZE){
+                    odd = AES_BLOCK_SIZE - aes->left ;
+                } else {
+                    odd = sz ;
+                }
+                XMEMCPY(tmp+aes->left, in, odd) ;
+                if((odd+aes->left) == AES_BLOCK_SIZE){
+                    AesProcess(aes, (byte *)out_block, (byte const *)tmp, AES_BLOCK_SIZE, 
+                             AES_CFG_DIR_ENCRYPT, AES_CFG_MODE_CTR) ;
+                    XMEMCPY(out, out_block+aes->left, odd) ;
+                    aes->left = 0 ;
+                    XMEMSET(tmp, 0x0, AES_BLOCK_SIZE) ;
+                }
+                in += odd ;
+                out+= odd ;
+                sz -= odd ;
+            }
+            odd = sz % AES_BLOCK_SIZE ;  /* if there is tail flagment */
+            if(sz / AES_BLOCK_SIZE) {
+                even = (sz/AES_BLOCK_SIZE)*AES_BLOCK_SIZE ;
+                AesProcess(aes, out, in, even, AES_CFG_DIR_ENCRYPT, AES_CFG_MODE_CTR);
+                out += even ;
+                in  += even ;
+            }
+            if(odd) {
+                XMEMSET(tmp+aes->left, 0x0, AES_BLOCK_SIZE - aes->left) ;
+                XMEMCPY(tmp+aes->left, in, odd) ;
+                AesProcess(aes, (byte *)out_block, (byte const *)tmp, AES_BLOCK_SIZE, 
+                           AES_CFG_DIR_ENCRYPT, 
+                           AES_CFG_MODE_CTR_NOCTR /* Counter mode without counting IV */
+                           );
+                XMEMCPY(out, out_block+aes->left,odd) ;
+                aes->left += odd ;
+            }
+}
+#endif
+
+/* AES-DIRECT */
+#if defined(WOLFSSL_AES_DIRECT)
+WOLFSSL_API void wc_AesEncryptDirect(Aes* aes, byte* out, const byte* in)
+{
+    AesProcess(aes, out, in, AES_BLOCK_SIZE, AES_CFG_DIR_ENCRYPT, AES_CFG_MODE_CBC) ;
+}
+WOLFSSL_API void wc_AesDecryptDirect(Aes* aes, byte* out, const byte* in)
+{
+    AesProcess(aes, out, in, AES_BLOCK_SIZE, AES_CFG_DIR_DECRYPT, AES_CFG_MODE_CBC) ;
+}
+WOLFSSL_API int wc_AesSetKeyDirect(Aes* aes, const byte* key, word32 len,
+                                     const byte* iv, int dir)
+{
+     return(wc_AesSetKey(aes, key, len, iv, dir)) ;
+}
+#endif
+
+
+#if defined(HAVE_AESGCM) || defined(HAVE_AESCCM)
+
+static int  AesAuthSetKey(Aes* aes, const byte* key, word32 keySz)
+{
+    byte nonce[AES_BLOCK_SIZE];
+
+    if ((aes == NULL) || (key == NULL))
+        return BAD_FUNC_ARG ;
+    if (!((keySz == 16) || (keySz == 24) || (keySz == 32)))
+        return BAD_FUNC_ARG ;
+
+    XMEMSET(nonce, 0, sizeof(nonce));
+    return wc_AesSetKey(aes, key, keySz, nonce, AES_ENCRYPTION);
+}
+
+
+static int AesAuthArgCheck(Aes* aes, byte* out, const byte* in, word32 inSz,
+                              const byte* nonce, word32 nonceSz,
+                              const byte* authTag, word32 authTagSz,
+                              const byte* authIn, word32 authInSz, word32 *M,  word32 *L)
+{
+    if((aes == NULL)||(nonce == NULL)||(authTag== NULL)||(authIn == NULL))
+        return BAD_FUNC_ARG;
+    if((inSz != 0) && ((out == NULL)||(in == NULL)))
+        return BAD_FUNC_ARG;
+    
+    switch(authTagSz){
+    case  4:
+        *M = AES_CFG_CCM_M_4; break ;
+    case 6:
+        *M = AES_CFG_CCM_M_6; break ;
+    case 8:
+        *M = AES_CFG_CCM_M_8; break ;
+    case 10:
+        *M = AES_CFG_CCM_M_10; break ;
+    case 12:
+        *M = AES_CFG_CCM_M_12; break ;
+    case 14:
+        *M = AES_CFG_CCM_M_14; break ;
+    case 16:
+        *M = AES_CFG_CCM_M_16; break ;
+    default:
+        return 1 ;
+    }
+
+    switch(nonceSz){
+    case 7:
+        *L = AES_CFG_CCM_L_8; break ;
+    case 8:
+        *L = AES_CFG_CCM_L_7; break ;
+    case 9:
+        *L = AES_CFG_CCM_L_6; break ;
+    case  10:
+        *L = AES_CFG_CCM_L_5; break ;
+    case 11:
+        *L = AES_CFG_CCM_L_4; break ;
+    case 12:
+        *L = AES_CFG_CCM_L_3; break ;
+    case 13:
+        *L = AES_CFG_CCM_L_2; break ;
+    case 14:
+        *L = AES_CFG_CCM_L_1; break ;
+    default:
+        return 1;
+    }
+    return 0 ;
+}
+
+static void AesAuthSetIv(Aes *aes, const byte *nonce, word32 len, word32 L, int mode) {
+
+  if(mode == AES_CFG_MODE_CCM){
+    XMEMSET(aes->reg, 0, 16) ;
+    switch(L){
+    case AES_CFG_CCM_L_8: 
+      aes->reg[0] = 0x7; break ;
+    case AES_CFG_CCM_L_7: 
+      aes->reg[0] = 0x6; break ;
+    case AES_CFG_CCM_L_6: 
+      aes->reg[0] = 0x5; break ;
+    case AES_CFG_CCM_L_5: 
+      aes->reg[0] = 0x4; break ;
+    case AES_CFG_CCM_L_4: 
+      aes->reg[0] = 0x3; break ;
+    case AES_CFG_CCM_L_3: 
+      aes->reg[0] = 0x2; break ;
+    case AES_CFG_CCM_L_2: 
+      aes->reg[0] = 0x1; break ;
+    case AES_CFG_CCM_L_1: 
+      aes->reg[0] = 0x0; break ;
+    }
+    XMEMCPY(((byte *)aes->reg)+1, nonce, len) ; 
+  } else {
+    byte *b = (byte *)aes->reg ;
+    XMEMSET(aes->reg, 0, AES_BLOCK_SIZE);
+    XMEMCPY(aes->reg, nonce, len);
+    b[AES_BLOCK_SIZE-4] = 0 ;
+    b[AES_BLOCK_SIZE-3] = 0 ;
+    b[AES_BLOCK_SIZE-2] = 0 ;
+    b[AES_BLOCK_SIZE-1] = 1 ;
+  }
+}
+
+#define RoundUp16(n) ((n+15)&0xfffffff0)
+#define FREE_ALL \
+    if(in_save)    XFREE(in_save, NULL, DYNAMIC_TYPE_TMP_BUFFER);\
+    if(out_save)   XFREE(out_save, NULL, DYNAMIC_TYPE_TMP_BUFFER);\
+    if(authIn_save)XFREE(authIn_save, NULL, DYNAMIC_TYPE_TMP_BUFFER);\
+    if(nonce_save) XFREE(nonce_save, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+
+static int AesAuthEncrypt(Aes* aes, byte* out, const byte* in, word32 inSz,
+                              const byte* nonce, word32 nonceSz,
+                              byte* authTag, word32 authTagSz,
+                              const byte* authIn, word32 authInSz, int mode)
+{ 
+    word32 M, L ;
+    byte *in_a,     *in_save ;
+    byte *out_a,    *out_save ;
+    byte *authIn_a, *authIn_save ;
+    byte *nonce_a,    *nonce_save ;
+    word32 tmpTag[4] ;
+    int ret ;
+
+    if(AesAuthArgCheck(aes, out, in, inSz, nonce, nonceSz, authTag, authTagSz, authIn, authInSz, &M, &L)
+       == BAD_FUNC_ARG)return BAD_FUNC_ARG ;
+    
+    /* 16 byte padding */
+    in_save = NULL ; out_save = NULL ; authIn_save = NULL ; nonce_save = NULL ;
+    if((inSz%16)==0){
+        in_save = NULL ; in_a = (byte *)in ;
+        out_save = NULL ; out_a = out ;
+    } else {
+      if((in_save = XMALLOC(RoundUp16(inSz), NULL, DYNAMIC_TYPE_TMP_BUFFER)) == NULL){ 
+          FREE_ALL; return MEMORY_E ; }
+      in_a = in_save ; XMEMSET(in_a, 0, RoundUp16(inSz)) ; XMEMCPY(in_a, in, inSz) ;
+      
+      if((out_save = XMALLOC(RoundUp16(inSz), NULL, DYNAMIC_TYPE_TMP_BUFFER)) == NULL){ 
+          FREE_ALL; return MEMORY_E ; } 
+      out_a = out_save ; 
+    }
+    
+    if((authInSz%16)==0){
+        authIn_save = NULL ; authIn_a = (byte *)authIn ;
+    } else {
+      if((authIn_save = XMALLOC(RoundUp16(authInSz), NULL, DYNAMIC_TYPE_TMP_BUFFER)) == NULL){ 
+          FREE_ALL; return MEMORY_E ; }
+      authIn_a = authIn_save ; XMEMSET(authIn_a, 0, RoundUp16(authInSz)) ; XMEMCPY(authIn_a, authIn, authInSz) ;
+    }
+
+    if((nonceSz%16)==0){
+        nonce_save = NULL ; nonce_a = (byte *)nonce ;
+    } else {
+      if((nonce_save = XMALLOC(RoundUp16(nonceSz), NULL, DYNAMIC_TYPE_TMP_BUFFER)) == NULL){ 
+          FREE_ALL; return MEMORY_E; }
+      nonce_a = nonce_save ; XMEMSET(nonce_a, 0, RoundUp16(nonceSz)) ; XMEMCPY(nonce_a, nonce, nonceSz) ;
+    }
+
+    /* do aes-ccm */
+    AesAuthSetIv(aes, nonce, nonceSz, L, mode) ;
+    ROM_AESReset(AES_BASE);
+    ROM_AESConfigSet(AES_BASE, (aes->keylen | AES_CFG_DIR_ENCRYPT |
+                                AES_CFG_CTR_WIDTH_128 |
+                                mode | ((mode== AES_CFG_MODE_CCM) ? (L | M) : 0 ))) ;
+    ROM_AESIVSet(AES_BASE, aes->reg);
+    ROM_AESKey1Set(AES_BASE, aes->key, aes->keylen);
+    ret = ROM_AESDataProcessAuth(AES_BASE, (unsigned int*)in_a, (unsigned int *)out_a, inSz,
+                           (unsigned int*)authIn_a, authInSz, (unsigned int *)tmpTag);
+    if(ret == false){
+        XMEMSET(out, 0, inSz) ;
+        XMEMSET(authTag, 0, authTagSz) ;
+    } else {
+        XMEMCPY(out, out_a, inSz) ;
+        XMEMCPY(authTag, tmpTag, authTagSz) ;
+    }
+
+    FREE_ALL; 
+    return 0 ;
+}
+
+static int AesAuthDecrypt(Aes* aes, byte* out, const byte* in, word32 inSz,
+                              const byte* nonce, word32 nonceSz,
+                              const byte* authTag, word32 authTagSz,
+                              const byte* authIn, word32 authInSz, int mode)
+{ 
+    word32 M, L ;
+    byte *in_a,     *in_save ;
+    byte *out_a,    *out_save ;
+    byte *authIn_a, *authIn_save ;
+    byte *nonce_a,    *nonce_save ;
+    word32 tmpTag[4] ;
+    bool ret ;
+
+    if(AesAuthArgCheck(aes, out, in, inSz, nonce, nonceSz, authTag, authTagSz, authIn, authInSz, &M, &L)
+       == BAD_FUNC_ARG)return  BAD_FUNC_ARG ;
+    
+    /* 16 byte padding */
+    in_save = NULL ; out_save = NULL ; authIn_save = NULL ; nonce_save = NULL ;
+    if((inSz%16)==0){
+        in_save = NULL ; in_a = (byte *)in ;
+        out_save = NULL ; out_a = out ;
+    } else {
+      if((in_save = XMALLOC(RoundUp16(inSz), NULL, DYNAMIC_TYPE_TMP_BUFFER)) == NULL){ 
+          FREE_ALL; return MEMORY_E;}
+      in_a = in_save ; XMEMSET(in_a, 0, RoundUp16(inSz)) ; XMEMCPY(in_a, in, inSz) ;
+      
+      if((out_save = XMALLOC(RoundUp16(inSz), NULL, DYNAMIC_TYPE_TMP_BUFFER)) == NULL){ 
+          FREE_ALL; return MEMORY_E;}
+      out_a = out_save ; 
+    }
+    
+    if((authInSz%16)==0){
+        authIn_save = NULL ; authIn_a = (byte *)authIn ;
+    } else {
+      if((authIn_save = XMALLOC(RoundUp16(authInSz), NULL, DYNAMIC_TYPE_TMP_BUFFER)) == NULL){ 
+          FREE_ALL; return MEMORY_E; }
+      authIn_a = authIn_save ; XMEMSET(authIn_a, 0, RoundUp16(authInSz)) ; XMEMCPY(authIn_a, authIn, authInSz) ;
+    }
+
+    if((nonceSz%16)==0){
+        nonce_save = NULL ; nonce_a = (byte *)nonce ;
+    } else {
+      if((nonce_save = XMALLOC(RoundUp16(nonceSz), NULL, DYNAMIC_TYPE_TMP_BUFFER)) == NULL){ 
+          FREE_ALL; return MEMORY_E; }
+      nonce_a = nonce_save ; XMEMSET(nonce_a, 0, RoundUp16(nonceSz)) ; XMEMCPY(nonce_a, nonce, nonceSz) ;
+    }
+
+    /* do aes-ccm */
+    AesAuthSetIv(aes, nonce, nonceSz, L, mode) ;
+    ROM_AESReset(AES_BASE);
+    ROM_AESConfigSet(AES_BASE, (aes->keylen | AES_CFG_DIR_DECRYPT |
+                                AES_CFG_CTR_WIDTH_128 |
+                                  mode | ((mode== AES_CFG_MODE_CCM) ? (L | M) : 0 ))) ;
+    ROM_AESIVSet(AES_BASE, aes->reg);
+    ROM_AESKey1Set(AES_BASE, aes->key, aes->keylen);
+    ret = ROM_AESDataProcessAuth(AES_BASE, (unsigned int*)in_a, (unsigned int *)out_a, inSz,
+                           (unsigned int*)authIn_a, authInSz, (unsigned int *)tmpTag);
+    if((ret == false) || (XMEMCMP(authTag, tmpTag, authTagSz) != 0)){
+        XMEMSET(out, 0, inSz) ;
+        ret = false ;
+    } else {
+        XMEMCPY(out, out_a, inSz) ;  
+    }
+
+    FREE_ALL ;
+    return ret==true ? 0 : 1 ;
+}
+#endif
+
+
+#ifdef HAVE_AESGCM
+WOLFSSL_API int  wc_AesGcmSetKey(Aes* aes, const byte* key, word32 len)
+{
+    return AesAuthSetKey(aes, key, len) ;
+}
+
+WOLFSSL_API int  wc_AesGcmEncrypt(Aes* aes, byte* out, const byte* in, word32 sz,
+                              const byte* iv, word32 ivSz,
+                              byte* authTag, word32 authTagSz,
+                              const byte* authIn, word32 authInSz)
+{
+    return AesAuthEncrypt(aes, out, in, sz, iv, ivSz, authTag, authTagSz,
+                              authIn, authInSz, AES_CFG_MODE_GCM_HY0CALC) ;
+}
+WOLFSSL_API int  wc_AesGcmDecrypt(Aes* aes, byte* out, const byte* in, word32 sz,
+                              const byte* iv, word32 ivSz,
+                              const byte* authTag, word32 authTagSz,
+                              const byte* authIn, word32 authInSz)
+{ 
+    return AesAuthDecrypt(aes, out, in, sz, iv, ivSz, authTag, authTagSz,
+                              authIn, authInSz, AES_CFG_MODE_GCM_HY0CALC) ;
+}
+
+WOLFSSL_API int wc_GmacSetKey(Gmac* gmac, const byte* key, word32 len)
+{
+      return AesAuthSetKey(&gmac->aes, key, len) ;
+}
+
+WOLFSSL_API int wc_GmacUpdate(Gmac* gmac, const byte* iv, word32 ivSz,
+                              const byte* authIn, word32 authInSz,
+                              byte* authTag, word32 authTagSz)
+{
+    return AesAuthEncrypt(&gmac->aes, NULL, NULL, 0, iv, ivSz, authTag, authTagSz,
+                              authIn, authInSz, AES_CFG_MODE_GCM_HY0CALC) ;
+}
+
+#endif /* HAVE_AESGCM */
+
+#ifdef HAVE_AESCCM
+WOLFSSL_API void wc_AesCcmSetKey(Aes* aes, const byte* key, word32 keySz)
+{
+    AesAuthSetKey(aes, key, keySz) ;
+}
+
+WOLFSSL_API void wc_AesCcmEncrypt(Aes* aes, byte* out, const byte* in, word32 inSz,
+                              const byte* nonce, word32 nonceSz,
+                              byte* authTag, word32 authTagSz,
+                              const byte* authIn, word32 authInSz)
+{ 
+    AesAuthEncrypt(aes, out, in, inSz, nonce, nonceSz, authTag, authTagSz,
+                              authIn, authInSz, AES_CFG_MODE_CCM) ;
+}
+
+WOLFSSL_API int wc_AesCcmDecrypt(Aes* aes, byte* out, const byte* in, word32 inSz,
+                              const byte* nonce, word32 nonceSz,
+                              const byte* authTag, word32 authTagSz,
+                              const byte* authIn, word32 authInSz)
+{ 
+    return AesAuthDecrypt(aes, out, in, inSz, nonce, nonceSz, authTag, authTagSz,
+                              authIn, authInSz, AES_CFG_MODE_CCM) ;
+}
+#endif /* HAVE_AESCCM */
+
+#endif /* WOLFSSL_TI_CRYPT */
+
+#endif /* NO_AES */
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/port/ti/ti-ccm.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/port/ti/ti-ccm.c
new file mode 100644
index 0000000..09705cf
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/port/ti/ti-ccm.c
@@ -0,0 +1,82 @@
+/* port/ti/ti_ccm.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#if defined(WOLFSSL_TI_CRYPT) ||  defined(WOLFSSL_TI_HASH)
+
+
+#include 
+#include 
+
+#include "driverlib/sysctl.h"
+#include "driverlib/rom_map.h"
+#include "driverlib/rom.h"
+
+#ifndef SINGLE_THREADED
+#include 
+    static wolfSSL_Mutex TI_CCM_Mutex ;
+#endif
+
+#define TIMEOUT  500000
+#define WAIT(stat) { volatile int i ; for(i=0; i
+#endif
+
+#include 
+
+#ifndef NO_DES
+
+#if defined(WOLFSSL_TI_CRYPT)
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include "inc/hw_des.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_ints.h"
+#include "driverlib/des.h"
+#include "driverlib/sysctl.h"
+#include "driverlib/rom_map.h"
+#include "driverlib/rom.h"
+
+static int  DesSetIV(Des* des, const byte* iv, int tri)
+{
+    if (des == NULL)
+        return BAD_FUNC_ARG;
+
+    if (iv)
+        XMEMCPY(des->reg, iv, tri == DES_CFG_TRIPLE ? DES3_IVLEN : DES_IVLEN);
+    else
+        XMEMSET(des->reg,  0, tri == DES_CFG_TRIPLE ? DES3_IVLEN : DES_IVLEN);
+
+    return 0;
+}
+
+static int  DesSetKey(Des* des, const byte* key, const byte* iv,int dir, int tri)
+{
+    if(!wolfSSL_TI_CCMInit())return 1 ;
+    if ((des == NULL) || (key == NULL) || (iv == NULL))
+        return BAD_FUNC_ARG;
+    if(!((dir == DES_ENCRYPTION) || (dir == DES_DECRYPTION)))
+        return BAD_FUNC_ARG;
+    
+    XMEMCPY(des->key, key, tri == DES_CFG_SINGLE ? DES_KEYLEN : DES3_KEYLEN) ;
+    return DesSetIV(des, iv, tri);
+}
+
+static int  DesCbcAlign16(Des* des, byte* out, const byte* in, word32 sz, word32 dir, word32 tri)
+{   
+
+    wolfSSL_TI_lockCCM() ;
+    ROM_DESReset(DES_BASE);
+    ROM_DESConfigSet(DES_BASE, (dir | DES_CFG_MODE_CBC | tri));
+    ROM_DESIVSet(DES_BASE, des->reg);
+    ROM_DESKeySet(DES_BASE, des->key);
+    if(dir == DES_CFG_DIR_DECRYPT)
+        /* if input and output same will overwrite input iv */
+        XMEMCPY(des->tmp, in + sz - DES_BLOCK_SIZE, DES_BLOCK_SIZE);
+    ROM_DESDataProcess(DES_BASE, (uint32_t *)in, (uint32_t *)out, sz);
+    wolfSSL_TI_unlockCCM() ;
+    
+    /* store iv for next call */
+    if(dir == DES_CFG_DIR_ENCRYPT)
+        XMEMCPY(des->reg, out + sz - DES_BLOCK_SIZE, DES_BLOCK_SIZE);
+    else
+        XMEMCPY(des->reg, des->tmp, DES_BLOCK_SIZE);
+    
+    return 0 ;
+}
+
+#define IS_ALIGN16(p) (((unsigned int)(p)&0xf) == 0)
+
+static int  DesCbc(Des* des, byte* out, const byte* in, word32 sz, word32 dir, word32 tri)
+{   
+    const byte * in_p ; byte * out_p ; 
+    word32 size ;
+    #define TI_BUFFSIZE 1024
+    byte buff[TI_BUFFSIZE] ;
+    if ((des == NULL) || (in == NULL) || (out == NULL))
+        return BAD_FUNC_ARG;
+    if(sz % DES_BLOCK_SIZE)
+        return BAD_FUNC_ARG;
+    
+    while(sz > 0) {
+        size = sz ; in_p = in ; out_p = out ;
+        if(!IS_ALIGN16(in)){
+            size = sz>TI_BUFFSIZE ? TI_BUFFSIZE : sz ;
+            XMEMCPY(buff, in, size) ; 
+            in_p = (const byte *)buff ;
+        }
+        if(!IS_ALIGN16(out)){
+            size = sz>TI_BUFFSIZE ? TI_BUFFSIZE : sz ;
+            out_p = (byte *)buff ;
+        }
+    
+        DesCbcAlign16(des, out_p, in_p, size, dir, tri) ;
+        
+        if(!IS_ALIGN16(out)){
+            XMEMCPY(out, buff, size) ;
+        }
+        sz -= size ; in += size ; out += size ;
+    }
+    return 0 ;
+}
+
+WOLFSSL_API int  wc_Des_SetKey(Des* des, const byte* key, const byte* iv,int dir)
+{
+    return DesSetKey(des, key, iv, dir, DES_CFG_SINGLE) ;
+}
+
+WOLFSSL_API void  wc_Des_SetIV(Des* des, const byte* iv)
+{
+    DesSetIV(des, iv, DES_CFG_SINGLE) ;
+}
+
+WOLFSSL_API int  wc_Des3_SetKey(Des3* des, const byte* key, const byte* iv,int dir)
+{
+    return DesSetKey((Des *)des, key, iv, dir, DES_CFG_TRIPLE) ;
+}
+
+WOLFSSL_API int  wc_Des3_SetIV(Des3* des, const byte* iv)
+{
+    return DesSetIV((Des *)des, iv, DES_CFG_TRIPLE) ;
+}
+
+
+WOLFSSL_API int  wc_Des_CbcEncrypt(Des* des, byte* out, const byte* in, word32 sz)
+{   
+    return DesCbc(des, out, in, sz, DES_CFG_DIR_ENCRYPT, DES_CFG_SINGLE) ;
+}
+
+WOLFSSL_API int  wc_Des_CbcDecrypt(Des* des, byte* out, const byte* in, word32 sz)
+{   
+    return DesCbc(des, out, in, sz, DES_CFG_DIR_DECRYPT, DES_CFG_SINGLE) ;
+}
+
+WOLFSSL_API int  wc_Des_CbcDecryptWithKey(byte* out, const byte* in, word32 sz,
+                                          const byte* key, const byte* iv)
+{ return 0 ;}
+
+WOLFSSL_API int  wc_Des3_CbcEncrypt(Des3* des, byte* out, const byte* in, word32 sz)
+{   
+    return DesCbc((Des *)des, out, in, sz, DES_CFG_DIR_ENCRYPT, DES_CFG_TRIPLE) ;
+}
+
+WOLFSSL_API int  wc_Des3_CbcDecrypt(Des3* des, byte* out, const byte* in, word32 sz)
+{   
+    return DesCbc((Des *)des, out, in, sz, DES_CFG_DIR_DECRYPT, DES_CFG_TRIPLE) ;
+}
+
+WOLFSSL_API int  wc_Des3_CbcDecryptWithKey(byte* out, const byte* in, word32 sz,
+                                               const byte* key, const byte* iv)
+{ return 0 ; }
+
+
+#endif /* WOLFSSL_TI_CRYPT */
+
+#endif /* NO_DES */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/port/ti/ti-hash.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/port/ti/ti-hash.c
new file mode 100644
index 0000000..c60f864
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/port/ti/ti-hash.c
@@ -0,0 +1,291 @@
+/* port/ti/ti-hash.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#include 
+
+#if defined(WOLFSSL_TI_HASH)
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#include 
+#include 
+
+#include 
+#include       
+#include       
+#include       
+#include 
+#include 
+#include 
+
+#ifndef TI_DUMMY_BUILD
+#include "inc/hw_memmap.h"
+#include "inc/hw_shamd5.h"
+#include "inc/hw_ints.h"
+#include "driverlib/shamd5.h"
+#include "driverlib/sysctl.h"
+#include "driverlib/rom_map.h"
+#include "driverlib/rom.h"
+#else
+#define SHAMD5_ALGO_MD5 1
+#define SHAMD5_ALGO_SHA1 2
+#define SHAMD5_ALGO_SHA256 3
+bool wolfSSL_TI_CCMInit(void) { return true ; }
+#endif
+
+static int hashInit(wolfssl_TI_Hash *hash) {
+    hash->used = 0 ;
+    hash->msg  = 0 ;
+    hash->len  = 0 ;
+    return 0 ;
+}
+
+static int hashUpdate(wolfssl_TI_Hash *hash, const byte* data, word32 len)
+{
+    void *p ;
+
+    if((hash== NULL) || (data == NULL))return BAD_FUNC_ARG;
+
+    if(hash->len < hash->used+len) {
+        if(hash->msg == NULL) {
+            p = XMALLOC(hash->used+len, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        } else {
+            p = XREALLOC(hash->msg, hash->used+len, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        }
+        if(p == 0)return 1 ;
+        hash->msg = p ;     
+        hash->len = hash->used+len ;
+    } 
+    XMEMCPY(hash->msg+hash->used, data, len) ;
+    hash->used += len ;
+    return 0 ;
+}
+
+static int hashGetHash(wolfssl_TI_Hash *hash, byte* result, word32 algo, word32 hsize)
+{   
+    uint32_t h[16] ;
+#ifndef TI_DUMMY_BUILD
+    wolfSSL_TI_lockCCM() ;
+    ROM_SHAMD5Reset(SHAMD5_BASE);
+    ROM_SHAMD5ConfigSet(SHAMD5_BASE, algo);
+    ROM_SHAMD5DataProcess(SHAMD5_BASE, 
+                   (uint32_t *)hash->msg, hash->used, h);
+    wolfSSL_TI_unlockCCM() ;
+#else
+    (void) hash ;
+    (void) algo ;
+#endif
+    XMEMCPY(result, h, hsize) ;
+
+    return 0 ;
+}
+
+static void hashRestorePos(wolfssl_TI_Hash *h1, wolfssl_TI_Hash *h2) {
+	h1->used = h2->used ;
+}
+
+static int hashFinal(wolfssl_TI_Hash *hash, byte* result, word32 algo, word32 hsize)
+{   
+    hashGetHash(hash, result, algo, hsize) ;
+    XFREE(hash->msg, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    hashInit(hash) ;
+    return 0 ;
+}
+
+static int hashHash(const byte* data, word32 len, byte* hash, word32 algo, word32 hsize)
+{
+    int ret = 0;
+#ifdef WOLFSSL_SMALL_STACK
+    wolfssl_TI_Hash* hash_desc;
+#else
+    wolfssl_TI_Hash  hash_desc[1];
+#endif
+
+#ifdef WOLFSSL_SMALL_STACK
+    hash_desc = (wolfssl_TI_Hash*)XMALLOC(sizeof(wolfssl_TI_Hash), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (hash_desc == NULL)
+        return MEMORY_E;
+#endif
+
+    if ((ret = hashInit(hash_desc)) != 0) {
+        WOLFSSL_MSG("Hash Init failed");
+    }
+    else {
+        hashUpdate(hash_desc, data, len);
+        hashFinal(hash_desc, hash, algo, hsize);
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(hash, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+#if !defined(NO_MD5)
+WOLFSSL_API void wc_InitMd5(Md5* md5)
+{
+    if (md5 == NULL)
+        return ;
+    if(!wolfSSL_TI_CCMInit())return  ;
+    hashInit((wolfssl_TI_Hash *)md5) ;
+}
+
+WOLFSSL_API void wc_Md5Update(Md5* md5, const byte* data, word32 len)
+{
+    hashUpdate((wolfssl_TI_Hash *)md5, data, len) ;
+}
+
+WOLFSSL_API void wc_Md5Final(Md5* md5, byte* hash)
+{
+    hashFinal((wolfssl_TI_Hash *)md5, hash, SHAMD5_ALGO_MD5, MD5_DIGEST_SIZE) ;
+}
+
+WOLFSSL_API void wc_Md5GetHash(Md5* md5, byte* hash)
+{
+    hashGetHash((wolfssl_TI_Hash *)md5, hash, SHAMD5_ALGO_MD5, MD5_DIGEST_SIZE) ;
+}
+
+WOLFSSL_API void wc_Md5RestorePos(Md5* m1, Md5* m2) {
+	hashRestorePos((wolfssl_TI_Hash *)m1, (wolfssl_TI_Hash *)m2) ;
+}
+
+WOLFSSL_API int wc_Md5Hash(const byte*data, word32 len, byte*hash)
+{ 
+    return hashHash(data, len, hash, SHAMD5_ALGO_MD5, MD5_DIGEST_SIZE) ;
+}
+
+#endif /* NO_MD5 */
+
+#if !defined(NO_SHA)
+WOLFSSL_API int wc_InitSha(Sha* sha)
+{
+    if (sha == NULL)
+        return 1 ;
+    if(!wolfSSL_TI_CCMInit())return 1 ;
+    return hashInit((wolfssl_TI_Hash *)sha) ;
+}
+
+WOLFSSL_API int wc_ShaUpdate(Sha* sha, const byte* data, word32 len)
+{
+    return hashUpdate((wolfssl_TI_Hash *)sha, data, len) ;
+}
+
+WOLFSSL_API int wc_ShaFinal(Sha* sha, byte* hash)
+{
+    return hashFinal((wolfssl_TI_Hash *)sha, hash, SHAMD5_ALGO_SHA1, SHA_DIGEST_SIZE) ;
+}
+
+WOLFSSL_API int wc_ShaGetHash(Sha* sha, byte* hash)
+{
+    return hashGetHash(sha, hash, SHAMD5_ALGO_SHA1, SHA_DIGEST_SIZE) ;
+}
+
+WOLFSSL_API void wc_ShaRestorePos(Sha* s1, Sha* s2) {
+	hashRestorePos((wolfssl_TI_Hash *)s1, (wolfssl_TI_Hash *)s2) ;
+}
+
+WOLFSSL_API int wc_ShaHash(const byte*data, word32 len, byte*hash)
+{ 
+    return hashHash(data, len, hash, SHAMD5_ALGO_SHA1, SHA_DIGEST_SIZE) ;
+}
+
+#endif /* NO_SHA */
+
+#if defined(HAVE_SHA224)
+WOLFSSL_API int wc_InitSha224(Sha224* sha224)
+{
+    if (sha224 == NULL)
+        return 1 ;
+    if(!wolfSSL_TI_CCMInit())return 1 ;
+    return hashInit((wolfssl_TI_Hash *)sha224) ;
+}
+
+WOLFSSL_API int wc_Sha224Update(Sha224* sha224, const byte* data, word32 len)
+{
+    return hashUpdate((wolfssl_TI_Hash *)sha224, data, len) ;
+}
+
+WOLFSSL_API int wc_Sha224Final(Sha224* sha224, byte* hash)
+{
+    return hashFinal((wolfssl_TI_Hash *)sha224, hash, SHAMD5_ALGO_SHA224, SHA224_DIGEST_SIZE) ;
+}
+
+WOLFSSL_API int wc_Sha224GetHash(Sha224* sha224, byte* hash)
+{
+    return hashGetHash(sha224, hash, SHAMD5_ALGO_SHA224, SHA224_DIGEST_SIZE) ;
+}
+
+WOLFSSL_API void wc_Sha224RestorePos(Sha224* s1, Sha224* s2) {
+	hashRestorePos((wolfssl_TI_Hash *)s1, (wolfssl_TI_Hash *)s2) ;
+}
+
+WOLFSSL_API int wc_Sha224Hash(const byte* data, word32 len, byte*hash)
+{ 
+    return hashHash(data, len, hash, SHAMD5_ALGO_SHA224, SHA224_DIGEST_SIZE) ;
+}
+
+#endif /* HAVE_SHA224 */
+
+#if !defined(NO_SHA256)
+WOLFSSL_API int wc_InitSha256(Sha256* sha256)
+{
+    if (sha256 == NULL)
+        return 1 ;
+    if(!wolfSSL_TI_CCMInit())return 1 ;
+    return hashInit((wolfssl_TI_Hash *)sha256) ;
+}
+
+WOLFSSL_API int wc_Sha256Update(Sha256* sha256, const byte* data, word32 len)
+{
+    return hashUpdate((wolfssl_TI_Hash *)sha256, data, len) ;
+}
+
+WOLFSSL_API int wc_Sha256Final(Sha256* sha256, byte* hash)
+{
+    return hashFinal((wolfssl_TI_Hash *)sha256, hash, SHAMD5_ALGO_SHA256, SHA256_DIGEST_SIZE) ;
+}
+
+WOLFSSL_API int wc_Sha256GetHash(Sha256* sha256, byte* hash)
+{
+    return hashGetHash(sha256, hash, SHAMD5_ALGO_SHA256, SHA256_DIGEST_SIZE) ;
+}
+
+WOLFSSL_API void wc_Sha256RestorePos(Sha256* s1, Sha256* s2) {
+	hashRestorePos((wolfssl_TI_Hash *)s1, (wolfssl_TI_Hash *)s2) ;
+}
+
+WOLFSSL_API int wc_Sha256Hash(const byte* data, word32 len, byte*hash)
+{
+    return hashHash(data, len, hash, SHAMD5_ALGO_SHA256, SHA256_DIGEST_SIZE) ;
+}
+#endif
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/pwdbased.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/pwdbased.c
new file mode 100644
index 0000000..b9764d8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/pwdbased.c
@@ -0,0 +1,562 @@
+/* pwdbased.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifndef NO_PWDBASED
+
+#ifdef WOLFSSL_PIC32MZ_HASH
+    #ifndef NO_MD5
+        #define wc_InitMd5   wc_InitMd5_sw
+        #define wc_Md5Update wc_Md5Update_sw
+        #define wc_Md5Final  wc_Md5Final_sw
+    #endif /* NO_MD5 */
+
+    #define wc_InitSha   wc_InitSha_sw
+    #define wc_ShaUpdate wc_ShaUpdate_sw
+    #define wc_ShaFinal  wc_ShaFinal_sw
+
+    #define wc_InitSha256   wc_InitSha256_sw
+    #define wc_Sha256Update wc_Sha256Update_sw
+    #define wc_Sha256Final  wc_Sha256Final_sw
+#endif
+
+#include 
+#include 
+#include 
+#include 
+#if defined(WOLFSSL_SHA512) || defined(WOLFSSL_SHA384)
+    #include 
+#endif
+
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+#ifndef WOLFSSL_HAVE_MIN
+#define WOLFSSL_HAVE_MIN
+
+    static INLINE word32 min(word32 a, word32 b)
+    {
+        return a > b ? b : a;
+    }
+
+#endif /* WOLFSSL_HAVE_MIN */
+
+
+#ifndef NO_SHA
+/* PBKDF1 needs at least SHA available */
+int wc_PBKDF1(byte* output, const byte* passwd, int pLen, const byte* salt,
+           int sLen, int iterations, int kLen, int hashType)
+{
+    Sha  sha;
+#ifndef NO_MD5
+    Md5  md5;
+#endif
+    int  hLen = (int)SHA_DIGEST_SIZE;
+    int  i, ret = 0;
+    byte buffer[SHA_DIGEST_SIZE];  /* max size */
+
+    if (hashType != MD5 && hashType != SHA)
+        return BAD_FUNC_ARG;
+
+#ifndef NO_MD5
+    if (hashType == MD5)
+        hLen = (int)MD5_DIGEST_SIZE;
+#endif
+
+    if (kLen > hLen)
+        return BAD_FUNC_ARG;
+
+    if (iterations < 1)
+        return BAD_FUNC_ARG;
+
+    switch (hashType) {
+#ifndef NO_MD5
+        case MD5:
+            wc_InitMd5(&md5);
+            wc_Md5Update(&md5, passwd, pLen);
+            wc_Md5Update(&md5, salt,   sLen);
+            wc_Md5Final(&md5,  buffer);
+            break;
+#endif /* NO_MD5 */
+        case SHA:
+        default:
+            ret = wc_InitSha(&sha);
+            if (ret != 0)
+                return ret;
+            wc_ShaUpdate(&sha, passwd, pLen);
+            wc_ShaUpdate(&sha, salt,   sLen);
+            wc_ShaFinal(&sha,  buffer);
+            break;
+    }
+
+    for (i = 1; i < iterations; i++) {
+        if (hashType == SHA) {
+            wc_ShaUpdate(&sha, buffer, hLen);
+            wc_ShaFinal(&sha,  buffer);
+        }
+#ifndef NO_MD5
+        else {
+            wc_Md5Update(&md5, buffer, hLen);
+            wc_Md5Final(&md5,  buffer);
+        }
+#endif
+    }
+    XMEMCPY(output, buffer, kLen);
+
+    return 0;
+}
+#endif /* NO_SHA */
+
+
+int GetDigestSize(int hashType)
+{
+    int hLen;
+
+    switch (hashType) {
+#ifndef NO_MD5
+        case MD5:
+            hLen = MD5_DIGEST_SIZE;
+            break;
+#endif
+#ifndef NO_SHA
+        case SHA:
+            hLen = SHA_DIGEST_SIZE;
+            break;
+#endif
+#ifndef NO_SHA256
+        case SHA256:
+            hLen = SHA256_DIGEST_SIZE;
+            break;
+#endif
+#ifdef WOLFSSL_SHA512
+        case SHA512:
+            hLen = SHA512_DIGEST_SIZE;
+            break;
+#endif
+        default:
+            return BAD_FUNC_ARG;
+    }
+
+    return hLen;
+}
+
+
+int wc_PBKDF2(byte* output, const byte* passwd, int pLen, const byte* salt,
+           int sLen, int iterations, int kLen, int hashType)
+{
+    word32 i = 1;
+    int    hLen;
+    int    j, ret;
+    Hmac   hmac;
+#ifdef WOLFSSL_SMALL_STACK
+    byte*  buffer;
+#else
+    byte   buffer[MAX_DIGEST_SIZE];
+#endif
+
+    hLen = GetDigestSize(hashType);
+    if (hLen < 0)
+        return BAD_FUNC_ARG;
+
+#ifdef WOLFSSL_SMALL_STACK
+    buffer = (byte*)XMALLOC(MAX_DIGEST_SIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (buffer == NULL)
+        return MEMORY_E;
+#endif
+
+    ret = wc_HmacSetKey(&hmac, hashType, passwd, pLen);
+
+    if (ret == 0) {
+        while (kLen) {
+            int currentLen;
+
+            ret = wc_HmacUpdate(&hmac, salt, sLen);
+            if (ret != 0)
+                break;
+
+            /* encode i */
+            for (j = 0; j < 4; j++) {
+                byte b = (byte)(i >> ((3-j) * 8));
+
+                ret = wc_HmacUpdate(&hmac, &b, 1);
+                if (ret != 0)
+                    break;
+            }
+
+            /* check ret from inside for loop */
+            if (ret != 0)
+                break;
+
+            ret = wc_HmacFinal(&hmac, buffer);
+            if (ret != 0)
+                break;
+
+            currentLen = min(kLen, hLen);
+            XMEMCPY(output, buffer, currentLen);
+
+            for (j = 1; j < iterations; j++) {
+                ret = wc_HmacUpdate(&hmac, buffer, hLen);
+                if (ret != 0)
+                    break;
+                ret = wc_HmacFinal(&hmac, buffer);
+                if (ret != 0)
+                    break;
+                xorbuf(output, buffer, currentLen);
+            }
+
+            /* check ret from inside for loop */
+            if (ret != 0)
+                break;
+
+            output += currentLen;
+            kLen   -= currentLen;
+            i++;
+        }
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(buffer, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+#ifdef WOLFSSL_SHA512
+    #define PBKDF_DIGEST_SIZE SHA512_BLOCK_SIZE
+#elif !defined(NO_SHA256)
+    #define PBKDF_DIGEST_SIZE SHA256_BLOCK_SIZE
+#else
+    #define PBKDF_DIGEST_SIZE SHA_DIGEST_SIZE
+#endif
+
+/* helper for wc_PKCS12_PBKDF(), sets block and digest sizes */
+int GetPKCS12HashSizes(int hashType, word32* v, word32* u)
+{
+    if (!v || !u)
+        return BAD_FUNC_ARG;
+
+    switch (hashType) {
+#ifndef NO_MD5
+        case MD5:
+            *v = MD5_BLOCK_SIZE;
+            *u = MD5_DIGEST_SIZE;
+            break;
+#endif
+#ifndef NO_SHA
+        case SHA:
+            *v = SHA_BLOCK_SIZE;
+            *u = SHA_DIGEST_SIZE;
+            break;
+#endif
+#ifndef NO_SHA256
+        case SHA256:
+            *v = SHA256_BLOCK_SIZE;
+            *u = SHA256_DIGEST_SIZE;
+            break;
+#endif
+#ifdef WOLFSSL_SHA512
+        case SHA512:
+            *v = SHA512_BLOCK_SIZE;
+            *u = SHA512_DIGEST_SIZE;
+            break;
+#endif
+        default:
+            return BAD_FUNC_ARG;
+    }
+
+    return 0;
+}
+
+/* helper for PKCS12_PBKDF(), does hash operation */
+int DoPKCS12Hash(int hashType, byte* buffer, word32 totalLen,
+                 byte* Ai, word32 u, int iterations)
+{
+    int i;
+    int ret = 0;
+
+    if (buffer == NULL || Ai == NULL)
+        return BAD_FUNC_ARG;
+
+    switch (hashType) {
+#ifndef NO_MD5
+        case MD5:
+            {
+                Md5 md5;
+                wc_InitMd5(&md5);
+                wc_Md5Update(&md5, buffer, totalLen);
+                wc_Md5Final(&md5, Ai);
+
+                for (i = 1; i < iterations; i++) {
+                    wc_Md5Update(&md5, Ai, u);
+                    wc_Md5Final(&md5, Ai);
+                }
+            }
+            break;
+#endif /* NO_MD5 */
+#ifndef NO_SHA
+        case SHA:
+            {
+                Sha sha;
+                ret = wc_InitSha(&sha);
+                if (ret != 0)
+                    break;
+                wc_ShaUpdate(&sha, buffer, totalLen);
+                wc_ShaFinal(&sha, Ai);
+
+                for (i = 1; i < iterations; i++) {
+                    wc_ShaUpdate(&sha, Ai, u);
+                    wc_ShaFinal(&sha, Ai);
+                }
+            }
+            break;
+#endif /* NO_SHA */
+#ifndef NO_SHA256
+        case SHA256:
+            {
+                Sha256 sha256;
+                ret = wc_InitSha256(&sha256);
+                if (ret != 0)
+                    break;
+
+                ret = wc_Sha256Update(&sha256, buffer, totalLen);
+                if (ret != 0)
+                    break;
+
+                ret = wc_Sha256Final(&sha256, Ai);
+                if (ret != 0)
+                    break;
+
+                for (i = 1; i < iterations; i++) {
+                    ret = wc_Sha256Update(&sha256, Ai, u);
+                    if (ret != 0)
+                        break;
+
+                    ret = wc_Sha256Final(&sha256, Ai);
+                    if (ret != 0)
+                        break;
+                }
+            }
+            break;
+#endif /* NO_SHA256 */
+#ifdef WOLFSSL_SHA512
+        case SHA512:
+            {
+                Sha512 sha512;
+                ret = wc_InitSha512(&sha512);
+                if (ret != 0)
+                    break;
+
+                ret = wc_Sha512Update(&sha512, buffer, totalLen);
+                if (ret != 0)
+                    break;
+
+                ret = wc_Sha512Final(&sha512, Ai);
+                if (ret != 0)
+                    break;
+
+                for (i = 1; i < iterations; i++) {
+                    ret = wc_Sha512Update(&sha512, Ai, u);
+                    if (ret != 0)
+                        break;
+
+                    ret = wc_Sha512Final(&sha512, Ai);
+                    if (ret != 0)
+                        break;
+                }
+            }
+            break;
+#endif /* WOLFSSL_SHA512 */
+
+        default:
+            ret = BAD_FUNC_ARG;
+            break;
+    }
+
+    return ret;
+}
+
+int wc_PKCS12_PBKDF(byte* output, const byte* passwd, int passLen,const byte* salt,
+                 int saltLen, int iterations, int kLen, int hashType, int id)
+{
+    /* all in bytes instead of bits */
+    word32 u, v, dLen, pLen, iLen, sLen, totalLen;
+    int    dynamic = 0;
+    int    ret = 0;
+    int    i;
+    byte   *D, *S, *P, *I;
+#ifdef WOLFSSL_SMALL_STACK
+    byte   staticBuffer[1]; /* force dynamic usage */
+#else
+    byte   staticBuffer[1024];
+#endif
+    byte*  buffer = staticBuffer;
+
+#ifdef WOLFSSL_SMALL_STACK
+    byte*  Ai;
+    byte*  B;
+#else
+    byte   Ai[PBKDF_DIGEST_SIZE];
+    byte   B[PBKDF_DIGEST_SIZE];
+#endif
+
+    if (!iterations)
+        iterations = 1;
+
+    ret = GetPKCS12HashSizes(hashType, &v, &u);
+    if (ret < 0)
+        return BAD_FUNC_ARG;
+
+#ifdef WOLFSSL_SMALL_STACK
+    Ai = (byte*)XMALLOC(PBKDF_DIGEST_SIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (Ai == NULL)
+        return MEMORY_E;
+
+    B = (byte*)XMALLOC(PBKDF_DIGEST_SIZE, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (B == NULL) {
+        XFREE(Ai, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        return MEMORY_E;
+    }
+#endif
+
+    XMEMSET(Ai, 0, PBKDF_DIGEST_SIZE);
+    XMEMSET(B,  0, PBKDF_DIGEST_SIZE);
+
+    dLen = v;
+    sLen =  v * ((saltLen + v - 1) / v);
+    if (passLen)
+        pLen = v * ((passLen + v - 1) / v);
+    else
+        pLen = 0;
+    iLen = sLen + pLen;
+
+    totalLen = dLen + sLen + pLen;
+
+    if (totalLen > sizeof(staticBuffer)) {
+        buffer = (byte*)XMALLOC(totalLen, 0, DYNAMIC_TYPE_KEY);
+        if (buffer == NULL) {
+#ifdef WOLFSSL_SMALL_STACK
+            XFREE(Ai, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+            XFREE(B,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+            return MEMORY_E;
+        }
+        dynamic = 1;
+    }
+
+    D = buffer;
+    S = D + dLen;
+    P = S + sLen;
+    I = S;
+
+    XMEMSET(D, id, dLen);
+
+    for (i = 0; i < (int)sLen; i++)
+        S[i] = salt[i % saltLen];
+    for (i = 0; i < (int)pLen; i++)
+        P[i] = passwd[i % passLen];
+
+    while (kLen > 0) {
+        word32 currentLen;
+        mp_int B1;
+
+        ret = DoPKCS12Hash(hashType, buffer, totalLen, Ai, u, iterations);
+        if (ret < 0)
+            break;
+
+        for (i = 0; i < (int)v; i++)
+            B[i] = Ai[i % u];
+
+        if (mp_init(&B1) != MP_OKAY)
+            ret = MP_INIT_E;
+        else if (mp_read_unsigned_bin(&B1, B, v) != MP_OKAY)
+            ret = MP_READ_E;
+        else if (mp_add_d(&B1, (mp_digit)1, &B1) != MP_OKAY)
+            ret = MP_ADD_E;
+
+        if (ret != 0) {
+            mp_clear(&B1);
+            break;
+        }
+
+        for (i = 0; i < (int)iLen; i += v) {
+            int    outSz;
+            mp_int i1;
+            mp_int res;
+
+            if (mp_init_multi(&i1, &res, NULL, NULL, NULL, NULL) != MP_OKAY) {
+                ret = MP_INIT_E;
+                break;
+            }
+            if (mp_read_unsigned_bin(&i1, I + i, v) != MP_OKAY)
+                ret = MP_READ_E;
+            else if (mp_add(&i1, &B1, &res) != MP_OKAY)
+                ret = MP_ADD_E;
+            else if ( (outSz = mp_unsigned_bin_size(&res)) < 0)
+                ret = MP_TO_E;
+            else {
+                if (outSz > (int)v) {
+                    /* take off MSB */
+                    byte  tmp[129];
+                    ret = mp_to_unsigned_bin(&res, tmp);
+                    XMEMCPY(I + i, tmp + 1, v);
+                }
+                else if (outSz < (int)v) {
+                    XMEMSET(I + i, 0, v - outSz);
+                    ret = mp_to_unsigned_bin(&res, I + i + v - outSz);
+                }
+                else
+                    ret = mp_to_unsigned_bin(&res, I + i);
+            }
+
+            mp_clear(&i1);
+            mp_clear(&res);
+            if (ret < 0) break;
+        }
+
+        currentLen = min(kLen, (int)u);
+        XMEMCPY(output, Ai, currentLen);
+        output += currentLen;
+        kLen   -= currentLen;
+        mp_clear(&B1);
+    }
+
+    if (dynamic) XFREE(buffer, 0, DYNAMIC_TYPE_KEY);
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(Ai, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(B,  NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+#undef PBKDF_DIGEST_SIZE
+
+#endif /* NO_PWDBASED */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/rabbit.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/rabbit.c
new file mode 100644
index 0000000..fc78611
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/rabbit.c
@@ -0,0 +1,310 @@
+/* rabbit.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifndef NO_RABBIT
+
+#include 
+#include 
+#include 
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+
+#ifdef BIG_ENDIAN_ORDER
+    #define LITTLE32(x) ByteReverseWord32(x)
+#else
+    #define LITTLE32(x) (x)
+#endif
+
+#define U32V(x) ((word32)(x) & 0xFFFFFFFFU)
+
+
+/* Square a 32-bit unsigned integer to obtain the 64-bit result and return */
+/* the upper 32 bits XOR the lower 32 bits */
+static word32 RABBIT_g_func(word32 x)
+{
+    /* Temporary variables */
+    word32 a, b, h, l;
+
+    /* Construct high and low argument for squaring */
+    a = x&0xFFFF;
+    b = x>>16;
+
+    /* Calculate high and low result of squaring */
+    h = (((U32V(a*a)>>17) + U32V(a*b))>>15) + b*b;
+    l = x*x;
+
+    /* Return high XOR low */
+    return U32V(h^l);
+}
+
+
+/* Calculate the next internal state */
+static void RABBIT_next_state(RabbitCtx* ctx)
+{
+    /* Temporary variables */
+    word32 g[8], c_old[8], i;
+
+    /* Save old counter values */
+    for (i=0; i<8; i++)
+        c_old[i] = ctx->c[i];
+
+    /* Calculate new counter values */
+    ctx->c[0] = U32V(ctx->c[0] + 0x4D34D34D + ctx->carry);
+    ctx->c[1] = U32V(ctx->c[1] + 0xD34D34D3 + (ctx->c[0] < c_old[0]));
+    ctx->c[2] = U32V(ctx->c[2] + 0x34D34D34 + (ctx->c[1] < c_old[1]));
+    ctx->c[3] = U32V(ctx->c[3] + 0x4D34D34D + (ctx->c[2] < c_old[2]));
+    ctx->c[4] = U32V(ctx->c[4] + 0xD34D34D3 + (ctx->c[3] < c_old[3]));
+    ctx->c[5] = U32V(ctx->c[5] + 0x34D34D34 + (ctx->c[4] < c_old[4]));
+    ctx->c[6] = U32V(ctx->c[6] + 0x4D34D34D + (ctx->c[5] < c_old[5]));
+    ctx->c[7] = U32V(ctx->c[7] + 0xD34D34D3 + (ctx->c[6] < c_old[6]));
+    ctx->carry = (ctx->c[7] < c_old[7]);
+   
+    /* Calculate the g-values */
+    for (i=0;i<8;i++)
+        g[i] = RABBIT_g_func(U32V(ctx->x[i] + ctx->c[i]));
+
+    /* Calculate new state values */
+    ctx->x[0] = U32V(g[0] + rotlFixed(g[7],16) + rotlFixed(g[6], 16));
+    ctx->x[1] = U32V(g[1] + rotlFixed(g[0], 8) + g[7]);
+    ctx->x[2] = U32V(g[2] + rotlFixed(g[1],16) + rotlFixed(g[0], 16));
+    ctx->x[3] = U32V(g[3] + rotlFixed(g[2], 8) + g[1]);
+    ctx->x[4] = U32V(g[4] + rotlFixed(g[3],16) + rotlFixed(g[2], 16));
+    ctx->x[5] = U32V(g[5] + rotlFixed(g[4], 8) + g[3]);
+    ctx->x[6] = U32V(g[6] + rotlFixed(g[5],16) + rotlFixed(g[4], 16));
+    ctx->x[7] = U32V(g[7] + rotlFixed(g[6], 8) + g[5]);
+}
+
+
+/* IV setup */
+static void wc_RabbitSetIV(Rabbit* ctx, const byte* inIv)
+{
+    /* Temporary variables */
+    word32 i0, i1, i2, i3, i;
+    word32 iv[2];
+
+    if (inIv)
+        XMEMCPY(iv, inIv, sizeof(iv));
+    else
+        XMEMSET(iv,    0, sizeof(iv));
+      
+    /* Generate four subvectors */
+    i0 = LITTLE32(iv[0]);
+    i2 = LITTLE32(iv[1]);
+    i1 = (i0>>16) | (i2&0xFFFF0000);
+    i3 = (i2<<16) | (i0&0x0000FFFF);
+
+    /* Modify counter values */
+    ctx->workCtx.c[0] = ctx->masterCtx.c[0] ^ i0;
+    ctx->workCtx.c[1] = ctx->masterCtx.c[1] ^ i1;
+    ctx->workCtx.c[2] = ctx->masterCtx.c[2] ^ i2;
+    ctx->workCtx.c[3] = ctx->masterCtx.c[3] ^ i3;
+    ctx->workCtx.c[4] = ctx->masterCtx.c[4] ^ i0;
+    ctx->workCtx.c[5] = ctx->masterCtx.c[5] ^ i1;
+    ctx->workCtx.c[6] = ctx->masterCtx.c[6] ^ i2;
+    ctx->workCtx.c[7] = ctx->masterCtx.c[7] ^ i3;
+
+    /* Copy state variables */
+    for (i=0; i<8; i++)
+        ctx->workCtx.x[i] = ctx->masterCtx.x[i];
+    ctx->workCtx.carry = ctx->masterCtx.carry;
+
+    /* Iterate the system four times */
+    for (i=0; i<4; i++)
+        RABBIT_next_state(&(ctx->workCtx));
+}
+
+
+/* Key setup */
+static INLINE int DoKey(Rabbit* ctx, const byte* key, const byte* iv)
+{
+    /* Temporary variables */
+    word32 k0, k1, k2, k3, i;
+
+    /* Generate four subkeys */
+    k0 = LITTLE32(*(word32*)(key+ 0));
+    k1 = LITTLE32(*(word32*)(key+ 4));
+    k2 = LITTLE32(*(word32*)(key+ 8));
+    k3 = LITTLE32(*(word32*)(key+12));
+
+    /* Generate initial state variables */
+    ctx->masterCtx.x[0] = k0;
+    ctx->masterCtx.x[2] = k1;
+    ctx->masterCtx.x[4] = k2;
+    ctx->masterCtx.x[6] = k3;
+    ctx->masterCtx.x[1] = U32V(k3<<16) | (k2>>16);
+    ctx->masterCtx.x[3] = U32V(k0<<16) | (k3>>16);
+    ctx->masterCtx.x[5] = U32V(k1<<16) | (k0>>16);
+    ctx->masterCtx.x[7] = U32V(k2<<16) | (k1>>16);
+
+    /* Generate initial counter values */
+    ctx->masterCtx.c[0] = rotlFixed(k2, 16);
+    ctx->masterCtx.c[2] = rotlFixed(k3, 16);
+    ctx->masterCtx.c[4] = rotlFixed(k0, 16);
+    ctx->masterCtx.c[6] = rotlFixed(k1, 16);
+    ctx->masterCtx.c[1] = (k0&0xFFFF0000) | (k1&0xFFFF);
+    ctx->masterCtx.c[3] = (k1&0xFFFF0000) | (k2&0xFFFF);
+    ctx->masterCtx.c[5] = (k2&0xFFFF0000) | (k3&0xFFFF);
+    ctx->masterCtx.c[7] = (k3&0xFFFF0000) | (k0&0xFFFF);
+
+    /* Clear carry bit */
+    ctx->masterCtx.carry = 0;
+
+    /* Iterate the system four times */
+    for (i=0; i<4; i++)
+        RABBIT_next_state(&(ctx->masterCtx));
+
+    /* Modify the counters */
+    for (i=0; i<8; i++)
+        ctx->masterCtx.c[i] ^= ctx->masterCtx.x[(i+4)&0x7];
+
+    /* Copy master instance to work instance */
+    for (i=0; i<8; i++) {
+        ctx->workCtx.x[i] = ctx->masterCtx.x[i];
+        ctx->workCtx.c[i] = ctx->masterCtx.c[i];
+    }
+    ctx->workCtx.carry = ctx->masterCtx.carry;
+
+    wc_RabbitSetIV(ctx, iv);
+
+    return 0;
+}
+
+
+/* Key setup */
+int wc_RabbitSetKey(Rabbit* ctx, const byte* key, const byte* iv)
+{
+#ifdef XSTREAM_ALIGN
+    if ((wolfssl_word)key % 4) {
+        int alignKey[4];
+
+        /* iv aligned in SetIV */
+        WOLFSSL_MSG("wc_RabbitSetKey unaligned key");
+
+        XMEMCPY(alignKey, key, sizeof(alignKey));
+
+        return DoKey(ctx, (const byte*)alignKey, iv);
+    }
+#endif /* XSTREAM_ALIGN */
+
+    return DoKey(ctx, key, iv);
+}
+
+
+/* Encrypt/decrypt a message of any size */
+static INLINE int DoProcess(Rabbit* ctx, byte* output, const byte* input,
+                            word32 msglen)
+{
+    /* Encrypt/decrypt all full blocks */
+    while (msglen >= 16) {
+        /* Iterate the system */
+        RABBIT_next_state(&(ctx->workCtx));
+
+        /* Encrypt/decrypt 16 bytes of data */
+        *(word32*)(output+ 0) = *(word32*)(input+ 0) ^
+                   LITTLE32(ctx->workCtx.x[0] ^ (ctx->workCtx.x[5]>>16) ^
+                   U32V(ctx->workCtx.x[3]<<16));
+        *(word32*)(output+ 4) = *(word32*)(input+ 4) ^
+                   LITTLE32(ctx->workCtx.x[2] ^ (ctx->workCtx.x[7]>>16) ^
+                   U32V(ctx->workCtx.x[5]<<16));
+        *(word32*)(output+ 8) = *(word32*)(input+ 8) ^
+                   LITTLE32(ctx->workCtx.x[4] ^ (ctx->workCtx.x[1]>>16) ^
+                   U32V(ctx->workCtx.x[7]<<16));
+        *(word32*)(output+12) = *(word32*)(input+12) ^
+                   LITTLE32(ctx->workCtx.x[6] ^ (ctx->workCtx.x[3]>>16) ^
+                   U32V(ctx->workCtx.x[1]<<16));
+
+        /* Increment pointers and decrement length */
+        input  += 16;
+        output += 16;
+        msglen -= 16;
+    }
+
+    /* Encrypt/decrypt remaining data */
+    if (msglen) {
+
+        word32 i;
+        word32 tmp[4];
+        byte*  buffer = (byte*)tmp;
+
+        XMEMSET(tmp, 0, sizeof(tmp));   /* help static analysis */
+
+        /* Iterate the system */
+        RABBIT_next_state(&(ctx->workCtx));
+
+        /* Generate 16 bytes of pseudo-random data */
+        tmp[0] = LITTLE32(ctx->workCtx.x[0] ^
+                  (ctx->workCtx.x[5]>>16) ^ U32V(ctx->workCtx.x[3]<<16));
+        tmp[1] = LITTLE32(ctx->workCtx.x[2] ^ 
+                  (ctx->workCtx.x[7]>>16) ^ U32V(ctx->workCtx.x[5]<<16));
+        tmp[2] = LITTLE32(ctx->workCtx.x[4] ^ 
+                  (ctx->workCtx.x[1]>>16) ^ U32V(ctx->workCtx.x[7]<<16));
+        tmp[3] = LITTLE32(ctx->workCtx.x[6] ^ 
+                  (ctx->workCtx.x[3]>>16) ^ U32V(ctx->workCtx.x[1]<<16));
+
+        /* Encrypt/decrypt the data */
+        for (i=0; i
+#endif
+ 
+#include 
+
+/* on HPUX 11 you may need to install /dev/random see
+   http://h20293.www2.hp.com/portal/swdepot/displayProductInfo.do?productNumber=KRNG11I
+
+*/
+
+#include 
+
+#ifdef HAVE_FIPS
+int wc_GenerateSeed(OS_Seed* os, byte* seed, word32 sz)
+{
+    return GenerateSeed(os, seed, sz);
+}
+
+#ifdef HAVE_CAVIUM
+    int  wc_InitRngCavium(RNG* rng, int i)
+    {
+        return InitRngCavium(rng, i);
+    }
+#endif
+
+
+int  wc_InitRng(RNG* rng)
+{
+    return InitRng_fips(rng);
+}
+
+
+int  wc_RNG_GenerateBlock(RNG* rng, byte* b, word32 sz)
+{
+    return RNG_GenerateBlock_fips(rng, b, sz);
+}
+
+
+int  wc_RNG_GenerateByte(RNG* rng, byte* b)
+{
+    return RNG_GenerateByte(rng, b);
+}
+
+#if defined(HAVE_HASHDRBG) || defined(NO_RC4)
+
+    int wc_FreeRng(RNG* rng)
+    {
+        return FreeRng_fips(rng);
+    }
+
+
+    int wc_RNG_HealthTest(int reseed,
+                                        const byte* entropyA, word32 entropyASz,
+                                        const byte* entropyB, word32 entropyBSz,
+                                        byte* output, word32 outputSz)
+    {
+        return RNG_HealthTest_fips(reseed, entropyA, entropyASz,
+                              entropyB, entropyBSz, output, outputSz);
+    }
+#endif /* HAVE_HASHDRBG || NO_RC4 */
+#else /* else build without fips */
+#include 
+
+#if defined(HAVE_HASHDRBG) || defined(NO_RC4)
+
+    #include 
+
+    #ifdef NO_INLINE
+        #include 
+    #else
+        #include 
+    #endif
+#endif /* HAVE_HASHDRBG || NO_RC4 */
+
+#if defined(USE_WINDOWS_API)
+    #ifndef _WIN32_WINNT
+        #define _WIN32_WINNT 0x0400
+    #endif
+    #include 
+    #include 
+#else
+    #if !defined(NO_DEV_RANDOM) && !defined(CUSTOM_RAND_GENERATE) && \
+                          !defined(WOLFSSL_MDK_ARM) && !defined(WOLFSSL_IAR_ARM)
+            #include 
+        #ifndef EBSNET
+            #include 
+        #endif
+    #else
+        /* include headers that may be needed to get good seed */
+    #endif
+#endif /* USE_WINDOWS_API */
+    
+#ifdef HAVE_INTEL_RDGEN
+    static int wc_InitRng_IntelRD(void) ;
+    #if defined(HAVE_HASHDRBG) || defined(NO_RC4)
+	static int wc_GenerateSeed_IntelRD(OS_Seed* os, byte* output, word32 sz) ;
+    #else
+    static int wc_GenerateRand_IntelRD(OS_Seed* os, byte* output, word32 sz) ;
+    #endif
+    static word32 cpuid_check = 0 ;
+    static word32 cpuid_flags = 0 ;
+    #define CPUID_RDRAND 0x4
+    #define CPUID_RDSEED 0x8
+    #define IS_INTEL_RDRAND     (cpuid_flags&CPUID_RDRAND)
+    #define IS_INTEL_RDSEED     (cpuid_flags&CPUID_RDSEED)
+#endif
+
+#if defined(HAVE_HASHDRBG) || defined(NO_RC4)
+
+/* Start NIST DRBG code */
+
+#define OUTPUT_BLOCK_LEN  (SHA256_DIGEST_SIZE)
+#define MAX_REQUEST_LEN   (0x10000)
+#define RESEED_INTERVAL   (1000000)
+#define SECURITY_STRENGTH (256)
+#define ENTROPY_SZ        (SECURITY_STRENGTH/8)
+#define NONCE_SZ          (ENTROPY_SZ/2)
+#define ENTROPY_NONCE_SZ  (ENTROPY_SZ+NONCE_SZ)
+
+/* Internal return codes */
+#define DRBG_SUCCESS      0
+#define DRBG_ERROR        1
+#define DRBG_FAILURE      2
+#define DRBG_NEED_RESEED  3
+#define DRBG_CONT_FAILURE 4
+
+/* RNG health states */
+#define DRBG_NOT_INIT     0
+#define DRBG_OK           1
+#define DRBG_FAILED       2
+#define DRBG_CONT_FAILED  3
+
+
+enum {
+    drbgInitC     = 0,
+    drbgReseed    = 1,
+    drbgGenerateW = 2,
+    drbgGenerateH = 3,
+    drbgInitV
+};
+
+
+typedef struct DRBG {
+    word32 reseedCtr;
+    word32 lastBlock;
+    byte V[DRBG_SEED_LEN];
+    byte C[DRBG_SEED_LEN];
+    byte   matchCount;
+} DRBG;
+
+
+static int wc_RNG_HealthTestLocal(int reseed);
+
+/* Hash Derivation Function */
+/* Returns: DRBG_SUCCESS or DRBG_FAILURE */
+static int Hash_df(DRBG* drbg, byte* out, word32 outSz, byte type,
+                                                  const byte* inA, word32 inASz,
+                                                  const byte* inB, word32 inBSz)
+{
+    byte ctr;
+    int i;
+    int len;
+    word32 bits = (outSz * 8); /* reverse byte order */
+    Sha256 sha;
+    byte digest[SHA256_DIGEST_SIZE];
+
+    (void)drbg;
+    #ifdef LITTLE_ENDIAN_ORDER
+        bits = ByteReverseWord32(bits);
+    #endif
+    len = (outSz / OUTPUT_BLOCK_LEN)
+        + ((outSz % OUTPUT_BLOCK_LEN) ? 1 : 0);
+
+    for (i = 0, ctr = 1; i < len; i++, ctr++)
+    {
+        if (wc_InitSha256(&sha) != 0)
+            return DRBG_FAILURE;
+
+        if (wc_Sha256Update(&sha, &ctr, sizeof(ctr)) != 0)
+            return DRBG_FAILURE;
+
+        if (wc_Sha256Update(&sha, (byte*)&bits, sizeof(bits)) != 0)
+            return DRBG_FAILURE;
+
+        /* churning V is the only string that doesn't have the type added */
+        if (type != drbgInitV)
+            if (wc_Sha256Update(&sha, &type, sizeof(type)) != 0)
+                return DRBG_FAILURE;
+
+        if (wc_Sha256Update(&sha, inA, inASz) != 0)
+            return DRBG_FAILURE;
+
+        if (inB != NULL && inBSz > 0)
+            if (wc_Sha256Update(&sha, inB, inBSz) != 0)
+                return DRBG_FAILURE;
+
+        if (wc_Sha256Final(&sha, digest) != 0)
+            return DRBG_FAILURE;
+
+        if (outSz > OUTPUT_BLOCK_LEN) {
+            XMEMCPY(out, digest, OUTPUT_BLOCK_LEN);
+            outSz -= OUTPUT_BLOCK_LEN;
+            out += OUTPUT_BLOCK_LEN;
+        }
+        else {
+            XMEMCPY(out, digest, outSz);
+        }
+    }
+    ForceZero(digest, sizeof(digest));
+
+    return DRBG_SUCCESS;
+}
+
+
+/* Returns: DRBG_SUCCESS or DRBG_FAILURE */
+static int Hash_DRBG_Reseed(DRBG* drbg, const byte* entropy, word32 entropySz)
+{
+    byte seed[DRBG_SEED_LEN];
+
+    if (Hash_df(drbg, seed, sizeof(seed), drbgReseed, drbg->V, sizeof(drbg->V),
+                                          entropy, entropySz) != DRBG_SUCCESS) {
+        return DRBG_FAILURE;
+    }
+
+    XMEMCPY(drbg->V, seed, sizeof(drbg->V));
+    ForceZero(seed, sizeof(seed));
+
+    if (Hash_df(drbg, drbg->C, sizeof(drbg->C), drbgInitC, drbg->V,
+                                    sizeof(drbg->V), NULL, 0) != DRBG_SUCCESS) {
+        return DRBG_FAILURE;
+    }
+
+    drbg->reseedCtr = 1;
+    drbg->lastBlock = 0;
+    drbg->matchCount = 0;
+    return DRBG_SUCCESS;
+}
+
+static INLINE void array_add_one(byte* data, word32 dataSz)
+{
+    int i;
+
+    for (i = dataSz - 1; i >= 0; i--)
+    {
+        data[i]++;
+        if (data[i] != 0) break;
+    }
+}
+
+
+/* Returns: DRBG_SUCCESS or DRBG_FAILURE */
+static int Hash_gen(DRBG* drbg, byte* out, word32 outSz, const byte* V)
+{
+    byte data[DRBG_SEED_LEN];
+    int i;
+    int len;
+    word32 checkBlock;
+    Sha256 sha;
+    byte digest[SHA256_DIGEST_SIZE];
+
+    /* Special case: outSz is 0 and out is NULL. wc_Generate a block to save for
+     * the continuous test. */
+
+    if (outSz == 0) outSz = 1;
+
+    len = (outSz / OUTPUT_BLOCK_LEN) + ((outSz % OUTPUT_BLOCK_LEN) ? 1 : 0);
+
+    XMEMCPY(data, V, sizeof(data));
+    for (i = 0; i < len; i++) {
+        if (wc_InitSha256(&sha) != 0 ||
+            wc_Sha256Update(&sha, data, sizeof(data)) != 0 ||
+            wc_Sha256Final(&sha, digest) != 0) {
+
+            return DRBG_FAILURE;
+        }
+
+        XMEMCPY(&checkBlock, digest, sizeof(word32));
+        if (drbg->reseedCtr > 1 && checkBlock == drbg->lastBlock) {
+            if (drbg->matchCount == 1) {
+                return DRBG_CONT_FAILURE;
+            }
+            else {
+                if (i == len) {
+                    len++;
+                }
+                drbg->matchCount = 1;
+            }
+        }
+        else {
+            drbg->matchCount = 0;
+            drbg->lastBlock = checkBlock;
+        }
+
+        if (outSz >= OUTPUT_BLOCK_LEN) {
+            XMEMCPY(out, digest, OUTPUT_BLOCK_LEN);
+            outSz -= OUTPUT_BLOCK_LEN;
+            out += OUTPUT_BLOCK_LEN;
+            array_add_one(data, DRBG_SEED_LEN);
+        }
+        else if (out != NULL && outSz != 0) {
+            XMEMCPY(out, digest, outSz);
+            outSz = 0;
+        }
+    }
+    ForceZero(data, sizeof(data));
+
+    return DRBG_SUCCESS;
+}
+
+
+static INLINE void array_add(byte* d, word32 dLen, const byte* s, word32 sLen)
+{
+    word16 carry = 0;
+
+    if (dLen > 0 && sLen > 0 && dLen >= sLen) {
+        int sIdx, dIdx;
+
+        for (sIdx = sLen - 1, dIdx = dLen - 1; sIdx >= 0; dIdx--, sIdx--)
+        {
+            carry += d[dIdx] + s[sIdx];
+            d[dIdx] = (byte)carry;
+            carry >>= 8;
+        }
+
+        for (; carry != 0 && dIdx >= 0; dIdx--) {
+            carry += d[dIdx];
+            d[dIdx] = (byte)carry;
+            carry >>= 8;
+        }
+    }
+}
+
+
+/* Returns: DRBG_SUCCESS, DRBG_NEED_RESEED, or DRBG_FAILURE */
+static int Hash_DRBG_Generate(DRBG* drbg, byte* out, word32 outSz)
+{
+    int ret = DRBG_NEED_RESEED;
+    Sha256 sha;
+    byte digest[SHA256_DIGEST_SIZE];
+
+    if (drbg->reseedCtr != RESEED_INTERVAL) {
+        byte type = drbgGenerateH;
+        word32 reseedCtr = drbg->reseedCtr;
+
+        ret = Hash_gen(drbg, out, outSz, drbg->V);
+        if (ret == DRBG_SUCCESS) {
+            if (wc_InitSha256(&sha) != 0 ||
+                wc_Sha256Update(&sha, &type, sizeof(type)) != 0 ||
+                wc_Sha256Update(&sha, drbg->V, sizeof(drbg->V)) != 0 ||
+                wc_Sha256Final(&sha, digest) != 0) {
+
+                ret = DRBG_FAILURE;
+            }
+            else {
+                array_add(drbg->V, sizeof(drbg->V), digest, sizeof(digest));
+                array_add(drbg->V, sizeof(drbg->V), drbg->C, sizeof(drbg->C));
+                #ifdef LITTLE_ENDIAN_ORDER
+                    reseedCtr = ByteReverseWord32(reseedCtr);
+                #endif
+                array_add(drbg->V, sizeof(drbg->V),
+                                          (byte*)&reseedCtr, sizeof(reseedCtr));
+                ret = DRBG_SUCCESS;
+            }
+            drbg->reseedCtr++;
+        }
+    }
+    ForceZero(digest, sizeof(digest));
+
+    return ret;
+}
+
+
+/* Returns: DRBG_SUCCESS or DRBG_FAILURE */
+static int Hash_DRBG_Instantiate(DRBG* drbg, const byte* seed, word32 seedSz,
+                                             const byte* nonce, word32 nonceSz)
+{
+    int ret = DRBG_FAILURE;
+
+    XMEMSET(drbg, 0, sizeof(DRBG));
+
+    if (Hash_df(drbg, drbg->V, sizeof(drbg->V), drbgInitV, seed, seedSz,
+                                              nonce, nonceSz) == DRBG_SUCCESS &&
+        Hash_df(drbg, drbg->C, sizeof(drbg->C), drbgInitC, drbg->V,
+                                    sizeof(drbg->V), NULL, 0) == DRBG_SUCCESS) {
+
+        drbg->reseedCtr = 1;
+        drbg->lastBlock = 0;
+        drbg->matchCount = 0;
+        ret = DRBG_SUCCESS;
+    }
+
+    return ret;
+}
+
+
+/* Returns: DRBG_SUCCESS or DRBG_FAILURE */
+static int Hash_DRBG_Uninstantiate(DRBG* drbg)
+{
+    word32 i;
+    int    compareSum = 0;
+    byte*  compareDrbg = (byte*)drbg;
+
+    ForceZero(drbg, sizeof(DRBG));
+
+    for (i = 0; i < sizeof(DRBG); i++)
+        compareSum |= compareDrbg[i] ^ 0;
+
+    return (compareSum == 0) ? DRBG_SUCCESS : DRBG_FAILURE;
+}
+
+/* End NIST DRBG Code */
+
+
+/* Get seed and key cipher */
+int wc_InitRng(RNG* rng)
+{
+    int ret = BAD_FUNC_ARG;
+
+    if (rng != NULL) {
+        if (wc_RNG_HealthTestLocal(0) == 0) {
+            byte entropy[ENTROPY_NONCE_SZ];
+
+            rng->drbg =
+                    (struct DRBG*)XMALLOC(sizeof(DRBG), NULL, DYNAMIC_TYPE_RNG);
+            if (rng->drbg == NULL) {
+                ret = MEMORY_E;
+            }
+            /* This doesn't use a separate nonce. The entropy input will be
+             * the default size plus the size of the nonce making the seed
+             * size. */
+            else if (wc_GenerateSeed(&rng->seed,
+                                              entropy, ENTROPY_NONCE_SZ) == 0 &&
+                     Hash_DRBG_Instantiate(rng->drbg,
+                          entropy, ENTROPY_NONCE_SZ, NULL, 0) == DRBG_SUCCESS) {
+
+                ret = Hash_DRBG_Generate(rng->drbg, NULL, 0);
+            }
+            else
+                ret = DRBG_FAILURE;
+
+            ForceZero(entropy, ENTROPY_NONCE_SZ);
+        }
+        else
+            ret = DRBG_CONT_FAILURE;
+
+        if (ret == DRBG_SUCCESS) {
+            rng->status = DRBG_OK;
+            ret = 0;
+        }
+        else if (ret == DRBG_CONT_FAILURE) {
+            rng->status = DRBG_CONT_FAILED;
+            ret = DRBG_CONT_FIPS_E;
+        }
+        else if (ret == DRBG_FAILURE) {
+            rng->status = DRBG_FAILED;
+            ret = RNG_FAILURE_E;
+        }
+        else {
+            rng->status = DRBG_FAILED;
+        }
+    }
+
+    return ret;
+}
+
+
+/* place a generated block in output */
+int wc_RNG_GenerateBlock(RNG* rng, byte* output, word32 sz)
+{
+    int ret;
+
+    if (rng == NULL || output == NULL || sz > MAX_REQUEST_LEN)
+        return BAD_FUNC_ARG;
+
+    if (rng->status != DRBG_OK)
+        return RNG_FAILURE_E;
+
+    ret = Hash_DRBG_Generate(rng->drbg, output, sz);
+
+    if (ret == DRBG_NEED_RESEED) {
+        if (wc_RNG_HealthTestLocal(1) == 0) {
+            byte entropy[ENTROPY_SZ];
+
+            if (wc_GenerateSeed(&rng->seed, entropy, ENTROPY_SZ) == 0 &&
+                Hash_DRBG_Reseed(rng->drbg, entropy, ENTROPY_SZ)
+                                                              == DRBG_SUCCESS) {
+
+                ret = Hash_DRBG_Generate(rng->drbg, NULL, 0);
+                if (ret == DRBG_SUCCESS)
+                    ret = Hash_DRBG_Generate(rng->drbg, output, sz);
+            }
+            else
+                ret = DRBG_FAILURE;
+
+            ForceZero(entropy, ENTROPY_SZ);
+        }
+        else
+            ret = DRBG_CONT_FAILURE;
+    }
+
+    if (ret == DRBG_SUCCESS) {
+        ret = 0;
+    }
+    else if (ret == DRBG_CONT_FAILURE) {
+        ret = DRBG_CONT_FIPS_E;
+        rng->status = DRBG_CONT_FAILED;
+    }
+    else {
+        ret = RNG_FAILURE_E;
+        rng->status = DRBG_FAILED;
+    }
+
+    return ret;
+}
+
+
+int wc_RNG_GenerateByte(RNG* rng, byte* b)
+{
+    return wc_RNG_GenerateBlock(rng, b, 1);
+}
+
+
+int wc_FreeRng(RNG* rng)
+{
+    int ret = BAD_FUNC_ARG;
+
+    if (rng != NULL) {
+        if (rng->drbg != NULL) {
+            if (Hash_DRBG_Uninstantiate(rng->drbg) == DRBG_SUCCESS)
+                ret = 0;
+            else
+                ret = RNG_FAILURE_E;
+
+            XFREE(rng->drbg, NULL, DYNAMIC_TYPE_RNG);
+            rng->drbg = NULL;
+        }
+
+        rng->status = DRBG_NOT_INIT;
+    }
+
+    return ret;
+}
+
+
+int wc_RNG_HealthTest(int reseed, const byte* entropyA, word32 entropyASz,
+                                  const byte* entropyB, word32 entropyBSz,
+                                  byte* output, word32 outputSz)
+{
+    DRBG drbg;
+
+    if (entropyA == NULL || output == NULL)
+        return BAD_FUNC_ARG;
+
+    if (reseed != 0 && entropyB == NULL)
+        return BAD_FUNC_ARG;
+
+    if (outputSz != (SHA256_DIGEST_SIZE * 4))
+        return -1;
+
+    if (Hash_DRBG_Instantiate(&drbg, entropyA, entropyASz, NULL, 0) != 0)
+        return -1;
+
+    if (reseed) {
+        if (Hash_DRBG_Reseed(&drbg, entropyB, entropyBSz) != 0) {
+            Hash_DRBG_Uninstantiate(&drbg);
+            return -1;
+        }
+    }
+
+    if (Hash_DRBG_Generate(&drbg, output, outputSz) != 0) {
+        Hash_DRBG_Uninstantiate(&drbg);
+        return -1;
+    }
+
+    if (Hash_DRBG_Generate(&drbg, output, outputSz) != 0) {
+        Hash_DRBG_Uninstantiate(&drbg);
+        return -1;
+    }
+
+    if (Hash_DRBG_Uninstantiate(&drbg) != 0) {
+        return -1;
+    }
+
+    return 0;
+}
+
+
+const byte entropyA[] = {
+    0x63, 0x36, 0x33, 0x77, 0xe4, 0x1e, 0x86, 0x46, 0x8d, 0xeb, 0x0a, 0xb4,
+    0xa8, 0xed, 0x68, 0x3f, 0x6a, 0x13, 0x4e, 0x47, 0xe0, 0x14, 0xc7, 0x00,
+    0x45, 0x4e, 0x81, 0xe9, 0x53, 0x58, 0xa5, 0x69, 0x80, 0x8a, 0xa3, 0x8f,
+    0x2a, 0x72, 0xa6, 0x23, 0x59, 0x91, 0x5a, 0x9f, 0x8a, 0x04, 0xca, 0x68
+};
+
+const byte reseedEntropyA[] = {
+    0xe6, 0x2b, 0x8a, 0x8e, 0xe8, 0xf1, 0x41, 0xb6, 0x98, 0x05, 0x66, 0xe3,
+    0xbf, 0xe3, 0xc0, 0x49, 0x03, 0xda, 0xd4, 0xac, 0x2c, 0xdf, 0x9f, 0x22,
+    0x80, 0x01, 0x0a, 0x67, 0x39, 0xbc, 0x83, 0xd3
+};
+
+const byte outputA[] = {
+    0x04, 0xee, 0xc6, 0x3b, 0xb2, 0x31, 0xdf, 0x2c, 0x63, 0x0a, 0x1a, 0xfb,
+    0xe7, 0x24, 0x94, 0x9d, 0x00, 0x5a, 0x58, 0x78, 0x51, 0xe1, 0xaa, 0x79,
+    0x5e, 0x47, 0x73, 0x47, 0xc8, 0xb0, 0x56, 0x62, 0x1c, 0x18, 0xbd, 0xdc,
+    0xdd, 0x8d, 0x99, 0xfc, 0x5f, 0xc2, 0xb9, 0x20, 0x53, 0xd8, 0xcf, 0xac,
+    0xfb, 0x0b, 0xb8, 0x83, 0x12, 0x05, 0xfa, 0xd1, 0xdd, 0xd6, 0xc0, 0x71,
+    0x31, 0x8a, 0x60, 0x18, 0xf0, 0x3b, 0x73, 0xf5, 0xed, 0xe4, 0xd4, 0xd0,
+    0x71, 0xf9, 0xde, 0x03, 0xfd, 0x7a, 0xea, 0x10, 0x5d, 0x92, 0x99, 0xb8,
+    0xaf, 0x99, 0xaa, 0x07, 0x5b, 0xdb, 0x4d, 0xb9, 0xaa, 0x28, 0xc1, 0x8d,
+    0x17, 0x4b, 0x56, 0xee, 0x2a, 0x01, 0x4d, 0x09, 0x88, 0x96, 0xff, 0x22,
+    0x82, 0xc9, 0x55, 0xa8, 0x19, 0x69, 0xe0, 0x69, 0xfa, 0x8c, 0xe0, 0x07,
+    0xa1, 0x80, 0x18, 0x3a, 0x07, 0xdf, 0xae, 0x17
+};
+
+const byte entropyB[] = {
+    0xa6, 0x5a, 0xd0, 0xf3, 0x45, 0xdb, 0x4e, 0x0e, 0xff, 0xe8, 0x75, 0xc3,
+    0xa2, 0xe7, 0x1f, 0x42, 0xc7, 0x12, 0x9d, 0x62, 0x0f, 0xf5, 0xc1, 0x19,
+    0xa9, 0xef, 0x55, 0xf0, 0x51, 0x85, 0xe0, 0xfb, 0x85, 0x81, 0xf9, 0x31,
+    0x75, 0x17, 0x27, 0x6e, 0x06, 0xe9, 0x60, 0x7d, 0xdb, 0xcb, 0xcc, 0x2e
+};
+
+const byte outputB[] = {
+    0xd3, 0xe1, 0x60, 0xc3, 0x5b, 0x99, 0xf3, 0x40, 0xb2, 0x62, 0x82, 0x64,
+    0xd1, 0x75, 0x10, 0x60, 0xe0, 0x04, 0x5d, 0xa3, 0x83, 0xff, 0x57, 0xa5,
+    0x7d, 0x73, 0xa6, 0x73, 0xd2, 0xb8, 0xd8, 0x0d, 0xaa, 0xf6, 0xa6, 0xc3,
+    0x5a, 0x91, 0xbb, 0x45, 0x79, 0xd7, 0x3f, 0xd0, 0xc8, 0xfe, 0xd1, 0x11,
+    0xb0, 0x39, 0x13, 0x06, 0x82, 0x8a, 0xdf, 0xed, 0x52, 0x8f, 0x01, 0x81,
+    0x21, 0xb3, 0xfe, 0xbd, 0xc3, 0x43, 0xe7, 0x97, 0xb8, 0x7d, 0xbb, 0x63,
+    0xdb, 0x13, 0x33, 0xde, 0xd9, 0xd1, 0xec, 0xe1, 0x77, 0xcf, 0xa6, 0xb7,
+    0x1f, 0xe8, 0xab, 0x1d, 0xa4, 0x66, 0x24, 0xed, 0x64, 0x15, 0xe5, 0x1c,
+    0xcd, 0xe2, 0xc7, 0xca, 0x86, 0xe2, 0x83, 0x99, 0x0e, 0xea, 0xeb, 0x91,
+    0x12, 0x04, 0x15, 0x52, 0x8b, 0x22, 0x95, 0x91, 0x02, 0x81, 0xb0, 0x2d,
+    0xd4, 0x31, 0xf4, 0xc9, 0xf7, 0x04, 0x27, 0xdf
+};
+
+
+static int wc_RNG_HealthTestLocal(int reseed)
+{
+    int ret = 0;
+    byte check[SHA256_DIGEST_SIZE * 4];
+
+    if (reseed) {
+        ret = wc_RNG_HealthTest(1, entropyA, sizeof(entropyA),
+                                reseedEntropyA, sizeof(reseedEntropyA),
+                                check, sizeof(check));
+        if (ret == 0) {
+            if (ConstantCompare(check, outputA, sizeof(check)) != 0)
+                ret = -1;
+        }
+    }
+    else {
+        ret = wc_RNG_HealthTest(0, entropyB, sizeof(entropyB),
+                                NULL, 0,
+                                check, sizeof(check));
+        if (ret == 0) {
+            if (ConstantCompare(check, outputB, sizeof(check)) != 0)
+                ret = -1;
+        }
+    }
+
+    return ret;
+}
+
+
+#else /* HAVE_HASHDRBG || NO_RC4 */
+
+/* Get seed and key cipher */
+int wc_InitRng(RNG* rng)
+{
+    int  ret;
+#ifdef WOLFSSL_SMALL_STACK
+    byte* key;
+    byte* junk;
+#else
+    byte key[32];
+    byte junk[256];
+#endif
+
+#ifdef HAVE_INTEL_RDGEN
+    wc_InitRng_IntelRD() ;
+    if(IS_INTEL_RDRAND)return 0 ;
+#endif
+#ifdef HAVE_CAVIUM
+    if (rng->magic == WOLFSSL_RNG_CAVIUM_MAGIC)
+        return 0;
+#endif
+
+#ifdef WOLFSSL_SMALL_STACK
+    key = (byte*)XMALLOC(32, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (key == NULL)
+        return MEMORY_E;
+
+    junk = (byte*)XMALLOC(256, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (junk == NULL) {
+        XFREE(key, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        return MEMORY_E;
+    }
+#endif
+
+    ret = wc_GenerateSeed(&rng->seed, key, 32);
+
+    if (ret == 0) {
+        wc_Arc4SetKey(&rng->cipher, key, sizeof(key));
+
+        ret = wc_RNG_GenerateBlock(rng, junk, 256); /*rid initial state*/
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(key, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    XFREE(junk, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+#ifdef HAVE_CAVIUM
+    static void CaviumRNG_GenerateBlock(RNG* rng, byte* output, word32 sz);
+#endif
+
+/* place a generated block in output */
+int wc_RNG_GenerateBlock(RNG* rng, byte* output, word32 sz)
+{
+#ifdef HAVE_INTEL_RDGEN
+    if(IS_INTEL_RDRAND)
+        return wc_GenerateRand_IntelRD(NULL, output, sz) ;
+#endif
+#ifdef HAVE_CAVIUM
+    if (rng->magic == WOLFSSL_RNG_CAVIUM_MAGIC)
+        return CaviumRNG_GenerateBlock(rng, output, sz);
+#endif
+    XMEMSET(output, 0, sz);
+    wc_Arc4Process(&rng->cipher, output, output, sz);
+
+    return 0;
+}
+
+
+int wc_RNG_GenerateByte(RNG* rng, byte* b)
+{
+    return wc_RNG_GenerateBlock(rng, b, 1);
+}
+
+
+int wc_FreeRng(RNG* rng)
+{
+    (void)rng;
+    return 0;
+}
+
+
+#ifdef HAVE_CAVIUM
+
+#include 
+#include "cavium_common.h"
+
+/* Initiliaze RNG for use with Nitrox device */
+int wc_InitRngCavium(RNG* rng, int devId)
+{
+    if (rng == NULL)
+        return -1;
+
+    rng->devId = devId;
+    rng->magic = WOLFSSL_RNG_CAVIUM_MAGIC;
+
+    return 0;
+}
+
+
+static void CaviumRNG_GenerateBlock(RNG* rng, byte* output, word32 sz)
+{
+    wolfssl_word offset = 0;
+    word32      requestId;
+
+    while (sz > WOLFSSL_MAX_16BIT) {
+        word16 slen = (word16)WOLFSSL_MAX_16BIT;
+        if (CspRandom(CAVIUM_BLOCKING, slen, output + offset, &requestId,
+                      rng->devId) != 0) {
+            WOLFSSL_MSG("Cavium RNG failed");
+        }
+        sz     -= WOLFSSL_MAX_16BIT;
+        offset += WOLFSSL_MAX_16BIT;
+    }
+    if (sz) {
+        word16 slen = (word16)sz;
+        if (CspRandom(CAVIUM_BLOCKING, slen, output + offset, &requestId,
+                      rng->devId) != 0) {
+            WOLFSSL_MSG("Cavium RNG failed");
+        }
+    }
+}
+
+#endif /* HAVE_CAVIUM */
+
+#endif /* HAVE_HASHDRBG || NO_RC4 */
+
+
+#if defined(HAVE_INTEL_RDGEN)
+
+#ifndef _MSC_VER
+    #define cpuid(reg, leaf, sub)\
+            __asm__ __volatile__ ("cpuid":\
+             "=a" (reg[0]), "=b" (reg[1]), "=c" (reg[2]), "=d" (reg[3]) :\
+             "a" (leaf), "c"(sub));
+
+    #define XASM_LINK(f) asm(f)
+#else
+
+    #include 
+    #define cpuid(a,b) __cpuid((int*)a,b)
+
+    #define XASM_LINK(f)
+
+#endif /* _MSC_VER */
+
+#define EAX 0
+#define EBX 1
+#define ECX 2 
+#define EDX 3
+
+static word32 cpuid_flag(word32 leaf, word32 sub, word32 num, word32 bit) {
+    int got_intel_cpu=0;
+    unsigned int reg[5]; 
+    
+    reg[4] = '\0' ;
+    cpuid(reg, 0, 0);  
+    if(memcmp((char *)&(reg[EBX]), "Genu", 4) == 0 &&  
+                memcmp((char *)&(reg[EDX]), "ineI", 4) == 0 &&  
+                memcmp((char *)&(reg[ECX]), "ntel", 4) == 0) {  
+        got_intel_cpu = 1;  
+    }    
+    if (got_intel_cpu) {
+        cpuid(reg, leaf, sub);
+        return((reg[num]>>bit)&0x1) ;
+    }
+    return 0 ;
+}
+
+static int wc_InitRng_IntelRD()
+{
+    if(cpuid_check==0) {
+        if(cpuid_flag(1, 0, ECX, 30)){ cpuid_flags |= CPUID_RDRAND ;} 
+        if(cpuid_flag(7, 0, EBX, 18)){ cpuid_flags |= CPUID_RDSEED ;}
+        cpuid_check = 1 ;
+    }
+    return 1 ;
+}
+
+#define INTELRD_RETRY 10
+
+#if defined(HAVE_HASHDRBG) || defined(NO_RC4)
+
+/* return 0 on success */
+static inline int IntelRDseed32(unsigned int *seed)  
+{  
+    int rdseed;  unsigned char ok ;
+
+    __asm__ volatile("rdseed %0; setc %1":"=r"(rdseed), "=qm"(ok));  
+    if(ok){
+        *seed = rdseed ;
+        return 0 ;
+    } else
+        return 1;
+}
+
+/* return 0 on success */
+static inline int IntelRDseed32_r(unsigned int *rnd)  
+{  
+    int i ;
+    for(i=0; i 0; sz-=4, output+=4) {
+        if(IS_INTEL_RDSEED)ret = IntelRDseed32_r((word32 *)output) ;
+        else return 1 ;
+        if(ret)
+             return 1 ;
+    }
+    if(sz == 0)return 0 ;
+
+    if(IS_INTEL_RDSEED)ret = IntelRDseed32_r(&rndTmp) ;
+    else return 1 ;
+    if(ret)
+         return 1 ;
+    XMEMCPY(output, &rndTmp, sz) ;
+    return 0;
+}
+
+#else
+
+/* return 0 on success */
+static inline int IntelRDrand32(unsigned int *rnd)  
+{  
+    int rdrand; unsigned char ok ;  
+    __asm__ volatile("rdrand %0; setc %1":"=r"(rdrand), "=qm"(ok));  
+    if(ok){
+        *rnd = rdrand;
+        return 0 ;
+    } else
+        return 1;
+}
+
+/* return 0 on success */
+static inline int IntelRDrand32_r(unsigned int *rnd)  
+{  
+    int i ;
+    for(i=0; i 0; sz-=4, output+=4) {
+        if(IS_INTEL_RDRAND)ret = IntelRDrand32_r((word32 *)output);
+        else return 1 ;
+        if(ret)
+             return 1 ;
+    }
+    if(sz == 0)return 0 ;
+
+    if(IS_INTEL_RDRAND)ret = IntelRDrand32_r(&rndTmp);
+    else return 1 ;
+    if(ret)
+         return 1 ;
+    XMEMCPY(output, &rndTmp, sz) ;
+    return 0;
+}
+#endif /* defined(HAVE_HASHDRBG) || defined(NO_RC4) */
+
+#endif /* HAVE_INTEL_RDGEN */
+
+
+#if defined(USE_WINDOWS_API)
+
+
+int wc_GenerateSeed(OS_Seed* os, byte* output, word32 sz)
+{
+    if(!CryptAcquireContext(&os->handle, 0, 0, PROV_RSA_FULL,
+                            CRYPT_VERIFYCONTEXT))
+        return WINCRYPT_E;
+
+    if (!CryptGenRandom(os->handle, sz, output))
+        return CRYPTGEN_E;
+
+    CryptReleaseContext(os->handle, 0);
+
+    return 0;
+}
+
+
+#elif defined(HAVE_RTP_SYS) || defined(EBSNET)
+
+#include "rtprand.h"   /* rtp_rand () */
+#include "rtptime.h"   /* rtp_get_system_msec() */
+
+
+int wc_GenerateSeed(OS_Seed* os, byte* output, word32 sz)
+{
+    int i;
+    rtp_srand(rtp_get_system_msec());
+
+    for (i = 0; i < sz; i++ ) {
+        output[i] = rtp_rand() % 256;
+        if ( (i % 8) == 7)
+            rtp_srand(rtp_get_system_msec());
+    }
+
+    return 0;
+}
+
+
+#elif defined(MICRIUM)
+
+int wc_GenerateSeed(OS_Seed* os, byte* output, word32 sz)
+{
+    #if (NET_SECURE_MGR_CFG_EN == DEF_ENABLED)
+        NetSecure_InitSeed(output, sz);
+    #endif
+    return 0;
+}
+
+#elif defined(MBED)
+
+/* write a real one !!!, just for testing board */
+int wc_GenerateSeed(OS_Seed* os, byte* output, word32 sz)
+{
+    int i;
+    for (i = 0; i < sz; i++ )
+        output[i] = i;
+
+    return 0;
+}
+
+#elif defined(MICROCHIP_PIC32)
+
+#ifdef MICROCHIP_MPLAB_HARMONY
+    #define PIC32_SEED_COUNT _CP0_GET_COUNT
+#else
+    #if !defined(WOLFSSL_MICROCHIP_PIC32MZ)
+        #include 
+    #endif
+    #define PIC32_SEED_COUNT ReadCoreTimer
+#endif
+    #ifdef WOLFSSL_MIC32MZ_RNG
+        #include "xc.h"
+        int wc_GenerateSeed(OS_Seed* os, byte* output, word32 sz)
+        {
+            int i ;
+            byte rnd[8] ;
+            word32 *rnd32 = (word32 *)rnd ;
+            word32 size = sz ;
+            byte* op = output ;
+
+            /* This part has to be replaced with better random seed */
+            RNGNUMGEN1 = ReadCoreTimer();
+            RNGPOLY1 = ReadCoreTimer();
+            RNGPOLY2 = ReadCoreTimer();
+            RNGNUMGEN2 = ReadCoreTimer();
+#ifdef DEBUG_WOLFSSL
+            printf("GenerateSeed::Seed=%08x, %08x\n", RNGNUMGEN1, RNGNUMGEN2) ;
+#endif
+            RNGCONbits.PLEN = 0x40;
+            RNGCONbits.PRNGEN = 1;
+            for(i=0; i<5; i++) { /* wait for RNGNUMGEN ready */
+                volatile int x ;
+                x = RNGNUMGEN1 ;
+                x = RNGNUMGEN2 ;
+            }
+            do {
+                rnd32[0] = RNGNUMGEN1;
+                rnd32[1] = RNGNUMGEN2;
+
+                for(i=0; i<8; i++, op++) {
+                    *op = rnd[i] ;
+                    size -- ;
+                    if(size==0)break ;
+                }
+            } while(size) ;
+            return 0;
+        }
+    #else  /* WOLFSSL_MIC32MZ_RNG */
+        /* uses the core timer, in nanoseconds to seed srand */
+        int wc_GenerateSeed(OS_Seed* os, byte* output, word32 sz)
+        {
+            int i;
+            srand(PIC32_SEED_COUNT() * 25);
+
+            for (i = 0; i < sz; i++ ) {
+                output[i] = rand() % 256;
+                if ( (i % 8) == 7)
+                    srand(PIC32_SEED_COUNT() * 25);
+            }
+            return 0;
+        }
+    #endif /* WOLFSSL_MIC32MZ_RNG */
+
+#elif defined(FREESCALE_MQX)
+
+    #ifdef FREESCALE_K70_RNGA
+        /*
+         * wc_Generates a RNG seed using the Random Number Generator Accelerator
+         * on the Kinetis K70. Documentation located in Chapter 37 of
+         * K70 Sub-Family Reference Manual (see Note 3 in the README for link).
+         */
+        int wc_GenerateSeed(OS_Seed* os, byte* output, word32 sz)
+        {
+            int i;
+
+            /* turn on RNGA module */
+            SIM_SCGC3 |= SIM_SCGC3_RNGA_MASK;
+
+            /* set SLP bit to 0 - "RNGA is not in sleep mode" */
+            RNG_CR &= ~RNG_CR_SLP_MASK;
+
+            /* set HA bit to 1 - "security violations masked" */
+            RNG_CR |= RNG_CR_HA_MASK;
+
+            /* set GO bit to 1 - "output register loaded with data" */
+            RNG_CR |= RNG_CR_GO_MASK;
+
+            for (i = 0; i < sz; i++) {
+
+                /* wait for RNG FIFO to be full */
+                while((RNG_SR & RNG_SR_OREG_LVL(0xF)) == 0) {}
+
+                /* get value */
+                output[i] = RNG_OR;
+            }
+
+            return 0;
+        }
+
+    #elif defined(FREESCALE_K53_RNGB)
+        /*
+         * wc_Generates a RNG seed using the Random Number Generator (RNGB)
+         * on the Kinetis K53. Documentation located in Chapter 33 of
+         * K53 Sub-Family Reference Manual (see note in the README for link).
+         */
+        int wc_GenerateSeed(OS_Seed* os, byte* output, word32 sz)
+        {
+            int i;
+
+            /* turn on RNGB module */
+            SIM_SCGC3 |= SIM_SCGC3_RNGB_MASK;
+
+            /* reset RNGB */
+            RNG_CMD |= RNG_CMD_SR_MASK;
+
+            /* FIFO generate interrupt, return all zeros on underflow,
+             * set auto reseed */
+            RNG_CR |= (RNG_CR_FUFMOD_MASK | RNG_CR_AR_MASK);
+
+            /* gen seed, clear interrupts, clear errors */
+            RNG_CMD |= (RNG_CMD_GS_MASK | RNG_CMD_CI_MASK | RNG_CMD_CE_MASK);
+
+            /* wait for seeding to complete */
+            while ((RNG_SR & RNG_SR_SDN_MASK) == 0) {}
+
+            for (i = 0; i < sz; i++) {
+
+                /* wait for a word to be available from FIFO */
+                while((RNG_SR & RNG_SR_FIFO_LVL_MASK) == 0) {}
+
+                /* get value */
+                output[i] = RNG_OUT;
+            }
+
+            return 0;
+        }
+
+    #else
+        #warning "write a real random seed!!!!, just for testing now"
+
+        int wc_GenerateSeed(OS_Seed* os, byte* output, word32 sz)
+        {
+            int i;
+            for (i = 0; i < sz; i++ )
+                output[i] = i;
+
+            return 0;
+        }
+    #endif /* FREESCALE_K70_RNGA */
+
+#elif defined(WOLFSSL_SAFERTOS) || defined(WOLFSSL_LEANPSK) \
+   || defined(WOLFSSL_IAR_ARM)  || defined(WOLFSSL_MDK_ARM) \
+   || defined(WOLFSSL_uITRON4)  || defined(WOLFSSL_uTKERNEL2)
+
+#warning "write a real random seed!!!!, just for testing now"
+
+int wc_GenerateSeed(OS_Seed* os, byte* output, word32 sz)
+{
+    word32 i;
+    for (i = 0; i < sz; i++ )
+        output[i] = i;
+
+    (void)os;
+
+    return 0;
+}
+
+#elif defined(STM32F2_RNG)
+    #undef RNG
+    #include "stm32f2xx_rng.h"
+    #include "stm32f2xx_rcc.h"
+    /*
+     * wc_Generate a RNG seed using the hardware random number generator
+     * on the STM32F2. Documentation located in STM32F2xx Standard Peripheral
+     * Library document (See note in README).
+     */
+    int wc_GenerateSeed(OS_Seed* os, byte* output, word32 sz)
+    {
+        int i;
+
+        /* enable RNG clock source */
+        RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE);
+
+        /* enable RNG peripheral */
+        RNG_Cmd(ENABLE);
+
+        for (i = 0; i < sz; i++) {
+            /* wait until RNG number is ready */
+            while(RNG_GetFlagStatus(RNG_FLAG_DRDY)== RESET) { }
+
+            /* get value */
+            output[i] = RNG_GetRandomNumber();
+        }
+
+        return 0;
+    }
+#elif defined(WOLFSSL_LPC43xx) || defined(WOLFSSL_STM32F2xx)
+
+    #warning "write a real random seed!!!!, just for testing now"
+
+    int wc_GenerateSeed(OS_Seed* os, byte* output, word32 sz)
+    {
+        int i;
+
+        for (i = 0; i < sz; i++ )
+            output[i] = i;
+
+        return 0;
+    }
+
+#elif defined(WOLFSSL_TIRTOS)
+
+    #include 
+    #include 
+    int wc_GenerateSeed(OS_Seed* os, byte* output, word32 sz)
+    {
+        int i;
+        srand(xdc_runtime_Timestamp_get32());
+
+        for (i = 0; i < sz; i++ ) {
+            output[i] = rand() % 256;
+            if ((i % 8) == 7) {
+                srand(xdc_runtime_Timestamp_get32());
+            }
+        }
+
+        return 0;
+    }
+
+#elif defined(CUSTOM_RAND_GENERATE)
+
+   /* Implement your own random generation function
+    * word32 rand_gen(void);
+    * #define CUSTOM_RAND_GENERATE  rand_gen  */
+
+    int wc_GenerateSeed(OS_Seed* os, byte* output, word32 sz)
+    {
+        word32 i;
+
+        (void)os;
+
+        for (i = 0; i < sz; i++ )
+            output[i] = CUSTOM_RAND_GENERATE();
+
+        return 0;
+    }
+
+#elif defined(NO_DEV_RANDOM)
+
+#error "you need to write an os specific wc_GenerateSeed() here"
+
+/*
+int wc_GenerateSeed(OS_Seed* os, byte* output, word32 sz)
+{
+    return 0;
+}
+*/
+
+
+#else /* !USE_WINDOWS_API && !HAVE_RPT_SYS && !MICRIUM && !NO_DEV_RANDOM */
+
+/* may block */
+int wc_GenerateSeed(OS_Seed* os, byte* output, word32 sz)
+{
+    int ret = 0;
+
+
+#if defined(HAVE_INTEL_RDGEN) && (defined(HAVE_HASHDRBG) || defined(NO_RC4))
+    wc_InitRng_IntelRD() ; /* set cpuid_flags if not yet */
+    if(IS_INTEL_RDSEED)
+         return wc_GenerateSeed_IntelRD(NULL, output, sz) ;
+#endif
+
+    os->fd = open("/dev/urandom",O_RDONLY);
+    if (os->fd == -1) {
+        /* may still have /dev/random */
+        os->fd = open("/dev/random",O_RDONLY);
+        if (os->fd == -1)
+            return OPEN_RAN_E;
+    }
+
+    while (sz) {
+        int len = (int)read(os->fd, output, sz);
+        if (len == -1) {
+            ret = READ_RAN_E;
+            break;
+        }
+
+        sz     -= len;
+        output += len;
+
+        if (sz) {
+#ifdef BLOCKING
+            sleep(0);             /* context switch */
+#else
+            ret = RAN_BLOCK_E;
+            break;
+#endif
+        }
+    }
+    close(os->fd);
+
+    return ret;
+}
+
+#endif /* USE_WINDOWS_API */
+#endif /* HAVE_FIPS */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/ripemd.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/ripemd.c
new file mode 100644
index 0000000..639a42d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/ripemd.c
@@ -0,0 +1,354 @@
+/* ripemd.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifdef WOLFSSL_RIPEMD
+
+#include 
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+
+#ifndef WOLFSSL_HAVE_MIN
+#define WOLFSSL_HAVE_MIN
+
+    static INLINE word32 min(word32 a, word32 b)
+    {
+        return a > b ? b : a;
+    }
+
+#endif /* WOLFSSL_HAVE_MIN */
+
+void wc_InitRipeMd(RipeMd* ripemd)
+{
+    ripemd->digest[0] = 0x67452301L;
+    ripemd->digest[1] = 0xEFCDAB89L;
+    ripemd->digest[2] = 0x98BADCFEL;
+    ripemd->digest[3] = 0x10325476L;
+    ripemd->digest[4] = 0xC3D2E1F0L;
+
+    ripemd->buffLen = 0;
+    ripemd->loLen   = 0;
+    ripemd->hiLen   = 0;
+}
+
+
+/* for all */
+#define F(x, y, z)    (x ^ y ^ z) 
+#define G(x, y, z)    (z ^ (x & (y^z)))
+#define H(x, y, z)    (z ^ (x | ~y))
+#define I(x, y, z)    (y ^ (z & (x^y)))
+#define J(x, y, z)    (x ^ (y | ~z))
+
+#define k0 0
+#define k1 0x5a827999
+#define k2 0x6ed9eba1
+#define k3 0x8f1bbcdc
+#define k4 0xa953fd4e
+#define k5 0x50a28be6
+#define k6 0x5c4dd124
+#define k7 0x6d703ef3
+#define k8 0x7a6d76e9
+#define k9 0
+
+/* for 160 and 320 */
+#define Subround(f, a, b, c, d, e, x, s, k) \
+    a += f(b, c, d) + x + k;\
+    a = rotlFixed((word32)a, s) + e;\
+    c = rotlFixed((word32)c, 10U)
+
+static void Transform(RipeMd* ripemd)
+{
+    word32 a1, b1, c1, d1, e1, a2, b2, c2, d2, e2;
+    a1 = a2 = ripemd->digest[0];
+    b1 = b2 = ripemd->digest[1];
+    c1 = c2 = ripemd->digest[2];
+    d1 = d2 = ripemd->digest[3];
+    e1 = e2 = ripemd->digest[4];
+
+    Subround(F, a1, b1, c1, d1, e1, ripemd->buffer[ 0], 11, k0);
+    Subround(F, e1, a1, b1, c1, d1, ripemd->buffer[ 1], 14, k0);
+    Subround(F, d1, e1, a1, b1, c1, ripemd->buffer[ 2], 15, k0);
+    Subround(F, c1, d1, e1, a1, b1, ripemd->buffer[ 3], 12, k0);
+    Subround(F, b1, c1, d1, e1, a1, ripemd->buffer[ 4],  5, k0);
+    Subround(F, a1, b1, c1, d1, e1, ripemd->buffer[ 5],  8, k0);
+    Subround(F, e1, a1, b1, c1, d1, ripemd->buffer[ 6],  7, k0);
+    Subround(F, d1, e1, a1, b1, c1, ripemd->buffer[ 7],  9, k0);
+    Subround(F, c1, d1, e1, a1, b1, ripemd->buffer[ 8], 11, k0);
+    Subround(F, b1, c1, d1, e1, a1, ripemd->buffer[ 9], 13, k0);
+    Subround(F, a1, b1, c1, d1, e1, ripemd->buffer[10], 14, k0);
+    Subround(F, e1, a1, b1, c1, d1, ripemd->buffer[11], 15, k0);
+    Subround(F, d1, e1, a1, b1, c1, ripemd->buffer[12],  6, k0);
+    Subround(F, c1, d1, e1, a1, b1, ripemd->buffer[13],  7, k0);
+    Subround(F, b1, c1, d1, e1, a1, ripemd->buffer[14],  9, k0);
+    Subround(F, a1, b1, c1, d1, e1, ripemd->buffer[15],  8, k0);
+
+    Subround(G, e1, a1, b1, c1, d1, ripemd->buffer[ 7],  7, k1);
+    Subround(G, d1, e1, a1, b1, c1, ripemd->buffer[ 4],  6, k1);
+    Subround(G, c1, d1, e1, a1, b1, ripemd->buffer[13],  8, k1);
+    Subround(G, b1, c1, d1, e1, a1, ripemd->buffer[ 1], 13, k1);
+    Subround(G, a1, b1, c1, d1, e1, ripemd->buffer[10], 11, k1);
+    Subround(G, e1, a1, b1, c1, d1, ripemd->buffer[ 6],  9, k1);
+    Subround(G, d1, e1, a1, b1, c1, ripemd->buffer[15],  7, k1);
+    Subround(G, c1, d1, e1, a1, b1, ripemd->buffer[ 3], 15, k1);
+    Subround(G, b1, c1, d1, e1, a1, ripemd->buffer[12],  7, k1);
+    Subround(G, a1, b1, c1, d1, e1, ripemd->buffer[ 0], 12, k1);
+    Subround(G, e1, a1, b1, c1, d1, ripemd->buffer[ 9], 15, k1);
+    Subround(G, d1, e1, a1, b1, c1, ripemd->buffer[ 5],  9, k1);
+    Subround(G, c1, d1, e1, a1, b1, ripemd->buffer[ 2], 11, k1);
+    Subround(G, b1, c1, d1, e1, a1, ripemd->buffer[14],  7, k1);
+    Subround(G, a1, b1, c1, d1, e1, ripemd->buffer[11], 13, k1);
+    Subround(G, e1, a1, b1, c1, d1, ripemd->buffer[ 8], 12, k1);
+
+    Subround(H, d1, e1, a1, b1, c1, ripemd->buffer[ 3], 11, k2);
+    Subround(H, c1, d1, e1, a1, b1, ripemd->buffer[10], 13, k2);
+    Subround(H, b1, c1, d1, e1, a1, ripemd->buffer[14],  6, k2);
+    Subround(H, a1, b1, c1, d1, e1, ripemd->buffer[ 4],  7, k2);
+    Subround(H, e1, a1, b1, c1, d1, ripemd->buffer[ 9], 14, k2);
+    Subround(H, d1, e1, a1, b1, c1, ripemd->buffer[15],  9, k2);
+    Subround(H, c1, d1, e1, a1, b1, ripemd->buffer[ 8], 13, k2);
+    Subround(H, b1, c1, d1, e1, a1, ripemd->buffer[ 1], 15, k2);
+    Subround(H, a1, b1, c1, d1, e1, ripemd->buffer[ 2], 14, k2);
+    Subround(H, e1, a1, b1, c1, d1, ripemd->buffer[ 7],  8, k2);
+    Subround(H, d1, e1, a1, b1, c1, ripemd->buffer[ 0], 13, k2);
+    Subround(H, c1, d1, e1, a1, b1, ripemd->buffer[ 6],  6, k2);
+    Subround(H, b1, c1, d1, e1, a1, ripemd->buffer[13],  5, k2);
+    Subround(H, a1, b1, c1, d1, e1, ripemd->buffer[11], 12, k2);
+    Subround(H, e1, a1, b1, c1, d1, ripemd->buffer[ 5],  7, k2);
+    Subround(H, d1, e1, a1, b1, c1, ripemd->buffer[12],  5, k2);
+
+    Subround(I, c1, d1, e1, a1, b1, ripemd->buffer[ 1], 11, k3);
+    Subround(I, b1, c1, d1, e1, a1, ripemd->buffer[ 9], 12, k3);
+    Subround(I, a1, b1, c1, d1, e1, ripemd->buffer[11], 14, k3);
+    Subround(I, e1, a1, b1, c1, d1, ripemd->buffer[10], 15, k3);
+    Subround(I, d1, e1, a1, b1, c1, ripemd->buffer[ 0], 14, k3);
+    Subround(I, c1, d1, e1, a1, b1, ripemd->buffer[ 8], 15, k3);
+    Subround(I, b1, c1, d1, e1, a1, ripemd->buffer[12],  9, k3);
+    Subround(I, a1, b1, c1, d1, e1, ripemd->buffer[ 4],  8, k3);
+    Subround(I, e1, a1, b1, c1, d1, ripemd->buffer[13],  9, k3);
+    Subround(I, d1, e1, a1, b1, c1, ripemd->buffer[ 3], 14, k3);
+    Subround(I, c1, d1, e1, a1, b1, ripemd->buffer[ 7],  5, k3);
+    Subround(I, b1, c1, d1, e1, a1, ripemd->buffer[15],  6, k3);
+    Subround(I, a1, b1, c1, d1, e1, ripemd->buffer[14],  8, k3);
+    Subround(I, e1, a1, b1, c1, d1, ripemd->buffer[ 5],  6, k3);
+    Subround(I, d1, e1, a1, b1, c1, ripemd->buffer[ 6],  5, k3);
+    Subround(I, c1, d1, e1, a1, b1, ripemd->buffer[ 2], 12, k3);
+
+    Subround(J, b1, c1, d1, e1, a1, ripemd->buffer[ 4],  9, k4);
+    Subround(J, a1, b1, c1, d1, e1, ripemd->buffer[ 0], 15, k4);
+    Subround(J, e1, a1, b1, c1, d1, ripemd->buffer[ 5],  5, k4);
+    Subround(J, d1, e1, a1, b1, c1, ripemd->buffer[ 9], 11, k4);
+    Subround(J, c1, d1, e1, a1, b1, ripemd->buffer[ 7],  6, k4);
+    Subround(J, b1, c1, d1, e1, a1, ripemd->buffer[12],  8, k4);
+    Subround(J, a1, b1, c1, d1, e1, ripemd->buffer[ 2], 13, k4);
+    Subround(J, e1, a1, b1, c1, d1, ripemd->buffer[10], 12, k4);
+    Subround(J, d1, e1, a1, b1, c1, ripemd->buffer[14],  5, k4);
+    Subround(J, c1, d1, e1, a1, b1, ripemd->buffer[ 1], 12, k4);
+    Subround(J, b1, c1, d1, e1, a1, ripemd->buffer[ 3], 13, k4);
+    Subround(J, a1, b1, c1, d1, e1, ripemd->buffer[ 8], 14, k4);
+    Subround(J, e1, a1, b1, c1, d1, ripemd->buffer[11], 11, k4);
+    Subround(J, d1, e1, a1, b1, c1, ripemd->buffer[ 6],  8, k4);
+    Subround(J, c1, d1, e1, a1, b1, ripemd->buffer[15],  5, k4);
+    Subround(J, b1, c1, d1, e1, a1, ripemd->buffer[13],  6, k4);
+
+    Subround(J, a2, b2, c2, d2, e2, ripemd->buffer[ 5],  8, k5);
+    Subround(J, e2, a2, b2, c2, d2, ripemd->buffer[14],  9, k5);
+    Subround(J, d2, e2, a2, b2, c2, ripemd->buffer[ 7],  9, k5);
+    Subround(J, c2, d2, e2, a2, b2, ripemd->buffer[ 0], 11, k5);
+    Subround(J, b2, c2, d2, e2, a2, ripemd->buffer[ 9], 13, k5);
+    Subround(J, a2, b2, c2, d2, e2, ripemd->buffer[ 2], 15, k5);
+    Subround(J, e2, a2, b2, c2, d2, ripemd->buffer[11], 15, k5);
+    Subround(J, d2, e2, a2, b2, c2, ripemd->buffer[ 4],  5, k5);
+    Subround(J, c2, d2, e2, a2, b2, ripemd->buffer[13],  7, k5);
+    Subround(J, b2, c2, d2, e2, a2, ripemd->buffer[ 6],  7, k5);
+    Subround(J, a2, b2, c2, d2, e2, ripemd->buffer[15],  8, k5);
+    Subround(J, e2, a2, b2, c2, d2, ripemd->buffer[ 8], 11, k5);
+    Subround(J, d2, e2, a2, b2, c2, ripemd->buffer[ 1], 14, k5);
+    Subround(J, c2, d2, e2, a2, b2, ripemd->buffer[10], 14, k5);
+    Subround(J, b2, c2, d2, e2, a2, ripemd->buffer[ 3], 12, k5);
+    Subround(J, a2, b2, c2, d2, e2, ripemd->buffer[12],  6, k5);
+
+    Subround(I, e2, a2, b2, c2, d2, ripemd->buffer[ 6],  9, k6); 
+    Subround(I, d2, e2, a2, b2, c2, ripemd->buffer[11], 13, k6);
+    Subround(I, c2, d2, e2, a2, b2, ripemd->buffer[ 3], 15, k6);
+    Subround(I, b2, c2, d2, e2, a2, ripemd->buffer[ 7],  7, k6);
+    Subround(I, a2, b2, c2, d2, e2, ripemd->buffer[ 0], 12, k6);
+    Subround(I, e2, a2, b2, c2, d2, ripemd->buffer[13],  8, k6);
+    Subround(I, d2, e2, a2, b2, c2, ripemd->buffer[ 5],  9, k6);
+    Subround(I, c2, d2, e2, a2, b2, ripemd->buffer[10], 11, k6);
+    Subround(I, b2, c2, d2, e2, a2, ripemd->buffer[14],  7, k6);
+    Subround(I, a2, b2, c2, d2, e2, ripemd->buffer[15],  7, k6);
+    Subround(I, e2, a2, b2, c2, d2, ripemd->buffer[ 8], 12, k6);
+    Subround(I, d2, e2, a2, b2, c2, ripemd->buffer[12],  7, k6);
+    Subround(I, c2, d2, e2, a2, b2, ripemd->buffer[ 4],  6, k6);
+    Subround(I, b2, c2, d2, e2, a2, ripemd->buffer[ 9], 15, k6);
+    Subround(I, a2, b2, c2, d2, e2, ripemd->buffer[ 1], 13, k6);
+    Subround(I, e2, a2, b2, c2, d2, ripemd->buffer[ 2], 11, k6);
+
+    Subround(H, d2, e2, a2, b2, c2, ripemd->buffer[15],  9, k7);
+    Subround(H, c2, d2, e2, a2, b2, ripemd->buffer[ 5],  7, k7);
+    Subround(H, b2, c2, d2, e2, a2, ripemd->buffer[ 1], 15, k7);
+    Subround(H, a2, b2, c2, d2, e2, ripemd->buffer[ 3], 11, k7);
+    Subround(H, e2, a2, b2, c2, d2, ripemd->buffer[ 7],  8, k7);
+    Subround(H, d2, e2, a2, b2, c2, ripemd->buffer[14],  6, k7);
+    Subround(H, c2, d2, e2, a2, b2, ripemd->buffer[ 6],  6, k7);
+    Subround(H, b2, c2, d2, e2, a2, ripemd->buffer[ 9], 14, k7);
+    Subround(H, a2, b2, c2, d2, e2, ripemd->buffer[11], 12, k7);
+    Subround(H, e2, a2, b2, c2, d2, ripemd->buffer[ 8], 13, k7);
+    Subround(H, d2, e2, a2, b2, c2, ripemd->buffer[12],  5, k7);
+    Subround(H, c2, d2, e2, a2, b2, ripemd->buffer[ 2], 14, k7);
+    Subround(H, b2, c2, d2, e2, a2, ripemd->buffer[10], 13, k7);
+    Subround(H, a2, b2, c2, d2, e2, ripemd->buffer[ 0], 13, k7);
+    Subround(H, e2, a2, b2, c2, d2, ripemd->buffer[ 4],  7, k7);
+    Subround(H, d2, e2, a2, b2, c2, ripemd->buffer[13],  5, k7);
+
+    Subround(G, c2, d2, e2, a2, b2, ripemd->buffer[ 8], 15, k8);
+    Subround(G, b2, c2, d2, e2, a2, ripemd->buffer[ 6],  5, k8);
+    Subround(G, a2, b2, c2, d2, e2, ripemd->buffer[ 4],  8, k8);
+    Subround(G, e2, a2, b2, c2, d2, ripemd->buffer[ 1], 11, k8);
+    Subround(G, d2, e2, a2, b2, c2, ripemd->buffer[ 3], 14, k8);
+    Subround(G, c2, d2, e2, a2, b2, ripemd->buffer[11], 14, k8);
+    Subround(G, b2, c2, d2, e2, a2, ripemd->buffer[15],  6, k8);
+    Subround(G, a2, b2, c2, d2, e2, ripemd->buffer[ 0], 14, k8);
+    Subround(G, e2, a2, b2, c2, d2, ripemd->buffer[ 5],  6, k8);
+    Subround(G, d2, e2, a2, b2, c2, ripemd->buffer[12],  9, k8);
+    Subround(G, c2, d2, e2, a2, b2, ripemd->buffer[ 2], 12, k8);
+    Subround(G, b2, c2, d2, e2, a2, ripemd->buffer[13],  9, k8);
+    Subround(G, a2, b2, c2, d2, e2, ripemd->buffer[ 9], 12, k8);
+    Subround(G, e2, a2, b2, c2, d2, ripemd->buffer[ 7],  5, k8);
+    Subround(G, d2, e2, a2, b2, c2, ripemd->buffer[10], 15, k8);
+    Subround(G, c2, d2, e2, a2, b2, ripemd->buffer[14],  8, k8);
+
+    Subround(F, b2, c2, d2, e2, a2, ripemd->buffer[12],  8, k9);
+    Subround(F, a2, b2, c2, d2, e2, ripemd->buffer[15],  5, k9);
+    Subround(F, e2, a2, b2, c2, d2, ripemd->buffer[10], 12, k9);
+    Subround(F, d2, e2, a2, b2, c2, ripemd->buffer[ 4],  9, k9);
+    Subround(F, c2, d2, e2, a2, b2, ripemd->buffer[ 1], 12, k9);
+    Subround(F, b2, c2, d2, e2, a2, ripemd->buffer[ 5],  5, k9);
+    Subround(F, a2, b2, c2, d2, e2, ripemd->buffer[ 8], 14, k9);
+    Subround(F, e2, a2, b2, c2, d2, ripemd->buffer[ 7],  6, k9);
+    Subround(F, d2, e2, a2, b2, c2, ripemd->buffer[ 6],  8, k9);
+    Subround(F, c2, d2, e2, a2, b2, ripemd->buffer[ 2], 13, k9);
+    Subround(F, b2, c2, d2, e2, a2, ripemd->buffer[13],  6, k9);
+    Subround(F, a2, b2, c2, d2, e2, ripemd->buffer[14],  5, k9);
+    Subround(F, e2, a2, b2, c2, d2, ripemd->buffer[ 0], 15, k9);
+    Subround(F, d2, e2, a2, b2, c2, ripemd->buffer[ 3], 13, k9);
+    Subround(F, c2, d2, e2, a2, b2, ripemd->buffer[ 9], 11, k9);
+    Subround(F, b2, c2, d2, e2, a2, ripemd->buffer[11], 11, k9);
+
+    c1                = ripemd->digest[1] + c1 + d2;
+    ripemd->digest[1] = ripemd->digest[2] + d1 + e2;
+    ripemd->digest[2] = ripemd->digest[3] + e1 + a2;
+    ripemd->digest[3] = ripemd->digest[4] + a1 + b2;
+    ripemd->digest[4] = ripemd->digest[0] + b1 + c2;
+    ripemd->digest[0] = c1;
+}
+
+
+static INLINE void AddLength(RipeMd* ripemd, word32 len)
+{
+    word32 tmp = ripemd->loLen;
+    if ( (ripemd->loLen += len) < tmp)
+        ripemd->hiLen++;                       /* carry low to high */
+}
+
+
+void wc_RipeMdUpdate(RipeMd* ripemd, const byte* data, word32 len)
+{
+    /* do block size increments */
+    byte* local = (byte*)ripemd->buffer;
+
+    while (len) {
+        word32 add = min(len, RIPEMD_BLOCK_SIZE - ripemd->buffLen);
+        XMEMCPY(&local[ripemd->buffLen], data, add);
+
+        ripemd->buffLen += add;
+        data         += add;
+        len          -= add;
+
+        if (ripemd->buffLen == RIPEMD_BLOCK_SIZE) {
+            #ifdef BIG_ENDIAN_ORDER
+                ByteReverseWords(ripemd->buffer, ripemd->buffer,
+                                 RIPEMD_BLOCK_SIZE);
+            #endif
+            Transform(ripemd);
+            AddLength(ripemd, RIPEMD_BLOCK_SIZE);
+            ripemd->buffLen = 0;
+        }
+    }
+}
+
+
+void wc_RipeMdFinal(RipeMd* ripemd, byte* hash)
+{
+    byte* local = (byte*)ripemd->buffer;
+
+    AddLength(ripemd, ripemd->buffLen);               /* before adding pads */
+
+    local[ripemd->buffLen++] = 0x80;  /* add 1 */
+
+    /* pad with zeros */
+    if (ripemd->buffLen > RIPEMD_PAD_SIZE) {
+        XMEMSET(&local[ripemd->buffLen], 0, RIPEMD_BLOCK_SIZE - ripemd->buffLen);
+        ripemd->buffLen += RIPEMD_BLOCK_SIZE - ripemd->buffLen;
+
+        #ifdef BIG_ENDIAN_ORDER
+            ByteReverseWords(ripemd->buffer, ripemd->buffer, RIPEMD_BLOCK_SIZE);
+        #endif
+        Transform(ripemd);
+        ripemd->buffLen = 0;
+    }
+    XMEMSET(&local[ripemd->buffLen], 0, RIPEMD_PAD_SIZE - ripemd->buffLen);
+   
+    /* put lengths in bits */
+    ripemd->loLen = ripemd->loLen << 3;
+    ripemd->hiLen = (ripemd->loLen >> (8*sizeof(ripemd->loLen) - 3)) + 
+                 (ripemd->hiLen << 3);
+
+    /* store lengths */
+    #ifdef BIG_ENDIAN_ORDER
+        ByteReverseWords(ripemd->buffer, ripemd->buffer, RIPEMD_BLOCK_SIZE);
+    #endif
+    /* ! length ordering dependent on digest endian type ! */
+    XMEMCPY(&local[RIPEMD_PAD_SIZE], &ripemd->loLen, sizeof(word32));
+    XMEMCPY(&local[RIPEMD_PAD_SIZE + sizeof(word32)], &ripemd->hiLen, 
+           sizeof(word32));
+
+    Transform(ripemd);
+    #ifdef BIG_ENDIAN_ORDER
+        ByteReverseWords(ripemd->digest, ripemd->digest, RIPEMD_DIGEST_SIZE);
+    #endif
+    XMEMCPY(hash, ripemd->digest, RIPEMD_DIGEST_SIZE);
+
+    wc_InitRipeMd(ripemd);  /* reset state */
+}
+
+
+#endif /* WOLFSSL_RIPEMD */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/rsa.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/rsa.c
new file mode 100644
index 0000000..1a50217
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/rsa.c
@@ -0,0 +1,972 @@
+/* rsa.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifndef NO_RSA
+
+#include 
+
+#ifdef HAVE_FIPS
+int  wc_InitRsaKey(RsaKey* key, void* ptr)
+{
+    return InitRsaKey_fips(key, ptr);
+}
+
+
+int  wc_FreeRsaKey(RsaKey* key)
+{
+    return FreeRsaKey_fips(key);
+}
+
+
+int  wc_RsaPublicEncrypt(const byte* in, word32 inLen, byte* out,
+                                 word32 outLen, RsaKey* key, RNG* rng)
+{
+    return RsaPublicEncrypt_fips(in, inLen, out, outLen, key, rng);
+}
+
+
+int  wc_RsaPrivateDecryptInline(byte* in, word32 inLen, byte** out,
+                                        RsaKey* key)
+{
+    return RsaPrivateDecryptInline_fips(in, inLen, out, key);
+}
+
+
+int  wc_RsaPrivateDecrypt(const byte* in, word32 inLen, byte* out,
+                                  word32 outLen, RsaKey* key)
+{
+    return RsaPrivateDecrypt_fips(in, inLen, out, outLen, key);
+}
+
+
+int  wc_RsaSSL_Sign(const byte* in, word32 inLen, byte* out,
+                            word32 outLen, RsaKey* key, RNG* rng)
+{
+    return RsaSSL_Sign_fips(in, inLen, out, outLen, key, rng);
+}
+
+
+int  wc_RsaSSL_VerifyInline(byte* in, word32 inLen, byte** out, RsaKey* key)
+{
+    return RsaSSL_VerifyInline_fips(in, inLen, out, key);
+}
+
+
+int  wc_RsaSSL_Verify(const byte* in, word32 inLen, byte* out,
+                              word32 outLen, RsaKey* key)
+{
+    return RsaSSL_Verify_fips(in, inLen, out, outLen, key);
+}
+
+
+int  wc_RsaEncryptSize(RsaKey* key)
+{
+    return RsaEncryptSize_fips(key);
+}
+
+
+int wc_RsaFlattenPublicKey(RsaKey* key, byte* a, word32* aSz, byte* b,
+                           word32* bSz)
+{
+    /* not specified as fips so not needing _fips */
+    return RsaFlattenPublicKey(key, a, aSz, b, bSz);
+}
+#ifdef WOLFSSL_KEY_GEN
+    int wc_MakeRsaKey(RsaKey* key, int size, long e, RNG* rng)
+    {
+        return MakeRsaKey(key, size, e, rng);
+    }
+#endif
+
+
+#ifdef HAVE_CAVIUM
+    int  wc_RsaInitCavium(RsaKey* key, int i)
+    {
+        return RsaInitCavium(key, i);
+    }
+
+
+    void wc_RsaFreeCavium(RsaKey* key)
+    {
+        RsaFreeCavium(key);
+    }
+#endif
+
+/* these are functions in asn and are routed to wolfssl/wolfcrypt/asn.c
+* wc_RsaPrivateKeyDecode
+* wc_RsaPublicKeyDecode
+*/
+
+#else /* else build without fips */
+#include 
+#include 
+#include 
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+#ifdef SHOW_GEN
+    #ifdef FREESCALE_MQX
+        #include 
+    #else
+        #include 
+    #endif
+#endif
+
+#ifdef HAVE_CAVIUM
+    static int  InitCaviumRsaKey(RsaKey* key, void* heap);
+    static int  FreeCaviumRsaKey(RsaKey* key);
+    static int  CaviumRsaPublicEncrypt(const byte* in, word32 inLen, byte* out,
+                                       word32 outLen, RsaKey* key);
+    static int  CaviumRsaPrivateDecrypt(const byte* in, word32 inLen, byte* out,
+                                        word32 outLen, RsaKey* key);
+    static int  CaviumRsaSSL_Sign(const byte* in, word32 inLen, byte* out,
+                                  word32 outLen, RsaKey* key);
+    static int  CaviumRsaSSL_Verify(const byte* in, word32 inLen, byte* out,
+                                    word32 outLen, RsaKey* key);
+#endif
+
+enum {
+    RSA_PUBLIC_ENCRYPT  = 0,
+    RSA_PUBLIC_DECRYPT  = 1,
+    RSA_PRIVATE_ENCRYPT = 2,
+    RSA_PRIVATE_DECRYPT = 3,
+
+    RSA_BLOCK_TYPE_1 = 1,
+    RSA_BLOCK_TYPE_2 = 2,
+
+    RSA_MIN_SIZE = 512,
+    RSA_MAX_SIZE = 4096,
+
+    RSA_MIN_PAD_SZ   = 11      /* seperator + 0 + pad value + 8 pads */
+};
+
+
+int wc_InitRsaKey(RsaKey* key, void* heap)
+{
+#ifdef HAVE_CAVIUM
+    if (key->magic == WOLFSSL_RSA_CAVIUM_MAGIC)
+        return InitCaviumRsaKey(key, heap);
+#endif
+
+    key->type = -1;  /* haven't decided yet */
+    key->heap = heap;
+
+/* TomsFastMath doesn't use memory allocation */
+#ifndef USE_FAST_MATH
+    key->n.dp = key->e.dp = 0;  /* public  alloc parts */
+
+    key->d.dp = key->p.dp  = 0;  /* private alloc parts */
+    key->q.dp = key->dP.dp = 0;  
+    key->u.dp = key->dQ.dp = 0;
+#else
+    mp_init(&key->n);
+    mp_init(&key->e);
+    mp_init(&key->d);
+    mp_init(&key->p);
+    mp_init(&key->q);
+    mp_init(&key->dP);
+    mp_init(&key->dQ);
+    mp_init(&key->u);
+#endif
+
+    return 0;
+}
+
+
+int wc_FreeRsaKey(RsaKey* key)
+{
+    (void)key;
+
+#ifdef HAVE_CAVIUM
+    if (key->magic == WOLFSSL_RSA_CAVIUM_MAGIC)
+        return FreeCaviumRsaKey(key);
+#endif
+
+/* TomsFastMath doesn't use memory allocation */
+#ifndef USE_FAST_MATH
+    if (key->type == RSA_PRIVATE) {
+        mp_clear(&key->u);
+        mp_clear(&key->dQ);
+        mp_clear(&key->dP);
+        mp_clear(&key->q);
+        mp_clear(&key->p);
+        mp_clear(&key->d);
+    }
+    mp_clear(&key->e);
+    mp_clear(&key->n);
+#endif
+
+    return 0;
+}
+
+static int wc_RsaPad(const byte* input, word32 inputLen, byte* pkcsBlock,
+                   word32 pkcsBlockLen, byte padValue, RNG* rng)
+{
+    if (inputLen == 0)
+        return 0;
+
+    pkcsBlock[0] = 0x0;       /* set first byte to zero and advance */
+    pkcsBlock++; pkcsBlockLen--;
+    pkcsBlock[0] = padValue;  /* insert padValue */
+
+    if (padValue == RSA_BLOCK_TYPE_1)
+        /* pad with 0xff bytes */
+        XMEMSET(&pkcsBlock[1], 0xFF, pkcsBlockLen - inputLen - 2);
+    else {
+        /* pad with non-zero random bytes */
+        word32 padLen = pkcsBlockLen - inputLen - 1, i;
+        int    ret    = wc_RNG_GenerateBlock(rng, &pkcsBlock[1], padLen);
+
+        if (ret != 0)
+            return ret;
+
+        /* remove zeros */
+        for (i = 1; i < padLen; i++)
+            if (pkcsBlock[i] == 0) pkcsBlock[i] = 0x01;
+    }
+
+    pkcsBlock[pkcsBlockLen-inputLen-1] = 0;     /* separator */
+    XMEMCPY(pkcsBlock+pkcsBlockLen-inputLen, input, inputLen);
+
+    return 0;
+}
+
+
+/* UnPad plaintext, set start to *output, return length of plaintext,
+ * < 0 on error */
+static int RsaUnPad(const byte *pkcsBlock, unsigned int pkcsBlockLen,
+                       byte **output, byte padValue)
+{
+    word32 maxOutputLen = (pkcsBlockLen > 10) ? (pkcsBlockLen - 10) : 0,
+           invalid = 0,
+           i = 1,
+           outputLen;
+
+    if (pkcsBlock[0] != 0x0) /* skip past zero */
+        invalid = 1;
+    pkcsBlock++; pkcsBlockLen--;
+
+    /* Require block type padValue */
+    invalid = (pkcsBlock[0] != padValue) || invalid;
+
+    /* verify the padding until we find the separator */
+    if (padValue == RSA_BLOCK_TYPE_1) {
+        while (i maxOutputLen) || invalid;
+
+    if (invalid) {
+        WOLFSSL_MSG("RsaUnPad error, bad formatting");
+        return RSA_PAD_E;
+    }
+
+    *output = (byte *)(pkcsBlock + i);
+    return outputLen;
+}
+
+
+static int wc_RsaFunction(const byte* in, word32 inLen, byte* out,
+                          word32* outLen, int type, RsaKey* key)
+{
+    #define ERROR_OUT(x) { ret = (x); goto done;}
+
+    mp_int tmp;
+    int    ret = 0;
+    word32 keyLen, len;
+
+    if (mp_init(&tmp) != MP_OKAY)
+        return MP_INIT_E;
+
+    if (mp_read_unsigned_bin(&tmp, (byte*)in, inLen) != MP_OKAY)
+        ERROR_OUT(MP_READ_E);
+
+    if (type == RSA_PRIVATE_DECRYPT || type == RSA_PRIVATE_ENCRYPT) {
+        #ifdef RSA_LOW_MEM      /* half as much memory but twice as slow */
+            if (mp_exptmod(&tmp, &key->d, &key->n, &tmp) != MP_OKAY)
+                ERROR_OUT(MP_EXPTMOD_E);
+        #else
+            #define INNER_ERROR_OUT(x) { ret = (x); goto inner_done; }
+
+            mp_int tmpa, tmpb;
+
+            if (mp_init(&tmpa) != MP_OKAY)
+                ERROR_OUT(MP_INIT_E);
+
+            if (mp_init(&tmpb) != MP_OKAY) {
+                mp_clear(&tmpa);
+                ERROR_OUT(MP_INIT_E);
+            }
+
+            /* tmpa = tmp^dP mod p */
+            if (mp_exptmod(&tmp, &key->dP, &key->p, &tmpa) != MP_OKAY)
+                INNER_ERROR_OUT(MP_EXPTMOD_E);
+
+            /* tmpb = tmp^dQ mod q */
+            if (mp_exptmod(&tmp, &key->dQ, &key->q, &tmpb) != MP_OKAY)
+                INNER_ERROR_OUT(MP_EXPTMOD_E);
+
+            /* tmp = (tmpa - tmpb) * qInv (mod p) */
+            if (mp_sub(&tmpa, &tmpb, &tmp) != MP_OKAY)
+                INNER_ERROR_OUT(MP_SUB_E);
+
+            if (mp_mulmod(&tmp, &key->u, &key->p, &tmp) != MP_OKAY)
+                INNER_ERROR_OUT(MP_MULMOD_E);
+
+            /* tmp = tmpb + q * tmp */
+            if (mp_mul(&tmp, &key->q, &tmp) != MP_OKAY)
+                INNER_ERROR_OUT(MP_MUL_E);
+
+            if (mp_add(&tmp, &tmpb, &tmp) != MP_OKAY)
+                INNER_ERROR_OUT(MP_ADD_E);
+
+        inner_done:
+            mp_clear(&tmpa);
+            mp_clear(&tmpb);
+
+            if (ret != 0) return ret;
+
+        #endif   /* RSA_LOW_MEM */
+    }
+    else if (type == RSA_PUBLIC_ENCRYPT || type == RSA_PUBLIC_DECRYPT) {
+        if (mp_exptmod(&tmp, &key->e, &key->n, &tmp) != MP_OKAY)
+            ERROR_OUT(MP_EXPTMOD_E);
+    }
+    else
+        ERROR_OUT(RSA_WRONG_TYPE_E);
+
+    keyLen = mp_unsigned_bin_size(&key->n);
+    if (keyLen > *outLen)
+        ERROR_OUT(RSA_BUFFER_E);
+
+    len = mp_unsigned_bin_size(&tmp);
+
+    /* pad front w/ zeros to match key length */
+    while (len < keyLen) {
+        *out++ = 0x00;
+        len++;
+    }
+
+    *outLen = keyLen;
+
+    /* convert */
+    if (mp_to_unsigned_bin(&tmp, out) != MP_OKAY)
+        ERROR_OUT(MP_TO_E);
+
+done:
+    mp_clear(&tmp);
+    if (ret == MP_EXPTMOD_E) {
+        WOLFSSL_MSG("RSA_FUNCTION MP_EXPTMOD_E: memory/config problem");
+    }
+    return ret;
+}
+
+
+int wc_RsaPublicEncrypt(const byte* in, word32 inLen, byte* out, word32 outLen,
+                     RsaKey* key, RNG* rng)
+{
+    int sz, ret;
+
+#ifdef HAVE_CAVIUM
+    if (key->magic == WOLFSSL_RSA_CAVIUM_MAGIC)
+        return CaviumRsaPublicEncrypt(in, inLen, out, outLen, key);
+#endif
+
+    sz = mp_unsigned_bin_size(&key->n);
+    if (sz > (int)outLen)
+        return RSA_BUFFER_E;
+
+    if (inLen > (word32)(sz - RSA_MIN_PAD_SZ))
+        return RSA_BUFFER_E;
+
+    ret = wc_RsaPad(in, inLen, out, sz, RSA_BLOCK_TYPE_2, rng);
+    if (ret != 0)
+        return ret;
+
+    if ((ret = wc_RsaFunction(out, sz, out, &outLen,
+                              RSA_PUBLIC_ENCRYPT, key)) < 0)
+        sz = ret;
+
+    return sz;
+}
+
+
+int wc_RsaPrivateDecryptInline(byte* in, word32 inLen, byte** out, RsaKey* key)
+{
+    int ret;
+
+#ifdef HAVE_CAVIUM
+    if (key->magic == WOLFSSL_RSA_CAVIUM_MAGIC) {
+        ret = CaviumRsaPrivateDecrypt(in, inLen, in, inLen, key);
+        if (ret > 0)
+            *out = in;
+        return ret;
+    }
+#endif
+
+    if ((ret = wc_RsaFunction(in, inLen, in, &inLen, RSA_PRIVATE_DECRYPT, key))
+            < 0) {
+        return ret;
+    }
+ 
+    return RsaUnPad(in, inLen, out, RSA_BLOCK_TYPE_2);
+}
+
+
+int wc_RsaPrivateDecrypt(const byte* in, word32 inLen, byte* out, word32 outLen,
+                     RsaKey* key)
+{
+    int plainLen;
+    byte*  tmp;
+    byte*  pad = 0;
+
+#ifdef HAVE_CAVIUM
+    if (key->magic == WOLFSSL_RSA_CAVIUM_MAGIC)
+        return CaviumRsaPrivateDecrypt(in, inLen, out, outLen, key);
+#endif
+
+    tmp = (byte*)XMALLOC(inLen, key->heap, DYNAMIC_TYPE_RSA);
+    if (tmp == NULL) {
+        return MEMORY_E;
+    }
+
+    XMEMCPY(tmp, in, inLen);
+
+    if ( (plainLen = wc_RsaPrivateDecryptInline(tmp, inLen, &pad, key) ) < 0) {
+        XFREE(tmp, key->heap, DYNAMIC_TYPE_RSA);
+        return plainLen;
+    }
+    if (plainLen > (int)outLen)
+        plainLen = BAD_FUNC_ARG;
+    else
+        XMEMCPY(out, pad, plainLen);
+
+    ForceZero(tmp, inLen);
+    XFREE(tmp, key->heap, DYNAMIC_TYPE_RSA);
+
+    return plainLen;
+}
+
+
+/* for Rsa Verify */
+int wc_RsaSSL_VerifyInline(byte* in, word32 inLen, byte** out, RsaKey* key)
+{
+    int ret;
+
+#ifdef HAVE_CAVIUM
+    if (key->magic == WOLFSSL_RSA_CAVIUM_MAGIC) {
+        ret = CaviumRsaSSL_Verify(in, inLen, in, inLen, key);
+        if (ret > 0)
+            *out = in;
+        return ret;
+    }
+#endif
+
+    if ((ret = wc_RsaFunction(in, inLen, in, &inLen, RSA_PUBLIC_DECRYPT, key))
+            < 0) {
+        return ret;
+    }
+  
+    return RsaUnPad(in, inLen, out, RSA_BLOCK_TYPE_1);
+}
+
+
+int wc_RsaSSL_Verify(const byte* in, word32 inLen, byte* out, word32 outLen,
+                     RsaKey* key)
+{
+    int plainLen;
+    byte*  tmp;
+    byte*  pad = 0;
+
+#ifdef HAVE_CAVIUM
+    if (key->magic == WOLFSSL_RSA_CAVIUM_MAGIC)
+        return CaviumRsaSSL_Verify(in, inLen, out, outLen, key);
+#endif
+
+    tmp = (byte*)XMALLOC(inLen, key->heap, DYNAMIC_TYPE_RSA);
+    if (tmp == NULL) {
+        return MEMORY_E;
+    }
+
+    XMEMCPY(tmp, in, inLen);
+
+    if ( (plainLen = wc_RsaSSL_VerifyInline(tmp, inLen, &pad, key) ) < 0) {
+        XFREE(tmp, key->heap, DYNAMIC_TYPE_RSA);
+        return plainLen;
+    }
+
+    if (plainLen > (int)outLen)
+        plainLen = BAD_FUNC_ARG;
+    else
+        XMEMCPY(out, pad, plainLen);
+
+    ForceZero(tmp, inLen);
+    XFREE(tmp, key->heap, DYNAMIC_TYPE_RSA);
+
+    return plainLen;
+}
+
+
+/* for Rsa Sign */
+int wc_RsaSSL_Sign(const byte* in, word32 inLen, byte* out, word32 outLen,
+                      RsaKey* key, RNG* rng)
+{
+    int sz, ret;
+
+#ifdef HAVE_CAVIUM
+    if (key->magic == WOLFSSL_RSA_CAVIUM_MAGIC)
+        return CaviumRsaSSL_Sign(in, inLen, out, outLen, key);
+#endif
+
+    sz = mp_unsigned_bin_size(&key->n);
+    if (sz > (int)outLen)
+        return RSA_BUFFER_E;
+
+    if (inLen > (word32)(sz - RSA_MIN_PAD_SZ))
+        return RSA_BUFFER_E;
+
+    ret = wc_RsaPad(in, inLen, out, sz, RSA_BLOCK_TYPE_1, rng);
+    if (ret != 0)
+        return ret;
+
+    if ((ret = wc_RsaFunction(out, sz, out, &outLen,
+                              RSA_PRIVATE_ENCRYPT,key)) < 0)
+        sz = ret;
+    
+    return sz;
+}
+
+
+int wc_RsaEncryptSize(RsaKey* key)
+{
+#ifdef HAVE_CAVIUM
+    if (key->magic == WOLFSSL_RSA_CAVIUM_MAGIC)
+        return key->c_nSz;
+#endif
+    return mp_unsigned_bin_size(&key->n);
+}
+
+/* flatten RsaKey structure into individual elements (e, n) */
+int wc_RsaFlattenPublicKey(RsaKey* key, byte* e, word32* eSz, byte* n,
+                           word32* nSz)
+{
+    int sz, ret;
+
+    if (key == NULL || e == NULL || eSz == NULL || n == NULL || nSz == NULL)
+       return BAD_FUNC_ARG;
+
+    sz = mp_unsigned_bin_size(&key->e);
+    if ((word32)sz > *nSz)
+        return RSA_BUFFER_E;
+    ret = mp_to_unsigned_bin(&key->e, e);
+    if (ret != MP_OKAY)
+        return ret;
+    *eSz = (word32)sz;
+
+    sz = mp_unsigned_bin_size(&key->n);
+    if ((word32)sz > *nSz)
+        return RSA_BUFFER_E;
+    ret = mp_to_unsigned_bin(&key->n, n);
+    if (ret != MP_OKAY)
+        return ret;
+    *nSz = (word32)sz;
+
+    return 0;
+}
+
+
+#ifdef WOLFSSL_KEY_GEN
+
+static const int USE_BBS = 1;
+
+static int rand_prime(mp_int* N, int len, RNG* rng, void* heap)
+{
+    int   err, res, type;
+    byte* buf;
+
+    (void)heap;
+    if (N == NULL || rng == NULL)
+       return BAD_FUNC_ARG; 
+
+    /* get type */
+    if (len < 0) {
+        type = USE_BBS;
+        len = -len;
+    } else {
+        type = 0;
+    }
+
+    /* allow sizes between 2 and 512 bytes for a prime size */
+    if (len < 2 || len > 512) { 
+        return BAD_FUNC_ARG;
+    }
+   
+    /* allocate buffer to work with */
+    buf = (byte*)XMALLOC(len, heap, DYNAMIC_TYPE_RSA);
+    if (buf == NULL) {
+        return MEMORY_E;
+    }
+    XMEMSET(buf, 0, len);
+
+    do {
+#ifdef SHOW_GEN
+        printf(".");
+        fflush(stdout);
+#endif
+        /* generate value */
+        err = wc_RNG_GenerateBlock(rng, buf, len);
+        if (err != 0) {
+            XFREE(buf, heap, DYNAMIC_TYPE_RSA);
+            return err;
+        }
+
+        /* munge bits */
+        buf[0]     |= 0x80 | 0x40;
+        buf[len-1] |= 0x01 | ((type & USE_BBS) ? 0x02 : 0x00);
+ 
+        /* load value */
+        if ((err = mp_read_unsigned_bin(N, buf, len)) != MP_OKAY) {
+            XFREE(buf, heap, DYNAMIC_TYPE_RSA);
+            return err;
+        }
+
+        /* test */
+        if ((err = mp_prime_is_prime(N, 8, &res)) != MP_OKAY) {
+            XFREE(buf, heap, DYNAMIC_TYPE_RSA);
+            return err;
+        }
+    } while (res == MP_NO);
+
+    ForceZero(buf, len);
+    XFREE(buf, heap, DYNAMIC_TYPE_RSA);
+
+    return 0;
+}
+
+
+/* Make an RSA key for size bits, with e specified, 65537 is a good e */
+int wc_MakeRsaKey(RsaKey* key, int size, long e, RNG* rng)
+{
+    mp_int p, q, tmp1, tmp2, tmp3;
+    int    err;
+
+    if (key == NULL || rng == NULL)
+        return BAD_FUNC_ARG;
+
+    if (size < RSA_MIN_SIZE || size > RSA_MAX_SIZE)
+        return BAD_FUNC_ARG;
+
+    if (e < 3 || (e & 1) == 0)
+        return BAD_FUNC_ARG;
+
+    if ((err = mp_init_multi(&p, &q, &tmp1, &tmp2, &tmp3, NULL)) != MP_OKAY)
+        return err;
+
+    err = mp_set_int(&tmp3, e);
+
+    /* make p */
+    if (err == MP_OKAY) {
+        do {
+            err = rand_prime(&p, size/16, rng, key->heap); /* size in bytes/2 */
+
+            if (err == MP_OKAY)
+                err = mp_sub_d(&p, 1, &tmp1);  /* tmp1 = p-1 */
+
+            if (err == MP_OKAY)
+                err = mp_gcd(&tmp1, &tmp3, &tmp2);  /* tmp2 = gcd(p-1, e) */
+        } while (err == MP_OKAY && mp_cmp_d(&tmp2, 1) != 0);  /* e divdes p-1 */
+    }
+
+    /* make q */
+    if (err == MP_OKAY) {
+        do {
+            err = rand_prime(&q, size/16, rng, key->heap); /* size in bytes/2 */
+
+            if (err == MP_OKAY)
+                err = mp_sub_d(&q, 1, &tmp1);  /* tmp1 = q-1 */
+
+            if (err == MP_OKAY)
+                err = mp_gcd(&tmp1, &tmp3, &tmp2);  /* tmp2 = gcd(q-1, e) */
+        } while (err == MP_OKAY && mp_cmp_d(&tmp2, 1) != 0);  /* e divdes q-1 */
+    }
+
+    if (err == MP_OKAY)
+        err = mp_init_multi(&key->n, &key->e, &key->d, &key->p, &key->q, NULL);
+
+    if (err == MP_OKAY)
+        err = mp_init_multi(&key->dP, &key->dQ, &key->u, NULL, NULL, NULL);
+
+    if (err == MP_OKAY)
+        err = mp_sub_d(&p, 1, &tmp2);  /* tmp2 = p-1 */
+
+    if (err == MP_OKAY)
+        err = mp_lcm(&tmp1, &tmp2, &tmp1);  /* tmp1 = lcm(p-1, q-1),last loop */
+
+    /* make key */
+    if (err == MP_OKAY)
+        err = mp_set_int(&key->e, e);  /* key->e = e */
+
+    if (err == MP_OKAY)                /* key->d = 1/e mod lcm(p-1, q-1) */
+        err = mp_invmod(&key->e, &tmp1, &key->d);
+
+    if (err == MP_OKAY)
+        err = mp_mul(&p, &q, &key->n);  /* key->n = pq */
+
+    if (err == MP_OKAY)
+        err = mp_sub_d(&p, 1, &tmp1);
+
+    if (err == MP_OKAY)
+        err = mp_sub_d(&q, 1, &tmp2);
+
+    if (err == MP_OKAY)
+        err = mp_mod(&key->d, &tmp1, &key->dP);
+
+    if (err == MP_OKAY)
+        err = mp_mod(&key->d, &tmp2, &key->dQ);
+
+    if (err == MP_OKAY)
+        err = mp_invmod(&q, &p, &key->u);
+
+    if (err == MP_OKAY)
+        err = mp_copy(&p, &key->p);
+
+    if (err == MP_OKAY)
+        err = mp_copy(&q, &key->q);
+
+    if (err == MP_OKAY)
+        key->type = RSA_PRIVATE; 
+
+    mp_clear(&tmp3); 
+    mp_clear(&tmp2); 
+    mp_clear(&tmp1); 
+    mp_clear(&q); 
+    mp_clear(&p);
+
+    if (err != MP_OKAY) {
+        wc_FreeRsaKey(key);        
+        return err;
+    }
+
+    return 0;
+}
+
+
+#endif /* WOLFSSL_KEY_GEN */
+
+
+#ifdef HAVE_CAVIUM
+
+#include 
+#include "cavium_common.h"
+
+/* Initiliaze RSA for use with Nitrox device */
+int RsaInitCavium(RsaKey* rsa, int devId)
+{
+    if (rsa == NULL)
+        return -1;
+
+    if (CspAllocContext(CONTEXT_SSL, &rsa->contextHandle, devId) != 0)
+        return -1;
+
+    rsa->devId = devId;
+    rsa->magic = WOLFSSL_RSA_CAVIUM_MAGIC;
+   
+    return 0;
+}
+
+
+/* Free RSA from use with Nitrox device */
+void wc_RsaFreeCavium(RsaKey* rsa)
+{
+    if (rsa == NULL)
+        return;
+
+    CspFreeContext(CONTEXT_SSL, rsa->contextHandle, rsa->devId);
+    rsa->magic = 0;
+}
+
+
+/* Initialize cavium RSA key */
+static int InitCaviumRsaKey(RsaKey* key, void* heap)
+{
+    if (key == NULL)
+        return BAD_FUNC_ARG;
+
+    key->heap = heap;
+    key->type = -1;   /* don't know yet */
+
+    key->c_n  = NULL;
+    key->c_e  = NULL;
+    key->c_d  = NULL;
+    key->c_p  = NULL;
+    key->c_q  = NULL;
+    key->c_dP = NULL;
+    key->c_dQ = NULL;
+    key->c_u  = NULL;
+
+    key->c_nSz   = 0;
+    key->c_eSz   = 0;
+    key->c_dSz   = 0;
+    key->c_pSz   = 0;
+    key->c_qSz   = 0;
+    key->c_dP_Sz = 0;
+    key->c_dQ_Sz = 0;
+    key->c_uSz   = 0;
+    
+    return 0;
+}
+
+
+/* Free cavium RSA key */
+static int FreeCaviumRsaKey(RsaKey* key)
+{
+    if (key == NULL)
+        return BAD_FUNC_ARG;
+
+    XFREE(key->c_n,  key->heap, DYNAMIC_TYPE_CAVIUM_TMP);
+    XFREE(key->c_e,  key->heap, DYNAMIC_TYPE_CAVIUM_TMP);
+    XFREE(key->c_d,  key->heap, DYNAMIC_TYPE_CAVIUM_TMP);
+    XFREE(key->c_p,  key->heap, DYNAMIC_TYPE_CAVIUM_TMP);
+    XFREE(key->c_q,  key->heap, DYNAMIC_TYPE_CAVIUM_TMP);
+    XFREE(key->c_dP, key->heap, DYNAMIC_TYPE_CAVIUM_TMP);
+    XFREE(key->c_dQ, key->heap, DYNAMIC_TYPE_CAVIUM_TMP);
+    XFREE(key->c_u,  key->heap, DYNAMIC_TYPE_CAVIUM_TMP);
+
+    return InitCaviumRsaKey(key, key->heap);  /* reset pointers */
+}
+
+
+static int CaviumRsaPublicEncrypt(const byte* in, word32 inLen, byte* out,
+                                   word32 outLen, RsaKey* key)
+{
+    word32 requestId;
+    word32 ret;
+
+    if (key == NULL || in == NULL || out == NULL || outLen < (word32)key->c_nSz)
+        return -1;
+
+    ret = CspPkcs1v15Enc(CAVIUM_BLOCKING, BT2, key->c_nSz, key->c_eSz,
+                         (word16)inLen, key->c_n, key->c_e, (byte*)in, out,
+                         &requestId, key->devId);
+    if (ret != 0) {
+        WOLFSSL_MSG("Cavium Enc BT2 failed");
+        return -1;
+    }
+    return key->c_nSz;
+}
+
+
+static INLINE void ato16(const byte* c, word16* u16)
+{
+    *u16 = (c[0] << 8) | (c[1]);
+}
+
+
+static int CaviumRsaPrivateDecrypt(const byte* in, word32 inLen, byte* out,
+                                    word32 outLen, RsaKey* key)
+{
+    word32 requestId;
+    word32 ret;
+    word16 outSz = (word16)outLen;
+
+    if (key == NULL || in == NULL || out == NULL || inLen != (word32)key->c_nSz)
+        return -1;
+
+    ret = CspPkcs1v15CrtDec(CAVIUM_BLOCKING, BT2, key->c_nSz, key->c_q,
+                            key->c_dQ, key->c_p, key->c_dP, key->c_u,
+                            (byte*)in, &outSz, out, &requestId, key->devId);
+    if (ret != 0) {
+        WOLFSSL_MSG("Cavium CRT Dec BT2 failed");
+        return -1;
+    }
+    ato16((const byte*)&outSz, &outSz); 
+
+    return outSz;
+}
+
+
+static int CaviumRsaSSL_Sign(const byte* in, word32 inLen, byte* out,
+                             word32 outLen, RsaKey* key)
+{
+    word32 requestId;
+    word32 ret;
+
+    if (key == NULL || in == NULL || out == NULL || inLen == 0 || outLen <
+                                                             (word32)key->c_nSz)
+        return -1;
+
+    ret = CspPkcs1v15CrtEnc(CAVIUM_BLOCKING, BT1, key->c_nSz, (word16)inLen,
+                            key->c_q, key->c_dQ, key->c_p, key->c_dP, key->c_u,
+                            (byte*)in, out, &requestId, key->devId);
+    if (ret != 0) {
+        WOLFSSL_MSG("Cavium CRT Enc BT1 failed");
+        return -1;
+    }
+    return key->c_nSz;
+}
+
+
+static int CaviumRsaSSL_Verify(const byte* in, word32 inLen, byte* out,
+                               word32 outLen, RsaKey* key)
+{
+    word32 requestId;
+    word32 ret;
+    word16 outSz = (word16)outLen;
+
+    if (key == NULL || in == NULL || out == NULL || inLen != (word32)key->c_nSz)
+        return -1;
+
+    ret = CspPkcs1v15Dec(CAVIUM_BLOCKING, BT1, key->c_nSz, key->c_eSz,
+                         key->c_n, key->c_e, (byte*)in, &outSz, out,
+                         &requestId, key->devId);
+    if (ret != 0) {
+        WOLFSSL_MSG("Cavium Dec BT1 failed");
+        return -1;
+    }
+    outSz = ntohs(outSz);
+
+    return outSz;
+}
+
+
+#endif /* HAVE_CAVIUM */
+
+#endif /* HAVE_FIPS */
+#endif /* NO_RSA */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/sha.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/sha.c
new file mode 100644
index 0000000..be8cf17
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/sha.c
@@ -0,0 +1,458 @@
+/* sha.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#if !defined(NO_SHA)
+
+#include 
+#include 
+#include 
+
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+/* fips wrapper calls, user can call direct */
+#ifdef HAVE_FIPS
+	int wc_InitSha(Sha* sha)
+	{
+	    return InitSha_fips(sha);
+	}
+
+
+	int wc_ShaUpdate(Sha* sha, const byte* data, word32 len)
+	{
+	    return ShaUpdate_fips(sha, data, len);
+	}
+
+
+	int wc_ShaFinal(Sha* sha, byte* out)
+	{
+	    return ShaFinal_fips(sha,out);
+    }
+
+    int wc_ShaHash(const byte* data, word32 sz, byte* out)
+    {
+        return ShaHash(data, sz, out);
+    }
+
+#else /* else build without fips */
+
+#if defined(WOLFSSL_TI_HASH)
+    /* #include  included by wc_port.c */
+#else
+
+#ifdef WOLFSSL_PIC32MZ_HASH
+#define wc_InitSha   wc_InitSha_sw
+#define wc_ShaUpdate wc_ShaUpdate_sw
+#define wc_ShaFinal  wc_ShaFinal_sw
+#endif
+
+
+#ifdef FREESCALE_MMCAU
+    #include "cau_api.h"
+    #define XTRANSFORM(S,B)  cau_sha1_hash_n((B), 1, ((S))->digest)
+#else
+    #define XTRANSFORM(S,B)  Transform((S))
+#endif
+
+#ifdef STM32F2_HASH
+/*
+ * STM32F2 hardware SHA1 support through the STM32F2 standard peripheral
+ * library. Documentation located in STM32F2xx Standard Peripheral Library
+ * document (See note in README).
+ */
+#include "stm32f2xx.h"
+#include "stm32f2xx_hash.h"
+
+int wc_InitSha(Sha* sha)
+{
+    /* STM32F2 struct notes:
+     * sha->buffer  = first 4 bytes used to hold partial block if needed
+     * sha->buffLen = num bytes currently stored in sha->buffer
+     * sha->loLen   = num bytes that have been written to STM32 FIFO
+     */
+    XMEMSET(sha->buffer, 0, SHA_REG_SIZE);
+    sha->buffLen = 0;
+    sha->loLen = 0;
+
+    /* initialize HASH peripheral */
+    HASH_DeInit();
+
+    /* configure algo used, algo mode, datatype */
+    HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE);
+    HASH->CR |= (HASH_AlgoSelection_SHA1 | HASH_AlgoMode_HASH
+                 | HASH_DataType_8b);
+
+    /* reset HASH processor */
+    HASH->CR |= HASH_CR_INIT;
+
+    return 0;
+}
+
+int wc_ShaUpdate(Sha* sha, const byte* data, word32 len)
+{
+    word32 i = 0;
+    word32 fill = 0;
+    word32 diff = 0;
+
+    /* if saved partial block is available */
+    if (sha->buffLen) {
+        fill = 4 - sha->buffLen;
+
+        /* if enough data to fill, fill and push to FIFO */
+        if (fill <= len) {
+            XMEMCPY((byte*)sha->buffer + sha->buffLen, data, fill);
+            HASH_DataIn(*(uint32_t*)sha->buffer);
+
+            data += fill;
+            len -= fill;
+            sha->loLen += 4;
+            sha->buffLen = 0;
+        } else {
+            /* append partial to existing stored block */
+            XMEMCPY((byte*)sha->buffer + sha->buffLen, data, len);
+            sha->buffLen += len;
+            return;
+        }
+    }
+
+    /* write input block in the IN FIFO */
+    for(i = 0; i < len; i += 4)
+    {
+        diff = len - i;
+        if ( diff < 4) {
+            /* store incomplete last block, not yet in FIFO */
+            XMEMSET(sha->buffer, 0, SHA_REG_SIZE);
+            XMEMCPY((byte*)sha->buffer, data, diff);
+            sha->buffLen = diff;
+        } else {
+            HASH_DataIn(*(uint32_t*)data);
+            data+=4;
+        }
+    }
+
+    /* keep track of total data length thus far */
+    sha->loLen += (len - sha->buffLen);
+
+    return 0;
+}
+
+int wc_ShaFinal(Sha* sha, byte* hash)
+{
+    __IO uint16_t nbvalidbitsdata = 0;
+
+    /* finish reading any trailing bytes into FIFO */
+    if (sha->buffLen) {
+        HASH_DataIn(*(uint32_t*)sha->buffer);
+        sha->loLen += sha->buffLen;
+    }
+
+    /* calculate number of valid bits in last word of input data */
+    nbvalidbitsdata = 8 * (sha->loLen % SHA_REG_SIZE);
+
+    /* configure number of valid bits in last word of the data */
+    HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
+
+    /* start HASH processor */
+    HASH_StartDigest();
+
+    /* wait until Busy flag == RESET */
+    while (HASH_GetFlagStatus(HASH_FLAG_BUSY) != RESET) {}
+
+    /* read message digest */
+    sha->digest[0] = HASH->HR[0];
+    sha->digest[1] = HASH->HR[1];
+    sha->digest[2] = HASH->HR[2];
+    sha->digest[3] = HASH->HR[3];
+    sha->digest[4] = HASH->HR[4];
+
+    ByteReverseWords(sha->digest, sha->digest, SHA_DIGEST_SIZE);
+
+    XMEMCPY(hash, sha->digest, SHA_DIGEST_SIZE);
+
+    return wc_InitSha(sha);  /* reset state */
+}
+
+#else /* wc_ software implementation */
+
+#ifndef WOLFSSL_HAVE_MIN
+#define WOLFSSL_HAVE_MIN
+
+    static INLINE word32 min(word32 a, word32 b)
+    {
+        return a > b ? b : a;
+    }
+
+#endif /* WOLFSSL_HAVE_MIN */
+
+
+int wc_InitSha(Sha* sha)
+{
+#ifdef FREESCALE_MMCAU
+    cau_sha1_initialize_output(sha->digest);
+#else
+    sha->digest[0] = 0x67452301L;
+    sha->digest[1] = 0xEFCDAB89L;
+    sha->digest[2] = 0x98BADCFEL;
+    sha->digest[3] = 0x10325476L;
+    sha->digest[4] = 0xC3D2E1F0L;
+#endif
+
+    sha->buffLen = 0;
+    sha->loLen   = 0;
+    sha->hiLen   = 0;
+
+    return 0;
+}
+
+#ifndef FREESCALE_MMCAU
+
+#define blk0(i) (W[i] = sha->buffer[i])
+#define blk1(i) (W[(i)&15] = \
+rotlFixed(W[((i)+13)&15]^W[((i)+8)&15]^W[((i)+2)&15]^W[(i)&15],1))
+
+#define f1(x,y,z) ((z)^((x) &((y)^(z))))
+#define f2(x,y,z) ((x)^(y)^(z))
+#define f3(x,y,z) (((x)&(y))|((z)&((x)|(y))))
+#define f4(x,y,z) ((x)^(y)^(z))
+
+/* (R0+R1), R2, R3, R4 are the different operations used in SHA1 */
+#define R0(v,w,x,y,z,i) (z)+= f1((w),(x),(y)) + blk0((i)) + 0x5A827999+ \
+rotlFixed((v),5); (w) = rotlFixed((w),30);
+#define R1(v,w,x,y,z,i) (z)+= f1((w),(x),(y)) + blk1((i)) + 0x5A827999+ \
+rotlFixed((v),5); (w) = rotlFixed((w),30);
+#define R2(v,w,x,y,z,i) (z)+= f2((w),(x),(y)) + blk1((i)) + 0x6ED9EBA1+ \
+rotlFixed((v),5); (w) = rotlFixed((w),30);
+#define R3(v,w,x,y,z,i) (z)+= f3((w),(x),(y)) + blk1((i)) + 0x8F1BBCDC+ \
+rotlFixed((v),5); (w) = rotlFixed((w),30);
+#define R4(v,w,x,y,z,i) (z)+= f4((w),(x),(y)) + blk1((i)) + 0xCA62C1D6+ \
+rotlFixed((v),5); (w) = rotlFixed((w),30);
+
+static void Transform(Sha* sha)
+{
+    word32 W[SHA_BLOCK_SIZE / sizeof(word32)];
+
+    /* Copy context->state[] to working vars */
+    word32 a = sha->digest[0];
+    word32 b = sha->digest[1];
+    word32 c = sha->digest[2];
+    word32 d = sha->digest[3];
+    word32 e = sha->digest[4];
+
+#ifdef USE_SLOW_SHA
+    word32 t, i;
+
+    for (i = 0; i < 16; i++) {
+        R0(a, b, c, d, e, i);
+        t = e; e = d; d = c; c = b; b = a; a = t;
+    }
+
+    for (; i < 20; i++) {
+        R1(a, b, c, d, e, i);
+        t = e; e = d; d = c; c = b; b = a; a = t;
+    }
+
+    for (; i < 40; i++) {
+        R2(a, b, c, d, e, i);
+        t = e; e = d; d = c; c = b; b = a; a = t;
+    }
+
+    for (; i < 60; i++) {
+        R3(a, b, c, d, e, i);
+        t = e; e = d; d = c; c = b; b = a; a = t;
+    }
+
+    for (; i < 80; i++) {
+        R4(a, b, c, d, e, i);
+        t = e; e = d; d = c; c = b; b = a; a = t;
+    }
+#else
+    /* nearly 1 K bigger in code size but 25% faster  */
+    /* 4 rounds of 20 operations each. Loop unrolled. */
+    R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3);
+    R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7);
+    R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11);
+    R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15);
+
+    R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19);
+
+    R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23);
+    R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27);
+    R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31);
+    R2(d,e,a,b,c,32); R2(c,d,e,a,b,33); R2(b,c,d,e,a,34); R2(a,b,c,d,e,35);
+    R2(e,a,b,c,d,36); R2(d,e,a,b,c,37); R2(c,d,e,a,b,38); R2(b,c,d,e,a,39);
+
+    R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43);
+    R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47);
+    R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51);
+    R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55);
+    R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59);
+
+    R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63);
+    R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67);
+    R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71);
+    R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75);
+    R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79);
+#endif
+
+    /* Add the working vars back into digest state[] */
+    sha->digest[0] += a;
+    sha->digest[1] += b;
+    sha->digest[2] += c;
+    sha->digest[3] += d;
+    sha->digest[4] += e;
+}
+
+#endif /* FREESCALE_MMCAU */
+
+
+static INLINE void AddLength(Sha* sha, word32 len)
+{
+    word32 tmp = sha->loLen;
+    if ( (sha->loLen += len) < tmp)
+        sha->hiLen++;                       /* carry low to high */
+}
+
+
+int wc_ShaUpdate(Sha* sha, const byte* data, word32 len)
+{
+    /* do block size increments */
+    byte* local = (byte*)sha->buffer;
+
+    while (len) {
+        word32 add = min(len, SHA_BLOCK_SIZE - sha->buffLen);
+        XMEMCPY(&local[sha->buffLen], data, add);
+
+        sha->buffLen += add;
+        data         += add;
+        len          -= add;
+
+        if (sha->buffLen == SHA_BLOCK_SIZE) {
+#if defined(LITTLE_ENDIAN_ORDER) && !defined(FREESCALE_MMCAU)
+            ByteReverseWords(sha->buffer, sha->buffer, SHA_BLOCK_SIZE);
+#endif
+            XTRANSFORM(sha, local);
+            AddLength(sha, SHA_BLOCK_SIZE);
+            sha->buffLen = 0;
+        }
+    }
+
+    return 0;
+}
+
+
+int wc_ShaFinal(Sha* sha, byte* hash)
+{
+    byte* local = (byte*)sha->buffer;
+
+    AddLength(sha, sha->buffLen);  /* before adding pads */
+
+    local[sha->buffLen++] = 0x80;  /* add 1 */
+
+    /* pad with zeros */
+    if (sha->buffLen > SHA_PAD_SIZE) {
+        XMEMSET(&local[sha->buffLen], 0, SHA_BLOCK_SIZE - sha->buffLen);
+        sha->buffLen += SHA_BLOCK_SIZE - sha->buffLen;
+
+#if defined(LITTLE_ENDIAN_ORDER) && !defined(FREESCALE_MMCAU)
+        ByteReverseWords(sha->buffer, sha->buffer, SHA_BLOCK_SIZE);
+#endif
+        XTRANSFORM(sha, local);
+        sha->buffLen = 0;
+    }
+    XMEMSET(&local[sha->buffLen], 0, SHA_PAD_SIZE - sha->buffLen);
+
+    /* put lengths in bits */
+    sha->hiLen = (sha->loLen >> (8*sizeof(sha->loLen) - 3)) +
+    (sha->hiLen << 3);
+    sha->loLen = sha->loLen << 3;
+
+    /* store lengths */
+#if defined(LITTLE_ENDIAN_ORDER) && !defined(FREESCALE_MMCAU)
+    ByteReverseWords(sha->buffer, sha->buffer, SHA_BLOCK_SIZE);
+#endif
+    /* ! length ordering dependent on digest endian type ! */
+    XMEMCPY(&local[SHA_PAD_SIZE], &sha->hiLen, sizeof(word32));
+    XMEMCPY(&local[SHA_PAD_SIZE + sizeof(word32)], &sha->loLen, sizeof(word32));
+
+#ifdef FREESCALE_MMCAU
+    /* Kinetis requires only these bytes reversed */
+    ByteReverseWords(&sha->buffer[SHA_PAD_SIZE/sizeof(word32)],
+                     &sha->buffer[SHA_PAD_SIZE/sizeof(word32)],
+                     2 * sizeof(word32));
+#endif
+
+    XTRANSFORM(sha, local);
+#ifdef LITTLE_ENDIAN_ORDER
+    ByteReverseWords(sha->digest, sha->digest, SHA_DIGEST_SIZE);
+#endif
+    XMEMCPY(hash, sha->digest, SHA_DIGEST_SIZE);
+
+    return wc_InitSha(sha);  /* reset state */
+}
+
+#endif /* STM32F2_HASH */
+
+
+int wc_ShaHash(const byte* data, word32 len, byte* hash)
+{
+    int ret = 0;
+#ifdef WOLFSSL_SMALL_STACK
+    Sha* sha;
+#else
+    Sha sha[1];
+#endif
+
+#ifdef WOLFSSL_SMALL_STACK
+    sha = (Sha*)XMALLOC(sizeof(Sha), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (sha == NULL)
+        return MEMORY_E;
+#endif
+
+    if ((ret = wc_InitSha(sha)) != 0) {
+        WOLFSSL_MSG("wc_InitSha failed");
+    }
+    else {
+        wc_ShaUpdate(sha, data, len);
+        wc_ShaFinal(sha, hash);
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(sha, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+
+}
+
+#endif /* HAVE_FIPS */
+#endif /* WOLFSSL_TI_HASH */
+#endif /* NO_SHA */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/sha256.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/sha256.c
new file mode 100644
index 0000000..f9f02b0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/sha256.c
@@ -0,0 +1,1766 @@
+/* sha256.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+/* code submitted by raphael.huck@efixo.com */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+#include 
+
+#if !defined(NO_SHA256)
+#ifdef HAVE_FIPS
+
+int wc_InitSha256(Sha256* sha)
+{
+    return InitSha256_fips(sha);
+}
+
+
+int wc_Sha256Update(Sha256* sha, const byte* data, word32 len)
+{
+    return Sha256Update_fips(sha, data, len);
+}
+
+
+int wc_Sha256Final(Sha256* sha, byte* out)
+{
+    return Sha256Final_fips(sha, out);
+}
+
+
+int wc_Sha256Hash(const byte* data, word32 len, byte* out)
+{
+    return Sha256Hash(data, len, out);
+}
+
+#else /* else build without fips */
+
+#if !defined(NO_SHA256) && defined(WOLFSSL_TI_HASH)
+    /* #include  included by wc_port.c */
+#else
+
+#if !defined (ALIGN32)
+    #if defined (__GNUC__)
+        #define ALIGN32 __attribute__ ( (aligned (32)))
+    #elif defined(_MSC_VER)
+        /* disable align warning, we want alignment ! */
+        #pragma warning(disable: 4324)
+        #define ALIGN32 __declspec (align (32))
+    #else
+        #define ALIGN32
+    #endif
+#endif
+
+#ifdef WOLFSSL_PIC32MZ_HASH
+#define wc_InitSha256   wc_InitSha256_sw
+#define wc_Sha256Update wc_Sha256Update_sw
+#define wc_Sha256Final  wc_Sha256Final_sw
+#endif
+
+#ifdef HAVE_FIPS
+    /* set NO_WRAPPERS before headers, use direct internal f()s not wrappers */
+    #define FIPS_NO_WRAPPERS
+#endif
+
+#if defined(USE_INTEL_SPEEDUP)
+#define HAVE_INTEL_AVX1
+#define HAVE_INTEL_AVX2
+
+#if defined(DEBUG_XMM)
+#include "stdio.h"
+#endif
+
+#endif
+
+#if defined(HAVE_INTEL_AVX2)
+#define HAVE_INTEL_RORX
+#endif
+ 
+
+/*****
+Intel AVX1/AVX2 Macro Control Structure
+
+#define HAVE_INTEL_AVX1
+#define HAVE_INTEL_AVX2
+
+#define HAVE_INTEL_RORX
+
+
+int InitSha256(Sha256* sha256) { 
+     Save/Recover XMM, YMM
+     ...
+}
+
+#if defined(HAVE_INTEL_AVX1)|| defined(HAVE_INTEL_AVX2)
+  Transform() ; Function prototype 
+#else
+  Transform() {   }
+  int Sha256Final() { 
+     Save/Recover XMM, YMM
+     ...
+  }
+#endif
+
+#if defined(HAVE_INTEL_AVX1)|| defined(HAVE_INTEL_AVX2)
+    #if defined(HAVE_INTEL_RORX
+         #define RND with rorx instuction
+    #else
+        #define RND
+    #endif
+#endif
+
+#if defined(HAVE_INTEL_AVX1)
+   
+   #define XMM Instructions/inline asm
+   
+   int Transform() {
+       Stitched Message Sched/Round
+    } 
+   
+#elif defined(HAVE_INTEL_AVX2)
+  
+  #define YMM Instructions/inline asm
+  
+  int Transform() {
+      More granural Stitched Message Sched/Round
+  }
+  
+*/
+
+
+#if defined(HAVE_INTEL_AVX1) || defined(HAVE_INTEL_AVX2)
+
+/* Each platform needs to query info type 1 from cpuid to see if aesni is
+ * supported. Also, let's setup a macro for proper linkage w/o ABI conflicts
+ */
+
+#ifndef _MSC_VER
+    #define cpuid(reg, leaf, sub)\
+            __asm__ __volatile__ ("cpuid":\
+             "=a" (reg[0]), "=b" (reg[1]), "=c" (reg[2]), "=d" (reg[3]) :\
+             "a" (leaf), "c"(sub));
+
+    #define XASM_LINK(f) asm(f)
+#else
+
+    #include 
+    #define cpuid(a,b) __cpuid((int*)a,b)
+
+    #define XASM_LINK(f)
+
+#endif /* _MSC_VER */
+
+#define EAX 0
+#define EBX 1
+#define ECX 2 
+#define EDX 3
+    
+#define CPUID_AVX1   0x1
+#define CPUID_AVX2   0x2
+#define CPUID_RDRAND 0x4
+#define CPUID_RDSEED 0x8
+#define CPUID_BMI2   0x10   /* MULX, RORX */
+
+#define IS_INTEL_AVX1       (cpuid_flags&CPUID_AVX1)
+#define IS_INTEL_AVX2       (cpuid_flags&CPUID_AVX2)
+#define IS_INTEL_BMI2       (cpuid_flags&CPUID_BMI2)
+#define IS_INTEL_RDRAND     (cpuid_flags&CPUID_RDRAND)
+#define IS_INTEL_RDSEED     (cpuid_flags&CPUID_RDSEED)
+
+static word32 cpuid_check = 0 ;
+static word32 cpuid_flags = 0 ;
+
+static word32 cpuid_flag(word32 leaf, word32 sub, word32 num, word32 bit) {
+    int got_intel_cpu=0;
+    unsigned int reg[5]; 
+    
+    reg[4] = '\0' ;
+    cpuid(reg, 0, 0);  
+    if(memcmp((char *)&(reg[EBX]), "Genu", 4) == 0 &&  
+                memcmp((char *)&(reg[EDX]), "ineI", 4) == 0 &&  
+                memcmp((char *)&(reg[ECX]), "ntel", 4) == 0) {  
+        got_intel_cpu = 1;  
+    }    
+    if (got_intel_cpu) {
+        cpuid(reg, leaf, sub);
+        return((reg[num]>>bit)&0x1) ;
+    }
+    return 0 ;
+}
+
+static int set_cpuid_flags(void) {  
+    if(cpuid_check==0) {
+        if(cpuid_flag(1, 0, ECX, 28)){ cpuid_flags |= CPUID_AVX1 ;}
+        if(cpuid_flag(7, 0, EBX, 5)){  cpuid_flags |= CPUID_AVX2 ; }
+        if(cpuid_flag(7, 0, EBX, 8)) { cpuid_flags |= CPUID_BMI2 ; }
+        if(cpuid_flag(1, 0, ECX, 30)){ cpuid_flags |= CPUID_RDRAND ;  } 
+        if(cpuid_flag(7, 0, EBX, 18)){ cpuid_flags |= CPUID_RDSEED ;  }
+        cpuid_check = 1 ;
+        return 0 ;
+    }
+    return 1 ;
+}
+
+
+/* #if defined(HAVE_INTEL_AVX1/2) at the tail of sha512 */
+static int Transform(Sha256* sha256);
+
+#if defined(HAVE_INTEL_AVX1)
+static int Transform_AVX1(Sha256 *sha256) ;
+#endif
+#if defined(HAVE_INTEL_AVX2)
+static int Transform_AVX2(Sha256 *sha256) ; 
+static int Transform_AVX1_RORX(Sha256 *sha256) ; 
+#endif
+
+static int (*Transform_p)(Sha256* sha256) /* = _Transform */;
+
+#define XTRANSFORM(sha256, B)  (*Transform_p)(sha256)
+
+static void set_Transform(void) {
+     if(set_cpuid_flags())return ;
+
+#if defined(HAVE_INTEL_AVX2)
+     if(IS_INTEL_AVX2 && IS_INTEL_BMI2){ 
+         Transform_p = Transform_AVX1_RORX; return ; 
+         Transform_p = Transform_AVX2      ; 
+                  /* for avoiding warning,"not used" */
+     }
+#endif
+#if defined(HAVE_INTEL_AVX1)
+     Transform_p = ((IS_INTEL_AVX1) ? Transform_AVX1 : Transform) ; return ;
+#endif
+     Transform_p = Transform ; return ;
+}
+
+#else
+   #if defined(FREESCALE_MMCAU)
+      #define XTRANSFORM(sha256, B) Transform(sha256, B)
+   #else
+      #define XTRANSFORM(sha256, B) Transform(sha256)
+   #endif
+#endif
+
+/* Dummy for saving MM_REGs on behalf of Transform */
+#if defined(HAVE_INTEL_AVX2)&& !defined(HAVE_INTEL_AVX1)
+#define  SAVE_XMM_YMM   __asm__ volatile("or %%r8d, %%r8d":::\
+  "%ymm4","%ymm5","%ymm6","%ymm7","%ymm8","%ymm9","%ymm10","%ymm11","%ymm12","%ymm13","%ymm14","%ymm15")
+#elif defined(HAVE_INTEL_AVX1)
+#define  SAVE_XMM_YMM   __asm__ volatile("or %%r8d, %%r8d":::\
+    "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7","xmm8","xmm9","xmm10",\
+    "xmm11","xmm12","xmm13","xmm14","xmm15")
+#else
+#define  SAVE_XMM_YMM
+#endif
+
+#ifdef WOLFSSL_PIC32MZ_HASH
+#define InitSha256   InitSha256_sw
+#define Sha256Update Sha256Update_sw
+#define Sha256Final  Sha256Final_sw
+#endif
+
+#include 
+#include 
+
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+#ifdef FREESCALE_MMCAU
+    #include "cau_api.h"
+#endif
+
+#ifndef WOLFSSL_HAVE_MIN
+#define WOLFSSL_HAVE_MIN
+
+    static INLINE word32 min(word32 a, word32 b)
+    {
+        return a > b ? b : a;
+    }
+
+#endif /* WOLFSSL_HAVE_MIN */
+
+
+int wc_InitSha256(Sha256* sha256)
+{
+    #ifdef FREESCALE_MMCAU
+        cau_sha256_initialize_output(sha256->digest);
+    #else
+        sha256->digest[0] = 0x6A09E667L;
+        sha256->digest[1] = 0xBB67AE85L;
+        sha256->digest[2] = 0x3C6EF372L;
+        sha256->digest[3] = 0xA54FF53AL;
+        sha256->digest[4] = 0x510E527FL;
+        sha256->digest[5] = 0x9B05688CL;
+        sha256->digest[6] = 0x1F83D9ABL;
+        sha256->digest[7] = 0x5BE0CD19L;
+    #endif
+
+    sha256->buffLen = 0;
+    sha256->loLen   = 0;
+    sha256->hiLen   = 0;
+    
+#if defined(HAVE_INTEL_AVX1)|| defined(HAVE_INTEL_AVX2)
+    set_Transform() ; /* choose best Transform function under this runtime environment */
+#endif
+
+    return 0;
+}
+
+
+#if !defined(FREESCALE_MMCAU)
+static const ALIGN32 word32 K[64] = {
+    0x428A2F98L, 0x71374491L, 0xB5C0FBCFL, 0xE9B5DBA5L, 0x3956C25BL,
+    0x59F111F1L, 0x923F82A4L, 0xAB1C5ED5L, 0xD807AA98L, 0x12835B01L,
+    0x243185BEL, 0x550C7DC3L, 0x72BE5D74L, 0x80DEB1FEL, 0x9BDC06A7L,
+    0xC19BF174L, 0xE49B69C1L, 0xEFBE4786L, 0x0FC19DC6L, 0x240CA1CCL,
+    0x2DE92C6FL, 0x4A7484AAL, 0x5CB0A9DCL, 0x76F988DAL, 0x983E5152L,
+    0xA831C66DL, 0xB00327C8L, 0xBF597FC7L, 0xC6E00BF3L, 0xD5A79147L,
+    0x06CA6351L, 0x14292967L, 0x27B70A85L, 0x2E1B2138L, 0x4D2C6DFCL,
+    0x53380D13L, 0x650A7354L, 0x766A0ABBL, 0x81C2C92EL, 0x92722C85L,
+    0xA2BFE8A1L, 0xA81A664BL, 0xC24B8B70L, 0xC76C51A3L, 0xD192E819L,
+    0xD6990624L, 0xF40E3585L, 0x106AA070L, 0x19A4C116L, 0x1E376C08L,
+    0x2748774CL, 0x34B0BCB5L, 0x391C0CB3L, 0x4ED8AA4AL, 0x5B9CCA4FL,
+    0x682E6FF3L, 0x748F82EEL, 0x78A5636FL, 0x84C87814L, 0x8CC70208L,
+    0x90BEFFFAL, 0xA4506CEBL, 0xBEF9A3F7L, 0xC67178F2L
+};
+
+#endif
+
+#if defined(FREESCALE_MMCAU)
+
+static int Transform(Sha256* sha256, byte* buf)
+{
+    cau_sha256_hash_n(buf, 1, sha256->digest);
+
+    return 0;
+}
+
+#endif /* FREESCALE_MMCAU */
+
+#define Ch(x,y,z)       ((z) ^ ((x) & ((y) ^ (z))))
+#define Maj(x,y,z)      ((((x) | (y)) & (z)) | ((x) & (y)))
+#define R(x, n)         (((x)&0xFFFFFFFFU)>>(n))
+
+#define S(x, n)         rotrFixed(x, n)
+#define Sigma0(x)       (S(x, 2) ^ S(x, 13) ^ S(x, 22))
+#define Sigma1(x)       (S(x, 6) ^ S(x, 11) ^ S(x, 25))
+#define Gamma0(x)       (S(x, 7) ^ S(x, 18) ^ R(x, 3))
+#define Gamma1(x)       (S(x, 17) ^ S(x, 19) ^ R(x, 10))
+
+#define RND(a,b,c,d,e,f,g,h,i) \
+     t0 = (h) + Sigma1((e)) + Ch((e), (f), (g)) + K[(i)] + W[(i)]; \
+     t1 = Sigma0((a)) + Maj((a), (b), (c)); \
+     (d) += t0; \
+     (h)  = t0 + t1;
+
+#if !defined(FREESCALE_MMCAU)
+static int Transform(Sha256* sha256)
+{
+    word32 S[8], t0, t1;
+    int i;
+
+#ifdef WOLFSSL_SMALL_STACK
+    word32* W;
+
+    W = (word32*) XMALLOC(sizeof(word32) * 64, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (W == NULL)
+        return MEMORY_E;
+#else
+    word32 W[64];
+#endif
+
+    /* Copy context->state[] to working vars */
+    for (i = 0; i < 8; i++)
+        S[i] = sha256->digest[i];
+
+    for (i = 0; i < 16; i++)
+        W[i] = sha256->buffer[i];
+
+    for (i = 16; i < 64; i++)
+        W[i] = Gamma1(W[i-2]) + W[i-7] + Gamma0(W[i-15]) + W[i-16];
+
+    for (i = 0; i < 64; i += 8) {
+        RND(S[0],S[1],S[2],S[3],S[4],S[5],S[6],S[7],i+0);
+        RND(S[7],S[0],S[1],S[2],S[3],S[4],S[5],S[6],i+1);
+        RND(S[6],S[7],S[0],S[1],S[2],S[3],S[4],S[5],i+2);
+        RND(S[5],S[6],S[7],S[0],S[1],S[2],S[3],S[4],i+3);
+        RND(S[4],S[5],S[6],S[7],S[0],S[1],S[2],S[3],i+4);
+        RND(S[3],S[4],S[5],S[6],S[7],S[0],S[1],S[2],i+5);
+        RND(S[2],S[3],S[4],S[5],S[6],S[7],S[0],S[1],i+6);
+        RND(S[1],S[2],S[3],S[4],S[5],S[6],S[7],S[0],i+7);
+    }
+
+    /* Add the working vars back into digest state[] */
+    for (i = 0; i < 8; i++) {
+        sha256->digest[i] += S[i];
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(W, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return 0;
+}
+
+#endif /* #if !defined(FREESCALE_MMCAU) */
+
+static INLINE void AddLength(Sha256* sha256, word32 len)
+{
+    word32 tmp = sha256->loLen;
+    if ( (sha256->loLen += len) < tmp)
+        sha256->hiLen++;                       /* carry low to high */
+}
+
+int wc_Sha256Update(Sha256* sha256, const byte* data, word32 len)
+{
+
+    /* do block size increments */
+    byte* local = (byte*)sha256->buffer;
+
+    SAVE_XMM_YMM ; /* for Intel AVX */
+
+    while (len) {
+        word32 add = min(len, SHA256_BLOCK_SIZE - sha256->buffLen);
+        XMEMCPY(&local[sha256->buffLen], data, add);
+
+        sha256->buffLen += add;
+        data            += add;
+        len             -= add;
+
+        if (sha256->buffLen == SHA256_BLOCK_SIZE) {
+            int ret;
+
+            #if defined(LITTLE_ENDIAN_ORDER) && !defined(FREESCALE_MMCAU)
+                #if defined(HAVE_INTEL_AVX1) || defined(HAVE_INTEL_AVX2)
+                if(!IS_INTEL_AVX1 && !IS_INTEL_AVX2)
+                #endif
+                ByteReverseWords(sha256->buffer, sha256->buffer,
+                                 SHA256_BLOCK_SIZE);
+            #endif
+            ret = XTRANSFORM(sha256, local);
+            if (ret != 0)
+                return ret;
+
+            AddLength(sha256, SHA256_BLOCK_SIZE);
+            sha256->buffLen = 0;
+        }
+    }
+
+    return 0;
+}
+
+int wc_Sha256Final(Sha256* sha256, byte* hash)
+{
+    byte* local = (byte*)sha256->buffer;
+    int ret;
+    
+    SAVE_XMM_YMM ; /* for Intel AVX */
+
+    AddLength(sha256, sha256->buffLen);  /* before adding pads */
+
+    local[sha256->buffLen++] = 0x80;     /* add 1 */
+
+    /* pad with zeros */
+    if (sha256->buffLen > SHA256_PAD_SIZE) {
+        XMEMSET(&local[sha256->buffLen], 0, SHA256_BLOCK_SIZE - sha256->buffLen);
+        sha256->buffLen += SHA256_BLOCK_SIZE - sha256->buffLen;
+
+        #if defined(LITTLE_ENDIAN_ORDER) && !defined(FREESCALE_MMCAU)
+            #if defined(HAVE_INTEL_AVX1) || defined(HAVE_INTEL_AVX2)
+            if(!IS_INTEL_AVX1 && !IS_INTEL_AVX2)
+            #endif
+            ByteReverseWords(sha256->buffer, sha256->buffer, SHA256_BLOCK_SIZE);
+        #endif
+
+        ret = XTRANSFORM(sha256, local);
+        if (ret != 0)
+            return ret;
+
+        sha256->buffLen = 0;
+    }
+    XMEMSET(&local[sha256->buffLen], 0, SHA256_PAD_SIZE - sha256->buffLen);
+
+    /* put lengths in bits */
+    sha256->hiLen = (sha256->loLen >> (8*sizeof(sha256->loLen) - 3)) +
+                 (sha256->hiLen << 3);
+    sha256->loLen = sha256->loLen << 3;
+
+    /* store lengths */
+    #if defined(LITTLE_ENDIAN_ORDER) && !defined(FREESCALE_MMCAU)
+        #if defined(HAVE_INTEL_AVX1) || defined(HAVE_INTEL_AVX2)
+        if(!IS_INTEL_AVX1 && !IS_INTEL_AVX2)
+        #endif
+            ByteReverseWords(sha256->buffer, sha256->buffer, SHA256_BLOCK_SIZE);
+    #endif
+    /* ! length ordering dependent on digest endian type ! */
+    XMEMCPY(&local[SHA256_PAD_SIZE], &sha256->hiLen, sizeof(word32));
+    XMEMCPY(&local[SHA256_PAD_SIZE + sizeof(word32)], &sha256->loLen,
+            sizeof(word32));
+
+    #if defined(FREESCALE_MMCAU) || defined(HAVE_INTEL_AVX1) || defined(HAVE_INTEL_AVX2)
+        /* Kinetis requires only these bytes reversed */
+        #if defined(HAVE_INTEL_AVX1) || defined(HAVE_INTEL_AVX2)
+        if(IS_INTEL_AVX1 || IS_INTEL_AVX2)
+        #endif
+        ByteReverseWords(&sha256->buffer[SHA256_PAD_SIZE/sizeof(word32)],
+                         &sha256->buffer[SHA256_PAD_SIZE/sizeof(word32)],
+                         2 * sizeof(word32));
+    #endif
+
+    ret = XTRANSFORM(sha256, local);
+    if (ret != 0)
+        return ret;
+
+    #if defined(LITTLE_ENDIAN_ORDER)
+        ByteReverseWords(sha256->digest, sha256->digest, SHA256_DIGEST_SIZE);
+    #endif
+    XMEMCPY(hash, sha256->digest, SHA256_DIGEST_SIZE);
+
+    return wc_InitSha256(sha256);  /* reset state */
+}
+
+
+
+int wc_Sha256Hash(const byte* data, word32 len, byte* hash)
+{
+    int ret = 0;
+#ifdef WOLFSSL_SMALL_STACK
+    Sha256* sha256;
+#else
+    Sha256 sha256[1];
+#endif
+
+#ifdef WOLFSSL_SMALL_STACK
+    sha256 = (Sha256*)XMALLOC(sizeof(Sha256), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (sha256 == NULL)
+        return MEMORY_E;
+#endif
+
+    if ((ret = wc_InitSha256(sha256)) != 0) {
+        WOLFSSL_MSG("InitSha256 failed");
+    }
+    else if ((ret = wc_Sha256Update(sha256, data, len)) != 0) {
+        WOLFSSL_MSG("Sha256Update failed");
+    }
+    else if ((ret = wc_Sha256Final(sha256, hash)) != 0) {
+        WOLFSSL_MSG("Sha256Final failed");
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(sha256, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+#if defined(HAVE_INTEL_AVX1) || defined(HAVE_INTEL_AVX2)
+
+#define _DigestToReg(S_0, S_1, S_2, S_3, S_4, S_5, S_6, S_7 )\
+    { word32 d ;\
+    d = sha256->digest[0]; __asm__ volatile("movl %0, %"#S_0::"r"(d):SSE_REGs) ;\
+    d = sha256->digest[1]; __asm__ volatile("movl %0, %"#S_1::"r"(d):SSE_REGs) ;\
+    d = sha256->digest[2]; __asm__ volatile("movl %0, %"#S_2::"r"(d):SSE_REGs) ;\
+    d = sha256->digest[3]; __asm__ volatile("movl %0, %"#S_3::"r"(d):SSE_REGs) ;\
+    d = sha256->digest[4]; __asm__ volatile("movl %0, %"#S_4::"r"(d):SSE_REGs) ;\
+    d = sha256->digest[5]; __asm__ volatile("movl %0, %"#S_5::"r"(d):SSE_REGs) ;\
+    d = sha256->digest[6]; __asm__ volatile("movl %0, %"#S_6::"r"(d):SSE_REGs) ;\
+    d = sha256->digest[7]; __asm__ volatile("movl %0, %"#S_7::"r"(d):SSE_REGs) ;\
+}
+
+#define _RegToDigest(S_0, S_1, S_2, S_3, S_4, S_5, S_6, S_7 )\
+    { word32 d ; \
+    __asm__ volatile("movl %"#S_0", %0":"=r"(d)::SSE_REGs) ; sha256->digest[0] += d;\
+    __asm__ volatile("movl %"#S_1", %0":"=r"(d)::SSE_REGs) ; sha256->digest[1] += d;\
+    __asm__ volatile("movl %"#S_2", %0":"=r"(d)::SSE_REGs) ; sha256->digest[2] += d;\
+    __asm__ volatile("movl %"#S_3", %0":"=r"(d)::SSE_REGs) ; sha256->digest[3] += d;\
+    __asm__ volatile("movl %"#S_4", %0":"=r"(d)::SSE_REGs) ; sha256->digest[4] += d;\
+    __asm__ volatile("movl %"#S_5", %0":"=r"(d)::SSE_REGs) ; sha256->digest[5] += d;\
+    __asm__ volatile("movl %"#S_6", %0":"=r"(d)::SSE_REGs) ; sha256->digest[6] += d;\
+    __asm__ volatile("movl %"#S_7", %0":"=r"(d)::SSE_REGs) ; sha256->digest[7] += d;\
+}
+
+
+#define DigestToReg(S_0, S_1, S_2, S_3, S_4, S_5, S_6, S_7 )\
+    _DigestToReg(S_0, S_1, S_2, S_3, S_4, S_5, S_6, S_7 )
+
+#define RegToDigest(S_0, S_1, S_2, S_3, S_4, S_5, S_6, S_7 )\
+    _RegToDigest(S_0, S_1, S_2, S_3, S_4, S_5, S_6, S_7 )
+
+
+
+
+#define S_0 %r15d 
+#define S_1 %r10d
+#define S_2 %r11d       
+#define S_3 %r12d
+#define S_4 %r13d
+#define S_5 %r14d
+#define S_6 %ebx
+#define S_7 %r9d
+
+#define SSE_REGs "%edi", "%ecx", "%esi", "%edx", "%ebx","%r8","%r9","%r10","%r11","%r12","%r13","%r14","%r15"
+
+#if defined(HAVE_INTEL_RORX)
+#define RND_STEP_RORX_1(a,b,c,d,e,f,g,h,i)\
+__asm__ volatile("rorx  $6, %"#e", %%edx\n\t":::"%edx",SSE_REGs);  /* edx = e>>6 */\
+
+#define RND_STEP_RORX_2(a,b,c,d,e,f,g,h,i)\
+__asm__ volatile("rorx  $11, %"#e",%%edi\n\t":::"%edi",SSE_REGs); /* edi = e>>11  */\
+__asm__ volatile("xorl  %%edx, %%edi\n\t":::"%edx","%edi",SSE_REGs); /* edi = (e>>11) ^ (e>>6)  */\
+__asm__ volatile("rorx  $25, %"#e", %%edx\n\t":::"%edx",SSE_REGs);   /* edx = e>>25             */\
+
+#define RND_STEP_RORX_3(a,b,c,d,e,f,g,h,i)\
+__asm__ volatile("movl  %"#f", %%esi\n\t":::"%esi",SSE_REGs);  /* esi = f   */\
+__asm__ volatile("xorl  %"#g", %%esi\n\t":::"%esi",SSE_REGs);  /* esi = f ^ g  */\
+__asm__ volatile("xorl  %%edi, %%edx\n\t":::"%edi","%edx",SSE_REGs);  /* edx = Sigma1(e)  */\
+__asm__ volatile("andl  %"#e", %%esi\n\t":::"%esi",SSE_REGs);  /* esi = (f ^ g) & e       */\
+__asm__ volatile("xorl  %"#g", %%esi\n\t":::"%esi",SSE_REGs);  /* esi = Ch(e,f,g)         */\
+
+#define RND_STEP_RORX_4(a,b,c,d,e,f,g,h,i)\
+/*__asm__ volatile("movl    %0, %%edx\n\t"::"m"(w_k):"%edx");*/\
+__asm__ volatile("addl  %0, %"#h"\n\t"::"r"(W_K[i]):SSE_REGs);    /* h += w_k  */\
+__asm__ volatile("addl  %%edx, %"#h"\n\t":::"%edx",SSE_REGs);     /* h = h + w_k + Sigma1(e) */\
+__asm__ volatile("rorx  $2, %"#a", %%r8d\n\t":::"%r8",SSE_REGs);  /* r8d = a>>2   */\
+__asm__ volatile("rorx  $13, %"#a", %%edi\n\t":::"%edi",SSE_REGs);/* edi = a>>13  */\
+
+#define RND_STEP_RORX_5(a,b,c,d,e,f,g,h,i)\
+__asm__ volatile("rorx  $22, %"#a", %%edx\n\t":::"%edx",SSE_REGs); /* edx = a>>22 */\
+__asm__ volatile("xorl  %%r8d, %%edi\n\t":::"%edi","%r8",SSE_REGs);/* edi = (a>>2) ^ (a>>13)  */\
+__asm__ volatile("xorl  %%edi, %%edx\n\t":::"%edi","%edx",SSE_REGs);  /* edx = Sigma0(a)      */\
+ 
+#define RND_STEP_RORX_6(a,b,c,d,e,f,g,h,i)\
+__asm__ volatile("movl  %"#b", %%edi\n\t":::"%edi",SSE_REGs);  /* edi = b          */\
+__asm__ volatile("orl   %"#a", %%edi\n\t":::"%edi",SSE_REGs);  /* edi = a | b      */\
+__asm__ volatile("andl  %"#c", %%edi\n\t":::"%edi",SSE_REGs);  /* edi = (a | b) & c*/\
+__asm__ volatile("movl  %"#b", %%r8d\n\t":::"%r8",SSE_REGs);  /* r8d = b           */\
+
+#define RND_STEP_RORX_7(a,b,c,d,e,f,g,h,i)\
+__asm__ volatile("addl  %%esi, %"#h"\n\t":::"%esi",SSE_REGs);  /* h += Ch(e,f,g)   */\
+__asm__ volatile("andl  %"#a", %%r8d\n\t":::"%r8",SSE_REGs);  /* r8d = b & a       */\
+__asm__ volatile("orl   %%edi, %%r8d\n\t":::"%edi","%r8",SSE_REGs); /* r8d = Maj(a,b,c) */\
+
+#define RND_STEP_RORX_8(a,b,c,d,e,f,g,h,i)\
+__asm__ volatile("addl  "#h", "#d"\n\t");  /* d += h + w_k + Sigma1(e) + Ch(e,f,g) */\
+__asm__ volatile("addl  %"#h", %%r8d\n\t":::"%r8",SSE_REGs); \
+__asm__ volatile("addl  %%edx, %%r8d\n\t":::"%edx","%r8",SSE_REGs); \
+__asm__ volatile("movl  %r8d, "#h"\n\t");   
+
+#endif
+
+#define RND_STEP_1(a,b,c,d,e,f,g,h,i)\
+__asm__ volatile("movl  %"#e", %%edx\n\t":::"%edx",SSE_REGs);\
+__asm__ volatile("roll  $26, %%edx\n\t":::"%edx",SSE_REGs);  /* edx = e>>6     */\
+__asm__ volatile("movl  %"#e", %%edi\n\t":::"%edi",SSE_REGs);\
+
+#define RND_STEP_2(a,b,c,d,e,f,g,h,i)\
+__asm__ volatile("roll  $21, %%edi\n\t":::"%edi",SSE_REGs);         /* edi = e>>11 */\
+__asm__ volatile("xorl  %%edx, %%edi\n\t":::"%edx","%edi",SSE_REGs); /* edi = (e>>11) ^ (e>>6)  */\
+__asm__ volatile("movl  %"#e", %%edx\n\t":::"%edx",SSE_REGs);   /* edx = e      */\
+__asm__ volatile("roll  $7, %%edx\n\t":::"%edx",SSE_REGs);      /* edx = e>>25  */\
+
+#define RND_STEP_3(a,b,c,d,e,f,g,h,i)\
+__asm__ volatile("movl  %"#f", %%esi\n\t":::"%esi",SSE_REGs);  /* esi = f       */\
+__asm__ volatile("xorl  %"#g", %%esi\n\t":::"%esi",SSE_REGs);  /* esi = f ^ g   */\
+__asm__ volatile("xorl  %%edi, %%edx\n\t":::"%edi","%edx",SSE_REGs); /* edx = Sigma1(e) */\
+__asm__ volatile("andl  %"#e", %%esi\n\t":::"%esi",SSE_REGs);  /* esi = (f ^ g) & e  */\
+__asm__ volatile("xorl  %"#g", %%esi\n\t":::"%esi",SSE_REGs);  /* esi = Ch(e,f,g)    */\
+
+#define RND_STEP_4(a,b,c,d,e,f,g,h,i)\
+__asm__ volatile("addl  %0, %"#h"\n\t"::"r"(W_K[i]):SSE_REGs); /* h += w_k  */\
+__asm__ volatile("addl  %%edx, %"#h"\n\t":::"%edx",SSE_REGs); /* h = h + w_k + Sigma1(e) */\
+__asm__ volatile("movl  %"#a", %%r8d\n\t":::"%r8",SSE_REGs);  /* r8d = a    */\
+__asm__ volatile("roll  $30, %%r8d\n\t":::"%r8",SSE_REGs);    /* r8d = a>>2 */\
+__asm__ volatile("movl  %"#a", %%edi\n\t":::"%edi",SSE_REGs);  /* edi = a   */\
+__asm__ volatile("roll  $19, %%edi\n\t":::"%edi",SSE_REGs);    /* edi = a>>13 */\
+__asm__ volatile("movl  %"#a", %%edx\n\t":::"%edx",SSE_REGs);  /* edx = a     */\
+
+#define RND_STEP_5(a,b,c,d,e,f,g,h,i)\
+__asm__ volatile("roll  $10, %%edx\n\t":::"%edx",SSE_REGs);    /* edx = a>>22 */\
+__asm__ volatile("xorl  %%r8d, %%edi\n\t":::"%edi","%r8",SSE_REGs); /* edi = (a>>2) ^ (a>>13)  */\
+__asm__ volatile("xorl  %%edi, %%edx\n\t":::"%edi","%edx",SSE_REGs);/* edx = Sigma0(a)         */\
+
+#define RND_STEP_6(a,b,c,d,e,f,g,h,i)\
+__asm__ volatile("movl  %"#b", %%edi\n\t":::"%edi",SSE_REGs);  /* edi = b      */\
+__asm__ volatile("orl   %"#a", %%edi\n\t":::"%edi",SSE_REGs);  /* edi = a | b  */\
+__asm__ volatile("andl  %"#c", %%edi\n\t":::"%edi",SSE_REGs);  /* edi = (a | b) & c */\
+__asm__ volatile("movl  %"#b", %%r8d\n\t":::"%r8",SSE_REGs);  /* r8d = b       */\
+
+#define RND_STEP_7(a,b,c,d,e,f,g,h,i)\
+__asm__ volatile("addl  %%esi, %"#h"\n\t":::"%esi",SSE_REGs);  /* h += Ch(e,f,g)        */\
+__asm__ volatile("andl  %"#a", %%r8d\n\t":::"%r8",SSE_REGs);  /* r8d = b & a            */\
+__asm__ volatile("orl   %%edi, %%r8d\n\t":::"%edi","%r8",SSE_REGs); /* r8d = Maj(a,b,c) */\
+
+#define RND_STEP_8(a,b,c,d,e,f,g,h,i)\
+__asm__ volatile("addl  "#h", "#d"\n\t");  /* d += h + w_k + Sigma1(e) + Ch(e,f,g) */\
+__asm__ volatile("addl  %"#h", %%r8d\n\t":::"%r8",SSE_REGs); \
+                 /* r8b = h + w_k + Sigma1(e) + Ch(e,f,g) + Maj(a,b,c) */\
+__asm__ volatile("addl  %%edx, %%r8d\n\t":::"%edx","%r8",SSE_REGs);\
+                 /* r8b = h + w_k + Sigma1(e) Sigma0(a) + Ch(e,f,g) + Maj(a,b,c)     */\
+__asm__ volatile("movl  %%r8d, %"#h"\n\t":::"%r8", SSE_REGs); \
+                 /* h = h + w_k + Sigma1(e) + Sigma0(a) + Ch(e,f,g) + Maj(a,b,c) */ \
+
+#define RND_X(a,b,c,d,e,f,g,h,i) \
+       RND_STEP_1(a,b,c,d,e,f,g,h,i); \
+       RND_STEP_2(a,b,c,d,e,f,g,h,i); \
+       RND_STEP_3(a,b,c,d,e,f,g,h,i); \
+       RND_STEP_4(a,b,c,d,e,f,g,h,i); \
+       RND_STEP_5(a,b,c,d,e,f,g,h,i); \
+       RND_STEP_6(a,b,c,d,e,f,g,h,i); \
+       RND_STEP_7(a,b,c,d,e,f,g,h,i); \
+       RND_STEP_8(a,b,c,d,e,f,g,h,i); 
+
+#define RND_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_X(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i);
+#define RND_7(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_X(S_7,S_0,S_1,S_2,S_3,S_4,S_5,S_6,_i);
+#define RND_6(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_X(S_6,S_7,S_0,S_1,S_2,S_3,S_4,S_5,_i);
+#define RND_5(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_X(S_5,S_6,S_7,S_0,S_1,S_2,S_3,S_4,_i);
+#define RND_4(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_X(S_4,S_5,S_6,S_7,S_0,S_1,S_2,S_3,_i);
+#define RND_3(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_X(S_3,S_4,S_5,S_6,S_7,S_0,S_1,S_2,_i);
+#define RND_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_X(S_2,S_3,S_4,S_5,S_6,S_7,S_0,S_1,_i);
+#define RND_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_X(S_1,S_2,S_3,S_4,S_5,S_6,S_7,S_0,_i);
+
+
+#define RND_1_3(a,b,c,d,e,f,g,h,i) {\
+       RND_STEP_1(a,b,c,d,e,f,g,h,i); \
+       RND_STEP_2(a,b,c,d,e,f,g,h,i); \
+       RND_STEP_3(a,b,c,d,e,f,g,h,i); \
+}
+
+#define RND_4_6(a,b,c,d,e,f,g,h,i) {\
+       RND_STEP_4(a,b,c,d,e,f,g,h,i); \
+       RND_STEP_5(a,b,c,d,e,f,g,h,i); \
+       RND_STEP_6(a,b,c,d,e,f,g,h,i); \
+}
+
+#define RND_7_8(a,b,c,d,e,f,g,h,i) {\
+       RND_STEP_7(a,b,c,d,e,f,g,h,i); \
+       RND_STEP_8(a,b,c,d,e,f,g,h,i); \
+}
+
+#define RND_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_X(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i);
+#define RND_7(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_X(S_7,S_0,S_1,S_2,S_3,S_4,S_5,S_6,_i);
+#define RND_6(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_X(S_6,S_7,S_0,S_1,S_2,S_3,S_4,S_5,_i);
+#define RND_5(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_X(S_5,S_6,S_7,S_0,S_1,S_2,S_3,S_4,_i);
+#define RND_4(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_X(S_4,S_5,S_6,S_7,S_0,S_1,S_2,S_3,_i);
+#define RND_3(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_X(S_3,S_4,S_5,S_6,S_7,S_0,S_1,S_2,_i);
+#define RND_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_X(S_2,S_3,S_4,S_5,S_6,S_7,S_0,S_1,_i);
+#define RND_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_X(S_1,S_2,S_3,S_4,S_5,S_6,S_7,S_0,_i);
+
+
+#define RND_0_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_1_3(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i);
+#define RND_7_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_1_3(S_7,S_0,S_1,S_2,S_3,S_4,S_5,S_6,_i);
+#define RND_6_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_1_3(S_6,S_7,S_0,S_1,S_2,S_3,S_4,S_5,_i);
+#define RND_5_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_1_3(S_5,S_6,S_7,S_0,S_1,S_2,S_3,S_4,_i);
+#define RND_4_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_1_3(S_4,S_5,S_6,S_7,S_0,S_1,S_2,S_3,_i);
+#define RND_3_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_1_3(S_3,S_4,S_5,S_6,S_7,S_0,S_1,S_2,_i);
+#define RND_2_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_1_3(S_2,S_3,S_4,S_5,S_6,S_7,S_0,S_1,_i);
+#define RND_1_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_1_3(S_1,S_2,S_3,S_4,S_5,S_6,S_7,S_0,_i);
+
+#define RND_0_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_4_6(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i);
+#define RND_7_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_4_6(S_7,S_0,S_1,S_2,S_3,S_4,S_5,S_6,_i);
+#define RND_6_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_4_6(S_6,S_7,S_0,S_1,S_2,S_3,S_4,S_5,_i);
+#define RND_5_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_4_6(S_5,S_6,S_7,S_0,S_1,S_2,S_3,S_4,_i);
+#define RND_4_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_4_6(S_4,S_5,S_6,S_7,S_0,S_1,S_2,S_3,_i);
+#define RND_3_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_4_6(S_3,S_4,S_5,S_6,S_7,S_0,S_1,S_2,_i);
+#define RND_2_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_4_6(S_2,S_3,S_4,S_5,S_6,S_7,S_0,S_1,_i);
+#define RND_1_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_4_6(S_1,S_2,S_3,S_4,S_5,S_6,S_7,S_0,_i);
+
+#define RND_0_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_7_8(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i);
+#define RND_7_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_7_8(S_7,S_0,S_1,S_2,S_3,S_4,S_5,S_6,_i);
+#define RND_6_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_7_8(S_6,S_7,S_0,S_1,S_2,S_3,S_4,S_5,_i);
+#define RND_5_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_7_8(S_5,S_6,S_7,S_0,S_1,S_2,S_3,S_4,_i);
+#define RND_4_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_7_8(S_4,S_5,S_6,S_7,S_0,S_1,S_2,S_3,_i);
+#define RND_3_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_7_8(S_3,S_4,S_5,S_6,S_7,S_0,S_1,S_2,_i);
+#define RND_2_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_7_8(S_2,S_3,S_4,S_5,S_6,S_7,S_0,S_1,_i);
+#define RND_1_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,_i) RND_7_8(S_1,S_2,S_3,S_4,S_5,S_6,S_7,S_0,_i);
+
+#define FOR(cnt, init, max, inc, loop)  \
+    __asm__ volatile("movl $"#init", %0\n\t"#loop":"::"m"(cnt):) 
+#define END(cnt, init, max, inc, loop)  \
+    __asm__ volatile("addl $"#inc", %0\n\tcmpl $"#max", %0\n\tjle "#loop"\n\t":"=m"(cnt)::) ;
+
+#endif  /* defined(HAVE_INTEL_AVX1) ||  defined(HAVE_INTEL_AVX2) */
+
+#if defined(HAVE_INTEL_AVX1) /* inline Assember for Intel AVX1 instructions */
+
+#define VPALIGNR(op1,op2,op3,op4) __asm__ volatile("vpalignr $"#op4", %"#op3", %"#op2", %"#op1:::XMM_REGs) 
+#define VPADDD(op1,op2,op3)       __asm__ volatile("vpaddd %"#op3", %"#op2", %"#op1:::XMM_REGs)
+#define VPSRLD(op1,op2,op3)       __asm__ volatile("vpsrld $"#op3", %"#op2", %"#op1:::XMM_REGs)
+#define VPSRLQ(op1,op2,op3)       __asm__ volatile("vpsrlq $"#op3", %"#op2", %"#op1:::XMM_REGs)
+#define VPSLLD(op1,op2,op3)       __asm__ volatile("vpslld $"#op3", %"#op2", %"#op1:::XMM_REGs)
+#define VPOR(op1,op2,op3)         __asm__ volatile("vpor   %"#op3", %"#op2", %"#op1:::XMM_REGs)
+#define VPXOR(op1,op2,op3)        __asm__ volatile("vpxor  %"#op3", %"#op2", %"#op1:::XMM_REGs)
+#define VPSHUFD(op1,op2,op3)      __asm__ volatile("vpshufd $"#op3", %"#op2", %"#op1:::XMM_REGs)
+#define VPSHUFB(op1,op2,op3)      __asm__ volatile("vpshufb %"#op3", %"#op2", %"#op1:::XMM_REGs)
+
+#define MessageSched(X0, X1, X2, X3, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, XFER, SHUF_00BA, SHUF_DC00,\
+     a,b,c,d,e,f,g,h,_i)\
+            RND_STEP_1(a,b,c,d,e,f,g,h,_i);\
+    VPALIGNR (XTMP0, X3, X2, 4) ;\
+            RND_STEP_2(a,b,c,d,e,f,g,h,_i);\
+    VPADDD   (XTMP0, XTMP0, X0) ;\
+            RND_STEP_3(a,b,c,d,e,f,g,h,_i);\
+    VPALIGNR (XTMP1, X1, X0, 4) ;   /* XTMP1 = W[-15] */\
+            RND_STEP_4(a,b,c,d,e,f,g,h,_i);\
+    VPSRLD   (XTMP2, XTMP1, 7) ;\
+            RND_STEP_5(a,b,c,d,e,f,g,h,_i);\
+    VPSLLD   (XTMP3, XTMP1, 25) ; /* VPSLLD   (XTMP3, XTMP1, (32-7)) */\
+            RND_STEP_6(a,b,c,d,e,f,g,h,_i);\
+    VPOR     (XTMP3, XTMP3, XTMP2)  ;  /* XTMP1 = W[-15] MY_ROR 7 */\
+            RND_STEP_7(a,b,c,d,e,f,g,h,_i);\
+    VPSRLD   (XTMP2, XTMP1,18) ;\
+            RND_STEP_8(a,b,c,d,e,f,g,h,_i);\
+\
+            RND_STEP_1(h,a,b,c,d,e,f,g,_i+1);\
+    VPSRLD   (XTMP4, XTMP1, 3)      ;  /* XTMP4 = W[-15] >> 3 */\
+            RND_STEP_2(h,a,b,c,d,e,f,g,_i+1);\
+    VPSLLD   (XTMP1, XTMP1, 14) ; /* VPSLLD   (XTMP1, XTMP1, (32-18)) */\
+            RND_STEP_3(h,a,b,c,d,e,f,g,_i+1);\
+    VPXOR    (XTMP3, XTMP3, XTMP1)  ;\
+            RND_STEP_4(h,a,b,c,d,e,f,g,_i+1);\
+    VPXOR    (XTMP3, XTMP3, XTMP2)  ;  /* XTMP1 = W[-15] MY_ROR 7 ^ W[-15] MY_ROR 18 */\
+            RND_STEP_5(h,a,b,c,d,e,f,g,_i+1);\
+    VPXOR    (XTMP1, XTMP3, XTMP4)  ;  /* XTMP1 = s0 */\
+            RND_STEP_6(h,a,b,c,d,e,f,g,_i+1);\
+    VPSHUFD(XTMP2, X3, 0b11111010)  ;  /* XTMP2 = W[-2] {BBAA}*/\
+            RND_STEP_7(h,a,b,c,d,e,f,g,_i+1);\
+    VPADDD   (XTMP0, XTMP0, XTMP1)  ;  /* XTMP0 = W[-16] + W[-7] + s0 */\
+            RND_STEP_8(h,a,b,c,d,e,f,g,_i+1);\
+\
+            RND_STEP_1(g,h,a,b,c,d,e,f,_i+2);\
+    VPSRLD   (XTMP4, XTMP2, 10) ;      /* XTMP4 = W[-2] >> 10 {BBAA} */\
+            RND_STEP_2(g,h,a,b,c,d,e,f,_i+2);\
+    VPSRLQ   (XTMP3, XTMP2, 19) ;      /* XTMP3 = W[-2] MY_ROR 19 {xBxA} */\
+            RND_STEP_3(g,h,a,b,c,d,e,f,_i+2);\
+    VPSRLQ   (XTMP2, XTMP2, 17) ;      /* XTMP2 = W[-2] MY_ROR 17 {xBxA} */\
+            RND_STEP_4(g,h,a,b,c,d,e,f,_i+2);\
+    VPXOR    (XTMP2, XTMP2, XTMP3) ;\
+            RND_STEP_5(g,h,a,b,c,d,e,f,_i+2);\
+    VPXOR    (XTMP4, XTMP4, XTMP2) ;   /* XTMP4 = s1 {xBxA} */\
+            RND_STEP_6(g,h,a,b,c,d,e,f,_i+2);\
+    VPSHUFB  (XTMP4, XTMP4, SHUF_00BA)  ;  /* XTMP4 = s1 {00BA} */\
+            RND_STEP_7(g,h,a,b,c,d,e,f,_i+2);\
+    VPADDD   (XTMP0, XTMP0, XTMP4)  ;  /* XTMP0 = {..., ..., W[1], W[0]} */\
+            RND_STEP_8(g,h,a,b,c,d,e,f,_i+2);\
+\
+            RND_STEP_1(f,g,h,a,b,c,d,e,_i+3);\
+    VPSHUFD  (XTMP2, XTMP0, 0b01010000) ; /* XTMP2 = W[-2] {DDCC} */\
+            RND_STEP_2(f,g,h,a,b,c,d,e,_i+3);\
+    VPSRLD   (XTMP5, XTMP2, 10);       /* XTMP5 = W[-2] >> 10 {DDCC} */\
+            RND_STEP_3(f,g,h,a,b,c,d,e,_i+3);\
+    VPSRLQ   (XTMP3, XTMP2, 19);       /* XTMP3 = W[-2] MY_ROR 19 {xDxC} */\
+            RND_STEP_4(f,g,h,a,b,c,d,e,_i+3);\
+    VPSRLQ   (XTMP2, XTMP2, 17) ;      /* XTMP2 = W[-2] MY_ROR 17 {xDxC} */\
+            RND_STEP_5(f,g,h,a,b,c,d,e,_i+3);\
+    VPXOR    (XTMP2, XTMP2, XTMP3) ;\
+            RND_STEP_6(f,g,h,a,b,c,d,e,_i+3);\
+    VPXOR    (XTMP5, XTMP5, XTMP2) ;   /* XTMP5 = s1 {xDxC} */\
+            RND_STEP_7(f,g,h,a,b,c,d,e,_i+3);\
+    VPSHUFB  (XTMP5, XTMP5, SHUF_DC00) ; /* XTMP5 = s1 {DC00} */\
+            RND_STEP_8(f,g,h,a,b,c,d,e,_i+3);\
+    VPADDD   (X0, XTMP5, XTMP0) ;      /* X0 = {W[3], W[2], W[1], W[0]} */\
+
+#if defined(HAVE_INTEL_RORX)
+
+#define MessageSched_RORX(X0, X1, X2, X3, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, \
+                          XFER, SHUF_00BA, SHUF_DC00,a,b,c,d,e,f,g,h,_i)\
+            RND_STEP_RORX_1(a,b,c,d,e,f,g,h,_i);\
+    VPALIGNR (XTMP0, X3, X2, 4) ;\
+            RND_STEP_RORX_2(a,b,c,d,e,f,g,h,_i);\
+    VPADDD   (XTMP0, XTMP0, X0) ;\
+            RND_STEP_RORX_3(a,b,c,d,e,f,g,h,_i);\
+    VPALIGNR (XTMP1, X1, X0, 4) ;   /* XTMP1 = W[-15] */\
+            RND_STEP_RORX_4(a,b,c,d,e,f,g,h,_i);\
+    VPSRLD   (XTMP2, XTMP1, 7) ;\
+            RND_STEP_RORX_5(a,b,c,d,e,f,g,h,_i);\
+    VPSLLD   (XTMP3, XTMP1, 25) ; /* VPSLLD   (XTMP3, XTMP1, (32-7)) */\
+            RND_STEP_RORX_6(a,b,c,d,e,f,g,h,_i);\
+    VPOR     (XTMP3, XTMP3, XTMP2)  ;  /* XTMP1 = W[-15] MY_ROR 7 */\
+            RND_STEP_RORX_7(a,b,c,d,e,f,g,h,_i);\
+    VPSRLD   (XTMP2, XTMP1,18) ;\
+            RND_STEP_RORX_8(a,b,c,d,e,f,g,h,_i);\
+\
+            RND_STEP_RORX_1(h,a,b,c,d,e,f,g,_i+1);\
+    VPSRLD   (XTMP4, XTMP1, 3)      ;  /* XTMP4 = W[-15] >> 3 */\
+            RND_STEP_RORX_2(h,a,b,c,d,e,f,g,_i+1);\
+    VPSLLD   (XTMP1, XTMP1, 14) ; /* VPSLLD   (XTMP1, XTMP1, (32-18)) */\
+            RND_STEP_RORX_3(h,a,b,c,d,e,f,g,_i+1);\
+    VPXOR    (XTMP3, XTMP3, XTMP1)  ;\
+            RND_STEP_RORX_4(h,a,b,c,d,e,f,g,_i+1);\
+    VPXOR    (XTMP3, XTMP3, XTMP2)  ;  /* XTMP1 = W[-15] MY_ROR 7 ^ W[-15] MY_ROR 18 */\
+            RND_STEP_RORX_5(h,a,b,c,d,e,f,g,_i+1);\
+    VPXOR    (XTMP1, XTMP3, XTMP4)  ;  /* XTMP1 = s0 */\
+            RND_STEP_RORX_6(h,a,b,c,d,e,f,g,_i+1);\
+    VPSHUFD(XTMP2, X3, 0b11111010)  ;  /* XTMP2 = W[-2] {BBAA}*/\
+            RND_STEP_RORX_7(h,a,b,c,d,e,f,g,_i+1);\
+    VPADDD   (XTMP0, XTMP0, XTMP1)  ;  /* XTMP0 = W[-16] + W[-7] + s0 */\
+            RND_STEP_RORX_8(h,a,b,c,d,e,f,g,_i+1);\
+\
+            RND_STEP_RORX_1(g,h,a,b,c,d,e,f,_i+2);\
+    VPSRLD   (XTMP4, XTMP2, 10) ;      /* XTMP4 = W[-2] >> 10 {BBAA} */\
+            RND_STEP_RORX_2(g,h,a,b,c,d,e,f,_i+2);\
+    VPSRLQ   (XTMP3, XTMP2, 19) ;      /* XTMP3 = W[-2] MY_ROR 19 {xBxA} */\
+            RND_STEP_RORX_3(g,h,a,b,c,d,e,f,_i+2);\
+    VPSRLQ   (XTMP2, XTMP2, 17) ;      /* XTMP2 = W[-2] MY_ROR 17 {xBxA} */\
+            RND_STEP_RORX_4(g,h,a,b,c,d,e,f,_i+2);\
+    VPXOR    (XTMP2, XTMP2, XTMP3) ;\
+            RND_STEP_RORX_5(g,h,a,b,c,d,e,f,_i+2);\
+    VPXOR    (XTMP4, XTMP4, XTMP2) ;   /* XTMP4 = s1 {xBxA} */\
+            RND_STEP_RORX_6(g,h,a,b,c,d,e,f,_i+2);\
+    VPSHUFB  (XTMP4, XTMP4, SHUF_00BA)  ;  /* XTMP4 = s1 {00BA} */\
+            RND_STEP_RORX_7(g,h,a,b,c,d,e,f,_i+2);\
+    VPADDD   (XTMP0, XTMP0, XTMP4)  ;  /* XTMP0 = {..., ..., W[1], W[0]} */\
+            RND_STEP_RORX_8(g,h,a,b,c,d,e,f,_i+2);\
+\
+            RND_STEP_RORX_1(f,g,h,a,b,c,d,e,_i+3);\
+    VPSHUFD  (XTMP2, XTMP0, 0b01010000) ; /* XTMP2 = W[-2] {DDCC} */\
+            RND_STEP_RORX_2(f,g,h,a,b,c,d,e,_i+3);\
+    VPSRLD   (XTMP5, XTMP2, 10);       /* XTMP5 = W[-2] >> 10 {DDCC} */\
+            RND_STEP_RORX_3(f,g,h,a,b,c,d,e,_i+3);\
+    VPSRLQ   (XTMP3, XTMP2, 19);       /* XTMP3 = W[-2] MY_ROR 19 {xDxC} */\
+            RND_STEP_RORX_4(f,g,h,a,b,c,d,e,_i+3);\
+    VPSRLQ   (XTMP2, XTMP2, 17) ;      /* XTMP2 = W[-2] MY_ROR 17 {xDxC} */\
+            RND_STEP_RORX_5(f,g,h,a,b,c,d,e,_i+3);\
+    VPXOR    (XTMP2, XTMP2, XTMP3) ;\
+            RND_STEP_RORX_6(f,g,h,a,b,c,d,e,_i+3);\
+    VPXOR    (XTMP5, XTMP5, XTMP2) ;   /* XTMP5 = s1 {xDxC} */\
+            RND_STEP_RORX_7(f,g,h,a,b,c,d,e,_i+3);\
+    VPSHUFB  (XTMP5, XTMP5, SHUF_DC00) ; /* XTMP5 = s1 {DC00} */\
+            RND_STEP_RORX_8(f,g,h,a,b,c,d,e,_i+3);\
+    VPADDD   (X0, XTMP5, XTMP0) ;      /* X0 = {W[3], W[2], W[1], W[0]} */\
+
+#endif
+
+
+#define W_K_from_buff\
+         __asm__ volatile("vmovdqu %0, %%xmm4\n\t"\
+                          "vpshufb %%xmm13, %%xmm4, %%xmm4\n\t"\
+                          :: "m"(sha256->buffer[0]):"%xmm4") ;\
+         __asm__ volatile("vmovdqu %0, %%xmm5\n\t"\
+                          "vpshufb %%xmm13, %%xmm5, %%xmm5\n\t"\
+                          ::"m"(sha256->buffer[4]):"%xmm5") ;\
+         __asm__ volatile("vmovdqu %0, %%xmm6\n\t"\
+                          "vpshufb %%xmm13, %%xmm6, %%xmm6\n\t"\
+                          ::"m"(sha256->buffer[8]):"%xmm6") ;\
+         __asm__ volatile("vmovdqu %0, %%xmm7\n\t"\
+                          "vpshufb %%xmm13, %%xmm7, %%xmm7\n\t"\
+                          ::"m"(sha256->buffer[12]):"%xmm7") ;\
+
+#define _SET_W_K_XFER(reg, i)\
+    __asm__ volatile("vpaddd %0, %"#reg", %%xmm9"::"m"(K[i]):XMM_REGs) ;\
+    __asm__ volatile("vmovdqa %%xmm9, %0":"=m"(W_K[i])::XMM_REGs) ;
+
+#define SET_W_K_XFER(reg, i) _SET_W_K_XFER(reg, i)
+
+static const ALIGN32 word64 mSHUF_00BA[] = { 0x0b0a090803020100, 0xFFFFFFFFFFFFFFFF } ; /* shuffle xBxA -> 00BA */
+static const ALIGN32 word64 mSHUF_DC00[] = { 0xFFFFFFFFFFFFFFFF, 0x0b0a090803020100 } ; /* shuffle xDxC -> DC00 */
+static const ALIGN32 word64 mBYTE_FLIP_MASK[] =  { 0x0405060700010203, 0x0c0d0e0f08090a0b } ;
+
+
+#define _Init_Masks(mask1, mask2, mask3)\
+__asm__ volatile("vmovdqu %0, %"#mask1 ::"m"(mBYTE_FLIP_MASK[0])) ;\
+__asm__ volatile("vmovdqu %0, %"#mask2 ::"m"(mSHUF_00BA[0])) ;\
+__asm__ volatile("vmovdqu %0, %"#mask3 ::"m"(mSHUF_DC00[0])) ;
+
+#define Init_Masks(BYTE_FLIP_MASK, SHUF_00BA, SHUF_DC00)\
+    _Init_Masks(BYTE_FLIP_MASK, SHUF_00BA, SHUF_DC00)
+
+#define X0 %xmm4
+#define X1 %xmm5
+#define X2 %xmm6
+#define X3 %xmm7
+#define X_ X0
+
+#define XTMP0 %xmm0
+#define XTMP1 %xmm1
+#define XTMP2 %xmm2
+#define XTMP3 %xmm3
+#define XTMP4 %xmm8
+#define XTMP5 %xmm9
+#define XFER  %xmm10
+
+#define SHUF_00BA   %xmm11 /* shuffle xBxA -> 00BA */
+#define SHUF_DC00   %xmm12 /* shuffle xDxC -> DC00 */
+#define BYTE_FLIP_MASK  %xmm13
+
+#define XMM_REGs   /* Registers are saved in Sha256Update/Finel */
+                   /*"xmm4","xmm5","xmm6","xmm7","xmm8","xmm9","xmm10","xmm11","xmm12","xmm13" */
+
+static int Transform_AVX1(Sha256* sha256)
+{
+
+    word32 W_K[64] ;  /* temp for W+K */
+
+    #if defined(DEBUG_XMM)
+    int i, j ;
+    word32 xmm[29][4*15] ;
+    #endif
+
+    Init_Masks(BYTE_FLIP_MASK, SHUF_00BA, SHUF_DC00) ;
+    W_K_from_buff ; /* X0, X1, X2, X3 = W[0..15] ; */
+
+    DigestToReg(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7) ;
+  
+    SET_W_K_XFER(X0, 0) ;
+    MessageSched(X0, X1, X2, X3, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, XFER, 
+            SHUF_00BA, SHUF_DC00, S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,0) ;
+    SET_W_K_XFER(X1, 4) ;
+    MessageSched(X1, X2, X3, X0, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, XFER,
+            SHUF_00BA, SHUF_DC00, S_4,S_5,S_6,S_7,S_0,S_1,S_2,S_3,4) ;
+    SET_W_K_XFER(X2, 8) ;
+    MessageSched(X2, X3, X0, X1, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, XFER, 
+            SHUF_00BA, SHUF_DC00, S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,8) ;
+    SET_W_K_XFER(X3, 12) ;
+    MessageSched(X3, X0, X1, X2, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, XFER, 
+            SHUF_00BA, SHUF_DC00, S_4,S_5,S_6,S_7,S_0,S_1,S_2,S_3,12) ;
+    SET_W_K_XFER(X0, 16) ;
+    MessageSched(X0, X1, X2, X3, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, XFER, 
+            SHUF_00BA, SHUF_DC00, S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,16) ;
+    SET_W_K_XFER(X1, 20) ;
+    MessageSched(X1, X2, X3, X0, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, XFER, 
+            SHUF_00BA, SHUF_DC00, S_4,S_5,S_6,S_7,S_0,S_1,S_2,S_3,20) ;
+    SET_W_K_XFER(X2, 24) ;
+    MessageSched(X2, X3, X0, X1, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, XFER, 
+            SHUF_00BA, SHUF_DC00, S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,24) ;
+    SET_W_K_XFER(X3, 28) ;
+    MessageSched(X3, X0, X1, X2, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, XFER, 
+            SHUF_00BA, SHUF_DC00, S_4,S_5,S_6,S_7,S_0,S_1,S_2,S_3,28) ;
+    SET_W_K_XFER(X0, 32) ;
+    MessageSched(X0, X1, X2, X3, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, XFER, 
+            SHUF_00BA, SHUF_DC00, S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,32) ;
+    SET_W_K_XFER(X1, 36) ;
+    MessageSched(X1, X2, X3, X0, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, XFER, 
+            SHUF_00BA, SHUF_DC00, S_4,S_5,S_6,S_7,S_0,S_1,S_2,S_3,36) ;
+    SET_W_K_XFER(X2, 40) ;
+    MessageSched(X2, X3, X0, X1, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, XFER, 
+            SHUF_00BA, SHUF_DC00, S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,40) ;
+    SET_W_K_XFER(X3, 44) ;
+    MessageSched(X3, X0, X1, X2, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, XFER, 
+            SHUF_00BA, SHUF_DC00, S_4,S_5,S_6,S_7,S_0,S_1,S_2,S_3,44) ;
+
+    SET_W_K_XFER(X0, 48) ;
+    SET_W_K_XFER(X1, 52) ;
+    SET_W_K_XFER(X2, 56) ;
+    SET_W_K_XFER(X3, 60) ;
+    
+    RND_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,48) ;
+    RND_7(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,49) ;
+    RND_6(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,50) ;
+    RND_5(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,51) ;
+
+    RND_4(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,52) ;
+    RND_3(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,53) ;
+    RND_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,54) ;
+    RND_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,55) ;
+
+    RND_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,56) ;     
+    RND_7(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,57) ;
+    RND_6(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,58) ;
+    RND_5(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,59) ;
+
+    RND_4(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,60) ;
+    RND_3(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,61) ;
+    RND_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,62) ;
+    RND_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,63) ;
+        
+    RegToDigest(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7) ;  
+        
+    #if defined(DEBUG_XMM)
+    for(i=0; i<29; i++) {
+        for(j=0; j<4*14; j+=4)
+            printf("xmm%d[%d]=%08x,%08x,%08x,%08x\n", j/4, i, 
+                   xmm[i][j],xmm[i][j+1],xmm[i][j+2],xmm[i][j+3]) ;
+        printf("\n") ;
+    }
+        
+    for(i=0; i<64; i++)printf("W_K[%d]%08x\n", i, W_K[i]) ;
+    #endif
+
+    return 0;
+}
+
+#if defined(HAVE_INTEL_RORX)
+static int Transform_AVX1_RORX(Sha256* sha256)
+{
+
+    word32 W_K[64] ;  /* temp for W+K */
+
+    #if defined(DEBUG_XMM)
+    int i, j ;
+    word32 xmm[29][4*15] ;
+    #endif
+
+    Init_Masks(BYTE_FLIP_MASK, SHUF_00BA, SHUF_DC00) ;
+    W_K_from_buff ; /* X0, X1, X2, X3 = W[0..15] ; */
+
+    DigestToReg(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7) ;
+    SET_W_K_XFER(X0, 0) ;
+    MessageSched_RORX(X0, X1, X2, X3, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, 
+            XFER, SHUF_00BA, SHUF_DC00, S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,0) ;
+    SET_W_K_XFER(X1, 4) ;
+    MessageSched_RORX(X1, X2, X3, X0, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, 
+            XFER, SHUF_00BA, SHUF_DC00, S_4,S_5,S_6,S_7,S_0,S_1,S_2,S_3,4) ;
+    SET_W_K_XFER(X2, 8) ;
+    MessageSched_RORX(X2, X3, X0, X1, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, 
+            XFER, SHUF_00BA, SHUF_DC00, S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,8) ;
+    SET_W_K_XFER(X3, 12) ;
+    MessageSched_RORX(X3, X0, X1, X2, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, 
+            XFER, SHUF_00BA, SHUF_DC00, S_4,S_5,S_6,S_7,S_0,S_1,S_2,S_3,12) ;
+    SET_W_K_XFER(X0, 16) ;
+    MessageSched_RORX(X0, X1, X2, X3, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, 
+            XFER, SHUF_00BA, SHUF_DC00, S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,16) ;
+    SET_W_K_XFER(X1, 20) ;
+    MessageSched_RORX(X1, X2, X3, X0, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, 
+            XFER, SHUF_00BA, SHUF_DC00, S_4,S_5,S_6,S_7,S_0,S_1,S_2,S_3,20) ;
+    SET_W_K_XFER(X2, 24) ;
+    MessageSched_RORX(X2, X3, X0, X1, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, 
+            XFER, SHUF_00BA, SHUF_DC00, S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,24) ;
+    SET_W_K_XFER(X3, 28) ;
+    MessageSched_RORX(X3, X0, X1, X2, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, 
+            XFER, SHUF_00BA, SHUF_DC00, S_4,S_5,S_6,S_7,S_0,S_1,S_2,S_3,28) ;
+    SET_W_K_XFER(X0, 32) ;
+    MessageSched_RORX(X0, X1, X2, X3, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, 
+            XFER, SHUF_00BA, SHUF_DC00, S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,32) ;
+    SET_W_K_XFER(X1, 36) ;
+    MessageSched_RORX(X1, X2, X3, X0, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5, 
+            XFER, SHUF_00BA, SHUF_DC00, S_4,S_5,S_6,S_7,S_0,S_1,S_2,S_3,36) ;
+    SET_W_K_XFER(X2, 40) ;
+    MessageSched_RORX(X2, X3, X0, X1, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5,
+            XFER, SHUF_00BA, SHUF_DC00, S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,40) ;
+    SET_W_K_XFER(X3, 44) ;
+    MessageSched_RORX(X3, X0, X1, X2, XTMP0, XTMP1, XTMP2, XTMP3, XTMP4, XTMP5,
+            XFER, SHUF_00BA, SHUF_DC00, S_4,S_5,S_6,S_7,S_0,S_1,S_2,S_3,44) ;
+
+    SET_W_K_XFER(X0, 48) ;
+    SET_W_K_XFER(X1, 52) ;
+    SET_W_K_XFER(X2, 56) ;
+    SET_W_K_XFER(X3, 60) ;
+    
+    RND_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,48) ;
+    RND_7(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,49) ;
+    RND_6(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,50) ;
+    RND_5(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,51) ;
+
+    RND_4(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,52) ;
+    RND_3(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,53) ;
+    RND_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,54) ;
+    RND_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,55) ;
+
+    RND_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,56) ;     
+    RND_7(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,57) ;
+    RND_6(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,58) ;
+    RND_5(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,59) ;
+
+    RND_4(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,60) ;
+    RND_3(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,61) ;
+    RND_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,62) ;
+    RND_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,63) ;
+        
+    RegToDigest(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7) ;  
+        
+    #if defined(DEBUG_XMM)
+    for(i=0; i<29; i++) {
+        for(j=0; j<4*14; j+=4)
+            printf("xmm%d[%d]=%08x,%08x,%08x,%08x\n", j/4, i, 
+                    xmm[i][j],xmm[i][j+1],xmm[i][j+2],xmm[i][j+3]) ;
+        printf("\n") ;
+    }
+        
+    for(i=0; i<64; i++)printf("W_K[%d]%08x\n", i, W_K[i]) ;
+    #endif
+
+    return 0;
+}
+#endif  /* HAVE_INTEL_RORX */
+
+#endif  /* HAVE_INTEL_AVX1 */
+
+
+#if defined(HAVE_INTEL_AVX2)
+
+#define _MOVE_to_REG(ymm, mem)       __asm__ volatile("vmovdqu %0, %%"#ymm" ":: "m"(mem):YMM_REGs) ;
+#define _MOVE_to_MEM(mem, ymm)       __asm__ volatile("vmovdqu %%"#ymm", %0" : "=m"(mem)::YMM_REGs) ;
+#define _BYTE_SWAP(ymm, map)              __asm__ volatile("vpshufb %0, %%"#ymm", %%"#ymm"\n\t"\
+                                                       :: "m"(map):YMM_REGs) ;
+#define _MOVE_128(ymm0, ymm1, ymm2, map)   __asm__ volatile("vperm2i128  $"#map", %%"\
+                                  #ymm2", %%"#ymm1", %%"#ymm0" ":::YMM_REGs) ;
+#define _MOVE_BYTE(ymm0, ymm1, map)  __asm__ volatile("vpshufb %0, %%"#ymm1", %%"\
+                                  #ymm0"\n\t":: "m"(map):YMM_REGs) ;
+#define _S_TEMP(dest, src, bits, temp)    __asm__ volatile("vpsrld  $"#bits", %%"\
+         #src", %%"#dest"\n\tvpslld  $32-"#bits", %%"#src", %%"#temp"\n\tvpor %%"\
+         #temp",%%"#dest", %%"#dest" ":::YMM_REGs) ;
+#define _AVX2_R(dest, src, bits)          __asm__ volatile("vpsrld  $"#bits", %%"\
+                                  #src", %%"#dest" ":::YMM_REGs) ;
+#define _XOR(dest, src1, src2)       __asm__ volatile("vpxor   %%"#src1", %%"\
+         #src2", %%"#dest" ":::YMM_REGs) ;
+#define _OR(dest, src1, src2)       __asm__ volatile("vpor    %%"#src1", %%"\
+         #src2", %%"#dest" ":::YMM_REGs) ;
+#define _ADD(dest, src1, src2)       __asm__ volatile("vpaddd   %%"#src1", %%"\
+         #src2", %%"#dest" ":::YMM_REGs) ;
+#define _ADD_MEM(dest, src1, mem)    __asm__ volatile("vpaddd   %0, %%"#src1", %%"\
+         #dest" "::"m"(mem):YMM_REGs) ;
+#define _BLEND(map, dest, src1, src2)    __asm__ volatile("vpblendd    $"#map", %%"\
+         #src1",   %%"#src2", %%"#dest" ":::YMM_REGs) ;
+
+#define    _EXTRACT_XMM_0(xmm, mem)  __asm__ volatile("vpextrd $0, %%"#xmm", %0 ":"=r"(mem)::YMM_REGs) ;
+#define    _EXTRACT_XMM_1(xmm, mem)  __asm__ volatile("vpextrd $1, %%"#xmm", %0 ":"=r"(mem)::YMM_REGs) ;
+#define    _EXTRACT_XMM_2(xmm, mem)  __asm__ volatile("vpextrd $2, %%"#xmm", %0 ":"=r"(mem)::YMM_REGs) ;
+#define    _EXTRACT_XMM_3(xmm, mem)  __asm__ volatile("vpextrd $3, %%"#xmm", %0 ":"=r"(mem)::YMM_REGs) ;
+#define    _EXTRACT_XMM_4(ymm, xmm, mem)\
+      __asm__ volatile("vperm2i128 $0x1, %%"#ymm", %%"#ymm", %%"#ymm" ":::YMM_REGs) ;\
+      __asm__ volatile("vpextrd $0, %%"#xmm", %0 ":"=r"(mem)::YMM_REGs) ;
+#define    _EXTRACT_XMM_5(xmm, mem)  __asm__ volatile("vpextrd $1, %%"#xmm", %0 ":"=r"(mem)::YMM_REGs) ;
+#define    _EXTRACT_XMM_6(xmm, mem)  __asm__ volatile("vpextrd $2, %%"#xmm", %0 ":"=r"(mem)::YMM_REGs) ;
+#define    _EXTRACT_XMM_7(xmm, mem)  __asm__ volatile("vpextrd $3, %%"#xmm", %0 ":"=r"(mem)::YMM_REGs) ;
+
+#define    _SWAP_YMM_HL(ymm)   __asm__ volatile("vperm2i128 $0x1, %%"#ymm", %%"#ymm", %%"#ymm" ":::YMM_REGs) ;
+#define     SWAP_YMM_HL(ymm)   _SWAP_YMM_HL(ymm) 
+
+#define MOVE_to_REG(ymm, mem)      _MOVE_to_REG(ymm, mem)
+#define MOVE_to_MEM(mem, ymm)      _MOVE_to_MEM(mem, ymm)
+#define BYTE_SWAP(ymm, map)        _BYTE_SWAP(ymm, map)
+#define MOVE_128(ymm0, ymm1, ymm2, map) _MOVE_128(ymm0, ymm1, ymm2, map) 
+#define MOVE_BYTE(ymm0, ymm1, map) _MOVE_BYTE(ymm0, ymm1, map)
+#define XOR(dest, src1, src2)      _XOR(dest, src1, src2)
+#define OR(dest, src1, src2)       _OR(dest, src1, src2)
+#define ADD(dest, src1, src2)      _ADD(dest, src1, src2)
+#define ADD_MEM(dest, src1, mem)  _ADD_MEM(dest, src1, mem)
+#define BLEND(map, dest, src1, src2) _BLEND(map, dest, src1, src2)
+
+#define S_TMP(dest, src, bits, temp) _S_TEMP(dest, src, bits, temp); 
+#define AVX2_S(dest, src, bits)      S_TMP(dest, src, bits, S_TEMP)
+#define AVX2_R(dest, src, bits)      _AVX2_R(dest, src, bits)
+
+#define GAMMA0(dest, src)      AVX2_S(dest, src, 7);  AVX2_S(G_TEMP, src, 18); \
+    XOR(dest, G_TEMP, dest) ; AVX2_R(G_TEMP, src, 3);  XOR(dest, G_TEMP, dest) ;
+#define GAMMA0_1(dest, src)    AVX2_S(dest, src, 7);  AVX2_S(G_TEMP, src, 18); 
+#define GAMMA0_2(dest, src)    XOR(dest, G_TEMP, dest) ; AVX2_R(G_TEMP, src, 3);  \
+    XOR(dest, G_TEMP, dest) ;
+
+#define GAMMA1(dest, src)      AVX2_S(dest, src, 17); AVX2_S(G_TEMP, src, 19); \
+    XOR(dest, G_TEMP, dest) ; AVX2_R(G_TEMP, src, 10); XOR(dest, G_TEMP, dest) ;
+#define GAMMA1_1(dest, src)    AVX2_S(dest, src, 17); AVX2_S(G_TEMP, src, 19); 
+#define GAMMA1_2(dest, src)    XOR(dest, G_TEMP, dest) ; AVX2_R(G_TEMP, src, 10); \
+    XOR(dest, G_TEMP, dest) ;
+
+#define    FEEDBACK1_to_W_I_2    MOVE_BYTE(YMM_TEMP0, W_I, mMAP1toW_I_2[0]) ; \
+    BLEND(0x0c, W_I_2, YMM_TEMP0, W_I_2) ;
+#define    FEEDBACK2_to_W_I_2    MOVE_128(YMM_TEMP0, W_I, W_I, 0x08) ;  \
+    MOVE_BYTE(YMM_TEMP0, YMM_TEMP0, mMAP2toW_I_2[0]) ; BLEND(0x30, W_I_2, YMM_TEMP0, W_I_2) ; 
+#define    FEEDBACK3_to_W_I_2    MOVE_BYTE(YMM_TEMP0, W_I, mMAP3toW_I_2[0]) ; \
+    BLEND(0xc0, W_I_2, YMM_TEMP0, W_I_2) ; 
+
+#define    FEEDBACK_to_W_I_7     MOVE_128(YMM_TEMP0, W_I, W_I, 0x08) ;\
+    MOVE_BYTE(YMM_TEMP0, YMM_TEMP0, mMAPtoW_I_7[0]) ; BLEND(0x80, W_I_7, YMM_TEMP0, W_I_7) ;
+
+#undef voitle
+
+#define W_I_16  ymm8
+#define W_I_15  ymm9
+#define W_I_7  ymm10
+#define W_I_2  ymm11
+#define W_I    ymm12
+#define G_TEMP     ymm13
+#define S_TEMP     ymm14
+#define YMM_TEMP0  ymm15
+#define YMM_TEMP0x xmm15
+#define W_I_TEMP   ymm7
+#define W_K_TEMP   ymm15
+#define W_K_TEMPx  xmm15
+
+#define YMM_REGs /* Registers are saved in Sha256Update/Finel */
+ /* "%ymm7","%ymm8","%ymm9","%ymm10","%ymm11","%ymm12","%ymm13","%ymm14","%ymm15"*/
+
+
+#define MOVE_15_to_16(w_i_16, w_i_15, w_i_7)\
+    __asm__ volatile("vperm2i128  $0x01, %%"#w_i_15", %%"#w_i_15", %%"#w_i_15" ":::YMM_REGs) ;\
+    __asm__ volatile("vpblendd    $0x08, %%"#w_i_15", %%"#w_i_7", %%"#w_i_16" ":::YMM_REGs) ;\
+    __asm__ volatile("vperm2i128 $0x01,  %%"#w_i_7",  %%"#w_i_7", %%"#w_i_15" ":::YMM_REGs) ;\
+    __asm__ volatile("vpblendd    $0x80, %%"#w_i_15", %%"#w_i_16", %%"#w_i_16" ":::YMM_REGs) ;\
+    __asm__ volatile("vpshufd    $0x93,  %%"#w_i_16", %%"#w_i_16" ":::YMM_REGs) ;\
+
+#define MOVE_7_to_15(w_i_15, w_i_7)\
+    __asm__ volatile("vmovdqu                 %%"#w_i_7",  %%"#w_i_15" ":::YMM_REGs) ;\
+
+#define MOVE_I_to_7(w_i_7, w_i)\
+    __asm__ volatile("vperm2i128 $0x01,       %%"#w_i",   %%"#w_i",   %%"#w_i_7" ":::YMM_REGs) ;\
+    __asm__ volatile("vpblendd    $0x01,       %%"#w_i_7",   %%"#w_i", %%"#w_i_7" ":::YMM_REGs) ;\
+    __asm__ volatile("vpshufd    $0x39, %%"#w_i_7", %%"#w_i_7" ":::YMM_REGs) ;\
+
+#define MOVE_I_to_2(w_i_2, w_i)\
+    __asm__ volatile("vperm2i128 $0x01,       %%"#w_i", %%"#w_i", %%"#w_i_2" ":::YMM_REGs) ;\
+    __asm__ volatile("vpshufd    $0x0e, %%"#w_i_2", %%"#w_i_2" ":::YMM_REGs) ;\
+
+#define ROTATE_W(w_i_16, w_i_15, w_i_7, w_i_2, w_i)\
+    MOVE_15_to_16(w_i_16, w_i_15, w_i_7) ; \
+    MOVE_7_to_15(w_i_15, w_i_7) ; \
+    MOVE_I_to_7(w_i_7, w_i) ; \
+    MOVE_I_to_2(w_i_2, w_i) ;\
+
+#define _RegToDigest(S_0, S_1, S_2, S_3, S_4, S_5, S_6, S_7 )\
+    { word32 d ;\
+    __asm__ volatile("movl %"#S_0", %0":"=r"(d)::SSE_REGs) ;\
+    sha256->digest[0] += d;\
+    __asm__ volatile("movl %"#S_1", %0":"=r"(d)::SSE_REGs) ;\
+    sha256->digest[1] += d;\
+    __asm__ volatile("movl %"#S_2", %0":"=r"(d)::SSE_REGs) ;\
+    sha256->digest[2] += d;\
+    __asm__ volatile("movl %"#S_3", %0":"=r"(d)::SSE_REGs) ;\
+    sha256->digest[3] += d;\
+    __asm__ volatile("movl %"#S_4", %0":"=r"(d)::SSE_REGs) ;\
+    sha256->digest[4] += d;\
+    __asm__ volatile("movl %"#S_5", %0":"=r"(d)::SSE_REGs) ;\
+    sha256->digest[5] += d;\
+    __asm__ volatile("movl %"#S_6", %0":"=r"(d)::SSE_REGs) ;\
+    sha256->digest[6] += d;\
+    __asm__ volatile("movl %"#S_7", %0":"=r"(d)::SSE_REGs) ;\
+    sha256->digest[7] += d;\
+}
+
+#define _DumpS(S_0, S_1, S_2, S_3, S_4, S_5, S_6, S_7 )\
+  { word32 d[8] ;\
+    __asm__ volatile("movl %"#S_0", %0":"=r"(d[0])::SSE_REGs) ;\
+    __asm__ volatile("movl %"#S_1", %0":"=r"(d[1])::SSE_REGs) ;\
+    __asm__ volatile("movl %"#S_2", %0":"=r"(d[2])::SSE_REGs) ;\
+    __asm__ volatile("movl %"#S_3", %0":"=r"(d[3])::SSE_REGs) ;\
+    __asm__ volatile("movl %"#S_4", %0":"=r"(d[4])::SSE_REGs) ;\
+    __asm__ volatile("movl %"#S_5", %0":"=r"(d[5])::SSE_REGs) ;\
+    __asm__ volatile("movl %"#S_6", %0":"=r"(d[6])::SSE_REGs) ;\
+    __asm__ volatile("movl %"#S_7", %0":"=r"(d[7])::SSE_REGs) ;\
+        printf("S[0..7]=%08x,%08x,%08x,%08x,%08x,%08x,%08x,%08x\n", d[0],d[1],d[2],d[3],d[4],d[5],d[6],d[7]);\
+    __asm__ volatile("movl %0, %"#S_0::"r"(d[0]):SSE_REGs) ;\
+    __asm__ volatile("movl %0, %"#S_1::"r"(d[1]):SSE_REGs) ;\
+    __asm__ volatile("movl %0, %"#S_2::"r"(d[2]):SSE_REGs) ;\
+    __asm__ volatile("movl %0, %"#S_3::"r"(d[3]):SSE_REGs) ;\
+    __asm__ volatile("movl %0, %"#S_4::"r"(d[4]):SSE_REGs) ;\
+    __asm__ volatile("movl %0, %"#S_5::"r"(d[5]):SSE_REGs) ;\
+    __asm__ volatile("movl %0, %"#S_6::"r"(d[6]):SSE_REGs) ;\
+    __asm__ volatile("movl %0, %"#S_7::"r"(d[7]):SSE_REGs) ;\
+}
+
+
+#define DigestToReg(S_0, S_1, S_2, S_3, S_4, S_5, S_6, S_7 )\
+    _DigestToReg(S_0, S_1, S_2, S_3, S_4, S_5, S_6, S_7 )
+
+#define RegToDigest(S_0, S_1, S_2, S_3, S_4, S_5, S_6, S_7 )\
+    _RegToDigest(S_0, S_1, S_2, S_3, S_4, S_5, S_6, S_7 )
+
+#define DumS(S_0, S_1, S_2, S_3, S_4, S_5, S_6, S_7 )\
+    _DumpS(S_0, S_1, S_2, S_3, S_4, S_5, S_6, S_7 )
+
+        
+    /* Byte swap Masks to ensure that rest of the words are filled with zero's. */
+    static const unsigned long mBYTE_FLIP_MASK_16[] =  
+        { 0x0405060700010203, 0x0c0d0e0f08090a0b, 0x0405060700010203, 0x0c0d0e0f08090a0b } ;
+    static const unsigned long mBYTE_FLIP_MASK_15[] =  
+        { 0x0405060700010203, 0x0c0d0e0f08090a0b, 0x0405060700010203, 0x0c0d0e0f08090a0b } ;
+    static const unsigned long mBYTE_FLIP_MASK_7 [] =  
+        { 0x0405060700010203, 0x0c0d0e0f08090a0b, 0x0405060700010203, 0x8080808008090a0b } ;
+    static const unsigned long mBYTE_FLIP_MASK_2 [] =  
+        { 0x0405060700010203, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080 } ;
+
+    static const unsigned long mMAPtoW_I_7[] =  
+        { 0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x0302010080808080 } ;
+    static const unsigned long mMAP1toW_I_2[] = 
+        { 0x8080808080808080, 0x0706050403020100, 0x8080808080808080, 0x8080808080808080 } ;
+    static const unsigned long mMAP2toW_I_2[] = 
+        { 0x8080808080808080, 0x8080808080808080, 0x0f0e0d0c0b0a0908, 0x8080808080808080 } ;
+    static const unsigned long mMAP3toW_I_2[] = 
+        { 0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x0706050403020100 } ;
+ 
+static int Transform_AVX2(Sha256* sha256)
+{
+
+    #ifdef WOLFSSL_SMALL_STACK
+        word32* W_K;
+        W_K = (word32*) XMALLOC(sizeof(word32) * 64, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+        if (W_K == NULL)
+            return MEMORY_E;
+    #else
+        word32 W_K[64]  ;
+    #endif
+
+    MOVE_to_REG(W_I_16, sha256->buffer[0]);     BYTE_SWAP(W_I_16, mBYTE_FLIP_MASK_16[0]) ;
+    MOVE_to_REG(W_I_15, sha256->buffer[1]);     BYTE_SWAP(W_I_15, mBYTE_FLIP_MASK_15[0]) ;
+    MOVE_to_REG(W_I,    sha256->buffer[8]) ;    BYTE_SWAP(W_I,    mBYTE_FLIP_MASK_16[0]) ;
+    MOVE_to_REG(W_I_7,  sha256->buffer[16-7]) ; BYTE_SWAP(W_I_7,  mBYTE_FLIP_MASK_7[0])  ;
+    MOVE_to_REG(W_I_2,  sha256->buffer[16-2]) ; BYTE_SWAP(W_I_2,  mBYTE_FLIP_MASK_2[0])  ;
+
+    DigestToReg(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7) ;
+
+    ADD_MEM(W_K_TEMP, W_I_16, K[0]) ;
+    MOVE_to_MEM(W_K[0], W_K_TEMP) ; 
+
+    RND_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,0) ;
+    RND_7(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,1) ;
+    RND_6(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,2) ;
+    RND_5(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,3) ;  
+    RND_4(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,4) ;
+    RND_3(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,5) ;
+    RND_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,6) ;
+    RND_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,7) ;
+
+    ADD_MEM(YMM_TEMP0, W_I, K[8]) ;
+    MOVE_to_MEM(W_K[8], YMM_TEMP0) ; 
+
+        /* W[i] = Gamma1(W[i-2]) + W[i-7] + Gamma0(W[i-15] + W[i-16]) */
+                RND_0_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,8) ;
+        GAMMA0_1(W_I_TEMP, W_I_15) ;
+                RND_0_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,8) ;
+        GAMMA0_2(W_I_TEMP, W_I_15) ;
+                RND_0_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,8) ;
+        ADD(W_I_TEMP, W_I_16, W_I_TEMP) ;/* for saving W_I before adding incomplete W_I_7 */
+                RND_7_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,9) ;
+        ADD(W_I, W_I_7, W_I_TEMP);
+                RND_7_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,9) ;
+        GAMMA1_1(YMM_TEMP0, W_I_2) ; 
+                RND_7_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,9) ;
+        GAMMA1_2(YMM_TEMP0, W_I_2) ; 
+                RND_6_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,10) ;
+        ADD(W_I, W_I, YMM_TEMP0) ;/* now W[16..17] are completed */
+                RND_6_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,10) ;
+        FEEDBACK1_to_W_I_2 ;
+                RND_6_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,10) ;
+        FEEDBACK_to_W_I_7 ; 
+                RND_5_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,11) ;
+        ADD(W_I_TEMP, W_I_7, W_I_TEMP);
+                RND_5_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,11) ;
+        GAMMA1_1(YMM_TEMP0, W_I_2) ; 
+                RND_5_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,11) ;
+        GAMMA1_2(YMM_TEMP0, W_I_2) ; 
+                RND_4_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,12) ;
+        ADD(W_I, W_I_TEMP, YMM_TEMP0) ;/* now W[16..19] are completed */
+                RND_4_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,12) ;
+        FEEDBACK2_to_W_I_2 ;
+                RND_4_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,12) ;
+        GAMMA1_1(YMM_TEMP0, W_I_2) ;
+                RND_3_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,13) ;
+        GAMMA1_2(YMM_TEMP0, W_I_2) ; 
+                RND_3_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,13) ;
+        ADD(W_I, W_I_TEMP, YMM_TEMP0) ; /* now W[16..21] are completed */
+                RND_3_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,13) ;
+        FEEDBACK3_to_W_I_2 ;
+                RND_2_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,14) ;
+        GAMMA1(YMM_TEMP0, W_I_2) ;
+                RND_2_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,14) ;
+                RND_2_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,14) ;
+        ADD(W_I, W_I_TEMP, YMM_TEMP0) ; /* now W[16..23] are completed */
+                RND_1_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,15) ;
+
+        MOVE_to_REG(YMM_TEMP0, K[16]) ;    
+                RND_1_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,15) ;
+        ROTATE_W(W_I_16, W_I_15, W_I_7, W_I_2, W_I) ;
+                RND_1_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,15) ;
+        ADD(YMM_TEMP0, YMM_TEMP0, W_I) ;
+        MOVE_to_MEM(W_K[16], YMM_TEMP0) ;
+
+        /* W[i] = Gamma1(W[i-2]) + W[i-7] + Gamma0(W[i-15] + W[i-16]) */
+                RND_0_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,16) ;
+        GAMMA0_1(W_I_TEMP, W_I_15) ;
+                RND_0_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,16) ;
+        GAMMA0_2(W_I_TEMP, W_I_15) ;
+                RND_0_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,16) ;
+        ADD(W_I_TEMP, W_I_16, W_I_TEMP) ;/* for saving W_I before adding incomplete W_I_7 */
+                RND_7_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,17) ;
+        ADD(W_I, W_I_7, W_I_TEMP);
+                RND_7_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,17) ;
+        GAMMA1_1(YMM_TEMP0, W_I_2) ; 
+                RND_7_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,17) ;
+        GAMMA1_2(YMM_TEMP0, W_I_2) ; 
+                RND_6_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,18) ;
+        ADD(W_I, W_I, YMM_TEMP0) ;/* now W[16..17] are completed */
+                RND_6_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,18) ;
+        FEEDBACK1_to_W_I_2 ;
+                RND_6_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,18) ;
+        FEEDBACK_to_W_I_7 ; 
+                RND_5_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,19) ;
+        ADD(W_I_TEMP, W_I_7, W_I_TEMP);
+                RND_5_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,19) ;
+        GAMMA1(YMM_TEMP0, W_I_2) ; 
+                RND_5_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,19) ;
+        GAMMA1_2(YMM_TEMP0, W_I_2) ; 
+                RND_4_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,20) ;
+        ADD(W_I, W_I_TEMP, YMM_TEMP0) ;/* now W[16..19] are completed */
+                RND_4_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,20) ;
+        FEEDBACK2_to_W_I_2 ;
+                RND_4_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,20) ;
+        GAMMA1_1(YMM_TEMP0, W_I_2) ;
+                RND_3_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,21) ;
+        GAMMA1_2(YMM_TEMP0, W_I_2) ; 
+                RND_3_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,21) ;
+        ADD(W_I, W_I_TEMP, YMM_TEMP0) ; /* now W[16..21] are completed */
+                RND_3_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,21) ;
+        FEEDBACK3_to_W_I_2 ;
+                RND_2_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,22) ;
+        GAMMA1_1(YMM_TEMP0, W_I_2) ;
+                RND_2_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,22) ;
+        GAMMA1_2(YMM_TEMP0, W_I_2) ; 
+                RND_2_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,22) ;
+        ADD(W_I, W_I_TEMP, YMM_TEMP0) ; /* now W[16..23] are completed */
+                RND_1_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,23) ;
+
+        MOVE_to_REG(YMM_TEMP0, K[24]) ;    
+                RND_1_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,23) ;
+        ROTATE_W(W_I_16, W_I_15, W_I_7, W_I_2, W_I) ;
+                RND_1_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,23) ;
+        ADD(YMM_TEMP0, YMM_TEMP0, W_I) ;
+        MOVE_to_MEM(W_K[24], YMM_TEMP0) ;
+
+                /* W[i] = Gamma1(W[i-2]) + W[i-7] + Gamma0(W[i-15] + W[i-16]) */
+                RND_0_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,24) ;
+        GAMMA0_1(W_I_TEMP, W_I_15) ;
+                RND_0_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,24) ;
+        GAMMA0_2(W_I_TEMP, W_I_15) ;
+                RND_0_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,24) ;
+        ADD(W_I_TEMP, W_I_16, W_I_TEMP) ;/* for saving W_I before adding incomplete W_I_7 */
+                RND_7_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,25) ;
+        ADD(W_I, W_I_7, W_I_TEMP);
+                RND_7_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,25) ;
+        GAMMA1_1(YMM_TEMP0, W_I_2) ; 
+                RND_7_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,25) ;
+        GAMMA1_2(YMM_TEMP0, W_I_2) ; 
+                RND_6_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,26) ;
+        ADD(W_I, W_I, YMM_TEMP0) ;/* now W[16..17] are completed */
+                RND_6_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,26) ;
+        FEEDBACK1_to_W_I_2 ;
+                RND_6_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,26) ;
+        FEEDBACK_to_W_I_7 ; 
+                RND_5_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,27) ;
+        ADD(W_I_TEMP, W_I_7, W_I_TEMP);
+                RND_5_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,27) ;
+        GAMMA1_1(YMM_TEMP0, W_I_2) ; 
+                RND_5_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,27) ;
+        GAMMA1_2(YMM_TEMP0, W_I_2) ; 
+                RND_4_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,28) ;
+        ADD(W_I, W_I_TEMP, YMM_TEMP0) ;/* now W[16..19] are completed */
+                RND_4_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,28) ;
+        FEEDBACK2_to_W_I_2 ;
+                RND_4_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,28) ;
+        GAMMA1_1(YMM_TEMP0, W_I_2) ;
+                RND_3_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,29) ;
+        GAMMA1_2(YMM_TEMP0, W_I_2) ; 
+                RND_3_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,29) ;
+        ADD(W_I, W_I_TEMP, YMM_TEMP0) ; /* now W[16..21] are completed */
+                RND_3_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,29) ;
+        FEEDBACK3_to_W_I_2 ;
+                RND_2_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,30) ;
+        GAMMA1(YMM_TEMP0, W_I_2) ;
+                RND_2_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,30) ;
+                RND_2_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,30) ;
+        ADD(W_I, W_I_TEMP, YMM_TEMP0) ; /* now W[16..23] are completed */
+                RND_1_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,31) ;
+
+        MOVE_to_REG(YMM_TEMP0, K[32]) ;    
+                RND_1_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,31) ;
+        ROTATE_W(W_I_16, W_I_15, W_I_7, W_I_2, W_I) ;
+                RND_1_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,31) ;
+        ADD(YMM_TEMP0, YMM_TEMP0, W_I) ;
+        MOVE_to_MEM(W_K[32], YMM_TEMP0) ;
+
+        
+                /* W[i] = Gamma1(W[i-2]) + W[i-7] + Gamma0(W[i-15] + W[i-16]) */
+                RND_0_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,32) ;
+        GAMMA0_1(W_I_TEMP, W_I_15) ;
+                RND_0_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,32) ;
+        GAMMA0_2(W_I_TEMP, W_I_15) ;
+                RND_0_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,32) ;
+        ADD(W_I_TEMP, W_I_16, W_I_TEMP) ;/* for saving W_I before adding incomplete W_I_7 */
+                RND_7_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,33) ;
+        ADD(W_I, W_I_7, W_I_TEMP);
+                RND_7_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,33) ;
+        GAMMA1_1(YMM_TEMP0, W_I_2) ;
+                RND_7_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,33) ;
+        GAMMA1_2(YMM_TEMP0, W_I_2) ; 
+                RND_6_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,34) ;
+        ADD(W_I, W_I, YMM_TEMP0) ;/* now W[16..17] are completed */
+                RND_6_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,34) ;
+        FEEDBACK1_to_W_I_2 ;
+                RND_6_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,34) ;
+        FEEDBACK_to_W_I_7 ; 
+                RND_5_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,35) ;
+        ADD(W_I_TEMP, W_I_7, W_I_TEMP);
+                RND_5_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,35) ;
+        GAMMA1_1(YMM_TEMP0, W_I_2) ;
+                RND_5_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,35) ;
+        GAMMA1_2(YMM_TEMP0, W_I_2) ;
+                RND_4_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,36) ;
+        ADD(W_I, W_I_TEMP, YMM_TEMP0) ;/* now W[16..19] are completed */
+                RND_4_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,36) ;
+        FEEDBACK2_to_W_I_2 ;
+                RND_4_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,36) ;
+        GAMMA1_1(YMM_TEMP0, W_I_2) ;
+                RND_3_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,37) ;
+        GAMMA1_2(YMM_TEMP0, W_I_2) ;
+                RND_3_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,37) ;
+        ADD(W_I, W_I_TEMP, YMM_TEMP0) ; /* now W[16..21] are completed */
+                RND_3_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,37) ;
+        FEEDBACK3_to_W_I_2 ;
+                RND_2_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,38) ;
+        GAMMA1_1(YMM_TEMP0, W_I_2) ;
+                RND_2_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,38) ;
+        GAMMA1_2(YMM_TEMP0, W_I_2) ;
+                RND_2_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,38) ;
+        ADD(W_I, W_I_TEMP, YMM_TEMP0) ; /* now W[16..23] are completed */
+                RND_1_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,39) ;
+
+        MOVE_to_REG(YMM_TEMP0, K[40]) ;    
+                RND_1_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,39) ;
+        ROTATE_W(W_I_16, W_I_15, W_I_7, W_I_2, W_I) ;
+                RND_1_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,39) ;
+        ADD(YMM_TEMP0, YMM_TEMP0, W_I) ;
+        MOVE_to_MEM(W_K[40], YMM_TEMP0) ;
+
+                /* W[i] = Gamma1(W[i-2]) + W[i-7] + Gamma0(W[i-15] + W[i-16]) */
+                RND_0_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,40) ;
+        GAMMA0_1(W_I_TEMP, W_I_15) ;
+                RND_0_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,40) ;
+        GAMMA0_2(W_I_TEMP, W_I_15) ;
+                RND_0_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,40) ;
+        ADD(W_I_TEMP, W_I_16, W_I_TEMP) ;/* for saving W_I before adding incomplete W_I_7 */
+                RND_7_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,41) ;
+        ADD(W_I, W_I_7, W_I_TEMP);
+                RND_7_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,41) ;
+        GAMMA1_1(YMM_TEMP0, W_I_2) ;
+                RND_7_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,41) ;
+        GAMMA1_2(YMM_TEMP0, W_I_2) ;
+                RND_6_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,42) ;
+        ADD(W_I, W_I, YMM_TEMP0) ;/* now W[16..17] are completed */
+                RND_6_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,42) ;
+        FEEDBACK1_to_W_I_2 ;
+                RND_6_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,42) ;
+        FEEDBACK_to_W_I_7 ; 
+                RND_5_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,43) ;
+        ADD(W_I_TEMP, W_I_7, W_I_TEMP);
+                RND_5_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,43) ;
+        GAMMA1_1(YMM_TEMP0, W_I_2) ; 
+                RND_5_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,43) ;
+        GAMMA1_2(YMM_TEMP0, W_I_2) ;
+                RND_4_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,44) ;
+        ADD(W_I, W_I_TEMP, YMM_TEMP0) ;/* now W[16..19] are completed */
+                RND_4_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,44) ;
+        FEEDBACK2_to_W_I_2 ;
+                RND_4_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,44) ;
+        GAMMA1_1(YMM_TEMP0, W_I_2) ;
+                RND_3_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,45) ;
+        GAMMA1_2(YMM_TEMP0, W_I_2) ;
+                RND_3_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,45) ;
+        ADD(W_I, W_I_TEMP, YMM_TEMP0) ; /* now W[16..21] are completed */
+                RND_3_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,45) ;
+        FEEDBACK3_to_W_I_2 ;
+                RND_2_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,46) ;
+        GAMMA1_1(YMM_TEMP0, W_I_2) ;
+                RND_2_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,46) ;
+        GAMMA1_2(YMM_TEMP0, W_I_2) ;
+                RND_2_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,46) ;
+        ADD(W_I, W_I_TEMP, YMM_TEMP0) ; /* now W[16..23] are completed */
+                RND_1_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,47) ;
+
+        MOVE_to_REG(YMM_TEMP0, K[48]) ;    
+                RND_1_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,47) ;
+        ROTATE_W(W_I_16, W_I_15, W_I_7, W_I_2, W_I) ;
+                RND_1_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,47) ;
+        ADD(YMM_TEMP0, YMM_TEMP0, W_I) ;
+        MOVE_to_MEM(W_K[48], YMM_TEMP0) ;
+        
+                /* W[i] = Gamma1(W[i-2]) + W[i-7] + Gamma0(W[i-15] + W[i-16]) */
+                RND_0_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,48) ;
+        GAMMA0_1(W_I_TEMP, W_I_15) ;
+                RND_0_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,48) ;
+        GAMMA0_2(W_I_TEMP, W_I_15) ;
+                RND_0_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,48) ;
+        ADD(W_I_TEMP, W_I_16, W_I_TEMP) ;/* for saving W_I before adding incomplete W_I_7 */
+                RND_7_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,49) ;
+        ADD(W_I, W_I_7, W_I_TEMP);
+                RND_7_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,49) ;
+        GAMMA1_1(YMM_TEMP0, W_I_2) ; 
+                RND_7_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,49) ;
+        GAMMA1_2(YMM_TEMP0, W_I_2) ;
+                RND_6_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,50) ;
+        ADD(W_I, W_I, YMM_TEMP0) ;/* now W[16..17] are completed */
+                RND_6_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,50) ;
+        FEEDBACK1_to_W_I_2 ;
+                RND_6_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,50) ;
+        FEEDBACK_to_W_I_7 ; 
+                RND_5_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,51) ;
+        ADD(W_I_TEMP, W_I_7, W_I_TEMP);
+                RND_5_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,51) ;
+        GAMMA1_1(YMM_TEMP0, W_I_2) ;
+                RND_5_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,51) ;
+        GAMMA1_2(YMM_TEMP0, W_I_2) ;
+                RND_4_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,52) ;
+        ADD(W_I, W_I_TEMP, YMM_TEMP0) ;/* now W[16..19] are completed */
+                RND_4_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,52) ;
+        FEEDBACK2_to_W_I_2 ;
+                RND_4_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,52) ;
+        GAMMA1_1(YMM_TEMP0, W_I_2) ;
+                RND_3_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,53) ;
+        GAMMA1_2(YMM_TEMP0, W_I_2) ;
+                RND_3_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,53) ;
+        ADD(W_I, W_I_TEMP, YMM_TEMP0) ; /* now W[16..21] are completed */
+                RND_3_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,53) ;
+        FEEDBACK3_to_W_I_2 ;
+                RND_2_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,54) ;
+        GAMMA1_1(YMM_TEMP0, W_I_2) ;
+                RND_2_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,54) ;
+        GAMMA1_2(YMM_TEMP0, W_I_2) ;
+                RND_2_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,54) ;
+        ADD(W_I, W_I_TEMP, YMM_TEMP0) ; /* now W[16..23] are completed */
+                RND_1_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,55) ;
+
+        MOVE_to_REG(YMM_TEMP0, K[56]) ;    
+                RND_1_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,55) ;
+        ROTATE_W(W_I_16, W_I_15, W_I_7, W_I_2, W_I) ;
+                RND_1_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,55) ;
+        ADD(YMM_TEMP0, YMM_TEMP0, W_I) ;
+        MOVE_to_MEM(W_K[56], YMM_TEMP0) ;        
+        
+        RND_0(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,56) ;
+        RND_7(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,57) ;
+        RND_6(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,58) ;
+        RND_5(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,59) ;
+
+        RND_4(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,60) ;
+        RND_3(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,61) ;
+        RND_2(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,62) ;
+        RND_1(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7,63) ;
+
+    RegToDigest(S_0,S_1,S_2,S_3,S_4,S_5,S_6,S_7) ;  
+
+    #ifdef WOLFSSL_SMALL_STACK
+        XFREE(W, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    #endif
+    
+    return 0;
+}
+
+#endif   /* HAVE_INTEL_AVX2 */
+
+#endif   /* HAVE_FIPS */
+
+#endif   /* WOLFSSL_TI_HAHS */
+
+#endif /* NO_SHA256 */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/sha512.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/sha512.c
new file mode 100644
index 0000000..8e52da9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/sha512.c
@@ -0,0 +1,1805 @@
+/* sha512.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+#include 
+
+#ifdef WOLFSSL_SHA512
+
+#ifdef HAVE_FIPS
+int wc_InitSha512(Sha512* sha)
+{
+    return InitSha512_fips(sha);
+}
+
+
+int wc_Sha512Update(Sha512* sha, const byte* data, word32 len)
+{
+    return Sha512Update_fips(sha, data, len);
+}
+
+
+int wc_Sha512Final(Sha512* sha, byte* out)
+{
+    return Sha512Final_fips(sha, out);
+}
+
+
+int wc_Sha512Hash(const byte* data, word32 len, byte* out)
+{
+    return Sha512Hash(data, len, out);
+}
+
+#if defined(WOLFSSL_SHA384) || defined(HAVE_AESGCM)
+
+int wc_InitSha384(Sha384* sha)
+{
+    return InitSha384_fips(sha);
+}
+
+
+int wc_Sha384Update(Sha384* sha, const byte* data, word32 len)
+{
+    return Sha384Update_fips(sha, data, len);
+}
+
+
+int wc_Sha384Final(Sha384* sha, byte* out)
+{
+    return Sha384Final_fips(sha, out);
+}
+
+
+int wc_Sha384Hash(const byte* data, word32 len, byte* out)
+{
+    return Sha384Hash(data, len, out);
+}
+#endif /* WOLFSSL_SHA384 */
+#else /* else build without using fips */
+#include 
+#include 
+
+#ifdef NO_INLINE
+    #include 
+#else
+    #include 
+#endif
+
+
+#ifndef WOLFSSL_HAVE_MIN
+#define WOLFSSL_HAVE_MIN
+
+    static INLINE word32 min(word32 a, word32 b)
+    {
+        return a > b ? b : a;
+    }
+
+#endif /* WOLFSSL_HAVE_MIN */
+
+#if defined(USE_INTEL_SPEEDUP)
+  #define HAVE_INTEL_AVX1
+  #define HAVE_INTEL_AVX2
+#endif
+
+#if defined(HAVE_INTEL_AVX1)
+/* #define DEBUG_XMM  */
+#endif
+
+#if defined(HAVE_INTEL_AVX2)
+#define HAVE_INTEL_RORX
+/* #define DEBUG_YMM  */
+#endif
+
+/*****
+Intel AVX1/AVX2 Macro Control Structure
+
+#if defined(HAVE_INteL_SPEEDUP)
+    #define HAVE_INTEL_AVX1
+    #define HAVE_INTEL_AVX2
+#endif
+
+int InitSha512(Sha512* sha512) { 
+     Save/Recover XMM, YMM
+     ...
+
+     Check Intel AVX cpuid flags
+}
+
+#if defined(HAVE_INTEL_AVX1)|| defined(HAVE_INTEL_AVX2)
+  Transform_AVX1() ; # Function prototype 
+  Transform_AVX2() ; #
+#endif
+
+  _Transform() {     # Native Transform Function body
+  
+  }
+  
+  int Sha512Update() { 
+     Save/Recover XMM, YMM
+     ...
+  }
+  
+  int Sha512Final() { 
+     Save/Recover XMM, YMM
+     ...
+  }
+
+
+#if defined(HAVE_INTEL_AVX1)
+   
+   XMM Instructions/inline asm Definitions
+
+#endif
+
+#if defined(HAVE_INTEL_AVX2)
+
+   YMM Instructions/inline asm Definitions
+
+#endif
+
+#if defnied(HAVE_INTEL_AVX1)
+  
+  int Transform_AVX1() {
+      Stitched Message Sched/Round
+  }
+
+#endif
+
+#if defnied(HAVE_INTEL_AVX2)
+  
+  int Transform_AVX2() {
+      Stitched Message Sched/Round
+  }
+#endif
+
+
+*/
+
+#if defined(HAVE_INTEL_AVX1) || defined(HAVE_INTEL_AVX2)
+
+
+/* Each platform needs to query info type 1 from cpuid to see if aesni is
+ * supported. Also, let's setup a macro for proper linkage w/o ABI conflicts
+ */
+
+#ifndef _MSC_VER
+    #define cpuid(reg, leaf, sub)\
+            __asm__ __volatile__ ("cpuid":\
+             "=a" (reg[0]), "=b" (reg[1]), "=c" (reg[2]), "=d" (reg[3]) :\
+             "a" (leaf), "c"(sub));
+
+    #define XASM_LINK(f) asm(f)
+#else
+
+    #include 
+    #define cpuid(a,b) __cpuid((int*)a,b)
+
+    #define XASM_LINK(f)
+
+#endif /* _MSC_VER */
+
+#define EAX 0
+#define EBX 1
+#define ECX 2 
+#define EDX 3
+    
+#define CPUID_AVX1   0x1
+#define CPUID_AVX2   0x2
+#define CPUID_RDRAND 0x4
+#define CPUID_RDSEED 0x8
+#define CPUID_BMI2   0x10   /* MULX, RORX */
+
+#define IS_INTEL_AVX1       (cpuid_flags&CPUID_AVX1)
+#define IS_INTEL_AVX2       (cpuid_flags&CPUID_AVX2)
+#define IS_INTEL_BMI2       (cpuid_flags&CPUID_BMI2)
+#define IS_INTEL_RDRAND     (cpuid_flags&CPUID_RDRAND)
+#define IS_INTEL_RDSEED     (cpuid_flags&CPUID_RDSEED)
+
+static word32 cpuid_check = 0 ;
+static word32 cpuid_flags = 0 ;
+
+static word32 cpuid_flag(word32 leaf, word32 sub, word32 num, word32 bit) {
+    int got_intel_cpu=0;
+    unsigned int reg[5]; 
+    
+    reg[4] = '\0' ;
+    cpuid(reg, 0, 0);  
+    if(memcmp((char *)&(reg[EBX]), "Genu", 4) == 0 &&  
+                memcmp((char *)&(reg[EDX]), "ineI", 4) == 0 &&  
+                memcmp((char *)&(reg[ECX]), "ntel", 4) == 0) {  
+        got_intel_cpu = 1;  
+    }    
+    if (got_intel_cpu) {
+        cpuid(reg, leaf, sub);
+        return((reg[num]>>bit)&0x1) ;
+    }
+    return 0 ;
+}
+
+#define CHECK_SHA512 0x1
+#define CHECK_SHA384 0x2
+
+static int set_cpuid_flags(int sha) {  
+    if((cpuid_check & sha) ==0) {
+        if(cpuid_flag(1, 0, ECX, 28)){ cpuid_flags |= CPUID_AVX1 ;}
+        if(cpuid_flag(7, 0, EBX, 5)){  cpuid_flags |= CPUID_AVX2 ; }
+        if(cpuid_flag(7, 0, EBX, 8)) { cpuid_flags |= CPUID_BMI2 ; }
+        if(cpuid_flag(1, 0, ECX, 30)){ cpuid_flags |= CPUID_RDRAND ;  } 
+        if(cpuid_flag(7, 0, EBX, 18)){ cpuid_flags |= CPUID_RDSEED ;  }
+		cpuid_check |= sha ;
+		return 0 ;
+    }
+    return 1 ;
+}
+
+
+/* #if defined(HAVE_INTEL_AVX1/2) at the tail of sha512 */
+
+#if defined(HAVE_INTEL_AVX1)
+static int Transform_AVX1(Sha512 *sha512) ;
+#endif
+
+#if defined(HAVE_INTEL_AVX2)
+static int Transform_AVX2(Sha512 *sha512) ; 
+
+#if defined(HAVE_INTEL_AVX1) && defined(HAVE_INTEL_AVX2) && defined(HAVE_INTEL_RORX)
+static int Transform_AVX1_RORX(Sha512 *sha512) ;
+#endif
+
+#endif
+
+static int _Transform(Sha512 *sha512) ; 
+    
+static int (*Transform_p)(Sha512* sha512) = _Transform ;
+
+#define Transform(sha512) (*Transform_p)(sha512)
+
+static void set_Transform(void) {
+     if(set_cpuid_flags(CHECK_SHA512)) return ;
+
+#if defined(HAVE_INTEL_AVX2)
+     if(IS_INTEL_AVX2 && IS_INTEL_BMI2){ 
+         Transform_p = Transform_AVX1_RORX; return ; 
+         Transform_p = Transform_AVX2      ; 
+                  /* for avoiding warning,"not used" */
+     }
+#endif
+#if defined(HAVE_INTEL_AVX1)
+     Transform_p = ((IS_INTEL_AVX1) ? Transform_AVX1 : _Transform) ; return ;
+#endif
+     Transform_p = _Transform ; return ;
+}
+
+#else
+   #define Transform(sha512) _Transform(sha512)
+#endif
+
+/* Dummy for saving MM_REGs on behalf of Transform */
+/* #if defined(HAVE_INTEL_AVX2)
+ #define  SAVE_XMM_YMM   __asm__ volatile("orq %%r8, %%r8":::\
+   "%ymm0","%ymm1","%ymm2","%ymm3","%ymm4","%ymm5","%ymm6","%ymm7","%ymm8","%ymm9","%ymm10","%ymm11",\
+   "%ymm12","%ymm13","%ymm14","%ymm15")
+*/
+#if defined(HAVE_INTEL_AVX1)
+   #define  SAVE_XMM_YMM   __asm__ volatile("orq %%r8, %%r8":::\
+    "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7","xmm8","xmm9","xmm10","xmm11","xmm12","xmm13","xmm14","xmm15")
+#else
+#define  SAVE_XMM_YMM
+#endif
+
+#if defined(HAVE_INTEL_AVX1)|| defined(HAVE_INTEL_AVX2)
+
+#include 
+
+#endif /* defined(HAVE_INTEL_AVX1)|| defined(HAVE_INTEL_AVX2) */
+
+
+#if defined(HAVE_INTEL_RORX)
+#define ROTR(func, bits, x) \
+word64 func(word64 x) {  word64 ret ;\
+    __asm__ ("rorx $"#bits", %1, %0\n\t":"=r"(ret):"r"(x):) ;\
+    return ret ;\
+}
+
+static INLINE ROTR(rotrFixed64_28, 28, x)
+static INLINE ROTR(rotrFixed64_34, 34, x)
+static INLINE ROTR(rotrFixed64_39, 39, x)
+static INLINE ROTR(rotrFixed64_14, 14, x)
+static INLINE ROTR(rotrFixed64_18, 18, x)
+static INLINE ROTR(rotrFixed64_41, 41, x)
+
+#define S0_RORX(x) (rotrFixed64_28(x)^rotrFixed64_34(x)^rotrFixed64_39(x))
+#define S1_RORX(x) (rotrFixed64_14(x)^rotrFixed64_18(x)^rotrFixed64_41(x))
+#endif
+
+#if defined(HAVE_BYTEREVERSE64) && !defined(HAVE_INTEL_AVX1) && !defined(HAVE_INTEL_AVX2)
+#define ByteReverseWords64(out, in, size) ByteReverseWords64_1(out, size)
+#define ByteReverseWords64_1(buf, size)\
+ { unsigned int i ;\
+   for(i=0; i< size/sizeof(word64); i++){\
+       __asm__ volatile("bswapq %0":"+r"(buf[i])::) ;\
+   }\
+}
+#endif
+
+
+int wc_InitSha512(Sha512* sha512)
+{
+    sha512->digest[0] = W64LIT(0x6a09e667f3bcc908);
+    sha512->digest[1] = W64LIT(0xbb67ae8584caa73b);
+    sha512->digest[2] = W64LIT(0x3c6ef372fe94f82b);
+    sha512->digest[3] = W64LIT(0xa54ff53a5f1d36f1);
+    sha512->digest[4] = W64LIT(0x510e527fade682d1);
+    sha512->digest[5] = W64LIT(0x9b05688c2b3e6c1f);
+    sha512->digest[6] = W64LIT(0x1f83d9abfb41bd6b);
+    sha512->digest[7] = W64LIT(0x5be0cd19137e2179);
+
+    sha512->buffLen = 0;
+    sha512->loLen   = 0;
+    sha512->hiLen   = 0;
+    
+#if defined(HAVE_INTEL_AVX1)|| defined(HAVE_INTEL_AVX2)
+    set_Transform() ; /* choose best Transform function under this runtime environment */
+#endif
+    
+    return 0 ;
+}
+
+
+static const word64 K512[80] = {
+	W64LIT(0x428a2f98d728ae22), W64LIT(0x7137449123ef65cd),
+	W64LIT(0xb5c0fbcfec4d3b2f), W64LIT(0xe9b5dba58189dbbc),
+	W64LIT(0x3956c25bf348b538), W64LIT(0x59f111f1b605d019),
+	W64LIT(0x923f82a4af194f9b), W64LIT(0xab1c5ed5da6d8118),
+	W64LIT(0xd807aa98a3030242), W64LIT(0x12835b0145706fbe),
+	W64LIT(0x243185be4ee4b28c), W64LIT(0x550c7dc3d5ffb4e2),
+	W64LIT(0x72be5d74f27b896f), W64LIT(0x80deb1fe3b1696b1),
+	W64LIT(0x9bdc06a725c71235), W64LIT(0xc19bf174cf692694),
+	W64LIT(0xe49b69c19ef14ad2), W64LIT(0xefbe4786384f25e3),
+	W64LIT(0x0fc19dc68b8cd5b5), W64LIT(0x240ca1cc77ac9c65),
+	W64LIT(0x2de92c6f592b0275), W64LIT(0x4a7484aa6ea6e483),
+	W64LIT(0x5cb0a9dcbd41fbd4), W64LIT(0x76f988da831153b5),
+	W64LIT(0x983e5152ee66dfab), W64LIT(0xa831c66d2db43210),
+	W64LIT(0xb00327c898fb213f), W64LIT(0xbf597fc7beef0ee4),
+	W64LIT(0xc6e00bf33da88fc2), W64LIT(0xd5a79147930aa725),
+	W64LIT(0x06ca6351e003826f), W64LIT(0x142929670a0e6e70),
+	W64LIT(0x27b70a8546d22ffc), W64LIT(0x2e1b21385c26c926),
+	W64LIT(0x4d2c6dfc5ac42aed), W64LIT(0x53380d139d95b3df),
+	W64LIT(0x650a73548baf63de), W64LIT(0x766a0abb3c77b2a8),
+	W64LIT(0x81c2c92e47edaee6), W64LIT(0x92722c851482353b),
+	W64LIT(0xa2bfe8a14cf10364), W64LIT(0xa81a664bbc423001),
+	W64LIT(0xc24b8b70d0f89791), W64LIT(0xc76c51a30654be30),
+	W64LIT(0xd192e819d6ef5218), W64LIT(0xd69906245565a910),
+	W64LIT(0xf40e35855771202a), W64LIT(0x106aa07032bbd1b8),
+	W64LIT(0x19a4c116b8d2d0c8), W64LIT(0x1e376c085141ab53),
+	W64LIT(0x2748774cdf8eeb99), W64LIT(0x34b0bcb5e19b48a8),
+	W64LIT(0x391c0cb3c5c95a63), W64LIT(0x4ed8aa4ae3418acb),
+	W64LIT(0x5b9cca4f7763e373), W64LIT(0x682e6ff3d6b2b8a3),
+	W64LIT(0x748f82ee5defb2fc), W64LIT(0x78a5636f43172f60),
+	W64LIT(0x84c87814a1f0ab72), W64LIT(0x8cc702081a6439ec),
+	W64LIT(0x90befffa23631e28), W64LIT(0xa4506cebde82bde9),
+	W64LIT(0xbef9a3f7b2c67915), W64LIT(0xc67178f2e372532b),
+	W64LIT(0xca273eceea26619c), W64LIT(0xd186b8c721c0c207),
+	W64LIT(0xeada7dd6cde0eb1e), W64LIT(0xf57d4f7fee6ed178),
+	W64LIT(0x06f067aa72176fba), W64LIT(0x0a637dc5a2c898a6),
+	W64LIT(0x113f9804bef90dae), W64LIT(0x1b710b35131c471b),
+	W64LIT(0x28db77f523047d84), W64LIT(0x32caab7b40c72493),
+	W64LIT(0x3c9ebe0a15c9bebc), W64LIT(0x431d67c49c100d4c),
+	W64LIT(0x4cc5d4becb3e42b6), W64LIT(0x597f299cfc657e2a),
+	W64LIT(0x5fcb6fab3ad6faec), W64LIT(0x6c44198c4a475817)
+};
+
+
+
+#define blk0(i) (W[i] = sha512->buffer[i])
+
+#define blk2(i) (W[i&15]+=s1(W[(i-2)&15])+W[(i-7)&15]+s0(W[(i-15)&15]))
+
+#define Ch(x,y,z) (z^(x&(y^z)))
+#define Maj(x,y,z) ((x&y)|(z&(x|y)))
+
+#define a(i) T[(0-i)&7]
+#define b(i) T[(1-i)&7]
+#define c(i) T[(2-i)&7]
+#define d(i) T[(3-i)&7]
+#define e(i) T[(4-i)&7]
+#define f(i) T[(5-i)&7]
+#define g(i) T[(6-i)&7]
+#define h(i) T[(7-i)&7]
+
+#define S0(x) (rotrFixed64(x,28)^rotrFixed64(x,34)^rotrFixed64(x,39))
+#define S1(x) (rotrFixed64(x,14)^rotrFixed64(x,18)^rotrFixed64(x,41))
+#define s0(x) (rotrFixed64(x,1)^rotrFixed64(x,8)^(x>>7))
+#define s1(x) (rotrFixed64(x,19)^rotrFixed64(x,61)^(x>>6))
+
+#define R(i) h(i)+=S1(e(i))+Ch(e(i),f(i),g(i))+K[i+j]+(j?blk2(i):blk0(i));\
+    d(i)+=h(i);h(i)+=S0(a(i))+Maj(a(i),b(i),c(i))
+
+#define blk384(i) (W[i] = sha384->buffer[i])
+
+#define R2(i) h(i)+=S1(e(i))+Ch(e(i),f(i),g(i))+K[i+j]+(j?blk2(i):blk384(i));\
+    d(i)+=h(i);h(i)+=S0(a(i))+Maj(a(i),b(i),c(i))
+
+static int _Transform(Sha512* sha512)
+{
+    const word64* K = K512;
+
+    word32 j;
+    word64 T[8];
+
+
+#ifdef WOLFSSL_SMALL_STACK
+    word64* W;
+    W = (word64*) XMALLOC(sizeof(word64) * 16, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (W == NULL)
+        return MEMORY_E;
+#else
+    word64 W[16];
+#endif
+
+    /* Copy digest to working vars */
+    XMEMCPY(T, sha512->digest, sizeof(T));
+
+#ifdef USE_SLOW_SHA2
+    /* over twice as small, but 50% slower */
+    /* 80 operations, not unrolled */
+    for (j = 0; j < 80; j += 16) {
+        int m; 
+        for (m = 0; m < 16; m++) { /* braces needed here for macros {} */
+            R(m);
+        }
+    }
+#else
+    /* 80 operations, partially loop unrolled */
+    for (j = 0; j < 80; j += 16) {
+        R( 0); R( 1); R( 2); R( 3);
+        R( 4); R( 5); R( 6); R( 7);
+        R( 8); R( 9); R(10); R(11);
+        R(12); R(13); R(14); R(15);
+    }
+#endif /* USE_SLOW_SHA2 */
+
+    /* Add the working vars back into digest */
+
+    sha512->digest[0] += a(0);
+    sha512->digest[1] += b(0);
+    sha512->digest[2] += c(0);
+    sha512->digest[3] += d(0);
+    sha512->digest[4] += e(0);
+    sha512->digest[5] += f(0);
+    sha512->digest[6] += g(0);
+    sha512->digest[7] += h(0);
+
+    /* Wipe variables */
+    ForceZero(W, sizeof(word64) * 16);
+    ForceZero(T, sizeof(T));
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(W, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return 0;
+}
+
+
+static INLINE void AddLength(Sha512* sha512, word32 len)
+{
+    word32 tmp = sha512->loLen;
+    if ( (sha512->loLen += len) < tmp)
+        sha512->hiLen++;                       /* carry low to high */
+}
+
+int wc_Sha512Update(Sha512* sha512, const byte* data, word32 len)
+{
+    /* do block size increments */
+    byte* local = (byte*)sha512->buffer;
+    SAVE_XMM_YMM ; /* for Intel AVX */
+
+    while (len) {
+        word32 add = min(len, SHA512_BLOCK_SIZE - sha512->buffLen);
+        XMEMCPY(&local[sha512->buffLen], data, add);
+
+        sha512->buffLen += add;
+        data         += add;
+        len          -= add;
+
+        if (sha512->buffLen == SHA512_BLOCK_SIZE) {
+            int ret;
+            #if defined(LITTLE_ENDIAN_ORDER)
+                #if defined(HAVE_INTEL_AVX1) || defined(HAVE_INTEL_AVX2)
+                if(!IS_INTEL_AVX1 && !IS_INTEL_AVX2) 
+                #endif
+                    ByteReverseWords64(sha512->buffer, sha512->buffer,
+                                   SHA512_BLOCK_SIZE);
+            #endif
+            ret = Transform(sha512);
+            if (ret != 0)
+                return ret;
+
+            AddLength(sha512, SHA512_BLOCK_SIZE);
+            sha512->buffLen = 0;
+        }
+    }
+    return 0;
+}
+
+
+int wc_Sha512Final(Sha512* sha512, byte* hash)
+{
+    byte* local = (byte*)sha512->buffer;
+    int ret;
+
+    SAVE_XMM_YMM ; /* for Intel AVX */
+    AddLength(sha512, sha512->buffLen);               /* before adding pads */
+
+    local[sha512->buffLen++] = 0x80;  /* add 1 */
+
+    /* pad with zeros */
+    if (sha512->buffLen > SHA512_PAD_SIZE) {
+        XMEMSET(&local[sha512->buffLen], 0, SHA512_BLOCK_SIZE -sha512->buffLen);
+        sha512->buffLen += SHA512_BLOCK_SIZE - sha512->buffLen;
+        #if defined(LITTLE_ENDIAN_ORDER) 
+            #if defined(HAVE_INTEL_AVX1) || defined(HAVE_INTEL_AVX2)
+            if(!IS_INTEL_AVX1 && !IS_INTEL_AVX2)
+            #endif
+            ByteReverseWords64(sha512->buffer,sha512->buffer,SHA512_BLOCK_SIZE);
+        #endif
+        ret = Transform(sha512);
+        if (ret != 0)
+            return ret;
+
+        sha512->buffLen = 0;
+    }
+    XMEMSET(&local[sha512->buffLen], 0, SHA512_PAD_SIZE - sha512->buffLen);
+   
+    /* put lengths in bits */
+    sha512->hiLen = (sha512->loLen >> (8*sizeof(sha512->loLen) - 3)) + 
+                 (sha512->hiLen << 3);
+    sha512->loLen = sha512->loLen << 3;
+
+    /* store lengths */
+    #if defined(LITTLE_ENDIAN_ORDER)
+        #if defined(HAVE_INTEL_AVX1) || defined(HAVE_INTEL_AVX2)
+        if(!IS_INTEL_AVX1 && !IS_INTEL_AVX2)
+        #endif
+        ByteReverseWords64(sha512->buffer, sha512->buffer, SHA512_PAD_SIZE);
+    #endif
+    /* ! length ordering dependent on digest endian type ! */
+
+    sha512->buffer[SHA512_BLOCK_SIZE / sizeof(word64) - 2] = sha512->hiLen;
+    sha512->buffer[SHA512_BLOCK_SIZE / sizeof(word64) - 1] = sha512->loLen;
+    #if defined(HAVE_INTEL_AVX1) || defined(HAVE_INTEL_AVX2)
+    if(IS_INTEL_AVX1 || IS_INTEL_AVX2)
+        ByteReverseWords64(&(sha512->buffer[SHA512_BLOCK_SIZE / sizeof(word64) - 2]),
+                           &(sha512->buffer[SHA512_BLOCK_SIZE / sizeof(word64) - 2]),
+                           SHA512_BLOCK_SIZE - SHA512_PAD_SIZE);
+    #endif
+    ret = Transform(sha512);
+    if (ret != 0)
+        return ret;
+
+    #ifdef LITTLE_ENDIAN_ORDER
+        ByteReverseWords64(sha512->digest, sha512->digest, SHA512_DIGEST_SIZE);
+    #endif
+    XMEMCPY(hash, sha512->digest, SHA512_DIGEST_SIZE);
+
+    return wc_InitSha512(sha512);  /* reset state */
+}
+
+
+int wc_Sha512Hash(const byte* data, word32 len, byte* hash)
+{
+    int ret = 0;
+#ifdef WOLFSSL_SMALL_STACK
+    Sha512* sha512;
+#else
+    Sha512 sha512[1];
+#endif
+
+#ifdef WOLFSSL_SMALL_STACK
+    sha512 = (Sha512*)XMALLOC(sizeof(Sha512), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (sha512 == NULL)
+        return MEMORY_E;
+#endif
+    
+    if ((ret = wc_InitSha512(sha512)) != 0) {
+        WOLFSSL_MSG("InitSha512 failed");
+    }
+    else if ((ret = wc_Sha512Update(sha512, data, len)) != 0) {
+        WOLFSSL_MSG("Sha512Update failed");
+    }
+    else if ((ret = wc_Sha512Final(sha512, hash)) != 0) {
+        WOLFSSL_MSG("Sha512Final failed");
+    }
+    
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(sha512, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+    
+    return ret;
+}
+
+#if defined(HAVE_INTEL_AVX1)
+
+#define Rx_1(i) h(i)+=S1(e(i))+Ch(e(i),f(i),g(i))+K[i+j] + W_X[i] ;
+#define Rx_2(i) d(i)+=h(i);
+#define Rx_3(i) h(i)+=S0(a(i))+Maj(a(i),b(i),c(i));
+
+#if defined(HAVE_INTEL_RORX)
+#define Rx_RORX_1(i) h(i)+=S1_RORX(e(i))+Ch(e(i),f(i),g(i))+K[i+j] + W_X[i] ;
+#define Rx_RORX_2(i) d(i)+=h(i);
+#define Rx_RORX_3(i) h(i)+=S0_RORX(a(i))+Maj(a(i),b(i),c(i));
+#endif
+
+#endif
+
+#if defined(HAVE_INTEL_AVX2) 
+#define Ry_1(i, w) h(i)+=S1(e(i))+Ch(e(i),f(i),g(i))+K[i+j] + w ; 
+#define Ry_2(i, w) d(i)+=h(i);
+#define Ry_3(i, w) h(i)+=S0(a(i))+Maj(a(i),b(i),c(i));
+#endif
+
+#if defined(HAVE_INTEL_AVX1) /* inline Assember for Intel AVX1 instructions */
+#if defined(DEBUG_XMM)
+
+#define SAVE_REG(i)     __asm__ volatile("vmovdqu %%xmm"#i", %0 \n\t":"=m"(reg[i][0])::XMM_REGs);
+#define RECV_REG(i)     __asm__ volatile("vmovdqu %0, %%xmm"#i" \n\t"::"m"(reg[i][0]):XMM_REGs);
+
+#define _DUMP_REG(REG, name)\
+    { word64 buf[16] ;word64 reg[16][2];int k ;\
+      SAVE_REG(0); SAVE_REG(1); SAVE_REG(2);  SAVE_REG(3);  SAVE_REG(4);  \
+      SAVE_REG(5);   SAVE_REG(6); SAVE_REG(7);SAVE_REG(8); SAVE_REG(9); SAVE_REG(10);\
+       SAVE_REG(11); SAVE_REG(12); SAVE_REG(13); SAVE_REG(14); SAVE_REG(15); \
+      __asm__ volatile("vmovdqu %%"#REG", %0 \n\t":"=m"(buf[0])::XMM_REGs);\
+      printf(" "#name":\t") ; for(k=0; k<2; k++) printf("%016lx.", (word64)(buf[k])); printf("\n") ; \
+      RECV_REG(0); RECV_REG(1); RECV_REG(2);  RECV_REG(3);  RECV_REG(4);\
+      RECV_REG(5);   RECV_REG(6); RECV_REG(7); RECV_REG(8); RECV_REG(9);\
+      RECV_REG(10); RECV_REG(11); RECV_REG(12); RECV_REG(13); RECV_REG(14); RECV_REG(15);\
+    }
+
+#define DUMP_REG(REG) _DUMP_REG(REG, #REG) 
+#define PRINTF(fmt, ...) 
+
+#else
+
+#define DUMP_REG(REG) 
+#define PRINTF(fmt, ...) 
+
+#endif
+
+#define _MOVE_to_REG(xymm, mem)       __asm__ volatile("vmovdqu %0, %%"#xymm" "\
+        :: "m"(mem):XMM_REGs) ;
+#define _MOVE_to_MEM(mem,i, xymm)     __asm__ volatile("vmovdqu %%"#xymm", %0" :\
+         "=m"(mem[i]),"=m"(mem[i+1]),"=m"(mem[i+2]),"=m"(mem[i+3])::XMM_REGs) ;
+#define _MOVE(dest, src)              __asm__ volatile("vmovdqu %%"#src",  %%"\
+        #dest" ":::XMM_REGs) ;
+
+#define _S_TEMP(dest, src, bits, temp)  __asm__ volatile("vpsrlq  $"#bits", %%"\
+        #src", %%"#dest"\n\tvpsllq  $64-"#bits", %%"#src", %%"#temp"\n\tvpor %%"\
+        #temp",%%"#dest", %%"#dest" ":::XMM_REGs) ;
+#define _AVX1_R(dest, src, bits)      __asm__ volatile("vpsrlq  $"#bits", %%"\
+        #src", %%"#dest" ":::XMM_REGs) ;
+#define _XOR(dest, src1, src2)        __asm__ volatile("vpxor   %%"#src1", %%"\
+        #src2", %%"#dest" ":::XMM_REGs) ;
+#define _OR(dest, src1, src2)         __asm__ volatile("vpor    %%"#src1", %%"\
+        #src2", %%"#dest" ":::XMM_REGs) ;
+#define _ADD(dest, src1, src2)        __asm__ volatile("vpaddq   %%"#src1", %%"\
+        #src2", %%"#dest" ":::XMM_REGs) ;
+#define _ADD_MEM(dest, src1, mem)     __asm__ volatile("vpaddq   %0, %%"#src1", %%"\
+        #dest" "::"m"(mem):XMM_REGs) ;
+
+#define MOVE_to_REG(xymm, mem)      _MOVE_to_REG(xymm, mem)
+#define MOVE_to_MEM(mem, i, xymm)   _MOVE_to_MEM(mem, i, xymm)
+#define MOVE(dest, src)             _MOVE(dest, src)  
+
+#define XOR(dest, src1, src2)      _XOR(dest, src1, src2)
+#define OR(dest, src1, src2)       _OR(dest, src1, src2)
+#define ADD(dest, src1, src2)      _ADD(dest, src1, src2)
+
+#define S_TMP(dest, src, bits, temp) _S_TEMP(dest, src, bits, temp);
+#define AVX1_S(dest, src, bits)      S_TMP(dest, src, bits, S_TEMP)
+#define AVX1_R(dest, src, bits)      _AVX1_R(dest, src, bits)
+
+#define Init_Mask(mask) \
+     __asm__ volatile("vmovdqu %0, %%xmm1\n\t"::"m"(mask):"%xmm1") ;
+     
+#define _W_from_buff1(w, buff, xmm) \
+    /* X0..3(xmm4..7), W[0..15] = sha512->buffer[0.15];  */\
+     __asm__ volatile("vmovdqu %1, %%"#xmm"\n\t"\
+                      "vpshufb %%xmm1, %%"#xmm", %%"#xmm"\n\t"\
+                      "vmovdqu %%"#xmm", %0"\
+                      :"=m"(w): "m"(buff):"%xmm0") ;
+
+#define W_from_buff1(w, buff, xmm) _W_from_buff1(w, buff, xmm) 
+
+#define W_from_buff(w, buff)\
+     Init_Mask(mBYTE_FLIP_MASK[0]) ;\
+     W_from_buff1(w[0], buff[0], W_0);\
+     W_from_buff1(w[2], buff[2], W_2);\
+     W_from_buff1(w[4], buff[4], W_4);\
+     W_from_buff1(w[6], buff[6], W_6);\
+     W_from_buff1(w[8], buff[8], W_8);\
+     W_from_buff1(w[10],buff[10],W_10);\
+     W_from_buff1(w[12],buff[12],W_12);\
+     W_from_buff1(w[14],buff[14],W_14);
+                          
+static word64 mBYTE_FLIP_MASK[] =  { 0x0001020304050607, 0x08090a0b0c0d0e0f } ;
+
+#define W_I_15  xmm14
+#define W_I_7   xmm11
+#define W_I_2   xmm13
+#define W_I     xmm12
+#define G_TEMP  xmm0
+#define S_TEMP  xmm1
+#define XMM_TEMP0  xmm2
+
+#define W_0     xmm12
+#define W_2     xmm3
+#define W_4     xmm4
+#define W_6     xmm5
+#define W_8     xmm6
+#define W_10    xmm7
+#define W_12    xmm8
+#define W_14    xmm9
+
+#define XMM_REGs
+
+#define s0_1(dest, src)      AVX1_S(dest, src, 1); 
+#define s0_2(dest, src)      AVX1_S(G_TEMP, src, 8); XOR(dest, G_TEMP, dest) ; 
+#define s0_3(dest, src)      AVX1_R(G_TEMP, src, 7);  XOR(dest, G_TEMP, dest) ;
+
+#define s1_1(dest, src)      AVX1_S(dest, src, 19);
+#define s1_2(dest, src)      AVX1_S(G_TEMP, src, 61); XOR(dest, G_TEMP, dest) ; 
+#define s1_3(dest, src)      AVX1_R(G_TEMP, src, 6); XOR(dest, G_TEMP, dest) ;
+
+#define s0_(dest, src)       s0_1(dest, src) ; s0_2(dest, src) ; s0_3(dest, src)
+#define s1_(dest, src)       s1_1(dest, src) ; s1_2(dest, src) ; s1_3(dest, src)
+        
+#define Block_xx_1(i) \
+    MOVE_to_REG(W_I_15, W_X[(i-15)&15]) ;\
+    MOVE_to_REG(W_I_7,  W_X[(i- 7)&15]) ;\
+        
+#define Block_xx_2(i) \
+    MOVE_to_REG(W_I_2,  W_X[(i- 2)&15]) ;\
+    MOVE_to_REG(W_I,    W_X[(i)]) ;\
+        
+#define Block_xx_3(i) \
+    s0_ (XMM_TEMP0, W_I_15) ;\
+        
+#define Block_xx_4(i) \
+    ADD(W_I, W_I, XMM_TEMP0) ;\
+    ADD(W_I, W_I, W_I_7) ;\
+        
+#define Block_xx_5(i) \
+    s1_ (XMM_TEMP0, W_I_2) ;\
+    
+#define Block_xx_6(i) \
+    ADD(W_I, W_I, XMM_TEMP0) ;\
+    MOVE_to_MEM(W_X,i, W_I) ;\
+    if(i==0)\
+        MOVE_to_MEM(W_X,16, W_I) ;\
+
+#define Block_xx_7(i) \
+    MOVE_to_REG(W_I_15, W_X[(i-15)&15]) ;\
+    MOVE_to_REG(W_I_7,  W_X[(i- 7)&15]) ;\
+            
+#define Block_xx_8(i) \
+    MOVE_to_REG(W_I_2,  W_X[(i- 2)&15]) ;\
+    MOVE_to_REG(W_I,    W_X[(i)]) ;\
+
+#define Block_xx_9(i) \
+    s0_ (XMM_TEMP0, W_I_15) ;\
+
+#define Block_xx_10(i) \
+    ADD(W_I, W_I, XMM_TEMP0) ;\
+    ADD(W_I, W_I, W_I_7) ;\
+
+#define Block_xx_11(i) \
+    s1_ (XMM_TEMP0, W_I_2) ;\
+
+#define Block_xx_12(i) \
+    ADD(W_I, W_I, XMM_TEMP0) ;\
+    MOVE_to_MEM(W_X,i, W_I) ;\
+    if((i)==0)\
+        MOVE_to_MEM(W_X,16, W_I) ;\
+
+static inline void Block_0_1(word64 *W_X) { Block_xx_1(0) ; }
+static inline void Block_0_2(word64 *W_X) { Block_xx_2(0) ; }
+static inline void Block_0_3(void) { Block_xx_3(0) ; }
+static inline void Block_0_4(void) { Block_xx_4(0) ; }
+static inline void Block_0_5(void) { Block_xx_5(0) ; }
+static inline void Block_0_6(word64 *W_X) { Block_xx_6(0) ; }
+static inline void Block_0_7(word64 *W_X) { Block_xx_7(2) ; }
+static inline void Block_0_8(word64 *W_X) { Block_xx_8(2) ; }
+static inline void Block_0_9(void) { Block_xx_9(2) ; }
+static inline void Block_0_10(void){ Block_xx_10(2) ; }
+static inline void Block_0_11(void){ Block_xx_11(2) ; }
+static inline void Block_0_12(word64 *W_X){ Block_xx_12(2) ; }
+
+static inline void Block_4_1(word64 *W_X) { Block_xx_1(4) ; }
+static inline void Block_4_2(word64 *W_X) { Block_xx_2(4) ; }
+static inline void Block_4_3(void) { Block_xx_3(4) ; }
+static inline void Block_4_4(void) { Block_xx_4(4) ; }
+static inline void Block_4_5(void) { Block_xx_5(4) ; }
+static inline void Block_4_6(word64 *W_X) { Block_xx_6(4) ; }
+static inline void Block_4_7(word64 *W_X) { Block_xx_7(6) ; }
+static inline void Block_4_8(word64 *W_X) { Block_xx_8(6) ; }
+static inline void Block_4_9(void) { Block_xx_9(6) ; }
+static inline void Block_4_10(void){ Block_xx_10(6) ; }
+static inline void Block_4_11(void){ Block_xx_11(6) ; }
+static inline void Block_4_12(word64 *W_X){ Block_xx_12(6) ; }
+
+static inline void Block_8_1(word64 *W_X) { Block_xx_1(8) ; }
+static inline void Block_8_2(word64 *W_X) { Block_xx_2(8) ; }
+static inline void Block_8_3(void) { Block_xx_3(8) ; }
+static inline void Block_8_4(void) { Block_xx_4(8) ; }
+static inline void Block_8_5(void) { Block_xx_5(8) ; }
+static inline void Block_8_6(word64 *W_X) { Block_xx_6(8) ; }
+static inline void Block_8_7(word64 *W_X) { Block_xx_7(10) ; }
+static inline void Block_8_8(word64 *W_X) { Block_xx_8(10) ; }
+static inline void Block_8_9(void) { Block_xx_9(10) ; }
+static inline void Block_8_10(void){ Block_xx_10(10) ; }
+static inline void Block_8_11(void){ Block_xx_11(10) ; }
+static inline void Block_8_12(word64 *W_X){ Block_xx_12(10) ; }
+
+static inline void Block_12_1(word64 *W_X) { Block_xx_1(12) ; }
+static inline void Block_12_2(word64 *W_X) { Block_xx_2(12) ; }
+static inline void Block_12_3(void) { Block_xx_3(12) ; }
+static inline void Block_12_4(void) { Block_xx_4(12) ; }
+static inline void Block_12_5(void) { Block_xx_5(12) ; }
+static inline void Block_12_6(word64 *W_X) { Block_xx_6(12) ; }
+static inline void Block_12_7(word64 *W_X) { Block_xx_7(14) ; }
+static inline void Block_12_8(word64 *W_X) { Block_xx_8(14) ; }
+static inline void Block_12_9(void) { Block_xx_9(14) ; }
+static inline void Block_12_10(void){ Block_xx_10(14) ; }
+static inline void Block_12_11(void){ Block_xx_11(14) ; }
+static inline void Block_12_12(word64 *W_X){ Block_xx_12(14) ; }
+
+#endif
+
+#if defined(HAVE_INTEL_AVX2)
+static const unsigned long mBYTE_FLIP_MASK_Y[] =
+   { 0x0001020304050607, 0x08090a0b0c0d0e0f, 0x0001020304050607, 0x08090a0b0c0d0e0f } ;
+
+#define W_from_buff_Y(buff)\
+    { /* X0..3(ymm9..12), W_X[0..15] = sha512->buffer[0.15];  */\
+     __asm__ volatile("vmovdqu %0, %%ymm8\n\t"::"m"(mBYTE_FLIP_MASK_Y[0]):YMM_REGs) ;\
+     __asm__ volatile("vmovdqu %0, %%ymm12\n\t"\
+                      "vmovdqu %1, %%ymm4\n\t"\
+                      "vpshufb %%ymm8, %%ymm12, %%ymm12\n\t"\
+                      "vpshufb %%ymm8, %%ymm4, %%ymm4\n\t"\
+                      :: "m"(buff[0]),  "m"(buff[4]):YMM_REGs) ;\
+     __asm__ volatile("vmovdqu %0, %%ymm5\n\t"\
+                      "vmovdqu %1, %%ymm6\n\t"\
+                      "vpshufb %%ymm8, %%ymm5, %%ymm5\n\t"\
+                      "vpshufb %%ymm8, %%ymm6, %%ymm6\n\t"\
+                      :: "m"(buff[8]),  "m"(buff[12]):YMM_REGs) ;\
+    }
+
+#if defined(DEBUG_YMM)
+
+#define SAVE_REG_Y(i) __asm__ volatile("vmovdqu %%ymm"#i", %0 \n\t":"=m"(reg[i-4][0])::YMM_REGs);
+#define RECV_REG_Y(i) __asm__ volatile("vmovdqu %0, %%ymm"#i" \n\t"::"m"(reg[i-4][0]):YMM_REGs);
+
+#define _DUMP_REG_Y(REG, name)\
+    { word64 buf[16] ;word64 reg[16][2];int k ;\
+      SAVE_REG_Y(4);  SAVE_REG_Y(5);   SAVE_REG_Y(6); SAVE_REG_Y(7); \
+      SAVE_REG_Y(8); SAVE_REG_Y(9); SAVE_REG_Y(10); SAVE_REG_Y(11); SAVE_REG_Y(12);\
+      SAVE_REG_Y(13); SAVE_REG_Y(14); SAVE_REG_Y(15); \
+      __asm__ volatile("vmovdqu %%"#REG", %0 \n\t":"=m"(buf[0])::YMM_REGs);\
+      printf(" "#name":\t") ; for(k=0; k<4; k++) printf("%016lx.", (word64)buf[k]) ; printf("\n") ; \
+      RECV_REG_Y(4);  RECV_REG_Y(5);   RECV_REG_Y(6); RECV_REG_Y(7); \
+      RECV_REG_Y(8); RECV_REG_Y(9); RECV_REG_Y(10); RECV_REG_Y(11); RECV_REG_Y(12); \
+      RECV_REG_Y(13); RECV_REG_Y(14); RECV_REG_Y(15);\
+    }
+
+#define DUMP_REG_Y(REG) _DUMP_REG_Y(REG, #REG) 
+#define DUMP_REG2_Y(REG) _DUMP_REG_Y(REG, #REG) 
+#define PRINTF_Y(fmt, ...) 
+
+#else
+
+#define DUMP_REG_Y(REG) 
+#define DUMP_REG2_Y(REG)
+#define PRINTF_Y(fmt, ...) 
+
+#endif
+
+#define _MOVE_to_REGy(ymm, mem)         __asm__ volatile("vmovdqu %0, %%"#ymm" "\
+                                        :: "m"(mem):YMM_REGs) ;
+#define _MOVE_to_MEMy(mem,i, ymm)       __asm__ volatile("vmovdqu %%"#ymm", %0" \
+        : "=m"(mem[i]),"=m"(mem[i+1]),"=m"(mem[i+2]),"=m"(mem[i+3])::YMM_REGs) ;
+#define _MOVE_128y(ymm0, ymm1, ymm2, map)  __asm__ volatile("vperm2i128  $"\
+        #map", %%"#ymm2", %%"#ymm1", %%"#ymm0" ":::YMM_REGs) ;
+#define _S_TEMPy(dest, src, bits, temp) \
+         __asm__ volatile("vpsrlq  $"#bits", %%"#src", %%"#dest"\n\tvpsllq  $64-"#bits\
+        ", %%"#src", %%"#temp"\n\tvpor %%"#temp",%%"#dest", %%"#dest" ":::YMM_REGs) ;
+#define _AVX2_R(dest, src, bits)        __asm__ volatile("vpsrlq  $"#bits", %%"\
+         #src", %%"#dest" ":::YMM_REGs) ;
+#define _XORy(dest, src1, src2)         __asm__ volatile("vpxor   %%"#src1", %%"\
+         #src2", %%"#dest" ":::YMM_REGs) ;
+#define _ADDy(dest, src1, src2)         __asm__ volatile("vpaddq   %%"#src1", %%"\
+         #src2", %%"#dest" ":::YMM_REGs) ;
+#define _BLENDy(map, dest, src1, src2)  __asm__ volatile("vpblendd    $"#map", %%"\
+         #src1",   %%"#src2", %%"#dest" ":::YMM_REGs) ;
+#define _BLENDQy(map, dest, src1, src2) __asm__ volatile("vblendpd   $"#map", %%"\
+         #src1",   %%"#src2", %%"#dest" ":::YMM_REGs) ;
+#define _PERMQy(map, dest, src)         __asm__ volatile("vpermq  $"#map", %%"\
+         #src", %%"#dest" ":::YMM_REGs) ;
+
+#define MOVE_to_REGy(ymm, mem)      _MOVE_to_REGy(ymm, mem)
+#define MOVE_to_MEMy(mem, i, ymm)   _MOVE_to_MEMy(mem, i, ymm)
+
+#define MOVE_128y(ymm0, ymm1, ymm2, map) _MOVE_128y(ymm0, ymm1, ymm2, map) 
+#define XORy(dest, src1, src2)      _XORy(dest, src1, src2)
+#define ADDy(dest, src1, src2)      _ADDy(dest, src1, src2)
+#define BLENDy(map, dest, src1, src2) _BLENDy(map, dest, src1, src2)
+#define BLENDQy(map, dest, src1, src2) _BLENDQy(map, dest, src1, src2)
+#define PERMQy(map, dest, src)      _PERMQy(map, dest, src)
+
+
+#define S_TMPy(dest, src, bits, temp) _S_TEMPy(dest, src, bits, temp);
+#define AVX2_S(dest, src, bits)      S_TMPy(dest, src, bits, S_TEMPy)
+#define AVX2_R(dest, src, bits)      _AVX2_R(dest, src, bits)
+
+
+#define    FEEDBACK1_to_W_I_2(w_i_2, w_i)    MOVE_128y(YMM_TEMP0, w_i, w_i, 0x08) ;\
+                                       BLENDy(0xf0, w_i_2, YMM_TEMP0, w_i_2) ; 
+
+#define    MOVE_W_to_W_I_15(w_i_15, w_0, w_4)  BLENDQy(0x1, w_i_15, w_4, w_0) ;\
+                                       PERMQy(0x39, w_i_15, w_i_15) ;
+#define    MOVE_W_to_W_I_7(w_i_7,  w_8, w_12)  BLENDQy(0x1, w_i_7, w_12, w_8) ;\
+                                       PERMQy(0x39, w_i_7, w_i_7) ; 
+#define    MOVE_W_to_W_I_2(w_i_2,  w_12)       BLENDQy(0xc, w_i_2, w_12, w_i_2) ;\
+                                       PERMQy(0x0e, w_i_2, w_i_2) ;
+
+
+#define W_I_16y  ymm8
+#define W_I_15y  ymm9
+#define W_I_7y  ymm10
+#define W_I_2y  ymm11
+#define W_Iy    ymm12
+#define G_TEMPy     ymm13
+#define S_TEMPy     ymm14
+#define YMM_TEMP0  ymm15
+#define YMM_TEMP0x xmm15
+#define W_I_TEMPy   ymm7
+#define W_K_TEMPy   ymm15
+#define W_K_TEMPx  xmm15
+#define W_0y     ymm12
+#define W_4y     ymm4
+#define W_8y     ymm5
+#define W_12y    ymm6
+
+#define YMM_REGs
+/* Registers are saved in Sha512Update/Final */
+                 /* "%ymm7","%ymm8","%ymm9","%ymm10","%ymm11","%ymm12","%ymm13","%ymm14","%ymm15"*/
+
+#define MOVE_15_to_16(w_i_16, w_i_15, w_i_7)\
+    __asm__ volatile("vperm2i128  $0x01, %%"#w_i_15", %%"#w_i_15", %%"#w_i_15" ":::YMM_REGs) ;\
+    __asm__ volatile("vpblendd    $0x08, %%"#w_i_15", %%"#w_i_7", %%"#w_i_16" ":::YMM_REGs) ;\
+    __asm__ volatile("vperm2i128 $0x01,  %%"#w_i_7",  %%"#w_i_7", %%"#w_i_15" ":::YMM_REGs) ;\
+    __asm__ volatile("vpblendd    $0x80, %%"#w_i_15", %%"#w_i_16", %%"#w_i_16" ":::YMM_REGs) ;\
+    __asm__ volatile("vpshufd    $0x93,  %%"#w_i_16", %%"#w_i_16" ":::YMM_REGs) ;\
+
+#define MOVE_7_to_15(w_i_15, w_i_7)\
+    __asm__ volatile("vmovdqu                 %%"#w_i_7",  %%"#w_i_15" ":::YMM_REGs) ;\
+
+#define MOVE_I_to_7(w_i_7, w_i)\
+    __asm__ volatile("vperm2i128 $0x01,       %%"#w_i",   %%"#w_i",   %%"#w_i_7" ":::YMM_REGs) ;\
+    __asm__ volatile("vpblendd    $0x01,       %%"#w_i_7",   %%"#w_i", %%"#w_i_7" ":::YMM_REGs) ;\
+    __asm__ volatile("vpshufd    $0x39, %%"#w_i_7", %%"#w_i_7" ":::YMM_REGs) ;\
+
+#define MOVE_I_to_2(w_i_2, w_i)\
+    __asm__ volatile("vperm2i128 $0x01,       %%"#w_i", %%"#w_i", %%"#w_i_2" ":::YMM_REGs) ;\
+    __asm__ volatile("vpshufd    $0x0e, %%"#w_i_2", %%"#w_i_2" ":::YMM_REGs) ;\
+
+#endif
+
+
+/***  Transform Body ***/
+#if defined(HAVE_INTEL_AVX1)
+
+static int Transform_AVX1(Sha512* sha512)
+{
+    const word64* K = K512;
+    word64 W_X[16+4];
+    word32 j;
+    word64 T[8];
+    /* Copy digest to working vars */
+    XMEMCPY(T, sha512->digest, sizeof(T));
+
+    W_from_buff(W_X, sha512->buffer) ;
+    for (j = 0; j < 80; j += 16) {
+        Rx_1( 0); Block_0_1(W_X); Rx_2( 0); Block_0_2(W_X); Rx_3( 0); Block_0_3(); 
+        Rx_1( 1); Block_0_4(); Rx_2( 1); Block_0_5(); Rx_3( 1); Block_0_6(W_X); 
+        Rx_1( 2); Block_0_7(W_X); Rx_2( 2); Block_0_8(W_X); Rx_3( 2); Block_0_9();
+        Rx_1( 3); Block_0_10();Rx_2( 3); Block_0_11();Rx_3( 3); Block_0_12(W_X);   
+        
+        Rx_1( 4); Block_4_1(W_X); Rx_2( 4); Block_4_2(W_X); Rx_3( 4); Block_4_3(); 
+        Rx_1( 5); Block_4_4(); Rx_2( 5); Block_4_5(); Rx_3( 5); Block_4_6(W_X); 
+        Rx_1( 6); Block_4_7(W_X); Rx_2( 6); Block_4_8(W_X); Rx_3( 6); Block_4_9();
+        Rx_1( 7); Block_4_10();Rx_2( 7); Block_4_11();Rx_3( 7); Block_4_12(W_X);   
+        
+        Rx_1( 8); Block_8_1(W_X); Rx_2( 8); Block_8_2(W_X); Rx_3( 8); Block_8_3(); 
+        Rx_1( 9); Block_8_4(); Rx_2( 9); Block_8_5(); Rx_3( 9); Block_8_6(W_X); 
+        Rx_1(10); Block_8_7(W_X); Rx_2(10); Block_8_8(W_X); Rx_3(10); Block_8_9();
+        Rx_1(11); Block_8_10();Rx_2(11); Block_8_11();Rx_3(11); Block_8_12(W_X);   
+        
+        Rx_1(12); Block_12_1(W_X); Rx_2(12); Block_12_2(W_X); Rx_3(12); Block_12_3(); 
+        Rx_1(13); Block_12_4(); Rx_2(13); Block_12_5(); Rx_3(13); Block_12_6(W_X); 
+        Rx_1(14); Block_12_7(W_X); Rx_2(14); Block_12_8(W_X); Rx_3(14); Block_12_9();
+        Rx_1(15); Block_12_10();Rx_2(15); Block_12_11();Rx_3(15); Block_12_12(W_X);     
+    }
+
+    /* Add the working vars back into digest */
+
+    sha512->digest[0] += a(0);
+    sha512->digest[1] += b(0);
+    sha512->digest[2] += c(0);
+    sha512->digest[3] += d(0);
+    sha512->digest[4] += e(0);
+    sha512->digest[5] += f(0);
+    sha512->digest[6] += g(0);
+    sha512->digest[7] += h(0);
+
+    /* Wipe variables */
+    #if !defined(HAVE_INTEL_AVX1)&&!defined(HAVE_INTEL_AVX2)
+    XMEMSET(W_X, 0, sizeof(word64) * 16);
+    #endif
+    XMEMSET(T, 0, sizeof(T));
+
+    return 0;
+}
+
+#endif
+
+#if defined(HAVE_INTEL_AVX2) && defined(HAVE_INTEL_AVX1) && defined(HAVE_INTEL_RORX)
+
+static int Transform_AVX1_RORX(Sha512* sha512)
+{
+    const word64* K = K512;
+    word64 W_X[16+4];
+    word32 j;
+    word64 T[8];
+    /* Copy digest to working vars */
+    XMEMCPY(T, sha512->digest, sizeof(T));
+
+    W_from_buff(W_X, sha512->buffer) ;
+    for (j = 0; j < 80; j += 16) {
+        Rx_RORX_1( 0); Block_0_1(W_X); Rx_RORX_2( 0); Block_0_2(W_X); 
+                                    Rx_RORX_3( 0); Block_0_3(); 
+        Rx_RORX_1( 1); Block_0_4(); Rx_RORX_2( 1); Block_0_5(); 
+                                    Rx_RORX_3( 1); Block_0_6(W_X); 
+        Rx_RORX_1( 2); Block_0_7(W_X); Rx_RORX_2( 2); Block_0_8(W_X); 
+                                    Rx_RORX_3( 2); Block_0_9();
+        Rx_RORX_1( 3); Block_0_10();Rx_RORX_2( 3); Block_0_11();
+                                    Rx_RORX_3( 3); Block_0_12(W_X);   
+        
+        Rx_RORX_1( 4); Block_4_1(W_X); Rx_RORX_2( 4); Block_4_2(W_X); 
+                                    Rx_RORX_3( 4); Block_4_3(); 
+        Rx_RORX_1( 5); Block_4_4(); Rx_RORX_2( 5); Block_4_5(); 
+                                    Rx_RORX_3( 5); Block_4_6(W_X); 
+        Rx_RORX_1( 6); Block_4_7(W_X); Rx_RORX_2( 6); Block_4_8(W_X); 
+                                    Rx_RORX_3( 6); Block_4_9();
+        Rx_RORX_1( 7); Block_4_10();Rx_RORX_2( 7); Block_4_11();
+                                    Rx_RORX_3( 7); Block_4_12(W_X);   
+        
+        Rx_RORX_1( 8); Block_8_1(W_X); Rx_RORX_2( 8); Block_8_2(W_X); 
+                                    Rx_RORX_3( 8); Block_8_3(); 
+        Rx_RORX_1( 9); Block_8_4(); Rx_RORX_2( 9); Block_8_5(); 
+                                    Rx_RORX_3( 9); Block_8_6(W_X); 
+        Rx_RORX_1(10); Block_8_7(W_X); Rx_RORX_2(10); Block_8_8(W_X); 
+                                    Rx_RORX_3(10); Block_8_9();
+        Rx_RORX_1(11); Block_8_10();Rx_RORX_2(11); Block_8_11();
+                                    Rx_RORX_3(11); Block_8_12(W_X);   
+        
+        Rx_RORX_1(12); Block_12_1(W_X); Rx_RORX_2(12); Block_12_2(W_X); 
+                                     Rx_RORX_3(12); Block_12_3(); 
+        Rx_RORX_1(13); Block_12_4(); Rx_RORX_2(13); Block_12_5(); 
+                                     Rx_RORX_3(13); Block_12_6(W_X); 
+        Rx_RORX_1(14); Block_12_7(W_X); Rx_RORX_2(14); Block_12_8(W_X); 
+                                     Rx_RORX_3(14); Block_12_9();
+        Rx_RORX_1(15); Block_12_10();Rx_RORX_2(15); Block_12_11();
+                                     Rx_RORX_3(15); Block_12_12(W_X);     
+    }
+    /* Add the working vars back into digest */
+
+    sha512->digest[0] += a(0);
+    sha512->digest[1] += b(0);
+    sha512->digest[2] += c(0);
+    sha512->digest[3] += d(0);
+    sha512->digest[4] += e(0);
+    sha512->digest[5] += f(0);
+    sha512->digest[6] += g(0);
+    sha512->digest[7] += h(0);
+
+    /* Wipe variables */
+    #if !defined(HAVE_INTEL_AVX1)&&!defined(HAVE_INTEL_AVX2)
+    XMEMSET(W_X, 0, sizeof(word64) * 16);
+    #endif
+    XMEMSET(T, 0, sizeof(T));
+
+    return 0;
+}
+#endif
+
+#if defined(HAVE_INTEL_AVX2)
+
+#define s0_1y(dest, src)      AVX2_S(dest, src, 1); 
+#define s0_2y(dest, src)      AVX2_S(G_TEMPy, src, 8); XORy(dest, G_TEMPy, dest) ; 
+#define s0_3y(dest, src)      AVX2_R(G_TEMPy, src, 7);  XORy(dest, G_TEMPy, dest) ;
+
+#define s1_1y(dest, src)      AVX2_S(dest, src, 19);
+#define s1_2y(dest, src)      AVX2_S(G_TEMPy, src, 61); XORy(dest, G_TEMPy, dest) ; 
+#define s1_3y(dest, src)      AVX2_R(G_TEMPy, src, 6); XORy(dest, G_TEMPy, dest) ;
+
+#define s0_y(dest, src)       s0_1y(dest, src) ; s0_2y(dest, src) ; s0_3y(dest, src)
+#define s1_y(dest, src)       s1_1y(dest, src) ; s1_2y(dest, src) ; s1_3y(dest, src)
+
+#define blk384(i) (W[i] = sha384->buffer[i])
+
+
+#define Block_Y_xx_1(i, w_0, w_4, w_8, w_12)\
+    MOVE_W_to_W_I_15(W_I_15y, w_0, w_4) ;\
+    MOVE_W_to_W_I_7 (W_I_7y,  w_8, w_12) ;\
+    MOVE_W_to_W_I_2 (W_I_2y,  w_12) ;\
+
+#define Block_Y_xx_2(i, w_0, w_4, w_8, w_12)\
+    s0_1y (YMM_TEMP0, W_I_15y) ;\
+
+#define Block_Y_xx_3(i, w_0, w_4, w_8, w_12)\
+    s0_2y (YMM_TEMP0, W_I_15y) ;\
+
+#define Block_Y_xx_4(i, w_0, w_4, w_8, w_12)\
+    s0_3y (YMM_TEMP0, W_I_15y) ;\
+
+#define Block_Y_xx_5(i, w_0, w_4, w_8, w_12)\
+    ADDy(W_I_TEMPy, w_0, YMM_TEMP0) ;\
+
+#define Block_Y_xx_6(i, w_0, w_4, w_8, w_12)\
+    ADDy(W_I_TEMPy, W_I_TEMPy, W_I_7y) ;\
+    s1_1y (YMM_TEMP0, W_I_2y) ;\
+
+#define Block_Y_xx_7(i, w_0, w_4, w_8, w_12)\
+    s1_2y (YMM_TEMP0, W_I_2y) ;\
+
+#define Block_Y_xx_8(i, w_0, w_4, w_8, w_12)\
+    s1_3y (YMM_TEMP0, W_I_2y) ;\
+    ADDy(w_0, W_I_TEMPy, YMM_TEMP0) ;\
+
+#define Block_Y_xx_9(i, w_0, w_4, w_8, w_12)\
+    FEEDBACK1_to_W_I_2(W_I_2y, w_0) ;\
+
+#define Block_Y_xx_10(i, w_0, w_4, w_8, w_12) \
+    s1_1y (YMM_TEMP0, W_I_2y) ;\
+
+#define Block_Y_xx_11(i, w_0, w_4, w_8, w_12) \
+    s1_2y (YMM_TEMP0, W_I_2y) ;\
+
+#define Block_Y_xx_12(i, w_0, w_4, w_8, w_12)\
+    s1_3y (YMM_TEMP0, W_I_2y) ;\
+    ADDy(w_0, W_I_TEMPy, YMM_TEMP0) ;\
+    MOVE_to_MEMy(w,0, w_4) ;\
+
+
+static inline void Block_Y_0_1(void) { Block_Y_xx_1(0, W_0y, W_4y, W_8y, W_12y) ; }
+static inline void Block_Y_0_2(void) { Block_Y_xx_2(0, W_0y, W_4y, W_8y, W_12y) ; }
+static inline void Block_Y_0_3(void) { Block_Y_xx_3(0, W_0y, W_4y, W_8y, W_12y) ; }
+static inline void Block_Y_0_4(void) { Block_Y_xx_4(0, W_0y, W_4y, W_8y, W_12y) ; }
+static inline void Block_Y_0_5(void) { Block_Y_xx_5(0, W_0y, W_4y, W_8y, W_12y) ; }
+static inline void Block_Y_0_6(void) { Block_Y_xx_6(0, W_0y, W_4y, W_8y, W_12y) ; }
+static inline void Block_Y_0_7(void) { Block_Y_xx_7(0, W_0y, W_4y, W_8y, W_12y) ; }
+static inline void Block_Y_0_8(void) { Block_Y_xx_8(0, W_0y, W_4y, W_8y, W_12y) ; }
+static inline void Block_Y_0_9(void) { Block_Y_xx_9(0, W_0y, W_4y, W_8y, W_12y) ; }
+static inline void Block_Y_0_10(void){ Block_Y_xx_10(0, W_0y, W_4y, W_8y, W_12y) ; }
+static inline void Block_Y_0_11(void){ Block_Y_xx_11(0, W_0y, W_4y, W_8y, W_12y) ; }
+static inline void Block_Y_0_12(word64 *w){ Block_Y_xx_12(0, W_0y, W_4y, W_8y, W_12y) ; }
+
+static inline void Block_Y_4_1(void) { Block_Y_xx_1(4, W_4y, W_8y, W_12y, W_0y) ; }
+static inline void Block_Y_4_2(void) { Block_Y_xx_2(4, W_4y, W_8y, W_12y, W_0y) ; }
+static inline void Block_Y_4_3(void) { Block_Y_xx_3(4, W_4y, W_8y, W_12y, W_0y) ; }
+static inline void Block_Y_4_4(void) { Block_Y_xx_4(4, W_4y, W_8y, W_12y, W_0y) ; }
+static inline void Block_Y_4_5(void) { Block_Y_xx_5(4, W_4y, W_8y, W_12y, W_0y) ; }
+static inline void Block_Y_4_6(void) { Block_Y_xx_6(4, W_4y, W_8y, W_12y, W_0y) ; }
+static inline void Block_Y_4_7(void) { Block_Y_xx_7(4, W_4y, W_8y, W_12y, W_0y) ; }
+static inline void Block_Y_4_8(void) { Block_Y_xx_8(4, W_4y, W_8y, W_12y, W_0y) ; }
+static inline void Block_Y_4_9(void) { Block_Y_xx_9(4, W_4y, W_8y, W_12y, W_0y) ; }
+static inline void Block_Y_4_10(void) { Block_Y_xx_10(4, W_4y, W_8y, W_12y, W_0y) ; }
+static inline void Block_Y_4_11(void) { Block_Y_xx_11(4, W_4y, W_8y, W_12y, W_0y) ; }
+static inline void Block_Y_4_12(word64 *w) { Block_Y_xx_12(4, W_4y, W_8y, W_12y, W_0y) ; }
+
+static inline void Block_Y_8_1(void) { Block_Y_xx_1(8, W_8y, W_12y, W_0y, W_4y) ; }
+static inline void Block_Y_8_2(void) { Block_Y_xx_2(8, W_8y, W_12y, W_0y, W_4y) ; }
+static inline void Block_Y_8_3(void) { Block_Y_xx_3(8, W_8y, W_12y, W_0y, W_4y) ; }
+static inline void Block_Y_8_4(void) { Block_Y_xx_4(8, W_8y, W_12y, W_0y, W_4y) ; }
+static inline void Block_Y_8_5(void) { Block_Y_xx_5(8, W_8y, W_12y, W_0y, W_4y) ; }
+static inline void Block_Y_8_6(void) { Block_Y_xx_6(8, W_8y, W_12y, W_0y, W_4y) ; }
+static inline void Block_Y_8_7(void) { Block_Y_xx_7(8, W_8y, W_12y, W_0y, W_4y) ; }
+static inline void Block_Y_8_8(void) { Block_Y_xx_8(8, W_8y, W_12y, W_0y, W_4y) ; }
+static inline void Block_Y_8_9(void) { Block_Y_xx_9(8, W_8y, W_12y, W_0y, W_4y) ; }
+static inline void Block_Y_8_10(void) { Block_Y_xx_10(8, W_8y, W_12y, W_0y, W_4y) ; }
+static inline void Block_Y_8_11(void) { Block_Y_xx_11(8, W_8y, W_12y, W_0y, W_4y) ; }
+static inline void Block_Y_8_12(word64 *w) { Block_Y_xx_12(8, W_8y, W_12y, W_0y, W_4y) ; }
+
+static inline void Block_Y_12_1(void) { Block_Y_xx_1(12, W_12y, W_0y, W_4y, W_8y) ; }
+static inline void Block_Y_12_2(void) { Block_Y_xx_2(12, W_12y, W_0y, W_4y, W_8y) ; }
+static inline void Block_Y_12_3(void) { Block_Y_xx_3(12, W_12y, W_0y, W_4y, W_8y) ; }
+static inline void Block_Y_12_4(void) { Block_Y_xx_4(12, W_12y, W_0y, W_4y, W_8y) ; }
+static inline void Block_Y_12_5(void) { Block_Y_xx_5(12, W_12y, W_0y, W_4y, W_8y) ; }
+static inline void Block_Y_12_6(void) { Block_Y_xx_6(12, W_12y, W_0y, W_4y, W_8y) ; }
+static inline void Block_Y_12_7(void) { Block_Y_xx_7(12, W_12y, W_0y, W_4y, W_8y) ; }
+static inline void Block_Y_12_8(void) { Block_Y_xx_8(12, W_12y, W_0y, W_4y, W_8y) ; }
+static inline void Block_Y_12_9(void) { Block_Y_xx_9(12, W_12y, W_0y, W_4y, W_8y) ; }
+static inline void Block_Y_12_10(void) { Block_Y_xx_10(12, W_12y, W_0y, W_4y, W_8y) ; }
+static inline void Block_Y_12_11(void) { Block_Y_xx_11(12, W_12y, W_0y, W_4y, W_8y) ; }
+static inline void Block_Y_12_12(word64 *w) { Block_Y_xx_12(12, W_12y, W_0y, W_4y, W_8y) ; }
+
+
+static int Transform_AVX2(Sha512* sha512)
+{
+    const word64* K = K512;
+    word64 w[4] ;
+    word32 j /*, k*/;
+    word64 T[8];
+    /* Copy digest to working vars */
+    XMEMCPY(T, sha512->digest, sizeof(T));
+
+    W_from_buff_Y(sha512->buffer) ;
+    MOVE_to_MEMy(w,0, W_0y) ; 
+    for (j = 0; j < 80; j += 16) {
+        Ry_1( 0, w[0]); Block_Y_0_1(); Ry_2( 0, w[0]); Block_Y_0_2(); 
+                                       Ry_3( 0, w[0]); Block_Y_0_3(); 
+        Ry_1( 1, w[1]); Block_Y_0_4(); Ry_2( 1, w[1]); Block_Y_0_5(); 
+                                       Ry_3( 1, w[1]); Block_Y_0_6();  
+        Ry_1( 2, w[2]); Block_Y_0_7(); Ry_2( 2, w[2]); Block_Y_0_8(); 
+                                       Ry_3( 2, w[2]); Block_Y_0_9();
+        Ry_1( 3, w[3]); Block_Y_0_10();Ry_2( 3, w[3]); Block_Y_0_11();
+                                       Ry_3( 3, w[3]); Block_Y_0_12(w);
+        
+        Ry_1( 4, w[0]); Block_Y_4_1(); Ry_2( 4, w[0]); Block_Y_4_2(); 
+                                       Ry_3( 4, w[0]); Block_Y_4_3(); 
+        Ry_1( 5, w[1]); Block_Y_4_4(); Ry_2( 5, w[1]); Block_Y_4_5(); 
+                                       Ry_3( 5, w[1]); Block_Y_4_6();
+        Ry_1( 6, w[2]); Block_Y_4_7(); Ry_2( 6, w[2]); Block_Y_4_8(); 
+                                       Ry_3( 6, w[2]); Block_Y_4_9();
+        Ry_1( 7, w[3]); Block_Y_4_10(); Ry_2( 7, w[3]);Block_Y_4_11(); 
+                                        Ry_3( 7, w[3]);Block_Y_4_12(w);  
+        
+        Ry_1( 8, w[0]); Block_Y_8_1(); Ry_2( 8, w[0]); Block_Y_8_2(); 
+                                       Ry_3( 8, w[0]); Block_Y_8_3();
+        Ry_1( 9, w[1]); Block_Y_8_4(); Ry_2( 9, w[1]); Block_Y_8_5(); 
+                                       Ry_3( 9, w[1]); Block_Y_8_6();
+        Ry_1(10, w[2]); Block_Y_8_7(); Ry_2(10, w[2]); Block_Y_8_8(); 
+                                       Ry_3(10, w[2]); Block_Y_8_9(); 
+        Ry_1(11, w[3]); Block_Y_8_10();Ry_2(11, w[3]); Block_Y_8_11();
+                                       Ry_3(11, w[3]); Block_Y_8_12(w);
+                 
+        Ry_1(12, w[0]); Block_Y_12_1(); Ry_2(12, w[0]); Block_Y_12_2(); 
+                                        Ry_3(12, w[0]); Block_Y_12_3();
+        Ry_1(13, w[1]); Block_Y_12_4(); Ry_2(13, w[1]); Block_Y_12_5(); 
+                                        Ry_3(13, w[1]); Block_Y_12_6(); 
+        Ry_1(14, w[2]); Block_Y_12_7(); Ry_2(14, w[2]); Block_Y_12_8(); 
+                                        Ry_3(14, w[2]); Block_Y_12_9();
+        Ry_1(15, w[3]); Block_Y_12_10();Ry_2(15, w[3]); Block_Y_12_11();
+                                        Ry_3(15, w[3]);Block_Y_12_12(w);
+    }
+ 
+    /* Add the working vars back into digest */
+
+    sha512->digest[0] += a(0);
+    sha512->digest[1] += b(0);
+    sha512->digest[2] += c(0);
+    sha512->digest[3] += d(0);
+    sha512->digest[4] += e(0);
+    sha512->digest[5] += f(0);
+    sha512->digest[6] += g(0);
+    sha512->digest[7] += h(0);
+
+    /* Wipe variables */
+    #if !defined(HAVE_INTEL_AVX1)&&!defined(HAVE_INTEL_AVX2)
+    XMEMSET(W, 0, sizeof(word64) * 16);
+    #endif
+    XMEMSET(T, 0, sizeof(T));
+
+    return 0;
+}
+
+#endif
+
+
+#ifdef WOLFSSL_SHA384
+
+#if defined(HAVE_INTEL_AVX1) ||  defined(HAVE_INTEL_AVX2) 
+
+#if defined(HAVE_INTEL_AVX1)
+static int Transform384_AVX1(Sha384 *sha384) ;
+#endif
+#if defined(HAVE_INTEL_AVX2)
+static int Transform384_AVX2(Sha384 *sha384) ; 
+#endif
+
+#if defined(HAVE_INTEL_AVX1) &&  defined(HAVE_INTEL_AVX2) &&defined(HAVE_INTEL_RORX)
+static int Transform384_AVX1_RORX(Sha384 *sha384) ; 
+#endif
+
+static int _Transform384(Sha384 *sha384) ; 
+static int (*Transform384_p)(Sha384* sha384) = _Transform384 ;
+
+#define Transform384(sha384) (*Transform384_p)(sha384)
+static void set_Transform384(void) {
+     if(set_cpuid_flags(CHECK_SHA384))return ;
+
+#if defined(HAVE_INTEL_AVX1) && !defined(HAVE_INTEL_AVX2)
+     Transform384_p = ((IS_INTEL_AVX1) ? Transform384_AVX1 : _Transform384) ;
+#elif defined(HAVE_INTEL_AVX2)
+     #if defined(HAVE_INTEL_AVX1) && defined(HAVE_INTEL_RORX)
+     if(IS_INTEL_AVX2 && IS_INTEL_BMI2) { Transform384_p = Transform384_AVX1_RORX ; return ; }
+     #endif
+     if(IS_INTEL_AVX2) { Transform384_p = Transform384_AVX2 ; return ; }
+     #if defined(HAVE_INTEL_AVX1)
+     Transform384_p = ((IS_INTEL_AVX1) ? Transform384_AVX1 : _Transform384) ;
+     #endif
+#else
+     Transform384_p = ((IS_INTEL_AVX1) ? Transform384_AVX1 : _Transform384) ;
+#endif
+}
+
+#else
+   #define Transform384(sha512) _Transform384(sha512)
+#endif
+
+int wc_InitSha384(Sha384* sha384)
+{
+    sha384->digest[0] = W64LIT(0xcbbb9d5dc1059ed8);
+    sha384->digest[1] = W64LIT(0x629a292a367cd507);
+    sha384->digest[2] = W64LIT(0x9159015a3070dd17);
+    sha384->digest[3] = W64LIT(0x152fecd8f70e5939);
+    sha384->digest[4] = W64LIT(0x67332667ffc00b31);
+    sha384->digest[5] = W64LIT(0x8eb44a8768581511);
+    sha384->digest[6] = W64LIT(0xdb0c2e0d64f98fa7);
+    sha384->digest[7] = W64LIT(0x47b5481dbefa4fa4);
+
+    sha384->buffLen = 0;
+    sha384->loLen   = 0;
+    sha384->hiLen   = 0;
+
+#if defined(HAVE_INTEL_AVX1)|| defined(HAVE_INTEL_AVX2)
+    set_Transform384() ;
+#endif
+    
+    return 0;
+}
+
+static int _Transform384(Sha384* sha384)
+{
+    const word64* K = K512;
+
+    word32 j;
+    word64 T[8];
+
+#ifdef WOLFSSL_SMALL_STACK
+    word64* W;
+
+    W = (word64*) XMALLOC(sizeof(word64) * 16, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (W == NULL)
+        return MEMORY_E;
+#else
+    word64 W[16];
+#endif
+
+    /* Copy digest to working vars */
+    XMEMCPY(T, sha384->digest, sizeof(T));
+
+#ifdef USE_SLOW_SHA2
+    /* over twice as small, but 50% slower */
+    /* 80 operations, not unrolled */
+    for (j = 0; j < 80; j += 16) {
+        int m;
+        for (m = 0; m < 16; m++) {  /* braces needed for macros {} */
+            R2(m);
+        }
+    }
+#else
+    /* 80 operations, partially loop unrolled */
+    for (j = 0; j < 80; j += 16) {
+        R2( 0); R2( 1); R2( 2); R2( 3);
+        R2( 4); R2( 5); R2( 6); R2( 7);
+        R2( 8); R2( 9); R2(10); R2(11);
+        R2(12); R2(13); R2(14); R2(15);
+    }
+#endif /* USE_SLOW_SHA2 */
+
+    /* Add the working vars back into digest */
+
+    sha384->digest[0] += a(0);
+    sha384->digest[1] += b(0);
+    sha384->digest[2] += c(0);
+    sha384->digest[3] += d(0);
+    sha384->digest[4] += e(0);
+    sha384->digest[5] += f(0);
+    sha384->digest[6] += g(0);
+    sha384->digest[7] += h(0);
+
+    /* Wipe variables */
+    XMEMSET(W, 0, sizeof(word64) * 16);
+    XMEMSET(T, 0, sizeof(T));
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(W, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return 0;
+}
+
+static INLINE void AddLength384(Sha384* sha384, word32 len)
+{
+    word32 tmp = sha384->loLen;
+    if ( (sha384->loLen += len) < tmp)
+        sha384->hiLen++;                       /* carry low to high */
+}
+
+int wc_Sha384Update(Sha384* sha384, const byte* data, word32 len)
+{
+    /* do block size increments */
+    byte* local = (byte*)sha384->buffer;
+	
+    SAVE_XMM_YMM ; /* for Intel AVX */
+    
+    while (len) {
+        word32 add = min(len, SHA384_BLOCK_SIZE - sha384->buffLen);
+        XMEMCPY(&local[sha384->buffLen], data, add);
+
+        sha384->buffLen += add;
+        data         += add;
+        len          -= add;
+
+        if (sha384->buffLen == SHA384_BLOCK_SIZE) {
+            int ret;
+
+            #if defined(LITTLE_ENDIAN_ORDER)
+                #if defined(HAVE_INTEL_AVX1) || defined(HAVE_INTEL_AVX2)
+                if(!IS_INTEL_AVX1 && !IS_INTEL_AVX2) 
+                #endif
+                    ByteReverseWords64(sha384->buffer, sha384->buffer,
+                                   SHA384_BLOCK_SIZE);
+            #endif
+            ret = Transform384(sha384);
+            if (ret != 0)
+                return ret;
+
+            AddLength384(sha384, SHA384_BLOCK_SIZE);
+            sha384->buffLen = 0;
+        }
+    }
+    return 0;
+}
+
+
+int wc_Sha384Final(Sha384* sha384, byte* hash)
+{
+    byte* local = (byte*)sha384->buffer;
+    int ret;
+
+    SAVE_XMM_YMM ; /* for Intel AVX */
+    AddLength384(sha384, sha384->buffLen);              /* before adding pads */
+
+    local[sha384->buffLen++] = 0x80;  /* add 1 */
+
+    /* pad with zeros */
+    if (sha384->buffLen > SHA384_PAD_SIZE) {
+        XMEMSET(&local[sha384->buffLen], 0, SHA384_BLOCK_SIZE -sha384->buffLen);
+        sha384->buffLen += SHA384_BLOCK_SIZE - sha384->buffLen;
+
+        #if defined(LITTLE_ENDIAN_ORDER)
+            #if defined(HAVE_INTEL_AVX1) || defined(HAVE_INTEL_AVX2)
+            if(!IS_INTEL_AVX1 && !IS_INTEL_AVX2) 
+            #endif
+                 ByteReverseWords64(sha384->buffer, sha384->buffer,
+                               SHA384_BLOCK_SIZE);
+        #endif
+        ret = Transform384(sha384);
+        if (ret !=  0)
+            return ret;
+
+        sha384->buffLen = 0;
+    }
+    XMEMSET(&local[sha384->buffLen], 0, SHA384_PAD_SIZE - sha384->buffLen);
+   
+    /* put lengths in bits */
+    sha384->hiLen = (sha384->loLen >> (8*sizeof(sha384->loLen) - 3)) + 
+                 (sha384->hiLen << 3);
+    sha384->loLen = sha384->loLen << 3;
+
+    /* store lengths */
+    #if defined(LITTLE_ENDIAN_ORDER)
+        #if defined(HAVE_INTEL_AVX1) || defined(HAVE_INTEL_AVX2)
+        if(!IS_INTEL_AVX1 && !IS_INTEL_AVX2) 
+        #endif
+             ByteReverseWords64(sha384->buffer, sha384->buffer,
+                           SHA384_BLOCK_SIZE);
+    #endif
+    /* ! length ordering dependent on digest endian type ! */
+    sha384->buffer[SHA384_BLOCK_SIZE / sizeof(word64) - 2] = sha384->hiLen;
+    sha384->buffer[SHA384_BLOCK_SIZE / sizeof(word64) - 1] = sha384->loLen;
+    #if defined(HAVE_INTEL_AVX1) || defined(HAVE_INTEL_AVX2)
+    if(IS_INTEL_AVX1 || IS_INTEL_AVX2)
+        ByteReverseWords64(&(sha384->buffer[SHA384_BLOCK_SIZE / sizeof(word64) - 2]),
+                           &(sha384->buffer[SHA384_BLOCK_SIZE / sizeof(word64) - 2]),
+                           SHA384_BLOCK_SIZE - SHA384_PAD_SIZE);
+    #endif
+    ret = Transform384(sha384);
+    if (ret != 0)
+        return ret;
+
+    #ifdef LITTLE_ENDIAN_ORDER
+        ByteReverseWords64(sha384->digest, sha384->digest, SHA384_DIGEST_SIZE);
+    #endif
+    XMEMCPY(hash, sha384->digest, SHA384_DIGEST_SIZE);
+
+    return wc_InitSha384(sha384);  /* reset state */
+}
+
+
+int wc_Sha384Hash(const byte* data, word32 len, byte* hash)
+{
+    int ret = 0;
+#ifdef WOLFSSL_SMALL_STACK
+    Sha384* sha384;
+#else
+    Sha384 sha384[1];
+#endif
+
+#ifdef WOLFSSL_SMALL_STACK
+    sha384 = (Sha384*)XMALLOC(sizeof(Sha384), NULL, DYNAMIC_TYPE_TMP_BUFFER);
+    if (sha384 == NULL)
+        return MEMORY_E;
+#endif
+
+    if ((ret = wc_InitSha384(sha384)) != 0) {
+        WOLFSSL_MSG("InitSha384 failed");
+    }
+    else if ((ret = wc_Sha384Update(sha384, data, len)) != 0) {
+        WOLFSSL_MSG("Sha384Update failed");
+    }
+    else if ((ret = wc_Sha384Final(sha384, hash)) != 0) {
+        WOLFSSL_MSG("Sha384Final failed");
+    }
+
+#ifdef WOLFSSL_SMALL_STACK
+    XFREE(sha384, NULL, DYNAMIC_TYPE_TMP_BUFFER);
+#endif
+
+    return ret;
+}
+
+#if defined(HAVE_INTEL_AVX1)
+ 
+static int Transform384_AVX1(Sha384* sha384)
+{
+    const word64* K = K512;
+    word64 W_X[16+4];
+    word32 j;
+    word64 T[8];
+
+    /* Copy digest to working vars */
+    XMEMCPY(T, sha384->digest, sizeof(T));
+    W_from_buff(W_X, sha384->buffer) ;
+    for (j = 0; j < 80; j += 16) {
+        Rx_1( 0); Block_0_1(W_X); Rx_2( 0); Block_0_2(W_X); Rx_3( 0); Block_0_3(); 
+        Rx_1( 1); Block_0_4(); Rx_2( 1); Block_0_5(); Rx_3( 1); Block_0_6(W_X); 
+        Rx_1( 2); Block_0_7(W_X); Rx_2( 2); Block_0_8(W_X); Rx_3( 2); Block_0_9();
+        Rx_1( 3); Block_0_10();Rx_2( 3); Block_0_11();Rx_3( 3); Block_0_12(W_X);   
+        
+        Rx_1( 4); Block_4_1(W_X); Rx_2( 4); Block_4_2(W_X); Rx_3( 4); Block_4_3(); 
+        Rx_1( 5); Block_4_4(); Rx_2( 5); Block_4_5(); Rx_3( 5); Block_4_6(W_X); 
+        Rx_1( 6); Block_4_7(W_X); Rx_2( 6); Block_4_8(W_X); Rx_3( 6); Block_4_9();
+        Rx_1( 7); Block_4_10();Rx_2( 7); Block_4_11();Rx_3( 7); Block_4_12(W_X);   
+        
+        Rx_1( 8); Block_8_1(W_X); Rx_2( 8); Block_8_2(W_X); Rx_3( 8); Block_8_3(); 
+        Rx_1( 9); Block_8_4(); Rx_2( 9); Block_8_5(); Rx_3( 9); Block_8_6(W_X); 
+        Rx_1(10); Block_8_7(W_X); Rx_2(10); Block_8_8(W_X); Rx_3(10); Block_8_9();
+        Rx_1(11); Block_8_10();Rx_2(11); Block_8_11();Rx_3(11); Block_8_12(W_X);   
+        
+        Rx_1(12); Block_12_1(W_X); Rx_2(12); Block_12_2(W_X); Rx_3(12); Block_12_3(); 
+        Rx_1(13); Block_12_4(); Rx_2(13); Block_12_5(); Rx_3(13); Block_12_6(W_X); 
+        Rx_1(14); Block_12_7(W_X); Rx_2(14); Block_12_8(W_X); Rx_3(14); Block_12_9();
+        Rx_1(15); Block_12_10();Rx_2(15); Block_12_11();Rx_3(15); Block_12_12(W_X);     
+    }
+
+    /* Add the working vars back into digest */
+
+    sha384->digest[0] += a(0);
+    sha384->digest[1] += b(0);
+    sha384->digest[2] += c(0);
+    sha384->digest[3] += d(0);
+    sha384->digest[4] += e(0);
+    sha384->digest[5] += f(0);
+    sha384->digest[6] += g(0);
+    sha384->digest[7] += h(0);
+
+    /* Wipe variables */
+    #if !defined(HAVE_INTEL_AVX1)&&!defined(HAVE_INTEL_AVX2)
+    XMEMSET(W, 0, sizeof(word64) * 16);
+    #endif
+    XMEMSET(T, 0, sizeof(T));
+
+    return 0;
+}
+
+#endif
+
+#if defined(HAVE_INTEL_AVX1) && defined(HAVE_INTEL_AVX2) && defined(HAVE_INTEL_RORX)
+static int Transform384_AVX1_RORX(Sha384* sha384)
+{
+    const word64* K = K512;
+    word64 W_X[16+4];
+    word32 j;
+    word64 T[8];
+
+    /* Copy digest to working vars */
+    XMEMCPY(T, sha384->digest, sizeof(T));
+
+    W_from_buff(W_X, sha384->buffer) ;
+    for (j = 0; j < 80; j += 16) {
+        Rx_RORX_1( 0); Block_0_1(W_X); Rx_RORX_2( 0); 
+            Block_0_2(W_X); Rx_RORX_3( 0); Block_0_3(); 
+        Rx_RORX_1( 1); Block_0_4(); Rx_RORX_2( 1); 
+            Block_0_5(); Rx_RORX_3( 1); Block_0_6(W_X); 
+        Rx_RORX_1( 2); Block_0_7(W_X); Rx_RORX_2( 2); 
+            Block_0_8(W_X); Rx_RORX_3( 2); Block_0_9();
+        Rx_RORX_1( 3); Block_0_10();Rx_RORX_2( 3); 
+            Block_0_11();Rx_RORX_3( 3); Block_0_12(W_X);   
+        
+        Rx_RORX_1( 4); Block_4_1(W_X); Rx_RORX_2( 4); 
+            Block_4_2(W_X); Rx_RORX_3( 4); Block_4_3(); 
+        Rx_RORX_1( 5); Block_4_4(); Rx_RORX_2( 5); 
+            Block_4_5(); Rx_RORX_3( 5); Block_4_6(W_X); 
+        Rx_RORX_1( 6); Block_4_7(W_X); Rx_RORX_2( 6); 
+            Block_4_8(W_X); Rx_RORX_3( 6); Block_4_9();
+        Rx_RORX_1( 7); Block_4_10();Rx_RORX_2( 7); 
+            Block_4_11();Rx_RORX_3( 7); Block_4_12(W_X);   
+        
+        Rx_RORX_1( 8); Block_8_1(W_X); Rx_RORX_2( 8); 
+            Block_8_2(W_X); Rx_RORX_3( 8); Block_8_3(); 
+        Rx_RORX_1( 9); Block_8_4(); Rx_RORX_2( 9); 
+            Block_8_5(); Rx_RORX_3( 9); Block_8_6(W_X); 
+        Rx_RORX_1(10); Block_8_7(W_X); Rx_RORX_2(10); 
+            Block_8_8(W_X); Rx_RORX_3(10); Block_8_9();
+        Rx_RORX_1(11); Block_8_10();Rx_RORX_2(11); 
+            Block_8_11();Rx_RORX_3(11); Block_8_12(W_X);   
+        
+        Rx_RORX_1(12); Block_12_1(W_X); Rx_RORX_2(12);
+            Block_12_2(W_X); Rx_RORX_3(12); Block_12_3(); 
+        Rx_RORX_1(13); Block_12_4(); Rx_RORX_2(13); 
+            Block_12_5(); Rx_RORX_3(13); Block_12_6(W_X); 
+        Rx_RORX_1(14); Block_12_7(W_X); Rx_RORX_2(14); 
+            Block_12_8(W_X); Rx_RORX_3(14); Block_12_9();
+        Rx_RORX_1(15); Block_12_10();Rx_RORX_2(15); 
+            Block_12_11();Rx_RORX_3(15); Block_12_12(W_X);     
+    }
+
+    /* Add the working vars back into digest */
+
+    sha384->digest[0] += a(0);
+    sha384->digest[1] += b(0);
+    sha384->digest[2] += c(0);
+    sha384->digest[3] += d(0);
+    sha384->digest[4] += e(0);
+    sha384->digest[5] += f(0);
+    sha384->digest[6] += g(0);
+    sha384->digest[7] += h(0);
+
+    /* Wipe variables */
+    #if !defined(HAVE_INTEL_AVX1)&&!defined(HAVE_INTEL_AVX2)
+    XMEMSET(W, 0, sizeof(word64) * 16);
+    #endif
+    XMEMSET(T, 0, sizeof(T));
+
+    return 0;
+}
+#endif
+
+#if defined(HAVE_INTEL_AVX2)
+
+static int Transform384_AVX2(Sha384* sha384)
+{
+    const word64* K = K512;
+    word64 w[4] ;
+    word32 j;
+    word64 T[8];
+
+    /* Copy digest to working vars */
+    XMEMCPY(T, sha384->digest, sizeof(T));
+
+    /* over twice as small, but 50% slower */
+    /* 80 operations, not unrolled */
+
+    W_from_buff_Y(sha384->buffer) ;
+
+    MOVE_to_MEMy(w,0, W_0y) ;
+    for (j = 0; j < 80; j += 16) {
+        Ry_1( 0, w[0]); Block_Y_0_1(); Ry_2( 0, w[0]); 
+            Block_Y_0_2(); Ry_3( 0, w[0]); Block_Y_0_3(); 
+        Ry_1( 1, w[1]); Block_Y_0_4(); Ry_2( 1, w[1]); 
+            Block_Y_0_5(); Ry_3( 1, w[1]); Block_Y_0_6();  
+        Ry_1( 2, w[2]); Block_Y_0_7(); Ry_2( 2, w[2]); 
+            Block_Y_0_8(); Ry_3( 2, w[2]); Block_Y_0_9();
+        Ry_1( 3, w[3]); Block_Y_0_10();Ry_2( 3, w[3]); 
+            Block_Y_0_11();Ry_3( 3, w[3]); Block_Y_0_12(w);
+        
+        Ry_1( 4, w[0]); Block_Y_4_1(); Ry_2( 4, w[0]); 
+            Block_Y_4_2(); Ry_3( 4, w[0]); Block_Y_4_3(); 
+        Ry_1( 5, w[1]); Block_Y_4_4(); Ry_2( 5, w[1]);   
+            Block_Y_4_5(); Ry_3( 5, w[1]); Block_Y_4_6();
+        Ry_1( 6, w[2]); Block_Y_4_7(); Ry_2( 6, w[2]); 
+            Block_Y_4_8(); Ry_3( 6, w[2]); Block_Y_4_9();
+        Ry_1( 7, w[3]); Block_Y_4_10(); Ry_2( 7, w[3]);
+            Block_Y_4_11(); Ry_3( 7, w[3]);Block_Y_4_12(w);  
+        
+        Ry_1( 8, w[0]); Block_Y_8_1(); Ry_2( 8, w[0]); 
+            Block_Y_8_2(); Ry_3( 8, w[0]); Block_Y_8_3();
+        Ry_1( 9, w[1]); Block_Y_8_4(); Ry_2( 9, w[1]);
+            Block_Y_8_5(); Ry_3( 9, w[1]); Block_Y_8_6();
+        Ry_1(10, w[2]); Block_Y_8_7(); Ry_2(10, w[2]); 
+            Block_Y_8_8(); Ry_3(10, w[2]); Block_Y_8_9(); 
+        Ry_1(11, w[3]); Block_Y_8_10();Ry_2(11, w[3]); 
+           Block_Y_8_11();Ry_3(11, w[3]); Block_Y_8_12(w);
+                 
+        Ry_1(12, w[0]); Block_Y_12_1(); Ry_2(12, w[0]); 
+            Block_Y_12_2(); Ry_3(12, w[0]); Block_Y_12_3();
+        Ry_1(13, w[1]); Block_Y_12_4(); Ry_2(13, w[1]); 
+            Block_Y_12_5(); Ry_3(13, w[1]); Block_Y_12_6(); 
+        Ry_1(14, w[2]); Block_Y_12_7(); Ry_2(14, w[2]); 
+            Block_Y_12_8(); Ry_3(14, w[2]); Block_Y_12_9();
+        Ry_1(15, w[3]); Block_Y_12_10();Ry_2(15, w[3]); 
+            Block_Y_12_11();Ry_3(15, w[3]); Block_Y_12_12(w);
+    }
+
+    /* Add the working vars back into digest */
+
+    sha384->digest[0] += a(0);
+    sha384->digest[1] += b(0);
+    sha384->digest[2] += c(0);
+    sha384->digest[3] += d(0);
+    sha384->digest[4] += e(0);
+    sha384->digest[5] += f(0);
+    sha384->digest[6] += g(0);
+    sha384->digest[7] += h(0);
+
+    /* Wipe variables */
+    XMEMSET(T, 0, sizeof(T));
+
+    return 0;
+}
+
+#endif
+
+#endif /* WOLFSSL_SHA384 */
+
+#endif /* HAVE_FIPS */
+
+#endif /* WOLFSSL_SHA512 */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/tfm.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/tfm.c
new file mode 100644
index 0000000..2c1e86c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/tfm.c
@@ -0,0 +1,2701 @@
+/* tfm.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+/*
+ * Based on public domain TomsFastMath 0.10 by Tom St Denis, tomstdenis@iahu.ca,
+ * http://math.libtomcrypt.com
+ */
+
+/**
+ *  Edited by Moisés Guimarães (moisesguimaraesm@gmail.com)
+ *  to fit CyaSSL's needs.
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+/* in case user set USE_FAST_MATH there */
+#include 
+
+#ifdef USE_FAST_MATH
+
+#include 
+#include   /* will define asm MACROS or C ones */
+
+
+/* math settings check */
+word32 CheckRunTimeSettings(void)
+{
+    return CTC_SETTINGS;
+}
+
+
+/* math settings size check */
+word32 CheckRunTimeFastMath(void)
+{
+    return FP_SIZE;
+}
+
+
+/* Functions */
+
+void fp_add(fp_int *a, fp_int *b, fp_int *c)
+{
+  int     sa, sb;
+
+  /* get sign of both inputs */
+  sa = a->sign;
+  sb = b->sign;
+
+  /* handle two cases, not four */
+  if (sa == sb) {
+    /* both positive or both negative */
+    /* add their magnitudes, copy the sign */
+    c->sign = sa;
+    s_fp_add (a, b, c);
+  } else {
+    /* one positive, the other negative */
+    /* subtract the one with the greater magnitude from */
+    /* the one of the lesser magnitude.  The result gets */
+    /* the sign of the one with the greater magnitude. */
+    if (fp_cmp_mag (a, b) == FP_LT) {
+      c->sign = sb;
+      s_fp_sub (b, a, c);
+    } else {
+      c->sign = sa;
+      s_fp_sub (a, b, c);
+    }
+  }
+}
+
+/* unsigned addition */
+void s_fp_add(fp_int *a, fp_int *b, fp_int *c)
+{
+  int      x, y, oldused;
+  register fp_word  t;
+
+  y       = MAX(a->used, b->used);
+  oldused = MIN(c->used, FP_SIZE);   /* help static analysis w/ largest size */
+  c->used = y;
+ 
+  t = 0;
+  for (x = 0; x < y; x++) {
+      t         += ((fp_word)a->dp[x]) + ((fp_word)b->dp[x]);
+      c->dp[x]   = (fp_digit)t;
+      t        >>= DIGIT_BIT;
+  }
+  if (t != 0 && x < FP_SIZE) {
+     c->dp[c->used++] = (fp_digit)t;
+     ++x;
+  }
+
+  c->used = x;
+  for (; x < oldused; x++) {
+     c->dp[x] = 0;
+  }
+  fp_clamp(c);
+}
+
+/* c = a - b */
+void fp_sub(fp_int *a, fp_int *b, fp_int *c)
+{
+  int     sa, sb;
+
+  sa = a->sign;
+  sb = b->sign;
+
+  if (sa != sb) {
+    /* subtract a negative from a positive, OR */
+    /* subtract a positive from a negative. */
+    /* In either case, ADD their magnitudes, */
+    /* and use the sign of the first number. */
+    c->sign = sa;
+    s_fp_add (a, b, c);
+  } else {
+    /* subtract a positive from a positive, OR */
+    /* subtract a negative from a negative. */
+    /* First, take the difference between their */
+    /* magnitudes, then... */
+    if (fp_cmp_mag (a, b) != FP_LT) {
+      /* Copy the sign from the first */
+      c->sign = sa;
+      /* The first has a larger or equal magnitude */
+      s_fp_sub (a, b, c);
+    } else {
+      /* The result has the *opposite* sign from */
+      /* the first number. */
+      c->sign = (sa == FP_ZPOS) ? FP_NEG : FP_ZPOS;
+      /* The second has a larger magnitude */
+      s_fp_sub (b, a, c);
+    }
+  }
+}
+
+/* unsigned subtraction ||a|| >= ||b|| ALWAYS! */
+void s_fp_sub(fp_int *a, fp_int *b, fp_int *c)
+{
+  int      x, oldbused, oldused;
+  fp_word  t;
+
+  oldused  = c->used;
+  oldbused = b->used;
+  c->used  = a->used;
+  t       = 0;
+  for (x = 0; x < oldbused; x++) {
+     t         = ((fp_word)a->dp[x]) - (((fp_word)b->dp[x]) + t);
+     c->dp[x]  = (fp_digit)t;
+     t         = (t >> DIGIT_BIT)&1;
+  }
+  for (; x < a->used; x++) {
+     t         = ((fp_word)a->dp[x]) - t;
+     c->dp[x]  = (fp_digit)t;
+     t         = (t >> DIGIT_BIT)&1;
+   }
+  for (; x < oldused; x++) {
+     c->dp[x] = 0;
+  }
+  fp_clamp(c);
+}
+
+/* c = a * b */
+void fp_mul(fp_int *A, fp_int *B, fp_int *C)
+{
+    int   y, yy;
+
+    y  = MAX(A->used, B->used);
+    yy = MIN(A->used, B->used);
+
+    /* call generic if we're out of range */
+    if (y + yy > FP_SIZE) {
+       fp_mul_comba(A, B, C);
+       return ;
+    }
+
+    /* pick a comba (unrolled 4/8/16/32 x or rolled) based on the size
+       of the largest input.  We also want to avoid doing excess mults if the 
+       inputs are not close to the next power of two.  That is, for example,
+       if say y=17 then we would do (32-17)^2 = 225 unneeded multiplications 
+    */
+
+#ifdef TFM_MUL3
+        if (y <= 3) {
+           fp_mul_comba3(A,B,C);
+           return;
+        }
+#endif
+#ifdef TFM_MUL4
+        if (y == 4) {
+           fp_mul_comba4(A,B,C);
+           return;
+        }
+#endif
+#ifdef TFM_MUL6
+        if (y <= 6) {
+           fp_mul_comba6(A,B,C);
+           return;
+        }
+#endif
+#ifdef TFM_MUL7
+        if (y == 7) {
+           fp_mul_comba7(A,B,C);
+           return;
+        }
+#endif
+#ifdef TFM_MUL8
+        if (y == 8) {
+           fp_mul_comba8(A,B,C);
+           return;
+        }
+#endif
+#ifdef TFM_MUL9
+        if (y == 9) {
+           fp_mul_comba9(A,B,C);
+           return;
+        }
+#endif
+#ifdef TFM_MUL12
+        if (y <= 12) {
+           fp_mul_comba12(A,B,C);
+           return;
+        }
+#endif
+#ifdef TFM_MUL17
+        if (y <= 17) {
+           fp_mul_comba17(A,B,C);
+           return;
+        }
+#endif
+
+#ifdef TFM_SMALL_SET
+        if (y <= 16) {
+           fp_mul_comba_small(A,B,C);
+           return;
+        }
+#endif        
+#if defined(TFM_MUL20)
+        if (y <= 20) {
+           fp_mul_comba20(A,B,C);
+           return;
+        }
+#endif
+#if defined(TFM_MUL24)
+        if (yy >= 16 && y <= 24) {
+           fp_mul_comba24(A,B,C);
+           return;
+        }
+#endif
+#if defined(TFM_MUL28)
+        if (yy >= 20 && y <= 28) {
+           fp_mul_comba28(A,B,C);
+           return;
+        }
+#endif
+#if defined(TFM_MUL32)
+        if (yy >= 24 && y <= 32) {
+           fp_mul_comba32(A,B,C);
+           return;
+        }
+#endif
+#if defined(TFM_MUL48)
+        if (yy >= 40 && y <= 48) {
+           fp_mul_comba48(A,B,C);
+           return;
+        }
+#endif        
+#if defined(TFM_MUL64)
+        if (yy >= 56 && y <= 64) {
+           fp_mul_comba64(A,B,C);
+           return;
+        }
+#endif
+        fp_mul_comba(A,B,C);
+}
+
+void fp_mul_2(fp_int * a, fp_int * b)
+{
+  int     x, oldused;
+   
+  oldused = b->used;
+  b->used = a->used;
+
+  {
+    register fp_digit r, rr, *tmpa, *tmpb;
+
+    /* alias for source */
+    tmpa = a->dp;
+    
+    /* alias for dest */
+    tmpb = b->dp;
+
+    /* carry */
+    r = 0;
+    for (x = 0; x < a->used; x++) {
+    
+      /* get what will be the *next* carry bit from the 
+       * MSB of the current digit 
+       */
+      rr = *tmpa >> ((fp_digit)(DIGIT_BIT - 1));
+      
+      /* now shift up this digit, add in the carry [from the previous] */
+      *tmpb++ = ((*tmpa++ << ((fp_digit)1)) | r);
+      
+      /* copy the carry that would be from the source 
+       * digit into the next iteration 
+       */
+      r = rr;
+    }
+
+    /* new leading digit? */
+    if (r != 0 && b->used != (FP_SIZE-1)) {
+      /* add a MSB which is always 1 at this point */
+      *tmpb = 1;
+      ++(b->used);
+    }
+
+    /* now zero any excess digits on the destination 
+     * that we didn't write to 
+     */
+    tmpb = b->dp + b->used;
+    for (x = b->used; x < oldused; x++) {
+      *tmpb++ = 0;
+    }
+  }
+  b->sign = a->sign;
+}
+
+/* c = a * b */
+void fp_mul_d(fp_int *a, fp_digit b, fp_int *c)
+{
+   fp_word  w;
+   int      x, oldused;
+
+   oldused = c->used;
+   c->used = a->used;
+   c->sign = a->sign;
+   w       = 0;
+   for (x = 0; x < a->used; x++) {
+       w         = ((fp_word)a->dp[x]) * ((fp_word)b) + w;
+       c->dp[x]  = (fp_digit)w;
+       w         = w >> DIGIT_BIT;
+   }
+   if (w != 0 && (a->used != FP_SIZE)) {
+      c->dp[c->used++] = (fp_digit) w;
+      ++x;
+   }
+   for (; x < oldused; x++) {
+      c->dp[x] = 0;
+   }
+   fp_clamp(c);
+}
+
+/* c = a * 2**d */
+void fp_mul_2d(fp_int *a, int b, fp_int *c)
+{
+   fp_digit carry, carrytmp, shift;
+   int x;
+
+   /* copy it */
+   fp_copy(a, c);
+
+   /* handle whole digits */
+   if (b >= DIGIT_BIT) {
+      fp_lshd(c, b/DIGIT_BIT);
+   }
+   b %= DIGIT_BIT;
+
+   /* shift the digits */
+   if (b != 0) {
+      carry = 0;   
+      shift = DIGIT_BIT - b;
+      for (x = 0; x < c->used; x++) {
+          carrytmp = c->dp[x] >> shift;
+          c->dp[x] = (c->dp[x] << b) + carry;
+          carry = carrytmp;
+      }
+      /* store last carry if room */
+      if (carry && x < FP_SIZE) {
+         c->dp[c->used++] = carry;
+      }
+   }
+   fp_clamp(c);
+}
+
+/* generic PxQ multiplier */
+#if defined(HAVE_INTEL_MULX)
+
+INLINE static void fp_mul_comba_mulx(fp_int *A, fp_int *B, fp_int *C)
+
+{     
+   int       ix, iy, iz, pa;
+   fp_int    tmp, *dst;
+
+   /* get size of output and trim */
+   pa = A->used + B->used;
+   if (pa >= FP_SIZE) {
+      pa = FP_SIZE-1;
+   }
+ 
+   if (A == C || B == C) {
+      fp_init(&tmp);
+      dst = &tmp;
+   } else {
+      fp_zero(C);
+      dst = C;
+   }
+
+   TFM_INTEL_MUL_COMBA(A, B, dst) ;
+
+  dst->used = pa;
+  dst->sign = A->sign ^ B->sign;
+  fp_clamp(dst);
+  fp_copy(dst, C);  
+}
+#endif
+
+void fp_mul_comba(fp_int *A, fp_int *B, fp_int *C)
+{
+   int       ix, iy, iz, tx, ty, pa;
+   fp_digit  c0, c1, c2, *tmpx, *tmpy;
+   fp_int    tmp, *dst;
+
+   IF_HAVE_INTEL_MULX(fp_mul_comba_mulx(A, B, C), return) ;
+
+   COMBA_START;
+   COMBA_CLEAR;
+   
+   /* get size of output and trim */
+   pa = A->used + B->used;
+   if (pa >= FP_SIZE) {
+      pa = FP_SIZE-1;
+   }
+
+   if (A == C || B == C) {
+      fp_init(&tmp);
+      dst = &tmp;
+   } else {
+      fp_zero(C);
+      dst = C;
+   }
+
+   for (ix = 0; ix < pa; ix++) {
+      /* get offsets into the two bignums */
+      ty = MIN(ix, B->used-1);
+      tx = ix - ty;
+
+      /* setup temp aliases */
+      tmpx = A->dp + tx;
+      tmpy = B->dp + ty;
+
+      /* this is the number of times the loop will iterrate, essentially its 
+         while (tx++ < a->used && ty-- >= 0) { ... }
+       */
+      iy = MIN(A->used-tx, ty+1);
+
+      /* execute loop */
+      COMBA_FORWARD;
+      for (iz = 0; iz < iy; ++iz) {
+          /* TAO change COMBA_ADD back to MULADD */
+          MULADD(*tmpx++, *tmpy--);
+      }
+
+      /* store term */
+      COMBA_STORE(dst->dp[ix]);
+  }
+  COMBA_FINI;
+
+  dst->used = pa;
+  dst->sign = A->sign ^ B->sign;
+  fp_clamp(dst);
+  fp_copy(dst, C);
+}
+
+/* a/b => cb + d == a */
+int fp_div(fp_int *a, fp_int *b, fp_int *c, fp_int *d)
+{
+  fp_int  q, x, y, t1, t2;
+  int     n, t, i, norm, neg;
+
+  /* is divisor zero ? */
+  if (fp_iszero (b) == 1) {
+    return FP_VAL;
+  }
+
+  /* if a < b then q=0, r = a */
+  if (fp_cmp_mag (a, b) == FP_LT) {
+    if (d != NULL) {
+      fp_copy (a, d);
+    } 
+    if (c != NULL) {
+      fp_zero (c);
+    }
+    return FP_OKAY;
+  }
+
+  fp_init(&q);
+  q.used = a->used + 2;
+
+  fp_init(&t1);
+  fp_init(&t2);
+  fp_init_copy(&x, a);
+  fp_init_copy(&y, b);
+
+  /* fix the sign */
+  neg = (a->sign == b->sign) ? FP_ZPOS : FP_NEG;
+  x.sign = y.sign = FP_ZPOS;
+
+  /* normalize both x and y, ensure that y >= b/2, [b == 2**DIGIT_BIT] */
+  norm = fp_count_bits(&y) % DIGIT_BIT;
+  if (norm < (int)(DIGIT_BIT-1)) {
+     norm = (DIGIT_BIT-1) - norm;
+     fp_mul_2d (&x, norm, &x);
+     fp_mul_2d (&y, norm, &y);
+  } else {
+     norm = 0;
+  }
+
+  /* note hac does 0 based, so if used==5 then its 0,1,2,3,4, e.g. use 4 */
+  n = x.used - 1;
+  t = y.used - 1;
+
+  /* while (x >= y*b**n-t) do { q[n-t] += 1; x -= y*b**{n-t} } */
+  fp_lshd (&y, n - t);                                             /* y = y*b**{n-t} */
+
+  while (fp_cmp (&x, &y) != FP_LT) {
+    ++(q.dp[n - t]);
+    fp_sub (&x, &y, &x);
+  }
+
+  /* reset y by shifting it back down */
+  fp_rshd (&y, n - t);
+
+  /* step 3. for i from n down to (t + 1) */
+  for (i = n; i >= (t + 1); i--) {
+    if (i > x.used) {
+      continue;
+    }
+
+    /* step 3.1 if xi == yt then set q{i-t-1} to b-1, 
+     * otherwise set q{i-t-1} to (xi*b + x{i-1})/yt */
+    if (x.dp[i] == y.dp[t]) {
+      q.dp[i - t - 1] = (fp_digit) ((((fp_word)1) << DIGIT_BIT) - 1);
+    } else {
+      fp_word tmp;
+      tmp = ((fp_word) x.dp[i]) << ((fp_word) DIGIT_BIT);
+      tmp |= ((fp_word) x.dp[i - 1]);
+      tmp /= ((fp_word)y.dp[t]);
+      q.dp[i - t - 1] = (fp_digit) (tmp);
+    }
+
+    /* while (q{i-t-1} * (yt * b + y{t-1})) > 
+             xi * b**2 + xi-1 * b + xi-2 
+     
+       do q{i-t-1} -= 1; 
+    */
+    q.dp[i - t - 1] = (q.dp[i - t - 1] + 1);
+    do {
+      q.dp[i - t - 1] = (q.dp[i - t - 1] - 1);
+
+      /* find left hand */
+      fp_zero (&t1);
+      t1.dp[0] = (t - 1 < 0) ? 0 : y.dp[t - 1];
+      t1.dp[1] = y.dp[t];
+      t1.used = 2;
+      fp_mul_d (&t1, q.dp[i - t - 1], &t1);
+
+      /* find right hand */
+      t2.dp[0] = (i - 2 < 0) ? 0 : x.dp[i - 2];
+      t2.dp[1] = (i - 1 < 0) ? 0 : x.dp[i - 1];
+      t2.dp[2] = x.dp[i];
+      t2.used = 3;
+    } while (fp_cmp_mag(&t1, &t2) == FP_GT);
+
+    /* step 3.3 x = x - q{i-t-1} * y * b**{i-t-1} */
+    fp_mul_d (&y, q.dp[i - t - 1], &t1);
+    fp_lshd  (&t1, i - t - 1);
+    fp_sub   (&x, &t1, &x);
+
+    /* if x < 0 then { x = x + y*b**{i-t-1}; q{i-t-1} -= 1; } */
+    if (x.sign == FP_NEG) {
+      fp_copy (&y, &t1);
+      fp_lshd (&t1, i - t - 1);
+      fp_add (&x, &t1, &x);
+      q.dp[i - t - 1] = q.dp[i - t - 1] - 1;
+    }
+  }
+
+  /* now q is the quotient and x is the remainder 
+   * [which we have to normalize] 
+   */
+  
+  /* get sign before writing to c */
+  x.sign = x.used == 0 ? FP_ZPOS : a->sign;
+
+  if (c != NULL) {
+    fp_clamp (&q);
+    fp_copy (&q, c);
+    c->sign = neg;
+  }
+
+  if (d != NULL) {
+    fp_div_2d (&x, norm, &x, NULL);
+
+/* the following is a kludge, essentially we were seeing the right remainder but 
+   with excess digits that should have been zero
+ */
+    for (i = b->used; i < x.used; i++) {
+        x.dp[i] = 0;
+    }
+    fp_clamp(&x);
+    fp_copy (&x, d);
+  }
+
+  return FP_OKAY;
+}
+
+/* b = a/2 */
+void fp_div_2(fp_int * a, fp_int * b)
+{
+  int     x, oldused;
+
+  oldused = b->used;
+  b->used = a->used;
+  {
+    register fp_digit r, rr, *tmpa, *tmpb;
+
+    /* source alias */
+    tmpa = a->dp + b->used - 1;
+
+    /* dest alias */
+    tmpb = b->dp + b->used - 1;
+
+    /* carry */
+    r = 0;
+    for (x = b->used - 1; x >= 0; x--) {
+      /* get the carry for the next iteration */
+      rr = *tmpa & 1;
+
+      /* shift the current digit, add in carry and store */
+      *tmpb-- = (*tmpa-- >> 1) | (r << (DIGIT_BIT - 1));
+
+      /* forward carry to next iteration */
+      r = rr;
+    }
+
+    /* zero excess digits */
+    tmpb = b->dp + b->used;
+    for (x = b->used; x < oldused; x++) {
+      *tmpb++ = 0;
+    }
+  }
+  b->sign = a->sign;
+  fp_clamp (b);
+}
+
+/* c = a / 2**b */
+void fp_div_2d(fp_int *a, int b, fp_int *c, fp_int *d)
+{
+  int      D;
+  fp_int   t;
+
+  /* if the shift count is <= 0 then we do no work */
+  if (b <= 0) {
+    fp_copy (a, c);
+    if (d != NULL) {
+      fp_zero (d);
+    }
+    return;
+  }
+
+  fp_init(&t);
+
+  /* get the remainder */
+  if (d != NULL) {
+    fp_mod_2d (a, b, &t);
+  }
+
+  /* copy */
+  fp_copy(a, c);
+
+  /* shift by as many digits in the bit count */
+  if (b >= (int)DIGIT_BIT) {
+    fp_rshd (c, b / DIGIT_BIT);
+  }
+
+  /* shift any bit count < DIGIT_BIT */
+  D = (b % DIGIT_BIT);
+  if (D != 0) {
+    fp_rshb(c, D);
+  }
+  fp_clamp (c);
+  if (d != NULL) {
+    fp_copy (&t, d);
+  }
+}
+
+/* c = a mod b, 0 <= c < b  */
+int fp_mod(fp_int *a, fp_int *b, fp_int *c)
+{
+   fp_int t;
+   int    err;
+
+   fp_init(&t);
+   if ((err = fp_div(a, b, NULL, &t)) != FP_OKAY) {
+      return err;
+   }
+   if (t.sign != b->sign) {
+      fp_add(&t, b, c);
+   } else {
+      fp_copy(&t, c);
+  }
+  return FP_OKAY;
+}
+
+/* c = a mod 2**d */
+void fp_mod_2d(fp_int *a, int b, fp_int *c)
+{
+   int x;
+
+   /* zero if count less than or equal to zero */
+   if (b <= 0) {
+      fp_zero(c);
+      return;
+   }
+
+   /* get copy of input */
+   fp_copy(a, c);
+ 
+   /* if 2**d is larger than we just return */
+   if (b >= (DIGIT_BIT * a->used)) {
+      return;
+   }
+
+  /* zero digits above the last digit of the modulus */
+  for (x = (b / DIGIT_BIT) + ((b % DIGIT_BIT) == 0 ? 0 : 1); x < c->used; x++) {
+    c->dp[x] = 0;
+  }
+  /* clear the digit that is not completely outside/inside the modulus */
+  c->dp[b / DIGIT_BIT] &= ~((fp_digit)0) >> (DIGIT_BIT - b);
+  fp_clamp (c);
+}
+
+static int fp_invmod_slow (fp_int * a, fp_int * b, fp_int * c)
+{
+  fp_int  x, y, u, v, A, B, C, D;
+  int     res;
+
+  /* b cannot be negative */
+  if (b->sign == FP_NEG || fp_iszero(b) == 1) {
+    return FP_VAL;
+  }
+
+  /* init temps */
+  fp_init(&x);    fp_init(&y);
+  fp_init(&u);    fp_init(&v);
+  fp_init(&A);    fp_init(&B);
+  fp_init(&C);    fp_init(&D);
+
+  /* x = a, y = b */
+  if ((res = fp_mod(a, b, &x)) != FP_OKAY) {
+      return res;
+  }
+  fp_copy(b, &y);
+
+  /* 2. [modified] if x,y are both even then return an error! */
+  if (fp_iseven (&x) == 1 && fp_iseven (&y) == 1) {
+    return FP_VAL;
+  }
+
+  /* 3. u=x, v=y, A=1, B=0, C=0,D=1 */
+  fp_copy (&x, &u);
+  fp_copy (&y, &v);
+  fp_set (&A, 1);
+  fp_set (&D, 1);
+
+top:
+  /* 4.  while u is even do */
+  while (fp_iseven (&u) == 1) {
+    /* 4.1 u = u/2 */
+    fp_div_2 (&u, &u);
+
+    /* 4.2 if A or B is odd then */
+    if (fp_isodd (&A) == 1 || fp_isodd (&B) == 1) {
+      /* A = (A+y)/2, B = (B-x)/2 */
+      fp_add (&A, &y, &A);
+      fp_sub (&B, &x, &B);
+    }
+    /* A = A/2, B = B/2 */
+    fp_div_2 (&A, &A);
+    fp_div_2 (&B, &B);
+  }
+
+  /* 5.  while v is even do */
+  while (fp_iseven (&v) == 1) {
+    /* 5.1 v = v/2 */
+    fp_div_2 (&v, &v);
+
+    /* 5.2 if C or D is odd then */
+    if (fp_isodd (&C) == 1 || fp_isodd (&D) == 1) {
+      /* C = (C+y)/2, D = (D-x)/2 */
+      fp_add (&C, &y, &C);
+      fp_sub (&D, &x, &D);
+    }
+    /* C = C/2, D = D/2 */
+    fp_div_2 (&C, &C);
+    fp_div_2 (&D, &D);
+  }
+
+  /* 6.  if u >= v then */
+  if (fp_cmp (&u, &v) != FP_LT) {
+    /* u = u - v, A = A - C, B = B - D */
+    fp_sub (&u, &v, &u);
+    fp_sub (&A, &C, &A);
+    fp_sub (&B, &D, &B);
+  } else {
+    /* v - v - u, C = C - A, D = D - B */
+    fp_sub (&v, &u, &v);
+    fp_sub (&C, &A, &C);
+    fp_sub (&D, &B, &D);
+  }
+
+  /* if not zero goto step 4 */
+  if (fp_iszero (&u) == 0)
+    goto top;
+
+  /* now a = C, b = D, gcd == g*v */
+
+  /* if v != 1 then there is no inverse */
+  if (fp_cmp_d (&v, 1) != FP_EQ) {
+    return FP_VAL;
+  }
+
+  /* if its too low */
+  while (fp_cmp_d(&C, 0) == FP_LT) {
+      fp_add(&C, b, &C);
+  }
+  
+  /* too big */
+  while (fp_cmp_mag(&C, b) != FP_LT) {
+      fp_sub(&C, b, &C);
+  }
+  
+  /* C is now the inverse */
+  fp_copy(&C, c);
+  return FP_OKAY;
+}
+
+
+/* c = 1/a (mod b) for odd b only */
+int fp_invmod(fp_int *a, fp_int *b, fp_int *c)
+{
+  fp_int  x, y, u, v, B, D;
+  int     neg, loop_check = 0;
+
+  /* 2. [modified] b must be odd   */
+  if (fp_iseven (b) == FP_YES) {
+    return fp_invmod_slow(a,b,c);
+  }
+
+  /* init all our temps */
+  fp_init(&x);  fp_init(&y);
+  fp_init(&u);  fp_init(&v);
+  fp_init(&B);  fp_init(&D);
+
+  /* x == modulus, y == value to invert */
+  fp_copy(b, &x);
+
+  /* we need y = |a| */
+  fp_abs(a, &y);
+
+  /* 3. u=x, v=y, A=1, B=0, C=0,D=1 */
+  fp_copy(&x, &u);
+  fp_copy(&y, &v);
+  fp_set (&D, 1);
+
+top:
+  /* 4.  while u is even do */
+  while (fp_iseven (&u) == FP_YES) {
+    /* 4.1 u = u/2 */
+    fp_div_2 (&u, &u);
+
+    /* 4.2 if B is odd then */
+    if (fp_isodd (&B) == FP_YES) {
+      fp_sub (&B, &x, &B);
+    }
+    /* B = B/2 */
+    fp_div_2 (&B, &B);
+  }
+
+  /* 5.  while v is even do */
+  while (fp_iseven (&v) == FP_YES) {
+    /* 5.1 v = v/2 */
+    fp_div_2 (&v, &v);
+
+    /* 5.2 if D is odd then */
+    if (fp_isodd (&D) == FP_YES) {
+      /* D = (D-x)/2 */
+      fp_sub (&D, &x, &D);
+    }
+    /* D = D/2 */
+    fp_div_2 (&D, &D);
+  }
+
+  /* 6.  if u >= v then */
+  if (fp_cmp (&u, &v) != FP_LT) {
+    /* u = u - v, B = B - D */
+    fp_sub (&u, &v, &u);
+    fp_sub (&B, &D, &B);
+  } else {
+    /* v - v - u, D = D - B */
+    fp_sub (&v, &u, &v);
+    fp_sub (&D, &B, &D);
+  }
+
+  /* if not zero goto step 4 */
+  if (fp_iszero (&u) == FP_NO) {
+    if (++loop_check > 1024) /* bad input */
+      return FP_VAL;
+    goto top;
+  }
+
+  /* now a = C, b = D, gcd == g*v */
+
+  /* if v != 1 then there is no inverse */
+  if (fp_cmp_d (&v, 1) != FP_EQ) {
+    return FP_VAL;
+  }
+
+  /* b is now the inverse */
+  neg = a->sign;
+  while (D.sign == FP_NEG) {
+    fp_add (&D, b, &D);
+  }
+  fp_copy (&D, c);
+  c->sign = neg;
+  return FP_OKAY;
+}
+
+/* d = a * b (mod c) */
+int fp_mulmod(fp_int *a, fp_int *b, fp_int *c, fp_int *d)
+{
+  fp_int tmp;
+  fp_init(&tmp);
+  fp_mul(a, b, &tmp);
+  return fp_mod(&tmp, c, d);
+}
+
+#ifdef TFM_TIMING_RESISTANT
+
+/* timing resistant montgomery ladder based exptmod 
+
+   Based on work by Marc Joye, Sung-Ming Yen, "The Montgomery Powering Ladder", Cryptographic Hardware and Embedded Systems, CHES 2002
+*/
+static int _fp_exptmod(fp_int * G, fp_int * X, fp_int * P, fp_int * Y)
+{
+  fp_int   R[2];
+  fp_digit buf, mp;
+  int      err, bitcnt, digidx, y;
+
+  /* now setup montgomery  */
+  if ((err = fp_montgomery_setup (P, &mp)) != FP_OKAY) {
+     return err;
+  }
+
+  fp_init(&R[0]);   
+  fp_init(&R[1]);   
+   
+  /* now we need R mod m */
+  fp_montgomery_calc_normalization (&R[0], P);
+
+  /* now set R[0][1] to G * R mod m */
+  if (fp_cmp_mag(P, G) != FP_GT) {
+     /* G > P so we reduce it first */
+     fp_mod(G, P, &R[1]);
+  } else {
+     fp_copy(G, &R[1]);
+  }
+  fp_mulmod (&R[1], &R[0], P, &R[1]);
+
+  /* for j = t-1 downto 0 do
+        r_!k = R0*R1; r_k = r_k^2
+  */
+  
+  /* set initial mode and bit cnt */
+  bitcnt = 1;
+  buf    = 0;
+  digidx = X->used - 1;
+
+  for (;;) {
+    /* grab next digit as required */
+    if (--bitcnt == 0) {
+      /* if digidx == -1 we are out of digits so break */
+      if (digidx == -1) {
+        break;
+      }
+      /* read next digit and reset bitcnt */
+      buf    = X->dp[digidx--];
+      bitcnt = (int)DIGIT_BIT;
+    }
+
+    /* grab the next msb from the exponent */
+    y     = (int)(buf >> (DIGIT_BIT - 1)) & 1;
+    buf <<= (fp_digit)1;
+
+    /* do ops */
+    fp_mul(&R[0], &R[1], &R[y^1]); fp_montgomery_reduce(&R[y^1], P, mp);
+    fp_sqr(&R[y], &R[y]);          fp_montgomery_reduce(&R[y], P, mp);
+  }
+
+   fp_montgomery_reduce(&R[0], P, mp);
+   fp_copy(&R[0], Y);
+   return FP_OKAY;
+}   
+
+#else
+
+/* y = g**x (mod b) 
+ * Some restrictions... x must be positive and < b
+ */
+static int _fp_exptmod(fp_int * G, fp_int * X, fp_int * P, fp_int * Y)
+{
+  fp_int   M[64], res;
+  fp_digit buf, mp;
+  int      err, bitbuf, bitcpy, bitcnt, mode, digidx, x, y, winsize;
+
+  /* find window size */
+  x = fp_count_bits (X);
+  if (x <= 21) {
+    winsize = 1;
+  } else if (x <= 36) {
+    winsize = 3;
+  } else if (x <= 140) {
+    winsize = 4;
+  } else if (x <= 450) {
+    winsize = 5;
+  } else {
+    winsize = 6;
+  } 
+
+  /* init M array */
+  XMEMSET(M, 0, sizeof(M)); 
+
+  /* now setup montgomery  */
+  if ((err = fp_montgomery_setup (P, &mp)) != FP_OKAY) {
+     return err;
+  }
+
+  /* setup result */
+  fp_init(&res);
+
+  /* create M table
+   *
+   * The M table contains powers of the input base, e.g. M[x] = G^x mod P
+   *
+   * The first half of the table is not computed though accept for M[0] and M[1]
+   */
+
+   /* now we need R mod m */
+   fp_montgomery_calc_normalization (&res, P);
+
+   /* now set M[1] to G * R mod m */
+   if (fp_cmp_mag(P, G) != FP_GT) {
+      /* G > P so we reduce it first */
+      fp_mod(G, P, &M[1]);
+   } else {
+      fp_copy(G, &M[1]);
+   }
+   fp_mulmod (&M[1], &res, P, &M[1]);
+
+  /* compute the value at M[1<<(winsize-1)] by squaring M[1] (winsize-1) times */
+  fp_copy (&M[1], &M[1 << (winsize - 1)]);
+  for (x = 0; x < (winsize - 1); x++) {
+    fp_sqr (&M[1 << (winsize - 1)], &M[1 << (winsize - 1)]);
+    fp_montgomery_reduce (&M[1 << (winsize - 1)], P, mp);
+  }
+
+  /* create upper table */
+  for (x = (1 << (winsize - 1)) + 1; x < (1 << winsize); x++) {
+    fp_mul(&M[x - 1], &M[1], &M[x]);
+    fp_montgomery_reduce(&M[x], P, mp);
+  }
+
+  /* set initial mode and bit cnt */
+  mode   = 0;
+  bitcnt = 1;
+  buf    = 0;
+  digidx = X->used - 1;
+  bitcpy = 0;
+  bitbuf = 0;
+
+  for (;;) {
+    /* grab next digit as required */
+    if (--bitcnt == 0) {
+      /* if digidx == -1 we are out of digits so break */
+      if (digidx == -1) {
+        break;
+      }
+      /* read next digit and reset bitcnt */
+      buf    = X->dp[digidx--];
+      bitcnt = (int)DIGIT_BIT;
+    }
+
+    /* grab the next msb from the exponent */
+    y     = (int)(buf >> (DIGIT_BIT - 1)) & 1;
+    buf <<= (fp_digit)1;
+
+    /* if the bit is zero and mode == 0 then we ignore it
+     * These represent the leading zero bits before the first 1 bit
+     * in the exponent.  Technically this opt is not required but it
+     * does lower the # of trivial squaring/reductions used
+     */
+    if (mode == 0 && y == 0) {
+      continue;
+    }
+
+    /* if the bit is zero and mode == 1 then we square */
+    if (mode == 1 && y == 0) {
+      fp_sqr(&res, &res);
+      fp_montgomery_reduce(&res, P, mp);
+      continue;
+    }
+
+    /* else we add it to the window */
+    bitbuf |= (y << (winsize - ++bitcpy));
+    mode    = 2;
+
+    if (bitcpy == winsize) {
+      /* ok window is filled so square as required and multiply  */
+      /* square first */
+      for (x = 0; x < winsize; x++) {
+        fp_sqr(&res, &res);
+        fp_montgomery_reduce(&res, P, mp);
+      }
+
+      /* then multiply */
+      fp_mul(&res, &M[bitbuf], &res);
+      fp_montgomery_reduce(&res, P, mp);
+
+      /* empty window and reset */
+      bitcpy = 0;
+      bitbuf = 0;
+      mode   = 1;
+    }
+  }
+
+  /* if bits remain then square/multiply */
+  if (mode == 2 && bitcpy > 0) {
+    /* square then multiply if the bit is set */
+    for (x = 0; x < bitcpy; x++) {
+      fp_sqr(&res, &res);
+      fp_montgomery_reduce(&res, P, mp);
+
+      /* get next bit of the window */
+      bitbuf <<= 1;
+      if ((bitbuf & (1 << winsize)) != 0) {
+        /* then multiply */
+        fp_mul(&res, &M[1], &res);
+        fp_montgomery_reduce(&res, P, mp);
+      }
+    }
+  }
+
+  /* fixup result if Montgomery reduction is used
+   * recall that any value in a Montgomery system is
+   * actually multiplied by R mod n.  So we have
+   * to reduce one more time to cancel out the factor
+   * of R.
+   */
+  fp_montgomery_reduce(&res, P, mp);
+
+  /* swap res with Y */
+  fp_copy (&res, Y);
+  return FP_OKAY;
+}
+
+#endif
+
+int fp_exptmod(fp_int * G, fp_int * X, fp_int * P, fp_int * Y)
+{
+   /* prevent overflows */
+   if (P->used > (FP_SIZE/2)) {
+      return FP_VAL;
+   }
+
+   if (X->sign == FP_NEG) {
+#ifndef POSITIVE_EXP_ONLY  /* reduce stack if assume no negatives */
+      int    err;
+      fp_int tmp;
+
+      /* yes, copy G and invmod it */
+      fp_copy(G, &tmp);
+      if ((err = fp_invmod(&tmp, P, &tmp)) != FP_OKAY) {
+         return err;
+      }
+      X->sign = FP_ZPOS;
+      err =  _fp_exptmod(&tmp, X, P, Y);
+      if (X != Y) {
+         X->sign = FP_NEG;
+      }
+      return err;
+#else
+      return FP_VAL;
+#endif 
+   }
+   else {
+      /* Positive exponent so just exptmod */
+      return _fp_exptmod(G, X, P, Y);
+   }
+}
+
+/* computes a = 2**b */
+void fp_2expt(fp_int *a, int b)
+{
+   int     z;
+
+   /* zero a as per default */
+   fp_zero (a);
+
+   if (b < 0) { 
+      return;
+   }
+
+   z = b / DIGIT_BIT;
+   if (z >= FP_SIZE) {
+      return; 
+   }
+
+  /* set the used count of where the bit will go */
+  a->used = z + 1;
+
+  /* put the single bit in its place */
+  a->dp[z] = ((fp_digit)1) << (b % DIGIT_BIT);
+}
+
+/* b = a*a  */
+void fp_sqr(fp_int *A, fp_int *B)
+{
+    int y = A->used;
+
+    /* call generic if we're out of range */
+    if (y + y > FP_SIZE) {
+       fp_sqr_comba(A, B);
+       return ;
+    }
+
+#if defined(TFM_SQR3)
+        if (y <= 3) {
+           fp_sqr_comba3(A,B);
+           return;
+        }
+#endif
+#if defined(TFM_SQR4)
+        if (y == 4) {
+           fp_sqr_comba4(A,B);
+           return;
+        }
+#endif
+#if defined(TFM_SQR6)
+        if (y <= 6) {
+           fp_sqr_comba6(A,B);
+           return;
+        }
+#endif
+#if defined(TFM_SQR7)
+        if (y == 7) {
+           fp_sqr_comba7(A,B);
+           return;
+        }
+#endif
+#if defined(TFM_SQR8)
+        if (y == 8) {
+           fp_sqr_comba8(A,B);
+           return;
+        }
+#endif
+#if defined(TFM_SQR9)
+        if (y == 9) {
+           fp_sqr_comba9(A,B);
+           return;
+        }
+#endif
+#if defined(TFM_SQR12)
+        if (y <= 12) {
+           fp_sqr_comba12(A,B);
+           return;
+        }
+#endif
+#if defined(TFM_SQR17)
+        if (y <= 17) {
+           fp_sqr_comba17(A,B);
+           return;
+        }
+#endif
+#if defined(TFM_SMALL_SET)
+        if (y <= 16) {
+           fp_sqr_comba_small(A,B);
+           return;
+        }
+#endif
+#if defined(TFM_SQR20)
+        if (y <= 20) {
+           fp_sqr_comba20(A,B);
+           return;
+        }
+#endif
+#if defined(TFM_SQR24)
+        if (y <= 24) {
+           fp_sqr_comba24(A,B);
+           return;
+        }
+#endif
+#if defined(TFM_SQR28)
+        if (y <= 28) {
+           fp_sqr_comba28(A,B);
+           return;
+        }
+#endif
+#if defined(TFM_SQR32)
+        if (y <= 32) {
+           fp_sqr_comba32(A,B);
+           return;
+        }
+#endif
+#if defined(TFM_SQR48)
+        if (y <= 48) {
+           fp_sqr_comba48(A,B);
+           return;
+        }
+#endif
+#if defined(TFM_SQR64)
+        if (y <= 64) {
+           fp_sqr_comba64(A,B);
+           return;
+        }
+#endif
+       fp_sqr_comba(A, B);
+}
+
+/* generic comba squarer */
+void fp_sqr_comba(fp_int *A, fp_int *B)
+{
+  int       pa, ix, iz;
+  fp_digit  c0, c1, c2;
+  fp_int    tmp, *dst;
+#ifdef TFM_ISO
+  fp_word   tt;
+#endif    
+
+  /* get size of output and trim */
+  pa = A->used + A->used;
+  if (pa >= FP_SIZE) {
+     pa = FP_SIZE-1;
+  }
+
+  /* number of output digits to produce */
+  COMBA_START;
+  COMBA_CLEAR;
+
+  if (A == B) {
+     fp_init(&tmp);
+     dst = &tmp;
+  } else {
+     fp_zero(B);
+     dst = B;
+  }
+
+  for (ix = 0; ix < pa; ix++) { 
+      int      tx, ty, iy;
+      fp_digit *tmpy, *tmpx;
+
+      /* get offsets into the two bignums */
+      ty = MIN(A->used-1, ix);
+      tx = ix - ty;
+
+      /* setup temp aliases */
+      tmpx = A->dp + tx;
+      tmpy = A->dp + ty;
+
+      /* this is the number of times the loop will iterrate,
+         while (tx++ < a->used && ty-- >= 0) { ... }
+       */
+      iy = MIN(A->used-tx, ty+1);
+
+      /* now for squaring tx can never equal ty 
+       * we halve the distance since they approach 
+       * at a rate of 2x and we have to round because 
+       * odd cases need to be executed
+       */
+      iy = MIN(iy, (ty-tx+1)>>1);
+
+      /* forward carries */
+      COMBA_FORWARD;
+
+      /* execute loop */
+      for (iz = 0; iz < iy; iz++) {
+          SQRADD2(*tmpx++, *tmpy--);
+      }
+
+      /* even columns have the square term in them */
+      if ((ix&1) == 0) {
+          /* TAO change COMBA_ADD back to SQRADD */
+          SQRADD(A->dp[ix>>1], A->dp[ix>>1]);
+      }
+
+      /* store it */
+      COMBA_STORE(dst->dp[ix]);
+  }
+
+  COMBA_FINI;
+
+  /* setup dest */
+  dst->used = pa;
+  fp_clamp (dst);
+  if (dst != B) {
+     fp_copy(dst, B);
+  }
+}
+
+int fp_cmp(fp_int *a, fp_int *b)
+{
+   if (a->sign == FP_NEG && b->sign == FP_ZPOS) {
+      return FP_LT;
+   } else if (a->sign == FP_ZPOS && b->sign == FP_NEG) {
+      return FP_GT;
+   } else {
+      /* compare digits */
+      if (a->sign == FP_NEG) {
+         /* if negative compare opposite direction */
+         return fp_cmp_mag(b, a);
+      } else {
+         return fp_cmp_mag(a, b);
+      }
+   }
+}
+
+/* compare against a single digit */
+int fp_cmp_d(fp_int *a, fp_digit b)
+{
+  /* compare based on sign */
+  if ((b && a->used == 0) || a->sign == FP_NEG) {
+    return FP_LT;
+  }
+
+  /* compare based on magnitude */
+  if (a->used > 1) {
+    return FP_GT;
+  }
+
+  /* compare the only digit of a to b */
+  if (a->dp[0] > b) {
+    return FP_GT;
+  } else if (a->dp[0] < b) {
+    return FP_LT;
+  } else {
+    return FP_EQ;
+  }
+
+}
+
+int fp_cmp_mag(fp_int *a, fp_int *b)
+{
+   int x;
+
+   if (a->used > b->used) {
+      return FP_GT;
+   } else if (a->used < b->used) {
+      return FP_LT;
+   } else {
+      for (x = a->used - 1; x >= 0; x--) {
+          if (a->dp[x] > b->dp[x]) {
+             return FP_GT;
+          } else if (a->dp[x] < b->dp[x]) {
+             return FP_LT;
+          }
+      }
+   }
+   return FP_EQ;
+}
+
+/* setups the montgomery reduction */
+int fp_montgomery_setup(fp_int *a, fp_digit *rho)
+{
+  fp_digit x, b;
+
+/* fast inversion mod 2**k
+ *
+ * Based on the fact that
+ *
+ * XA = 1 (mod 2**n)  =>  (X(2-XA)) A = 1 (mod 2**2n)
+ *                    =>  2*X*A - X*X*A*A = 1
+ *                    =>  2*(1) - (1)     = 1
+ */
+  b = a->dp[0];
+
+  if ((b & 1) == 0) {
+    return FP_VAL;
+  }
+
+  x = (((b + 2) & 4) << 1) + b; /* here x*a==1 mod 2**4 */
+  x *= 2 - b * x;               /* here x*a==1 mod 2**8 */
+  x *= 2 - b * x;               /* here x*a==1 mod 2**16 */
+  x *= 2 - b * x;               /* here x*a==1 mod 2**32 */
+#ifdef FP_64BIT
+  x *= 2 - b * x;               /* here x*a==1 mod 2**64 */
+#endif
+
+  /* rho = -1/m mod b */
+  *rho = (fp_digit) (((fp_word) 1 << ((fp_word) DIGIT_BIT)) - ((fp_word)x));
+
+  return FP_OKAY;
+}
+
+/* computes a = B**n mod b without division or multiplication useful for
+ * normalizing numbers in a Montgomery system.
+ */
+void fp_montgomery_calc_normalization(fp_int *a, fp_int *b)
+{
+  int     x, bits;
+
+  /* how many bits of last digit does b use */
+  bits = fp_count_bits (b) % DIGIT_BIT;
+  if (!bits) bits = DIGIT_BIT;
+
+  /* compute A = B^(n-1) * 2^(bits-1) */
+  if (b->used > 1) {
+     fp_2expt (a, (b->used - 1) * DIGIT_BIT + bits - 1);
+  } else {
+     fp_set(a, 1);
+     bits = 1;
+  }
+
+  /* now compute C = A * B mod b */
+  for (x = bits - 1; x < (int)DIGIT_BIT; x++) {
+    fp_mul_2 (a, a);
+    if (fp_cmp_mag (a, b) != FP_LT) {
+      s_fp_sub (a, b, a);
+    }
+  }
+}
+
+
+#ifdef TFM_SMALL_MONT_SET
+    #include "fp_mont_small.i"
+#endif
+
+#ifdef HAVE_INTEL_MULX
+static inline void innermul8_mulx(fp_digit *c_mulx, fp_digit *cy_mulx, fp_digit *tmpm, fp_digit mu) 
+{
+    fp_digit _c0, _c1, _c2, _c3, _c4, _c5, _c6, _c7, cy ;
+
+    cy = *cy_mulx ;
+    _c0=c_mulx[0]; _c1=c_mulx[1]; _c2=c_mulx[2]; _c3=c_mulx[3]; _c4=c_mulx[4]; _c5=c_mulx[5]; _c6=c_mulx[6]; _c7=c_mulx[7];    
+    INNERMUL8_MULX ;
+    c_mulx[0]=_c0; c_mulx[1]=_c1; c_mulx[2]=_c2; c_mulx[3]=_c3; c_mulx[4]=_c4; c_mulx[5]=_c5; c_mulx[6]=_c6; c_mulx[7]=_c7; 
+    *cy_mulx = cy ;
+}
+
+/* computes x/R == x (mod N) via Montgomery Reduction */
+static void fp_montgomery_reduce_mulx(fp_int *a, fp_int *m, fp_digit mp)
+{
+   fp_digit c[FP_SIZE], *_c, *tmpm, mu = 0;
+   int      oldused, x, y, pa;
+
+   /* bail if too large */
+   if (m->used > (FP_SIZE/2)) {
+      (void)mu;                     /* shut up compiler */
+      return;
+   }
+
+#ifdef TFM_SMALL_MONT_SET
+   if (m->used <= 16) {
+      fp_montgomery_reduce_small(a, m, mp);
+      return;
+   }
+#endif
+
+
+   /* now zero the buff */
+   XMEMSET(c, 0, sizeof c);
+   pa = m->used;
+
+   /* copy the input */
+   oldused = a->used;
+   for (x = 0; x < oldused; x++) {
+       c[x] = a->dp[x];
+   }
+   MONT_START;
+
+   for (x = 0; x < pa; x++) {
+       fp_digit cy = 0;
+       /* get Mu for this round */
+       LOOP_START;
+       _c   = c + x;
+       tmpm = m->dp;
+       y = 0;
+        for (; y < (pa & ~7); y += 8) {
+              innermul8_mulx(_c, &cy, tmpm, mu) ;
+              _c   += 8;
+              tmpm += 8;
+           }
+       for (; y < pa; y++) {
+          INNERMUL;
+          ++_c;
+       }
+       LOOP_END;
+       while (cy) {
+           PROPCARRY;
+           ++_c;
+       }
+  }         
+
+  /* now copy out */
+  _c   = c + pa;
+  tmpm = a->dp;
+  for (x = 0; x < pa+1; x++) {
+     *tmpm++ = *_c++;
+  }
+
+  for (; x < oldused; x++)   {
+     *tmpm++ = 0;
+  }
+
+  MONT_FINI;
+
+  a->used = pa+1;
+  fp_clamp(a);
+  
+  /* if A >= m then A = A - m */
+  if (fp_cmp_mag (a, m) != FP_LT) {
+    s_fp_sub (a, m, a);
+  }
+}
+#endif
+
+/* computes x/R == x (mod N) via Montgomery Reduction */
+void fp_montgomery_reduce(fp_int *a, fp_int *m, fp_digit mp)
+{
+   fp_digit c[FP_SIZE], *_c, *tmpm, mu = 0;
+   int      oldused, x, y, pa;
+
+   IF_HAVE_INTEL_MULX(fp_montgomery_reduce_mulx(a, m, mp), return) ;
+
+   /* bail if too large */
+   if (m->used > (FP_SIZE/2)) {
+      (void)mu;                     /* shut up compiler */
+      return;
+   }
+
+#ifdef TFM_SMALL_MONT_SET
+   if (m->used <= 16) {
+      fp_montgomery_reduce_small(a, m, mp);
+      return;
+   }
+#endif
+
+
+   /* now zero the buff */
+   XMEMSET(c, 0, sizeof c);
+   pa = m->used;
+
+   /* copy the input */
+   oldused = a->used;
+   for (x = 0; x < oldused; x++) {
+       c[x] = a->dp[x];
+   }
+   MONT_START;
+
+   for (x = 0; x < pa; x++) {
+       fp_digit cy = 0;
+       /* get Mu for this round */
+       LOOP_START;
+       _c   = c + x;
+       tmpm = m->dp;
+       y = 0;
+       #if (defined(TFM_SSE2) || defined(TFM_X86_64))
+        for (; y < (pa & ~7); y += 8) {
+              INNERMUL8 ;
+              _c   += 8;
+              tmpm += 8;
+           }
+       #endif
+       for (; y < pa; y++) {
+          INNERMUL;
+          ++_c;
+       }
+       LOOP_END;
+       while (cy) {
+           PROPCARRY;
+           ++_c;
+       }
+  }         
+
+  /* now copy out */
+  _c   = c + pa;
+  tmpm = a->dp;
+  for (x = 0; x < pa+1; x++) {
+     *tmpm++ = *_c++;
+  }
+
+  for (; x < oldused; x++)   {
+     *tmpm++ = 0;
+  }
+
+  MONT_FINI;
+
+  a->used = pa+1;
+  fp_clamp(a);
+  
+  /* if A >= m then A = A - m */
+  if (fp_cmp_mag (a, m) != FP_LT) {
+    s_fp_sub (a, m, a);
+  }
+}
+
+void fp_read_unsigned_bin(fp_int *a, unsigned char *b, int c)
+{
+  /* zero the int */
+  fp_zero (a);
+
+  /* If we know the endianness of this architecture, and we're using
+     32-bit fp_digits, we can optimize this */
+#if (defined(LITTLE_ENDIAN_ORDER) || defined(BIG_ENDIAN_ORDER)) && defined(FP_32BIT)
+  /* But not for both simultaneously */
+#if defined(LITTLE_ENDIAN_ORDER) && defined(BIG_ENDIAN_ORDER)
+#error Both LITTLE_ENDIAN_ORDER and BIG_ENDIAN_ORDER defined.
+#endif
+  {
+     unsigned char *pd = (unsigned char *)a->dp;
+
+     if ((unsigned)c > (FP_SIZE * sizeof(fp_digit))) {
+        int excess = c - (FP_SIZE * sizeof(fp_digit));
+        c -= excess;
+        b += excess;
+     }
+     a->used = (c + sizeof(fp_digit) - 1)/sizeof(fp_digit);
+     /* read the bytes in */
+#ifdef BIG_ENDIAN_ORDER
+     {
+       /* Use Duff's device to unroll the loop. */
+       int idx = (c - 1) & ~3;
+       switch (c % 4) {
+       case 0:	do { pd[idx+0] = *b++;
+       case 3:	     pd[idx+1] = *b++;
+       case 2:	     pd[idx+2] = *b++;
+       case 1:	     pd[idx+3] = *b++;
+                     idx -= 4;
+	 	        } while ((c -= 4) > 0);
+       }
+     }
+#else
+     for (c -= 1; c >= 0; c -= 1) {
+       pd[c] = *b++;
+     }
+#endif
+  }
+#else
+  /* read the bytes in */
+  for (; c > 0; c--) {
+     fp_mul_2d (a, 8, a);
+     a->dp[0] |= *b++;
+     a->used += 1;
+  }
+#endif
+  fp_clamp (a);
+}
+
+void fp_to_unsigned_bin(fp_int *a, unsigned char *b)
+{
+  int     x;
+  fp_int  t;
+
+  fp_init_copy(&t, a);
+
+  x = 0;
+  while (fp_iszero (&t) == FP_NO) {
+      b[x++] = (unsigned char) (t.dp[0] & 255);
+      fp_div_2d (&t, 8, &t, NULL);
+  }
+  fp_reverse (b, x);
+}
+
+int fp_unsigned_bin_size(fp_int *a)
+{
+  int     size = fp_count_bits (a);
+  return (size / 8 + ((size & 7) != 0 ? 1 : 0));
+}
+
+void fp_set(fp_int *a, fp_digit b)
+{
+   fp_zero(a);
+   a->dp[0] = b;
+   a->used  = a->dp[0] ? 1 : 0;
+}
+
+int fp_count_bits (fp_int * a)
+{
+  int     r;
+  fp_digit q;
+
+  /* shortcut */
+  if (a->used == 0) {
+    return 0;
+  }
+
+  /* get number of digits and add that */
+  r = (a->used - 1) * DIGIT_BIT;
+
+  /* take the last digit and count the bits in it */
+  q = a->dp[a->used - 1];
+  while (q > ((fp_digit) 0)) {
+    ++r;
+    q >>= ((fp_digit) 1);
+  }
+  return r;
+}
+
+int fp_leading_bit(fp_int *a)
+{
+    int bit = 0;
+
+    if (a->used != 0) {
+        fp_digit q = a->dp[a->used - 1];
+        int qSz = sizeof(fp_digit);
+
+        while (qSz > 0) {
+            if ((unsigned char)q != 0)
+                bit = (q & 0x80) != 0;
+            q >>= 8;
+            qSz--;
+        }
+    }
+
+    return bit;
+}
+
+void fp_lshd(fp_int *a, int x)
+{
+   int y;
+
+   /* move up and truncate as required */
+   y = MIN(a->used + x - 1, (int)(FP_SIZE-1));
+
+   /* store new size */
+   a->used = y + 1;
+
+   /* move digits */
+   for (; y >= x; y--) {
+       a->dp[y] = a->dp[y-x];
+   }
+ 
+   /* zero lower digits */
+   for (; y >= 0; y--) {
+       a->dp[y] = 0;
+   }
+
+   /* clamp digits */
+   fp_clamp(a);
+}
+
+
+/* right shift by bit count */
+void fp_rshb(fp_int *c, int x)
+{
+    register fp_digit *tmpc, mask, shift;
+    fp_digit r, rr;
+    fp_digit D = x;
+
+    /* mask */
+    mask = (((fp_digit)1) << D) - 1;
+
+    /* shift for lsb */
+    shift = DIGIT_BIT - D;
+
+    /* alias */
+    tmpc = c->dp + (c->used - 1);
+
+    /* carry */
+    r = 0;
+    for (x = c->used - 1; x >= 0; x--) {
+      /* get the lower  bits of this word in a temp */
+      rr = *tmpc & mask;
+
+      /* shift the current word and mix in the carry bits from previous word */
+      *tmpc = (*tmpc >> D) | (r << shift);
+      --tmpc;
+
+      /* set the carry to the carry bits of the current word found above */
+      r = rr;
+    }
+}
+
+
+void fp_rshd(fp_int *a, int x)
+{
+  int y;
+
+  /* too many digits just zero and return */
+  if (x >= a->used) {
+     fp_zero(a);
+     return;
+  }
+
+   /* shift */
+   for (y = 0; y < a->used - x; y++) {
+      a->dp[y] = a->dp[y+x];
+   }
+
+   /* zero rest */
+   for (; y < a->used; y++) {
+      a->dp[y] = 0;
+   }
+   
+   /* decrement count */
+   a->used -= x;
+   fp_clamp(a);
+}
+
+/* reverse an array, used for radix code */
+void fp_reverse (unsigned char *s, int len)
+{
+  int     ix, iy;
+  unsigned char t;
+
+  ix = 0;
+  iy = len - 1;
+  while (ix < iy) {
+    t     = s[ix];
+    s[ix] = s[iy];
+    s[iy] = t;
+    ++ix;
+    --iy;
+  }
+}
+
+
+/* c = a - b */
+void fp_sub_d(fp_int *a, fp_digit b, fp_int *c)
+{
+   fp_int tmp;
+   fp_init(&tmp);
+   fp_set(&tmp, b);
+   fp_sub(a, &tmp, c);
+}
+
+
+/* CyaSSL callers from normal lib */
+
+/* init a new mp_int */
+int mp_init (mp_int * a)
+{
+  if (a)
+    fp_init(a);
+  return MP_OKAY;
+}
+
+#ifdef ALT_ECC_SIZE
+void fp_init(fp_int *a)
+{
+    a->size = FP_SIZE;
+    fp_zero(a);
+}
+
+void fp_zero(fp_int *a)
+{
+    a->used = 0;
+    a->sign = FP_ZPOS;
+    XMEMSET(a->dp, 0, a->size * sizeof(fp_digit));
+}
+#endif
+
+
+/* clear one (frees)  */
+void mp_clear (mp_int * a)
+{
+  fp_zero(a);
+}
+
+/* handle up to 6 inits */
+int mp_init_multi(mp_int* a, mp_int* b, mp_int* c, mp_int* d, mp_int* e, mp_int* f)
+{
+    if (a)
+        fp_init(a);
+    if (b)
+        fp_init(b);
+    if (c)
+        fp_init(c);
+    if (d)
+        fp_init(d);
+    if (e)
+        fp_init(e);
+    if (f)
+        fp_init(f);
+
+    return MP_OKAY;
+}
+
+/* high level addition (handles signs) */
+int mp_add (mp_int * a, mp_int * b, mp_int * c)
+{
+  fp_add(a, b, c);
+  return MP_OKAY;
+}
+
+/* high level subtraction (handles signs) */
+int mp_sub (mp_int * a, mp_int * b, mp_int * c)
+{
+  fp_sub(a, b, c);
+  return MP_OKAY;
+}
+
+/* high level multiplication (handles sign) */
+int mp_mul (mp_int * a, mp_int * b, mp_int * c)
+{
+  fp_mul(a, b, c);
+  return MP_OKAY;
+}
+
+/* d = a * b (mod c) */
+int mp_mulmod (mp_int * a, mp_int * b, mp_int * c, mp_int * d)
+{
+  return fp_mulmod(a, b, c, d);
+}
+
+/* c = a mod b, 0 <= c < b */
+int mp_mod (mp_int * a, mp_int * b, mp_int * c)
+{
+  return fp_mod (a, b, c);
+}
+
+/* hac 14.61, pp608 */
+int mp_invmod (mp_int * a, mp_int * b, mp_int * c)
+{
+  return fp_invmod(a, b, c);
+}
+
+/* this is a shell function that calls either the normal or Montgomery
+ * exptmod functions.  Originally the call to the montgomery code was
+ * embedded in the normal function but that wasted alot of stack space
+ * for nothing (since 99% of the time the Montgomery code would be called)
+ */
+int mp_exptmod (mp_int * G, mp_int * X, mp_int * P, mp_int * Y)
+{
+  return fp_exptmod(G, X, P, Y);
+}
+
+/* compare two ints (signed)*/
+int mp_cmp (mp_int * a, mp_int * b)
+{
+  return fp_cmp(a, b);
+}
+
+/* compare a digit */
+int mp_cmp_d(mp_int * a, mp_digit b)
+{
+  return fp_cmp_d(a, b);
+}
+
+/* get the size for an unsigned equivalent */
+int mp_unsigned_bin_size (mp_int * a)
+{
+  return fp_unsigned_bin_size(a);
+}
+
+/* store in unsigned [big endian] format */
+int mp_to_unsigned_bin (mp_int * a, unsigned char *b)
+{
+  fp_to_unsigned_bin(a,b);
+  return MP_OKAY;
+}
+
+/* reads a unsigned char array, assumes the msb is stored first [big endian] */
+int mp_read_unsigned_bin (mp_int * a, const unsigned char *b, int c)
+{
+  fp_read_unsigned_bin(a, (unsigned char *)b, c);
+  return MP_OKAY;
+}
+
+
+int mp_sub_d(fp_int *a, fp_digit b, fp_int *c)
+{
+    fp_sub_d(a, b, c);
+    return MP_OKAY;
+}
+
+
+#ifdef ALT_ECC_SIZE
+void fp_copy(fp_int *a, fp_int* b)
+{
+    if (a != b) {
+        b->used = a->used;
+        b->sign = a->sign;
+        XMEMCPY(b->dp, a->dp, a->used * sizeof(fp_digit));
+    }
+}
+
+void fp_init_copy(fp_int *a, fp_int* b)
+{
+    if (a != b) {
+        fp_init(a);
+        fp_copy(b, a);
+    }
+}
+#endif
+
+/* fast math conversion */
+int mp_copy(fp_int* a, fp_int* b)
+{
+    fp_copy(a, b);
+    return MP_OKAY;
+}
+
+
+/* fast math conversion */
+int mp_isodd(mp_int* a)
+{
+    return fp_isodd(a);
+}
+
+
+/* fast math conversion */
+int mp_iszero(mp_int* a)
+{
+    return fp_iszero(a);
+}
+
+
+/* fast math conversion */
+int mp_count_bits (mp_int* a)
+{
+    return fp_count_bits(a);
+}
+
+
+int mp_leading_bit (mp_int* a)
+{
+    return fp_leading_bit(a);
+}
+
+
+/* fast math conversion */
+void mp_rshb (mp_int* a, int x)
+{
+    fp_rshb(a, x);
+}
+
+
+/* fast math wrappers */
+int mp_set_int(fp_int *a, fp_digit b)
+{
+    fp_set(a, b);
+    return MP_OKAY;
+}
+
+
+#if defined(WOLFSSL_KEY_GEN) || defined (HAVE_ECC)
+
+/* c = a * a (mod b) */
+int fp_sqrmod(fp_int *a, fp_int *b, fp_int *c)
+{
+  fp_int tmp;
+  fp_init(&tmp);
+  fp_sqr(a, &tmp);
+  return fp_mod(&tmp, b, c);
+}
+
+/* fast math conversion */
+int mp_sqrmod(mp_int *a, mp_int *b, mp_int *c)
+{
+    return fp_sqrmod(a, b, c);
+}
+
+/* fast math conversion */
+int mp_montgomery_calc_normalization(mp_int *a, mp_int *b)
+{
+    fp_montgomery_calc_normalization(a, b);
+    return MP_OKAY;
+}
+
+#endif /* WOLFSSL_KEYGEN || HAVE_ECC */
+
+
+#if defined(WOLFSSL_KEY_GEN) || defined(HAVE_COMP_KEY)
+
+static const int lnz[16] = {
+   4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0
+};
+
+/* Counts the number of lsbs which are zero before the first zero bit */
+int fp_cnt_lsb(fp_int *a)
+{
+   int x;
+   fp_digit q, qq;
+
+   /* easy out */
+   if (fp_iszero(a) == 1) {
+      return 0;
+   }
+
+   /* scan lower digits until non-zero */
+   for (x = 0; x < a->used && a->dp[x] == 0; x++);
+   q = a->dp[x];
+   x *= DIGIT_BIT;
+
+   /* now scan this digit until a 1 is found */
+   if ((q & 1) == 0) {
+      do {
+         qq  = q & 15;
+         x  += lnz[qq];
+         q >>= 4;
+      } while (qq == 0);
+   }
+   return x;
+}
+
+
+
+
+static int s_is_power_of_two(fp_digit b, int *p)
+{
+   int x;
+
+   /* fast return if no power of two */
+   if ((b==0) || (b & (b-1))) {
+      return 0;
+   }
+
+   for (x = 0; x < DIGIT_BIT; x++) {
+      if (b == (((fp_digit)1)< cb + d == a */
+static int fp_div_d(fp_int *a, fp_digit b, fp_int *c, fp_digit *d)
+{
+  fp_int   q;
+  fp_word  w;
+  fp_digit t;
+  int      ix;
+
+  /* cannot divide by zero */
+  if (b == 0) {
+     return FP_VAL;
+  }
+
+  /* quick outs */
+  if (b == 1 || fp_iszero(a) == 1) {
+     if (d != NULL) {
+        *d = 0;
+     }
+     if (c != NULL) {
+        fp_copy(a, c);
+     }
+     return FP_OKAY;
+  }
+
+  /* power of two ? */
+  if (s_is_power_of_two(b, &ix) == 1) {
+     if (d != NULL) {
+        *d = a->dp[0] & ((((fp_digit)1)<used;
+  q.sign = a->sign;
+  w = 0;
+  for (ix = a->used - 1; ix >= 0; ix--) {
+     w = (w << ((fp_word)DIGIT_BIT)) | ((fp_word)a->dp[ix]);
+     
+     if (w >= b) {
+        t = (fp_digit)(w / b);
+        w -= ((fp_word)t) * ((fp_word)b);
+      } else {
+        t = 0;
+      }
+      q.dp[ix] = (fp_digit)t;
+  }
+  
+  if (d != NULL) {
+     *d = (fp_digit)w;
+  }
+  
+  if (c != NULL) {
+     fp_clamp(&q);
+     fp_copy(&q, c);
+  }
+ 
+  return FP_OKAY;
+}
+
+
+/* c = a mod b, 0 <= c < b  */
+static int fp_mod_d(fp_int *a, fp_digit b, fp_digit *c)
+{
+   return fp_div_d(a, b, NULL, c);
+}
+
+int mp_mod_d(fp_int *a, fp_digit b, fp_digit *c)
+{
+   return fp_mod_d(a, b, c);
+}
+
+#endif /* defined(WOLFSSL_KEY_GEN) || defined(HAVE_COMP_KEY) */
+
+#ifdef WOLFSSL_KEY_GEN
+
+void fp_gcd(fp_int *a, fp_int *b, fp_int *c);
+void fp_lcm(fp_int *a, fp_int *b, fp_int *c);
+int  fp_isprime(fp_int *a);
+
+int mp_gcd(fp_int *a, fp_int *b, fp_int *c)
+{
+    fp_gcd(a, b, c);
+    return MP_OKAY;
+}
+
+
+int mp_lcm(fp_int *a, fp_int *b, fp_int *c)
+{
+    fp_lcm(a, b, c);
+    return MP_OKAY;
+}
+
+
+int mp_prime_is_prime(mp_int* a, int t, int* result)
+{
+    (void)t;
+    *result = fp_isprime(a);
+    return MP_OKAY;
+}
+
+/* Miller-Rabin test of "a" to the base of "b" as described in 
+ * HAC pp. 139 Algorithm 4.24
+ *
+ * Sets result to 0 if definitely composite or 1 if probably prime.
+ * Randomly the chance of error is no more than 1/4 and often 
+ * very much lower.
+ */
+static void fp_prime_miller_rabin (fp_int * a, fp_int * b, int *result)
+{
+  fp_int  n1, y, r;
+  int     s, j;
+
+  /* default */
+  *result = FP_NO;
+
+  /* ensure b > 1 */
+  if (fp_cmp_d(b, 1) != FP_GT) {
+     return;
+  }     
+
+  /* get n1 = a - 1 */
+  fp_init_copy(&n1, a);
+  fp_sub_d(&n1, 1, &n1);
+
+  /* set 2**s * r = n1 */
+  fp_init_copy(&r, &n1);
+
+  /* count the number of least significant bits
+   * which are zero
+   */
+  s = fp_cnt_lsb(&r);
+
+  /* now divide n - 1 by 2**s */
+  fp_div_2d (&r, s, &r, NULL);
+
+  /* compute y = b**r mod a */
+  fp_init(&y);
+  fp_exptmod(b, &r, a, &y);
+
+  /* if y != 1 and y != n1 do */
+  if (fp_cmp_d (&y, 1) != FP_EQ && fp_cmp (&y, &n1) != FP_EQ) {
+    j = 1;
+    /* while j <= s-1 and y != n1 */
+    while ((j <= (s - 1)) && fp_cmp (&y, &n1) != FP_EQ) {
+      fp_sqrmod (&y, a, &y);
+
+      /* if y == 1 then composite */
+      if (fp_cmp_d (&y, 1) == FP_EQ) {
+         return;
+      }
+      ++j;
+    }
+
+    /* if y != n1 then composite */
+    if (fp_cmp (&y, &n1) != FP_EQ) {
+       return;
+    }
+  }
+
+  /* probably prime now */
+  *result = FP_YES;
+}
+
+
+/* a few primes */
+static const fp_digit primes[256] = {
+  0x0002, 0x0003, 0x0005, 0x0007, 0x000B, 0x000D, 0x0011, 0x0013,
+  0x0017, 0x001D, 0x001F, 0x0025, 0x0029, 0x002B, 0x002F, 0x0035,
+  0x003B, 0x003D, 0x0043, 0x0047, 0x0049, 0x004F, 0x0053, 0x0059,
+  0x0061, 0x0065, 0x0067, 0x006B, 0x006D, 0x0071, 0x007F, 0x0083,
+  0x0089, 0x008B, 0x0095, 0x0097, 0x009D, 0x00A3, 0x00A7, 0x00AD,
+  0x00B3, 0x00B5, 0x00BF, 0x00C1, 0x00C5, 0x00C7, 0x00D3, 0x00DF,
+  0x00E3, 0x00E5, 0x00E9, 0x00EF, 0x00F1, 0x00FB, 0x0101, 0x0107,
+  0x010D, 0x010F, 0x0115, 0x0119, 0x011B, 0x0125, 0x0133, 0x0137,
+
+  0x0139, 0x013D, 0x014B, 0x0151, 0x015B, 0x015D, 0x0161, 0x0167,
+  0x016F, 0x0175, 0x017B, 0x017F, 0x0185, 0x018D, 0x0191, 0x0199,
+  0x01A3, 0x01A5, 0x01AF, 0x01B1, 0x01B7, 0x01BB, 0x01C1, 0x01C9,
+  0x01CD, 0x01CF, 0x01D3, 0x01DF, 0x01E7, 0x01EB, 0x01F3, 0x01F7,
+  0x01FD, 0x0209, 0x020B, 0x021D, 0x0223, 0x022D, 0x0233, 0x0239,
+  0x023B, 0x0241, 0x024B, 0x0251, 0x0257, 0x0259, 0x025F, 0x0265,
+  0x0269, 0x026B, 0x0277, 0x0281, 0x0283, 0x0287, 0x028D, 0x0293,
+  0x0295, 0x02A1, 0x02A5, 0x02AB, 0x02B3, 0x02BD, 0x02C5, 0x02CF,
+
+  0x02D7, 0x02DD, 0x02E3, 0x02E7, 0x02EF, 0x02F5, 0x02F9, 0x0301,
+  0x0305, 0x0313, 0x031D, 0x0329, 0x032B, 0x0335, 0x0337, 0x033B,
+  0x033D, 0x0347, 0x0355, 0x0359, 0x035B, 0x035F, 0x036D, 0x0371,
+  0x0373, 0x0377, 0x038B, 0x038F, 0x0397, 0x03A1, 0x03A9, 0x03AD,
+  0x03B3, 0x03B9, 0x03C7, 0x03CB, 0x03D1, 0x03D7, 0x03DF, 0x03E5,
+  0x03F1, 0x03F5, 0x03FB, 0x03FD, 0x0407, 0x0409, 0x040F, 0x0419,
+  0x041B, 0x0425, 0x0427, 0x042D, 0x043F, 0x0443, 0x0445, 0x0449,
+  0x044F, 0x0455, 0x045D, 0x0463, 0x0469, 0x047F, 0x0481, 0x048B,
+
+  0x0493, 0x049D, 0x04A3, 0x04A9, 0x04B1, 0x04BD, 0x04C1, 0x04C7,
+  0x04CD, 0x04CF, 0x04D5, 0x04E1, 0x04EB, 0x04FD, 0x04FF, 0x0503,
+  0x0509, 0x050B, 0x0511, 0x0515, 0x0517, 0x051B, 0x0527, 0x0529,
+  0x052F, 0x0551, 0x0557, 0x055D, 0x0565, 0x0577, 0x0581, 0x058F,
+  0x0593, 0x0595, 0x0599, 0x059F, 0x05A7, 0x05AB, 0x05AD, 0x05B3,
+  0x05BF, 0x05C9, 0x05CB, 0x05CF, 0x05D1, 0x05D5, 0x05DB, 0x05E7,
+  0x05F3, 0x05FB, 0x0607, 0x060D, 0x0611, 0x0617, 0x061F, 0x0623,
+  0x062B, 0x062F, 0x063D, 0x0641, 0x0647, 0x0649, 0x064D, 0x0653
+};
+
+int fp_isprime(fp_int *a)
+{
+   fp_int   b;
+   fp_digit d = 0;
+   int      r, res;
+
+   /* do trial division */
+   for (r = 0; r < 256; r++) {
+       fp_mod_d(a, primes[r], &d);
+       if (d == 0) {
+          return FP_NO;
+       }
+   }
+
+   /* now do 8 miller rabins */
+   fp_init(&b);
+   for (r = 0; r < 8; r++) {
+       fp_set(&b, primes[r]);
+       fp_prime_miller_rabin(a, &b, &res);
+       if (res == FP_NO) {
+          return FP_NO;
+       }
+   }
+   return FP_YES;
+}
+
+
+/* c = [a, b] */
+void fp_lcm(fp_int *a, fp_int *b, fp_int *c)
+{
+   fp_int  t1, t2;
+
+   fp_init(&t1);
+   fp_init(&t2);
+   fp_gcd(a, b, &t1);
+   if (fp_cmp_mag(a, b) == FP_GT) {
+      fp_div(a, &t1, &t2, NULL);
+      fp_mul(b, &t2, c);
+   } else {
+      fp_div(b, &t1, &t2, NULL);
+      fp_mul(a, &t2, c);
+   }   
+}
+
+
+
+/* c = (a, b) */
+void fp_gcd(fp_int *a, fp_int *b, fp_int *c)
+{
+   fp_int u, v, r;
+
+   /* either zero than gcd is the largest */
+   if (fp_iszero (a) == 1 && fp_iszero (b) == 0) {
+     fp_abs (b, c);
+     return;
+   }
+   if (fp_iszero (a) == 0 && fp_iszero (b) == 1) {
+     fp_abs (a, c);
+     return;
+   }
+
+   /* optimized.  At this point if a == 0 then
+    * b must equal zero too
+    */
+   if (fp_iszero (a) == 1) {
+     fp_zero(c);
+     return;
+   }
+
+   /* sort inputs */
+   if (fp_cmp_mag(a, b) != FP_LT) {
+      fp_init_copy(&u, a);
+      fp_init_copy(&v, b);
+   } else {
+      fp_init_copy(&u, b);
+      fp_init_copy(&v, a);
+   }
+ 
+   fp_init(&r);
+   while (fp_iszero(&v) == FP_NO) {
+      fp_mod(&u, &v, &r);
+      fp_copy(&v, &u);
+      fp_copy(&r, &v);
+   }
+   fp_copy(&u, c);
+}
+
+#endif /* WOLFSSL_KEY_GEN */
+
+
+#if defined(HAVE_ECC) || !defined(NO_PWDBASED)
+/* c = a + b */
+void fp_add_d(fp_int *a, fp_digit b, fp_int *c)
+{
+   fp_int tmp;
+   fp_init(&tmp);
+   fp_set(&tmp, b);
+   fp_add(a,&tmp,c);
+}
+
+/* external compatibility */
+int mp_add_d(fp_int *a, fp_digit b, fp_int *c)
+{
+    fp_add_d(a, b, c);
+    return MP_OKAY;
+}
+
+#endif  /* HAVE_ECC || !NO_PWDBASED */
+
+
+#ifdef HAVE_ECC
+
+/* chars used in radix conversions */
+static const char *fp_s_rmap = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz+/";
+
+static int fp_read_radix(fp_int *a, const char *str, int radix)
+{
+  int     y, neg;
+  char    ch;
+
+  /* make sure the radix is ok */
+  if (radix < 2 || radix > 64) {
+    return FP_VAL;
+  }
+
+  /* if the leading digit is a
+   * minus set the sign to negative.
+   */
+  if (*str == '-') {
+    ++str;
+    neg = FP_NEG;
+  } else {
+    neg = FP_ZPOS;
+  }
+
+  /* set the integer to the default of zero */
+  fp_zero (a);
+
+  /* process each digit of the string */
+  while (*str) {
+    /* if the radix < 36 the conversion is case insensitive
+     * this allows numbers like 1AB and 1ab to represent the same  value
+     * [e.g. in hex]
+     */
+    ch = (char) ((radix < 36) ? XTOUPPER((unsigned char)*str) : *str);
+    for (y = 0; y < 64; y++) {
+      if (ch == fp_s_rmap[y]) {
+         break;
+      }
+    }
+
+    /* if the char was found in the map
+     * and is less than the given radix add it
+     * to the number, otherwise exit the loop.
+     */
+    if (y < radix) {
+      fp_mul_d (a, (fp_digit) radix, a);
+      fp_add_d (a, (fp_digit) y, a);
+    } else {
+      break;
+    }
+    ++str;
+  }
+
+  /* set the sign only if a != 0 */
+  if (fp_iszero(a) != FP_YES) {
+     a->sign = neg;
+  }
+  return FP_OKAY;
+}
+
+/* fast math conversion */
+int mp_read_radix(mp_int *a, const char *str, int radix)
+{
+    return fp_read_radix(a, str, radix);
+}
+
+/* fast math conversion */
+void mp_set(fp_int *a, fp_digit b)
+{
+    fp_set(a,b);
+}
+
+/* fast math conversion */
+int mp_sqr(fp_int *A, fp_int *B)
+{
+    fp_sqr(A, B);
+    return MP_OKAY;
+}
+  
+/* fast math conversion */
+int mp_montgomery_reduce(fp_int *a, fp_int *m, fp_digit mp)
+{
+    fp_montgomery_reduce(a, m, mp);
+    return MP_OKAY;
+}
+
+
+/* fast math conversion */
+int mp_montgomery_setup(fp_int *a, fp_digit *rho)
+{
+    return fp_montgomery_setup(a, rho);
+}
+
+int mp_div_2(fp_int * a, fp_int * b)
+{
+    fp_div_2(a, b);
+    return MP_OKAY;
+}
+
+
+int mp_init_copy(fp_int * a, fp_int * b)
+{
+    fp_init_copy(a, b);
+    return MP_OKAY;
+}
+
+
+#ifdef HAVE_COMP_KEY
+
+int mp_cnt_lsb(fp_int* a)
+{
+    fp_cnt_lsb(a);
+    return MP_OKAY;
+}
+
+int mp_div_2d(fp_int* a, int b, fp_int* c, fp_int* d)
+{
+    fp_div_2d(a, b, c, d);
+    return MP_OKAY;
+}
+
+#endif /* HAVE_COMP_KEY */
+
+
+#endif /* HAVE_ECC */
+
+#endif /* USE_FAST_MATH */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/wc_port.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/wc_port.c
new file mode 100644
index 0000000..4190337
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/src/wc_port.c
@@ -0,0 +1,656 @@
+/* port.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+#include 
+#include 
+
+
+#ifdef _MSC_VER
+    /* 4996 warning to use MS extensions e.g., strcpy_s instead of strncpy */
+    #pragma warning(disable: 4996)
+#endif
+
+
+
+#ifdef SINGLE_THREADED
+
+int InitMutex(wolfSSL_Mutex* m)
+{
+    (void)m;
+    return 0;
+}
+
+
+int FreeMutex(wolfSSL_Mutex *m)
+{
+    (void)m;
+    return 0;
+}
+
+
+int LockMutex(wolfSSL_Mutex *m)
+{
+    (void)m;
+    return 0;
+}
+
+
+int UnLockMutex(wolfSSL_Mutex *m)
+{
+    (void)m;
+    return 0;
+}
+
+#else /* MULTI_THREAD */
+
+    #if defined(FREERTOS)
+
+        int InitMutex(wolfSSL_Mutex* m)
+        {
+            int iReturn;
+
+            *m = ( wolfSSL_Mutex ) xSemaphoreCreateMutex();
+            if( *m != NULL )
+                iReturn = 0;
+            else
+                iReturn = BAD_MUTEX_E;
+
+            return iReturn;
+        }
+
+        int FreeMutex(wolfSSL_Mutex* m)
+        {
+            vSemaphoreDelete( *m );
+            return 0;
+        }
+
+        int LockMutex(wolfSSL_Mutex* m)
+        {
+            /* Assume an infinite block, or should there be zero block? */
+            xSemaphoreTake( *m, portMAX_DELAY );
+            return 0;
+        }
+
+        int UnLockMutex(wolfSSL_Mutex* m)
+        {
+            xSemaphoreGive( *m );
+            return 0;
+        }
+
+    #elif defined(WOLFSSL_SAFERTOS)
+
+        int InitMutex(wolfSSL_Mutex* m)
+        {
+            vSemaphoreCreateBinary(m->mutexBuffer, m->mutex);
+            if (m->mutex == NULL)
+                return BAD_MUTEX_E;
+
+            return 0;
+        }
+
+        int FreeMutex(wolfSSL_Mutex* m)
+        {
+            (void)m;
+            return 0;
+        }
+
+        int LockMutex(wolfSSL_Mutex* m)
+        {
+            /* Assume an infinite block */
+            xSemaphoreTake(m->mutex, portMAX_DELAY);
+            return 0;
+        }
+
+        int UnLockMutex(wolfSSL_Mutex* m)
+        {
+            xSemaphoreGive(m->mutex);
+            return 0;
+        }
+
+
+    #elif defined(USE_WINDOWS_API)
+
+        int InitMutex(wolfSSL_Mutex* m)
+        {
+            InitializeCriticalSection(m);
+            return 0;
+        }
+
+
+        int FreeMutex(wolfSSL_Mutex* m)
+        {
+            DeleteCriticalSection(m);
+            return 0;
+        }
+
+
+        int LockMutex(wolfSSL_Mutex* m)
+        {
+            EnterCriticalSection(m);
+            return 0;
+        }
+
+
+        int UnLockMutex(wolfSSL_Mutex* m)
+        {
+            LeaveCriticalSection(m);
+            return 0;
+        }
+
+    #elif defined(WOLFSSL_PTHREADS)
+
+        int InitMutex(wolfSSL_Mutex* m)
+        {
+            if (pthread_mutex_init(m, 0) == 0)
+                return 0;
+            else
+                return BAD_MUTEX_E;
+        }
+
+
+        int FreeMutex(wolfSSL_Mutex* m)
+        {
+            if (pthread_mutex_destroy(m) == 0)
+                return 0;
+            else
+                return BAD_MUTEX_E;
+        }
+
+
+        int LockMutex(wolfSSL_Mutex* m)
+        {
+            if (pthread_mutex_lock(m) == 0)
+                return 0;
+            else
+                return BAD_MUTEX_E;
+        }
+
+
+        int UnLockMutex(wolfSSL_Mutex* m)
+        {
+            if (pthread_mutex_unlock(m) == 0)
+                return 0;
+            else
+                return BAD_MUTEX_E;
+        }
+
+    #elif defined(THREADX)
+
+        int InitMutex(wolfSSL_Mutex* m)
+        {
+            if (tx_mutex_create(m, "wolfSSL Mutex", TX_NO_INHERIT) == 0)
+                return 0;
+            else
+                return BAD_MUTEX_E;
+        }
+
+
+        int FreeMutex(wolfSSL_Mutex* m)
+        {
+            if (tx_mutex_delete(m) == 0)
+                return 0;
+            else
+                return BAD_MUTEX_E;
+        }
+
+
+        int LockMutex(wolfSSL_Mutex* m)
+        {
+            if (tx_mutex_get(m, TX_WAIT_FOREVER) == 0)
+                return 0;
+            else
+                return BAD_MUTEX_E;
+        }
+
+
+        int UnLockMutex(wolfSSL_Mutex* m)
+        {
+            if (tx_mutex_put(m) == 0)
+                return 0;
+            else
+                return BAD_MUTEX_E;
+        }
+
+    #elif defined(MICRIUM)
+
+        int InitMutex(wolfSSL_Mutex* m)
+        {
+            #if (NET_SECURE_MGR_CFG_EN == DEF_ENABLED)
+                if (NetSecure_OS_MutexCreate(m) == 0)
+                    return 0;
+                else
+                    return BAD_MUTEX_E;
+            #else
+                return 0;
+            #endif
+        }
+
+
+        int FreeMutex(wolfSSL_Mutex* m)
+        {
+            #if (NET_SECURE_MGR_CFG_EN == DEF_ENABLED)
+                if (NetSecure_OS_FreeMutex(m) == 0)
+                    return 0;
+                else
+                    return BAD_MUTEX_E;
+            #else
+                return 0;
+            #endif
+        }
+
+
+        int LockMutex(wolfSSL_Mutex* m)
+        {
+            #if (NET_SECURE_MGR_CFG_EN == DEF_ENABLED)
+                if (NetSecure_OS_LockMutex(m) == 0)
+                    return 0;
+                else
+                    return BAD_MUTEX_E;
+            #else
+                return 0;
+            #endif
+        }
+
+
+        int UnLockMutex(wolfSSL_Mutex* m)
+        {
+            #if (NET_SECURE_MGR_CFG_EN == DEF_ENABLED)
+                if (NetSecure_OS_UnLockMutex(m) == 0)
+                    return 0;
+                else
+                    return BAD_MUTEX_E;
+            #else
+                return 0;
+            #endif
+
+        }
+
+    #elif defined(EBSNET)
+
+        int InitMutex(wolfSSL_Mutex* m)
+        {
+            if (rtp_sig_mutex_alloc(m, "wolfSSL Mutex") == -1)
+                return BAD_MUTEX_E;
+            else
+                return 0;
+        }
+
+        int FreeMutex(wolfSSL_Mutex* m)
+        {
+            rtp_sig_mutex_free(*m);
+            return 0;
+        }
+
+        int LockMutex(wolfSSL_Mutex* m)
+        {
+            if (rtp_sig_mutex_claim_timed(*m, RTIP_INF) == 0)
+                return 0;
+            else
+                return BAD_MUTEX_E;
+        }
+
+        int UnLockMutex(wolfSSL_Mutex* m)
+        {
+            rtp_sig_mutex_release(*m);
+            return 0;
+        }
+
+    #elif defined(FREESCALE_MQX)
+
+        int InitMutex(wolfSSL_Mutex* m)
+        {
+            if (_mutex_init(m, NULL) == MQX_EOK)
+                return 0;
+            else
+                return BAD_MUTEX_E;
+        }
+
+        int FreeMutex(wolfSSL_Mutex* m)
+        {
+            if (_mutex_destroy(m) == MQX_EOK)
+                return 0;
+            else
+                return BAD_MUTEX_E;
+        }
+
+        int LockMutex(wolfSSL_Mutex* m)
+        {
+            if (_mutex_lock(m) == MQX_EOK)
+                return 0;
+            else
+                return BAD_MUTEX_E;
+        }
+
+        int UnLockMutex(wolfSSL_Mutex* m)
+        {
+            if (_mutex_unlock(m) == MQX_EOK)
+                return 0;
+            else
+                return BAD_MUTEX_E;
+        }
+
+    #elif defined (WOLFSSL_TIRTOS)
+
+        int InitMutex(wolfSSL_Mutex* m)
+        {
+           Semaphore_Params params;
+
+           Semaphore_Params_init(¶ms);
+           params.mode = Semaphore_Mode_BINARY;
+
+           *m = Semaphore_create(1, ¶ms, NULL);
+
+           return 0;
+        }
+
+        int FreeMutex(wolfSSL_Mutex* m)
+        {
+            Semaphore_delete(m);
+
+            return 0;
+        }
+
+        int LockMutex(wolfSSL_Mutex* m)
+        {
+            Semaphore_pend(*m, BIOS_WAIT_FOREVER);
+
+            return 0;
+        }
+
+        int UnLockMutex(wolfSSL_Mutex* m)
+        {
+            Semaphore_post(*m);
+
+            return 0;
+        }
+
+    #elif defined(WOLFSSL_uITRON4)
+        #include "kernel.h"
+        int InitMutex(wolfSSL_Mutex* m)
+        {
+            int iReturn;
+            m->sem.sematr  = TA_TFIFO ;
+            m->sem.isemcnt = 1 ;
+            m->sem.maxsem  = 1 ;
+            m->sem.name    = NULL ;
+
+            m->id = acre_sem(&m->sem);
+            if( m->id != NULL )
+                iReturn = 0;
+            else
+                iReturn = BAD_MUTEX_E;
+
+            return iReturn;
+        }
+
+        int FreeMutex(wolfSSL_Mutex* m)
+        {
+            del_sem( m->id );
+            return 0;
+        }
+
+        int LockMutex(wolfSSL_Mutex* m)
+        {
+            wai_sem(m->id);
+            return 0;
+        }
+
+        int UnLockMutex(wolfSSL_Mutex* m)
+        {
+            sig_sem(m->id);
+            return 0;
+        }
+
+        /****  uITRON malloc/free ***/
+        static ID ID_wolfssl_MPOOL = 0 ;
+        static T_CMPL wolfssl_MPOOL = {TA_TFIFO, 0, NULL, "wolfSSL_MPOOL"};
+
+        int uITRON4_minit(size_t poolsz) {
+            ER ercd;
+            wolfssl_MPOOL.mplsz = poolsz ;
+            ercd = acre_mpl(&wolfssl_MPOOL);
+            if (ercd > 0) {
+                ID_wolfssl_MPOOL = ercd;
+                return 0;
+            } else {
+                return -1;
+            }
+        }
+
+        void *uITRON4_malloc(size_t sz) {
+            ER ercd;
+            void *p ;
+            ercd = get_mpl(ID_wolfssl_MPOOL, sz, (VP)&p);
+            if (ercd == E_OK) {
+                return p;
+            } else {
+                return 0 ;
+            }
+        }
+
+        void *uITRON4_realloc(void *p, size_t sz) {
+          ER ercd;
+          void *newp ;
+          if(p) {
+              ercd = get_mpl(ID_wolfssl_MPOOL, sz, (VP)&newp);
+              if (ercd == E_OK) {
+                  memcpy(newp, p, sz) ;
+                  ercd = rel_mpl(ID_wolfssl_MPOOL, (VP)p);
+                  if (ercd == E_OK) {
+                      return newp;
+                  }
+              }
+          }
+          return 0 ;
+        }
+
+        void uITRON4_free(void *p) {
+            ER ercd;
+            ercd = rel_mpl(ID_wolfssl_MPOOL, (VP)p);
+            if (ercd == E_OK) {
+                return ;
+            } else {
+                return ;
+            }
+        }
+
+#elif defined(WOLFSSL_uTKERNEL2)
+        #include "tk/tkernel.h"
+        int InitMutex(wolfSSL_Mutex* m)
+        {
+            int iReturn;
+            m->sem.sematr  = TA_TFIFO ;
+            m->sem.isemcnt = 1 ;
+            m->sem.maxsem  = 1 ;
+
+            m->id = tk_cre_sem(&m->sem);
+            if( m->id != NULL )
+                iReturn = 0;
+            else
+                iReturn = BAD_MUTEX_E;
+
+            return iReturn;
+        }
+
+        int FreeMutex(wolfSSL_Mutex* m)
+        {
+            tk_del_sem( m->id );
+            return 0;
+        }
+
+        int LockMutex(wolfSSL_Mutex* m)
+        {
+            tk_wai_sem(m->id, 1, TMO_FEVR);
+            return 0;
+        }
+
+        int UnLockMutex(wolfSSL_Mutex* m)
+        {
+            tk_sig_sem(m->id, 1);
+            return 0;
+        }
+
+        /****  uT-Kernel malloc/free ***/
+        static ID ID_wolfssl_MPOOL = 0 ;
+        static T_CMPL wolfssl_MPOOL =
+                     {(void *)NULL,
+        TA_TFIFO , 0,   "wolfSSL_MPOOL"};
+
+        int uTKernel_init_mpool(unsigned int sz) {
+            ER ercd;
+            wolfssl_MPOOL.mplsz = sz ;
+            ercd = tk_cre_mpl(&wolfssl_MPOOL);
+            if (ercd > 0) {
+                ID_wolfssl_MPOOL = ercd;
+                return 0;
+            } else {
+                return -1;
+            }
+        }
+
+        void *uTKernel_malloc(unsigned int sz) {
+            ER ercd;
+            void *p ;
+            ercd = tk_get_mpl(ID_wolfssl_MPOOL, sz, (VP)&p, TMO_FEVR);
+            if (ercd == E_OK) {
+                return p;
+            } else {
+                return 0 ;
+            }
+        }
+
+        void *uTKernel_realloc(void *p, unsigned int sz) {
+          ER ercd;
+          void *newp ;
+          if(p) {
+              ercd = tk_get_mpl(ID_wolfssl_MPOOL, sz, (VP)&newp, TMO_FEVR);
+              if (ercd == E_OK) {
+                  memcpy(newp, p, sz) ;
+                  ercd = tk_rel_mpl(ID_wolfssl_MPOOL, (VP)p);
+                  if (ercd == E_OK) {
+                      return newp;
+                  }
+              }
+          }
+          return 0 ;
+        }
+
+        void uTKernel_free(void *p) {
+            ER ercd;
+            ercd = tk_rel_mpl(ID_wolfssl_MPOOL, (VP)p);
+            if (ercd == E_OK) {
+                return ;
+            } else {
+                return ;
+            }
+        }
+
+    #elif defined(WOLFSSL_MDK_ARM)|| defined(WOLFSSL_CMSIS_RTOS)
+    
+        #if defined(WOLFSSL_CMSIS_RTOS)
+            #include "cmsis_os.h"
+            #define CMSIS_NMUTEX 10
+            osMutexDef(wolfSSL_mt0) ;  osMutexDef(wolfSSL_mt1) ;  osMutexDef(wolfSSL_mt2) ;
+            osMutexDef(wolfSSL_mt3) ;  osMutexDef(wolfSSL_mt4) ;  osMutexDef(wolfSSL_mt5) ;  
+            osMutexDef(wolfSSL_mt6) ;  osMutexDef(wolfSSL_mt7) ;  osMutexDef(wolfSSL_mt8) ;  
+            osMutexDef(wolfSSL_mt9) ;  
+            
+            static const osMutexDef_t *CMSIS_mutex[] = { osMutex(wolfSSL_mt0),   
+                osMutex(wolfSSL_mt1),    osMutex(wolfSSL_mt2),   osMutex(wolfSSL_mt3),    
+                osMutex(wolfSSL_mt4),    osMutex(wolfSSL_mt5),   osMutex(wolfSSL_mt6),
+                osMutex(wolfSSL_mt7),    osMutex(wolfSSL_mt8),    osMutex(wolfSSL_mt9) } ;                 
+            
+            static osMutexId CMSIS_mutexID[CMSIS_NMUTEX] = {0} ;
+
+            int InitMutex(wolfSSL_Mutex* m)
+            {
+                int i ;
+                for (i=0; i  /* initialize and Mutex for TI Crypt Engine */
+    #include  /* md5, sha1, sha224, sha256 */
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/test/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/test/include.am
new file mode 100644
index 0000000..950d7c6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/test/include.am
@@ -0,0 +1,11 @@
+# vim:ft=automake
+# All paths should be given relative to the root
+
+noinst_PROGRAMS+= wolfcrypt/test/testwolfcrypt
+wolfcrypt_test_testwolfcrypt_SOURCES      = wolfcrypt/test/test.c
+wolfcrypt_test_testwolfcrypt_LDADD        = src/libwolfssl.la
+wolfcrypt_test_testwolfcrypt_DEPENDENCIES = src/libwolfssl.la
+noinst_HEADERS += wolfcrypt/test/test.h
+EXTRA_DIST += wolfcrypt/test/test.sln
+EXTRA_DIST += wolfcrypt/test/test.vcproj
+DISTCLEANFILES+= wolfcrypt/test/.libs/testwolfcrypt
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/test/test.c b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/test/test.c
new file mode 100644
index 0000000..cf5dbe5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/test/test.c
@@ -0,0 +1,6239 @@
+/* test.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifdef XMALLOC_USER
+    #include   /* we're using malloc / free direct here */
+#endif
+
+#ifndef NO_CRYPT_TEST
+
+#ifdef WOLFSSL_TEST_CERT
+    #include 
+#else
+    #include 
+#endif
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#ifdef HAVE_ECC
+    #include 
+#endif
+#ifdef HAVE_CURVE25519
+    #include 
+#endif
+#ifdef HAVE_ED25519
+    #include 
+#endif
+#ifdef HAVE_BLAKE2
+    #include 
+#endif
+#ifdef HAVE_LIBZ
+    #include 
+#endif
+#ifdef HAVE_PKCS7
+    #include 
+#endif
+#ifdef HAVE_FIPS
+    #include 
+#endif
+
+#ifdef _MSC_VER
+    /* 4996 warning to use MS extensions e.g., strcpy_s instead of strncpy */
+    #pragma warning(disable: 4996)
+#endif
+
+#ifdef OPENSSL_EXTRA
+    #include 
+    #include 
+    #include 
+    #include 
+#endif
+
+
+#if defined(USE_CERT_BUFFERS_1024) || defined(USE_CERT_BUFFERS_2048) \
+                                   || !defined(NO_DH)
+    /* include test cert and key buffers for use with NO_FILESYSTEM */
+    #if defined(WOLFSSL_MDK_ARM)
+        #include "cert_data.h"
+                        /* use certs_test.c for initial data, so other
+                                               commands can share the data. */
+    #else
+        #include 
+    #endif
+#endif
+
+#if defined(WOLFSSL_MDK_ARM)
+        #include 
+        #include 
+    extern FILE * wolfSSL_fopen(const char *fname, const char *mode) ;
+    #define fopen wolfSSL_fopen
+#endif
+
+#ifdef HAVE_NTRU
+    #include "ntru_crypto.h"
+#endif
+#ifdef HAVE_CAVIUM
+    #include "cavium_sysdep.h"
+    #include "cavium_common.h"
+    #include "cavium_ioctl.h"
+#endif
+
+#ifdef FREESCALE_MQX
+    #include 
+    #include 
+    #include 
+#else
+    #include 
+#endif
+
+
+#ifdef THREADX
+    /* since just testing, use THREADX log printf instead */
+    int dc_log_printf(char*, ...);
+        #undef printf
+        #define printf dc_log_printf
+#endif
+
+#include "wolfcrypt/test/test.h"
+
+
+typedef struct testVector {
+    const char*  input;
+    const char*  output;
+    size_t inLen;
+    size_t outLen;
+} testVector;
+
+int  md2_test(void);
+int  md5_test(void);
+int  md4_test(void);
+int  sha_test(void);
+int  sha256_test(void);
+int  sha512_test(void);
+int  sha384_test(void);
+int  hmac_md5_test(void);
+int  hmac_sha_test(void);
+int  hmac_sha256_test(void);
+int  hmac_sha384_test(void);
+int  hmac_sha512_test(void);
+int  hmac_blake2b_test(void);
+int  hkdf_test(void);
+int  arc4_test(void);
+int  hc128_test(void);
+int  rabbit_test(void);
+int  chacha_test(void);
+int  chacha20_poly1305_aead_test(void);
+int  des_test(void);
+int  des3_test(void);
+int  aes_test(void);
+int  poly1305_test(void);
+int  aesgcm_test(void);
+int  gmac_test(void);
+int  aesccm_test(void);
+int  camellia_test(void);
+int  rsa_test(void);
+int  dh_test(void);
+int  dsa_test(void);
+int  random_test(void);
+int  pwdbased_test(void);
+int  ripemd_test(void);
+int  openssl_test(void);   /* test mini api */
+int pbkdf1_test(void);
+int pkcs12_test(void);
+int pbkdf2_test(void);
+#ifdef HAVE_ECC
+    int  ecc_test(void);
+    #ifdef HAVE_ECC_ENCRYPT
+        int  ecc_encrypt_test(void);
+    #endif
+#endif
+#ifdef HAVE_CURVE25519
+    int  curve25519_test(void);
+#endif
+#ifdef HAVE_ED25519
+    int  ed25519_test(void);
+#endif
+#ifdef HAVE_BLAKE2
+    int  blake2b_test(void);
+#endif
+#ifdef HAVE_LIBZ
+    int compress_test(void);
+#endif
+#ifdef HAVE_PKCS7
+    int pkcs7enveloped_test(void);
+    int pkcs7signed_test(void);
+#endif
+
+
+/* General big buffer size for many tests. */ 
+#define FOURK_BUF 4096
+
+
+static int err_sys(const char* msg, int es)
+
+{
+    printf("%s error = %d\n", msg, es);
+    return -1; /* error state */
+}
+
+/* func_args from test.h, so don't have to pull in other junk */
+typedef struct func_args {
+    int    argc;
+    char** argv;
+    int    return_code;
+} func_args;
+
+
+#ifdef HAVE_FIPS
+
+static void myFipsCb(int ok, int err, const char* hash)
+{
+    printf("in my Fips callback, ok = %d, err = %d\n", ok, err);
+    printf("message = %s\n", wc_GetErrorString(err));
+    printf("hash = %s\n", hash);
+
+    if (err == IN_CORE_FIPS_E) {
+        printf("In core integrity hash check failure, copy above hash\n");
+        printf("into verifyCore[] in fips_test.c and rebuild\n");
+    }
+}
+
+#endif /* HAVE_FIPS */
+
+
+int wolfcrypt_test(void* args)
+{
+    int ret = 0;
+
+    ((func_args*)args)->return_code = -1; /* error state */
+
+#ifdef HAVE_FIPS
+    wolfCrypt_SetCb_fips(myFipsCb);
+#endif
+
+#if !defined(NO_BIG_INT)
+    if (CheckCtcSettings() != 1)
+        return err_sys("Build vs runtime math mismatch\n", -1234);
+
+#ifdef USE_FAST_MATH
+    if (CheckFastMathSettings() != 1)
+        return err_sys("Build vs runtime fastmath FP_MAX_BITS mismatch\n",
+                       -1235);
+#endif /* USE_FAST_MATH */
+#endif /* !NO_BIG_INT */
+
+
+#ifndef NO_MD5
+    if ( (ret = md5_test()) != 0)
+        return err_sys("MD5      test failed!\n", ret);
+    else
+        printf( "MD5      test passed!\n");
+#endif
+
+#ifdef WOLFSSL_MD2
+    if ( (ret = md2_test()) != 0)
+        return err_sys("MD2      test failed!\n", ret);
+    else
+        printf( "MD2      test passed!\n");
+#endif
+
+#ifndef NO_MD4
+    if ( (ret = md4_test()) != 0)
+        return err_sys("MD4      test failed!\n", ret);
+    else
+        printf( "MD4      test passed!\n");
+#endif
+
+#ifndef NO_SHA
+    if ( (ret = sha_test()) != 0)
+        return err_sys("SHA      test failed!\n", ret);
+    else
+        printf( "SHA      test passed!\n");
+#endif
+
+#ifndef NO_SHA256
+    if ( (ret = sha256_test()) != 0)
+        return err_sys("SHA-256  test failed!\n", ret);
+    else
+        printf( "SHA-256  test passed!\n");
+#endif
+
+#ifdef WOLFSSL_SHA384
+    if ( (ret = sha384_test()) != 0)
+        return err_sys("SHA-384  test failed!\n", ret);
+    else
+        printf( "SHA-384  test passed!\n");
+#endif
+
+#ifdef WOLFSSL_SHA512
+    if ( (ret = sha512_test()) != 0)
+        return err_sys("SHA-512  test failed!\n", ret);
+    else
+        printf( "SHA-512  test passed!\n");
+#endif
+
+#ifdef WOLFSSL_RIPEMD
+    if ( (ret = ripemd_test()) != 0)
+        return err_sys("RIPEMD   test failed!\n", ret);
+    else
+        printf( "RIPEMD   test passed!\n");
+#endif
+
+#ifdef HAVE_BLAKE2
+    if ( (ret = blake2b_test()) != 0)
+        return err_sys("BLAKE2b  test failed!\n", ret);
+    else
+        printf( "BLAKE2b  test passed!\n");
+#endif
+
+#ifndef NO_HMAC
+    #ifndef NO_MD5
+        if ( (ret = hmac_md5_test()) != 0)
+            return err_sys("HMAC-MD5 test failed!\n", ret);
+        else
+            printf( "HMAC-MD5 test passed!\n");
+    #endif
+
+    #ifndef NO_SHA
+    if ( (ret = hmac_sha_test()) != 0)
+        return err_sys("HMAC-SHA test failed!\n", ret);
+    else
+        printf( "HMAC-SHA test passed!\n");
+    #endif
+
+    #ifndef NO_SHA256
+        if ( (ret = hmac_sha256_test()) != 0)
+            return err_sys("HMAC-SHA256 test failed!\n", ret);
+        else
+            printf( "HMAC-SHA256 test passed!\n");
+    #endif
+
+    #ifdef WOLFSSL_SHA384
+        if ( (ret = hmac_sha384_test()) != 0)
+            return err_sys("HMAC-SHA384 test failed!\n", ret);
+        else
+            printf( "HMAC-SHA384 test passed!\n");
+    #endif
+
+    #ifdef WOLFSSL_SHA512
+        if ( (ret = hmac_sha512_test()) != 0)
+            return err_sys("HMAC-SHA512 test failed!\n", ret);
+        else
+            printf( "HMAC-SHA512 test passed!\n");
+    #endif
+
+    #ifdef HAVE_BLAKE2
+        if ( (ret = hmac_blake2b_test()) != 0)
+            return err_sys("HMAC-BLAKE2 test failed!\n", ret);
+        else
+            printf( "HMAC-BLAKE2 test passed!\n");
+    #endif
+
+    #ifdef HAVE_HKDF
+        if ( (ret = hkdf_test()) != 0)
+            return err_sys("HMAC-KDF    test failed!\n", ret);
+        else
+            printf( "HMAC-KDF    test passed!\n");
+    #endif
+
+#endif
+
+#ifdef HAVE_AESGCM
+    if ( (ret = gmac_test()) != 0)
+        return err_sys("GMAC     test passed!\n", ret);
+    else
+        printf( "GMAC     test passed!\n");
+#endif
+
+#ifndef NO_RC4
+    if ( (ret = arc4_test()) != 0)
+        return err_sys("ARC4     test failed!\n", ret);
+    else
+        printf( "ARC4     test passed!\n");
+#endif
+
+#ifndef NO_HC128
+    if ( (ret = hc128_test()) != 0)
+        return err_sys("HC-128   test failed!\n", ret);
+    else
+        printf( "HC-128   test passed!\n");
+#endif
+
+#ifndef NO_RABBIT
+    if ( (ret = rabbit_test()) != 0)
+        return err_sys("Rabbit   test failed!\n", ret);
+    else
+        printf( "Rabbit   test passed!\n");
+#endif
+
+#ifdef HAVE_CHACHA
+    if ( (ret = chacha_test()) != 0)
+        return err_sys("Chacha   test failed!\n", ret);
+    else
+        printf( "Chacha   test passed!\n");
+#endif
+
+#ifdef HAVE_POLY1305
+    if ( (ret = poly1305_test()) != 0)
+        return err_sys("POLY1305 test failed!\n", ret);
+    else
+        printf( "POLY1305 test passed!\n");
+#endif
+
+#if defined(HAVE_CHACHA) && defined(HAVE_POLY1305)
+    if ( (ret = chacha20_poly1305_aead_test()) != 0)
+        return err_sys("ChaCha20-Poly1305 AEAD test failed!\n", ret);
+    else
+        printf( "ChaCha20-Poly1305 AEAD test passed!\n");
+#endif
+
+#ifndef NO_DES3
+    if ( (ret = des_test()) != 0)
+        return err_sys("DES      test failed!\n", ret);
+    else
+        printf( "DES      test passed!\n");
+#endif
+
+#ifndef NO_DES3
+    if ( (ret = des3_test()) != 0)
+        return err_sys("DES3     test failed!\n", ret);
+    else
+        printf( "DES3     test passed!\n");
+#endif
+
+#ifndef NO_AES
+    if ( (ret = aes_test()) != 0)
+        return err_sys("AES      test failed!\n", ret);
+    else
+        printf( "AES      test passed!\n");
+
+#ifdef HAVE_AESGCM
+    if ( (ret = aesgcm_test()) != 0)
+        return err_sys("AES-GCM  test failed!\n", ret);
+    else
+        printf( "AES-GCM  test passed!\n");
+#endif
+
+#ifdef HAVE_AESCCM
+    if ( (ret = aesccm_test()) != 0)
+        return err_sys("AES-CCM  test failed!\n", ret);
+    else
+        printf( "AES-CCM  test passed!\n");
+#endif
+#endif
+
+#ifdef HAVE_CAMELLIA
+    if ( (ret = camellia_test()) != 0)
+        return err_sys("CAMELLIA test failed!\n", ret);
+    else
+        printf( "CAMELLIA test passed!\n");
+#endif
+
+    if ( (ret = random_test()) != 0)
+        return err_sys("RANDOM   test failed!\n", ret);
+    else
+        printf( "RANDOM   test passed!\n");
+
+#ifndef NO_RSA
+    if ( (ret = rsa_test()) != 0)
+        return err_sys("RSA      test failed!\n", ret);
+    else
+        printf( "RSA      test passed!\n");
+#endif
+
+#ifndef NO_DH
+    if ( (ret = dh_test()) != 0)
+        return err_sys("DH       test failed!\n", ret);
+    else
+        printf( "DH       test passed!\n");
+#endif
+
+#ifndef NO_DSA
+    if ( (ret = dsa_test()) != 0)
+        return err_sys("DSA      test failed!\n", ret);
+    else
+        printf( "DSA      test passed!\n");
+#endif
+
+#ifndef NO_PWDBASED
+    if ( (ret = pwdbased_test()) != 0)
+        return err_sys("PWDBASED test failed!\n", ret);
+    else
+        printf( "PWDBASED test passed!\n");
+#endif
+
+#ifdef OPENSSL_EXTRA
+    if ( (ret = openssl_test()) != 0)
+        return err_sys("OPENSSL  test failed!\n", ret);
+    else
+        printf( "OPENSSL  test passed!\n");
+#endif
+
+#ifdef HAVE_ECC
+    if ( (ret = ecc_test()) != 0)
+        return err_sys("ECC      test failed!\n", ret);
+    else
+        printf( "ECC      test passed!\n");
+    #ifdef HAVE_ECC_ENCRYPT
+        if ( (ret = ecc_encrypt_test()) != 0)
+            return err_sys("ECC Enc  test failed!\n", ret);
+        else
+            printf( "ECC Enc  test passed!\n");
+    #endif
+#endif
+
+#ifdef HAVE_CURVE25519
+    if ( (ret = curve25519_test()) != 0)
+        return err_sys("CURVE25519 test failed!\n", ret);
+    else
+        printf( "CURVE25519 test passed!\n");
+#endif
+
+#ifdef HAVE_ED25519
+    if ( (ret = ed25519_test()) != 0)
+        return err_sys("ED25519  test failed!\n", ret);
+    else
+        printf( "ED25519  test passed!\n");
+#endif
+
+#ifdef HAVE_LIBZ
+    if ( (ret = compress_test()) != 0)
+        return err_sys("COMPRESS test failed!\n", ret);
+    else
+        printf( "COMPRESS test passed!\n");
+#endif
+
+#ifdef HAVE_PKCS7
+    if ( (ret = pkcs7enveloped_test()) != 0)
+        return err_sys("PKCS7enveloped test failed!\n", ret);
+    else
+        printf( "PKCS7enveloped test passed!\n");
+
+    if ( (ret = pkcs7signed_test()) != 0)
+        return err_sys("PKCS7signed    test failed!\n", ret);
+    else
+        printf( "PKCS7signed    test passed!\n");
+#endif
+
+    ((func_args*)args)->return_code = ret;
+
+    return ret;
+}
+
+
+#ifndef NO_MAIN_DRIVER
+
+#ifdef HAVE_CAVIUM
+
+static int OpenNitroxDevice(int dma_mode,int dev_id)
+{
+   Csp1CoreAssignment core_assign;
+   Uint32             device;
+
+   if (CspInitialize(CAVIUM_DIRECT,CAVIUM_DEV_ID))
+      return -1;
+   if (Csp1GetDevType(&device))
+      return -1;
+   if (device != NPX_DEVICE) {
+      if (ioctl(gpkpdev_hdlr[CAVIUM_DEV_ID], IOCTL_CSP1_GET_CORE_ASSIGNMENT,
+                (Uint32 *)&core_assign)!= 0)
+         return -1;
+   }
+   CspShutdown(CAVIUM_DEV_ID);
+
+   return CspInitialize(dma_mode, dev_id);
+}
+
+#endif /* HAVE_CAVIUM */
+
+    /* so overall tests can pull in test function */
+
+    int main(int argc, char** argv)
+    {
+
+        func_args args;
+
+
+#ifdef HAVE_CAVIUM
+        int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID);
+        if (ret != 0) {
+            err_sys("Cavium OpenNitroxDevice failed", -1236);
+            return -1236;
+        }
+#endif /* HAVE_CAVIUM */
+
+        args.argc = argc;
+        args.argv = argv;
+
+        wolfcrypt_test(&args);
+
+#ifdef HAVE_CAVIUM
+        CspShutdown(CAVIUM_DEV_ID);
+#endif
+
+        return args.return_code;
+    }
+
+#endif /* NO_MAIN_DRIVER */
+
+
+#ifdef WOLFSSL_MD2
+int md2_test()
+{
+    Md2  md2;
+    byte hash[MD2_DIGEST_SIZE];
+
+    testVector a, b, c, d, e, f, g;
+    testVector test_md2[7];
+    int times = sizeof(test_md2) / sizeof(testVector), i;
+
+    a.input  = "";
+    a.output = "\x83\x50\xe5\xa3\xe2\x4c\x15\x3d\xf2\x27\x5c\x9f\x80\x69"
+               "\x27\x73";
+    a.inLen  = strlen(a.input);
+    a.outLen = MD2_DIGEST_SIZE;
+
+    b.input  = "a";
+    b.output = "\x32\xec\x01\xec\x4a\x6d\xac\x72\xc0\xab\x96\xfb\x34\xc0"
+               "\xb5\xd1";
+    b.inLen  = strlen(b.input);
+    b.outLen = MD2_DIGEST_SIZE;
+
+    c.input  = "abc";
+    c.output = "\xda\x85\x3b\x0d\x3f\x88\xd9\x9b\x30\x28\x3a\x69\xe6\xde"
+               "\xd6\xbb";
+    c.inLen  = strlen(c.input);
+    c.outLen = MD2_DIGEST_SIZE;
+
+    d.input  = "message digest";
+    d.output = "\xab\x4f\x49\x6b\xfb\x2a\x53\x0b\x21\x9f\xf3\x30\x31\xfe"
+               "\x06\xb0";
+    d.inLen  = strlen(d.input);
+    d.outLen = MD2_DIGEST_SIZE;
+
+    e.input  = "abcdefghijklmnopqrstuvwxyz";
+    e.output = "\x4e\x8d\xdf\xf3\x65\x02\x92\xab\x5a\x41\x08\xc3\xaa\x47"
+               "\x94\x0b";
+    e.inLen  = strlen(e.input);
+    e.outLen = MD2_DIGEST_SIZE;
+
+    f.input  = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz012345"
+               "6789";
+    f.output = "\xda\x33\xde\xf2\xa4\x2d\xf1\x39\x75\x35\x28\x46\xc3\x03"
+               "\x38\xcd";
+    f.inLen  = strlen(f.input);
+    f.outLen = MD2_DIGEST_SIZE;
+
+    g.input  = "1234567890123456789012345678901234567890123456789012345678"
+               "9012345678901234567890";
+    g.output = "\xd5\x97\x6f\x79\xd8\x3d\x3a\x0d\xc9\x80\x6c\x3c\x66\xf3"
+               "\xef\xd8";
+    g.inLen  = strlen(g.input);
+    g.outLen = MD2_DIGEST_SIZE;
+
+    test_md2[0] = a;
+    test_md2[1] = b;
+    test_md2[2] = c;
+    test_md2[3] = d;
+    test_md2[4] = e;
+    test_md2[5] = f;
+    test_md2[6] = g;
+
+    wc_InitMd2(&md2);
+
+    for (i = 0; i < times; ++i) {
+        wc_Md2Update(&md2, (byte*)test_md2[i].input, (word32)test_md2[i].inLen);
+        wc_Md2Final(&md2, hash);
+
+        if (memcmp(hash, test_md2[i].output, MD2_DIGEST_SIZE) != 0)
+            return -155 - i;
+    }
+
+    return 0;
+}
+#endif
+
+#ifndef NO_MD5
+int md5_test(void)
+{
+    Md5  md5;
+    byte hash[MD5_DIGEST_SIZE];
+
+    testVector a, b, c, d, e;
+    testVector test_md5[5];
+    int times = sizeof(test_md5) / sizeof(testVector), i;
+
+    a.input  = "abc";
+    a.output = "\x90\x01\x50\x98\x3c\xd2\x4f\xb0\xd6\x96\x3f\x7d\x28\xe1\x7f"
+               "\x72";
+    a.inLen  = strlen(a.input);
+    a.outLen = MD5_DIGEST_SIZE;
+
+    b.input  = "message digest";
+    b.output = "\xf9\x6b\x69\x7d\x7c\xb7\x93\x8d\x52\x5a\x2f\x31\xaa\xf1\x61"
+               "\xd0";
+    b.inLen  = strlen(b.input);
+    b.outLen = MD5_DIGEST_SIZE;
+
+    c.input  = "abcdefghijklmnopqrstuvwxyz";
+    c.output = "\xc3\xfc\xd3\xd7\x61\x92\xe4\x00\x7d\xfb\x49\x6c\xca\x67\xe1"
+               "\x3b";
+    c.inLen  = strlen(c.input);
+    c.outLen = MD5_DIGEST_SIZE;
+
+    d.input  = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz012345"
+               "6789";
+    d.output = "\xd1\x74\xab\x98\xd2\x77\xd9\xf5\xa5\x61\x1c\x2c\x9f\x41\x9d"
+               "\x9f";
+    d.inLen  = strlen(d.input);
+    d.outLen = MD5_DIGEST_SIZE;
+
+    e.input  = "1234567890123456789012345678901234567890123456789012345678"
+               "9012345678901234567890";
+    e.output = "\x57\xed\xf4\xa2\x2b\xe3\xc9\x55\xac\x49\xda\x2e\x21\x07\xb6"
+               "\x7a";
+    e.inLen  = strlen(e.input);
+    e.outLen = MD5_DIGEST_SIZE;
+
+    test_md5[0] = a;
+    test_md5[1] = b;
+    test_md5[2] = c;
+    test_md5[3] = d;
+    test_md5[4] = e;
+
+    wc_InitMd5(&md5);
+
+    for (i = 0; i < times; ++i) {
+        wc_Md5Update(&md5, (byte*)test_md5[i].input, (word32)test_md5[i].inLen);
+        wc_Md5Final(&md5, hash);
+
+        if (memcmp(hash, test_md5[i].output, MD5_DIGEST_SIZE) != 0)
+            return -5 - i;
+    }
+
+    return 0;
+}
+#endif /* NO_MD5 */
+
+
+#ifndef NO_MD4
+
+int md4_test(void)
+{
+    Md4  md4;
+    byte hash[MD4_DIGEST_SIZE];
+
+    testVector a, b, c, d, e, f, g;
+    testVector test_md4[7];
+    int times = sizeof(test_md4) / sizeof(testVector), i;
+
+    a.input  = "";
+    a.output = "\x31\xd6\xcf\xe0\xd1\x6a\xe9\x31\xb7\x3c\x59\xd7\xe0\xc0\x89"
+               "\xc0";
+    a.inLen  = strlen(a.input);
+    a.outLen = MD4_DIGEST_SIZE;
+
+    b.input  = "a";
+    b.output = "\xbd\xe5\x2c\xb3\x1d\xe3\x3e\x46\x24\x5e\x05\xfb\xdb\xd6\xfb"
+               "\x24";
+    b.inLen  = strlen(b.input);
+    b.outLen = MD4_DIGEST_SIZE;
+
+    c.input  = "abc";
+    c.output = "\xa4\x48\x01\x7a\xaf\x21\xd8\x52\x5f\xc1\x0a\xe8\x7a\xa6\x72"
+               "\x9d";
+    c.inLen  = strlen(c.input);
+    c.outLen = MD4_DIGEST_SIZE;
+
+    d.input  = "message digest";
+    d.output = "\xd9\x13\x0a\x81\x64\x54\x9f\xe8\x18\x87\x48\x06\xe1\xc7\x01"
+               "\x4b";
+    d.inLen  = strlen(d.input);
+    d.outLen = MD4_DIGEST_SIZE;
+
+    e.input  = "abcdefghijklmnopqrstuvwxyz";
+    e.output = "\xd7\x9e\x1c\x30\x8a\xa5\xbb\xcd\xee\xa8\xed\x63\xdf\x41\x2d"
+               "\xa9";
+    e.inLen  = strlen(e.input);
+    e.outLen = MD4_DIGEST_SIZE;
+
+    f.input  = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz012345"
+               "6789";
+    f.output = "\x04\x3f\x85\x82\xf2\x41\xdb\x35\x1c\xe6\x27\xe1\x53\xe7\xf0"
+               "\xe4";
+    f.inLen  = strlen(f.input);
+    f.outLen = MD4_DIGEST_SIZE;
+
+    g.input  = "1234567890123456789012345678901234567890123456789012345678"
+               "9012345678901234567890";
+    g.output = "\xe3\x3b\x4d\xdc\x9c\x38\xf2\x19\x9c\x3e\x7b\x16\x4f\xcc\x05"
+               "\x36";
+    g.inLen  = strlen(g.input);
+    g.outLen = MD4_DIGEST_SIZE;
+
+    test_md4[0] = a;
+    test_md4[1] = b;
+    test_md4[2] = c;
+    test_md4[3] = d;
+    test_md4[4] = e;
+    test_md4[5] = f;
+    test_md4[6] = g;
+
+    wc_InitMd4(&md4);
+
+    for (i = 0; i < times; ++i) {
+        wc_Md4Update(&md4, (byte*)test_md4[i].input, (word32)test_md4[i].inLen);
+        wc_Md4Final(&md4, hash);
+
+        if (memcmp(hash, test_md4[i].output, MD4_DIGEST_SIZE) != 0)
+            return -205 - i;
+    }
+
+    return 0;
+}
+
+#endif /* NO_MD4 */
+
+#ifndef NO_SHA
+
+int sha_test(void)
+{
+    Sha  sha;
+    byte hash[SHA_DIGEST_SIZE];
+
+    testVector a, b, c, d;
+    testVector test_sha[4];
+    int ret;
+    int times = sizeof(test_sha) / sizeof(struct testVector), i;
+
+    a.input  = "abc";
+    a.output = "\xA9\x99\x3E\x36\x47\x06\x81\x6A\xBA\x3E\x25\x71\x78\x50\xC2"
+               "\x6C\x9C\xD0\xD8\x9D";
+    a.inLen  = strlen(a.input);
+    a.outLen = SHA_DIGEST_SIZE;
+
+    b.input  = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq";
+    b.output = "\x84\x98\x3E\x44\x1C\x3B\xD2\x6E\xBA\xAE\x4A\xA1\xF9\x51\x29"
+               "\xE5\xE5\x46\x70\xF1";
+    b.inLen  = strlen(b.input);
+    b.outLen = SHA_DIGEST_SIZE;
+
+    c.input  = "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa"
+               "aaaaaa";
+    c.output = "\x00\x98\xBA\x82\x4B\x5C\x16\x42\x7B\xD7\xA1\x12\x2A\x5A\x44"
+               "\x2A\x25\xEC\x64\x4D";
+    c.inLen  = strlen(c.input);
+    c.outLen = SHA_DIGEST_SIZE;
+
+    d.input  = "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa"
+               "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa"
+               "aaaaaaaaaa";
+    d.output = "\xAD\x5B\x3F\xDB\xCB\x52\x67\x78\xC2\x83\x9D\x2F\x15\x1E\xA7"
+               "\x53\x99\x5E\x26\xA0";
+    d.inLen  = strlen(d.input);
+    d.outLen = SHA_DIGEST_SIZE;
+
+    test_sha[0] = a;
+    test_sha[1] = b;
+    test_sha[2] = c;
+    test_sha[3] = d;
+
+    ret = wc_InitSha(&sha);
+    if (ret != 0)
+        return -4001;
+
+    for (i = 0; i < times; ++i) {
+        wc_ShaUpdate(&sha, (byte*)test_sha[i].input, (word32)test_sha[i].inLen);
+        wc_ShaFinal(&sha, hash);
+
+        if (memcmp(hash, test_sha[i].output, SHA_DIGEST_SIZE) != 0)
+            return -10 - i;
+    }
+
+    return 0;
+}
+
+#endif /* NO_SHA */
+
+#ifdef WOLFSSL_RIPEMD
+int ripemd_test(void)
+{
+    RipeMd  ripemd;
+    byte hash[RIPEMD_DIGEST_SIZE];
+
+    testVector a, b, c, d;
+    testVector test_ripemd[4];
+    int times = sizeof(test_ripemd) / sizeof(struct testVector), i;
+
+    a.input  = "abc";
+    a.output = "\x8e\xb2\x08\xf7\xe0\x5d\x98\x7a\x9b\x04\x4a\x8e\x98\xc6"
+               "\xb0\x87\xf1\x5a\x0b\xfc";
+    a.inLen  = strlen(a.input);
+    a.outLen = RIPEMD_DIGEST_SIZE;
+
+    b.input  = "message digest";
+    b.output = "\x5d\x06\x89\xef\x49\xd2\xfa\xe5\x72\xb8\x81\xb1\x23\xa8"
+               "\x5f\xfa\x21\x59\x5f\x36";
+    b.inLen  = strlen(b.input);
+    b.outLen = RIPEMD_DIGEST_SIZE;
+
+    c.input  = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq";
+    c.output = "\x12\xa0\x53\x38\x4a\x9c\x0c\x88\xe4\x05\xa0\x6c\x27\xdc"
+               "\xf4\x9a\xda\x62\xeb\x2b";
+    c.inLen  = strlen(c.input);
+    c.outLen = RIPEMD_DIGEST_SIZE;
+
+    d.input  = "12345678901234567890123456789012345678901234567890123456"
+               "789012345678901234567890";
+    d.output = "\x9b\x75\x2e\x45\x57\x3d\x4b\x39\xf4\xdb\xd3\x32\x3c\xab"
+               "\x82\xbf\x63\x32\x6b\xfb";
+    d.inLen  = strlen(d.input);
+    d.outLen = RIPEMD_DIGEST_SIZE;
+
+    test_ripemd[0] = a;
+    test_ripemd[1] = b;
+    test_ripemd[2] = c;
+    test_ripemd[3] = d;
+
+    wc_InitRipeMd(&ripemd);
+
+    for (i = 0; i < times; ++i) {
+        wc_RipeMdUpdate(&ripemd, (byte*)test_ripemd[i].input,
+                     (word32)test_ripemd[i].inLen);
+        wc_RipeMdFinal(&ripemd, hash);
+
+        if (memcmp(hash, test_ripemd[i].output, RIPEMD_DIGEST_SIZE) != 0)
+            return -10 - i;
+    }
+
+    return 0;
+}
+#endif /* WOLFSSL_RIPEMD */
+
+
+#ifdef HAVE_BLAKE2
+
+
+#define BLAKE2_TESTS 3
+
+static const byte blake2b_vec[BLAKE2_TESTS][BLAKE2B_OUTBYTES] =
+{
+  {
+    0x78, 0x6A, 0x02, 0xF7, 0x42, 0x01, 0x59, 0x03,
+    0xC6, 0xC6, 0xFD, 0x85, 0x25, 0x52, 0xD2, 0x72,
+    0x91, 0x2F, 0x47, 0x40, 0xE1, 0x58, 0x47, 0x61,
+    0x8A, 0x86, 0xE2, 0x17, 0xF7, 0x1F, 0x54, 0x19,
+    0xD2, 0x5E, 0x10, 0x31, 0xAF, 0xEE, 0x58, 0x53,
+    0x13, 0x89, 0x64, 0x44, 0x93, 0x4E, 0xB0, 0x4B,
+    0x90, 0x3A, 0x68, 0x5B, 0x14, 0x48, 0xB7, 0x55,
+    0xD5, 0x6F, 0x70, 0x1A, 0xFE, 0x9B, 0xE2, 0xCE
+  },
+  {
+    0x2F, 0xA3, 0xF6, 0x86, 0xDF, 0x87, 0x69, 0x95,
+    0x16, 0x7E, 0x7C, 0x2E, 0x5D, 0x74, 0xC4, 0xC7,
+    0xB6, 0xE4, 0x8F, 0x80, 0x68, 0xFE, 0x0E, 0x44,
+    0x20, 0x83, 0x44, 0xD4, 0x80, 0xF7, 0x90, 0x4C,
+    0x36, 0x96, 0x3E, 0x44, 0x11, 0x5F, 0xE3, 0xEB,
+    0x2A, 0x3A, 0xC8, 0x69, 0x4C, 0x28, 0xBC, 0xB4,
+    0xF5, 0xA0, 0xF3, 0x27, 0x6F, 0x2E, 0x79, 0x48,
+    0x7D, 0x82, 0x19, 0x05, 0x7A, 0x50, 0x6E, 0x4B
+  },
+  {
+    0x1C, 0x08, 0x79, 0x8D, 0xC6, 0x41, 0xAB, 0xA9,
+    0xDE, 0xE4, 0x35, 0xE2, 0x25, 0x19, 0xA4, 0x72,
+    0x9A, 0x09, 0xB2, 0xBF, 0xE0, 0xFF, 0x00, 0xEF,
+    0x2D, 0xCD, 0x8E, 0xD6, 0xF8, 0xA0, 0x7D, 0x15,
+    0xEA, 0xF4, 0xAE, 0xE5, 0x2B, 0xBF, 0x18, 0xAB,
+    0x56, 0x08, 0xA6, 0x19, 0x0F, 0x70, 0xB9, 0x04,
+    0x86, 0xC8, 0xA7, 0xD4, 0x87, 0x37, 0x10, 0xB1,
+    0x11, 0x5D, 0x3D, 0xEB, 0xBB, 0x43, 0x27, 0xB5
+  }
+};
+
+
+
+int blake2b_test(void)
+{
+    Blake2b b2b;
+    byte    digest[64];
+    byte    input[64];
+    int     i, ret;
+
+    for (i = 0; i < (int)sizeof(input); i++)
+        input[i] = (byte)i;
+
+    for (i = 0; i < BLAKE2_TESTS; i++) {
+        ret = wc_InitBlake2b(&b2b, 64);
+        if (ret != 0)
+            return -4002;
+
+        ret = wc_Blake2bUpdate(&b2b, input, i);
+        if (ret != 0)
+            return -4003;
+
+        ret = wc_Blake2bFinal(&b2b, digest, 64);
+        if (ret != 0)
+            return -4004;
+
+        if (memcmp(digest, blake2b_vec[i], 64) != 0) {
+            return -300 - i;
+        }
+    }
+
+    return 0;
+}
+#endif /* HAVE_BLAKE2 */
+
+
+#ifndef NO_SHA256
+int sha256_test(void)
+{
+    Sha256 sha;
+    byte   hash[SHA256_DIGEST_SIZE];
+
+    testVector a, b;
+    testVector test_sha[2];
+    int ret;
+    int times = sizeof(test_sha) / sizeof(struct testVector), i;
+
+    a.input  = "abc";
+    a.output = "\xBA\x78\x16\xBF\x8F\x01\xCF\xEA\x41\x41\x40\xDE\x5D\xAE\x22"
+               "\x23\xB0\x03\x61\xA3\x96\x17\x7A\x9C\xB4\x10\xFF\x61\xF2\x00"
+               "\x15\xAD";
+    a.inLen  = strlen(a.input);
+    a.outLen = SHA256_DIGEST_SIZE;
+
+    b.input  = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq";
+    b.output = "\x24\x8D\x6A\x61\xD2\x06\x38\xB8\xE5\xC0\x26\x93\x0C\x3E\x60"
+               "\x39\xA3\x3C\xE4\x59\x64\xFF\x21\x67\xF6\xEC\xED\xD4\x19\xDB"
+               "\x06\xC1";
+    b.inLen  = strlen(b.input);
+    b.outLen = SHA256_DIGEST_SIZE;
+
+    test_sha[0] = a;
+    test_sha[1] = b;
+
+    ret = wc_InitSha256(&sha);
+    if (ret != 0)
+        return -4005;
+
+    for (i = 0; i < times; ++i) {
+        ret = wc_Sha256Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen);
+        if (ret != 0)
+            return -4006;
+        ret = wc_Sha256Final(&sha, hash);
+        if (ret != 0)
+            return -4007;
+
+        if (memcmp(hash, test_sha[i].output, SHA256_DIGEST_SIZE) != 0)
+            return -10 - i;
+    }
+
+    return 0;
+}
+#endif
+
+
+#ifdef WOLFSSL_SHA512
+int sha512_test(void)
+{
+    Sha512 sha;
+    byte   hash[SHA512_DIGEST_SIZE];
+    int    ret;
+
+    testVector a, b;
+    testVector test_sha[2];
+    int times = sizeof(test_sha) / sizeof(struct testVector), i;
+
+    a.input  = "abc";
+    a.output = "\xdd\xaf\x35\xa1\x93\x61\x7a\xba\xcc\x41\x73\x49\xae\x20\x41"
+               "\x31\x12\xe6\xfa\x4e\x89\xa9\x7e\xa2\x0a\x9e\xee\xe6\x4b\x55"
+               "\xd3\x9a\x21\x92\x99\x2a\x27\x4f\xc1\xa8\x36\xba\x3c\x23\xa3"
+               "\xfe\xeb\xbd\x45\x4d\x44\x23\x64\x3c\xe8\x0e\x2a\x9a\xc9\x4f"
+               "\xa5\x4c\xa4\x9f";
+    a.inLen  = strlen(a.input);
+    a.outLen = SHA512_DIGEST_SIZE;
+
+    b.input  = "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmnhi"
+               "jklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu";
+    b.output = "\x8e\x95\x9b\x75\xda\xe3\x13\xda\x8c\xf4\xf7\x28\x14\xfc\x14"
+               "\x3f\x8f\x77\x79\xc6\xeb\x9f\x7f\xa1\x72\x99\xae\xad\xb6\x88"
+               "\x90\x18\x50\x1d\x28\x9e\x49\x00\xf7\xe4\x33\x1b\x99\xde\xc4"
+               "\xb5\x43\x3a\xc7\xd3\x29\xee\xb6\xdd\x26\x54\x5e\x96\xe5\x5b"
+               "\x87\x4b\xe9\x09";
+    b.inLen  = strlen(b.input);
+    b.outLen = SHA512_DIGEST_SIZE;
+
+    test_sha[0] = a;
+    test_sha[1] = b;
+
+    ret = wc_InitSha512(&sha);
+    if (ret != 0)
+        return -4009;
+
+    for (i = 0; i < times; ++i) {
+        ret = wc_Sha512Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen);
+        if (ret != 0)
+            return -4010;
+
+        ret = wc_Sha512Final(&sha, hash);
+        if (ret != 0)
+            return -4011;
+
+        if (memcmp(hash, test_sha[i].output, SHA512_DIGEST_SIZE) != 0)
+            return -10 - i;
+    }
+
+    return 0;
+}
+#endif
+
+
+#ifdef WOLFSSL_SHA384
+int sha384_test(void)
+{
+    Sha384 sha;
+    byte   hash[SHA384_DIGEST_SIZE];
+    int    ret;
+
+    testVector a, b;
+    testVector test_sha[2];
+    int times = sizeof(test_sha) / sizeof(struct testVector), i;
+
+    a.input  = "abc";
+    a.output = "\xcb\x00\x75\x3f\x45\xa3\x5e\x8b\xb5\xa0\x3d\x69\x9a\xc6\x50"
+               "\x07\x27\x2c\x32\xab\x0e\xde\xd1\x63\x1a\x8b\x60\x5a\x43\xff"
+               "\x5b\xed\x80\x86\x07\x2b\xa1\xe7\xcc\x23\x58\xba\xec\xa1\x34"
+               "\xc8\x25\xa7";
+    a.inLen  = strlen(a.input);
+    a.outLen = SHA384_DIGEST_SIZE;
+
+    b.input  = "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmnhi"
+               "jklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu";
+    b.output = "\x09\x33\x0c\x33\xf7\x11\x47\xe8\x3d\x19\x2f\xc7\x82\xcd\x1b"
+               "\x47\x53\x11\x1b\x17\x3b\x3b\x05\xd2\x2f\xa0\x80\x86\xe3\xb0"
+               "\xf7\x12\xfc\xc7\xc7\x1a\x55\x7e\x2d\xb9\x66\xc3\xe9\xfa\x91"
+               "\x74\x60\x39";
+    b.inLen  = strlen(b.input);
+    b.outLen = SHA384_DIGEST_SIZE;
+
+    test_sha[0] = a;
+    test_sha[1] = b;
+
+    ret = wc_InitSha384(&sha);
+    if (ret != 0)
+        return -4012;
+
+    for (i = 0; i < times; ++i) {
+        ret = wc_Sha384Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen);
+        if (ret != 0)
+            return -4013;
+
+        ret = wc_Sha384Final(&sha, hash);
+        if (ret != 0)
+            return -4014;
+
+        if (memcmp(hash, test_sha[i].output, SHA384_DIGEST_SIZE) != 0)
+            return -10 - i;
+    }
+
+    return 0;
+}
+#endif /* WOLFSSL_SHA384 */
+
+
+#if !defined(NO_HMAC) && !defined(NO_MD5)
+int hmac_md5_test(void)
+{
+    Hmac hmac;
+    byte hash[MD5_DIGEST_SIZE];
+
+    const char* keys[]=
+    {
+        "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b",
+        "Jefe",
+        "\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA"
+    };
+
+    testVector a, b, c;
+    testVector test_hmac[3];
+
+    int ret;
+    int times = sizeof(test_hmac) / sizeof(testVector), i;
+
+    a.input  = "Hi There";
+    a.output = "\x92\x94\x72\x7a\x36\x38\xbb\x1c\x13\xf4\x8e\xf8\x15\x8b\xfc"
+               "\x9d";
+    a.inLen  = strlen(a.input);
+    a.outLen = MD5_DIGEST_SIZE;
+
+    b.input  = "what do ya want for nothing?";
+    b.output = "\x75\x0c\x78\x3e\x6a\xb0\xb5\x03\xea\xa8\x6e\x31\x0a\x5d\xb7"
+               "\x38";
+    b.inLen  = strlen(b.input);
+    b.outLen = MD5_DIGEST_SIZE;
+
+    c.input  = "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD";
+    c.output = "\x56\xbe\x34\x52\x1d\x14\x4c\x88\xdb\xb8\xc7\x33\xf0\xe8\xb3"
+               "\xf6";
+    c.inLen  = strlen(c.input);
+    c.outLen = MD5_DIGEST_SIZE;
+
+    test_hmac[0] = a;
+    test_hmac[1] = b;
+    test_hmac[2] = c;
+
+    for (i = 0; i < times; ++i) {
+#if defined(HAVE_FIPS) || defined(HAVE_CAVIUM)
+        if (i == 1)
+            continue; /* cavium can't handle short keys, fips not allowed */
+#endif
+#ifdef HAVE_CAVIUM
+        if (wc_HmacInitCavium(&hmac, CAVIUM_DEV_ID) != 0)
+            return -20009;
+#endif
+        ret = wc_HmacSetKey(&hmac, MD5, (byte*)keys[i], (word32)strlen(keys[i]));
+        if (ret != 0)
+            return -4015;
+        ret = wc_HmacUpdate(&hmac, (byte*)test_hmac[i].input,
+                   (word32)test_hmac[i].inLen);
+        if (ret != 0)
+            return -4016;
+        ret = wc_HmacFinal(&hmac, hash);
+        if (ret != 0)
+            return -4017;
+
+        if (memcmp(hash, test_hmac[i].output, MD5_DIGEST_SIZE) != 0)
+            return -20 - i;
+#ifdef HAVE_CAVIUM
+        wc_HmacFreeCavium(&hmac);
+#endif
+    }
+
+    return 0;
+}
+#endif /* NO_HMAC && NO_MD5 */
+
+#if !defined(NO_HMAC) && !defined(NO_SHA)
+int hmac_sha_test(void)
+{
+    Hmac hmac;
+    byte hash[SHA_DIGEST_SIZE];
+
+    const char* keys[]=
+    {
+        "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+                                                                "\x0b\x0b\x0b",
+        "Jefe",
+        "\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA"
+                                                                "\xAA\xAA\xAA"
+    };
+
+    testVector a, b, c;
+    testVector test_hmac[3];
+
+    int ret;
+    int times = sizeof(test_hmac) / sizeof(testVector), i;
+
+    a.input  = "Hi There";
+    a.output = "\xb6\x17\x31\x86\x55\x05\x72\x64\xe2\x8b\xc0\xb6\xfb\x37\x8c"
+               "\x8e\xf1\x46\xbe\x00";
+    a.inLen  = strlen(a.input);
+    a.outLen = SHA_DIGEST_SIZE;
+
+    b.input  = "what do ya want for nothing?";
+    b.output = "\xef\xfc\xdf\x6a\xe5\xeb\x2f\xa2\xd2\x74\x16\xd5\xf1\x84\xdf"
+               "\x9c\x25\x9a\x7c\x79";
+    b.inLen  = strlen(b.input);
+    b.outLen = SHA_DIGEST_SIZE;
+
+    c.input  = "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD";
+    c.output = "\x12\x5d\x73\x42\xb9\xac\x11\xcd\x91\xa3\x9a\xf4\x8a\xa1\x7b"
+               "\x4f\x63\xf1\x75\xd3";
+    c.inLen  = strlen(c.input);
+    c.outLen = SHA_DIGEST_SIZE;
+
+    test_hmac[0] = a;
+    test_hmac[1] = b;
+    test_hmac[2] = c;
+
+    for (i = 0; i < times; ++i) {
+#if defined(HAVE_FIPS) || defined(HAVE_CAVIUM)
+        if (i == 1)
+            continue; /* cavium can't handle short keys, fips not allowed */
+#endif
+#ifdef HAVE_CAVIUM
+        if (wc_HmacInitCavium(&hmac, CAVIUM_DEV_ID) != 0)
+            return -20010;
+#endif
+        ret = wc_HmacSetKey(&hmac, SHA, (byte*)keys[i], (word32)strlen(keys[i]));
+        if (ret != 0)
+            return -4018;
+        ret = wc_HmacUpdate(&hmac, (byte*)test_hmac[i].input,
+                   (word32)test_hmac[i].inLen);
+        if (ret != 0)
+            return -4019;
+        ret = wc_HmacFinal(&hmac, hash);
+        if (ret != 0)
+            return -4020;
+
+        if (memcmp(hash, test_hmac[i].output, SHA_DIGEST_SIZE) != 0)
+            return -20 - i;
+#ifdef HAVE_CAVIUM
+        wc_HmacFreeCavium(&hmac);
+#endif
+    }
+
+    return 0;
+}
+#endif
+
+
+#if !defined(NO_HMAC) && !defined(NO_SHA256)
+int hmac_sha256_test(void)
+{
+    Hmac hmac;
+    byte hash[SHA256_DIGEST_SIZE];
+
+    const char* keys[]=
+    {
+        "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+                                                                "\x0b\x0b\x0b",
+        "Jefe",
+        "\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA"
+                                                                "\xAA\xAA\xAA"
+    };
+
+    testVector a, b, c;
+    testVector test_hmac[3];
+
+    int ret;
+    int times = sizeof(test_hmac) / sizeof(testVector), i;
+
+    a.input  = "Hi There";
+    a.output = "\xb0\x34\x4c\x61\xd8\xdb\x38\x53\x5c\xa8\xaf\xce\xaf\x0b\xf1"
+               "\x2b\x88\x1d\xc2\x00\xc9\x83\x3d\xa7\x26\xe9\x37\x6c\x2e\x32"
+               "\xcf\xf7";
+    a.inLen  = strlen(a.input);
+    a.outLen = SHA256_DIGEST_SIZE;
+
+    b.input  = "what do ya want for nothing?";
+    b.output = "\x5b\xdc\xc1\x46\xbf\x60\x75\x4e\x6a\x04\x24\x26\x08\x95\x75"
+               "\xc7\x5a\x00\x3f\x08\x9d\x27\x39\x83\x9d\xec\x58\xb9\x64\xec"
+               "\x38\x43";
+    b.inLen  = strlen(b.input);
+    b.outLen = SHA256_DIGEST_SIZE;
+
+    c.input  = "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD";
+    c.output = "\x77\x3e\xa9\x1e\x36\x80\x0e\x46\x85\x4d\xb8\xeb\xd0\x91\x81"
+               "\xa7\x29\x59\x09\x8b\x3e\xf8\xc1\x22\xd9\x63\x55\x14\xce\xd5"
+               "\x65\xfe";
+    c.inLen  = strlen(c.input);
+    c.outLen = SHA256_DIGEST_SIZE;
+
+    test_hmac[0] = a;
+    test_hmac[1] = b;
+    test_hmac[2] = c;
+
+    for (i = 0; i < times; ++i) {
+#if defined(HAVE_FIPS) || defined(HAVE_CAVIUM)
+        if (i == 1)
+            continue; /* cavium can't handle short keys, fips not allowed */
+#endif
+#ifdef HAVE_CAVIUM
+        if (wc_HmacInitCavium(&hmac, CAVIUM_DEV_ID) != 0)
+            return -20011;
+#endif
+        ret = wc_HmacSetKey(&hmac, SHA256, (byte*)keys[i],(word32)strlen(keys[i]));
+        if (ret != 0)
+            return -4021;
+        ret = wc_HmacUpdate(&hmac, (byte*)test_hmac[i].input,
+                   (word32)test_hmac[i].inLen);
+        if (ret != 0)
+            return -4022;
+        ret = wc_HmacFinal(&hmac, hash);
+        if (ret != 0)
+            return -4023;
+
+        if (memcmp(hash, test_hmac[i].output, SHA256_DIGEST_SIZE) != 0)
+            return -20 - i;
+#ifdef HAVE_CAVIUM
+        wc_HmacFreeCavium(&hmac);
+#endif
+    }
+
+    return 0;
+}
+#endif
+
+
+#if !defined(NO_HMAC) && defined(HAVE_BLAKE2)
+int hmac_blake2b_test(void)
+{
+    Hmac hmac;
+    byte hash[BLAKE2B_256];
+
+    const char* keys[]=
+    {
+        "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+                                                                "\x0b\x0b\x0b",
+        "Jefe",
+        "\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA"
+                                                                "\xAA\xAA\xAA"
+    };
+
+    testVector a, b, c;
+    testVector test_hmac[3];
+
+    int ret;
+    int times = sizeof(test_hmac) / sizeof(testVector), i;
+
+    a.input  = "Hi There";
+    a.output = "\x72\x93\x0d\xdd\xf5\xf7\xe1\x78\x38\x07\x44\x18\x0b\x3f\x51"
+               "\x37\x25\xb5\x82\xc2\x08\x83\x2f\x1c\x99\xfd\x03\xa0\x16\x75"
+               "\xac\xfd";
+    a.inLen  = strlen(a.input);
+    a.outLen = BLAKE2B_256;
+
+    b.input  = "what do ya want for nothing?";
+    b.output = "\x3d\x20\x50\x71\x05\xc0\x8c\x0c\x38\x44\x1e\xf7\xf9\xd1\x67"
+               "\x21\xff\x64\xf5\x94\x00\xcf\xf9\x75\x41\xda\x88\x61\x9d\x7c"
+               "\xda\x2b";
+    b.inLen  = strlen(b.input);
+    b.outLen = BLAKE2B_256;
+
+    c.input  = "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD";
+    c.output = "\xda\xfe\x2a\x24\xfc\xe7\xea\x36\x34\xbe\x41\x92\xc7\x11\xa7"
+               "\x00\xae\x53\x9c\x11\x9c\x80\x74\x55\x22\x25\x4a\xb9\x55\xd3"
+               "\x0f\x87";
+    c.inLen  = strlen(c.input);
+    c.outLen = BLAKE2B_256;
+
+    test_hmac[0] = a;
+    test_hmac[1] = b;
+    test_hmac[2] = c;
+
+    for (i = 0; i < times; ++i) {
+#if defined(HAVE_FIPS) || defined(HAVE_CAVIUM)
+        if (i == 1)
+            continue; /* cavium can't handle short keys, fips not allowed */
+#endif
+#ifdef HAVE_CAVIUM
+        if (wc_HmacInitCavium(&hmac, CAVIUM_DEV_ID) != 0)
+            return -20011;
+#endif
+        ret = wc_HmacSetKey(&hmac, BLAKE2B_ID, (byte*)keys[i],
+                         (word32)strlen(keys[i]));
+        if (ret != 0)
+            return -4024;
+        ret = wc_HmacUpdate(&hmac, (byte*)test_hmac[i].input,
+                   (word32)test_hmac[i].inLen);
+        if (ret != 0)
+            return -4025;
+        ret = wc_HmacFinal(&hmac, hash);
+        if (ret != 0)
+            return -4026;
+
+        if (memcmp(hash, test_hmac[i].output, BLAKE2B_256) != 0)
+            return -20 - i;
+#ifdef HAVE_CAVIUM
+        wc_HmacFreeCavium(&hmac);
+#endif
+    }
+
+    return 0;
+}
+#endif
+
+
+#if !defined(NO_HMAC) && defined(WOLFSSL_SHA384)
+int hmac_sha384_test(void)
+{
+    Hmac hmac;
+    byte hash[SHA384_DIGEST_SIZE];
+
+    const char* keys[]=
+    {
+        "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+                                                                "\x0b\x0b\x0b",
+        "Jefe",
+        "\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA"
+                                                                "\xAA\xAA\xAA"
+    };
+
+    testVector a, b, c;
+    testVector test_hmac[3];
+
+    int ret;
+    int times = sizeof(test_hmac) / sizeof(testVector), i;
+
+    a.input  = "Hi There";
+    a.output = "\xaf\xd0\x39\x44\xd8\x48\x95\x62\x6b\x08\x25\xf4\xab\x46\x90"
+               "\x7f\x15\xf9\xda\xdb\xe4\x10\x1e\xc6\x82\xaa\x03\x4c\x7c\xeb"
+               "\xc5\x9c\xfa\xea\x9e\xa9\x07\x6e\xde\x7f\x4a\xf1\x52\xe8\xb2"
+               "\xfa\x9c\xb6";
+    a.inLen  = strlen(a.input);
+    a.outLen = SHA384_DIGEST_SIZE;
+
+    b.input  = "what do ya want for nothing?";
+    b.output = "\xaf\x45\xd2\xe3\x76\x48\x40\x31\x61\x7f\x78\xd2\xb5\x8a\x6b"
+               "\x1b\x9c\x7e\xf4\x64\xf5\xa0\x1b\x47\xe4\x2e\xc3\x73\x63\x22"
+               "\x44\x5e\x8e\x22\x40\xca\x5e\x69\xe2\xc7\x8b\x32\x39\xec\xfa"
+               "\xb2\x16\x49";
+    b.inLen  = strlen(b.input);
+    b.outLen = SHA384_DIGEST_SIZE;
+
+    c.input  = "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD";
+    c.output = "\x88\x06\x26\x08\xd3\xe6\xad\x8a\x0a\xa2\xac\xe0\x14\xc8\xa8"
+               "\x6f\x0a\xa6\x35\xd9\x47\xac\x9f\xeb\xe8\x3e\xf4\xe5\x59\x66"
+               "\x14\x4b\x2a\x5a\xb3\x9d\xc1\x38\x14\xb9\x4e\x3a\xb6\xe1\x01"
+               "\xa3\x4f\x27";
+    c.inLen  = strlen(c.input);
+    c.outLen = SHA384_DIGEST_SIZE;
+
+    test_hmac[0] = a;
+    test_hmac[1] = b;
+    test_hmac[2] = c;
+
+    for (i = 0; i < times; ++i) {
+#if defined(HAVE_FIPS)
+        if (i == 1)
+            continue; /* fips not allowed */
+#endif
+        ret = wc_HmacSetKey(&hmac, SHA384, (byte*)keys[i],(word32)strlen(keys[i]));
+        if (ret != 0)
+            return -4027;
+        ret = wc_HmacUpdate(&hmac, (byte*)test_hmac[i].input,
+                   (word32)test_hmac[i].inLen);
+        if (ret != 0)
+            return -4028;
+        ret = wc_HmacFinal(&hmac, hash);
+        if (ret != 0)
+            return -4029;
+
+        if (memcmp(hash, test_hmac[i].output, SHA384_DIGEST_SIZE) != 0)
+            return -20 - i;
+    }
+
+    return 0;
+}
+#endif
+
+
+#if !defined(NO_HMAC) && defined(WOLFSSL_SHA512)
+int hmac_sha512_test(void)
+{
+    Hmac hmac;
+    byte hash[SHA512_DIGEST_SIZE];
+
+    const char* keys[]=
+    {
+        "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+                                                                "\x0b\x0b\x0b",
+        "Jefe",
+        "\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA"
+                                                                "\xAA\xAA\xAA"
+    };
+
+    testVector a, b, c;
+    testVector test_hmac[3];
+
+    int ret;
+    int times = sizeof(test_hmac) / sizeof(testVector), i;
+
+    a.input  = "Hi There";
+    a.output = "\x87\xaa\x7c\xde\xa5\xef\x61\x9d\x4f\xf0\xb4\x24\x1a\x1d\x6c"
+               "\xb0\x23\x79\xf4\xe2\xce\x4e\xc2\x78\x7a\xd0\xb3\x05\x45\xe1"
+               "\x7c\xde\xda\xa8\x33\xb7\xd6\xb8\xa7\x02\x03\x8b\x27\x4e\xae"
+               "\xa3\xf4\xe4\xbe\x9d\x91\x4e\xeb\x61\xf1\x70\x2e\x69\x6c\x20"
+               "\x3a\x12\x68\x54";
+    a.inLen  = strlen(a.input);
+    a.outLen = SHA512_DIGEST_SIZE;
+
+    b.input  = "what do ya want for nothing?";
+    b.output = "\x16\x4b\x7a\x7b\xfc\xf8\x19\xe2\xe3\x95\xfb\xe7\x3b\x56\xe0"
+               "\xa3\x87\xbd\x64\x22\x2e\x83\x1f\xd6\x10\x27\x0c\xd7\xea\x25"
+               "\x05\x54\x97\x58\xbf\x75\xc0\x5a\x99\x4a\x6d\x03\x4f\x65\xf8"
+               "\xf0\xe6\xfd\xca\xea\xb1\xa3\x4d\x4a\x6b\x4b\x63\x6e\x07\x0a"
+               "\x38\xbc\xe7\x37";
+    b.inLen  = strlen(b.input);
+    b.outLen = SHA512_DIGEST_SIZE;
+
+    c.input  = "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD";
+    c.output = "\xfa\x73\xb0\x08\x9d\x56\xa2\x84\xef\xb0\xf0\x75\x6c\x89\x0b"
+               "\xe9\xb1\xb5\xdb\xdd\x8e\xe8\x1a\x36\x55\xf8\x3e\x33\xb2\x27"
+               "\x9d\x39\xbf\x3e\x84\x82\x79\xa7\x22\xc8\x06\xb4\x85\xa4\x7e"
+               "\x67\xc8\x07\xb9\x46\xa3\x37\xbe\xe8\x94\x26\x74\x27\x88\x59"
+               "\xe1\x32\x92\xfb";
+    c.inLen  = strlen(c.input);
+    c.outLen = SHA512_DIGEST_SIZE;
+
+    test_hmac[0] = a;
+    test_hmac[1] = b;
+    test_hmac[2] = c;
+
+    for (i = 0; i < times; ++i) {
+#if defined(HAVE_FIPS)
+        if (i == 1)
+            continue; /* fips not allowed */
+#endif
+        ret = wc_HmacSetKey(&hmac, SHA512, (byte*)keys[i],(word32)strlen(keys[i]));
+        if (ret != 0)
+            return -4030;
+        ret = wc_HmacUpdate(&hmac, (byte*)test_hmac[i].input,
+                   (word32)test_hmac[i].inLen);
+        if (ret != 0)
+            return -4031;
+        ret = wc_HmacFinal(&hmac, hash);
+        if (ret != 0)
+            return -4032;
+
+        if (memcmp(hash, test_hmac[i].output, SHA512_DIGEST_SIZE) != 0)
+            return -20 - i;
+    }
+
+    return 0;
+}
+#endif
+
+
+#ifndef NO_RC4
+int arc4_test(void)
+{
+    byte cipher[16];
+    byte plain[16];
+
+    const char* keys[] =
+    {
+        "\x01\x23\x45\x67\x89\xab\xcd\xef",
+        "\x01\x23\x45\x67\x89\xab\xcd\xef",
+        "\x00\x00\x00\x00\x00\x00\x00\x00",
+        "\xef\x01\x23\x45"
+    };
+
+    testVector a, b, c, d;
+    testVector test_arc4[4];
+
+    int times = sizeof(test_arc4) / sizeof(testVector), i;
+
+    a.input  = "\x01\x23\x45\x67\x89\xab\xcd\xef";
+    a.output = "\x75\xb7\x87\x80\x99\xe0\xc5\x96";
+    a.inLen  = 8;
+    a.outLen = 8;
+
+    b.input  = "\x00\x00\x00\x00\x00\x00\x00\x00";
+    b.output = "\x74\x94\xc2\xe7\x10\x4b\x08\x79";
+    b.inLen  = 8;
+    b.outLen = 8;
+
+    c.input  = "\x00\x00\x00\x00\x00\x00\x00\x00";
+    c.output = "\xde\x18\x89\x41\xa3\x37\x5d\x3a";
+    c.inLen  = 8;
+    c.outLen = 8;
+
+    d.input  = "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00";
+    d.output = "\xd6\xa1\x41\xa7\xec\x3c\x38\xdf\xbd\x61";
+    d.inLen  = 10;
+    d.outLen = 10;
+
+    test_arc4[0] = a;
+    test_arc4[1] = b;
+    test_arc4[2] = c;
+    test_arc4[3] = d;
+
+    for (i = 0; i < times; ++i) {
+        Arc4 enc;
+        Arc4 dec;
+        int  keylen = 8;  /* strlen with key 0x00 not good */
+        if (i == 3)
+            keylen = 4;
+
+#ifdef HAVE_CAVIUM
+        if (wc_Arc4InitCavium(&enc, CAVIUM_DEV_ID) != 0)
+            return -20001;
+        if (wc_Arc4InitCavium(&dec, CAVIUM_DEV_ID) != 0)
+            return -20002;
+#endif
+
+        wc_Arc4SetKey(&enc, (byte*)keys[i], keylen);
+        wc_Arc4SetKey(&dec, (byte*)keys[i], keylen);
+
+        wc_Arc4Process(&enc, cipher, (byte*)test_arc4[i].input,
+                    (word32)test_arc4[i].outLen);
+        wc_Arc4Process(&dec, plain,  cipher, (word32)test_arc4[i].outLen);
+
+        if (memcmp(plain, test_arc4[i].input, test_arc4[i].outLen))
+            return -20 - i;
+
+        if (memcmp(cipher, test_arc4[i].output, test_arc4[i].outLen))
+            return -20 - 5 - i;
+
+#ifdef HAVE_CAVIUM
+        wc_Arc4FreeCavium(&enc);
+        wc_Arc4FreeCavium(&dec);
+#endif
+    }
+
+    return 0;
+}
+#endif
+
+
+int hc128_test(void)
+{
+#ifdef HAVE_HC128
+    byte cipher[16];
+    byte plain[16];
+
+    const char* keys[] =
+    {
+        "\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00",
+        "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00",
+        "\x00\x53\xA6\xF9\x4C\x9F\xF2\x45\x98\xEB\x3E\x91\xE4\x37\x8A\xDD",
+        "\x0F\x62\xB5\x08\x5B\xAE\x01\x54\xA7\xFA\x4D\xA0\xF3\x46\x99\xEC"
+    };
+
+    const char* ivs[] =
+    {
+        "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00",
+        "\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00",
+        "\x0D\x74\xDB\x42\xA9\x10\x77\xDE\x45\xAC\x13\x7A\xE1\x48\xAF\x16",
+        "\x28\x8F\xF6\x5D\xC4\x2B\x92\xF9\x60\xC7\x2E\x95\xFC\x63\xCA\x31"
+    };
+
+
+    testVector a, b, c, d;
+    testVector test_hc128[4];
+
+    int times = sizeof(test_hc128) / sizeof(testVector), i;
+
+    a.input  = "\x00\x00\x00\x00\x00\x00\x00\x00";
+    a.output = "\x37\x86\x02\xB9\x8F\x32\xA7\x48";
+    a.inLen  = 8;
+    a.outLen = 8;
+
+    b.input  = "\x00\x00\x00\x00\x00\x00\x00\x00";
+    b.output = "\x33\x7F\x86\x11\xC6\xED\x61\x5F";
+    b.inLen  = 8;
+    b.outLen = 8;
+
+    c.input  = "\x00\x00\x00\x00\x00\x00\x00\x00";
+    c.output = "\x2E\x1E\xD1\x2A\x85\x51\xC0\x5A";
+    c.inLen  = 8;
+    c.outLen = 8;
+
+    d.input  = "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00";
+    d.output = "\x1C\xD8\xAE\xDD\xFE\x52\xE2\x17\xE8\x35\xD0\xB7\xE8\x4E\x29";
+    d.inLen  = 15;
+    d.outLen = 15;
+
+    test_hc128[0] = a;
+    test_hc128[1] = b;
+    test_hc128[2] = c;
+    test_hc128[3] = d;
+
+    for (i = 0; i < times; ++i) {
+        HC128 enc;
+        HC128 dec;
+
+        /* align keys/ivs in plain/cipher buffers */
+        memcpy(plain,  keys[i], 16);
+        memcpy(cipher, ivs[i],  16);
+
+        wc_Hc128_SetKey(&enc, plain, cipher);
+        wc_Hc128_SetKey(&dec, plain, cipher);
+
+        /* align input */
+        memcpy(plain, test_hc128[i].input, test_hc128[i].outLen);
+        wc_Hc128_Process(&enc, cipher, plain,  (word32)test_hc128[i].outLen);
+        wc_Hc128_Process(&dec, plain,  cipher, (word32)test_hc128[i].outLen);
+
+        if (memcmp(plain, test_hc128[i].input, test_hc128[i].outLen))
+            return -120 - i;
+
+        if (memcmp(cipher, test_hc128[i].output, test_hc128[i].outLen))
+            return -120 - 5 - i;
+    }
+
+#endif /* HAVE_HC128 */
+    return 0;
+}
+
+
+#ifndef NO_RABBIT
+int rabbit_test(void)
+{
+    byte cipher[16];
+    byte plain[16];
+
+    const char* keys[] =
+    {
+        "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00",
+        "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00",
+        "\xAC\xC3\x51\xDC\xF1\x62\xFC\x3B\xFE\x36\x3D\x2E\x29\x13\x28\x91"
+    };
+
+    const char* ivs[] =
+    {
+        "\x00\x00\x00\x00\x00\x00\x00\x00",
+        "\x59\x7E\x26\xC1\x75\xF5\x73\xC3",
+        0
+    };
+
+    testVector a, b, c;
+    testVector test_rabbit[3];
+
+    int times = sizeof(test_rabbit) / sizeof(testVector), i;
+
+    a.input  = "\x00\x00\x00\x00\x00\x00\x00\x00";
+    a.output = "\xED\xB7\x05\x67\x37\x5D\xCD\x7C";
+    a.inLen  = 8;
+    a.outLen = 8;
+
+    b.input  = "\x00\x00\x00\x00\x00\x00\x00\x00";
+    b.output = "\x6D\x7D\x01\x22\x92\xCC\xDC\xE0";
+    b.inLen  = 8;
+    b.outLen = 8;
+
+    c.input  = "\x00\x00\x00\x00\x00\x00\x00\x00";
+    c.output = "\x04\xCE\xCA\x7A\x1A\x86\x6E\x77";
+    c.inLen  = 8;
+    c.outLen = 8;
+
+    test_rabbit[0] = a;
+    test_rabbit[1] = b;
+    test_rabbit[2] = c;
+
+    for (i = 0; i < times; ++i) {
+        Rabbit enc;
+        Rabbit dec;
+        byte*  iv;
+
+        /* align keys/ivs in plain/cipher buffers */
+        memcpy(plain,  keys[i], 16);
+        if (ivs[i]) {
+            memcpy(cipher, ivs[i],   8);
+            iv = cipher;
+        } else
+            iv = NULL;
+        wc_RabbitSetKey(&enc, plain, iv);
+        wc_RabbitSetKey(&dec, plain, iv);
+
+        /* align input */
+        memcpy(plain, test_rabbit[i].input, test_rabbit[i].outLen);
+        wc_RabbitProcess(&enc, cipher, plain,  (word32)test_rabbit[i].outLen);
+        wc_RabbitProcess(&dec, plain,  cipher, (word32)test_rabbit[i].outLen);
+
+        if (memcmp(plain, test_rabbit[i].input, test_rabbit[i].outLen))
+            return -130 - i;
+
+        if (memcmp(cipher, test_rabbit[i].output, test_rabbit[i].outLen))
+            return -130 - 5 - i;
+    }
+
+    return 0;
+}
+#endif /* NO_RABBIT */
+
+
+#ifdef HAVE_CHACHA
+int chacha_test(void)
+{
+    ChaCha enc;
+    ChaCha dec;
+    byte   cipher[32];
+    byte   plain[32];
+    byte   input[] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+    word32 keySz;
+    int    i;
+    int    times = 4;
+
+    static const byte key1[] =
+    {
+         0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+         0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+         0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+         0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+    };
+
+    static const byte key2[] =
+    {
+         0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+         0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+         0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+         0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01
+    };
+
+    static const byte key3[] =
+    {
+         0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+         0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+         0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+         0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+    };
+
+    /* 128 bit key */
+    static const byte key4[] =
+    {
+         0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+         0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+    };
+
+
+    const byte* keys[] = {key1, key2, key3, key4};
+
+    static const byte ivs1[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
+    static const byte ivs2[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
+    static const byte ivs3[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01};
+    static const byte ivs4[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
+
+
+    const byte* ivs[] = {ivs1, ivs2, ivs3, ivs4};
+
+
+    byte a[] = {0x76,0xb8,0xe0,0xad,0xa0,0xf1,0x3d,0x90};
+    byte b[] = {0x45,0x40,0xf0,0x5a,0x9f,0x1f,0xb2,0x96};
+    byte c[] = {0xde,0x9c,0xba,0x7b,0xf3,0xd6,0x9e,0xf5};
+    byte d[] = {0x89,0x67,0x09,0x52,0x60,0x83,0x64,0xfd};
+
+    byte* test_chacha[4];
+
+    test_chacha[0] = a;
+    test_chacha[1] = b;
+    test_chacha[2] = c;
+    test_chacha[3] = d;
+
+    for (i = 0; i < times; ++i) {
+        if (i < 3) {
+            keySz = 32;
+        }
+        else {
+            keySz = 16;
+        }
+
+        XMEMCPY(plain, keys[i], keySz);
+        XMEMSET(cipher, 0, 32);
+        XMEMCPY(cipher + 4, ivs[i], 8);
+
+        wc_Chacha_SetKey(&enc, keys[i], keySz);
+        wc_Chacha_SetKey(&dec, keys[i], keySz);
+
+        wc_Chacha_SetIV(&enc, cipher, 0);
+        wc_Chacha_SetIV(&dec, cipher, 0);
+        XMEMCPY(plain, input, 8);
+
+        wc_Chacha_Process(&enc, cipher, plain,  (word32)8);
+        wc_Chacha_Process(&dec, plain,  cipher, (word32)8);
+
+        if (memcmp(test_chacha[i], cipher, 8))
+            return -130 - 5 - i;
+
+        if (memcmp(plain, input, 8))
+            return -130 - i;
+    }
+
+    return 0;
+}
+#endif /* HAVE_CHACHA */
+
+
+#ifdef HAVE_POLY1305
+int poly1305_test(void)
+{
+    int      ret = 0;
+    int      i;
+    byte     tag[16];
+    Poly1305 enc;
+
+    const byte msg[] =
+    {
+        0x43,0x72,0x79,0x70,0x74,0x6f,0x67,0x72,
+        0x61,0x70,0x68,0x69,0x63,0x20,0x46,0x6f,
+        0x72,0x75,0x6d,0x20,0x52,0x65,0x73,0x65,
+        0x61,0x72,0x63,0x68,0x20,0x47,0x72,0x6f,
+        0x75,0x70
+    };
+
+    const byte msg2[] =
+    {
+        0x48,0x65,0x6c,0x6c,0x6f,0x20,0x77,0x6f,0x72,
+        0x6c,0x64,0x21
+    };
+
+    const byte msg3[] =
+    {
+        0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+        0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+        0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+        0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+    };
+
+    const byte correct[] =
+    {
+        0xa8,0x06,0x1d,0xc1,0x30,0x51,0x36,0xc6,
+        0xc2,0x2b,0x8b,0xaf,0x0c,0x01,0x27,0xa9
+
+    };
+
+    const byte correct2[] =
+    {
+        0xa6,0xf7,0x45,0x00,0x8f,0x81,0xc9,0x16,
+        0xa2,0x0d,0xcc,0x74,0xee,0xf2,0xb2,0xf0
+    };
+
+    const byte correct3[] =
+    {
+        0x49,0xec,0x78,0x09,0x0e,0x48,0x1e,0xc6,
+        0xc2,0x6b,0x33,0xb9,0x1c,0xcc,0x03,0x07
+    };
+
+    const byte key[] = {
+        0x85,0xd6,0xbe,0x78,0x57,0x55,0x6d,0x33,
+        0x7f,0x44,0x52,0xfe,0x42,0xd5,0x06,0xa8,
+        0x01,0x03,0x80,0x8a,0xfb,0x0d,0xb2,0xfd,
+        0x4a,0xbf,0xf6,0xaf,0x41,0x49,0xf5,0x1b
+    };
+
+    const byte key2[] = {
+        0x74,0x68,0x69,0x73,0x20,0x69,0x73,0x20,
+        0x33,0x32,0x2d,0x62,0x79,0x74,0x65,0x20,
+        0x6b,0x65,0x79,0x20,0x66,0x6f,0x72,0x20,
+        0x50,0x6f,0x6c,0x79,0x31,0x33,0x30,0x35
+    };
+
+    const byte* msgs[]  = {msg, msg2, msg3};
+    word32      szm[]   = {sizeof(msg),sizeof(msg2),sizeof(msg3)};
+    const byte* keys[]  = {key, key2, key2};
+    const byte* tests[] = {correct, correct2, correct3};
+
+    for (i = 0; i < 3; i++) {
+        ret = wc_Poly1305SetKey(&enc, keys[i], 32);
+        if (ret != 0)
+            return -1001;
+
+        ret = wc_Poly1305Update(&enc, msgs[i], szm[i]);
+        if (ret != 0)
+            return -1005;
+
+        ret = wc_Poly1305Final(&enc, tag);
+        if (ret != 0)
+            return -60;
+
+        if (memcmp(tag, tests[i], sizeof(tag)))
+            return -61;
+    }
+
+    return 0;
+}
+#endif /* HAVE_POLY1305 */
+
+
+#if defined(HAVE_CHACHA) && defined(HAVE_POLY1305)
+int chacha20_poly1305_aead_test(void)
+{
+    /* Test #1 from Section 2.8.2 of draft-irtf-cfrg-chacha20-poly1305-10 */
+    /* https://tools.ietf.org/html/draft-irtf-cfrg-chacha20-poly1305-10  */
+
+    const byte key1[] = {
+        0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
+        0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
+        0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
+        0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f
+    };
+
+    const byte plaintext1[] = {
+        0x4c, 0x61, 0x64, 0x69, 0x65, 0x73, 0x20, 0x61,
+        0x6e, 0x64, 0x20, 0x47, 0x65, 0x6e, 0x74, 0x6c,
+        0x65, 0x6d, 0x65, 0x6e, 0x20, 0x6f, 0x66, 0x20,
+        0x74, 0x68, 0x65, 0x20, 0x63, 0x6c, 0x61, 0x73,
+        0x73, 0x20, 0x6f, 0x66, 0x20, 0x27, 0x39, 0x39,
+        0x3a, 0x20, 0x49, 0x66, 0x20, 0x49, 0x20, 0x63,
+        0x6f, 0x75, 0x6c, 0x64, 0x20, 0x6f, 0x66, 0x66,
+        0x65, 0x72, 0x20, 0x79, 0x6f, 0x75, 0x20, 0x6f,
+        0x6e, 0x6c, 0x79, 0x20, 0x6f, 0x6e, 0x65, 0x20,
+        0x74, 0x69, 0x70, 0x20, 0x66, 0x6f, 0x72, 0x20,
+        0x74, 0x68, 0x65, 0x20, 0x66, 0x75, 0x74, 0x75,
+        0x72, 0x65, 0x2c, 0x20, 0x73, 0x75, 0x6e, 0x73,
+        0x63, 0x72, 0x65, 0x65, 0x6e, 0x20, 0x77, 0x6f,
+        0x75, 0x6c, 0x64, 0x20, 0x62, 0x65, 0x20, 0x69,
+        0x74, 0x2e
+    };
+
+    const byte iv1[] = {
+        0x07, 0x00, 0x00, 0x00, 0x40, 0x41, 0x42, 0x43,
+        0x44, 0x45, 0x46, 0x47
+    };
+
+    const byte aad1[] = { /* additional data */
+        0x50, 0x51, 0x52, 0x53, 0xc0, 0xc1, 0xc2, 0xc3,
+        0xc4, 0xc5, 0xc6, 0xc7
+    };
+
+    const byte cipher1[] = { /* expected output from operation */
+        0xd3, 0x1a, 0x8d, 0x34, 0x64, 0x8e, 0x60, 0xdb,
+        0x7b, 0x86, 0xaf, 0xbc, 0x53, 0xef, 0x7e, 0xc2,
+        0xa4, 0xad, 0xed, 0x51, 0x29, 0x6e, 0x08, 0xfe,
+        0xa9, 0xe2, 0xb5, 0xa7, 0x36, 0xee, 0x62, 0xd6,
+        0x3d, 0xbe, 0xa4, 0x5e, 0x8c, 0xa9, 0x67, 0x12,
+        0x82, 0xfa, 0xfb, 0x69, 0xda, 0x92, 0x72, 0x8b,
+        0x1a, 0x71, 0xde, 0x0a, 0x9e, 0x06, 0x0b, 0x29,
+        0x05, 0xd6, 0xa5, 0xb6, 0x7e, 0xcd, 0x3b, 0x36,
+        0x92, 0xdd, 0xbd, 0x7f, 0x2d, 0x77, 0x8b, 0x8c,
+        0x98, 0x03, 0xae, 0xe3, 0x28, 0x09, 0x1b, 0x58,
+        0xfa, 0xb3, 0x24, 0xe4, 0xfa, 0xd6, 0x75, 0x94,
+        0x55, 0x85, 0x80, 0x8b, 0x48, 0x31, 0xd7, 0xbc,
+        0x3f, 0xf4, 0xde, 0xf0, 0x8e, 0x4b, 0x7a, 0x9d,
+        0xe5, 0x76, 0xd2, 0x65, 0x86, 0xce, 0xc6, 0x4b,
+        0x61, 0x16
+    };
+
+    const byte authTag1[] = { /* expected output from operation */
+        0x1a, 0xe1, 0x0b, 0x59, 0x4f, 0x09, 0xe2, 0x6a,
+        0x7e, 0x90, 0x2e, 0xcb, 0xd0, 0x60, 0x06, 0x91
+    };
+
+    /* Test #2 from Appendix A.2 in draft-irtf-cfrg-chacha20-poly1305-10 */
+    /* https://tools.ietf.org/html/draft-irtf-cfrg-chacha20-poly1305-10  */
+
+    const byte key2[] = {
+        0x1c, 0x92, 0x40, 0xa5, 0xeb, 0x55, 0xd3, 0x8a,
+        0xf3, 0x33, 0x88, 0x86, 0x04, 0xf6, 0xb5, 0xf0,
+        0x47, 0x39, 0x17, 0xc1, 0x40, 0x2b, 0x80, 0x09,
+        0x9d, 0xca, 0x5c, 0xbc, 0x20, 0x70, 0x75, 0xc0
+    };
+
+    const byte plaintext2[] = {
+        0x49, 0x6e, 0x74, 0x65, 0x72, 0x6e, 0x65, 0x74,
+        0x2d, 0x44, 0x72, 0x61, 0x66, 0x74, 0x73, 0x20,
+        0x61, 0x72, 0x65, 0x20, 0x64, 0x72, 0x61, 0x66,
+        0x74, 0x20, 0x64, 0x6f, 0x63, 0x75, 0x6d, 0x65,
+        0x6e, 0x74, 0x73, 0x20, 0x76, 0x61, 0x6c, 0x69,
+        0x64, 0x20, 0x66, 0x6f, 0x72, 0x20, 0x61, 0x20,
+        0x6d, 0x61, 0x78, 0x69, 0x6d, 0x75, 0x6d, 0x20,
+        0x6f, 0x66, 0x20, 0x73, 0x69, 0x78, 0x20, 0x6d,
+        0x6f, 0x6e, 0x74, 0x68, 0x73, 0x20, 0x61, 0x6e,
+        0x64, 0x20, 0x6d, 0x61, 0x79, 0x20, 0x62, 0x65,
+        0x20, 0x75, 0x70, 0x64, 0x61, 0x74, 0x65, 0x64,
+        0x2c, 0x20, 0x72, 0x65, 0x70, 0x6c, 0x61, 0x63,
+        0x65, 0x64, 0x2c, 0x20, 0x6f, 0x72, 0x20, 0x6f,
+        0x62, 0x73, 0x6f, 0x6c, 0x65, 0x74, 0x65, 0x64,
+        0x20, 0x62, 0x79, 0x20, 0x6f, 0x74, 0x68, 0x65,
+        0x72, 0x20, 0x64, 0x6f, 0x63, 0x75, 0x6d, 0x65,
+        0x6e, 0x74, 0x73, 0x20, 0x61, 0x74, 0x20, 0x61,
+        0x6e, 0x79, 0x20, 0x74, 0x69, 0x6d, 0x65, 0x2e,
+        0x20, 0x49, 0x74, 0x20, 0x69, 0x73, 0x20, 0x69,
+        0x6e, 0x61, 0x70, 0x70, 0x72, 0x6f, 0x70, 0x72,
+        0x69, 0x61, 0x74, 0x65, 0x20, 0x74, 0x6f, 0x20,
+        0x75, 0x73, 0x65, 0x20, 0x49, 0x6e, 0x74, 0x65,
+        0x72, 0x6e, 0x65, 0x74, 0x2d, 0x44, 0x72, 0x61,
+        0x66, 0x74, 0x73, 0x20, 0x61, 0x73, 0x20, 0x72,
+        0x65, 0x66, 0x65, 0x72, 0x65, 0x6e, 0x63, 0x65,
+        0x20, 0x6d, 0x61, 0x74, 0x65, 0x72, 0x69, 0x61,
+        0x6c, 0x20, 0x6f, 0x72, 0x20, 0x74, 0x6f, 0x20,
+        0x63, 0x69, 0x74, 0x65, 0x20, 0x74, 0x68, 0x65,
+        0x6d, 0x20, 0x6f, 0x74, 0x68, 0x65, 0x72, 0x20,
+        0x74, 0x68, 0x61, 0x6e, 0x20, 0x61, 0x73, 0x20,
+        0x2f, 0xe2, 0x80, 0x9c, 0x77, 0x6f, 0x72, 0x6b,
+        0x20, 0x69, 0x6e, 0x20, 0x70, 0x72, 0x6f, 0x67,
+        0x72, 0x65, 0x73, 0x73, 0x2e, 0x2f, 0xe2, 0x80,
+        0x9d
+    };
+
+    const byte iv2[] = {
+        0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04,
+        0x05, 0x06, 0x07, 0x08
+    };
+
+    const byte aad2[] = { /* additional data */
+        0xf3, 0x33, 0x88, 0x86, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x4e, 0x91
+    };
+
+    const byte cipher2[] = { /* expected output from operation */
+        0x64, 0xa0, 0x86, 0x15, 0x75, 0x86, 0x1a, 0xf4,
+        0x60, 0xf0, 0x62, 0xc7, 0x9b, 0xe6, 0x43, 0xbd,
+        0x5e, 0x80, 0x5c, 0xfd, 0x34, 0x5c, 0xf3, 0x89,
+        0xf1, 0x08, 0x67, 0x0a, 0xc7, 0x6c, 0x8c, 0xb2,
+        0x4c, 0x6c, 0xfc, 0x18, 0x75, 0x5d, 0x43, 0xee,
+        0xa0, 0x9e, 0xe9, 0x4e, 0x38, 0x2d, 0x26, 0xb0,
+        0xbd, 0xb7, 0xb7, 0x3c, 0x32, 0x1b, 0x01, 0x00,
+        0xd4, 0xf0, 0x3b, 0x7f, 0x35, 0x58, 0x94, 0xcf,
+        0x33, 0x2f, 0x83, 0x0e, 0x71, 0x0b, 0x97, 0xce,
+        0x98, 0xc8, 0xa8, 0x4a, 0xbd, 0x0b, 0x94, 0x81,
+        0x14, 0xad, 0x17, 0x6e, 0x00, 0x8d, 0x33, 0xbd,
+        0x60, 0xf9, 0x82, 0xb1, 0xff, 0x37, 0xc8, 0x55,
+        0x97, 0x97, 0xa0, 0x6e, 0xf4, 0xf0, 0xef, 0x61,
+        0xc1, 0x86, 0x32, 0x4e, 0x2b, 0x35, 0x06, 0x38,
+        0x36, 0x06, 0x90, 0x7b, 0x6a, 0x7c, 0x02, 0xb0,
+        0xf9, 0xf6, 0x15, 0x7b, 0x53, 0xc8, 0x67, 0xe4,
+        0xb9, 0x16, 0x6c, 0x76, 0x7b, 0x80, 0x4d, 0x46,
+        0xa5, 0x9b, 0x52, 0x16, 0xcd, 0xe7, 0xa4, 0xe9,
+        0x90, 0x40, 0xc5, 0xa4, 0x04, 0x33, 0x22, 0x5e,
+        0xe2, 0x82, 0xa1, 0xb0, 0xa0, 0x6c, 0x52, 0x3e,
+        0xaf, 0x45, 0x34, 0xd7, 0xf8, 0x3f, 0xa1, 0x15,
+        0x5b, 0x00, 0x47, 0x71, 0x8c, 0xbc, 0x54, 0x6a,
+        0x0d, 0x07, 0x2b, 0x04, 0xb3, 0x56, 0x4e, 0xea,
+        0x1b, 0x42, 0x22, 0x73, 0xf5, 0x48, 0x27, 0x1a,
+        0x0b, 0xb2, 0x31, 0x60, 0x53, 0xfa, 0x76, 0x99,
+        0x19, 0x55, 0xeb, 0xd6, 0x31, 0x59, 0x43, 0x4e,
+        0xce, 0xbb, 0x4e, 0x46, 0x6d, 0xae, 0x5a, 0x10,
+        0x73, 0xa6, 0x72, 0x76, 0x27, 0x09, 0x7a, 0x10,
+        0x49, 0xe6, 0x17, 0xd9, 0x1d, 0x36, 0x10, 0x94,
+        0xfa, 0x68, 0xf0, 0xff, 0x77, 0x98, 0x71, 0x30,
+        0x30, 0x5b, 0xea, 0xba, 0x2e, 0xda, 0x04, 0xdf,
+        0x99, 0x7b, 0x71, 0x4d, 0x6c, 0x6f, 0x2c, 0x29,
+        0xa6, 0xad, 0x5c, 0xb4, 0x02, 0x2b, 0x02, 0x70,
+        0x9b
+    };
+
+    const byte authTag2[] = { /* expected output from operation */
+        0xee, 0xad, 0x9d, 0x67, 0x89, 0x0c, 0xbb, 0x22,
+        0x39, 0x23, 0x36, 0xfe, 0xa1, 0x85, 0x1f, 0x38
+    };
+
+    byte generatedCiphertext[272];
+    byte generatedPlaintext[272];
+    byte generatedAuthTag[CHACHA20_POLY1305_AEAD_AUTHTAG_SIZE];
+    int err;
+
+    XMEMSET(generatedCiphertext, 0, sizeof(generatedCiphertext));
+    XMEMSET(generatedAuthTag, 0, sizeof(generatedAuthTag));
+    XMEMSET(generatedPlaintext, 0, sizeof(generatedPlaintext));
+
+    /* Test #1 */
+
+    err = wc_ChaCha20Poly1305_Encrypt(key1, iv1,
+                                       aad1, sizeof(aad1),
+                                       plaintext1, sizeof(plaintext1),
+                                       generatedCiphertext, generatedAuthTag);
+    if (err)
+    {
+        return err;
+    }
+
+    /* -- Check the ciphertext and authtag */
+
+    if (XMEMCMP(generatedCiphertext, cipher1, sizeof(cipher1)))
+    {
+        return -1064;
+    }
+
+    if (XMEMCMP(generatedAuthTag, authTag1, sizeof(authTag1)))
+    {
+        return -1065;
+    }
+
+    /* -- Verify decryption works */
+
+    err = wc_ChaCha20Poly1305_Decrypt(key1, iv1,
+                                       aad1, sizeof(aad1),
+                                       cipher1, sizeof(cipher1),
+                                       authTag1, generatedPlaintext);
+    if (err)
+    {
+        return err;
+    }
+
+    if (XMEMCMP(generatedPlaintext, plaintext1, sizeof( plaintext1)))
+    {
+        return -1066;
+    }
+
+    XMEMSET(generatedCiphertext, 0, sizeof(generatedCiphertext));
+    XMEMSET(generatedAuthTag, 0, sizeof(generatedAuthTag));
+    XMEMSET(generatedPlaintext, 0, sizeof(generatedPlaintext));
+
+    /* Test #2 */
+
+    err = wc_ChaCha20Poly1305_Encrypt(key2, iv2,
+                                       aad2, sizeof(aad2),
+                                       plaintext2, sizeof(plaintext2),
+                                       generatedCiphertext, generatedAuthTag);
+    if (err)
+    {
+        return err;
+    }
+
+    /* -- Check the ciphertext and authtag */
+
+    if (XMEMCMP(generatedCiphertext, cipher2, sizeof(cipher2)))
+    {
+        return -1067;
+    }
+
+    if (XMEMCMP(generatedAuthTag, authTag2, sizeof(authTag2)))
+    {
+        return -1068;
+    }
+
+    /* -- Verify decryption works */
+
+    err = wc_ChaCha20Poly1305_Decrypt(key2, iv2,
+                                      aad2, sizeof(aad2),
+                                      cipher2, sizeof(cipher2),
+                                      authTag2, generatedPlaintext);
+    if (err)
+    {
+        return err;
+    }
+
+    if (XMEMCMP(generatedPlaintext, plaintext2, sizeof(plaintext2)))
+    {
+        return -1069;
+    }
+
+    return err;
+}
+#endif /* HAVE_CHACHA && HAVE_POLY1305 */
+
+
+#ifndef NO_DES3
+int des_test(void)
+{
+    const byte vector[] = { /* "now is the time for all " w/o trailing 0 */
+        0x6e,0x6f,0x77,0x20,0x69,0x73,0x20,0x74,
+        0x68,0x65,0x20,0x74,0x69,0x6d,0x65,0x20,
+        0x66,0x6f,0x72,0x20,0x61,0x6c,0x6c,0x20
+    };
+
+    byte plain[24];
+    byte cipher[24];
+
+    Des enc;
+    Des dec;
+
+    const byte key[] =
+    {
+        0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef
+    };
+
+    const byte iv[] =
+    {
+        0x12,0x34,0x56,0x78,0x90,0xab,0xcd,0xef
+    };
+
+    const byte verify[] =
+    {
+        0x8b,0x7c,0x52,0xb0,0x01,0x2b,0x6c,0xb8,
+        0x4f,0x0f,0xeb,0xf3,0xfb,0x5f,0x86,0x73,
+        0x15,0x85,0xb3,0x22,0x4b,0x86,0x2b,0x4b
+    };
+
+    int ret;
+
+    ret = wc_Des_SetKey(&enc, key, iv, DES_ENCRYPTION);
+    if (ret != 0)
+        return -31;
+
+    wc_Des_CbcEncrypt(&enc, cipher, vector, sizeof(vector));
+    ret = wc_Des_SetKey(&dec, key, iv, DES_DECRYPTION);
+    if (ret != 0)
+        return -32;
+    wc_Des_CbcDecrypt(&dec, plain, cipher, sizeof(cipher));
+
+    if (memcmp(plain, vector, sizeof(plain)))
+        return -33;
+
+    if (memcmp(cipher, verify, sizeof(cipher)))
+        return -34;
+
+    return 0;
+}
+#endif /* NO_DES3 */
+
+
+#ifndef NO_DES3
+int des3_test(void)
+{
+    const byte vector[] = { /* "Now is the time for all " w/o trailing 0 */
+        0x4e,0x6f,0x77,0x20,0x69,0x73,0x20,0x74,
+        0x68,0x65,0x20,0x74,0x69,0x6d,0x65,0x20,
+        0x66,0x6f,0x72,0x20,0x61,0x6c,0x6c,0x20
+    };
+
+    byte plain[24];
+    byte cipher[24];
+
+    Des3 enc;
+    Des3 dec;
+
+    const byte key3[] =
+    {
+        0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef,
+        0xfe,0xde,0xba,0x98,0x76,0x54,0x32,0x10,
+        0x89,0xab,0xcd,0xef,0x01,0x23,0x45,0x67
+    };
+    const byte iv3[] =
+    {
+        0x12,0x34,0x56,0x78,0x90,0xab,0xcd,0xef,
+        0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
+        0x11,0x21,0x31,0x41,0x51,0x61,0x71,0x81
+
+    };
+
+    const byte verify3[] =
+    {
+        0x43,0xa0,0x29,0x7e,0xd1,0x84,0xf8,0x0e,
+        0x89,0x64,0x84,0x32,0x12,0xd5,0x08,0x98,
+        0x18,0x94,0x15,0x74,0x87,0x12,0x7d,0xb0
+    };
+
+    int ret;
+
+
+#ifdef HAVE_CAVIUM
+    if (wc_Des3_InitCavium(&enc, CAVIUM_DEV_ID) != 0)
+        return -20005;
+    if (wc_Des3_InitCavium(&dec, CAVIUM_DEV_ID) != 0)
+        return -20006;
+#endif
+    ret = wc_Des3_SetKey(&enc, key3, iv3, DES_ENCRYPTION);
+    if (ret != 0)
+        return -31;
+    ret = wc_Des3_SetKey(&dec, key3, iv3, DES_DECRYPTION);
+    if (ret != 0)
+        return -32;
+    ret = wc_Des3_CbcEncrypt(&enc, cipher, vector, sizeof(vector));
+    if (ret != 0)
+        return -33;
+    ret = wc_Des3_CbcDecrypt(&dec, plain, cipher, sizeof(cipher));
+    if (ret != 0)
+        return -34;
+
+    if (memcmp(plain, vector, sizeof(plain)))
+        return -35;
+
+    if (memcmp(cipher, verify3, sizeof(cipher)))
+        return -36;
+
+#ifdef HAVE_CAVIUM
+    wc_Des3_FreeCavium(&enc);
+    wc_Des3_FreeCavium(&dec);
+#endif
+    return 0;
+}
+#endif /* NO_DES */
+
+
+#ifndef NO_AES
+int aes_test(void)
+{
+    Aes enc;
+    Aes dec;
+
+    const byte msg[] = { /* "Now is the time for all " w/o trailing 0 */
+        0x6e,0x6f,0x77,0x20,0x69,0x73,0x20,0x74,
+        0x68,0x65,0x20,0x74,0x69,0x6d,0x65,0x20,
+        0x66,0x6f,0x72,0x20,0x61,0x6c,0x6c,0x20
+    };
+
+    const byte verify[] =
+    {
+        0x95,0x94,0x92,0x57,0x5f,0x42,0x81,0x53,
+        0x2c,0xcc,0x9d,0x46,0x77,0xa2,0x33,0xcb
+    };
+
+    byte key[] = "0123456789abcdef   ";  /* align */
+    byte iv[]  = "1234567890abcdef   ";  /* align */
+
+    byte cipher[AES_BLOCK_SIZE * 4];
+    byte plain [AES_BLOCK_SIZE * 4];
+    int  ret;
+
+#ifdef HAVE_CAVIUM
+        if (wc_AesInitCavium(&enc, CAVIUM_DEV_ID) != 0)
+            return -20003;
+        if (wc_AesInitCavium(&dec, CAVIUM_DEV_ID) != 0)
+            return -20004;
+#endif
+    ret = wc_AesSetKey(&enc, key, AES_BLOCK_SIZE, iv, AES_ENCRYPTION);
+    if (ret != 0)
+        return -1001;
+    ret = wc_AesSetKey(&dec, key, AES_BLOCK_SIZE, iv, AES_DECRYPTION);
+    if (ret != 0)
+        return -1002;
+
+    ret = wc_AesCbcEncrypt(&enc, cipher, msg,   AES_BLOCK_SIZE);
+    if (ret != 0)
+        return -1005;
+    ret = wc_AesCbcDecrypt(&dec, plain, cipher, AES_BLOCK_SIZE);
+    if (ret != 0)
+        return -1006;
+
+    if (memcmp(plain, msg, AES_BLOCK_SIZE))
+        return -60;
+
+    if (memcmp(cipher, verify, AES_BLOCK_SIZE))
+        return -61;
+
+#ifdef HAVE_CAVIUM
+        wc_AesFreeCavium(&enc);
+        wc_AesFreeCavium(&dec);
+#endif
+#ifdef WOLFSSL_AES_COUNTER
+    {
+        const byte ctrKey[] =
+        {
+            0x2b,0x7e,0x15,0x16,0x28,0xae,0xd2,0xa6,
+            0xab,0xf7,0x15,0x88,0x09,0xcf,0x4f,0x3c
+        };
+
+        const byte ctrIv[] =
+        {
+            0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,
+            0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfe,0xff
+        };
+
+
+        const byte ctrPlain[] =
+        {
+            0x6b,0xc1,0xbe,0xe2,0x2e,0x40,0x9f,0x96,
+            0xe9,0x3d,0x7e,0x11,0x73,0x93,0x17,0x2a,
+            0xae,0x2d,0x8a,0x57,0x1e,0x03,0xac,0x9c,
+            0x9e,0xb7,0x6f,0xac,0x45,0xaf,0x8e,0x51,
+            0x30,0xc8,0x1c,0x46,0xa3,0x5c,0xe4,0x11,
+            0xe5,0xfb,0xc1,0x19,0x1a,0x0a,0x52,0xef,
+            0xf6,0x9f,0x24,0x45,0xdf,0x4f,0x9b,0x17,
+            0xad,0x2b,0x41,0x7b,0xe6,0x6c,0x37,0x10
+        };
+
+        const byte ctrCipher[] =
+        {
+            0x87,0x4d,0x61,0x91,0xb6,0x20,0xe3,0x26,
+            0x1b,0xef,0x68,0x64,0x99,0x0d,0xb6,0xce,
+            0x98,0x06,0xf6,0x6b,0x79,0x70,0xfd,0xff,
+            0x86,0x17,0x18,0x7b,0xb9,0xff,0xfd,0xff,
+            0x5a,0xe4,0xdf,0x3e,0xdb,0xd5,0xd3,0x5e,
+            0x5b,0x4f,0x09,0x02,0x0d,0xb0,0x3e,0xab,
+            0x1e,0x03,0x1d,0xda,0x2f,0xbe,0x03,0xd1,
+            0x79,0x21,0x70,0xa0,0xf3,0x00,0x9c,0xee
+        };
+
+        const byte oddCipher[] =
+        {
+            0xb9,0xd7,0xcb,0x08,0xb0,0xe1,0x7b,0xa0,
+            0xc2
+        };
+
+        wc_AesSetKeyDirect(&enc, ctrKey, AES_BLOCK_SIZE, ctrIv, AES_ENCRYPTION);
+        /* Ctr only uses encrypt, even on key setup */
+        wc_AesSetKeyDirect(&dec, ctrKey, AES_BLOCK_SIZE, ctrIv, AES_ENCRYPTION);
+
+        wc_AesCtrEncrypt(&enc, cipher, ctrPlain, AES_BLOCK_SIZE*4);
+        wc_AesCtrEncrypt(&dec, plain, cipher, AES_BLOCK_SIZE*4);
+
+        if (memcmp(plain, ctrPlain, AES_BLOCK_SIZE*4))
+            return -66;
+
+        if (memcmp(cipher, ctrCipher, AES_BLOCK_SIZE*4))
+            return -67;
+
+        /* let's try with just 9 bytes, non block size test */
+        wc_AesSetKeyDirect(&enc, ctrKey, AES_BLOCK_SIZE, ctrIv, AES_ENCRYPTION);
+        /* Ctr only uses encrypt, even on key setup */
+        wc_AesSetKeyDirect(&dec, ctrKey, AES_BLOCK_SIZE, ctrIv, AES_ENCRYPTION);
+
+        wc_AesCtrEncrypt(&enc, cipher, ctrPlain, 9);
+        wc_AesCtrEncrypt(&dec, plain, cipher, 9);
+
+        if (memcmp(plain, ctrPlain, 9))
+            return -68;
+
+        if (memcmp(cipher, ctrCipher, 9))
+            return -69;
+
+        /* and an additional 9 bytes to reuse tmp left buffer */
+        wc_AesCtrEncrypt(&enc, cipher, ctrPlain, 9);
+        wc_AesCtrEncrypt(&dec, plain, cipher, 9);
+
+        if (memcmp(plain, ctrPlain, 9))
+            return -70;
+
+        if (memcmp(cipher, oddCipher, 9))
+            return -71;
+    }
+#endif /* WOLFSSL_AES_COUNTER */
+
+#if defined(WOLFSSL_AESNI) && defined(WOLFSSL_AES_DIRECT)
+    {
+        const byte niPlain[] =
+        {
+            0x6b,0xc1,0xbe,0xe2,0x2e,0x40,0x9f,0x96,
+            0xe9,0x3d,0x7e,0x11,0x73,0x93,0x17,0x2a
+        };
+
+        const byte niCipher[] =
+        {
+            0xf3,0xee,0xd1,0xbd,0xb5,0xd2,0xa0,0x3c,
+            0x06,0x4b,0x5a,0x7e,0x3d,0xb1,0x81,0xf8
+        };
+
+        const byte niKey[] =
+        {
+            0x60,0x3d,0xeb,0x10,0x15,0xca,0x71,0xbe,
+            0x2b,0x73,0xae,0xf0,0x85,0x7d,0x77,0x81,
+            0x1f,0x35,0x2c,0x07,0x3b,0x61,0x08,0xd7,
+            0x2d,0x98,0x10,0xa3,0x09,0x14,0xdf,0xf4
+        };
+
+        XMEMSET(cipher, 0, AES_BLOCK_SIZE);
+        ret = wc_AesSetKey(&enc, niKey, sizeof(niKey), cipher, AES_ENCRYPTION);
+        if (ret != 0)
+            return -1003;
+        wc_AesEncryptDirect(&enc, cipher, niPlain);
+        if (XMEMCMP(cipher, niCipher, AES_BLOCK_SIZE) != 0)
+            return -20006;
+
+        XMEMSET(plain, 0, AES_BLOCK_SIZE);
+        ret = wc_AesSetKey(&dec, niKey, sizeof(niKey), plain, AES_DECRYPTION);
+        if (ret != 0)
+            return -1004;
+        wc_AesDecryptDirect(&dec, plain, niCipher);
+        if (XMEMCMP(plain, niPlain, AES_BLOCK_SIZE) != 0)
+            return -20007;
+    }
+#endif /* WOLFSSL_AESNI && WOLFSSL_AES_DIRECT */
+
+    return 0;
+}
+
+#ifdef HAVE_AESGCM
+int aesgcm_test(void)
+{
+    Aes enc;
+
+    /*
+     * This is Test Case 16 from the document Galois/
+     * Counter Mode of Operation (GCM) by McGrew and
+     * Viega.
+     */
+    const byte k[] =
+    {
+        0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
+        0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
+        0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
+        0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08
+    };
+
+    const byte iv[] =
+    {
+        0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
+        0xde, 0xca, 0xf8, 0x88
+    };
+
+    const byte p[] =
+    {
+        0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
+        0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
+        0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
+        0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
+        0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
+        0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
+        0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
+        0xba, 0x63, 0x7b, 0x39
+    };
+
+    const byte a[] =
+    {
+        0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef,
+        0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef,
+        0xab, 0xad, 0xda, 0xd2
+    };
+
+    const byte c[] =
+    {
+        0x52, 0x2d, 0xc1, 0xf0, 0x99, 0x56, 0x7d, 0x07,
+        0xf4, 0x7f, 0x37, 0xa3, 0x2a, 0x84, 0x42, 0x7d,
+        0x64, 0x3a, 0x8c, 0xdc, 0xbf, 0xe5, 0xc0, 0xc9,
+        0x75, 0x98, 0xa2, 0xbd, 0x25, 0x55, 0xd1, 0xaa,
+        0x8c, 0xb0, 0x8e, 0x48, 0x59, 0x0d, 0xbb, 0x3d,
+        0xa7, 0xb0, 0x8b, 0x10, 0x56, 0x82, 0x88, 0x38,
+        0xc5, 0xf6, 0x1e, 0x63, 0x93, 0xba, 0x7a, 0x0a,
+        0xbc, 0xc9, 0xf6, 0x62
+    };
+
+    const byte t[] =
+    {
+        0x76, 0xfc, 0x6e, 0xce, 0x0f, 0x4e, 0x17, 0x68,
+        0xcd, 0xdf, 0x88, 0x53, 0xbb, 0x2d, 0x55, 0x1b
+    };
+
+    byte t2[sizeof(t)];
+    byte p2[sizeof(c)];
+    byte c2[sizeof(p)];
+
+    int result;
+
+    memset(t2, 0, sizeof(t2));
+    memset(c2, 0, sizeof(c2));
+    memset(p2, 0, sizeof(p2));
+
+    wc_AesGcmSetKey(&enc, k, sizeof(k));
+    /* AES-GCM encrypt and decrypt both use AES encrypt internally */
+    wc_AesGcmEncrypt(&enc, c2, p, sizeof(c2), iv, sizeof(iv),
+                                                 t2, sizeof(t2), a, sizeof(a));
+    if (memcmp(c, c2, sizeof(c2)))
+        return -68;
+    if (memcmp(t, t2, sizeof(t2)))
+        return -69;
+
+    result = wc_AesGcmDecrypt(&enc, p2, c2, sizeof(p2), iv, sizeof(iv),
+                                                 t2, sizeof(t2), a, sizeof(a));
+    if (result != 0)
+        return -70;
+    if (memcmp(p, p2, sizeof(p2)))
+        return -71;
+
+    return 0;
+}
+
+int gmac_test(void)
+{
+    Gmac gmac;
+
+    const byte k1[] =
+    {
+        0x89, 0xc9, 0x49, 0xe9, 0xc8, 0x04, 0xaf, 0x01,
+        0x4d, 0x56, 0x04, 0xb3, 0x94, 0x59, 0xf2, 0xc8
+    };
+    const byte iv1[] =
+    {
+        0xd1, 0xb1, 0x04, 0xc8, 0x15, 0xbf, 0x1e, 0x94,
+        0xe2, 0x8c, 0x8f, 0x16
+    };
+    const byte a1[] =
+    {
+       0x82, 0xad, 0xcd, 0x63, 0x8d, 0x3f, 0xa9, 0xd9,
+       0xf3, 0xe8, 0x41, 0x00, 0xd6, 0x1e, 0x07, 0x77
+    };
+    const byte t1[] =
+    {
+        0x88, 0xdb, 0x9d, 0x62, 0x17, 0x2e, 0xd0, 0x43,
+        0xaa, 0x10, 0xf1, 0x6d, 0x22, 0x7d, 0xc4, 0x1b
+    };
+
+    const byte k2[] =
+    {
+        0x40, 0xf7, 0xec, 0xb2, 0x52, 0x6d, 0xaa, 0xd4,
+        0x74, 0x25, 0x1d, 0xf4, 0x88, 0x9e, 0xf6, 0x5b
+    };
+    const byte iv2[] =
+    {
+        0xee, 0x9c, 0x6e, 0x06, 0x15, 0x45, 0x45, 0x03,
+        0x1a, 0x60, 0x24, 0xa7
+    };
+    const byte a2[] =
+    {
+        0x94, 0x81, 0x2c, 0x87, 0x07, 0x4e, 0x15, 0x18,
+        0x34, 0xb8, 0x35, 0xaf, 0x1c, 0xa5, 0x7e, 0x56
+    };
+    const byte t2[] =
+    {
+        0xc6, 0x81, 0x79, 0x8e, 0x3d, 0xda, 0xb0, 0x9f,
+        0x8d, 0x83, 0xb0, 0xbb, 0x14, 0xb6, 0x91
+    };
+
+    const byte k3[] =
+    {
+        0xb8, 0xe4, 0x9a, 0x5e, 0x37, 0xf9, 0x98, 0x2b,
+        0xb9, 0x6d, 0xd0, 0xc9, 0xb6, 0xab, 0x26, 0xac
+    };
+    const byte iv3[] =
+    {
+        0xe4, 0x4a, 0x42, 0x18, 0x8c, 0xae, 0x94, 0x92,
+        0x6a, 0x9c, 0x26, 0xb0
+    };
+    const byte a3[] =
+    {
+        0x9d, 0xb9, 0x61, 0x68, 0xa6, 0x76, 0x7a, 0x31,
+        0xf8, 0x29, 0xe4, 0x72, 0x61, 0x68, 0x3f, 0x8a
+    };
+    const byte t3[] =
+    {
+        0x23, 0xe2, 0x9f, 0x66, 0xe4, 0xc6, 0x52, 0x48
+    };
+
+    byte tag[16];
+
+    memset(tag, 0, sizeof(tag));
+    wc_GmacSetKey(&gmac, k1, sizeof(k1));
+    wc_GmacUpdate(&gmac, iv1, sizeof(iv1), a1, sizeof(a1), tag, sizeof(t1));
+    if (memcmp(t1, tag, sizeof(t1)) != 0)
+        return -126;
+
+    memset(tag, 0, sizeof(tag));
+    wc_GmacSetKey(&gmac, k2, sizeof(k2));
+    wc_GmacUpdate(&gmac, iv2, sizeof(iv2), a2, sizeof(a2), tag, sizeof(t2));
+    if (memcmp(t2, tag, sizeof(t2)) != 0)
+        return -127;
+
+    memset(tag, 0, sizeof(tag));
+    wc_GmacSetKey(&gmac, k3, sizeof(k3));
+    wc_GmacUpdate(&gmac, iv3, sizeof(iv3), a3, sizeof(a3), tag, sizeof(t3));
+    if (memcmp(t3, tag, sizeof(t3)) != 0)
+        return -128;
+
+    return 0;
+}
+#endif /* HAVE_AESGCM */
+
+#ifdef HAVE_AESCCM
+int aesccm_test(void)
+{
+    Aes enc;
+
+    /* key */
+    const byte k[] =
+    {
+        0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
+        0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf
+    };
+
+    /* nonce */
+    const byte iv[] =
+    {
+        0x00, 0x00, 0x00, 0x03, 0x02, 0x01, 0x00, 0xa0,
+        0xa1, 0xa2, 0xa3, 0xa4, 0xa5
+    };
+
+    /* plaintext */
+    const byte p[] =
+    {
+        0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+        0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+        0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e
+    };
+
+    const byte a[] =
+    {
+        0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07
+    };
+
+    const byte c[] =
+    {
+        0x58, 0x8c, 0x97, 0x9a, 0x61, 0xc6, 0x63, 0xd2,
+        0xf0, 0x66, 0xd0, 0xc2, 0xc0, 0xf9, 0x89, 0x80,
+        0x6d, 0x5f, 0x6b, 0x61, 0xda, 0xc3, 0x84
+    };
+
+    const byte t[] =
+    {
+        0x17, 0xe8, 0xd1, 0x2c, 0xfd, 0xf9, 0x26, 0xe0
+    };
+
+    byte t2[sizeof(t)];
+    byte p2[sizeof(p)];
+    byte c2[sizeof(c)];
+
+    int result;
+
+    memset(t2, 0, sizeof(t2));
+    memset(c2, 0, sizeof(c2));
+    memset(p2, 0, sizeof(p2));
+
+    wc_AesCcmSetKey(&enc, k, sizeof(k));
+    /* AES-CCM encrypt and decrypt both use AES encrypt internally */
+    wc_AesCcmEncrypt(&enc, c2, p, sizeof(c2), iv, sizeof(iv),
+                                                 t2, sizeof(t2), a, sizeof(a));
+    if (memcmp(c, c2, sizeof(c2)))
+        return -107;
+    if (memcmp(t, t2, sizeof(t2)))
+        return -108;
+
+    result = wc_AesCcmDecrypt(&enc, p2, c2, sizeof(p2), iv, sizeof(iv),
+                                                 t2, sizeof(t2), a, sizeof(a));
+    if (result != 0)
+        return -109;
+    if (memcmp(p, p2, sizeof(p2)))
+        return -110;
+
+    /* Test the authentication failure */
+    t2[0]++; /* Corrupt the authentication tag. */
+    result = wc_AesCcmDecrypt(&enc, p2, c, sizeof(p2), iv, sizeof(iv),
+                                                 t2, sizeof(t2), a, sizeof(a));
+    if (result == 0)
+        return -111;
+
+    /* Clear c2 to compare against p2. p2 should be set to zero in case of
+     * authentication fail. */
+    memset(c2, 0, sizeof(c2));
+    if (memcmp(p2, c2, sizeof(p2)))
+        return -112;
+
+    return 0;
+}
+#endif /* HAVE_AESCCM */
+
+
+#endif /* NO_AES */
+
+
+#ifdef HAVE_CAMELLIA
+
+enum {
+    CAM_ECB_ENC, CAM_ECB_DEC, CAM_CBC_ENC, CAM_CBC_DEC
+};
+
+typedef struct {
+    int type;
+    const byte* plaintext;
+    const byte* iv;
+    const byte* ciphertext;
+    const byte* key;
+    word32 keySz;
+    int errorCode;
+} test_vector_t;
+
+int camellia_test(void)
+{
+    /* Camellia ECB Test Plaintext */
+    static const byte pte[] =
+    {
+        0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
+        0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10
+    };
+
+    /* Camellia ECB Test Initialization Vector */
+    static const byte ive[] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+
+    /* Test 1: Camellia ECB 128-bit key */
+    static const byte k1[] =
+    {
+        0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
+        0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10
+    };
+    static const byte c1[] =
+    {
+        0x67, 0x67, 0x31, 0x38, 0x54, 0x96, 0x69, 0x73,
+        0x08, 0x57, 0x06, 0x56, 0x48, 0xea, 0xbe, 0x43
+    };
+
+    /* Test 2: Camellia ECB 192-bit key */
+    static const byte k2[] =
+    {
+        0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
+        0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10,
+        0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77
+    };
+    static const byte c2[] =
+    {
+        0xb4, 0x99, 0x34, 0x01, 0xb3, 0xe9, 0x96, 0xf8,
+        0x4e, 0xe5, 0xce, 0xe7, 0xd7, 0x9b, 0x09, 0xb9
+    };
+
+    /* Test 3: Camellia ECB 256-bit key */
+    static const byte k3[] =
+    {
+        0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
+        0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10,
+        0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
+        0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff
+    };
+    static const byte c3[] =
+    {
+        0x9a, 0xcc, 0x23, 0x7d, 0xff, 0x16, 0xd7, 0x6c,
+        0x20, 0xef, 0x7c, 0x91, 0x9e, 0x3a, 0x75, 0x09
+    };
+
+    /* Camellia CBC Test Plaintext */
+    static const byte ptc[] =
+    {
+        0x6B, 0xC1, 0xBE, 0xE2, 0x2E, 0x40, 0x9F, 0x96,
+        0xE9, 0x3D, 0x7E, 0x11, 0x73, 0x93, 0x17, 0x2A
+    };
+
+    /* Camellia CBC Test Initialization Vector */
+    static const byte ivc[] =
+    {
+        0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+        0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F
+    };
+
+    /* Test 4: Camellia-CBC 128-bit key */
+    static const byte k4[] =
+    {
+        0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6,
+        0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C
+    };
+    static const byte c4[] =
+    {
+        0x16, 0x07, 0xCF, 0x49, 0x4B, 0x36, 0xBB, 0xF0,
+        0x0D, 0xAE, 0xB0, 0xB5, 0x03, 0xC8, 0x31, 0xAB
+    };
+
+    /* Test 5: Camellia-CBC 192-bit key */
+    static const byte k5[] =
+    {
+        0x8E, 0x73, 0xB0, 0xF7, 0xDA, 0x0E, 0x64, 0x52,
+        0xC8, 0x10, 0xF3, 0x2B, 0x80, 0x90, 0x79, 0xE5,
+        0x62, 0xF8, 0xEA, 0xD2, 0x52, 0x2C, 0x6B, 0x7B
+    };
+    static const byte c5[] =
+    {
+        0x2A, 0x48, 0x30, 0xAB, 0x5A, 0xC4, 0xA1, 0xA2,
+        0x40, 0x59, 0x55, 0xFD, 0x21, 0x95, 0xCF, 0x93
+    };
+
+    /* Test 6: CBC 256-bit key */
+    static const byte k6[] =
+    {
+        0x60, 0x3D, 0xEB, 0x10, 0x15, 0xCA, 0x71, 0xBE,
+        0x2B, 0x73, 0xAE, 0xF0, 0x85, 0x7D, 0x77, 0x81,
+        0x1F, 0x35, 0x2C, 0x07, 0x3B, 0x61, 0x08, 0xD7,
+        0x2D, 0x98, 0x10, 0xA3, 0x09, 0x14, 0xDF, 0xF4
+    };
+    static const byte c6[] =
+    {
+        0xE6, 0xCF, 0xA3, 0x5F, 0xC0, 0x2B, 0x13, 0x4A,
+        0x4D, 0x2C, 0x0B, 0x67, 0x37, 0xAC, 0x3E, 0xDA
+    };
+
+    byte out[CAMELLIA_BLOCK_SIZE];
+    Camellia cam;
+    int i, testsSz;
+    const test_vector_t testVectors[] =
+    {
+        {CAM_ECB_ENC, pte, ive, c1, k1, sizeof(k1), -114},
+        {CAM_ECB_ENC, pte, ive, c2, k2, sizeof(k2), -115},
+        {CAM_ECB_ENC, pte, ive, c3, k3, sizeof(k3), -116},
+        {CAM_ECB_DEC, pte, ive, c1, k1, sizeof(k1), -117},
+        {CAM_ECB_DEC, pte, ive, c2, k2, sizeof(k2), -118},
+        {CAM_ECB_DEC, pte, ive, c3, k3, sizeof(k3), -119},
+        {CAM_CBC_ENC, ptc, ivc, c4, k4, sizeof(k4), -120},
+        {CAM_CBC_ENC, ptc, ivc, c5, k5, sizeof(k5), -121},
+        {CAM_CBC_ENC, ptc, ivc, c6, k6, sizeof(k6), -122},
+        {CAM_CBC_DEC, ptc, ivc, c4, k4, sizeof(k4), -123},
+        {CAM_CBC_DEC, ptc, ivc, c5, k5, sizeof(k5), -124},
+        {CAM_CBC_DEC, ptc, ivc, c6, k6, sizeof(k6), -125}
+    };
+
+    testsSz = sizeof(testVectors)/sizeof(test_vector_t);
+    for (i = 0; i < testsSz; i++) {
+        if (wc_CamelliaSetKey(&cam, testVectors[i].key, testVectors[i].keySz,
+                                                        testVectors[i].iv) != 0)
+            return testVectors[i].errorCode;
+
+        switch (testVectors[i].type) {
+            case CAM_ECB_ENC:
+                wc_CamelliaEncryptDirect(&cam, out, testVectors[i].plaintext);
+                if (memcmp(out, testVectors[i].ciphertext, CAMELLIA_BLOCK_SIZE))
+                    return testVectors[i].errorCode;
+                break;
+            case CAM_ECB_DEC:
+                wc_CamelliaDecryptDirect(&cam, out, testVectors[i].ciphertext);
+                if (memcmp(out, testVectors[i].plaintext, CAMELLIA_BLOCK_SIZE))
+                    return testVectors[i].errorCode;
+                break;
+            case CAM_CBC_ENC:
+                wc_CamelliaCbcEncrypt(&cam, out, testVectors[i].plaintext,
+                                                           CAMELLIA_BLOCK_SIZE);
+                if (memcmp(out, testVectors[i].ciphertext, CAMELLIA_BLOCK_SIZE))
+                    return testVectors[i].errorCode;
+                break;
+            case CAM_CBC_DEC:
+                wc_CamelliaCbcDecrypt(&cam, out, testVectors[i].ciphertext,
+                                                           CAMELLIA_BLOCK_SIZE);
+                if (memcmp(out, testVectors[i].plaintext, CAMELLIA_BLOCK_SIZE))
+                    return testVectors[i].errorCode;
+                break;
+            default:
+                break;
+        }
+    }
+
+    /* Setting the IV and checking it was actually set. */
+    wc_CamelliaSetIV(&cam, ivc);
+    if (XMEMCMP(cam.reg, ivc, CAMELLIA_BLOCK_SIZE))
+        return -1;
+
+    /* Setting the IV to NULL should be same as all zeros IV */
+    if (wc_CamelliaSetIV(&cam, NULL) != 0 ||
+                                    XMEMCMP(cam.reg, ive, CAMELLIA_BLOCK_SIZE))
+        return -1;
+
+    /* First parameter should never be null */
+    if (wc_CamelliaSetIV(NULL, NULL) == 0)
+        return -1;
+
+    /* First parameter should never be null, check it fails */
+    if (wc_CamelliaSetKey(NULL, k1, sizeof(k1), NULL) == 0)
+        return -1;
+
+    /* Key should have a size of 16, 24, or 32 */
+    if (wc_CamelliaSetKey(&cam, k1, 0, NULL) == 0)
+        return -1;
+
+    return 0;
+}
+#endif /* HAVE_CAMELLIA */
+
+
+#if defined(HAVE_HASHDRBG) || defined(NO_RC4)
+
+int random_test(void)
+{
+    const byte test1Entropy[] =
+    {
+        0xa6, 0x5a, 0xd0, 0xf3, 0x45, 0xdb, 0x4e, 0x0e, 0xff, 0xe8, 0x75, 0xc3,
+        0xa2, 0xe7, 0x1f, 0x42, 0xc7, 0x12, 0x9d, 0x62, 0x0f, 0xf5, 0xc1, 0x19,
+        0xa9, 0xef, 0x55, 0xf0, 0x51, 0x85, 0xe0, 0xfb, 0x85, 0x81, 0xf9, 0x31,
+        0x75, 0x17, 0x27, 0x6e, 0x06, 0xe9, 0x60, 0x7d, 0xdb, 0xcb, 0xcc, 0x2e
+    };
+    const byte test1Output[] =
+    {
+        0xd3, 0xe1, 0x60, 0xc3, 0x5b, 0x99, 0xf3, 0x40, 0xb2, 0x62, 0x82, 0x64,
+        0xd1, 0x75, 0x10, 0x60, 0xe0, 0x04, 0x5d, 0xa3, 0x83, 0xff, 0x57, 0xa5,
+        0x7d, 0x73, 0xa6, 0x73, 0xd2, 0xb8, 0xd8, 0x0d, 0xaa, 0xf6, 0xa6, 0xc3,
+        0x5a, 0x91, 0xbb, 0x45, 0x79, 0xd7, 0x3f, 0xd0, 0xc8, 0xfe, 0xd1, 0x11,
+        0xb0, 0x39, 0x13, 0x06, 0x82, 0x8a, 0xdf, 0xed, 0x52, 0x8f, 0x01, 0x81,
+        0x21, 0xb3, 0xfe, 0xbd, 0xc3, 0x43, 0xe7, 0x97, 0xb8, 0x7d, 0xbb, 0x63,
+        0xdb, 0x13, 0x33, 0xde, 0xd9, 0xd1, 0xec, 0xe1, 0x77, 0xcf, 0xa6, 0xb7,
+        0x1f, 0xe8, 0xab, 0x1d, 0xa4, 0x66, 0x24, 0xed, 0x64, 0x15, 0xe5, 0x1c,
+        0xcd, 0xe2, 0xc7, 0xca, 0x86, 0xe2, 0x83, 0x99, 0x0e, 0xea, 0xeb, 0x91,
+        0x12, 0x04, 0x15, 0x52, 0x8b, 0x22, 0x95, 0x91, 0x02, 0x81, 0xb0, 0x2d,
+        0xd4, 0x31, 0xf4, 0xc9, 0xf7, 0x04, 0x27, 0xdf
+    };
+    const byte test2EntropyA[] =
+    {
+        0x63, 0x36, 0x33, 0x77, 0xe4, 0x1e, 0x86, 0x46, 0x8d, 0xeb, 0x0a, 0xb4,
+        0xa8, 0xed, 0x68, 0x3f, 0x6a, 0x13, 0x4e, 0x47, 0xe0, 0x14, 0xc7, 0x00,
+        0x45, 0x4e, 0x81, 0xe9, 0x53, 0x58, 0xa5, 0x69, 0x80, 0x8a, 0xa3, 0x8f,
+        0x2a, 0x72, 0xa6, 0x23, 0x59, 0x91, 0x5a, 0x9f, 0x8a, 0x04, 0xca, 0x68
+    };
+    const byte test2EntropyB[] =
+    {
+        0xe6, 0x2b, 0x8a, 0x8e, 0xe8, 0xf1, 0x41, 0xb6, 0x98, 0x05, 0x66, 0xe3,
+        0xbf, 0xe3, 0xc0, 0x49, 0x03, 0xda, 0xd4, 0xac, 0x2c, 0xdf, 0x9f, 0x22,
+        0x80, 0x01, 0x0a, 0x67, 0x39, 0xbc, 0x83, 0xd3
+    };
+    const byte test2Output[] =
+    {
+        0x04, 0xee, 0xc6, 0x3b, 0xb2, 0x31, 0xdf, 0x2c, 0x63, 0x0a, 0x1a, 0xfb,
+        0xe7, 0x24, 0x94, 0x9d, 0x00, 0x5a, 0x58, 0x78, 0x51, 0xe1, 0xaa, 0x79,
+        0x5e, 0x47, 0x73, 0x47, 0xc8, 0xb0, 0x56, 0x62, 0x1c, 0x18, 0xbd, 0xdc,
+        0xdd, 0x8d, 0x99, 0xfc, 0x5f, 0xc2, 0xb9, 0x20, 0x53, 0xd8, 0xcf, 0xac,
+        0xfb, 0x0b, 0xb8, 0x83, 0x12, 0x05, 0xfa, 0xd1, 0xdd, 0xd6, 0xc0, 0x71,
+        0x31, 0x8a, 0x60, 0x18, 0xf0, 0x3b, 0x73, 0xf5, 0xed, 0xe4, 0xd4, 0xd0,
+        0x71, 0xf9, 0xde, 0x03, 0xfd, 0x7a, 0xea, 0x10, 0x5d, 0x92, 0x99, 0xb8,
+        0xaf, 0x99, 0xaa, 0x07, 0x5b, 0xdb, 0x4d, 0xb9, 0xaa, 0x28, 0xc1, 0x8d,
+        0x17, 0x4b, 0x56, 0xee, 0x2a, 0x01, 0x4d, 0x09, 0x88, 0x96, 0xff, 0x22,
+        0x82, 0xc9, 0x55, 0xa8, 0x19, 0x69, 0xe0, 0x69, 0xfa, 0x8c, 0xe0, 0x07,
+        0xa1, 0x80, 0x18, 0x3a, 0x07, 0xdf, 0xae, 0x17
+    };
+
+    byte output[SHA256_DIGEST_SIZE * 4];
+    int ret;
+
+    ret = wc_RNG_HealthTest(0, test1Entropy, sizeof(test1Entropy), NULL, 0,
+                            output, sizeof(output));
+    if (ret != 0)
+        return -39;
+
+    if (XMEMCMP(test1Output, output, sizeof(output)) != 0)
+        return -40;
+
+    ret = wc_RNG_HealthTest(1, test2EntropyA, sizeof(test2EntropyA),
+                            test2EntropyB, sizeof(test2EntropyB),
+                            output, sizeof(output));
+    if (ret != 0)
+        return -41;
+
+    if (XMEMCMP(test2Output, output, sizeof(output)) != 0)
+        return -42;
+
+    return 0;
+}
+
+#else /* HAVE_HASHDRBG || NO_RC4 */
+
+int random_test(void)
+{
+    RNG  rng;
+    byte block[32];
+    int ret;
+
+#ifdef HAVE_CAVIUM
+    ret = wc_InitRngCavium(&rng, CAVIUM_DEV_ID);
+    if (ret != 0) return -2007;
+#endif
+    ret = wc_InitRng(&rng);
+    if (ret != 0) return -39;
+
+    ret = wc_RNG_GenerateBlock(&rng, block, sizeof(block));
+    if (ret != 0) return -40;
+
+    wc_FreeRng(&rng);
+
+    return 0;
+}
+
+#endif /* HAVE_HASHDRBG || NO_RC4 */
+
+
+#ifdef HAVE_NTRU
+
+byte GetEntropy(ENTROPY_CMD cmd, byte* out);
+
+byte GetEntropy(ENTROPY_CMD cmd, byte* out)
+{
+    static RNG rng;
+
+    if (cmd == INIT)
+        return (wc_InitRng(&rng) == 0) ? 1 : 0;
+
+    if (out == NULL)
+        return 0;
+
+    if (cmd == GET_BYTE_OF_ENTROPY)
+        return (wc_RNG_GenerateBlock(&rng, out, 1) == 0) ? 1 : 0;
+
+    if (cmd == GET_NUM_BYTES_PER_BYTE_OF_ENTROPY) {
+        *out = 1;
+        return 1;
+    }
+
+    return 0;
+}
+
+#endif /* HAVE_NTRU */
+
+#ifndef NO_RSA
+
+#if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048)
+    #ifdef FREESCALE_MQX
+        static const char* clientKey  = "a:\\certs\\client-key.der";
+        static const char* clientCert = "a:\\certs\\client-cert.der";
+        #ifdef WOLFSSL_CERT_GEN
+            static const char* caKeyFile  = "a:\\certs\\ca-key.der";
+            static const char* caCertFile = "a:\\certs\\ca-cert.pem";
+            #ifdef HAVE_ECC
+                static const char* eccCaKeyFile  = "a:\\certs\\ecc-key.der";
+                static const char* eccCaCertFile = "a:\\certs\\server-ecc.pem";
+            #endif
+        #endif
+    #elif defined(WOLFSSL_MKD_SHELL)
+        static char* clientKey = "certs/client-key.der";
+        static char* clientCert = "certs/client-cert.der";
+        void set_clientKey(char *key) {  clientKey = key ; }
+        void set_clientCert(char *cert) {  clientCert = cert ; }
+        #ifdef WOLFSSL_CERT_GEN
+            static char* caKeyFile  = "certs/ca-key.der";
+            static char* caCertFile = "certs/ca-cert.pem";
+            void set_caKeyFile (char * key)  { caKeyFile   = key ; }
+            void set_caCertFile(char * cert) { caCertFile = cert ; }
+            #ifdef HAVE_ECC
+                static const char* eccCaKeyFile  = "certs/ecc-key.der";
+                static const char* eccCaCertFile = "certs/server-ecc.pem";
+                void set_eccCaKeyFile (char * key)  { eccCaKeyFile  = key ; }
+                void set_eccCaCertFile(char * cert) { eccCaCertFile = cert ; }
+            #endif
+        #endif
+    #else
+        static const char* clientKey  = "./certs/client-key.der";
+        static const char* clientCert = "./certs/client-cert.der";
+        #ifdef WOLFSSL_CERT_GEN
+            static const char* caKeyFile  = "./certs/ca-key.der";
+            static const char* caCertFile = "./certs/ca-cert.pem";
+            #ifdef HAVE_ECC
+                static const char* eccCaKeyFile  = "./certs/ecc-key.der";
+                static const char* eccCaCertFile = "./certs/server-ecc.pem";
+            #endif
+        #endif
+    #endif
+#endif
+
+
+int rsa_test(void)
+{
+    byte*   tmp;
+    size_t bytes;
+    RsaKey key;
+    RNG    rng;
+    word32 idx = 0;
+    int    ret;
+    byte   in[] = "Everyone gets Friday off.";
+    word32 inLen = (word32)strlen((char*)in);
+    byte   out[256];
+    byte   plain[256];
+#if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048)
+    FILE*  file, * file2;
+#endif
+#ifdef WOLFSSL_TEST_CERT
+    DecodedCert cert;
+#endif
+
+    tmp = (byte*)malloc(FOURK_BUF);
+    if (tmp == NULL)
+        return -40;
+
+#ifdef USE_CERT_BUFFERS_1024
+    XMEMCPY(tmp, client_key_der_1024, sizeof_client_key_der_1024);
+    bytes = sizeof_client_key_der_1024;
+#elif defined(USE_CERT_BUFFERS_2048)
+    XMEMCPY(tmp, client_key_der_2048, sizeof_client_key_der_2048);
+    bytes = sizeof_client_key_der_2048;
+#else
+    file = fopen(clientKey, "rb");
+
+    if (!file) {
+        err_sys("can't open ./certs/client-key.der, "
+                "Please run from wolfSSL home dir", -40);
+        free(tmp);
+        return -40;
+    }
+
+    bytes = fread(tmp, 1, FOURK_BUF, file);
+    fclose(file);
+#endif /* USE_CERT_BUFFERS */
+
+#ifdef HAVE_CAVIUM
+    wc_RsaInitCavium(&key, CAVIUM_DEV_ID);
+#endif
+    ret = wc_InitRsaKey(&key, 0);
+    if (ret != 0) {
+        free(tmp);
+        return -39;
+    }
+    ret = wc_RsaPrivateKeyDecode(tmp, &idx, &key, (word32)bytes);
+    if (ret != 0) {
+        free(tmp);
+        return -41;
+    }
+    ret = wc_InitRng(&rng);
+    if (ret != 0) {
+        free(tmp);
+        return -42;
+    }
+    ret = wc_RsaPublicEncrypt(in, inLen, out, sizeof(out), &key, &rng);
+    if (ret < 0) {
+        free(tmp);
+        return -43;
+    }
+    ret = wc_RsaPrivateDecrypt(out, ret, plain, sizeof(plain), &key);
+    if (ret < 0) {
+        free(tmp);
+        return -44;
+    }
+    if (memcmp(plain, in, inLen)) {
+        free(tmp);
+        return -45;
+    }
+    ret = wc_RsaSSL_Sign(in, inLen, out, sizeof(out), &key, &rng);
+    if (ret < 0) {
+        free(tmp);
+        return -46;
+    }
+    memset(plain, 0, sizeof(plain));
+    ret = wc_RsaSSL_Verify(out, ret, plain, sizeof(plain), &key);
+    if (ret < 0) {
+        free(tmp);
+        return -47;
+    }
+    if (memcmp(plain, in, ret)) {
+        free(tmp);
+        return -48;
+    }
+#if defined(WOLFSSL_MDK_ARM)
+    #define sizeof(s) strlen((char *)(s))
+#endif
+
+#ifdef USE_CERT_BUFFERS_1024
+    XMEMCPY(tmp, client_cert_der_1024, sizeof_client_cert_der_1024);
+    bytes = sizeof_client_cert_der_1024;
+#elif defined(USE_CERT_BUFFERS_2048)
+    XMEMCPY(tmp, client_cert_der_2048, sizeof_client_cert_der_2048);
+    bytes = sizeof_client_cert_der_2048;
+#else
+    file2 = fopen(clientCert, "rb");
+    if (!file2) {
+        free(tmp);
+        return -49;
+    }
+
+    bytes = fread(tmp, 1, FOURK_BUF, file2);
+    fclose(file2);
+#endif
+
+#ifdef sizeof
+		#undef sizeof
+#endif
+
+#ifdef WOLFSSL_TEST_CERT
+    InitDecodedCert(&cert, tmp, (word32)bytes, 0);
+
+    ret = ParseCert(&cert, CERT_TYPE, NO_VERIFY, 0);
+    if (ret != 0) return -491;
+
+    FreeDecodedCert(&cert);
+#else
+    (void)bytes;
+#endif
+
+
+#ifdef WOLFSSL_KEY_GEN
+    {
+        byte*  der;
+        byte*  pem;
+        int    derSz = 0;
+        int    pemSz = 0;
+        RsaKey derIn;
+        RsaKey genKey;
+        FILE*  keyFile;
+        FILE*  pemFile;
+
+        ret = wc_InitRsaKey(&genKey, 0);
+        if (ret != 0)
+            return -300;
+        ret = wc_MakeRsaKey(&genKey, 1024, 65537, &rng);
+        if (ret != 0)
+            return -301;
+
+        der = (byte*)malloc(FOURK_BUF);
+        if (der == NULL) {
+            wc_FreeRsaKey(&genKey);
+            return -307;
+        }
+        pem = (byte*)malloc(FOURK_BUF);
+        if (pem == NULL) {
+            free(der);
+            wc_FreeRsaKey(&genKey);
+            return -308;
+        }
+
+        derSz = wc_RsaKeyToDer(&genKey, der, FOURK_BUF);
+        if (derSz < 0) {
+            free(der);
+            free(pem);
+            return -302;
+        }
+
+#ifdef FREESCALE_MQX
+        keyFile = fopen("a:\\certs\\key.der", "wb");
+#else
+        keyFile = fopen("./key.der", "wb");
+#endif
+        if (!keyFile) {
+            free(der);
+            free(pem);
+            wc_FreeRsaKey(&genKey);
+            return -303;
+        }
+        ret = (int)fwrite(der, 1, derSz, keyFile);
+        fclose(keyFile);
+        if (ret != derSz) {
+            free(der);
+            free(pem);
+            wc_FreeRsaKey(&genKey);
+            return -313;
+        }
+
+        pemSz = wc_DerToPem(der, derSz, pem, FOURK_BUF, PRIVATEKEY_TYPE);
+        if (pemSz < 0) {
+            free(der);
+            free(pem);
+            wc_FreeRsaKey(&genKey);
+            return -304;
+        }
+
+#ifdef FREESCALE_MQX
+        pemFile = fopen("a:\\certs\\key.pem", "wb");
+#else
+        pemFile = fopen("./key.pem", "wb");
+#endif
+        if (!pemFile) {
+            free(der);
+            free(pem);
+            wc_FreeRsaKey(&genKey);
+            return -305;
+        }
+        ret = (int)fwrite(pem, 1, pemSz, pemFile);
+        fclose(pemFile);
+        if (ret != pemSz) {
+            free(der);
+            free(pem);
+            wc_FreeRsaKey(&genKey);
+            return -314;
+        }
+
+        ret = wc_InitRsaKey(&derIn, 0);
+        if (ret != 0) {
+            free(der);
+            free(pem);
+            wc_FreeRsaKey(&genKey);
+            return -3060;
+        }
+        idx = 0;
+        ret = wc_RsaPrivateKeyDecode(der, &idx, &derIn, derSz);
+        if (ret != 0) {
+            free(der);
+            free(pem);
+            wc_FreeRsaKey(&derIn);
+            wc_FreeRsaKey(&genKey);
+            return -306;
+        }
+
+        wc_FreeRsaKey(&derIn);
+        wc_FreeRsaKey(&genKey);
+        free(pem);
+        free(der);
+    }
+#endif /* WOLFSSL_KEY_GEN */
+
+
+#ifdef WOLFSSL_CERT_GEN
+    /* self signed */
+    {
+        Cert        myCert;
+        byte*       derCert;
+        byte*       pem;
+        FILE*       derFile;
+        FILE*       pemFile;
+        int         certSz;
+        int         pemSz;
+#ifdef WOLFSSL_TEST_CERT
+        DecodedCert decode;
+#endif
+
+        derCert = (byte*)malloc(FOURK_BUF);
+        if (derCert == NULL)
+            return -309;
+        pem = (byte*)malloc(FOURK_BUF);
+        if (pem == NULL) {
+            free(derCert);
+            return -310;
+        }
+
+        wc_InitCert(&myCert);
+
+        strncpy(myCert.subject.country, "US", CTC_NAME_SIZE);
+        strncpy(myCert.subject.state, "OR", CTC_NAME_SIZE);
+        strncpy(myCert.subject.locality, "Portland", CTC_NAME_SIZE);
+        strncpy(myCert.subject.org, "yaSSL", CTC_NAME_SIZE);
+        strncpy(myCert.subject.unit, "Development", CTC_NAME_SIZE);
+        strncpy(myCert.subject.commonName, "www.yassl.com", CTC_NAME_SIZE);
+        strncpy(myCert.subject.email, "info@yassl.com", CTC_NAME_SIZE);
+        myCert.isCA    = 1;
+        myCert.sigType = CTC_SHA256wRSA;
+
+        certSz = wc_MakeSelfCert(&myCert, derCert, FOURK_BUF, &key, &rng);
+        if (certSz < 0) {
+            free(derCert);
+            free(pem);
+            return -401;
+        }
+
+#ifdef WOLFSSL_TEST_CERT
+        InitDecodedCert(&decode, derCert, certSz, 0);
+        ret = ParseCert(&decode, CERT_TYPE, NO_VERIFY, 0);
+        if (ret != 0) {
+            free(derCert);
+            free(pem);
+            return -402;
+        }
+        FreeDecodedCert(&decode);
+#endif
+
+#ifdef FREESCALE_MQX
+        derFile = fopen("a:\\certs\\cert.der", "wb");
+#else
+        derFile = fopen("./cert.der", "wb");
+#endif
+        if (!derFile) {
+            free(derCert);
+            free(pem);
+            return -403;
+        }
+        ret = (int)fwrite(derCert, 1, certSz, derFile);
+        fclose(derFile);
+        if (ret != certSz) {
+            free(derCert);
+            free(pem);
+            return -414;
+        }
+
+        pemSz = wc_DerToPem(derCert, certSz, pem, FOURK_BUF, CERT_TYPE);
+        if (pemSz < 0) {
+            free(derCert);
+            free(pem);
+            return -404;
+        }
+
+#ifdef FREESCALE_MQX
+        pemFile = fopen("a:\\certs\\cert.pem", "wb");
+#else
+        pemFile = fopen("./cert.pem", "wb");
+#endif
+        if (!pemFile) {
+            free(derCert);
+            free(pem);
+            return -405;
+        }
+        ret = (int)fwrite(pem, 1, pemSz, pemFile);
+        fclose(pemFile);
+        if (ret != pemSz) {
+            free(derCert);
+            free(pem);
+            return -406;
+        }
+        free(pem);
+        free(derCert);
+    }
+    /* CA style */
+    {
+        RsaKey      caKey;
+        Cert        myCert;
+        byte*       derCert;
+        byte*       pem;
+        FILE*       derFile;
+        FILE*       pemFile;
+        int         certSz;
+        int         pemSz;
+        size_t      bytes3;
+        word32      idx3 = 0;
+        FILE*       file3 ;
+#ifdef WOLFSSL_TEST_CERT
+        DecodedCert decode;
+#endif
+
+        derCert = (byte*)malloc(FOURK_BUF);
+        if (derCert == NULL)
+            return -311;
+        pem = (byte*)malloc(FOURK_BUF);
+        if (pem == NULL) {
+            free(derCert);
+            return -312;
+        }
+
+        file3 = fopen(caKeyFile, "rb");
+
+        if (!file3) {
+            free(derCert);
+            free(pem);
+            return -412;
+        }
+
+        bytes3 = fread(tmp, 1, FOURK_BUF, file3);
+        fclose(file3);
+
+        ret = wc_InitRsaKey(&caKey, 0);
+        if (ret != 0) {
+            free(derCert);
+            free(pem);
+            return -411;
+        }
+        ret = wc_RsaPrivateKeyDecode(tmp, &idx3, &caKey, (word32)bytes3);
+        if (ret != 0) {
+            free(derCert);
+            free(pem);
+            wc_FreeRsaKey(&caKey);
+            return -413;
+        }
+
+        wc_InitCert(&myCert);
+
+        strncpy(myCert.subject.country, "US", CTC_NAME_SIZE);
+        strncpy(myCert.subject.state, "OR", CTC_NAME_SIZE);
+        strncpy(myCert.subject.locality, "Portland", CTC_NAME_SIZE);
+        strncpy(myCert.subject.org, "yaSSL", CTC_NAME_SIZE);
+        strncpy(myCert.subject.unit, "Development", CTC_NAME_SIZE);
+        strncpy(myCert.subject.commonName, "www.yassl.com", CTC_NAME_SIZE);
+        strncpy(myCert.subject.email, "info@yassl.com", CTC_NAME_SIZE);
+
+        ret = wc_SetIssuer(&myCert, caCertFile);
+        if (ret < 0) {
+            free(derCert);
+            free(pem);
+            wc_FreeRsaKey(&caKey);
+            return -405;
+        }
+
+        certSz = wc_MakeCert(&myCert, derCert, FOURK_BUF, &key, NULL, &rng);
+        if (certSz < 0) {
+            free(derCert);
+            free(pem);
+            wc_FreeRsaKey(&caKey);
+            return -407;
+        }
+
+        certSz = wc_SignCert(myCert.bodySz, myCert.sigType, derCert, FOURK_BUF,
+                          &caKey, NULL, &rng);
+        if (certSz < 0) {
+            free(derCert);
+            free(pem);
+            wc_FreeRsaKey(&caKey);
+            return -408;
+        }
+
+
+#ifdef WOLFSSL_TEST_CERT
+        InitDecodedCert(&decode, derCert, certSz, 0);
+        ret = ParseCert(&decode, CERT_TYPE, NO_VERIFY, 0);
+        if (ret != 0) {
+            free(derCert);
+            free(pem);
+            wc_FreeRsaKey(&caKey);
+            return -409;
+        }
+        FreeDecodedCert(&decode);
+#endif
+
+#ifdef FREESCALE_MQX
+        derFile = fopen("a:\\certs\\othercert.der", "wb");
+#else
+        derFile = fopen("./othercert.der", "wb");
+#endif
+        if (!derFile) {
+            free(derCert);
+            free(pem);
+            wc_FreeRsaKey(&caKey);
+            return -410;
+        }
+        ret = (int)fwrite(derCert, 1, certSz, derFile);
+        fclose(derFile);
+        if (ret != certSz) {
+            free(derCert);
+            free(pem);
+            wc_FreeRsaKey(&caKey);
+            return -416;
+        }
+
+        pemSz = wc_DerToPem(derCert, certSz, pem, FOURK_BUF, CERT_TYPE);
+        if (pemSz < 0) {
+            free(derCert);
+            free(pem);
+            wc_FreeRsaKey(&caKey);
+            return -411;
+        }
+
+#ifdef FREESCALE_MQX
+        pemFile = fopen("a:\\certs\\othercert.pem", "wb");
+#else
+        pemFile = fopen("./othercert.pem", "wb");
+#endif
+        if (!pemFile) {
+            free(derCert);
+            free(pem);
+            wc_FreeRsaKey(&caKey);
+            return -412;
+        }
+        ret = (int)fwrite(pem, 1, pemSz, pemFile);
+        if (ret != pemSz) {
+            free(derCert);
+            free(pem);
+            wc_FreeRsaKey(&caKey);
+            return -415;
+        }
+        fclose(pemFile);
+        free(pem);
+        free(derCert);
+        wc_FreeRsaKey(&caKey);
+    }
+#ifdef HAVE_ECC
+    /* ECC CA style */
+    {
+        ecc_key     caKey;
+        Cert        myCert;
+        byte*       derCert;
+        byte*       pem;
+        FILE*       derFile;
+        FILE*       pemFile;
+        int         certSz;
+        int         pemSz;
+        size_t      bytes3;
+        word32      idx3 = 0;
+        FILE*       file3;
+#ifdef WOLFSSL_TEST_CERT
+        DecodedCert decode;
+#endif
+
+        derCert = (byte*)malloc(FOURK_BUF);
+        if (derCert == NULL)
+            return -5311;
+        pem = (byte*)malloc(FOURK_BUF);
+        if (pem == NULL) {
+            free(derCert);
+            return -5312;
+        }
+
+        file3 = fopen(eccCaKeyFile, "rb");
+
+        if (!file3) {
+            free(derCert);
+            free(pem);
+            return -5412;
+        }
+
+        bytes3 = fread(tmp, 1, FOURK_BUF, file3);
+        fclose(file3);
+
+        wc_ecc_init(&caKey);
+        ret = wc_EccPrivateKeyDecode(tmp, &idx3, &caKey, (word32)bytes3);
+        if (ret != 0) {
+            free(derCert);
+            free(pem);
+            return -5413;
+        }
+
+        wc_InitCert(&myCert);
+        myCert.sigType = CTC_SHA256wECDSA;
+
+        strncpy(myCert.subject.country, "US", CTC_NAME_SIZE);
+        strncpy(myCert.subject.state, "OR", CTC_NAME_SIZE);
+        strncpy(myCert.subject.locality, "Portland", CTC_NAME_SIZE);
+        strncpy(myCert.subject.org, "wolfSSL", CTC_NAME_SIZE);
+        strncpy(myCert.subject.unit, "Development", CTC_NAME_SIZE);
+        strncpy(myCert.subject.commonName, "www.wolfssl.com", CTC_NAME_SIZE);
+        strncpy(myCert.subject.email, "info@wolfssl.com", CTC_NAME_SIZE);
+
+        ret = wc_SetIssuer(&myCert, eccCaCertFile);
+        if (ret < 0) {
+            free(pem);
+            free(derCert);
+            wc_ecc_free(&caKey);
+            return -5405;
+        }
+
+        certSz = wc_MakeCert(&myCert, derCert, FOURK_BUF, NULL, &caKey, &rng);
+        if (certSz < 0) {
+            free(pem);
+            free(derCert);
+            wc_ecc_free(&caKey);
+            return -5407;
+        }
+
+        certSz = wc_SignCert(myCert.bodySz, myCert.sigType, derCert, FOURK_BUF,
+                          NULL, &caKey, &rng);
+        if (certSz < 0) {
+            free(pem);
+            free(derCert);
+            wc_ecc_free(&caKey);
+            return -5408;
+        }
+
+#ifdef WOLFSSL_TEST_CERT
+        InitDecodedCert(&decode, derCert, certSz, 0);
+        ret = ParseCert(&decode, CERT_TYPE, NO_VERIFY, 0);
+        if (ret != 0) {
+            free(pem);
+            free(derCert);
+            wc_ecc_free(&caKey);
+            return -5409;
+        }
+        FreeDecodedCert(&decode);
+#endif
+
+#ifdef FREESCALE_MQX
+        derFile = fopen("a:\\certs\\certecc.der", "wb");
+#else
+        derFile = fopen("./certecc.der", "wb");
+#endif
+        if (!derFile) {
+            free(pem);
+            free(derCert);
+            wc_ecc_free(&caKey);
+            return -5410;
+        }
+        ret = (int)fwrite(derCert, 1, certSz, derFile);
+        fclose(derFile);
+        if (ret != certSz) {
+            free(pem);
+            free(derCert);
+            wc_ecc_free(&caKey);
+            return -5414;
+        }
+
+        pemSz = wc_DerToPem(derCert, certSz, pem, FOURK_BUF, CERT_TYPE);
+        if (pemSz < 0) {
+            free(pem);
+            free(derCert);
+            wc_ecc_free(&caKey);
+            return -5411;
+        }
+
+#ifdef FREESCALE_MQX
+        pemFile = fopen("a:\\certs\\certecc.pem", "wb");
+#else
+        pemFile = fopen("./certecc.pem", "wb");
+#endif
+        if (!pemFile) {
+            free(pem);
+            free(derCert);
+            wc_ecc_free(&caKey);
+            return -5412;
+        }
+        ret = (int)fwrite(pem, 1, pemSz, pemFile);
+        if (ret != pemSz) {
+            free(pem);
+            free(derCert);
+            wc_ecc_free(&caKey);
+            return -5415;
+        }
+        fclose(pemFile);
+        free(pem);
+        free(derCert);
+        wc_ecc_free(&caKey);
+    }
+#endif /* HAVE_ECC */
+#ifdef HAVE_NTRU
+    {
+        RsaKey      caKey;
+        Cert        myCert;
+        byte*       derCert;
+        byte*       pem;
+        FILE*       derFile;
+        FILE*       pemFile;
+        FILE*       caFile;
+        FILE*       ntruPrivFile;
+        int         certSz;
+        int         pemSz;
+        word32      idx3;
+#ifdef WOLFSSL_TEST_CERT
+        DecodedCert decode;
+#endif
+        derCert = (byte*)malloc(FOURK_BUF);
+        if (derCert == NULL)
+            return -311;
+        pem = (byte*)malloc(FOURK_BUF);
+        if (pem == NULL) {
+            free(derCert);
+            return -312;
+        }
+
+        byte   public_key[557];          /* sized for EES401EP2 */
+        word16 public_key_len;           /* no. of octets in public key */
+        byte   private_key[607];         /* sized for EES401EP2 */
+        word16 private_key_len;          /* no. of octets in private key */
+        DRBG_HANDLE drbg;
+        static uint8_t const pers_str[] = {
+                'C', 'y', 'a', 'S', 'S', 'L', ' ', 't', 'e', 's', 't'
+        };
+        word32 rc = ntru_crypto_drbg_instantiate(112, pers_str,
+                          sizeof(pers_str), GetEntropy, &drbg);
+        if (rc != DRBG_OK) {
+            free(derCert);
+            free(pem);
+            return -448;
+        }
+
+        rc = ntru_crypto_ntru_encrypt_keygen(drbg, NTRU_EES401EP2,
+                                             &public_key_len, NULL,
+                                             &private_key_len, NULL);
+        if (rc != NTRU_OK) {
+            free(derCert);
+            free(pem);
+            return -449;
+        }
+
+        rc = ntru_crypto_ntru_encrypt_keygen(drbg, NTRU_EES401EP2,
+                                             &public_key_len, public_key,
+                                             &private_key_len, private_key);
+        if (rc != NTRU_OK) {
+            free(derCert);
+            free(pem);
+            return -450;
+        }
+
+        rc = ntru_crypto_drbg_uninstantiate(drbg);
+
+        if (rc != NTRU_OK) {
+            free(derCert);
+            free(pem);
+            return -451;
+        }
+
+        caFile = fopen(caKeyFile, "rb");
+
+        if (!caFile) {
+            free(derCert);
+            free(pem);
+            return -452;
+        }
+
+        bytes = fread(tmp, 1, FOURK_BUF, caFile);
+        fclose(caFile);
+
+        ret = wc_InitRsaKey(&caKey, 0);
+        if (ret != 0) {
+            free(derCert);
+            free(pem);
+            return -453;
+        }
+        ret = wc_RsaPrivateKeyDecode(tmp, &idx3, &caKey, (word32)bytes);
+        if (ret != 0) {
+            free(derCert);
+            free(pem);
+            return -454;
+        }
+
+        wc_InitCert(&myCert);
+
+        strncpy(myCert.subject.country, "US", CTC_NAME_SIZE);
+        strncpy(myCert.subject.state, "OR", CTC_NAME_SIZE);
+        strncpy(myCert.subject.locality, "Portland", CTC_NAME_SIZE);
+        strncpy(myCert.subject.org, "yaSSL", CTC_NAME_SIZE);
+        strncpy(myCert.subject.unit, "Development", CTC_NAME_SIZE);
+        strncpy(myCert.subject.commonName, "www.yassl.com", CTC_NAME_SIZE);
+        strncpy(myCert.subject.email, "info@yassl.com", CTC_NAME_SIZE);
+
+        ret = wc_SetIssuer(&myCert, caCertFile);
+        if (ret < 0) {
+            free(derCert);
+            free(pem);
+            wc_FreeRsaKey(&caKey);
+            return -455;
+        }
+
+        certSz = wc_MakeNtruCert(&myCert, derCert, FOURK_BUF, public_key,
+                              public_key_len, &rng);
+        if (certSz < 0) {
+            free(derCert);
+            free(pem);
+            wc_FreeRsaKey(&caKey);
+            return -456;
+        }
+
+        certSz = wc_SignCert(myCert.bodySz, myCert.sigType, derCert, FOURK_BUF,
+                          &caKey, NULL, &rng);
+        wc_FreeRsaKey(&caKey);
+        if (certSz < 0) {
+            free(derCert);
+            free(pem);
+            return -457;
+        }
+
+
+#ifdef WOLFSSL_TEST_CERT
+        InitDecodedCert(&decode, derCert, certSz, 0);
+        ret = ParseCert(&decode, CERT_TYPE, NO_VERIFY, 0);
+        if (ret != 0) {
+            free(derCert);
+            free(pem);
+            return -458;
+        }
+        FreeDecodedCert(&decode);
+#endif
+        derFile = fopen("./ntru-cert.der", "wb");
+        if (!derFile) {
+            free(derCert);
+            free(pem);
+            return -459;
+        }
+        ret = (int)fwrite(derCert, 1, certSz, derFile);
+        fclose(derFile);
+        if (ret != certSz) {
+            free(derCert);
+            free(pem);
+            return -473;
+        }
+
+        pemSz = wc_DerToPem(derCert, certSz, pem, FOURK_BUF, CERT_TYPE);
+        if (pemSz < 0) {
+            free(derCert);
+            free(pem);
+            return -460;
+        }
+
+        pemFile = fopen("./ntru-cert.pem", "wb");
+        if (!pemFile) {
+            free(derCert);
+            free(pem);
+            return -461;
+        }
+        ret = (int)fwrite(pem, 1, pemSz, pemFile);
+        fclose(pemFile);
+        if (ret != pemSz) {
+            free(derCert);
+            free(pem);
+            return -474;
+        }
+
+        ntruPrivFile = fopen("./ntru-key.raw", "wb");
+        if (!ntruPrivFile) {
+            free(derCert);
+            free(pem);
+            return -462;
+        }
+        ret = (int)fwrite(private_key, 1, private_key_len, ntruPrivFile);
+        fclose(ntruPrivFile);
+        if (ret != private_key_len) {
+            free(pem);
+            free(derCert);
+            return -475;
+        }
+        free(pem);
+        free(derCert);
+    }
+#endif /* HAVE_NTRU */
+#ifdef WOLFSSL_CERT_REQ
+    {
+        Cert        req;
+        byte*       der;
+        byte*       pem;
+        int         derSz;
+        int         pemSz;
+        FILE*       reqFile;
+
+        der = (byte*)malloc(FOURK_BUF);
+        if (der == NULL)
+            return -463;
+        pem = (byte*)malloc(FOURK_BUF);
+        if (pem == NULL) {
+            free(der);
+            return -464;
+        }
+
+        wc_InitCert(&req);
+
+        req.version = 0;
+        req.isCA    = 1;
+        strncpy(req.challengePw, "yassl123", CTC_NAME_SIZE);
+        strncpy(req.subject.country, "US", CTC_NAME_SIZE);
+        strncpy(req.subject.state, "OR", CTC_NAME_SIZE);
+        strncpy(req.subject.locality, "Portland", CTC_NAME_SIZE);
+        strncpy(req.subject.org, "yaSSL", CTC_NAME_SIZE);
+        strncpy(req.subject.unit, "Development", CTC_NAME_SIZE);
+        strncpy(req.subject.commonName, "www.yassl.com", CTC_NAME_SIZE);
+        strncpy(req.subject.email, "info@yassl.com", CTC_NAME_SIZE);
+        req.sigType = CTC_SHA256wRSA;
+
+        derSz = wc_MakeCertReq(&req, der, FOURK_BUF, &key, NULL);
+        if (derSz < 0) {
+            free(pem);
+            free(der);
+            return -465;
+        }
+
+        derSz = wc_SignCert(req.bodySz, req.sigType, der, FOURK_BUF,
+                          &key, NULL, &rng);
+        if (derSz < 0) {
+            free(pem);
+            free(der);
+            return -466;
+        }
+
+        pemSz = wc_DerToPem(der, derSz, pem, FOURK_BUF, CERTREQ_TYPE);
+        if (pemSz < 0) {
+            free(pem);
+            free(der);
+            return -467;
+        }
+
+#ifdef FREESCALE_MQX
+        reqFile = fopen("a:\\certs\\certreq.der", "wb");
+#else
+        reqFile = fopen("./certreq.der", "wb");
+#endif
+        if (!reqFile) {
+            free(pem);
+            free(der);
+            return -468;
+        }
+
+        ret = (int)fwrite(der, 1, derSz, reqFile);
+        fclose(reqFile);
+        if (ret != derSz) {
+            free(pem);
+            free(der);
+            return -471;
+        }
+
+#ifdef FREESCALE_MQX
+        reqFile = fopen("a:\\certs\\certreq.pem", "wb");
+#else
+        reqFile = fopen("./certreq.pem", "wb");
+#endif
+        if (!reqFile) {
+            free(pem);
+            free(der);
+            return -469;
+        }
+        ret = (int)fwrite(pem, 1, pemSz, reqFile);
+        fclose(reqFile);
+        if (ret != pemSz) {
+            free(pem);
+            free(der);
+            return -470;
+        }
+
+        free(pem);
+        free(der);
+    }
+#endif /* WOLFSSL_CERT_REQ */
+#endif /* WOLFSSL_CERT_GEN */
+
+    wc_FreeRsaKey(&key);
+#ifdef HAVE_CAVIUM
+    wc_RsaFreeCavium(&key);
+#endif
+    free(tmp);
+    wc_FreeRng(&rng);
+
+    return 0;
+}
+
+#endif
+
+
+#ifndef NO_DH
+
+#if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048)
+    #ifdef FREESCALE_MQX
+        static const char* dhKey = "a:\\certs\\dh2048.der";
+    #elif defined(NO_ASN)
+        /* don't use file, no DER parsing */
+    #else
+        static const char* dhKey = "./certs/dh2048.der";
+    #endif
+#endif
+
+int dh_test(void)
+{
+    int    ret;
+    word32 bytes;
+    word32 idx = 0, privSz, pubSz, privSz2, pubSz2, agreeSz, agreeSz2;
+    byte   tmp[1024];
+    byte   priv[256];
+    byte   pub[256];
+    byte   priv2[256];
+    byte   pub2[256];
+    byte   agree[256];
+    byte   agree2[256];
+    DhKey  key;
+    DhKey  key2;
+    RNG    rng;
+
+#ifdef USE_CERT_BUFFERS_1024
+    XMEMCPY(tmp, dh_key_der_1024, sizeof_dh_key_der_1024);
+    bytes = sizeof_dh_key_der_1024;
+#elif defined(USE_CERT_BUFFERS_2048)
+    XMEMCPY(tmp, dh_key_der_2048, sizeof_dh_key_der_2048);
+    bytes = sizeof_dh_key_der_2048;
+#elif defined(NO_ASN)
+    /* don't use file, no DER parsing */
+#else
+    FILE*  file = fopen(dhKey, "rb");
+
+    if (!file)
+        return -50;
+
+    bytes = (word32) fread(tmp, 1, sizeof(tmp), file);
+    fclose(file);
+#endif /* USE_CERT_BUFFERS */
+
+    (void)idx;
+    (void)tmp;
+    (void)bytes;
+
+    wc_InitDhKey(&key);
+    wc_InitDhKey(&key2);
+#ifdef NO_ASN
+    ret = wc_DhSetKey(&key, dh_p, sizeof(dh_p), dh_g, sizeof(dh_g));
+    if (ret != 0)
+        return -51;
+
+    ret = wc_DhSetKey(&key2, dh_p, sizeof(dh_p), dh_g, sizeof(dh_g));
+    if (ret != 0)
+        return -51;
+#else
+    ret = wc_DhKeyDecode(tmp, &idx, &key, bytes);
+    if (ret != 0)
+        return -51;
+
+    idx = 0;
+    ret = wc_DhKeyDecode(tmp, &idx, &key2, bytes);
+    if (ret != 0)
+        return -52;
+#endif
+
+    ret = wc_InitRng(&rng);
+    if (ret != 0)
+        return -53;
+
+    ret =  wc_DhGenerateKeyPair(&key, &rng, priv, &privSz, pub, &pubSz);
+    ret += wc_DhGenerateKeyPair(&key2, &rng, priv2, &privSz2, pub2, &pubSz2);
+    if (ret != 0)
+        return -54;
+
+    ret =  wc_DhAgree(&key, agree, &agreeSz, priv, privSz, pub2, pubSz2);
+    ret += wc_DhAgree(&key2, agree2, &agreeSz2, priv2, privSz2, pub, pubSz);
+    if (ret != 0)
+        return -55;
+
+    if (memcmp(agree, agree2, agreeSz))
+        return -56;
+
+    wc_FreeDhKey(&key);
+    wc_FreeDhKey(&key2);
+    wc_FreeRng(&rng);
+
+    return 0;
+}
+
+#endif /* NO_DH */
+
+
+#ifndef NO_DSA
+
+#if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048)
+    #ifdef FREESCALE_MQX
+        static const char* dsaKey = "a:\\certs\\dsa2048.der";
+    #else
+        static const char* dsaKey = "./certs/dsa2048.der";
+    #endif
+#endif
+
+int dsa_test(void)
+{
+    int    ret, answer;
+    word32 bytes;
+    word32 idx = 0;
+    byte   tmp[1024];
+    DsaKey key;
+    RNG    rng;
+    Sha    sha;
+    byte   hash[SHA_DIGEST_SIZE];
+    byte   signature[40];
+
+
+#ifdef USE_CERT_BUFFERS_1024
+    XMEMCPY(tmp, dsa_key_der_1024, sizeof_dsa_key_der_1024);
+    bytes = sizeof_dsa_key_der_1024;
+#elif defined(USE_CERT_BUFFERS_2048)
+    XMEMCPY(tmp, dsa_key_der_2048, sizeof_dsa_key_der_2048);
+    bytes = sizeof_dsa_key_der_2048;
+#else
+    FILE*  file = fopen(dsaKey, "rb");
+
+    if (!file)
+        return -60;
+
+    bytes = (word32) fread(tmp, 1, sizeof(tmp), file);
+    fclose(file);
+#endif /* USE_CERT_BUFFERS */
+
+    ret = wc_InitSha(&sha);
+    if (ret != 0)
+        return -4002;
+    wc_ShaUpdate(&sha, tmp, bytes);
+    wc_ShaFinal(&sha, hash);
+
+    wc_InitDsaKey(&key);
+    ret = wc_DsaPrivateKeyDecode(tmp, &idx, &key, bytes);
+    if (ret != 0) return -61;
+
+    ret = wc_InitRng(&rng);
+    if (ret != 0) return -62;
+
+    ret = wc_DsaSign(hash, signature, &key, &rng);
+    if (ret != 0) return -63;
+
+    ret = wc_DsaVerify(hash, signature, &key, &answer);
+    if (ret != 0) return -64;
+    if (answer != 1) return -65;
+
+    wc_FreeDsaKey(&key);
+    wc_FreeRng(&rng);
+
+    return 0;
+}
+
+#endif /* NO_DSA */
+
+
+#ifdef OPENSSL_EXTRA
+
+int openssl_test(void)
+{
+    EVP_MD_CTX md_ctx;
+    testVector a, b, c, d, e, f;
+    byte       hash[SHA256_DIGEST_SIZE*2];  /* max size */
+
+    (void)a;
+    (void)b;
+    (void)c;
+    (void)e;
+    (void)f;
+
+#ifndef NO_MD5
+
+    a.input  = "1234567890123456789012345678901234567890123456789012345678"
+               "9012345678901234567890";
+    a.output = "\x57\xed\xf4\xa2\x2b\xe3\xc9\x55\xac\x49\xda\x2e\x21\x07\xb6"
+               "\x7a";
+    a.inLen  = strlen(a.input);
+    a.outLen = MD5_DIGEST_SIZE;
+
+    EVP_MD_CTX_init(&md_ctx);
+    EVP_DigestInit(&md_ctx, EVP_md5());
+
+    EVP_DigestUpdate(&md_ctx, a.input, (unsigned long)a.inLen);
+    EVP_DigestFinal(&md_ctx, hash, 0);
+
+    if (memcmp(hash, a.output, MD5_DIGEST_SIZE) != 0)
+        return -71;
+
+#endif /* NO_MD5 */
+
+#ifndef NO_SHA
+
+    b.input  = "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa"
+               "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa"
+               "aaaaaaaaaa";
+    b.output = "\xAD\x5B\x3F\xDB\xCB\x52\x67\x78\xC2\x83\x9D\x2F\x15\x1E\xA7"
+               "\x53\x99\x5E\x26\xA0";
+    b.inLen  = strlen(b.input);
+    b.outLen = SHA_DIGEST_SIZE;
+
+    EVP_MD_CTX_init(&md_ctx);
+    EVP_DigestInit(&md_ctx, EVP_sha1());
+
+    EVP_DigestUpdate(&md_ctx, b.input, (unsigned long)b.inLen);
+    EVP_DigestFinal(&md_ctx, hash, 0);
+
+    if (memcmp(hash, b.output, SHA_DIGEST_SIZE) != 0)
+        return -72;
+
+#endif /* NO_SHA */
+
+
+    d.input  = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq";
+    d.output = "\x24\x8D\x6A\x61\xD2\x06\x38\xB8\xE5\xC0\x26\x93\x0C\x3E\x60"
+               "\x39\xA3\x3C\xE4\x59\x64\xFF\x21\x67\xF6\xEC\xED\xD4\x19\xDB"
+               "\x06\xC1";
+    d.inLen  = strlen(d.input);
+    d.outLen = SHA256_DIGEST_SIZE;
+
+    EVP_MD_CTX_init(&md_ctx);
+    EVP_DigestInit(&md_ctx, EVP_sha256());
+
+    EVP_DigestUpdate(&md_ctx, d.input, (unsigned long)d.inLen);
+    EVP_DigestFinal(&md_ctx, hash, 0);
+
+    if (memcmp(hash, d.output, SHA256_DIGEST_SIZE) != 0)
+        return -78;
+
+#ifdef WOLFSSL_SHA384
+
+    e.input  = "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmnhi"
+               "jklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu";
+    e.output = "\x09\x33\x0c\x33\xf7\x11\x47\xe8\x3d\x19\x2f\xc7\x82\xcd\x1b"
+               "\x47\x53\x11\x1b\x17\x3b\x3b\x05\xd2\x2f\xa0\x80\x86\xe3\xb0"
+               "\xf7\x12\xfc\xc7\xc7\x1a\x55\x7e\x2d\xb9\x66\xc3\xe9\xfa\x91"
+               "\x74\x60\x39";
+    e.inLen  = strlen(e.input);
+    e.outLen = SHA384_DIGEST_SIZE;
+
+    EVP_MD_CTX_init(&md_ctx);
+    EVP_DigestInit(&md_ctx, EVP_sha384());
+
+    EVP_DigestUpdate(&md_ctx, e.input, (unsigned long)e.inLen);
+    EVP_DigestFinal(&md_ctx, hash, 0);
+
+    if (memcmp(hash, e.output, SHA384_DIGEST_SIZE) != 0)
+        return -79;
+
+#endif /* WOLFSSL_SHA384 */
+
+
+#ifdef WOLFSSL_SHA512
+
+    f.input  = "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmnhi"
+               "jklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu";
+    f.output = "\x8e\x95\x9b\x75\xda\xe3\x13\xda\x8c\xf4\xf7\x28\x14\xfc\x14"
+               "\x3f\x8f\x77\x79\xc6\xeb\x9f\x7f\xa1\x72\x99\xae\xad\xb6\x88"
+               "\x90\x18\x50\x1d\x28\x9e\x49\x00\xf7\xe4\x33\x1b\x99\xde\xc4"
+               "\xb5\x43\x3a\xc7\xd3\x29\xee\xb6\xdd\x26\x54\x5e\x96\xe5\x5b"
+               "\x87\x4b\xe9\x09";
+    f.inLen  = strlen(f.input);
+    f.outLen = SHA512_DIGEST_SIZE;
+
+    EVP_MD_CTX_init(&md_ctx);
+    EVP_DigestInit(&md_ctx, EVP_sha512());
+
+    EVP_DigestUpdate(&md_ctx, f.input, (unsigned long)f.inLen);
+    EVP_DigestFinal(&md_ctx, hash, 0);
+
+    if (memcmp(hash, f.output, SHA512_DIGEST_SIZE) != 0)
+        return -80;
+
+#endif /* WOLFSSL_SHA512 */
+
+
+#ifndef NO_MD5
+    if (RAND_bytes(hash, sizeof(hash)) != 1)
+        return -73;
+
+    c.input  = "what do ya want for nothing?";
+    c.output = "\x55\x78\xe8\x48\x4b\xcc\x93\x80\x93\xec\x53\xaf\x22\xd6\x14"
+               "\x76";
+    c.inLen  = strlen(c.input);
+    c.outLen = MD5_DIGEST_SIZE;
+
+    HMAC(EVP_md5(),
+                 "JefeJefeJefeJefe", 16, (byte*)c.input, (int)c.inLen, hash, 0);
+
+    if (memcmp(hash, c.output, MD5_DIGEST_SIZE) != 0)
+        return -74;
+
+#endif /* NO_MD5 */
+
+#ifndef NO_DES3
+    { /* des test */
+    const byte vector[] = { /* "now is the time for all " w/o trailing 0 */
+        0x6e,0x6f,0x77,0x20,0x69,0x73,0x20,0x74,
+        0x68,0x65,0x20,0x74,0x69,0x6d,0x65,0x20,
+        0x66,0x6f,0x72,0x20,0x61,0x6c,0x6c,0x20
+    };
+
+    byte plain[24];
+    byte cipher[24];
+
+    const_DES_cblock key =
+    {
+        0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef
+    };
+
+    DES_cblock iv =
+    {
+        0x12,0x34,0x56,0x78,0x90,0xab,0xcd,0xef
+    };
+
+    DES_key_schedule sched;
+
+    const byte verify[] =
+    {
+        0x8b,0x7c,0x52,0xb0,0x01,0x2b,0x6c,0xb8,
+        0x4f,0x0f,0xeb,0xf3,0xfb,0x5f,0x86,0x73,
+        0x15,0x85,0xb3,0x22,0x4b,0x86,0x2b,0x4b
+    };
+
+    DES_key_sched(&key, &sched);
+
+    DES_cbc_encrypt(vector, cipher, sizeof(vector), &sched, &iv, DES_ENCRYPT);
+    DES_cbc_encrypt(cipher, plain, sizeof(vector), &sched, &iv, DES_DECRYPT);
+
+    if (memcmp(plain, vector, sizeof(vector)) != 0)
+        return -75;
+
+    if (memcmp(cipher, verify, sizeof(verify)) != 0)
+        return -76;
+
+        /* test changing iv */
+    DES_ncbc_encrypt(vector, cipher, 8, &sched, &iv, DES_ENCRYPT);
+    DES_ncbc_encrypt(vector + 8, cipher + 8, 16, &sched, &iv, DES_ENCRYPT);
+
+    if (memcmp(cipher, verify, sizeof(verify)) != 0)
+        return -77;
+
+    }  /* end des test */
+
+#endif /* NO_DES3 */
+
+#ifndef NO_AES
+
+    {  /* evp_cipher test */
+        EVP_CIPHER_CTX ctx;
+
+
+        const byte msg[] = { /* "Now is the time for all " w/o trailing 0 */
+            0x6e,0x6f,0x77,0x20,0x69,0x73,0x20,0x74,
+            0x68,0x65,0x20,0x74,0x69,0x6d,0x65,0x20,
+            0x66,0x6f,0x72,0x20,0x61,0x6c,0x6c,0x20
+        };
+
+        const byte verify[] =
+        {
+            0x95,0x94,0x92,0x57,0x5f,0x42,0x81,0x53,
+            0x2c,0xcc,0x9d,0x46,0x77,0xa2,0x33,0xcb
+        };
+
+        byte key[] = "0123456789abcdef   ";  /* align */
+        byte iv[]  = "1234567890abcdef   ";  /* align */
+
+        byte cipher[AES_BLOCK_SIZE * 4];
+        byte plain [AES_BLOCK_SIZE * 4];
+
+        EVP_CIPHER_CTX_init(&ctx);
+        if (EVP_CipherInit(&ctx, EVP_aes_128_cbc(), key, iv, 1) == 0)
+            return -81;
+
+        if (EVP_Cipher(&ctx, cipher, (byte*)msg, 16) == 0)
+            return -82;
+
+        if (memcmp(cipher, verify, AES_BLOCK_SIZE))
+            return -83;
+
+        EVP_CIPHER_CTX_init(&ctx);
+        if (EVP_CipherInit(&ctx, EVP_aes_128_cbc(), key, iv, 0) == 0)
+            return -84;
+
+        if (EVP_Cipher(&ctx, plain, cipher, 16) == 0)
+            return -85;
+
+        if (memcmp(plain, msg, AES_BLOCK_SIZE))
+            return -86;
+
+
+    }  /* end evp_cipher test */
+
+#endif /* NO_AES */
+
+    return 0;
+}
+
+#endif /* OPENSSL_EXTRA */
+
+
+#ifndef NO_PWDBASED
+
+int pkcs12_test(void)
+{
+    const byte passwd[] = { 0x00, 0x73, 0x00, 0x6d, 0x00, 0x65, 0x00, 0x67,
+                            0x00, 0x00 };
+    const byte salt[] =   { 0x0a, 0x58, 0xCF, 0x64, 0x53, 0x0d, 0x82, 0x3f };
+
+    const byte passwd2[] = { 0x00, 0x71, 0x00, 0x75, 0x00, 0x65, 0x00, 0x65,
+                             0x00, 0x67, 0x00, 0x00 };
+    const byte salt2[] =   { 0x16, 0x82, 0xC0, 0xfC, 0x5b, 0x3f, 0x7e, 0xc5 };
+    byte  derived[64];
+
+    const byte verify[] = {
+        0x27, 0xE9, 0x0D, 0x7E, 0xD5, 0xA1, 0xC4, 0x11,
+        0xBA, 0x87, 0x8B, 0xC0, 0x90, 0xF5, 0xCE, 0xBE,
+        0x5E, 0x9D, 0x5F, 0xE3, 0xD6, 0x2B, 0x73, 0xAA
+    };
+
+    const byte verify2[] = {
+        0x90, 0x1B, 0x49, 0x70, 0xF0, 0x94, 0xF0, 0xF8,
+        0x45, 0xC0, 0xF3, 0xF3, 0x13, 0x59, 0x18, 0x6A,
+        0x35, 0xE3, 0x67, 0xFE, 0xD3, 0x21, 0xFD, 0x7C
+    };
+
+    int id         =  1;
+    int kLen       = 24;
+    int iterations =  1;
+    int ret = wc_PKCS12_PBKDF(derived, passwd, sizeof(passwd), salt, 8,
+                                                  iterations, kLen, SHA256, id);
+
+    if (ret < 0)
+        return -103;
+
+    if ( (ret = memcmp(derived, verify, kLen)) != 0)
+        return -104;
+
+    iterations = 1000;
+    ret = wc_PKCS12_PBKDF(derived, passwd2, sizeof(passwd2), salt2, 8,
+                                                  iterations, kLen, SHA256, id);
+    if (ret < 0)
+        return -105;
+
+    if ( (ret = memcmp(derived, verify2, 24)) != 0)
+        return -106;
+
+    return 0;
+}
+
+
+int pbkdf2_test(void)
+{
+    char passwd[] = "passwordpassword";
+    const byte salt[] = { 0x78, 0x57, 0x8E, 0x5a, 0x5d, 0x63, 0xcb, 0x06 };
+    int   iterations = 2048;
+    int   kLen = 24;
+    byte  derived[64];
+
+    const byte verify[] = {
+        0x43, 0x6d, 0xb5, 0xe8, 0xd0, 0xfb, 0x3f, 0x35, 0x42, 0x48, 0x39, 0xbc,
+        0x2d, 0xd4, 0xf9, 0x37, 0xd4, 0x95, 0x16, 0xa7, 0x2a, 0x9a, 0x21, 0xd1
+    };
+
+    int ret = wc_PBKDF2(derived, (byte*)passwd, (int)strlen(passwd), salt, 8,
+                                                      iterations, kLen, SHA256);
+    if (ret != 0)
+        return ret;
+
+    if (memcmp(derived, verify, sizeof(verify)) != 0)
+        return -102;
+
+    return 0;
+}
+
+
+#ifndef NO_SHA
+int pbkdf1_test(void)
+{
+    char passwd[] = "password";
+    const byte salt[] = { 0x78, 0x57, 0x8E, 0x5a, 0x5d, 0x63, 0xcb, 0x06 };
+    int   iterations = 1000;
+    int   kLen = 16;
+    byte  derived[16];
+
+    const byte verify[] = {
+        0xDC, 0x19, 0x84, 0x7E, 0x05, 0xC6, 0x4D, 0x2F, 0xAF, 0x10, 0xEB, 0xFB,
+        0x4A, 0x3D, 0x2A, 0x20
+    };
+
+    wc_PBKDF1(derived, (byte*)passwd, (int)strlen(passwd), salt, 8, iterations,
+           kLen, SHA);
+
+    if (memcmp(derived, verify, sizeof(verify)) != 0)
+        return -101;
+
+    return 0;
+}
+#endif
+
+
+int pwdbased_test(void)
+{
+   int ret = 0;
+#ifndef NO_SHA
+   ret += pbkdf1_test();
+#endif
+   ret += pbkdf2_test();
+
+   return ret + pkcs12_test();
+}
+
+#endif /* NO_PWDBASED */
+
+#if defined(HAVE_HKDF) && (!defined(NO_SHA) || !defined(NO_SHA256))
+
+int hkdf_test(void)
+{
+    int ret;
+    int L = 42;
+    byte okm1[42];
+    byte ikm1[22] = { 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b,
+                      0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b,
+                      0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b };
+    byte salt1[13] ={ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+                      0x08, 0x09, 0x0a, 0x0b, 0x0c };
+    byte info1[10] ={ 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
+                      0xf8, 0xf9 };
+    byte res1[42] = { 0x0a, 0xc1, 0xaf, 0x70, 0x02, 0xb3, 0xd7, 0x61,
+                      0xd1, 0xe5, 0x52, 0x98, 0xda, 0x9d, 0x05, 0x06,
+                      0xb9, 0xae, 0x52, 0x05, 0x72, 0x20, 0xa3, 0x06,
+                      0xe0, 0x7b, 0x6b, 0x87, 0xe8, 0xdf, 0x21, 0xd0,
+                      0xea, 0x00, 0x03, 0x3d, 0xe0, 0x39, 0x84, 0xd3,
+                      0x49, 0x18 };
+    byte res2[42] = { 0x08, 0x5a, 0x01, 0xea, 0x1b, 0x10, 0xf3, 0x69,
+                      0x33, 0x06, 0x8b, 0x56, 0xef, 0xa5, 0xad, 0x81,
+                      0xa4, 0xf1, 0x4b, 0x82, 0x2f, 0x5b, 0x09, 0x15,
+                      0x68, 0xa9, 0xcd, 0xd4, 0xf1, 0x55, 0xfd, 0xa2,
+                      0xc2, 0x2e, 0x42, 0x24, 0x78, 0xd3, 0x05, 0xf3,
+                      0xf8, 0x96 };
+    byte res3[42] = { 0x8d, 0xa4, 0xe7, 0x75, 0xa5, 0x63, 0xc1, 0x8f,
+                      0x71, 0x5f, 0x80, 0x2a, 0x06, 0x3c, 0x5a, 0x31,
+                      0xb8, 0xa1, 0x1f, 0x5c, 0x5e, 0xe1, 0x87, 0x9e,
+                      0xc3, 0x45, 0x4e, 0x5f, 0x3c, 0x73, 0x8d, 0x2d,
+                      0x9d, 0x20, 0x13, 0x95, 0xfa, 0xa4, 0xb6, 0x1a,
+                      0x96, 0xc8 };
+    byte res4[42] = { 0x3c, 0xb2, 0x5f, 0x25, 0xfa, 0xac, 0xd5, 0x7a,
+                      0x90, 0x43, 0x4f, 0x64, 0xd0, 0x36, 0x2f, 0x2a,
+                      0x2d, 0x2d, 0x0a, 0x90, 0xcf, 0x1a, 0x5a, 0x4c,
+                      0x5d, 0xb0, 0x2d, 0x56, 0xec, 0xc4, 0xc5, 0xbf,
+                      0x34, 0x00, 0x72, 0x08, 0xd5, 0xb8, 0x87, 0x18,
+                      0x58, 0x65 };
+
+    (void)res1;
+    (void)res2;
+    (void)res3;
+    (void)res4;
+    (void)salt1;
+    (void)info1;
+
+#ifndef NO_SHA
+    ret = wc_HKDF(SHA, ikm1, 22, NULL, 0, NULL, 0, okm1, L);
+    if (ret != 0)
+        return -2001;
+
+    if (memcmp(okm1, res1, L) != 0)
+        return -2002;
+
+#ifndef HAVE_FIPS
+    /* fips can't have key size under 14 bytes, salt is key too */
+    ret = wc_HKDF(SHA, ikm1, 11, salt1, 13, info1, 10, okm1, L);
+    if (ret != 0)
+        return -2003;
+
+    if (memcmp(okm1, res2, L) != 0)
+        return -2004;
+#endif /* HAVE_FIPS */
+#endif /* NO_SHA */
+
+#ifndef NO_SHA256
+    ret = wc_HKDF(SHA256, ikm1, 22, NULL, 0, NULL, 0, okm1, L);
+    if (ret != 0)
+        return -2005;
+
+    if (memcmp(okm1, res3, L) != 0)
+        return -2006;
+
+#ifndef HAVE_FIPS
+    /* fips can't have key size under 14 bytes, salt is key too */
+    ret = wc_HKDF(SHA256, ikm1, 22, salt1, 13, info1, 10, okm1, L);
+    if (ret != 0)
+        return -2007;
+
+    if (memcmp(okm1, res4, L) != 0)
+        return -2007;
+#endif /* HAVE_FIPS */
+#endif /* NO_SHA256 */
+
+    return 0;
+}
+
+#endif /* HAVE_HKDF */
+
+
+#ifdef HAVE_ECC
+
+typedef struct rawEccVector {
+    const char* msg;
+    const char* Qx;
+    const char* Qy;
+    const char* d;
+    const char* R;
+    const char* S;
+    const char* curveName;
+    size_t msgLen;
+} rawEccVector;
+
+int ecc_test(void)
+{
+    RNG     rng;
+    byte    sharedA[1024];
+    byte    sharedB[1024];
+    byte    sig[1024];
+    byte    digest[20];
+    byte    exportBuf[1024];
+    word32  x, y;
+    int     i, verify, ret;
+    ecc_key userA, userB, pubKey;
+
+    ret = wc_InitRng(&rng);
+    if (ret != 0)
+        return -1001;
+
+    wc_ecc_init(&userA);
+    wc_ecc_init(&userB);
+    wc_ecc_init(&pubKey);
+
+    ret = wc_ecc_make_key(&rng, 32, &userA);
+
+    if (ret != 0)
+        return -1014;
+
+    ret = wc_ecc_check_key(&userA);
+    if (ret != 0)
+        return -1024;
+
+    ret = wc_ecc_make_key(&rng, 32, &userB);
+
+    if (ret != 0)
+        return -1002;
+
+    x = sizeof(sharedA);
+    ret = wc_ecc_shared_secret(&userA, &userB, sharedA, &x);
+
+    if (ret != 0)
+        return -1015;
+
+    y = sizeof(sharedB);
+    ret = wc_ecc_shared_secret(&userB, &userA, sharedB, &y);
+
+    if (ret != 0)
+        return -1003;
+
+    if (y != x)
+        return -1004;
+
+    if (memcmp(sharedA, sharedB, x))
+        return -1005;
+
+    x = sizeof(exportBuf);
+    ret = wc_ecc_export_x963(&userA, exportBuf, &x);
+    if (ret != 0)
+        return -1006;
+
+    ret = wc_ecc_import_x963(exportBuf, x, &pubKey);
+
+    if (ret != 0)
+        return -1007;
+
+    y = sizeof(sharedB);
+    ret = wc_ecc_shared_secret(&userB, &pubKey, sharedB, &y);
+
+    if (ret != 0)
+        return -1008;
+
+    if (memcmp(sharedA, sharedB, y))
+        return -1009;
+
+#ifdef HAVE_COMP_KEY
+    /* try compressed export / import too */
+    x = sizeof(exportBuf);
+    ret = wc_ecc_export_x963_ex(&userA, exportBuf, &x, 1);
+    if (ret != 0)
+        return -1010;
+
+    wc_ecc_free(&pubKey);
+    wc_ecc_init(&pubKey);
+    ret = wc_ecc_import_x963(exportBuf, x, &pubKey);
+
+    if (ret != 0)
+        return -1011;
+#endif
+
+    y = sizeof(sharedB);
+    ret = wc_ecc_shared_secret(&userB, &pubKey, sharedB, &y);
+
+    if (ret != 0)
+        return -1012;
+
+    if (memcmp(sharedA, sharedB, y))
+        return -1013;
+
+    /* test DSA sign hash */
+    for (i = 0; i < (int)sizeof(digest); i++)
+        digest[i] = (byte)i;
+
+    x = sizeof(sig);
+    ret = wc_ecc_sign_hash(digest, sizeof(digest), sig, &x, &rng, &userA);
+
+    if (ret != 0)
+        return -1014;
+
+    verify = 0;
+    ret = wc_ecc_verify_hash(sig, x, digest, sizeof(digest), &verify, &userA);
+
+    if (ret != 0)
+        return -1015;
+
+    if (verify != 1)
+        return -1016;
+
+    x = sizeof(exportBuf);
+    ret = wc_ecc_export_private_only(&userA, exportBuf, &x);
+    if (ret != 0)
+        return -1017;
+
+#if !defined(NO_SHA) && \
+    ((defined(HAVE_ECC192) && defined(HAVE_ECC224)) || defined(HAVE_ALL_CURVES))
+    {
+        /* test raw ECC key import */
+        Sha sha;
+        byte hash[SHA_DIGEST_SIZE];
+        rawEccVector a, b;
+        rawEccVector test_ecc[2];
+        int times = sizeof(test_ecc) / sizeof(rawEccVector);
+
+        /* first [P-192,SHA-1] vector from FIPS 186-3 NIST vectors */
+        a.msg = "\xeb\xf7\x48\xd7\x48\xeb\xbc\xa7\xd2\x9f\xb4\x73\x69\x8a"
+                "\x6e\x6b\x4f\xb1\x0c\x86\x5d\x4a\xf0\x24\xcc\x39\xae\x3d"
+                "\xf3\x46\x4b\xa4\xf1\xd6\xd4\x0f\x32\xbf\x96\x18\xa9\x1b"
+                "\xb5\x98\x6f\xa1\xa2\xaf\x04\x8a\x0e\x14\xdc\x51\xe5\x26"
+                "\x7e\xb0\x5e\x12\x7d\x68\x9d\x0a\xc6\xf1\xa7\xf1\x56\xce"
+                "\x06\x63\x16\xb9\x71\xcc\x7a\x11\xd0\xfd\x7a\x20\x93\xe2"
+                "\x7c\xf2\xd0\x87\x27\xa4\xe6\x74\x8c\xc3\x2f\xd5\x9c\x78"
+                "\x10\xc5\xb9\x01\x9d\xf2\x1c\xdc\xc0\xbc\xa4\x32\xc0\xa3"
+                "\xee\xd0\x78\x53\x87\x50\x88\x77\x11\x43\x59\xce\xe4\xa0"
+                "\x71\xcf";
+        a.msgLen = 128;
+        a.Qx = "07008ea40b08dbe76432096e80a2494c94982d2d5bcf98e6";
+        a.Qy = "76fab681d00b414ea636ba215de26d98c41bd7f2e4d65477";
+        a.d  = "e14f37b3d1374ff8b03f41b9b3fdd2f0ebccf275d660d7f3";
+        a.R  = "6994d962bdd0d793ffddf855ec5bf2f91a9698b46258a63e";
+        a.S  = "02ba6465a234903744ab02bc8521405b73cf5fc00e1a9f41";
+        a.curveName = "ECC-192";
+
+        /* first [P-224,SHA-1] vector from FIPS 186-3 NIST vectors */
+        b.msg = "\x36\xc8\xb2\x29\x86\x48\x7f\x67\x7c\x18\xd0\x97\x2a\x9e"
+                "\x20\x47\xb3\xaf\xa5\x9e\xc1\x62\x76\x4e\xc3\x0b\x5b\x69"
+                "\xe0\x63\x0f\x99\x0d\x4e\x05\xc2\x73\xb0\xe5\xa9\xd4\x28"
+                "\x27\xb6\x95\xfc\x2d\x64\xd9\x13\x8b\x1c\xf4\xc1\x21\x55"
+                "\x89\x4c\x42\x13\x21\xa7\xbb\x97\x0b\xdc\xe0\xfb\xf0\xd2"
+                "\xae\x85\x61\xaa\xd8\x71\x7f\x2e\x46\xdf\xe3\xff\x8d\xea"
+                "\xb4\xd7\x93\x23\x56\x03\x2c\x15\x13\x0d\x59\x9e\x26\xc1"
+                "\x0f\x2f\xec\x96\x30\x31\xac\x69\x38\xa1\x8d\x66\x45\x38"
+                "\xb9\x4d\xac\x55\x34\xef\x7b\x59\x94\x24\xd6\x9b\xe1\xf7"
+                "\x1c\x20";
+        b.msgLen = 128;
+        b.Qx = "8a4dca35136c4b70e588e23554637ae251077d1365a6ba5db9585de7";
+        b.Qy = "ad3dee06de0be8279d4af435d7245f14f3b4f82eb578e519ee0057b1";
+        b.d  = "97c4b796e1639dd1035b708fc00dc7ba1682cec44a1002a1a820619f";
+        b.R  = "147b33758321e722a0360a4719738af848449e2c1d08defebc1671a7";
+        b.S  = "24fc7ed7f1352ca3872aa0916191289e2e04d454935d50fe6af3ad5b";
+        b.curveName = "ECC-224";
+
+        test_ecc[0] = a;
+        test_ecc[1] = b;
+
+        for (i = 0; i < times; i++) {
+
+            wc_ecc_free(&userA);
+            wc_ecc_init(&userA);
+
+            memset(sig, 0, sizeof(sig));
+            x = sizeof(sig);
+
+            /* calculate SHA-1 hash of message */
+            ret = wc_InitSha(&sha);
+            if (ret != 0)
+                return -1015 - i;
+
+            wc_ShaUpdate(&sha, (byte*)test_ecc[i].msg, (word32)test_ecc[i].msgLen);
+            wc_ShaFinal(&sha, hash);
+
+            ret = wc_ecc_import_raw(&userA, test_ecc[i].Qx, test_ecc[i].Qy,
+                                 test_ecc[i].d, test_ecc[i].curveName);
+            if (ret != 0)
+                return -1017 - i;
+
+            ret = wc_ecc_rs_to_sig(test_ecc[i].R, test_ecc[i].S, sig, &x);
+            if (ret != 0)
+                return -1019 - i;
+
+            ret = wc_ecc_verify_hash(sig, x, hash, sizeof(hash), &verify, &userA);
+            if (ret != 0)
+                return -1021 - i;
+
+            if (verify != 1)
+                return -1023 - i;
+        }
+    }
+#endif /* defined(HAVE_ECC192) && defined(HAVE_ECC256) */
+
+
+#ifdef WOLFSSL_KEY_GEN
+    {
+        int   derSz, pemSz;
+        byte  der[FOURK_BUF];
+        byte  pem[FOURK_BUF];
+        FILE* keyFile;
+        FILE* pemFile;
+
+        derSz = wc_EccKeyToDer(&userB, der, FOURK_BUF);
+        if (derSz < 0) {
+            return -1024;
+        }
+
+        keyFile = fopen("./ecc-key.der", "wb");
+        if (!keyFile) {
+            return -1025;
+        }
+        ret = (int)fwrite(der, 1, derSz, keyFile);
+        fclose(keyFile);
+        if (ret != derSz) {
+            return -1026;
+        }
+
+        pemSz = wc_DerToPem(der, derSz, pem, FOURK_BUF, ECC_PRIVATEKEY_TYPE);
+        if (pemSz < 0) {
+            return -1027;
+        }
+
+        pemFile = fopen("./ecc-key.pem", "wb");
+        if (!pemFile) {
+            return -1028;
+        }
+        ret = (int)fwrite(pem, 1, pemSz, pemFile);
+        fclose(pemFile);
+        if (ret != pemSz) {
+            return -1029;
+        }
+    }
+#endif /* WOLFSSL_KEY_GEN */
+
+    wc_ecc_free(&pubKey);
+    wc_ecc_free(&userB);
+    wc_ecc_free(&userA);
+    wc_FreeRng(&rng);
+
+    return 0;
+}
+
+#ifdef HAVE_ECC_ENCRYPT
+
+int ecc_encrypt_test(void)
+{
+    RNG     rng;
+    int     ret;
+    ecc_key userA, userB;
+    byte    msg[48];
+    byte    plain[48];
+    byte    out[80];
+    word32  outSz   = sizeof(out);
+    word32  plainSz = sizeof(plain);
+    int     i;
+
+    ret = wc_InitRng(&rng);
+    if (ret != 0)
+        return -3001;
+
+    wc_ecc_init(&userA);
+    wc_ecc_init(&userB);
+
+    ret  = wc_ecc_make_key(&rng, 32, &userA);
+    ret += wc_ecc_make_key(&rng, 32, &userB);
+
+    if (ret != 0)
+        return -3002;
+
+    for (i = 0; i < 48; i++)
+        msg[i] = i;
+
+    /* encrypt msg to B */
+    ret = wc_ecc_encrypt(&userA, &userB, msg, sizeof(msg), out, &outSz, NULL);
+    if (ret != 0)
+        return -3003;
+
+    /* decrypt msg from A */
+    ret = wc_ecc_decrypt(&userB, &userA, out, outSz, plain, &plainSz, NULL);
+    if (ret != 0)
+        return -3004;
+
+    if (memcmp(plain, msg, sizeof(msg)) != 0)
+        return -3005;
+
+
+    {  /* let's verify message exchange works, A is client, B is server */
+        ecEncCtx* cliCtx = wc_ecc_ctx_new(REQ_RESP_CLIENT, &rng);
+        ecEncCtx* srvCtx = wc_ecc_ctx_new(REQ_RESP_SERVER, &rng);
+
+        byte cliSalt[EXCHANGE_SALT_SZ];
+        byte srvSalt[EXCHANGE_SALT_SZ];
+        const byte* tmpSalt;
+
+        if (cliCtx == NULL || srvCtx == NULL)
+            return -3006;
+
+        /* get salt to send to peer */
+        tmpSalt = wc_ecc_ctx_get_own_salt(cliCtx);
+        if (tmpSalt == NULL)
+            return -3007;
+        memcpy(cliSalt, tmpSalt, EXCHANGE_SALT_SZ);
+
+        tmpSalt = wc_ecc_ctx_get_own_salt(srvCtx);
+        if (tmpSalt == NULL)
+            return -3007;
+        memcpy(srvSalt, tmpSalt, EXCHANGE_SALT_SZ);
+
+        /* in actual use, we'd get the peer's salt over the transport */
+        ret  = wc_ecc_ctx_set_peer_salt(cliCtx, srvSalt);
+        ret += wc_ecc_ctx_set_peer_salt(srvCtx, cliSalt);
+
+        ret += wc_ecc_ctx_set_info(cliCtx, (byte*)"wolfSSL MSGE", 11);
+        ret += wc_ecc_ctx_set_info(srvCtx, (byte*)"wolfSSL MSGE", 11);
+
+        if (ret != 0)
+            return -3008;
+
+        /* get encrypted msg (request) to send to B */
+        outSz  = sizeof(out);
+        ret = wc_ecc_encrypt(&userA, &userB, msg, sizeof(msg), out, &outSz,cliCtx);
+        if (ret != 0)
+            return -3009;
+
+        /* B decrypts msg (request) from A */
+        plainSz = sizeof(plain);
+        ret = wc_ecc_decrypt(&userB, &userA, out, outSz, plain, &plainSz, srvCtx);
+        if (ret != 0)
+            return -3010;
+
+        if (memcmp(plain, msg, sizeof(msg)) != 0)
+            return -3011;
+
+        {
+            /* msg2 (response) from B to A */
+            byte    msg2[48];
+            byte    plain2[48];
+            byte    out2[80];
+            word32  outSz2   = sizeof(out2);
+            word32  plainSz2 = sizeof(plain2);
+
+            for (i = 0; i < 48; i++)
+                msg2[i] = i+48;
+
+            /* get encrypted msg (response) to send to B */
+            ret = wc_ecc_encrypt(&userB, &userA, msg2, sizeof(msg2), out2,
+                              &outSz2, srvCtx);
+            if (ret != 0)
+                return -3012;
+
+            /* A decrypts msg (response) from B */
+            ret = wc_ecc_decrypt(&userA, &userB, out2, outSz2, plain2, &plainSz2,
+                             cliCtx);
+            if (ret != 0)
+                return -3013;
+
+            if (memcmp(plain2, msg2, sizeof(msg2)) != 0)
+                return -3014;
+        }
+
+        /* cleanup */
+        wc_ecc_ctx_free(srvCtx);
+        wc_ecc_ctx_free(cliCtx);
+    }
+
+    /* cleanup */
+    wc_ecc_free(&userB);
+    wc_ecc_free(&userA);
+    wc_FreeRng(&rng);
+
+    return 0;
+}
+
+#endif /* HAVE_ECC_ENCRYPT */
+#endif /* HAVE_ECC */
+
+
+#ifdef HAVE_CURVE25519
+
+int curve25519_test(void)
+{
+    RNG     rng;
+    byte    sharedA[32];
+    byte    sharedB[32];
+    byte    exportBuf[32];
+    word32  x, y;
+    curve25519_key userA, userB, pubKey;
+
+    /* test vectors from
+       https://tools.ietf.org/html/draft-josefsson-tls-curve25519-03
+     */
+
+    /* secret key for party a */
+    byte sa[] = {
+        0x5A,0xC9,0x9F,0x33,0x63,0x2E,0x5A,0x76,
+        0x8D,0xE7,0xE8,0x1B,0xF8,0x54,0xC2,0x7C,
+        0x46,0xE3,0xFB,0xF2,0xAB,0xBA,0xCD,0x29,
+        0xEC,0x4A,0xFF,0x51,0x73,0x69,0xC6,0x60
+    };
+
+    /* public key for party a */
+    byte pa[] = {
+        0x05,0x7E,0x23,0xEA,0x9F,0x1C,0xBE,0x8A,
+        0x27,0x16,0x8F,0x6E,0x69,0x6A,0x79,0x1D,
+        0xE6,0x1D,0xD3,0xAF,0x7A,0xCD,0x4E,0xEA,
+        0xCC,0x6E,0x7B,0xA5,0x14,0xFD,0xA8,0x63
+    };
+
+    /* secret key for party b */
+    byte sb[] = {
+        0x47,0xDC,0x3D,0x21,0x41,0x74,0x82,0x0E,
+        0x11,0x54,0xB4,0x9B,0xC6,0xCD,0xB2,0xAB,
+        0xD4,0x5E,0xE9,0x58,0x17,0x05,0x5D,0x25,
+        0x5A,0xA3,0x58,0x31,0xB7,0x0D,0x32,0x60
+    };
+
+    /* public key for party b */
+    byte pb[] = {
+        0x6E,0xB8,0x9D,0xA9,0x19,0x89,0xAE,0x37,
+        0xC7,0xEA,0xC7,0x61,0x8D,0x9E,0x5C,0x49,
+        0x51,0xDB,0xA1,0xD7,0x3C,0x28,0x5A,0xE1,
+        0xCD,0x26,0xA8,0x55,0x02,0x0E,0xEF,0x04
+    };
+
+    /* expected shared key */
+    byte ss[] = {
+        0x61,0x45,0x0C,0xD9,0x8E,0x36,0x01,0x6B,
+        0x58,0x77,0x6A,0x89,0x7A,0x9F,0x0A,0xEF,
+        0x73,0x8B,0x99,0xF0,0x94,0x68,0xB8,0xD6,
+        0xB8,0x51,0x11,0x84,0xD5,0x34,0x94,0xAB
+    };
+
+    if (wc_InitRng(&rng) != 0)
+        return -1001;
+
+    wc_curve25519_init(&userA);
+    wc_curve25519_init(&userB);
+    wc_curve25519_init(&pubKey);
+
+    /* make curve25519 keys */
+    if (wc_curve25519_make_key(&rng, 32, &userA) != 0)
+        return -1002;
+
+    if (wc_curve25519_make_key(&rng, 32, &userB) != 0)
+        return -1003;
+
+    /* find shared secret key */
+    if (wc_curve25519_shared_secret(&userA, &userB, sharedA, &x) != 0)
+        return -1004;
+
+    if (wc_curve25519_shared_secret(&userB, &userA, sharedB, &y) != 0)
+        return -1005;
+
+    /* compare shared secret keys to test they are the same */
+    if (y != x)
+        return -1006;
+
+    if (XMEMCMP(sharedA, sharedB, x))
+        return -1007;
+
+    /* export a public key and import it for another user */
+    if (wc_curve25519_export_public(&userA, exportBuf, &x) != 0)
+        return -1008;
+
+    if (wc_curve25519_import_public(exportBuf, x, &pubKey) != 0)
+        return -1009;
+
+    /* test shared key after importing a public key */
+    XMEMSET(sharedB, 0, sizeof(sharedB));
+    if (wc_curve25519_shared_secret(&userB, &pubKey, sharedB, &y) != 0)
+        return -1010;
+
+    if (XMEMCMP(sharedA, sharedB, y))
+        return -1011;
+
+    /* import RFC test vectors and compare shared key */
+    if (wc_curve25519_import_private_raw(sa, sizeof(sa), pa, sizeof(pa), &userA)
+            != 0)
+        return -1012;
+
+    if (wc_curve25519_import_private_raw(sb, sizeof(sb), pb, sizeof(pb), &userB)
+            != 0)
+        return -1013;
+
+    /* test against known test vector */
+    XMEMSET(sharedB, 0, sizeof(sharedB));
+    if (wc_curve25519_shared_secret(&userA, &userB, sharedB, &y) != 0)
+        return -1014;
+
+    if (XMEMCMP(ss, sharedB, y))
+        return -1015;
+
+    /* test swaping roles of keys and generating same shared key */
+    XMEMSET(sharedB, 0, sizeof(sharedB));
+    if (wc_curve25519_shared_secret(&userB, &userA, sharedB, &y) != 0)
+        return -1016;
+
+    if (XMEMCMP(ss, sharedB, y))
+        return -1017;
+
+    /* clean up keys when done */
+    wc_curve25519_free(&pubKey);
+    wc_curve25519_free(&userB);
+    wc_curve25519_free(&userA);
+
+    wc_FreeRng(&rng);
+
+    return 0;
+}
+#endif /* HAVE_CURVE25519 */
+
+
+#ifdef HAVE_ED25519
+int ed25519_test(void)
+{
+    RNG    rng;
+    byte   out[ED25519_SIG_SIZE];
+    byte   exportPKey[ED25519_KEY_SIZE];
+    byte   exportSKey[ED25519_KEY_SIZE];
+    word32 outlen;
+    word32 exportPSz;
+    word32 exportSSz;
+    word32 keySz, sigSz;
+    int    i, verify;
+    ed25519_key key;
+    ed25519_key key2;
+
+    /* test vectors from
+       https://tools.ietf.org/html/draft-josefsson-eddsa-ed25519-02
+     */
+
+    const byte sKey1[] = {
+		0x9d,0x61,0xb1,0x9d,0xef,0xfd,0x5a,0x60,
+		0xba,0x84,0x4a,0xf4,0x92,0xec,0x2c,0xc4,
+		0x44,0x49,0xc5,0x69,0x7b,0x32,0x69,0x19,
+		0x70,0x3b,0xac,0x03,0x1c,0xae,0x7f,0x60
+    };
+
+    const byte sKey2[] = {
+		0x4c,0xcd,0x08,0x9b,0x28,0xff,0x96,0xda,
+		0x9d,0xb6,0xc3,0x46,0xec,0x11,0x4e,0x0f,
+		0x5b,0x8a,0x31,0x9f,0x35,0xab,0xa6,0x24,
+		0xda,0x8c,0xf6,0xed,0x4f,0xb8,0xa6,0xfb
+    };
+
+    const byte sKey3[] = {
+		0xc5,0xaa,0x8d,0xf4,0x3f,0x9f,0x83,0x7b,
+		0xed,0xb7,0x44,0x2f,0x31,0xdc,0xb7,0xb1,
+		0x66,0xd3,0x85,0x35,0x07,0x6f,0x09,0x4b,
+		0x85,0xce,0x3a,0x2e,0x0b,0x44,0x58,0xf7
+    };
+
+    /* uncompressed test */
+    const byte sKey4[] = {
+		0x9d,0x61,0xb1,0x9d,0xef,0xfd,0x5a,0x60,
+		0xba,0x84,0x4a,0xf4,0x92,0xec,0x2c,0xc4,
+		0x44,0x49,0xc5,0x69,0x7b,0x32,0x69,0x19,
+		0x70,0x3b,0xac,0x03,0x1c,0xae,0x7f,0x60
+    };
+
+    /* compressed prefix test */
+    const byte sKey5[] = {
+		0x9d,0x61,0xb1,0x9d,0xef,0xfd,0x5a,0x60,
+		0xba,0x84,0x4a,0xf4,0x92,0xec,0x2c,0xc4,
+		0x44,0x49,0xc5,0x69,0x7b,0x32,0x69,0x19,
+		0x70,0x3b,0xac,0x03,0x1c,0xae,0x7f,0x60
+    };
+
+    const byte sKey6[] = {
+		0xf5,0xe5,0x76,0x7c,0xf1,0x53,0x31,0x95,
+		0x17,0x63,0x0f,0x22,0x68,0x76,0xb8,0x6c,
+		0x81,0x60,0xcc,0x58,0x3b,0xc0,0x13,0x74,
+		0x4c,0x6b,0xf2,0x55,0xf5,0xcc,0x0e,0xe5
+    };
+
+    const byte* sKeys[] = {sKey1, sKey2, sKey3, sKey4, sKey5, sKey6};
+
+    const byte pKey1[] = {
+		0xd7,0x5a,0x98,0x01,0x82,0xb1,0x0a,0xb7,
+		0xd5,0x4b,0xfe,0xd3,0xc9,0x64,0x07,0x3a,
+		0x0e,0xe1,0x72,0xf3,0xda,0xa6,0x23,0x25,
+		0xaf,0x02,0x1a,0x68,0xf7,0x07,0x51,0x1a
+    };
+
+    const byte pKey2[] = {
+		0x3d,0x40,0x17,0xc3,0xe8,0x43,0x89,0x5a,
+		0x92,0xb7,0x0a,0xa7,0x4d,0x1b,0x7e,0xbc,
+        0x9c,0x98,0x2c,0xcf,0x2e,0xc4,0x96,0x8c,
+		0xc0,0xcd,0x55,0xf1,0x2a,0xf4,0x66,0x0c
+    };
+
+    const byte pKey3[] = {
+		0xfc,0x51,0xcd,0x8e,0x62,0x18,0xa1,0xa3,
+		0x8d,0xa4,0x7e,0xd0,0x02,0x30,0xf0,0x58,
+		0x08,0x16,0xed,0x13,0xba,0x33,0x03,0xac,
+		0x5d,0xeb,0x91,0x15,0x48,0x90,0x80,0x25
+    };
+
+    /* uncompressed test */
+    const byte pKey4[] = {
+		0x04,0x55,0xd0,0xe0,0x9a,0x2b,0x9d,0x34,
+		0x29,0x22,0x97,0xe0,0x8d,0x60,0xd0,0xf6,
+		0x20,0xc5,0x13,0xd4,0x72,0x53,0x18,0x7c,
+		0x24,0xb1,0x27,0x86,0xbd,0x77,0x76,0x45,
+		0xce,0x1a,0x51,0x07,0xf7,0x68,0x1a,0x02,
+		0xaf,0x25,0x23,0xa6,0xda,0xf3,0x72,0xe1,
+		0x0e,0x3a,0x07,0x64,0xc9,0xd3,0xfe,0x4b,
+		0xd5,0xb7,0x0a,0xb1,0x82,0x01,0x98,0x5a,
+		0xd7
+    };
+
+    /* compressed prefix */
+    const byte pKey5[] = {
+		0x40,0xd7,0x5a,0x98,0x01,0x82,0xb1,0x0a,0xb7,
+		0xd5,0x4b,0xfe,0xd3,0xc9,0x64,0x07,0x3a,
+		0x0e,0xe1,0x72,0xf3,0xda,0xa6,0x23,0x25,
+		0xaf,0x02,0x1a,0x68,0xf7,0x07,0x51,0x1a
+    };
+
+    const byte pKey6[] = {
+		0x27,0x81,0x17,0xfc,0x14,0x4c,0x72,0x34,
+		0x0f,0x67,0xd0,0xf2,0x31,0x6e,0x83,0x86,
+		0xce,0xff,0xbf,0x2b,0x24,0x28,0xc9,0xc5,
+		0x1f,0xef,0x7c,0x59,0x7f,0x1d,0x42,0x6e
+    };
+
+    const byte* pKeys[] = {pKey1, pKey2, pKey3, pKey4, pKey5, pKey6};
+    const byte  pKeySz[] = {sizeof(pKey1), sizeof(pKey2), sizeof(pKey3),
+                            sizeof(pKey4), sizeof(pKey5), sizeof(pKey6)};
+
+    const byte sig1[] = {
+		0xe5,0x56,0x43,0x00,0xc3,0x60,0xac,0x72,
+		0x90,0x86,0xe2,0xcc,0x80,0x6e,0x82,0x8a,
+		0x84,0x87,0x7f,0x1e,0xb8,0xe5,0xd9,0x74,
+		0xd8,0x73,0xe0,0x65,0x22,0x49,0x01,0x55,
+		0x5f,0xb8,0x82,0x15,0x90,0xa3,0x3b,0xac,
+		0xc6,0x1e,0x39,0x70,0x1c,0xf9,0xb4,0x6b,
+		0xd2,0x5b,0xf5,0xf0,0x59,0x5b,0xbe,0x24,
+		0x65,0x51,0x41,0x43,0x8e,0x7a,0x10,0x0b
+    };
+
+    const byte sig2[] = {
+		0x92,0xa0,0x09,0xa9,0xf0,0xd4,0xca,0xb8,
+		0x72,0x0e,0x82,0x0b,0x5f,0x64,0x25,0x40,
+		0xa2,0xb2,0x7b,0x54,0x16,0x50,0x3f,0x8f,
+		0xb3,0x76,0x22,0x23,0xeb,0xdb,0x69,0xda,
+		0x08,0x5a,0xc1,0xe4,0x3e,0x15,0x99,0x6e,
+		0x45,0x8f,0x36,0x13,0xd0,0xf1,0x1d,0x8c,
+		0x38,0x7b,0x2e,0xae,0xb4,0x30,0x2a,0xee,
+		0xb0,0x0d,0x29,0x16,0x12,0xbb,0x0c,0x00
+    };
+
+    const byte sig3[] = {
+		0x62,0x91,0xd6,0x57,0xde,0xec,0x24,0x02,
+		0x48,0x27,0xe6,0x9c,0x3a,0xbe,0x01,0xa3,
+		0x0c,0xe5,0x48,0xa2,0x84,0x74,0x3a,0x44,
+		0x5e,0x36,0x80,0xd7,0xdb,0x5a,0xc3,0xac,
+		0x18,0xff,0x9b,0x53,0x8d,0x16,0xf2,0x90,
+		0xae,0x67,0xf7,0x60,0x98,0x4d,0xc6,0x59,
+		0x4a,0x7c,0x15,0xe9,0x71,0x6e,0xd2,0x8d,
+		0xc0,0x27,0xbe,0xce,0xea,0x1e,0xc4,0x0a
+    };
+
+    /* uncompressed test */
+    const byte sig4[] = {
+		0xe5,0x56,0x43,0x00,0xc3,0x60,0xac,0x72,
+		0x90,0x86,0xe2,0xcc,0x80,0x6e,0x82,0x8a,
+		0x84,0x87,0x7f,0x1e,0xb8,0xe5,0xd9,0x74,
+		0xd8,0x73,0xe0,0x65,0x22,0x49,0x01,0x55,
+		0x5f,0xb8,0x82,0x15,0x90,0xa3,0x3b,0xac,
+		0xc6,0x1e,0x39,0x70,0x1c,0xf9,0xb4,0x6b,
+		0xd2,0x5b,0xf5,0xf0,0x59,0x5b,0xbe,0x24,
+		0x65,0x51,0x41,0x43,0x8e,0x7a,0x10,0x0b
+    };
+
+    /* compressed prefix */
+    const byte sig5[] = {
+		0xe5,0x56,0x43,0x00,0xc3,0x60,0xac,0x72,
+		0x90,0x86,0xe2,0xcc,0x80,0x6e,0x82,0x8a,
+		0x84,0x87,0x7f,0x1e,0xb8,0xe5,0xd9,0x74,
+		0xd8,0x73,0xe0,0x65,0x22,0x49,0x01,0x55,
+		0x5f,0xb8,0x82,0x15,0x90,0xa3,0x3b,0xac,
+		0xc6,0x1e,0x39,0x70,0x1c,0xf9,0xb4,0x6b,
+		0xd2,0x5b,0xf5,0xf0,0x59,0x5b,0xbe,0x24,
+		0x65,0x51,0x41,0x43,0x8e,0x7a,0x10,0x0b
+    };
+
+    const byte sig6[] = {
+		0x0a,0xab,0x4c,0x90,0x05,0x01,0xb3,0xe2,
+		0x4d,0x7c,0xdf,0x46,0x63,0x32,0x6a,0x3a,
+		0x87,0xdf,0x5e,0x48,0x43,0xb2,0xcb,0xdb,
+		0x67,0xcb,0xf6,0xe4,0x60,0xfe,0xc3,0x50,
+		0xaa,0x53,0x71,0xb1,0x50,0x8f,0x9f,0x45,
+		0x28,0xec,0xea,0x23,0xc4,0x36,0xd9,0x4b,
+		0x5e,0x8f,0xcd,0x4f,0x68,0x1e,0x30,0xa6,
+		0xac,0x00,0xa9,0x70,0x4a,0x18,0x8a,0x03
+    };
+
+    const byte* sigs[] = {sig1, sig2, sig3, sig4, sig5, sig6};
+
+    const byte msg1[]  = {};
+    const byte msg2[]  = {0x72};
+    const byte msg3[]  = {0xAF,0x82};
+
+    /* test of a 1024 byte long message */
+    const byte msg4[]  = {
+		0x08,0xb8,0xb2,0xb7,0x33,0x42,0x42,0x43,
+		0x76,0x0f,0xe4,0x26,0xa4,0xb5,0x49,0x08,
+		0x63,0x21,0x10,0xa6,0x6c,0x2f,0x65,0x91,
+		0xea,0xbd,0x33,0x45,0xe3,0xe4,0xeb,0x98,
+		0xfa,0x6e,0x26,0x4b,0xf0,0x9e,0xfe,0x12,
+		0xee,0x50,0xf8,0xf5,0x4e,0x9f,0x77,0xb1,
+		0xe3,0x55,0xf6,0xc5,0x05,0x44,0xe2,0x3f,
+		0xb1,0x43,0x3d,0xdf,0x73,0xbe,0x84,0xd8,
+		0x79,0xde,0x7c,0x00,0x46,0xdc,0x49,0x96,
+		0xd9,0xe7,0x73,0xf4,0xbc,0x9e,0xfe,0x57,
+		0x38,0x82,0x9a,0xdb,0x26,0xc8,0x1b,0x37,
+		0xc9,0x3a,0x1b,0x27,0x0b,0x20,0x32,0x9d,
+		0x65,0x86,0x75,0xfc,0x6e,0xa5,0x34,0xe0,
+		0x81,0x0a,0x44,0x32,0x82,0x6b,0xf5,0x8c,
+		0x94,0x1e,0xfb,0x65,0xd5,0x7a,0x33,0x8b,
+		0xbd,0x2e,0x26,0x64,0x0f,0x89,0xff,0xbc,
+		0x1a,0x85,0x8e,0xfc,0xb8,0x55,0x0e,0xe3,
+		0xa5,0xe1,0x99,0x8b,0xd1,0x77,0xe9,0x3a,
+		0x73,0x63,0xc3,0x44,0xfe,0x6b,0x19,0x9e,
+		0xe5,0xd0,0x2e,0x82,0xd5,0x22,0xc4,0xfe,
+		0xba,0x15,0x45,0x2f,0x80,0x28,0x8a,0x82,
+		0x1a,0x57,0x91,0x16,0xec,0x6d,0xad,0x2b,
+		0x3b,0x31,0x0d,0xa9,0x03,0x40,0x1a,0xa6,
+		0x21,0x00,0xab,0x5d,0x1a,0x36,0x55,0x3e,
+		0x06,0x20,0x3b,0x33,0x89,0x0c,0xc9,0xb8,
+		0x32,0xf7,0x9e,0xf8,0x05,0x60,0xcc,0xb9,
+		0xa3,0x9c,0xe7,0x67,0x96,0x7e,0xd6,0x28,
+		0xc6,0xad,0x57,0x3c,0xb1,0x16,0xdb,0xef,
+		0xef,0xd7,0x54,0x99,0xda,0x96,0xbd,0x68,
+		0xa8,0xa9,0x7b,0x92,0x8a,0x8b,0xbc,0x10,
+		0x3b,0x66,0x21,0xfc,0xde,0x2b,0xec,0xa1,
+		0x23,0x1d,0x20,0x6b,0xe6,0xcd,0x9e,0xc7,
+		0xaf,0xf6,0xf6,0xc9,0x4f,0xcd,0x72,0x04,
+		0xed,0x34,0x55,0xc6,0x8c,0x83,0xf4,0xa4,
+		0x1d,0xa4,0xaf,0x2b,0x74,0xef,0x5c,0x53,
+		0xf1,0xd8,0xac,0x70,0xbd,0xcb,0x7e,0xd1,
+		0x85,0xce,0x81,0xbd,0x84,0x35,0x9d,0x44,
+		0x25,0x4d,0x95,0x62,0x9e,0x98,0x55,0xa9,
+		0x4a,0x7c,0x19,0x58,0xd1,0xf8,0xad,0xa5,
+		0xd0,0x53,0x2e,0xd8,0xa5,0xaa,0x3f,0xb2,
+		0xd1,0x7b,0xa7,0x0e,0xb6,0x24,0x8e,0x59,
+		0x4e,0x1a,0x22,0x97,0xac,0xbb,0xb3,0x9d,
+		0x50,0x2f,0x1a,0x8c,0x6e,0xb6,0xf1,0xce,
+		0x22,0xb3,0xde,0x1a,0x1f,0x40,0xcc,0x24,
+		0x55,0x41,0x19,0xa8,0x31,0xa9,0xaa,0xd6,
+		0x07,0x9c,0xad,0x88,0x42,0x5d,0xe6,0xbd,
+		0xe1,0xa9,0x18,0x7e,0xbb,0x60,0x92,0xcf,
+		0x67,0xbf,0x2b,0x13,0xfd,0x65,0xf2,0x70,
+		0x88,0xd7,0x8b,0x7e,0x88,0x3c,0x87,0x59,
+		0xd2,0xc4,0xf5,0xc6,0x5a,0xdb,0x75,0x53,
+		0x87,0x8a,0xd5,0x75,0xf9,0xfa,0xd8,0x78,
+		0xe8,0x0a,0x0c,0x9b,0xa6,0x3b,0xcb,0xcc,
+		0x27,0x32,0xe6,0x94,0x85,0xbb,0xc9,0xc9,
+		0x0b,0xfb,0xd6,0x24,0x81,0xd9,0x08,0x9b,
+		0xec,0xcf,0x80,0xcf,0xe2,0xdf,0x16,0xa2,
+		0xcf,0x65,0xbd,0x92,0xdd,0x59,0x7b,0x07,
+		0x07,0xe0,0x91,0x7a,0xf4,0x8b,0xbb,0x75,
+		0xfe,0xd4,0x13,0xd2,0x38,0xf5,0x55,0x5a,
+		0x7a,0x56,0x9d,0x80,0xc3,0x41,0x4a,0x8d,
+		0x08,0x59,0xdc,0x65,0xa4,0x61,0x28,0xba,
+		0xb2,0x7a,0xf8,0x7a,0x71,0x31,0x4f,0x31,
+		0x8c,0x78,0x2b,0x23,0xeb,0xfe,0x80,0x8b,
+		0x82,0xb0,0xce,0x26,0x40,0x1d,0x2e,0x22,
+		0xf0,0x4d,0x83,0xd1,0x25,0x5d,0xc5,0x1a,
+		0xdd,0xd3,0xb7,0x5a,0x2b,0x1a,0xe0,0x78,
+		0x45,0x04,0xdf,0x54,0x3a,0xf8,0x96,0x9b,
+		0xe3,0xea,0x70,0x82,0xff,0x7f,0xc9,0x88,
+		0x8c,0x14,0x4d,0xa2,0xaf,0x58,0x42,0x9e,
+		0xc9,0x60,0x31,0xdb,0xca,0xd3,0xda,0xd9,
+		0xaf,0x0d,0xcb,0xaa,0xaf,0x26,0x8c,0xb8,
+		0xfc,0xff,0xea,0xd9,0x4f,0x3c,0x7c,0xa4,
+		0x95,0xe0,0x56,0xa9,0xb4,0x7a,0xcd,0xb7,
+		0x51,0xfb,0x73,0xe6,0x66,0xc6,0xc6,0x55,
+		0xad,0xe8,0x29,0x72,0x97,0xd0,0x7a,0xd1,
+		0xba,0x5e,0x43,0xf1,0xbc,0xa3,0x23,0x01,
+		0x65,0x13,0x39,0xe2,0x29,0x04,0xcc,0x8c,
+		0x42,0xf5,0x8c,0x30,0xc0,0x4a,0xaf,0xdb,
+		0x03,0x8d,0xda,0x08,0x47,0xdd,0x98,0x8d,
+		0xcd,0xa6,0xf3,0xbf,0xd1,0x5c,0x4b,0x4c,
+		0x45,0x25,0x00,0x4a,0xa0,0x6e,0xef,0xf8,
+		0xca,0x61,0x78,0x3a,0xac,0xec,0x57,0xfb,
+		0x3d,0x1f,0x92,0xb0,0xfe,0x2f,0xd1,0xa8,
+		0x5f,0x67,0x24,0x51,0x7b,0x65,0xe6,0x14,
+		0xad,0x68,0x08,0xd6,0xf6,0xee,0x34,0xdf,
+		0xf7,0x31,0x0f,0xdc,0x82,0xae,0xbf,0xd9,
+		0x04,0xb0,0x1e,0x1d,0xc5,0x4b,0x29,0x27,
+		0x09,0x4b,0x2d,0xb6,0x8d,0x6f,0x90,0x3b,
+		0x68,0x40,0x1a,0xde,0xbf,0x5a,0x7e,0x08,
+		0xd7,0x8f,0xf4,0xef,0x5d,0x63,0x65,0x3a,
+		0x65,0x04,0x0c,0xf9,0xbf,0xd4,0xac,0xa7,
+		0x98,0x4a,0x74,0xd3,0x71,0x45,0x98,0x67,
+		0x80,0xfc,0x0b,0x16,0xac,0x45,0x16,0x49,
+		0xde,0x61,0x88,0xa7,0xdb,0xdf,0x19,0x1f,
+		0x64,0xb5,0xfc,0x5e,0x2a,0xb4,0x7b,0x57,
+		0xf7,0xf7,0x27,0x6c,0xd4,0x19,0xc1,0x7a,
+		0x3c,0xa8,0xe1,0xb9,0x39,0xae,0x49,0xe4,
+		0x88,0xac,0xba,0x6b,0x96,0x56,0x10,0xb5,
+		0x48,0x01,0x09,0xc8,0xb1,0x7b,0x80,0xe1,
+		0xb7,0xb7,0x50,0xdf,0xc7,0x59,0x8d,0x5d,
+		0x50,0x11,0xfd,0x2d,0xcc,0x56,0x00,0xa3,
+		0x2e,0xf5,0xb5,0x2a,0x1e,0xcc,0x82,0x0e,
+		0x30,0x8a,0xa3,0x42,0x72,0x1a,0xac,0x09,
+		0x43,0xbf,0x66,0x86,0xb6,0x4b,0x25,0x79,
+		0x37,0x65,0x04,0xcc,0xc4,0x93,0xd9,0x7e,
+		0x6a,0xed,0x3f,0xb0,0xf9,0xcd,0x71,0xa4,
+		0x3d,0xd4,0x97,0xf0,0x1f,0x17,0xc0,0xe2,
+		0xcb,0x37,0x97,0xaa,0x2a,0x2f,0x25,0x66,
+		0x56,0x16,0x8e,0x6c,0x49,0x6a,0xfc,0x5f,
+		0xb9,0x32,0x46,0xf6,0xb1,0x11,0x63,0x98,
+		0xa3,0x46,0xf1,0xa6,0x41,0xf3,0xb0,0x41,
+		0xe9,0x89,0xf7,0x91,0x4f,0x90,0xcc,0x2c,
+		0x7f,0xff,0x35,0x78,0x76,0xe5,0x06,0xb5,
+		0x0d,0x33,0x4b,0xa7,0x7c,0x22,0x5b,0xc3,
+		0x07,0xba,0x53,0x71,0x52,0xf3,0xf1,0x61,
+		0x0e,0x4e,0xaf,0xe5,0x95,0xf6,0xd9,0xd9,
+		0x0d,0x11,0xfa,0xa9,0x33,0xa1,0x5e,0xf1,
+		0x36,0x95,0x46,0x86,0x8a,0x7f,0x3a,0x45,
+		0xa9,0x67,0x68,0xd4,0x0f,0xd9,0xd0,0x34,
+		0x12,0xc0,0x91,0xc6,0x31,0x5c,0xf4,0xfd,
+		0xe7,0xcb,0x68,0x60,0x69,0x37,0x38,0x0d,
+		0xb2,0xea,0xaa,0x70,0x7b,0x4c,0x41,0x85,
+		0xc3,0x2e,0xdd,0xcd,0xd3,0x06,0x70,0x5e,
+		0x4d,0xc1,0xff,0xc8,0x72,0xee,0xee,0x47,
+		0x5a,0x64,0xdf,0xac,0x86,0xab,0xa4,0x1c,
+		0x06,0x18,0x98,0x3f,0x87,0x41,0xc5,0xef,
+		0x68,0xd3,0xa1,0x01,0xe8,0xa3,0xb8,0xca,
+		0xc6,0x0c,0x90,0x5c,0x15,0xfc,0x91,0x08,
+		0x40,0xb9,0x4c,0x00,0xa0,0xb9,0xd0
+    };
+
+    const byte* msgs[] = {msg1, msg2, msg3, msg1, msg1, msg4};
+    const word16 msgSz[] = {sizeof(msg1), sizeof(msg2), sizeof(msg3),
+                            sizeof(msg1), sizeof(msg1), sizeof(msg4)};
+
+    /* create ed25519 keys */
+    wc_InitRng(&rng);
+    wc_ed25519_init(&key);
+    wc_ed25519_init(&key2);
+    wc_ed25519_make_key(&rng, ED25519_KEY_SIZE, &key);
+    wc_ed25519_make_key(&rng, ED25519_KEY_SIZE, &key2);
+
+    /* helper functions for signature and key size */
+    keySz = wc_ed25519_size(&key);
+    sigSz = wc_ed25519_sig_size(&key);
+
+    for (i = 0; i < 6; i++) {
+        outlen = sizeof(out);
+        XMEMSET(out, 0, sizeof(out));
+
+        if (wc_ed25519_import_private_key(sKeys[i], ED25519_KEY_SIZE, pKeys[i],
+                pKeySz[i], &key) != 0)
+            return -1021 - i;
+
+        if (wc_ed25519_sign_msg(msgs[i], msgSz[i], out, &outlen, &key)
+                != 0)
+            return -1027 - i;
+
+        if (XMEMCMP(out, sigs[i], 64))
+            return -1033 - i;
+
+        /* test verify on good msg */
+        if (wc_ed25519_verify_msg(out, outlen, msgs[i], msgSz[i], &verify,
+                    &key) != 0 || verify != 1)
+            return -1039 - i;
+
+        /* test verify on bad msg */
+        out[outlen-1] = out[outlen-1] + 1;
+        if (wc_ed25519_verify_msg(out, outlen, msgs[i], msgSz[i], &verify,
+                    &key) == 0 || verify == 1)
+            return -1045 - i;
+
+        /* test api for import/exporting keys */
+        exportPSz = sizeof(exportPKey);
+        exportSSz = sizeof(exportSKey);
+        if (wc_ed25519_export_public(&key, exportPKey, &exportPSz) != 0)
+            return -1051 - i;
+
+        if (wc_ed25519_import_public(exportPKey, exportPSz, &key2) != 0)
+            return -1057 - i;
+
+        if (wc_ed25519_export_private_only(&key, exportSKey, &exportSSz) != 0)
+            return -1063 - i;
+
+        if (wc_ed25519_import_private_key(exportSKey, exportSSz,
+                                          exportPKey, exportPSz, &key2) != 0)
+            return -1069 - i;
+
+        /* clear "out" buffer and test sign with imported keys */
+        outlen = sizeof(out);
+        XMEMSET(out, 0, sizeof(out));
+        if (wc_ed25519_sign_msg(msgs[i], msgSz[i], out, &outlen, &key2) != 0)
+            return -1075 - i;
+
+        if (wc_ed25519_verify_msg(out, outlen, msgs[i], msgSz[i], &verify,
+                                  &key2) != 0 || verify != 1)
+            return -1081 - i;
+
+        if (XMEMCMP(out, sigs[i], 64))
+            return -1087 - i;
+    }
+
+    /* clean up keys when done */
+    wc_ed25519_free(&key);
+    wc_ed25519_free(&key2);
+
+#if defined(HAVE_HASHDRBG) || defined(NO_RC4)
+    wc_FreeRng(&rng);
+#endif
+
+    /* hush warrnings of unused keySz and sigSz */
+    (void)keySz;
+    (void)sigSz;
+
+    return 0;
+}
+#endif /* HAVE_ED25519 */
+
+
+#ifdef HAVE_LIBZ
+
+const byte sample_text[] =
+    "Biodiesel cupidatat marfa, cliche aute put a bird on it incididunt elit\n"
+    "polaroid. Sunt tattooed bespoke reprehenderit. Sint twee organic id\n"
+    "marfa. Commodo veniam ad esse gastropub. 3 wolf moon sartorial vero,\n"
+    "plaid delectus biodiesel squid +1 vice. Post-ironic keffiyeh leggings\n"
+    "selfies cray fap hoodie, forage anim. Carles cupidatat shoreditch, VHS\n"
+    "small batch meggings kogi dolore food truck bespoke gastropub.\n"
+    "\n"
+    "Terry richardson adipisicing actually typewriter tumblr, twee whatever\n"
+    "four loko you probably haven't heard of them high life. Messenger bag\n"
+    "whatever tattooed deep v mlkshk. Brooklyn pinterest assumenda chillwave\n"
+    "et, banksy ullamco messenger bag umami pariatur direct trade forage.\n"
+    "Typewriter culpa try-hard, pariatur sint brooklyn meggings. Gentrify\n"
+    "food truck next level, tousled irony non semiotics PBR ethical anim cred\n"
+    "readymade. Mumblecore brunch lomo odd future, portland organic terry\n"
+    "richardson elit leggings adipisicing ennui raw denim banjo hella. Godard\n"
+    "mixtape polaroid, pork belly readymade organic cray typewriter helvetica\n"
+    "four loko whatever street art yr farm-to-table.\n"
+    "\n"
+    "Vinyl keytar vice tofu. Locavore you probably haven't heard of them pug\n"
+    "pickled, hella tonx labore truffaut DIY mlkshk elit cosby sweater sint\n"
+    "et mumblecore. Elit swag semiotics, reprehenderit DIY sartorial nisi ugh\n"
+    "nesciunt pug pork belly wayfarers selfies delectus. Ethical hoodie\n"
+    "seitan fingerstache kale chips. Terry richardson artisan williamsburg,\n"
+    "eiusmod fanny pack irony tonx ennui lo-fi incididunt tofu YOLO\n"
+    "readymade. 8-bit sed ethnic beard officia. Pour-over iphone DIY butcher,\n"
+    "ethnic art party qui letterpress nisi proident jean shorts mlkshk\n"
+    "locavore.\n"
+    "\n"
+    "Narwhal flexitarian letterpress, do gluten-free voluptate next level\n"
+    "banh mi tonx incididunt carles DIY. Odd future nulla 8-bit beard ut\n"
+    "cillum pickled velit, YOLO officia you probably haven't heard of them\n"
+    "trust fund gastropub. Nisi adipisicing tattooed, Austin mlkshk 90's\n"
+    "small batch american apparel. Put a bird on it cosby sweater before they\n"
+    "sold out pork belly kogi hella. Street art mollit sustainable polaroid,\n"
+    "DIY ethnic ea pug beard dreamcatcher cosby sweater magna scenester nisi.\n"
+    "Sed pork belly skateboard mollit, labore proident eiusmod. Sriracha\n"
+    "excepteur cosby sweater, anim deserunt laborum eu aliquip ethical et\n"
+    "neutra PBR selvage.\n"
+    "\n"
+    "Raw denim pork belly truffaut, irony plaid sustainable put a bird on it\n"
+    "next level jean shorts exercitation. Hashtag keytar whatever, nihil\n"
+    "authentic aliquip disrupt laborum. Tattooed selfies deserunt trust fund\n"
+    "wayfarers. 3 wolf moon synth church-key sartorial, gastropub leggings\n"
+    "tattooed. Labore high life commodo, meggings raw denim fingerstache pug\n"
+    "trust fund leggings seitan forage. Nostrud ullamco duis, reprehenderit\n"
+    "incididunt flannel sustainable helvetica pork belly pug banksy you\n"
+    "probably haven't heard of them nesciunt farm-to-table. Disrupt nostrud\n"
+    "mollit magna, sriracha sartorial helvetica.\n"
+    "\n"
+    "Nulla kogi reprehenderit, skateboard sustainable duis adipisicing viral\n"
+    "ad fanny pack salvia. Fanny pack trust fund you probably haven't heard\n"
+    "of them YOLO vice nihil. Keffiyeh cray lo-fi pinterest cardigan aliqua,\n"
+    "reprehenderit aute. Culpa tousled williamsburg, marfa lomo actually anim\n"
+    "skateboard. Iphone aliqua ugh, semiotics pariatur vero readymade\n"
+    "organic. Marfa squid nulla, in laborum disrupt laboris irure gastropub.\n"
+    "Veniam sunt food truck leggings, sint vinyl fap.\n"
+    "\n"
+    "Hella dolore pork belly, truffaut carles you probably haven't heard of\n"
+    "them PBR helvetica in sapiente. Fashion axe ugh bushwick american\n"
+    "apparel. Fingerstache sed iphone, jean shorts blue bottle nisi bushwick\n"
+    "flexitarian officia veniam plaid bespoke fap YOLO lo-fi. Blog\n"
+    "letterpress mumblecore, food truck id cray brooklyn cillum ad sed.\n"
+    "Assumenda chambray wayfarers vinyl mixtape sustainable. VHS vinyl\n"
+    "delectus, culpa williamsburg polaroid cliche swag church-key synth kogi\n"
+    "magna pop-up literally. Swag thundercats ennui shoreditch vegan\n"
+    "pitchfork neutra truffaut etsy, sed single-origin coffee craft beer.\n"
+    "\n"
+    "Odio letterpress brooklyn elit. Nulla single-origin coffee in occaecat\n"
+    "meggings. Irony meggings 8-bit, chillwave lo-fi adipisicing cred\n"
+    "dreamcatcher veniam. Put a bird on it irony umami, trust fund bushwick\n"
+    "locavore kale chips. Sriracha swag thundercats, chillwave disrupt\n"
+    "tousled beard mollit mustache leggings portland next level. Nihil esse\n"
+    "est, skateboard art party etsy thundercats sed dreamcatcher ut iphone\n"
+    "swag consectetur et. Irure skateboard banjo, nulla deserunt messenger\n"
+    "bag dolor terry richardson sapiente.\n";
+
+
+int compress_test(void)
+{
+    int ret = 0;
+    word32 dSz = sizeof(sample_text);
+    word32 cSz = (dSz + (word32)(dSz * 0.001) + 12);
+    byte *c = NULL;
+    byte *d = NULL;
+
+    c = calloc(cSz, sizeof(byte));
+    d = calloc(dSz, sizeof(byte));
+
+    if (c == NULL || d == NULL)
+        ret = -300;
+
+    if (ret == 0 && (ret = wc_Compress(c, cSz, sample_text, dSz, 0)) < 0)
+        ret = -301;
+
+    if (ret > 0) {
+        cSz = (word32)ret;
+        ret = 0;
+    }
+
+    if (ret == 0 && wc_DeCompress(d, dSz, c, cSz) != (int)dSz)
+        ret = -302;
+
+    if (ret == 0 && memcmp(d, sample_text, dSz))
+        ret = -303;
+
+    if (c) free(c);
+    if (d) free(d);
+
+    return ret;
+}
+
+#endif /* HAVE_LIBZ */
+
+#ifdef HAVE_PKCS7
+
+int pkcs7enveloped_test(void)
+{
+    int ret = 0;
+
+    int cipher = DES3b;
+    int envelopedSz, decodedSz;
+    PKCS7 pkcs7;
+    byte* cert;
+    byte* privKey;
+    byte  enveloped[2048];
+    byte  decoded[2048];
+
+    size_t certSz;
+    size_t privKeySz;
+    FILE*  certFile;
+    FILE*  keyFile;
+    FILE*  pkcs7File;
+    const char* pkcs7OutFile = "pkcs7envelopedData.der";
+
+    const byte data[] = { /* Hello World */
+        0x48,0x65,0x6c,0x6c,0x6f,0x20,0x57,0x6f,
+        0x72,0x6c,0x64
+    };
+
+    /* read client cert and key in DER format */
+    cert = (byte*)malloc(FOURK_BUF);
+    if (cert == NULL)
+        return -201;
+
+    privKey = (byte*)malloc(FOURK_BUF);
+    if (privKey == NULL) {
+        free(cert);
+        return -202;
+    }
+
+    certFile = fopen(clientCert, "rb");
+    if (!certFile) {
+        free(cert);
+        free(privKey);
+        err_sys("can't open ./certs/client-cert.der, "
+                "Please run from wolfSSL home dir", -42);
+        return -42;
+    }
+
+    certSz = fread(cert, 1, FOURK_BUF, certFile);
+    fclose(certFile);
+
+    keyFile = fopen(clientKey, "rb");
+    if (!keyFile) {
+        free(cert);
+        free(privKey);
+        err_sys("can't open ./certs/client-key.der, "
+                "Please run from wolfSSL home dir", -43);
+        return -43;
+    }
+
+    privKeySz = fread(privKey, 1, FOURK_BUF, keyFile);
+    fclose(keyFile);
+
+    wc_PKCS7_InitWithCert(&pkcs7, cert, (word32)certSz);
+    pkcs7.content     = (byte*)data;
+    pkcs7.contentSz   = (word32)sizeof(data);
+    pkcs7.contentOID  = DATA;
+    pkcs7.encryptOID  = cipher;
+    pkcs7.privateKey  = privKey;
+    pkcs7.privateKeySz = (word32)privKeySz;
+
+    /* encode envelopedData */
+    envelopedSz = wc_PKCS7_EncodeEnvelopedData(&pkcs7, enveloped,
+                                            sizeof(enveloped));
+    if (envelopedSz <= 0) {
+        free(cert);
+        free(privKey);
+        return -203;
+    }
+
+    /* decode envelopedData */
+    decodedSz = wc_PKCS7_DecodeEnvelopedData(&pkcs7, enveloped, envelopedSz,
+                                          decoded, sizeof(decoded));
+    if (decodedSz <= 0) {
+        free(cert);
+        free(privKey);
+        return -204;
+    }
+
+    /* test decode result */
+    if (memcmp(decoded, data, sizeof(data)) != 0) {
+        free(cert);
+        free(privKey);
+        return -205;
+    }
+
+    /* output pkcs7 envelopedData for external testing */
+    pkcs7File = fopen(pkcs7OutFile, "wb");
+    if (!pkcs7File) {
+        free(cert);
+        free(privKey);
+        return -206;
+    }
+
+    ret = (int)fwrite(enveloped, envelopedSz, 1, pkcs7File);
+    fclose(pkcs7File);
+
+    free(cert);
+    free(privKey);
+    wc_PKCS7_Free(&pkcs7);
+
+    if (ret > 0)
+        return 0;
+
+    return ret;
+}
+
+int pkcs7signed_test(void)
+{
+    int ret = 0;
+
+    FILE* file;
+    byte* certDer;
+    byte* keyDer;
+    byte* out;
+    char data[] = "Hello World";
+    word32 dataSz, outSz, certDerSz, keyDerSz;
+    PKCS7 msg;
+    RNG rng;
+
+    byte transIdOid[] =
+               { 0x06, 0x0a, 0x60, 0x86, 0x48, 0x01, 0x86, 0xF8, 0x45, 0x01,
+                 0x09, 0x07 };
+    byte messageTypeOid[] =
+               { 0x06, 0x0a, 0x60, 0x86, 0x48, 0x01, 0x86, 0xF8, 0x45, 0x01,
+                 0x09, 0x02 };
+    byte senderNonceOid[] =
+               { 0x06, 0x0a, 0x60, 0x86, 0x48, 0x01, 0x86, 0xF8, 0x45, 0x01,
+                 0x09, 0x05 };
+    byte transId[(SHA_DIGEST_SIZE + 1) * 2 + 1];
+    byte messageType[] = { 0x13, 2, '1', '9' };
+    byte senderNonce[PKCS7_NONCE_SZ + 2];
+
+    PKCS7Attrib attribs[] =
+    {
+        { transIdOid, sizeof(transIdOid),
+                     transId, sizeof(transId) - 1 }, /* take off the null */
+        { messageTypeOid, sizeof(messageTypeOid),
+                     messageType, sizeof(messageType) },
+        { senderNonceOid, sizeof(senderNonceOid),
+                     senderNonce, sizeof(senderNonce) }
+    };
+
+    dataSz = (word32) strlen(data);
+    outSz = FOURK_BUF;
+
+    certDer = (byte*)malloc(FOURK_BUF);
+    if (certDer == NULL)
+        return -207;
+    keyDer = (byte*)malloc(FOURK_BUF);
+    if (keyDer == NULL) {
+        free(certDer);
+        return -208;
+    }
+    out = (byte*)malloc(FOURK_BUF);
+    if (out == NULL) {
+        free(certDer);
+        free(keyDer);
+        return -209;
+    }
+
+    /* read in DER cert of recipient, into cert of size certSz */
+    file = fopen(clientCert, "rb");
+    if (!file) {
+        free(certDer);
+        free(keyDer);
+        free(out);
+        err_sys("can't open ./certs/client-cert.der, "
+                "Please run from wolfSSL home dir", -44);
+        return -44;
+    }
+    certDerSz = (word32)fread(certDer, 1, FOURK_BUF, file);
+    fclose(file);
+
+    file = fopen(clientKey, "rb");
+    if (!file) {
+        free(certDer);
+        free(keyDer);
+        free(out);
+        err_sys("can't open ./certs/client-key.der, "
+                "Please run from wolfSSL home dir", -45);
+        return -45;
+    }
+    keyDerSz = (word32)fread(keyDer, 1, FOURK_BUF, file);
+    fclose(file);
+
+    ret = wc_InitRng(&rng);
+    if (ret != 0) {
+        free(certDer);
+        free(keyDer);
+        free(out);
+        return -210;
+    }
+
+    senderNonce[0] = 0x04;
+    senderNonce[1] = PKCS7_NONCE_SZ;
+
+    ret = wc_RNG_GenerateBlock(&rng, &senderNonce[2], PKCS7_NONCE_SZ);
+    if (ret != 0) {
+        free(certDer);
+        free(keyDer);
+        free(out);
+        return -211;
+    }
+
+    wc_PKCS7_InitWithCert(&msg, certDer, certDerSz);
+    msg.privateKey = keyDer;
+    msg.privateKeySz = keyDerSz;
+    msg.content = (byte*)data;
+    msg.contentSz = dataSz;
+    msg.hashOID = SHAh;
+    msg.encryptOID = RSAk;
+    msg.signedAttribs = attribs;
+    msg.signedAttribsSz = sizeof(attribs)/sizeof(PKCS7Attrib);
+    msg.rng = &rng;
+    {
+        Sha sha;
+        byte digest[SHA_DIGEST_SIZE];
+        int i,j;
+
+        transId[0] = 0x13;
+        transId[1] = SHA_DIGEST_SIZE * 2;
+
+        ret = wc_InitSha(&sha);
+        if (ret != 0) {
+            free(certDer);
+            free(keyDer);
+            free(out);
+            return -4003;
+        }
+        wc_ShaUpdate(&sha, msg.publicKey, msg.publicKeySz);
+        wc_ShaFinal(&sha, digest);
+
+        for (i = 0, j = 2; i < SHA_DIGEST_SIZE; i++, j += 2) {
+            snprintf((char*)&transId[j], 3, "%02x", digest[i]);
+        }
+    }
+    ret = wc_PKCS7_EncodeSignedData(&msg, out, outSz);
+    if (ret < 0) {
+        free(certDer);
+        free(keyDer);
+        free(out);
+        wc_PKCS7_Free(&msg);
+        return -212;
+    }
+    else
+        outSz = ret;
+
+    /* write PKCS#7 to output file for more testing */
+    file = fopen("./pkcs7signedData.der", "wb");
+    if (!file) {
+        free(certDer);
+        free(keyDer);
+        free(out);
+        wc_PKCS7_Free(&msg);
+        return -213;
+    }
+    ret = (int)fwrite(out, 1, outSz, file);
+    fclose(file);
+    if (ret != (int)outSz) {
+        free(certDer);
+        free(keyDer);
+        free(out);
+        wc_PKCS7_Free(&msg);
+        return -218;
+    }
+
+    wc_PKCS7_Free(&msg);
+    wc_PKCS7_InitWithCert(&msg, NULL, 0);
+
+    ret = wc_PKCS7_VerifySignedData(&msg, out, outSz);
+    if (ret < 0) {
+        free(certDer);
+        free(keyDer);
+        free(out);
+        wc_PKCS7_Free(&msg);
+        return -214;
+    }
+
+    if (msg.singleCert == NULL || msg.singleCertSz == 0) {
+        free(certDer);
+        free(keyDer);
+        free(out);
+        wc_PKCS7_Free(&msg);
+        return -215;
+    }
+
+    file = fopen("./pkcs7cert.der", "wb");
+    if (!file) {
+        free(certDer);
+        free(keyDer);
+        free(out);
+        wc_PKCS7_Free(&msg);
+        return -216;
+    }
+    ret = (int)fwrite(msg.singleCert, 1, msg.singleCertSz, file);
+    fclose(file);
+
+    free(certDer);
+    free(keyDer);
+    free(out);
+    wc_PKCS7_Free(&msg);
+
+    wc_FreeRng(&rng);
+
+    if (ret > 0)
+        return 0;
+
+    return ret;
+}
+
+#endif /* HAVE_PKCS7 */
+
+#endif /* NO_CRYPT_TEST */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/test/test.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/test/test.h
new file mode 100644
index 0000000..dbe6e25
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/test/test.h
@@ -0,0 +1,33 @@
+/* ctaocrypt/test/test.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+int wolfcrypt_test(void* args);
+
+#ifdef __cplusplus
+    }  /* extern "C" */
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/test/test.sln b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/test/test.sln
new file mode 100644
index 0000000..97b2e8d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/test/test.sln
@@ -0,0 +1,20 @@
+
+Microsoft Visual Studio Solution File, Format Version 9.00
+# Visual C++ Express 2005
+Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "test", "test.vcproj", "{D04BDF66-664A-4D59-BEAC-8AB2D5809C21}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|Win32 = Debug|Win32
+		Release|Win32 = Release|Win32
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{D04BDF66-664A-4D59-BEAC-8AB2D5809C21}.Debug|Win32.ActiveCfg = Debug|Win32
+		{D04BDF66-664A-4D59-BEAC-8AB2D5809C21}.Debug|Win32.Build.0 = Debug|Win32
+		{D04BDF66-664A-4D59-BEAC-8AB2D5809C21}.Release|Win32.ActiveCfg = Release|Win32
+		{D04BDF66-664A-4D59-BEAC-8AB2D5809C21}.Release|Win32.Build.0 = Release|Win32
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/test/test.vcproj b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/test/test.vcproj
new file mode 100644
index 0000000..38c5c6b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfcrypt/test/test.vcproj
@@ -0,0 +1,195 @@
+
+
+	
+		
+	
+	
+	
+	
+		
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+		
+		
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+			
+		
+	
+	
+	
+	
+		
+		
+		
+		
+		
+			
+			
+		
+	
+	
+	
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/callbacks.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/callbacks.h
new file mode 100644
index 0000000..8794e9e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/callbacks.h
@@ -0,0 +1,80 @@
+/* callbacks.h
+ *
+ * Copyright (C) 2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifndef WOLFSSL_CALLBACKS_H
+#define WOLFSSL_CALLBACKS_H
+
+#include 
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+
+enum { /* CALLBACK CONTSTANTS */
+    MAX_PACKETNAME_SZ     =  24,
+    MAX_CIPHERNAME_SZ     =  24,
+    MAX_TIMEOUT_NAME_SZ   =  24,       
+    MAX_PACKETS_HANDSHAKE =  14,       /* 12 for client auth plus 2 alerts */
+    MAX_VALUE_SZ          = 128,       /* all handshake packets but Cert should
+                                          fit here  */
+};
+
+
+typedef struct handShakeInfo_st {
+    char   cipherName[MAX_CIPHERNAME_SZ + 1];    /* negotiated cipher */
+    char   packetNames[MAX_PACKETS_HANDSHAKE][MAX_PACKETNAME_SZ + 1];
+                                                 /* SSL packet names  */ 
+    int    numberPackets;                        /* actual # of packets */
+    int    negotiationError;                     /* cipher/parameter err */
+} HandShakeInfo;
+
+
+typedef struct timeval Timeval;
+
+
+typedef struct packetInfo_st {
+    char           packetName[MAX_PACKETNAME_SZ + 1]; /* SSL packet name */
+    Timeval        timestamp;                       /* when it occured    */
+    unsigned char  value[MAX_VALUE_SZ];             /* if fits, it's here */ 
+    unsigned char* bufferValue;                     /* otherwise here (non 0) */
+    int            valueSz;                         /* sz of value or buffer */
+} PacketInfo;
+
+
+typedef struct timeoutInfo_st {
+    char       timeoutName[MAX_TIMEOUT_NAME_SZ + 1]; /* timeout Name */
+    int        flags;                              /* for future use */
+    int        numberPackets;                      /* actual # of packets */
+    PacketInfo packets[MAX_PACKETS_HANDSHAKE];     /* list of all packets  */
+    Timeval    timeoutValue;                       /* timer that caused it */
+} TimeoutInfo;
+
+
+
+#ifdef __cplusplus
+    }  /* extern "C" */
+#endif
+
+
+#endif /* WOLFSSL_CALLBACKS_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/certs_test.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/certs_test.h
new file mode 100644
index 0000000..3ce4915
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/certs_test.h
@@ -0,0 +1,1226 @@
+/* certs_test.h */
+
+#ifndef WOLFSSL_CERTS_TEST_H
+#define WOLFSSL_CERTS_TEST_H
+
+#ifdef USE_CERT_BUFFERS_1024
+
+/* ./certs/1024/client-key.der, 1024-bit */
+static const unsigned char client_key_der_1024[] =
+{
+	0x30, 0x82, 0x02, 0x5C, 0x02, 0x01, 0x00, 0x02, 0x81, 0x81, 
+	0x00, 0xBC, 0x73, 0x0E, 0xA8, 0x49, 0xF3, 0x74, 0xA2, 0xA9, 
+	0xEF, 0x18, 0xA5, 0xDA, 0x55, 0x99, 0x21, 0xF9, 0xC8, 0xEC, 
+	0xB3, 0x6D, 0x48, 0xE5, 0x35, 0x35, 0x75, 0x77, 0x37, 0xEC, 
+	0xD1, 0x61, 0x90, 0x5F, 0x3E, 0xD9, 0xE4, 0xD5, 0xDF, 0x94, 
+	0xCA, 0xC1, 0xA9, 0xD7, 0x19, 0xDA, 0x86, 0xC9, 0xE8, 0x4D, 
+	0xC4, 0x61, 0x36, 0x82, 0xFE, 0xAB, 0xAD, 0x7E, 0x77, 0x25, 
+	0xBB, 0x8D, 0x11, 0xA5, 0xBC, 0x62, 0x3A, 0xA8, 0x38, 0xCC, 
+	0x39, 0xA2, 0x04, 0x66, 0xB4, 0xF7, 0xF7, 0xF3, 0xAA, 0xDA, 
+	0x4D, 0x02, 0x0E, 0xBB, 0x5E, 0x8D, 0x69, 0x48, 0xDC, 0x77, 
+	0xC9, 0x28, 0x0E, 0x22, 0xE9, 0x6B, 0xA4, 0x26, 0xBA, 0x4C, 
+	0xE8, 0xC1, 0xFD, 0x4A, 0x6F, 0x2B, 0x1F, 0xEF, 0x8A, 0xAE, 
+	0xF6, 0x90, 0x62, 0xE5, 0x64, 0x1E, 0xEB, 0x2B, 0x3C, 0x67, 
+	0xC8, 0xDC, 0x27, 0x00, 0xF6, 0x91, 0x68, 0x65, 0xA9, 0x02, 
+	0x03, 0x01, 0x00, 0x01, 0x02, 0x81, 0x80, 0x13, 0x97, 0xEA, 
+	0xE8, 0x38, 0x78, 0x25, 0xA2, 0x5C, 0x04, 0xCE, 0x0D, 0x40, 
+	0x7C, 0x31, 0xE5, 0xC4, 0x70, 0xCD, 0x9B, 0x82, 0x3B, 0x58, 
+	0x09, 0x86, 0x3B, 0x66, 0x5F, 0xDC, 0x31, 0x90, 0xF1, 0x4F, 
+	0xD5, 0xDB, 0x15, 0xDD, 0xDE, 0xD7, 0x3B, 0x95, 0x93, 0x31, 
+	0x18, 0x31, 0x0E, 0x5E, 0xA3, 0xD6, 0xA2, 0x1A, 0x71, 0x6E, 
+	0x81, 0x48, 0x1C, 0x4B, 0xCF, 0xDB, 0x8E, 0x7A, 0x86, 0x61, 
+	0x32, 0xDC, 0xFB, 0x55, 0xC1, 0x16, 0x6D, 0x27, 0x92, 0x24, 
+	0x45, 0x8B, 0xF1, 0xB8, 0x48, 0xB1, 0x4B, 0x1D, 0xAC, 0xDE, 
+	0xDA, 0xDD, 0x8E, 0x2F, 0xC2, 0x91, 0xFB, 0xA5, 0xA9, 0x6E, 
+	0xF8, 0x3A, 0x6A, 0xF1, 0xFD, 0x50, 0x18, 0xEF, 0x9F, 0xE7, 
+	0xC3, 0xCA, 0x78, 0xEA, 0x56, 0xD3, 0xD3, 0x72, 0x5B, 0x96, 
+	0xDD, 0x4E, 0x06, 0x4E, 0x3A, 0xC3, 0xD9, 0xBE, 0x72, 0xB6, 
+	0x65, 0x07, 0x07, 0x4C, 0x01, 0x02, 0x41, 0x00, 0xFA, 0x47, 
+	0xD4, 0x7A, 0x7C, 0x92, 0x3C, 0x55, 0xEF, 0x81, 0xF0, 0x41, 
+	0x30, 0x2D, 0xA3, 0xCF, 0x8F, 0x1C, 0xE6, 0x87, 0x27, 0x05, 
+	0x70, 0x0D, 0xDF, 0x98, 0x35, 0xD6, 0xF1, 0x8B, 0x38, 0x2F, 
+	0x24, 0xB5, 0xD0, 0x84, 0xB6, 0x79, 0x4F, 0x71, 0x29, 0x94, 
+	0x5A, 0xF0, 0x64, 0x6A, 0xAC, 0xE7, 0x72, 0xC6, 0xED, 0x4D, 
+	0x59, 0x98, 0x3E, 0x67, 0x3A, 0xF3, 0x74, 0x2C, 0xF9, 0x61, 
+	0x17, 0x69, 0x02, 0x41, 0x00, 0xC0, 0xC1, 0x82, 0x0D, 0x0C, 
+	0xEB, 0xC6, 0x2F, 0xDC, 0x92, 0xF9, 0x9D, 0x82, 0x1A, 0x31, 
+	0xE9, 0xE9, 0xF7, 0x4B, 0xF2, 0x82, 0x87, 0x1C, 0xEE, 0x16, 
+	0x6A, 0xD1, 0x1D, 0x18, 0x82, 0x70, 0xF3, 0xC0, 0xB6, 0x2F, 
+	0xF6, 0xF3, 0xF7, 0x1D, 0xF1, 0x86, 0x23, 0xC8, 0x4E, 0xEB, 
+	0x8F, 0x56, 0x8E, 0x8F, 0xF5, 0xBF, 0xF1, 0xF7, 0x2B, 0xB5, 
+	0xCC, 0x3D, 0xC6, 0x57, 0x39, 0x0C, 0x1B, 0x54, 0x41, 0x02, 
+	0x41, 0x00, 0x9D, 0x7E, 0x05, 0xDE, 0xED, 0xF4, 0xB7, 0xB2, 
+	0xFB, 0xFC, 0x30, 0x4B, 0x55, 0x1D, 0xE3, 0x2F, 0x01, 0x47, 
+	0x96, 0x69, 0x05, 0xCD, 0x0E, 0x2E, 0x2C, 0xBD, 0x83, 0x63, 
+	0xB6, 0xAB, 0x7C, 0xB7, 0x6D, 0xCA, 0x5B, 0x64, 0xA7, 0xCE, 
+	0xBE, 0x86, 0xDF, 0x3B, 0x53, 0xDE, 0x61, 0xD2, 0x1E, 0xEB, 
+	0xA5, 0xF6, 0x37, 0xED, 0xAC, 0xAB, 0x78, 0xD9, 0x4C, 0xE7, 
+	0x55, 0xFB, 0xD7, 0x11, 0x99, 0xC1, 0x02, 0x40, 0x18, 0x98, 
+	0x18, 0x29, 0xE6, 0x1E, 0x27, 0x39, 0x70, 0x21, 0x68, 0xAC, 
+	0x0A, 0x2F, 0xA1, 0x72, 0xC1, 0x21, 0x86, 0x95, 0x38, 0xC6, 
+	0x58, 0x90, 0xA0, 0x57, 0x9C, 0xBA, 0xE3, 0xA7, 0xB1, 0x15, 
+	0xC8, 0xDE, 0xF6, 0x1B, 0xC2, 0x61, 0x23, 0x76, 0xEF, 0xB0, 
+	0x9D, 0x1C, 0x44, 0xBE, 0x13, 0x43, 0x39, 0x67, 0x17, 0xC8, 
+	0x9D, 0xCA, 0xFB, 0xF5, 0x45, 0x64, 0x8B, 0x38, 0x82, 0x2C, 
+	0xF2, 0x81, 0x02, 0x40, 0x39, 0x89, 0xE5, 0x9C, 0x19, 0x55, 
+	0x30, 0xBA, 0xB7, 0x48, 0x8C, 0x48, 0x14, 0x0E, 0xF4, 0x9F, 
+	0x7E, 0x77, 0x97, 0x43, 0xE1, 0xB4, 0x19, 0x35, 0x31, 0x23, 
+	0x75, 0x9C, 0x3B, 0x44, 0xAD, 0x69, 0x12, 0x56, 0xEE, 0x00, 
+	0x61, 0x64, 0x16, 0x66, 0xD3, 0x7C, 0x74, 0x2B, 0x15, 0xB4, 
+	0xA2, 0xFE, 0xBF, 0x08, 0x6B, 0x1A, 0x5D, 0x3F, 0x90, 0x12, 
+	0xB1, 0x05, 0x86, 0x31, 0x29, 0xDB, 0xD9, 0xE2
+};
+static const int sizeof_client_key_der_1024 = sizeof(client_key_der_1024);
+
+/* ./certs/1024/client-cert.der, 1024-bit */
+static const unsigned char client_cert_der_1024[] =
+{
+	0x30, 0x82, 0x03, 0xC5, 0x30, 0x82, 0x03, 0x2E, 0xA0, 0x03, 
+	0x02, 0x01, 0x02, 0x02, 0x09, 0x00, 0xE3, 0xD7, 0xA0, 0xFA, 
+	0x76, 0xDF, 0x2A, 0xFA, 0x30, 0x0D, 0x06, 0x09, 0x2A, 0x86, 
+	0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01, 0x0B, 0x05, 0x00, 0x30, 
+	0x81, 0x9E, 0x31, 0x0B, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 
+	0x06, 0x13, 0x02, 0x55, 0x53, 0x31, 0x10, 0x30, 0x0E, 0x06, 
+	0x03, 0x55, 0x04, 0x08, 0x0C, 0x07, 0x4D, 0x6F, 0x6E, 0x74, 
+	0x61, 0x6E, 0x61, 0x31, 0x10, 0x30, 0x0E, 0x06, 0x03, 0x55, 
+	0x04, 0x07, 0x0C, 0x07, 0x42, 0x6F, 0x7A, 0x65, 0x6D, 0x61, 
+	0x6E, 0x31, 0x15, 0x30, 0x13, 0x06, 0x03, 0x55, 0x04, 0x0A, 
+	0x0C, 0x0C, 0x77, 0x6F, 0x6C, 0x66, 0x53, 0x53, 0x4C, 0x5F, 
+	0x31, 0x30, 0x32, 0x34, 0x31, 0x19, 0x30, 0x17, 0x06, 0x03, 
+	0x55, 0x04, 0x0B, 0x0C, 0x10, 0x50, 0x72, 0x6F, 0x67, 0x72, 
+	0x61, 0x6D, 0x6D, 0x69, 0x6E, 0x67, 0x2D, 0x31, 0x30, 0x32, 
+	0x34, 0x31, 0x18, 0x30, 0x16, 0x06, 0x03, 0x55, 0x04, 0x03, 
+	0x0C, 0x0F, 0x77, 0x77, 0x77, 0x2E, 0x77, 0x6F, 0x6C, 0x66, 
+	0x73, 0x73, 0x6C, 0x2E, 0x63, 0x6F, 0x6D, 0x31, 0x1F, 0x30, 
+	0x1D, 0x06, 0x09, 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 
+	0x09, 0x01, 0x16, 0x10, 0x69, 0x6E, 0x66, 0x6F, 0x40, 0x77, 
+	0x6F, 0x6C, 0x66, 0x73, 0x73, 0x6C, 0x2E, 0x63, 0x6F, 0x6D, 
+	0x30, 0x1E, 0x17, 0x0D, 0x31, 0x35, 0x30, 0x35, 0x30, 0x37, 
+	0x31, 0x38, 0x32, 0x31, 0x30, 0x31, 0x5A, 0x17, 0x0D, 0x31, 
+	0x38, 0x30, 0x31, 0x33, 0x31, 0x31, 0x38, 0x32, 0x31, 0x30, 
+	0x31, 0x5A, 0x30, 0x81, 0x9E, 0x31, 0x0B, 0x30, 0x09, 0x06, 
+	0x03, 0x55, 0x04, 0x06, 0x13, 0x02, 0x55, 0x53, 0x31, 0x10, 
+	0x30, 0x0E, 0x06, 0x03, 0x55, 0x04, 0x08, 0x0C, 0x07, 0x4D, 
+	0x6F, 0x6E, 0x74, 0x61, 0x6E, 0x61, 0x31, 0x10, 0x30, 0x0E, 
+	0x06, 0x03, 0x55, 0x04, 0x07, 0x0C, 0x07, 0x42, 0x6F, 0x7A, 
+	0x65, 0x6D, 0x61, 0x6E, 0x31, 0x15, 0x30, 0x13, 0x06, 0x03, 
+	0x55, 0x04, 0x0A, 0x0C, 0x0C, 0x77, 0x6F, 0x6C, 0x66, 0x53, 
+	0x53, 0x4C, 0x5F, 0x31, 0x30, 0x32, 0x34, 0x31, 0x19, 0x30, 
+	0x17, 0x06, 0x03, 0x55, 0x04, 0x0B, 0x0C, 0x10, 0x50, 0x72, 
+	0x6F, 0x67, 0x72, 0x61, 0x6D, 0x6D, 0x69, 0x6E, 0x67, 0x2D, 
+	0x31, 0x30, 0x32, 0x34, 0x31, 0x18, 0x30, 0x16, 0x06, 0x03, 
+	0x55, 0x04, 0x03, 0x0C, 0x0F, 0x77, 0x77, 0x77, 0x2E, 0x77, 
+	0x6F, 0x6C, 0x66, 0x73, 0x73, 0x6C, 0x2E, 0x63, 0x6F, 0x6D, 
+	0x31, 0x1F, 0x30, 0x1D, 0x06, 0x09, 0x2A, 0x86, 0x48, 0x86, 
+	0xF7, 0x0D, 0x01, 0x09, 0x01, 0x16, 0x10, 0x69, 0x6E, 0x66, 
+	0x6F, 0x40, 0x77, 0x6F, 0x6C, 0x66, 0x73, 0x73, 0x6C, 0x2E, 
+	0x63, 0x6F, 0x6D, 0x30, 0x81, 0x9F, 0x30, 0x0D, 0x06, 0x09, 
+	0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01, 0x01, 0x05, 
+	0x00, 0x03, 0x81, 0x8D, 0x00, 0x30, 0x81, 0x89, 0x02, 0x81, 
+	0x81, 0x00, 0xBC, 0x73, 0x0E, 0xA8, 0x49, 0xF3, 0x74, 0xA2, 
+	0xA9, 0xEF, 0x18, 0xA5, 0xDA, 0x55, 0x99, 0x21, 0xF9, 0xC8, 
+	0xEC, 0xB3, 0x6D, 0x48, 0xE5, 0x35, 0x35, 0x75, 0x77, 0x37, 
+	0xEC, 0xD1, 0x61, 0x90, 0x5F, 0x3E, 0xD9, 0xE4, 0xD5, 0xDF, 
+	0x94, 0xCA, 0xC1, 0xA9, 0xD7, 0x19, 0xDA, 0x86, 0xC9, 0xE8, 
+	0x4D, 0xC4, 0x61, 0x36, 0x82, 0xFE, 0xAB, 0xAD, 0x7E, 0x77, 
+	0x25, 0xBB, 0x8D, 0x11, 0xA5, 0xBC, 0x62, 0x3A, 0xA8, 0x38, 
+	0xCC, 0x39, 0xA2, 0x04, 0x66, 0xB4, 0xF7, 0xF7, 0xF3, 0xAA, 
+	0xDA, 0x4D, 0x02, 0x0E, 0xBB, 0x5E, 0x8D, 0x69, 0x48, 0xDC, 
+	0x77, 0xC9, 0x28, 0x0E, 0x22, 0xE9, 0x6B, 0xA4, 0x26, 0xBA, 
+	0x4C, 0xE8, 0xC1, 0xFD, 0x4A, 0x6F, 0x2B, 0x1F, 0xEF, 0x8A, 
+	0xAE, 0xF6, 0x90, 0x62, 0xE5, 0x64, 0x1E, 0xEB, 0x2B, 0x3C, 
+	0x67, 0xC8, 0xDC, 0x27, 0x00, 0xF6, 0x91, 0x68, 0x65, 0xA9, 
+	0x02, 0x03, 0x01, 0x00, 0x01, 0xA3, 0x82, 0x01, 0x07, 0x30, 
+	0x82, 0x01, 0x03, 0x30, 0x1D, 0x06, 0x03, 0x55, 0x1D, 0x0E, 
+	0x04, 0x16, 0x04, 0x14, 0x81, 0x69, 0x0F, 0xF8, 0xDF, 0xDD, 
+	0xCF, 0x34, 0x29, 0xD5, 0x67, 0x75, 0x71, 0x85, 0xC7, 0x75, 
+	0x10, 0x69, 0x59, 0xEC, 0x30, 0x81, 0xD3, 0x06, 0x03, 0x55, 
+	0x1D, 0x23, 0x04, 0x81, 0xCB, 0x30, 0x81, 0xC8, 0x80, 0x14, 
+	0x81, 0x69, 0x0F, 0xF8, 0xDF, 0xDD, 0xCF, 0x34, 0x29, 0xD5, 
+	0x67, 0x75, 0x71, 0x85, 0xC7, 0x75, 0x10, 0x69, 0x59, 0xEC, 
+	0xA1, 0x81, 0xA4, 0xA4, 0x81, 0xA1, 0x30, 0x81, 0x9E, 0x31, 
+	0x0B, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x06, 0x13, 0x02, 
+	0x55, 0x53, 0x31, 0x10, 0x30, 0x0E, 0x06, 0x03, 0x55, 0x04, 
+	0x08, 0x0C, 0x07, 0x4D, 0x6F, 0x6E, 0x74, 0x61, 0x6E, 0x61, 
+	0x31, 0x10, 0x30, 0x0E, 0x06, 0x03, 0x55, 0x04, 0x07, 0x0C, 
+	0x07, 0x42, 0x6F, 0x7A, 0x65, 0x6D, 0x61, 0x6E, 0x31, 0x15, 
+	0x30, 0x13, 0x06, 0x03, 0x55, 0x04, 0x0A, 0x0C, 0x0C, 0x77, 
+	0x6F, 0x6C, 0x66, 0x53, 0x53, 0x4C, 0x5F, 0x31, 0x30, 0x32, 
+	0x34, 0x31, 0x19, 0x30, 0x17, 0x06, 0x03, 0x55, 0x04, 0x0B, 
+	0x0C, 0x10, 0x50, 0x72, 0x6F, 0x67, 0x72, 0x61, 0x6D, 0x6D, 
+	0x69, 0x6E, 0x67, 0x2D, 0x31, 0x30, 0x32, 0x34, 0x31, 0x18, 
+	0x30, 0x16, 0x06, 0x03, 0x55, 0x04, 0x03, 0x0C, 0x0F, 0x77, 
+	0x77, 0x77, 0x2E, 0x77, 0x6F, 0x6C, 0x66, 0x73, 0x73, 0x6C, 
+	0x2E, 0x63, 0x6F, 0x6D, 0x31, 0x1F, 0x30, 0x1D, 0x06, 0x09, 
+	0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x09, 0x01, 0x16, 
+	0x10, 0x69, 0x6E, 0x66, 0x6F, 0x40, 0x77, 0x6F, 0x6C, 0x66, 
+	0x73, 0x73, 0x6C, 0x2E, 0x63, 0x6F, 0x6D, 0x82, 0x09, 0x00, 
+	0xE3, 0xD7, 0xA0, 0xFA, 0x76, 0xDF, 0x2A, 0xFA, 0x30, 0x0C, 
+	0x06, 0x03, 0x55, 0x1D, 0x13, 0x04, 0x05, 0x30, 0x03, 0x01, 
+	0x01, 0xFF, 0x30, 0x0D, 0x06, 0x09, 0x2A, 0x86, 0x48, 0x86, 
+	0xF7, 0x0D, 0x01, 0x01, 0x0B, 0x05, 0x00, 0x03, 0x81, 0x81, 
+	0x00, 0x1D, 0xB7, 0xD5, 0x7C, 0xE1, 0xB1, 0xD8, 0xC0, 0x67, 
+	0x5D, 0xB5, 0xD3, 0x88, 0xE7, 0x50, 0x29, 0x71, 0x63, 0x8F, 
+	0xCC, 0x26, 0x1F, 0x33, 0x09, 0x55, 0x43, 0x9B, 0xAB, 0xC6, 
+	0x1B, 0xBC, 0xC7, 0x01, 0x95, 0x1A, 0xFA, 0x65, 0xE0, 0xFD, 
+	0x9C, 0xEB, 0x6F, 0x0A, 0x0F, 0x14, 0xEC, 0xB5, 0x2F, 0xDC, 
+	0x1C, 0x30, 0xDD, 0x52, 0x97, 0xD4, 0x1C, 0x09, 0x00, 0x33, 
+	0x38, 0x5F, 0xCB, 0xA8, 0x16, 0x8F, 0x11, 0xB7, 0xB8, 0xD0, 
+	0x66, 0xE1, 0x54, 0x28, 0xF3, 0x3F, 0xBF, 0x6A, 0x6F, 0x76, 
+	0x48, 0x2A, 0x5E, 0x56, 0xA7, 0xCE, 0x1C, 0xF0, 0x04, 0xDD, 
+	0x17, 0xBD, 0x06, 0x78, 0x21, 0x6D, 0xD6, 0xB1, 0x9B, 0x75, 
+	0x31, 0x92, 0xC1, 0xFE, 0xD4, 0x8D, 0xD4, 0x67, 0x2F, 0x03, 
+	0x1B, 0x27, 0x8D, 0xAB, 0xFF, 0x30, 0x3B, 0xC3, 0x7F, 0x23, 
+	0xE4, 0xAB, 0x5B, 0x91, 0xE1, 0x1B, 0x66, 0xE6, 0xED
+};
+static const int sizeof_client_cert_der_1024 = sizeof(client_cert_der_1024);
+
+/* ./certs/1024/dh1024.der, 1024-bit */
+static const unsigned char dh_key_der_1024[] =
+{
+	0x30, 0x81, 0x87, 0x02, 0x81, 0x81, 0x00, 0xA4, 0xD2, 0xB8, 
+	0x6E, 0x78, 0xF5, 0xD9, 0xED, 0x2D, 0x7C, 0xDD, 0xB6, 0x16, 
+	0x86, 0x5A, 0x4B, 0x05, 0x76, 0x90, 0xDD, 0x66, 0x61, 0xB9, 
+	0x6D, 0x52, 0xA7, 0x1C, 0xAF, 0x62, 0xC6, 0x69, 0x47, 0x7B, 
+	0x39, 0xF2, 0xFB, 0x94, 0xEC, 0xBC, 0x79, 0xFF, 0x24, 0x5E, 
+	0xEF, 0x79, 0xBB, 0x59, 0xB2, 0xFC, 0xCA, 0x07, 0xD6, 0xF4, 
+	0xE9, 0x34, 0xF7, 0xE8, 0x38, 0xE7, 0xD7, 0x33, 0x44, 0x1D, 
+	0xA3, 0x64, 0x76, 0x1A, 0x84, 0x97, 0x54, 0x74, 0x40, 0x84, 
+	0x1F, 0x15, 0xFE, 0x7C, 0x25, 0x2A, 0x2B, 0x25, 0xFD, 0x9E, 
+	0xC1, 0x89, 0x33, 0x8C, 0x39, 0x25, 0x2B, 0x40, 0xE6, 0xCD, 
+	0xF8, 0xA8, 0xA1, 0x8A, 0x53, 0xC6, 0x47, 0xB2, 0xA0, 0xD7, 
+	0x8F, 0xEB, 0x2E, 0x60, 0x0A, 0x0D, 0x4B, 0xF8, 0xB4, 0x94, 
+	0x8C, 0x63, 0x0A, 0xAD, 0xC7, 0x10, 0xEA, 0xC7, 0xA1, 0xB9, 
+	0x9D, 0xF2, 0xA8, 0x37, 0x73, 0x02, 0x01, 0x02
+};
+static const int sizeof_dh_key_der_1024 = sizeof(dh_key_der_1024);
+
+/* ./certs/1024/dsa1024.der, 1024-bit */
+static const unsigned char dsa_key_der_1024[] =
+{
+	0x30, 0x82, 0x01, 0xBC, 0x02, 0x01, 0x00, 0x02, 0x81, 0x81, 
+	0x00, 0xF7, 0x4B, 0xF9, 0xBB, 0x15, 0x98, 0xEB, 0xDD, 0xDE, 
+	0x1E, 0x4E, 0x71, 0x88, 0x85, 0xF2, 0xB7, 0xBA, 0xE2, 0x4A, 
+	0xDA, 0x76, 0x40, 0xCD, 0x69, 0x48, 0x9E, 0x83, 0x7C, 0x11, 
+	0xF7, 0x65, 0x31, 0x78, 0xF5, 0x25, 0x2D, 0xF7, 0xB7, 0xF8, 
+	0x52, 0x3F, 0xBE, 0xD8, 0xB6, 0xC5, 0xFE, 0x18, 0x15, 0x5B, 
+	0xB9, 0xD5, 0x92, 0x86, 0xBC, 0xB2, 0x17, 0x7C, 0xD8, 0xB0, 
+	0xBE, 0xA0, 0x7C, 0xF2, 0xD5, 0x73, 0x7A, 0x58, 0x8F, 0x8D, 
+	0xE5, 0x4A, 0x00, 0x99, 0x83, 0x4A, 0xC0, 0x9E, 0x16, 0x09, 
+	0xA1, 0x10, 0x34, 0xD5, 0x19, 0xBB, 0x63, 0xE3, 0xDD, 0x83, 
+	0x74, 0x7F, 0x10, 0xCA, 0x73, 0x75, 0xEE, 0x31, 0x4A, 0xDD, 
+	0x9F, 0xE0, 0x02, 0x6A, 0x9D, 0xEE, 0xB2, 0x4B, 0xA7, 0x6B, 
+	0x2A, 0x6C, 0xC7, 0x86, 0x77, 0xE8, 0x04, 0x15, 0xDC, 0x92, 
+	0xB4, 0x7A, 0x29, 0x1F, 0x4E, 0x83, 0x63, 0x85, 0x55, 0x02, 
+	0x15, 0x00, 0xD2, 0x05, 0xE4, 0x73, 0xFB, 0xC1, 0x99, 0xC5, 
+	0xDC, 0x68, 0xA4, 0x8D, 0x92, 0x27, 0x3D, 0xE2, 0x52, 0x5F, 
+	0x89, 0x8B, 0x02, 0x81, 0x81, 0x00, 0xAA, 0x21, 0x02, 0x09, 
+	0x43, 0x6E, 0xFB, 0xA2, 0x54, 0x14, 0x85, 0x0A, 0xF4, 0x28, 
+	0x7C, 0xCB, 0xCC, 0xDB, 0xF5, 0x1E, 0xA2, 0x18, 0xA9, 0x21, 
+	0xDE, 0x88, 0x88, 0x33, 0x8C, 0x2E, 0xEB, 0x8D, 0xA3, 0xF0, 
+	0x1D, 0xC8, 0x8F, 0xF6, 0x7E, 0xF8, 0xCF, 0x12, 0xF5, 0xB4, 
+	0xA1, 0x11, 0x6F, 0x0C, 0xD4, 0xF0, 0x06, 0xAD, 0xC4, 0xFC, 
+	0x14, 0x45, 0xC7, 0x94, 0x15, 0xBC, 0x19, 0x4B, 0xAE, 0xEF, 
+	0x93, 0x6A, 0x4F, 0xCC, 0x14, 0xD8, 0x47, 0x8B, 0x39, 0x66, 
+	0x87, 0x02, 0xD4, 0x28, 0x0A, 0xB8, 0xEE, 0x09, 0x37, 0xF4, 
+	0x00, 0xA0, 0x04, 0xA7, 0x79, 0xA7, 0xD2, 0x3C, 0xF7, 0x34, 
+	0x43, 0x56, 0x8E, 0xD0, 0x7C, 0xC2, 0xD8, 0x4D, 0x0F, 0x89, 
+	0xED, 0x14, 0xC1, 0x2C, 0x9C, 0x4C, 0x19, 0x9B, 0x9E, 0xDC, 
+	0x53, 0x09, 0x9F, 0xDF, 0x2D, 0xF0, 0x0C, 0x27, 0x54, 0x3A, 
+	0x77, 0x14, 0x2D, 0xDE, 0x02, 0x81, 0x81, 0x00, 0xE8, 0x1F, 
+	0x7C, 0xB7, 0xC0, 0x54, 0x51, 0xA7, 0x28, 0x2D, 0x58, 0x7C, 
+	0xDE, 0xD4, 0x5C, 0xDD, 0xD5, 0x76, 0x84, 0x3C, 0x36, 0x20, 
+	0xC0, 0xC3, 0x25, 0xD7, 0x3A, 0x38, 0xE1, 0x54, 0xC8, 0xFD, 
+	0x40, 0x68, 0x1A, 0x21, 0x54, 0x26, 0x39, 0x14, 0xBF, 0xF6, 
+	0xA3, 0x9C, 0x5E, 0xD9, 0x2B, 0xF7, 0xC9, 0x25, 0xBA, 0x00, 
+	0x09, 0xCB, 0x7F, 0x0C, 0x4A, 0x24, 0xFD, 0x15, 0x16, 0x15, 
+	0x48, 0xCD, 0x0B, 0x52, 0x44, 0x40, 0x7B, 0x90, 0x63, 0x2B, 
+	0x90, 0x22, 0xC5, 0x18, 0x05, 0x80, 0x53, 0xAF, 0x83, 0x1F, 
+	0x54, 0xE2, 0xB0, 0xA2, 0x0B, 0x5A, 0x92, 0x24, 0xE1, 0x62, 
+	0x28, 0x3F, 0xB7, 0xCA, 0xB9, 0x89, 0xD6, 0xA0, 0xB7, 0xAD, 
+	0xAE, 0x05, 0xE1, 0xC1, 0x59, 0x40, 0xED, 0x4A, 0x1B, 0x68, 
+	0xA7, 0x7B, 0xFB, 0xC3, 0x20, 0x81, 0xEF, 0x4B, 0xF3, 0x69, 
+	0x91, 0xB0, 0xCE, 0x3A, 0xB0, 0x38, 0x02, 0x14, 0x25, 0x38, 
+	0x3B, 0xA1, 0x19, 0x75, 0xDF, 0x9B, 0xF5, 0x72, 0x53, 0x4F, 
+	0x39, 0xE1, 0x1C, 0xEC, 0x13, 0x84, 0x82, 0x18
+};
+static const int sizeof_dsa_key_der_1024 = sizeof(dsa_key_der_1024);
+
+/* ./certs/1024/rsa1024.der, 1024-bit */
+static const unsigned char rsa_key_der_1024[] =
+{
+	0x30, 0x82, 0x02, 0x5D, 0x02, 0x01, 0x00, 0x02, 0x81, 0x81, 
+	0x00, 0xBE, 0x70, 0x70, 0xB8, 0x04, 0x18, 0xE5, 0x28, 0xFE, 
+	0x66, 0xD8, 0x90, 0x88, 0xE0, 0xF1, 0xB7, 0xC3, 0xD0, 0xD2, 
+	0x3E, 0xE6, 0x4B, 0x94, 0x74, 0xB0, 0xFF, 0xB0, 0xF7, 0x63, 
+	0xA5, 0xAB, 0x7E, 0xAF, 0xB6, 0x2B, 0xB7, 0x38, 0x16, 0x1A, 
+	0x50, 0xBF, 0xF1, 0xCA, 0x87, 0x3A, 0xD5, 0xB0, 0xDA, 0xF8, 
+	0x43, 0x7A, 0x15, 0xB9, 0x7E, 0xEA, 0x2A, 0x80, 0xD2, 0x51, 
+	0xB0, 0x35, 0xAF, 0x07, 0xF3, 0xF2, 0x5D, 0x24, 0x3A, 0x4B, 
+	0x87, 0x56, 0x48, 0x1B, 0x3C, 0x24, 0x9A, 0xDA, 0x70, 0x80, 
+	0xBD, 0x3C, 0x8B, 0x03, 0x4A, 0x0C, 0x83, 0x71, 0xDE, 0xE3, 
+	0x03, 0x70, 0xA2, 0xB7, 0x60, 0x09, 0x1B, 0x5E, 0xC7, 0x3D, 
+	0xA0, 0x64, 0x60, 0xE3, 0xA9, 0x06, 0x8D, 0xD3, 0xFF, 0x42, 
+	0xBB, 0x0A, 0x94, 0x27, 0x2D, 0x57, 0x42, 0x0D, 0xB0, 0x2D, 
+	0xE0, 0xBA, 0x18, 0x25, 0x60, 0x92, 0x11, 0x92, 0xF3, 0x02, 
+	0x03, 0x01, 0x00, 0x01, 0x02, 0x81, 0x80, 0x0E, 0xEE, 0x1D, 
+	0xC8, 0x2F, 0x7A, 0x0C, 0x2D, 0x44, 0x94, 0xA7, 0x91, 0xDD, 
+	0x49, 0x55, 0x6A, 0x04, 0xCE, 0x10, 0x4D, 0xA2, 0x1C, 0x76, 
+	0xCD, 0x17, 0x3B, 0x54, 0x92, 0x70, 0x9B, 0x82, 0x70, 0x72, 
+	0x32, 0x24, 0x07, 0x3F, 0x3C, 0x6C, 0x5F, 0xBC, 0x4C, 0xA6, 
+	0x86, 0x27, 0x94, 0xAD, 0x42, 0xDD, 0x87, 0xDC, 0xC0, 0x6B, 
+	0x44, 0x89, 0xF3, 0x3F, 0x1A, 0x3E, 0x11, 0x44, 0x84, 0x2E, 
+	0x69, 0x4C, 0xBB, 0x4A, 0x71, 0x1A, 0xBB, 0x9A, 0x52, 0x3C, 
+	0x6B, 0xDE, 0xBC, 0xB2, 0x7C, 0x51, 0xEF, 0x4F, 0x8F, 0x3A, 
+	0xDC, 0x50, 0x04, 0x4E, 0xB6, 0x31, 0x66, 0xA8, 0x8E, 0x06, 
+	0x3B, 0x51, 0xA9, 0xC1, 0x8A, 0xCB, 0xC4, 0x81, 0xCA, 0x2D, 
+	0x69, 0xEC, 0x88, 0xFC, 0x33, 0x88, 0xD1, 0xD4, 0x29, 0x47, 
+	0x87, 0x37, 0xF9, 0x6A, 0x22, 0x69, 0xB9, 0xC9, 0xFE, 0xEB, 
+	0x8C, 0xC5, 0x21, 0x41, 0x71, 0x02, 0x41, 0x00, 0xFD, 0x17, 
+	0x98, 0x42, 0x54, 0x1C, 0x23, 0xF8, 0xD7, 0x5D, 0xEF, 0x49, 
+	0x4F, 0xAF, 0xD9, 0x35, 0x6F, 0x08, 0xC6, 0xC7, 0x40, 0x5C, 
+	0x7E, 0x58, 0x86, 0xC2, 0xB2, 0x16, 0x39, 0x24, 0xC5, 0x06, 
+	0xB0, 0x3D, 0xAF, 0x02, 0xD2, 0x87, 0x77, 0xD2, 0x76, 0xBA, 
+	0xE3, 0x59, 0x60, 0x42, 0xF1, 0x16, 0xEF, 0x33, 0x0B, 0xF2, 
+	0x0B, 0xBA, 0x99, 0xCC, 0xB6, 0x4C, 0x46, 0x3F, 0x33, 0xE4, 
+	0xD4, 0x67, 0x02, 0x41, 0x00, 0xC0, 0xA0, 0x91, 0x6D, 0xFE, 
+	0x28, 0xE0, 0x81, 0x5A, 0x15, 0xA7, 0xC9, 0xA8, 0x98, 0xC6, 
+	0x0A, 0xAB, 0x00, 0xC5, 0x40, 0xC9, 0x21, 0xBB, 0xB2, 0x33, 
+	0x5A, 0xA7, 0xCB, 0x6E, 0xB8, 0x08, 0x56, 0x4A, 0x76, 0x28, 
+	0xE8, 0x6D, 0xBD, 0xF5, 0x26, 0x7B, 0xBF, 0xC5, 0x46, 0x45, 
+	0x0D, 0xEC, 0x7D, 0xEE, 0x82, 0xD6, 0xCA, 0x5F, 0x3D, 0x6E, 
+	0xCC, 0x94, 0x73, 0xCD, 0xCE, 0x86, 0x6E, 0x95, 0x95, 0x02, 
+	0x40, 0x38, 0xFD, 0x28, 0x1E, 0xBF, 0x5B, 0xBA, 0xC9, 0xDC, 
+	0x8C, 0xDD, 0x45, 0xAF, 0xB8, 0xD3, 0xFB, 0x11, 0x2E, 0x73, 
+	0xBC, 0x08, 0x05, 0x0B, 0xBA, 0x19, 0x56, 0x1B, 0xCD, 0x9F, 
+	0x3E, 0x65, 0x53, 0x15, 0x3A, 0x3E, 0x7F, 0x2F, 0x32, 0xAB, 
+	0xCB, 0x6B, 0x4A, 0xB7, 0xC8, 0xB7, 0x41, 0x3B, 0x92, 0x43, 
+	0x78, 0x46, 0x17, 0x51, 0x86, 0xC9, 0xFC, 0xEB, 0x8B, 0x8F, 
+	0x41, 0xCA, 0x08, 0x9B, 0xBF, 0x02, 0x41, 0x00, 0xAD, 0x9B, 
+	0x89, 0xB6, 0xF2, 0x8C, 0x70, 0xDA, 0xE4, 0x10, 0x04, 0x6B, 
+	0x11, 0x92, 0xAF, 0x5A, 0xCA, 0x08, 0x25, 0xBF, 0x60, 0x07, 
+	0x11, 0x1D, 0x68, 0x7F, 0x5A, 0x1F, 0x55, 0x28, 0x74, 0x0B, 
+	0x21, 0x8D, 0x21, 0x0D, 0x6A, 0x6A, 0xFB, 0xD9, 0xB5, 0x4A, 
+	0x7F, 0x47, 0xF7, 0xD0, 0xB6, 0xC6, 0x41, 0x02, 0x97, 0x07, 
+	0x49, 0x93, 0x1A, 0x9B, 0x33, 0x68, 0xB3, 0xA2, 0x61, 0x32, 
+	0xA5, 0x89, 0x02, 0x41, 0x00, 0x8F, 0xEF, 0xAD, 0xB5, 0xB0, 
+	0xB0, 0x7E, 0x86, 0x03, 0x43, 0x93, 0x6E, 0xDD, 0x3C, 0x2D, 
+	0x9B, 0x6A, 0x55, 0xFF, 0x6F, 0x3E, 0x70, 0x2A, 0xD4, 0xBF, 
+	0x1F, 0x8C, 0x93, 0x60, 0x9E, 0x6D, 0x2F, 0x18, 0x6C, 0x11, 
+	0x36, 0x98, 0x3F, 0x10, 0x78, 0xE8, 0x3E, 0x8F, 0xFE, 0x55, 
+	0xB9, 0x9E, 0xD5, 0x5B, 0x2E, 0x87, 0x1C, 0x58, 0xD0, 0x37, 
+	0x89, 0x96, 0xEC, 0x48, 0x54, 0xF5, 0x9F, 0x0F, 0xB3
+};
+static const int sizeof_rsa_key_der_1024 = sizeof(rsa_key_der_1024);
+
+#elif defined(USE_CERT_BUFFERS_2048)
+
+/* ./certs/client-key.der, 2048-bit */
+static const unsigned char client_key_der_2048[] =
+{
+	0x30, 0x82, 0x04, 0xA4, 0x02, 0x01, 0x00, 0x02, 0x82, 0x01, 
+	0x01, 0x00, 0xC3, 0x03, 0xD1, 0x2B, 0xFE, 0x39, 0xA4, 0x32, 
+	0x45, 0x3B, 0x53, 0xC8, 0x84, 0x2B, 0x2A, 0x7C, 0x74, 0x9A, 
+	0xBD, 0xAA, 0x2A, 0x52, 0x07, 0x47, 0xD6, 0xA6, 0x36, 0xB2, 
+	0x07, 0x32, 0x8E, 0xD0, 0xBA, 0x69, 0x7B, 0xC6, 0xC3, 0x44, 
+	0x9E, 0xD4, 0x81, 0x48, 0xFD, 0x2D, 0x68, 0xA2, 0x8B, 0x67, 
+	0xBB, 0xA1, 0x75, 0xC8, 0x36, 0x2C, 0x4A, 0xD2, 0x1B, 0xF7, 
+	0x8B, 0xBA, 0xCF, 0x0D, 0xF9, 0xEF, 0xEC, 0xF1, 0x81, 0x1E, 
+	0x7B, 0x9B, 0x03, 0x47, 0x9A, 0xBF, 0x65, 0xCC, 0x7F, 0x65, 
+	0x24, 0x69, 0xA6, 0xE8, 0x14, 0x89, 0x5B, 0xE4, 0x34, 0xF7, 
+	0xC5, 0xB0, 0x14, 0x93, 0xF5, 0x67, 0x7B, 0x3A, 0x7A, 0x78, 
+	0xE1, 0x01, 0x56, 0x56, 0x91, 0xA6, 0x13, 0x42, 0x8D, 0xD2, 
+	0x3C, 0x40, 0x9C, 0x4C, 0xEF, 0xD1, 0x86, 0xDF, 0x37, 0x51, 
+	0x1B, 0x0C, 0xA1, 0x3B, 0xF5, 0xF1, 0xA3, 0x4A, 0x35, 0xE4, 
+	0xE1, 0xCE, 0x96, 0xDF, 0x1B, 0x7E, 0xBF, 0x4E, 0x97, 0xD0, 
+	0x10, 0xE8, 0xA8, 0x08, 0x30, 0x81, 0xAF, 0x20, 0x0B, 0x43, 
+	0x14, 0xC5, 0x74, 0x67, 0xB4, 0x32, 0x82, 0x6F, 0x8D, 0x86, 
+	0xC2, 0x88, 0x40, 0x99, 0x36, 0x83, 0xBA, 0x1E, 0x40, 0x72, 
+	0x22, 0x17, 0xD7, 0x52, 0x65, 0x24, 0x73, 0xB0, 0xCE, 0xEF, 
+	0x19, 0xCD, 0xAE, 0xFF, 0x78, 0x6C, 0x7B, 0xC0, 0x12, 0x03, 
+	0xD4, 0x4E, 0x72, 0x0D, 0x50, 0x6D, 0x3B, 0xA3, 0x3B, 0xA3, 
+	0x99, 0x5E, 0x9D, 0xC8, 0xD9, 0x0C, 0x85, 0xB3, 0xD9, 0x8A, 
+	0xD9, 0x54, 0x26, 0xDB, 0x6D, 0xFA, 0xAC, 0xBB, 0xFF, 0x25, 
+	0x4C, 0xC4, 0xD1, 0x79, 0xF4, 0x71, 0xD3, 0x86, 0x40, 0x18, 
+	0x13, 0xB0, 0x63, 0xB5, 0x72, 0x4E, 0x30, 0xC4, 0x97, 0x84, 
+	0x86, 0x2D, 0x56, 0x2F, 0xD7, 0x15, 0xF7, 0x7F, 0xC0, 0xAE, 
+	0xF5, 0xFC, 0x5B, 0xE5, 0xFB, 0xA1, 0xBA, 0xD3, 0x02, 0x03, 
+	0x01, 0x00, 0x01, 0x02, 0x82, 0x01, 0x01, 0x00, 0xA2, 0xE6, 
+	0xD8, 0x5F, 0x10, 0x71, 0x64, 0x08, 0x9E, 0x2E, 0x6D, 0xD1, 
+	0x6D, 0x1E, 0x85, 0xD2, 0x0A, 0xB1, 0x8C, 0x47, 0xCE, 0x2C, 
+	0x51, 0x6A, 0xA0, 0x12, 0x9E, 0x53, 0xDE, 0x91, 0x4C, 0x1D, 
+	0x6D, 0xEA, 0x59, 0x7B, 0xF2, 0x77, 0xAA, 0xD9, 0xC6, 0xD9, 
+	0x8A, 0xAB, 0xD8, 0xE1, 0x16, 0xE4, 0x63, 0x26, 0xFF, 0xB5, 
+	0x6C, 0x13, 0x59, 0xB8, 0xE3, 0xA5, 0xC8, 0x72, 0x17, 0x2E, 
+	0x0C, 0x9F, 0x6F, 0xE5, 0x59, 0x3F, 0x76, 0x6F, 0x49, 0xB1, 
+	0x11, 0xC2, 0x5A, 0x2E, 0x16, 0x29, 0x0D, 0xDE, 0xB7, 0x8E, 
+	0xDC, 0x40, 0xD5, 0xA2, 0xEE, 0xE0, 0x1E, 0xA1, 0xF4, 0xBE, 
+	0x97, 0xDB, 0x86, 0x63, 0x96, 0x14, 0xCD, 0x98, 0x09, 0x60, 
+	0x2D, 0x30, 0x76, 0x9C, 0x3C, 0xCD, 0xE6, 0x88, 0xEE, 0x47, 
+	0x92, 0x79, 0x0B, 0x5A, 0x00, 0xE2, 0x5E, 0x5F, 0x11, 0x7C, 
+	0x7D, 0xF9, 0x08, 0xB7, 0x20, 0x06, 0x89, 0x2A, 0x5D, 0xFD, 
+	0x00, 0xAB, 0x22, 0xE1, 0xF0, 0xB3, 0xBC, 0x24, 0xA9, 0x5E, 
+	0x26, 0x0E, 0x1F, 0x00, 0x2D, 0xFE, 0x21, 0x9A, 0x53, 0x5B, 
+	0x6D, 0xD3, 0x2B, 0xAB, 0x94, 0x82, 0x68, 0x43, 0x36, 0xD8, 
+	0xF6, 0x2F, 0xC6, 0x22, 0xFC, 0xB5, 0x41, 0x5D, 0x0D, 0x33, 
+	0x60, 0xEA, 0xA4, 0x7D, 0x7E, 0xE8, 0x4B, 0x55, 0x91, 0x56, 
+	0xD3, 0x5C, 0x57, 0x8F, 0x1F, 0x94, 0x17, 0x2F, 0xAA, 0xDE, 
+	0xE9, 0x9E, 0xA8, 0xF4, 0xCF, 0x8A, 0x4C, 0x8E, 0xA0, 0xE4, 
+	0x56, 0x73, 0xB2, 0xCF, 0x4F, 0x86, 0xC5, 0x69, 0x3C, 0xF3, 
+	0x24, 0x20, 0x8B, 0x5C, 0x96, 0x0C, 0xFA, 0x6B, 0x12, 0x3B, 
+	0x9A, 0x67, 0xC1, 0xDF, 0xC6, 0x96, 0xB2, 0xA5, 0xD5, 0x92, 
+	0x0D, 0x9B, 0x09, 0x42, 0x68, 0x24, 0x10, 0x45, 0xD4, 0x50, 
+	0xE4, 0x17, 0x39, 0x48, 0xD0, 0x35, 0x8B, 0x94, 0x6D, 0x11, 
+	0xDE, 0x8F, 0xCA, 0x59, 0x02, 0x81, 0x81, 0x00, 0xEA, 0x24, 
+	0xA7, 0xF9, 0x69, 0x33, 0xE9, 0x71, 0xDC, 0x52, 0x7D, 0x88, 
+	0x21, 0x28, 0x2F, 0x49, 0xDE, 0xBA, 0x72, 0x16, 0xE9, 0xCC, 
+	0x47, 0x7A, 0x88, 0x0D, 0x94, 0x57, 0x84, 0x58, 0x16, 0x3A, 
+	0x81, 0xB0, 0x3F, 0xA2, 0xCF, 0xA6, 0x6C, 0x1E, 0xB0, 0x06, 
+	0x29, 0x00, 0x8F, 0xE7, 0x77, 0x76, 0xAC, 0xDB, 0xCA, 0xC7, 
+	0xD9, 0x5E, 0x9B, 0x3F, 0x26, 0x90, 0x52, 0xAE, 0xFC, 0x38, 
+	0x90, 0x00, 0x14, 0xBB, 0xB4, 0x0F, 0x58, 0x94, 0xE7, 0x2F, 
+	0x6A, 0x7E, 0x1C, 0x4F, 0x41, 0x21, 0xD4, 0x31, 0x59, 0x1F, 
+	0x4E, 0x8A, 0x1A, 0x8D, 0xA7, 0x57, 0x6C, 0x22, 0xD8, 0xE5, 
+	0xF4, 0x7E, 0x32, 0xA6, 0x10, 0xCB, 0x64, 0xA5, 0x55, 0x03, 
+	0x87, 0xA6, 0x27, 0x05, 0x8C, 0xC3, 0xD7, 0xB6, 0x27, 0xB2, 
+	0x4D, 0xBA, 0x30, 0xDA, 0x47, 0x8F, 0x54, 0xD3, 0x3D, 0x8B, 
+	0x84, 0x8D, 0x94, 0x98, 0x58, 0xA5, 0x02, 0x81, 0x81, 0x00, 
+	0xD5, 0x38, 0x1B, 0xC3, 0x8F, 0xC5, 0x93, 0x0C, 0x47, 0x0B, 
+	0x6F, 0x35, 0x92, 0xC5, 0xB0, 0x8D, 0x46, 0xC8, 0x92, 0x18, 
+	0x8F, 0xF5, 0x80, 0x0A, 0xF7, 0xEF, 0xA1, 0xFE, 0x80, 0xB9, 
+	0xB5, 0x2A, 0xBA, 0xCA, 0x18, 0xB0, 0x5D, 0xA5, 0x07, 0xD0, 
+	0x93, 0x8D, 0xD8, 0x9C, 0x04, 0x1C, 0xD4, 0x62, 0x8E, 0xA6, 
+	0x26, 0x81, 0x01, 0xFF, 0xCE, 0x8A, 0x2A, 0x63, 0x34, 0x35, 
+	0x40, 0xAA, 0x6D, 0x80, 0xDE, 0x89, 0x23, 0x6A, 0x57, 0x4D, 
+	0x9E, 0x6E, 0xAD, 0x93, 0x4E, 0x56, 0x90, 0x0B, 0x6D, 0x9D, 
+	0x73, 0x8B, 0x0C, 0xAE, 0x27, 0x3D, 0xDE, 0x4E, 0xF0, 0xAA, 
+	0xC5, 0x6C, 0x78, 0x67, 0x6C, 0x94, 0x52, 0x9C, 0x37, 0x67, 
+	0x6C, 0x2D, 0xEF, 0xBB, 0xAF, 0xDF, 0xA6, 0x90, 0x3C, 0xC4, 
+	0x47, 0xCF, 0x8D, 0x96, 0x9E, 0x98, 0xA9, 0xB4, 0x9F, 0xC5, 
+	0xA6, 0x50, 0xDC, 0xB3, 0xF0, 0xFB, 0x74, 0x17, 0x02, 0x81, 
+	0x80, 0x5E, 0x83, 0x09, 0x62, 0xBD, 0xBA, 0x7C, 0xA2, 0xBF, 
+	0x42, 0x74, 0xF5, 0x7C, 0x1C, 0xD2, 0x69, 0xC9, 0x04, 0x0D, 
+	0x85, 0x7E, 0x3E, 0x3D, 0x24, 0x12, 0xC3, 0x18, 0x7B, 0xF3, 
+	0x29, 0xF3, 0x5F, 0x0E, 0x76, 0x6C, 0x59, 0x75, 0xE4, 0x41, 
+	0x84, 0x69, 0x9D, 0x32, 0xF3, 0xCD, 0x22, 0xAB, 0xB0, 0x35, 
+	0xBA, 0x4A, 0xB2, 0x3C, 0xE5, 0xD9, 0x58, 0xB6, 0x62, 0x4F, 
+	0x5D, 0xDE, 0xE5, 0x9E, 0x0A, 0xCA, 0x53, 0xB2, 0x2C, 0xF7, 
+	0x9E, 0xB3, 0x6B, 0x0A, 0x5B, 0x79, 0x65, 0xEC, 0x6E, 0x91, 
+	0x4E, 0x92, 0x20, 0xF6, 0xFC, 0xFC, 0x16, 0xED, 0xD3, 0x76, 
+	0x0C, 0xE2, 0xEC, 0x7F, 0xB2, 0x69, 0x13, 0x6B, 0x78, 0x0E, 
+	0x5A, 0x46, 0x64, 0xB4, 0x5E, 0xB7, 0x25, 0xA0, 0x5A, 0x75, 
+	0x3A, 0x4B, 0xEF, 0xC7, 0x3C, 0x3E, 0xF7, 0xFD, 0x26, 0xB8, 
+	0x20, 0xC4, 0x99, 0x0A, 0x9A, 0x73, 0xBE, 0xC3, 0x19, 0x02, 
+	0x81, 0x81, 0x00, 0xBA, 0x44, 0x93, 0x14, 0xAC, 0x34, 0x19, 
+	0x3B, 0x5F, 0x91, 0x60, 0xAC, 0xF7, 0xB4, 0xD6, 0x81, 0x05, 
+	0x36, 0x51, 0x53, 0x3D, 0xE8, 0x65, 0xDC, 0xAF, 0x2E, 0xDC, 
+	0x61, 0x3E, 0xC9, 0x7D, 0xB8, 0x7F, 0x87, 0xF0, 0x3B, 0x9B, 
+	0x03, 0x82, 0x29, 0x37, 0xCE, 0x72, 0x4E, 0x11, 0xD5, 0xB1, 
+	0xC1, 0x0C, 0x07, 0xA0, 0x99, 0x91, 0x4A, 0x8D, 0x7F, 0xEC, 
+	0x79, 0xCF, 0xF1, 0x39, 0xB5, 0xE9, 0x85, 0xEC, 0x62, 0xF7, 
+	0xDA, 0x7D, 0xBC, 0x64, 0x4D, 0x22, 0x3C, 0x0E, 0xF2, 0xD6, 
+	0x51, 0xF5, 0x87, 0xD8, 0x99, 0xC0, 0x11, 0x20, 0x5D, 0x0F, 
+	0x29, 0xFD, 0x5B, 0xE2, 0xAE, 0xD9, 0x1C, 0xD9, 0x21, 0x56, 
+	0x6D, 0xFC, 0x84, 0xD0, 0x5F, 0xED, 0x10, 0x15, 0x1C, 0x18, 
+	0x21, 0xE7, 0xC4, 0x3D, 0x4B, 0xD7, 0xD0, 0x9E, 0x6A, 0x95, 
+	0xCF, 0x22, 0xC9, 0x03, 0x7B, 0x9E, 0xE3, 0x60, 0x01, 0xFC, 
+	0x2F, 0x02, 0x81, 0x80, 0x11, 0xD0, 0x4B, 0xCF, 0x1B, 0x67, 
+	0xB9, 0x9F, 0x10, 0x75, 0x47, 0x86, 0x65, 0xAE, 0x31, 0xC2, 
+	0xC6, 0x30, 0xAC, 0x59, 0x06, 0x50, 0xD9, 0x0F, 0xB5, 0x70, 
+	0x06, 0xF7, 0xF0, 0xD3, 0xC8, 0x62, 0x7C, 0xA8, 0xDA, 0x6E, 
+	0xF6, 0x21, 0x3F, 0xD3, 0x7F, 0x5F, 0xEA, 0x8A, 0xAB, 0x3F, 
+	0xD9, 0x2A, 0x5E, 0xF3, 0x51, 0xD2, 0xC2, 0x30, 0x37, 0xE3, 
+	0x2D, 0xA3, 0x75, 0x0D, 0x1E, 0x4D, 0x21, 0x34, 0xD5, 0x57, 
+	0x70, 0x5C, 0x89, 0xBF, 0x72, 0xEC, 0x4A, 0x6E, 0x68, 0xD5, 
+	0xCD, 0x18, 0x74, 0x33, 0x4E, 0x8C, 0x3A, 0x45, 0x8F, 0xE6, 
+	0x96, 0x40, 0xEB, 0x63, 0xF9, 0x19, 0x86, 0x3A, 0x51, 0xDD, 
+	0x89, 0x4B, 0xB0, 0xF3, 0xF9, 0x9F, 0x5D, 0x28, 0x95, 0x38, 
+	0xBE, 0x35, 0xAB, 0xCA, 0x5C, 0xE7, 0x93, 0x53, 0x34, 0xA1, 
+	0x45, 0x5D, 0x13, 0x39, 0x65, 0x42, 0x46, 0xA1, 0x9F, 0xCD, 
+	0xF5, 0xBF
+};
+static const int sizeof_client_key_der_2048 = sizeof(client_key_der_2048);
+
+/* ./certs/client-cert.der, 2048-bit */
+static const unsigned char client_cert_der_2048[] =
+{
+	0x30, 0x82, 0x04, 0xCA, 0x30, 0x82, 0x03, 0xB2, 0xA0, 0x03, 
+	0x02, 0x01, 0x02, 0x02, 0x09, 0x00, 0xAA, 0x27, 0xB3, 0xC5, 
+	0xA9, 0x72, 0x6E, 0x0D, 0x30, 0x0D, 0x06, 0x09, 0x2A, 0x86, 
+	0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01, 0x0B, 0x05, 0x00, 0x30, 
+	0x81, 0x9E, 0x31, 0x0B, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 
+	0x06, 0x13, 0x02, 0x55, 0x53, 0x31, 0x10, 0x30, 0x0E, 0x06, 
+	0x03, 0x55, 0x04, 0x08, 0x0C, 0x07, 0x4D, 0x6F, 0x6E, 0x74, 
+	0x61, 0x6E, 0x61, 0x31, 0x10, 0x30, 0x0E, 0x06, 0x03, 0x55, 
+	0x04, 0x07, 0x0C, 0x07, 0x42, 0x6F, 0x7A, 0x65, 0x6D, 0x61, 
+	0x6E, 0x31, 0x15, 0x30, 0x13, 0x06, 0x03, 0x55, 0x04, 0x0A, 
+	0x0C, 0x0C, 0x77, 0x6F, 0x6C, 0x66, 0x53, 0x53, 0x4C, 0x5F, 
+	0x32, 0x30, 0x34, 0x38, 0x31, 0x19, 0x30, 0x17, 0x06, 0x03, 
+	0x55, 0x04, 0x0B, 0x0C, 0x10, 0x50, 0x72, 0x6F, 0x67, 0x72, 
+	0x61, 0x6D, 0x6D, 0x69, 0x6E, 0x67, 0x2D, 0x32, 0x30, 0x34, 
+	0x38, 0x31, 0x18, 0x30, 0x16, 0x06, 0x03, 0x55, 0x04, 0x03, 
+	0x0C, 0x0F, 0x77, 0x77, 0x77, 0x2E, 0x77, 0x6F, 0x6C, 0x66, 
+	0x73, 0x73, 0x6C, 0x2E, 0x63, 0x6F, 0x6D, 0x31, 0x1F, 0x30, 
+	0x1D, 0x06, 0x09, 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 
+	0x09, 0x01, 0x16, 0x10, 0x69, 0x6E, 0x66, 0x6F, 0x40, 0x77, 
+	0x6F, 0x6C, 0x66, 0x73, 0x73, 0x6C, 0x2E, 0x63, 0x6F, 0x6D, 
+	0x30, 0x1E, 0x17, 0x0D, 0x31, 0x35, 0x30, 0x35, 0x30, 0x37, 
+	0x31, 0x38, 0x32, 0x31, 0x30, 0x31, 0x5A, 0x17, 0x0D, 0x31, 
+	0x38, 0x30, 0x31, 0x33, 0x31, 0x31, 0x38, 0x32, 0x31, 0x30, 
+	0x31, 0x5A, 0x30, 0x81, 0x9E, 0x31, 0x0B, 0x30, 0x09, 0x06, 
+	0x03, 0x55, 0x04, 0x06, 0x13, 0x02, 0x55, 0x53, 0x31, 0x10, 
+	0x30, 0x0E, 0x06, 0x03, 0x55, 0x04, 0x08, 0x0C, 0x07, 0x4D, 
+	0x6F, 0x6E, 0x74, 0x61, 0x6E, 0x61, 0x31, 0x10, 0x30, 0x0E, 
+	0x06, 0x03, 0x55, 0x04, 0x07, 0x0C, 0x07, 0x42, 0x6F, 0x7A, 
+	0x65, 0x6D, 0x61, 0x6E, 0x31, 0x15, 0x30, 0x13, 0x06, 0x03, 
+	0x55, 0x04, 0x0A, 0x0C, 0x0C, 0x77, 0x6F, 0x6C, 0x66, 0x53, 
+	0x53, 0x4C, 0x5F, 0x32, 0x30, 0x34, 0x38, 0x31, 0x19, 0x30, 
+	0x17, 0x06, 0x03, 0x55, 0x04, 0x0B, 0x0C, 0x10, 0x50, 0x72, 
+	0x6F, 0x67, 0x72, 0x61, 0x6D, 0x6D, 0x69, 0x6E, 0x67, 0x2D, 
+	0x32, 0x30, 0x34, 0x38, 0x31, 0x18, 0x30, 0x16, 0x06, 0x03, 
+	0x55, 0x04, 0x03, 0x0C, 0x0F, 0x77, 0x77, 0x77, 0x2E, 0x77, 
+	0x6F, 0x6C, 0x66, 0x73, 0x73, 0x6C, 0x2E, 0x63, 0x6F, 0x6D, 
+	0x31, 0x1F, 0x30, 0x1D, 0x06, 0x09, 0x2A, 0x86, 0x48, 0x86, 
+	0xF7, 0x0D, 0x01, 0x09, 0x01, 0x16, 0x10, 0x69, 0x6E, 0x66, 
+	0x6F, 0x40, 0x77, 0x6F, 0x6C, 0x66, 0x73, 0x73, 0x6C, 0x2E, 
+	0x63, 0x6F, 0x6D, 0x30, 0x82, 0x01, 0x22, 0x30, 0x0D, 0x06, 
+	0x09, 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01, 0x01, 
+	0x05, 0x00, 0x03, 0x82, 0x01, 0x0F, 0x00, 0x30, 0x82, 0x01, 
+	0x0A, 0x02, 0x82, 0x01, 0x01, 0x00, 0xC3, 0x03, 0xD1, 0x2B, 
+	0xFE, 0x39, 0xA4, 0x32, 0x45, 0x3B, 0x53, 0xC8, 0x84, 0x2B, 
+	0x2A, 0x7C, 0x74, 0x9A, 0xBD, 0xAA, 0x2A, 0x52, 0x07, 0x47, 
+	0xD6, 0xA6, 0x36, 0xB2, 0x07, 0x32, 0x8E, 0xD0, 0xBA, 0x69, 
+	0x7B, 0xC6, 0xC3, 0x44, 0x9E, 0xD4, 0x81, 0x48, 0xFD, 0x2D, 
+	0x68, 0xA2, 0x8B, 0x67, 0xBB, 0xA1, 0x75, 0xC8, 0x36, 0x2C, 
+	0x4A, 0xD2, 0x1B, 0xF7, 0x8B, 0xBA, 0xCF, 0x0D, 0xF9, 0xEF, 
+	0xEC, 0xF1, 0x81, 0x1E, 0x7B, 0x9B, 0x03, 0x47, 0x9A, 0xBF, 
+	0x65, 0xCC, 0x7F, 0x65, 0x24, 0x69, 0xA6, 0xE8, 0x14, 0x89, 
+	0x5B, 0xE4, 0x34, 0xF7, 0xC5, 0xB0, 0x14, 0x93, 0xF5, 0x67, 
+	0x7B, 0x3A, 0x7A, 0x78, 0xE1, 0x01, 0x56, 0x56, 0x91, 0xA6, 
+	0x13, 0x42, 0x8D, 0xD2, 0x3C, 0x40, 0x9C, 0x4C, 0xEF, 0xD1, 
+	0x86, 0xDF, 0x37, 0x51, 0x1B, 0x0C, 0xA1, 0x3B, 0xF5, 0xF1, 
+	0xA3, 0x4A, 0x35, 0xE4, 0xE1, 0xCE, 0x96, 0xDF, 0x1B, 0x7E, 
+	0xBF, 0x4E, 0x97, 0xD0, 0x10, 0xE8, 0xA8, 0x08, 0x30, 0x81, 
+	0xAF, 0x20, 0x0B, 0x43, 0x14, 0xC5, 0x74, 0x67, 0xB4, 0x32, 
+	0x82, 0x6F, 0x8D, 0x86, 0xC2, 0x88, 0x40, 0x99, 0x36, 0x83, 
+	0xBA, 0x1E, 0x40, 0x72, 0x22, 0x17, 0xD7, 0x52, 0x65, 0x24, 
+	0x73, 0xB0, 0xCE, 0xEF, 0x19, 0xCD, 0xAE, 0xFF, 0x78, 0x6C, 
+	0x7B, 0xC0, 0x12, 0x03, 0xD4, 0x4E, 0x72, 0x0D, 0x50, 0x6D, 
+	0x3B, 0xA3, 0x3B, 0xA3, 0x99, 0x5E, 0x9D, 0xC8, 0xD9, 0x0C, 
+	0x85, 0xB3, 0xD9, 0x8A, 0xD9, 0x54, 0x26, 0xDB, 0x6D, 0xFA, 
+	0xAC, 0xBB, 0xFF, 0x25, 0x4C, 0xC4, 0xD1, 0x79, 0xF4, 0x71, 
+	0xD3, 0x86, 0x40, 0x18, 0x13, 0xB0, 0x63, 0xB5, 0x72, 0x4E, 
+	0x30, 0xC4, 0x97, 0x84, 0x86, 0x2D, 0x56, 0x2F, 0xD7, 0x15, 
+	0xF7, 0x7F, 0xC0, 0xAE, 0xF5, 0xFC, 0x5B, 0xE5, 0xFB, 0xA1, 
+	0xBA, 0xD3, 0x02, 0x03, 0x01, 0x00, 0x01, 0xA3, 0x82, 0x01, 
+	0x07, 0x30, 0x82, 0x01, 0x03, 0x30, 0x1D, 0x06, 0x03, 0x55, 
+	0x1D, 0x0E, 0x04, 0x16, 0x04, 0x14, 0x33, 0xD8, 0x45, 0x66, 
+	0xD7, 0x68, 0x87, 0x18, 0x7E, 0x54, 0x0D, 0x70, 0x27, 0x91, 
+	0xC7, 0x26, 0xD7, 0x85, 0x65, 0xC0, 0x30, 0x81, 0xD3, 0x06, 
+	0x03, 0x55, 0x1D, 0x23, 0x04, 0x81, 0xCB, 0x30, 0x81, 0xC8, 
+	0x80, 0x14, 0x33, 0xD8, 0x45, 0x66, 0xD7, 0x68, 0x87, 0x18, 
+	0x7E, 0x54, 0x0D, 0x70, 0x27, 0x91, 0xC7, 0x26, 0xD7, 0x85, 
+	0x65, 0xC0, 0xA1, 0x81, 0xA4, 0xA4, 0x81, 0xA1, 0x30, 0x81, 
+	0x9E, 0x31, 0x0B, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x06, 
+	0x13, 0x02, 0x55, 0x53, 0x31, 0x10, 0x30, 0x0E, 0x06, 0x03, 
+	0x55, 0x04, 0x08, 0x0C, 0x07, 0x4D, 0x6F, 0x6E, 0x74, 0x61, 
+	0x6E, 0x61, 0x31, 0x10, 0x30, 0x0E, 0x06, 0x03, 0x55, 0x04, 
+	0x07, 0x0C, 0x07, 0x42, 0x6F, 0x7A, 0x65, 0x6D, 0x61, 0x6E, 
+	0x31, 0x15, 0x30, 0x13, 0x06, 0x03, 0x55, 0x04, 0x0A, 0x0C, 
+	0x0C, 0x77, 0x6F, 0x6C, 0x66, 0x53, 0x53, 0x4C, 0x5F, 0x32, 
+	0x30, 0x34, 0x38, 0x31, 0x19, 0x30, 0x17, 0x06, 0x03, 0x55, 
+	0x04, 0x0B, 0x0C, 0x10, 0x50, 0x72, 0x6F, 0x67, 0x72, 0x61, 
+	0x6D, 0x6D, 0x69, 0x6E, 0x67, 0x2D, 0x32, 0x30, 0x34, 0x38, 
+	0x31, 0x18, 0x30, 0x16, 0x06, 0x03, 0x55, 0x04, 0x03, 0x0C, 
+	0x0F, 0x77, 0x77, 0x77, 0x2E, 0x77, 0x6F, 0x6C, 0x66, 0x73, 
+	0x73, 0x6C, 0x2E, 0x63, 0x6F, 0x6D, 0x31, 0x1F, 0x30, 0x1D, 
+	0x06, 0x09, 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x09, 
+	0x01, 0x16, 0x10, 0x69, 0x6E, 0x66, 0x6F, 0x40, 0x77, 0x6F, 
+	0x6C, 0x66, 0x73, 0x73, 0x6C, 0x2E, 0x63, 0x6F, 0x6D, 0x82, 
+	0x09, 0x00, 0xAA, 0x27, 0xB3, 0xC5, 0xA9, 0x72, 0x6E, 0x0D, 
+	0x30, 0x0C, 0x06, 0x03, 0x55, 0x1D, 0x13, 0x04, 0x05, 0x30, 
+	0x03, 0x01, 0x01, 0xFF, 0x30, 0x0D, 0x06, 0x09, 0x2A, 0x86, 
+	0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01, 0x0B, 0x05, 0x00, 0x03, 
+	0x82, 0x01, 0x01, 0x00, 0x51, 0x96, 0xA7, 0x1C, 0x26, 0x5D, 
+	0x1C, 0x90, 0xC6, 0x32, 0x9F, 0x96, 0x15, 0xF2, 0x1D, 0xE7, 
+	0x93, 0x9C, 0xAC, 0x75, 0x56, 0x95, 0xFD, 0x20, 0x70, 0xAB, 
+	0x45, 0x6A, 0x09, 0xB0, 0xF3, 0xF2, 0x03, 0xA8, 0xDB, 0xDC, 
+	0x2F, 0xBC, 0x1F, 0x87, 0x7A, 0xA3, 0xD4, 0x8F, 0xD5, 0x49, 
+	0x97, 0x7E, 0x3C, 0x54, 0xAC, 0xB1, 0xE3, 0xF0, 0x39, 0x0D, 
+	0xFE, 0x09, 0x9A, 0x23, 0xF6, 0x32, 0xA6, 0x41, 0x59, 0xBD, 
+	0x60, 0xE8, 0xBD, 0xDE, 0x00, 0x36, 0x6F, 0x3E, 0xE9, 0x41, 
+	0x6F, 0xA9, 0x63, 0xC7, 0xAA, 0xD5, 0x7B, 0xF3, 0xE4, 0x39, 
+	0x48, 0x9E, 0xF6, 0x60, 0xC6, 0xC6, 0x86, 0xD5, 0x72, 0x86, 
+	0x23, 0xCD, 0xF5, 0x6A, 0x63, 0x53, 0xA4, 0xF8, 0xFC, 0x51, 
+	0x6A, 0xCD, 0x60, 0x74, 0x8E, 0xA3, 0x86, 0x61, 0x01, 0x34, 
+	0x78, 0xF7, 0x29, 0x97, 0xB3, 0xA7, 0x34, 0xB6, 0x0A, 0xDE, 
+	0xB5, 0x71, 0x7A, 0x09, 0xA6, 0x3E, 0xD6, 0x82, 0x58, 0x89, 
+	0x67, 0x9C, 0xC5, 0x68, 0x62, 0xBA, 0x06, 0xD6, 0x39, 0xBB, 
+	0xCB, 0x3A, 0xC0, 0xE0, 0x63, 0x1F, 0xC7, 0x0C, 0x9C, 0x12, 
+	0x86, 0xEC, 0xF7, 0x39, 0x6A, 0x61, 0x93, 0xD0, 0x33, 0x14, 
+	0xC6, 0x55, 0x3B, 0xB6, 0xCF, 0x80, 0x5B, 0x8C, 0x43, 0xEF, 
+	0x43, 0x44, 0x0B, 0x3C, 0x93, 0x39, 0xA3, 0x4E, 0x15, 0xD1, 
+	0x0B, 0x5F, 0x84, 0x98, 0x1D, 0xCD, 0x9F, 0xA9, 0x47, 0xEB, 
+	0x3B, 0x56, 0x30, 0xB6, 0x76, 0x92, 0xC1, 0x48, 0x5F, 0xBC, 
+	0x95, 0xB0, 0x50, 0x1A, 0x55, 0xC8, 0x4E, 0x62, 0x47, 0x87, 
+	0x54, 0x64, 0x0C, 0x9B, 0x91, 0xFA, 0x43, 0xB3, 0x29, 0x48, 
+	0xBE, 0xE6, 0x12, 0xEB, 0xE3, 0x44, 0xC6, 0x52, 0xE4, 0x40, 
+	0xC6, 0x83, 0x95, 0x1B, 0xA7, 0x65, 0x27, 0x69, 0x73, 0x2F, 
+	0xC8, 0xA0, 0x4D, 0x7F, 0xBE, 0xEA, 0x9B, 0x67, 0xB2, 0x7B
+
+};
+static const int sizeof_client_cert_der_2048 = sizeof(client_cert_der_2048);
+
+/* ./certs/dh2048.der, 2048-bit */
+static const unsigned char dh_key_der_2048[] =
+{
+	0x30, 0x82, 0x01, 0x08, 0x02, 0x82, 0x01, 0x01, 0x00, 0xB0, 
+	0xA1, 0x08, 0x06, 0x9C, 0x08, 0x13, 0xBA, 0x59, 0x06, 0x3C, 
+	0xBC, 0x30, 0xD5, 0xF5, 0x00, 0xC1, 0x4F, 0x44, 0xA7, 0xD6, 
+	0xEF, 0x4A, 0xC6, 0x25, 0x27, 0x1C, 0xE8, 0xD2, 0x96, 0x53, 
+	0x0A, 0x5C, 0x91, 0xDD, 0xA2, 0xC2, 0x94, 0x84, 0xBF, 0x7D, 
+	0xB2, 0x44, 0x9F, 0x9B, 0xD2, 0xC1, 0x8A, 0xC5, 0xBE, 0x72, 
+	0x5C, 0xA7, 0xE7, 0x91, 0xE6, 0xD4, 0x9F, 0x73, 0x07, 0x85, 
+	0x5B, 0x66, 0x48, 0xC7, 0x70, 0xFA, 0xB4, 0xEE, 0x02, 0xC9, 
+	0x3D, 0x9A, 0x4A, 0xDA, 0x3D, 0xC1, 0x46, 0x3E, 0x19, 0x69, 
+	0xD1, 0x17, 0x46, 0x07, 0xA3, 0x4D, 0x9F, 0x2B, 0x96, 0x17, 
+	0x39, 0x6D, 0x30, 0x8D, 0x2A, 0xF3, 0x94, 0xD3, 0x75, 0xCF, 
+	0xA0, 0x75, 0xE6, 0xF2, 0x92, 0x1F, 0x1A, 0x70, 0x05, 0xAA, 
+	0x04, 0x83, 0x57, 0x30, 0xFB, 0xDA, 0x76, 0x93, 0x38, 0x50, 
+	0xE8, 0x27, 0xFD, 0x63, 0xEE, 0x3C, 0xE5, 0xB7, 0xC8, 0x09, 
+	0xAE, 0x6F, 0x50, 0x35, 0x8E, 0x84, 0xCE, 0x4A, 0x00, 0xE9, 
+	0x12, 0x7E, 0x5A, 0x31, 0xD7, 0x33, 0xFC, 0x21, 0x13, 0x76, 
+	0xCC, 0x16, 0x30, 0xDB, 0x0C, 0xFC, 0xC5, 0x62, 0xA7, 0x35, 
+	0xB8, 0xEF, 0xB7, 0xB0, 0xAC, 0xC0, 0x36, 0xF6, 0xD9, 0xC9, 
+	0x46, 0x48, 0xF9, 0x40, 0x90, 0x00, 0x2B, 0x1B, 0xAA, 0x6C, 
+	0xE3, 0x1A, 0xC3, 0x0B, 0x03, 0x9E, 0x1B, 0xC2, 0x46, 0xE4, 
+	0x48, 0x4E, 0x22, 0x73, 0x6F, 0xC3, 0x5F, 0xD4, 0x9A, 0xD6, 
+	0x30, 0x07, 0x48, 0xD6, 0x8C, 0x90, 0xAB, 0xD4, 0xF6, 0xF1, 
+	0xE3, 0x48, 0xD3, 0x58, 0x4B, 0xA6, 0xB9, 0xCD, 0x29, 0xBF, 
+	0x68, 0x1F, 0x08, 0x4B, 0x63, 0x86, 0x2F, 0x5C, 0x6B, 0xD6, 
+	0xB6, 0x06, 0x65, 0xF7, 0xA6, 0xDC, 0x00, 0x67, 0x6B, 0xBB, 
+	0xC3, 0xA9, 0x41, 0x83, 0xFB, 0xC7, 0xFA, 0xC8, 0xE2, 0x1E, 
+	0x7E, 0xAF, 0x00, 0x3F, 0x93, 0x02, 0x01, 0x02
+};
+static const int sizeof_dh_key_der_2048 = sizeof(dh_key_der_2048);
+
+/* ./certs/dsa2048.der, 2048-bit */
+static const unsigned char dsa_key_der_2048[] =
+{
+	0x30, 0x82, 0x03, 0x3F, 0x02, 0x01, 0x00, 0x02, 0x82, 0x01, 
+	0x01, 0x00, 0xCC, 0x8E, 0xC9, 0xA0, 0xD5, 0x9A, 0x27, 0x1C, 
+	0xDA, 0x52, 0xDF, 0xC7, 0xC0, 0xE6, 0x06, 0xA4, 0x3E, 0x8A, 
+	0x66, 0x49, 0xD0, 0x59, 0x33, 0x51, 0x69, 0xC4, 0x9C, 0x5E, 
+	0x64, 0x85, 0xC7, 0xF1, 0xAB, 0xD5, 0xD9, 0x62, 0xAC, 0xFD, 
+	0xA1, 0xE0, 0x1B, 0x57, 0xFF, 0x96, 0xEF, 0x0C, 0x9F, 0xC8, 
+	0x44, 0x87, 0xEB, 0x5C, 0x91, 0xD0, 0x46, 0x42, 0x09, 0x50, 
+	0x6A, 0x23, 0xCB, 0x89, 0x6F, 0x55, 0xE9, 0x6A, 0x11, 0xA9, 
+	0xA8, 0x32, 0xAB, 0x33, 0x0D, 0x51, 0xB5, 0x79, 0x51, 0xB4, 
+	0xAB, 0xA2, 0x25, 0x11, 0x8D, 0xE5, 0x24, 0xBE, 0xD8, 0xF1, 
+	0x9D, 0x4E, 0x12, 0x6F, 0xAC, 0x44, 0x54, 0x80, 0xA9, 0xB4, 
+	0x81, 0x68, 0x4E, 0x44, 0x0E, 0xB8, 0x39, 0xF3, 0xBE, 0x83, 
+	0x08, 0x74, 0xA2, 0xC6, 0x7A, 0xD7, 0x6A, 0x7D, 0x0A, 0x88, 
+	0x57, 0x83, 0x48, 0xDC, 0xCF, 0x5E, 0x6F, 0xEE, 0x68, 0x0C, 
+	0xF7, 0xFF, 0x03, 0x04, 0x90, 0xAA, 0xF7, 0x07, 0x98, 0xF8, 
+	0x67, 0x5A, 0x83, 0x23, 0x66, 0x47, 0x60, 0xC3, 0x43, 0x6E, 
+	0x03, 0x91, 0xAC, 0x28, 0x66, 0xCB, 0xF0, 0xD3, 0x05, 0xC8, 
+	0x09, 0x97, 0xB5, 0xAE, 0x01, 0x5E, 0x80, 0x3B, 0x9D, 0x4F, 
+	0xDE, 0x3E, 0x94, 0xFE, 0xCB, 0x82, 0xB0, 0xB1, 0xFC, 0x91, 
+	0x8B, 0x1D, 0x8A, 0xEE, 0xC6, 0x06, 0x1F, 0x37, 0x91, 0x48, 
+	0xD2, 0xF8, 0x6C, 0x5D, 0x60, 0x13, 0x83, 0xA7, 0x81, 0xAC, 
+	0xCA, 0x8D, 0xD0, 0x6A, 0x04, 0x0A, 0xEA, 0x3E, 0x22, 0x4E, 
+	0x13, 0xF1, 0x0D, 0xBB, 0x60, 0x6B, 0xCD, 0xBC, 0x5C, 0x87, 
+	0xA3, 0x67, 0x2B, 0x42, 0xA1, 0x9F, 0xCD, 0x39, 0x58, 0xBE, 
+	0x55, 0xB1, 0x93, 0x84, 0xCE, 0xB2, 0x10, 0x4E, 0xE4, 0xC3, 
+	0x9F, 0xB2, 0x53, 0x61, 0x01, 0x29, 0xAA, 0x96, 0xCB, 0x20, 
+	0x60, 0x42, 0x1D, 0xBA, 0x75, 0x4B, 0x63, 0xC1, 0x02, 0x15, 
+	0x00, 0xE7, 0xA5, 0x39, 0xD4, 0x6A, 0x37, 0x5E, 0x95, 0x06, 
+	0x39, 0x07, 0x77, 0x0A, 0xEB, 0xA0, 0x03, 0xEB, 0x78, 0x82, 
+	0x9B, 0x02, 0x82, 0x01, 0x01, 0x00, 0x9A, 0xD4, 0x4C, 0x71, 
+	0x2F, 0xEC, 0xFA, 0x32, 0xB2, 0x80, 0x7E, 0x61, 0x4A, 0x6B, 
+	0x5F, 0x18, 0x76, 0x43, 0xC3, 0x69, 0xBA, 0x41, 0xC7, 0xA7, 
+	0x1D, 0x79, 0x01, 0xEC, 0xAF, 0x34, 0x87, 0x67, 0x4F, 0x29, 
+	0x80, 0xA8, 0x3B, 0x87, 0xF6, 0xE8, 0xA1, 0xE8, 0xCD, 0x1B, 
+	0x1C, 0x86, 0x38, 0xF6, 0xD1, 0x0C, 0x46, 0x2E, 0xC8, 0xE0, 
+	0xC9, 0x30, 0x26, 0xD5, 0x2C, 0x7F, 0xC1, 0x08, 0xBF, 0xCC, 
+	0x5A, 0x82, 0x8E, 0xD4, 0xD4, 0x49, 0xAA, 0xA2, 0xFA, 0xE6, 
+	0xC1, 0x9D, 0xF0, 0xD9, 0x96, 0xB0, 0xFF, 0x0C, 0x5B, 0x33, 
+	0x8E, 0x06, 0xDD, 0x9D, 0x28, 0xA9, 0xE9, 0x80, 0x41, 0x3B, 
+	0xD8, 0x7A, 0x94, 0x21, 0x8F, 0x56, 0xF1, 0xA2, 0xB4, 0x2B, 
+	0x89, 0x1C, 0x74, 0xFF, 0x7E, 0x91, 0xDC, 0x1F, 0x91, 0x13, 
+	0x98, 0xAF, 0xC7, 0x06, 0xD2, 0x4C, 0x90, 0xA2, 0xBD, 0xDA, 
+	0x16, 0xBA, 0x65, 0xB0, 0x2D, 0x68, 0x87, 0x3C, 0x6E, 0x25, 
+	0x8D, 0x90, 0xC7, 0xBC, 0x0D, 0xA9, 0x43, 0x03, 0xC9, 0xBE, 
+	0xCF, 0x85, 0x6F, 0xDB, 0x07, 0x7B, 0x8C, 0xF8, 0xB1, 0xC2, 
+	0x49, 0x10, 0x69, 0x63, 0x56, 0x37, 0xC5, 0x30, 0xD2, 0xFB, 
+	0x71, 0x9A, 0xE8, 0x82, 0x07, 0x2E, 0x3E, 0x95, 0x50, 0xF3, 
+	0x73, 0xCF, 0x34, 0x5B, 0xD5, 0xAB, 0x02, 0x15, 0xF2, 0xCC, 
+	0xD7, 0x52, 0xC5, 0x28, 0xD8, 0x41, 0x19, 0x55, 0x6F, 0xB8, 
+	0x5F, 0xF1, 0x99, 0xB3, 0xC7, 0xD9, 0xB3, 0x71, 0xF4, 0x2D, 
+	0xDF, 0x22, 0x59, 0x35, 0x86, 0xDB, 0x39, 0xCA, 0x1B, 0x4D, 
+	0x35, 0x90, 0x19, 0x6B, 0x31, 0xE3, 0xC8, 0xC6, 0x09, 0xBF, 
+	0x7C, 0xED, 0x01, 0xB4, 0xB2, 0xF5, 0x6E, 0xDA, 0x63, 0x41, 
+	0x3C, 0xE6, 0x3A, 0x72, 0x2D, 0x65, 0x48, 0xF6, 0x07, 0xCD, 
+	0x92, 0x84, 0x8B, 0x1D, 0xA7, 0x31, 0x6B, 0xD6, 0xF0, 0xFB, 
+	0xD9, 0xF4, 0x02, 0x82, 0x01, 0x00, 0x66, 0x4B, 0xBB, 0xB7, 
+	0xC9, 0x48, 0x95, 0x0D, 0x5A, 0xA6, 0x2D, 0xA1, 0x7F, 0xDF, 
+	0x1F, 0x67, 0x6D, 0xED, 0x52, 0x4B, 0x16, 0x6C, 0x17, 0xC6, 
+	0xAE, 0xF8, 0x6A, 0xC4, 0x57, 0xED, 0x2F, 0xB3, 0xF0, 0x2A, 
+	0x55, 0xAB, 0xBA, 0xCA, 0xEA, 0x17, 0xE8, 0x35, 0x7C, 0xE5, 
+	0x31, 0x0D, 0x4A, 0x95, 0xFC, 0x43, 0x6F, 0x97, 0x3C, 0x5C, 
+	0x67, 0xAC, 0xBE, 0x67, 0x7F, 0xE9, 0x4E, 0xAA, 0x48, 0xB3, 
+	0x92, 0xA1, 0x76, 0x75, 0xEA, 0x04, 0x34, 0x7F, 0x87, 0x33, 
+	0x2D, 0x24, 0xB6, 0x29, 0x97, 0xE3, 0x04, 0x77, 0x93, 0x89, 
+	0x13, 0xDB, 0x1B, 0x93, 0xB8, 0x2C, 0x90, 0x1A, 0x09, 0x3B, 
+	0x26, 0xD9, 0x59, 0xF3, 0x2A, 0x09, 0x58, 0xDC, 0xAC, 0x25, 
+	0xB4, 0xA9, 0x45, 0x3B, 0xA2, 0x3A, 0x6C, 0x61, 0x84, 0xBF, 
+	0x68, 0xD4, 0xEA, 0x9B, 0xC5, 0x29, 0x48, 0x60, 0x15, 0x10, 
+	0x35, 0x2C, 0x44, 0x1D, 0xB5, 0x9A, 0xEE, 0xAC, 0xC1, 0x68, 
+	0xE8, 0x47, 0xB7, 0x41, 0x34, 0x39, 0x9A, 0xF8, 0xA5, 0x20, 
+	0xE9, 0x24, 0xC4, 0x2C, 0x58, 0x3F, 0x4C, 0x41, 0x30, 0x3A, 
+	0x14, 0x6E, 0x8D, 0xEA, 0xAD, 0xBA, 0x9B, 0x43, 0xD3, 0x98, 
+	0x2F, 0x83, 0xD8, 0x14, 0x67, 0xE8, 0xF8, 0xD5, 0x4F, 0xAC, 
+	0xE0, 0x3B, 0xBF, 0xA7, 0x54, 0x16, 0x5E, 0x49, 0x64, 0x26, 
+	0x54, 0xA4, 0x6B, 0x69, 0x7C, 0xBA, 0x8A, 0x83, 0xD9, 0x2E, 
+	0x65, 0x0A, 0xA2, 0x27, 0xEF, 0x99, 0x99, 0x08, 0xD7, 0xB5, 
+	0x9F, 0xA0, 0x01, 0xEF, 0x7E, 0x17, 0xBF, 0x83, 0x6B, 0x2E, 
+	0xDD, 0xC0, 0x39, 0x38, 0x23, 0x68, 0xB4, 0x76, 0x6B, 0xE5, 
+	0xCA, 0xF7, 0x7C, 0xEE, 0xC0, 0x52, 0xE2, 0xDD, 0xAD, 0x59, 
+	0x3A, 0x42, 0x06, 0x45, 0xB0, 0xC7, 0xC1, 0x77, 0x05, 0xB2, 
+	0x0C, 0x32, 0x40, 0x46, 0xAA, 0xDA, 0x79, 0x77, 0x04, 0x71, 
+	0xDF, 0x7A, 0x02, 0x15, 0x00, 0x98, 0xEE, 0xB9, 0x51, 0x37, 
+	0x3E, 0x75, 0x13, 0x13, 0x06, 0x8F, 0x94, 0xD3, 0xE6, 0xE9, 
+	0x00, 0xCB, 0x62, 0x6D, 0x9A
+};
+static const int sizeof_dsa_key_der_2048 = sizeof(dsa_key_der_2048);
+
+/* ./certs/rsa2048.der, 2048-bit */
+static const unsigned char rsa_key_der_2048[] =
+{
+	0x30, 0x82, 0x04, 0xA3, 0x02, 0x01, 0x00, 0x02, 0x82, 0x01, 
+	0x01, 0x00, 0xE9, 0x8A, 0x5D, 0x15, 0xA4, 0xD4, 0x34, 0xB9, 
+	0x59, 0xA2, 0xDA, 0xAF, 0x74, 0xC8, 0xC9, 0x03, 0x26, 0x38, 
+	0xFA, 0x48, 0xFC, 0x4D, 0x30, 0x6E, 0xEA, 0x76, 0x89, 0xCE, 
+	0x4F, 0xF6, 0x87, 0xDE, 0x32, 0x3A, 0x46, 0x6E, 0x38, 0x12, 
+	0x58, 0x37, 0x22, 0x0D, 0x80, 0xAC, 0x2D, 0xAF, 0x2F, 0x12, 
+	0x3E, 0x62, 0x73, 0x60, 0x66, 0x68, 0x90, 0xB2, 0x6F, 0x47, 
+	0x17, 0x04, 0x2B, 0xCA, 0xB7, 0x26, 0xB7, 0x10, 0xC2, 0x13, 
+	0xF9, 0x7A, 0x62, 0x0A, 0x93, 0x32, 0x90, 0x42, 0x0D, 0x16, 
+	0x2E, 0xFA, 0xD7, 0x29, 0xD7, 0x9F, 0x54, 0xE4, 0xFC, 0x65, 
+	0x74, 0xF8, 0xF6, 0x43, 0x6B, 0x4E, 0x9E, 0x34, 0x7F, 0xCB, 
+	0x6B, 0x1C, 0x1A, 0xDE, 0x82, 0x81, 0xBF, 0x08, 0x5D, 0x3F, 
+	0xC0, 0xB6, 0xB1, 0xA8, 0xA5, 0x9C, 0x81, 0x70, 0xA7, 0x4E, 
+	0x32, 0x87, 0x15, 0x1C, 0x78, 0x0E, 0xF0, 0x18, 0xFE, 0xEB, 
+	0x4B, 0x37, 0x2B, 0xE9, 0xE1, 0xF7, 0xFA, 0x51, 0xC6, 0x58, 
+	0xB9, 0xD8, 0x06, 0x03, 0xED, 0xC0, 0x03, 0x18, 0x55, 0x8B, 
+	0x98, 0xFE, 0xB1, 0xF6, 0xD0, 0x3D, 0xFA, 0x63, 0xC0, 0x38, 
+	0x19, 0xC7, 0x00, 0xEF, 0x4D, 0x99, 0x60, 0xB4, 0xBA, 0xCE, 
+	0xE3, 0xCE, 0xD9, 0x6B, 0x2D, 0x76, 0x94, 0xFF, 0xFB, 0x77, 
+	0x18, 0x4A, 0xFE, 0x65, 0xF0, 0x0A, 0x91, 0x5C, 0x3B, 0x22, 
+	0x94, 0x85, 0xD0, 0x20, 0x18, 0x59, 0x2E, 0xA5, 0x33, 0x03, 
+	0xAC, 0x1B, 0x5F, 0x78, 0x32, 0x11, 0x25, 0xEE, 0x7F, 0x96, 
+	0x21, 0xA9, 0xD6, 0x76, 0x97, 0x8D, 0x66, 0x7E, 0xB2, 0x91, 
+	0xD0, 0x36, 0x2E, 0xA3, 0x1D, 0xBF, 0xF1, 0x85, 0xED, 0xC0, 
+	0x3E, 0x60, 0xB8, 0x5A, 0x9F, 0xAB, 0x80, 0xE0, 0xEA, 0x5D, 
+	0x5F, 0x75, 0x56, 0xC7, 0x4D, 0x51, 0x8E, 0xD4, 0x1F, 0x34, 
+	0xA6, 0x36, 0xF1, 0x30, 0x1F, 0x51, 0x99, 0x2F, 0x02, 0x03, 
+	0x01, 0x00, 0x01, 0x02, 0x82, 0x01, 0x00, 0x52, 0x11, 0x33, 
+	0x40, 0xC5, 0xD9, 0x64, 0x65, 0xB5, 0xE0, 0x0A, 0xA5, 0x19, 
+	0x8E, 0xED, 0x44, 0x54, 0x0C, 0x35, 0xB7, 0xAC, 0x21, 0x9B, 
+	0xE1, 0x7E, 0x37, 0x05, 0x9A, 0x20, 0x73, 0x6B, 0xAF, 0x63, 
+	0x4B, 0x23, 0x30, 0xDC, 0x37, 0x66, 0x14, 0x89, 0xBC, 0xE0, 
+	0xF8, 0xA0, 0x5D, 0x2D, 0x57, 0x65, 0xE0, 0xC6, 0xD6, 0x9B, 
+	0x66, 0x27, 0x62, 0xEC, 0xC3, 0xB8, 0x8C, 0xD8, 0xAE, 0xB5, 
+	0xC9, 0xBF, 0x0E, 0xFE, 0x84, 0x72, 0x68, 0xD5, 0x47, 0x0E, 
+	0x0E, 0xF8, 0xAE, 0x9D, 0x56, 0xAC, 0x4F, 0xAD, 0x88, 0xA0, 
+	0xA2, 0xF6, 0xFC, 0x38, 0xCD, 0x96, 0x5B, 0x5E, 0x7E, 0xB6, 
+	0x98, 0xBB, 0xF3, 0x8A, 0xEC, 0xFA, 0xC8, 0xB7, 0x90, 0x75, 
+	0xA0, 0x0E, 0x77, 0x6B, 0xFD, 0x59, 0x45, 0x5A, 0x0C, 0xFF, 
+	0x95, 0x8D, 0xCE, 0xFE, 0x9B, 0xF6, 0x19, 0x8E, 0x0B, 0xA1, 
+	0x0C, 0xEE, 0xC6, 0x79, 0xDD, 0x9D, 0x61, 0x85, 0x5C, 0x19, 
+	0x6C, 0x47, 0xCC, 0x08, 0xFF, 0xA5, 0x62, 0xDB, 0xE4, 0x2D, 
+	0x2D, 0xDD, 0x14, 0x67, 0xD6, 0x4A, 0x64, 0x2A, 0x66, 0x49, 
+	0x54, 0x9C, 0xE3, 0x85, 0x18, 0xE7, 0x31, 0x42, 0xE2, 0xD0, 
+	0x2C, 0x20, 0xA0, 0x74, 0x0F, 0x1F, 0x20, 0x89, 0xBA, 0xAB, 
+	0x80, 0xD8, 0x38, 0xD9, 0x46, 0x69, 0xBB, 0xEF, 0xCC, 0x8B, 
+	0xA1, 0x73, 0xA7, 0xF2, 0xE4, 0x38, 0x5D, 0xD6, 0x75, 0x9F, 
+	0x88, 0x0E, 0x56, 0xCD, 0xD8, 0x84, 0x59, 0x29, 0x73, 0xF5, 
+	0xA1, 0x79, 0xDA, 0x7A, 0x1F, 0xBF, 0x73, 0x83, 0xC0, 0x6D, 
+	0x9F, 0x8B, 0x34, 0x15, 0xC0, 0x6D, 0x69, 0x6A, 0x20, 0xE6, 
+	0x51, 0xCF, 0x45, 0x6E, 0xCC, 0x05, 0xC4, 0x3A, 0xC0, 0x9E, 
+	0xAA, 0xC1, 0x06, 0x2F, 0xAB, 0x99, 0x30, 0xE1, 0x6E, 0x9D, 
+	0x45, 0x7A, 0xFF, 0xA9, 0xCE, 0x70, 0xB8, 0x16, 0x1A, 0x0E, 
+	0x20, 0xFA, 0xC1, 0x02, 0x81, 0x81, 0x00, 0xFF, 0x30, 0x11, 
+	0xC2, 0x3C, 0x6B, 0xB4, 0xD6, 0x9E, 0x6B, 0xC1, 0x93, 0xD1, 
+	0x48, 0xCE, 0x80, 0x2D, 0xBE, 0xAF, 0xF7, 0xBA, 0xB2, 0xD7, 
+	0xC3, 0xC4, 0x53, 0x6E, 0x15, 0x02, 0xAA, 0x61, 0xB9, 0xEA, 
+	0x05, 0x9B, 0x79, 0x67, 0x0B, 0xCE, 0xD9, 0xFB, 0x98, 0x8C, 
+	0x1D, 0x6B, 0xF4, 0x5A, 0xA7, 0xA0, 0x5E, 0x54, 0x18, 0xE9, 
+	0x31, 0x44, 0x7C, 0xC7, 0x52, 0xD8, 0x6D, 0xA0, 0x3E, 0xD6, 
+	0x14, 0x2D, 0x7B, 0x15, 0x9D, 0x1E, 0x39, 0x87, 0x96, 0xDD, 
+	0xA8, 0x33, 0x55, 0x2A, 0x8E, 0x32, 0xC0, 0xC4, 0xE5, 0xB8, 
+	0xCB, 0xCD, 0x32, 0x8D, 0xAD, 0x7B, 0xE5, 0xC6, 0x7E, 0x4D, 
+	0x6F, 0xF3, 0xA4, 0xC5, 0xA6, 0x40, 0xBE, 0x90, 0x3A, 0x33, 
+	0x6A, 0x24, 0xB2, 0x80, 0x81, 0x12, 0xAC, 0xE3, 0x7B, 0x26, 
+	0x63, 0xCF, 0x88, 0xB9, 0xFF, 0x74, 0x23, 0x37, 0x52, 0xF0, 
+	0xC4, 0x27, 0x5D, 0x45, 0x1F, 0x02, 0x81, 0x81, 0x00, 0xEA, 
+	0x48, 0xA7, 0xDD, 0x73, 0x41, 0x56, 0x21, 0x15, 0xF7, 0x42, 
+	0x45, 0x4D, 0xA9, 0xE1, 0x66, 0x5B, 0xBD, 0x25, 0x7D, 0xF7, 
+	0xA8, 0x65, 0x13, 0xAE, 0x2D, 0x38, 0x11, 0xCD, 0x93, 0xFC, 
+	0x30, 0xA3, 0x2C, 0x44, 0xBB, 0xCF, 0xD0, 0x21, 0x8F, 0xFB, 
+	0xC1, 0xF9, 0xAD, 0x1D, 0xEE, 0x96, 0xCF, 0x97, 0x49, 0x60, 
+	0x53, 0x80, 0xA5, 0xA2, 0xF8, 0xEE, 0xB9, 0xD5, 0x77, 0x44, 
+	0xDD, 0xFD, 0x19, 0x2A, 0xF1, 0x81, 0xF4, 0xD9, 0x3C, 0xEC, 
+	0x73, 0xD0, 0x2A, 0xD8, 0x3C, 0x27, 0x87, 0x79, 0x12, 0x86, 
+	0xE7, 0x57, 0x0C, 0x59, 0xD1, 0x44, 0x55, 0xAE, 0xC3, 0x4D, 
+	0x42, 0xAD, 0xA9, 0xB3, 0x28, 0x61, 0xB4, 0x9C, 0xA6, 0x63, 
+	0xD3, 0x96, 0xB1, 0x75, 0x9F, 0x2A, 0x78, 0x99, 0xE3, 0x1E, 
+	0x71, 0x47, 0x39, 0xF4, 0x52, 0xE3, 0x66, 0xF1, 0xEB, 0x7F, 
+	0xEF, 0xC6, 0x81, 0x93, 0x4C, 0x99, 0xF1, 0x02, 0x81, 0x81, 
+	0x00, 0xC5, 0xB6, 0x20, 0x8C, 0x34, 0xF3, 0xDD, 0xF0, 0x4A, 
+	0x5D, 0x82, 0x65, 0x5C, 0x48, 0xE4, 0x75, 0x3A, 0xFB, 0xFA, 
+	0xAA, 0x1C, 0xE4, 0x63, 0x77, 0x31, 0xAC, 0xD2, 0x25, 0x45, 
+	0x23, 0x6D, 0x03, 0xF5, 0xE4, 0xD2, 0x48, 0x85, 0x26, 0x08, 
+	0xE5, 0xAA, 0xA0, 0xCE, 0x2E, 0x1D, 0x6D, 0xFC, 0xAE, 0xD2, 
+	0xF9, 0x42, 0x7E, 0xEA, 0x6D, 0x59, 0x7A, 0xB3, 0x93, 0xE4, 
+	0x4B, 0x4B, 0x54, 0x63, 0xD8, 0xCE, 0x44, 0x06, 0xC2, 0xEC, 
+	0x9F, 0xF6, 0x05, 0x55, 0x46, 0xF4, 0x3E, 0x8F, 0xF2, 0x0C, 
+	0x30, 0x7E, 0x5C, 0xDD, 0x88, 0x49, 0x3B, 0x59, 0xB9, 0x87, 
+	0xBC, 0xC6, 0xC5, 0x24, 0x8A, 0x10, 0x63, 0x21, 0x1F, 0x66, 
+	0x1A, 0x3E, 0xF4, 0x58, 0xD1, 0x6C, 0x0D, 0x40, 0xB2, 0xC0, 
+	0x1D, 0x63, 0x42, 0x0E, 0xC4, 0x56, 0x0E, 0xC0, 0xCC, 0xC2, 
+	0xD6, 0x66, 0x0E, 0xC4, 0xAB, 0xB5, 0x33, 0xF6, 0x51, 0x02, 
+	0x81, 0x80, 0x19, 0x7E, 0xE6, 0xA5, 0xB6, 0xD1, 0x39, 0x6A, 
+	0x48, 0x55, 0xAC, 0x24, 0x96, 0x9B, 0x12, 0x28, 0x6D, 0x7B, 
+	0x5C, 0x05, 0x25, 0x5A, 0x72, 0x05, 0x7E, 0x42, 0xF5, 0x83, 
+	0x1A, 0x78, 0x2C, 0x4D, 0xAE, 0xB4, 0x36, 0x96, 0xA9, 0xBA, 
+	0xE0, 0xAC, 0x26, 0x9D, 0xA9, 0x6A, 0x29, 0x83, 0xB9, 0x6D, 
+	0xC5, 0xEC, 0xFA, 0x4A, 0x9C, 0x09, 0x6A, 0x7E, 0xE4, 0x9B, 
+	0xDC, 0x9B, 0x2A, 0x27, 0x6E, 0x4F, 0xBA, 0xD8, 0xA5, 0x67, 
+	0xDB, 0xEC, 0x41, 0x5F, 0x29, 0x1C, 0x40, 0x83, 0xEB, 0x59, 
+	0x56, 0xD7, 0xA9, 0x4E, 0xAB, 0xAE, 0x70, 0x67, 0xD1, 0xA3, 
+	0xF1, 0x6C, 0xD7, 0x8F, 0x96, 0x0E, 0x8D, 0xAC, 0xAB, 0x55, 
+	0x58, 0x66, 0xD3, 0x1E, 0x47, 0x9B, 0xF0, 0x4C, 0xED, 0xF6, 
+	0x49, 0xE8, 0xE9, 0x7B, 0x32, 0x61, 0x20, 0x31, 0x95, 0x05, 
+	0xB2, 0xF6, 0x09, 0xEA, 0x32, 0x14, 0x0F, 0xCF, 0x9A, 0x41, 
+	0x02, 0x81, 0x80, 0x77, 0x3F, 0xB6, 0x14, 0x8D, 0xC5, 0x13, 
+	0x08, 0x7E, 0xC9, 0xC4, 0xEA, 0xD4, 0xBA, 0x0D, 0xA4, 0x9E, 
+	0xB3, 0x6E, 0xDE, 0x1A, 0x7A, 0xF8, 0x89, 0x88, 0xEF, 0x36, 
+	0x3C, 0x11, 0xBC, 0x83, 0xE8, 0x30, 0x6C, 0x81, 0x7C, 0x47, 
+	0xF3, 0x4D, 0xCA, 0xEA, 0x56, 0x01, 0x62, 0x55, 0x2E, 0x4B, 
+	0x89, 0xA9, 0xBD, 0x6F, 0x01, 0xF6, 0x74, 0x02, 0xAA, 0xE3, 
+	0x84, 0x66, 0x06, 0x95, 0x34, 0xA1, 0xE2, 0xCA, 0x65, 0xFE, 
+	0xA3, 0x2D, 0x43, 0x97, 0x95, 0x6C, 0x6F, 0xD5, 0xB4, 0x38, 
+	0xF6, 0xF9, 0x95, 0x30, 0xFA, 0xF8, 0x9C, 0x25, 0x2B, 0xB6, 
+	0x14, 0x51, 0xCC, 0x2E, 0xB3, 0x5B, 0xD6, 0xDC, 0x1A, 0xEC, 
+	0x2D, 0x09, 0x5B, 0x3F, 0x3A, 0xD0, 0xB8, 0x4E, 0x27, 0x1F, 
+	0xDC, 0x2A, 0xEE, 0xAC, 0xA9, 0x59, 0x5D, 0x07, 0x63, 0x11, 
+	0x83, 0x0B, 0xD4, 0x74, 0x80, 0xB6, 0x7D, 0x62, 0x45, 0xBF, 
+	0x56
+};
+static const int sizeof_rsa_key_der_2048 = sizeof(rsa_key_der_2048);
+
+/* ./certs/ca-cert.der, 2048-bit */
+static const unsigned char ca_cert_der_2048[] =
+{
+	0x30, 0x82, 0x04, 0xAA, 0x30, 0x82, 0x03, 0x92, 0xA0, 0x03, 
+	0x02, 0x01, 0x02, 0x02, 0x09, 0x00, 0xD9, 0x80, 0x3A, 0xC3, 
+	0xD2, 0xF4, 0xDA, 0x37, 0x30, 0x0D, 0x06, 0x09, 0x2A, 0x86, 
+	0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01, 0x0B, 0x05, 0x00, 0x30, 
+	0x81, 0x94, 0x31, 0x0B, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 
+	0x06, 0x13, 0x02, 0x55, 0x53, 0x31, 0x10, 0x30, 0x0E, 0x06, 
+	0x03, 0x55, 0x04, 0x08, 0x0C, 0x07, 0x4D, 0x6F, 0x6E, 0x74, 
+	0x61, 0x6E, 0x61, 0x31, 0x10, 0x30, 0x0E, 0x06, 0x03, 0x55, 
+	0x04, 0x07, 0x0C, 0x07, 0x42, 0x6F, 0x7A, 0x65, 0x6D, 0x61, 
+	0x6E, 0x31, 0x11, 0x30, 0x0F, 0x06, 0x03, 0x55, 0x04, 0x0A, 
+	0x0C, 0x08, 0x53, 0x61, 0x77, 0x74, 0x6F, 0x6F, 0x74, 0x68, 
+	0x31, 0x13, 0x30, 0x11, 0x06, 0x03, 0x55, 0x04, 0x0B, 0x0C, 
+	0x0A, 0x43, 0x6F, 0x6E, 0x73, 0x75, 0x6C, 0x74, 0x69, 0x6E, 
+	0x67, 0x31, 0x18, 0x30, 0x16, 0x06, 0x03, 0x55, 0x04, 0x03, 
+	0x0C, 0x0F, 0x77, 0x77, 0x77, 0x2E, 0x77, 0x6F, 0x6C, 0x66, 
+	0x73, 0x73, 0x6C, 0x2E, 0x63, 0x6F, 0x6D, 0x31, 0x1F, 0x30, 
+	0x1D, 0x06, 0x09, 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 
+	0x09, 0x01, 0x16, 0x10, 0x69, 0x6E, 0x66, 0x6F, 0x40, 0x77, 
+	0x6F, 0x6C, 0x66, 0x73, 0x73, 0x6C, 0x2E, 0x63, 0x6F, 0x6D, 
+	0x30, 0x1E, 0x17, 0x0D, 0x31, 0x35, 0x30, 0x35, 0x30, 0x37, 
+	0x31, 0x38, 0x32, 0x31, 0x30, 0x31, 0x5A, 0x17, 0x0D, 0x31, 
+	0x38, 0x30, 0x31, 0x33, 0x31, 0x31, 0x38, 0x32, 0x31, 0x30, 
+	0x31, 0x5A, 0x30, 0x81, 0x94, 0x31, 0x0B, 0x30, 0x09, 0x06, 
+	0x03, 0x55, 0x04, 0x06, 0x13, 0x02, 0x55, 0x53, 0x31, 0x10, 
+	0x30, 0x0E, 0x06, 0x03, 0x55, 0x04, 0x08, 0x0C, 0x07, 0x4D, 
+	0x6F, 0x6E, 0x74, 0x61, 0x6E, 0x61, 0x31, 0x10, 0x30, 0x0E, 
+	0x06, 0x03, 0x55, 0x04, 0x07, 0x0C, 0x07, 0x42, 0x6F, 0x7A, 
+	0x65, 0x6D, 0x61, 0x6E, 0x31, 0x11, 0x30, 0x0F, 0x06, 0x03, 
+	0x55, 0x04, 0x0A, 0x0C, 0x08, 0x53, 0x61, 0x77, 0x74, 0x6F, 
+	0x6F, 0x74, 0x68, 0x31, 0x13, 0x30, 0x11, 0x06, 0x03, 0x55, 
+	0x04, 0x0B, 0x0C, 0x0A, 0x43, 0x6F, 0x6E, 0x73, 0x75, 0x6C, 
+	0x74, 0x69, 0x6E, 0x67, 0x31, 0x18, 0x30, 0x16, 0x06, 0x03, 
+	0x55, 0x04, 0x03, 0x0C, 0x0F, 0x77, 0x77, 0x77, 0x2E, 0x77, 
+	0x6F, 0x6C, 0x66, 0x73, 0x73, 0x6C, 0x2E, 0x63, 0x6F, 0x6D, 
+	0x31, 0x1F, 0x30, 0x1D, 0x06, 0x09, 0x2A, 0x86, 0x48, 0x86, 
+	0xF7, 0x0D, 0x01, 0x09, 0x01, 0x16, 0x10, 0x69, 0x6E, 0x66, 
+	0x6F, 0x40, 0x77, 0x6F, 0x6C, 0x66, 0x73, 0x73, 0x6C, 0x2E, 
+	0x63, 0x6F, 0x6D, 0x30, 0x82, 0x01, 0x22, 0x30, 0x0D, 0x06, 
+	0x09, 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01, 0x01, 
+	0x05, 0x00, 0x03, 0x82, 0x01, 0x0F, 0x00, 0x30, 0x82, 0x01, 
+	0x0A, 0x02, 0x82, 0x01, 0x01, 0x00, 0xBF, 0x0C, 0xCA, 0x2D, 
+	0x14, 0xB2, 0x1E, 0x84, 0x42, 0x5B, 0xCD, 0x38, 0x1F, 0x4A, 
+	0xF2, 0x4D, 0x75, 0x10, 0xF1, 0xB6, 0x35, 0x9F, 0xDF, 0xCA, 
+	0x7D, 0x03, 0x98, 0xD3, 0xAC, 0xDE, 0x03, 0x66, 0xEE, 0x2A, 
+	0xF1, 0xD8, 0xB0, 0x7D, 0x6E, 0x07, 0x54, 0x0B, 0x10, 0x98, 
+	0x21, 0x4D, 0x80, 0xCB, 0x12, 0x20, 0xE7, 0xCC, 0x4F, 0xDE, 
+	0x45, 0x7D, 0xC9, 0x72, 0x77, 0x32, 0xEA, 0xCA, 0x90, 0xBB, 
+	0x69, 0x52, 0x10, 0x03, 0x2F, 0xA8, 0xF3, 0x95, 0xC5, 0xF1, 
+	0x8B, 0x62, 0x56, 0x1B, 0xEF, 0x67, 0x6F, 0xA4, 0x10, 0x41, 
+	0x95, 0xAD, 0x0A, 0x9B, 0xE3, 0xA5, 0xC0, 0xB0, 0xD2, 0x70, 
+	0x76, 0x50, 0x30, 0x5B, 0xA8, 0xE8, 0x08, 0x2C, 0x7C, 0xED, 
+	0xA7, 0xA2, 0x7A, 0x8D, 0x38, 0x29, 0x1C, 0xAC, 0xC7, 0xED, 
+	0xF2, 0x7C, 0x95, 0xB0, 0x95, 0x82, 0x7D, 0x49, 0x5C, 0x38, 
+	0xCD, 0x77, 0x25, 0xEF, 0xBD, 0x80, 0x75, 0x53, 0x94, 0x3C, 
+	0x3D, 0xCA, 0x63, 0x5B, 0x9F, 0x15, 0xB5, 0xD3, 0x1D, 0x13, 
+	0x2F, 0x19, 0xD1, 0x3C, 0xDB, 0x76, 0x3A, 0xCC, 0xB8, 0x7D, 
+	0xC9, 0xE5, 0xC2, 0xD7, 0xDA, 0x40, 0x6F, 0xD8, 0x21, 0xDC, 
+	0x73, 0x1B, 0x42, 0x2D, 0x53, 0x9C, 0xFE, 0x1A, 0xFC, 0x7D, 
+	0xAB, 0x7A, 0x36, 0x3F, 0x98, 0xDE, 0x84, 0x7C, 0x05, 0x67, 
+	0xCE, 0x6A, 0x14, 0x38, 0x87, 0xA9, 0xF1, 0x8C, 0xB5, 0x68, 
+	0xCB, 0x68, 0x7F, 0x71, 0x20, 0x2B, 0xF5, 0xA0, 0x63, 0xF5, 
+	0x56, 0x2F, 0xA3, 0x26, 0xD2, 0xB7, 0x6F, 0xB1, 0x5A, 0x17, 
+	0xD7, 0x38, 0x99, 0x08, 0xFE, 0x93, 0x58, 0x6F, 0xFE, 0xC3, 
+	0x13, 0x49, 0x08, 0x16, 0x0B, 0xA7, 0x4D, 0x67, 0x00, 0x52, 
+	0x31, 0x67, 0x23, 0x4E, 0x98, 0xED, 0x51, 0x45, 0x1D, 0xB9, 
+	0x04, 0xD9, 0x0B, 0xEC, 0xD8, 0x28, 0xB3, 0x4B, 0xBD, 0xED, 
+	0x36, 0x79, 0x02, 0x03, 0x01, 0x00, 0x01, 0xA3, 0x81, 0xFC, 
+	0x30, 0x81, 0xF9, 0x30, 0x1D, 0x06, 0x03, 0x55, 0x1D, 0x0E, 
+	0x04, 0x16, 0x04, 0x14, 0x27, 0x8E, 0x67, 0x11, 0x74, 0xC3, 
+	0x26, 0x1D, 0x3F, 0xED, 0x33, 0x63, 0xB3, 0xA4, 0xD8, 0x1D, 
+	0x30, 0xE5, 0xE8, 0xD5, 0x30, 0x81, 0xC9, 0x06, 0x03, 0x55, 
+	0x1D, 0x23, 0x04, 0x81, 0xC1, 0x30, 0x81, 0xBE, 0x80, 0x14, 
+	0x27, 0x8E, 0x67, 0x11, 0x74, 0xC3, 0x26, 0x1D, 0x3F, 0xED, 
+	0x33, 0x63, 0xB3, 0xA4, 0xD8, 0x1D, 0x30, 0xE5, 0xE8, 0xD5, 
+	0xA1, 0x81, 0x9A, 0xA4, 0x81, 0x97, 0x30, 0x81, 0x94, 0x31, 
+	0x0B, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x06, 0x13, 0x02, 
+	0x55, 0x53, 0x31, 0x10, 0x30, 0x0E, 0x06, 0x03, 0x55, 0x04, 
+	0x08, 0x0C, 0x07, 0x4D, 0x6F, 0x6E, 0x74, 0x61, 0x6E, 0x61, 
+	0x31, 0x10, 0x30, 0x0E, 0x06, 0x03, 0x55, 0x04, 0x07, 0x0C, 
+	0x07, 0x42, 0x6F, 0x7A, 0x65, 0x6D, 0x61, 0x6E, 0x31, 0x11, 
+	0x30, 0x0F, 0x06, 0x03, 0x55, 0x04, 0x0A, 0x0C, 0x08, 0x53, 
+	0x61, 0x77, 0x74, 0x6F, 0x6F, 0x74, 0x68, 0x31, 0x13, 0x30, 
+	0x11, 0x06, 0x03, 0x55, 0x04, 0x0B, 0x0C, 0x0A, 0x43, 0x6F, 
+	0x6E, 0x73, 0x75, 0x6C, 0x74, 0x69, 0x6E, 0x67, 0x31, 0x18, 
+	0x30, 0x16, 0x06, 0x03, 0x55, 0x04, 0x03, 0x0C, 0x0F, 0x77, 
+	0x77, 0x77, 0x2E, 0x77, 0x6F, 0x6C, 0x66, 0x73, 0x73, 0x6C, 
+	0x2E, 0x63, 0x6F, 0x6D, 0x31, 0x1F, 0x30, 0x1D, 0x06, 0x09, 
+	0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x09, 0x01, 0x16, 
+	0x10, 0x69, 0x6E, 0x66, 0x6F, 0x40, 0x77, 0x6F, 0x6C, 0x66, 
+	0x73, 0x73, 0x6C, 0x2E, 0x63, 0x6F, 0x6D, 0x82, 0x09, 0x00, 
+	0xD9, 0x80, 0x3A, 0xC3, 0xD2, 0xF4, 0xDA, 0x37, 0x30, 0x0C, 
+	0x06, 0x03, 0x55, 0x1D, 0x13, 0x04, 0x05, 0x30, 0x03, 0x01, 
+	0x01, 0xFF, 0x30, 0x0D, 0x06, 0x09, 0x2A, 0x86, 0x48, 0x86, 
+	0xF7, 0x0D, 0x01, 0x01, 0x0B, 0x05, 0x00, 0x03, 0x82, 0x01, 
+	0x01, 0x00, 0x7A, 0xAF, 0x44, 0x3B, 0xAA, 0x6F, 0x53, 0x42, 
+	0xB2, 0x33, 0xAA, 0x43, 0x5F, 0x56, 0x30, 0xD3, 0xB9, 0x96, 
+	0x0B, 0x9A, 0x55, 0x5A, 0x39, 0x2A, 0x0B, 0x4E, 0xE4, 0x2E, 
+	0xF1, 0x95, 0x66, 0xC9, 0x86, 0x36, 0x82, 0x8D, 0x63, 0x7C, 
+	0x4D, 0xA2, 0xEE, 0x48, 0xBA, 0x03, 0xC7, 0x90, 0xD7, 0xA7, 
+	0xC6, 0x74, 0x60, 0x48, 0x5F, 0x31, 0xA2, 0xF9, 0x5E, 0x3E, 
+	0xC3, 0x82, 0xE1, 0xE5, 0x2F, 0x41, 0x81, 0x83, 0x29, 0x25, 
+	0x79, 0xD1, 0x53, 0x00, 0x69, 0x3C, 0xED, 0x0A, 0x30, 0x3B, 
+	0x41, 0x1D, 0x92, 0xA1, 0x2C, 0xA8, 0x9D, 0x2C, 0xE3, 0x23, 
+	0x87, 0x79, 0xE0, 0x55, 0x6E, 0x91, 0xA8, 0x50, 0xDA, 0x46, 
+	0x2F, 0xC2, 0x20, 0x50, 0x3E, 0x2B, 0x47, 0x97, 0x14, 0xB0, 
+	0x7D, 0x04, 0xBA, 0x45, 0x51, 0xD0, 0x6E, 0xE1, 0x5A, 0xA2, 
+	0x4B, 0x84, 0x9C, 0x4D, 0xCD, 0x85, 0x04, 0xF9, 0x28, 0x31, 
+	0x82, 0x93, 0xBC, 0xC7, 0x59, 0x49, 0x91, 0x03, 0xE8, 0xDF, 
+	0x6A, 0xE4, 0x56, 0xAD, 0x6A, 0xCB, 0x1F, 0x0D, 0x37, 0xE4, 
+	0x5E, 0xBD, 0xE7, 0x9F, 0xD5, 0xEC, 0x9D, 0x3C, 0x18, 0x25, 
+	0x9B, 0xF1, 0x2F, 0x50, 0x7D, 0xEB, 0x31, 0xCB, 0xF1, 0x63, 
+	0x22, 0x9D, 0x57, 0xFC, 0xF3, 0x84, 0x20, 0x1A, 0xC6, 0x07, 
+	0x87, 0x92, 0x26, 0x9E, 0x15, 0x18, 0x59, 0x33, 0x06, 0xDC, 
+	0xFB, 0xB0, 0xB6, 0x76, 0x5D, 0xF1, 0xC1, 0x2F, 0xC8, 0x2F, 
+	0x62, 0x9C, 0xC0, 0xD6, 0xDE, 0xEB, 0x65, 0x77, 0xF3, 0x5C, 
+	0xA6, 0xC3, 0x88, 0x27, 0x96, 0x75, 0xB4, 0xF4, 0x54, 0xCD, 
+	0xFF, 0x2D, 0x21, 0x2E, 0x96, 0xF0, 0x07, 0x73, 0x4B, 0xE9, 
+	0x93, 0x92, 0x90, 0xDE, 0x62, 0xD9, 0xA3, 0x3B, 0xAC, 0x6E, 
+	0x24, 0x5F, 0x27, 0x4A, 0xB3, 0x94, 0x70, 0xFF, 0x30, 0x17, 
+	0xE7, 0x7E, 0x32, 0x8F, 0x65, 0xB7, 0x75, 0x58
+};
+static const int sizeof_ca_cert_der_2048 = sizeof(ca_cert_der_2048);
+
+/* ./certs/server-key.der, 2048-bit */
+static const unsigned char server_key_der_2048[] =
+{
+	0x30, 0x82, 0x04, 0xA5, 0x02, 0x01, 0x00, 0x02, 0x82, 0x01, 
+	0x01, 0x00, 0xC0, 0x95, 0x08, 0xE1, 0x57, 0x41, 0xF2, 0x71, 
+	0x6D, 0xB7, 0xD2, 0x45, 0x41, 0x27, 0x01, 0x65, 0xC6, 0x45, 
+	0xAE, 0xF2, 0xBC, 0x24, 0x30, 0xB8, 0x95, 0xCE, 0x2F, 0x4E, 
+	0xD6, 0xF6, 0x1C, 0x88, 0xBC, 0x7C, 0x9F, 0xFB, 0xA8, 0x67, 
+	0x7F, 0xFE, 0x5C, 0x9C, 0x51, 0x75, 0xF7, 0x8A, 0xCA, 0x07, 
+	0xE7, 0x35, 0x2F, 0x8F, 0xE1, 0xBD, 0x7B, 0xC0, 0x2F, 0x7C, 
+	0xAB, 0x64, 0xA8, 0x17, 0xFC, 0xCA, 0x5D, 0x7B, 0xBA, 0xE0, 
+	0x21, 0xE5, 0x72, 0x2E, 0x6F, 0x2E, 0x86, 0xD8, 0x95, 0x73, 
+	0xDA, 0xAC, 0x1B, 0x53, 0xB9, 0x5F, 0x3F, 0xD7, 0x19, 0x0D, 
+	0x25, 0x4F, 0xE1, 0x63, 0x63, 0x51, 0x8B, 0x0B, 0x64, 0x3F, 
+	0xAD, 0x43, 0xB8, 0xA5, 0x1C, 0x5C, 0x34, 0xB3, 0xAE, 0x00, 
+	0xA0, 0x63, 0xC5, 0xF6, 0x7F, 0x0B, 0x59, 0x68, 0x78, 0x73, 
+	0xA6, 0x8C, 0x18, 0xA9, 0x02, 0x6D, 0xAF, 0xC3, 0x19, 0x01, 
+	0x2E, 0xB8, 0x10, 0xE3, 0xC6, 0xCC, 0x40, 0xB4, 0x69, 0xA3, 
+	0x46, 0x33, 0x69, 0x87, 0x6E, 0xC4, 0xBB, 0x17, 0xA6, 0xF3, 
+	0xE8, 0xDD, 0xAD, 0x73, 0xBC, 0x7B, 0x2F, 0x21, 0xB5, 0xFD, 
+	0x66, 0x51, 0x0C, 0xBD, 0x54, 0xB3, 0xE1, 0x6D, 0x5F, 0x1C, 
+	0xBC, 0x23, 0x73, 0xD1, 0x09, 0x03, 0x89, 0x14, 0xD2, 0x10, 
+	0xB9, 0x64, 0xC3, 0x2A, 0xD0, 0xA1, 0x96, 0x4A, 0xBC, 0xE1, 
+	0xD4, 0x1A, 0x5B, 0xC7, 0xA0, 0xC0, 0xC1, 0x63, 0x78, 0x0F, 
+	0x44, 0x37, 0x30, 0x32, 0x96, 0x80, 0x32, 0x23, 0x95, 0xA1, 
+	0x77, 0xBA, 0x13, 0xD2, 0x97, 0x73, 0xE2, 0x5D, 0x25, 0xC9, 
+	0x6A, 0x0D, 0xC3, 0x39, 0x60, 0xA4, 0xB4, 0xB0, 0x69, 0x42, 
+	0x42, 0x09, 0xE9, 0xD8, 0x08, 0xBC, 0x33, 0x20, 0xB3, 0x58, 
+	0x22, 0xA7, 0xAA, 0xEB, 0xC4, 0xE1, 0xE6, 0x61, 0x83, 0xC5, 
+	0xD2, 0x96, 0xDF, 0xD9, 0xD0, 0x4F, 0xAD, 0xD7, 0x02, 0x03, 
+	0x01, 0x00, 0x01, 0x02, 0x82, 0x01, 0x01, 0x00, 0x9A, 0xD0, 
+	0x34, 0x0F, 0x52, 0x62, 0x05, 0x50, 0x01, 0xEF, 0x9F, 0xED, 
+	0x64, 0x6E, 0xC2, 0xC4, 0xDA, 0x1A, 0xF2, 0x84, 0xD7, 0x92, 
+	0x10, 0x48, 0x92, 0xC4, 0xE9, 0x6A, 0xEB, 0x8B, 0x75, 0x6C, 
+	0xC6, 0x79, 0x38, 0xF2, 0xC9, 0x72, 0x4A, 0x86, 0x64, 0x54, 
+	0x95, 0x77, 0xCB, 0xC3, 0x9A, 0x9D, 0xB7, 0xD4, 0x1D, 0xA4, 
+	0x00, 0xC8, 0x9E, 0x4E, 0xE4, 0xDD, 0xC7, 0xBA, 0x67, 0x16, 
+	0xC1, 0x74, 0xBC, 0xA9, 0xD6, 0x94, 0x8F, 0x2B, 0x30, 0x1A, 
+	0xFB, 0xED, 0xDF, 0x21, 0x05, 0x23, 0xD9, 0x4A, 0x39, 0xBD, 
+	0x98, 0x6B, 0x65, 0x9A, 0xB8, 0xDC, 0xC4, 0x7D, 0xEE, 0xA6, 
+	0x43, 0x15, 0x2E, 0x3D, 0xBE, 0x1D, 0x22, 0x60, 0x2A, 0x73, 
+	0x30, 0xD5, 0x3E, 0xD8, 0xA2, 0xAC, 0x86, 0x43, 0x2E, 0xC4, 
+	0xF5, 0x64, 0x5E, 0x3F, 0x89, 0x75, 0x0F, 0x11, 0xD8, 0x51, 
+	0x25, 0x4E, 0x9F, 0xD8, 0xAA, 0xA3, 0xCE, 0x60, 0xB3, 0xE2, 
+	0x8A, 0xD9, 0x7E, 0x1B, 0xF0, 0x64, 0xCA, 0x9A, 0x5B, 0x05, 
+	0x0B, 0x5B, 0xAA, 0xCB, 0xE5, 0xE3, 0x3F, 0x6E, 0x32, 0x22, 
+	0x05, 0xF3, 0xD0, 0xFA, 0xEF, 0x74, 0x52, 0x81, 0xE2, 0x5F, 
+	0x74, 0xD3, 0xBD, 0xFF, 0x31, 0x83, 0x45, 0x75, 0xFA, 0x63, 
+	0x7A, 0x97, 0x2E, 0xD6, 0xB6, 0x19, 0xC6, 0x92, 0x26, 0xE4, 
+	0x28, 0x06, 0x50, 0x50, 0x0E, 0x78, 0x2E, 0xA9, 0x78, 0x0D, 
+	0x14, 0x97, 0xB4, 0x12, 0xD8, 0x31, 0x40, 0xAB, 0xA1, 0x01, 
+	0x41, 0xC2, 0x30, 0xF8, 0x07, 0x5F, 0x16, 0xE4, 0x61, 0x77, 
+	0xD2, 0x60, 0xF2, 0x9F, 0x8D, 0xE8, 0xF4, 0xBA, 0xEB, 0x63, 
+	0xDE, 0x2A, 0x97, 0x81, 0xEF, 0x4C, 0x6C, 0xE6, 0x55, 0x34, 
+	0x51, 0x2B, 0x28, 0x34, 0xF4, 0x53, 0x1C, 0xC4, 0x58, 0x0A, 
+	0x3F, 0xBB, 0xAF, 0xB5, 0xF7, 0x4A, 0x85, 0x43, 0x2D, 0x3C, 
+	0xF1, 0x58, 0x58, 0x81, 0x02, 0x81, 0x81, 0x00, 0xF2, 0x2C, 
+	0x54, 0x76, 0x39, 0x23, 0x63, 0xC9, 0x10, 0x32, 0xB7, 0x93, 
+	0xAD, 0xAF, 0xBE, 0x19, 0x75, 0x96, 0x81, 0x64, 0xE6, 0xB5, 
+	0xB8, 0x89, 0x42, 0x41, 0xD1, 0x6D, 0xD0, 0x1C, 0x1B, 0xF8, 
+	0x1B, 0xAC, 0x69, 0xCB, 0x36, 0x3C, 0x64, 0x7D, 0xDC, 0xF4, 
+	0x19, 0xB8, 0xC3, 0x60, 0xB1, 0x57, 0x48, 0x5F, 0x52, 0x4F, 
+	0x59, 0x3A, 0x55, 0x7F, 0x32, 0xC0, 0x19, 0x43, 0x50, 0x3F, 
+	0xAE, 0xCE, 0x6F, 0x17, 0xF3, 0x0E, 0x9F, 0x40, 0xCA, 0x4E, 
+	0xAD, 0x15, 0x3B, 0xC9, 0x79, 0xE9, 0xC0, 0x59, 0x38, 0x73, 
+	0x70, 0x9C, 0x0A, 0x7C, 0xC9, 0x3A, 0x48, 0x32, 0xA7, 0xD8, 
+	0x49, 0x75, 0x0A, 0x85, 0xC2, 0xC2, 0xFD, 0x15, 0x73, 0xDA, 
+	0x99, 0x09, 0x2A, 0x69, 0x9A, 0x9F, 0x0A, 0x71, 0xBF, 0xB0, 
+	0x04, 0xA6, 0x8C, 0x7A, 0x5A, 0x6F, 0x48, 0x5A, 0x54, 0x3B, 
+	0xC6, 0xB1, 0x53, 0x17, 0xDF, 0xE7, 0x02, 0x81, 0x81, 0x00, 
+	0xCB, 0x93, 0xDE, 0x77, 0x15, 0x5D, 0xB7, 0x5C, 0x5C, 0x7C, 
+	0xD8, 0x90, 0xA9, 0x98, 0x2D, 0xD6, 0x69, 0x0E, 0x63, 0xB3, 
+	0xA3, 0xDC, 0xA6, 0xCC, 0x8B, 0x6A, 0xA4, 0xA2, 0x12, 0x8C, 
+	0x8E, 0x7B, 0x48, 0x2C, 0xB2, 0x4B, 0x37, 0xDC, 0x06, 0x18, 
+	0x7D, 0xEA, 0xFE, 0x76, 0xA1, 0xD4, 0xA1, 0xE9, 0x3F, 0x0D, 
+	0xCD, 0x1B, 0x5F, 0xAF, 0x5F, 0x9E, 0x96, 0x5B, 0x5B, 0x0F, 
+	0xA1, 0x7C, 0xAF, 0xB3, 0x9B, 0x90, 0xDB, 0x57, 0x73, 0x3A, 
+	0xED, 0xB0, 0x23, 0x44, 0xAE, 0x41, 0x4F, 0x1F, 0x07, 0x42, 
+	0x13, 0x23, 0x4C, 0xCB, 0xFA, 0xF4, 0x14, 0xA4, 0xD5, 0xF7, 
+	0x9E, 0x36, 0x7C, 0x5B, 0x9F, 0xA8, 0x3C, 0xC1, 0x85, 0x5F, 
+	0x74, 0xD2, 0x39, 0x2D, 0xFF, 0xD0, 0x84, 0xDF, 0xFB, 0xB3, 
+	0x20, 0x7A, 0x2E, 0x9B, 0x17, 0xAE, 0xE6, 0xBA, 0x0B, 0xAE, 
+	0x5F, 0x53, 0xA4, 0x52, 0xED, 0x1B, 0xC4, 0x91, 0x02, 0x81, 
+	0x81, 0x00, 0xEC, 0x98, 0xDA, 0xBB, 0xD5, 0xFE, 0xF9, 0x52, 
+	0x4A, 0x7D, 0x02, 0x55, 0x49, 0x6F, 0x55, 0x6E, 0x52, 0x2F, 
+	0x84, 0xA3, 0x2B, 0xB3, 0x86, 0x62, 0xB3, 0x54, 0xD2, 0x63, 
+	0x52, 0xDA, 0xE3, 0x88, 0x76, 0xA0, 0xEF, 0x8B, 0x15, 0xA5, 
+	0xD3, 0x18, 0x14, 0x72, 0x77, 0x5E, 0xC7, 0xA3, 0x04, 0x1F, 
+	0x9E, 0x19, 0x62, 0xB5, 0x1B, 0x1B, 0x9E, 0xC3, 0xF2, 0xB5, 
+	0x32, 0xF9, 0x4C, 0xC1, 0xAA, 0xEB, 0x0C, 0x26, 0x7D, 0xD4, 
+	0x5F, 0x4A, 0x51, 0x5C, 0xA4, 0x45, 0x06, 0x70, 0x44, 0xA7, 
+	0x56, 0xC0, 0xD4, 0x22, 0x14, 0x76, 0x9E, 0xD8, 0x63, 0x50, 
+	0x89, 0x90, 0xD3, 0xE2, 0xBF, 0x81, 0x95, 0x92, 0x31, 0x41, 
+	0x87, 0x39, 0x1A, 0x43, 0x0B, 0x18, 0xA5, 0x53, 0x1F, 0x39, 
+	0x1A, 0x5F, 0x1F, 0x43, 0xBC, 0x87, 0x6A, 0xDF, 0x6E, 0xD3, 
+	0x22, 0x00, 0xFE, 0x22, 0x98, 0x70, 0x4E, 0x1A, 0x19, 0x29, 
+	0x02, 0x81, 0x81, 0x00, 0x8A, 0x41, 0x56, 0x28, 0x51, 0x9E, 
+	0x5F, 0xD4, 0x9E, 0x0B, 0x3B, 0x98, 0xA3, 0x54, 0xF2, 0x6C, 
+	0x56, 0xD4, 0xAA, 0xE9, 0x69, 0x33, 0x85, 0x24, 0x0C, 0xDA, 
+	0xD4, 0x0C, 0x2D, 0xC4, 0xBF, 0x4F, 0x02, 0x69, 0x38, 0x7C, 
+	0xD4, 0xE6, 0xDC, 0x4C, 0xED, 0xD7, 0x16, 0x11, 0xC3, 0x3E, 
+	0x00, 0xE7, 0xC3, 0x26, 0xC0, 0x51, 0x02, 0xDE, 0xBB, 0x75, 
+	0x9C, 0x6F, 0x56, 0x9C, 0x7A, 0xF3, 0x8E, 0xEF, 0xCF, 0x8A, 
+	0xC5, 0x2B, 0xD2, 0xDA, 0x06, 0x6A, 0x44, 0xC9, 0x73, 0xFE, 
+	0x6E, 0x99, 0x87, 0xF8, 0x5B, 0xBE, 0xF1, 0x7C, 0xE6, 0x65, 
+	0xB5, 0x4F, 0x6C, 0xF0, 0xC9, 0xC5, 0xFF, 0x16, 0xCA, 0x8B, 
+	0x1B, 0x17, 0xE2, 0x58, 0x3D, 0xA2, 0x37, 0xAB, 0x01, 0xBC, 
+	0xBF, 0x40, 0xCE, 0x53, 0x8C, 0x8E, 0xED, 0xEF, 0xEE, 0x59, 
+	0x9D, 0xE0, 0x63, 0xE6, 0x7C, 0x5E, 0xF5, 0x8E, 0x4B, 0xF1, 
+	0x3B, 0xC1, 0x02, 0x81, 0x80, 0x4D, 0x45, 0xF9, 0x40, 0x8C, 
+	0xC5, 0x5B, 0xF4, 0x2A, 0x1A, 0x8A, 0xB4, 0xF2, 0x1C, 0xAC, 
+	0x6B, 0xE9, 0x0C, 0x56, 0x36, 0xB7, 0x4E, 0x72, 0x96, 0xD5, 
+	0xE5, 0x8A, 0xD2, 0xE2, 0xFF, 0xF1, 0xF1, 0x18, 0x13, 0x3D, 
+	0x86, 0x09, 0xB8, 0xD8, 0x76, 0xA7, 0xC9, 0x1C, 0x71, 0x52, 
+	0x94, 0x30, 0x43, 0xE0, 0xF1, 0x78, 0x74, 0xFD, 0x61, 0x1B, 
+	0x4C, 0x09, 0xCC, 0xE6, 0x68, 0x2A, 0x71, 0xAD, 0x1C, 0xDF, 
+	0x43, 0xBC, 0x56, 0xDB, 0xA5, 0xA4, 0xBE, 0x35, 0x70, 0xA4, 
+	0x5E, 0xCF, 0x4F, 0xFC, 0x00, 0x55, 0x99, 0x3A, 0x3D, 0x23, 
+	0xCF, 0x67, 0x5A, 0xF5, 0x22, 0xF8, 0xB5, 0x29, 0xD0, 0x44, 
+	0x11, 0xEB, 0x35, 0x2E, 0x46, 0xBE, 0xFD, 0x8E, 0x18, 0xB2, 
+	0x5F, 0xA8, 0xBF, 0x19, 0x32, 0xA1, 0xF5, 0xDC, 0x03, 0xE6, 
+	0x7C, 0x9A, 0x1F, 0x0C, 0x7C, 0xA9, 0xB0, 0x0E, 0x21, 0x37, 
+	0x3B, 0xF1, 0xB0
+};
+static const int sizeof_server_key_der_2048 = sizeof(server_key_der_2048);
+
+/* ./certs/server-cert.der, 2048-bit */
+static const unsigned char server_cert_der_2048[] =
+{
+	0x30, 0x82, 0x04, 0x9E, 0x30, 0x82, 0x03, 0x86, 0xA0, 0x03, 
+	0x02, 0x01, 0x02, 0x02, 0x01, 0x01, 0x30, 0x0D, 0x06, 0x09, 
+	0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01, 0x0B, 0x05, 
+	0x00, 0x30, 0x81, 0x94, 0x31, 0x0B, 0x30, 0x09, 0x06, 0x03, 
+	0x55, 0x04, 0x06, 0x13, 0x02, 0x55, 0x53, 0x31, 0x10, 0x30, 
+	0x0E, 0x06, 0x03, 0x55, 0x04, 0x08, 0x0C, 0x07, 0x4D, 0x6F, 
+	0x6E, 0x74, 0x61, 0x6E, 0x61, 0x31, 0x10, 0x30, 0x0E, 0x06, 
+	0x03, 0x55, 0x04, 0x07, 0x0C, 0x07, 0x42, 0x6F, 0x7A, 0x65, 
+	0x6D, 0x61, 0x6E, 0x31, 0x11, 0x30, 0x0F, 0x06, 0x03, 0x55, 
+	0x04, 0x0A, 0x0C, 0x08, 0x53, 0x61, 0x77, 0x74, 0x6F, 0x6F, 
+	0x74, 0x68, 0x31, 0x13, 0x30, 0x11, 0x06, 0x03, 0x55, 0x04, 
+	0x0B, 0x0C, 0x0A, 0x43, 0x6F, 0x6E, 0x73, 0x75, 0x6C, 0x74, 
+	0x69, 0x6E, 0x67, 0x31, 0x18, 0x30, 0x16, 0x06, 0x03, 0x55, 
+	0x04, 0x03, 0x0C, 0x0F, 0x77, 0x77, 0x77, 0x2E, 0x77, 0x6F, 
+	0x6C, 0x66, 0x73, 0x73, 0x6C, 0x2E, 0x63, 0x6F, 0x6D, 0x31, 
+	0x1F, 0x30, 0x1D, 0x06, 0x09, 0x2A, 0x86, 0x48, 0x86, 0xF7, 
+	0x0D, 0x01, 0x09, 0x01, 0x16, 0x10, 0x69, 0x6E, 0x66, 0x6F, 
+	0x40, 0x77, 0x6F, 0x6C, 0x66, 0x73, 0x73, 0x6C, 0x2E, 0x63, 
+	0x6F, 0x6D, 0x30, 0x1E, 0x17, 0x0D, 0x31, 0x35, 0x30, 0x35, 
+	0x30, 0x37, 0x31, 0x38, 0x32, 0x31, 0x30, 0x31, 0x5A, 0x17, 
+	0x0D, 0x31, 0x38, 0x30, 0x31, 0x33, 0x31, 0x31, 0x38, 0x32, 
+	0x31, 0x30, 0x31, 0x5A, 0x30, 0x81, 0x90, 0x31, 0x0B, 0x30, 
+	0x09, 0x06, 0x03, 0x55, 0x04, 0x06, 0x13, 0x02, 0x55, 0x53, 
+	0x31, 0x10, 0x30, 0x0E, 0x06, 0x03, 0x55, 0x04, 0x08, 0x0C, 
+	0x07, 0x4D, 0x6F, 0x6E, 0x74, 0x61, 0x6E, 0x61, 0x31, 0x10, 
+	0x30, 0x0E, 0x06, 0x03, 0x55, 0x04, 0x07, 0x0C, 0x07, 0x42, 
+	0x6F, 0x7A, 0x65, 0x6D, 0x61, 0x6E, 0x31, 0x10, 0x30, 0x0E, 
+	0x06, 0x03, 0x55, 0x04, 0x0A, 0x0C, 0x07, 0x77, 0x6F, 0x6C, 
+	0x66, 0x53, 0x53, 0x4C, 0x31, 0x10, 0x30, 0x0E, 0x06, 0x03, 
+	0x55, 0x04, 0x0B, 0x0C, 0x07, 0x53, 0x75, 0x70, 0x70, 0x6F, 
+	0x72, 0x74, 0x31, 0x18, 0x30, 0x16, 0x06, 0x03, 0x55, 0x04, 
+	0x03, 0x0C, 0x0F, 0x77, 0x77, 0x77, 0x2E, 0x77, 0x6F, 0x6C, 
+	0x66, 0x73, 0x73, 0x6C, 0x2E, 0x63, 0x6F, 0x6D, 0x31, 0x1F, 
+	0x30, 0x1D, 0x06, 0x09, 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 
+	0x01, 0x09, 0x01, 0x16, 0x10, 0x69, 0x6E, 0x66, 0x6F, 0x40, 
+	0x77, 0x6F, 0x6C, 0x66, 0x73, 0x73, 0x6C, 0x2E, 0x63, 0x6F, 
+	0x6D, 0x30, 0x82, 0x01, 0x22, 0x30, 0x0D, 0x06, 0x09, 0x2A, 
+	0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01, 0x01, 0x05, 0x00, 
+	0x03, 0x82, 0x01, 0x0F, 0x00, 0x30, 0x82, 0x01, 0x0A, 0x02, 
+	0x82, 0x01, 0x01, 0x00, 0xC0, 0x95, 0x08, 0xE1, 0x57, 0x41, 
+	0xF2, 0x71, 0x6D, 0xB7, 0xD2, 0x45, 0x41, 0x27, 0x01, 0x65, 
+	0xC6, 0x45, 0xAE, 0xF2, 0xBC, 0x24, 0x30, 0xB8, 0x95, 0xCE, 
+	0x2F, 0x4E, 0xD6, 0xF6, 0x1C, 0x88, 0xBC, 0x7C, 0x9F, 0xFB, 
+	0xA8, 0x67, 0x7F, 0xFE, 0x5C, 0x9C, 0x51, 0x75, 0xF7, 0x8A, 
+	0xCA, 0x07, 0xE7, 0x35, 0x2F, 0x8F, 0xE1, 0xBD, 0x7B, 0xC0, 
+	0x2F, 0x7C, 0xAB, 0x64, 0xA8, 0x17, 0xFC, 0xCA, 0x5D, 0x7B, 
+	0xBA, 0xE0, 0x21, 0xE5, 0x72, 0x2E, 0x6F, 0x2E, 0x86, 0xD8, 
+	0x95, 0x73, 0xDA, 0xAC, 0x1B, 0x53, 0xB9, 0x5F, 0x3F, 0xD7, 
+	0x19, 0x0D, 0x25, 0x4F, 0xE1, 0x63, 0x63, 0x51, 0x8B, 0x0B, 
+	0x64, 0x3F, 0xAD, 0x43, 0xB8, 0xA5, 0x1C, 0x5C, 0x34, 0xB3, 
+	0xAE, 0x00, 0xA0, 0x63, 0xC5, 0xF6, 0x7F, 0x0B, 0x59, 0x68, 
+	0x78, 0x73, 0xA6, 0x8C, 0x18, 0xA9, 0x02, 0x6D, 0xAF, 0xC3, 
+	0x19, 0x01, 0x2E, 0xB8, 0x10, 0xE3, 0xC6, 0xCC, 0x40, 0xB4, 
+	0x69, 0xA3, 0x46, 0x33, 0x69, 0x87, 0x6E, 0xC4, 0xBB, 0x17, 
+	0xA6, 0xF3, 0xE8, 0xDD, 0xAD, 0x73, 0xBC, 0x7B, 0x2F, 0x21, 
+	0xB5, 0xFD, 0x66, 0x51, 0x0C, 0xBD, 0x54, 0xB3, 0xE1, 0x6D, 
+	0x5F, 0x1C, 0xBC, 0x23, 0x73, 0xD1, 0x09, 0x03, 0x89, 0x14, 
+	0xD2, 0x10, 0xB9, 0x64, 0xC3, 0x2A, 0xD0, 0xA1, 0x96, 0x4A, 
+	0xBC, 0xE1, 0xD4, 0x1A, 0x5B, 0xC7, 0xA0, 0xC0, 0xC1, 0x63, 
+	0x78, 0x0F, 0x44, 0x37, 0x30, 0x32, 0x96, 0x80, 0x32, 0x23, 
+	0x95, 0xA1, 0x77, 0xBA, 0x13, 0xD2, 0x97, 0x73, 0xE2, 0x5D, 
+	0x25, 0xC9, 0x6A, 0x0D, 0xC3, 0x39, 0x60, 0xA4, 0xB4, 0xB0, 
+	0x69, 0x42, 0x42, 0x09, 0xE9, 0xD8, 0x08, 0xBC, 0x33, 0x20, 
+	0xB3, 0x58, 0x22, 0xA7, 0xAA, 0xEB, 0xC4, 0xE1, 0xE6, 0x61, 
+	0x83, 0xC5, 0xD2, 0x96, 0xDF, 0xD9, 0xD0, 0x4F, 0xAD, 0xD7, 
+	0x02, 0x03, 0x01, 0x00, 0x01, 0xA3, 0x81, 0xFC, 0x30, 0x81, 
+	0xF9, 0x30, 0x1D, 0x06, 0x03, 0x55, 0x1D, 0x0E, 0x04, 0x16, 
+	0x04, 0x14, 0xB3, 0x11, 0x32, 0xC9, 0x92, 0x98, 0x84, 0xE2, 
+	0xC9, 0xF8, 0xD0, 0x3B, 0x6E, 0x03, 0x42, 0xCA, 0x1F, 0x0E, 
+	0x8E, 0x3C, 0x30, 0x81, 0xC9, 0x06, 0x03, 0x55, 0x1D, 0x23, 
+	0x04, 0x81, 0xC1, 0x30, 0x81, 0xBE, 0x80, 0x14, 0x27, 0x8E, 
+	0x67, 0x11, 0x74, 0xC3, 0x26, 0x1D, 0x3F, 0xED, 0x33, 0x63, 
+	0xB3, 0xA4, 0xD8, 0x1D, 0x30, 0xE5, 0xE8, 0xD5, 0xA1, 0x81, 
+	0x9A, 0xA4, 0x81, 0x97, 0x30, 0x81, 0x94, 0x31, 0x0B, 0x30, 
+	0x09, 0x06, 0x03, 0x55, 0x04, 0x06, 0x13, 0x02, 0x55, 0x53, 
+	0x31, 0x10, 0x30, 0x0E, 0x06, 0x03, 0x55, 0x04, 0x08, 0x0C, 
+	0x07, 0x4D, 0x6F, 0x6E, 0x74, 0x61, 0x6E, 0x61, 0x31, 0x10, 
+	0x30, 0x0E, 0x06, 0x03, 0x55, 0x04, 0x07, 0x0C, 0x07, 0x42, 
+	0x6F, 0x7A, 0x65, 0x6D, 0x61, 0x6E, 0x31, 0x11, 0x30, 0x0F, 
+	0x06, 0x03, 0x55, 0x04, 0x0A, 0x0C, 0x08, 0x53, 0x61, 0x77, 
+	0x74, 0x6F, 0x6F, 0x74, 0x68, 0x31, 0x13, 0x30, 0x11, 0x06, 
+	0x03, 0x55, 0x04, 0x0B, 0x0C, 0x0A, 0x43, 0x6F, 0x6E, 0x73, 
+	0x75, 0x6C, 0x74, 0x69, 0x6E, 0x67, 0x31, 0x18, 0x30, 0x16, 
+	0x06, 0x03, 0x55, 0x04, 0x03, 0x0C, 0x0F, 0x77, 0x77, 0x77, 
+	0x2E, 0x77, 0x6F, 0x6C, 0x66, 0x73, 0x73, 0x6C, 0x2E, 0x63, 
+	0x6F, 0x6D, 0x31, 0x1F, 0x30, 0x1D, 0x06, 0x09, 0x2A, 0x86, 
+	0x48, 0x86, 0xF7, 0x0D, 0x01, 0x09, 0x01, 0x16, 0x10, 0x69, 
+	0x6E, 0x66, 0x6F, 0x40, 0x77, 0x6F, 0x6C, 0x66, 0x73, 0x73, 
+	0x6C, 0x2E, 0x63, 0x6F, 0x6D, 0x82, 0x09, 0x00, 0xD9, 0x80, 
+	0x3A, 0xC3, 0xD2, 0xF4, 0xDA, 0x37, 0x30, 0x0C, 0x06, 0x03, 
+	0x55, 0x1D, 0x13, 0x04, 0x05, 0x30, 0x03, 0x01, 0x01, 0xFF, 
+	0x30, 0x0D, 0x06, 0x09, 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 
+	0x01, 0x01, 0x0B, 0x05, 0x00, 0x03, 0x82, 0x01, 0x01, 0x00, 
+	0x67, 0xC0, 0x2C, 0xA9, 0x43, 0x47, 0xE7, 0x11, 0x14, 0x77, 
+	0xAE, 0xCC, 0xD8, 0xE0, 0x6B, 0x23, 0x82, 0x91, 0x63, 0xE8, 
+	0xA8, 0x0D, 0x21, 0xC5, 0xC8, 0x47, 0x97, 0x2F, 0xD5, 0xF3, 
+	0x86, 0xFB, 0x6C, 0xCE, 0x25, 0xF9, 0x7C, 0x78, 0xC8, 0x3A, 
+	0x22, 0x68, 0xF2, 0x16, 0x1E, 0xD2, 0xD2, 0x3F, 0x24, 0x04, 
+	0x87, 0xF2, 0xB7, 0xC1, 0x62, 0x63, 0xBA, 0xC5, 0xFA, 0xAE, 
+	0xD2, 0x20, 0x81, 0x1A, 0xD2, 0x0C, 0xAE, 0x26, 0x6B, 0x1B, 
+	0x2B, 0x10, 0xD3, 0xE1, 0x9A, 0x4E, 0x64, 0x6C, 0x97, 0xDB, 
+	0x36, 0xA8, 0x8F, 0xF8, 0x05, 0x63, 0xBF, 0xBA, 0x0D, 0x88, 
+	0x0B, 0x87, 0x46, 0xC9, 0xE4, 0x64, 0xE3, 0xD7, 0xBD, 0xB8, 
+	0x2D, 0xD5, 0xC1, 0xC3, 0xC4, 0xDB, 0x55, 0x68, 0xDC, 0xA3, 
+	0x7A, 0x40, 0xB9, 0xA9, 0xF6, 0x04, 0x4A, 0x22, 0xCF, 0x98, 
+	0x76, 0x1C, 0xE4, 0xA3, 0xFF, 0x79, 0x19, 0x96, 0x57, 0x63, 
+	0x07, 0x6F, 0xF6, 0x32, 0x77, 0x16, 0x50, 0x9B, 0xE3, 0x34, 
+	0x18, 0xD4, 0xEB, 0xBE, 0xFD, 0xB6, 0x6F, 0xE3, 0xC7, 0xF6, 
+	0x85, 0xBF, 0xAC, 0x32, 0xAD, 0x98, 0x57, 0xBE, 0x13, 0x92, 
+	0x44, 0x10, 0xA5, 0xF3, 0xAE, 0xE2, 0x66, 0xDA, 0x44, 0xA9, 
+	0x94, 0x71, 0x3F, 0xD0, 0x2F, 0x20, 0x59, 0x87, 0xE4, 0x5A, 
+	0x40, 0xEE, 0xD2, 0xE4, 0x0C, 0xCE, 0x25, 0x94, 0xDC, 0x0F, 
+	0xFE, 0x38, 0xE0, 0x41, 0x52, 0x34, 0x5C, 0xBB, 0xC3, 0xDB, 
+	0xC1, 0x5F, 0x76, 0xC3, 0x5D, 0x0E, 0x32, 0x69, 0x2B, 0x9D, 
+	0x01, 0xED, 0x50, 0x1B, 0x4F, 0x77, 0xA9, 0xA9, 0xD8, 0x71, 
+	0x30, 0xCB, 0x2E, 0x2C, 0x70, 0x00, 0xAB, 0x78, 0x4B, 0xD7, 
+	0x15, 0xD9, 0x17, 0xF8, 0x64, 0xB2, 0xF7, 0x3A, 0xDA, 0xE1, 
+	0x0B, 0x8B, 0x0A, 0xE1, 0x4E, 0xB1, 0x03, 0x46, 0x14, 0xCA, 
+	0x94, 0xE3, 0x44, 0x77, 0xD7, 0x59
+};
+static const int sizeof_server_cert_der_2048 = sizeof(server_cert_der_2048);
+
+#endif /* USE_CERT_BUFFERS_1024 */
+
+/* dh1024 p */
+static const unsigned char dh_p[] =
+{
+    0xE6, 0x96, 0x9D, 0x3D, 0x49, 0x5B, 0xE3, 0x2C, 0x7C, 0xF1, 0x80, 0xC3,
+    0xBD, 0xD4, 0x79, 0x8E, 0x91, 0xB7, 0x81, 0x82, 0x51, 0xBB, 0x05, 0x5E,
+    0x2A, 0x20, 0x64, 0x90, 0x4A, 0x79, 0xA7, 0x70, 0xFA, 0x15, 0xA2, 0x59,
+    0xCB, 0xD5, 0x23, 0xA6, 0xA6, 0xEF, 0x09, 0xC4, 0x30, 0x48, 0xD5, 0xA2,
+    0x2F, 0x97, 0x1F, 0x3C, 0x20, 0x12, 0x9B, 0x48, 0x00, 0x0E, 0x6E, 0xDD,
+    0x06, 0x1C, 0xBC, 0x05, 0x3E, 0x37, 0x1D, 0x79, 0x4E, 0x53, 0x27, 0xDF,
+    0x61, 0x1E, 0xBB, 0xBE, 0x1B, 0xAC, 0x9B, 0x5C, 0x60, 0x44, 0xCF, 0x02,
+    0x3D, 0x76, 0xE0, 0x5E, 0xEA, 0x9B, 0xAD, 0x99, 0x1B, 0x13, 0xA6, 0x3C,
+    0x97, 0x4E, 0x9E, 0xF1, 0x83, 0x9E, 0xB5, 0xDB, 0x12, 0x51, 0x36, 0xF7,
+    0x26, 0x2E, 0x56, 0xA8, 0x87, 0x15, 0x38, 0xDF, 0xD8, 0x23, 0xC6, 0x50,
+    0x50, 0x85, 0xE2, 0x1F, 0x0D, 0xD5, 0xC8, 0x6B,
+};
+
+/* dh1024 g */
+static const unsigned char dh_g[] =
+{
+  0x02,
+};
+
+
+#endif /* WOLFSSL_CERTS_TEST_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/crl.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/crl.h
new file mode 100644
index 0000000..05c039a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/crl.h
@@ -0,0 +1,51 @@
+/* crl.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifndef WOLFSSL_CRL_H
+#define WOLFSSL_CRL_H
+
+
+#ifdef HAVE_CRL
+
+#include 
+#include 
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+typedef struct WOLFSSL_CRL WOLFSSL_CRL;
+
+WOLFSSL_LOCAL int  InitCRL(WOLFSSL_CRL*, WOLFSSL_CERT_MANAGER*);
+WOLFSSL_LOCAL void FreeCRL(WOLFSSL_CRL*, int dynamic);
+
+WOLFSSL_LOCAL int  LoadCRL(WOLFSSL_CRL* crl, const char* path, int type, int mon);
+WOLFSSL_LOCAL int  BufferLoadCRL(WOLFSSL_CRL*, const byte*, long, int);
+WOLFSSL_LOCAL int  CheckCertCRL(WOLFSSL_CRL*, DecodedCert*);
+
+
+#ifdef __cplusplus
+    }  /* extern "C" */
+#endif
+
+#endif /* HAVE_CRL */
+#endif /* WOLFSSL_CRL_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/error-ssl.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/error-ssl.h
new file mode 100644
index 0000000..f151c3f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/error-ssl.h
@@ -0,0 +1,169 @@
+/* error-ssl.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifndef WOLFSSL_ERROR_H
+#define WOLFSSL_ERROR_H
+
+#include    /* pull in wolfCrypt errors */
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+enum wolfSSL_ErrorCodes {
+    INPUT_CASE_ERROR        = -301,        /* process input state error */
+    PREFIX_ERROR            = -302,        /* bad index to key rounds  */
+    MEMORY_ERROR            = -303,        /* out of memory            */
+    VERIFY_FINISHED_ERROR   = -304,        /* verify problem on finished */
+    VERIFY_MAC_ERROR        = -305,        /* verify mac problem       */
+    PARSE_ERROR             = -306,        /* parse error on header    */
+    UNKNOWN_HANDSHAKE_TYPE  = -307,        /* weird handshake type     */
+    SOCKET_ERROR_E          = -308,        /* error state on socket    */
+    SOCKET_NODATA           = -309,        /* expected data, not there */
+    INCOMPLETE_DATA         = -310,        /* don't have enough data to
+                                              complete task            */
+    UNKNOWN_RECORD_TYPE     = -311,        /* unknown type in record hdr */
+    DECRYPT_ERROR           = -312,        /* error during decryption  */
+    FATAL_ERROR             = -313,        /* recvd alert fatal error  */
+    ENCRYPT_ERROR           = -314,        /* error during encryption  */
+    FREAD_ERROR             = -315,        /* fread problem            */
+    NO_PEER_KEY             = -316,        /* need peer's key          */
+    NO_PRIVATE_KEY          = -317,        /* need the private key     */
+    RSA_PRIVATE_ERROR       = -318,        /* error during rsa priv op */
+    NO_DH_PARAMS            = -319,        /* server missing DH params */
+    BUILD_MSG_ERROR         = -320,        /* build message failure    */
+
+    BAD_HELLO               = -321,        /* client hello malformed   */
+    DOMAIN_NAME_MISMATCH    = -322,        /* peer subject name mismatch */
+    WANT_READ               = -323,        /* want read, call again    */
+    NOT_READY_ERROR         = -324,        /* handshake layer not ready */
+    PMS_VERSION_ERROR       = -325,        /* pre m secret version error */
+    VERSION_ERROR           = -326,        /* record layer version error */
+    WANT_WRITE              = -327,        /* want write, call again   */
+    BUFFER_ERROR            = -328,        /* malformed buffer input   */
+    VERIFY_CERT_ERROR       = -329,        /* verify cert error        */
+    VERIFY_SIGN_ERROR       = -330,        /* verify sign error        */
+    CLIENT_ID_ERROR         = -331,        /* psk client identity error  */
+    SERVER_HINT_ERROR       = -332,        /* psk server hint error  */
+    PSK_KEY_ERROR           = -333,        /* psk key error  */
+    ZLIB_INIT_ERROR         = -334,        /* zlib init error  */
+    ZLIB_COMPRESS_ERROR     = -335,        /* zlib compression error  */
+    ZLIB_DECOMPRESS_ERROR   = -336,        /* zlib decompression error  */
+
+    GETTIME_ERROR           = -337,        /* gettimeofday failed ??? */
+    GETITIMER_ERROR         = -338,        /* getitimer failed ??? */
+    SIGACT_ERROR            = -339,        /* sigaction failed ??? */
+    SETITIMER_ERROR         = -340,        /* setitimer failed ??? */
+    LENGTH_ERROR            = -341,        /* record layer length error */
+    PEER_KEY_ERROR          = -342,        /* can't decode peer key */
+    ZERO_RETURN             = -343,        /* peer sent close notify */
+    SIDE_ERROR              = -344,        /* wrong client/server type */
+    NO_PEER_CERT            = -345,        /* peer didn't send key */
+    NTRU_KEY_ERROR          = -346,        /* NTRU key error  */
+    NTRU_DRBG_ERROR         = -347,        /* NTRU drbg error  */
+    NTRU_ENCRYPT_ERROR      = -348,        /* NTRU encrypt error  */
+    NTRU_DECRYPT_ERROR      = -349,        /* NTRU decrypt error  */
+    ECC_CURVETYPE_ERROR     = -350,        /* Bad ECC Curve Type */
+    ECC_CURVE_ERROR         = -351,        /* Bad ECC Curve */
+    ECC_PEERKEY_ERROR       = -352,        /* Bad Peer ECC Key */
+    ECC_MAKEKEY_ERROR       = -353,        /* Bad Make ECC Key */
+    ECC_EXPORT_ERROR        = -354,        /* Bad ECC Export Key */
+    ECC_SHARED_ERROR        = -355,        /* Bad ECC Shared Secret */
+    NOT_CA_ERROR            = -357,        /* Not a CA cert error */
+    BAD_PATH_ERROR          = -358,        /* Bad path for opendir */
+    BAD_CERT_MANAGER_ERROR  = -359,        /* Bad Cert Manager */
+    OCSP_CERT_REVOKED       = -360,        /* OCSP Certificate revoked */
+    CRL_CERT_REVOKED        = -361,        /* CRL Certificate revoked */
+    CRL_MISSING             = -362,        /* CRL Not loaded */
+    MONITOR_RUNNING_E       = -363,        /* CRL Monitor already running */
+    THREAD_CREATE_E         = -364,        /* Thread Create Error */
+    OCSP_NEED_URL           = -365,        /* OCSP need an URL for lookup */
+    OCSP_CERT_UNKNOWN       = -366,        /* OCSP responder doesn't know */
+    OCSP_LOOKUP_FAIL        = -367,        /* OCSP lookup not successful */
+    MAX_CHAIN_ERROR         = -368,        /* max chain depth exceeded */
+    COOKIE_ERROR            = -369,        /* dtls cookie error */
+    SEQUENCE_ERROR          = -370,        /* dtls sequence error */
+    SUITES_ERROR            = -371,        /* suites pointer error */
+    SSL_NO_PEM_HEADER       = -372,        /* no PEM header found */
+    OUT_OF_ORDER_E          = -373,        /* out of order message */
+    BAD_KEA_TYPE_E          = -374,        /* bad KEA type found */
+    SANITY_CIPHER_E         = -375,        /* sanity check on cipher error */
+    RECV_OVERFLOW_E         = -376,        /* RXCB returned more than rqed */
+    GEN_COOKIE_E            = -377,        /* Generate Cookie Error */
+    NO_PEER_VERIFY          = -378,        /* Need peer cert verify Error */
+    FWRITE_ERROR            = -379,        /* fwrite problem */
+    CACHE_MATCH_ERROR       = -380,        /* chache hdr match error */
+    UNKNOWN_SNI_HOST_NAME_E = -381,        /* Unrecognized host name Error */
+    UNKNOWN_MAX_FRAG_LEN_E  = -382,        /* Unrecognized max frag len Error */
+    KEYUSE_SIGNATURE_E      = -383,        /* KeyUse digSignature error */
+    KEYUSE_ENCIPHER_E       = -385,        /* KeyUse keyEncipher error */
+    EXTKEYUSE_AUTH_E        = -386,        /* ExtKeyUse server|client_auth */
+    SEND_OOB_READ_E         = -387,        /* Send Cb out of bounds read */
+    SECURE_RENEGOTIATION_E  = -388,        /* Invalid Renegotiation Info */
+    SESSION_TICKET_LEN_E    = -389,        /* Session Ticket too large */
+    SESSION_TICKET_EXPECT_E = -390,        /* Session Ticket missing   */
+    SCR_DIFFERENT_CERT_E    = -391,        /* SCR Different cert error  */
+    SESSION_SECRET_CB_E     = -392,        /* Session secret Cb fcn failure */
+    NO_CHANGE_CIPHER_E      = -393,        /* Finished before change cipher */
+    SANITY_MSG_E            = -394,        /* Sanity check on msg order error */
+    DUPLICATE_MSG_E         = -395,        /* Duplicate message error */
+    SNI_UNSUPPORTED         = -396,        /* SSL 3.0 does not support SNI */
+    SOCKET_PEER_CLOSED_E    = -397,        /* Underlying transport closed */
+
+    BAD_TICKET_KEY_CB_SZ    = -398,        /* Bad session ticket key cb size */
+    BAD_TICKET_MSG_SZ       = -399,        /* Bad session ticket msg size    */
+    BAD_TICKET_ENCRYPT      = -400,        /* Bad user ticket encrypt        */
+
+    DH_KEY_SIZE_E           = -401,        /* DH Key too small */
+
+    /* add strings to SetErrorString !!!!! */
+
+    /* begin negotiation parameter errors */
+    UNSUPPORTED_SUITE       = -500,        /* unsupported cipher suite */
+    MATCH_SUITE_ERROR       = -501         /* can't match cipher suite */
+    /* end negotiation parameter errors only 10 for now */
+    /* add strings to SetErrorString !!!!! */
+
+    /* no error stings go down here, add above negotiation errors !!!! */
+};
+
+
+#ifdef WOLFSSL_CALLBACKS
+    enum {
+        MIN_PARAM_ERR = UNSUPPORTED_SUITE,
+        MAX_PARAM_ERR = MIN_PARAM_ERR - 10
+    };
+#endif
+
+
+WOLFSSL_LOCAL
+void SetErrorString(int err, char* buff);
+
+
+#ifdef __cplusplus
+    }  /* extern "C" */
+#endif
+
+
+#endif /* wolfSSL_ERROR_H */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/include.am
new file mode 100644
index 0000000..a02488f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/include.am
@@ -0,0 +1,25 @@
+# vim:ft=automake
+# All paths should be given relative to the root
+#
+
+include wolfssl/wolfcrypt/include.am
+include wolfssl/openssl/include.am
+
+EXTRA_DIST+= wolfssl/sniffer_error.rc
+
+nobase_include_HEADERS+= \
+                         wolfssl/error-ssl.h \
+                         wolfssl/ssl.h \
+                         wolfssl/sniffer_error.h \
+                         wolfssl/sniffer.h \
+                         wolfssl/callbacks.h \
+                         wolfssl/certs_test.h \
+                         wolfssl/test.h \
+                         wolfssl/version.h \
+                         wolfssl/options.h \
+                         wolfssl/ocsp.h \
+                         wolfssl/crl.h
+
+noinst_HEADERS+= \
+                         wolfssl/internal.h
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/internal.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/internal.h
new file mode 100644
index 0000000..99d3e9a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/internal.h
@@ -0,0 +1,2513 @@
+/* internal.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as wolfSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifndef WOLFSSL_INT_H
+#define WOLFSSL_INT_H
+
+
+#include 
+#include 
+#ifdef HAVE_CRL
+    #include 
+#endif
+#include 
+#ifndef NO_DES3
+    #include 
+#endif
+#ifndef NO_HC128
+    #include 
+#endif
+#ifndef NO_RABBIT
+    #include 
+#endif
+#ifdef HAVE_CHACHA
+    #include 
+#endif
+#ifndef NO_ASN
+    #include 
+#endif
+#ifndef NO_MD5
+    #include 
+#endif
+#ifndef NO_SHA
+    #include 
+#endif
+#ifndef NO_AES
+    #include 
+#endif
+#ifdef HAVE_POLY1305
+    #include 
+#endif
+#ifdef HAVE_CAMELLIA
+    #include 
+#endif
+#include 
+#ifndef NO_HMAC
+    #include 
+#endif
+#ifndef NO_RC4
+    #include 
+#endif
+#ifdef HAVE_ECC
+    #include 
+#endif
+#ifndef NO_SHA256
+    #include 
+#endif
+#ifdef HAVE_OCSP
+    #include 
+#endif
+#ifdef WOLFSSL_SHA512
+    #include 
+#endif
+
+#ifdef HAVE_AESGCM
+    #include 
+#endif
+
+#ifdef WOLFSSL_RIPEMD
+    #include 
+#endif
+
+#include 
+
+#ifdef WOLFSSL_CALLBACKS
+    #include 
+    #include 
+#endif
+
+#ifdef USE_WINDOWS_API
+    #ifdef WOLFSSL_GAME_BUILD
+        #include "system/xtl.h"
+    #else
+        #if defined(_WIN32_WCE) || defined(WIN32_LEAN_AND_MEAN)
+            /* On WinCE winsock2.h must be included before windows.h */
+            #include 
+        #endif
+        #include 
+    #endif
+#elif defined(THREADX)
+    #ifndef SINGLE_THREADED
+        #include "tx_api.h"
+    #endif
+#elif defined(MICRIUM)
+    /* do nothing, just don't pick Unix */
+#elif defined(FREERTOS) || defined(WOLFSSL_SAFERTOS)
+    /* do nothing */
+#elif defined(EBSNET)
+    /* do nothing */
+#elif defined(FREESCALE_MQX)
+    /* do nothing */
+#elif defined(WOLFSSL_MDK_ARM)
+    #if defined(WOLFSSL_MDK5)
+         #include "cmsis_os.h"
+    #else
+        #include 
+    #endif
+#elif defined(MBED)
+#elif defined(WOLFSSL_TIRTOS)
+    /* do nothing */
+#else
+    #ifndef SINGLE_THREADED
+        #define WOLFSSL_PTHREADS
+        #include 
+    #endif
+    #if defined(OPENSSL_EXTRA) || defined(GOAHEAD_WS)
+        #include       /* for close of BIO */
+    #endif
+#endif
+
+
+#ifdef HAVE_LIBZ
+    #include "zlib.h"
+#endif
+
+#ifdef _MSC_VER
+    /* 4996 warning to use MS extensions e.g., strcpy_s instead of strncpy */
+    #pragma warning(disable: 4996)
+#endif
+
+#ifdef NO_AES
+    #if !defined (ALIGN16)
+        #define ALIGN16
+    #endif
+#endif
+
+#ifdef NO_SHA
+    #define SHA_DIGEST_SIZE 20
+#endif
+
+#ifdef NO_SHA256
+    #define SHA256_DIGEST_SIZE 32
+#endif
+
+#ifdef NO_MD5
+    #define MD5_DIGEST_SIZE 16
+#endif
+
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+
+#ifdef USE_WINDOWS_API
+    typedef unsigned int SOCKET_T;
+#else
+    typedef int SOCKET_T;
+#endif
+
+
+typedef byte word24[3];
+
+/* Define or comment out the cipher suites you'd like to be compiled in
+   make sure to use at least one BUILD_SSL_xxx or BUILD_TLS_xxx is defined
+
+   When adding cipher suites, add name to cipher_names, idx to cipher_name_idx
+
+   Now that there is a maximum strength crypto build, the following BUILD_XXX
+   flags need to be divided into two groups selected by WOLFSSL_MAX_STRENGTH.
+   Those that do not use Perfect Forward Security and do not use AEAD ciphers
+   need to be switched off. Allowed suites use (EC)DHE, AES-GCM|CCM, or
+   CHACHA-POLY.
+*/
+
+/* Check that if WOLFSSL_MAX_STRENGTH is set that all the required options are
+ * not turned off. */
+#if defined(WOLFSSL_MAX_STRENGTH) && \
+    ((!defined(HAVE_ECC) && (defined(NO_DH) || defined(NO_RSA))) || \
+     (!defined(HAVE_AESGCM) && !defined(HAVE_AESCCM) && \
+      (!defined(HAVE_POLY1305) || !defined(HAVE_CHACHA))) || \
+     (defined(NO_SHA256) && !defined(WOLFSSL_SHA384)) || \
+     !defined(NO_OLD_TLS))
+
+    #error "You are trying to build max strength with requirements disabled."
+#endif
+
+#ifndef WOLFSSL_MAX_STRENGTH
+
+    #if !defined(NO_RSA) && !defined(NO_RC4)
+        #if !defined(NO_SHA)
+            #define BUILD_SSL_RSA_WITH_RC4_128_SHA
+        #endif
+        #if !defined(NO_MD5)
+            #define BUILD_SSL_RSA_WITH_RC4_128_MD5
+        #endif
+        #if !defined(NO_TLS) && defined(HAVE_NTRU) && !defined(NO_SHA)
+            #define BUILD_TLS_NTRU_RSA_WITH_RC4_128_SHA
+        #endif
+    #endif
+
+    #if !defined(NO_RSA) && !defined(NO_DES3)
+        #if !defined(NO_SHA)
+            #define BUILD_SSL_RSA_WITH_3DES_EDE_CBC_SHA
+            #if !defined(NO_TLS) && defined(HAVE_NTRU)
+                    #define BUILD_TLS_NTRU_RSA_WITH_3DES_EDE_CBC_SHA
+            #endif
+        #endif
+    #endif
+
+    #if !defined(NO_RSA) && !defined(NO_AES) && !defined(NO_TLS)
+        #if !defined(NO_SHA)
+            #define BUILD_TLS_RSA_WITH_AES_128_CBC_SHA
+            #define BUILD_TLS_RSA_WITH_AES_256_CBC_SHA
+            #if defined(HAVE_NTRU)
+                    #define BUILD_TLS_NTRU_RSA_WITH_AES_128_CBC_SHA
+                    #define BUILD_TLS_NTRU_RSA_WITH_AES_256_CBC_SHA
+            #endif
+        #endif
+        #if !defined (NO_SHA256)
+            #define BUILD_TLS_RSA_WITH_AES_128_CBC_SHA256
+            #define BUILD_TLS_RSA_WITH_AES_256_CBC_SHA256
+        #endif
+        #if defined (HAVE_AESGCM)
+            #define BUILD_TLS_RSA_WITH_AES_128_GCM_SHA256
+            #if defined (WOLFSSL_SHA384)
+                #define BUILD_TLS_RSA_WITH_AES_256_GCM_SHA384
+            #endif
+        #endif
+        #if defined (HAVE_AESCCM)
+            #define BUILD_TLS_RSA_WITH_AES_128_CCM_8
+            #define BUILD_TLS_RSA_WITH_AES_256_CCM_8
+        #endif
+        #if defined(HAVE_BLAKE2)
+            #define BUILD_TLS_RSA_WITH_AES_128_CBC_B2B256
+            #define BUILD_TLS_RSA_WITH_AES_256_CBC_B2B256
+        #endif
+    #endif
+
+    #if defined(HAVE_CAMELLIA) && !defined(NO_TLS)
+        #ifndef NO_RSA
+          #if !defined(NO_SHA)
+            #define BUILD_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA
+            #define BUILD_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA
+          #endif
+            #ifndef NO_SHA256
+                #define BUILD_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256
+                #define BUILD_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256
+            #endif
+            #if !defined(NO_DH)
+              #if !defined(NO_SHA)
+                #define BUILD_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA
+                #define BUILD_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA
+              #endif
+                #ifndef NO_SHA256
+                    #define BUILD_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
+                    #define BUILD_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256
+                #endif
+            #endif
+        #endif
+    #endif
+
+    #if !defined(NO_PSK) && !defined(NO_AES) && !defined(NO_TLS)
+        #if !defined(NO_SHA)
+            #define BUILD_TLS_PSK_WITH_AES_128_CBC_SHA
+            #define BUILD_TLS_PSK_WITH_AES_256_CBC_SHA
+        #endif
+        #ifndef NO_SHA256
+            #define BUILD_TLS_PSK_WITH_AES_128_CBC_SHA256
+            #ifdef HAVE_AESGCM
+                #define BUILD_TLS_PSK_WITH_AES_128_GCM_SHA256
+            #endif
+            #ifdef HAVE_AESCCM
+                #define BUILD_TLS_PSK_WITH_AES_128_CCM_8
+                #define BUILD_TLS_PSK_WITH_AES_256_CCM_8
+                #define BUILD_TLS_PSK_WITH_AES_128_CCM
+                #define BUILD_TLS_PSK_WITH_AES_256_CCM
+            #endif
+        #endif
+        #ifdef WOLFSSL_SHA384
+            #define BUILD_TLS_PSK_WITH_AES_256_CBC_SHA384
+            #ifdef HAVE_AESGCM
+                #define BUILD_TLS_PSK_WITH_AES_256_GCM_SHA384
+            #endif
+        #endif
+    #endif
+
+    #if !defined(NO_TLS) && defined(HAVE_NULL_CIPHER)
+        #if !defined(NO_RSA)
+            #if !defined(NO_SHA)
+                #define BUILD_TLS_RSA_WITH_NULL_SHA
+            #endif
+            #ifndef NO_SHA256
+                #define BUILD_TLS_RSA_WITH_NULL_SHA256
+            #endif
+        #endif
+        #if !defined(NO_PSK)
+            #if !defined(NO_SHA)
+                #define BUILD_TLS_PSK_WITH_NULL_SHA
+            #endif
+            #ifndef NO_SHA256
+                #define BUILD_TLS_PSK_WITH_NULL_SHA256
+            #endif
+            #ifdef WOLFSSL_SHA384
+                #define BUILD_TLS_PSK_WITH_NULL_SHA384
+            #endif
+        #endif
+    #endif
+
+    #if !defined(NO_HC128) && !defined(NO_RSA) && !defined(NO_TLS)
+        #define BUILD_TLS_RSA_WITH_HC_128_MD5
+        #if !defined(NO_SHA)
+            #define BUILD_TLS_RSA_WITH_HC_128_SHA
+        #endif
+        #if defined(HAVE_BLAKE2)
+            #define BUILD_TLS_RSA_WITH_HC_128_B2B256
+        #endif
+    #endif
+
+    #if !defined(NO_RABBIT) && !defined(NO_TLS) && !defined(NO_RSA)
+        #if !defined(NO_SHA)
+            #define BUILD_TLS_RSA_WITH_RABBIT_SHA
+        #endif
+    #endif
+
+    #if !defined(NO_DH) && !defined(NO_AES) && !defined(NO_TLS) && \
+        !defined(NO_RSA)
+
+        #if !defined(NO_SHA)
+            #define BUILD_TLS_DHE_RSA_WITH_AES_128_CBC_SHA
+            #define BUILD_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
+        #endif
+        #if !defined(NO_SHA256)
+            #define BUILD_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256
+            #define BUILD_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
+        #endif
+    #endif
+
+    #if defined(HAVE_ANON) && !defined(NO_TLS) && !defined(NO_DH) && \
+        !defined(NO_AES) && !defined(NO_SHA)
+        #define BUILD_TLS_DH_anon_WITH_AES_128_CBC_SHA
+    #endif
+
+    #if !defined(NO_DH) && !defined(NO_PSK) && !defined(NO_TLS)
+        #ifndef NO_SHA256
+            #define BUILD_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256
+            #ifdef HAVE_NULL_CIPHER
+                #define BUILD_TLS_DHE_PSK_WITH_NULL_SHA256
+            #endif
+        #endif
+        #ifdef WOLFSSL_SHA384
+            #define BUILD_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384
+            #ifdef HAVE_NULL_CIPHER
+                #define BUILD_TLS_DHE_PSK_WITH_NULL_SHA384
+            #endif
+        #endif
+    #endif
+
+    #if defined(HAVE_ECC) && !defined(NO_TLS)
+        #if !defined(NO_AES)
+            #if !defined(NO_SHA)
+                #if !defined(NO_RSA)
+                    #define BUILD_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA
+                    #define BUILD_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
+                    #define BUILD_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA
+                    #define BUILD_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA
+                #endif
+
+                #define BUILD_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
+                #define BUILD_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
+
+                #define BUILD_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA
+                #define BUILD_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA
+            #endif /* NO_SHA */
+            #ifndef NO_SHA256
+                #if !defined(NO_RSA)
+                    #define BUILD_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
+                    #define BUILD_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256
+                #endif
+                #define BUILD_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
+                #define BUILD_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256
+            #endif
+
+            #ifdef WOLFSSL_SHA384
+                #if !defined(NO_RSA)
+                    #define BUILD_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384
+                    #define BUILD_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384
+                #endif
+                #define BUILD_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384
+                #define BUILD_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384
+            #endif
+
+            #if defined (HAVE_AESGCM)
+                #if !defined(NO_RSA)
+                    #define BUILD_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256
+                    #if defined(WOLFSSL_SHA384)
+                        #define BUILD_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384
+                    #endif
+                #endif
+
+                #define BUILD_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256
+
+                #if defined(WOLFSSL_SHA384)
+                    #define BUILD_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384
+                #endif
+            #endif
+        #endif /* NO_AES */
+        #if !defined(NO_RC4)
+            #if !defined(NO_SHA)
+                #if !defined(NO_RSA)
+                    #define BUILD_TLS_ECDHE_RSA_WITH_RC4_128_SHA
+                    #define BUILD_TLS_ECDH_RSA_WITH_RC4_128_SHA
+                #endif
+
+                #define BUILD_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA
+                #define BUILD_TLS_ECDH_ECDSA_WITH_RC4_128_SHA
+            #endif
+        #endif
+        #if !defined(NO_DES3)
+            #ifndef NO_SHA
+                #if !defined(NO_RSA)
+                    #define BUILD_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA
+                    #define BUILD_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA
+                #endif
+
+                #define BUILD_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA
+                #define BUILD_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA
+            #endif /* NO_SHA */
+        #endif
+    #endif
+
+#endif /* !WOLFSSL_MAX_STRENGTH */
+
+#if !defined(NO_DH) && !defined(NO_AES) && !defined(NO_TLS) && \
+    !defined(NO_RSA) && defined(HAVE_AESGCM)
+
+    #ifndef NO_SHA256
+        #define BUILD_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
+    #endif
+
+    #ifdef WOLFSSL_SHA384
+        #define BUILD_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
+    #endif
+#endif
+
+#if !defined(NO_DH) && !defined(NO_PSK) && !defined(NO_TLS)
+    #ifndef NO_SHA256
+        #ifdef HAVE_AESGCM
+            #define BUILD_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256
+        #endif
+        #ifdef HAVE_AESCCM
+            #define BUILD_TLS_DHE_PSK_WITH_AES_128_CCM
+            #define BUILD_TLS_DHE_PSK_WITH_AES_256_CCM
+        #endif
+    #endif
+    #if defined(WOLFSSL_SHA384) && defined(HAVE_AESGCM)
+        #define BUILD_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384
+    #endif
+#endif
+
+#if defined(HAVE_ECC) && !defined(NO_TLS) && !defined(NO_AES)
+    #ifdef HAVE_AESGCM
+        #ifndef NO_SHA256
+            #define BUILD_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
+            #ifndef NO_RSA
+                #define BUILD_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
+            #endif
+        #endif
+        #ifdef WOLFSSL_SHA384
+            #define BUILD_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
+            #ifndef NO_RSA
+                #define BUILD_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
+            #endif
+        #endif
+    #endif
+    #if defined(HAVE_AESCCM) && !defined(NO_SHA256)
+        #define BUILD_TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8
+        #define BUILD_TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8
+    #endif
+#endif
+
+#if defined(HAVE_CHACHA) && defined(HAVE_POLY1305) && !defined(NO_SHA256)
+    #ifdef HAVE_ECC
+        #define BUILD_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256
+        #ifndef NO_RSA
+            #define BUILD_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256
+        #endif
+    #endif
+    #if !defined(NO_DH) && !defined(NO_RSA)
+        #define BUILD_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256
+    #endif
+#endif
+
+
+#if defined(BUILD_SSL_RSA_WITH_RC4_128_SHA) || \
+    defined(BUILD_SSL_RSA_WITH_RC4_128_MD5)
+    #define BUILD_ARC4
+#endif
+
+#if defined(BUILD_SSL_RSA_WITH_3DES_EDE_CBC_SHA)
+    #define BUILD_DES3
+#endif
+
+#if defined(BUILD_TLS_RSA_WITH_AES_128_CBC_SHA) || \
+    defined(BUILD_TLS_RSA_WITH_AES_256_CBC_SHA) || \
+    defined(BUILD_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256)
+    #undef  BUILD_AES
+    #define BUILD_AES
+#endif
+
+#if defined(BUILD_TLS_RSA_WITH_AES_128_GCM_SHA256) || \
+    defined(BUILD_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256) || \
+    defined(BUILD_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256) || \
+    defined(BUILD_TLS_PSK_WITH_AES_128_GCM_SHA256)
+    #define BUILD_AESGCM
+#endif
+
+#if defined(BUILD_TLS_RSA_WITH_HC_128_SHA) || \
+    defined(BUILD_TLS_RSA_WITH_HC_128_MD5) || \
+    defined(BUILD_TLS_RSA_WITH_HC_128_B2B256)
+    #define BUILD_HC128
+#endif
+
+#if defined(BUILD_TLS_RSA_WITH_RABBIT_SHA)
+    #define BUILD_RABBIT
+#endif
+
+#ifdef NO_DES3
+    #define DES_BLOCK_SIZE 8
+#else
+    #undef  BUILD_DES3
+    #define BUILD_DES3
+#endif
+
+#ifdef NO_AES
+    #define AES_BLOCK_SIZE 16
+#else
+    #undef  BUILD_AES
+    #define BUILD_AES
+#endif
+
+#ifndef NO_RC4
+    #undef  BUILD_ARC4
+    #define BUILD_ARC4
+#endif
+
+#ifdef HAVE_CHACHA
+    #define CHACHA20_BLOCK_SIZE 16
+#endif
+
+#if defined(WOLFSSL_MAX_STRENGTH) || \
+    defined(HAVE_AESGCM) || defined(HAVE_AESCCM) || \
+    (defined(HAVE_CHACHA) && defined(HAVE_POLY1305))
+
+    #define HAVE_AEAD
+#endif
+
+#if defined(WOLFSSL_MAX_STRENGTH) || \
+    defined(HAVE_ECC) || !defined(NO_DH)
+
+    #define HAVE_PFS
+#endif
+
+
+/* actual cipher values, 2nd byte */
+enum {
+    TLS_DHE_RSA_WITH_AES_256_CBC_SHA  = 0x39,
+    TLS_DHE_RSA_WITH_AES_128_CBC_SHA  = 0x33,
+    TLS_DH_anon_WITH_AES_128_CBC_SHA  = 0x34,
+    TLS_RSA_WITH_AES_256_CBC_SHA      = 0x35,
+    TLS_RSA_WITH_AES_128_CBC_SHA      = 0x2F,
+    TLS_RSA_WITH_NULL_SHA             = 0x02,
+    TLS_PSK_WITH_AES_256_CBC_SHA      = 0x8d,
+    TLS_PSK_WITH_AES_128_CBC_SHA256   = 0xae,
+    TLS_PSK_WITH_AES_256_CBC_SHA384   = 0xaf,
+    TLS_PSK_WITH_AES_128_CBC_SHA      = 0x8c,
+    TLS_PSK_WITH_NULL_SHA256          = 0xb0,
+    TLS_PSK_WITH_NULL_SHA384          = 0xb1,
+    TLS_PSK_WITH_NULL_SHA             = 0x2c,
+    SSL_RSA_WITH_RC4_128_SHA          = 0x05,
+    SSL_RSA_WITH_RC4_128_MD5          = 0x04,
+    SSL_RSA_WITH_3DES_EDE_CBC_SHA     = 0x0A,
+
+    /* ECC suites, first byte is 0xC0 (ECC_BYTE) */
+    TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA    = 0x14,
+    TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA    = 0x13,
+    TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA  = 0x0A,
+    TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA  = 0x09,
+    TLS_ECDHE_RSA_WITH_RC4_128_SHA        = 0x11,
+    TLS_ECDHE_ECDSA_WITH_RC4_128_SHA      = 0x07,
+    TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA   = 0x12,
+    TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA = 0x08,
+    TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256   = 0x27,
+    TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 = 0x23,
+    TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384   = 0x28,
+    TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384 = 0x24,
+
+    /* static ECDH, first byte is 0xC0 (ECC_BYTE) */
+    TLS_ECDH_RSA_WITH_AES_256_CBC_SHA    = 0x0F,
+    TLS_ECDH_RSA_WITH_AES_128_CBC_SHA    = 0x0E,
+    TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA  = 0x05,
+    TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA  = 0x04,
+    TLS_ECDH_RSA_WITH_RC4_128_SHA        = 0x0C,
+    TLS_ECDH_ECDSA_WITH_RC4_128_SHA      = 0x02,
+    TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA   = 0x0D,
+    TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA = 0x03,
+    TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256   = 0x29,
+    TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256 = 0x25,
+    TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384   = 0x2A,
+    TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384 = 0x26,
+
+    /* wolfSSL extension - eSTREAM */
+    TLS_RSA_WITH_HC_128_MD5       = 0xFB,
+    TLS_RSA_WITH_HC_128_SHA       = 0xFC,
+    TLS_RSA_WITH_RABBIT_SHA       = 0xFD,
+
+    /* wolfSSL extension - Blake2b 256 */
+    TLS_RSA_WITH_AES_128_CBC_B2B256   = 0xF8,
+    TLS_RSA_WITH_AES_256_CBC_B2B256   = 0xF9,
+    TLS_RSA_WITH_HC_128_B2B256        = 0xFA,   /* eSTREAM too */
+
+    /* wolfSSL extension - NTRU */
+    TLS_NTRU_RSA_WITH_RC4_128_SHA      = 0xe5,
+    TLS_NTRU_RSA_WITH_3DES_EDE_CBC_SHA = 0xe6,
+    TLS_NTRU_RSA_WITH_AES_128_CBC_SHA  = 0xe7,  /* clashes w/official SHA-256 */
+    TLS_NTRU_RSA_WITH_AES_256_CBC_SHA  = 0xe8,
+
+    /* SHA256 */
+    TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 = 0x6b,
+    TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 = 0x67,
+    TLS_RSA_WITH_AES_256_CBC_SHA256     = 0x3d,
+    TLS_RSA_WITH_AES_128_CBC_SHA256     = 0x3c,
+    TLS_RSA_WITH_NULL_SHA256            = 0x3b,
+    TLS_DHE_PSK_WITH_AES_128_CBC_SHA256 = 0xb2,
+    TLS_DHE_PSK_WITH_NULL_SHA256        = 0xb4,
+
+    /* SHA384 */
+    TLS_DHE_PSK_WITH_AES_256_CBC_SHA384 = 0xb3,
+    TLS_DHE_PSK_WITH_NULL_SHA384        = 0xb5,
+
+    /* AES-GCM */
+    TLS_RSA_WITH_AES_128_GCM_SHA256          = 0x9c,
+    TLS_RSA_WITH_AES_256_GCM_SHA384          = 0x9d,
+    TLS_DHE_RSA_WITH_AES_128_GCM_SHA256      = 0x9e,
+    TLS_DHE_RSA_WITH_AES_256_GCM_SHA384      = 0x9f,
+    TLS_PSK_WITH_AES_128_GCM_SHA256          = 0xa8,
+    TLS_PSK_WITH_AES_256_GCM_SHA384          = 0xa9,
+    TLS_DHE_PSK_WITH_AES_128_GCM_SHA256      = 0xaa,
+    TLS_DHE_PSK_WITH_AES_256_GCM_SHA384      = 0xab,
+
+    /* ECC AES-GCM, first byte is 0xC0 (ECC_BYTE) */
+    TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256  = 0x2b,
+    TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384  = 0x2c,
+    TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256   = 0x2d,
+    TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384   = 0x2e,
+    TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256    = 0x2f,
+    TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384    = 0x30,
+    TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256     = 0x31,
+    TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384     = 0x32,
+
+    /* AES-CCM, first byte is 0xC0 but isn't ECC,
+     * also, in some of the other AES-CCM suites
+     * there will be second byte number conflicts
+     * with non-ECC AES-GCM */
+    TLS_RSA_WITH_AES_128_CCM_8         = 0xa0,
+    TLS_RSA_WITH_AES_256_CCM_8         = 0xa1,
+    TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8 = 0xae,
+    TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8 = 0xaf,
+    TLS_PSK_WITH_AES_128_CCM           = 0xa4,
+    TLS_PSK_WITH_AES_256_CCM           = 0xa5,
+    TLS_PSK_WITH_AES_128_CCM_8         = 0xa8,
+    TLS_PSK_WITH_AES_256_CCM_8         = 0xa9,
+    TLS_DHE_PSK_WITH_AES_128_CCM       = 0xa6,
+    TLS_DHE_PSK_WITH_AES_256_CCM       = 0xa7,
+
+    /* Camellia */
+    TLS_RSA_WITH_CAMELLIA_128_CBC_SHA        = 0x41,
+    TLS_RSA_WITH_CAMELLIA_256_CBC_SHA        = 0x84,
+    TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256     = 0xba,
+    TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256     = 0xc0,
+    TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA    = 0x45,
+    TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA    = 0x88,
+    TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 = 0xbe,
+    TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256 = 0xc4,
+
+    TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256   = 0x13,
+    TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256 = 0x14,
+    TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256     = 0x15,
+
+    /* Renegotiation Indication Extension Special Suite */
+    TLS_EMPTY_RENEGOTIATION_INFO_SCSV        = 0xff
+};
+
+
+#ifndef WOLFSSL_SESSION_TIMEOUT
+    #define WOLFSSL_SESSION_TIMEOUT 500
+    /* default session resumption cache timeout in seconds */
+#endif
+
+
+enum Misc {
+    ECC_BYTE    =  0xC0,           /* ECC first cipher suite byte */
+    CHACHA_BYTE = 0xCC,            /* ChaCha first cipher suite */
+
+    SEND_CERT       = 1,
+    SEND_BLANK_CERT = 2,
+
+    DTLS_MAJOR      = 0xfe,     /* DTLS major version number */
+    DTLS_MINOR      = 0xff,     /* DTLS minor version number */
+    DTLSv1_2_MINOR  = 0xfd,     /* DTLS minor version number */
+    SSLv3_MAJOR     = 3,        /* SSLv3 and TLSv1+  major version number */
+    SSLv3_MINOR     = 0,        /* TLSv1   minor version number */
+    TLSv1_MINOR     = 1,        /* TLSv1   minor version number */
+    TLSv1_1_MINOR   = 2,        /* TLSv1_1 minor version number */
+    TLSv1_2_MINOR   = 3,        /* TLSv1_2 minor version number */
+    OLD_HELLO_ID    = 0x01,     /* SSLv2 Client Hello Indicator */
+    INVALID_BYTE    = 0xff,     /* Used to initialize cipher specs values */
+    NO_COMPRESSION  =  0,
+    ZLIB_COMPRESSION = 221,     /* wolfSSL zlib compression */
+    HELLO_EXT_SIG_ALGO = 13,    /* ID for the sig_algo hello extension */
+    SECRET_LEN      = 48,       /* pre RSA and all master */
+    ENCRYPT_LEN     = 512,      /* allow 4096 bit static buffer */
+    SIZEOF_SENDER   =  4,       /* clnt or srvr           */
+    FINISHED_SZ     = 36,       /* MD5_DIGEST_SIZE + SHA_DIGEST_SIZE */
+    MAX_RECORD_SIZE = 16384,    /* 2^14, max size by standard */
+    MAX_MSG_EXTRA   = 38 + MAX_DIGEST_SIZE,
+                                /* max added to msg, mac + pad  from */
+                                /* RECORD_HEADER_SZ + BLOCK_SZ (pad) + Max
+                                   digest sz + BLOC_SZ (iv) + pad byte (1) */
+    MAX_COMP_EXTRA  = 1024,     /* max compression extra */
+    MAX_MTU         = 1500,     /* max expected MTU */
+    MAX_UDP_SIZE    = 8192 - 100, /* was MAX_MTU - 100 */
+    MAX_DH_SZ       = 1036,     /* 4096 p, pub, g + 2 byte size for each */
+    MAX_STR_VERSION = 8,        /* string rep of protocol version */
+
+    PAD_MD5        = 48,       /* pad length for finished */
+    PAD_SHA        = 40,       /* pad length for finished */
+    MAX_PAD_SIZE   = 256,      /* maximum length of padding */
+    COMPRESS_DUMMY_SIZE = 64,  /* compression dummy round size */
+    COMPRESS_CONSTANT   = 13,  /* compression calc constant */
+    COMPRESS_UPPER      = 55,  /* compression calc numerator */
+    COMPRESS_LOWER      = 64,  /* compression calc denominator */
+
+    PEM_LINE_LEN   = 80,       /* PEM line max + fudge */
+    LENGTH_SZ      =  2,       /* length field for HMAC, data only */
+    VERSION_SZ     =  2,       /* length of proctocol version */
+    SEQ_SZ         =  8,       /* 64 bit sequence number  */
+    BYTE3_LEN      =  3,       /* up to 24 bit byte lengths */
+    ALERT_SIZE     =  2,       /* level + description     */
+    VERIFY_HEADER  =  2,       /* always use 2 bytes      */
+    EXT_ID_SZ      =  2,       /* always use 2 bytes      */
+    MAX_DH_SIZE    = 513,      /* 4096 bit plus possible leading 0 */
+    SESSION_HINT_SZ = 4,       /* session timeout hint */
+
+    MAX_SUITE_SZ = 200,        /* 100 suites for now! */
+    RAN_LEN      = 32,         /* random length           */
+    SEED_LEN     = RAN_LEN * 2, /* tls prf seed length    */
+    ID_LEN       = 32,         /* session id length       */
+    MAX_COOKIE_LEN = 32,       /* max dtls cookie size    */
+    COOKIE_SZ    = 20,         /* use a 20 byte cookie    */
+    SUITE_LEN    =  2,         /* cipher suite sz length  */
+    ENUM_LEN     =  1,         /* always a byte           */
+    OPAQUE8_LEN  =  1,         /* 1 byte                  */
+    OPAQUE16_LEN =  2,         /* 2 bytes                 */
+    OPAQUE24_LEN =  3,         /* 3 bytes                 */
+    OPAQUE32_LEN =  4,         /* 4 bytes                 */
+    COMP_LEN     =  1,         /* compression length      */
+    CURVE_LEN    =  2,         /* ecc named curve length  */
+    SERVER_ID_LEN = 20,        /* server session id length  */
+    
+    HANDSHAKE_HEADER_SZ   = 4,  /* type + length(3)        */
+    RECORD_HEADER_SZ      = 5,  /* type + version + len(2) */
+    CERT_HEADER_SZ        = 3,  /* always 3 bytes          */
+    REQ_HEADER_SZ         = 2,  /* cert request header sz  */
+    HINT_LEN_SZ           = 2,  /* length of hint size field */
+    TRUNCATED_HMAC_SZ     = 10, /* length of hmac w/ truncated hmac extension */
+    HELLO_EXT_TYPE_SZ     = 2,  /* length of a hello extension type */
+    HELLO_EXT_SZ          = 8,  /* total length of the lazy hello extensions */
+    HELLO_EXT_LEN         = 6,  /* length of the lazy hello extensions */
+    HELLO_EXT_SIGALGO_SZ  = 2,  /* length of signature algo extension  */
+    HELLO_EXT_SIGALGO_MAX = 32, /* number of items in the signature algo list */
+
+    DTLS_HANDSHAKE_HEADER_SZ = 12, /* normal + seq(2) + offset(3) + length(3) */
+    DTLS_RECORD_HEADER_SZ    = 13, /* normal + epoch(2) + seq_num(6) */
+    DTLS_HANDSHAKE_EXTRA     = 8,  /* diff from normal */
+    DTLS_RECORD_EXTRA        = 8,  /* diff from normal */
+    DTLS_HANDSHAKE_SEQ_SZ    = 2,  /* handshake header sequence number */
+    DTLS_HANDSHAKE_FRAG_SZ   = 3,  /* fragment offset and length are 24 bit */
+    DTLS_POOL_SZ             = 5,  /* buffers to hold in the retry pool */
+
+    FINISHED_LABEL_SZ   = 15,  /* TLS finished label size */
+    TLS_FINISHED_SZ     = 12,  /* TLS has a shorter size  */
+    MASTER_LABEL_SZ     = 13,  /* TLS master secret label sz */
+    KEY_LABEL_SZ        = 13,  /* TLS key block expansion sz */
+    MAX_PRF_HALF        = 256, /* Maximum half secret len */
+    MAX_PRF_LABSEED     = 128, /* Maximum label + seed len */
+    MAX_PRF_DIG         = 224, /* Maximum digest len      */
+    MAX_REQUEST_SZ      = 256, /* Maximum cert req len (no auth yet */
+    SESSION_FLUSH_COUNT = 256, /* Flush session cache unless user turns off */ 
+
+    RC4_KEY_SIZE        = 16,  /* always 128bit           */
+    DES_KEY_SIZE        =  8,  /* des                     */
+    DES3_KEY_SIZE       = 24,  /* 3 des ede               */
+    DES_IV_SIZE         = DES_BLOCK_SIZE,
+    AES_256_KEY_SIZE    = 32,  /* for 256 bit             */
+    AES_192_KEY_SIZE    = 24,  /* for 192 bit             */
+    AES_IV_SIZE         = 16,  /* always block size       */
+    AES_128_KEY_SIZE    = 16,  /* for 128 bit             */
+
+    AEAD_SEQ_OFFSET     = 4,        /* Auth Data: Sequence number */
+    AEAD_TYPE_OFFSET    = 8,        /* Auth Data: Type            */
+    AEAD_VMAJ_OFFSET    = 9,        /* Auth Data: Major Version   */
+    AEAD_VMIN_OFFSET    = 10,       /* Auth Data: Minor Version   */
+    AEAD_LEN_OFFSET     = 11,       /* Auth Data: Length          */
+    AEAD_AUTH_DATA_SZ   = 13,       /* Size of the data to authenticate */
+    AEAD_IMP_IV_SZ      = 4,        /* Size of the implicit IV     */
+    AEAD_EXP_IV_SZ      = 8,        /* Size of the explicit IV     */
+    AEAD_NONCE_SZ       = AEAD_EXP_IV_SZ + AEAD_IMP_IV_SZ,
+
+    AES_GCM_AUTH_SZ     = 16, /* AES-GCM Auth Tag length    */
+    AES_CCM_16_AUTH_SZ  = 16, /* AES-CCM-16 Auth Tag length */
+    AES_CCM_8_AUTH_SZ   = 8,  /* AES-CCM-8 Auth Tag Length  */
+
+    CAMELLIA_128_KEY_SIZE = 16, /* for 128 bit */
+    CAMELLIA_192_KEY_SIZE = 24, /* for 192 bit */
+    CAMELLIA_256_KEY_SIZE = 32, /* for 256 bit */
+    CAMELLIA_IV_SIZE      = 16, /* always block size */
+
+    CHACHA20_256_KEY_SIZE = 32,  /* for 256 bit             */
+    CHACHA20_128_KEY_SIZE = 16,  /* for 128 bit             */
+    CHACHA20_IV_SIZE      =  8,  /* 64 bits for iv          */
+
+    POLY1305_AUTH_SZ    = 16,  /* 128 bits                */
+
+    HC_128_KEY_SIZE     = 16,  /* 128 bits                */
+    HC_128_IV_SIZE      = 16,  /* also 128 bits           */
+
+    RABBIT_KEY_SIZE     = 16,  /* 128 bits                */
+    RABBIT_IV_SIZE      =  8,  /* 64 bits for iv          */
+
+    EVP_SALT_SIZE       =  8,  /* evp salt size 64 bits   */
+
+    ECDHE_SIZE          = 32,  /* ECHDE server size defaults to 256 bit */
+    MAX_EXPORT_ECC_SZ   = 256, /* Export ANS X9.62 max future size */
+
+    MAX_HELLO_SZ       = 128,  /* max client or server hello */
+    MAX_CERT_VERIFY_SZ = 1024, /* max   */
+    CLIENT_HELLO_FIRST =  35,  /* Protocol + RAN_LEN + sizeof(id_len) */
+    MAX_SUITE_NAME     =  48,  /* maximum length of cipher suite string */
+
+    DTLS_TIMEOUT_INIT       =  1, /* default timeout init for DTLS receive  */
+    DTLS_TIMEOUT_MAX        = 64, /* default max timeout for DTLS receive */
+    DTLS_TIMEOUT_MULTIPLIER =  2, /* default timeout multiplier for DTLS recv */
+
+    MAX_PSK_ID_LEN     = 128,  /* max psk identity/hint supported */
+    MAX_PSK_KEY_LEN    =  64,  /* max psk key supported */
+
+    MAX_WOLFSSL_FILE_SIZE = 1024 * 1024 * 4,  /* 4 mb file size alloc limit */
+
+#ifdef FORTRESS
+    MAX_EX_DATA        =   3,  /* allow for three items of ex_data */
+#endif
+
+    MAX_X509_SIZE      = 2048, /* max static x509 buffer size */
+    CERT_MIN_SIZE      =  256, /* min PEM cert size with header/footer */
+    MAX_FILENAME_SZ    =  256, /* max file name length */
+    FILE_BUFFER_SIZE   = 1024, /* default static file buffer size for input,
+                                  will use dynamic buffer if not big enough */
+
+    MAX_NTRU_PUB_KEY_SZ = 1027, /* NTRU max for now */
+    MAX_NTRU_ENCRYPT_SZ = 1027, /* NTRU max for now */
+    MAX_NTRU_BITS       =  256, /* max symmetric bit strength */
+    NO_SNIFF           =   0,  /* not sniffing */
+    SNIFF              =   1,  /* currently sniffing */
+
+    HASH_SIG_SIZE      =   2,  /* default SHA1 RSA */
+
+    NO_CAVIUM_DEVICE   =  -2,  /* invalid cavium device id */
+
+    NO_COPY            =   0,  /* should we copy static buffer for write */
+    COPY               =   1   /* should we copy static buffer for write */
+};
+
+
+#ifndef WOLFSSL_MIN_DHKEY_BITS
+    #ifdef WOLFSSL_MAX_STRENGTH
+        #define WOLFSSL_MIN_DHKEY_BITS 2048
+    #else
+        #define WOLFSSL_MIN_DHKEY_BITS 1024
+    #endif
+#endif
+#if (WOLFSSL_MIN_DHKEY_BITS % 8)
+    #error DH minimum bit size must be multiple of 8
+#endif
+#if (WOLFSSL_MIN_DHKEY_BITS > 16000)
+    #error DH minimum bit size must not be greater than 16000
+#endif
+#define MIN_DHKEY_SZ (WOLFSSL_MIN_DHKEY_BITS / 8)
+
+
+#ifdef SESSION_INDEX
+/* Shift values for making a session index */
+#define SESSIDX_ROW_SHIFT 4
+#define SESSIDX_IDX_MASK  0x0F
+#endif
+
+
+/* max cert chain peer depth */
+#ifndef MAX_CHAIN_DEPTH
+    #define MAX_CHAIN_DEPTH 9
+#endif
+
+#ifndef SESSION_TICKET_LEN
+    #define SESSION_TICKET_LEN 256
+#endif
+
+#ifndef SESSION_TICKET_HINT_DEFAULT
+    #define SESSION_TICKET_HINT_DEFAULT 300
+#endif
+
+
+/* don't use extra 3/4k stack space unless need to */
+#ifdef HAVE_NTRU
+    #define MAX_ENCRYPT_SZ MAX_NTRU_ENCRYPT_SZ
+#else
+    #define MAX_ENCRYPT_SZ ENCRYPT_LEN
+#endif
+
+
+/* states */
+enum states {
+    NULL_STATE = 0,
+
+    SERVER_HELLOVERIFYREQUEST_COMPLETE,
+    SERVER_HELLO_COMPLETE,
+    SERVER_CERT_COMPLETE,
+    SERVER_KEYEXCHANGE_COMPLETE,
+    SERVER_HELLODONE_COMPLETE,
+    SERVER_FINISHED_COMPLETE,
+
+    CLIENT_HELLO_COMPLETE,
+    CLIENT_KEYEXCHANGE_COMPLETE,
+    CLIENT_FINISHED_COMPLETE,
+
+    HANDSHAKE_DONE
+};
+
+
+#if defined(__GNUC__)
+    #define WOLFSSL_PACK __attribute__ ((packed))
+#else
+    #define WOLFSSL_PACK
+#endif
+
+/* SSL Version */
+typedef struct ProtocolVersion {
+    byte major;
+    byte minor;
+} WOLFSSL_PACK ProtocolVersion;
+
+
+WOLFSSL_LOCAL ProtocolVersion MakeSSLv3(void);
+WOLFSSL_LOCAL ProtocolVersion MakeTLSv1(void);
+WOLFSSL_LOCAL ProtocolVersion MakeTLSv1_1(void);
+WOLFSSL_LOCAL ProtocolVersion MakeTLSv1_2(void);
+
+#ifdef WOLFSSL_DTLS
+    WOLFSSL_LOCAL ProtocolVersion MakeDTLSv1(void);
+    WOLFSSL_LOCAL ProtocolVersion MakeDTLSv1_2(void);
+#endif
+
+
+enum BIO_TYPE {
+    BIO_BUFFER = 1,
+    BIO_SOCKET = 2,
+    BIO_SSL    = 3,
+    BIO_MEMORY = 4
+};
+
+
+/* wolfSSL BIO_METHOD type */
+struct WOLFSSL_BIO_METHOD {
+    byte type;               /* method type */
+};
+
+
+/* wolfSSL BIO type */
+struct WOLFSSL_BIO {
+    byte        type;          /* method type */
+    byte        close;         /* close flag */
+    byte        eof;           /* eof flag */
+    WOLFSSL*     ssl;           /* possible associated ssl */
+    byte*       mem;           /* memory buffer */
+    int         memLen;        /* memory buffer length */
+    int         fd;            /* possible file descriptor */
+    WOLFSSL_BIO* prev;          /* previous in chain */
+    WOLFSSL_BIO* next;          /* next in chain */
+};
+
+
+/* wolfSSL method type */
+struct WOLFSSL_METHOD {
+    ProtocolVersion version;
+    byte            side;         /* connection side, server or client */
+    byte            downgrade;    /* whether to downgrade version, default no */
+};
+
+
+/* defautls to client */
+WOLFSSL_LOCAL void InitSSL_Method(WOLFSSL_METHOD*, ProtocolVersion);
+
+/* for sniffer */
+WOLFSSL_LOCAL int DoFinished(WOLFSSL* ssl, const byte* input, word32* inOutIdx,
+                            word32 size, word32 totalSz, int sniff);
+WOLFSSL_LOCAL int DoApplicationData(WOLFSSL* ssl, byte* input, word32* inOutIdx);
+
+
+/* wolfSSL buffer type */
+typedef struct buffer {
+    byte*  buffer;
+    word32 length;
+} buffer;
+
+
+enum {
+    FORCED_FREE = 1,
+    NO_FORCED_FREE = 0
+};
+
+
+/* only use compression extra if using compression */
+#ifdef HAVE_LIBZ
+    #define COMP_EXTRA MAX_COMP_EXTRA
+#else
+    #define COMP_EXTRA 0
+#endif
+
+/* only the sniffer needs space in the buffer for extra MTU record(s) */
+#ifdef WOLFSSL_SNIFFER
+    #define MTU_EXTRA MAX_MTU * 3 
+#else
+    #define MTU_EXTRA 0
+#endif
+
+
+/* embedded callbacks require large static buffers, make sure on */
+#ifdef WOLFSSL_CALLBACKS
+    #undef  LARGE_STATIC_BUFFERS
+    #define LARGE_STATIC_BUFFERS
+#endif
+
+
+/* give user option to use 16K static buffers */
+#if defined(LARGE_STATIC_BUFFERS)
+    #define RECORD_SIZE MAX_RECORD_SIZE
+#else
+    #ifdef WOLFSSL_DTLS
+        #define RECORD_SIZE MAX_MTU 
+    #else
+        #define RECORD_SIZE 128 
+    #endif
+#endif
+
+
+/* user option to turn off 16K output option */
+/* if using small static buffers (default) and SSL_write tries to write data
+   larger than the record we have, dynamically get it, unless user says only
+   write in static buffer chuncks  */
+#ifndef STATIC_CHUNKS_ONLY
+    #define OUTPUT_RECORD_SIZE MAX_RECORD_SIZE
+#else
+    #define OUTPUT_RECORD_SIZE RECORD_SIZE
+#endif
+
+/* wolfSSL input buffer
+
+   RFC 2246:
+
+   length
+       The length (in bytes) of the following TLSPlaintext.fragment.
+       The length should not exceed 2^14.
+*/
+#if defined(LARGE_STATIC_BUFFERS)
+    #define STATIC_BUFFER_LEN RECORD_HEADER_SZ + RECORD_SIZE + COMP_EXTRA + \
+             MTU_EXTRA + MAX_MSG_EXTRA
+#else
+    /* don't fragment memory from the record header */
+    #define STATIC_BUFFER_LEN RECORD_HEADER_SZ
+#endif
+
+typedef struct {
+    ALIGN16 byte staticBuffer[STATIC_BUFFER_LEN];
+    byte*  buffer;       /* place holder for static or dynamic buffer */
+    word32 length;       /* total buffer length used */
+    word32 idx;          /* idx to part of length already consumed */
+    word32 bufferSize;   /* current buffer size */
+    byte   dynamicFlag;  /* dynamic memory currently in use */
+    byte   offset;       /* alignment offset attempt */
+} bufferStatic;
+
+/* Cipher Suites holder */
+typedef struct Suites {
+    word16 suiteSz;                 /* suite length in bytes        */
+    word16 hashSigAlgoSz;           /* SigAlgo extension length in bytes */
+    byte   suites[MAX_SUITE_SZ];
+    byte   hashSigAlgo[HELLO_EXT_SIGALGO_MAX]; /* sig/algo to offer */
+    byte   setSuites;               /* user set suites from default */
+    byte   hashAlgo;                /* selected hash algorithm */
+    byte   sigAlgo;                 /* selected sig algorithm */
+} Suites;
+
+
+WOLFSSL_LOCAL
+void InitSuites(Suites*, ProtocolVersion, word16, word16, word16, word16,
+                word16, word16, int);
+WOLFSSL_LOCAL
+int  SetCipherList(Suites*, const char* list);
+
+#ifndef PSK_TYPES_DEFINED
+    typedef unsigned int (*psk_client_callback)(WOLFSSL*, const char*, char*,
+                          unsigned int, unsigned char*, unsigned int);
+    typedef unsigned int (*psk_server_callback)(WOLFSSL*, const char*,
+                          unsigned char*, unsigned int);
+#endif /* PSK_TYPES_DEFINED */
+
+
+#ifdef HAVE_NETX
+    WOLFSSL_LOCAL int NetX_Receive(WOLFSSL *ssl, char *buf, int sz, void *ctx);
+    WOLFSSL_LOCAL int NetX_Send(WOLFSSL *ssl, char *buf, int sz, void *ctx);
+#endif /* HAVE_NETX */
+
+
+/* wolfSSL Cipher type just points back to SSL */
+struct WOLFSSL_CIPHER {
+    WOLFSSL* ssl;
+};
+
+
+typedef struct OCSP_Entry OCSP_Entry;
+
+#ifdef NO_SHA
+    #define OCSP_DIGEST_SIZE SHA256_DIGEST_SIZE
+#else
+    #define OCSP_DIGEST_SIZE SHA_DIGEST_SIZE
+#endif
+
+#ifdef NO_ASN 
+    /* no_asn won't have */
+    typedef struct CertStatus CertStatus;
+#endif
+
+struct OCSP_Entry {
+    OCSP_Entry* next;                        /* next entry             */
+    byte    issuerHash[OCSP_DIGEST_SIZE];    /* issuer hash            */ 
+    byte    issuerKeyHash[OCSP_DIGEST_SIZE]; /* issuer public key hash */
+    CertStatus* status;                      /* OCSP response list     */
+    int         totalStatus;                 /* number on list         */
+};
+
+
+#ifndef HAVE_OCSP
+    typedef struct WOLFSSL_OCSP WOLFSSL_OCSP;
+#endif
+
+/* wolfSSL OCSP controller */
+struct WOLFSSL_OCSP {
+    WOLFSSL_CERT_MANAGER* cm;            /* pointer back to cert manager */
+    OCSP_Entry*          ocspList;      /* OCSP response list */
+    wolfSSL_Mutex         ocspLock;      /* OCSP list lock */
+};
+
+#ifndef MAX_DATE_SIZE
+#define MAX_DATE_SIZE 32
+#endif
+
+typedef struct CRL_Entry CRL_Entry;
+
+#ifdef NO_SHA
+    #define CRL_DIGEST_SIZE SHA256_DIGEST_SIZE
+#else
+    #define CRL_DIGEST_SIZE SHA_DIGEST_SIZE
+#endif
+
+#ifdef NO_ASN 
+    typedef struct RevokedCert RevokedCert;
+#endif
+
+/* Complete CRL */
+struct CRL_Entry {
+    CRL_Entry* next;                      /* next entry */
+    byte    issuerHash[CRL_DIGEST_SIZE];  /* issuer hash                 */ 
+    /* byte    crlHash[CRL_DIGEST_SIZE];      raw crl data hash           */ 
+    /* restore the hash here if needed for optimized comparisons */
+    byte    lastDate[MAX_DATE_SIZE]; /* last date updated  */
+    byte    nextDate[MAX_DATE_SIZE]; /* next update date   */
+    byte    lastDateFormat;          /* last date format */
+    byte    nextDateFormat;          /* next date format */
+    RevokedCert* certs;              /* revoked cert list  */
+    int          totalCerts;         /* number on list     */
+};
+
+
+typedef struct CRL_Monitor CRL_Monitor;
+
+/* CRL directory monitor */
+struct CRL_Monitor {
+    char* path;      /* full dir path, if valid pointer we're using */
+    int   type;      /* PEM or ASN1 type */
+};
+
+
+#ifndef HAVE_CRL
+    typedef struct WOLFSSL_CRL WOLFSSL_CRL;
+#endif
+
+/* wolfSSL CRL controller */
+struct WOLFSSL_CRL {
+    WOLFSSL_CERT_MANAGER* cm;            /* pointer back to cert manager */
+    CRL_Entry*           crlList;       /* our CRL list */
+    wolfSSL_Mutex         crlLock;       /* CRL list lock */
+    CRL_Monitor          monitors[2];   /* PEM and DER possible */
+#ifdef HAVE_CRL_MONITOR
+    pthread_t            tid;           /* monitoring thread */
+    int                  mfd;           /* monitor fd, -1 if no init yet */
+#endif
+};
+
+
+#ifdef NO_ASN 
+    typedef struct Signer Signer;
+#endif
+
+
+#ifndef CA_TABLE_SIZE
+    #define CA_TABLE_SIZE 11
+#endif
+
+/* wolfSSL Certificate Manager */
+struct WOLFSSL_CERT_MANAGER {
+    Signer*         caTable[CA_TABLE_SIZE]; /* the CA signer table */
+    void*           heap;               /* heap helper */
+    WOLFSSL_CRL*    crl;                /* CRL checker */
+    WOLFSSL_OCSP*   ocsp;               /* OCSP checker */
+    char*           ocspOverrideURL;    /* use this responder */
+    void*           ocspIOCtx;          /* I/O callback CTX */
+    CallbackCACache caCacheCallback;    /* CA cache addition callback */
+    CbMissingCRL    cbMissingCRL;       /* notify through cb of missing crl */
+    CbOCSPIO        ocspIOCb;           /* I/O callback for OCSP lookup */
+    CbOCSPRespFree  ocspRespFreeCb;     /* Frees OCSP Response from IO Cb */
+    wolfSSL_Mutex   caLock;             /* CA list lock */
+    byte            crlEnabled;         /* is CRL on ? */
+    byte            crlCheckAll;        /* always leaf, but all ? */
+    byte            ocspEnabled;        /* is OCSP on ? */
+    byte            ocspCheckAll;       /* always leaf, but all ? */
+    byte            ocspSendNonce;      /* send the OCSP nonce ? */
+    byte            ocspUseOverrideURL; /* ignore cert's responder, override */
+};
+
+WOLFSSL_LOCAL int CM_SaveCertCache(WOLFSSL_CERT_MANAGER*, const char*);
+WOLFSSL_LOCAL int CM_RestoreCertCache(WOLFSSL_CERT_MANAGER*, const char*);
+WOLFSSL_LOCAL int CM_MemSaveCertCache(WOLFSSL_CERT_MANAGER*, void*, int, int*);
+WOLFSSL_LOCAL int CM_MemRestoreCertCache(WOLFSSL_CERT_MANAGER*, const void*, int);
+WOLFSSL_LOCAL int CM_GetCertCacheMemSize(WOLFSSL_CERT_MANAGER*);
+
+/* wolfSSL Sock Addr */
+struct WOLFSSL_SOCKADDR {
+    unsigned int sz; /* sockaddr size */
+    void*        sa; /* pointer to the sockaddr_in or sockaddr_in6 */
+};
+
+typedef struct WOLFSSL_DTLS_CTX {
+    WOLFSSL_SOCKADDR peer;
+    int fd;
+} WOLFSSL_DTLS_CTX;
+
+
+#ifdef WOLFSSL_DTLS
+
+    #ifdef WORD64_AVAILABLE
+        typedef word64 DtlsSeq;
+    #else
+        typedef word32 DtlsSeq;
+    #endif
+    #define DTLS_SEQ_BITS (sizeof(DtlsSeq) * CHAR_BIT)
+
+    typedef struct DtlsState {
+        DtlsSeq window;     /* Sliding window for current epoch    */
+        word16 nextEpoch;   /* Expected epoch in next record       */
+        word32 nextSeq;     /* Expected sequence in next record    */
+
+        word16 curEpoch;    /* Received epoch in current record    */
+        word32 curSeq;      /* Received sequence in current record */
+
+        DtlsSeq prevWindow; /* Sliding window for old epoch        */
+        word32 prevSeq;     /* Next sequence in allowed old epoch  */
+    } DtlsState;
+
+#endif /* WOLFSSL_DTLS */
+
+
+/* keys and secrets */
+typedef struct Keys {
+    byte client_write_MAC_secret[MAX_DIGEST_SIZE];   /* max sizes */
+    byte server_write_MAC_secret[MAX_DIGEST_SIZE];
+    byte client_write_key[AES_256_KEY_SIZE];         /* max sizes */
+    byte server_write_key[AES_256_KEY_SIZE];
+    byte client_write_IV[AES_IV_SIZE];               /* max sizes */
+    byte server_write_IV[AES_IV_SIZE];
+#ifdef HAVE_AEAD
+    byte aead_exp_IV[AEAD_EXP_IV_SZ];
+    byte aead_enc_imp_IV[AEAD_IMP_IV_SZ];
+    byte aead_dec_imp_IV[AEAD_IMP_IV_SZ];
+#endif
+
+    word32 peer_sequence_number;
+    word32 sequence_number;
+
+#ifdef WOLFSSL_DTLS
+    DtlsState dtls_state;                       /* Peer's state */
+    word16 dtls_peer_handshake_number;
+    word16 dtls_expected_peer_handshake_number;
+
+    word16 dtls_epoch;                          /* Current tx epoch    */
+    word32 dtls_sequence_number;                /* Current tx sequence */
+    word16 dtls_handshake_number;               /* Current tx handshake seq */
+#endif
+
+    word32 encryptSz;             /* last size of encrypted data   */
+    word32 padSz;                 /* how much to advance after decrypt part */
+    byte   encryptionOn;          /* true after change cipher spec */
+    byte   decryptedCur;          /* only decrypt current record once */
+} Keys;
+
+
+
+/* RFC 6066 TLS Extensions */
+#ifdef HAVE_TLS_EXTENSIONS
+
+typedef enum {
+    SERVER_NAME_INDICATION = 0x0000,
+    MAX_FRAGMENT_LENGTH    = 0x0001,
+    TRUNCATED_HMAC         = 0x0004,
+    ELLIPTIC_CURVES        = 0x000a,
+    SESSION_TICKET         = 0x0023,
+    SECURE_RENEGOTIATION   = 0xff01
+} TLSX_Type;
+
+typedef struct TLSX {
+    TLSX_Type    type; /* Extension Type  */
+    void*        data; /* Extension Data  */
+    byte         resp; /* IsResponse Flag */
+    struct TLSX* next; /* List Behavior   */
+} TLSX;
+
+WOLFSSL_LOCAL TLSX*  TLSX_Find(TLSX* list, TLSX_Type type);
+WOLFSSL_LOCAL void   TLSX_FreeAll(TLSX* list);
+WOLFSSL_LOCAL int    TLSX_SupportExtensions(WOLFSSL* ssl);
+
+#ifndef NO_WOLFSSL_CLIENT
+WOLFSSL_LOCAL word16 TLSX_GetRequestSize(WOLFSSL* ssl);
+WOLFSSL_LOCAL word16 TLSX_WriteRequest(WOLFSSL* ssl, byte* output);
+#endif
+
+#ifndef NO_WOLFSSL_SERVER
+WOLFSSL_LOCAL word16 TLSX_GetResponseSize(WOLFSSL* ssl);
+WOLFSSL_LOCAL word16 TLSX_WriteResponse(WOLFSSL* ssl, byte* output);
+#endif
+
+WOLFSSL_LOCAL int    TLSX_Parse(WOLFSSL* ssl, byte* input, word16 length,
+                                                byte isRequest, Suites *suites);
+                                                
+#elif defined(HAVE_SNI)                  \
+   || defined(HAVE_MAX_FRAGMENT)         \
+   || defined(HAVE_TRUNCATED_HMAC)       \
+   || defined(HAVE_SUPPORTED_CURVES)     \
+   || defined(HAVE_SECURE_RENEGOTIATION) \
+   || defined(HAVE_SESSION_TICKET)
+
+#error Using TLS extensions requires HAVE_TLS_EXTENSIONS to be defined.
+
+#endif /* HAVE_TLS_EXTENSIONS */
+
+/* Server Name Indication */
+#ifdef HAVE_SNI
+
+typedef struct SNI {
+    byte                       type;    /* SNI Type          */
+    union { char* host_name; } data;    /* SNI Data          */
+    struct SNI*                next;    /* List Behavior     */
+#ifndef NO_WOLFSSL_SERVER
+    byte                       options; /* Behaviour options */
+    byte                       status;  /* Matching result   */
+#endif
+} SNI;
+
+WOLFSSL_LOCAL int TLSX_UseSNI(TLSX** extensions, byte type, const void* data,
+                                                                   word16 size);
+
+#ifndef NO_WOLFSSL_SERVER
+WOLFSSL_LOCAL void   TLSX_SNI_SetOptions(TLSX* extensions, byte type,
+                                                                  byte options);
+WOLFSSL_LOCAL byte   TLSX_SNI_Status(TLSX* extensions, byte type);
+WOLFSSL_LOCAL word16 TLSX_SNI_GetRequest(TLSX* extensions, byte type,
+                                                                   void** data);
+WOLFSSL_LOCAL int    TLSX_SNI_GetFromBuffer(const byte* buffer, word32 bufferSz,
+                                         byte type, byte* sni, word32* inOutSz);
+#endif
+
+#endif /* HAVE_SNI */
+
+/* Maximum Fragment Length */
+#ifdef HAVE_MAX_FRAGMENT
+
+WOLFSSL_LOCAL int TLSX_UseMaxFragment(TLSX** extensions, byte mfl);
+
+#endif /* HAVE_MAX_FRAGMENT */
+
+#ifdef HAVE_TRUNCATED_HMAC
+
+WOLFSSL_LOCAL int TLSX_UseTruncatedHMAC(TLSX** extensions);
+
+#endif /* HAVE_TRUNCATED_HMAC */
+
+#ifdef HAVE_SUPPORTED_CURVES
+
+typedef struct EllipticCurve {
+    word16                name; /* CurveNames    */
+    struct EllipticCurve* next; /* List Behavior */
+} EllipticCurve;
+
+WOLFSSL_LOCAL int TLSX_UseSupportedCurve(TLSX** extensions, word16 name);
+
+#ifndef NO_WOLFSSL_SERVER
+WOLFSSL_LOCAL int TLSX_ValidateEllipticCurves(WOLFSSL* ssl, byte first,
+                                                                   byte second);
+#endif
+
+#endif /* HAVE_SUPPORTED_CURVES */
+
+#ifdef HAVE_SECURE_RENEGOTIATION
+
+enum key_cache_state {
+    SCR_CACHE_NULL   = 0,       /* empty / begin state */
+    SCR_CACHE_NEEDED,           /* need to cache keys */
+    SCR_CACHE_COPY,             /* we have a cached copy */
+    SCR_CACHE_PARTIAL,          /* partial restore to real keys */
+    SCR_CACHE_COMPLETE          /* complete restore to real keys */
+};
+
+
+/* Additional Conection State according to rfc5746 section 3.1 */
+typedef struct SecureRenegotiation {
+   byte                 enabled;  /* secure_renegotiation flag in rfc */
+   byte                 startScr; /* server requested client to start scr */
+   enum key_cache_state cache_status;  /* track key cache state */
+   byte                 client_verify_data[TLS_FINISHED_SZ];  /* cached */
+   byte                 server_verify_data[TLS_FINISHED_SZ];  /* cached */
+   byte                 subject_hash[SHA_DIGEST_SIZE];  /* peer cert hash */
+   Keys                 tmp_keys;  /* can't overwrite real keys yet */
+} SecureRenegotiation;
+
+WOLFSSL_LOCAL int TLSX_UseSecureRenegotiation(TLSX** extensions);
+
+#endif /* HAVE_SECURE_RENEGOTIATION */
+
+#ifdef HAVE_SESSION_TICKET
+
+typedef struct SessionTicket {
+    word32 lifetime;
+    byte*  data;
+    word16 size;
+} SessionTicket;
+
+WOLFSSL_LOCAL int  TLSX_UseSessionTicket(TLSX** extensions, 
+                                                         SessionTicket* ticket);
+WOLFSSL_LOCAL SessionTicket* TLSX_SessionTicket_Create(word32 lifetime,
+                                                       byte* data, word16 size);
+WOLFSSL_LOCAL void TLSX_SessionTicket_Free(SessionTicket* ticket);
+#endif /* HAVE_SESSION_TICKET */
+
+/* wolfSSL context type */
+struct WOLFSSL_CTX {
+    WOLFSSL_METHOD* method;
+    wolfSSL_Mutex   countMutex;    /* reference count mutex */
+    int         refCount;         /* reference count */
+#ifndef NO_DH
+    buffer      serverDH_P;
+    buffer      serverDH_G;
+#endif
+#ifndef NO_CERTS
+    buffer      certificate;
+    buffer      certChain;
+                 /* chain after self, in DER, with leading size for each cert */
+    buffer      privateKey;
+    WOLFSSL_CERT_MANAGER* cm;      /* our cert manager, ctx owns SSL will use */
+#endif
+    Suites*     suites;           /* make dynamic, user may not need/set */
+    void*       heap;             /* for user memory overrides */
+    byte        verifyPeer;
+    byte        verifyNone;
+    byte        failNoCert;
+    byte        sessionCacheOff;
+    byte        sessionCacheFlushOff;
+    byte        sendVerify;       /* for client side */
+    byte        haveRSA;          /* RSA available */
+    byte        haveDH;           /* server DH parms set by user */
+    byte        haveNTRU;         /* server private NTRU  key loaded */
+    byte        haveECDSAsig;     /* server cert signed w/ ECDSA */
+    byte        haveStaticECC;    /* static server ECC private key */
+    byte        partialWrite;     /* only one msg per write call */
+    byte        quietShutdown;    /* don't send close notify */
+    byte        groupMessages;    /* group handshake messages before sending */
+    byte        minDowngrade;     /* minimum downgrade version */
+#ifndef NO_DH
+    word16      minDhKeySz;       /* minimum DH key size */
+#endif
+    CallbackIORecv CBIORecv;
+    CallbackIOSend CBIOSend;
+#ifdef WOLFSSL_DTLS
+    CallbackGenCookie CBIOCookie;       /* gen cookie callback */
+#endif
+    VerifyCallback  verifyCallback;     /* cert verification callback */
+    word32          timeout;            /* session timeout */
+#ifdef HAVE_ECC
+    word16          eccTempKeySz;       /* in octets 20 - 66 */
+    word32          pkCurveOID;         /* curve Ecc_Sum */
+#endif
+#ifndef NO_PSK
+    byte        havePSK;                /* psk key set by user */
+    psk_client_callback client_psk_cb;  /* client callback */
+    psk_server_callback server_psk_cb;  /* server callback */
+    char        server_hint[MAX_PSK_ID_LEN];
+#endif /* NO_PSK */
+#ifdef HAVE_ANON
+    byte        haveAnon;               /* User wants to allow Anon suites */
+#endif /* HAVE_ANON */
+#if defined(OPENSSL_EXTRA) || defined(HAVE_WEBSERVER)
+    pem_password_cb passwd_cb;
+    void*            userdata;
+#endif /* OPENSSL_EXTRA */
+#ifdef HAVE_OCSP
+    WOLFSSL_OCSP      ocsp;
+#endif
+#ifdef HAVE_CAVIUM
+    int              devId;            /* cavium device id to use */
+#endif
+#ifdef HAVE_TLS_EXTENSIONS
+    TLSX* extensions;                  /* RFC 6066 TLS Extensions data */
+    #if defined(HAVE_SESSION_TICKET) && !defined(NO_WOLFSSL_SEVER)
+        SessionTicketEncCb ticketEncCb;   /* enc/dec session ticket Cb */
+        void*              ticketEncCtx;  /* session encrypt context */
+        int                ticketHint;    /* ticket hint in seconds */
+    #endif
+#endif
+#ifdef ATOMIC_USER
+    CallbackMacEncrypt    MacEncryptCb;    /* Atomic User Mac/Encrypt Cb */
+    CallbackDecryptVerify DecryptVerifyCb; /* Atomic User Decrypt/Verify Cb */
+#endif
+#ifdef HAVE_PK_CALLBACKS
+    #ifdef HAVE_ECC
+        CallbackEccSign   EccSignCb;    /* User EccSign   Callback handler */
+        CallbackEccVerify EccVerifyCb;  /* User EccVerify Callback handler */
+    #endif /* HAVE_ECC */
+    #ifndef NO_RSA 
+        CallbackRsaSign   RsaSignCb;    /* User RsaSign   Callback handler */
+        CallbackRsaVerify RsaVerifyCb;  /* User RsaVerify Callback handler */
+        CallbackRsaEnc    RsaEncCb;     /* User Rsa Public Encrypt  handler */
+        CallbackRsaDec    RsaDecCb;     /* User Rsa Private Decrypt handler */
+    #endif /* NO_RSA */
+#endif /* HAVE_PK_CALLBACKS */
+};
+
+
+WOLFSSL_LOCAL
+int InitSSL_Ctx(WOLFSSL_CTX*, WOLFSSL_METHOD*);
+WOLFSSL_LOCAL
+void FreeSSL_Ctx(WOLFSSL_CTX*);
+WOLFSSL_LOCAL
+void SSL_CtxResourceFree(WOLFSSL_CTX*);
+
+WOLFSSL_LOCAL
+int DeriveTlsKeys(WOLFSSL* ssl);
+WOLFSSL_LOCAL
+int ProcessOldClientHello(WOLFSSL* ssl, const byte* input, word32* inOutIdx,
+                          word32 inSz, word16 sz);
+#ifndef NO_CERTS
+    WOLFSSL_LOCAL
+    int AddCA(WOLFSSL_CERT_MANAGER* ctx, buffer der, int type, int verify);
+    WOLFSSL_LOCAL
+    int AlreadySigner(WOLFSSL_CERT_MANAGER* cm, byte* hash);
+#endif
+
+/* All cipher suite related info */
+typedef struct CipherSpecs {
+    word16 key_size;
+    word16 iv_size;
+    word16 block_size;
+    word16 aead_mac_size;
+    byte bulk_cipher_algorithm;
+    byte cipher_type;               /* block, stream, or aead */
+    byte mac_algorithm;
+    byte kea;                       /* key exchange algo */
+    byte sig_algo;
+    byte hash_size;
+    byte pad_size;
+    byte static_ecdh;
+} CipherSpecs;
+
+
+void InitCipherSpecs(CipherSpecs* cs);
+
+
+/* Supported Message Authentication Codes from page 43 */
+enum MACAlgorithm { 
+    no_mac,
+    md5_mac,
+    sha_mac,
+    sha224_mac,
+    sha256_mac,     /* needs to match external KDF_MacAlgorithm */
+    sha384_mac,
+    sha512_mac,
+    rmd_mac,
+    blake2b_mac
+};
+
+
+/* Supported Key Exchange Protocols */
+enum KeyExchangeAlgorithm { 
+    no_kea,
+    rsa_kea, 
+    diffie_hellman_kea, 
+    fortezza_kea,
+    psk_kea,
+    dhe_psk_kea,
+    ntru_kea,
+    ecc_diffie_hellman_kea,
+    ecc_static_diffie_hellman_kea       /* for verify suite only */
+};
+
+
+/* Supported Authentication Schemes */
+enum SignatureAlgorithm {
+    anonymous_sa_algo,
+    rsa_sa_algo,
+    dsa_sa_algo,
+    ecc_dsa_sa_algo
+};
+
+
+/* Supprted ECC Curve Types */
+enum EccCurves {
+    named_curve = 3
+};
+
+
+/* Valid client certificate request types from page 27 */
+enum ClientCertificateType {    
+    rsa_sign            = 1, 
+    dss_sign            = 2,
+    rsa_fixed_dh        = 3,
+    dss_fixed_dh        = 4,
+    rsa_ephemeral_dh    = 5,
+    dss_ephemeral_dh    = 6,
+    fortezza_kea_cert   = 20,
+    ecdsa_sign          = 64,
+    rsa_fixed_ecdh      = 65,
+    ecdsa_fixed_ecdh    = 66
+};
+
+
+enum CipherType { stream, block, aead };
+
+
+
+
+
+
+/* cipher for now */
+typedef struct Ciphers {
+#ifdef BUILD_ARC4
+    Arc4*   arc4;
+#endif
+#ifdef BUILD_DES3
+    Des3*   des3;
+#endif
+#if defined(BUILD_AES) || defined(BUILD_AESGCM)
+    Aes*    aes;
+#endif
+#ifdef HAVE_CAMELLIA
+    Camellia* cam;
+#endif
+#ifdef HAVE_CHACHA
+    ChaCha*   chacha;
+#endif
+#ifdef HAVE_HC128
+    HC128*  hc128;
+#endif
+#ifdef BUILD_RABBIT
+    Rabbit* rabbit;
+#endif
+    byte    setup;       /* have we set it up flag for detection */
+} Ciphers;
+
+
+#ifdef HAVE_ONE_TIME_AUTH
+/* Ciphers for one time authentication such as poly1305 */
+typedef struct OneTimeAuth {
+#ifdef HAVE_POLY1305
+    Poly1305* poly1305;
+#endif
+    byte    setup;      /* flag for if a cipher has been set */
+
+} OneTimeAuth;
+#endif
+
+
+WOLFSSL_LOCAL void InitCiphers(WOLFSSL* ssl);
+WOLFSSL_LOCAL void FreeCiphers(WOLFSSL* ssl);
+
+
+/* hashes type */
+typedef struct Hashes {
+    #ifndef NO_OLD_TLS
+        byte md5[MD5_DIGEST_SIZE];
+    #endif
+    byte sha[SHA_DIGEST_SIZE];
+    #ifndef NO_SHA256
+        byte sha256[SHA256_DIGEST_SIZE];
+    #endif
+    #ifdef WOLFSSL_SHA384
+        byte sha384[SHA384_DIGEST_SIZE];
+    #endif
+    #ifdef WOLFSSL_SHA512
+        byte sha512[SHA512_DIGEST_SIZE];
+    #endif
+} Hashes;
+
+
+/* Static x509 buffer */
+typedef struct x509_buffer {
+    int  length;                  /* actual size */
+    byte buffer[MAX_X509_SIZE];   /* max static cert size */
+} x509_buffer;
+
+
+/* wolfSSL X509_CHAIN, for no dynamic memory SESSION_CACHE */
+struct WOLFSSL_X509_CHAIN {
+    int         count;                    /* total number in chain */
+    x509_buffer certs[MAX_CHAIN_DEPTH];   /* only allow max depth 4 for now */
+};
+
+
+/* wolfSSL session type */
+struct WOLFSSL_SESSION {
+    word32       bornOn;                        /* create time in seconds   */
+    word32       timeout;                       /* timeout in seconds       */
+    byte         sessionID[ID_LEN];             /* id for protocol */
+    byte         sessionIDSz;
+    byte         masterSecret[SECRET_LEN];      /* stored secret */
+#ifdef SESSION_CERTS
+    WOLFSSL_X509_CHAIN chain;                    /* peer cert chain, static  */
+    ProtocolVersion version;                    /* which version was used */
+    byte            cipherSuite0;               /* first byte, normally 0 */
+    byte            cipherSuite;                /* 2nd byte, actual suite */
+#endif
+#ifndef NO_CLIENT_CACHE
+    word16       idLen;                         /* serverID length */
+    byte         serverID[SERVER_ID_LEN];       /* for easier client lookup */
+#endif
+#ifdef HAVE_SESSION_TICKET
+    word16       ticketLen;
+    byte         ticket[SESSION_TICKET_LEN];
+#endif
+};
+
+
+WOLFSSL_LOCAL
+WOLFSSL_SESSION* GetSession(WOLFSSL*, byte*);
+WOLFSSL_LOCAL
+int          SetSession(WOLFSSL*, WOLFSSL_SESSION*);
+
+typedef int (*hmacfp) (WOLFSSL*, byte*, const byte*, word32, int, int);
+
+#ifndef NO_CLIENT_CACHE
+    WOLFSSL_SESSION* GetSessionClient(WOLFSSL*, const byte*, int);
+#endif
+
+/* client connect state for nonblocking restart */
+enum ConnectState {
+    CONNECT_BEGIN = 0,
+    CLIENT_HELLO_SENT,
+    HELLO_AGAIN,               /* HELLO_AGAIN s for DTLS case */
+    HELLO_AGAIN_REPLY,
+    FIRST_REPLY_DONE,
+    FIRST_REPLY_FIRST,
+    FIRST_REPLY_SECOND,
+    FIRST_REPLY_THIRD,
+    FIRST_REPLY_FOURTH,
+    FINISHED_DONE,
+    SECOND_REPLY_DONE
+};
+
+
+/* server accept state for nonblocking restart */
+enum AcceptState {
+    ACCEPT_BEGIN = 0,
+    ACCEPT_CLIENT_HELLO_DONE,
+    HELLO_VERIFY_SENT,
+    ACCEPT_FIRST_REPLY_DONE,
+    SERVER_HELLO_SENT,
+    CERT_SENT,
+    KEY_EXCHANGE_SENT,
+    CERT_REQ_SENT,
+    SERVER_HELLO_DONE,
+    ACCEPT_SECOND_REPLY_DONE,
+    TICKET_SENT,
+    CHANGE_CIPHER_SENT,
+    ACCEPT_FINISHED_DONE,
+    ACCEPT_THIRD_REPLY_DONE
+};
+
+
+typedef struct Buffers {
+    bufferStatic    inputBuffer;
+    bufferStatic    outputBuffer;
+    buffer          domainName;             /* for client check */
+    buffer          clearOutputBuffer;
+    int             prevSent;              /* previous plain text bytes sent
+                                              when got WANT_WRITE            */
+    int             plainSz;               /* plain text bytes in buffer to send
+                                              when got WANT_WRITE            */
+    byte            weOwnCert;             /* SSL own cert flag */
+    byte            weOwnCertChain;        /* SSL own cert chain flag */
+    byte            weOwnKey;              /* SSL own key  flag */
+    byte            weOwnDH;               /* SSL own dh (p,g)  flag */
+#ifndef NO_DH
+    buffer          serverDH_P;            /* WOLFSSL_CTX owns, unless we own */
+    buffer          serverDH_G;            /* WOLFSSL_CTX owns, unless we own */
+    buffer          serverDH_Pub;
+    buffer          serverDH_Priv;
+#endif
+#ifndef NO_CERTS
+    buffer          certificate;           /* WOLFSSL_CTX owns, unless we own */
+    buffer          key;                   /* WOLFSSL_CTX owns, unless we own */
+    buffer          certChain;             /* WOLFSSL_CTX owns, unless we own */
+                 /* chain after self, in DER, with leading size for each cert */
+#endif
+#ifdef WOLFSSL_DTLS
+    WOLFSSL_DTLS_CTX dtlsCtx;               /* DTLS connection context */
+#endif
+#ifdef HAVE_PK_CALLBACKS
+    #ifdef HAVE_ECC
+        buffer peerEccDsaKey;              /* we own for Ecc Verify Callbacks */
+    #endif /* HAVE_ECC */
+    #ifndef NO_RSA
+        buffer peerRsaKey;                 /* we own for Rsa Verify Callbacks */
+    #endif /* NO_RSA */
+#endif /* HAVE_PK_CALLBACKS */
+} Buffers;
+
+typedef struct Options {
+#ifndef NO_PSK
+    psk_client_callback client_psk_cb;
+    psk_server_callback server_psk_cb;
+    word16            havePSK:1;            /* psk key set by user */
+#endif /* NO_PSK */
+
+    /* on/off or small bit flags, optimize layout */
+    word16            sendVerify:2;     /* false = 0, true = 1, sendBlank = 2 */
+    word16            sessionCacheOff:1;
+    word16            sessionCacheFlushOff:1;
+    word16            side:1;             /* client or server end */
+    word16            verifyPeer:1;
+    word16            verifyNone:1;
+    word16            failNoCert:1;
+    word16            downgrade:1;        /* allow downgrade of versions */
+    word16            resuming:1;
+    word16            haveSessionId:1;    /* server may not send */
+    word16            tls:1;              /* using TLS ? */
+    word16            tls1_1:1;           /* using TLSv1.1+ ? */
+    word16            dtls:1;             /* using datagrams ? */
+    word16            connReset:1;        /* has the peer reset */
+    word16            isClosed:1;         /* if we consider conn closed */
+    word16            closeNotify:1;      /* we've recieved a close notify */
+    word16            sentNotify:1;       /* we've sent a close notify */
+    word16            usingCompression:1; /* are we using compression */
+    word16            haveRSA:1;          /* RSA available */
+    word16            haveDH:1;           /* server DH parms set by user */
+    word16            haveNTRU:1;         /* server NTRU  private key loaded */
+    word16            haveECDSAsig:1;     /* server ECDSA signed cert */
+    word16            haveStaticECC:1;    /* static server ECC private key */
+    word16            havePeerCert:1;     /* do we have peer's cert */
+    word16            havePeerVerify:1;   /* and peer's cert verify */
+    word16            usingPSK_cipher:1;  /* are using psk as cipher */
+    word16            usingAnon_cipher:1; /* are we using an anon cipher */
+    word16            sendAlertState:1;   /* nonblocking resume */
+    word16            partialWrite:1;     /* only one msg per write call */
+    word16            quietShutdown:1;    /* don't send close notify */
+    word16            certOnly:1;         /* stop once we get cert */
+    word16            groupMessages:1;    /* group handshake messages */
+    word16            usingNonblock:1;    /* are we using nonblocking socket */
+    word16            saveArrays:1;       /* save array Memory for user get keys
+                                           or psk */
+#ifdef HAVE_POLY1305
+    word16            oldPoly:1;        /* set when to use old rfc way of poly*/
+#endif
+#ifdef HAVE_ANON
+    word16            haveAnon:1;       /* User wants to allow Anon suites */
+#endif
+#ifdef HAVE_SESSION_TICKET
+    word16            createTicket:1;     /* Server to create new Ticket */
+    word16            useTicket:1;        /* Use Ticket not session cache */
+#endif
+
+    /* need full byte values for this section */
+    byte            processReply;           /* nonblocking resume */
+    byte            cipherSuite0;           /* first byte, normally 0 */
+    byte            cipherSuite;            /* second byte, actual suite */
+    byte            serverState;
+    byte            clientState;
+    byte            handShakeState;
+    byte            handShakeDone;      /* at least one handshake complete */
+    byte            minDowngrade;       /* minimum downgrade version */
+    byte            connectState;       /* nonblocking resume */
+    byte            acceptState;        /* nonblocking resume */
+#ifndef NO_DH
+    word16          minDhKeySz;         /* minimum DH key size */
+    word16          dhKeySz;            /* actual DH key size */
+#endif
+
+} Options;
+
+typedef struct Arrays {
+    word32          preMasterSz;        /* differs for DH, actual size */
+#ifndef NO_PSK
+    word32          psk_keySz;          /* acutal size */
+    char            client_identity[MAX_PSK_ID_LEN];
+    char            server_hint[MAX_PSK_ID_LEN];
+    byte            psk_key[MAX_PSK_KEY_LEN];
+#endif
+    byte            clientRandom[RAN_LEN];
+    byte            serverRandom[RAN_LEN];
+    byte            sessionID[ID_LEN];
+    byte            sessionIDSz;
+    byte            preMasterSecret[ENCRYPT_LEN];
+    byte            masterSecret[SECRET_LEN];
+#ifdef WOLFSSL_DTLS
+    byte            cookie[MAX_COOKIE_LEN];
+    byte            cookieSz;
+#endif
+} Arrays;
+
+#ifndef ASN_NAME_MAX
+#define ASN_NAME_MAX 256
+#endif
+
+#ifndef MAX_DATE_SZ
+#define MAX_DATE_SZ 32
+#endif
+
+struct WOLFSSL_X509_NAME {
+    char  *name;
+    char  staticName[ASN_NAME_MAX];
+    int   dynamicName;
+    int   sz;
+#ifdef OPENSSL_EXTRA
+    DecodedName fullName;
+#endif /* OPENSSL_EXTRA */
+};
+
+#ifndef EXTERNAL_SERIAL_SIZE
+    #define EXTERNAL_SERIAL_SIZE 32
+#endif
+
+#ifdef NO_ASN 
+    typedef struct DNS_entry DNS_entry;
+#endif
+
+struct WOLFSSL_X509 {
+    int              version;
+    WOLFSSL_X509_NAME issuer;
+    WOLFSSL_X509_NAME subject;
+    int              serialSz;
+    byte             serial[EXTERNAL_SERIAL_SIZE];
+    char             subjectCN[ASN_NAME_MAX];        /* common name short cut */
+#ifdef WOLFSSL_SEP
+    int              deviceTypeSz;
+    byte             deviceType[EXTERNAL_SERIAL_SIZE];
+    int              hwTypeSz;
+    byte             hwType[EXTERNAL_SERIAL_SIZE];
+    int              hwSerialNumSz;
+    byte             hwSerialNum[EXTERNAL_SERIAL_SIZE];
+    #ifdef OPENSSL_EXTRA
+        byte             certPolicySet;
+        byte             certPolicyCrit;
+    #endif /* OPENSSL_EXTRA */
+#endif
+    int              notBeforeSz;
+    byte             notBefore[MAX_DATE_SZ];
+    int              notAfterSz;
+    byte             notAfter[MAX_DATE_SZ];
+    int              sigOID;
+    buffer           sig;
+    int              pubKeyOID;
+    buffer           pubKey;
+    #ifdef HAVE_ECC
+        word32       pkCurveOID;
+    #endif /* HAVE_ECC */
+    buffer           derCert;                        /* may need  */
+    DNS_entry*       altNames;                       /* alt names list */
+    DNS_entry*       altNamesNext;                   /* hint for retrieval */
+    byte             dynamicMemory;                  /* dynamic memory flag */
+    byte             isCa;
+#ifdef OPENSSL_EXTRA
+    word32           pathLength;
+    word16           keyUsage;
+    byte             basicConstSet;
+    byte             basicConstCrit;
+    byte             basicConstPlSet;
+    byte             subjAltNameSet;
+    byte             subjAltNameCrit;
+    byte             authKeyIdSet;
+    byte             authKeyIdCrit;
+    byte*            authKeyId;
+    word32           authKeyIdSz;
+    byte             subjKeyIdSet;
+    byte             subjKeyIdCrit;
+    byte*            subjKeyId;
+    word32           subjKeyIdSz;
+    byte             keyUsageSet;
+    byte             keyUsageCrit;
+#endif /* OPENSSL_EXTRA */
+};
+
+
+/* record layer header for PlainText, Compressed, and CipherText */
+typedef struct RecordLayerHeader {
+    byte            type;
+    byte            pvMajor;
+    byte            pvMinor;
+    byte            length[2];
+} RecordLayerHeader;
+
+
+/* record layer header for DTLS PlainText, Compressed, and CipherText */
+typedef struct DtlsRecordLayerHeader {
+    byte            type;
+    byte            pvMajor;
+    byte            pvMinor;
+    byte            epoch[2];             /* increment on cipher state change */
+    byte            sequence_number[6];   /* per record */
+    byte            length[2];
+} DtlsRecordLayerHeader;
+
+
+typedef struct DtlsPool {
+    buffer          buf[DTLS_POOL_SZ];
+    int             used;
+} DtlsPool;
+
+typedef struct DtlsMsg {
+    struct DtlsMsg* next;
+    word32          seq;       /* Handshake sequence number    */
+    word32          sz;        /* Length of whole mesage       */
+    word32          fragSz;    /* Length of fragments received */
+    byte            type;
+    byte*           buf;
+    byte*           msg;
+} DtlsMsg;
+
+
+#ifdef HAVE_NETX
+
+    /* NETX I/O Callback default */
+    typedef struct NetX_Ctx {
+        NX_TCP_SOCKET* nxSocket;    /* send/recv socket handle */
+        NX_PACKET*     nxPacket;    /* incoming packet handle for short reads */
+        ULONG          nxOffset;    /* offset already read from nxPacket */
+        ULONG          nxWait;      /* wait option flag */
+    } NetX_Ctx;
+
+#endif
+
+
+/* Handshake messages recevied from peer (plus change cipher */
+typedef struct MsgsReceived {
+    word16 got_hello_request:1;
+    word16 got_client_hello:1;
+    word16 got_server_hello:1;
+    word16 got_hello_verify_request:1;
+    word16 got_session_ticket:1;
+    word16 got_certificate:1;
+    word16 got_server_key_exchange:1;
+    word16 got_certificate_request:1;
+    word16 got_server_hello_done:1;
+    word16 got_certificate_verify:1;
+    word16 got_client_key_exchange:1;
+    word16 got_finished:1;
+    word16 got_change_cipher:1;
+} MsgsReceived;
+
+
+/* Handshake hashes */
+typedef struct HS_Hashes {
+    Hashes          verifyHashes;
+    Hashes          certHashes;         /* for cert verify */
+#ifndef NO_OLD_TLS
+#ifndef NO_SHA
+    Sha             hashSha;            /* sha hash of handshake msgs */
+#endif
+#ifndef NO_MD5
+    Md5             hashMd5;            /* md5 hash of handshake msgs */
+#endif
+#endif /* NO_OLD_TLS */
+#ifndef NO_SHA256
+    Sha256          hashSha256;         /* sha256 hash of handshake msgs */
+#endif
+#ifdef WOLFSSL_SHA384
+    Sha384          hashSha384;         /* sha384 hash of handshake msgs */
+#endif
+#ifdef WOLFSSL_SHA512
+    Sha512          hashSha512;         /* sha512 hash of handshake msgs */
+#endif
+} HS_Hashes;
+
+
+/* wolfSSL ssl type */
+struct WOLFSSL {
+    WOLFSSL_CTX*    ctx;
+    Suites*         suites;             /* only need during handshake */
+    Arrays*         arrays;
+    HS_Hashes*      hsHashes;
+    void*           IOCB_ReadCtx;
+    void*           IOCB_WriteCtx;
+    RNG*            rng;
+    void*           verifyCbCtx;        /* cert verify callback user ctx*/
+    VerifyCallback  verifyCallback;     /* cert verification callback */
+    void*           heap;               /* for user overrides */
+#ifndef NO_HANDSHAKE_DONE_CB
+    HandShakeDoneCb hsDoneCb;          /*  notify user handshake done */
+    void*           hsDoneCtx;         /*  user handshake cb context  */
+#endif
+    WOLFSSL_CIPHER  cipher;
+    hmacfp          hmac;
+    Ciphers         encrypt;
+    Ciphers         decrypt;
+    Buffers         buffers;
+    WOLFSSL_SESSION session;
+    WOLFSSL_ALERT_HISTORY alert_history;
+    int             error;
+    int             rfd;                /* read  file descriptor */
+    int             wfd;                /* write file descriptor */
+    int             rflags;             /* user read  flags */
+    int             wflags;             /* user write flags */
+    word32          timeout;            /* session timeout */
+    word16          curSize;
+    RecordLayerHeader curRL;
+    MsgsReceived    msgsReceived;       /* peer messages received */
+    ProtocolVersion version;            /* negotiated version */
+    ProtocolVersion chVersion;          /* client hello version */
+    CipherSpecs     specs;
+    Keys            keys;
+    Options         options;
+#ifdef OPENSSL_EXTRA
+    WOLFSSL_BIO*     biord;              /* socket bio read  to free/close */
+    WOLFSSL_BIO*     biowr;              /* socket bio write to free/close */
+#endif
+#ifndef NO_RSA
+    RsaKey*         peerRsaKey;
+    byte            peerRsaKeyPresent;
+#endif
+#ifdef HAVE_NTRU
+    word16          peerNtruKeyLen;
+    byte            peerNtruKey[MAX_NTRU_PUB_KEY_SZ];
+    byte            peerNtruKeyPresent;
+#endif
+#ifdef HAVE_ECC
+    ecc_key*        peerEccKey;              /* peer's  ECDHE key */
+    ecc_key*        peerEccDsaKey;           /* peer's  ECDSA key */
+    ecc_key*        eccTempKey;              /* private ECDHE key */
+    word32          pkCurveOID;              /* curve Ecc_Sum     */
+    word16          eccTempKeySz;            /* in octets 20 - 66 */
+    byte            peerEccKeyPresent;
+    byte            peerEccDsaKeyPresent;
+    byte            eccTempKeyPresent;
+#endif
+#ifdef HAVE_LIBZ
+    z_stream        c_stream;           /* compression   stream */
+    z_stream        d_stream;           /* decompression stream */
+    byte            didStreamInit;      /* for stream init and end */
+#endif
+#ifdef WOLFSSL_DTLS
+    int             dtls_timeout_init;  /* starting timeout vaule */
+    int             dtls_timeout_max;   /* maximum timeout value */
+    int             dtls_timeout;       /* current timeout value, changes */
+    DtlsPool*       dtls_pool;
+    DtlsMsg*        dtls_msg_list;
+    void*           IOCB_CookieCtx;     /* gen cookie ctx */
+    word32          dtls_expected_rx;
+#endif
+#ifdef WOLFSSL_CALLBACKS
+    HandShakeInfo   handShakeInfo;      /* info saved during handshake */
+    TimeoutInfo     timeoutInfo;        /* info saved during handshake */
+    byte            hsInfoOn;           /* track handshake info        */
+    byte            toInfoOn;           /* track timeout   info        */
+#endif
+#ifdef HAVE_FUZZER
+    CallbackFuzzer  fuzzerCb;           /* for testing with using fuzzer */
+    void*           fuzzerCtx;          /* user defined pointer */
+#endif
+#ifdef KEEP_PEER_CERT
+    WOLFSSL_X509     peerCert;           /* X509 peer cert */
+#endif
+#ifdef FORTRESS
+    void*           ex_data[MAX_EX_DATA]; /* external data, for Fortress */
+#endif
+#ifdef HAVE_CAVIUM
+    int              devId;            /* cavium device id to use */
+#endif
+#ifdef HAVE_ONE_TIME_AUTH
+    OneTimeAuth     auth;
+#endif
+#ifdef HAVE_TLS_EXTENSIONS
+    TLSX* extensions;                  /* RFC 6066 TLS Extensions data */
+    #ifdef HAVE_MAX_FRAGMENT
+        word16 max_fragment;
+    #endif
+    #ifdef HAVE_TRUNCATED_HMAC
+        byte truncated_hmac;
+    #endif
+    #ifdef HAVE_SECURE_RENEGOTIATION
+        SecureRenegotiation* secure_renegotiation; /* valid pointer indicates */
+    #endif                                         /* user turned on */
+    #if !defined(NO_WOLFSSL_CLIENT) && defined(HAVE_SESSION_TICKET)
+        CallbackSessionTicket session_ticket_cb;
+        void*                 session_ticket_ctx;
+        byte                  expect_session_ticket;
+    #endif
+#endif /* HAVE_TLS_EXTENSIONS */
+#ifdef HAVE_NETX
+    NetX_Ctx        nxCtx;             /* NetX IO Context */
+#endif
+#ifdef SESSION_INDEX
+    int sessionIndex;                  /* Session's location in the cache. */
+#endif
+#ifdef ATOMIC_USER
+    void*    MacEncryptCtx;    /* Atomic User Mac/Encrypt Callback Context */
+    void*    DecryptVerifyCtx; /* Atomic User Decrypt/Verify Callback Context */
+#endif
+#ifdef HAVE_PK_CALLBACKS
+    #ifdef HAVE_ECC
+        void* EccSignCtx;     /* Ecc Sign   Callback Context */
+        void* EccVerifyCtx;   /* Ecc Verify Callback Context */
+    #endif /* HAVE_ECC */
+    #ifndef NO_RSA
+        void* RsaSignCtx;     /* Rsa Sign   Callback Context */
+        void* RsaVerifyCtx;   /* Rsa Verify Callback Context */
+        void* RsaEncCtx;      /* Rsa Public  Encrypt   Callback Context */
+        void* RsaDecCtx;      /* Rsa Private Decrypt   Callback Context */
+    #endif /* NO_RSA */
+#endif /* HAVE_PK_CALLBACKS */
+#ifdef HAVE_SECRET_CALLBACK
+        SessionSecretCb sessionSecretCb;
+        void*           sessionSecretCtx;
+#endif /* HAVE_SECRET_CALLBACK */
+};
+
+
+WOLFSSL_LOCAL
+int  InitSSL(WOLFSSL*, WOLFSSL_CTX*);
+WOLFSSL_LOCAL
+void FreeSSL(WOLFSSL*);
+WOLFSSL_API void SSL_ResourceFree(WOLFSSL*);   /* Micrium uses */
+
+
+enum {
+    IV_SZ   = 32,          /* max iv sz */
+    NAME_SZ = 80          /* max one line */
+};
+
+
+typedef struct EncryptedInfo {
+    char     name[NAME_SZ];    /* encryption name */
+    byte     iv[IV_SZ];        /* encrypted IV */
+    word32   ivSz;             /* encrypted IV size */
+    long     consumed;         /* tracks PEM bytes consumed */
+    byte     set;              /* if encryption set */
+    WOLFSSL_CTX* ctx;              /* CTX owner */
+} EncryptedInfo;
+
+
+#ifndef NO_CERTS
+    WOLFSSL_LOCAL int PemToDer(const unsigned char* buff, long sz, int type,
+                              buffer* der, void* heap, EncryptedInfo* info,
+                              int* eccKey);
+
+    WOLFSSL_LOCAL int ProcessFile(WOLFSSL_CTX* ctx, const char* fname, int format,
+                                 int type, WOLFSSL* ssl, int userChain,
+                                WOLFSSL_CRL* crl);
+#endif
+
+
+#ifdef WOLFSSL_CALLBACKS
+    WOLFSSL_LOCAL
+    void InitHandShakeInfo(HandShakeInfo*);
+    WOLFSSL_LOCAL 
+    void FinishHandShakeInfo(HandShakeInfo*, const WOLFSSL*);
+    WOLFSSL_LOCAL 
+    void AddPacketName(const char*, HandShakeInfo*);
+
+    WOLFSSL_LOCAL
+    void InitTimeoutInfo(TimeoutInfo*);
+    WOLFSSL_LOCAL 
+    void FreeTimeoutInfo(TimeoutInfo*, void*);
+    WOLFSSL_LOCAL 
+    void AddPacketInfo(const char*, TimeoutInfo*, const byte*, int, void*);
+    WOLFSSL_LOCAL 
+    void AddLateName(const char*, TimeoutInfo*);
+    WOLFSSL_LOCAL 
+    void AddLateRecordHeader(const RecordLayerHeader* rl, TimeoutInfo* info);
+#endif
+
+
+/* Record Layer Header identifier from page 12 */
+enum ContentType {
+    no_type            = 0,
+    change_cipher_spec = 20, 
+    alert              = 21, 
+    handshake          = 22, 
+    application_data   = 23 
+};
+
+
+/* handshake header, same for each message type, pgs 20/21 */
+typedef struct HandShakeHeader {
+    byte            type;
+    word24          length;
+} HandShakeHeader;
+
+
+/* DTLS handshake header, same for each message type */
+typedef struct DtlsHandShakeHeader {
+    byte            type;
+    word24          length;
+    byte            message_seq[2];    /* start at 0, restransmit gets same # */
+    word24          fragment_offset;   /* bytes in previous fragments */
+    word24          fragment_length;   /* length of this fragment */
+} DtlsHandShakeHeader;
+
+
+enum HandShakeType {
+    no_shake            = -1,
+    hello_request       = 0, 
+    client_hello        = 1, 
+    server_hello        = 2,
+    hello_verify_request = 3,       /* DTLS addition */
+    session_ticket      =  4,
+    certificate         = 11, 
+    server_key_exchange = 12,
+    certificate_request = 13, 
+    server_hello_done   = 14,
+    certificate_verify  = 15, 
+    client_key_exchange = 16,
+    finished            = 20,
+    certificate_status  = 22,
+    change_cipher_hs    = 55      /* simulate unique handshake type for sanity
+                                     checks.  record layer change_cipher
+                                     conflicts with handshake finished */
+};
+
+
+static const byte client[SIZEOF_SENDER] = { 0x43, 0x4C, 0x4E, 0x54 };
+static const byte server[SIZEOF_SENDER] = { 0x53, 0x52, 0x56, 0x52 };
+
+static const byte tls_client[FINISHED_LABEL_SZ + 1] = "client finished";
+static const byte tls_server[FINISHED_LABEL_SZ + 1] = "server finished";
+
+
+/* internal functions */
+WOLFSSL_LOCAL int SendChangeCipher(WOLFSSL*);
+WOLFSSL_LOCAL int SendTicket(WOLFSSL*);
+WOLFSSL_LOCAL int DoClientTicket(WOLFSSL*, const byte*, word32);
+WOLFSSL_LOCAL int SendData(WOLFSSL*, const void*, int);
+WOLFSSL_LOCAL int SendCertificate(WOLFSSL*);
+WOLFSSL_LOCAL int SendCertificateRequest(WOLFSSL*);
+WOLFSSL_LOCAL int SendServerKeyExchange(WOLFSSL*);
+WOLFSSL_LOCAL int SendBuffered(WOLFSSL*);
+WOLFSSL_LOCAL int ReceiveData(WOLFSSL*, byte*, int, int);
+WOLFSSL_LOCAL int SendFinished(WOLFSSL*);
+WOLFSSL_LOCAL int SendAlert(WOLFSSL*, int, int);
+WOLFSSL_LOCAL int ProcessReply(WOLFSSL*);
+
+WOLFSSL_LOCAL int SetCipherSpecs(WOLFSSL*);
+WOLFSSL_LOCAL int MakeMasterSecret(WOLFSSL*);
+
+WOLFSSL_LOCAL int  AddSession(WOLFSSL*);
+WOLFSSL_LOCAL int  DeriveKeys(WOLFSSL* ssl);
+WOLFSSL_LOCAL int  StoreKeys(WOLFSSL* ssl, const byte* keyData);
+
+WOLFSSL_LOCAL int IsTLS(const WOLFSSL* ssl);
+WOLFSSL_LOCAL int IsAtLeastTLSv1_2(const WOLFSSL* ssl);
+
+WOLFSSL_LOCAL void FreeHandshakeResources(WOLFSSL* ssl);
+WOLFSSL_LOCAL void ShrinkInputBuffer(WOLFSSL* ssl, int forcedFree);
+WOLFSSL_LOCAL void ShrinkOutputBuffer(WOLFSSL* ssl);
+
+WOLFSSL_LOCAL int VerifyClientSuite(WOLFSSL* ssl);
+#ifndef NO_CERTS
+    WOLFSSL_LOCAL Signer* GetCA(void* cm, byte* hash);
+    #ifndef NO_SKID
+        WOLFSSL_LOCAL Signer* GetCAByName(void* cm, byte* hash);
+    #endif
+#endif
+WOLFSSL_LOCAL int  BuildTlsFinished(WOLFSSL* ssl, Hashes* hashes,
+                                   const byte* sender);
+WOLFSSL_LOCAL void FreeArrays(WOLFSSL* ssl, int keep);
+WOLFSSL_LOCAL  int CheckAvailableSize(WOLFSSL *ssl, int size);
+WOLFSSL_LOCAL  int GrowInputBuffer(WOLFSSL* ssl, int size, int usedLength);
+
+#ifndef NO_TLS
+    WOLFSSL_LOCAL int  MakeTlsMasterSecret(WOLFSSL*);
+    WOLFSSL_LOCAL int  TLS_hmac(WOLFSSL* ssl, byte* digest, const byte* in,
+                               word32 sz, int content, int verify);
+#endif
+
+#ifndef NO_WOLFSSL_CLIENT
+    WOLFSSL_LOCAL int SendClientHello(WOLFSSL*);
+    WOLFSSL_LOCAL int SendClientKeyExchange(WOLFSSL*);
+    WOLFSSL_LOCAL int SendCertificateVerify(WOLFSSL*);
+#endif /* NO_WOLFSSL_CLIENT */
+
+#ifndef NO_WOLFSSL_SERVER
+    WOLFSSL_LOCAL int SendServerHello(WOLFSSL*);
+    WOLFSSL_LOCAL int SendServerHelloDone(WOLFSSL*);
+    #ifdef WOLFSSL_DTLS
+        WOLFSSL_LOCAL int SendHelloVerifyRequest(WOLFSSL*);
+    #endif
+#endif /* NO_WOLFSSL_SERVER */
+
+#ifdef WOLFSSL_DTLS
+    WOLFSSL_LOCAL int  DtlsPoolInit(WOLFSSL*);
+    WOLFSSL_LOCAL int  DtlsPoolSave(WOLFSSL*, const byte*, int);
+    WOLFSSL_LOCAL int  DtlsPoolTimeout(WOLFSSL*);
+    WOLFSSL_LOCAL int  DtlsPoolSend(WOLFSSL*);
+    WOLFSSL_LOCAL void DtlsPoolReset(WOLFSSL*);
+
+    WOLFSSL_LOCAL DtlsMsg* DtlsMsgNew(word32, void*);
+    WOLFSSL_LOCAL void DtlsMsgDelete(DtlsMsg*, void*);
+    WOLFSSL_LOCAL void DtlsMsgListDelete(DtlsMsg*, void*);
+    WOLFSSL_LOCAL void DtlsMsgSet(DtlsMsg*, word32, const byte*, byte,
+                                                             word32, word32);
+    WOLFSSL_LOCAL DtlsMsg* DtlsMsgFind(DtlsMsg*, word32);
+    WOLFSSL_LOCAL DtlsMsg* DtlsMsgStore(DtlsMsg*, word32, const byte*, word32,
+                                                byte, word32, word32, void*);
+    WOLFSSL_LOCAL DtlsMsg* DtlsMsgInsert(DtlsMsg*, DtlsMsg*);
+#endif /* WOLFSSL_DTLS */
+
+#ifndef NO_TLS
+    
+
+#endif /* NO_TLS */
+
+
+WOLFSSL_LOCAL word32  LowResTimer(void);
+
+WOLFSSL_LOCAL void InitX509Name(WOLFSSL_X509_NAME*, int);
+WOLFSSL_LOCAL void FreeX509Name(WOLFSSL_X509_NAME* name);
+WOLFSSL_LOCAL void InitX509(WOLFSSL_X509*, int);
+WOLFSSL_LOCAL void FreeX509(WOLFSSL_X509*);
+#ifndef NO_CERTS
+    WOLFSSL_LOCAL int  CopyDecodedToX509(WOLFSSL_X509*, DecodedCert*);
+#endif
+
+/* used by ssl.c and wolfssl_int.c */
+WOLFSSL_LOCAL void c32to24(word32 in, word24 out);
+
+WOLFSSL_LOCAL const char* const* GetCipherNames(void);
+WOLFSSL_LOCAL int GetCipherNamesSize(void);
+
+
+enum encrypt_side {
+    ENCRYPT_SIDE_ONLY = 1,
+    DECRYPT_SIDE_ONLY,
+    ENCRYPT_AND_DECRYPT_SIDE
+};
+
+WOLFSSL_LOCAL int SetKeysSide(WOLFSSL*, enum encrypt_side);
+
+
+#ifdef __cplusplus
+    }  /* extern "C" */
+#endif
+
+#endif /* wolfSSL_INT_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/ocsp.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/ocsp.h
new file mode 100644
index 0000000..77a4157
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/ocsp.h
@@ -0,0 +1,52 @@
+/* ocsp.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+/* wolfSSL OCSP API */
+
+#ifndef WOLFSSL_OCSP_H
+#define WOLFSSL_OCSP_H
+
+#ifdef HAVE_OCSP
+
+#include 
+#include 
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+typedef struct WOLFSSL_OCSP WOLFSSL_OCSP;
+
+WOLFSSL_LOCAL int  InitOCSP(WOLFSSL_OCSP*, WOLFSSL_CERT_MANAGER*);
+WOLFSSL_LOCAL void FreeOCSP(WOLFSSL_OCSP*, int dynamic);
+
+WOLFSSL_LOCAL int  CheckCertOCSP(WOLFSSL_OCSP*, DecodedCert*);
+
+#ifdef __cplusplus
+    }  /* extern "C" */
+#endif
+
+
+#endif /* HAVE_OCSP */
+#endif /* WOLFSSL_OCSP_H */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/asn1.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/asn1.h
new file mode 100644
index 0000000..3f34d7d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/asn1.h
@@ -0,0 +1,2 @@
+/* asn1.h for openssl */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/bio.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/bio.h
new file mode 100644
index 0000000..5f1d421
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/bio.h
@@ -0,0 +1,23 @@
+/* bio.h for openssl */
+
+
+#ifndef WOLFSSL_BIO_H_
+#define WOLFSSL_BIO_H_
+
+#include 
+
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+
+
+
+#ifdef __cplusplus
+    }  /* extern "C" */ 
+#endif
+
+
+#endif /* WOLFSSL_BIO_H_ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/bn.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/bn.h
new file mode 100644
index 0000000..4d81eb1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/bn.h
@@ -0,0 +1,115 @@
+/* bn.h for openssl */
+
+
+#ifndef WOLFSSL_BN_H_
+#define WOLFSSL_BN_H_
+
+#include 
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+typedef struct WOLFSSL_BIGNUM {
+    int   neg;              /* openssh deference */
+    void* internal;         /* our big num */
+} WOLFSSL_BIGNUM;
+
+
+typedef struct WOLFSSL_BN_CTX WOLFSSL_BN_CTX;
+
+
+WOLFSSL_API WOLFSSL_BN_CTX* wolfSSL_BN_CTX_new(void);
+WOLFSSL_API void           wolfSSL_BN_CTX_init(WOLFSSL_BN_CTX*);
+WOLFSSL_API void           wolfSSL_BN_CTX_free(WOLFSSL_BN_CTX*);
+
+WOLFSSL_API WOLFSSL_BIGNUM* wolfSSL_BN_new(void);
+WOLFSSL_API void           wolfSSL_BN_free(WOLFSSL_BIGNUM*);
+WOLFSSL_API void           wolfSSL_BN_clear_free(WOLFSSL_BIGNUM*);
+
+
+WOLFSSL_API int wolfSSL_BN_sub(WOLFSSL_BIGNUM*, const WOLFSSL_BIGNUM*,
+	                         const WOLFSSL_BIGNUM*);
+WOLFSSL_API int wolfSSL_BN_mod(WOLFSSL_BIGNUM*, const WOLFSSL_BIGNUM*,
+	                         const WOLFSSL_BIGNUM*, const WOLFSSL_BN_CTX*);
+
+WOLFSSL_API const WOLFSSL_BIGNUM* wolfSSL_BN_value_one(void);
+
+
+WOLFSSL_API int wolfSSL_BN_num_bytes(const WOLFSSL_BIGNUM*);
+WOLFSSL_API int wolfSSL_BN_num_bits(const WOLFSSL_BIGNUM*);
+
+WOLFSSL_API int wolfSSL_BN_is_zero(const WOLFSSL_BIGNUM*);
+WOLFSSL_API int wolfSSL_BN_is_one(const WOLFSSL_BIGNUM*);
+WOLFSSL_API int wolfSSL_BN_is_odd(const WOLFSSL_BIGNUM*);
+
+WOLFSSL_API int wolfSSL_BN_cmp(const WOLFSSL_BIGNUM*, const WOLFSSL_BIGNUM*);
+
+WOLFSSL_API int wolfSSL_BN_bn2bin(const WOLFSSL_BIGNUM*, unsigned char*);
+WOLFSSL_API WOLFSSL_BIGNUM* wolfSSL_BN_bin2bn(const unsigned char*, int len,
+	                            WOLFSSL_BIGNUM* ret);
+
+WOLFSSL_API int wolfSSL_mask_bits(WOLFSSL_BIGNUM*, int n);
+
+WOLFSSL_API int wolfSSL_BN_rand(WOLFSSL_BIGNUM*, int bits, int top, int bottom);
+WOLFSSL_API int wolfSSL_BN_is_bit_set(const WOLFSSL_BIGNUM*, int n);
+WOLFSSL_API int wolfSSL_BN_hex2bn(WOLFSSL_BIGNUM**, const char* str);
+
+WOLFSSL_API WOLFSSL_BIGNUM* wolfSSL_BN_dup(const WOLFSSL_BIGNUM*);
+WOLFSSL_API WOLFSSL_BIGNUM* wolfSSL_BN_copy(WOLFSSL_BIGNUM*, const WOLFSSL_BIGNUM*);
+
+WOLFSSL_API int wolfSSL_BN_set_word(WOLFSSL_BIGNUM*, unsigned long w);
+
+WOLFSSL_API int   wolfSSL_BN_dec2bn(WOLFSSL_BIGNUM**, const char* str);
+WOLFSSL_API char* wolfSSL_BN_bn2dec(const WOLFSSL_BIGNUM*);
+
+
+typedef WOLFSSL_BIGNUM BIGNUM;
+typedef WOLFSSL_BN_CTX BN_CTX;
+
+#define BN_CTX_new        wolfSSL_BN_CTX_new
+#define BN_CTX_init       wolfSSL_BN_CTX_init
+#define BN_CTX_free       wolfSSL_BN_CTX_free
+
+#define BN_new        wolfSSL_BN_new
+#define BN_free       wolfSSL_BN_free
+#define BN_clear_free wolfSSL_BN_clear_free
+
+#define BN_num_bytes wolfSSL_BN_num_bytes
+#define BN_num_bits  wolfSSL_BN_num_bits
+
+#define BN_is_zero  wolfSSL_BN_is_zero
+#define BN_is_one   wolfSSL_BN_is_one
+#define BN_is_odd   wolfSSL_BN_is_odd
+
+#define BN_cmp    wolfSSL_BN_cmp
+
+#define BN_bn2bin  wolfSSL_BN_bn2bin
+#define BN_bin2bn  wolfSSL_BN_bin2bn
+
+#define BN_mod       wolfSSL_BN_mod
+#define BN_sub       wolfSSL_BN_sub
+#define BN_value_one wolfSSL_BN_value_one
+
+#define BN_mask_bits wolfSSL_mask_bits
+
+#define BN_rand       wolfSSL_BN_rand
+#define BN_is_bit_set wolfSSL_BN_is_bit_set
+#define BN_hex2bn     wolfSSL_BN_hex2bn
+
+#define BN_dup  wolfSSL_BN_dup
+#define BN_copy wolfSSL_BN_copy
+
+#define BN_set_word wolfSSL_BN_set_word
+
+#define BN_dec2bn wolfSSL_BN_dec2bn
+#define BN_bn2dec wolfSSL_BN_bn2dec
+
+
+#ifdef __cplusplus
+    }  /* extern "C" */ 
+#endif
+
+
+#endif /* WOLFSSL__H_ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/conf.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/conf.h
new file mode 100644
index 0000000..1e328cf
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/conf.h
@@ -0,0 +1,2 @@
+/* conf.h for openssl */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/crypto.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/crypto.h
new file mode 100644
index 0000000..8f7c6f4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/crypto.h
@@ -0,0 +1,26 @@
+/* crypto.h for openSSL */
+
+#ifndef WOLFSSL_CRYPTO_H_
+#define WOLFSSL_CRYPTO_H_
+
+
+#include 
+
+#ifdef WOLFSSL_PREFIX
+#include "prefix_crypto.h"
+#endif
+
+
+WOLFSSL_API const char*   wolfSSLeay_version(int type);
+WOLFSSL_API unsigned long wolfSSLeay(void);
+
+#define SSLeay_version wolfSSLeay_version
+#define SSLeay wolfSSLeay
+
+
+#define SSLEAY_VERSION 0x0090600fL
+#define SSLEAY_VERSION_NUMBER SSLEAY_VERSION
+
+
+#endif /* header */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/des.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/des.h
new file mode 100644
index 0000000..f5b4f2a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/des.h
@@ -0,0 +1,106 @@
+/* des.h
+ *
+ * Copyright (C) 2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as wolfSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+/*  des.h defines mini des openssl compatibility layer 
+ *
+ */
+
+
+#ifndef WOLFSSL_DES_H_
+#define WOLFSSL_DES_H_
+
+#include 
+
+#ifndef NO_DES3
+
+#ifdef WOLFSSL_PREFIX
+#include "prefix_des.h"
+#endif
+
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+typedef unsigned char WOLFSSL_DES_cblock[8];
+typedef /* const */ WOLFSSL_DES_cblock WOLFSSL_const_DES_cblock;
+typedef WOLFSSL_DES_cblock WOLFSSL_DES_key_schedule;
+
+
+enum {
+    DES_ENCRYPT = 1,
+    DES_DECRYPT = 0
+};
+
+
+WOLFSSL_API void wolfSSL_DES_set_key_unchecked(WOLFSSL_const_DES_cblock*,
+                                             WOLFSSL_DES_key_schedule*);
+WOLFSSL_API int  wolfSSL_DES_key_sched(WOLFSSL_const_DES_cblock* key,
+                                     WOLFSSL_DES_key_schedule* schedule);
+WOLFSSL_API void wolfSSL_DES_cbc_encrypt(const unsigned char* input,
+                     unsigned char* output, long length,
+                     WOLFSSL_DES_key_schedule* schedule, WOLFSSL_DES_cblock* ivec,
+                     int enc);
+WOLFSSL_API void wolfSSL_DES_ncbc_encrypt(const unsigned char* input,
+                      unsigned char* output, long length,
+                      WOLFSSL_DES_key_schedule* schedule,
+                      WOLFSSL_DES_cblock* ivec, int enc);
+
+WOLFSSL_API void wolfSSL_DES_set_odd_parity(WOLFSSL_DES_cblock*);
+WOLFSSL_API void wolfSSL_DES_ecb_encrypt(WOLFSSL_DES_cblock*, WOLFSSL_DES_cblock*,
+                                       WOLFSSL_DES_key_schedule*, int);
+
+
+typedef WOLFSSL_DES_cblock DES_cblock;
+typedef WOLFSSL_const_DES_cblock const_DES_cblock;
+typedef WOLFSSL_DES_key_schedule DES_key_schedule;
+
+#define DES_set_key_unchecked wolfSSL_DES_set_key_unchecked
+#define DES_key_sched wolfSSL_DES_key_sched
+#define DES_cbc_encrypt wolfSSL_DES_cbc_encrypt
+#define DES_ncbc_encrypt wolfSSL_DES_ncbc_encrypt
+#define DES_set_odd_parity wolfSSL_DES_set_odd_parity
+#define DES_ecb_encrypt wolfSSL_DES_ecb_encrypt
+#define DES_ede3_cbc_encrypt(input, output, sz, ks1, ks2, ks3, ivec, enc) \
+do {                                                         \
+    Des3 des;                                                \
+    byte key[24];/* EDE uses 24 size key */                  \
+    memcpy(key, (ks1), DES_BLOCK_SIZE);                      \
+    memcpy(&key[DES_BLOCK_SIZE], (ks2), DES_BLOCK_SIZE);     \
+    memcpy(&key[DES_BLOCK_SIZE * 2], (ks3), DES_BLOCK_SIZE); \
+    if (enc) {                                               \
+        wc_Des3_SetKey(&des, key, (const byte*)(ivec), DES_ENCRYPTION);    \
+        wc_Des3_CbcEncrypt(&des, (output), (input), (sz));    \
+    }                                                         \
+    else {                                                    \
+        wc_Des3_SetKey(&des, key, (const byte*)(ivec), DES_ENCRYPTION);    \
+        wc_Des3_CbcDecrypt(&des, (output), (input), (sz));    \
+    }                                                         \
+} while(0)
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* NO_DES3 */
+
+#endif /* WOLFSSL_DES_H_ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/dh.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/dh.h
new file mode 100644
index 0000000..071abf7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/dh.h
@@ -0,0 +1,52 @@
+/* dh.h for openSSL */
+
+
+#ifndef WOLFSSL_DH_H_
+#define WOLFSSL_DH_H_
+
+
+#include 
+#include 
+
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+
+
+
+typedef struct WOLFSSL_DH {
+	WOLFSSL_BIGNUM* p;
+	WOLFSSL_BIGNUM* g;
+    WOLFSSL_BIGNUM* pub_key;      /* openssh deference g^x */
+    WOLFSSL_BIGNUM* priv_key;     /* openssh deference x   */
+    void*          internal;     /* our DH */
+    char           inSet;        /* internal set from external ? */
+    char           exSet;        /* external set from internal ? */
+} WOLFSSL_DH;
+
+
+WOLFSSL_API WOLFSSL_DH* wolfSSL_DH_new(void);
+WOLFSSL_API void       wolfSSL_DH_free(WOLFSSL_DH*);
+
+WOLFSSL_API int wolfSSL_DH_size(WOLFSSL_DH*);
+WOLFSSL_API int wolfSSL_DH_generate_key(WOLFSSL_DH*);
+WOLFSSL_API int wolfSSL_DH_compute_key(unsigned char* key, WOLFSSL_BIGNUM* pub,
+                                     WOLFSSL_DH*);
+
+typedef WOLFSSL_DH DH;
+
+#define DH_new  wolfSSL_DH_new 
+#define DH_free wolfSSL_DH_free
+
+#define DH_size         wolfSSL_DH_size
+#define DH_generate_key wolfSSL_DH_generate_key
+#define DH_compute_key  wolfSSL_DH_compute_key
+
+
+#ifdef __cplusplus
+    }  /* extern "C" */ 
+#endif
+
+#endif /* header */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/dsa.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/dsa.h
new file mode 100644
index 0000000..7255670
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/dsa.h
@@ -0,0 +1,53 @@
+/* dsa.h for openSSL */
+
+
+#ifndef WOLFSSL_DSA_H_
+#define WOLFSSL_DSA_H_
+
+
+#include 
+#include 
+
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+
+
+struct WOLFSSL_DSA {
+	WOLFSSL_BIGNUM* p;
+	WOLFSSL_BIGNUM* q;
+	WOLFSSL_BIGNUM* g;
+	WOLFSSL_BIGNUM* pub_key;      /* our y */
+	WOLFSSL_BIGNUM* priv_key;     /* our x */
+    void*          internal;     /* our Dsa Key */
+    char           inSet;        /* internal set from external ? */
+    char           exSet;        /* external set from internal ? */
+};
+
+
+WOLFSSL_API WOLFSSL_DSA* wolfSSL_DSA_new(void);
+WOLFSSL_API void        wolfSSL_DSA_free(WOLFSSL_DSA*);
+
+WOLFSSL_API int wolfSSL_DSA_generate_key(WOLFSSL_DSA*);
+WOLFSSL_API int wolfSSL_DSA_generate_parameters_ex(WOLFSSL_DSA*, int bits,
+                   unsigned char* seed, int seedLen, int* counterRet,
+                   unsigned long* hRet, void* cb);
+
+WOLFSSL_API int wolfSSL_DSA_LoadDer(WOLFSSL_DSA*, const unsigned char*, int sz);
+WOLFSSL_API int wolfSSL_DSA_do_sign(const unsigned char* d, unsigned char* sigRet,
+                                  WOLFSSL_DSA* dsa);
+
+#define DSA_new wolfSSL_DSA_new
+#define DSA_free wolfSSL_DSA_free
+
+#define DSA_generate_key           wolfSSL_DSA_generate_key
+#define DSA_generate_parameters_ex wolfSSL_DSA_generate_parameters_ex
+
+
+#ifdef __cplusplus
+    }  /* extern "C" */ 
+#endif
+
+#endif /* header */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/ec.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/ec.h
new file mode 100644
index 0000000..5ffdaf6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/ec.h
@@ -0,0 +1,2 @@
+/* ec.h for openssl */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/ecdsa.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/ecdsa.h
new file mode 100644
index 0000000..f3cf0de
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/ecdsa.h
@@ -0,0 +1,2 @@
+/* ecdsa.h for openssl */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/engine.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/engine.h
new file mode 100644
index 0000000..39952fc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/engine.h
@@ -0,0 +1,5 @@
+/* engine.h for libcurl */
+
+#undef HAVE_OPENSSL_ENGINE_H
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/err.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/err.h
new file mode 100644
index 0000000..7e7f1eb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/err.h
@@ -0,0 +1,2 @@
+/* err.h for openssl */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/evp.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/evp.h
new file mode 100644
index 0000000..ded0b2f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/evp.h
@@ -0,0 +1,257 @@
+/* evp.h
+ *
+ * Copyright (C) 2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+/*  evp.h defines mini evp openssl compatibility layer 
+ *
+ */
+
+
+#ifndef WOLFSSL_EVP_H_
+#define WOLFSSL_EVP_H_
+
+#include 
+
+#ifdef WOLFSSL_PREFIX
+#include "prefix_evp.h"
+#endif
+
+#ifndef NO_MD5
+    #include 
+#endif
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+typedef char WOLFSSL_EVP_MD;
+typedef char WOLFSSL_EVP_CIPHER;
+
+#ifndef NO_MD5
+    WOLFSSL_API const WOLFSSL_EVP_MD* wolfSSL_EVP_md5(void);
+#endif
+WOLFSSL_API const WOLFSSL_EVP_MD* wolfSSL_EVP_sha1(void);
+WOLFSSL_API const WOLFSSL_EVP_MD* wolfSSL_EVP_sha256(void);
+WOLFSSL_API const WOLFSSL_EVP_MD* wolfSSL_EVP_sha384(void);
+WOLFSSL_API const WOLFSSL_EVP_MD* wolfSSL_EVP_sha512(void);
+WOLFSSL_API const WOLFSSL_EVP_MD* wolfSSL_EVP_ripemd160(void);
+
+WOLFSSL_API const WOLFSSL_EVP_CIPHER* wolfSSL_EVP_aes_128_cbc(void);
+WOLFSSL_API const WOLFSSL_EVP_CIPHER* wolfSSL_EVP_aes_192_cbc(void);
+WOLFSSL_API const WOLFSSL_EVP_CIPHER* wolfSSL_EVP_aes_256_cbc(void);
+WOLFSSL_API const WOLFSSL_EVP_CIPHER* wolfSSL_EVP_aes_128_ctr(void);
+WOLFSSL_API const WOLFSSL_EVP_CIPHER* wolfSSL_EVP_aes_192_ctr(void);
+WOLFSSL_API const WOLFSSL_EVP_CIPHER* wolfSSL_EVP_aes_256_ctr(void);
+WOLFSSL_API const WOLFSSL_EVP_CIPHER* wolfSSL_EVP_des_cbc(void);
+WOLFSSL_API const WOLFSSL_EVP_CIPHER* wolfSSL_EVP_des_ede3_cbc(void);
+WOLFSSL_API const WOLFSSL_EVP_CIPHER* wolfSSL_EVP_rc4(void);
+WOLFSSL_API const WOLFSSL_EVP_CIPHER* wolfSSL_EVP_enc_null(void);
+
+
+typedef union {
+    #ifndef NO_MD5
+        WOLFSSL_MD5_CTX    md5;
+    #endif
+    WOLFSSL_SHA_CTX    sha;
+    WOLFSSL_SHA256_CTX sha256;
+    #ifdef WOLFSSL_SHA384
+        WOLFSSL_SHA384_CTX sha384;
+    #endif
+    #ifdef WOLFSSL_SHA512
+        WOLFSSL_SHA512_CTX sha512;
+    #endif
+    #ifdef WOLFSSL_RIPEMD
+        WOLFSSL_RIPEMD_CTX ripemd;
+    #endif
+} WOLFSSL_Hasher;
+
+
+typedef struct WOLFSSL_EVP_MD_CTX {
+    unsigned char macType;
+    WOLFSSL_Hasher hash;
+} WOLFSSL_EVP_MD_CTX;
+
+
+typedef union {
+#ifndef NO_AES
+    Aes  aes;
+#endif
+#ifndef NO_DES3
+    Des  des;
+    Des3 des3;
+#endif
+    Arc4 arc4;
+} WOLFSSL_Cipher;
+
+
+enum {
+    AES_128_CBC_TYPE  = 1,
+    AES_192_CBC_TYPE  = 2,
+    AES_256_CBC_TYPE  = 3,
+    AES_128_CTR_TYPE  = 4,
+    AES_192_CTR_TYPE  = 5,
+    AES_256_CTR_TYPE  = 6,
+    DES_CBC_TYPE      = 7,
+    DES_EDE3_CBC_TYPE = 8,
+    ARC4_TYPE         = 9,
+    NULL_CIPHER_TYPE  = 10,
+    EVP_PKEY_RSA      = 11,
+    EVP_PKEY_DSA      = 12,
+    NID_sha1          = 64,
+    NID_md5           =  4
+};
+
+
+typedef struct WOLFSSL_EVP_CIPHER_CTX {
+    int            keyLen;         /* user may set for variable */
+    unsigned char  enc;            /* if encrypt side, then true */
+    unsigned char  cipherType;
+#ifndef NO_AES
+    unsigned char  iv[AES_BLOCK_SIZE];    /* working iv pointer into cipher */
+#elif !defined(NO_DES3)
+    unsigned char  iv[DES_BLOCK_SIZE];    /* working iv pointer into cipher */
+#endif
+    WOLFSSL_Cipher  cipher;
+} WOLFSSL_EVP_CIPHER_CTX;
+
+
+WOLFSSL_API int  wolfSSL_EVP_MD_size(const WOLFSSL_EVP_MD* md);
+WOLFSSL_API void wolfSSL_EVP_MD_CTX_init(WOLFSSL_EVP_MD_CTX* ctx);
+WOLFSSL_API int  wolfSSL_EVP_MD_CTX_cleanup(WOLFSSL_EVP_MD_CTX* ctx);
+
+WOLFSSL_API int wolfSSL_EVP_DigestInit(WOLFSSL_EVP_MD_CTX* ctx,
+                                     const WOLFSSL_EVP_MD* type);
+WOLFSSL_API int wolfSSL_EVP_DigestUpdate(WOLFSSL_EVP_MD_CTX* ctx, const void* data,
+                                       unsigned long sz);
+WOLFSSL_API int wolfSSL_EVP_DigestFinal(WOLFSSL_EVP_MD_CTX* ctx, unsigned char* md,
+                                      unsigned int* s);
+WOLFSSL_API int wolfSSL_EVP_DigestFinal_ex(WOLFSSL_EVP_MD_CTX* ctx,
+                                            unsigned char* md, unsigned int* s);
+#ifndef NO_MD5
+WOLFSSL_API int wolfSSL_EVP_BytesToKey(const WOLFSSL_EVP_CIPHER*,
+                              const WOLFSSL_EVP_MD*, const unsigned char*,
+                              const unsigned char*, int, int, unsigned char*,
+                              unsigned char*);
+#endif
+
+WOLFSSL_API void wolfSSL_EVP_CIPHER_CTX_init(WOLFSSL_EVP_CIPHER_CTX* ctx);
+WOLFSSL_API int  wolfSSL_EVP_CIPHER_CTX_cleanup(WOLFSSL_EVP_CIPHER_CTX* ctx);
+
+WOLFSSL_API int  wolfSSL_EVP_CIPHER_CTX_iv_length(const WOLFSSL_EVP_CIPHER_CTX*);
+
+
+WOLFSSL_API int  wolfSSL_EVP_CipherInit(WOLFSSL_EVP_CIPHER_CTX* ctx,
+                                    const WOLFSSL_EVP_CIPHER* type,
+                                    unsigned char* key, unsigned char* iv,
+                                    int enc);
+WOLFSSL_API int  wolfSSL_EVP_CIPHER_CTX_key_length(WOLFSSL_EVP_CIPHER_CTX* ctx);
+WOLFSSL_API int  wolfSSL_EVP_CIPHER_CTX_set_key_length(WOLFSSL_EVP_CIPHER_CTX* ctx,
+                                                     int keylen);
+WOLFSSL_API int  wolfSSL_EVP_Cipher(WOLFSSL_EVP_CIPHER_CTX* ctx,
+                          unsigned char* dst, unsigned char* src,
+                          unsigned int len);
+
+WOLFSSL_API const WOLFSSL_EVP_MD* wolfSSL_EVP_get_digestbynid(int);
+
+WOLFSSL_API WOLFSSL_RSA* wolfSSL_EVP_PKEY_get1_RSA(WOLFSSL_EVP_PKEY*);
+WOLFSSL_API WOLFSSL_DSA* wolfSSL_EVP_PKEY_get1_DSA(WOLFSSL_EVP_PKEY*);
+
+/* these next ones don't need real OpenSSL type, for OpenSSH compat only */
+WOLFSSL_API void* wolfSSL_EVP_X_STATE(const WOLFSSL_EVP_CIPHER_CTX* ctx);
+WOLFSSL_API int   wolfSSL_EVP_X_STATE_LEN(const WOLFSSL_EVP_CIPHER_CTX* ctx);
+
+WOLFSSL_API void  wolfSSL_3des_iv(WOLFSSL_EVP_CIPHER_CTX* ctx, int doset,
+                                unsigned char* iv, int len);
+WOLFSSL_API void  wolfSSL_aes_ctr_iv(WOLFSSL_EVP_CIPHER_CTX* ctx, int doset,
+                                unsigned char* iv, int len);
+
+WOLFSSL_API int  wolfSSL_StoreExternalIV(WOLFSSL_EVP_CIPHER_CTX* ctx);
+WOLFSSL_API int  wolfSSL_SetInternalIV(WOLFSSL_EVP_CIPHER_CTX* ctx);
+
+
+/* end OpenSSH compat */
+
+typedef WOLFSSL_EVP_MD         EVP_MD;
+typedef WOLFSSL_EVP_CIPHER     EVP_CIPHER;
+typedef WOLFSSL_EVP_MD_CTX     EVP_MD_CTX;
+typedef WOLFSSL_EVP_CIPHER_CTX EVP_CIPHER_CTX;
+
+#ifndef NO_MD5
+    #define EVP_md5       wolfSSL_EVP_md5
+#endif
+#define EVP_sha1      wolfSSL_EVP_sha1
+#define EVP_sha256    wolfSSL_EVP_sha256
+#define EVP_sha384    wolfSSL_EVP_sha384
+#define EVP_sha512    wolfSSL_EVP_sha512
+#define EVP_ripemd160 wolfSSL_EVP_ripemd160
+
+#define EVP_aes_128_cbc  wolfSSL_EVP_aes_128_cbc
+#define EVP_aes_192_cbc  wolfSSL_EVP_aes_192_cbc
+#define EVP_aes_256_cbc  wolfSSL_EVP_aes_256_cbc
+#define EVP_aes_128_ctr  wolfSSL_EVP_aes_128_ctr
+#define EVP_aes_192_ctr  wolfSSL_EVP_aes_192_ctr
+#define EVP_aes_256_ctr  wolfSSL_EVP_aes_256_ctr
+#define EVP_des_cbc      wolfSSL_EVP_des_cbc
+#define EVP_des_ede3_cbc wolfSSL_EVP_des_ede3_cbc
+#define EVP_rc4          wolfSSL_EVP_rc4
+#define EVP_enc_null     wolfSSL_EVP_enc_null
+
+#define EVP_MD_size        wolfSSL_EVP_MD_size
+#define EVP_MD_CTX_init    wolfSSL_EVP_MD_CTX_init
+#define EVP_MD_CTX_cleanup wolfSSL_EVP_MD_CTX_cleanup
+#define EVP_DigestInit     wolfSSL_EVP_DigestInit
+#define EVP_DigestUpdate   wolfSSL_EVP_DigestUpdate
+#define EVP_DigestFinal    wolfSSL_EVP_DigestFinal
+#define EVP_DigestFinal_ex wolfSSL_EVP_DigestFinal_ex
+#define EVP_BytesToKey     wolfSSL_EVP_BytesToKey
+
+#define EVP_CIPHER_CTX_init           wolfSSL_EVP_CIPHER_CTX_init
+#define EVP_CIPHER_CTX_cleanup        wolfSSL_EVP_CIPHER_CTX_cleanup
+#define EVP_CIPHER_CTX_iv_length      wolfSSL_EVP_CIPHER_CTX_iv_length
+#define EVP_CIPHER_CTX_key_length     wolfSSL_EVP_CIPHER_CTX_key_length
+#define EVP_CIPHER_CTX_set_key_length wolfSSL_EVP_CIPHER_CTX_set_key_length
+#define EVP_CipherInit                wolfSSL_EVP_CipherInit
+#define EVP_Cipher                    wolfSSL_EVP_Cipher
+
+#define EVP_get_digestbynid           wolfSSL_EVP_get_digestbynid
+
+#define EVP_PKEY_get1_RSA   wolfSSL_EVP_PKEY_get1_RSA
+#define EVP_PKEY_get1_DSA   wolfSSL_EVP_PKEY_get1_DSA
+
+#ifndef EVP_MAX_MD_SIZE
+    #define EVP_MAX_MD_SIZE   64     /* sha512 */
+#endif
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+
+#endif /* WOLFSSL_EVP_H_ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/hmac.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/hmac.h
new file mode 100644
index 0000000..0dca8cb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/hmac.h
@@ -0,0 +1,81 @@
+/* hmac.h
+ *
+ * Copyright (C) 2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+/*  hmac.h defines mini hamc openssl compatibility layer 
+ *
+ */
+
+
+#ifndef WOLFSSL_HMAC_H_
+#define WOLFSSL_HMAC_H_
+
+#include 
+
+#ifdef WOLFSSL_PREFIX
+#include "prefix_hmac.h"
+#endif
+
+#include 
+#include 
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+
+WOLFSSL_API unsigned char* wolfSSL_HMAC(const WOLFSSL_EVP_MD* evp_md,
+                               const void* key, int key_len,
+                               const unsigned char* d, int n, unsigned char* md,
+                               unsigned int* md_len);
+
+
+typedef struct WOLFSSL_HMAC_CTX {
+    Hmac hmac;
+    int  type;
+} WOLFSSL_HMAC_CTX;
+
+
+WOLFSSL_API void wolfSSL_HMAC_Init(WOLFSSL_HMAC_CTX* ctx, const void* key,
+                                 int keylen, const EVP_MD* type);
+WOLFSSL_API void wolfSSL_HMAC_Update(WOLFSSL_HMAC_CTX* ctx,
+                                   const unsigned char* data, int len);
+WOLFSSL_API void wolfSSL_HMAC_Final(WOLFSSL_HMAC_CTX* ctx, unsigned char* hash,
+                                  unsigned int* len);
+WOLFSSL_API void wolfSSL_HMAC_cleanup(WOLFSSL_HMAC_CTX* ctx);
+
+
+typedef struct WOLFSSL_HMAC_CTX HMAC_CTX;
+
+#define HMAC(a,b,c,d,e,f,g) wolfSSL_HMAC((a),(b),(c),(d),(e),(f),(g))
+
+#define HMAC_Init    wolfSSL_HMAC_Init
+#define HMAC_Update  wolfSSL_HMAC_Update
+#define HMAC_Final   wolfSSL_HMAC_Final
+#define HMAC_cleanup wolfSSL_HMAC_cleanup
+
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+
+#endif /* WOLFSSL_HMAC_H_ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/include.am
new file mode 100644
index 0000000..05b509b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/include.am
@@ -0,0 +1,36 @@
+# vim:ft=automake
+# All paths should be given relative to the root
+
+nobase_include_HEADERS+= \
+                         wolfssl/openssl/asn1.h \
+                         wolfssl/openssl/bio.h \
+                         wolfssl/openssl/bn.h \
+                         wolfssl/openssl/conf.h \
+                         wolfssl/openssl/crypto.h \
+                         wolfssl/openssl/des.h \
+                         wolfssl/openssl/dh.h \
+                         wolfssl/openssl/dsa.h \
+                         wolfssl/openssl/ecdsa.h \
+                         wolfssl/openssl/ec.h \
+                         wolfssl/openssl/engine.h \
+                         wolfssl/openssl/err.h \
+                         wolfssl/openssl/evp.h \
+                         wolfssl/openssl/hmac.h \
+                         wolfssl/openssl/lhash.h \
+                         wolfssl/openssl/md4.h \
+                         wolfssl/openssl/md5.h \
+                         wolfssl/openssl/ripemd.h \
+                         wolfssl/openssl/ocsp.h \
+                         wolfssl/openssl/opensslconf.h \
+                         wolfssl/openssl/opensslv.h \
+                         wolfssl/openssl/ossl_typ.h \
+                         wolfssl/openssl/pem.h \
+                         wolfssl/openssl/pkcs12.h \
+                         wolfssl/openssl/rand.h \
+                         wolfssl/openssl/rsa.h \
+                         wolfssl/openssl/sha.h \
+                         wolfssl/openssl/ssl.h \
+                         wolfssl/openssl/stack.h \
+                         wolfssl/openssl/ui.h \
+                         wolfssl/openssl/x509.h \
+                         wolfssl/openssl/x509v3.h
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/lhash.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/lhash.h
new file mode 100644
index 0000000..01f8535
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/lhash.h
@@ -0,0 +1,2 @@
+/* lhash.h for openSSL */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/md4.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/md4.h
new file mode 100644
index 0000000..2e99f97
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/md4.h
@@ -0,0 +1 @@
+/* md4.h for libcurl */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/md5.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/md5.h
new file mode 100644
index 0000000..bdcda5b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/md5.h
@@ -0,0 +1,42 @@
+/* md5.h for openssl */
+
+
+#ifndef WOLFSSL_MD5_H_
+#define WOLFSSL_MD5_H_
+
+#include 
+
+#ifndef NO_MD5
+
+#ifdef WOLFSSL_PREFIX
+#include "prefix_md5.h"
+#endif
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+
+typedef struct WOLFSSL_MD5_CTX {
+    int holder[24];   /* big enough to hold wolfcrypt md5, but check on init */
+} WOLFSSL_MD5_CTX;
+
+WOLFSSL_API void wolfSSL_MD5_Init(WOLFSSL_MD5_CTX*);
+WOLFSSL_API void wolfSSL_MD5_Update(WOLFSSL_MD5_CTX*, const void*, unsigned long);
+WOLFSSL_API void wolfSSL_MD5_Final(unsigned char*, WOLFSSL_MD5_CTX*);
+
+
+typedef WOLFSSL_MD5_CTX MD5_CTX;
+
+#define MD5_Init wolfSSL_MD5_Init
+#define MD5_Update wolfSSL_MD5_Update
+#define MD5_Final wolfSSL_MD5_Final
+
+#ifdef __cplusplus
+    }  /* extern "C" */ 
+#endif
+
+#endif /* NO_MD5 */
+
+#endif /* WOLFSSL_MD5_H_ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/ocsp.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/ocsp.h
new file mode 100644
index 0000000..7463eec
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/ocsp.h
@@ -0,0 +1 @@
+/* ocsp.h for libcurl */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/opensslconf.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/opensslconf.h
new file mode 100644
index 0000000..ac6b55b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/opensslconf.h
@@ -0,0 +1,8 @@
+/* opensslconf.h for openSSL */
+
+
+#ifndef OPENSSL_THREADS
+    #define OPENSSL_THREADS
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/opensslv.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/opensslv.h
new file mode 100644
index 0000000..e13e992
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/opensslv.h
@@ -0,0 +1,12 @@
+/* opensslv.h compatibility */
+
+#ifndef WOLFSSL_OPENSSLV_H_
+#define WOLFSSL_OPENSSLV_H_
+
+
+/* api version compatibility */
+#define OPENSSL_VERSION_NUMBER 0x0090410fL
+
+
+#endif /* header */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/ossl_typ.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/ossl_typ.h
new file mode 100644
index 0000000..65b00c7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/ossl_typ.h
@@ -0,0 +1,2 @@
+/* ossl_typ.h for openssl */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/pem.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/pem.h
new file mode 100644
index 0000000..926e43f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/pem.h
@@ -0,0 +1,41 @@
+/* pem.h for openssl */
+
+
+#ifndef WOLFSSL_PEM_H_
+#define WOLFSSL_PEM_H_
+
+#include 
+#include 
+#include 
+#include 
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+
+WOLFSSL_API int wolfSSL_PEM_write_bio_RSAPrivateKey(WOLFSSL_BIO* bio, RSA* rsa,
+	                                  const EVP_CIPHER* cipher,
+	                                  unsigned char* passwd, int len,
+	                                  pem_password_cb cb, void* arg);
+
+WOLFSSL_API int wolfSSL_PEM_write_bio_DSAPrivateKey(WOLFSSL_BIO* bio, DSA* rsa,
+	                                  const EVP_CIPHER* cipher,
+	                                  unsigned char* passwd, int len,
+	                                  pem_password_cb cb, void* arg);
+
+WOLFSSL_API WOLFSSL_EVP_PKEY* wolfSSL_PEM_read_bio_PrivateKey(WOLFSSL_BIO* bio,
+                        WOLFSSL_EVP_PKEY**, pem_password_cb cb, void* arg); 
+
+#define PEM_write_bio_RSAPrivateKey wolfSSL_PEM_write_bio_RSAPrivateKey
+#define PEM_write_bio_DSAPrivateKey wolfSSL_PEM_write_bio_DSAPrivateKey
+#define PEM_read_bio_PrivateKey     wolfSSL_PEM_read_bio_PrivateKey
+
+
+#ifdef __cplusplus
+    }  /* extern "C" */ 
+#endif
+
+
+#endif /* WOLFSSL_PEM_H_ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/pkcs12.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/pkcs12.h
new file mode 100644
index 0000000..544b6f0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/pkcs12.h
@@ -0,0 +1,2 @@
+/* pkcs12.h for openssl */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/rand.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/rand.h
new file mode 100644
index 0000000..c1fa62e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/rand.h
@@ -0,0 +1,4 @@
+/* rand.h for openSSL */
+
+#include 
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/ripemd.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/ripemd.h
new file mode 100644
index 0000000..ef1578e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/ripemd.h
@@ -0,0 +1,37 @@
+/* ripemd.h for openssl */
+
+
+#ifndef WOLFSSL_RIPEMD_H_
+#define WOLFSSL_RIPEMD_H_
+
+#include 
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+
+typedef struct WOLFSSL_RIPEMD_CTX {
+    int holder[32];   /* big enough to hold wolfcrypt, but check on init */
+} WOLFSSL_RIPEMD_CTX;
+
+WOLFSSL_API void wolfSSL_RIPEMD_Init(WOLFSSL_RIPEMD_CTX*);
+WOLFSSL_API void wolfSSL_RIPEMD_Update(WOLFSSL_RIPEMD_CTX*, const void*,
+                                     unsigned long);
+WOLFSSL_API void wolfSSL_RIPEMD_Final(unsigned char*, WOLFSSL_RIPEMD_CTX*);
+
+
+typedef WOLFSSL_RIPEMD_CTX RIPEMD_CTX;
+
+#define RIPEMD_Init   wolfSSL_RIPEMD_Init
+#define RIPEMD_Update wolfSSL_RIPEMD_Update
+#define RIPEMD_Final  wolfSSL_RIPEMD_Final
+
+
+#ifdef __cplusplus
+    }  /* extern "C" */ 
+#endif
+
+
+#endif /* WOLFSSL_MD5_H_ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/rsa.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/rsa.h
new file mode 100644
index 0000000..2db993b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/rsa.h
@@ -0,0 +1,75 @@
+/* rsa.h for openSSL */
+
+
+#ifndef WOLFSSL_RSA_H_
+#define WOLFSSL_RSA_H_
+
+#include 
+#include 
+
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+
+enum  { 
+	RSA_PKCS1_PADDING = 1
+ };
+
+struct WOLFSSL_RSA {
+	WOLFSSL_BIGNUM* n;
+	WOLFSSL_BIGNUM* e;
+	WOLFSSL_BIGNUM* d;
+	WOLFSSL_BIGNUM* p;
+	WOLFSSL_BIGNUM* q;
+	WOLFSSL_BIGNUM* dmp1;      /* dP */
+	WOLFSSL_BIGNUM* dmq1;      /* dQ */
+	WOLFSSL_BIGNUM* iqmp;      /* u */
+    void*          internal;  /* our RSA */
+    char           inSet;     /* internal set from external ? */
+    char           exSet;     /* external set from internal ? */
+};
+
+
+WOLFSSL_API WOLFSSL_RSA* wolfSSL_RSA_new(void);
+WOLFSSL_API void        wolfSSL_RSA_free(WOLFSSL_RSA*);
+
+WOLFSSL_API int wolfSSL_RSA_generate_key_ex(WOLFSSL_RSA*, int bits, WOLFSSL_BIGNUM*,
+                                          void* cb);
+
+WOLFSSL_API int wolfSSL_RSA_blinding_on(WOLFSSL_RSA*, WOLFSSL_BN_CTX*);
+WOLFSSL_API int wolfSSL_RSA_public_encrypt(int len, unsigned char* fr,
+	                               unsigned char* to, WOLFSSL_RSA*, int padding);
+WOLFSSL_API int wolfSSL_RSA_private_decrypt(int len, unsigned char* fr,
+	                               unsigned char* to, WOLFSSL_RSA*, int padding);
+
+WOLFSSL_API int wolfSSL_RSA_size(const WOLFSSL_RSA*);
+WOLFSSL_API int wolfSSL_RSA_sign(int type, const unsigned char* m,
+                               unsigned int mLen, unsigned char* sigRet,
+                               unsigned int* sigLen, WOLFSSL_RSA*);
+WOLFSSL_API int wolfSSL_RSA_public_decrypt(int flen, unsigned char* from,
+                                  unsigned char* to, WOLFSSL_RSA*, int padding);
+WOLFSSL_API int wolfSSL_RSA_GenAdd(WOLFSSL_RSA*);
+WOLFSSL_API int wolfSSL_RSA_LoadDer(WOLFSSL_RSA*, const unsigned char*, int sz);
+
+
+#define RSA_new  wolfSSL_RSA_new
+#define RSA_free wolfSSL_RSA_free
+
+#define RSA_generate_key_ex wolfSSL_RSA_generate_key_ex
+
+#define RSA_blinding_on     wolfSSL_RSA_blinding_on
+#define RSA_public_encrypt  wolfSSL_RSA_public_encrypt
+#define RSA_private_decrypt wolfSSL_RSA_private_decrypt
+
+#define RSA_size           wolfSSL_RSA_size
+#define RSA_sign           wolfSSL_RSA_sign
+#define RSA_public_decrypt wolfSSL_RSA_public_decrypt
+
+
+#ifdef __cplusplus
+    }  /* extern "C" */ 
+#endif
+
+#endif /* header */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/sha.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/sha.h
new file mode 100644
index 0000000..7f8b0eb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/sha.h
@@ -0,0 +1,125 @@
+/* sha.h for openssl */
+
+
+#ifndef WOLFSSL_SHA_H_
+#define WOLFSSL_SHA_H_
+
+#include 
+
+#ifdef WOLFSSL_PREFIX
+#include "prefix_sha.h"
+#endif
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+
+typedef struct WOLFSSL_SHA_CTX {
+    int holder[24];   /* big enough to hold wolfcrypt sha, but check on init */
+} WOLFSSL_SHA_CTX;
+
+WOLFSSL_API void wolfSSL_SHA_Init(WOLFSSL_SHA_CTX*);
+WOLFSSL_API void wolfSSL_SHA_Update(WOLFSSL_SHA_CTX*, const void*, unsigned long);
+WOLFSSL_API void wolfSSL_SHA_Final(unsigned char*, WOLFSSL_SHA_CTX*);
+
+/* SHA1 points to above, shouldn't use SHA0 ever */
+WOLFSSL_API void wolfSSL_SHA1_Init(WOLFSSL_SHA_CTX*);
+WOLFSSL_API void wolfSSL_SHA1_Update(WOLFSSL_SHA_CTX*, const void*, unsigned long);
+WOLFSSL_API void wolfSSL_SHA1_Final(unsigned char*, WOLFSSL_SHA_CTX*);
+
+enum {
+    SHA_DIGEST_LENGTH = 20
+};
+
+
+typedef WOLFSSL_SHA_CTX SHA_CTX;
+
+#define SHA_Init wolfSSL_SHA_Init
+#define SHA_Update wolfSSL_SHA_Update
+#define SHA_Final wolfSSL_SHA_Final
+
+#define SHA1_Init wolfSSL_SHA1_Init
+#define SHA1_Update wolfSSL_SHA1_Update
+#define SHA1_Final wolfSSL_SHA1_Final
+
+
+typedef struct WOLFSSL_SHA256_CTX {
+    int holder[28];   /* big enough to hold wolfcrypt sha, but check on init */
+} WOLFSSL_SHA256_CTX;
+
+WOLFSSL_API void wolfSSL_SHA256_Init(WOLFSSL_SHA256_CTX*);
+WOLFSSL_API void wolfSSL_SHA256_Update(WOLFSSL_SHA256_CTX*, const void*,
+	                                 unsigned long);
+WOLFSSL_API void wolfSSL_SHA256_Final(unsigned char*, WOLFSSL_SHA256_CTX*);
+
+enum {
+    SHA256_DIGEST_LENGTH = 32 
+};
+
+
+typedef WOLFSSL_SHA256_CTX SHA256_CTX;
+
+#define SHA256_Init   wolfSSL_SHA256_Init
+#define SHA256_Update wolfSSL_SHA256_Update
+#define SHA256_Final  wolfSSL_SHA256_Final
+
+
+#ifdef WOLFSSL_SHA384
+
+typedef struct WOLFSSL_SHA384_CTX {
+    long long holder[32];   /* big enough, but check on init */
+} WOLFSSL_SHA384_CTX;
+
+WOLFSSL_API void wolfSSL_SHA384_Init(WOLFSSL_SHA384_CTX*);
+WOLFSSL_API void wolfSSL_SHA384_Update(WOLFSSL_SHA384_CTX*, const void*,
+	                                 unsigned long);
+WOLFSSL_API void wolfSSL_SHA384_Final(unsigned char*, WOLFSSL_SHA384_CTX*);
+
+enum {
+    SHA384_DIGEST_LENGTH = 48 
+};
+
+
+typedef WOLFSSL_SHA384_CTX SHA384_CTX;
+
+#define SHA384_Init   wolfSSL_SHA384_Init
+#define SHA384_Update wolfSSL_SHA384_Update
+#define SHA384_Final  wolfSSL_SHA384_Final
+
+#endif /* WOLFSSL_SHA384 */
+
+#ifdef WOLFSSL_SHA512
+
+typedef struct WOLFSSL_SHA512_CTX {
+    long long holder[36];   /* big enough, but check on init */
+} WOLFSSL_SHA512_CTX;
+
+WOLFSSL_API void wolfSSL_SHA512_Init(WOLFSSL_SHA512_CTX*);
+WOLFSSL_API void wolfSSL_SHA512_Update(WOLFSSL_SHA512_CTX*, const void*,
+	                                 unsigned long);
+WOLFSSL_API void wolfSSL_SHA512_Final(unsigned char*, WOLFSSL_SHA512_CTX*);
+
+enum {
+    SHA512_DIGEST_LENGTH = 64 
+};
+
+
+typedef WOLFSSL_SHA512_CTX SHA512_CTX;
+
+#define SHA512_Init   wolfSSL_SHA512_Init
+#define SHA512_Update wolfSSL_SHA512_Update
+#define SHA512_Final  wolfSSL_SHA512_Final
+
+#endif /* WOLFSSL_SHA512 */
+
+
+
+
+#ifdef __cplusplus
+    }  /* extern "C" */ 
+#endif
+
+
+#endif /* WOLFSSL_SHA_H_ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/ssl.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/ssl.h
new file mode 100644
index 0000000..34d7948
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/ssl.h
@@ -0,0 +1,406 @@
+/* ssl.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * a with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+/*  ssl.h defines wolfssl_openssl compatibility layer 
+ *
+ */
+
+
+#ifndef WOLFSSL_OPENSSL_H_
+#define WOLFSSL_OPENSSL_H_
+
+/* wolfssl_openssl compatibility layer */
+#include 
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#ifdef _WIN32
+    /* wincrypt.h clashes */
+    #undef X509_NAME
+#endif
+
+
+typedef WOLFSSL          SSL;
+typedef WOLFSSL_SESSION  SSL_SESSION;
+typedef WOLFSSL_METHOD   SSL_METHOD;
+typedef WOLFSSL_CTX      SSL_CTX;
+
+typedef WOLFSSL_X509       X509;
+typedef WOLFSSL_X509_NAME  X509_NAME;
+typedef WOLFSSL_X509_CHAIN X509_CHAIN;
+
+
+/* redeclare guard */
+#define WOLFSSL_TYPES_DEFINED
+
+
+typedef WOLFSSL_EVP_PKEY       EVP_PKEY;
+typedef WOLFSSL_RSA            RSA;
+typedef WOLFSSL_DSA            DSA;
+typedef WOLFSSL_BIO            BIO;
+typedef WOLFSSL_BIO_METHOD     BIO_METHOD;
+typedef WOLFSSL_CIPHER         SSL_CIPHER;
+typedef WOLFSSL_X509_LOOKUP    X509_LOOKUP;
+typedef WOLFSSL_X509_LOOKUP_METHOD X509_LOOKUP_METHOD;
+typedef WOLFSSL_X509_CRL       X509_CRL;
+typedef WOLFSSL_X509_EXTENSION X509_EXTENSION;
+typedef WOLFSSL_ASN1_TIME      ASN1_TIME;
+typedef WOLFSSL_ASN1_INTEGER   ASN1_INTEGER;
+typedef WOLFSSL_ASN1_OBJECT    ASN1_OBJECT;
+typedef WOLFSSL_ASN1_STRING    ASN1_STRING;
+typedef WOLFSSL_dynlock_value  CRYPTO_dynlock_value;
+
+#define ASN1_UTCTIME WOLFSSL_ASN1_TIME
+
+typedef WOLFSSL_MD4_CTX        MD4_CTX;
+typedef WOLFSSL_COMP_METHOD    COMP_METHOD;
+typedef WOLFSSL_X509_STORE     X509_STORE;
+typedef WOLFSSL_X509_REVOKED   X509_REVOKED;
+typedef WOLFSSL_X509_OBJECT    X509_OBJECT;
+typedef WOLFSSL_X509_STORE_CTX X509_STORE_CTX;
+
+#define SSL_get_cipher_list(ctx,i)          wolfSSL_get_cipher_list((i))
+#define SSL_get_cipher_name(ctx)            wolfSSL_get_cipher((ctx))
+#define SSL_get_shared_ciphers(ctx,buf,len) \
+                                strncpy(buf, "Not Implemented, SSLv2 only", len)
+
+/* @TODO */
+#define ERR_print_errors_fp(file)
+
+/* at the moment only returns ok */
+#define SSL_get_verify_result(ctx)    X509_V_OK
+#define SSL_get_verify_mode           wolfSSL_SSL_get_mode
+#define SSL_get_verify_depth          wolfSSL_get_verify_depth
+#define SSL_CTX_get_verify_mode       wolfSSL_CTX_get_mode
+#define SSL_CTX_get_verify_depth      wolfSSL_CTX_get_verify_depth
+#define SSL_get_certificate(ctx)      0 /* used to pass to get_privatekey */
+
+#define SSLv3_server_method wolfSSLv3_server_method
+#define SSLv3_client_method wolfSSLv3_client_method
+#define TLSv1_server_method wolfTLSv1_server_method
+#define TLSv1_client_method wolfTLSv1_client_method
+#define TLSv1_1_server_method wolfTLSv1_1_server_method
+#define TLSv1_1_client_method wolfTLSv1_1_client_method
+#define TLSv1_2_server_method wolfTLSv1_2_server_method
+#define TLSv1_2_client_method wolfTLSv1_2_client_method
+
+#ifdef WOLFSSL_DTLS
+    #define DTLSv1_client_method wolfDTLSv1_client_method
+    #define DTLSv1_server_method wolfDTLSv1_server_method
+    #define DTLSv1_2_client_method wolfDTLSv1_2_client_method
+    #define DTLSv1_2_server_method wolfDTLSv1_2_server_method
+#endif
+
+
+#ifndef NO_FILESYSTEM
+    #define SSL_CTX_use_certificate_file wolfSSL_CTX_use_certificate_file
+    #define SSL_CTX_use_PrivateKey_file wolfSSL_CTX_use_PrivateKey_file
+    #define SSL_CTX_load_verify_locations wolfSSL_CTX_load_verify_locations
+    #define SSL_CTX_use_certificate_chain_file wolfSSL_CTX_use_certificate_chain_file
+    #define SSL_CTX_use_RSAPrivateKey_file wolfSSL_CTX_use_RSAPrivateKey_file
+    
+    #define SSL_use_certificate_file wolfSSL_use_certificate_file
+    #define SSL_use_PrivateKey_file wolfSSL_use_PrivateKey_file
+    #define SSL_use_certificate_chain_file wolfSSL_use_certificate_chain_file
+    #define SSL_use_RSAPrivateKey_file wolfSSL_use_RSAPrivateKey_file
+#endif
+
+#define SSL_CTX_new wolfSSL_CTX_new
+#define SSL_new     wolfSSL_new
+#define SSL_set_fd  wolfSSL_set_fd
+#define SSL_get_fd  wolfSSL_get_fd
+#define SSL_connect wolfSSL_connect
+#define SSL_clear   wolfSSL_clear
+
+#define SSL_write    wolfSSL_write
+#define SSL_read     wolfSSL_read
+#define SSL_peek     wolfSSL_peek
+#define SSL_accept   wolfSSL_accept
+#define SSL_CTX_free wolfSSL_CTX_free
+#define SSL_free     wolfSSL_free
+#define SSL_shutdown wolfSSL_shutdown
+
+#define SSL_CTX_set_quiet_shutdown wolfSSL_CTX_set_quiet_shutdown
+#define SSL_set_quiet_shutdown wolfSSL_set_quiet_shutdown
+#define SSL_get_error wolfSSL_get_error
+#define SSL_set_session wolfSSL_set_session
+#define SSL_get_session wolfSSL_get_session
+#define SSL_flush_sessions wolfSSL_flush_sessions
+/* assume unlimited temporarly */
+#define SSL_CTX_get_session_cache_mode(ctx) 0
+
+#define SSL_CTX_set_verify wolfSSL_CTX_set_verify
+#define SSL_set_verify wolfSSL_set_verify
+#define SSL_pending wolfSSL_pending
+#define SSL_load_error_strings wolfSSL_load_error_strings
+#define SSL_library_init wolfSSL_library_init
+#define SSL_CTX_set_session_cache_mode wolfSSL_CTX_set_session_cache_mode
+#define SSL_CTX_set_cipher_list wolfSSL_CTX_set_cipher_list
+#define SSL_set_cipher_list     wolfSSL_set_cipher_list
+
+#define ERR_error_string wolfSSL_ERR_error_string
+#define ERR_error_string_n wolfSSL_ERR_error_string_n
+#define ERR_reason_error_string wolfSSL_ERR_reason_error_string
+
+#define SSL_set_ex_data wolfSSL_set_ex_data
+#define SSL_get_shutdown wolfSSL_get_shutdown
+#define SSL_set_rfd wolfSSL_set_rfd
+#define SSL_set_wfd wolfSSL_set_wfd
+#define SSL_set_shutdown wolfSSL_set_shutdown
+#define SSL_set_session_id_context wolfSSL_set_session_id_context
+#define SSL_set_connect_state wolfSSL_set_connect_state
+#define SSL_set_accept_state wolfSSL_set_accept_state
+#define SSL_session_reused wolfSSL_session_reused
+#define SSL_SESSION_free wolfSSL_SESSION_free
+#define SSL_is_init_finished wolfSSL_is_init_finished
+
+#define SSL_get_version wolfSSL_get_version
+#define SSL_get_current_cipher wolfSSL_get_current_cipher
+#define SSL_get_cipher wolfSSL_get_cipher
+#define SSL_CIPHER_description wolfSSL_CIPHER_description
+#define SSL_CIPHER_get_name wolfSSL_CIPHER_get_name
+#define SSL_get1_session wolfSSL_get1_session
+
+#define SSL_get_keyblock_size wolfSSL_get_keyblock_size
+#define SSL_get_keys          wolfSSL_get_keys
+
+#define X509_free wolfSSL_X509_free
+#define OPENSSL_free wolfSSL_OPENSSL_free
+
+#define OCSP_parse_url wolfSSL_OCSP_parse_url
+#define SSLv23_client_method wolfSSLv23_client_method
+#define SSLv2_client_method wolfSSLv2_client_method
+#define SSLv2_server_method wolfSSLv2_server_method
+
+#define MD4_Init wolfSSL_MD4_Init
+#define MD4_Update  wolfSSL_MD4_Update
+#define MD4_Final wolfSSL_MD4_Final
+
+#define BIO_new      wolfSSL_BIO_new
+#define BIO_free     wolfSSL_BIO_free
+#define BIO_free_all wolfSSL_BIO_free_all
+#define BIO_read     wolfSSL_BIO_read
+#define BIO_write    wolfSSL_BIO_write
+#define BIO_push     wolfSSL_BIO_push
+#define BIO_pop      wolfSSL_BIO_pop
+#define BIO_flush    wolfSSL_BIO_flush
+#define BIO_pending  wolfSSL_BIO_pending
+
+#define BIO_get_mem_data wolfSSL_BIO_get_mem_data
+#define BIO_new_mem_buf  wolfSSL_BIO_new_mem_buf
+
+#define BIO_f_buffer              wolfSSL_BIO_f_buffer
+#define BIO_set_write_buffer_size wolfSSL_BIO_set_write_buffer_size
+#define BIO_f_ssl                 wolfSSL_BIO_f_ssl
+#define BIO_new_socket            wolfSSL_BIO_new_socket
+#define SSL_set_bio               wolfSSL_set_bio
+#define BIO_eof                   wolfSSL_BIO_eof
+#define BIO_set_ss                wolfSSL_BIO_set_ss
+
+#define BIO_s_mem     wolfSSL_BIO_s_mem
+#define BIO_f_base64  wolfSSL_BIO_f_base64
+#define BIO_set_flags wolfSSL_BIO_set_flags
+
+#define OpenSSL_add_all_algorithms wolfSSL_add_all_algorithms
+#define SSLeay_add_ssl_algorithms  wolfSSL_add_all_algorithms
+#define SSLeay_add_all_algorithms wolfSSL_add_all_algorithms
+
+#define RAND_screen     wolfSSL_RAND_screen
+#define RAND_file_name  wolfSSL_RAND_file_name
+#define RAND_write_file wolfSSL_RAND_write_file
+#define RAND_load_file  wolfSSL_RAND_load_file
+#define RAND_egd        wolfSSL_RAND_egd
+#define RAND_seed       wolfSSL_RAND_seed
+#define RAND_add        wolfSSL_RAND_add
+
+#define COMP_zlib                       wolfSSL_COMP_zlib
+#define COMP_rle                        wolfSSL_COMP_rle
+#define SSL_COMP_add_compression_method wolfSSL_COMP_add_compression_method
+
+#define SSL_get_ex_new_index wolfSSL_get_ex_new_index
+
+#define CRYPTO_set_id_callback wolfSSL_set_id_callback
+#define CRYPTO_set_locking_callback wolfSSL_set_locking_callback
+#define CRYPTO_set_dynlock_create_callback wolfSSL_set_dynlock_create_callback
+#define CRYPTO_set_dynlock_lock_callback wolfSSL_set_dynlock_lock_callback
+#define CRYPTO_set_dynlock_destroy_callback wolfSSL_set_dynlock_destroy_callback
+#define CRYPTO_num_locks wolfSSL_num_locks
+
+#define X509_STORE_CTX_get_current_cert wolfSSL_X509_STORE_CTX_get_current_cert
+#define X509_STORE_CTX_get_error wolfSSL_X509_STORE_CTX_get_error
+#define X509_STORE_CTX_get_error_depth wolfSSL_X509_STORE_CTX_get_error_depth
+
+#define X509_NAME_oneline             wolfSSL_X509_NAME_oneline
+#define X509_get_issuer_name          wolfSSL_X509_get_issuer_name
+#define X509_get_subject_name         wolfSSL_X509_get_subject_name
+#define X509_verify_cert_error_string wolfSSL_X509_verify_cert_error_string
+
+#define X509_LOOKUP_add_dir wolfSSL_X509_LOOKUP_add_dir
+#define X509_LOOKUP_load_file wolfSSL_X509_LOOKUP_load_file
+#define X509_LOOKUP_hash_dir wolfSSL_X509_LOOKUP_hash_dir
+#define X509_LOOKUP_file wolfSSL_X509_LOOKUP_file
+
+#define X509_STORE_add_lookup wolfSSL_X509_STORE_add_lookup
+#define X509_STORE_new wolfSSL_X509_STORE_new
+#define X509_STORE_get_by_subject wolfSSL_X509_STORE_get_by_subject
+#define X509_STORE_CTX_init wolfSSL_X509_STORE_CTX_init
+#define X509_STORE_CTX_cleanup wolfSSL_X509_STORE_CTX_cleanup
+
+#define X509_CRL_get_lastUpdate wolfSSL_X509_CRL_get_lastUpdate
+#define X509_CRL_get_nextUpdate wolfSSL_X509_CRL_get_nextUpdate
+
+#define X509_get_pubkey           wolfSSL_X509_get_pubkey
+#define X509_CRL_verify           wolfSSL_X509_CRL_verify
+#define X509_STORE_CTX_set_error  wolfSSL_X509_STORE_CTX_set_error
+#define X509_OBJECT_free_contents wolfSSL_X509_OBJECT_free_contents
+#define EVP_PKEY_free             wolfSSL_EVP_PKEY_free
+#define X509_cmp_current_time     wolfSSL_X509_cmp_current_time
+#define sk_X509_REVOKED_num       wolfSSL_sk_X509_REVOKED_num
+#define X509_CRL_get_REVOKED      wolfSSL_X509_CRL_get_REVOKED
+#define sk_X509_REVOKED_value     wolfSSL_sk_X509_REVOKED_value
+#define X509_get_notBefore(cert)  (ASN1_TIME*)wolfSSL_X509_notBefore((cert))
+#define X509_get_notAfter(cert)   (ASN1_TIME*)wolfSSL_X509_notAfter((cert))
+
+
+#define X509_get_serialNumber wolfSSL_X509_get_serialNumber
+
+#define ASN1_TIME_pr wolfSSL_ASN1_TIME_pr
+
+#define ASN1_INTEGER_cmp wolfSSL_ASN1_INTEGER_cmp
+#define ASN1_INTEGER_get wolfSSL_ASN1_INTEGER_get
+
+#define SSL_load_client_CA_file wolfSSL_load_client_CA_file
+
+#define SSL_CTX_set_client_CA_list         wolfSSL_CTX_set_client_CA_list
+#define X509_STORE_CTX_get_ex_data         wolfSSL_X509_STORE_CTX_get_ex_data
+#define SSL_get_ex_data_X509_STORE_CTX_idx wolfSSL_get_ex_data_X509_STORE_CTX_idx
+#define SSL_get_ex_data wolfSSL_get_ex_data
+
+#define SSL_CTX_set_default_passwd_cb_userdata wolfSSL_CTX_set_default_passwd_cb_userdata
+#define SSL_CTX_set_default_passwd_cb wolfSSL_CTX_set_default_passwd_cb
+
+#define SSL_CTX_set_timeout wolfSSL_CTX_set_timeout
+#define SSL_CTX_set_info_callback wolfSSL_CTX_set_info_callback
+
+#define ERR_peek_error wolfSSL_ERR_peek_error
+#define ERR_GET_REASON wolfSSL_ERR_GET_REASON
+
+#define SSL_alert_type_string wolfSSL_alert_type_string
+#define SSL_alert_desc_string wolfSSL_alert_desc_string
+#define SSL_state_string wolfSSL_state_string
+
+#define RSA_free wolfSSL_RSA_free
+#define RSA_generate_key wolfSSL_RSA_generate_key
+#define SSL_CTX_set_tmp_rsa_callback wolfSSL_CTX_set_tmp_rsa_callback
+
+#define PEM_def_callback wolfSSL_PEM_def_callback
+
+#define SSL_CTX_sess_accept wolfSSL_CTX_sess_accept
+#define SSL_CTX_sess_connect wolfSSL_CTX_sess_connect
+#define SSL_CTX_sess_accept_good wolfSSL_CTX_sess_accept_good
+#define SSL_CTX_sess_connect_good wolfSSL_CTX_sess_connect_good
+#define SSL_CTX_sess_accept_renegotiate wolfSSL_CTX_sess_accept_renegotiate
+#define SSL_CTX_sess_connect_renegotiate wolfSSL_CTX_sess_connect_renegotiate
+#define SSL_CTX_sess_hits wolfSSL_CTX_sess_hits
+#define SSL_CTX_sess_cb_hits wolfSSL_CTX_sess_cb_hits
+#define SSL_CTX_sess_cache_full wolfSSL_CTX_sess_cache_full
+#define SSL_CTX_sess_misses wolfSSL_CTX_sess_misses
+#define SSL_CTX_sess_timeouts wolfSSL_CTX_sess_timeouts
+#define SSL_CTX_sess_number wolfSSL_CTX_sess_number
+#define SSL_CTX_sess_get_cache_size wolfSSL_CTX_sess_get_cache_size
+
+
+#define SSL_DEFAULT_CIPHER_LIST WOLFSSL_DEFAULT_CIPHER_LIST
+#define RSA_F4 WOLFSSL_RSA_F4
+
+#define SSL_CTX_set_psk_client_callback wolfSSL_CTX_set_psk_client_callback
+#define SSL_set_psk_client_callback wolfSSL_set_psk_client_callback
+
+#define SSL_get_psk_identity_hint wolfSSL_get_psk_identity_hint
+#define SSL_get_psk_identity wolfSSL_get_psk_identity
+
+#define SSL_CTX_use_psk_identity_hint wolfSSL_CTX_use_psk_identity_hint
+#define SSL_use_psk_identity_hint wolfSSL_use_psk_identity_hint
+
+#define SSL_CTX_set_psk_server_callback wolfSSL_CTX_set_psk_server_callback
+#define SSL_set_psk_server_callback wolfSSL_set_psk_server_callback
+
+#define ERR_get_error_line_data wolfSSL_ERR_get_error_line_data
+
+#define ERR_get_error wolfSSL_ERR_get_error
+#define ERR_clear_error wolfSSL_ERR_clear_error
+
+#define RAND_status wolfSSL_RAND_status
+#define RAND_bytes wolfSSL_RAND_bytes
+#define SSLv23_server_method wolfSSLv23_server_method
+#define SSL_CTX_set_options wolfSSL_CTX_set_options 
+#define SSL_CTX_check_private_key wolfSSL_CTX_check_private_key
+
+#define ERR_free_strings wolfSSL_ERR_free_strings
+#define ERR_remove_state wolfSSL_ERR_remove_state
+#define EVP_cleanup wolfSSL_EVP_cleanup
+
+#define CRYPTO_cleanup_all_ex_data wolfSSL_cleanup_all_ex_data
+#define SSL_CTX_set_mode wolfSSL_CTX_set_mode
+#define SSL_CTX_get_mode wolfSSL_CTX_get_mode
+#define SSL_CTX_set_default_read_ahead wolfSSL_CTX_set_default_read_ahead
+
+#define SSL_CTX_sess_set_cache_size wolfSSL_CTX_sess_set_cache_size
+#define SSL_CTX_set_default_verify_paths wolfSSL_CTX_set_default_verify_paths
+
+#define SSL_CTX_set_session_id_context wolfSSL_CTX_set_session_id_context
+#define SSL_get_peer_certificate wolfSSL_get_peer_certificate
+
+#define SSL_want_read wolfSSL_want_read
+#define SSL_want_write wolfSSL_want_write
+
+#define BIO_prf wolfSSL_BIO_prf
+#define ASN1_UTCTIME_pr wolfSSL_ASN1_UTCTIME_pr
+
+#define sk_num wolfSSL_sk_num
+#define sk_value wolfSSL_sk_value
+
+#define SSL_CTX_get_ex_data wolfSSL_CTX_get_ex_data
+#define SSL_CTX_set_ex_data wolfSSL_CTX_set_ex_data
+#define SSL_CTX_sess_set_get_cb wolfSSL_CTX_sess_set_get_cb
+#define SSL_CTX_sess_set_new_cb wolfSSL_CTX_sess_set_new_cb
+#define SSL_CTX_sess_set_remove_cb wolfSSL_CTX_sess_set_remove_cb
+
+#define i2d_SSL_SESSION wolfSSL_i2d_SSL_SESSION
+#define d2i_SSL_SESSION wolfSSL_d2i_SSL_SESSION
+#define SSL_SESSION_set_timeout wolfSSL_SSL_SESSION_set_timeout
+#define SSL_SESSION_get_timeout wolfSSL_SESSION_get_timeout
+#define SSL_SESSION_get_time wolfSSL_SESSION_get_time
+#define SSL_CTX_get_ex_new_index wolfSSL_CTX_get_ex_new_index
+
+/* yassl had set the default to be 500 */
+#define SSL_get_default_timeout(ctx) 500
+
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+
+#endif /* wolfSSL_openssl_h__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/stack.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/stack.h
new file mode 100644
index 0000000..374c1fc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/stack.h
@@ -0,0 +1,2 @@
+/* stack.h for openssl */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/ui.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/ui.h
new file mode 100644
index 0000000..a253930
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/ui.h
@@ -0,0 +1,2 @@
+/* ui.h for openssl */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/x509.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/x509.h
new file mode 100644
index 0000000..9d13002
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/x509.h
@@ -0,0 +1,3 @@
+/* x509.h for openssl */
+
+#include 
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/x509v3.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/x509v3.h
new file mode 100644
index 0000000..77828a3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/openssl/x509v3.h
@@ -0,0 +1,2 @@
+/* x509v3.h for openssl */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/options.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/options.h
new file mode 100644
index 0000000..d1e362c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/options.h
@@ -0,0 +1,34 @@
+/* options.h.in
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+/* default blank options for autoconf */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/options.h.in b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/options.h.in
new file mode 100644
index 0000000..d1e362c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/options.h.in
@@ -0,0 +1,34 @@
+/* options.h.in
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+/* default blank options for autoconf */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/sniffer.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/sniffer.h
new file mode 100644
index 0000000..a14f883
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/sniffer.h
@@ -0,0 +1,82 @@
+/* sniffer.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifndef WOLFSSL_SNIFFER_H
+#define WOLFSSL_SNIFFER_H
+
+#include 
+
+#ifdef _WIN32
+    #ifdef SSL_SNIFFER_EXPORTS
+        #define SSL_SNIFFER_API __declspec(dllexport)
+    #else
+        #define SSL_SNIFFER_API __declspec(dllimport)
+    #endif
+#else
+    #define SSL_SNIFFER_API
+#endif /* _WIN32 */
+
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+/* @param typeK: (formerly keyType) was shadowing a global declaration in 
+ *                wolfssl/wolfcrypt/asn.h line 175
+ */
+WOLFSSL_API 
+SSL_SNIFFER_API int ssl_SetPrivateKey(const char* address, int port,
+                                      const char* keyFile, int typeK,
+                                      const char* password, char* error);
+
+WOLFSSL_API
+SSL_SNIFFER_API int ssl_SetNamedPrivateKey(const char* name,
+                                           const char* address, int port,
+                                           const char* keyFile, int typeK,
+                                           const char* password, char* error);
+
+WOLFSSL_API 
+SSL_SNIFFER_API int ssl_DecodePacket(const unsigned char* packet, int length,
+                                     unsigned char* data, char* error);
+
+WOLFSSL_API 
+SSL_SNIFFER_API int ssl_Trace(const char* traceFile, char* error);
+        
+        
+WOLFSSL_API void ssl_InitSniffer(void);
+        
+WOLFSSL_API void ssl_FreeSniffer(void);
+
+        
+/* ssl_SetPrivateKey typeKs */
+enum {
+    FILETYPE_PEM = 1,
+    FILETYPE_DER = 2,
+};
+
+
+#ifdef __cplusplus
+    }  /* extern "C" */
+#endif
+
+#endif /* wolfSSL_SNIFFER_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/sniffer_error.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/sniffer_error.h
new file mode 100644
index 0000000..ad89a50
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/sniffer_error.h
@@ -0,0 +1,114 @@
+/* sniffer_error.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifndef WOLFSSL_SNIFFER_ERROR_H
+#define WOLFSSL_SNIFFER_ERROR_H
+
+/* need to have errors as #defines since .rc files can't handle enums */
+/* need to start at 1 and go in order for same reason */
+
+#define MEMORY_STR 1
+#define NEW_SERVER_STR 2
+#define IP_CHECK_STR 3
+#define SERVER_NOT_REG_STR 4
+#define TCP_CHECK_STR 5
+#define SERVER_PORT_NOT_REG_STR 6
+#define RSA_DECRYPT_STR 7
+#define RSA_DECODE_STR 8
+#define BAD_CIPHER_SPEC_STR 9
+#define SERVER_HELLO_INPUT_STR 10
+
+#define BAD_SESSION_RESUME_STR 11
+#define SERVER_DID_RESUMPTION_STR 12
+#define CLIENT_HELLO_INPUT_STR 13
+#define CLIENT_RESUME_TRY_STR 14
+#define HANDSHAKE_INPUT_STR 15
+#define GOT_HELLO_VERIFY_STR 16
+#define GOT_SERVER_HELLO_STR 17
+#define GOT_CERT_REQ_STR 18
+#define GOT_SERVER_KEY_EX_STR 19
+#define GOT_CERT_STR 20
+
+#define GOT_SERVER_HELLO_DONE_STR 21
+#define GOT_FINISHED_STR 22
+#define GOT_CLIENT_HELLO_STR 23
+#define GOT_CLIENT_KEY_EX_STR 24
+#define GOT_CERT_VER_STR 25
+#define GOT_UNKNOWN_HANDSHAKE_STR 26
+#define NEW_SESSION_STR 27
+#define BAD_NEW_SSL_STR 28
+#define GOT_PACKET_STR 29
+#define NO_DATA_STR 30
+
+#define BAD_SESSION_STR 31
+#define GOT_OLD_CLIENT_HELLO_STR 32
+#define OLD_CLIENT_INPUT_STR 33
+#define OLD_CLIENT_OK_STR 34
+#define BAD_OLD_CLIENT_STR 35
+#define BAD_RECORD_HDR_STR 36
+#define RECORD_INPUT_STR 37
+#define GOT_HANDSHAKE_STR 38
+#define BAD_HANDSHAKE_STR 39
+#define GOT_CHANGE_CIPHER_STR 40
+
+#define GOT_APP_DATA_STR 41
+#define BAD_APP_DATA_STR 42
+#define GOT_ALERT_STR 43
+#define ANOTHER_MSG_STR 44
+#define REMOVE_SESSION_STR 45
+#define KEY_FILE_STR 46
+#define BAD_IPVER_STR 47
+#define BAD_PROTO_STR 48
+#define PACKET_HDR_SHORT_STR 49
+#define GOT_UNKNOWN_RECORD_STR 50
+
+#define BAD_TRACE_FILE_STR 51
+#define FATAL_ERROR_STR 52
+#define PARTIAL_INPUT_STR 53
+#define BUFFER_ERROR_STR 54
+#define PARTIAL_ADD_STR 55
+#define DUPLICATE_STR 56
+#define OUT_OF_ORDER_STR 57
+#define OVERLAP_DUPLICATE_STR 58
+#define OVERLAP_REASSEMBLY_BEGIN_STR 59
+#define OVERLAP_REASSEMBLY_END_STR 60
+
+#define MISSED_CLIENT_HELLO_STR 61
+#define GOT_HELLO_REQUEST_STR 62
+#define GOT_SESSION_TICKET_STR 63
+#define BAD_INPUT_STR 64
+#define BAD_DECRYPT_TYPE 65
+#define BAD_FINISHED_MSG 66
+#define BAD_COMPRESSION_STR 67
+#define BAD_DERIVE_STR 68
+#define ACK_MISSED_STR 69
+#define BAD_DECRYPT    70 
+
+#define DECRYPT_KEYS_NOT_SETUP 71
+#define CLIENT_HELLO_LATE_KEY_STR 72
+#define GOT_CERT_STATUS_STR 73
+#define RSA_KEY_MISSING_STR 74
+/* !!!! also add to msgTable in sniffer.c and .rc file !!!! */
+
+
+#endif /* wolfSSL_SNIFFER_ERROR_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/sniffer_error.rc b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/sniffer_error.rc
new file mode 100644
index 0000000..8bcd692
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/sniffer_error.rc
@@ -0,0 +1,93 @@
+
+STRINGTABLE 
+{
+    1, "Out of Memory"
+    2, "New SSL Sniffer Server Registered"
+    3, "Checking IP Header"
+    4, "SSL Sniffer Server Not Registered"
+    5, "Checking TCP Header"
+
+    6, "SSL Sniffer Server Port Not Registered"
+    7, "RSA Private Decrypt Error"
+    8, "RSA Private Decode Error"
+    9, "Set Cipher Spec Error"
+    10, "Server Hello Input Malformed"
+
+    11, "Couldn't Resume Session Error"
+    12, "Server Did Resumption"
+    13, "Client Hello Input Malformed"
+    14, "Client Trying to Resume"
+    15, "Handshake Input Malformed"
+
+    16, "Got Hello Verify msg"
+    17, "Got Server Hello msg"
+    18, "Got Cert Request msg"
+    19, "Got Server Key Exchange msg"
+    20, "Got Cert msg"
+
+    21, "Got Server Hello Done msg"
+    22, "Got Finished msg"
+    23, "Got Client Hello msg"
+    24, "Got Client Key Exchange msg"
+    25, "Got Cert Verify msg"
+
+    26, "Got Unknown Handshake msg"
+    27, "New SSL Sniffer Session created"
+    28, "Couldn't create new SSL"
+    29, "Got a Packet to decode"
+    30, "No data present"
+
+    31, "Session Not Found"
+    32, "Got an Old Client Hello msg"
+    33, "Old Client Hello Input Malformed"
+    34, "Old Client Hello OK"
+    35, "Bad Old Client Hello"
+
+    36, "Bad Record Header"
+    37, "Record Header Input Malformed"
+    38, "Got a HandShake msg"
+    39, "Bad HandShake msg"
+    40, "Got a Change Cipher Spec msg"
+
+    41, "Got Application Data msg"
+    42, "Bad Application Data"
+    43, "Got an Alert msg"
+    44, "Another msg to Process"
+    45, "Removing Session From Table"
+
+    46, "Bad Key File"
+    47, "Wrong IP Version"
+    48, "Wrong Protocol type"
+    49, "Packet Short for header processing"
+    50, "Got Unknown Record Type"
+    
+    51, "Can't Open Trace File"
+    52, "Session in Fatal Error State"
+    53, "Partial SSL record received"
+    54, "Buffer Error, malformed input"
+    55, "Added to Partial Input"
+
+    56, "Received a Duplicate Packet"
+    57, "Received an Out of Order Packet"
+    58, "Received an Overlap Duplicate Packet"
+    59, "Received an Overlap Reassembly Begin Duplicate Packet"
+    60, "Received an Overlap Reassembly End Duplicate Packet"
+    
+    61, "Missed the Client Hello Entirely"
+    62, "Got Hello Request msg"
+    63, "Got Session Ticket msg"
+    64, "Bad Input"
+    65, "Bad Decrypt Type"
+
+    66, "Bad Finished Message Processing"
+    67, "Bad Compression Type"
+    68, "Bad DeriveKeys Error"
+    69, "Saw ACK for Missing Packet Error"
+    70, "Bad Decrypt Operation"
+
+    71, "Decrypt Keys Not Set Up"
+    72, "Late Key Load Error"
+    73, "Got Certificate Status msg"
+    74, "RSA Key Missing Error"
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/ssl.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/ssl.h
new file mode 100644
index 0000000..9c3ac84
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/ssl.h
@@ -0,0 +1,1464 @@
+/* ssl.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+/* wolfSSL API */
+
+#ifndef WOLFSSL_SSL_H
+#define WOLFSSL_SSL_H
+
+
+/* for users not using preprocessor flags*/
+#include 
+#include 
+
+#ifndef NO_FILESYSTEM
+    #ifdef FREESCALE_MQX
+        #include 
+    #else
+        #include    /* ERR_printf */
+    #endif
+#endif
+
+#ifdef WOLFSSL_PREFIX
+    #include "prefix_ssl.h"
+#endif
+
+#ifdef LIBWOLFSSL_VERSION_STRING
+    #define WOLFSSL_VERSION LIBWOLFSSL_VERSION_STRING
+#endif
+
+#ifdef _WIN32
+    /* wincrypt.h clashes */
+    #undef OCSP_REQUEST
+    #undef OCSP_RESPONSE
+#endif
+
+
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+typedef struct WOLFSSL          WOLFSSL;
+typedef struct WOLFSSL_SESSION  WOLFSSL_SESSION;
+typedef struct WOLFSSL_METHOD   WOLFSSL_METHOD;
+typedef struct WOLFSSL_CTX      WOLFSSL_CTX;
+
+typedef struct WOLFSSL_X509       WOLFSSL_X509;
+typedef struct WOLFSSL_X509_NAME  WOLFSSL_X509_NAME;
+typedef struct WOLFSSL_X509_CHAIN WOLFSSL_X509_CHAIN;
+
+typedef struct WOLFSSL_CERT_MANAGER WOLFSSL_CERT_MANAGER;
+typedef struct WOLFSSL_SOCKADDR     WOLFSSL_SOCKADDR;
+
+/* redeclare guard */
+#define WOLFSSL_TYPES_DEFINED
+
+
+typedef struct WOLFSSL_RSA            WOLFSSL_RSA;
+typedef struct WOLFSSL_DSA            WOLFSSL_DSA;
+typedef struct WOLFSSL_CIPHER         WOLFSSL_CIPHER;
+typedef struct WOLFSSL_X509_LOOKUP    WOLFSSL_X509_LOOKUP;
+typedef struct WOLFSSL_X509_LOOKUP_METHOD WOLFSSL_X509_LOOKUP_METHOD;
+typedef struct WOLFSSL_X509_CRL       WOLFSSL_X509_CRL;
+typedef struct WOLFSSL_BIO            WOLFSSL_BIO;
+typedef struct WOLFSSL_BIO_METHOD     WOLFSSL_BIO_METHOD;
+typedef struct WOLFSSL_X509_EXTENSION WOLFSSL_X509_EXTENSION;
+typedef struct WOLFSSL_ASN1_TIME      WOLFSSL_ASN1_TIME;
+typedef struct WOLFSSL_ASN1_INTEGER   WOLFSSL_ASN1_INTEGER;
+typedef struct WOLFSSL_ASN1_OBJECT    WOLFSSL_ASN1_OBJECT;
+typedef struct WOLFSSL_ASN1_STRING    WOLFSSL_ASN1_STRING;
+typedef struct WOLFSSL_dynlock_value  WOLFSSL_dynlock_value;
+
+#define WOLFSSL_ASN1_UTCTIME WOLFSSL_ASN1_TIME
+
+typedef struct WOLFSSL_EVP_PKEY {
+    int type;         /* openssh dereference */
+    int save_type;    /* openssh dereference */
+    int pkey_sz;
+    union {
+        char* ptr;
+    } pkey;
+    #ifdef HAVE_ECC
+        int pkey_curve;
+    #endif
+} WOLFSSL_EVP_PKEY;
+
+typedef struct WOLFSSL_MD4_CTX {
+    int buffer[32];      /* big enough to hold, check size in Init */
+} WOLFSSL_MD4_CTX;
+
+
+typedef struct WOLFSSL_COMP_METHOD {
+    int type;            /* stunnel dereference */
+} WOLFSSL_COMP_METHOD;
+
+
+typedef struct WOLFSSL_X509_STORE {
+    int                  cache;          /* stunnel dereference */
+    WOLFSSL_CERT_MANAGER* cm;
+} WOLFSSL_X509_STORE;
+
+typedef struct WOLFSSL_ALERT {
+    int code;
+    int level;
+} WOLFSSL_ALERT;
+
+typedef struct WOLFSSL_ALERT_HISTORY {
+    WOLFSSL_ALERT last_rx;
+    WOLFSSL_ALERT last_tx;
+} WOLFSSL_ALERT_HISTORY;
+
+typedef struct WOLFSSL_X509_REVOKED {
+    WOLFSSL_ASN1_INTEGER* serialNumber;          /* stunnel dereference */
+} WOLFSSL_X509_REVOKED;
+
+
+typedef struct WOLFSSL_X509_OBJECT {
+    union {
+        char* ptr;
+        WOLFSSL_X509_CRL* crl;           /* stunnel dereference */
+    } data;
+} WOLFSSL_X509_OBJECT;
+
+
+typedef struct WOLFSSL_X509_STORE_CTX {
+    WOLFSSL_X509_STORE* store;    /* Store full of a CA cert chain */
+    WOLFSSL_X509* current_cert;   /* stunnel dereference */
+    char* domain;                /* subject CN domain name */
+    void* ex_data;               /* external data, for fortress build */
+    void* userCtx;               /* user ctx */
+    int   error;                 /* current error */
+    int   error_depth;           /* cert depth for this error */
+    int   discardSessionCerts;   /* so verify callback can flag for discard */
+} WOLFSSL_X509_STORE_CTX;
+
+
+/* Valid Alert types from page 16/17 */
+enum AlertDescription {
+    close_notify            = 0,
+    unexpected_message      = 10,
+    bad_record_mac          = 20,
+    record_overflow         = 22,
+    decompression_failure   = 30,
+    handshake_failure       = 40,
+    no_certificate          = 41,
+    bad_certificate         = 42,
+    unsupported_certificate = 43,
+    certificate_revoked     = 44,
+    certificate_expired     = 45,
+    certificate_unknown     = 46,
+    illegal_parameter       = 47,
+    decrypt_error           = 51,
+    #ifdef WOLFSSL_MYSQL_COMPATIBLE
+    /* catch name conflict for enum protocol with MYSQL build */
+    wc_protocol_version     = 70,
+    #else
+    protocol_version        = 70,
+    #endif
+    no_renegotiation        = 100,
+    unrecognized_name       = 112
+};
+
+
+enum AlertLevel {
+    alert_warning = 1,
+    alert_fatal = 2
+};
+
+
+WOLFSSL_API WOLFSSL_METHOD *wolfSSLv3_server_method(void);
+WOLFSSL_API WOLFSSL_METHOD *wolfSSLv3_client_method(void);
+WOLFSSL_API WOLFSSL_METHOD *wolfTLSv1_server_method(void);
+WOLFSSL_API WOLFSSL_METHOD *wolfTLSv1_client_method(void);
+WOLFSSL_API WOLFSSL_METHOD *wolfTLSv1_1_server_method(void);
+WOLFSSL_API WOLFSSL_METHOD *wolfTLSv1_1_client_method(void);
+WOLFSSL_API WOLFSSL_METHOD *wolfTLSv1_2_server_method(void);
+WOLFSSL_API WOLFSSL_METHOD *wolfTLSv1_2_client_method(void);
+
+#ifdef WOLFSSL_DTLS
+    WOLFSSL_API WOLFSSL_METHOD *wolfDTLSv1_client_method(void);
+    WOLFSSL_API WOLFSSL_METHOD *wolfDTLSv1_server_method(void);
+    WOLFSSL_API WOLFSSL_METHOD *wolfDTLSv1_2_client_method(void);
+    WOLFSSL_API WOLFSSL_METHOD *wolfDTLSv1_2_server_method(void);
+#endif
+
+#ifdef HAVE_POLY1305
+    WOLFSSL_API int wolfSSL_use_old_poly(WOLFSSL*, int);
+#endif
+
+#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS)
+
+WOLFSSL_API int wolfSSL_CTX_use_certificate_file(WOLFSSL_CTX*, const char*, int);
+WOLFSSL_API int wolfSSL_CTX_use_PrivateKey_file(WOLFSSL_CTX*, const char*, int);
+WOLFSSL_API int wolfSSL_CTX_load_verify_locations(WOLFSSL_CTX*, const char*,
+                                                const char*);
+WOLFSSL_API int wolfSSL_CTX_use_certificate_chain_file(WOLFSSL_CTX *,
+                                                     const char *file);
+WOLFSSL_API int wolfSSL_CTX_use_RSAPrivateKey_file(WOLFSSL_CTX*, const char*, int);
+
+WOLFSSL_API long wolfSSL_get_verify_depth(WOLFSSL* ssl);
+WOLFSSL_API long wolfSSL_CTX_get_verify_depth(WOLFSSL_CTX* ctx);
+WOLFSSL_API int wolfSSL_use_certificate_file(WOLFSSL*, const char*, int);
+WOLFSSL_API int wolfSSL_use_PrivateKey_file(WOLFSSL*, const char*, int);
+WOLFSSL_API int wolfSSL_use_certificate_chain_file(WOLFSSL*, const char *file);
+WOLFSSL_API int wolfSSL_use_RSAPrivateKey_file(WOLFSSL*, const char*, int);
+
+#ifdef WOLFSSL_DER_LOAD
+    WOLFSSL_API int wolfSSL_CTX_der_load_verify_locations(WOLFSSL_CTX*,
+                                                    const char*, int);
+#endif
+
+#ifdef HAVE_NTRU
+    WOLFSSL_API int wolfSSL_CTX_use_NTRUPrivateKey_file(WOLFSSL_CTX*, const char*);
+    /* load NTRU private key blob */
+#endif
+
+#ifndef WOLFSSL_PEMCERT_TODER_DEFINED
+    WOLFSSL_API int wolfSSL_PemCertToDer(const char*, unsigned char*, int);
+    #define WOLFSSL_PEMCERT_TODER_DEFINED
+#endif
+
+#endif /* !NO_FILESYSTEM && !NO_CERTS */
+
+WOLFSSL_API WOLFSSL_CTX* wolfSSL_CTX_new(WOLFSSL_METHOD*);
+WOLFSSL_API WOLFSSL* wolfSSL_new(WOLFSSL_CTX*);
+WOLFSSL_API int  wolfSSL_set_fd (WOLFSSL*, int);
+WOLFSSL_API char* wolfSSL_get_cipher_list(int priority);
+WOLFSSL_API int  wolfSSL_get_ciphers(char*, int);
+WOLFSSL_API int  wolfSSL_get_fd(const WOLFSSL*);
+WOLFSSL_API void wolfSSL_set_using_nonblock(WOLFSSL*, int);
+WOLFSSL_API int  wolfSSL_get_using_nonblock(WOLFSSL*);
+WOLFSSL_API int  wolfSSL_connect(WOLFSSL*);     /* please see note at top of README
+                                             if you get an error from connect */
+WOLFSSL_API int  wolfSSL_write(WOLFSSL*, const void*, int);
+WOLFSSL_API int  wolfSSL_read(WOLFSSL*, void*, int);
+WOLFSSL_API int  wolfSSL_peek(WOLFSSL*, void*, int);
+WOLFSSL_API int  wolfSSL_accept(WOLFSSL*);
+WOLFSSL_API void wolfSSL_CTX_free(WOLFSSL_CTX*);
+WOLFSSL_API void wolfSSL_free(WOLFSSL*);
+WOLFSSL_API int  wolfSSL_shutdown(WOLFSSL*);
+WOLFSSL_API int  wolfSSL_send(WOLFSSL*, const void*, int sz, int flags);
+WOLFSSL_API int  wolfSSL_recv(WOLFSSL*, void*, int sz, int flags);
+
+WOLFSSL_API void wolfSSL_CTX_set_quiet_shutdown(WOLFSSL_CTX*, int);
+WOLFSSL_API void wolfSSL_set_quiet_shutdown(WOLFSSL*, int);
+
+WOLFSSL_API int  wolfSSL_get_error(WOLFSSL*, int);
+WOLFSSL_API int  wolfSSL_get_alert_history(WOLFSSL*, WOLFSSL_ALERT_HISTORY *);
+
+WOLFSSL_API int        wolfSSL_set_session(WOLFSSL* ssl,WOLFSSL_SESSION* session);
+WOLFSSL_API long       wolfSSL_SSL_SESSION_set_timeout(WOLFSSL_SESSION* session, long t);
+WOLFSSL_API WOLFSSL_SESSION* wolfSSL_get_session(WOLFSSL* ssl);
+WOLFSSL_API void       wolfSSL_flush_sessions(WOLFSSL_CTX *ctx, long tm);
+WOLFSSL_API int        wolfSSL_SetServerID(WOLFSSL* ssl, const unsigned char*,
+                                         int, int);
+
+#ifdef SESSION_INDEX
+WOLFSSL_API int wolfSSL_GetSessionIndex(WOLFSSL* ssl);
+WOLFSSL_API int wolfSSL_GetSessionAtIndex(int index, WOLFSSL_SESSION* session);
+#endif /* SESSION_INDEX */
+
+#if defined(SESSION_INDEX) && defined(SESSION_CERTS)
+WOLFSSL_API
+    WOLFSSL_X509_CHAIN* wolfSSL_SESSION_get_peer_chain(WOLFSSL_SESSION* session);
+#endif /* SESSION_INDEX && SESSION_CERTS */
+
+typedef int (*VerifyCallback)(int, WOLFSSL_X509_STORE_CTX*);
+typedef int (*pem_password_cb)(char*, int, int, void*);
+
+WOLFSSL_API void wolfSSL_CTX_set_verify(WOLFSSL_CTX*, int,
+                                      VerifyCallback verify_callback);
+WOLFSSL_API void wolfSSL_set_verify(WOLFSSL*, int, VerifyCallback verify_callback);
+WOLFSSL_API void wolfSSL_SetCertCbCtx(WOLFSSL*, void*);
+
+WOLFSSL_API int  wolfSSL_pending(WOLFSSL*);
+
+WOLFSSL_API void wolfSSL_load_error_strings(void);
+WOLFSSL_API int  wolfSSL_library_init(void);
+WOLFSSL_API long wolfSSL_CTX_set_session_cache_mode(WOLFSSL_CTX*, long);
+
+#ifdef HAVE_SECRET_CALLBACK
+typedef int (*SessionSecretCb)(WOLFSSL* ssl,
+                                        void* secret, int* secretSz, void* ctx);
+WOLFSSL_API int  wolfSSL_set_session_secret_cb(WOLFSSL*, SessionSecretCb, void*);
+#endif /* HAVE_SECRET_CALLBACK */
+
+/* session cache persistence */
+WOLFSSL_API int  wolfSSL_save_session_cache(const char*);
+WOLFSSL_API int  wolfSSL_restore_session_cache(const char*);
+WOLFSSL_API int  wolfSSL_memsave_session_cache(void*, int);
+WOLFSSL_API int  wolfSSL_memrestore_session_cache(const void*, int);
+WOLFSSL_API int  wolfSSL_get_session_cache_memsize(void);
+
+/* certificate cache persistence, uses ctx since certs are per ctx */
+WOLFSSL_API int  wolfSSL_CTX_save_cert_cache(WOLFSSL_CTX*, const char*);
+WOLFSSL_API int  wolfSSL_CTX_restore_cert_cache(WOLFSSL_CTX*, const char*);
+WOLFSSL_API int  wolfSSL_CTX_memsave_cert_cache(WOLFSSL_CTX*, void*, int, int*);
+WOLFSSL_API int  wolfSSL_CTX_memrestore_cert_cache(WOLFSSL_CTX*, const void*, int);
+WOLFSSL_API int  wolfSSL_CTX_get_cert_cache_memsize(WOLFSSL_CTX*);
+
+/* only supports full name from cipher_name[] delimited by : */
+WOLFSSL_API int  wolfSSL_CTX_set_cipher_list(WOLFSSL_CTX*, const char*);
+WOLFSSL_API int  wolfSSL_set_cipher_list(WOLFSSL*, const char*);
+
+/* Nonblocking DTLS helper functions */
+WOLFSSL_API int  wolfSSL_dtls_get_current_timeout(WOLFSSL* ssl);
+WOLFSSL_API int  wolfSSL_dtls_set_timeout_init(WOLFSSL* ssl, int);
+WOLFSSL_API int  wolfSSL_dtls_set_timeout_max(WOLFSSL* ssl, int);
+WOLFSSL_API int  wolfSSL_dtls_got_timeout(WOLFSSL* ssl);
+WOLFSSL_API int  wolfSSL_dtls(WOLFSSL* ssl);
+
+WOLFSSL_API int  wolfSSL_dtls_set_peer(WOLFSSL*, void*, unsigned int);
+WOLFSSL_API int  wolfSSL_dtls_get_peer(WOLFSSL*, void*, unsigned int*);
+
+WOLFSSL_API int   wolfSSL_ERR_GET_REASON(int err);
+WOLFSSL_API char* wolfSSL_ERR_error_string(unsigned long,char*);
+WOLFSSL_API void  wolfSSL_ERR_error_string_n(unsigned long e, char* buf,
+                                           unsigned long sz);
+WOLFSSL_API const char* wolfSSL_ERR_reason_error_string(unsigned long);
+
+/* extras */
+
+#define STACK_OF(x) x
+
+WOLFSSL_API int  wolfSSL_set_ex_data(WOLFSSL*, int, void*);
+WOLFSSL_API int  wolfSSL_get_shutdown(const WOLFSSL*);
+WOLFSSL_API int  wolfSSL_set_rfd(WOLFSSL*, int);
+WOLFSSL_API int  wolfSSL_set_wfd(WOLFSSL*, int);
+WOLFSSL_API void wolfSSL_set_shutdown(WOLFSSL*, int);
+WOLFSSL_API int  wolfSSL_set_session_id_context(WOLFSSL*, const unsigned char*,
+                                           unsigned int);
+WOLFSSL_API void wolfSSL_set_connect_state(WOLFSSL*);
+WOLFSSL_API void wolfSSL_set_accept_state(WOLFSSL*);
+WOLFSSL_API int  wolfSSL_session_reused(WOLFSSL*);
+WOLFSSL_API void wolfSSL_SESSION_free(WOLFSSL_SESSION* session);
+WOLFSSL_API int  wolfSSL_is_init_finished(WOLFSSL*);
+
+WOLFSSL_API const char*  wolfSSL_get_version(WOLFSSL*);
+WOLFSSL_API int  wolfSSL_get_current_cipher_suite(WOLFSSL* ssl);
+WOLFSSL_API WOLFSSL_CIPHER*  wolfSSL_get_current_cipher(WOLFSSL*);
+WOLFSSL_API char*        wolfSSL_CIPHER_description(WOLFSSL_CIPHER*, char*, int);
+WOLFSSL_API const char*  wolfSSL_CIPHER_get_name(const WOLFSSL_CIPHER* cipher);
+WOLFSSL_API const char*  wolfSSL_get_cipher(WOLFSSL*);
+WOLFSSL_API WOLFSSL_SESSION* wolfSSL_get1_session(WOLFSSL* ssl);
+                           /* what's ref count */
+
+WOLFSSL_API void wolfSSL_X509_free(WOLFSSL_X509*);
+WOLFSSL_API void wolfSSL_OPENSSL_free(void*);
+
+WOLFSSL_API int wolfSSL_OCSP_parse_url(char* url, char** host, char** port,
+                                     char** path, int* ssl);
+
+WOLFSSL_API WOLFSSL_METHOD* wolfSSLv23_client_method(void);
+WOLFSSL_API WOLFSSL_METHOD* wolfSSLv2_client_method(void);
+WOLFSSL_API WOLFSSL_METHOD* wolfSSLv2_server_method(void);
+
+WOLFSSL_API void wolfSSL_MD4_Init(WOLFSSL_MD4_CTX*);
+WOLFSSL_API void wolfSSL_MD4_Update(WOLFSSL_MD4_CTX*, const void*, unsigned long);
+WOLFSSL_API void wolfSSL_MD4_Final(unsigned char*, WOLFSSL_MD4_CTX*);
+
+
+WOLFSSL_API WOLFSSL_BIO* wolfSSL_BIO_new(WOLFSSL_BIO_METHOD*);
+WOLFSSL_API int  wolfSSL_BIO_free(WOLFSSL_BIO*);
+WOLFSSL_API int  wolfSSL_BIO_free_all(WOLFSSL_BIO*);
+WOLFSSL_API int  wolfSSL_BIO_read(WOLFSSL_BIO*, void*, int);
+WOLFSSL_API int  wolfSSL_BIO_write(WOLFSSL_BIO*, const void*, int);
+WOLFSSL_API WOLFSSL_BIO* wolfSSL_BIO_push(WOLFSSL_BIO*, WOLFSSL_BIO* append);
+WOLFSSL_API WOLFSSL_BIO* wolfSSL_BIO_pop(WOLFSSL_BIO*);
+WOLFSSL_API int  wolfSSL_BIO_flush(WOLFSSL_BIO*);
+WOLFSSL_API int  wolfSSL_BIO_pending(WOLFSSL_BIO*);
+
+WOLFSSL_API WOLFSSL_BIO_METHOD* wolfSSL_BIO_f_buffer(void);
+WOLFSSL_API long wolfSSL_BIO_set_write_buffer_size(WOLFSSL_BIO*, long size);
+WOLFSSL_API WOLFSSL_BIO_METHOD* wolfSSL_BIO_f_ssl(void);
+WOLFSSL_API WOLFSSL_BIO*        wolfSSL_BIO_new_socket(int sfd, int flag);
+WOLFSSL_API int         wolfSSL_BIO_eof(WOLFSSL_BIO*);
+
+WOLFSSL_API WOLFSSL_BIO_METHOD* wolfSSL_BIO_s_mem(void);
+WOLFSSL_API WOLFSSL_BIO_METHOD* wolfSSL_BIO_f_base64(void);
+WOLFSSL_API void wolfSSL_BIO_set_flags(WOLFSSL_BIO*, int);
+
+WOLFSSL_API int wolfSSL_BIO_get_mem_data(WOLFSSL_BIO* bio,const unsigned char** p);
+WOLFSSL_API WOLFSSL_BIO* wolfSSL_BIO_new_mem_buf(void* buf, int len);
+
+
+WOLFSSL_API long        wolfSSL_BIO_set_ssl(WOLFSSL_BIO*, WOLFSSL*, int flag);
+WOLFSSL_API void        wolfSSL_set_bio(WOLFSSL*, WOLFSSL_BIO* rd, WOLFSSL_BIO* wr);
+
+WOLFSSL_API int  wolfSSL_add_all_algorithms(void);
+
+WOLFSSL_API void        wolfSSL_RAND_screen(void);
+WOLFSSL_API const char* wolfSSL_RAND_file_name(char*, unsigned long);
+WOLFSSL_API int         wolfSSL_RAND_write_file(const char*);
+WOLFSSL_API int         wolfSSL_RAND_load_file(const char*, long);
+WOLFSSL_API int         wolfSSL_RAND_egd(const char*);
+WOLFSSL_API int         wolfSSL_RAND_seed(const void*, int);
+WOLFSSL_API void        wolfSSL_RAND_add(const void*, int, double);
+
+WOLFSSL_API WOLFSSL_COMP_METHOD* wolfSSL_COMP_zlib(void);
+WOLFSSL_API WOLFSSL_COMP_METHOD* wolfSSL_COMP_rle(void);
+WOLFSSL_API int wolfSSL_COMP_add_compression_method(int, void*);
+
+WOLFSSL_API int wolfSSL_get_ex_new_index(long, void*, void*, void*, void*);
+
+WOLFSSL_API void wolfSSL_set_id_callback(unsigned long (*f)(void));
+WOLFSSL_API void wolfSSL_set_locking_callback(void (*f)(int, int, const char*,
+                                                      int));
+WOLFSSL_API void wolfSSL_set_dynlock_create_callback(WOLFSSL_dynlock_value* (*f)
+                                                   (const char*, int));
+WOLFSSL_API void wolfSSL_set_dynlock_lock_callback(void (*f)(int,
+                                      WOLFSSL_dynlock_value*, const char*, int));
+WOLFSSL_API void wolfSSL_set_dynlock_destroy_callback(void (*f)
+                                     (WOLFSSL_dynlock_value*, const char*, int));
+WOLFSSL_API int  wolfSSL_num_locks(void);
+
+WOLFSSL_API WOLFSSL_X509* wolfSSL_X509_STORE_CTX_get_current_cert(
+                                                        WOLFSSL_X509_STORE_CTX*);
+WOLFSSL_API int   wolfSSL_X509_STORE_CTX_get_error(WOLFSSL_X509_STORE_CTX*);
+WOLFSSL_API int   wolfSSL_X509_STORE_CTX_get_error_depth(WOLFSSL_X509_STORE_CTX*);
+
+WOLFSSL_API char*       wolfSSL_X509_NAME_oneline(WOLFSSL_X509_NAME*, char*, int);
+WOLFSSL_API WOLFSSL_X509_NAME*  wolfSSL_X509_get_issuer_name(WOLFSSL_X509*);
+WOLFSSL_API WOLFSSL_X509_NAME*  wolfSSL_X509_get_subject_name(WOLFSSL_X509*);
+WOLFSSL_API int  wolfSSL_X509_ext_isSet_by_NID(WOLFSSL_X509*, int);
+WOLFSSL_API int  wolfSSL_X509_ext_get_critical_by_NID(WOLFSSL_X509*, int);
+WOLFSSL_API int  wolfSSL_X509_get_isCA(WOLFSSL_X509*);
+WOLFSSL_API int  wolfSSL_X509_get_isSet_pathLength(WOLFSSL_X509*);
+WOLFSSL_API unsigned int wolfSSL_X509_get_pathLength(WOLFSSL_X509*);
+WOLFSSL_API unsigned int wolfSSL_X509_get_keyUsage(WOLFSSL_X509*);
+WOLFSSL_API unsigned char* wolfSSL_X509_get_authorityKeyID(
+                                            WOLFSSL_X509*, unsigned char*, int*);
+WOLFSSL_API unsigned char* wolfSSL_X509_get_subjectKeyID(
+                                            WOLFSSL_X509*, unsigned char*, int*);
+WOLFSSL_API int wolfSSL_X509_NAME_entry_count(WOLFSSL_X509_NAME*);
+WOLFSSL_API int wolfSSL_X509_NAME_get_text_by_NID(
+                                            WOLFSSL_X509_NAME*, int, char*, int);
+WOLFSSL_API int         wolfSSL_X509_verify_cert(WOLFSSL_X509_STORE_CTX*);
+WOLFSSL_API const char* wolfSSL_X509_verify_cert_error_string(long);
+WOLFSSL_API int wolfSSL_X509_get_signature_type(WOLFSSL_X509*);
+WOLFSSL_API int wolfSSL_X509_get_signature(WOLFSSL_X509*, unsigned char*, int*);
+
+WOLFSSL_API int wolfSSL_X509_LOOKUP_add_dir(WOLFSSL_X509_LOOKUP*,const char*,long);
+WOLFSSL_API int wolfSSL_X509_LOOKUP_load_file(WOLFSSL_X509_LOOKUP*, const char*,
+                                            long);
+WOLFSSL_API WOLFSSL_X509_LOOKUP_METHOD* wolfSSL_X509_LOOKUP_hash_dir(void);
+WOLFSSL_API WOLFSSL_X509_LOOKUP_METHOD* wolfSSL_X509_LOOKUP_file(void);
+
+WOLFSSL_API WOLFSSL_X509_LOOKUP* wolfSSL_X509_STORE_add_lookup(WOLFSSL_X509_STORE*,
+                                                    WOLFSSL_X509_LOOKUP_METHOD*);
+WOLFSSL_API WOLFSSL_X509_STORE*  wolfSSL_X509_STORE_new(void);
+WOLFSSL_API void         wolfSSL_X509_STORE_free(WOLFSSL_X509_STORE*);
+WOLFSSL_API int          wolfSSL_X509_STORE_add_cert(
+                                              WOLFSSL_X509_STORE*, WOLFSSL_X509*);
+WOLFSSL_API int          wolfSSL_X509_STORE_set_default_paths(WOLFSSL_X509_STORE*);
+WOLFSSL_API int          wolfSSL_X509_STORE_get_by_subject(WOLFSSL_X509_STORE_CTX*,
+                                   int, WOLFSSL_X509_NAME*, WOLFSSL_X509_OBJECT*);
+WOLFSSL_API WOLFSSL_X509_STORE_CTX* wolfSSL_X509_STORE_CTX_new(void);
+WOLFSSL_API int  wolfSSL_X509_STORE_CTX_init(WOLFSSL_X509_STORE_CTX*,
+                      WOLFSSL_X509_STORE*, WOLFSSL_X509*, STACK_OF(WOLFSSL_X509)*);
+WOLFSSL_API void wolfSSL_X509_STORE_CTX_free(WOLFSSL_X509_STORE_CTX*);
+WOLFSSL_API void wolfSSL_X509_STORE_CTX_cleanup(WOLFSSL_X509_STORE_CTX*);
+
+WOLFSSL_API WOLFSSL_ASN1_TIME* wolfSSL_X509_CRL_get_lastUpdate(WOLFSSL_X509_CRL*);
+WOLFSSL_API WOLFSSL_ASN1_TIME* wolfSSL_X509_CRL_get_nextUpdate(WOLFSSL_X509_CRL*);
+
+WOLFSSL_API WOLFSSL_EVP_PKEY* wolfSSL_X509_get_pubkey(WOLFSSL_X509*);
+WOLFSSL_API int       wolfSSL_X509_CRL_verify(WOLFSSL_X509_CRL*, WOLFSSL_EVP_PKEY*);
+WOLFSSL_API void      wolfSSL_X509_STORE_CTX_set_error(WOLFSSL_X509_STORE_CTX*,
+                                                     int);
+WOLFSSL_API void      wolfSSL_X509_OBJECT_free_contents(WOLFSSL_X509_OBJECT*);
+WOLFSSL_API void      wolfSSL_EVP_PKEY_free(WOLFSSL_EVP_PKEY*);
+WOLFSSL_API int       wolfSSL_X509_cmp_current_time(const WOLFSSL_ASN1_TIME*);
+WOLFSSL_API int       wolfSSL_sk_X509_REVOKED_num(WOLFSSL_X509_REVOKED*);
+
+WOLFSSL_API WOLFSSL_X509_REVOKED* wolfSSL_X509_CRL_get_REVOKED(WOLFSSL_X509_CRL*);
+WOLFSSL_API WOLFSSL_X509_REVOKED* wolfSSL_sk_X509_REVOKED_value(
+                                                      WOLFSSL_X509_REVOKED*,int);
+WOLFSSL_API WOLFSSL_ASN1_INTEGER* wolfSSL_X509_get_serialNumber(WOLFSSL_X509*);
+
+WOLFSSL_API int wolfSSL_ASN1_TIME_print(WOLFSSL_BIO*, const WOLFSSL_ASN1_TIME*);
+
+WOLFSSL_API int  wolfSSL_ASN1_INTEGER_cmp(const WOLFSSL_ASN1_INTEGER*,
+                                       const WOLFSSL_ASN1_INTEGER*);
+WOLFSSL_API long wolfSSL_ASN1_INTEGER_get(const WOLFSSL_ASN1_INTEGER*);
+
+WOLFSSL_API STACK_OF(WOLFSSL_X509_NAME)* wolfSSL_load_client_CA_file(const char*);
+
+WOLFSSL_API void  wolfSSL_CTX_set_client_CA_list(WOLFSSL_CTX*,
+                                               STACK_OF(WOLFSSL_X509_NAME)*);
+WOLFSSL_API void* wolfSSL_X509_STORE_CTX_get_ex_data(WOLFSSL_X509_STORE_CTX*, int);
+WOLFSSL_API int   wolfSSL_get_ex_data_X509_STORE_CTX_idx(void);
+WOLFSSL_API void* wolfSSL_get_ex_data(const WOLFSSL*, int);
+
+WOLFSSL_API void wolfSSL_CTX_set_default_passwd_cb_userdata(WOLFSSL_CTX*,
+                                                          void* userdata);
+WOLFSSL_API void wolfSSL_CTX_set_default_passwd_cb(WOLFSSL_CTX*, pem_password_cb);
+
+
+WOLFSSL_API void wolfSSL_CTX_set_info_callback(WOLFSSL_CTX*, void (*)(void));
+
+WOLFSSL_API unsigned long wolfSSL_ERR_peek_error(void);
+WOLFSSL_API int           wolfSSL_GET_REASON(int);
+
+WOLFSSL_API char* wolfSSL_alert_type_string_long(int);
+WOLFSSL_API char* wolfSSL_alert_desc_string_long(int);
+WOLFSSL_API char* wolfSSL_state_string_long(WOLFSSL*);
+
+WOLFSSL_API WOLFSSL_RSA* wolfSSL_RSA_generate_key(int, unsigned long,
+                                               void(*)(int, int, void*), void*);
+WOLFSSL_API void wolfSSL_CTX_set_tmp_rsa_callback(WOLFSSL_CTX*,
+                                             WOLFSSL_RSA*(*)(WOLFSSL*, int, int));
+
+WOLFSSL_API int wolfSSL_PEM_def_callback(char*, int num, int w, void* key);
+
+WOLFSSL_API long wolfSSL_CTX_sess_accept(WOLFSSL_CTX*);
+WOLFSSL_API long wolfSSL_CTX_sess_connect(WOLFSSL_CTX*);
+WOLFSSL_API long wolfSSL_CTX_sess_accept_good(WOLFSSL_CTX*);
+WOLFSSL_API long wolfSSL_CTX_sess_connect_good(WOLFSSL_CTX*);
+WOLFSSL_API long wolfSSL_CTX_sess_accept_renegotiate(WOLFSSL_CTX*);
+WOLFSSL_API long wolfSSL_CTX_sess_connect_renegotiate(WOLFSSL_CTX*);
+WOLFSSL_API long wolfSSL_CTX_sess_hits(WOLFSSL_CTX*);
+WOLFSSL_API long wolfSSL_CTX_sess_cb_hits(WOLFSSL_CTX*);
+WOLFSSL_API long wolfSSL_CTX_sess_cache_full(WOLFSSL_CTX*);
+WOLFSSL_API long wolfSSL_CTX_sess_misses(WOLFSSL_CTX*);
+WOLFSSL_API long wolfSSL_CTX_sess_timeouts(WOLFSSL_CTX*);
+WOLFSSL_API long wolfSSL_CTX_sess_number(WOLFSSL_CTX*);
+WOLFSSL_API long wolfSSL_CTX_sess_get_cache_size(WOLFSSL_CTX*);
+
+#define WOLFSSL_DEFAULT_CIPHER_LIST ""   /* default all */
+#define WOLFSSL_RSA_F4 0x10001L
+
+enum {
+    OCSP_NOCERTS     = 1,
+    OCSP_NOINTERN    = 2,
+    OCSP_NOSIGS      = 4,
+    OCSP_NOCHAIN     = 8,
+    OCSP_NOVERIFY    = 16,
+    OCSP_NOEXPLICIT  = 32,
+    OCSP_NOCASIGN    = 64,
+    OCSP_NODELEGATED = 128,
+    OCSP_NOCHECKS    = 256,
+    OCSP_TRUSTOTHER  = 512,
+    OCSP_RESPID_KEY  = 1024,
+    OCSP_NOTIME      = 2048,
+
+    OCSP_CERTID   = 2,
+    OCSP_REQUEST  = 4,
+    OCSP_RESPONSE = 8,
+    OCSP_BASICRESP = 16,
+
+    WOLFSSL_OCSP_URL_OVERRIDE = 1,
+    WOLFSSL_OCSP_NO_NONCE     = 2,
+    WOLFSSL_OCSP_CHECKALL     = 4,
+
+    WOLFSSL_CRL_CHECKALL = 1,
+
+    ASN1_GENERALIZEDTIME = 4,
+
+    SSL_OP_MICROSOFT_SESS_ID_BUG = 1,
+    SSL_OP_NETSCAPE_CHALLENGE_BUG = 2,
+    SSL_OP_NETSCAPE_REUSE_CIPHER_CHANGE_BUG = 3,
+    SSL_OP_SSLREF2_REUSE_CERT_TYPE_BUG = 4,
+    SSL_OP_MICROSOFT_BIG_SSLV3_BUFFER = 5,
+    SSL_OP_MSIE_SSLV2_RSA_PADDING = 6,
+    SSL_OP_SSLEAY_080_CLIENT_DH_BUG = 7,
+    SSL_OP_TLS_D5_BUG = 8,
+    SSL_OP_TLS_BLOCK_PADDING_BUG = 9,
+    SSL_OP_TLS_ROLLBACK_BUG = 10,
+    SSL_OP_ALL = 11,
+    SSL_OP_EPHEMERAL_RSA = 12,
+    SSL_OP_NO_SSLv3 = 13,
+    SSL_OP_NO_TLSv1 = 14,
+    SSL_OP_PKCS1_CHECK_1 = 15,
+    SSL_OP_PKCS1_CHECK_2 = 16,
+    SSL_OP_NETSCAPE_CA_DN_BUG = 17,
+    SSL_OP_NETSCAPE_DEMO_CIPHER_CHANGE_BUG = 18,
+    SSL_OP_SINGLE_DH_USE = 19,
+    SSL_OP_NO_TICKET = 20,
+    SSL_OP_DONT_INSERT_EMPTY_FRAGMENTS = 21,
+    SSL_OP_NO_QUERY_MTU = 22,
+    SSL_OP_COOKIE_EXCHANGE = 23,
+    SSL_OP_NO_SESSION_RESUMPTION_ON_RENEGOTIATION = 24,
+    SSL_OP_SINGLE_ECDH_USE = 25,
+    SSL_OP_CIPHER_SERVER_PREFERENCE = 26,
+
+    SSL_MAX_SSL_SESSION_ID_LENGTH = 32,
+
+    EVP_R_BAD_DECRYPT = 2,
+
+    SSL_CB_LOOP = 4,
+    SSL_ST_CONNECT = 5,
+    SSL_ST_ACCEPT  = 6,
+    SSL_CB_ALERT   = 7,
+    SSL_CB_READ    = 8,
+    SSL_CB_HANDSHAKE_DONE = 9,
+
+    SSL_MODE_ENABLE_PARTIAL_WRITE = 2,
+
+    BIO_FLAGS_BASE64_NO_NL = 1,
+    BIO_CLOSE   = 1,
+    BIO_NOCLOSE = 0,
+
+    NID_undef = 0,
+
+    X509_FILETYPE_PEM = 8,
+    X509_LU_X509      = 9,
+    X509_LU_CRL       = 12,
+
+    X509_V_ERR_CRL_SIGNATURE_FAILURE = 13,
+    X509_V_ERR_ERROR_IN_CRL_NEXT_UPDATE_FIELD = 14,
+    X509_V_ERR_CRL_HAS_EXPIRED                = 15,
+    X509_V_ERR_CERT_REVOKED                   = 16,
+    X509_V_ERR_CERT_CHAIN_TOO_LONG            = 17,
+    X509_V_ERR_UNABLE_TO_GET_ISSUER_CERT      = 18,
+    X509_V_ERR_CERT_NOT_YET_VALID             = 19,
+    X509_V_ERR_ERROR_IN_CERT_NOT_BEFORE_FIELD = 20,
+    X509_V_ERR_CERT_HAS_EXPIRED               = 21,
+    X509_V_ERR_ERROR_IN_CERT_NOT_AFTER_FIELD  = 22,
+
+    X509_V_OK = 0,
+
+    CRYPTO_LOCK = 1,
+    CRYPTO_NUM_LOCKS = 10
+};
+
+/* extras end */
+
+#if !defined(NO_FILESYSTEM) && !defined(NO_STDIO_FILESYSTEM)
+/* wolfSSL extension, provide last error from SSL_get_error
+   since not using thread storage error queue */
+WOLFSSL_API void  wolfSSL_ERR_print_errors_fp(FILE*, int err);
+#endif
+
+enum { /* ssl Constants */
+    SSL_ERROR_NONE      =  0,   /* for most functions */
+    SSL_FAILURE         =  0,   /* for some functions */
+    SSL_SUCCESS         =  1,
+    SSL_SHUTDOWN_NOT_DONE =  2,  /* call wolfSSL_shutdown again to complete */
+
+    SSL_BAD_CERTTYPE    = -8,
+    SSL_BAD_STAT        = -7,
+    SSL_BAD_PATH        = -6,
+    SSL_BAD_FILETYPE    = -5,
+    SSL_BAD_FILE        = -4,
+    SSL_NOT_IMPLEMENTED = -3,
+    SSL_UNKNOWN         = -2,
+    SSL_FATAL_ERROR     = -1,
+
+    SSL_FILETYPE_ASN1    = 2,
+    SSL_FILETYPE_PEM     = 1,
+    SSL_FILETYPE_DEFAULT = 2, /* ASN1 */
+    SSL_FILETYPE_RAW     = 3, /* NTRU raw key blob */
+
+    SSL_VERIFY_NONE                 = 0,
+    SSL_VERIFY_PEER                 = 1,
+    SSL_VERIFY_FAIL_IF_NO_PEER_CERT = 2,
+    SSL_VERIFY_CLIENT_ONCE          = 4,
+
+    SSL_SESS_CACHE_OFF                = 30,
+    SSL_SESS_CACHE_CLIENT             = 31,
+    SSL_SESS_CACHE_SERVER             = 32,
+    SSL_SESS_CACHE_BOTH               = 33,
+    SSL_SESS_CACHE_NO_AUTO_CLEAR      = 34,
+    SSL_SESS_CACHE_NO_INTERNAL_LOOKUP = 35,
+
+    SSL_ERROR_WANT_READ        =  2,
+    SSL_ERROR_WANT_WRITE       =  3,
+    SSL_ERROR_WANT_CONNECT     =  7,
+    SSL_ERROR_WANT_ACCEPT      =  8,
+    SSL_ERROR_SYSCALL          =  5,
+    SSL_ERROR_WANT_X509_LOOKUP = 83,
+    SSL_ERROR_ZERO_RETURN      =  6,
+    SSL_ERROR_SSL              = 85,
+
+    SSL_SENT_SHUTDOWN     = 1,
+    SSL_RECEIVED_SHUTDOWN = 2,
+    SSL_MODE_ACCEPT_MOVING_WRITE_BUFFER = 4,
+    SSL_OP_NO_SSLv2       = 8,
+
+    SSL_R_SSL_HANDSHAKE_FAILURE           = 101,
+    SSL_R_TLSV1_ALERT_UNKNOWN_CA          = 102,
+    SSL_R_SSLV3_ALERT_CERTIFICATE_UNKNOWN = 103,
+    SSL_R_SSLV3_ALERT_BAD_CERTIFICATE     = 104,
+
+    PEM_BUFSIZE = 1024
+};
+
+
+#ifndef NO_PSK
+    typedef unsigned int (*psk_client_callback)(WOLFSSL*, const char*, char*,
+                                    unsigned int, unsigned char*, unsigned int);
+    WOLFSSL_API void wolfSSL_CTX_set_psk_client_callback(WOLFSSL_CTX*,
+                                                    psk_client_callback);
+    WOLFSSL_API void wolfSSL_set_psk_client_callback(WOLFSSL*,psk_client_callback);
+
+    WOLFSSL_API const char* wolfSSL_get_psk_identity_hint(const WOLFSSL*);
+    WOLFSSL_API const char* wolfSSL_get_psk_identity(const WOLFSSL*);
+
+    WOLFSSL_API int wolfSSL_CTX_use_psk_identity_hint(WOLFSSL_CTX*, const char*);
+    WOLFSSL_API int wolfSSL_use_psk_identity_hint(WOLFSSL*, const char*);
+
+    typedef unsigned int (*psk_server_callback)(WOLFSSL*, const char*,
+                          unsigned char*, unsigned int);
+    WOLFSSL_API void wolfSSL_CTX_set_psk_server_callback(WOLFSSL_CTX*,
+                                                    psk_server_callback);
+    WOLFSSL_API void wolfSSL_set_psk_server_callback(WOLFSSL*,psk_server_callback);
+
+    #define PSK_TYPES_DEFINED
+#endif /* NO_PSK */
+
+
+#ifdef HAVE_ANON
+    WOLFSSL_API int wolfSSL_CTX_allow_anon_cipher(WOLFSSL_CTX*);
+#endif /* HAVE_ANON */
+
+
+/* extra begins */
+
+enum {  /* ERR Constants */
+    ERR_TXT_STRING = 1
+};
+
+WOLFSSL_API unsigned long wolfSSL_ERR_get_error_line_data(const char**, int*,
+                                                 const char**, int *);
+
+WOLFSSL_API unsigned long wolfSSL_ERR_get_error(void);
+WOLFSSL_API void          wolfSSL_ERR_clear_error(void);
+
+
+WOLFSSL_API int  wolfSSL_RAND_status(void);
+WOLFSSL_API int  wolfSSL_RAND_bytes(unsigned char* buf, int num);
+WOLFSSL_API WOLFSSL_METHOD *wolfSSLv23_server_method(void);
+WOLFSSL_API long wolfSSL_CTX_set_options(WOLFSSL_CTX*, long);
+#ifndef NO_CERTS
+  WOLFSSL_API int  wolfSSL_CTX_check_private_key(WOLFSSL_CTX*);
+#endif /* !NO_CERTS */
+
+WOLFSSL_API void wolfSSL_ERR_free_strings(void);
+WOLFSSL_API void wolfSSL_ERR_remove_state(unsigned long);
+WOLFSSL_API void wolfSSL_EVP_cleanup(void);
+WOLFSSL_API int  wolfSSL_clear(WOLFSSL* ssl);
+
+WOLFSSL_API void wolfSSL_cleanup_all_ex_data(void);
+WOLFSSL_API long wolfSSL_CTX_set_mode(WOLFSSL_CTX* ctx, long mode);
+WOLFSSL_API long wolfSSL_CTX_get_mode(WOLFSSL_CTX* ctx);
+WOLFSSL_API void wolfSSL_CTX_set_default_read_ahead(WOLFSSL_CTX* ctx, int m);
+WOLFSSL_API long wolfSSL_SSL_get_mode(WOLFSSL* ssl);
+
+WOLFSSL_API long wolfSSL_CTX_sess_set_cache_size(WOLFSSL_CTX*, long);
+
+WOLFSSL_API int  wolfSSL_CTX_set_default_verify_paths(WOLFSSL_CTX*);
+WOLFSSL_API int  wolfSSL_CTX_set_session_id_context(WOLFSSL_CTX*,
+                                            const unsigned char*, unsigned int);
+WOLFSSL_API WOLFSSL_X509* wolfSSL_get_peer_certificate(WOLFSSL* ssl);
+
+WOLFSSL_API int wolfSSL_want_read(WOLFSSL*);
+WOLFSSL_API int wolfSSL_want_write(WOLFSSL*);
+
+WOLFSSL_API int wolfSSL_BIO_printf(WOLFSSL_BIO*, const char*, ...);
+WOLFSSL_API int wolfSSL_ASN1_UTCTIME_print(WOLFSSL_BIO*,
+                                         const WOLFSSL_ASN1_UTCTIME*);
+WOLFSSL_API int   wolfSSL_sk_num(WOLFSSL_X509_REVOKED*);
+WOLFSSL_API void* wolfSSL_sk_value(WOLFSSL_X509_REVOKED*, int);
+
+/* stunnel 4.28 needs */
+WOLFSSL_API void* wolfSSL_CTX_get_ex_data(const WOLFSSL_CTX*, int);
+WOLFSSL_API int   wolfSSL_CTX_set_ex_data(WOLFSSL_CTX*, int, void*);
+WOLFSSL_API void  wolfSSL_CTX_sess_set_get_cb(WOLFSSL_CTX*,
+                       WOLFSSL_SESSION*(*f)(WOLFSSL*, unsigned char*, int, int*));
+WOLFSSL_API void  wolfSSL_CTX_sess_set_new_cb(WOLFSSL_CTX*,
+                                            int (*f)(WOLFSSL*, WOLFSSL_SESSION*));
+WOLFSSL_API void  wolfSSL_CTX_sess_set_remove_cb(WOLFSSL_CTX*,
+                                       void (*f)(WOLFSSL_CTX*, WOLFSSL_SESSION*));
+
+WOLFSSL_API int          wolfSSL_i2d_SSL_SESSION(WOLFSSL_SESSION*,unsigned char**);
+WOLFSSL_API WOLFSSL_SESSION* wolfSSL_d2i_SSL_SESSION(WOLFSSL_SESSION**,
+                                                   const unsigned char**, long);
+
+WOLFSSL_API long wolfSSL_SESSION_get_timeout(const WOLFSSL_SESSION*);
+WOLFSSL_API long wolfSSL_SESSION_get_time(const WOLFSSL_SESSION*);
+WOLFSSL_API int  wolfSSL_CTX_get_ex_new_index(long, void*, void*, void*, void*);
+
+/* extra ends */
+
+
+/* wolfSSL extensions */
+
+/* call before SSL_connect, if verifying will add name check to
+   date check and signature check */
+WOLFSSL_API int wolfSSL_check_domain_name(WOLFSSL* ssl, const char* dn);
+
+/* need to call once to load library (session cache) */
+WOLFSSL_API int wolfSSL_Init(void);
+/* call when done to cleanup/free session cache mutex / resources  */
+WOLFSSL_API int wolfSSL_Cleanup(void);
+
+/* which library version do we have */
+WOLFSSL_API const char* wolfSSL_lib_version(void);
+/* which library version do we have in hex */
+WOLFSSL_API unsigned int wolfSSL_lib_version_hex(void);
+
+/* turn logging on, only if compiled in */
+WOLFSSL_API int  wolfSSL_Debugging_ON(void);
+/* turn logging off */
+WOLFSSL_API void wolfSSL_Debugging_OFF(void);
+
+/* do accept or connect depedning on side */
+WOLFSSL_API int wolfSSL_negotiate(WOLFSSL* ssl);
+/* turn on wolfSSL data compression */
+WOLFSSL_API int wolfSSL_set_compression(WOLFSSL* ssl);
+
+WOLFSSL_API int wolfSSL_set_timeout(WOLFSSL*, unsigned int);
+WOLFSSL_API int wolfSSL_CTX_set_timeout(WOLFSSL_CTX*, unsigned int);
+
+/* get wolfSSL peer X509_CHAIN */
+WOLFSSL_API WOLFSSL_X509_CHAIN* wolfSSL_get_peer_chain(WOLFSSL* ssl);
+/* peer chain count */
+WOLFSSL_API int  wolfSSL_get_chain_count(WOLFSSL_X509_CHAIN* chain);
+/* index cert length */
+WOLFSSL_API int  wolfSSL_get_chain_length(WOLFSSL_X509_CHAIN*, int idx);
+/* index cert */
+WOLFSSL_API unsigned char* wolfSSL_get_chain_cert(WOLFSSL_X509_CHAIN*, int idx);
+/* index cert in X509 */
+WOLFSSL_API WOLFSSL_X509* wolfSSL_get_chain_X509(WOLFSSL_X509_CHAIN*, int idx);
+/* free X509 */
+WOLFSSL_API void wolfSSL_FreeX509(WOLFSSL_X509*);
+/* get index cert in PEM */
+WOLFSSL_API int  wolfSSL_get_chain_cert_pem(WOLFSSL_X509_CHAIN*, int idx,
+                                unsigned char* buffer, int inLen, int* outLen);
+WOLFSSL_API const unsigned char* wolfSSL_get_sessionID(const WOLFSSL_SESSION* s);
+WOLFSSL_API int  wolfSSL_X509_get_serial_number(WOLFSSL_X509*,unsigned char*,int*);
+WOLFSSL_API char*  wolfSSL_X509_get_subjectCN(WOLFSSL_X509*);
+WOLFSSL_API const unsigned char* wolfSSL_X509_get_der(WOLFSSL_X509*, int*);
+WOLFSSL_API const unsigned char* wolfSSL_X509_notBefore(WOLFSSL_X509*);
+WOLFSSL_API const unsigned char* wolfSSL_X509_notAfter(WOLFSSL_X509*);
+WOLFSSL_API int wolfSSL_X509_version(WOLFSSL_X509*);
+
+WOLFSSL_API int wolfSSL_cmp_peer_cert_to_file(WOLFSSL*, const char*);
+
+WOLFSSL_API char* wolfSSL_X509_get_next_altname(WOLFSSL_X509*);
+
+WOLFSSL_API WOLFSSL_X509*
+    wolfSSL_X509_d2i(WOLFSSL_X509** x509, const unsigned char* in, int len);
+#ifndef NO_FILESYSTEM
+    #ifndef NO_STDIO_FILESYSTEM
+    WOLFSSL_API WOLFSSL_X509*
+        wolfSSL_X509_d2i_fp(WOLFSSL_X509** x509, FILE* file);
+    #endif
+WOLFSSL_API WOLFSSL_X509*
+    wolfSSL_X509_load_certificate_file(const char* fname, int format);
+#endif
+
+#ifdef WOLFSSL_SEP
+    WOLFSSL_API unsigned char*
+           wolfSSL_X509_get_device_type(WOLFSSL_X509*, unsigned char*, int*);
+    WOLFSSL_API unsigned char*
+           wolfSSL_X509_get_hw_type(WOLFSSL_X509*, unsigned char*, int*);
+    WOLFSSL_API unsigned char*
+           wolfSSL_X509_get_hw_serial_number(WOLFSSL_X509*, unsigned char*, int*);
+#endif
+
+/* connect enough to get peer cert */
+WOLFSSL_API int  wolfSSL_connect_cert(WOLFSSL* ssl);
+
+#ifndef NO_DH
+/* server Diffie-Hellman parameters */
+WOLFSSL_API int  wolfSSL_SetTmpDH(WOLFSSL*, const unsigned char* p, int pSz,
+                                const unsigned char* g, int gSz);
+WOLFSSL_API int  wolfSSL_SetTmpDH_buffer(WOLFSSL*, const unsigned char* b, long sz,
+                                       int format);
+#ifndef NO_FILESYSTEM
+    WOLFSSL_API int  wolfSSL_SetTmpDH_file(WOLFSSL*, const char* f, int format);
+#endif
+
+/* server ctx Diffie-Hellman parameters */
+WOLFSSL_API int  wolfSSL_CTX_SetTmpDH(WOLFSSL_CTX*, const unsigned char* p,
+                                    int pSz, const unsigned char* g, int gSz);
+WOLFSSL_API int  wolfSSL_CTX_SetTmpDH_buffer(WOLFSSL_CTX*, const unsigned char* b,
+                                           long sz, int format);
+
+#ifndef NO_FILESYSTEM
+    WOLFSSL_API int  wolfSSL_CTX_SetTmpDH_file(WOLFSSL_CTX*, const char* f,
+                                             int format);
+#endif
+
+WOLFSSL_API int wolfSSL_CTX_SetMinDhKey_Sz(WOLFSSL_CTX*, unsigned short);
+WOLFSSL_API int wolfSSL_SetMinDhKey_Sz(WOLFSSL*, unsigned short);
+WOLFSSL_API int wolfSSL_GetDhKey_Sz(WOLFSSL*);
+#endif /* NO_DH */
+
+WOLFSSL_API int  wolfSSL_SetTmpEC_DHE_Sz(WOLFSSL*, unsigned short);
+WOLFSSL_API int  wolfSSL_CTX_SetTmpEC_DHE_Sz(WOLFSSL_CTX*, unsigned short);
+
+/* keyblock size in bytes or -1 */
+/* need to call wolfSSL_KeepArrays before handshake to save keys */
+WOLFSSL_API int wolfSSL_get_keyblock_size(WOLFSSL*);
+WOLFSSL_API int wolfSSL_get_keys(WOLFSSL*,unsigned char** ms, unsigned int* msLen,
+                                       unsigned char** sr, unsigned int* srLen,
+                                       unsigned char** cr, unsigned int* crLen);
+
+/* Computes EAP-TLS and EAP-TTLS keying material from the master_secret. */
+WOLFSSL_API int wolfSSL_make_eap_keys(WOLFSSL*, void* key, unsigned int len,
+                                                             const char* label);
+
+
+#ifndef _WIN32
+    #ifndef NO_WRITEV
+        #ifdef __PPU
+            #include 
+            #include 
+        #elif !defined(WOLFSSL_MDK_ARM) && !defined(WOLFSSL_IAR_ARM) && !defined(WOLFSSL_PICOTCP)
+            #include 
+        #endif
+        /* allow writev style writing */
+        WOLFSSL_API int wolfSSL_writev(WOLFSSL* ssl, const struct iovec* iov,
+                                     int iovcnt);
+    #endif
+#endif
+
+
+#ifndef NO_CERTS
+    /* SSL_CTX versions */
+    WOLFSSL_API int wolfSSL_CTX_UnloadCAs(WOLFSSL_CTX*);
+    WOLFSSL_API int wolfSSL_CTX_load_verify_buffer(WOLFSSL_CTX*,
+                                               const unsigned char*, long, int);
+    WOLFSSL_API int wolfSSL_CTX_use_certificate_buffer(WOLFSSL_CTX*,
+                                               const unsigned char*, long, int);
+    WOLFSSL_API int wolfSSL_CTX_use_PrivateKey_buffer(WOLFSSL_CTX*,
+                                               const unsigned char*, long, int);
+    WOLFSSL_API int wolfSSL_CTX_use_certificate_chain_buffer(WOLFSSL_CTX*,
+                                                    const unsigned char*, long);
+
+    /* SSL versions */
+    WOLFSSL_API int wolfSSL_use_certificate_buffer(WOLFSSL*, const unsigned char*,
+                                               long, int);
+    WOLFSSL_API int wolfSSL_use_PrivateKey_buffer(WOLFSSL*, const unsigned char*,
+                                               long, int);
+    WOLFSSL_API int wolfSSL_use_certificate_chain_buffer(WOLFSSL*,
+                                               const unsigned char*, long);
+    WOLFSSL_API int wolfSSL_UnloadCertsKeys(WOLFSSL*);
+#endif
+
+WOLFSSL_API int wolfSSL_CTX_set_group_messages(WOLFSSL_CTX*);
+WOLFSSL_API int wolfSSL_set_group_messages(WOLFSSL*);
+
+/* I/O callbacks */
+typedef int (*CallbackIORecv)(WOLFSSL *ssl, char *buf, int sz, void *ctx);
+typedef int (*CallbackIOSend)(WOLFSSL *ssl, char *buf, int sz, void *ctx);
+
+#ifdef HAVE_FUZZER
+enum fuzzer_type {
+    FUZZ_HMAC      = 0,
+    FUZZ_ENCRYPT   = 1,
+    FUZZ_SIGNATURE = 2,
+    FUZZ_HASH      = 3,
+    FUZZ_HEAD      = 4
+};
+
+typedef int (*CallbackFuzzer)(WOLFSSL* ssl, const unsigned char* buf, int sz,
+        int type, void* fuzzCtx);
+
+WOLFSSL_API void wolfSSL_SetFuzzerCb(WOLFSSL* ssl, CallbackFuzzer cbf, void* fCtx);
+#endif
+
+WOLFSSL_API void wolfSSL_SetIORecv(WOLFSSL_CTX*, CallbackIORecv);
+WOLFSSL_API void wolfSSL_SetIOSend(WOLFSSL_CTX*, CallbackIOSend);
+
+WOLFSSL_API void wolfSSL_SetIOReadCtx( WOLFSSL* ssl, void *ctx);
+WOLFSSL_API void wolfSSL_SetIOWriteCtx(WOLFSSL* ssl, void *ctx);
+
+WOLFSSL_API void* wolfSSL_GetIOReadCtx( WOLFSSL* ssl);
+WOLFSSL_API void* wolfSSL_GetIOWriteCtx(WOLFSSL* ssl);
+
+WOLFSSL_API void wolfSSL_SetIOReadFlags( WOLFSSL* ssl, int flags);
+WOLFSSL_API void wolfSSL_SetIOWriteFlags(WOLFSSL* ssl, int flags);
+
+
+#ifndef WOLFSSL_USER_IO
+    /* default IO callbacks */
+    WOLFSSL_API int EmbedReceive(WOLFSSL* ssl, char* buf, int sz, void* ctx);
+    WOLFSSL_API int EmbedSend(WOLFSSL* ssl, char* buf, int sz, void* ctx);
+
+    #ifdef HAVE_OCSP
+        WOLFSSL_API int EmbedOcspLookup(void*, const char*, int, unsigned char*,
+                                       int, unsigned char**);
+        WOLFSSL_API void EmbedOcspRespFree(void*, unsigned char*);
+    #endif
+
+    #ifdef WOLFSSL_DTLS
+        WOLFSSL_API int EmbedReceiveFrom(WOLFSSL* ssl, char* buf, int sz, void*);
+        WOLFSSL_API int EmbedSendTo(WOLFSSL* ssl, char* buf, int sz, void* ctx);
+        WOLFSSL_API int EmbedGenerateCookie(WOLFSSL* ssl, unsigned char* buf,
+                                           int sz, void*);
+    #endif /* WOLFSSL_DTLS */
+#endif /* WOLFSSL_USER_IO */
+
+
+#ifdef HAVE_NETX
+    WOLFSSL_API void wolfSSL_SetIO_NetX(WOLFSSL* ssl, NX_TCP_SOCKET* nxsocket,
+                                      ULONG waitoption);
+#endif
+
+typedef int (*CallbackGenCookie)(WOLFSSL* ssl, unsigned char* buf, int sz,
+                                 void* ctx);
+WOLFSSL_API void  wolfSSL_CTX_SetGenCookie(WOLFSSL_CTX*, CallbackGenCookie);
+WOLFSSL_API void  wolfSSL_SetCookieCtx(WOLFSSL* ssl, void *ctx);
+WOLFSSL_API void* wolfSSL_GetCookieCtx(WOLFSSL* ssl);
+
+
+/* I/O Callback default errors */
+enum IOerrors {
+    WOLFSSL_CBIO_ERR_GENERAL    = -1,     /* general unexpected err */
+    WOLFSSL_CBIO_ERR_WANT_READ  = -2,     /* need to call read  again */
+    WOLFSSL_CBIO_ERR_WANT_WRITE = -2,     /* need to call write again */
+    WOLFSSL_CBIO_ERR_CONN_RST   = -3,     /* connection reset */
+    WOLFSSL_CBIO_ERR_ISR        = -4,     /* interrupt */
+    WOLFSSL_CBIO_ERR_CONN_CLOSE = -5,     /* connection closed or epipe */
+    WOLFSSL_CBIO_ERR_TIMEOUT    = -6      /* socket timeout */
+};
+
+
+/* CA cache callbacks */
+enum {
+    WOLFSSL_SSLV3    = 0,
+    WOLFSSL_TLSV1    = 1,
+    WOLFSSL_TLSV1_1  = 2,
+    WOLFSSL_TLSV1_2  = 3,
+    WOLFSSL_USER_CA  = 1,          /* user added as trusted */
+    WOLFSSL_CHAIN_CA = 2           /* added to cache from trusted chain */
+};
+
+WOLFSSL_API int wolfSSL_CTX_SetMinVersion(WOLFSSL_CTX* ctx, int version);
+WOLFSSL_API int wolfSSL_SetMinVersion(WOLFSSL* ssl, int version);
+WOLFSSL_API int wolfSSL_GetObjectSize(void);  /* object size based on build */
+WOLFSSL_API int wolfSSL_SetVersion(WOLFSSL* ssl, int version);
+WOLFSSL_API int wolfSSL_KeyPemToDer(const unsigned char*, int sz, unsigned char*,
+                                  int, const char*);
+WOLFSSL_API int wolfSSL_CertPemToDer(const unsigned char*, int sz, unsigned char*,
+                                   int, int);
+
+typedef void (*CallbackCACache)(unsigned char* der, int sz, int type);
+typedef void (*CbMissingCRL)(const char* url);
+typedef int  (*CbOCSPIO)(void*, const char*, int,
+                                         unsigned char*, int, unsigned char**);
+typedef void (*CbOCSPRespFree)(void*,unsigned char*);
+
+/* User Atomic Record Layer CallBacks */
+typedef int (*CallbackMacEncrypt)(WOLFSSL* ssl, unsigned char* macOut,
+       const unsigned char* macIn, unsigned int macInSz, int macContent,
+       int macVerify, unsigned char* encOut, const unsigned char* encIn,
+       unsigned int encSz, void* ctx);
+WOLFSSL_API void  wolfSSL_CTX_SetMacEncryptCb(WOLFSSL_CTX*, CallbackMacEncrypt);
+WOLFSSL_API void  wolfSSL_SetMacEncryptCtx(WOLFSSL* ssl, void *ctx);
+WOLFSSL_API void* wolfSSL_GetMacEncryptCtx(WOLFSSL* ssl);
+
+typedef int (*CallbackDecryptVerify)(WOLFSSL* ssl,
+       unsigned char* decOut, const unsigned char* decIn,
+       unsigned int decSz, int content, int verify, unsigned int* padSz,
+       void* ctx);
+WOLFSSL_API void  wolfSSL_CTX_SetDecryptVerifyCb(WOLFSSL_CTX*,
+                                               CallbackDecryptVerify);
+WOLFSSL_API void  wolfSSL_SetDecryptVerifyCtx(WOLFSSL* ssl, void *ctx);
+WOLFSSL_API void* wolfSSL_GetDecryptVerifyCtx(WOLFSSL* ssl);
+
+WOLFSSL_API const unsigned char* wolfSSL_GetMacSecret(WOLFSSL*, int);
+WOLFSSL_API const unsigned char* wolfSSL_GetClientWriteKey(WOLFSSL*);
+WOLFSSL_API const unsigned char* wolfSSL_GetClientWriteIV(WOLFSSL*);
+WOLFSSL_API const unsigned char* wolfSSL_GetServerWriteKey(WOLFSSL*);
+WOLFSSL_API const unsigned char* wolfSSL_GetServerWriteIV(WOLFSSL*);
+WOLFSSL_API int                  wolfSSL_GetKeySize(WOLFSSL*);
+WOLFSSL_API int                  wolfSSL_GetIVSize(WOLFSSL*);
+WOLFSSL_API int                  wolfSSL_GetSide(WOLFSSL*);
+WOLFSSL_API int                  wolfSSL_IsTLSv1_1(WOLFSSL*);
+WOLFSSL_API int                  wolfSSL_GetBulkCipher(WOLFSSL*);
+WOLFSSL_API int                  wolfSSL_GetCipherBlockSize(WOLFSSL*);
+WOLFSSL_API int                  wolfSSL_GetAeadMacSize(WOLFSSL*);
+WOLFSSL_API int                  wolfSSL_GetHmacSize(WOLFSSL*);
+WOLFSSL_API int                  wolfSSL_GetHmacType(WOLFSSL*);
+WOLFSSL_API int                  wolfSSL_GetCipherType(WOLFSSL*);
+WOLFSSL_API int                  wolfSSL_SetTlsHmacInner(WOLFSSL*, unsigned char*,
+                                                       unsigned int, int, int);
+
+/* Atomic User Needs */
+enum {
+    WOLFSSL_SERVER_END = 0,
+    WOLFSSL_CLIENT_END = 1,
+    WOLFSSL_BLOCK_TYPE = 2,
+    WOLFSSL_STREAM_TYPE = 3,
+    WOLFSSL_AEAD_TYPE = 4,
+    WOLFSSL_TLS_HMAC_INNER_SZ = 13      /* SEQ_SZ + ENUM + VERSION_SZ + LEN_SZ */
+};
+
+/* for GetBulkCipher and internal use */
+enum BulkCipherAlgorithm {
+    wolfssl_cipher_null,
+    wolfssl_rc4,
+    wolfssl_rc2,
+    wolfssl_des,
+    wolfssl_triple_des,             /* leading 3 (3des) not valid identifier */
+    wolfssl_des40,
+    wolfssl_idea,
+    wolfssl_aes,
+    wolfssl_aes_gcm,
+    wolfssl_aes_ccm,
+    wolfssl_chacha,
+    wolfssl_camellia,
+    wolfssl_hc128,                  /* wolfSSL extensions */
+    wolfssl_rabbit
+};
+
+
+/* for KDF TLS 1.2 mac types */
+enum KDF_MacAlgorithm {
+    wolfssl_sha256 = 4,     /* needs to match internal MACAlgorithm */
+    wolfssl_sha384,
+    wolfssl_sha512
+};
+
+
+/* Public Key Callback support */
+typedef int (*CallbackEccSign)(WOLFSSL* ssl,
+       const unsigned char* in, unsigned int inSz,
+       unsigned char* out, unsigned int* outSz,
+       const unsigned char* keyDer, unsigned int keySz,
+       void* ctx);
+WOLFSSL_API void  wolfSSL_CTX_SetEccSignCb(WOLFSSL_CTX*, CallbackEccSign);
+WOLFSSL_API void  wolfSSL_SetEccSignCtx(WOLFSSL* ssl, void *ctx);
+WOLFSSL_API void* wolfSSL_GetEccSignCtx(WOLFSSL* ssl);
+
+typedef int (*CallbackEccVerify)(WOLFSSL* ssl,
+       const unsigned char* sig, unsigned int sigSz,
+       const unsigned char* hash, unsigned int hashSz,
+       const unsigned char* keyDer, unsigned int keySz,
+       int* result, void* ctx);
+WOLFSSL_API void  wolfSSL_CTX_SetEccVerifyCb(WOLFSSL_CTX*, CallbackEccVerify);
+WOLFSSL_API void  wolfSSL_SetEccVerifyCtx(WOLFSSL* ssl, void *ctx);
+WOLFSSL_API void* wolfSSL_GetEccVerifyCtx(WOLFSSL* ssl);
+
+typedef int (*CallbackRsaSign)(WOLFSSL* ssl,
+       const unsigned char* in, unsigned int inSz,
+       unsigned char* out, unsigned int* outSz,
+       const unsigned char* keyDer, unsigned int keySz,
+       void* ctx);
+WOLFSSL_API void  wolfSSL_CTX_SetRsaSignCb(WOLFSSL_CTX*, CallbackRsaSign);
+WOLFSSL_API void  wolfSSL_SetRsaSignCtx(WOLFSSL* ssl, void *ctx);
+WOLFSSL_API void* wolfSSL_GetRsaSignCtx(WOLFSSL* ssl);
+
+typedef int (*CallbackRsaVerify)(WOLFSSL* ssl,
+       unsigned char* sig, unsigned int sigSz,
+       unsigned char** out,
+       const unsigned char* keyDer, unsigned int keySz,
+       void* ctx);
+WOLFSSL_API void  wolfSSL_CTX_SetRsaVerifyCb(WOLFSSL_CTX*, CallbackRsaVerify);
+WOLFSSL_API void  wolfSSL_SetRsaVerifyCtx(WOLFSSL* ssl, void *ctx);
+WOLFSSL_API void* wolfSSL_GetRsaVerifyCtx(WOLFSSL* ssl);
+
+/* RSA Public Encrypt cb */
+typedef int (*CallbackRsaEnc)(WOLFSSL* ssl,
+       const unsigned char* in, unsigned int inSz,
+       unsigned char* out, unsigned int* outSz,
+       const unsigned char* keyDer, unsigned int keySz,
+       void* ctx);
+WOLFSSL_API void  wolfSSL_CTX_SetRsaEncCb(WOLFSSL_CTX*, CallbackRsaEnc);
+WOLFSSL_API void  wolfSSL_SetRsaEncCtx(WOLFSSL* ssl, void *ctx);
+WOLFSSL_API void* wolfSSL_GetRsaEncCtx(WOLFSSL* ssl);
+
+/* RSA Private Decrypt cb */
+typedef int (*CallbackRsaDec)(WOLFSSL* ssl,
+       unsigned char* in, unsigned int inSz,
+       unsigned char** out,
+       const unsigned char* keyDer, unsigned int keySz,
+       void* ctx);
+WOLFSSL_API void  wolfSSL_CTX_SetRsaDecCb(WOLFSSL_CTX*, CallbackRsaDec);
+WOLFSSL_API void  wolfSSL_SetRsaDecCtx(WOLFSSL* ssl, void *ctx);
+WOLFSSL_API void* wolfSSL_GetRsaDecCtx(WOLFSSL* ssl);
+
+
+#ifndef NO_CERTS
+	WOLFSSL_API void wolfSSL_CTX_SetCACb(WOLFSSL_CTX*, CallbackCACache);
+
+    WOLFSSL_API WOLFSSL_CERT_MANAGER* wolfSSL_CertManagerNew(void);
+    WOLFSSL_API void wolfSSL_CertManagerFree(WOLFSSL_CERT_MANAGER*);
+
+    WOLFSSL_API int wolfSSL_CertManagerLoadCA(WOLFSSL_CERT_MANAGER*, const char* f,
+                                                                 const char* d);
+    WOLFSSL_API int wolfSSL_CertManagerUnloadCAs(WOLFSSL_CERT_MANAGER* cm);
+    WOLFSSL_API int wolfSSL_CertManagerVerify(WOLFSSL_CERT_MANAGER*, const char* f,
+                                                                    int format);
+    WOLFSSL_API int wolfSSL_CertManagerVerifyBuffer(WOLFSSL_CERT_MANAGER* cm,
+                                const unsigned char* buff, long sz, int format);
+    WOLFSSL_API int wolfSSL_CertManagerCheckCRL(WOLFSSL_CERT_MANAGER*,
+                                                        unsigned char*, int sz);
+    WOLFSSL_API int wolfSSL_CertManagerEnableCRL(WOLFSSL_CERT_MANAGER*,
+                                                                   int options);
+    WOLFSSL_API int wolfSSL_CertManagerDisableCRL(WOLFSSL_CERT_MANAGER*);
+    WOLFSSL_API int wolfSSL_CertManagerLoadCRL(WOLFSSL_CERT_MANAGER*, const char*,
+                                                                      int, int);
+    WOLFSSL_API int wolfSSL_CertManagerSetCRL_Cb(WOLFSSL_CERT_MANAGER*,
+                                                                  CbMissingCRL);
+    WOLFSSL_API int wolfSSL_CertManagerCheckOCSP(WOLFSSL_CERT_MANAGER*,
+                                                        unsigned char*, int sz);
+    WOLFSSL_API int wolfSSL_CertManagerEnableOCSP(WOLFSSL_CERT_MANAGER*,
+                                                                   int options);
+    WOLFSSL_API int wolfSSL_CertManagerDisableOCSP(WOLFSSL_CERT_MANAGER*);
+    WOLFSSL_API int wolfSSL_CertManagerSetOCSPOverrideURL(WOLFSSL_CERT_MANAGER*,
+                                                                   const char*);
+    WOLFSSL_API int wolfSSL_CertManagerSetOCSP_Cb(WOLFSSL_CERT_MANAGER*,
+                                               CbOCSPIO, CbOCSPRespFree, void*);
+
+    WOLFSSL_API int wolfSSL_EnableCRL(WOLFSSL* ssl, int options);
+    WOLFSSL_API int wolfSSL_DisableCRL(WOLFSSL* ssl);
+    WOLFSSL_API int wolfSSL_LoadCRL(WOLFSSL*, const char*, int, int);
+    WOLFSSL_API int wolfSSL_SetCRL_Cb(WOLFSSL*, CbMissingCRL);
+    WOLFSSL_API int wolfSSL_EnableOCSP(WOLFSSL*, int options);
+    WOLFSSL_API int wolfSSL_DisableOCSP(WOLFSSL*);
+    WOLFSSL_API int wolfSSL_SetOCSP_OverrideURL(WOLFSSL*, const char*);
+    WOLFSSL_API int wolfSSL_SetOCSP_Cb(WOLFSSL*, CbOCSPIO, CbOCSPRespFree, void*);
+
+    WOLFSSL_API int wolfSSL_CTX_EnableCRL(WOLFSSL_CTX* ctx, int options);
+    WOLFSSL_API int wolfSSL_CTX_DisableCRL(WOLFSSL_CTX* ctx);
+    WOLFSSL_API int wolfSSL_CTX_LoadCRL(WOLFSSL_CTX*, const char*, int, int);
+    WOLFSSL_API int wolfSSL_CTX_SetCRL_Cb(WOLFSSL_CTX*, CbMissingCRL);
+    WOLFSSL_API int wolfSSL_CTX_EnableOCSP(WOLFSSL_CTX*, int options);
+    WOLFSSL_API int wolfSSL_CTX_DisableOCSP(WOLFSSL_CTX*);
+    WOLFSSL_API int wolfSSL_CTX_SetOCSP_OverrideURL(WOLFSSL_CTX*, const char*);
+    WOLFSSL_API int wolfSSL_CTX_SetOCSP_Cb(WOLFSSL_CTX*,
+                                               CbOCSPIO, CbOCSPRespFree, void*);
+#endif /* !NO_CERTS */
+
+/* end of handshake frees temporary arrays, if user needs for get_keys or
+   psk hints, call KeepArrays before handshake and then FreeArrays when done
+   if don't want to wait for object free */
+WOLFSSL_API void wolfSSL_KeepArrays(WOLFSSL*);
+WOLFSSL_API void wolfSSL_FreeArrays(WOLFSSL*);
+
+
+/* cavium additions */
+WOLFSSL_API int wolfSSL_UseCavium(WOLFSSL*, int devId);
+WOLFSSL_API int wolfSSL_CTX_UseCavium(WOLFSSL_CTX*, int devId);
+
+/* TLS Extensions */
+
+/* Server Name Indication */
+#ifdef HAVE_SNI
+
+/* SNI types */
+enum {
+    WOLFSSL_SNI_HOST_NAME = 0
+};
+
+WOLFSSL_API int wolfSSL_UseSNI(WOLFSSL* ssl, unsigned char type, const void* data,
+                                                           unsigned short size);
+WOLFSSL_API int wolfSSL_CTX_UseSNI(WOLFSSL_CTX* ctx, unsigned char type,
+                                         const void* data, unsigned short size);
+
+#ifndef NO_WOLFSSL_SERVER
+
+/* SNI options */
+enum {
+    WOLFSSL_SNI_CONTINUE_ON_MISMATCH = 0x01, /* do not abort on mismatch flag */
+    WOLFSSL_SNI_ANSWER_ON_MISMATCH   = 0x02  /* fake match on mismatch flag */
+};
+
+WOLFSSL_API void wolfSSL_SNI_SetOptions(WOLFSSL* ssl, unsigned char type,
+                                                         unsigned char options);
+WOLFSSL_API void wolfSSL_CTX_SNI_SetOptions(WOLFSSL_CTX* ctx, unsigned char type,
+                                                         unsigned char options);
+
+/* SNI status */
+enum {
+    WOLFSSL_SNI_NO_MATCH   = 0,
+    WOLFSSL_SNI_FAKE_MATCH = 1, /* if WOLFSSL_SNI_ANSWER_ON_MISMATCH is enabled */
+    WOLFSSL_SNI_REAL_MATCH = 2
+};
+
+WOLFSSL_API unsigned char wolfSSL_SNI_Status(WOLFSSL* ssl, unsigned char type);
+
+WOLFSSL_API unsigned short wolfSSL_SNI_GetRequest(WOLFSSL *ssl, unsigned char type,
+                                                                   void** data);
+WOLFSSL_API int wolfSSL_SNI_GetFromBuffer(
+                 const unsigned char* clientHello, unsigned int helloSz,
+                 unsigned char type, unsigned char* sni, unsigned int* inOutSz);
+
+#endif
+#endif
+
+/* Maximum Fragment Length */
+#ifdef HAVE_MAX_FRAGMENT
+
+/* Fragment lengths */
+enum {
+    WOLFSSL_MFL_2_9  = 1, /*  512 bytes */
+    WOLFSSL_MFL_2_10 = 2, /* 1024 bytes */
+    WOLFSSL_MFL_2_11 = 3, /* 2048 bytes */
+    WOLFSSL_MFL_2_12 = 4, /* 4096 bytes */
+    WOLFSSL_MFL_2_13 = 5  /* 8192 bytes *//* wolfSSL ONLY!!! */
+};
+
+#ifndef NO_WOLFSSL_CLIENT
+
+WOLFSSL_API int wolfSSL_UseMaxFragment(WOLFSSL* ssl, unsigned char mfl);
+WOLFSSL_API int wolfSSL_CTX_UseMaxFragment(WOLFSSL_CTX* ctx, unsigned char mfl);
+
+#endif
+#endif
+
+/* Truncated HMAC */
+#ifdef HAVE_TRUNCATED_HMAC
+#ifndef NO_WOLFSSL_CLIENT
+
+WOLFSSL_API int wolfSSL_UseTruncatedHMAC(WOLFSSL* ssl);
+WOLFSSL_API int wolfSSL_CTX_UseTruncatedHMAC(WOLFSSL_CTX* ctx);
+
+#endif
+#endif
+
+/* Elliptic Curves */
+enum {
+    WOLFSSL_ECC_SECP160R1 = 0x10,
+    WOLFSSL_ECC_SECP192R1 = 0x13,
+    WOLFSSL_ECC_SECP224R1 = 0x15,
+    WOLFSSL_ECC_SECP256R1 = 0x17,
+    WOLFSSL_ECC_SECP384R1 = 0x18,
+    WOLFSSL_ECC_SECP521R1 = 0x19
+};
+
+#ifdef HAVE_SUPPORTED_CURVES
+#ifndef NO_WOLFSSL_CLIENT
+
+WOLFSSL_API int wolfSSL_UseSupportedCurve(WOLFSSL* ssl, unsigned short name);
+WOLFSSL_API int wolfSSL_CTX_UseSupportedCurve(WOLFSSL_CTX* ctx,
+                                                           unsigned short name);
+
+#endif
+#endif
+
+/* Secure Renegotiation */
+#ifdef HAVE_SECURE_RENEGOTIATION
+
+WOLFSSL_API int wolfSSL_UseSecureRenegotiation(WOLFSSL* ssl);
+WOLFSSL_API int wolfSSL_Rehandshake(WOLFSSL* ssl);
+
+#endif
+
+/* Session Ticket */
+#ifdef HAVE_SESSION_TICKET
+
+#ifndef NO_WOLFSSL_CLIENT
+WOLFSSL_API int wolfSSL_UseSessionTicket(WOLFSSL* ssl);
+WOLFSSL_API int wolfSSL_CTX_UseSessionTicket(WOLFSSL_CTX* ctx);
+WOLFSSL_API int wolfSSL_get_SessionTicket(WOLFSSL*, unsigned char*, unsigned int*);
+WOLFSSL_API int wolfSSL_set_SessionTicket(WOLFSSL*, unsigned char*, unsigned int);
+typedef int (*CallbackSessionTicket)(WOLFSSL*, const unsigned char*, int, void*);
+WOLFSSL_API int wolfSSL_set_SessionTicket_cb(WOLFSSL*,
+                                                  CallbackSessionTicket, void*);
+#endif /* NO_WOLFSSL_CLIENT */
+
+#ifndef NO_WOLFSSL_SERVER
+
+#define WOLFSSL_TICKET_NAME_SZ 16
+#define WOLFSSL_TICKET_IV_SZ   16
+#define WOLFSSL_TICKET_MAC_SZ  32
+
+enum TicketEncRet {
+    WOLFSSL_TICKET_RET_FATAL  = -1,  /* fatal error, don't use ticket */
+    WOLFSSL_TICKET_RET_OK     =  0,  /* ok, use ticket */
+    WOLFSSL_TICKET_RET_REJECT,       /* don't use ticket, but not fatal */
+    WOLFSSL_TICKET_RET_CREATE        /* existing ticket ok and create new one */
+};
+
+typedef int (*SessionTicketEncCb)(WOLFSSL*,
+                                 unsigned char key_name[WOLFSSL_TICKET_NAME_SZ],
+                                 unsigned char iv[WOLFSSL_TICKET_IV_SZ],
+                                 unsigned char mac[WOLFSSL_TICKET_MAC_SZ],
+                                 int enc, unsigned char*, int, int*, void*);
+WOLFSSL_API int wolfSSL_CTX_set_TicketEncCb(WOLFSSL_CTX* ctx,
+                                            SessionTicketEncCb);
+WOLFSSL_API int wolfSSL_CTX_set_TicketHint(WOLFSSL_CTX* ctx, int);
+WOLFSSL_API int wolfSSL_CTX_set_TicketEncCtx(WOLFSSL_CTX* ctx, void*);
+
+#endif /* NO_WOLFSSL_SERVER */
+
+#endif /* HAVE_SESSION_TICKET */
+
+#define WOLFSSL_CRL_MONITOR   0x01   /* monitor this dir flag */
+#define WOLFSSL_CRL_START_MON 0x02   /* start monitoring flag */
+
+
+/* notify user the hanshake is done */
+typedef int (*HandShakeDoneCb)(WOLFSSL*, void*);
+WOLFSSL_API int wolfSSL_SetHsDoneCb(WOLFSSL*, HandShakeDoneCb, void*);
+
+
+WOLFSSL_API int wolfSSL_PrintSessionStats(void);
+WOLFSSL_API int wolfSSL_get_session_stats(unsigned int* active,
+                                          unsigned int* total,
+                                          unsigned int* peak,
+                                          unsigned int* maxSessions);
+/* External facing KDF */
+WOLFSSL_API
+int wolfSSL_MakeTlsMasterSecret(unsigned char* ms, unsigned int msLen,
+                               const unsigned char* pms, unsigned int pmsLen,
+                               const unsigned char* cr, const unsigned char* sr,
+                               int tls1_2, int hash_type);
+
+WOLFSSL_API
+int wolfSSL_DeriveTlsKeys(unsigned char* key_data, unsigned int keyLen,
+                               const unsigned char* ms, unsigned int msLen,
+                               const unsigned char* sr, const unsigned char* cr,
+                               int tls1_2, int hash_type);
+
+#ifdef WOLFSSL_CALLBACKS
+
+/* used internally by wolfSSL while OpenSSL types aren't */
+#include 
+
+typedef int (*HandShakeCallBack)(HandShakeInfo*);
+typedef int (*TimeoutCallBack)(TimeoutInfo*);
+
+/* wolfSSL connect extension allowing HandShakeCallBack and/or TimeoutCallBack
+   for diagnostics */
+WOLFSSL_API int wolfSSL_connect_ex(WOLFSSL*, HandShakeCallBack, TimeoutCallBack,
+                                 Timeval);
+WOLFSSL_API int wolfSSL_accept_ex(WOLFSSL*, HandShakeCallBack, TimeoutCallBack,
+                                Timeval);
+
+#endif /* WOLFSSL_CALLBACKS */
+
+
+#ifdef WOLFSSL_HAVE_WOLFSCEP
+    WOLFSSL_API void wolfSSL_wolfSCEP(void);
+#endif /* WOLFSSL_HAVE_WOLFSCEP */
+
+#ifdef WOLFSSL_HAVE_CERT_SERVICE
+    WOLFSSL_API void wolfSSL_cert_service(void);
+#endif
+
+
+#ifdef __cplusplus
+    }  /* extern "C" */
+#endif
+
+
+#endif /* WOLFSSL_SSL_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/test.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/test.h
new file mode 100644
index 0000000..4c95d72
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/test.h
@@ -0,0 +1,1952 @@
+/* test.h */
+
+#ifndef wolfSSL_TEST_H
+#define wolfSSL_TEST_H
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifdef ATOMIC_USER
+    #include 
+    #include 
+    #include 
+#endif
+#ifdef HAVE_PK_CALLBACKS
+    #include 
+    #ifdef HAVE_ECC
+        #include 
+    #endif /* HAVE_ECC */
+#endif /*HAVE_PK_CALLBACKS */
+
+#ifdef USE_WINDOWS_API 
+    #include 
+    #include 
+    #ifdef TEST_IPV6            /* don't require newer SDK for IPV4 */
+        #include 
+        #include 
+    #endif
+    #define SOCKET_T SOCKET
+    #define SNPRINTF _snprintf
+#elif defined(WOLFSSL_MDK_ARM)
+    #include 
+#elif defined(WOLFSSL_TIRTOS)
+    #include 
+    #include 
+    #include 
+    #include 
+    #include 
+    #include 
+    struct hostent {
+    	char *h_name; /* official name of host */
+    	char **h_aliases; /* alias list */
+    	int h_addrtype; /* host address type */
+    	int h_length; /* length of address */
+    	char **h_addr_list; /* list of addresses from name server */
+    };
+    #define SOCKET_T int
+#else
+    #include 
+    #include 
+#ifndef WOLFSSL_LEANPSK
+    #include 
+    #include 
+    #include 
+    #include 
+    #include 
+    #include 
+    #include 
+    #include 
+    #include 
+    #include 
+    #ifdef TEST_IPV6
+        #include 
+    #endif
+#endif
+    #define SOCKET_T int
+    #ifndef SO_NOSIGPIPE
+        #include   /* ignore SIGPIPE */
+    #endif
+    #define SNPRINTF snprintf
+#endif /* USE_WINDOWS_API */
+
+#ifdef HAVE_CAVIUM
+    #include "cavium_sysdep.h"
+    #include "cavium_common.h"
+    #include "cavium_ioctl.h"
+#endif
+
+#ifdef _MSC_VER
+    /* disable conversion warning */
+    /* 4996 warning to use MS extensions e.g., strcpy_s instead of strncpy */
+    #pragma warning(disable:4244 4996)
+#endif
+
+
+#if defined(__MACH__) || defined(USE_WINDOWS_API)
+    #ifndef _SOCKLEN_T
+        typedef int socklen_t;
+    #endif
+#endif
+
+
+/* HPUX doesn't use socklent_t for third parameter to accept, unless
+   _XOPEN_SOURCE_EXTENDED is defined */
+#if !defined(__hpux__) && !defined(WOLFSSL_MDK_ARM) && !defined(WOLFSSL_IAR_ARM)
+    typedef socklen_t* ACCEPT_THIRD_T;
+#else
+    #if defined _XOPEN_SOURCE_EXTENDED
+        typedef socklen_t* ACCEPT_THIRD_T;
+    #else
+        typedef int*       ACCEPT_THIRD_T;
+    #endif
+#endif
+
+
+#ifdef USE_WINDOWS_API 
+    #define CloseSocket(s) closesocket(s)
+    #define StartTCP() { WSADATA wsd; WSAStartup(0x0002, &wsd); }
+#elif defined(WOLFSSL_MDK_ARM)
+    #define CloseSocket(s) closesocket(s)
+    #define StartTCP() 
+#else
+    #define CloseSocket(s) close(s)
+    #define StartTCP() 
+#endif
+
+
+#ifdef SINGLE_THREADED
+    typedef unsigned int  THREAD_RETURN;
+    typedef void*         THREAD_TYPE;
+    #define WOLFSSL_THREAD
+#else
+    #if defined(_POSIX_THREADS) && !defined(__MINGW32__)
+        typedef void*         THREAD_RETURN;
+        typedef pthread_t     THREAD_TYPE;
+        #define WOLFSSL_THREAD
+        #define INFINITE -1
+        #define WAIT_OBJECT_0 0L
+    #elif defined(WOLFSSL_MDK_ARM)
+        typedef unsigned int  THREAD_RETURN;
+        typedef int           THREAD_TYPE;
+        #define WOLFSSL_THREAD
+    #elif defined(WOLFSSL_TIRTOS)
+        typedef void          THREAD_RETURN;
+        typedef Task_Handle   THREAD_TYPE;
+        #define WOLFSSL_THREAD
+    #else
+        typedef unsigned int  THREAD_RETURN;
+        typedef intptr_t      THREAD_TYPE;
+        #define WOLFSSL_THREAD __stdcall
+    #endif
+#endif
+
+
+#ifdef TEST_IPV6
+    typedef struct sockaddr_in6 SOCKADDR_IN_T;
+    #define AF_INET_V    AF_INET6
+#else
+    typedef struct sockaddr_in  SOCKADDR_IN_T;
+    #define AF_INET_V    AF_INET
+#endif
+   
+
+#define SERVER_DEFAULT_VERSION 3
+#define SERVER_DTLS_DEFAULT_VERSION (-2)
+#define SERVER_INVALID_VERSION (-99)
+#define CLIENT_DEFAULT_VERSION 3
+#define CLIENT_DTLS_DEFAULT_VERSION (-2)
+#define CLIENT_INVALID_VERSION (-99)
+#if !defined(NO_FILESYSTEM) && defined(WOLFSSL_MAX_STRENGTH)
+    #define DEFAULT_MIN_DHKEY_BITS 2048
+#else
+    #define DEFAULT_MIN_DHKEY_BITS 1024
+#endif
+
+/* all certs relative to wolfSSL home directory now */
+#define caCert     "./certs/ca-cert.pem"
+#define eccCert    "./certs/server-ecc.pem"
+#define eccKey     "./certs/ecc-key.pem"
+#define svrCert    "./certs/server-cert.pem"
+#define svrKey     "./certs/server-key.pem"
+#define cliCert    "./certs/client-cert.pem"
+#define cliKey     "./certs/client-key.pem"
+#define ntruCert   "./certs/ntru-cert.pem"
+#define ntruKey    "./certs/ntru-key.raw"
+#define dhParam    "./certs/dh2048.pem"
+#define cliEccKey  "./certs/ecc-client-key.pem"
+#define cliEccCert "./certs/client-ecc-cert.pem"
+#define crlPemDir  "./certs/crl"
+
+typedef struct tcp_ready {
+    word16 ready;              /* predicate */
+    word16 port;
+#if defined(_POSIX_THREADS) && !defined(__MINGW32__)
+    pthread_mutex_t mutex;
+    pthread_cond_t  cond;
+#endif
+} tcp_ready;    
+
+
+void InitTcpReady(tcp_ready*);
+void FreeTcpReady(tcp_ready*);
+
+typedef WOLFSSL_METHOD* (*method_provider)(void);
+typedef void (*ctx_callback)(WOLFSSL_CTX* ctx);
+typedef void (*ssl_callback)(WOLFSSL* ssl);
+
+typedef struct callback_functions {
+    method_provider method;
+    ctx_callback ctx_ready;
+    ssl_callback ssl_ready;
+    ssl_callback on_result;
+} callback_functions;
+
+typedef struct func_args {
+    int    argc;
+    char** argv;
+    int    return_code;
+    tcp_ready* signal;
+    callback_functions *callbacks;
+} func_args;
+
+void wait_tcp_ready(func_args*);
+
+typedef THREAD_RETURN WOLFSSL_THREAD THREAD_FUNC(void*);
+
+void start_thread(THREAD_FUNC, func_args*, THREAD_TYPE*);
+void join_thread(THREAD_TYPE);
+
+/* wolfSSL */
+#ifndef TEST_IPV6
+    static const char* const wolfSSLIP   = "127.0.0.1";
+#else
+    static const char* const wolfSSLIP   = "::1";
+#endif
+static const word16      wolfSSLPort = 11111;
+
+static INLINE void err_sys(const char* msg)
+{
+    printf("wolfSSL error: %s\n", msg);
+    if (msg)
+        exit(EXIT_FAILURE);
+}
+
+
+#define MY_EX_USAGE 2
+
+extern int   myoptind;
+extern char* myoptarg;
+
+static INLINE int mygetopt(int argc, char** argv, const char* optstring)
+{
+    static char* next = NULL;
+
+    char  c;
+    char* cp;
+
+    if (myoptind == 0)
+        next = NULL;   /* we're starting new/over */
+
+    if (next == NULL || *next == '\0') {
+        if (myoptind == 0)
+            myoptind++;
+
+        if (myoptind >= argc || argv[myoptind][0] != '-' ||
+                                argv[myoptind][1] == '\0') {
+            myoptarg = NULL;
+            if (myoptind < argc)
+                myoptarg = argv[myoptind];
+
+            return -1;
+        }
+
+        if (strcmp(argv[myoptind], "--") == 0) {
+            myoptind++;
+            myoptarg = NULL;
+
+            if (myoptind < argc)
+                myoptarg = argv[myoptind];
+
+            return -1;
+        }
+
+        next = argv[myoptind];
+        next++;                  /* skip - */
+        myoptind++;
+    }
+
+    c  = *next++;
+    /* The C++ strchr can return a different value */
+    cp = (char*)strchr(optstring, c);
+
+    if (cp == NULL || c == ':') 
+        return '?';
+
+    cp++;
+
+    if (*cp == ':') {
+        if (*next != '\0') {
+            myoptarg = next;
+            next     = NULL;
+        }
+        else if (myoptind < argc) {
+            myoptarg = argv[myoptind];
+            myoptind++;
+        }
+        else 
+            return '?';
+    }
+
+    return c;
+}
+
+
+#if defined(OPENSSL_EXTRA) || defined(HAVE_WEBSERVER)
+
+static INLINE int PasswordCallBack(char* passwd, int sz, int rw, void* userdata)
+{
+    (void)rw;
+    (void)userdata;
+    strncpy(passwd, "yassl123", sz);
+    return 8;
+}
+
+#endif
+
+
+#if defined(KEEP_PEER_CERT) || defined(SESSION_CERTS)
+
+static INLINE void ShowX509(WOLFSSL_X509* x509, const char* hdr)
+{
+    char* altName;
+    char* issuer  = wolfSSL_X509_NAME_oneline(
+                                       wolfSSL_X509_get_issuer_name(x509), 0, 0);
+    char* subject = wolfSSL_X509_NAME_oneline(
+                                      wolfSSL_X509_get_subject_name(x509), 0, 0);
+    byte  serial[32];
+    int   ret;
+    int   sz = sizeof(serial);
+        
+    printf("%s\n issuer : %s\n subject: %s\n", hdr, issuer, subject);
+
+    while ( (altName = wolfSSL_X509_get_next_altname(x509)) != NULL)
+        printf(" altname = %s\n", altName);
+
+    ret = wolfSSL_X509_get_serial_number(x509, serial, &sz);
+    if (ret == SSL_SUCCESS) {
+        int  i;
+        int  strLen;
+        char serialMsg[80];
+
+        /* testsuite has multiple threads writing to stdout, get output
+           message ready to write once */
+        strLen = sprintf(serialMsg, " serial number");
+        for (i = 0; i < sz; i++)
+            sprintf(serialMsg + strLen + (i*3), ":%02x ", serial[i]);
+        printf("%s\n", serialMsg);
+    }
+
+    XFREE(subject, 0, DYNAMIC_TYPE_OPENSSL);
+    XFREE(issuer,  0, DYNAMIC_TYPE_OPENSSL);
+}
+
+#endif /* KEEP_PEER_CERT || SESSION_CERTS */
+
+
+static INLINE void showPeer(WOLFSSL* ssl)
+{
+
+    WOLFSSL_CIPHER* cipher;
+#ifdef KEEP_PEER_CERT
+    WOLFSSL_X509* peer = wolfSSL_get_peer_certificate(ssl);
+    if (peer)
+        ShowX509(peer, "peer's cert info:");
+    else
+        printf("peer has no cert!\n");
+#endif
+    printf("SSL version is %s\n", wolfSSL_get_version(ssl));
+
+    cipher = wolfSSL_get_current_cipher(ssl);
+    printf("SSL cipher suite is %s\n", wolfSSL_CIPHER_get_name(cipher));
+
+#if defined(SESSION_CERTS) && defined(SHOW_CERTS)
+    {
+        WOLFSSL_X509_CHAIN* chain = wolfSSL_get_peer_chain(ssl);
+        int                count = wolfSSL_get_chain_count(chain);
+        int i;
+
+        for (i = 0; i < count; i++) {
+            int length;
+            unsigned char buffer[3072];
+            WOLFSSL_X509* chainX509;
+
+            wolfSSL_get_chain_cert_pem(chain,i,buffer, sizeof(buffer), &length);
+            buffer[length] = 0;
+            printf("cert %d has length %d data = \n%s\n", i, length, buffer);
+
+            chainX509 = wolfSSL_get_chain_X509(chain, i);
+            if (chainX509)
+                ShowX509(chainX509, "session cert info:");
+            else
+                printf("get_chain_X509 failed\n");
+            wolfSSL_FreeX509(chainX509);
+        }
+    }
+#endif
+  (void)ssl;
+}
+
+
+static INLINE void build_addr(SOCKADDR_IN_T* addr, const char* peer,
+                              word16 port, int udp)
+{
+    int useLookup = 0;
+    (void)useLookup;
+    (void)udp;
+
+    memset(addr, 0, sizeof(SOCKADDR_IN_T));
+
+#ifndef TEST_IPV6
+    /* peer could be in human readable form */
+    if ( (peer != INADDR_ANY) && isalpha((int)peer[0])) {
+        #ifdef WOLFSSL_MDK_ARM
+            int err;
+            struct hostent* entry = gethostbyname(peer, &err);
+        #elif defined(WOLFSSL_TIRTOS)
+            struct hostent* entry = DNSGetHostByName(peer);
+        #else
+            struct hostent* entry = gethostbyname(peer);
+        #endif
+
+        if (entry) {
+            memcpy(&addr->sin_addr.s_addr, entry->h_addr_list[0],
+                   entry->h_length);
+            useLookup = 1;
+        }
+        else
+            err_sys("no entry for host");
+    }
+#endif
+
+
+#ifndef TEST_IPV6
+    #if defined(WOLFSSL_MDK_ARM)
+        addr->sin_family = PF_INET;
+    #else
+        addr->sin_family = AF_INET_V;
+    #endif
+    addr->sin_port = htons(port);
+    if (peer == INADDR_ANY)
+        addr->sin_addr.s_addr = INADDR_ANY;
+    else {
+        if (!useLookup)
+            addr->sin_addr.s_addr = inet_addr(peer);
+    }
+#else
+    addr->sin6_family = AF_INET_V;
+    addr->sin6_port = htons(port);
+    if (peer == INADDR_ANY)
+        addr->sin6_addr = in6addr_any;
+    else {
+        #ifdef HAVE_GETADDRINFO
+            struct addrinfo  hints;
+            struct addrinfo* answer = NULL;
+            int    ret;
+            char   strPort[80];
+
+            memset(&hints, 0, sizeof(hints));
+
+            hints.ai_family   = AF_INET_V;
+            hints.ai_socktype = udp ? SOCK_DGRAM : SOCK_STREAM;
+            hints.ai_protocol = udp ? IPPROTO_UDP : IPPROTO_TCP;
+
+            SNPRINTF(strPort, sizeof(strPort), "%d", port);
+            strPort[79] = '\0';
+
+            ret = getaddrinfo(peer, strPort, &hints, &answer);
+            if (ret < 0 || answer == NULL)
+                err_sys("getaddrinfo failed");
+
+            memcpy(addr, answer->ai_addr, answer->ai_addrlen);
+            freeaddrinfo(answer);
+        #else
+            printf("no ipv6 getaddrinfo, loopback only tests/examples\n");
+            addr->sin6_addr = in6addr_loopback;
+        #endif
+    }
+#endif
+}
+
+
+static INLINE void tcp_socket(SOCKET_T* sockfd, int udp)
+{
+    if (udp)
+        *sockfd = socket(AF_INET_V, SOCK_DGRAM, 0);
+    else
+        *sockfd = socket(AF_INET_V, SOCK_STREAM, 0);
+
+#ifdef USE_WINDOWS_API
+    if (*sockfd == INVALID_SOCKET)
+        err_sys("socket failed\n");
+#elif defined(WOLFSSL_TIRTOS)
+    if (*sockfd == -1)
+        err_sys("socket failed\n");
+#else
+    if (*sockfd < 0)
+        err_sys("socket failed\n");
+#endif
+
+#ifndef USE_WINDOWS_API 
+#ifdef SO_NOSIGPIPE
+    {
+        int       on = 1;
+        socklen_t len = sizeof(on);
+        int       res = setsockopt(*sockfd, SOL_SOCKET, SO_NOSIGPIPE, &on, len);
+        if (res < 0)
+            err_sys("setsockopt SO_NOSIGPIPE failed\n");
+    }
+#elif defined(WOLFSSL_MDK_ARM) || defined (WOLFSSL_TIRTOS)
+    /* nothing to define */
+#else  /* no S_NOSIGPIPE */
+    signal(SIGPIPE, SIG_IGN);
+#endif /* S_NOSIGPIPE */
+
+#if defined(TCP_NODELAY)
+    if (!udp)
+    {
+        int       on = 1;
+        socklen_t len = sizeof(on);
+        int       res = setsockopt(*sockfd, IPPROTO_TCP, TCP_NODELAY, &on, len);
+        if (res < 0)
+            err_sys("setsockopt TCP_NODELAY failed\n");
+    }
+#endif
+#endif  /* USE_WINDOWS_API */
+}
+
+static INLINE void tcp_connect(SOCKET_T* sockfd, const char* ip, word16 port,
+                               int udp)
+{
+    SOCKADDR_IN_T addr;
+    build_addr(&addr, ip, port, udp);
+    tcp_socket(sockfd, udp);
+
+    if (!udp) {
+        if (connect(*sockfd, (const struct sockaddr*)&addr, sizeof(addr)) != 0)
+            err_sys("tcp connect failed");
+    }
+}
+
+
+static INLINE void udp_connect(SOCKET_T* sockfd, void* addr, int addrSz)
+{
+    if (connect(*sockfd, (const struct sockaddr*)addr, addrSz) != 0)
+        err_sys("tcp connect failed");
+}
+
+
+enum {
+    TEST_SELECT_FAIL,
+    TEST_TIMEOUT,
+    TEST_RECV_READY,
+    TEST_ERROR_READY
+};
+
+
+#if !defined(WOLFSSL_MDK_ARM) && !defined(WOLFSSL_TIRTOS)
+static INLINE int tcp_select(SOCKET_T socketfd, int to_sec)
+{
+    fd_set recvfds, errfds;
+    SOCKET_T nfds = socketfd + 1;
+    struct timeval timeout = { (to_sec > 0) ? to_sec : 0, 0};
+    int result;
+
+    FD_ZERO(&recvfds);
+    FD_SET(socketfd, &recvfds);
+    FD_ZERO(&errfds);
+    FD_SET(socketfd, &errfds);
+
+    result = select(nfds, &recvfds, NULL, &errfds, &timeout);
+
+    if (result == 0)
+        return TEST_TIMEOUT;
+    else if (result > 0) {
+        if (FD_ISSET(socketfd, &recvfds))
+            return TEST_RECV_READY;
+        else if(FD_ISSET(socketfd, &errfds))
+            return TEST_ERROR_READY;
+    }
+
+    return TEST_SELECT_FAIL;
+}
+#elif defined(WOLFSSL_TIRTOS)
+static INLINE int tcp_select(SOCKET_T socketfd, int to_sec)
+{
+    return TEST_RECV_READY;
+}
+#endif /* !WOLFSSL_MDK_ARM */
+
+
+static INLINE void tcp_listen(SOCKET_T* sockfd, word16* port, int useAnyAddr,
+                              int udp)
+{
+    SOCKADDR_IN_T addr;
+
+    /* don't use INADDR_ANY by default, firewall may block, make user switch
+       on */
+    build_addr(&addr, (useAnyAddr ? INADDR_ANY : wolfSSLIP), *port, udp);
+    tcp_socket(sockfd, udp);
+
+#if !defined(USE_WINDOWS_API) && !defined(WOLFSSL_MDK_ARM)
+    {
+        int       res, on  = 1;
+        socklen_t len = sizeof(on);
+        res = setsockopt(*sockfd, SOL_SOCKET, SO_REUSEADDR, &on, len);
+        if (res < 0)
+            err_sys("setsockopt SO_REUSEADDR failed\n");
+    }
+#endif
+
+    if (bind(*sockfd, (const struct sockaddr*)&addr, sizeof(addr)) != 0)
+        err_sys("tcp bind failed");
+    if (!udp) {
+        if (listen(*sockfd, 5) != 0)
+            err_sys("tcp listen failed");
+    }
+    #if (defined(NO_MAIN_DRIVER) && !defined(USE_WINDOWS_API)) && !defined(WOLFSSL_TIRTOS)
+        if (*port == 0) {
+            socklen_t len = sizeof(addr);
+            if (getsockname(*sockfd, (struct sockaddr*)&addr, &len) == 0) {
+                #ifndef TEST_IPV6
+                    *port = ntohs(addr.sin_port);
+                #else
+                    *port = ntohs(addr.sin6_port);
+                #endif
+            }
+        }
+    #endif
+}
+
+
+static INLINE int udp_read_connect(SOCKET_T sockfd)
+{
+    SOCKADDR_IN_T cliaddr;
+    byte          b[1500];
+    int           n;
+    socklen_t     len = sizeof(cliaddr);
+
+    n = (int)recvfrom(sockfd, (char*)b, sizeof(b), MSG_PEEK,
+                      (struct sockaddr*)&cliaddr, &len);
+    if (n > 0) {
+        if (connect(sockfd, (const struct sockaddr*)&cliaddr,
+                    sizeof(cliaddr)) != 0)
+            err_sys("udp connect failed");
+    }
+    else
+        err_sys("recvfrom failed");
+
+    return sockfd;
+}
+
+static INLINE void udp_accept(SOCKET_T* sockfd, SOCKET_T* clientfd,
+                              int useAnyAddr, word16 port, func_args* args)
+{
+    SOCKADDR_IN_T addr;
+
+    (void)args;
+    build_addr(&addr, (useAnyAddr ? INADDR_ANY : wolfSSLIP), port, 1);
+    tcp_socket(sockfd, 1);
+
+
+#if !defined(USE_WINDOWS_API) && !defined(WOLFSSL_MDK_ARM)
+    {
+        int       res, on  = 1;
+        socklen_t len = sizeof(on);
+        res = setsockopt(*sockfd, SOL_SOCKET, SO_REUSEADDR, &on, len);
+        if (res < 0)
+            err_sys("setsockopt SO_REUSEADDR failed\n");
+    }
+#endif
+
+    if (bind(*sockfd, (const struct sockaddr*)&addr, sizeof(addr)) != 0)
+        err_sys("tcp bind failed");
+
+    #if (defined(NO_MAIN_DRIVER) && !defined(USE_WINDOWS_API)) && !defined(WOLFSSL_TIRTOS)
+        if (port == 0) {
+            socklen_t len = sizeof(addr);
+            if (getsockname(*sockfd, (struct sockaddr*)&addr, &len) == 0) {
+                #ifndef TEST_IPV6
+                    port = ntohs(addr.sin_port);
+                #else
+                    port = ntohs(addr.sin6_port);
+                #endif
+            }
+        }
+    #endif
+
+#if defined(_POSIX_THREADS) && defined(NO_MAIN_DRIVER) && !defined(__MINGW32__)
+    /* signal ready to accept data */
+    {
+    tcp_ready* ready = args->signal;
+    pthread_mutex_lock(&ready->mutex);
+    ready->ready = 1;
+    ready->port = port;
+    pthread_cond_signal(&ready->cond);
+    pthread_mutex_unlock(&ready->mutex);
+    }
+#elif defined (WOLFSSL_TIRTOS)
+    /* Need mutex? */
+    tcp_ready* ready = args->signal;
+    ready->ready = 1;
+    ready->port = port;
+#endif
+
+    *clientfd = udp_read_connect(*sockfd);
+}
+
+static INLINE void tcp_accept(SOCKET_T* sockfd, SOCKET_T* clientfd,
+                              func_args* args, word16 port, int useAnyAddr,
+                              int udp, int ready_file)
+{
+    SOCKADDR_IN_T client;
+    socklen_t client_len = sizeof(client);
+
+    if (udp) {
+        udp_accept(sockfd, clientfd, useAnyAddr, port, args);
+        return;
+    }
+
+    tcp_listen(sockfd, &port, useAnyAddr, udp);
+
+#if defined(_POSIX_THREADS) && defined(NO_MAIN_DRIVER) && !defined(__MINGW32__)
+    /* signal ready to tcp_accept */
+    {
+    tcp_ready* ready = args->signal;
+    pthread_mutex_lock(&ready->mutex);
+    ready->ready = 1;
+    ready->port = port;
+    pthread_cond_signal(&ready->cond);
+    pthread_mutex_unlock(&ready->mutex);
+    }
+#elif defined (WOLFSSL_TIRTOS)
+    /* Need mutex? */
+    tcp_ready* ready = args->signal;
+    ready->ready = 1;
+    ready->port = port;
+#endif
+
+    if (ready_file) {
+#ifndef NO_FILESYSTEM
+    #ifndef USE_WINDOWS_API
+        FILE* srf = fopen("/tmp/wolfssl_server_ready", "w");
+    #else
+        FILE* srf = fopen("wolfssl_server_ready", "w");
+    #endif
+
+        if (srf) {
+            fputs("ready", srf);
+            fclose(srf);
+        }
+#endif
+    }
+
+    *clientfd = accept(*sockfd, (struct sockaddr*)&client,
+                      (ACCEPT_THIRD_T)&client_len);
+#ifdef USE_WINDOWS_API
+    if (*clientfd == INVALID_SOCKET)
+        err_sys("tcp accept failed");
+#else
+    if (*clientfd == -1)
+        err_sys("tcp accept failed");
+#endif
+}
+
+
+static INLINE void tcp_set_nonblocking(SOCKET_T* sockfd)
+{
+    #ifdef USE_WINDOWS_API 
+        unsigned long blocking = 1;
+        int ret = ioctlsocket(*sockfd, FIONBIO, &blocking);
+        if (ret == SOCKET_ERROR)
+            err_sys("ioctlsocket failed");
+    #elif defined(WOLFSSL_MDK_ARM) || defined (WOLFSSL_TIRTOS)
+         /* non blocking not suppported, for now */ 
+    #else
+        int flags = fcntl(*sockfd, F_GETFL, 0);
+        if (flags < 0)
+            err_sys("fcntl get failed");
+        flags = fcntl(*sockfd, F_SETFL, flags | O_NONBLOCK);
+        if (flags < 0)
+            err_sys("fcntl set failed");
+    #endif
+}
+
+
+#ifndef NO_PSK
+
+static INLINE unsigned int my_psk_client_cb(WOLFSSL* ssl, const char* hint,
+        char* identity, unsigned int id_max_len, unsigned char* key,
+        unsigned int key_max_len)
+{
+    (void)ssl;
+    (void)hint;
+    (void)key_max_len;
+
+    /* identity is OpenSSL testing default for openssl s_client, keep same */
+    strncpy(identity, "Client_identity", id_max_len);
+
+
+    /* test key in hex is 0x1a2b3c4d , in decimal 439,041,101 , we're using
+       unsigned binary */
+    key[0] = 26;
+    key[1] = 43;
+    key[2] = 60;
+    key[3] = 77;
+
+    return 4;   /* length of key in octets or 0 for error */
+}
+
+
+static INLINE unsigned int my_psk_server_cb(WOLFSSL* ssl, const char* identity,
+        unsigned char* key, unsigned int key_max_len)
+{
+    (void)ssl;
+    (void)key_max_len;
+
+    /* identity is OpenSSL testing default for openssl s_client, keep same */
+    if (strncmp(identity, "Client_identity", 15) != 0)
+        return 0;
+
+    /* test key in hex is 0x1a2b3c4d , in decimal 439,041,101 , we're using
+       unsigned binary */
+    key[0] = 26;
+    key[1] = 43;
+    key[2] = 60;
+    key[3] = 77;
+
+    return 4;   /* length of key in octets or 0 for error */
+}
+
+#endif /* NO_PSK */
+
+
+#ifdef USE_WINDOWS_API 
+
+    #define WIN32_LEAN_AND_MEAN
+    #include 
+
+    static INLINE double current_time()
+    {
+        static int init = 0;
+        static LARGE_INTEGER freq;
+    
+        LARGE_INTEGER count;
+
+        if (!init) {
+            QueryPerformanceFrequency(&freq);
+            init = 1;
+        }
+
+        QueryPerformanceCounter(&count);
+
+        return (double)count.QuadPart / freq.QuadPart;
+    }
+
+#elif defined(WOLFSSL_TIRTOS)
+    extern double current_time();
+#else
+
+#if !defined(WOLFSSL_MDK_ARM)
+    #include 
+
+    static INLINE double current_time(void)
+    {
+        struct timeval tv;
+        gettimeofday(&tv, 0);
+
+        return (double)tv.tv_sec + (double)tv.tv_usec / 1000000;
+    }
+        
+#endif
+#endif /* USE_WINDOWS_API */
+
+
+#if defined(NO_FILESYSTEM) && !defined(NO_CERTS)
+
+    enum {
+        WOLFSSL_CA   = 1,
+        WOLFSSL_CERT = 2,
+        WOLFSSL_KEY  = 3
+    };
+
+    static INLINE void load_buffer(WOLFSSL_CTX* ctx, const char* fname, int type)
+    {
+        /* test buffer load */
+        long  sz = 0;
+        byte  buff[10000];
+        FILE* file = fopen(fname, "rb");
+
+        if (!file)
+            err_sys("can't open file for buffer load "
+                    "Please run from wolfSSL home directory if not");
+        fseek(file, 0, SEEK_END);
+        sz = ftell(file);
+        rewind(file);
+        fread(buff, sizeof(buff), 1, file);
+  
+        if (type == WOLFSSL_CA) {
+            if (wolfSSL_CTX_load_verify_buffer(ctx, buff, sz, SSL_FILETYPE_PEM)
+                                              != SSL_SUCCESS)
+                err_sys("can't load buffer ca file");
+        }
+        else if (type == WOLFSSL_CERT) {
+            if (wolfSSL_CTX_use_certificate_buffer(ctx, buff, sz,
+                        SSL_FILETYPE_PEM) != SSL_SUCCESS)
+                err_sys("can't load buffer cert file");
+        }
+        else if (type == WOLFSSL_KEY) {
+            if (wolfSSL_CTX_use_PrivateKey_buffer(ctx, buff, sz,
+                        SSL_FILETYPE_PEM) != SSL_SUCCESS)
+                err_sys("can't load buffer key file");
+        }
+    }
+
+#endif /* NO_FILESYSTEM */
+
+#ifdef VERIFY_CALLBACK
+
+static INLINE int myVerify(int preverify, WOLFSSL_X509_STORE_CTX* store)
+{
+    (void)preverify;
+    char buffer[WOLFSSL_MAX_ERROR_SZ];
+
+#ifdef OPENSSL_EXTRA
+    WOLFSSL_X509* peer;
+#endif
+
+    printf("In verification callback, error = %d, %s\n", store->error,
+                                 wolfSSL_ERR_error_string(store->error, buffer));
+#ifdef OPENSSL_EXTRA
+    peer = store->current_cert;
+    if (peer) {
+        char* issuer  = wolfSSL_X509_NAME_oneline(
+                                       wolfSSL_X509_get_issuer_name(peer), 0, 0);
+        char* subject = wolfSSL_X509_NAME_oneline(
+                                      wolfSSL_X509_get_subject_name(peer), 0, 0);
+        printf("peer's cert info:\n issuer : %s\n subject: %s\n", issuer,
+                                                                  subject);
+        XFREE(subject, 0, DYNAMIC_TYPE_OPENSSL);
+        XFREE(issuer,  0, DYNAMIC_TYPE_OPENSSL);
+    }
+    else
+        printf("peer has no cert!\n");
+#endif
+    printf("Subject's domain name is %s\n", store->domain);
+
+    printf("Allowing to continue anyway (shouldn't do this, EVER!!!)\n");
+    return 1;
+}
+
+#endif /* VERIFY_CALLBACK */
+
+
+static INLINE int myDateCb(int preverify, WOLFSSL_X509_STORE_CTX* store)
+{
+    char buffer[WOLFSSL_MAX_ERROR_SZ];
+    (void)preverify;
+
+    printf("In verification callback, error = %d, %s\n", store->error,
+                                 wolfSSL_ERR_error_string(store->error, buffer));
+    printf("Subject's domain name is %s\n", store->domain);
+
+    if (store->error == ASN_BEFORE_DATE_E || store->error == ASN_AFTER_DATE_E) {
+        printf("Overriding cert date error as example for bad clock testing\n");
+        return 1;
+    }
+    printf("Cert error is not date error, not overriding\n");
+
+    return 0;
+}
+
+
+#ifdef HAVE_CRL
+
+static INLINE void CRL_CallBack(const char* url)
+{
+    printf("CRL callback url = %s\n", url);
+}
+
+#endif
+
+#ifndef NO_DH
+static INLINE void SetDH(WOLFSSL* ssl)
+{
+    /* dh1024 p */
+    static unsigned char p[] =
+    {
+        0xE6, 0x96, 0x9D, 0x3D, 0x49, 0x5B, 0xE3, 0x2C, 0x7C, 0xF1, 0x80, 0xC3,
+        0xBD, 0xD4, 0x79, 0x8E, 0x91, 0xB7, 0x81, 0x82, 0x51, 0xBB, 0x05, 0x5E,
+        0x2A, 0x20, 0x64, 0x90, 0x4A, 0x79, 0xA7, 0x70, 0xFA, 0x15, 0xA2, 0x59,
+        0xCB, 0xD5, 0x23, 0xA6, 0xA6, 0xEF, 0x09, 0xC4, 0x30, 0x48, 0xD5, 0xA2,
+        0x2F, 0x97, 0x1F, 0x3C, 0x20, 0x12, 0x9B, 0x48, 0x00, 0x0E, 0x6E, 0xDD,
+        0x06, 0x1C, 0xBC, 0x05, 0x3E, 0x37, 0x1D, 0x79, 0x4E, 0x53, 0x27, 0xDF,
+        0x61, 0x1E, 0xBB, 0xBE, 0x1B, 0xAC, 0x9B, 0x5C, 0x60, 0x44, 0xCF, 0x02,
+        0x3D, 0x76, 0xE0, 0x5E, 0xEA, 0x9B, 0xAD, 0x99, 0x1B, 0x13, 0xA6, 0x3C,
+        0x97, 0x4E, 0x9E, 0xF1, 0x83, 0x9E, 0xB5, 0xDB, 0x12, 0x51, 0x36, 0xF7,
+        0x26, 0x2E, 0x56, 0xA8, 0x87, 0x15, 0x38, 0xDF, 0xD8, 0x23, 0xC6, 0x50,
+        0x50, 0x85, 0xE2, 0x1F, 0x0D, 0xD5, 0xC8, 0x6B,
+    };
+
+    /* dh1024 g */
+    static unsigned char g[] =
+    {
+      0x02,
+    };
+
+    wolfSSL_SetTmpDH(ssl, p, sizeof(p), g, sizeof(g));
+}
+
+static INLINE void SetDHCtx(WOLFSSL_CTX* ctx)
+{
+    /* dh1024 p */
+    static unsigned char p[] =
+    {
+        0xE6, 0x96, 0x9D, 0x3D, 0x49, 0x5B, 0xE3, 0x2C, 0x7C, 0xF1, 0x80, 0xC3,
+        0xBD, 0xD4, 0x79, 0x8E, 0x91, 0xB7, 0x81, 0x82, 0x51, 0xBB, 0x05, 0x5E,
+        0x2A, 0x20, 0x64, 0x90, 0x4A, 0x79, 0xA7, 0x70, 0xFA, 0x15, 0xA2, 0x59,
+        0xCB, 0xD5, 0x23, 0xA6, 0xA6, 0xEF, 0x09, 0xC4, 0x30, 0x48, 0xD5, 0xA2,
+        0x2F, 0x97, 0x1F, 0x3C, 0x20, 0x12, 0x9B, 0x48, 0x00, 0x0E, 0x6E, 0xDD,
+        0x06, 0x1C, 0xBC, 0x05, 0x3E, 0x37, 0x1D, 0x79, 0x4E, 0x53, 0x27, 0xDF,
+        0x61, 0x1E, 0xBB, 0xBE, 0x1B, 0xAC, 0x9B, 0x5C, 0x60, 0x44, 0xCF, 0x02,
+        0x3D, 0x76, 0xE0, 0x5E, 0xEA, 0x9B, 0xAD, 0x99, 0x1B, 0x13, 0xA6, 0x3C,
+        0x97, 0x4E, 0x9E, 0xF1, 0x83, 0x9E, 0xB5, 0xDB, 0x12, 0x51, 0x36, 0xF7,
+        0x26, 0x2E, 0x56, 0xA8, 0x87, 0x15, 0x38, 0xDF, 0xD8, 0x23, 0xC6, 0x50,
+        0x50, 0x85, 0xE2, 0x1F, 0x0D, 0xD5, 0xC8, 0x6B,
+    };
+
+    /* dh1024 g */
+    static unsigned char g[] =
+    {
+      0x02,
+    };
+
+    wolfSSL_CTX_SetTmpDH(ctx, p, sizeof(p), g, sizeof(g));
+}
+#endif /* NO_DH */
+
+#ifndef NO_CERTS
+
+static INLINE void CaCb(unsigned char* der, int sz, int type)
+{
+    (void)der;
+    printf("Got CA cache add callback, derSz = %d, type = %d\n", sz, type);
+}
+
+#endif /* !NO_CERTS */
+
+#ifdef HAVE_CAVIUM
+
+static INLINE int OpenNitroxDevice(int dma_mode,int dev_id)
+{
+   Csp1CoreAssignment core_assign;
+   Uint32             device;
+
+   if (CspInitialize(CAVIUM_DIRECT,CAVIUM_DEV_ID))
+      return -1;
+   if (Csp1GetDevType(&device))
+      return -1;
+   if (device != NPX_DEVICE) {
+      if (ioctl(gpkpdev_hdlr[CAVIUM_DEV_ID], IOCTL_CSP1_GET_CORE_ASSIGNMENT,
+                (Uint32 *)&core_assign)!= 0)
+         return -1;
+   }
+   CspShutdown(CAVIUM_DEV_ID);
+
+   return CspInitialize(dma_mode, dev_id);
+}
+
+#endif /* HAVE_CAVIUM */
+
+
+#ifdef USE_WINDOWS_API 
+
+/* do back x number of directories */
+static INLINE void ChangeDirBack(int x)
+{
+    char path[MAX_PATH];
+
+    if (x == 1)
+        strncpy(path, "..\\", MAX_PATH);
+    else if (x == 2)
+        strncpy(path, "..\\..\\", MAX_PATH);
+    else if (x == 3)
+        strncpy(path, "..\\..\\..\\", MAX_PATH);
+    else if (x == 4)
+        strncpy(path, "..\\..\\..\\..\\", MAX_PATH);
+    else
+        strncpy(path, ".\\", MAX_PATH);
+    
+    SetCurrentDirectoryA(path);
+}
+
+/* does current dir contain str */
+static INLINE int CurrentDir(const char* str)
+{
+    char  path[MAX_PATH];
+    char* baseName;
+
+    GetCurrentDirectoryA(sizeof(path), path);
+
+    baseName = strrchr(path, '\\');
+    if (baseName)
+        baseName++;
+    else
+        baseName = path;
+
+    if (strstr(baseName, str))
+        return 1;
+
+    return 0;
+}
+
+#elif defined(WOLFSSL_MDK_ARM)
+    /* KEIL-RL File System does not support relative directry */
+#elif defined(WOLFSSL_TIRTOS)
+#else
+
+#ifndef MAX_PATH
+    #define MAX_PATH 256
+#endif
+
+/* do back x number of directories */
+static INLINE void ChangeDirBack(int x)
+{
+    char path[MAX_PATH];
+
+    if (x == 1)
+        strncpy(path, "../", MAX_PATH);
+    else if (x == 2)
+        strncpy(path, "../../", MAX_PATH);
+    else if (x == 3)
+        strncpy(path, "../../../", MAX_PATH);
+    else if (x == 4)
+        strncpy(path, "../../../../", MAX_PATH);
+    else
+        strncpy(path, "./", MAX_PATH);
+    
+    if (chdir(path) < 0)
+        printf("chdir to %s failed\n", path);
+}
+
+/* does current dir contain str */
+static INLINE int CurrentDir(const char* str)
+{
+    char  path[MAX_PATH];
+    char* baseName;
+
+    if (getcwd(path, sizeof(path)) == NULL) {
+        printf("no current dir?\n");
+        return 0;
+    }
+
+    baseName = strrchr(path, '/');
+    if (baseName)
+        baseName++;
+    else
+        baseName = path;
+
+    if (strstr(baseName, str))
+        return 1;
+
+    return 0;
+}
+
+#endif /* USE_WINDOWS_API */
+
+
+#ifdef USE_WOLFSSL_MEMORY
+
+    typedef struct memoryStats {
+        size_t totalAllocs;     /* number of allocations */
+        size_t totalBytes;      /* total number of bytes allocated */
+        size_t peakBytes;       /* concurrent max bytes */
+        size_t currentBytes;    /* total current bytes in use */
+    } memoryStats;
+
+    typedef struct memHint {
+        size_t thisSize;      /* size of this memory */
+        void*  thisMemory;    /* actual memory for user */
+    } memHint;
+
+    typedef struct memoryTrack {
+        union {
+            memHint hint;
+            byte    alignit[16];   /* make sure we have strong alignment */
+        } u;
+    } memoryTrack;
+
+    #if defined(WOLFSSL_TRACK_MEMORY)
+        #define DO_MEM_STATS
+        static memoryStats ourMemStats;
+    #endif
+
+    static INLINE void* TrackMalloc(size_t sz)
+    {
+        memoryTrack* mt;
+
+        if (sz == 0)
+            return NULL;
+
+        mt = (memoryTrack*)malloc(sizeof(memoryTrack) + sz);
+        if (mt == NULL)
+            return NULL;
+
+        mt->u.hint.thisSize   = sz;
+        mt->u.hint.thisMemory = (byte*)mt + sizeof(memoryTrack);
+
+#ifdef DO_MEM_STATS
+        ourMemStats.totalAllocs++;
+        ourMemStats.totalBytes   += sz;
+        ourMemStats.currentBytes += sz;
+        if (ourMemStats.currentBytes > ourMemStats.peakBytes)
+            ourMemStats.peakBytes = ourMemStats.currentBytes;
+#endif
+
+        return mt->u.hint.thisMemory;
+    }
+
+
+    static INLINE void TrackFree(void* ptr)
+    {
+        memoryTrack* mt;
+
+        if (ptr == NULL)
+            return;
+
+        mt = (memoryTrack*)ptr;
+        --mt;   /* same as minus sizeof(memoryTrack), removes header */
+
+#ifdef DO_MEM_STATS 
+        ourMemStats.currentBytes -= mt->u.hint.thisSize; 
+#endif
+
+        free(mt);
+    }
+
+
+    static INLINE void* TrackRealloc(void* ptr, size_t sz)
+    {
+        void* ret = TrackMalloc(sz);
+
+        if (ptr) {
+            /* if realloc is bigger, don't overread old ptr */
+            memoryTrack* mt = (memoryTrack*)ptr;
+            --mt;  /* same as minus sizeof(memoryTrack), removes header */
+
+            if (mt->u.hint.thisSize < sz)
+                sz = mt->u.hint.thisSize;
+        }
+
+        if (ret && ptr)
+            memcpy(ret, ptr, sz);
+
+        if (ret)
+            TrackFree(ptr);
+
+        return ret;
+    }
+
+    static INLINE void InitMemoryTracker(void) 
+    {
+        if (wolfSSL_SetAllocators(TrackMalloc, TrackFree, TrackRealloc) != 0)
+            err_sys("wolfSSL SetAllocators failed for track memory");
+
+    #ifdef DO_MEM_STATS
+        ourMemStats.totalAllocs  = 0;
+        ourMemStats.totalBytes   = 0;
+        ourMemStats.peakBytes    = 0;
+        ourMemStats.currentBytes = 0;
+    #endif
+    }
+
+    static INLINE void ShowMemoryTracker(void) 
+    {
+    #ifdef DO_MEM_STATS 
+        printf("total   Allocs = %9lu\n",
+                                       (unsigned long)ourMemStats.totalAllocs);
+        printf("total   Bytes  = %9lu\n",
+                                       (unsigned long)ourMemStats.totalBytes);
+        printf("peak    Bytes  = %9lu\n",
+                                       (unsigned long)ourMemStats.peakBytes);
+        printf("current Bytes  = %9lu\n",
+                                       (unsigned long)ourMemStats.currentBytes);
+    #endif
+    }
+
+#endif /* USE_WOLFSSL_MEMORY */
+
+
+#ifdef HAVE_STACK_SIZE
+
+typedef THREAD_RETURN WOLFSSL_THREAD (*thread_func)(void* args);
+
+
+static INLINE void StackSizeCheck(func_args* args, thread_func tf)
+{
+    int            ret, i, used;
+    unsigned char* myStack;
+    int            stackSize = 1024*128;
+    pthread_attr_t myAttr;
+    pthread_t      threadId;
+
+#ifdef PTHREAD_STACK_MIN
+    if (stackSize < PTHREAD_STACK_MIN)
+        stackSize = PTHREAD_STACK_MIN;
+#endif
+
+    ret = posix_memalign((void**)&myStack, sysconf(_SC_PAGESIZE), stackSize);
+    if (ret != 0) 
+        err_sys("posix_memalign failed\n");        
+
+    memset(myStack, 0x01, stackSize);
+
+    ret = pthread_attr_init(&myAttr);
+    if (ret != 0)
+        err_sys("attr_init failed");
+
+    ret = pthread_attr_setstack(&myAttr, myStack, stackSize);
+    if (ret != 0)
+        err_sys("attr_setstackaddr failed");
+
+    ret = pthread_create(&threadId, &myAttr, tf, args);
+    if (ret != 0) {
+        perror("pthread_create failed");
+        exit(EXIT_FAILURE);
+    }
+
+    ret = pthread_join(threadId, NULL);
+    if (ret != 0)
+        err_sys("pthread_join failed");
+
+    for (i = 0; i < stackSize; i++) {
+        if (myStack[i] != 0x01) {
+            break;
+        }
+    }
+
+    used = stackSize - i;
+    printf("stack used = %d\n", used);
+}
+
+
+#endif /* HAVE_STACK_SIZE */
+
+
+#ifdef STACK_TRAP
+
+/* good settings
+   --enable-debug --disable-shared C_EXTRA_FLAGS="-DUSER_TIME -DTFM_TIMING_RESISTANT -DPOSITIVE_EXP_ONLY -DSTACK_TRAP"
+
+*/
+
+#ifdef HAVE_STACK_SIZE
+    /* client only for now, setrlimit will fail if pthread_create() called */
+    /* STACK_SIZE does pthread_create() on client */
+    #error "can't use STACK_TRAP with STACK_SIZE, setrlimit will fail"
+#endif /* HAVE_STACK_SIZE */
+
+static INLINE void StackTrap(void)
+{
+    struct rlimit  rl;
+    if (getrlimit(RLIMIT_STACK, &rl) != 0)
+        err_sys("getrlimit failed");
+    printf("rlim_cur = %llu\n", rl.rlim_cur);
+    rl.rlim_cur = 1024*21;  /* adjust trap size here */
+    if (setrlimit(RLIMIT_STACK, &rl) != 0) {
+        perror("setrlimit");
+        err_sys("setrlimit failed");
+    }
+}
+
+#else /* STACK_TRAP */
+
+static INLINE void StackTrap(void)
+{
+}
+
+#endif /* STACK_TRAP */
+
+
+#ifdef ATOMIC_USER
+
+/* Atomic Encrypt Context example */
+typedef struct AtomicEncCtx {
+    int  keySetup;           /* have we done key setup yet */
+    Aes  aes;                /* for aes example */
+} AtomicEncCtx;
+
+
+/* Atomic Decrypt Context example */
+typedef struct AtomicDecCtx {
+    int  keySetup;           /* have we done key setup yet */
+    Aes  aes;                /* for aes example */
+} AtomicDecCtx;
+
+
+static INLINE int myMacEncryptCb(WOLFSSL* ssl, unsigned char* macOut, 
+       const unsigned char* macIn, unsigned int macInSz, int macContent, 
+       int macVerify, unsigned char* encOut, const unsigned char* encIn,
+       unsigned int encSz, void* ctx)
+{
+    int  ret;
+    Hmac hmac;
+    byte myInner[WOLFSSL_TLS_HMAC_INNER_SZ];
+    AtomicEncCtx* encCtx = (AtomicEncCtx*)ctx;
+    const char* tlsStr = "TLS";
+
+    /* example supports (d)tls aes */
+    if (wolfSSL_GetBulkCipher(ssl) != wolfssl_aes) {
+        printf("myMacEncryptCb not using AES\n");
+        return -1;
+    }
+
+    if (strstr(wolfSSL_get_version(ssl), tlsStr) == NULL) {
+        printf("myMacEncryptCb not using (D)TLS\n");
+        return -1;
+    }
+
+    /* hmac, not needed if aead mode */
+    wolfSSL_SetTlsHmacInner(ssl, myInner, macInSz, macContent, macVerify);
+
+    ret = wc_HmacSetKey(&hmac, wolfSSL_GetHmacType(ssl),
+               wolfSSL_GetMacSecret(ssl, macVerify), wolfSSL_GetHmacSize(ssl));
+    if (ret != 0)
+        return ret;
+    ret = wc_HmacUpdate(&hmac, myInner, sizeof(myInner));
+    if (ret != 0)
+        return ret;
+    ret = wc_HmacUpdate(&hmac, macIn, macInSz);
+    if (ret != 0)
+        return ret;
+    ret = wc_HmacFinal(&hmac, macOut);
+    if (ret != 0)
+        return ret;
+
+
+    /* encrypt setup on first time */
+    if (encCtx->keySetup == 0) {
+        int   keyLen = wolfSSL_GetKeySize(ssl);
+        const byte* key;
+        const byte* iv;
+
+        if (wolfSSL_GetSide(ssl) == WOLFSSL_CLIENT_END) {
+            key = wolfSSL_GetClientWriteKey(ssl);
+            iv  = wolfSSL_GetClientWriteIV(ssl);
+        }
+        else {
+            key = wolfSSL_GetServerWriteKey(ssl);
+            iv  = wolfSSL_GetServerWriteIV(ssl);
+        }
+
+        ret = wc_AesSetKey(&encCtx->aes, key, keyLen, iv, AES_ENCRYPTION);
+        if (ret != 0) {
+            printf("AesSetKey failed in myMacEncryptCb\n");
+            return ret;
+        }
+        encCtx->keySetup = 1;
+    }
+
+    /* encrypt */
+    return wc_AesCbcEncrypt(&encCtx->aes, encOut, encIn, encSz);
+}
+
+
+static INLINE int myDecryptVerifyCb(WOLFSSL* ssl, 
+       unsigned char* decOut, const unsigned char* decIn,
+       unsigned int decSz, int macContent, int macVerify,
+       unsigned int* padSz, void* ctx)
+{
+    AtomicDecCtx* decCtx = (AtomicDecCtx*)ctx;
+    int ret      = 0;
+    int macInSz  = 0;
+    int ivExtra  = 0;
+    int digestSz = wolfSSL_GetHmacSize(ssl);
+    unsigned int pad     = 0;
+    unsigned int padByte = 0;
+    Hmac hmac;
+    byte myInner[WOLFSSL_TLS_HMAC_INNER_SZ];
+    byte verify[MAX_DIGEST_SIZE];
+    const char* tlsStr = "TLS";
+
+    /* example supports (d)tls aes */
+    if (wolfSSL_GetBulkCipher(ssl) != wolfssl_aes) {
+        printf("myMacEncryptCb not using AES\n");
+        return -1;
+    }
+
+    if (strstr(wolfSSL_get_version(ssl), tlsStr) == NULL) {
+        printf("myMacEncryptCb not using (D)TLS\n");
+        return -1;
+    }
+
+    /*decrypt */
+    if (decCtx->keySetup == 0) {
+        int   keyLen = wolfSSL_GetKeySize(ssl);
+        const byte* key;
+        const byte* iv;
+
+        /* decrypt is from other side (peer) */
+        if (wolfSSL_GetSide(ssl) == WOLFSSL_SERVER_END) {
+            key = wolfSSL_GetClientWriteKey(ssl);
+            iv  = wolfSSL_GetClientWriteIV(ssl);
+        }
+        else {
+            key = wolfSSL_GetServerWriteKey(ssl);
+            iv  = wolfSSL_GetServerWriteIV(ssl);
+        }
+
+        ret = wc_AesSetKey(&decCtx->aes, key, keyLen, iv, AES_DECRYPTION);
+        if (ret != 0) {
+            printf("AesSetKey failed in myDecryptVerifyCb\n");
+            return ret;
+        }
+        decCtx->keySetup = 1;
+    }
+
+    /* decrypt */
+    ret = wc_AesCbcDecrypt(&decCtx->aes, decOut, decIn, decSz);
+
+    if (wolfSSL_GetCipherType(ssl) == WOLFSSL_AEAD_TYPE) {
+        *padSz = wolfSSL_GetAeadMacSize(ssl);
+        return 0; /* hmac, not needed if aead mode */
+    }
+
+    if (wolfSSL_GetCipherType(ssl) == WOLFSSL_BLOCK_TYPE) {
+        pad     = *(decOut + decSz - 1);
+        padByte = 1;
+        if (wolfSSL_IsTLSv1_1(ssl))
+            ivExtra = wolfSSL_GetCipherBlockSize(ssl);
+    }
+
+    *padSz  = wolfSSL_GetHmacSize(ssl) + pad + padByte;
+    macInSz = decSz - ivExtra - digestSz - pad - padByte;
+
+    wolfSSL_SetTlsHmacInner(ssl, myInner, macInSz, macContent, macVerify);
+
+    ret = wc_HmacSetKey(&hmac, wolfSSL_GetHmacType(ssl),
+               wolfSSL_GetMacSecret(ssl, macVerify), digestSz);
+    if (ret != 0)
+        return ret;
+    ret = wc_HmacUpdate(&hmac, myInner, sizeof(myInner));
+    if (ret != 0)
+        return ret;
+    ret = wc_HmacUpdate(&hmac, decOut + ivExtra, macInSz);
+    if (ret != 0)
+        return ret;
+    ret = wc_HmacFinal(&hmac, verify);
+    if (ret != 0)
+        return ret;
+
+    if (memcmp(verify, decOut + decSz - digestSz - pad - padByte,
+               digestSz) != 0) {
+        printf("myDecryptVerify verify failed\n");
+        return -1;
+    }
+
+    return ret;
+}
+
+
+static INLINE void SetupAtomicUser(WOLFSSL_CTX* ctx, WOLFSSL* ssl)
+{
+    AtomicEncCtx* encCtx;
+    AtomicDecCtx* decCtx;
+
+    encCtx = (AtomicEncCtx*)malloc(sizeof(AtomicEncCtx));
+    if (encCtx == NULL)
+        err_sys("AtomicEncCtx malloc failed");
+    memset(encCtx, 0, sizeof(AtomicEncCtx));
+
+    decCtx = (AtomicDecCtx*)malloc(sizeof(AtomicDecCtx));
+    if (decCtx == NULL) {
+        free(encCtx);
+        err_sys("AtomicDecCtx malloc failed");
+    }
+    memset(decCtx, 0, sizeof(AtomicDecCtx));
+
+    wolfSSL_CTX_SetMacEncryptCb(ctx, myMacEncryptCb);
+    wolfSSL_SetMacEncryptCtx(ssl, encCtx);
+
+    wolfSSL_CTX_SetDecryptVerifyCb(ctx, myDecryptVerifyCb);
+    wolfSSL_SetDecryptVerifyCtx(ssl, decCtx);
+}
+
+
+static INLINE void FreeAtomicUser(WOLFSSL* ssl)
+{
+    AtomicEncCtx* encCtx = (AtomicEncCtx*)wolfSSL_GetMacEncryptCtx(ssl);
+    AtomicDecCtx* decCtx = (AtomicDecCtx*)wolfSSL_GetDecryptVerifyCtx(ssl);
+
+    free(decCtx);
+    free(encCtx);
+}
+
+#endif /* ATOMIC_USER */
+
+
+#ifdef HAVE_PK_CALLBACKS
+
+#ifdef HAVE_ECC
+
+static INLINE int myEccSign(WOLFSSL* ssl, const byte* in, word32 inSz,
+        byte* out, word32* outSz, const byte* key, word32 keySz, void* ctx)
+{
+    RNG     rng;
+    int     ret;
+    word32  idx = 0;
+    ecc_key myKey;
+
+    (void)ssl;
+    (void)ctx;
+
+    ret = wc_InitRng(&rng);
+    if (ret != 0)
+        return ret;
+
+    wc_ecc_init(&myKey);
+    
+    ret = wc_EccPrivateKeyDecode(key, &idx, &myKey, keySz);    
+    if (ret == 0)
+        ret = wc_ecc_sign_hash(in, inSz, out, outSz, &rng, &myKey);
+    wc_ecc_free(&myKey);
+    wc_FreeRng(&rng);
+
+    return ret;
+}
+
+
+static INLINE int myEccVerify(WOLFSSL* ssl, const byte* sig, word32 sigSz,
+        const byte* hash, word32 hashSz, const byte* key, word32 keySz,
+        int* result, void* ctx)
+{
+    int     ret;
+    ecc_key myKey;
+
+    (void)ssl;
+    (void)ctx;
+
+    wc_ecc_init(&myKey);
+    
+    ret = wc_ecc_import_x963(key, keySz, &myKey);
+    if (ret == 0)
+        ret = wc_ecc_verify_hash(sig, sigSz, hash, hashSz, result, &myKey);
+    wc_ecc_free(&myKey);
+
+    return ret;
+}
+
+#endif /* HAVE_ECC */
+
+#ifndef NO_RSA
+
+static INLINE int myRsaSign(WOLFSSL* ssl, const byte* in, word32 inSz,
+        byte* out, word32* outSz, const byte* key, word32 keySz, void* ctx)
+{
+    RNG     rng;
+    int     ret;
+    word32  idx = 0;
+    RsaKey  myKey;
+
+    (void)ssl;
+    (void)ctx;
+
+    ret = wc_InitRng(&rng);
+    if (ret != 0)
+        return ret;
+
+    wc_InitRsaKey(&myKey, NULL);
+    
+    ret = wc_RsaPrivateKeyDecode(key, &idx, &myKey, keySz);    
+    if (ret == 0)
+        ret = wc_RsaSSL_Sign(in, inSz, out, *outSz, &myKey, &rng);
+    if (ret > 0) {  /* save and convert to 0 success */
+        *outSz = ret;
+        ret = 0;
+    }
+    wc_FreeRsaKey(&myKey);
+    wc_FreeRng(&rng);
+
+    return ret;
+}
+
+
+static INLINE int myRsaVerify(WOLFSSL* ssl, byte* sig, word32 sigSz,
+        byte** out,
+        const byte* key, word32 keySz,
+        void* ctx)
+{
+    int     ret;
+    word32  idx = 0;
+    RsaKey  myKey;
+
+    (void)ssl;
+    (void)ctx;
+
+    wc_InitRsaKey(&myKey, NULL);
+
+    ret = wc_RsaPublicKeyDecode(key, &idx, &myKey, keySz);
+    if (ret == 0)
+        ret = wc_RsaSSL_VerifyInline(sig, sigSz, out, &myKey);
+    wc_FreeRsaKey(&myKey);
+
+    return ret;
+}
+
+
+static INLINE int myRsaEnc(WOLFSSL* ssl, const byte* in, word32 inSz,
+                           byte* out, word32* outSz, const byte* key,
+                           word32 keySz, void* ctx)
+{
+    int     ret;
+    word32  idx = 0;
+    RsaKey  myKey;
+    RNG     rng;
+
+    (void)ssl;
+    (void)ctx;
+
+    ret = wc_InitRng(&rng);
+    if (ret != 0)
+        return ret;
+
+    wc_InitRsaKey(&myKey, NULL);
+    
+    ret = wc_RsaPublicKeyDecode(key, &idx, &myKey, keySz);
+    if (ret == 0) {
+        ret = wc_RsaPublicEncrypt(in, inSz, out, *outSz, &myKey, &rng);
+        if (ret > 0) {
+            *outSz = ret;
+            ret = 0;  /* reset to success */
+        }
+    }
+    wc_FreeRsaKey(&myKey);
+    wc_FreeRng(&rng);
+
+    return ret;
+}
+
+static INLINE int myRsaDec(WOLFSSL* ssl, byte* in, word32 inSz,
+                           byte** out,
+                           const byte* key, word32 keySz, void* ctx)
+{
+    int     ret;
+    word32  idx = 0;
+    RsaKey  myKey;
+
+    (void)ssl;
+    (void)ctx;
+
+    wc_InitRsaKey(&myKey, NULL);
+
+    ret = wc_RsaPrivateKeyDecode(key, &idx, &myKey, keySz);
+    if (ret == 0) {
+        ret = wc_RsaPrivateDecryptInline(in, inSz, out, &myKey);
+    }
+    wc_FreeRsaKey(&myKey);
+
+    return ret;
+}
+
+#endif /* NO_RSA */
+
+static INLINE void SetupPkCallbacks(WOLFSSL_CTX* ctx, WOLFSSL* ssl)
+{
+    (void)ctx;
+    (void)ssl;
+
+    #ifdef HAVE_ECC
+        wolfSSL_CTX_SetEccSignCb(ctx, myEccSign);
+        wolfSSL_CTX_SetEccVerifyCb(ctx, myEccVerify);
+    #endif /* HAVE_ECC */
+    #ifndef NO_RSA 
+        wolfSSL_CTX_SetRsaSignCb(ctx, myRsaSign);
+        wolfSSL_CTX_SetRsaVerifyCb(ctx, myRsaVerify);
+        wolfSSL_CTX_SetRsaEncCb(ctx, myRsaEnc);
+        wolfSSL_CTX_SetRsaDecCb(ctx, myRsaDec);
+    #endif /* NO_RSA */
+}
+
+#endif /* HAVE_PK_CALLBACKS */
+
+
+
+
+
+#if defined(__hpux__) || defined(__MINGW32__) || defined (WOLFSSL_TIRTOS) \
+                      || defined(_MSC_VER)
+
+/* HP/UX doesn't have strsep, needed by test/suites.c */
+static INLINE char* strsep(char **stringp, const char *delim)
+{
+    char* start;
+    char* end;
+
+    start = *stringp;
+    if (start == NULL)
+        return NULL;
+
+    if ((end = strpbrk(start, delim))) {
+        *end++ = '\0';
+        *stringp = end;
+    } else {
+        *stringp = NULL;
+    }
+
+    return start;
+}
+
+#endif /* __hpux__ and others */
+
+/* Create unique filename, len is length of tempfn name, assuming
+   len does not include null terminating character,
+   num is number of characters in tempfn name to randomize */
+static INLINE const char* mymktemp(char *tempfn, int len, int num)
+{
+    int x, size;
+    static const char alphanum[] = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"
+                                   "abcdefghijklmnopqrstuvwxyz";
+    RNG rng;
+    byte out;
+
+    if (tempfn == NULL || len < 1 || num < 1 || len <= num) {
+        printf("Bad input\n");
+        return NULL;
+    }
+
+    size = len - 1;
+
+    if (wc_InitRng(&rng) != 0) {
+        printf("InitRng failed\n");
+        return NULL;
+    }
+
+    for (x = size; x > size - num; x--) {
+        if (wc_RNG_GenerateBlock(&rng,(byte*)&out, sizeof(out)) != 0) {
+            printf("RNG_GenerateBlock failed\n");
+            return NULL;
+        }
+        tempfn[x] = alphanum[out % (sizeof(alphanum) - 1)];
+    }
+    tempfn[len] = '\0';
+
+    wc_FreeRng(&rng);
+
+    return tempfn;
+}
+
+
+
+#if defined(HAVE_SESSION_TICKET) && defined(HAVE_CHACHA) && \
+                                    defined(HAVE_POLY1305)
+
+    #include 
+
+    typedef struct key_ctx {
+        byte name[WOLFSSL_TICKET_NAME_SZ];     /* name for this context */
+        byte key[16];                          /* cipher key */
+    } key_ctx;
+
+    static key_ctx myKey_ctx;
+    static RNG rng;
+
+    static INLINE int TicketInit(void)
+    {
+        int ret = wc_InitRng(&rng);
+        if (ret != 0) return ret;
+
+        ret = wc_RNG_GenerateBlock(&rng, myKey_ctx.key, sizeof(myKey_ctx.key));
+        if (ret != 0) return ret;
+
+        ret = wc_RNG_GenerateBlock(&rng, myKey_ctx.name,sizeof(myKey_ctx.name));
+        if (ret != 0) return ret;
+
+        return 0;
+    }
+
+    static INLINE void TicketCleanup(void)
+    {
+        wc_FreeRng(&rng);
+    }
+
+    static INLINE int myTicketEncCb(WOLFSSL* ssl,
+                             byte key_name[WOLFSSL_TICKET_NAME_SZ],
+                             byte iv[WOLFSSL_TICKET_IV_SZ],
+                             byte mac[WOLFSSL_TICKET_MAC_SZ],
+                             int enc, byte* ticket, int inLen, int* outLen,
+                             void* userCtx)
+    {
+        (void)ssl;
+        (void)userCtx;
+
+        int ret;
+        word16 sLen = htons(inLen);
+        byte aad[WOLFSSL_TICKET_NAME_SZ + WOLFSSL_TICKET_IV_SZ + 2];
+        int  aadSz = WOLFSSL_TICKET_NAME_SZ + WOLFSSL_TICKET_IV_SZ + 2;
+        byte* tmp = aad;
+
+        if (enc) {
+            XMEMCPY(key_name, myKey_ctx.name, WOLFSSL_TICKET_NAME_SZ);
+
+            ret = wc_RNG_GenerateBlock(&rng, iv, WOLFSSL_TICKET_IV_SZ);
+            if (ret != 0) return WOLFSSL_TICKET_RET_REJECT;
+
+            /* build aad from key name, iv, and length */
+            XMEMCPY(tmp, key_name, WOLFSSL_TICKET_NAME_SZ);
+            tmp += WOLFSSL_TICKET_NAME_SZ;
+            XMEMCPY(tmp, iv, WOLFSSL_TICKET_IV_SZ);
+            tmp += WOLFSSL_TICKET_IV_SZ;
+            XMEMCPY(tmp, &sLen, 2);
+
+            ret = wc_ChaCha20Poly1305_Encrypt(myKey_ctx.key, iv,
+                                              aad, aadSz,
+                                              ticket, inLen,
+                                              ticket,
+                                              mac);
+            if (ret != 0) return WOLFSSL_TICKET_RET_REJECT;
+            *outLen = inLen;  /* no padding in this mode */
+        } else {
+            /* decrypt */
+
+            /* see if we know this key */
+            if (XMEMCMP(key_name, myKey_ctx.name, WOLFSSL_TICKET_NAME_SZ) != 0){
+                printf("client presented unknown ticket key name ");
+                return WOLFSSL_TICKET_RET_FATAL;
+            }
+
+            /* build aad from key name, iv, and length */
+            XMEMCPY(tmp, key_name, WOLFSSL_TICKET_NAME_SZ);
+            tmp += WOLFSSL_TICKET_NAME_SZ;
+            XMEMCPY(tmp, iv, WOLFSSL_TICKET_IV_SZ);
+            tmp += WOLFSSL_TICKET_IV_SZ;
+            XMEMCPY(tmp, &sLen, 2);
+
+            ret = wc_ChaCha20Poly1305_Decrypt(myKey_ctx.key, iv,
+                                              aad, aadSz,
+                                              ticket, inLen,
+                                              mac,
+                                              ticket);
+            if (ret != 0) return WOLFSSL_TICKET_RET_REJECT;
+            *outLen = inLen;  /* no padding in this mode */
+        }
+
+        return WOLFSSL_TICKET_RET_OK;
+    }
+
+#endif  /* HAVE_SESSION_TICKET && CHACHA20 && POLY1305 */
+
+#endif /* wolfSSL_TEST_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/version.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/version.h
new file mode 100644
index 0000000..b163a0a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/version.h
@@ -0,0 +1,35 @@
+/* wolfssl_version.h.in
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LIBWOLFSSL_VERSION_STRING "3.6.0"
+#define LIBWOLFSSL_VERSION_HEX 0x03006000
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/version.h.in b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/version.h.in
new file mode 100644
index 0000000..966ff5a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/version.h.in
@@ -0,0 +1,35 @@
+/* wolfssl_version.h.in
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LIBWOLFSSL_VERSION_STRING "@VERSION@"
+#define LIBWOLFSSL_VERSION_HEX @HEX_VERSION@
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/aes.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/aes.h
new file mode 100644
index 0000000..a94ad08
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/aes.h
@@ -0,0 +1,188 @@
+/* aes.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_AES_H
+#define WOLF_CRYPT_AES_H
+
+#include 
+
+#ifndef NO_AES
+
+/* included for fips @wc_fips */
+#ifdef HAVE_FIPS
+#include 
+#if defined(CYASSL_AES_COUNTER) && !defined(WOLFSSL_AES_COUNTER)
+    #define WOLFSSL_AES_COUNTER
+#endif
+#if !defined(WOLFSSL_AES_DIRECT) && defined(CYASSL_AES_DIRECT)
+    #define WOLFSSL_AES_DIRECT
+#endif
+#endif
+
+#ifndef HAVE_FIPS /* to avoid redefinition of macros */
+#ifdef HAVE_CAVIUM
+    #include 
+    #include "cavium_common.h"
+#endif
+
+#ifdef WOLFSSL_AESNI
+
+#include 
+
+#if !defined (ALIGN16)
+    #if defined (__GNUC__)
+        #define ALIGN16 __attribute__ ( (aligned (16)))
+    #elif defined(_MSC_VER)
+        /* disable align warning, we want alignment ! */
+        #pragma warning(disable: 4324)
+        #define ALIGN16 __declspec (align (16))
+    #else
+        #define ALIGN16
+    #endif
+#endif
+
+#endif /* WOLFSSL_AESNI */
+
+#if !defined (ALIGN16)
+    #define ALIGN16
+#endif
+#endif /* HAVE_FIPS */
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#ifndef HAVE_FIPS /* to avoid redefinition of structures */
+#define WOLFSSL_AES_CAVIUM_MAGIC 0xBEEF0002
+
+enum {
+    AES_ENC_TYPE   = 1,   /* cipher unique type */
+    AES_ENCRYPTION = 0,
+    AES_DECRYPTION = 1,
+    AES_BLOCK_SIZE = 16
+};
+
+
+typedef struct Aes {
+    /* AESNI needs key first, rounds 2nd, not sure why yet */
+    ALIGN16 word32 key[60];
+    word32  rounds;
+
+    ALIGN16 word32 reg[AES_BLOCK_SIZE / sizeof(word32)];      /* for CBC mode */
+    ALIGN16 word32 tmp[AES_BLOCK_SIZE / sizeof(word32)];      /* same         */
+
+#ifdef HAVE_AESGCM
+    ALIGN16 byte H[AES_BLOCK_SIZE];
+#ifdef GCM_TABLE
+    /* key-based fast multiplication table. */
+    ALIGN16 byte M0[256][AES_BLOCK_SIZE];
+#endif /* GCM_TABLE */
+#endif /* HAVE_AESGCM */
+#ifdef WOLFSSL_AESNI
+    byte use_aesni;
+#endif /* WOLFSSL_AESNI */
+#ifdef HAVE_CAVIUM
+    AesType type;            /* aes key type */
+    int     devId;           /* nitrox device id */
+    word32  magic;           /* using cavium magic */
+    word64  contextHandle;   /* nitrox context memory handle */
+#endif
+#ifdef WOLFSSL_AES_COUNTER
+    word32  left;            /* unsued bytes left from last call */
+#endif
+#ifdef WOLFSSL_PIC32MZ_CRYPT
+    word32 key_ce[AES_BLOCK_SIZE*2/sizeof(word32)] ;
+    word32 iv_ce [AES_BLOCK_SIZE  /sizeof(word32)] ;
+    int    keylen ;
+#endif
+#ifdef WOLFSSL_TI_CRYPT
+    int    keylen ;
+#endif
+} Aes;
+
+
+#ifdef HAVE_AESGCM
+typedef struct Gmac {
+    Aes aes;
+} Gmac;
+#endif /* HAVE_AESGCM */
+#endif /* HAVE_FIPS */
+
+ WOLFSSL_API int  wc_AesSetKey(Aes* aes, const byte* key, word32 len, const byte* iv,
+                          int dir);
+ WOLFSSL_API int  wc_AesSetIV(Aes* aes, const byte* iv);
+ WOLFSSL_API int  wc_AesCbcEncrypt(Aes* aes, byte* out, const byte* in, word32 sz);
+ WOLFSSL_API int  wc_AesCbcDecrypt(Aes* aes, byte* out, const byte* in, word32 sz);
+ WOLFSSL_API int  wc_AesCbcDecryptWithKey(byte* out, const byte* in, word32 inSz,
+                                 const byte* key, word32 keySz, const byte* iv);
+
+/* AES-CTR */
+#ifdef WOLFSSL_AES_COUNTER
+ WOLFSSL_API void wc_AesCtrEncrypt(Aes* aes, byte* out, const byte* in, word32 sz);
+#endif
+/* AES-DIRECT */
+#if defined(WOLFSSL_AES_DIRECT)
+ WOLFSSL_API void wc_AesEncryptDirect(Aes* aes, byte* out, const byte* in);
+ WOLFSSL_API void wc_AesDecryptDirect(Aes* aes, byte* out, const byte* in);
+ WOLFSSL_API int  wc_AesSetKeyDirect(Aes* aes, const byte* key, word32 len,
+                                const byte* iv, int dir);
+#endif
+#ifdef HAVE_AESGCM
+ WOLFSSL_API int  wc_AesGcmSetKey(Aes* aes, const byte* key, word32 len);
+ WOLFSSL_API int  wc_AesGcmEncrypt(Aes* aes, byte* out, const byte* in, word32 sz,
+                              const byte* iv, word32 ivSz,
+                              byte* authTag, word32 authTagSz,
+                              const byte* authIn, word32 authInSz);
+ WOLFSSL_API int  wc_AesGcmDecrypt(Aes* aes, byte* out, const byte* in, word32 sz,
+                              const byte* iv, word32 ivSz,
+                              const byte* authTag, word32 authTagSz,
+                              const byte* authIn, word32 authInSz);
+
+ WOLFSSL_API int wc_GmacSetKey(Gmac* gmac, const byte* key, word32 len);
+ WOLFSSL_API int wc_GmacUpdate(Gmac* gmac, const byte* iv, word32 ivSz,
+                              const byte* authIn, word32 authInSz,
+                              byte* authTag, word32 authTagSz);
+#endif /* HAVE_AESGCM */
+#ifdef HAVE_AESCCM
+ WOLFSSL_API void wc_AesCcmSetKey(Aes* aes, const byte* key, word32 keySz);
+ WOLFSSL_API void wc_AesCcmEncrypt(Aes* aes, byte* out, const byte* in, word32 inSz,
+                              const byte* nonce, word32 nonceSz,
+                              byte* authTag, word32 authTagSz,
+                              const byte* authIn, word32 authInSz);
+ WOLFSSL_API int  wc_AesCcmDecrypt(Aes* aes, byte* out, const byte* in, word32 inSz,
+                              const byte* nonce, word32 nonceSz,
+                              const byte* authTag, word32 authTagSz,
+                              const byte* authIn, word32 authInSz);
+#endif /* HAVE_AESCCM */
+
+#ifdef HAVE_CAVIUM
+     WOLFSSL_API int  wc_AesInitCavium(Aes*, int);
+     WOLFSSL_API void wc_AesFreeCavium(Aes*);
+#endif
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+
+#endif /* NO_AES */
+#endif /* WOLF_CRYPT_AES_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/arc4.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/arc4.h
new file mode 100644
index 0000000..727b627
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/arc4.h
@@ -0,0 +1,65 @@
+/* arc4.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifndef WOLF_CRYPT_ARC4_H
+#define WOLF_CRYPT_ARC4_H
+
+#include 
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#define WOLFSSL_ARC4_CAVIUM_MAGIC 0xBEEF0001
+
+enum {
+	ARC4_ENC_TYPE   = 4,    /* cipher unique type */
+    ARC4_STATE_SIZE = 256
+};
+
+/* ARC4 encryption and decryption */
+typedef struct Arc4 {
+    byte x;
+    byte y;
+    byte state[ARC4_STATE_SIZE];
+#ifdef HAVE_CAVIUM
+    int    devId;           /* nitrox device id */
+    word32 magic;           /* using cavium magic */
+    word64 contextHandle;   /* nitrox context memory handle */
+#endif
+} Arc4;
+
+WOLFSSL_API void wc_Arc4Process(Arc4*, byte*, const byte*, word32);
+WOLFSSL_API void wc_Arc4SetKey(Arc4*, const byte*, word32);
+
+#ifdef HAVE_CAVIUM
+    WOLFSSL_API int  wc_Arc4InitCavium(Arc4*, int);
+    WOLFSSL_API void wc_Arc4FreeCavium(Arc4*);
+#endif
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+
+#endif /* WOLF_CRYPT_ARC4_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/asn.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/asn.h
new file mode 100644
index 0000000..10d0943
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/asn.h
@@ -0,0 +1,742 @@
+/* asn.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_ASN_H
+#define WOLF_CRYPT_ASN_H
+
+#include 
+
+#ifndef NO_ASN
+
+#include 
+#ifndef NO_RSA
+    #include 
+#endif
+
+/* fips declare of RsaPrivateKeyDecode @wc_fips */
+#if defined(HAVE_FIPS) && !defined(NO_RSA)
+    #include 
+#endif
+
+#ifndef NO_DH
+    #include 
+#endif
+#ifndef NO_DSA
+    #include 
+#endif
+#ifndef NO_SHA
+    #include 
+#endif
+#ifndef NO_MD5
+    #include 
+#endif
+#include 
+#include    /* public interface */
+#ifdef HAVE_ECC
+    #include 
+#endif
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+
+enum {
+    ISSUER  = 0,
+    SUBJECT = 1,
+
+    EXTERNAL_SERIAL_SIZE = 32,
+
+    BEFORE  = 0,
+    AFTER   = 1
+};
+
+/* ASN Tags   */
+enum ASN_Tags {
+    ASN_BOOLEAN           = 0x01,
+    ASN_INTEGER           = 0x02,
+    ASN_BIT_STRING        = 0x03,
+    ASN_OCTET_STRING      = 0x04,
+    ASN_TAG_NULL          = 0x05,
+    ASN_OBJECT_ID         = 0x06,
+    ASN_ENUMERATED        = 0x0a,
+    ASN_UTF8STRING        = 0x0c,
+    ASN_SEQUENCE          = 0x10,
+    ASN_SET               = 0x11,
+    ASN_UTC_TIME          = 0x17,
+    ASN_OTHER_TYPE        = 0x00,
+    ASN_RFC822_TYPE       = 0x01,
+    ASN_DNS_TYPE          = 0x02,
+    ASN_DIR_TYPE          = 0x04,
+    ASN_GENERALIZED_TIME  = 0x18,
+    CRL_EXTENSIONS        = 0xa0,
+    ASN_EXTENSIONS        = 0xa3,
+    ASN_LONG_LENGTH       = 0x80
+};
+
+enum  ASN_Flags{
+    ASN_CONSTRUCTED       = 0x20,
+    ASN_CONTEXT_SPECIFIC  = 0x80
+};
+
+enum DN_Tags {
+    ASN_COMMON_NAME   = 0x03,   /* CN */
+    ASN_SUR_NAME      = 0x04,   /* SN */
+    ASN_SERIAL_NUMBER = 0x05,   /* serialNumber */
+    ASN_COUNTRY_NAME  = 0x06,   /* C  */
+    ASN_LOCALITY_NAME = 0x07,   /* L  */
+    ASN_STATE_NAME    = 0x08,   /* ST */
+    ASN_ORG_NAME      = 0x0a,   /* O  */
+    ASN_ORGUNIT_NAME  = 0x0b    /* OU */
+};
+
+enum PBES {
+    PBE_MD5_DES      = 0,
+    PBE_SHA1_DES     = 1,
+    PBE_SHA1_DES3    = 2,
+    PBE_SHA1_RC4_128 = 3,
+    PBES2            = 13       /* algo ID */
+};
+
+enum ENCRYPTION_TYPES {
+    DES_TYPE  = 0,
+    DES3_TYPE = 1,
+    RC4_TYPE  = 2
+};
+
+enum ECC_TYPES {
+    ECC_PREFIX_0 = 160,
+    ECC_PREFIX_1 = 161
+};
+
+enum Misc_ASN {
+    ASN_NAME_MAX        = 256,
+    MAX_SALT_SIZE       =  64,     /* MAX PKCS Salt length */
+    MAX_IV_SIZE         =  64,     /* MAX PKCS Iv length */
+    MAX_KEY_SIZE        =  64,     /* MAX PKCS Key  length */
+    PKCS5               =   5,     /* PKCS oid tag */
+    PKCS5v2             =   6,     /* PKCS #5 v2.0 */
+    PKCS12              =  12,     /* PKCS #12 */
+    MAX_UNICODE_SZ      = 256,
+    ASN_BOOL_SIZE       =   2,     /* including type */
+    ASN_ECC_HEADER_SZ   =   2,     /* String type + 1 byte len */
+    ASN_ECC_CONTEXT_SZ  =   2,     /* Content specific type + 1 byte len */
+#ifdef NO_SHA
+    KEYID_SIZE          = SHA256_DIGEST_SIZE,
+#else
+    KEYID_SIZE          = SHA_DIGEST_SIZE,
+#endif
+    RSA_INTS            =   8,     /* RSA ints in private key */
+    MIN_DATE_SIZE       =  13,
+    MAX_DATE_SIZE       =  32,
+    ASN_GEN_TIME_SZ     =  15,     /* 7 numbers * 2 + Zulu tag */
+    MAX_ENCODED_SIG_SZ  = 512,
+    MAX_SIG_SZ          = 256,
+    MAX_ALGO_SZ         =  20,
+    MAX_SEQ_SZ          =   5,     /* enum(seq | con) + length(4) */
+    MAX_SET_SZ          =   5,     /* enum(set | con) + length(4) */
+    MAX_OCTET_STR_SZ    =   5,     /* enum(set | con) + length(4) */
+    MAX_EXP_SZ          =   5,     /* enum(contextspec|con|exp) + length(4) */
+    MAX_PRSTR_SZ        =   5,     /* enum(prstr) + length(4) */
+    MAX_VERSION_SZ      =   5,     /* enum + id + version(byte) + (header(2))*/
+    MAX_ENCODED_DIG_SZ  =  73,     /* sha512 + enum(bit or octet) + legnth(4) */
+    MAX_RSA_INT_SZ      = 517,     /* RSA raw sz 4096 for bits + tag + len(4) */
+    MAX_NTRU_KEY_SZ     = 610,     /* NTRU 112 bit public key */
+    MAX_NTRU_ENC_SZ     = 628,     /* NTRU 112 bit DER public encoding */
+    MAX_LENGTH_SZ       =   4,     /* Max length size for DER encoding */
+    MAX_RSA_E_SZ        =  16,     /* Max RSA public e size */
+    MAX_CA_SZ           =  32,     /* Max encoded CA basic constraint length */
+    MAX_SN_SZ           =  35,     /* Max encoded serial number (INT) length */
+#ifdef WOLFSSL_CERT_GEN
+    #ifdef WOLFSSL_CERT_REQ
+                          /* Max encoded cert req attributes length */
+        MAX_ATTRIB_SZ   = MAX_SEQ_SZ * 3 + (11 + MAX_SEQ_SZ) * 2 +
+                          MAX_PRSTR_SZ + CTC_NAME_SIZE, /* 11 is the OID size */
+    #endif
+    #ifdef WOLFSSL_ALT_NAMES
+        MAX_EXTENSIONS_SZ   = 1 + MAX_LENGTH_SZ + CTC_MAX_ALT_SIZE,
+    #else
+        MAX_EXTENSIONS_SZ   = 1 + MAX_LENGTH_SZ + MAX_CA_SZ,
+    #endif
+                                   /* Max total extensions, id + len + others */
+#endif
+    MAX_OCSP_EXT_SZ     = 58,      /* Max OCSP Extension length */
+    MAX_OCSP_NONCE_SZ   = 18,      /* OCSP Nonce size           */
+    EIGHTK_BUF          = 8192,    /* Tmp buffer size           */
+    MAX_PUBLIC_KEY_SZ   = MAX_NTRU_ENC_SZ + MAX_ALGO_SZ + MAX_SEQ_SZ * 2
+                                   /* use bigger NTRU size */
+};
+
+
+enum Oid_Types {
+    hashType  = 0,
+    sigType   = 1,
+    keyType   = 2,
+    curveType = 3,
+    blkType   = 4
+};
+
+
+enum Hash_Sum  {
+    MD2h    = 646,
+    MD5h    = 649,
+    SHAh    =  88,
+    SHA256h = 414,
+    SHA384h = 415,
+    SHA512h = 416
+};
+
+
+enum Block_Sum {
+    DESb  = 69,
+    DES3b = 652
+};
+
+
+enum Key_Sum {
+    DSAk   = 515,
+    RSAk   = 645,
+    NTRUk  = 274,
+    ECDSAk = 518
+};
+
+
+enum Ecc_Sum {
+    ECC_256R1 = 526,
+    ECC_384R1 = 210,
+    ECC_521R1 = 211,
+    ECC_160R1 = 184,
+    ECC_192R1 = 520,
+    ECC_224R1 = 209
+};
+
+
+enum KDF_Sum {
+    PBKDF2_OID = 660
+};
+
+
+enum Extensions_Sum {
+    BASIC_CA_OID    = 133,
+    ALT_NAMES_OID   = 131,
+    CRL_DIST_OID    = 145,
+    AUTH_INFO_OID   = 69,
+    CA_ISSUER_OID   = 117,
+    AUTH_KEY_OID    = 149,
+    SUBJ_KEY_OID    = 128,
+    CERT_POLICY_OID = 146,
+    KEY_USAGE_OID   = 129,  /* 2.5.29.15 */
+    INHIBIT_ANY_OID = 168,  /* 2.5.29.54 */
+    EXT_KEY_USAGE_OID = 151, /* 2.5.29.37 */
+    NAME_CONS_OID   = 144   /* 2.5.29.30 */
+};
+
+enum CertificatePolicy_Sum {
+    CP_ANY_OID      = 146  /* id-ce 32 0 */
+};
+
+enum SepHardwareName_Sum {
+    HW_NAME_OID     = 79   /* 1.3.6.1.5.5.7.8.4 from RFC 4108*/
+};
+
+enum AuthInfo_Sum {
+    AIA_OCSP_OID      = 116, /* 1.3.6.1.5.5.7.48.1 */
+    AIA_CA_ISSUER_OID = 117  /* 1.3.6.1.5.5.7.48.2 */
+};
+
+enum ExtKeyUsage_Sum { /* From RFC 5280 */
+    EKU_ANY_OID         = 151, /* 2.5.29.37.0, anyExtendedKeyUsage         */
+    EKU_SERVER_AUTH_OID = 71,  /* 1.3.6.1.5.5.7.3.1, id-kp-serverAuth      */
+    EKU_CLIENT_AUTH_OID = 72,  /* 1.3.6.1.5.5.7.3.2, id-kp-clientAuth      */
+    EKU_OCSP_SIGN_OID   = 79   /* 1.3.6.1.5.5.7.3.9, OCSPSigning           */
+};
+
+
+enum VerifyType {
+    NO_VERIFY = 0,
+    VERIFY    = 1
+};
+
+
+/* Key usage extension bits */
+#define KEYUSE_DIGITAL_SIG    0x0100
+#define KEYUSE_CONTENT_COMMIT 0x0080
+#define KEYUSE_KEY_ENCIPHER   0x0040
+#define KEYUSE_DATA_ENCIPHER  0x0020
+#define KEYUSE_KEY_AGREE      0x0010
+#define KEYUSE_KEY_CERT_SIGN  0x0008
+#define KEYUSE_CRL_SIGN       0x0004
+#define KEYUSE_ENCIPHER_ONLY  0x0002
+#define KEYUSE_DECIPHER_ONLY  0x0001
+
+#define EXTKEYUSE_ANY         0x08
+#define EXTKEYUSE_OCSP_SIGN   0x04
+#define EXTKEYUSE_CLIENT_AUTH 0x02
+#define EXTKEYUSE_SERVER_AUTH 0x01
+
+typedef struct DNS_entry   DNS_entry;
+
+struct DNS_entry {
+    DNS_entry* next;   /* next on DNS list */
+    char*      name;   /* actual DNS name */
+};
+
+
+typedef struct Base_entry  Base_entry;
+
+struct Base_entry {
+    Base_entry* next;   /* next on name base list */
+    char*       name;   /* actual name base */
+    int         nameSz; /* name length */
+    byte        type;   /* Name base type (DNS or RFC822) */
+};
+
+
+struct DecodedName {
+    char*   fullName;
+    int     fullNameLen;
+    int     entryCount;
+    int     cnIdx;
+    int     cnLen;
+    int     snIdx;
+    int     snLen;
+    int     cIdx;
+    int     cLen;
+    int     lIdx;
+    int     lLen;
+    int     stIdx;
+    int     stLen;
+    int     oIdx;
+    int     oLen;
+    int     ouIdx;
+    int     ouLen;
+    int     emailIdx;
+    int     emailLen;
+    int     uidIdx;
+    int     uidLen;
+    int     serialIdx;
+    int     serialLen;
+};
+
+
+typedef struct DecodedCert DecodedCert;
+typedef struct DecodedName DecodedName;
+typedef struct Signer      Signer;
+
+
+struct DecodedCert {
+    byte*   publicKey;
+    word32  pubKeySize;
+    int     pubKeyStored;
+    word32  certBegin;               /* offset to start of cert          */
+    word32  sigIndex;                /* offset to start of signature     */
+    word32  sigLength;               /* length of signature              */
+    word32  signatureOID;            /* sum of algorithm object id       */
+    word32  keyOID;                  /* sum of key algo  object id       */
+    int     version;                 /* cert version, 1 or 3             */
+    DNS_entry* altNames;             /* alt names list of dns entries    */
+#ifndef IGNORE_NAME_CONSTRAINTS
+    DNS_entry* altEmailNames;        /* alt names list of RFC822 entries */
+    Base_entry* permittedNames;      /* Permitted name bases             */
+    Base_entry* excludedNames;       /* Excluded name bases              */
+#endif /* IGNORE_NAME_CONSTRAINTS */
+    byte    subjectHash[KEYID_SIZE]; /* hash of all Names                */
+    byte    issuerHash[KEYID_SIZE];  /* hash of all Names                */
+#ifdef HAVE_OCSP
+    byte    issuerKeyHash[KEYID_SIZE]; /* hash of the public Key         */
+#endif /* HAVE_OCSP */
+    byte*   signature;               /* not owned, points into raw cert  */
+    char*   subjectCN;               /* CommonName                       */
+    int     subjectCNLen;            /* CommonName Length                */
+    char    subjectCNEnc;            /* CommonName Encoding              */
+    int     subjectCNStored;         /* have we saved a copy we own      */
+    char    issuer[ASN_NAME_MAX];    /* full name including common name  */
+    char    subject[ASN_NAME_MAX];   /* full name including common name  */
+    int     verify;                  /* Default to yes, but could be off */
+    byte*   source;                  /* byte buffer holder cert, NOT owner */
+    word32  srcIdx;                  /* current offset into buffer       */
+    word32  maxIdx;                  /* max offset based on init size    */
+    void*   heap;                    /* for user memory overrides        */
+    byte    serial[EXTERNAL_SERIAL_SIZE];  /* raw serial number          */
+    int     serialSz;                /* raw serial bytes stored */
+    byte*   extensions;              /* not owned, points into raw cert  */
+    int     extensionsSz;            /* length of cert extensions */
+    word32  extensionsIdx;           /* if want to go back and parse later */
+    byte*   extAuthInfo;             /* Authority Information Access URI */
+    int     extAuthInfoSz;           /* length of the URI                */
+    byte*   extCrlInfo;              /* CRL Distribution Points          */
+    int     extCrlInfoSz;            /* length of the URI                */
+    byte    extSubjKeyId[KEYID_SIZE]; /* Subject Key ID                  */
+    byte    extSubjKeyIdSet;         /* Set when the SKID was read from cert */
+    byte    extAuthKeyId[KEYID_SIZE]; /* Authority Key ID                */
+    byte    extAuthKeyIdSet;         /* Set when the AKID was read from cert */
+#ifndef IGNORE_NAME_CONSTRAINTS
+    byte    extNameConstraintSet;
+#endif /* IGNORE_NAME_CONSTRAINTS */
+    byte    isCA;                    /* CA basic constraint true         */
+    byte    weOwnAltNames;           /* altNames haven't been given to copy */
+    byte    extKeyUsageSet;
+    word16  extKeyUsage;             /* Key usage bitfield               */
+    byte    extExtKeyUsageSet;       /* Extended Key Usage               */
+    byte    extExtKeyUsage;          /* Extended Key usage bitfield      */
+#ifdef OPENSSL_EXTRA
+    byte    extBasicConstSet;
+    byte    extBasicConstCrit;
+    byte    extBasicConstPlSet;
+    word32  pathLength;              /* CA basic constraint path length, opt */
+    byte    extSubjAltNameSet;
+    byte    extSubjAltNameCrit;
+    byte    extAuthKeyIdCrit;
+#ifndef IGNORE_NAME_CONSTRAINTS
+    byte    extNameConstraintCrit;
+#endif /* IGNORE_NAME_CONSTRAINTS */
+    byte    extSubjKeyIdCrit;
+    byte    extKeyUsageCrit;
+    byte    extExtKeyUsageCrit;
+    byte*   extExtKeyUsageSrc;
+    word32  extExtKeyUsageSz;
+    word32  extExtKeyUsageCount;
+    byte*   extAuthKeyIdSrc;
+    word32  extAuthKeyIdSz;
+    byte*   extSubjKeyIdSrc;
+    word32  extSubjKeyIdSz;
+#endif
+#ifdef HAVE_ECC
+    word32  pkCurveOID;           /* Public Key's curve OID */
+#endif /* HAVE_ECC */
+    byte*   beforeDate;
+    int     beforeDateLen;
+    byte*   afterDate;
+    int     afterDateLen;
+#ifdef HAVE_PKCS7
+    byte*   issuerRaw;               /* pointer to issuer inside source */
+    int     issuerRawLen;
+#endif
+#ifndef IGNORE_NAME_CONSTRAINT
+    byte*   subjectRaw;               /* pointer to subject inside source */
+    int     subjectRawLen;
+#endif
+#if defined(WOLFSSL_CERT_GEN)
+    /* easy access to subject info for other sign */
+    char*   subjectSN;
+    int     subjectSNLen;
+    char    subjectSNEnc;
+    char*   subjectC;
+    int     subjectCLen;
+    char    subjectCEnc;
+    char*   subjectL;
+    int     subjectLLen;
+    char    subjectLEnc;
+    char*   subjectST;
+    int     subjectSTLen;
+    char    subjectSTEnc;
+    char*   subjectO;
+    int     subjectOLen;
+    char    subjectOEnc;
+    char*   subjectOU;
+    int     subjectOULen;
+    char    subjectOUEnc;
+    char*   subjectEmail;
+    int     subjectEmailLen;
+#endif /* WOLFSSL_CERT_GEN */
+#ifdef OPENSSL_EXTRA
+    DecodedName issuerName;
+    DecodedName subjectName;
+#endif /* OPENSSL_EXTRA */
+#ifdef WOLFSSL_SEP
+    int     deviceTypeSz;
+    byte*   deviceType;
+    int     hwTypeSz;
+    byte*   hwType;
+    int     hwSerialNumSz;
+    byte*   hwSerialNum;
+    #ifdef OPENSSL_EXTRA
+        byte    extCertPolicySet;
+        byte    extCertPolicyCrit;
+    #endif /* OPENSSL_EXTRA */
+#endif /* WOLFSSL_SEP */
+};
+
+
+#ifdef NO_SHA
+    #define SIGNER_DIGEST_SIZE SHA256_DIGEST_SIZE
+#else
+    #define SIGNER_DIGEST_SIZE SHA_DIGEST_SIZE
+#endif
+
+/* CA Signers */
+/* if change layout change PERSIST_CERT_CACHE functions too */
+struct Signer {
+    word32  pubKeySize;
+    word32  keyOID;                  /* key type */
+    word16  keyUsage;
+    byte*   publicKey;
+    int     nameLen;
+    char*   name;                    /* common name */
+#ifndef IGNORE_NAME_CONSTRAINTS
+        Base_entry* permittedNames;
+        Base_entry* excludedNames;
+#endif /* IGNORE_NAME_CONSTRAINTS */
+    byte    subjectNameHash[SIGNER_DIGEST_SIZE];
+                                     /* sha hash of names in certificate */
+    #ifndef NO_SKID
+        byte    subjectKeyIdHash[SIGNER_DIGEST_SIZE];
+                                     /* sha hash of names in certificate */
+    #endif
+    Signer* next;
+};
+
+
+/* not for public consumption but may use for testing sometimes */
+#ifdef WOLFSSL_TEST_CERT
+    #define WOLFSSL_TEST_API WOLFSSL_API
+#else
+    #define WOLFSSL_TEST_API WOLFSSL_LOCAL
+#endif
+
+WOLFSSL_TEST_API void FreeAltNames(DNS_entry*, void*);
+#ifndef IGNORE_NAME_CONSTRAINTS
+    WOLFSSL_TEST_API void FreeNameSubtrees(Base_entry*, void*);
+#endif /* IGNORE_NAME_CONSTRAINTS */
+WOLFSSL_TEST_API void InitDecodedCert(DecodedCert*, byte*, word32, void*);
+WOLFSSL_TEST_API void FreeDecodedCert(DecodedCert*);
+WOLFSSL_TEST_API int  ParseCert(DecodedCert*, int type, int verify, void* cm);
+
+WOLFSSL_LOCAL int ParseCertRelative(DecodedCert*, int type, int verify,void* cm);
+WOLFSSL_LOCAL int DecodeToKey(DecodedCert*, int verify);
+
+WOLFSSL_LOCAL Signer* MakeSigner(void*);
+WOLFSSL_LOCAL void    FreeSigner(Signer*, void*);
+WOLFSSL_LOCAL void    FreeSignerTable(Signer**, int, void*);
+
+
+WOLFSSL_LOCAL int ToTraditional(byte* buffer, word32 length);
+WOLFSSL_LOCAL int ToTraditionalEnc(byte* buffer, word32 length,const char*, int);
+
+WOLFSSL_LOCAL int ValidateDate(const byte* date, byte format, int dateType);
+
+/* ASN.1 helper functions */
+WOLFSSL_LOCAL int GetLength(const byte* input, word32* inOutIdx, int* len,
+                           word32 maxIdx);
+WOLFSSL_LOCAL int GetSequence(const byte* input, word32* inOutIdx, int* len,
+                             word32 maxIdx);
+WOLFSSL_LOCAL int GetSet(const byte* input, word32* inOutIdx, int* len,
+                        word32 maxIdx);
+WOLFSSL_LOCAL int GetMyVersion(const byte* input, word32* inOutIdx,
+                              int* version);
+WOLFSSL_LOCAL int GetInt(mp_int* mpi, const byte* input, word32* inOutIdx,
+                        word32 maxIdx);
+WOLFSSL_LOCAL int GetAlgoId(const byte* input, word32* inOutIdx, word32* oid,
+                           word32 maxIdx);
+WOLFSSL_LOCAL word32 SetLength(word32 length, byte* output);
+WOLFSSL_LOCAL word32 SetSequence(word32 len, byte* output);
+WOLFSSL_LOCAL word32 SetOctetString(word32 len, byte* output);
+WOLFSSL_LOCAL word32 SetImplicit(byte tag, byte number, word32 len,byte* output);
+WOLFSSL_LOCAL word32 SetExplicit(byte number, word32 len, byte* output);
+WOLFSSL_LOCAL word32 SetSet(word32 len, byte* output);
+WOLFSSL_LOCAL word32 SetAlgoID(int algoOID, byte* output, int type, int curveSz);
+WOLFSSL_LOCAL int SetMyVersion(word32 version, byte* output, int header);
+WOLFSSL_LOCAL int SetSerialNumber(const byte* sn, word32 snSz, byte* output);
+WOLFSSL_LOCAL int GetNameHash(const byte* source, word32* idx, byte* hash,
+                             int maxIdx);
+
+#ifdef HAVE_ECC
+    /* ASN sig helpers */
+    WOLFSSL_LOCAL int StoreECC_DSA_Sig(byte* out, word32* outLen, mp_int* r,
+                                      mp_int* s);
+    WOLFSSL_LOCAL int DecodeECC_DSA_Sig(const byte* sig, word32 sigLen,
+                                       mp_int* r, mp_int* s);
+#endif
+
+#ifdef WOLFSSL_CERT_GEN
+
+enum cert_enums {
+    NAME_ENTRIES    =  8,
+    JOINT_LEN       =  2,
+    EMAIL_JOINT_LEN =  9,
+    RSA_KEY         = 10,
+    NTRU_KEY        = 11,
+    ECC_KEY         = 12
+};
+
+#ifndef WOLFSSL_PEMCERT_TODER_DEFINED
+#ifndef NO_FILESYSTEM
+/* forward from wolfSSL */
+WOLFSSL_API
+int wolfSSL_PemCertToDer(const char* fileName, unsigned char* derBuf, int derSz);
+#define WOLFSSL_PEMCERT_TODER_DEFINED
+#endif
+#endif
+
+#endif /* WOLFSSL_CERT_GEN */
+
+
+
+/* for pointer use */
+typedef struct CertStatus CertStatus;
+
+#ifdef HAVE_OCSP
+
+enum Ocsp_Response_Status {
+    OCSP_SUCCESSFUL        = 0, /* Response has valid confirmations */
+    OCSP_MALFORMED_REQUEST = 1, /* Illegal confirmation request */
+    OCSP_INTERNAL_ERROR    = 2, /* Internal error in issuer */
+    OCSP_TRY_LATER         = 3, /* Try again later */
+    OCSP_SIG_REQUIRED      = 5, /* Must sign the request (4 is skipped) */
+    OCSP_UNAUTHROIZED      = 6  /* Request unauthorized */
+};
+
+
+enum Ocsp_Cert_Status {
+    CERT_GOOD    = 0,
+    CERT_REVOKED = 1,
+    CERT_UNKNOWN = 2
+};
+
+
+enum Ocsp_Sums {
+    OCSP_BASIC_OID = 117,
+    OCSP_NONCE_OID = 118
+};
+
+
+typedef struct OcspRequest  OcspRequest;
+typedef struct OcspResponse OcspResponse;
+
+
+struct CertStatus {
+    CertStatus* next;
+
+    byte serial[EXTERNAL_SERIAL_SIZE];
+    int serialSz;
+
+    int status;
+
+    byte thisDate[MAX_DATE_SIZE];
+    byte nextDate[MAX_DATE_SIZE];
+    byte thisDateFormat;
+    byte nextDateFormat;
+};
+
+
+struct OcspResponse {
+    int     responseStatus;  /* return code from Responder */
+
+    byte*   response;        /* Pointer to beginning of OCSP Response */
+    word32  responseSz;      /* length of the OCSP Response */
+
+    byte    producedDate[MAX_DATE_SIZE];
+							 /* Date at which this response was signed */
+    byte    producedDateFormat; /* format of the producedDate */
+    byte*   issuerHash;
+    byte*   issuerKeyHash;
+
+    byte*   cert;
+    word32  certSz;
+
+    byte*   sig;             /* Pointer to sig in source */
+    word32  sigSz;           /* Length in octets for the sig */
+    word32  sigOID;          /* OID for hash used for sig */
+
+    CertStatus* status;      /* certificate status to fill out */
+
+    byte*   nonce;           /* pointer to nonce inside ASN.1 response */
+    int     nonceSz;         /* length of the nonce string */
+
+    byte*   source;          /* pointer to source buffer, not owned */
+    word32  maxIdx;          /* max offset based on init size */
+};
+
+
+struct OcspRequest {
+    DecodedCert* cert;
+
+    byte    useNonce;
+    byte    nonce[MAX_OCSP_NONCE_SZ];
+    int     nonceSz;
+
+    byte*   issuerHash;      /* pointer to issuerHash in source cert */
+    byte*   issuerKeyHash;   /* pointer to issuerKeyHash in source cert */
+    byte*   serial;          /* pointer to serial number in source cert */
+    int     serialSz;        /* length of the serial number */
+
+    byte*   dest;            /* pointer to the destination ASN.1 buffer */
+    word32  destSz;          /* length of the destination buffer */
+};
+
+
+WOLFSSL_LOCAL void InitOcspResponse(OcspResponse*, CertStatus*, byte*, word32);
+WOLFSSL_LOCAL int  OcspResponseDecode(OcspResponse*);
+
+WOLFSSL_LOCAL void InitOcspRequest(OcspRequest*, DecodedCert*,
+                                                          byte, byte*, word32);
+WOLFSSL_LOCAL int  EncodeOcspRequest(OcspRequest*);
+
+WOLFSSL_LOCAL int  CompareOcspReqResp(OcspRequest*, OcspResponse*);
+
+
+#endif /* HAVE_OCSP */
+
+
+/* for pointer use */
+typedef struct RevokedCert RevokedCert;
+
+#ifdef HAVE_CRL
+
+struct RevokedCert {
+    byte         serialNumber[EXTERNAL_SERIAL_SIZE];
+    int          serialSz;
+    RevokedCert* next;
+};
+
+typedef struct DecodedCRL DecodedCRL;
+
+struct DecodedCRL {
+    word32  certBegin;               /* offset to start of cert          */
+    word32  sigIndex;                /* offset to start of signature     */
+    word32  sigLength;               /* length of signature              */
+    word32  signatureOID;            /* sum of algorithm object id       */
+    byte*   signature;               /* pointer into raw source, not owned */
+    byte    issuerHash[SIGNER_DIGEST_SIZE]; /* issuer hash               */
+    byte    crlHash[SIGNER_DIGEST_SIZE]; /* raw crl data hash            */
+    byte    lastDate[MAX_DATE_SIZE]; /* last date updated  */
+    byte    nextDate[MAX_DATE_SIZE]; /* next update date   */
+    byte    lastDateFormat;          /* format of last date */
+    byte    nextDateFormat;          /* format of next date */
+    RevokedCert* certs;              /* revoked cert list  */
+    int          totalCerts;         /* number on list     */
+};
+
+WOLFSSL_LOCAL void InitDecodedCRL(DecodedCRL*);
+WOLFSSL_LOCAL int  ParseCRL(DecodedCRL*, const byte* buff, word32 sz, void* cm);
+WOLFSSL_LOCAL void FreeDecodedCRL(DecodedCRL*);
+
+
+#endif /* HAVE_CRL */
+
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* !NO_ASN */
+#endif /* WOLF_CRYPT_ASN_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/asn_public.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/asn_public.h
new file mode 100644
index 0000000..8708708
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/asn_public.h
@@ -0,0 +1,197 @@
+/* asn_public.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifndef WOLF_CRYPT_ASN_PUBLIC_H
+#define WOLF_CRYPT_ASN_PUBLIC_H
+
+#include 
+#ifdef HAVE_ECC
+    #include 
+#endif
+#if defined(WOLFSSL_CERT_GEN) && !defined(NO_RSA)
+    #include 
+#endif
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+/* Certificate file Type */
+enum CertType {
+    CERT_TYPE       = 0,
+    PRIVATEKEY_TYPE,
+    DH_PARAM_TYPE,
+    CRL_TYPE,
+    CA_TYPE,
+    ECC_PRIVATEKEY_TYPE,
+    CERTREQ_TYPE
+};
+
+
+/* Signature type, by OID sum */
+enum Ctc_SigType {
+    CTC_SHAwDSA      = 517,
+    CTC_MD2wRSA      = 646,
+    CTC_MD5wRSA      = 648,
+    CTC_SHAwRSA      = 649,
+    CTC_SHAwECDSA    = 520,
+    CTC_SHA256wRSA   = 655,
+    CTC_SHA256wECDSA = 524,
+    CTC_SHA384wRSA   = 656,
+    CTC_SHA384wECDSA = 525,
+    CTC_SHA512wRSA   = 657,
+    CTC_SHA512wECDSA = 526
+};
+
+enum Ctc_Encoding {
+    CTC_UTF8       = 0x0c, /* utf8      */
+    CTC_PRINTABLE  = 0x13  /* printable */
+};
+
+
+#ifdef WOLFSSL_CERT_GEN
+
+#ifndef HAVE_ECC
+    typedef struct ecc_key ecc_key;
+#endif
+
+enum Ctc_Misc {
+    CTC_NAME_SIZE    =    64,
+    CTC_DATE_SIZE    =    32,
+    CTC_MAX_ALT_SIZE = 16384,   /* may be huge */
+    CTC_SERIAL_SIZE  =     8
+};
+
+typedef struct CertName {
+    char country[CTC_NAME_SIZE];
+    char countryEnc;
+    char state[CTC_NAME_SIZE];
+    char stateEnc;
+    char locality[CTC_NAME_SIZE];
+    char localityEnc;
+    char sur[CTC_NAME_SIZE];
+    char surEnc;
+    char org[CTC_NAME_SIZE];
+    char orgEnc;
+    char unit[CTC_NAME_SIZE];
+    char unitEnc;
+    char commonName[CTC_NAME_SIZE];
+    char commonNameEnc;
+    char email[CTC_NAME_SIZE];  /* !!!! email has to be last !!!! */
+} CertName;
+
+
+/* for user to fill for certificate generation */
+typedef struct Cert {
+    int      version;                   /* x509 version  */
+    byte     serial[CTC_SERIAL_SIZE];   /* serial number */
+    int      sigType;                   /* signature algo type */
+    CertName issuer;                    /* issuer info */
+    int      daysValid;                 /* validity days */
+    int      selfSigned;                /* self signed flag */
+    CertName subject;                   /* subject info */
+    int      isCA;                      /* is this going to be a CA */
+    /* internal use only */
+    int      bodySz;                    /* pre sign total size */
+    int      keyType;                   /* public key type of subject */
+#ifdef WOLFSSL_ALT_NAMES
+    byte     altNames[CTC_MAX_ALT_SIZE]; /* altNames copy */
+    int      altNamesSz;                 /* altNames size in bytes */
+    byte     beforeDate[CTC_DATE_SIZE];  /* before date copy */
+    int      beforeDateSz;               /* size of copy */
+    byte     afterDate[CTC_DATE_SIZE];   /* after date copy */
+    int      afterDateSz;                /* size of copy */
+#endif
+#ifdef WOLFSSL_CERT_REQ
+    char     challengePw[CTC_NAME_SIZE];
+#endif
+} Cert;
+#endif /* WOLFSSL_CERT_GEN */
+
+
+#ifdef WOLFSSL_CERT_GEN
+
+
+
+/* Initialize and Set Certficate defaults:
+   version    = 3 (0x2)
+   serial     = 0 (Will be randomly generated)
+   sigType    = SHA_WITH_RSA
+   issuer     = blank
+   daysValid  = 500
+   selfSigned = 1 (true) use subject as issuer
+   subject    = blank
+   isCA       = 0 (false)
+   keyType    = RSA_KEY (default)
+*/
+WOLFSSL_API void wc_InitCert(Cert*);
+WOLFSSL_API int  wc_MakeCert(Cert*, byte* derBuffer, word32 derSz, RsaKey*,
+                         ecc_key*, RNG*);
+#ifdef WOLFSSL_CERT_REQ
+    WOLFSSL_API int  wc_MakeCertReq(Cert*, byte* derBuffer, word32 derSz, RsaKey*,
+                                ecc_key*);
+#endif
+WOLFSSL_API int  wc_SignCert(int requestSz, int sigType, byte* derBuffer,
+                         word32 derSz, RsaKey*, ecc_key*, RNG*);
+WOLFSSL_API int  wc_MakeSelfCert(Cert*, byte* derBuffer, word32 derSz, RsaKey*,
+                             RNG*);
+WOLFSSL_API int  wc_SetIssuer(Cert*, const char*);
+WOLFSSL_API int  wc_SetSubject(Cert*, const char*);
+#ifdef WOLFSSL_ALT_NAMES
+    WOLFSSL_API int  wc_SetAltNames(Cert*, const char*);
+#endif
+WOLFSSL_API int  wc_SetIssuerBuffer(Cert*, const byte*, int);
+WOLFSSL_API int  wc_SetSubjectBuffer(Cert*, const byte*, int);
+WOLFSSL_API int  wc_SetAltNamesBuffer(Cert*, const byte*, int);
+WOLFSSL_API int  wc_SetDatesBuffer(Cert*, const byte*, int);
+
+    #ifdef HAVE_NTRU
+        WOLFSSL_API int  wc_MakeNtruCert(Cert*, byte* derBuffer, word32 derSz,
+                                     const byte* ntruKey, word16 keySz, RNG*);
+    #endif
+
+#endif /* WOLFSSL_CERT_GEN */
+
+
+#if defined(WOLFSSL_KEY_GEN) || defined(WOLFSSL_CERT_GEN)
+    WOLFSSL_API int wc_DerToPem(const byte* der, word32 derSz, byte* output,
+                            word32 outputSz, int type);
+#endif
+
+#ifdef HAVE_ECC
+    /* private key helpers */
+    WOLFSSL_API int wc_EccPrivateKeyDecode(const byte* input,word32* inOutIdx,
+                                         ecc_key*,word32);
+    WOLFSSL_API int wc_EccKeyToDer(ecc_key*, byte* output, word32 inLen);
+#endif
+
+/* DER encode signature */
+WOLFSSL_API word32 wc_EncodeSignature(byte* out, const byte* digest, word32 digSz,
+                                  int hashOID);
+WOLFSSL_API int wc_GetCTC_HashOID(int type);
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* WOLF_CRYPT_ASN_PUBLIC_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/blake2-impl.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/blake2-impl.h
new file mode 100644
index 0000000..e1882f2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/blake2-impl.h
@@ -0,0 +1,154 @@
+/*
+   BLAKE2 reference source code package - reference C implementations
+
+   Written in 2012 by Samuel Neves 
+
+   To the extent possible under law, the author(s) have dedicated all copyright
+   and related and neighboring rights to this software to the public domain
+   worldwide. This software is distributed without any warranty.
+
+   You should have received a copy of the CC0 Public Domain Dedication along with
+   this software. If not, see .
+*/
+/* blake2-impl.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifndef WOLFCRYPT_BLAKE2_IMPL_H
+#define WOLFCRYPT_BLAKE2_IMPL_H
+
+#include 
+
+static inline word32 load32( const void *src )
+{
+#if defined(LITTLE_ENDIAN_ORDER)
+  return *( word32 * )( src );
+#else
+  const byte *p = ( byte * )src;
+  word32 w = *p++;
+  w |= ( word32 )( *p++ ) <<  8;
+  w |= ( word32 )( *p++ ) << 16;
+  w |= ( word32 )( *p++ ) << 24;
+  return w;
+#endif
+}
+
+static inline word64 load64( const void *src )
+{
+#if defined(LITTLE_ENDIAN_ORDER)
+  return *( word64 * )( src );
+#else
+  const byte *p = ( byte * )src;
+  word64 w = *p++;
+  w |= ( word64 )( *p++ ) <<  8;
+  w |= ( word64 )( *p++ ) << 16;
+  w |= ( word64 )( *p++ ) << 24;
+  w |= ( word64 )( *p++ ) << 32;
+  w |= ( word64 )( *p++ ) << 40;
+  w |= ( word64 )( *p++ ) << 48;
+  w |= ( word64 )( *p++ ) << 56;
+  return w;
+#endif
+}
+
+static inline void store32( void *dst, word32 w )
+{
+#if defined(LITTLE_ENDIAN_ORDER)
+  *( word32 * )( dst ) = w;
+#else
+  byte *p = ( byte * )dst;
+  *p++ = ( byte )w; w >>= 8;
+  *p++ = ( byte )w; w >>= 8;
+  *p++ = ( byte )w; w >>= 8;
+  *p++ = ( byte )w;
+#endif
+}
+
+static inline void store64( void *dst, word64 w )
+{
+#if defined(LITTLE_ENDIAN_ORDER)
+  *( word64 * )( dst ) = w;
+#else
+  byte *p = ( byte * )dst;
+  *p++ = ( byte )w; w >>= 8;
+  *p++ = ( byte )w; w >>= 8;
+  *p++ = ( byte )w; w >>= 8;
+  *p++ = ( byte )w; w >>= 8;
+  *p++ = ( byte )w; w >>= 8;
+  *p++ = ( byte )w; w >>= 8;
+  *p++ = ( byte )w; w >>= 8;
+  *p++ = ( byte )w;
+#endif
+}
+
+static inline word64 load48( const void *src )
+{
+  const byte *p = ( const byte * )src;
+  word64 w = *p++;
+  w |= ( word64 )( *p++ ) <<  8;
+  w |= ( word64 )( *p++ ) << 16;
+  w |= ( word64 )( *p++ ) << 24;
+  w |= ( word64 )( *p++ ) << 32;
+  w |= ( word64 )( *p++ ) << 40;
+  return w;
+}
+
+static inline void store48( void *dst, word64 w )
+{
+  byte *p = ( byte * )dst;
+  *p++ = ( byte )w; w >>= 8;
+  *p++ = ( byte )w; w >>= 8;
+  *p++ = ( byte )w; w >>= 8;
+  *p++ = ( byte )w; w >>= 8;
+  *p++ = ( byte )w; w >>= 8;
+  *p++ = ( byte )w;
+}
+
+static inline word32 rotl32( const word32 w, const unsigned c )
+{
+  return ( w << c ) | ( w >> ( 32 - c ) );
+}
+
+static inline word64 rotl64( const word64 w, const unsigned c )
+{
+  return ( w << c ) | ( w >> ( 64 - c ) );
+}
+
+static inline word32 rotr32( const word32 w, const unsigned c )
+{
+  return ( w >> c ) | ( w << ( 32 - c ) );
+}
+
+static inline word64 rotr64( const word64 w, const unsigned c )
+{
+  return ( w >> c ) | ( w << ( 64 - c ) );
+}
+
+/* prevents compiler optimizing out memset() */
+static inline void secure_zero_memory( void *v, word64 n )
+{
+  volatile byte *p = ( volatile byte * )v;
+
+  while( n-- ) *p++ = 0;
+}
+
+#endif  /* WOLFCRYPT_BLAKE2_IMPL_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/blake2-int.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/blake2-int.h
new file mode 100644
index 0000000..05fd027
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/blake2-int.h
@@ -0,0 +1,183 @@
+/*
+   BLAKE2 reference source code package - reference C implementations
+
+   Written in 2012 by Samuel Neves 
+
+   To the extent possible under law, the author(s) have dedicated all copyright
+   and related and neighboring rights to this software to the public domain
+   worldwide. This software is distributed without any warranty.
+
+   You should have received a copy of the CC0 Public Domain Dedication along with
+   this software. If not, see .
+*/
+/* blake2-int.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+
+#ifndef WOLFCRYPT_BLAKE2_INT_H
+#define WOLFCRYPT_BLAKE2_INT_H
+
+#include 
+
+
+#if defined(_MSC_VER)
+    #define ALIGN(x) __declspec(align(x))
+#elif defined(__GNUC__)
+    #define ALIGN(x) __attribute__((aligned(x)))
+#else
+    #define ALIGN(x)
+#endif
+
+
+#if defined(__cplusplus)
+    extern "C" {
+#endif
+
+  enum blake2s_constant
+  {
+    BLAKE2S_BLOCKBYTES = 64,
+    BLAKE2S_OUTBYTES   = 32,
+    BLAKE2S_KEYBYTES   = 32,
+    BLAKE2S_SALTBYTES  = 8,
+    BLAKE2S_PERSONALBYTES = 8
+  };
+
+  enum blake2b_constant
+  {
+    BLAKE2B_BLOCKBYTES = 128,
+    BLAKE2B_OUTBYTES   = 64,
+    BLAKE2B_KEYBYTES   = 64,
+    BLAKE2B_SALTBYTES  = 16,
+    BLAKE2B_PERSONALBYTES = 16
+  };
+
+#pragma pack(push, 1)
+  typedef struct __blake2s_param
+  {
+    byte  digest_length; /* 1 */
+    byte  key_length;    /* 2 */
+    byte  fanout;        /* 3 */
+    byte  depth;         /* 4 */
+    word32 leaf_length;   /* 8 */
+    byte  node_offset[6];/* 14 */
+    byte  node_depth;    /* 15 */
+    byte  inner_length;  /* 16 */
+    /* byte  reserved[0]; */
+    byte  salt[BLAKE2B_SALTBYTES]; /* 24 */
+    byte  personal[BLAKE2S_PERSONALBYTES];  /* 32 */
+  } blake2s_param;
+
+  ALIGN( 64 ) typedef struct __blake2s_state
+  {
+    word32 h[8];
+    word32 t[2];
+    word32 f[2];
+    byte  buf[2 * BLAKE2S_BLOCKBYTES];
+    word64 buflen;
+    byte  last_node;
+  } blake2s_state ;
+
+  typedef struct __blake2b_param
+  {
+    byte  digest_length; /* 1 */
+    byte  key_length;    /* 2 */
+    byte  fanout;        /* 3 */
+    byte  depth;         /* 4 */
+    word32 leaf_length;   /* 8 */
+    word64 node_offset;   /* 16 */
+    byte  node_depth;    /* 17 */
+    byte  inner_length;  /* 18 */
+    byte  reserved[14];  /* 32 */
+    byte  salt[BLAKE2B_SALTBYTES]; /* 48 */
+    byte  personal[BLAKE2B_PERSONALBYTES];  /* 64 */
+  } blake2b_param;
+
+  ALIGN( 64 ) typedef struct __blake2b_state
+  {
+    word64 h[8];
+    word64 t[2];
+    word64 f[2];
+    byte  buf[2 * BLAKE2B_BLOCKBYTES];
+    word64 buflen;
+    byte  last_node;
+  } blake2b_state;
+
+  typedef struct __blake2sp_state
+  {
+    blake2s_state S[8][1];
+    blake2s_state R[1];
+    byte buf[8 * BLAKE2S_BLOCKBYTES];
+    word64 buflen;
+  } blake2sp_state;
+
+  typedef struct __blake2bp_state
+  {
+    blake2b_state S[4][1];
+    blake2b_state R[1];
+    byte buf[4 * BLAKE2B_BLOCKBYTES];
+    word64 buflen;
+  } blake2bp_state;
+#pragma pack(pop)
+
+  /* Streaming API */
+  int blake2s_init( blake2s_state *S, const byte outlen );
+  int blake2s_init_key( blake2s_state *S, const byte outlen, const void *key, const byte keylen );
+  int blake2s_init_param( blake2s_state *S, const blake2s_param *P );
+  int blake2s_update( blake2s_state *S, const byte *in, word64 inlen );
+  int blake2s_final( blake2s_state *S, byte *out, byte outlen );
+
+  int blake2b_init( blake2b_state *S, const byte outlen );
+  int blake2b_init_key( blake2b_state *S, const byte outlen, const void *key, const byte keylen );
+  int blake2b_init_param( blake2b_state *S, const blake2b_param *P );
+  int blake2b_update( blake2b_state *S, const byte *in, word64 inlen );
+  int blake2b_final( blake2b_state *S, byte *out, byte outlen );
+
+  int blake2sp_init( blake2sp_state *S, const byte outlen );
+  int blake2sp_init_key( blake2sp_state *S, const byte outlen, const void *key, const byte keylen );
+  int blake2sp_update( blake2sp_state *S, const byte *in, word64 inlen );
+  int blake2sp_final( blake2sp_state *S, byte *out, byte outlen );
+
+  int blake2bp_init( blake2bp_state *S, const byte outlen );
+  int blake2bp_init_key( blake2bp_state *S, const byte outlen, const void *key, const byte keylen );
+  int blake2bp_update( blake2bp_state *S, const byte *in, word64 inlen );
+  int blake2bp_final( blake2bp_state *S, byte *out, byte outlen );
+
+  /* Simple API */
+  int blake2s( byte *out, const void *in, const void *key, const byte outlen, const word64 inlen, byte keylen );
+  int blake2b( byte *out, const void *in, const void *key, const byte outlen, const word64 inlen, byte keylen );
+
+  int blake2sp( byte *out, const void *in, const void *key, const byte outlen, const word64 inlen, byte keylen );
+  int blake2bp( byte *out, const void *in, const void *key, const byte outlen, const word64 inlen, byte keylen );
+
+  static inline int blake2( byte *out, const void *in, const void *key, const byte outlen, const word64 inlen, byte keylen )
+  {
+    return blake2b( out, in, key, outlen, inlen, keylen );
+  }
+
+
+
+#if defined(__cplusplus)
+    }
+#endif
+
+#endif  /* WOLFCRYPT_BLAKE2_INT_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/blake2.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/blake2.h
new file mode 100644
index 0000000..5186663
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/blake2.h
@@ -0,0 +1,71 @@
+/* blake2.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * a with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+
+#ifndef WOLF_CRYPT_BLAKE2_H
+#define WOLF_CRYPT_BLAKE2_H
+
+#include 
+
+#ifdef HAVE_BLAKE2
+
+#include 
+
+/* call old functions if using fips for the sake of hmac @wc_fips */
+#ifdef HAVE_FIPS
+    /* Since hmac can call blake functions provide original calls */
+    #define wc_InitBlake2b   InitBlake2b
+    #define wc_Blake2bUpdate Blake2bUpdate
+    #define wc_Blake2bFinal  Blake2bFinal
+#endif
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+/* in bytes, variable digest size up to 512 bits (64 bytes) */
+enum {
+    BLAKE2B_ID  = 7,   /* hash type unique */
+    BLAKE2B_256 = 32   /* 256 bit type, SSL default */
+};
+
+
+/* BLAKE2b digest */
+typedef struct Blake2b {
+    blake2b_state S[1];         /* our state */
+    word32        digestSz;     /* digest size used on init */
+} Blake2b;
+
+
+WOLFSSL_API int wc_InitBlake2b(Blake2b*, word32);
+WOLFSSL_API int wc_Blake2bUpdate(Blake2b*, const byte*, word32);
+WOLFSSL_API int wc_Blake2bFinal(Blake2b*, byte*, word32);
+
+
+
+#ifdef __cplusplus
+    }
+#endif
+
+#endif  /* HAVE_BLAKE2 */
+#endif  /* WOLF_CRYPT_BLAKE2_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/camellia.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/camellia.h
new file mode 100644
index 0000000..4b7b92a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/camellia.h
@@ -0,0 +1,96 @@
+/* camellia.h ver 1.2.0
+ *
+ * Copyright (c) 2006,2007
+ * NTT (Nippon Telegraph and Telephone Corporation) . All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer as
+ *   the first lines of this file unmodified.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NTT ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL NTT BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* camellia.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_CAMELLIA_H
+#define WOLF_CRYPT_CAMELLIA_H
+
+#include 
+
+#ifdef HAVE_CAMELLIA
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+enum {
+    CAMELLIA_BLOCK_SIZE = 16
+};
+
+#define CAMELLIA_TABLE_BYTE_LEN 272
+#define CAMELLIA_TABLE_WORD_LEN (CAMELLIA_TABLE_BYTE_LEN / sizeof(word32))
+
+typedef word32 KEY_TABLE_TYPE[CAMELLIA_TABLE_WORD_LEN];
+
+typedef struct Camellia {
+    word32 keySz;
+    KEY_TABLE_TYPE key;
+    word32 reg[CAMELLIA_BLOCK_SIZE / sizeof(word32)]; /* for CBC mode */
+    word32 tmp[CAMELLIA_BLOCK_SIZE / sizeof(word32)]; /* for CBC mode */
+} Camellia;
+
+
+WOLFSSL_API int  wc_CamelliaSetKey(Camellia* cam,
+                                   const byte* key, word32 len, const byte* iv);
+WOLFSSL_API int  wc_CamelliaSetIV(Camellia* cam, const byte* iv);
+WOLFSSL_API void wc_CamelliaEncryptDirect(Camellia* cam, byte* out,
+                                                                const byte* in);
+WOLFSSL_API void wc_CamelliaDecryptDirect(Camellia* cam, byte* out,
+                                                                const byte* in);
+WOLFSSL_API void wc_CamelliaCbcEncrypt(Camellia* cam,
+                                          byte* out, const byte* in, word32 sz);
+WOLFSSL_API void wc_CamelliaCbcDecrypt(Camellia* cam,
+                                          byte* out, const byte* in, word32 sz);
+
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* HAVE_CAMELLIA */
+#endif /* WOLF_CRYPT_CAMELLIA_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/chacha.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/chacha.h
new file mode 100644
index 0000000..da938c9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/chacha.h
@@ -0,0 +1,57 @@
+/* chacha.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_CHACHA_H
+#define WOLF_CRYPT_CHACHA_H
+
+#include 
+
+#ifdef HAVE_CHACHA
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+enum {
+	CHACHA_ENC_TYPE = 7     /* cipher unique type */
+};
+
+typedef struct ChaCha {
+    word32 X[16];           /* state of cipher */
+} ChaCha;
+
+/**
+  * IV(nonce) changes with each record
+  * counter is for what value the block counter should start ... usually 0
+  */
+WOLFSSL_API int wc_Chacha_SetIV(ChaCha* ctx, const byte* inIv, word32 counter);
+
+WOLFSSL_API int wc_Chacha_Process(ChaCha* ctx, byte* cipher, const byte* plain,
+                              word32 msglen);
+WOLFSSL_API int wc_Chacha_SetKey(ChaCha* ctx, const byte* key, word32 keySz);
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* HAVE_CHACHA */
+#endif /* WOLF_CRYPT_CHACHA_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/chacha20_poly1305.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/chacha20_poly1305.h
new file mode 100644
index 0000000..e65842b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/chacha20_poly1305.h
@@ -0,0 +1,79 @@
+/* chacha20_poly1305.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+/* This implementation of the ChaCha20-Poly1305 AEAD is based on "ChaCha20
+ * and Poly1305 for IETF protocols" (draft-irtf-cfrg-chacha20-poly1305-10):
+ * https://tools.ietf.org/html/draft-irtf-cfrg-chacha20-poly1305-10
+ */
+
+#ifndef WOLF_CRYPT_CHACHA20_POLY1305_H
+#define WOLF_CRYPT_CHACHA20_POLY1305_H
+
+#include 
+
+#if defined(HAVE_CHACHA) && defined(HAVE_POLY1305)
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#define CHACHA20_POLY1305_AEAD_KEYSIZE      32
+#define CHACHA20_POLY1305_AEAD_IV_SIZE      12
+#define CHACHA20_POLY1305_AEAD_AUTHTAG_SIZE 16
+
+enum {
+    CHACHA20_POLY_1305_ENC_TYPE = 8    /* cipher unique type */
+};
+
+    /*
+     * The IV for this implementation is 96 bits to give the most flexibility.
+     *
+     * Some protocols may have unique per-invocation inputs that are not
+     * 96-bit in length. For example, IPsec may specify a 64-bit nonce. In
+     * such a case, it is up to the protocol document to define how to
+     * transform the protocol nonce into a 96-bit nonce, for example by
+     * concatenating a constant value.
+     */
+
+WOLFSSL_API
+int wc_ChaCha20Poly1305_Encrypt(
+                const byte inKey[CHACHA20_POLY1305_AEAD_KEYSIZE],
+                const byte inIV[CHACHA20_POLY1305_AEAD_IV_SIZE],
+                const byte* inAAD, const word32 inAADLen,
+                const byte* inPlaintext, const word32 inPlaintextLen,
+                byte* outCiphertext,
+                byte outAuthTag[CHACHA20_POLY1305_AEAD_AUTHTAG_SIZE]);
+
+WOLFSSL_API
+int wc_ChaCha20Poly1305_Decrypt(
+                const byte inKey[CHACHA20_POLY1305_AEAD_KEYSIZE],
+                const byte inIV[CHACHA20_POLY1305_AEAD_IV_SIZE],
+                const byte* inAAD, const word32 inAADLen,
+                const byte* inCiphertext, const word32 inCiphertextLen,
+                const byte inAuthTag[CHACHA20_POLY1305_AEAD_AUTHTAG_SIZE],
+                byte* outPlaintext);
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* HAVE_CHACHA && HAVE_POLY1305 */
+#endif /* WOLF_CRYPT_CHACHA20_POLY1305_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/coding.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/coding.h
new file mode 100644
index 0000000..296bc3c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/coding.h
@@ -0,0 +1,64 @@
+/* coding.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifndef WOLF_CRYPT_CODING_H
+#define WOLF_CRYPT_CODING_H
+
+#include 
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+
+WOLFSSL_API int Base64_Decode(const byte* in, word32 inLen, byte* out,
+                               word32* outLen);
+
+#if defined(OPENSSL_EXTRA) || defined(SESSION_CERTS) || defined(WOLFSSL_KEY_GEN)                         || defined(WOLFSSL_CERT_GEN) || defined(HAVE_WEBSERVER)
+    #ifndef WOLFSSL_BASE64_ENCODE
+        #define WOLFSSL_BASE64_ENCODE
+    #endif
+#endif
+
+
+#ifdef WOLFSSL_BASE64_ENCODE
+    /* encode isn't */
+    WOLFSSL_API
+    int Base64_Encode(const byte* in, word32 inLen, byte* out,
+                                  word32* outLen);
+    WOLFSSL_API
+    int Base64_EncodeEsc(const byte* in, word32 inLen, byte* out,
+                                  word32* outLen);
+#endif
+
+#if defined(OPENSSL_EXTRA) || defined(HAVE_WEBSERVER) || defined(HAVE_FIPS)
+    WOLFSSL_API
+    int Base16_Decode(const byte* in, word32 inLen, byte* out, word32* outLen);
+#endif
+
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* WOLF_CRYPT_CODING_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/compress.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/compress.h
new file mode 100644
index 0000000..dc012b8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/compress.h
@@ -0,0 +1,48 @@
+/* compress.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_COMPRESS_H
+#define WOLF_CRYPT_COMPRESS_H
+
+#include 
+
+#ifdef HAVE_LIBZ
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+
+#define COMPRESS_FIXED 1
+
+
+WOLFSSL_API int wc_Compress(byte*, word32, const byte*, word32, word32);
+WOLFSSL_API int wc_DeCompress(byte*, word32, const byte*, word32);
+
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+
+#endif /* HAVE_LIBZ */
+#endif /* WOLF_CRYPT_COMPRESS_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/curve25519.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/curve25519.h
new file mode 100644
index 0000000..1171577
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/curve25519.h
@@ -0,0 +1,102 @@
+/* curve25519.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_CURVE25519_H
+#define WOLF_CRYPT_CURVE25519_H
+
+#include 
+
+#ifdef HAVE_CURVE25519
+
+#include 
+#include 
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#define CURVE25519_KEYSIZE 32
+
+/* curve25519 set type */
+typedef struct {
+    int size;       /* The size of the curve in octets */
+    const char* name;     /* name of this curve */
+} curve25519_set_type;
+
+
+/* ECC point */
+typedef struct {
+    byte point[CURVE25519_KEYSIZE];
+}ECPoint;
+
+/* A CURVE25519 Key */
+typedef struct {
+    int idx;            /* Index into the ecc_sets[] for the parameters of
+                           this curve if -1, this key is using user supplied
+                           curve in dp */
+    const curve25519_set_type* dp;   /* domain parameters, either points to
+                                   curves (idx >= 0) or user supplied */
+    ECPoint   p;        /* public key  */
+    ECPoint   k;        /* private key */
+} curve25519_key;
+
+WOLFSSL_API
+int wc_curve25519_make_key(RNG* rng, int keysize, curve25519_key* key);
+
+WOLFSSL_API
+int wc_curve25519_shared_secret(curve25519_key* private_key,
+                                curve25519_key* public_key,
+                                byte* out, word32* outlen);
+
+WOLFSSL_API
+int wc_curve25519_init(curve25519_key* key);
+
+WOLFSSL_API
+void wc_curve25519_free(curve25519_key* key);
+
+
+/* raw key helpers */
+WOLFSSL_API
+int wc_curve25519_import_private_raw(const byte* priv, word32 privSz,
+                            const byte* pub, word32 pubSz, curve25519_key* key);
+WOLFSSL_API
+int wc_curve25519_export_private_raw(curve25519_key* key, byte* out,
+                                     word32* outLen);
+
+WOLFSSL_API
+int wc_curve25519_import_public(const byte* in, word32 inLen,
+                                curve25519_key* key);
+
+WOLFSSL_API
+int wc_curve25519_export_public(curve25519_key* key, byte* out, word32* outLen);
+
+
+/* size helper */
+WOLFSSL_API
+int wc_curve25519_size(curve25519_key* key);
+
+#ifdef __cplusplus
+    }    /* extern "C" */
+#endif
+
+#endif /* HAVE_CURVE25519 */
+#endif /* WOLF_CRYPT_CURVE25519_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/des3.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/des3.h
new file mode 100644
index 0000000..c178849
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/des3.h
@@ -0,0 +1,113 @@
+/* des3.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_DES3_H
+#define WOLF_CRYPT_DES3_H
+
+#include 
+
+#ifndef NO_DES3
+
+#ifdef HAVE_FIPS
+/* included for fips @wc_fips */
+#include 
+#endif
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#ifndef HAVE_FIPS /* to avoid redifinition of macros */
+#define WOLFSSL_3DES_CAVIUM_MAGIC 0xBEEF0003
+
+enum {
+    DES_ENC_TYPE    = 2,     /* cipher unique type */
+    DES3_ENC_TYPE   = 3,     /* cipher unique type */
+    DES_BLOCK_SIZE  = 8,
+    DES_KS_SIZE     = 32,
+
+    DES_ENCRYPTION  = 0,
+    DES_DECRYPTION  = 1
+};
+
+#define DES_IVLEN 8
+#define DES_KEYLEN 8
+#define DES3_IVLEN 8
+#define DES3_KEYLEN 24
+
+
+#ifdef STM32F2_CRYPTO
+enum {
+    DES_CBC = 0,
+    DES_ECB = 1
+};
+#endif
+
+
+/* DES encryption and decryption */
+typedef struct Des {
+    word32 reg[DES_BLOCK_SIZE / sizeof(word32)];      /* for CBC mode */
+    word32 tmp[DES_BLOCK_SIZE / sizeof(word32)];      /* same         */
+    word32 key[DES_KS_SIZE];
+} Des;
+
+
+/* DES3 encryption and decryption */
+typedef struct Des3 {
+    word32 key[3][DES_KS_SIZE];
+    word32 reg[DES_BLOCK_SIZE / sizeof(word32)];      /* for CBC mode */
+    word32 tmp[DES_BLOCK_SIZE / sizeof(word32)];      /* same         */
+#ifdef HAVE_CAVIUM
+    int     devId;           /* nitrox device id */
+    word32  magic;           /* using cavium magic */
+    word64  contextHandle;   /* nitrox context memory handle */
+#endif
+} Des3;
+#endif /* HAVE_FIPS */
+
+WOLFSSL_API int  wc_Des_SetKey(Des* des, const byte* key, const byte* iv, int dir);
+WOLFSSL_API void wc_Des_SetIV(Des* des, const byte* iv);
+WOLFSSL_API int  wc_Des_CbcEncrypt(Des* des, byte* out, const byte* in, word32 sz);
+WOLFSSL_API int  wc_Des_CbcDecrypt(Des* des, byte* out, const byte* in, word32 sz);
+WOLFSSL_API int  wc_Des_EcbEncrypt(Des* des, byte* out, const byte* in, word32 sz);
+WOLFSSL_API int  wc_Des_CbcDecryptWithKey(byte* out, const byte* in, word32 sz,
+                                               const byte* key, const byte* iv);
+
+WOLFSSL_API int  wc_Des3_SetKey(Des3* des, const byte* key, const byte* iv,int dir);
+WOLFSSL_API int  wc_Des3_SetIV(Des3* des, const byte* iv);
+WOLFSSL_API int  wc_Des3_CbcEncrypt(Des3* des, byte* out, const byte* in,word32 sz);
+WOLFSSL_API int  wc_Des3_CbcDecrypt(Des3* des, byte* out, const byte* in,word32 sz);
+WOLFSSL_API int  wc_Des3_CbcDecryptWithKey(byte* out, const byte* in, word32 sz,
+                                               const byte* key, const byte* iv);
+
+
+#ifdef HAVE_CAVIUM
+    WOLFSSL_API int  wc_Des3_InitCavium(Des3*, int);
+    WOLFSSL_API void wc_Des3_FreeCavium(Des3*);
+#endif
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* NO_DES3 */
+#endif /* WOLF_CRYPT_DES3_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/dh.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/dh.h
new file mode 100644
index 0000000..7cee7dc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/dh.h
@@ -0,0 +1,66 @@
+/* dh.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_DH_H
+#define WOLF_CRYPT_DH_H
+
+#include 
+
+#ifndef NO_DH
+
+#include 
+#include 
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+
+/* Diffie-Hellman Key */
+typedef struct DhKey {
+    mp_int p, g;                            /* group parameters  */
+} DhKey;
+
+
+WOLFSSL_API void wc_InitDhKey(DhKey* key);
+WOLFSSL_API void wc_FreeDhKey(DhKey* key);
+
+WOLFSSL_API int wc_DhGenerateKeyPair(DhKey* key, RNG* rng, byte* priv,
+                                 word32* privSz, byte* pub, word32* pubSz);
+WOLFSSL_API int wc_DhAgree(DhKey* key, byte* agree, word32* agreeSz,
+                       const byte* priv, word32 privSz, const byte* otherPub,
+                       word32 pubSz);
+
+WOLFSSL_API int wc_DhKeyDecode(const byte* input, word32* inOutIdx, DhKey* key,
+                           word32);
+WOLFSSL_API int wc_DhSetKey(DhKey* key, const byte* p, word32 pSz, const byte* g,
+                        word32 gSz);
+WOLFSSL_API int wc_DhParamsLoad(const byte* input, word32 inSz, byte* p,
+                            word32* pInOutSz, byte* g, word32* gInOutSz);
+
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* NO_DH */
+#endif /* WOLF_CRYPT_DH_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/dsa.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/dsa.h
new file mode 100644
index 0000000..960bd75
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/dsa.h
@@ -0,0 +1,75 @@
+/* dsa.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_DSA_H
+#define WOLF_CRYPT_DSA_H
+
+#include 
+
+#ifndef NO_DSA
+
+#include 
+#include 
+
+/* for DSA reverse compatibility */
+#define InitDsaKey wc_InitDsaKey
+#define FreeDsaKey wc_FreeDsaKey
+#define DsaSign wc_DsaSign
+#define DsaVerify wc_DsaVerify
+#define DsaPublicKeyDecode wc_DsaPublicKeyDecode
+#define DsaPrivateKeyDecode wc_DsaPrivateKeyDecode
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+
+enum {
+    DSA_PUBLIC   = 0,
+    DSA_PRIVATE  = 1
+};
+
+/* DSA */
+typedef struct DsaKey {
+    mp_int p, q, g, y, x;
+    int type;                               /* public or private */
+} DsaKey;
+
+
+WOLFSSL_API void wc_InitDsaKey(DsaKey* key);
+WOLFSSL_API void wc_FreeDsaKey(DsaKey* key);
+
+WOLFSSL_API int wc_DsaSign(const byte* digest, byte* out, DsaKey* key, RNG* rng);
+WOLFSSL_API int wc_DsaVerify(const byte* digest, const byte* sig, DsaKey* key,
+                         int* answer);
+
+WOLFSSL_API int wc_DsaPublicKeyDecode(const byte* input, word32* inOutIdx, DsaKey*,
+                                  word32);
+WOLFSSL_API int wc_DsaPrivateKeyDecode(const byte* input, word32* inOutIdx, DsaKey*,
+                                   word32);
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* NO_DSA */
+#endif /* WOLF_CRYPT_DSA_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/ecc.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/ecc.h
new file mode 100644
index 0000000..447e8d3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/ecc.h
@@ -0,0 +1,245 @@
+/* ecc.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_ECC_H
+#define WOLF_CRYPT_ECC_H
+
+#include 
+
+#ifdef HAVE_ECC
+
+#include 
+#include 
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+enum {
+    ECC_PUBLICKEY  = 1,
+    ECC_PRIVATEKEY = 2,
+    ECC_MAXNAME    = 16,     /* MAX CURVE NAME LENGTH */
+    SIG_HEADER_SZ  =  6,     /* ECC signature header size */
+    ECC_BUFSIZE    = 256,    /* for exported keys temp buffer */
+    ECC_MINSIZE    = 20,     /* MIN Private Key size */
+    ECC_MAXSIZE    = 66      /* MAX Private Key size */
+};
+
+
+/* ECC set type defined a NIST GF(p) curve */
+typedef struct {
+    int size;       /* The size of the curve in octets */
+    const char* name;     /* name of this curve */
+    const char* prime;    /* prime that defines the field, curve is in (hex) */
+    const char* Af;       /* fields A param (hex) */
+    const char* Bf;       /* fields B param (hex) */
+    const char* order;    /* order of the curve (hex) */
+    const char* Gx;       /* x coordinate of the base point on curve (hex) */
+    const char* Gy;       /* y coordinate of the base point on curve (hex) */
+} ecc_set_type;
+
+
+#ifdef ALT_ECC_SIZE
+
+/* Note on ALT_ECC_SIZE:
+ * The fast math code uses an array of a fixed size to store the big integers.
+ * By default, the array is big enough for RSA keys. There is a size,
+ * FP_MAX_BITS which can be used to make the array smaller when one wants ECC
+ * but not RSA. Some people want fast math sized for both RSA and ECC, where
+ * ECC won't use as much as RSA. The flag ALT_ECC_SIZE switches in an alternate
+ * ecc_point structure that uses an alternate fp_int that has a shorter array
+ * of fp_digits.
+ *
+ * Now, without ALT_ECC_SIZE, the ecc_point has three single item arrays of
+ * mp_ints for the components of the point. With ALT_ECC_SIZE, the components
+ * of the point are pointers that are set to each of a three item array of
+ * alt_fp_ints. While an mp_int will have 4096 bits of digit inside the
+ * structure, the alt_fp_int will only have 512 bits. A size value was added
+ * in the ALT case, as well, and is set by mp_init() and alt_fp_init(). The
+ * functions fp_zero() and fp_copy() use the size parameter. An int needs to
+ * be initialized before using it instead of just fp_zeroing it, the init will
+ * call zero. FP_MAX_BITS_ECC defaults to 512, but can be set to change the
+ * number of bits used in the alternate FP_INT.
+ *
+ * Do not enable ALT_ECC_SIZE and disable fast math in the configuration.
+ */
+
+#ifndef FP_MAX_BITS_ECC
+    #define FP_MAX_BITS_ECC           512
+#endif
+#define FP_MAX_SIZE_ECC           (FP_MAX_BITS_ECC+(8*DIGIT_BIT))
+#if FP_MAX_BITS_ECC % CHAR_BIT
+   #error FP_MAX_BITS_ECC must be a multiple of CHAR_BIT
+#endif
+#define FP_SIZE_ECC    (FP_MAX_SIZE_ECC/DIGIT_BIT)
+
+/* This needs to match the size of the fp_int struct, except the
+ * fp_digit array will be shorter. */
+typedef struct alt_fp_int {
+    int used, sign, size;
+    fp_digit dp[FP_SIZE_ECC];
+} alt_fp_int;
+#endif
+
+/* A point on an ECC curve, stored in Jacbobian format such that (x,y,z) =>
+   (x/z^2, y/z^3, 1) when interpreted as affine */
+typedef struct {
+#ifndef ALT_ECC_SIZE
+    mp_int x[1];        /* The x coordinate */
+    mp_int y[1];        /* The y coordinate */
+    mp_int z[1];        /* The z coordinate */
+#else
+    mp_int* x;        /* The x coordinate */
+    mp_int* y;        /* The y coordinate */
+    mp_int* z;        /* The z coordinate */
+    alt_fp_int xyz[3];
+#endif
+} ecc_point;
+
+
+/* An ECC Key */
+typedef struct {
+    int type;           /* Public or Private */
+    int idx;            /* Index into the ecc_sets[] for the parameters of
+                           this curve if -1, this key is using user supplied
+                           curve in dp */
+    const ecc_set_type* dp;     /* domain parameters, either points to NIST
+                                   curves (idx >= 0) or user supplied */
+    ecc_point pubkey;   /* public key */
+    mp_int    k;        /* private key */
+} ecc_key;
+
+
+/* ECC predefined curve sets  */
+extern const ecc_set_type ecc_sets[];
+
+
+WOLFSSL_API
+int wc_ecc_make_key(RNG* rng, int keysize, ecc_key* key);
+WOLFSSL_API
+int wc_ecc_check_key(ecc_key* key);
+WOLFSSL_API
+int wc_ecc_shared_secret(ecc_key* private_key, ecc_key* public_key, byte* out,
+                      word32* outlen);
+WOLFSSL_API
+int wc_ecc_sign_hash(const byte* in, word32 inlen, byte* out, word32 *outlen, 
+                  RNG* rng, ecc_key* key);
+WOLFSSL_API
+int wc_ecc_verify_hash(const byte* sig, word32 siglen, const byte* hash,
+                    word32 hashlen, int* stat, ecc_key* key);
+WOLFSSL_API
+int wc_ecc_init(ecc_key* key);
+WOLFSSL_API
+void wc_ecc_free(ecc_key* key);
+WOLFSSL_API
+void wc_ecc_fp_free(void);
+
+
+/* ASN key helpers */
+WOLFSSL_API
+int wc_ecc_export_x963(ecc_key*, byte* out, word32* outLen);
+WOLFSSL_API
+int wc_ecc_export_x963_ex(ecc_key*, byte* out, word32* outLen, int compressed);
+    /* extended functionality with compressed option */
+WOLFSSL_API
+int wc_ecc_import_x963(const byte* in, word32 inLen, ecc_key* key);
+WOLFSSL_API
+int wc_ecc_import_private_key(const byte* priv, word32 privSz, const byte* pub,
+                           word32 pubSz, ecc_key* key);
+WOLFSSL_API
+int wc_ecc_rs_to_sig(const char* r, const char* s, byte* out, word32* outlen);
+WOLFSSL_API
+int wc_ecc_import_raw(ecc_key* key, const char* qx, const char* qy,
+                   const char* d, const char* curveName);
+
+WOLFSSL_API
+int wc_ecc_export_private_only(ecc_key* key, byte* out, word32* outLen);
+
+/* size helper */
+WOLFSSL_API
+int wc_ecc_size(ecc_key* key);
+WOLFSSL_API
+int wc_ecc_sig_size(ecc_key* key);
+
+
+#ifdef HAVE_ECC_ENCRYPT
+/* ecc encrypt */
+
+enum ecEncAlgo {
+    ecAES_128_CBC = 1,  /* default */
+    ecAES_256_CBC = 2
+};
+
+enum ecKdfAlgo {
+    ecHKDF_SHA256 = 1,  /* default */
+    ecHKDF_SHA1   = 2
+};
+
+enum ecMacAlgo {
+    ecHMAC_SHA256 = 1,  /* default */
+    ecHMAC_SHA1   = 2
+};
+
+enum {
+    KEY_SIZE_128     = 16,
+    KEY_SIZE_256     = 32,
+    IV_SIZE_64       =  8,
+    EXCHANGE_SALT_SZ = 16,
+    EXCHANGE_INFO_SZ = 23
+};
+
+enum ecFlags {
+    REQ_RESP_CLIENT = 1,
+    REQ_RESP_SERVER = 2
+};
+
+
+typedef struct ecEncCtx ecEncCtx;
+
+WOLFSSL_API
+ecEncCtx* wc_ecc_ctx_new(int flags, RNG* rng);
+WOLFSSL_API
+void wc_ecc_ctx_free(ecEncCtx*);
+WOLFSSL_API
+int wc_ecc_ctx_reset(ecEncCtx*, RNG*);   /* reset for use again w/o alloc/free */
+
+WOLFSSL_API
+const byte* wc_ecc_ctx_get_own_salt(ecEncCtx*);
+WOLFSSL_API
+int wc_ecc_ctx_set_peer_salt(ecEncCtx*, const byte* salt);
+WOLFSSL_API
+int wc_ecc_ctx_set_info(ecEncCtx*, const byte* info, int sz);
+
+WOLFSSL_API
+int wc_ecc_encrypt(ecc_key* privKey, ecc_key* pubKey, const byte* msg,
+                word32 msgSz, byte* out, word32* outSz, ecEncCtx* ctx);
+WOLFSSL_API
+int wc_ecc_decrypt(ecc_key* privKey, ecc_key* pubKey, const byte* msg,
+                word32 msgSz, byte* out, word32* outSz, ecEncCtx* ctx);
+
+#endif /* HAVE_ECC_ENCRYPT */
+
+#ifdef __cplusplus
+    }    /* extern "C" */
+#endif
+
+#endif /* HAVE_ECC */
+#endif /* WOLF_CRYPT_ECC_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/ed25519.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/ed25519.h
new file mode 100644
index 0000000..6f9a199
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/ed25519.h
@@ -0,0 +1,94 @@
+/* ed25519.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_ED25519_H
+#define WOLF_CRYPT_ED25519_H
+
+#include 
+
+#ifdef HAVE_ED25519
+
+#include 
+#include 
+#include 
+#include 
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+
+/* info about EdDSA curve specifically ed25519, defined as an elliptic curve
+   over GF(p) */
+/*
+    32,                key size
+    "ED25519",         curve name
+    "2^255-19",        prime number
+    "SHA512",          hash function
+    "-121665/121666",  value of d
+*/
+
+#define ED25519_KEY_SIZE 32
+#define ED25519_SIG_SIZE 64
+
+
+/* An ED25519 Key */
+typedef struct {
+    byte    p[32];        /* compressed public key */
+    byte    k[64];        /* private key : 32 secret -- 32 public */
+} ed25519_key;
+
+
+WOLFSSL_API
+int wc_ed25519_make_key(RNG* rng, int keysize, ed25519_key* key);
+WOLFSSL_API
+int wc_ed25519_sign_msg(const byte* in, word32 inlen, byte* out,
+                        word32 *outlen, ed25519_key* key);
+WOLFSSL_API
+int wc_ed25519_verify_msg(byte* sig, word32 siglen, const byte* msg,
+                          word32 msglen, int* stat, ed25519_key* key);
+WOLFSSL_API
+int wc_ed25519_init(ed25519_key* key);
+WOLFSSL_API
+void wc_ed25519_free(ed25519_key* key);
+WOLFSSL_API
+int wc_ed25519_import_public(const byte* in, word32 inLen, ed25519_key* key);
+WOLFSSL_API
+int wc_ed25519_import_private_key(const byte* priv, word32 privSz,
+                               const byte* pub, word32 pubSz, ed25519_key* key);
+WOLFSSL_API
+int wc_ed25519_export_public(ed25519_key*, byte* out, word32* outLen);
+WOLFSSL_API
+int wc_ed25519_export_private_only(ed25519_key* key, byte* out, word32* outLen);
+
+/* size helper */
+WOLFSSL_API
+int wc_ed25519_size(ed25519_key* key);
+WOLFSSL_API
+int wc_ed25519_sig_size(ed25519_key* key);
+
+#ifdef __cplusplus
+    }    /* extern "C" */
+#endif
+
+#endif /* HAVE_ED25519 */
+#endif /* WOLF_CRYPT_ED25519_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/error-crypt.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/error-crypt.h
new file mode 100644
index 0000000..79991fd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/error-crypt.h
@@ -0,0 +1,167 @@
+/* error-crypt.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifndef WOLF_CRYPT_ERROR_H
+#define WOLF_CRYPT_ERROR_H
+
+#include 
+
+#ifdef HAVE_FIPS
+	#include 
+	#define wc_ErrorString    CTaoCryptErrorString
+	#define wc_GetErrorString CTaoCryptGetErrorString
+#endif /* HAVE_FIPS */
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+
+/* error codes */
+enum {
+    MAX_CODE_E         = -100,  /* errors -101 - -299 */
+    OPEN_RAN_E         = -101,  /* opening random device error */
+    READ_RAN_E         = -102,  /* reading random device error */
+    WINCRYPT_E         = -103,  /* windows crypt init error */
+    CRYPTGEN_E         = -104,  /* windows crypt generation error */
+    RAN_BLOCK_E        = -105,  /* reading random device would block */
+    BAD_MUTEX_E        = -106,  /* Bad mutex operation */
+
+    MP_INIT_E          = -110,  /* mp_init error state */
+    MP_READ_E          = -111,  /* mp_read error state */
+    MP_EXPTMOD_E       = -112,  /* mp_exptmod error state */
+    MP_TO_E            = -113,  /* mp_to_xxx error state, can't convert */
+    MP_SUB_E           = -114,  /* mp_sub error state, can't subtract */
+    MP_ADD_E           = -115,  /* mp_add error state, can't add */
+    MP_MUL_E           = -116,  /* mp_mul error state, can't multiply */
+    MP_MULMOD_E        = -117,  /* mp_mulmod error state, can't multiply mod */
+    MP_MOD_E           = -118,  /* mp_mod error state, can't mod */
+    MP_INVMOD_E        = -119,  /* mp_invmod error state, can't inv mod */
+    MP_CMP_E           = -120,  /* mp_cmp error state */
+    MP_ZERO_E          = -121,  /* got a mp zero result, not expected */
+
+    MEMORY_E           = -125,  /* out of memory error */
+
+    RSA_WRONG_TYPE_E   = -130,  /* RSA wrong block type for RSA function */
+    RSA_BUFFER_E       = -131,  /* RSA buffer error, output too small or
+                                   input too large */
+    BUFFER_E           = -132,  /* output buffer too small or input too large */
+    ALGO_ID_E          = -133,  /* setting algo id error */
+    PUBLIC_KEY_E       = -134,  /* setting public key error */
+    DATE_E             = -135,  /* setting date validity error */
+    SUBJECT_E          = -136,  /* setting subject name error */
+    ISSUER_E           = -137,  /* setting issuer  name error */
+    CA_TRUE_E          = -138,  /* setting CA basic constraint true error */
+    EXTENSIONS_E       = -139,  /* setting extensions error */
+
+    ASN_PARSE_E        = -140,  /* ASN parsing error, invalid input */
+    ASN_VERSION_E      = -141,  /* ASN version error, invalid number */
+    ASN_GETINT_E       = -142,  /* ASN get big int error, invalid data */
+    ASN_RSA_KEY_E      = -143,  /* ASN key init error, invalid input */
+    ASN_OBJECT_ID_E    = -144,  /* ASN object id error, invalid id */
+    ASN_TAG_NULL_E     = -145,  /* ASN tag error, not null */
+    ASN_EXPECT_0_E     = -146,  /* ASN expect error, not zero */
+    ASN_BITSTR_E       = -147,  /* ASN bit string error, wrong id */
+    ASN_UNKNOWN_OID_E  = -148,  /* ASN oid error, unknown sum id */
+    ASN_DATE_SZ_E      = -149,  /* ASN date error, bad size */
+    ASN_BEFORE_DATE_E  = -150,  /* ASN date error, current date before */
+    ASN_AFTER_DATE_E   = -151,  /* ASN date error, current date after */
+    ASN_SIG_OID_E      = -152,  /* ASN signature error, mismatched oid */
+    ASN_TIME_E         = -153,  /* ASN time error, unknown time type */
+    ASN_INPUT_E        = -154,  /* ASN input error, not enough data */
+    ASN_SIG_CONFIRM_E  = -155,  /* ASN sig error, confirm failure */
+    ASN_SIG_HASH_E     = -156,  /* ASN sig error, unsupported hash type */
+    ASN_SIG_KEY_E      = -157,  /* ASN sig error, unsupported key type */
+    ASN_DH_KEY_E       = -158,  /* ASN key init error, invalid input */
+    ASN_NTRU_KEY_E     = -159,  /* ASN ntru key decode error, invalid input */
+    ASN_CRIT_EXT_E     = -160,  /* ASN unsupported critical extension */
+
+    ECC_BAD_ARG_E      = -170,  /* ECC input argument of wrong type */
+    ASN_ECC_KEY_E      = -171,  /* ASN ECC bad input */
+    ECC_CURVE_OID_E    = -172,  /* Unsupported ECC OID curve type */
+    BAD_FUNC_ARG       = -173,  /* Bad function argument provided */
+    NOT_COMPILED_IN    = -174,  /* Feature not compiled in */
+    UNICODE_SIZE_E     = -175,  /* Unicode password too big */
+    NO_PASSWORD        = -176,  /* no password provided by user */
+    ALT_NAME_E         = -177,  /* alt name size problem, too big */
+
+    AES_GCM_AUTH_E     = -180,  /* AES-GCM Authentication check failure */
+    AES_CCM_AUTH_E     = -181,  /* AES-CCM Authentication check failure */
+
+    CAVIUM_INIT_E      = -182,  /* Cavium Init type error */
+
+    COMPRESS_INIT_E    = -183,  /* Compress init error */
+    COMPRESS_E         = -184,  /* Compress error */
+    DECOMPRESS_INIT_E  = -185,  /* DeCompress init error */
+    DECOMPRESS_E       = -186,  /* DeCompress error */
+
+    BAD_ALIGN_E         = -187,  /* Bad alignment for operation, no alloc */
+    ASN_NO_SIGNER_E     = -188,  /* ASN no signer to confirm failure */
+    ASN_CRL_CONFIRM_E   = -189,  /* ASN CRL signature confirm failure */
+    ASN_CRL_NO_SIGNER_E = -190,  /* ASN CRL no signer to confirm failure */
+    ASN_OCSP_CONFIRM_E  = -191,  /* ASN OCSP signature confirm failure */
+
+    BAD_ENC_STATE_E     = -192,  /* Bad ecc enc state operation */
+    BAD_PADDING_E       = -193,  /* Bad padding, msg not correct length  */
+
+    REQ_ATTRIBUTE_E     = -194,  /* setting cert request attributes error */
+
+    PKCS7_OID_E         = -195,  /* PKCS#7, mismatched OID error */
+    PKCS7_RECIP_E       = -196,  /* PKCS#7, recipient error */
+    FIPS_NOT_ALLOWED_E  = -197,  /* FIPS not allowed error */
+    ASN_NAME_INVALID_E  = -198,  /* ASN name constraint error */
+
+    RNG_FAILURE_E       = -199,  /* RNG Failed, Reinitialize */
+    HMAC_MIN_KEYLEN_E   = -200,  /* FIPS Mode HMAC Minimum Key Length error */
+    RSA_PAD_E           = -201,  /* RSA Padding Error */
+    LENGTH_ONLY_E       = -202,  /* Returning output length only */
+
+    IN_CORE_FIPS_E      = -203,  /* In Core Integrity check failure */
+    AES_KAT_FIPS_E      = -204,  /* AES KAT failure */
+    DES3_KAT_FIPS_E     = -205,  /* DES3 KAT failure */
+    HMAC_KAT_FIPS_E     = -206,  /* HMAC KAT failure */
+    RSA_KAT_FIPS_E      = -207,  /* RSA KAT failure */
+    DRBG_KAT_FIPS_E     = -208,  /* HASH DRBG KAT failure */
+    DRBG_CONT_FIPS_E    = -209,  /* HASH DRBG Continious test failure */
+    AESGCM_KAT_FIPS_E   = -210,  /* AESGCM KAT failure */
+    THREAD_STORE_KEY_E  = -211,  /* Thread local storage key create failure */
+    THREAD_STORE_SET_E  = -212,  /* Thread local storage key set failure */
+
+    MAC_CMP_FAILED_E    = -213,  /* MAC comparison failed */
+    IS_POINT_E          = -214,  /* ECC is point on curve failed */
+    ECC_INF_E           = -215,  /* ECC point infinity error */
+    ECC_PRIV_KEY_E      = -216,  /* ECC private key not valid error */
+
+    MIN_CODE_E          = -300   /* errors -101 - -299 */
+};
+
+
+WOLFSSL_API void wc_ErrorString(int err, char* buff);
+WOLFSSL_API const char* wc_GetErrorString(int error);
+
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+#endif /* WOLF_CRYPT_ERROR_H */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/fe_operations.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/fe_operations.h
new file mode 100644
index 0000000..a779f2b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/fe_operations.h
@@ -0,0 +1,132 @@
+/* fe_operations.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_FE_OPERATIONS_H
+#define WOLF_CRYPT_FE_OPERATIONS_H
+
+#include 
+
+#if defined(HAVE_CURVE25519) || defined(HAVE_ED25519)
+
+#ifndef CURVED25519_SMALL
+    #include 
+#endif
+#include 
+
+/*
+fe means field element.
+Here the field is \Z/(2^255-19).
+An element t, entries t[0]...t[9], represents the integer
+t[0]+2^26 t[1]+2^51 t[2]+2^77 t[3]+2^102 t[4]+...+2^230 t[9].
+Bounds on each t[i] vary depending on context.
+*/
+
+#ifdef CURVED25519_SMALL
+    #define F25519_SIZE	32
+    typedef byte     fe[32];
+#else
+    typedef int32_t  fe[10];
+#endif
+
+WOLFSSL_LOCAL int  curve25519(byte * q, byte * n, byte * p);
+WOLFSSL_LOCAL void fe_copy(fe, const fe);
+WOLFSSL_LOCAL void fe_add(fe, const fe, const fe);
+WOLFSSL_LOCAL void fe_neg(fe,const fe);
+WOLFSSL_LOCAL void fe_sub(fe, const fe, const fe);
+WOLFSSL_LOCAL void fe_invert(fe, const fe);
+WOLFSSL_LOCAL void fe_mul(fe,const fe,const fe);
+
+/* default to be faster but take more memory */
+#ifndef CURVED25519_SMALL
+
+/* Based On Daniel J Bernstein's curve25519 and ed25519 Public Domain ref10
+   work. */
+
+WOLFSSL_LOCAL void fe_0(fe);
+WOLFSSL_LOCAL void fe_1(fe);
+WOLFSSL_LOCAL int  fe_isnonzero(const fe);
+WOLFSSL_LOCAL int  fe_isnegative(const fe);
+WOLFSSL_LOCAL void fe_tobytes(unsigned char *, const fe);
+WOLFSSL_LOCAL void fe_sq(fe, const fe);
+WOLFSSL_LOCAL void fe_sq2(fe,const fe);
+WOLFSSL_LOCAL void fe_frombytes(fe,const unsigned char *);
+WOLFSSL_LOCAL void fe_cswap(fe,fe,unsigned int);
+WOLFSSL_LOCAL void fe_mul121666(fe,fe);
+WOLFSSL_LOCAL void fe_cmov(fe,const fe,unsigned int);
+WOLFSSL_LOCAL void fe_pow22523(fe,const fe);
+
+/* 64 type needed for SHA512 */
+WOLFSSL_LOCAL uint64_t load_3(const unsigned char *in);
+WOLFSSL_LOCAL uint64_t load_4(const unsigned char *in);
+#endif /* not defined CURVED25519_SMALL */
+
+/* Use less memory and only 32bit types or less, but is slower
+   Based on Daniel Beer's public domain work. */
+#ifdef CURVED25519_SMALL
+static const byte c25519_base_x[F25519_SIZE] = {9};
+static const byte f25519_zero[F25519_SIZE]   = {0};
+static const byte f25519_one[F25519_SIZE]    = {1};
+static const byte fprime_zero[F25519_SIZE]   = {0};
+static const byte fprime_one[F25519_SIZE]    = {1};
+
+WOLFSSL_LOCAL void fe_load(byte *x, word32 c);
+WOLFSSL_LOCAL void fe_normalize(byte *x);
+WOLFSSL_LOCAL void fe_inv__distinct(byte *r, const byte *x);
+
+/* Conditional copy. If condition == 0, then zero is copied to dst. If
+ * condition == 1, then one is copied to dst. Any other value results in
+ * undefined behaviour.
+ */
+WOLFSSL_LOCAL void fe_select(byte *dst, const byte *zero, const byte *one,
+		   byte condition);
+
+/* Multiply a point by a small constant. The two pointers are not
+ * required to be distinct.
+ *
+ * The constant must be less than 2^24.
+ */
+WOLFSSL_LOCAL void fe_mul_c(byte *r, const byte *a, word32 b);
+WOLFSSL_LOCAL void fe_mul__distinct(byte *r, const byte *a, const byte *b);
+
+/* Compute one of the square roots of the field element, if the element
+ * is square. The other square is -r.
+ *
+ * If the input is not square, the returned value is a valid field
+ * element, but not the correct answer. If you don't already know that
+ * your element is square, you should square the return value and test.
+ */
+WOLFSSL_LOCAL void fe_sqrt(byte *r, const byte *x);
+
+/* Conditional copy. If condition == 0, then zero is copied to dst. If
+ * condition == 1, then one is copied to dst. Any other value results in
+ * undefined behaviour.
+ */
+WOLFSSL_LOCAL void fprime_select(byte *dst, const byte *zero, const byte *one,
+		                         byte condition);
+WOLFSSL_LOCAL void fprime_add(byte *r, const byte *a, const byte *modulus);
+WOLFSSL_LOCAL void fprime_sub(byte *r, const byte *a, const byte *modulus);
+WOLFSSL_LOCAL void fprime_mul(byte *r, const byte *a, const byte *b,
+		                      const byte *modulus);
+WOLFSSL_LOCAL void fprime_copy(byte *x, const byte *a);
+#endif /* CURVED25519_SMALL */
+#endif /* HAVE_CURVE25519 or HAVE_ED25519 */
+#endif /* WOLF_CRYPT_FE_OPERATIONS_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/fips_test.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/fips_test.h
new file mode 100644
index 0000000..6ef0678
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/fips_test.h
@@ -0,0 +1,58 @@
+/* fips_test.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifndef WOLF_CRYPT_FIPS_TEST_H
+#define WOLF_CRYPT_FIPS_TEST_H
+
+#include 
+
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+/* Known Answer Test string inputs are hex, internal */
+CYASSL_LOCAL int DoKnownAnswerTests(char*, int);
+
+
+/* FIPS failure callback */
+typedef void(*wolfCrypt_fips_cb)(int ok, int err, const char* hash);
+
+/* Public set function */
+CYASSL_API int wolfCrypt_SetCb_fips(wolfCrypt_fips_cb cbf);
+
+/* Public get status functions */
+CYASSL_API int wolfCrypt_GetStatus_fips(void);
+CYASSL_API const char* wolfCrypt_GetCoreHash_fips(void);
+
+#ifdef HAVE_FORCE_FIPS_FAILURE
+    /* Public function to force failure mode for operational testing */
+    CYASSL_API int wolfCrypt_SetStatus_fips(int);
+#endif
+
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* WOLF_CRYPT_FIPS_TEST_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/ge_operations.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/ge_operations.h
new file mode 100644
index 0000000..00d1b3e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/ge_operations.h
@@ -0,0 +1,115 @@
+/* ge_operations.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+ /* Based On Daniel J Bernstein's ed25519 Public Domain ref10 work. */
+
+#ifndef WOLF_CRYPT_GE_OPERATIONS_H
+#define WOLF_CRYPT_GE_OPERATIONS_H
+
+#include 
+
+#ifdef HAVE_ED25519
+
+#ifndef CURVED25519_SMALL
+    #include 
+#endif
+#include 
+
+/*
+ge means group element.
+
+Here the group is the set of pairs (x,y) of field elements (see fe.h)
+satisfying -x^2 + y^2 = 1 + d x^2y^2
+where d = -121665/121666.
+
+Representations:
+  ge_p2 (projective): (X:Y:Z) satisfying x=X/Z, y=Y/Z
+  ge_p3 (extended): (X:Y:Z:T) satisfying x=X/Z, y=Y/Z, XY=ZT
+  ge_p1p1 (completed): ((X:Z),(Y:T)) satisfying x=X/Z, y=Y/T
+  ge_precomp (Duif): (y+x,y-x,2dxy)
+*/
+
+
+typedef struct {
+  fe X;
+  fe Y;
+  fe Z;
+} ge_p2;
+
+typedef struct {
+  fe X;
+  fe Y;
+  fe Z;
+  fe T;
+} ge_p3;
+
+WOLFSSL_LOCAL int  ge_compress_key(byte* out, const byte* xIn, const byte* yIn,
+                                                                word32 keySz);
+WOLFSSL_LOCAL int  ge_frombytes_negate_vartime(ge_p3 *,const unsigned char *);
+
+WOLFSSL_LOCAL int  ge_double_scalarmult_vartime(ge_p2 *,const unsigned char *,
+                                         const ge_p3 *,const unsigned char *);
+WOLFSSL_LOCAL void ge_scalarmult_base(ge_p3 *,const unsigned char *);
+WOLFSSL_LOCAL void sc_reduce(byte* s);
+WOLFSSL_LOCAL void sc_muladd(byte* s, const byte* a, const byte* b,
+                             const byte* c);
+WOLFSSL_LOCAL void ge_tobytes(unsigned char *,const ge_p2 *);
+WOLFSSL_LOCAL void ge_p3_tobytes(unsigned char *,const ge_p3 *);
+
+#ifndef CURVED25519_SMALL
+typedef struct {
+  fe X;
+  fe Y;
+  fe Z;
+  fe T;
+} ge_p1p1;
+
+typedef struct {
+  fe yplusx;
+  fe yminusx;
+  fe xy2d;
+} ge_precomp;
+
+typedef struct {
+  fe YplusX;
+  fe YminusX;
+  fe Z;
+  fe T2d;
+} ge_cached;
+
+WOLFSSL_LOCAL void ge_p2_0(ge_p2 *);
+WOLFSSL_LOCAL void ge_p3_0(ge_p3 *);
+WOLFSSL_LOCAL void ge_precomp_0(ge_precomp *);
+WOLFSSL_LOCAL void ge_p3_to_p2(ge_p2 *,const ge_p3 *);
+WOLFSSL_LOCAL void ge_p3_to_cached(ge_cached *,const ge_p3 *);
+WOLFSSL_LOCAL void ge_p1p1_to_p2(ge_p2 *,const ge_p1p1 *);
+WOLFSSL_LOCAL void ge_p1p1_to_p3(ge_p3 *,const ge_p1p1 *);
+WOLFSSL_LOCAL void ge_p2_dbl(ge_p1p1 *,const ge_p2 *);
+WOLFSSL_LOCAL void ge_p3_dbl(ge_p1p1 *,const ge_p3 *);
+
+WOLFSSL_LOCAL void ge_madd(ge_p1p1 *,const ge_p3 *,const ge_precomp *);
+WOLFSSL_LOCAL void ge_msub(ge_p1p1 *,const ge_p3 *,const ge_precomp *);
+WOLFSSL_LOCAL void ge_add(ge_p1p1 *,const ge_p3 *,const ge_cached *);
+WOLFSSL_LOCAL void ge_sub(ge_p1p1 *,const ge_p3 *,const ge_cached *);
+#endif /* no CURVED25519_SMALL */
+#endif /* HAVE_ED25519 */
+#endif /* WOLF_CRYPT_GE_OPERATIONS_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/hash.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/hash.h
new file mode 100644
index 0000000..ad10628
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/hash.h
@@ -0,0 +1,41 @@
+/* hash.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_HASH_H
+#define WOLF_CRYPT_HASH_H
+
+#ifndef NO_MD5
+#include 
+WOLFSSL_API void wc_Md5GetHash(Md5*, byte*);
+WOLFSSL_API void wc_Md5RestorePos(Md5*, Md5*) ;
+#endif
+#ifndef NO_SHA
+#include 
+WOLFSSL_API int wc_ShaGetHash(Sha*, byte*);
+WOLFSSL_API void wc_ShaRestorePos(Sha*, Sha*) ;
+#endif
+#ifndef NO_SHA256
+#include 
+WOLFSSL_API int wc_Sha256GetHash(Sha256*, byte*);
+WOLFSSL_API void wc_Sha256RestorePos(Sha256*, Sha256*) ;
+#endif
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/hc128.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/hc128.h
new file mode 100644
index 0000000..ba53dd3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/hc128.h
@@ -0,0 +1,58 @@
+/* hc128.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_HC128_H
+#define WOLF_CRYPT_HC128_H
+
+#include 
+
+#ifndef NO_HC128
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+enum {
+	HC128_ENC_TYPE    =  6    /* cipher unique type */
+};
+
+/* HC-128 stream cipher */
+typedef struct HC128 {
+    word32 T[1024];             /* P[i] = T[i];  Q[i] = T[1024 + i ]; */
+    word32 X[16];
+    word32 Y[16];
+    word32 counter1024;         /* counter1024 = i mod 1024 at the ith step */
+    word32 key[8];
+    word32 iv[8];
+} HC128;
+
+
+WOLFSSL_API int wc_Hc128_Process(HC128*, byte*, const byte*, word32);
+WOLFSSL_API int wc_Hc128_SetKey(HC128*, const byte* key, const byte* iv);
+
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* HAVE_HC128 */
+#endif /* WOLF_CRYPT_HC128_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/hmac.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/hmac.h
new file mode 100644
index 0000000..2be5afc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/hmac.h
@@ -0,0 +1,190 @@
+/* hmac.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifndef NO_HMAC
+
+#ifndef WOLF_CRYPT_HMAC_H
+#define WOLF_CRYPT_HMAC_H
+
+#include 
+
+#ifndef NO_MD5
+    #include 
+#endif
+
+#ifndef NO_SHA
+    #include 
+#endif
+
+#ifndef NO_SHA256
+    #include 
+#endif
+
+#ifdef WOLFSSL_SHA512
+    #include 
+#endif
+
+#ifdef HAVE_BLAKE2
+    #include 
+#endif
+
+#ifdef HAVE_FIPS
+/* for fips */
+    #include 
+#endif
+
+#ifdef HAVE_CAVIUM
+    #include 
+    #include "cavium_common.h"
+#endif
+
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+#ifndef HAVE_FIPS
+#define WOLFSSL_HMAC_CAVIUM_MAGIC 0xBEEF0005
+
+enum {
+    HMAC_FIPS_MIN_KEY = 14,   /* 112 bit key length minimum */
+
+    IPAD    = 0x36,
+    OPAD    = 0x5C,
+
+/* If any hash is not enabled, add the ID here. */
+#ifdef NO_MD5
+    MD5     = 0,
+#endif
+#ifdef NO_SHA
+    SHA     = 1,
+#endif
+#ifdef NO_SHA256
+    SHA256  = 2,
+#endif
+#ifndef WOLFSSL_SHA512
+    SHA512  = 4,
+#endif
+#ifndef WOLFSSL_SHA384
+    SHA384  = 5,
+#endif
+#ifndef HAVE_BLAKE2
+    BLAKE2B_ID = 7,
+#endif
+
+/* Select the largest available hash for the buffer size. */
+#if defined(WOLFSSL_SHA512)
+    MAX_DIGEST_SIZE = SHA512_DIGEST_SIZE,
+    HMAC_BLOCK_SIZE = SHA512_BLOCK_SIZE
+#elif defined(HAVE_BLAKE2)
+    MAX_DIGEST_SIZE = BLAKE2B_OUTBYTES,
+    HMAC_BLOCK_SIZE = BLAKE2B_BLOCKBYTES,
+#elif defined(WOLFSSL_SHA384)
+    MAX_DIGEST_SIZE = SHA384_DIGEST_SIZE,
+    HMAC_BLOCK_SIZE = SHA384_BLOCK_SIZE
+#elif !defined(NO_SHA256)
+    MAX_DIGEST_SIZE = SHA256_DIGEST_SIZE,
+    HMAC_BLOCK_SIZE = SHA256_BLOCK_SIZE
+#elif !defined(NO_SHA)
+    MAX_DIGEST_SIZE = SHA_DIGEST_SIZE,
+    HMAC_BLOCK_SIZE = SHA_BLOCK_SIZE
+#elif !defined(NO_MD5)
+    MAX_DIGEST_SIZE = MD5_DIGEST_SIZE,
+    HMAC_BLOCK_SIZE = MD5_BLOCK_SIZE
+#else
+    #error "You have to have some kind of hash if you want to use HMAC."
+#endif
+};
+
+
+/* hash union */
+typedef union {
+    #ifndef NO_MD5
+        Md5 md5;
+    #endif
+    #ifndef NO_SHA
+        Sha sha;
+    #endif
+    #ifndef NO_SHA256
+        Sha256 sha256;
+    #endif
+    #ifdef WOLFSSL_SHA384
+        Sha384 sha384;
+    #endif
+    #ifdef WOLFSSL_SHA512
+        Sha512 sha512;
+    #endif
+    #ifdef HAVE_BLAKE2
+        Blake2b blake2b;
+    #endif
+} Hash;
+
+/* Hmac digest */
+typedef struct Hmac {
+    Hash    hash;
+    word32  ipad[HMAC_BLOCK_SIZE  / sizeof(word32)];  /* same block size all*/
+    word32  opad[HMAC_BLOCK_SIZE  / sizeof(word32)];
+    word32  innerHash[MAX_DIGEST_SIZE / sizeof(word32)];
+    byte    macType;                                     /* md5 sha or sha256 */
+    byte    innerHashKeyed;                              /* keyed flag */
+#ifdef HAVE_CAVIUM
+    word16   keyLen;          /* hmac key length */
+    word16   dataLen;
+    HashType type;            /* hmac key type */
+    int      devId;           /* nitrox device id */
+    word32   magic;           /* using cavium magic */
+    word64   contextHandle;   /* nitrox context memory handle */
+    byte*    data;            /* buffered input data for one call */
+#endif
+} Hmac;
+
+#endif /* HAVE_FIPS */
+
+/* does init */
+WOLFSSL_API int wc_HmacSetKey(Hmac*, int type, const byte* key, word32 keySz);
+WOLFSSL_API int wc_HmacUpdate(Hmac*, const byte*, word32);
+WOLFSSL_API int wc_HmacFinal(Hmac*, byte*);
+
+#ifdef HAVE_CAVIUM
+    WOLFSSL_API int  wc_HmacInitCavium(Hmac*, int);
+    WOLFSSL_API void wc_HmacFreeCavium(Hmac*);
+#endif
+
+WOLFSSL_API int wolfSSL_GetHmacMaxSize(void);
+
+
+#ifdef HAVE_HKDF
+
+WOLFSSL_API int wc_HKDF(int type, const byte* inKey, word32 inKeySz,
+                    const byte* salt, word32 saltSz,
+                    const byte* info, word32 infoSz,
+                    byte* out, word32 outSz);
+
+#endif /* HAVE_HKDF */
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* WOLF_CRYPT_HMAC_H */
+
+#endif /* NO_HMAC */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/include.am b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/include.am
new file mode 100644
index 0000000..1f3a726
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/include.am
@@ -0,0 +1,59 @@
+# vim:ft=automake
+# All paths should be given relative to the root
+
+nobase_include_HEADERS+= \
+                         wolfssl/wolfcrypt/aes.h \
+                         wolfssl/wolfcrypt/arc4.h \
+                         wolfssl/wolfcrypt/asn.h \
+                         wolfssl/wolfcrypt/asn_public.h \
+                         wolfssl/wolfcrypt/poly1305.h \
+                         wolfssl/wolfcrypt/camellia.h \
+                         wolfssl/wolfcrypt/coding.h \
+                         wolfssl/wolfcrypt/compress.h \
+                         wolfssl/wolfcrypt/des3.h \
+                         wolfssl/wolfcrypt/dh.h \
+                         wolfssl/wolfcrypt/dsa.h \
+                         wolfssl/wolfcrypt/ecc.h \
+                         wolfssl/wolfcrypt/curve25519.h \
+                         wolfssl/wolfcrypt/ed25519.h \
+                         wolfssl/wolfcrypt/fe_operations.h \
+                         wolfssl/wolfcrypt/ge_operations.h \
+                         wolfssl/wolfcrypt/error-crypt.h \
+                         wolfssl/wolfcrypt/fips_test.h \
+                         wolfssl/wolfcrypt/hash.h \
+                         wolfssl/wolfcrypt/hc128.h \
+                         wolfssl/wolfcrypt/hmac.h \
+                         wolfssl/wolfcrypt/integer.h \
+                         wolfssl/wolfcrypt/md2.h \
+                         wolfssl/wolfcrypt/md4.h \
+                         wolfssl/wolfcrypt/md5.h \
+                         wolfssl/wolfcrypt/misc.h \
+                         wolfssl/wolfcrypt/pkcs7.h \
+                         wolfssl/wolfcrypt/wc_port.h \
+                         wolfssl/wolfcrypt/pwdbased.h \
+                         wolfssl/wolfcrypt/rabbit.h \
+                         wolfssl/wolfcrypt/chacha.h \
+                         wolfssl/wolfcrypt/chacha20_poly1305.h \
+                         wolfssl/wolfcrypt/random.h \
+                         wolfssl/wolfcrypt/ripemd.h \
+                         wolfssl/wolfcrypt/rsa.h \
+                         wolfssl/wolfcrypt/settings.h \
+                         wolfssl/wolfcrypt/sha256.h \
+                         wolfssl/wolfcrypt/sha512.h \
+                         wolfssl/wolfcrypt/sha.h \
+                         wolfssl/wolfcrypt/blake2.h \
+                         wolfssl/wolfcrypt/blake2-int.h \
+                         wolfssl/wolfcrypt/blake2-impl.h \
+                         wolfssl/wolfcrypt/tfm.h \
+                         wolfssl/wolfcrypt/types.h \
+                         wolfssl/wolfcrypt/visibility.h \
+                         wolfssl/wolfcrypt/logging.h \
+                         wolfssl/wolfcrypt/memory.h \
+                         wolfssl/wolfcrypt/mpi_class.h \
+                         wolfssl/wolfcrypt/mpi_superclass.h
+
+noinst_HEADERS+= \
+                         wolfssl/wolfcrypt/port/pic32/pic32mz-crypt.h \
+                         wolfssl/wolfcrypt/port/ti/ti-hash.h \
+                         wolfssl/wolfcrypt/port/ti/ti-ccm.h
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/integer.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/integer.h
new file mode 100644
index 0000000..b623298
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/integer.h
@@ -0,0 +1,324 @@
+/* integer.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+/*
+ * Based on public domain LibTomMath 0.38 by Tom St Denis, tomstdenis@iahu.ca,
+ * http://math.libtomcrypt.com
+ */
+
+
+#ifndef WOLF_CRYPT_INTEGER_H
+#define WOLF_CRYPT_INTEGER_H
+
+/* may optionally use fast math instead, not yet supported on all platforms and
+   may not be faster on all
+*/
+#include        /* will set MP_xxBIT if not default */
+#ifdef USE_FAST_MATH
+    #include 
+#else
+
+#ifndef CHAR_BIT
+    #include 
+#endif
+
+#include 
+
+#ifndef MIN
+   #define MIN(x,y) ((x)<(y)?(x):(y))
+#endif
+
+#ifndef MAX
+   #define MAX(x,y) ((x)>(y)?(x):(y))
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+
+/* C++ compilers don't like assigning void * to mp_digit * */
+#define  OPT_CAST(x)  (x *)
+
+#else
+
+/* C on the other hand doesn't care */
+#define  OPT_CAST(x)
+
+#endif
+
+
+/* detect 64-bit mode if possible */
+#if defined(__x86_64__)
+   #if !(defined(MP_64BIT) && defined(MP_16BIT) && defined(MP_8BIT))
+      #define MP_64BIT
+   #endif
+#endif
+/* if intel compiler doesn't provide 128 bit type don't turn on 64bit */
+#if defined(MP_64BIT) && defined(__INTEL_COMPILER) && !defined(HAVE___UINT128_T)
+    #undef MP_64BIT
+#endif
+
+/* some default configurations.
+ *
+ * A "mp_digit" must be able to hold DIGIT_BIT + 1 bits
+ * A "mp_word" must be able to hold 2*DIGIT_BIT + 1 bits
+ *
+ * At the very least a mp_digit must be able to hold 7 bits
+ * [any size beyond that is ok provided it doesn't overflow the data type]
+ */
+#ifdef MP_8BIT
+   typedef unsigned char      mp_digit;
+   typedef unsigned short     mp_word;
+#elif defined(MP_16BIT) || defined(NO_64BIT)
+   typedef unsigned short     mp_digit;
+   typedef unsigned int       mp_word;
+#elif defined(MP_64BIT)
+   /* for GCC only on supported platforms */
+   typedef unsigned long long mp_digit;  /* 64 bit type, 128 uses mode(TI) */
+   typedef unsigned long      mp_word __attribute__ ((mode(TI)));
+
+   #define DIGIT_BIT          60
+#else
+   /* this is the default case, 28-bit digits */
+
+   #if defined(_MSC_VER) || defined(__BORLANDC__)
+      typedef unsigned __int64   ulong64;
+   #else
+      typedef unsigned long long ulong64;
+   #endif
+
+   typedef unsigned int       mp_digit;  /* long could be 64 now, changed TAO */
+   typedef ulong64            mp_word;
+
+#ifdef MP_31BIT
+   /* this is an extension that uses 31-bit digits */
+   #define DIGIT_BIT          31
+#else
+   /* default case is 28-bit digits, defines MP_28BIT as a handy test macro */
+   #define DIGIT_BIT          28
+   #define MP_28BIT
+#endif
+#endif
+
+
+/* otherwise the bits per digit is calculated automatically from the size of
+   a mp_digit */
+#ifndef DIGIT_BIT
+   #define DIGIT_BIT ((int)((CHAR_BIT * sizeof(mp_digit) - 1)))
+      /* bits per digit */
+#endif
+
+#define MP_DIGIT_BIT     DIGIT_BIT
+#define MP_MASK          ((((mp_digit)1)<<((mp_digit)DIGIT_BIT))-((mp_digit)1))
+#define MP_DIGIT_MAX     MP_MASK
+
+/* equalities */
+#define MP_LT        -1   /* less than */
+#define MP_EQ         0   /* equal to */
+#define MP_GT         1   /* greater than */
+
+#define MP_ZPOS       0   /* positive integer */
+#define MP_NEG        1   /* negative */
+
+#define MP_OKAY       0   /* ok result */
+#define MP_MEM        -2  /* out of mem */
+#define MP_VAL        -3  /* invalid input */
+#define MP_RANGE      MP_VAL
+
+#define MP_YES        1   /* yes response */
+#define MP_NO         0   /* no response */
+
+/* Primality generation flags */
+#define LTM_PRIME_BBS      0x0001 /* BBS style prime */
+#define LTM_PRIME_SAFE     0x0002 /* Safe prime (p-1)/2 == prime */
+#define LTM_PRIME_2MSB_ON  0x0008 /* force 2nd MSB to 1 */
+
+typedef int           mp_err;
+
+/* define this to use lower memory usage routines (exptmods mostly) */
+#define MP_LOW_MEM
+
+/* default precision */
+#ifndef MP_PREC
+   #ifndef MP_LOW_MEM
+      #define MP_PREC                 32     /* default digits of precision */
+   #else
+      #define MP_PREC                 1      /* default digits of precision */
+   #endif
+#endif
+
+/* size of comba arrays, should be at least 2 * 2**(BITS_PER_WORD -
+   BITS_PER_DIGIT*2) */
+#define MP_WARRAY  (1 << (sizeof(mp_word) * CHAR_BIT - 2 * DIGIT_BIT + 1))
+
+/* the infamous mp_int structure */
+typedef struct  {
+    int used, alloc, sign;
+    mp_digit *dp;
+} mp_int;
+
+/* callback for mp_prime_random, should fill dst with random bytes and return
+   how many read [upto len] */
+typedef int ltm_prime_callback(unsigned char *dst, int len, void *dat);
+
+
+#define USED(m)    ((m)->used)
+#define DIGIT(m,k) ((m)->dp[(k)])
+#define SIGN(m)    ((m)->sign)
+
+
+/* ---> Basic Manipulations <--- */
+#define mp_iszero(a) (((a)->used == 0) ? MP_YES : MP_NO)
+#define mp_iseven(a) \
+    (((a)->used > 0 && (((a)->dp[0] & 1) == 0)) ? MP_YES : MP_NO)
+#define mp_isodd(a) \
+    (((a)->used > 0 && (((a)->dp[0] & 1) == 1)) ? MP_YES : MP_NO)
+
+
+/* number of primes */
+#ifdef MP_8BIT
+   #define PRIME_SIZE      31
+#else
+   #define PRIME_SIZE      256
+#endif
+
+#define mp_prime_random(a, t, size, bbs, cb, dat) \
+   mp_prime_random_ex(a, t, ((size) * 8) + 1, (bbs==1)?LTM_PRIME_BBS:0, cb, dat)
+
+#define mp_read_raw(mp, str, len) mp_read_signed_bin((mp), (str), (len))
+#define mp_raw_size(mp)           mp_signed_bin_size(mp)
+#define mp_toraw(mp, str)         mp_to_signed_bin((mp), (str))
+#define mp_read_mag(mp, str, len) mp_read_unsigned_bin((mp), (str), (len))
+#define mp_mag_size(mp)           mp_unsigned_bin_size(mp)
+#define mp_tomag(mp, str)         mp_to_unsigned_bin((mp), (str))
+
+#define mp_tobinary(M, S)  mp_toradix((M), (S), 2)
+#define mp_tooctal(M, S)   mp_toradix((M), (S), 8)
+#define mp_todecimal(M, S) mp_toradix((M), (S), 10)
+#define mp_tohex(M, S)     mp_toradix((M), (S), 16)
+
+#define s_mp_mul(a, b, c) s_mp_mul_digs(a, b, c, (a)->used + (b)->used + 1)
+
+extern const char *mp_s_rmap;
+
+/* 6 functions needed by Rsa */
+int  mp_init (mp_int * a);
+void mp_clear (mp_int * a);
+int  mp_unsigned_bin_size(mp_int * a);
+int  mp_read_unsigned_bin (mp_int * a, const unsigned char *b, int c);
+int  mp_to_unsigned_bin (mp_int * a, unsigned char *b);
+int  mp_exptmod (mp_int * G, mp_int * X, mp_int * P, mp_int * Y);
+/* end functions needed by Rsa */
+
+/* functions added to support above needed, removed TOOM and KARATSUBA */
+int  mp_count_bits (mp_int * a);
+int  mp_leading_bit (mp_int * a);
+int  mp_init_copy (mp_int * a, mp_int * b);
+int  mp_copy (mp_int * a, mp_int * b);
+int  mp_grow (mp_int * a, int size);
+int  mp_div_2d (mp_int * a, int b, mp_int * c, mp_int * d);
+void mp_zero (mp_int * a);
+void mp_clamp (mp_int * a);
+void mp_exch (mp_int * a, mp_int * b);
+void mp_rshd (mp_int * a, int b);
+void mp_rshb (mp_int * a, int b);
+int  mp_mod_2d (mp_int * a, int b, mp_int * c);
+int  mp_mul_2d (mp_int * a, int b, mp_int * c);
+int  mp_lshd (mp_int * a, int b);
+int  mp_abs (mp_int * a, mp_int * b);
+int  mp_invmod (mp_int * a, mp_int * b, mp_int * c);
+int  fast_mp_invmod (mp_int * a, mp_int * b, mp_int * c);
+int  mp_invmod_slow (mp_int * a, mp_int * b, mp_int * c);
+int  mp_cmp_mag (mp_int * a, mp_int * b);
+int  mp_cmp (mp_int * a, mp_int * b);
+int  mp_cmp_d(mp_int * a, mp_digit b);
+void mp_set (mp_int * a, mp_digit b);
+int  mp_mod (mp_int * a, mp_int * b, mp_int * c);
+int  mp_div(mp_int * a, mp_int * b, mp_int * c, mp_int * d);
+int  mp_div_2(mp_int * a, mp_int * b);
+int  mp_add (mp_int * a, mp_int * b, mp_int * c);
+int  s_mp_add (mp_int * a, mp_int * b, mp_int * c);
+int  s_mp_sub (mp_int * a, mp_int * b, mp_int * c);
+int  mp_sub (mp_int * a, mp_int * b, mp_int * c);
+int  mp_reduce_is_2k_l(mp_int *a);
+int  mp_reduce_is_2k(mp_int *a);
+int  mp_dr_is_modulus(mp_int *a);
+int  mp_exptmod_fast (mp_int * G, mp_int * X, mp_int * P, mp_int * Y, int);
+int  mp_montgomery_setup (mp_int * n, mp_digit * rho);
+int  fast_mp_montgomery_reduce (mp_int * x, mp_int * n, mp_digit rho);
+int  mp_montgomery_reduce (mp_int * x, mp_int * n, mp_digit rho);
+void mp_dr_setup(mp_int *a, mp_digit *d);
+int  mp_dr_reduce (mp_int * x, mp_int * n, mp_digit k);
+int  mp_reduce_2k(mp_int *a, mp_int *n, mp_digit d);
+int  fast_s_mp_mul_high_digs (mp_int * a, mp_int * b, mp_int * c, int digs);
+int  s_mp_mul_high_digs (mp_int * a, mp_int * b, mp_int * c, int digs);
+int  mp_reduce_2k_setup_l(mp_int *a, mp_int *d);
+int  mp_reduce_2k_l(mp_int *a, mp_int *n, mp_int *d);
+int  mp_reduce (mp_int * x, mp_int * m, mp_int * mu);
+int  mp_reduce_setup (mp_int * a, mp_int * b);
+int  s_mp_exptmod (mp_int * G, mp_int * X, mp_int * P, mp_int * Y, int redmode);
+int  mp_montgomery_calc_normalization (mp_int * a, mp_int * b);
+int  s_mp_mul_digs (mp_int * a, mp_int * b, mp_int * c, int digs);
+int  s_mp_sqr (mp_int * a, mp_int * b);
+int  fast_s_mp_mul_digs (mp_int * a, mp_int * b, mp_int * c, int digs);
+int  fast_s_mp_sqr (mp_int * a, mp_int * b);
+int  mp_init_size (mp_int * a, int size);
+int  mp_div_3 (mp_int * a, mp_int *c, mp_digit * d);
+int  mp_mul_2(mp_int * a, mp_int * b);
+int  mp_mul (mp_int * a, mp_int * b, mp_int * c);
+int  mp_sqr (mp_int * a, mp_int * b);
+int  mp_mulmod (mp_int * a, mp_int * b, mp_int * c, mp_int * d);
+int  mp_mul_d (mp_int * a, mp_digit b, mp_int * c);
+int  mp_2expt (mp_int * a, int b);
+int  mp_reduce_2k_setup(mp_int *a, mp_digit *d);
+int  mp_add_d (mp_int* a, mp_digit b, mp_int* c);
+int mp_set_int (mp_int * a, unsigned long b);
+int mp_sub_d (mp_int * a, mp_digit b, mp_int * c);
+/* end support added functions */
+
+/* added */
+int mp_init_multi(mp_int* a, mp_int* b, mp_int* c, mp_int* d, mp_int* e,
+                  mp_int* f);
+
+#if defined(HAVE_ECC) || defined(WOLFSSL_KEY_GEN)
+    int mp_sqrmod(mp_int* a, mp_int* b, mp_int* c);
+#endif
+#ifdef HAVE_ECC
+    int mp_read_radix(mp_int* a, const char* str, int radix);
+#endif
+
+#ifdef WOLFSSL_KEY_GEN
+    int mp_prime_is_prime (mp_int * a, int t, int *result);
+    int mp_gcd (mp_int * a, mp_int * b, mp_int * c);
+    int mp_lcm (mp_int * a, mp_int * b, mp_int * c);
+#endif
+
+int mp_cnt_lsb(mp_int *a);
+int mp_mod_d(mp_int* a, mp_digit b, mp_digit* c);
+
+#ifdef __cplusplus
+   }
+#endif
+
+
+#endif /* USE_FAST_MATH */
+
+#endif  /* WOLF_CRYPT_INTEGER_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/logging.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/logging.h
new file mode 100644
index 0000000..0b12483
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/logging.h
@@ -0,0 +1,70 @@
+/* logging.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+/* submitted by eof */
+
+
+#ifndef WOLFSSL_LOGGING_H
+#define WOLFSSL_LOGGING_H
+
+#include 
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+
+enum  CYA_Log_Levels {
+    ERROR_LOG = 0,
+    INFO_LOG,
+    ENTER_LOG,
+    LEAVE_LOG,
+    OTHER_LOG
+};
+
+typedef void (*wolfSSL_Logging_cb)(const int logLevel,
+                                  const char *const logMessage);
+
+WOLFSSL_API int wolfSSL_SetLoggingCb(wolfSSL_Logging_cb log_function);
+
+#ifdef DEBUG_WOLFSSL
+
+    void WOLFSSL_ENTER(const char* msg);
+    void WOLFSSL_LEAVE(const char* msg, int ret);
+
+    void WOLFSSL_ERROR(int);
+    void WOLFSSL_MSG(const char* msg);
+
+#else /* DEBUG_WOLFSSL   */
+
+    #define WOLFSSL_ENTER(m)
+    #define WOLFSSL_LEAVE(m, r)
+
+    #define WOLFSSL_ERROR(e)
+    #define WOLFSSL_MSG(m)
+
+#endif /* DEBUG_WOLFSSL  */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* WOLFSSL_LOGGING_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/md2.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/md2.h
new file mode 100644
index 0000000..d494078
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/md2.h
@@ -0,0 +1,64 @@
+/* md2.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_MD2_H
+#define WOLF_CRYPT_MD2_H
+
+#include 
+
+#ifdef WOLFSSL_MD2
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+/* in bytes */
+enum {
+    MD2             =  6,    /* hash type unique */
+    MD2_BLOCK_SIZE  = 16,
+    MD2_DIGEST_SIZE = 16,
+    MD2_PAD_SIZE    = 16,
+    MD2_X_SIZE      = 48
+};
+
+
+/* Md2 digest */
+typedef struct Md2 {
+    word32  count;   /* bytes % PAD_SIZE  */
+    byte    X[MD2_X_SIZE];
+    byte    C[MD2_BLOCK_SIZE];
+    byte    buffer[MD2_BLOCK_SIZE];
+} Md2;
+
+
+WOLFSSL_API void wc_InitMd2(Md2*);
+WOLFSSL_API void wc_Md2Update(Md2*, const byte*, word32);
+WOLFSSL_API void wc_Md2Final(Md2*, byte*);
+WOLFSSL_API int  wc_Md2Hash(const byte*, word32, byte*);
+
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* WOLFSSL_MD2 */
+#endif /* WOLF_CRYPT_MD2_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/md4.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/md4.h
new file mode 100644
index 0000000..369e15b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/md4.h
@@ -0,0 +1,62 @@
+/* md4.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_MD4_H
+#define WOLF_CRYPT_MD4_H
+
+#include 
+
+#ifndef NO_MD4
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+/* in bytes */
+enum {
+    MD4_BLOCK_SIZE  = 64,
+    MD4_DIGEST_SIZE = 16,
+    MD4_PAD_SIZE    = 56
+};
+
+
+/* MD4 digest */
+typedef struct Md4 {
+    word32  buffLen;   /* in bytes          */
+    word32  loLen;     /* length in bytes   */
+    word32  hiLen;     /* length in bytes   */
+    word32  digest[MD4_DIGEST_SIZE / sizeof(word32)];
+    word32  buffer[MD4_BLOCK_SIZE  / sizeof(word32)];
+} Md4;
+
+
+WOLFSSL_API void wc_InitMd4(Md4*);
+WOLFSSL_API void wc_Md4Update(Md4*, const byte*, word32);
+WOLFSSL_API void wc_Md4Final(Md4*, byte*);
+
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* NO_MD4 */
+#endif /* WOLF_CRYPT_MD4_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/md5.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/md5.h
new file mode 100644
index 0000000..d0b134b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/md5.h
@@ -0,0 +1,85 @@
+/* md5.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_MD5_H
+#define WOLF_CRYPT_MD5_H
+
+#include 
+
+#ifndef NO_MD5
+
+#ifdef HAVE_FIPS
+    #define wc_InitMd5   InitMd5
+    #define wc_Md5Update Md5Update
+    #define wc_Md5Final  Md5Final
+    #define wc_Md5Hash   Md5Hash
+#endif
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+/* in bytes */
+enum {
+#ifdef STM32F2_HASH
+    MD5_REG_SIZE    =  4,      /* STM32 register size, bytes */
+#endif
+    MD5             =  0,      /* hash type unique */
+    MD5_BLOCK_SIZE  = 64,
+    MD5_DIGEST_SIZE = 16,
+    MD5_PAD_SIZE    = 56
+};
+
+#if defined(WOLFSSL_PIC32MZ_HASH)
+#include "port/pic32/pic32mz-crypt.h"
+#endif
+
+#ifndef WOLFSSL_TI_HASH
+
+/* MD5 digest */
+typedef struct Md5 {
+    word32  buffLen;   /* in bytes          */
+    word32  loLen;     /* length in bytes   */
+    word32  hiLen;     /* length in bytes   */
+    word32  buffer[MD5_BLOCK_SIZE  / sizeof(word32)];
+    #if !defined(WOLFSSL_PIC32MZ_HASH)
+    word32  digest[MD5_DIGEST_SIZE / sizeof(word32)];
+    #else
+    word32  digest[PIC32_HASH_SIZE / sizeof(word32)];
+    pic32mz_desc desc ; /* Crypt Engine descripter */
+    #endif
+} Md5;
+
+#else /* WOLFSSL_TI_HASH */
+    #include "wolfssl/wolfcrypt/port/ti/ti-hash.h"
+#endif
+
+WOLFSSL_API void wc_InitMd5(Md5*);
+WOLFSSL_API void wc_Md5Update(Md5*, const byte*, word32);
+WOLFSSL_API void wc_Md5Final(Md5*, byte*);
+WOLFSSL_API int  wc_Md5Hash(const byte*, word32, byte*);
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* NO_MD5 */
+#endif /* WOLF_CRYPT_MD5_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/memory.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/memory.h
new file mode 100644
index 0000000..3968b35
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/memory.h
@@ -0,0 +1,56 @@
+/* memory.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+/* submitted by eof */
+
+
+#ifndef WOLFSSL_MEMORY_H
+#define WOLFSSL_MEMORY_H
+
+#include 
+#include 
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+typedef void *(*wolfSSL_Malloc_cb)(size_t size);
+typedef void (*wolfSSL_Free_cb)(void *ptr);
+typedef void *(*wolfSSL_Realloc_cb)(void *ptr, size_t size);
+
+
+/* Public set function */
+WOLFSSL_API int wolfSSL_SetAllocators(wolfSSL_Malloc_cb  malloc_function,
+                                    wolfSSL_Free_cb    free_function,
+                                    wolfSSL_Realloc_cb realloc_function);
+
+/* Public in case user app wants to use XMALLOC/XFREE */
+WOLFSSL_API void* wolfSSL_Malloc(size_t size);
+WOLFSSL_API void  wolfSSL_Free(void *ptr);
+WOLFSSL_API void* wolfSSL_Realloc(void *ptr, size_t size);
+
+
+#ifdef __cplusplus
+    }  /* extern "C" */
+#endif
+
+#endif /* WOLFSSL_MEMORY_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/misc.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/misc.h
new file mode 100644
index 0000000..78c7fbd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/misc.h
@@ -0,0 +1,78 @@
+/* misc.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifndef WOLF_CRYPT_MISC_H
+#define WOLF_CRYPT_MISC_H
+
+
+#include 
+
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+
+#ifdef NO_INLINE
+WOLFSSL_LOCAL
+word32 rotlFixed(word32, word32);
+WOLFSSL_LOCAL
+word32 rotrFixed(word32, word32);
+
+WOLFSSL_LOCAL
+word32 ByteReverseWord32(word32);
+WOLFSSL_LOCAL
+void   ByteReverseWords(word32*, const word32*, word32);
+
+WOLFSSL_LOCAL
+void XorWords(wolfssl_word*, const wolfssl_word*, word32);
+WOLFSSL_LOCAL
+void xorbuf(void*, const void*, word32);
+
+WOLFSSL_LOCAL
+void ForceZero(const void*, word32);
+
+WOLFSSL_LOCAL
+int ConstantCompare(const byte*, const byte*, int);
+
+#ifdef WORD64_AVAILABLE
+WOLFSSL_LOCAL
+word64 rotlFixed64(word64, word64);
+WOLFSSL_LOCAL
+word64 rotrFixed64(word64, word64);
+
+WOLFSSL_LOCAL
+word64 ByteReverseWord64(word64);
+WOLFSSL_LOCAL
+void   ByteReverseWords64(word64*, const word64*, word32);
+#endif /* WORD64_AVAILABLE */
+
+#endif /* NO_INLINE */
+
+
+#ifdef __cplusplus
+    }   /* extern "C" */
+#endif
+
+
+#endif /* WOLF_CRYPT_MISC_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/mpi_class.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/mpi_class.h
new file mode 100644
index 0000000..334a7a4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/mpi_class.h
@@ -0,0 +1,1018 @@
+/* mpi_class.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#if !(defined(LTM1) && defined(LTM2) && defined(LTM3))
+#if defined(LTM2)
+#define LTM3
+#endif
+#if defined(LTM1)
+#define LTM2
+#endif
+#define LTM1
+
+#if defined(LTM_ALL)
+#define BN_ERROR_C
+#define BN_FAST_MP_INVMOD_C
+#define BN_FAST_MP_MONTGOMERY_REDUCE_C
+#define BN_FAST_S_MP_MUL_DIGS_C
+#define BN_FAST_S_MP_MUL_HIGH_DIGS_C
+#define BN_FAST_S_MP_SQR_C
+#define BN_MP_2EXPT_C
+#define BN_MP_ABS_C
+#define BN_MP_ADD_C
+#define BN_MP_ADD_D_C
+#define BN_MP_ADDMOD_C
+#define BN_MP_AND_C
+#define BN_MP_CLAMP_C
+#define BN_MP_CLEAR_C
+#define BN_MP_CLEAR_MULTI_C
+#define BN_MP_CMP_C
+#define BN_MP_CMP_D_C
+#define BN_MP_CMP_MAG_C
+#define BN_MP_CNT_LSB_C
+#define BN_MP_COPY_C
+#define BN_MP_COUNT_BITS_C
+#define BN_MP_DIV_C
+#define BN_MP_DIV_2_C
+#define BN_MP_DIV_2D_C
+#define BN_MP_DIV_3_C
+#define BN_MP_DIV_D_C
+#define BN_MP_DR_IS_MODULUS_C
+#define BN_MP_DR_REDUCE_C
+#define BN_MP_DR_SETUP_C
+#define BN_MP_EXCH_C
+#define BN_MP_EXPT_D_C
+#define BN_MP_EXPTMOD_C
+#define BN_MP_EXPTMOD_FAST_C
+#define BN_MP_EXTEUCLID_C
+#define BN_MP_FREAD_C
+#define BN_MP_FWRITE_C
+#define BN_MP_GCD_C
+#define BN_MP_GET_INT_C
+#define BN_MP_GROW_C
+#define BN_MP_INIT_C
+#define BN_MP_INIT_COPY_C
+#define BN_MP_INIT_MULTI_C
+#define BN_MP_INIT_SET_C
+#define BN_MP_INIT_SET_INT_C
+#define BN_MP_INIT_SIZE_C
+#define BN_MP_INVMOD_C
+#define BN_MP_INVMOD_SLOW_C
+#define BN_MP_IS_SQUARE_C
+#define BN_MP_JACOBI_C
+#define BN_MP_KARATSUBA_MUL_C
+#define BN_MP_KARATSUBA_SQR_C
+#define BN_MP_LCM_C
+#define BN_MP_LSHD_C
+#define BN_MP_MOD_C
+#define BN_MP_MOD_2D_C
+#define BN_MP_MOD_D_C
+#define BN_MP_MONTGOMERY_CALC_NORMALIZATION_C
+#define BN_MP_MONTGOMERY_REDUCE_C
+#define BN_MP_MONTGOMERY_SETUP_C
+#define BN_MP_MUL_C
+#define BN_MP_MUL_2_C
+#define BN_MP_MUL_2D_C
+#define BN_MP_MUL_D_C
+#define BN_MP_MULMOD_C
+#define BN_MP_N_ROOT_C
+#define BN_MP_NEG_C
+#define BN_MP_OR_C
+#define BN_MP_PRIME_FERMAT_C
+#define BN_MP_PRIME_IS_DIVISIBLE_C
+#define BN_MP_PRIME_IS_PRIME_C
+#define BN_MP_PRIME_MILLER_RABIN_C
+#define BN_MP_PRIME_NEXT_PRIME_C
+#define BN_MP_PRIME_RABIN_MILLER_TRIALS_C
+#define BN_MP_PRIME_RANDOM_EX_C
+#define BN_MP_RADIX_SIZE_C
+#define BN_MP_RADIX_SMAP_C
+#define BN_MP_RAND_C
+#define BN_MP_READ_RADIX_C
+#define BN_MP_READ_SIGNED_BIN_C
+#define BN_MP_READ_UNSIGNED_BIN_C
+#define BN_MP_REDUCE_C
+#define BN_MP_REDUCE_2K_C
+#define BN_MP_REDUCE_2K_L_C
+#define BN_MP_REDUCE_2K_SETUP_C
+#define BN_MP_REDUCE_2K_SETUP_L_C
+#define BN_MP_REDUCE_IS_2K_C
+#define BN_MP_REDUCE_IS_2K_L_C
+#define BN_MP_REDUCE_SETUP_C
+#define BN_MP_RSHD_C
+#define BN_MP_SET_C
+#define BN_MP_SET_INT_C
+#define BN_MP_SHRINK_C
+#define BN_MP_SIGNED_BIN_SIZE_C
+#define BN_MP_SQR_C
+#define BN_MP_SQRMOD_C
+#define BN_MP_SQRT_C
+#define BN_MP_SUB_C
+#define BN_MP_SUB_D_C
+#define BN_MP_SUBMOD_C
+#define BN_MP_TO_SIGNED_BIN_C
+#define BN_MP_TO_SIGNED_BIN_N_C
+#define BN_MP_TO_UNSIGNED_BIN_C
+#define BN_MP_TO_UNSIGNED_BIN_N_C
+#define BN_MP_TOOM_MUL_C
+#define BN_MP_TOOM_SQR_C
+#define BN_MP_TORADIX_C
+#define BN_MP_TORADIX_N_C
+#define BN_MP_UNSIGNED_BIN_SIZE_C
+#define BN_MP_XOR_C
+#define BN_MP_ZERO_C
+#define BN_PRIME_TAB_C
+#define BN_REVERSE_C
+#define BN_S_MP_ADD_C
+#define BN_S_MP_EXPTMOD_C
+#define BN_S_MP_MUL_DIGS_C
+#define BN_S_MP_MUL_HIGH_DIGS_C
+#define BN_S_MP_SQR_C
+#define BN_S_MP_SUB_C
+#define BNCORE_C
+#endif
+
+#if defined(BN_ERROR_C)
+   #define BN_MP_ERROR_TO_STRING_C
+#endif
+
+#if defined(BN_FAST_MP_INVMOD_C)
+   #define BN_MP_ISEVEN_C
+   #define BN_MP_INIT_MULTI_C
+   #define BN_MP_COPY_C
+   #define BN_MP_MOD_C
+   #define BN_MP_SET_C
+   #define BN_MP_DIV_2_C
+   #define BN_MP_ISODD_C
+   #define BN_MP_SUB_C
+   #define BN_MP_CMP_C
+   #define BN_MP_ISZERO_C
+   #define BN_MP_CMP_D_C
+   #define BN_MP_ADD_C
+   #define BN_MP_EXCH_C
+   #define BN_MP_CLEAR_MULTI_C
+#endif
+
+#if defined(BN_FAST_MP_MONTGOMERY_REDUCE_C)
+   #define BN_MP_GROW_C
+   #define BN_MP_RSHD_C
+   #define BN_MP_CLAMP_C
+   #define BN_MP_CMP_MAG_C
+   #define BN_S_MP_SUB_C
+#endif
+
+#if defined(BN_FAST_S_MP_MUL_DIGS_C)
+   #define BN_MP_GROW_C
+   #define BN_MP_CLAMP_C
+#endif
+
+#if defined(BN_FAST_S_MP_MUL_HIGH_DIGS_C)
+   #define BN_MP_GROW_C
+   #define BN_MP_CLAMP_C
+#endif
+
+#if defined(BN_FAST_S_MP_SQR_C)
+   #define BN_MP_GROW_C
+   #define BN_MP_CLAMP_C
+#endif
+
+#if defined(BN_MP_2EXPT_C)
+   #define BN_MP_ZERO_C
+   #define BN_MP_GROW_C
+#endif
+
+#if defined(BN_MP_ABS_C)
+   #define BN_MP_COPY_C
+#endif
+
+#if defined(BN_MP_ADD_C)
+   #define BN_S_MP_ADD_C
+   #define BN_MP_CMP_MAG_C
+   #define BN_S_MP_SUB_C
+#endif
+
+#if defined(BN_MP_ADD_D_C)
+   #define BN_MP_GROW_C
+   #define BN_MP_SUB_D_C
+   #define BN_MP_CLAMP_C
+#endif
+
+#if defined(BN_MP_ADDMOD_C)
+   #define BN_MP_INIT_C
+   #define BN_MP_ADD_C
+   #define BN_MP_CLEAR_C
+   #define BN_MP_MOD_C
+#endif
+
+#if defined(BN_MP_AND_C)
+   #define BN_MP_INIT_COPY_C
+   #define BN_MP_CLAMP_C
+   #define BN_MP_EXCH_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_CLAMP_C)
+#endif
+
+#if defined(BN_MP_CLEAR_C)
+#endif
+
+#if defined(BN_MP_CLEAR_MULTI_C)
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_CMP_C)
+   #define BN_MP_CMP_MAG_C
+#endif
+
+#if defined(BN_MP_CMP_D_C)
+#endif
+
+#if defined(BN_MP_CMP_MAG_C)
+#endif
+
+#if defined(BN_MP_CNT_LSB_C)
+   #define BN_MP_ISZERO_C
+#endif
+
+#if defined(BN_MP_COPY_C)
+   #define BN_MP_GROW_C
+#endif
+
+#if defined(BN_MP_COUNT_BITS_C)
+#endif
+
+#if defined(BN_MP_DIV_C)
+   #define BN_MP_ISZERO_C
+   #define BN_MP_CMP_MAG_C
+   #define BN_MP_COPY_C
+   #define BN_MP_ZERO_C
+   #define BN_MP_INIT_MULTI_C
+   #define BN_MP_SET_C
+   #define BN_MP_COUNT_BITS_C
+   #define BN_MP_ABS_C
+   #define BN_MP_MUL_2D_C
+   #define BN_MP_CMP_C
+   #define BN_MP_SUB_C
+   #define BN_MP_ADD_C
+   #define BN_MP_DIV_2D_C
+   #define BN_MP_EXCH_C
+   #define BN_MP_CLEAR_MULTI_C
+   #define BN_MP_INIT_SIZE_C
+   #define BN_MP_INIT_C
+   #define BN_MP_INIT_COPY_C
+   #define BN_MP_LSHD_C
+   #define BN_MP_RSHD_C
+   #define BN_MP_MUL_D_C
+   #define BN_MP_CLAMP_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_DIV_2_C)
+   #define BN_MP_GROW_C
+   #define BN_MP_CLAMP_C
+#endif
+
+#if defined(BN_MP_DIV_2D_C)
+   #define BN_MP_COPY_C
+   #define BN_MP_ZERO_C
+   #define BN_MP_INIT_C
+   #define BN_MP_MOD_2D_C
+   #define BN_MP_CLEAR_C
+   #define BN_MP_RSHD_C
+   #define BN_MP_CLAMP_C
+   #define BN_MP_EXCH_C
+#endif
+
+#if defined(BN_MP_DIV_3_C)
+   #define BN_MP_INIT_SIZE_C
+   #define BN_MP_CLAMP_C
+   #define BN_MP_EXCH_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_DIV_D_C)
+   #define BN_MP_ISZERO_C
+   #define BN_MP_COPY_C
+   #define BN_MP_DIV_2D_C
+   #define BN_MP_DIV_3_C
+   #define BN_MP_INIT_SIZE_C
+   #define BN_MP_CLAMP_C
+   #define BN_MP_EXCH_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_DR_IS_MODULUS_C)
+#endif
+
+#if defined(BN_MP_DR_REDUCE_C)
+   #define BN_MP_GROW_C
+   #define BN_MP_CLAMP_C
+   #define BN_MP_CMP_MAG_C
+   #define BN_S_MP_SUB_C
+#endif
+
+#if defined(BN_MP_DR_SETUP_C)
+#endif
+
+#if defined(BN_MP_EXCH_C)
+#endif
+
+#if defined(BN_MP_EXPT_D_C)
+   #define BN_MP_INIT_COPY_C
+   #define BN_MP_SET_C
+   #define BN_MP_SQR_C
+   #define BN_MP_CLEAR_C
+   #define BN_MP_MUL_C
+#endif
+
+#if defined(BN_MP_EXPTMOD_C)
+   #define BN_MP_INIT_C
+   #define BN_MP_INVMOD_C
+   #define BN_MP_CLEAR_C
+   #define BN_MP_ABS_C
+   #define BN_MP_CLEAR_MULTI_C
+   #define BN_MP_REDUCE_IS_2K_L_C
+   #define BN_S_MP_EXPTMOD_C
+   #define BN_MP_DR_IS_MODULUS_C
+   #define BN_MP_REDUCE_IS_2K_C
+   #define BN_MP_ISODD_C
+   #define BN_MP_EXPTMOD_FAST_C
+#endif
+
+#if defined(BN_MP_EXPTMOD_FAST_C)
+   #define BN_MP_COUNT_BITS_C
+   #define BN_MP_INIT_C
+   #define BN_MP_CLEAR_C
+   #define BN_MP_MONTGOMERY_SETUP_C
+   #define BN_FAST_MP_MONTGOMERY_REDUCE_C
+   #define BN_MP_MONTGOMERY_REDUCE_C
+   #define BN_MP_DR_SETUP_C
+   #define BN_MP_DR_REDUCE_C
+   #define BN_MP_REDUCE_2K_SETUP_C
+   #define BN_MP_REDUCE_2K_C
+   #define BN_MP_MONTGOMERY_CALC_NORMALIZATION_C
+   #define BN_MP_MULMOD_C
+   #define BN_MP_SET_C
+   #define BN_MP_MOD_C
+   #define BN_MP_COPY_C
+   #define BN_MP_SQR_C
+   #define BN_MP_MUL_C
+   #define BN_MP_EXCH_C
+#endif
+
+#if defined(BN_MP_EXTEUCLID_C)
+   #define BN_MP_INIT_MULTI_C
+   #define BN_MP_SET_C
+   #define BN_MP_COPY_C
+   #define BN_MP_ISZERO_C
+   #define BN_MP_DIV_C
+   #define BN_MP_MUL_C
+   #define BN_MP_SUB_C
+   #define BN_MP_NEG_C
+   #define BN_MP_EXCH_C
+   #define BN_MP_CLEAR_MULTI_C
+#endif
+
+#if defined(BN_MP_FREAD_C)
+   #define BN_MP_ZERO_C
+   #define BN_MP_S_RMAP_C
+   #define BN_MP_MUL_D_C
+   #define BN_MP_ADD_D_C
+   #define BN_MP_CMP_D_C
+#endif
+
+#if defined(BN_MP_FWRITE_C)
+   #define BN_MP_RADIX_SIZE_C
+   #define BN_MP_TORADIX_C
+#endif
+
+#if defined(BN_MP_GCD_C)
+   #define BN_MP_ISZERO_C
+   #define BN_MP_ABS_C
+   #define BN_MP_ZERO_C
+   #define BN_MP_INIT_COPY_C
+   #define BN_MP_CNT_LSB_C
+   #define BN_MP_DIV_2D_C
+   #define BN_MP_CMP_MAG_C
+   #define BN_MP_EXCH_C
+   #define BN_S_MP_SUB_C
+   #define BN_MP_MUL_2D_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_GET_INT_C)
+#endif
+
+#if defined(BN_MP_GROW_C)
+#endif
+
+#if defined(BN_MP_INIT_C)
+#endif
+
+#if defined(BN_MP_INIT_COPY_C)
+   #define BN_MP_COPY_C
+#endif
+
+#if defined(BN_MP_INIT_MULTI_C)
+   #define BN_MP_ERR_C
+   #define BN_MP_INIT_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_INIT_SET_C)
+   #define BN_MP_INIT_C
+   #define BN_MP_SET_C
+#endif
+
+#if defined(BN_MP_INIT_SET_INT_C)
+   #define BN_MP_INIT_C
+   #define BN_MP_SET_INT_C
+#endif
+
+#if defined(BN_MP_INIT_SIZE_C)
+   #define BN_MP_INIT_C
+#endif
+
+#if defined(BN_MP_INVMOD_C)
+   #define BN_MP_ISZERO_C
+   #define BN_MP_ISODD_C
+   #define BN_FAST_MP_INVMOD_C
+   #define BN_MP_INVMOD_SLOW_C
+#endif
+
+#if defined(BN_MP_INVMOD_SLOW_C)
+   #define BN_MP_ISZERO_C
+   #define BN_MP_INIT_MULTI_C
+   #define BN_MP_MOD_C
+   #define BN_MP_COPY_C
+   #define BN_MP_ISEVEN_C
+   #define BN_MP_SET_C
+   #define BN_MP_DIV_2_C
+   #define BN_MP_ISODD_C
+   #define BN_MP_ADD_C
+   #define BN_MP_SUB_C
+   #define BN_MP_CMP_C
+   #define BN_MP_CMP_D_C
+   #define BN_MP_CMP_MAG_C
+   #define BN_MP_EXCH_C
+   #define BN_MP_CLEAR_MULTI_C
+#endif
+
+#if defined(BN_MP_IS_SQUARE_C)
+   #define BN_MP_MOD_D_C
+   #define BN_MP_INIT_SET_INT_C
+   #define BN_MP_MOD_C
+   #define BN_MP_GET_INT_C
+   #define BN_MP_SQRT_C
+   #define BN_MP_SQR_C
+   #define BN_MP_CMP_MAG_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_JACOBI_C)
+   #define BN_MP_CMP_D_C
+   #define BN_MP_ISZERO_C
+   #define BN_MP_INIT_COPY_C
+   #define BN_MP_CNT_LSB_C
+   #define BN_MP_DIV_2D_C
+   #define BN_MP_MOD_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_KARATSUBA_MUL_C)
+   #define BN_MP_MUL_C
+   #define BN_MP_INIT_SIZE_C
+   #define BN_MP_CLAMP_C
+   #define BN_MP_SUB_C
+   #define BN_MP_ADD_C
+   #define BN_MP_LSHD_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_KARATSUBA_SQR_C)
+   #define BN_MP_INIT_SIZE_C
+   #define BN_MP_CLAMP_C
+   #define BN_MP_SQR_C
+   #define BN_MP_SUB_C
+   #define BN_S_MP_ADD_C
+   #define BN_MP_LSHD_C
+   #define BN_MP_ADD_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_LCM_C)
+   #define BN_MP_INIT_MULTI_C
+   #define BN_MP_GCD_C
+   #define BN_MP_CMP_MAG_C
+   #define BN_MP_DIV_C
+   #define BN_MP_MUL_C
+   #define BN_MP_CLEAR_MULTI_C
+#endif
+
+#if defined(BN_MP_LSHD_C)
+   #define BN_MP_GROW_C
+   #define BN_MP_RSHD_C
+#endif
+
+#if defined(BN_MP_MOD_C)
+   #define BN_MP_INIT_C
+   #define BN_MP_DIV_C
+   #define BN_MP_CLEAR_C
+   #define BN_MP_ADD_C
+   #define BN_MP_EXCH_C
+#endif
+
+#if defined(BN_MP_MOD_2D_C)
+   #define BN_MP_ZERO_C
+   #define BN_MP_COPY_C
+   #define BN_MP_CLAMP_C
+#endif
+
+#if defined(BN_MP_MOD_D_C)
+   #define BN_MP_DIV_D_C
+#endif
+
+#if defined(BN_MP_MONTGOMERY_CALC_NORMALIZATION_C)
+   #define BN_MP_COUNT_BITS_C
+   #define BN_MP_2EXPT_C
+   #define BN_MP_SET_C
+   #define BN_MP_MUL_2_C
+   #define BN_MP_CMP_MAG_C
+   #define BN_S_MP_SUB_C
+#endif
+
+#if defined(BN_MP_MONTGOMERY_REDUCE_C)
+   #define BN_FAST_MP_MONTGOMERY_REDUCE_C
+   #define BN_MP_GROW_C
+   #define BN_MP_CLAMP_C
+   #define BN_MP_RSHD_C
+   #define BN_MP_CMP_MAG_C
+   #define BN_S_MP_SUB_C
+#endif
+
+#if defined(BN_MP_MONTGOMERY_SETUP_C)
+#endif
+
+#if defined(BN_MP_MUL_C)
+   #define BN_MP_TOOM_MUL_C
+   #define BN_MP_KARATSUBA_MUL_C
+   #define BN_FAST_S_MP_MUL_DIGS_C
+   #define BN_S_MP_MUL_C
+   #define BN_S_MP_MUL_DIGS_C
+#endif
+
+#if defined(BN_MP_MUL_2_C)
+   #define BN_MP_GROW_C
+#endif
+
+#if defined(BN_MP_MUL_2D_C)
+   #define BN_MP_COPY_C
+   #define BN_MP_GROW_C
+   #define BN_MP_LSHD_C
+   #define BN_MP_CLAMP_C
+#endif
+
+#if defined(BN_MP_MUL_D_C)
+   #define BN_MP_GROW_C
+   #define BN_MP_CLAMP_C
+#endif
+
+#if defined(BN_MP_MULMOD_C)
+   #define BN_MP_INIT_C
+   #define BN_MP_MUL_C
+   #define BN_MP_CLEAR_C
+   #define BN_MP_MOD_C
+#endif
+
+#if defined(BN_MP_N_ROOT_C)
+   #define BN_MP_INIT_C
+   #define BN_MP_SET_C
+   #define BN_MP_COPY_C
+   #define BN_MP_EXPT_D_C
+   #define BN_MP_MUL_C
+   #define BN_MP_SUB_C
+   #define BN_MP_MUL_D_C
+   #define BN_MP_DIV_C
+   #define BN_MP_CMP_C
+   #define BN_MP_SUB_D_C
+   #define BN_MP_EXCH_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_NEG_C)
+   #define BN_MP_COPY_C
+   #define BN_MP_ISZERO_C
+#endif
+
+#if defined(BN_MP_OR_C)
+   #define BN_MP_INIT_COPY_C
+   #define BN_MP_CLAMP_C
+   #define BN_MP_EXCH_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_PRIME_FERMAT_C)
+   #define BN_MP_CMP_D_C
+   #define BN_MP_INIT_C
+   #define BN_MP_EXPTMOD_C
+   #define BN_MP_CMP_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_PRIME_IS_DIVISIBLE_C)
+   #define BN_MP_MOD_D_C
+#endif
+
+#if defined(BN_MP_PRIME_IS_PRIME_C)
+   #define BN_MP_CMP_D_C
+   #define BN_MP_PRIME_IS_DIVISIBLE_C
+   #define BN_MP_INIT_C
+   #define BN_MP_SET_C
+   #define BN_MP_PRIME_MILLER_RABIN_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_PRIME_MILLER_RABIN_C)
+   #define BN_MP_CMP_D_C
+   #define BN_MP_INIT_COPY_C
+   #define BN_MP_SUB_D_C
+   #define BN_MP_CNT_LSB_C
+   #define BN_MP_DIV_2D_C
+   #define BN_MP_EXPTMOD_C
+   #define BN_MP_CMP_C
+   #define BN_MP_SQRMOD_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_PRIME_NEXT_PRIME_C)
+   #define BN_MP_CMP_D_C
+   #define BN_MP_SET_C
+   #define BN_MP_SUB_D_C
+   #define BN_MP_ISEVEN_C
+   #define BN_MP_MOD_D_C
+   #define BN_MP_INIT_C
+   #define BN_MP_ADD_D_C
+   #define BN_MP_PRIME_MILLER_RABIN_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_PRIME_RABIN_MILLER_TRIALS_C)
+#endif
+
+#if defined(BN_MP_PRIME_RANDOM_EX_C)
+   #define BN_MP_READ_UNSIGNED_BIN_C
+   #define BN_MP_PRIME_IS_PRIME_C
+   #define BN_MP_SUB_D_C
+   #define BN_MP_DIV_2_C
+   #define BN_MP_MUL_2_C
+   #define BN_MP_ADD_D_C
+#endif
+
+#if defined(BN_MP_RADIX_SIZE_C)
+   #define BN_MP_COUNT_BITS_C
+   #define BN_MP_INIT_COPY_C
+   #define BN_MP_ISZERO_C
+   #define BN_MP_DIV_D_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_RADIX_SMAP_C)
+   #define BN_MP_S_RMAP_C
+#endif
+
+#if defined(BN_MP_RAND_C)
+   #define BN_MP_ZERO_C
+   #define BN_MP_ADD_D_C
+   #define BN_MP_LSHD_C
+#endif
+
+#if defined(BN_MP_READ_RADIX_C)
+   #define BN_MP_ZERO_C
+   #define BN_MP_S_RMAP_C
+   #define BN_MP_RADIX_SMAP_C
+   #define BN_MP_MUL_D_C
+   #define BN_MP_ADD_D_C
+   #define BN_MP_ISZERO_C
+#endif
+
+#if defined(BN_MP_READ_SIGNED_BIN_C)
+   #define BN_MP_READ_UNSIGNED_BIN_C
+#endif
+
+#if defined(BN_MP_READ_UNSIGNED_BIN_C)
+   #define BN_MP_GROW_C
+   #define BN_MP_ZERO_C
+   #define BN_MP_MUL_2D_C
+   #define BN_MP_CLAMP_C
+#endif
+
+#if defined(BN_MP_REDUCE_C)
+   #define BN_MP_REDUCE_SETUP_C
+   #define BN_MP_INIT_COPY_C
+   #define BN_MP_RSHD_C
+   #define BN_MP_MUL_C
+   #define BN_S_MP_MUL_HIGH_DIGS_C
+   #define BN_FAST_S_MP_MUL_HIGH_DIGS_C
+   #define BN_MP_MOD_2D_C
+   #define BN_S_MP_MUL_DIGS_C
+   #define BN_MP_SUB_C
+   #define BN_MP_CMP_D_C
+   #define BN_MP_SET_C
+   #define BN_MP_LSHD_C
+   #define BN_MP_ADD_C
+   #define BN_MP_CMP_C
+   #define BN_S_MP_SUB_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_REDUCE_2K_C)
+   #define BN_MP_INIT_C
+   #define BN_MP_COUNT_BITS_C
+   #define BN_MP_DIV_2D_C
+   #define BN_MP_MUL_D_C
+   #define BN_S_MP_ADD_C
+   #define BN_MP_CMP_MAG_C
+   #define BN_S_MP_SUB_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_REDUCE_2K_L_C)
+   #define BN_MP_INIT_C
+   #define BN_MP_COUNT_BITS_C
+   #define BN_MP_DIV_2D_C
+   #define BN_MP_MUL_C
+   #define BN_S_MP_ADD_C
+   #define BN_MP_CMP_MAG_C
+   #define BN_S_MP_SUB_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_REDUCE_2K_SETUP_C)
+   #define BN_MP_INIT_C
+   #define BN_MP_COUNT_BITS_C
+   #define BN_MP_2EXPT_C
+   #define BN_MP_CLEAR_C
+   #define BN_S_MP_SUB_C
+#endif
+
+#if defined(BN_MP_REDUCE_2K_SETUP_L_C)
+   #define BN_MP_INIT_C
+   #define BN_MP_2EXPT_C
+   #define BN_MP_COUNT_BITS_C
+   #define BN_S_MP_SUB_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_REDUCE_IS_2K_C)
+   #define BN_MP_REDUCE_2K_C
+   #define BN_MP_COUNT_BITS_C
+#endif
+
+#if defined(BN_MP_REDUCE_IS_2K_L_C)
+#endif
+
+#if defined(BN_MP_REDUCE_SETUP_C)
+   #define BN_MP_2EXPT_C
+   #define BN_MP_DIV_C
+#endif
+
+#if defined(BN_MP_RSHD_C)
+   #define BN_MP_ZERO_C
+#endif
+
+#if defined(BN_MP_SET_C)
+   #define BN_MP_ZERO_C
+#endif
+
+#if defined(BN_MP_SET_INT_C)
+   #define BN_MP_ZERO_C
+   #define BN_MP_MUL_2D_C
+   #define BN_MP_CLAMP_C
+#endif
+
+#if defined(BN_MP_SHRINK_C)
+#endif
+
+#if defined(BN_MP_SIGNED_BIN_SIZE_C)
+   #define BN_MP_UNSIGNED_BIN_SIZE_C
+#endif
+
+#if defined(BN_MP_SQR_C)
+   #define BN_MP_TOOM_SQR_C
+   #define BN_MP_KARATSUBA_SQR_C
+   #define BN_FAST_S_MP_SQR_C
+   #define BN_S_MP_SQR_C
+#endif
+
+#if defined(BN_MP_SQRMOD_C)
+   #define BN_MP_INIT_C
+   #define BN_MP_SQR_C
+   #define BN_MP_CLEAR_C
+   #define BN_MP_MOD_C
+#endif
+
+#if defined(BN_MP_SQRT_C)
+   #define BN_MP_N_ROOT_C
+   #define BN_MP_ISZERO_C
+   #define BN_MP_ZERO_C
+   #define BN_MP_INIT_COPY_C
+   #define BN_MP_RSHD_C
+   #define BN_MP_DIV_C
+   #define BN_MP_ADD_C
+   #define BN_MP_DIV_2_C
+   #define BN_MP_CMP_MAG_C
+   #define BN_MP_EXCH_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_SUB_C)
+   #define BN_S_MP_ADD_C
+   #define BN_MP_CMP_MAG_C
+   #define BN_S_MP_SUB_C
+#endif
+
+#if defined(BN_MP_SUB_D_C)
+   #define BN_MP_GROW_C
+   #define BN_MP_ADD_D_C
+   #define BN_MP_CLAMP_C
+#endif
+
+#if defined(BN_MP_SUBMOD_C)
+   #define BN_MP_INIT_C
+   #define BN_MP_SUB_C
+   #define BN_MP_CLEAR_C
+   #define BN_MP_MOD_C
+#endif
+
+#if defined(BN_MP_TO_SIGNED_BIN_C)
+   #define BN_MP_TO_UNSIGNED_BIN_C
+#endif
+
+#if defined(BN_MP_TO_SIGNED_BIN_N_C)
+   #define BN_MP_SIGNED_BIN_SIZE_C
+   #define BN_MP_TO_SIGNED_BIN_C
+#endif
+
+#if defined(BN_MP_TO_UNSIGNED_BIN_C)
+   #define BN_MP_INIT_COPY_C
+   #define BN_MP_ISZERO_C
+   #define BN_MP_DIV_2D_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_TO_UNSIGNED_BIN_N_C)
+   #define BN_MP_UNSIGNED_BIN_SIZE_C
+   #define BN_MP_TO_UNSIGNED_BIN_C
+#endif
+
+#if defined(BN_MP_TOOM_MUL_C)
+   #define BN_MP_INIT_MULTI_C
+   #define BN_MP_MOD_2D_C
+   #define BN_MP_COPY_C
+   #define BN_MP_RSHD_C
+   #define BN_MP_MUL_C
+   #define BN_MP_MUL_2_C
+   #define BN_MP_ADD_C
+   #define BN_MP_SUB_C
+   #define BN_MP_DIV_2_C
+   #define BN_MP_MUL_2D_C
+   #define BN_MP_MUL_D_C
+   #define BN_MP_DIV_3_C
+   #define BN_MP_LSHD_C
+   #define BN_MP_CLEAR_MULTI_C
+#endif
+
+#if defined(BN_MP_TOOM_SQR_C)
+   #define BN_MP_INIT_MULTI_C
+   #define BN_MP_MOD_2D_C
+   #define BN_MP_COPY_C
+   #define BN_MP_RSHD_C
+   #define BN_MP_SQR_C
+   #define BN_MP_MUL_2_C
+   #define BN_MP_ADD_C
+   #define BN_MP_SUB_C
+   #define BN_MP_DIV_2_C
+   #define BN_MP_MUL_2D_C
+   #define BN_MP_MUL_D_C
+   #define BN_MP_DIV_3_C
+   #define BN_MP_LSHD_C
+   #define BN_MP_CLEAR_MULTI_C
+#endif
+
+#if defined(BN_MP_TORADIX_C)
+   #define BN_MP_ISZERO_C
+   #define BN_MP_INIT_COPY_C
+   #define BN_MP_DIV_D_C
+   #define BN_MP_CLEAR_C
+   #define BN_MP_S_RMAP_C
+#endif
+
+#if defined(BN_MP_TORADIX_N_C)
+   #define BN_MP_ISZERO_C
+   #define BN_MP_INIT_COPY_C
+   #define BN_MP_DIV_D_C
+   #define BN_MP_CLEAR_C
+   #define BN_MP_S_RMAP_C
+#endif
+
+#if defined(BN_MP_UNSIGNED_BIN_SIZE_C)
+   #define BN_MP_COUNT_BITS_C
+#endif
+
+#if defined(BN_MP_XOR_C)
+   #define BN_MP_INIT_COPY_C
+   #define BN_MP_CLAMP_C
+   #define BN_MP_EXCH_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_MP_ZERO_C)
+#endif
+
+#if defined(BN_PRIME_TAB_C)
+#endif
+
+#if defined(BN_REVERSE_C)
+#endif
+
+#if defined(BN_S_MP_ADD_C)
+   #define BN_MP_GROW_C
+   #define BN_MP_CLAMP_C
+#endif
+
+#if defined(BN_S_MP_EXPTMOD_C)
+   #define BN_MP_COUNT_BITS_C
+   #define BN_MP_INIT_C
+   #define BN_MP_CLEAR_C
+   #define BN_MP_REDUCE_SETUP_C
+   #define BN_MP_REDUCE_C
+   #define BN_MP_REDUCE_2K_SETUP_L_C
+   #define BN_MP_REDUCE_2K_L_C
+   #define BN_MP_MOD_C
+   #define BN_MP_COPY_C
+   #define BN_MP_SQR_C
+   #define BN_MP_MUL_C
+   #define BN_MP_SET_C
+   #define BN_MP_EXCH_C
+#endif
+
+#if defined(BN_S_MP_MUL_DIGS_C)
+   #define BN_FAST_S_MP_MUL_DIGS_C
+   #define BN_MP_INIT_SIZE_C
+   #define BN_MP_CLAMP_C
+   #define BN_MP_EXCH_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_S_MP_MUL_HIGH_DIGS_C)
+   #define BN_FAST_S_MP_MUL_HIGH_DIGS_C
+   #define BN_MP_INIT_SIZE_C
+   #define BN_MP_CLAMP_C
+   #define BN_MP_EXCH_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_S_MP_SQR_C)
+   #define BN_MP_INIT_SIZE_C
+   #define BN_MP_CLAMP_C
+   #define BN_MP_EXCH_C
+   #define BN_MP_CLEAR_C
+#endif
+
+#if defined(BN_S_MP_SUB_C)
+   #define BN_MP_GROW_C
+   #define BN_MP_CLAMP_C
+#endif
+
+#if defined(BNCORE_C)
+#endif
+
+#ifdef LTM3
+#define LTM_LAST
+#endif
+#include "mpi_superclass.h"
+#include "mpi_class.h"
+#else
+#define LTM_LAST
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/mpi_superclass.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/mpi_superclass.h
new file mode 100644
index 0000000..f4c95ab
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/mpi_superclass.h
@@ -0,0 +1,95 @@
+/* mpi_superclass.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+/* super class file for PK algos */
+
+/* default ... include all MPI */
+#define LTM_ALL
+
+/* RSA only (does not support DH/DSA/ECC) */
+/* #define SC_RSA_1 */
+
+/* For reference.... On an Athlon64 optimizing for speed...
+
+   LTM's mpi.o with all functions [striped] is 142KiB in size.
+
+*/
+
+/* Works for RSA only, mpi.o is 68KiB */
+#ifdef SC_RSA_1
+   #define BN_MP_SHRINK_C
+   #define BN_MP_LCM_C
+   #define BN_MP_PRIME_RANDOM_EX_C
+   #define BN_MP_INVMOD_C
+   #define BN_MP_GCD_C
+   #define BN_MP_MOD_C
+   #define BN_MP_MULMOD_C
+   #define BN_MP_ADDMOD_C
+   #define BN_MP_EXPTMOD_C
+   #define BN_MP_SET_INT_C
+   #define BN_MP_INIT_MULTI_C
+   #define BN_MP_CLEAR_MULTI_C
+   #define BN_MP_UNSIGNED_BIN_SIZE_C
+   #define BN_MP_TO_UNSIGNED_BIN_C
+   #define BN_MP_MOD_D_C
+   #define BN_MP_PRIME_RABIN_MILLER_TRIALS_C
+   #define BN_REVERSE_C
+   #define BN_PRIME_TAB_C
+
+   /* other modifiers */
+   #define BN_MP_DIV_SMALL                    /* Slower division, not critical */
+
+   /* here we are on the last pass so we turn things off.  The functions classes are still there
+    * but we remove them specifically from the build.  This also invokes tweaks in functions
+    * like removing support for even moduli, etc...
+    */
+#ifdef LTM_LAST
+   #undef  BN_MP_TOOM_MUL_C
+   #undef  BN_MP_TOOM_SQR_C
+   #undef  BN_MP_KARATSUBA_MUL_C
+   #undef  BN_MP_KARATSUBA_SQR_C
+   #undef  BN_MP_REDUCE_C
+   #undef  BN_MP_REDUCE_SETUP_C
+   #undef  BN_MP_DR_IS_MODULUS_C
+   #undef  BN_MP_DR_SETUP_C
+   #undef  BN_MP_DR_REDUCE_C
+   #undef  BN_MP_REDUCE_IS_2K_C
+   #undef  BN_MP_REDUCE_2K_SETUP_C
+   #undef  BN_MP_REDUCE_2K_C
+   #undef  BN_S_MP_EXPTMOD_C
+   #undef  BN_MP_DIV_3_C
+   #undef  BN_S_MP_MUL_HIGH_DIGS_C
+   #undef  BN_FAST_S_MP_MUL_HIGH_DIGS_C
+   #undef  BN_FAST_MP_INVMOD_C
+
+   /* To safely undefine these you have to make sure your RSA key won't exceed the Comba threshold
+    * which is roughly 255 digits [7140 bits for 32-bit machines, 15300 bits for 64-bit machines] 
+    * which means roughly speaking you can handle upto 2536-bit RSA keys with these defined without
+    * trouble.  
+    */
+   #undef  BN_S_MP_MUL_DIGS_C
+   #undef  BN_S_MP_SQR_C
+   #undef  BN_MP_MONTGOMERY_REDUCE_C
+#endif
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/pkcs7.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/pkcs7.h
new file mode 100644
index 0000000..e39a12b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/pkcs7.h
@@ -0,0 +1,126 @@
+/* pkcs7.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_PKCS7_H
+#define WOLF_CRYPT_PKCS7_H
+
+#include 
+
+#ifdef HAVE_PKCS7
+
+#ifndef NO_ASN
+    #include 
+#endif
+#include 
+#include 
+#ifndef NO_DES3
+    #include 
+#endif
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+/* PKCS#7 content types, ref RFC 2315 (Section 14) */
+enum PKCS7_TYPES {
+    PKCS7_MSG                 = 650,   /* 1.2.840.113549.1.7   */
+    DATA                      = 651,   /* 1.2.840.113549.1.7.1 */
+    SIGNED_DATA               = 652,   /* 1.2.840.113549.1.7.2 */
+    ENVELOPED_DATA            = 653,   /* 1.2.840.113549.1.7.3 */
+    SIGNED_AND_ENVELOPED_DATA = 654,   /* 1.2.840.113549.1.7.4 */
+    DIGESTED_DATA             = 655,   /* 1.2.840.113549.1.7.5 */
+    ENCRYPTED_DATA            = 656    /* 1.2.840.113549.1.7.6 */
+};
+
+enum Pkcs7_Misc {
+    PKCS7_NONCE_SZ       = 16,
+    MAX_ENCRYPTED_KEY_SZ = 512,           /* max enc. key size, RSA <= 4096 */
+    MAX_CONTENT_KEY_LEN  = DES3_KEYLEN,   /* highest current cipher is 3DES */
+    MAX_RECIP_SZ         = MAX_VERSION_SZ +
+                           MAX_SEQ_SZ + ASN_NAME_MAX + MAX_SN_SZ +
+                           MAX_SEQ_SZ + MAX_ALGO_SZ + 1 + MAX_ENCRYPTED_KEY_SZ
+};
+
+
+typedef struct PKCS7Attrib {
+    byte* oid;
+    word32 oidSz;
+    byte* value;
+    word32 valueSz;
+} PKCS7Attrib;
+
+
+typedef struct PKCS7 {
+    byte* content;                /* inner content, not owner             */
+    word32 contentSz;             /* content size                         */
+    int contentOID;               /* PKCS#7 content type OID sum          */
+
+    RNG* rng;
+
+    int hashOID;
+    int encryptOID;               /* key encryption algorithm OID         */
+
+    byte*  singleCert;            /* recipient cert, DER, not owner       */
+    word32 singleCertSz;          /* size of recipient cert buffer, bytes */
+    byte issuerHash[KEYID_SIZE];  /* hash of all alt Names                */
+    byte*  issuer;                /* issuer name of singleCert            */
+    word32 issuerSz;              /* length of issuer name                */
+    byte issuerSn[MAX_SN_SZ];     /* singleCert's serial number           */
+    word32 issuerSnSz;            /* length of serial number              */
+    byte publicKey[512];
+    word32 publicKeySz;
+    byte*  privateKey;            /* private key, DER, not owner          */
+    word32 privateKeySz;          /* size of private key buffer, bytes    */
+
+    PKCS7Attrib* signedAttribs;
+    word32 signedAttribsSz;
+} PKCS7;
+
+
+WOLFSSL_LOCAL int wc_SetContentType(int pkcs7TypeOID, byte* output);
+WOLFSSL_LOCAL int wc_GetContentType(const byte* input, word32* inOutIdx,
+                                word32* oid, word32 maxIdx);
+WOLFSSL_LOCAL int wc_CreateRecipientInfo(const byte* cert, word32 certSz,
+                                     int keyEncAlgo, int blockKeySz,
+                                     RNG* rng, byte* contentKeyPlain,
+                                     byte* contentKeyEnc,
+                                     int* keyEncSz, byte* out, word32 outSz);
+
+WOLFSSL_API int  wc_PKCS7_InitWithCert(PKCS7* pkcs7, byte* cert, word32 certSz);
+WOLFSSL_API void wc_PKCS7_Free(PKCS7* pkcs7);
+WOLFSSL_API int  wc_PKCS7_EncodeData(PKCS7* pkcs7, byte* output, word32 outputSz);
+WOLFSSL_API int  wc_PKCS7_EncodeSignedData(PKCS7* pkcs7,
+                                       byte* output, word32 outputSz);
+WOLFSSL_API int  wc_PKCS7_VerifySignedData(PKCS7* pkcs7,
+                                       byte* pkiMsg, word32 pkiMsgSz);
+WOLFSSL_API int  wc_PKCS7_EncodeEnvelopedData(PKCS7* pkcs7,
+                                          byte* output, word32 outputSz);
+WOLFSSL_API int  wc_PKCS7_DecodeEnvelopedData(PKCS7* pkcs7, byte* pkiMsg,
+                                          word32 pkiMsgSz, byte* output,
+                                          word32 outputSz);
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* HAVE_PKCS7 */
+#endif /* WOLF_CRYPT_PKCS7_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/poly1305.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/poly1305.h
new file mode 100644
index 0000000..0e76d06
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/poly1305.h
@@ -0,0 +1,81 @@
+/* poly1305.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_POLY1305_H
+#define WOLF_CRYPT_POLY1305_H
+
+#include 
+
+#ifdef HAVE_POLY1305
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+/* auto detect between 32bit / 64bit */
+#define HAS_SIZEOF_INT128_64BIT (defined(__SIZEOF_INT128__) && defined(__LP64__))
+#define HAS_MSVC_64BIT (defined(_MSC_VER) && defined(_M_X64))
+#define HAS_GCC_4_4_64BIT (defined(__GNUC__) && defined(__LP64__) && \
+        ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 4))))
+
+#if (HAS_SIZEOF_INT128_64BIT || HAS_MSVC_64BIT || HAS_GCC_4_4_64BIT)
+#define POLY130564
+#else
+#define POLY130532
+#endif
+
+enum {
+    POLY1305 = 7,
+    POLY1305_BLOCK_SIZE = 16,
+    POLY1305_DIGEST_SIZE = 16,
+    POLY1305_PAD_SIZE = 56
+};
+
+/* Poly1305 state */
+typedef struct Poly1305 {
+#if defined(POLY130564)
+	word64 r[3];
+	word64 h[3];
+	word64 pad[2];
+#else
+	word32 r[5];
+	word32 h[5];
+	word32 pad[4];
+#endif
+	size_t leftover;
+	unsigned char buffer[POLY1305_BLOCK_SIZE];
+	unsigned char final;
+} Poly1305;
+
+
+/* does init */
+
+WOLFSSL_API int wc_Poly1305SetKey(Poly1305* poly1305, const byte* key, word32 kySz);
+WOLFSSL_API int wc_Poly1305Update(Poly1305* poly1305, const byte*, word32);
+WOLFSSL_API int wc_Poly1305Final(Poly1305* poly1305, byte* tag);
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* HAVE_POLY1305 */
+#endif /* WOLF_CRYPT_POLY1305_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/port/pic32/pic32mz-crypt.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/port/pic32/pic32mz-crypt.h
new file mode 100644
index 0000000..44c54d7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/port/pic32/pic32mz-crypt.h
@@ -0,0 +1,138 @@
+/* pic32mz-crypt.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef PIC32MZ_CRYPT_H
+#define PIC32MZ_CRYPT_H
+
+#ifdef  WOLFSSL_MICROCHIP_PIC32MZ
+
+#define MICROCHIP_PIC32
+#include 
+#include 
+#include 
+
+typedef struct saCtrl {
+    unsigned int CRYPTOALGO : 4;
+    unsigned int MULTITASK : 3;
+    unsigned int KEYSIZE : 2;
+    unsigned int ENCTYPE : 1;
+    unsigned int ALGO : 7;
+    unsigned int : 3;
+    unsigned int FLAGS : 1;
+    unsigned int FB : 1;
+    unsigned int LOADIV : 1;
+    unsigned int LNC : 1;
+    unsigned int IRFLAG : 1;
+    unsigned int ICVONLY : 1;
+    unsigned int OR_EN : 1;
+    unsigned int NO_RX : 1;
+    unsigned int : 1;
+    unsigned int VERIFY : 1;
+    unsigned int : 2;
+} saCtrl;
+
+typedef struct securityAssociation {
+    saCtrl SA_CTRL;
+    unsigned int SA_AUTHKEY[8];
+    unsigned int SA_ENCKEY[8];
+    unsigned int SA_AUTHIV[8];
+    unsigned int SA_ENCIV[4];
+} securityAssociation;
+
+typedef struct bdCtrl {
+    unsigned int BUFLEN : 16;
+    unsigned int CBD_INT_EN : 1;
+    unsigned int PKT_INT_EN : 1;
+    unsigned int LIFM : 1;
+    unsigned int LAST_BD: 1;
+    unsigned int : 2;
+    unsigned int SA_FETCH_EN : 1;
+    unsigned int : 8;
+    unsigned int DESC_EN : 1;
+} bdCtrl;
+
+typedef struct bufferDescriptor {
+    bdCtrl BD_CTRL;
+    unsigned int SA_ADDR;
+    unsigned int SRCADDR;
+    unsigned int DSTADDR;
+    unsigned int NXTPTR;
+    unsigned int UPDPTR;
+    unsigned int MSGLEN;
+    unsigned int ENCOFF;
+} bufferDescriptor;
+
+
+#define PIC32_ENCRYPTION      0b1
+#define PIC32_DECRYPTION      0b0
+
+#define PIC32_ALGO_HMAC1     0b01000000
+#define PIC32_ALGO_SHA256    0b00100000
+#define PIC32_ALGO_SHA1      0b00010000
+#define PIC32_ALGO_MD5       0b00001000
+#define PIC32_ALGO_AES       0b00000100
+#define PIC32_ALGO_TDES      0b00000010
+#define PIC32_ALGO_DES       0b00000001
+
+#define PIC32_CRYPTOALGO_AES_GCM 0b1110
+#define PIC32_CRYPTOALGO_RCTR    0b1101
+#define PIC32_CRYPTOALGO_RCBC    0b1001
+#define PIC32_CRYPTOALGO_REBC    0b1000
+#define PIC32_CRYPTOALGO_TCBC    0b0101
+#define PIC32_CRYPTOALGO_CBC     0b0001
+
+#define PIC32_AES_KEYSIZE_256     0b10
+#define PIC32_AES_KEYSIZE_192     0b01
+#define PIC32_AES_KEYSIZE_128     0b00
+
+#define PIC32_AES_BLOCK_SIZE 16
+#define MD5_HASH_SIZE 16
+#define SHA1_HASH_SIZE 20
+#define SHA256_HASH_SIZE 32
+#define PIC32_HASH_SIZE 32
+
+#define PIC32MZ_MAX_BD   2
+typedef struct {      /* Crypt Engine descripter */
+    int bdCount ;
+    int err   ;
+    volatile bufferDescriptor 
+        bd[PIC32MZ_MAX_BD] __attribute__((aligned (8), coherent));
+    securityAssociation 
+        sa                 __attribute__((aligned (8), coherent));
+} pic32mz_desc ;
+
+#define PIC32MZ_IF_RAM(addr) (KVA_TO_PA(addr) < 0x80000)
+
+#define WAIT_ENGINE \
+    { volatile int v ; while (CESTATbits.ACTIVE) ; for(v=0; v<100; v++) ; }
+
+#ifdef DEBUG_CYASSL
+static void print_mem(const unsigned char *p, int size) {
+    for(; size>0; size--, p++) {
+        if(size%4 == 0)printf(" ") ;
+            printf("%02x", (int)*p) ;
+    }
+    puts("") ;
+}
+#endif
+
+#endif
+#endif /* PIC32MZ_CRYPT_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/port/ti/ti-ccm.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/port/ti/ti-ccm.h
new file mode 100644
index 0000000..f0fb247
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/port/ti/ti-ccm.h
@@ -0,0 +1,40 @@
+/* port/ti/ti_ccm.c
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#if defined(WOLFSSL_TI_CRYPT) ||  defined(WOLFSSL_TI_HASH)
+
+bool wolfSSL_TI_CCMInit(void) ;
+
+#ifndef SINGLE_THREADED
+void wolfSSL_TI_lockCCM() ;
+void wolfSSL_TI_unlockCCM() ;
+#else 
+#define wolfSSL_TI_lockCCM()
+#define wolfSSL_TI_unlockCCM()
+#endif
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/port/ti/ti-hash.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/port/ti/ti-hash.h
new file mode 100644
index 0000000..505ccc4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/port/ti/ti-hash.h
@@ -0,0 +1,64 @@
+/* port/ti/ti-hash.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+ 
+#ifndef WOLF_CRYPT_TI_HASH_H
+#define WOLF_CRYPT_TI_HASH_H
+
+#include 
+
+#ifndef WOLFSSL_TI_INITBUFF
+#define WOLFSSL_TI_INITBUFF 64
+#endif
+
+#define WOLFSSL_MAX_HASH_SIZE  64
+
+typedef struct {
+    byte   *msg ;
+    word32 used ;
+    word32 len ;
+    byte hash[WOLFSSL_MAX_HASH_SIZE] ;
+} wolfssl_TI_Hash ;
+
+
+#ifndef TI_HASH_TEST
+#if !defined(NO_MD5)
+typedef wolfssl_TI_Hash Md5 ;
+
+#endif
+#if !defined(NO_SHA)
+typedef wolfssl_TI_Hash Sha ;
+#endif
+#if !defined(NO_SHA256)
+typedef wolfssl_TI_Hash Sha256 ;
+#endif
+
+#if defined(HAVE_SHA224)
+typedef wolfssl_TI_Hash Sha224 ;
+#define SHA224_DIGEST_SIZE  28
+
+WOLFSSL_API int wc_InitSha224(Sha224* sha224) ;
+WOLFSSL_API int wc_Sha224Update(Sha224* sha224, const byte* data, word32 len) ;
+WOLFSSL_API int wc_Sha224Final(Sha224* sha224, byte* hash) ;
+WOLFSSL_API int wc_Sha224Hash(const byte* data, word32 len, byte*hash) ;
+
+#endif
+#endif
+#endif /* WOLF_CRYPT_TI_HASH_H  */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/pwdbased.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/pwdbased.h
new file mode 100644
index 0000000..0173bee
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/pwdbased.h
@@ -0,0 +1,65 @@
+/* pwdbased.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_PWDBASED_H
+#define WOLF_CRYPT_PWDBASED_H
+
+#include 
+
+#ifndef NO_PWDBASED
+
+#ifndef NO_MD5
+    #include        /* for hash type */
+#endif
+
+#include 
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+/*
+ * hashType renamed to typeH to avoid shadowing global declation here:
+ * wolfssl/wolfcrypt/asn.h line 173 in enum Oid_Types
+ */
+WOLFSSL_API int wc_PBKDF1(byte* output, const byte* passwd, int pLen,
+                      const byte* salt, int sLen, int iterations, int kLen,
+                      int typeH);
+WOLFSSL_API int wc_PBKDF2(byte* output, const byte* passwd, int pLen,
+                      const byte* salt, int sLen, int iterations, int kLen,
+                      int typeH);
+WOLFSSL_API int wc_PKCS12_PBKDF(byte* output, const byte* passwd, int pLen,
+                            const byte* salt, int sLen, int iterations,
+                            int kLen, int typeH, int purpose);
+
+/* helper functions */
+WOLFSSL_LOCAL int GetDigestSize(int hashType);
+WOLFSSL_LOCAL int GetPKCS12HashSizes(int hashType, word32* v, word32* u);
+WOLFSSL_LOCAL int DoPKCS12Hash(int hashType, byte* buffer, word32 totalLen,
+                               byte* Ai, word32 u, int iterations);
+
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* NO_PWDBASED */
+#endif /* WOLF_CRYPT_PWDBASED_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/rabbit.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/rabbit.h
new file mode 100644
index 0000000..ea5ae73
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/rabbit.h
@@ -0,0 +1,64 @@
+/* rabbit.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_RABBIT_H
+#define WOLF_CRYPT_RABBIT_H
+
+#include 
+
+#ifndef NO_RABBIT
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+
+enum {
+	RABBIT_ENC_TYPE  = 5     /* cipher unique type */
+};
+
+
+/* Rabbit Context */
+typedef struct RabbitCtx {
+    word32 x[8];
+    word32 c[8];
+    word32 carry;
+} RabbitCtx;
+
+
+/* Rabbit stream cipher */
+typedef struct Rabbit {
+    RabbitCtx masterCtx;
+    RabbitCtx workCtx;
+} Rabbit;
+
+
+WOLFSSL_API int wc_RabbitProcess(Rabbit*, byte*, const byte*, word32);
+WOLFSSL_API int wc_RabbitSetKey(Rabbit*, const byte* key, const byte* iv);
+
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* NO_RABBIT */
+#endif /* WOLF_CRYPT_RABBIT_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/random.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/random.h
new file mode 100644
index 0000000..1921443
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/random.h
@@ -0,0 +1,143 @@
+/* random.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifndef WOLF_CRYPT_RANDOM_H
+#define WOLF_CRYPT_RANDOM_H
+
+#include 
+
+#ifdef HAVE_FIPS
+/* for fips @wc_fips */
+#include 
+#endif
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#ifndef HAVE_FIPS /* avoid redefining structs and macros */
+#if defined(HAVE_HASHDRBG) || defined(NO_RC4)
+    #ifdef NO_SHA256
+        #error "Hash DRBG requires SHA-256."
+    #endif /* NO_SHA256 */
+
+    #include 
+#else /* HAVE_HASHDRBG || NO_RC4 */
+    #include 
+#endif /* HAVE_HASHDRBG || NO_RC4 */
+
+#if defined(USE_WINDOWS_API)
+    #if defined(_WIN64)
+        typedef unsigned __int64 ProviderHandle;
+        /* type HCRYPTPROV, avoid #include  */
+    #else
+        typedef unsigned long ProviderHandle;
+    #endif
+#endif
+
+
+/* OS specific seeder */
+typedef struct OS_Seed {
+    #if defined(USE_WINDOWS_API)
+        ProviderHandle handle;
+    #else
+        int fd;
+    #endif
+} OS_Seed;
+
+
+#if defined(WOLFSSL_MDK_ARM)
+#undef RNG
+#define RNG wolfSSL_RNG   /* for avoiding name conflict in "stm32f2xx.h" */
+#endif
+
+
+#if defined(HAVE_HASHDRBG) || defined(NO_RC4)
+
+
+#define DRBG_SEED_LEN (440/8)
+
+
+struct DRBG; /* Private DRBG state */
+
+
+/* Hash-based Deterministic Random Bit Generator */
+typedef struct RNG {
+    struct DRBG* drbg;
+    OS_Seed seed;
+    byte status;
+} RNG;
+
+
+#else /* HAVE_HASHDRBG || NO_RC4 */
+
+
+#define WOLFSSL_RNG_CAVIUM_MAGIC 0xBEEF0004
+
+/* secure Random Number Generator */
+
+
+typedef struct RNG {
+    OS_Seed seed;
+    Arc4    cipher;
+#ifdef HAVE_CAVIUM
+    int    devId;           /* nitrox device id */
+    word32 magic;           /* using cavium magic */
+#endif
+} RNG;
+
+
+#endif /* HAVE_HASH_DRBG || NO_RC4 */
+
+#endif /* HAVE_FIPS */
+
+WOLFSSL_LOCAL
+int wc_GenerateSeed(OS_Seed* os, byte* seed, word32 sz);
+
+#if defined(HAVE_HASHDRBG) || defined(NO_RC4)
+
+#ifdef HAVE_CAVIUM
+    WOLFSSL_API int  wc_InitRngCavium(RNG*, int);
+#endif
+
+#endif /* HAVE_HASH_DRBG || NO_RC4 */
+
+
+WOLFSSL_API int  wc_InitRng(RNG*);
+WOLFSSL_API int  wc_RNG_GenerateBlock(RNG*, byte*, word32 sz);
+WOLFSSL_API int  wc_RNG_GenerateByte(RNG*, byte*);
+WOLFSSL_API int  wc_FreeRng(RNG*);
+
+
+#if defined(HAVE_HASHDRBG) || defined(NO_RC4)
+    WOLFSSL_API int wc_RNG_HealthTest(int reseed,
+                                        const byte* entropyA, word32 entropyASz,
+                                        const byte* entropyB, word32 entropyBSz,
+                                        byte* output, word32 outputSz);
+#endif /* HAVE_HASHDRBG || NO_RC4 */
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* WOLF_CRYPT_RANDOM_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/ripemd.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/ripemd.h
new file mode 100644
index 0000000..a76b64d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/ripemd.h
@@ -0,0 +1,63 @@
+/* ripemd.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_RIPEMD_H
+#define WOLF_CRYPT_RIPEMD_H
+
+#include 
+
+#ifdef WOLFSSL_RIPEMD
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+
+/* in bytes */
+enum {
+    RIPEMD             =  3,    /* hash type unique */
+    RIPEMD_BLOCK_SIZE  = 64,
+    RIPEMD_DIGEST_SIZE = 20,
+    RIPEMD_PAD_SIZE    = 56
+};
+
+
+/* RipeMd 160 digest */
+typedef struct RipeMd {
+    word32  buffLen;   /* in bytes          */
+    word32  loLen;     /* length in bytes   */
+    word32  hiLen;     /* length in bytes   */
+    word32  digest[RIPEMD_DIGEST_SIZE / sizeof(word32)];
+    word32  buffer[RIPEMD_BLOCK_SIZE  / sizeof(word32)];
+} RipeMd;
+
+
+WOLFSSL_API void wc_InitRipeMd(RipeMd*);
+WOLFSSL_API void wc_RipeMdUpdate(RipeMd*, const byte*, word32);
+WOLFSSL_API void wc_RipeMdFinal(RipeMd*, byte*);
+
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* WOLFSSL_RIPEMD */
+#endif /* WOLF_CRYPT_RIPEMD_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/rsa.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/rsa.h
new file mode 100644
index 0000000..5441535
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/rsa.h
@@ -0,0 +1,121 @@
+/* rsa.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_RSA_H
+#define WOLF_CRYPT_RSA_H
+
+#include 
+
+#ifndef NO_RSA
+
+#ifdef HAVE_FIPS
+/* for fips @wc_fips */
+#include 
+#if defined(CYASSL_KEY_GEN) && !defined(WOLFSSL_KEY_GEN)
+    #define WOLFSSL_KEY_GEN
+#endif
+#else
+    #include 
+    #include 
+#endif /* HAVE_FIPS */
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#ifndef HAVE_FIPS /* avoid redefinition of structs */
+#define WOLFSSL_RSA_CAVIUM_MAGIC 0xBEEF0006
+
+enum {
+    RSA_PUBLIC   = 0,
+    RSA_PRIVATE  = 1
+};
+
+/* RSA */
+typedef struct RsaKey {
+    mp_int n, e, d, p, q, dP, dQ, u;
+    int   type;                               /* public or private */
+    void* heap;                               /* for user memory overrides */
+#ifdef HAVE_CAVIUM
+    int    devId;           /* nitrox device id */
+    word32 magic;           /* using cavium magic */
+    word64 contextHandle;   /* nitrox context memory handle */
+    byte*  c_n;             /* cavium byte buffers for key parts */
+    byte*  c_e;
+    byte*  c_d;
+    byte*  c_p;
+    byte*  c_q;
+    byte*  c_dP;
+    byte*  c_dQ;
+    byte*  c_u;             /* sizes in bytes */
+    word16 c_nSz, c_eSz, c_dSz, c_pSz, c_qSz, c_dP_Sz, c_dQ_Sz, c_uSz;
+#endif
+} RsaKey;
+#endif /*HAVE_FIPS */
+
+
+WOLFSSL_API int  wc_InitRsaKey(RsaKey* key, void*);
+WOLFSSL_API int  wc_FreeRsaKey(RsaKey* key);
+
+WOLFSSL_API int  wc_RsaPublicEncrypt(const byte* in, word32 inLen, byte* out,
+                                 word32 outLen, RsaKey* key, RNG* rng);
+WOLFSSL_API int  wc_RsaPrivateDecryptInline(byte* in, word32 inLen, byte** out,
+                                        RsaKey* key);
+WOLFSSL_API int  wc_RsaPrivateDecrypt(const byte* in, word32 inLen, byte* out,
+                                  word32 outLen, RsaKey* key);
+WOLFSSL_API int  wc_RsaSSL_Sign(const byte* in, word32 inLen, byte* out,
+                            word32 outLen, RsaKey* key, RNG* rng);
+WOLFSSL_API int  wc_RsaSSL_VerifyInline(byte* in, word32 inLen, byte** out,
+                                    RsaKey* key);
+WOLFSSL_API int  wc_RsaSSL_Verify(const byte* in, word32 inLen, byte* out,
+                              word32 outLen, RsaKey* key);
+WOLFSSL_API int  wc_RsaEncryptSize(RsaKey* key);
+
+#ifndef HAVE_FIPS /* to avoid asn duplicate symbols @wc_fips */
+WOLFSSL_API int  wc_RsaPrivateKeyDecode(const byte* input, word32* inOutIdx,
+                                                               RsaKey*, word32);
+WOLFSSL_API int  wc_RsaPublicKeyDecode(const byte* input, word32* inOutIdx,
+                                                               RsaKey*, word32);
+WOLFSSL_API int  wc_RsaPublicKeyDecodeRaw(const byte* n, word32 nSz,
+                                        const byte* e, word32 eSz, RsaKey* key);
+#ifdef WOLFSSL_KEY_GEN
+    WOLFSSL_API int wc_RsaKeyToDer(RsaKey*, byte* output, word32 inLen);
+#endif
+#endif /* HAVE_FIPS*/
+WOLFSSL_API int  wc_RsaFlattenPublicKey(RsaKey*, byte*, word32*, byte*,
+                                                                       word32*);
+
+#ifdef WOLFSSL_KEY_GEN
+    WOLFSSL_API int wc_MakeRsaKey(RsaKey* key, int size, long e, RNG* rng);
+#endif
+
+#ifdef HAVE_CAVIUM
+    WOLFSSL_API int  wc_RsaInitCavium(RsaKey*, int);
+    WOLFSSL_API void wc_RsaFreeCavium(RsaKey*);
+#endif
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* NO_RSA */
+#endif /* WOLF_CRYPT_RSA_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/settings.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/settings.h
new file mode 100644
index 0000000..57c404a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/settings.h
@@ -0,0 +1,800 @@
+/* settings.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+/* Place OS specific preprocessor flags, defines, includes here, will be
+   included into every file because types.h includes it */
+
+
+#ifndef WOLF_CRYPT_SETTINGS_H
+#define WOLF_CRYPT_SETTINGS_H
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+/* Uncomment next line if using IPHONE */
+/* #define IPHONE */
+
+/* Uncomment next line if using ThreadX */
+/* #define THREADX */
+
+/* Uncomment next line if using Micrium ucOS */
+/* #define MICRIUM */
+
+/* Uncomment next line if using Mbed */
+/* #define MBED */
+
+/* Uncomment next line if using Microchip PIC32 ethernet starter kit */
+/* #define MICROCHIP_PIC32 */
+
+/* Uncomment next line if using Microchip TCP/IP stack, version 5 */
+/* #define MICROCHIP_TCPIP_V5 */
+
+/* Uncomment next line if using Microchip TCP/IP stack, version 6 or later */
+/* #define MICROCHIP_TCPIP */
+
+/* Uncomment next line if using PIC32MZ Crypto Engine */
+/* #define WOLFSSL_MICROCHIP_PIC32MZ */
+
+/* Uncomment next line if using FreeRTOS */
+/* #define FREERTOS */
+
+/* Uncomment next line if using FreeRTOS Windows Simulator */
+/* #define FREERTOS_WINSIM */
+
+/* Uncomment next line if using RTIP */
+/* #define EBSNET */
+
+/* Uncomment next line if using lwip */
+/* #define WOLFSSL_LWIP */
+
+/* Uncomment next line if building wolfSSL for a game console */
+/* #define WOLFSSL_GAME_BUILD */
+
+/* Uncomment next line if building wolfSSL for LSR */
+/* #define WOLFSSL_LSR */
+
+/* Uncomment next line if building wolfSSL for Freescale MQX/RTCS/MFS */
+/* #define FREESCALE_MQX */
+
+/* Uncomment next line if using STM32F2 */
+/* #define WOLFSSL_STM32F2 */
+
+/* Uncomment next line if using Comverge settings */
+/* #define COMVERGE */
+
+/* Uncomment next line if using QL SEP settings */
+/* #define WOLFSSL_QL */
+
+/* Uncomment next line if building for EROAD */
+/* #define WOLFSSL_EROAD */
+
+/* Uncomment next line if building for IAR EWARM */
+/* #define WOLFSSL_IAR_ARM */
+
+/* Uncomment next line if using TI-RTOS settings */
+/* #define WOLFSSL_TIRTOS */
+
+/* Uncomment next line if building with PicoTCP */
+/* #define WOLFSSL_PICOTCP */
+
+/* Uncomment next line if building for PicoTCP demo bundle */
+/* #define WOLFSSL_PICOTCP_DEMO */
+
+/* Uncomment next line if building for uITRON4  */
+/* #define WOLFSSL_uITRON4 */
+
+/* Uncomment next line if building for uT-Kernel */
+/* #define WOLFSSL_uTKERNEL2 */
+
+/* Uncomment next line if using Max Strength build */
+/* #define WOLFSSL_MAX_STRENGTH */
+
+/* Uncomment next line if building for VxWorks */
+/* #define WOLFSSL_VXWORKS */
+
+#include 
+
+#ifdef WOLFSSL_USER_SETTINGS
+    #include 
+#endif
+
+
+#ifdef IPHONE
+    #define SIZEOF_LONG_LONG 8
+#endif
+
+
+#ifdef COMVERGE
+    #define THREADX
+    #define HAVE_NETX
+    #define WOLFSSL_USER_IO
+    #define NO_WRITEV
+    #define NO_DEV_RANDOM
+    #define NO_FILESYSTEM
+    #define NO_SHA512
+    #define NO_DH
+    #define NO_DSA
+    #define NO_HC128
+    #define NO_RSA
+    #define NO_SESSION_CACHE
+    #define HAVE_ECC
+#endif
+
+
+#ifdef THREADX
+    #define SIZEOF_LONG_LONG 8
+#endif
+
+#ifdef HAVE_NETX
+    #include "nx_api.h"
+#endif
+
+#if defined(HAVE_LWIP_NATIVE) /* using LwIP native TCP socket */
+    #define WOLFSSL_LWIP
+    #define NO_WRITEV
+    #define SINGLE_THREADED
+    #define WOLFSSL_USER_IO
+    #define NO_FILESYSTEM
+#endif
+
+#if defined(WOLFSSL_IAR_ARM)
+    #define NO_MAIN_DRIVER
+    #define SINGLE_THREADED
+    #define USE_CERT_BUFFERS_1024
+    #define BENCH_EMBEDDED
+    #define NO_FILESYSTEM
+    #define NO_WRITEV
+    #define WOLFSSL_USER_IO
+    #define  BENCH_EMBEDDED
+#endif
+
+#ifdef MICROCHIP_PIC32
+    /* #define WOLFSSL_MICROCHIP_PIC32MZ */
+    #define SIZEOF_LONG_LONG 8
+    #define SINGLE_THREADED
+    #define WOLFSSL_USER_IO
+    #define NO_WRITEV
+    #define NO_DEV_RANDOM
+    #define NO_FILESYSTEM
+    #define USE_FAST_MATH
+    #define TFM_TIMING_RESISTANT
+    #define NEED_AES_TABLES
+#endif
+
+#ifdef WOLFSSL_MICROCHIP_PIC32MZ
+    #define WOLFSSL_PIC32MZ_CE
+    #define WOLFSSL_PIC32MZ_CRYPT
+    #define HAVE_AES_ENGINE
+    #define WOLFSSL_PIC32MZ_RNG
+    /* #define WOLFSSL_PIC32MZ_HASH */
+    #define WOLFSSL_AES_COUNTER
+    #define HAVE_AESGCM
+    #define NO_BIG_INT
+#endif
+
+#ifdef MICROCHIP_TCPIP_V5
+    /* include timer functions */
+    #include "TCPIP Stack/TCPIP.h"
+#endif
+
+#ifdef MICROCHIP_TCPIP
+    /* include timer, NTP functions */
+    #ifdef MICROCHIP_MPLAB_HARMONY
+        #include "tcpip/tcpip.h"
+    #else
+        #include "system/system_services.h"
+        #include "tcpip/sntp.h"
+    #endif
+#endif
+
+#ifdef MBED
+    #define WOLFSSL_USER_IO
+    #define NO_FILESYSTEM
+    #define NO_CERT
+    #define USE_CERT_BUFFERS_1024
+    #define NO_WRITEV
+    #define NO_DEV_RANDOM
+    #define NO_SHA512
+    #define NO_DH
+    #define NO_DSA
+    #define NO_HC128
+    #define HAVE_ECC
+    #define NO_SESSION_CACHE
+    #define WOLFSSL_CMSIS_RTOS
+#endif
+
+
+#ifdef WOLFSSL_EROAD
+    #define FREESCALE_MQX
+    #define FREESCALE_MMCAU
+    #define SINGLE_THREADED
+    #define NO_STDIO_FILESYSTEM
+    #define WOLFSSL_LEANPSK
+    #define HAVE_NULL_CIPHER
+    #define NO_OLD_TLS
+    #define NO_ASN
+    #define NO_BIG_INT
+    #define NO_RSA
+    #define NO_DSA
+    #define NO_DH
+    #define NO_CERTS
+    #define NO_PWDBASED
+    #define NO_DES3
+    #define NO_MD4
+    #define NO_RC4
+    #define NO_MD5
+    #define NO_SESSION_CACHE
+    #define NO_MAIN_DRIVER
+#endif
+
+#ifdef WOLFSSL_PICOTCP
+    #ifndef errno
+        #define errno pico_err
+    #endif
+    #include "pico_defines.h"
+    #include "pico_stack.h"
+    #include "pico_constants.h"
+    #include "pico_protocol.h"
+    #define CUSTOM_RAND_GENERATE pico_rand
+#endif
+
+#ifdef WOLFSSL_PICOTCP_DEMO
+    #define WOLFSSL_STM32
+    #define USE_FAST_MATH
+    #define TFM_TIMING_RESISTANT
+    #define XMALLOC(s, h, type)  PICO_ZALLOC((s))
+    #define XFREE(p, h, type)    PICO_FREE((p))
+    #define SINGLE_THREADED
+    #define NO_WRITEV
+    #define WOLFSSL_USER_IO
+    #define NO_DEV_RANDOM
+    #define NO_FILESYSTEM
+#endif
+
+#ifdef FREERTOS_WINSIM
+    #define FREERTOS
+    #define USE_WINDOWS_API
+#endif
+
+
+#ifdef WOLFSSL_VXWORKS
+    #define NO_DEV_RANDOM
+    #define NO_WRITEV
+#endif
+
+
+/* Micrium will use Visual Studio for compilation but not the Win32 API */
+#if defined(_WIN32) && !defined(MICRIUM) && !defined(FREERTOS) \
+        && !defined(EBSNET) && !defined(WOLFSSL_EROAD)
+    #define USE_WINDOWS_API
+#endif
+
+
+#if defined(WOLFSSL_LEANPSK) && !defined(XMALLOC_USER)
+    #include 
+    #define XMALLOC(s, h, type)  malloc((s))
+    #define XFREE(p, h, type)    free((p))
+    #define XREALLOC(p, n, h, t) realloc((p), (n))
+#endif
+
+#if defined(XMALLOC_USER) && defined(SSN_BUILDING_LIBYASSL)
+    #undef  XMALLOC
+    #define XMALLOC     yaXMALLOC
+    #undef  XFREE
+    #define XFREE       yaXFREE
+    #undef  XREALLOC
+    #define XREALLOC    yaXREALLOC
+#endif
+
+
+#ifdef FREERTOS
+    #ifndef NO_WRITEV
+        #define NO_WRITEV
+    #endif
+    #ifndef HAVE_SHA512
+        #ifndef NO_SHA512
+            #define NO_SHA512
+        #endif
+    #endif
+    #ifndef HAVE_DH
+        #ifndef NO_DH
+            #define NO_DH
+        #endif
+    #endif
+    #ifndef NO_DSA
+        #define NO_DSA
+    #endif
+    #ifndef NO_HC128
+        #define NO_HC128
+    #endif
+
+    #ifndef SINGLE_THREADED
+        #include "FreeRTOS.h"
+        #include "semphr.h"
+    #endif
+#endif
+
+#ifdef WOLFSSL_TIRTOS
+    #define SIZEOF_LONG_LONG 8
+    #define NO_WRITEV
+    #define NO_WOLFSSL_DIR
+    #define USE_FAST_MATH
+    #define TFM_TIMING_RESISTANT
+    #define NO_DEV_RANDOM
+    #define NO_FILESYSTEM
+    #define USE_CERT_BUFFERS_2048
+    #define NO_ERROR_STRINGS
+    #define USER_TIME
+
+    #ifdef __IAR_SYSTEMS_ICC__
+        #pragma diag_suppress=Pa089
+    #elif !defined(__GNUC__)
+        /* Suppress the sslpro warning */
+        #pragma diag_suppress=11
+    #endif
+
+    #include 
+#endif
+
+#ifdef EBSNET
+    #include "rtip.h"
+
+    /* #define DEBUG_WOLFSSL */
+    #define NO_WOLFSSL_DIR  /* tbd */
+
+    #if (POLLOS)
+        #define SINGLE_THREADED
+    #endif
+
+    #if (RTPLATFORM)
+        #if (!RTP_LITTLE_ENDIAN)
+            #define BIG_ENDIAN_ORDER
+        #endif
+    #else
+        #if (!KS_LITTLE_ENDIAN)
+            #define BIG_ENDIAN_ORDER
+        #endif
+    #endif
+
+    #if (WINMSP3)
+        #undef SIZEOF_LONG
+        #define SIZEOF_LONG_LONG 8
+    #else
+        #sslpro: settings.h - please implement SIZEOF_LONG and SIZEOF_LONG_LONG
+    #endif
+
+    #define XMALLOC(s, h, type) ((void *)rtp_malloc((s), SSL_PRO_MALLOC))
+    #define XFREE(p, h, type) (rtp_free(p))
+    #define XREALLOC(p, n, h, t) realloc((p), (n))
+
+#endif /* EBSNET */
+
+#ifdef WOLFSSL_GAME_BUILD
+    #define SIZEOF_LONG_LONG 8
+    #if defined(__PPU) || defined(__XENON)
+        #define BIG_ENDIAN_ORDER
+    #endif
+#endif
+
+#ifdef WOLFSSL_LSR
+    #define HAVE_WEBSERVER
+    #define SIZEOF_LONG_LONG 8
+    #define WOLFSSL_LOW_MEMORY
+    #define NO_WRITEV
+    #define NO_SHA512
+    #define NO_DH
+    #define NO_DSA
+    #define NO_HC128
+    #define NO_DEV_RANDOM
+    #define NO_WOLFSSL_DIR
+    #define NO_RABBIT
+    #ifndef NO_FILESYSTEM
+        #define LSR_FS
+        #include "inc/hw_types.h"
+        #include "fs.h"
+    #endif
+    #define WOLFSSL_LWIP
+    #include   /* for tcp errno */
+    #define WOLFSSL_SAFERTOS
+    #if defined(__IAR_SYSTEMS_ICC__)
+        /* enum uses enum */
+        #pragma diag_suppress=Pa089
+    #endif
+#endif
+
+#ifdef WOLFSSL_SAFERTOS
+    #ifndef SINGLE_THREADED
+        #include "SafeRTOS/semphr.h"
+    #endif
+
+    #include "SafeRTOS/heap.h"
+    #define XMALLOC(s, h, type)  pvPortMalloc((s))
+    #define XFREE(p, h, type)    vPortFree((p))
+    #define XREALLOC(p, n, h, t) pvPortRealloc((p), (n))
+#endif
+
+#ifdef WOLFSSL_LOW_MEMORY
+    #undef  RSA_LOW_MEM
+    #define RSA_LOW_MEM
+    #undef  WOLFSSL_SMALL_STACK
+    #define WOLFSSL_SMALL_STACK
+    #undef  TFM_TIMING_RESISTANT
+    #define TFM_TIMING_RESISTANT
+#endif
+
+#ifdef FREESCALE_MQX
+    #define SIZEOF_LONG_LONG 8
+    #define NO_WRITEV
+    #define NO_DEV_RANDOM
+    #define NO_RABBIT
+    #define NO_WOLFSSL_DIR
+    #define USE_FAST_MATH
+    #define TFM_TIMING_RESISTANT
+    #define FREESCALE_K70_RNGA
+    /* #define FREESCALE_K53_RNGB */
+    #include "mqx.h"
+    #ifndef NO_FILESYSTEM
+        #include "mfs.h"
+        #include "fio.h"
+    #endif
+    #ifndef SINGLE_THREADED
+        #include "mutex.h"
+    #endif
+
+    #define XMALLOC(s, h, t)    (void *)_mem_alloc_system((s))
+    #define XFREE(p, h, t)      {void* xp = (p); if ((xp)) _mem_free((xp));}
+    /* Note: MQX has no realloc, using fastmath above */
+#endif
+
+#ifdef WOLFSSL_STM32F2
+    #define SIZEOF_LONG_LONG 8
+    #define NO_DEV_RANDOM
+    #define NO_WOLFSSL_DIR
+    #define NO_RABBIT
+    #define STM32F2_RNG
+    #define STM32F2_CRYPTO
+    #define KEIL_INTRINSICS
+#endif
+
+#ifdef MICRIUM
+
+    #include "stdlib.h"
+    #include "net_cfg.h"
+    #include "ssl_cfg.h"
+    #include "net_secure_os.h"
+
+    #define WOLFSSL_TYPES
+
+    typedef CPU_INT08U byte;
+    typedef CPU_INT16U word16;
+    typedef CPU_INT32U word32;
+
+    #if (NET_SECURE_MGR_CFG_WORD_SIZE == CPU_WORD_SIZE_32)
+        #define SIZEOF_LONG        4
+        #undef  SIZEOF_LONG_LONG
+    #else
+        #undef  SIZEOF_LONG
+        #define SIZEOF_LONG_LONG   8
+    #endif
+
+    #define STRING_USER
+
+    #define XSTRLEN(pstr) ((CPU_SIZE_T)Str_Len((CPU_CHAR *)(pstr)))
+    #define XSTRNCPY(pstr_dest, pstr_src, len_max) \
+                    ((CPU_CHAR *)Str_Copy_N((CPU_CHAR *)(pstr_dest), \
+                     (CPU_CHAR *)(pstr_src), (CPU_SIZE_T)(len_max)))
+    #define XSTRNCMP(pstr_1, pstr_2, len_max) \
+                    ((CPU_INT16S)Str_Cmp_N((CPU_CHAR *)(pstr_1), \
+                     (CPU_CHAR *)(pstr_2), (CPU_SIZE_T)(len_max)))
+    #define XSTRSTR(pstr, pstr_srch) \
+                    ((CPU_CHAR *)Str_Str((CPU_CHAR *)(pstr), \
+                     (CPU_CHAR *)(pstr_srch)))
+    #define XMEMSET(pmem, data_val, size) \
+                    ((void)Mem_Set((void *)(pmem), (CPU_INT08U) (data_val), \
+                    (CPU_SIZE_T)(size)))
+    #define XMEMCPY(pdest, psrc, size) ((void)Mem_Copy((void *)(pdest), \
+                     (void *)(psrc), (CPU_SIZE_T)(size)))
+    #define XMEMCMP(pmem_1, pmem_2, size) \
+                   (((CPU_BOOLEAN)Mem_Cmp((void *)(pmem_1), (void *)(pmem_2), \
+                     (CPU_SIZE_T)(size))) ? DEF_NO : DEF_YES)
+    #define XMEMMOVE XMEMCPY
+
+#if (NET_SECURE_MGR_CFG_EN == DEF_ENABLED)
+    #define MICRIUM_MALLOC
+    #define XMALLOC(s, h, type) ((void *)NetSecure_BlkGet((CPU_INT08U)(type), \
+                                 (CPU_SIZE_T)(s), (void *)0))
+    #define XFREE(p, h, type)   (NetSecure_BlkFree((CPU_INT08U)(type), \
+                                 (p), (void *)0))
+    #define XREALLOC(p, n, h, t) realloc((p), (n))
+#endif
+
+    #if (NET_SECURE_MGR_CFG_FS_EN == DEF_ENABLED)
+        #undef  NO_FILESYSTEM
+    #else
+        #define NO_FILESYSTEM
+    #endif
+
+    #if (SSL_CFG_TRACE_LEVEL == WOLFSSL_TRACE_LEVEL_DBG)
+        #define DEBUG_WOLFSSL
+    #else
+        #undef  DEBUG_WOLFSSL
+    #endif
+
+    #if (SSL_CFG_OPENSSL_EN == DEF_ENABLED)
+        #define OPENSSL_EXTRA
+    #else
+        #undef  OPENSSL_EXTRA
+    #endif
+
+    #if (SSL_CFG_MULTI_THREAD_EN == DEF_ENABLED)
+        #undef  SINGLE_THREADED
+    #else
+        #define SINGLE_THREADED
+    #endif
+
+    #if (SSL_CFG_DH_EN == DEF_ENABLED)
+        #undef  NO_DH
+    #else
+        #define NO_DH
+    #endif
+
+    #if (SSL_CFG_DSA_EN == DEF_ENABLED)
+        #undef  NO_DSA
+    #else
+        #define NO_DSA
+    #endif
+
+    #if (SSL_CFG_PSK_EN == DEF_ENABLED)
+        #undef  NO_PSK
+    #else
+        #define NO_PSK
+    #endif
+
+    #if (SSL_CFG_3DES_EN == DEF_ENABLED)
+        #undef  NO_DES
+    #else
+        #define NO_DES
+    #endif
+
+    #if (SSL_CFG_AES_EN == DEF_ENABLED)
+        #undef  NO_AES
+    #else
+        #define NO_AES
+    #endif
+
+    #if (SSL_CFG_RC4_EN == DEF_ENABLED)
+        #undef  NO_RC4
+    #else
+        #define NO_RC4
+    #endif
+
+    #if (SSL_CFG_RABBIT_EN == DEF_ENABLED)
+        #undef  NO_RABBIT
+    #else
+        #define NO_RABBIT
+    #endif
+
+    #if (SSL_CFG_HC128_EN == DEF_ENABLED)
+        #undef  NO_HC128
+    #else
+        #define NO_HC128
+    #endif
+
+    #if (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_BIG)
+        #define BIG_ENDIAN_ORDER
+    #else
+        #undef  BIG_ENDIAN_ORDER
+        #define LITTLE_ENDIAN_ORDER
+    #endif
+
+    #if (SSL_CFG_MD4_EN == DEF_ENABLED)
+        #undef  NO_MD4
+    #else
+        #define NO_MD4
+    #endif
+
+    #if (SSL_CFG_WRITEV_EN == DEF_ENABLED)
+        #undef  NO_WRITEV
+    #else
+        #define NO_WRITEV
+    #endif
+
+    #if (SSL_CFG_USER_RNG_SEED_EN == DEF_ENABLED)
+        #define NO_DEV_RANDOM
+    #else
+        #undef  NO_DEV_RANDOM
+    #endif
+
+    #if (SSL_CFG_USER_IO_EN == DEF_ENABLED)
+        #define WOLFSSL_USER_IO
+    #else
+        #undef  WOLFSSL_USER_IO
+    #endif
+
+    #if (SSL_CFG_DYNAMIC_BUFFERS_EN == DEF_ENABLED)
+        #undef  LARGE_STATIC_BUFFERS
+        #undef  STATIC_CHUNKS_ONLY
+    #else
+        #define LARGE_STATIC_BUFFERS
+        #define STATIC_CHUNKS_ONLY
+    #endif
+
+    #if (SSL_CFG_DER_LOAD_EN == DEF_ENABLED)
+        #define  WOLFSSL_DER_LOAD
+    #else
+        #undef   WOLFSSL_DER_LOAD
+    #endif
+
+    #if (SSL_CFG_DTLS_EN == DEF_ENABLED)
+        #define  WOLFSSL_DTLS
+    #else
+        #undef   WOLFSSL_DTLS
+    #endif
+
+    #if (SSL_CFG_CALLBACKS_EN == DEF_ENABLED)
+         #define WOLFSSL_CALLBACKS
+    #else
+         #undef  WOLFSSL_CALLBACKS
+    #endif
+
+    #if (SSL_CFG_FAST_MATH_EN == DEF_ENABLED)
+         #define USE_FAST_MATH
+    #else
+         #undef  USE_FAST_MATH
+    #endif
+
+    #if (SSL_CFG_TFM_TIMING_RESISTANT_EN == DEF_ENABLED)
+         #define TFM_TIMING_RESISTANT
+    #else
+         #undef  TFM_TIMING_RESISTANT
+    #endif
+
+#endif /* MICRIUM */
+
+
+#ifdef WOLFSSL_QL
+    #ifndef WOLFSSL_SEP
+        #define WOLFSSL_SEP
+    #endif
+    #ifndef OPENSSL_EXTRA
+        #define OPENSSL_EXTRA
+    #endif
+    #ifndef SESSION_CERTS
+        #define SESSION_CERTS
+    #endif
+    #ifndef HAVE_AESCCM
+        #define HAVE_AESCCM
+    #endif
+    #ifndef ATOMIC_USER
+        #define ATOMIC_USER
+    #endif
+    #ifndef WOLFSSL_DER_LOAD
+        #define WOLFSSL_DER_LOAD
+    #endif
+    #ifndef KEEP_PEER_CERT
+        #define KEEP_PEER_CERT
+    #endif
+    #ifndef HAVE_ECC
+        #define HAVE_ECC
+    #endif
+    #ifndef SESSION_INDEX
+        #define SESSION_INDEX
+    #endif
+#endif /* WOLFSSL_QL */
+
+
+#if !defined(XMALLOC_USER) && !defined(MICRIUM_MALLOC) && \
+    !defined(WOLFSSL_LEANPSK) && !defined(NO_WOLFSSL_MEMORY)
+    #define USE_WOLFSSL_MEMORY
+#endif
+
+
+#if defined(OPENSSL_EXTRA) && !defined(NO_CERTS)
+    #undef  KEEP_PEER_CERT
+    #define KEEP_PEER_CERT
+#endif
+
+
+/* stream ciphers except arc4 need 32bit alignment, intel ok without */
+#ifndef XSTREAM_ALIGN
+    #if defined(__x86_64__) || defined(__ia64__) || defined(__i386__)
+        #define NO_XSTREAM_ALIGN
+    #else
+        #define XSTREAM_ALIGN
+    #endif
+#endif
+
+
+/* FreeScale MMCAU hardware crypto has 4 byte alignment */
+#ifdef FREESCALE_MMCAU
+    #define WOLFSSL_MMCAU_ALIGNMENT 4
+#endif
+
+/* if using hardware crypto and have alignment requirements, specify the
+   requirement here.  The record header of SSL/TLS will prvent easy alignment.
+   This hint tries to help as much as possible.  */
+#ifndef WOLFSSL_GENERAL_ALIGNMENT
+    #ifdef WOLFSSL_AESNI
+        #define WOLFSSL_GENERAL_ALIGNMENT 16
+    #elif defined(XSTREAM_ALIGN)
+        #define WOLFSSL_GENERAL_ALIGNMENT  4
+    #elif defined(FREESCALE_MMCAU)
+        #define WOLFSSL_GENERAL_ALIGNMENT  WOLFSSL_MMCAU_ALIGNMENT
+    #else
+        #define WOLFSSL_GENERAL_ALIGNMENT  0
+    #endif
+#endif
+
+#if defined(WOLFSSL_GENERAL_ALIGNMENT) && (WOLFSSL_GENERAL_ALIGNMENT > 0)
+    #if defined(_MSC_VER)
+        #define XGEN_ALIGN __declspec(align(WOLFSSL_GENERAL_ALIGNMENT))
+    #elif defined(__GNUC__)
+        #define XGEN_ALIGN __attribute__((aligned(WOLFSSL_GENERAL_ALIGNMENT)))
+    #else
+        #define XGEN_ALIGN
+    #endif
+#else
+    #define XGEN_ALIGN
+#endif
+
+#ifdef HAVE_CRL
+    /* not widely supported yet */
+    #undef NO_SKID
+    #define NO_SKID
+#endif
+
+
+#ifdef __INTEL_COMPILER
+    #pragma warning(disable:2259) /* explicit casts to smaller sizes, disable */
+#endif
+
+/* user can specify what curves they want with ECC_USER_CURVES otherwise
+ * all curves are on by default for now */
+#ifndef ECC_USER_CURVES
+    #ifndef HAVE_ALL_CURVES
+        #define HAVE_ALL_CURVES
+    #endif
+#endif
+
+/* if desktop type system and fastmath increase default max bits */
+#ifdef WOLFSSL_X86_64_BUILD
+    #ifdef USE_FAST_MATH
+        #ifndef FP_MAX_BITS
+            #define FP_MAX_BITS 8192
+        #endif
+    #endif
+#endif
+
+/* If using the max strength build, ensure OLD TLS is disabled. */
+#ifdef WOLFSSL_MAX_STRENGTH
+    #undef NO_OLD_TLS
+    #define NO_OLD_TLS
+#endif
+
+/* Place any other flags or defines here */
+
+
+#ifdef __cplusplus
+    }   /* extern "C" */
+#endif
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/sha.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/sha.h
new file mode 100644
index 0000000..80a2c98
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/sha.h
@@ -0,0 +1,87 @@
+/* sha.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_SHA_H
+#define WOLF_CRYPT_SHA_H
+
+#include 
+
+#ifndef NO_SHA
+
+#ifdef HAVE_FIPS
+/* for fips @wc_fips */
+#include 
+#endif
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#ifndef HAVE_FIPS /* avoid redefining structs */
+/* in bytes */
+enum {
+#ifdef STM32F2_HASH
+    SHA_REG_SIZE     =  4,    /* STM32 register size, bytes */
+#endif
+    SHA              =  1,    /* hash type unique */
+    SHA_BLOCK_SIZE   = 64,
+    SHA_DIGEST_SIZE  = 20,
+    SHA_PAD_SIZE     = 56
+};
+
+#ifdef WOLFSSL_PIC32MZ_HASH
+#include "port/pic32/pic32mz-crypt.h"
+#endif
+
+#ifndef WOLFSSL_TI_HASH
+      
+/* Sha digest */
+typedef struct Sha {
+    word32  buffLen;   /* in bytes          */
+    word32  loLen;     /* length in bytes   */
+    word32  hiLen;     /* length in bytes   */
+    word32  buffer[SHA_BLOCK_SIZE  / sizeof(word32)];
+    #ifndef WOLFSSL_PIC32MZ_HASH
+        word32  digest[SHA_DIGEST_SIZE / sizeof(word32)];
+    #else
+        word32  digest[PIC32_HASH_SIZE / sizeof(word32)];
+        pic32mz_desc desc; /* Crypt Engine descripter */
+    #endif
+} Sha;
+
+#else /* WOLFSSL_TI_HASH */
+    #include "wolfssl/wolfcrypt/port/ti/ti-hash.h"
+#endif
+
+#endif /* HAVE_FIPS */
+
+WOLFSSL_API int wc_InitSha(Sha*);
+WOLFSSL_API int wc_ShaUpdate(Sha*, const byte*, word32);
+WOLFSSL_API int wc_ShaFinal(Sha*, byte*);
+WOLFSSL_API int wc_ShaHash(const byte*, word32, byte*);
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* NO_SHA */
+#endif /* WOLF_CRYPT_SHA_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/sha256.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/sha256.h
new file mode 100644
index 0000000..7cf6d86
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/sha256.h
@@ -0,0 +1,85 @@
+/* sha256.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+/* code submitted by raphael.huck@efixo.com */
+
+#ifndef WOLF_CRYPT_SHA256_H
+#define WOLF_CRYPT_SHA256_H
+
+#include 
+
+#ifndef NO_SHA256
+
+#ifdef HAVE_FIPS
+    /* for fips @wc_fips */
+    #include 
+#endif
+
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#ifndef HAVE_FIPS /* avoid redefinition of structs */
+#ifdef WOLFSSL_PIC32MZ_HASH
+    #include "port/pic32/pic32mz-crypt.h"
+#endif
+
+/* in bytes */
+enum {
+    SHA256              =  2,   /* hash type unique */
+    SHA256_BLOCK_SIZE   = 64,
+    SHA256_DIGEST_SIZE  = 32,
+    SHA256_PAD_SIZE     = 56
+};
+
+#ifndef WOLFSSL_TI_HASH
+
+/* Sha256 digest */
+typedef struct Sha256 {
+    word32  buffLen;   /* in bytes          */
+    word32  loLen;     /* length in bytes   */
+    word32  hiLen;     /* length in bytes   */
+    word32  digest[SHA256_DIGEST_SIZE / sizeof(word32)];
+    word32  buffer[SHA256_BLOCK_SIZE  / sizeof(word32)];
+    #ifdef WOLFSSL_PIC32MZ_HASH
+        pic32mz_desc desc ; /* Crypt Engine descripter */
+    #endif
+} Sha256;
+
+#else /* WOLFSSL_TI_HASH */
+    #include "wolfssl/wolfcrypt/port/ti/ti-hash.h"
+#endif
+
+#endif /* HAVE_FIPS */
+
+WOLFSSL_API int wc_InitSha256(Sha256*);
+WOLFSSL_API int wc_Sha256Update(Sha256*, const byte*, word32);
+WOLFSSL_API int wc_Sha256Final(Sha256*, byte*);
+WOLFSSL_API int wc_Sha256Hash(const byte*, word32, byte*);
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* NO_SHA256 */
+#endif /* WOLF_CRYPT_SHA256_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/sha512.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/sha512.h
new file mode 100644
index 0000000..83f07c7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/sha512.h
@@ -0,0 +1,104 @@
+/* sha512.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+#ifndef WOLF_CRYPT_SHA512_H
+#define WOLF_CRYPT_SHA512_H
+
+#include 
+
+#ifdef WOLFSSL_SHA512
+
+/* for fips @wc_fips */
+#ifdef HAVE_FIPS
+    #define CYASSL_SHA512
+    #if defined(WOLFSSL_SHA384)
+        #define CYASSL_SHA384
+    #endif
+    #include 
+#endif
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#ifndef HAVE_FIPS /* avoid redefinition of structs */
+
+/* in bytes */
+enum {
+    SHA512              =   4,   /* hash type unique */
+    SHA512_BLOCK_SIZE   = 128,
+    SHA512_DIGEST_SIZE  =  64,
+    SHA512_PAD_SIZE     = 112
+};
+
+
+/* Sha512 digest */
+typedef struct Sha512 {
+    word32  buffLen;   /* in bytes          */
+    word32  loLen;     /* length in bytes   */
+    word32  hiLen;     /* length in bytes   */
+    word64  digest[SHA512_DIGEST_SIZE / sizeof(word64)];
+    word64  buffer[SHA512_BLOCK_SIZE  / sizeof(word64)];
+} Sha512;
+
+#endif /* HAVE_FIPS */
+
+WOLFSSL_API int wc_InitSha512(Sha512*);
+WOLFSSL_API int wc_Sha512Update(Sha512*, const byte*, word32);
+WOLFSSL_API int wc_Sha512Final(Sha512*, byte*);
+WOLFSSL_API int wc_Sha512Hash(const byte*, word32, byte*);
+
+#if defined(WOLFSSL_SHA384)
+
+#ifndef HAVE_FIPS /* avoid redefinition of structs */
+/* in bytes */
+enum {
+    SHA384              =   5,   /* hash type unique */
+    SHA384_BLOCK_SIZE   = 128,
+    SHA384_DIGEST_SIZE  =  48,
+    SHA384_PAD_SIZE     = 112
+};
+
+
+/* Sha384 digest */
+typedef struct Sha384 {
+    word32  buffLen;   /* in bytes          */
+    word32  loLen;     /* length in bytes   */
+    word32  hiLen;     /* length in bytes   */
+    word64  digest[SHA512_DIGEST_SIZE / sizeof(word64)]; /* for transform 512 */
+    word64  buffer[SHA384_BLOCK_SIZE  / sizeof(word64)];
+} Sha384;
+#endif /* HAVE_FIPS */
+
+WOLFSSL_API int wc_InitSha384(Sha384*);
+WOLFSSL_API int wc_Sha384Update(Sha384*, const byte*, word32);
+WOLFSSL_API int wc_Sha384Final(Sha384*, byte*);
+WOLFSSL_API int wc_Sha384Hash(const byte*, word32, byte*);
+
+#endif /* WOLFSSL_SHA384 */
+
+#ifdef __cplusplus
+    } /* extern "C" */
+#endif
+
+#endif /* WOLFSSL_SHA512 */
+#endif /* WOLF_CRYPT_SHA512_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/tfm.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/tfm.h
new file mode 100644
index 0000000..1b0bbea
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/tfm.h
@@ -0,0 +1,720 @@
+/* tfm.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+/*
+ * Based on public domain TomsFastMath 0.10 by Tom St Denis, tomstdenis@iahu.ca,
+ * http://math.libtomcrypt.com
+ */
+
+
+/**
+ *  Edited by Moisés Guimarães (moises.guimaraes@phoebus.com.br)
+ *  to fit CyaSSL's needs.
+ */
+
+
+#ifndef WOLF_CRYPT_TFM_H
+#define WOLF_CRYPT_TFM_H
+
+#include 
+#ifndef CHAR_BIT
+    #include 
+#endif
+
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#ifndef MIN
+   #define MIN(x,y) ((x)<(y)?(x):(y))
+#endif
+
+#ifndef MAX
+   #define MAX(x,y) ((x)>(y)?(x):(y))
+#endif
+
+
+#ifndef NO_64BIT
+/* autodetect x86-64 and make sure we are using 64-bit digits with x86-64 asm */
+#if defined(__x86_64__)
+   #if defined(TFM_X86) || defined(TFM_SSE2) || defined(TFM_ARM)
+       #error x86-64 detected, x86-32/SSE2/ARM optimizations are not valid!
+   #endif
+   #if !defined(TFM_X86_64) && !defined(TFM_NO_ASM)
+      #define TFM_X86_64
+   #endif
+#endif
+#if defined(TFM_X86_64)
+    #if !defined(FP_64BIT)
+       #define FP_64BIT
+    #endif
+#endif
+/* use 64-bit digit even if not using asm on x86_64 */
+#if defined(__x86_64__) && !defined(FP_64BIT)
+    #define FP_64BIT
+#endif
+/* if intel compiler doesn't provide 128 bit type don't turn on 64bit */
+#if defined(FP_64BIT) && defined(__INTEL_COMPILER) && !defined(HAVE___UINT128_T)
+    #undef FP_64BIT
+    #undef TFM_X86_64
+#endif
+#endif /* NO_64BIT */
+
+/* try to detect x86-32 */
+#if defined(__i386__) && !defined(TFM_SSE2)
+   #if defined(TFM_X86_64) || defined(TFM_ARM)
+       #error x86-32 detected, x86-64/ARM optimizations are not valid!
+   #endif
+   #if !defined(TFM_X86) && !defined(TFM_NO_ASM)
+      #define TFM_X86
+   #endif
+#endif
+
+/* make sure we're 32-bit for x86-32/sse/arm/ppc32 */
+#if (defined(TFM_X86) || defined(TFM_SSE2) || defined(TFM_ARM) || defined(TFM_PPC32)) && defined(FP_64BIT)
+   #warning x86-32, SSE2 and ARM, PPC32 optimizations require 32-bit digits (undefining)
+   #undef FP_64BIT
+#endif
+
+/* multi asms? */
+#ifdef TFM_X86
+   #define TFM_ASM
+#endif
+#ifdef TFM_X86_64
+   #ifdef TFM_ASM
+      #error TFM_ASM already defined!
+   #endif
+   #define TFM_ASM
+#endif
+#ifdef TFM_SSE2
+   #ifdef TFM_ASM
+      #error TFM_ASM already defined!
+   #endif
+   #define TFM_ASM
+#endif
+#ifdef TFM_ARM
+   #ifdef TFM_ASM
+      #error TFM_ASM already defined!
+   #endif
+   #define TFM_ASM
+#endif
+#ifdef TFM_PPC32
+   #ifdef TFM_ASM
+      #error TFM_ASM already defined!
+   #endif
+   #define TFM_ASM
+#endif
+#ifdef TFM_PPC64
+   #ifdef TFM_ASM
+      #error TFM_ASM already defined!
+   #endif
+   #define TFM_ASM
+#endif
+#ifdef TFM_AVR32
+   #ifdef TFM_ASM
+      #error TFM_ASM already defined!
+   #endif
+   #define TFM_ASM
+#endif
+
+/* we want no asm? */
+#ifdef TFM_NO_ASM
+   #undef TFM_X86
+   #undef TFM_X86_64
+   #undef TFM_SSE2
+   #undef TFM_ARM
+   #undef TFM_PPC32
+   #undef TFM_PPC64
+   #undef TFM_AVR32
+   #undef TFM_ASM
+#endif
+
+/* ECC helpers */
+#ifdef TFM_ECC192
+   #ifdef FP_64BIT
+       #define TFM_MUL3
+       #define TFM_SQR3
+   #else
+       #define TFM_MUL6
+       #define TFM_SQR6
+   #endif
+#endif
+
+#ifdef TFM_ECC224
+   #ifdef FP_64BIT
+       #define TFM_MUL4
+       #define TFM_SQR4
+   #else
+       #define TFM_MUL7
+       #define TFM_SQR7
+   #endif
+#endif
+
+#ifdef TFM_ECC256
+   #ifdef FP_64BIT
+       #define TFM_MUL4
+       #define TFM_SQR4
+   #else
+       #define TFM_MUL8
+       #define TFM_SQR8
+   #endif
+#endif
+
+#ifdef TFM_ECC384
+   #ifdef FP_64BIT
+       #define TFM_MUL6
+       #define TFM_SQR6
+   #else
+       #define TFM_MUL12
+       #define TFM_SQR12
+   #endif
+#endif
+
+#ifdef TFM_ECC521
+   #ifdef FP_64BIT
+       #define TFM_MUL9
+       #define TFM_SQR9
+   #else
+       #define TFM_MUL17
+       #define TFM_SQR17
+   #endif
+#endif
+
+
+/* some default configurations.
+ */
+#if defined(FP_64BIT)
+   /* for GCC only on supported platforms */
+   typedef unsigned long long fp_digit;   /* 64bit, 128 uses mode(TI) below */
+   typedef unsigned long      fp_word __attribute__ ((mode(TI)));
+#else
+   #if defined(_MSC_VER) || defined(__BORLANDC__)
+      typedef unsigned __int64   ulong64;
+   #else
+      typedef unsigned long long ulong64;
+   #endif
+
+   #ifndef NO_64BIT
+      typedef unsigned int       fp_digit;
+      typedef ulong64            fp_word;
+      #define FP_32BIT
+   #else
+      /* some procs like coldfire prefer not to place multiply into 64bit type
+         even though it exists */
+      typedef unsigned short     fp_digit;
+      typedef unsigned int       fp_word;
+   #endif
+#endif
+
+/* # of digits this is */
+#define DIGIT_BIT  (int)((CHAR_BIT) * sizeof(fp_digit))
+
+/* Max size of any number in bits.  Basically the largest size you will be
+ * multiplying should be half [or smaller] of FP_MAX_SIZE-four_digit
+ *
+ * It defaults to 4096-bits [allowing multiplications upto 2048x2048 bits ]
+ */
+#ifndef FP_MAX_BITS
+    #define FP_MAX_BITS           4096
+#endif
+#define FP_MAX_SIZE           (FP_MAX_BITS+(8*DIGIT_BIT))
+
+/* will this lib work? */
+#if (CHAR_BIT & 7)
+   #error CHAR_BIT must be a multiple of eight.
+#endif
+#if FP_MAX_BITS % CHAR_BIT
+   #error FP_MAX_BITS must be a multiple of CHAR_BIT
+#endif
+
+#define FP_MASK    (fp_digit)(-1)
+#define FP_SIZE    (FP_MAX_SIZE/DIGIT_BIT)
+
+/* signs */
+#define FP_ZPOS     0
+#define FP_NEG      1
+
+/* return codes */
+#define FP_OKAY     0
+#define FP_VAL      1
+#define FP_MEM      2
+
+/* equalities */
+#define FP_LT        -1   /* less than */
+#define FP_EQ         0   /* equal to */
+#define FP_GT         1   /* greater than */
+
+/* replies */
+#define FP_YES        1   /* yes response */
+#define FP_NO         0   /* no response */
+
+/* a FP type */
+typedef struct {
+    int      used,
+             sign;
+#ifdef ALT_ECC_SIZE
+    int      size;
+#endif
+    fp_digit dp[FP_SIZE];
+} fp_int;
+
+/* externally define this symbol to ignore the default settings, useful for changing the build from the make process */
+#ifndef TFM_ALREADY_SET
+
+/* do we want the large set of small multiplications ?
+   Enable these if you are going to be doing a lot of small (<= 16 digit) multiplications say in ECC
+   Or if you're on a 64-bit machine doing RSA as a 1024-bit integer == 16 digits ;-)
+ */
+/* need to refactor the function */
+/*#define TFM_SMALL_SET */
+
+/* do we want huge code
+   Enable these if you are doing 20, 24, 28, 32, 48, 64 digit multiplications (useful for RSA)
+   Less important on 64-bit machines as 32 digits == 2048 bits
+ */
+#if 0
+#define TFM_MUL3
+#define TFM_MUL4
+#define TFM_MUL6
+#define TFM_MUL7
+#define TFM_MUL8
+#define TFM_MUL9
+#define TFM_MUL12
+#define TFM_MUL17
+#endif
+#ifdef TFM_HUGE_SET
+#define TFM_MUL20
+#define TFM_MUL24
+#define TFM_MUL28
+#define TFM_MUL32
+#if (FP_MAX_BITS >= 6144) && defined(FP_64BIT)
+    #define TFM_MUL48
+#endif
+#if (FP_MAX_BITS >= 8192) && defined(FP_64BIT)
+    #define TFM_MUL64
+#endif
+#endif
+
+#if 0
+#define TFM_SQR3
+#define TFM_SQR4
+#define TFM_SQR6
+#define TFM_SQR7
+#define TFM_SQR8
+#define TFM_SQR9
+#define TFM_SQR12
+#define TFM_SQR17
+#endif
+#ifdef TFM_HUGE_SET
+#define TFM_SQR20
+#define TFM_SQR24
+#define TFM_SQR28
+#define TFM_SQR32
+#define TFM_SQR48
+#define TFM_SQR64
+#endif
+
+/* do we want some overflow checks
+   Not required if you make sure your numbers are within range (e.g. by default a modulus for fp_exptmod() can only be upto 2048 bits long)
+ */
+/* #define TFM_CHECK */
+
+/* Is the target a P4 Prescott
+ */
+/* #define TFM_PRESCOTT */
+
+/* Do we want timing resistant fp_exptmod() ?
+ * This makes it slower but also timing invariant with respect to the exponent 
+ */
+/* #define TFM_TIMING_RESISTANT */
+
+#endif /* TFM_ALREADY_SET */
+
+/* functions */
+
+/* returns a TFM ident string useful for debugging... */
+/*const char *fp_ident(void);*/
+
+/* initialize [or zero] an fp int */
+#ifdef ALT_ECC_SIZE
+    void fp_init(fp_int *a);
+    void fp_zero(fp_int *a);
+#else
+    #define fp_init(a)  (void)XMEMSET((a), 0, sizeof(fp_int))
+    #define fp_zero(a)  fp_init(a)
+#endif
+
+/* zero/even/odd ? */
+#define fp_iszero(a) (((a)->used == 0) ? FP_YES : FP_NO)
+#define fp_iseven(a) (((a)->used > 0 && (((a)->dp[0] & 1) == 0)) ? FP_YES : FP_NO)
+#define fp_isodd(a)  (((a)->used > 0  && (((a)->dp[0] & 1) == 1)) ? FP_YES : FP_NO)
+
+/* set to a small digit */
+void fp_set(fp_int *a, fp_digit b);
+
+/* copy from a to b */
+#ifndef ALT_ECC_SIZE
+    #define fp_copy(a, b)  (void)(((a) != (b)) ? ((void)XMEMCPY((b), (a), sizeof(fp_int))) : (void)0)
+    #define fp_init_copy(a, b) fp_copy(b, a)
+#else
+    void fp_copy(fp_int *a, fp_int *b);
+    void fp_init_copy(fp_int *a, fp_int *b);
+#endif
+
+/* clamp digits */
+#define fp_clamp(a)   { while ((a)->used && (a)->dp[(a)->used-1] == 0) --((a)->used); (a)->sign = (a)->used ? (a)->sign : FP_ZPOS; }
+
+/* negate and absolute */
+#define fp_neg(a, b)  { fp_copy(a, b); (b)->sign ^= 1; fp_clamp(b); }
+#define fp_abs(a, b)  { fp_copy(a, b); (b)->sign  = 0; }
+
+/* right shift x digits */
+void fp_rshd(fp_int *a, int x);
+
+/* right shift x bits */
+void fp_rshb(fp_int *a, int x);
+
+/* left shift x digits */
+void fp_lshd(fp_int *a, int x);
+
+/* signed comparison */
+int fp_cmp(fp_int *a, fp_int *b);
+
+/* unsigned comparison */
+int fp_cmp_mag(fp_int *a, fp_int *b);
+
+/* power of 2 operations */
+void fp_div_2d(fp_int *a, int b, fp_int *c, fp_int *d);
+void fp_mod_2d(fp_int *a, int b, fp_int *c);
+void fp_mul_2d(fp_int *a, int b, fp_int *c);
+void fp_2expt (fp_int *a, int b);
+void fp_mul_2(fp_int *a, fp_int *c);
+void fp_div_2(fp_int *a, fp_int *c);
+
+/* Counts the number of lsbs which are zero before the first zero bit */
+int fp_cnt_lsb(fp_int *a);
+
+/* c = a + b */
+void fp_add(fp_int *a, fp_int *b, fp_int *c);
+
+/* c = a - b */
+void fp_sub(fp_int *a, fp_int *b, fp_int *c);
+
+/* c = a * b */
+void fp_mul(fp_int *a, fp_int *b, fp_int *c);
+
+/* b = a*a  */
+void fp_sqr(fp_int *a, fp_int *b);
+
+/* a/b => cb + d == a */
+int fp_div(fp_int *a, fp_int *b, fp_int *c, fp_int *d);
+
+/* c = a mod b, 0 <= c < b  */
+int fp_mod(fp_int *a, fp_int *b, fp_int *c);
+
+/* compare against a single digit */
+int fp_cmp_d(fp_int *a, fp_digit b);
+
+/* c = a + b */
+void fp_add_d(fp_int *a, fp_digit b, fp_int *c);
+
+/* c = a - b */
+void fp_sub_d(fp_int *a, fp_digit b, fp_int *c);
+
+/* c = a * b */
+void fp_mul_d(fp_int *a, fp_digit b, fp_int *c);
+
+/* a/b => cb + d == a */
+/*int fp_div_d(fp_int *a, fp_digit b, fp_int *c, fp_digit *d);*/
+
+/* c = a mod b, 0 <= c < b  */
+/*int fp_mod_d(fp_int *a, fp_digit b, fp_digit *c);*/
+
+/* ---> number theory <--- */
+/* d = a + b (mod c) */
+/*int fp_addmod(fp_int *a, fp_int *b, fp_int *c, fp_int *d);*/
+
+/* d = a - b (mod c) */
+/*int fp_submod(fp_int *a, fp_int *b, fp_int *c, fp_int *d);*/
+
+/* d = a * b (mod c) */
+int fp_mulmod(fp_int *a, fp_int *b, fp_int *c, fp_int *d);
+
+/* c = a * a (mod b) */
+int fp_sqrmod(fp_int *a, fp_int *b, fp_int *c);
+
+/* c = 1/a (mod b) */
+int fp_invmod(fp_int *a, fp_int *b, fp_int *c);
+
+/* c = (a, b) */
+/*void fp_gcd(fp_int *a, fp_int *b, fp_int *c);*/
+
+/* c = [a, b] */
+/*void fp_lcm(fp_int *a, fp_int *b, fp_int *c);*/
+
+/* setups the montgomery reduction */
+int fp_montgomery_setup(fp_int *a, fp_digit *mp);
+
+/* computes a = B**n mod b without division or multiplication useful for
+ * normalizing numbers in a Montgomery system.
+ */
+void fp_montgomery_calc_normalization(fp_int *a, fp_int *b);
+
+/* computes x/R == x (mod N) via Montgomery Reduction */
+void fp_montgomery_reduce(fp_int *a, fp_int *m, fp_digit mp);
+
+/* d = a**b (mod c) */
+int fp_exptmod(fp_int *a, fp_int *b, fp_int *c, fp_int *d);
+
+/* primality stuff */
+
+/* perform a Miller-Rabin test of a to the base b and store result in "result" */
+/*void fp_prime_miller_rabin (fp_int * a, fp_int * b, int *result);*/
+
+/* 256 trial divisions + 8 Miller-Rabins, returns FP_YES if probable prime  */
+/*int fp_isprime(fp_int *a);*/
+
+/* Primality generation flags */
+/*#define TFM_PRIME_BBS      0x0001 */ /* BBS style prime */
+/*#define TFM_PRIME_SAFE     0x0002 */ /* Safe prime (p-1)/2 == prime */
+/*#define TFM_PRIME_2MSB_OFF 0x0004 */ /* force 2nd MSB to 0 */
+/*#define TFM_PRIME_2MSB_ON  0x0008 */ /* force 2nd MSB to 1 */
+
+/* callback for fp_prime_random, should fill dst with random bytes and return how many read [upto len] */
+/*typedef int tfm_prime_callback(unsigned char *dst, int len, void *dat);*/
+
+/*#define fp_prime_random(a, t, size, bbs, cb, dat) fp_prime_random_ex(a, t, ((size) * 8) + 1, (bbs==1)?TFM_PRIME_BBS:0, cb, dat)*/
+
+/*int fp_prime_random_ex(fp_int *a, int t, int size, int flags, tfm_prime_callback cb, void *dat);*/
+
+/* radix conersions */
+int fp_count_bits(fp_int *a);
+int fp_leading_bit(fp_int *a);
+
+int fp_unsigned_bin_size(fp_int *a);
+void fp_read_unsigned_bin(fp_int *a, unsigned char *b, int c);
+void fp_to_unsigned_bin(fp_int *a, unsigned char *b);
+
+/*int fp_signed_bin_size(fp_int *a);*/
+/*void fp_read_signed_bin(fp_int *a, unsigned char *b, int c);*/
+/*void fp_to_signed_bin(fp_int *a, unsigned char *b);*/
+
+/*int fp_read_radix(fp_int *a, char *str, int radix);*/
+/*int fp_toradix(fp_int *a, char *str, int radix);*/
+/*int fp_toradix_n(fp_int * a, char *str, int radix, int maxlen);*/
+
+
+/* VARIOUS LOW LEVEL STUFFS */
+void s_fp_add(fp_int *a, fp_int *b, fp_int *c);
+void s_fp_sub(fp_int *a, fp_int *b, fp_int *c);
+void fp_reverse(unsigned char *s, int len);
+
+void fp_mul_comba(fp_int *a, fp_int *b, fp_int *c);
+
+#ifdef TFM_SMALL_SET
+void fp_mul_comba_small(fp_int *a, fp_int *b, fp_int *c);
+#endif
+
+#ifdef TFM_MUL3
+void fp_mul_comba3(fp_int *a, fp_int *b, fp_int *c);
+#endif
+#ifdef TFM_MUL4
+void fp_mul_comba4(fp_int *a, fp_int *b, fp_int *c);
+#endif
+#ifdef TFM_MUL6
+void fp_mul_comba6(fp_int *a, fp_int *b, fp_int *c);
+#endif
+#ifdef TFM_MUL7
+void fp_mul_comba7(fp_int *a, fp_int *b, fp_int *c);
+#endif
+#ifdef TFM_MUL8
+void fp_mul_comba8(fp_int *a, fp_int *b, fp_int *c);
+#endif
+#ifdef TFM_MUL9
+void fp_mul_comba9(fp_int *a, fp_int *b, fp_int *c);
+#endif
+#ifdef TFM_MUL12
+void fp_mul_comba12(fp_int *a, fp_int *b, fp_int *c);
+#endif
+#ifdef TFM_MUL17
+void fp_mul_comba17(fp_int *a, fp_int *b, fp_int *c);
+#endif
+
+#ifdef TFM_MUL20
+void fp_mul_comba20(fp_int *a, fp_int *b, fp_int *c);
+#endif
+#ifdef TFM_MUL24
+void fp_mul_comba24(fp_int *a, fp_int *b, fp_int *c);
+#endif
+#ifdef TFM_MUL28
+void fp_mul_comba28(fp_int *a, fp_int *b, fp_int *c);
+#endif
+#ifdef TFM_MUL32
+void fp_mul_comba32(fp_int *a, fp_int *b, fp_int *c);
+#endif
+#ifdef TFM_MUL48
+void fp_mul_comba48(fp_int *a, fp_int *b, fp_int *c);
+#endif
+#ifdef TFM_MUL64
+void fp_mul_comba64(fp_int *a, fp_int *b, fp_int *c);
+#endif
+
+void fp_sqr_comba(fp_int *a, fp_int *b);
+
+#ifdef TFM_SMALL_SET
+void fp_sqr_comba_small(fp_int *a, fp_int *b);
+#endif
+
+#ifdef TFM_SQR3
+void fp_sqr_comba3(fp_int *a, fp_int *b);
+#endif
+#ifdef TFM_SQR4
+void fp_sqr_comba4(fp_int *a, fp_int *b);
+#endif
+#ifdef TFM_SQR6
+void fp_sqr_comba6(fp_int *a, fp_int *b);
+#endif
+#ifdef TFM_SQR7
+void fp_sqr_comba7(fp_int *a, fp_int *b);
+#endif
+#ifdef TFM_SQR8
+void fp_sqr_comba8(fp_int *a, fp_int *b);
+#endif
+#ifdef TFM_SQR9
+void fp_sqr_comba9(fp_int *a, fp_int *b);
+#endif
+#ifdef TFM_SQR12
+void fp_sqr_comba12(fp_int *a, fp_int *b);
+#endif
+#ifdef TFM_SQR17
+void fp_sqr_comba17(fp_int *a, fp_int *b);
+#endif
+
+#ifdef TFM_SQR20
+void fp_sqr_comba20(fp_int *a, fp_int *b);
+#endif
+#ifdef TFM_SQR24
+void fp_sqr_comba24(fp_int *a, fp_int *b);
+#endif
+#ifdef TFM_SQR28
+void fp_sqr_comba28(fp_int *a, fp_int *b);
+#endif
+#ifdef TFM_SQR32
+void fp_sqr_comba32(fp_int *a, fp_int *b);
+#endif
+#ifdef TFM_SQR48
+void fp_sqr_comba48(fp_int *a, fp_int *b);
+#endif
+#ifdef TFM_SQR64
+void fp_sqr_comba64(fp_int *a, fp_int *b);
+#endif
+/*extern const char *fp_s_rmap;*/
+
+
+/**
+ * Used by wolfSSL
+ */
+
+/* Types */
+    typedef fp_digit mp_digit;
+    typedef fp_word  mp_word;
+    typedef fp_int mp_int;
+
+/* Constants */
+    #define MP_LT   FP_LT   /* less than    */
+    #define MP_EQ   FP_EQ   /* equal to     */
+    #define MP_GT   FP_GT   /* greater than */
+    #define MP_VAL  FP_VAL  /* invalid */
+    #define MP_OKAY FP_OKAY /* ok result    */
+    #define MP_NO   FP_NO   /* yes/no result */
+    #define MP_YES  FP_YES  /* yes/no result */
+
+/* Prototypes */
+#define mp_zero(a)  fp_zero(a)
+#define mp_iseven(a)  fp_iseven(a)
+int  mp_init (mp_int * a);
+void mp_clear (mp_int * a);
+int mp_init_multi(mp_int* a, mp_int* b, mp_int* c, mp_int* d, mp_int* e, mp_int* f);
+
+int  mp_add (mp_int * a, mp_int * b, mp_int * c);
+int  mp_sub (mp_int * a, mp_int * b, mp_int * c);
+int  mp_add_d (mp_int * a, mp_digit b, mp_int * c);
+
+int  mp_mul (mp_int * a, mp_int * b, mp_int * c);
+int  mp_mulmod (mp_int * a, mp_int * b, mp_int * c, mp_int * d);
+int  mp_mod(mp_int *a, mp_int *b, mp_int *c);
+int  mp_invmod(mp_int *a, mp_int *b, mp_int *c);
+int  mp_exptmod (mp_int * g, mp_int * x, mp_int * p, mp_int * y);
+
+int  mp_cmp(mp_int *a, mp_int *b);
+int  mp_cmp_d(mp_int *a, mp_digit b);
+
+int  mp_unsigned_bin_size(mp_int * a);
+int  mp_read_unsigned_bin (mp_int * a, const unsigned char *b, int c);
+int  mp_to_unsigned_bin (mp_int * a, unsigned char *b);
+
+int  mp_sub_d(fp_int *a, fp_digit b, fp_int *c);
+int  mp_copy(fp_int* a, fp_int* b);
+int  mp_isodd(mp_int* a);
+int  mp_iszero(mp_int* a);
+int  mp_count_bits(mp_int *a);
+int  mp_leading_bit(mp_int *a);
+int  mp_set_int(fp_int *a, fp_digit b);
+void mp_rshb(mp_int *a, int x);
+
+#ifdef HAVE_ECC
+    int mp_read_radix(mp_int* a, const char* str, int radix);
+    void mp_set(fp_int *a, fp_digit b);
+    int mp_sqr(fp_int *a, fp_int *b);
+    int mp_montgomery_reduce(fp_int *a, fp_int *m, fp_digit mp);
+    int mp_montgomery_setup(fp_int *a, fp_digit *rho);
+    int mp_div_2(fp_int * a, fp_int * b);
+    int mp_init_copy(fp_int * a, fp_int * b);
+#endif
+
+#if defined(HAVE_ECC) || defined(WOLFSSL_KEY_GEN)
+    int mp_sqrmod(mp_int* a, mp_int* b, mp_int* c);
+    int mp_montgomery_calc_normalization(mp_int *a, mp_int *b);
+#endif
+
+#ifdef WOLFSSL_KEY_GEN
+int  mp_gcd(fp_int *a, fp_int *b, fp_int *c);
+int  mp_lcm(fp_int *a, fp_int *b, fp_int *c);
+int  mp_prime_is_prime(mp_int* a, int t, int* result);
+#endif /* WOLFSSL_KEY_GEN */
+
+int  mp_cnt_lsb(fp_int *a);
+int  mp_div_2d(fp_int *a, int b, fp_int *c, fp_int *d);
+int  mp_mod_d(fp_int* a, fp_digit b, fp_digit* c);
+
+WOLFSSL_API word32 CheckRunTimeFastMath(void);
+
+/* If user uses RSA, DH, DSA, or ECC math lib directly then fast math FP_SIZE
+   must match, return 1 if a match otherwise 0 */
+#define CheckFastMathSettings() (FP_SIZE == CheckRunTimeFastMath())
+#ifdef __cplusplus
+   }
+#endif
+
+#endif  /* WOLF_CRYPT_TFM_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/types.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/types.h
new file mode 100644
index 0000000..a5ff1d3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/types.h
@@ -0,0 +1,322 @@
+/* types.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifndef WOLF_CRYPT_TYPES_H
+#define WOLF_CRYPT_TYPES_H
+
+	#include 
+	#include 
+
+	#ifdef __cplusplus
+	    extern "C" {
+	#endif
+
+
+	#if defined(WORDS_BIGENDIAN)
+	    #define BIG_ENDIAN_ORDER
+	#endif
+
+	#ifndef BIG_ENDIAN_ORDER
+	    #define LITTLE_ENDIAN_ORDER
+	#endif
+
+	#ifndef WOLFSSL_TYPES
+	    #ifndef byte
+	        typedef unsigned char  byte;
+	    #endif
+	    typedef unsigned short word16;
+	    typedef unsigned int   word32;
+	#endif
+
+
+	/* try to set SIZEOF_LONG or LONG_LONG if user didn't */
+	#if !defined(_MSC_VER) && !defined(__BCPLUSPLUS__)
+	    #if !defined(SIZEOF_LONG_LONG) && !defined(SIZEOF_LONG)
+	        #if (defined(__alpha__) || defined(__ia64__) || defined(_ARCH_PPC64) \
+	                || defined(__mips64)  || defined(__x86_64__))
+	            /* long should be 64bit */
+	            #define SIZEOF_LONG 8
+	        #elif defined(__i386__) || defined(__CORTEX_M3__)
+	            /* long long should be 64bit */
+	            #define SIZEOF_LONG_LONG 8
+	        #endif
+	    #endif
+	#endif
+
+
+	#if defined(_MSC_VER) || defined(__BCPLUSPLUS__)
+	    #define WORD64_AVAILABLE
+	    #define W64LIT(x) x##ui64
+	    typedef unsigned __int64 word64;
+	#elif defined(SIZEOF_LONG) && SIZEOF_LONG == 8
+	    #define WORD64_AVAILABLE
+	    #define W64LIT(x) x##LL
+	    typedef unsigned long word64;
+	#elif defined(SIZEOF_LONG_LONG) && SIZEOF_LONG_LONG == 8
+	    #define WORD64_AVAILABLE
+	    #define W64LIT(x) x##LL
+	    typedef unsigned long long word64;
+	#elif defined(__SIZEOF_LONG_LONG__) && __SIZEOF_LONG_LONG__ == 8
+	    #define WORD64_AVAILABLE
+	    #define W64LIT(x) x##LL
+	    typedef unsigned long long word64;
+	#else
+	    #define MP_16BIT  /* for mp_int, mp_word needs to be twice as big as
+	                         mp_digit, no 64 bit type so make mp_digit 16 bit */
+	#endif
+
+
+	/* These platforms have 64-bit CPU registers.  */
+	#if (defined(__alpha__) || defined(__ia64__) || defined(_ARCH_PPC64) || \
+	     defined(__mips64)  || defined(__x86_64__) || defined(_M_X64))
+	    typedef word64 wolfssl_word;
+	#else
+	    typedef word32 wolfssl_word;
+	    #ifdef WORD64_AVAILABLE
+	        #define WOLFCRYPT_SLOW_WORD64
+	    #endif
+	#endif
+
+
+	enum {
+	    WOLFSSL_WORD_SIZE  = sizeof(wolfssl_word),
+	    WOLFSSL_BIT_SIZE   = 8,
+	    WOLFSSL_WORD_BITS  = WOLFSSL_WORD_SIZE * WOLFSSL_BIT_SIZE
+	};
+
+	#define WOLFSSL_MAX_16BIT 0xffffU
+
+	/* use inlining if compiler allows */
+	#ifndef INLINE
+	#ifndef NO_INLINE
+	    #ifdef _MSC_VER
+	        #define INLINE __inline
+	    #elif defined(__GNUC__)
+	        #define INLINE inline
+	    #elif defined(__IAR_SYSTEMS_ICC__)
+	        #define INLINE inline
+	    #elif defined(THREADX)
+	        #define INLINE _Inline
+	    #else
+	        #define INLINE
+	    #endif
+	#else
+	    #define INLINE
+	#endif
+	#endif
+
+
+	/* set up rotate style */
+	#if defined(_MSC_VER) || defined(__BCPLUSPLUS__)
+	    #define INTEL_INTRINSICS
+	    #define FAST_ROTATE
+	#elif defined(__MWERKS__) && TARGET_CPU_PPC
+	    #define PPC_INTRINSICS
+	    #define FAST_ROTATE
+	#elif defined(__GNUC__) && defined(__i386__)
+	        /* GCC does peephole optimizations which should result in using rotate
+	           instructions  */
+	    #define FAST_ROTATE
+	#endif
+
+
+	/* set up thread local storage if available */
+	#ifdef HAVE_THREAD_LS
+	    #if defined(_MSC_VER)
+	        #define THREAD_LS_T __declspec(thread)
+	    #else
+	        #define THREAD_LS_T __thread
+	    #endif
+	#else
+	    #define THREAD_LS_T
+	#endif
+
+
+	/* Micrium will use Visual Studio for compilation but not the Win32 API */
+	#if defined(_WIN32) && !defined(MICRIUM) && !defined(FREERTOS) \
+	        && !defined(EBSNET)
+	    #define USE_WINDOWS_API
+	#endif
+
+
+	/* idea to add global alloc override by Moisés Guimarães  */
+	/* default to libc stuff */
+	/* XREALLOC is used once in normal math lib, not in fast math lib */
+	/* XFREE on some embeded systems doesn't like free(0) so test  */
+	#if defined(XMALLOC_USER)
+	    /* prototypes for user heap override functions */
+	    #include   /* for size_t */
+	    extern void *XMALLOC(size_t n, void* heap, int type);
+	    extern void *XREALLOC(void *p, size_t n, void* heap, int type);
+	    extern void XFREE(void *p, void* heap, int type);
+	#elif defined(NO_WOLFSSL_MEMORY)
+	    /* just use plain C stdlib stuff if desired */
+	    #include 
+	    #define XMALLOC(s, h, t)     ((void)h, (void)t, malloc((s)))
+	    #define XFREE(p, h, t)       {void* xp = (p); if((xp)) free((xp));}
+	    #define XREALLOC(p, n, h, t) realloc((p), (n))
+	#elif !defined(MICRIUM_MALLOC) && !defined(EBSNET) \
+	        && !defined(WOLFSSL_SAFERTOS) && !defined(FREESCALE_MQX) \
+	        && !defined(WOLFSSL_LEANPSK)
+	    /* default C runtime, can install different routines at runtime via cbs */
+	    #include 
+	    #define XMALLOC(s, h, t)     ((void)h, (void)t, wolfSSL_Malloc((s)))
+	    #define XFREE(p, h, t)       {void* xp = (p); if((xp)) wolfSSL_Free((xp));}
+	    #define XREALLOC(p, n, h, t) wolfSSL_Realloc((p), (n))
+	#endif
+
+	#ifndef STRING_USER
+	    #include 
+	    char* mystrnstr(const char* s1, const char* s2, unsigned int n);
+
+	    #define XMEMCPY(d,s,l)    memcpy((d),(s),(l))
+	    #define XMEMSET(b,c,l)    memset((b),(c),(l))
+	    #define XMEMCMP(s1,s2,n)  memcmp((s1),(s2),(n))
+	    #define XMEMMOVE(d,s,l)   memmove((d),(s),(l))
+
+	    #define XSTRLEN(s1)       strlen((s1))
+	    #define XSTRNCPY(s1,s2,n) strncpy((s1),(s2),(n))
+	    /* strstr, strncmp, and strncat only used by wolfSSL proper, not required for
+	       CTaoCrypt only */
+	    #define XSTRSTR(s1,s2)    strstr((s1),(s2))
+	    #define XSTRNSTR(s1,s2,n) mystrnstr((s1),(s2),(n))
+	    #define XSTRNCMP(s1,s2,n) strncmp((s1),(s2),(n))
+	    #define XSTRNCAT(s1,s2,n) strncat((s1),(s2),(n))
+	    #ifndef USE_WINDOWS_API
+	        #define XSTRNCASECMP(s1,s2,n) strncasecmp((s1),(s2),(n))
+	        #define XSNPRINTF snprintf
+	    #else
+	        #define XSTRNCASECMP(s1,s2,n) _strnicmp((s1),(s2),(n))
+	        #define XSNPRINTF _snprintf
+	    #endif
+	#endif
+
+	#ifndef CTYPE_USER
+	    #include 
+	    #if defined(HAVE_ECC) || defined(HAVE_OCSP)
+	        #define XTOUPPER(c)     toupper((c))
+	        #define XISALPHA(c)     isalpha((c))
+	    #endif
+	    /* needed by wolfSSL_check_domain_name() */
+	    #define XTOLOWER(c)      tolower((c))
+	#endif
+
+
+	/* memory allocation types for user hints */
+	enum {
+	    DYNAMIC_TYPE_CA           = 1,
+	    DYNAMIC_TYPE_CERT         = 2,
+	    DYNAMIC_TYPE_KEY          = 3,
+	    DYNAMIC_TYPE_FILE         = 4,
+	    DYNAMIC_TYPE_SUBJECT_CN   = 5,
+	    DYNAMIC_TYPE_PUBLIC_KEY   = 6,
+	    DYNAMIC_TYPE_SIGNER       = 7,
+	    DYNAMIC_TYPE_NONE         = 8,
+	    DYNAMIC_TYPE_BIGINT       = 9,
+	    DYNAMIC_TYPE_RSA          = 10,
+	    DYNAMIC_TYPE_METHOD       = 11,
+	    DYNAMIC_TYPE_OUT_BUFFER   = 12,
+	    DYNAMIC_TYPE_IN_BUFFER    = 13,
+	    DYNAMIC_TYPE_INFO         = 14,
+	    DYNAMIC_TYPE_DH           = 15,
+	    DYNAMIC_TYPE_DOMAIN       = 16,
+	    DYNAMIC_TYPE_SSL          = 17,
+	    DYNAMIC_TYPE_CTX          = 18,
+	    DYNAMIC_TYPE_WRITEV       = 19,
+	    DYNAMIC_TYPE_OPENSSL      = 20,
+	    DYNAMIC_TYPE_DSA          = 21,
+	    DYNAMIC_TYPE_CRL          = 22,
+	    DYNAMIC_TYPE_REVOKED      = 23,
+	    DYNAMIC_TYPE_CRL_ENTRY    = 24,
+	    DYNAMIC_TYPE_CERT_MANAGER = 25,
+	    DYNAMIC_TYPE_CRL_MONITOR  = 26,
+	    DYNAMIC_TYPE_OCSP_STATUS  = 27,
+	    DYNAMIC_TYPE_OCSP_ENTRY   = 28,
+	    DYNAMIC_TYPE_ALTNAME      = 29,
+	    DYNAMIC_TYPE_SUITES       = 30,
+	    DYNAMIC_TYPE_CIPHER       = 31,
+	    DYNAMIC_TYPE_RNG          = 32,
+	    DYNAMIC_TYPE_ARRAYS       = 33,
+	    DYNAMIC_TYPE_DTLS_POOL    = 34,
+	    DYNAMIC_TYPE_SOCKADDR     = 35,
+	    DYNAMIC_TYPE_LIBZ         = 36,
+	    DYNAMIC_TYPE_ECC          = 37,
+	    DYNAMIC_TYPE_TMP_BUFFER   = 38,
+	    DYNAMIC_TYPE_DTLS_MSG     = 39,
+	    DYNAMIC_TYPE_CAVIUM_TMP   = 40,
+	    DYNAMIC_TYPE_CAVIUM_RSA   = 41,
+	    DYNAMIC_TYPE_X509         = 42,
+	    DYNAMIC_TYPE_TLSX         = 43,
+	    DYNAMIC_TYPE_OCSP         = 44,
+	    DYNAMIC_TYPE_SIGNATURE    = 45,
+	    DYNAMIC_TYPE_HASHES       = 46
+	};
+
+	/* max error buffer string size */
+	enum {
+	    WOLFSSL_MAX_ERROR_SZ = 80
+	};
+
+	/* stack protection */
+	enum {
+	    MIN_STACK_BUFFER = 8
+	};
+
+
+
+	/* settings detection for compile vs runtime math incombatibilities */
+	enum {
+	#if !defined(USE_FAST_MATH) && !defined(SIZEOF_LONG) && !defined(SIZEOF_LONG_LONG)
+	    CTC_SETTINGS = 0x0
+	#elif !defined(USE_FAST_MATH) && defined(SIZEOF_LONG) && (SIZEOF_LONG == 8)
+	    CTC_SETTINGS = 0x1
+	#elif !defined(USE_FAST_MATH) && defined(SIZEOF_LONG_LONG) && (SIZEOF_LONG_LONG == 8)
+	    CTC_SETTINGS = 0x2
+	#elif !defined(USE_FAST_MATH) && defined(SIZEOF_LONG_LONG) && (SIZEOF_LONG_LONG == 4)
+	    CTC_SETTINGS = 0x4
+	#elif defined(USE_FAST_MATH) && !defined(SIZEOF_LONG) && !defined(SIZEOF_LONG_LONG)
+	    CTC_SETTINGS = 0x8
+	#elif defined(USE_FAST_MATH) && defined(SIZEOF_LONG) && (SIZEOF_LONG == 8)
+	    CTC_SETTINGS = 0x10
+	#elif defined(USE_FAST_MATH) && defined(SIZEOF_LONG_LONG) && (SIZEOF_LONG_LONG == 8)
+	    CTC_SETTINGS = 0x20
+	#elif defined(USE_FAST_MATH) && defined(SIZEOF_LONG_LONG) && (SIZEOF_LONG_LONG == 4)
+	    CTC_SETTINGS = 0x40
+	#else
+	    #error "bad math long / long long settings"
+	#endif
+	};
+
+
+	WOLFSSL_API word32 CheckRunTimeSettings(void);
+
+	/* If user uses RSA, DH, DSA, or ECC math lib directly then fast math and long
+	   types need to match at compile time and run time, CheckCtcSettings will
+	   return 1 if a match otherwise 0 */
+	#define CheckCtcSettings() (CTC_SETTINGS == CheckRunTimeSettings())
+
+
+	#ifdef __cplusplus
+	    }   /* extern "C" */
+	#endif
+
+#endif /* WOLF_CRYPT_TYPES_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/visibility.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/visibility.h
new file mode 100644
index 0000000..6e41d23
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/visibility.h
@@ -0,0 +1,75 @@
+/* visibility.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+/* Visibility control macros */
+
+#ifndef WOLF_CRYPT_VISIBILITY_H
+#define WOLF_CRYPT_VISIBILITY_H
+
+
+/* for compatibility and so that fips is using same name of macro @wc_fips */
+#ifdef HAVE_FIPS
+    #include 
+    #define WOLFSSL_API   CYASSL_API
+	#define WOLFSSL_LOCAL CYASSL_LOCAL
+#else
+
+/* WOLFSSL_API is used for the public API symbols.
+        It either imports or exports (or does nothing for static builds)
+
+   WOLFSSL_LOCAL is used for non-API symbols (private).
+*/
+
+#if defined(BUILDING_WOLFSSL)
+    #if defined(HAVE_VISIBILITY) && HAVE_VISIBILITY
+        #define WOLFSSL_API   __attribute__ ((visibility("default")))
+        #define WOLFSSL_LOCAL __attribute__ ((visibility("hidden")))
+    #elif defined(__SUNPRO_C) && (__SUNPRO_C >= 0x550)
+        #define WOLFSSL_API   __global
+        #define WOLFSSL_LOCAL __hidden
+    #elif defined(_MSC_VER)
+        #ifdef WOLFSSL_DLL
+            #define WOLFSSL_API __declspec(dllexport)
+        #else
+            #define WOLFSSL_API
+        #endif
+        #define WOLFSSL_LOCAL
+    #else
+        #define WOLFSSL_API
+        #define WOLFSSL_LOCAL
+    #endif /* HAVE_VISIBILITY */
+#else /* BUILDING_WOLFSSL */
+    #if defined(_MSC_VER)
+        #ifdef WOLFSSL_DLL
+            #define WOLFSSL_API __declspec(dllimport)
+        #else
+            #define WOLFSSL_API
+        #endif
+        #define WOLFSSL_LOCAL
+    #else
+        #define WOLFSSL_API
+        #define WOLFSSL_LOCAL
+    #endif
+#endif /* BUILDING_WOLFSSL */
+
+#endif /* HAVE_FIPS */
+#endif /* WOLF_CRYPT_VISIBILITY_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/wc_port.h b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/wc_port.h
new file mode 100644
index 0000000..c13f394
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/Source/WolfSSL/wolfssl/wolfcrypt/wc_port.h
@@ -0,0 +1,207 @@
+/* wc_port.h
+ *
+ * Copyright (C) 2006-2015 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL. (formerly known as CyaSSL)
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ */
+
+
+#ifndef WOLF_CRYPT_PORT_H
+#define WOLF_CRYPT_PORT_H
+
+#include 
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+
+#ifdef USE_WINDOWS_API
+    #ifdef WOLFSSL_GAME_BUILD
+        #include "system/xtl.h"
+    #else
+        #ifndef WIN32_LEAN_AND_MEAN
+            #define WIN32_LEAN_AND_MEAN
+        #endif
+        #if defined(_WIN32_WCE) || defined(WIN32_LEAN_AND_MEAN)
+            /* On WinCE winsock2.h must be included before windows.h */
+            #include 
+        #endif
+        #include 
+    #endif
+#elif defined(THREADX)
+    #ifndef SINGLE_THREADED
+        #include "tx_api.h"
+    #endif
+#elif defined(MICRIUM)
+    /* do nothing, just don't pick Unix */
+#elif defined(FREERTOS) || defined(WOLFSSL_SAFERTOS)
+    /* do nothing */
+#elif defined(EBSNET)
+    /* do nothing */
+#elif defined(FREESCALE_MQX)
+    /* do nothing */
+#elif defined(WOLFSSL_MDK_ARM)
+    #if defined(WOLFSSL_MDK5)
+         #include "cmsis_os.h"
+    #else
+        #include 
+    #endif
+#elif defined(WOLFSSL_CMSIS_RTOS)
+    #include "cmsis_os.h"
+#elif defined(WOLFSSL_TIRTOS)
+    #include 
+    #include 
+#else
+    #ifndef SINGLE_THREADED
+        #define WOLFSSL_PTHREADS
+        #include 
+    #endif
+    #if defined(OPENSSL_EXTRA) || defined(GOAHEAD_WS)
+        #include       /* for close of BIO */
+    #endif
+#endif
+
+
+#ifdef SINGLE_THREADED
+    typedef int wolfSSL_Mutex;
+#else /* MULTI_THREADED */
+    /* FREERTOS comes first to enable use of FreeRTOS Windows simulator only */
+    #ifdef FREERTOS
+        typedef xSemaphoreHandle wolfSSL_Mutex;
+    #elif defined(WOLFSSL_SAFERTOS)
+        typedef struct wolfSSL_Mutex {
+            signed char mutexBuffer[portQUEUE_OVERHEAD_BYTES];
+            xSemaphoreHandle mutex;
+        } wolfSSL_Mutex;
+    #elif defined(USE_WINDOWS_API)
+        typedef CRITICAL_SECTION wolfSSL_Mutex;
+    #elif defined(WOLFSSL_PTHREADS)
+        typedef pthread_mutex_t wolfSSL_Mutex;
+    #elif defined(THREADX)
+        typedef TX_MUTEX wolfSSL_Mutex;
+    #elif defined(MICRIUM)
+        typedef OS_MUTEX wolfSSL_Mutex;
+    #elif defined(EBSNET)
+        typedef RTP_MUTEX wolfSSL_Mutex;
+    #elif defined(FREESCALE_MQX)
+        typedef MUTEX_STRUCT wolfSSL_Mutex;
+    #elif defined(WOLFSSL_MDK_ARM)
+        #if defined(WOLFSSL_CMSIS_RTOS)
+            typedef osMutexId wolfSSL_Mutex;
+        #else
+            typedef OS_MUT wolfSSL_Mutex;
+        #endif
+    #elif defined(WOLFSSL_CMSIS_RTOS)
+        typedef osMutexId wolfSSL_Mutex;
+    #elif defined(WOLFSSL_TIRTOS)
+        typedef ti_sysbios_knl_Semaphore_Handle wolfSSL_Mutex;
+    #else
+        #error Need a mutex type in multithreaded mode
+    #endif /* USE_WINDOWS_API */
+#endif /* SINGLE_THREADED */
+
+WOLFSSL_LOCAL int InitMutex(wolfSSL_Mutex*);
+WOLFSSL_LOCAL int FreeMutex(wolfSSL_Mutex*);
+WOLFSSL_LOCAL int LockMutex(wolfSSL_Mutex*);
+WOLFSSL_LOCAL int UnLockMutex(wolfSSL_Mutex*);
+
+
+/* filesystem abstraction layer, used by ssl.c */
+#ifndef NO_FILESYSTEM
+
+#if defined(EBSNET)
+    #define XFILE                    int
+    #define XFOPEN(NAME, MODE)       vf_open((const char *)NAME, VO_RDONLY, 0);
+    #define XFSEEK                   vf_lseek
+    #define XFTELL                   vf_tell
+    #define XREWIND                  vf_rewind
+    #define XFREAD(BUF, SZ, AMT, FD) vf_read(FD, BUF, SZ*AMT)
+    #define XFWRITE(BUF, SZ, AMT, FD) vf_write(FD, BUF, SZ*AMT)
+    #define XFCLOSE                  vf_close
+    #define XSEEK_END                VSEEK_END
+    #define XBADFILE                 -1
+#elif defined(LSR_FS)
+    #include 
+    #define XFILE                   struct fs_file*
+    #define XFOPEN(NAME, MODE)      fs_open((char*)NAME);
+    #define XFSEEK(F, O, W)         (void)F
+    #define XFTELL(F)               (F)->len
+    #define XREWIND(F)              (void)F
+    #define XFREAD(BUF, SZ, AMT, F) fs_read(F, (char*)BUF, SZ*AMT)
+    #define XFWRITE(BUF, SZ, AMT, F) fs_write(F, (char*)BUF, SZ*AMT)
+    #define XFCLOSE                 fs_close
+    #define XSEEK_END               0
+    #define XBADFILE                NULL
+#elif defined(FREESCALE_MQX)
+    #define XFILE                   MQX_FILE_PTR
+    #define XFOPEN                  fopen
+    #define XFSEEK                  fseek
+    #define XFTELL                  ftell
+    #define XREWIND(F)              fseek(F, 0, IO_SEEK_SET)
+    #define XFREAD                  fread
+    #define XFWRITE                 fwrite
+    #define XFCLOSE                 fclose
+    #define XSEEK_END               IO_SEEK_END
+    #define XBADFILE                NULL
+#elif defined(MICRIUM)
+    #include 
+    #define XFILE      FS_FILE*
+    #define XFOPEN     fs_fopen
+    #define XFSEEK     fs_fseek
+    #define XFTELL     fs_ftell
+    #define XREWIND    fs_rewind
+    #define XFREAD     fs_fread
+    #define XFWRITE    fs_fwrite
+    #define XFCLOSE    fs_fclose
+    #define XSEEK_END  FS_SEEK_END
+    #define XBADFILE   NULL
+#else
+    /* stdio, default case */
+    #define XFILE      FILE*
+    #if defined(WOLFSSL_MDK_ARM)
+        #include 
+        extern FILE * wolfSSL_fopen(const char *name, const char *mode) ;
+        #define XFOPEN     wolfSSL_fopen
+    #else
+        #define XFOPEN     fopen
+    #endif
+    #define XFSEEK     fseek
+    #define XFTELL     ftell
+    #define XREWIND    rewind
+    #define XFREAD     fread
+    #define XFWRITE    fwrite
+    #define XFCLOSE    fclose
+    #define XSEEK_END  SEEK_END
+    #define XBADFILE   NULL
+#endif
+
+#endif /* NO_FILESYSTEM */
+
+
+/* Windows API defines its own min() macro. */
+#if defined(USE_WINDOWS_API) && defined(min)
+    #define WOLFSSL_HAVE_MIN
+#endif
+
+
+#ifdef __cplusplus
+    }  /* extern "C" */
+#endif
+
+#endif /* WOLF_CRYPT_PORT_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS-Plus/readme.txt b/FreeRTOSv10.2.1/FreeRTOS-Plus/readme.txt
new file mode 100644
index 0000000..9854164
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS-Plus/readme.txt
@@ -0,0 +1,13 @@
+Directories:
+
++ The FreeRTOS-Plus/Source directory contains source code for some of the
+  FreeRTOS+ components.  These subdirectories contain further readme files and
+  links to documentation.
+
++ The FreeRTOS-Plus/Demo directory contains a demo application for every most of
+  the FreeRTOS+ components.  Lots of the demo applications use the FreeRTOS
+  Windows simulator for easy evaluation.  Be aware that FreeRTOS is much slower
+  and not deterministic when executed in a simulated environment.
+
++ See http://www.freertos.org/plus
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ARMv8M/mpu_demo/mpu_demo.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ARMv8M/mpu_demo/mpu_demo.c
new file mode 100644
index 0000000..6dea6db
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ARMv8M/mpu_demo/mpu_demo.c
@@ -0,0 +1,226 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/**
+ * @brief Size of the shared memory region.
+ */
+#define SHARED_MEMORY_SIZE 32
+
+/**
+ * @brief Memory region shared between two tasks.
+ */
+static uint8_t ucSharedMemory[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( 32 ) ) );
+
+/**
+ * @brief Memory region used to track Memory Fault intentionally caused by the
+ * RO Access task.
+ *
+ * RO Access task sets ucROTaskFaultTracker[ 0 ] to 1 before accessing illegal
+ * memory. Illegal memory access causes Memory Fault and the fault handler
+ * checks ucROTaskFaultTracker[ 0 ] to see if this is an expected fault. We
+ * recover gracefully from an expected fault by jumping to the next instruction.
+ *
+ * @note We are declaring a region of 32 bytes even though we need only one. The
+ * reason is that the size of an MPU region must be a multiple of 32 bytes.
+ */
+static uint8_t ucROTaskFaultTracker[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( 32 ) ) ) = { 0 };
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Implements the task which has Read Only access to the memory region
+ * ucSharedMemory.
+ *
+ * @param pvParameters[in] Parameters as passed during task creation.
+ */
+static void prvROAccessTask( void * pvParameters );
+
+/**
+ * @brief Implements the task which has Read Write access to the memory region
+ * ucSharedMemory.
+ *
+ * @param pvParameters[in] Parameters as passed during task creation.
+ */
+static void prvRWAccessTask( void * pvParameters );
+
+/*-----------------------------------------------------------*/
+
+static void prvROAccessTask( void * pvParameters )
+{
+uint8_t ucVal;
+
+	/* Unused parameters. */
+	( void ) pvParameters;
+
+	for( ; ; )
+	{
+		/* This task has RO access to ucSharedMemory and therefore it can read
+		 * it but cannot modify it. */
+		ucVal = ucSharedMemory[ 0 ];
+
+		/* Silent compiler warnings about unused variables. */
+		( void ) ucVal;
+
+		/* Since this task has Read Only access to the ucSharedMemory region,
+		 * writing to it results in Memory Fault. Set ucROTaskFaultTracker[ 0 ]
+		 * to 1 to tell the Memory Fault Handler that this is an expected fault.
+		 * The handler will recover from this fault gracefully by jumping to the
+		 * next instruction. */
+		ucROTaskFaultTracker[ 0 ] = 1;
+
+		/* Illegal access to generate Memory Fault. */
+		ucSharedMemory[ 0 ] = 0;
+
+		/* Wait for a second. */
+		vTaskDelay( pdMS_TO_TICKS( 1000 ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvRWAccessTask( void * pvParameters )
+{
+	/* Unused parameters. */
+	( void ) pvParameters;
+
+	for( ; ; )
+	{
+		/* This task has RW access to ucSharedMemory and therefore can write to
+		 * it. */
+		ucSharedMemory[ 0 ] = 0;
+
+		/* Wait for a second. */
+		vTaskDelay( pdMS_TO_TICKS( 1000 ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vStartMPUDemo( void )
+{
+static StackType_t xROAccessTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );
+static StackType_t xRWAccessTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );
+TaskParameters_t xROAccessTaskParameters =
+{
+	.pvTaskCode		= prvROAccessTask,
+	.pcName			= "ROAccess",
+	.usStackDepth	= configMINIMAL_STACK_SIZE,
+	.pvParameters	= NULL,
+	.uxPriority		= tskIDLE_PRIORITY,
+	.puxStackBuffer	= xROAccessTaskStack,
+	.xRegions		=	{
+							{ ucSharedMemory,		32,	tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER	},
+							{ ucROTaskFaultTracker,	32,	tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER	},
+							{ 0,					0,	0														},
+						}
+};
+TaskParameters_t xRWAccessTaskParameters =
+{
+	.pvTaskCode		= prvRWAccessTask,
+	.pcName			= "RWAccess",
+	.usStackDepth	= configMINIMAL_STACK_SIZE,
+	.pvParameters	= NULL,
+	.uxPriority		= tskIDLE_PRIORITY,
+	.puxStackBuffer	= xRWAccessTaskStack,
+	.xRegions		=	{
+							{ ucSharedMemory,	32,	tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER	},
+							{ 0,				0,	0														},
+							{ 0,				0,	0														},
+						}
+};
+
+	/* Create an unprivileged task with RO access to ucSharedMemory. */
+	xTaskCreateRestricted( &( xROAccessTaskParameters ), NULL );
+
+	/* Create an unprivileged task with RW access to ucSharedMemory. */
+	xTaskCreateRestricted( &( xRWAccessTaskParameters ), NULL );
+}
+/*-----------------------------------------------------------*/
+
+portDONT_DISCARD void vHandleMemoryFault( uint32_t * pulFaultStackAddress )
+{
+uint32_t ulPC;
+uint16_t usOffendingInstruction;
+
+	/* Is this an expected fault? */
+	if( ucROTaskFaultTracker[ 0 ] == 1 )
+	{
+		/* Read program counter. */
+		ulPC = pulFaultStackAddress[ 6 ];
+
+		/* Read the offending instruction. */
+		usOffendingInstruction = *( uint16_t * )ulPC;
+
+		/* From ARM docs:
+		 * If the value of bits[15:11] of the halfword being decoded is one of
+		 * the following, the halfword is the first halfword of a 32-bit
+		 * instruction:
+		 * - 0b11101.
+		 * - 0b11110.
+		 * - 0b11111.
+		 * Otherwise, the halfword is a 16-bit instruction.
+		 */
+
+		/* Extract bits[15:11] of the offending instruction. */
+		usOffendingInstruction = usOffendingInstruction & 0xF800;
+		usOffendingInstruction = ( usOffendingInstruction >> 11 );
+
+		/* Determine if the offending instruction is a 32-bit instruction or
+		 * a 16-bit instruction. */
+		if( usOffendingInstruction == 0x001F ||
+			usOffendingInstruction == 0x001E ||
+			usOffendingInstruction == 0x001D )
+		{
+			/* Since the offending instruction is a 32-bit instruction,
+			 * increment the program counter by 4 to move to the next
+			 * instruction. */
+			ulPC += 4;
+		}
+		else
+		{
+			/* Since the offending instruction is a 16-bit instruction,
+			 * increment the program counter by 2 to move to the next
+			 * instruction. */
+			ulPC += 2;
+		}
+
+		/* Save the new program counter on the stack. */
+		pulFaultStackAddress[ 6 ] = ulPC;
+
+		/* Mark the fault as handled. */
+		ucROTaskFaultTracker[ 0 ] = 0;
+	}
+	else
+	{
+		/* This is an unexpected fault - loop forever. */
+		for( ; ; )
+		{
+		}
+	}
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ARMv8M/mpu_demo/mpu_demo.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ARMv8M/mpu_demo/mpu_demo.h
new file mode 100644
index 0000000..e624027
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ARMv8M/mpu_demo/mpu_demo.h
@@ -0,0 +1,45 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __MPU_DEMO_H__
+#define __MPU_DEMO_H__
+
+/**
+ * @brief Creates all the tasks for MPU demo.
+ *
+ * The MPU demo creates 2 unprivileged tasks - One of which has Read Only access
+ * to a shared memory region while the other has Read Write access. The task
+ * with Read Only access then tries to write to the shared memory which results
+ * in a Memory fault. The fault handler examines that it is the fault generated
+ * by the task with Read Only access and if so, it recovers from the fault
+ * greacefully by moving the Program Counter to the next instruction to the one
+ * which generated the fault. If any other memory access violation occurs, the
+ * fault handler will get stuck in an inifinite loop.
+ */
+void vStartMPUDemo( void );
+
+#endif /* __MPU_DEMO_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ARMv8M/tz_demo/nsc_functions.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ARMv8M/tz_demo/nsc_functions.c
new file mode 100644
index 0000000..9bf2b59
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ARMv8M/tz_demo/nsc_functions.c
@@ -0,0 +1,59 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include 
+#include "nsc_functions.h"
+#include "secure_port_macros.h"
+
+/**
+ * @brief Counter returned from NSCFunction.
+ */
+static uint32_t ulSecureCounter = 0;
+
+/**
+ * @brief typedef for non-secure callback.
+ */
+typedef void ( *NonSecureCallback_t ) ( void ) __attribute__( ( cmse_nonsecure_call ) );
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE uint32_t NSCFunction( Callback_t pxCallback )
+{
+NonSecureCallback_t pxNonSecureCallback;
+
+	/* Return function pointer with cleared LSB. */
+	pxNonSecureCallback = ( NonSecureCallback_t ) cmse_nsfptr_create( pxCallback );
+
+	/* Invoke the supplied callback. */
+	pxNonSecureCallback();
+
+	/* Increment the secure side counter. */
+	ulSecureCounter += 1;
+
+	/* Return the secure side counter. */
+	return ulSecureCounter;
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ARMv8M/tz_demo/nsc_functions.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ARMv8M/tz_demo/nsc_functions.h
new file mode 100644
index 0000000..4564230
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ARMv8M/tz_demo/nsc_functions.h
@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __NSC_FUNCTIONS_H__
+#define __NSC_FUNCTIONS_H__
+
+#include 
+
+/**
+ * @brief Callback function pointer definition.
+ */
+typedef void ( *Callback_t ) ( void );
+
+/**
+ * @brief Invokes the supplied callback which is on the non-secure side.
+ *
+ * Returns a number which is one more than the value returned in previous
+ * invocation of this function. Initial invocation returns 1.
+ *
+ * @param pxCallback[in] The callback to invoke.
+ *
+ * @return A number which is one more than the value returned in previous
+ * invocation of this function.
+ */
+uint32_t NSCFunction( Callback_t pxCallback );
+
+#endif /* __NSC_FUNCTIONS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ARMv8M/tz_demo/tz_demo.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ARMv8M/tz_demo/tz_demo.c
new file mode 100644
index 0000000..7d42da4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ARMv8M/tz_demo/tz_demo.c
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Non-Secure callable functions. */
+#include "nsc_functions.h"
+
+/**
+ * @brief Counter incremented in the callback which is called from the secure
+ * side.
+ *
+ * The size of an MPU region must be a multiple of 32 bytes. Therefore we need
+ * to declare an array of size 8 to ensure that the total size is 32 bytes -
+ * even though we only need 4 bytes. If we do not do that, anything placed after
+ * 4 bytes and upto 32 bytes will also fall in the same MPU region and the task
+ * having access to ulNonSecureCounter will also have access to all those items.
+ */
+static uint32_t ulNonSecureCounter[8] __attribute__( ( aligned( 32 ) ) ) = { 0 };
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Creates all the tasks for TZ demo.
+ */
+void vStartTZDemo( void );
+
+/**
+ * @brief Increments the ulNonSecureCounter.
+ *
+ * This function is called from the secure side.
+ */
+static void prvCallback( void );
+
+/**
+ * @brief Implements the task which calls the functions exported from the secure
+ * side.
+ *
+ * @param pvParameters[in] Parameters as passed during task creation.
+ */
+static void prvSecureCallingTask( void * pvParameters );
+/*-----------------------------------------------------------*/
+
+void vStartTZDemo( void )
+{
+static StackType_t xSecureCallingTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );
+TaskParameters_t xSecureCallingTaskParameters =
+{
+	.pvTaskCode		= prvSecureCallingTask,
+	.pcName			= "SecCalling",
+	.usStackDepth	= configMINIMAL_STACK_SIZE,
+	.pvParameters	= NULL,
+	.uxPriority		= tskIDLE_PRIORITY,
+	.puxStackBuffer	= xSecureCallingTaskStack,
+	.xRegions		=	{
+							{ ulNonSecureCounter,	32,	tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER	},
+							{ 0,					0,	0														},
+							{ 0,					0,	0														},
+						}
+};
+
+	/* Create an unprivileged task which calls secure functions. */
+	xTaskCreateRestricted( &( xSecureCallingTaskParameters ), NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvCallback( void )
+{
+	/* This function is called from the secure side. Just increment the counter
+	 * here. The check that this counter keeps incrementing is performed in the
+	 * prvSecureCallingTask. */
+	ulNonSecureCounter[ 0 ] += 1;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSecureCallingTask( void * pvParameters )
+{
+uint32_t ulLastSecureCounter = 0, ulLastNonSecureCounter = 0;
+uint32_t ulCurrentSecureCounter = 0;
+
+	/* This task calls secure side functions. So allocate a secure context for
+	 * it. */
+	portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
+
+	for( ; ; )
+	{
+		/* Call the secure side function. It does two things:
+		 * - It calls the supplied function (prvCallback) which in turn
+		 *   increments the non-secure counter.
+		 * - It increments the secure counter and returns the incremented value.
+		 * Therefore at the end of this function call both the secure and
+		 * non-secure counters must have been incremented.
+		 */
+		ulCurrentSecureCounter = NSCFunction( prvCallback );
+
+		/* Make sure that both the counters are incremented. */
+		configASSERT( ulCurrentSecureCounter == ulLastSecureCounter + 1 );
+		configASSERT( ulNonSecureCounter[ 0 ] == ulLastNonSecureCounter + 1 );
+
+		/* Update the last values for both the counters. */
+		ulLastSecureCounter = ulCurrentSecureCounter;
+		ulLastNonSecureCounter = ulNonSecureCounter[ 0 ];
+
+		/* Wait for a second. */
+		vTaskDelay( pdMS_TO_TICKS( 1000 ) );
+	}
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ARMv8M/tz_demo/tz_demo.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ARMv8M/tz_demo/tz_demo.h
new file mode 100644
index 0000000..f3277ab
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ARMv8M/tz_demo/tz_demo.h
@@ -0,0 +1,45 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __TZ_DEMO_H__
+#define __TZ_DEMO_H__
+
+/**
+ * @brief Creates all the tasks for TZ demo.
+ *
+ * The Trust Zone (TZ) demo creates an unprivileged task which calls a secure
+ * side function and passes a pointer to a callback function. The secure side
+ * function does two things:
+ * 1. It calls the provided callback function. The callback function increments
+ * a counter.
+ * 2. It increments a counter and returns the incremented value.
+ * After the secure function call finishes, it verifies that both the counters
+ * are incremented.
+ */
+void vStartTZDemo( void );
+
+#endif /* __TZ_DEMO_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/BlockQ.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/BlockQ.c
new file mode 100644
index 0000000..63e1091
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/BlockQ.c
@@ -0,0 +1,308 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/**
+ * Creates six tasks that operate on three queues as follows:
+ *
+ * The first two tasks send and receive an incrementing number to/from a queue.  
+ * One task acts as a producer and the other as the consumer.  The consumer is a 
+ * higher priority than the producer and is set to block on queue reads.  The queue 
+ * only has space for one item - as soon as the producer posts a message on the 
+ * queue the consumer will unblock, pre-empt the producer, and remove the item.
+ * 
+ * The second two tasks work the other way around.  Again the queue used only has
+ * enough space for one item.  This time the consumer has a lower priority than the 
+ * producer.  The producer will try to post on the queue blocking when the queue is 
+ * full.  When the consumer wakes it will remove the item from the queue, causing 
+ * the producer to unblock, pre-empt the consumer, and immediately re-fill the 
+ * queue.
+ * 
+ * The last two tasks use the same queue producer and consumer functions.  This time the queue has
+ * enough space for lots of items and the tasks operate at the same priority.  The 
+ * producer will execute, placing items into the queue.  The consumer will start 
+ * executing when either the queue becomes full (causing the producer to block) or 
+ * a context switch occurs (tasks of the same priority will time slice).
+ *
+ * \page BlockQC blockQ.c
+ * \ingroup DemoFiles
+ * 

+ */
+
+/*
+Changes from V1.00:
+	
+	+ Reversed the priority and block times of the second two demo tasks so
+	  they operate as per the description above.
+
+Changes from V2.0.0
+
+	+ Delay periods are now specified using variables and constants of
+	  TickType_t rather than unsigned long.
+
+Changes from V4.0.2
+
+	+ The second set of tasks were created the wrong way around.  This has been
+	  corrected.
+*/
+
+
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* Demo program include files. */
+#include "BlockQ.h"
+#include "print.h"
+
+#define blckqSTACK_SIZE		( ( unsigned short ) configMINIMAL_STACK_SIZE )
+#define blckqNUM_TASK_SETS	( 3 )
+
+/* Structure used to pass parameters to the blocking queue tasks. */
+typedef struct BLOCKING_QUEUE_PARAMETERS
+{
+	QueueHandle_t xQueue;					/*< The queue to be used by the task. */
+	TickType_t xBlockTime;			/*< The block time to use on queue reads/writes. */
+	volatile short *psCheckVariable;	/*< Incremented on each successful cycle to check the task is still running. */
+} xBlockingQueueParameters;
+
+/* Task function that creates an incrementing number and posts it on a queue. */
+static void vBlockingQueueProducer( void *pvParameters );
+
+/* Task function that removes the incrementing number from a queue and checks that 
+it is the expected number. */
+static void vBlockingQueueConsumer( void *pvParameters );
+
+/* Variables which are incremented each time an item is removed from a queue, and 
+found to be the expected value. 
+These are used to check that the tasks are still running. */
+static volatile short sBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( short ) 0, ( short ) 0, ( short ) 0 };
+
+/* Variable which are incremented each time an item is posted on a queue.   These 
+are used to check that the tasks are still running. */
+static volatile short sBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( short ) 0, ( short ) 0, ( short ) 0 };
+
+/*-----------------------------------------------------------*/
+
+void vStartBlockingQueueTasks( unsigned portBASE_TYPE uxPriority )
+{
+xBlockingQueueParameters *pxQueueParameters1, *pxQueueParameters2;
+xBlockingQueueParameters *pxQueueParameters3, *pxQueueParameters4;
+xBlockingQueueParameters *pxQueueParameters5, *pxQueueParameters6;
+const unsigned portBASE_TYPE uxQueueSize1 = 1, uxQueueSize5 = 5;
+const TickType_t xBlockTime = ( TickType_t ) 1000 / portTICK_PERIOD_MS;
+const TickType_t xDontBlock = ( TickType_t ) 0;
+
+	/* Create the first two tasks as described at the top of the file. */ 
+	
+	/* First create the structure used to pass parameters to the consumer tasks. */
+	pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+
+	/* Create the queue used by the first two tasks to pass the incrementing number.  
+	Pass a pointer to the queue in the parameter structure. */
+	pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) );
+
+	/* The consumer is created first so gets a block time as described above. */
+	pxQueueParameters1->xBlockTime = xBlockTime;
+
+	/* Pass in the variable that this task is going to increment so we can check it 
+	is still running. */
+	pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] );
+		
+	/* Create the structure used to pass parameters to the producer task. */
+	pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+
+	/* Pass the queue to this task also, using the parameter structure. */
+	pxQueueParameters2->xQueue = pxQueueParameters1->xQueue;
+
+	/* The producer is not going to block - as soon as it posts the consumer will 
+	wake and remove the item so the producer should always have room to post. */
+	pxQueueParameters2->xBlockTime = xDontBlock;
+
+	/* Pass in the variable that this task is going to increment so we can check 
+	it is still running. */
+	pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] );
+
+
+	/* Note the producer has a lower priority than the consumer when the tasks are 
+	spawned. */
+	xTaskCreate( vBlockingQueueConsumer, "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL );
+	xTaskCreate( vBlockingQueueProducer, "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL );
+
+	
+
+	/* Create the second two tasks as described at the top of the file.   This uses 
+	the same mechanism but reverses the task priorities. */
+
+	pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+	pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) );
+	pxQueueParameters3->xBlockTime = xDontBlock;
+	pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] );
+
+	pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+	pxQueueParameters4->xQueue = pxQueueParameters3->xQueue;
+	pxQueueParameters4->xBlockTime = xBlockTime;
+	pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] );
+
+	xTaskCreate( vBlockingQueueProducer, "QProdB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL );
+	xTaskCreate( vBlockingQueueConsumer, "QConsB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL );
+
+
+
+	/* Create the last two tasks as described above.  The mechanism is again just 
+	the same.  This time both parameter structures are given a block time. */
+	pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+	pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) );
+	pxQueueParameters5->xBlockTime = xBlockTime;
+	pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] );
+
+	pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+	pxQueueParameters6->xQueue = pxQueueParameters5->xQueue;
+	pxQueueParameters6->xBlockTime = xBlockTime;
+	pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] );	
+
+	xTaskCreate( vBlockingQueueProducer, "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL );
+	xTaskCreate( vBlockingQueueConsumer, "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void vBlockingQueueProducer( void *pvParameters )
+{
+unsigned short usValue = 0;
+xBlockingQueueParameters *pxQueueParameters;
+const char * const pcTaskStartMsg = "Blocking queue producer started.\r\n";
+const char * const pcTaskErrorMsg = "Could not post on blocking queue\r\n";
+short sErrorEverOccurred = pdFALSE;
+
+	pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;
+
+	/* Queue a message for printing to say the task has started. */
+	vPrintDisplayMessage( &pcTaskStartMsg );
+
+	for( ;; )
+	{		
+		if( xQueueSendToBack( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS )
+		{
+			vPrintDisplayMessage( &pcTaskErrorMsg );
+			sErrorEverOccurred = pdTRUE;
+		}
+		else
+		{
+			/* We have successfully posted a message, so increment the variable 
+			used to check we are still running. */
+			if( sErrorEverOccurred == pdFALSE )
+			{
+				( *pxQueueParameters->psCheckVariable )++;
+			}
+
+			/* Increment the variable we are going to post next time round.  The 
+			consumer will expect the numbers to	follow in numerical order. */
+			++usValue;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void vBlockingQueueConsumer( void *pvParameters )
+{
+unsigned short usData, usExpectedValue = 0;
+xBlockingQueueParameters *pxQueueParameters;
+const char * const pcTaskStartMsg = "Blocking queue consumer started.\r\n";
+const char * const pcTaskErrorMsg = "Incorrect value received on blocking queue.\r\n";
+short sErrorEverOccurred = pdFALSE;
+
+	/* Queue a message for printing to say the task has started. */
+	vPrintDisplayMessage( &pcTaskStartMsg );
+
+	pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;
+
+	for( ;; )
+	{	
+		if( xQueueReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS )
+		{
+			if( usData != usExpectedValue )
+			{
+				vPrintDisplayMessage( &pcTaskErrorMsg );
+
+				/* Catch-up. */
+				usExpectedValue = usData;
+
+				sErrorEverOccurred = pdTRUE;
+			}
+			else
+			{
+				/* We have successfully received a message, so increment the 
+				variable used to check we are still running. */	
+				if( sErrorEverOccurred == pdFALSE )
+				{
+					( *pxQueueParameters->psCheckVariable )++;
+				}
+							
+				/* Increment the value we expect to remove from the queue next time 
+				round. */
+				++usExpectedValue;
+			}			
+		}		
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* This is called to check that all the created tasks are still running. */
+portBASE_TYPE xAreBlockingQueuesStillRunning( void )
+{
+static short sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( short ) 0, ( short ) 0, ( short ) 0 };
+static short sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( short ) 0, ( short ) 0, ( short ) 0 };
+portBASE_TYPE xReturn = pdPASS, xTasks;
+
+	/* Not too worried about mutual exclusion on these variables as they are 16 
+	bits and we are only reading them. We also only care to see if they have 
+	changed or not.
+	
+	Loop through each check variable and return pdFALSE if any are found not 
+	to have changed since the last call. */
+
+	for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ )
+	{
+		if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ]  )
+		{
+			xReturn = pdFALSE;
+		}
+		sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ];
+
+
+		if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ]  )
+		{
+			xReturn = pdFALSE;
+		}
+		sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ];
+	}
+
+	return xReturn;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/PollQ.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/PollQ.c
new file mode 100644
index 0000000..169ab48
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/PollQ.c
@@ -0,0 +1,220 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/**
+ * This is a very simple queue test.  See the BlockQ. c documentation for a more 
+ * comprehensive version.
+ *
+ * Creates two tasks that communicate over a single queue.  One task acts as a 
+ * producer, the other a consumer.  
+ *
+ * The producer loops for three iteration, posting an incrementing number onto the 
+ * queue each cycle.  It then delays for a fixed period before doing exactly the 
+ * same again.
+ *
+ * The consumer loops emptying the queue.  Each item removed from the queue is 
+ * checked to ensure it contains the expected value.  When the queue is empty it 
+ * blocks for a fixed period, then does the same again.
+ *
+ * All queue access is performed without blocking.  The consumer completely empties 
+ * the queue each time it runs so the producer should never find the queue full.  
+ *
+ * An error is flagged if the consumer obtains an unexpected value or the producer 
+ * find the queue is full.
+ *
+ * \page PollQC pollQ.c
+ * \ingroup DemoFiles
+ * 

+ */
+
+/*
+Changes from V2.0.0
+
+	+ Delay periods are now specified using variables and constants of
+	  TickType_t rather than unsigned long.
+*/
+
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "print.h"
+
+/* Demo program include files. */
+#include "PollQ.h"
+
+#define pollqSTACK_SIZE		( ( unsigned short ) configMINIMAL_STACK_SIZE )
+
+/* The task that posts the incrementing number onto the queue. */
+static void vPolledQueueProducer( void *pvParameters );
+
+/* The task that empties the queue. */
+static void vPolledQueueConsumer( void *pvParameters );
+
+/* Variables that are used to check that the tasks are still running with no errors. */
+static volatile short sPollingConsumerCount = 0, sPollingProducerCount = 0;
+/*-----------------------------------------------------------*/
+
+void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority )
+{
+static QueueHandle_t xPolledQueue;
+const unsigned portBASE_TYPE uxQueueSize = 10;
+
+	/* Create the queue used by the producer and consumer. */
+	xPolledQueue = xQueueCreate( uxQueueSize, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) );
+
+	/* Spawn the producer and consumer. */
+	xTaskCreate( vPolledQueueConsumer, "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, NULL );
+	xTaskCreate( vPolledQueueProducer, "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void vPolledQueueProducer( void *pvParameters )
+{
+unsigned short usValue = 0, usLoop;
+QueueHandle_t *pxQueue;
+const TickType_t xDelay = ( TickType_t ) 200 / portTICK_PERIOD_MS;
+const unsigned short usNumToProduce = 3;
+const char * const pcTaskStartMsg = "Polled queue producer started.\r\n";
+const char * const pcTaskErrorMsg = "Could not post on polled queue.\r\n";
+short sError = pdFALSE;
+
+	/* Queue a message for printing to say the task has started. */
+	vPrintDisplayMessage( &pcTaskStartMsg );
+
+	/* The queue being used is passed in as the parameter. */
+	pxQueue = ( QueueHandle_t * ) pvParameters;
+
+	for( ;; )
+	{		
+		for( usLoop = 0; usLoop < usNumToProduce; ++usLoop )
+		{
+			/* Send an incrementing number on the queue without blocking. */
+			if( xQueueSendToBack( *pxQueue, ( void * ) &usValue, ( TickType_t ) 0 ) != pdPASS )
+			{
+				/* We should never find the queue full - this is an error. */
+				vPrintDisplayMessage( &pcTaskErrorMsg );
+				sError = pdTRUE;
+			}
+			else
+			{
+				if( sError == pdFALSE )
+				{
+					/* If an error has ever been recorded we stop incrementing the 
+					check variable. */
+					++sPollingProducerCount;
+				}
+
+				/* Update the value we are going to post next time around. */
+				++usValue;
+			}
+		}
+
+		/* Wait before we start posting again to ensure the consumer runs and 
+		empties the queue. */
+		vTaskDelay( xDelay );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void vPolledQueueConsumer( void *pvParameters )
+{
+unsigned short usData, usExpectedValue = 0;
+QueueHandle_t *pxQueue;
+const TickType_t xDelay = ( TickType_t ) 200 / portTICK_PERIOD_MS;
+const char * const pcTaskStartMsg = "Polled queue consumer started.\r\n";
+const char * const pcTaskErrorMsg = "Incorrect value received on polled queue.\r\n";
+short sError = pdFALSE;
+
+	/* Queue a message for printing to say the task has started. */
+	vPrintDisplayMessage( &pcTaskStartMsg );
+
+	/* The queue being used is passed in as the parameter. */
+	pxQueue = ( QueueHandle_t * ) pvParameters;
+
+	for( ;; )
+	{		
+		/* Loop until the queue is empty. */
+		while( uxQueueMessagesWaiting( *pxQueue ) )
+		{
+			if( xQueueReceive( *pxQueue, &usData, ( TickType_t ) 0 ) == pdPASS )
+			{
+				if( usData != usExpectedValue )
+				{
+					/* This is not what we expected to receive so an error has 
+					occurred. */
+					vPrintDisplayMessage( &pcTaskErrorMsg );
+					sError = pdTRUE;
+					/* Catch-up to the value we received so our next expected value 
+					should again be correct. */
+					usExpectedValue = usData;
+				}
+				else
+				{
+					if( sError == pdFALSE )
+					{
+						/* Only increment the check variable if no errors have 
+						occurred. */
+						++sPollingConsumerCount;
+					}
+				}
+				++usExpectedValue;
+			}
+		}
+
+		/* Now the queue is empty we block, allowing the producer to place more 
+		items in the queue. */
+		vTaskDelay( xDelay );
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* This is called to check that all the created tasks are still running with no errors. */
+portBASE_TYPE xArePollingQueuesStillRunning( void )
+{
+static short sLastPollingConsumerCount = 0, sLastPollingProducerCount = 0;
+portBASE_TYPE xReturn;
+
+	if( ( sLastPollingConsumerCount == sPollingConsumerCount ) ||
+		( sLastPollingProducerCount == sPollingProducerCount ) 
+	  )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	sLastPollingConsumerCount = sPollingConsumerCount;
+	sLastPollingProducerCount = sPollingProducerCount;
+
+	return xReturn;
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/comtest.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/comtest.c
new file mode 100644
index 0000000..6019c7c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/comtest.c
@@ -0,0 +1,346 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/**
+ * Creates two tasks that operate on an interrupt driven serial port.  A loopback 
+ * connector should be used so that everything that is transmitted is also received.  
+ * The serial port does not use any flow control.  On a standard 9way 'D' connector 
+ * pins two and three should be connected together.
+ *
+ * The first task repeatedly sends a string to a queue, character at a time.  The 
+ * serial port interrupt will empty the queue and transmit the characters.  The 
+ * task blocks for a pseudo random period before resending the string.
+ *
+ * The second task blocks on a queue waiting for a character to be received.  
+ * Characters received by the serial port interrupt routine are posted onto the 
+ * queue - unblocking the task making it ready to execute.  If this is then the 
+ * highest priority task ready to run it will run immediately - with a context 
+ * switch occurring at the end of the interrupt service routine.  The task 
+ * receiving characters is spawned with a higher priority than the task 
+ * transmitting the characters.
+ *
+ * With the loop back connector in place, one task will transmit a string and the 
+ * other will immediately receive it.  The receiving task knows the string it 
+ * expects to receive so can detect an error.
+ *
+ * This also creates a third task.  This is used to test semaphore usage from an
+ * ISR and does nothing interesting.  
+ * 
+ * \page ComTestC comtest.c
+ * \ingroup DemoFiles
+ * 

+ */
+
+/*
+Changes from V1.00:
+	
+	+ The priority of the Rx task has been lowered.  Received characters are
+	  now processed (read from the queue) at the idle priority, allowing low
+	  priority tasks to run evenly at times of a high communications overhead.
+
+Changes from V1.01:
+
+	+ The Tx task now waits a pseudo random time between transissions.
+	  Previously a fixed period was used but this was not such a good test as
+	  interrupts fired at regular intervals.
+
+Changes From V1.2.0:
+
+	+ Use vSerialPutString() instead of single character puts.
+	+ Only stop the check variable incrementing after two consecutive errors. 
+
+Changed from V1.2.5
+
+	+ Made the Rx task 2 priorities higher than the Tx task.  Previously it was
+	  only 1.  This is done to tie in better with the other demo application 
+	  tasks.
+
+Changes from V2.0.0
+
+	+ Delay periods are now specified using variables and constants of
+	  TickType_t rather than unsigned long.
+	+ Slight modification to task priorities.
+
+*/
+
+
+/* Scheduler include files. */
+#include 
+#include 
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo program include files. */
+#include "serial.h"
+#include "comtest.h"
+#include "print.h"
+
+/* The Tx task will transmit the sequence of characters at a pseudo random
+interval.  This is the maximum and minimum block time between sends. */
+#define comTX_MAX_BLOCK_TIME		( ( TickType_t ) 0x15e )
+#define comTX_MIN_BLOCK_TIME		( ( TickType_t ) 0xc8 )
+
+#define comMAX_CONSECUTIVE_ERRORS	( 2 )
+
+#define comSTACK_SIZE				( ( unsigned short ) 256 )
+
+#define comRX_RELATIVE_PRIORITY		( 1 )
+
+/* Handle to the com port used by both tasks. */
+static xComPortHandle xPort;
+
+/* The transmit function as described at the top of the file. */
+static void vComTxTask( void *pvParameters );
+
+/* The receive function as described at the top of the file. */
+static void vComRxTask( void *pvParameters );
+
+/* The semaphore test function as described at the top of the file. */
+static void vSemTestTask( void * pvParameters );
+
+/* The string that is repeatedly transmitted. */
+const char * const pcMessageToExchange = 	"Send this message over and over again to check communications interrupts. "
+									   			"0123456789abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ\r\n";
+
+/* Variables that are incremented on each cycle of each task.  These are used to 
+check that both tasks are still executing. */
+volatile short sTxCount = 0, sRxCount = 0, sSemCount = 0;
+
+/* The handle to the semaphore test task. */
+static TaskHandle_t xSemTestTaskHandle = NULL;
+
+/*-----------------------------------------------------------*/
+
+void vStartComTestTasks( unsigned portBASE_TYPE uxPriority, eCOMPort ePort, eBaud eBaudRate )
+{
+const unsigned portBASE_TYPE uxBufferLength = 255;
+
+	/* Initialise the com port then spawn both tasks. */
+	xPort = xSerialPortInit( ePort, eBaudRate, serNO_PARITY, serBITS_8, serSTOP_1, uxBufferLength );
+	xTaskCreate( vComTxTask, "COMTx", comSTACK_SIZE, NULL, uxPriority, NULL );
+	xTaskCreate( vComRxTask, "COMRx", comSTACK_SIZE, NULL, uxPriority + comRX_RELATIVE_PRIORITY, NULL );
+	xTaskCreate( vSemTestTask, "ISRSem", comSTACK_SIZE, NULL, tskIDLE_PRIORITY, &xSemTestTaskHandle );
+}
+/*-----------------------------------------------------------*/
+
+static void vComTxTask( void *pvParameters )
+{
+const char * const pcTaskStartMsg = "COM Tx task started.\r\n";
+TickType_t xTimeToWait;
+
+	/* Stop warnings. */
+	( void ) pvParameters;
+
+	/* Queue a message for printing to say the task has started. */
+	vPrintDisplayMessage( &pcTaskStartMsg );
+
+	for( ;; )
+	{
+		/* Send the string to the serial port. */
+		vSerialPutString( xPort, pcMessageToExchange, strlen( pcMessageToExchange ) );
+
+		/* We have posted all the characters in the string - increment the variable 
+		used to check that this task is still running, then wait before re-sending 
+		the string. */
+		sTxCount++;
+
+		xTimeToWait = xTaskGetTickCount();
+
+		/* Make sure we don't wait too long... */
+		xTimeToWait %= comTX_MAX_BLOCK_TIME;
+
+		/* ...but we do want to wait. */
+		if( xTimeToWait < comTX_MIN_BLOCK_TIME )
+		{
+			xTimeToWait = comTX_MIN_BLOCK_TIME;
+		}
+
+		vTaskDelay( xTimeToWait );
+	}
+} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */
+/*-----------------------------------------------------------*/
+
+static void vComRxTask( void *pvParameters )
+{
+const char * const pcTaskStartMsg = "COM Rx task started.\r\n";
+const char * const pcTaskErrorMsg = "COM read error\r\n";
+const char * const pcTaskRestartMsg = "COM resynced\r\n";
+const char * const pcTaskTimeoutMsg = "COM Rx timed out\r\n";
+const TickType_t xBlockTime = ( TickType_t ) 0xffff / portTICK_PERIOD_MS;
+const char *pcExpectedChar;
+portBASE_TYPE xGotChar;
+char cRxedChar;
+short sResyncRequired, sConsecutiveErrors, sLatchedError;
+
+	/* Stop warnings. */
+	( void ) pvParameters;
+
+	/* Queue a message for printing to say the task has started. */
+	vPrintDisplayMessage( &pcTaskStartMsg );
+	
+	/* The first expected character is the first character in the string. */
+	pcExpectedChar = pcMessageToExchange;
+	sResyncRequired = pdFALSE;
+	sConsecutiveErrors = 0;
+	sLatchedError = pdFALSE;
+
+	for( ;; )
+	{
+		/* Receive a message from the com port interrupt routine.  If a message is 
+		not yet available the call will block the task. */
+		xGotChar = xSerialGetChar( xPort, &cRxedChar, xBlockTime );
+		if( xGotChar == pdTRUE )
+		{
+			if( sResyncRequired == pdTRUE )
+			{
+				/* We got out of sequence and are waiting for the start of the next 
+				transmission of the string. */
+				if( cRxedChar == '\n' )
+				{
+					/* This is the end of the message so we can start again - with 
+					the first character in the string being the next thing we expect 
+					to receive. */
+					pcExpectedChar = pcMessageToExchange;
+					sResyncRequired = pdFALSE;
+
+					/* Queue a message for printing to say that we are going to try 
+					again. */
+					vPrintDisplayMessage( &pcTaskRestartMsg );
+
+					/* Stop incrementing the check variable, if consecutive errors occur. */
+					sConsecutiveErrors++;
+					if( sConsecutiveErrors >= comMAX_CONSECUTIVE_ERRORS )
+					{
+						sLatchedError = pdTRUE;
+					}
+				}
+			}
+			else
+			{
+				/* We have received a character, but is it the expected character? */
+				if( cRxedChar != *pcExpectedChar )
+				{
+					/* This was not the expected character so post a message for 
+					printing to say that an error has occurred.  We will then wait 
+					to resynchronise. */
+					vPrintDisplayMessage( &pcTaskErrorMsg );					
+					sResyncRequired = pdTRUE;
+				}
+				else
+				{
+					/* This was the expected character so next time we will expect 
+					the next character in the string.  Wrap back to the beginning 
+					of the string when the null terminator has been reached. */
+					pcExpectedChar++;
+					if( *pcExpectedChar == '\0' )
+					{
+						pcExpectedChar = pcMessageToExchange;
+
+						/* We have got through the entire string without error. */
+						sConsecutiveErrors = 0;
+					}
+				}
+			}
+
+			/* Increment the count that is used to check that this task is still 
+			running.  This is only done if an error has never occurred. */
+			if( sLatchedError == pdFALSE )
+			{
+				sRxCount++;			
+			}
+		}
+		else
+		{
+			vPrintDisplayMessage( &pcTaskTimeoutMsg );
+		}
+	}
+} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */
+/*-----------------------------------------------------------*/
+
+static void vSemTestTask( void * pvParameters )
+{
+const char * const pcTaskStartMsg = "ISR Semaphore test started.\r\n";
+portBASE_TYPE xError = pdFALSE;
+
+ 	/* Stop warnings. */
+	( void ) pvParameters;
+
+	/* Queue a message for printing to say the task has started. */
+	vPrintDisplayMessage( &pcTaskStartMsg );
+
+	for( ;; )
+	{
+		if( xSerialWaitForSemaphore( xPort ) )
+		{
+			if( xError == pdFALSE )
+			{
+				sSemCount++;
+			}
+		}
+		else
+		{
+			xError = pdTRUE;
+		}
+	}
+} /*lint !e715 !e830 !e818 pvParameters not used but function prototype must be standard for task function. */
+/*-----------------------------------------------------------*/
+
+/* This is called to check that all the created tasks are still running. */
+portBASE_TYPE xAreComTestTasksStillRunning( void )
+{
+static short sLastTxCount = 0, sLastRxCount = 0, sLastSemCount = 0;
+portBASE_TYPE xReturn;
+
+	/* Not too worried about mutual exclusion on these variables as they are 16 
+	bits and we are only reading them.  We also only care to see if they have 
+	changed or not. */
+
+	if( ( sTxCount == sLastTxCount ) || ( sRxCount == sLastRxCount ) || ( sSemCount == sLastSemCount ) )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	sLastTxCount = sTxCount;
+	sLastRxCount = sRxCount;
+	sLastSemCount = sSemCount;
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vComTestUnsuspendTask( void )
+{
+	/* The task that is suspended on the semaphore will be referenced from the
+	Suspended list as it is blocking indefinitely.  This call just checks that
+	the kernel correctly detects this and does not attempt to unsuspend the
+	task. */
+	xTaskResumeFromISR( xSemTestTaskHandle );
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/death.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/death.c
new file mode 100644
index 0000000..7bc65f5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/death.c
@@ -0,0 +1,203 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/**
+ * Create a single persistent task which periodically dynamically creates another 
+ * four tasks.  The original task is called the creator task, the four tasks it 
+ * creates are called suicidal tasks.
+ *
+ * Two of the created suicidal tasks kill one other suicidal task before killing 
+ * themselves - leaving just the original task remaining.  
+ *
+ * The creator task must be spawned after all of the other demo application tasks 
+ * as it keeps a check on the number of tasks under the scheduler control.  The 
+ * number of tasks it expects to see running should never be greater than the 
+ * number of tasks that were in existence when the creator task was spawned, plus 
+ * one set of four suicidal tasks.  If this number is exceeded an error is flagged.
+ *
+ * \page DeathC death.c
+ * \ingroup DemoFiles
+ * 

+ */
+
+/*
+Changes from V2.0.0
+
+	+ Delay periods are now specified using variables and constants of
+	  TickType_t rather than unsigned long.
+*/
+
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo program include files. */
+#include "death.h"
+#include "print.h"
+
+#define deathSTACK_SIZE		( ( unsigned short ) 512 )
+
+/* The task originally created which is responsible for periodically dynamically 
+creating another four tasks. */
+static void vCreateTasks( void *pvParameters );
+
+/* The task function of the dynamically created tasks. */
+static void vSuicidalTask( void *pvParameters );
+
+/* A variable which is incremented every time the dynamic tasks are created.  This 
+is used to check that the task is still running. */
+static volatile short sCreationCount = 0;
+
+/* Used to store the number of tasks that were originally running so the creator 
+task can tell if any of the suicidal tasks have failed to die. */
+static volatile unsigned portBASE_TYPE uxTasksRunningAtStart = 0;
+static const unsigned portBASE_TYPE uxMaxNumberOfExtraTasksRunning = 5;
+
+/* Used to store a handle to the tasks that should be killed by a suicidal task, 
+before it kills itself. */
+TaskHandle_t xCreatedTask1, xCreatedTask2;
+
+/*-----------------------------------------------------------*/
+
+void vCreateSuicidalTasks( unsigned portBASE_TYPE uxPriority )
+{
+unsigned portBASE_TYPE *puxPriority;
+
+	/* Create the Creator tasks - passing in as a parameter the priority at which 
+	the suicidal tasks should be created. */
+	puxPriority = ( unsigned portBASE_TYPE * ) pvPortMalloc( sizeof( unsigned portBASE_TYPE ) );
+	*puxPriority = uxPriority;
+
+	xTaskCreate( vCreateTasks, "CREATOR", deathSTACK_SIZE, ( void * ) puxPriority, uxPriority, NULL );
+
+	/* Record the number of tasks that are running now so we know if any of the 
+	suicidal tasks have failed to be killed. */
+	uxTasksRunningAtStart = uxTaskGetNumberOfTasks();
+}
+/*-----------------------------------------------------------*/
+
+static void vSuicidalTask( void *pvParameters )
+{
+portDOUBLE d1, d2;
+TaskHandle_t xTaskToKill;
+const TickType_t xDelay = ( TickType_t ) 500 / portTICK_PERIOD_MS;
+
+	if( pvParameters != NULL )
+	{
+		/* This task is periodically created four times.  Tow created tasks are 
+		passed a handle to the other task so it can kill it before killing itself.  
+		The other task is passed in null. */
+		xTaskToKill = *( TaskHandle_t* )pvParameters;
+	}
+	else
+	{
+		xTaskToKill = NULL;
+	}
+
+	for( ;; )
+	{
+		/* Do something random just to use some stack and registers. */
+		d1 = 2.4;
+		d2 = 89.2;
+		d2 *= d1;
+		vTaskDelay( xDelay );
+
+		if( xTaskToKill != NULL )
+		{
+			/* Make sure the other task has a go before we delete it. */
+			vTaskDelay( ( TickType_t ) 0 );
+			/* Kill the other task that was created by vCreateTasks(). */
+			vTaskDelete( xTaskToKill );
+			/* Kill ourselves. */
+			vTaskDelete( NULL );
+		}
+	}
+}/*lint !e818 !e550 Function prototype must be as per standard for task functions. */
+/*-----------------------------------------------------------*/
+
+static void vCreateTasks( void *pvParameters )
+{
+const TickType_t xDelay = ( TickType_t ) 1000 / portTICK_PERIOD_MS;
+unsigned portBASE_TYPE uxPriority;
+const char * const pcTaskStartMsg = "Create task started.\r\n";
+
+	/* Queue a message for printing to say the task has started. */
+	vPrintDisplayMessage( &pcTaskStartMsg );
+
+	uxPriority = *( unsigned portBASE_TYPE * ) pvParameters;
+	vPortFree( pvParameters );
+
+	for( ;; )
+	{
+		/* Just loop round, delaying then creating the four suicidal tasks. */
+		vTaskDelay( xDelay );
+
+		xTaskCreate( vSuicidalTask, "SUICIDE1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask1 );
+		xTaskCreate( vSuicidalTask, "SUICIDE2", deathSTACK_SIZE, &xCreatedTask1, uxPriority, NULL );
+
+		xTaskCreate( vSuicidalTask, "SUICIDE1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask2 );
+		xTaskCreate( vSuicidalTask, "SUICIDE2", deathSTACK_SIZE, &xCreatedTask2, uxPriority, NULL );
+
+		++sCreationCount;
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* This is called to check that the creator task is still running and that there 
+are not any more than four extra tasks. */
+portBASE_TYPE xIsCreateTaskStillRunning( void )
+{
+static short sLastCreationCount = 0;
+short sReturn = pdTRUE;
+unsigned portBASE_TYPE uxTasksRunningNow;
+
+	if( sLastCreationCount == sCreationCount )
+	{
+		sReturn = pdFALSE;
+	}
+	
+	uxTasksRunningNow = uxTaskGetNumberOfTasks();
+
+	if( uxTasksRunningNow < uxTasksRunningAtStart )
+	{
+		sReturn = pdFALSE;
+	}
+	else if( ( uxTasksRunningNow - uxTasksRunningAtStart ) > uxMaxNumberOfExtraTasksRunning )
+	{
+		sReturn = pdFALSE;
+	}
+	else
+	{
+		/* Everything is okay. */
+	}
+
+	return sReturn;
+}
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/dynamic.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/dynamic.c
new file mode 100644
index 0000000..1311eb6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/dynamic.c
@@ -0,0 +1,578 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/**
+ * The first test creates three tasks - two counter tasks (one continuous count 
+ * and one limited count) and one controller.  A "count" variable is shared 
+ * between all three tasks.  The two counter tasks should never be in a "ready" 
+ * state at the same time.  The controller task runs at the same priority as 
+ * the continuous count task, and at a lower priority than the limited count 
+ * task.
+ *
+ * One counter task loops indefinitely, incrementing the shared count variable
+ * on each iteration.  To ensure it has exclusive access to the variable it
+ * raises it's priority above that of the controller task before each 
+ * increment, lowering it again to it's original priority before starting the
+ * next iteration.
+ *
+ * The other counter task increments the shared count variable on each
+ * iteration of it's loop until the count has reached a limit of 0xff - at
+ * which point it suspends itself.  It will not start a new loop until the 
+ * controller task has made it "ready" again by calling vTaskResume ().  
+ * This second counter task operates at a higher priority than controller 
+ * task so does not need to worry about mutual exclusion of the counter 
+ * variable.
+ *
+ * The controller task is in two sections.  The first section controls and
+ * monitors the continuous count task.  When this section is operational the 
+ * limited count task is suspended.  Likewise, the second section controls 
+ * and monitors the limited count task.  When this section is operational the 
+ * continuous count task is suspended.
+ *
+ * In the first section the controller task first takes a copy of the shared
+ * count variable.  To ensure mutual exclusion on the count variable it
+ * suspends the continuous count task, resuming it again when the copy has been
+ * taken.  The controller task then sleeps for a fixed period - during which
+ * the continuous count task will execute and increment the shared variable.
+ * When the controller task wakes it checks that the continuous count task
+ * has executed by comparing the copy of the shared variable with its current
+ * value.  This time, to ensure mutual exclusion, the scheduler itself is 
+ * suspended with a call to vTaskSuspendAll ().  This is for demonstration 
+ * purposes only and is not a recommended technique due to its inefficiency.
+ *
+ * After a fixed number of iterations the controller task suspends the 
+ * continuous count task, and moves on to its second section.
+ *
+ * At the start of the second section the shared variable is cleared to zero.
+ * The limited count task is then woken from it's suspension by a call to
+ * vTaskResume ().  As this counter task operates at a higher priority than
+ * the controller task the controller task should not run again until the
+ * shared variable has been counted up to the limited value causing the counter
+ * task to suspend itself.  The next line after vTaskResume () is therefore
+ * a check on the shared variable to ensure everything is as expected.
+ *
+ *
+ * The second test consists of a couple of very simple tasks that post onto a 
+ * queue while the scheduler is suspended.  This test was added to test parts
+ * of the scheduler not exercised by the first test.
+ *
+ *
+ * The final set of two tasks implements a third test.  This simply raises the
+ * priority of a task while the scheduler is suspended.  Again this test was
+ * added to exercise parts of the code not covered by the first test.
+ *
+ * \page Priorities dynamic.c
+ * \ingroup DemoFiles
+ * 

+ */
+
+/*
+Changes from V2.0.0
+
+	+ Delay periods are now specified using variables and constants of
+	  TickType_t rather than unsigned long.
+	+ Added a second, simple test that uses the functions 
+	  vQueueReceiveWhenSuspendedTask() and vQueueSendWhenSuspendedTask().
+
+Changes from V3.1.1
+
+	+ Added a third simple test that uses the vTaskPrioritySet() function
+	  while the scheduler is suspended.
+	+ Modified the controller task slightly to test the calling of 
+	  vTaskResumeAll() while the scheduler is suspended.
+*/
+
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+
+/* Demo app include files. */
+#include "dynamic.h"
+#include "print.h"
+
+/* Function that implements the "limited count" task as described above. */
+static void vLimitedIncrementTask( void * pvParameters );
+
+/* Function that implements the "continuous count" task as described above. */
+static void vContinuousIncrementTask( void * pvParameters );
+
+/* Function that implements the controller task as described above. */
+static void vCounterControlTask( void * pvParameters );
+
+/* The simple test functions that check sending and receiving while the
+scheduler is suspended. */
+static void vQueueReceiveWhenSuspendedTask( void *pvParameters );
+static void vQueueSendWhenSuspendedTask( void *pvParameters );
+
+/* The simple test functions that check raising and lowering of task priorities
+while the scheduler is suspended. */
+static void prvChangePriorityWhenSuspendedTask( void *pvParameters );
+static void prvChangePriorityHelperTask( void *pvParameters );
+
+
+/* Demo task specific constants. */
+#define priSTACK_SIZE				( ( unsigned short ) configMINIMAL_STACK_SIZE )
+#define priSLEEP_TIME				( ( TickType_t ) 50 )
+#define priLOOPS					( 5 )
+#define priMAX_COUNT				( ( unsigned long ) 0xff )
+#define priNO_BLOCK					( ( TickType_t ) 0 )
+#define priSUSPENDED_QUEUE_LENGTH	( 1 )
+
+/*-----------------------------------------------------------*/
+
+/* Handles to the two counter tasks.  These could be passed in as parameters
+to the controller task to prevent them having to be file scope. */
+static TaskHandle_t xContinuousIncrementHandle, xLimitedIncrementHandle, xChangePriorityWhenSuspendedHandle;
+
+/* The shared counter variable.  This is passed in as a parameter to the two 
+counter variables for demonstration purposes. */
+static unsigned long ulCounter;
+
+/* Variable used in a similar way by the test that checks the raising and
+lowering of task priorities while the scheduler is suspended. */
+static unsigned long ulPrioritySetCounter;
+
+/* Variables used to check that the tasks are still operating without error.
+Each complete iteration of the controller task increments this variable
+provided no errors have been found.  The variable maintaining the same value
+is therefore indication of an error. */
+static unsigned short usCheckVariable = ( unsigned short ) 0;
+static portBASE_TYPE xSuspendedQueueSendError = pdFALSE;
+static portBASE_TYPE xSuspendedQueueReceiveError = pdFALSE;
+static portBASE_TYPE xPriorityRaiseWhenSuspendedError = pdFALSE;
+
+/* Queue used by the second test. */
+QueueHandle_t xSuspendedTestQueue;
+
+/*-----------------------------------------------------------*/
+/*
+ * Start the seven tasks as described at the top of the file.
+ * Note that the limited count task is given a higher priority.
+ */
+void vStartDynamicPriorityTasks( void )
+{
+	xSuspendedTestQueue = xQueueCreate( priSUSPENDED_QUEUE_LENGTH, sizeof( unsigned long ) );
+	xTaskCreate( vContinuousIncrementTask, "CONT_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY, &xContinuousIncrementHandle );
+	xTaskCreate( vLimitedIncrementTask, "LIM_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY + 1, &xLimitedIncrementHandle );
+	xTaskCreate( vCounterControlTask, "C_CTRL", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+	xTaskCreate( vQueueSendWhenSuspendedTask, "SUSP_SEND", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+	xTaskCreate( vQueueReceiveWhenSuspendedTask, "SUSP_RECV", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+	xTaskCreate( prvChangePriorityWhenSuspendedTask, "1st_P_CHANGE", priSTACK_SIZE, NULL, tskIDLE_PRIORITY + 1, NULL );
+	xTaskCreate( prvChangePriorityHelperTask, "2nd_P_CHANGE", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, &xChangePriorityWhenSuspendedHandle );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Just loops around incrementing the shared variable until the limit has been
+ * reached.  Once the limit has been reached it suspends itself. 
+ */
+static void vLimitedIncrementTask( void * pvParameters )
+{
+unsigned long *pulCounter;
+
+	/* Take a pointer to the shared variable from the parameters passed into
+	the task. */
+	pulCounter = ( unsigned long * ) pvParameters;
+
+	/* This will run before the control task, so the first thing it does is
+	suspend - the control task will resume it when ready. */
+	vTaskSuspend( NULL );
+
+	for( ;; )
+	{
+		/* Just count up to a value then suspend. */
+		( *pulCounter )++;	
+		
+		if( *pulCounter >= priMAX_COUNT )
+		{
+			vTaskSuspend( NULL );
+		} 	
+	}
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Just keep counting the shared variable up.  The control task will suspend
+ * this task when it wants.
+ */
+static void vContinuousIncrementTask( void * pvParameters )
+{
+unsigned long *pulCounter;
+unsigned portBASE_TYPE uxOurPriority;
+
+	/* Take a pointer to the shared variable from the parameters passed into
+	the task. */
+	pulCounter = ( unsigned long * ) pvParameters;
+
+	/* Query our priority so we can raise it when exclusive access to the 
+	shared variable is required. */
+	uxOurPriority = uxTaskPriorityGet( NULL );
+
+	for( ;; )
+	{
+		/* Raise our priority above the controller task to ensure a context
+		switch does not occur while we are accessing this variable. */
+		vTaskPrioritySet( NULL, uxOurPriority + 1 );
+			( *pulCounter )++;		
+		vTaskPrioritySet( NULL, uxOurPriority );
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+	}
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Controller task as described above.
+ */
+static void vCounterControlTask( void * pvParameters )
+{
+unsigned long ulLastCounter;
+short sLoops;
+short sError = pdFALSE;
+const char * const pcTaskStartMsg = "Priority manipulation tasks started.\r\n";
+const char * const pcTaskFailMsg = "Priority manipulation Task Failed\r\n";
+
+	/* Just to stop warning messages. */
+	( void ) pvParameters;
+
+	/* Queue a message for printing to say the task has started. */
+	vPrintDisplayMessage( &pcTaskStartMsg );
+
+	for( ;; )
+	{
+		/* Start with the counter at zero. */
+		ulCounter = ( unsigned long ) 0;
+
+		/* First section : */
+
+		/* Check the continuous count task is running. */
+		for( sLoops = 0; sLoops < priLOOPS; sLoops++ )
+		{
+			/* Suspend the continuous count task so we can take a mirror of the
+			shared variable without risk of corruption. */
+			vTaskSuspend( xContinuousIncrementHandle );
+				ulLastCounter = ulCounter;
+			vTaskResume( xContinuousIncrementHandle );
+			
+			/* Now delay to ensure the other task has processor time. */
+			vTaskDelay( priSLEEP_TIME );
+
+			/* Check the shared variable again.  This time to ensure mutual 
+			exclusion the whole scheduler will be locked.  This is just for
+			demo purposes! */
+			vTaskSuspendAll();
+			{
+				if( ulLastCounter == ulCounter )
+				{
+					/* The shared variable has not changed.  There is a problem
+					with the continuous count task so flag an error. */
+					sError = pdTRUE;
+					xTaskResumeAll();
+						vPrintDisplayMessage( &pcTaskFailMsg );
+					vTaskSuspendAll();
+				}
+			}
+			xTaskResumeAll();
+		}
+
+
+		/* Second section: */
+
+		/* Suspend the continuous counter task so it stops accessing the shared variable. */
+		vTaskSuspend( xContinuousIncrementHandle );
+
+		/* Reset the variable. */
+		ulCounter = ( unsigned long ) 0;
+
+		/* Resume the limited count task which has a higher priority than us.
+		We should therefore not return from this call until the limited count
+		task has suspended itself with a known value in the counter variable. 
+		The scheduler suspension is not necessary but is included for test
+		purposes. */
+		vTaskSuspendAll();
+			vTaskResume( xLimitedIncrementHandle );
+		xTaskResumeAll();
+
+		/* Does the counter variable have the expected value? */
+		if( ulCounter != priMAX_COUNT )
+		{
+			sError = pdTRUE;
+			vPrintDisplayMessage( &pcTaskFailMsg );
+		}
+
+		if( sError == pdFALSE )
+		{
+			/* If no errors have occurred then increment the check variable. */
+			portENTER_CRITICAL();
+				usCheckVariable++;
+			portEXIT_CRITICAL();
+		}
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+		/* Resume the continuous count task and do it all again. */
+		vTaskResume( xContinuousIncrementHandle );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void vQueueSendWhenSuspendedTask( void *pvParameters )
+{
+static unsigned long ulValueToSend = ( unsigned long ) 0;
+const char * const pcTaskStartMsg = "Queue send while suspended task started.\r\n";
+const char * const pcTaskFailMsg = "Queue send while suspended failed.\r\n";
+
+	/* Just to stop warning messages. */
+	( void ) pvParameters;
+
+	/* Queue a message for printing to say the task has started. */
+	vPrintDisplayMessage( &pcTaskStartMsg );
+
+	for( ;; )
+	{
+		vTaskSuspendAll();
+		{
+			/* We must not block while the scheduler is suspended! */
+			if( xQueueSend( xSuspendedTestQueue, ( void * ) &ulValueToSend, priNO_BLOCK ) != pdTRUE )
+			{
+				if( xSuspendedQueueSendError == pdFALSE )
+				{
+					xTaskResumeAll();
+						vPrintDisplayMessage( &pcTaskFailMsg );
+					vTaskSuspendAll();
+				}
+
+				xSuspendedQueueSendError = pdTRUE;
+			}
+		}
+		xTaskResumeAll();
+
+		vTaskDelay( priSLEEP_TIME );
+
+		++ulValueToSend;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void vQueueReceiveWhenSuspendedTask( void *pvParameters )
+{
+static unsigned long ulExpectedValue = ( unsigned long ) 0, ulReceivedValue;
+const char * const pcTaskStartMsg = "Queue receive while suspended task started.\r\n";
+const char * const pcTaskFailMsg = "Queue receive while suspended failed.\r\n";
+portBASE_TYPE xGotValue;
+
+	/* Just to stop warning messages. */
+	( void ) pvParameters;
+
+	/* Queue a message for printing to say the task has started. */
+	vPrintDisplayMessage( &pcTaskStartMsg );
+
+	for( ;; )
+	{
+		do
+		{
+			/* Suspending the scheduler here is fairly pointless and 
+			undesirable for a normal application.  It is done here purely
+			to test the scheduler.  The inner xTaskResumeAll() should
+			never return pdTRUE as the scheduler is still locked by the
+			outer call. */
+			vTaskSuspendAll();
+			{
+				vTaskSuspendAll();
+				{
+					xGotValue = xQueueReceive( xSuspendedTestQueue, ( void * ) &ulReceivedValue, priNO_BLOCK );
+				}
+				if( xTaskResumeAll() )
+				{
+					xSuspendedQueueReceiveError = pdTRUE;
+				}
+			}
+			xTaskResumeAll();
+
+			#if configUSE_PREEMPTION == 0
+				taskYIELD();
+			#endif
+
+		} while( xGotValue == pdFALSE );
+
+		if( ulReceivedValue != ulExpectedValue )
+		{
+			if( xSuspendedQueueReceiveError == pdFALSE )
+			{
+				vPrintDisplayMessage( &pcTaskFailMsg );
+			}
+			xSuspendedQueueReceiveError = pdTRUE;
+		}
+
+		++ulExpectedValue;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvChangePriorityWhenSuspendedTask( void *pvParameters )
+{
+const char * const pcTaskStartMsg = "Priority change when suspended task started.\r\n";
+const char * const pcTaskFailMsg = "Priority change when suspended task failed.\r\n";
+
+	/* Just to stop warning messages. */
+	( void ) pvParameters;
+
+	/* Queue a message for printing to say the task has started. */
+	vPrintDisplayMessage( &pcTaskStartMsg );	
+	
+	for( ;; )
+	{
+		/* Start with the counter at 0 so we know what the counter should be
+		when we check it next. */
+		ulPrioritySetCounter = ( unsigned long ) 0;
+
+		/* Resume the helper task.  At this time it has a priority lower than
+		ours so no context switch should occur. */
+		vTaskResume( xChangePriorityWhenSuspendedHandle );
+
+		/* Check to ensure the task just resumed has not executed. */
+		portENTER_CRITICAL();
+		{
+			if( ulPrioritySetCounter != ( unsigned long ) 0 )
+			{
+				xPriorityRaiseWhenSuspendedError = pdTRUE;
+				vPrintDisplayMessage( &pcTaskFailMsg );
+			}
+		}
+		portEXIT_CRITICAL();
+
+		/* Now try raising the priority while the scheduler is suspended. */
+		vTaskSuspendAll();
+		{
+			vTaskPrioritySet( xChangePriorityWhenSuspendedHandle, ( configMAX_PRIORITIES - 1 ) );
+
+			/* Again, even though the helper task has a priority greater than 
+			ours, it should not have executed yet because the scheduler is
+			suspended. */
+			portENTER_CRITICAL();
+			{
+				if( ulPrioritySetCounter != ( unsigned long ) 0 )
+				{
+					xPriorityRaiseWhenSuspendedError = pdTRUE;
+					vPrintDisplayMessage( &pcTaskFailMsg );
+				}
+			}
+			portEXIT_CRITICAL();
+		}
+		xTaskResumeAll();
+		
+		/* Now the scheduler has been resumed the helper task should 
+		immediately preempt us and execute.  When it executes it will increment
+		the ulPrioritySetCounter exactly once before suspending itself.
+
+		We should now always find the counter set to 1. */
+		portENTER_CRITICAL();
+		{
+			if( ulPrioritySetCounter != ( unsigned long ) 1 )
+			{
+				xPriorityRaiseWhenSuspendedError = pdTRUE;
+				vPrintDisplayMessage( &pcTaskFailMsg );
+			}
+		}
+		portEXIT_CRITICAL();
+
+		/* Delay until we try this again. */		
+		vTaskDelay( priSLEEP_TIME * 2 );
+		
+		/* Set the priority of the helper task back ready for the next 
+		execution of this task. */
+		vTaskSuspendAll();
+			vTaskPrioritySet( xChangePriorityWhenSuspendedHandle, tskIDLE_PRIORITY );				
+		xTaskResumeAll();				
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvChangePriorityHelperTask( void *pvParameters )
+{
+	/* Just to stop warning messages. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		/* This is the helper task for prvChangePriorityWhenSuspendedTask().
+		It has it's priority raised and lowered.  When it runs it simply 
+		increments the counter then suspends itself again.  This allows
+		prvChangePriorityWhenSuspendedTask() to know how many times it has
+		executed. */
+		ulPrioritySetCounter++;
+		vTaskSuspend( NULL );
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* Called to check that all the created tasks are still running without error. */
+portBASE_TYPE xAreDynamicPriorityTasksStillRunning( void )
+{
+/* Keep a history of the check variables so we know if it has been incremented 
+since the last call. */
+static unsigned short usLastTaskCheck = ( unsigned short ) 0;
+portBASE_TYPE xReturn = pdTRUE;
+
+	/* Check the tasks are still running by ensuring the check variable
+	is still incrementing. */
+
+	if( usCheckVariable == usLastTaskCheck )
+	{
+		/* The check has not incremented so an error exists. */
+		xReturn = pdFALSE;
+	}
+
+	if( xSuspendedQueueSendError == pdTRUE )
+	{
+		xReturn = pdFALSE;
+	}
+
+	if( xSuspendedQueueReceiveError == pdTRUE )
+	{
+		xReturn = pdFALSE;
+	}
+
+	if( xPriorityRaiseWhenSuspendedError == pdTRUE )
+	{
+		xReturn = pdFALSE;
+	}
+
+	usLastTaskCheck = usCheckVariable;
+	return xReturn;
+}
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/events.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/events.c
new file mode 100644
index 0000000..1e0ec99
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/events.c
@@ -0,0 +1,368 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/**
+ * This file exercises the event mechanism whereby more than one task is
+ * blocked waiting for the same event.
+ *
+ * The demo creates five tasks - four 'event' tasks, and a controlling task.
+ * The event tasks have various different priorities and all block on reading
+ * the same queue.  The controlling task writes data to the queue, then checks
+ * to see which of the event tasks read the data from the queue.  The
+ * controlling task has the lowest priority of all the tasks so is guaranteed
+ * to always get preempted immediately upon writing to the queue.
+ *
+ * By selectively suspending and resuming the event tasks the controlling task
+ * can check that the highest priority task that is blocked on the queue is the
+ * task that reads the posted data from the queue.
+ *
+ * Two of the event tasks share the same priority.  When neither of these tasks
+ * are suspended they should alternate - one reading one message from the queue,
+ * the other the next message, etc.
+ */
+
+/* Standard includes. */
+#include 
+#include 
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* Demo program include files. */
+#include "mevents.h"
+#include "print.h"
+
+/* Demo specific constants. */
+#define evtSTACK_SIZE		( ( unsigned portBASE_TYPE ) configMINIMAL_STACK_SIZE )
+#define evtNUM_TASKS		( 4 )
+#define evtQUEUE_LENGTH		( ( unsigned portBASE_TYPE ) 3 )
+#define evtNO_DELAY						0
+
+/* Just indexes used to uniquely identify the tasks.  Note that two tasks are
+'highest' priority. */
+#define evtHIGHEST_PRIORITY_INDEX_2		3
+#define evtHIGHEST_PRIORITY_INDEX_1		2
+#define evtMEDIUM_PRIORITY_INDEX		1
+#define evtLOWEST_PRIORITY_INDEX		0
+
+/* Each event task increments one of these counters each time it reads data
+from the queue. */
+static volatile portBASE_TYPE xTaskCounters[ evtNUM_TASKS ] = { 0, 0, 0, 0 };
+
+/* Each time the controlling task posts onto the queue it increments the 
+expected count of the task that it expected to read the data from the queue 
+(i.e. the task with the highest priority that should be blocked on the queue).  
+
+xExpectedTaskCounters are incremented from the controlling task, and 
+xTaskCounters are incremented from the individual event tasks - therefore
+comparing xTaskCounters to xExpectedTaskCounters shows whether or not the 
+correct task was unblocked by the post. */
+static portBASE_TYPE xExpectedTaskCounters[ evtNUM_TASKS ] = { 0, 0, 0, 0 };
+
+/* Handles to the four event tasks.  These are required to suspend and resume
+the tasks. */
+static TaskHandle_t xCreatedTasks[ evtNUM_TASKS ];
+
+/* The single queue onto which the controlling task posts, and the four event
+tasks block. */
+static QueueHandle_t xQueue;
+
+/* Flag used to indicate whether or not an error has occurred at any time.
+An error is either the queue being full when not expected, or an unexpected
+task reading data from the queue. */
+static portBASE_TYPE xHealthStatus = pdPASS;
+
+/*-----------------------------------------------------------*/
+
+/* Function that implements the event task.  This is created four times. */
+static void prvMultiEventTask( void *pvParameters );
+
+/* Function that implements the controlling task. */
+static void prvEventControllerTask( void *pvParameters );
+
+/* This is a utility function that posts data to the queue, then compares 
+xExpectedTaskCounters with xTaskCounters to ensure everything worked as 
+expected.
+
+The event tasks all have higher priorities the controlling task.  Therefore
+the controlling task will always get preempted between writhing to the queue
+and checking the task counters. 
+
+@param xExpectedTask  The index to the task that the controlling task thinks
+                      should be the highest priority task waiting for data, and
+					  therefore the task that will unblock.
+					  
+@param	xIncrement    The number of items that should be written to the queue.
+*/
+static void prvCheckTaskCounters( portBASE_TYPE xExpectedTask, portBASE_TYPE xIncrement );
+
+/* This is just incremented each cycle of the controlling tasks function so
+the main application can ensure the test is still running. */
+static portBASE_TYPE xCheckVariable = 0;
+
+/*-----------------------------------------------------------*/
+
+void vStartMultiEventTasks( void )
+{
+	/* Create the queue to be used for all the communications. */
+	xQueue = xQueueCreate( evtQUEUE_LENGTH, ( unsigned portBASE_TYPE ) sizeof( unsigned portBASE_TYPE ) );
+
+	/* Start the controlling task.  This has the idle priority to ensure it is
+	always preempted by the event tasks. */
+	xTaskCreate( prvEventControllerTask, "EvntCTRL", evtSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	/* Start the four event tasks.  Note that two have priority 3, one 
+	priority 2 and the other priority 1. */
+	xTaskCreate( prvMultiEventTask, "Event0", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 0 ] ), 1, &( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ) );
+	xTaskCreate( prvMultiEventTask, "Event1", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 1 ] ), 2, &( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ) );
+	xTaskCreate( prvMultiEventTask, "Event2", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 2 ] ), 3, &( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ) );
+	xTaskCreate( prvMultiEventTask, "Event3", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 3 ] ), 3, &( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] ) );
+}
+/*-----------------------------------------------------------*/
+
+static void prvMultiEventTask( void *pvParameters )
+{
+portBASE_TYPE *pxCounter;
+unsigned portBASE_TYPE uxDummy;
+const char * const pcTaskStartMsg = "Multi event task started.\r\n";
+
+	/* The variable this task will increment is passed in as a parameter. */
+	pxCounter = ( portBASE_TYPE * ) pvParameters;
+
+	vPrintDisplayMessage( &pcTaskStartMsg );
+
+	for( ;; )
+	{
+		/* Block on the queue. */
+		if( xQueueReceive( xQueue, &uxDummy, portMAX_DELAY ) )
+		{
+			/* We unblocked by reading the queue - so simply increment
+			the counter specific to this task instance. */
+			( *pxCounter )++;
+		}
+		else
+		{
+			xHealthStatus = pdFAIL;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvEventControllerTask( void *pvParameters )
+{
+const char * const pcTaskStartMsg = "Multi event controller task started.\r\n";
+portBASE_TYPE xDummy = 0;
+
+	/* Just to stop warnings. */
+	( void ) pvParameters;
+
+	vPrintDisplayMessage( &pcTaskStartMsg );
+
+	for( ;; )
+	{
+		/* All tasks are blocked on the queue.  When a message is posted one of
+		the two tasks that share the highest priority should unblock to read
+		the queue.  The next message written should unblock the other task with
+		the same high priority, and so on in order.   No other task should 
+		unblock to read data as they have lower priorities. */
+
+		prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
+		prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_2, 1 );
+		prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
+		prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_2, 1 );
+		prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
+
+		/* For the rest of these tests we don't need the second 'highest' 
+		priority task - so it is suspended. */
+		vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] );
+
+
+
+		/* Now suspend the other highest priority task.  The medium priority 
+		task will then be the task with the highest priority that remains 
+		blocked on the queue. */
+		vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
+		
+		/* This time, when we post onto the queue we will expect the medium
+		priority task to unblock and preempt us. */
+		prvCheckTaskCounters( evtMEDIUM_PRIORITY_INDEX, 1 );
+
+		/* Now try resuming the highest priority task while the scheduler is
+		suspended.  The task should start executing as soon as the scheduler
+		is resumed - therefore when we post to the queue again, the highest
+		priority task should again preempt us. */
+		vTaskSuspendAll();
+			vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
+		xTaskResumeAll();
+		prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
+		
+		/* Now we are going to suspend the high and medium priority tasks.  The
+		low priority task should then preempt us.  Again the task suspension is 
+		done with the whole scheduler suspended just for test purposes. */
+		vTaskSuspendAll();
+			vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
+			vTaskSuspend( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] );
+		xTaskResumeAll();
+		prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, 1 );
+		
+		/* Do the same basic test another few times - selectively suspending
+		and resuming tasks and each time calling prvCheckTaskCounters() passing
+		to the function the number of the task we expected to be unblocked by 
+		the	post. */
+
+		vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
+		prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
+		
+		vTaskSuspendAll(); /* Just for test. */
+			vTaskSuspendAll(); /* Just for test. */
+				vTaskSuspendAll(); /* Just for even more test. */
+					vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
+				xTaskResumeAll();
+			xTaskResumeAll();
+		xTaskResumeAll();
+		prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, 1 );
+		
+		vTaskResume( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] );
+		prvCheckTaskCounters( evtMEDIUM_PRIORITY_INDEX, 1 );
+		
+		vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
+		prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
+
+		/* Now a slight change, first suspend all tasks. */
+		vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
+		vTaskSuspend( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] );
+		vTaskSuspend( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] );
+		
+		/* Now when we resume the low priority task and write to the queue 3 
+		times.  We expect the low priority task to service the queue three
+		times. */
+		vTaskResume( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] );
+		prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, evtQUEUE_LENGTH );
+		
+		/* Again suspend all tasks (only the low priority task is not suspended
+		already). */
+		vTaskSuspend( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] );
+		
+		/* This time we are going to suspend the scheduler, resume the low
+		priority task, then resume the high priority task.  In this state we
+		will write to the queue three times.  When the scheduler is resumed
+		we expect the high priority task to service all three messages. */
+		vTaskSuspendAll();
+		{
+			vTaskResume( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] );
+			vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
+			
+			for( xDummy = 0; xDummy < evtQUEUE_LENGTH; xDummy++ )
+			{
+				if( xQueueSend( xQueue, &xDummy, evtNO_DELAY ) != pdTRUE )
+				{
+					xHealthStatus = pdFAIL;
+				}
+			}			
+			
+			/* The queue should not have been serviced yet!.  The scheduler
+			is still suspended. */
+			if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) )
+			{
+				xHealthStatus = pdFAIL;
+			}
+		}
+		xTaskResumeAll();
+
+		/* We should have been preempted by resuming the scheduler - so by the
+		time we are running again we expect the high priority task to have 
+		removed three items from the queue. */
+		xExpectedTaskCounters[ evtHIGHEST_PRIORITY_INDEX_1 ] += evtQUEUE_LENGTH;
+		if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) )
+		{
+			xHealthStatus = pdFAIL;
+		}
+		
+		/* The medium priority and second high priority tasks are still 
+		suspended.  Make sure to resume them before starting again. */
+		vTaskResume( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] );
+		vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] );
+
+		/* Just keep incrementing to show the task is still executing. */
+		xCheckVariable++;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTaskCounters( portBASE_TYPE xExpectedTask, portBASE_TYPE xIncrement )
+{
+portBASE_TYPE xDummy = 0;
+
+	/* Write to the queue the requested number of times.  The data written is
+	not important. */
+	for( xDummy = 0; xDummy < xIncrement; xDummy++ )
+	{
+		if( xQueueSend( xQueue, &xDummy, evtNO_DELAY ) != pdTRUE )
+		{
+			/* Did not expect to ever find the queue full. */
+			xHealthStatus = pdFAIL;
+		}
+	}
+
+	/* All the tasks blocked on the queue have a priority higher than the 
+	controlling task.  Writing to the queue will therefore have caused this
+	task to be preempted.  By the time this line executes the event task will
+	have executed and incremented its counter.  Increment the expected counter
+	to the same value. */
+	( xExpectedTaskCounters[ xExpectedTask ] ) += xIncrement;
+
+	/* Check the actual counts and expected counts really are the same. */
+	if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) )
+	{
+		/* The counters were not the same.  This means a task we did not expect
+		to unblock actually did unblock. */
+		xHealthStatus = pdFAIL;
+	}
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xAreMultiEventTasksStillRunning( void )
+{
+static portBASE_TYPE xPreviousCheckVariable = 0;
+
+	/* Called externally to periodically check that this test is still
+	operational. */
+
+	if( xPreviousCheckVariable == xCheckVariable )
+	{
+		xHealthStatus = pdFAIL;
+	}
+	
+	xPreviousCheckVariable = xCheckVariable;
+	
+	return xHealthStatus;	
+}
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/flash.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/flash.c
new file mode 100644
index 0000000..1a56a69
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/flash.c
@@ -0,0 +1,128 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/**
+ * Creates eight tasks, each of which flash an LED at a different rate.  The first 
+ * LED flashes every 125ms, the second every 250ms, the third every 375ms, etc.
+ *
+ * The LED flash tasks provide instant visual feedback.  They show that the scheduler 
+ * is still operational.
+ *
+ * The PC port uses the standard parallel port for outputs, the Flashlite 186 port 
+ * uses IO port F.
+ *
+ * \page flashC flash.c
+ * \ingroup DemoFiles
+ * 

+ */
+
+/*
+Changes from V2.0.0
+
+	+ Delay periods are now specified using variables and constants of
+	  TickType_t rather than unsigned long.
+
+Changes from V2.1.1
+
+	+ The stack size now uses configMINIMAL_STACK_SIZE.
+	+ String constants made file scope to decrease stack depth on 8051 port.
+*/
+
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo program include files. */
+#include "partest.h"
+#include "flash.h"
+#include "print.h"
+
+#define ledSTACK_SIZE		configMINIMAL_STACK_SIZE
+
+/* Structure used to pass parameters to the LED tasks. */
+typedef struct LED_PARAMETERS
+{
+	unsigned portBASE_TYPE uxLED;		/*< The output the task should use. */
+	TickType_t xFlashRate;	/*< The rate at which the LED should flash. */
+} xLEDParameters;
+
+/* The task that is created eight times - each time with a different xLEDParaemtes 
+structure passed in as the parameter. */
+static void vLEDFlashTask( void *pvParameters );
+
+/* String to print if USE_STDIO is defined. */
+const char * const pcTaskStartMsg = "LED flash task started.\r\n";
+
+/*-----------------------------------------------------------*/
+
+void vStartLEDFlashTasks( unsigned portBASE_TYPE uxPriority )
+{
+unsigned portBASE_TYPE uxLEDTask;
+xLEDParameters *pxLEDParameters;
+const unsigned portBASE_TYPE uxNumOfLEDs = 8;
+const TickType_t xFlashRate = 125;
+
+	/* Create the eight tasks. */
+	for( uxLEDTask = 0; uxLEDTask < uxNumOfLEDs; ++uxLEDTask )
+	{
+		/* Create and complete the structure used to pass parameters to the next 
+		created task. */
+		pxLEDParameters = ( xLEDParameters * ) pvPortMalloc( sizeof( xLEDParameters ) );
+		pxLEDParameters->uxLED = uxLEDTask;
+		pxLEDParameters->xFlashRate = ( xFlashRate + ( xFlashRate * ( TickType_t ) uxLEDTask ) );
+		pxLEDParameters->xFlashRate /= portTICK_PERIOD_MS;
+
+		/* Spawn the task. */
+		xTaskCreate( vLEDFlashTask, "LEDx", ledSTACK_SIZE, ( void * ) pxLEDParameters, uxPriority, ( TaskHandle_t * ) NULL );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void vLEDFlashTask( void *pvParameters )
+{
+xLEDParameters *pxParameters;
+
+	/* Queue a message for printing to say the task has started. */
+	vPrintDisplayMessage( &pcTaskStartMsg );
+
+	pxParameters = ( xLEDParameters * ) pvParameters;
+
+	for(;;)
+	{
+		/* Delay for half the flash period then turn the LED on. */
+		vTaskDelay( pxParameters->xFlashRate / ( TickType_t ) 2 );
+		vParTestToggleLED( pxParameters->uxLED );
+
+		/* Delay for half the flash period then turn the LED off. */
+		vTaskDelay( pxParameters->xFlashRate / ( TickType_t ) 2 );
+		vParTestToggleLED( pxParameters->uxLED );
+	}
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/flop.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/flop.c
new file mode 100644
index 0000000..b1c6b13
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/flop.c
@@ -0,0 +1,331 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V1.2.3
+	
+	+ The created tasks now include calls to tskYIELD(), allowing them to be used
+	  with the cooperative scheduler.
+*/
+
+/**
+ * Creates eight tasks, each of which loops continuously performing an (emulated) 
+ * floating point calculation.
+ *
+ * All the tasks run at the idle priority and never block or yield.  This causes 
+ * all eight tasks to time slice with the idle task.  Running at the idle priority 
+ * means that these tasks will get pre-empted any time another task is ready to run
+ * or a time slice occurs.  More often than not the pre-emption will occur mid 
+ * calculation, creating a good test of the schedulers context switch mechanism - a 
+ * calculation producing an unexpected result could be a symptom of a corruption in 
+ * the context of a task.
+ *
+ * \page FlopC flop.c
+ * \ingroup DemoFiles
+ * 

+ */
+
+#include 
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "print.h"
+
+/* Demo program include files. */
+#include "flop.h"
+
+#define mathSTACK_SIZE		( ( unsigned short ) 512 )
+#define mathNUMBER_OF_TASKS  ( 8 )
+
+/* Four tasks, each of which performs a different floating point calculation.  
+Each of the four is created twice. */
+static void vCompetingMathTask1( void *pvParameters );
+static void vCompetingMathTask2( void *pvParameters );
+static void vCompetingMathTask3( void *pvParameters );
+static void vCompetingMathTask4( void *pvParameters );
+
+/* These variables are used to check that all the tasks are still running.  If a 
+task gets a calculation wrong it will
+stop incrementing its check variable. */
+static volatile unsigned short usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned short ) 0 };
+
+/*-----------------------------------------------------------*/
+
+void vStartMathTasks( unsigned portBASE_TYPE uxPriority )
+{
+	xTaskCreate( vCompetingMathTask1, "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL );
+	xTaskCreate( vCompetingMathTask2, "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL );
+	xTaskCreate( vCompetingMathTask3, "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL );
+	xTaskCreate( vCompetingMathTask4, "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL );
+	xTaskCreate( vCompetingMathTask1, "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL );
+	xTaskCreate( vCompetingMathTask2, "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL );
+	xTaskCreate( vCompetingMathTask3, "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL );
+	xTaskCreate( vCompetingMathTask4, "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void vCompetingMathTask1( void *pvParameters )
+{
+portDOUBLE d1, d2, d3, d4;
+volatile unsigned short *pusTaskCheckVariable;
+const portDOUBLE dAnswer = ( 123.4567 + 2345.6789 ) * -918.222;
+const char * const pcTaskStartMsg = "Math task 1 started.\r\n";
+const char * const pcTaskFailMsg = "Math task 1 failed.\r\n";
+short sError = pdFALSE;
+
+	/* Queue a message for printing to say the task has started. */
+	vPrintDisplayMessage( &pcTaskStartMsg );
+
+	/* The variable this task increments to show it is still running is passed in 
+	as the parameter. */
+	pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+	/* Keep performing a calculation and checking the result against a constant. */
+	for(;;)
+	{
+		d1 = 123.4567;
+		d2 = 2345.6789;
+		d3 = -918.222;
+
+		d4 = ( d1 + d2 ) * d3;
+
+		taskYIELD();
+
+		/* If the calculation does not match the expected constant, stop the 
+		increment of the check variable. */
+		if( fabs( d4 - dAnswer ) > 0.001 )
+		{
+			vPrintDisplayMessage( &pcTaskFailMsg );
+			sError = pdTRUE;
+		}
+
+		if( sError == pdFALSE )
+		{
+			/* If the calculation has always been correct, increment the check 
+			variable so we know this task is still running okay. */
+			( *pusTaskCheckVariable )++;
+		}
+
+		taskYIELD();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void vCompetingMathTask2( void *pvParameters )
+{
+portDOUBLE d1, d2, d3, d4;
+volatile unsigned short *pusTaskCheckVariable;
+const portDOUBLE dAnswer = ( -389.38 / 32498.2 ) * -2.0001;
+const char * const pcTaskStartMsg = "Math task 2 started.\r\n";
+const char * const pcTaskFailMsg = "Math task 2 failed.\r\n";
+short sError = pdFALSE;
+
+	/* Queue a message for printing to say the task has started. */
+	vPrintDisplayMessage( &pcTaskStartMsg );
+
+	/* The variable this task increments to show it is still running is passed in 
+	as the parameter. */
+	pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+	/* Keep performing a calculation and checking the result against a constant. */
+	for( ;; )
+	{
+		d1 = -389.38;
+		d2 = 32498.2;
+		d3 = -2.0001;
+
+		d4 = ( d1 / d2 ) * d3;
+
+		taskYIELD();
+		
+		/* If the calculation does not match the expected constant, stop the 
+		increment of the check variable. */
+		if( fabs( d4 - dAnswer ) > 0.001 )
+		{
+			vPrintDisplayMessage( &pcTaskFailMsg );
+			sError = pdTRUE;
+		}
+
+		if( sError == pdFALSE )
+		{
+			/* If the calculation has always been correct, increment the check 
+			variable so we know
+			this task is still running okay. */
+			( *pusTaskCheckVariable )++;
+		}
+
+		taskYIELD();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void vCompetingMathTask3( void *pvParameters )
+{
+portDOUBLE *pdArray, dTotal1, dTotal2, dDifference;
+volatile unsigned short *pusTaskCheckVariable;
+const unsigned short usArraySize = 250;
+unsigned short usPosition;
+const char * const pcTaskStartMsg = "Math task 3 started.\r\n";
+const char * const pcTaskFailMsg = "Math task 3 failed.\r\n";
+short sError = pdFALSE;
+
+	/* Queue a message for printing to say the task has started. */
+	vPrintDisplayMessage( &pcTaskStartMsg );
+
+	/* The variable this task increments to show it is still running is passed in 
+	as the parameter. */
+	pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+	pdArray = ( portDOUBLE * ) pvPortMalloc( ( size_t ) 250 * sizeof( portDOUBLE ) );
+
+	/* Keep filling an array, keeping a running total of the values placed in the 
+	array.  Then run through the array adding up all the values.  If the two totals 
+	do not match, stop the check variable from incrementing. */
+	for( ;; )
+	{
+		dTotal1 = 0.0;
+		dTotal2 = 0.0;
+
+		for( usPosition = 0; usPosition < usArraySize; usPosition++ )
+		{
+			pdArray[ usPosition ] = ( portDOUBLE ) usPosition + 5.5;
+			dTotal1 += ( portDOUBLE ) usPosition + 5.5;	
+		}
+
+		taskYIELD();
+
+		for( usPosition = 0; usPosition < usArraySize; usPosition++ )
+		{
+			dTotal2 += pdArray[ usPosition ];
+		}
+
+		dDifference = dTotal1 - dTotal2;
+		if( fabs( dDifference ) > 0.001 )
+		{
+			vPrintDisplayMessage( &pcTaskFailMsg );
+			sError = pdTRUE;
+		}
+
+		taskYIELD();
+
+		if( sError == pdFALSE )
+		{
+			/* If the calculation has always been correct, increment the check 
+			variable so we know	this task is still running okay. */
+			( *pusTaskCheckVariable )++;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void vCompetingMathTask4( void *pvParameters )
+{
+portDOUBLE *pdArray, dTotal1, dTotal2, dDifference;
+volatile unsigned short *pusTaskCheckVariable;
+const unsigned short usArraySize = 250;
+unsigned short usPosition;
+const char * const pcTaskStartMsg = "Math task 4 started.\r\n";
+const char * const pcTaskFailMsg = "Math task 4 failed.\r\n";
+short sError = pdFALSE;
+
+	/* Queue a message for printing to say the task has started. */
+	vPrintDisplayMessage( &pcTaskStartMsg );
+
+	/* The variable this task increments to show it is still running is passed in 
+	as the parameter. */
+	pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+	pdArray = ( portDOUBLE * ) pvPortMalloc( ( size_t ) 250 * sizeof( portDOUBLE ) );
+
+	/* Keep filling an array, keeping a running total of the values placed in the 
+	array.  Then run through the array adding up all the values.  If the two totals 
+	do not match, stop the check variable from incrementing. */
+	for( ;; )
+	{
+		dTotal1 = 0.0;
+		dTotal2 = 0.0;
+
+		for( usPosition = 0; usPosition < usArraySize; usPosition++ )
+		{
+			pdArray[ usPosition ] = ( portDOUBLE ) usPosition * 12.123;
+			dTotal1 += ( portDOUBLE ) usPosition * 12.123;	
+		}
+
+		taskYIELD();
+
+		for( usPosition = 0; usPosition < usArraySize; usPosition++ )
+		{
+			dTotal2 += pdArray[ usPosition ];
+		}
+
+		dDifference = dTotal1 - dTotal2;
+		if( fabs( dDifference ) > 0.001 )
+		{
+			vPrintDisplayMessage( &pcTaskFailMsg );
+			sError = pdTRUE;
+		}
+
+		taskYIELD();
+
+		if( sError == pdFALSE )
+		{
+			/* If the calculation has always been correct, increment the check 
+			variable so we know	this task is still running okay. */
+			( *pusTaskCheckVariable )++;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* This is called to check that all the created tasks are still running. */
+portBASE_TYPE xAreMathsTaskStillRunning( void )
+{
+/* Keep a history of the check variables so we know if they have been incremented 
+since the last call. */
+static unsigned short usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned short ) 0 };
+portBASE_TYPE xReturn = pdTRUE, xTask;
+
+	/* Check the maths tasks are still running by ensuring their check variables 
+	are still incrementing. */
+	for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ )
+	{
+		if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] )
+		{
+			/* The check has not incremented so an error exists. */
+			xReturn = pdFALSE;
+		}
+
+		usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ];
+	}
+
+	return xReturn;
+}
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/integer.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/integer.c
new file mode 100644
index 0000000..cc77878
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/integer.c
@@ -0,0 +1,327 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V1.2.3
+	
+	+ The created tasks now include calls to tskYIELD(), allowing them to be used
+	  with the cooperative scheduler.
+*/
+
+/**
+ * This does the same as flop. c, but uses variables of type long instead of 
+ * type double.  
+ *
+ * As with flop. c, the tasks created in this file are a good test of the 
+ * scheduler context switch mechanism.  The processor has to access 32bit 
+ * variables in two or four chunks (depending on the processor).  The low 
+ * priority of these tasks means there is a high probability that a context 
+ * switch will occur mid calculation.  See the flop. c documentation for 
+ * more information.
+ *
+ * \page IntegerC integer.c
+ * \ingroup DemoFiles
+ * 

+ */
+
+/*
+Changes from V1.2.1
+
+	+ The constants used in the calculations are larger to ensure the
+	  optimiser does not truncate them to 16 bits.
+*/
+
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "print.h"
+
+/* Demo program include files. */
+#include "integer.h"
+
+#define intgSTACK_SIZE		( ( unsigned short ) 256 )
+#define intgNUMBER_OF_TASKS  ( 8 )
+
+/* Four tasks, each of which performs a different calculation on four byte 
+variables.  Each of the four is created twice. */
+static void vCompeteingIntMathTask1( void *pvParameters );
+static void vCompeteingIntMathTask2( void *pvParameters );
+static void vCompeteingIntMathTask3( void *pvParameters );
+static void vCompeteingIntMathTask4( void *pvParameters );
+
+/* These variables are used to check that all the tasks are still running.  If a 
+task gets a calculation wrong it will stop incrementing its check variable. */
+static volatile unsigned short usTaskCheck[ intgNUMBER_OF_TASKS ] = { ( unsigned short ) 0 };
+/*-----------------------------------------------------------*/
+
+void vStartIntegerMathTasks( unsigned portBASE_TYPE uxPriority )
+{
+	xTaskCreate( vCompeteingIntMathTask1, "IntMath1", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL );
+	xTaskCreate( vCompeteingIntMathTask2, "IntMath2", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL );
+	xTaskCreate( vCompeteingIntMathTask3, "IntMath3", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL );
+	xTaskCreate( vCompeteingIntMathTask4, "IntMath4", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL );
+	xTaskCreate( vCompeteingIntMathTask1, "IntMath5", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL );
+	xTaskCreate( vCompeteingIntMathTask2, "IntMath6", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL );
+	xTaskCreate( vCompeteingIntMathTask3, "IntMath7", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL );
+	xTaskCreate( vCompeteingIntMathTask4, "IntMath8", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void vCompeteingIntMathTask1( void *pvParameters )
+{
+long l1, l2, l3, l4;
+short sError = pdFALSE;
+volatile unsigned short *pusTaskCheckVariable;
+const long lAnswer = ( ( long ) 74565L + ( long ) 1234567L ) * ( long ) -918L;
+const char * const pcTaskStartMsg = "Integer math task 1 started.\r\n";
+const char * const pcTaskFailMsg = "Integer math task 1 failed.\r\n";
+
+	/* Queue a message for printing to say the task has started. */
+	vPrintDisplayMessage( &pcTaskStartMsg );
+
+	/* The variable this task increments to show it is still running is passed in
+	as the parameter. */
+	pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+	/* Keep performing a calculation and checking the result against a constant. */
+	for(;;)
+	{
+		l1 = ( long ) 74565L;
+		l2 = ( long ) 1234567L;
+		l3 = ( long ) -918L;
+
+		l4 = ( l1 + l2 ) * l3;
+
+		taskYIELD();
+
+		/* If the calculation does not match the expected constant, stop the
+		increment of the check variable. */
+		if( l4 != lAnswer )
+		{
+			vPrintDisplayMessage( &pcTaskFailMsg );
+			sError = pdTRUE;
+		}
+
+		if( sError == pdFALSE )
+		{
+			/* If the calculation has always been correct, increment the check
+			variable so we know	this task is still running okay. */
+			( *pusTaskCheckVariable )++;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void vCompeteingIntMathTask2( void *pvParameters )
+{
+long l1, l2, l3, l4;
+short sError = pdFALSE;
+volatile unsigned short *pusTaskCheckVariable;
+const long lAnswer = ( ( long ) -389000L / ( long ) 329999L ) * ( long ) -89L;
+const char * const pcTaskStartMsg = "Integer math task 2 started.\r\n";
+const char * const pcTaskFailMsg = "Integer math task 2 failed.\r\n";
+
+	/* Queue a message for printing to say the task has started. */
+	vPrintDisplayMessage( &pcTaskStartMsg );
+
+	/* The variable this task increments to show it is still running is passed in
+	as the parameter. */
+	pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+	/* Keep performing a calculation and checking the result against a constant. */
+	for( ;; )
+	{
+		l1 = -389000L;
+		l2 = 329999L;
+		l3 = -89L;
+
+		l4 = ( l1 / l2 ) * l3;
+
+		taskYIELD();
+
+		/* If the calculation does not match the expected constant, stop the
+		increment of the check variable. */
+		if( l4 != lAnswer )
+		{
+			vPrintDisplayMessage( &pcTaskFailMsg );
+			sError = pdTRUE;
+		}
+
+		if( sError == pdFALSE )
+		{
+			/* If the calculation has always been correct, increment the check
+			variable so we know this task is still running okay. */
+			( *pusTaskCheckVariable )++;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void vCompeteingIntMathTask3( void *pvParameters )
+{
+long *plArray, lTotal1, lTotal2;
+short sError = pdFALSE;
+volatile unsigned short *pusTaskCheckVariable;
+const unsigned short usArraySize = ( unsigned short ) 250;
+unsigned short usPosition;
+const char * const pcTaskStartMsg = "Integer math task 3 started.\r\n";
+const char * const pcTaskFailMsg = "Integer math task 3 failed.\r\n";
+
+	/* Queue a message for printing to say the task has started. */
+	vPrintDisplayMessage( &pcTaskStartMsg );
+
+	/* The variable this task increments to show it is still running is passed in
+	as the parameter. */
+	pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+	/* Create the array we are going to use for our check calculation. */
+	plArray = ( long * ) pvPortMalloc( ( size_t ) 250 * sizeof( long ) );
+
+	/* Keep filling the array, keeping a running total of the values placed in the
+	array.  Then run through the array adding up all the values.  If the two totals
+	do not match, stop the check variable from incrementing. */
+	for( ;; )
+	{
+		lTotal1 = ( long ) 0;
+		lTotal2 = ( long ) 0;
+
+		for( usPosition = 0; usPosition < usArraySize; usPosition++ )
+		{
+			plArray[ usPosition ] = ( long ) usPosition + ( long ) 5;
+			lTotal1 += ( long ) usPosition + ( long ) 5;
+		}
+
+		taskYIELD();
+
+		for( usPosition = 0; usPosition < usArraySize; usPosition++ )
+		{
+			lTotal2 += plArray[ usPosition ];
+		}
+
+		if( lTotal1 != lTotal2 )
+		{
+			vPrintDisplayMessage( &pcTaskFailMsg );
+			sError = pdTRUE;
+		}
+
+		taskYIELD();
+
+		if( sError == pdFALSE )
+		{
+			/* If the calculation has always been correct, increment the check
+			variable so we know	this task is still running okay. */
+			( *pusTaskCheckVariable )++;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void vCompeteingIntMathTask4( void *pvParameters )
+{
+long *plArray, lTotal1, lTotal2;
+short sError = pdFALSE;
+volatile unsigned short *pusTaskCheckVariable;
+const unsigned short usArraySize = 250;
+unsigned short usPosition;
+const char * const pcTaskStartMsg = "Integer math task 4 started.\r\n";
+const char * const pcTaskFailMsg = "Integer math task 4 failed.\r\n";
+
+	/* Queue a message for printing to say the task has started. */
+	vPrintDisplayMessage( &pcTaskStartMsg );
+
+	/* The variable this task increments to show it is still running is passed in
+	as the parameter. */
+	pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+	/* Create the array we are going to use for our check calculation. */
+	plArray = ( long * ) pvPortMalloc( ( size_t ) 250 * sizeof( long ) );
+
+	/* Keep filling the array, keeping a running total of the values placed in the 
+	array.  Then run through the array adding up all the values.  If the two totals 
+	do not match, stop the check variable from incrementing. */
+	for( ;; )
+	{
+		lTotal1 = ( long ) 0;
+		lTotal2 = ( long ) 0;
+
+		for( usPosition = 0; usPosition < usArraySize; usPosition++ )
+		{
+			plArray[ usPosition ] = ( long ) usPosition * ( long ) 12;
+			lTotal1 += ( long ) usPosition * ( long ) 12;	
+		}
+
+		taskYIELD();
+	
+		for( usPosition = 0; usPosition < usArraySize; usPosition++ )
+		{
+			lTotal2 += plArray[ usPosition ];
+		}
+
+
+		if( lTotal1 != lTotal2 )
+		{
+			vPrintDisplayMessage( &pcTaskFailMsg );
+			sError = pdTRUE;
+		}
+
+		taskYIELD();
+
+		if( sError == pdFALSE )
+		{
+			/* If the calculation has always been correct, increment the check 
+			variable so we know	this task is still running okay. */
+			( *pusTaskCheckVariable )++;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* This is called to check that all the created tasks are still running. */
+portBASE_TYPE xAreIntegerMathsTaskStillRunning( void )
+{
+/* Keep a history of the check variables so we know if they have been incremented 
+since the last call. */
+static unsigned short usLastTaskCheck[ intgNUMBER_OF_TASKS ] = { ( unsigned short ) 0 };
+portBASE_TYPE xReturn = pdTRUE, xTask;
+
+	/* Check the maths tasks are still running by ensuring their check variables 
+	are still incrementing. */
+	for( xTask = 0; xTask < intgNUMBER_OF_TASKS; xTask++ )
+	{
+		if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] )
+		{
+			/* The check has not incremented so an error exists. */
+			xReturn = pdFALSE;
+		}
+
+		usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ];
+	}
+
+	return xReturn;
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/print.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/print.c
new file mode 100644
index 0000000..787609f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/print.c
@@ -0,0 +1,106 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/**
+ * Manages a queue of strings that are waiting to be displayed.  This is used to 
+ * ensure mutual exclusion of console output.
+ *
+ * A task wishing to display a message will call vPrintDisplayMessage (), with a 
+ * pointer to the string as the parameter. The pointer is posted onto the 
+ * xPrintQueue queue.
+ *
+ * The task spawned in main. c blocks on xPrintQueue.  When a message becomes 
+ * available it calls pcPrintGetNextMessage () to obtain a pointer to the next 
+ * string, then uses the functions defined in the portable layer FileIO. c to 
+ * display the message.
+ *
+ * NOTE:
+ * Using console IO can disrupt real time performance - depending on the port.  
+ * Standard C IO routines are not designed for real time applications.  While 
+ * standard IO is useful for demonstration and debugging an alternative method 
+ * should be used if you actually require console IO as part of your application.
+ *
+ * \page PrintC print.c
+ * \ingroup DemoFiles
+ * 

+ */
+
+/*
+Changes from V2.0.0
+
+	+ Delay periods are now specified using variables and constants of
+	  TickType_t rather than unsigned long.
+*/
+
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "queue.h"
+
+/* Demo program include files. */
+#include "print.h"
+
+static QueueHandle_t xPrintQueue;
+
+/*-----------------------------------------------------------*/
+
+void vPrintInitialise( void )
+{
+const unsigned portBASE_TYPE uxQueueSize = 20;
+
+	/* Create the queue on which errors will be reported. */
+	xPrintQueue = xQueueCreate( uxQueueSize, ( unsigned portBASE_TYPE ) sizeof( char * ) );
+}
+/*-----------------------------------------------------------*/
+
+void vPrintDisplayMessage( const char * const * ppcMessageToSend )
+{
+	#ifdef USE_STDIO
+		xQueueSend( xPrintQueue, ( void * ) ppcMessageToSend, ( TickType_t ) 0 );
+	#else
+    	/* Stop warnings. */
+		( void ) ppcMessageToSend;
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+const char *pcPrintGetNextMessage( TickType_t xPrintRate )
+{
+char *pcMessage;
+
+	if( xQueueReceive( xPrintQueue, &pcMessage, xPrintRate ) == pdPASS )
+	{
+		return pcMessage;
+	}
+	else
+	{
+		return NULL;
+	}
+}
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/semtest.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/semtest.c
new file mode 100644
index 0000000..382bf2a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Full/semtest.c
@@ -0,0 +1,285 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/**
+ * Creates two sets of two tasks.  The tasks within a set share a variable, access 
+ * to which is guarded by a semaphore.
+ * 
+ * Each task starts by attempting to obtain the semaphore.  On obtaining a 
+ * semaphore a task checks to ensure that the guarded variable has an expected 
+ * value.  It then clears the variable to zero before counting it back up to the 
+ * expected value in increments of 1.  After each increment the variable is checked 
+ * to ensure it contains the value to which it was just set. When the starting 
+ * value is again reached the task releases the semaphore giving the other task in 
+ * the set a chance to do exactly the same thing.  The starting value is high 
+ * enough to ensure that a tick is likely to occur during the incrementing loop.
+ *
+ * An error is flagged if at any time during the process a shared variable is 
+ * found to have a value other than that expected.  Such an occurrence would 
+ * suggest an error in the mutual exclusion mechanism by which access to the 
+ * variable is restricted.
+ *
+ * The first set of two tasks poll their semaphore.  The second set use blocking 
+ * calls.
+ *
+ * \page SemTestC semtest.c
+ * \ingroup DemoFiles
+ * 

+ */
+
+/*
+Changes from V1.2.0:
+
+	+ The tasks that operate at the idle priority now use a lower expected
+	  count than those running at a higher priority.  This prevents the low
+	  priority tasks from signaling an error because they have not been 
+	  scheduled enough time for each of them to count the shared variable to
+	  the high value.
+
+Changes from V2.0.0
+
+	+ Delay periods are now specified using variables and constants of
+	  TickType_t rather than unsigned long.
+
+Changes from V2.1.1
+
+	+ The stack size now uses configMINIMAL_STACK_SIZE.
+	+ String constants made file scope to decrease stack depth on 8051 port.
+*/
+
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+
+/* Demo app include files. */
+#include "semtest.h"
+#include "print.h"
+
+/* The value to which the shared variables are counted. */
+#define semtstBLOCKING_EXPECTED_VALUE		( ( unsigned long ) 0xfff )
+#define semtstNON_BLOCKING_EXPECTED_VALUE	( ( unsigned long ) 0xff  )
+
+#define semtstSTACK_SIZE			configMINIMAL_STACK_SIZE
+
+#define semtstNUM_TASKS				( 4 )
+
+#define semtstDELAY_FACTOR			( ( TickType_t ) 10 )
+
+/* The task function as described at the top of the file. */
+static void prvSemaphoreTest( void *pvParameters );
+
+/* Structure used to pass parameters to each task. */
+typedef struct SEMAPHORE_PARAMETERS
+{
+	SemaphoreHandle_t xSemaphore;
+	volatile unsigned long *pulSharedVariable;
+	TickType_t xBlockTime;
+} xSemaphoreParameters;
+
+/* Variables used to check that all the tasks are still running without errors. */
+static volatile short sCheckVariables[ semtstNUM_TASKS ] = { 0 };
+static volatile short sNextCheckVariable = 0;
+
+/* Strings to print if USE_STDIO is defined. */
+const char * const pcPollingSemaphoreTaskError = "Guarded shared variable in unexpected state.\r\n";
+const char * const pcSemaphoreTaskStart = "Guarded shared variable task started.\r\n";
+
+/*-----------------------------------------------------------*/
+
+void vStartSemaphoreTasks( unsigned portBASE_TYPE uxPriority )
+{
+xSemaphoreParameters *pxFirstSemaphoreParameters, *pxSecondSemaphoreParameters;
+const TickType_t xBlockTime = ( TickType_t ) 100;
+
+	/* Create the structure used to pass parameters to the first two tasks. */
+	pxFirstSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) );
+
+	if( pxFirstSemaphoreParameters != NULL )
+	{
+		/* Create the semaphore used by the first two tasks. */
+		vSemaphoreCreateBinary( pxFirstSemaphoreParameters->xSemaphore );
+
+		if( pxFirstSemaphoreParameters->xSemaphore != NULL )
+		{
+			/* Create the variable which is to be shared by the first two tasks. */
+			pxFirstSemaphoreParameters->pulSharedVariable = ( unsigned long * ) pvPortMalloc( sizeof( unsigned long ) );
+
+			/* Initialise the share variable to the value the tasks expect. */
+			*( pxFirstSemaphoreParameters->pulSharedVariable ) = semtstNON_BLOCKING_EXPECTED_VALUE;
+
+			/* The first two tasks do not block on semaphore calls. */
+			pxFirstSemaphoreParameters->xBlockTime = ( TickType_t ) 0;
+
+			/* Spawn the first two tasks.  As they poll they operate at the idle priority. */
+			xTaskCreate( prvSemaphoreTest, "PolSEM1", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( TaskHandle_t * ) NULL );
+			xTaskCreate( prvSemaphoreTest, "PolSEM2", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( TaskHandle_t * ) NULL );
+		}
+	}
+
+	/* Do exactly the same to create the second set of tasks, only this time 
+	provide a block time for the semaphore calls. */
+	pxSecondSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) );
+	if( pxSecondSemaphoreParameters != NULL )
+	{
+		vSemaphoreCreateBinary( pxSecondSemaphoreParameters->xSemaphore );
+
+		if( pxSecondSemaphoreParameters->xSemaphore != NULL )
+		{
+			pxSecondSemaphoreParameters->pulSharedVariable = ( unsigned long * ) pvPortMalloc( sizeof( unsigned long ) );
+			*( pxSecondSemaphoreParameters->pulSharedVariable ) = semtstBLOCKING_EXPECTED_VALUE;
+			pxSecondSemaphoreParameters->xBlockTime = xBlockTime / portTICK_PERIOD_MS;
+
+			xTaskCreate( prvSemaphoreTest, "BlkSEM1", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( TaskHandle_t * ) NULL );
+			xTaskCreate( prvSemaphoreTest, "BlkSEM2", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( TaskHandle_t * ) NULL );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSemaphoreTest( void *pvParameters )
+{
+xSemaphoreParameters *pxParameters;
+volatile unsigned long *pulSharedVariable, ulExpectedValue;
+unsigned long ulCounter;
+short sError = pdFALSE, sCheckVariableToUse;
+
+	/* See which check variable to use.  sNextCheckVariable is not semaphore 
+	protected! */
+	portENTER_CRITICAL();
+		sCheckVariableToUse = sNextCheckVariable;
+		sNextCheckVariable++;
+	portEXIT_CRITICAL();
+
+	/* Queue a message for printing to say the task has started. */
+	vPrintDisplayMessage( &pcSemaphoreTaskStart );
+
+	/* A structure is passed in as the parameter.  This contains the shared 
+	variable being guarded. */
+	pxParameters = ( xSemaphoreParameters * ) pvParameters;
+	pulSharedVariable = pxParameters->pulSharedVariable;
+
+	/* If we are blocking we use a much higher count to ensure loads of context
+	switches occur during the count. */
+	if( pxParameters->xBlockTime > ( TickType_t ) 0 )
+	{
+		ulExpectedValue = semtstBLOCKING_EXPECTED_VALUE;
+	}
+	else
+	{
+		ulExpectedValue = semtstNON_BLOCKING_EXPECTED_VALUE;
+	}
+
+	for( ;; )
+	{
+		/* Try to obtain the semaphore. */
+		if( xSemaphoreTake( pxParameters->xSemaphore, pxParameters->xBlockTime ) == pdPASS )
+		{
+			/* We have the semaphore and so expect any other tasks using the
+			shared variable to have left it in the state we expect to find
+			it. */
+			if( *pulSharedVariable != ulExpectedValue )
+			{
+				vPrintDisplayMessage( &pcPollingSemaphoreTaskError );
+				sError = pdTRUE;
+			}
+			
+			/* Clear the variable, then count it back up to the expected value
+			before releasing the semaphore.  Would expect a context switch or
+			two during this time. */
+			for( ulCounter = ( unsigned long ) 0; ulCounter <= ulExpectedValue; ulCounter++ )
+			{
+				*pulSharedVariable = ulCounter;
+				if( *pulSharedVariable != ulCounter )
+				{
+					if( sError == pdFALSE )
+					{
+						vPrintDisplayMessage( &pcPollingSemaphoreTaskError );
+					}
+					sError = pdTRUE;
+				}
+			}
+
+			/* Release the semaphore, and if no errors have occurred increment the check
+			variable. */
+			if(	xSemaphoreGive( pxParameters->xSemaphore ) == pdFALSE )
+			{
+				vPrintDisplayMessage( &pcPollingSemaphoreTaskError );
+				sError = pdTRUE;
+			}
+
+			if( sError == pdFALSE )
+			{
+				if( sCheckVariableToUse < semtstNUM_TASKS )
+				{
+					( sCheckVariables[ sCheckVariableToUse ] )++;
+				}
+			}
+
+			/* If we have a block time then we are running at a priority higher
+			than the idle priority.  This task takes a long time to complete
+			a cycle	(deliberately so to test the guarding) so will be starving
+			out lower priority tasks.  Block for some time to allow give lower
+			priority tasks some processor time. */
+			vTaskDelay( pxParameters->xBlockTime * semtstDELAY_FACTOR );
+		}
+		else
+		{
+			if( pxParameters->xBlockTime == ( TickType_t ) 0 )
+			{
+				/* We have not got the semaphore yet, so no point using the
+				processor.  We are not blocking when attempting to obtain the
+				semaphore. */
+				taskYIELD();
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* This is called to check that all the created tasks are still running. */
+portBASE_TYPE xAreSemaphoreTasksStillRunning( void )
+{
+static short sLastCheckVariables[ semtstNUM_TASKS ] = { 0 };
+portBASE_TYPE xTask, xReturn = pdTRUE;
+
+	for( xTask = 0; xTask < semtstNUM_TASKS; xTask++ )
+	{
+		if( sLastCheckVariables[ xTask ] == sCheckVariables[ xTask ] )
+		{
+			xReturn = pdFALSE;
+		}
+
+		sLastCheckVariables[ xTask ] = sCheckVariables[ xTask ];
+	}
+
+	return xReturn;
+}
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/AbortDelay.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/AbortDelay.c
new file mode 100644
index 0000000..27d41c7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/AbortDelay.c
@@ -0,0 +1,720 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * This file contains some test scenarios that ensure tasks respond correctly
+ * to xTaskAbortDelay() calls.  It also ensures tasks return the correct state
+ * of eBlocked when blocked indefinitely in both the case where a task is
+ * blocked on an object and when a task is blocked on a notification.
+ */
+
+/* Standard includes. */
+#include "limits.h"
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+#include "event_groups.h"
+#include "stream_buffer.h"
+
+/* Demo includes. */
+#include "AbortDelay.h"
+
+/* This file can only be used if the functionality it tests is included in the
+build.  Remove the whole file if this is not the case. */
+#if( INCLUDE_xTaskAbortDelay == 1 )
+
+#if( INCLUDE_xTaskGetHandle != 1 )
+	#error This test file uses the xTaskGetHandle() API function so INCLUDE_xTaskGetHandle must be set to 1 in FreeRTOSConfig.h.
+#endif
+
+/* Task priorities.  Allow these to be overridden. */
+#ifndef abtCONTROLLING_PRIORITY
+	#define abtCONTROLLING_PRIORITY		( configMAX_PRIORITIES - 3 )
+#endif
+
+#ifndef abtBLOCKING_PRIORITY
+	#define abtBLOCKING_PRIORITY	( configMAX_PRIORITIES - 2 )
+#endif
+
+/* The tests that are performed. */
+#define abtNOTIFY_WAIT_ABORTS		0
+#define abtNOTIFY_TAKE_ABORTS		1
+#define abtDELAY_ABORTS				2
+#define abtDELAY_UNTIL_ABORTS		3
+#define abtSEMAPHORE_TAKE_ABORTS	4
+#define abtEVENT_GROUP_ABORTS		5
+#define abtQUEUE_SEND_ABORTS		6
+#define abtSTREAM_BUFFER_RECEIVE	7
+#define abtMAX_TESTS				8
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The two test tasks.  The controlling task specifies which test to executed.
+ * More information is provided in the comments within the tasks.
+ */
+static void prvControllingTask( void *pvParameters );
+static void prvBlockingTask( void *pvParameters );
+
+/*
+ * Test functions called by the blocking task.  Each function follows the same
+ * pattern, but the way the task blocks is different in each case.
+ *
+ * In each function three blocking calls are made.  The first and third
+ * blocking call is expected to time out, while the middle blocking call is
+ * expected to be aborted by the controlling task half way through the block
+ * time.
+ */
+static void prvTestAbortingTaskNotifyWait( void );
+static void prvTestAbortingTaskNotifyTake( void );
+static void prvTestAbortingTaskDelay( void );
+static void prvTestAbortingTaskDelayUntil( void );
+static void prvTestAbortingSemaphoreTake( void );
+static void prvTestAbortingEventGroupWait( void );
+static void prvTestAbortingQueueSend( void );
+static void prvTestAbortingStreamBufferReceive( void );
+
+/*
+ * Checks the amount of time a task spent in the Blocked state is within the
+ * expected bounds.
+ */
+static void prvCheckExpectedTimeIsWithinAnAcceptableMargin( TickType_t xStartTime, TickType_t xExpectedBlockTime );
+
+/*-----------------------------------------------------------*/
+
+/* Used to ensure that tasks are still executing without error. */
+static volatile BaseType_t xControllingCycles = 0, xBlockingCycles = 0;
+static volatile BaseType_t xErrorOccurred = pdFALSE;
+
+/* Each task needs to know the other tasks handle so they can send signals to
+each other.  The handle is obtained from the task's name. */
+static const char *pcControllingTaskName = "AbtCtrl", *pcBlockingTaskName = "AbtBlk";
+
+/* The maximum amount of time a task will block for. */
+const TickType_t xMaxBlockTime = pdMS_TO_TICKS( 100 );
+const TickType_t xHalfMaxBlockTime = pdMS_TO_TICKS( 50 );
+
+/* The actual block time is dependent on the priority of other tasks in the
+system so the actual block time might be greater than that expected, but it
+should be within an acceptable upper bound. */
+const TickType_t xAllowableMargin = pdMS_TO_TICKS( 7 );
+
+/*-----------------------------------------------------------*/
+
+void vCreateAbortDelayTasks( void )
+{
+	/* Create the two test tasks described above. */
+	xTaskCreate( prvControllingTask, pcControllingTaskName, configMINIMAL_STACK_SIZE, NULL, abtCONTROLLING_PRIORITY, NULL );
+	xTaskCreate( prvBlockingTask, pcBlockingTaskName, configMINIMAL_STACK_SIZE, NULL, abtBLOCKING_PRIORITY, NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvControllingTask( void *pvParameters )
+{
+TaskHandle_t xBlockingTask;
+uint32_t ulTestToPerform = abtNOTIFY_WAIT_ABORTS;
+TickType_t xTimeAtStart;
+const TickType_t xStartMargin = 2UL;
+
+	/* Just to remove compiler warnings. */
+	( void ) pvParameters;
+
+	xBlockingTask = xTaskGetHandle( pcBlockingTaskName );
+	configASSERT( xBlockingTask );
+
+	for( ;; )
+	{
+		/* Tell the secondary task to perform the next test. */
+		xTimeAtStart = xTaskGetTickCount();
+		xTaskNotify( xBlockingTask, ulTestToPerform, eSetValueWithOverwrite );
+
+		/* The secondary task has a higher priority, so will now be in the
+		Blocked state to wait for a maximum of xMaxBlockTime.  It expects that
+		period to complete with a timeout.  It will then block for
+		xMaxBlockTimeAgain, but this time it expects to the block time to abort
+		half way through.  Block until it is time to send the abort to the
+		secondary task.  xStartMargin is used because this task takes timing
+		from the beginning of the test, whereas the blocking task takes timing
+		from the entry into the Blocked state - and as the tasks run at
+		different priorities, there may be some discrepancy.  Also, temporarily
+		raise the priority of the controlling task to that of the blocking
+		task to minimise discrepancies. */
+		vTaskPrioritySet( NULL, abtBLOCKING_PRIORITY );
+		vTaskDelay( xMaxBlockTime + xHalfMaxBlockTime + xStartMargin );
+		if( xTaskAbortDelay( xBlockingTask ) != pdPASS )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+
+		/* Reset the priority to the normal controlling priority. */
+		vTaskPrioritySet( NULL, abtCONTROLLING_PRIORITY );
+
+		/* Now wait to be notified that the secondary task has completed its
+		test. */
+		ulTaskNotifyTake( pdTRUE, portMAX_DELAY );
+
+		/* Did the entire test run for the expected time, which is two full
+		block times plus the half block time caused by calling
+		xTaskAbortDelay()? */
+		prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, ( xMaxBlockTime + xMaxBlockTime + xHalfMaxBlockTime ) );
+
+		/* Move onto the next test. */
+		ulTestToPerform++;
+
+		if( ulTestToPerform >= abtMAX_TESTS )
+		{
+			ulTestToPerform = 0;
+		}
+
+		/* To indicate this task is still executing. */
+		xControllingCycles++;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvBlockingTask( void *pvParameters )
+{
+TaskHandle_t xControllingTask;
+uint32_t ulNotificationValue;
+const uint32_t ulMax = 0xffffffffUL;
+
+	/* Just to remove compiler warnings. */
+	( void ) pvParameters;
+
+	xControllingTask = xTaskGetHandle( pcControllingTaskName );
+	configASSERT( xControllingTask );
+
+	for( ;; )
+	{
+		/* Wait to be notified of the test that is to be performed next. */
+		xTaskNotifyWait( 0, ulMax, &ulNotificationValue, portMAX_DELAY );
+
+		switch( ulNotificationValue )
+		{
+			case abtNOTIFY_WAIT_ABORTS:
+				prvTestAbortingTaskNotifyWait();
+				break;
+
+			case abtNOTIFY_TAKE_ABORTS:
+				prvTestAbortingTaskNotifyTake();
+				break;
+
+			case abtDELAY_ABORTS:
+				prvTestAbortingTaskDelay();
+				break;
+
+			case abtDELAY_UNTIL_ABORTS:
+				prvTestAbortingTaskDelayUntil();
+				break;
+
+			case abtSEMAPHORE_TAKE_ABORTS:
+				prvTestAbortingSemaphoreTake();
+				break;
+
+			case abtEVENT_GROUP_ABORTS:
+				prvTestAbortingEventGroupWait();
+				break;
+
+			case abtQUEUE_SEND_ABORTS:
+				prvTestAbortingQueueSend();
+				break;
+
+			case abtSTREAM_BUFFER_RECEIVE:
+				prvTestAbortingStreamBufferReceive();
+				break;
+
+			default:
+				/* Should not get here. */
+				break;
+		}
+
+		/* Let the primary task know the test is complete. */
+		xTaskNotifyGive( xControllingTask );
+
+		/* To indicate this task is still executing. */
+		xBlockingCycles++;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvTestAbortingTaskDelayUntil( void )
+{
+TickType_t xTimeAtStart, xLastBlockTime;
+
+	/* Note the time before the delay so the length of the delay is known. */
+	xTimeAtStart = xTaskGetTickCount();
+
+	/* Take a copy of the time as it is updated in the call to
+	vTaskDelayUntil() but its original value is needed to determine the actual
+	time spend in the Blocked state. */
+	xLastBlockTime = xTimeAtStart;
+
+	/* This first delay should just time out. */
+	vTaskDelayUntil( &xLastBlockTime, xMaxBlockTime );
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+
+	/* This second delay should be aborted by the primary task half way
+	through.  Again take a copy of the time as it is updated in the call to
+	vTaskDelayUntil() buts its original value is needed to determine the amount
+	of time actually spent in the Blocked state. */
+	xTimeAtStart = xTaskGetTickCount();
+	xLastBlockTime = xTimeAtStart;
+	vTaskDelayUntil( &xLastBlockTime, xMaxBlockTime );
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
+
+	/* As with the other tests, the third block period should not time out. */
+	xTimeAtStart = xTaskGetTickCount();
+	xLastBlockTime = xTimeAtStart;
+	vTaskDelayUntil( &xLastBlockTime, xMaxBlockTime );
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+}
+/*-----------------------------------------------------------*/
+
+static void prvTestAbortingTaskDelay( void )
+{
+TickType_t xTimeAtStart;
+
+	/* Note the time before the delay so the length of the delay is known. */
+	xTimeAtStart = xTaskGetTickCount();
+
+	/* This first delay should just time out. */
+	vTaskDelay( xMaxBlockTime );
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+
+	/* Note the time before the delay so the length of the delay is known. */
+	xTimeAtStart = xTaskGetTickCount();
+
+	/* This second delay should be aborted by the primary task half way
+	through. */
+	vTaskDelay( xMaxBlockTime );
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
+
+	/* Note the time before the delay so the length of the delay is known. */
+	xTimeAtStart = xTaskGetTickCount();
+
+	/* This third delay should just time out again. */
+	vTaskDelay( xMaxBlockTime );
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+}
+/*-----------------------------------------------------------*/
+
+static void prvTestAbortingTaskNotifyTake( void )
+{
+TickType_t xTimeAtStart;
+uint32_t ulReturn;
+
+	/* Note the time before the delay so the length of the delay is known. */
+	xTimeAtStart = xTaskGetTickCount();
+
+	/* This first delay should just time out. */
+	ulReturn = ulTaskNotifyTake( pdFALSE, xMaxBlockTime );
+	if( ulReturn != 0 )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+
+	/* Note the time before the delay so the length of the delay is known. */
+	xTimeAtStart = xTaskGetTickCount();
+
+	/* This second delay should be aborted by the primary task half way
+	through. */
+	ulReturn = ulTaskNotifyTake( pdFALSE, xMaxBlockTime );
+	if( ulReturn != 0 )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
+
+	/* Note the time before the delay so the length of the delay is known. */
+	xTimeAtStart = xTaskGetTickCount();
+
+	/* This third delay should just time out again. */
+	ulReturn = ulTaskNotifyTake( pdFALSE, xMaxBlockTime );
+	if( ulReturn != 0 )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+}
+/*-----------------------------------------------------------*/
+
+static void prvTestAbortingEventGroupWait( void )
+{
+TickType_t xTimeAtStart;
+EventGroupHandle_t xEventGroup;
+EventBits_t xBitsToWaitFor = ( EventBits_t ) 0x01, xReturn;
+
+	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	{
+		static StaticEventGroup_t xEventGroupBuffer;
+
+		/* Create the event group.  Statically allocated memory is used so the
+		creation cannot fail. */
+		xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
+	}
+	#else
+	{
+		xEventGroup = xEventGroupCreate();
+		configASSERT( xEventGroup );
+	}
+	#endif
+
+	/* Note the time before the delay so the length of the delay is known. */
+	xTimeAtStart = xTaskGetTickCount();
+
+	/* This first delay should just time out. */
+	xReturn = xEventGroupWaitBits( xEventGroup, xBitsToWaitFor, pdTRUE, pdTRUE, xMaxBlockTime );
+	if( xReturn != 0x00 )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+
+	/* Note the time before the delay so the length of the delay is known. */
+	xTimeAtStart = xTaskGetTickCount();
+
+	/* This second delay should be aborted by the primary task half way
+	through. */
+	xReturn = xEventGroupWaitBits( xEventGroup, xBitsToWaitFor, pdTRUE, pdTRUE, xMaxBlockTime );
+	if( xReturn != 0x00 )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
+
+	/* Note the time before the delay so the length of the delay is known. */
+	xTimeAtStart = xTaskGetTickCount();
+
+	/* This third delay should just time out again. */
+	xReturn = xEventGroupWaitBits( xEventGroup, xBitsToWaitFor, pdTRUE, pdTRUE, xMaxBlockTime );
+	if( xReturn != 0x00 )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+
+	/* Not really necessary in this case, but for completeness. */
+	vEventGroupDelete( xEventGroup );
+}
+/*-----------------------------------------------------------*/
+
+static void prvTestAbortingStreamBufferReceive( void )
+{
+TickType_t xTimeAtStart;
+StreamBufferHandle_t xStreamBuffer;
+EventBits_t xReturn;
+const size_t xTriggerLevelBytes = ( size_t ) 1;
+uint8_t uxRxData;
+
+	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	{
+		/* Defines the memory that will actually hold the streams within the
+		stream buffer. */
+		static uint8_t ucStorageBuffer[ sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) + 1 ];
+
+		/* The variable used to hold the stream buffer structure. */
+		StaticStreamBuffer_t xStreamBufferStruct;
+
+
+		xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucStorageBuffer ),
+												   xTriggerLevelBytes,
+												   ucStorageBuffer,
+												   &xStreamBufferStruct );
+	}
+	#else
+	{
+		xStreamBuffer = xStreamBufferCreate( sizeof( uint8_t ), xTriggerLevelBytes );
+		configASSERT( xStreamBuffer );
+	}
+	#endif
+
+	/* Note the time before the delay so the length of the delay is known. */
+	xTimeAtStart = xTaskGetTickCount();
+
+	/* This first delay should just time out. */
+	xReturn = xStreamBufferReceive( xStreamBuffer, &uxRxData, sizeof( uxRxData ), xMaxBlockTime );
+	if( xReturn != 0x00 )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+
+	/* Note the time before the delay so the length of the delay is known. */
+	xTimeAtStart = xTaskGetTickCount();
+
+	/* This second delay should be aborted by the primary task half way
+	through xMaxBlockTime. */
+	xReturn = xStreamBufferReceive( xStreamBuffer, &uxRxData, sizeof( uxRxData ), xMaxBlockTime );
+	if( xReturn != 0x00 )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
+
+	/* Note the time before the delay so the length of the delay is known. */
+	xTimeAtStart = xTaskGetTickCount();
+
+	/* This third delay should just time out again. */
+	xReturn = xStreamBufferReceive( xStreamBuffer, &uxRxData, sizeof( uxRxData ), xMaxBlockTime );
+	if( xReturn != 0x00 )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+
+	/* Not really necessary in this case, but for completeness. */
+	vStreamBufferDelete( xStreamBuffer );
+}
+/*-----------------------------------------------------------*/
+
+static void prvTestAbortingQueueSend( void )
+{
+TickType_t xTimeAtStart;
+BaseType_t xReturn;
+const UBaseType_t xQueueLength = ( UBaseType_t ) 1;
+QueueHandle_t xQueue;
+uint8_t ucItemToQueue;
+
+	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	{
+		static StaticQueue_t xQueueBuffer;
+		static uint8_t ucQueueStorage[ sizeof( uint8_t ) ];
+
+		/* Create the queue.  Statically allocated memory is used so the
+		creation cannot fail. */
+		xQueue = xQueueCreateStatic( xQueueLength, sizeof( uint8_t ), ucQueueStorage, &xQueueBuffer );
+	}
+	#else
+	{
+		xQueue = xQueueCreate( xQueueLength, sizeof( uint8_t ) );
+		configASSERT( xQueue );
+	}
+	#endif
+
+	/* This function tests aborting when in the blocked state waiting to send,
+	so the queue must be full.  There is only one space in the queue. */
+	xReturn = xQueueSend( xQueue, &ucItemToQueue, xMaxBlockTime );
+	if( xReturn != pdPASS )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+
+	/* Note the time before the delay so the length of the delay is known. */
+	xTimeAtStart = xTaskGetTickCount();
+
+	/* This first delay should just time out. */
+	xReturn = xQueueSend( xQueue, &ucItemToQueue, xMaxBlockTime );
+	if( xReturn != pdFALSE )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+
+	/* Note the time before the delay so the length of the delay is known. */
+	xTimeAtStart = xTaskGetTickCount();
+
+	/* This second delay should be aborted by the primary task half way
+	through. */
+	xReturn = xQueueSend( xQueue, &ucItemToQueue, xMaxBlockTime );
+	if( xReturn != pdFALSE )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
+
+	/* Note the time before the delay so the length of the delay is known. */
+	xTimeAtStart = xTaskGetTickCount();
+
+	/* This third delay should just time out again. */
+	xReturn = xQueueSend( xQueue, &ucItemToQueue, xMaxBlockTime );
+	if( xReturn != pdFALSE )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+
+	/* Not really necessary in this case, but for completeness. */
+	vQueueDelete( xQueue );
+}
+/*-----------------------------------------------------------*/
+
+static void prvTestAbortingSemaphoreTake( void )
+{
+TickType_t xTimeAtStart;
+BaseType_t xReturn;
+SemaphoreHandle_t xSemaphore;
+
+	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	{
+		static StaticSemaphore_t xSemaphoreBuffer;
+
+		/* Create the semaphore.  Statically allocated memory is used so the
+		creation cannot fail. */
+		xSemaphore = xSemaphoreCreateBinaryStatic( &xSemaphoreBuffer );
+	}
+	#else
+	{
+		xSemaphore = xSemaphoreCreateBinary();
+	}
+	#endif
+
+	/* Note the time before the delay so the length of the delay is known. */
+	xTimeAtStart = xTaskGetTickCount();
+
+	/* This first delay should just time out. */
+	xReturn = xSemaphoreTake( xSemaphore, xMaxBlockTime );
+	if( xReturn != pdFALSE )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+
+	/* Note the time before the delay so the length of the delay is known. */
+	xTimeAtStart = xTaskGetTickCount();
+
+	/* This second delay should be aborted by the primary task half way
+	through xMaxBlockTime. */
+	xReturn = xSemaphoreTake( xSemaphore, portMAX_DELAY );
+	if( xReturn != pdFALSE )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
+
+	/* Note the time before the delay so the length of the delay is known. */
+	xTimeAtStart = xTaskGetTickCount();
+
+	/* This third delay should just time out again. */
+	xReturn = xSemaphoreTake( xSemaphore, xMaxBlockTime );
+	if( xReturn != pdFALSE )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+
+	/* Not really necessary in this case, but for completeness. */
+	vSemaphoreDelete( xSemaphore );
+}
+/*-----------------------------------------------------------*/
+
+static void prvTestAbortingTaskNotifyWait( void )
+{
+TickType_t xTimeAtStart;
+BaseType_t xReturn;
+
+	/* Note the time before the delay so the length of the delay is known. */
+	xTimeAtStart = xTaskGetTickCount();
+
+	/* This first delay should just time out. */
+	xReturn = xTaskNotifyWait( 0, 0, NULL, xMaxBlockTime );
+	if( xReturn != pdFALSE )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+
+	/* Note the time before the delay so the length of the delay is known. */
+	xTimeAtStart = xTaskGetTickCount();
+
+	/* This second delay should be aborted by the primary task half way
+	through xMaxBlockTime. */
+	xReturn = xTaskNotifyWait( 0, 0, NULL, portMAX_DELAY );
+	if( xReturn != pdFALSE )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
+
+	/* Note the time before the delay so the length of the delay is known. */
+	xTimeAtStart = xTaskGetTickCount();
+
+	/* This third delay should just time out again. */
+	xReturn = xTaskNotifyWait( 0, 0, NULL, xMaxBlockTime );
+	if( xReturn != pdFALSE )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+	prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckExpectedTimeIsWithinAnAcceptableMargin( TickType_t xStartTime, TickType_t xExpectedBlockTime )
+{
+TickType_t xTimeNow, xActualBlockTime;
+
+	xTimeNow = xTaskGetTickCount();
+	xActualBlockTime = xTimeNow - xStartTime;
+
+	/* The actual block time should not be less than the expected block time. */
+	if( xActualBlockTime < xExpectedBlockTime )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+
+	/* The actual block time can be greater than the expected block time, as it
+	depends on the priority of the other tasks, but it should be within an
+	acceptable margin. */
+	if( xActualBlockTime > ( xExpectedBlockTime + xAllowableMargin ) )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xAreAbortDelayTestTasksStillRunning( void )
+{
+static BaseType_t xLastControllingCycleCount = 0, xLastBlockingCycleCount = 0;
+BaseType_t xReturn = pdPASS;
+
+	/* Have both tasks performed at least one cycle since this function was
+	last called? */
+	if( xControllingCycles == xLastControllingCycleCount )
+	{
+		xReturn = pdFAIL;
+	}
+
+	if( xBlockingCycles == xLastBlockingCycleCount )
+	{
+		xReturn = pdFAIL;
+	}
+
+	if( xErrorOccurred == pdTRUE )
+	{
+		xReturn = pdFAIL;
+	}
+
+	xLastBlockingCycleCount = xBlockingCycles;
+	xLastControllingCycleCount = xControllingCycles;
+
+	return xReturn;
+}
+
+#endif /* INCLUDE_xTaskAbortDelay == 1 */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/BlockQ.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/BlockQ.c
new file mode 100644
index 0000000..9660786
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/BlockQ.c
@@ -0,0 +1,290 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Creates six tasks that operate on three queues as follows:
+ *
+ * The first two tasks send and receive an incrementing number to/from a queue.
+ * One task acts as a producer and the other as the consumer.  The consumer is a
+ * higher priority than the producer and is set to block on queue reads.  The queue
+ * only has space for one item - as soon as the producer posts a message on the
+ * queue the consumer will unblock, pre-empt the producer, and remove the item.
+ *
+ * The second two tasks work the other way around.  Again the queue used only has
+ * enough space for one item.  This time the consumer has a lower priority than the
+ * producer.  The producer will try to post on the queue blocking when the queue is
+ * full.  When the consumer wakes it will remove the item from the queue, causing
+ * the producer to unblock, pre-empt the consumer, and immediately re-fill the
+ * queue.
+ *
+ * The last two tasks use the same queue producer and consumer functions.  This time the queue has
+ * enough space for lots of items and the tasks operate at the same priority.  The
+ * producer will execute, placing items into the queue.  The consumer will start
+ * executing when either the queue becomes full (causing the producer to block) or
+ * a context switch occurs (tasks of the same priority will time slice).
+ *
+ */
+
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* Demo program include files. */
+#include "BlockQ.h"
+
+#define blckqSTACK_SIZE		configMINIMAL_STACK_SIZE
+#define blckqNUM_TASK_SETS	( 3 )
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+	#error This example cannot be used if dynamic allocation is not allowed.
+#endif
+
+/* Structure used to pass parameters to the blocking queue tasks. */
+typedef struct BLOCKING_QUEUE_PARAMETERS
+{
+	QueueHandle_t xQueue;					/*< The queue to be used by the task. */
+	TickType_t xBlockTime;				/*< The block time to use on queue reads/writes. */
+	volatile short *psCheckVariable;	/*< Incremented on each successful cycle to check the task is still running. */
+} xBlockingQueueParameters;
+
+/* Task function that creates an incrementing number and posts it on a queue. */
+static portTASK_FUNCTION_PROTO( vBlockingQueueProducer, pvParameters );
+
+/* Task function that removes the incrementing number from a queue and checks that
+it is the expected number. */
+static portTASK_FUNCTION_PROTO( vBlockingQueueConsumer, pvParameters );
+
+/* Variables which are incremented each time an item is removed from a queue, and
+found to be the expected value.
+These are used to check that the tasks are still running. */
+static volatile short sBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( uint16_t ) 0, ( uint16_t ) 0, ( uint16_t ) 0 };
+
+/* Variable which are incremented each time an item is posted on a queue.   These
+are used to check that the tasks are still running. */
+static volatile short sBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( uint16_t ) 0, ( uint16_t ) 0, ( uint16_t ) 0 };
+
+/*-----------------------------------------------------------*/
+
+void vStartBlockingQueueTasks( UBaseType_t uxPriority )
+{
+xBlockingQueueParameters *pxQueueParameters1, *pxQueueParameters2;
+xBlockingQueueParameters *pxQueueParameters3, *pxQueueParameters4;
+xBlockingQueueParameters *pxQueueParameters5, *pxQueueParameters6;
+const UBaseType_t uxQueueSize1 = 1, uxQueueSize5 = 5;
+const TickType_t xBlockTime = pdMS_TO_TICKS( ( TickType_t ) 1000 );
+const TickType_t xDontBlock = ( TickType_t ) 0;
+
+	/* Create the first two tasks as described at the top of the file. */
+
+	/* First create the structure used to pass parameters to the consumer tasks. */
+	pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+
+	/* Create the queue used by the first two tasks to pass the incrementing number.
+	Pass a pointer to the queue in the parameter structure. */
+	pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( UBaseType_t ) sizeof( uint16_t ) );
+
+	/* The consumer is created first so gets a block time as described above. */
+	pxQueueParameters1->xBlockTime = xBlockTime;
+
+	/* Pass in the variable that this task is going to increment so we can check it
+	is still running. */
+	pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] );
+
+	/* Create the structure used to pass parameters to the producer task. */
+	pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+
+	/* Pass the queue to this task also, using the parameter structure. */
+	pxQueueParameters2->xQueue = pxQueueParameters1->xQueue;
+
+	/* The producer is not going to block - as soon as it posts the consumer will
+	wake and remove the item so the producer should always have room to post. */
+	pxQueueParameters2->xBlockTime = xDontBlock;
+
+	/* Pass in the variable that this task is going to increment so we can check
+	it is still running. */
+	pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] );
+
+
+	/* Note the producer has a lower priority than the consumer when the tasks are
+	spawned. */
+	xTaskCreate( vBlockingQueueConsumer, "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL );
+	xTaskCreate( vBlockingQueueProducer, "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL );
+
+
+
+	/* Create the second two tasks as described at the top of the file.   This uses
+	the same mechanism but reverses the task priorities. */
+
+	pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+	pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( UBaseType_t ) sizeof( uint16_t ) );
+	pxQueueParameters3->xBlockTime = xDontBlock;
+	pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] );
+
+	pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+	pxQueueParameters4->xQueue = pxQueueParameters3->xQueue;
+	pxQueueParameters4->xBlockTime = xBlockTime;
+	pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] );
+
+	xTaskCreate( vBlockingQueueConsumer, "QConsB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL );
+	xTaskCreate( vBlockingQueueProducer, "QProdB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL );
+
+
+
+	/* Create the last two tasks as described above.  The mechanism is again just
+	the same.  This time both parameter structures are given a block time. */
+	pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+	pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( UBaseType_t ) sizeof( uint16_t ) );
+	pxQueueParameters5->xBlockTime = xBlockTime;
+	pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] );
+
+	pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+	pxQueueParameters6->xQueue = pxQueueParameters5->xQueue;
+	pxQueueParameters6->xBlockTime = xBlockTime;
+	pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] );
+
+	xTaskCreate( vBlockingQueueProducer, "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL );
+	xTaskCreate( vBlockingQueueConsumer, "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL );
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vBlockingQueueProducer, pvParameters )
+{
+uint16_t usValue = 0;
+xBlockingQueueParameters *pxQueueParameters;
+short sErrorEverOccurred = pdFALSE;
+
+	pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;
+
+	for( ;; )
+	{
+		if( xQueueSend( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS )
+		{
+			sErrorEverOccurred = pdTRUE;
+		}
+		else
+		{
+			/* We have successfully posted a message, so increment the variable
+			used to check we are still running. */
+			if( sErrorEverOccurred == pdFALSE )
+			{
+				( *pxQueueParameters->psCheckVariable )++;
+			}
+
+			/* Increment the variable we are going to post next time round.  The
+			consumer will expect the numbers to	follow in numerical order. */
+			++usValue;
+
+			#if configUSE_PREEMPTION == 0
+				taskYIELD();
+			#endif
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vBlockingQueueConsumer, pvParameters )
+{
+uint16_t usData, usExpectedValue = 0;
+xBlockingQueueParameters *pxQueueParameters;
+short sErrorEverOccurred = pdFALSE;
+
+	pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;
+
+	for( ;; )
+	{
+		if( xQueueReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS )
+		{
+			if( usData != usExpectedValue )
+			{
+				/* Catch-up. */
+				usExpectedValue = usData;
+
+				sErrorEverOccurred = pdTRUE;
+			}
+			else
+			{
+				/* We have successfully received a message, so increment the
+				variable used to check we are still running. */
+				if( sErrorEverOccurred == pdFALSE )
+				{
+					( *pxQueueParameters->psCheckVariable )++;
+				}
+
+				/* Increment the value we expect to remove from the queue next time
+				round. */
+				++usExpectedValue;
+			}
+
+			#if configUSE_PREEMPTION == 0
+			{
+				if( pxQueueParameters->xBlockTime == 0 )
+				{
+					taskYIELD();
+				}
+			}
+			#endif
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* This is called to check that all the created tasks are still running. */
+BaseType_t xAreBlockingQueuesStillRunning( void )
+{
+static short sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( uint16_t ) 0, ( uint16_t ) 0, ( uint16_t ) 0 };
+static short sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( uint16_t ) 0, ( uint16_t ) 0, ( uint16_t ) 0 };
+BaseType_t xReturn = pdPASS, xTasks;
+
+	/* Not too worried about mutual exclusion on these variables as they are 16
+	bits and we are only reading them. We also only care to see if they have
+	changed or not.
+
+	Loop through each check variable to and return pdFALSE if any are found not
+	to have changed since the last call. */
+
+	for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ )
+	{
+		if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ]  )
+		{
+			xReturn = pdFALSE;
+		}
+		sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ];
+
+
+		if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ]  )
+		{
+			xReturn = pdFALSE;
+		}
+		sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ];
+	}
+
+	return xReturn;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/EventGroupsDemo.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/EventGroupsDemo.c
new file mode 100644
index 0000000..8890f4d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/EventGroupsDemo.c
@@ -0,0 +1,1067 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+
+/*
+* This file contains fairly comprehensive checks on the behaviour of event
+* groups.  It is not intended to be a user friendly demonstration of the
+* event groups API.
+*
+* NOTE:  The tests implemented in this file are informal 'sanity' tests
+* only and are not part of the module tests that make use of the
+* mtCOVERAGE_TEST_MARKER macro within the event groups implementation.
+*/
+
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "event_groups.h"
+
+/* Demo app includes. */
+#include "EventGroupsDemo.h"
+
+#if( INCLUDE_eTaskGetState != 1 )
+	#error INCLUDE_eTaskGetState must be set to 1 in FreeRTOSConfig.h to use this demo file.
+#endif
+
+/* Priorities used by the tasks. */
+#define ebSET_BIT_TASK_PRIORITY		( tskIDLE_PRIORITY )
+#define ebWAIT_BIT_TASK_PRIORITY	( tskIDLE_PRIORITY + 1 )
+
+/* Generic bit definitions. */
+#define ebBIT_0		( 0x01 )
+#define ebBIT_1		( 0x02 )
+#define ebBIT_2		( 0x04 )
+#define ebBIT_3		( 0x08 )
+#define ebBIT_4		( 0x10 )
+#define ebBIT_5		( 0x20 )
+#define ebBIT_6		( 0x40 )
+#define ebBIT_7		( 0x80 )
+
+/* Combinations of bits used in the demo. */
+#define ebCOMBINED_BITS ( ebBIT_1 | ebBIT_5 | ebBIT_7 )
+#define ebALL_BITS ( ebBIT_0 | ebBIT_1 | ebBIT_2 | ebBIT_3 | ebBIT_4 | ebBIT_5 | ebBIT_6 | ebBIT_7 )
+
+/* Associate a bit to each task.  These bits are used to identify all the tasks
+that synchronise with the xEventGroupSync() function. */
+#define ebSET_BIT_TASK_SYNC_BIT			ebBIT_0
+#define ebWAIT_BIT_TASK_SYNC_BIT		ebBIT_1
+#define ebRENDESVOUS_TASK_1_SYNC_BIT	ebBIT_2
+#define ebRENDESVOUS_TASK_2_SYNC_BIT	ebBIT_3
+#define ebALL_SYNC_BITS ( ebSET_BIT_TASK_SYNC_BIT | ebWAIT_BIT_TASK_SYNC_BIT | ebRENDESVOUS_TASK_1_SYNC_BIT | ebRENDESVOUS_TASK_2_SYNC_BIT )
+
+/* A block time of zero simply means "don't block". */
+#define ebDONT_BLOCK	( 0 )
+#define ebONE_TICK		( ( TickType_t ) 1 )
+
+/* A 5ms delay. */
+#define ebSHORT_DELAY	pdMS_TO_TICKS( ( TickType_t ) 5 )
+
+/* Used in the selective bits test which checks no, one or both tasks blocked on
+event bits in a group are unblocked as appropriate as different bits get set. */
+#define ebSELECTIVE_BITS_1		0x03
+#define ebSELECTIVE_BITS_2		0x05
+
+#ifndef ebRENDESVOUS_TEST_TASK_STACK_SIZE
+	#define ebRENDESVOUS_TEST_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
+#endif
+
+#ifndef ebEVENT_GROUP_SET_BITS_TEST_TASK_STACK_SIZE
+	#define ebEVENT_GROUP_SET_BITS_TEST_TASK_STACK_SIZE	configMINIMAL_STACK_SIZE
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * NOTE:  The tests implemented in this function are informal 'sanity' tests
+ * only and are not part of the module tests that make use of the
+ * mtCOVERAGE_TEST_MARKER macro within the event groups implementation.
+ *
+ * The master test task.  This task:
+ *
+ * 1) Calls prvSelectiveBitsTestMasterFunction() to test the behaviour when two
+ *    tasks are blocked on different bits in an event group.  The counterpart of
+ *    this test is implemented by the prvSelectiveBitsTestSlaveFunction()
+ *    function (which is called by the two tasks that block on the event group).
+ *
+ * 2) Calls prvBitCombinationTestMasterFunction() to test the behaviour when
+ *    just one task is blocked on various combinations of bits within an event
+ *    group.  The counterpart of this test is implemented within the 'test
+ *    slave' task.
+ *
+ * 3) Calls prvPerformTaskSyncTests() to test task synchronisation behaviour.
+ */
+static void prvTestMasterTask( void *pvParameters );
+
+/*
+ * A helper task that enables the 'test master' task to perform several
+ * behavioural tests.  See the comments above the prvTestMasterTask() prototype
+ * above.
+ */
+static void prvTestSlaveTask( void *pvParameters );
+
+/*
+ * The part of the test that is performed between the 'test master' task and the
+ * 'test slave' task to test the behaviour when the slave blocks on various
+ * event bit combinations.
+ */
+static BaseType_t prvBitCombinationTestMasterFunction( BaseType_t xError, TaskHandle_t xTestSlaveTaskHandle );
+
+/*
+ * The part of the test that uses all the tasks to test the task synchronisation
+ * behaviour.
+ */
+static BaseType_t prvPerformTaskSyncTests( BaseType_t xError, TaskHandle_t xTestSlaveTaskHandle );
+
+/*
+ * Two instances of prvSyncTask() are created.  They start by calling
+ * prvSelectiveBitsTestSlaveFunction() to act as slaves when the test master is
+ * executing the prvSelectiveBitsTestMasterFunction() function.  They then loop
+ * to test the task synchronisation (rendezvous) behaviour.
+ */
+static void prvSyncTask( void *pvParameters );
+
+/*
+ * Functions used in a test that blocks two tasks on various different bits
+ * within an event group - then sets each bit in turn and checks that the
+ * correct tasks unblock at the correct times.
+ */
+static BaseType_t prvSelectiveBitsTestMasterFunction( void );
+static void prvSelectiveBitsTestSlaveFunction( void );
+
+/*-----------------------------------------------------------*/
+
+/* Variables that are incremented by the tasks on each cycle provided no errors
+have been found.  Used to detect an error or stall in the test cycling. */
+static volatile uint32_t ulTestMasterCycles = 0, ulTestSlaveCycles = 0, ulISRCycles = 0;
+
+/* The event group used by all the task based tests. */
+static EventGroupHandle_t xEventGroup = NULL;
+
+/* The event group used by the interrupt based tests. */
+static EventGroupHandle_t xISREventGroup = NULL;
+
+/* Handles to the tasks that only take part in the synchronisation calls. */
+static TaskHandle_t xSyncTask1 = NULL, xSyncTask2 = NULL;
+
+/*-----------------------------------------------------------*/
+
+void vStartEventGroupTasks( void )
+{
+TaskHandle_t xTestSlaveTaskHandle;
+
+	/*
+	 * This file contains fairly comprehensive checks on the behaviour of event
+	 * groups.  It is not intended to be a user friendly demonstration of the
+	 * event groups API.
+	 *
+	 * NOTE:  The tests implemented in this file are informal 'sanity' tests
+	 * only and are not part of the module tests that make use of the
+	 * mtCOVERAGE_TEST_MARKER macro within the event groups implementation.
+	 *
+	 * Create the test tasks as described at the top of this file.
+	 */
+	xTaskCreate( prvTestSlaveTask, "WaitO", ebRENDESVOUS_TEST_TASK_STACK_SIZE, NULL, ebWAIT_BIT_TASK_PRIORITY, &xTestSlaveTaskHandle );
+	xTaskCreate( prvTestMasterTask, "SetB", ebEVENT_GROUP_SET_BITS_TEST_TASK_STACK_SIZE, ( void * ) xTestSlaveTaskHandle, ebSET_BIT_TASK_PRIORITY, NULL );
+	xTaskCreate( prvSyncTask, "Rndv", ebRENDESVOUS_TEST_TASK_STACK_SIZE, ( void * ) ebRENDESVOUS_TASK_1_SYNC_BIT, ebWAIT_BIT_TASK_PRIORITY, &xSyncTask1 );
+	xTaskCreate( prvSyncTask, "Rndv", ebRENDESVOUS_TEST_TASK_STACK_SIZE, ( void * ) ebRENDESVOUS_TASK_2_SYNC_BIT, ebWAIT_BIT_TASK_PRIORITY, &xSyncTask2 );
+
+	/* If the last task was created then the others will have been too. */
+	configASSERT( xSyncTask2 );
+
+	/* Create the event group used by the ISR tests.  The event group used by
+	the tasks is created by the tasks themselves. */
+	xISREventGroup = xEventGroupCreate();
+	configASSERT( xISREventGroup );
+}
+/*-----------------------------------------------------------*/
+
+static void prvTestMasterTask( void *pvParameters )
+{
+BaseType_t xError;
+
+/* The handle to the slave task is passed in as the task parameter. */
+TaskHandle_t xTestSlaveTaskHandle = ( TaskHandle_t ) pvParameters;
+
+	/* Avoid compiler warnings. */
+	( void ) pvParameters;
+
+	/* Create the event group used by the tasks ready for the initial tests. */
+	xEventGroup = xEventGroupCreate();
+	configASSERT( xEventGroup );
+
+	/* Perform the tests that block two tasks on different combinations of bits,
+	then set each bit in turn and check the correct tasks unblock at the correct
+	times. */
+	xError = prvSelectiveBitsTestMasterFunction();
+
+	for( ;; )
+	{
+		/* Recreate the event group ready for the next cycle. */
+		xEventGroup = xEventGroupCreate();
+		configASSERT( xEventGroup );
+
+		/* Perform the tests that check the behaviour when a single task is
+		blocked on various combinations of event bits. */
+		xError = prvBitCombinationTestMasterFunction( xError, xTestSlaveTaskHandle );
+
+		/* Perform the task synchronisation tests. */
+		xError = prvPerformTaskSyncTests( xError, xTestSlaveTaskHandle );
+
+		/* Delete the event group. */
+		vEventGroupDelete( xEventGroup );
+
+		/* Now all the other tasks should have completed and suspended
+		themselves ready for the next go around the loop. */
+		if( eTaskGetState( xTestSlaveTaskHandle ) != eSuspended )
+		{
+			xError = pdTRUE;
+		}
+
+		if( eTaskGetState( xSyncTask1 ) != eSuspended )
+		{
+			xError = pdTRUE;
+		}
+
+		if( eTaskGetState( xSyncTask2 ) != eSuspended )
+		{
+			xError = pdTRUE;
+		}
+
+		/* Only increment the cycle variable if no errors have been detected. */
+		if( xError == pdFALSE )
+		{
+			ulTestMasterCycles++;
+		}
+
+		configASSERT( xError == pdFALSE );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSyncTask( void *pvParameters )
+{
+EventBits_t uxSynchronisationBit, uxReturned;
+
+	/* A few tests that check the behaviour when two tasks are blocked on
+	various different bits within an event group are performed before this task
+	enters its infinite loop to carry out its main demo function. */
+	prvSelectiveBitsTestSlaveFunction();
+
+	/* The bit to use to indicate this task is at the synchronisation point is
+	passed in as the task parameter. */
+	uxSynchronisationBit = ( EventBits_t ) pvParameters;
+
+	for( ;; )
+	{
+		/* Now this task takes part in a task synchronisation - sometimes known
+		as a 'rendezvous'.  Its execution pattern is controlled by the 'test
+		master' task, which is responsible for taking this task out of the
+		Suspended state when it is time to test the synchronisation behaviour.
+		See: http://www.freertos.org/xEventGroupSync.html. */
+		vTaskSuspend( NULL );
+
+		/* Set the bit that indicates this task is at the synchronisation
+		point.  The first time this is done the 'test master' task has a lower
+		priority than this task so this task will get to the sync point before
+		the set bits task - test this by first calling xEventGroupSync() with
+		a zero block time, and a block time that is too short for the other
+		task, before calling again with a max delay - the first two calls should
+		return before the rendezvous completes, the third only after the
+		rendezvous is complete. */
+		uxReturned = xEventGroupSync( xEventGroup,	/* The event group used for the synchronisation. */
+									  uxSynchronisationBit, /* The bit to set in the event group to indicate this task is at the sync point. */
+									  ebALL_SYNC_BITS,/* The bits to wait for - these bits are set by the other tasks taking part in the sync. */
+									  ebDONT_BLOCK ); /* The maximum time to wait for the sync condition to be met before giving up. */
+
+		/* No block time was specified, so as per the comments above, the
+		rendezvous is not expected to have completed yet. */
+		configASSERT( ( uxReturned & ebALL_SYNC_BITS ) != ebALL_SYNC_BITS );
+
+		uxReturned = xEventGroupSync( xEventGroup,	/* The event group used for the synchronisation. */
+									  uxSynchronisationBit, /* The bit to set in the event group to indicate this task is at the sync point. */
+									  ebALL_SYNC_BITS, /* The bits to wait for - these bits are set by the other tasks taking part in the sync. */
+									  ebONE_TICK ); /* The maximum time to wait for the sync condition to be met before giving up. */
+
+		/* A short block time was specified, so as per the comments above, the
+		rendezvous is not expected to have completed yet. */
+		configASSERT( ( uxReturned & ebALL_SYNC_BITS ) != ebALL_SYNC_BITS );
+
+		uxReturned = xEventGroupSync( xEventGroup,	/* The event group used for the synchronisation. */
+									uxSynchronisationBit, /* The bit to set in the event group to indicate this task is at the sync point. */
+									ebALL_SYNC_BITS,/* The bits to wait for - these bits are set by the other tasks taking part in the sync. */
+									portMAX_DELAY );/* The maximum time to wait for the sync condition to be met before giving up. */
+
+		/* A max delay was used, so this task should only exit the above
+		function call when the sync condition is met.  Check this is the
+		case. */
+		configASSERT( ( uxReturned & ebALL_SYNC_BITS ) == ebALL_SYNC_BITS );
+
+		/* Remove compiler warning if configASSERT() is not defined. */
+		( void ) uxReturned;
+
+		/* Wait until the 'test master' task unsuspends this task again. */
+		vTaskSuspend( NULL );
+
+		/* Set the bit that indicates this task is at the synchronisation
+		point again.  This time the 'test master' task has a higher priority
+		than this task so will get to the sync point before this task. */
+		uxReturned = xEventGroupSync( xEventGroup, uxSynchronisationBit, ebALL_SYNC_BITS, portMAX_DELAY );
+
+		/* Again a max delay was used, so this task should only exit the above
+		function call when the sync condition is met.  Check this is the
+		case. */
+		configASSERT( ( uxReturned & ebALL_SYNC_BITS ) == ebALL_SYNC_BITS );
+
+		/* Block on the event group again.  This time the event group is going
+		to be deleted while this task is blocked on it so it is expected that 0
+		be returned. */
+		uxReturned = xEventGroupWaitBits( xEventGroup, ebALL_SYNC_BITS, pdFALSE, pdTRUE, portMAX_DELAY );
+		configASSERT( uxReturned == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvTestSlaveTask( void *pvParameters )
+{
+EventBits_t uxReturned;
+BaseType_t xError = pdFALSE;
+
+	/* Avoid compiler warnings. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		/**********************************************************************
+		* Part 1:  This section is the counterpart to the
+		* prvBitCombinationTestMasterFunction() function which is called by the
+		* test master task.
+		***********************************************************************
+
+		This task is controller by the 'test master' task (which is
+		implemented by prvTestMasterTask()).  Suspend until resumed by the
+		'test master' task. */
+		vTaskSuspend( NULL );
+
+		/* Wait indefinitely for one of the bits in ebCOMBINED_BITS to get
+		set.  Clear the bit on exit. */
+		uxReturned = xEventGroupWaitBits( xEventGroup,	/* The event group that contains the event bits being queried. */
+										 ebBIT_1,		/* The bit to wait for. */
+										 pdTRUE,		/* Clear the bit on exit. */
+										 pdTRUE,		/* Wait for all the bits (only one in this case anyway). */
+										 portMAX_DELAY ); /* Block indefinitely to wait for the condition to be met. */
+
+		/* The 'test master' task set all the bits defined by ebCOMBINED_BITS,
+		only one of which was being waited for by this task.  The return value
+		shows the state of the event bits when the task was unblocked, however
+		because the task was waiting for ebBIT_1 and 'clear on exit' was set to
+		the current state of the event bits will have ebBIT_1 clear.  */
+		if( uxReturned != ebCOMBINED_BITS )
+		{
+			xError = pdTRUE;
+		}
+
+		/* Now call xEventGroupWaitBits() again, this time waiting for all the
+		bits in ebCOMBINED_BITS to be set.  This call should block until the
+		'test master' task sets ebBIT_1 - which was the bit cleared in the call
+		to xEventGroupWaitBits() above. */
+		uxReturned = xEventGroupWaitBits( xEventGroup,
+										 ebCOMBINED_BITS, /* The bits being waited on. */
+										 pdFALSE,		  /* Don't clear the bits on exit. */
+										 pdTRUE,		  /* All the bits must be set to unblock. */
+										 portMAX_DELAY );
+
+		/* Were all the bits set? */
+		if( ( uxReturned & ebCOMBINED_BITS ) != ebCOMBINED_BITS )
+		{
+			xError = pdTRUE;
+		}
+
+		/* Suspend again to wait for the 'test master' task. */
+		vTaskSuspend( NULL );
+
+		/* Now call xEventGroupWaitBits() again, again waiting for all the bits
+		in ebCOMBINED_BITS to be set, but this time clearing the bits when the
+		task is unblocked. */
+		uxReturned = xEventGroupWaitBits( xEventGroup,
+									 ebCOMBINED_BITS, /* The bits being waited on. */
+									 pdTRUE,		  /* Clear the bits on exit. */
+									 pdTRUE,		  /* All the bits must be set to unblock. */
+									 portMAX_DELAY );
+
+		/* The 'test master' task set all the bits in the event group, so that
+		is the value that should have been returned.  The bits defined by
+		ebCOMBINED_BITS will have been clear again in the current value though
+		as 'clear on exit' was set to pdTRUE. */
+		if( uxReturned != ebALL_BITS )
+		{
+			xError = pdTRUE;
+		}
+
+
+
+
+
+		/**********************************************************************
+		* Part 2:  This section is the counterpart to the
+		* prvPerformTaskSyncTests() function which is called by the
+		* test master task.
+		***********************************************************************
+
+
+		Once again wait for the 'test master' task to unsuspend this task
+		when it is time for the next test. */
+		vTaskSuspend( NULL );
+
+		/* Now peform a synchronisation with all the other tasks.  At this point
+		the 'test master' task has the lowest priority so will get to the sync
+		point after all the other synchronising tasks. */
+		uxReturned = xEventGroupSync( xEventGroup,		/* The event group used for the sync. */
+									ebWAIT_BIT_TASK_SYNC_BIT, /* The bit in the event group used to indicate this task is at the sync point. */
+									ebALL_SYNC_BITS,	/* The bits to wait for.  These bits are set by the other tasks taking part in the sync. */
+									portMAX_DELAY );	/* The maximum time to wait for the sync condition to be met before giving up. */
+
+		/* A sync with a max delay should only exit when all the synchronisation
+		bits are set... */
+		if( ( uxReturned & ebALL_SYNC_BITS ) != ebALL_SYNC_BITS )
+		{
+			xError = pdTRUE;
+		}
+
+		/* ...but now the synchronisation bits should be clear again.  Read back
+		the current value of the bits within the event group to check that is
+		the case.  Setting the bits to zero will return the bits previous value
+		then leave all the bits clear. */
+		if( xEventGroupSetBits( xEventGroup, 0x00 ) != 0 )
+		{
+			xError = pdTRUE;
+		}
+
+		/* Check the bits are indeed 0 now by simply reading then. */
+		if( xEventGroupGetBits( xEventGroup ) != 0 )
+		{
+			xError = pdTRUE;
+		}
+
+		if( xError == pdFALSE )
+		{
+			/* This task is still cycling without finding an error. */
+			ulTestSlaveCycles++;
+		}
+
+		vTaskSuspend( NULL );
+
+		/* This time sync when the 'test master' task has the highest priority
+		at the point where it sets its sync bit - so this time the 'test master'
+		task will get to the sync point before this task. */
+		uxReturned = xEventGroupSync( xEventGroup, ebWAIT_BIT_TASK_SYNC_BIT, ebALL_SYNC_BITS, portMAX_DELAY );
+
+		/* A sync with a max delay should only exit when all the synchronisation
+		bits are set... */
+		if( ( uxReturned & ebALL_SYNC_BITS ) != ebALL_SYNC_BITS )
+		{
+			xError = pdTRUE;
+		}
+
+		/* ...but now the sync bits should be clear again. */
+		if( xEventGroupSetBits( xEventGroup, 0x00 ) != 0 )
+		{
+			xError = pdTRUE;
+		}
+
+		/* Block on the event group again.  This time the event group is going
+		to be deleted while this task is blocked on it, so it is expected that 0
+		will be returned. */
+		uxReturned = xEventGroupWaitBits( xEventGroup, ebALL_SYNC_BITS, pdFALSE, pdTRUE, portMAX_DELAY );
+
+		if( uxReturned != 0 )
+		{
+			xError = pdTRUE;
+		}
+
+		if( xError == pdFALSE )
+		{
+			/* This task is still cycling without finding an error. */
+			ulTestSlaveCycles++;
+		}
+
+		configASSERT( xError == pdFALSE );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvPerformTaskSyncTests( BaseType_t xError, TaskHandle_t xTestSlaveTaskHandle )
+{
+EventBits_t uxBits;
+
+	/* The three tasks that take part in the synchronisation (rendezvous) are
+	expected to be in the suspended state at the start of the test. */
+	if( eTaskGetState( xTestSlaveTaskHandle ) != eSuspended )
+	{
+		xError = pdTRUE;
+	}
+
+	if( eTaskGetState( xSyncTask1 ) != eSuspended )
+	{
+		xError = pdTRUE;
+	}
+
+	if( eTaskGetState( xSyncTask2 ) != eSuspended )
+	{
+		xError = pdTRUE;
+	}
+
+	/* Try a synch with no other tasks involved.  First set all the bits other
+	than this task's bit. */
+	xEventGroupSetBits( xEventGroup, ( ebALL_SYNC_BITS & ~ebSET_BIT_TASK_SYNC_BIT ) );
+
+	/* Then wait on just one bit - the bit that is being set. */
+	uxBits = xEventGroupSync( xEventGroup,			/* The event group used for the synchronisation. */
+							ebSET_BIT_TASK_SYNC_BIT,/* The bit set by this task when it reaches the sync point. */
+							ebSET_BIT_TASK_SYNC_BIT,/* The bits to wait for - in this case it is just waiting for itself. */
+							portMAX_DELAY );		/* The maximum time to wait for the sync condition to be met. */
+
+	/* A sync with a max delay should only exit when all the synchronise
+	bits are set...check that is the case.  In this case there is only one
+	sync bit anyway. */
+	if( ( uxBits & ebSET_BIT_TASK_SYNC_BIT ) != ebSET_BIT_TASK_SYNC_BIT )
+	{
+		xError = pdTRUE;
+	}
+
+	/* ...but now the sync bits should be clear again, leaving all the other
+	bits set (as only one bit was being waited for). */
+	if( xEventGroupGetBits( xEventGroup ) != ( ebALL_SYNC_BITS & ~ebSET_BIT_TASK_SYNC_BIT ) )
+	{
+		xError = pdTRUE;
+	}
+
+	/* Clear all the bits to zero again. */
+	xEventGroupClearBits( xEventGroup, ( ebALL_SYNC_BITS & ~ebSET_BIT_TASK_SYNC_BIT ) );
+	if( xEventGroupGetBits( xEventGroup ) != 0 )
+	{
+		xError = pdTRUE;
+	}
+
+	/* Unsuspend the other tasks then check they have executed up to the
+	synchronisation point. */
+	vTaskResume( xTestSlaveTaskHandle );
+	vTaskResume( xSyncTask1 );
+	vTaskResume( xSyncTask2 );
+
+	if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked )
+	{
+		xError = pdTRUE;
+	}
+
+	if( eTaskGetState( xSyncTask1 ) != eBlocked )
+	{
+		xError = pdTRUE;
+	}
+
+	if( eTaskGetState( xSyncTask2 ) != eBlocked )
+	{
+		xError = pdTRUE;
+	}
+
+	/* Set this task's sync bit. */
+	uxBits = xEventGroupSync( xEventGroup,			/* The event group used for the synchronisation. */
+							ebSET_BIT_TASK_SYNC_BIT,/* The bit set by this task when it reaches the sync point. */
+							ebALL_SYNC_BITS,		/* The bits to wait for - these bits are set by the other tasks that take part in the sync. */
+							portMAX_DELAY );		/* The maximum time to wait for the sync condition to be met. */
+
+	/* A sync with a max delay should only exit when all the synchronise
+	bits are set...check that is the case. */
+	if( ( uxBits & ebALL_SYNC_BITS ) != ebALL_SYNC_BITS )
+	{
+		xError = pdTRUE;
+	}
+
+	/* ...but now the sync bits should be clear again. */
+	if( xEventGroupGetBits( xEventGroup ) != 0 )
+	{
+		xError = pdTRUE;
+	}
+
+
+	/* The other tasks should now all be suspended again, ready for the next
+	synchronisation. */
+	if( eTaskGetState( xTestSlaveTaskHandle ) != eSuspended )
+	{
+		xError = pdTRUE;
+	}
+
+	if( eTaskGetState( xSyncTask1 ) != eSuspended )
+	{
+		xError = pdTRUE;
+	}
+
+	if( eTaskGetState( xSyncTask2 ) != eSuspended )
+	{
+		xError = pdTRUE;
+	}
+
+
+	/* Sync again - but this time set the last necessary bit as the
+	highest priority task, rather than the lowest priority task.  Unsuspend
+	the other tasks then check they have executed up to the	synchronisation
+	point. */
+	vTaskResume( xTestSlaveTaskHandle );
+	vTaskResume( xSyncTask1 );
+	vTaskResume( xSyncTask2 );
+
+	if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked )
+	{
+		xError = pdTRUE;
+	}
+
+	if( eTaskGetState( xSyncTask1 ) != eBlocked )
+	{
+		xError = pdTRUE;
+	}
+
+	if( eTaskGetState( xSyncTask2 ) != eBlocked )
+	{
+		xError = pdTRUE;
+	}
+
+	/* Raise the priority of this task above that of the other tasks. */
+	vTaskPrioritySet( NULL, ebWAIT_BIT_TASK_PRIORITY + 1 );
+
+	/* Set this task's sync bit. */
+	uxBits = xEventGroupSync( xEventGroup, ebSET_BIT_TASK_SYNC_BIT, ebALL_SYNC_BITS, portMAX_DELAY );
+
+	/* A sync with a max delay should only exit when all the synchronisation
+	bits are set... */
+	if( ( uxBits & ebALL_SYNC_BITS ) != ebALL_SYNC_BITS )
+	{
+		xError = pdTRUE;
+	}
+
+	/* ...but now the sync bits should be clear again. */
+	if( xEventGroupGetBits( xEventGroup ) != 0 )
+	{
+		xError = pdTRUE;
+	}
+
+
+	/* The other tasks should now all be in the ready state again, but not
+	executed yet as this task still has a higher relative priority. */
+	if( eTaskGetState( xTestSlaveTaskHandle ) != eReady )
+	{
+		xError = pdTRUE;
+	}
+
+	if( eTaskGetState( xSyncTask1 ) != eReady )
+	{
+		xError = pdTRUE;
+	}
+
+	if( eTaskGetState( xSyncTask2 ) != eReady )
+	{
+		xError = pdTRUE;
+	}
+
+
+	/* Reset the priority of this task back to its original value. */
+	vTaskPrioritySet( NULL, ebSET_BIT_TASK_PRIORITY );
+
+	/* Now all the other tasks should have reblocked on the event bits
+	to test the behaviour when the event bits are deleted. */
+	if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked )
+	{
+		xError = pdTRUE;
+	}
+
+	if( eTaskGetState( xSyncTask1 ) != eBlocked )
+	{
+		xError = pdTRUE;
+	}
+
+	if( eTaskGetState( xSyncTask2 ) != eBlocked )
+	{
+		xError = pdTRUE;
+	}
+
+	return xError;
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvBitCombinationTestMasterFunction( BaseType_t xError, TaskHandle_t xTestSlaveTaskHandle )
+{
+EventBits_t uxBits;
+
+	/* Resume the other task.  It will block, pending a single bit from
+	within ebCOMBINED_BITS. */
+	vTaskResume( xTestSlaveTaskHandle );
+
+	/* Ensure the other task is blocked on the task. */
+	if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked )
+	{
+		xError = pdTRUE;
+	}
+
+	/* Set all the bits in ebCOMBINED_BITS - the 'test slave' task is only
+	blocked waiting for one of them. */
+	xEventGroupSetBits( xEventGroup, ebCOMBINED_BITS );
+
+	/* The 'test slave' task should now have executed, clearing ebBIT_1 (the
+	bit it was blocked on), then re-entered the Blocked state to wait for
+	all the other bits in ebCOMBINED_BITS to be set again.  First check
+	ebBIT_1 is clear. */
+	uxBits = xEventGroupWaitBits( xEventGroup, ebALL_BITS, pdFALSE, pdFALSE, ebDONT_BLOCK );
+
+	if( uxBits != ( ebCOMBINED_BITS & ~ebBIT_1 ) )
+	{
+		xError = pdTRUE;
+	}
+
+	/* Ensure the other task is still in the blocked state. */
+	if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked )
+	{
+		xError = pdTRUE;
+	}
+
+	/* Set all the bits other than ebBIT_1 - which is the bit that must be
+	set before the other task unblocks. */
+	xEventGroupSetBits( xEventGroup, ebALL_BITS & ~ebBIT_1 );
+
+	/* Ensure all the expected bits are still set. */
+	uxBits = xEventGroupWaitBits( xEventGroup, ebALL_BITS, pdFALSE, pdFALSE, ebDONT_BLOCK );
+
+	if( uxBits != ( ebALL_BITS & ~ebBIT_1 ) )
+	{
+		xError = pdTRUE;
+	}
+
+	/* Ensure the other task is still in the blocked state. */
+	if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked )
+	{
+		xError = pdTRUE;
+	}
+
+	/* Now also set ebBIT_1, which should unblock the other task, which will
+	then suspend itself. */
+	xEventGroupSetBits( xEventGroup, ebBIT_1 );
+
+	/* Ensure the other task is suspended. */
+	if( eTaskGetState( xTestSlaveTaskHandle ) != eSuspended )
+	{
+		xError = pdTRUE;
+	}
+
+	/* The other task should not have cleared the bits - so all the bits
+	should still be set. */
+	if( xEventGroupSetBits( xEventGroup, 0x00 ) != ebALL_BITS )
+	{
+		xError = pdTRUE;
+	}
+
+	/* Clear ebBIT_1 again. */
+	if( xEventGroupClearBits( xEventGroup, ebBIT_1 ) != ebALL_BITS )
+	{
+		xError = pdTRUE;
+	}
+
+	/* Resume the other task - which will wait on all the ebCOMBINED_BITS
+	again - this time clearing the bits when it is unblocked. */
+	vTaskResume( xTestSlaveTaskHandle );
+
+	/* Ensure the other task is blocked once again. */
+	if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked )
+	{
+		xError = pdTRUE;
+	}
+
+	/* Set the bit the other task is waiting for. */
+	xEventGroupSetBits( xEventGroup, ebBIT_1 );
+
+	/* Ensure the other task is suspended once again. */
+	if( eTaskGetState( xTestSlaveTaskHandle ) != eSuspended )
+	{
+		xError = pdTRUE;
+	}
+
+	/* The other task should have cleared the bits in ebCOMBINED_BITS.
+	Clear the remaining bits. */
+	uxBits = xEventGroupWaitBits( xEventGroup, ebALL_BITS, pdFALSE, pdFALSE, ebDONT_BLOCK );
+
+	if( uxBits != ( ebALL_BITS & ~ebCOMBINED_BITS ) )
+	{
+		xError = pdTRUE;
+	}
+
+	/* Clear all bits ready for the sync with the other three tasks.  The
+	value returned is the value prior to the bits being cleared. */
+	if( xEventGroupClearBits( xEventGroup, ebALL_BITS ) != ( ebALL_BITS & ~ebCOMBINED_BITS ) )
+	{
+		xError = pdTRUE;
+	}
+
+	/* The bits should be clear now. */
+	if( xEventGroupGetBits( xEventGroup ) != 0x00 )
+	{
+		xError = pdTRUE;
+	}
+
+	return xError;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSelectiveBitsTestSlaveFunction( void )
+{
+EventBits_t uxPendBits, uxReturned;
+
+	/* Used in a test that blocks two tasks on various different bits within an
+	event group - then sets each bit in turn and checks that the correct tasks
+	unblock at the correct times.
+
+	This function is called by two different tasks - each of which will use a
+	different bit.  Check the task handle to see which task the function was
+	called by. */
+	if( xTaskGetCurrentTaskHandle() == xSyncTask1 )
+	{
+		uxPendBits = ebSELECTIVE_BITS_1;
+	}
+	else
+	{
+		uxPendBits = ebSELECTIVE_BITS_2;
+	}
+
+	for( ;; )
+	{
+		/* Wait until it is time to perform the next cycle of the test.  The
+		task is unsuspended by the tests implemented in the
+		prvSelectiveBitsTestMasterFunction() function. */
+		vTaskSuspend( NULL );
+		uxReturned = xEventGroupWaitBits( xEventGroup, uxPendBits, pdTRUE, pdFALSE, portMAX_DELAY );
+
+		if( uxReturned == ( EventBits_t ) 0 )
+		{
+			break;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvSelectiveBitsTestMasterFunction( void )
+{
+BaseType_t xError = pdFALSE;
+EventBits_t uxBit;
+
+	/* Used in a test that blocks two tasks on various different bits within an
+	event group - then sets each bit in turn and checks that the correct tasks
+	unblock at the correct times.  The two other tasks (xSyncTask1 and
+	xSyncTask2) call prvSelectiveBitsTestSlaveFunction() to perform their parts in
+	this test.
+
+	Both other tasks should start in the suspended state. */
+	if( eTaskGetState( xSyncTask1 ) != eSuspended )
+	{
+		xError = pdTRUE;
+	}
+
+	if( eTaskGetState( xSyncTask2 ) != eSuspended )
+	{
+		xError = pdTRUE;
+	}
+
+	/* Test each bit in the byte individually. */
+	for( uxBit = 0x01; uxBit < 0x100; uxBit <<= 1 )
+	{
+		/* Resume both tasks. */
+		vTaskResume( xSyncTask1 );
+		vTaskResume( xSyncTask2 );
+
+		/* Now both tasks should be blocked on the event group. */
+		if( eTaskGetState( xSyncTask1 ) != eBlocked )
+		{
+			xError = pdTRUE;
+		}
+
+		if( eTaskGetState( xSyncTask2 ) != eBlocked )
+		{
+			xError = pdTRUE;
+		}
+
+		/* Set one bit. */
+		xEventGroupSetBits( xEventGroup, uxBit );
+
+		/* Is the bit set in the first set of selective bits?  If so the first
+		sync task should have unblocked and returned to the suspended state. */
+		if( ( uxBit & ebSELECTIVE_BITS_1 ) == 0 )
+		{
+			/* Task should not have unblocked. */
+			if( eTaskGetState( xSyncTask1 ) != eBlocked )
+			{
+				xError = pdTRUE;
+			}
+		}
+		else
+		{
+			/* Task should have unblocked and returned to the suspended state. */
+			if( eTaskGetState( xSyncTask1 ) != eSuspended )
+			{
+				xError = pdTRUE;
+			}
+		}
+
+		/* Same checks for the second sync task. */
+		if( ( uxBit & ebSELECTIVE_BITS_2 ) == 0 )
+		{
+			/* Task should not have unblocked. */
+			if( eTaskGetState( xSyncTask2 ) != eBlocked )
+			{
+				xError = pdTRUE;
+			}
+		}
+		else
+		{
+			/* Task should have unblocked and returned to the suspended state. */
+			if( eTaskGetState( xSyncTask2 ) != eSuspended )
+			{
+				xError = pdTRUE;
+			}
+		}
+	}
+
+	/* Ensure both tasks are blocked on the event group again, then delete the
+	event group so the other tasks leave this portion of the test. */
+	vTaskResume( xSyncTask1 );
+	vTaskResume( xSyncTask2 );
+
+	/* Deleting the event group is the signal that the two other tasks should
+	leave the prvSelectiveBitsTestSlaveFunction() function and continue to the main
+	part of their functionality. */
+	vEventGroupDelete( xEventGroup );
+
+	return xError;
+}
+/*-----------------------------------------------------------*/
+
+void vPeriodicEventGroupsProcessing( void )
+{
+static BaseType_t xCallCount = 0, xISRTestError = pdFALSE;
+const BaseType_t xSetBitCount = 100, xGetBitsCount = 200, xClearBitsCount = 300;
+const EventBits_t uxBitsToSet = 0x12U;
+EventBits_t uxReturned;
+BaseType_t xMessagePosted;
+
+	/* Called periodically from the tick hook to exercise the "FromISR"
+	functions. */
+
+	xCallCount++;
+
+	if( xCallCount == xSetBitCount )
+	{
+		/* All the event bits should start clear. */
+		uxReturned = xEventGroupGetBitsFromISR( xISREventGroup );
+		if( uxReturned != 0x00 )
+		{
+			xISRTestError = pdTRUE;
+		}
+		else
+		{
+			/* Set the bits.  This is called from the tick hook so it is not
+			necessary to use the last parameter to ensure a context switch
+			occurs immediately. */
+			xMessagePosted = xEventGroupSetBitsFromISR( xISREventGroup, uxBitsToSet, NULL );
+			if( xMessagePosted != pdPASS )
+			{
+				xISRTestError = pdTRUE;
+			}
+		}
+	}
+	else if( xCallCount == xGetBitsCount )
+	{
+		/* Check the bits were set as expected. */
+		uxReturned = xEventGroupGetBitsFromISR( xISREventGroup );
+		if( uxReturned != uxBitsToSet )
+		{
+			xISRTestError = pdTRUE;
+		}
+	}
+	else if( xCallCount == xClearBitsCount )
+	{
+		/* Clear the bits again. */
+		uxReturned = ( EventBits_t ) xEventGroupClearBitsFromISR( xISREventGroup, uxBitsToSet );
+
+		/* Check the message was posted. */
+		if( uxReturned != pdPASS )
+		{
+			xISRTestError = pdTRUE;
+		}
+
+		/* Go back to the start. */
+		xCallCount = 0;
+
+		/* If no errors have been detected then increment the count of test
+		cycles. */
+		if( xISRTestError == pdFALSE )
+		{
+			ulISRCycles++;
+		}
+	}
+	else
+	{
+		/* Nothing else to do. */
+	}
+}
+
+/*-----------------------------------------------------------*/
+/* This is called to check that all the created tasks are still running. */
+BaseType_t xAreEventGroupTasksStillRunning( void )
+{
+static uint32_t ulPreviousWaitBitCycles = 0, ulPreviousSetBitCycles = 0, ulPreviousISRCycles = 0;
+BaseType_t xStatus = pdPASS;
+
+	/* Check the tasks are still cycling without finding any errors. */
+	if( ulPreviousSetBitCycles == ulTestMasterCycles )
+	{
+		xStatus = pdFAIL;
+	}
+	ulPreviousSetBitCycles = ulTestMasterCycles;
+
+	if( ulPreviousWaitBitCycles == ulTestSlaveCycles )
+	{
+		xStatus = pdFAIL;
+	}
+	ulPreviousWaitBitCycles = ulTestSlaveCycles;
+
+	if( ulPreviousISRCycles == ulISRCycles )
+	{
+		xStatus = pdFAIL;
+	}
+	ulPreviousISRCycles = ulISRCycles;
+
+	return xStatus;
+}
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/GenQTest.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/GenQTest.c
new file mode 100644
index 0000000..97f693c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/GenQTest.c
@@ -0,0 +1,1029 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*
+ * Tests the extra queue functionality introduced in FreeRTOS.org V4.5.0 -
+ * including xQueueSendToFront(), xQueueSendToBack(), xQueuePeek() and
+ * mutex behaviour.
+ *
+ * See the comments above the prvSendFrontAndBackTest() and
+ * prvLowPriorityMutexTask() prototypes below for more information.
+ */
+
+/* Standard includes. */
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+
+/* Demo program include files. */
+#include "GenQTest.h"
+
+#define genqQUEUE_LENGTH		( 5 )
+#define intsemNO_BLOCK			( 0 )
+#define genqSHORT_BLOCK			( pdMS_TO_TICKS( 2 ) )
+
+#define genqMUTEX_LOW_PRIORITY		( tskIDLE_PRIORITY )
+#define genqMUTEX_TEST_PRIORITY		( tskIDLE_PRIORITY + 1 )
+#define genqMUTEX_MEDIUM_PRIORITY	( tskIDLE_PRIORITY + 2 )
+#define genqMUTEX_HIGH_PRIORITY		( tskIDLE_PRIORITY + 3 )
+
+#ifndef genqMUTEX_TEST_TASK_STACK_SIZE
+	#define genqMUTEX_TEST_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
+#endif
+
+#ifndef genqGENERIC_QUEUE_TEST_TASK_STACK_SIZE
+	#define genqGENERIC_QUEUE_TEST_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * Tests the behaviour of the xQueueSendToFront() and xQueueSendToBack()
+ * macros by using both to fill a queue, then reading from the queue to
+ * check the resultant queue order is as expected.  Queue data is also
+ * peeked.
+ */
+static void prvSendFrontAndBackTest( void *pvParameters );
+
+/*
+ * The following three tasks are used to demonstrate the mutex behaviour.
+ * Each task is given a different priority to demonstrate the priority
+ * inheritance mechanism.
+ *
+ * The low priority task obtains a mutex.  After this a high priority task
+ * attempts to obtain the same mutex, causing its priority to be inherited
+ * by the low priority task.  The task with the inherited high priority then
+ * resumes a medium priority task to ensure it is not blocked by the medium
+ * priority task while it holds the inherited high priority.  Once the mutex
+ * is returned the task with the inherited priority returns to its original
+ * low priority, and is therefore immediately preempted by first the high
+ * priority task and then the medium priority task before it can continue.
+ */
+static void prvLowPriorityMutexTask( void *pvParameters );
+static void prvMediumPriorityMutexTask( void *pvParameters );
+static void prvHighPriorityMutexTask( void *pvParameters );
+
+/*
+ * Tests the behaviour when a low priority task inherits the priority of a
+ * higher priority task when taking two mutexes, and returns the mutexes in
+ * first the same order as the two mutexes were obtained, and second the
+ * opposite order as the two mutexes were obtained.
+ */
+static void prvTakeTwoMutexesReturnInSameOrder( SemaphoreHandle_t xMutex, SemaphoreHandle_t xLocalMutex );
+static void prvTakeTwoMutexesReturnInDifferentOrder( SemaphoreHandle_t xMutex, SemaphoreHandle_t xLocalMutex );
+
+#if( INCLUDE_xTaskAbortDelay == 1 )
+
+	#if( configUSE_PREEMPTION == 0 )
+		#error The additional tests included when INCLUDE_xTaskAbortDelay is 1 expect preemption to be used.
+	#endif
+
+	/* Tests the behaviour when a low priority task inherits the priority of a
+	high priority task only for the high priority task to timeout before
+	obtaining the mutex. */
+	static void prvHighPriorityTimeout( SemaphoreHandle_t xMutex );
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Flag that will be latched to pdTRUE should any unexpected behaviour be
+detected in any of the tasks. */
+static volatile BaseType_t xErrorDetected = pdFALSE;
+
+/* Counters that are incremented on each cycle of a test.  This is used to
+detect a stalled task - a test that is no longer running. */
+static volatile uint32_t ulLoopCounter = 0;
+static volatile uint32_t ulLoopCounter2 = 0;
+
+/* The variable that is guarded by the mutex in the mutex demo tasks. */
+static volatile uint32_t ulGuardedVariable = 0;
+
+/* Handles used in the mutex test to suspend and resume the high and medium
+priority mutex test tasks. */
+static TaskHandle_t xHighPriorityMutexTask, xMediumPriorityMutexTask;
+
+/* If INCLUDE_xTaskAbortDelay is 1 additional tests are performed, requiring an
+additional task. */
+#if( INCLUDE_xTaskAbortDelay == 1 )
+	static TaskHandle_t xSecondMediumPriorityMutexTask;
+#endif
+
+/* Lets the high priority semaphore task know that its wait for the semaphore
+was aborted, in which case not being able to obtain the semaphore is not to be
+considered an error. */
+static volatile BaseType_t xBlockWasAborted = pdFALSE;
+
+/*-----------------------------------------------------------*/
+
+void vStartGenericQueueTasks( UBaseType_t uxPriority )
+{
+QueueHandle_t xQueue;
+SemaphoreHandle_t xMutex;
+
+	/* Create the queue that we are going to use for the
+	prvSendFrontAndBackTest demo. */
+	xQueue = xQueueCreate( genqQUEUE_LENGTH, sizeof( uint32_t ) );
+
+	if( xQueue != NULL )
+	{
+		/* vQueueAddToRegistry() adds the queue to the queue registry, if one
+		is in use.  The queue registry is provided as a means for kernel aware
+		debuggers to locate queues and has no purpose if a kernel aware debugger
+		is not being used.  The call to vQueueAddToRegistry() will be removed
+		by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is
+		defined to be less than 1. */
+		vQueueAddToRegistry( xQueue, "Gen_Queue_Test" );
+
+		/* Create the demo task and pass it the queue just created.  We are
+		passing the queue handle by value so it does not matter that it is
+		declared on the stack here. */
+		xTaskCreate( prvSendFrontAndBackTest, "GenQ", genqGENERIC_QUEUE_TEST_TASK_STACK_SIZE, ( void * ) xQueue, uxPriority, NULL );
+	}
+
+	/* Create the mutex used by the prvMutexTest task. */
+	xMutex = xSemaphoreCreateMutex();
+
+	if( xMutex != NULL )
+	{
+		/* vQueueAddToRegistry() adds the mutex to the registry, if one is
+		in use.  The registry is provided as a means for kernel aware
+		debuggers to locate mutexes and has no purpose if a kernel aware
+		debugger is not being used.  The call to vQueueAddToRegistry() will be
+		removed by the pre-processor if configQUEUE_REGISTRY_SIZE is not
+		defined or is defined to be less than 1. */
+		vQueueAddToRegistry( ( QueueHandle_t ) xMutex, "Gen_Queue_Mutex" );
+
+		/* Create the mutex demo tasks and pass it the mutex just created.  We
+		are passing the mutex handle by value so it does not matter that it is
+		declared on the stack here. */
+		xTaskCreate( prvLowPriorityMutexTask, "MuLow", genqMUTEX_TEST_TASK_STACK_SIZE, ( void * ) xMutex, genqMUTEX_LOW_PRIORITY, NULL );
+		xTaskCreate( prvMediumPriorityMutexTask, "MuMed", configMINIMAL_STACK_SIZE, NULL, genqMUTEX_MEDIUM_PRIORITY, &xMediumPriorityMutexTask );
+		xTaskCreate( prvHighPriorityMutexTask, "MuHigh", genqMUTEX_TEST_TASK_STACK_SIZE, ( void * ) xMutex, genqMUTEX_HIGH_PRIORITY, &xHighPriorityMutexTask );
+
+		/* If INCLUDE_xTaskAbortDelay is set then additional tests are performed,
+		requiring two instances of prvHighPriorityMutexTask(). */
+		#if( INCLUDE_xTaskAbortDelay == 1 )
+		{
+			xTaskCreate( prvHighPriorityMutexTask, "MuHigh2", configMINIMAL_STACK_SIZE, ( void * ) xMutex, genqMUTEX_MEDIUM_PRIORITY, &xSecondMediumPriorityMutexTask );
+		}
+		#endif /* INCLUDE_xTaskAbortDelay */
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSendFrontAndBackTest( void *pvParameters )
+{
+uint32_t ulData, ulData2, ulLoopCounterSnapshot;
+QueueHandle_t xQueue;
+
+	#ifdef USE_STDIO
+	void vPrintDisplayMessage( const char * const * ppcMessageToSend );
+
+		const char * const pcTaskStartMsg = "Queue SendToFront/SendToBack/Peek test started.\r\n";
+
+		/* Queue a message for printing to say the task has started. */
+		vPrintDisplayMessage( &pcTaskStartMsg );
+	#endif
+
+	xQueue = ( QueueHandle_t ) pvParameters;
+
+	for( ;; )
+	{
+		/* The queue is empty, so sending an item to the back of the queue
+		should have the same efect as sending it to the front of the queue.
+
+		First send to the front and check everything is as expected. */
+		ulLoopCounterSnapshot = ulLoopCounter;
+		xQueueSendToFront( xQueue, ( void * ) &ulLoopCounterSnapshot, intsemNO_BLOCK );
+
+		if( uxQueueMessagesWaiting( xQueue ) != 1 )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		if( xQueueReceive( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != pdPASS )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		/* The data we sent to the queue should equal the data we just received
+		from the queue. */
+		if( ulLoopCounter != ulData )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		/* Then do the same, sending the data to the back, checking everything
+		is as expected. */
+		if( uxQueueMessagesWaiting( xQueue ) != 0 )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		ulLoopCounterSnapshot = ulLoopCounter;
+		xQueueSendToBack( xQueue, ( void * ) &ulLoopCounterSnapshot, intsemNO_BLOCK );
+
+		if( uxQueueMessagesWaiting( xQueue ) != 1 )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		if( xQueueReceive( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != pdPASS )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		if( uxQueueMessagesWaiting( xQueue ) != 0 )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		/* The data sent to the queue should equal the data just received from
+		the queue. */
+		if( ulLoopCounter != ulData )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+
+
+		/* Place 2, 3, 4 into the queue, adding items to the back of the queue. */
+		for( ulData = 2; ulData < 5; ulData++ )
+		{
+			xQueueSendToBack( xQueue, ( void * ) &ulData, intsemNO_BLOCK );
+		}
+
+		/* Now the order in the queue should be 2, 3, 4, with 2 being the first
+		thing to be read out.  Now add 1 then 0 to the front of the queue. */
+		if( uxQueueMessagesWaiting( xQueue ) != 3 )
+		{
+			xErrorDetected = pdTRUE;
+		}
+		ulData = 1;
+		xQueueSendToFront( xQueue, ( void * ) &ulData, intsemNO_BLOCK );
+		ulData = 0;
+		xQueueSendToFront( xQueue, ( void * ) &ulData, intsemNO_BLOCK );
+
+		/* Now the queue should be full, and when we read the data out we
+		should receive 0, 1, 2, 3, 4. */
+		if( uxQueueMessagesWaiting( xQueue ) != 5 )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		if( xQueueSendToFront( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != errQUEUE_FULL )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		if( xQueueSendToBack( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != errQUEUE_FULL )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+		/* Check the data we read out is in the expected order. */
+		for( ulData = 0; ulData < genqQUEUE_LENGTH; ulData++ )
+		{
+			/* Try peeking the data first. */
+			if( xQueuePeek( xQueue, &ulData2, intsemNO_BLOCK ) != pdPASS )
+			{
+				xErrorDetected = pdTRUE;
+			}
+
+			if( ulData != ulData2 )
+			{
+				xErrorDetected = pdTRUE;
+			}
+
+
+			/* Now try receiving the data for real.  The value should be the
+			same.  Clobber the value first so we know we really received it. */
+			ulData2 = ~ulData2;
+			if( xQueueReceive( xQueue, &ulData2, intsemNO_BLOCK ) != pdPASS )
+			{
+				xErrorDetected = pdTRUE;
+			}
+
+			if( ulData != ulData2 )
+			{
+				xErrorDetected = pdTRUE;
+			}
+		}
+
+		/* The queue should now be empty again. */
+		if( uxQueueMessagesWaiting( xQueue ) != 0 )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+
+		/* Our queue is empty once more, add 10, 11 to the back. */
+		ulData = 10;
+		if( xQueueSend( xQueue, &ulData, intsemNO_BLOCK ) != pdPASS )
+		{
+			xErrorDetected = pdTRUE;
+		}
+		ulData = 11;
+		if( xQueueSend( xQueue, &ulData, intsemNO_BLOCK ) != pdPASS )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		if( uxQueueMessagesWaiting( xQueue ) != 2 )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		/* Now we should have 10, 11 in the queue.  Add 7, 8, 9 to the
+		front. */
+		for( ulData = 9; ulData >= 7; ulData-- )
+		{
+			if( xQueueSendToFront( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != pdPASS )
+			{
+				xErrorDetected = pdTRUE;
+			}
+		}
+
+		/* Now check that the queue is full, and that receiving data provides
+		the expected sequence of 7, 8, 9, 10, 11. */
+		if( uxQueueMessagesWaiting( xQueue ) != 5 )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		if( xQueueSendToFront( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != errQUEUE_FULL )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		if( xQueueSendToBack( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != errQUEUE_FULL )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+		/* Check the data we read out is in the expected order. */
+		for( ulData = 7; ulData < ( 7 + genqQUEUE_LENGTH ); ulData++ )
+		{
+			if( xQueueReceive( xQueue, &ulData2, intsemNO_BLOCK ) != pdPASS )
+			{
+				xErrorDetected = pdTRUE;
+			}
+
+			if( ulData != ulData2 )
+			{
+				xErrorDetected = pdTRUE;
+			}
+		}
+
+		if( uxQueueMessagesWaiting( xQueue ) != 0 )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		/* Increment the loop counter to indicate these tasks are still
+		executing. */
+		ulLoopCounter++;
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTaskAbortDelay == 1 )
+
+	static void prvHighPriorityTimeout( SemaphoreHandle_t xMutex )
+	{
+	static UBaseType_t uxLoopCount = 0;
+
+		/* The tests in this function are very similar, the slight variations
+		are for code coverage purposes. */
+
+		/* Take the mutex.  It should be available now.  Check before and after
+		taking that the holder is reported correctly. */
+		if( xSemaphoreGetMutexHolder( xMutex ) != NULL )
+		{
+			xErrorDetected = pdTRUE;
+		}
+		if( xSemaphoreTake( xMutex, intsemNO_BLOCK ) != pdPASS )
+		{
+			xErrorDetected = pdTRUE;
+		}
+		if( xSemaphoreGetMutexHolder( xMutex ) != xTaskGetCurrentTaskHandle() )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		/* This task's priority should be as per that assigned when the task was
+		created. */
+		if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		/* Now unsuspend the high priority task.  This will attempt to take the
+		mutex, and block when it finds it cannot obtain it. */
+		vTaskResume( xHighPriorityMutexTask );
+
+		/* This task should now have inherited the priority of the high priority
+		task as by now the high priority task will have attempted to obtain the
+		mutex. */
+		if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		/* Unblock a second medium priority task.  It too will attempt to take
+		the mutex and enter the Blocked state - it won't run yet though as this
+		task has inherited a priority above it. */
+		vTaskResume( xSecondMediumPriorityMutexTask );
+
+		/* This task should still have the priority of the high priority task as
+		that had already been inherited as is the highest priority of the three
+		tasks using the mutex. */
+		if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		/* On some loops, block for a short while to provide additional
+		code coverage.  Blocking here will allow the medium priority task to
+		execute and so also block on the mutex so when the high priority task
+		causes this task to disinherit the high priority it is inherited down to
+		the priority of the medium priority task.  When there is no delay the
+		medium priority task will not run until after the disinheritance, so
+		this task will disinherit back to its base priority, then only up to the
+		medium priority after the medium priority has executed. */
+		vTaskDelay( uxLoopCount & ( UBaseType_t ) 0x07 );
+
+		/* Now force the high priority task to unblock.  It will fail to obtain
+		the mutex and go back to the suspended state - allowing this task to
+		execute again.  xBlockWasAborted is set to pdTRUE so the higher priority
+		task knows that its failure to obtain the semaphore is not an error. */
+		xBlockWasAborted = pdTRUE;
+		if( xTaskAbortDelay( xHighPriorityMutexTask ) != pdPASS )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		/* This task has inherited the priority of xHighPriorityMutexTask so
+		could still be running even though xHighPriorityMutexTask is no longer
+		blocked.  Delay for a short while to ensure xHighPriorityMutexTask gets
+		a chance to run - indicated by this task changing priority.  It should
+		disinherit the high priority task, but then inherit the priority of the
+		medium priority task that is waiting for the same mutex. */
+		while( uxTaskPriorityGet( NULL ) != genqMUTEX_MEDIUM_PRIORITY )
+		{
+			/* If this task gets stuck here then the check variables will stop
+			incrementing and the check task will detect the error. */
+			vTaskDelay( genqSHORT_BLOCK );
+		}
+
+		/* Now force the medium priority task to unblock.  xBlockWasAborted is
+		set to pdTRUE so the medium priority task knows that its failure to
+		obtain the semaphore is not an error. */
+		xBlockWasAborted = pdTRUE;
+		if( xTaskAbortDelay( xSecondMediumPriorityMutexTask ) != pdPASS )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		/* This time no other tasks are waiting for the mutex, so this task
+		should return to its base priority.  This might not happen straight
+		away as it is running at the same priority as the task it just
+		unblocked. */
+		while( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
+		{
+			/* If this task gets stuck here then the check variables will stop
+			incrementing and the check task will detect the error. */
+			vTaskDelay( genqSHORT_BLOCK );
+		}
+
+		/* Give the semaphore back ready for the next test.  Check the mutex
+		holder before and after using the "FromISR" version for code coverage. */
+		if( xSemaphoreGetMutexHolderFromISR( xMutex ) != xTaskGetCurrentTaskHandle() )
+		{
+			xErrorDetected = pdTRUE;
+		}
+		xSemaphoreGive( xMutex );
+		if( xSemaphoreGetMutexHolderFromISR( xMutex ) != NULL )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		configASSERT( xErrorDetected == pdFALSE );
+
+
+
+		/* Now do the same again, but this time unsuspend the tasks in the
+		opposite order.  This takes a different path though the code because
+		when the high priority task has its block aborted there is already
+		another task in the list of tasks waiting for the mutex, and the
+		low priority task drops down to that priority, rather than dropping
+		down to its base priority before inheriting the priority of the medium
+		priority task. */
+		if( xSemaphoreTake( xMutex, intsemNO_BLOCK ) != pdPASS )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		/* This time unsuspend the medium priority task first.  This will
+		attempt to take the mutex, and block when it finds it cannot obtain it. */
+		vTaskResume( xSecondMediumPriorityMutexTask );
+
+		/* This time this task should now have inherited the priority of the
+		medium task. */
+		if( uxTaskPriorityGet( NULL ) != genqMUTEX_MEDIUM_PRIORITY )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		/* This time the high priority task in unsuspended second. */
+		vTaskResume( xHighPriorityMutexTask );
+
+		/* The high priority task should already have run, causing this task to
+		inherit a priority for the second time. */
+		if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		/* This time, when the high priority task has its delay aborted and it
+		fails to obtain the mutex this task will immediately have its priority
+		lowered down to that of the highest priority task waiting on the mutex,
+		which is the medium priority task. */
+		xBlockWasAborted = pdTRUE;
+		if( xTaskAbortDelay( xHighPriorityMutexTask ) != pdPASS )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		while( uxTaskPriorityGet( NULL ) != genqMUTEX_MEDIUM_PRIORITY )
+		{
+			/* If this task gets stuck here then the check variables will stop
+			incrementing and the check task will detect the error. */
+			vTaskDelay( genqSHORT_BLOCK );
+		}
+
+		/* And finally, when the medium priority task also have its delay
+		aborted there are no other tasks waiting for the mutex so this task
+		returns to its base priority. */
+		xBlockWasAborted = pdTRUE;
+		if( xTaskAbortDelay( xSecondMediumPriorityMutexTask ) != pdPASS )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		while( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
+		{
+			/* If this task gets stuck here then the check variables will stop
+			incrementing and the check task will detect the error. */
+			vTaskDelay( genqSHORT_BLOCK );
+		}
+
+		/* Give the semaphore back ready for the next test. */
+		xSemaphoreGive( xMutex );
+
+		configASSERT( xErrorDetected == pdFALSE );
+
+		/* uxLoopCount is used to add a variable delay, and in-so-doing provide
+		additional code coverage. */
+		uxLoopCount++;
+	}
+
+#endif /* INCLUDE_xTaskAbortDelay == 1 */
+/*-----------------------------------------------------------*/
+
+static void prvTakeTwoMutexesReturnInDifferentOrder( SemaphoreHandle_t xMutex, SemaphoreHandle_t xLocalMutex )
+{
+	/* Take the mutex.  It should be available now. */
+	if( xSemaphoreTake( xMutex, intsemNO_BLOCK ) != pdPASS )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Set the guarded variable to a known start value. */
+	ulGuardedVariable = 0;
+
+	/* This task's priority should be as per that assigned when the task was
+	created. */
+	if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Now unsuspend the high priority task.  This will attempt to take the
+	mutex, and block when it finds it cannot obtain it. */
+	vTaskResume( xHighPriorityMutexTask );
+
+	#if configUSE_PREEMPTION == 0
+		taskYIELD();
+	#endif
+
+	/* Ensure the task is reporting its priority as blocked and not
+	suspended (as it would have done in versions up to V7.5.3). */
+	#if( INCLUDE_eTaskGetState == 1 )
+	{
+		configASSERT( eTaskGetState( xHighPriorityMutexTask ) == eBlocked );
+	}
+	#endif /* INCLUDE_eTaskGetState */
+
+	/* This task should now have inherited the priority of the high priority
+	task as by now the high priority task will have attempted to obtain the
+	mutex. */
+	if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Attempt to set the priority of this task to the test priority -
+	between the idle priority and the medium/high test priorities, but the
+	actual priority should remain at the high priority. */
+	vTaskPrioritySet( NULL, genqMUTEX_TEST_PRIORITY );
+	if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Now unsuspend the medium priority task.  This should not run as the
+	inherited priority of this task is above that of the medium priority
+	task. */
+	vTaskResume( xMediumPriorityMutexTask );
+
+	/* If the medium priority task did run then it will have incremented the
+	guarded variable. */
+	if( ulGuardedVariable != 0 )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Take the local mutex too, so two mutexes are now held. */
+	if( xSemaphoreTake( xLocalMutex, intsemNO_BLOCK ) != pdPASS )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* When the semaphore is given back the priority of this task should not
+	yet be disinherited because the local mutex is still held.  This is a
+	simplification to allow FreeRTOS to be integrated with middleware that
+	attempts to hold multiple mutexes without bloating the code with complex
+	algorithms.  It is possible that the high priority mutex task will
+	execute as it shares a priority with this task. */
+	if( xSemaphoreGive( xMutex ) != pdPASS )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	#if configUSE_PREEMPTION == 0
+		taskYIELD();
+	#endif
+
+	/* The guarded variable is only incremented by the medium priority task,
+	which still should not have executed as this task should remain at the
+	higher priority, ensure this is the case. */
+	if( ulGuardedVariable != 0 )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Now also give back the local mutex, taking the held count back to 0.
+	This time the priority of this task should be disinherited back to the
+	priority to which it was set while the mutex was held.  This means
+	the medium priority task should execute and increment the guarded
+	variable.   When this task next	runs both the high and medium priority
+	tasks will have been suspended again. */
+	if( xSemaphoreGive( xLocalMutex ) != pdPASS )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	#if configUSE_PREEMPTION == 0
+		taskYIELD();
+	#endif
+
+	/* Check the guarded variable did indeed increment... */
+	if( ulGuardedVariable != 1 )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* ... and that the priority of this task has been disinherited to
+	genqMUTEX_TEST_PRIORITY. */
+	if( uxTaskPriorityGet( NULL ) != genqMUTEX_TEST_PRIORITY )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Set the priority of this task back to its original value, ready for
+	the next loop around this test. */
+	vTaskPrioritySet( NULL, genqMUTEX_LOW_PRIORITY );
+}
+/*-----------------------------------------------------------*/
+
+static void prvTakeTwoMutexesReturnInSameOrder( SemaphoreHandle_t xMutex, SemaphoreHandle_t xLocalMutex )
+{
+	/* Take the mutex.  It should be available now. */
+	if( xSemaphoreTake( xMutex, intsemNO_BLOCK ) != pdPASS )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Set the guarded variable to a known start value. */
+	ulGuardedVariable = 0;
+
+	/* This task's priority should be as per that assigned when the task was
+	created. */
+	if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Now unsuspend the high priority task.  This will attempt to take the
+	mutex, and block when it finds it cannot obtain it. */
+	vTaskResume( xHighPriorityMutexTask );
+
+	#if configUSE_PREEMPTION == 0
+		taskYIELD();
+	#endif
+
+	/* Ensure the task is reporting its priority as blocked and not
+	suspended (as it would have done in versions up to V7.5.3). */
+	#if( INCLUDE_eTaskGetState == 1 )
+	{
+		configASSERT( eTaskGetState( xHighPriorityMutexTask ) == eBlocked );
+	}
+	#endif /* INCLUDE_eTaskGetState */
+
+	/* This task should now have inherited the priority of the high priority
+	task as by now the high priority task will have attempted to obtain the
+	mutex. */
+	if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Now unsuspend the medium priority task.  This should not run as the
+	inherited priority of this task is above that of the medium priority
+	task. */
+	vTaskResume( xMediumPriorityMutexTask );
+
+	/* If the medium priority task did run then it will have incremented the
+	guarded variable. */
+	if( ulGuardedVariable != 0 )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Take the local mutex too, so two mutexes are now held. */
+	if( xSemaphoreTake( xLocalMutex, intsemNO_BLOCK ) != pdPASS )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* When the local semaphore is given back the priority of this task should
+	not yet be disinherited because the shared mutex is still held.  This is a
+	simplification to allow FreeRTOS to be integrated with middleware that
+	attempts to hold multiple mutexes without bloating the code with complex
+	algorithms.  It is possible that the high priority mutex task will
+	execute as it shares a priority with this task. */
+	if( xSemaphoreGive( xLocalMutex ) != pdPASS )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	#if configUSE_PREEMPTION == 0
+		taskYIELD();
+	#endif
+
+	/* The guarded variable is only incremented by the medium priority task,
+	which still should not have executed as this task should remain at the
+	higher priority, ensure this is the case. */
+	if( ulGuardedVariable != 0 )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Now also give back the shared mutex, taking the held count back to 0.
+	This time the priority of this task should be disinherited back to the
+	priority at which it was created.  This means the medium priority task
+	should execute and increment the guarded variable.  When this task next runs
+	both the high and medium priority tasks will have been suspended again. */
+	if( xSemaphoreGive( xMutex ) != pdPASS )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	#if configUSE_PREEMPTION == 0
+		taskYIELD();
+	#endif
+
+	/* Check the guarded variable did indeed increment... */
+	if( ulGuardedVariable != 1 )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* ... and that the priority of this task has been disinherited to
+	genqMUTEX_LOW_PRIORITY. */
+	if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
+	{
+		xErrorDetected = pdTRUE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvLowPriorityMutexTask( void *pvParameters )
+{
+SemaphoreHandle_t xMutex = ( SemaphoreHandle_t ) pvParameters, xLocalMutex;
+
+	#ifdef USE_STDIO
+	void vPrintDisplayMessage( const char * const * ppcMessageToSend );
+
+		const char * const pcTaskStartMsg = "Mutex with priority inheritance test started.\r\n";
+
+		/* Queue a message for printing to say the task has started. */
+		vPrintDisplayMessage( &pcTaskStartMsg );
+	#endif
+
+	/* The local mutex is used to check the 'mutexs held' count. */
+	xLocalMutex = xSemaphoreCreateMutex();
+	configASSERT( xLocalMutex );
+
+	for( ;; )
+	{
+		/* The first tests exercise the priority inheritance when two mutexes
+		are taken then returned in a different order to which they were
+		taken. */
+		prvTakeTwoMutexesReturnInDifferentOrder( xMutex, xLocalMutex );
+
+		/* Just to show this task is still running. */
+		ulLoopCounter2++;
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+		/* The second tests exercise the priority inheritance when two mutexes
+		are taken then returned in the same order in which they were taken. */
+		prvTakeTwoMutexesReturnInSameOrder( xMutex, xLocalMutex );
+
+		/* Just to show this task is still running. */
+		ulLoopCounter2++;
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+		#if( INCLUDE_xTaskAbortDelay == 1 )
+		{
+			/* Tests the behaviour when a low priority task inherits the
+			priority of a high priority task only for the high priority task to
+			timeout before obtaining the mutex. */
+			prvHighPriorityTimeout( xMutex );
+		}
+		#endif
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvMediumPriorityMutexTask( void *pvParameters )
+{
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		/* The medium priority task starts by suspending itself.  The low
+		priority task will unsuspend this task when required. */
+		vTaskSuspend( NULL );
+
+		/* When this task unsuspends all it does is increment the guarded
+		variable, this is so the low priority task knows that it has
+		executed. */
+		ulGuardedVariable++;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvHighPriorityMutexTask( void *pvParameters )
+{
+SemaphoreHandle_t xMutex = ( SemaphoreHandle_t ) pvParameters;
+
+	for( ;; )
+	{
+		/* The high priority task starts by suspending itself.  The low
+		priority task will unsuspend this task when required. */
+		vTaskSuspend( NULL );
+
+		/* When this task unsuspends all it does is attempt to obtain the
+		mutex.  It should find the mutex is not available so a block time is
+		specified. */
+		if( xSemaphoreTake( xMutex, portMAX_DELAY ) != pdPASS )
+		{
+			/* This task would expect to obtain the mutex unless its wait for
+			the mutex was aborted. */
+			if( xBlockWasAborted == pdFALSE )
+			{
+				xErrorDetected = pdTRUE;
+			}
+			else
+			{
+				xBlockWasAborted = pdFALSE;
+			}
+		}
+		else
+		{
+			/* When the mutex is eventually obtained it is just given back before
+			returning to suspend ready for the next cycle. */
+			if( xSemaphoreGive( xMutex ) != pdPASS )
+			{
+				xErrorDetected = pdTRUE;
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+
+/* This is called to check that all the created tasks are still running. */
+BaseType_t xAreGenericQueueTasksStillRunning( void )
+{
+static uint32_t ulLastLoopCounter = 0, ulLastLoopCounter2 = 0;
+
+	/* If the demo task is still running then we expect the loop counters to
+	have incremented since this function was last called. */
+	if( ulLastLoopCounter == ulLoopCounter )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	if( ulLastLoopCounter2 == ulLoopCounter2 )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	ulLastLoopCounter = ulLoopCounter;
+	ulLastLoopCounter2 = ulLoopCounter2;
+
+	/* Errors detected in the task itself will have latched xErrorDetected
+	to true. */
+
+	return ( BaseType_t ) !xErrorDetected;
+}
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/IntQueue.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/IntQueue.c
new file mode 100644
index 0000000..d6e823e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/IntQueue.c
@@ -0,0 +1,727 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * This file defines one of the more complex set of demo/test tasks.  They are
+ * designed to stress test the queue implementation though pseudo simultaneous
+ * multiple reads and multiple writes from both tasks of varying priority and
+ * interrupts.  The interrupts are prioritised such to ensure that nesting
+ * occurs (for those ports that support it).
+ *
+ * The test ensures that, while being accessed from three tasks and two
+ * interrupts, all the data sent to the queues is also received from
+ * the same queue, and that no duplicate items are either sent or received.
+ * The tests also ensure that a low priority task is never able to successfully
+ * read from or write to a queue when a task of higher priority is attempting
+ * the same operation.
+ */
+
+/* Standard includes. */
+#include 
+
+/* SafeRTOS includes. */
+#include "FreeRTOS.h"
+#include "queue.h"
+#include "task.h"
+
+/* Demo app includes. */
+#include "IntQueue.h"
+#include "IntQueueTimer.h"
+
+#if( INCLUDE_eTaskGetState != 1 )
+	#error INCLUDE_eTaskGetState must be set to 1 in FreeRTOSConfig.h to use this demo file.
+#endif
+
+/* Priorities used by test tasks. */
+#ifndef intqHIGHER_PRIORITY
+	#define intqHIGHER_PRIORITY		( configMAX_PRIORITIES - 2 )
+#endif
+#define intqLOWER_PRIORITY		( tskIDLE_PRIORITY )
+
+/* The number of values to send/receive before checking that all values were
+processed as expected. */
+#define intqNUM_VALUES_TO_LOG	( 200 )
+#define intqSHORT_DELAY			( 140 )
+
+/* The value by which the value being sent to or received from a queue should
+increment past intqNUM_VALUES_TO_LOG before we check that all values have been
+sent/received correctly.  This is done to ensure that all tasks and interrupts
+accessing the queue have completed their accesses with the
+intqNUM_VALUES_TO_LOG range. */
+#define intqVALUE_OVERRUN		( 50 )
+
+/* The delay used by the polling task.  A short delay is used for code
+coverage. */
+#define intqONE_TICK_DELAY		( 1 )
+
+/* Each task and interrupt is given a unique identifier.  This value is used to
+identify which task sent or received each value.  The identifier is also used
+to distinguish between two tasks that are running the same task function. */
+#define intqHIGH_PRIORITY_TASK1	( ( UBaseType_t ) 1 )
+#define intqHIGH_PRIORITY_TASK2	( ( UBaseType_t ) 2 )
+#define intqLOW_PRIORITY_TASK	( ( UBaseType_t ) 3 )
+#define intqFIRST_INTERRUPT		( ( UBaseType_t ) 4 )
+#define intqSECOND_INTERRUPT	( ( UBaseType_t ) 5 )
+#define intqQUEUE_LENGTH		( ( UBaseType_t ) 10 )
+
+/* At least intqMIN_ACCEPTABLE_TASK_COUNT values should be sent to/received
+from each queue by each task, otherwise an error is detected. */
+#define intqMIN_ACCEPTABLE_TASK_COUNT		( 5 )
+
+/* Send the next value to the queue that is normally empty.  This is called
+from within the interrupts. */
+#define timerNORMALLY_EMPTY_TX()																							\
+	if( xQueueIsQueueFullFromISR( xNormallyEmptyQueue ) != pdTRUE )															\
+	{																														\
+	UBaseType_t uxSavedInterruptStatus;																						\
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();															\
+		{																													\
+			uxValueForNormallyEmptyQueue++;																					\
+			if( xQueueSendFromISR( xNormallyEmptyQueue, ( void * ) &uxValueForNormallyEmptyQueue, &xHigherPriorityTaskWoken ) != pdPASS ) \
+			{																												\
+				uxValueForNormallyEmptyQueue--;																				\
+			}																												\
+		}																													\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );														\
+	}																														\
+
+/* Send the next value to the queue that is normally full.  This is called
+from within the interrupts. */
+#define timerNORMALLY_FULL_TX()																								\
+	if( xQueueIsQueueFullFromISR( xNormallyFullQueue ) != pdTRUE )															\
+	{																														\
+	UBaseType_t uxSavedInterruptStatus;																						\
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();															\
+		{																													\
+			uxValueForNormallyFullQueue++;																					\
+			if( xQueueSendFromISR( xNormallyFullQueue, ( void * ) &uxValueForNormallyFullQueue, &xHigherPriorityTaskWoken ) != pdPASS ) \
+			{																												\
+				uxValueForNormallyFullQueue--;																				\
+			} 																												\
+		}																													\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );														\
+	}																														\
+
+/* Receive a value from the normally empty queue.  This is called from within
+an interrupt. */
+#define timerNORMALLY_EMPTY_RX()																			\
+	if( xQueueReceiveFromISR( xNormallyEmptyQueue, &uxRxedValue, &xHigherPriorityTaskWoken ) != pdPASS )	\
+	{																										\
+		prvQueueAccessLogError( __LINE__ );																	\
+	}																										\
+	else																									\
+	{																										\
+		prvRecordValue_NormallyEmpty( uxRxedValue, intqSECOND_INTERRUPT );									\
+	}
+
+/* Receive a value from the normally full queue.  This is called from within
+an interrupt. */
+#define timerNORMALLY_FULL_RX()																				\
+	if( xQueueReceiveFromISR( xNormallyFullQueue, &uxRxedValue, &xHigherPriorityTaskWoken ) == pdPASS )		\
+	{																										\
+		prvRecordValue_NormallyFull( uxRxedValue, intqSECOND_INTERRUPT );									\
+	}																										\
+
+
+/*-----------------------------------------------------------*/
+
+/* The two queues used by the test. */
+static QueueHandle_t xNormallyEmptyQueue, xNormallyFullQueue;
+
+/* Variables used to detect a stall in one of the tasks. */
+static volatile UBaseType_t uxHighPriorityLoops1 = 0, uxHighPriorityLoops2 = 0, uxLowPriorityLoops1 = 0, uxLowPriorityLoops2 = 0;
+
+/* Any unexpected behaviour sets xErrorStatus to fail and log the line that
+caused the error in xErrorLine. */
+static BaseType_t xErrorStatus = pdPASS;
+static volatile UBaseType_t xErrorLine = ( UBaseType_t ) 0;
+
+/* Used for sequencing between tasks. */
+static BaseType_t xWasSuspended = pdFALSE;
+
+/* The values that are sent to the queues.  An incremented value is sent each
+time to each queue. */
+static volatile UBaseType_t uxValueForNormallyEmptyQueue = 0, uxValueForNormallyFullQueue = 0;
+
+/* A handle to some of the tasks is required so they can be suspended/resumed. */
+TaskHandle_t xHighPriorityNormallyEmptyTask1, xHighPriorityNormallyEmptyTask2, xHighPriorityNormallyFullTask1, xHighPriorityNormallyFullTask2;
+
+/* When a value is received in a queue the value is ticked off in the array
+the array position of the value is set to a the identifier of the task or
+interrupt that accessed the queue.  This way missing or duplicate values can be
+detected. */
+static uint8_t ucNormallyEmptyReceivedValues[ intqNUM_VALUES_TO_LOG ] = { 0 };
+static uint8_t ucNormallyFullReceivedValues[ intqNUM_VALUES_TO_LOG ] = { 0 };
+
+/* The test tasks themselves. */
+static void prvLowerPriorityNormallyEmptyTask( void *pvParameters );
+static void prvLowerPriorityNormallyFullTask( void *pvParameters );
+static void prvHigherPriorityNormallyEmptyTask( void *pvParameters );
+static void prv1stHigherPriorityNormallyFullTask( void *pvParameters );
+static void prv2ndHigherPriorityNormallyFullTask( void *pvParameters );
+
+/* Used to mark the positions within the ucNormallyEmptyReceivedValues and
+ucNormallyFullReceivedValues arrays, while checking for duplicates. */
+static void prvRecordValue_NormallyEmpty( UBaseType_t uxValue, UBaseType_t uxSource );
+static void prvRecordValue_NormallyFull( UBaseType_t uxValue, UBaseType_t uxSource );
+
+/* Logs the line on which an error occurred. */
+static void prvQueueAccessLogError( UBaseType_t uxLine );
+
+/*-----------------------------------------------------------*/
+
+void vStartInterruptQueueTasks( void )
+{
+	/* Start the test tasks. */
+	xTaskCreate( prvHigherPriorityNormallyEmptyTask, "H1QRx", configMINIMAL_STACK_SIZE, ( void * ) intqHIGH_PRIORITY_TASK1, intqHIGHER_PRIORITY, &xHighPriorityNormallyEmptyTask1 );
+	xTaskCreate( prvHigherPriorityNormallyEmptyTask, "H2QRx", configMINIMAL_STACK_SIZE, ( void * ) intqHIGH_PRIORITY_TASK2, intqHIGHER_PRIORITY, &xHighPriorityNormallyEmptyTask2 );
+	xTaskCreate( prvLowerPriorityNormallyEmptyTask, "L1QRx", configMINIMAL_STACK_SIZE, NULL, intqLOWER_PRIORITY, NULL );
+	xTaskCreate( prv1stHigherPriorityNormallyFullTask, "H1QTx", configMINIMAL_STACK_SIZE, ( void * ) intqHIGH_PRIORITY_TASK1, intqHIGHER_PRIORITY, &xHighPriorityNormallyFullTask1 );
+	xTaskCreate( prv2ndHigherPriorityNormallyFullTask, "H2QTx", configMINIMAL_STACK_SIZE, ( void * ) intqHIGH_PRIORITY_TASK2, intqHIGHER_PRIORITY, &xHighPriorityNormallyFullTask2 );
+	xTaskCreate( prvLowerPriorityNormallyFullTask, "L2QRx", configMINIMAL_STACK_SIZE, NULL, intqLOWER_PRIORITY, NULL );
+
+	/* Create the queues that are accessed by multiple tasks and multiple
+	interrupts. */
+	xNormallyFullQueue = xQueueCreate( intqQUEUE_LENGTH, ( UBaseType_t ) sizeof( UBaseType_t ) );
+	xNormallyEmptyQueue = xQueueCreate( intqQUEUE_LENGTH, ( UBaseType_t ) sizeof( UBaseType_t ) );
+
+	/* vQueueAddToRegistry() adds the queue to the queue registry, if one is
+	in use.  The queue registry is provided as a means for kernel aware
+	debuggers to locate queues and has no purpose if a kernel aware debugger
+	is not being used.  The call to vQueueAddToRegistry() will be removed
+	by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is
+	defined to be less than 1. */
+	vQueueAddToRegistry( xNormallyFullQueue, "NormallyFull" );
+	vQueueAddToRegistry( xNormallyEmptyQueue, "NormallyEmpty" );
+}
+/*-----------------------------------------------------------*/
+
+static void prvRecordValue_NormallyFull( UBaseType_t uxValue, UBaseType_t uxSource )
+{
+	if( uxValue < intqNUM_VALUES_TO_LOG )
+	{
+		/* We don't expect to receive the same value twice, so if the value
+		has already been marked as received an error has occurred. */
+		if( ucNormallyFullReceivedValues[ uxValue ] != 0x00 )
+		{
+			prvQueueAccessLogError( __LINE__ );
+		}
+
+		/* Log that this value has been received. */
+		ucNormallyFullReceivedValues[ uxValue ] = ( uint8_t ) uxSource;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvRecordValue_NormallyEmpty( UBaseType_t uxValue, UBaseType_t uxSource )
+{
+	if( uxValue < intqNUM_VALUES_TO_LOG )
+	{
+		/* We don't expect to receive the same value twice, so if the value
+		has already been marked as received an error has occurred. */
+		if( ucNormallyEmptyReceivedValues[ uxValue ] != 0x00 )
+		{
+			prvQueueAccessLogError( __LINE__ );
+		}
+
+		/* Log that this value has been received. */
+		ucNormallyEmptyReceivedValues[ uxValue ] = ( uint8_t ) uxSource;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueAccessLogError( UBaseType_t uxLine )
+{
+	/* Latch the line number that caused the error. */
+	xErrorLine = uxLine;
+	xErrorStatus = pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+static void prvHigherPriorityNormallyEmptyTask( void *pvParameters )
+{
+UBaseType_t uxRxed, ux, uxTask1, uxTask2, uxInterrupts, uxErrorCount1 = 0, uxErrorCount2 = 0;
+
+	/* The timer should not be started until after the scheduler has started.
+	More than one task is running this code so we check the parameter value
+	to determine which task should start the timer. */
+	if( ( UBaseType_t ) pvParameters == intqHIGH_PRIORITY_TASK1 )
+	{
+		vInitialiseTimerForIntQueueTest();
+	}
+
+	for( ;; )
+	{
+		/* Block waiting to receive a value from the normally empty queue.
+		Interrupts will write to the queue so we should receive a value. */
+		if( xQueueReceive( xNormallyEmptyQueue, &uxRxed, intqSHORT_DELAY ) != pdPASS )
+		{
+			prvQueueAccessLogError( __LINE__ );
+		}
+		else
+		{
+			/* Note which value was received so we can check all expected
+			values are received and no values are duplicated. */
+			prvRecordValue_NormallyEmpty( uxRxed, ( UBaseType_t ) pvParameters );
+		}
+
+		/* Ensure the other task running this code gets a chance to execute. */
+		taskYIELD();
+
+		if( ( UBaseType_t ) pvParameters == intqHIGH_PRIORITY_TASK1 )
+		{
+			/* Have we received all the expected values? */
+			if( uxValueForNormallyEmptyQueue > ( intqNUM_VALUES_TO_LOG + intqVALUE_OVERRUN ) )
+			{
+				vTaskSuspend( xHighPriorityNormallyEmptyTask2 );
+
+				uxTask1 = 0;
+				uxTask2 = 0;
+				uxInterrupts = 0;
+
+				/* Loop through the array, checking that both tasks have
+				placed values into the array, and that no values are missing.
+				Start at 1 as we expect position 0 to be unused. */
+				for( ux = 1; ux < intqNUM_VALUES_TO_LOG; ux++ )
+				{
+					if( ucNormallyEmptyReceivedValues[ ux ] == 0 )
+					{
+						/* A value is missing. */
+						prvQueueAccessLogError( __LINE__ );
+					}
+					else
+					{
+						if( ucNormallyEmptyReceivedValues[ ux ] == intqHIGH_PRIORITY_TASK1 )
+						{
+							/* Value was placed into the array by task 1. */
+							uxTask1++;
+						}
+						else if( ucNormallyEmptyReceivedValues[ ux ] == intqHIGH_PRIORITY_TASK2 )
+						{
+							/* Value was placed into the array by task 2. */
+							uxTask2++;
+						}
+						else if( ucNormallyEmptyReceivedValues[ ux ] == intqSECOND_INTERRUPT )
+						{
+							uxInterrupts++;
+						}
+					}
+				}
+
+				if( uxTask1 < intqMIN_ACCEPTABLE_TASK_COUNT )
+				{
+					/* Only task 2 seemed to log any values. */
+					uxErrorCount1++;
+					if( uxErrorCount1 > 2 )
+					{
+						prvQueueAccessLogError( __LINE__ );
+					}
+				}
+				else
+				{
+					uxErrorCount1 = 0;
+				}
+
+				if( uxTask2 < intqMIN_ACCEPTABLE_TASK_COUNT  )
+				{
+					/* Only task 1 seemed to log any values. */
+					uxErrorCount2++;
+					if( uxErrorCount2 > 2 )
+					{
+						prvQueueAccessLogError( __LINE__ );
+					}
+				}
+				else
+				{
+					uxErrorCount2 = 0;
+				}
+
+				if( uxInterrupts == 0 )
+				{
+					prvQueueAccessLogError( __LINE__ );
+				}
+
+				/* Clear the array again, ready to start a new cycle. */
+				memset( ucNormallyEmptyReceivedValues, 0x00, sizeof( ucNormallyEmptyReceivedValues ) );
+
+				uxHighPriorityLoops1++;
+				uxValueForNormallyEmptyQueue = 0;
+
+				/* Suspend ourselves, allowing the lower priority task to
+				actually receive something from the queue.  Until now it
+				will have been prevented from doing so by the higher
+				priority tasks.  The lower priority task will resume us
+				if it receives something.  We will then resume the other
+				higher priority task. */
+				vTaskSuspend( NULL );
+				vTaskResume( xHighPriorityNormallyEmptyTask2 );
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvLowerPriorityNormallyEmptyTask( void *pvParameters )
+{
+UBaseType_t uxValue, uxRxed;
+
+	/* The parameters are not being used so avoid compiler warnings. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		if( xQueueReceive( xNormallyEmptyQueue, &uxRxed, intqONE_TICK_DELAY ) != errQUEUE_EMPTY )
+		{
+			/* A value should only be obtained when the high priority task is
+			suspended. */
+			if( eTaskGetState( xHighPriorityNormallyEmptyTask1 ) != eSuspended )
+			{
+				prvQueueAccessLogError( __LINE__ );
+			}
+
+			prvRecordValue_NormallyEmpty( uxRxed, intqLOW_PRIORITY_TASK );
+
+			/* Wake the higher priority task again. */
+			vTaskResume( xHighPriorityNormallyEmptyTask1 );
+			uxLowPriorityLoops1++;
+		}
+		else
+		{
+			/* Raise our priority while we send so we can preempt the higher
+			priority task, and ensure we get the Tx value into the queue. */
+			vTaskPrioritySet( NULL, intqHIGHER_PRIORITY + 1 );
+
+			portENTER_CRITICAL();
+			{
+				uxValueForNormallyEmptyQueue++;
+				uxValue = uxValueForNormallyEmptyQueue;
+			}
+			portEXIT_CRITICAL();
+
+			if( xQueueSend( xNormallyEmptyQueue, &uxValue, portMAX_DELAY ) != pdPASS )
+			{
+				prvQueueAccessLogError( __LINE__ );
+			}
+
+			vTaskPrioritySet( NULL, intqLOWER_PRIORITY );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prv1stHigherPriorityNormallyFullTask( void *pvParameters )
+{
+UBaseType_t uxValueToTx, ux, uxInterrupts;
+
+	/* The parameters are not being used so avoid compiler warnings. */
+	( void ) pvParameters;
+
+	/* Make sure the queue starts full or near full.  >> 1 as there are two
+	high priority tasks. */
+	for( ux = 0; ux < ( intqQUEUE_LENGTH >> 1 ); ux++ )
+	{
+		portENTER_CRITICAL();
+		{
+			uxValueForNormallyFullQueue++;
+			uxValueToTx = uxValueForNormallyFullQueue;
+		}
+		portEXIT_CRITICAL();
+
+		xQueueSend( xNormallyFullQueue, &uxValueToTx, intqSHORT_DELAY );
+	}
+
+	for( ;; )
+	{
+		portENTER_CRITICAL();
+		{
+			uxValueForNormallyFullQueue++;
+			uxValueToTx = uxValueForNormallyFullQueue;
+		}
+		portEXIT_CRITICAL();
+
+		if( xQueueSend( xNormallyFullQueue, &uxValueToTx, intqSHORT_DELAY ) != pdPASS )
+		{
+			/* intqHIGH_PRIORITY_TASK2 is never suspended so we would not
+			expect it to ever time out. */
+			prvQueueAccessLogError( __LINE__ );
+		}
+
+		/* Allow the other task running this code to run. */
+		taskYIELD();
+
+		/* Have all the expected values been sent to the queue? */
+		if( uxValueToTx > ( intqNUM_VALUES_TO_LOG + intqVALUE_OVERRUN ) )
+		{
+			/* Make sure the other high priority task completes its send of
+			any values below intqNUM_VALUE_TO_LOG. */
+			vTaskDelay( intqSHORT_DELAY );
+
+			vTaskSuspend( xHighPriorityNormallyFullTask2 );
+
+			if( xWasSuspended == pdTRUE )
+			{
+				/* We would have expected the other high priority task to have
+				set this back to false by now. */
+				prvQueueAccessLogError( __LINE__ );
+			}
+
+			/* Set the suspended flag so an error is not logged if the other
+			task recognises a time out when it is unsuspended. */
+			xWasSuspended = pdTRUE;
+
+			/* Check interrupts are also sending. */
+			uxInterrupts = 0U;
+
+			/* Start at 1 as we expect position 0 to be unused. */
+			for( ux = 1; ux < intqNUM_VALUES_TO_LOG; ux++ )
+			{
+				if( ucNormallyFullReceivedValues[ ux ] == 0 )
+				{
+					/* A value was missing. */
+					prvQueueAccessLogError( __LINE__ );
+				}
+				else if( ucNormallyFullReceivedValues[ ux ] == intqSECOND_INTERRUPT )
+				{
+					uxInterrupts++;
+				}
+			}
+
+			if( uxInterrupts == 0 )
+			{
+				/* No writes from interrupts were found.  Are interrupts
+				actually running? */
+				prvQueueAccessLogError( __LINE__ );
+			}
+
+			/* Reset the array ready for the next cycle. */
+			memset( ucNormallyFullReceivedValues, 0x00, sizeof( ucNormallyFullReceivedValues ) );
+
+			uxHighPriorityLoops2++;
+			uxValueForNormallyFullQueue = 0;
+
+			/* Suspend ourselves, allowing the lower priority task to
+			actually receive something from the queue.  Until now it
+			will have been prevented from doing so by the higher
+			priority tasks.  The lower priority task will resume us
+			if it receives something.  We will then resume the other
+			higher priority task. */
+			vTaskSuspend( NULL );
+			vTaskResume( xHighPriorityNormallyFullTask2 );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prv2ndHigherPriorityNormallyFullTask( void *pvParameters )
+{
+UBaseType_t uxValueToTx, ux;
+
+	/* The parameters are not being used so avoid compiler warnings. */
+	( void ) pvParameters;
+
+	/* Make sure the queue starts full or near full.  >> 1 as there are two
+	high priority tasks. */
+	for( ux = 0; ux < ( intqQUEUE_LENGTH >> 1 ); ux++ )
+	{
+		portENTER_CRITICAL();
+		{
+			uxValueForNormallyFullQueue++;
+			uxValueToTx = uxValueForNormallyFullQueue;
+		}
+		portEXIT_CRITICAL();
+
+		xQueueSend( xNormallyFullQueue, &uxValueToTx, intqSHORT_DELAY );
+	}
+
+	for( ;; )
+	{
+		portENTER_CRITICAL();
+		{
+			uxValueForNormallyFullQueue++;
+			uxValueToTx = uxValueForNormallyFullQueue;
+		}
+		portEXIT_CRITICAL();
+
+		if( xQueueSend( xNormallyFullQueue, &uxValueToTx, intqSHORT_DELAY ) != pdPASS )
+		{
+			if( xWasSuspended != pdTRUE )
+			{
+				/* It is ok to time out if the task has been suspended. */
+				prvQueueAccessLogError( __LINE__ );
+			}
+		}
+
+		xWasSuspended = pdFALSE;
+
+		taskYIELD();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvLowerPriorityNormallyFullTask( void *pvParameters )
+{
+UBaseType_t uxValue, uxTxed = 9999;
+
+	/* The parameters are not being used so avoid compiler warnings. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		if( xQueueSend( xNormallyFullQueue, &uxTxed, intqONE_TICK_DELAY ) != errQUEUE_FULL )
+		{
+			/* Should only succeed when the higher priority task is suspended */
+			if( eTaskGetState( xHighPriorityNormallyFullTask1 ) != eSuspended )
+			{
+				prvQueueAccessLogError( __LINE__ );
+			}
+
+			vTaskResume( xHighPriorityNormallyFullTask1 );
+			uxLowPriorityLoops2++;
+		}
+		else
+		{
+			/* Raise our priority while we receive so we can preempt the higher
+			priority task, and ensure we get the value from the queue. */
+			vTaskPrioritySet( NULL, intqHIGHER_PRIORITY + 1 );
+
+			if( xQueueReceive( xNormallyFullQueue, &uxValue, portMAX_DELAY ) != pdPASS )
+			{
+				prvQueueAccessLogError( __LINE__ );
+			}
+			else
+			{
+				prvRecordValue_NormallyFull( uxValue, intqLOW_PRIORITY_TASK );
+			}
+
+			vTaskPrioritySet( NULL, intqLOWER_PRIORITY );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xFirstTimerHandler( void )
+{
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+UBaseType_t uxRxedValue;
+static UBaseType_t uxNextOperation = 0;
+
+	/* Called from a timer interrupt.  Perform various read and write
+	accesses on the queues. */
+
+	uxNextOperation++;
+
+	if( uxNextOperation & ( UBaseType_t ) 0x01 )
+	{
+		timerNORMALLY_EMPTY_TX();
+		timerNORMALLY_EMPTY_TX();
+		timerNORMALLY_EMPTY_TX();
+	}
+	else
+	{
+		timerNORMALLY_FULL_RX();
+		timerNORMALLY_FULL_RX();
+		timerNORMALLY_FULL_RX();
+	}
+
+	return xHigherPriorityTaskWoken;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xSecondTimerHandler( void )
+{
+UBaseType_t uxRxedValue;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+static UBaseType_t uxNextOperation = 0;
+
+	/* Called from a timer interrupt.  Perform various read and write
+	accesses on the queues. */
+
+	uxNextOperation++;
+
+	if( uxNextOperation & ( UBaseType_t ) 0x01 )
+	{
+		timerNORMALLY_EMPTY_TX();
+		timerNORMALLY_EMPTY_TX();
+
+		timerNORMALLY_EMPTY_RX();
+		timerNORMALLY_EMPTY_RX();
+	}
+	else
+	{
+		timerNORMALLY_FULL_RX();
+		timerNORMALLY_FULL_TX();
+		timerNORMALLY_FULL_TX();
+		timerNORMALLY_FULL_TX();
+	}
+
+	return xHigherPriorityTaskWoken;
+}
+/*-----------------------------------------------------------*/
+
+
+BaseType_t xAreIntQueueTasksStillRunning( void )
+{
+static UBaseType_t uxLastHighPriorityLoops1 = 0, uxLastHighPriorityLoops2 = 0, uxLastLowPriorityLoops1 = 0, uxLastLowPriorityLoops2 = 0;
+
+	/* xErrorStatus can be set outside of this function.  This function just
+	checks that all the tasks are still cycling. */
+
+	if( uxHighPriorityLoops1 == uxLastHighPriorityLoops1 )
+	{
+		/* The high priority 1 task has stalled. */
+		prvQueueAccessLogError( __LINE__ );
+	}
+
+	uxLastHighPriorityLoops1 = uxHighPriorityLoops1;
+
+	if( uxHighPriorityLoops2 == uxLastHighPriorityLoops2 )
+	{
+		/* The high priority 2 task has stalled. */
+		prvQueueAccessLogError( __LINE__ );
+	}
+
+	uxLastHighPriorityLoops2 = uxHighPriorityLoops2;
+
+	if( uxLowPriorityLoops1 == uxLastLowPriorityLoops1 )
+	{
+		/* The low priority 1 task has stalled. */
+		prvQueueAccessLogError( __LINE__ );
+	}
+
+	uxLastLowPriorityLoops1 = uxLowPriorityLoops1;
+
+	if( uxLowPriorityLoops2 == uxLastLowPriorityLoops2 )
+	{
+		/* The low priority 2 task has stalled. */
+		prvQueueAccessLogError( __LINE__ );
+	}
+
+	uxLastLowPriorityLoops2 = uxLowPriorityLoops2;
+
+	return xErrorStatus;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/IntSemTest.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/IntSemTest.c
new file mode 100644
index 0000000..884f719
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/IntSemTest.c
@@ -0,0 +1,525 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*
+ * Demonstrates and tests mutexes being used from an interrupt.
+ */
+
+
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+
+/* Demo program include files. */
+#include "IntSemTest.h"
+
+/*-----------------------------------------------------------*/
+
+/* The priorities of the test tasks. */
+#define intsemMASTER_PRIORITY		( tskIDLE_PRIORITY )
+#define intsemSLAVE_PRIORITY		( tskIDLE_PRIORITY + 1 )
+
+/* The rate at which the tick hook will give the mutex. */
+#define intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS ( 100 )
+
+/* A block time of 0 means 'don't block'. */
+#define intsemNO_BLOCK				0
+
+/* The maximum count value for the counting semaphore given from an
+interrupt. */
+#define intsemMAX_COUNT				3
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The master is a task that receives a mutex that is given from an interrupt -
+ * although generally mutexes should not be used given in interrupts (and
+ * definitely never taken in an interrupt) there are some circumstances when it
+ * may be desirable.
+ *
+ * The slave task is just used by the master task to force priority inheritance
+ * on a mutex that is shared between the master and the slave - which is a
+ * separate mutex to that given by the interrupt.
+ */
+static void vInterruptMutexSlaveTask( void *pvParameters );
+static void vInterruptMutexMasterTask( void *pvParameters );
+
+/*
+ * A test whereby the master takes the shared and interrupt mutexes in that
+ * order, then gives them back in the same order, ensuring the priority
+ * inheritance is behaving as expected at each step.
+ */
+static void prvTakeAndGiveInTheSameOrder( void );
+
+/*
+ * A test whereby the master takes the shared and interrupt mutexes in that
+ * order, then gives them back in the opposite order to which they were taken,
+ * ensuring the priority inheritance is behaving as expected at each step.
+ */
+static void prvTakeAndGiveInTheOppositeOrder( void );
+
+/*
+ * A simple task that interacts with an interrupt using a counting semaphore,
+ * primarily for code coverage purposes.
+ */
+static void vInterruptCountingSemaphoreTask( void *pvParameters );
+
+/*-----------------------------------------------------------*/
+
+/* Flag that will be latched to pdTRUE should any unexpected behaviour be
+detected in any of the tasks. */
+static volatile BaseType_t xErrorDetected = pdFALSE;
+
+/* Counters that are incremented on each cycle of a test.  This is used to
+detect a stalled task - a test that is no longer running. */
+static volatile uint32_t ulMasterLoops = 0, ulCountingSemaphoreLoops = 0;
+
+/* Handles of the test tasks that must be accessed from other test tasks. */
+static TaskHandle_t xSlaveHandle;
+
+/* A mutex which is given from an interrupt - although generally mutexes should
+not be used given in interrupts (and definitely never taken in an interrupt)
+there are some circumstances when it may be desirable. */
+static SemaphoreHandle_t xISRMutex = NULL;
+
+/* A counting semaphore which is given from an interrupt. */
+static SemaphoreHandle_t xISRCountingSemaphore = NULL;
+
+/* A mutex which is shared between the master and slave tasks - the master
+does both sharing of this mutex with the slave and receiving a mutex from the
+interrupt. */
+static SemaphoreHandle_t xMasterSlaveMutex = NULL;
+
+/* Flag that allows the master task to control when the interrupt gives or does
+not give the mutex.  There is no mutual exclusion on this variable, but this is
+only test code and it should be fine in the 32=bit test environment. */
+static BaseType_t xOkToGiveMutex = pdFALSE, xOkToGiveCountingSemaphore = pdFALSE;
+
+/* Used to coordinate timing between tasks and the interrupt. */
+const TickType_t xInterruptGivePeriod = pdMS_TO_TICKS( intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS );
+
+/*-----------------------------------------------------------*/
+
+void vStartInterruptSemaphoreTasks( void )
+{
+	/* Create the semaphores that are given from an interrupt. */
+	xISRMutex = xSemaphoreCreateMutex();
+	configASSERT( xISRMutex );
+	xISRCountingSemaphore = xSemaphoreCreateCounting( intsemMAX_COUNT, 0 );
+	configASSERT( xISRCountingSemaphore );
+
+	/* Create the mutex that is shared between the master and slave tasks (the
+	master receives a mutex from an interrupt and shares a mutex with the
+	slave. */
+	xMasterSlaveMutex = xSemaphoreCreateMutex();
+	configASSERT( xMasterSlaveMutex );
+
+	/* Create the tasks that share mutexes between then and with interrupts. */
+	xTaskCreate( vInterruptMutexSlaveTask, "IntMuS", configMINIMAL_STACK_SIZE, NULL, intsemSLAVE_PRIORITY, &xSlaveHandle );
+	xTaskCreate( vInterruptMutexMasterTask, "IntMuM", configMINIMAL_STACK_SIZE, NULL, intsemMASTER_PRIORITY, NULL );
+
+	/* Create the task that blocks on the counting semaphore. */
+	xTaskCreate( vInterruptCountingSemaphoreTask, "IntCnt", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void vInterruptMutexMasterTask( void *pvParameters )
+{
+	/* Just to avoid compiler warnings. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		prvTakeAndGiveInTheSameOrder();
+
+		/* Ensure not to starve out other tests. */
+		ulMasterLoops++;
+		vTaskDelay( intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS );
+
+		prvTakeAndGiveInTheOppositeOrder();
+
+		/* Ensure not to starve out other tests. */
+		ulMasterLoops++;
+		vTaskDelay( intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvTakeAndGiveInTheSameOrder( void )
+{
+	/* Ensure the slave is suspended, and that this task is running at the
+	lower priority as expected as the start conditions. */
+	#if( INCLUDE_eTaskGetState == 1 )
+	{
+		configASSERT( eTaskGetState( xSlaveHandle ) == eSuspended );
+	}
+	#endif /* INCLUDE_eTaskGetState */
+
+	if( uxTaskPriorityGet( NULL ) != intsemMASTER_PRIORITY )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Take the semaphore that is shared with the slave. */
+	if( xSemaphoreTake( xMasterSlaveMutex, intsemNO_BLOCK ) != pdPASS )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* This task now has the mutex.  Unsuspend the slave so it too
+	attempts to take the mutex. */
+	vTaskResume( xSlaveHandle );
+
+	/* The slave has the higher priority so should now have executed and
+	blocked on the semaphore. */
+	#if( INCLUDE_eTaskGetState == 1 )
+	{
+		configASSERT( eTaskGetState( xSlaveHandle ) == eBlocked );
+	}
+	#endif /* INCLUDE_eTaskGetState */
+
+	/* This task should now have inherited the priority of the slave
+	task. */
+	if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Now wait a little longer than the time between ISR gives to also
+	obtain the ISR mutex. */
+	xOkToGiveMutex = pdTRUE;
+	if( xSemaphoreTake( xISRMutex, ( xInterruptGivePeriod * 2 ) ) != pdPASS )
+	{
+		xErrorDetected = pdTRUE;
+	}
+	xOkToGiveMutex = pdFALSE;
+
+	/* Attempting to take again immediately should fail as the mutex is
+	already held. */
+	if( xSemaphoreTake( xISRMutex, intsemNO_BLOCK ) != pdFAIL )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Should still be at the priority of the slave task. */
+	if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Give back the ISR semaphore to ensure the priority is not
+	disinherited as the shared mutex (which the higher priority task is
+	attempting to obtain) is still held. */
+	if( xSemaphoreGive( xISRMutex ) != pdPASS )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Finally give back the shared mutex.  This time the higher priority
+	task should run before this task runs again - so this task should have
+	disinherited the priority and the higher priority task should be in the
+	suspended state again. */
+	if( xSemaphoreGive( xMasterSlaveMutex ) != pdPASS )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	if( uxTaskPriorityGet( NULL ) != intsemMASTER_PRIORITY )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	#if( INCLUDE_eTaskGetState == 1 )
+	{
+		configASSERT( eTaskGetState( xSlaveHandle ) == eSuspended );
+	}
+	#endif /* INCLUDE_eTaskGetState */
+
+	/* Reset the mutex ready for the next round. */
+	xQueueReset( xISRMutex );
+}
+/*-----------------------------------------------------------*/
+
+static void prvTakeAndGiveInTheOppositeOrder( void )
+{
+	/* Ensure the slave is suspended, and that this task is running at the
+	lower priority as expected as the start conditions. */
+	#if( INCLUDE_eTaskGetState == 1 )
+	{
+		configASSERT( eTaskGetState( xSlaveHandle ) == eSuspended );
+	}
+	#endif /* INCLUDE_eTaskGetState */
+
+	if( uxTaskPriorityGet( NULL ) != intsemMASTER_PRIORITY )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Take the semaphore that is shared with the slave. */
+	if( xSemaphoreTake( xMasterSlaveMutex, intsemNO_BLOCK ) != pdPASS )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* This task now has the mutex.  Unsuspend the slave so it too
+	attempts to take the mutex. */
+	vTaskResume( xSlaveHandle );
+
+	/* The slave has the higher priority so should now have executed and
+	blocked on the semaphore. */
+	#if( INCLUDE_eTaskGetState == 1 )
+	{
+		configASSERT( eTaskGetState( xSlaveHandle ) == eBlocked );
+	}
+	#endif /* INCLUDE_eTaskGetState */
+
+	/* This task should now have inherited the priority of the slave
+	task. */
+	if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Now wait a little longer than the time between ISR gives to also
+	obtain the ISR mutex. */
+	xOkToGiveMutex = pdTRUE;
+	if( xSemaphoreTake( xISRMutex, ( xInterruptGivePeriod * 2 ) ) != pdPASS )
+	{
+		xErrorDetected = pdTRUE;
+	}
+	xOkToGiveMutex = pdFALSE;
+
+	/* Attempting to take again immediately should fail as the mutex is
+	already held. */
+	if( xSemaphoreTake( xISRMutex, intsemNO_BLOCK ) != pdFAIL )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Should still be at the priority of the slave task. */
+	if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Give back the shared semaphore to ensure the priority is not disinherited
+	as the ISR mutex is still held.  The higher priority slave task should run
+	before this task runs again. */
+	if( xSemaphoreGive( xMasterSlaveMutex ) != pdPASS )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Should still be at the priority of the slave task as this task still
+	holds one semaphore (this is a simplification in the priority inheritance
+	mechanism. */
+	if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Give back the ISR semaphore, which should result in the priority being
+	disinherited as it was the last mutex held. */
+	if( xSemaphoreGive( xISRMutex ) != pdPASS )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	if( uxTaskPriorityGet( NULL ) != intsemMASTER_PRIORITY )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* Reset the mutex ready for the next round. */
+	xQueueReset( xISRMutex );
+}
+/*-----------------------------------------------------------*/
+
+static void vInterruptMutexSlaveTask( void *pvParameters )
+{
+	/* Just to avoid compiler warnings. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		/* This task starts by suspending itself so when it executes can be
+		controlled by the master task. */
+		vTaskSuspend( NULL );
+
+		/* This task will execute when the master task already holds the mutex.
+		Attempting to take the mutex will place this task in the Blocked
+		state. */
+		if( xSemaphoreTake( xMasterSlaveMutex, portMAX_DELAY ) != pdPASS )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		if( xSemaphoreGive( xMasterSlaveMutex ) != pdPASS )
+		{
+			xErrorDetected = pdTRUE;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void vInterruptCountingSemaphoreTask( void *pvParameters )
+{
+BaseType_t xCount;
+const TickType_t xDelay = pdMS_TO_TICKS( intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS ) * ( intsemMAX_COUNT + 1 );
+
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		/* Expect to start with the counting semaphore empty. */
+		if( uxQueueMessagesWaiting( ( QueueHandle_t ) xISRCountingSemaphore ) != 0 )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		/* Wait until it is expected that the interrupt will have filled the
+		counting semaphore. */
+		xOkToGiveCountingSemaphore = pdTRUE;
+		vTaskDelay( xDelay );
+		xOkToGiveCountingSemaphore = pdFALSE;
+
+		/* Now it is expected that the counting semaphore is full. */
+		if( uxQueueMessagesWaiting( ( QueueHandle_t ) xISRCountingSemaphore ) != intsemMAX_COUNT )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		if( uxQueueSpacesAvailable( ( QueueHandle_t ) xISRCountingSemaphore ) != 0 )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		ulCountingSemaphoreLoops++;
+
+		/* Expect to be able to take the counting semaphore intsemMAX_COUNT
+		times.  A block time of 0 is used as the semaphore should already be
+		there. */
+		xCount = 0;
+		while( xSemaphoreTake( xISRCountingSemaphore, 0 ) == pdPASS )
+		{
+			xCount++;
+		}
+
+		if( xCount != intsemMAX_COUNT )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		/* Now raise the priority of this task so it runs immediately that the
+		semaphore is given from the interrupt. */
+		vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
+
+		/* Block to wait for the semaphore to be given from the interrupt. */
+		xOkToGiveCountingSemaphore = pdTRUE;
+		xSemaphoreTake( xISRCountingSemaphore, portMAX_DELAY );
+		xSemaphoreTake( xISRCountingSemaphore, portMAX_DELAY );
+		xOkToGiveCountingSemaphore = pdFALSE;
+
+		/* Reset the priority so as not to disturbe other tests too much. */
+		vTaskPrioritySet( NULL, tskIDLE_PRIORITY );
+
+		ulCountingSemaphoreLoops++;
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vInterruptSemaphorePeriodicTest( void )
+{
+static TickType_t xLastGiveTime = 0;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+TickType_t xTimeNow;
+
+	/* No mutual exclusion on xOkToGiveMutex, but this is only test code (and
+	only executed on a 32-bit architecture) so ignore that in this case. */
+	xTimeNow = xTaskGetTickCountFromISR();
+	if( ( ( TickType_t ) ( xTimeNow - xLastGiveTime ) ) >= pdMS_TO_TICKS( intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS ) )
+	{
+		configASSERT( xISRMutex );
+		if( xOkToGiveMutex != pdFALSE )
+		{
+			/* Null is used as the second parameter in this give, and non-NULL
+			in the other gives for code coverage reasons. */
+			xSemaphoreGiveFromISR( xISRMutex, NULL );
+
+			/* Second give attempt should fail. */
+			configASSERT( xSemaphoreGiveFromISR( xISRMutex, &xHigherPriorityTaskWoken ) == pdFAIL );
+		}
+
+		if( xOkToGiveCountingSemaphore != pdFALSE )
+		{
+			xSemaphoreGiveFromISR( xISRCountingSemaphore, &xHigherPriorityTaskWoken );
+		}
+		xLastGiveTime = xTimeNow;
+	}
+
+	/* Remove compiler warnings about the value being set but not used. */
+	( void ) xHigherPriorityTaskWoken;
+}
+/*-----------------------------------------------------------*/
+
+/* This is called to check that all the created tasks are still running. */
+BaseType_t xAreInterruptSemaphoreTasksStillRunning( void )
+{
+static uint32_t ulLastMasterLoopCounter = 0, ulLastCountingSemaphoreLoops = 0;
+
+	/* If the demo tasks are running then it is expected that the loop counters
+	will have changed since this function was last called. */
+	if( ulLastMasterLoopCounter == ulMasterLoops )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	ulLastMasterLoopCounter = ulMasterLoops;
+
+	if( ulLastCountingSemaphoreLoops == ulCountingSemaphoreLoops )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	ulLastCountingSemaphoreLoops = ulCountingSemaphoreLoops++;
+
+	/* Errors detected in the task itself will have latched xErrorDetected
+	to true. */
+
+	return ( BaseType_t ) !xErrorDetected;
+}
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/MessageBufferAMP.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/MessageBufferAMP.c
new file mode 100644
index 0000000..2417844
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/MessageBufferAMP.c
@@ -0,0 +1,330 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * An example that mimics a message buffer being used to pass data from one core
+ * to another.  The core that sends the data is referred to as core A.  The core
+ * that receives the data is referred to as core B.  The task implemented by
+ * prvCoreATask() runs on core A.  Two instances of the task implemented by
+ * prvCoreBTasks() run on core B.  prvCoreATask() sends messages via message
+ * buffers to both instances of prvCoreBTasks(), one message buffer per channel.
+ * A third message buffer is used to pass the handle of the message buffer
+ * written to by core A to an interrupt service routine that is triggered by
+ * core A but executes on core B.
+ *
+ * The example relies on the FreeRTOS provided default implementation of
+ * sbSEND_COMPLETED() being overridden by an implementation in FreeRTOSConfig.h
+ * that writes the handle of the message buffer that contains data into the
+ * control message buffer, then generates an interrupt in core B.  The necessary
+ * implementation is provided in this file and can be enabled by adding the
+ * following to FreeRTOSConfig.h:
+ *
+ * #define sbSEND_COMPLETED( pxStreamBuffer ) vGenerateCoreBInterrupt( pxStreamBuffer )
+ *
+ * Core to core communication via message buffer requires the message buffers
+ * to be at an address known to both cores within shared memory.
+ *
+ * Note that, while this example uses three message buffers, the same
+ * functionality can be implemented using a single message buffer by using the
+ * same design pattern described on the link below for queues, but using message
+ * buffers instead.  It is actually simpler with a message buffer as variable
+ * length data can be written into the message buffer directly:
+ * http://www.freertos.org/Pend-on-multiple-rtos-objects.html#alternative_design_pattern
+ */
+
+/* Standard includes. */
+#include "stdio.h"
+#include "string.h"
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "message_buffer.h"
+
+/* Demo app includes. */
+#include "MessageBufferAMP.h"
+
+/* Enough for 3 4 byte pointers, including the additional 4 bytes per message
+overhead of message buffers. */
+#define mbaCONTROL_MESSAGE_BUFFER_SIZE ( 24 )
+
+/* Enough four 4 8 byte strings, plus the additional 4 bytes per message
+overhead of message buffers. */
+#define mbaTASK_MESSAGE_BUFFER_SIZE ( 60 )
+
+/* The number of instances of prvCoreBTasks that are created. */
+#define mbaNUMBER_OF_CORE_B_TASKS	2
+
+/* A block time of 0 simply means, don't block. */
+#define mbaDONT_BLOCK				0
+
+/* Macro that mimics an interrupt service routine executing by simply calling
+the routine inline. */
+#define mbaGENERATE_CORE_B_INTERRUPT() prvCoreBInterruptHandler()
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Implementation of the task that, on a real dual core device, would run on
+ * core A and send message to tasks running on core B.
+ */
+static void prvCoreATask( void *pvParameters );
+
+/*
+ * Implementation of the task that, on a real dual core device, would run on
+ * core B and receive message from core A.  The demo creates two instances of
+ * this task.
+ */
+static void prvCoreBTasks( void *pvParameters );
+
+/*
+ * The function that, on a real dual core device, would handle inter-core
+ * interrupts, but in this case is just called inline.
+ */
+static void prvCoreBInterruptHandler( void );
+
+/*-----------------------------------------------------------*/
+
+/* The message buffers used to pass data from core A to core B. */
+static MessageBufferHandle_t xCoreBMessageBuffers[ mbaNUMBER_OF_CORE_B_TASKS ];
+
+/* The control message buffer.  This is used to pass the handle of the message
+message buffer that holds application data into the core to core interrupt
+service routine. */
+static MessageBufferHandle_t xControlMessageBuffer;
+
+/* Counters used to indicate to the check that the tasks are still executing. */
+static uint32_t ulCycleCounters[ mbaNUMBER_OF_CORE_B_TASKS ];
+
+/* Set to pdFALSE if any errors are detected.  Used to inform the check task
+that something might be wrong. */
+BaseType_t xDemoStatus = pdPASS;
+
+/*-----------------------------------------------------------*/
+
+void vStartMessageBufferAMPTasks( configSTACK_DEPTH_TYPE xStackSize )
+{
+BaseType_t x;
+
+	xControlMessageBuffer = xMessageBufferCreate( mbaCONTROL_MESSAGE_BUFFER_SIZE );
+
+	xTaskCreate( prvCoreATask,		/* The function that implements the task. */
+				 "AMPCoreA",		/* Human readable name for the task. */
+				 xStackSize,		/* Stack size (in words!). */
+				 NULL,				/* Task parameter is not used. */
+				 tskIDLE_PRIORITY,	/* The priority at which the task is created. */
+				 NULL );			/* No use for the task handle. */
+
+	for( x = 0; x < mbaNUMBER_OF_CORE_B_TASKS; x++ )
+	{
+		xCoreBMessageBuffers[ x ] = xMessageBufferCreate( mbaTASK_MESSAGE_BUFFER_SIZE );
+		configASSERT( xCoreBMessageBuffers[ x ] );
+
+		/* Pass the loop counter into the created task using the task's
+		parameter.  The task then uses the value as an index into the
+		ulCycleCounters and xCoreBMessageBuffers arrays. */
+		xTaskCreate( prvCoreBTasks,
+					 "AMPCoreB1",
+					 xStackSize,
+					 ( void * ) x,
+					 tskIDLE_PRIORITY + 1,
+					 NULL );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvCoreATask( void *pvParameters )
+{
+BaseType_t x;
+uint32_t ulNextValue = 0;
+const TickType_t xDelay = pdMS_TO_TICKS( 250 );
+char cString[ 15 ]; /* At least large enough to hold "4294967295\0" (0xffffffff). */
+
+	/* Remove warning about unused parameters. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		/* Create the next string to send.  The value is incremented on each
+		loop iteration, and the length of the string changes as the number of
+		digits in the value increases. */
+		sprintf( cString, "%lu", ( unsigned long ) ulNextValue );
+
+		/* Send the value from this (pseudo) Core A to the tasks on the (pseudo)
+		Core B via the message buffers.  This will result in sbSEND_COMPLETED()
+		being executed, which in turn will write the handle of the message
+		buffer written to into xControlMessageBuffer then generate an interrupt
+		in core B. */
+		for( x = 0; x < mbaNUMBER_OF_CORE_B_TASKS; x++ )
+		{
+			xMessageBufferSend( /* The message buffer to write to. */
+								xCoreBMessageBuffers[ x ],
+								/* The source of the data to send. */
+								( void * ) cString,
+								/* The length of the data to send. */
+								strlen( cString ),
+								/* The block time, should the buffer be full. */
+								mbaDONT_BLOCK );
+		}
+
+		/* Delay before repeating with a different and potentially different
+		length string. */
+		vTaskDelay( xDelay );
+		ulNextValue++;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvCoreBTasks( void *pvParameters )
+{
+BaseType_t x;
+size_t xReceivedBytes;
+uint32_t ulNextValue = 0;
+char cExpectedString[ 15 ]; /* At least large enough to hold "4294967295\0" (0xffffffff). */
+char cReceivedString[ 15 ];
+
+	/* The index into the xCoreBMessageBuffers and ulLoopCounter arrays is
+	passed into this task using the task's parameter. */
+	x = ( BaseType_t ) pvParameters;
+	configASSERT( x < mbaNUMBER_OF_CORE_B_TASKS );
+
+	for( ;; )
+	{
+		/* Create the string that is expected to be received this time round. */
+		sprintf( cExpectedString, "%lu", ( unsigned long ) ulNextValue );
+
+		/* Wait to receive the next message from core A. */
+		memset( cReceivedString, 0x00, sizeof( cReceivedString ) );
+		xReceivedBytes = xMessageBufferReceive( /* The message buffer to receive from. */
+												xCoreBMessageBuffers[ x ],
+												/* Location to store received data. */
+												cReceivedString,
+												/* Maximum number of bytes to receive. */
+												sizeof( cReceivedString ),
+												/* Ticks to wait if buffer is empty. */
+												portMAX_DELAY );
+
+		/* Check the number of bytes received was as expected. */
+		configASSERT( xReceivedBytes == strlen( cExpectedString ) );
+		( void ) xReceivedBytes; /* Incase configASSERT() is not defined. */
+
+		/* If the received string matches that expected then increment the loop
+		counter so the check task knows this task is still running. */
+		if( strcmp( cReceivedString, cExpectedString ) == 0 )
+		{
+			( ulCycleCounters[ x ] )++;
+		}
+		else
+		{
+			xDemoStatus = pdFAIL;
+		}
+
+		/* Expect the next string in sequence the next time around. */
+		ulNextValue++;
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* Called by the reimplementation of sbSEND_COMPLETED(), which can be defined
+as follows in FreeRTOSConfig.h:
+#define sbSEND_COMPLETED( pxStreamBuffer ) vGenerateCoreBInterrupt( pxStreamBuffer )
+*/
+void vGenerateCoreBInterrupt( void * xUpdatedMessageBuffer )
+{
+MessageBufferHandle_t xUpdatedBuffer = ( MessageBufferHandle_t ) xUpdatedMessageBuffer;
+
+	/* If sbSEND_COMPLETED() has been implemented as above, then this function
+	is called from within xMessageBufferSend().  As this function also calls
+	xMessageBufferSend() itself it is necessary to guard against a recursive
+	call.  If the message buffer just updated is the message buffer written to
+	by this function, then this is a recursive call, and the function can just
+	exit without taking further action. */
+	if( xUpdatedBuffer != xControlMessageBuffer )
+	{
+		/* Use xControlMessageBuffer to pass the handle of the message buffer
+		written to by core A to the interrupt handler about to be generated in
+		core B. */
+		xMessageBufferSend( xControlMessageBuffer, &xUpdatedBuffer, sizeof( xUpdatedBuffer ), mbaDONT_BLOCK );
+
+		/* This is where the interrupt would be generated.  In this case it is
+		not a genuine interrupt handler that executes, just a standard function
+		call. */
+		mbaGENERATE_CORE_B_INTERRUPT();
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* Handler for the interrupts that are triggered on core A but execute on core
+B. */
+static void prvCoreBInterruptHandler( void )
+{
+MessageBufferHandle_t xUpdatedMessageBuffer;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+
+	/* xControlMessageBuffer contains the handle of the message buffer that
+	contains data. */
+	if( xMessageBufferReceive( xControlMessageBuffer,
+							   &xUpdatedMessageBuffer,
+							   sizeof( xUpdatedMessageBuffer ),
+							   mbaDONT_BLOCK ) == sizeof( xUpdatedMessageBuffer ) )
+	{
+		/* Call the API function that sends a notification to any task that is
+		blocked on the xUpdatedMessageBuffer message buffer waiting for data to
+		arrive. */
+		xMessageBufferSendCompletedFromISR( xUpdatedMessageBuffer, &xHigherPriorityTaskWoken );
+	}
+
+	/* Normal FreeRTOS yield from interrupt semantics, where
+	xHigherPriorityTaskWoken is initialzed to pdFALSE and will then get set to
+	pdTRUE if the interrupt safe API unblocks a task that has a priority above
+	that of the currently executing task. */
+	portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xAreMessageBufferAMPTasksStillRunning( void )
+{
+static uint32_t ulLastCycleCounters[ mbaNUMBER_OF_CORE_B_TASKS ] = { 0 };
+BaseType_t x;
+
+	/* Called by the check task to determine the health status of the tasks
+	implemented in this demo. */
+	for( x = 0; x < mbaNUMBER_OF_CORE_B_TASKS; x++ )
+	{
+		if( ulLastCycleCounters[ x ] == ulCycleCounters[ x ] )
+		{
+			xDemoStatus = pdFAIL;
+		}
+		else
+		{
+			ulLastCycleCounters[ x ] = ulCycleCounters[ x ];
+		}
+	}
+
+	return xDemoStatus;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/MessageBufferDemo.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/MessageBufferDemo.c
new file mode 100644
index 0000000..d50f573
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/MessageBufferDemo.c
@@ -0,0 +1,851 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include "stdio.h"
+#include "string.h"
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "message_buffer.h"
+
+/* Demo app includes. */
+#include "MessageBufferDemo.h"
+
+/* The number of bytes of storage in the message buffers used in this test. */
+#define mbMESSAGE_BUFFER_LENGTH_BYTES	( ( size_t ) 50 )
+
+/* The number of additional bytes used to store the length of each message. */
+#define mbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
+
+/* Start and end ASCII characters used in messages sent to the buffers. */
+#define mbASCII_SPACE					32
+#define mbASCII_TILDA					126
+
+/* Defines the number of tasks to create in this test and demo. */
+#define mbNUMBER_OF_ECHO_CLIENTS	( 2 )
+#define mbNUMBER_OF_SENDER_TASKS	( 2 )
+
+/* Priority of the test tasks.  The send and receive go from low to high
+priority tasks, and from high to low priority tasks. */
+#define mbLOWER_PRIORITY			( tskIDLE_PRIORITY )
+#define mbHIGHER_PRIORITY			( tskIDLE_PRIORITY + 1 )
+
+/* Block times used when sending and receiving from the message buffers. */
+#define mbRX_TX_BLOCK_TIME			pdMS_TO_TICKS( 125UL )
+
+/* A block time of 0 means "don't block". */
+#define mbDONT_BLOCK				( 0 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Performs various tests that do not require multiple tasks to interact.
+ */
+static void prvSingleTaskTests( MessageBufferHandle_t xMessageBuffer );
+
+/*
+ * Tests sending and receiving various lengths of messages via a message buffer.
+ * The echo client sends the messages to the echo server, which then sends the
+ * message back to the echo client which, checks it receives exactly what it
+ * sent.
+ */
+static void prvEchoClient( void *pvParameters );
+static void prvEchoServer( void *pvParameters );
+
+/*
+ * Tasks that send and receive to a message buffer at a low priority and without
+ * blocking, so the send and receive functions interleave in time as the tasks
+ * are switched in and out.
+ */
+static void prvNonBlockingReceiverTask( void *pvParameters );
+static void prvNonBlockingSenderTask( void *pvParameters );
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1  )
+	/* This file tests both statically and dynamically allocated message buffers.
+	Allocate the structures and buffers to be used by the statically allocated
+	objects, which get used in the echo tests. */
+	static void prvReceiverTask( void *pvParameters );
+	static void prvSenderTask( void *pvParameters );
+
+	static StaticMessageBuffer_t xStaticMessageBuffers[ mbNUMBER_OF_ECHO_CLIENTS ];
+	static uint8_t ucBufferStorage[ mbNUMBER_OF_SENDER_TASKS ][ mbMESSAGE_BUFFER_LENGTH_BYTES + 1 ];
+	static uint32_t ulSenderLoopCounters[ mbNUMBER_OF_SENDER_TASKS ] = { 0 };
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/*-----------------------------------------------------------*/
+
+/* The buffers used by the echo client and server tasks. */
+typedef struct ECHO_MESSAGE_BUFFERS
+{
+	/* Handles to the data structures that describe the message buffers. */
+	MessageBufferHandle_t xEchoClientBuffer;
+	MessageBufferHandle_t xEchoServerBuffer;
+} EchoMessageBuffers_t;
+static uint32_t ulEchoLoopCounters[ mbNUMBER_OF_ECHO_CLIENTS ] = { 0 };
+
+/* The non-blocking tasks monitor their operation, and if no errors have been
+found, increment ulNonBlockingRxCounter.  xAreMessageBufferTasksStillRunning()
+then checks ulNonBlockingRxCounter and only returns pdPASS if
+ulNonBlockingRxCounter is still incrementing. */
+static uint32_t ulNonBlockingRxCounter = 0;
+
+/* A message that is longer than the buffer, parts of which are written to the
+message buffer to test writing different lengths at different offsets. */
+static const char *pc55ByteString = "One two three four five six seven eight nine ten eleve";
+
+/* Remember the required stack size so tasks can be created at run time (after
+initialisation time. */
+static configSTACK_DEPTH_TYPE xBlockingStackSize = 0;
+
+/*-----------------------------------------------------------*/
+
+void vStartMessageBufferTasks( configSTACK_DEPTH_TYPE xStackSize  )
+{
+MessageBufferHandle_t xMessageBuffer;
+
+	xBlockingStackSize = ( xStackSize + ( xStackSize >> 1U ) );
+
+	/* The echo servers sets up the message buffers before creating the echo
+	client tasks.  One set of tasks has the server as the higher priority, and
+	the other has the client as the higher priority. */
+	xTaskCreate( prvEchoServer, "1EchoServer", xBlockingStackSize, NULL, mbHIGHER_PRIORITY, NULL );
+	xTaskCreate( prvEchoServer, "2EchoServer", xBlockingStackSize, NULL, mbLOWER_PRIORITY, NULL );
+
+	/* The non blocking tasks run continuously and will interleave with each
+	other, so must be created at the lowest priority.  The message buffer they
+	use is created and passed in using the task's parameter. */
+	xMessageBuffer = xMessageBufferCreate( mbMESSAGE_BUFFER_LENGTH_BYTES );
+	xTaskCreate( prvNonBlockingReceiverTask, "NonBlkRx", xStackSize, ( void * ) xMessageBuffer, tskIDLE_PRIORITY, NULL );
+	xTaskCreate( prvNonBlockingSenderTask, "NonBlkTx", xStackSize, ( void * ) xMessageBuffer, tskIDLE_PRIORITY, NULL );
+
+	#if( configSUPPORT_STATIC_ALLOCATION == 1  )
+	{
+		/* The sender tasks set up the message buffers before creating the
+		receiver tasks.  Priorities must be 0 and 1 as the priority is used to
+		index into the xStaticMessageBuffers and ucBufferStorage arrays. */
+		xTaskCreate( prvSenderTask, "1Sender", xBlockingStackSize, NULL, mbHIGHER_PRIORITY, NULL );
+		xTaskCreate( prvSenderTask, "2Sender", xBlockingStackSize, NULL, mbLOWER_PRIORITY, NULL );
+	}
+	#endif /* configSUPPORT_STATIC_ALLOCATION */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSingleTaskTests( MessageBufferHandle_t xMessageBuffer )
+{
+size_t xReturned, xItem, xExpectedSpace, xNextLength;
+const size_t xMax6ByteMessages = mbMESSAGE_BUFFER_LENGTH_BYTES / ( 6 + mbBYTES_TO_STORE_MESSAGE_LENGTH );
+const size_t x6ByteLength = 6, x17ByteLength = 17;
+uint8_t *pucFullBuffer, *pucData, *pucReadData;
+TickType_t xTimeBeforeCall, xTimeAfterCall;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 25 ), xAllowableMargin = pdMS_TO_TICKS( 3 );
+UBaseType_t uxOriginalPriority;
+
+	/* Remove warning in case configASSERT() is not defined. */
+	( void ) xAllowableMargin;
+
+	/* To minimise stack and heap usage a full size buffer is allocated from
+	the heap, then buffers which hold smaller amounts of data are overlayed
+	with the larger buffer - just make sure not to use both at once!. */
+	pucFullBuffer = pvPortMalloc( mbMESSAGE_BUFFER_LENGTH_BYTES );
+	configASSERT( pucFullBuffer );
+
+	pucData = pucFullBuffer;
+	pucReadData = pucData + x17ByteLength;
+
+	/* Nothing has been added or removed yet, so expect the free space to be
+	exactly as created and the length of the next message to be 0. */
+	xExpectedSpace = xMessageBufferSpaceAvailable( xMessageBuffer );
+	configASSERT( xExpectedSpace == mbMESSAGE_BUFFER_LENGTH_BYTES );
+	configASSERT( xMessageBufferIsEmpty( xMessageBuffer ) == pdTRUE );
+	xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
+	configASSERT( xNextLength == 0 );
+	/* In case configASSERT() is not define. */
+	( void ) xExpectedSpace;
+	( void ) xNextLength;
+
+	/* The buffer is 50 bytes long.  When an item is added to the buffer an
+	additional 4 bytes are added to hold the item's size.  That means adding
+	6 bytes to the buffer will actually add 10 bytes to the buffer.  Therefore,
+	with a 50 byte buffer, a maximum of 5 6 bytes items can be added before the
+	buffer is completely full.  NOTE:  The numbers in this paragraph assume
+	sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) == 4. */
+	for( xItem = 0; xItem < xMax6ByteMessages; xItem++ )
+	{
+		configASSERT( xMessageBufferIsFull( xMessageBuffer ) == pdFALSE );
+
+		/* Generate recognisable data to write to the buffer.  This is just
+		ascii characters that shows which loop iteration the data was written
+		in. The 'FromISR' version is used to give it some exercise as a block
+		time is not used.  That requires the call to be in a critical section
+		so this code can also run on FreeRTOS ports that do not support
+		interrupt nesting (and so don't have interrupt safe critical
+		sections).*/
+		memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x6ByteLength );
+		taskENTER_CRITICAL();
+		{
+			xReturned = xMessageBufferSendFromISR( xMessageBuffer, ( void * ) pucData, x6ByteLength, NULL );
+		}
+		taskEXIT_CRITICAL();
+		configASSERT( xReturned == x6ByteLength );
+		( void ) xReturned; /* In case configASSERT() is not defined. */
+
+		/* The space in the buffer will have reduced by the amount of user data
+		written into the buffer and the amount of space used to store the length
+		of the data written into the buffer. */
+		xExpectedSpace -= ( x6ByteLength + mbBYTES_TO_STORE_MESSAGE_LENGTH );
+		xReturned = xMessageBufferSpaceAvailable( xMessageBuffer );
+		configASSERT( xReturned == xExpectedSpace );
+		( void ) xReturned; /* In case configASSERT() is not defined. */
+
+		/* Only 6 byte messages are written. */
+		xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
+		configASSERT( xNextLength == x6ByteLength );
+		( void ) xNextLength; /* In case configASSERT() is not defined. */
+	}
+
+	/* Now the buffer should be full, and attempting to add anything will should
+	fail. */
+	configASSERT( xMessageBufferIsFull( xMessageBuffer ) == pdTRUE );
+	xReturned = xMessageBufferSend( xMessageBuffer, ( void * ) pucData, sizeof( pucData[ 0 ] ), mbDONT_BLOCK );
+	configASSERT( xReturned == 0 );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+
+	/* Adding with a timeout should also fail after the appropriate time.  The
+	priority is temporarily boosted in this part of the test to keep the
+	allowable margin to a minimum. */
+	uxOriginalPriority = uxTaskPriorityGet( NULL );
+	vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
+	xTimeBeforeCall = xTaskGetTickCount();
+	xReturned = xMessageBufferSend( xMessageBuffer, ( void * ) pucData, sizeof( pucData[ 0 ] ), xBlockTime );
+	xTimeAfterCall = xTaskGetTickCount();
+	vTaskPrioritySet( NULL, uxOriginalPriority );
+	configASSERT( ( xTimeAfterCall - xTimeBeforeCall ) >= xBlockTime );
+	configASSERT( ( xTimeAfterCall - xTimeBeforeCall ) < ( xBlockTime + xAllowableMargin ) );
+	configASSERT( xReturned == 0 );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+	( void ) xTimeBeforeCall;
+	( void ) xTimeAfterCall;
+
+
+	/* The buffer is now full of data in the form "000000", "111111", etc.  Make
+	sure the data is read out as expected. */
+	for( xItem = 0; xItem < xMax6ByteMessages; xItem++ )
+	{
+		/* Generate the data that is expected to be read out for this loop
+		iteration. */
+		memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x6ByteLength );
+
+		/* Try reading the message into a buffer that is too small.  The message
+		should remain in the buffer. */
+		xReturned = xMessageBufferReceive( xMessageBuffer, ( void * ) pucReadData, x6ByteLength - 1, mbDONT_BLOCK );
+		configASSERT( xReturned == 0 );
+		( void ) xReturned; /* In case configASSERT() is not defined. */
+
+		/* Should still be at least one 6 byte message still available. */
+		xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
+		configASSERT( xNextLength == x6ByteLength );
+		( void ) xNextLength; /* In case configASSERT() is not defined. */
+
+		/* Read the next 6 bytes out.  The 'FromISR' version is used to give it
+		some exercise as a block time is not used.  THa requires the code to be
+		in a critical section so this test can be run with FreeRTOS ports that
+		do not support interrupt nesting (and therefore don't have interrupt
+		safe critical sections). */
+		taskENTER_CRITICAL();
+		{
+			xReturned = xMessageBufferReceiveFromISR( xMessageBuffer, ( void * ) pucReadData, x6ByteLength, NULL );
+		}
+		taskEXIT_CRITICAL();
+		configASSERT( xReturned == x6ByteLength );
+		( void ) xReturned; /* In case configASSERT() is not defined. */
+
+		/* Does the data read out match that expected? */
+		configASSERT( memcmp( ( void * ) pucData, ( void * ) pucReadData, x6ByteLength ) == 0 );
+
+		/* The space in the buffer will have increased by the amount of user
+		data read from into the buffer and the amount of space used to store the
+		length of the data read into the buffer. */
+		xExpectedSpace += ( x6ByteLength + mbBYTES_TO_STORE_MESSAGE_LENGTH );
+		xReturned = xMessageBufferSpaceAvailable( xMessageBuffer );
+		configASSERT( xReturned == xExpectedSpace );
+		( void ) xReturned; /* In case configASSERT() is not defined. */
+	}
+
+	/* The buffer should be empty again. */
+	configASSERT( xMessageBufferIsEmpty( xMessageBuffer ) == pdTRUE );
+	xExpectedSpace = xMessageBufferSpaceAvailable( xMessageBuffer );
+	configASSERT( xExpectedSpace == mbMESSAGE_BUFFER_LENGTH_BYTES );
+	( void ) xExpectedSpace; /* In case configASSERT() is not defined. */
+	xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
+	configASSERT( xNextLength == 0 );
+	( void ) xNextLength; /* In case configASSERT() is not defined. */
+
+
+	/* Reading with a timeout should also fail after the appropriate time.  The
+	priority is temporarily boosted in this part of the test to keep the
+	allowable margin to a minimum. */
+	vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
+	xTimeBeforeCall = xTaskGetTickCount();
+	xReturned = xMessageBufferReceive( xMessageBuffer, ( void * ) pucReadData, x6ByteLength, xBlockTime );
+	xTimeAfterCall = xTaskGetTickCount();
+	vTaskPrioritySet( NULL, uxOriginalPriority );
+	configASSERT( ( xTimeAfterCall - xTimeBeforeCall ) >= xBlockTime );
+	configASSERT( ( xTimeAfterCall - xTimeBeforeCall ) < ( xBlockTime + xAllowableMargin ) );
+	configASSERT( xReturned == 0 );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+	( void ) xTimeBeforeCall;
+	( void ) xTimeAfterCall;
+
+
+	/* In the next loop 17 bytes are written to then read out on each iteration.
+	The expected length variable is always used after 17 bytes have been written
+	into the buffer - the length of the message is also written, making a total
+	of 21 bytes consumed for each 17 byte message. */
+	xExpectedSpace = mbMESSAGE_BUFFER_LENGTH_BYTES - ( x17ByteLength + mbBYTES_TO_STORE_MESSAGE_LENGTH );
+
+	/* Reading and writing 17 bytes at a time will result in 21 bytes being
+	written into the buffer, and as 50 is not divisible by 21, writing multiple
+	times will cause the data to wrap in the buffer.*/
+	for( xItem = 0; xItem < 100; xItem++ )
+	{
+		/* Generate recognisable data to write to the queue.  This is just
+		ascii characters that shows which loop iteration the data was written
+		in. */
+		memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x17ByteLength );
+		xReturned = xMessageBufferSend( xMessageBuffer, ( void * ) pucData, x17ByteLength, mbDONT_BLOCK );
+		configASSERT( xReturned == x17ByteLength );
+		( void ) xReturned; /* In case configASSERT() is not defined. */
+
+		/* Only 17 byte messages are written. */
+		xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
+		configASSERT( xNextLength == x17ByteLength );
+		( void ) xNextLength; /* In case configASSERT() is not defined. */
+
+		/* The space in the buffer will have reduced by the amount of user data
+		written into the buffer and the amount of space used to store the length
+		of the data written into the buffer. */
+		xReturned = xMessageBufferSpaceAvailable( xMessageBuffer );
+		configASSERT( xReturned == xExpectedSpace );
+		( void ) xReturned; /* In case configASSERT() is not defined. */
+
+		/* Read the 17 bytes out again. */
+		xReturned = xMessageBufferReceive( xMessageBuffer, ( void * ) pucReadData, x17ByteLength, mbDONT_BLOCK );
+		configASSERT( xReturned == x17ByteLength );
+		( void ) xReturned; /* In case configASSERT() is not defined. */
+
+		/* Does the data read out match that expected? */
+		configASSERT( memcmp( ( void * ) pucData, ( void * ) pucReadData, x17ByteLength ) == 0 );
+
+		/* Don't expect any messages to be available as the data was read out
+		again. */
+		xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
+		configASSERT( xNextLength == 0 );
+		( void ) xNextLength; /* In case configASSERT() is not defined. */
+	}
+
+	/* The buffer should be empty again. */
+	configASSERT( xMessageBufferIsEmpty( xMessageBuffer ) == pdTRUE );
+	xExpectedSpace = xMessageBufferSpaceAvailable( xMessageBuffer );
+	configASSERT( xExpectedSpace == mbMESSAGE_BUFFER_LENGTH_BYTES );
+
+	/* Cannot write within sizeof( size_t ) (assumed to be 4 bytes in this test)
+	bytes of the full 50 bytes, as that would not leave space for the four bytes
+	taken by the data length. */
+	xReturned = xMessageBufferSend( xMessageBuffer, ( const void * ) pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES, mbDONT_BLOCK );
+	configASSERT( xReturned == 0 );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+	#ifndef configMESSAGE_BUFFER_LENGTH_TYPE
+	{
+		/* The following will fail if configMESSAGE_BUFFER_LENGTH_TYPE is set
+		to a non 32-bit type. */
+		xReturned = xMessageBufferSend( xMessageBuffer, ( const void * ) pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES - 1, mbDONT_BLOCK );
+		configASSERT( xReturned == 0 );
+		( void ) xReturned; /* In case configASSERT() is not defined. */
+		xReturned = xMessageBufferSend( xMessageBuffer, ( const void * ) pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES - 2, mbDONT_BLOCK );
+		configASSERT( xReturned == 0 );
+		( void ) xReturned; /* In case configASSERT() is not defined. */
+		xReturned = xMessageBufferSend( xMessageBuffer, ( const void * ) pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES - 3, mbDONT_BLOCK );
+		configASSERT( xReturned == 0 );
+		( void ) xReturned; /* In case configASSERT() is not defined. */
+	}
+	#endif
+
+	/* Don't expect any messages to be available as the above were too large to
+	get written. */
+	xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
+	configASSERT( xNextLength == 0 );
+	( void ) xNextLength; /* In case configASSERT() is not defined. */
+
+	/* Can write mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) bytes though. */
+	xReturned = xMessageBufferSend( xMessageBuffer, ( const void * ) pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ), mbDONT_BLOCK );
+	configASSERT( xReturned == mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+	xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
+	configASSERT( xNextLength == ( mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) ) );
+	( void ) xNextLength; /* In case configASSERT() is not defined. */
+	xReturned = xMessageBufferReceive( xMessageBuffer, ( void * ) pucFullBuffer, mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ), mbDONT_BLOCK );
+	configASSERT( xReturned == ( mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) ) );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+	configASSERT( memcmp( ( const void * ) pucFullBuffer, pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) ) == 0 );
+
+	/* Clean up. */
+	vPortFree( pucFullBuffer );
+	xMessageBufferReset( xMessageBuffer );
+}
+/*-----------------------------------------------------------*/
+
+static void prvNonBlockingSenderTask( void *pvParameters )
+{
+MessageBufferHandle_t xMessageBuffer;
+int32_t iDataToSend = 0;
+size_t xStringLength;
+const int32_t iMaxValue = 1500;
+char cTxString[ 12 ]; /* Large enough to hold a 32 number in ASCII. */
+
+	/* In this case the message buffer has already been created and is passed
+	into the task using the task's parameter. */
+	xMessageBuffer = ( MessageBufferHandle_t ) pvParameters;
+
+	/* Create a string from an incrementing number.  The length of the
+	string will increase and decrease as the value of the number increases
+	then overflows. */
+	memset( cTxString, 0x00, sizeof( cTxString ) );
+	sprintf( cTxString, "%d", ( int ) iDataToSend );
+	xStringLength = strlen( cTxString );
+
+	for( ;; )
+	{
+		/* Doesn't block so calls can interleave with the non-blocking
+		receives performed by prvNonBlockingReceiverTask(). */
+		if( xMessageBufferSend( xMessageBuffer, ( void * ) cTxString, strlen( cTxString ), mbDONT_BLOCK ) == xStringLength )
+		{
+			iDataToSend++;
+
+			if( iDataToSend > iMaxValue )
+			{
+				/* The value sent is reset back to 0 to ensure the string being sent
+				does not remain at the same length for too long. */
+				iDataToSend = 0;
+			}
+
+			/* Create the next string. */
+			memset( cTxString, 0x00, sizeof( cTxString ) );
+			sprintf( cTxString, "%d", ( int ) iDataToSend );
+			xStringLength = strlen( cTxString );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvNonBlockingReceiverTask( void *pvParameters )
+{
+MessageBufferHandle_t xMessageBuffer;
+BaseType_t xNonBlockingReceiveError = pdFALSE;
+int32_t iDataToSend = 0;
+size_t xStringLength, xReceiveLength;
+const int32_t iMaxValue = 1500;
+char cExpectedString[ 12 ]; /* Large enough to hold a 32 number in ASCII. */
+char cRxString[ 12 ];
+
+	/* In this case the message buffer has already been created and is passed
+	into the task using the task's parameter. */
+	xMessageBuffer = ( MessageBufferHandle_t ) pvParameters;
+
+	/* Create a string from an incrementing number.  The length of the
+	string will increase and decrease as the value of the number increases
+	then overflows.  This should always match the string sent to the buffer by
+	the non blocking sender task. */
+	memset( cExpectedString, 0x00, sizeof( cExpectedString ) );
+	memset( cRxString, 0x00, sizeof( cRxString ) );
+	sprintf( cExpectedString, "%d", ( int ) iDataToSend );
+	xStringLength = strlen( cExpectedString );
+
+	for( ;; )
+	{
+		/* Doesn't block so calls can interleave with the non-blocking
+		receives performed by prvNonBlockingReceiverTask(). */
+		xReceiveLength = xMessageBufferReceive( xMessageBuffer, ( void * ) cRxString, sizeof( cRxString ), mbDONT_BLOCK );
+
+		/* Should only ever receive no data is available, or the expected
+		length of data is available. */
+		if( ( xReceiveLength != 0 ) && ( xReceiveLength != xStringLength ) )
+		{
+			xNonBlockingReceiveError = pdTRUE;
+		}
+
+		if( xReceiveLength == xStringLength )
+		{
+			/* Ensure the received data was that expected, then generate the
+			next expected string. */
+			if( strcmp( cRxString, cExpectedString ) != 0 )
+			{
+				xNonBlockingReceiveError = pdTRUE;
+			}
+
+			iDataToSend++;
+
+			if( iDataToSend > iMaxValue )
+			{
+				/* The value sent is reset back to 0 to ensure the string being sent
+				does not remain at the same length for too long. */
+				iDataToSend = 0;
+			}
+
+			memset( cExpectedString, 0x00, sizeof( cExpectedString ) );
+			memset( cRxString, 0x00, sizeof( cRxString ) );
+			sprintf( cExpectedString, "%d", ( int ) iDataToSend );
+			xStringLength = strlen( cExpectedString );
+
+			if( xNonBlockingReceiveError == pdFALSE )
+			{
+				/* No errors detected so increment the counter that lets the
+				check task know this test is still functioning correctly. */
+				ulNonBlockingRxCounter++;
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1  )
+
+	static void prvSenderTask( void *pvParameters )
+	{
+	MessageBufferHandle_t xMessageBuffer, xTempMessageBuffer;
+	int32_t iDataToSend = 0;
+	const int32_t iSendsBetweenIncrements = 100;
+	char cTxString[ 12 ]; /* Large enough to hold a 32 number in ASCII. */
+	const TickType_t xTicksToWait = mbRX_TX_BLOCK_TIME, xShortDelay = pdMS_TO_TICKS( 50 );
+	StaticMessageBuffer_t xStaticMessageBuffer;
+
+
+	/* The task's priority is used as an index into the loop counters used to
+	indicate this task is still running. */
+	UBaseType_t uxIndex = uxTaskPriorityGet( NULL );
+
+		/* Make sure a change in priority does not inadvertently result in an
+		invalid array index. */
+		configASSERT( uxIndex < mbNUMBER_OF_ECHO_CLIENTS );
+
+		/* Avoid compiler warnings about unused parameters. */
+		( void ) pvParameters;
+
+		xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ) / mbNUMBER_OF_SENDER_TASKS, /* The number of bytes in each buffer in the array. */
+													 &( ucBufferStorage[ uxIndex ][ 0 ] ), /* The address of the buffer to use within the array. */
+													 &( xStaticMessageBuffers[ uxIndex ] ) ); /* The static message buffer structure to use within the array. */
+
+		/* Now the message buffer has been created the receiver task can be created.
+		If this sender task has the higher priority then the receiver task is
+		created at the lower priority - if this sender task has the lower priority
+		then the receiver task is created at the higher priority. */
+		if( uxTaskPriorityGet( NULL ) == mbLOWER_PRIORITY )
+		{
+			/* Here prvSingleTaskTests() performs various tests on a message buffer
+			that was created statically. */
+			prvSingleTaskTests( xMessageBuffer );
+			xTaskCreate( prvReceiverTask, "MsgReceiver", xBlockingStackSize,  ( void * ) xMessageBuffer, mbHIGHER_PRIORITY, NULL );
+		}
+		else
+		{
+			xTaskCreate( prvReceiverTask, "MsgReceiver", xBlockingStackSize,  ( void * ) xMessageBuffer, mbLOWER_PRIORITY, NULL );
+		}
+
+		for( ;; )
+		{
+			/* Create a string from an incrementing number.  The length of the
+			string will increase and decrease as the value of the number increases
+			then overflows. */
+			memset( cTxString, 0x00, sizeof( cTxString ) );
+			sprintf( cTxString, "%d", ( int ) iDataToSend );
+			xMessageBufferSend( xMessageBuffer, ( void * ) cTxString, strlen( cTxString ), xTicksToWait );
+
+			iDataToSend++;
+
+			if( ( iDataToSend % iSendsBetweenIncrements ) == 0 )
+			{
+				/* Increment a loop counter so a check task can tell this task is
+				still running as expected. */
+				ulSenderLoopCounters[ uxIndex ]++;
+
+				if( uxTaskPriorityGet( NULL ) == mbHIGHER_PRIORITY )
+				{
+					/* Allow other tasks to run. */
+					vTaskDelay( xShortDelay );
+				}
+
+				/* This message buffer is just created and deleted to ensure no
+				issues when attempting to delete a message buffer that was
+				created using statically allocated memory.  To save stack space
+				the buffer is set to point to the cTxString array - this is
+				ok because nothing is actually written to the memory. */
+				xTempMessageBuffer = xMessageBufferCreateStatic( sizeof( cTxString ), ( uint8_t * ) cTxString, &xStaticMessageBuffer );
+				vMessageBufferDelete( xTempMessageBuffer );
+			}
+		}
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1  )
+
+	static void prvReceiverTask( void *pvParameters )
+	{
+	MessageBufferHandle_t * const pxMessageBuffer = ( MessageBufferHandle_t * ) pvParameters;
+	char cExpectedString[ 12 ]; /* Large enough to hold a 32-bit number in ASCII. */
+	char cReceivedString[ 12 ]; /* Large enough to hold a 32-bit number in ASCII. */
+	int32_t iExpectedData = 0;
+	const TickType_t xTicksToWait = pdMS_TO_TICKS( 5UL );
+	size_t xReceivedBytes;
+
+		for( ;; )
+		{
+			/* Generate the next expected string in the cExpectedString buffer. */
+			memset( cExpectedString, 0x00, sizeof( cExpectedString ) );
+			sprintf( cExpectedString, "%d", ( int ) iExpectedData );
+
+			/* Receive the next string from the message buffer. */
+			memset( cReceivedString, 0x00, sizeof( cReceivedString ) );
+
+			do
+			{
+				xReceivedBytes = xMessageBufferReceive( pxMessageBuffer, ( void * ) cReceivedString, sizeof( cExpectedString ), xTicksToWait );
+
+			} while( xReceivedBytes == 0 );
+
+			/* Ensure the received string matches the expected string. */
+			configASSERT( strcmp( cExpectedString, cReceivedString ) == 0 );
+
+			iExpectedData++;
+		}
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvEchoClient( void *pvParameters )
+{
+size_t xSendLength = 0, ux;
+char *pcStringToSend, *pcStringReceived, cNextChar = mbASCII_SPACE;
+const TickType_t xTicksToWait = pdMS_TO_TICKS( 50 );
+
+/* The task's priority is used as an index into the loop counters used to
+indicate this task is still running. */
+UBaseType_t uxIndex = uxTaskPriorityGet( NULL );
+
+/* Pointers to the client and server message buffers are passed into this task
+using the task's parameter. */
+EchoMessageBuffers_t *pxMessageBuffers = ( EchoMessageBuffers_t * ) pvParameters;
+
+	/* Prevent compiler warnings. */
+	( void ) pvParameters;
+
+	/* Create the buffer into which strings to send to the server will be
+	created, and the buffer into which strings echoed back from the server will
+	be copied. */
+	pcStringToSend = ( char * ) pvPortMalloc( mbMESSAGE_BUFFER_LENGTH_BYTES );
+	pcStringReceived = ( char * ) pvPortMalloc( mbMESSAGE_BUFFER_LENGTH_BYTES );
+
+	configASSERT( pcStringToSend );
+	configASSERT( pcStringReceived );
+
+	for( ;; )
+	{
+		/* Generate the length of the next string to send. */
+		xSendLength++;
+
+		/* The message buffer is being used to hold variable length data, so
+		each data item requires sizeof( size_t ) bytes to hold the data's
+		length, hence the sizeof() in the if() condition below. */
+		if( xSendLength > ( mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) ) )
+		{
+			/* Back to a string length of 1. */
+			xSendLength = sizeof( char );
+
+			/* Maintain a count of the number of times this code executes so a
+			check task can determine if this task is still functioning as
+			expected or not.  As there are two client tasks, and the priorities
+			used are 0 and 1, the task's priority is used as an index into the
+			loop count array. */
+			ulEchoLoopCounters[ uxIndex ]++;
+		}
+
+		memset( pcStringToSend, 0x00, mbMESSAGE_BUFFER_LENGTH_BYTES );
+
+		for( ux = 0; ux < xSendLength; ux++ )
+		{
+			pcStringToSend[ ux ] = cNextChar;
+
+			cNextChar++;
+
+			if( cNextChar > mbASCII_TILDA )
+			{
+				cNextChar = mbASCII_SPACE;
+			}
+		}
+
+		/* Send the generated string to the buffer. */
+		do
+		{
+			ux = xMessageBufferSend( pxMessageBuffers->xEchoClientBuffer, ( void * ) pcStringToSend, xSendLength, xTicksToWait );
+
+			if( ux == 0 )
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+		} while( ux == 0 );
+
+		/* Wait for the string to be echoed back. */
+		memset( pcStringReceived, 0x00, mbMESSAGE_BUFFER_LENGTH_BYTES );
+		xMessageBufferReceive( pxMessageBuffers->xEchoServerBuffer, ( void * ) pcStringReceived, xSendLength, portMAX_DELAY );
+
+		configASSERT( strcmp( pcStringToSend, pcStringReceived ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvEchoServer( void *pvParameters )
+{
+MessageBufferHandle_t xTempMessageBuffer;
+size_t xReceivedLength;
+char *pcReceivedString;
+EchoMessageBuffers_t xMessageBuffers;
+TickType_t xTimeOnEntering;
+const TickType_t xTicksToBlock = pdMS_TO_TICKS( 250UL );
+
+	/* Prevent compiler warnings about unused parameters. */
+	( void ) pvParameters;
+
+	/* Create the message buffer used to send data from the client to the server,
+	and the message buffer used to echo the data from the server back to the
+	client. */
+	xMessageBuffers.xEchoClientBuffer = xMessageBufferCreate( mbMESSAGE_BUFFER_LENGTH_BYTES );
+	xMessageBuffers.xEchoServerBuffer = xMessageBufferCreate( mbMESSAGE_BUFFER_LENGTH_BYTES );
+	configASSERT( xMessageBuffers.xEchoClientBuffer );
+	configASSERT( xMessageBuffers.xEchoServerBuffer );
+
+	/* Create the buffer into which received strings will be copied. */
+	pcReceivedString = ( char * ) pvPortMalloc( mbMESSAGE_BUFFER_LENGTH_BYTES );
+	configASSERT( pcReceivedString );
+
+	/* Don't expect to receive anything yet! */
+	xTimeOnEntering = xTaskGetTickCount();
+	xReceivedLength = xMessageBufferReceive( xMessageBuffers.xEchoClientBuffer, ( void * ) pcReceivedString, mbMESSAGE_BUFFER_LENGTH_BYTES, xTicksToBlock );
+	configASSERT( ( xTaskGetTickCount() - xTimeOnEntering ) >= xTicksToBlock );
+	configASSERT( xReceivedLength == 0 );
+	( void ) xTimeOnEntering; /* In case configASSERT() is not defined. */
+
+	/* Now the message buffers have been created the echo client task can be
+	created.  If this server task has the higher priority then the client task
+	is created at the lower priority - if this server task has the lower
+	priority then the client task is created at the higher priority. */
+	if( uxTaskPriorityGet( NULL ) == mbLOWER_PRIORITY )
+	{
+		xTaskCreate( prvEchoClient, "EchoClient", configMINIMAL_STACK_SIZE,  ( void * ) &xMessageBuffers, mbHIGHER_PRIORITY, NULL );
+	}
+	else
+	{
+		/* Here prvSingleTaskTests() performs various tests on a message buffer
+		that was created dynamically. */
+		prvSingleTaskTests( xMessageBuffers.xEchoClientBuffer );
+		xTaskCreate( prvEchoClient, "EchoClient", configMINIMAL_STACK_SIZE, ( void * ) &xMessageBuffers, mbLOWER_PRIORITY, NULL );
+	}
+
+	for( ;; )
+	{
+		memset( pcReceivedString, 0x00, mbMESSAGE_BUFFER_LENGTH_BYTES );
+
+		/* Has any data been sent by the client? */
+		xReceivedLength = xMessageBufferReceive( xMessageBuffers.xEchoClientBuffer, ( void * ) pcReceivedString, mbMESSAGE_BUFFER_LENGTH_BYTES, portMAX_DELAY );
+
+		/* Should always receive data as max delay was used. */
+		configASSERT( xReceivedLength > 0 );
+
+		/* Echo the received data back to the client. */
+		xMessageBufferSend( xMessageBuffers.xEchoServerBuffer, ( void * ) pcReceivedString, xReceivedLength, portMAX_DELAY );
+
+		/* This message buffer is just created and deleted to ensure no memory
+		leaks. */
+		xTempMessageBuffer = xMessageBufferCreate( mbMESSAGE_BUFFER_LENGTH_BYTES );
+		vMessageBufferDelete( xTempMessageBuffer );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xAreMessageBufferTasksStillRunning( void )
+{
+static uint32_t ulLastEchoLoopCounters[ mbNUMBER_OF_ECHO_CLIENTS ] = { 0 };
+static uint32_t ulLastNonBlockingRxCounter = 0;
+BaseType_t xReturn = pdPASS, x;
+
+	for( x = 0; x < mbNUMBER_OF_ECHO_CLIENTS; x++ )
+	{
+		if( ulLastEchoLoopCounters[ x ] == ulEchoLoopCounters[ x ] )
+		{
+			xReturn = pdFAIL;
+		}
+		else
+		{
+			ulLastEchoLoopCounters[ x ] = ulEchoLoopCounters[ x ];
+		}
+	}
+
+	if( ulNonBlockingRxCounter == ulLastNonBlockingRxCounter )
+	{
+		xReturn = pdFAIL;
+	}
+	else
+	{
+		ulLastNonBlockingRxCounter = ulNonBlockingRxCounter;
+	}
+
+	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	{
+		static uint32_t ulLastSenderLoopCounters[ mbNUMBER_OF_ECHO_CLIENTS ] = { 0 };
+
+		for( x = 0; x < mbNUMBER_OF_SENDER_TASKS; x++ )
+		{
+			if( ulLastSenderLoopCounters[ x ] == ulSenderLoopCounters[ x ] )
+			{
+				xReturn = pdFAIL;
+			}
+			else
+			{
+				ulLastSenderLoopCounters[ x ] = ulSenderLoopCounters[ x ];
+			}
+		}
+	}
+	#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/PollQ.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/PollQ.c
new file mode 100644
index 0000000..f24dd07
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/PollQ.c
@@ -0,0 +1,223 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * This version of PollQ. c is for use on systems that have limited stack
+ * space and no display facilities.  The complete version can be found in
+ * the Demo/Common/Full directory.
+ *
+ * Creates two tasks that communicate over a single queue.  One task acts as a
+ * producer, the other a consumer.
+ *
+ * The producer loops for three iteration, posting an incrementing number onto the
+ * queue each cycle.  It then delays for a fixed period before doing exactly the
+ * same again.
+ *
+ * The consumer loops emptying the queue.  Each item removed from the queue is
+ * checked to ensure it contains the expected value.  When the queue is empty it
+ * blocks for a fixed period, then does the same again.
+ *
+ * All queue access is performed without blocking.  The consumer completely empties
+ * the queue each time it runs so the producer should never find the queue full.
+ *
+ * An error is flagged if the consumer obtains an unexpected value or the producer
+ * find the queue is full.
+ */
+
+/*
+Changes from V2.0.0
+
+	+ Delay periods are now specified using variables and constants of
+	  TickType_t rather than uint32_t.
+*/
+
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* Demo program include files. */
+#include "PollQ.h"
+
+#define pollqSTACK_SIZE			configMINIMAL_STACK_SIZE
+#define pollqQUEUE_SIZE			( 10 )
+#define pollqPRODUCER_DELAY		( pdMS_TO_TICKS( ( TickType_t ) 200 ) )
+#define pollqCONSUMER_DELAY		( pollqPRODUCER_DELAY - ( TickType_t ) ( 20 / portTICK_PERIOD_MS ) )
+#define pollqNO_DELAY			( ( TickType_t ) 0 )
+#define pollqVALUES_TO_PRODUCE	( ( BaseType_t ) 3 )
+#define pollqINITIAL_VALUE		( ( BaseType_t ) 0 )
+
+/* The task that posts the incrementing number onto the queue. */
+static portTASK_FUNCTION_PROTO( vPolledQueueProducer, pvParameters );
+
+/* The task that empties the queue. */
+static portTASK_FUNCTION_PROTO( vPolledQueueConsumer, pvParameters );
+
+/* Variables that are used to check that the tasks are still running with no
+errors. */
+static volatile BaseType_t xPollingConsumerCount = pollqINITIAL_VALUE, xPollingProducerCount = pollqINITIAL_VALUE;
+
+/*-----------------------------------------------------------*/
+
+void vStartPolledQueueTasks( UBaseType_t uxPriority )
+{
+static QueueHandle_t xPolledQueue;
+
+	/* Create the queue used by the producer and consumer. */
+	xPolledQueue = xQueueCreate( pollqQUEUE_SIZE, ( UBaseType_t ) sizeof( uint16_t ) );
+
+	if( xPolledQueue != NULL )
+	{
+		/* vQueueAddToRegistry() adds the queue to the queue registry, if one is
+		in use.  The queue registry is provided as a means for kernel aware
+		debuggers to locate queues and has no purpose if a kernel aware debugger
+		is not being used.  The call to vQueueAddToRegistry() will be removed
+		by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is
+		defined to be less than 1. */
+		vQueueAddToRegistry( xPolledQueue, "Poll_Test_Queue" );
+
+		/* Spawn the producer and consumer. */
+		xTaskCreate( vPolledQueueConsumer, "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( TaskHandle_t * ) NULL );
+		xTaskCreate( vPolledQueueProducer, "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( TaskHandle_t * ) NULL );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vPolledQueueProducer, pvParameters )
+{
+uint16_t usValue = ( uint16_t ) 0;
+BaseType_t xError = pdFALSE, xLoop;
+
+	for( ;; )
+	{
+		for( xLoop = 0; xLoop < pollqVALUES_TO_PRODUCE; xLoop++ )
+		{
+			/* Send an incrementing number on the queue without blocking. */
+			if( xQueueSend( *( ( QueueHandle_t * ) pvParameters ), ( void * ) &usValue, pollqNO_DELAY ) != pdPASS )
+			{
+				/* We should never find the queue full so if we get here there
+				has been an error. */
+				xError = pdTRUE;
+			}
+			else
+			{
+				if( xError == pdFALSE )
+				{
+					/* If an error has ever been recorded we stop incrementing the
+					check variable. */
+					portENTER_CRITICAL();
+						xPollingProducerCount++;
+					portEXIT_CRITICAL();
+				}
+
+				/* Update the value we are going to post next time around. */
+				usValue++;
+			}
+		}
+
+		/* Wait before we start posting again to ensure the consumer runs and
+		empties the queue. */
+		vTaskDelay( pollqPRODUCER_DELAY );
+	}
+}  /*lint !e818 Function prototype must conform to API. */
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vPolledQueueConsumer, pvParameters )
+{
+uint16_t usData, usExpectedValue = ( uint16_t ) 0;
+BaseType_t xError = pdFALSE;
+
+	for( ;; )
+	{
+		/* Loop until the queue is empty. */
+		while( uxQueueMessagesWaiting( *( ( QueueHandle_t * ) pvParameters ) ) )
+		{
+			if( xQueueReceive( *( ( QueueHandle_t * ) pvParameters ), &usData, pollqNO_DELAY ) == pdPASS )
+			{
+				if( usData != usExpectedValue )
+				{
+					/* This is not what we expected to receive so an error has
+					occurred. */
+					xError = pdTRUE;
+
+					/* Catch-up to the value we received so our next expected
+					value should again be correct. */
+					usExpectedValue = usData;
+				}
+				else
+				{
+					if( xError == pdFALSE )
+					{
+						/* Only increment the check variable if no errors have
+						occurred. */
+						portENTER_CRITICAL();
+							xPollingConsumerCount++;
+						portEXIT_CRITICAL();
+					}
+				}
+
+				/* Next time round we would expect the number to be one higher. */
+				usExpectedValue++;
+			}
+		}
+
+		/* Now the queue is empty we block, allowing the producer to place more
+		items in the queue. */
+		vTaskDelay( pollqCONSUMER_DELAY );
+	}
+} /*lint !e818 Function prototype must conform to API. */
+/*-----------------------------------------------------------*/
+
+/* This is called to check that all the created tasks are still running with no errors. */
+BaseType_t xArePollingQueuesStillRunning( void )
+{
+BaseType_t xReturn;
+
+	/* Check both the consumer and producer poll count to check they have both
+	been changed since out last trip round.  We do not need a critical section
+	around the check variables as this is called from a higher priority than
+	the other tasks that access the same variables. */
+	if( ( xPollingConsumerCount == pollqINITIAL_VALUE ) ||
+		( xPollingProducerCount == pollqINITIAL_VALUE )
+	  )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	/* Set the check variables back down so we know if they have been
+	incremented the next time around. */
+	xPollingConsumerCount = pollqINITIAL_VALUE;
+	xPollingProducerCount = pollqINITIAL_VALUE;
+
+	return xReturn;
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/QPeek.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/QPeek.c
new file mode 100644
index 0000000..f1820b9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/QPeek.c
@@ -0,0 +1,439 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*
+ * Tests the behaviour when data is peeked from a queue when there are
+ * multiple tasks blocked on the queue.
+ */
+
+
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+
+/* Demo program include files. */
+#include "QPeek.h"
+
+#define qpeekQUEUE_LENGTH		( 5 )
+#define qpeekNO_BLOCK			( 0 )
+#define qpeekSHORT_DELAY		( 10 )
+
+#define qpeekLOW_PRIORITY			( tskIDLE_PRIORITY + 0 )
+#define qpeekMEDIUM_PRIORITY		( tskIDLE_PRIORITY + 1 )
+#define qpeekHIGH_PRIORITY			( tskIDLE_PRIORITY + 2 )
+#define qpeekHIGHEST_PRIORITY		( tskIDLE_PRIORITY + 3 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The following three tasks are used to demonstrate the peeking behaviour.
+ * Each task is given a different priority to demonstrate the order in which
+ * tasks are woken as data is peeked from a queue.
+ */
+static void prvLowPriorityPeekTask( void *pvParameters );
+static void prvMediumPriorityPeekTask( void *pvParameters );
+static void prvHighPriorityPeekTask( void *pvParameters );
+static void prvHighestPriorityPeekTask( void *pvParameters );
+
+/*-----------------------------------------------------------*/
+
+/* Flag that will be latched to pdTRUE should any unexpected behaviour be
+detected in any of the tasks. */
+static volatile BaseType_t xErrorDetected = pdFALSE;
+
+/* Counter that is incremented on each cycle of a test.  This is used to
+detect a stalled task - a test that is no longer running. */
+static volatile uint32_t ulLoopCounter = 0;
+
+/* Handles to the test tasks. */
+TaskHandle_t xMediumPriorityTask, xHighPriorityTask, xHighestPriorityTask;
+/*-----------------------------------------------------------*/
+
+void vStartQueuePeekTasks( void )
+{
+QueueHandle_t xQueue;
+
+	/* Create the queue that we are going to use for the test/demo. */
+	xQueue = xQueueCreate( qpeekQUEUE_LENGTH, sizeof( uint32_t ) );
+
+	if( xQueue != NULL )
+	{
+		/* vQueueAddToRegistry() adds the queue to the queue registry, if one is
+		in use.  The queue registry is provided as a means for kernel aware
+		debuggers to locate queues and has no purpose if a kernel aware debugger
+		is not being used.  The call to vQueueAddToRegistry() will be removed
+		by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is
+		defined to be less than 1. */
+		vQueueAddToRegistry( xQueue, "QPeek_Test_Queue" );
+
+		/* Create the demo tasks and pass it the queue just created.  We are
+		passing the queue handle by value so it does not matter that it is declared
+		on the stack here. */
+		xTaskCreate( prvLowPriorityPeekTask, "PeekL", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekLOW_PRIORITY, NULL );
+		xTaskCreate( prvMediumPriorityPeekTask, "PeekM", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekMEDIUM_PRIORITY, &xMediumPriorityTask );
+		xTaskCreate( prvHighPriorityPeekTask, "PeekH1", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekHIGH_PRIORITY, &xHighPriorityTask );
+		xTaskCreate( prvHighestPriorityPeekTask, "PeekH2", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekHIGHEST_PRIORITY, &xHighestPriorityTask );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvHighestPriorityPeekTask( void *pvParameters )
+{
+QueueHandle_t xQueue = ( QueueHandle_t ) pvParameters;
+uint32_t ulValue;
+
+	#ifdef USE_STDIO
+	{
+		void vPrintDisplayMessage( const char * const * ppcMessageToSend );
+
+		const char * const pcTaskStartMsg = "Queue peek test started.\r\n";
+
+		/* Queue a message for printing to say the task has started. */
+		vPrintDisplayMessage( &pcTaskStartMsg );
+	}
+	#endif
+
+	for( ;; )
+	{
+		/* Try peeking from the queue.  The queue should be empty so we will
+		block, allowing the high priority task to execute. */
+		if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
+		{
+			/* We expected to have received something by the time we unblock. */
+			xErrorDetected = pdTRUE;
+		}
+
+		/* When we reach here the high and medium priority tasks should still
+		be blocked on the queue.  We unblocked because the low priority task
+		wrote a value to the queue, which we should have peeked.  Peeking the
+		data (rather than receiving it) will leave the data on the queue, so
+		the high priority task should then have also been unblocked, but not
+		yet executed. */
+		if( ulValue != 0x11223344 )
+		{
+			/* We did not receive the expected value. */
+			xErrorDetected = pdTRUE;
+		}
+
+		if( uxQueueMessagesWaiting( xQueue ) != 1 )
+		{
+			/* The message should have been left on the queue. */
+			xErrorDetected = pdTRUE;
+		}
+
+		/* Now we are going to actually receive the data, so when the high
+		priority task runs it will find the queue empty and return to the
+		blocked state. */
+		ulValue = 0;
+		if( xQueueReceive( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS )
+		{
+			/* We expected to receive the value. */
+			xErrorDetected = pdTRUE;
+		}
+
+		if( ulValue != 0x11223344 )
+		{
+			/* We did not receive the expected value - which should have been
+			the same value as was peeked. */
+			xErrorDetected = pdTRUE;
+		}
+
+		/* Now we will block again as the queue is once more empty.  The low
+		priority task can then execute again. */
+		if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
+		{
+			/* We expected to have received something by the time we unblock. */
+			xErrorDetected = pdTRUE;
+		}
+
+		/* When we get here the low priority task should have again written to the
+		queue. */
+		if( ulValue != 0x01234567 )
+		{
+			/* We did not receive the expected value. */
+			xErrorDetected = pdTRUE;
+		}
+
+		if( uxQueueMessagesWaiting( xQueue ) != 1 )
+		{
+			/* The message should have been left on the queue. */
+			xErrorDetected = pdTRUE;
+		}
+
+		/* We only peeked the data, so suspending ourselves now should enable
+		the high priority task to also peek the data.  The high priority task
+		will have been unblocked when we peeked the data as we left the data
+		in the queue. */
+		vTaskSuspend( NULL );
+
+
+
+		/* This time we are going to do the same as the above test, but the
+		high priority task is going to receive the data, rather than peek it.
+		This means that the medium priority task should never peek the value. */
+		if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		if( ulValue != 0xaabbaabb )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		vTaskSuspend( NULL );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvHighPriorityPeekTask( void *pvParameters )
+{
+QueueHandle_t xQueue = ( QueueHandle_t ) pvParameters;
+uint32_t ulValue;
+
+	for( ;; )
+	{
+		/* Try peeking from the queue.  The queue should be empty so we will
+		block, allowing the medium priority task to execute.  Both the high
+		and highest priority tasks will then be blocked on the queue. */
+		if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
+		{
+			/* We expected to have received something by the time we unblock. */
+			xErrorDetected = pdTRUE;
+		}
+
+		/* When we get here the highest priority task should have peeked the data
+		(unblocking this task) then suspended (allowing this task to also peek
+		the data). */
+		if( ulValue != 0x01234567 )
+		{
+			/* We did not receive the expected value. */
+			xErrorDetected = pdTRUE;
+		}
+
+		if( uxQueueMessagesWaiting( xQueue ) != 1 )
+		{
+			/* The message should have been left on the queue. */
+			xErrorDetected = pdTRUE;
+		}
+
+		/* We only peeked the data, so suspending ourselves now should enable
+		the medium priority task to also peek the data.  The medium priority task
+		will have been unblocked when we peeked the data as we left the data
+		in the queue. */
+		vTaskSuspend( NULL );
+
+
+		/* This time we are going actually receive the value, so the medium
+		priority task will never peek the data - we removed it from the queue. */
+		if( xQueueReceive( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		if( ulValue != 0xaabbaabb )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		vTaskSuspend( NULL );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvMediumPriorityPeekTask( void *pvParameters )
+{
+QueueHandle_t xQueue = ( QueueHandle_t ) pvParameters;
+uint32_t ulValue;
+
+	for( ;; )
+	{
+		/* Try peeking from the queue.  The queue should be empty so we will
+		block, allowing the low priority task to execute.  The highest, high
+		and medium priority tasks will then all be blocked on the queue. */
+		if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
+		{
+			/* We expected to have received something by the time we unblock. */
+			xErrorDetected = pdTRUE;
+		}
+
+		/* When we get here the high priority task should have peeked the data
+		(unblocking this task) then suspended (allowing this task to also peek
+		the data). */
+		if( ulValue != 0x01234567 )
+		{
+			/* We did not receive the expected value. */
+			xErrorDetected = pdTRUE;
+		}
+
+		if( uxQueueMessagesWaiting( xQueue ) != 1 )
+		{
+			/* The message should have been left on the queue. */
+			xErrorDetected = pdTRUE;
+		}
+
+		/* Just so we know the test is still running. */
+		ulLoopCounter++;
+
+		/* Now we can suspend ourselves so the low priority task can execute
+		again. */
+		vTaskSuspend( NULL );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvLowPriorityPeekTask( void *pvParameters )
+{
+QueueHandle_t xQueue = ( QueueHandle_t ) pvParameters;
+uint32_t ulValue;
+
+	for( ;; )
+	{
+		/* Write some data to the queue.  This should unblock the highest
+		priority task that is waiting to peek data from the queue. */
+		ulValue = 0x11223344;
+		if( xQueueSendToBack( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS )
+		{
+			/* We were expecting the queue to be empty so we should not of
+			had a problem writing to the queue. */
+			xErrorDetected = pdTRUE;
+		}
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+		/* By the time we get here the data should have been removed from
+		the queue. */
+		if( uxQueueMessagesWaiting( xQueue ) != 0 )
+		{
+			xErrorDetected = pdTRUE;
+		}
+
+		/* Write another value to the queue, again waking the highest priority
+		task that is blocked on the queue. */
+		ulValue = 0x01234567;
+		if( xQueueSendToBack( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS )
+		{
+			/* We were expecting the queue to be empty so we should not of
+			had a problem writing to the queue. */
+			xErrorDetected = pdTRUE;
+		}
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+		/* All the other tasks should now have successfully peeked the data.
+		The data is still in the queue so we should be able to receive it. */
+		ulValue = 0;
+		if( xQueueReceive( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS )
+		{
+			/* We expected to receive the data. */
+			xErrorDetected = pdTRUE;
+		}
+
+		if( ulValue != 0x01234567 )
+		{
+			/* We did not receive the expected value. */
+		}
+
+		/* Lets just delay a while as this is an intensive test as we don't
+		want to starve other tests of processing time. */
+		vTaskDelay( qpeekSHORT_DELAY );
+
+		/* Unsuspend the other tasks so we can repeat the test - this time
+		however not all the other tasks will peek the data as the high
+		priority task is actually going to remove it from the queue.  Send
+		to front is used just to be different.  As the queue is empty it
+		makes no difference to the result. */
+		vTaskResume( xMediumPriorityTask );
+		vTaskResume( xHighPriorityTask );
+		vTaskResume( xHighestPriorityTask );
+
+		#if( configUSE_PREEMPTION == 0 )
+			taskYIELD();
+		#endif
+
+		ulValue = 0xaabbaabb;
+		if( xQueueSendToFront( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS )
+		{
+			/* We were expecting the queue to be empty so we should not of
+			had a problem writing to the queue. */
+			xErrorDetected = pdTRUE;
+		}
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+		/* This time we should find that the queue is empty.  The high priority
+		task actually removed the data rather than just peeking it. */
+		if( xQueuePeek( xQueue, &ulValue, qpeekNO_BLOCK ) != errQUEUE_EMPTY )
+		{
+			/* We expected to receive the data. */
+			xErrorDetected = pdTRUE;
+		}
+
+		/* Unsuspend the highest and high priority tasks so we can go back
+		and repeat the whole thing.  The medium priority task should not be
+		suspended as it was not able to peek the data in this last case. */
+		vTaskResume( xHighPriorityTask );
+		vTaskResume( xHighestPriorityTask );
+
+		/* Lets just delay a while as this is an intensive test as we don't
+		want to starve other tests of processing time. */
+		vTaskDelay( qpeekSHORT_DELAY );
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* This is called to check that all the created tasks are still running. */
+BaseType_t xAreQueuePeekTasksStillRunning( void )
+{
+static uint32_t ulLastLoopCounter = 0;
+
+	/* If the demo task is still running then we expect the loopcounter to
+	have incremented since this function was last called. */
+	if( ulLastLoopCounter == ulLoopCounter )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	ulLastLoopCounter = ulLoopCounter;
+
+	/* Errors detected in the task itself will have latched xErrorDetected
+	to true. */
+
+	return ( BaseType_t ) !xErrorDetected;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/QueueOverwrite.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/QueueOverwrite.c
new file mode 100644
index 0000000..5b1dea5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/QueueOverwrite.c
@@ -0,0 +1,230 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Basic task to demonstrate the xQueueOverwrite() function.  See the comments
+ * in the function itself.
+ */
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* Demo program include files. */
+#include "QueueOverwrite.h"
+
+/* A block time of 0 just means "don't block". */
+#define qoDONT_BLOCK		0
+
+/* Number of times to overwrite the value in the queue. */
+#define qoLOOPS			5
+
+/* The task that uses the queue. */
+static void prvQueueOverwriteTask( void *pvParameters );
+
+/* Variable that is incremented on each loop of prvQueueOverwriteTask() provided
+prvQueueOverwriteTask() has not found any errors. */
+static uint32_t ulLoopCounter = 0;
+
+/* Set to pdFALSE if an error is discovered by the
+vQueueOverwritePeriodicISRDemo() function. */
+static BaseType_t xISRTestStatus = pdPASS;
+
+/* The queue that is accessed from the ISR.  The queue accessed by the task is
+created inside the task itself. */
+static QueueHandle_t xISRQueue = NULL;
+
+/*-----------------------------------------------------------*/
+
+void vStartQueueOverwriteTask( UBaseType_t uxPriority )
+{
+const UBaseType_t uxQueueLength = 1;
+
+	/* Create the queue used by the ISR.  xQueueOverwriteFromISR() should only
+	be used on queues that have a length of 1. */
+	xISRQueue = xQueueCreate( uxQueueLength, ( UBaseType_t ) sizeof( uint32_t ) );
+
+	/* Create the test task.  The queue used by the test task is created inside
+	the task itself. */
+	xTaskCreate( prvQueueOverwriteTask, "QOver", configMINIMAL_STACK_SIZE, NULL, uxPriority, ( TaskHandle_t * ) NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueOverwriteTask( void *pvParameters )
+{
+QueueHandle_t xTaskQueue;
+const UBaseType_t uxQueueLength = 1;
+uint32_t ulValue, ulStatus = pdPASS, x;
+
+	/* The parameter is not used. */
+	( void ) pvParameters;
+
+	/* Create the queue.  xQueueOverwrite() should only be used on queues that
+	have a length of 1. */
+	xTaskQueue = xQueueCreate( uxQueueLength, ( UBaseType_t ) sizeof( uint32_t ) );
+	configASSERT( xTaskQueue );
+
+	for( ;; )
+	{
+		/* The queue is empty.  Writing to the queue then reading from the queue
+		should return the item written. */
+		ulValue = 10;
+		xQueueOverwrite( xTaskQueue, &ulValue );
+
+		ulValue = 0;
+		xQueueReceive( xTaskQueue, &ulValue, qoDONT_BLOCK );
+
+		if( ulValue != 10 )
+		{
+			ulStatus = pdFAIL;
+		}
+
+		/* Now try writing to the queue several times.  Each time the value
+		in the queue should get overwritten. */
+		for( x = 0; x < qoLOOPS; x++ )
+		{
+			/* Write to the queue. */
+			xQueueOverwrite( xTaskQueue, &x );
+
+			/* Check the value in the queue is that written, even though the
+			queue was not necessarily empty. */
+			xQueuePeek( xTaskQueue, &ulValue, qoDONT_BLOCK );
+			if( ulValue != x )
+			{
+				ulStatus = pdFAIL;
+			}
+
+			/* There should always be one item in the queue. */
+			if( uxQueueMessagesWaiting( xTaskQueue ) != uxQueueLength )
+			{
+				ulStatus = pdFAIL;
+			}
+		}
+
+		/* Empty the queue again. */
+		xQueueReceive( xTaskQueue, &ulValue, qoDONT_BLOCK );
+
+		if( uxQueueMessagesWaiting( xTaskQueue ) != 0 )
+		{
+			ulStatus = pdFAIL;
+		}
+
+		if( ulStatus != pdFAIL )
+		{
+			/* Increment a counter to show this task is still running without
+			error. */
+			ulLoopCounter++;
+		}
+
+		#if( configUSE_PREEMPTION == 0 )
+			taskYIELD();
+		#endif
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsQueueOverwriteTaskStillRunning( void )
+{
+BaseType_t xReturn;
+
+	if( xISRTestStatus != pdPASS )
+	{
+		xReturn = pdFAIL;
+	}
+	else if( ulLoopCounter > 0 )
+	{
+		xReturn = pdPASS;
+	}
+	else
+	{
+		/* The task has either stalled of discovered an error. */
+		xReturn = pdFAIL;
+	}
+
+	ulLoopCounter = 0;
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vQueueOverwritePeriodicISRDemo( void )
+{
+static uint32_t ulCallCount = 0;
+const uint32_t ulTx1 = 10UL, ulTx2 = 20UL, ulNumberOfSwitchCases = 3UL;
+uint32_t ulRx;
+
+	/* This function should be called from an interrupt, such as the tick hook
+	function vApplicationTickHook(). */
+
+	configASSERT( xISRQueue );
+
+	switch( ulCallCount )
+	{
+		case 0:
+			/* The queue is empty.  Write ulTx1 to the queue.  In this demo the
+			last parameter is not used because there are no tasks blocked on
+			this queue. */
+			xQueueOverwriteFromISR( xISRQueue, &ulTx1, NULL );
+
+			/* Peek the queue to check it holds the expected value. */
+			xQueuePeekFromISR( xISRQueue, &ulRx );
+			if( ulRx != ulTx1 )
+			{
+				xISRTestStatus = pdFAIL;
+			}
+			break;
+
+		case 1:
+			/* The queue already holds ulTx1.  Overwrite the value in the queue
+			with ulTx2. */
+			xQueueOverwriteFromISR( xISRQueue, &ulTx2, NULL );
+			break;
+
+		case 2:
+			/* Read from the queue to empty the queue again.  The value read
+			should be ulTx2. */
+			xQueueReceiveFromISR( xISRQueue, &ulRx, NULL );
+
+			if( ulRx != ulTx2 )
+			{
+				xISRTestStatus = pdFAIL;
+			}
+			break;
+	}
+
+	/* Run the next case in the switch statement above next time this function
+	is called. */
+	ulCallCount++;
+
+	if( ulCallCount >= ulNumberOfSwitchCases )
+	{
+		/* Go back to the start. */
+		ulCallCount = 0;
+	}
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/QueueSet.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/QueueSet.c
new file mode 100644
index 0000000..0dc5928
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/QueueSet.c
@@ -0,0 +1,775 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Tests the use of queue sets.
+ *
+ * A receive task creates a number of queues and adds them to a queue set before
+ * blocking on the queue set receive.  A transmit task and (optionally) an
+ * interrupt repeatedly unblocks the receive task by sending messages to the
+ * queues in a pseudo random order.  The receive task removes the messages from
+ * the queues and flags an error if the received message does not match that
+ * expected.  The task sends values in the range 0 to
+ * queuesetINITIAL_ISR_TX_VALUE, and the ISR sends value in the range
+ * queuesetINITIAL_ISR_TX_VALUE to ULONG_MAX.
+ */
+
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* Demo includes. */
+#include "QueueSet.h"
+
+/* The number of queues that are created and added to the queue set. */
+#define queuesetNUM_QUEUES_IN_SET 3
+
+/* The length of each created queue. */
+#define queuesetQUEUE_LENGTH	3
+
+/* Block times used in this demo.  A block time or 0 means "don't block". */
+#define queuesetSHORT_DELAY	200
+#define queuesetDONT_BLOCK 0
+
+/* Messages are sent in incrementing order from both a task and an interrupt.
+The task sends values in the range 0 to 0xfffe, and the interrupt sends values
+in the range of 0xffff to ULONG_MAX. */
+#define queuesetINITIAL_ISR_TX_VALUE 0xffffUL
+
+/* The priorities used in this demo. */
+#define queuesetLOW_PRIORITY	( tskIDLE_PRIORITY )
+#define queuesetMEDIUM_PRIORITY ( queuesetLOW_PRIORITY + 1 )
+
+/* For test purposes the priority of the sending task is changed after every
+queuesetPRIORITY_CHANGE_LOOPS number of values are sent to a queue. */
+#define queuesetPRIORITY_CHANGE_LOOPS	( ( queuesetNUM_QUEUES_IN_SET * queuesetQUEUE_LENGTH ) * 2 )
+
+/* The ISR sends to the queue every queuesetISR_TX_PERIOD ticks. */
+#define queuesetISR_TX_PERIOD	( 100UL )
+
+/* A delay inserted when the Tx task changes its priority to be above the idle
+task priority to ensure the idle priority tasks get some CPU time before the
+next iteration of the queue set Tx task. */
+#define queuesetTX_LOOP_DELAY	pdMS_TO_TICKS( ( TickType_t ) 200 )
+
+/* The allowable maximum deviation between a received value and the expected
+received value.  A deviation will occur when data is received from a queue
+inside an ISR in between a task receiving from a queue and the task checking
+the received value. */
+#define queuesetALLOWABLE_RX_DEVIATION 3
+
+/* Ignore values that are at the boundaries of allowable values to make the
+testing of limits easier (don't have to deal with wrapping values). */
+#define queuesetIGNORED_BOUNDARY	( queuesetALLOWABLE_RX_DEVIATION * 2 )
+
+typedef enum
+{
+	eEqualPriority = 0,	/* Tx and Rx tasks have the same priority. */
+	eTxHigherPriority,	/* The priority of the Tx task is above that of the Rx task. */
+	eTxLowerPriority	/* The priority of the Tx task is below that of the Rx task. */
+} eRelativePriorities;
+
+/*
+ * The task that periodically sends to the queue set.
+ */
+static void prvQueueSetSendingTask( void *pvParameters );
+
+/*
+ * The task that reads from the queue set.
+ */
+static void prvQueueSetReceivingTask( void *pvParameters );
+
+/*
+ * Check the value received from a queue is the expected value.  Some values
+ * originate from the send task, some values originate from the ISR, with the
+ * range of the value being used to distinguish between the two message
+ * sources.
+ */
+static void prvCheckReceivedValue( uint32_t ulReceived );
+
+/*
+ * For purposes of test coverage, functions that read from and write to a
+ * queue set from an ISR respectively.
+ */
+static void prvReceiveFromQueueInSetFromISR( void );
+static void prvSendToQueueInSetFromISR( void );
+
+/*
+ * Create the queues and add them to a queue set before resuming the Tx
+ * task.
+ */
+static void prvSetupTest( void );
+
+/*
+ * Checks a value received from a queue falls within the range of expected
+ * values.
+ */
+static BaseType_t prvCheckReceivedValueWithinExpectedRange( uint32_t ulReceived, uint32_t ulExpectedReceived );
+
+/*
+ * Increase test coverage by occasionally change the priorities of the two tasks
+ * relative to each other.
+ */
+static void prvChangeRelativePriorities( void );
+
+/*
+ * Queue overwrites can only be performed on queues of length of one, requiring
+ * a special test function so a queue of length 1 can temporarily be added to a
+ * set.
+ */
+static void prvTestQueueOverwriteWithQueueSet( void );
+
+/*
+ * Local pseudo random number seed and return functions.  Used to avoid calls
+ * to the standard library.
+ */
+static size_t prvRand( void );
+static void prvSRand( size_t uxSeed );
+
+/*-----------------------------------------------------------*/
+
+/* The queues that are added to the set. */
+static QueueHandle_t xQueues[ queuesetNUM_QUEUES_IN_SET ] = { 0 };
+
+/* Counts how many times each queue in the set is used to ensure all the
+queues are used. */
+static uint32_t ulQueueUsedCounter[ queuesetNUM_QUEUES_IN_SET ] = { 0 };
+
+/* The handle of the queue set to which the queues are added. */
+static QueueSetHandle_t xQueueSet;
+
+/* If the prvQueueSetReceivingTask() task has not detected any errors then
+it increments ulCycleCounter on each iteration.
+xAreQueueSetTasksStillRunning() returns pdPASS if the value of
+ulCycleCounter has changed between consecutive calls, and pdFALSE if
+ulCycleCounter has stopped incrementing (indicating an error condition). */
+static volatile uint32_t ulCycleCounter = 0UL;
+
+/* Set to pdFAIL if an error is detected by any queue set task.
+ulCycleCounter will only be incremented if xQueueSetTasksSatus equals pdPASS. */
+static volatile BaseType_t xQueueSetTasksStatus = pdPASS;
+
+/* Just a flag to let the function that writes to a queue from an ISR know that
+the queues are setup and can be used. */
+static volatile BaseType_t xSetupComplete = pdFALSE;
+
+/* The value sent to the queue from the ISR is file scope so the
+xAreQueeuSetTasksStillRunning() function can check it is incrementing as
+expected. */
+static volatile uint32_t ulISRTxValue = queuesetINITIAL_ISR_TX_VALUE;
+
+/* Used by the pseudo random number generator. */
+static size_t uxNextRand = 0;
+
+/* The task handles are stored so their priorities can be changed. */
+TaskHandle_t xQueueSetSendingTask, xQueueSetReceivingTask;
+
+/*-----------------------------------------------------------*/
+
+void vStartQueueSetTasks( void )
+{
+	/* Create the tasks. */
+	xTaskCreate( prvQueueSetSendingTask, "SetTx", configMINIMAL_STACK_SIZE, NULL, queuesetMEDIUM_PRIORITY, &xQueueSetSendingTask );
+
+	if( xQueueSetSendingTask != NULL )
+	{
+		xTaskCreate( prvQueueSetReceivingTask, "SetRx", configMINIMAL_STACK_SIZE, ( void * ) xQueueSetSendingTask, queuesetMEDIUM_PRIORITY, &xQueueSetReceivingTask );
+
+		/* It is important that the sending task does not attempt to write to a
+		queue before the queue has been created.  It is therefore placed into
+		the suspended state before the scheduler has started.  It is resumed by
+		the receiving task after the receiving task has created the queues and
+		added the queues to the queue set. */
+		vTaskSuspend( xQueueSetSendingTask );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xAreQueueSetTasksStillRunning( void )
+{
+static uint32_t ulLastCycleCounter, ulLastISRTxValue = 0;
+static uint32_t ulLastQueueUsedCounter[ queuesetNUM_QUEUES_IN_SET ] = { 0 };
+BaseType_t xReturn = pdPASS, x;
+
+	if( ulLastCycleCounter == ulCycleCounter )
+	{
+		/* The cycle counter is no longer being incremented.  Either one of the
+		tasks is stalled or an error has been detected. */
+		xReturn = pdFAIL;
+	}
+
+	ulLastCycleCounter = ulCycleCounter;
+
+	/* Ensure that all the queues in the set have been used.  This ensures the
+	test is working as intended and guards against the rand() in the Tx task
+	missing some values. */
+	for( x = 0; x < queuesetNUM_QUEUES_IN_SET; x++ )
+	{
+		if( ulLastQueueUsedCounter[ x ] == ulQueueUsedCounter[ x ] )
+		{
+			xReturn = pdFAIL;
+		}
+
+		ulLastQueueUsedCounter[ x ] = ulQueueUsedCounter[ x ];
+	}
+
+	/* Check the global status flag. */
+	if( xQueueSetTasksStatus != pdPASS )
+	{
+		xReturn = pdFAIL;
+	}
+
+	/* Check that the ISR is still sending values to the queues too. */
+	if( ulISRTxValue == ulLastISRTxValue )
+	{
+		xReturn = pdFAIL;
+	}
+	else
+	{
+		ulLastISRTxValue = ulISRTxValue;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueSetSendingTask( void *pvParameters )
+{
+uint32_t ulTaskTxValue = 0;
+size_t uxQueueToWriteTo;
+QueueHandle_t xQueueInUse;
+
+	/* Remove compiler warning about the unused parameter. */
+	( void ) pvParameters;
+
+	/* Seed mini pseudo random number generator. */
+	prvSRand( ( size_t ) &ulTaskTxValue );
+
+	for( ;; )
+	{
+		/* Generate the index for the queue to which a value is to be sent. */
+		uxQueueToWriteTo = prvRand() % queuesetNUM_QUEUES_IN_SET;
+		xQueueInUse = xQueues[ uxQueueToWriteTo ];
+
+		/* Note which index is being written to to ensure all the queues are
+		used. */
+		( ulQueueUsedCounter[ uxQueueToWriteTo ] )++;
+
+		/* Send to the queue to unblock the task that is waiting for data to
+		arrive on a queue within the queue set to which this queue belongs. */
+		if( xQueueSendToBack( xQueueInUse, &ulTaskTxValue, portMAX_DELAY ) != pdPASS )
+		{
+			/* The send should always pass as an infinite block time was
+			used. */
+			xQueueSetTasksStatus = pdFAIL;
+		}
+
+		#if( configUSE_PREEMPTION == 0 )
+			taskYIELD();
+		#endif
+
+		ulTaskTxValue++;
+
+		/* If the Tx value has reached the range used by the ISR then set it
+		back to 0. */
+		if( ulTaskTxValue == queuesetINITIAL_ISR_TX_VALUE )
+		{
+			ulTaskTxValue = 0;
+		}
+
+		/* Increase test coverage by occasionally change the priorities of the
+		two tasks relative to each other. */
+		prvChangeRelativePriorities();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvChangeRelativePriorities( void )
+{
+static UBaseType_t ulLoops = 0;
+static eRelativePriorities ePriorities = eEqualPriority;
+
+	/* Occasionally change the task priority relative to the priority of
+	the receiving task. */
+	ulLoops++;
+	if( ulLoops >= queuesetPRIORITY_CHANGE_LOOPS )
+	{
+		ulLoops = 0;
+
+		switch( ePriorities )
+		{
+			case eEqualPriority:
+				/* Both tasks are running with medium priority.  Now lower the
+				priority of the receiving task so the Tx task has the higher
+				relative priority. */
+				vTaskPrioritySet( xQueueSetReceivingTask, queuesetLOW_PRIORITY );
+				ePriorities = eTxHigherPriority;
+				break;
+
+			case eTxHigherPriority:
+				/* The Tx task is running with a higher priority than the Rx
+				task.  Switch the priorities around so the Rx task has the
+				higher relative priority. */
+				vTaskPrioritySet( xQueueSetReceivingTask, queuesetMEDIUM_PRIORITY );
+				vTaskPrioritySet( xQueueSetSendingTask, queuesetLOW_PRIORITY );
+				ePriorities = eTxLowerPriority;
+				break;
+
+			case eTxLowerPriority:
+				/* The Tx task is running with a lower priority than the Rx
+				task.  Make the priorities equal again. */
+				vTaskPrioritySet( xQueueSetSendingTask, queuesetMEDIUM_PRIORITY );
+				ePriorities = eEqualPriority;
+
+				/* When both tasks are using a non-idle priority the queue set
+				tasks will starve idle priority tasks of execution time - so
+				relax a bit before the next iteration to minimise the impact. */
+				vTaskDelay( queuesetTX_LOOP_DELAY );
+
+				break;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueSetReceivingTask( void *pvParameters )
+{
+uint32_t ulReceived;
+QueueHandle_t xActivatedQueue;
+TickType_t xBlockTime;
+
+	/* Remove compiler warnings. */
+	( void ) pvParameters;
+
+	/* Create the queues and add them to the queue set before resuming the Tx
+	task. */
+	prvSetupTest();
+
+	for( ;; )
+	{
+		/* For test coverage reasons, the block time is dependent on the
+		priority of this task - which changes during the test.  When the task
+		is at the idle priority it polls the queue set. */
+		if( uxTaskPriorityGet( NULL ) == tskIDLE_PRIORITY )
+		{
+			xBlockTime = 0;
+		}
+		else
+		{
+			xBlockTime = portMAX_DELAY;
+		}
+
+		/* Wait for a message to arrive on one of the queues in the set. */
+		xActivatedQueue = xQueueSelectFromSet( xQueueSet, portMAX_DELAY );
+
+		if( xActivatedQueue == NULL )
+		{
+			if( xBlockTime != 0 )
+			{
+				/* This should not happen as an infinite delay was used. */
+				xQueueSetTasksStatus = pdFAIL;
+			}
+		}
+		else
+		{
+			/* Reading from the queue should pass with a zero block time as
+			this task will only run when something has been posted to a task
+			in the queue set. */
+			if( xQueueReceive( xActivatedQueue, &ulReceived, queuesetDONT_BLOCK ) != pdPASS )
+			{
+				xQueueSetTasksStatus = pdFAIL;
+			}
+
+			/* Ensure the value received was the value expected.  This function
+			manipulates file scope data and is also called from an ISR, hence
+			the critical section. */
+			taskENTER_CRITICAL();
+			{
+				prvCheckReceivedValue( ulReceived );
+			}
+			taskEXIT_CRITICAL();
+
+			if( xQueueSetTasksStatus == pdPASS )
+			{
+				ulCycleCounter++;
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vQueueSetAccessQueueSetFromISR( void )
+{
+static uint32_t ulCallCount = 0;
+
+	/* xSetupComplete is set to pdTRUE when the queues have been created and
+	are available for use. */
+	if( xSetupComplete == pdTRUE )
+	{
+		/* It is intended that this function is called from the tick hook
+		function, so each call is one tick period apart. */
+		ulCallCount++;
+		if( ulCallCount > queuesetISR_TX_PERIOD )
+		{
+			ulCallCount = 0;
+
+			/* First attempt to read from the queue set. */
+			prvReceiveFromQueueInSetFromISR();
+
+			/* Then write to the queue set. */
+			prvSendToQueueInSetFromISR();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckReceivedValue( uint32_t ulReceived )
+{
+static uint32_t ulExpectedReceivedFromTask = 0, ulExpectedReceivedFromISR = queuesetINITIAL_ISR_TX_VALUE;
+
+	/* Values are received in tasks and interrupts.  It is likely that the
+	receiving task will sometimes get preempted by the receiving interrupt
+	between reading a value from the queue and calling this function.  When
+	that happens, if the receiving interrupt calls this function the values
+	will get passed into this function slightly out of order.  For that
+	reason the value passed in is tested against a small range of expected
+	values, rather than a single absolute value.  To make the range testing
+	easier values in the range limits are ignored. */
+
+	/* If the received value is equal to or greater than
+	queuesetINITIAL_ISR_TX_VALUE then it was sent by an ISR. */
+	if( ulReceived >= queuesetINITIAL_ISR_TX_VALUE )
+	{
+		/* The value was sent from the ISR. */
+		if( ( ulReceived - queuesetINITIAL_ISR_TX_VALUE ) < queuesetIGNORED_BOUNDARY )
+		{
+			/* The value received is at the lower limit of the expected range.
+			Don't test it and expect to receive one higher next time. */
+		}
+		else if( ( ULONG_MAX - ulReceived ) <= queuesetIGNORED_BOUNDARY )
+		{
+			/* The value received is at the higher limit of the expected range.
+			Don't test it and expect to wrap soon. */
+		}
+		else
+		{
+			/* Check the value against its expected value range. */
+			if( prvCheckReceivedValueWithinExpectedRange( ulReceived, ulExpectedReceivedFromISR ) != pdPASS )
+			{
+				xQueueSetTasksStatus = pdFAIL;
+			}
+		}
+
+		configASSERT( xQueueSetTasksStatus );
+
+		/* It is expected to receive an incrementing number. */
+		ulExpectedReceivedFromISR++;
+		if( ulExpectedReceivedFromISR == 0 )
+		{
+			ulExpectedReceivedFromISR = queuesetINITIAL_ISR_TX_VALUE;
+		}
+	}
+	else
+	{
+		/* The value was sent from the Tx task. */
+		if( ulReceived < queuesetIGNORED_BOUNDARY )
+		{
+			/* The value received is at the lower limit of the expected range.
+			Don't test it, and expect to receive one higher next time. */
+		}
+		else if( ( ( queuesetINITIAL_ISR_TX_VALUE - 1 ) - ulReceived ) <= queuesetIGNORED_BOUNDARY )
+		{
+			/* The value received is at the higher limit of the expected range.
+			Don't test it and expect to wrap soon. */
+		}
+		else
+		{
+			/* Check the value against its expected value range. */
+			if( prvCheckReceivedValueWithinExpectedRange( ulReceived, ulExpectedReceivedFromTask ) != pdPASS )
+			{
+				xQueueSetTasksStatus = pdFAIL;
+			}
+		}
+
+		configASSERT( xQueueSetTasksStatus );
+
+		/* It is expected to receive an incrementing number. */
+		ulExpectedReceivedFromTask++;
+		if( ulExpectedReceivedFromTask >= queuesetINITIAL_ISR_TX_VALUE )
+		{
+			ulExpectedReceivedFromTask = 0;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvCheckReceivedValueWithinExpectedRange( uint32_t ulReceived, uint32_t ulExpectedReceived )
+{
+BaseType_t xReturn = pdPASS;
+
+	if( ulReceived > ulExpectedReceived )
+	{
+		configASSERT( ( ulReceived - ulExpectedReceived ) <= queuesetALLOWABLE_RX_DEVIATION );
+		if( ( ulReceived - ulExpectedReceived ) > queuesetALLOWABLE_RX_DEVIATION )
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	else
+	{
+		configASSERT( ( ulExpectedReceived - ulReceived ) <= queuesetALLOWABLE_RX_DEVIATION );
+		if( ( ulExpectedReceived - ulReceived ) > queuesetALLOWABLE_RX_DEVIATION )
+		{
+			xReturn = pdFALSE;
+		}
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void prvReceiveFromQueueInSetFromISR( void )
+{
+QueueSetMemberHandle_t xActivatedQueue;
+uint32_t ulReceived;
+
+	/* See if any of the queues in the set contain data. */
+	xActivatedQueue = xQueueSelectFromSetFromISR( xQueueSet );
+
+	if( xActivatedQueue != NULL )
+	{
+		/* Reading from the queue for test purposes only. */
+		if( xQueueReceiveFromISR( xActivatedQueue, &ulReceived, NULL ) != pdPASS )
+		{
+			/* Data should have been available as the handle was returned from
+			xQueueSelectFromSetFromISR(). */
+			xQueueSetTasksStatus = pdFAIL;
+		}
+
+		/* Ensure the value received was the value expected. */
+		prvCheckReceivedValue( ulReceived );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSendToQueueInSetFromISR( void )
+{
+static BaseType_t xQueueToWriteTo = 0;
+uint32_t ulTxValueSnapshot = ulISRTxValue;
+
+	if( xQueueSendFromISR( xQueues[ xQueueToWriteTo ], ( void * ) &ulTxValueSnapshot, NULL ) == pdPASS )
+	{
+		ulISRTxValue++;
+
+		/* If the Tx value has wrapped then set it back to its initial value. */
+		if( ulISRTxValue == 0UL )
+		{
+			ulISRTxValue = queuesetINITIAL_ISR_TX_VALUE;
+		}
+
+		/* Use a different queue next time. */
+		xQueueToWriteTo++;
+		if( xQueueToWriteTo >= queuesetNUM_QUEUES_IN_SET )
+		{
+			xQueueToWriteTo = 0;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvTestQueueOverwriteWithQueueSet( void )
+{
+uint32_t ulValueToSend = 0, ulValueReceived = 0;
+QueueHandle_t xQueueHandle = NULL, xReceivedHandle = NULL;
+const UBaseType_t xLengthOfOne = ( UBaseType_t ) 1;
+
+	/* Create a queue that has a length of one - a requirement in order to call
+	xQueueOverwrite.  This will get deleted again when this test completes. */
+	xQueueHandle = xQueueCreate( xLengthOfOne, sizeof( uint32_t ) );
+
+	if( xQueueHandle != NULL )
+	{
+		xQueueAddToSet( xQueueHandle, xQueueSet );
+
+		/* Add an item to the queue then ensure the queue set correctly
+		indicates that one item is available, and that that item is indeed the
+		queue written to. */
+		xQueueOverwrite( xQueueHandle, ( void * ) &ulValueToSend );
+		if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 )
+		{
+			/* Expected one item in the queue set. */
+			xQueueSetTasksStatus = pdFAIL;
+		}
+		xQueuePeek( xQueueSet, &xReceivedHandle, queuesetDONT_BLOCK );
+		if( xReceivedHandle != xQueueHandle )
+		{
+			/* Wrote to xQueueHandle so expected xQueueHandle to be the handle
+			held in the queue set. */
+			xQueueSetTasksStatus = pdFAIL;
+		}
+
+		/* Now overwrite the value in the queue and ensure the queue set state
+		doesn't change as the number of items in the queues within the set have
+		not changed. */
+		ulValueToSend++;
+		xQueueOverwrite( xQueueHandle, ( void * ) &ulValueToSend );
+		if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 )
+		{
+			/* Still expected one item in the queue set. */
+			xQueueSetTasksStatus = pdFAIL;
+		}
+		xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK );
+		if( xReceivedHandle != xQueueHandle )
+		{
+			/* Wrote to xQueueHandle so expected xQueueHandle to be the handle
+			held in the queue set. */
+			xQueueSetTasksStatus = pdFAIL;
+		}
+
+		/* Also ensure the value received from the queue is the overwritten
+		value, not the value originally written. */
+		xQueueReceive( xQueueHandle, &ulValueReceived, queuesetDONT_BLOCK );
+		if( ulValueReceived != ulValueToSend )
+		{
+			/* Unexpected value recevied from the queue. */
+			xQueueSetTasksStatus = pdFAIL;
+		}
+
+		/* Clean up. */
+		xQueueRemoveFromSet( xQueueHandle, xQueueSet );
+		vQueueDelete( xQueueHandle );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTest( void )
+{
+BaseType_t x;
+uint32_t ulValueToSend = 0;
+
+	/* Ensure the queues are created and the queue set configured before the
+	sending task is unsuspended.
+
+	First Create the queue set such that it will be able to hold a message for
+	every space in every queue in the set. */
+	xQueueSet = xQueueCreateSet( queuesetNUM_QUEUES_IN_SET * queuesetQUEUE_LENGTH );
+
+	for( x = 0; x < queuesetNUM_QUEUES_IN_SET; x++ )
+	{
+		/* Create the queue and add it to the set.  The queue is just holding
+		uint32_t value. */
+		xQueues[ x ] = xQueueCreate( queuesetQUEUE_LENGTH, sizeof( uint32_t ) );
+		configASSERT( xQueues[ x ] );
+		if( xQueueAddToSet( xQueues[ x ], xQueueSet ) != pdPASS )
+		{
+			xQueueSetTasksStatus = pdFAIL;
+		}
+		else
+		{
+			/* The queue has now been added to the queue set and cannot be added to
+			another. */
+			if( xQueueAddToSet( xQueues[ x ], xQueueSet ) != pdFAIL )
+			{
+				xQueueSetTasksStatus = pdFAIL;
+			}
+		}
+	}
+
+	/* Attempt to remove a queue from a queue set it does not belong
+	to (NULL being passed as the queue set in this case). */
+	if( xQueueRemoveFromSet( xQueues[ 0 ], NULL ) != pdFAIL )
+	{
+		/* It is not possible to successfully remove a queue from a queue
+		set it does not belong to. */
+		xQueueSetTasksStatus = pdFAIL;
+	}
+
+	/* Attempt to remove a queue from the queue set it does belong to. */
+	if( xQueueRemoveFromSet( xQueues[ 0 ], xQueueSet ) != pdPASS )
+	{
+		/* It should be possible to remove the queue from the queue set it
+		does belong to. */
+		xQueueSetTasksStatus = pdFAIL;
+	}
+
+	/* Add an item to the queue before attempting to add it back into the
+	set. */
+	xQueueSend( xQueues[ 0 ], ( void * ) &ulValueToSend, 0 );
+	if( xQueueAddToSet( xQueues[ 0 ], xQueueSet ) != pdFAIL )
+	{
+		/* Should not be able to add a non-empty queue to a set. */
+		xQueueSetTasksStatus = pdFAIL;
+	}
+
+	/* Remove the item from the queue before adding the queue back into the
+	set so the dynamic tests can begin. */
+	xQueueReceive( xQueues[ 0 ], &ulValueToSend, 0 );
+	if( xQueueAddToSet( xQueues[ 0 ], xQueueSet ) != pdPASS )
+	{
+		/* If the queue was successfully removed from the queue set then it
+		should be possible to add it back in again. */
+		xQueueSetTasksStatus = pdFAIL;
+	}
+
+	/* The task that sends to the queues is not running yet, so attempting to
+	read from the queue set should fail. */
+	if( xQueueSelectFromSet( xQueueSet, queuesetSHORT_DELAY ) != NULL )
+	{
+		xQueueSetTasksStatus = pdFAIL;
+	}
+
+	/* Testing the behaviour of queue sets when a queue overwrite operation is
+	performed on a set member requires a special test as overwrites can only
+	be performed on queues that have a length of 1. */
+	prvTestQueueOverwriteWithQueueSet();
+
+	/* Resume the task that writes to the queues. */
+	vTaskResume( xQueueSetSendingTask );
+
+	/* Let the ISR access the queues also. */
+	xSetupComplete = pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvRand( void )
+{
+	uxNextRand = ( uxNextRand * ( size_t ) 1103515245 ) + ( size_t ) 12345;
+	return ( uxNextRand / ( size_t ) 65536 ) % ( size_t ) 32768;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSRand( size_t uxSeed )
+{
+	uxNextRand = uxSeed;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/QueueSetPolling.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/QueueSetPolling.c
new file mode 100644
index 0000000..7815d73
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/QueueSetPolling.c
@@ -0,0 +1,179 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Tests the use of queue sets.
+ *
+ * A receive task creates a number of queues and adds them to a queue set before
+ * blocking on the queue set receive.  A transmit task and (optionally) an
+ * interrupt repeatedly unblocks the receive task by sending messages to the
+ * queues in a pseudo random order.  The receive task removes the messages from
+ * the queues and flags an error if the received message does not match that
+ * expected.  The task sends values in the range 0 to
+ * queuesetINITIAL_ISR_TX_VALUE, and the ISR sends value in the range
+ * queuesetINITIAL_ISR_TX_VALUE to ULONG_MAX.
+ */
+
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* Demo includes. */
+#include "QueueSetPolling.h"
+
+/* The length of each created queue. */
+#define setpollQUEUE_LENGTH	10
+
+/* Block times used in this demo.  A block time or 0 means "don't block". */
+#define setpollDONT_BLOCK 0
+
+/* The ISR sends to the queue every setpollISR_TX_PERIOD ticks. */
+#define queuesetISR_TX_PERIOD	( 50UL )
+
+/*
+ * The task that reads from the queue set.
+ */
+static void prvQueueSetReceivingTask( void *pvParameters );
+
+/*-----------------------------------------------------------*/
+
+/* The queue that is added to the set. */
+static QueueHandle_t xQueue = NULL;
+
+/* The handle of the queue set to which the queue is added. */
+static QueueSetHandle_t xQueueSet = NULL;
+
+/* Set to pdFAIL if an error is detected by any queue set task.
+ulCycleCounter will only be incremented if xQueueSetTasksSatus equals pdPASS. */
+static volatile BaseType_t xQueueSetPollStatus = pdPASS;
+
+/* Counter used to ensure the task is still running. */
+static uint32_t ulCycleCounter = 0;
+
+/*-----------------------------------------------------------*/
+
+void vStartQueueSetPollingTask( void )
+{
+	/* Create the queue that is added to the set, the set, and add the queue to
+	the set. */
+	xQueue = xQueueCreate( setpollQUEUE_LENGTH, sizeof( uint32_t ) );
+	xQueueSet = xQueueCreateSet( setpollQUEUE_LENGTH );
+
+	if( ( xQueue != NULL ) && ( xQueueSet != NULL ) )
+	{
+		xQueueAddToSet( xQueue, xQueueSet );
+
+		/* Create the task. */
+		xTaskCreate( prvQueueSetReceivingTask, "SetPoll", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueSetReceivingTask( void *pvParameters )
+{
+uint32_t ulReceived, ulExpected = 0;
+QueueHandle_t xActivatedQueue;
+
+	/* Remove compiler warnings. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		/* Is a message waiting?  A block time is not used to ensure the queue
+		set is polled while it is being written to from an interrupt. */
+		xActivatedQueue = xQueueSelectFromSet( xQueueSet, setpollDONT_BLOCK );
+
+		if( xActivatedQueue != NULL )
+		{
+			/* Reading from the queue should pass with a zero block time as
+			this task will only run when something has been posted to a task
+			in the queue set. */
+			if( xQueueReceive( xActivatedQueue, &ulReceived, setpollDONT_BLOCK ) != pdPASS )
+			{
+				xQueueSetPollStatus = pdFAIL;
+			}
+
+			if( ulReceived == ulExpected )
+			{
+				ulExpected++;
+			}
+			else
+			{
+				xQueueSetPollStatus = pdFAIL;
+			}
+
+			if( xQueueSetPollStatus == pdPASS )
+			{
+				ulCycleCounter++;
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vQueueSetPollingInterruptAccess( void )
+{
+static uint32_t ulCallCount = 0, ulValueToSend = 0;
+
+	/* It is intended that this function is called from the tick hook
+	function, so each call is one tick period apart. */
+	ulCallCount++;
+	if( ulCallCount > queuesetISR_TX_PERIOD )
+	{
+		ulCallCount = 0;
+
+		if( xQueueSendFromISR( xQueue, ( void * ) &ulValueToSend, NULL ) == pdPASS )
+		{
+			/* Send the next value next time. */
+			ulValueToSend++;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xAreQueueSetPollTasksStillRunning( void )
+{
+static uint32_t ulLastCycleCounter = 0;
+
+	if( ulLastCycleCounter == ulCycleCounter )
+	{
+		xQueueSetPollStatus = pdFAIL;
+	}
+
+	ulLastCycleCounter = ulCycleCounter;
+
+	return xQueueSetPollStatus;
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/StaticAllocation.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/StaticAllocation.c
new file mode 100644
index 0000000..32e6777
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/StaticAllocation.c
@@ -0,0 +1,1107 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*
+ * Demonstrates how to create FreeRTOS objects using pre-allocated memory,
+ * rather than the normal dynamically allocated memory, and tests objects being
+ * created and deleted with both statically allocated memory and dynamically
+ * allocated memory.
+ *
+ * See http://www.FreeRTOS.org/Static_Vs_Dynamic_Memory_Allocation.html
+ */
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+#include "event_groups.h"
+#include "timers.h"
+
+/* Demo program include files. */
+#include "StaticAllocation.h"
+
+/* Exclude the entire file if configSUPPORT_STATIC_ALLOCATION is 0. */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+/* The priority at which the task that performs the tests is created. */
+#define staticTASK_PRIORITY					( tskIDLE_PRIORITY + 2 )
+
+/* The length of the queue, in items, not bytes, used in the queue static
+allocation tests. */
+#define staticQUEUE_LENGTH_IN_ITEMS			( 5 )
+
+/* A block time of 0 simply means "don't block". */
+#define staticDONT_BLOCK					( ( TickType_t ) 0 )
+
+/* Binary semaphores have a maximum count of 1. */
+#define staticBINARY_SEMAPHORE_MAX_COUNT	( 1 )
+
+/* The size of the stack used by the task that runs the tests. */
+#define staticCREATOR_TASK_STACK_SIZE		( configMINIMAL_STACK_SIZE * 2 )
+
+/* The number of times the software timer will execute before stopping itself. */
+#define staticMAX_TIMER_CALLBACK_EXECUTIONS	( 5 )
+
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The task that repeatedly creates and deletes statically allocated tasks, and
+ * other RTOS objects.
+ */
+static void prvStaticallyAllocatedCreator( void *pvParameters );
+
+/*
+ * The callback function used by the software timer that is repeatedly created
+ * and deleted using both static and dynamically allocated memory.
+ */
+static void prvTimerCallback( TimerHandle_t xExpiredTimer );
+
+/*
+ * A task that is created and deleted multiple times, using both statically and
+ * dynamically allocated stack and TCB.
+ */
+static void prvStaticallyAllocatedTask( void *pvParameters );
+
+/*
+ * A function that demonstrates and tests the API functions that create and
+ * delete tasks using both statically and dynamically allocated TCBs and stacks.
+ */
+static void prvCreateAndDeleteStaticallyAllocatedTasks( void );
+
+/*
+ * A function that demonstrates and tests the API functions that create and
+ * delete event groups using both statically and dynamically allocated RAM.
+ */
+static void prvCreateAndDeleteStaticallyAllocatedEventGroups( void );
+
+/*
+ * A function that demonstrates and tests the API functions that create and
+ * delete queues using both statically and dynamically allocated RAM.
+ */
+static void prvCreateAndDeleteStaticallyAllocatedQueues( void );
+
+/*
+ * A function that demonstrates and tests the API functions that create and
+ * delete binary semaphores using both statically and dynamically allocated RAM.
+ */
+static void prvCreateAndDeleteStaticallyAllocatedBinarySemaphores( void );
+
+/*
+ * A function that demonstrates and tests the API functions that create and
+ * delete software timers using both statically and dynamically allocated RAM.
+ */
+static void prvCreateAndDeleteStaticallyAllocatedTimers( void );
+
+/*
+ * A function that demonstrates and tests the API functions that create and
+ * delete mutexes using both statically and dynamically allocated RAM.
+ */
+static void prvCreateAndDeleteStaticallyAllocatedMutexes( void );
+
+/*
+ * A function that demonstrates and tests the API functions that create and
+ * delete counting semaphores using both statically and dynamically allocated
+ * RAM.
+ */
+static void prvCreateAndDeleteStaticallyAllocatedCountingSemaphores( void );
+
+/*
+ * A function that demonstrates and tests the API functions that create and
+ * delete recursive mutexes using both statically and dynamically allocated RAM.
+ */
+static void prvCreateAndDeleteStaticallyAllocatedRecursiveMutexes( void );
+
+/*
+ * Utility function to create pseudo random numbers.
+ */
+static UBaseType_t prvRand( void );
+
+/*
+ * The task that creates and deletes other tasks has to delay occasionally to
+ * ensure lower priority tasks are not starved of processing time.  A pseudo
+ * random delay time is used just to add a little bit of randomisation into the
+ * execution pattern.  prvGetNextDelayTime() generates the pseudo random delay.
+ */
+static TickType_t prvGetNextDelayTime( void );
+
+/*
+ * Checks the basic operation of a queue after it has been created.
+ */
+static void prvSanityCheckCreatedQueue( QueueHandle_t xQueue );
+
+/*
+ * Checks the basic operation of a recursive mutex after it has been created.
+ */
+static void prvSanityCheckCreatedRecursiveMutex( SemaphoreHandle_t xSemaphore );
+
+/*
+ * Checks the basic operation of a binary semaphore after it has been created.
+ */
+static void prvSanityCheckCreatedSemaphore( SemaphoreHandle_t xSemaphore, UBaseType_t uxMaxCount );
+
+/*
+ * Checks the basic operation of an event group after it has been created.
+ */
+static void prvSanityCheckCreatedEventGroup( EventGroupHandle_t xEventGroup );
+
+/*-----------------------------------------------------------*/
+
+/* StaticTask_t is a publicly accessible structure that has the same size and
+alignment requirements as the real TCB structure.  It is provided as a mechanism
+for applications to know the size of the TCB (which is dependent on the
+architecture and configuration file settings) without breaking the strict data
+hiding policy by exposing the real TCB.  This StaticTask_t variable is passed
+into the xTaskCreateStatic() function that creates the
+prvStaticallyAllocatedCreator() task, and will hold the TCB of the created
+tasks. */
+static StaticTask_t xCreatorTaskTCBBuffer;
+
+/* This is the stack that will be used by the prvStaticallyAllocatedCreator()
+task, which is itself created using statically allocated buffers (so without any
+dynamic memory allocation). */
+static StackType_t uxCreatorTaskStackBuffer[ staticCREATOR_TASK_STACK_SIZE ];
+
+/* Used by the pseudo random number generating function. */
+static uint32_t ulNextRand = 0;
+
+/* Used so a check task can ensure this test is still executing, and not
+stalled. */
+static volatile UBaseType_t uxCycleCounter = 0;
+
+/* A variable that gets set to pdTRUE if an error is detected. */
+static volatile BaseType_t xErrorOccurred = pdFALSE;
+
+/*-----------------------------------------------------------*/
+
+void vStartStaticallyAllocatedTasks( void  )
+{
+	/* Create a single task, which then repeatedly creates and deletes the other
+	RTOS objects using both statically and dynamically allocated RAM. */
+	xTaskCreateStatic( prvStaticallyAllocatedCreator,		/* The function that implements the task being created. */
+					   "StatCreate",						/* Text name for the task - not used by the RTOS, its just to assist debugging. */
+					   staticCREATOR_TASK_STACK_SIZE,		/* Size of the buffer passed in as the stack - in words, not bytes! */
+					   NULL,								/* Parameter passed into the task - not used in this case. */
+					   staticTASK_PRIORITY,					/* Priority of the task. */
+					   &( uxCreatorTaskStackBuffer[ 0 ] ),  /* The buffer to use as the task's stack. */
+					   &xCreatorTaskTCBBuffer );			/* The variable that will hold the task's TCB. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvStaticallyAllocatedCreator( void *pvParameters )
+{
+	/* Avoid compiler warnings. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		/* Loop, running functions that create and delete the various RTOS
+		objects that can be optionally created using either static or dynamic
+		memory allocation. */
+		prvCreateAndDeleteStaticallyAllocatedTasks();
+		prvCreateAndDeleteStaticallyAllocatedQueues();
+
+		/* Delay to ensure lower priority tasks get CPU time, and increment the
+		cycle counter so a 'check' task can determine that this task is still
+		executing. */
+		vTaskDelay( prvGetNextDelayTime() );
+		uxCycleCounter++;
+
+		prvCreateAndDeleteStaticallyAllocatedBinarySemaphores();
+		prvCreateAndDeleteStaticallyAllocatedCountingSemaphores();
+
+		vTaskDelay( prvGetNextDelayTime() );
+		uxCycleCounter++;
+
+		prvCreateAndDeleteStaticallyAllocatedMutexes();
+		prvCreateAndDeleteStaticallyAllocatedRecursiveMutexes();
+
+		vTaskDelay( prvGetNextDelayTime() );
+		uxCycleCounter++;
+
+		prvCreateAndDeleteStaticallyAllocatedEventGroups();
+		prvCreateAndDeleteStaticallyAllocatedTimers();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvCreateAndDeleteStaticallyAllocatedCountingSemaphores( void )
+{
+SemaphoreHandle_t xSemaphore;
+const UBaseType_t uxMaxCount = ( UBaseType_t ) 10;
+
+/* StaticSemaphore_t is a publicly accessible structure that has the same size
+and alignment requirements as the real semaphore structure.  It is provided as a
+mechanism for applications to know the size of the semaphore (which is dependent
+on the architecture and configuration file settings) without breaking the strict
+data hiding policy by exposing the real semaphore internals.  This
+StaticSemaphore_t variable is passed into the xSemaphoreCreateCountingStatic()
+function calls within this function.  NOTE: In most usage scenarios now it is
+faster and more memory efficient to use a direct to task notification instead of
+a counting semaphore.  http://www.freertos.org/RTOS-task-notifications.html */
+StaticSemaphore_t xSemaphoreBuffer;
+
+	/* Create the semaphore.  xSemaphoreCreateCountingStatic() has one more
+	parameter than the usual xSemaphoreCreateCounting() function.  The parameter
+	is a pointer to the pre-allocated StaticSemaphore_t structure, which will
+	hold information on the semaphore in an anonymous way.  If the pointer is
+	passed as NULL then the structure will be allocated dynamically, just as
+	when xSemaphoreCreateCounting() is called. */
+	xSemaphore = xSemaphoreCreateCountingStatic( uxMaxCount, 0, &xSemaphoreBuffer );
+
+	/* The semaphore handle should equal the static semaphore structure passed
+	into the xSemaphoreCreateBinaryStatic() function. */
+	configASSERT( xSemaphore == ( SemaphoreHandle_t ) &xSemaphoreBuffer );
+
+	/* Ensure the semaphore passes a few sanity checks as a valid semaphore. */
+	prvSanityCheckCreatedSemaphore( xSemaphore, uxMaxCount );
+
+	/* Delete the semaphore again so the buffers can be reused. */
+	vSemaphoreDelete( xSemaphore );
+
+	#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	{
+		/* Now do the same but using dynamically allocated buffers to ensure the
+		delete functions are working correctly in both the static and dynamic
+		allocation cases. */
+		xSemaphore = xSemaphoreCreateCounting( uxMaxCount, 0 );
+		configASSERT( xSemaphore != NULL );
+		prvSanityCheckCreatedSemaphore( xSemaphore, uxMaxCount );
+		vSemaphoreDelete( xSemaphore );
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+static void prvCreateAndDeleteStaticallyAllocatedRecursiveMutexes( void )
+{
+SemaphoreHandle_t xSemaphore;
+
+/* StaticSemaphore_t is a publicly accessible structure that has the same size
+and alignment requirements as the real semaphore structure.  It is provided as a
+mechanism for applications to know the size of the semaphore (which is dependent
+on the architecture and configuration file settings) without breaking the strict
+data hiding policy by exposing the real semaphore internals.  This
+StaticSemaphore_t variable is passed into the
+xSemaphoreCreateRecursiveMutexStatic() function calls within this function. */
+StaticSemaphore_t xSemaphoreBuffer;
+
+	/* Create the semaphore.  xSemaphoreCreateRecursiveMutexStatic() has one
+	more parameter than the usual xSemaphoreCreateRecursiveMutex() function.
+	The parameter is a pointer to the pre-allocated StaticSemaphore_t structure,
+	which will hold information on the semaphore in an anonymous way.  If the
+	pointer is passed as NULL then the structure will be allocated dynamically,
+	just as	when xSemaphoreCreateRecursiveMutex() is called. */
+	xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xSemaphoreBuffer );
+
+	/* The semaphore handle should equal the static semaphore structure passed
+	into the xSemaphoreCreateBinaryStatic() function. */
+	configASSERT( xSemaphore == ( SemaphoreHandle_t ) &xSemaphoreBuffer );
+
+	/* Ensure the semaphore passes a few sanity checks as a valid
+	recursive semaphore. */
+	prvSanityCheckCreatedRecursiveMutex( xSemaphore );
+
+	/* Delete the semaphore again so the buffers can be reused. */
+	vSemaphoreDelete( xSemaphore );
+
+	/* Now do the same using dynamically allocated buffers to ensure the delete
+	functions are working correctly in both the static and dynamic memory
+	allocation cases. */
+	#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	{
+		xSemaphore = xSemaphoreCreateRecursiveMutex();
+		configASSERT( xSemaphore != NULL );
+		prvSanityCheckCreatedRecursiveMutex( xSemaphore );
+		vSemaphoreDelete( xSemaphore );
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+static void prvCreateAndDeleteStaticallyAllocatedQueues( void )
+{
+QueueHandle_t xQueue;
+
+/* StaticQueue_t is a publicly accessible structure that has the same size and
+alignment requirements as the real queue structure.  It is provided as a
+mechanism for applications to know the size of the queue (which is dependent on
+the architecture and configuration file settings) without breaking the strict
+data hiding policy by exposing the real queue internals.  This StaticQueue_t
+variable is passed into the xQueueCreateStatic() function calls within this
+function. */
+static StaticQueue_t xStaticQueue;
+
+/* The queue storage area must be large enough to hold the maximum number of
+items it is possible for the queue to hold at any one time, which equals the
+queue length (in items, not bytes) multiplied by the size of each item.  In this
+case the queue will hold staticQUEUE_LENGTH_IN_ITEMS 64-bit items.  See
+http://www.freertos.org/Embedded-RTOS-Queues.html */
+static uint8_t ucQueueStorageArea[ staticQUEUE_LENGTH_IN_ITEMS * sizeof( uint64_t ) ];
+
+	/* Create the queue.  xQueueCreateStatic() has two more parameters than the
+	usual xQueueCreate() function.  The first new parameter is a pointer to the
+	pre-allocated queue storage area.  The second new parameter is a pointer to
+	the StaticQueue_t structure that will hold the queue state information in
+	an anonymous way.  If the two pointers are passed as NULL then the data
+	will be allocated dynamically as if xQueueCreate() had been called. */
+	xQueue = xQueueCreateStatic( staticQUEUE_LENGTH_IN_ITEMS, /* The maximum number of items the queue can hold. */
+								 sizeof( uint64_t ), /* The size of each item. */
+								 ucQueueStorageArea, /* The buffer used to hold items within the queue. */
+								 &xStaticQueue );	 /* The static queue structure that will hold the state of the queue. */
+
+	/* The queue handle should equal the static queue structure passed into the
+	xQueueCreateStatic() function. */
+	configASSERT( xQueue == ( QueueHandle_t ) &xStaticQueue );
+
+	/* Ensure the queue passes a few sanity checks as a valid queue. */
+	prvSanityCheckCreatedQueue( xQueue );
+
+	/* Delete the queue again so the buffers can be reused. */
+	vQueueDelete( xQueue );
+
+	/* Now do the same using a dynamically allocated queue to ensure the delete
+	function is working correctly in both the static and dynamic memory
+	allocation cases. */
+	#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	{
+		xQueue = xQueueCreate( staticQUEUE_LENGTH_IN_ITEMS, /* The maximum number of items the queue can hold. */
+							   sizeof( uint64_t ) ); 		/* The size of each item. */
+
+		/* The queue handle should equal the static queue structure passed into the
+		xQueueCreateStatic() function. */
+		configASSERT( xQueue != NULL );
+
+		/* Ensure the queue passes a few sanity checks as a valid queue. */
+		prvSanityCheckCreatedQueue( xQueue );
+
+		/* Delete the queue again so the buffers can be reused. */
+		vQueueDelete( xQueue );
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+static void prvCreateAndDeleteStaticallyAllocatedMutexes( void )
+{
+SemaphoreHandle_t xSemaphore;
+BaseType_t xReturned;
+
+/* StaticSemaphore_t is a publicly accessible structure that has the same size
+and alignment requirements as the real semaphore structure.  It is provided as a
+mechanism for applications to know the size of the semaphore (which is dependent
+on the architecture and configuration file settings) without breaking the strict
+data hiding policy by exposing the real semaphore internals.  This
+StaticSemaphore_t variable is passed into the xSemaphoreCreateMutexStatic()
+function calls within this function. */
+StaticSemaphore_t xSemaphoreBuffer;
+
+	/* Create the semaphore.  xSemaphoreCreateMutexStatic() has one more
+	parameter than the usual xSemaphoreCreateMutex() function.  The parameter
+	is a pointer to the pre-allocated StaticSemaphore_t structure, which will
+	hold information on the semaphore in an anonymous way.  If the pointer is
+	passed as NULL then the structure will be allocated dynamically, just as
+	when xSemaphoreCreateMutex() is called. */
+	xSemaphore = xSemaphoreCreateMutexStatic( &xSemaphoreBuffer );
+
+	/* The semaphore handle should equal the static semaphore structure passed
+	into the xSemaphoreCreateMutexStatic() function. */
+	configASSERT( xSemaphore == ( SemaphoreHandle_t ) &xSemaphoreBuffer );
+
+	/* Take the mutex so the mutex is in the state expected by the
+	prvSanityCheckCreatedSemaphore() function. */
+	xReturned = xSemaphoreTake( xSemaphore, staticDONT_BLOCK );
+
+	if( xReturned != pdPASS )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+
+	/* Ensure the semaphore passes a few sanity checks as a valid semaphore. */
+	prvSanityCheckCreatedSemaphore( xSemaphore, staticBINARY_SEMAPHORE_MAX_COUNT );
+
+	/* Delete the semaphore again so the buffers can be reused. */
+	vSemaphoreDelete( xSemaphore );
+
+	/* Now do the same using a dynamically allocated mutex to ensure the delete
+	function is working correctly in both the static and dynamic allocation
+	cases. */
+	#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	{
+		xSemaphore = xSemaphoreCreateMutex();
+
+		/* The semaphore handle should equal the static semaphore structure
+		passed into the xSemaphoreCreateMutexStatic() function. */
+		configASSERT( xSemaphore != NULL );
+
+		/* Take the mutex so the mutex is in the state expected by the
+		prvSanityCheckCreatedSemaphore() function. */
+		xReturned = xSemaphoreTake( xSemaphore, staticDONT_BLOCK );
+
+		if( xReturned != pdPASS )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+
+		/* Ensure the semaphore passes a few sanity checks as a valid semaphore. */
+		prvSanityCheckCreatedSemaphore( xSemaphore, staticBINARY_SEMAPHORE_MAX_COUNT );
+
+		/* Delete the semaphore again so the buffers can be reused. */
+		vSemaphoreDelete( xSemaphore );
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+static void prvCreateAndDeleteStaticallyAllocatedBinarySemaphores( void )
+{
+SemaphoreHandle_t xSemaphore;
+
+/* StaticSemaphore_t is a publicly accessible structure that has the same size
+and alignment requirements as the real semaphore structure.  It is provided as a
+mechanism for applications to know the size of the semaphore (which is dependent
+on the architecture and configuration file settings) without breaking the strict
+data hiding policy by exposing the real semaphore internals.  This
+StaticSemaphore_t variable is passed into the xSemaphoreCreateBinaryStatic()
+function calls within this function.  NOTE: In most usage scenarios now it is
+faster and more memory efficient to use a direct to task notification instead of
+a binary semaphore.  http://www.freertos.org/RTOS-task-notifications.html */
+StaticSemaphore_t xSemaphoreBuffer;
+
+	/* Create the semaphore.  xSemaphoreCreateBinaryStatic() has one more
+	parameter than the usual xSemaphoreCreateBinary() function.  The parameter
+	is a pointer to the pre-allocated StaticSemaphore_t structure, which will
+	hold information on the semaphore in an anonymous way.  If the pointer is
+	passed as NULL then the structure will be allocated dynamically, just as
+	when xSemaphoreCreateBinary() is called. */
+	xSemaphore = xSemaphoreCreateBinaryStatic( &xSemaphoreBuffer );
+
+	/* The semaphore handle should equal the static semaphore structure passed
+	into the xSemaphoreCreateBinaryStatic() function. */
+	configASSERT( xSemaphore == ( SemaphoreHandle_t ) &xSemaphoreBuffer );
+
+	/* Ensure the semaphore passes a few sanity checks as a valid semaphore. */
+	prvSanityCheckCreatedSemaphore( xSemaphore, staticBINARY_SEMAPHORE_MAX_COUNT );
+
+	/* Delete the semaphore again so the buffers can be reused. */
+	vSemaphoreDelete( xSemaphore );
+
+	/* Now do the same using a dynamically allocated semaphore to check the
+	delete function is working correctly in both the static and dynamic
+	allocation cases. */
+	#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	{
+		xSemaphore = xSemaphoreCreateBinary();
+		configASSERT( xSemaphore != NULL );
+		prvSanityCheckCreatedSemaphore( xSemaphore, staticBINARY_SEMAPHORE_MAX_COUNT );
+		vSemaphoreDelete( xSemaphore );
+	}
+	#endif
+
+	/* There isn't a static version of the old and deprecated
+	vSemaphoreCreateBinary() macro (because its deprecated!), but check it is
+	still functioning correctly. */
+	#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	{
+		vSemaphoreCreateBinary( xSemaphore );
+
+		/* The macro starts with the binary semaphore available, but the test
+		function expects it to be unavailable. */
+		if( xSemaphoreTake( xSemaphore, staticDONT_BLOCK ) == pdFAIL )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+
+		prvSanityCheckCreatedSemaphore( xSemaphore, staticBINARY_SEMAPHORE_MAX_COUNT );
+		vSemaphoreDelete( xSemaphore );
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+static void prvTimerCallback( TimerHandle_t xExpiredTimer )
+{
+UBaseType_t *puxVariableToIncrement;
+BaseType_t xReturned;
+
+	/* The timer callback just demonstrates it is executing by incrementing a
+	variable - the address of which is passed into the timer as its ID.  Obtain
+	the address of the variable to increment. */
+	puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );
+
+	/* Increment the variable to show the timer callback has executed. */
+	( *puxVariableToIncrement )++;
+
+	/* If this callback has executed the required number of times, stop the
+	timer. */
+	if( *puxVariableToIncrement == staticMAX_TIMER_CALLBACK_EXECUTIONS )
+	{
+		/* This is called from a timer callback so must not block.  See
+		http://www.FreeRTOS.org/FreeRTOS-timers-xTimerStop.html */
+		xReturned = xTimerStop( xExpiredTimer, staticDONT_BLOCK );
+
+		if( xReturned != pdPASS )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvCreateAndDeleteStaticallyAllocatedTimers( void )
+{
+TimerHandle_t xTimer;
+UBaseType_t uxVariableToIncrement;
+const TickType_t xTimerPeriod = pdMS_TO_TICKS( 20 );
+BaseType_t xReturned;
+
+/* StaticTimer_t is a publicly accessible structure that has the same size
+and alignment requirements as the real timer structure.  It is provided as a
+mechanism for applications to know the size of the timer structure (which is
+dependent on the architecture and configuration file settings) without breaking
+the strict data hiding policy by exposing the real timer internals.  This
+StaticTimer_t variable is passed into the xTimerCreateStatic() function calls
+within this function. */
+StaticTimer_t xTimerBuffer;
+
+	/* Create the software time.  xTimerCreateStatic() has an extra parameter
+	than the normal xTimerCreate() API function.  The parameter is a pointer to
+	the StaticTimer_t structure that will hold the software timer structure.  If
+	the parameter is passed as NULL then the structure will be allocated
+	dynamically, just as if xTimerCreate() had been called. */
+	xTimer = xTimerCreateStatic( "T1",					/* Text name for the task.  Helps debugging only.  Not used by FreeRTOS. */
+								 xTimerPeriod,			/* The period of the timer in ticks. */
+								 pdTRUE,				/* This is an auto-reload timer. */
+								 ( void * ) &uxVariableToIncrement,	/* The variable incremented by the test is passed into the timer callback using the timer ID. */
+								 prvTimerCallback,		/* The function to execute when the timer expires. */
+								 &xTimerBuffer );		/* The buffer that will hold the software timer structure. */
+
+	/* The timer handle should equal the static timer structure passed into the
+	xTimerCreateStatic() function. */
+	configASSERT( xTimer == ( TimerHandle_t ) &xTimerBuffer );
+
+	/* Set the variable to 0, wait for a few timer periods to expire, then check
+	the timer callback has incremented the variable to the expected value. */
+	uxVariableToIncrement = 0;
+
+	/* This is a low priority so a block time should not be needed. */
+	xReturned = xTimerStart( xTimer, staticDONT_BLOCK );
+
+	if( xReturned != pdPASS )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+
+	vTaskDelay( xTimerPeriod * staticMAX_TIMER_CALLBACK_EXECUTIONS );
+
+	/* By now the timer should have expired staticMAX_TIMER_CALLBACK_EXECUTIONS
+	times, and then stopped itself. */
+	if( uxVariableToIncrement != staticMAX_TIMER_CALLBACK_EXECUTIONS )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+
+	/* Finished with the timer, delete it. */
+	xReturned = xTimerDelete( xTimer, staticDONT_BLOCK );
+
+	/* Again, as this is a low priority task it is expected that the timer
+	command will have been sent even without a block time being used. */
+	if( xReturned != pdPASS )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+
+	/* Just to show the check task that this task is still executing. */
+	uxCycleCounter++;
+
+	/* Now do the same using a dynamically allocated software timer to ensure
+	the delete function is working correctly in both the static and dynamic
+	allocation cases. */
+	#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	{
+		xTimer = xTimerCreate( "T1",								/* Text name for the task.  Helps debugging only.  Not used by FreeRTOS. */
+							    xTimerPeriod,						/* The period of the timer in ticks. */
+								pdTRUE,								/* This is an auto-reload timer. */
+								( void * ) &uxVariableToIncrement,	/* The variable incremented by the test is passed into the timer callback using the timer ID. */
+								prvTimerCallback );					/* The function to execute when the timer expires. */
+
+		configASSERT( xTimer != NULL );
+
+		uxVariableToIncrement = 0;
+		xReturned = xTimerStart( xTimer, staticDONT_BLOCK );
+
+		if( xReturned != pdPASS )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+
+		vTaskDelay( xTimerPeriod * staticMAX_TIMER_CALLBACK_EXECUTIONS );
+
+		if( uxVariableToIncrement != staticMAX_TIMER_CALLBACK_EXECUTIONS )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+
+		xReturned = xTimerDelete( xTimer, staticDONT_BLOCK );
+
+		if( xReturned != pdPASS )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+static void prvCreateAndDeleteStaticallyAllocatedEventGroups( void )
+{
+EventGroupHandle_t xEventGroup;
+
+/* StaticEventGroup_t is a publicly accessible structure that has the same size
+and alignment requirements as the real event group structure.  It is provided as
+a mechanism for applications to know the size of the event group (which is
+dependent on the architecture and configuration file settings) without breaking
+the strict data hiding policy by exposing the real event group internals.  This
+StaticEventGroup_t variable is passed into the xSemaphoreCreateEventGroupStatic()
+function calls within this function. */
+StaticEventGroup_t xEventGroupBuffer;
+
+	/* Create the event group.  xEventGroupCreateStatic() has an extra parameter
+	than the normal xEventGroupCreate() API function.  The parameter is a
+	pointer to the StaticEventGroup_t structure that will hold the event group
+	structure. */
+	xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
+
+	/* The event group handle should equal the static event group structure
+	passed into the xEventGroupCreateStatic() function. */
+	configASSERT( xEventGroup == ( EventGroupHandle_t ) &xEventGroupBuffer );
+
+	/* Ensure the event group passes a few sanity checks as a valid event
+	group. */
+	prvSanityCheckCreatedEventGroup( xEventGroup );
+
+	/* Delete the event group again so the buffers can be reused. */
+	vEventGroupDelete( xEventGroup );
+
+	/* Now do the same using a dynamically allocated event group to ensure the
+	delete function is working correctly in both the static and dynamic
+	allocation cases. */
+	#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	{
+		xEventGroup = xEventGroupCreate();
+		configASSERT( xEventGroup != NULL );
+		prvSanityCheckCreatedEventGroup( xEventGroup );
+		vEventGroupDelete( xEventGroup );
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+static void prvCreateAndDeleteStaticallyAllocatedTasks( void )
+{
+TaskHandle_t xCreatedTask;
+
+/* The variable that will hold the TCB of tasks created by this function.  See
+the comments above the declaration of the xCreatorTaskTCBBuffer variable for
+more information.  NOTE:  This is not static so relies on the tasks that use it
+being deleted before this function returns and deallocates its stack.  That will
+only be the case if configUSE_PREEMPTION is set to 1. */
+StaticTask_t xTCBBuffer;
+
+/* This buffer that will be used as the stack of tasks created by this function.
+See the comments above the declaration of the uxCreatorTaskStackBuffer[] array
+above for more information. */
+static StackType_t uxStackBuffer[ configMINIMAL_STACK_SIZE ];
+
+	/* Create the task.  xTaskCreateStatic() has two more parameters than
+	the usual xTaskCreate() function.  The first new parameter is a pointer to
+	the pre-allocated stack.  The second new parameter is a pointer to the
+	StaticTask_t structure that will hold the task's TCB.  If both pointers are
+	passed as NULL then the respective object will be allocated dynamically as
+	if xTaskCreate() had been called. */
+	xCreatedTask = xTaskCreateStatic(
+						prvStaticallyAllocatedTask, 	/* Function that implements the task. */
+						"Static",						/* Human readable name for the task. */
+						configMINIMAL_STACK_SIZE,		/* Task's stack size, in words (not bytes!). */
+						NULL,							/* Parameter to pass into the task. */
+						uxTaskPriorityGet( NULL ) + 1,	/* The priority of the task. */
+						&( uxStackBuffer[ 0 ] ),		/* The buffer to use as the task's stack. */
+						&xTCBBuffer );					/* The variable that will hold that task's TCB. */
+
+	/* Check the task was created correctly, then delete the task. */
+	if( xCreatedTask == NULL )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+	else if( eTaskGetState( xCreatedTask ) != eSuspended )
+	{
+		/* The created task had a higher priority so should have executed and
+		suspended itself by now. */
+		xErrorOccurred = pdTRUE;
+	}
+	else
+	{
+		vTaskDelete( xCreatedTask );
+	}
+
+	/* Now do the same using a dynamically allocated task to ensure the delete
+	function is working correctly in both the static and dynamic allocation
+	cases. */
+	#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	{
+	BaseType_t xReturned;
+
+		xReturned = xTaskCreate(
+									prvStaticallyAllocatedTask,		/* Function that implements the task - the same function is used but is actually dynamically allocated this time. */
+									"Static",						/* Human readable name for the task. */
+									configMINIMAL_STACK_SIZE,		/* Task's stack size, in words (not bytes!). */
+									NULL,							/* Parameter to pass into the task. */
+									uxTaskPriorityGet( NULL ) + 1,	/* The priority of the task. */
+									&xCreatedTask );				/* Handle of the task being created. */
+
+		if( eTaskGetState( xCreatedTask ) != eSuspended )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+
+		configASSERT( xReturned == pdPASS );
+		if( xReturned != pdPASS )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+		vTaskDelete( xCreatedTask );
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+static void prvStaticallyAllocatedTask( void *pvParameters )
+{
+	( void ) pvParameters;
+
+	/* The created task just suspends itself to wait to get deleted.  The task
+	that creates this task checks this task is in the expected Suspended state
+	before deleting it. */
+	vTaskSuspend( NULL );
+}
+/*-----------------------------------------------------------*/
+
+static UBaseType_t prvRand( void )
+{
+const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL;
+
+	/* Utility function to generate a pseudo random number. */
+	ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement;
+	return( ( ulNextRand >> 16UL ) & 0x7fffUL );
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvGetNextDelayTime( void )
+{
+TickType_t xNextDelay;
+const TickType_t xMaxDelay = pdMS_TO_TICKS( ( TickType_t ) 150 );
+const TickType_t xMinDelay = pdMS_TO_TICKS( ( TickType_t ) 75 );
+const TickType_t xTinyDelay = pdMS_TO_TICKS( ( TickType_t ) 2 );
+
+	/* Generate the next delay time.  This is kept within a narrow band so as
+	not to disturb the timing of other tests - but does add in some pseudo
+	randomisation into the tests. */
+	do
+	{
+		xNextDelay = prvRand() % xMaxDelay;
+
+		/* Just in case this loop is executed lots of times. */
+		vTaskDelay( xTinyDelay );
+
+	} while ( xNextDelay < xMinDelay );
+
+	return xNextDelay;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSanityCheckCreatedEventGroup( EventGroupHandle_t xEventGroup )
+{
+EventBits_t xEventBits;
+const EventBits_t xFirstTestBits = ( EventBits_t ) 0xaa, xSecondTestBits = ( EventBits_t ) 0x55;
+
+	/* The event group should not have any bits set yet. */
+	xEventBits = xEventGroupGetBits( xEventGroup );
+
+	if( xEventBits != ( EventBits_t ) 0 )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+
+	/* Some some bits, then read them back to check they are as expected. */
+	xEventGroupSetBits( xEventGroup, xFirstTestBits );
+
+	xEventBits = xEventGroupGetBits( xEventGroup );
+
+	if( xEventBits != xFirstTestBits )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+
+	xEventGroupSetBits( xEventGroup, xSecondTestBits );
+
+	xEventBits = xEventGroupGetBits( xEventGroup );
+
+	if( xEventBits != ( xFirstTestBits | xSecondTestBits ) )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+
+	/* Finally try clearing some bits too and check that operation proceeds as
+	expected. */
+	xEventGroupClearBits( xEventGroup, xFirstTestBits );
+
+	xEventBits = xEventGroupGetBits( xEventGroup );
+
+	if( xEventBits != xSecondTestBits )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSanityCheckCreatedSemaphore( SemaphoreHandle_t xSemaphore, UBaseType_t uxMaxCount )
+{
+BaseType_t xReturned;
+UBaseType_t x;
+const TickType_t xShortBlockTime = pdMS_TO_TICKS( 10 );
+TickType_t xTickCount;
+
+	/* The binary semaphore should start 'empty', so a call to xSemaphoreTake()
+	should fail. */
+	xTickCount = xTaskGetTickCount();
+	xReturned = xSemaphoreTake( xSemaphore, xShortBlockTime );
+
+	if( ( ( TickType_t ) ( xTaskGetTickCount() - xTickCount ) ) < xShortBlockTime )
+	{
+		/* Did not block on the semaphore as long as expected. */
+		xErrorOccurred = pdTRUE;
+	}
+
+	if( xReturned != pdFAIL )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+
+	/* Should be possible to 'give' the semaphore up to a maximum of uxMaxCount
+	times. */
+	for( x = 0; x < uxMaxCount; x++ )
+	{
+		xReturned = xSemaphoreGive( xSemaphore );
+
+		if( xReturned == pdFAIL )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+	}
+
+	/* Giving the semaphore again should fail, as it is 'full'. */
+	xReturned = xSemaphoreGive( xSemaphore );
+
+	if( xReturned != pdFAIL )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+
+	configASSERT( uxSemaphoreGetCount( xSemaphore ) == uxMaxCount );
+
+	/* Should now be possible to 'take' the semaphore up to a maximum of
+	uxMaxCount times without blocking. */
+	for( x = 0; x < uxMaxCount; x++ )
+	{
+		xReturned = xSemaphoreTake( xSemaphore, staticDONT_BLOCK );
+
+		if( xReturned == pdFAIL )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+	}
+
+	/* Back to the starting condition, where the semaphore should not be
+	available. */
+	xTickCount = xTaskGetTickCount();
+	xReturned = xSemaphoreTake( xSemaphore, xShortBlockTime );
+
+	if( ( ( TickType_t ) ( xTaskGetTickCount() - xTickCount ) ) < xShortBlockTime )
+	{
+		/* Did not block on the semaphore as long as expected. */
+		xErrorOccurred = pdTRUE;
+	}
+
+	if( xReturned != pdFAIL )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+
+	configASSERT( uxSemaphoreGetCount( xSemaphore ) == 0 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSanityCheckCreatedQueue( QueueHandle_t xQueue )
+{
+uint64_t ull, ullRead;
+BaseType_t xReturned, xLoop;
+
+	/* This test is done twice to ensure the queue storage area wraps. */
+	for( xLoop = 0; xLoop < 2; xLoop++ )
+	{
+		/* A very basic test that the queue can be written to and read from as
+		expected.  First the queue should be empty. */
+		xReturned = xQueueReceive( xQueue, &ull, staticDONT_BLOCK );
+		if( xReturned != errQUEUE_EMPTY )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+
+		/* Now it should be possible to write to the queue staticQUEUE_LENGTH_IN_ITEMS
+		times. */
+		for( ull = 0; ull < staticQUEUE_LENGTH_IN_ITEMS; ull++ )
+		{
+			xReturned = xQueueSend( xQueue, &ull, staticDONT_BLOCK );
+			if( xReturned != pdPASS )
+			{
+				xErrorOccurred = pdTRUE;
+			}
+		}
+
+		/* Should not now be possible to write to the queue again. */
+		xReturned = xQueueSend( xQueue, &ull, staticDONT_BLOCK );
+		if( xReturned != errQUEUE_FULL )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+
+		/* Now read back from the queue to ensure the data read back matches that
+		written. */
+		for( ull = 0; ull < staticQUEUE_LENGTH_IN_ITEMS; ull++ )
+		{
+			xReturned = xQueueReceive( xQueue, &ullRead, staticDONT_BLOCK );
+
+			if( xReturned != pdPASS )
+			{
+				xErrorOccurred = pdTRUE;
+			}
+
+			if( ullRead != ull )
+			{
+				xErrorOccurred = pdTRUE;
+			}
+		}
+
+		/* The queue should be empty again. */
+		xReturned = xQueueReceive( xQueue, &ull, staticDONT_BLOCK );
+		if( xReturned != errQUEUE_EMPTY )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSanityCheckCreatedRecursiveMutex( SemaphoreHandle_t xSemaphore )
+{
+const BaseType_t xLoops = 5;
+BaseType_t x, xReturned;
+
+	/* A very basic test that the recursive semaphore behaved like a recursive
+	semaphore. First the semaphore should not be able to be given, as it has not
+	yet been taken. */
+	xReturned = xSemaphoreGiveRecursive( xSemaphore );
+
+	if( xReturned != pdFAIL )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+
+	/* Now it should be possible to take the mutex a number of times. */
+	for( x = 0; x < xLoops; x++ )
+	{
+		xReturned = xSemaphoreTakeRecursive( xSemaphore, staticDONT_BLOCK );
+
+		if( xReturned != pdPASS )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+	}
+
+	/* Should be possible to give the semaphore the same number of times as it
+	was given in the loop above. */
+	for( x = 0; x < xLoops; x++ )
+	{
+		xReturned = xSemaphoreGiveRecursive( xSemaphore );
+
+		if( xReturned != pdPASS )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+	}
+
+	/* No more gives should be possible though. */
+	xReturned = xSemaphoreGiveRecursive( xSemaphore );
+
+	if( xReturned != pdFAIL )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xAreStaticAllocationTasksStillRunning( void )
+{
+static UBaseType_t uxLastCycleCounter = 0;
+BaseType_t xReturn;
+
+	if( uxCycleCounter == uxLastCycleCounter )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+	else
+	{
+		uxLastCycleCounter = uxCycleCounter;
+	}
+
+	if( xErrorOccurred != pdFALSE )
+	{
+		xReturn = pdFAIL;
+	}
+	else
+	{
+		xReturn = pdPASS;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+/* Exclude the entire file if configSUPPORT_STATIC_ALLOCATION is 0. */
+#endif /* configSUPPORT_STATIC_ALLOCATION == 1 */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/StreamBufferDemo.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/StreamBufferDemo.c
new file mode 100644
index 0000000..0efddcd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/StreamBufferDemo.c
@@ -0,0 +1,1061 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include "stdio.h"
+#include "string.h"
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "stream_buffer.h"
+
+/* Demo app includes. */
+#include "StreamBufferDemo.h"
+
+/* The number of bytes of storage in the stream buffers used in this test. */
+#define sbSTREAM_BUFFER_LENGTH_BYTES	( ( size_t ) 30 )
+
+/* Stream buffer length one. */
+#define sbSTREAM_BUFFER_LENGTH_ONE		( ( size_t ) 1 )
+
+/* Start and end ASCII characters used in data sent to the buffers. */
+#define sbASCII_SPACE					32
+#define sbASCII_TILDA					126
+
+/* Defines the number of tasks to create in this test and demo. */
+#define sbNUMBER_OF_ECHO_CLIENTS	( 2 )
+#define sbNUMBER_OF_SENDER_TASKS	( 2 )
+
+/* Priority of the test tasks.  The send and receive go from low to high
+priority tasks, and from high to low priority tasks. */
+#define sbLOWER_PRIORITY			( tskIDLE_PRIORITY )
+#define sbHIGHER_PRIORITY			( tskIDLE_PRIORITY + 1 )
+
+/* Block times used when sending and receiving from the stream buffers. */
+#define sbRX_TX_BLOCK_TIME			pdMS_TO_TICKS( 125UL )
+
+/* A block time of 0 means "don't block". */
+#define sbDONT_BLOCK				( 0 )
+
+/* The trigger level sets the number of bytes that must be present in the
+stream buffer before a task that is blocked on the stream buffer is moved out of
+the Blocked state so it can read the bytes. */
+#define sbTRIGGER_LEVEL_1			( 1 )
+
+/* The size of the stack allocated to the tasks that run as part of this demo/
+test.  The stack size is over generous in most cases. */
+#define sbSTACK_SIZE				( configMINIMAL_STACK_SIZE + ( configMINIMAL_STACK_SIZE >> 1 ) )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Performs various tests that do not require multiple tasks to interact.
+ */
+static void prvSingleTaskTests( StreamBufferHandle_t xStreamBuffer );
+
+/*
+ * Tests sending and receiving various lengths of data via a stream buffer.
+ * The echo client sends the data to the echo server, which then sends the
+ * data back to the echo client, which checks it receives exactly what it
+ * sent.
+ */
+static void prvEchoClient( void *pvParameters );
+static void prvEchoServer( void *pvParameters );
+
+/*
+ * Tasks that send and receive to a stream buffer at a low priority and without
+ * blocking, so the send and receive functions interleave in time as the tasks
+ * are switched in and out.
+ */
+static void prvNonBlockingReceiverTask( void *pvParameters );
+static void prvNonBlockingSenderTask( void *pvParameters );
+
+/* Performs an assert() like check in a way that won't get removed when
+performing a code coverage analysis. */
+static void prvCheckExpectedState( BaseType_t xState );
+
+/*
+ * A task that creates a stream buffer with a specific trigger level, then
+ * receives a string from an interrupt (the RTOS tick hook) byte by byte to
+ * check it is only unblocked when the specified trigger level is reached.
+ */
+static void prvInterruptTriggerLevelTest( void *pvParameters );
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1  )
+	/* This file tests both statically and dynamically allocated stream buffers.
+	Allocate the structures and buffers to be used by the statically allocated
+	objects, which get used in the echo tests. */
+	static void prvReceiverTask( void *pvParameters );
+	static void prvSenderTask( void *pvParameters );
+
+	static StaticStreamBuffer_t xStaticStreamBuffers[ sbNUMBER_OF_ECHO_CLIENTS ];
+	static uint8_t ucBufferStorage[ sbNUMBER_OF_SENDER_TASKS ][ sbSTREAM_BUFFER_LENGTH_BYTES + 1 ];
+	static uint32_t ulSenderLoopCounters[ sbNUMBER_OF_SENDER_TASKS ] = { 0 };
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/*-----------------------------------------------------------*/
+
+/* The buffers used by the echo client and server tasks. */
+typedef struct ECHO_STREAM_BUFFERS
+{
+	/* Handles to the data structures that describe the stream buffers. */
+	StreamBufferHandle_t xEchoClientBuffer;
+	StreamBufferHandle_t xEchoServerBuffer;
+} EchoStreamBuffers_t;
+static volatile uint32_t ulEchoLoopCounters[ sbNUMBER_OF_ECHO_CLIENTS ] = { 0 };
+
+/* The non-blocking tasks monitor their operation, and if no errors have been
+found, increment ulNonBlockingRxCounter.  xAreStreamBufferTasksStillRunning()
+then checks ulNonBlockingRxCounter and only returns pdPASS if
+ulNonBlockingRxCounter is still incrementing. */
+static volatile uint32_t ulNonBlockingRxCounter = 0;
+
+/* The task that receives characters from the tick interrupt in order to test
+different trigger levels monitors its own behaviour.  If it has not detected any
+error then it increments ulInterruptTriggerCounter to indicate to the check task
+that it is still operating correctly. */
+static volatile uint32_t ulInterruptTriggerCounter = 0UL;
+
+/* The stream buffer used from the tick interrupt.  This sends one byte at a time
+to a test task to test the trigger level operation.  The variable is set to NULL
+in between test runs. */
+static volatile StreamBufferHandle_t xInterruptStreamBuffer = NULL;
+
+/* The data sent from the tick interrupt to the task that tests the trigger
+level functionality. */
+static const char *pcDataSentFromInterrupt = "12345678";
+
+/* Data that is longer than the buffer that is sent to the buffers as a stream
+of bytes.  Parts of which are written to the stream buffer to test writing
+different lengths at different offsets, to many bytes, part streams, streams
+that wrap, etc..  Two messages are defined to ensure left over data is not
+accidentally read out of the buffer. */
+static const char *pc55ByteString = "One two three four five six seven eight nine ten eleven";
+static const char *pc54ByteString = "01234567891abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQ";
+
+/* Used to log the status of the tests contained within this file for reporting
+to a monitoring task ('check' task). */
+static BaseType_t xErrorStatus = pdPASS;
+
+/*-----------------------------------------------------------*/
+
+void vStartStreamBufferTasks( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+
+	/* The echo servers sets up the stream buffers before creating the echo
+	client tasks.  One set of tasks has the server as the higher priority, and
+	the other has the client as the higher priority. */
+	xTaskCreate( prvEchoServer, "1StrEchoServer", sbSTACK_SIZE, NULL, sbHIGHER_PRIORITY, NULL );
+	xTaskCreate( prvEchoServer, "2StrEchoServer", sbSTACK_SIZE, NULL, sbLOWER_PRIORITY, NULL );
+
+	/* The non blocking tasks run continuously and will interleave with each
+	other, so must be created at the lowest priority.  The stream buffer they
+	use is created and passed in using the task's parameter. */
+	xStreamBuffer = xStreamBufferCreate( sbSTREAM_BUFFER_LENGTH_BYTES, sbTRIGGER_LEVEL_1 );
+	xTaskCreate( prvNonBlockingReceiverTask, "StrNonBlkRx", configMINIMAL_STACK_SIZE, ( void * ) xStreamBuffer, tskIDLE_PRIORITY, NULL );
+	xTaskCreate( prvNonBlockingSenderTask, "StrNonBlkTx", configMINIMAL_STACK_SIZE, ( void * ) xStreamBuffer, tskIDLE_PRIORITY, NULL );
+
+	/* The task that receives bytes from an interrupt to test that it unblocks
+	at a specific trigger level must run at a high priority to minimise the risk
+	of it receiving more characters before it can execute again after being
+	unblocked. */
+	xTaskCreate( prvInterruptTriggerLevelTest, "StrTrig", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );
+
+	#if( configSUPPORT_STATIC_ALLOCATION == 1  )
+	{
+		/* The sender tasks set up the stream buffers before creating the
+		receiver tasks.  Priorities must be 0 and 1 as the priority is used to
+		index into the xStaticStreamBuffers and ucBufferStorage arrays. */
+		xTaskCreate( prvSenderTask, "Str1Sender", sbSTACK_SIZE, NULL, sbHIGHER_PRIORITY, NULL );
+		xTaskCreate( prvSenderTask, "Str2Sender", sbSTACK_SIZE, NULL, sbLOWER_PRIORITY, NULL );
+	}
+	#endif /* configSUPPORT_STATIC_ALLOCATION */
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckExpectedState( BaseType_t xState )
+{
+	configASSERT( xState );
+	if( xState == pdFAIL )
+	{
+		xErrorStatus = pdFAIL;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSingleTaskTests( StreamBufferHandle_t xStreamBuffer )
+{
+size_t xReturned, xItem, xExpectedSpace;
+const size_t xMax6ByteMessages = sbSTREAM_BUFFER_LENGTH_BYTES / 6;
+const size_t x6ByteLength = 6, x17ByteLength = 17, xFullBufferSize = sbSTREAM_BUFFER_LENGTH_BYTES * ( size_t ) 2;
+uint8_t *pucFullBuffer, *pucData, *pucReadData;
+TickType_t xTimeBeforeCall, xTimeAfterCall;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 15 ), xAllowableMargin = pdMS_TO_TICKS( 3 ), xMinimalBlockTime = 2;
+UBaseType_t uxOriginalPriority;
+
+	/* Remove warning in case configASSERT() is not defined. */
+	( void ) xAllowableMargin;
+
+	/* To minimise stack and heap usage a full size buffer is allocated from the
+	heap, then buffers which hold smaller amounts of data are overlayed with the
+	larger buffer - just make sure not to use both at once! */
+	pucFullBuffer = pvPortMalloc( xFullBufferSize );
+	configASSERT( pucFullBuffer );
+
+	pucData = pucFullBuffer;
+	pucReadData = pucData + x17ByteLength;
+
+	/* Nothing has been added or removed yet, so expect the free space to be
+	exactly as created. */
+	xExpectedSpace = xStreamBufferSpacesAvailable( xStreamBuffer );
+	prvCheckExpectedState( xExpectedSpace == sbSTREAM_BUFFER_LENGTH_BYTES );
+	prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE );
+
+
+	/* The buffer is 30 bytes long.  6 5 byte messages should fit before the
+	buffer is completely full. */
+	for( xItem = 0; xItem < xMax6ByteMessages; xItem++ )
+	{
+		prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
+
+		/* Generate recognisable data to write to the buffer.  This is just
+		ascii characters that shows which loop iteration the data was written
+		in. The 'FromISR' version is used to give it some exercise as a block
+		time is not used, so the call must be inside a critical section so it
+		runs with ports that don't support interrupt nesting (and therefore
+		don't have interrupt safe critical sections). */
+		memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x6ByteLength );
+		taskENTER_CRITICAL();
+		{
+			xReturned = xStreamBufferSendFromISR( xStreamBuffer, ( void * ) pucData, x6ByteLength, NULL );
+		}
+		taskEXIT_CRITICAL();
+		prvCheckExpectedState( xReturned == x6ByteLength );
+
+		/* The space in the buffer will have reduced by the amount of user data
+		written into the buffer. */
+		xExpectedSpace -= x6ByteLength;
+		xReturned = xStreamBufferSpacesAvailable( xStreamBuffer );
+		prvCheckExpectedState( xReturned == xExpectedSpace );
+		xReturned = xStreamBufferBytesAvailable( xStreamBuffer );
+		/* +1 as it is zero indexed. */
+		prvCheckExpectedState( xReturned == ( ( xItem + 1 ) * x6ByteLength ) );
+	}
+
+	/* Now the buffer should be full, and attempting to add anything will should
+	fail. */
+	prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE );
+	xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, sizeof( pucData[ 0 ] ), sbDONT_BLOCK );
+	prvCheckExpectedState( xReturned == 0 );
+
+	/* Adding with a timeout should also fail after the appropriate time.  The
+	priority is temporarily boosted in this part of the test to keep the
+	allowable margin to a minimum. */
+	uxOriginalPriority = uxTaskPriorityGet( NULL );
+	vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
+	xTimeBeforeCall = xTaskGetTickCount();
+	xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, sizeof( pucData[ 0 ] ), xBlockTime );
+	xTimeAfterCall = xTaskGetTickCount();
+	vTaskPrioritySet( NULL, uxOriginalPriority );
+	prvCheckExpectedState( ( xTimeAfterCall - xTimeBeforeCall ) >= xBlockTime );
+	prvCheckExpectedState( ( xTimeAfterCall - xTimeBeforeCall ) < ( xBlockTime + xAllowableMargin ) );
+	prvCheckExpectedState( xReturned == 0 );
+
+	/* The buffer is now full of data in the form "000000", "111111", etc.  Make
+	sure the data is read out as expected. */
+	for( xItem = 0; xItem < xMax6ByteMessages; xItem++ )
+	{
+		/* Generate the data that is expected to be read out for this loop
+		iteration. */
+		memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x6ByteLength );
+
+		/* Read the next 6 bytes out.  The 'FromISR' version is used to give it
+		some exercise as a block time is not used, so a it must be called from
+		a critical section so this will work on ports that don't support
+		interrupt nesting (so don't have interrupt safe critical sections). */
+		taskENTER_CRITICAL();
+		{
+			xReturned = xStreamBufferReceiveFromISR( xStreamBuffer, ( void * ) pucReadData, x6ByteLength, NULL );
+		}
+		taskEXIT_CRITICAL();
+		prvCheckExpectedState( xReturned == x6ByteLength );
+
+		/* Does the data read out match that expected? */
+		prvCheckExpectedState( memcmp( ( void * ) pucData, ( void * ) pucReadData, x6ByteLength ) == 0 );
+
+		/* The space in the buffer will have increased by the amount of user
+		data removed from the buffer. */
+		xExpectedSpace += x6ByteLength;
+		xReturned = xStreamBufferSpacesAvailable( xStreamBuffer );
+		prvCheckExpectedState( xReturned == xExpectedSpace );
+		xReturned = xStreamBufferBytesAvailable( xStreamBuffer );
+		prvCheckExpectedState( xReturned == ( sbSTREAM_BUFFER_LENGTH_BYTES - xExpectedSpace ) );
+	}
+
+	/* The buffer should be empty again. */
+	prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE );
+	xExpectedSpace = xStreamBufferSpacesAvailable( xStreamBuffer );
+	prvCheckExpectedState( xExpectedSpace == sbSTREAM_BUFFER_LENGTH_BYTES );
+
+	/* Reading with a timeout should also fail after the appropriate time.  The
+	priority is temporarily boosted in this part of the test to keep the
+	allowable margin to a minimum. */
+	vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
+	xTimeBeforeCall = xTaskGetTickCount();
+	xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucReadData, x6ByteLength, xBlockTime );
+	xTimeAfterCall = xTaskGetTickCount();
+	vTaskPrioritySet( NULL, uxOriginalPriority );
+	prvCheckExpectedState( ( xTimeAfterCall - xTimeBeforeCall ) >= xBlockTime );
+	prvCheckExpectedState( ( xTimeAfterCall - xTimeBeforeCall ) < ( xBlockTime + xAllowableMargin ) );
+	prvCheckExpectedState( xReturned == 0 );
+
+
+	/* In the next loop 17 bytes are written to then read out on each
+	iteration.  As 30 is not divisible by 17 the data will wrap around. */
+	xExpectedSpace = sbSTREAM_BUFFER_LENGTH_BYTES - x17ByteLength;
+
+	for( xItem = 0; xItem < 100; xItem++ )
+	{
+		/* Generate recognisable data to write to the queue.  This is just
+		ascii characters that shows which loop iteration the data was written
+		in. */
+		memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x17ByteLength );
+		xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, x17ByteLength, sbDONT_BLOCK );
+		prvCheckExpectedState( xReturned == x17ByteLength );
+
+		/* The space in the buffer will have reduced by the amount of user data
+		written into the buffer. */
+		xReturned = xStreamBufferSpacesAvailable( xStreamBuffer );
+		prvCheckExpectedState( xReturned == xExpectedSpace );
+		xReturned = xStreamBufferBytesAvailable( xStreamBuffer );
+		prvCheckExpectedState( xReturned == x17ByteLength );
+		prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
+		prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE );
+
+		/* Read the 17 bytes out again. */
+		xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucReadData, x17ByteLength, sbDONT_BLOCK );
+		prvCheckExpectedState( xReturned == x17ByteLength );
+
+		/* Does the data read out match that expected? */
+		prvCheckExpectedState( memcmp( ( void * ) pucData, ( void * ) pucReadData, x17ByteLength ) == 0 );
+
+		/* Full buffer space available again. */
+		xReturned = xStreamBufferSpacesAvailable( xStreamBuffer );
+		prvCheckExpectedState( xReturned == sbSTREAM_BUFFER_LENGTH_BYTES );
+		xReturned = xStreamBufferBytesAvailable( xStreamBuffer );
+		prvCheckExpectedState( xReturned == 0 );
+		prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
+		prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE );
+	}
+
+	/* Fill the buffer with one message, check it is full, then read it back
+	again and check the correct data is received. */
+	xStreamBufferSend( xStreamBuffer, ( const void * ) pc55ByteString, sbSTREAM_BUFFER_LENGTH_BYTES, sbDONT_BLOCK );
+	xStreamBufferReceive( xStreamBuffer, ( void * ) pucFullBuffer, sbSTREAM_BUFFER_LENGTH_BYTES, sbDONT_BLOCK );
+	prvCheckExpectedState( memcmp( pc55ByteString, pucFullBuffer, sbSTREAM_BUFFER_LENGTH_BYTES ) == 0 );
+
+	/* Fill the buffer one bytes at a time. */
+	for( xItem = 0; xItem < sbSTREAM_BUFFER_LENGTH_BYTES; xItem++ )
+	{
+		/* Block time is only for test coverage, the task should never actually
+		block here. */
+		xStreamBufferSend( xStreamBuffer, ( const void * ) &( pc54ByteString[ xItem ] ), sizeof( char ), sbRX_TX_BLOCK_TIME );
+	}
+
+	/* The buffer should now be full. */
+	prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE );
+
+	/* Read the message out in one go, even though it was written in individual
+	bytes.  Try reading much more data than is actually available to ensure only
+	the available bytes are returned (otherwise this read will write outside of
+	the memory allocated anyway!). */
+	xReturned = xStreamBufferReceive( xStreamBuffer, pucFullBuffer, sbSTREAM_BUFFER_LENGTH_BYTES * ( size_t ) 2, sbRX_TX_BLOCK_TIME );
+	prvCheckExpectedState( xReturned == sbSTREAM_BUFFER_LENGTH_BYTES );
+	prvCheckExpectedState( memcmp( ( const void * ) pc54ByteString, ( const void * ) pucFullBuffer, sbSTREAM_BUFFER_LENGTH_BYTES ) == 0 );
+
+	/* Now do the opposite, write in one go and read out in single bytes. */
+	xReturned = xStreamBufferSend( xStreamBuffer, ( const void * ) pc55ByteString, sbSTREAM_BUFFER_LENGTH_BYTES, sbRX_TX_BLOCK_TIME );
+	prvCheckExpectedState( xReturned == sbSTREAM_BUFFER_LENGTH_BYTES );
+	prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE );
+	prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE );
+	prvCheckExpectedState( xStreamBufferBytesAvailable( xStreamBuffer ) == sbSTREAM_BUFFER_LENGTH_BYTES );
+	prvCheckExpectedState( xStreamBufferSpacesAvailable( xStreamBuffer ) == 0 );
+
+	/* Read from the buffer one byte at a time. */
+	for( xItem = 0; xItem < sbSTREAM_BUFFER_LENGTH_BYTES; xItem++ )
+	{
+		/* Block time is only for test coverage, the task should never actually
+		block here. */
+		xStreamBufferReceive( xStreamBuffer, ( void * ) pucFullBuffer, sizeof( char ), sbRX_TX_BLOCK_TIME );
+		prvCheckExpectedState( pc55ByteString[ xItem ] == pucFullBuffer[ 0 ] );
+	}
+	prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE );
+	prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
+
+	/* Try writing more bytes than there is space. */
+	vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
+	xTimeBeforeCall = xTaskGetTickCount();
+	xReturned = xStreamBufferSend( xStreamBuffer, ( const void * ) pc54ByteString, sbSTREAM_BUFFER_LENGTH_BYTES * ( size_t ) 2, xMinimalBlockTime );
+	xTimeAfterCall = xTaskGetTickCount();
+	vTaskPrioritySet( NULL, uxOriginalPriority );
+	prvCheckExpectedState( ( xTimeAfterCall - xTimeBeforeCall ) >= xMinimalBlockTime );
+	prvCheckExpectedState( ( xTimeAfterCall - xTimeBeforeCall ) < ( xMinimalBlockTime + xAllowableMargin ) );
+	prvCheckExpectedState( xReturned == sbSTREAM_BUFFER_LENGTH_BYTES );
+	prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE );
+	prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE );
+
+	/* No space now though. */
+	xReturned = xStreamBufferSend( xStreamBuffer, ( const void * ) pc54ByteString, sbSTREAM_BUFFER_LENGTH_BYTES * ( size_t ) 2, xMinimalBlockTime );
+	prvCheckExpectedState( xReturned == 0 );
+
+	/* Ensure data was written as expected even when there was an attempt to
+	write more than was available.  This also tries to read more bytes than are
+	available. */
+	xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucFullBuffer, xFullBufferSize, xMinimalBlockTime );
+	prvCheckExpectedState( memcmp( ( const void * ) pucFullBuffer, ( const void * ) pc54ByteString, sbSTREAM_BUFFER_LENGTH_BYTES ) == 0 );
+	prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
+	prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE );
+
+	/* Clean up with data in the buffer to ensure the tests that follow don't
+	see the data (the data should be discarded). */
+	( void ) xStreamBufferSend( xStreamBuffer, ( const void * ) pc55ByteString, sbSTREAM_BUFFER_LENGTH_BYTES / ( size_t ) 2, sbDONT_BLOCK );
+	vPortFree( pucFullBuffer );
+	xStreamBufferReset( xStreamBuffer );
+}
+/*-----------------------------------------------------------*/
+
+static void prvNonBlockingSenderTask( void *pvParameters )
+{
+StreamBufferHandle_t xStreamBuffer;
+size_t xNextChar = 0, xBytesToSend, xBytesActuallySent;
+const size_t xStringLength = strlen( pc54ByteString );
+
+	/* In this case the stream buffer has already been created and is passed
+	into the task using the task's parameter. */
+	xStreamBuffer = ( StreamBufferHandle_t ) pvParameters;
+
+	/* Keep sending the string to the stream buffer as many bytes as possible in
+	each go.  Doesn't block so calls can interleave with the non-blocking
+	receives performed by prvNonBlockingReceiverTask(). */
+	for( ;; )
+	{
+		/* The whole string cannot be sent at once, so xNextChar is an index to
+		the position within the string that has been sent so far.  How many
+		bytes are there left to send before the end of the string? */
+		xBytesToSend = xStringLength - xNextChar;
+
+		/* Attempt to send right up to the end of the string. */
+		xBytesActuallySent = xStreamBufferSend( xStreamBuffer, ( const void * ) &( pc54ByteString[ xNextChar ] ), xBytesToSend, sbDONT_BLOCK );
+		prvCheckExpectedState( xBytesActuallySent <= xBytesToSend );
+
+		/* Move the index up the string to the next character to be sent,
+		wrapping if the end of the string has been reached. */
+		xNextChar += xBytesActuallySent;
+		prvCheckExpectedState( xNextChar <= xStringLength );
+
+		if( xNextChar == xStringLength )
+		{
+			xNextChar = 0;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvNonBlockingReceiverTask( void *pvParameters )
+{
+StreamBufferHandle_t xStreamBuffer;
+size_t xNextChar = 0, xReceiveLength, xBytesToTest, xStartIndex;
+const size_t xStringLength = strlen( pc54ByteString );
+char cRxString[ 12 ]; /* Holds received characters. */
+BaseType_t xNonBlockingReceiveError = pdFALSE;
+
+	/* In this case the stream buffer has already been created and is passed
+	into the task using the task's parameter. */
+	xStreamBuffer = ( StreamBufferHandle_t ) pvParameters;
+
+	/* Expects to receive the pc54ByteString over and over again.  Sends and
+	receives are not blocking so will interleave. */
+	for( ;; )
+	{
+		/* Attempt to receive as many bytes as possible, up to the limit of the
+		Rx buffer size. */
+		xReceiveLength = xStreamBufferReceive( xStreamBuffer, ( void * ) cRxString, sizeof( cRxString ), sbDONT_BLOCK );
+
+		if( xReceiveLength > 0 )
+		{
+			/* xNextChar is the index into pc54ByteString that has been received
+			already.  If xReceiveLength bytes are added to that, will it go off
+			the end of the string?  If so, then first test up to the end of the
+			string, then go back to the start of pc54ByteString to test the
+			remains of the received data. */
+			xBytesToTest = xReceiveLength;
+			if( ( xNextChar + xBytesToTest ) > xStringLength )
+			{
+				/* Cap to test the received data to the end of the string. */
+				xBytesToTest = xStringLength - xNextChar;
+
+				if( memcmp( ( const void * ) &( pc54ByteString[ xNextChar ] ), ( const void * ) cRxString, xBytesToTest ) != 0 )
+				{
+					xNonBlockingReceiveError = pdTRUE;
+				}
+
+				/* Then move back to the start of the string to test the
+				remaining received bytes. */
+				xNextChar = 0;
+				xStartIndex = xBytesToTest;
+				xBytesToTest = xReceiveLength - xBytesToTest;
+			}
+			else
+			{
+				/* The string didn't wrap in the buffer, so start comparing from
+				the start of the received data. */
+				xStartIndex = 0;
+			}
+
+			/* Test the received bytes are as expected, then move the index
+			along the string to the next expected char to receive. */
+			if( memcmp( ( const void * ) &( pc54ByteString[ xNextChar ] ), ( const void * ) &( cRxString[ xStartIndex ] ), xBytesToTest ) != 0 )
+			{
+				xNonBlockingReceiveError = pdTRUE;
+			}
+
+			if( xNonBlockingReceiveError == pdFALSE )
+			{
+				/* No errors detected so increment the counter that lets the
+				check task know this test is still functioning correctly. */
+				ulNonBlockingRxCounter++;
+			}
+
+			xNextChar += xBytesToTest;
+			if( xNextChar >= xStringLength )
+			{
+				xNextChar = 0;
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1  )
+
+	static void prvSenderTask( void *pvParameters )
+	{
+	StreamBufferHandle_t xStreamBuffer, xTempStreamBuffer;
+	static uint8_t ucTempBuffer[ 10 ]; /* Just used to exercise stream buffer creating and deletion. */
+	const TickType_t xTicksToWait = sbRX_TX_BLOCK_TIME, xShortDelay = pdMS_TO_TICKS( 50 );
+	StaticStreamBuffer_t xStaticStreamBuffer;
+	size_t xNextChar = 0, xBytesToSend, xBytesActuallySent;
+	const size_t xStringLength = strlen( pc55ByteString );
+
+	/* The task's priority is used as an index into the loop counters used to
+	indicate this task is still running. */
+	UBaseType_t uxIndex = uxTaskPriorityGet( NULL );
+
+		/* Make sure a change in priority does not inadvertently result in an
+		invalid array index. */
+		prvCheckExpectedState( uxIndex < sbNUMBER_OF_ECHO_CLIENTS );
+
+		/* Avoid compiler warnings about unused parameters. */
+		( void ) pvParameters;
+
+		xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ) / sbNUMBER_OF_SENDER_TASKS, /* The number of bytes in each buffer in the array. */
+												   sbTRIGGER_LEVEL_1, /* The number of bytes to be in the buffer before a task blocked to wait for data is unblocked. */
+												   &( ucBufferStorage[ uxIndex ][ 0 ] ), /* The address of the buffer to use within the array. */
+												   &( xStaticStreamBuffers[ uxIndex ] ) ); /* The static stream buffer structure to use within the array. */
+
+		/* Now the stream buffer has been created the receiver task can be
+		created.  If this sender task has the higher priority then the receiver
+		task is created at the lower priority - if this sender task has the
+		lower priority then the receiver task is created at the higher
+		priority. */
+		if( uxTaskPriorityGet( NULL ) == sbLOWER_PRIORITY )
+		{
+			/* Here prvSingleTaskTests() performs various tests on a stream buffer
+			that was created statically. */
+			prvSingleTaskTests( xStreamBuffer );
+			xTaskCreate( prvReceiverTask, "StrReceiver", sbSTACK_SIZE,  ( void * ) xStreamBuffer, sbHIGHER_PRIORITY, NULL );
+		}
+		else
+		{
+			xTaskCreate( prvReceiverTask, "StrReceiver", sbSTACK_SIZE,  ( void * ) xStreamBuffer, sbLOWER_PRIORITY, NULL );
+		}
+
+		for( ;; )
+		{
+			/* The whole string cannot be sent at once, so xNextChar is an index
+			to the position within the string that has been sent so far.  How
+			many bytes are there left to send before the end of the string? */
+			xBytesToSend = xStringLength - xNextChar;
+
+			/* Attempt to send right up to the end of the string. */
+			xBytesActuallySent = xStreamBufferSend( xStreamBuffer, ( const void * ) &( pc55ByteString[ xNextChar ] ), xBytesToSend, xTicksToWait );
+			prvCheckExpectedState( xBytesActuallySent <= xBytesToSend );
+
+			/* Move the index up the string to the next character to be sent,
+			wrapping if the end of the string has been reached. */
+			xNextChar += xBytesActuallySent;
+			prvCheckExpectedState( xNextChar <= xStringLength );
+
+			if( xNextChar == xStringLength )
+			{
+				xNextChar = 0;
+			}
+
+			/* Increment a loop counter so a check task can tell this task is
+			still running as expected. */
+			ulSenderLoopCounters[ uxIndex ]++;
+
+			if( uxTaskPriorityGet( NULL ) == sbHIGHER_PRIORITY )
+			{
+				/* Allow other tasks to run. */
+				vTaskDelay( xShortDelay );
+			}
+
+			/* This stream buffer is just created and deleted to ensure no
+			issues when attempting to delete a stream buffer that was
+			created using statically allocated memory.  To save stack space
+			the buffer is set to point to the pc55ByteString, which is a const
+			string, but no data is written into the buffer so any valid address
+			will do. */
+			xTempStreamBuffer = xStreamBufferCreateStatic( sizeof( ucTempBuffer ), sbTRIGGER_LEVEL_1, ucTempBuffer, &xStaticStreamBuffer );
+			xStreamBufferReset( xTempStreamBuffer );
+			vStreamBufferDelete( xTempStreamBuffer );
+		}
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1  )
+
+	static void prvReceiverTask( void *pvParameters )
+	{
+	StreamBufferHandle_t const pxStreamBuffer = ( StreamBufferHandle_t ) pvParameters;
+	char cRxString[ 12 ]; /* Large enough to hold a 32-bit number in ASCII. */
+	const TickType_t xTicksToWait = pdMS_TO_TICKS( 5UL );
+	const size_t xStringLength = strlen( pc55ByteString );
+	size_t xNextChar = 0, xReceivedLength, xBytesToReceive;
+
+		for( ;; )
+		{
+			/* Attempt to receive the number of bytes to the end of the string,
+			or the number of byte that can be placed into the rx buffer,
+			whichever is smallest. */
+			xBytesToReceive = configMIN( ( xStringLength - xNextChar ), sizeof( cRxString ) );
+
+			do
+			{
+				xReceivedLength = xStreamBufferReceive( pxStreamBuffer, ( void * ) cRxString, xBytesToReceive, xTicksToWait );
+
+			} while( xReceivedLength == 0 );
+
+			/* Ensure the received string matches the expected string. */
+			prvCheckExpectedState( memcmp( ( void * ) cRxString, ( const void * ) &( pc55ByteString[ xNextChar ] ), xReceivedLength ) == 0 );
+
+			/* Move the index into the string up to the end of the bytes
+			received so far - wrapping if the end of the string has been
+			reached. */
+			xNextChar += xReceivedLength;
+			if( xNextChar >= xStringLength )
+			{
+				xNextChar = 0;
+			}
+		}
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvEchoClient( void *pvParameters )
+{
+size_t xSendLength = 0, ux;
+char *pcStringToSend, *pcStringReceived, cNextChar = sbASCII_SPACE;
+const TickType_t xTicksToWait = pdMS_TO_TICKS( 50 );
+StreamBufferHandle_t xTempStreamBuffer;
+
+/* The task's priority is used as an index into the loop counters used to
+indicate this task is still running. */
+UBaseType_t uxIndex = uxTaskPriorityGet( NULL );
+
+/* Pointers to the client and server stream buffers are passed into this task
+using the task's parameter. */
+EchoStreamBuffers_t *pxStreamBuffers = ( EchoStreamBuffers_t * ) pvParameters;
+
+	/* Prevent compiler warnings. */
+	( void ) pvParameters;
+
+	/* Create the buffer into which strings to send to the server will be
+	created, and the buffer into which strings echoed back from the server will
+	be copied. */
+	pcStringToSend = ( char * ) pvPortMalloc( sbSTREAM_BUFFER_LENGTH_BYTES );
+	pcStringReceived = ( char * ) pvPortMalloc( sbSTREAM_BUFFER_LENGTH_BYTES );
+
+	configASSERT( pcStringToSend );
+	configASSERT( pcStringReceived );
+
+	for( ;; )
+	{
+		/* Generate the length of the next string to send. */
+		xSendLength++;
+
+		/* The stream buffer is being used to hold variable length data, so
+		each data item requires sizeof( size_t ) bytes to hold the data's
+		length, hence the sizeof() in the if() condition below. */
+		if( xSendLength > ( sbSTREAM_BUFFER_LENGTH_BYTES - sizeof( size_t ) ) )
+		{
+			/* Back to a string length of 1. */
+			xSendLength = sizeof( char );
+		}
+
+		memset( pcStringToSend, 0x00, sbSTREAM_BUFFER_LENGTH_BYTES );
+
+		for( ux = 0; ux < xSendLength; ux++ )
+		{
+			pcStringToSend[ ux ] = cNextChar;
+
+			cNextChar++;
+
+			if( cNextChar > sbASCII_TILDA )
+			{
+				cNextChar = sbASCII_SPACE;
+			}
+		}
+
+		/* Send the generated string to the buffer. */
+		do
+		{
+			ux = xStreamBufferSend( pxStreamBuffers->xEchoClientBuffer, ( void * ) pcStringToSend, xSendLength, xTicksToWait );
+
+		} while( ux == 0 );
+
+		/* Wait for the string to be echoed back. */
+		memset( pcStringReceived, 0x00, sbSTREAM_BUFFER_LENGTH_BYTES );
+		xStreamBufferReceive( pxStreamBuffers->xEchoServerBuffer, ( void * ) pcStringReceived, xSendLength, portMAX_DELAY );
+
+		prvCheckExpectedState( strcmp( pcStringToSend, pcStringReceived ) == 0 );
+
+		/* Maintain a count of the number of times this code executes so a
+		check task can determine if this task is still functioning as
+		expected or not.  As there are two client tasks, and the priorities
+		used are 0 and 1, the task's priority is used as an index into the
+		loop count array. */
+		ulEchoLoopCounters[ uxIndex ]++;
+
+		/* This stream buffer is just created and deleted to ensure no memory
+		leaks. */
+		xTempStreamBuffer = xStreamBufferCreate( sbSTREAM_BUFFER_LENGTH_BYTES, sbTRIGGER_LEVEL_1 );
+		prvSingleTaskTests( xTempStreamBuffer );
+		vStreamBufferDelete( xTempStreamBuffer );
+
+		/* The following are tests for a stream buffer of size one. */
+		/* Create a buffer of size one. */
+		xTempStreamBuffer = xStreamBufferCreate( sbSTREAM_BUFFER_LENGTH_ONE, sbTRIGGER_LEVEL_1 );
+		/* Ensure that the buffer was created successfully. */
+		configASSERT( xTempStreamBuffer );
+
+		/* Send one byte to the buffer. */
+		ux = xStreamBufferSend( xTempStreamBuffer, ( void * ) pcStringToSend, ( size_t ) 1, sbDONT_BLOCK );
+		/* Ensure that the byte was sent successfully. */
+		configASSERT( ux == 1 );
+		/* Try sending another byte to the buffer. */
+		ux = xStreamBufferSend( xTempStreamBuffer, ( void * ) pcStringToSend, ( size_t ) 1, sbDONT_BLOCK );
+		/* Make sure that send failed as the buffer is full. */
+		configASSERT( ux == 0 );
+
+		/* Receive one byte from the buffer. */
+		memset( pcStringReceived, 0x00, sbSTREAM_BUFFER_LENGTH_BYTES );
+		ux = xStreamBufferReceive( xTempStreamBuffer, ( void * ) pcStringReceived, ( size_t ) 1, sbDONT_BLOCK );
+		/* Ensure that the receive was successful. */
+		configASSERT( ux == 1 );
+		/* Ensure that the correct data was received. */
+		configASSERT( pcStringToSend[ 0 ] == pcStringReceived[ 0 ] );
+		/* Try receiving another byte from the buffer. */
+		ux = xStreamBufferReceive( xTempStreamBuffer, ( void * ) pcStringReceived, ( size_t ) 1, sbDONT_BLOCK );
+		/* Ensure that the receive failed as the buffer is empty. */
+		configASSERT( ux == 0 );
+
+		/* Try sending two bytes to the buffer. Since the size of the
+		 * buffer is one, we must not be able to send more than one. */
+		ux = xStreamBufferSend( xTempStreamBuffer, ( void * ) pcStringToSend, ( size_t ) 2, sbDONT_BLOCK );
+		/* Ensure that only one byte was sent. */
+		configASSERT( ux == 1 );
+
+		/* Try receiving two bytes from the buffer. Since the size of the
+		 * buffer is one, we must not be able to get more than one. */
+		memset( pcStringReceived, 0x00, sbSTREAM_BUFFER_LENGTH_BYTES );
+		ux = xStreamBufferReceive( xTempStreamBuffer, ( void * ) pcStringReceived, ( size_t ) 2, sbDONT_BLOCK );
+		/* Ensure that only one byte was received. */
+		configASSERT( ux == 1 );
+		/* Ensure that the correct data was received. */
+		configASSERT( pcStringToSend[ 0 ] == pcStringReceived[ 0 ] );
+
+		/* Delete the buffer. */
+		vStreamBufferDelete( xTempStreamBuffer );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvEchoServer( void *pvParameters )
+{
+size_t xReceivedLength;
+char *pcReceivedString;
+EchoStreamBuffers_t xStreamBuffers;
+TickType_t xTimeOnEntering;
+const TickType_t xTicksToBlock = pdMS_TO_TICKS( 350UL );
+
+	/* Prevent compiler warnings about unused parameters. */
+	( void ) pvParameters;
+
+	/* Create the stream buffer used to send data from the client to the server,
+	and the stream buffer used to echo the data from the server back to the
+	client. */
+	xStreamBuffers.xEchoClientBuffer = xStreamBufferCreate( sbSTREAM_BUFFER_LENGTH_BYTES, sbTRIGGER_LEVEL_1 );
+	xStreamBuffers.xEchoServerBuffer = xStreamBufferCreate( sbSTREAM_BUFFER_LENGTH_BYTES, sbTRIGGER_LEVEL_1 );
+	configASSERT( xStreamBuffers.xEchoClientBuffer );
+	configASSERT( xStreamBuffers.xEchoServerBuffer );
+
+	/* Create the buffer into which received strings will be copied. */
+	pcReceivedString = ( char * ) pvPortMalloc( sbSTREAM_BUFFER_LENGTH_BYTES );
+	configASSERT( pcReceivedString );
+
+	/* Don't expect to receive anything yet! */
+	xTimeOnEntering = xTaskGetTickCount();
+	xReceivedLength = xStreamBufferReceive( xStreamBuffers.xEchoClientBuffer, ( void * ) pcReceivedString, sbSTREAM_BUFFER_LENGTH_BYTES, xTicksToBlock );
+	prvCheckExpectedState( ( xTaskGetTickCount() - xTimeOnEntering ) >= xTicksToBlock );
+	prvCheckExpectedState( xReceivedLength == 0 );
+
+	/* Now the stream buffers have been created the echo client task can be
+	created.  If this server task has the higher priority then the client task
+	is created at the lower priority - if this server task has the lower
+	priority then the client task is created at the higher priority. */
+	if( uxTaskPriorityGet( NULL ) == sbLOWER_PRIORITY )
+	{
+		xTaskCreate( prvEchoClient, "EchoClient", sbSTACK_SIZE,  ( void * ) &xStreamBuffers, sbHIGHER_PRIORITY, NULL );
+	}
+	else
+	{
+		/* Here prvSingleTaskTests() performs various tests on a stream buffer
+		that was created dynamically. */
+		prvSingleTaskTests( xStreamBuffers.xEchoClientBuffer );
+		xTaskCreate( prvEchoClient, "EchoClient", sbSTACK_SIZE, ( void * ) &xStreamBuffers, sbLOWER_PRIORITY, NULL );
+	}
+
+	for( ;; )
+	{
+		memset( pcReceivedString, 0x00, sbSTREAM_BUFFER_LENGTH_BYTES );
+
+		/* Has any data been sent by the client? */
+		xReceivedLength = xStreamBufferReceive( xStreamBuffers.xEchoClientBuffer, ( void * ) pcReceivedString, sbSTREAM_BUFFER_LENGTH_BYTES, portMAX_DELAY );
+
+		/* Should always receive data as max delay was used. */
+		prvCheckExpectedState( xReceivedLength > 0 );
+
+		/* Echo the received data back to the client. */
+		xStreamBufferSend( xStreamBuffers.xEchoServerBuffer, ( void * ) pcReceivedString, xReceivedLength, portMAX_DELAY );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPeriodicStreamBufferProcessing( void )
+{
+static size_t xNextChar = 0;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+
+	/* Called from the tick interrupt hook.  If the global stream buffer
+	variable is not NULL then the prvInterruptTriggerTest() task expects a byte
+	to be sent to the stream buffer on each tick interrupt. */
+	if( xInterruptStreamBuffer != NULL )
+	{
+		/* One character from the pcDataSentFromInterrupt string is sent on each
+		interrupt.  The task blocked on the stream buffer should not be
+		unblocked until the defined trigger level is hit. */
+		xStreamBufferSendFromISR( xInterruptStreamBuffer, ( const void * ) &( pcDataSentFromInterrupt[ xNextChar ] ), sizeof( char ), &xHigherPriorityTaskWoken );
+
+		if( xNextChar < strlen( pcDataSentFromInterrupt ) )
+		{
+			xNextChar++;
+		}
+	}
+	else
+	{
+		/* Start at the beginning of the string being sent again. */
+		xNextChar = 0;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvInterruptTriggerLevelTest( void *pvParameters )
+{
+StreamBufferHandle_t xStreamBuffer;
+size_t xTriggerLevel = 1, xBytesReceived;
+const size_t xStreamBufferSizeBytes = ( size_t ) 8, xMaxTriggerLevel = ( size_t ) 6, xMinTriggerLevel = ( size_t ) 1;
+const TickType_t xReadBlockTime = 4, xCycleBlockTime = pdMS_TO_TICKS( 100 );
+uint8_t ucRxData[ 8 ];
+BaseType_t xErrorDetected = pdFALSE;
+#ifndef configSTREAM_BUFFER_TRIGGER_LEVEL_TEST_MARGIN
+    const size_t xAllowableMargin = ( size_t ) 0;
+#else
+    const size_t xAllowableMargin = ( size_t ) configSTREAM_BUFFER_TRIGGER_LEVEL_TEST_MARGIN;
+#endif
+
+	/* Remove compiler warning about unused parameter. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		for( xTriggerLevel = xMinTriggerLevel; xTriggerLevel < xMaxTriggerLevel; xTriggerLevel++ )
+		{
+			/* Create the stream buffer that will be used from inside the tick
+			interrupt. */
+			xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
+			configASSERT( xStreamBuffer );
+
+			/* Now the stream buffer has been created it can be assigned to the
+			file scope variable, which will allow the tick interrupt to start
+			using it. */
+			taskENTER_CRITICAL();
+			{
+				xInterruptStreamBuffer = xStreamBuffer;
+			}
+			taskEXIT_CRITICAL();
+
+			xBytesReceived = xStreamBufferReceive( xStreamBuffer, ( void * ) ucRxData, sizeof( ucRxData ), xReadBlockTime );
+
+			/* Set the file scope variable back to NULL so the interrupt doesn't
+			try to use it again. */
+			taskENTER_CRITICAL();
+			{
+				xInterruptStreamBuffer = NULL;
+			}
+			taskEXIT_CRITICAL();
+
+			/* Now check the number of bytes received equals the trigger level,
+			except in the case that the read timed out before the trigger level
+			was reached. */
+			if( xBytesReceived < xTriggerLevel )
+			{
+				/* This should only happen if the trigger level was greater than
+				the block time. */
+				if( xTriggerLevel < xReadBlockTime )
+				{
+					xErrorDetected = pdTRUE;
+				}
+			}
+			else if( ( xBytesReceived - xTriggerLevel ) > xAllowableMargin )
+			{
+				/* A margin may be required here if there are other high priority
+				tasks prevent the task that reads from the message buffer running
+				immediately. */
+				xErrorDetected = pdTRUE;
+			}
+
+			if( xBytesReceived > sizeof( ucRxData ) )
+			{
+				xErrorDetected = pdTRUE;
+			}
+			else if( memcmp( ( void * ) ucRxData, ( const void * ) pcDataSentFromInterrupt, xBytesReceived ) != 0 )
+			{
+				/* Received data didn't match that expected. */
+				xErrorDetected = pdTRUE;
+			}
+
+			if( xErrorDetected == pdFALSE )
+			{
+				/* Increment the cycle counter so the 'check' task knows this test
+				is still running without error. */
+				ulInterruptTriggerCounter++;
+			}
+
+			/* Tidy up ready for the next loop. */
+			vStreamBufferDelete( xStreamBuffer );
+			vTaskDelay( xCycleBlockTime );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xAreStreamBufferTasksStillRunning( void )
+{
+static uint32_t ulLastEchoLoopCounters[ sbNUMBER_OF_ECHO_CLIENTS ] = { 0 };
+static uint32_t ulLastNonBlockingRxCounter = 0;
+static uint32_t ulLastInterruptTriggerCounter = 0;
+BaseType_t x;
+
+	for( x = 0; x < sbNUMBER_OF_ECHO_CLIENTS; x++ )
+	{
+		if( ulLastEchoLoopCounters[ x ] == ulEchoLoopCounters[ x ] )
+		{
+			xErrorStatus = pdFAIL;
+		}
+		else
+		{
+			ulLastEchoLoopCounters[ x ] = ulEchoLoopCounters[ x ];
+		}
+	}
+
+	if( ulNonBlockingRxCounter == ulLastNonBlockingRxCounter )
+	{
+		xErrorStatus = pdFAIL;
+	}
+	else
+	{
+		ulLastNonBlockingRxCounter = ulNonBlockingRxCounter;
+	}
+
+	if( ulLastInterruptTriggerCounter == ulInterruptTriggerCounter )
+	{
+		xErrorStatus = pdFAIL;
+	}
+	else
+	{
+		ulLastInterruptTriggerCounter = ulInterruptTriggerCounter;
+	}
+
+	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	{
+		static uint32_t ulLastSenderLoopCounters[ sbNUMBER_OF_ECHO_CLIENTS ] = { 0 };
+
+		for( x = 0; x < sbNUMBER_OF_SENDER_TASKS; x++ )
+		{
+			if( ulLastSenderLoopCounters[ x ] == ulSenderLoopCounters[ x ] )
+			{
+				xErrorStatus = pdFAIL;
+			}
+			else
+			{
+				ulLastSenderLoopCounters[ x ] = ulSenderLoopCounters[ x ];
+			}
+		}
+	}
+	#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+	return xErrorStatus;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/StreamBufferInterrupt.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/StreamBufferInterrupt.c
new file mode 100644
index 0000000..997d1d7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/StreamBufferInterrupt.c
@@ -0,0 +1,228 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * A simple example that shows a stream buffer being used to pass data from an
+ * interrupt to a task.
+ *
+ * There are two strings, pcStringToSend and pcStringToReceive, where
+ * pcStringToReceive is a substring of pcStringToSend.  The interrupt sends
+ * a few bytes of pcStringToSend to a stream buffer ever few times that it
+ * executes.  A task reads the bytes from the stream buffer, looking for the
+ * substring, and flagging an error if the received data is invalid.
+ */
+
+/* Standard includes. */
+#include "stdio.h"
+#include "string.h"
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "stream_buffer.h"
+
+/* Demo app includes. */
+#include "StreamBufferInterrupt.h"
+
+#define sbiSTREAM_BUFFER_LENGTH_BYTES		( ( size_t ) 100 )
+#define sbiSTREAM_BUFFER_TRIGGER_LEVEL_10	( ( BaseType_t ) 10 )
+
+/*-----------------------------------------------------------*/
+
+/* Implements the task that receives a stream of bytes from the interrupt. */
+static void prvReceivingTask( void *pvParameters );
+
+/*-----------------------------------------------------------*/
+
+/* The stream buffer that is used to send data from an interrupt to the task. */
+static StreamBufferHandle_t xStreamBuffer = NULL;
+
+/* The string that is sent from the interrupt to the task four bytes at a
+time.  Must be multiple of 4 bytes long as the ISR sends 4 bytes at a time*/
+static const char * pcStringToSend = "_____Hello FreeRTOS_____";
+
+/* The string to task is looking for, which must be a substring of
+pcStringToSend. */
+static const char * pcStringToReceive = "Hello FreeRTOS";
+
+/* Set to pdFAIL if anything unexpected happens. */
+static BaseType_t xDemoStatus = pdPASS;
+
+/* Incremented each time pcStringToReceive is correctly received, provided no
+errors have occurred.  Used so the check task can check this task is still
+running as expected. */
+static uint32_t ulCycleCount = 0;
+
+/*-----------------------------------------------------------*/
+
+void vStartStreamBufferInterruptDemo( void )
+{
+	/* Create the stream buffer that sends data from the interrupt to the
+	task, and create the task. */
+	xStreamBuffer = xStreamBufferCreate( /* The buffer length in bytes. */
+										 sbiSTREAM_BUFFER_LENGTH_BYTES,
+										 /* The stream buffer's trigger level. */
+										 sbiSTREAM_BUFFER_TRIGGER_LEVEL_10 );
+
+	xTaskCreate( prvReceivingTask, /* The function that implements the task. */
+				 "StrIntRx",	   /* Human readable name for the task. */
+				 configMINIMAL_STACK_SIZE,	/* Stack size (in words!). */
+				 NULL,			   /* Task parameter is not used. */
+				 tskIDLE_PRIORITY + 2, /* The priority at which the task is created. */
+				 NULL );		   /* No use for the task handle. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvReceivingTask( void *pvParameters )
+{
+char cRxBuffer[ 20 ];
+BaseType_t xNextByte = 0;
+
+	/* Remove warning about unused parameters. */
+	( void ) pvParameters;
+
+	/* Make sure the string will fit in the Rx buffer, including the NULL
+	terminator. */
+	configASSERT( sizeof( cRxBuffer ) > strlen( pcStringToReceive ) );
+
+	/* Make sure the stream buffer has been created. */
+	configASSERT( xStreamBuffer != NULL );
+
+	/* Start with the Rx buffer in a known state. */
+	memset( cRxBuffer, 0x00, sizeof( cRxBuffer ) );
+
+	for( ;; )
+	{
+		/* Keep receiving characters until the end of the string is received.
+		Note:  An infinite block time is used to simplify the example.  Infinite
+		block times are not recommended in production code as they do not allow
+		for error recovery. */
+		xStreamBufferReceive( /* The stream buffer data is being received from. */
+							  xStreamBuffer,
+							  /* Where to place received data. */
+							  ( void * ) &( cRxBuffer[ xNextByte ] ),
+							  /* The number of bytes to receive. */
+							  sizeof( char ),
+							  /* The time to wait for the next data if the buffer
+							  is empty. */
+							  portMAX_DELAY );
+
+		/* If xNextByte is 0 then this task is looking for the start of the
+		string, which is 'H'. */
+		if( xNextByte == 0 )
+		{
+			if( cRxBuffer[ xNextByte ] == 'H' )
+			{
+				/* The start of the string has been found.  Now receive
+				characters until the end of the string is found. */
+				xNextByte++;
+			}
+		}
+		else
+		{
+			/* Receiving characters while looking for the end of the string,
+			which is an 'S'. */
+			if( cRxBuffer[ xNextByte ] == 'S' )
+			{
+				/* The string has now been received.  Check its validity. */
+				if( strcmp( cRxBuffer, pcStringToReceive ) != 0 )
+				{
+					xDemoStatus = pdFAIL;
+				}
+
+				/* Return to start looking for the beginning of the string
+				again. */
+				memset( cRxBuffer, 0x00, sizeof( cRxBuffer ) );
+				xNextByte = 0;
+
+				/* Increment the cycle count as an indication to the check task
+				that this demo is still running. */
+				if( xDemoStatus == pdPASS )
+				{
+					ulCycleCount++;
+				}
+			}
+			else
+			{
+				/* Receive the next character the next time around, while
+				continuing to look for the end of the string. */
+				xNextByte++;
+
+				configASSERT( ( size_t ) xNextByte < sizeof( cRxBuffer ) );
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vBasicStreamBufferSendFromISR( void )
+{
+static size_t xNextByteToSend = 0;
+const BaseType_t xCallsBetweenSends = 100, xBytesToSend = 4;
+static BaseType_t xCallCount = 0;
+
+	/* Is it time to write to the stream buffer again? */
+	xCallCount++;
+	if( xCallCount > xCallsBetweenSends )
+	{
+		xCallCount = 0;
+
+		/* Send the next four bytes to the stream buffer. */
+		xStreamBufferSendFromISR( xStreamBuffer,
+								  ( const void * ) ( pcStringToSend + xNextByteToSend ),
+								  xBytesToSend,
+								  NULL );
+
+		/* Send the next four bytes the next time around, wrapping to the start
+		of the string if necessary. */
+		xNextByteToSend += xBytesToSend;
+
+		if( xNextByteToSend >= strlen( pcStringToSend ) )
+		{
+			xNextByteToSend = 0;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsInterruptStreamBufferDemoStillRunning( void )
+{
+uint32_t ulLastCycleCount = 0;
+
+	/* Check the demo is still running. */
+	if( ulLastCycleCount == ulCycleCount )
+	{
+		xDemoStatus = pdFAIL;
+	}
+	else
+	{
+		ulLastCycleCount = ulCycleCount;
+	}
+
+	return xDemoStatus;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/TaskNotify.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/TaskNotify.c
new file mode 100644
index 0000000..8307323
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/TaskNotify.c
@@ -0,0 +1,693 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*
+ * Tests the behaviour of direct task notifications.
+ */
+
+/* Standard includes. */
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+
+/* Demo program include files. */
+#include "TaskNotify.h"
+
+/* Allow parameters to be overridden on a demo by demo basis. */
+#ifndef notifyNOTIFIED_TASK_STACK_SIZE
+	#define notifyNOTIFIED_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
+#endif
+
+#define notifyTASK_PRIORITY		( tskIDLE_PRIORITY )
+#define notifyUINT32_MAX	( ( uint32_t ) 0xffffffff )
+#define notifySUSPENDED_TEST_TIMER_PERIOD pdMS_TO_TICKS( 50 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Implementation of the task that gets notified.
+ */
+static void prvNotifiedTask( void *pvParameters );
+
+/*
+ * Performs a few initial tests that can be done prior to creating the second
+ * task.
+ */
+static void prvSingleTaskTests( void );
+
+/*
+ * Software timer callback function from which xTaskNotify() is called.
+ */
+static void prvNotifyingTimer( TimerHandle_t xTimer );
+
+/*
+ * Utility function to create pseudo random numbers.
+ */
+static UBaseType_t prvRand( void );
+
+/*
+ * Callback for a timer that is used during preliminary testing.  The timer
+ * tests the behaviour when 1: a task waiting for a notification is suspended
+ * and then resumed without ever receiving a notification, and 2: when a task
+ * waiting for a notification receives a notification while it is suspended.
+ */
+static void prvSuspendedTaskTimerTestCallback( TimerHandle_t xExpiredTimer );
+
+/*-----------------------------------------------------------*/
+
+/* Used to latch errors during the test's execution. */
+static BaseType_t xErrorStatus = pdPASS;
+
+/* Used to ensure the task has not stalled. */
+static volatile uint32_t ulNotifyCycleCount = 0;
+
+/* The handle of the task that receives the notifications. */
+static TaskHandle_t xTaskToNotify = NULL;
+
+/* Used to count the notifications sent to the task from a software timer and
+the number of notifications received by the task from the software timer.  The
+two should stay synchronised. */
+static uint32_t ulTimerNotificationsReceived = 0UL, ulTimerNotificationsSent = 0UL;
+
+/* The timer used to notify the task. */
+static TimerHandle_t xTimer = NULL;
+
+/* Used by the pseudo random number generating function. */
+static size_t uxNextRand = 0;
+
+/*-----------------------------------------------------------*/
+
+void vStartTaskNotifyTask( void  )
+{
+	/* Create the task that performs some tests by itself, then loops around
+	being notified by both a software timer and an interrupt. */
+	xTaskCreate( prvNotifiedTask, /* Function that implements the task. */
+				 "Notified", /* Text name for the task - for debugging only - not used by the kernel. */
+				 notifyNOTIFIED_TASK_STACK_SIZE, /* Task's stack size in words, not bytes!. */
+				 NULL, /* Task parameter, not used in this case. */
+				 notifyTASK_PRIORITY, /* Task priority, 0 is the lowest. */
+				 &xTaskToNotify ); /* Used to pass a handle to the task out is needed, otherwise set to NULL. */
+
+	/* Pseudo seed the random number generator. */
+	uxNextRand = ( size_t ) prvRand;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSingleTaskTests( void )
+{
+const TickType_t xTicksToWait = pdMS_TO_TICKS( 100UL );
+BaseType_t xReturned;
+uint32_t ulNotifiedValue, ulLoop, ulNotifyingValue, ulPreviousValue, ulExpectedValue;
+TickType_t xTimeOnEntering;
+const uint32_t ulFirstNotifiedConst = 100001UL, ulSecondNotifiedValueConst = 5555UL, ulMaxLoops = 5UL;
+const uint32_t ulBit0 = 0x01UL, ulBit1 = 0x02UL;
+TimerHandle_t xSingleTaskTimer;
+
+
+	/* ------------------------------------------------------------------------
+	Check blocking when there are no notifications. */
+	xTimeOnEntering = xTaskGetTickCount();
+	xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, xTicksToWait );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+
+	/* Should have blocked for the entire block time. */
+	if( ( xTaskGetTickCount() - xTimeOnEntering ) < xTicksToWait )
+	{
+		xErrorStatus = pdFAIL;
+	}
+	configASSERT( xReturned == pdFAIL );
+	configASSERT( ulNotifiedValue == 0UL );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+	( void ) ulNotifiedValue;
+
+
+
+
+	/* ------------------------------------------------------------------------
+	Check no blocking when notifications are pending.  First notify itself -
+	this would not be a normal thing to do and is done here for test purposes
+	only. */
+	xReturned = xTaskNotifyAndQuery( xTaskToNotify, ulFirstNotifiedConst, eSetValueWithoutOverwrite, &ulPreviousValue );
+
+	/* Even through the 'without overwrite' action was used the update should
+	have been successful. */
+	configASSERT( xReturned == pdPASS );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+
+	/* No bits should have been pending previously. */
+	configASSERT( ulPreviousValue == 0 );
+	( void ) ulPreviousValue;
+
+	/* The task should now have a notification pending, and so not time out. */
+	xTimeOnEntering = xTaskGetTickCount();
+	xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, xTicksToWait );
+
+	if( ( xTaskGetTickCount() - xTimeOnEntering ) >= xTicksToWait )
+	{
+		xErrorStatus = pdFAIL;
+	}
+
+	/* The task should have been notified, and the notified value should
+	be equal to ulFirstNotifiedConst. */
+	configASSERT( xReturned == pdPASS );
+	configASSERT( ulNotifiedValue == ulFirstNotifiedConst );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+	( void ) ulNotifiedValue;
+
+	/* Incremented to show the task is still running. */
+	ulNotifyCycleCount++;
+
+
+
+
+
+	/*-------------------------------------------------------------------------
+	Check the non-overwriting functionality.  The notification is done twice
+	using two different notification values.  The action says don't overwrite so
+	only the first notification should pass and the value read back should also
+	be that used with the first notification. */
+	xReturned = xTaskNotify( xTaskToNotify, ulFirstNotifiedConst, eSetValueWithoutOverwrite );
+	configASSERT( xReturned == pdPASS );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+
+	xReturned = xTaskNotify( xTaskToNotify, ulSecondNotifiedValueConst, eSetValueWithoutOverwrite );
+	configASSERT( xReturned == pdFAIL );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+
+	/* Waiting for the notification should now return immediately so a block
+	time of zero is used. */
+	xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
+
+	configASSERT( xReturned == pdPASS );
+	configASSERT( ulNotifiedValue == ulFirstNotifiedConst );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+	( void ) ulNotifiedValue;
+
+
+
+
+
+	/*-------------------------------------------------------------------------
+	Do the same again, only this time use the overwriting version.  This time
+	both notifications should pass, and the value written the second time should
+	overwrite the value written the first time, and so be the value that is read
+	back. */
+	xReturned = xTaskNotify( xTaskToNotify, ulFirstNotifiedConst, eSetValueWithOverwrite );
+	configASSERT( xReturned == pdPASS );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+	xReturned = xTaskNotify( xTaskToNotify, ulSecondNotifiedValueConst, eSetValueWithOverwrite );
+	configASSERT( xReturned == pdPASS );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+	xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
+	configASSERT( xReturned == pdPASS );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+	configASSERT( ulNotifiedValue == ulSecondNotifiedValueConst );
+	( void ) ulNotifiedValue;
+
+
+
+
+	/*-------------------------------------------------------------------------
+	Check notifications with no action pass without updating the value.  Even
+	though ulFirstNotifiedConst is used as the value the value read back should
+	remain at ulSecondNotifiedConst. */
+	xReturned = xTaskNotify( xTaskToNotify, ulFirstNotifiedConst, eNoAction );
+	configASSERT( xReturned == pdPASS );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+	xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
+	configASSERT( ulNotifiedValue == ulSecondNotifiedValueConst );
+	( void ) ulNotifiedValue; /* In case configASSERT() is not defined. */
+
+
+
+
+	/*-------------------------------------------------------------------------
+	Check incrementing values.  Send ulMaxLoop increment notifications, then
+	ensure the received value is as expected - which should be
+	ulSecondNotificationValueConst plus how ever many times to loop iterated. */
+	for( ulLoop = 0; ulLoop < ulMaxLoops; ulLoop++ )
+	{
+		xReturned = xTaskNotify( xTaskToNotify, 0, eIncrement );
+		configASSERT( xReturned == pdPASS );
+		( void ) xReturned; /* In case configASSERT() is not defined. */
+	}
+
+	xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
+	configASSERT( xReturned == pdPASS );
+	configASSERT( ulNotifiedValue == ( ulSecondNotifiedValueConst + ulMaxLoops ) );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+	( void ) ulNotifiedValue;
+
+	/* Should not be any notifications pending now. */
+	xReturned = xTaskNotifyWait( 0, 0, &ulNotifiedValue, 0 );
+	configASSERT( xReturned == pdFAIL );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+	( void ) ulNotifiedValue;
+
+
+
+
+	/*-------------------------------------------------------------------------
+	Check all bits can be set by notifying the task with one additional bit	set
+	on each notification, and exiting the loop when all the bits are found to be
+	set.  As there are 32-bits the loop should execute 32 times before all the
+	bits are found to be set. */
+	ulNotifyingValue = 0x01;
+	ulLoop = 0;
+
+	/* Start with all bits clear. */
+	xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
+
+	do
+	{
+		/* Set the next bit in the task's notified value. */
+		xTaskNotify( xTaskToNotify, ulNotifyingValue, eSetBits );
+
+		/* Wait for the notified value - which of course will already be
+		available.  Don't clear the bits on entry or exit as this loop is exited
+		when all the bits are set. */
+		xReturned = xTaskNotifyWait( 0, 0, &ulNotifiedValue, 0 );
+		configASSERT( xReturned == pdPASS );
+		( void ) xReturned; /* In case configASSERT() is not defined. */
+
+		ulLoop++;
+
+		/* Use the next bit on the next iteration around this loop. */
+		ulNotifyingValue <<= 1UL;
+
+	} while ( ulNotifiedValue != notifyUINT32_MAX );
+
+	/* As a 32-bit value was used the loop should have executed 32 times before
+	all the bits were set. */
+	configASSERT( ulLoop == 32 );
+
+
+
+
+	/*-------------------------------------------------------------------------
+	Check bits are cleared on entry but not on exit when a notification fails
+	to arrive before timing out - both with and without a timeout value.  Wait
+	for the notification again - but this time it is not given by anything and
+	should return pdFAIL.  The parameters are set to clear bit zero on entry and
+	bit one on exit.  As no notification was received only the bit cleared on
+	entry should actually get cleared. */
+	xReturned = xTaskNotifyWait( ulBit0, ulBit1, &ulNotifiedValue, xTicksToWait );
+	configASSERT( xReturned == pdFAIL );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+
+	/* Notify the task with no action so as not to update the bits even though
+	notifyUINT32_MAX is used as the notification value. */
+	xTaskNotify( xTaskToNotify, notifyUINT32_MAX, eNoAction );
+
+	/* Reading back the value should should find bit 0 is clear, as this was
+	cleared on entry, but bit 1 is not clear as it will not have been cleared on
+	exit as no notification was received. */
+	xReturned = xTaskNotifyWait( 0x00UL, 0x00UL, &ulNotifiedValue, 0 );
+	configASSERT( xReturned == pdPASS );
+	configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~ulBit0 ) );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+
+
+
+
+
+	/*-------------------------------------------------------------------------
+	Now try clearing the bit on exit.  For that to happen a notification must be
+	received, so the task is notified first. */
+	xTaskNotify( xTaskToNotify, 0, eNoAction );
+	xTaskNotifyWait( 0x00, ulBit1, &ulNotifiedValue, 0 );
+
+	/* However as the bit is cleared on exit, after the returned notification
+	value is set, the returned notification value should not have the bit
+	cleared... */
+	configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~ulBit0 ) );
+
+	/* ...but reading the value back again should find that the bit was indeed
+	cleared internally.  The returned value should be pdFAIL however as nothing
+	has notified the task in the mean time. */
+	xReturned = xTaskNotifyWait( 0x00, 0x00, &ulNotifiedValue, 0 );
+	configASSERT( xReturned == pdFAIL );
+	configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~( ulBit0 | ulBit1 ) ) );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+
+
+
+
+	/*-------------------------------------------------------------------------
+	Now try querying the previous value while notifying a task. */
+	xTaskNotifyAndQuery( xTaskToNotify, 0x00, eSetBits, &ulPreviousValue );
+	configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~( ulBit0 | ulBit1 ) ) );
+
+	/* Clear all bits. */
+	xTaskNotifyWait( 0x00, notifyUINT32_MAX, &ulNotifiedValue, 0 );
+	xTaskNotifyAndQuery( xTaskToNotify, 0x00, eSetBits, &ulPreviousValue );
+	configASSERT( ulPreviousValue == 0 );
+
+	ulExpectedValue = 0;
+	for( ulLoop = 0x01; ulLoop < 0x80UL; ulLoop <<= 1UL )
+	{
+		/* Set the next bit up, and expect to receive the last bits set (so
+		the previous value will not yet have the bit being set this time
+		around). */
+		xTaskNotifyAndQuery( xTaskToNotify, ulLoop, eSetBits, &ulPreviousValue );
+		configASSERT( ulExpectedValue == ulPreviousValue );
+		ulExpectedValue |= ulLoop;
+	}
+
+
+
+	/* ------------------------------------------------------------------------
+	Clear the previous notifications. */
+	xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
+
+	/* The task should not have any notifications pending, so an attempt to clear
+	the notification state should fail. */
+	configASSERT( xTaskNotifyStateClear( NULL ) == pdFALSE );
+
+	/* Get the task to notify itself.  This is not a normal thing to do, and is
+	only done here for test purposes. */
+	xTaskNotifyAndQuery( xTaskToNotify, ulFirstNotifiedConst, eSetValueWithoutOverwrite, &ulPreviousValue );
+
+	/* Now the notification state should be eNotified, so it should now be
+	possible to clear the notification state. */
+	configASSERT( xTaskNotifyStateClear( NULL ) == pdTRUE );
+	configASSERT( xTaskNotifyStateClear( NULL ) == pdFALSE );
+
+
+
+	/* ------------------------------------------------------------------------
+	Create a timer that will try notifying this task while it is suspended. */
+	xSingleTaskTimer = xTimerCreate( "SingleNotify", notifySUSPENDED_TEST_TIMER_PERIOD, pdFALSE, NULL, prvSuspendedTaskTimerTestCallback );
+	configASSERT( xSingleTaskTimer );
+
+	/* Incremented to show the task is still running. */
+	ulNotifyCycleCount++;
+
+	/* Ensure no notifications are pending. */
+	xTaskNotifyWait( notifyUINT32_MAX, 0, NULL, 0 );
+
+	/* Raise the task's priority so it can suspend itself before the timer
+	expires. */
+	vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
+
+	/* Start the timer that will try notifying this task while it is
+	suspended, then wait for a notification.  The first time the callback
+	executes the timer will suspend the task, then resume the task, without
+	ever sending a notification to the task. */
+	ulNotifiedValue = 0;
+	xTimerStart( xSingleTaskTimer, portMAX_DELAY );
+
+	/* Check a notification is not received. */
+	xReturned = xTaskNotifyWait( 0, 0, &ulNotifiedValue, portMAX_DELAY );
+	configASSERT( xReturned == pdFALSE );
+	configASSERT( ulNotifiedValue == 0 );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+
+	/* Incremented to show the task is still running. */
+	ulNotifyCycleCount++;
+
+	/* Start the timer that will try notifying this task while it is
+	suspended, then wait for a notification.  The second time the callback
+	executes the timer will suspend the task, notify the task, then resume the
+	task (previously it was suspended and resumed without being notified). */
+	xTimerStart( xSingleTaskTimer, portMAX_DELAY );
+
+	/* Check a notification is received. */
+	xReturned = xTaskNotifyWait( 0, 0, &ulNotifiedValue, portMAX_DELAY );
+	configASSERT( xReturned == pdPASS );
+	( void ) xReturned; /* In case configASSERT() is not defined. */
+	configASSERT( ulNotifiedValue != 0 );
+
+	/* Return the task to its proper priority and delete the timer as it is
+	not used again. */
+	vTaskPrioritySet( NULL, notifyTASK_PRIORITY );
+	xTimerDelete( xSingleTaskTimer, portMAX_DELAY );
+
+	/* Incremented to show the task is still running. */
+	ulNotifyCycleCount++;
+
+	/* Leave all bits cleared. */
+	xTaskNotifyWait( notifyUINT32_MAX, 0, NULL, 0 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSuspendedTaskTimerTestCallback( TimerHandle_t xExpiredTimer )
+{
+static uint32_t ulCallCount = 0;
+
+	/* Remove compiler warnings about unused parameters. */
+	( void ) xExpiredTimer;
+
+	/* Callback for a timer that is used during preliminary testing.  The timer
+	tests the behaviour when 1: a task waiting for a notification is suspended
+	and then resumed without ever receiving a notification, and 2: when a task
+	waiting for a notification receives a notification while it is suspended. */
+
+	if( ulCallCount == 0 )
+	{
+		vTaskSuspend( xTaskToNotify );
+		configASSERT( eTaskGetState( xTaskToNotify ) == eSuspended );
+		vTaskResume( xTaskToNotify );
+	}
+	else
+	{
+		vTaskSuspend( xTaskToNotify );
+
+		/* Sending a notification while the task is suspended should pass, but
+		not cause the task to resume.  ulCallCount is just used as a convenient
+		non-zero value. */
+		xTaskNotify( xTaskToNotify, ulCallCount, eSetValueWithOverwrite );
+
+		/* Make sure giving the notification didn't resume the task. */
+		configASSERT( eTaskGetState( xTaskToNotify ) == eSuspended );
+
+		vTaskResume( xTaskToNotify );
+	}
+
+	ulCallCount++;
+}
+/*-----------------------------------------------------------*/
+
+static void prvNotifyingTimer( TimerHandle_t xNotUsed )
+{
+	( void ) xNotUsed;
+
+	xTaskNotifyGive( xTaskToNotify );
+
+	/* This value is also incremented from an interrupt. */
+	taskENTER_CRITICAL();
+	{
+		ulTimerNotificationsSent++;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+static void prvNotifiedTask( void *pvParameters )
+{
+const TickType_t xMaxPeriod = pdMS_TO_TICKS( 90 ), xMinPeriod = pdMS_TO_TICKS( 10 ), xDontBlock = 0;
+TickType_t xPeriod;
+const uint32_t ulCyclesToRaisePriority = 50UL;
+
+	/* Remove compiler warnings about unused parameters. */
+	( void ) pvParameters;
+
+	/* Run a few tests that can be done from a single task before entering the
+	main loop. */
+	prvSingleTaskTests();
+
+	/* Create the software timer that is used to send notifications to this
+	task.  Notifications are also received from an interrupt. */
+	xTimer = xTimerCreate( "Notifier", xMaxPeriod, pdFALSE, NULL, prvNotifyingTimer );
+
+	for( ;; )
+	{
+		/* Start the timer again with a different period.  Sometimes the period
+		will be higher than the task's block time, sometimes it will be lower
+		than the task's block time. */
+		xPeriod = prvRand() % xMaxPeriod;
+		if( xPeriod < xMinPeriod )
+		{
+			xPeriod = xMinPeriod;
+		}
+
+		/* Change the timer period and start the timer. */
+		xTimerChangePeriod( xTimer, xPeriod, portMAX_DELAY );
+
+		/* Block waiting for the notification again with a different period.
+		Sometimes the period will be higher than the task's block time,
+		sometimes it will be lower than the task's block time. */
+		xPeriod = prvRand() % xMaxPeriod;
+		if( xPeriod < xMinPeriod )
+		{
+			xPeriod = xMinPeriod;
+		}
+
+		/* Block to wait for a notification but without clearing the
+		notification count, so only add one to the count of received
+		notifications as any other notifications will remain pending. */
+		if( ulTaskNotifyTake( pdFALSE, xPeriod ) != 0 )
+		{
+			ulTimerNotificationsReceived++;
+		}
+
+
+		/* Take a notification without clearing again, but this time without a
+		block time specified. */
+		if( ulTaskNotifyTake( pdFALSE, xDontBlock ) != 0 )
+		{
+			ulTimerNotificationsReceived++;
+		}
+
+		/* Wait for the next notification from the timer, clearing all
+		notifications if one is received, so this time adding the total number
+		of notifications that were pending as none will be left pending after
+		the function call. */
+		ulTimerNotificationsReceived += ulTaskNotifyTake( pdTRUE, xPeriod );
+
+		/* Occasionally raise the priority of the task being notified to test
+		the path where the task is notified from an ISR and becomes the highest
+		priority ready state task, but the pxHigherPriorityTaskWoken parameter
+		is NULL (which it is in the tick hook that sends notifications to this
+		task). */
+		if( ( ulNotifyCycleCount % ulCyclesToRaisePriority ) == 0 )
+		{
+			vTaskPrioritySet( xTaskToNotify, configMAX_PRIORITIES - 1 );
+
+			/* Wait for the next notification again, clearing all notifications
+			if one is received, but this time blocking indefinitely. */
+			ulTimerNotificationsReceived += ulTaskNotifyTake( pdTRUE, portMAX_DELAY );
+
+			/* Reset the priority. */
+			vTaskPrioritySet( xTaskToNotify, notifyTASK_PRIORITY );
+		}
+		else
+		{
+			/* Wait for the next notification again, clearing all notifications
+			if one is received, but this time blocking indefinitely. */
+			ulTimerNotificationsReceived += ulTaskNotifyTake( pdTRUE, portMAX_DELAY );
+		}
+
+		/* Incremented to show the task is still running. */
+		ulNotifyCycleCount++;
+	}
+}
+/*-----------------------------------------------------------*/
+
+void xNotifyTaskFromISR( void )
+{
+static BaseType_t xCallCount = 0, xAPIToUse = 0;
+const BaseType_t xCallInterval = pdMS_TO_TICKS( 50 );
+uint32_t ulPreviousValue;
+const uint32_t ulUnexpectedValue = 0xff;
+
+	/* The task performs some tests before starting the timer that gives the
+	notification from this interrupt.  If the timer has not been created yet
+	then the initial tests have not yet completed and the notification should
+	not be sent. */
+	if( xTimer != NULL )
+	{
+		xCallCount++;
+
+		if( xCallCount >= xCallInterval )
+		{
+			/* It is time to 'give' the notification again. */
+			xCallCount = 0;
+
+			/* Test using both vTaskNotifyGiveFromISR(), xTaskNotifyFromISR()
+			and xTaskNotifyAndQueryFromISR(). */
+			switch( xAPIToUse )
+			{
+				case 0:	vTaskNotifyGiveFromISR( xTaskToNotify, NULL );
+						xAPIToUse++;
+						break;
+
+				case 1:	xTaskNotifyFromISR( xTaskToNotify, 0, eIncrement, NULL );
+						xAPIToUse++;
+						break;
+
+				case 2: ulPreviousValue = ulUnexpectedValue;
+						xTaskNotifyAndQueryFromISR( xTaskToNotify, 0, eIncrement, &ulPreviousValue, NULL );
+						configASSERT( ulPreviousValue != ulUnexpectedValue );
+						xAPIToUse = 0;
+						break;
+
+				default:/* Should never get here!. */
+						break;
+			}
+
+			ulTimerNotificationsSent++;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* This is called to check the created tasks are still running and have not
+detected any errors. */
+BaseType_t xAreTaskNotificationTasksStillRunning( void )
+{
+static uint32_t ulLastNotifyCycleCount = 0;
+const uint32_t ulMaxSendReceiveDeviation = 5UL;
+
+	/* Check the cycle count is still incrementing to ensure the task is still
+	actually running. */
+	if( ulLastNotifyCycleCount == ulNotifyCycleCount )
+	{
+		xErrorStatus = pdFAIL;
+	}
+	else
+	{
+		ulLastNotifyCycleCount = ulNotifyCycleCount;
+	}
+
+	/* Check the count of 'takes' from the software timer is keeping track with
+	the amount of 'gives'. */
+	if( ulTimerNotificationsSent > ulTimerNotificationsReceived )
+	{
+		if( ( ulTimerNotificationsSent - ulTimerNotificationsReceived ) > ulMaxSendReceiveDeviation )
+		{
+			xErrorStatus = pdFAIL;
+		}
+	}
+
+	return xErrorStatus;
+}
+/*-----------------------------------------------------------*/
+
+static UBaseType_t prvRand( void )
+{
+const size_t uxMultiplier = ( size_t ) 0x015a4e35, uxIncrement = ( size_t ) 1;
+
+	/* Utility function to generate a pseudo random number. */
+	uxNextRand = ( uxMultiplier * uxNextRand ) + uxIncrement;
+	return( ( uxNextRand >> 16 ) & ( ( size_t ) 0x7fff ) );
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/TimerDemo.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/TimerDemo.c
new file mode 100644
index 0000000..584b63f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/TimerDemo.c
@@ -0,0 +1,1069 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*
+ * Tests the behaviour of timers.  Some timers are created before the scheduler
+ * is started, and some after.
+ */
+
+/* Standard includes. */
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+
+/* Demo program include files. */
+#include "TimerDemo.h"
+
+#if ( configTIMER_TASK_PRIORITY < 1 )
+	#error configTIMER_TASK_PRIORITY must be set to at least 1 for this test/demo to function correctly.
+#endif
+
+#define tmrdemoDONT_BLOCK				( ( TickType_t ) 0 )
+#define tmrdemoONE_SHOT_TIMER_PERIOD	( xBasePeriod * ( TickType_t ) 3 )
+#define tmrdemoNUM_TIMER_RESETS			( ( uint8_t ) 10 )
+
+#ifndef tmrTIMER_TEST_TASK_STACK_SIZE
+	#define tmrTIMER_TEST_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* The callback functions used by the timers.  These each increment a counter
+to indicate which timer has expired.  The auto-reload timers that are used by
+the test task (as opposed to being used from an ISR) all share the same
+prvAutoReloadTimerCallback() callback function, and use the ID of the
+pxExpiredTimer parameter passed into that function to know which counter to
+increment.  The other timers all have their own unique callback function and
+simply increment their counters without using the callback function parameter. */
+static void prvAutoReloadTimerCallback( TimerHandle_t pxExpiredTimer );
+static void prvOneShotTimerCallback( TimerHandle_t pxExpiredTimer );
+static void prvTimerTestTask( void *pvParameters );
+static void prvISRAutoReloadTimerCallback( TimerHandle_t pxExpiredTimer );
+static void prvISROneShotTimerCallback( TimerHandle_t pxExpiredTimer );
+
+/* The test functions used by the timer test task.  These manipulate the auto
+reload and one shot timers in various ways, then delay, then inspect the timers
+to ensure they have behaved as expected. */
+static void prvTest1_CreateTimersWithoutSchedulerRunning( void );
+static void prvTest2_CheckTaskAndTimersInitialState( void );
+static void	prvTest3_CheckAutoReloadExpireRates( void );
+static void prvTest4_CheckAutoReloadTimersCanBeStopped( void );
+static void prvTest5_CheckBasicOneShotTimerBehaviour( void );
+static void prvTest6_CheckAutoReloadResetBehaviour( void );
+static void prvResetStartConditionsForNextIteration( void );
+
+/*-----------------------------------------------------------*/
+
+/* Flag that will be latched to pdFAIL should any unexpected behaviour be
+detected in any of the demo tests. */
+static volatile BaseType_t xTestStatus = pdPASS;
+
+/* Counter that is incremented on each cycle of a test.  This is used to
+detect a stalled task - a test that is no longer running. */
+static volatile uint32_t ulLoopCounter = 0;
+
+/* A set of auto reload timers - each of which use the same callback function.
+The callback function uses the timer ID to index into, and then increment, a
+counter in the ucAutoReloadTimerCounters[] array.  The auto reload timers
+referenced from xAutoReloadTimers[] are used by the prvTimerTestTask task. */
+static TimerHandle_t xAutoReloadTimers[ configTIMER_QUEUE_LENGTH + 1 ] = { 0 };
+static uint8_t ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH + 1 ] = { 0 };
+
+/* The one shot timer is configured to use a callback function that increments
+ucOneShotTimerCounter each time it gets called. */
+static TimerHandle_t xOneShotTimer = NULL;
+static uint8_t ucOneShotTimerCounter = ( uint8_t ) 0;
+
+/* The ISR reload timer is controlled from the tick hook to exercise the timer
+API functions that can be used from an ISR.  It is configured to increment
+ucISRReloadTimerCounter each time its callback function is executed. */
+static TimerHandle_t xISRAutoReloadTimer = NULL;
+static uint8_t ucISRAutoReloadTimerCounter = ( uint8_t ) 0;
+
+/* The ISR one shot timer is controlled from the tick hook to exercise the timer
+API functions that can be used from an ISR.  It is configured to increment
+ucISRReloadTimerCounter each time its callback function is executed. */
+static TimerHandle_t xISROneShotTimer = NULL;
+static uint8_t ucISROneShotTimerCounter = ( uint8_t ) 0;
+
+/* The period of all the timers are a multiple of the base period.  The base
+period is configured by the parameter to vStartTimerDemoTask(). */
+static TickType_t xBasePeriod = 0;
+
+/*-----------------------------------------------------------*/
+
+void vStartTimerDemoTask( TickType_t xBasePeriodIn )
+{
+	/* Start with the timer and counter arrays clear - this is only necessary
+	where the compiler does not clear them automatically on start up. */
+	memset( ucAutoReloadTimerCounters, 0x00, sizeof( ucAutoReloadTimerCounters ) );
+	memset( xAutoReloadTimers, 0x00, sizeof( xAutoReloadTimers ) );
+
+	/* Store the period from which all the timer periods will be generated from
+	(multiples of). */
+	xBasePeriod = xBasePeriodIn;
+
+	/* Create a set of timers for use by this demo/test. */
+	prvTest1_CreateTimersWithoutSchedulerRunning();
+
+	/* Create the task that will control and monitor the timers.  This is
+	created at a lower priority than the timer service task to ensure, as
+	far as it is concerned, commands on timers are actioned immediately
+	(sending a command to the timer service task will unblock the timer service
+	task, which will then preempt this task). */
+	if( xTestStatus != pdFAIL )
+	{
+		xTaskCreate( prvTimerTestTask, "Tmr Tst", tmrTIMER_TEST_TASK_STACK_SIZE, NULL, configTIMER_TASK_PRIORITY - 1, NULL );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvTimerTestTask( void *pvParameters )
+{
+	( void ) pvParameters;
+
+	/* Create a one-shot timer for use later on in this test. */
+	xOneShotTimer = xTimerCreate(	"Oneshot Timer",				/* Text name to facilitate debugging.  The kernel does not use this itself. */
+									tmrdemoONE_SHOT_TIMER_PERIOD,	/* The period for the timer. */
+									pdFALSE,						/* Don't auto-reload - hence a one shot timer. */
+									( void * ) 0,					/* The timer identifier.  Initialise to 0, then increment each time it is called. */
+									prvOneShotTimerCallback );		/* The callback to be called when the timer expires. */
+
+	if( xOneShotTimer == NULL )
+	{
+		xTestStatus = pdFAIL;
+		configASSERT( xTestStatus );
+	}
+
+
+	/* Ensure all the timers are in their expected initial state.  This
+	depends on the timer service task having a higher priority than this task. */
+	prvTest2_CheckTaskAndTimersInitialState();
+
+	for( ;; )
+	{
+		/* Check the auto reload timers expire at the expected/correct rates. */
+		prvTest3_CheckAutoReloadExpireRates();
+
+		/* Check the auto reload timers can be stopped correctly, and correctly
+		report their state. */
+		prvTest4_CheckAutoReloadTimersCanBeStopped();
+
+		/* Check the one shot timer only calls its callback once after it has been
+		started, and that it reports its state correctly. */
+		prvTest5_CheckBasicOneShotTimerBehaviour();
+
+		/* Check timer reset behaviour. */
+		prvTest6_CheckAutoReloadResetBehaviour();
+
+		/* Start the timers again to restart all the tests over again. */
+		prvResetStartConditionsForNextIteration();
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* This is called to check that the created task is still running and has not
+detected any errors. */
+BaseType_t xAreTimerDemoTasksStillRunning( TickType_t xCycleFrequency )
+{
+static uint32_t ulLastLoopCounter = 0UL;
+TickType_t xMaxBlockTimeUsedByTheseTests, xLoopCounterIncrementTimeMax;
+static TickType_t xIterationsWithoutCounterIncrement = ( TickType_t ) 0, xLastCycleFrequency;
+
+	if( xLastCycleFrequency != xCycleFrequency )
+	{
+		/* The cycle frequency has probably become much faster due to an error
+		elsewhere.  Start counting Iterations again. */
+		xIterationsWithoutCounterIncrement = ( TickType_t ) 0;
+		xLastCycleFrequency = xCycleFrequency;
+	}
+
+	/* Calculate the maximum number of times that it is permissible for this
+	function to be called without ulLoopCounter being incremented.  This is
+	necessary because the tests in this file block for extended periods, and the
+	block period might be longer than the time between calls to this function. */
+	xMaxBlockTimeUsedByTheseTests = ( ( TickType_t ) configTIMER_QUEUE_LENGTH ) * xBasePeriod;
+	xLoopCounterIncrementTimeMax = ( xMaxBlockTimeUsedByTheseTests / xCycleFrequency ) + 1;
+
+	/* If the demo task is still running then the loop counter is expected to
+	have incremented every xLoopCounterIncrementTimeMax calls. */
+	if( ulLastLoopCounter == ulLoopCounter )
+	{
+		xIterationsWithoutCounterIncrement++;
+		if( xIterationsWithoutCounterIncrement > xLoopCounterIncrementTimeMax )
+		{
+			/* The tests appear to be no longer running (stalled). */
+			xTestStatus = pdFAIL;
+		}
+	}
+	else
+	{
+		/* ulLoopCounter changed, so the count of times this function was called
+		without a change can be reset to zero. */
+		xIterationsWithoutCounterIncrement = ( TickType_t ) 0;
+	}
+
+	ulLastLoopCounter = ulLoopCounter;
+
+	/* Errors detected in the task itself will have latched xTestStatus
+	to pdFAIL. */
+
+	return xTestStatus;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTest1_CreateTimersWithoutSchedulerRunning( void )
+{
+TickType_t xTimer;
+
+	for( xTimer = 0; xTimer < configTIMER_QUEUE_LENGTH; xTimer++ )
+	{
+		/* As the timer queue is not yet full, it should be possible to both
+		create and start a timer.  These timers are being started before the
+		scheduler has been started, so their block times should get set to zero
+		within the timer API itself. */
+		xAutoReloadTimers[ xTimer ] = xTimerCreate( "FR Timer",							/* Text name to facilitate debugging.  The kernel does not use this itself. */
+													( ( xTimer + ( TickType_t ) 1 ) * xBasePeriod ),/* The period for the timer.  The plus 1 ensures a period of zero is not specified. */
+													pdTRUE,								/* Auto-reload is set to true. */
+													( void * ) xTimer,					/* An identifier for the timer as all the auto reload timers use the same callback. */
+													prvAutoReloadTimerCallback );		/* The callback to be called when the timer expires. */
+
+		if( xAutoReloadTimers[ xTimer ] == NULL )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+		else
+		{
+			configASSERT( strcmp( pcTimerGetName( xAutoReloadTimers[ xTimer ] ), "FR Timer" ) == 0 );
+
+			/* The scheduler has not yet started, so the block period of
+			portMAX_DELAY should just get set to zero in xTimerStart().  Also,
+			the timer queue is not yet full so xTimerStart() should return
+			pdPASS. */
+			if( xTimerStart( xAutoReloadTimers[ xTimer ], portMAX_DELAY ) != pdPASS )
+			{
+				xTestStatus = pdFAIL;
+				configASSERT( xTestStatus );
+			}
+		}
+	}
+
+	/* The timers queue should now be full, so it should be possible to create
+	another timer, but not possible to start it (the timer queue will not get
+	drained until the scheduler has been started. */
+	xAutoReloadTimers[ configTIMER_QUEUE_LENGTH ] = xTimerCreate( "FR Timer",					/* Text name to facilitate debugging.  The kernel does not use this itself. */
+													( configTIMER_QUEUE_LENGTH * xBasePeriod ),	/* The period for the timer. */
+													pdTRUE,										/* Auto-reload is set to true. */
+													( void * ) xTimer,							/* An identifier for the timer as all the auto reload timers use the same callback. */
+													prvAutoReloadTimerCallback );				/* The callback executed when the timer expires. */
+
+	if( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH ] == NULL )
+	{
+		xTestStatus = pdFAIL;
+		configASSERT( xTestStatus );
+	}
+	else
+	{
+		if( xTimerStart( xAutoReloadTimers[ xTimer ], portMAX_DELAY ) == pdPASS )
+		{
+			/* This time it would not be expected that the timer could be
+			started at this point. */
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+	}
+
+	/* Create the timers that are used from the tick interrupt to test the timer
+	API functions that can be called from an ISR. */
+	xISRAutoReloadTimer = xTimerCreate( "ISR AR",							/* The text name given to the timer. */
+										0xffff,								/* The timer is not given a period yet - this will be done from the tick hook, but a period of 0 is invalid. */
+										pdTRUE,								/* This is an auto reload timer. */
+										( void * ) NULL,					/* The identifier is not required. */
+										prvISRAutoReloadTimerCallback );	/* The callback that is executed when the timer expires. */
+
+	xISROneShotTimer = xTimerCreate( 	"ISR OS",							/* The text name given to the timer. */
+										0xffff,								/* The timer is not given a period yet - this will be done from the tick hook, but a period of 0 is invalid. */
+										pdFALSE,							/* This is a one shot timer. */
+										( void * ) NULL,					/* The identifier is not required. */
+										prvISROneShotTimerCallback );		/* The callback that is executed when the timer expires. */
+
+	if( ( xISRAutoReloadTimer == NULL ) || ( xISROneShotTimer == NULL ) )
+	{
+		xTestStatus = pdFAIL;
+		configASSERT( xTestStatus );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvTest2_CheckTaskAndTimersInitialState( void )
+{
+uint8_t ucTimer;
+
+	/* Ensure all the timers are in their expected initial state.  This	depends
+	on the timer service task having a higher priority than this task.
+
+	auto reload timers 0 to ( configTIMER_QUEUE_LENGTH - 1 ) should now be active,
+	and auto reload timer configTIMER_QUEUE_LENGTH should not yet be active (it
+	could not be started prior to the scheduler being started when it was
+	created). */
+	for( ucTimer = 0; ucTimer < ( uint8_t ) configTIMER_QUEUE_LENGTH; ucTimer++ )
+	{
+		if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) == pdFALSE )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+	}
+
+	if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH ] ) != pdFALSE )
+	{
+		xTestStatus = pdFAIL;
+		configASSERT( xTestStatus );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void	prvTest3_CheckAutoReloadExpireRates( void )
+{
+uint8_t ucMaxAllowableValue, ucMinAllowableValue, ucTimer;
+TickType_t xBlockPeriod, xTimerPeriod, xExpectedNumber;
+UBaseType_t uxOriginalPriority;
+
+	/* Check the auto reload timers expire at the expected rates.  Do this at a
+	high priority for maximum accuracy.  This is ok as most of the time is spent
+	in the Blocked state. */
+	uxOriginalPriority = uxTaskPriorityGet( NULL );
+	vTaskPrioritySet( NULL, ( configMAX_PRIORITIES - 1 ) );
+
+	/* Delaying for configTIMER_QUEUE_LENGTH * xBasePeriod ticks should allow
+	all the auto reload timers to expire at least once. */
+	xBlockPeriod = ( ( TickType_t ) configTIMER_QUEUE_LENGTH ) * xBasePeriod;
+	vTaskDelay( xBlockPeriod );
+
+	/* Check that all the auto reload timers have called their callback
+	function the expected number of times. */
+	for( ucTimer = 0; ucTimer < ( uint8_t ) configTIMER_QUEUE_LENGTH; ucTimer++ )
+	{
+		/* The expected number of expiries is equal to the block period divided
+		by the timer period. */
+		xTimerPeriod = ( ( ( TickType_t ) ucTimer + ( TickType_t ) 1 ) * xBasePeriod );
+		xExpectedNumber = xBlockPeriod / xTimerPeriod;
+
+		ucMaxAllowableValue = ( ( uint8_t ) xExpectedNumber ) ;
+		ucMinAllowableValue = ( uint8_t ) ( ( uint8_t ) xExpectedNumber - ( uint8_t ) 1 ); /* Weird casting to try and please all compilers. */
+
+		if( ( ucAutoReloadTimerCounters[ ucTimer ] < ucMinAllowableValue ) ||
+			( ucAutoReloadTimerCounters[ ucTimer ] > ucMaxAllowableValue )
+			)
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+	}
+
+	/* Return to the original priority. */
+	vTaskPrioritySet( NULL, uxOriginalPriority );
+
+	if( xTestStatus == pdPASS )
+	{
+		/* No errors have been reported so increment the loop counter so the
+		check task knows this task is still running. */
+		ulLoopCounter++;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvTest4_CheckAutoReloadTimersCanBeStopped( void )
+{
+uint8_t ucTimer;
+
+	/* Check the auto reload timers can be stopped correctly, and correctly
+	report their state. */
+
+	/* Stop all the active timers. */
+	for( ucTimer = 0; ucTimer < ( uint8_t ) configTIMER_QUEUE_LENGTH; ucTimer++ )
+	{
+		/* The timer has not been stopped yet! */
+		if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) == pdFALSE )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		/* Now stop the timer.  This will appear to happen immediately to
+		this task because this task is running at a priority below the
+		timer service task. */
+		xTimerStop( xAutoReloadTimers[ ucTimer ], tmrdemoDONT_BLOCK );
+
+		/* The timer should now be inactive. */
+		if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) != pdFALSE )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+	}
+
+	taskENTER_CRITICAL();
+	{
+		/* The timer in array position configTIMER_QUEUE_LENGTH should not
+		be active.  The critical section is used to ensure the timer does
+		not call its callback between the next line running and the array
+		being cleared back to zero, as that would mask an error condition. */
+		if( ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH ] != ( uint8_t ) 0 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		/* Clear the timer callback count. */
+		memset( ( void * ) ucAutoReloadTimerCounters, 0, sizeof( ucAutoReloadTimerCounters ) );
+	}
+	taskEXIT_CRITICAL();
+
+	/* The timers are now all inactive, so this time, after delaying, none
+	of the callback counters should have incremented. */
+	vTaskDelay( ( ( TickType_t ) configTIMER_QUEUE_LENGTH ) * xBasePeriod );
+	for( ucTimer = 0; ucTimer < ( uint8_t ) configTIMER_QUEUE_LENGTH; ucTimer++ )
+	{
+		if( ucAutoReloadTimerCounters[ ucTimer ] != ( uint8_t ) 0 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+	}
+
+	if( xTestStatus == pdPASS )
+	{
+		/* No errors have been reported so increment the loop counter so
+		the check task knows this task is still running. */
+		ulLoopCounter++;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvTest5_CheckBasicOneShotTimerBehaviour( void )
+{
+	/* Check the one shot timer only calls its callback once after it has been
+	started, and that it reports its state correctly. */
+
+	/* The one shot timer should not be active yet. */
+	if( xTimerIsTimerActive( xOneShotTimer ) != pdFALSE )
+	{
+		xTestStatus = pdFAIL;
+		configASSERT( xTestStatus );
+	}
+
+	if( ucOneShotTimerCounter != ( uint8_t ) 0 )
+	{
+		xTestStatus = pdFAIL;
+		configASSERT( xTestStatus );
+	}
+
+	/* Start the one shot timer and check that it reports its state correctly. */
+	xTimerStart( xOneShotTimer, tmrdemoDONT_BLOCK );
+	if( xTimerIsTimerActive( xOneShotTimer ) == pdFALSE )
+	{
+		xTestStatus = pdFAIL;
+		configASSERT( xTestStatus );
+	}
+
+	/* Delay for three times as long as the one shot timer period, then check
+	to ensure it has only called its callback once, and is now not in the
+	active state. */
+	vTaskDelay( tmrdemoONE_SHOT_TIMER_PERIOD * ( TickType_t ) 3 );
+
+	if( xTimerIsTimerActive( xOneShotTimer ) != pdFALSE )
+	{
+		xTestStatus = pdFAIL;
+		configASSERT( xTestStatus );
+	}
+
+	if( ucOneShotTimerCounter != ( uint8_t ) 1 )
+	{
+		xTestStatus = pdFAIL;
+		configASSERT( xTestStatus );
+	}
+	else
+	{
+		/* Reset the one shot timer callback count. */
+		ucOneShotTimerCounter = ( uint8_t ) 0;
+	}
+
+	if( xTestStatus == pdPASS )
+	{
+		/* No errors have been reported so increment the loop counter so the
+		check task knows this task is still running. */
+		ulLoopCounter++;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvTest6_CheckAutoReloadResetBehaviour( void )
+{
+uint8_t ucTimer;
+
+	/* Check timer reset behaviour. */
+
+	/* Restart the one shot timer and check it reports its status correctly. */
+	xTimerStart( xOneShotTimer, tmrdemoDONT_BLOCK );
+	if( xTimerIsTimerActive( xOneShotTimer ) == pdFALSE )
+	{
+		xTestStatus = pdFAIL;
+		configASSERT( xTestStatus );
+	}
+
+	/* Restart one of the auto reload timers and check that it reports its
+	status correctly. */
+	xTimerStart( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ], tmrdemoDONT_BLOCK );
+	if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ] ) == pdFALSE )
+	{
+		xTestStatus = pdFAIL;
+		configASSERT( xTestStatus );
+	}
+
+	for( ucTimer = 0; ucTimer < tmrdemoNUM_TIMER_RESETS; ucTimer++ )
+	{
+		/* Delay for half as long as the one shot timer period, then reset it.
+		It should never expire while this is done, so its callback count should
+		never increment. */
+		vTaskDelay( tmrdemoONE_SHOT_TIMER_PERIOD / 2 );
+
+		/* Check both running timers are still active, but have not called their
+		callback functions. */
+		if( xTimerIsTimerActive( xOneShotTimer ) == pdFALSE )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		if( ucOneShotTimerCounter != ( uint8_t ) 0 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ] ) == pdFALSE )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		if( ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH - 1 ] != ( uint8_t ) 0 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		/* Reset both running timers. */
+		xTimerReset( xOneShotTimer, tmrdemoDONT_BLOCK );
+		xTimerReset( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ], tmrdemoDONT_BLOCK );
+
+		if( xTestStatus == pdPASS )
+		{
+			/* No errors have been reported so increment the loop counter so
+			the check task knows this task is still running. */
+			ulLoopCounter++;
+		}
+	}
+
+	/* Finally delay long enough for both running timers to expire. */
+	vTaskDelay( ( ( TickType_t ) configTIMER_QUEUE_LENGTH ) * xBasePeriod );
+
+	/* The timers were not reset during the above delay period so should now
+	both have called their callback functions. */
+	if( ucOneShotTimerCounter != ( uint8_t ) 1 )
+	{
+		xTestStatus = pdFAIL;
+		configASSERT( xTestStatus );
+	}
+
+	if( ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH - 1 ] == 0 )
+	{
+		xTestStatus = pdFAIL;
+		configASSERT( xTestStatus );
+	}
+
+	/* The one shot timer should no longer be active, while the auto reload
+	timer should still be active. */
+	if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ] ) == pdFALSE )
+	{
+		xTestStatus = pdFAIL;
+		configASSERT( xTestStatus );
+	}
+
+	if( xTimerIsTimerActive( xOneShotTimer ) == pdTRUE )
+	{
+		xTestStatus = pdFAIL;
+		configASSERT( xTestStatus );
+	}
+
+	/* Stop the auto reload timer again. */
+	xTimerStop( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ], tmrdemoDONT_BLOCK );
+
+	if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ] ) != pdFALSE )
+	{
+		xTestStatus = pdFAIL;
+		configASSERT( xTestStatus );
+	}
+
+	/* Clear the timer callback counts, ready for another iteration of these
+	tests. */
+	ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH - 1 ] = ( uint8_t ) 0;
+	ucOneShotTimerCounter = ( uint8_t ) 0;
+
+	if( xTestStatus == pdPASS )
+	{
+		/* No errors have been reported so increment the loop counter so the check
+		task knows this task is still running. */
+		ulLoopCounter++;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvResetStartConditionsForNextIteration( void )
+{
+uint8_t ucTimer;
+
+	/* Start the timers again to start all the tests over again. */
+
+	/* Start the timers again. */
+	for( ucTimer = 0; ucTimer < ( uint8_t ) configTIMER_QUEUE_LENGTH; ucTimer++ )
+	{
+		/* The timer has not been started yet! */
+		if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) != pdFALSE )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		/* Now start the timer.  This will appear to happen immediately to
+		this task because this task is running at a priority below the timer
+		service task. */
+		xTimerStart( xAutoReloadTimers[ ucTimer ], tmrdemoDONT_BLOCK );
+
+		/* The timer should now be active. */
+		if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) == pdFALSE )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+	}
+
+	if( xTestStatus == pdPASS )
+	{
+		/* No errors have been reported so increment the loop counter so the
+		check task knows this task is still running. */
+		ulLoopCounter++;
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vTimerPeriodicISRTests( void )
+{
+static TickType_t uxTick = ( TickType_t ) -1;
+
+#if( configTIMER_TASK_PRIORITY != ( configMAX_PRIORITIES - 1 ) )
+	/* The timer service task is not the highest priority task, so it cannot
+	be assumed that timings will be exact.  Timers should never call their
+	callback before their expiry time, but a margin is permissible for calling
+	their callback after their expiry time.  If exact timing is required then
+	configTIMER_TASK_PRIORITY must be set to ensure the timer service task
+	is the highest priority task in the system.
+
+	This function is called from the tick hook.  The tick hook is called
+	even when the scheduler is suspended.  Therefore it is possible that the
+	uxTick count maintained in this function is temporarily ahead of the tick
+	count maintained by the kernel.  When this is the case a message posted from
+	this function will assume a time stamp in advance of the real time stamp,
+	which can result in a timer being processed before this function expects it
+	to.  For example, if the kernel's tick count was 100, and uxTick was 102,
+	then this function will not expect the timer to have expired until the
+	kernel's tick count is (102 + xBasePeriod), whereas in reality the timer
+	will expire when the kernel's tick count is (100 + xBasePeriod).  For this
+	reason xMargin is used as an allowable margin for premature timer expiries
+	as well as late timer expiries. */
+	#ifdef _WINDOWS_
+		/* Windows is not real real time. */
+		const TickType_t xMargin = 20;
+	#else
+		const TickType_t xMargin = 6;
+	#endif /* _WINDOWS_ */
+#else
+	#ifdef _WINDOWS_
+		/* Windows is not real real time. */
+		const TickType_t xMargin = 20;
+	#else
+		const TickType_t xMargin = 4;
+	#endif /* _WINDOWS_ */
+#endif
+
+
+	uxTick++;
+
+	if( uxTick == 0 )
+	{
+		/* The timers will have been created, but not started.  Start them now
+		by setting their period. */
+		ucISRAutoReloadTimerCounter = 0;
+		ucISROneShotTimerCounter = 0;
+
+		/* It is possible that the timer task has not yet made room in the
+		timer queue.  If the timers cannot be started then reset uxTick so
+		another attempt is made later. */
+		uxTick = ( TickType_t ) -1;
+
+		/* Try starting first timer. */
+		if( xTimerChangePeriodFromISR( xISRAutoReloadTimer, xBasePeriod, NULL ) == pdPASS )
+		{
+			/* First timer was started, try starting the second timer. */
+			if( xTimerChangePeriodFromISR( xISROneShotTimer, xBasePeriod, NULL ) == pdPASS )
+			{
+				/* Both timers were started, so set the uxTick back to its
+				proper value. */
+				uxTick = 0;
+			}
+			else
+			{
+				/* Second timer could not be started, so stop the first one
+				again. */
+				xTimerStopFromISR( xISRAutoReloadTimer, NULL );
+			}
+		}
+	}
+	else if( uxTick == ( xBasePeriod - xMargin ) )
+	{
+		/* Neither timer should have expired yet. */
+		if( ( ucISRAutoReloadTimerCounter != 0 ) || ( ucISROneShotTimerCounter != 0 ) )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+	}
+	else if( uxTick == ( xBasePeriod + xMargin ) )
+	{
+		/* Both timers should now have expired once.  The auto reload timer will
+		still be active, but the one shot timer should now have stopped. */
+		if( ( ucISRAutoReloadTimerCounter != 1 ) || ( ucISROneShotTimerCounter != 1 ) )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+	}
+	else if( uxTick == ( ( 2 * xBasePeriod ) - xMargin ) )
+	{
+		/* The auto reload timer will still be active, but the one shot timer
+		should now have stopped - however, at this time neither of the timers
+		should have expired again since the last test. */
+		if( ( ucISRAutoReloadTimerCounter != 1 ) || ( ucISROneShotTimerCounter != 1 ) )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+	}
+	else if( uxTick == ( ( 2 * xBasePeriod ) + xMargin ) )
+	{
+		/* The auto reload timer will still be active, but the one shot timer
+		should now have stopped.  At this time the auto reload timer should have
+		expired again, but the one shot timer count should not have changed. */
+		if( ucISRAutoReloadTimerCounter != 2 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		if( ucISROneShotTimerCounter != 1 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+	}
+	else if( uxTick == ( ( 2 * xBasePeriod ) + ( xBasePeriod >> ( TickType_t ) 2U ) ) )
+	{
+		/* The auto reload timer will still be active, but the one shot timer
+		should now have stopped.  Again though, at this time, neither timer call
+		back should have been called since the last test. */
+		if( ucISRAutoReloadTimerCounter != 2 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		if( ucISROneShotTimerCounter != 1 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+	}
+	else if( uxTick == ( 3 * xBasePeriod ) )
+	{
+		/* Start the one shot timer again. */
+		xTimerStartFromISR( xISROneShotTimer, NULL );
+	}
+	else if( uxTick == ( ( 3 * xBasePeriod ) + xMargin ) )
+	{
+		/* The auto reload timer and one shot timer will be active.  At
+		this time the auto reload timer should have	expired again, but the one
+		shot timer count should not have changed yet. */
+		if( ucISRAutoReloadTimerCounter != 3 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		if( ucISROneShotTimerCounter != 1 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		/* Now stop the auto reload timer.  The one shot timer was started
+		a few ticks ago. */
+		xTimerStopFromISR( xISRAutoReloadTimer, NULL );
+	}
+	else if( uxTick == ( 4 * ( xBasePeriod - xMargin ) ) )
+	{
+		/* The auto reload timer is now stopped, and the one shot timer is
+		active, but at this time neither timer should have expired since the
+		last test. */
+		if( ucISRAutoReloadTimerCounter != 3 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		if( ucISROneShotTimerCounter != 1 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+	}
+	else if( uxTick == ( ( 4 * xBasePeriod ) + xMargin ) )
+	{
+		/* The auto reload timer is now stopped, and the one shot timer is
+		active.  The one shot timer should have expired again, but the auto
+		reload timer should not have executed its callback. */
+		if( ucISRAutoReloadTimerCounter != 3 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		if( ucISROneShotTimerCounter != 2 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+	}
+	else if( uxTick == ( 8 * xBasePeriod ) )
+	{
+		/* The auto reload timer is now stopped, and the one shot timer has
+		already expired and then stopped itself.  Both callback counters should
+		not have incremented since the last test. */
+		if( ucISRAutoReloadTimerCounter != 3 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		if( ucISROneShotTimerCounter != 2 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		/* Now reset the one shot timer. */
+		xTimerResetFromISR( xISROneShotTimer, NULL );
+	}
+	else if( uxTick == ( ( 9 * xBasePeriod ) - xMargin ) )
+	{
+		/* Only the one shot timer should be running, but it should not have
+		expired since the last test.  Check the callback counters have not
+		incremented, then reset the one shot timer again. */
+		if( ucISRAutoReloadTimerCounter != 3 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		if( ucISROneShotTimerCounter != 2 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		xTimerResetFromISR( xISROneShotTimer, NULL );
+	}
+	else if( uxTick == ( ( 10 * xBasePeriod ) - ( 2 * xMargin ) ) )
+	{
+		/* Only the one shot timer should be running, but it should not have
+		expired since the last test.  Check the callback counters have not
+		incremented, then reset the one shot timer again. */
+		if( ucISRAutoReloadTimerCounter != 3 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		if( ucISROneShotTimerCounter != 2 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		xTimerResetFromISR( xISROneShotTimer, NULL );
+	}
+	else if( uxTick == ( ( 11 * xBasePeriod ) - ( 3 * xMargin ) ) )
+	{
+		/* Only the one shot timer should be running, but it should not have
+		expired since the last test.  Check the callback counters have not
+		incremented, then reset the one shot timer once again. */
+		if( ucISRAutoReloadTimerCounter != 3 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		if( ucISROneShotTimerCounter != 2 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		xTimerResetFromISR( xISROneShotTimer, NULL );
+	}
+	else if( uxTick == ( ( 12 * xBasePeriod ) - ( 2 * xMargin ) ) )
+	{
+		/* Only the one shot timer should have been running and this time it
+		should have	expired.  Check its callback count has been incremented.
+		The auto reload	timer is still not running so should still have the same
+		count value.  This time the one shot timer is not reset so should not
+		restart from its expiry period again. */
+		if( ucISRAutoReloadTimerCounter != 3 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		if( ucISROneShotTimerCounter != 3 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+	}
+	else if( uxTick == ( 15 * xBasePeriod ) )
+	{
+		/* Neither timer should be running now.  Check neither callback count
+		has incremented, then go back to the start to run these tests all
+		over again. */
+		if( ucISRAutoReloadTimerCounter != 3 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		if( ucISROneShotTimerCounter != 3 )
+		{
+			xTestStatus = pdFAIL;
+			configASSERT( xTestStatus );
+		}
+
+		uxTick = ( TickType_t ) -1;
+	}
+}
+/*-----------------------------------------------------------*/
+
+/*** Timer callback functions are defined below here. ***/
+
+static void prvAutoReloadTimerCallback( TimerHandle_t pxExpiredTimer )
+{
+size_t uxTimerID;
+
+	uxTimerID = ( size_t ) pvTimerGetTimerID( pxExpiredTimer );
+	if( uxTimerID <= ( configTIMER_QUEUE_LENGTH + 1 ) )
+	{
+		( ucAutoReloadTimerCounters[ uxTimerID ] )++;
+	}
+	else
+	{
+		/* The timer ID appears to be unexpected (invalid). */
+		xTestStatus = pdFAIL;
+		configASSERT( xTestStatus );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvOneShotTimerCallback( TimerHandle_t pxExpiredTimer )
+{
+/* A count is kept of the number of times this callback function is executed.
+The count is stored as the timer's ID.  This is only done to test the
+vTimerSetTimerID() function. */
+static size_t uxCallCount = 0;
+size_t uxLastCallCount;
+
+	/* Obtain the timer's ID, which should be a count of the number of times
+	this callback function has been executed. */
+	uxLastCallCount = ( size_t ) pvTimerGetTimerID( pxExpiredTimer );
+	configASSERT( uxLastCallCount == uxCallCount );
+
+	/* Increment the call count, then save it back as the timer's ID.  This is
+	only done to test the vTimerSetTimerID() API function. */
+	uxLastCallCount++;
+	vTimerSetTimerID( pxExpiredTimer, ( void * ) uxLastCallCount );
+	uxCallCount++;
+
+	ucOneShotTimerCounter++;
+}
+/*-----------------------------------------------------------*/
+
+static void prvISRAutoReloadTimerCallback( TimerHandle_t pxExpiredTimer )
+{
+	/* The parameter is not used in this case as only one timer uses this
+	callback function. */
+	( void ) pxExpiredTimer;
+
+	ucISRAutoReloadTimerCounter++;
+}
+/*-----------------------------------------------------------*/
+
+static void prvISROneShotTimerCallback( TimerHandle_t pxExpiredTimer )
+{
+	/* The parameter is not used in this case as only one timer uses this
+	callback function. */
+	( void ) pxExpiredTimer;
+
+	ucISROneShotTimerCounter++;
+}
+/*-----------------------------------------------------------*/
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/blocktim.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/blocktim.c
new file mode 100644
index 0000000..22a3b8c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/blocktim.c
@@ -0,0 +1,544 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * This file contains some test scenarios that ensure tasks do not exit queue
+ * send or receive functions prematurely.  A description of the tests is
+ * included within the code.
+ */
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* Demo includes. */
+#include "blocktim.h"
+
+/* Task priorities and stack sizes.  Allow these to be overridden. */
+#ifndef bktPRIMARY_PRIORITY
+	#define bktPRIMARY_PRIORITY		( configMAX_PRIORITIES - 3 )
+#endif
+
+#ifndef bktSECONDARY_PRIORITY
+	#define bktSECONDARY_PRIORITY	( configMAX_PRIORITIES - 4 )
+#endif
+
+#ifndef bktBLOCK_TIME_TASK_STACK_SIZE
+	#define bktBLOCK_TIME_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
+#endif
+
+/* Task behaviour. */
+#define bktQUEUE_LENGTH				( 5 )
+#define bktSHORT_WAIT				pdMS_TO_TICKS( ( TickType_t ) 20 )
+#define bktPRIMARY_BLOCK_TIME		( 10 )
+#define bktALLOWABLE_MARGIN			( 15 )
+#define bktTIME_TO_BLOCK			( 175 )
+#define bktDONT_BLOCK				( ( TickType_t ) 0 )
+#define bktRUN_INDICATOR			( ( UBaseType_t ) 0x55 )
+
+/* In case the demo does not have software timers enabled, as this file uses
+the configTIMER_TASK_PRIORITY setting. */
+#ifndef configTIMER_TASK_PRIORITY
+	#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The two test tasks.  Their behaviour is commented within the functions.
+ */
+static void vPrimaryBlockTimeTestTask( void *pvParameters );
+static void vSecondaryBlockTimeTestTask( void *pvParameters );
+
+/*
+ * Very basic tests to verify the block times are as expected.
+ */
+static void prvBasicDelayTests( void );
+
+/*-----------------------------------------------------------*/
+
+/* The queue on which the tasks block. */
+static QueueHandle_t xTestQueue;
+
+/* Handle to the secondary task is required by the primary task for calls
+to vTaskSuspend/Resume(). */
+static TaskHandle_t xSecondary;
+
+/* Used to ensure that tasks are still executing without error. */
+static volatile BaseType_t xPrimaryCycles = 0, xSecondaryCycles = 0;
+static volatile BaseType_t xErrorOccurred = pdFALSE;
+
+/* Provides a simple mechanism for the primary task to know when the
+secondary task has executed. */
+static volatile UBaseType_t xRunIndicator;
+
+/*-----------------------------------------------------------*/
+
+void vCreateBlockTimeTasks( void )
+{
+	/* Create the queue on which the two tasks block. */
+	xTestQueue = xQueueCreate( bktQUEUE_LENGTH, sizeof( BaseType_t ) );
+
+	if( xTestQueue != NULL )
+	{
+		/* vQueueAddToRegistry() adds the queue to the queue registry, if one
+		is in use.  The queue registry is provided as a means for kernel aware
+		debuggers to locate queues and has no purpose if a kernel aware
+		debugger is not being used.  The call to vQueueAddToRegistry() will be
+		removed by the pre-processor if configQUEUE_REGISTRY_SIZE is not
+		defined or is defined to be less than 1. */
+		vQueueAddToRegistry( xTestQueue, "Block_Time_Queue" );
+
+		/* Create the two test tasks. */
+		xTaskCreate( vPrimaryBlockTimeTestTask, "BTest1", bktBLOCK_TIME_TASK_STACK_SIZE, NULL, bktPRIMARY_PRIORITY, NULL );
+		xTaskCreate( vSecondaryBlockTimeTestTask, "BTest2", bktBLOCK_TIME_TASK_STACK_SIZE, NULL, bktSECONDARY_PRIORITY, &xSecondary );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void vPrimaryBlockTimeTestTask( void *pvParameters )
+{
+BaseType_t xItem, xData;
+TickType_t xTimeWhenBlocking;
+TickType_t xTimeToBlock, xBlockedTime;
+
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		/*********************************************************************
+		Test 0
+
+		Basic vTaskDelay() and vTaskDelayUntil() tests. */
+		prvBasicDelayTests();
+
+
+		/*********************************************************************
+		Test 1
+
+		Simple block time wakeup test on queue receives. */
+		for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
+		{
+			/* The queue is empty. Attempt to read from the queue using a block
+			time.  When we wake, ensure the delta in time is as expected. */
+			xTimeToBlock = ( TickType_t ) ( bktPRIMARY_BLOCK_TIME << xItem );
+
+			xTimeWhenBlocking = xTaskGetTickCount();
+
+			/* We should unblock after xTimeToBlock having not received
+			anything on the queue. */
+			if( xQueueReceive( xTestQueue, &xData, xTimeToBlock ) != errQUEUE_EMPTY )
+			{
+				xErrorOccurred = pdTRUE;
+			}
+
+			/* How long were we blocked for? */
+			xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;
+
+			if( xBlockedTime < xTimeToBlock )
+			{
+				/* Should not have blocked for less than we requested. */
+				xErrorOccurred = pdTRUE;
+			}
+
+			if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) )
+			{
+				/* Should not have blocked for longer than we requested,
+				although we would not necessarily run as soon as we were
+				unblocked so a margin is allowed. */
+				xErrorOccurred = pdTRUE;
+			}
+		}
+
+		/*********************************************************************
+		Test 2
+
+		Simple block time wakeup test on queue sends.
+
+		First fill the queue.  It should be empty so all sends should pass. */
+		for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
+		{
+			if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS )
+			{
+				xErrorOccurred = pdTRUE;
+			}
+
+			#if configUSE_PREEMPTION == 0
+				taskYIELD();
+			#endif
+		}
+
+		for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
+		{
+			/* The queue is full. Attempt to write to the queue using a block
+			time.  When we wake, ensure the delta in time is as expected. */
+			xTimeToBlock = ( TickType_t ) ( bktPRIMARY_BLOCK_TIME << xItem );
+
+			xTimeWhenBlocking = xTaskGetTickCount();
+
+			/* We should unblock after xTimeToBlock having not received
+			anything on the queue. */
+			if( xQueueSend( xTestQueue, &xItem, xTimeToBlock ) != errQUEUE_FULL )
+			{
+				xErrorOccurred = pdTRUE;
+			}
+
+			/* How long were we blocked for? */
+			xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;
+
+			if( xBlockedTime < xTimeToBlock )
+			{
+				/* Should not have blocked for less than we requested. */
+				xErrorOccurred = pdTRUE;
+			}
+
+			if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) )
+			{
+				/* Should not have blocked for longer than we requested,
+				although we would not necessarily run as soon as we were
+				unblocked so a margin is allowed. */
+				xErrorOccurred = pdTRUE;
+			}
+		}
+
+		/*********************************************************************
+		Test 3
+
+		Wake the other task, it will block attempting to post to the queue.
+		When we read from the queue the other task will wake, but before it
+		can run we will post to the queue again.  When the other task runs it
+		will find the queue still full, even though it was woken.  It should
+		recognise that its block time has not expired and return to block for
+		the remains of its block time.
+
+		Wake the other task so it blocks attempting to post to the already
+		full queue. */
+		xRunIndicator = 0;
+		vTaskResume( xSecondary );
+
+		/* We need to wait a little to ensure the other task executes. */
+		while( xRunIndicator != bktRUN_INDICATOR )
+		{
+			/* The other task has not yet executed. */
+			vTaskDelay( bktSHORT_WAIT );
+		}
+		/* Make sure the other task is blocked on the queue. */
+		vTaskDelay( bktSHORT_WAIT );
+		xRunIndicator = 0;
+
+		for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
+		{
+			/* Now when we make space on the queue the other task should wake
+			but not execute as this task has higher priority. */
+			if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS )
+			{
+				xErrorOccurred = pdTRUE;
+			}
+
+			/* Now fill the queue again before the other task gets a chance to
+			execute.  If the other task had executed we would find the queue
+			full ourselves, and the other task have set xRunIndicator. */
+			if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS )
+			{
+				xErrorOccurred = pdTRUE;
+			}
+
+			if( xRunIndicator == bktRUN_INDICATOR )
+			{
+				/* The other task should not have executed. */
+				xErrorOccurred = pdTRUE;
+			}
+
+			/* Raise the priority of the other task so it executes and blocks
+			on the queue again. */
+			vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 );
+
+			/* The other task should now have re-blocked without exiting the
+			queue function. */
+			if( xRunIndicator == bktRUN_INDICATOR )
+			{
+				/* The other task should not have executed outside of the
+				queue function. */
+				xErrorOccurred = pdTRUE;
+			}
+
+			/* Set the priority back down. */
+			vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY );
+		}
+
+		/* Let the other task timeout.  When it unblockes it will check that it
+		unblocked at the correct time, then suspend itself. */
+		while( xRunIndicator != bktRUN_INDICATOR )
+		{
+			vTaskDelay( bktSHORT_WAIT );
+		}
+		vTaskDelay( bktSHORT_WAIT );
+		xRunIndicator = 0;
+
+
+		/*********************************************************************
+		Test 4
+
+		As per test 3 - but with the send and receive the other way around.
+		The other task blocks attempting to read from the queue.
+
+		Empty the queue.  We should find that it is full. */
+		for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
+		{
+			if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS )
+			{
+				xErrorOccurred = pdTRUE;
+			}
+		}
+
+		/* Wake the other task so it blocks attempting to read from  the
+		already	empty queue. */
+		vTaskResume( xSecondary );
+
+		/* We need to wait a little to ensure the other task executes. */
+		while( xRunIndicator != bktRUN_INDICATOR )
+		{
+			vTaskDelay( bktSHORT_WAIT );
+		}
+		vTaskDelay( bktSHORT_WAIT );
+		xRunIndicator = 0;
+
+		for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
+		{
+			/* Now when we place an item on the queue the other task should
+			wake but not execute as this task has higher priority. */
+			if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS )
+			{
+				xErrorOccurred = pdTRUE;
+			}
+
+			/* Now empty the queue again before the other task gets a chance to
+			execute.  If the other task had executed we would find the queue
+			empty ourselves, and the other task would be suspended. */
+			if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS )
+			{
+				xErrorOccurred = pdTRUE;
+			}
+
+			if( xRunIndicator == bktRUN_INDICATOR )
+			{
+				/* The other task should not have executed. */
+				xErrorOccurred = pdTRUE;
+			}
+
+			/* Raise the priority of the other task so it executes and blocks
+			on the queue again. */
+			vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 );
+
+			/* The other task should now have re-blocked without exiting the
+			queue function. */
+			if( xRunIndicator == bktRUN_INDICATOR )
+			{
+				/* The other task should not have executed outside of the
+				queue function. */
+				xErrorOccurred = pdTRUE;
+			}
+			vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY );
+		}
+
+		/* Let the other task timeout.  When it unblockes it will check that it
+		unblocked at the correct time, then suspend itself. */
+		while( xRunIndicator != bktRUN_INDICATOR )
+		{
+			vTaskDelay( bktSHORT_WAIT );
+		}
+		vTaskDelay( bktSHORT_WAIT );
+
+		xPrimaryCycles++;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void vSecondaryBlockTimeTestTask( void *pvParameters )
+{
+TickType_t xTimeWhenBlocking, xBlockedTime;
+BaseType_t xData;
+
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		/*********************************************************************
+		Test 0, 1 and 2
+
+		This task does not participate in these tests. */
+		vTaskSuspend( NULL );
+
+		/*********************************************************************
+		Test 3
+
+		The first thing we do is attempt to read from the queue.  It should be
+		full so we block.  Note the time before we block so we can check the
+		wake time is as per that expected. */
+		xTimeWhenBlocking = xTaskGetTickCount();
+
+		/* We should unblock after bktTIME_TO_BLOCK having not sent anything to
+		the queue. */
+		xData = 0;
+		xRunIndicator = bktRUN_INDICATOR;
+		if( xQueueSend( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_FULL )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+
+		/* How long were we inside the send function? */
+		xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;
+
+		/* We should not have blocked for less time than bktTIME_TO_BLOCK. */
+		if( xBlockedTime < bktTIME_TO_BLOCK )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+
+		/* We should of not blocked for much longer than bktALLOWABLE_MARGIN
+		either.  A margin is permitted as we would not necessarily run as
+		soon as we unblocked. */
+		if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+
+		/* Suspend ready for test 3. */
+		xRunIndicator = bktRUN_INDICATOR;
+		vTaskSuspend( NULL );
+
+		/*********************************************************************
+        Test 4
+
+		As per test three, but with the send and receive reversed. */
+		xTimeWhenBlocking = xTaskGetTickCount();
+
+		/* We should unblock after bktTIME_TO_BLOCK having not received
+		anything on the queue. */
+		xRunIndicator = bktRUN_INDICATOR;
+		if( xQueueReceive( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_EMPTY )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+
+		xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;
+
+		/* We should not have blocked for less time than bktTIME_TO_BLOCK. */
+		if( xBlockedTime < bktTIME_TO_BLOCK )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+
+		/* We should of not blocked for much longer than bktALLOWABLE_MARGIN
+		either.  A margin is permitted as we would not necessarily run as soon
+		as we unblocked. */
+		if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+
+		xRunIndicator = bktRUN_INDICATOR;
+
+		xSecondaryCycles++;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvBasicDelayTests( void )
+{
+TickType_t xPreTime, xPostTime, x, xLastUnblockTime, xExpectedUnblockTime;
+const TickType_t xPeriod = 75, xCycles = 5, xAllowableMargin = ( bktALLOWABLE_MARGIN >> 1 );
+
+	/* Temporarily increase priority so the timing is more accurate, but not so
+	high as to disrupt the timer tests. */
+	vTaskPrioritySet( NULL, configTIMER_TASK_PRIORITY - 1 );
+
+	/* Crude check to too that vTaskDelay() blocks for the expected period. */
+	xPreTime = xTaskGetTickCount();
+	vTaskDelay( bktTIME_TO_BLOCK );
+	xPostTime = xTaskGetTickCount();
+
+	/* The priority is higher, so the allowable margin is halved when compared
+	to the other tests in this file. */
+	if( ( xPostTime - xPreTime ) > ( bktTIME_TO_BLOCK + xAllowableMargin ) )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+
+	/* Now crude tests to check the vTaskDelayUntil() functionality. */
+	xPostTime = xTaskGetTickCount();
+	xLastUnblockTime = xPostTime;
+
+	for( x = 0; x < xCycles; x++ )
+	{
+		/* Calculate the next expected unblock time from the time taken before
+		this loop was entered. */
+		xExpectedUnblockTime = xPostTime + ( x * xPeriod );
+
+		vTaskDelayUntil( &xLastUnblockTime, xPeriod );
+
+		if( ( xTaskGetTickCount() - xExpectedUnblockTime ) > ( bktTIME_TO_BLOCK + xAllowableMargin ) )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+
+		xPrimaryCycles++;
+	}
+
+	/* Reset to the original task priority ready for the other tests. */
+	vTaskPrioritySet( NULL, bktPRIMARY_PRIORITY );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xAreBlockTimeTestTasksStillRunning( void )
+{
+static BaseType_t xLastPrimaryCycleCount = 0, xLastSecondaryCycleCount = 0;
+BaseType_t xReturn = pdPASS;
+
+	/* Have both tasks performed at least one cycle since this function was
+	last called? */
+	if( xPrimaryCycles == xLastPrimaryCycleCount )
+	{
+		xReturn = pdFAIL;
+	}
+
+	if( xSecondaryCycles == xLastSecondaryCycleCount )
+	{
+		xReturn = pdFAIL;
+	}
+
+	if( xErrorOccurred == pdTRUE )
+	{
+		xReturn = pdFAIL;
+	}
+
+	xLastSecondaryCycleCount = xSecondaryCycles;
+	xLastPrimaryCycleCount = xPrimaryCycles;
+
+	return xReturn;
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/comtest.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/comtest.c
new file mode 100644
index 0000000..3c4de38
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/comtest.c
@@ -0,0 +1,265 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*
+ * This version of comtest. c is for use on systems that have limited stack
+ * space and no display facilities.  The complete version can be found in
+ * the Demo/Common/Full directory.
+ *
+ * Creates two tasks that operate on an interrupt driven serial port.  A
+ * loopback connector should be used so that everything that is transmitted is
+ * also received.  The serial port does not use any flow control.  On a
+ * standard 9way 'D' connector pins two and three should be connected together.
+ *
+ * The first task posts a sequence of characters to the Tx queue, toggling an
+ * LED on each successful post.  At the end of the sequence it sleeps for a
+ * pseudo-random period before resending the same sequence.
+ *
+ * The UART Tx end interrupt is enabled whenever data is available in the Tx
+ * queue.  The Tx end ISR removes a single character from the Tx queue and
+ * passes it to the UART for transmission.
+ *
+ * The second task blocks on the Rx queue waiting for a character to become
+ * available.  When the UART Rx end interrupt receives a character it places
+ * it in the Rx queue, waking the second task.  The second task checks that the
+ * characters removed from the Rx queue form the same sequence as those posted
+ * to the Tx queue, and toggles an LED for each correct character.
+ *
+ * The receiving task is spawned with a higher priority than the transmitting
+ * task.  The receiver will therefore wake every time a character is
+ * transmitted so neither the Tx or Rx queue should ever hold more than a few
+ * characters.
+ *
+ */
+
+/* Scheduler include files. */
+#include 
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo program include files. */
+#include "serial.h"
+#include "comtest.h"
+#include "partest.h"
+
+#define comSTACK_SIZE				configMINIMAL_STACK_SIZE
+#define comTX_LED_OFFSET			( 0 )
+#define comRX_LED_OFFSET			( 1 )
+#define comTOTAL_PERMISSIBLE_ERRORS ( 2 )
+
+/* The Tx task will transmit the sequence of characters at a pseudo random
+interval.  This is the maximum and minimum block time between sends. */
+#define comTX_MAX_BLOCK_TIME		( ( TickType_t ) 0x96 )
+#define comTX_MIN_BLOCK_TIME		( ( TickType_t ) 0x32 )
+#define comOFFSET_TIME				( ( TickType_t ) 3 )
+
+/* We should find that each character can be queued for Tx immediately and we
+don't have to block to send. */
+#define comNO_BLOCK					( ( TickType_t ) 0 )
+
+/* The Rx task will block on the Rx queue for a long period. */
+#define comRX_BLOCK_TIME			( ( TickType_t ) 0xffff )
+
+/* The sequence transmitted is from comFIRST_BYTE to and including comLAST_BYTE. */
+#define comFIRST_BYTE				( 'A' )
+#define comLAST_BYTE				( 'X' )
+
+#define comBUFFER_LEN				( ( UBaseType_t ) ( comLAST_BYTE - comFIRST_BYTE ) + ( UBaseType_t ) 1 )
+#define comINITIAL_RX_COUNT_VALUE	( 0 )
+
+/* Handle to the com port used by both tasks. */
+static xComPortHandle xPort = NULL;
+
+/* The transmit task as described at the top of the file. */
+static portTASK_FUNCTION_PROTO( vComTxTask, pvParameters );
+
+/* The receive task as described at the top of the file. */
+static portTASK_FUNCTION_PROTO( vComRxTask, pvParameters );
+
+/* The LED that should be toggled by the Rx and Tx tasks.  The Rx task will
+toggle LED ( uxBaseLED + comRX_LED_OFFSET).  The Tx task will toggle LED
+( uxBaseLED + comTX_LED_OFFSET ). */
+static UBaseType_t uxBaseLED = 0;
+
+/* Check variable used to ensure no error have occurred.  The Rx task will
+increment this variable after every successfully received sequence.  If at any
+time the sequence is incorrect the the variable will stop being incremented. */
+static volatile UBaseType_t uxRxLoops = comINITIAL_RX_COUNT_VALUE;
+
+/*-----------------------------------------------------------*/
+
+void vAltStartComTestTasks( UBaseType_t uxPriority, uint32_t ulBaudRate, UBaseType_t uxLED )
+{
+	/* Initialise the com port then spawn the Rx and Tx tasks. */
+	uxBaseLED = uxLED;
+	xSerialPortInitMinimal( ulBaudRate, comBUFFER_LEN );
+
+	/* The Tx task is spawned with a lower priority than the Rx task. */
+	xTaskCreate( vComTxTask, "COMTx", comSTACK_SIZE, NULL, uxPriority - 1, ( TaskHandle_t * ) NULL );
+	xTaskCreate( vComRxTask, "COMRx", comSTACK_SIZE, NULL, uxPriority, ( TaskHandle_t * ) NULL );
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vComTxTask, pvParameters )
+{
+char cByteToSend;
+TickType_t xTimeToWait;
+
+	/* Just to stop compiler warnings. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		/* Simply transmit a sequence of characters from comFIRST_BYTE to
+		comLAST_BYTE. */
+		for( cByteToSend = comFIRST_BYTE; cByteToSend <= comLAST_BYTE; cByteToSend++ )
+		{
+			if( xSerialPutChar( xPort, cByteToSend, comNO_BLOCK ) == pdPASS )
+			{
+				vParTestToggleLED( uxBaseLED + comTX_LED_OFFSET );
+			}
+		}
+
+		/* Turn the LED off while we are not doing anything. */
+		vParTestSetLED( uxBaseLED + comTX_LED_OFFSET, pdFALSE );
+
+		/* We have posted all the characters in the string - wait before
+		re-sending.  Wait a pseudo-random time as this will provide a better
+		test. */
+		xTimeToWait = xTaskGetTickCount() + comOFFSET_TIME;
+
+		/* Make sure we don't wait too long... */
+		xTimeToWait %= comTX_MAX_BLOCK_TIME;
+
+		/* ...but we do want to wait. */
+		if( xTimeToWait < comTX_MIN_BLOCK_TIME )
+		{
+			xTimeToWait = comTX_MIN_BLOCK_TIME;
+		}
+
+		vTaskDelay( xTimeToWait );
+	}
+} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vComRxTask, pvParameters )
+{
+signed char cExpectedByte, cByteRxed;
+BaseType_t xResyncRequired = pdFALSE, xErrorOccurred = pdFALSE;
+
+	/* Just to stop compiler warnings. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		/* We expect to receive the characters from comFIRST_BYTE to
+		comLAST_BYTE in an incrementing order.  Loop to receive each byte. */
+		for( cExpectedByte = comFIRST_BYTE; cExpectedByte <= comLAST_BYTE; cExpectedByte++ )
+		{
+			/* Block on the queue that contains received bytes until a byte is
+			available. */
+			if( xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME ) )
+			{
+				/* Was this the byte we were expecting?  If so, toggle the LED,
+				otherwise we are out on sync and should break out of the loop
+				until the expected character sequence is about to restart. */
+				if( cByteRxed == cExpectedByte )
+				{
+					vParTestToggleLED( uxBaseLED + comRX_LED_OFFSET );
+				}
+				else
+				{
+					xResyncRequired = pdTRUE;
+					break; /*lint !e960 Non-switch break allowed. */
+				}
+			}
+		}
+
+		/* Turn the LED off while we are not doing anything. */
+		vParTestSetLED( uxBaseLED + comRX_LED_OFFSET, pdFALSE );
+
+		/* Did we break out of the loop because the characters were received in
+		an unexpected order?  If so wait here until the character sequence is
+		about to restart. */
+		if( xResyncRequired == pdTRUE )
+		{
+			while( cByteRxed != comLAST_BYTE )
+			{
+				/* Block until the next char is available. */
+				xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME );
+			}
+
+			/* Note that an error occurred which caused us to have to resync.
+			We use this to stop incrementing the loop counter so
+			sAreComTestTasksStillRunning() will return false - indicating an
+			error. */
+			xErrorOccurred++;
+
+			/* We have now resynced with the Tx task and can continue. */
+			xResyncRequired = pdFALSE;
+		}
+		else
+		{
+			if( xErrorOccurred < comTOTAL_PERMISSIBLE_ERRORS )
+			{
+				/* Increment the count of successful loops.  As error
+				occurring (i.e. an unexpected character being received) will
+				prevent this counter being incremented for the rest of the
+				execution.   Don't worry about mutual exclusion on this
+				variable - it doesn't really matter as we just want it
+				to change. */
+				uxRxLoops++;
+			}
+		}
+	}
+} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */
+/*-----------------------------------------------------------*/
+
+BaseType_t xAreComTestTasksStillRunning( void )
+{
+BaseType_t xReturn;
+
+	/* If the count of successful reception loops has not changed than at
+	some time an error occurred (i.e. a character was received out of sequence)
+	and we will return false. */
+	if( uxRxLoops == comINITIAL_RX_COUNT_VALUE )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	/* Reset the count of successful Rx loops.  When this function is called
+	again we expect this to have been incremented. */
+	uxRxLoops = comINITIAL_RX_COUNT_VALUE;
+
+	return xReturn;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/comtest_strings.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/comtest_strings.c
new file mode 100644
index 0000000..286725d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/comtest_strings.c
@@ -0,0 +1,311 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*
+ * Creates a task and a timer that operate on an interrupt driven serial port.
+ * This demo assumes that the characters transmitted on a port will also be
+ * received on the same port.  Therefore, the UART must either be connected to
+ * an echo server, or the uart connector must have a loopback connector fitted.
+ * See http://www.serialporttool.com/CommEcho.htm for a suitable echo server
+ * for Windows hosts.
+ *
+ * The timer sends a string to the UART, toggles an LED, then resets itself by
+ * changing its own period.  The period is calculated as a pseudo random number
+ * between comTX_MAX_BLOCK_TIME and comTX_MIN_BLOCK_TIME.
+ *
+ * The task blocks on an Rx queue waiting for a character to become available.
+ * Received characters are checked to ensure they match those transmitted by the
+ * Tx timer.  An error is latched if characters are missing, incorrect, or
+ * arrive too slowly.
+ *
+ * How characters are actually transmitted and received is port specific.  Demos
+ * that include this test/demo file will provide example drivers.  The Tx timer
+ * executes in the context of the timer service (daemon) task, and must
+ * therefore never attempt to block.
+ *
+ */
+
+/* Scheduler include files. */
+#include 
+#include 
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+
+#ifndef configUSE_TIMERS
+	#error This demo uses timers.  configUSE_TIMERS must be set to 1 in FreeRTOSConfig.h.
+#endif
+
+#if configUSE_TIMERS != 1
+	#error This demo uses timers.  configUSE_TIMERS must be set to 1 in FreeRTOSConfig.h.
+#endif
+
+
+/* Demo program include files. */
+#include "serial.h"
+#include "comtest_strings.h"
+#include "partest.h"
+
+/* The size of the stack given to the Rx task. */
+#define comSTACK_SIZE				configMINIMAL_STACK_SIZE
+
+/* See the comment above the declaraction of the uxBaseLED variable. */
+#define comTX_LED_OFFSET			( 0 )
+#define comRX_LED_OFFSET			( 1 )
+
+/* The Tx timer transmits the sequence of characters at a pseudo random
+interval that is capped between comTX_MAX_BLOCK_TIME and
+comTX_MIN_BLOCK_TIME. */
+#define comTX_MAX_BLOCK_TIME		( ( TickType_t ) 0x96 )
+#define comTX_MIN_BLOCK_TIME		( ( TickType_t ) 0x32 )
+#define comOFFSET_TIME				( ( TickType_t ) 3 )
+
+/* States for the simple state machine implemented in the Rx task. */
+#define comtstWAITING_START_OF_STRING 	0
+#define comtstWAITING_END_OF_STRING		1
+
+/* A short delay in ticks - this delay is used to allow the Rx queue to fill up
+a bit so more than one character can be processed at a time.  This is relative
+to comTX_MIN_BLOCK_TIME to ensure it is never longer than the shortest gap
+between transmissions.  It could be worked out more scientifically from the
+baud rate being used. */
+#define comSHORT_DELAY				( comTX_MIN_BLOCK_TIME >> ( TickType_t ) 2 )
+
+/* The string that is transmitted and received. */
+#define comTRANSACTED_STRING		"abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ1234567890"
+
+/* A block time of 0 simply means "don't block". */
+#define comtstDONT_BLOCK			( TickType_t ) 0
+
+/* Handle to the com port used by both tasks. */
+static xComPortHandle xPort = NULL;
+
+/* The callback function allocated to the transmit timer, as described in the
+comments at the top of this file. */
+static void prvComTxTimerCallback( TimerHandle_t xTimer );
+
+/* The receive task as described in the comments at the top of this file. */
+static void vComRxTask( void *pvParameters );
+
+/* The Rx task will toggle LED ( uxBaseLED + comRX_LED_OFFSET).  The Tx task
+will toggle LED ( uxBaseLED + comTX_LED_OFFSET ). */
+static UBaseType_t uxBaseLED = 0;
+
+/* The Rx task toggles uxRxLoops on each successful iteration of its defined
+function - provided no errors have ever been latched.  If this variable stops
+incrementing, then an error has occurred. */
+static volatile UBaseType_t uxRxLoops = 0UL;
+
+/* The timer used to periodically transmit the string.  This is the timer that
+has prvComTxTimerCallback allocated to it as its callback function. */
+static TimerHandle_t xTxTimer = NULL;
+
+/* The string length is held at file scope so the Tx timer does not need to
+calculate it each time it executes. */
+static size_t xStringLength = 0U;
+
+/*-----------------------------------------------------------*/
+
+void vStartComTestStringsTasks( UBaseType_t uxPriority, uint32_t ulBaudRate, UBaseType_t uxLED )
+{
+	/* Store values that are used at run time. */
+	uxBaseLED = uxLED;
+
+	/* Calculate the string length here, rather than each time the Tx timer
+	executes. */
+	xStringLength = strlen( comTRANSACTED_STRING );
+
+	/* Include the null terminator in the string length as this is used to
+	detect the end of the string in the Rx task. */
+	xStringLength++;
+
+	/* Initialise the com port, then spawn the Rx task and create the Tx
+	timer. */
+	xSerialPortInitMinimal( ulBaudRate, ( xStringLength * 2U ) );
+
+	/* Create the Rx task and the Tx timer.  The timer is started from the
+	Rx task. */
+	xTaskCreate( vComRxTask, "COMRx", comSTACK_SIZE, NULL, uxPriority, ( TaskHandle_t * ) NULL );
+	xTxTimer = xTimerCreate( "TxTimer", comTX_MIN_BLOCK_TIME, pdFALSE, NULL, prvComTxTimerCallback );
+	configASSERT( xTxTimer );
+}
+/*-----------------------------------------------------------*/
+
+static void prvComTxTimerCallback( TimerHandle_t xTimer )
+{
+TickType_t xTimeToWait;
+
+	/* The parameter is not used in this case. */
+	( void ) xTimer;
+
+	/* Send the string.  How this is actually performed depends on the
+	sample driver provided with this demo.  However - as this is a timer,
+	it executes in the context of the timer task and therefore must not
+	block. */
+	vSerialPutString( xPort, comTRANSACTED_STRING, xStringLength );
+
+	/* Toggle an LED to give a visible indication that another transmission
+	has been performed. */
+	vParTestToggleLED( uxBaseLED + comTX_LED_OFFSET );
+
+	/* Wait a pseudo random time before sending the string again. */
+	xTimeToWait = xTaskGetTickCount() + comOFFSET_TIME;
+
+	/* Ensure the time to wait is not greater than comTX_MAX_BLOCK_TIME. */
+	xTimeToWait %= comTX_MAX_BLOCK_TIME;
+
+	/* Ensure the time to wait is not less than comTX_MIN_BLOCK_TIME. */
+	if( xTimeToWait < comTX_MIN_BLOCK_TIME )
+	{
+		xTimeToWait = comTX_MIN_BLOCK_TIME;
+	}
+
+	/* Reset the timer to run again xTimeToWait ticks from now.  This function
+	is called from the context of the timer task, so the block time must not
+	be anything other than zero. */
+	xTimerChangePeriod( xTxTimer, xTimeToWait, comtstDONT_BLOCK );
+}
+/*-----------------------------------------------------------*/
+
+static void vComRxTask( void *pvParameters )
+{
+BaseType_t xState = comtstWAITING_START_OF_STRING, xErrorOccurred = pdFALSE;
+char *pcExpectedByte, cRxedChar;
+const xComPortHandle xPort = NULL;
+
+	/* The parameter is not used in this example. */
+	( void ) pvParameters;
+
+	/* Start the Tx timer.  This only needs to be started once, as it will
+	reset itself thereafter. */
+	xTimerStart( xTxTimer, portMAX_DELAY );
+
+	/* The first expected Rx character is the first in the string that is
+	transmitted. */
+	pcExpectedByte = comTRANSACTED_STRING;
+
+	for( ;; )
+	{
+		/* Wait for the next character. */
+		if( xSerialGetChar( xPort, &cRxedChar, ( comTX_MAX_BLOCK_TIME * 2 ) ) == pdFALSE )
+		{
+			/* A character definitely should have been received by now.  As a
+			character was not received an error must have occurred (which might
+			just be that the loopback connector is not fitted). */
+			xErrorOccurred = pdTRUE;
+		}
+
+		switch( xState )
+		{
+			case comtstWAITING_START_OF_STRING:
+				if( cRxedChar == *pcExpectedByte )
+				{
+					/* The received character was the first character of the
+					string.  Move to the next state to check each character
+					as it comes in until the entire string has been received. */
+					xState = comtstWAITING_END_OF_STRING;
+					pcExpectedByte++;
+
+					/* Block for a short period.  This just allows the Rx queue
+					to contain more than one character, and therefore prevent
+					thrashing reads to the queue, and repetitive context
+					switches as	each character is received. */
+					vTaskDelay( comSHORT_DELAY );
+				}
+				break;
+
+			case comtstWAITING_END_OF_STRING:
+				if( cRxedChar == *pcExpectedByte )
+				{
+					/* The received character was the expected character.  Was
+					it the last character in the string - i.e. the null
+					terminator? */
+					if( cRxedChar == 0x00 )
+					{
+						/* The entire string has been received.  If no errors
+						have been latched, then increment the loop counter to
+						show this task is still healthy. */
+						if( xErrorOccurred == pdFALSE )
+						{
+							uxRxLoops++;
+
+							/* Toggle an LED to give a visible sign that a
+							complete string has been received. */
+							vParTestToggleLED( uxBaseLED + comRX_LED_OFFSET );
+						}
+
+						/* Go back to wait for the start of the next string. */
+						pcExpectedByte = comTRANSACTED_STRING;
+						xState = comtstWAITING_START_OF_STRING;
+					}
+					else
+					{
+						/* Wait for the next character in the string. */
+						pcExpectedByte++;
+					}
+				}
+				else
+				{
+					/* The character received was not that expected. */
+					xErrorOccurred = pdTRUE;
+				}
+				break;
+
+			default:
+				/* Should not get here.  Stop the Rx loop counter from
+				incrementing to latch the error. */
+				xErrorOccurred = pdTRUE;
+				break;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xAreComTestTasksStillRunning( void )
+{
+BaseType_t xReturn;
+
+	/* If the count of successful reception loops has not changed than at
+	some time an error occurred (i.e. a character was received out of sequence)
+	and false is returned. */
+	if( uxRxLoops == 0UL )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	/* Reset the count of successful Rx loops.  When this function is called
+	again it should have been incremented again. */
+	uxRxLoops = 0UL;
+
+	return xReturn;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/countsem.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/countsem.c
new file mode 100644
index 0000000..5f49369
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/countsem.c
@@ -0,0 +1,288 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*
+ * Simple demonstration of the usage of counting semaphore.
+ */
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+
+/* Demo program include files. */
+#include "countsem.h"
+
+/* The maximum count value that the semaphore used for the demo can hold. */
+#define countMAX_COUNT_VALUE	( 200 )
+
+/* Constants used to indicate whether or not the semaphore should have been
+created with its maximum count value, or its minimum count value.  These
+numbers are used to ensure that the pointers passed in as the task parameters
+are valid. */
+#define countSTART_AT_MAX_COUNT	( 0xaa )
+#define countSTART_AT_ZERO		( 0x55 )
+
+/* Two tasks are created for the test.  One uses a semaphore created with its
+count value set to the maximum, and one with the count value set to zero. */
+#define countNUM_TEST_TASKS		( 2 )
+#define countDONT_BLOCK			( 0 )
+
+/*-----------------------------------------------------------*/
+
+/* Flag that will be latched to pdTRUE should any unexpected behaviour be
+detected in any of the tasks. */
+static volatile BaseType_t xErrorDetected = pdFALSE;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The demo task.  This simply counts the semaphore up to its maximum value,
+ * the counts it back down again.  The result of each semaphore 'give' and
+ * 'take' is inspected, with an error being flagged if it is found not to be
+ * the expected result.
+ */
+static void prvCountingSemaphoreTask( void *pvParameters );
+
+/*
+ * Utility function to increment the semaphore count value up from zero to
+ * countMAX_COUNT_VALUE.
+ */
+static void prvIncrementSemaphoreCount( SemaphoreHandle_t xSemaphore, volatile UBaseType_t *puxLoopCounter );
+
+/*
+ * Utility function to decrement the semaphore count value up from
+ * countMAX_COUNT_VALUE to zero.
+ */
+static void prvDecrementSemaphoreCount( SemaphoreHandle_t xSemaphore, volatile UBaseType_t *puxLoopCounter );
+
+/*-----------------------------------------------------------*/
+
+/* The structure that is passed into the task as the task parameter. */
+typedef struct COUNT_SEM_STRUCT
+{
+	/* The semaphore to be used for the demo. */
+	SemaphoreHandle_t xSemaphore;
+
+	/* Set to countSTART_AT_MAX_COUNT if the semaphore should be created with
+	its count value set to its max count value, or countSTART_AT_ZERO if it
+	should have been created with its count value set to 0. */
+	UBaseType_t uxExpectedStartCount;
+
+	/* Incremented on each cycle of the demo task.  Used to detect a stalled
+	task. */
+	volatile UBaseType_t uxLoopCounter;
+} xCountSemStruct;
+
+/* Two structures are defined, one is passed to each test task. */
+static xCountSemStruct xParameters[ countNUM_TEST_TASKS ];
+
+/*-----------------------------------------------------------*/
+
+void vStartCountingSemaphoreTasks( void )
+{
+	/* Create the semaphores that we are going to use for the test/demo.  The
+	first should be created such that it starts at its maximum count value,
+	the second should be created such that it starts with a count value of zero. */
+	xParameters[ 0 ].xSemaphore = xSemaphoreCreateCounting( countMAX_COUNT_VALUE, countMAX_COUNT_VALUE );
+	xParameters[ 0 ].uxExpectedStartCount = countSTART_AT_MAX_COUNT;
+	xParameters[ 0 ].uxLoopCounter = 0;
+
+	xParameters[ 1 ].xSemaphore = xSemaphoreCreateCounting( countMAX_COUNT_VALUE, 0 );
+	xParameters[ 1 ].uxExpectedStartCount = 0;
+	xParameters[ 1 ].uxLoopCounter = 0;
+
+	/* Were the semaphores created? */
+	if( ( xParameters[ 0 ].xSemaphore != NULL ) || ( xParameters[ 1 ].xSemaphore != NULL ) )
+	{
+		/* vQueueAddToRegistry() adds the semaphore to the registry, if one is
+		in use.  The registry is provided as a means for kernel aware
+		debuggers to locate semaphores and has no purpose if a kernel aware
+		debugger is not being used.  The call to vQueueAddToRegistry() will be
+		removed by the pre-processor if configQUEUE_REGISTRY_SIZE is not
+		defined or is defined to be less than 1. */
+		vQueueAddToRegistry( ( QueueHandle_t ) xParameters[ 0 ].xSemaphore, "Counting_Sem_1" );
+		vQueueAddToRegistry( ( QueueHandle_t ) xParameters[ 1 ].xSemaphore, "Counting_Sem_2" );
+
+		/* Create the demo tasks, passing in the semaphore to use as the parameter. */
+		xTaskCreate( prvCountingSemaphoreTask, "CNT1", configMINIMAL_STACK_SIZE, ( void * ) &( xParameters[ 0 ] ), tskIDLE_PRIORITY, NULL );
+		xTaskCreate( prvCountingSemaphoreTask, "CNT2", configMINIMAL_STACK_SIZE, ( void * ) &( xParameters[ 1 ] ), tskIDLE_PRIORITY, NULL );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvDecrementSemaphoreCount( SemaphoreHandle_t xSemaphore, volatile UBaseType_t *puxLoopCounter )
+{
+UBaseType_t ux;
+
+	/* If the semaphore count is at its maximum then we should not be able to
+	'give' the semaphore. */
+	if( xSemaphoreGive( xSemaphore ) == pdPASS )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* We should be able to 'take' the semaphore countMAX_COUNT_VALUE times. */
+	for( ux = 0; ux < countMAX_COUNT_VALUE; ux++ )
+	{
+		configASSERT( uxSemaphoreGetCount( xSemaphore ) == ( countMAX_COUNT_VALUE - ux ) );
+
+		if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) != pdPASS )
+		{
+			/* We expected to be able to take the semaphore. */
+			xErrorDetected = pdTRUE;
+		}
+
+		( *puxLoopCounter )++;
+	}
+
+	#if configUSE_PREEMPTION == 0
+		taskYIELD();
+	#endif
+
+	/* If the semaphore count is zero then we should not be able to	'take'
+	the semaphore. */
+	configASSERT( uxSemaphoreGetCount( xSemaphore ) == 0 );
+	if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) == pdPASS )
+	{
+		xErrorDetected = pdTRUE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvIncrementSemaphoreCount( SemaphoreHandle_t xSemaphore, volatile UBaseType_t *puxLoopCounter )
+{
+UBaseType_t ux;
+
+	/* If the semaphore count is zero then we should not be able to	'take'
+	the semaphore. */
+	if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) == pdPASS )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	/* We should be able to 'give' the semaphore countMAX_COUNT_VALUE times. */
+	for( ux = 0; ux < countMAX_COUNT_VALUE; ux++ )
+	{
+		configASSERT( uxSemaphoreGetCount( xSemaphore ) == ux );
+
+		if( xSemaphoreGive( xSemaphore ) != pdPASS )
+		{
+			/* We expected to be able to take the semaphore. */
+			xErrorDetected = pdTRUE;
+		}
+
+		( *puxLoopCounter )++;
+	}
+
+	#if configUSE_PREEMPTION == 0
+		taskYIELD();
+	#endif
+
+	/* If the semaphore count is at its maximum then we should not be able to
+	'give' the semaphore. */
+	if( xSemaphoreGive( xSemaphore ) == pdPASS )
+	{
+		xErrorDetected = pdTRUE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvCountingSemaphoreTask( void *pvParameters )
+{
+xCountSemStruct *pxParameter;
+
+	#ifdef USE_STDIO
+	void vPrintDisplayMessage( const char * const * ppcMessageToSend );
+
+		const char * const pcTaskStartMsg = "Counting semaphore demo started.\r\n";
+
+		/* Queue a message for printing to say the task has started. */
+		vPrintDisplayMessage( &pcTaskStartMsg );
+	#endif
+
+	/* The semaphore to be used was passed as the parameter. */
+	pxParameter = ( xCountSemStruct * ) pvParameters;
+
+	/* Did we expect to find the semaphore already at its max count value, or
+	at zero? */
+	if( pxParameter->uxExpectedStartCount == countSTART_AT_MAX_COUNT )
+	{
+		prvDecrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) );
+	}
+
+	/* Now we expect the semaphore count to be 0, so this time there is an
+	error if we can take the semaphore. */
+	if( xSemaphoreTake( pxParameter->xSemaphore, 0 ) == pdPASS )
+	{
+		xErrorDetected = pdTRUE;
+	}
+
+	for( ;; )
+	{
+		prvIncrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) );
+		prvDecrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xAreCountingSemaphoreTasksStillRunning( void )
+{
+static UBaseType_t uxLastCount0 = 0, uxLastCount1 = 0;
+BaseType_t xReturn = pdPASS;
+
+	/* Return fail if any 'give' or 'take' did not result in the expected
+	behaviour. */
+	if( xErrorDetected != pdFALSE )
+	{
+		xReturn = pdFAIL;
+	}
+
+	/* Return fail if either task is not still incrementing its loop counter. */
+	if( uxLastCount0 == xParameters[ 0 ].uxLoopCounter )
+	{
+		xReturn = pdFAIL;
+	}
+	else
+	{
+		uxLastCount0 = xParameters[ 0 ].uxLoopCounter;
+	}
+
+	if( uxLastCount1 == xParameters[ 1 ].uxLoopCounter )
+	{
+		xReturn = pdFAIL;
+	}
+	else
+	{
+		uxLastCount1 = xParameters[ 1 ].uxLoopCounter;
+	}
+
+	return xReturn;
+}
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/crflash.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/crflash.c
new file mode 100644
index 0000000..23f553b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/crflash.c
@@ -0,0 +1,208 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * This demo application file demonstrates the use of queues to pass data
+ * between co-routines.
+ *
+ * N represents the number of 'fixed delay' co-routines that are created and
+ * is set during initialisation.
+ *
+ * N 'fixed delay' co-routines are created that just block for a fixed
+ * period then post the number of an LED onto a queue.  Each such co-routine
+ * uses a different block period.  A single 'flash' co-routine is also created
+ * that blocks on the same queue, waiting for the number of the next LED it
+ * should flash.  Upon receiving a number it simply toggle the instructed LED
+ * then blocks on the queue once more.  In this manner each LED from LED 0 to
+ * LED N-1 is caused to flash at a different rate.
+ *
+ * The 'fixed delay' co-routines are created with co-routine priority 0.  The
+ * flash co-routine is created with co-routine priority 1.  This means that
+ * the queue should never contain more than a single item.  This is because
+ * posting to the queue will unblock the 'flash' co-routine, and as this has
+ * a priority greater than the tasks posting to the queue it is guaranteed to
+ * have emptied the queue and blocked once again before the queue can contain
+ * any more date.  An error is indicated if an attempt to post data to the
+ * queue fails - indicating that the queue is already full.
+ *
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "croutine.h"
+#include "queue.h"
+
+/* Demo application includes. */
+#include "partest.h"
+#include "crflash.h"
+
+/* The queue should only need to be of length 1.  See the description at the
+top of the file. */
+#define crfQUEUE_LENGTH		1
+
+#define crfFIXED_DELAY_PRIORITY		0
+#define crfFLASH_PRIORITY			1
+
+/* Only one flash co-routine is created so the index is not significant. */
+#define crfFLASH_INDEX				0
+
+/* Don't allow more than crfMAX_FLASH_TASKS 'fixed delay' co-routines to be
+created. */
+#define crfMAX_FLASH_TASKS			8
+
+/* We don't want to block when posting to the queue. */
+#define crfPOSTING_BLOCK_TIME		0
+
+/*
+ * The 'fixed delay' co-routine as described at the top of the file.
+ */
+static void prvFixedDelayCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex );
+
+/*
+ * The 'flash' co-routine as described at the top of the file.
+ */
+static void prvFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex );
+
+/* The queue used to pass data between the 'fixed delay' co-routines and the
+'flash' co-routine. */
+static QueueHandle_t xFlashQueue;
+
+/* This will be set to pdFALSE if we detect an error. */
+static BaseType_t xCoRoutineFlashStatus = pdPASS;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See the header file for details.
+ */
+void vStartFlashCoRoutines( UBaseType_t uxNumberToCreate )
+{
+UBaseType_t uxIndex;
+
+	if( uxNumberToCreate > crfMAX_FLASH_TASKS )
+	{
+		uxNumberToCreate = crfMAX_FLASH_TASKS;
+	}
+
+	/* Create the queue used to pass data between the co-routines. */
+	xFlashQueue = xQueueCreate( crfQUEUE_LENGTH, sizeof( UBaseType_t ) );
+
+	if( xFlashQueue )
+	{
+		/* Create uxNumberToCreate 'fixed delay' co-routines. */
+		for( uxIndex = 0; uxIndex < uxNumberToCreate; uxIndex++ )
+		{
+			xCoRoutineCreate( prvFixedDelayCoRoutine, crfFIXED_DELAY_PRIORITY, uxIndex );
+		}
+
+		/* Create the 'flash' co-routine. */
+		xCoRoutineCreate( prvFlashCoRoutine, crfFLASH_PRIORITY, crfFLASH_INDEX );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvFixedDelayCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+{
+/* Even though this is a co-routine the xResult variable does not need to be
+static as we do not need it to maintain its state between blocks. */
+BaseType_t xResult;
+/* The uxIndex parameter of the co-routine function is used as an index into
+the xFlashRates array to obtain the delay period to use. */
+static const TickType_t xFlashRates[ crfMAX_FLASH_TASKS ] = { 150 / portTICK_PERIOD_MS,
+																200 / portTICK_PERIOD_MS,
+																250 / portTICK_PERIOD_MS,
+																300 / portTICK_PERIOD_MS,
+																350 / portTICK_PERIOD_MS,
+																400 / portTICK_PERIOD_MS,
+																450 / portTICK_PERIOD_MS,
+																500  / portTICK_PERIOD_MS };
+
+	/* Co-routines MUST start with a call to crSTART. */
+	crSTART( xHandle );
+
+	for( ;; )
+	{
+		/* Post our uxIndex value onto the queue.  This is used as the LED to
+		flash. */
+		crQUEUE_SEND( xHandle, xFlashQueue, ( void * ) &uxIndex, crfPOSTING_BLOCK_TIME, &xResult );
+
+		if( xResult != pdPASS )
+		{
+			/* For the reasons stated at the top of the file we should always
+			find that we can post to the queue.  If we could not then an error
+			has occurred. */
+			xCoRoutineFlashStatus = pdFAIL;
+		}
+
+		crDELAY( xHandle, xFlashRates[ uxIndex ] );
+	}
+
+	/* Co-routines MUST end with a call to crEND. */
+	crEND();
+}
+/*-----------------------------------------------------------*/
+
+static void prvFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+{
+/* Even though this is a co-routine the variable do not need to be
+static as we do not need it to maintain their state between blocks. */
+BaseType_t xResult;
+UBaseType_t uxLEDToFlash;
+
+	/* Co-routines MUST start with a call to crSTART. */
+	crSTART( xHandle );
+	( void ) uxIndex;
+
+	for( ;; )
+	{
+		/* Block to wait for the number of the LED to flash. */
+		crQUEUE_RECEIVE( xHandle, xFlashQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+		if( xResult != pdPASS )
+		{
+			/* We would not expect to wake unless we received something. */
+			xCoRoutineFlashStatus = pdFAIL;
+		}
+		else
+		{
+			/* We received the number of an LED to flash - flash it! */
+			vParTestToggleLED( uxLEDToFlash );
+		}
+	}
+
+	/* Co-routines MUST end with a call to crEND. */
+	crEND();
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xAreFlashCoRoutinesStillRunning( void )
+{
+	/* Return pdPASS or pdFAIL depending on whether an error has been detected
+	or not. */
+	return xCoRoutineFlashStatus;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/crhook.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/crhook.c
new file mode 100644
index 0000000..6069ada
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/crhook.c
@@ -0,0 +1,232 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * This demo file demonstrates how to send data between an ISR and a
+ * co-routine.  A tick hook function is used to periodically pass data between
+ * the RTOS tick and a set of 'hook' co-routines.
+ *
+ * hookNUM_HOOK_CO_ROUTINES co-routines are created.  Each co-routine blocks
+ * to wait for a character to be received on a queue from the tick ISR, checks
+ * to ensure the character received was that expected, then sends the number
+ * back to the tick ISR on a different queue.
+ *
+ * The tick ISR checks the numbers received back from the 'hook' co-routines
+ * matches the number previously sent.
+ *
+ * If at any time a queue function returns unexpectedly, or an incorrect value
+ * is received either by the tick hook or a co-routine then an error is
+ * latched.
+ *
+ * This demo relies on each 'hook' co-routine to execute between each
+ * hookTICK_CALLS_BEFORE_POST tick interrupts.  This and the heavy use of
+ * queues from within an interrupt may result in an error being detected on
+ * slower targets simply due to timing.
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "croutine.h"
+#include "queue.h"
+
+/* Demo application includes. */
+#include "crhook.h"
+
+/* The number of 'hook' co-routines that are to be created. */
+#define hookNUM_HOOK_CO_ROUTINES        ( 4 )
+
+/* The number of times the tick hook should be called before a character is
+posted to the 'hook' co-routines. */
+#define hookTICK_CALLS_BEFORE_POST      ( 500 )
+
+/* There should never be more than one item in any queue at any time. */
+#define hookHOOK_QUEUE_LENGTH           ( 1 )
+
+/* Don't block when initially posting to the queue. */
+#define hookNO_BLOCK_TIME               ( 0 )
+
+/* The priority relative to other co-routines (rather than tasks) that the
+'hook' co-routines should take. */
+#define mainHOOK_CR_PRIORITY			( 1 )
+/*-----------------------------------------------------------*/
+
+/*
+ * The co-routine function itself.
+ */
+static void prvHookCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex );
+
+
+/*
+ * The tick hook function.  This receives a number from each 'hook' co-routine
+ * then sends a number to each co-routine.  An error is flagged if a send or
+ * receive fails, or an unexpected number is received.
+ */
+void vApplicationTickHook( void );
+
+/*-----------------------------------------------------------*/
+
+/* Queues used to send data FROM a co-routine TO the tick hook function.
+The hook functions received (Rx's) on these queues.  One queue per
+'hook' co-routine. */
+static QueueHandle_t xHookRxQueues[ hookNUM_HOOK_CO_ROUTINES ];
+
+/* Queues used to send data FROM the tick hook TO a co-routine function.
+The hood function transmits (Tx's) on these queues.  One queue per
+'hook' co-routine. */
+static QueueHandle_t xHookTxQueues[ hookNUM_HOOK_CO_ROUTINES ];
+
+/* Set to true if an error is detected at any time. */
+static BaseType_t xCoRoutineErrorDetected = pdFALSE;
+
+/*-----------------------------------------------------------*/
+
+void vStartHookCoRoutines( void )
+{
+UBaseType_t uxIndex, uxValueToPost = 0;
+
+	for( uxIndex = 0; uxIndex < hookNUM_HOOK_CO_ROUTINES; uxIndex++ )
+	{
+		/* Create a queue to transmit to and receive from each 'hook'
+		co-routine. */
+		xHookRxQueues[ uxIndex ] = xQueueCreate( hookHOOK_QUEUE_LENGTH, sizeof( UBaseType_t ) );
+		xHookTxQueues[ uxIndex ] = xQueueCreate( hookHOOK_QUEUE_LENGTH, sizeof( UBaseType_t ) );
+
+		/* To start things off the tick hook function expects the queue it
+		uses to receive data to contain a value.  */
+		xQueueSend( xHookRxQueues[ uxIndex ], &uxValueToPost, hookNO_BLOCK_TIME );
+
+		/* Create the 'hook' co-routine itself. */
+		xCoRoutineCreate( prvHookCoRoutine, mainHOOK_CR_PRIORITY, uxIndex );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static UBaseType_t uxCallCounter = 0, uxNumberToPost = 0;
+void vApplicationTickHook( void )
+{
+UBaseType_t uxReceivedNumber;
+BaseType_t xIndex, xCoRoutineWoken;
+
+	/* Is it time to talk to the 'hook' co-routines again? */
+	uxCallCounter++;
+	if( uxCallCounter >= hookTICK_CALLS_BEFORE_POST )
+	{
+		uxCallCounter = 0;
+
+		for( xIndex = 0; xIndex < hookNUM_HOOK_CO_ROUTINES; xIndex++ )
+		{
+			xCoRoutineWoken = pdFALSE;
+			if( crQUEUE_RECEIVE_FROM_ISR( xHookRxQueues[ xIndex ], &uxReceivedNumber, &xCoRoutineWoken ) != pdPASS )
+			{
+				/* There is no reason why we would not expect the queue to
+				contain a value. */
+				xCoRoutineErrorDetected = pdTRUE;
+			}
+			else
+			{
+				/* Each queue used to receive data from the 'hook' co-routines
+				should contain the number we last posted to the same co-routine. */
+				if( uxReceivedNumber != uxNumberToPost )
+				{
+					xCoRoutineErrorDetected = pdTRUE;
+				}
+
+				/* Nothing should be blocked waiting to post to the queue. */
+				if( xCoRoutineWoken != pdFALSE )
+				{
+					xCoRoutineErrorDetected = pdTRUE;
+				}
+			}
+		}
+
+		/* Start the next cycle by posting the next number onto each Tx queue. */
+		uxNumberToPost++;
+
+		for( xIndex = 0; xIndex < hookNUM_HOOK_CO_ROUTINES; xIndex++ )
+		{
+			if( crQUEUE_SEND_FROM_ISR( xHookTxQueues[ xIndex ], &uxNumberToPost, pdFALSE ) != pdTRUE )
+			{
+				/* Posting to the queue should have woken the co-routine that
+				was blocked on the queue. */
+				xCoRoutineErrorDetected = pdTRUE;
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvHookCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+{
+static UBaseType_t uxReceivedValue[ hookNUM_HOOK_CO_ROUTINES ];
+BaseType_t xResult;
+
+	/* Each co-routine MUST start with a call to crSTART(); */
+	crSTART( xHandle );
+
+	for( ;; )
+	{
+		/* Wait to receive a value from the tick hook. */
+		xResult = pdFAIL;
+		crQUEUE_RECEIVE( xHandle, xHookTxQueues[ uxIndex ], &( uxReceivedValue[ uxIndex ] ), portMAX_DELAY, &xResult );
+
+		/* There is no reason why we should not have received something on
+		the queue. */
+		if( xResult != pdPASS )
+		{
+			xCoRoutineErrorDetected = pdTRUE;
+		}
+
+		/* Send the same number back to the idle hook so it can verify it. */
+		xResult = pdFAIL;
+		crQUEUE_SEND( xHandle, xHookRxQueues[ uxIndex ], &( uxReceivedValue[ uxIndex ] ), hookNO_BLOCK_TIME, &xResult );
+		if( xResult != pdPASS )
+		{
+			/* There is no reason why we should not have been able to post to
+			the queue. */
+			xCoRoutineErrorDetected = pdTRUE;
+		}
+	}
+
+	/* Each co-routine MUST end with a call to crEND(). */
+	crEND();
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xAreHookCoRoutinesStillRunning( void )
+{
+	if( xCoRoutineErrorDetected )
+	{
+		return pdFALSE;
+	}
+	else
+	{
+		return pdTRUE;
+	}
+}
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/death.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/death.c
new file mode 100644
index 0000000..b2fa898
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/death.c
@@ -0,0 +1,203 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/**
+ * Create a single persistent task which periodically dynamically creates another
+ * two tasks.  The original task is called the creator task, the two tasks it
+ * creates are called suicidal tasks.
+ *
+ * One of the created suicidal tasks kill one other suicidal task before killing
+ * itself - leaving just the original task remaining.
+ *
+ * The creator task must be spawned after all of the other demo application tasks
+ * as it keeps a check on the number of tasks under the scheduler control.  The
+ * number of tasks it expects to see running should never be greater than the
+ * number of tasks that were in existence when the creator task was spawned, plus
+ * one set of four suicidal tasks.  If this number is exceeded an error is flagged.
+ *
+ * \page DeathC death.c
+ * \ingroup DemoFiles
+ * 

+ */
+
+
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo program include files. */
+#include "death.h"
+
+#define deathSTACK_SIZE		( configMINIMAL_STACK_SIZE + 60 )
+
+/* The task originally created which is responsible for periodically dynamically
+creating another four tasks. */
+static portTASK_FUNCTION_PROTO( vCreateTasks, pvParameters );
+
+/* The task function of the dynamically created tasks. */
+static portTASK_FUNCTION_PROTO( vSuicidalTask, pvParameters );
+
+/* A variable which is incremented every time the dynamic tasks are created.  This
+is used to check that the task is still running. */
+static volatile uint16_t usCreationCount = 0;
+
+/* Used to store the number of tasks that were originally running so the creator
+task can tell if any of the suicidal tasks have failed to die.
+*/
+static volatile UBaseType_t uxTasksRunningAtStart = 0;
+
+/* When a task deletes itself, it stack and TCB are cleaned up by the Idle task.
+Under heavy load the idle task might not get much processing time, so it would
+be legitimate for several tasks to remain undeleted for a short period.  There
+may also be a few other unexpected tasks if, for example, the tasks that test
+static allocation are also being used. */
+static const UBaseType_t uxMaxNumberOfExtraTasksRunning = 3;
+
+/* Used to store a handle to the task that should be killed by a suicidal task,
+before it kills itself. */
+TaskHandle_t xCreatedTask;
+
+/*-----------------------------------------------------------*/
+
+void vCreateSuicidalTasks( UBaseType_t uxPriority )
+{
+	xTaskCreate( vCreateTasks, "CREATOR", deathSTACK_SIZE, ( void * ) NULL, uxPriority, NULL );
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vSuicidalTask, pvParameters )
+{
+volatile long l1, l2;
+TaskHandle_t xTaskToKill;
+const TickType_t xDelay = pdMS_TO_TICKS( ( TickType_t ) 200 );
+
+	/* Test deletion of a task's secure context, if any. */
+	portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
+
+	if( pvParameters != NULL )
+	{
+		/* This task is periodically created four times.  Two created tasks are
+		passed a handle to the other task so it can kill it before killing itself.
+		The other task is passed in null. */
+		xTaskToKill = *( TaskHandle_t* )pvParameters;
+	}
+	else
+	{
+		xTaskToKill = NULL;
+	}
+
+	for( ;; )
+	{
+		/* Do something random just to use some stack and registers. */
+		l1 = 2;
+		l2 = 89;
+		l2 *= l1;
+		vTaskDelay( xDelay );
+
+		if( xTaskToKill != NULL )
+		{
+			/* Make sure the other task has a go before we delete it. */
+			vTaskDelay( ( TickType_t ) 0 );
+
+			/* Kill the other task that was created by vCreateTasks(). */
+			vTaskDelete( xTaskToKill );
+
+			/* Kill ourselves. */
+			vTaskDelete( NULL );
+		}
+	}
+}/*lint !e818 !e550 Function prototype must be as per standard for task functions. */
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vCreateTasks, pvParameters )
+{
+const TickType_t xDelay = pdMS_TO_TICKS( ( TickType_t ) 1000 );
+UBaseType_t uxPriority;
+
+	/* Remove compiler warning about unused parameter. */
+	( void ) pvParameters;
+
+	/* Delay at the start to ensure tasks created by other demos have been
+	created before storing the current number of tasks. */
+	vTaskDelay( xDelay );
+	uxTasksRunningAtStart = ( UBaseType_t ) uxTaskGetNumberOfTasks();
+
+	uxPriority = uxTaskPriorityGet( NULL );
+
+	for( ;; )
+	{
+		/* Just loop round, delaying then creating the four suicidal tasks. */
+		vTaskDelay( xDelay );
+
+		xCreatedTask = NULL;
+
+		xTaskCreate( vSuicidalTask, "SUICID1", configMINIMAL_STACK_SIZE, NULL, uxPriority, &xCreatedTask );
+		xTaskCreate( vSuicidalTask, "SUICID2", configMINIMAL_STACK_SIZE, &xCreatedTask, uxPriority, NULL );
+
+		++usCreationCount;
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* This is called to check that the creator task is still running and that there
+are not any more than four extra tasks. */
+BaseType_t xIsCreateTaskStillRunning( void )
+{
+static uint16_t usLastCreationCount = 0xfff;
+BaseType_t xReturn = pdTRUE;
+static UBaseType_t uxTasksRunningNow;
+
+	if( usLastCreationCount == usCreationCount )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		usLastCreationCount = usCreationCount;
+	}
+
+	uxTasksRunningNow = ( UBaseType_t ) uxTaskGetNumberOfTasks();
+
+	if( uxTasksRunningNow < uxTasksRunningAtStart )
+	{
+		xReturn = pdFALSE;
+	}
+	else if( ( uxTasksRunningNow - uxTasksRunningAtStart ) > uxMaxNumberOfExtraTasksRunning )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		/* Everything is okay. */
+	}
+
+	return xReturn;
+}
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/dynamic.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/dynamic.c
new file mode 100644
index 0000000..26ccdf0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/dynamic.c
@@ -0,0 +1,479 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * The first test creates three tasks - two counter tasks (one continuous count
+ * and one limited count) and one controller.  A "count" variable is shared
+ * between all three tasks.  The two counter tasks should never be in a "ready"
+ * state at the same time.  The controller task runs at the same priority as
+ * the continuous count task, and at a lower priority than the limited count
+ * task.
+ *
+ * One counter task loops indefinitely, incrementing the shared count variable
+ * on each iteration.  To ensure it has exclusive access to the variable it
+ * raises its priority above that of the controller task before each
+ * increment, lowering it again to its original priority before starting the
+ * next iteration.
+ *
+ * The other counter task increments the shared count variable on each
+ * iteration of its loop until the count has reached a limit of 0xff - at
+ * which point it suspends itself.  It will not start a new loop until the
+ * controller task has made it "ready" again by calling vTaskResume().
+ * This second counter task operates at a higher priority than controller
+ * task so does not need to worry about mutual exclusion of the counter
+ * variable.
+ *
+ * The controller task is in two sections.  The first section controls and
+ * monitors the continuous count task.  When this section is operational the
+ * limited count task is suspended.  Likewise, the second section controls
+ * and monitors the limited count task.  When this section is operational the
+ * continuous count task is suspended.
+ *
+ * In the first section the controller task first takes a copy of the shared
+ * count variable.  To ensure mutual exclusion on the count variable it
+ * suspends the continuous count task, resuming it again when the copy has been
+ * taken.  The controller task then sleeps for a fixed period - during which
+ * the continuous count task will execute and increment the shared variable.
+ * When the controller task wakes it checks that the continuous count task
+ * has executed by comparing the copy of the shared variable with its current
+ * value.  This time, to ensure mutual exclusion, the scheduler itself is
+ * suspended with a call to vTaskSuspendAll ().  This is for demonstration
+ * purposes only and is not a recommended technique due to its inefficiency.
+ *
+ * After a fixed number of iterations the controller task suspends the
+ * continuous count task, and moves on to its second section.
+ *
+ * At the start of the second section the shared variable is cleared to zero.
+ * The limited count task is then woken from its suspension by a call to
+ * vTaskResume ().  As this counter task operates at a higher priority than
+ * the controller task the controller task should not run again until the
+ * shared variable has been counted up to the limited value causing the counter
+ * task to suspend itself.  The next line after vTaskResume () is therefore
+ * a check on the shared variable to ensure everything is as expected.
+ *
+ *
+ * The second test consists of a couple of very simple tasks that post onto a
+ * queue while the scheduler is suspended.  This test was added to test parts
+ * of the scheduler not exercised by the first test.
+ *
+ */
+
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+
+/* Demo app include files. */
+#include "dynamic.h"
+
+/* Function that implements the "limited count" task as described above. */
+static portTASK_FUNCTION_PROTO( vLimitedIncrementTask, pvParameters );
+
+/* Function that implements the "continuous count" task as described above. */
+static portTASK_FUNCTION_PROTO( vContinuousIncrementTask, pvParameters );
+
+/* Function that implements the controller task as described above. */
+static portTASK_FUNCTION_PROTO( vCounterControlTask, pvParameters );
+
+static portTASK_FUNCTION_PROTO( vQueueReceiveWhenSuspendedTask, pvParameters );
+static portTASK_FUNCTION_PROTO( vQueueSendWhenSuspendedTask, pvParameters );
+
+/* Demo task specific constants. */
+#ifndef priSUSPENDED_RX_TASK_STACK_SIZE
+	#define priSUSPENDED_RX_TASK_STACK_SIZE			( configMINIMAL_STACK_SIZE )
+#endif
+#define priSTACK_SIZE				( configMINIMAL_STACK_SIZE )
+#define priSLEEP_TIME				pdMS_TO_TICKS( 128 )
+#define priLOOPS					( 5 )
+#define priMAX_COUNT				( ( uint32_t ) 0xff )
+#define priNO_BLOCK					( ( TickType_t ) 0 )
+#define priSUSPENDED_QUEUE_LENGTH	( 1 )
+
+/*-----------------------------------------------------------*/
+
+/* Handles to the two counter tasks.  These could be passed in as parameters
+to the controller task to prevent them having to be file scope. */
+static TaskHandle_t xContinuousIncrementHandle, xLimitedIncrementHandle;
+
+/* The shared counter variable.  This is passed in as a parameter to the two
+counter variables for demonstration purposes. */
+static uint32_t ulCounter;
+
+/* Variables used to check that the tasks are still operating without error.
+Each complete iteration of the controller task increments this variable
+provided no errors have been found.  The variable maintaining the same value
+is therefore indication of an error. */
+static volatile uint16_t usCheckVariable = ( uint16_t ) 0;
+static volatile BaseType_t xSuspendedQueueSendError = pdFALSE;
+static volatile BaseType_t xSuspendedQueueReceiveError = pdFALSE;
+
+/* Queue used by the second test. */
+QueueHandle_t xSuspendedTestQueue;
+
+/* The value the queue receive task expects to receive next.  This is file
+scope so xAreDynamicPriorityTasksStillRunning() can ensure it is still
+incrementing. */
+static uint32_t ulExpectedValue = ( uint32_t ) 0;
+
+/*-----------------------------------------------------------*/
+/*
+ * Start the three tasks as described at the top of the file.
+ * Note that the limited count task is given a higher priority.
+ */
+void vStartDynamicPriorityTasks( void )
+{
+	xSuspendedTestQueue = xQueueCreate( priSUSPENDED_QUEUE_LENGTH, sizeof( uint32_t ) );
+
+	if( xSuspendedTestQueue != NULL )
+	{
+		/* vQueueAddToRegistry() adds the queue to the queue registry, if one is
+		in use.  The queue registry is provided as a means for kernel aware
+		debuggers to locate queues and has no purpose if a kernel aware debugger
+		is not being used.  The call to vQueueAddToRegistry() will be removed
+		by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is
+		defined to be less than 1. */
+		vQueueAddToRegistry( xSuspendedTestQueue, "Suspended_Test_Queue" );
+
+		xTaskCreate( vContinuousIncrementTask, "CNT_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY, &xContinuousIncrementHandle );
+		xTaskCreate( vLimitedIncrementTask, "LIM_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY + 1, &xLimitedIncrementHandle );
+		xTaskCreate( vCounterControlTask, "C_CTRL", priSUSPENDED_RX_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+		xTaskCreate( vQueueSendWhenSuspendedTask, "SUSP_TX", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+		xTaskCreate( vQueueReceiveWhenSuspendedTask, "SUSP_RX", priSUSPENDED_RX_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+	}
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Just loops around incrementing the shared variable until the limit has been
+ * reached.  Once the limit has been reached it suspends itself.
+ */
+static portTASK_FUNCTION( vLimitedIncrementTask, pvParameters )
+{
+volatile uint32_t *pulCounter;
+
+	/* Take a pointer to the shared variable from the parameters passed into
+	the task. */
+	pulCounter = ( volatile uint32_t * ) pvParameters;
+
+	/* This will run before the control task, so the first thing it does is
+	suspend - the control task will resume it when ready. */
+	vTaskSuspend( NULL );
+
+	for( ;; )
+	{
+		/* Just count up to a value then suspend. */
+		( *pulCounter )++;
+
+		if( *pulCounter >= priMAX_COUNT )
+		{
+			vTaskSuspend( NULL );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Just keep counting the shared variable up.  The control task will suspend
+ * this task when it wants.
+ */
+static portTASK_FUNCTION( vContinuousIncrementTask, pvParameters )
+{
+volatile uint32_t *pulCounter;
+UBaseType_t uxOurPriority;
+
+	/* Take a pointer to the shared variable from the parameters passed into
+	the task. */
+	pulCounter = ( volatile uint32_t * ) pvParameters;
+
+	/* Query our priority so we can raise it when exclusive access to the
+	shared variable is required. */
+	uxOurPriority = uxTaskPriorityGet( NULL );
+
+	for( ;; )
+	{
+		/* Raise the priority above the controller task to ensure a context
+		switch does not occur while the variable is being accessed. */
+		vTaskPrioritySet( NULL, uxOurPriority + 1 );
+		{
+			configASSERT( ( uxTaskPriorityGet( NULL ) == ( uxOurPriority + 1 ) ) );
+			( *pulCounter )++;
+		}
+		vTaskPrioritySet( NULL, uxOurPriority );
+
+		#if( configUSE_PREEMPTION == 0 )
+			taskYIELD();
+		#endif
+
+		configASSERT( ( uxTaskPriorityGet( NULL ) == uxOurPriority ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Controller task as described above.
+ */
+static portTASK_FUNCTION( vCounterControlTask, pvParameters )
+{
+uint32_t ulLastCounter;
+short sLoops;
+short sError = pdFALSE;
+
+	/* Just to stop warning messages. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		/* Start with the counter at zero. */
+		ulCounter = ( uint32_t ) 0;
+
+		/* First section : */
+
+		/* Check the continuous count task is running. */
+		for( sLoops = 0; sLoops < priLOOPS; sLoops++ )
+		{
+			/* Suspend the continuous count task so we can take a mirror of the
+			shared variable without risk of corruption.  This is not really
+			needed as the other task raises its priority above this task's
+			priority. */
+			vTaskSuspend( xContinuousIncrementHandle );
+			{
+				#if( INCLUDE_eTaskGetState == 1 )
+				{
+					configASSERT( eTaskGetState( xContinuousIncrementHandle ) == eSuspended );
+				}
+				#endif /* INCLUDE_eTaskGetState */
+
+				ulLastCounter = ulCounter;
+			}
+			vTaskResume( xContinuousIncrementHandle );
+
+			#if( configUSE_PREEMPTION == 0 )
+				taskYIELD();
+			#endif
+
+			#if( INCLUDE_eTaskGetState == 1 )
+			{
+				configASSERT( eTaskGetState( xContinuousIncrementHandle ) == eReady );
+			}
+			#endif /* INCLUDE_eTaskGetState */
+
+			/* Now delay to ensure the other task has processor time. */
+			vTaskDelay( priSLEEP_TIME );
+
+			/* Check the shared variable again.  This time to ensure mutual
+			exclusion the whole scheduler will be locked.  This is just for
+			demo purposes! */
+			vTaskSuspendAll();
+			{
+				if( ulLastCounter == ulCounter )
+				{
+					/* The shared variable has not changed.  There is a problem
+					with the continuous count task so flag an error. */
+					sError = pdTRUE;
+				}
+			}
+			xTaskResumeAll();
+		}
+
+		/* Second section: */
+
+		/* Suspend the continuous counter task so it stops accessing the shared
+		variable. */
+		vTaskSuspend( xContinuousIncrementHandle );
+
+		/* Reset the variable. */
+		ulCounter = ( uint32_t ) 0;
+
+		#if( INCLUDE_eTaskGetState == 1 )
+		{
+			configASSERT( eTaskGetState( xLimitedIncrementHandle ) == eSuspended );
+		}
+		#endif /* INCLUDE_eTaskGetState */
+
+		/* Resume the limited count task which has a higher priority than us.
+		We should therefore not return from this call until the limited count
+		task has suspended itself with a known value in the counter variable. */
+		vTaskResume( xLimitedIncrementHandle );
+
+		#if( configUSE_PREEMPTION == 0 )
+			taskYIELD();
+		#endif
+
+		/* This task should not run again until xLimitedIncrementHandle has
+		suspended itself. */
+		#if( INCLUDE_eTaskGetState == 1 )
+		{
+			configASSERT( eTaskGetState( xLimitedIncrementHandle ) == eSuspended );
+		}
+		#endif /* INCLUDE_eTaskGetState */
+
+		/* Does the counter variable have the expected value? */
+		if( ulCounter != priMAX_COUNT )
+		{
+			sError = pdTRUE;
+		}
+
+		if( sError == pdFALSE )
+		{
+			/* If no errors have occurred then increment the check variable. */
+			portENTER_CRITICAL();
+				usCheckVariable++;
+			portEXIT_CRITICAL();
+		}
+
+		/* Resume the continuous count task and do it all again. */
+		vTaskResume( xContinuousIncrementHandle );
+
+		#if( configUSE_PREEMPTION == 0 )
+			taskYIELD();
+		#endif
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vQueueSendWhenSuspendedTask, pvParameters )
+{
+static uint32_t ulValueToSend = ( uint32_t ) 0;
+
+	/* Just to stop warning messages. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		vTaskSuspendAll();
+		{
+			/* We must not block while the scheduler is suspended! */
+			if( xQueueSend( xSuspendedTestQueue, ( void * ) &ulValueToSend, priNO_BLOCK ) != pdTRUE )
+			{
+				xSuspendedQueueSendError = pdTRUE;
+			}
+		}
+		xTaskResumeAll();
+
+		vTaskDelay( priSLEEP_TIME );
+
+		++ulValueToSend;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vQueueReceiveWhenSuspendedTask, pvParameters )
+{
+uint32_t ulReceivedValue;
+BaseType_t xGotValue;
+
+	/* Just to stop warning messages. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		do
+		{
+			/* Suspending the scheduler here is fairly pointless and
+			undesirable for a normal application.  It is done here purely
+			to test the scheduler.  The inner xTaskResumeAll() should
+			never return pdTRUE as the scheduler is still locked by the
+			outer call. */
+			vTaskSuspendAll();
+			{
+				vTaskSuspendAll();
+				{
+					xGotValue = xQueueReceive( xSuspendedTestQueue, ( void * ) &ulReceivedValue, priNO_BLOCK );
+				}
+				if( xTaskResumeAll() != pdFALSE )
+				{
+					xSuspendedQueueReceiveError = pdTRUE;
+				}
+			}
+			xTaskResumeAll();
+
+			#if configUSE_PREEMPTION == 0
+			{
+				taskYIELD();
+			}
+			#endif
+
+		} while( xGotValue == pdFALSE );
+
+		if( ulReceivedValue != ulExpectedValue )
+		{
+			xSuspendedQueueReceiveError = pdTRUE;
+		}
+
+		if( xSuspendedQueueReceiveError != pdTRUE )
+		{
+			/* Only increment the variable if an error has not occurred.  This
+			allows xAreDynamicPriorityTasksStillRunning() to check for stalled
+			tasks as well as explicit errors. */
+			++ulExpectedValue;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* Called to check that all the created tasks are still running without error. */
+BaseType_t xAreDynamicPriorityTasksStillRunning( void )
+{
+/* Keep a history of the check variables so we know if it has been incremented
+since the last call. */
+static uint16_t usLastTaskCheck = ( uint16_t ) 0;
+static uint32_t ulLastExpectedValue = ( uint32_t ) 0U;
+BaseType_t xReturn = pdTRUE;
+
+	/* Check the tasks are still running by ensuring the check variable
+	is still incrementing. */
+
+	if( usCheckVariable == usLastTaskCheck )
+	{
+		/* The check has not incremented so an error exists. */
+		xReturn = pdFALSE;
+	}
+
+	if( ulExpectedValue == ulLastExpectedValue )
+	{
+		/* The value being received by the queue receive task has not
+		incremented so an error exists. */
+		xReturn = pdFALSE;
+	}
+
+	if( xSuspendedQueueSendError == pdTRUE )
+	{
+		xReturn = pdFALSE;
+	}
+
+	if( xSuspendedQueueReceiveError == pdTRUE )
+	{
+		xReturn = pdFALSE;
+	}
+
+	usLastTaskCheck = usCheckVariable;
+	ulLastExpectedValue = ulExpectedValue;
+
+	return xReturn;
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/flash.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/flash.c
new file mode 100644
index 0000000..58a70a4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/flash.c
@@ -0,0 +1,119 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/**
+ * This version of flash .c is for use on systems that have limited stack space
+ * and no display facilities.  The complete version can be found in the
+ * Demo/Common/Full directory.
+ *
+ * Three tasks are created, each of which flash an LED at a different rate.  The first
+ * LED flashes every 200ms, the second every 400ms, the third every 600ms.
+ *
+ * The LED flash tasks provide instant visual feedback.  They show that the scheduler
+ * is still operational.
+ *
+ */
+
+
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo program include files. */
+#include "partest.h"
+#include "flash.h"
+
+#define ledSTACK_SIZE		configMINIMAL_STACK_SIZE
+#define ledNUMBER_OF_LEDS	( 3 )
+#define ledFLASH_RATE_BASE	( ( TickType_t ) 333 )
+
+/* Variable used by the created tasks to calculate the LED number to use, and
+the rate at which they should flash the LED. */
+static volatile UBaseType_t uxFlashTaskNumber = 0;
+
+/* The task that is created three times. */
+static portTASK_FUNCTION_PROTO( vLEDFlashTask, pvParameters );
+
+/*-----------------------------------------------------------*/
+
+void vStartLEDFlashTasks( UBaseType_t uxPriority )
+{
+BaseType_t xLEDTask;
+
+	/* Create the three tasks. */
+	for( xLEDTask = 0; xLEDTask < ledNUMBER_OF_LEDS; ++xLEDTask )
+	{
+		/* Spawn the task. */
+		xTaskCreate( vLEDFlashTask, "LEDx", ledSTACK_SIZE, NULL, uxPriority, ( TaskHandle_t * ) NULL );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vLEDFlashTask, pvParameters )
+{
+TickType_t xFlashRate, xLastFlashTime;
+UBaseType_t uxLED;
+
+	/* The parameters are not used. */
+	( void ) pvParameters;
+
+	/* Calculate the LED and flash rate. */
+	portENTER_CRITICAL();
+	{
+		/* See which of the eight LED's we should use. */
+		uxLED = uxFlashTaskNumber;
+
+		/* Update so the next task uses the next LED. */
+		uxFlashTaskNumber++;
+	}
+	portEXIT_CRITICAL();
+
+	xFlashRate = ledFLASH_RATE_BASE + ( ledFLASH_RATE_BASE * ( TickType_t ) uxLED );
+	xFlashRate /= portTICK_PERIOD_MS;
+
+	/* We will turn the LED on and off again in the delay period, so each
+	delay is only half the total period. */
+	xFlashRate /= ( TickType_t ) 2;
+
+	/* We need to initialise xLastFlashTime prior to the first call to
+	vTaskDelayUntil(). */
+	xLastFlashTime = xTaskGetTickCount();
+
+	for(;;)
+	{
+		/* Delay for half the flash period then turn the LED on. */
+		vTaskDelayUntil( &xLastFlashTime, xFlashRate );
+		vParTestToggleLED( uxLED );
+
+		/* Delay for half the flash period then turn the LED off. */
+		vTaskDelayUntil( &xLastFlashTime, xFlashRate );
+		vParTestToggleLED( uxLED );
+	}
+} /*lint !e715 !e818 !e830 Function definition must be standard for task creation. */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/flash_timer.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/flash_timer.c
new file mode 100644
index 0000000..5a244ba
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/flash_timer.c
@@ -0,0 +1,98 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/**
+ * Repeatedly toggles one or more LEDs using software timers - one timer per
+ * LED.
+ */
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "timers.h"
+
+/* Demo program include files. */
+#include "partest.h"
+#include "flash_timer.h"
+
+/* The toggle rates are all a multple of ledFLASH_RATE_BASE. */
+#define ledFLASH_RATE_BASE	( ( ( TickType_t ) 333 ) / portTICK_PERIOD_MS )
+
+/* A block time of zero simple means "don't block". */
+#define ledDONT_BLOCK		( ( TickType_t ) 0 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The callback function used by each LED flashing timer.  All the timers use
+ * this function, and the timer ID is used within the function to determine
+ * which timer has actually expired.
+ */
+static void prvLEDTimerCallback( TimerHandle_t xTimer );
+
+/*-----------------------------------------------------------*/
+
+void vStartLEDFlashTimers( UBaseType_t uxNumberOfLEDs )
+{
+UBaseType_t uxLEDTimer;
+TimerHandle_t xTimer;
+
+	/* Create and start the requested number of timers. */
+	for( uxLEDTimer = 0; uxLEDTimer < uxNumberOfLEDs; ++uxLEDTimer )
+	{
+		/* Create the timer. */
+		xTimer = xTimerCreate( 	"Flasher",								/* A text name, purely to help debugging. */
+								ledFLASH_RATE_BASE * ( uxLEDTimer + 1 ),/* The timer period, which is a multiple of ledFLASH_RATE_BASE. */
+								pdTRUE,									/* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
+								( void * ) uxLEDTimer,					/* The ID is used to identify the timer within the timer callback function, as each timer uses the same callback. */
+								prvLEDTimerCallback						/* Each timer uses the same callback. */
+							  );
+
+		/* If the timer was created successfully, attempt to start it.  If the
+		scheduler has not yet been started then the timer command queue must
+		be long enough to hold each command sent to it until such time that the
+		scheduler is started.  The timer command queue length is set by
+		configTIMER_QUEUE_LENGTH in FreeRTOSConfig.h. */
+		if( xTimer != NULL )
+		{
+			xTimerStart( xTimer, ledDONT_BLOCK );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvLEDTimerCallback( TimerHandle_t xTimer )
+{
+BaseType_t xTimerID;
+
+	/* The timer ID is used to identify the timer that has actually expired as
+	each timer uses the same callback.  The ID is then also used as the number
+	of the LED that is to be toggled. */
+	xTimerID = ( BaseType_t ) pvTimerGetTimerID( xTimer );
+	vParTestToggleLED( xTimerID );
+}
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/flop.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/flop.c
new file mode 100644
index 0000000..186b97f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/flop.c
@@ -0,0 +1,349 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Creates eight tasks, each of which loops continuously performing a floating
+ * point calculation.
+ *
+ * All the tasks run at the idle priority and never block or yield.  This causes
+ * all eight tasks to time slice with the idle task.  Running at the idle
+ * priority means that these tasks will get pre-empted any time another task is
+ * ready to run or a time slice occurs.  More often than not the pre-emption
+ * will occur mid calculation, creating a good test of the schedulers context
+ * switch mechanism - a calculation producing an unexpected result could be a
+ * symptom of a corruption in the context of a task.
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo program include files. */
+#include "flop.h"
+
+#ifndef mathSTACK_SIZE
+	#define mathSTACK_SIZE		configMINIMAL_STACK_SIZE
+#endif
+
+#define mathNUMBER_OF_TASKS  ( 4 )
+
+/* Four tasks, each of which performs a different floating point calculation.
+Each of the four is created twice. */
+static portTASK_FUNCTION_PROTO( vCompetingMathTask1, pvParameters );
+static portTASK_FUNCTION_PROTO( vCompetingMathTask2, pvParameters );
+static portTASK_FUNCTION_PROTO( vCompetingMathTask3, pvParameters );
+static portTASK_FUNCTION_PROTO( vCompetingMathTask4, pvParameters );
+
+/* These variables are used to check that all the tasks are still running.  If a
+task gets a calculation wrong it will stop setting its check variable. */
+static uint16_t usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( uint16_t ) 0 };
+
+/*-----------------------------------------------------------*/
+
+void vStartMathTasks( UBaseType_t uxPriority )
+{
+	xTaskCreate( vCompetingMathTask1, "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL );
+	xTaskCreate( vCompetingMathTask2, "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL );
+	xTaskCreate( vCompetingMathTask3, "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL );
+	xTaskCreate( vCompetingMathTask4, "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL );
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vCompetingMathTask1, pvParameters )
+{
+volatile portDOUBLE d1, d2, d3, d4;
+volatile uint16_t *pusTaskCheckVariable;
+volatile portDOUBLE dAnswer;
+short sError = pdFALSE;
+
+	/* Some ports require that tasks that use a hardware floating point unit
+	tell the kernel that they require a floating point context before any
+	floating point instructions are executed. */
+	portTASK_USES_FLOATING_POINT();
+
+	d1 = 123.4567;
+	d2 = 2345.6789;
+	d3 = -918.222;
+
+	dAnswer = ( d1 + d2 ) * d3;
+
+	/* The variable this task increments to show it is still running is passed in
+	as the parameter. */
+	pusTaskCheckVariable = ( volatile uint16_t * ) pvParameters;
+
+	/* Keep performing a calculation and checking the result against a constant. */
+	for(;;)
+	{
+		d1 = 123.4567;
+		d2 = 2345.6789;
+		d3 = -918.222;
+
+		d4 = ( d1 + d2 ) * d3;
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+		/* If the calculation does not match the expected constant, stop the
+		increment of the check variable. */
+		if( fabs( d4 - dAnswer ) > 0.001 )
+		{
+			sError = pdTRUE;
+		}
+
+		if( sError == pdFALSE )
+		{
+			/* If the calculation has always been correct then set set the check
+			variable.  The check variable will get set to pdFALSE each time
+			xAreMathsTaskStillRunning() is executed. */
+			( *pusTaskCheckVariable ) = pdTRUE;
+		}
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vCompetingMathTask2, pvParameters )
+{
+volatile portDOUBLE d1, d2, d3, d4;
+volatile uint16_t *pusTaskCheckVariable;
+volatile portDOUBLE dAnswer;
+short sError = pdFALSE;
+
+	/* Some ports require that tasks that use a hardware floating point unit
+	tell the kernel that they require a floating point context before any
+	floating point instructions are executed. */
+	portTASK_USES_FLOATING_POINT();
+
+	d1 = -389.38;
+	d2 = 32498.2;
+	d3 = -2.0001;
+
+	dAnswer = ( d1 / d2 ) * d3;
+
+
+	/* The variable this task increments to show it is still running is passed in
+	as the parameter. */
+	pusTaskCheckVariable = ( volatile uint16_t * ) pvParameters;
+
+	/* Keep performing a calculation and checking the result against a constant. */
+	for( ;; )
+	{
+		d1 = -389.38;
+		d2 = 32498.2;
+		d3 = -2.0001;
+
+		d4 = ( d1 / d2 ) * d3;
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+		/* If the calculation does not match the expected constant, stop the
+		increment of the check variable. */
+		if( fabs( d4 - dAnswer ) > 0.001 )
+		{
+			sError = pdTRUE;
+		}
+
+		if( sError == pdFALSE )
+		{
+			/* If the calculation has always been correct then set set the check
+			variable.  The check variable will get set to pdFALSE each time
+			xAreMathsTaskStillRunning() is executed. */
+			( *pusTaskCheckVariable ) = pdTRUE;
+		}
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vCompetingMathTask3, pvParameters )
+{
+volatile portDOUBLE *pdArray, dTotal1, dTotal2, dDifference;
+volatile uint16_t *pusTaskCheckVariable;
+const size_t xArraySize = 10;
+size_t xPosition;
+short sError = pdFALSE;
+
+	/* Some ports require that tasks that use a hardware floating point unit
+	tell the kernel that they require a floating point context before any
+	floating point instructions are executed. */
+	portTASK_USES_FLOATING_POINT();
+
+	/* The variable this task increments to show it is still running is passed in
+	as the parameter. */
+	pusTaskCheckVariable = ( volatile uint16_t * ) pvParameters;
+
+	pdArray = ( portDOUBLE * ) pvPortMalloc( xArraySize * sizeof( portDOUBLE ) );
+
+	/* Keep filling an array, keeping a running total of the values placed in the
+	array.  Then run through the array adding up all the values.  If the two totals
+	do not match, stop the check variable from incrementing. */
+	for( ;; )
+	{
+		dTotal1 = 0.0;
+		dTotal2 = 0.0;
+
+		for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+		{
+			pdArray[ xPosition ] = ( portDOUBLE ) xPosition + 5.5;
+			dTotal1 += ( portDOUBLE ) xPosition + 5.5;
+		}
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+		for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+		{
+			dTotal2 += pdArray[ xPosition ];
+		}
+
+		dDifference = dTotal1 - dTotal2;
+		if( fabs( dDifference ) > 0.001 )
+		{
+			sError = pdTRUE;
+		}
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+		if( sError == pdFALSE )
+		{
+			/* If the calculation has always been correct then set set the check
+			variable.  The check variable will get set to pdFALSE each time
+			xAreMathsTaskStillRunning() is executed. */
+			( *pusTaskCheckVariable ) = pdTRUE;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vCompetingMathTask4, pvParameters )
+{
+volatile portDOUBLE *pdArray, dTotal1, dTotal2, dDifference;
+volatile uint16_t *pusTaskCheckVariable;
+const size_t xArraySize = 10;
+size_t xPosition;
+short sError = pdFALSE;
+
+	/* Some ports require that tasks that use a hardware floating point unit
+	tell the kernel that they require a floating point context before any
+	floating point instructions are executed. */
+	portTASK_USES_FLOATING_POINT();
+
+	/* The variable this task increments to show it is still running is passed in
+	as the parameter. */
+	pusTaskCheckVariable = ( volatile uint16_t * ) pvParameters;
+
+	pdArray = ( portDOUBLE * ) pvPortMalloc( xArraySize * sizeof( portDOUBLE ) );
+
+	/* Keep filling an array, keeping a running total of the values placed in the
+	array.  Then run through the array adding up all the values.  If the two totals
+	do not match, stop the check variable from incrementing. */
+	for( ;; )
+	{
+		dTotal1 = 0.0;
+		dTotal2 = 0.0;
+
+		for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+		{
+			pdArray[ xPosition ] = ( portDOUBLE ) xPosition * 12.123;
+			dTotal1 += ( portDOUBLE ) xPosition * 12.123;
+		}
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+		for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+		{
+			dTotal2 += pdArray[ xPosition ];
+		}
+
+		dDifference = dTotal1 - dTotal2;
+		if( fabs( dDifference ) > 0.001 )
+		{
+			sError = pdTRUE;
+		}
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+		if( sError == pdFALSE )
+		{
+			/* If the calculation has always been correct then set set the check
+			variable.  The check variable will get set to pdFALSE each time
+			xAreMathsTaskStillRunning() is executed. */
+			( *pusTaskCheckVariable ) = pdTRUE;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* This is called to check that all the created tasks are still running. */
+BaseType_t xAreMathsTaskStillRunning( void )
+{
+BaseType_t xReturn = pdPASS, xTask;
+
+	/* Check the maths tasks are still running by ensuring their check variables
+	have been set to pdPASS. */
+	for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ )
+	{
+		if( usTaskCheck[ xTask ] != pdTRUE )
+		{
+			/* The check has not been set so the associated task has either
+			stalled or detected an error. */
+			xReturn = pdFAIL;
+		}
+		else
+		{
+			/* Reset the variable so it can be checked again the next time this
+			function is executed. */
+			usTaskCheck[ xTask ] = pdFALSE;
+		}
+	}
+
+	return xReturn;
+}
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/integer.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/integer.c
new file mode 100644
index 0000000..25b6eab
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/integer.c
@@ -0,0 +1,163 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Creates one or more tasks that repeatedly perform a set of integer
+ * calculations.  The result of each run-time calculation is compared to the
+ * known expected result - with a mismatch being indicative of an error in the
+ * context switch mechanism.
+ */
+
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo program include files. */
+#include "integer.h"
+
+/* The constants used in the calculation. */
+#define intgCONST1				( ( long ) 123 )
+#define intgCONST2				( ( long ) 234567 )
+#define intgCONST3				( ( long ) -3 )
+#define intgCONST4				( ( long ) 7 )
+#define intgEXPECTED_ANSWER		( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 )
+
+#define intgSTACK_SIZE			configMINIMAL_STACK_SIZE
+
+/* As this is the minimal version, we will only create one task. */
+#define intgNUMBER_OF_TASKS		( 1 )
+
+/* The task function.  Repeatedly performs a 32 bit calculation, checking the
+result against the expected result.  If the result is incorrect then the
+context switch must have caused some corruption. */
+static portTASK_FUNCTION_PROTO( vCompeteingIntMathTask, pvParameters );
+
+/* Variables that are set to true within the calculation task to indicate
+that the task is still executing.  The check task sets the variable back to
+false, flagging an error if the variable is still false the next time it
+is called. */
+static BaseType_t xTaskCheck[ intgNUMBER_OF_TASKS ] = { ( BaseType_t ) pdFALSE };
+
+/*-----------------------------------------------------------*/
+
+void vStartIntegerMathTasks( UBaseType_t uxPriority )
+{
+short sTask;
+
+	for( sTask = 0; sTask < intgNUMBER_OF_TASKS; sTask++ )
+	{
+		xTaskCreate( vCompeteingIntMathTask, "IntMath", intgSTACK_SIZE, ( void * ) &( xTaskCheck[ sTask ] ), uxPriority, ( TaskHandle_t * ) NULL );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vCompeteingIntMathTask, pvParameters )
+{
+/* These variables are all effectively set to constants so they are volatile to
+ensure the compiler does not just get rid of them. */
+volatile long lValue;
+short sError = pdFALSE;
+volatile BaseType_t *pxTaskHasExecuted;
+
+	/* Set a pointer to the variable we are going to set to true each
+	iteration.  This is also a good test of the parameter passing mechanism
+	within each port. */
+	pxTaskHasExecuted = ( volatile BaseType_t * ) pvParameters;
+
+	/* Keep performing a calculation and checking the result against a constant. */
+	for( ;; )
+	{
+		/* Perform the calculation.  This will store partial value in
+		registers, resulting in a good test of the context switch mechanism. */
+		lValue = intgCONST1;
+		lValue += intgCONST2;
+
+		/* Yield in case cooperative scheduling is being used. */
+		#if configUSE_PREEMPTION == 0
+		{
+			taskYIELD();
+		}
+		#endif
+
+		/* Finish off the calculation. */
+		lValue *= intgCONST3;
+		lValue /= intgCONST4;
+
+		/* If the calculation is found to be incorrect we stop setting the
+		TaskHasExecuted variable so the check task can see an error has
+		occurred. */
+		if( lValue != intgEXPECTED_ANSWER ) /*lint !e774 volatile used to prevent this being optimised out. */
+		{
+			sError = pdTRUE;
+		}
+
+		if( sError == pdFALSE )
+		{
+			/* We have not encountered any errors, so set the flag that show
+			we are still executing.  This will be periodically cleared by
+			the check task. */
+			portENTER_CRITICAL();
+				*pxTaskHasExecuted = pdTRUE;
+			portEXIT_CRITICAL();
+		}
+
+		/* Yield in case cooperative scheduling is being used. */
+		#if configUSE_PREEMPTION == 0
+		{
+			taskYIELD();
+		}
+		#endif
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* This is called to check that all the created tasks are still running. */
+BaseType_t xAreIntegerMathsTaskStillRunning( void )
+{
+BaseType_t xReturn = pdTRUE;
+short sTask;
+
+	/* Check the maths tasks are still running by ensuring their check variables
+	are still being set to true. */
+	for( sTask = 0; sTask < intgNUMBER_OF_TASKS; sTask++ )
+	{
+		if( xTaskCheck[ sTask ] == pdFALSE )
+		{
+			/* The check has not incremented so an error exists. */
+			xReturn = pdFALSE;
+		}
+
+		/* Reset the check variable so we can tell if it has been set by
+		the next time around. */
+		xTaskCheck[ sTask ] = pdFALSE;
+	}
+
+	return xReturn;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/readme.txt b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/readme.txt
new file mode 100644
index 0000000..4125d2c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/readme.txt
@@ -0,0 +1,2 @@
+This directory contains the implementation of the "common demo tasks".  These
+are test tasks and demo tasks that are used by nearly all the demo applications.
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/recmutex.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/recmutex.c
new file mode 100644
index 0000000..a2d4ed2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/recmutex.c
@@ -0,0 +1,416 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+	The tasks defined on this page demonstrate the use of recursive mutexes.
+
+	For recursive mutex functionality the created mutex should be created using
+	xSemaphoreCreateRecursiveMutex(), then be manipulated
+	using the xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() API
+	functions.
+
+	This demo creates three tasks all of which access the same recursive mutex:
+
+	prvRecursiveMutexControllingTask() has the highest priority so executes
+	first and grabs the mutex.  It then performs some recursive accesses -
+	between each of which it sleeps for a short period to let the lower
+	priority tasks execute.  When it has completed its demo functionality
+	it gives the mutex back before suspending itself.
+
+	prvRecursiveMutexBlockingTask() attempts to access the mutex by performing
+	a blocking 'take'.  The blocking task has a lower priority than the
+	controlling	task so by the time it executes the mutex has already been
+	taken by the controlling task,  causing the blocking task to block.  It
+	does not unblock until the controlling task has given the mutex back,
+	and it does not actually run until the controlling task has suspended
+	itself (due to the relative priorities).  When it eventually does obtain
+	the mutex all it does is give the mutex back prior to also suspending
+	itself.  At this point both the controlling task and the blocking task are
+	suspended.
+
+	prvRecursiveMutexPollingTask() runs at the idle priority.  It spins round
+	a tight loop attempting to obtain the mutex with a non-blocking call.  As
+	the lowest priority task it will not successfully obtain the mutex until
+	both the controlling and blocking tasks are suspended.  Once it eventually
+	does obtain the mutex it first unsuspends both the controlling task and
+	blocking task prior to giving the mutex back - resulting in the polling
+	task temporarily inheriting the controlling tasks priority.
+*/
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+
+/* Demo app include files. */
+#include "recmutex.h"
+
+/* Priorities assigned to the three tasks.  recmuCONTROLLING_TASK_PRIORITY can
+be overridden by a definition in FreeRTOSConfig.h. */
+#ifndef recmuCONTROLLING_TASK_PRIORITY
+	#define recmuCONTROLLING_TASK_PRIORITY	( tskIDLE_PRIORITY + 2 )
+#endif
+#define recmuBLOCKING_TASK_PRIORITY		( tskIDLE_PRIORITY + 1 )
+#define recmuPOLLING_TASK_PRIORITY		( tskIDLE_PRIORITY + 0 )
+
+/* The recursive call depth. */
+#define recmuMAX_COUNT					( 10 )
+
+/* Misc. */
+#define recmuSHORT_DELAY				( pdMS_TO_TICKS( 20 ) )
+#define recmuNO_DELAY					( ( TickType_t ) 0 )
+#define recmu15ms_DELAY					( pdMS_TO_TICKS( 15 ) )
+
+#ifndef recmuRECURSIVE_MUTEX_TEST_TASK_STACK_SIZE
+	#define recmuRECURSIVE_MUTEX_TEST_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
+#endif
+
+/* The three tasks as described at the top of this file. */
+static void prvRecursiveMutexControllingTask( void *pvParameters );
+static void prvRecursiveMutexBlockingTask( void *pvParameters );
+static void prvRecursiveMutexPollingTask( void *pvParameters );
+
+/* The mutex used by the demo. */
+static SemaphoreHandle_t xMutex;
+
+/* Variables used to detect and latch errors. */
+static volatile BaseType_t xErrorOccurred = pdFALSE, xControllingIsSuspended = pdFALSE, xBlockingIsSuspended = pdFALSE;
+static volatile UBaseType_t uxControllingCycles = 0, uxBlockingCycles = 0, uxPollingCycles = 0;
+
+/* Handles of the two higher priority tasks, required so they can be resumed
+(unsuspended). */
+static TaskHandle_t xControllingTaskHandle, xBlockingTaskHandle;
+
+/*-----------------------------------------------------------*/
+
+void vStartRecursiveMutexTasks( void )
+{
+	/* Just creates the mutex and the three tasks. */
+
+	xMutex = xSemaphoreCreateRecursiveMutex();
+
+	if( xMutex != NULL )
+	{
+		/* vQueueAddToRegistry() adds the mutex to the registry, if one is
+		in use.  The registry is provided as a means for kernel aware
+		debuggers to locate mutex and has no purpose if a kernel aware debugger
+		is not being used.  The call to vQueueAddToRegistry() will be removed
+		by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is
+		defined to be less than 1. */
+		vQueueAddToRegistry( ( QueueHandle_t ) xMutex, "Recursive_Mutex" );
+
+		xTaskCreate( prvRecursiveMutexControllingTask, "Rec1", recmuRECURSIVE_MUTEX_TEST_TASK_STACK_SIZE, NULL, recmuCONTROLLING_TASK_PRIORITY, &xControllingTaskHandle );
+		xTaskCreate( prvRecursiveMutexBlockingTask, "Rec2", recmuRECURSIVE_MUTEX_TEST_TASK_STACK_SIZE, NULL, recmuBLOCKING_TASK_PRIORITY, &xBlockingTaskHandle );
+		xTaskCreate( prvRecursiveMutexPollingTask, "Rec3", recmuRECURSIVE_MUTEX_TEST_TASK_STACK_SIZE, NULL, recmuPOLLING_TASK_PRIORITY, NULL );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvRecursiveMutexControllingTask( void *pvParameters )
+{
+UBaseType_t ux;
+
+	/* Just to remove compiler warning. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		/* Should not be able to 'give' the mutex, as we have not yet 'taken'
+		it.   The first time through, the mutex will not have been used yet,
+		subsequent times through, at this point the mutex will be held by the
+		polling task. */
+		if( xSemaphoreGiveRecursive( xMutex ) == pdPASS )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+
+		for( ux = 0; ux < recmuMAX_COUNT; ux++ )
+		{
+			/* We should now be able to take the mutex as many times as
+			we like.
+
+			The first time through the mutex will be immediately available, on
+			subsequent times through the mutex will be held by the polling task
+			at this point and this Take will cause the polling task to inherit
+			the priority of this task.  In this case the block time must be
+			long enough to ensure the polling task will execute again before the
+			block time expires.  If the block time does expire then the error
+			flag will be set here. */
+			if( xSemaphoreTakeRecursive( xMutex, recmu15ms_DELAY ) != pdPASS )
+			{
+				xErrorOccurred = pdTRUE;
+			}
+
+			/* Ensure the other task attempting to access the mutex (and the
+			other demo tasks) are able to execute to ensure they either block
+			(where a block time is specified) or return an error (where no
+			block time is specified) as the mutex is held by this task. */
+			vTaskDelay( recmuSHORT_DELAY );
+		}
+
+		/* For each time we took the mutex, give it back. */
+		for( ux = 0; ux < recmuMAX_COUNT; ux++ )
+		{
+			/* Ensure the other task attempting to access the mutex (and the
+			other demo tasks) are able to execute. */
+			vTaskDelay( recmuSHORT_DELAY );
+
+			/* We should now be able to give the mutex as many times as we
+			took it.  When the mutex is available again the Blocking task
+			should be unblocked but not run because it has a lower priority
+			than this task.  The polling task should also not run at this point
+			as it too has a lower priority than this task. */
+			if( xSemaphoreGiveRecursive( xMutex ) != pdPASS )
+			{
+				xErrorOccurred = pdTRUE;
+			}
+
+			#if( configUSE_PREEMPTION == 0 )
+				taskYIELD();
+			#endif
+		}
+
+		/* Having given it back the same number of times as it was taken, we
+		should no longer be the mutex owner, so the next give should fail. */
+		if( xSemaphoreGiveRecursive( xMutex ) == pdPASS )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+
+		/* Keep count of the number of cycles this task has performed so a
+		stall can be detected. */
+		uxControllingCycles++;
+
+		/* Suspend ourselves so the blocking task can execute. */
+		xControllingIsSuspended = pdTRUE;
+		vTaskSuspend( NULL );
+		xControllingIsSuspended = pdFALSE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvRecursiveMutexBlockingTask( void *pvParameters )
+{
+	/* Just to remove compiler warning. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		/* This task will run while the controlling task is blocked, and the
+		controlling task will block only once it has the mutex - therefore
+		this call should block until the controlling task has given up the
+		mutex, and not actually execute	past this call until the controlling
+		task is suspended.  portMAX_DELAY - 1 is used instead of portMAX_DELAY
+		to ensure the task's state is reported as Blocked and not Suspended in
+		a later call to configASSERT() (within the polling task). */
+		if( xSemaphoreTakeRecursive( xMutex, ( portMAX_DELAY - 1 ) ) == pdPASS )
+		{
+			if( xControllingIsSuspended != pdTRUE )
+			{
+				/* Did not expect to execute until the controlling task was
+				suspended. */
+				xErrorOccurred = pdTRUE;
+			}
+			else
+			{
+				/* Give the mutex back before suspending ourselves to allow
+				the polling task to obtain the mutex. */
+				if( xSemaphoreGiveRecursive( xMutex ) != pdPASS )
+				{
+					xErrorOccurred = pdTRUE;
+				}
+
+				xBlockingIsSuspended = pdTRUE;
+				vTaskSuspend( NULL );
+				xBlockingIsSuspended = pdFALSE;
+			}
+		}
+		else
+		{
+			/* We should not leave the xSemaphoreTakeRecursive() function
+			until the mutex was obtained. */
+			xErrorOccurred = pdTRUE;
+		}
+
+		/* The controlling and blocking tasks should be in lock step. */
+		if( uxControllingCycles != ( uxBlockingCycles + 1 ) )
+		{
+			xErrorOccurred = pdTRUE;
+		}
+
+		/* Keep count of the number of cycles this task has performed so a
+		stall can be detected. */
+		uxBlockingCycles++;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvRecursiveMutexPollingTask( void *pvParameters )
+{
+	/* Just to remove compiler warning. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		/* Keep attempting to obtain the mutex.  It should only be obtained when
+		the blocking task has suspended itself, which in turn should only
+		happen when the controlling task is also suspended. */
+		if( xSemaphoreTakeRecursive( xMutex, recmuNO_DELAY ) == pdPASS )
+		{
+			#if( INCLUDE_eTaskGetState == 1 )
+			{
+				configASSERT( eTaskGetState( xControllingTaskHandle ) == eSuspended );
+				configASSERT( eTaskGetState( xBlockingTaskHandle ) == eSuspended );
+			}
+			#endif /* INCLUDE_eTaskGetState */
+
+			/* Is the blocking task suspended? */
+			if( ( xBlockingIsSuspended != pdTRUE ) || ( xControllingIsSuspended != pdTRUE ) )
+			{
+				xErrorOccurred = pdTRUE;
+			}
+			else
+			{
+				/* Keep count of the number of cycles this task has performed
+				so a stall can be detected. */
+				uxPollingCycles++;
+
+				/* We can resume the other tasks here even though they have a
+				higher priority than the polling task.  When they execute they
+				will attempt to obtain the mutex but fail because the polling
+				task is still the mutex holder.  The polling task (this task)
+				will then inherit the higher priority.  The Blocking task will
+				block indefinitely when it attempts to obtain the mutex, the
+				Controlling task will only block for a fixed period and an
+				error will be latched if the polling task has not returned the
+				mutex by the time this fixed period has expired. */
+				vTaskResume( xBlockingTaskHandle );
+				#if( configUSE_PREEMPTION == 0 )
+					taskYIELD();
+				#endif
+
+				vTaskResume( xControllingTaskHandle );
+				#if( configUSE_PREEMPTION == 0 )
+					taskYIELD();
+				#endif
+
+				/* The other two tasks should now have executed and no longer
+				be suspended. */
+				if( ( xBlockingIsSuspended == pdTRUE ) || ( xControllingIsSuspended == pdTRUE ) )
+				{
+					xErrorOccurred = pdTRUE;
+				}
+
+				#if( INCLUDE_uxTaskPriorityGet == 1 )
+				{
+					/* Check priority inherited. */
+					configASSERT( uxTaskPriorityGet( NULL ) == recmuCONTROLLING_TASK_PRIORITY );
+				}
+				#endif /* INCLUDE_uxTaskPriorityGet */
+
+				#if( INCLUDE_eTaskGetState == 1 )
+				{
+					configASSERT( eTaskGetState( xControllingTaskHandle ) == eBlocked );
+					configASSERT( eTaskGetState( xBlockingTaskHandle ) == eBlocked );
+				}
+				#endif /* INCLUDE_eTaskGetState */
+
+				/* Release the mutex, disinheriting the higher priority again. */
+				if( xSemaphoreGiveRecursive( xMutex ) != pdPASS )
+				{
+					xErrorOccurred = pdTRUE;
+				}
+
+				#if( INCLUDE_uxTaskPriorityGet == 1 )
+				{
+					/* Check priority disinherited. */
+					configASSERT( uxTaskPriorityGet( NULL ) == recmuPOLLING_TASK_PRIORITY );
+				}
+				#endif /* INCLUDE_uxTaskPriorityGet */
+			}
+		}
+
+		#if configUSE_PREEMPTION == 0
+		{
+			taskYIELD();
+		}
+		#endif
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* This is called to check that all the created tasks are still running. */
+BaseType_t xAreRecursiveMutexTasksStillRunning( void )
+{
+BaseType_t xReturn;
+static UBaseType_t uxLastControllingCycles = 0, uxLastBlockingCycles = 0, uxLastPollingCycles = 0;
+
+	/* Is the controlling task still cycling? */
+	if( uxLastControllingCycles == uxControllingCycles )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+	else
+	{
+		uxLastControllingCycles = uxControllingCycles;
+	}
+
+	/* Is the blocking task still cycling? */
+	if( uxLastBlockingCycles == uxBlockingCycles )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+	else
+	{
+		uxLastBlockingCycles = uxBlockingCycles;
+	}
+
+	/* Is the polling task still cycling? */
+	if( uxLastPollingCycles == uxPollingCycles )
+	{
+		xErrorOccurred = pdTRUE;
+	}
+	else
+	{
+		uxLastPollingCycles = uxPollingCycles;
+	}
+
+	if( xErrorOccurred == pdTRUE )
+	{
+		xReturn = pdFAIL;
+	}
+	else
+	{
+		xReturn = pdPASS;
+	}
+
+	return xReturn;
+}
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/semtest.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/semtest.c
new file mode 100644
index 0000000..84c53a7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/semtest.c
@@ -0,0 +1,269 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Creates two sets of two tasks.  The tasks within a set share a variable, access
+ * to which is guarded by a semaphore.
+ *
+ * Each task starts by attempting to obtain the semaphore.  On obtaining a
+ * semaphore a task checks to ensure that the guarded variable has an expected
+ * value.  It then clears the variable to zero before counting it back up to the
+ * expected value in increments of 1.  After each increment the variable is checked
+ * to ensure it contains the value to which it was just set. When the starting
+ * value is again reached the task releases the semaphore giving the other task in
+ * the set a chance to do exactly the same thing.  The starting value is high
+ * enough to ensure that a tick is likely to occur during the incrementing loop.
+ *
+ * An error is flagged if at any time during the process a shared variable is
+ * found to have a value other than that expected.  Such an occurrence would
+ * suggest an error in the mutual exclusion mechanism by which access to the
+ * variable is restricted.
+ *
+ * The first set of two tasks poll their semaphore.  The second set use blocking
+ * calls.
+ *
+ */
+
+
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+
+/* Demo app include files. */
+#include "semtest.h"
+
+/* The value to which the shared variables are counted. */
+#define semtstBLOCKING_EXPECTED_VALUE		( ( uint32_t ) 0xfff )
+#define semtstNON_BLOCKING_EXPECTED_VALUE	( ( uint32_t ) 0xff  )
+
+#define semtstSTACK_SIZE			configMINIMAL_STACK_SIZE
+
+#define semtstNUM_TASKS				( 4 )
+
+#define semtstDELAY_FACTOR			( ( TickType_t ) 10 )
+
+/* The task function as described at the top of the file. */
+static portTASK_FUNCTION_PROTO( prvSemaphoreTest, pvParameters );
+
+/* Structure used to pass parameters to each task. */
+typedef struct SEMAPHORE_PARAMETERS
+{
+	SemaphoreHandle_t xSemaphore;
+	volatile uint32_t *pulSharedVariable;
+	TickType_t xBlockTime;
+} xSemaphoreParameters;
+
+/* Variables used to check that all the tasks are still running without errors. */
+static volatile short sCheckVariables[ semtstNUM_TASKS ] = { 0 };
+static volatile short sNextCheckVariable = 0;
+
+/*-----------------------------------------------------------*/
+
+void vStartSemaphoreTasks( UBaseType_t uxPriority )
+{
+xSemaphoreParameters *pxFirstSemaphoreParameters, *pxSecondSemaphoreParameters;
+const TickType_t xBlockTime = ( TickType_t ) 100;
+
+	/* Create the structure used to pass parameters to the first two tasks. */
+	pxFirstSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) );
+
+	if( pxFirstSemaphoreParameters != NULL )
+	{
+		/* Create the semaphore used by the first two tasks. */
+		pxFirstSemaphoreParameters->xSemaphore = xSemaphoreCreateBinary();
+
+		if( pxFirstSemaphoreParameters->xSemaphore != NULL )
+		{
+			xSemaphoreGive( pxFirstSemaphoreParameters->xSemaphore );
+
+			/* Create the variable which is to be shared by the first two tasks. */
+			pxFirstSemaphoreParameters->pulSharedVariable = ( uint32_t * ) pvPortMalloc( sizeof( uint32_t ) );
+
+			/* Initialise the share variable to the value the tasks expect. */
+			*( pxFirstSemaphoreParameters->pulSharedVariable ) = semtstNON_BLOCKING_EXPECTED_VALUE;
+
+			/* The first two tasks do not block on semaphore calls. */
+			pxFirstSemaphoreParameters->xBlockTime = ( TickType_t ) 0;
+
+			/* Spawn the first two tasks.  As they poll they operate at the idle priority. */
+			xTaskCreate( prvSemaphoreTest, "PolSEM1", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( TaskHandle_t * ) NULL );
+			xTaskCreate( prvSemaphoreTest, "PolSEM2", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( TaskHandle_t * ) NULL );
+
+			/* vQueueAddToRegistry() adds the semaphore to the registry, if one
+			is in use.  The registry is provided as a means for kernel aware
+			debuggers to locate semaphores and has no purpose if a kernel aware
+			debugger is not being used.  The call to vQueueAddToRegistry() will
+			be removed by the pre-processor if configQUEUE_REGISTRY_SIZE is not
+			defined or is defined to be less than 1. */
+			vQueueAddToRegistry( ( QueueHandle_t ) pxFirstSemaphoreParameters->xSemaphore, "Counting_Sem_1" );
+		}
+	}
+
+	/* Do exactly the same to create the second set of tasks, only this time
+	provide a block time for the semaphore calls. */
+	pxSecondSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) );
+	if( pxSecondSemaphoreParameters != NULL )
+	{
+		pxSecondSemaphoreParameters->xSemaphore = xSemaphoreCreateBinary();
+
+		if( pxSecondSemaphoreParameters->xSemaphore != NULL )
+		{
+			xSemaphoreGive( pxSecondSemaphoreParameters->xSemaphore );
+
+			pxSecondSemaphoreParameters->pulSharedVariable = ( uint32_t * ) pvPortMalloc( sizeof( uint32_t ) );
+			*( pxSecondSemaphoreParameters->pulSharedVariable ) = semtstBLOCKING_EXPECTED_VALUE;
+			pxSecondSemaphoreParameters->xBlockTime = xBlockTime / portTICK_PERIOD_MS;
+
+			xTaskCreate( prvSemaphoreTest, "BlkSEM1", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( TaskHandle_t * ) NULL );
+			xTaskCreate( prvSemaphoreTest, "BlkSEM2", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( TaskHandle_t * ) NULL );
+
+			/* vQueueAddToRegistry() adds the semaphore to the registry, if one
+			is in use.  The registry is provided as a means for kernel aware
+			debuggers to locate semaphores and has no purpose if a kernel aware
+			debugger is not being used.  The call to vQueueAddToRegistry() will
+			be removed by the pre-processor if configQUEUE_REGISTRY_SIZE is not
+			defined or is defined to be less than 1. */
+			vQueueAddToRegistry( ( QueueHandle_t ) pxSecondSemaphoreParameters->xSemaphore, "Counting_Sem_2" );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( prvSemaphoreTest, pvParameters )
+{
+xSemaphoreParameters *pxParameters;
+volatile uint32_t *pulSharedVariable, ulExpectedValue;
+uint32_t ulCounter;
+short sError = pdFALSE, sCheckVariableToUse;
+
+	/* See which check variable to use.  sNextCheckVariable is not semaphore
+	protected! */
+	portENTER_CRITICAL();
+		sCheckVariableToUse = sNextCheckVariable;
+		sNextCheckVariable++;
+	portEXIT_CRITICAL();
+
+	/* A structure is passed in as the parameter.  This contains the shared
+	variable being guarded. */
+	pxParameters = ( xSemaphoreParameters * ) pvParameters;
+	pulSharedVariable = pxParameters->pulSharedVariable;
+
+	/* If we are blocking we use a much higher count to ensure loads of context
+	switches occur during the count. */
+	if( pxParameters->xBlockTime > ( TickType_t ) 0 )
+	{
+		ulExpectedValue = semtstBLOCKING_EXPECTED_VALUE;
+	}
+	else
+	{
+		ulExpectedValue = semtstNON_BLOCKING_EXPECTED_VALUE;
+	}
+
+	for( ;; )
+	{
+		/* Try to obtain the semaphore. */
+		if( xSemaphoreTake( pxParameters->xSemaphore, pxParameters->xBlockTime ) == pdPASS )
+		{
+			/* We have the semaphore and so expect any other tasks using the
+			shared variable to have left it in the state we expect to find
+			it. */
+			if( *pulSharedVariable != ulExpectedValue )
+			{
+				sError = pdTRUE;
+			}
+
+			/* Clear the variable, then count it back up to the expected value
+			before releasing the semaphore.  Would expect a context switch or
+			two during this time. */
+			for( ulCounter = ( uint32_t ) 0; ulCounter <= ulExpectedValue; ulCounter++ )
+			{
+				*pulSharedVariable = ulCounter;
+				if( *pulSharedVariable != ulCounter )
+				{
+					sError = pdTRUE;
+				}
+			}
+
+			/* Release the semaphore, and if no errors have occurred increment the check
+			variable. */
+			if(	xSemaphoreGive( pxParameters->xSemaphore ) == pdFALSE )
+			{
+				sError = pdTRUE;
+			}
+
+			if( sError == pdFALSE )
+			{
+				if( sCheckVariableToUse < semtstNUM_TASKS )
+				{
+					( sCheckVariables[ sCheckVariableToUse ] )++;
+				}
+			}
+
+			/* If we have a block time then we are running at a priority higher
+			than the idle priority.  This task takes a long time to complete
+			a cycle	(deliberately so to test the guarding) so will be starving
+			out lower priority tasks.  Block for some time to allow give lower
+			priority tasks some processor time. */
+			vTaskDelay( pxParameters->xBlockTime * semtstDELAY_FACTOR );
+		}
+		else
+		{
+			if( pxParameters->xBlockTime == ( TickType_t ) 0 )
+			{
+				/* We have not got the semaphore yet, so no point using the
+				processor.  We are not blocking when attempting to obtain the
+				semaphore. */
+				taskYIELD();
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* This is called to check that all the created tasks are still running. */
+BaseType_t xAreSemaphoreTasksStillRunning( void )
+{
+static short sLastCheckVariables[ semtstNUM_TASKS ] = { 0 };
+BaseType_t xTask, xReturn = pdTRUE;
+
+	for( xTask = 0; xTask < semtstNUM_TASKS; xTask++ )
+	{
+		if( sLastCheckVariables[ xTask ] == sCheckVariables[ xTask ] )
+		{
+			xReturn = pdFALSE;
+		}
+
+		sLastCheckVariables[ xTask ] = sCheckVariables[ xTask ];
+	}
+
+	return xReturn;
+}
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/sp_flop.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/sp_flop.c
new file mode 100644
index 0000000..6feaed3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/Minimal/sp_flop.c
@@ -0,0 +1,327 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Creates eight tasks, each of which loops continuously performing a floating
+ * point calculation - using single precision variables.
+ *
+ * All the tasks run at the idle priority and never block or yield.  This causes
+ * all eight tasks to time slice with the idle task.  Running at the idle priority
+ * means that these tasks will get pre-empted any time another task is ready to run
+ * or a time slice occurs.  More often than not the pre-emption will occur mid
+ * calculation, creating a good test of the schedulers context switch mechanism - a
+ * calculation producing an unexpected result could be a symptom of a corruption in
+ * the context of a task.
+ */
+
+#include 
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo program include files. */
+#include "flop.h"
+
+#define mathSTACK_SIZE		configMINIMAL_STACK_SIZE
+#define mathNUMBER_OF_TASKS  ( 8 )
+
+/* Four tasks, each of which performs a different floating point calculation.
+Each of the four is created twice. */
+static portTASK_FUNCTION_PROTO( vCompetingMathTask1, pvParameters );
+static portTASK_FUNCTION_PROTO( vCompetingMathTask2, pvParameters );
+static portTASK_FUNCTION_PROTO( vCompetingMathTask3, pvParameters );
+static portTASK_FUNCTION_PROTO( vCompetingMathTask4, pvParameters );
+
+/* These variables are used to check that all the tasks are still running.  If a
+task gets a calculation wrong it will
+stop incrementing its check variable. */
+static volatile uint16_t usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( uint16_t ) 0 };
+
+/*-----------------------------------------------------------*/
+
+void vStartMathTasks( UBaseType_t uxPriority )
+{
+	xTaskCreate( vCompetingMathTask1, "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL );
+	xTaskCreate( vCompetingMathTask2, "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL );
+	xTaskCreate( vCompetingMathTask3, "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL );
+	xTaskCreate( vCompetingMathTask4, "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL );
+	xTaskCreate( vCompetingMathTask1, "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL );
+	xTaskCreate( vCompetingMathTask2, "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL );
+	xTaskCreate( vCompetingMathTask3, "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL );
+	xTaskCreate( vCompetingMathTask4, "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL );
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vCompetingMathTask1, pvParameters )
+{
+volatile float f1, f2, f3, f4;
+volatile uint16_t *pusTaskCheckVariable;
+volatile float fAnswer;
+short sError = pdFALSE;
+
+	f1 = 123.4567F;
+	f2 = 2345.6789F;
+	f3 = -918.222F;
+
+	fAnswer = ( f1 + f2 ) * f3;
+
+	/* The variable this task increments to show it is still running is passed in
+	as the parameter. */
+	pusTaskCheckVariable = ( uint16_t * ) pvParameters;
+
+	/* Keep performing a calculation and checking the result against a constant. */
+	for(;;)
+	{
+		f1 = 123.4567F;
+		f2 = 2345.6789F;
+		f3 = -918.222F;
+
+		f4 = ( f1 + f2 ) * f3;
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+		/* If the calculation does not match the expected constant, stop the
+		increment of the check variable. */
+		if( fabs( f4 - fAnswer ) > 0.001F )
+		{
+			sError = pdTRUE;
+		}
+
+		if( sError == pdFALSE )
+		{
+			/* If the calculation has always been correct, increment the check
+			variable so we know this task is still running okay. */
+			( *pusTaskCheckVariable )++;
+		}
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vCompetingMathTask2, pvParameters )
+{
+volatile float f1, f2, f3, f4;
+volatile uint16_t *pusTaskCheckVariable;
+volatile float fAnswer;
+short sError = pdFALSE;
+
+	f1 = -389.38F;
+	f2 = 32498.2F;
+	f3 = -2.0001F;
+
+	fAnswer = ( f1 / f2 ) * f3;
+
+
+	/* The variable this task increments to show it is still running is passed in
+	as the parameter. */
+	pusTaskCheckVariable = ( uint16_t * ) pvParameters;
+
+	/* Keep performing a calculation and checking the result against a constant. */
+	for( ;; )
+	{
+		f1 = -389.38F;
+		f2 = 32498.2F;
+		f3 = -2.0001F;
+
+		f4 = ( f1 / f2 ) * f3;
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+		/* If the calculation does not match the expected constant, stop the
+		increment of the check variable. */
+		if( fabs( f4 - fAnswer ) > 0.001F )
+		{
+			sError = pdTRUE;
+		}
+
+		if( sError == pdFALSE )
+		{
+			/* If the calculation has always been correct, increment the check
+			variable so we know
+			this task is still running okay. */
+			( *pusTaskCheckVariable )++;
+		}
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vCompetingMathTask3, pvParameters )
+{
+volatile float *pfArray, fTotal1, fTotal2, fDifference, fPosition;
+volatile uint16_t *pusTaskCheckVariable;
+const size_t xArraySize = 10;
+size_t xPosition;
+short sError = pdFALSE;
+
+	/* The variable this task increments to show it is still running is passed in
+	as the parameter. */
+	pusTaskCheckVariable = ( uint16_t * ) pvParameters;
+
+	pfArray = ( float * ) pvPortMalloc( xArraySize * sizeof( float ) );
+
+	/* Keep filling an array, keeping a running total of the values placed in the
+	array.  Then run through the array adding up all the values.  If the two totals
+	do not match, stop the check variable from incrementing. */
+	for( ;; )
+	{
+		fTotal1 = 0.0F;
+		fTotal2 = 0.0F;
+		fPosition = 0.0F;
+
+		for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+		{
+			pfArray[ xPosition ] = fPosition + 5.5F;
+			fTotal1 += fPosition + 5.5F;
+		}
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+		for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+		{
+			fTotal2 += pfArray[ xPosition ];
+		}
+
+		fDifference = fTotal1 - fTotal2;
+		if( fabs( fDifference ) > 0.001F )
+		{
+			sError = pdTRUE;
+		}
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+		if( sError == pdFALSE )
+		{
+			/* If the calculation has always been correct, increment the check
+			variable so we know	this task is still running okay. */
+			( *pusTaskCheckVariable )++;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vCompetingMathTask4, pvParameters )
+{
+volatile float *pfArray, fTotal1, fTotal2, fDifference, fPosition;
+volatile uint16_t *pusTaskCheckVariable;
+const size_t xArraySize = 10;
+size_t xPosition;
+short sError = pdFALSE;
+
+	/* The variable this task increments to show it is still running is passed in
+	as the parameter. */
+	pusTaskCheckVariable = ( uint16_t * ) pvParameters;
+
+	pfArray = ( float * ) pvPortMalloc( xArraySize * sizeof( float ) );
+
+	/* Keep filling an array, keeping a running total of the values placed in the
+	array.  Then run through the array adding up all the values.  If the two totals
+	do not match, stop the check variable from incrementing. */
+	for( ;; )
+	{
+		fTotal1 = 0.0F;
+		fTotal2 = 0.0F;
+		fPosition = 0.0F;
+
+		for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+		{
+			pfArray[ xPosition ] = fPosition * 12.123F;
+			fTotal1 += fPosition * 12.123F;
+		}
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+		for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+		{
+			fTotal2 += pfArray[ xPosition ];
+		}
+
+		fDifference = fTotal1 - fTotal2;
+		if( fabs( fDifference ) > 0.001F )
+		{
+			sError = pdTRUE;
+		}
+
+		#if configUSE_PREEMPTION == 0
+			taskYIELD();
+		#endif
+
+		if( sError == pdFALSE )
+		{
+			/* If the calculation has always been correct, increment the check
+			variable so we know	this task is still running okay. */
+			( *pusTaskCheckVariable )++;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* This is called to check that all the created tasks are still running. */
+BaseType_t xAreMathsTaskStillRunning( void )
+{
+/* Keep a history of the check variables so we know if they have been incremented
+since the last call. */
+static uint16_t usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( uint16_t ) 0 };
+BaseType_t xReturn = pdTRUE, xTask;
+
+	/* Check the maths tasks are still running by ensuring their check variables
+	are still incrementing. */
+	for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ )
+	{
+		if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] )
+		{
+			/* The check has not incremented so an error exists. */
+			xReturn = pdFALSE;
+		}
+
+		usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ];
+	}
+
+	return xReturn;
+}
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ReadMe.txt b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ReadMe.txt
new file mode 100644
index 0000000..72b46db
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ReadMe.txt
@@ -0,0 +1,14 @@
+Contains the files that are not specific to any one demo, but are instead used
+by all the demo applications.
+
+Most of the directories are now obsolete, and only maintained for backward
+compatibility.  The directories in active use are:
+
++ Minimal - this contains the implementation of what are referred to as the
+"Standard Demo Tasks".  These are used by all the demo applications.  Their only
+purpose is to demonstrate the FreeRTOS API and test the FreeRTOS features.  The
+directory is called 'Minimal' as it contains a minimal implementation of files
+contained in the 'Full' directory - but the 'Full' directory is no longer used.
+
++ include - contains header files for the C source files located in the Minimal
+directory.
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/AT91SAM9XE128.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/AT91SAM9XE128.h
new file mode 100644
index 0000000..e548551
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/AT91SAM9XE128.h
@@ -0,0 +1,4042 @@
+//  ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+//  ----------------------------------------------------------------------------
+//  Copyright (c) 2006, Atmel Corporation
+// 
+//  All rights reserved.
+// 
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions are met:
+// 
+//  - Redistributions of source code must retain the above copyright notice,
+//  this list of conditions and the disclaimer below.
+// 
+//  - Redistributions in binary form must reproduce the above copyright notice,
+//  this list of conditions and the disclaimer below in the documentation and/or
+//  other materials provided with the distribution. 
+// 
+//  Atmel's name may not be used to endorse or promote products derived from
+//  this software without specific prior written permission. 
+//  
+//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  ----------------------------------------------------------------------------
+// File Name           : AT91SAM9XE128.h
+// Object              : AT91SAM9XE128 definitions
+// Generated           : AT91 SW Application Group  02/13/2008 (18:26:05)
+// 
+// CVS Reference       : /AT91SAM9XE128.pl/1.3/Wed Jan 30 13:58:28 2008//
+// CVS Reference       : /SYS_SAM9260.pl/1.2/Wed Feb 13 13:29:23 2008//
+// CVS Reference       : /HMATRIX1_SAM9260.pl/1.7/Mon Apr 23 10:39:45 2007//
+// CVS Reference       : /CCR_SAM9260.pl/1.2/Mon Apr 16 10:47:39 2007//
+// CVS Reference       : /PMC_SAM9262.pl/1.4/Mon Mar  7 18:03:13 2005//
+// CVS Reference       : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
+// CVS Reference       : /HSDRAMC1_6100A.pl/1.2/Mon Aug  9 10:52:25 2004//
+// CVS Reference       : /HSMC3_6105A.pl/1.4/Tue Nov 16 09:16:23 2004//
+// CVS Reference       : /AIC_6075A.pl/1.1/Mon Jul 12 17:04:01 2004//
+// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 09:02:11 2005//
+// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
+// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:29:42 2005//
+// CVS Reference       : /RSTC_6098A.pl/1.3/Thu Nov  4 13:57:00 2004//
+// CVS Reference       : /SHDWC_6122A.pl/1.3/Wed Oct  6 14:16:58 2004//
+// CVS Reference       : /RTTC_6081A.pl/1.2/Thu Nov  4 13:57:22 2004//
+// CVS Reference       : /PITC_6079A.pl/1.2/Thu Nov  4 13:56:22 2004//
+// CVS Reference       : /WDTC_6080A.pl/1.3/Thu Nov  4 13:58:52 2004//
+// CVS Reference       : /EFC2_IGS036.pl/1.2/Fri Nov 10 10:47:53 2006//
+// CVS Reference       : /TC_6082A.pl/1.7/Wed Mar  9 16:31:51 2005//
+// CVS Reference       : /MCI_6101E.pl/1.1/Fri Jun  3 13:20:23 2005//
+// CVS Reference       : /TWI_6061B.pl/1.2/Fri Aug  4 08:53:02 2006//
+// CVS Reference       : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
+// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//
+// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
+// CVS Reference       : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//
+// CVS Reference       : /UDP_6ept_puon.pl/1.1/Wed Aug 30 14:20:53 2006//
+// CVS Reference       : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005//
+// CVS Reference       : /EBI_SAM9260.pl/1.1/Fri Sep 30 12:12:14 2005//
+// CVS Reference       : /HECC_6143A.pl/1.1/Wed Feb  9 17:16:57 2005//
+// CVS Reference       : /ISI_xxxxx.pl/1.3/Thu Mar  3 11:11:48 2005//
+//  ----------------------------------------------------------------------------
+
+#ifndef AT91SAM9XE128_H
+#define AT91SAM9XE128_H
+
+#ifndef __ASSEMBLY__
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+#define AT91_CAST(a) (a)
+#else
+#define AT91_CAST(a)
+#endif
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SYS {
+	AT91_REG	 Reserved0[2560]; 	// 
+	AT91_REG	 ECC_CR; 	//  ECC reset register
+	AT91_REG	 ECC_MR; 	//  ECC Page size register
+	AT91_REG	 ECC_SR; 	//  ECC Status register
+	AT91_REG	 ECC_PR; 	//  ECC Parity register
+	AT91_REG	 ECC_NPR; 	//  ECC Parity N register
+	AT91_REG	 Reserved1[58]; 	// 
+	AT91_REG	 ECC_VR; 	//  ECC Version register
+	AT91_REG	 Reserved2[64]; 	// 
+	AT91_REG	 SDRAMC_MR; 	// SDRAM Controller Mode Register
+	AT91_REG	 SDRAMC_TR; 	// SDRAM Controller Refresh Timer Register
+	AT91_REG	 SDRAMC_CR; 	// SDRAM Controller Configuration Register
+	AT91_REG	 SDRAMC_HSR; 	// SDRAM Controller High Speed Register
+	AT91_REG	 SDRAMC_LPR; 	// SDRAM Controller Low Power Register
+	AT91_REG	 SDRAMC_IER; 	// SDRAM Controller Interrupt Enable Register
+	AT91_REG	 SDRAMC_IDR; 	// SDRAM Controller Interrupt Disable Register
+	AT91_REG	 SDRAMC_IMR; 	// SDRAM Controller Interrupt Mask Register
+	AT91_REG	 SDRAMC_ISR; 	// SDRAM Controller Interrupt Mask Register
+	AT91_REG	 SDRAMC_MDR; 	// SDRAM Memory Device Register
+	AT91_REG	 Reserved3[118]; 	// 
+	AT91_REG	 SMC_SETUP0; 	//  Setup Register for CS 0
+	AT91_REG	 SMC_PULSE0; 	//  Pulse Register for CS 0
+	AT91_REG	 SMC_CYCLE0; 	//  Cycle Register for CS 0
+	AT91_REG	 SMC_CTRL0; 	//  Control Register for CS 0
+	AT91_REG	 SMC_SETUP1; 	//  Setup Register for CS 1
+	AT91_REG	 SMC_PULSE1; 	//  Pulse Register for CS 1
+	AT91_REG	 SMC_CYCLE1; 	//  Cycle Register for CS 1
+	AT91_REG	 SMC_CTRL1; 	//  Control Register for CS 1
+	AT91_REG	 SMC_SETUP2; 	//  Setup Register for CS 2
+	AT91_REG	 SMC_PULSE2; 	//  Pulse Register for CS 2
+	AT91_REG	 SMC_CYCLE2; 	//  Cycle Register for CS 2
+	AT91_REG	 SMC_CTRL2; 	//  Control Register for CS 2
+	AT91_REG	 SMC_SETUP3; 	//  Setup Register for CS 3
+	AT91_REG	 SMC_PULSE3; 	//  Pulse Register for CS 3
+	AT91_REG	 SMC_CYCLE3; 	//  Cycle Register for CS 3
+	AT91_REG	 SMC_CTRL3; 	//  Control Register for CS 3
+	AT91_REG	 SMC_SETUP4; 	//  Setup Register for CS 4
+	AT91_REG	 SMC_PULSE4; 	//  Pulse Register for CS 4
+	AT91_REG	 SMC_CYCLE4; 	//  Cycle Register for CS 4
+	AT91_REG	 SMC_CTRL4; 	//  Control Register for CS 4
+	AT91_REG	 SMC_SETUP5; 	//  Setup Register for CS 5
+	AT91_REG	 SMC_PULSE5; 	//  Pulse Register for CS 5
+	AT91_REG	 SMC_CYCLE5; 	//  Cycle Register for CS 5
+	AT91_REG	 SMC_CTRL5; 	//  Control Register for CS 5
+	AT91_REG	 SMC_SETUP6; 	//  Setup Register for CS 6
+	AT91_REG	 SMC_PULSE6; 	//  Pulse Register for CS 6
+	AT91_REG	 SMC_CYCLE6; 	//  Cycle Register for CS 6
+	AT91_REG	 SMC_CTRL6; 	//  Control Register for CS 6
+	AT91_REG	 SMC_SETUP7; 	//  Setup Register for CS 7
+	AT91_REG	 SMC_PULSE7; 	//  Pulse Register for CS 7
+	AT91_REG	 SMC_CYCLE7; 	//  Cycle Register for CS 7
+	AT91_REG	 SMC_CTRL7; 	//  Control Register for CS 7
+	AT91_REG	 Reserved4[96]; 	// 
+	AT91_REG	 MATRIX_MCFG0; 	//  Master Configuration Register 0 (ram96k)     
+	AT91_REG	 MATRIX_MCFG1; 	//  Master Configuration Register 1 (rom)    
+	AT91_REG	 MATRIX_MCFG2; 	//  Master Configuration Register 2 (hperiphs) 
+	AT91_REG	 MATRIX_MCFG3; 	//  Master Configuration Register 3 (ebi)
+	AT91_REG	 MATRIX_MCFG4; 	//  Master Configuration Register 4 (bridge)    
+	AT91_REG	 MATRIX_MCFG5; 	//  Master Configuration Register 5 (mailbox)    
+	AT91_REG	 MATRIX_MCFG6; 	//  Master Configuration Register 6 (ram16k)  
+	AT91_REG	 MATRIX_MCFG7; 	//  Master Configuration Register 7 (teak_prog)     
+	AT91_REG	 Reserved5[8]; 	// 
+	AT91_REG	 MATRIX_SCFG0; 	//  Slave Configuration Register 0 (ram96k)     
+	AT91_REG	 MATRIX_SCFG1; 	//  Slave Configuration Register 1 (rom)    
+	AT91_REG	 MATRIX_SCFG2; 	//  Slave Configuration Register 2 (hperiphs) 
+	AT91_REG	 MATRIX_SCFG3; 	//  Slave Configuration Register 3 (ebi)
+	AT91_REG	 MATRIX_SCFG4; 	//  Slave Configuration Register 4 (bridge)    
+	AT91_REG	 Reserved6[11]; 	// 
+	AT91_REG	 MATRIX_PRAS0; 	//  PRAS0 (ram0) 
+	AT91_REG	 MATRIX_PRBS0; 	//  PRBS0 (ram0) 
+	AT91_REG	 MATRIX_PRAS1; 	//  PRAS1 (ram1) 
+	AT91_REG	 MATRIX_PRBS1; 	//  PRBS1 (ram1) 
+	AT91_REG	 MATRIX_PRAS2; 	//  PRAS2 (ram2) 
+	AT91_REG	 MATRIX_PRBS2; 	//  PRBS2 (ram2) 
+	AT91_REG	 MATRIX_PRAS3; 	//  PRAS3 : usb_dev_hs
+	AT91_REG	 MATRIX_PRBS3; 	//  PRBS3 : usb_dev_hs
+	AT91_REG	 MATRIX_PRAS4; 	//  PRAS4 : ebi
+	AT91_REG	 MATRIX_PRBS4; 	//  PRBS4 : ebi
+	AT91_REG	 Reserved7[22]; 	// 
+	AT91_REG	 MATRIX_MRCR; 	//  Master Remp Control Register 
+	AT91_REG	 Reserved8[6]; 	// 
+	AT91_REG	 CCFG_EBICSA; 	//  EBI Chip Select Assignement Register
+	AT91_REG	 Reserved9[3]; 	// 
+	AT91_REG	 MATRIX_TEAKCFG; 	//  Slave 7 (teak_prog) Special Function Register
+	AT91_REG	 Reserved10[51]; 	// 
+	AT91_REG	 CCFG_MATRIXVERSION; 	//  Version Register
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved11[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved12[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+	AT91_REG	 Reserved13[45]; 	// 
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved14[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved15[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+	AT91_REG	 Reserved16[54]; 	// 
+	AT91_REG	 PIOA_PER; 	// PIO Enable Register
+	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOA_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved17[1]; 	// 
+	AT91_REG	 PIOA_OER; 	// Output Enable Register
+	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOA_OSR; 	// Output Status Register
+	AT91_REG	 Reserved18[1]; 	// 
+	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved19[1]; 	// 
+	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved20[1]; 	// 
+	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved21[1]; 	// 
+	AT91_REG	 PIOA_ASR; 	// Select A Register
+	AT91_REG	 PIOA_BSR; 	// Select B Register
+	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved22[9]; 	// 
+	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved23[213]; 	// 
+	AT91_REG	 PIOB_PER; 	// PIO Enable Register
+	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOB_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved24[1]; 	// 
+	AT91_REG	 PIOB_OER; 	// Output Enable Register
+	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOB_OSR; 	// Output Status Register
+	AT91_REG	 Reserved25[1]; 	// 
+	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved26[1]; 	// 
+	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved27[1]; 	// 
+	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved28[1]; 	// 
+	AT91_REG	 PIOB_ASR; 	// Select A Register
+	AT91_REG	 PIOB_BSR; 	// Select B Register
+	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved29[9]; 	// 
+	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved30[85]; 	// 
+	AT91_REG	 PIOC_PER; 	// PIO Enable Register
+	AT91_REG	 PIOC_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOC_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved31[1]; 	// 
+	AT91_REG	 PIOC_OER; 	// Output Enable Register
+	AT91_REG	 PIOC_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOC_OSR; 	// Output Status Register
+	AT91_REG	 Reserved32[1]; 	// 
+	AT91_REG	 PIOC_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOC_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOC_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved33[1]; 	// 
+	AT91_REG	 PIOC_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOC_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOC_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOC_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOC_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOC_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOC_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOC_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved34[1]; 	// 
+	AT91_REG	 PIOC_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOC_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOC_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved35[1]; 	// 
+	AT91_REG	 PIOC_ASR; 	// Select A Register
+	AT91_REG	 PIOC_BSR; 	// Select B Register
+	AT91_REG	 PIOC_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved36[9]; 	// 
+	AT91_REG	 PIOC_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOC_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOC_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved37[85]; 	// 
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved38[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved39[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 PMC_PLLAR; 	// PLL A Register
+	AT91_REG	 PMC_PLLBR; 	// PLL B Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved40[3]; 	// 
+	AT91_REG	 PMC_PCKR[8]; 	// Programmable Clock Register
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved41[36]; 	// 
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+	AT91_REG	 Reserved42[1]; 	// 
+	AT91_REG	 SHDWC_SHCR; 	// Shut Down Control Register
+	AT91_REG	 SHDWC_SHMR; 	// Shut Down Mode Register
+	AT91_REG	 SHDWC_SHSR; 	// Shut Down Status Register
+	AT91_REG	 Reserved43[1]; 	// 
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+	AT91_REG	 Reserved44[1]; 	// 
+	AT91_REG	 SYS_GPBR[4]; 	// General Purpose Register
+} AT91S_SYS, *AT91PS_SYS;
+#else
+#define SYS_GPBR        (AT91_CAST(AT91_REG *) 	0x00003D50) // (SYS_GPBR) General Purpose Register
+
+#endif
+// -------- GPBR : (SYS Offset: 0x3d50) GPBR General Purpose Register -------- 
+#define AT91C_GPBR_GPRV       (0x0 <<  0) // (SYS) General Purpose Register Value
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR External Bus Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_EBI {
+	AT91_REG	 EBI_DUMMY; 	// Dummy register - Do not use
+} AT91S_EBI, *AT91PS_EBI;
+#else
+#define EBI_DUMMY       (AT91_CAST(AT91_REG *) 	0x00000000) // (EBI_DUMMY) Dummy register - Do not use
+
+#endif
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Error Correction Code controller
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_ECC {
+	AT91_REG	 ECC_CR; 	//  ECC reset register
+	AT91_REG	 ECC_MR; 	//  ECC Page size register
+	AT91_REG	 ECC_SR; 	//  ECC Status register
+	AT91_REG	 ECC_PR; 	//  ECC Parity register
+	AT91_REG	 ECC_NPR; 	//  ECC Parity N register
+	AT91_REG	 Reserved0[58]; 	// 
+	AT91_REG	 ECC_VR; 	//  ECC Version register
+} AT91S_ECC, *AT91PS_ECC;
+#else
+#define ECC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (ECC_CR)  ECC reset register
+#define ECC_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (ECC_MR)  ECC Page size register
+#define ECC_SR          (AT91_CAST(AT91_REG *) 	0x00000008) // (ECC_SR)  ECC Status register
+#define ECC_PR          (AT91_CAST(AT91_REG *) 	0x0000000C) // (ECC_PR)  ECC Parity register
+#define ECC_NPR         (AT91_CAST(AT91_REG *) 	0x00000010) // (ECC_NPR)  ECC Parity N register
+#define ECC_VR          (AT91_CAST(AT91_REG *) 	0x000000FC) // (ECC_VR)  ECC Version register
+
+#endif
+// -------- ECC_CR : (ECC Offset: 0x0) ECC reset register -------- 
+#define AT91C_ECC_RST         (0x1 <<  0) // (ECC) ECC reset parity
+// -------- ECC_MR : (ECC Offset: 0x4) ECC page size register -------- 
+#define AT91C_ECC_PAGE_SIZE   (0x3 <<  0) // (ECC) Nand Flash page size
+// -------- ECC_SR : (ECC Offset: 0x8) ECC status register -------- 
+#define AT91C_ECC_RECERR      (0x1 <<  0) // (ECC) ECC error
+#define AT91C_ECC_ECCERR      (0x1 <<  1) // (ECC) ECC single error
+#define AT91C_ECC_MULERR      (0x1 <<  2) // (ECC) ECC_MULERR
+// -------- ECC_PR : (ECC Offset: 0xc) ECC parity register -------- 
+#define AT91C_ECC_BITADDR     (0xF <<  0) // (ECC) Bit address error
+#define AT91C_ECC_WORDADDR    (0xFFF <<  4) // (ECC) address of the failing bit
+// -------- ECC_NPR : (ECC Offset: 0x10) ECC N parity register -------- 
+#define AT91C_ECC_NPARITY     (0xFFFF <<  0) // (ECC) ECC parity N 
+// -------- ECC_VR : (ECC Offset: 0xfc) ECC version register -------- 
+#define AT91C_ECC_VR          (0xF <<  0) // (ECC) ECC version register
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR SDRAM Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SDRAMC {
+	AT91_REG	 SDRAMC_MR; 	// SDRAM Controller Mode Register
+	AT91_REG	 SDRAMC_TR; 	// SDRAM Controller Refresh Timer Register
+	AT91_REG	 SDRAMC_CR; 	// SDRAM Controller Configuration Register
+	AT91_REG	 SDRAMC_HSR; 	// SDRAM Controller High Speed Register
+	AT91_REG	 SDRAMC_LPR; 	// SDRAM Controller Low Power Register
+	AT91_REG	 SDRAMC_IER; 	// SDRAM Controller Interrupt Enable Register
+	AT91_REG	 SDRAMC_IDR; 	// SDRAM Controller Interrupt Disable Register
+	AT91_REG	 SDRAMC_IMR; 	// SDRAM Controller Interrupt Mask Register
+	AT91_REG	 SDRAMC_ISR; 	// SDRAM Controller Interrupt Mask Register
+	AT91_REG	 SDRAMC_MDR; 	// SDRAM Memory Device Register
+} AT91S_SDRAMC, *AT91PS_SDRAMC;
+#else
+#define SDRAMC_MR       (AT91_CAST(AT91_REG *) 	0x00000000) // (SDRAMC_MR) SDRAM Controller Mode Register
+#define SDRAMC_TR       (AT91_CAST(AT91_REG *) 	0x00000004) // (SDRAMC_TR) SDRAM Controller Refresh Timer Register
+#define SDRAMC_CR       (AT91_CAST(AT91_REG *) 	0x00000008) // (SDRAMC_CR) SDRAM Controller Configuration Register
+#define SDRAMC_HSR      (AT91_CAST(AT91_REG *) 	0x0000000C) // (SDRAMC_HSR) SDRAM Controller High Speed Register
+#define SDRAMC_LPR      (AT91_CAST(AT91_REG *) 	0x00000010) // (SDRAMC_LPR) SDRAM Controller Low Power Register
+#define SDRAMC_IER      (AT91_CAST(AT91_REG *) 	0x00000014) // (SDRAMC_IER) SDRAM Controller Interrupt Enable Register
+#define SDRAMC_IDR      (AT91_CAST(AT91_REG *) 	0x00000018) // (SDRAMC_IDR) SDRAM Controller Interrupt Disable Register
+#define SDRAMC_IMR      (AT91_CAST(AT91_REG *) 	0x0000001C) // (SDRAMC_IMR) SDRAM Controller Interrupt Mask Register
+#define SDRAMC_ISR      (AT91_CAST(AT91_REG *) 	0x00000020) // (SDRAMC_ISR) SDRAM Controller Interrupt Mask Register
+#define SDRAMC_MDR      (AT91_CAST(AT91_REG *) 	0x00000024) // (SDRAMC_MDR) SDRAM Memory Device Register
+
+#endif
+// -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register -------- 
+#define AT91C_SDRAMC_MODE     (0xF <<  0) // (SDRAMC) Mode
+#define 	AT91C_SDRAMC_MODE_NORMAL_CMD           (0x0) // (SDRAMC) Normal Mode
+#define 	AT91C_SDRAMC_MODE_NOP_CMD              (0x1) // (SDRAMC) Issue a NOP Command at every access
+#define 	AT91C_SDRAMC_MODE_PRCGALL_CMD          (0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access
+#define 	AT91C_SDRAMC_MODE_LMR_CMD              (0x3) // (SDRAMC) Issue a Load Mode Register at every access
+#define 	AT91C_SDRAMC_MODE_RFSH_CMD             (0x4) // (SDRAMC) Issue a Refresh
+#define 	AT91C_SDRAMC_MODE_EXT_LMR_CMD          (0x5) // (SDRAMC) Issue an Extended Load Mode Register
+#define 	AT91C_SDRAMC_MODE_DEEP_CMD             (0x6) // (SDRAMC) Enter Deep Power Mode
+// -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register -------- 
+#define AT91C_SDRAMC_COUNT    (0xFFF <<  0) // (SDRAMC) Refresh Counter
+// -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register -------- 
+#define AT91C_SDRAMC_NC       (0x3 <<  0) // (SDRAMC) Number of Column Bits
+#define 	AT91C_SDRAMC_NC_8                    (0x0) // (SDRAMC) 8 Bits
+#define 	AT91C_SDRAMC_NC_9                    (0x1) // (SDRAMC) 9 Bits
+#define 	AT91C_SDRAMC_NC_10                   (0x2) // (SDRAMC) 10 Bits
+#define 	AT91C_SDRAMC_NC_11                   (0x3) // (SDRAMC) 11 Bits
+#define AT91C_SDRAMC_NR       (0x3 <<  2) // (SDRAMC) Number of Row Bits
+#define 	AT91C_SDRAMC_NR_11                   (0x0 <<  2) // (SDRAMC) 11 Bits
+#define 	AT91C_SDRAMC_NR_12                   (0x1 <<  2) // (SDRAMC) 12 Bits
+#define 	AT91C_SDRAMC_NR_13                   (0x2 <<  2) // (SDRAMC) 13 Bits
+#define AT91C_SDRAMC_NB       (0x1 <<  4) // (SDRAMC) Number of Banks
+#define 	AT91C_SDRAMC_NB_2_BANKS              (0x0 <<  4) // (SDRAMC) 2 banks
+#define 	AT91C_SDRAMC_NB_4_BANKS              (0x1 <<  4) // (SDRAMC) 4 banks
+#define AT91C_SDRAMC_CAS      (0x3 <<  5) // (SDRAMC) CAS Latency
+#define 	AT91C_SDRAMC_CAS_2                    (0x2 <<  5) // (SDRAMC) 2 cycles
+#define 	AT91C_SDRAMC_CAS_3                    (0x3 <<  5) // (SDRAMC) 3 cycles
+#define AT91C_SDRAMC_DBW      (0x1 <<  7) // (SDRAMC) Data Bus Width
+#define 	AT91C_SDRAMC_DBW_32_BITS              (0x0 <<  7) // (SDRAMC) 32 Bits datas bus
+#define 	AT91C_SDRAMC_DBW_16_BITS              (0x1 <<  7) // (SDRAMC) 16 Bits datas bus
+#define AT91C_SDRAMC_TWR      (0xF <<  8) // (SDRAMC) Number of Write Recovery Time Cycles
+#define 	AT91C_SDRAMC_TWR_0                    (0x0 <<  8) // (SDRAMC) Value :  0
+#define 	AT91C_SDRAMC_TWR_1                    (0x1 <<  8) // (SDRAMC) Value :  1
+#define 	AT91C_SDRAMC_TWR_2                    (0x2 <<  8) // (SDRAMC) Value :  2
+#define 	AT91C_SDRAMC_TWR_3                    (0x3 <<  8) // (SDRAMC) Value :  3
+#define 	AT91C_SDRAMC_TWR_4                    (0x4 <<  8) // (SDRAMC) Value :  4
+#define 	AT91C_SDRAMC_TWR_5                    (0x5 <<  8) // (SDRAMC) Value :  5
+#define 	AT91C_SDRAMC_TWR_6                    (0x6 <<  8) // (SDRAMC) Value :  6
+#define 	AT91C_SDRAMC_TWR_7                    (0x7 <<  8) // (SDRAMC) Value :  7
+#define 	AT91C_SDRAMC_TWR_8                    (0x8 <<  8) // (SDRAMC) Value :  8
+#define 	AT91C_SDRAMC_TWR_9                    (0x9 <<  8) // (SDRAMC) Value :  9
+#define 	AT91C_SDRAMC_TWR_10                   (0xA <<  8) // (SDRAMC) Value : 10
+#define 	AT91C_SDRAMC_TWR_11                   (0xB <<  8) // (SDRAMC) Value : 11
+#define 	AT91C_SDRAMC_TWR_12                   (0xC <<  8) // (SDRAMC) Value : 12
+#define 	AT91C_SDRAMC_TWR_13                   (0xD <<  8) // (SDRAMC) Value : 13
+#define 	AT91C_SDRAMC_TWR_14                   (0xE <<  8) // (SDRAMC) Value : 14
+#define 	AT91C_SDRAMC_TWR_15                   (0xF <<  8) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TRC      (0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles
+#define 	AT91C_SDRAMC_TRC_0                    (0x0 << 12) // (SDRAMC) Value :  0
+#define 	AT91C_SDRAMC_TRC_1                    (0x1 << 12) // (SDRAMC) Value :  1
+#define 	AT91C_SDRAMC_TRC_2                    (0x2 << 12) // (SDRAMC) Value :  2
+#define 	AT91C_SDRAMC_TRC_3                    (0x3 << 12) // (SDRAMC) Value :  3
+#define 	AT91C_SDRAMC_TRC_4                    (0x4 << 12) // (SDRAMC) Value :  4
+#define 	AT91C_SDRAMC_TRC_5                    (0x5 << 12) // (SDRAMC) Value :  5
+#define 	AT91C_SDRAMC_TRC_6                    (0x6 << 12) // (SDRAMC) Value :  6
+#define 	AT91C_SDRAMC_TRC_7                    (0x7 << 12) // (SDRAMC) Value :  7
+#define 	AT91C_SDRAMC_TRC_8                    (0x8 << 12) // (SDRAMC) Value :  8
+#define 	AT91C_SDRAMC_TRC_9                    (0x9 << 12) // (SDRAMC) Value :  9
+#define 	AT91C_SDRAMC_TRC_10                   (0xA << 12) // (SDRAMC) Value : 10
+#define 	AT91C_SDRAMC_TRC_11                   (0xB << 12) // (SDRAMC) Value : 11
+#define 	AT91C_SDRAMC_TRC_12                   (0xC << 12) // (SDRAMC) Value : 12
+#define 	AT91C_SDRAMC_TRC_13                   (0xD << 12) // (SDRAMC) Value : 13
+#define 	AT91C_SDRAMC_TRC_14                   (0xE << 12) // (SDRAMC) Value : 14
+#define 	AT91C_SDRAMC_TRC_15                   (0xF << 12) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TRP      (0xF << 16) // (SDRAMC) Number of RAS Precharge Time Cycles
+#define 	AT91C_SDRAMC_TRP_0                    (0x0 << 16) // (SDRAMC) Value :  0
+#define 	AT91C_SDRAMC_TRP_1                    (0x1 << 16) // (SDRAMC) Value :  1
+#define 	AT91C_SDRAMC_TRP_2                    (0x2 << 16) // (SDRAMC) Value :  2
+#define 	AT91C_SDRAMC_TRP_3                    (0x3 << 16) // (SDRAMC) Value :  3
+#define 	AT91C_SDRAMC_TRP_4                    (0x4 << 16) // (SDRAMC) Value :  4
+#define 	AT91C_SDRAMC_TRP_5                    (0x5 << 16) // (SDRAMC) Value :  5
+#define 	AT91C_SDRAMC_TRP_6                    (0x6 << 16) // (SDRAMC) Value :  6
+#define 	AT91C_SDRAMC_TRP_7                    (0x7 << 16) // (SDRAMC) Value :  7
+#define 	AT91C_SDRAMC_TRP_8                    (0x8 << 16) // (SDRAMC) Value :  8
+#define 	AT91C_SDRAMC_TRP_9                    (0x9 << 16) // (SDRAMC) Value :  9
+#define 	AT91C_SDRAMC_TRP_10                   (0xA << 16) // (SDRAMC) Value : 10
+#define 	AT91C_SDRAMC_TRP_11                   (0xB << 16) // (SDRAMC) Value : 11
+#define 	AT91C_SDRAMC_TRP_12                   (0xC << 16) // (SDRAMC) Value : 12
+#define 	AT91C_SDRAMC_TRP_13                   (0xD << 16) // (SDRAMC) Value : 13
+#define 	AT91C_SDRAMC_TRP_14                   (0xE << 16) // (SDRAMC) Value : 14
+#define 	AT91C_SDRAMC_TRP_15                   (0xF << 16) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TRCD     (0xF << 20) // (SDRAMC) Number of RAS to CAS Delay Cycles
+#define 	AT91C_SDRAMC_TRCD_0                    (0x0 << 20) // (SDRAMC) Value :  0
+#define 	AT91C_SDRAMC_TRCD_1                    (0x1 << 20) // (SDRAMC) Value :  1
+#define 	AT91C_SDRAMC_TRCD_2                    (0x2 << 20) // (SDRAMC) Value :  2
+#define 	AT91C_SDRAMC_TRCD_3                    (0x3 << 20) // (SDRAMC) Value :  3
+#define 	AT91C_SDRAMC_TRCD_4                    (0x4 << 20) // (SDRAMC) Value :  4
+#define 	AT91C_SDRAMC_TRCD_5                    (0x5 << 20) // (SDRAMC) Value :  5
+#define 	AT91C_SDRAMC_TRCD_6                    (0x6 << 20) // (SDRAMC) Value :  6
+#define 	AT91C_SDRAMC_TRCD_7                    (0x7 << 20) // (SDRAMC) Value :  7
+#define 	AT91C_SDRAMC_TRCD_8                    (0x8 << 20) // (SDRAMC) Value :  8
+#define 	AT91C_SDRAMC_TRCD_9                    (0x9 << 20) // (SDRAMC) Value :  9
+#define 	AT91C_SDRAMC_TRCD_10                   (0xA << 20) // (SDRAMC) Value : 10
+#define 	AT91C_SDRAMC_TRCD_11                   (0xB << 20) // (SDRAMC) Value : 11
+#define 	AT91C_SDRAMC_TRCD_12                   (0xC << 20) // (SDRAMC) Value : 12
+#define 	AT91C_SDRAMC_TRCD_13                   (0xD << 20) // (SDRAMC) Value : 13
+#define 	AT91C_SDRAMC_TRCD_14                   (0xE << 20) // (SDRAMC) Value : 14
+#define 	AT91C_SDRAMC_TRCD_15                   (0xF << 20) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TRAS     (0xF << 24) // (SDRAMC) Number of RAS Active Time Cycles
+#define 	AT91C_SDRAMC_TRAS_0                    (0x0 << 24) // (SDRAMC) Value :  0
+#define 	AT91C_SDRAMC_TRAS_1                    (0x1 << 24) // (SDRAMC) Value :  1
+#define 	AT91C_SDRAMC_TRAS_2                    (0x2 << 24) // (SDRAMC) Value :  2
+#define 	AT91C_SDRAMC_TRAS_3                    (0x3 << 24) // (SDRAMC) Value :  3
+#define 	AT91C_SDRAMC_TRAS_4                    (0x4 << 24) // (SDRAMC) Value :  4
+#define 	AT91C_SDRAMC_TRAS_5                    (0x5 << 24) // (SDRAMC) Value :  5
+#define 	AT91C_SDRAMC_TRAS_6                    (0x6 << 24) // (SDRAMC) Value :  6
+#define 	AT91C_SDRAMC_TRAS_7                    (0x7 << 24) // (SDRAMC) Value :  7
+#define 	AT91C_SDRAMC_TRAS_8                    (0x8 << 24) // (SDRAMC) Value :  8
+#define 	AT91C_SDRAMC_TRAS_9                    (0x9 << 24) // (SDRAMC) Value :  9
+#define 	AT91C_SDRAMC_TRAS_10                   (0xA << 24) // (SDRAMC) Value : 10
+#define 	AT91C_SDRAMC_TRAS_11                   (0xB << 24) // (SDRAMC) Value : 11
+#define 	AT91C_SDRAMC_TRAS_12                   (0xC << 24) // (SDRAMC) Value : 12
+#define 	AT91C_SDRAMC_TRAS_13                   (0xD << 24) // (SDRAMC) Value : 13
+#define 	AT91C_SDRAMC_TRAS_14                   (0xE << 24) // (SDRAMC) Value : 14
+#define 	AT91C_SDRAMC_TRAS_15                   (0xF << 24) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TXSR     (0xF << 28) // (SDRAMC) Number of Command Recovery Time Cycles
+#define 	AT91C_SDRAMC_TXSR_0                    (0x0 << 28) // (SDRAMC) Value :  0
+#define 	AT91C_SDRAMC_TXSR_1                    (0x1 << 28) // (SDRAMC) Value :  1
+#define 	AT91C_SDRAMC_TXSR_2                    (0x2 << 28) // (SDRAMC) Value :  2
+#define 	AT91C_SDRAMC_TXSR_3                    (0x3 << 28) // (SDRAMC) Value :  3
+#define 	AT91C_SDRAMC_TXSR_4                    (0x4 << 28) // (SDRAMC) Value :  4
+#define 	AT91C_SDRAMC_TXSR_5                    (0x5 << 28) // (SDRAMC) Value :  5
+#define 	AT91C_SDRAMC_TXSR_6                    (0x6 << 28) // (SDRAMC) Value :  6
+#define 	AT91C_SDRAMC_TXSR_7                    (0x7 << 28) // (SDRAMC) Value :  7
+#define 	AT91C_SDRAMC_TXSR_8                    (0x8 << 28) // (SDRAMC) Value :  8
+#define 	AT91C_SDRAMC_TXSR_9                    (0x9 << 28) // (SDRAMC) Value :  9
+#define 	AT91C_SDRAMC_TXSR_10                   (0xA << 28) // (SDRAMC) Value : 10
+#define 	AT91C_SDRAMC_TXSR_11                   (0xB << 28) // (SDRAMC) Value : 11
+#define 	AT91C_SDRAMC_TXSR_12                   (0xC << 28) // (SDRAMC) Value : 12
+#define 	AT91C_SDRAMC_TXSR_13                   (0xD << 28) // (SDRAMC) Value : 13
+#define 	AT91C_SDRAMC_TXSR_14                   (0xE << 28) // (SDRAMC) Value : 14
+#define 	AT91C_SDRAMC_TXSR_15                   (0xF << 28) // (SDRAMC) Value : 15
+// -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register -------- 
+#define AT91C_SDRAMC_DA       (0x1 <<  0) // (SDRAMC) Decode Cycle Enable Bit
+#define 	AT91C_SDRAMC_DA_DISABLE              (0x0) // (SDRAMC) Disable Decode Cycle
+#define 	AT91C_SDRAMC_DA_ENABLE               (0x1) // (SDRAMC) Enable Decode Cycle
+// -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register -------- 
+#define AT91C_SDRAMC_LPCB     (0x3 <<  0) // (SDRAMC) Low-power Configurations
+#define 	AT91C_SDRAMC_LPCB_DISABLE              (0x0) // (SDRAMC) Disable Low Power Features
+#define 	AT91C_SDRAMC_LPCB_SELF_REFRESH         (0x1) // (SDRAMC) Enable SELF_REFRESH
+#define 	AT91C_SDRAMC_LPCB_POWER_DOWN           (0x2) // (SDRAMC) Enable POWER_DOWN
+#define 	AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN      (0x3) // (SDRAMC) Enable DEEP_POWER_DOWN
+#define AT91C_SDRAMC_PASR     (0x7 <<  4) // (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM)
+#define AT91C_SDRAMC_TCSR     (0x3 <<  8) // (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM)
+#define AT91C_SDRAMC_DS       (0x3 << 10) // (SDRAMC) Drive Strenght (only for Low Power SDRAM)
+#define AT91C_SDRAMC_TIMEOUT  (0x3 << 12) // (SDRAMC) Time to define when Low Power Mode is enabled
+#define 	AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES         (0x0 << 12) // (SDRAMC) Activate SDRAM Low Power Mode Immediately
+#define 	AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES        (0x1 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
+#define 	AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES       (0x2 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
+// -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- 
+#define AT91C_SDRAMC_RES      (0x1 <<  0) // (SDRAMC) Refresh Error Status
+// -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- 
+// -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- 
+// -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- 
+// -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register -------- 
+#define AT91C_SDRAMC_MD       (0x3 <<  0) // (SDRAMC) Memory Device Type
+#define 	AT91C_SDRAMC_MD_SDRAM                (0x0) // (SDRAMC) SDRAM Mode
+#define 	AT91C_SDRAMC_MD_LOW_POWER_SDRAM      (0x1) // (SDRAMC) SDRAM Low Power Mode
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Static Memory Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SMC {
+	AT91_REG	 SMC_SETUP0; 	//  Setup Register for CS 0
+	AT91_REG	 SMC_PULSE0; 	//  Pulse Register for CS 0
+	AT91_REG	 SMC_CYCLE0; 	//  Cycle Register for CS 0
+	AT91_REG	 SMC_CTRL0; 	//  Control Register for CS 0
+	AT91_REG	 SMC_SETUP1; 	//  Setup Register for CS 1
+	AT91_REG	 SMC_PULSE1; 	//  Pulse Register for CS 1
+	AT91_REG	 SMC_CYCLE1; 	//  Cycle Register for CS 1
+	AT91_REG	 SMC_CTRL1; 	//  Control Register for CS 1
+	AT91_REG	 SMC_SETUP2; 	//  Setup Register for CS 2
+	AT91_REG	 SMC_PULSE2; 	//  Pulse Register for CS 2
+	AT91_REG	 SMC_CYCLE2; 	//  Cycle Register for CS 2
+	AT91_REG	 SMC_CTRL2; 	//  Control Register for CS 2
+	AT91_REG	 SMC_SETUP3; 	//  Setup Register for CS 3
+	AT91_REG	 SMC_PULSE3; 	//  Pulse Register for CS 3
+	AT91_REG	 SMC_CYCLE3; 	//  Cycle Register for CS 3
+	AT91_REG	 SMC_CTRL3; 	//  Control Register for CS 3
+	AT91_REG	 SMC_SETUP4; 	//  Setup Register for CS 4
+	AT91_REG	 SMC_PULSE4; 	//  Pulse Register for CS 4
+	AT91_REG	 SMC_CYCLE4; 	//  Cycle Register for CS 4
+	AT91_REG	 SMC_CTRL4; 	//  Control Register for CS 4
+	AT91_REG	 SMC_SETUP5; 	//  Setup Register for CS 5
+	AT91_REG	 SMC_PULSE5; 	//  Pulse Register for CS 5
+	AT91_REG	 SMC_CYCLE5; 	//  Cycle Register for CS 5
+	AT91_REG	 SMC_CTRL5; 	//  Control Register for CS 5
+	AT91_REG	 SMC_SETUP6; 	//  Setup Register for CS 6
+	AT91_REG	 SMC_PULSE6; 	//  Pulse Register for CS 6
+	AT91_REG	 SMC_CYCLE6; 	//  Cycle Register for CS 6
+	AT91_REG	 SMC_CTRL6; 	//  Control Register for CS 6
+	AT91_REG	 SMC_SETUP7; 	//  Setup Register for CS 7
+	AT91_REG	 SMC_PULSE7; 	//  Pulse Register for CS 7
+	AT91_REG	 SMC_CYCLE7; 	//  Cycle Register for CS 7
+	AT91_REG	 SMC_CTRL7; 	//  Control Register for CS 7
+} AT91S_SMC, *AT91PS_SMC;
+#else
+#define SETUP0          (AT91_CAST(AT91_REG *) 	0x00000000) // (SETUP0)  Setup Register for CS 0
+#define PULSE0          (AT91_CAST(AT91_REG *) 	0x00000004) // (PULSE0)  Pulse Register for CS 0
+#define CYCLE0          (AT91_CAST(AT91_REG *) 	0x00000008) // (CYCLE0)  Cycle Register for CS 0
+#define CTRL0           (AT91_CAST(AT91_REG *) 	0x0000000C) // (CTRL0)  Control Register for CS 0
+#define SETUP1          (AT91_CAST(AT91_REG *) 	0x00000010) // (SETUP1)  Setup Register for CS 1
+#define PULSE1          (AT91_CAST(AT91_REG *) 	0x00000014) // (PULSE1)  Pulse Register for CS 1
+#define CYCLE1          (AT91_CAST(AT91_REG *) 	0x00000018) // (CYCLE1)  Cycle Register for CS 1
+#define CTRL1           (AT91_CAST(AT91_REG *) 	0x0000001C) // (CTRL1)  Control Register for CS 1
+#define SETUP2          (AT91_CAST(AT91_REG *) 	0x00000020) // (SETUP2)  Setup Register for CS 2
+#define PULSE2          (AT91_CAST(AT91_REG *) 	0x00000024) // (PULSE2)  Pulse Register for CS 2
+#define CYCLE2          (AT91_CAST(AT91_REG *) 	0x00000028) // (CYCLE2)  Cycle Register for CS 2
+#define CTRL2           (AT91_CAST(AT91_REG *) 	0x0000002C) // (CTRL2)  Control Register for CS 2
+#define SETUP3          (AT91_CAST(AT91_REG *) 	0x00000030) // (SETUP3)  Setup Register for CS 3
+#define PULSE3          (AT91_CAST(AT91_REG *) 	0x00000034) // (PULSE3)  Pulse Register for CS 3
+#define CYCLE3          (AT91_CAST(AT91_REG *) 	0x00000038) // (CYCLE3)  Cycle Register for CS 3
+#define CTRL3           (AT91_CAST(AT91_REG *) 	0x0000003C) // (CTRL3)  Control Register for CS 3
+#define SETUP4          (AT91_CAST(AT91_REG *) 	0x00000040) // (SETUP4)  Setup Register for CS 4
+#define PULSE4          (AT91_CAST(AT91_REG *) 	0x00000044) // (PULSE4)  Pulse Register for CS 4
+#define CYCLE4          (AT91_CAST(AT91_REG *) 	0x00000048) // (CYCLE4)  Cycle Register for CS 4
+#define CTRL4           (AT91_CAST(AT91_REG *) 	0x0000004C) // (CTRL4)  Control Register for CS 4
+#define SETUP5          (AT91_CAST(AT91_REG *) 	0x00000050) // (SETUP5)  Setup Register for CS 5
+#define PULSE5          (AT91_CAST(AT91_REG *) 	0x00000054) // (PULSE5)  Pulse Register for CS 5
+#define CYCLE5          (AT91_CAST(AT91_REG *) 	0x00000058) // (CYCLE5)  Cycle Register for CS 5
+#define CTRL5           (AT91_CAST(AT91_REG *) 	0x0000005C) // (CTRL5)  Control Register for CS 5
+#define SETUP6          (AT91_CAST(AT91_REG *) 	0x00000060) // (SETUP6)  Setup Register for CS 6
+#define PULSE6          (AT91_CAST(AT91_REG *) 	0x00000064) // (PULSE6)  Pulse Register for CS 6
+#define CYCLE6          (AT91_CAST(AT91_REG *) 	0x00000068) // (CYCLE6)  Cycle Register for CS 6
+#define CTRL6           (AT91_CAST(AT91_REG *) 	0x0000006C) // (CTRL6)  Control Register for CS 6
+#define SETUP7          (AT91_CAST(AT91_REG *) 	0x00000070) // (SETUP7)  Setup Register for CS 7
+#define PULSE7          (AT91_CAST(AT91_REG *) 	0x00000074) // (PULSE7)  Pulse Register for CS 7
+#define CYCLE7          (AT91_CAST(AT91_REG *) 	0x00000078) // (CYCLE7)  Cycle Register for CS 7
+#define CTRL7           (AT91_CAST(AT91_REG *) 	0x0000007C) // (CTRL7)  Control Register for CS 7
+
+#endif
+// -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x -------- 
+#define AT91C_SMC_NWESETUP    (0x3F <<  0) // (SMC) NWE Setup Length
+#define AT91C_SMC_NCSSETUPWR  (0x3F <<  8) // (SMC) NCS Setup Length in WRite Access
+#define AT91C_SMC_NRDSETUP    (0x3F << 16) // (SMC) NRD Setup Length
+#define AT91C_SMC_NCSSETUPRD  (0x3F << 24) // (SMC) NCS Setup Length in ReaD Access
+// -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x -------- 
+#define AT91C_SMC_NWEPULSE    (0x7F <<  0) // (SMC) NWE Pulse Length
+#define AT91C_SMC_NCSPULSEWR  (0x7F <<  8) // (SMC) NCS Pulse Length in WRite Access
+#define AT91C_SMC_NRDPULSE    (0x7F << 16) // (SMC) NRD Pulse Length
+#define AT91C_SMC_NCSPULSERD  (0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access
+// -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x -------- 
+#define AT91C_SMC_NWECYCLE    (0x1FF <<  0) // (SMC) Total Write Cycle Length
+#define AT91C_SMC_NRDCYCLE    (0x1FF << 16) // (SMC) Total Read Cycle Length
+// -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x -------- 
+#define AT91C_SMC_READMODE    (0x1 <<  0) // (SMC) Read Mode
+#define AT91C_SMC_WRITEMODE   (0x1 <<  1) // (SMC) Write Mode
+#define AT91C_SMC_NWAITM      (0x3 <<  4) // (SMC) NWAIT Mode
+#define 	AT91C_SMC_NWAITM_NWAIT_DISABLE        (0x0 <<  4) // (SMC) External NWAIT disabled.
+#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN  (0x2 <<  4) // (SMC) External NWAIT enabled in frozen mode.
+#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_READY   (0x3 <<  4) // (SMC) External NWAIT enabled in ready mode.
+#define AT91C_SMC_BAT         (0x1 <<  8) // (SMC) Byte Access Type
+#define 	AT91C_SMC_BAT_BYTE_SELECT          (0x0 <<  8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
+#define 	AT91C_SMC_BAT_BYTE_WRITE           (0x1 <<  8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
+#define AT91C_SMC_DBW         (0x3 << 12) // (SMC) Data Bus Width
+#define 	AT91C_SMC_DBW_WIDTH_EIGTH_BITS     (0x0 << 12) // (SMC) 8 bits.
+#define 	AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS   (0x1 << 12) // (SMC) 16 bits.
+#define 	AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (SMC) 32 bits.
+#define AT91C_SMC_TDF         (0xF << 16) // (SMC) Data Float Time.
+#define AT91C_SMC_TDFEN       (0x1 << 20) // (SMC) TDF Enabled.
+#define AT91C_SMC_PMEN        (0x1 << 24) // (SMC) Page Mode Enabled.
+#define AT91C_SMC_PS          (0x3 << 28) // (SMC) Page Size
+#define 	AT91C_SMC_PS_SIZE_FOUR_BYTES      (0x0 << 28) // (SMC) 4 bytes.
+#define 	AT91C_SMC_PS_SIZE_EIGHT_BYTES     (0x1 << 28) // (SMC) 8 bytes.
+#define 	AT91C_SMC_PS_SIZE_SIXTEEN_BYTES   (0x2 << 28) // (SMC) 16 bytes.
+#define 	AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (SMC) 32 bytes.
+// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR AHB Matrix Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_MATRIX {
+	AT91_REG	 MATRIX_MCFG0; 	//  Master Configuration Register 0 (ram96k)     
+	AT91_REG	 MATRIX_MCFG1; 	//  Master Configuration Register 1 (rom)    
+	AT91_REG	 MATRIX_MCFG2; 	//  Master Configuration Register 2 (hperiphs) 
+	AT91_REG	 MATRIX_MCFG3; 	//  Master Configuration Register 3 (ebi)
+	AT91_REG	 MATRIX_MCFG4; 	//  Master Configuration Register 4 (bridge)    
+	AT91_REG	 MATRIX_MCFG5; 	//  Master Configuration Register 5 (mailbox)    
+	AT91_REG	 MATRIX_MCFG6; 	//  Master Configuration Register 6 (ram16k)  
+	AT91_REG	 MATRIX_MCFG7; 	//  Master Configuration Register 7 (teak_prog)     
+	AT91_REG	 Reserved0[8]; 	// 
+	AT91_REG	 MATRIX_SCFG0; 	//  Slave Configuration Register 0 (ram96k)     
+	AT91_REG	 MATRIX_SCFG1; 	//  Slave Configuration Register 1 (rom)    
+	AT91_REG	 MATRIX_SCFG2; 	//  Slave Configuration Register 2 (hperiphs) 
+	AT91_REG	 MATRIX_SCFG3; 	//  Slave Configuration Register 3 (ebi)
+	AT91_REG	 MATRIX_SCFG4; 	//  Slave Configuration Register 4 (bridge)    
+	AT91_REG	 Reserved1[11]; 	// 
+	AT91_REG	 MATRIX_PRAS0; 	//  PRAS0 (ram0) 
+	AT91_REG	 MATRIX_PRBS0; 	//  PRBS0 (ram0) 
+	AT91_REG	 MATRIX_PRAS1; 	//  PRAS1 (ram1) 
+	AT91_REG	 MATRIX_PRBS1; 	//  PRBS1 (ram1) 
+	AT91_REG	 MATRIX_PRAS2; 	//  PRAS2 (ram2) 
+	AT91_REG	 MATRIX_PRBS2; 	//  PRBS2 (ram2) 
+	AT91_REG	 MATRIX_PRAS3; 	//  PRAS3 : usb_dev_hs
+	AT91_REG	 MATRIX_PRBS3; 	//  PRBS3 : usb_dev_hs
+	AT91_REG	 MATRIX_PRAS4; 	//  PRAS4 : ebi
+	AT91_REG	 MATRIX_PRBS4; 	//  PRBS4 : ebi
+	AT91_REG	 Reserved2[22]; 	// 
+	AT91_REG	 MATRIX_MRCR; 	//  Master Remp Control Register 
+	AT91_REG	 Reserved3[6]; 	// 
+	AT91_REG	 MATRIX_EBI; 	//  Slave 3 (ebi) Special Function Register
+	AT91_REG	 Reserved4[3]; 	// 
+	AT91_REG	 MATRIX_TEAKCFG; 	//  Slave 7 (teak_prog) Special Function Register
+	AT91_REG	 Reserved5[51]; 	// 
+	AT91_REG	 MATRIX_VERSION; 	//  Version Register
+} AT91S_MATRIX, *AT91PS_MATRIX;
+#else
+#define MATRIX_MCFG0    (AT91_CAST(AT91_REG *) 	0x00000000) // (MATRIX_MCFG0)  Master Configuration Register 0 (ram96k)     
+#define MATRIX_MCFG1    (AT91_CAST(AT91_REG *) 	0x00000004) // (MATRIX_MCFG1)  Master Configuration Register 1 (rom)    
+#define MATRIX_MCFG2    (AT91_CAST(AT91_REG *) 	0x00000008) // (MATRIX_MCFG2)  Master Configuration Register 2 (hperiphs) 
+#define MATRIX_MCFG3    (AT91_CAST(AT91_REG *) 	0x0000000C) // (MATRIX_MCFG3)  Master Configuration Register 3 (ebi)
+#define MATRIX_MCFG4    (AT91_CAST(AT91_REG *) 	0x00000010) // (MATRIX_MCFG4)  Master Configuration Register 4 (bridge)    
+#define MATRIX_MCFG5    (AT91_CAST(AT91_REG *) 	0x00000014) // (MATRIX_MCFG5)  Master Configuration Register 5 (mailbox)    
+#define MATRIX_MCFG6    (AT91_CAST(AT91_REG *) 	0x00000018) // (MATRIX_MCFG6)  Master Configuration Register 6 (ram16k)  
+#define MATRIX_MCFG7    (AT91_CAST(AT91_REG *) 	0x0000001C) // (MATRIX_MCFG7)  Master Configuration Register 7 (teak_prog)     
+#define MATRIX_SCFG0    (AT91_CAST(AT91_REG *) 	0x00000040) // (MATRIX_SCFG0)  Slave Configuration Register 0 (ram96k)     
+#define MATRIX_SCFG1    (AT91_CAST(AT91_REG *) 	0x00000044) // (MATRIX_SCFG1)  Slave Configuration Register 1 (rom)    
+#define MATRIX_SCFG2    (AT91_CAST(AT91_REG *) 	0x00000048) // (MATRIX_SCFG2)  Slave Configuration Register 2 (hperiphs) 
+#define MATRIX_SCFG3    (AT91_CAST(AT91_REG *) 	0x0000004C) // (MATRIX_SCFG3)  Slave Configuration Register 3 (ebi)
+#define MATRIX_SCFG4    (AT91_CAST(AT91_REG *) 	0x00000050) // (MATRIX_SCFG4)  Slave Configuration Register 4 (bridge)    
+#define MATRIX_PRAS0    (AT91_CAST(AT91_REG *) 	0x00000080) // (MATRIX_PRAS0)  PRAS0 (ram0) 
+#define MATRIX_PRBS0    (AT91_CAST(AT91_REG *) 	0x00000084) // (MATRIX_PRBS0)  PRBS0 (ram0) 
+#define MATRIX_PRAS1    (AT91_CAST(AT91_REG *) 	0x00000088) // (MATRIX_PRAS1)  PRAS1 (ram1) 
+#define MATRIX_PRBS1    (AT91_CAST(AT91_REG *) 	0x0000008C) // (MATRIX_PRBS1)  PRBS1 (ram1) 
+#define MATRIX_PRAS2    (AT91_CAST(AT91_REG *) 	0x00000090) // (MATRIX_PRAS2)  PRAS2 (ram2) 
+#define MATRIX_PRBS2    (AT91_CAST(AT91_REG *) 	0x00000094) // (MATRIX_PRBS2)  PRBS2 (ram2) 
+#define MATRIX_PRAS3    (AT91_CAST(AT91_REG *) 	0x00000098) // (MATRIX_PRAS3)  PRAS3 : usb_dev_hs
+#define MATRIX_PRBS3    (AT91_CAST(AT91_REG *) 	0x0000009C) // (MATRIX_PRBS3)  PRBS3 : usb_dev_hs
+#define MATRIX_PRAS4    (AT91_CAST(AT91_REG *) 	0x000000A0) // (MATRIX_PRAS4)  PRAS4 : ebi
+#define MATRIX_PRBS4    (AT91_CAST(AT91_REG *) 	0x000000A4) // (MATRIX_PRBS4)  PRBS4 : ebi
+#define MATRIX_MRCR     (AT91_CAST(AT91_REG *) 	0x00000100) // (MATRIX_MRCR)  Master Remp Control Register 
+#define MATRIX_EBI      (AT91_CAST(AT91_REG *) 	0x0000011C) // (MATRIX_EBI)  Slave 3 (ebi) Special Function Register
+#define MATRIX_TEAKCFG  (AT91_CAST(AT91_REG *) 	0x0000012C) // (MATRIX_TEAKCFG)  Slave 7 (teak_prog) Special Function Register
+#define MATRIX_VERSION  (AT91_CAST(AT91_REG *) 	0x000001FC) // (MATRIX_VERSION)  Version Register
+
+#endif
+// -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 -------- 
+#define AT91C_MATRIX_SLOT_CYCLE (0xFF <<  0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst
+#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type
+#define 	AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR           (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
+#define 	AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR         (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
+#define 	AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR        (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
+#define AT91C_MATRIX_FIXED_DEFMSTR0 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3                (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_LCDC                 (0x3 << 18) // (MATRIX) LCDC Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_DMA                  (0x4 << 18) // (MATRIX) DMA Master is Default Master
+// -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 -------- 
+#define AT91C_MATRIX_FIXED_DEFMSTR1 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3                (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR1_LCDC                 (0x3 << 18) // (MATRIX) LCDC Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR1_DMA                  (0x4 << 18) // (MATRIX) DMA Master is Default Master
+// -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 -------- 
+#define AT91C_MATRIX_FIXED_DEFMSTR2 (0x1 << 18) // (MATRIX) Fixed Index of Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+// -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 -------- 
+#define AT91C_MATRIX_FIXED_DEFMSTR3 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3                (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR3_LCDC                 (0x3 << 18) // (MATRIX) LCDC Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR3_DMA                  (0x4 << 18) // (MATRIX) DMA Master is Default Master
+// -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 -------- 
+#define AT91C_MATRIX_FIXED_DEFMSTR4 (0x3 << 18) // (MATRIX) Fixed Index of Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3                (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
+// -------- MATRIX_PRAS0 : (MATRIX Offset: 0x80) PRAS0 Register -------- 
+#define AT91C_MATRIX_M0PR     (0x3 <<  0) // (MATRIX) ARM926EJ-S Instruction priority
+#define AT91C_MATRIX_M1PR     (0x3 <<  4) // (MATRIX) ARM926EJ-S Data priority
+#define AT91C_MATRIX_M2PR     (0x3 <<  8) // (MATRIX) PDC priority
+#define AT91C_MATRIX_M3PR     (0x3 << 12) // (MATRIX) LCDC priority
+#define AT91C_MATRIX_M4PR     (0x3 << 16) // (MATRIX) 2DGC priority
+#define AT91C_MATRIX_M5PR     (0x3 << 20) // (MATRIX) ISI priority
+#define AT91C_MATRIX_M6PR     (0x3 << 24) // (MATRIX) DMA priority
+#define AT91C_MATRIX_M7PR     (0x3 << 28) // (MATRIX) EMAC priority
+// -------- MATRIX_PRBS0 : (MATRIX Offset: 0x84) PRBS0 Register -------- 
+#define AT91C_MATRIX_M8PR     (0x3 <<  0) // (MATRIX) USB priority
+// -------- MATRIX_PRAS1 : (MATRIX Offset: 0x88) PRAS1 Register -------- 
+// -------- MATRIX_PRBS1 : (MATRIX Offset: 0x8c) PRBS1 Register -------- 
+// -------- MATRIX_PRAS2 : (MATRIX Offset: 0x90) PRAS2 Register -------- 
+// -------- MATRIX_PRBS2 : (MATRIX Offset: 0x94) PRBS2 Register -------- 
+// -------- MATRIX_PRAS3 : (MATRIX Offset: 0x98) PRAS3 Register -------- 
+// -------- MATRIX_PRBS3 : (MATRIX Offset: 0x9c) PRBS3 Register -------- 
+// -------- MATRIX_PRAS4 : (MATRIX Offset: 0xa0) PRAS4 Register -------- 
+// -------- MATRIX_PRBS4 : (MATRIX Offset: 0xa4) PRBS4 Register -------- 
+// -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register -------- 
+#define AT91C_MATRIX_RCA926I  (0x1 <<  0) // (MATRIX) Remap Command for ARM926EJ-S Instruction Master
+#define AT91C_MATRIX_RCA926D  (0x1 <<  1) // (MATRIX) Remap Command for ARM926EJ-S Data Master
+// -------- MATRIX_EBI : (MATRIX Offset: 0x11c) EBI (Slave 3) Special Function Register -------- 
+#define AT91C_MATRIX_CS1A     (0x1 <<  1) // (MATRIX) Chip Select 1 Assignment
+#define 	AT91C_MATRIX_CS1A_SMC                  (0x0 <<  1) // (MATRIX) Chip Select 1 is assigned to the Static Memory Controller.
+#define 	AT91C_MATRIX_CS1A_SDRAMC               (0x1 <<  1) // (MATRIX) Chip Select 1 is assigned to the SDRAM Controller.
+#define AT91C_MATRIX_CS3A     (0x1 <<  3) // (MATRIX) Chip Select 3 Assignment
+#define 	AT91C_MATRIX_CS3A_SMC                  (0x0 <<  3) // (MATRIX) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
+#define 	AT91C_MATRIX_CS3A_SM                   (0x1 <<  3) // (MATRIX) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
+#define AT91C_MATRIX_CS4A     (0x1 <<  4) // (MATRIX) Chip Select 4 Assignment
+#define 	AT91C_MATRIX_CS4A_SMC                  (0x0 <<  4) // (MATRIX) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
+#define 	AT91C_MATRIX_CS4A_CF                   (0x1 <<  4) // (MATRIX) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
+#define AT91C_MATRIX_CS5A     (0x1 <<  5) // (MATRIX) Chip Select 5 Assignment
+#define 	AT91C_MATRIX_CS5A_SMC                  (0x0 <<  5) // (MATRIX) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
+#define 	AT91C_MATRIX_CS5A_CF                   (0x1 <<  5) // (MATRIX) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
+#define AT91C_MATRIX_DBPUC    (0x1 <<  8) // (MATRIX) Data Bus Pull-up Configuration
+// -------- MATRIX_TEAKCFG : (MATRIX Offset: 0x12c) Slave 7 Special Function Register -------- 
+#define AT91C_TEAK_PROGRAM_ACCESS (0x1 <<  0) // (MATRIX) TEAK program memory access from AHB
+#define 	AT91C_TEAK_PROGRAM_ACCESS_DISABLED             (0x0) // (MATRIX) TEAK program access disabled
+#define 	AT91C_TEAK_PROGRAM_ACCESS_ENABLED              (0x1) // (MATRIX) TEAK program access enabled
+#define AT91C_TEAK_BOOT       (0x1 <<  1) // (MATRIX) TEAK program start from boot routine
+#define 	AT91C_TEAK_BOOT_DISABLED             (0x0 <<  1) // (MATRIX) TEAK program starts from boot routine disabled
+#define 	AT91C_TEAK_BOOT_ENABLED              (0x1 <<  1) // (MATRIX) TEAK program starts from boot routine enabled
+#define AT91C_TEAK_NRESET     (0x1 <<  2) // (MATRIX) active low TEAK reset
+#define 	AT91C_TEAK_NRESET_ENABLED              (0x0 <<  2) // (MATRIX) active low TEAK reset enabled
+#define 	AT91C_TEAK_NRESET_DISABLED             (0x1 <<  2) // (MATRIX) active low TEAK reset disabled
+#define AT91C_TEAK_LVECTORP   (0x3FFFF << 14) // (MATRIX) boot routine start address
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Chip Configuration Registers
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_CCFG {
+	AT91_REG	 Reserved0[3]; 	// 
+	AT91_REG	 CCFG_EBICSA; 	//  EBI Chip Select Assignement Register
+	AT91_REG	 Reserved1[55]; 	// 
+	AT91_REG	 CCFG_MATRIXVERSION; 	//  Version Register
+} AT91S_CCFG, *AT91PS_CCFG;
+#else
+#define CCFG_EBICSA     (AT91_CAST(AT91_REG *) 	0x0000000C) // (CCFG_EBICSA)  EBI Chip Select Assignement Register
+#define CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 	0x000000EC) // (CCFG_MATRIXVERSION)  Version Register
+
+#endif
+// -------- CCFG_EBICSA : (CCFG Offset: 0xc) EBI Chip Select Assignement Register -------- 
+#define AT91C_EBI_CS1A        (0x1 <<  1) // (CCFG) Chip Select 1 Assignment
+#define 	AT91C_EBI_CS1A_SMC                  (0x0 <<  1) // (CCFG) Chip Select 1 is assigned to the Static Memory Controller.
+#define 	AT91C_EBI_CS1A_SDRAMC               (0x1 <<  1) // (CCFG) Chip Select 1 is assigned to the SDRAM Controller.
+#define AT91C_EBI_CS3A        (0x1 <<  3) // (CCFG) Chip Select 3 Assignment
+#define 	AT91C_EBI_CS3A_SMC                  (0x0 <<  3) // (CCFG) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
+#define 	AT91C_EBI_CS3A_SM                   (0x1 <<  3) // (CCFG) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
+#define AT91C_EBI_CS4A        (0x1 <<  4) // (CCFG) Chip Select 4 Assignment
+#define 	AT91C_EBI_CS4A_SMC                  (0x0 <<  4) // (CCFG) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
+#define 	AT91C_EBI_CS4A_CF                   (0x1 <<  4) // (CCFG) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
+#define AT91C_EBI_CS5A        (0x1 <<  5) // (CCFG) Chip Select 5 Assignment
+#define 	AT91C_EBI_CS5A_SMC                  (0x0 <<  5) // (CCFG) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
+#define 	AT91C_EBI_CS5A_CF                   (0x1 <<  5) // (CCFG) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
+#define AT91C_EBI_DBPUC       (0x1 <<  8) // (CCFG) Data Bus Pull-up Configuration
+#define AT91C_EBI_SUPPLY      (0x1 << 16) // (CCFG) EBI supply selection
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PDC {
+	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
+	AT91_REG	 PDC_RCR; 	// Receive Counter Register
+	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
+	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+#else
+#define PDC_RPR         (AT91_CAST(AT91_REG *) 	0x00000000) // (PDC_RPR) Receive Pointer Register
+#define PDC_RCR         (AT91_CAST(AT91_REG *) 	0x00000004) // (PDC_RCR) Receive Counter Register
+#define PDC_TPR         (AT91_CAST(AT91_REG *) 	0x00000008) // (PDC_TPR) Transmit Pointer Register
+#define PDC_TCR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (PDC_TCR) Transmit Counter Register
+#define PDC_RNPR        (AT91_CAST(AT91_REG *) 	0x00000010) // (PDC_RNPR) Receive Next Pointer Register
+#define PDC_RNCR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PDC_RNCR) Receive Next Counter Register
+#define PDC_TNPR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
+#define PDC_TNCR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
+#define PDC_PTCR        (AT91_CAST(AT91_REG *) 	0x00000020) // (PDC_PTCR) PDC Transfer Control Register
+#define PDC_PTSR        (AT91_CAST(AT91_REG *) 	0x00000024) // (PDC_PTSR) PDC Transfer Status Register
+
+#endif
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN       (0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS      (0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN       (0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS      (0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_DBGU {
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved0[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved1[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+#else
+#define DBGU_CR         (AT91_CAST(AT91_REG *) 	0x00000000) // (DBGU_CR) Control Register
+#define DBGU_MR         (AT91_CAST(AT91_REG *) 	0x00000004) // (DBGU_MR) Mode Register
+#define DBGU_IER        (AT91_CAST(AT91_REG *) 	0x00000008) // (DBGU_IER) Interrupt Enable Register
+#define DBGU_IDR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (DBGU_IDR) Interrupt Disable Register
+#define DBGU_IMR        (AT91_CAST(AT91_REG *) 	0x00000010) // (DBGU_IMR) Interrupt Mask Register
+#define DBGU_CSR        (AT91_CAST(AT91_REG *) 	0x00000014) // (DBGU_CSR) Channel Status Register
+#define DBGU_RHR        (AT91_CAST(AT91_REG *) 	0x00000018) // (DBGU_RHR) Receiver Holding Register
+#define DBGU_THR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (DBGU_THR) Transmitter Holding Register
+#define DBGU_BRGR       (AT91_CAST(AT91_REG *) 	0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
+#define DBGU_CIDR       (AT91_CAST(AT91_REG *) 	0x00000040) // (DBGU_CIDR) Chip ID Register
+#define DBGU_EXID       (AT91_CAST(AT91_REG *) 	0x00000044) // (DBGU_EXID) Chip ID Extension Register
+#define DBGU_FNTR       (AT91_CAST(AT91_REG *) 	0x00000048) // (DBGU_FNTR) Force NTRST Register
+
+#endif
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX        (0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX        (0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN         (0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS        (0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN         (0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS        (0x1 <<  7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA       (0x1 <<  8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR          (0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE       (0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY        (0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY        (0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX        (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX        (0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE         (0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME        (0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE         (0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY      (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE       (0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF       (0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX      (0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX      (0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST  (0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_AIC {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+#else
+#define AIC_SMR         (AT91_CAST(AT91_REG *) 	0x00000000) // (AIC_SMR) Source Mode Register
+#define AIC_SVR         (AT91_CAST(AT91_REG *) 	0x00000080) // (AIC_SVR) Source Vector Register
+#define AIC_IVR         (AT91_CAST(AT91_REG *) 	0x00000100) // (AIC_IVR) IRQ Vector Register
+#define AIC_FVR         (AT91_CAST(AT91_REG *) 	0x00000104) // (AIC_FVR) FIQ Vector Register
+#define AIC_ISR         (AT91_CAST(AT91_REG *) 	0x00000108) // (AIC_ISR) Interrupt Status Register
+#define AIC_IPR         (AT91_CAST(AT91_REG *) 	0x0000010C) // (AIC_IPR) Interrupt Pending Register
+#define AIC_IMR         (AT91_CAST(AT91_REG *) 	0x00000110) // (AIC_IMR) Interrupt Mask Register
+#define AIC_CISR        (AT91_CAST(AT91_REG *) 	0x00000114) // (AIC_CISR) Core Interrupt Status Register
+#define AIC_IECR        (AT91_CAST(AT91_REG *) 	0x00000120) // (AIC_IECR) Interrupt Enable Command Register
+#define AIC_IDCR        (AT91_CAST(AT91_REG *) 	0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
+#define AIC_ICCR        (AT91_CAST(AT91_REG *) 	0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
+#define AIC_ISCR        (AT91_CAST(AT91_REG *) 	0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
+#define AIC_EOICR       (AT91_CAST(AT91_REG *) 	0x00000130) // (AIC_EOICR) End of Interrupt Command Register
+#define AIC_SPU         (AT91_CAST(AT91_REG *) 	0x00000134) // (AIC_SPU) Spurious Vector Register
+#define AIC_DCR         (AT91_CAST(AT91_REG *) 	0x00000138) // (AIC_DCR) Debug Control Register (Protect)
+#define AIC_FFER        (AT91_CAST(AT91_REG *) 	0x00000140) // (AIC_FFER) Fast Forcing Enable Register
+#define AIC_FFDR        (AT91_CAST(AT91_REG *) 	0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
+#define AIC_FFSR        (AT91_CAST(AT91_REG *) 	0x00000148) // (AIC_FFSR) Fast Forcing Status Register
+
+#endif
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR       (0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE     (0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  (0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   (0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       (0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    (0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ        (0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ        (0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT    (0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK    (0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PIO {
+	AT91_REG	 PIO_PER; 	// PIO Enable Register
+	AT91_REG	 PIO_PDR; 	// PIO Disable Register
+	AT91_REG	 PIO_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PIO_OER; 	// Output Enable Register
+	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIO_OSR; 	// Output Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PIO_SODR; 	// Set Output Data Register
+	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved3[1]; 	// 
+	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved4[1]; 	// 
+	AT91_REG	 PIO_ASR; 	// Select A Register
+	AT91_REG	 PIO_BSR; 	// Select B Register
+	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved5[9]; 	// 
+	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+#else
+#define PIO_PER         (AT91_CAST(AT91_REG *) 	0x00000000) // (PIO_PER) PIO Enable Register
+#define PIO_PDR         (AT91_CAST(AT91_REG *) 	0x00000004) // (PIO_PDR) PIO Disable Register
+#define PIO_PSR         (AT91_CAST(AT91_REG *) 	0x00000008) // (PIO_PSR) PIO Status Register
+#define PIO_OER         (AT91_CAST(AT91_REG *) 	0x00000010) // (PIO_OER) Output Enable Register
+#define PIO_ODR         (AT91_CAST(AT91_REG *) 	0x00000014) // (PIO_ODR) Output Disable Registerr
+#define PIO_OSR         (AT91_CAST(AT91_REG *) 	0x00000018) // (PIO_OSR) Output Status Register
+#define PIO_IFER        (AT91_CAST(AT91_REG *) 	0x00000020) // (PIO_IFER) Input Filter Enable Register
+#define PIO_IFDR        (AT91_CAST(AT91_REG *) 	0x00000024) // (PIO_IFDR) Input Filter Disable Register
+#define PIO_IFSR        (AT91_CAST(AT91_REG *) 	0x00000028) // (PIO_IFSR) Input Filter Status Register
+#define PIO_SODR        (AT91_CAST(AT91_REG *) 	0x00000030) // (PIO_SODR) Set Output Data Register
+#define PIO_CODR        (AT91_CAST(AT91_REG *) 	0x00000034) // (PIO_CODR) Clear Output Data Register
+#define PIO_ODSR        (AT91_CAST(AT91_REG *) 	0x00000038) // (PIO_ODSR) Output Data Status Register
+#define PIO_PDSR        (AT91_CAST(AT91_REG *) 	0x0000003C) // (PIO_PDSR) Pin Data Status Register
+#define PIO_IER         (AT91_CAST(AT91_REG *) 	0x00000040) // (PIO_IER) Interrupt Enable Register
+#define PIO_IDR         (AT91_CAST(AT91_REG *) 	0x00000044) // (PIO_IDR) Interrupt Disable Register
+#define PIO_IMR         (AT91_CAST(AT91_REG *) 	0x00000048) // (PIO_IMR) Interrupt Mask Register
+#define PIO_ISR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (PIO_ISR) Interrupt Status Register
+#define PIO_MDER        (AT91_CAST(AT91_REG *) 	0x00000050) // (PIO_MDER) Multi-driver Enable Register
+#define PIO_MDDR        (AT91_CAST(AT91_REG *) 	0x00000054) // (PIO_MDDR) Multi-driver Disable Register
+#define PIO_MDSR        (AT91_CAST(AT91_REG *) 	0x00000058) // (PIO_MDSR) Multi-driver Status Register
+#define PIO_PPUDR       (AT91_CAST(AT91_REG *) 	0x00000060) // (PIO_PPUDR) Pull-up Disable Register
+#define PIO_PPUER       (AT91_CAST(AT91_REG *) 	0x00000064) // (PIO_PPUER) Pull-up Enable Register
+#define PIO_PPUSR       (AT91_CAST(AT91_REG *) 	0x00000068) // (PIO_PPUSR) Pull-up Status Register
+#define PIO_ASR         (AT91_CAST(AT91_REG *) 	0x00000070) // (PIO_ASR) Select A Register
+#define PIO_BSR         (AT91_CAST(AT91_REG *) 	0x00000074) // (PIO_BSR) Select B Register
+#define PIO_ABSR        (AT91_CAST(AT91_REG *) 	0x00000078) // (PIO_ABSR) AB Select Status Register
+#define PIO_OWER        (AT91_CAST(AT91_REG *) 	0x000000A0) // (PIO_OWER) Output Write Enable Register
+#define PIO_OWDR        (AT91_CAST(AT91_REG *) 	0x000000A4) // (PIO_OWDR) Output Write Disable Register
+#define PIO_OWSR        (AT91_CAST(AT91_REG *) 	0x000000A8) // (PIO_OWSR) Output Write Status Register
+
+#endif
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Embedded Flash Controller 2.0
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_EFC {
+	AT91_REG	 EFC_FMR; 	// EFC Flash Mode Register
+	AT91_REG	 EFC_FCR; 	// EFC Flash Command Register
+	AT91_REG	 EFC_FSR; 	// EFC Flash Status Register
+	AT91_REG	 EFC_FRR; 	// EFC Flash Result Register
+	AT91_REG	 EFC_FVR; 	// EFC Flash Version Register
+} AT91S_EFC, *AT91PS_EFC;
+#else
+#define EFC_FMR         (AT91_CAST(AT91_REG *) 	0x00000000) // (EFC_FMR) EFC Flash Mode Register
+#define EFC_FCR         (AT91_CAST(AT91_REG *) 	0x00000004) // (EFC_FCR) EFC Flash Command Register
+#define EFC_FSR         (AT91_CAST(AT91_REG *) 	0x00000008) // (EFC_FSR) EFC Flash Status Register
+#define EFC_FRR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (EFC_FRR) EFC Flash Result Register
+#define EFC_FVR         (AT91_CAST(AT91_REG *) 	0x00000010) // (EFC_FVR) EFC Flash Version Register
+
+#endif
+// -------- EFC_FMR : (EFC Offset: 0x0) EFC Flash Mode Register -------- 
+#define AT91C_EFC_FRDY        (0x1 <<  0) // (EFC) Ready Interrupt Enable
+#define AT91C_EFC_FWS         (0xF <<  8) // (EFC) Flash Wait State.
+#define 	AT91C_EFC_FWS_0WS                  (0x0 <<  8) // (EFC) 0 Wait State
+#define 	AT91C_EFC_FWS_1WS                  (0x1 <<  8) // (EFC) 1 Wait State
+#define 	AT91C_EFC_FWS_2WS                  (0x2 <<  8) // (EFC) 2 Wait States
+#define 	AT91C_EFC_FWS_3WS                  (0x3 <<  8) // (EFC) 3 Wait States
+// -------- EFC_FCR : (EFC Offset: 0x4) EFC Flash Command Register -------- 
+#define AT91C_EFC_FCMD        (0xFF <<  0) // (EFC) Flash Command
+#define 	AT91C_EFC_FCMD_GETD                 (0x0) // (EFC) Get Flash Descriptor
+#define 	AT91C_EFC_FCMD_WP                   (0x1) // (EFC) Write Page
+#define 	AT91C_EFC_FCMD_WPL                  (0x2) // (EFC) Write Page and Lock
+#define 	AT91C_EFC_FCMD_EWP                  (0x3) // (EFC) Erase Page and Write Page
+#define 	AT91C_EFC_FCMD_EWPL                 (0x4) // (EFC) Erase Page and Write Page then Lock
+#define 	AT91C_EFC_FCMD_EA                   (0x5) // (EFC) Erase All
+#define 	AT91C_EFC_FCMD_EPL                  (0x6) // (EFC) Erase Plane
+#define 	AT91C_EFC_FCMD_EPA                  (0x7) // (EFC) Erase Pages
+#define 	AT91C_EFC_FCMD_SLB                  (0x8) // (EFC) Set Lock Bit
+#define 	AT91C_EFC_FCMD_CLB                  (0x9) // (EFC) Clear Lock Bit
+#define 	AT91C_EFC_FCMD_GLB                  (0xA) // (EFC) Get Lock Bit
+#define 	AT91C_EFC_FCMD_SFB                  (0xB) // (EFC) Set Fuse Bit
+#define 	AT91C_EFC_FCMD_CFB                  (0xC) // (EFC) Clear Fuse Bit
+#define 	AT91C_EFC_FCMD_GFB                  (0xD) // (EFC) Get Fuse Bit
+#define AT91C_EFC_FARG        (0xFFFF <<  8) // (EFC) Flash Command Argument
+#define AT91C_EFC_FKEY        (0xFF << 24) // (EFC) Flash Writing Protection Key
+// -------- EFC_FSR : (EFC Offset: 0x8) EFC Flash Status Register -------- 
+#define AT91C_EFC_FRDY_S      (0x1 <<  0) // (EFC) Flash Ready Status
+#define AT91C_EFC_FCMDE       (0x1 <<  1) // (EFC) Flash Command Error Status
+#define AT91C_EFC_LOCKE       (0x1 <<  2) // (EFC) Flash Lock Error Status
+// -------- EFC_FRR : (EFC Offset: 0xc) EFC Flash Result Register -------- 
+#define AT91C_EFC_FVALUE      (0x0 <<  0) // (EFC) Flash Result Value
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_CKGR {
+	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
+	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 CKGR_PLLAR; 	// PLL A Register
+	AT91_REG	 CKGR_PLLBR; 	// PLL B Register
+} AT91S_CKGR, *AT91PS_CKGR;
+#else
+#define CKGR_MOR        (AT91_CAST(AT91_REG *) 	0x00000000) // (CKGR_MOR) Main Oscillator Register
+#define CKGR_MCFR       (AT91_CAST(AT91_REG *) 	0x00000004) // (CKGR_MCFR) Main Clock  Frequency Register
+#define CKGR_PLLAR      (AT91_CAST(AT91_REG *) 	0x00000008) // (CKGR_PLLAR) PLL A Register
+#define CKGR_PLLBR      (AT91_CAST(AT91_REG *) 	0x0000000C) // (CKGR_PLLBR) PLL B Register
+
+#endif
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN     (0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS  (0x1 <<  1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT    (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF      (0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY    (0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- 
+#define AT91C_CKGR_DIVA       (0xFF <<  0) // (CKGR) Divider A Selected
+#define 	AT91C_CKGR_DIVA_0                    (0x0) // (CKGR) Divider A output is 0
+#define 	AT91C_CKGR_DIVA_BYPASS               (0x1) // (CKGR) Divider A is bypassed
+#define AT91C_CKGR_PLLACOUNT  (0x3F <<  8) // (CKGR) PLL A Counter
+#define AT91C_CKGR_OUTA       (0x3 << 14) // (CKGR) PLL A Output Frequency Range
+#define 	AT91C_CKGR_OUTA_0                    (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define 	AT91C_CKGR_OUTA_1                    (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define 	AT91C_CKGR_OUTA_2                    (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define 	AT91C_CKGR_OUTA_3                    (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define AT91C_CKGR_MULA       (0x7FF << 16) // (CKGR) PLL A Multiplier
+#define AT91C_CKGR_SRCA       (0x1 << 29) // (CKGR) 
+// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- 
+#define AT91C_CKGR_DIVB       (0xFF <<  0) // (CKGR) Divider B Selected
+#define 	AT91C_CKGR_DIVB_0                    (0x0) // (CKGR) Divider B output is 0
+#define 	AT91C_CKGR_DIVB_BYPASS               (0x1) // (CKGR) Divider B is bypassed
+#define AT91C_CKGR_PLLBCOUNT  (0x3F <<  8) // (CKGR) PLL B Counter
+#define AT91C_CKGR_OUTB       (0x3 << 14) // (CKGR) PLL B Output Frequency Range
+#define 	AT91C_CKGR_OUTB_0                    (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define 	AT91C_CKGR_OUTB_1                    (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define 	AT91C_CKGR_OUTB_2                    (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define 	AT91C_CKGR_OUTB_3                    (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define AT91C_CKGR_MULB       (0x7FF << 16) // (CKGR) PLL B Multiplier
+#define AT91C_CKGR_USBDIV     (0x3 << 28) // (CKGR) Divider for USB Clocks
+#define 	AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define 	AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define 	AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PMC {
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 PMC_PLLAR; 	// PLL A Register
+	AT91_REG	 PMC_PLLBR; 	// PLL B Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved2[3]; 	// 
+	AT91_REG	 PMC_PCKR[8]; 	// Programmable Clock Register
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+#else
+#define PMC_SCER        (AT91_CAST(AT91_REG *) 	0x00000000) // (PMC_SCER) System Clock Enable Register
+#define PMC_SCDR        (AT91_CAST(AT91_REG *) 	0x00000004) // (PMC_SCDR) System Clock Disable Register
+#define PMC_SCSR        (AT91_CAST(AT91_REG *) 	0x00000008) // (PMC_SCSR) System Clock Status Register
+#define PMC_PCER        (AT91_CAST(AT91_REG *) 	0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
+#define PMC_PCDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
+#define PMC_PCSR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
+#define PMC_MCKR        (AT91_CAST(AT91_REG *) 	0x00000030) // (PMC_MCKR) Master Clock Register
+#define PMC_PCKR        (AT91_CAST(AT91_REG *) 	0x00000040) // (PMC_PCKR) Programmable Clock Register
+#define PMC_IER         (AT91_CAST(AT91_REG *) 	0x00000060) // (PMC_IER) Interrupt Enable Register
+#define PMC_IDR         (AT91_CAST(AT91_REG *) 	0x00000064) // (PMC_IDR) Interrupt Disable Register
+#define PMC_SR          (AT91_CAST(AT91_REG *) 	0x00000068) // (PMC_SR) Status Register
+#define PMC_IMR         (AT91_CAST(AT91_REG *) 	0x0000006C) // (PMC_IMR) Interrupt Mask Register
+
+#endif
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_PCK         (0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_OTG         (0x1 <<  5) // (PMC) USB OTG Clock
+#define AT91C_PMC_UHP         (0x1 <<  6) // (PMC) USB Host Port Clock
+#define AT91C_PMC_UDP         (0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0        (0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1        (0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2        (0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3        (0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- 
+// -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register -------- 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS         (0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLLA_CLK             (0x2) // (PMC) Clock from PLL A is selected
+#define 	AT91C_PMC_CSS_PLLB_CLK             (0x3) // (PMC) Clock from PLL B is selected
+#define AT91C_PMC_PRES        (0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
+#define AT91C_PMC_MDIV        (0x3 <<  8) // (PMC) Master Clock Division
+#define 	AT91C_PMC_MDIV_1                    (0x0 <<  8) // (PMC) The master clock and the processor clock are the same
+#define 	AT91C_PMC_MDIV_2                    (0x1 <<  8) // (PMC) The processor clock is twice as fast as the master clock
+#define 	AT91C_PMC_MDIV_3                    (0x2 <<  8) // (PMC) The processor clock is four times faster than the master clock
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS       (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCKA       (0x1 <<  1) // (PMC) PLL A Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCKB       (0x1 <<  2) // (PMC) PLL B Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY      (0x1 <<  3) // (PMC) Master Clock Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY     (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY     (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY     (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY     (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_RSTC {
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
+#else
+#define RSTC_RCR        (AT91_CAST(AT91_REG *) 	0x00000000) // (RSTC_RCR) Reset Control Register
+#define RSTC_RSR        (AT91_CAST(AT91_REG *) 	0x00000004) // (RSTC_RSR) Reset Status Register
+#define RSTC_RMR        (AT91_CAST(AT91_REG *) 	0x00000008) // (RSTC_RMR) Reset Mode Register
+
+#endif
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_RSTC_PROCRST    (0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_RSTC_ICERST     (0x1 <<  1) // (RSTC) ICE Interface Reset
+#define AT91C_RSTC_PERRST     (0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST     (0x1 <<  3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY        (0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_RSTC_URSTS      (0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_RSTC_RSTTYP     (0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_RSTC_RSTTYP_GENERAL              (0x0 <<  8) // (RSTC) General reset. Both VDDCORE and VDDBU rising.
+#define 	AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define AT91C_RSTC_NRSTL      (0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP      (0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_RSTC_URSTEN     (0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN    (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL      (0xF <<  8) // (RSTC) User Reset Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Shut Down Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SHDWC {
+	AT91_REG	 SHDWC_SHCR; 	// Shut Down Control Register
+	AT91_REG	 SHDWC_SHMR; 	// Shut Down Mode Register
+	AT91_REG	 SHDWC_SHSR; 	// Shut Down Status Register
+} AT91S_SHDWC, *AT91PS_SHDWC;
+#else
+#define SHDWC_SHCR      (AT91_CAST(AT91_REG *) 	0x00000000) // (SHDWC_SHCR) Shut Down Control Register
+#define SHDWC_SHMR      (AT91_CAST(AT91_REG *) 	0x00000004) // (SHDWC_SHMR) Shut Down Mode Register
+#define SHDWC_SHSR      (AT91_CAST(AT91_REG *) 	0x00000008) // (SHDWC_SHSR) Shut Down Status Register
+
+#endif
+// -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register -------- 
+#define AT91C_SHDWC_SHDW      (0x1 <<  0) // (SHDWC) Processor Reset
+#define AT91C_SHDWC_KEY       (0xFF << 24) // (SHDWC) Shut down KEY Password
+// -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register -------- 
+#define AT91C_SHDWC_WKMODE0   (0x3 <<  0) // (SHDWC) Wake Up 0 Mode Selection
+#define 	AT91C_SHDWC_WKMODE0_NONE                 (0x0) // (SHDWC) None. No detection is performed on the wake up input.
+#define 	AT91C_SHDWC_WKMODE0_HIGH                 (0x1) // (SHDWC) High Level.
+#define 	AT91C_SHDWC_WKMODE0_LOW                  (0x2) // (SHDWC) Low Level.
+#define 	AT91C_SHDWC_WKMODE0_ANYLEVEL             (0x3) // (SHDWC) Any level change.
+#define AT91C_SHDWC_CPTWK0    (0xF <<  4) // (SHDWC) Counter On Wake Up 0
+#define AT91C_SHDWC_WKMODE1   (0x3 <<  8) // (SHDWC) Wake Up 1 Mode Selection
+#define 	AT91C_SHDWC_WKMODE1_NONE                 (0x0 <<  8) // (SHDWC) None. No detection is performed on the wake up input.
+#define 	AT91C_SHDWC_WKMODE1_HIGH                 (0x1 <<  8) // (SHDWC) High Level.
+#define 	AT91C_SHDWC_WKMODE1_LOW                  (0x2 <<  8) // (SHDWC) Low Level.
+#define 	AT91C_SHDWC_WKMODE1_ANYLEVEL             (0x3 <<  8) // (SHDWC) Any level change.
+#define AT91C_SHDWC_CPTWK1    (0xF << 12) // (SHDWC) Counter On Wake Up 1
+#define AT91C_SHDWC_RTTWKEN   (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable
+#define AT91C_SHDWC_RTCWKEN   (0x1 << 17) // (SHDWC) Real Time Clock Wake Up Enable
+// -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register -------- 
+#define AT91C_SHDWC_WAKEUP0   (0x1 <<  0) // (SHDWC) Wake Up 0 Status
+#define AT91C_SHDWC_WAKEUP1   (0x1 <<  1) // (SHDWC) Wake Up 1 Status
+#define AT91C_SHDWC_FWKUP     (0x1 <<  2) // (SHDWC) Force Wake Up Status
+#define AT91C_SHDWC_RTTWK     (0x1 << 16) // (SHDWC) Real Time Timer wake Up
+#define AT91C_SHDWC_RTCWK     (0x1 << 17) // (SHDWC) Real Time Clock wake Up
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_RTTC {
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+#else
+#define RTTC_RTMR       (AT91_CAST(AT91_REG *) 	0x00000000) // (RTTC_RTMR) Real-time Mode Register
+#define RTTC_RTAR       (AT91_CAST(AT91_REG *) 	0x00000004) // (RTTC_RTAR) Real-time Alarm Register
+#define RTTC_RTVR       (AT91_CAST(AT91_REG *) 	0x00000008) // (RTTC_RTVR) Real-time Value Register
+#define RTTC_RTSR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (RTTC_RTSR) Real-time Status Register
+
+#endif
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_RTTC_RTPRES     (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN     (0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN  (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST     (0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_RTTC_ALMV       (0x0 <<  0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_RTTC_CRTV       (0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_RTTC_ALMS       (0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC     (0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PITC {
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+#else
+#define PITC_PIMR       (AT91_CAST(AT91_REG *) 	0x00000000) // (PITC_PIMR) Period Interval Mode Register
+#define PITC_PISR       (AT91_CAST(AT91_REG *) 	0x00000004) // (PITC_PISR) Period Interval Status Register
+#define PITC_PIVR       (AT91_CAST(AT91_REG *) 	0x00000008) // (PITC_PIVR) Period Interval Value Register
+#define PITC_PIIR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (PITC_PIIR) Period Interval Image Register
+
+#endif
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_PITC_PIV        (0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN      (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN     (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_PITC_PITS       (0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_PITC_CPIV       (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT      (0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_WDTC {
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+#else
+#define WDTC_WDCR       (AT91_CAST(AT91_REG *) 	0x00000000) // (WDTC_WDCR) Watchdog Control Register
+#define WDTC_WDMR       (AT91_CAST(AT91_REG *) 	0x00000004) // (WDTC_WDMR) Watchdog Mode Register
+#define WDTC_WDSR       (AT91_CAST(AT91_REG *) 	0x00000008) // (WDTC_WDSR) Watchdog Status Register
+
+#endif
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_WDTC_WDRSTT     (0x1 <<  0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY        (0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_WDTC_WDV        (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN     (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN    (0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC    (0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS      (0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD        (0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT   (0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT  (0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_WDTC_WDUNF      (0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR      (0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_TC {
+	AT91_REG	 TC_CCR; 	// Channel Control Register
+	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TC_CV; 	// Counter Value
+	AT91_REG	 TC_RA; 	// Register A
+	AT91_REG	 TC_RB; 	// Register B
+	AT91_REG	 TC_RC; 	// Register C
+	AT91_REG	 TC_SR; 	// Status Register
+	AT91_REG	 TC_IER; 	// Interrupt Enable Register
+	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+#else
+#define TC_CCR          (AT91_CAST(AT91_REG *) 	0x00000000) // (TC_CCR) Channel Control Register
+#define TC_CMR          (AT91_CAST(AT91_REG *) 	0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
+#define TC_CV           (AT91_CAST(AT91_REG *) 	0x00000010) // (TC_CV) Counter Value
+#define TC_RA           (AT91_CAST(AT91_REG *) 	0x00000014) // (TC_RA) Register A
+#define TC_RB           (AT91_CAST(AT91_REG *) 	0x00000018) // (TC_RB) Register B
+#define TC_RC           (AT91_CAST(AT91_REG *) 	0x0000001C) // (TC_RC) Register C
+#define TC_SR           (AT91_CAST(AT91_REG *) 	0x00000020) // (TC_SR) Status Register
+#define TC_IER          (AT91_CAST(AT91_REG *) 	0x00000024) // (TC_IER) Interrupt Enable Register
+#define TC_IDR          (AT91_CAST(AT91_REG *) 	0x00000028) // (TC_IDR) Interrupt Disable Register
+#define TC_IMR          (AT91_CAST(AT91_REG *) 	0x0000002C) // (TC_IMR) Interrupt Mask Register
+
+#endif
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN        (0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS       (0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG        (0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS         (0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI         (0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST        (0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS       (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS       (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG      (0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG      (0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT         (0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG       (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG       (0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL      (0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG       (0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE         (0x1 << 15) // (TC) 
+#define AT91C_TC_ACPA         (0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA         (0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC         (0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB         (0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT        (0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG       (0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB         (0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC         (0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT        (0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG       (0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS        (0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS        (0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS         (0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS         (0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS         (0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS        (0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS        (0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRGS        (0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA       (0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA        (0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB        (0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_TCB {
+	AT91S_TC	 TCB_TC0; 	// TC Channel 0
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91S_TC	 TCB_TC1; 	// TC Channel 1
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91S_TC	 TCB_TC2; 	// TC Channel 2
+	AT91_REG	 Reserved2[4]; 	// 
+	AT91_REG	 TCB_BCR; 	// TC Block Control Register
+	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+#else
+#define TCB_BCR         (AT91_CAST(AT91_REG *) 	0x000000C0) // (TCB_BCR) TC Block Control Register
+#define TCB_BMR         (AT91_CAST(AT91_REG *) 	0x000000C4) // (TCB_BMR) TC Block Mode Register
+
+#endif
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC        (0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S     (0x3 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S     (0x3 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S     (0x3 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Multimedia Card Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_MCI {
+	AT91_REG	 MCI_CR; 	// MCI Control Register
+	AT91_REG	 MCI_MR; 	// MCI Mode Register
+	AT91_REG	 MCI_DTOR; 	// MCI Data Timeout Register
+	AT91_REG	 MCI_SDCR; 	// MCI SD Card Register
+	AT91_REG	 MCI_ARGR; 	// MCI Argument Register
+	AT91_REG	 MCI_CMDR; 	// MCI Command Register
+	AT91_REG	 MCI_BLKR; 	// MCI Block Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 MCI_RSPR[4]; 	// MCI Response Register
+	AT91_REG	 MCI_RDR; 	// MCI Receive Data Register
+	AT91_REG	 MCI_TDR; 	// MCI Transmit Data Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 MCI_SR; 	// MCI Status Register
+	AT91_REG	 MCI_IER; 	// MCI Interrupt Enable Register
+	AT91_REG	 MCI_IDR; 	// MCI Interrupt Disable Register
+	AT91_REG	 MCI_IMR; 	// MCI Interrupt Mask Register
+	AT91_REG	 Reserved2[43]; 	// 
+	AT91_REG	 MCI_VR; 	// MCI Version Register
+	AT91_REG	 MCI_RPR; 	// Receive Pointer Register
+	AT91_REG	 MCI_RCR; 	// Receive Counter Register
+	AT91_REG	 MCI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 MCI_TCR; 	// Transmit Counter Register
+	AT91_REG	 MCI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 MCI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 MCI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 MCI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 MCI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 MCI_PTSR; 	// PDC Transfer Status Register
+} AT91S_MCI, *AT91PS_MCI;
+#else
+#define MCI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (MCI_CR) MCI Control Register
+#define MCI_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (MCI_MR) MCI Mode Register
+#define MCI_DTOR        (AT91_CAST(AT91_REG *) 	0x00000008) // (MCI_DTOR) MCI Data Timeout Register
+#define MCI_SDCR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (MCI_SDCR) MCI SD Card Register
+#define MCI_ARGR        (AT91_CAST(AT91_REG *) 	0x00000010) // (MCI_ARGR) MCI Argument Register
+#define MCI_CMDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (MCI_CMDR) MCI Command Register
+#define MCI_BLKR        (AT91_CAST(AT91_REG *) 	0x00000018) // (MCI_BLKR) MCI Block Register
+#define MCI_RSPR        (AT91_CAST(AT91_REG *) 	0x00000020) // (MCI_RSPR) MCI Response Register
+#define MCI_RDR         (AT91_CAST(AT91_REG *) 	0x00000030) // (MCI_RDR) MCI Receive Data Register
+#define MCI_TDR         (AT91_CAST(AT91_REG *) 	0x00000034) // (MCI_TDR) MCI Transmit Data Register
+#define MCI_SR          (AT91_CAST(AT91_REG *) 	0x00000040) // (MCI_SR) MCI Status Register
+#define MCI_IER         (AT91_CAST(AT91_REG *) 	0x00000044) // (MCI_IER) MCI Interrupt Enable Register
+#define MCI_IDR         (AT91_CAST(AT91_REG *) 	0x00000048) // (MCI_IDR) MCI Interrupt Disable Register
+#define MCI_IMR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (MCI_IMR) MCI Interrupt Mask Register
+#define MCI_VR          (AT91_CAST(AT91_REG *) 	0x000000FC) // (MCI_VR) MCI Version Register
+
+#endif
+// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- 
+#define AT91C_MCI_MCIEN       (0x1 <<  0) // (MCI) Multimedia Interface Enable
+#define AT91C_MCI_MCIDIS      (0x1 <<  1) // (MCI) Multimedia Interface Disable
+#define AT91C_MCI_PWSEN       (0x1 <<  2) // (MCI) Power Save Mode Enable
+#define AT91C_MCI_PWSDIS      (0x1 <<  3) // (MCI) Power Save Mode Disable
+#define AT91C_MCI_SWRST       (0x1 <<  7) // (MCI) MCI Software reset
+// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- 
+#define AT91C_MCI_CLKDIV      (0xFF <<  0) // (MCI) Clock Divider
+#define AT91C_MCI_PWSDIV      (0x7 <<  8) // (MCI) Power Saving Divider
+#define AT91C_MCI_RDPROOF     (0x1 << 11) // (MCI) Read Proof Enable
+#define AT91C_MCI_WRPROOF     (0x1 << 12) // (MCI) Write Proof Enable
+#define AT91C_MCI_PDCFBYTE    (0x1 << 13) // (MCI) PDC Force Byte Transfer
+#define AT91C_MCI_PDCPADV     (0x1 << 14) // (MCI) PDC Padding Value
+#define AT91C_MCI_PDCMODE     (0x1 << 15) // (MCI) PDC Oriented Mode
+#define AT91C_MCI_BLKLEN      (0xFFFF << 16) // (MCI) Data Block Length
+// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- 
+#define AT91C_MCI_DTOCYC      (0xF <<  0) // (MCI) Data Timeout Cycle Number
+#define AT91C_MCI_DTOMUL      (0x7 <<  4) // (MCI) Data Timeout Multiplier
+#define 	AT91C_MCI_DTOMUL_1                    (0x0 <<  4) // (MCI) DTOCYC x 1
+#define 	AT91C_MCI_DTOMUL_16                   (0x1 <<  4) // (MCI) DTOCYC x 16
+#define 	AT91C_MCI_DTOMUL_128                  (0x2 <<  4) // (MCI) DTOCYC x 128
+#define 	AT91C_MCI_DTOMUL_256                  (0x3 <<  4) // (MCI) DTOCYC x 256
+#define 	AT91C_MCI_DTOMUL_1024                 (0x4 <<  4) // (MCI) DTOCYC x 1024
+#define 	AT91C_MCI_DTOMUL_4096                 (0x5 <<  4) // (MCI) DTOCYC x 4096
+#define 	AT91C_MCI_DTOMUL_65536                (0x6 <<  4) // (MCI) DTOCYC x 65536
+#define 	AT91C_MCI_DTOMUL_1048576              (0x7 <<  4) // (MCI) DTOCYC x 1048576
+// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- 
+#define AT91C_MCI_SCDSEL      (0x3 <<  0) // (MCI) SD Card Selector
+#define AT91C_MCI_SCDBUS      (0x1 <<  7) // (MCI) SDCard/SDIO Bus Width
+// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- 
+#define AT91C_MCI_CMDNB       (0x3F <<  0) // (MCI) Command Number
+#define AT91C_MCI_RSPTYP      (0x3 <<  6) // (MCI) Response Type
+#define 	AT91C_MCI_RSPTYP_NO                   (0x0 <<  6) // (MCI) No response
+#define 	AT91C_MCI_RSPTYP_48                   (0x1 <<  6) // (MCI) 48-bit response
+#define 	AT91C_MCI_RSPTYP_136                  (0x2 <<  6) // (MCI) 136-bit response
+#define AT91C_MCI_SPCMD       (0x7 <<  8) // (MCI) Special CMD
+#define 	AT91C_MCI_SPCMD_NONE                 (0x0 <<  8) // (MCI) Not a special CMD
+#define 	AT91C_MCI_SPCMD_INIT                 (0x1 <<  8) // (MCI) Initialization CMD
+#define 	AT91C_MCI_SPCMD_SYNC                 (0x2 <<  8) // (MCI) Synchronized CMD
+#define 	AT91C_MCI_SPCMD_IT_CMD               (0x4 <<  8) // (MCI) Interrupt command
+#define 	AT91C_MCI_SPCMD_IT_REP               (0x5 <<  8) // (MCI) Interrupt response
+#define AT91C_MCI_OPDCMD      (0x1 << 11) // (MCI) Open Drain Command
+#define AT91C_MCI_MAXLAT      (0x1 << 12) // (MCI) Maximum Latency for Command to respond
+#define AT91C_MCI_TRCMD       (0x3 << 16) // (MCI) Transfer CMD
+#define 	AT91C_MCI_TRCMD_NO                   (0x0 << 16) // (MCI) No transfer
+#define 	AT91C_MCI_TRCMD_START                (0x1 << 16) // (MCI) Start transfer
+#define 	AT91C_MCI_TRCMD_STOP                 (0x2 << 16) // (MCI) Stop transfer
+#define AT91C_MCI_TRDIR       (0x1 << 18) // (MCI) Transfer Direction
+#define AT91C_MCI_TRTYP       (0x7 << 19) // (MCI) Transfer Type
+#define 	AT91C_MCI_TRTYP_BLOCK                (0x0 << 19) // (MCI) MMC/SDCard Single Block Transfer type
+#define 	AT91C_MCI_TRTYP_MULTIPLE             (0x1 << 19) // (MCI) MMC/SDCard Multiple Block transfer type
+#define 	AT91C_MCI_TRTYP_STREAM               (0x2 << 19) // (MCI) MMC Stream transfer type
+#define 	AT91C_MCI_TRTYP_SDIO_BYTE            (0x4 << 19) // (MCI) SDIO Byte transfer type
+#define 	AT91C_MCI_TRTYP_SDIO_BLOCK           (0x5 << 19) // (MCI) SDIO Block transfer type
+#define AT91C_MCI_IOSPCMD     (0x3 << 24) // (MCI) SDIO Special Command
+#define 	AT91C_MCI_IOSPCMD_NONE                 (0x0 << 24) // (MCI) NOT a special command
+#define 	AT91C_MCI_IOSPCMD_SUSPEND              (0x1 << 24) // (MCI) SDIO Suspend Command
+#define 	AT91C_MCI_IOSPCMD_RESUME               (0x2 << 24) // (MCI) SDIO Resume Command
+// -------- MCI_BLKR : (MCI Offset: 0x18) MCI Block Register -------- 
+#define AT91C_MCI_BCNT        (0xFFFF <<  0) // (MCI) MMC/SDIO Block Count / SDIO Byte Count
+// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- 
+#define AT91C_MCI_CMDRDY      (0x1 <<  0) // (MCI) Command Ready flag
+#define AT91C_MCI_RXRDY       (0x1 <<  1) // (MCI) RX Ready flag
+#define AT91C_MCI_TXRDY       (0x1 <<  2) // (MCI) TX Ready flag
+#define AT91C_MCI_BLKE        (0x1 <<  3) // (MCI) Data Block Transfer Ended flag
+#define AT91C_MCI_DTIP        (0x1 <<  4) // (MCI) Data Transfer in Progress flag
+#define AT91C_MCI_NOTBUSY     (0x1 <<  5) // (MCI) Data Line Not Busy flag
+#define AT91C_MCI_ENDRX       (0x1 <<  6) // (MCI) End of RX Buffer flag
+#define AT91C_MCI_ENDTX       (0x1 <<  7) // (MCI) End of TX Buffer flag
+#define AT91C_MCI_SDIOIRQA    (0x1 <<  8) // (MCI) SDIO Interrupt for Slot A
+#define AT91C_MCI_SDIOIRQB    (0x1 <<  9) // (MCI) SDIO Interrupt for Slot B
+#define AT91C_MCI_SDIOIRQC    (0x1 << 10) // (MCI) SDIO Interrupt for Slot C
+#define AT91C_MCI_SDIOIRQD    (0x1 << 11) // (MCI) SDIO Interrupt for Slot D
+#define AT91C_MCI_RXBUFF      (0x1 << 14) // (MCI) RX Buffer Full flag
+#define AT91C_MCI_TXBUFE      (0x1 << 15) // (MCI) TX Buffer Empty flag
+#define AT91C_MCI_RINDE       (0x1 << 16) // (MCI) Response Index Error flag
+#define AT91C_MCI_RDIRE       (0x1 << 17) // (MCI) Response Direction Error flag
+#define AT91C_MCI_RCRCE       (0x1 << 18) // (MCI) Response CRC Error flag
+#define AT91C_MCI_RENDE       (0x1 << 19) // (MCI) Response End Bit Error flag
+#define AT91C_MCI_RTOE        (0x1 << 20) // (MCI) Response Time-out Error flag
+#define AT91C_MCI_DCRCE       (0x1 << 21) // (MCI) data CRC Error flag
+#define AT91C_MCI_DTOE        (0x1 << 22) // (MCI) Data timeout Error flag
+#define AT91C_MCI_OVRE        (0x1 << 30) // (MCI) Overrun flag
+#define AT91C_MCI_UNRE        (0x1 << 31) // (MCI) Underrun flag
+// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- 
+// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- 
+// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_TWI {
+	AT91_REG	 TWI_CR; 	// Control Register
+	AT91_REG	 TWI_MMR; 	// Master Mode Register
+	AT91_REG	 TWI_SMR; 	// Slave Mode Register
+	AT91_REG	 TWI_IADR; 	// Internal Address Register
+	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
+	AT91_REG	 Reserved0[3]; 	// 
+	AT91_REG	 TWI_SR; 	// Status Register
+	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
+	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TWI_RHR; 	// Receive Holding Register
+	AT91_REG	 TWI_THR; 	// Transmit Holding Register
+	AT91_REG	 Reserved1[50]; 	// 
+	AT91_REG	 TWI_RPR; 	// Receive Pointer Register
+	AT91_REG	 TWI_RCR; 	// Receive Counter Register
+	AT91_REG	 TWI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 TWI_TCR; 	// Transmit Counter Register
+	AT91_REG	 TWI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 TWI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 TWI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 TWI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 TWI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 TWI_PTSR; 	// PDC Transfer Status Register
+} AT91S_TWI, *AT91PS_TWI;
+#else
+#define TWI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (TWI_CR) Control Register
+#define TWI_MMR         (AT91_CAST(AT91_REG *) 	0x00000004) // (TWI_MMR) Master Mode Register
+#define TWI_SMR         (AT91_CAST(AT91_REG *) 	0x00000008) // (TWI_SMR) Slave Mode Register
+#define TWI_IADR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (TWI_IADR) Internal Address Register
+#define TWI_CWGR        (AT91_CAST(AT91_REG *) 	0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
+#define TWI_SR          (AT91_CAST(AT91_REG *) 	0x00000020) // (TWI_SR) Status Register
+#define TWI_IER         (AT91_CAST(AT91_REG *) 	0x00000024) // (TWI_IER) Interrupt Enable Register
+#define TWI_IDR         (AT91_CAST(AT91_REG *) 	0x00000028) // (TWI_IDR) Interrupt Disable Register
+#define TWI_IMR         (AT91_CAST(AT91_REG *) 	0x0000002C) // (TWI_IMR) Interrupt Mask Register
+#define TWI_RHR         (AT91_CAST(AT91_REG *) 	0x00000030) // (TWI_RHR) Receive Holding Register
+#define TWI_THR         (AT91_CAST(AT91_REG *) 	0x00000034) // (TWI_THR) Transmit Holding Register
+
+#endif
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START       (0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP        (0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN        (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS       (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SVEN        (0x1 <<  4) // (TWI) TWI Slave mode Enabled
+#define AT91C_TWI_SVDIS       (0x1 <<  5) // (TWI) TWI Slave mode Disabled
+#define AT91C_TWI_SWRST       (0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ      (0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD       (0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR        (0x7F << 16) // (TWI) Device Address
+// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- 
+#define AT91C_TWI_SADR        (0x7F << 16) // (TWI) Slave Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV       (0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV       (0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV       (0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP_SLAVE (0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_TXCOMP_MASTER (0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY       (0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY_MASTER (0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_TXRDY_SLAVE (0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_SVREAD      (0x1 <<  3) // (TWI) Slave READ (used only in Slave mode)
+#define AT91C_TWI_SVACC       (0x1 <<  4) // (TWI) Slave ACCess (used only in Slave mode)
+#define AT91C_TWI_GACC        (0x1 <<  5) // (TWI) General Call ACcess (used only in Slave mode)
+#define AT91C_TWI_OVRE        (0x1 <<  6) // (TWI) Overrun Error (used only in Master and Multi-master mode)
+#define AT91C_TWI_NACK_SLAVE  (0x1 <<  8) // (TWI) Not Acknowledged
+#define AT91C_TWI_NACK_MASTER (0x1 <<  8) // (TWI) Not Acknowledged
+#define AT91C_TWI_ARBLST_MULTI_MASTER (0x1 <<  9) // (TWI) Arbitration Lost (used only in Multimaster mode)
+#define AT91C_TWI_SCLWS       (0x1 << 10) // (TWI) Clock Wait State (used only in Slave mode)
+#define AT91C_TWI_EOSACC      (0x1 << 11) // (TWI) End Of Slave ACCess (used only in Slave mode)
+#define AT91C_TWI_ENDRX       (0x1 << 12) // (TWI) End of Receiver Transfer
+#define AT91C_TWI_ENDTX       (0x1 << 13) // (TWI) End of Receiver Transfer
+#define AT91C_TWI_RXBUFF      (0x1 << 14) // (TWI) RXBUFF Interrupt
+#define AT91C_TWI_TXBUFE      (0x1 << 15) // (TWI) TXBUFE Interrupt
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_USART {
+	AT91_REG	 US_CR; 	// Control Register
+	AT91_REG	 US_MR; 	// Mode Register
+	AT91_REG	 US_IER; 	// Interrupt Enable Register
+	AT91_REG	 US_IDR; 	// Interrupt Disable Register
+	AT91_REG	 US_IMR; 	// Interrupt Mask Register
+	AT91_REG	 US_CSR; 	// Channel Status Register
+	AT91_REG	 US_RHR; 	// Receiver Holding Register
+	AT91_REG	 US_THR; 	// Transmitter Holding Register
+	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
+	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
+	AT91_REG	 Reserved0[5]; 	// 
+	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
+	AT91_REG	 US_NER; 	// Nb Errors Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 US_IF; 	// IRDA_FILTER Register
+	AT91_REG	 Reserved2[44]; 	// 
+	AT91_REG	 US_RPR; 	// Receive Pointer Register
+	AT91_REG	 US_RCR; 	// Receive Counter Register
+	AT91_REG	 US_TPR; 	// Transmit Pointer Register
+	AT91_REG	 US_TCR; 	// Transmit Counter Register
+	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+#else
+#define US_CR           (AT91_CAST(AT91_REG *) 	0x00000000) // (US_CR) Control Register
+#define US_MR           (AT91_CAST(AT91_REG *) 	0x00000004) // (US_MR) Mode Register
+#define US_IER          (AT91_CAST(AT91_REG *) 	0x00000008) // (US_IER) Interrupt Enable Register
+#define US_IDR          (AT91_CAST(AT91_REG *) 	0x0000000C) // (US_IDR) Interrupt Disable Register
+#define US_IMR          (AT91_CAST(AT91_REG *) 	0x00000010) // (US_IMR) Interrupt Mask Register
+#define US_CSR          (AT91_CAST(AT91_REG *) 	0x00000014) // (US_CSR) Channel Status Register
+#define US_RHR          (AT91_CAST(AT91_REG *) 	0x00000018) // (US_RHR) Receiver Holding Register
+#define US_THR          (AT91_CAST(AT91_REG *) 	0x0000001C) // (US_THR) Transmitter Holding Register
+#define US_BRGR         (AT91_CAST(AT91_REG *) 	0x00000020) // (US_BRGR) Baud Rate Generator Register
+#define US_RTOR         (AT91_CAST(AT91_REG *) 	0x00000024) // (US_RTOR) Receiver Time-out Register
+#define US_TTGR         (AT91_CAST(AT91_REG *) 	0x00000028) // (US_TTGR) Transmitter Time-guard Register
+#define US_FIDI         (AT91_CAST(AT91_REG *) 	0x00000040) // (US_FIDI) FI_DI_Ratio Register
+#define US_NER          (AT91_CAST(AT91_REG *) 	0x00000044) // (US_NER) Nb Errors Register
+#define US_IF           (AT91_CAST(AT91_REG *) 	0x0000004C) // (US_IF) IRDA_FILTER Register
+
+#endif
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_STTBRK       (0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK       (0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO        (0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA        (0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT        (0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK      (0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO        (0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN        (0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS       (0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN        (0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS       (0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_USMODE       (0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS         (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL         (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC         (0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP       (0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF         (0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9        (0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO         (0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER         (0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK        (0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK       (0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER     (0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER       (0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK        (0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT      (0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION    (0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK         (0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC         (0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC        (0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC        (0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC        (0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+#define AT91C_US_RI           (0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR          (0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD          (0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS          (0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SSC {
+	AT91_REG	 SSC_CR; 	// Control Register
+	AT91_REG	 SSC_CMR; 	// Clock Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
+	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
+	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
+	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
+	AT91_REG	 SSC_RHR; 	// Receive Holding Register
+	AT91_REG	 SSC_THR; 	// Transmit Holding Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
+	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 SSC_SR; 	// Status Register
+	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
+	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved3[44]; 	// 
+	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
+	AT91_REG	 SSC_RCR; 	// Receive Counter Register
+	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
+	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+#else
+#define SSC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (SSC_CR) Control Register
+#define SSC_CMR         (AT91_CAST(AT91_REG *) 	0x00000004) // (SSC_CMR) Clock Mode Register
+#define SSC_RCMR        (AT91_CAST(AT91_REG *) 	0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
+#define SSC_RFMR        (AT91_CAST(AT91_REG *) 	0x00000014) // (SSC_RFMR) Receive Frame Mode Register
+#define SSC_TCMR        (AT91_CAST(AT91_REG *) 	0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
+#define SSC_TFMR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
+#define SSC_RHR         (AT91_CAST(AT91_REG *) 	0x00000020) // (SSC_RHR) Receive Holding Register
+#define SSC_THR         (AT91_CAST(AT91_REG *) 	0x00000024) // (SSC_THR) Transmit Holding Register
+#define SSC_RSHR        (AT91_CAST(AT91_REG *) 	0x00000030) // (SSC_RSHR) Receive Sync Holding Register
+#define SSC_TSHR        (AT91_CAST(AT91_REG *) 	0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
+#define SSC_SR          (AT91_CAST(AT91_REG *) 	0x00000040) // (SSC_SR) Status Register
+#define SSC_IER         (AT91_CAST(AT91_REG *) 	0x00000044) // (SSC_IER) Interrupt Enable Register
+#define SSC_IDR         (AT91_CAST(AT91_REG *) 	0x00000048) // (SSC_IDR) Interrupt Disable Register
+#define SSC_IMR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (SSC_IMR) Interrupt Mask Register
+
+#endif
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN        (0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS       (0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN        (0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS       (0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST       (0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS         (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO         (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI         (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START       (0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY      (0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD      (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN      (0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP        (0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF        (0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB       (0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN       (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS        (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE      (0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF      (0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN       (0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY       (0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY     (0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX       (0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE      (0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY       (0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN       (0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX       (0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF      (0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN       (0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN       (0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA       (0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA       (0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SPI {
+	AT91_REG	 SPI_CR; 	// Control Register
+	AT91_REG	 SPI_MR; 	// Mode Register
+	AT91_REG	 SPI_RDR; 	// Receive Data Register
+	AT91_REG	 SPI_TDR; 	// Transmit Data Register
+	AT91_REG	 SPI_SR; 	// Status Register
+	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
+	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
+	AT91_REG	 Reserved1[48]; 	// 
+	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
+	AT91_REG	 SPI_RCR; 	// Receive Counter Register
+	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
+	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+#else
+#define SPI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (SPI_CR) Control Register
+#define SPI_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (SPI_MR) Mode Register
+#define SPI_RDR         (AT91_CAST(AT91_REG *) 	0x00000008) // (SPI_RDR) Receive Data Register
+#define SPI_TDR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (SPI_TDR) Transmit Data Register
+#define SPI_SR          (AT91_CAST(AT91_REG *) 	0x00000010) // (SPI_SR) Status Register
+#define SPI_IER         (AT91_CAST(AT91_REG *) 	0x00000014) // (SPI_IER) Interrupt Enable Register
+#define SPI_IDR         (AT91_CAST(AT91_REG *) 	0x00000018) // (SPI_IDR) Interrupt Disable Register
+#define SPI_IMR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (SPI_IMR) Interrupt Mask Register
+#define SPI_CSR         (AT91_CAST(AT91_REG *) 	0x00000030) // (SPI_CSR) Chip Select Register
+
+#endif
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN       (0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS      (0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST       (0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER    (0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR        (0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS          (0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC      (0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV        (0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS     (0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB         (0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS         (0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS      (0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD          (0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD          (0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF        (0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE        (0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF        (0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES       (0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX       (0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX       (0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF      (0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE      (0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR        (0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY     (0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS      (0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL        (0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA       (0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT       (0x1 <<  3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS        (0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR        (0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS       (0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT      (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_ADC {
+	AT91_REG	 ADC_CR; 	// ADC Control Register
+	AT91_REG	 ADC_MR; 	// ADC Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
+	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
+	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
+	AT91_REG	 ADC_SR; 	// ADC Status Register
+	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
+	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
+	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
+	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
+	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
+	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
+	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
+	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
+	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
+	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
+	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
+	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
+	AT91_REG	 Reserved1[44]; 	// 
+	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
+	AT91_REG	 ADC_RCR; 	// Receive Counter Register
+	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
+	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
+#else
+#define ADC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (ADC_CR) ADC Control Register
+#define ADC_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (ADC_MR) ADC Mode Register
+#define ADC_CHER        (AT91_CAST(AT91_REG *) 	0x00000010) // (ADC_CHER) ADC Channel Enable Register
+#define ADC_CHDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (ADC_CHDR) ADC Channel Disable Register
+#define ADC_CHSR        (AT91_CAST(AT91_REG *) 	0x00000018) // (ADC_CHSR) ADC Channel Status Register
+#define ADC_SR          (AT91_CAST(AT91_REG *) 	0x0000001C) // (ADC_SR) ADC Status Register
+#define ADC_LCDR        (AT91_CAST(AT91_REG *) 	0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
+#define ADC_IER         (AT91_CAST(AT91_REG *) 	0x00000024) // (ADC_IER) ADC Interrupt Enable Register
+#define ADC_IDR         (AT91_CAST(AT91_REG *) 	0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
+#define ADC_IMR         (AT91_CAST(AT91_REG *) 	0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
+#define ADC_CDR0        (AT91_CAST(AT91_REG *) 	0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
+#define ADC_CDR1        (AT91_CAST(AT91_REG *) 	0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
+#define ADC_CDR2        (AT91_CAST(AT91_REG *) 	0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
+#define ADC_CDR3        (AT91_CAST(AT91_REG *) 	0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
+#define ADC_CDR4        (AT91_CAST(AT91_REG *) 	0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
+#define ADC_CDR5        (AT91_CAST(AT91_REG *) 	0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
+#define ADC_CDR6        (AT91_CAST(AT91_REG *) 	0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
+#define ADC_CDR7        (AT91_CAST(AT91_REG *) 	0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
+
+#endif
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+#define AT91C_ADC_SWRST       (0x1 <<  0) // (ADC) Software Reset
+#define AT91C_ADC_START       (0x1 <<  1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+#define AT91C_ADC_TRGEN       (0x1 <<  0) // (ADC) Trigger Enable
+#define 	AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define 	AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL      (0x7 <<  1) // (ADC) Trigger Selection
+#define 	AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
+#define 	AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
+#define 	AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
+#define 	AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
+#define 	AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
+#define 	AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
+#define 	AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES      (0x1 <<  4) // (ADC) Resolution.
+#define 	AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
+#define 	AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP       (0x1 <<  5) // (ADC) Sleep Mode
+#define 	AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
+#define 	AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL     (0x3F <<  8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP     (0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM       (0xF << 24) // (ADC) Sample & Hold Time
+// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+#define AT91C_ADC_CH0         (0x1 <<  0) // (ADC) Channel 0
+#define AT91C_ADC_CH1         (0x1 <<  1) // (ADC) Channel 1
+#define AT91C_ADC_CH2         (0x1 <<  2) // (ADC) Channel 2
+#define AT91C_ADC_CH3         (0x1 <<  3) // (ADC) Channel 3
+#define AT91C_ADC_CH4         (0x1 <<  4) // (ADC) Channel 4
+#define AT91C_ADC_CH5         (0x1 <<  5) // (ADC) Channel 5
+#define AT91C_ADC_CH6         (0x1 <<  6) // (ADC) Channel 6
+#define AT91C_ADC_CH7         (0x1 <<  7) // (ADC) Channel 7
+// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+#define AT91C_ADC_EOC0        (0x1 <<  0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1        (0x1 <<  1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2        (0x1 <<  2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3        (0x1 <<  3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4        (0x1 <<  4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5        (0x1 <<  5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6        (0x1 <<  6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7        (0x1 <<  7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0       (0x1 <<  8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1       (0x1 <<  9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2       (0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3       (0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4       (0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5       (0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6       (0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7       (0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY        (0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE       (0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX       (0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF      (0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+#define AT91C_ADC_LDATA       (0x3FF <<  0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+#define AT91C_ADC_DATA        (0x3FF <<  0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_EMAC {
+	AT91_REG	 EMAC_NCR; 	// Network Control Register
+	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
+	AT91_REG	 EMAC_NSR; 	// Network Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
+	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
+	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
+	AT91_REG	 EMAC_RSR; 	// Receive Status Register
+	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
+	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
+	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
+	AT91_REG	 EMAC_PTR; 	// Pause Time Register
+	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
+	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
+	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
+	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
+	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
+	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
+	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
+	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
+	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
+	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
+	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
+	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
+	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
+	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
+	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
+	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
+	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
+	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
+	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
+	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
+	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
+	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
+	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
+	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
+	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
+	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
+	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
+	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
+	AT91_REG	 Reserved1[13]; 	// 
+	AT91_REG	 EMAC_REV; 	// Revision Register
+} AT91S_EMAC, *AT91PS_EMAC;
+#else
+#define EMAC_NCR        (AT91_CAST(AT91_REG *) 	0x00000000) // (EMAC_NCR) Network Control Register
+#define EMAC_NCFGR      (AT91_CAST(AT91_REG *) 	0x00000004) // (EMAC_NCFGR) Network Configuration Register
+#define EMAC_NSR        (AT91_CAST(AT91_REG *) 	0x00000008) // (EMAC_NSR) Network Status Register
+#define EMAC_TSR        (AT91_CAST(AT91_REG *) 	0x00000014) // (EMAC_TSR) Transmit Status Register
+#define EMAC_RBQP       (AT91_CAST(AT91_REG *) 	0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer
+#define EMAC_TBQP       (AT91_CAST(AT91_REG *) 	0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer
+#define EMAC_RSR        (AT91_CAST(AT91_REG *) 	0x00000020) // (EMAC_RSR) Receive Status Register
+#define EMAC_ISR        (AT91_CAST(AT91_REG *) 	0x00000024) // (EMAC_ISR) Interrupt Status Register
+#define EMAC_IER        (AT91_CAST(AT91_REG *) 	0x00000028) // (EMAC_IER) Interrupt Enable Register
+#define EMAC_IDR        (AT91_CAST(AT91_REG *) 	0x0000002C) // (EMAC_IDR) Interrupt Disable Register
+#define EMAC_IMR        (AT91_CAST(AT91_REG *) 	0x00000030) // (EMAC_IMR) Interrupt Mask Register
+#define EMAC_MAN        (AT91_CAST(AT91_REG *) 	0x00000034) // (EMAC_MAN) PHY Maintenance Register
+#define EMAC_PTR        (AT91_CAST(AT91_REG *) 	0x00000038) // (EMAC_PTR) Pause Time Register
+#define EMAC_PFR        (AT91_CAST(AT91_REG *) 	0x0000003C) // (EMAC_PFR) Pause Frames received Register
+#define EMAC_FTO        (AT91_CAST(AT91_REG *) 	0x00000040) // (EMAC_FTO) Frames Transmitted OK Register
+#define EMAC_SCF        (AT91_CAST(AT91_REG *) 	0x00000044) // (EMAC_SCF) Single Collision Frame Register
+#define EMAC_MCF        (AT91_CAST(AT91_REG *) 	0x00000048) // (EMAC_MCF) Multiple Collision Frame Register
+#define EMAC_FRO        (AT91_CAST(AT91_REG *) 	0x0000004C) // (EMAC_FRO) Frames Received OK Register
+#define EMAC_FCSE       (AT91_CAST(AT91_REG *) 	0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register
+#define EMAC_ALE        (AT91_CAST(AT91_REG *) 	0x00000054) // (EMAC_ALE) Alignment Error Register
+#define EMAC_DTF        (AT91_CAST(AT91_REG *) 	0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register
+#define EMAC_LCOL       (AT91_CAST(AT91_REG *) 	0x0000005C) // (EMAC_LCOL) Late Collision Register
+#define EMAC_ECOL       (AT91_CAST(AT91_REG *) 	0x00000060) // (EMAC_ECOL) Excessive Collision Register
+#define EMAC_TUND       (AT91_CAST(AT91_REG *) 	0x00000064) // (EMAC_TUND) Transmit Underrun Error Register
+#define EMAC_CSE        (AT91_CAST(AT91_REG *) 	0x00000068) // (EMAC_CSE) Carrier Sense Error Register
+#define EMAC_RRE        (AT91_CAST(AT91_REG *) 	0x0000006C) // (EMAC_RRE) Receive Ressource Error Register
+#define EMAC_ROV        (AT91_CAST(AT91_REG *) 	0x00000070) // (EMAC_ROV) Receive Overrun Errors Register
+#define EMAC_RSE        (AT91_CAST(AT91_REG *) 	0x00000074) // (EMAC_RSE) Receive Symbol Errors Register
+#define EMAC_ELE        (AT91_CAST(AT91_REG *) 	0x00000078) // (EMAC_ELE) Excessive Length Errors Register
+#define EMAC_RJA        (AT91_CAST(AT91_REG *) 	0x0000007C) // (EMAC_RJA) Receive Jabbers Register
+#define EMAC_USF        (AT91_CAST(AT91_REG *) 	0x00000080) // (EMAC_USF) Undersize Frames Register
+#define EMAC_STE        (AT91_CAST(AT91_REG *) 	0x00000084) // (EMAC_STE) SQE Test Error Register
+#define EMAC_RLE        (AT91_CAST(AT91_REG *) 	0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register
+#define EMAC_TPF        (AT91_CAST(AT91_REG *) 	0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register
+#define EMAC_HRB        (AT91_CAST(AT91_REG *) 	0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0]
+#define EMAC_HRT        (AT91_CAST(AT91_REG *) 	0x00000094) // (EMAC_HRT) Hash Address Top[63:32]
+#define EMAC_SA1L       (AT91_CAST(AT91_REG *) 	0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes
+#define EMAC_SA1H       (AT91_CAST(AT91_REG *) 	0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes
+#define EMAC_SA2L       (AT91_CAST(AT91_REG *) 	0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes
+#define EMAC_SA2H       (AT91_CAST(AT91_REG *) 	0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes
+#define EMAC_SA3L       (AT91_CAST(AT91_REG *) 	0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes
+#define EMAC_SA3H       (AT91_CAST(AT91_REG *) 	0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes
+#define EMAC_SA4L       (AT91_CAST(AT91_REG *) 	0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes
+#define EMAC_SA4H       (AT91_CAST(AT91_REG *) 	0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes
+#define EMAC_TID        (AT91_CAST(AT91_REG *) 	0x000000B8) // (EMAC_TID) Type ID Checking Register
+#define EMAC_TPQ        (AT91_CAST(AT91_REG *) 	0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register
+#define EMAC_USRIO      (AT91_CAST(AT91_REG *) 	0x000000C0) // (EMAC_USRIO) USER Input/Output Register
+#define EMAC_WOL        (AT91_CAST(AT91_REG *) 	0x000000C4) // (EMAC_WOL) Wake On LAN Register
+#define EMAC_REV        (AT91_CAST(AT91_REG *) 	0x000000FC) // (EMAC_REV) Revision Register
+
+#endif
+// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+#define AT91C_EMAC_LB         (0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB        (0x1 <<  1) // (EMAC) Loopback local. 
+#define AT91C_EMAC_RE         (0x1 <<  2) // (EMAC) Receive enable. 
+#define AT91C_EMAC_TE         (0x1 <<  3) // (EMAC) Transmit enable. 
+#define AT91C_EMAC_MPE        (0x1 <<  4) // (EMAC) Management port enable. 
+#define AT91C_EMAC_CLRSTAT    (0x1 <<  5) // (EMAC) Clear statistics registers. 
+#define AT91C_EMAC_INCSTAT    (0x1 <<  6) // (EMAC) Increment statistics registers. 
+#define AT91C_EMAC_WESTAT     (0x1 <<  7) // (EMAC) Write enable for statistics registers. 
+#define AT91C_EMAC_BP         (0x1 <<  8) // (EMAC) Back pressure. 
+#define AT91C_EMAC_TSTART     (0x1 <<  9) // (EMAC) Start Transmission. 
+#define AT91C_EMAC_THALT      (0x1 << 10) // (EMAC) Transmission Halt. 
+#define AT91C_EMAC_TPFR       (0x1 << 11) // (EMAC) Transmit pause frame 
+#define AT91C_EMAC_TZQ        (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+#define AT91C_EMAC_SPD        (0x1 <<  0) // (EMAC) Speed. 
+#define AT91C_EMAC_FD         (0x1 <<  1) // (EMAC) Full duplex. 
+#define AT91C_EMAC_JFRAME     (0x1 <<  3) // (EMAC) Jumbo Frames. 
+#define AT91C_EMAC_CAF        (0x1 <<  4) // (EMAC) Copy all frames. 
+#define AT91C_EMAC_NBC        (0x1 <<  5) // (EMAC) No broadcast. 
+#define AT91C_EMAC_MTI        (0x1 <<  6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI        (0x1 <<  7) // (EMAC) Unicast hash enable. 
+#define AT91C_EMAC_BIG        (0x1 <<  8) // (EMAC) Receive 1522 bytes. 
+#define AT91C_EMAC_EAE        (0x1 <<  9) // (EMAC) External address match enable. 
+#define AT91C_EMAC_CLK        (0x3 << 10) // (EMAC) 
+#define 	AT91C_EMAC_CLK_HCLK_8               (0x0 << 10) // (EMAC) HCLK divided by 8
+#define 	AT91C_EMAC_CLK_HCLK_16              (0x1 << 10) // (EMAC) HCLK divided by 16
+#define 	AT91C_EMAC_CLK_HCLK_32              (0x2 << 10) // (EMAC) HCLK divided by 32
+#define 	AT91C_EMAC_CLK_HCLK_64              (0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY        (0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PAE        (0x1 << 13) // (EMAC) 
+#define AT91C_EMAC_RBOF       (0x3 << 14) // (EMAC) 
+#define 	AT91C_EMAC_RBOF_OFFSET_0             (0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_1             (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_2             (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_3             (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE       (0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS      (0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD      (0x1 << 18) // (EMAC) 
+#define AT91C_EMAC_IRXFCS     (0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+#define AT91C_EMAC_LINKR      (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_MDIO       (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_IDLE       (0x1 <<  2) // (EMAC) 
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+#define AT91C_EMAC_UBR        (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_COL        (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RLES       (0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TGO        (0x1 <<  3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX        (0x1 <<  4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP       (0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_UND        (0x1 <<  6) // (EMAC) 
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+#define AT91C_EMAC_BNA        (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_REC        (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_OVR        (0x1 <<  2) // (EMAC) 
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+#define AT91C_EMAC_MFD        (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_RCOMP      (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RXUBR      (0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TXUBR      (0x1 <<  3) // (EMAC) 
+#define AT91C_EMAC_TUNDR      (0x1 <<  4) // (EMAC) 
+#define AT91C_EMAC_RLEX       (0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_TXERR      (0x1 <<  6) // (EMAC) 
+#define AT91C_EMAC_TCOMP      (0x1 <<  7) // (EMAC) 
+#define AT91C_EMAC_LINK       (0x1 <<  9) // (EMAC) 
+#define AT91C_EMAC_ROVR       (0x1 << 10) // (EMAC) 
+#define AT91C_EMAC_HRESP      (0x1 << 11) // (EMAC) 
+#define AT91C_EMAC_PFRE       (0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PTZ        (0x1 << 13) // (EMAC) 
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+#define AT91C_EMAC_DATA       (0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_CODE       (0x3 << 16) // (EMAC) 
+#define AT91C_EMAC_REGA       (0x1F << 18) // (EMAC) 
+#define AT91C_EMAC_PHYA       (0x1F << 23) // (EMAC) 
+#define AT91C_EMAC_RW         (0x3 << 28) // (EMAC) 
+#define AT91C_EMAC_SOF        (0x3 << 30) // (EMAC) 
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+#define AT91C_EMAC_RMII       (0x1 <<  0) // (EMAC) Reduce MII
+#define AT91C_EMAC_CLKEN      (0x1 <<  1) // (EMAC) Clock Enable
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+#define AT91C_EMAC_IP         (0xFFFF <<  0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG        (0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP        (0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1        (0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+#define AT91C_EMAC_REVREF     (0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_PARTREF    (0xFFFF << 16) // (EMAC) 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_UDP {
+	AT91_REG	 UDP_NUM; 	// Frame Number Register
+	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
+	AT91_REG	 UDP_FADDR; 	// Function Address Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
+	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
+	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
+	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
+	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
+	AT91_REG	 Reserved4[3]; 	// 
+	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
+#else
+#define UDP_FRM_NUM     (AT91_CAST(AT91_REG *) 	0x00000000) // (UDP_FRM_NUM) Frame Number Register
+#define UDP_GLBSTATE    (AT91_CAST(AT91_REG *) 	0x00000004) // (UDP_GLBSTATE) Global State Register
+#define UDP_FADDR       (AT91_CAST(AT91_REG *) 	0x00000008) // (UDP_FADDR) Function Address Register
+#define UDP_IER         (AT91_CAST(AT91_REG *) 	0x00000010) // (UDP_IER) Interrupt Enable Register
+#define UDP_IDR         (AT91_CAST(AT91_REG *) 	0x00000014) // (UDP_IDR) Interrupt Disable Register
+#define UDP_IMR         (AT91_CAST(AT91_REG *) 	0x00000018) // (UDP_IMR) Interrupt Mask Register
+#define UDP_ISR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (UDP_ISR) Interrupt Status Register
+#define UDP_ICR         (AT91_CAST(AT91_REG *) 	0x00000020) // (UDP_ICR) Interrupt Clear Register
+#define UDP_RSTEP       (AT91_CAST(AT91_REG *) 	0x00000028) // (UDP_RSTEP) Reset Endpoint Register
+#define UDP_CSR         (AT91_CAST(AT91_REG *) 	0x00000030) // (UDP_CSR) Endpoint Control and Status Register
+#define UDP_FDR         (AT91_CAST(AT91_REG *) 	0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
+#define UDP_TXVC        (AT91_CAST(AT91_REG *) 	0x00000074) // (UDP_TXVC) Transceiver Control Register
+
+#endif
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+#define AT91C_UDP_FRM_NUM     (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR     (0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK      (0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+#define AT91C_UDP_FADDEN      (0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG       (0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_ESR         (0x1 <<  2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR     (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE      (0x1 <<  4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+#define AT91C_UDP_FADD        (0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN         (0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+#define AT91C_UDP_EPINT0      (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1      (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2      (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3      (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4      (0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5      (0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP      (0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM       (0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM      (0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT      (0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP      (0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+#define AT91C_UDP_ENDBUSRES   (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+#define AT91C_UDP_EP0         (0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1         (0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2         (0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3         (0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4         (0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5         (0x1 <<  5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+#define AT91C_UDP_TXCOMP      (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 (0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP     (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR    (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_STALLSENT   (0x1 <<  3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
+#define AT91C_UDP_TXPKTRDY    (0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL  (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR         (0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE      (0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE       (0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS       (0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT   (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+#define AT91C_UDP_TXVDIS      (0x1 <<  8) // (UDP) 
+#define AT91C_UDP_PUON        (0x1 <<  9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Host Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_UHP {
+	AT91_REG	 UHP_HcRevision; 	// Revision
+	AT91_REG	 UHP_HcControl; 	// Operating modes for the Host Controller
+	AT91_REG	 UHP_HcCommandStatus; 	// Command & status Register
+	AT91_REG	 UHP_HcInterruptStatus; 	// Interrupt Status Register
+	AT91_REG	 UHP_HcInterruptEnable; 	// Interrupt Enable Register
+	AT91_REG	 UHP_HcInterruptDisable; 	// Interrupt Disable Register
+	AT91_REG	 UHP_HcHCCA; 	// Pointer to the Host Controller Communication Area
+	AT91_REG	 UHP_HcPeriodCurrentED; 	// Current Isochronous or Interrupt Endpoint Descriptor
+	AT91_REG	 UHP_HcControlHeadED; 	// First Endpoint Descriptor of the Control list
+	AT91_REG	 UHP_HcControlCurrentED; 	// Endpoint Control and Status Register
+	AT91_REG	 UHP_HcBulkHeadED; 	// First endpoint register of the Bulk list
+	AT91_REG	 UHP_HcBulkCurrentED; 	// Current endpoint of the Bulk list
+	AT91_REG	 UHP_HcBulkDoneHead; 	// Last completed transfer descriptor
+	AT91_REG	 UHP_HcFmInterval; 	// Bit time between 2 consecutive SOFs
+	AT91_REG	 UHP_HcFmRemaining; 	// Bit time remaining in the current Frame
+	AT91_REG	 UHP_HcFmNumber; 	// Frame number
+	AT91_REG	 UHP_HcPeriodicStart; 	// Periodic Start
+	AT91_REG	 UHP_HcLSThreshold; 	// LS Threshold
+	AT91_REG	 UHP_HcRhDescriptorA; 	// Root Hub characteristics A
+	AT91_REG	 UHP_HcRhDescriptorB; 	// Root Hub characteristics B
+	AT91_REG	 UHP_HcRhStatus; 	// Root Hub Status register
+	AT91_REG	 UHP_HcRhPortStatus[2]; 	// Root Hub Port Status Register
+} AT91S_UHP, *AT91PS_UHP;
+#else
+#define HcRevision      (AT91_CAST(AT91_REG *) 	0x00000000) // (HcRevision) Revision
+#define HcControl       (AT91_CAST(AT91_REG *) 	0x00000004) // (HcControl) Operating modes for the Host Controller
+#define HcCommandStatus (AT91_CAST(AT91_REG *) 	0x00000008) // (HcCommandStatus) Command & status Register
+#define HcInterruptStatus (AT91_CAST(AT91_REG *) 	0x0000000C) // (HcInterruptStatus) Interrupt Status Register
+#define HcInterruptEnable (AT91_CAST(AT91_REG *) 	0x00000010) // (HcInterruptEnable) Interrupt Enable Register
+#define HcInterruptDisable (AT91_CAST(AT91_REG *) 	0x00000014) // (HcInterruptDisable) Interrupt Disable Register
+#define HcHCCA          (AT91_CAST(AT91_REG *) 	0x00000018) // (HcHCCA) Pointer to the Host Controller Communication Area
+#define HcPeriodCurrentED (AT91_CAST(AT91_REG *) 	0x0000001C) // (HcPeriodCurrentED) Current Isochronous or Interrupt Endpoint Descriptor
+#define HcControlHeadED (AT91_CAST(AT91_REG *) 	0x00000020) // (HcControlHeadED) First Endpoint Descriptor of the Control list
+#define HcControlCurrentED (AT91_CAST(AT91_REG *) 	0x00000024) // (HcControlCurrentED) Endpoint Control and Status Register
+#define HcBulkHeadED    (AT91_CAST(AT91_REG *) 	0x00000028) // (HcBulkHeadED) First endpoint register of the Bulk list
+#define HcBulkCurrentED (AT91_CAST(AT91_REG *) 	0x0000002C) // (HcBulkCurrentED) Current endpoint of the Bulk list
+#define HcBulkDoneHead  (AT91_CAST(AT91_REG *) 	0x00000030) // (HcBulkDoneHead) Last completed transfer descriptor
+#define HcFmInterval    (AT91_CAST(AT91_REG *) 	0x00000034) // (HcFmInterval) Bit time between 2 consecutive SOFs
+#define HcFmRemaining   (AT91_CAST(AT91_REG *) 	0x00000038) // (HcFmRemaining) Bit time remaining in the current Frame
+#define HcFmNumber      (AT91_CAST(AT91_REG *) 	0x0000003C) // (HcFmNumber) Frame number
+#define HcPeriodicStart (AT91_CAST(AT91_REG *) 	0x00000040) // (HcPeriodicStart) Periodic Start
+#define HcLSThreshold   (AT91_CAST(AT91_REG *) 	0x00000044) // (HcLSThreshold) LS Threshold
+#define HcRhDescriptorA (AT91_CAST(AT91_REG *) 	0x00000048) // (HcRhDescriptorA) Root Hub characteristics A
+#define HcRhDescriptorB (AT91_CAST(AT91_REG *) 	0x0000004C) // (HcRhDescriptorB) Root Hub characteristics B
+#define HcRhStatus      (AT91_CAST(AT91_REG *) 	0x00000050) // (HcRhStatus) Root Hub Status register
+#define HcRhPortStatus  (AT91_CAST(AT91_REG *) 	0x00000054) // (HcRhPortStatus) Root Hub Port Status Register
+
+#endif
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Image Sensor Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_ISI {
+	AT91_REG	 ISI_CR1; 	// Control Register 1
+	AT91_REG	 ISI_CR2; 	// Control Register 2
+	AT91_REG	 ISI_SR; 	// Status Register
+	AT91_REG	 ISI_IER; 	// Interrupt Enable Register
+	AT91_REG	 ISI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 ISI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 ISI_PSIZE; 	// Preview Size Register
+	AT91_REG	 ISI_PDECF; 	// Preview Decimation Factor Register
+	AT91_REG	 ISI_PFBD; 	// Preview Frame Buffer Address Register
+	AT91_REG	 ISI_CDBA; 	// Codec Dma Address Register
+	AT91_REG	 ISI_Y2RSET0; 	// Color Space Conversion Register
+	AT91_REG	 ISI_Y2RSET1; 	// Color Space Conversion Register
+	AT91_REG	 ISI_R2YSET0; 	// Color Space Conversion Register
+	AT91_REG	 ISI_R2YSET1; 	// Color Space Conversion Register
+	AT91_REG	 ISI_R2YSET2; 	// Color Space Conversion Register
+} AT91S_ISI, *AT91PS_ISI;
+#else
+#define ISI_CR1         (AT91_CAST(AT91_REG *) 	0x00000000) // (ISI_CR1) Control Register 1
+#define ISI_CR2         (AT91_CAST(AT91_REG *) 	0x00000004) // (ISI_CR2) Control Register 2
+#define ISI_SR          (AT91_CAST(AT91_REG *) 	0x00000008) // (ISI_SR) Status Register
+#define ISI_IER         (AT91_CAST(AT91_REG *) 	0x0000000C) // (ISI_IER) Interrupt Enable Register
+#define ISI_IDR         (AT91_CAST(AT91_REG *) 	0x00000010) // (ISI_IDR) Interrupt Disable Register
+#define ISI_IMR         (AT91_CAST(AT91_REG *) 	0x00000014) // (ISI_IMR) Interrupt Mask Register
+#define ISI_PSIZE       (AT91_CAST(AT91_REG *) 	0x00000020) // (ISI_PSIZE) Preview Size Register
+#define ISI_PDECF       (AT91_CAST(AT91_REG *) 	0x00000024) // (ISI_PDECF) Preview Decimation Factor Register
+#define ISI_PFBD        (AT91_CAST(AT91_REG *) 	0x00000028) // (ISI_PFBD) Preview Frame Buffer Address Register
+#define ISI_CDBA        (AT91_CAST(AT91_REG *) 	0x0000002C) // (ISI_CDBA) Codec Dma Address Register
+#define ISI_Y2RSET0     (AT91_CAST(AT91_REG *) 	0x00000030) // (ISI_Y2RSET0) Color Space Conversion Register
+#define ISI_Y2RSET1     (AT91_CAST(AT91_REG *) 	0x00000034) // (ISI_Y2RSET1) Color Space Conversion Register
+#define ISI_R2YSET0     (AT91_CAST(AT91_REG *) 	0x00000038) // (ISI_R2YSET0) Color Space Conversion Register
+#define ISI_R2YSET1     (AT91_CAST(AT91_REG *) 	0x0000003C) // (ISI_R2YSET1) Color Space Conversion Register
+#define ISI_R2YSET2     (AT91_CAST(AT91_REG *) 	0x00000040) // (ISI_R2YSET2) Color Space Conversion Register
+
+#endif
+// -------- ISI_CR1 : (ISI Offset: 0x0) ISI Control Register 1 -------- 
+#define AT91C_ISI_RST         (0x1 <<  0) // (ISI) Image sensor interface reset
+#define AT91C_ISI_DISABLE     (0x1 <<  1) // (ISI) image sensor disable.
+#define AT91C_ISI_HSYNC_POL   (0x1 <<  2) // (ISI) Horizontal synchronisation polarity
+#define AT91C_ISI_PIXCLK_POL  (0x1 <<  4) // (ISI) Pixel Clock Polarity
+#define AT91C_ISI_EMB_SYNC    (0x1 <<  6) // (ISI) Embedded synchronisation
+#define AT91C_ISI_CRC_SYNC    (0x1 <<  7) // (ISI) CRC correction
+#define AT91C_ISI_FULL        (0x1 << 12) // (ISI) Full mode is allowed
+#define AT91C_ISI_THMASK      (0x3 << 13) // (ISI) DMA Burst Mask
+#define 	AT91C_ISI_THMASK_4_8_16_BURST         (0x0 << 13) // (ISI) 4,8 and 16 AHB burst are allowed
+#define 	AT91C_ISI_THMASK_8_16_BURST           (0x1 << 13) // (ISI) 8 and 16 AHB burst are allowed
+#define 	AT91C_ISI_THMASK_16_BURST             (0x2 << 13) // (ISI) Only 16 AHB burst are allowed
+#define AT91C_ISI_CODEC_ON    (0x1 << 15) // (ISI) Enable the codec path
+#define AT91C_ISI_SLD         (0xFF << 16) // (ISI) Start of Line Delay
+#define AT91C_ISI_SFD         (0xFF << 24) // (ISI) Start of frame Delay
+// -------- ISI_CR2 : (ISI Offset: 0x4) ISI Control Register 2 -------- 
+#define AT91C_ISI_IM_VSIZE    (0x7FF <<  0) // (ISI) Vertical size of the Image sensor [0..2047]
+#define AT91C_ISI_GS_MODE     (0x1 << 11) // (ISI) Grayscale Memory Mode
+#define AT91C_ISI_RGB_MODE    (0x3 << 12) // (ISI) RGB mode
+#define 	AT91C_ISI_RGB_MODE_RGB_888              (0x0 << 12) // (ISI) RGB 8:8:8 24 bits
+#define 	AT91C_ISI_RGB_MODE_RGB_565              (0x1 << 12) // (ISI) RGB 5:6:5 16 bits
+#define 	AT91C_ISI_RGB_MODE_RGB_555              (0x2 << 12) // (ISI) RGB 5:5:5 16 bits
+#define AT91C_ISI_GRAYSCALE   (0x1 << 13) // (ISI) Grayscale Mode
+#define AT91C_ISI_RGB_SWAP    (0x1 << 14) // (ISI) RGB Swap
+#define AT91C_ISI_COL_SPACE   (0x1 << 15) // (ISI) Color space for the image data
+#define AT91C_ISI_IM_HSIZE    (0x7FF << 16) // (ISI) Horizontal size of the Image sensor [0..2047]
+#define 	AT91C_ISI_RGB_MODE_YCC_DEF              (0x0 << 28) // (ISI) Cb(i) Y(i) Cr(i) Y(i+1)
+#define 	AT91C_ISI_RGB_MODE_YCC_MOD1             (0x1 << 28) // (ISI) Cr(i) Y(i) Cb(i) Y(i+1)
+#define 	AT91C_ISI_RGB_MODE_YCC_MOD2             (0x2 << 28) // (ISI) Y(i) Cb(i) Y(i+1) Cr(i)
+#define 	AT91C_ISI_RGB_MODE_YCC_MOD3             (0x3 << 28) // (ISI) Y(i) Cr(i) Y(i+1) Cb(i)
+#define AT91C_ISI_RGB_CFG     (0x3 << 30) // (ISI) RGB configuration
+#define 	AT91C_ISI_RGB_CFG_RGB_DEF              (0x0 << 30) // (ISI) R/G(MSB)  G(LSB)/B  R/G(MSB)  G(LSB)/B
+#define 	AT91C_ISI_RGB_CFG_RGB_MOD1             (0x1 << 30) // (ISI) B/G(MSB)  G(LSB)/R  B/G(MSB)  G(LSB)/R
+#define 	AT91C_ISI_RGB_CFG_RGB_MOD2             (0x2 << 30) // (ISI) G(LSB)/R  B/G(MSB)  G(LSB)/R  B/G(MSB)
+#define 	AT91C_ISI_RGB_CFG_RGB_MOD3             (0x3 << 30) // (ISI) G(LSB)/B  R/G(MSB)  G(LSB)/B  R/G(MSB)
+// -------- ISI_SR : (ISI Offset: 0x8) ISI Status Register -------- 
+#define AT91C_ISI_SOF         (0x1 <<  0) // (ISI) Start of Frame
+#define AT91C_ISI_DIS         (0x1 <<  1) // (ISI) Image Sensor Interface disable
+#define AT91C_ISI_SOFTRST     (0x1 <<  2) // (ISI) Software Reset
+#define AT91C_ISI_CRC_ERR     (0x1 <<  4) // (ISI) CRC synchronisation error
+#define AT91C_ISI_FO_C_OVF    (0x1 <<  5) // (ISI) Fifo Codec Overflow 
+#define AT91C_ISI_FO_P_OVF    (0x1 <<  6) // (ISI) Fifo Preview Overflow 
+#define AT91C_ISI_FO_P_EMP    (0x1 <<  7) // (ISI) Fifo Preview Empty
+#define AT91C_ISI_FO_C_EMP    (0x1 <<  8) // (ISI) Fifo Codec Empty
+#define AT91C_ISI_FR_OVR      (0x1 <<  9) // (ISI) Frame rate overun
+// -------- ISI_IER : (ISI Offset: 0xc) ISI Interrupt Enable Register -------- 
+// -------- ISI_IDR : (ISI Offset: 0x10) ISI Interrupt Disable Register -------- 
+// -------- ISI_IMR : (ISI Offset: 0x14) ISI Interrupt Mask Register -------- 
+// -------- ISI_PSIZE : (ISI Offset: 0x20) ISI Preview Register -------- 
+#define AT91C_ISI_PREV_VSIZE  (0x3FF <<  0) // (ISI) Vertical size for the preview path
+#define AT91C_ISI_PREV_HSIZE  (0x3FF << 16) // (ISI) Horizontal size for the preview path
+// -------- ISI_Y2R_SET0 : (ISI Offset: 0x30) Color Space Conversion YCrCb to RGB Register -------- 
+#define AT91C_ISI_Y2R_C0      (0xFF <<  0) // (ISI) Color Space Conversion Matrix Coefficient C0
+#define AT91C_ISI_Y2R_C1      (0xFF <<  8) // (ISI) Color Space Conversion Matrix Coefficient C1
+#define AT91C_ISI_Y2R_C2      (0xFF << 16) // (ISI) Color Space Conversion Matrix Coefficient C2
+#define AT91C_ISI_Y2R_C3      (0xFF << 24) // (ISI) Color Space Conversion Matrix Coefficient C3
+// -------- ISI_Y2R_SET1 : (ISI Offset: 0x34) ISI Color Space Conversion YCrCb to RGB set 1 Register -------- 
+#define AT91C_ISI_Y2R_C4      (0x1FF <<  0) // (ISI) Color Space Conversion Matrix Coefficient C4
+#define AT91C_ISI_Y2R_YOFF    (0xFF << 12) // (ISI) Color Space Conversion Luninance default offset
+#define AT91C_ISI_Y2R_CROFF   (0xFF << 13) // (ISI) Color Space Conversion Red Chrominance default offset
+#define AT91C_ISI_Y2R_CBFF    (0xFF << 14) // (ISI) Color Space Conversion Luninance default offset
+// -------- ISI_R2Y_SET0 : (ISI Offset: 0x38) Color Space Conversion RGB to YCrCb set 0 register -------- 
+#define AT91C_ISI_R2Y_C0      (0x7F <<  0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C0
+#define AT91C_ISI_R2Y_C1      (0x7F <<  1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C1
+#define AT91C_ISI_R2Y_C2      (0x7F <<  3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C2
+#define AT91C_ISI_R2Y_ROFF    (0x1 <<  4) // (ISI) Color Space Conversion Red component offset
+// -------- ISI_R2Y_SET1 : (ISI Offset: 0x3c) Color Space Conversion RGB to YCrCb set 1 register -------- 
+#define AT91C_ISI_R2Y_C3      (0x7F <<  0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C3
+#define AT91C_ISI_R2Y_C4      (0x7F <<  1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C4
+#define AT91C_ISI_R2Y_C5      (0x7F <<  3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C5
+#define AT91C_ISI_R2Y_GOFF    (0x1 <<  4) // (ISI) Color Space Conversion Green component offset
+// -------- ISI_R2Y_SET2 : (ISI Offset: 0x40) Color Space Conversion RGB to YCrCb set 2 register -------- 
+#define AT91C_ISI_R2Y_C6      (0x7F <<  0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C6
+#define AT91C_ISI_R2Y_C7      (0x7F <<  1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C7
+#define AT91C_ISI_R2Y_C8      (0x7F <<  3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C8
+#define AT91C_ISI_R2Y_BOFF    (0x1 <<  4) // (ISI) Color Space Conversion Blue component offset
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM9XE128
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ========== 
+#define AT91C_SYS_GPBR  (AT91_CAST(AT91_REG *) 	0xFFFFFFFF) // (SYS) General Purpose Register
+// ========== Register definition for EBI peripheral ========== 
+#define AT91C_EBI_DUMMY (AT91_CAST(AT91_REG *) 	0xFFFFEA00) // (EBI) Dummy register - Do not use
+// ========== Register definition for HECC peripheral ========== 
+#define AT91C_HECC_VR   (AT91_CAST(AT91_REG *) 	0xFFFFE8FC) // (HECC)  ECC Version register
+#define AT91C_HECC_NPR  (AT91_CAST(AT91_REG *) 	0xFFFFE810) // (HECC)  ECC Parity N register
+#define AT91C_HECC_SR   (AT91_CAST(AT91_REG *) 	0xFFFFE808) // (HECC)  ECC Status register
+#define AT91C_HECC_PR   (AT91_CAST(AT91_REG *) 	0xFFFFE80C) // (HECC)  ECC Parity register
+#define AT91C_HECC_MR   (AT91_CAST(AT91_REG *) 	0xFFFFE804) // (HECC)  ECC Page size register
+#define AT91C_HECC_CR   (AT91_CAST(AT91_REG *) 	0xFFFFE800) // (HECC)  ECC reset register
+// ========== Register definition for SDRAMC peripheral ========== 
+#define AT91C_SDRAMC_MR (AT91_CAST(AT91_REG *) 	0xFFFFEA00) // (SDRAMC) SDRAM Controller Mode Register
+#define AT91C_SDRAMC_IMR (AT91_CAST(AT91_REG *) 	0xFFFFEA1C) // (SDRAMC) SDRAM Controller Interrupt Mask Register
+#define AT91C_SDRAMC_LPR (AT91_CAST(AT91_REG *) 	0xFFFFEA10) // (SDRAMC) SDRAM Controller Low Power Register
+#define AT91C_SDRAMC_ISR (AT91_CAST(AT91_REG *) 	0xFFFFEA20) // (SDRAMC) SDRAM Controller Interrupt Mask Register
+#define AT91C_SDRAMC_IDR (AT91_CAST(AT91_REG *) 	0xFFFFEA18) // (SDRAMC) SDRAM Controller Interrupt Disable Register
+#define AT91C_SDRAMC_CR (AT91_CAST(AT91_REG *) 	0xFFFFEA08) // (SDRAMC) SDRAM Controller Configuration Register
+#define AT91C_SDRAMC_TR (AT91_CAST(AT91_REG *) 	0xFFFFEA04) // (SDRAMC) SDRAM Controller Refresh Timer Register
+#define AT91C_SDRAMC_MDR (AT91_CAST(AT91_REG *) 	0xFFFFEA24) // (SDRAMC) SDRAM Memory Device Register
+#define AT91C_SDRAMC_HSR (AT91_CAST(AT91_REG *) 	0xFFFFEA0C) // (SDRAMC) SDRAM Controller High Speed Register
+#define AT91C_SDRAMC_IER (AT91_CAST(AT91_REG *) 	0xFFFFEA14) // (SDRAMC) SDRAM Controller Interrupt Enable Register
+// ========== Register definition for SMC peripheral ========== 
+#define AT91C_SMC_CTRL1 (AT91_CAST(AT91_REG *) 	0xFFFFEC1C) // (SMC)  Control Register for CS 1
+#define AT91C_SMC_PULSE7 (AT91_CAST(AT91_REG *) 	0xFFFFEC74) // (SMC)  Pulse Register for CS 7
+#define AT91C_SMC_PULSE6 (AT91_CAST(AT91_REG *) 	0xFFFFEC64) // (SMC)  Pulse Register for CS 6
+#define AT91C_SMC_SETUP4 (AT91_CAST(AT91_REG *) 	0xFFFFEC40) // (SMC)  Setup Register for CS 4
+#define AT91C_SMC_PULSE3 (AT91_CAST(AT91_REG *) 	0xFFFFEC34) // (SMC)  Pulse Register for CS 3
+#define AT91C_SMC_CYCLE5 (AT91_CAST(AT91_REG *) 	0xFFFFEC58) // (SMC)  Cycle Register for CS 5
+#define AT91C_SMC_CYCLE2 (AT91_CAST(AT91_REG *) 	0xFFFFEC28) // (SMC)  Cycle Register for CS 2
+#define AT91C_SMC_CTRL2 (AT91_CAST(AT91_REG *) 	0xFFFFEC2C) // (SMC)  Control Register for CS 2
+#define AT91C_SMC_CTRL0 (AT91_CAST(AT91_REG *) 	0xFFFFEC0C) // (SMC)  Control Register for CS 0
+#define AT91C_SMC_PULSE5 (AT91_CAST(AT91_REG *) 	0xFFFFEC54) // (SMC)  Pulse Register for CS 5
+#define AT91C_SMC_PULSE1 (AT91_CAST(AT91_REG *) 	0xFFFFEC14) // (SMC)  Pulse Register for CS 1
+#define AT91C_SMC_PULSE0 (AT91_CAST(AT91_REG *) 	0xFFFFEC04) // (SMC)  Pulse Register for CS 0
+#define AT91C_SMC_CYCLE7 (AT91_CAST(AT91_REG *) 	0xFFFFEC78) // (SMC)  Cycle Register for CS 7
+#define AT91C_SMC_CTRL4 (AT91_CAST(AT91_REG *) 	0xFFFFEC4C) // (SMC)  Control Register for CS 4
+#define AT91C_SMC_CTRL3 (AT91_CAST(AT91_REG *) 	0xFFFFEC3C) // (SMC)  Control Register for CS 3
+#define AT91C_SMC_SETUP7 (AT91_CAST(AT91_REG *) 	0xFFFFEC70) // (SMC)  Setup Register for CS 7
+#define AT91C_SMC_CTRL7 (AT91_CAST(AT91_REG *) 	0xFFFFEC7C) // (SMC)  Control Register for CS 7
+#define AT91C_SMC_SETUP1 (AT91_CAST(AT91_REG *) 	0xFFFFEC10) // (SMC)  Setup Register for CS 1
+#define AT91C_SMC_CYCLE0 (AT91_CAST(AT91_REG *) 	0xFFFFEC08) // (SMC)  Cycle Register for CS 0
+#define AT91C_SMC_CTRL5 (AT91_CAST(AT91_REG *) 	0xFFFFEC5C) // (SMC)  Control Register for CS 5
+#define AT91C_SMC_CYCLE1 (AT91_CAST(AT91_REG *) 	0xFFFFEC18) // (SMC)  Cycle Register for CS 1
+#define AT91C_SMC_CTRL6 (AT91_CAST(AT91_REG *) 	0xFFFFEC6C) // (SMC)  Control Register for CS 6
+#define AT91C_SMC_SETUP0 (AT91_CAST(AT91_REG *) 	0xFFFFEC00) // (SMC)  Setup Register for CS 0
+#define AT91C_SMC_PULSE4 (AT91_CAST(AT91_REG *) 	0xFFFFEC44) // (SMC)  Pulse Register for CS 4
+#define AT91C_SMC_SETUP5 (AT91_CAST(AT91_REG *) 	0xFFFFEC50) // (SMC)  Setup Register for CS 5
+#define AT91C_SMC_SETUP2 (AT91_CAST(AT91_REG *) 	0xFFFFEC20) // (SMC)  Setup Register for CS 2
+#define AT91C_SMC_CYCLE3 (AT91_CAST(AT91_REG *) 	0xFFFFEC38) // (SMC)  Cycle Register for CS 3
+#define AT91C_SMC_CYCLE6 (AT91_CAST(AT91_REG *) 	0xFFFFEC68) // (SMC)  Cycle Register for CS 6
+#define AT91C_SMC_SETUP6 (AT91_CAST(AT91_REG *) 	0xFFFFEC60) // (SMC)  Setup Register for CS 6
+#define AT91C_SMC_CYCLE4 (AT91_CAST(AT91_REG *) 	0xFFFFEC48) // (SMC)  Cycle Register for CS 4
+#define AT91C_SMC_PULSE2 (AT91_CAST(AT91_REG *) 	0xFFFFEC24) // (SMC)  Pulse Register for CS 2
+#define AT91C_SMC_SETUP3 (AT91_CAST(AT91_REG *) 	0xFFFFEC30) // (SMC)  Setup Register for CS 3
+// ========== Register definition for MATRIX peripheral ========== 
+#define AT91C_MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 	0xFFFFEE00) // (MATRIX)  Master Configuration Register 0 (ram96k)     
+#define AT91C_MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 	0xFFFFEE1C) // (MATRIX)  Master Configuration Register 7 (teak_prog)     
+#define AT91C_MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 	0xFFFFEE44) // (MATRIX)  Slave Configuration Register 1 (rom)    
+#define AT91C_MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 	0xFFFFEE10) // (MATRIX)  Master Configuration Register 4 (bridge)    
+#define AT91C_MATRIX_VERSION (AT91_CAST(AT91_REG *) 	0xFFFFEFFC) // (MATRIX)  Version Register
+#define AT91C_MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 	0xFFFFEE08) // (MATRIX)  Master Configuration Register 2 (hperiphs) 
+#define AT91C_MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 	0xFFFFEEA4) // (MATRIX)  PRBS4 : ebi
+#define AT91C_MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 	0xFFFFEE84) // (MATRIX)  PRBS0 (ram0) 
+#define AT91C_MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 	0xFFFFEE4C) // (MATRIX)  Slave Configuration Register 3 (ebi)
+#define AT91C_MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 	0xFFFFEE18) // (MATRIX)  Master Configuration Register 6 (ram16k)  
+#define AT91C_MATRIX_EBI (AT91_CAST(AT91_REG *) 	0xFFFFEF1C) // (MATRIX)  Slave 3 (ebi) Special Function Register
+#define AT91C_MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 	0xFFFFEE40) // (MATRIX)  Slave Configuration Register 0 (ram96k)     
+#define AT91C_MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 	0xFFFFEE9C) // (MATRIX)  PRBS3 : usb_dev_hs
+#define AT91C_MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 	0xFFFFEE98) // (MATRIX)  PRAS3 : usb_dev_hs
+#define AT91C_MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 	0xFFFFEE80) // (MATRIX)  PRAS0 (ram0) 
+#define AT91C_MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 	0xFFFFEE0C) // (MATRIX)  Master Configuration Register 3 (ebi)
+#define AT91C_MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 	0xFFFFEE88) // (MATRIX)  PRAS1 (ram1) 
+#define AT91C_MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 	0xFFFFEE90) // (MATRIX)  PRAS2 (ram2) 
+#define AT91C_MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 	0xFFFFEE48) // (MATRIX)  Slave Configuration Register 2 (hperiphs) 
+#define AT91C_MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 	0xFFFFEE14) // (MATRIX)  Master Configuration Register 5 (mailbox)    
+#define AT91C_MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 	0xFFFFEE04) // (MATRIX)  Master Configuration Register 1 (rom)    
+#define AT91C_MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 	0xFFFFEEA0) // (MATRIX)  PRAS4 : ebi
+#define AT91C_MATRIX_MRCR (AT91_CAST(AT91_REG *) 	0xFFFFEF00) // (MATRIX)  Master Remp Control Register 
+#define AT91C_MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 	0xFFFFEE94) // (MATRIX)  PRBS2 (ram2) 
+#define AT91C_MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 	0xFFFFEE50) // (MATRIX)  Slave Configuration Register 4 (bridge)    
+#define AT91C_MATRIX_TEAKCFG (AT91_CAST(AT91_REG *) 	0xFFFFEF2C) // (MATRIX)  Slave 7 (teak_prog) Special Function Register
+#define AT91C_MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 	0xFFFFEE8C) // (MATRIX)  PRBS1 (ram1) 
+// ========== Register definition for CCFG peripheral ========== 
+#define AT91C_CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 	0xFFFFEFFC) // (CCFG)  Version Register
+#define AT91C_CCFG_EBICSA (AT91_CAST(AT91_REG *) 	0xFFFFEF1C) // (CCFG)  EBI Chip Select Assignement Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_TCR  (AT91_CAST(AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR  (AT91_CAST(AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR  (AT91_CAST(AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR  (AT91_CAST(AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR  (AT91_CAST(AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR   (AT91_CAST(AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR   (AT91_CAST(AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR  (AT91_CAST(AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR  (AT91_CAST(AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_IVR   (AT91_CAST(AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR   (AT91_CAST(AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR   (AT91_CAST(AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR   (AT91_CAST(AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR   (AT91_CAST(AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR  (AT91_CAST(AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR  (AT91_CAST(AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR   (AT91_CAST(AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR   (AT91_CAST(AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER  (AT91_CAST(AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR  (AT91_CAST(AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR  (AT91_CAST(AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR  (AT91_CAST(AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR  (AT91_CAST(AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR  (AT91_CAST(AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU   (AT91_CAST(AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_ODR  (AT91_CAST(AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR  (AT91_CAST(AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER  (AT91_CAST(AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR  (AT91_CAST(AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR  (AT91_CAST(AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR  (AT91_CAST(AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR  (AT91_CAST(AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER  (AT91_CAST(AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR  (AT91_CAST(AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ========== 
+#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR  (AT91_CAST(AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR  (AT91_CAST(AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR  (AT91_CAST(AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR  (AT91_CAST(AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR  (AT91_CAST(AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR  (AT91_CAST(AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR  (AT91_CAST(AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER  (AT91_CAST(AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER  (AT91_CAST(AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for PIOC peripheral ========== 
+#define AT91C_PIOC_OWDR (AT91_CAST(AT91_REG *) 	0xFFFFF8A4) // (PIOC) Output Write Disable Register
+#define AT91C_PIOC_SODR (AT91_CAST(AT91_REG *) 	0xFFFFF830) // (PIOC) Set Output Data Register
+#define AT91C_PIOC_PPUER (AT91_CAST(AT91_REG *) 	0xFFFFF864) // (PIOC) Pull-up Enable Register
+#define AT91C_PIOC_CODR (AT91_CAST(AT91_REG *) 	0xFFFFF834) // (PIOC) Clear Output Data Register
+#define AT91C_PIOC_PSR  (AT91_CAST(AT91_REG *) 	0xFFFFF808) // (PIOC) PIO Status Register
+#define AT91C_PIOC_PDR  (AT91_CAST(AT91_REG *) 	0xFFFFF804) // (PIOC) PIO Disable Register
+#define AT91C_PIOC_ODR  (AT91_CAST(AT91_REG *) 	0xFFFFF814) // (PIOC) Output Disable Registerr
+#define AT91C_PIOC_PPUSR (AT91_CAST(AT91_REG *) 	0xFFFFF868) // (PIOC) Pull-up Status Register
+#define AT91C_PIOC_ABSR (AT91_CAST(AT91_REG *) 	0xFFFFF878) // (PIOC) AB Select Status Register
+#define AT91C_PIOC_IFSR (AT91_CAST(AT91_REG *) 	0xFFFFF828) // (PIOC) Input Filter Status Register
+#define AT91C_PIOC_OER  (AT91_CAST(AT91_REG *) 	0xFFFFF810) // (PIOC) Output Enable Register
+#define AT91C_PIOC_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF848) // (PIOC) Interrupt Mask Register
+#define AT91C_PIOC_ASR  (AT91_CAST(AT91_REG *) 	0xFFFFF870) // (PIOC) Select A Register
+#define AT91C_PIOC_MDDR (AT91_CAST(AT91_REG *) 	0xFFFFF854) // (PIOC) Multi-driver Disable Register
+#define AT91C_PIOC_OWSR (AT91_CAST(AT91_REG *) 	0xFFFFF8A8) // (PIOC) Output Write Status Register
+#define AT91C_PIOC_PER  (AT91_CAST(AT91_REG *) 	0xFFFFF800) // (PIOC) PIO Enable Register
+#define AT91C_PIOC_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF844) // (PIOC) Interrupt Disable Register
+#define AT91C_PIOC_MDER (AT91_CAST(AT91_REG *) 	0xFFFFF850) // (PIOC) Multi-driver Enable Register
+#define AT91C_PIOC_PDSR (AT91_CAST(AT91_REG *) 	0xFFFFF83C) // (PIOC) Pin Data Status Register
+#define AT91C_PIOC_MDSR (AT91_CAST(AT91_REG *) 	0xFFFFF858) // (PIOC) Multi-driver Status Register
+#define AT91C_PIOC_OWER (AT91_CAST(AT91_REG *) 	0xFFFFF8A0) // (PIOC) Output Write Enable Register
+#define AT91C_PIOC_BSR  (AT91_CAST(AT91_REG *) 	0xFFFFF874) // (PIOC) Select B Register
+#define AT91C_PIOC_PPUDR (AT91_CAST(AT91_REG *) 	0xFFFFF860) // (PIOC) Pull-up Disable Register
+#define AT91C_PIOC_IFDR (AT91_CAST(AT91_REG *) 	0xFFFFF824) // (PIOC) Input Filter Disable Register
+#define AT91C_PIOC_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF840) // (PIOC) Interrupt Enable Register
+#define AT91C_PIOC_OSR  (AT91_CAST(AT91_REG *) 	0xFFFFF818) // (PIOC) Output Status Register
+#define AT91C_PIOC_ODSR (AT91_CAST(AT91_REG *) 	0xFFFFF838) // (PIOC) Output Data Status Register
+#define AT91C_PIOC_ISR  (AT91_CAST(AT91_REG *) 	0xFFFFF84C) // (PIOC) Interrupt Status Register
+#define AT91C_PIOC_IFER (AT91_CAST(AT91_REG *) 	0xFFFFF820) // (PIOC) Input Filter Enable Register
+// ========== Register definition for EFC peripheral ========== 
+#define AT91C_EFC_FVR   (AT91_CAST(AT91_REG *) 	0xFFFFFA10) // (EFC) EFC Flash Version Register
+#define AT91C_EFC_FCR   (AT91_CAST(AT91_REG *) 	0xFFFFFA04) // (EFC) EFC Flash Command Register
+#define AT91C_EFC_FMR   (AT91_CAST(AT91_REG *) 	0xFFFFFA00) // (EFC) EFC Flash Mode Register
+#define AT91C_EFC_FRR   (AT91_CAST(AT91_REG *) 	0xFFFFFA0C) // (EFC) EFC Flash Result Register
+#define AT91C_EFC_FSR   (AT91_CAST(AT91_REG *) 	0xFFFFFA08) // (EFC) EFC Flash Status Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_MOR  (AT91_CAST(AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLBR (AT91_CAST(AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL B Register
+#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+#define AT91C_CKGR_PLLAR (AT91_CAST(AT91_REG *) 	0xFFFFFC28) // (CKGR) PLL A Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_PCER  (AT91_CAST(AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR  (AT91_CAST(AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR  (AT91_CAST(AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_PLLAR (AT91_CAST(AT91_REG *) 	0xFFFFFC28) // (PMC) PLL A Register
+#define AT91C_PMC_PCDR  (AT91_CAST(AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR  (AT91_CAST(AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_MCFR  (AT91_CAST(AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER   (AT91_CAST(AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_MOR   (AT91_CAST(AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_PLLBR (AT91_CAST(AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL B Register
+#define AT91C_PMC_SCDR  (AT91_CAST(AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCSR  (AT91_CAST(AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_SCER  (AT91_CAST(AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_SR    (AT91_CAST(AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RCR  (AT91_CAST(AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR  (AT91_CAST(AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR  (AT91_CAST(AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for SHDWC peripheral ========== 
+#define AT91C_SHDWC_SHSR (AT91_CAST(AT91_REG *) 	0xFFFFFD18) // (SHDWC) Shut Down Status Register
+#define AT91C_SHDWC_SHMR (AT91_CAST(AT91_REG *) 	0xFFFFFD14) // (SHDWC) Shut Down Mode Register
+#define AT91C_SHDWC_SHCR (AT91_CAST(AT91_REG *) 	0xFFFFFD10) // (SHDWC) Shut Down Control Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_SR    (AT91_CAST(AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC    (AT91_CAST(AT91_REG *) 	0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER   (AT91_CAST(AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER   (AT91_CAST(AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR    (AT91_CAST(AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC    (AT91_CAST(AT91_REG *) 	0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC    (AT91_CAST(AT91_REG *) 	0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER   (AT91_CAST(AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR    (AT91_CAST(AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TC3 peripheral ========== 
+#define AT91C_TC3_IER   (AT91_CAST(AT91_REG *) 	0xFFFDC024) // (TC3) Interrupt Enable Register
+#define AT91C_TC3_RB    (AT91_CAST(AT91_REG *) 	0xFFFDC018) // (TC3) Register B
+#define AT91C_TC3_CMR   (AT91_CAST(AT91_REG *) 	0xFFFDC004) // (TC3) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC3_RC    (AT91_CAST(AT91_REG *) 	0xFFFDC01C) // (TC3) Register C
+#define AT91C_TC3_CCR   (AT91_CAST(AT91_REG *) 	0xFFFDC000) // (TC3) Channel Control Register
+#define AT91C_TC3_SR    (AT91_CAST(AT91_REG *) 	0xFFFDC020) // (TC3) Status Register
+#define AT91C_TC3_CV    (AT91_CAST(AT91_REG *) 	0xFFFDC010) // (TC3) Counter Value
+#define AT91C_TC3_RA    (AT91_CAST(AT91_REG *) 	0xFFFDC014) // (TC3) Register A
+#define AT91C_TC3_IDR   (AT91_CAST(AT91_REG *) 	0xFFFDC028) // (TC3) Interrupt Disable Register
+#define AT91C_TC3_IMR   (AT91_CAST(AT91_REG *) 	0xFFFDC02C) // (TC3) Interrupt Mask Register
+// ========== Register definition for TC4 peripheral ========== 
+#define AT91C_TC4_CMR   (AT91_CAST(AT91_REG *) 	0xFFFDC044) // (TC4) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC4_RC    (AT91_CAST(AT91_REG *) 	0xFFFDC05C) // (TC4) Register C
+#define AT91C_TC4_SR    (AT91_CAST(AT91_REG *) 	0xFFFDC060) // (TC4) Status Register
+#define AT91C_TC4_RB    (AT91_CAST(AT91_REG *) 	0xFFFDC058) // (TC4) Register B
+#define AT91C_TC4_IER   (AT91_CAST(AT91_REG *) 	0xFFFDC064) // (TC4) Interrupt Enable Register
+#define AT91C_TC4_CV    (AT91_CAST(AT91_REG *) 	0xFFFDC050) // (TC4) Counter Value
+#define AT91C_TC4_RA    (AT91_CAST(AT91_REG *) 	0xFFFDC054) // (TC4) Register A
+#define AT91C_TC4_IDR   (AT91_CAST(AT91_REG *) 	0xFFFDC068) // (TC4) Interrupt Disable Register
+#define AT91C_TC4_IMR   (AT91_CAST(AT91_REG *) 	0xFFFDC06C) // (TC4) Interrupt Mask Register
+#define AT91C_TC4_CCR   (AT91_CAST(AT91_REG *) 	0xFFFDC040) // (TC4) Channel Control Register
+// ========== Register definition for TC5 peripheral ========== 
+#define AT91C_TC5_RB    (AT91_CAST(AT91_REG *) 	0xFFFDC098) // (TC5) Register B
+#define AT91C_TC5_RA    (AT91_CAST(AT91_REG *) 	0xFFFDC094) // (TC5) Register A
+#define AT91C_TC5_CV    (AT91_CAST(AT91_REG *) 	0xFFFDC090) // (TC5) Counter Value
+#define AT91C_TC5_CCR   (AT91_CAST(AT91_REG *) 	0xFFFDC080) // (TC5) Channel Control Register
+#define AT91C_TC5_SR    (AT91_CAST(AT91_REG *) 	0xFFFDC0A0) // (TC5) Status Register
+#define AT91C_TC5_IER   (AT91_CAST(AT91_REG *) 	0xFFFDC0A4) // (TC5) Interrupt Enable Register
+#define AT91C_TC5_IDR   (AT91_CAST(AT91_REG *) 	0xFFFDC0A8) // (TC5) Interrupt Disable Register
+#define AT91C_TC5_RC    (AT91_CAST(AT91_REG *) 	0xFFFDC09C) // (TC5) Register C
+#define AT91C_TC5_IMR   (AT91_CAST(AT91_REG *) 	0xFFFDC0AC) // (TC5) Interrupt Mask Register
+#define AT91C_TC5_CMR   (AT91_CAST(AT91_REG *) 	0xFFFDC084) // (TC5) Channel Mode Register (Capture Mode / Waveform Mode)
+// ========== Register definition for TCB0 peripheral ========== 
+#define AT91C_TCB0_BMR  (AT91_CAST(AT91_REG *) 	0xFFFA00C4) // (TCB0) TC Block Mode Register
+#define AT91C_TCB0_BCR  (AT91_CAST(AT91_REG *) 	0xFFFA00C0) // (TCB0) TC Block Control Register
+// ========== Register definition for TCB1 peripheral ========== 
+#define AT91C_TCB1_BCR  (AT91_CAST(AT91_REG *) 	0xFFFDC0C0) // (TCB1) TC Block Control Register
+#define AT91C_TCB1_BMR  (AT91_CAST(AT91_REG *) 	0xFFFDC0C4) // (TCB1) TC Block Mode Register
+// ========== Register definition for PDC_MCI peripheral ========== 
+#define AT91C_MCI_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFA8114) // (PDC_MCI) Receive Next Counter Register
+#define AT91C_MCI_TCR   (AT91_CAST(AT91_REG *) 	0xFFFA810C) // (PDC_MCI) Transmit Counter Register
+#define AT91C_MCI_RCR   (AT91_CAST(AT91_REG *) 	0xFFFA8104) // (PDC_MCI) Receive Counter Register
+#define AT91C_MCI_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFA8118) // (PDC_MCI) Transmit Next Pointer Register
+#define AT91C_MCI_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFA8110) // (PDC_MCI) Receive Next Pointer Register
+#define AT91C_MCI_RPR   (AT91_CAST(AT91_REG *) 	0xFFFA8100) // (PDC_MCI) Receive Pointer Register
+#define AT91C_MCI_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFA811C) // (PDC_MCI) Transmit Next Counter Register
+#define AT91C_MCI_TPR   (AT91_CAST(AT91_REG *) 	0xFFFA8108) // (PDC_MCI) Transmit Pointer Register
+#define AT91C_MCI_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFA8124) // (PDC_MCI) PDC Transfer Status Register
+#define AT91C_MCI_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFA8120) // (PDC_MCI) PDC Transfer Control Register
+// ========== Register definition for MCI peripheral ========== 
+#define AT91C_MCI_RDR   (AT91_CAST(AT91_REG *) 	0xFFFA8030) // (MCI) MCI Receive Data Register
+#define AT91C_MCI_CMDR  (AT91_CAST(AT91_REG *) 	0xFFFA8014) // (MCI) MCI Command Register
+#define AT91C_MCI_VR    (AT91_CAST(AT91_REG *) 	0xFFFA80FC) // (MCI) MCI Version Register
+#define AT91C_MCI_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA8048) // (MCI) MCI Interrupt Disable Register
+#define AT91C_MCI_DTOR  (AT91_CAST(AT91_REG *) 	0xFFFA8008) // (MCI) MCI Data Timeout Register
+#define AT91C_MCI_TDR   (AT91_CAST(AT91_REG *) 	0xFFFA8034) // (MCI) MCI Transmit Data Register
+#define AT91C_MCI_IER   (AT91_CAST(AT91_REG *) 	0xFFFA8044) // (MCI) MCI Interrupt Enable Register
+#define AT91C_MCI_BLKR  (AT91_CAST(AT91_REG *) 	0xFFFA8018) // (MCI) MCI Block Register
+#define AT91C_MCI_MR    (AT91_CAST(AT91_REG *) 	0xFFFA8004) // (MCI) MCI Mode Register
+#define AT91C_MCI_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA804C) // (MCI) MCI Interrupt Mask Register
+#define AT91C_MCI_CR    (AT91_CAST(AT91_REG *) 	0xFFFA8000) // (MCI) MCI Control Register
+#define AT91C_MCI_ARGR  (AT91_CAST(AT91_REG *) 	0xFFFA8010) // (MCI) MCI Argument Register
+#define AT91C_MCI_SDCR  (AT91_CAST(AT91_REG *) 	0xFFFA800C) // (MCI) MCI SD Card Register
+#define AT91C_MCI_SR    (AT91_CAST(AT91_REG *) 	0xFFFA8040) // (MCI) MCI Status Register
+#define AT91C_MCI_RSPR  (AT91_CAST(AT91_REG *) 	0xFFFA8020) // (MCI) MCI Response Register
+// ========== Register definition for PDC_TWI0 peripheral ========== 
+#define AT91C_TWI0_PTSR (AT91_CAST(AT91_REG *) 	0xFFFAC124) // (PDC_TWI0) PDC Transfer Status Register
+#define AT91C_TWI0_RPR  (AT91_CAST(AT91_REG *) 	0xFFFAC100) // (PDC_TWI0) Receive Pointer Register
+#define AT91C_TWI0_RNCR (AT91_CAST(AT91_REG *) 	0xFFFAC114) // (PDC_TWI0) Receive Next Counter Register
+#define AT91C_TWI0_RCR  (AT91_CAST(AT91_REG *) 	0xFFFAC104) // (PDC_TWI0) Receive Counter Register
+#define AT91C_TWI0_PTCR (AT91_CAST(AT91_REG *) 	0xFFFAC120) // (PDC_TWI0) PDC Transfer Control Register
+#define AT91C_TWI0_TPR  (AT91_CAST(AT91_REG *) 	0xFFFAC108) // (PDC_TWI0) Transmit Pointer Register
+#define AT91C_TWI0_RNPR (AT91_CAST(AT91_REG *) 	0xFFFAC110) // (PDC_TWI0) Receive Next Pointer Register
+#define AT91C_TWI0_TNPR (AT91_CAST(AT91_REG *) 	0xFFFAC118) // (PDC_TWI0) Transmit Next Pointer Register
+#define AT91C_TWI0_TCR  (AT91_CAST(AT91_REG *) 	0xFFFAC10C) // (PDC_TWI0) Transmit Counter Register
+#define AT91C_TWI0_TNCR (AT91_CAST(AT91_REG *) 	0xFFFAC11C) // (PDC_TWI0) Transmit Next Counter Register
+// ========== Register definition for TWI0 peripheral ========== 
+#define AT91C_TWI0_THR  (AT91_CAST(AT91_REG *) 	0xFFFAC034) // (TWI0) Transmit Holding Register
+#define AT91C_TWI0_IDR  (AT91_CAST(AT91_REG *) 	0xFFFAC028) // (TWI0) Interrupt Disable Register
+#define AT91C_TWI0_SMR  (AT91_CAST(AT91_REG *) 	0xFFFAC008) // (TWI0) Slave Mode Register
+#define AT91C_TWI0_CWGR (AT91_CAST(AT91_REG *) 	0xFFFAC010) // (TWI0) Clock Waveform Generator Register
+#define AT91C_TWI0_IADR (AT91_CAST(AT91_REG *) 	0xFFFAC00C) // (TWI0) Internal Address Register
+#define AT91C_TWI0_RHR  (AT91_CAST(AT91_REG *) 	0xFFFAC030) // (TWI0) Receive Holding Register
+#define AT91C_TWI0_IER  (AT91_CAST(AT91_REG *) 	0xFFFAC024) // (TWI0) Interrupt Enable Register
+#define AT91C_TWI0_MMR  (AT91_CAST(AT91_REG *) 	0xFFFAC004) // (TWI0) Master Mode Register
+#define AT91C_TWI0_SR   (AT91_CAST(AT91_REG *) 	0xFFFAC020) // (TWI0) Status Register
+#define AT91C_TWI0_IMR  (AT91_CAST(AT91_REG *) 	0xFFFAC02C) // (TWI0) Interrupt Mask Register
+#define AT91C_TWI0_CR   (AT91_CAST(AT91_REG *) 	0xFFFAC000) // (TWI0) Control Register
+// ========== Register definition for PDC_TWI1 peripheral ========== 
+#define AT91C_TWI1_PTSR (AT91_CAST(AT91_REG *) 	0xFFFD8124) // (PDC_TWI1) PDC Transfer Status Register
+#define AT91C_TWI1_PTCR (AT91_CAST(AT91_REG *) 	0xFFFD8120) // (PDC_TWI1) PDC Transfer Control Register
+#define AT91C_TWI1_TNPR (AT91_CAST(AT91_REG *) 	0xFFFD8118) // (PDC_TWI1) Transmit Next Pointer Register
+#define AT91C_TWI1_TNCR (AT91_CAST(AT91_REG *) 	0xFFFD811C) // (PDC_TWI1) Transmit Next Counter Register
+#define AT91C_TWI1_RNPR (AT91_CAST(AT91_REG *) 	0xFFFD8110) // (PDC_TWI1) Receive Next Pointer Register
+#define AT91C_TWI1_RNCR (AT91_CAST(AT91_REG *) 	0xFFFD8114) // (PDC_TWI1) Receive Next Counter Register
+#define AT91C_TWI1_RPR  (AT91_CAST(AT91_REG *) 	0xFFFD8100) // (PDC_TWI1) Receive Pointer Register
+#define AT91C_TWI1_TCR  (AT91_CAST(AT91_REG *) 	0xFFFD810C) // (PDC_TWI1) Transmit Counter Register
+#define AT91C_TWI1_TPR  (AT91_CAST(AT91_REG *) 	0xFFFD8108) // (PDC_TWI1) Transmit Pointer Register
+#define AT91C_TWI1_RCR  (AT91_CAST(AT91_REG *) 	0xFFFD8104) // (PDC_TWI1) Receive Counter Register
+// ========== Register definition for TWI1 peripheral ========== 
+#define AT91C_TWI1_RHR  (AT91_CAST(AT91_REG *) 	0xFFFD8030) // (TWI1) Receive Holding Register
+#define AT91C_TWI1_IER  (AT91_CAST(AT91_REG *) 	0xFFFD8024) // (TWI1) Interrupt Enable Register
+#define AT91C_TWI1_CWGR (AT91_CAST(AT91_REG *) 	0xFFFD8010) // (TWI1) Clock Waveform Generator Register
+#define AT91C_TWI1_MMR  (AT91_CAST(AT91_REG *) 	0xFFFD8004) // (TWI1) Master Mode Register
+#define AT91C_TWI1_IADR (AT91_CAST(AT91_REG *) 	0xFFFD800C) // (TWI1) Internal Address Register
+#define AT91C_TWI1_THR  (AT91_CAST(AT91_REG *) 	0xFFFD8034) // (TWI1) Transmit Holding Register
+#define AT91C_TWI1_IMR  (AT91_CAST(AT91_REG *) 	0xFFFD802C) // (TWI1) Interrupt Mask Register
+#define AT91C_TWI1_SR   (AT91_CAST(AT91_REG *) 	0xFFFD8020) // (TWI1) Status Register
+#define AT91C_TWI1_IDR  (AT91_CAST(AT91_REG *) 	0xFFFD8028) // (TWI1) Interrupt Disable Register
+#define AT91C_TWI1_CR   (AT91_CAST(AT91_REG *) 	0xFFFD8000) // (TWI1) Control Register
+#define AT91C_TWI1_SMR  (AT91_CAST(AT91_REG *) 	0xFFFD8008) // (TWI1) Slave Mode Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_TCR   (AT91_CAST(AT91_REG *) 	0xFFFB010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFB0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFB0114) // (PDC_US0) Receive Next Counter Register
+#define AT91C_US0_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFB0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFB011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFB0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_RCR   (AT91_CAST(AT91_REG *) 	0xFFFB0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_TPR   (AT91_CAST(AT91_REG *) 	0xFFFB0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFB0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RPR   (AT91_CAST(AT91_REG *) 	0xFFFB0100) // (PDC_US0) Receive Pointer Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_RHR   (AT91_CAST(AT91_REG *) 	0xFFFB0018) // (US0) Receiver Holding Register
+#define AT91C_US0_NER   (AT91_CAST(AT91_REG *) 	0xFFFB0044) // (US0) Nb Errors Register
+#define AT91C_US0_IER   (AT91_CAST(AT91_REG *) 	0xFFFB0008) // (US0) Interrupt Enable Register
+#define AT91C_US0_CR    (AT91_CAST(AT91_REG *) 	0xFFFB0000) // (US0) Control Register
+#define AT91C_US0_THR   (AT91_CAST(AT91_REG *) 	0xFFFB001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_CSR   (AT91_CAST(AT91_REG *) 	0xFFFB0014) // (US0) Channel Status Register
+#define AT91C_US0_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFB0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFB0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFB0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_MR    (AT91_CAST(AT91_REG *) 	0xFFFB0004) // (US0) Mode Register
+#define AT91C_US0_IF    (AT91_CAST(AT91_REG *) 	0xFFFB004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFB0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB0010) // (US0) Interrupt Mask Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFB4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_RCR   (AT91_CAST(AT91_REG *) 	0xFFFB4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RPR   (AT91_CAST(AT91_REG *) 	0xFFFB4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFB4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TPR   (AT91_CAST(AT91_REG *) 	0xFFFB4108) // (PDC_US1) Transmit Pointer Register
+#define AT91C_US1_TCR   (AT91_CAST(AT91_REG *) 	0xFFFB410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFB4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFB411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFB4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFB4118) // (PDC_US1) Transmit Next Pointer Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_THR   (AT91_CAST(AT91_REG *) 	0xFFFB401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFB4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFB4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_MR    (AT91_CAST(AT91_REG *) 	0xFFFB4004) // (US1) Mode Register
+#define AT91C_US1_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFB4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CR    (AT91_CAST(AT91_REG *) 	0xFFFB4000) // (US1) Control Register
+#define AT91C_US1_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFB4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_RHR   (AT91_CAST(AT91_REG *) 	0xFFFB4018) // (US1) Receiver Holding Register
+#define AT91C_US1_IER   (AT91_CAST(AT91_REG *) 	0xFFFB4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_CSR   (AT91_CAST(AT91_REG *) 	0xFFFB4014) // (US1) Channel Status Register
+#define AT91C_US1_IF    (AT91_CAST(AT91_REG *) 	0xFFFB404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER   (AT91_CAST(AT91_REG *) 	0xFFFB4044) // (US1) Nb Errors Register
+// ========== Register definition for PDC_US2 peripheral ========== 
+#define AT91C_US2_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFB811C) // (PDC_US2) Transmit Next Counter Register
+#define AT91C_US2_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFB8114) // (PDC_US2) Receive Next Counter Register
+#define AT91C_US2_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFB8118) // (PDC_US2) Transmit Next Pointer Register
+#define AT91C_US2_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFB8120) // (PDC_US2) PDC Transfer Control Register
+#define AT91C_US2_TCR   (AT91_CAST(AT91_REG *) 	0xFFFB810C) // (PDC_US2) Transmit Counter Register
+#define AT91C_US2_RPR   (AT91_CAST(AT91_REG *) 	0xFFFB8100) // (PDC_US2) Receive Pointer Register
+#define AT91C_US2_TPR   (AT91_CAST(AT91_REG *) 	0xFFFB8108) // (PDC_US2) Transmit Pointer Register
+#define AT91C_US2_RCR   (AT91_CAST(AT91_REG *) 	0xFFFB8104) // (PDC_US2) Receive Counter Register
+#define AT91C_US2_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFB8124) // (PDC_US2) PDC Transfer Status Register
+#define AT91C_US2_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFB8110) // (PDC_US2) Receive Next Pointer Register
+// ========== Register definition for US2 peripheral ========== 
+#define AT91C_US2_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFB8024) // (US2) Receiver Time-out Register
+#define AT91C_US2_CSR   (AT91_CAST(AT91_REG *) 	0xFFFB8014) // (US2) Channel Status Register
+#define AT91C_US2_CR    (AT91_CAST(AT91_REG *) 	0xFFFB8000) // (US2) Control Register
+#define AT91C_US2_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFB8020) // (US2) Baud Rate Generator Register
+#define AT91C_US2_NER   (AT91_CAST(AT91_REG *) 	0xFFFB8044) // (US2) Nb Errors Register
+#define AT91C_US2_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFB8040) // (US2) FI_DI_Ratio Register
+#define AT91C_US2_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFB8028) // (US2) Transmitter Time-guard Register
+#define AT91C_US2_RHR   (AT91_CAST(AT91_REG *) 	0xFFFB8018) // (US2) Receiver Holding Register
+#define AT91C_US2_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB800C) // (US2) Interrupt Disable Register
+#define AT91C_US2_THR   (AT91_CAST(AT91_REG *) 	0xFFFB801C) // (US2) Transmitter Holding Register
+#define AT91C_US2_MR    (AT91_CAST(AT91_REG *) 	0xFFFB8004) // (US2) Mode Register
+#define AT91C_US2_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB8010) // (US2) Interrupt Mask Register
+#define AT91C_US2_IF    (AT91_CAST(AT91_REG *) 	0xFFFB804C) // (US2) IRDA_FILTER Register
+#define AT91C_US2_IER   (AT91_CAST(AT91_REG *) 	0xFFFB8008) // (US2) Interrupt Enable Register
+// ========== Register definition for PDC_US3 peripheral ========== 
+#define AT91C_US3_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFD0110) // (PDC_US3) Receive Next Pointer Register
+#define AT91C_US3_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFD0114) // (PDC_US3) Receive Next Counter Register
+#define AT91C_US3_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFD0124) // (PDC_US3) PDC Transfer Status Register
+#define AT91C_US3_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFD0120) // (PDC_US3) PDC Transfer Control Register
+#define AT91C_US3_TCR   (AT91_CAST(AT91_REG *) 	0xFFFD010C) // (PDC_US3) Transmit Counter Register
+#define AT91C_US3_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFD0118) // (PDC_US3) Transmit Next Pointer Register
+#define AT91C_US3_RCR   (AT91_CAST(AT91_REG *) 	0xFFFD0104) // (PDC_US3) Receive Counter Register
+#define AT91C_US3_TPR   (AT91_CAST(AT91_REG *) 	0xFFFD0108) // (PDC_US3) Transmit Pointer Register
+#define AT91C_US3_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFD011C) // (PDC_US3) Transmit Next Counter Register
+#define AT91C_US3_RPR   (AT91_CAST(AT91_REG *) 	0xFFFD0100) // (PDC_US3) Receive Pointer Register
+// ========== Register definition for US3 peripheral ========== 
+#define AT91C_US3_NER   (AT91_CAST(AT91_REG *) 	0xFFFD0044) // (US3) Nb Errors Register
+#define AT91C_US3_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFD0024) // (US3) Receiver Time-out Register
+#define AT91C_US3_IDR   (AT91_CAST(AT91_REG *) 	0xFFFD000C) // (US3) Interrupt Disable Register
+#define AT91C_US3_MR    (AT91_CAST(AT91_REG *) 	0xFFFD0004) // (US3) Mode Register
+#define AT91C_US3_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFD0040) // (US3) FI_DI_Ratio Register
+#define AT91C_US3_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFD0020) // (US3) Baud Rate Generator Register
+#define AT91C_US3_THR   (AT91_CAST(AT91_REG *) 	0xFFFD001C) // (US3) Transmitter Holding Register
+#define AT91C_US3_CR    (AT91_CAST(AT91_REG *) 	0xFFFD0000) // (US3) Control Register
+#define AT91C_US3_IF    (AT91_CAST(AT91_REG *) 	0xFFFD004C) // (US3) IRDA_FILTER Register
+#define AT91C_US3_IER   (AT91_CAST(AT91_REG *) 	0xFFFD0008) // (US3) Interrupt Enable Register
+#define AT91C_US3_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFD0028) // (US3) Transmitter Time-guard Register
+#define AT91C_US3_RHR   (AT91_CAST(AT91_REG *) 	0xFFFD0018) // (US3) Receiver Holding Register
+#define AT91C_US3_IMR   (AT91_CAST(AT91_REG *) 	0xFFFD0010) // (US3) Interrupt Mask Register
+#define AT91C_US3_CSR   (AT91_CAST(AT91_REG *) 	0xFFFD0014) // (US3) Channel Status Register
+// ========== Register definition for PDC_US4 peripheral ========== 
+#define AT91C_US4_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFD411C) // (PDC_US4) Transmit Next Counter Register
+#define AT91C_US4_RPR   (AT91_CAST(AT91_REG *) 	0xFFFD4100) // (PDC_US4) Receive Pointer Register
+#define AT91C_US4_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFD4114) // (PDC_US4) Receive Next Counter Register
+#define AT91C_US4_TPR   (AT91_CAST(AT91_REG *) 	0xFFFD4108) // (PDC_US4) Transmit Pointer Register
+#define AT91C_US4_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFD4120) // (PDC_US4) PDC Transfer Control Register
+#define AT91C_US4_TCR   (AT91_CAST(AT91_REG *) 	0xFFFD410C) // (PDC_US4) Transmit Counter Register
+#define AT91C_US4_RCR   (AT91_CAST(AT91_REG *) 	0xFFFD4104) // (PDC_US4) Receive Counter Register
+#define AT91C_US4_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFD4110) // (PDC_US4) Receive Next Pointer Register
+#define AT91C_US4_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFD4118) // (PDC_US4) Transmit Next Pointer Register
+#define AT91C_US4_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFD4124) // (PDC_US4) PDC Transfer Status Register
+// ========== Register definition for US4 peripheral ========== 
+#define AT91C_US4_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFD4020) // (US4) Baud Rate Generator Register
+#define AT91C_US4_THR   (AT91_CAST(AT91_REG *) 	0xFFFD401C) // (US4) Transmitter Holding Register
+#define AT91C_US4_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFD4024) // (US4) Receiver Time-out Register
+#define AT91C_US4_IMR   (AT91_CAST(AT91_REG *) 	0xFFFD4010) // (US4) Interrupt Mask Register
+#define AT91C_US4_NER   (AT91_CAST(AT91_REG *) 	0xFFFD4044) // (US4) Nb Errors Register
+#define AT91C_US4_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFD4028) // (US4) Transmitter Time-guard Register
+#define AT91C_US4_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFD4040) // (US4) FI_DI_Ratio Register
+#define AT91C_US4_MR    (AT91_CAST(AT91_REG *) 	0xFFFD4004) // (US4) Mode Register
+#define AT91C_US4_IER   (AT91_CAST(AT91_REG *) 	0xFFFD4008) // (US4) Interrupt Enable Register
+#define AT91C_US4_RHR   (AT91_CAST(AT91_REG *) 	0xFFFD4018) // (US4) Receiver Holding Register
+#define AT91C_US4_CR    (AT91_CAST(AT91_REG *) 	0xFFFD4000) // (US4) Control Register
+#define AT91C_US4_IF    (AT91_CAST(AT91_REG *) 	0xFFFD404C) // (US4) IRDA_FILTER Register
+#define AT91C_US4_IDR   (AT91_CAST(AT91_REG *) 	0xFFFD400C) // (US4) Interrupt Disable Register
+#define AT91C_US4_CSR   (AT91_CAST(AT91_REG *) 	0xFFFD4014) // (US4) Channel Status Register
+// ========== Register definition for PDC_SSC0 peripheral ========== 
+#define AT91C_SSC0_TNPR (AT91_CAST(AT91_REG *) 	0xFFFBC118) // (PDC_SSC0) Transmit Next Pointer Register
+#define AT91C_SSC0_TCR  (AT91_CAST(AT91_REG *) 	0xFFFBC10C) // (PDC_SSC0) Transmit Counter Register
+#define AT91C_SSC0_RNCR (AT91_CAST(AT91_REG *) 	0xFFFBC114) // (PDC_SSC0) Receive Next Counter Register
+#define AT91C_SSC0_RPR  (AT91_CAST(AT91_REG *) 	0xFFFBC100) // (PDC_SSC0) Receive Pointer Register
+#define AT91C_SSC0_TPR  (AT91_CAST(AT91_REG *) 	0xFFFBC108) // (PDC_SSC0) Transmit Pointer Register
+#define AT91C_SSC0_RCR  (AT91_CAST(AT91_REG *) 	0xFFFBC104) // (PDC_SSC0) Receive Counter Register
+#define AT91C_SSC0_RNPR (AT91_CAST(AT91_REG *) 	0xFFFBC110) // (PDC_SSC0) Receive Next Pointer Register
+#define AT91C_SSC0_PTCR (AT91_CAST(AT91_REG *) 	0xFFFBC120) // (PDC_SSC0) PDC Transfer Control Register
+#define AT91C_SSC0_TNCR (AT91_CAST(AT91_REG *) 	0xFFFBC11C) // (PDC_SSC0) Transmit Next Counter Register
+#define AT91C_SSC0_PTSR (AT91_CAST(AT91_REG *) 	0xFFFBC124) // (PDC_SSC0) PDC Transfer Status Register
+// ========== Register definition for SSC0 peripheral ========== 
+#define AT91C_SSC0_IMR  (AT91_CAST(AT91_REG *) 	0xFFFBC04C) // (SSC0) Interrupt Mask Register
+#define AT91C_SSC0_RFMR (AT91_CAST(AT91_REG *) 	0xFFFBC014) // (SSC0) Receive Frame Mode Register
+#define AT91C_SSC0_CR   (AT91_CAST(AT91_REG *) 	0xFFFBC000) // (SSC0) Control Register
+#define AT91C_SSC0_TFMR (AT91_CAST(AT91_REG *) 	0xFFFBC01C) // (SSC0) Transmit Frame Mode Register
+#define AT91C_SSC0_CMR  (AT91_CAST(AT91_REG *) 	0xFFFBC004) // (SSC0) Clock Mode Register
+#define AT91C_SSC0_IER  (AT91_CAST(AT91_REG *) 	0xFFFBC044) // (SSC0) Interrupt Enable Register
+#define AT91C_SSC0_RHR  (AT91_CAST(AT91_REG *) 	0xFFFBC020) // (SSC0) Receive Holding Register
+#define AT91C_SSC0_RCMR (AT91_CAST(AT91_REG *) 	0xFFFBC010) // (SSC0) Receive Clock ModeRegister
+#define AT91C_SSC0_SR   (AT91_CAST(AT91_REG *) 	0xFFFBC040) // (SSC0) Status Register
+#define AT91C_SSC0_RSHR (AT91_CAST(AT91_REG *) 	0xFFFBC030) // (SSC0) Receive Sync Holding Register
+#define AT91C_SSC0_THR  (AT91_CAST(AT91_REG *) 	0xFFFBC024) // (SSC0) Transmit Holding Register
+#define AT91C_SSC0_TCMR (AT91_CAST(AT91_REG *) 	0xFFFBC018) // (SSC0) Transmit Clock Mode Register
+#define AT91C_SSC0_IDR  (AT91_CAST(AT91_REG *) 	0xFFFBC048) // (SSC0) Interrupt Disable Register
+#define AT91C_SSC0_TSHR (AT91_CAST(AT91_REG *) 	0xFFFBC034) // (SSC0) Transmit Sync Holding Register
+// ========== Register definition for PDC_SPI0 peripheral ========== 
+#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 	0xFFFC8120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TCR  (AT91_CAST(AT91_REG *) 	0xFFFC810C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RPR  (AT91_CAST(AT91_REG *) 	0xFFFC8100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TPR  (AT91_CAST(AT91_REG *) 	0xFFFC8108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 	0xFFFC8124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 	0xFFFC8114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 	0xFFFC8118) // (PDC_SPI0) Transmit Next Pointer Register
+#define AT91C_SPI0_RCR  (AT91_CAST(AT91_REG *) 	0xFFFC8104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 	0xFFFC8110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 	0xFFFC811C) // (PDC_SPI0) Transmit Next Counter Register
+// ========== Register definition for SPI0 peripheral ========== 
+#define AT91C_SPI0_IDR  (AT91_CAST(AT91_REG *) 	0xFFFC8018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_TDR  (AT91_CAST(AT91_REG *) 	0xFFFC800C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_SR   (AT91_CAST(AT91_REG *) 	0xFFFC8010) // (SPI0) Status Register
+#define AT91C_SPI0_CR   (AT91_CAST(AT91_REG *) 	0xFFFC8000) // (SPI0) Control Register
+#define AT91C_SPI0_CSR  (AT91_CAST(AT91_REG *) 	0xFFFC8030) // (SPI0) Chip Select Register
+#define AT91C_SPI0_RDR  (AT91_CAST(AT91_REG *) 	0xFFFC8008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_MR   (AT91_CAST(AT91_REG *) 	0xFFFC8004) // (SPI0) Mode Register
+#define AT91C_SPI0_IER  (AT91_CAST(AT91_REG *) 	0xFFFC8014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_IMR  (AT91_CAST(AT91_REG *) 	0xFFFC801C) // (SPI0) Interrupt Mask Register
+// ========== Register definition for PDC_SPI1 peripheral ========== 
+#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 	0xFFFCC120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 	0xFFFCC110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RCR  (AT91_CAST(AT91_REG *) 	0xFFFCC104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_TPR  (AT91_CAST(AT91_REG *) 	0xFFFCC108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 	0xFFFCC124) // (PDC_SPI1) PDC Transfer Status Register
+#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 	0xFFFCC11C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_RPR  (AT91_CAST(AT91_REG *) 	0xFFFCC100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TCR  (AT91_CAST(AT91_REG *) 	0xFFFCC10C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 	0xFFFCC114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 	0xFFFCC118) // (PDC_SPI1) Transmit Next Pointer Register
+// ========== Register definition for SPI1 peripheral ========== 
+#define AT91C_SPI1_IER  (AT91_CAST(AT91_REG *) 	0xFFFCC014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_RDR  (AT91_CAST(AT91_REG *) 	0xFFFCC008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_SR   (AT91_CAST(AT91_REG *) 	0xFFFCC010) // (SPI1) Status Register
+#define AT91C_SPI1_IMR  (AT91_CAST(AT91_REG *) 	0xFFFCC01C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_TDR  (AT91_CAST(AT91_REG *) 	0xFFFCC00C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_IDR  (AT91_CAST(AT91_REG *) 	0xFFFCC018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_CSR  (AT91_CAST(AT91_REG *) 	0xFFFCC030) // (SPI1) Chip Select Register
+#define AT91C_SPI1_CR   (AT91_CAST(AT91_REG *) 	0xFFFCC000) // (SPI1) Control Register
+#define AT91C_SPI1_MR   (AT91_CAST(AT91_REG *) 	0xFFFCC004) // (SPI1) Mode Register
+// ========== Register definition for PDC_ADC peripheral ========== 
+#define AT91C_ADC_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFE0120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TPR   (AT91_CAST(AT91_REG *) 	0xFFFE0108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_TCR   (AT91_CAST(AT91_REG *) 	0xFFFE010C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_RCR   (AT91_CAST(AT91_REG *) 	0xFFFE0104) // (PDC_ADC) Receive Counter Register
+#define AT91C_ADC_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFE0124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFE0110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RPR   (AT91_CAST(AT91_REG *) 	0xFFFE0100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFE011C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFE0114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFE0118) // (PDC_ADC) Transmit Next Pointer Register
+// ========== Register definition for ADC peripheral ========== 
+#define AT91C_ADC_CHDR  (AT91_CAST(AT91_REG *) 	0xFFFE0014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_CDR3  (AT91_CAST(AT91_REG *) 	0xFFFE003C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CR    (AT91_CAST(AT91_REG *) 	0xFFFE0000) // (ADC) ADC Control Register
+#define AT91C_ADC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFE002C) // (ADC) ADC Interrupt Mask Register
+#define AT91C_ADC_CDR2  (AT91_CAST(AT91_REG *) 	0xFFFE0038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_SR    (AT91_CAST(AT91_REG *) 	0xFFFE001C) // (ADC) ADC Status Register
+#define AT91C_ADC_IER   (AT91_CAST(AT91_REG *) 	0xFFFE0024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CDR7  (AT91_CAST(AT91_REG *) 	0xFFFE004C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR0  (AT91_CAST(AT91_REG *) 	0xFFFE0030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5  (AT91_CAST(AT91_REG *) 	0xFFFE0044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CDR4  (AT91_CAST(AT91_REG *) 	0xFFFE0040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CHER  (AT91_CAST(AT91_REG *) 	0xFFFE0010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR  (AT91_CAST(AT91_REG *) 	0xFFFE0018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR    (AT91_CAST(AT91_REG *) 	0xFFFE0004) // (ADC) ADC Mode Register
+#define AT91C_ADC_CDR6  (AT91_CAST(AT91_REG *) 	0xFFFE0048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_LCDR  (AT91_CAST(AT91_REG *) 	0xFFFE0020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_CDR1  (AT91_CAST(AT91_REG *) 	0xFFFE0034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFE0028) // (ADC) ADC Interrupt Disable Register
+// ========== Register definition for EMACB peripheral ========== 
+#define AT91C_EMACB_USRIO (AT91_CAST(AT91_REG *) 	0xFFFC40C0) // (EMACB) USER Input/Output Register
+#define AT91C_EMACB_RSE (AT91_CAST(AT91_REG *) 	0xFFFC4074) // (EMACB) Receive Symbol Errors Register
+#define AT91C_EMACB_SCF (AT91_CAST(AT91_REG *) 	0xFFFC4044) // (EMACB) Single Collision Frame Register
+#define AT91C_EMACB_STE (AT91_CAST(AT91_REG *) 	0xFFFC4084) // (EMACB) SQE Test Error Register
+#define AT91C_EMACB_SA1H (AT91_CAST(AT91_REG *) 	0xFFFC409C) // (EMACB) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMACB_ROV (AT91_CAST(AT91_REG *) 	0xFFFC4070) // (EMACB) Receive Overrun Errors Register
+#define AT91C_EMACB_TBQP (AT91_CAST(AT91_REG *) 	0xFFFC401C) // (EMACB) Transmit Buffer Queue Pointer
+#define AT91C_EMACB_IMR (AT91_CAST(AT91_REG *) 	0xFFFC4030) // (EMACB) Interrupt Mask Register
+#define AT91C_EMACB_IER (AT91_CAST(AT91_REG *) 	0xFFFC4028) // (EMACB) Interrupt Enable Register
+#define AT91C_EMACB_REV (AT91_CAST(AT91_REG *) 	0xFFFC40FC) // (EMACB) Revision Register
+#define AT91C_EMACB_SA3L (AT91_CAST(AT91_REG *) 	0xFFFC40A8) // (EMACB) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMACB_ELE (AT91_CAST(AT91_REG *) 	0xFFFC4078) // (EMACB) Excessive Length Errors Register
+#define AT91C_EMACB_HRT (AT91_CAST(AT91_REG *) 	0xFFFC4094) // (EMACB) Hash Address Top[63:32]
+#define AT91C_EMACB_SA2L (AT91_CAST(AT91_REG *) 	0xFFFC40A0) // (EMACB) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMACB_RRE (AT91_CAST(AT91_REG *) 	0xFFFC406C) // (EMACB) Receive Ressource Error Register
+#define AT91C_EMACB_FRO (AT91_CAST(AT91_REG *) 	0xFFFC404C) // (EMACB) Frames Received OK Register
+#define AT91C_EMACB_TPQ (AT91_CAST(AT91_REG *) 	0xFFFC40BC) // (EMACB) Transmit Pause Quantum Register
+#define AT91C_EMACB_ISR (AT91_CAST(AT91_REG *) 	0xFFFC4024) // (EMACB) Interrupt Status Register
+#define AT91C_EMACB_TSR (AT91_CAST(AT91_REG *) 	0xFFFC4014) // (EMACB) Transmit Status Register
+#define AT91C_EMACB_RLE (AT91_CAST(AT91_REG *) 	0xFFFC4088) // (EMACB) Receive Length Field Mismatch Register
+#define AT91C_EMACB_USF (AT91_CAST(AT91_REG *) 	0xFFFC4080) // (EMACB) Undersize Frames Register
+#define AT91C_EMACB_WOL (AT91_CAST(AT91_REG *) 	0xFFFC40C4) // (EMACB) Wake On LAN Register
+#define AT91C_EMACB_TPF (AT91_CAST(AT91_REG *) 	0xFFFC408C) // (EMACB) Transmitted Pause Frames Register
+#define AT91C_EMACB_PTR (AT91_CAST(AT91_REG *) 	0xFFFC4038) // (EMACB) Pause Time Register
+#define AT91C_EMACB_TUND (AT91_CAST(AT91_REG *) 	0xFFFC4064) // (EMACB) Transmit Underrun Error Register
+#define AT91C_EMACB_MAN (AT91_CAST(AT91_REG *) 	0xFFFC4034) // (EMACB) PHY Maintenance Register
+#define AT91C_EMACB_RJA (AT91_CAST(AT91_REG *) 	0xFFFC407C) // (EMACB) Receive Jabbers Register
+#define AT91C_EMACB_SA4L (AT91_CAST(AT91_REG *) 	0xFFFC40B0) // (EMACB) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMACB_CSE (AT91_CAST(AT91_REG *) 	0xFFFC4068) // (EMACB) Carrier Sense Error Register
+#define AT91C_EMACB_HRB (AT91_CAST(AT91_REG *) 	0xFFFC4090) // (EMACB) Hash Address Bottom[31:0]
+#define AT91C_EMACB_ALE (AT91_CAST(AT91_REG *) 	0xFFFC4054) // (EMACB) Alignment Error Register
+#define AT91C_EMACB_SA1L (AT91_CAST(AT91_REG *) 	0xFFFC4098) // (EMACB) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMACB_NCR (AT91_CAST(AT91_REG *) 	0xFFFC4000) // (EMACB) Network Control Register
+#define AT91C_EMACB_FTO (AT91_CAST(AT91_REG *) 	0xFFFC4040) // (EMACB) Frames Transmitted OK Register
+#define AT91C_EMACB_ECOL (AT91_CAST(AT91_REG *) 	0xFFFC4060) // (EMACB) Excessive Collision Register
+#define AT91C_EMACB_DTF (AT91_CAST(AT91_REG *) 	0xFFFC4058) // (EMACB) Deferred Transmission Frame Register
+#define AT91C_EMACB_SA4H (AT91_CAST(AT91_REG *) 	0xFFFC40B4) // (EMACB) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMACB_FCSE (AT91_CAST(AT91_REG *) 	0xFFFC4050) // (EMACB) Frame Check Sequence Error Register
+#define AT91C_EMACB_TID (AT91_CAST(AT91_REG *) 	0xFFFC40B8) // (EMACB) Type ID Checking Register
+#define AT91C_EMACB_PFR (AT91_CAST(AT91_REG *) 	0xFFFC403C) // (EMACB) Pause Frames received Register
+#define AT91C_EMACB_IDR (AT91_CAST(AT91_REG *) 	0xFFFC402C) // (EMACB) Interrupt Disable Register
+#define AT91C_EMACB_SA3H (AT91_CAST(AT91_REG *) 	0xFFFC40AC) // (EMACB) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMACB_NSR (AT91_CAST(AT91_REG *) 	0xFFFC4008) // (EMACB) Network Status Register
+#define AT91C_EMACB_MCF (AT91_CAST(AT91_REG *) 	0xFFFC4048) // (EMACB) Multiple Collision Frame Register
+#define AT91C_EMACB_RBQP (AT91_CAST(AT91_REG *) 	0xFFFC4018) // (EMACB) Receive Buffer Queue Pointer
+#define AT91C_EMACB_RSR (AT91_CAST(AT91_REG *) 	0xFFFC4020) // (EMACB) Receive Status Register
+#define AT91C_EMACB_SA2H (AT91_CAST(AT91_REG *) 	0xFFFC40A4) // (EMACB) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMACB_NCFGR (AT91_CAST(AT91_REG *) 	0xFFFC4004) // (EMACB) Network Configuration Register
+#define AT91C_EMACB_LCOL (AT91_CAST(AT91_REG *) 	0xFFFC405C) // (EMACB) Late Collision Register
+// ========== Register definition for UDP peripheral ========== 
+#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 	0xFFFA4004) // (UDP) Global State Register
+#define AT91C_UDP_FDR   (AT91_CAST(AT91_REG *) 	0xFFFA4050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 	0xFFFA4028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 	0xFFFA4008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM   (AT91_CAST(AT91_REG *) 	0xFFFA4000) // (UDP) Frame Number Register
+#define AT91C_UDP_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA4014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA4018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_CSR   (AT91_CAST(AT91_REG *) 	0xFFFA4030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IER   (AT91_CAST(AT91_REG *) 	0xFFFA4010) // (UDP) Interrupt Enable Register
+#define AT91C_UDP_ICR   (AT91_CAST(AT91_REG *) 	0xFFFA4020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_TXVC  (AT91_CAST(AT91_REG *) 	0xFFFA4074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_ISR   (AT91_CAST(AT91_REG *) 	0xFFFA401C) // (UDP) Interrupt Status Register
+// ========== Register definition for UHP peripheral ========== 
+#define AT91C_UHP_HcInterruptStatus (AT91_CAST(AT91_REG *) 	0x0050000C) // (UHP) Interrupt Status Register
+#define AT91C_UHP_HcCommandStatus (AT91_CAST(AT91_REG *) 	0x00500008) // (UHP) Command & status Register
+#define AT91C_UHP_HcRhStatus (AT91_CAST(AT91_REG *) 	0x00500050) // (UHP) Root Hub Status register
+#define AT91C_UHP_HcInterruptDisable (AT91_CAST(AT91_REG *) 	0x00500014) // (UHP) Interrupt Disable Register
+#define AT91C_UHP_HcPeriodicStart (AT91_CAST(AT91_REG *) 	0x00500040) // (UHP) Periodic Start
+#define AT91C_UHP_HcControlCurrentED (AT91_CAST(AT91_REG *) 	0x00500024) // (UHP) Endpoint Control and Status Register
+#define AT91C_UHP_HcPeriodCurrentED (AT91_CAST(AT91_REG *) 	0x0050001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor
+#define AT91C_UHP_HcBulkHeadED (AT91_CAST(AT91_REG *) 	0x00500028) // (UHP) First endpoint register of the Bulk list
+#define AT91C_UHP_HcRevision (AT91_CAST(AT91_REG *) 	0x00500000) // (UHP) Revision
+#define AT91C_UHP_HcBulkCurrentED (AT91_CAST(AT91_REG *) 	0x0050002C) // (UHP) Current endpoint of the Bulk list
+#define AT91C_UHP_HcRhDescriptorB (AT91_CAST(AT91_REG *) 	0x0050004C) // (UHP) Root Hub characteristics B
+#define AT91C_UHP_HcControlHeadED (AT91_CAST(AT91_REG *) 	0x00500020) // (UHP) First Endpoint Descriptor of the Control list
+#define AT91C_UHP_HcFmRemaining (AT91_CAST(AT91_REG *) 	0x00500038) // (UHP) Bit time remaining in the current Frame
+#define AT91C_UHP_HcHCCA (AT91_CAST(AT91_REG *) 	0x00500018) // (UHP) Pointer to the Host Controller Communication Area
+#define AT91C_UHP_HcLSThreshold (AT91_CAST(AT91_REG *) 	0x00500044) // (UHP) LS Threshold
+#define AT91C_UHP_HcRhPortStatus (AT91_CAST(AT91_REG *) 	0x00500054) // (UHP) Root Hub Port Status Register
+#define AT91C_UHP_HcInterruptEnable (AT91_CAST(AT91_REG *) 	0x00500010) // (UHP) Interrupt Enable Register
+#define AT91C_UHP_HcFmNumber (AT91_CAST(AT91_REG *) 	0x0050003C) // (UHP) Frame number
+#define AT91C_UHP_HcFmInterval (AT91_CAST(AT91_REG *) 	0x00500034) // (UHP) Bit time between 2 consecutive SOFs
+#define AT91C_UHP_HcControl (AT91_CAST(AT91_REG *) 	0x00500004) // (UHP) Operating modes for the Host Controller
+#define AT91C_UHP_HcBulkDoneHead (AT91_CAST(AT91_REG *) 	0x00500030) // (UHP) Last completed transfer descriptor
+#define AT91C_UHP_HcRhDescriptorA (AT91_CAST(AT91_REG *) 	0x00500048) // (UHP) Root Hub characteristics A
+// ========== Register definition for HECC peripheral ========== 
+// ========== Register definition for HISI peripheral ========== 
+#define AT91C_HISI_PSIZE (AT91_CAST(AT91_REG *) 	0xFFFC0020) // (HISI) Preview Size Register
+#define AT91C_HISI_CR1  (AT91_CAST(AT91_REG *) 	0xFFFC0000) // (HISI) Control Register 1
+#define AT91C_HISI_R2YSET1 (AT91_CAST(AT91_REG *) 	0xFFFC003C) // (HISI) Color Space Conversion Register
+#define AT91C_HISI_CDBA (AT91_CAST(AT91_REG *) 	0xFFFC002C) // (HISI) Codec Dma Address Register
+#define AT91C_HISI_IDR  (AT91_CAST(AT91_REG *) 	0xFFFC0010) // (HISI) Interrupt Disable Register
+#define AT91C_HISI_R2YSET2 (AT91_CAST(AT91_REG *) 	0xFFFC0040) // (HISI) Color Space Conversion Register
+#define AT91C_HISI_Y2RSET1 (AT91_CAST(AT91_REG *) 	0xFFFC0034) // (HISI) Color Space Conversion Register
+#define AT91C_HISI_PFBD (AT91_CAST(AT91_REG *) 	0xFFFC0028) // (HISI) Preview Frame Buffer Address Register
+#define AT91C_HISI_CR2  (AT91_CAST(AT91_REG *) 	0xFFFC0004) // (HISI) Control Register 2
+#define AT91C_HISI_Y2RSET0 (AT91_CAST(AT91_REG *) 	0xFFFC0030) // (HISI) Color Space Conversion Register
+#define AT91C_HISI_PDECF (AT91_CAST(AT91_REG *) 	0xFFFC0024) // (HISI) Preview Decimation Factor Register
+#define AT91C_HISI_IMR  (AT91_CAST(AT91_REG *) 	0xFFFC0014) // (HISI) Interrupt Mask Register
+#define AT91C_HISI_IER  (AT91_CAST(AT91_REG *) 	0xFFFC000C) // (HISI) Interrupt Enable Register
+#define AT91C_HISI_R2YSET0 (AT91_CAST(AT91_REG *) 	0xFFFC0038) // (HISI) Color Space Conversion Register
+#define AT91C_HISI_SR   (AT91_CAST(AT91_REG *) 	0xFFFC0008) // (HISI) Status Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM9XE128
+// *****************************************************************************
+#define AT91C_PIO_PA0        (1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_SPI0_MISO (AT91C_PIO_PA0) //  SPI 0 Master In Slave
+#define AT91C_PA0_MCDB0    (AT91C_PIO_PA0) //  Multimedia Card B Data 0
+#define AT91C_PIO_PA1        (1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_SPI0_MOSI (AT91C_PIO_PA1) //  SPI 0 Master Out Slave
+#define AT91C_PA1_MCCDB    (AT91C_PIO_PA1) //  Multimedia Card B Command
+#define AT91C_PIO_PA10       (1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_MCDA2    (AT91C_PIO_PA10) //  Multimedia Card A Data 2
+#define AT91C_PA10_ETX2_0   (AT91C_PIO_PA10) //  Ethernet MAC Transmit Data 2
+#define AT91C_PIO_PA11       (1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_MCDA3    (AT91C_PIO_PA11) //  Multimedia Card A Data 3
+#define AT91C_PA11_ETX3_0   (AT91C_PIO_PA11) //  Ethernet MAC Transmit Data 3
+#define AT91C_PIO_PA12       (1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_ETX0     (AT91C_PIO_PA12) //  Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PA13       (1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_ETX1     (AT91C_PIO_PA13) //  Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PA14       (1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_ERX0     (AT91C_PIO_PA14) //  Ethernet MAC Receive Data 0
+#define AT91C_PIO_PA15       (1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_ERX1     (AT91C_PIO_PA15) //  Ethernet MAC Receive Data 1
+#define AT91C_PIO_PA16       (1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_ETXEN    (AT91C_PIO_PA16) //  Ethernet MAC Transmit Enable
+#define AT91C_PIO_PA17       (1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_ERXDV    (AT91C_PIO_PA17) //  Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PA18       (1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_ERXER    (AT91C_PIO_PA18) //  Ethernet MAC Receive Error
+#define AT91C_PIO_PA19       (1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_ETXCK    (AT91C_PIO_PA19) //  Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PIO_PA2        (1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_SPI0_SPCK (AT91C_PIO_PA2) //  SPI 0 Serial Clock
+#define AT91C_PIO_PA20       (1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_EMDC     (AT91C_PIO_PA20) //  Ethernet MAC Management Data Clock
+#define AT91C_PIO_PA21       (1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_EMDIO    (AT91C_PIO_PA21) //  Ethernet MAC Management Data Input/Output
+#define AT91C_PIO_PA22       (1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_ADTRG    (AT91C_PIO_PA22) //  ADC Trigger
+#define AT91C_PA22_ETXER    (AT91C_PIO_PA22) //  Ethernet MAC Transmikt Coding Error
+#define AT91C_PIO_PA23       (1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TWD0     (AT91C_PIO_PA23) //  TWI Two-wire Serial Data 0
+#define AT91C_PA23_ETX2_1   (AT91C_PIO_PA23) //  Ethernet MAC Transmit Data 2
+#define AT91C_PIO_PA24       (1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_TWCK0    (AT91C_PIO_PA24) //  TWI Two-wire Serial Clock 0
+#define AT91C_PA24_ETX3_1   (AT91C_PIO_PA24) //  Ethernet MAC Transmit Data 3
+#define AT91C_PIO_PA25       (1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_TCLK0    (AT91C_PIO_PA25) //  Timer Counter 0 external clock input
+#define AT91C_PA25_ERX2     (AT91C_PIO_PA25) //  Ethernet MAC Receive Data 2
+#define AT91C_PIO_PA26       (1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_TIOA0    (AT91C_PIO_PA26) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PA26_ERX3     (AT91C_PIO_PA26) //  Ethernet MAC Receive Data 3
+#define AT91C_PIO_PA27       (1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_TIOA1    (AT91C_PIO_PA27) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PA27_ERXCK    (AT91C_PIO_PA27) //  Ethernet MAC Receive Clock
+#define AT91C_PIO_PA28       (1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_TIOA2    (AT91C_PIO_PA28) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PA28_ECRS     (AT91C_PIO_PA28) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PA29       (1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_SCK1     (AT91C_PIO_PA29) //  USART 1 Serial Clock
+#define AT91C_PA29_ECOL     (AT91C_PIO_PA29) //  Ethernet MAC Collision Detected
+#define AT91C_PIO_PA3        (1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_SPI0_NPCS0 (AT91C_PIO_PA3) //  SPI 0 Peripheral Chip Select 0
+#define AT91C_PA3_MCDB3    (AT91C_PIO_PA3) //  Multimedia Card B Data 3
+#define AT91C_PIO_PA30       (1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_SCK2     (AT91C_PIO_PA30) //  USART 2 Serial Clock
+#define AT91C_PA30_RXD4     (AT91C_PIO_PA30) //  USART 4 Receive Data
+#define AT91C_PIO_PA31       (1 << 31) // Pin Controlled by PA31
+#define AT91C_PA31_SCK0     (AT91C_PIO_PA31) //  USART 0 Serial Clock
+#define AT91C_PA31_TXD4     (AT91C_PIO_PA31) //  USART 4 Transmit Data
+#define AT91C_PIO_PA4        (1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_RTS2     (AT91C_PIO_PA4) //  USART 2 Ready To Send
+#define AT91C_PA4_MCDB2    (AT91C_PIO_PA4) //  Multimedia Card B Data 2
+#define AT91C_PIO_PA5        (1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_CTS2     (AT91C_PIO_PA5) //  USART 2 Clear To Send
+#define AT91C_PA5_MCDB1    (AT91C_PIO_PA5) //  Multimedia Card B Data 1
+#define AT91C_PIO_PA6        (1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_MCDA0    (AT91C_PIO_PA6) //  Multimedia Card A Data 0
+#define AT91C_PIO_PA7        (1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_MCCDA    (AT91C_PIO_PA7) //  Multimedia Card A Command
+#define AT91C_PIO_PA8        (1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_MCCK     (AT91C_PIO_PA8) //  Multimedia Card Clock
+#define AT91C_PIO_PA9        (1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_MCDA1    (AT91C_PIO_PA9) //  Multimedia Card A Data 1
+#define AT91C_PIO_PB0        (1 <<  0) // Pin Controlled by PB0
+#define AT91C_PB0_SPI1_MISO (AT91C_PIO_PB0) //  SPI 1 Master In Slave
+#define AT91C_PB0_TIOA3    (AT91C_PIO_PB0) //  Timer Counter 3 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PB1        (1 <<  1) // Pin Controlled by PB1
+#define AT91C_PB1_SPI1_MOSI (AT91C_PIO_PB1) //  SPI 1 Master Out Slave
+#define AT91C_PB1_TIOB3    (AT91C_PIO_PB1) //  Timer Counter 3 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PB10       (1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_TXD3     (AT91C_PIO_PB10) //  USART 3 Transmit Data
+#define AT91C_PB10_ISI_D8   (AT91C_PIO_PB10) //  Image Sensor Data 8
+#define AT91C_PIO_PB11       (1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_RXD3     (AT91C_PIO_PB11) //  USART 3 Receive Data
+#define AT91C_PB11_ISI_D9   (AT91C_PIO_PB11) //  Image Sensor Data 9
+#define AT91C_PIO_PB12       (1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_TWD1     (AT91C_PIO_PB12) //  TWI Two-wire Serial Data 1
+#define AT91C_PB12_ISI_D10  (AT91C_PIO_PB12) //  Image Sensor Data 10
+#define AT91C_PIO_PB13       (1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_TWCK1    (AT91C_PIO_PB13) //  TWI Two-wire Serial Clock 1
+#define AT91C_PB13_ISI_D11  (AT91C_PIO_PB13) //  Image Sensor Data 11
+#define AT91C_PIO_PB14       (1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_DRXD     (AT91C_PIO_PB14) //  DBGU Debug Receive Data
+#define AT91C_PIO_PB15       (1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_DTXD     (AT91C_PIO_PB15) //  DBGU Debug Transmit Data
+#define AT91C_PIO_PB16       (1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_TK0      (AT91C_PIO_PB16) //  SSC0 Transmit Clock
+#define AT91C_PB16_TCLK3    (AT91C_PIO_PB16) //  Timer Counter 3 external clock input
+#define AT91C_PIO_PB17       (1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_TF0      (AT91C_PIO_PB17) //  SSC0 Transmit Frame Sync
+#define AT91C_PB17_TCLK4    (AT91C_PIO_PB17) //  Timer Counter 4 external clock input
+#define AT91C_PIO_PB18       (1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_TD0      (AT91C_PIO_PB18) //  SSC0 Transmit data
+#define AT91C_PB18_TIOB4    (AT91C_PIO_PB18) //  Timer Counter 4 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PB19       (1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_RD0      (AT91C_PIO_PB19) //  SSC0 Receive Data
+#define AT91C_PB19_TIOB5    (AT91C_PIO_PB19) //  Timer Counter 5 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PB2        (1 <<  2) // Pin Controlled by PB2
+#define AT91C_PB2_SPI1_SPCK (AT91C_PIO_PB2) //  SPI 1 Serial Clock
+#define AT91C_PB2_TIOA4    (AT91C_PIO_PB2) //  Timer Counter 4 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PB20       (1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_RK0      (AT91C_PIO_PB20) //  SSC0 Receive Clock
+#define AT91C_PB20_ISI_D0   (AT91C_PIO_PB20) //  Image Sensor Data 0
+#define AT91C_PIO_PB21       (1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_RF0      (AT91C_PIO_PB21) //  SSC0 Receive Frame Sync
+#define AT91C_PB21_ISI_D1   (AT91C_PIO_PB21) //  Image Sensor Data 1
+#define AT91C_PIO_PB22       (1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_DSR0     (AT91C_PIO_PB22) //  USART 0 Data Set ready
+#define AT91C_PB22_ISI_D2   (AT91C_PIO_PB22) //  Image Sensor Data 2
+#define AT91C_PIO_PB23       (1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_DCD0     (AT91C_PIO_PB23) //  USART 0 Data Carrier Detect
+#define AT91C_PB23_ISI_D3   (AT91C_PIO_PB23) //  Image Sensor Data 3
+#define AT91C_PIO_PB24       (1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_DTR0     (AT91C_PIO_PB24) //  USART 0 Data Terminal ready
+#define AT91C_PB24_ISI_D4   (AT91C_PIO_PB24) //  Image Sensor Data 4
+#define AT91C_PIO_PB25       (1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_RI0      (AT91C_PIO_PB25) //  USART 0 Ring Indicator
+#define AT91C_PB25_ISI_D5   (AT91C_PIO_PB25) //  Image Sensor Data 5
+#define AT91C_PIO_PB26       (1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_RTS0     (AT91C_PIO_PB26) //  USART 0 Ready To Send
+#define AT91C_PB26_ISI_D6   (AT91C_PIO_PB26) //  Image Sensor Data 6
+#define AT91C_PIO_PB27       (1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_CTS0     (AT91C_PIO_PB27) //  USART 0 Clear To Send
+#define AT91C_PB27_ISI_D7   (AT91C_PIO_PB27) //  Image Sensor Data 7
+#define AT91C_PIO_PB28       (1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_RTS1     (AT91C_PIO_PB28) //  USART 1 Ready To Send
+#define AT91C_PB28_ISI_PCK  (AT91C_PIO_PB28) //  Image Sensor Data Clock
+#define AT91C_PIO_PB29       (1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_CTS1     (AT91C_PIO_PB29) //  USART 1 Clear To Send
+#define AT91C_PB29_ISI_VSYNC (AT91C_PIO_PB29) //  Image Sensor Vertical Synchro
+#define AT91C_PIO_PB3        (1 <<  3) // Pin Controlled by PB3
+#define AT91C_PB3_SPI1_NPCS0 (AT91C_PIO_PB3) //  SPI 1 Peripheral Chip Select 0
+#define AT91C_PB3_TIOA5    (AT91C_PIO_PB3) //  Timer Counter 5 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PB30       (1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK0_0   (AT91C_PIO_PB30) //  PMC Programmable Clock Output 0
+#define AT91C_PB30_ISI_HSYNC (AT91C_PIO_PB30) //  Image Sensor Horizontal Synchro
+#define AT91C_PIO_PB31       (1 << 31) // Pin Controlled by PB31
+#define AT91C_PB31_PCK1_0   (AT91C_PIO_PB31) //  PMC Programmable Clock Output 1
+#define AT91C_PB31_ISI_MCK  (AT91C_PIO_PB31) //  Image Sensor Reference Clock
+#define AT91C_PIO_PB4        (1 <<  4) // Pin Controlled by PB4
+#define AT91C_PB4_TXD0     (AT91C_PIO_PB4) //  USART 0 Transmit Data
+#define AT91C_PIO_PB5        (1 <<  5) // Pin Controlled by PB5
+#define AT91C_PB5_RXD0     (AT91C_PIO_PB5) //  USART 0 Receive Data
+#define AT91C_PIO_PB6        (1 <<  6) // Pin Controlled by PB6
+#define AT91C_PB6_TXD1     (AT91C_PIO_PB6) //  USART 1 Transmit Data
+#define AT91C_PB6_TCLK1    (AT91C_PIO_PB6) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PB7        (1 <<  7) // Pin Controlled by PB7
+#define AT91C_PB7_RXD1     (AT91C_PIO_PB7) //  USART 1 Receive Data
+#define AT91C_PB7_TCLK2    (AT91C_PIO_PB7) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PB8        (1 <<  8) // Pin Controlled by PB8
+#define AT91C_PB8_TXD2     (AT91C_PIO_PB8) //  USART 2 Transmit Data
+#define AT91C_PIO_PB9        (1 <<  9) // Pin Controlled by PB9
+#define AT91C_PB9_RXD2     (AT91C_PIO_PB9) //  USART 2 Receive Data
+#define AT91C_PIO_PC0        (1 <<  0) // Pin Controlled by PC0
+#define AT91C_PC0_AD0      (AT91C_PIO_PC0) //  ADC Analog Input 0
+#define AT91C_PC0_SCK3     (AT91C_PIO_PC0) //  USART 3 Serial Clock
+#define AT91C_PIO_PC1        (1 <<  1) // Pin Controlled by PC1
+#define AT91C_PC1_AD1      (AT91C_PIO_PC1) //  ADC Analog Input 1
+#define AT91C_PC1_PCK0     (AT91C_PIO_PC1) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PC10       (1 << 10) // Pin Controlled by PC10
+#define AT91C_PC10_A25_CFRNW (AT91C_PIO_PC10) //  Address Bus[25]
+#define AT91C_PC10_CTS3     (AT91C_PIO_PC10) //  USART 3 Clear To Send
+#define AT91C_PIO_PC11       (1 << 11) // Pin Controlled by PC11
+#define AT91C_PC11_NCS2     (AT91C_PIO_PC11) //  Chip Select Line 2
+#define AT91C_PC11_SPI0_NPCS1 (AT91C_PIO_PC11) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PC12       (1 << 12) // Pin Controlled by PC12
+#define AT91C_PC12_IRQ0     (AT91C_PIO_PC12) //  External Interrupt 0
+#define AT91C_PC12_NCS7     (AT91C_PIO_PC12) //  Chip Select Line 7
+#define AT91C_PIO_PC13       (1 << 13) // Pin Controlled by PC13
+#define AT91C_PC13_FIQ      (AT91C_PIO_PC13) //  AIC Fast Interrupt Input
+#define AT91C_PC13_NCS6     (AT91C_PIO_PC13) //  Chip Select Line 6
+#define AT91C_PIO_PC14       (1 << 14) // Pin Controlled by PC14
+#define AT91C_PC14_NCS3_NANDCS (AT91C_PIO_PC14) //  Chip Select Line 3
+#define AT91C_PC14_IRQ2     (AT91C_PIO_PC14) //  External Interrupt 2
+#define AT91C_PIO_PC15       (1 << 15) // Pin Controlled by PC15
+#define AT91C_PC15_NWAIT    (AT91C_PIO_PC15) //  External Wait Signal
+#define AT91C_PC15_IRQ1     (AT91C_PIO_PC15) //  External Interrupt 1
+#define AT91C_PIO_PC16       (1 << 16) // Pin Controlled by PC16
+#define AT91C_PC16_D16      (AT91C_PIO_PC16) //  Data Bus[16]
+#define AT91C_PC16_SPI0_NPCS2 (AT91C_PIO_PC16) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PC17       (1 << 17) // Pin Controlled by PC17
+#define AT91C_PC17_D17      (AT91C_PIO_PC17) //  Data Bus[17]
+#define AT91C_PC17_SPI0_NPCS3 (AT91C_PIO_PC17) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PC18       (1 << 18) // Pin Controlled by PC18
+#define AT91C_PC18_D18      (AT91C_PIO_PC18) //  Data Bus[18]
+#define AT91C_PC18_SPI1_NPCS1_1 (AT91C_PIO_PC18) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PC19       (1 << 19) // Pin Controlled by PC19
+#define AT91C_PC19_D19      (AT91C_PIO_PC19) //  Data Bus[19]
+#define AT91C_PC19_SPI1_NPCS2_1 (AT91C_PIO_PC19) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PC2        (1 <<  2) // Pin Controlled by PC2
+#define AT91C_PC2_AD2      (AT91C_PIO_PC2) //  ADC Analog Input 2
+#define AT91C_PC2_PCK1     (AT91C_PIO_PC2) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PC20       (1 << 20) // Pin Controlled by PC20
+#define AT91C_PC20_D20      (AT91C_PIO_PC20) //  Data Bus[20]
+#define AT91C_PC20_SPI1_NPCS3_1 (AT91C_PIO_PC20) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PC21       (1 << 21) // Pin Controlled by PC21
+#define AT91C_PC21_D21      (AT91C_PIO_PC21) //  Data Bus[21]
+#define AT91C_PC21_EF100    (AT91C_PIO_PC21) //  Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PIO_PC22       (1 << 22) // Pin Controlled by PC22
+#define AT91C_PC22_D22      (AT91C_PIO_PC22) //  Data Bus[22]
+#define AT91C_PC22_TCLK5    (AT91C_PIO_PC22) //  Timer Counter 5 external clock input
+#define AT91C_PIO_PC23       (1 << 23) // Pin Controlled by PC23
+#define AT91C_PC23_D23      (AT91C_PIO_PC23) //  Data Bus[23]
+#define AT91C_PIO_PC24       (1 << 24) // Pin Controlled by PC24
+#define AT91C_PC24_D24      (AT91C_PIO_PC24) //  Data Bus[24]
+#define AT91C_PIO_PC25       (1 << 25) // Pin Controlled by PC25
+#define AT91C_PC25_D25      (AT91C_PIO_PC25) //  Data Bus[25]
+#define AT91C_PIO_PC26       (1 << 26) // Pin Controlled by PC26
+#define AT91C_PC26_D26      (AT91C_PIO_PC26) //  Data Bus[26]
+#define AT91C_PIO_PC27       (1 << 27) // Pin Controlled by PC27
+#define AT91C_PC27_D27      (AT91C_PIO_PC27) //  Data Bus[27]
+#define AT91C_PIO_PC28       (1 << 28) // Pin Controlled by PC28
+#define AT91C_PC28_D28      (AT91C_PIO_PC28) //  Data Bus[28]
+#define AT91C_PIO_PC29       (1 << 29) // Pin Controlled by PC29
+#define AT91C_PC29_D29      (AT91C_PIO_PC29) //  Data Bus[29]
+#define AT91C_PIO_PC3        (1 <<  3) // Pin Controlled by PC3
+#define AT91C_PC3_AD3      (AT91C_PIO_PC3) //  ADC Analog Input 3
+#define AT91C_PC3_SPI1_NPCS3_0 (AT91C_PIO_PC3) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PC30       (1 << 30) // Pin Controlled by PC30
+#define AT91C_PC30_D30      (AT91C_PIO_PC30) //  Data Bus[30]
+#define AT91C_PIO_PC31       (1 << 31) // Pin Controlled by PC31
+#define AT91C_PC31_D31      (AT91C_PIO_PC31) //  Data Bus[31]
+#define AT91C_PIO_PC4        (1 <<  4) // Pin Controlled by PC4
+#define AT91C_PC4_A23      (AT91C_PIO_PC4) //  Address Bus[23]
+#define AT91C_PC4_SPI1_NPCS2_0 (AT91C_PIO_PC4) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PC5        (1 <<  5) // Pin Controlled by PC5
+#define AT91C_PC5_A24      (AT91C_PIO_PC5) //  Address Bus[24]
+#define AT91C_PC5_SPI1_NPCS1_0 (AT91C_PIO_PC5) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PC6        (1 <<  6) // Pin Controlled by PC6
+#define AT91C_PC6_TIOB2    (AT91C_PIO_PC6) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PC6_CFCE1    (AT91C_PIO_PC6) //  Compact Flash Enable 1
+#define AT91C_PIO_PC7        (1 <<  7) // Pin Controlled by PC7
+#define AT91C_PC7_TIOB1    (AT91C_PIO_PC7) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PC7_CFCE2    (AT91C_PIO_PC7) //  Compact Flash Enable 2
+#define AT91C_PIO_PC8        (1 <<  8) // Pin Controlled by PC8
+#define AT91C_PC8_NCS4_CFCS0 (AT91C_PIO_PC8) //  Chip Select Line 4
+#define AT91C_PC8_RTS3     (AT91C_PIO_PC8) //  USART 3 Ready To Send
+#define AT91C_PIO_PC9        (1 <<  9) // Pin Controlled by PC9
+#define AT91C_PC9_NCS5_CFCS1 (AT91C_PIO_PC9) //  Chip Select Line 5
+#define AT91C_PC9_TIOB0    (AT91C_PIO_PC9) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM9XE128
+// *****************************************************************************
+#define AT91C_ID_FIQ    ( 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS    ( 1) // System Controller
+#define AT91C_ID_PIOA   ( 2) // Parallel IO Controller A
+#define AT91C_ID_PIOB   ( 3) // Parallel IO Controller B
+#define AT91C_ID_PIOC   ( 4) // Parallel IO Controller C
+#define AT91C_ID_ADC    ( 5) // ADC
+#define AT91C_ID_US0    ( 6) // USART 0
+#define AT91C_ID_US1    ( 7) // USART 1
+#define AT91C_ID_US2    ( 8) // USART 2
+#define AT91C_ID_MCI    ( 9) // Multimedia Card Interface 0
+#define AT91C_ID_UDP    (10) // USB Device Port
+#define AT91C_ID_TWI0   (11) // Two-Wire Interface 0
+#define AT91C_ID_SPI0   (12) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1   (13) // Serial Peripheral Interface 1
+#define AT91C_ID_SSC0   (14) // Serial Synchronous Controller 0
+#define AT91C_ID_TC0    (17) // Timer Counter 0
+#define AT91C_ID_TC1    (18) // Timer Counter 1
+#define AT91C_ID_TC2    (19) // Timer Counter 2
+#define AT91C_ID_UHP    (20) // USB Host Port
+#define AT91C_ID_EMAC   (21) // Ethernet Mac
+#define AT91C_ID_HISI   (22) // Image Sensor Interface
+#define AT91C_ID_US3    (23) // USART 3
+#define AT91C_ID_US4    (24) // USART 4
+#define AT91C_ID_TWI1   (25) // Two-Wire Interface 1
+#define AT91C_ID_TC3    (26) // Timer Counter 3
+#define AT91C_ID_TC4    (27) // Timer Counter 4
+#define AT91C_ID_TC5    (28) // Timer Counter 5
+#define AT91C_ID_IRQ0   (29) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1   (30) // Advanced Interrupt Controller (IRQ1)
+#define AT91C_ID_IRQ2   (31) // Advanced Interrupt Controller (IRQ2)
+#define AT91C_ALL_INT   (0xFFFE7FFF) // ALL VALID INTERRUPTS
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM9XE128
+// *****************************************************************************
+#define AT91C_BASE_SYS       (AT91_CAST(AT91PS_SYS) 	0xFFFFFD00) // (SYS) Base Address
+#define AT91C_BASE_EBI       (AT91_CAST(AT91PS_EBI) 	0xFFFFEA00) // (EBI) Base Address
+#define AT91C_BASE_HECC      (AT91_CAST(AT91PS_ECC) 	0xFFFFE800) // (HECC) Base Address
+#define AT91C_BASE_SDRAMC    (AT91_CAST(AT91PS_SDRAMC) 	0xFFFFEA00) // (SDRAMC) Base Address
+#define AT91C_BASE_SMC       (AT91_CAST(AT91PS_SMC) 	0xFFFFEC00) // (SMC) Base Address
+#define AT91C_BASE_MATRIX    (AT91_CAST(AT91PS_MATRIX) 	0xFFFFEE00) // (MATRIX) Base Address
+#define AT91C_BASE_CCFG      (AT91_CAST(AT91PS_CCFG) 	0xFFFFEF10) // (CCFG) Base Address
+#define AT91C_BASE_PDC_DBGU  (AT91_CAST(AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU      (AT91_CAST(AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_AIC       (AT91_CAST(AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PIOA      (AT91_CAST(AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB      (AT91_CAST(AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_PIOC      (AT91_CAST(AT91PS_PIO) 	0xFFFFF800) // (PIOC) Base Address
+#define AT91C_BASE_EFC       (AT91_CAST(AT91PS_EFC) 	0xFFFFFA00) // (EFC) Base Address
+#define AT91C_BASE_CKGR      (AT91_CAST(AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC       (AT91_CAST(AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC      (AT91_CAST(AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_SHDWC     (AT91_CAST(AT91PS_SHDWC) 	0xFFFFFD10) // (SHDWC) Base Address
+#define AT91C_BASE_RTTC      (AT91_CAST(AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC      (AT91_CAST(AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC      (AT91_CAST(AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_TC0       (AT91_CAST(AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1       (AT91_CAST(AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2       (AT91_CAST(AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TC3       (AT91_CAST(AT91PS_TC) 	0xFFFDC000) // (TC3) Base Address
+#define AT91C_BASE_TC4       (AT91_CAST(AT91PS_TC) 	0xFFFDC040) // (TC4) Base Address
+#define AT91C_BASE_TC5       (AT91_CAST(AT91PS_TC) 	0xFFFDC080) // (TC5) Base Address
+#define AT91C_BASE_TCB0      (AT91_CAST(AT91PS_TCB) 	0xFFFA0000) // (TCB0) Base Address
+#define AT91C_BASE_TCB1      (AT91_CAST(AT91PS_TCB) 	0xFFFDC000) // (TCB1) Base Address
+#define AT91C_BASE_PDC_MCI   (AT91_CAST(AT91PS_PDC) 	0xFFFA8100) // (PDC_MCI) Base Address
+#define AT91C_BASE_MCI       (AT91_CAST(AT91PS_MCI) 	0xFFFA8000) // (MCI) Base Address
+#define AT91C_BASE_PDC_TWI0  (AT91_CAST(AT91PS_PDC) 	0xFFFAC100) // (PDC_TWI0) Base Address
+#define AT91C_BASE_TWI0      (AT91_CAST(AT91PS_TWI) 	0xFFFAC000) // (TWI0) Base Address
+#define AT91C_BASE_PDC_TWI1  (AT91_CAST(AT91PS_PDC) 	0xFFFD8100) // (PDC_TWI1) Base Address
+#define AT91C_BASE_TWI1      (AT91_CAST(AT91PS_TWI) 	0xFFFD8000) // (TWI1) Base Address
+#define AT91C_BASE_PDC_US0   (AT91_CAST(AT91PS_PDC) 	0xFFFB0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0       (AT91_CAST(AT91PS_USART) 	0xFFFB0000) // (US0) Base Address
+#define AT91C_BASE_PDC_US1   (AT91_CAST(AT91PS_PDC) 	0xFFFB4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1       (AT91_CAST(AT91PS_USART) 	0xFFFB4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US2   (AT91_CAST(AT91PS_PDC) 	0xFFFB8100) // (PDC_US2) Base Address
+#define AT91C_BASE_US2       (AT91_CAST(AT91PS_USART) 	0xFFFB8000) // (US2) Base Address
+#define AT91C_BASE_PDC_US3   (AT91_CAST(AT91PS_PDC) 	0xFFFD0100) // (PDC_US3) Base Address
+#define AT91C_BASE_US3       (AT91_CAST(AT91PS_USART) 	0xFFFD0000) // (US3) Base Address
+#define AT91C_BASE_PDC_US4   (AT91_CAST(AT91PS_PDC) 	0xFFFD4100) // (PDC_US4) Base Address
+#define AT91C_BASE_US4       (AT91_CAST(AT91PS_USART) 	0xFFFD4000) // (US4) Base Address
+#define AT91C_BASE_PDC_SSC0  (AT91_CAST(AT91PS_PDC) 	0xFFFBC100) // (PDC_SSC0) Base Address
+#define AT91C_BASE_SSC0      (AT91_CAST(AT91PS_SSC) 	0xFFFBC000) // (SSC0) Base Address
+#define AT91C_BASE_PDC_SPI0  (AT91_CAST(AT91PS_PDC) 	0xFFFC8100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0      (AT91_CAST(AT91PS_SPI) 	0xFFFC8000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_SPI1  (AT91_CAST(AT91PS_PDC) 	0xFFFCC100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1      (AT91_CAST(AT91PS_SPI) 	0xFFFCC000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_ADC   (AT91_CAST(AT91PS_PDC) 	0xFFFE0100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC       (AT91_CAST(AT91PS_ADC) 	0xFFFE0000) // (ADC) Base Address
+#define AT91C_BASE_EMACB     (AT91_CAST(AT91PS_EMAC) 	0xFFFC4000) // (EMACB) Base Address
+#define AT91C_BASE_UDP       (AT91_CAST(AT91PS_UDP) 	0xFFFA4000) // (UDP) Base Address
+#define AT91C_BASE_UHP       (AT91_CAST(AT91PS_UHP) 	0x00500000) // (UHP) Base Address
+#define AT91C_BASE_HISI      (AT91_CAST(AT91PS_ISI) 	0xFFFC0000) // (HISI) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM9XE128
+// *****************************************************************************
+// IROM
+#define AT91C_IROM 	 (0x00100000) // Internal ROM base address
+#define AT91C_IROM_SIZE	 (0x00008000) // Internal ROM size in byte (32 Kbytes)
+// ISRAM
+#define AT91C_ISRAM	 (0x00300000) // Maximum IRAM Area : 16Kbyte base address
+#define AT91C_ISRAM_SIZE	 (0x00004000) // Maximum IRAM Area : 16Kbyte size in byte (16 Kbytes)
+// ISRAM_MIN
+#define AT91C_ISRAM_MIN	 (0x00300000) // Minimun IRAM Area : 16Kbyte base address
+#define AT91C_ISRAM_MIN_SIZE	 (0x00004000) // Minimun IRAM Area : 16Kbyte size in byte (16 Kbytes)
+// IFLASH
+#define AT91C_IFLASH	 (0x00200000) // Maximum IFLASH Area : 128Kbyte base address
+#define AT91C_IFLASH_SIZE	 (0x00020000) // Maximum IFLASH Area : 128Kbyte size in byte (128 Kbytes)
+#define AT91C_IFLASH_PAGE_SIZE	 (512) // Maximum IFLASH Area : 128Kbyte Page Size: 512 bytes
+#define AT91C_IFLASH_LOCK_REGION_SIZE	 (16384) // Maximum IFLASH Area : 128Kbyte Lock Region Size: 16 Kbytes
+#define AT91C_IFLASH_NB_OF_PAGES	 (256) // Maximum IFLASH Area : 128Kbyte Number of Pages: 256 bytes
+#define AT91C_IFLASH_NB_OF_LOCK_BITS	 (8) // Maximum IFLASH Area : 128Kbyte Number of Lock Bits: 8 bytes
+// EBI_CS0
+#define AT91C_EBI_CS0	 (0x10000000) // EBI Chip Select 0 base address
+#define AT91C_EBI_CS0_SIZE	 (0x10000000) // EBI Chip Select 0 size in byte (262144 Kbytes)
+// EBI_CS1
+#define AT91C_EBI_CS1	 (0x20000000) // EBI Chip Select 1 base address
+#define AT91C_EBI_CS1_SIZE	 (0x10000000) // EBI Chip Select 1 size in byte (262144 Kbytes)
+// EBI_SDRAM
+#define AT91C_EBI_SDRAM	 (0x20000000) // SDRAM on EBI Chip Select 1 base address
+#define AT91C_EBI_SDRAM_SIZE	 (0x10000000) // SDRAM on EBI Chip Select 1 size in byte (262144 Kbytes)
+// EBI_SDRAM_16BIT
+#define AT91C_EBI_SDRAM_16BIT	 (0x20000000) // SDRAM on EBI Chip Select 1 base address
+#define AT91C_EBI_SDRAM_16BIT_SIZE	 (0x02000000) // SDRAM on EBI Chip Select 1 size in byte (32768 Kbytes)
+// EBI_SDRAM_32BIT
+#define AT91C_EBI_SDRAM_32BIT	 (0x20000000) // SDRAM on EBI Chip Select 1 base address
+#define AT91C_EBI_SDRAM_32BIT_SIZE	 (0x04000000) // SDRAM on EBI Chip Select 1 size in byte (65536 Kbytes)
+// EBI_CS2
+#define AT91C_EBI_CS2	 (0x30000000) // EBI Chip Select 2 base address
+#define AT91C_EBI_CS2_SIZE	 (0x10000000) // EBI Chip Select 2 size in byte (262144 Kbytes)
+// EBI_CS3
+#define AT91C_EBI_CS3	 (0x40000000) // EBI Chip Select 3 base address
+#define AT91C_EBI_CS3_SIZE	 (0x10000000) // EBI Chip Select 3 size in byte (262144 Kbytes)
+// EBI_SM
+#define AT91C_EBI_SM	 (0x40000000) // SmartMedia on Chip Select 3 base address
+#define AT91C_EBI_SM_SIZE	 (0x10000000) // SmartMedia on Chip Select 3 size in byte (262144 Kbytes)
+// EBI_CS4
+#define AT91C_EBI_CS4	 (0x50000000) // EBI Chip Select 4 base address
+#define AT91C_EBI_CS4_SIZE	 (0x10000000) // EBI Chip Select 4 size in byte (262144 Kbytes)
+// EBI_CF0
+#define AT91C_EBI_CF0	 (0x50000000) // CompactFlash 0 on Chip Select 4 base address
+#define AT91C_EBI_CF0_SIZE	 (0x10000000) // CompactFlash 0 on Chip Select 4 size in byte (262144 Kbytes)
+// EBI_CS5
+#define AT91C_EBI_CS5	 (0x60000000) // EBI Chip Select 5 base address
+#define AT91C_EBI_CS5_SIZE	 (0x10000000) // EBI Chip Select 5 size in byte (262144 Kbytes)
+// EBI_CF1
+#define AT91C_EBI_CF1	 (0x60000000) // CompactFlash 1 on Chip Select 5 base address
+#define AT91C_EBI_CF1_SIZE	 (0x10000000) // CompactFlash 1 on Chip Select 5 size in byte (262144 Kbytes)
+// EBI_CS6
+#define AT91C_EBI_CS6	 (0x70000000) // EBI Chip Select 6 base address
+#define AT91C_EBI_CS6_SIZE	 (0x10000000) // EBI Chip Select 6 size in byte (262144 Kbytes)
+// EBI_CS7
+#define AT91C_EBI_CS7	 (0x80000000) // EBI Chip Select 7 base address
+#define AT91C_EBI_CS7_SIZE	 (0x10000000) // EBI Chip Select 7 size in byte (262144 Kbytes)
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/flash.icf b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/flash.icf
new file mode 100644
index 0000000..c1755de
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/flash.icf
@@ -0,0 +1,48 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x200000;
+define symbol __ICFEDIT_region_ROM_end__     = 0x21FFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x300000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x303FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_startup__  = 0x100;
+define symbol __ICFEDIT_size_vectors__  = 0x100;
+define symbol __ICFEDIT_size_cstack__   = 0x1000;
+define symbol __ICFEDIT_size_svcstack__ = 0x60;
+define symbol __ICFEDIT_size_irqstack__ = 0x60;
+define symbol __ICFEDIT_size_heap__     = 0x0;
+/*-Exports-*/
+export symbol __ICFEDIT_region_ROM_start__;
+export symbol __ICFEDIT_region_ROM_end__;
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+export symbol __ICFEDIT_size_startup__;
+export symbol __ICFEDIT_size_vectors__;
+export symbol __ICFEDIT_size_cstack__;
+export symbol __ICFEDIT_size_svcstack__;
+export symbol __ICFEDIT_size_irqstack__;
+export symbol __ICFEDIT_size_heap__;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region STA_region = mem:[from __ICFEDIT_region_ROM_start__ size __ICFEDIT_size_startup__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_ROM_end__];
+define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+initialize by copy { section .vectors };
+do not initialize  { section .noinit };
+
+place in STA_region { section .cstartup };
+place in ROM_region { readonly };
+place in VEC_region { section .vectors };
+place in RAM_region { readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/sdram.icf b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/sdram.icf
new file mode 100644
index 0000000..f79413b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/sdram.icf
@@ -0,0 +1,46 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_SDRAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_SDRAM_end__   = 0x21FFFFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x300000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x303FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_startup__  = 0x100;
+define symbol __ICFEDIT_size_vectors__  = 0x100;
+define symbol __ICFEDIT_size_cstack__   = 0x1000;
+define symbol __ICFEDIT_size_svcstack__ = 0x60;
+define symbol __ICFEDIT_size_irqstack__ = 0x60;
+define symbol __ICFEDIT_size_heap__     = 0x0;
+/*-Exports-*/
+export symbol __ICFEDIT_region_SDRAM_start__;
+export symbol __ICFEDIT_region_SDRAM_end__;
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+export symbol __ICFEDIT_size_startup__;
+export symbol __ICFEDIT_size_vectors__;
+export symbol __ICFEDIT_size_cstack__;
+export symbol __ICFEDIT_size_svcstack__;
+export symbol __ICFEDIT_size_irqstack__;
+export symbol __ICFEDIT_size_heap__;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region STA_region =   mem:[from __ICFEDIT_region_SDRAM_start__ size __ICFEDIT_size_startup__];
+define region SDRAM_region = mem:[from __ICFEDIT_region_SDRAM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_SDRAM_end__];
+define region VEC_region =   mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
+define region RAM_region =   mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { section .vectors };
+do not initialize  { section .noinit };
+
+place in STA_region { section .cstartup };
+place in VEC_region { section .vectors };
+place in SDRAM_region { readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/sram.icf b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/sram.icf
new file mode 100644
index 0000000..45d75b2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe128/sram.icf
@@ -0,0 +1,36 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__   = 0x300000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x303FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_vectors__  = 0x100;
+define symbol __ICFEDIT_size_cstack__   = 0x800;
+define symbol __ICFEDIT_size_svcstack__ = 0x60;
+define symbol __ICFEDIT_size_irqstack__ = 0x60;
+define symbol __ICFEDIT_size_heap__     = 0x0;
+/*-Exports-*/
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+export symbol __ICFEDIT_size_vectors__;
+export symbol __ICFEDIT_size_cstack__;
+export symbol __ICFEDIT_size_svcstack__;
+export symbol __ICFEDIT_size_irqstack__;
+export symbol __ICFEDIT_size_heap__;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+do not initialize  { section .noinit };
+
+place in VEC_region { section .vectors };
+place in RAM_region { section .cstartup, readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/AT91SAM9XE256.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/AT91SAM9XE256.h
new file mode 100644
index 0000000..861c849
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/AT91SAM9XE256.h
@@ -0,0 +1,4042 @@
+//  ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+//  ----------------------------------------------------------------------------
+//  Copyright (c) 2006, Atmel Corporation
+// 
+//  All rights reserved.
+// 
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions are met:
+// 
+//  - Redistributions of source code must retain the above copyright notice,
+//  this list of conditions and the disclaimer below.
+// 
+//  - Redistributions in binary form must reproduce the above copyright notice,
+//  this list of conditions and the disclaimer below in the documentation and/or
+//  other materials provided with the distribution. 
+// 
+//  Atmel's name may not be used to endorse or promote products derived from
+//  this software without specific prior written permission. 
+//  
+//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  ----------------------------------------------------------------------------
+// File Name           : AT91SAM9XE256.h
+// Object              : AT91SAM9XE256 definitions
+// Generated           : AT91 SW Application Group  02/13/2008 (18:26:11)
+// 
+// CVS Reference       : /AT91SAM9XE256.pl/1.3/Wed Jan 30 13:59:12 2008//
+// CVS Reference       : /SYS_SAM9260.pl/1.2/Wed Feb 13 13:29:23 2008//
+// CVS Reference       : /HMATRIX1_SAM9260.pl/1.7/Mon Apr 23 10:39:45 2007//
+// CVS Reference       : /CCR_SAM9260.pl/1.2/Mon Apr 16 10:47:39 2007//
+// CVS Reference       : /PMC_SAM9262.pl/1.4/Mon Mar  7 18:03:13 2005//
+// CVS Reference       : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
+// CVS Reference       : /HSDRAMC1_6100A.pl/1.2/Mon Aug  9 10:52:25 2004//
+// CVS Reference       : /HSMC3_6105A.pl/1.4/Tue Nov 16 09:16:23 2004//
+// CVS Reference       : /AIC_6075A.pl/1.1/Mon Jul 12 17:04:01 2004//
+// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 09:02:11 2005//
+// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
+// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:29:42 2005//
+// CVS Reference       : /RSTC_6098A.pl/1.3/Thu Nov  4 13:57:00 2004//
+// CVS Reference       : /SHDWC_6122A.pl/1.3/Wed Oct  6 14:16:58 2004//
+// CVS Reference       : /RTTC_6081A.pl/1.2/Thu Nov  4 13:57:22 2004//
+// CVS Reference       : /PITC_6079A.pl/1.2/Thu Nov  4 13:56:22 2004//
+// CVS Reference       : /WDTC_6080A.pl/1.3/Thu Nov  4 13:58:52 2004//
+// CVS Reference       : /EFC2_IGS036.pl/1.2/Fri Nov 10 10:47:53 2006//
+// CVS Reference       : /TC_6082A.pl/1.7/Wed Mar  9 16:31:51 2005//
+// CVS Reference       : /MCI_6101E.pl/1.1/Fri Jun  3 13:20:23 2005//
+// CVS Reference       : /TWI_6061B.pl/1.2/Fri Aug  4 08:53:02 2006//
+// CVS Reference       : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
+// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//
+// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
+// CVS Reference       : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//
+// CVS Reference       : /UDP_6ept_puon.pl/1.1/Wed Aug 30 14:20:53 2006//
+// CVS Reference       : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005//
+// CVS Reference       : /EBI_SAM9260.pl/1.1/Fri Sep 30 12:12:14 2005//
+// CVS Reference       : /HECC_6143A.pl/1.1/Wed Feb  9 17:16:57 2005//
+// CVS Reference       : /ISI_xxxxx.pl/1.3/Thu Mar  3 11:11:48 2005//
+//  ----------------------------------------------------------------------------
+
+#ifndef AT91SAM9XE256_H
+#define AT91SAM9XE256_H
+
+#ifndef __ASSEMBLY__
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+#define AT91_CAST(a) (a)
+#else
+#define AT91_CAST(a)
+#endif
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SYS {
+	AT91_REG	 Reserved0[2560]; 	// 
+	AT91_REG	 ECC_CR; 	//  ECC reset register
+	AT91_REG	 ECC_MR; 	//  ECC Page size register
+	AT91_REG	 ECC_SR; 	//  ECC Status register
+	AT91_REG	 ECC_PR; 	//  ECC Parity register
+	AT91_REG	 ECC_NPR; 	//  ECC Parity N register
+	AT91_REG	 Reserved1[58]; 	// 
+	AT91_REG	 ECC_VR; 	//  ECC Version register
+	AT91_REG	 Reserved2[64]; 	// 
+	AT91_REG	 SDRAMC_MR; 	// SDRAM Controller Mode Register
+	AT91_REG	 SDRAMC_TR; 	// SDRAM Controller Refresh Timer Register
+	AT91_REG	 SDRAMC_CR; 	// SDRAM Controller Configuration Register
+	AT91_REG	 SDRAMC_HSR; 	// SDRAM Controller High Speed Register
+	AT91_REG	 SDRAMC_LPR; 	// SDRAM Controller Low Power Register
+	AT91_REG	 SDRAMC_IER; 	// SDRAM Controller Interrupt Enable Register
+	AT91_REG	 SDRAMC_IDR; 	// SDRAM Controller Interrupt Disable Register
+	AT91_REG	 SDRAMC_IMR; 	// SDRAM Controller Interrupt Mask Register
+	AT91_REG	 SDRAMC_ISR; 	// SDRAM Controller Interrupt Mask Register
+	AT91_REG	 SDRAMC_MDR; 	// SDRAM Memory Device Register
+	AT91_REG	 Reserved3[118]; 	// 
+	AT91_REG	 SMC_SETUP0; 	//  Setup Register for CS 0
+	AT91_REG	 SMC_PULSE0; 	//  Pulse Register for CS 0
+	AT91_REG	 SMC_CYCLE0; 	//  Cycle Register for CS 0
+	AT91_REG	 SMC_CTRL0; 	//  Control Register for CS 0
+	AT91_REG	 SMC_SETUP1; 	//  Setup Register for CS 1
+	AT91_REG	 SMC_PULSE1; 	//  Pulse Register for CS 1
+	AT91_REG	 SMC_CYCLE1; 	//  Cycle Register for CS 1
+	AT91_REG	 SMC_CTRL1; 	//  Control Register for CS 1
+	AT91_REG	 SMC_SETUP2; 	//  Setup Register for CS 2
+	AT91_REG	 SMC_PULSE2; 	//  Pulse Register for CS 2
+	AT91_REG	 SMC_CYCLE2; 	//  Cycle Register for CS 2
+	AT91_REG	 SMC_CTRL2; 	//  Control Register for CS 2
+	AT91_REG	 SMC_SETUP3; 	//  Setup Register for CS 3
+	AT91_REG	 SMC_PULSE3; 	//  Pulse Register for CS 3
+	AT91_REG	 SMC_CYCLE3; 	//  Cycle Register for CS 3
+	AT91_REG	 SMC_CTRL3; 	//  Control Register for CS 3
+	AT91_REG	 SMC_SETUP4; 	//  Setup Register for CS 4
+	AT91_REG	 SMC_PULSE4; 	//  Pulse Register for CS 4
+	AT91_REG	 SMC_CYCLE4; 	//  Cycle Register for CS 4
+	AT91_REG	 SMC_CTRL4; 	//  Control Register for CS 4
+	AT91_REG	 SMC_SETUP5; 	//  Setup Register for CS 5
+	AT91_REG	 SMC_PULSE5; 	//  Pulse Register for CS 5
+	AT91_REG	 SMC_CYCLE5; 	//  Cycle Register for CS 5
+	AT91_REG	 SMC_CTRL5; 	//  Control Register for CS 5
+	AT91_REG	 SMC_SETUP6; 	//  Setup Register for CS 6
+	AT91_REG	 SMC_PULSE6; 	//  Pulse Register for CS 6
+	AT91_REG	 SMC_CYCLE6; 	//  Cycle Register for CS 6
+	AT91_REG	 SMC_CTRL6; 	//  Control Register for CS 6
+	AT91_REG	 SMC_SETUP7; 	//  Setup Register for CS 7
+	AT91_REG	 SMC_PULSE7; 	//  Pulse Register for CS 7
+	AT91_REG	 SMC_CYCLE7; 	//  Cycle Register for CS 7
+	AT91_REG	 SMC_CTRL7; 	//  Control Register for CS 7
+	AT91_REG	 Reserved4[96]; 	// 
+	AT91_REG	 MATRIX_MCFG0; 	//  Master Configuration Register 0 (ram96k)     
+	AT91_REG	 MATRIX_MCFG1; 	//  Master Configuration Register 1 (rom)    
+	AT91_REG	 MATRIX_MCFG2; 	//  Master Configuration Register 2 (hperiphs) 
+	AT91_REG	 MATRIX_MCFG3; 	//  Master Configuration Register 3 (ebi)
+	AT91_REG	 MATRIX_MCFG4; 	//  Master Configuration Register 4 (bridge)    
+	AT91_REG	 MATRIX_MCFG5; 	//  Master Configuration Register 5 (mailbox)    
+	AT91_REG	 MATRIX_MCFG6; 	//  Master Configuration Register 6 (ram16k)  
+	AT91_REG	 MATRIX_MCFG7; 	//  Master Configuration Register 7 (teak_prog)     
+	AT91_REG	 Reserved5[8]; 	// 
+	AT91_REG	 MATRIX_SCFG0; 	//  Slave Configuration Register 0 (ram96k)     
+	AT91_REG	 MATRIX_SCFG1; 	//  Slave Configuration Register 1 (rom)    
+	AT91_REG	 MATRIX_SCFG2; 	//  Slave Configuration Register 2 (hperiphs) 
+	AT91_REG	 MATRIX_SCFG3; 	//  Slave Configuration Register 3 (ebi)
+	AT91_REG	 MATRIX_SCFG4; 	//  Slave Configuration Register 4 (bridge)    
+	AT91_REG	 Reserved6[11]; 	// 
+	AT91_REG	 MATRIX_PRAS0; 	//  PRAS0 (ram0) 
+	AT91_REG	 MATRIX_PRBS0; 	//  PRBS0 (ram0) 
+	AT91_REG	 MATRIX_PRAS1; 	//  PRAS1 (ram1) 
+	AT91_REG	 MATRIX_PRBS1; 	//  PRBS1 (ram1) 
+	AT91_REG	 MATRIX_PRAS2; 	//  PRAS2 (ram2) 
+	AT91_REG	 MATRIX_PRBS2; 	//  PRBS2 (ram2) 
+	AT91_REG	 MATRIX_PRAS3; 	//  PRAS3 : usb_dev_hs
+	AT91_REG	 MATRIX_PRBS3; 	//  PRBS3 : usb_dev_hs
+	AT91_REG	 MATRIX_PRAS4; 	//  PRAS4 : ebi
+	AT91_REG	 MATRIX_PRBS4; 	//  PRBS4 : ebi
+	AT91_REG	 Reserved7[22]; 	// 
+	AT91_REG	 MATRIX_MRCR; 	//  Master Remp Control Register 
+	AT91_REG	 Reserved8[6]; 	// 
+	AT91_REG	 CCFG_EBICSA; 	//  EBI Chip Select Assignement Register
+	AT91_REG	 Reserved9[3]; 	// 
+	AT91_REG	 MATRIX_TEAKCFG; 	//  Slave 7 (teak_prog) Special Function Register
+	AT91_REG	 Reserved10[51]; 	// 
+	AT91_REG	 CCFG_MATRIXVERSION; 	//  Version Register
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved11[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved12[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+	AT91_REG	 Reserved13[45]; 	// 
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved14[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved15[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+	AT91_REG	 Reserved16[54]; 	// 
+	AT91_REG	 PIOA_PER; 	// PIO Enable Register
+	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOA_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved17[1]; 	// 
+	AT91_REG	 PIOA_OER; 	// Output Enable Register
+	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOA_OSR; 	// Output Status Register
+	AT91_REG	 Reserved18[1]; 	// 
+	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved19[1]; 	// 
+	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved20[1]; 	// 
+	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved21[1]; 	// 
+	AT91_REG	 PIOA_ASR; 	// Select A Register
+	AT91_REG	 PIOA_BSR; 	// Select B Register
+	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved22[9]; 	// 
+	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved23[213]; 	// 
+	AT91_REG	 PIOB_PER; 	// PIO Enable Register
+	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOB_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved24[1]; 	// 
+	AT91_REG	 PIOB_OER; 	// Output Enable Register
+	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOB_OSR; 	// Output Status Register
+	AT91_REG	 Reserved25[1]; 	// 
+	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved26[1]; 	// 
+	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved27[1]; 	// 
+	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved28[1]; 	// 
+	AT91_REG	 PIOB_ASR; 	// Select A Register
+	AT91_REG	 PIOB_BSR; 	// Select B Register
+	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved29[9]; 	// 
+	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved30[85]; 	// 
+	AT91_REG	 PIOC_PER; 	// PIO Enable Register
+	AT91_REG	 PIOC_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOC_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved31[1]; 	// 
+	AT91_REG	 PIOC_OER; 	// Output Enable Register
+	AT91_REG	 PIOC_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOC_OSR; 	// Output Status Register
+	AT91_REG	 Reserved32[1]; 	// 
+	AT91_REG	 PIOC_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOC_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOC_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved33[1]; 	// 
+	AT91_REG	 PIOC_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOC_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOC_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOC_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOC_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOC_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOC_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOC_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved34[1]; 	// 
+	AT91_REG	 PIOC_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOC_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOC_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved35[1]; 	// 
+	AT91_REG	 PIOC_ASR; 	// Select A Register
+	AT91_REG	 PIOC_BSR; 	// Select B Register
+	AT91_REG	 PIOC_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved36[9]; 	// 
+	AT91_REG	 PIOC_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOC_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOC_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved37[85]; 	// 
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved38[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved39[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 PMC_PLLAR; 	// PLL A Register
+	AT91_REG	 PMC_PLLBR; 	// PLL B Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved40[3]; 	// 
+	AT91_REG	 PMC_PCKR[8]; 	// Programmable Clock Register
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved41[36]; 	// 
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+	AT91_REG	 Reserved42[1]; 	// 
+	AT91_REG	 SHDWC_SHCR; 	// Shut Down Control Register
+	AT91_REG	 SHDWC_SHMR; 	// Shut Down Mode Register
+	AT91_REG	 SHDWC_SHSR; 	// Shut Down Status Register
+	AT91_REG	 Reserved43[1]; 	// 
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+	AT91_REG	 Reserved44[1]; 	// 
+	AT91_REG	 SYS_GPBR[4]; 	// General Purpose Register
+} AT91S_SYS, *AT91PS_SYS;
+#else
+#define SYS_GPBR        (AT91_CAST(AT91_REG *) 	0x00003D50) // (SYS_GPBR) General Purpose Register
+
+#endif
+// -------- GPBR : (SYS Offset: 0x3d50) GPBR General Purpose Register -------- 
+#define AT91C_GPBR_GPRV       (0x0 <<  0) // (SYS) General Purpose Register Value
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR External Bus Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_EBI {
+	AT91_REG	 EBI_DUMMY; 	// Dummy register - Do not use
+} AT91S_EBI, *AT91PS_EBI;
+#else
+#define EBI_DUMMY       (AT91_CAST(AT91_REG *) 	0x00000000) // (EBI_DUMMY) Dummy register - Do not use
+
+#endif
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Error Correction Code controller
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_ECC {
+	AT91_REG	 ECC_CR; 	//  ECC reset register
+	AT91_REG	 ECC_MR; 	//  ECC Page size register
+	AT91_REG	 ECC_SR; 	//  ECC Status register
+	AT91_REG	 ECC_PR; 	//  ECC Parity register
+	AT91_REG	 ECC_NPR; 	//  ECC Parity N register
+	AT91_REG	 Reserved0[58]; 	// 
+	AT91_REG	 ECC_VR; 	//  ECC Version register
+} AT91S_ECC, *AT91PS_ECC;
+#else
+#define ECC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (ECC_CR)  ECC reset register
+#define ECC_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (ECC_MR)  ECC Page size register
+#define ECC_SR          (AT91_CAST(AT91_REG *) 	0x00000008) // (ECC_SR)  ECC Status register
+#define ECC_PR          (AT91_CAST(AT91_REG *) 	0x0000000C) // (ECC_PR)  ECC Parity register
+#define ECC_NPR         (AT91_CAST(AT91_REG *) 	0x00000010) // (ECC_NPR)  ECC Parity N register
+#define ECC_VR          (AT91_CAST(AT91_REG *) 	0x000000FC) // (ECC_VR)  ECC Version register
+
+#endif
+// -------- ECC_CR : (ECC Offset: 0x0) ECC reset register -------- 
+#define AT91C_ECC_RST         (0x1 <<  0) // (ECC) ECC reset parity
+// -------- ECC_MR : (ECC Offset: 0x4) ECC page size register -------- 
+#define AT91C_ECC_PAGE_SIZE   (0x3 <<  0) // (ECC) Nand Flash page size
+// -------- ECC_SR : (ECC Offset: 0x8) ECC status register -------- 
+#define AT91C_ECC_RECERR      (0x1 <<  0) // (ECC) ECC error
+#define AT91C_ECC_ECCERR      (0x1 <<  1) // (ECC) ECC single error
+#define AT91C_ECC_MULERR      (0x1 <<  2) // (ECC) ECC_MULERR
+// -------- ECC_PR : (ECC Offset: 0xc) ECC parity register -------- 
+#define AT91C_ECC_BITADDR     (0xF <<  0) // (ECC) Bit address error
+#define AT91C_ECC_WORDADDR    (0xFFF <<  4) // (ECC) address of the failing bit
+// -------- ECC_NPR : (ECC Offset: 0x10) ECC N parity register -------- 
+#define AT91C_ECC_NPARITY     (0xFFFF <<  0) // (ECC) ECC parity N 
+// -------- ECC_VR : (ECC Offset: 0xfc) ECC version register -------- 
+#define AT91C_ECC_VR          (0xF <<  0) // (ECC) ECC version register
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR SDRAM Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SDRAMC {
+	AT91_REG	 SDRAMC_MR; 	// SDRAM Controller Mode Register
+	AT91_REG	 SDRAMC_TR; 	// SDRAM Controller Refresh Timer Register
+	AT91_REG	 SDRAMC_CR; 	// SDRAM Controller Configuration Register
+	AT91_REG	 SDRAMC_HSR; 	// SDRAM Controller High Speed Register
+	AT91_REG	 SDRAMC_LPR; 	// SDRAM Controller Low Power Register
+	AT91_REG	 SDRAMC_IER; 	// SDRAM Controller Interrupt Enable Register
+	AT91_REG	 SDRAMC_IDR; 	// SDRAM Controller Interrupt Disable Register
+	AT91_REG	 SDRAMC_IMR; 	// SDRAM Controller Interrupt Mask Register
+	AT91_REG	 SDRAMC_ISR; 	// SDRAM Controller Interrupt Mask Register
+	AT91_REG	 SDRAMC_MDR; 	// SDRAM Memory Device Register
+} AT91S_SDRAMC, *AT91PS_SDRAMC;
+#else
+#define SDRAMC_MR       (AT91_CAST(AT91_REG *) 	0x00000000) // (SDRAMC_MR) SDRAM Controller Mode Register
+#define SDRAMC_TR       (AT91_CAST(AT91_REG *) 	0x00000004) // (SDRAMC_TR) SDRAM Controller Refresh Timer Register
+#define SDRAMC_CR       (AT91_CAST(AT91_REG *) 	0x00000008) // (SDRAMC_CR) SDRAM Controller Configuration Register
+#define SDRAMC_HSR      (AT91_CAST(AT91_REG *) 	0x0000000C) // (SDRAMC_HSR) SDRAM Controller High Speed Register
+#define SDRAMC_LPR      (AT91_CAST(AT91_REG *) 	0x00000010) // (SDRAMC_LPR) SDRAM Controller Low Power Register
+#define SDRAMC_IER      (AT91_CAST(AT91_REG *) 	0x00000014) // (SDRAMC_IER) SDRAM Controller Interrupt Enable Register
+#define SDRAMC_IDR      (AT91_CAST(AT91_REG *) 	0x00000018) // (SDRAMC_IDR) SDRAM Controller Interrupt Disable Register
+#define SDRAMC_IMR      (AT91_CAST(AT91_REG *) 	0x0000001C) // (SDRAMC_IMR) SDRAM Controller Interrupt Mask Register
+#define SDRAMC_ISR      (AT91_CAST(AT91_REG *) 	0x00000020) // (SDRAMC_ISR) SDRAM Controller Interrupt Mask Register
+#define SDRAMC_MDR      (AT91_CAST(AT91_REG *) 	0x00000024) // (SDRAMC_MDR) SDRAM Memory Device Register
+
+#endif
+// -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register -------- 
+#define AT91C_SDRAMC_MODE     (0xF <<  0) // (SDRAMC) Mode
+#define 	AT91C_SDRAMC_MODE_NORMAL_CMD           (0x0) // (SDRAMC) Normal Mode
+#define 	AT91C_SDRAMC_MODE_NOP_CMD              (0x1) // (SDRAMC) Issue a NOP Command at every access
+#define 	AT91C_SDRAMC_MODE_PRCGALL_CMD          (0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access
+#define 	AT91C_SDRAMC_MODE_LMR_CMD              (0x3) // (SDRAMC) Issue a Load Mode Register at every access
+#define 	AT91C_SDRAMC_MODE_RFSH_CMD             (0x4) // (SDRAMC) Issue a Refresh
+#define 	AT91C_SDRAMC_MODE_EXT_LMR_CMD          (0x5) // (SDRAMC) Issue an Extended Load Mode Register
+#define 	AT91C_SDRAMC_MODE_DEEP_CMD             (0x6) // (SDRAMC) Enter Deep Power Mode
+// -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register -------- 
+#define AT91C_SDRAMC_COUNT    (0xFFF <<  0) // (SDRAMC) Refresh Counter
+// -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register -------- 
+#define AT91C_SDRAMC_NC       (0x3 <<  0) // (SDRAMC) Number of Column Bits
+#define 	AT91C_SDRAMC_NC_8                    (0x0) // (SDRAMC) 8 Bits
+#define 	AT91C_SDRAMC_NC_9                    (0x1) // (SDRAMC) 9 Bits
+#define 	AT91C_SDRAMC_NC_10                   (0x2) // (SDRAMC) 10 Bits
+#define 	AT91C_SDRAMC_NC_11                   (0x3) // (SDRAMC) 11 Bits
+#define AT91C_SDRAMC_NR       (0x3 <<  2) // (SDRAMC) Number of Row Bits
+#define 	AT91C_SDRAMC_NR_11                   (0x0 <<  2) // (SDRAMC) 11 Bits
+#define 	AT91C_SDRAMC_NR_12                   (0x1 <<  2) // (SDRAMC) 12 Bits
+#define 	AT91C_SDRAMC_NR_13                   (0x2 <<  2) // (SDRAMC) 13 Bits
+#define AT91C_SDRAMC_NB       (0x1 <<  4) // (SDRAMC) Number of Banks
+#define 	AT91C_SDRAMC_NB_2_BANKS              (0x0 <<  4) // (SDRAMC) 2 banks
+#define 	AT91C_SDRAMC_NB_4_BANKS              (0x1 <<  4) // (SDRAMC) 4 banks
+#define AT91C_SDRAMC_CAS      (0x3 <<  5) // (SDRAMC) CAS Latency
+#define 	AT91C_SDRAMC_CAS_2                    (0x2 <<  5) // (SDRAMC) 2 cycles
+#define 	AT91C_SDRAMC_CAS_3                    (0x3 <<  5) // (SDRAMC) 3 cycles
+#define AT91C_SDRAMC_DBW      (0x1 <<  7) // (SDRAMC) Data Bus Width
+#define 	AT91C_SDRAMC_DBW_32_BITS              (0x0 <<  7) // (SDRAMC) 32 Bits datas bus
+#define 	AT91C_SDRAMC_DBW_16_BITS              (0x1 <<  7) // (SDRAMC) 16 Bits datas bus
+#define AT91C_SDRAMC_TWR      (0xF <<  8) // (SDRAMC) Number of Write Recovery Time Cycles
+#define 	AT91C_SDRAMC_TWR_0                    (0x0 <<  8) // (SDRAMC) Value :  0
+#define 	AT91C_SDRAMC_TWR_1                    (0x1 <<  8) // (SDRAMC) Value :  1
+#define 	AT91C_SDRAMC_TWR_2                    (0x2 <<  8) // (SDRAMC) Value :  2
+#define 	AT91C_SDRAMC_TWR_3                    (0x3 <<  8) // (SDRAMC) Value :  3
+#define 	AT91C_SDRAMC_TWR_4                    (0x4 <<  8) // (SDRAMC) Value :  4
+#define 	AT91C_SDRAMC_TWR_5                    (0x5 <<  8) // (SDRAMC) Value :  5
+#define 	AT91C_SDRAMC_TWR_6                    (0x6 <<  8) // (SDRAMC) Value :  6
+#define 	AT91C_SDRAMC_TWR_7                    (0x7 <<  8) // (SDRAMC) Value :  7
+#define 	AT91C_SDRAMC_TWR_8                    (0x8 <<  8) // (SDRAMC) Value :  8
+#define 	AT91C_SDRAMC_TWR_9                    (0x9 <<  8) // (SDRAMC) Value :  9
+#define 	AT91C_SDRAMC_TWR_10                   (0xA <<  8) // (SDRAMC) Value : 10
+#define 	AT91C_SDRAMC_TWR_11                   (0xB <<  8) // (SDRAMC) Value : 11
+#define 	AT91C_SDRAMC_TWR_12                   (0xC <<  8) // (SDRAMC) Value : 12
+#define 	AT91C_SDRAMC_TWR_13                   (0xD <<  8) // (SDRAMC) Value : 13
+#define 	AT91C_SDRAMC_TWR_14                   (0xE <<  8) // (SDRAMC) Value : 14
+#define 	AT91C_SDRAMC_TWR_15                   (0xF <<  8) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TRC      (0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles
+#define 	AT91C_SDRAMC_TRC_0                    (0x0 << 12) // (SDRAMC) Value :  0
+#define 	AT91C_SDRAMC_TRC_1                    (0x1 << 12) // (SDRAMC) Value :  1
+#define 	AT91C_SDRAMC_TRC_2                    (0x2 << 12) // (SDRAMC) Value :  2
+#define 	AT91C_SDRAMC_TRC_3                    (0x3 << 12) // (SDRAMC) Value :  3
+#define 	AT91C_SDRAMC_TRC_4                    (0x4 << 12) // (SDRAMC) Value :  4
+#define 	AT91C_SDRAMC_TRC_5                    (0x5 << 12) // (SDRAMC) Value :  5
+#define 	AT91C_SDRAMC_TRC_6                    (0x6 << 12) // (SDRAMC) Value :  6
+#define 	AT91C_SDRAMC_TRC_7                    (0x7 << 12) // (SDRAMC) Value :  7
+#define 	AT91C_SDRAMC_TRC_8                    (0x8 << 12) // (SDRAMC) Value :  8
+#define 	AT91C_SDRAMC_TRC_9                    (0x9 << 12) // (SDRAMC) Value :  9
+#define 	AT91C_SDRAMC_TRC_10                   (0xA << 12) // (SDRAMC) Value : 10
+#define 	AT91C_SDRAMC_TRC_11                   (0xB << 12) // (SDRAMC) Value : 11
+#define 	AT91C_SDRAMC_TRC_12                   (0xC << 12) // (SDRAMC) Value : 12
+#define 	AT91C_SDRAMC_TRC_13                   (0xD << 12) // (SDRAMC) Value : 13
+#define 	AT91C_SDRAMC_TRC_14                   (0xE << 12) // (SDRAMC) Value : 14
+#define 	AT91C_SDRAMC_TRC_15                   (0xF << 12) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TRP      (0xF << 16) // (SDRAMC) Number of RAS Precharge Time Cycles
+#define 	AT91C_SDRAMC_TRP_0                    (0x0 << 16) // (SDRAMC) Value :  0
+#define 	AT91C_SDRAMC_TRP_1                    (0x1 << 16) // (SDRAMC) Value :  1
+#define 	AT91C_SDRAMC_TRP_2                    (0x2 << 16) // (SDRAMC) Value :  2
+#define 	AT91C_SDRAMC_TRP_3                    (0x3 << 16) // (SDRAMC) Value :  3
+#define 	AT91C_SDRAMC_TRP_4                    (0x4 << 16) // (SDRAMC) Value :  4
+#define 	AT91C_SDRAMC_TRP_5                    (0x5 << 16) // (SDRAMC) Value :  5
+#define 	AT91C_SDRAMC_TRP_6                    (0x6 << 16) // (SDRAMC) Value :  6
+#define 	AT91C_SDRAMC_TRP_7                    (0x7 << 16) // (SDRAMC) Value :  7
+#define 	AT91C_SDRAMC_TRP_8                    (0x8 << 16) // (SDRAMC) Value :  8
+#define 	AT91C_SDRAMC_TRP_9                    (0x9 << 16) // (SDRAMC) Value :  9
+#define 	AT91C_SDRAMC_TRP_10                   (0xA << 16) // (SDRAMC) Value : 10
+#define 	AT91C_SDRAMC_TRP_11                   (0xB << 16) // (SDRAMC) Value : 11
+#define 	AT91C_SDRAMC_TRP_12                   (0xC << 16) // (SDRAMC) Value : 12
+#define 	AT91C_SDRAMC_TRP_13                   (0xD << 16) // (SDRAMC) Value : 13
+#define 	AT91C_SDRAMC_TRP_14                   (0xE << 16) // (SDRAMC) Value : 14
+#define 	AT91C_SDRAMC_TRP_15                   (0xF << 16) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TRCD     (0xF << 20) // (SDRAMC) Number of RAS to CAS Delay Cycles
+#define 	AT91C_SDRAMC_TRCD_0                    (0x0 << 20) // (SDRAMC) Value :  0
+#define 	AT91C_SDRAMC_TRCD_1                    (0x1 << 20) // (SDRAMC) Value :  1
+#define 	AT91C_SDRAMC_TRCD_2                    (0x2 << 20) // (SDRAMC) Value :  2
+#define 	AT91C_SDRAMC_TRCD_3                    (0x3 << 20) // (SDRAMC) Value :  3
+#define 	AT91C_SDRAMC_TRCD_4                    (0x4 << 20) // (SDRAMC) Value :  4
+#define 	AT91C_SDRAMC_TRCD_5                    (0x5 << 20) // (SDRAMC) Value :  5
+#define 	AT91C_SDRAMC_TRCD_6                    (0x6 << 20) // (SDRAMC) Value :  6
+#define 	AT91C_SDRAMC_TRCD_7                    (0x7 << 20) // (SDRAMC) Value :  7
+#define 	AT91C_SDRAMC_TRCD_8                    (0x8 << 20) // (SDRAMC) Value :  8
+#define 	AT91C_SDRAMC_TRCD_9                    (0x9 << 20) // (SDRAMC) Value :  9
+#define 	AT91C_SDRAMC_TRCD_10                   (0xA << 20) // (SDRAMC) Value : 10
+#define 	AT91C_SDRAMC_TRCD_11                   (0xB << 20) // (SDRAMC) Value : 11
+#define 	AT91C_SDRAMC_TRCD_12                   (0xC << 20) // (SDRAMC) Value : 12
+#define 	AT91C_SDRAMC_TRCD_13                   (0xD << 20) // (SDRAMC) Value : 13
+#define 	AT91C_SDRAMC_TRCD_14                   (0xE << 20) // (SDRAMC) Value : 14
+#define 	AT91C_SDRAMC_TRCD_15                   (0xF << 20) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TRAS     (0xF << 24) // (SDRAMC) Number of RAS Active Time Cycles
+#define 	AT91C_SDRAMC_TRAS_0                    (0x0 << 24) // (SDRAMC) Value :  0
+#define 	AT91C_SDRAMC_TRAS_1                    (0x1 << 24) // (SDRAMC) Value :  1
+#define 	AT91C_SDRAMC_TRAS_2                    (0x2 << 24) // (SDRAMC) Value :  2
+#define 	AT91C_SDRAMC_TRAS_3                    (0x3 << 24) // (SDRAMC) Value :  3
+#define 	AT91C_SDRAMC_TRAS_4                    (0x4 << 24) // (SDRAMC) Value :  4
+#define 	AT91C_SDRAMC_TRAS_5                    (0x5 << 24) // (SDRAMC) Value :  5
+#define 	AT91C_SDRAMC_TRAS_6                    (0x6 << 24) // (SDRAMC) Value :  6
+#define 	AT91C_SDRAMC_TRAS_7                    (0x7 << 24) // (SDRAMC) Value :  7
+#define 	AT91C_SDRAMC_TRAS_8                    (0x8 << 24) // (SDRAMC) Value :  8
+#define 	AT91C_SDRAMC_TRAS_9                    (0x9 << 24) // (SDRAMC) Value :  9
+#define 	AT91C_SDRAMC_TRAS_10                   (0xA << 24) // (SDRAMC) Value : 10
+#define 	AT91C_SDRAMC_TRAS_11                   (0xB << 24) // (SDRAMC) Value : 11
+#define 	AT91C_SDRAMC_TRAS_12                   (0xC << 24) // (SDRAMC) Value : 12
+#define 	AT91C_SDRAMC_TRAS_13                   (0xD << 24) // (SDRAMC) Value : 13
+#define 	AT91C_SDRAMC_TRAS_14                   (0xE << 24) // (SDRAMC) Value : 14
+#define 	AT91C_SDRAMC_TRAS_15                   (0xF << 24) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TXSR     (0xF << 28) // (SDRAMC) Number of Command Recovery Time Cycles
+#define 	AT91C_SDRAMC_TXSR_0                    (0x0 << 28) // (SDRAMC) Value :  0
+#define 	AT91C_SDRAMC_TXSR_1                    (0x1 << 28) // (SDRAMC) Value :  1
+#define 	AT91C_SDRAMC_TXSR_2                    (0x2 << 28) // (SDRAMC) Value :  2
+#define 	AT91C_SDRAMC_TXSR_3                    (0x3 << 28) // (SDRAMC) Value :  3
+#define 	AT91C_SDRAMC_TXSR_4                    (0x4 << 28) // (SDRAMC) Value :  4
+#define 	AT91C_SDRAMC_TXSR_5                    (0x5 << 28) // (SDRAMC) Value :  5
+#define 	AT91C_SDRAMC_TXSR_6                    (0x6 << 28) // (SDRAMC) Value :  6
+#define 	AT91C_SDRAMC_TXSR_7                    (0x7 << 28) // (SDRAMC) Value :  7
+#define 	AT91C_SDRAMC_TXSR_8                    (0x8 << 28) // (SDRAMC) Value :  8
+#define 	AT91C_SDRAMC_TXSR_9                    (0x9 << 28) // (SDRAMC) Value :  9
+#define 	AT91C_SDRAMC_TXSR_10                   (0xA << 28) // (SDRAMC) Value : 10
+#define 	AT91C_SDRAMC_TXSR_11                   (0xB << 28) // (SDRAMC) Value : 11
+#define 	AT91C_SDRAMC_TXSR_12                   (0xC << 28) // (SDRAMC) Value : 12
+#define 	AT91C_SDRAMC_TXSR_13                   (0xD << 28) // (SDRAMC) Value : 13
+#define 	AT91C_SDRAMC_TXSR_14                   (0xE << 28) // (SDRAMC) Value : 14
+#define 	AT91C_SDRAMC_TXSR_15                   (0xF << 28) // (SDRAMC) Value : 15
+// -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register -------- 
+#define AT91C_SDRAMC_DA       (0x1 <<  0) // (SDRAMC) Decode Cycle Enable Bit
+#define 	AT91C_SDRAMC_DA_DISABLE              (0x0) // (SDRAMC) Disable Decode Cycle
+#define 	AT91C_SDRAMC_DA_ENABLE               (0x1) // (SDRAMC) Enable Decode Cycle
+// -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register -------- 
+#define AT91C_SDRAMC_LPCB     (0x3 <<  0) // (SDRAMC) Low-power Configurations
+#define 	AT91C_SDRAMC_LPCB_DISABLE              (0x0) // (SDRAMC) Disable Low Power Features
+#define 	AT91C_SDRAMC_LPCB_SELF_REFRESH         (0x1) // (SDRAMC) Enable SELF_REFRESH
+#define 	AT91C_SDRAMC_LPCB_POWER_DOWN           (0x2) // (SDRAMC) Enable POWER_DOWN
+#define 	AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN      (0x3) // (SDRAMC) Enable DEEP_POWER_DOWN
+#define AT91C_SDRAMC_PASR     (0x7 <<  4) // (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM)
+#define AT91C_SDRAMC_TCSR     (0x3 <<  8) // (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM)
+#define AT91C_SDRAMC_DS       (0x3 << 10) // (SDRAMC) Drive Strenght (only for Low Power SDRAM)
+#define AT91C_SDRAMC_TIMEOUT  (0x3 << 12) // (SDRAMC) Time to define when Low Power Mode is enabled
+#define 	AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES         (0x0 << 12) // (SDRAMC) Activate SDRAM Low Power Mode Immediately
+#define 	AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES        (0x1 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
+#define 	AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES       (0x2 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
+// -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- 
+#define AT91C_SDRAMC_RES      (0x1 <<  0) // (SDRAMC) Refresh Error Status
+// -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- 
+// -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- 
+// -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- 
+// -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register -------- 
+#define AT91C_SDRAMC_MD       (0x3 <<  0) // (SDRAMC) Memory Device Type
+#define 	AT91C_SDRAMC_MD_SDRAM                (0x0) // (SDRAMC) SDRAM Mode
+#define 	AT91C_SDRAMC_MD_LOW_POWER_SDRAM      (0x1) // (SDRAMC) SDRAM Low Power Mode
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Static Memory Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SMC {
+	AT91_REG	 SMC_SETUP0; 	//  Setup Register for CS 0
+	AT91_REG	 SMC_PULSE0; 	//  Pulse Register for CS 0
+	AT91_REG	 SMC_CYCLE0; 	//  Cycle Register for CS 0
+	AT91_REG	 SMC_CTRL0; 	//  Control Register for CS 0
+	AT91_REG	 SMC_SETUP1; 	//  Setup Register for CS 1
+	AT91_REG	 SMC_PULSE1; 	//  Pulse Register for CS 1
+	AT91_REG	 SMC_CYCLE1; 	//  Cycle Register for CS 1
+	AT91_REG	 SMC_CTRL1; 	//  Control Register for CS 1
+	AT91_REG	 SMC_SETUP2; 	//  Setup Register for CS 2
+	AT91_REG	 SMC_PULSE2; 	//  Pulse Register for CS 2
+	AT91_REG	 SMC_CYCLE2; 	//  Cycle Register for CS 2
+	AT91_REG	 SMC_CTRL2; 	//  Control Register for CS 2
+	AT91_REG	 SMC_SETUP3; 	//  Setup Register for CS 3
+	AT91_REG	 SMC_PULSE3; 	//  Pulse Register for CS 3
+	AT91_REG	 SMC_CYCLE3; 	//  Cycle Register for CS 3
+	AT91_REG	 SMC_CTRL3; 	//  Control Register for CS 3
+	AT91_REG	 SMC_SETUP4; 	//  Setup Register for CS 4
+	AT91_REG	 SMC_PULSE4; 	//  Pulse Register for CS 4
+	AT91_REG	 SMC_CYCLE4; 	//  Cycle Register for CS 4
+	AT91_REG	 SMC_CTRL4; 	//  Control Register for CS 4
+	AT91_REG	 SMC_SETUP5; 	//  Setup Register for CS 5
+	AT91_REG	 SMC_PULSE5; 	//  Pulse Register for CS 5
+	AT91_REG	 SMC_CYCLE5; 	//  Cycle Register for CS 5
+	AT91_REG	 SMC_CTRL5; 	//  Control Register for CS 5
+	AT91_REG	 SMC_SETUP6; 	//  Setup Register for CS 6
+	AT91_REG	 SMC_PULSE6; 	//  Pulse Register for CS 6
+	AT91_REG	 SMC_CYCLE6; 	//  Cycle Register for CS 6
+	AT91_REG	 SMC_CTRL6; 	//  Control Register for CS 6
+	AT91_REG	 SMC_SETUP7; 	//  Setup Register for CS 7
+	AT91_REG	 SMC_PULSE7; 	//  Pulse Register for CS 7
+	AT91_REG	 SMC_CYCLE7; 	//  Cycle Register for CS 7
+	AT91_REG	 SMC_CTRL7; 	//  Control Register for CS 7
+} AT91S_SMC, *AT91PS_SMC;
+#else
+#define SETUP0          (AT91_CAST(AT91_REG *) 	0x00000000) // (SETUP0)  Setup Register for CS 0
+#define PULSE0          (AT91_CAST(AT91_REG *) 	0x00000004) // (PULSE0)  Pulse Register for CS 0
+#define CYCLE0          (AT91_CAST(AT91_REG *) 	0x00000008) // (CYCLE0)  Cycle Register for CS 0
+#define CTRL0           (AT91_CAST(AT91_REG *) 	0x0000000C) // (CTRL0)  Control Register for CS 0
+#define SETUP1          (AT91_CAST(AT91_REG *) 	0x00000010) // (SETUP1)  Setup Register for CS 1
+#define PULSE1          (AT91_CAST(AT91_REG *) 	0x00000014) // (PULSE1)  Pulse Register for CS 1
+#define CYCLE1          (AT91_CAST(AT91_REG *) 	0x00000018) // (CYCLE1)  Cycle Register for CS 1
+#define CTRL1           (AT91_CAST(AT91_REG *) 	0x0000001C) // (CTRL1)  Control Register for CS 1
+#define SETUP2          (AT91_CAST(AT91_REG *) 	0x00000020) // (SETUP2)  Setup Register for CS 2
+#define PULSE2          (AT91_CAST(AT91_REG *) 	0x00000024) // (PULSE2)  Pulse Register for CS 2
+#define CYCLE2          (AT91_CAST(AT91_REG *) 	0x00000028) // (CYCLE2)  Cycle Register for CS 2
+#define CTRL2           (AT91_CAST(AT91_REG *) 	0x0000002C) // (CTRL2)  Control Register for CS 2
+#define SETUP3          (AT91_CAST(AT91_REG *) 	0x00000030) // (SETUP3)  Setup Register for CS 3
+#define PULSE3          (AT91_CAST(AT91_REG *) 	0x00000034) // (PULSE3)  Pulse Register for CS 3
+#define CYCLE3          (AT91_CAST(AT91_REG *) 	0x00000038) // (CYCLE3)  Cycle Register for CS 3
+#define CTRL3           (AT91_CAST(AT91_REG *) 	0x0000003C) // (CTRL3)  Control Register for CS 3
+#define SETUP4          (AT91_CAST(AT91_REG *) 	0x00000040) // (SETUP4)  Setup Register for CS 4
+#define PULSE4          (AT91_CAST(AT91_REG *) 	0x00000044) // (PULSE4)  Pulse Register for CS 4
+#define CYCLE4          (AT91_CAST(AT91_REG *) 	0x00000048) // (CYCLE4)  Cycle Register for CS 4
+#define CTRL4           (AT91_CAST(AT91_REG *) 	0x0000004C) // (CTRL4)  Control Register for CS 4
+#define SETUP5          (AT91_CAST(AT91_REG *) 	0x00000050) // (SETUP5)  Setup Register for CS 5
+#define PULSE5          (AT91_CAST(AT91_REG *) 	0x00000054) // (PULSE5)  Pulse Register for CS 5
+#define CYCLE5          (AT91_CAST(AT91_REG *) 	0x00000058) // (CYCLE5)  Cycle Register for CS 5
+#define CTRL5           (AT91_CAST(AT91_REG *) 	0x0000005C) // (CTRL5)  Control Register for CS 5
+#define SETUP6          (AT91_CAST(AT91_REG *) 	0x00000060) // (SETUP6)  Setup Register for CS 6
+#define PULSE6          (AT91_CAST(AT91_REG *) 	0x00000064) // (PULSE6)  Pulse Register for CS 6
+#define CYCLE6          (AT91_CAST(AT91_REG *) 	0x00000068) // (CYCLE6)  Cycle Register for CS 6
+#define CTRL6           (AT91_CAST(AT91_REG *) 	0x0000006C) // (CTRL6)  Control Register for CS 6
+#define SETUP7          (AT91_CAST(AT91_REG *) 	0x00000070) // (SETUP7)  Setup Register for CS 7
+#define PULSE7          (AT91_CAST(AT91_REG *) 	0x00000074) // (PULSE7)  Pulse Register for CS 7
+#define CYCLE7          (AT91_CAST(AT91_REG *) 	0x00000078) // (CYCLE7)  Cycle Register for CS 7
+#define CTRL7           (AT91_CAST(AT91_REG *) 	0x0000007C) // (CTRL7)  Control Register for CS 7
+
+#endif
+// -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x -------- 
+#define AT91C_SMC_NWESETUP    (0x3F <<  0) // (SMC) NWE Setup Length
+#define AT91C_SMC_NCSSETUPWR  (0x3F <<  8) // (SMC) NCS Setup Length in WRite Access
+#define AT91C_SMC_NRDSETUP    (0x3F << 16) // (SMC) NRD Setup Length
+#define AT91C_SMC_NCSSETUPRD  (0x3F << 24) // (SMC) NCS Setup Length in ReaD Access
+// -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x -------- 
+#define AT91C_SMC_NWEPULSE    (0x7F <<  0) // (SMC) NWE Pulse Length
+#define AT91C_SMC_NCSPULSEWR  (0x7F <<  8) // (SMC) NCS Pulse Length in WRite Access
+#define AT91C_SMC_NRDPULSE    (0x7F << 16) // (SMC) NRD Pulse Length
+#define AT91C_SMC_NCSPULSERD  (0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access
+// -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x -------- 
+#define AT91C_SMC_NWECYCLE    (0x1FF <<  0) // (SMC) Total Write Cycle Length
+#define AT91C_SMC_NRDCYCLE    (0x1FF << 16) // (SMC) Total Read Cycle Length
+// -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x -------- 
+#define AT91C_SMC_READMODE    (0x1 <<  0) // (SMC) Read Mode
+#define AT91C_SMC_WRITEMODE   (0x1 <<  1) // (SMC) Write Mode
+#define AT91C_SMC_NWAITM      (0x3 <<  4) // (SMC) NWAIT Mode
+#define 	AT91C_SMC_NWAITM_NWAIT_DISABLE        (0x0 <<  4) // (SMC) External NWAIT disabled.
+#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN  (0x2 <<  4) // (SMC) External NWAIT enabled in frozen mode.
+#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_READY   (0x3 <<  4) // (SMC) External NWAIT enabled in ready mode.
+#define AT91C_SMC_BAT         (0x1 <<  8) // (SMC) Byte Access Type
+#define 	AT91C_SMC_BAT_BYTE_SELECT          (0x0 <<  8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
+#define 	AT91C_SMC_BAT_BYTE_WRITE           (0x1 <<  8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
+#define AT91C_SMC_DBW         (0x3 << 12) // (SMC) Data Bus Width
+#define 	AT91C_SMC_DBW_WIDTH_EIGTH_BITS     (0x0 << 12) // (SMC) 8 bits.
+#define 	AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS   (0x1 << 12) // (SMC) 16 bits.
+#define 	AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (SMC) 32 bits.
+#define AT91C_SMC_TDF         (0xF << 16) // (SMC) Data Float Time.
+#define AT91C_SMC_TDFEN       (0x1 << 20) // (SMC) TDF Enabled.
+#define AT91C_SMC_PMEN        (0x1 << 24) // (SMC) Page Mode Enabled.
+#define AT91C_SMC_PS          (0x3 << 28) // (SMC) Page Size
+#define 	AT91C_SMC_PS_SIZE_FOUR_BYTES      (0x0 << 28) // (SMC) 4 bytes.
+#define 	AT91C_SMC_PS_SIZE_EIGHT_BYTES     (0x1 << 28) // (SMC) 8 bytes.
+#define 	AT91C_SMC_PS_SIZE_SIXTEEN_BYTES   (0x2 << 28) // (SMC) 16 bytes.
+#define 	AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (SMC) 32 bytes.
+// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR AHB Matrix Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_MATRIX {
+	AT91_REG	 MATRIX_MCFG0; 	//  Master Configuration Register 0 (ram96k)     
+	AT91_REG	 MATRIX_MCFG1; 	//  Master Configuration Register 1 (rom)    
+	AT91_REG	 MATRIX_MCFG2; 	//  Master Configuration Register 2 (hperiphs) 
+	AT91_REG	 MATRIX_MCFG3; 	//  Master Configuration Register 3 (ebi)
+	AT91_REG	 MATRIX_MCFG4; 	//  Master Configuration Register 4 (bridge)    
+	AT91_REG	 MATRIX_MCFG5; 	//  Master Configuration Register 5 (mailbox)    
+	AT91_REG	 MATRIX_MCFG6; 	//  Master Configuration Register 6 (ram16k)  
+	AT91_REG	 MATRIX_MCFG7; 	//  Master Configuration Register 7 (teak_prog)     
+	AT91_REG	 Reserved0[8]; 	// 
+	AT91_REG	 MATRIX_SCFG0; 	//  Slave Configuration Register 0 (ram96k)     
+	AT91_REG	 MATRIX_SCFG1; 	//  Slave Configuration Register 1 (rom)    
+	AT91_REG	 MATRIX_SCFG2; 	//  Slave Configuration Register 2 (hperiphs) 
+	AT91_REG	 MATRIX_SCFG3; 	//  Slave Configuration Register 3 (ebi)
+	AT91_REG	 MATRIX_SCFG4; 	//  Slave Configuration Register 4 (bridge)    
+	AT91_REG	 Reserved1[11]; 	// 
+	AT91_REG	 MATRIX_PRAS0; 	//  PRAS0 (ram0) 
+	AT91_REG	 MATRIX_PRBS0; 	//  PRBS0 (ram0) 
+	AT91_REG	 MATRIX_PRAS1; 	//  PRAS1 (ram1) 
+	AT91_REG	 MATRIX_PRBS1; 	//  PRBS1 (ram1) 
+	AT91_REG	 MATRIX_PRAS2; 	//  PRAS2 (ram2) 
+	AT91_REG	 MATRIX_PRBS2; 	//  PRBS2 (ram2) 
+	AT91_REG	 MATRIX_PRAS3; 	//  PRAS3 : usb_dev_hs
+	AT91_REG	 MATRIX_PRBS3; 	//  PRBS3 : usb_dev_hs
+	AT91_REG	 MATRIX_PRAS4; 	//  PRAS4 : ebi
+	AT91_REG	 MATRIX_PRBS4; 	//  PRBS4 : ebi
+	AT91_REG	 Reserved2[22]; 	// 
+	AT91_REG	 MATRIX_MRCR; 	//  Master Remp Control Register 
+	AT91_REG	 Reserved3[6]; 	// 
+	AT91_REG	 MATRIX_EBI; 	//  Slave 3 (ebi) Special Function Register
+	AT91_REG	 Reserved4[3]; 	// 
+	AT91_REG	 MATRIX_TEAKCFG; 	//  Slave 7 (teak_prog) Special Function Register
+	AT91_REG	 Reserved5[51]; 	// 
+	AT91_REG	 MATRIX_VERSION; 	//  Version Register
+} AT91S_MATRIX, *AT91PS_MATRIX;
+#else
+#define MATRIX_MCFG0    (AT91_CAST(AT91_REG *) 	0x00000000) // (MATRIX_MCFG0)  Master Configuration Register 0 (ram96k)     
+#define MATRIX_MCFG1    (AT91_CAST(AT91_REG *) 	0x00000004) // (MATRIX_MCFG1)  Master Configuration Register 1 (rom)    
+#define MATRIX_MCFG2    (AT91_CAST(AT91_REG *) 	0x00000008) // (MATRIX_MCFG2)  Master Configuration Register 2 (hperiphs) 
+#define MATRIX_MCFG3    (AT91_CAST(AT91_REG *) 	0x0000000C) // (MATRIX_MCFG3)  Master Configuration Register 3 (ebi)
+#define MATRIX_MCFG4    (AT91_CAST(AT91_REG *) 	0x00000010) // (MATRIX_MCFG4)  Master Configuration Register 4 (bridge)    
+#define MATRIX_MCFG5    (AT91_CAST(AT91_REG *) 	0x00000014) // (MATRIX_MCFG5)  Master Configuration Register 5 (mailbox)    
+#define MATRIX_MCFG6    (AT91_CAST(AT91_REG *) 	0x00000018) // (MATRIX_MCFG6)  Master Configuration Register 6 (ram16k)  
+#define MATRIX_MCFG7    (AT91_CAST(AT91_REG *) 	0x0000001C) // (MATRIX_MCFG7)  Master Configuration Register 7 (teak_prog)     
+#define MATRIX_SCFG0    (AT91_CAST(AT91_REG *) 	0x00000040) // (MATRIX_SCFG0)  Slave Configuration Register 0 (ram96k)     
+#define MATRIX_SCFG1    (AT91_CAST(AT91_REG *) 	0x00000044) // (MATRIX_SCFG1)  Slave Configuration Register 1 (rom)    
+#define MATRIX_SCFG2    (AT91_CAST(AT91_REG *) 	0x00000048) // (MATRIX_SCFG2)  Slave Configuration Register 2 (hperiphs) 
+#define MATRIX_SCFG3    (AT91_CAST(AT91_REG *) 	0x0000004C) // (MATRIX_SCFG3)  Slave Configuration Register 3 (ebi)
+#define MATRIX_SCFG4    (AT91_CAST(AT91_REG *) 	0x00000050) // (MATRIX_SCFG4)  Slave Configuration Register 4 (bridge)    
+#define MATRIX_PRAS0    (AT91_CAST(AT91_REG *) 	0x00000080) // (MATRIX_PRAS0)  PRAS0 (ram0) 
+#define MATRIX_PRBS0    (AT91_CAST(AT91_REG *) 	0x00000084) // (MATRIX_PRBS0)  PRBS0 (ram0) 
+#define MATRIX_PRAS1    (AT91_CAST(AT91_REG *) 	0x00000088) // (MATRIX_PRAS1)  PRAS1 (ram1) 
+#define MATRIX_PRBS1    (AT91_CAST(AT91_REG *) 	0x0000008C) // (MATRIX_PRBS1)  PRBS1 (ram1) 
+#define MATRIX_PRAS2    (AT91_CAST(AT91_REG *) 	0x00000090) // (MATRIX_PRAS2)  PRAS2 (ram2) 
+#define MATRIX_PRBS2    (AT91_CAST(AT91_REG *) 	0x00000094) // (MATRIX_PRBS2)  PRBS2 (ram2) 
+#define MATRIX_PRAS3    (AT91_CAST(AT91_REG *) 	0x00000098) // (MATRIX_PRAS3)  PRAS3 : usb_dev_hs
+#define MATRIX_PRBS3    (AT91_CAST(AT91_REG *) 	0x0000009C) // (MATRIX_PRBS3)  PRBS3 : usb_dev_hs
+#define MATRIX_PRAS4    (AT91_CAST(AT91_REG *) 	0x000000A0) // (MATRIX_PRAS4)  PRAS4 : ebi
+#define MATRIX_PRBS4    (AT91_CAST(AT91_REG *) 	0x000000A4) // (MATRIX_PRBS4)  PRBS4 : ebi
+#define MATRIX_MRCR     (AT91_CAST(AT91_REG *) 	0x00000100) // (MATRIX_MRCR)  Master Remp Control Register 
+#define MATRIX_EBI      (AT91_CAST(AT91_REG *) 	0x0000011C) // (MATRIX_EBI)  Slave 3 (ebi) Special Function Register
+#define MATRIX_TEAKCFG  (AT91_CAST(AT91_REG *) 	0x0000012C) // (MATRIX_TEAKCFG)  Slave 7 (teak_prog) Special Function Register
+#define MATRIX_VERSION  (AT91_CAST(AT91_REG *) 	0x000001FC) // (MATRIX_VERSION)  Version Register
+
+#endif
+// -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 -------- 
+#define AT91C_MATRIX_SLOT_CYCLE (0xFF <<  0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst
+#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type
+#define 	AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR           (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
+#define 	AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR         (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
+#define 	AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR        (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
+#define AT91C_MATRIX_FIXED_DEFMSTR0 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3                (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_LCDC                 (0x3 << 18) // (MATRIX) LCDC Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_DMA                  (0x4 << 18) // (MATRIX) DMA Master is Default Master
+// -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 -------- 
+#define AT91C_MATRIX_FIXED_DEFMSTR1 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3                (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR1_LCDC                 (0x3 << 18) // (MATRIX) LCDC Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR1_DMA                  (0x4 << 18) // (MATRIX) DMA Master is Default Master
+// -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 -------- 
+#define AT91C_MATRIX_FIXED_DEFMSTR2 (0x1 << 18) // (MATRIX) Fixed Index of Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+// -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 -------- 
+#define AT91C_MATRIX_FIXED_DEFMSTR3 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3                (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR3_LCDC                 (0x3 << 18) // (MATRIX) LCDC Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR3_DMA                  (0x4 << 18) // (MATRIX) DMA Master is Default Master
+// -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 -------- 
+#define AT91C_MATRIX_FIXED_DEFMSTR4 (0x3 << 18) // (MATRIX) Fixed Index of Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3                (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
+// -------- MATRIX_PRAS0 : (MATRIX Offset: 0x80) PRAS0 Register -------- 
+#define AT91C_MATRIX_M0PR     (0x3 <<  0) // (MATRIX) ARM926EJ-S Instruction priority
+#define AT91C_MATRIX_M1PR     (0x3 <<  4) // (MATRIX) ARM926EJ-S Data priority
+#define AT91C_MATRIX_M2PR     (0x3 <<  8) // (MATRIX) PDC priority
+#define AT91C_MATRIX_M3PR     (0x3 << 12) // (MATRIX) LCDC priority
+#define AT91C_MATRIX_M4PR     (0x3 << 16) // (MATRIX) 2DGC priority
+#define AT91C_MATRIX_M5PR     (0x3 << 20) // (MATRIX) ISI priority
+#define AT91C_MATRIX_M6PR     (0x3 << 24) // (MATRIX) DMA priority
+#define AT91C_MATRIX_M7PR     (0x3 << 28) // (MATRIX) EMAC priority
+// -------- MATRIX_PRBS0 : (MATRIX Offset: 0x84) PRBS0 Register -------- 
+#define AT91C_MATRIX_M8PR     (0x3 <<  0) // (MATRIX) USB priority
+// -------- MATRIX_PRAS1 : (MATRIX Offset: 0x88) PRAS1 Register -------- 
+// -------- MATRIX_PRBS1 : (MATRIX Offset: 0x8c) PRBS1 Register -------- 
+// -------- MATRIX_PRAS2 : (MATRIX Offset: 0x90) PRAS2 Register -------- 
+// -------- MATRIX_PRBS2 : (MATRIX Offset: 0x94) PRBS2 Register -------- 
+// -------- MATRIX_PRAS3 : (MATRIX Offset: 0x98) PRAS3 Register -------- 
+// -------- MATRIX_PRBS3 : (MATRIX Offset: 0x9c) PRBS3 Register -------- 
+// -------- MATRIX_PRAS4 : (MATRIX Offset: 0xa0) PRAS4 Register -------- 
+// -------- MATRIX_PRBS4 : (MATRIX Offset: 0xa4) PRBS4 Register -------- 
+// -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register -------- 
+#define AT91C_MATRIX_RCA926I  (0x1 <<  0) // (MATRIX) Remap Command for ARM926EJ-S Instruction Master
+#define AT91C_MATRIX_RCA926D  (0x1 <<  1) // (MATRIX) Remap Command for ARM926EJ-S Data Master
+// -------- MATRIX_EBI : (MATRIX Offset: 0x11c) EBI (Slave 3) Special Function Register -------- 
+#define AT91C_MATRIX_CS1A     (0x1 <<  1) // (MATRIX) Chip Select 1 Assignment
+#define 	AT91C_MATRIX_CS1A_SMC                  (0x0 <<  1) // (MATRIX) Chip Select 1 is assigned to the Static Memory Controller.
+#define 	AT91C_MATRIX_CS1A_SDRAMC               (0x1 <<  1) // (MATRIX) Chip Select 1 is assigned to the SDRAM Controller.
+#define AT91C_MATRIX_CS3A     (0x1 <<  3) // (MATRIX) Chip Select 3 Assignment
+#define 	AT91C_MATRIX_CS3A_SMC                  (0x0 <<  3) // (MATRIX) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
+#define 	AT91C_MATRIX_CS3A_SM                   (0x1 <<  3) // (MATRIX) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
+#define AT91C_MATRIX_CS4A     (0x1 <<  4) // (MATRIX) Chip Select 4 Assignment
+#define 	AT91C_MATRIX_CS4A_SMC                  (0x0 <<  4) // (MATRIX) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
+#define 	AT91C_MATRIX_CS4A_CF                   (0x1 <<  4) // (MATRIX) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
+#define AT91C_MATRIX_CS5A     (0x1 <<  5) // (MATRIX) Chip Select 5 Assignment
+#define 	AT91C_MATRIX_CS5A_SMC                  (0x0 <<  5) // (MATRIX) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
+#define 	AT91C_MATRIX_CS5A_CF                   (0x1 <<  5) // (MATRIX) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
+#define AT91C_MATRIX_DBPUC    (0x1 <<  8) // (MATRIX) Data Bus Pull-up Configuration
+// -------- MATRIX_TEAKCFG : (MATRIX Offset: 0x12c) Slave 7 Special Function Register -------- 
+#define AT91C_TEAK_PROGRAM_ACCESS (0x1 <<  0) // (MATRIX) TEAK program memory access from AHB
+#define 	AT91C_TEAK_PROGRAM_ACCESS_DISABLED             (0x0) // (MATRIX) TEAK program access disabled
+#define 	AT91C_TEAK_PROGRAM_ACCESS_ENABLED              (0x1) // (MATRIX) TEAK program access enabled
+#define AT91C_TEAK_BOOT       (0x1 <<  1) // (MATRIX) TEAK program start from boot routine
+#define 	AT91C_TEAK_BOOT_DISABLED             (0x0 <<  1) // (MATRIX) TEAK program starts from boot routine disabled
+#define 	AT91C_TEAK_BOOT_ENABLED              (0x1 <<  1) // (MATRIX) TEAK program starts from boot routine enabled
+#define AT91C_TEAK_NRESET     (0x1 <<  2) // (MATRIX) active low TEAK reset
+#define 	AT91C_TEAK_NRESET_ENABLED              (0x0 <<  2) // (MATRIX) active low TEAK reset enabled
+#define 	AT91C_TEAK_NRESET_DISABLED             (0x1 <<  2) // (MATRIX) active low TEAK reset disabled
+#define AT91C_TEAK_LVECTORP   (0x3FFFF << 14) // (MATRIX) boot routine start address
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Chip Configuration Registers
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_CCFG {
+	AT91_REG	 Reserved0[3]; 	// 
+	AT91_REG	 CCFG_EBICSA; 	//  EBI Chip Select Assignement Register
+	AT91_REG	 Reserved1[55]; 	// 
+	AT91_REG	 CCFG_MATRIXVERSION; 	//  Version Register
+} AT91S_CCFG, *AT91PS_CCFG;
+#else
+#define CCFG_EBICSA     (AT91_CAST(AT91_REG *) 	0x0000000C) // (CCFG_EBICSA)  EBI Chip Select Assignement Register
+#define CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 	0x000000EC) // (CCFG_MATRIXVERSION)  Version Register
+
+#endif
+// -------- CCFG_EBICSA : (CCFG Offset: 0xc) EBI Chip Select Assignement Register -------- 
+#define AT91C_EBI_CS1A        (0x1 <<  1) // (CCFG) Chip Select 1 Assignment
+#define 	AT91C_EBI_CS1A_SMC                  (0x0 <<  1) // (CCFG) Chip Select 1 is assigned to the Static Memory Controller.
+#define 	AT91C_EBI_CS1A_SDRAMC               (0x1 <<  1) // (CCFG) Chip Select 1 is assigned to the SDRAM Controller.
+#define AT91C_EBI_CS3A        (0x1 <<  3) // (CCFG) Chip Select 3 Assignment
+#define 	AT91C_EBI_CS3A_SMC                  (0x0 <<  3) // (CCFG) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
+#define 	AT91C_EBI_CS3A_SM                   (0x1 <<  3) // (CCFG) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
+#define AT91C_EBI_CS4A        (0x1 <<  4) // (CCFG) Chip Select 4 Assignment
+#define 	AT91C_EBI_CS4A_SMC                  (0x0 <<  4) // (CCFG) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
+#define 	AT91C_EBI_CS4A_CF                   (0x1 <<  4) // (CCFG) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
+#define AT91C_EBI_CS5A        (0x1 <<  5) // (CCFG) Chip Select 5 Assignment
+#define 	AT91C_EBI_CS5A_SMC                  (0x0 <<  5) // (CCFG) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
+#define 	AT91C_EBI_CS5A_CF                   (0x1 <<  5) // (CCFG) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
+#define AT91C_EBI_DBPUC       (0x1 <<  8) // (CCFG) Data Bus Pull-up Configuration
+#define AT91C_EBI_SUPPLY      (0x1 << 16) // (CCFG) EBI supply selection
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PDC {
+	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
+	AT91_REG	 PDC_RCR; 	// Receive Counter Register
+	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
+	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+#else
+#define PDC_RPR         (AT91_CAST(AT91_REG *) 	0x00000000) // (PDC_RPR) Receive Pointer Register
+#define PDC_RCR         (AT91_CAST(AT91_REG *) 	0x00000004) // (PDC_RCR) Receive Counter Register
+#define PDC_TPR         (AT91_CAST(AT91_REG *) 	0x00000008) // (PDC_TPR) Transmit Pointer Register
+#define PDC_TCR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (PDC_TCR) Transmit Counter Register
+#define PDC_RNPR        (AT91_CAST(AT91_REG *) 	0x00000010) // (PDC_RNPR) Receive Next Pointer Register
+#define PDC_RNCR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PDC_RNCR) Receive Next Counter Register
+#define PDC_TNPR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
+#define PDC_TNCR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
+#define PDC_PTCR        (AT91_CAST(AT91_REG *) 	0x00000020) // (PDC_PTCR) PDC Transfer Control Register
+#define PDC_PTSR        (AT91_CAST(AT91_REG *) 	0x00000024) // (PDC_PTSR) PDC Transfer Status Register
+
+#endif
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN       (0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS      (0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN       (0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS      (0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_DBGU {
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved0[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved1[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+#else
+#define DBGU_CR         (AT91_CAST(AT91_REG *) 	0x00000000) // (DBGU_CR) Control Register
+#define DBGU_MR         (AT91_CAST(AT91_REG *) 	0x00000004) // (DBGU_MR) Mode Register
+#define DBGU_IER        (AT91_CAST(AT91_REG *) 	0x00000008) // (DBGU_IER) Interrupt Enable Register
+#define DBGU_IDR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (DBGU_IDR) Interrupt Disable Register
+#define DBGU_IMR        (AT91_CAST(AT91_REG *) 	0x00000010) // (DBGU_IMR) Interrupt Mask Register
+#define DBGU_CSR        (AT91_CAST(AT91_REG *) 	0x00000014) // (DBGU_CSR) Channel Status Register
+#define DBGU_RHR        (AT91_CAST(AT91_REG *) 	0x00000018) // (DBGU_RHR) Receiver Holding Register
+#define DBGU_THR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (DBGU_THR) Transmitter Holding Register
+#define DBGU_BRGR       (AT91_CAST(AT91_REG *) 	0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
+#define DBGU_CIDR       (AT91_CAST(AT91_REG *) 	0x00000040) // (DBGU_CIDR) Chip ID Register
+#define DBGU_EXID       (AT91_CAST(AT91_REG *) 	0x00000044) // (DBGU_EXID) Chip ID Extension Register
+#define DBGU_FNTR       (AT91_CAST(AT91_REG *) 	0x00000048) // (DBGU_FNTR) Force NTRST Register
+
+#endif
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX        (0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX        (0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN         (0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS        (0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN         (0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS        (0x1 <<  7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA       (0x1 <<  8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR          (0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE       (0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY        (0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY        (0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX        (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX        (0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE         (0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME        (0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE         (0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY      (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE       (0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF       (0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX      (0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX      (0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST  (0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_AIC {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+#else
+#define AIC_SMR         (AT91_CAST(AT91_REG *) 	0x00000000) // (AIC_SMR) Source Mode Register
+#define AIC_SVR         (AT91_CAST(AT91_REG *) 	0x00000080) // (AIC_SVR) Source Vector Register
+#define AIC_IVR         (AT91_CAST(AT91_REG *) 	0x00000100) // (AIC_IVR) IRQ Vector Register
+#define AIC_FVR         (AT91_CAST(AT91_REG *) 	0x00000104) // (AIC_FVR) FIQ Vector Register
+#define AIC_ISR         (AT91_CAST(AT91_REG *) 	0x00000108) // (AIC_ISR) Interrupt Status Register
+#define AIC_IPR         (AT91_CAST(AT91_REG *) 	0x0000010C) // (AIC_IPR) Interrupt Pending Register
+#define AIC_IMR         (AT91_CAST(AT91_REG *) 	0x00000110) // (AIC_IMR) Interrupt Mask Register
+#define AIC_CISR        (AT91_CAST(AT91_REG *) 	0x00000114) // (AIC_CISR) Core Interrupt Status Register
+#define AIC_IECR        (AT91_CAST(AT91_REG *) 	0x00000120) // (AIC_IECR) Interrupt Enable Command Register
+#define AIC_IDCR        (AT91_CAST(AT91_REG *) 	0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
+#define AIC_ICCR        (AT91_CAST(AT91_REG *) 	0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
+#define AIC_ISCR        (AT91_CAST(AT91_REG *) 	0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
+#define AIC_EOICR       (AT91_CAST(AT91_REG *) 	0x00000130) // (AIC_EOICR) End of Interrupt Command Register
+#define AIC_SPU         (AT91_CAST(AT91_REG *) 	0x00000134) // (AIC_SPU) Spurious Vector Register
+#define AIC_DCR         (AT91_CAST(AT91_REG *) 	0x00000138) // (AIC_DCR) Debug Control Register (Protect)
+#define AIC_FFER        (AT91_CAST(AT91_REG *) 	0x00000140) // (AIC_FFER) Fast Forcing Enable Register
+#define AIC_FFDR        (AT91_CAST(AT91_REG *) 	0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
+#define AIC_FFSR        (AT91_CAST(AT91_REG *) 	0x00000148) // (AIC_FFSR) Fast Forcing Status Register
+
+#endif
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR       (0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE     (0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  (0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   (0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       (0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    (0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ        (0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ        (0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT    (0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK    (0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PIO {
+	AT91_REG	 PIO_PER; 	// PIO Enable Register
+	AT91_REG	 PIO_PDR; 	// PIO Disable Register
+	AT91_REG	 PIO_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PIO_OER; 	// Output Enable Register
+	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIO_OSR; 	// Output Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PIO_SODR; 	// Set Output Data Register
+	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved3[1]; 	// 
+	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved4[1]; 	// 
+	AT91_REG	 PIO_ASR; 	// Select A Register
+	AT91_REG	 PIO_BSR; 	// Select B Register
+	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved5[9]; 	// 
+	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+#else
+#define PIO_PER         (AT91_CAST(AT91_REG *) 	0x00000000) // (PIO_PER) PIO Enable Register
+#define PIO_PDR         (AT91_CAST(AT91_REG *) 	0x00000004) // (PIO_PDR) PIO Disable Register
+#define PIO_PSR         (AT91_CAST(AT91_REG *) 	0x00000008) // (PIO_PSR) PIO Status Register
+#define PIO_OER         (AT91_CAST(AT91_REG *) 	0x00000010) // (PIO_OER) Output Enable Register
+#define PIO_ODR         (AT91_CAST(AT91_REG *) 	0x00000014) // (PIO_ODR) Output Disable Registerr
+#define PIO_OSR         (AT91_CAST(AT91_REG *) 	0x00000018) // (PIO_OSR) Output Status Register
+#define PIO_IFER        (AT91_CAST(AT91_REG *) 	0x00000020) // (PIO_IFER) Input Filter Enable Register
+#define PIO_IFDR        (AT91_CAST(AT91_REG *) 	0x00000024) // (PIO_IFDR) Input Filter Disable Register
+#define PIO_IFSR        (AT91_CAST(AT91_REG *) 	0x00000028) // (PIO_IFSR) Input Filter Status Register
+#define PIO_SODR        (AT91_CAST(AT91_REG *) 	0x00000030) // (PIO_SODR) Set Output Data Register
+#define PIO_CODR        (AT91_CAST(AT91_REG *) 	0x00000034) // (PIO_CODR) Clear Output Data Register
+#define PIO_ODSR        (AT91_CAST(AT91_REG *) 	0x00000038) // (PIO_ODSR) Output Data Status Register
+#define PIO_PDSR        (AT91_CAST(AT91_REG *) 	0x0000003C) // (PIO_PDSR) Pin Data Status Register
+#define PIO_IER         (AT91_CAST(AT91_REG *) 	0x00000040) // (PIO_IER) Interrupt Enable Register
+#define PIO_IDR         (AT91_CAST(AT91_REG *) 	0x00000044) // (PIO_IDR) Interrupt Disable Register
+#define PIO_IMR         (AT91_CAST(AT91_REG *) 	0x00000048) // (PIO_IMR) Interrupt Mask Register
+#define PIO_ISR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (PIO_ISR) Interrupt Status Register
+#define PIO_MDER        (AT91_CAST(AT91_REG *) 	0x00000050) // (PIO_MDER) Multi-driver Enable Register
+#define PIO_MDDR        (AT91_CAST(AT91_REG *) 	0x00000054) // (PIO_MDDR) Multi-driver Disable Register
+#define PIO_MDSR        (AT91_CAST(AT91_REG *) 	0x00000058) // (PIO_MDSR) Multi-driver Status Register
+#define PIO_PPUDR       (AT91_CAST(AT91_REG *) 	0x00000060) // (PIO_PPUDR) Pull-up Disable Register
+#define PIO_PPUER       (AT91_CAST(AT91_REG *) 	0x00000064) // (PIO_PPUER) Pull-up Enable Register
+#define PIO_PPUSR       (AT91_CAST(AT91_REG *) 	0x00000068) // (PIO_PPUSR) Pull-up Status Register
+#define PIO_ASR         (AT91_CAST(AT91_REG *) 	0x00000070) // (PIO_ASR) Select A Register
+#define PIO_BSR         (AT91_CAST(AT91_REG *) 	0x00000074) // (PIO_BSR) Select B Register
+#define PIO_ABSR        (AT91_CAST(AT91_REG *) 	0x00000078) // (PIO_ABSR) AB Select Status Register
+#define PIO_OWER        (AT91_CAST(AT91_REG *) 	0x000000A0) // (PIO_OWER) Output Write Enable Register
+#define PIO_OWDR        (AT91_CAST(AT91_REG *) 	0x000000A4) // (PIO_OWDR) Output Write Disable Register
+#define PIO_OWSR        (AT91_CAST(AT91_REG *) 	0x000000A8) // (PIO_OWSR) Output Write Status Register
+
+#endif
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Embedded Flash Controller 2.0
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_EFC {
+	AT91_REG	 EFC_FMR; 	// EFC Flash Mode Register
+	AT91_REG	 EFC_FCR; 	// EFC Flash Command Register
+	AT91_REG	 EFC_FSR; 	// EFC Flash Status Register
+	AT91_REG	 EFC_FRR; 	// EFC Flash Result Register
+	AT91_REG	 EFC_FVR; 	// EFC Flash Version Register
+} AT91S_EFC, *AT91PS_EFC;
+#else
+#define EFC_FMR         (AT91_CAST(AT91_REG *) 	0x00000000) // (EFC_FMR) EFC Flash Mode Register
+#define EFC_FCR         (AT91_CAST(AT91_REG *) 	0x00000004) // (EFC_FCR) EFC Flash Command Register
+#define EFC_FSR         (AT91_CAST(AT91_REG *) 	0x00000008) // (EFC_FSR) EFC Flash Status Register
+#define EFC_FRR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (EFC_FRR) EFC Flash Result Register
+#define EFC_FVR         (AT91_CAST(AT91_REG *) 	0x00000010) // (EFC_FVR) EFC Flash Version Register
+
+#endif
+// -------- EFC_FMR : (EFC Offset: 0x0) EFC Flash Mode Register -------- 
+#define AT91C_EFC_FRDY        (0x1 <<  0) // (EFC) Ready Interrupt Enable
+#define AT91C_EFC_FWS         (0xF <<  8) // (EFC) Flash Wait State.
+#define 	AT91C_EFC_FWS_0WS                  (0x0 <<  8) // (EFC) 0 Wait State
+#define 	AT91C_EFC_FWS_1WS                  (0x1 <<  8) // (EFC) 1 Wait State
+#define 	AT91C_EFC_FWS_2WS                  (0x2 <<  8) // (EFC) 2 Wait States
+#define 	AT91C_EFC_FWS_3WS                  (0x3 <<  8) // (EFC) 3 Wait States
+// -------- EFC_FCR : (EFC Offset: 0x4) EFC Flash Command Register -------- 
+#define AT91C_EFC_FCMD        (0xFF <<  0) // (EFC) Flash Command
+#define 	AT91C_EFC_FCMD_GETD                 (0x0) // (EFC) Get Flash Descriptor
+#define 	AT91C_EFC_FCMD_WP                   (0x1) // (EFC) Write Page
+#define 	AT91C_EFC_FCMD_WPL                  (0x2) // (EFC) Write Page and Lock
+#define 	AT91C_EFC_FCMD_EWP                  (0x3) // (EFC) Erase Page and Write Page
+#define 	AT91C_EFC_FCMD_EWPL                 (0x4) // (EFC) Erase Page and Write Page then Lock
+#define 	AT91C_EFC_FCMD_EA                   (0x5) // (EFC) Erase All
+#define 	AT91C_EFC_FCMD_EPL                  (0x6) // (EFC) Erase Plane
+#define 	AT91C_EFC_FCMD_EPA                  (0x7) // (EFC) Erase Pages
+#define 	AT91C_EFC_FCMD_SLB                  (0x8) // (EFC) Set Lock Bit
+#define 	AT91C_EFC_FCMD_CLB                  (0x9) // (EFC) Clear Lock Bit
+#define 	AT91C_EFC_FCMD_GLB                  (0xA) // (EFC) Get Lock Bit
+#define 	AT91C_EFC_FCMD_SFB                  (0xB) // (EFC) Set Fuse Bit
+#define 	AT91C_EFC_FCMD_CFB                  (0xC) // (EFC) Clear Fuse Bit
+#define 	AT91C_EFC_FCMD_GFB                  (0xD) // (EFC) Get Fuse Bit
+#define AT91C_EFC_FARG        (0xFFFF <<  8) // (EFC) Flash Command Argument
+#define AT91C_EFC_FKEY        (0xFF << 24) // (EFC) Flash Writing Protection Key
+// -------- EFC_FSR : (EFC Offset: 0x8) EFC Flash Status Register -------- 
+#define AT91C_EFC_FRDY_S      (0x1 <<  0) // (EFC) Flash Ready Status
+#define AT91C_EFC_FCMDE       (0x1 <<  1) // (EFC) Flash Command Error Status
+#define AT91C_EFC_LOCKE       (0x1 <<  2) // (EFC) Flash Lock Error Status
+// -------- EFC_FRR : (EFC Offset: 0xc) EFC Flash Result Register -------- 
+#define AT91C_EFC_FVALUE      (0x0 <<  0) // (EFC) Flash Result Value
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_CKGR {
+	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
+	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 CKGR_PLLAR; 	// PLL A Register
+	AT91_REG	 CKGR_PLLBR; 	// PLL B Register
+} AT91S_CKGR, *AT91PS_CKGR;
+#else
+#define CKGR_MOR        (AT91_CAST(AT91_REG *) 	0x00000000) // (CKGR_MOR) Main Oscillator Register
+#define CKGR_MCFR       (AT91_CAST(AT91_REG *) 	0x00000004) // (CKGR_MCFR) Main Clock  Frequency Register
+#define CKGR_PLLAR      (AT91_CAST(AT91_REG *) 	0x00000008) // (CKGR_PLLAR) PLL A Register
+#define CKGR_PLLBR      (AT91_CAST(AT91_REG *) 	0x0000000C) // (CKGR_PLLBR) PLL B Register
+
+#endif
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN     (0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS  (0x1 <<  1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT    (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF      (0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY    (0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- 
+#define AT91C_CKGR_DIVA       (0xFF <<  0) // (CKGR) Divider A Selected
+#define 	AT91C_CKGR_DIVA_0                    (0x0) // (CKGR) Divider A output is 0
+#define 	AT91C_CKGR_DIVA_BYPASS               (0x1) // (CKGR) Divider A is bypassed
+#define AT91C_CKGR_PLLACOUNT  (0x3F <<  8) // (CKGR) PLL A Counter
+#define AT91C_CKGR_OUTA       (0x3 << 14) // (CKGR) PLL A Output Frequency Range
+#define 	AT91C_CKGR_OUTA_0                    (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define 	AT91C_CKGR_OUTA_1                    (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define 	AT91C_CKGR_OUTA_2                    (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define 	AT91C_CKGR_OUTA_3                    (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define AT91C_CKGR_MULA       (0x7FF << 16) // (CKGR) PLL A Multiplier
+#define AT91C_CKGR_SRCA       (0x1 << 29) // (CKGR) 
+// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- 
+#define AT91C_CKGR_DIVB       (0xFF <<  0) // (CKGR) Divider B Selected
+#define 	AT91C_CKGR_DIVB_0                    (0x0) // (CKGR) Divider B output is 0
+#define 	AT91C_CKGR_DIVB_BYPASS               (0x1) // (CKGR) Divider B is bypassed
+#define AT91C_CKGR_PLLBCOUNT  (0x3F <<  8) // (CKGR) PLL B Counter
+#define AT91C_CKGR_OUTB       (0x3 << 14) // (CKGR) PLL B Output Frequency Range
+#define 	AT91C_CKGR_OUTB_0                    (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define 	AT91C_CKGR_OUTB_1                    (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define 	AT91C_CKGR_OUTB_2                    (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define 	AT91C_CKGR_OUTB_3                    (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define AT91C_CKGR_MULB       (0x7FF << 16) // (CKGR) PLL B Multiplier
+#define AT91C_CKGR_USBDIV     (0x3 << 28) // (CKGR) Divider for USB Clocks
+#define 	AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define 	AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define 	AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PMC {
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 PMC_PLLAR; 	// PLL A Register
+	AT91_REG	 PMC_PLLBR; 	// PLL B Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved2[3]; 	// 
+	AT91_REG	 PMC_PCKR[8]; 	// Programmable Clock Register
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+#else
+#define PMC_SCER        (AT91_CAST(AT91_REG *) 	0x00000000) // (PMC_SCER) System Clock Enable Register
+#define PMC_SCDR        (AT91_CAST(AT91_REG *) 	0x00000004) // (PMC_SCDR) System Clock Disable Register
+#define PMC_SCSR        (AT91_CAST(AT91_REG *) 	0x00000008) // (PMC_SCSR) System Clock Status Register
+#define PMC_PCER        (AT91_CAST(AT91_REG *) 	0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
+#define PMC_PCDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
+#define PMC_PCSR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
+#define PMC_MCKR        (AT91_CAST(AT91_REG *) 	0x00000030) // (PMC_MCKR) Master Clock Register
+#define PMC_PCKR        (AT91_CAST(AT91_REG *) 	0x00000040) // (PMC_PCKR) Programmable Clock Register
+#define PMC_IER         (AT91_CAST(AT91_REG *) 	0x00000060) // (PMC_IER) Interrupt Enable Register
+#define PMC_IDR         (AT91_CAST(AT91_REG *) 	0x00000064) // (PMC_IDR) Interrupt Disable Register
+#define PMC_SR          (AT91_CAST(AT91_REG *) 	0x00000068) // (PMC_SR) Status Register
+#define PMC_IMR         (AT91_CAST(AT91_REG *) 	0x0000006C) // (PMC_IMR) Interrupt Mask Register
+
+#endif
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_PCK         (0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_OTG         (0x1 <<  5) // (PMC) USB OTG Clock
+#define AT91C_PMC_UHP         (0x1 <<  6) // (PMC) USB Host Port Clock
+#define AT91C_PMC_UDP         (0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0        (0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1        (0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2        (0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3        (0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- 
+// -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register -------- 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS         (0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLLA_CLK             (0x2) // (PMC) Clock from PLL A is selected
+#define 	AT91C_PMC_CSS_PLLB_CLK             (0x3) // (PMC) Clock from PLL B is selected
+#define AT91C_PMC_PRES        (0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
+#define AT91C_PMC_MDIV        (0x3 <<  8) // (PMC) Master Clock Division
+#define 	AT91C_PMC_MDIV_1                    (0x0 <<  8) // (PMC) The master clock and the processor clock are the same
+#define 	AT91C_PMC_MDIV_2                    (0x1 <<  8) // (PMC) The processor clock is twice as fast as the master clock
+#define 	AT91C_PMC_MDIV_3                    (0x2 <<  8) // (PMC) The processor clock is four times faster than the master clock
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS       (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCKA       (0x1 <<  1) // (PMC) PLL A Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCKB       (0x1 <<  2) // (PMC) PLL B Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY      (0x1 <<  3) // (PMC) Master Clock Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY     (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY     (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY     (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY     (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_RSTC {
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
+#else
+#define RSTC_RCR        (AT91_CAST(AT91_REG *) 	0x00000000) // (RSTC_RCR) Reset Control Register
+#define RSTC_RSR        (AT91_CAST(AT91_REG *) 	0x00000004) // (RSTC_RSR) Reset Status Register
+#define RSTC_RMR        (AT91_CAST(AT91_REG *) 	0x00000008) // (RSTC_RMR) Reset Mode Register
+
+#endif
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_RSTC_PROCRST    (0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_RSTC_ICERST     (0x1 <<  1) // (RSTC) ICE Interface Reset
+#define AT91C_RSTC_PERRST     (0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST     (0x1 <<  3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY        (0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_RSTC_URSTS      (0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_RSTC_RSTTYP     (0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_RSTC_RSTTYP_GENERAL              (0x0 <<  8) // (RSTC) General reset. Both VDDCORE and VDDBU rising.
+#define 	AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define AT91C_RSTC_NRSTL      (0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP      (0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_RSTC_URSTEN     (0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN    (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL      (0xF <<  8) // (RSTC) User Reset Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Shut Down Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SHDWC {
+	AT91_REG	 SHDWC_SHCR; 	// Shut Down Control Register
+	AT91_REG	 SHDWC_SHMR; 	// Shut Down Mode Register
+	AT91_REG	 SHDWC_SHSR; 	// Shut Down Status Register
+} AT91S_SHDWC, *AT91PS_SHDWC;
+#else
+#define SHDWC_SHCR      (AT91_CAST(AT91_REG *) 	0x00000000) // (SHDWC_SHCR) Shut Down Control Register
+#define SHDWC_SHMR      (AT91_CAST(AT91_REG *) 	0x00000004) // (SHDWC_SHMR) Shut Down Mode Register
+#define SHDWC_SHSR      (AT91_CAST(AT91_REG *) 	0x00000008) // (SHDWC_SHSR) Shut Down Status Register
+
+#endif
+// -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register -------- 
+#define AT91C_SHDWC_SHDW      (0x1 <<  0) // (SHDWC) Processor Reset
+#define AT91C_SHDWC_KEY       (0xFF << 24) // (SHDWC) Shut down KEY Password
+// -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register -------- 
+#define AT91C_SHDWC_WKMODE0   (0x3 <<  0) // (SHDWC) Wake Up 0 Mode Selection
+#define 	AT91C_SHDWC_WKMODE0_NONE                 (0x0) // (SHDWC) None. No detection is performed on the wake up input.
+#define 	AT91C_SHDWC_WKMODE0_HIGH                 (0x1) // (SHDWC) High Level.
+#define 	AT91C_SHDWC_WKMODE0_LOW                  (0x2) // (SHDWC) Low Level.
+#define 	AT91C_SHDWC_WKMODE0_ANYLEVEL             (0x3) // (SHDWC) Any level change.
+#define AT91C_SHDWC_CPTWK0    (0xF <<  4) // (SHDWC) Counter On Wake Up 0
+#define AT91C_SHDWC_WKMODE1   (0x3 <<  8) // (SHDWC) Wake Up 1 Mode Selection
+#define 	AT91C_SHDWC_WKMODE1_NONE                 (0x0 <<  8) // (SHDWC) None. No detection is performed on the wake up input.
+#define 	AT91C_SHDWC_WKMODE1_HIGH                 (0x1 <<  8) // (SHDWC) High Level.
+#define 	AT91C_SHDWC_WKMODE1_LOW                  (0x2 <<  8) // (SHDWC) Low Level.
+#define 	AT91C_SHDWC_WKMODE1_ANYLEVEL             (0x3 <<  8) // (SHDWC) Any level change.
+#define AT91C_SHDWC_CPTWK1    (0xF << 12) // (SHDWC) Counter On Wake Up 1
+#define AT91C_SHDWC_RTTWKEN   (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable
+#define AT91C_SHDWC_RTCWKEN   (0x1 << 17) // (SHDWC) Real Time Clock Wake Up Enable
+// -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register -------- 
+#define AT91C_SHDWC_WAKEUP0   (0x1 <<  0) // (SHDWC) Wake Up 0 Status
+#define AT91C_SHDWC_WAKEUP1   (0x1 <<  1) // (SHDWC) Wake Up 1 Status
+#define AT91C_SHDWC_FWKUP     (0x1 <<  2) // (SHDWC) Force Wake Up Status
+#define AT91C_SHDWC_RTTWK     (0x1 << 16) // (SHDWC) Real Time Timer wake Up
+#define AT91C_SHDWC_RTCWK     (0x1 << 17) // (SHDWC) Real Time Clock wake Up
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_RTTC {
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+#else
+#define RTTC_RTMR       (AT91_CAST(AT91_REG *) 	0x00000000) // (RTTC_RTMR) Real-time Mode Register
+#define RTTC_RTAR       (AT91_CAST(AT91_REG *) 	0x00000004) // (RTTC_RTAR) Real-time Alarm Register
+#define RTTC_RTVR       (AT91_CAST(AT91_REG *) 	0x00000008) // (RTTC_RTVR) Real-time Value Register
+#define RTTC_RTSR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (RTTC_RTSR) Real-time Status Register
+
+#endif
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_RTTC_RTPRES     (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN     (0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN  (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST     (0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_RTTC_ALMV       (0x0 <<  0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_RTTC_CRTV       (0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_RTTC_ALMS       (0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC     (0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PITC {
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+#else
+#define PITC_PIMR       (AT91_CAST(AT91_REG *) 	0x00000000) // (PITC_PIMR) Period Interval Mode Register
+#define PITC_PISR       (AT91_CAST(AT91_REG *) 	0x00000004) // (PITC_PISR) Period Interval Status Register
+#define PITC_PIVR       (AT91_CAST(AT91_REG *) 	0x00000008) // (PITC_PIVR) Period Interval Value Register
+#define PITC_PIIR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (PITC_PIIR) Period Interval Image Register
+
+#endif
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_PITC_PIV        (0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN      (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN     (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_PITC_PITS       (0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_PITC_CPIV       (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT      (0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_WDTC {
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+#else
+#define WDTC_WDCR       (AT91_CAST(AT91_REG *) 	0x00000000) // (WDTC_WDCR) Watchdog Control Register
+#define WDTC_WDMR       (AT91_CAST(AT91_REG *) 	0x00000004) // (WDTC_WDMR) Watchdog Mode Register
+#define WDTC_WDSR       (AT91_CAST(AT91_REG *) 	0x00000008) // (WDTC_WDSR) Watchdog Status Register
+
+#endif
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_WDTC_WDRSTT     (0x1 <<  0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY        (0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_WDTC_WDV        (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN     (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN    (0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC    (0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS      (0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD        (0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT   (0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT  (0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_WDTC_WDUNF      (0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR      (0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_TC {
+	AT91_REG	 TC_CCR; 	// Channel Control Register
+	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TC_CV; 	// Counter Value
+	AT91_REG	 TC_RA; 	// Register A
+	AT91_REG	 TC_RB; 	// Register B
+	AT91_REG	 TC_RC; 	// Register C
+	AT91_REG	 TC_SR; 	// Status Register
+	AT91_REG	 TC_IER; 	// Interrupt Enable Register
+	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+#else
+#define TC_CCR          (AT91_CAST(AT91_REG *) 	0x00000000) // (TC_CCR) Channel Control Register
+#define TC_CMR          (AT91_CAST(AT91_REG *) 	0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
+#define TC_CV           (AT91_CAST(AT91_REG *) 	0x00000010) // (TC_CV) Counter Value
+#define TC_RA           (AT91_CAST(AT91_REG *) 	0x00000014) // (TC_RA) Register A
+#define TC_RB           (AT91_CAST(AT91_REG *) 	0x00000018) // (TC_RB) Register B
+#define TC_RC           (AT91_CAST(AT91_REG *) 	0x0000001C) // (TC_RC) Register C
+#define TC_SR           (AT91_CAST(AT91_REG *) 	0x00000020) // (TC_SR) Status Register
+#define TC_IER          (AT91_CAST(AT91_REG *) 	0x00000024) // (TC_IER) Interrupt Enable Register
+#define TC_IDR          (AT91_CAST(AT91_REG *) 	0x00000028) // (TC_IDR) Interrupt Disable Register
+#define TC_IMR          (AT91_CAST(AT91_REG *) 	0x0000002C) // (TC_IMR) Interrupt Mask Register
+
+#endif
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN        (0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS       (0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG        (0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS         (0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI         (0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST        (0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS       (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS       (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG      (0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG      (0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT         (0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG       (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG       (0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL      (0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG       (0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE         (0x1 << 15) // (TC) 
+#define AT91C_TC_ACPA         (0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA         (0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC         (0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB         (0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT        (0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG       (0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB         (0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC         (0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT        (0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG       (0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS        (0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS        (0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS         (0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS         (0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS         (0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS        (0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS        (0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRGS        (0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA       (0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA        (0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB        (0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_TCB {
+	AT91S_TC	 TCB_TC0; 	// TC Channel 0
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91S_TC	 TCB_TC1; 	// TC Channel 1
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91S_TC	 TCB_TC2; 	// TC Channel 2
+	AT91_REG	 Reserved2[4]; 	// 
+	AT91_REG	 TCB_BCR; 	// TC Block Control Register
+	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+#else
+#define TCB_BCR         (AT91_CAST(AT91_REG *) 	0x000000C0) // (TCB_BCR) TC Block Control Register
+#define TCB_BMR         (AT91_CAST(AT91_REG *) 	0x000000C4) // (TCB_BMR) TC Block Mode Register
+
+#endif
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC        (0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S     (0x3 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S     (0x3 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S     (0x3 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Multimedia Card Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_MCI {
+	AT91_REG	 MCI_CR; 	// MCI Control Register
+	AT91_REG	 MCI_MR; 	// MCI Mode Register
+	AT91_REG	 MCI_DTOR; 	// MCI Data Timeout Register
+	AT91_REG	 MCI_SDCR; 	// MCI SD Card Register
+	AT91_REG	 MCI_ARGR; 	// MCI Argument Register
+	AT91_REG	 MCI_CMDR; 	// MCI Command Register
+	AT91_REG	 MCI_BLKR; 	// MCI Block Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 MCI_RSPR[4]; 	// MCI Response Register
+	AT91_REG	 MCI_RDR; 	// MCI Receive Data Register
+	AT91_REG	 MCI_TDR; 	// MCI Transmit Data Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 MCI_SR; 	// MCI Status Register
+	AT91_REG	 MCI_IER; 	// MCI Interrupt Enable Register
+	AT91_REG	 MCI_IDR; 	// MCI Interrupt Disable Register
+	AT91_REG	 MCI_IMR; 	// MCI Interrupt Mask Register
+	AT91_REG	 Reserved2[43]; 	// 
+	AT91_REG	 MCI_VR; 	// MCI Version Register
+	AT91_REG	 MCI_RPR; 	// Receive Pointer Register
+	AT91_REG	 MCI_RCR; 	// Receive Counter Register
+	AT91_REG	 MCI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 MCI_TCR; 	// Transmit Counter Register
+	AT91_REG	 MCI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 MCI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 MCI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 MCI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 MCI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 MCI_PTSR; 	// PDC Transfer Status Register
+} AT91S_MCI, *AT91PS_MCI;
+#else
+#define MCI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (MCI_CR) MCI Control Register
+#define MCI_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (MCI_MR) MCI Mode Register
+#define MCI_DTOR        (AT91_CAST(AT91_REG *) 	0x00000008) // (MCI_DTOR) MCI Data Timeout Register
+#define MCI_SDCR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (MCI_SDCR) MCI SD Card Register
+#define MCI_ARGR        (AT91_CAST(AT91_REG *) 	0x00000010) // (MCI_ARGR) MCI Argument Register
+#define MCI_CMDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (MCI_CMDR) MCI Command Register
+#define MCI_BLKR        (AT91_CAST(AT91_REG *) 	0x00000018) // (MCI_BLKR) MCI Block Register
+#define MCI_RSPR        (AT91_CAST(AT91_REG *) 	0x00000020) // (MCI_RSPR) MCI Response Register
+#define MCI_RDR         (AT91_CAST(AT91_REG *) 	0x00000030) // (MCI_RDR) MCI Receive Data Register
+#define MCI_TDR         (AT91_CAST(AT91_REG *) 	0x00000034) // (MCI_TDR) MCI Transmit Data Register
+#define MCI_SR          (AT91_CAST(AT91_REG *) 	0x00000040) // (MCI_SR) MCI Status Register
+#define MCI_IER         (AT91_CAST(AT91_REG *) 	0x00000044) // (MCI_IER) MCI Interrupt Enable Register
+#define MCI_IDR         (AT91_CAST(AT91_REG *) 	0x00000048) // (MCI_IDR) MCI Interrupt Disable Register
+#define MCI_IMR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (MCI_IMR) MCI Interrupt Mask Register
+#define MCI_VR          (AT91_CAST(AT91_REG *) 	0x000000FC) // (MCI_VR) MCI Version Register
+
+#endif
+// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- 
+#define AT91C_MCI_MCIEN       (0x1 <<  0) // (MCI) Multimedia Interface Enable
+#define AT91C_MCI_MCIDIS      (0x1 <<  1) // (MCI) Multimedia Interface Disable
+#define AT91C_MCI_PWSEN       (0x1 <<  2) // (MCI) Power Save Mode Enable
+#define AT91C_MCI_PWSDIS      (0x1 <<  3) // (MCI) Power Save Mode Disable
+#define AT91C_MCI_SWRST       (0x1 <<  7) // (MCI) MCI Software reset
+// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- 
+#define AT91C_MCI_CLKDIV      (0xFF <<  0) // (MCI) Clock Divider
+#define AT91C_MCI_PWSDIV      (0x7 <<  8) // (MCI) Power Saving Divider
+#define AT91C_MCI_RDPROOF     (0x1 << 11) // (MCI) Read Proof Enable
+#define AT91C_MCI_WRPROOF     (0x1 << 12) // (MCI) Write Proof Enable
+#define AT91C_MCI_PDCFBYTE    (0x1 << 13) // (MCI) PDC Force Byte Transfer
+#define AT91C_MCI_PDCPADV     (0x1 << 14) // (MCI) PDC Padding Value
+#define AT91C_MCI_PDCMODE     (0x1 << 15) // (MCI) PDC Oriented Mode
+#define AT91C_MCI_BLKLEN      (0xFFFF << 16) // (MCI) Data Block Length
+// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- 
+#define AT91C_MCI_DTOCYC      (0xF <<  0) // (MCI) Data Timeout Cycle Number
+#define AT91C_MCI_DTOMUL      (0x7 <<  4) // (MCI) Data Timeout Multiplier
+#define 	AT91C_MCI_DTOMUL_1                    (0x0 <<  4) // (MCI) DTOCYC x 1
+#define 	AT91C_MCI_DTOMUL_16                   (0x1 <<  4) // (MCI) DTOCYC x 16
+#define 	AT91C_MCI_DTOMUL_128                  (0x2 <<  4) // (MCI) DTOCYC x 128
+#define 	AT91C_MCI_DTOMUL_256                  (0x3 <<  4) // (MCI) DTOCYC x 256
+#define 	AT91C_MCI_DTOMUL_1024                 (0x4 <<  4) // (MCI) DTOCYC x 1024
+#define 	AT91C_MCI_DTOMUL_4096                 (0x5 <<  4) // (MCI) DTOCYC x 4096
+#define 	AT91C_MCI_DTOMUL_65536                (0x6 <<  4) // (MCI) DTOCYC x 65536
+#define 	AT91C_MCI_DTOMUL_1048576              (0x7 <<  4) // (MCI) DTOCYC x 1048576
+// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- 
+#define AT91C_MCI_SCDSEL      (0x3 <<  0) // (MCI) SD Card Selector
+#define AT91C_MCI_SCDBUS      (0x1 <<  7) // (MCI) SDCard/SDIO Bus Width
+// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- 
+#define AT91C_MCI_CMDNB       (0x3F <<  0) // (MCI) Command Number
+#define AT91C_MCI_RSPTYP      (0x3 <<  6) // (MCI) Response Type
+#define 	AT91C_MCI_RSPTYP_NO                   (0x0 <<  6) // (MCI) No response
+#define 	AT91C_MCI_RSPTYP_48                   (0x1 <<  6) // (MCI) 48-bit response
+#define 	AT91C_MCI_RSPTYP_136                  (0x2 <<  6) // (MCI) 136-bit response
+#define AT91C_MCI_SPCMD       (0x7 <<  8) // (MCI) Special CMD
+#define 	AT91C_MCI_SPCMD_NONE                 (0x0 <<  8) // (MCI) Not a special CMD
+#define 	AT91C_MCI_SPCMD_INIT                 (0x1 <<  8) // (MCI) Initialization CMD
+#define 	AT91C_MCI_SPCMD_SYNC                 (0x2 <<  8) // (MCI) Synchronized CMD
+#define 	AT91C_MCI_SPCMD_IT_CMD               (0x4 <<  8) // (MCI) Interrupt command
+#define 	AT91C_MCI_SPCMD_IT_REP               (0x5 <<  8) // (MCI) Interrupt response
+#define AT91C_MCI_OPDCMD      (0x1 << 11) // (MCI) Open Drain Command
+#define AT91C_MCI_MAXLAT      (0x1 << 12) // (MCI) Maximum Latency for Command to respond
+#define AT91C_MCI_TRCMD       (0x3 << 16) // (MCI) Transfer CMD
+#define 	AT91C_MCI_TRCMD_NO                   (0x0 << 16) // (MCI) No transfer
+#define 	AT91C_MCI_TRCMD_START                (0x1 << 16) // (MCI) Start transfer
+#define 	AT91C_MCI_TRCMD_STOP                 (0x2 << 16) // (MCI) Stop transfer
+#define AT91C_MCI_TRDIR       (0x1 << 18) // (MCI) Transfer Direction
+#define AT91C_MCI_TRTYP       (0x7 << 19) // (MCI) Transfer Type
+#define 	AT91C_MCI_TRTYP_BLOCK                (0x0 << 19) // (MCI) MMC/SDCard Single Block Transfer type
+#define 	AT91C_MCI_TRTYP_MULTIPLE             (0x1 << 19) // (MCI) MMC/SDCard Multiple Block transfer type
+#define 	AT91C_MCI_TRTYP_STREAM               (0x2 << 19) // (MCI) MMC Stream transfer type
+#define 	AT91C_MCI_TRTYP_SDIO_BYTE            (0x4 << 19) // (MCI) SDIO Byte transfer type
+#define 	AT91C_MCI_TRTYP_SDIO_BLOCK           (0x5 << 19) // (MCI) SDIO Block transfer type
+#define AT91C_MCI_IOSPCMD     (0x3 << 24) // (MCI) SDIO Special Command
+#define 	AT91C_MCI_IOSPCMD_NONE                 (0x0 << 24) // (MCI) NOT a special command
+#define 	AT91C_MCI_IOSPCMD_SUSPEND              (0x1 << 24) // (MCI) SDIO Suspend Command
+#define 	AT91C_MCI_IOSPCMD_RESUME               (0x2 << 24) // (MCI) SDIO Resume Command
+// -------- MCI_BLKR : (MCI Offset: 0x18) MCI Block Register -------- 
+#define AT91C_MCI_BCNT        (0xFFFF <<  0) // (MCI) MMC/SDIO Block Count / SDIO Byte Count
+// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- 
+#define AT91C_MCI_CMDRDY      (0x1 <<  0) // (MCI) Command Ready flag
+#define AT91C_MCI_RXRDY       (0x1 <<  1) // (MCI) RX Ready flag
+#define AT91C_MCI_TXRDY       (0x1 <<  2) // (MCI) TX Ready flag
+#define AT91C_MCI_BLKE        (0x1 <<  3) // (MCI) Data Block Transfer Ended flag
+#define AT91C_MCI_DTIP        (0x1 <<  4) // (MCI) Data Transfer in Progress flag
+#define AT91C_MCI_NOTBUSY     (0x1 <<  5) // (MCI) Data Line Not Busy flag
+#define AT91C_MCI_ENDRX       (0x1 <<  6) // (MCI) End of RX Buffer flag
+#define AT91C_MCI_ENDTX       (0x1 <<  7) // (MCI) End of TX Buffer flag
+#define AT91C_MCI_SDIOIRQA    (0x1 <<  8) // (MCI) SDIO Interrupt for Slot A
+#define AT91C_MCI_SDIOIRQB    (0x1 <<  9) // (MCI) SDIO Interrupt for Slot B
+#define AT91C_MCI_SDIOIRQC    (0x1 << 10) // (MCI) SDIO Interrupt for Slot C
+#define AT91C_MCI_SDIOIRQD    (0x1 << 11) // (MCI) SDIO Interrupt for Slot D
+#define AT91C_MCI_RXBUFF      (0x1 << 14) // (MCI) RX Buffer Full flag
+#define AT91C_MCI_TXBUFE      (0x1 << 15) // (MCI) TX Buffer Empty flag
+#define AT91C_MCI_RINDE       (0x1 << 16) // (MCI) Response Index Error flag
+#define AT91C_MCI_RDIRE       (0x1 << 17) // (MCI) Response Direction Error flag
+#define AT91C_MCI_RCRCE       (0x1 << 18) // (MCI) Response CRC Error flag
+#define AT91C_MCI_RENDE       (0x1 << 19) // (MCI) Response End Bit Error flag
+#define AT91C_MCI_RTOE        (0x1 << 20) // (MCI) Response Time-out Error flag
+#define AT91C_MCI_DCRCE       (0x1 << 21) // (MCI) data CRC Error flag
+#define AT91C_MCI_DTOE        (0x1 << 22) // (MCI) Data timeout Error flag
+#define AT91C_MCI_OVRE        (0x1 << 30) // (MCI) Overrun flag
+#define AT91C_MCI_UNRE        (0x1 << 31) // (MCI) Underrun flag
+// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- 
+// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- 
+// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_TWI {
+	AT91_REG	 TWI_CR; 	// Control Register
+	AT91_REG	 TWI_MMR; 	// Master Mode Register
+	AT91_REG	 TWI_SMR; 	// Slave Mode Register
+	AT91_REG	 TWI_IADR; 	// Internal Address Register
+	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
+	AT91_REG	 Reserved0[3]; 	// 
+	AT91_REG	 TWI_SR; 	// Status Register
+	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
+	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TWI_RHR; 	// Receive Holding Register
+	AT91_REG	 TWI_THR; 	// Transmit Holding Register
+	AT91_REG	 Reserved1[50]; 	// 
+	AT91_REG	 TWI_RPR; 	// Receive Pointer Register
+	AT91_REG	 TWI_RCR; 	// Receive Counter Register
+	AT91_REG	 TWI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 TWI_TCR; 	// Transmit Counter Register
+	AT91_REG	 TWI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 TWI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 TWI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 TWI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 TWI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 TWI_PTSR; 	// PDC Transfer Status Register
+} AT91S_TWI, *AT91PS_TWI;
+#else
+#define TWI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (TWI_CR) Control Register
+#define TWI_MMR         (AT91_CAST(AT91_REG *) 	0x00000004) // (TWI_MMR) Master Mode Register
+#define TWI_SMR         (AT91_CAST(AT91_REG *) 	0x00000008) // (TWI_SMR) Slave Mode Register
+#define TWI_IADR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (TWI_IADR) Internal Address Register
+#define TWI_CWGR        (AT91_CAST(AT91_REG *) 	0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
+#define TWI_SR          (AT91_CAST(AT91_REG *) 	0x00000020) // (TWI_SR) Status Register
+#define TWI_IER         (AT91_CAST(AT91_REG *) 	0x00000024) // (TWI_IER) Interrupt Enable Register
+#define TWI_IDR         (AT91_CAST(AT91_REG *) 	0x00000028) // (TWI_IDR) Interrupt Disable Register
+#define TWI_IMR         (AT91_CAST(AT91_REG *) 	0x0000002C) // (TWI_IMR) Interrupt Mask Register
+#define TWI_RHR         (AT91_CAST(AT91_REG *) 	0x00000030) // (TWI_RHR) Receive Holding Register
+#define TWI_THR         (AT91_CAST(AT91_REG *) 	0x00000034) // (TWI_THR) Transmit Holding Register
+
+#endif
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START       (0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP        (0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN        (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS       (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SVEN        (0x1 <<  4) // (TWI) TWI Slave mode Enabled
+#define AT91C_TWI_SVDIS       (0x1 <<  5) // (TWI) TWI Slave mode Disabled
+#define AT91C_TWI_SWRST       (0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ      (0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD       (0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR        (0x7F << 16) // (TWI) Device Address
+// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- 
+#define AT91C_TWI_SADR        (0x7F << 16) // (TWI) Slave Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV       (0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV       (0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV       (0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP_SLAVE (0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_TXCOMP_MASTER (0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY       (0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY_MASTER (0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_TXRDY_SLAVE (0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_SVREAD      (0x1 <<  3) // (TWI) Slave READ (used only in Slave mode)
+#define AT91C_TWI_SVACC       (0x1 <<  4) // (TWI) Slave ACCess (used only in Slave mode)
+#define AT91C_TWI_GACC        (0x1 <<  5) // (TWI) General Call ACcess (used only in Slave mode)
+#define AT91C_TWI_OVRE        (0x1 <<  6) // (TWI) Overrun Error (used only in Master and Multi-master mode)
+#define AT91C_TWI_NACK_SLAVE  (0x1 <<  8) // (TWI) Not Acknowledged
+#define AT91C_TWI_NACK_MASTER (0x1 <<  8) // (TWI) Not Acknowledged
+#define AT91C_TWI_ARBLST_MULTI_MASTER (0x1 <<  9) // (TWI) Arbitration Lost (used only in Multimaster mode)
+#define AT91C_TWI_SCLWS       (0x1 << 10) // (TWI) Clock Wait State (used only in Slave mode)
+#define AT91C_TWI_EOSACC      (0x1 << 11) // (TWI) End Of Slave ACCess (used only in Slave mode)
+#define AT91C_TWI_ENDRX       (0x1 << 12) // (TWI) End of Receiver Transfer
+#define AT91C_TWI_ENDTX       (0x1 << 13) // (TWI) End of Receiver Transfer
+#define AT91C_TWI_RXBUFF      (0x1 << 14) // (TWI) RXBUFF Interrupt
+#define AT91C_TWI_TXBUFE      (0x1 << 15) // (TWI) TXBUFE Interrupt
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_USART {
+	AT91_REG	 US_CR; 	// Control Register
+	AT91_REG	 US_MR; 	// Mode Register
+	AT91_REG	 US_IER; 	// Interrupt Enable Register
+	AT91_REG	 US_IDR; 	// Interrupt Disable Register
+	AT91_REG	 US_IMR; 	// Interrupt Mask Register
+	AT91_REG	 US_CSR; 	// Channel Status Register
+	AT91_REG	 US_RHR; 	// Receiver Holding Register
+	AT91_REG	 US_THR; 	// Transmitter Holding Register
+	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
+	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
+	AT91_REG	 Reserved0[5]; 	// 
+	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
+	AT91_REG	 US_NER; 	// Nb Errors Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 US_IF; 	// IRDA_FILTER Register
+	AT91_REG	 Reserved2[44]; 	// 
+	AT91_REG	 US_RPR; 	// Receive Pointer Register
+	AT91_REG	 US_RCR; 	// Receive Counter Register
+	AT91_REG	 US_TPR; 	// Transmit Pointer Register
+	AT91_REG	 US_TCR; 	// Transmit Counter Register
+	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+#else
+#define US_CR           (AT91_CAST(AT91_REG *) 	0x00000000) // (US_CR) Control Register
+#define US_MR           (AT91_CAST(AT91_REG *) 	0x00000004) // (US_MR) Mode Register
+#define US_IER          (AT91_CAST(AT91_REG *) 	0x00000008) // (US_IER) Interrupt Enable Register
+#define US_IDR          (AT91_CAST(AT91_REG *) 	0x0000000C) // (US_IDR) Interrupt Disable Register
+#define US_IMR          (AT91_CAST(AT91_REG *) 	0x00000010) // (US_IMR) Interrupt Mask Register
+#define US_CSR          (AT91_CAST(AT91_REG *) 	0x00000014) // (US_CSR) Channel Status Register
+#define US_RHR          (AT91_CAST(AT91_REG *) 	0x00000018) // (US_RHR) Receiver Holding Register
+#define US_THR          (AT91_CAST(AT91_REG *) 	0x0000001C) // (US_THR) Transmitter Holding Register
+#define US_BRGR         (AT91_CAST(AT91_REG *) 	0x00000020) // (US_BRGR) Baud Rate Generator Register
+#define US_RTOR         (AT91_CAST(AT91_REG *) 	0x00000024) // (US_RTOR) Receiver Time-out Register
+#define US_TTGR         (AT91_CAST(AT91_REG *) 	0x00000028) // (US_TTGR) Transmitter Time-guard Register
+#define US_FIDI         (AT91_CAST(AT91_REG *) 	0x00000040) // (US_FIDI) FI_DI_Ratio Register
+#define US_NER          (AT91_CAST(AT91_REG *) 	0x00000044) // (US_NER) Nb Errors Register
+#define US_IF           (AT91_CAST(AT91_REG *) 	0x0000004C) // (US_IF) IRDA_FILTER Register
+
+#endif
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_STTBRK       (0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK       (0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO        (0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA        (0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT        (0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK      (0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO        (0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN        (0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS       (0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN        (0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS       (0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_USMODE       (0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS         (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL         (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC         (0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP       (0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF         (0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9        (0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO         (0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER         (0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK        (0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK       (0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER     (0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER       (0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK        (0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT      (0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION    (0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK         (0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC         (0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC        (0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC        (0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC        (0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+#define AT91C_US_RI           (0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR          (0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD          (0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS          (0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SSC {
+	AT91_REG	 SSC_CR; 	// Control Register
+	AT91_REG	 SSC_CMR; 	// Clock Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
+	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
+	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
+	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
+	AT91_REG	 SSC_RHR; 	// Receive Holding Register
+	AT91_REG	 SSC_THR; 	// Transmit Holding Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
+	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 SSC_SR; 	// Status Register
+	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
+	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved3[44]; 	// 
+	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
+	AT91_REG	 SSC_RCR; 	// Receive Counter Register
+	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
+	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+#else
+#define SSC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (SSC_CR) Control Register
+#define SSC_CMR         (AT91_CAST(AT91_REG *) 	0x00000004) // (SSC_CMR) Clock Mode Register
+#define SSC_RCMR        (AT91_CAST(AT91_REG *) 	0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
+#define SSC_RFMR        (AT91_CAST(AT91_REG *) 	0x00000014) // (SSC_RFMR) Receive Frame Mode Register
+#define SSC_TCMR        (AT91_CAST(AT91_REG *) 	0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
+#define SSC_TFMR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
+#define SSC_RHR         (AT91_CAST(AT91_REG *) 	0x00000020) // (SSC_RHR) Receive Holding Register
+#define SSC_THR         (AT91_CAST(AT91_REG *) 	0x00000024) // (SSC_THR) Transmit Holding Register
+#define SSC_RSHR        (AT91_CAST(AT91_REG *) 	0x00000030) // (SSC_RSHR) Receive Sync Holding Register
+#define SSC_TSHR        (AT91_CAST(AT91_REG *) 	0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
+#define SSC_SR          (AT91_CAST(AT91_REG *) 	0x00000040) // (SSC_SR) Status Register
+#define SSC_IER         (AT91_CAST(AT91_REG *) 	0x00000044) // (SSC_IER) Interrupt Enable Register
+#define SSC_IDR         (AT91_CAST(AT91_REG *) 	0x00000048) // (SSC_IDR) Interrupt Disable Register
+#define SSC_IMR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (SSC_IMR) Interrupt Mask Register
+
+#endif
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN        (0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS       (0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN        (0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS       (0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST       (0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS         (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO         (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI         (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START       (0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY      (0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD      (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN      (0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP        (0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF        (0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB       (0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN       (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS        (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE      (0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF      (0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN       (0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY       (0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY     (0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX       (0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE      (0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY       (0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN       (0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX       (0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF      (0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN       (0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN       (0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA       (0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA       (0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SPI {
+	AT91_REG	 SPI_CR; 	// Control Register
+	AT91_REG	 SPI_MR; 	// Mode Register
+	AT91_REG	 SPI_RDR; 	// Receive Data Register
+	AT91_REG	 SPI_TDR; 	// Transmit Data Register
+	AT91_REG	 SPI_SR; 	// Status Register
+	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
+	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
+	AT91_REG	 Reserved1[48]; 	// 
+	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
+	AT91_REG	 SPI_RCR; 	// Receive Counter Register
+	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
+	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+#else
+#define SPI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (SPI_CR) Control Register
+#define SPI_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (SPI_MR) Mode Register
+#define SPI_RDR         (AT91_CAST(AT91_REG *) 	0x00000008) // (SPI_RDR) Receive Data Register
+#define SPI_TDR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (SPI_TDR) Transmit Data Register
+#define SPI_SR          (AT91_CAST(AT91_REG *) 	0x00000010) // (SPI_SR) Status Register
+#define SPI_IER         (AT91_CAST(AT91_REG *) 	0x00000014) // (SPI_IER) Interrupt Enable Register
+#define SPI_IDR         (AT91_CAST(AT91_REG *) 	0x00000018) // (SPI_IDR) Interrupt Disable Register
+#define SPI_IMR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (SPI_IMR) Interrupt Mask Register
+#define SPI_CSR         (AT91_CAST(AT91_REG *) 	0x00000030) // (SPI_CSR) Chip Select Register
+
+#endif
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN       (0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS      (0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST       (0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER    (0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR        (0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS          (0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC      (0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV        (0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS     (0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB         (0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS         (0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS      (0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD          (0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD          (0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF        (0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE        (0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF        (0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES       (0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX       (0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX       (0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF      (0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE      (0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR        (0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY     (0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS      (0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL        (0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA       (0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT       (0x1 <<  3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS        (0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR        (0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS       (0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT      (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_ADC {
+	AT91_REG	 ADC_CR; 	// ADC Control Register
+	AT91_REG	 ADC_MR; 	// ADC Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
+	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
+	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
+	AT91_REG	 ADC_SR; 	// ADC Status Register
+	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
+	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
+	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
+	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
+	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
+	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
+	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
+	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
+	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
+	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
+	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
+	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
+	AT91_REG	 Reserved1[44]; 	// 
+	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
+	AT91_REG	 ADC_RCR; 	// Receive Counter Register
+	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
+	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
+#else
+#define ADC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (ADC_CR) ADC Control Register
+#define ADC_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (ADC_MR) ADC Mode Register
+#define ADC_CHER        (AT91_CAST(AT91_REG *) 	0x00000010) // (ADC_CHER) ADC Channel Enable Register
+#define ADC_CHDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (ADC_CHDR) ADC Channel Disable Register
+#define ADC_CHSR        (AT91_CAST(AT91_REG *) 	0x00000018) // (ADC_CHSR) ADC Channel Status Register
+#define ADC_SR          (AT91_CAST(AT91_REG *) 	0x0000001C) // (ADC_SR) ADC Status Register
+#define ADC_LCDR        (AT91_CAST(AT91_REG *) 	0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
+#define ADC_IER         (AT91_CAST(AT91_REG *) 	0x00000024) // (ADC_IER) ADC Interrupt Enable Register
+#define ADC_IDR         (AT91_CAST(AT91_REG *) 	0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
+#define ADC_IMR         (AT91_CAST(AT91_REG *) 	0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
+#define ADC_CDR0        (AT91_CAST(AT91_REG *) 	0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
+#define ADC_CDR1        (AT91_CAST(AT91_REG *) 	0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
+#define ADC_CDR2        (AT91_CAST(AT91_REG *) 	0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
+#define ADC_CDR3        (AT91_CAST(AT91_REG *) 	0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
+#define ADC_CDR4        (AT91_CAST(AT91_REG *) 	0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
+#define ADC_CDR5        (AT91_CAST(AT91_REG *) 	0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
+#define ADC_CDR6        (AT91_CAST(AT91_REG *) 	0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
+#define ADC_CDR7        (AT91_CAST(AT91_REG *) 	0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
+
+#endif
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+#define AT91C_ADC_SWRST       (0x1 <<  0) // (ADC) Software Reset
+#define AT91C_ADC_START       (0x1 <<  1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+#define AT91C_ADC_TRGEN       (0x1 <<  0) // (ADC) Trigger Enable
+#define 	AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define 	AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL      (0x7 <<  1) // (ADC) Trigger Selection
+#define 	AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
+#define 	AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
+#define 	AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
+#define 	AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
+#define 	AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
+#define 	AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
+#define 	AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES      (0x1 <<  4) // (ADC) Resolution.
+#define 	AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
+#define 	AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP       (0x1 <<  5) // (ADC) Sleep Mode
+#define 	AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
+#define 	AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL     (0x3F <<  8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP     (0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM       (0xF << 24) // (ADC) Sample & Hold Time
+// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+#define AT91C_ADC_CH0         (0x1 <<  0) // (ADC) Channel 0
+#define AT91C_ADC_CH1         (0x1 <<  1) // (ADC) Channel 1
+#define AT91C_ADC_CH2         (0x1 <<  2) // (ADC) Channel 2
+#define AT91C_ADC_CH3         (0x1 <<  3) // (ADC) Channel 3
+#define AT91C_ADC_CH4         (0x1 <<  4) // (ADC) Channel 4
+#define AT91C_ADC_CH5         (0x1 <<  5) // (ADC) Channel 5
+#define AT91C_ADC_CH6         (0x1 <<  6) // (ADC) Channel 6
+#define AT91C_ADC_CH7         (0x1 <<  7) // (ADC) Channel 7
+// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+#define AT91C_ADC_EOC0        (0x1 <<  0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1        (0x1 <<  1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2        (0x1 <<  2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3        (0x1 <<  3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4        (0x1 <<  4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5        (0x1 <<  5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6        (0x1 <<  6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7        (0x1 <<  7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0       (0x1 <<  8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1       (0x1 <<  9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2       (0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3       (0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4       (0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5       (0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6       (0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7       (0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY        (0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE       (0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX       (0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF      (0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+#define AT91C_ADC_LDATA       (0x3FF <<  0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+#define AT91C_ADC_DATA        (0x3FF <<  0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_EMAC {
+	AT91_REG	 EMAC_NCR; 	// Network Control Register
+	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
+	AT91_REG	 EMAC_NSR; 	// Network Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
+	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
+	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
+	AT91_REG	 EMAC_RSR; 	// Receive Status Register
+	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
+	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
+	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
+	AT91_REG	 EMAC_PTR; 	// Pause Time Register
+	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
+	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
+	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
+	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
+	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
+	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
+	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
+	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
+	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
+	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
+	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
+	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
+	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
+	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
+	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
+	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
+	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
+	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
+	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
+	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
+	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
+	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
+	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
+	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
+	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
+	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
+	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
+	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
+	AT91_REG	 Reserved1[13]; 	// 
+	AT91_REG	 EMAC_REV; 	// Revision Register
+} AT91S_EMAC, *AT91PS_EMAC;
+#else
+#define EMAC_NCR        (AT91_CAST(AT91_REG *) 	0x00000000) // (EMAC_NCR) Network Control Register
+#define EMAC_NCFGR      (AT91_CAST(AT91_REG *) 	0x00000004) // (EMAC_NCFGR) Network Configuration Register
+#define EMAC_NSR        (AT91_CAST(AT91_REG *) 	0x00000008) // (EMAC_NSR) Network Status Register
+#define EMAC_TSR        (AT91_CAST(AT91_REG *) 	0x00000014) // (EMAC_TSR) Transmit Status Register
+#define EMAC_RBQP       (AT91_CAST(AT91_REG *) 	0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer
+#define EMAC_TBQP       (AT91_CAST(AT91_REG *) 	0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer
+#define EMAC_RSR        (AT91_CAST(AT91_REG *) 	0x00000020) // (EMAC_RSR) Receive Status Register
+#define EMAC_ISR        (AT91_CAST(AT91_REG *) 	0x00000024) // (EMAC_ISR) Interrupt Status Register
+#define EMAC_IER        (AT91_CAST(AT91_REG *) 	0x00000028) // (EMAC_IER) Interrupt Enable Register
+#define EMAC_IDR        (AT91_CAST(AT91_REG *) 	0x0000002C) // (EMAC_IDR) Interrupt Disable Register
+#define EMAC_IMR        (AT91_CAST(AT91_REG *) 	0x00000030) // (EMAC_IMR) Interrupt Mask Register
+#define EMAC_MAN        (AT91_CAST(AT91_REG *) 	0x00000034) // (EMAC_MAN) PHY Maintenance Register
+#define EMAC_PTR        (AT91_CAST(AT91_REG *) 	0x00000038) // (EMAC_PTR) Pause Time Register
+#define EMAC_PFR        (AT91_CAST(AT91_REG *) 	0x0000003C) // (EMAC_PFR) Pause Frames received Register
+#define EMAC_FTO        (AT91_CAST(AT91_REG *) 	0x00000040) // (EMAC_FTO) Frames Transmitted OK Register
+#define EMAC_SCF        (AT91_CAST(AT91_REG *) 	0x00000044) // (EMAC_SCF) Single Collision Frame Register
+#define EMAC_MCF        (AT91_CAST(AT91_REG *) 	0x00000048) // (EMAC_MCF) Multiple Collision Frame Register
+#define EMAC_FRO        (AT91_CAST(AT91_REG *) 	0x0000004C) // (EMAC_FRO) Frames Received OK Register
+#define EMAC_FCSE       (AT91_CAST(AT91_REG *) 	0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register
+#define EMAC_ALE        (AT91_CAST(AT91_REG *) 	0x00000054) // (EMAC_ALE) Alignment Error Register
+#define EMAC_DTF        (AT91_CAST(AT91_REG *) 	0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register
+#define EMAC_LCOL       (AT91_CAST(AT91_REG *) 	0x0000005C) // (EMAC_LCOL) Late Collision Register
+#define EMAC_ECOL       (AT91_CAST(AT91_REG *) 	0x00000060) // (EMAC_ECOL) Excessive Collision Register
+#define EMAC_TUND       (AT91_CAST(AT91_REG *) 	0x00000064) // (EMAC_TUND) Transmit Underrun Error Register
+#define EMAC_CSE        (AT91_CAST(AT91_REG *) 	0x00000068) // (EMAC_CSE) Carrier Sense Error Register
+#define EMAC_RRE        (AT91_CAST(AT91_REG *) 	0x0000006C) // (EMAC_RRE) Receive Ressource Error Register
+#define EMAC_ROV        (AT91_CAST(AT91_REG *) 	0x00000070) // (EMAC_ROV) Receive Overrun Errors Register
+#define EMAC_RSE        (AT91_CAST(AT91_REG *) 	0x00000074) // (EMAC_RSE) Receive Symbol Errors Register
+#define EMAC_ELE        (AT91_CAST(AT91_REG *) 	0x00000078) // (EMAC_ELE) Excessive Length Errors Register
+#define EMAC_RJA        (AT91_CAST(AT91_REG *) 	0x0000007C) // (EMAC_RJA) Receive Jabbers Register
+#define EMAC_USF        (AT91_CAST(AT91_REG *) 	0x00000080) // (EMAC_USF) Undersize Frames Register
+#define EMAC_STE        (AT91_CAST(AT91_REG *) 	0x00000084) // (EMAC_STE) SQE Test Error Register
+#define EMAC_RLE        (AT91_CAST(AT91_REG *) 	0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register
+#define EMAC_TPF        (AT91_CAST(AT91_REG *) 	0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register
+#define EMAC_HRB        (AT91_CAST(AT91_REG *) 	0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0]
+#define EMAC_HRT        (AT91_CAST(AT91_REG *) 	0x00000094) // (EMAC_HRT) Hash Address Top[63:32]
+#define EMAC_SA1L       (AT91_CAST(AT91_REG *) 	0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes
+#define EMAC_SA1H       (AT91_CAST(AT91_REG *) 	0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes
+#define EMAC_SA2L       (AT91_CAST(AT91_REG *) 	0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes
+#define EMAC_SA2H       (AT91_CAST(AT91_REG *) 	0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes
+#define EMAC_SA3L       (AT91_CAST(AT91_REG *) 	0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes
+#define EMAC_SA3H       (AT91_CAST(AT91_REG *) 	0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes
+#define EMAC_SA4L       (AT91_CAST(AT91_REG *) 	0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes
+#define EMAC_SA4H       (AT91_CAST(AT91_REG *) 	0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes
+#define EMAC_TID        (AT91_CAST(AT91_REG *) 	0x000000B8) // (EMAC_TID) Type ID Checking Register
+#define EMAC_TPQ        (AT91_CAST(AT91_REG *) 	0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register
+#define EMAC_USRIO      (AT91_CAST(AT91_REG *) 	0x000000C0) // (EMAC_USRIO) USER Input/Output Register
+#define EMAC_WOL        (AT91_CAST(AT91_REG *) 	0x000000C4) // (EMAC_WOL) Wake On LAN Register
+#define EMAC_REV        (AT91_CAST(AT91_REG *) 	0x000000FC) // (EMAC_REV) Revision Register
+
+#endif
+// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+#define AT91C_EMAC_LB         (0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB        (0x1 <<  1) // (EMAC) Loopback local. 
+#define AT91C_EMAC_RE         (0x1 <<  2) // (EMAC) Receive enable. 
+#define AT91C_EMAC_TE         (0x1 <<  3) // (EMAC) Transmit enable. 
+#define AT91C_EMAC_MPE        (0x1 <<  4) // (EMAC) Management port enable. 
+#define AT91C_EMAC_CLRSTAT    (0x1 <<  5) // (EMAC) Clear statistics registers. 
+#define AT91C_EMAC_INCSTAT    (0x1 <<  6) // (EMAC) Increment statistics registers. 
+#define AT91C_EMAC_WESTAT     (0x1 <<  7) // (EMAC) Write enable for statistics registers. 
+#define AT91C_EMAC_BP         (0x1 <<  8) // (EMAC) Back pressure. 
+#define AT91C_EMAC_TSTART     (0x1 <<  9) // (EMAC) Start Transmission. 
+#define AT91C_EMAC_THALT      (0x1 << 10) // (EMAC) Transmission Halt. 
+#define AT91C_EMAC_TPFR       (0x1 << 11) // (EMAC) Transmit pause frame 
+#define AT91C_EMAC_TZQ        (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+#define AT91C_EMAC_SPD        (0x1 <<  0) // (EMAC) Speed. 
+#define AT91C_EMAC_FD         (0x1 <<  1) // (EMAC) Full duplex. 
+#define AT91C_EMAC_JFRAME     (0x1 <<  3) // (EMAC) Jumbo Frames. 
+#define AT91C_EMAC_CAF        (0x1 <<  4) // (EMAC) Copy all frames. 
+#define AT91C_EMAC_NBC        (0x1 <<  5) // (EMAC) No broadcast. 
+#define AT91C_EMAC_MTI        (0x1 <<  6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI        (0x1 <<  7) // (EMAC) Unicast hash enable. 
+#define AT91C_EMAC_BIG        (0x1 <<  8) // (EMAC) Receive 1522 bytes. 
+#define AT91C_EMAC_EAE        (0x1 <<  9) // (EMAC) External address match enable. 
+#define AT91C_EMAC_CLK        (0x3 << 10) // (EMAC) 
+#define 	AT91C_EMAC_CLK_HCLK_8               (0x0 << 10) // (EMAC) HCLK divided by 8
+#define 	AT91C_EMAC_CLK_HCLK_16              (0x1 << 10) // (EMAC) HCLK divided by 16
+#define 	AT91C_EMAC_CLK_HCLK_32              (0x2 << 10) // (EMAC) HCLK divided by 32
+#define 	AT91C_EMAC_CLK_HCLK_64              (0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY        (0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PAE        (0x1 << 13) // (EMAC) 
+#define AT91C_EMAC_RBOF       (0x3 << 14) // (EMAC) 
+#define 	AT91C_EMAC_RBOF_OFFSET_0             (0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_1             (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_2             (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_3             (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE       (0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS      (0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD      (0x1 << 18) // (EMAC) 
+#define AT91C_EMAC_IRXFCS     (0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+#define AT91C_EMAC_LINKR      (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_MDIO       (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_IDLE       (0x1 <<  2) // (EMAC) 
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+#define AT91C_EMAC_UBR        (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_COL        (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RLES       (0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TGO        (0x1 <<  3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX        (0x1 <<  4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP       (0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_UND        (0x1 <<  6) // (EMAC) 
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+#define AT91C_EMAC_BNA        (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_REC        (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_OVR        (0x1 <<  2) // (EMAC) 
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+#define AT91C_EMAC_MFD        (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_RCOMP      (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RXUBR      (0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TXUBR      (0x1 <<  3) // (EMAC) 
+#define AT91C_EMAC_TUNDR      (0x1 <<  4) // (EMAC) 
+#define AT91C_EMAC_RLEX       (0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_TXERR      (0x1 <<  6) // (EMAC) 
+#define AT91C_EMAC_TCOMP      (0x1 <<  7) // (EMAC) 
+#define AT91C_EMAC_LINK       (0x1 <<  9) // (EMAC) 
+#define AT91C_EMAC_ROVR       (0x1 << 10) // (EMAC) 
+#define AT91C_EMAC_HRESP      (0x1 << 11) // (EMAC) 
+#define AT91C_EMAC_PFRE       (0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PTZ        (0x1 << 13) // (EMAC) 
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+#define AT91C_EMAC_DATA       (0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_CODE       (0x3 << 16) // (EMAC) 
+#define AT91C_EMAC_REGA       (0x1F << 18) // (EMAC) 
+#define AT91C_EMAC_PHYA       (0x1F << 23) // (EMAC) 
+#define AT91C_EMAC_RW         (0x3 << 28) // (EMAC) 
+#define AT91C_EMAC_SOF        (0x3 << 30) // (EMAC) 
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+#define AT91C_EMAC_RMII       (0x1 <<  0) // (EMAC) Reduce MII
+#define AT91C_EMAC_CLKEN      (0x1 <<  1) // (EMAC) Clock Enable
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+#define AT91C_EMAC_IP         (0xFFFF <<  0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG        (0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP        (0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1        (0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+#define AT91C_EMAC_REVREF     (0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_PARTREF    (0xFFFF << 16) // (EMAC) 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_UDP {
+	AT91_REG	 UDP_NUM; 	// Frame Number Register
+	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
+	AT91_REG	 UDP_FADDR; 	// Function Address Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
+	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
+	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
+	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
+	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
+	AT91_REG	 Reserved4[3]; 	// 
+	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
+#else
+#define UDP_FRM_NUM     (AT91_CAST(AT91_REG *) 	0x00000000) // (UDP_FRM_NUM) Frame Number Register
+#define UDP_GLBSTATE    (AT91_CAST(AT91_REG *) 	0x00000004) // (UDP_GLBSTATE) Global State Register
+#define UDP_FADDR       (AT91_CAST(AT91_REG *) 	0x00000008) // (UDP_FADDR) Function Address Register
+#define UDP_IER         (AT91_CAST(AT91_REG *) 	0x00000010) // (UDP_IER) Interrupt Enable Register
+#define UDP_IDR         (AT91_CAST(AT91_REG *) 	0x00000014) // (UDP_IDR) Interrupt Disable Register
+#define UDP_IMR         (AT91_CAST(AT91_REG *) 	0x00000018) // (UDP_IMR) Interrupt Mask Register
+#define UDP_ISR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (UDP_ISR) Interrupt Status Register
+#define UDP_ICR         (AT91_CAST(AT91_REG *) 	0x00000020) // (UDP_ICR) Interrupt Clear Register
+#define UDP_RSTEP       (AT91_CAST(AT91_REG *) 	0x00000028) // (UDP_RSTEP) Reset Endpoint Register
+#define UDP_CSR         (AT91_CAST(AT91_REG *) 	0x00000030) // (UDP_CSR) Endpoint Control and Status Register
+#define UDP_FDR         (AT91_CAST(AT91_REG *) 	0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
+#define UDP_TXVC        (AT91_CAST(AT91_REG *) 	0x00000074) // (UDP_TXVC) Transceiver Control Register
+
+#endif
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+#define AT91C_UDP_FRM_NUM     (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR     (0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK      (0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+#define AT91C_UDP_FADDEN      (0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG       (0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_ESR         (0x1 <<  2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR     (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE      (0x1 <<  4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+#define AT91C_UDP_FADD        (0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN         (0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+#define AT91C_UDP_EPINT0      (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1      (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2      (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3      (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4      (0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5      (0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP      (0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM       (0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM      (0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT      (0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP      (0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+#define AT91C_UDP_ENDBUSRES   (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+#define AT91C_UDP_EP0         (0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1         (0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2         (0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3         (0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4         (0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5         (0x1 <<  5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+#define AT91C_UDP_TXCOMP      (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 (0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP     (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR    (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_STALLSENT   (0x1 <<  3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
+#define AT91C_UDP_TXPKTRDY    (0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL  (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR         (0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE      (0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE       (0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS       (0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT   (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+#define AT91C_UDP_TXVDIS      (0x1 <<  8) // (UDP) 
+#define AT91C_UDP_PUON        (0x1 <<  9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Host Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_UHP {
+	AT91_REG	 UHP_HcRevision; 	// Revision
+	AT91_REG	 UHP_HcControl; 	// Operating modes for the Host Controller
+	AT91_REG	 UHP_HcCommandStatus; 	// Command & status Register
+	AT91_REG	 UHP_HcInterruptStatus; 	// Interrupt Status Register
+	AT91_REG	 UHP_HcInterruptEnable; 	// Interrupt Enable Register
+	AT91_REG	 UHP_HcInterruptDisable; 	// Interrupt Disable Register
+	AT91_REG	 UHP_HcHCCA; 	// Pointer to the Host Controller Communication Area
+	AT91_REG	 UHP_HcPeriodCurrentED; 	// Current Isochronous or Interrupt Endpoint Descriptor
+	AT91_REG	 UHP_HcControlHeadED; 	// First Endpoint Descriptor of the Control list
+	AT91_REG	 UHP_HcControlCurrentED; 	// Endpoint Control and Status Register
+	AT91_REG	 UHP_HcBulkHeadED; 	// First endpoint register of the Bulk list
+	AT91_REG	 UHP_HcBulkCurrentED; 	// Current endpoint of the Bulk list
+	AT91_REG	 UHP_HcBulkDoneHead; 	// Last completed transfer descriptor
+	AT91_REG	 UHP_HcFmInterval; 	// Bit time between 2 consecutive SOFs
+	AT91_REG	 UHP_HcFmRemaining; 	// Bit time remaining in the current Frame
+	AT91_REG	 UHP_HcFmNumber; 	// Frame number
+	AT91_REG	 UHP_HcPeriodicStart; 	// Periodic Start
+	AT91_REG	 UHP_HcLSThreshold; 	// LS Threshold
+	AT91_REG	 UHP_HcRhDescriptorA; 	// Root Hub characteristics A
+	AT91_REG	 UHP_HcRhDescriptorB; 	// Root Hub characteristics B
+	AT91_REG	 UHP_HcRhStatus; 	// Root Hub Status register
+	AT91_REG	 UHP_HcRhPortStatus[2]; 	// Root Hub Port Status Register
+} AT91S_UHP, *AT91PS_UHP;
+#else
+#define HcRevision      (AT91_CAST(AT91_REG *) 	0x00000000) // (HcRevision) Revision
+#define HcControl       (AT91_CAST(AT91_REG *) 	0x00000004) // (HcControl) Operating modes for the Host Controller
+#define HcCommandStatus (AT91_CAST(AT91_REG *) 	0x00000008) // (HcCommandStatus) Command & status Register
+#define HcInterruptStatus (AT91_CAST(AT91_REG *) 	0x0000000C) // (HcInterruptStatus) Interrupt Status Register
+#define HcInterruptEnable (AT91_CAST(AT91_REG *) 	0x00000010) // (HcInterruptEnable) Interrupt Enable Register
+#define HcInterruptDisable (AT91_CAST(AT91_REG *) 	0x00000014) // (HcInterruptDisable) Interrupt Disable Register
+#define HcHCCA          (AT91_CAST(AT91_REG *) 	0x00000018) // (HcHCCA) Pointer to the Host Controller Communication Area
+#define HcPeriodCurrentED (AT91_CAST(AT91_REG *) 	0x0000001C) // (HcPeriodCurrentED) Current Isochronous or Interrupt Endpoint Descriptor
+#define HcControlHeadED (AT91_CAST(AT91_REG *) 	0x00000020) // (HcControlHeadED) First Endpoint Descriptor of the Control list
+#define HcControlCurrentED (AT91_CAST(AT91_REG *) 	0x00000024) // (HcControlCurrentED) Endpoint Control and Status Register
+#define HcBulkHeadED    (AT91_CAST(AT91_REG *) 	0x00000028) // (HcBulkHeadED) First endpoint register of the Bulk list
+#define HcBulkCurrentED (AT91_CAST(AT91_REG *) 	0x0000002C) // (HcBulkCurrentED) Current endpoint of the Bulk list
+#define HcBulkDoneHead  (AT91_CAST(AT91_REG *) 	0x00000030) // (HcBulkDoneHead) Last completed transfer descriptor
+#define HcFmInterval    (AT91_CAST(AT91_REG *) 	0x00000034) // (HcFmInterval) Bit time between 2 consecutive SOFs
+#define HcFmRemaining   (AT91_CAST(AT91_REG *) 	0x00000038) // (HcFmRemaining) Bit time remaining in the current Frame
+#define HcFmNumber      (AT91_CAST(AT91_REG *) 	0x0000003C) // (HcFmNumber) Frame number
+#define HcPeriodicStart (AT91_CAST(AT91_REG *) 	0x00000040) // (HcPeriodicStart) Periodic Start
+#define HcLSThreshold   (AT91_CAST(AT91_REG *) 	0x00000044) // (HcLSThreshold) LS Threshold
+#define HcRhDescriptorA (AT91_CAST(AT91_REG *) 	0x00000048) // (HcRhDescriptorA) Root Hub characteristics A
+#define HcRhDescriptorB (AT91_CAST(AT91_REG *) 	0x0000004C) // (HcRhDescriptorB) Root Hub characteristics B
+#define HcRhStatus      (AT91_CAST(AT91_REG *) 	0x00000050) // (HcRhStatus) Root Hub Status register
+#define HcRhPortStatus  (AT91_CAST(AT91_REG *) 	0x00000054) // (HcRhPortStatus) Root Hub Port Status Register
+
+#endif
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Image Sensor Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_ISI {
+	AT91_REG	 ISI_CR1; 	// Control Register 1
+	AT91_REG	 ISI_CR2; 	// Control Register 2
+	AT91_REG	 ISI_SR; 	// Status Register
+	AT91_REG	 ISI_IER; 	// Interrupt Enable Register
+	AT91_REG	 ISI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 ISI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 ISI_PSIZE; 	// Preview Size Register
+	AT91_REG	 ISI_PDECF; 	// Preview Decimation Factor Register
+	AT91_REG	 ISI_PFBD; 	// Preview Frame Buffer Address Register
+	AT91_REG	 ISI_CDBA; 	// Codec Dma Address Register
+	AT91_REG	 ISI_Y2RSET0; 	// Color Space Conversion Register
+	AT91_REG	 ISI_Y2RSET1; 	// Color Space Conversion Register
+	AT91_REG	 ISI_R2YSET0; 	// Color Space Conversion Register
+	AT91_REG	 ISI_R2YSET1; 	// Color Space Conversion Register
+	AT91_REG	 ISI_R2YSET2; 	// Color Space Conversion Register
+} AT91S_ISI, *AT91PS_ISI;
+#else
+#define ISI_CR1         (AT91_CAST(AT91_REG *) 	0x00000000) // (ISI_CR1) Control Register 1
+#define ISI_CR2         (AT91_CAST(AT91_REG *) 	0x00000004) // (ISI_CR2) Control Register 2
+#define ISI_SR          (AT91_CAST(AT91_REG *) 	0x00000008) // (ISI_SR) Status Register
+#define ISI_IER         (AT91_CAST(AT91_REG *) 	0x0000000C) // (ISI_IER) Interrupt Enable Register
+#define ISI_IDR         (AT91_CAST(AT91_REG *) 	0x00000010) // (ISI_IDR) Interrupt Disable Register
+#define ISI_IMR         (AT91_CAST(AT91_REG *) 	0x00000014) // (ISI_IMR) Interrupt Mask Register
+#define ISI_PSIZE       (AT91_CAST(AT91_REG *) 	0x00000020) // (ISI_PSIZE) Preview Size Register
+#define ISI_PDECF       (AT91_CAST(AT91_REG *) 	0x00000024) // (ISI_PDECF) Preview Decimation Factor Register
+#define ISI_PFBD        (AT91_CAST(AT91_REG *) 	0x00000028) // (ISI_PFBD) Preview Frame Buffer Address Register
+#define ISI_CDBA        (AT91_CAST(AT91_REG *) 	0x0000002C) // (ISI_CDBA) Codec Dma Address Register
+#define ISI_Y2RSET0     (AT91_CAST(AT91_REG *) 	0x00000030) // (ISI_Y2RSET0) Color Space Conversion Register
+#define ISI_Y2RSET1     (AT91_CAST(AT91_REG *) 	0x00000034) // (ISI_Y2RSET1) Color Space Conversion Register
+#define ISI_R2YSET0     (AT91_CAST(AT91_REG *) 	0x00000038) // (ISI_R2YSET0) Color Space Conversion Register
+#define ISI_R2YSET1     (AT91_CAST(AT91_REG *) 	0x0000003C) // (ISI_R2YSET1) Color Space Conversion Register
+#define ISI_R2YSET2     (AT91_CAST(AT91_REG *) 	0x00000040) // (ISI_R2YSET2) Color Space Conversion Register
+
+#endif
+// -------- ISI_CR1 : (ISI Offset: 0x0) ISI Control Register 1 -------- 
+#define AT91C_ISI_RST         (0x1 <<  0) // (ISI) Image sensor interface reset
+#define AT91C_ISI_DISABLE     (0x1 <<  1) // (ISI) image sensor disable.
+#define AT91C_ISI_HSYNC_POL   (0x1 <<  2) // (ISI) Horizontal synchronisation polarity
+#define AT91C_ISI_PIXCLK_POL  (0x1 <<  4) // (ISI) Pixel Clock Polarity
+#define AT91C_ISI_EMB_SYNC    (0x1 <<  6) // (ISI) Embedded synchronisation
+#define AT91C_ISI_CRC_SYNC    (0x1 <<  7) // (ISI) CRC correction
+#define AT91C_ISI_FULL        (0x1 << 12) // (ISI) Full mode is allowed
+#define AT91C_ISI_THMASK      (0x3 << 13) // (ISI) DMA Burst Mask
+#define 	AT91C_ISI_THMASK_4_8_16_BURST         (0x0 << 13) // (ISI) 4,8 and 16 AHB burst are allowed
+#define 	AT91C_ISI_THMASK_8_16_BURST           (0x1 << 13) // (ISI) 8 and 16 AHB burst are allowed
+#define 	AT91C_ISI_THMASK_16_BURST             (0x2 << 13) // (ISI) Only 16 AHB burst are allowed
+#define AT91C_ISI_CODEC_ON    (0x1 << 15) // (ISI) Enable the codec path
+#define AT91C_ISI_SLD         (0xFF << 16) // (ISI) Start of Line Delay
+#define AT91C_ISI_SFD         (0xFF << 24) // (ISI) Start of frame Delay
+// -------- ISI_CR2 : (ISI Offset: 0x4) ISI Control Register 2 -------- 
+#define AT91C_ISI_IM_VSIZE    (0x7FF <<  0) // (ISI) Vertical size of the Image sensor [0..2047]
+#define AT91C_ISI_GS_MODE     (0x1 << 11) // (ISI) Grayscale Memory Mode
+#define AT91C_ISI_RGB_MODE    (0x3 << 12) // (ISI) RGB mode
+#define 	AT91C_ISI_RGB_MODE_RGB_888              (0x0 << 12) // (ISI) RGB 8:8:8 24 bits
+#define 	AT91C_ISI_RGB_MODE_RGB_565              (0x1 << 12) // (ISI) RGB 5:6:5 16 bits
+#define 	AT91C_ISI_RGB_MODE_RGB_555              (0x2 << 12) // (ISI) RGB 5:5:5 16 bits
+#define AT91C_ISI_GRAYSCALE   (0x1 << 13) // (ISI) Grayscale Mode
+#define AT91C_ISI_RGB_SWAP    (0x1 << 14) // (ISI) RGB Swap
+#define AT91C_ISI_COL_SPACE   (0x1 << 15) // (ISI) Color space for the image data
+#define AT91C_ISI_IM_HSIZE    (0x7FF << 16) // (ISI) Horizontal size of the Image sensor [0..2047]
+#define 	AT91C_ISI_RGB_MODE_YCC_DEF              (0x0 << 28) // (ISI) Cb(i) Y(i) Cr(i) Y(i+1)
+#define 	AT91C_ISI_RGB_MODE_YCC_MOD1             (0x1 << 28) // (ISI) Cr(i) Y(i) Cb(i) Y(i+1)
+#define 	AT91C_ISI_RGB_MODE_YCC_MOD2             (0x2 << 28) // (ISI) Y(i) Cb(i) Y(i+1) Cr(i)
+#define 	AT91C_ISI_RGB_MODE_YCC_MOD3             (0x3 << 28) // (ISI) Y(i) Cr(i) Y(i+1) Cb(i)
+#define AT91C_ISI_RGB_CFG     (0x3 << 30) // (ISI) RGB configuration
+#define 	AT91C_ISI_RGB_CFG_RGB_DEF              (0x0 << 30) // (ISI) R/G(MSB)  G(LSB)/B  R/G(MSB)  G(LSB)/B
+#define 	AT91C_ISI_RGB_CFG_RGB_MOD1             (0x1 << 30) // (ISI) B/G(MSB)  G(LSB)/R  B/G(MSB)  G(LSB)/R
+#define 	AT91C_ISI_RGB_CFG_RGB_MOD2             (0x2 << 30) // (ISI) G(LSB)/R  B/G(MSB)  G(LSB)/R  B/G(MSB)
+#define 	AT91C_ISI_RGB_CFG_RGB_MOD3             (0x3 << 30) // (ISI) G(LSB)/B  R/G(MSB)  G(LSB)/B  R/G(MSB)
+// -------- ISI_SR : (ISI Offset: 0x8) ISI Status Register -------- 
+#define AT91C_ISI_SOF         (0x1 <<  0) // (ISI) Start of Frame
+#define AT91C_ISI_DIS         (0x1 <<  1) // (ISI) Image Sensor Interface disable
+#define AT91C_ISI_SOFTRST     (0x1 <<  2) // (ISI) Software Reset
+#define AT91C_ISI_CRC_ERR     (0x1 <<  4) // (ISI) CRC synchronisation error
+#define AT91C_ISI_FO_C_OVF    (0x1 <<  5) // (ISI) Fifo Codec Overflow 
+#define AT91C_ISI_FO_P_OVF    (0x1 <<  6) // (ISI) Fifo Preview Overflow 
+#define AT91C_ISI_FO_P_EMP    (0x1 <<  7) // (ISI) Fifo Preview Empty
+#define AT91C_ISI_FO_C_EMP    (0x1 <<  8) // (ISI) Fifo Codec Empty
+#define AT91C_ISI_FR_OVR      (0x1 <<  9) // (ISI) Frame rate overun
+// -------- ISI_IER : (ISI Offset: 0xc) ISI Interrupt Enable Register -------- 
+// -------- ISI_IDR : (ISI Offset: 0x10) ISI Interrupt Disable Register -------- 
+// -------- ISI_IMR : (ISI Offset: 0x14) ISI Interrupt Mask Register -------- 
+// -------- ISI_PSIZE : (ISI Offset: 0x20) ISI Preview Register -------- 
+#define AT91C_ISI_PREV_VSIZE  (0x3FF <<  0) // (ISI) Vertical size for the preview path
+#define AT91C_ISI_PREV_HSIZE  (0x3FF << 16) // (ISI) Horizontal size for the preview path
+// -------- ISI_Y2R_SET0 : (ISI Offset: 0x30) Color Space Conversion YCrCb to RGB Register -------- 
+#define AT91C_ISI_Y2R_C0      (0xFF <<  0) // (ISI) Color Space Conversion Matrix Coefficient C0
+#define AT91C_ISI_Y2R_C1      (0xFF <<  8) // (ISI) Color Space Conversion Matrix Coefficient C1
+#define AT91C_ISI_Y2R_C2      (0xFF << 16) // (ISI) Color Space Conversion Matrix Coefficient C2
+#define AT91C_ISI_Y2R_C3      (0xFF << 24) // (ISI) Color Space Conversion Matrix Coefficient C3
+// -------- ISI_Y2R_SET1 : (ISI Offset: 0x34) ISI Color Space Conversion YCrCb to RGB set 1 Register -------- 
+#define AT91C_ISI_Y2R_C4      (0x1FF <<  0) // (ISI) Color Space Conversion Matrix Coefficient C4
+#define AT91C_ISI_Y2R_YOFF    (0xFF << 12) // (ISI) Color Space Conversion Luninance default offset
+#define AT91C_ISI_Y2R_CROFF   (0xFF << 13) // (ISI) Color Space Conversion Red Chrominance default offset
+#define AT91C_ISI_Y2R_CBFF    (0xFF << 14) // (ISI) Color Space Conversion Luninance default offset
+// -------- ISI_R2Y_SET0 : (ISI Offset: 0x38) Color Space Conversion RGB to YCrCb set 0 register -------- 
+#define AT91C_ISI_R2Y_C0      (0x7F <<  0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C0
+#define AT91C_ISI_R2Y_C1      (0x7F <<  1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C1
+#define AT91C_ISI_R2Y_C2      (0x7F <<  3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C2
+#define AT91C_ISI_R2Y_ROFF    (0x1 <<  4) // (ISI) Color Space Conversion Red component offset
+// -------- ISI_R2Y_SET1 : (ISI Offset: 0x3c) Color Space Conversion RGB to YCrCb set 1 register -------- 
+#define AT91C_ISI_R2Y_C3      (0x7F <<  0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C3
+#define AT91C_ISI_R2Y_C4      (0x7F <<  1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C4
+#define AT91C_ISI_R2Y_C5      (0x7F <<  3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C5
+#define AT91C_ISI_R2Y_GOFF    (0x1 <<  4) // (ISI) Color Space Conversion Green component offset
+// -------- ISI_R2Y_SET2 : (ISI Offset: 0x40) Color Space Conversion RGB to YCrCb set 2 register -------- 
+#define AT91C_ISI_R2Y_C6      (0x7F <<  0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C6
+#define AT91C_ISI_R2Y_C7      (0x7F <<  1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C7
+#define AT91C_ISI_R2Y_C8      (0x7F <<  3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C8
+#define AT91C_ISI_R2Y_BOFF    (0x1 <<  4) // (ISI) Color Space Conversion Blue component offset
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM9XE256
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ========== 
+#define AT91C_SYS_GPBR  (AT91_CAST(AT91_REG *) 	0xFFFFFFFF) // (SYS) General Purpose Register
+// ========== Register definition for EBI peripheral ========== 
+#define AT91C_EBI_DUMMY (AT91_CAST(AT91_REG *) 	0xFFFFEA00) // (EBI) Dummy register - Do not use
+// ========== Register definition for HECC peripheral ========== 
+#define AT91C_HECC_VR   (AT91_CAST(AT91_REG *) 	0xFFFFE8FC) // (HECC)  ECC Version register
+#define AT91C_HECC_NPR  (AT91_CAST(AT91_REG *) 	0xFFFFE810) // (HECC)  ECC Parity N register
+#define AT91C_HECC_SR   (AT91_CAST(AT91_REG *) 	0xFFFFE808) // (HECC)  ECC Status register
+#define AT91C_HECC_PR   (AT91_CAST(AT91_REG *) 	0xFFFFE80C) // (HECC)  ECC Parity register
+#define AT91C_HECC_MR   (AT91_CAST(AT91_REG *) 	0xFFFFE804) // (HECC)  ECC Page size register
+#define AT91C_HECC_CR   (AT91_CAST(AT91_REG *) 	0xFFFFE800) // (HECC)  ECC reset register
+// ========== Register definition for SDRAMC peripheral ========== 
+#define AT91C_SDRAMC_MR (AT91_CAST(AT91_REG *) 	0xFFFFEA00) // (SDRAMC) SDRAM Controller Mode Register
+#define AT91C_SDRAMC_IMR (AT91_CAST(AT91_REG *) 	0xFFFFEA1C) // (SDRAMC) SDRAM Controller Interrupt Mask Register
+#define AT91C_SDRAMC_LPR (AT91_CAST(AT91_REG *) 	0xFFFFEA10) // (SDRAMC) SDRAM Controller Low Power Register
+#define AT91C_SDRAMC_ISR (AT91_CAST(AT91_REG *) 	0xFFFFEA20) // (SDRAMC) SDRAM Controller Interrupt Mask Register
+#define AT91C_SDRAMC_IDR (AT91_CAST(AT91_REG *) 	0xFFFFEA18) // (SDRAMC) SDRAM Controller Interrupt Disable Register
+#define AT91C_SDRAMC_CR (AT91_CAST(AT91_REG *) 	0xFFFFEA08) // (SDRAMC) SDRAM Controller Configuration Register
+#define AT91C_SDRAMC_TR (AT91_CAST(AT91_REG *) 	0xFFFFEA04) // (SDRAMC) SDRAM Controller Refresh Timer Register
+#define AT91C_SDRAMC_MDR (AT91_CAST(AT91_REG *) 	0xFFFFEA24) // (SDRAMC) SDRAM Memory Device Register
+#define AT91C_SDRAMC_HSR (AT91_CAST(AT91_REG *) 	0xFFFFEA0C) // (SDRAMC) SDRAM Controller High Speed Register
+#define AT91C_SDRAMC_IER (AT91_CAST(AT91_REG *) 	0xFFFFEA14) // (SDRAMC) SDRAM Controller Interrupt Enable Register
+// ========== Register definition for SMC peripheral ========== 
+#define AT91C_SMC_CTRL1 (AT91_CAST(AT91_REG *) 	0xFFFFEC1C) // (SMC)  Control Register for CS 1
+#define AT91C_SMC_PULSE7 (AT91_CAST(AT91_REG *) 	0xFFFFEC74) // (SMC)  Pulse Register for CS 7
+#define AT91C_SMC_PULSE6 (AT91_CAST(AT91_REG *) 	0xFFFFEC64) // (SMC)  Pulse Register for CS 6
+#define AT91C_SMC_SETUP4 (AT91_CAST(AT91_REG *) 	0xFFFFEC40) // (SMC)  Setup Register for CS 4
+#define AT91C_SMC_PULSE3 (AT91_CAST(AT91_REG *) 	0xFFFFEC34) // (SMC)  Pulse Register for CS 3
+#define AT91C_SMC_CYCLE5 (AT91_CAST(AT91_REG *) 	0xFFFFEC58) // (SMC)  Cycle Register for CS 5
+#define AT91C_SMC_CYCLE2 (AT91_CAST(AT91_REG *) 	0xFFFFEC28) // (SMC)  Cycle Register for CS 2
+#define AT91C_SMC_CTRL2 (AT91_CAST(AT91_REG *) 	0xFFFFEC2C) // (SMC)  Control Register for CS 2
+#define AT91C_SMC_CTRL0 (AT91_CAST(AT91_REG *) 	0xFFFFEC0C) // (SMC)  Control Register for CS 0
+#define AT91C_SMC_PULSE5 (AT91_CAST(AT91_REG *) 	0xFFFFEC54) // (SMC)  Pulse Register for CS 5
+#define AT91C_SMC_PULSE1 (AT91_CAST(AT91_REG *) 	0xFFFFEC14) // (SMC)  Pulse Register for CS 1
+#define AT91C_SMC_PULSE0 (AT91_CAST(AT91_REG *) 	0xFFFFEC04) // (SMC)  Pulse Register for CS 0
+#define AT91C_SMC_CYCLE7 (AT91_CAST(AT91_REG *) 	0xFFFFEC78) // (SMC)  Cycle Register for CS 7
+#define AT91C_SMC_CTRL4 (AT91_CAST(AT91_REG *) 	0xFFFFEC4C) // (SMC)  Control Register for CS 4
+#define AT91C_SMC_CTRL3 (AT91_CAST(AT91_REG *) 	0xFFFFEC3C) // (SMC)  Control Register for CS 3
+#define AT91C_SMC_SETUP7 (AT91_CAST(AT91_REG *) 	0xFFFFEC70) // (SMC)  Setup Register for CS 7
+#define AT91C_SMC_CTRL7 (AT91_CAST(AT91_REG *) 	0xFFFFEC7C) // (SMC)  Control Register for CS 7
+#define AT91C_SMC_SETUP1 (AT91_CAST(AT91_REG *) 	0xFFFFEC10) // (SMC)  Setup Register for CS 1
+#define AT91C_SMC_CYCLE0 (AT91_CAST(AT91_REG *) 	0xFFFFEC08) // (SMC)  Cycle Register for CS 0
+#define AT91C_SMC_CTRL5 (AT91_CAST(AT91_REG *) 	0xFFFFEC5C) // (SMC)  Control Register for CS 5
+#define AT91C_SMC_CYCLE1 (AT91_CAST(AT91_REG *) 	0xFFFFEC18) // (SMC)  Cycle Register for CS 1
+#define AT91C_SMC_CTRL6 (AT91_CAST(AT91_REG *) 	0xFFFFEC6C) // (SMC)  Control Register for CS 6
+#define AT91C_SMC_SETUP0 (AT91_CAST(AT91_REG *) 	0xFFFFEC00) // (SMC)  Setup Register for CS 0
+#define AT91C_SMC_PULSE4 (AT91_CAST(AT91_REG *) 	0xFFFFEC44) // (SMC)  Pulse Register for CS 4
+#define AT91C_SMC_SETUP5 (AT91_CAST(AT91_REG *) 	0xFFFFEC50) // (SMC)  Setup Register for CS 5
+#define AT91C_SMC_SETUP2 (AT91_CAST(AT91_REG *) 	0xFFFFEC20) // (SMC)  Setup Register for CS 2
+#define AT91C_SMC_CYCLE3 (AT91_CAST(AT91_REG *) 	0xFFFFEC38) // (SMC)  Cycle Register for CS 3
+#define AT91C_SMC_CYCLE6 (AT91_CAST(AT91_REG *) 	0xFFFFEC68) // (SMC)  Cycle Register for CS 6
+#define AT91C_SMC_SETUP6 (AT91_CAST(AT91_REG *) 	0xFFFFEC60) // (SMC)  Setup Register for CS 6
+#define AT91C_SMC_CYCLE4 (AT91_CAST(AT91_REG *) 	0xFFFFEC48) // (SMC)  Cycle Register for CS 4
+#define AT91C_SMC_PULSE2 (AT91_CAST(AT91_REG *) 	0xFFFFEC24) // (SMC)  Pulse Register for CS 2
+#define AT91C_SMC_SETUP3 (AT91_CAST(AT91_REG *) 	0xFFFFEC30) // (SMC)  Setup Register for CS 3
+// ========== Register definition for MATRIX peripheral ========== 
+#define AT91C_MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 	0xFFFFEE00) // (MATRIX)  Master Configuration Register 0 (ram96k)     
+#define AT91C_MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 	0xFFFFEE1C) // (MATRIX)  Master Configuration Register 7 (teak_prog)     
+#define AT91C_MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 	0xFFFFEE44) // (MATRIX)  Slave Configuration Register 1 (rom)    
+#define AT91C_MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 	0xFFFFEE10) // (MATRIX)  Master Configuration Register 4 (bridge)    
+#define AT91C_MATRIX_VERSION (AT91_CAST(AT91_REG *) 	0xFFFFEFFC) // (MATRIX)  Version Register
+#define AT91C_MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 	0xFFFFEE08) // (MATRIX)  Master Configuration Register 2 (hperiphs) 
+#define AT91C_MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 	0xFFFFEEA4) // (MATRIX)  PRBS4 : ebi
+#define AT91C_MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 	0xFFFFEE84) // (MATRIX)  PRBS0 (ram0) 
+#define AT91C_MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 	0xFFFFEE4C) // (MATRIX)  Slave Configuration Register 3 (ebi)
+#define AT91C_MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 	0xFFFFEE18) // (MATRIX)  Master Configuration Register 6 (ram16k)  
+#define AT91C_MATRIX_EBI (AT91_CAST(AT91_REG *) 	0xFFFFEF1C) // (MATRIX)  Slave 3 (ebi) Special Function Register
+#define AT91C_MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 	0xFFFFEE40) // (MATRIX)  Slave Configuration Register 0 (ram96k)     
+#define AT91C_MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 	0xFFFFEE9C) // (MATRIX)  PRBS3 : usb_dev_hs
+#define AT91C_MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 	0xFFFFEE98) // (MATRIX)  PRAS3 : usb_dev_hs
+#define AT91C_MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 	0xFFFFEE80) // (MATRIX)  PRAS0 (ram0) 
+#define AT91C_MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 	0xFFFFEE0C) // (MATRIX)  Master Configuration Register 3 (ebi)
+#define AT91C_MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 	0xFFFFEE88) // (MATRIX)  PRAS1 (ram1) 
+#define AT91C_MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 	0xFFFFEE90) // (MATRIX)  PRAS2 (ram2) 
+#define AT91C_MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 	0xFFFFEE48) // (MATRIX)  Slave Configuration Register 2 (hperiphs) 
+#define AT91C_MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 	0xFFFFEE14) // (MATRIX)  Master Configuration Register 5 (mailbox)    
+#define AT91C_MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 	0xFFFFEE04) // (MATRIX)  Master Configuration Register 1 (rom)    
+#define AT91C_MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 	0xFFFFEEA0) // (MATRIX)  PRAS4 : ebi
+#define AT91C_MATRIX_MRCR (AT91_CAST(AT91_REG *) 	0xFFFFEF00) // (MATRIX)  Master Remp Control Register 
+#define AT91C_MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 	0xFFFFEE94) // (MATRIX)  PRBS2 (ram2) 
+#define AT91C_MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 	0xFFFFEE50) // (MATRIX)  Slave Configuration Register 4 (bridge)    
+#define AT91C_MATRIX_TEAKCFG (AT91_CAST(AT91_REG *) 	0xFFFFEF2C) // (MATRIX)  Slave 7 (teak_prog) Special Function Register
+#define AT91C_MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 	0xFFFFEE8C) // (MATRIX)  PRBS1 (ram1) 
+// ========== Register definition for CCFG peripheral ========== 
+#define AT91C_CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 	0xFFFFEFFC) // (CCFG)  Version Register
+#define AT91C_CCFG_EBICSA (AT91_CAST(AT91_REG *) 	0xFFFFEF1C) // (CCFG)  EBI Chip Select Assignement Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_TCR  (AT91_CAST(AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR  (AT91_CAST(AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR  (AT91_CAST(AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR  (AT91_CAST(AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR  (AT91_CAST(AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR   (AT91_CAST(AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR   (AT91_CAST(AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR  (AT91_CAST(AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR  (AT91_CAST(AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_IVR   (AT91_CAST(AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR   (AT91_CAST(AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR   (AT91_CAST(AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR   (AT91_CAST(AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR   (AT91_CAST(AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR  (AT91_CAST(AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR  (AT91_CAST(AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR   (AT91_CAST(AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR   (AT91_CAST(AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER  (AT91_CAST(AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR  (AT91_CAST(AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR  (AT91_CAST(AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR  (AT91_CAST(AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR  (AT91_CAST(AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR  (AT91_CAST(AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU   (AT91_CAST(AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_ODR  (AT91_CAST(AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR  (AT91_CAST(AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER  (AT91_CAST(AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR  (AT91_CAST(AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR  (AT91_CAST(AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR  (AT91_CAST(AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR  (AT91_CAST(AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER  (AT91_CAST(AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR  (AT91_CAST(AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ========== 
+#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR  (AT91_CAST(AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR  (AT91_CAST(AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR  (AT91_CAST(AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR  (AT91_CAST(AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR  (AT91_CAST(AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR  (AT91_CAST(AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR  (AT91_CAST(AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER  (AT91_CAST(AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER  (AT91_CAST(AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for PIOC peripheral ========== 
+#define AT91C_PIOC_OWDR (AT91_CAST(AT91_REG *) 	0xFFFFF8A4) // (PIOC) Output Write Disable Register
+#define AT91C_PIOC_SODR (AT91_CAST(AT91_REG *) 	0xFFFFF830) // (PIOC) Set Output Data Register
+#define AT91C_PIOC_PPUER (AT91_CAST(AT91_REG *) 	0xFFFFF864) // (PIOC) Pull-up Enable Register
+#define AT91C_PIOC_CODR (AT91_CAST(AT91_REG *) 	0xFFFFF834) // (PIOC) Clear Output Data Register
+#define AT91C_PIOC_PSR  (AT91_CAST(AT91_REG *) 	0xFFFFF808) // (PIOC) PIO Status Register
+#define AT91C_PIOC_PDR  (AT91_CAST(AT91_REG *) 	0xFFFFF804) // (PIOC) PIO Disable Register
+#define AT91C_PIOC_ODR  (AT91_CAST(AT91_REG *) 	0xFFFFF814) // (PIOC) Output Disable Registerr
+#define AT91C_PIOC_PPUSR (AT91_CAST(AT91_REG *) 	0xFFFFF868) // (PIOC) Pull-up Status Register
+#define AT91C_PIOC_ABSR (AT91_CAST(AT91_REG *) 	0xFFFFF878) // (PIOC) AB Select Status Register
+#define AT91C_PIOC_IFSR (AT91_CAST(AT91_REG *) 	0xFFFFF828) // (PIOC) Input Filter Status Register
+#define AT91C_PIOC_OER  (AT91_CAST(AT91_REG *) 	0xFFFFF810) // (PIOC) Output Enable Register
+#define AT91C_PIOC_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF848) // (PIOC) Interrupt Mask Register
+#define AT91C_PIOC_ASR  (AT91_CAST(AT91_REG *) 	0xFFFFF870) // (PIOC) Select A Register
+#define AT91C_PIOC_MDDR (AT91_CAST(AT91_REG *) 	0xFFFFF854) // (PIOC) Multi-driver Disable Register
+#define AT91C_PIOC_OWSR (AT91_CAST(AT91_REG *) 	0xFFFFF8A8) // (PIOC) Output Write Status Register
+#define AT91C_PIOC_PER  (AT91_CAST(AT91_REG *) 	0xFFFFF800) // (PIOC) PIO Enable Register
+#define AT91C_PIOC_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF844) // (PIOC) Interrupt Disable Register
+#define AT91C_PIOC_MDER (AT91_CAST(AT91_REG *) 	0xFFFFF850) // (PIOC) Multi-driver Enable Register
+#define AT91C_PIOC_PDSR (AT91_CAST(AT91_REG *) 	0xFFFFF83C) // (PIOC) Pin Data Status Register
+#define AT91C_PIOC_MDSR (AT91_CAST(AT91_REG *) 	0xFFFFF858) // (PIOC) Multi-driver Status Register
+#define AT91C_PIOC_OWER (AT91_CAST(AT91_REG *) 	0xFFFFF8A0) // (PIOC) Output Write Enable Register
+#define AT91C_PIOC_BSR  (AT91_CAST(AT91_REG *) 	0xFFFFF874) // (PIOC) Select B Register
+#define AT91C_PIOC_PPUDR (AT91_CAST(AT91_REG *) 	0xFFFFF860) // (PIOC) Pull-up Disable Register
+#define AT91C_PIOC_IFDR (AT91_CAST(AT91_REG *) 	0xFFFFF824) // (PIOC) Input Filter Disable Register
+#define AT91C_PIOC_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF840) // (PIOC) Interrupt Enable Register
+#define AT91C_PIOC_OSR  (AT91_CAST(AT91_REG *) 	0xFFFFF818) // (PIOC) Output Status Register
+#define AT91C_PIOC_ODSR (AT91_CAST(AT91_REG *) 	0xFFFFF838) // (PIOC) Output Data Status Register
+#define AT91C_PIOC_ISR  (AT91_CAST(AT91_REG *) 	0xFFFFF84C) // (PIOC) Interrupt Status Register
+#define AT91C_PIOC_IFER (AT91_CAST(AT91_REG *) 	0xFFFFF820) // (PIOC) Input Filter Enable Register
+// ========== Register definition for EFC peripheral ========== 
+#define AT91C_EFC_FVR   (AT91_CAST(AT91_REG *) 	0xFFFFFA10) // (EFC) EFC Flash Version Register
+#define AT91C_EFC_FCR   (AT91_CAST(AT91_REG *) 	0xFFFFFA04) // (EFC) EFC Flash Command Register
+#define AT91C_EFC_FMR   (AT91_CAST(AT91_REG *) 	0xFFFFFA00) // (EFC) EFC Flash Mode Register
+#define AT91C_EFC_FRR   (AT91_CAST(AT91_REG *) 	0xFFFFFA0C) // (EFC) EFC Flash Result Register
+#define AT91C_EFC_FSR   (AT91_CAST(AT91_REG *) 	0xFFFFFA08) // (EFC) EFC Flash Status Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_MOR  (AT91_CAST(AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLBR (AT91_CAST(AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL B Register
+#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+#define AT91C_CKGR_PLLAR (AT91_CAST(AT91_REG *) 	0xFFFFFC28) // (CKGR) PLL A Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_PCER  (AT91_CAST(AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR  (AT91_CAST(AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR  (AT91_CAST(AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_PLLAR (AT91_CAST(AT91_REG *) 	0xFFFFFC28) // (PMC) PLL A Register
+#define AT91C_PMC_PCDR  (AT91_CAST(AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR  (AT91_CAST(AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_MCFR  (AT91_CAST(AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER   (AT91_CAST(AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_MOR   (AT91_CAST(AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_PLLBR (AT91_CAST(AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL B Register
+#define AT91C_PMC_SCDR  (AT91_CAST(AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCSR  (AT91_CAST(AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_SCER  (AT91_CAST(AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_SR    (AT91_CAST(AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RCR  (AT91_CAST(AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR  (AT91_CAST(AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR  (AT91_CAST(AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for SHDWC peripheral ========== 
+#define AT91C_SHDWC_SHSR (AT91_CAST(AT91_REG *) 	0xFFFFFD18) // (SHDWC) Shut Down Status Register
+#define AT91C_SHDWC_SHMR (AT91_CAST(AT91_REG *) 	0xFFFFFD14) // (SHDWC) Shut Down Mode Register
+#define AT91C_SHDWC_SHCR (AT91_CAST(AT91_REG *) 	0xFFFFFD10) // (SHDWC) Shut Down Control Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_SR    (AT91_CAST(AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC    (AT91_CAST(AT91_REG *) 	0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER   (AT91_CAST(AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER   (AT91_CAST(AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR    (AT91_CAST(AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC    (AT91_CAST(AT91_REG *) 	0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC    (AT91_CAST(AT91_REG *) 	0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER   (AT91_CAST(AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR    (AT91_CAST(AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TC3 peripheral ========== 
+#define AT91C_TC3_IER   (AT91_CAST(AT91_REG *) 	0xFFFDC024) // (TC3) Interrupt Enable Register
+#define AT91C_TC3_RB    (AT91_CAST(AT91_REG *) 	0xFFFDC018) // (TC3) Register B
+#define AT91C_TC3_CMR   (AT91_CAST(AT91_REG *) 	0xFFFDC004) // (TC3) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC3_RC    (AT91_CAST(AT91_REG *) 	0xFFFDC01C) // (TC3) Register C
+#define AT91C_TC3_CCR   (AT91_CAST(AT91_REG *) 	0xFFFDC000) // (TC3) Channel Control Register
+#define AT91C_TC3_SR    (AT91_CAST(AT91_REG *) 	0xFFFDC020) // (TC3) Status Register
+#define AT91C_TC3_CV    (AT91_CAST(AT91_REG *) 	0xFFFDC010) // (TC3) Counter Value
+#define AT91C_TC3_RA    (AT91_CAST(AT91_REG *) 	0xFFFDC014) // (TC3) Register A
+#define AT91C_TC3_IDR   (AT91_CAST(AT91_REG *) 	0xFFFDC028) // (TC3) Interrupt Disable Register
+#define AT91C_TC3_IMR   (AT91_CAST(AT91_REG *) 	0xFFFDC02C) // (TC3) Interrupt Mask Register
+// ========== Register definition for TC4 peripheral ========== 
+#define AT91C_TC4_CMR   (AT91_CAST(AT91_REG *) 	0xFFFDC044) // (TC4) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC4_RC    (AT91_CAST(AT91_REG *) 	0xFFFDC05C) // (TC4) Register C
+#define AT91C_TC4_SR    (AT91_CAST(AT91_REG *) 	0xFFFDC060) // (TC4) Status Register
+#define AT91C_TC4_RB    (AT91_CAST(AT91_REG *) 	0xFFFDC058) // (TC4) Register B
+#define AT91C_TC4_IER   (AT91_CAST(AT91_REG *) 	0xFFFDC064) // (TC4) Interrupt Enable Register
+#define AT91C_TC4_CV    (AT91_CAST(AT91_REG *) 	0xFFFDC050) // (TC4) Counter Value
+#define AT91C_TC4_RA    (AT91_CAST(AT91_REG *) 	0xFFFDC054) // (TC4) Register A
+#define AT91C_TC4_IDR   (AT91_CAST(AT91_REG *) 	0xFFFDC068) // (TC4) Interrupt Disable Register
+#define AT91C_TC4_IMR   (AT91_CAST(AT91_REG *) 	0xFFFDC06C) // (TC4) Interrupt Mask Register
+#define AT91C_TC4_CCR   (AT91_CAST(AT91_REG *) 	0xFFFDC040) // (TC4) Channel Control Register
+// ========== Register definition for TC5 peripheral ========== 
+#define AT91C_TC5_RB    (AT91_CAST(AT91_REG *) 	0xFFFDC098) // (TC5) Register B
+#define AT91C_TC5_RA    (AT91_CAST(AT91_REG *) 	0xFFFDC094) // (TC5) Register A
+#define AT91C_TC5_CV    (AT91_CAST(AT91_REG *) 	0xFFFDC090) // (TC5) Counter Value
+#define AT91C_TC5_CCR   (AT91_CAST(AT91_REG *) 	0xFFFDC080) // (TC5) Channel Control Register
+#define AT91C_TC5_SR    (AT91_CAST(AT91_REG *) 	0xFFFDC0A0) // (TC5) Status Register
+#define AT91C_TC5_IER   (AT91_CAST(AT91_REG *) 	0xFFFDC0A4) // (TC5) Interrupt Enable Register
+#define AT91C_TC5_IDR   (AT91_CAST(AT91_REG *) 	0xFFFDC0A8) // (TC5) Interrupt Disable Register
+#define AT91C_TC5_RC    (AT91_CAST(AT91_REG *) 	0xFFFDC09C) // (TC5) Register C
+#define AT91C_TC5_IMR   (AT91_CAST(AT91_REG *) 	0xFFFDC0AC) // (TC5) Interrupt Mask Register
+#define AT91C_TC5_CMR   (AT91_CAST(AT91_REG *) 	0xFFFDC084) // (TC5) Channel Mode Register (Capture Mode / Waveform Mode)
+// ========== Register definition for TCB0 peripheral ========== 
+#define AT91C_TCB0_BMR  (AT91_CAST(AT91_REG *) 	0xFFFA00C4) // (TCB0) TC Block Mode Register
+#define AT91C_TCB0_BCR  (AT91_CAST(AT91_REG *) 	0xFFFA00C0) // (TCB0) TC Block Control Register
+// ========== Register definition for TCB1 peripheral ========== 
+#define AT91C_TCB1_BCR  (AT91_CAST(AT91_REG *) 	0xFFFDC0C0) // (TCB1) TC Block Control Register
+#define AT91C_TCB1_BMR  (AT91_CAST(AT91_REG *) 	0xFFFDC0C4) // (TCB1) TC Block Mode Register
+// ========== Register definition for PDC_MCI peripheral ========== 
+#define AT91C_MCI_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFA8114) // (PDC_MCI) Receive Next Counter Register
+#define AT91C_MCI_TCR   (AT91_CAST(AT91_REG *) 	0xFFFA810C) // (PDC_MCI) Transmit Counter Register
+#define AT91C_MCI_RCR   (AT91_CAST(AT91_REG *) 	0xFFFA8104) // (PDC_MCI) Receive Counter Register
+#define AT91C_MCI_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFA8118) // (PDC_MCI) Transmit Next Pointer Register
+#define AT91C_MCI_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFA8110) // (PDC_MCI) Receive Next Pointer Register
+#define AT91C_MCI_RPR   (AT91_CAST(AT91_REG *) 	0xFFFA8100) // (PDC_MCI) Receive Pointer Register
+#define AT91C_MCI_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFA811C) // (PDC_MCI) Transmit Next Counter Register
+#define AT91C_MCI_TPR   (AT91_CAST(AT91_REG *) 	0xFFFA8108) // (PDC_MCI) Transmit Pointer Register
+#define AT91C_MCI_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFA8124) // (PDC_MCI) PDC Transfer Status Register
+#define AT91C_MCI_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFA8120) // (PDC_MCI) PDC Transfer Control Register
+// ========== Register definition for MCI peripheral ========== 
+#define AT91C_MCI_RDR   (AT91_CAST(AT91_REG *) 	0xFFFA8030) // (MCI) MCI Receive Data Register
+#define AT91C_MCI_CMDR  (AT91_CAST(AT91_REG *) 	0xFFFA8014) // (MCI) MCI Command Register
+#define AT91C_MCI_VR    (AT91_CAST(AT91_REG *) 	0xFFFA80FC) // (MCI) MCI Version Register
+#define AT91C_MCI_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA8048) // (MCI) MCI Interrupt Disable Register
+#define AT91C_MCI_DTOR  (AT91_CAST(AT91_REG *) 	0xFFFA8008) // (MCI) MCI Data Timeout Register
+#define AT91C_MCI_TDR   (AT91_CAST(AT91_REG *) 	0xFFFA8034) // (MCI) MCI Transmit Data Register
+#define AT91C_MCI_IER   (AT91_CAST(AT91_REG *) 	0xFFFA8044) // (MCI) MCI Interrupt Enable Register
+#define AT91C_MCI_BLKR  (AT91_CAST(AT91_REG *) 	0xFFFA8018) // (MCI) MCI Block Register
+#define AT91C_MCI_MR    (AT91_CAST(AT91_REG *) 	0xFFFA8004) // (MCI) MCI Mode Register
+#define AT91C_MCI_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA804C) // (MCI) MCI Interrupt Mask Register
+#define AT91C_MCI_CR    (AT91_CAST(AT91_REG *) 	0xFFFA8000) // (MCI) MCI Control Register
+#define AT91C_MCI_ARGR  (AT91_CAST(AT91_REG *) 	0xFFFA8010) // (MCI) MCI Argument Register
+#define AT91C_MCI_SDCR  (AT91_CAST(AT91_REG *) 	0xFFFA800C) // (MCI) MCI SD Card Register
+#define AT91C_MCI_SR    (AT91_CAST(AT91_REG *) 	0xFFFA8040) // (MCI) MCI Status Register
+#define AT91C_MCI_RSPR  (AT91_CAST(AT91_REG *) 	0xFFFA8020) // (MCI) MCI Response Register
+// ========== Register definition for PDC_TWI0 peripheral ========== 
+#define AT91C_TWI0_PTSR (AT91_CAST(AT91_REG *) 	0xFFFAC124) // (PDC_TWI0) PDC Transfer Status Register
+#define AT91C_TWI0_RPR  (AT91_CAST(AT91_REG *) 	0xFFFAC100) // (PDC_TWI0) Receive Pointer Register
+#define AT91C_TWI0_RNCR (AT91_CAST(AT91_REG *) 	0xFFFAC114) // (PDC_TWI0) Receive Next Counter Register
+#define AT91C_TWI0_RCR  (AT91_CAST(AT91_REG *) 	0xFFFAC104) // (PDC_TWI0) Receive Counter Register
+#define AT91C_TWI0_PTCR (AT91_CAST(AT91_REG *) 	0xFFFAC120) // (PDC_TWI0) PDC Transfer Control Register
+#define AT91C_TWI0_TPR  (AT91_CAST(AT91_REG *) 	0xFFFAC108) // (PDC_TWI0) Transmit Pointer Register
+#define AT91C_TWI0_RNPR (AT91_CAST(AT91_REG *) 	0xFFFAC110) // (PDC_TWI0) Receive Next Pointer Register
+#define AT91C_TWI0_TNPR (AT91_CAST(AT91_REG *) 	0xFFFAC118) // (PDC_TWI0) Transmit Next Pointer Register
+#define AT91C_TWI0_TCR  (AT91_CAST(AT91_REG *) 	0xFFFAC10C) // (PDC_TWI0) Transmit Counter Register
+#define AT91C_TWI0_TNCR (AT91_CAST(AT91_REG *) 	0xFFFAC11C) // (PDC_TWI0) Transmit Next Counter Register
+// ========== Register definition for TWI0 peripheral ========== 
+#define AT91C_TWI0_THR  (AT91_CAST(AT91_REG *) 	0xFFFAC034) // (TWI0) Transmit Holding Register
+#define AT91C_TWI0_IDR  (AT91_CAST(AT91_REG *) 	0xFFFAC028) // (TWI0) Interrupt Disable Register
+#define AT91C_TWI0_SMR  (AT91_CAST(AT91_REG *) 	0xFFFAC008) // (TWI0) Slave Mode Register
+#define AT91C_TWI0_CWGR (AT91_CAST(AT91_REG *) 	0xFFFAC010) // (TWI0) Clock Waveform Generator Register
+#define AT91C_TWI0_IADR (AT91_CAST(AT91_REG *) 	0xFFFAC00C) // (TWI0) Internal Address Register
+#define AT91C_TWI0_RHR  (AT91_CAST(AT91_REG *) 	0xFFFAC030) // (TWI0) Receive Holding Register
+#define AT91C_TWI0_IER  (AT91_CAST(AT91_REG *) 	0xFFFAC024) // (TWI0) Interrupt Enable Register
+#define AT91C_TWI0_MMR  (AT91_CAST(AT91_REG *) 	0xFFFAC004) // (TWI0) Master Mode Register
+#define AT91C_TWI0_SR   (AT91_CAST(AT91_REG *) 	0xFFFAC020) // (TWI0) Status Register
+#define AT91C_TWI0_IMR  (AT91_CAST(AT91_REG *) 	0xFFFAC02C) // (TWI0) Interrupt Mask Register
+#define AT91C_TWI0_CR   (AT91_CAST(AT91_REG *) 	0xFFFAC000) // (TWI0) Control Register
+// ========== Register definition for PDC_TWI1 peripheral ========== 
+#define AT91C_TWI1_PTSR (AT91_CAST(AT91_REG *) 	0xFFFD8124) // (PDC_TWI1) PDC Transfer Status Register
+#define AT91C_TWI1_PTCR (AT91_CAST(AT91_REG *) 	0xFFFD8120) // (PDC_TWI1) PDC Transfer Control Register
+#define AT91C_TWI1_TNPR (AT91_CAST(AT91_REG *) 	0xFFFD8118) // (PDC_TWI1) Transmit Next Pointer Register
+#define AT91C_TWI1_TNCR (AT91_CAST(AT91_REG *) 	0xFFFD811C) // (PDC_TWI1) Transmit Next Counter Register
+#define AT91C_TWI1_RNPR (AT91_CAST(AT91_REG *) 	0xFFFD8110) // (PDC_TWI1) Receive Next Pointer Register
+#define AT91C_TWI1_RNCR (AT91_CAST(AT91_REG *) 	0xFFFD8114) // (PDC_TWI1) Receive Next Counter Register
+#define AT91C_TWI1_RPR  (AT91_CAST(AT91_REG *) 	0xFFFD8100) // (PDC_TWI1) Receive Pointer Register
+#define AT91C_TWI1_TCR  (AT91_CAST(AT91_REG *) 	0xFFFD810C) // (PDC_TWI1) Transmit Counter Register
+#define AT91C_TWI1_TPR  (AT91_CAST(AT91_REG *) 	0xFFFD8108) // (PDC_TWI1) Transmit Pointer Register
+#define AT91C_TWI1_RCR  (AT91_CAST(AT91_REG *) 	0xFFFD8104) // (PDC_TWI1) Receive Counter Register
+// ========== Register definition for TWI1 peripheral ========== 
+#define AT91C_TWI1_RHR  (AT91_CAST(AT91_REG *) 	0xFFFD8030) // (TWI1) Receive Holding Register
+#define AT91C_TWI1_IER  (AT91_CAST(AT91_REG *) 	0xFFFD8024) // (TWI1) Interrupt Enable Register
+#define AT91C_TWI1_CWGR (AT91_CAST(AT91_REG *) 	0xFFFD8010) // (TWI1) Clock Waveform Generator Register
+#define AT91C_TWI1_MMR  (AT91_CAST(AT91_REG *) 	0xFFFD8004) // (TWI1) Master Mode Register
+#define AT91C_TWI1_IADR (AT91_CAST(AT91_REG *) 	0xFFFD800C) // (TWI1) Internal Address Register
+#define AT91C_TWI1_THR  (AT91_CAST(AT91_REG *) 	0xFFFD8034) // (TWI1) Transmit Holding Register
+#define AT91C_TWI1_IMR  (AT91_CAST(AT91_REG *) 	0xFFFD802C) // (TWI1) Interrupt Mask Register
+#define AT91C_TWI1_SR   (AT91_CAST(AT91_REG *) 	0xFFFD8020) // (TWI1) Status Register
+#define AT91C_TWI1_IDR  (AT91_CAST(AT91_REG *) 	0xFFFD8028) // (TWI1) Interrupt Disable Register
+#define AT91C_TWI1_CR   (AT91_CAST(AT91_REG *) 	0xFFFD8000) // (TWI1) Control Register
+#define AT91C_TWI1_SMR  (AT91_CAST(AT91_REG *) 	0xFFFD8008) // (TWI1) Slave Mode Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_TCR   (AT91_CAST(AT91_REG *) 	0xFFFB010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFB0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFB0114) // (PDC_US0) Receive Next Counter Register
+#define AT91C_US0_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFB0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFB011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFB0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_RCR   (AT91_CAST(AT91_REG *) 	0xFFFB0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_TPR   (AT91_CAST(AT91_REG *) 	0xFFFB0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFB0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RPR   (AT91_CAST(AT91_REG *) 	0xFFFB0100) // (PDC_US0) Receive Pointer Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_RHR   (AT91_CAST(AT91_REG *) 	0xFFFB0018) // (US0) Receiver Holding Register
+#define AT91C_US0_NER   (AT91_CAST(AT91_REG *) 	0xFFFB0044) // (US0) Nb Errors Register
+#define AT91C_US0_IER   (AT91_CAST(AT91_REG *) 	0xFFFB0008) // (US0) Interrupt Enable Register
+#define AT91C_US0_CR    (AT91_CAST(AT91_REG *) 	0xFFFB0000) // (US0) Control Register
+#define AT91C_US0_THR   (AT91_CAST(AT91_REG *) 	0xFFFB001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_CSR   (AT91_CAST(AT91_REG *) 	0xFFFB0014) // (US0) Channel Status Register
+#define AT91C_US0_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFB0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFB0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFB0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_MR    (AT91_CAST(AT91_REG *) 	0xFFFB0004) // (US0) Mode Register
+#define AT91C_US0_IF    (AT91_CAST(AT91_REG *) 	0xFFFB004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFB0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB0010) // (US0) Interrupt Mask Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFB4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_RCR   (AT91_CAST(AT91_REG *) 	0xFFFB4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RPR   (AT91_CAST(AT91_REG *) 	0xFFFB4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFB4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TPR   (AT91_CAST(AT91_REG *) 	0xFFFB4108) // (PDC_US1) Transmit Pointer Register
+#define AT91C_US1_TCR   (AT91_CAST(AT91_REG *) 	0xFFFB410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFB4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFB411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFB4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFB4118) // (PDC_US1) Transmit Next Pointer Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_THR   (AT91_CAST(AT91_REG *) 	0xFFFB401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFB4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFB4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_MR    (AT91_CAST(AT91_REG *) 	0xFFFB4004) // (US1) Mode Register
+#define AT91C_US1_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFB4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CR    (AT91_CAST(AT91_REG *) 	0xFFFB4000) // (US1) Control Register
+#define AT91C_US1_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFB4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_RHR   (AT91_CAST(AT91_REG *) 	0xFFFB4018) // (US1) Receiver Holding Register
+#define AT91C_US1_IER   (AT91_CAST(AT91_REG *) 	0xFFFB4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_CSR   (AT91_CAST(AT91_REG *) 	0xFFFB4014) // (US1) Channel Status Register
+#define AT91C_US1_IF    (AT91_CAST(AT91_REG *) 	0xFFFB404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER   (AT91_CAST(AT91_REG *) 	0xFFFB4044) // (US1) Nb Errors Register
+// ========== Register definition for PDC_US2 peripheral ========== 
+#define AT91C_US2_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFB811C) // (PDC_US2) Transmit Next Counter Register
+#define AT91C_US2_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFB8114) // (PDC_US2) Receive Next Counter Register
+#define AT91C_US2_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFB8118) // (PDC_US2) Transmit Next Pointer Register
+#define AT91C_US2_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFB8120) // (PDC_US2) PDC Transfer Control Register
+#define AT91C_US2_TCR   (AT91_CAST(AT91_REG *) 	0xFFFB810C) // (PDC_US2) Transmit Counter Register
+#define AT91C_US2_RPR   (AT91_CAST(AT91_REG *) 	0xFFFB8100) // (PDC_US2) Receive Pointer Register
+#define AT91C_US2_TPR   (AT91_CAST(AT91_REG *) 	0xFFFB8108) // (PDC_US2) Transmit Pointer Register
+#define AT91C_US2_RCR   (AT91_CAST(AT91_REG *) 	0xFFFB8104) // (PDC_US2) Receive Counter Register
+#define AT91C_US2_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFB8124) // (PDC_US2) PDC Transfer Status Register
+#define AT91C_US2_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFB8110) // (PDC_US2) Receive Next Pointer Register
+// ========== Register definition for US2 peripheral ========== 
+#define AT91C_US2_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFB8024) // (US2) Receiver Time-out Register
+#define AT91C_US2_CSR   (AT91_CAST(AT91_REG *) 	0xFFFB8014) // (US2) Channel Status Register
+#define AT91C_US2_CR    (AT91_CAST(AT91_REG *) 	0xFFFB8000) // (US2) Control Register
+#define AT91C_US2_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFB8020) // (US2) Baud Rate Generator Register
+#define AT91C_US2_NER   (AT91_CAST(AT91_REG *) 	0xFFFB8044) // (US2) Nb Errors Register
+#define AT91C_US2_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFB8040) // (US2) FI_DI_Ratio Register
+#define AT91C_US2_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFB8028) // (US2) Transmitter Time-guard Register
+#define AT91C_US2_RHR   (AT91_CAST(AT91_REG *) 	0xFFFB8018) // (US2) Receiver Holding Register
+#define AT91C_US2_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB800C) // (US2) Interrupt Disable Register
+#define AT91C_US2_THR   (AT91_CAST(AT91_REG *) 	0xFFFB801C) // (US2) Transmitter Holding Register
+#define AT91C_US2_MR    (AT91_CAST(AT91_REG *) 	0xFFFB8004) // (US2) Mode Register
+#define AT91C_US2_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB8010) // (US2) Interrupt Mask Register
+#define AT91C_US2_IF    (AT91_CAST(AT91_REG *) 	0xFFFB804C) // (US2) IRDA_FILTER Register
+#define AT91C_US2_IER   (AT91_CAST(AT91_REG *) 	0xFFFB8008) // (US2) Interrupt Enable Register
+// ========== Register definition for PDC_US3 peripheral ========== 
+#define AT91C_US3_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFD0110) // (PDC_US3) Receive Next Pointer Register
+#define AT91C_US3_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFD0114) // (PDC_US3) Receive Next Counter Register
+#define AT91C_US3_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFD0124) // (PDC_US3) PDC Transfer Status Register
+#define AT91C_US3_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFD0120) // (PDC_US3) PDC Transfer Control Register
+#define AT91C_US3_TCR   (AT91_CAST(AT91_REG *) 	0xFFFD010C) // (PDC_US3) Transmit Counter Register
+#define AT91C_US3_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFD0118) // (PDC_US3) Transmit Next Pointer Register
+#define AT91C_US3_RCR   (AT91_CAST(AT91_REG *) 	0xFFFD0104) // (PDC_US3) Receive Counter Register
+#define AT91C_US3_TPR   (AT91_CAST(AT91_REG *) 	0xFFFD0108) // (PDC_US3) Transmit Pointer Register
+#define AT91C_US3_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFD011C) // (PDC_US3) Transmit Next Counter Register
+#define AT91C_US3_RPR   (AT91_CAST(AT91_REG *) 	0xFFFD0100) // (PDC_US3) Receive Pointer Register
+// ========== Register definition for US3 peripheral ========== 
+#define AT91C_US3_NER   (AT91_CAST(AT91_REG *) 	0xFFFD0044) // (US3) Nb Errors Register
+#define AT91C_US3_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFD0024) // (US3) Receiver Time-out Register
+#define AT91C_US3_IDR   (AT91_CAST(AT91_REG *) 	0xFFFD000C) // (US3) Interrupt Disable Register
+#define AT91C_US3_MR    (AT91_CAST(AT91_REG *) 	0xFFFD0004) // (US3) Mode Register
+#define AT91C_US3_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFD0040) // (US3) FI_DI_Ratio Register
+#define AT91C_US3_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFD0020) // (US3) Baud Rate Generator Register
+#define AT91C_US3_THR   (AT91_CAST(AT91_REG *) 	0xFFFD001C) // (US3) Transmitter Holding Register
+#define AT91C_US3_CR    (AT91_CAST(AT91_REG *) 	0xFFFD0000) // (US3) Control Register
+#define AT91C_US3_IF    (AT91_CAST(AT91_REG *) 	0xFFFD004C) // (US3) IRDA_FILTER Register
+#define AT91C_US3_IER   (AT91_CAST(AT91_REG *) 	0xFFFD0008) // (US3) Interrupt Enable Register
+#define AT91C_US3_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFD0028) // (US3) Transmitter Time-guard Register
+#define AT91C_US3_RHR   (AT91_CAST(AT91_REG *) 	0xFFFD0018) // (US3) Receiver Holding Register
+#define AT91C_US3_IMR   (AT91_CAST(AT91_REG *) 	0xFFFD0010) // (US3) Interrupt Mask Register
+#define AT91C_US3_CSR   (AT91_CAST(AT91_REG *) 	0xFFFD0014) // (US3) Channel Status Register
+// ========== Register definition for PDC_US4 peripheral ========== 
+#define AT91C_US4_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFD411C) // (PDC_US4) Transmit Next Counter Register
+#define AT91C_US4_RPR   (AT91_CAST(AT91_REG *) 	0xFFFD4100) // (PDC_US4) Receive Pointer Register
+#define AT91C_US4_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFD4114) // (PDC_US4) Receive Next Counter Register
+#define AT91C_US4_TPR   (AT91_CAST(AT91_REG *) 	0xFFFD4108) // (PDC_US4) Transmit Pointer Register
+#define AT91C_US4_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFD4120) // (PDC_US4) PDC Transfer Control Register
+#define AT91C_US4_TCR   (AT91_CAST(AT91_REG *) 	0xFFFD410C) // (PDC_US4) Transmit Counter Register
+#define AT91C_US4_RCR   (AT91_CAST(AT91_REG *) 	0xFFFD4104) // (PDC_US4) Receive Counter Register
+#define AT91C_US4_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFD4110) // (PDC_US4) Receive Next Pointer Register
+#define AT91C_US4_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFD4118) // (PDC_US4) Transmit Next Pointer Register
+#define AT91C_US4_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFD4124) // (PDC_US4) PDC Transfer Status Register
+// ========== Register definition for US4 peripheral ========== 
+#define AT91C_US4_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFD4020) // (US4) Baud Rate Generator Register
+#define AT91C_US4_THR   (AT91_CAST(AT91_REG *) 	0xFFFD401C) // (US4) Transmitter Holding Register
+#define AT91C_US4_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFD4024) // (US4) Receiver Time-out Register
+#define AT91C_US4_IMR   (AT91_CAST(AT91_REG *) 	0xFFFD4010) // (US4) Interrupt Mask Register
+#define AT91C_US4_NER   (AT91_CAST(AT91_REG *) 	0xFFFD4044) // (US4) Nb Errors Register
+#define AT91C_US4_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFD4028) // (US4) Transmitter Time-guard Register
+#define AT91C_US4_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFD4040) // (US4) FI_DI_Ratio Register
+#define AT91C_US4_MR    (AT91_CAST(AT91_REG *) 	0xFFFD4004) // (US4) Mode Register
+#define AT91C_US4_IER   (AT91_CAST(AT91_REG *) 	0xFFFD4008) // (US4) Interrupt Enable Register
+#define AT91C_US4_RHR   (AT91_CAST(AT91_REG *) 	0xFFFD4018) // (US4) Receiver Holding Register
+#define AT91C_US4_CR    (AT91_CAST(AT91_REG *) 	0xFFFD4000) // (US4) Control Register
+#define AT91C_US4_IF    (AT91_CAST(AT91_REG *) 	0xFFFD404C) // (US4) IRDA_FILTER Register
+#define AT91C_US4_IDR   (AT91_CAST(AT91_REG *) 	0xFFFD400C) // (US4) Interrupt Disable Register
+#define AT91C_US4_CSR   (AT91_CAST(AT91_REG *) 	0xFFFD4014) // (US4) Channel Status Register
+// ========== Register definition for PDC_SSC0 peripheral ========== 
+#define AT91C_SSC0_TNPR (AT91_CAST(AT91_REG *) 	0xFFFBC118) // (PDC_SSC0) Transmit Next Pointer Register
+#define AT91C_SSC0_TCR  (AT91_CAST(AT91_REG *) 	0xFFFBC10C) // (PDC_SSC0) Transmit Counter Register
+#define AT91C_SSC0_RNCR (AT91_CAST(AT91_REG *) 	0xFFFBC114) // (PDC_SSC0) Receive Next Counter Register
+#define AT91C_SSC0_RPR  (AT91_CAST(AT91_REG *) 	0xFFFBC100) // (PDC_SSC0) Receive Pointer Register
+#define AT91C_SSC0_TPR  (AT91_CAST(AT91_REG *) 	0xFFFBC108) // (PDC_SSC0) Transmit Pointer Register
+#define AT91C_SSC0_RCR  (AT91_CAST(AT91_REG *) 	0xFFFBC104) // (PDC_SSC0) Receive Counter Register
+#define AT91C_SSC0_RNPR (AT91_CAST(AT91_REG *) 	0xFFFBC110) // (PDC_SSC0) Receive Next Pointer Register
+#define AT91C_SSC0_PTCR (AT91_CAST(AT91_REG *) 	0xFFFBC120) // (PDC_SSC0) PDC Transfer Control Register
+#define AT91C_SSC0_TNCR (AT91_CAST(AT91_REG *) 	0xFFFBC11C) // (PDC_SSC0) Transmit Next Counter Register
+#define AT91C_SSC0_PTSR (AT91_CAST(AT91_REG *) 	0xFFFBC124) // (PDC_SSC0) PDC Transfer Status Register
+// ========== Register definition for SSC0 peripheral ========== 
+#define AT91C_SSC0_IMR  (AT91_CAST(AT91_REG *) 	0xFFFBC04C) // (SSC0) Interrupt Mask Register
+#define AT91C_SSC0_RFMR (AT91_CAST(AT91_REG *) 	0xFFFBC014) // (SSC0) Receive Frame Mode Register
+#define AT91C_SSC0_CR   (AT91_CAST(AT91_REG *) 	0xFFFBC000) // (SSC0) Control Register
+#define AT91C_SSC0_TFMR (AT91_CAST(AT91_REG *) 	0xFFFBC01C) // (SSC0) Transmit Frame Mode Register
+#define AT91C_SSC0_CMR  (AT91_CAST(AT91_REG *) 	0xFFFBC004) // (SSC0) Clock Mode Register
+#define AT91C_SSC0_IER  (AT91_CAST(AT91_REG *) 	0xFFFBC044) // (SSC0) Interrupt Enable Register
+#define AT91C_SSC0_RHR  (AT91_CAST(AT91_REG *) 	0xFFFBC020) // (SSC0) Receive Holding Register
+#define AT91C_SSC0_RCMR (AT91_CAST(AT91_REG *) 	0xFFFBC010) // (SSC0) Receive Clock ModeRegister
+#define AT91C_SSC0_SR   (AT91_CAST(AT91_REG *) 	0xFFFBC040) // (SSC0) Status Register
+#define AT91C_SSC0_RSHR (AT91_CAST(AT91_REG *) 	0xFFFBC030) // (SSC0) Receive Sync Holding Register
+#define AT91C_SSC0_THR  (AT91_CAST(AT91_REG *) 	0xFFFBC024) // (SSC0) Transmit Holding Register
+#define AT91C_SSC0_TCMR (AT91_CAST(AT91_REG *) 	0xFFFBC018) // (SSC0) Transmit Clock Mode Register
+#define AT91C_SSC0_IDR  (AT91_CAST(AT91_REG *) 	0xFFFBC048) // (SSC0) Interrupt Disable Register
+#define AT91C_SSC0_TSHR (AT91_CAST(AT91_REG *) 	0xFFFBC034) // (SSC0) Transmit Sync Holding Register
+// ========== Register definition for PDC_SPI0 peripheral ========== 
+#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 	0xFFFC8120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TCR  (AT91_CAST(AT91_REG *) 	0xFFFC810C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RPR  (AT91_CAST(AT91_REG *) 	0xFFFC8100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TPR  (AT91_CAST(AT91_REG *) 	0xFFFC8108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 	0xFFFC8124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 	0xFFFC8114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 	0xFFFC8118) // (PDC_SPI0) Transmit Next Pointer Register
+#define AT91C_SPI0_RCR  (AT91_CAST(AT91_REG *) 	0xFFFC8104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 	0xFFFC8110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 	0xFFFC811C) // (PDC_SPI0) Transmit Next Counter Register
+// ========== Register definition for SPI0 peripheral ========== 
+#define AT91C_SPI0_IDR  (AT91_CAST(AT91_REG *) 	0xFFFC8018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_TDR  (AT91_CAST(AT91_REG *) 	0xFFFC800C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_SR   (AT91_CAST(AT91_REG *) 	0xFFFC8010) // (SPI0) Status Register
+#define AT91C_SPI0_CR   (AT91_CAST(AT91_REG *) 	0xFFFC8000) // (SPI0) Control Register
+#define AT91C_SPI0_CSR  (AT91_CAST(AT91_REG *) 	0xFFFC8030) // (SPI0) Chip Select Register
+#define AT91C_SPI0_RDR  (AT91_CAST(AT91_REG *) 	0xFFFC8008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_MR   (AT91_CAST(AT91_REG *) 	0xFFFC8004) // (SPI0) Mode Register
+#define AT91C_SPI0_IER  (AT91_CAST(AT91_REG *) 	0xFFFC8014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_IMR  (AT91_CAST(AT91_REG *) 	0xFFFC801C) // (SPI0) Interrupt Mask Register
+// ========== Register definition for PDC_SPI1 peripheral ========== 
+#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 	0xFFFCC120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 	0xFFFCC110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RCR  (AT91_CAST(AT91_REG *) 	0xFFFCC104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_TPR  (AT91_CAST(AT91_REG *) 	0xFFFCC108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 	0xFFFCC124) // (PDC_SPI1) PDC Transfer Status Register
+#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 	0xFFFCC11C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_RPR  (AT91_CAST(AT91_REG *) 	0xFFFCC100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TCR  (AT91_CAST(AT91_REG *) 	0xFFFCC10C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 	0xFFFCC114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 	0xFFFCC118) // (PDC_SPI1) Transmit Next Pointer Register
+// ========== Register definition for SPI1 peripheral ========== 
+#define AT91C_SPI1_IER  (AT91_CAST(AT91_REG *) 	0xFFFCC014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_RDR  (AT91_CAST(AT91_REG *) 	0xFFFCC008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_SR   (AT91_CAST(AT91_REG *) 	0xFFFCC010) // (SPI1) Status Register
+#define AT91C_SPI1_IMR  (AT91_CAST(AT91_REG *) 	0xFFFCC01C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_TDR  (AT91_CAST(AT91_REG *) 	0xFFFCC00C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_IDR  (AT91_CAST(AT91_REG *) 	0xFFFCC018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_CSR  (AT91_CAST(AT91_REG *) 	0xFFFCC030) // (SPI1) Chip Select Register
+#define AT91C_SPI1_CR   (AT91_CAST(AT91_REG *) 	0xFFFCC000) // (SPI1) Control Register
+#define AT91C_SPI1_MR   (AT91_CAST(AT91_REG *) 	0xFFFCC004) // (SPI1) Mode Register
+// ========== Register definition for PDC_ADC peripheral ========== 
+#define AT91C_ADC_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFE0120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TPR   (AT91_CAST(AT91_REG *) 	0xFFFE0108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_TCR   (AT91_CAST(AT91_REG *) 	0xFFFE010C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_RCR   (AT91_CAST(AT91_REG *) 	0xFFFE0104) // (PDC_ADC) Receive Counter Register
+#define AT91C_ADC_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFE0124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFE0110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RPR   (AT91_CAST(AT91_REG *) 	0xFFFE0100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFE011C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFE0114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFE0118) // (PDC_ADC) Transmit Next Pointer Register
+// ========== Register definition for ADC peripheral ========== 
+#define AT91C_ADC_CHDR  (AT91_CAST(AT91_REG *) 	0xFFFE0014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_CDR3  (AT91_CAST(AT91_REG *) 	0xFFFE003C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CR    (AT91_CAST(AT91_REG *) 	0xFFFE0000) // (ADC) ADC Control Register
+#define AT91C_ADC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFE002C) // (ADC) ADC Interrupt Mask Register
+#define AT91C_ADC_CDR2  (AT91_CAST(AT91_REG *) 	0xFFFE0038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_SR    (AT91_CAST(AT91_REG *) 	0xFFFE001C) // (ADC) ADC Status Register
+#define AT91C_ADC_IER   (AT91_CAST(AT91_REG *) 	0xFFFE0024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CDR7  (AT91_CAST(AT91_REG *) 	0xFFFE004C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR0  (AT91_CAST(AT91_REG *) 	0xFFFE0030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5  (AT91_CAST(AT91_REG *) 	0xFFFE0044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CDR4  (AT91_CAST(AT91_REG *) 	0xFFFE0040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CHER  (AT91_CAST(AT91_REG *) 	0xFFFE0010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR  (AT91_CAST(AT91_REG *) 	0xFFFE0018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR    (AT91_CAST(AT91_REG *) 	0xFFFE0004) // (ADC) ADC Mode Register
+#define AT91C_ADC_CDR6  (AT91_CAST(AT91_REG *) 	0xFFFE0048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_LCDR  (AT91_CAST(AT91_REG *) 	0xFFFE0020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_CDR1  (AT91_CAST(AT91_REG *) 	0xFFFE0034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFE0028) // (ADC) ADC Interrupt Disable Register
+// ========== Register definition for EMACB peripheral ========== 
+#define AT91C_EMACB_USRIO (AT91_CAST(AT91_REG *) 	0xFFFC40C0) // (EMACB) USER Input/Output Register
+#define AT91C_EMACB_RSE (AT91_CAST(AT91_REG *) 	0xFFFC4074) // (EMACB) Receive Symbol Errors Register
+#define AT91C_EMACB_SCF (AT91_CAST(AT91_REG *) 	0xFFFC4044) // (EMACB) Single Collision Frame Register
+#define AT91C_EMACB_STE (AT91_CAST(AT91_REG *) 	0xFFFC4084) // (EMACB) SQE Test Error Register
+#define AT91C_EMACB_SA1H (AT91_CAST(AT91_REG *) 	0xFFFC409C) // (EMACB) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMACB_ROV (AT91_CAST(AT91_REG *) 	0xFFFC4070) // (EMACB) Receive Overrun Errors Register
+#define AT91C_EMACB_TBQP (AT91_CAST(AT91_REG *) 	0xFFFC401C) // (EMACB) Transmit Buffer Queue Pointer
+#define AT91C_EMACB_IMR (AT91_CAST(AT91_REG *) 	0xFFFC4030) // (EMACB) Interrupt Mask Register
+#define AT91C_EMACB_IER (AT91_CAST(AT91_REG *) 	0xFFFC4028) // (EMACB) Interrupt Enable Register
+#define AT91C_EMACB_REV (AT91_CAST(AT91_REG *) 	0xFFFC40FC) // (EMACB) Revision Register
+#define AT91C_EMACB_SA3L (AT91_CAST(AT91_REG *) 	0xFFFC40A8) // (EMACB) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMACB_ELE (AT91_CAST(AT91_REG *) 	0xFFFC4078) // (EMACB) Excessive Length Errors Register
+#define AT91C_EMACB_HRT (AT91_CAST(AT91_REG *) 	0xFFFC4094) // (EMACB) Hash Address Top[63:32]
+#define AT91C_EMACB_SA2L (AT91_CAST(AT91_REG *) 	0xFFFC40A0) // (EMACB) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMACB_RRE (AT91_CAST(AT91_REG *) 	0xFFFC406C) // (EMACB) Receive Ressource Error Register
+#define AT91C_EMACB_FRO (AT91_CAST(AT91_REG *) 	0xFFFC404C) // (EMACB) Frames Received OK Register
+#define AT91C_EMACB_TPQ (AT91_CAST(AT91_REG *) 	0xFFFC40BC) // (EMACB) Transmit Pause Quantum Register
+#define AT91C_EMACB_ISR (AT91_CAST(AT91_REG *) 	0xFFFC4024) // (EMACB) Interrupt Status Register
+#define AT91C_EMACB_TSR (AT91_CAST(AT91_REG *) 	0xFFFC4014) // (EMACB) Transmit Status Register
+#define AT91C_EMACB_RLE (AT91_CAST(AT91_REG *) 	0xFFFC4088) // (EMACB) Receive Length Field Mismatch Register
+#define AT91C_EMACB_USF (AT91_CAST(AT91_REG *) 	0xFFFC4080) // (EMACB) Undersize Frames Register
+#define AT91C_EMACB_WOL (AT91_CAST(AT91_REG *) 	0xFFFC40C4) // (EMACB) Wake On LAN Register
+#define AT91C_EMACB_TPF (AT91_CAST(AT91_REG *) 	0xFFFC408C) // (EMACB) Transmitted Pause Frames Register
+#define AT91C_EMACB_PTR (AT91_CAST(AT91_REG *) 	0xFFFC4038) // (EMACB) Pause Time Register
+#define AT91C_EMACB_TUND (AT91_CAST(AT91_REG *) 	0xFFFC4064) // (EMACB) Transmit Underrun Error Register
+#define AT91C_EMACB_MAN (AT91_CAST(AT91_REG *) 	0xFFFC4034) // (EMACB) PHY Maintenance Register
+#define AT91C_EMACB_RJA (AT91_CAST(AT91_REG *) 	0xFFFC407C) // (EMACB) Receive Jabbers Register
+#define AT91C_EMACB_SA4L (AT91_CAST(AT91_REG *) 	0xFFFC40B0) // (EMACB) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMACB_CSE (AT91_CAST(AT91_REG *) 	0xFFFC4068) // (EMACB) Carrier Sense Error Register
+#define AT91C_EMACB_HRB (AT91_CAST(AT91_REG *) 	0xFFFC4090) // (EMACB) Hash Address Bottom[31:0]
+#define AT91C_EMACB_ALE (AT91_CAST(AT91_REG *) 	0xFFFC4054) // (EMACB) Alignment Error Register
+#define AT91C_EMACB_SA1L (AT91_CAST(AT91_REG *) 	0xFFFC4098) // (EMACB) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMACB_NCR (AT91_CAST(AT91_REG *) 	0xFFFC4000) // (EMACB) Network Control Register
+#define AT91C_EMACB_FTO (AT91_CAST(AT91_REG *) 	0xFFFC4040) // (EMACB) Frames Transmitted OK Register
+#define AT91C_EMACB_ECOL (AT91_CAST(AT91_REG *) 	0xFFFC4060) // (EMACB) Excessive Collision Register
+#define AT91C_EMACB_DTF (AT91_CAST(AT91_REG *) 	0xFFFC4058) // (EMACB) Deferred Transmission Frame Register
+#define AT91C_EMACB_SA4H (AT91_CAST(AT91_REG *) 	0xFFFC40B4) // (EMACB) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMACB_FCSE (AT91_CAST(AT91_REG *) 	0xFFFC4050) // (EMACB) Frame Check Sequence Error Register
+#define AT91C_EMACB_TID (AT91_CAST(AT91_REG *) 	0xFFFC40B8) // (EMACB) Type ID Checking Register
+#define AT91C_EMACB_PFR (AT91_CAST(AT91_REG *) 	0xFFFC403C) // (EMACB) Pause Frames received Register
+#define AT91C_EMACB_IDR (AT91_CAST(AT91_REG *) 	0xFFFC402C) // (EMACB) Interrupt Disable Register
+#define AT91C_EMACB_SA3H (AT91_CAST(AT91_REG *) 	0xFFFC40AC) // (EMACB) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMACB_NSR (AT91_CAST(AT91_REG *) 	0xFFFC4008) // (EMACB) Network Status Register
+#define AT91C_EMACB_MCF (AT91_CAST(AT91_REG *) 	0xFFFC4048) // (EMACB) Multiple Collision Frame Register
+#define AT91C_EMACB_RBQP (AT91_CAST(AT91_REG *) 	0xFFFC4018) // (EMACB) Receive Buffer Queue Pointer
+#define AT91C_EMACB_RSR (AT91_CAST(AT91_REG *) 	0xFFFC4020) // (EMACB) Receive Status Register
+#define AT91C_EMACB_SA2H (AT91_CAST(AT91_REG *) 	0xFFFC40A4) // (EMACB) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMACB_NCFGR (AT91_CAST(AT91_REG *) 	0xFFFC4004) // (EMACB) Network Configuration Register
+#define AT91C_EMACB_LCOL (AT91_CAST(AT91_REG *) 	0xFFFC405C) // (EMACB) Late Collision Register
+// ========== Register definition for UDP peripheral ========== 
+#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 	0xFFFA4004) // (UDP) Global State Register
+#define AT91C_UDP_FDR   (AT91_CAST(AT91_REG *) 	0xFFFA4050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 	0xFFFA4028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 	0xFFFA4008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM   (AT91_CAST(AT91_REG *) 	0xFFFA4000) // (UDP) Frame Number Register
+#define AT91C_UDP_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA4014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA4018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_CSR   (AT91_CAST(AT91_REG *) 	0xFFFA4030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IER   (AT91_CAST(AT91_REG *) 	0xFFFA4010) // (UDP) Interrupt Enable Register
+#define AT91C_UDP_ICR   (AT91_CAST(AT91_REG *) 	0xFFFA4020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_TXVC  (AT91_CAST(AT91_REG *) 	0xFFFA4074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_ISR   (AT91_CAST(AT91_REG *) 	0xFFFA401C) // (UDP) Interrupt Status Register
+// ========== Register definition for UHP peripheral ========== 
+#define AT91C_UHP_HcInterruptStatus (AT91_CAST(AT91_REG *) 	0x0050000C) // (UHP) Interrupt Status Register
+#define AT91C_UHP_HcCommandStatus (AT91_CAST(AT91_REG *) 	0x00500008) // (UHP) Command & status Register
+#define AT91C_UHP_HcRhStatus (AT91_CAST(AT91_REG *) 	0x00500050) // (UHP) Root Hub Status register
+#define AT91C_UHP_HcInterruptDisable (AT91_CAST(AT91_REG *) 	0x00500014) // (UHP) Interrupt Disable Register
+#define AT91C_UHP_HcPeriodicStart (AT91_CAST(AT91_REG *) 	0x00500040) // (UHP) Periodic Start
+#define AT91C_UHP_HcControlCurrentED (AT91_CAST(AT91_REG *) 	0x00500024) // (UHP) Endpoint Control and Status Register
+#define AT91C_UHP_HcPeriodCurrentED (AT91_CAST(AT91_REG *) 	0x0050001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor
+#define AT91C_UHP_HcBulkHeadED (AT91_CAST(AT91_REG *) 	0x00500028) // (UHP) First endpoint register of the Bulk list
+#define AT91C_UHP_HcRevision (AT91_CAST(AT91_REG *) 	0x00500000) // (UHP) Revision
+#define AT91C_UHP_HcBulkCurrentED (AT91_CAST(AT91_REG *) 	0x0050002C) // (UHP) Current endpoint of the Bulk list
+#define AT91C_UHP_HcRhDescriptorB (AT91_CAST(AT91_REG *) 	0x0050004C) // (UHP) Root Hub characteristics B
+#define AT91C_UHP_HcControlHeadED (AT91_CAST(AT91_REG *) 	0x00500020) // (UHP) First Endpoint Descriptor of the Control list
+#define AT91C_UHP_HcFmRemaining (AT91_CAST(AT91_REG *) 	0x00500038) // (UHP) Bit time remaining in the current Frame
+#define AT91C_UHP_HcHCCA (AT91_CAST(AT91_REG *) 	0x00500018) // (UHP) Pointer to the Host Controller Communication Area
+#define AT91C_UHP_HcLSThreshold (AT91_CAST(AT91_REG *) 	0x00500044) // (UHP) LS Threshold
+#define AT91C_UHP_HcRhPortStatus (AT91_CAST(AT91_REG *) 	0x00500054) // (UHP) Root Hub Port Status Register
+#define AT91C_UHP_HcInterruptEnable (AT91_CAST(AT91_REG *) 	0x00500010) // (UHP) Interrupt Enable Register
+#define AT91C_UHP_HcFmNumber (AT91_CAST(AT91_REG *) 	0x0050003C) // (UHP) Frame number
+#define AT91C_UHP_HcFmInterval (AT91_CAST(AT91_REG *) 	0x00500034) // (UHP) Bit time between 2 consecutive SOFs
+#define AT91C_UHP_HcControl (AT91_CAST(AT91_REG *) 	0x00500004) // (UHP) Operating modes for the Host Controller
+#define AT91C_UHP_HcBulkDoneHead (AT91_CAST(AT91_REG *) 	0x00500030) // (UHP) Last completed transfer descriptor
+#define AT91C_UHP_HcRhDescriptorA (AT91_CAST(AT91_REG *) 	0x00500048) // (UHP) Root Hub characteristics A
+// ========== Register definition for HECC peripheral ========== 
+// ========== Register definition for HISI peripheral ========== 
+#define AT91C_HISI_PSIZE (AT91_CAST(AT91_REG *) 	0xFFFC0020) // (HISI) Preview Size Register
+#define AT91C_HISI_CR1  (AT91_CAST(AT91_REG *) 	0xFFFC0000) // (HISI) Control Register 1
+#define AT91C_HISI_R2YSET1 (AT91_CAST(AT91_REG *) 	0xFFFC003C) // (HISI) Color Space Conversion Register
+#define AT91C_HISI_CDBA (AT91_CAST(AT91_REG *) 	0xFFFC002C) // (HISI) Codec Dma Address Register
+#define AT91C_HISI_IDR  (AT91_CAST(AT91_REG *) 	0xFFFC0010) // (HISI) Interrupt Disable Register
+#define AT91C_HISI_R2YSET2 (AT91_CAST(AT91_REG *) 	0xFFFC0040) // (HISI) Color Space Conversion Register
+#define AT91C_HISI_Y2RSET1 (AT91_CAST(AT91_REG *) 	0xFFFC0034) // (HISI) Color Space Conversion Register
+#define AT91C_HISI_PFBD (AT91_CAST(AT91_REG *) 	0xFFFC0028) // (HISI) Preview Frame Buffer Address Register
+#define AT91C_HISI_CR2  (AT91_CAST(AT91_REG *) 	0xFFFC0004) // (HISI) Control Register 2
+#define AT91C_HISI_Y2RSET0 (AT91_CAST(AT91_REG *) 	0xFFFC0030) // (HISI) Color Space Conversion Register
+#define AT91C_HISI_PDECF (AT91_CAST(AT91_REG *) 	0xFFFC0024) // (HISI) Preview Decimation Factor Register
+#define AT91C_HISI_IMR  (AT91_CAST(AT91_REG *) 	0xFFFC0014) // (HISI) Interrupt Mask Register
+#define AT91C_HISI_IER  (AT91_CAST(AT91_REG *) 	0xFFFC000C) // (HISI) Interrupt Enable Register
+#define AT91C_HISI_R2YSET0 (AT91_CAST(AT91_REG *) 	0xFFFC0038) // (HISI) Color Space Conversion Register
+#define AT91C_HISI_SR   (AT91_CAST(AT91_REG *) 	0xFFFC0008) // (HISI) Status Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM9XE256
+// *****************************************************************************
+#define AT91C_PIO_PA0        (1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_SPI0_MISO (AT91C_PIO_PA0) //  SPI 0 Master In Slave
+#define AT91C_PA0_MCDB0    (AT91C_PIO_PA0) //  Multimedia Card B Data 0
+#define AT91C_PIO_PA1        (1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_SPI0_MOSI (AT91C_PIO_PA1) //  SPI 0 Master Out Slave
+#define AT91C_PA1_MCCDB    (AT91C_PIO_PA1) //  Multimedia Card B Command
+#define AT91C_PIO_PA10       (1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_MCDA2    (AT91C_PIO_PA10) //  Multimedia Card A Data 2
+#define AT91C_PA10_ETX2_0   (AT91C_PIO_PA10) //  Ethernet MAC Transmit Data 2
+#define AT91C_PIO_PA11       (1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_MCDA3    (AT91C_PIO_PA11) //  Multimedia Card A Data 3
+#define AT91C_PA11_ETX3_0   (AT91C_PIO_PA11) //  Ethernet MAC Transmit Data 3
+#define AT91C_PIO_PA12       (1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_ETX0     (AT91C_PIO_PA12) //  Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PA13       (1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_ETX1     (AT91C_PIO_PA13) //  Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PA14       (1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_ERX0     (AT91C_PIO_PA14) //  Ethernet MAC Receive Data 0
+#define AT91C_PIO_PA15       (1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_ERX1     (AT91C_PIO_PA15) //  Ethernet MAC Receive Data 1
+#define AT91C_PIO_PA16       (1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_ETXEN    (AT91C_PIO_PA16) //  Ethernet MAC Transmit Enable
+#define AT91C_PIO_PA17       (1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_ERXDV    (AT91C_PIO_PA17) //  Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PA18       (1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_ERXER    (AT91C_PIO_PA18) //  Ethernet MAC Receive Error
+#define AT91C_PIO_PA19       (1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_ETXCK    (AT91C_PIO_PA19) //  Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PIO_PA2        (1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_SPI0_SPCK (AT91C_PIO_PA2) //  SPI 0 Serial Clock
+#define AT91C_PIO_PA20       (1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_EMDC     (AT91C_PIO_PA20) //  Ethernet MAC Management Data Clock
+#define AT91C_PIO_PA21       (1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_EMDIO    (AT91C_PIO_PA21) //  Ethernet MAC Management Data Input/Output
+#define AT91C_PIO_PA22       (1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_ADTRG    (AT91C_PIO_PA22) //  ADC Trigger
+#define AT91C_PA22_ETXER    (AT91C_PIO_PA22) //  Ethernet MAC Transmikt Coding Error
+#define AT91C_PIO_PA23       (1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TWD0     (AT91C_PIO_PA23) //  TWI Two-wire Serial Data 0
+#define AT91C_PA23_ETX2_1   (AT91C_PIO_PA23) //  Ethernet MAC Transmit Data 2
+#define AT91C_PIO_PA24       (1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_TWCK0    (AT91C_PIO_PA24) //  TWI Two-wire Serial Clock 0
+#define AT91C_PA24_ETX3_1   (AT91C_PIO_PA24) //  Ethernet MAC Transmit Data 3
+#define AT91C_PIO_PA25       (1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_TCLK0    (AT91C_PIO_PA25) //  Timer Counter 0 external clock input
+#define AT91C_PA25_ERX2     (AT91C_PIO_PA25) //  Ethernet MAC Receive Data 2
+#define AT91C_PIO_PA26       (1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_TIOA0    (AT91C_PIO_PA26) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PA26_ERX3     (AT91C_PIO_PA26) //  Ethernet MAC Receive Data 3
+#define AT91C_PIO_PA27       (1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_TIOA1    (AT91C_PIO_PA27) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PA27_ERXCK    (AT91C_PIO_PA27) //  Ethernet MAC Receive Clock
+#define AT91C_PIO_PA28       (1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_TIOA2    (AT91C_PIO_PA28) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PA28_ECRS     (AT91C_PIO_PA28) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PA29       (1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_SCK1     (AT91C_PIO_PA29) //  USART 1 Serial Clock
+#define AT91C_PA29_ECOL     (AT91C_PIO_PA29) //  Ethernet MAC Collision Detected
+#define AT91C_PIO_PA3        (1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_SPI0_NPCS0 (AT91C_PIO_PA3) //  SPI 0 Peripheral Chip Select 0
+#define AT91C_PA3_MCDB3    (AT91C_PIO_PA3) //  Multimedia Card B Data 3
+#define AT91C_PIO_PA30       (1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_SCK2     (AT91C_PIO_PA30) //  USART 2 Serial Clock
+#define AT91C_PA30_RXD4     (AT91C_PIO_PA30) //  USART 4 Receive Data
+#define AT91C_PIO_PA31       (1 << 31) // Pin Controlled by PA31
+#define AT91C_PA31_SCK0     (AT91C_PIO_PA31) //  USART 0 Serial Clock
+#define AT91C_PA31_TXD4     (AT91C_PIO_PA31) //  USART 4 Transmit Data
+#define AT91C_PIO_PA4        (1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_RTS2     (AT91C_PIO_PA4) //  USART 2 Ready To Send
+#define AT91C_PA4_MCDB2    (AT91C_PIO_PA4) //  Multimedia Card B Data 2
+#define AT91C_PIO_PA5        (1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_CTS2     (AT91C_PIO_PA5) //  USART 2 Clear To Send
+#define AT91C_PA5_MCDB1    (AT91C_PIO_PA5) //  Multimedia Card B Data 1
+#define AT91C_PIO_PA6        (1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_MCDA0    (AT91C_PIO_PA6) //  Multimedia Card A Data 0
+#define AT91C_PIO_PA7        (1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_MCCDA    (AT91C_PIO_PA7) //  Multimedia Card A Command
+#define AT91C_PIO_PA8        (1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_MCCK     (AT91C_PIO_PA8) //  Multimedia Card Clock
+#define AT91C_PIO_PA9        (1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_MCDA1    (AT91C_PIO_PA9) //  Multimedia Card A Data 1
+#define AT91C_PIO_PB0        (1 <<  0) // Pin Controlled by PB0
+#define AT91C_PB0_SPI1_MISO (AT91C_PIO_PB0) //  SPI 1 Master In Slave
+#define AT91C_PB0_TIOA3    (AT91C_PIO_PB0) //  Timer Counter 3 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PB1        (1 <<  1) // Pin Controlled by PB1
+#define AT91C_PB1_SPI1_MOSI (AT91C_PIO_PB1) //  SPI 1 Master Out Slave
+#define AT91C_PB1_TIOB3    (AT91C_PIO_PB1) //  Timer Counter 3 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PB10       (1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_TXD3     (AT91C_PIO_PB10) //  USART 3 Transmit Data
+#define AT91C_PB10_ISI_D8   (AT91C_PIO_PB10) //  Image Sensor Data 8
+#define AT91C_PIO_PB11       (1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_RXD3     (AT91C_PIO_PB11) //  USART 3 Receive Data
+#define AT91C_PB11_ISI_D9   (AT91C_PIO_PB11) //  Image Sensor Data 9
+#define AT91C_PIO_PB12       (1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_TWD1     (AT91C_PIO_PB12) //  TWI Two-wire Serial Data 1
+#define AT91C_PB12_ISI_D10  (AT91C_PIO_PB12) //  Image Sensor Data 10
+#define AT91C_PIO_PB13       (1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_TWCK1    (AT91C_PIO_PB13) //  TWI Two-wire Serial Clock 1
+#define AT91C_PB13_ISI_D11  (AT91C_PIO_PB13) //  Image Sensor Data 11
+#define AT91C_PIO_PB14       (1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_DRXD     (AT91C_PIO_PB14) //  DBGU Debug Receive Data
+#define AT91C_PIO_PB15       (1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_DTXD     (AT91C_PIO_PB15) //  DBGU Debug Transmit Data
+#define AT91C_PIO_PB16       (1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_TK0      (AT91C_PIO_PB16) //  SSC0 Transmit Clock
+#define AT91C_PB16_TCLK3    (AT91C_PIO_PB16) //  Timer Counter 3 external clock input
+#define AT91C_PIO_PB17       (1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_TF0      (AT91C_PIO_PB17) //  SSC0 Transmit Frame Sync
+#define AT91C_PB17_TCLK4    (AT91C_PIO_PB17) //  Timer Counter 4 external clock input
+#define AT91C_PIO_PB18       (1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_TD0      (AT91C_PIO_PB18) //  SSC0 Transmit data
+#define AT91C_PB18_TIOB4    (AT91C_PIO_PB18) //  Timer Counter 4 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PB19       (1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_RD0      (AT91C_PIO_PB19) //  SSC0 Receive Data
+#define AT91C_PB19_TIOB5    (AT91C_PIO_PB19) //  Timer Counter 5 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PB2        (1 <<  2) // Pin Controlled by PB2
+#define AT91C_PB2_SPI1_SPCK (AT91C_PIO_PB2) //  SPI 1 Serial Clock
+#define AT91C_PB2_TIOA4    (AT91C_PIO_PB2) //  Timer Counter 4 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PB20       (1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_RK0      (AT91C_PIO_PB20) //  SSC0 Receive Clock
+#define AT91C_PB20_ISI_D0   (AT91C_PIO_PB20) //  Image Sensor Data 0
+#define AT91C_PIO_PB21       (1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_RF0      (AT91C_PIO_PB21) //  SSC0 Receive Frame Sync
+#define AT91C_PB21_ISI_D1   (AT91C_PIO_PB21) //  Image Sensor Data 1
+#define AT91C_PIO_PB22       (1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_DSR0     (AT91C_PIO_PB22) //  USART 0 Data Set ready
+#define AT91C_PB22_ISI_D2   (AT91C_PIO_PB22) //  Image Sensor Data 2
+#define AT91C_PIO_PB23       (1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_DCD0     (AT91C_PIO_PB23) //  USART 0 Data Carrier Detect
+#define AT91C_PB23_ISI_D3   (AT91C_PIO_PB23) //  Image Sensor Data 3
+#define AT91C_PIO_PB24       (1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_DTR0     (AT91C_PIO_PB24) //  USART 0 Data Terminal ready
+#define AT91C_PB24_ISI_D4   (AT91C_PIO_PB24) //  Image Sensor Data 4
+#define AT91C_PIO_PB25       (1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_RI0      (AT91C_PIO_PB25) //  USART 0 Ring Indicator
+#define AT91C_PB25_ISI_D5   (AT91C_PIO_PB25) //  Image Sensor Data 5
+#define AT91C_PIO_PB26       (1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_RTS0     (AT91C_PIO_PB26) //  USART 0 Ready To Send
+#define AT91C_PB26_ISI_D6   (AT91C_PIO_PB26) //  Image Sensor Data 6
+#define AT91C_PIO_PB27       (1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_CTS0     (AT91C_PIO_PB27) //  USART 0 Clear To Send
+#define AT91C_PB27_ISI_D7   (AT91C_PIO_PB27) //  Image Sensor Data 7
+#define AT91C_PIO_PB28       (1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_RTS1     (AT91C_PIO_PB28) //  USART 1 Ready To Send
+#define AT91C_PB28_ISI_PCK  (AT91C_PIO_PB28) //  Image Sensor Data Clock
+#define AT91C_PIO_PB29       (1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_CTS1     (AT91C_PIO_PB29) //  USART 1 Clear To Send
+#define AT91C_PB29_ISI_VSYNC (AT91C_PIO_PB29) //  Image Sensor Vertical Synchro
+#define AT91C_PIO_PB3        (1 <<  3) // Pin Controlled by PB3
+#define AT91C_PB3_SPI1_NPCS0 (AT91C_PIO_PB3) //  SPI 1 Peripheral Chip Select 0
+#define AT91C_PB3_TIOA5    (AT91C_PIO_PB3) //  Timer Counter 5 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PB30       (1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK0_0   (AT91C_PIO_PB30) //  PMC Programmable Clock Output 0
+#define AT91C_PB30_ISI_HSYNC (AT91C_PIO_PB30) //  Image Sensor Horizontal Synchro
+#define AT91C_PIO_PB31       (1 << 31) // Pin Controlled by PB31
+#define AT91C_PB31_PCK1_0   (AT91C_PIO_PB31) //  PMC Programmable Clock Output 1
+#define AT91C_PB31_ISI_MCK  (AT91C_PIO_PB31) //  Image Sensor Reference Clock
+#define AT91C_PIO_PB4        (1 <<  4) // Pin Controlled by PB4
+#define AT91C_PB4_TXD0     (AT91C_PIO_PB4) //  USART 0 Transmit Data
+#define AT91C_PIO_PB5        (1 <<  5) // Pin Controlled by PB5
+#define AT91C_PB5_RXD0     (AT91C_PIO_PB5) //  USART 0 Receive Data
+#define AT91C_PIO_PB6        (1 <<  6) // Pin Controlled by PB6
+#define AT91C_PB6_TXD1     (AT91C_PIO_PB6) //  USART 1 Transmit Data
+#define AT91C_PB6_TCLK1    (AT91C_PIO_PB6) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PB7        (1 <<  7) // Pin Controlled by PB7
+#define AT91C_PB7_RXD1     (AT91C_PIO_PB7) //  USART 1 Receive Data
+#define AT91C_PB7_TCLK2    (AT91C_PIO_PB7) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PB8        (1 <<  8) // Pin Controlled by PB8
+#define AT91C_PB8_TXD2     (AT91C_PIO_PB8) //  USART 2 Transmit Data
+#define AT91C_PIO_PB9        (1 <<  9) // Pin Controlled by PB9
+#define AT91C_PB9_RXD2     (AT91C_PIO_PB9) //  USART 2 Receive Data
+#define AT91C_PIO_PC0        (1 <<  0) // Pin Controlled by PC0
+#define AT91C_PC0_AD0      (AT91C_PIO_PC0) //  ADC Analog Input 0
+#define AT91C_PC0_SCK3     (AT91C_PIO_PC0) //  USART 3 Serial Clock
+#define AT91C_PIO_PC1        (1 <<  1) // Pin Controlled by PC1
+#define AT91C_PC1_AD1      (AT91C_PIO_PC1) //  ADC Analog Input 1
+#define AT91C_PC1_PCK0     (AT91C_PIO_PC1) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PC10       (1 << 10) // Pin Controlled by PC10
+#define AT91C_PC10_A25_CFRNW (AT91C_PIO_PC10) //  Address Bus[25]
+#define AT91C_PC10_CTS3     (AT91C_PIO_PC10) //  USART 3 Clear To Send
+#define AT91C_PIO_PC11       (1 << 11) // Pin Controlled by PC11
+#define AT91C_PC11_NCS2     (AT91C_PIO_PC11) //  Chip Select Line 2
+#define AT91C_PC11_SPI0_NPCS1 (AT91C_PIO_PC11) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PC12       (1 << 12) // Pin Controlled by PC12
+#define AT91C_PC12_IRQ0     (AT91C_PIO_PC12) //  External Interrupt 0
+#define AT91C_PC12_NCS7     (AT91C_PIO_PC12) //  Chip Select Line 7
+#define AT91C_PIO_PC13       (1 << 13) // Pin Controlled by PC13
+#define AT91C_PC13_FIQ      (AT91C_PIO_PC13) //  AIC Fast Interrupt Input
+#define AT91C_PC13_NCS6     (AT91C_PIO_PC13) //  Chip Select Line 6
+#define AT91C_PIO_PC14       (1 << 14) // Pin Controlled by PC14
+#define AT91C_PC14_NCS3_NANDCS (AT91C_PIO_PC14) //  Chip Select Line 3
+#define AT91C_PC14_IRQ2     (AT91C_PIO_PC14) //  External Interrupt 2
+#define AT91C_PIO_PC15       (1 << 15) // Pin Controlled by PC15
+#define AT91C_PC15_NWAIT    (AT91C_PIO_PC15) //  External Wait Signal
+#define AT91C_PC15_IRQ1     (AT91C_PIO_PC15) //  External Interrupt 1
+#define AT91C_PIO_PC16       (1 << 16) // Pin Controlled by PC16
+#define AT91C_PC16_D16      (AT91C_PIO_PC16) //  Data Bus[16]
+#define AT91C_PC16_SPI0_NPCS2 (AT91C_PIO_PC16) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PC17       (1 << 17) // Pin Controlled by PC17
+#define AT91C_PC17_D17      (AT91C_PIO_PC17) //  Data Bus[17]
+#define AT91C_PC17_SPI0_NPCS3 (AT91C_PIO_PC17) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PC18       (1 << 18) // Pin Controlled by PC18
+#define AT91C_PC18_D18      (AT91C_PIO_PC18) //  Data Bus[18]
+#define AT91C_PC18_SPI1_NPCS1_1 (AT91C_PIO_PC18) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PC19       (1 << 19) // Pin Controlled by PC19
+#define AT91C_PC19_D19      (AT91C_PIO_PC19) //  Data Bus[19]
+#define AT91C_PC19_SPI1_NPCS2_1 (AT91C_PIO_PC19) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PC2        (1 <<  2) // Pin Controlled by PC2
+#define AT91C_PC2_AD2      (AT91C_PIO_PC2) //  ADC Analog Input 2
+#define AT91C_PC2_PCK1     (AT91C_PIO_PC2) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PC20       (1 << 20) // Pin Controlled by PC20
+#define AT91C_PC20_D20      (AT91C_PIO_PC20) //  Data Bus[20]
+#define AT91C_PC20_SPI1_NPCS3_1 (AT91C_PIO_PC20) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PC21       (1 << 21) // Pin Controlled by PC21
+#define AT91C_PC21_D21      (AT91C_PIO_PC21) //  Data Bus[21]
+#define AT91C_PC21_EF100    (AT91C_PIO_PC21) //  Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PIO_PC22       (1 << 22) // Pin Controlled by PC22
+#define AT91C_PC22_D22      (AT91C_PIO_PC22) //  Data Bus[22]
+#define AT91C_PC22_TCLK5    (AT91C_PIO_PC22) //  Timer Counter 5 external clock input
+#define AT91C_PIO_PC23       (1 << 23) // Pin Controlled by PC23
+#define AT91C_PC23_D23      (AT91C_PIO_PC23) //  Data Bus[23]
+#define AT91C_PIO_PC24       (1 << 24) // Pin Controlled by PC24
+#define AT91C_PC24_D24      (AT91C_PIO_PC24) //  Data Bus[24]
+#define AT91C_PIO_PC25       (1 << 25) // Pin Controlled by PC25
+#define AT91C_PC25_D25      (AT91C_PIO_PC25) //  Data Bus[25]
+#define AT91C_PIO_PC26       (1 << 26) // Pin Controlled by PC26
+#define AT91C_PC26_D26      (AT91C_PIO_PC26) //  Data Bus[26]
+#define AT91C_PIO_PC27       (1 << 27) // Pin Controlled by PC27
+#define AT91C_PC27_D27      (AT91C_PIO_PC27) //  Data Bus[27]
+#define AT91C_PIO_PC28       (1 << 28) // Pin Controlled by PC28
+#define AT91C_PC28_D28      (AT91C_PIO_PC28) //  Data Bus[28]
+#define AT91C_PIO_PC29       (1 << 29) // Pin Controlled by PC29
+#define AT91C_PC29_D29      (AT91C_PIO_PC29) //  Data Bus[29]
+#define AT91C_PIO_PC3        (1 <<  3) // Pin Controlled by PC3
+#define AT91C_PC3_AD3      (AT91C_PIO_PC3) //  ADC Analog Input 3
+#define AT91C_PC3_SPI1_NPCS3_0 (AT91C_PIO_PC3) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PC30       (1 << 30) // Pin Controlled by PC30
+#define AT91C_PC30_D30      (AT91C_PIO_PC30) //  Data Bus[30]
+#define AT91C_PIO_PC31       (1 << 31) // Pin Controlled by PC31
+#define AT91C_PC31_D31      (AT91C_PIO_PC31) //  Data Bus[31]
+#define AT91C_PIO_PC4        (1 <<  4) // Pin Controlled by PC4
+#define AT91C_PC4_A23      (AT91C_PIO_PC4) //  Address Bus[23]
+#define AT91C_PC4_SPI1_NPCS2_0 (AT91C_PIO_PC4) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PC5        (1 <<  5) // Pin Controlled by PC5
+#define AT91C_PC5_A24      (AT91C_PIO_PC5) //  Address Bus[24]
+#define AT91C_PC5_SPI1_NPCS1_0 (AT91C_PIO_PC5) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PC6        (1 <<  6) // Pin Controlled by PC6
+#define AT91C_PC6_TIOB2    (AT91C_PIO_PC6) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PC6_CFCE1    (AT91C_PIO_PC6) //  Compact Flash Enable 1
+#define AT91C_PIO_PC7        (1 <<  7) // Pin Controlled by PC7
+#define AT91C_PC7_TIOB1    (AT91C_PIO_PC7) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PC7_CFCE2    (AT91C_PIO_PC7) //  Compact Flash Enable 2
+#define AT91C_PIO_PC8        (1 <<  8) // Pin Controlled by PC8
+#define AT91C_PC8_NCS4_CFCS0 (AT91C_PIO_PC8) //  Chip Select Line 4
+#define AT91C_PC8_RTS3     (AT91C_PIO_PC8) //  USART 3 Ready To Send
+#define AT91C_PIO_PC9        (1 <<  9) // Pin Controlled by PC9
+#define AT91C_PC9_NCS5_CFCS1 (AT91C_PIO_PC9) //  Chip Select Line 5
+#define AT91C_PC9_TIOB0    (AT91C_PIO_PC9) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM9XE256
+// *****************************************************************************
+#define AT91C_ID_FIQ    ( 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS    ( 1) // System Controller
+#define AT91C_ID_PIOA   ( 2) // Parallel IO Controller A
+#define AT91C_ID_PIOB   ( 3) // Parallel IO Controller B
+#define AT91C_ID_PIOC   ( 4) // Parallel IO Controller C
+#define AT91C_ID_ADC    ( 5) // ADC
+#define AT91C_ID_US0    ( 6) // USART 0
+#define AT91C_ID_US1    ( 7) // USART 1
+#define AT91C_ID_US2    ( 8) // USART 2
+#define AT91C_ID_MCI    ( 9) // Multimedia Card Interface 0
+#define AT91C_ID_UDP    (10) // USB Device Port
+#define AT91C_ID_TWI0   (11) // Two-Wire Interface 0
+#define AT91C_ID_SPI0   (12) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1   (13) // Serial Peripheral Interface 1
+#define AT91C_ID_SSC0   (14) // Serial Synchronous Controller 0
+#define AT91C_ID_TC0    (17) // Timer Counter 0
+#define AT91C_ID_TC1    (18) // Timer Counter 1
+#define AT91C_ID_TC2    (19) // Timer Counter 2
+#define AT91C_ID_UHP    (20) // USB Host Port
+#define AT91C_ID_EMAC   (21) // Ethernet Mac
+#define AT91C_ID_HISI   (22) // Image Sensor Interface
+#define AT91C_ID_US3    (23) // USART 3
+#define AT91C_ID_US4    (24) // USART 4
+#define AT91C_ID_TWI1   (25) // Two-Wire Interface 1
+#define AT91C_ID_TC3    (26) // Timer Counter 3
+#define AT91C_ID_TC4    (27) // Timer Counter 4
+#define AT91C_ID_TC5    (28) // Timer Counter 5
+#define AT91C_ID_IRQ0   (29) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1   (30) // Advanced Interrupt Controller (IRQ1)
+#define AT91C_ID_IRQ2   (31) // Advanced Interrupt Controller (IRQ2)
+#define AT91C_ALL_INT   (0xFFFE7FFF) // ALL VALID INTERRUPTS
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM9XE256
+// *****************************************************************************
+#define AT91C_BASE_SYS       (AT91_CAST(AT91PS_SYS) 	0xFFFFFD00) // (SYS) Base Address
+#define AT91C_BASE_EBI       (AT91_CAST(AT91PS_EBI) 	0xFFFFEA00) // (EBI) Base Address
+#define AT91C_BASE_HECC      (AT91_CAST(AT91PS_ECC) 	0xFFFFE800) // (HECC) Base Address
+#define AT91C_BASE_SDRAMC    (AT91_CAST(AT91PS_SDRAMC) 	0xFFFFEA00) // (SDRAMC) Base Address
+#define AT91C_BASE_SMC       (AT91_CAST(AT91PS_SMC) 	0xFFFFEC00) // (SMC) Base Address
+#define AT91C_BASE_MATRIX    (AT91_CAST(AT91PS_MATRIX) 	0xFFFFEE00) // (MATRIX) Base Address
+#define AT91C_BASE_CCFG      (AT91_CAST(AT91PS_CCFG) 	0xFFFFEF10) // (CCFG) Base Address
+#define AT91C_BASE_PDC_DBGU  (AT91_CAST(AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU      (AT91_CAST(AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_AIC       (AT91_CAST(AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PIOA      (AT91_CAST(AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB      (AT91_CAST(AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_PIOC      (AT91_CAST(AT91PS_PIO) 	0xFFFFF800) // (PIOC) Base Address
+#define AT91C_BASE_EFC       (AT91_CAST(AT91PS_EFC) 	0xFFFFFA00) // (EFC) Base Address
+#define AT91C_BASE_CKGR      (AT91_CAST(AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC       (AT91_CAST(AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC      (AT91_CAST(AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_SHDWC     (AT91_CAST(AT91PS_SHDWC) 	0xFFFFFD10) // (SHDWC) Base Address
+#define AT91C_BASE_RTTC      (AT91_CAST(AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC      (AT91_CAST(AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC      (AT91_CAST(AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_TC0       (AT91_CAST(AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1       (AT91_CAST(AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2       (AT91_CAST(AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TC3       (AT91_CAST(AT91PS_TC) 	0xFFFDC000) // (TC3) Base Address
+#define AT91C_BASE_TC4       (AT91_CAST(AT91PS_TC) 	0xFFFDC040) // (TC4) Base Address
+#define AT91C_BASE_TC5       (AT91_CAST(AT91PS_TC) 	0xFFFDC080) // (TC5) Base Address
+#define AT91C_BASE_TCB0      (AT91_CAST(AT91PS_TCB) 	0xFFFA0000) // (TCB0) Base Address
+#define AT91C_BASE_TCB1      (AT91_CAST(AT91PS_TCB) 	0xFFFDC000) // (TCB1) Base Address
+#define AT91C_BASE_PDC_MCI   (AT91_CAST(AT91PS_PDC) 	0xFFFA8100) // (PDC_MCI) Base Address
+#define AT91C_BASE_MCI       (AT91_CAST(AT91PS_MCI) 	0xFFFA8000) // (MCI) Base Address
+#define AT91C_BASE_PDC_TWI0  (AT91_CAST(AT91PS_PDC) 	0xFFFAC100) // (PDC_TWI0) Base Address
+#define AT91C_BASE_TWI0      (AT91_CAST(AT91PS_TWI) 	0xFFFAC000) // (TWI0) Base Address
+#define AT91C_BASE_PDC_TWI1  (AT91_CAST(AT91PS_PDC) 	0xFFFD8100) // (PDC_TWI1) Base Address
+#define AT91C_BASE_TWI1      (AT91_CAST(AT91PS_TWI) 	0xFFFD8000) // (TWI1) Base Address
+#define AT91C_BASE_PDC_US0   (AT91_CAST(AT91PS_PDC) 	0xFFFB0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0       (AT91_CAST(AT91PS_USART) 	0xFFFB0000) // (US0) Base Address
+#define AT91C_BASE_PDC_US1   (AT91_CAST(AT91PS_PDC) 	0xFFFB4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1       (AT91_CAST(AT91PS_USART) 	0xFFFB4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US2   (AT91_CAST(AT91PS_PDC) 	0xFFFB8100) // (PDC_US2) Base Address
+#define AT91C_BASE_US2       (AT91_CAST(AT91PS_USART) 	0xFFFB8000) // (US2) Base Address
+#define AT91C_BASE_PDC_US3   (AT91_CAST(AT91PS_PDC) 	0xFFFD0100) // (PDC_US3) Base Address
+#define AT91C_BASE_US3       (AT91_CAST(AT91PS_USART) 	0xFFFD0000) // (US3) Base Address
+#define AT91C_BASE_PDC_US4   (AT91_CAST(AT91PS_PDC) 	0xFFFD4100) // (PDC_US4) Base Address
+#define AT91C_BASE_US4       (AT91_CAST(AT91PS_USART) 	0xFFFD4000) // (US4) Base Address
+#define AT91C_BASE_PDC_SSC0  (AT91_CAST(AT91PS_PDC) 	0xFFFBC100) // (PDC_SSC0) Base Address
+#define AT91C_BASE_SSC0      (AT91_CAST(AT91PS_SSC) 	0xFFFBC000) // (SSC0) Base Address
+#define AT91C_BASE_PDC_SPI0  (AT91_CAST(AT91PS_PDC) 	0xFFFC8100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0      (AT91_CAST(AT91PS_SPI) 	0xFFFC8000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_SPI1  (AT91_CAST(AT91PS_PDC) 	0xFFFCC100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1      (AT91_CAST(AT91PS_SPI) 	0xFFFCC000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_ADC   (AT91_CAST(AT91PS_PDC) 	0xFFFE0100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC       (AT91_CAST(AT91PS_ADC) 	0xFFFE0000) // (ADC) Base Address
+#define AT91C_BASE_EMACB     (AT91_CAST(AT91PS_EMAC) 	0xFFFC4000) // (EMACB) Base Address
+#define AT91C_BASE_UDP       (AT91_CAST(AT91PS_UDP) 	0xFFFA4000) // (UDP) Base Address
+#define AT91C_BASE_UHP       (AT91_CAST(AT91PS_UHP) 	0x00500000) // (UHP) Base Address
+#define AT91C_BASE_HISI      (AT91_CAST(AT91PS_ISI) 	0xFFFC0000) // (HISI) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM9XE256
+// *****************************************************************************
+// IROM
+#define AT91C_IROM 	 (0x00100000) // Internal ROM base address
+#define AT91C_IROM_SIZE	 (0x00008000) // Internal ROM size in byte (32 Kbytes)
+// ISRAM
+#define AT91C_ISRAM	 (0x00300000) // Maximum IRAM Area : 32Kbyte base address
+#define AT91C_ISRAM_SIZE	 (0x00008000) // Maximum IRAM Area : 32Kbyte size in byte (32 Kbytes)
+// ISRAM_MIN
+#define AT91C_ISRAM_MIN	 (0x00300000) // Minimun IRAM Area : 32Kbyte base address
+#define AT91C_ISRAM_MIN_SIZE	 (0x00008000) // Minimun IRAM Area : 32Kbyte size in byte (32 Kbytes)
+// IFLASH
+#define AT91C_IFLASH	 (0x00200000) // Maximum IFLASH Area : 256Kbyte base address
+#define AT91C_IFLASH_SIZE	 (0x00040000) // Maximum IFLASH Area : 256Kbyte size in byte (256 Kbytes)
+#define AT91C_IFLASH_PAGE_SIZE	 (512) // Maximum IFLASH Area : 256Kbyte Page Size: 512 bytes
+#define AT91C_IFLASH_LOCK_REGION_SIZE	 (16384) // Maximum IFLASH Area : 256Kbyte Lock Region Size: 16 Kbytes
+#define AT91C_IFLASH_NB_OF_PAGES	 (512) // Maximum IFLASH Area : 256Kbyte Number of Pages: 512 bytes
+#define AT91C_IFLASH_NB_OF_LOCK_BITS	 (16) // Maximum IFLASH Area : 256Kbyte Number of Lock Bits: 16 bytes
+// EBI_CS0
+#define AT91C_EBI_CS0	 (0x10000000) // EBI Chip Select 0 base address
+#define AT91C_EBI_CS0_SIZE	 (0x10000000) // EBI Chip Select 0 size in byte (262144 Kbytes)
+// EBI_CS1
+#define AT91C_EBI_CS1	 (0x20000000) // EBI Chip Select 1 base address
+#define AT91C_EBI_CS1_SIZE	 (0x10000000) // EBI Chip Select 1 size in byte (262144 Kbytes)
+// EBI_SDRAM
+#define AT91C_EBI_SDRAM	 (0x20000000) // SDRAM on EBI Chip Select 1 base address
+#define AT91C_EBI_SDRAM_SIZE	 (0x10000000) // SDRAM on EBI Chip Select 1 size in byte (262144 Kbytes)
+// EBI_SDRAM_16BIT
+#define AT91C_EBI_SDRAM_16BIT	 (0x20000000) // SDRAM on EBI Chip Select 1 base address
+#define AT91C_EBI_SDRAM_16BIT_SIZE	 (0x02000000) // SDRAM on EBI Chip Select 1 size in byte (32768 Kbytes)
+// EBI_SDRAM_32BIT
+#define AT91C_EBI_SDRAM_32BIT	 (0x20000000) // SDRAM on EBI Chip Select 1 base address
+#define AT91C_EBI_SDRAM_32BIT_SIZE	 (0x04000000) // SDRAM on EBI Chip Select 1 size in byte (65536 Kbytes)
+// EBI_CS2
+#define AT91C_EBI_CS2	 (0x30000000) // EBI Chip Select 2 base address
+#define AT91C_EBI_CS2_SIZE	 (0x10000000) // EBI Chip Select 2 size in byte (262144 Kbytes)
+// EBI_CS3
+#define AT91C_EBI_CS3	 (0x40000000) // EBI Chip Select 3 base address
+#define AT91C_EBI_CS3_SIZE	 (0x10000000) // EBI Chip Select 3 size in byte (262144 Kbytes)
+// EBI_SM
+#define AT91C_EBI_SM	 (0x40000000) // SmartMedia on Chip Select 3 base address
+#define AT91C_EBI_SM_SIZE	 (0x10000000) // SmartMedia on Chip Select 3 size in byte (262144 Kbytes)
+// EBI_CS4
+#define AT91C_EBI_CS4	 (0x50000000) // EBI Chip Select 4 base address
+#define AT91C_EBI_CS4_SIZE	 (0x10000000) // EBI Chip Select 4 size in byte (262144 Kbytes)
+// EBI_CF0
+#define AT91C_EBI_CF0	 (0x50000000) // CompactFlash 0 on Chip Select 4 base address
+#define AT91C_EBI_CF0_SIZE	 (0x10000000) // CompactFlash 0 on Chip Select 4 size in byte (262144 Kbytes)
+// EBI_CS5
+#define AT91C_EBI_CS5	 (0x60000000) // EBI Chip Select 5 base address
+#define AT91C_EBI_CS5_SIZE	 (0x10000000) // EBI Chip Select 5 size in byte (262144 Kbytes)
+// EBI_CF1
+#define AT91C_EBI_CF1	 (0x60000000) // CompactFlash 1 on Chip Select 5 base address
+#define AT91C_EBI_CF1_SIZE	 (0x10000000) // CompactFlash 1 on Chip Select 5 size in byte (262144 Kbytes)
+// EBI_CS6
+#define AT91C_EBI_CS6	 (0x70000000) // EBI Chip Select 6 base address
+#define AT91C_EBI_CS6_SIZE	 (0x10000000) // EBI Chip Select 6 size in byte (262144 Kbytes)
+// EBI_CS7
+#define AT91C_EBI_CS7	 (0x80000000) // EBI Chip Select 7 base address
+#define AT91C_EBI_CS7_SIZE	 (0x10000000) // EBI Chip Select 7 size in byte (262144 Kbytes)
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/flash.icf b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/flash.icf
new file mode 100644
index 0000000..eeb2bcb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/flash.icf
@@ -0,0 +1,48 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x200000;
+define symbol __ICFEDIT_region_ROM_end__     = 0x23FFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x300000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x307FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_startup__  = 0x100;
+define symbol __ICFEDIT_size_vectors__  = 0x100;
+define symbol __ICFEDIT_size_cstack__   = 0x1000;
+define symbol __ICFEDIT_size_svcstack__ = 0x60;
+define symbol __ICFEDIT_size_irqstack__ = 0x60;
+define symbol __ICFEDIT_size_heap__     = 0x0;
+/*-Exports-*/
+export symbol __ICFEDIT_region_ROM_start__;
+export symbol __ICFEDIT_region_ROM_end__;
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+export symbol __ICFEDIT_size_startup__;
+export symbol __ICFEDIT_size_vectors__;
+export symbol __ICFEDIT_size_cstack__;
+export symbol __ICFEDIT_size_svcstack__;
+export symbol __ICFEDIT_size_irqstack__;
+export symbol __ICFEDIT_size_heap__;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region STA_region = mem:[from __ICFEDIT_region_ROM_start__ size __ICFEDIT_size_startup__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_ROM_end__];
+define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+initialize by copy { section .vectors };
+do not initialize  { section .noinit };
+
+place in STA_region { section .cstartup };
+place in ROM_region { readonly };
+place in VEC_region { section .vectors };
+place in RAM_region { readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/sdram.icf b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/sdram.icf
new file mode 100644
index 0000000..4753f07
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/sdram.icf
@@ -0,0 +1,46 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_SDRAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_SDRAM_end__   = 0x21FFFFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x300000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x307FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_startup__  = 0x100;
+define symbol __ICFEDIT_size_vectors__  = 0x100;
+define symbol __ICFEDIT_size_cstack__   = 0x1000;
+define symbol __ICFEDIT_size_svcstack__ = 0x60;
+define symbol __ICFEDIT_size_irqstack__ = 0x60;
+define symbol __ICFEDIT_size_heap__     = 0x0;
+/*-Exports-*/
+export symbol __ICFEDIT_region_SDRAM_start__;
+export symbol __ICFEDIT_region_SDRAM_end__;
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+export symbol __ICFEDIT_size_startup__;
+export symbol __ICFEDIT_size_vectors__;
+export symbol __ICFEDIT_size_cstack__;
+export symbol __ICFEDIT_size_svcstack__;
+export symbol __ICFEDIT_size_irqstack__;
+export symbol __ICFEDIT_size_heap__;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region STA_region =   mem:[from __ICFEDIT_region_SDRAM_start__ size __ICFEDIT_size_startup__];
+define region SDRAM_region = mem:[from __ICFEDIT_region_SDRAM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_SDRAM_end__];
+define region VEC_region =   mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
+define region RAM_region =   mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { section .vectors };
+do not initialize  { section .noinit };
+
+place in STA_region { section .cstartup };
+place in VEC_region { section .vectors };
+place in SDRAM_region { readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/sram.icf b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/sram.icf
new file mode 100644
index 0000000..2544f86
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe256/sram.icf
@@ -0,0 +1,36 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__   = 0x300000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x307FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_vectors__  = 0x100;
+define symbol __ICFEDIT_size_cstack__   = 0x800;
+define symbol __ICFEDIT_size_svcstack__ = 0x60;
+define symbol __ICFEDIT_size_irqstack__ = 0x60;
+define symbol __ICFEDIT_size_heap__     = 0x0;
+/*-Exports-*/
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+export symbol __ICFEDIT_size_vectors__;
+export symbol __ICFEDIT_size_cstack__;
+export symbol __ICFEDIT_size_svcstack__;
+export symbol __ICFEDIT_size_irqstack__;
+export symbol __ICFEDIT_size_heap__;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+do not initialize  { section .noinit };
+
+place in VEC_region { section .vectors };
+place in RAM_region { section .cstartup, readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/AT91SAM9XE512.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/AT91SAM9XE512.h
new file mode 100644
index 0000000..54ac781
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/AT91SAM9XE512.h
@@ -0,0 +1,4042 @@
+//  ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+//  ----------------------------------------------------------------------------
+//  Copyright (c) 2006, Atmel Corporation
+// 
+//  All rights reserved.
+// 
+//  Redistribution and use in source and binary forms, with or without
+//  modification, are permitted provided that the following conditions are met:
+// 
+//  - Redistributions of source code must retain the above copyright notice,
+//  this list of conditions and the disclaimer below.
+// 
+//  - Redistributions in binary form must reproduce the above copyright notice,
+//  this list of conditions and the disclaimer below in the documentation and/or
+//  other materials provided with the distribution. 
+// 
+//  Atmel's name may not be used to endorse or promote products derived from
+//  this software without specific prior written permission. 
+//  
+//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  ----------------------------------------------------------------------------
+// File Name           : AT91SAM9XE512.h
+// Object              : AT91SAM9XE512 definitions
+// Generated           : AT91 SW Application Group  02/13/2008 (18:25:59)
+// 
+// CVS Reference       : /AT91SAM9XE512.pl/1.16/Wed Jan 30 14:02:22 2008//
+// CVS Reference       : /SYS_SAM9260.pl/1.2/Wed Feb 13 13:29:23 2008//
+// CVS Reference       : /HMATRIX1_SAM9260.pl/1.7/Mon Apr 23 10:39:45 2007//
+// CVS Reference       : /CCR_SAM9260.pl/1.2/Mon Apr 16 10:47:39 2007//
+// CVS Reference       : /PMC_SAM9262.pl/1.4/Mon Mar  7 18:03:13 2005//
+// CVS Reference       : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
+// CVS Reference       : /HSDRAMC1_6100A.pl/1.2/Mon Aug  9 10:52:25 2004//
+// CVS Reference       : /HSMC3_6105A.pl/1.4/Tue Nov 16 09:16:23 2004//
+// CVS Reference       : /AIC_6075A.pl/1.1/Mon Jul 12 17:04:01 2004//
+// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 09:02:11 2005//
+// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
+// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:29:42 2005//
+// CVS Reference       : /RSTC_6098A.pl/1.3/Thu Nov  4 13:57:00 2004//
+// CVS Reference       : /SHDWC_6122A.pl/1.3/Wed Oct  6 14:16:58 2004//
+// CVS Reference       : /RTTC_6081A.pl/1.2/Thu Nov  4 13:57:22 2004//
+// CVS Reference       : /PITC_6079A.pl/1.2/Thu Nov  4 13:56:22 2004//
+// CVS Reference       : /WDTC_6080A.pl/1.3/Thu Nov  4 13:58:52 2004//
+// CVS Reference       : /EFC2_IGS036.pl/1.2/Fri Nov 10 10:47:53 2006//
+// CVS Reference       : /TC_6082A.pl/1.7/Wed Mar  9 16:31:51 2005//
+// CVS Reference       : /MCI_6101E.pl/1.1/Fri Jun  3 13:20:23 2005//
+// CVS Reference       : /TWI_6061B.pl/1.2/Fri Aug  4 08:53:02 2006//
+// CVS Reference       : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
+// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//
+// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
+// CVS Reference       : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//
+// CVS Reference       : /UDP_6ept_puon.pl/1.1/Wed Aug 30 14:20:53 2006//
+// CVS Reference       : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005//
+// CVS Reference       : /EBI_SAM9260.pl/1.1/Fri Sep 30 12:12:14 2005//
+// CVS Reference       : /HECC_6143A.pl/1.1/Wed Feb  9 17:16:57 2005//
+// CVS Reference       : /ISI_xxxxx.pl/1.3/Thu Mar  3 11:11:48 2005//
+//  ----------------------------------------------------------------------------
+
+#ifndef AT91SAM9XE512_H
+#define AT91SAM9XE512_H
+
+#ifndef __ASSEMBLY__
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+#define AT91_CAST(a) (a)
+#else
+#define AT91_CAST(a)
+#endif
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SYS {
+	AT91_REG	 Reserved0[2560]; 	// 
+	AT91_REG	 ECC_CR; 	//  ECC reset register
+	AT91_REG	 ECC_MR; 	//  ECC Page size register
+	AT91_REG	 ECC_SR; 	//  ECC Status register
+	AT91_REG	 ECC_PR; 	//  ECC Parity register
+	AT91_REG	 ECC_NPR; 	//  ECC Parity N register
+	AT91_REG	 Reserved1[58]; 	// 
+	AT91_REG	 ECC_VR; 	//  ECC Version register
+	AT91_REG	 Reserved2[64]; 	// 
+	AT91_REG	 SDRAMC_MR; 	// SDRAM Controller Mode Register
+	AT91_REG	 SDRAMC_TR; 	// SDRAM Controller Refresh Timer Register
+	AT91_REG	 SDRAMC_CR; 	// SDRAM Controller Configuration Register
+	AT91_REG	 SDRAMC_HSR; 	// SDRAM Controller High Speed Register
+	AT91_REG	 SDRAMC_LPR; 	// SDRAM Controller Low Power Register
+	AT91_REG	 SDRAMC_IER; 	// SDRAM Controller Interrupt Enable Register
+	AT91_REG	 SDRAMC_IDR; 	// SDRAM Controller Interrupt Disable Register
+	AT91_REG	 SDRAMC_IMR; 	// SDRAM Controller Interrupt Mask Register
+	AT91_REG	 SDRAMC_ISR; 	// SDRAM Controller Interrupt Mask Register
+	AT91_REG	 SDRAMC_MDR; 	// SDRAM Memory Device Register
+	AT91_REG	 Reserved3[118]; 	// 
+	AT91_REG	 SMC_SETUP0; 	//  Setup Register for CS 0
+	AT91_REG	 SMC_PULSE0; 	//  Pulse Register for CS 0
+	AT91_REG	 SMC_CYCLE0; 	//  Cycle Register for CS 0
+	AT91_REG	 SMC_CTRL0; 	//  Control Register for CS 0
+	AT91_REG	 SMC_SETUP1; 	//  Setup Register for CS 1
+	AT91_REG	 SMC_PULSE1; 	//  Pulse Register for CS 1
+	AT91_REG	 SMC_CYCLE1; 	//  Cycle Register for CS 1
+	AT91_REG	 SMC_CTRL1; 	//  Control Register for CS 1
+	AT91_REG	 SMC_SETUP2; 	//  Setup Register for CS 2
+	AT91_REG	 SMC_PULSE2; 	//  Pulse Register for CS 2
+	AT91_REG	 SMC_CYCLE2; 	//  Cycle Register for CS 2
+	AT91_REG	 SMC_CTRL2; 	//  Control Register for CS 2
+	AT91_REG	 SMC_SETUP3; 	//  Setup Register for CS 3
+	AT91_REG	 SMC_PULSE3; 	//  Pulse Register for CS 3
+	AT91_REG	 SMC_CYCLE3; 	//  Cycle Register for CS 3
+	AT91_REG	 SMC_CTRL3; 	//  Control Register for CS 3
+	AT91_REG	 SMC_SETUP4; 	//  Setup Register for CS 4
+	AT91_REG	 SMC_PULSE4; 	//  Pulse Register for CS 4
+	AT91_REG	 SMC_CYCLE4; 	//  Cycle Register for CS 4
+	AT91_REG	 SMC_CTRL4; 	//  Control Register for CS 4
+	AT91_REG	 SMC_SETUP5; 	//  Setup Register for CS 5
+	AT91_REG	 SMC_PULSE5; 	//  Pulse Register for CS 5
+	AT91_REG	 SMC_CYCLE5; 	//  Cycle Register for CS 5
+	AT91_REG	 SMC_CTRL5; 	//  Control Register for CS 5
+	AT91_REG	 SMC_SETUP6; 	//  Setup Register for CS 6
+	AT91_REG	 SMC_PULSE6; 	//  Pulse Register for CS 6
+	AT91_REG	 SMC_CYCLE6; 	//  Cycle Register for CS 6
+	AT91_REG	 SMC_CTRL6; 	//  Control Register for CS 6
+	AT91_REG	 SMC_SETUP7; 	//  Setup Register for CS 7
+	AT91_REG	 SMC_PULSE7; 	//  Pulse Register for CS 7
+	AT91_REG	 SMC_CYCLE7; 	//  Cycle Register for CS 7
+	AT91_REG	 SMC_CTRL7; 	//  Control Register for CS 7
+	AT91_REG	 Reserved4[96]; 	// 
+	AT91_REG	 MATRIX_MCFG0; 	//  Master Configuration Register 0 (ram96k)     
+	AT91_REG	 MATRIX_MCFG1; 	//  Master Configuration Register 1 (rom)    
+	AT91_REG	 MATRIX_MCFG2; 	//  Master Configuration Register 2 (hperiphs) 
+	AT91_REG	 MATRIX_MCFG3; 	//  Master Configuration Register 3 (ebi)
+	AT91_REG	 MATRIX_MCFG4; 	//  Master Configuration Register 4 (bridge)    
+	AT91_REG	 MATRIX_MCFG5; 	//  Master Configuration Register 5 (mailbox)    
+	AT91_REG	 MATRIX_MCFG6; 	//  Master Configuration Register 6 (ram16k)  
+	AT91_REG	 MATRIX_MCFG7; 	//  Master Configuration Register 7 (teak_prog)     
+	AT91_REG	 Reserved5[8]; 	// 
+	AT91_REG	 MATRIX_SCFG0; 	//  Slave Configuration Register 0 (ram96k)     
+	AT91_REG	 MATRIX_SCFG1; 	//  Slave Configuration Register 1 (rom)    
+	AT91_REG	 MATRIX_SCFG2; 	//  Slave Configuration Register 2 (hperiphs) 
+	AT91_REG	 MATRIX_SCFG3; 	//  Slave Configuration Register 3 (ebi)
+	AT91_REG	 MATRIX_SCFG4; 	//  Slave Configuration Register 4 (bridge)    
+	AT91_REG	 Reserved6[11]; 	// 
+	AT91_REG	 MATRIX_PRAS0; 	//  PRAS0 (ram0) 
+	AT91_REG	 MATRIX_PRBS0; 	//  PRBS0 (ram0) 
+	AT91_REG	 MATRIX_PRAS1; 	//  PRAS1 (ram1) 
+	AT91_REG	 MATRIX_PRBS1; 	//  PRBS1 (ram1) 
+	AT91_REG	 MATRIX_PRAS2; 	//  PRAS2 (ram2) 
+	AT91_REG	 MATRIX_PRBS2; 	//  PRBS2 (ram2) 
+	AT91_REG	 MATRIX_PRAS3; 	//  PRAS3 : usb_dev_hs
+	AT91_REG	 MATRIX_PRBS3; 	//  PRBS3 : usb_dev_hs
+	AT91_REG	 MATRIX_PRAS4; 	//  PRAS4 : ebi
+	AT91_REG	 MATRIX_PRBS4; 	//  PRBS4 : ebi
+	AT91_REG	 Reserved7[22]; 	// 
+	AT91_REG	 MATRIX_MRCR; 	//  Master Remp Control Register 
+	AT91_REG	 Reserved8[6]; 	// 
+	AT91_REG	 CCFG_EBICSA; 	//  EBI Chip Select Assignement Register
+	AT91_REG	 Reserved9[3]; 	// 
+	AT91_REG	 MATRIX_TEAKCFG; 	//  Slave 7 (teak_prog) Special Function Register
+	AT91_REG	 Reserved10[51]; 	// 
+	AT91_REG	 CCFG_MATRIXVERSION; 	//  Version Register
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved11[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved12[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+	AT91_REG	 Reserved13[45]; 	// 
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved14[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved15[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+	AT91_REG	 Reserved16[54]; 	// 
+	AT91_REG	 PIOA_PER; 	// PIO Enable Register
+	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOA_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved17[1]; 	// 
+	AT91_REG	 PIOA_OER; 	// Output Enable Register
+	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOA_OSR; 	// Output Status Register
+	AT91_REG	 Reserved18[1]; 	// 
+	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved19[1]; 	// 
+	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved20[1]; 	// 
+	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved21[1]; 	// 
+	AT91_REG	 PIOA_ASR; 	// Select A Register
+	AT91_REG	 PIOA_BSR; 	// Select B Register
+	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved22[9]; 	// 
+	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved23[213]; 	// 
+	AT91_REG	 PIOB_PER; 	// PIO Enable Register
+	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOB_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved24[1]; 	// 
+	AT91_REG	 PIOB_OER; 	// Output Enable Register
+	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOB_OSR; 	// Output Status Register
+	AT91_REG	 Reserved25[1]; 	// 
+	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved26[1]; 	// 
+	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved27[1]; 	// 
+	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved28[1]; 	// 
+	AT91_REG	 PIOB_ASR; 	// Select A Register
+	AT91_REG	 PIOB_BSR; 	// Select B Register
+	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved29[9]; 	// 
+	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved30[85]; 	// 
+	AT91_REG	 PIOC_PER; 	// PIO Enable Register
+	AT91_REG	 PIOC_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOC_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved31[1]; 	// 
+	AT91_REG	 PIOC_OER; 	// Output Enable Register
+	AT91_REG	 PIOC_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOC_OSR; 	// Output Status Register
+	AT91_REG	 Reserved32[1]; 	// 
+	AT91_REG	 PIOC_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOC_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOC_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved33[1]; 	// 
+	AT91_REG	 PIOC_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOC_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOC_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOC_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOC_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOC_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOC_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOC_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved34[1]; 	// 
+	AT91_REG	 PIOC_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOC_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOC_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved35[1]; 	// 
+	AT91_REG	 PIOC_ASR; 	// Select A Register
+	AT91_REG	 PIOC_BSR; 	// Select B Register
+	AT91_REG	 PIOC_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved36[9]; 	// 
+	AT91_REG	 PIOC_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOC_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOC_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved37[85]; 	// 
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved38[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved39[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 PMC_PLLAR; 	// PLL A Register
+	AT91_REG	 PMC_PLLBR; 	// PLL B Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved40[3]; 	// 
+	AT91_REG	 PMC_PCKR[8]; 	// Programmable Clock Register
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved41[36]; 	// 
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+	AT91_REG	 Reserved42[1]; 	// 
+	AT91_REG	 SHDWC_SHCR; 	// Shut Down Control Register
+	AT91_REG	 SHDWC_SHMR; 	// Shut Down Mode Register
+	AT91_REG	 SHDWC_SHSR; 	// Shut Down Status Register
+	AT91_REG	 Reserved43[1]; 	// 
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+	AT91_REG	 Reserved44[1]; 	// 
+	AT91_REG	 SYS_GPBR[4]; 	// General Purpose Register
+} AT91S_SYS, *AT91PS_SYS;
+#else
+#define SYS_GPBR        (AT91_CAST(AT91_REG *) 	0x00003D50) // (SYS_GPBR) General Purpose Register
+
+#endif
+// -------- GPBR : (SYS Offset: 0x3d50) GPBR General Purpose Register -------- 
+#define AT91C_GPBR_GPRV       (0x0 <<  0) // (SYS) General Purpose Register Value
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR External Bus Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_EBI {
+	AT91_REG	 EBI_DUMMY; 	// Dummy register - Do not use
+} AT91S_EBI, *AT91PS_EBI;
+#else
+#define EBI_DUMMY       (AT91_CAST(AT91_REG *) 	0x00000000) // (EBI_DUMMY) Dummy register - Do not use
+
+#endif
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Error Correction Code controller
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_ECC {
+	AT91_REG	 ECC_CR; 	//  ECC reset register
+	AT91_REG	 ECC_MR; 	//  ECC Page size register
+	AT91_REG	 ECC_SR; 	//  ECC Status register
+	AT91_REG	 ECC_PR; 	//  ECC Parity register
+	AT91_REG	 ECC_NPR; 	//  ECC Parity N register
+	AT91_REG	 Reserved0[58]; 	// 
+	AT91_REG	 ECC_VR; 	//  ECC Version register
+} AT91S_ECC, *AT91PS_ECC;
+#else
+#define ECC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (ECC_CR)  ECC reset register
+#define ECC_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (ECC_MR)  ECC Page size register
+#define ECC_SR          (AT91_CAST(AT91_REG *) 	0x00000008) // (ECC_SR)  ECC Status register
+#define ECC_PR          (AT91_CAST(AT91_REG *) 	0x0000000C) // (ECC_PR)  ECC Parity register
+#define ECC_NPR         (AT91_CAST(AT91_REG *) 	0x00000010) // (ECC_NPR)  ECC Parity N register
+#define ECC_VR          (AT91_CAST(AT91_REG *) 	0x000000FC) // (ECC_VR)  ECC Version register
+
+#endif
+// -------- ECC_CR : (ECC Offset: 0x0) ECC reset register -------- 
+#define AT91C_ECC_RST         (0x1 <<  0) // (ECC) ECC reset parity
+// -------- ECC_MR : (ECC Offset: 0x4) ECC page size register -------- 
+#define AT91C_ECC_PAGE_SIZE   (0x3 <<  0) // (ECC) Nand Flash page size
+// -------- ECC_SR : (ECC Offset: 0x8) ECC status register -------- 
+#define AT91C_ECC_RECERR      (0x1 <<  0) // (ECC) ECC error
+#define AT91C_ECC_ECCERR      (0x1 <<  1) // (ECC) ECC single error
+#define AT91C_ECC_MULERR      (0x1 <<  2) // (ECC) ECC_MULERR
+// -------- ECC_PR : (ECC Offset: 0xc) ECC parity register -------- 
+#define AT91C_ECC_BITADDR     (0xF <<  0) // (ECC) Bit address error
+#define AT91C_ECC_WORDADDR    (0xFFF <<  4) // (ECC) address of the failing bit
+// -------- ECC_NPR : (ECC Offset: 0x10) ECC N parity register -------- 
+#define AT91C_ECC_NPARITY     (0xFFFF <<  0) // (ECC) ECC parity N 
+// -------- ECC_VR : (ECC Offset: 0xfc) ECC version register -------- 
+#define AT91C_ECC_VR          (0xF <<  0) // (ECC) ECC version register
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR SDRAM Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SDRAMC {
+	AT91_REG	 SDRAMC_MR; 	// SDRAM Controller Mode Register
+	AT91_REG	 SDRAMC_TR; 	// SDRAM Controller Refresh Timer Register
+	AT91_REG	 SDRAMC_CR; 	// SDRAM Controller Configuration Register
+	AT91_REG	 SDRAMC_HSR; 	// SDRAM Controller High Speed Register
+	AT91_REG	 SDRAMC_LPR; 	// SDRAM Controller Low Power Register
+	AT91_REG	 SDRAMC_IER; 	// SDRAM Controller Interrupt Enable Register
+	AT91_REG	 SDRAMC_IDR; 	// SDRAM Controller Interrupt Disable Register
+	AT91_REG	 SDRAMC_IMR; 	// SDRAM Controller Interrupt Mask Register
+	AT91_REG	 SDRAMC_ISR; 	// SDRAM Controller Interrupt Mask Register
+	AT91_REG	 SDRAMC_MDR; 	// SDRAM Memory Device Register
+} AT91S_SDRAMC, *AT91PS_SDRAMC;
+#else
+#define SDRAMC_MR       (AT91_CAST(AT91_REG *) 	0x00000000) // (SDRAMC_MR) SDRAM Controller Mode Register
+#define SDRAMC_TR       (AT91_CAST(AT91_REG *) 	0x00000004) // (SDRAMC_TR) SDRAM Controller Refresh Timer Register
+#define SDRAMC_CR       (AT91_CAST(AT91_REG *) 	0x00000008) // (SDRAMC_CR) SDRAM Controller Configuration Register
+#define SDRAMC_HSR      (AT91_CAST(AT91_REG *) 	0x0000000C) // (SDRAMC_HSR) SDRAM Controller High Speed Register
+#define SDRAMC_LPR      (AT91_CAST(AT91_REG *) 	0x00000010) // (SDRAMC_LPR) SDRAM Controller Low Power Register
+#define SDRAMC_IER      (AT91_CAST(AT91_REG *) 	0x00000014) // (SDRAMC_IER) SDRAM Controller Interrupt Enable Register
+#define SDRAMC_IDR      (AT91_CAST(AT91_REG *) 	0x00000018) // (SDRAMC_IDR) SDRAM Controller Interrupt Disable Register
+#define SDRAMC_IMR      (AT91_CAST(AT91_REG *) 	0x0000001C) // (SDRAMC_IMR) SDRAM Controller Interrupt Mask Register
+#define SDRAMC_ISR      (AT91_CAST(AT91_REG *) 	0x00000020) // (SDRAMC_ISR) SDRAM Controller Interrupt Mask Register
+#define SDRAMC_MDR      (AT91_CAST(AT91_REG *) 	0x00000024) // (SDRAMC_MDR) SDRAM Memory Device Register
+
+#endif
+// -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register -------- 
+#define AT91C_SDRAMC_MODE     (0xF <<  0) // (SDRAMC) Mode
+#define 	AT91C_SDRAMC_MODE_NORMAL_CMD           (0x0) // (SDRAMC) Normal Mode
+#define 	AT91C_SDRAMC_MODE_NOP_CMD              (0x1) // (SDRAMC) Issue a NOP Command at every access
+#define 	AT91C_SDRAMC_MODE_PRCGALL_CMD          (0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access
+#define 	AT91C_SDRAMC_MODE_LMR_CMD              (0x3) // (SDRAMC) Issue a Load Mode Register at every access
+#define 	AT91C_SDRAMC_MODE_RFSH_CMD             (0x4) // (SDRAMC) Issue a Refresh
+#define 	AT91C_SDRAMC_MODE_EXT_LMR_CMD          (0x5) // (SDRAMC) Issue an Extended Load Mode Register
+#define 	AT91C_SDRAMC_MODE_DEEP_CMD             (0x6) // (SDRAMC) Enter Deep Power Mode
+// -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register -------- 
+#define AT91C_SDRAMC_COUNT    (0xFFF <<  0) // (SDRAMC) Refresh Counter
+// -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register -------- 
+#define AT91C_SDRAMC_NC       (0x3 <<  0) // (SDRAMC) Number of Column Bits
+#define 	AT91C_SDRAMC_NC_8                    (0x0) // (SDRAMC) 8 Bits
+#define 	AT91C_SDRAMC_NC_9                    (0x1) // (SDRAMC) 9 Bits
+#define 	AT91C_SDRAMC_NC_10                   (0x2) // (SDRAMC) 10 Bits
+#define 	AT91C_SDRAMC_NC_11                   (0x3) // (SDRAMC) 11 Bits
+#define AT91C_SDRAMC_NR       (0x3 <<  2) // (SDRAMC) Number of Row Bits
+#define 	AT91C_SDRAMC_NR_11                   (0x0 <<  2) // (SDRAMC) 11 Bits
+#define 	AT91C_SDRAMC_NR_12                   (0x1 <<  2) // (SDRAMC) 12 Bits
+#define 	AT91C_SDRAMC_NR_13                   (0x2 <<  2) // (SDRAMC) 13 Bits
+#define AT91C_SDRAMC_NB       (0x1 <<  4) // (SDRAMC) Number of Banks
+#define 	AT91C_SDRAMC_NB_2_BANKS              (0x0 <<  4) // (SDRAMC) 2 banks
+#define 	AT91C_SDRAMC_NB_4_BANKS              (0x1 <<  4) // (SDRAMC) 4 banks
+#define AT91C_SDRAMC_CAS      (0x3 <<  5) // (SDRAMC) CAS Latency
+#define 	AT91C_SDRAMC_CAS_2                    (0x2 <<  5) // (SDRAMC) 2 cycles
+#define 	AT91C_SDRAMC_CAS_3                    (0x3 <<  5) // (SDRAMC) 3 cycles
+#define AT91C_SDRAMC_DBW      (0x1 <<  7) // (SDRAMC) Data Bus Width
+#define 	AT91C_SDRAMC_DBW_32_BITS              (0x0 <<  7) // (SDRAMC) 32 Bits datas bus
+#define 	AT91C_SDRAMC_DBW_16_BITS              (0x1 <<  7) // (SDRAMC) 16 Bits datas bus
+#define AT91C_SDRAMC_TWR      (0xF <<  8) // (SDRAMC) Number of Write Recovery Time Cycles
+#define 	AT91C_SDRAMC_TWR_0                    (0x0 <<  8) // (SDRAMC) Value :  0
+#define 	AT91C_SDRAMC_TWR_1                    (0x1 <<  8) // (SDRAMC) Value :  1
+#define 	AT91C_SDRAMC_TWR_2                    (0x2 <<  8) // (SDRAMC) Value :  2
+#define 	AT91C_SDRAMC_TWR_3                    (0x3 <<  8) // (SDRAMC) Value :  3
+#define 	AT91C_SDRAMC_TWR_4                    (0x4 <<  8) // (SDRAMC) Value :  4
+#define 	AT91C_SDRAMC_TWR_5                    (0x5 <<  8) // (SDRAMC) Value :  5
+#define 	AT91C_SDRAMC_TWR_6                    (0x6 <<  8) // (SDRAMC) Value :  6
+#define 	AT91C_SDRAMC_TWR_7                    (0x7 <<  8) // (SDRAMC) Value :  7
+#define 	AT91C_SDRAMC_TWR_8                    (0x8 <<  8) // (SDRAMC) Value :  8
+#define 	AT91C_SDRAMC_TWR_9                    (0x9 <<  8) // (SDRAMC) Value :  9
+#define 	AT91C_SDRAMC_TWR_10                   (0xA <<  8) // (SDRAMC) Value : 10
+#define 	AT91C_SDRAMC_TWR_11                   (0xB <<  8) // (SDRAMC) Value : 11
+#define 	AT91C_SDRAMC_TWR_12                   (0xC <<  8) // (SDRAMC) Value : 12
+#define 	AT91C_SDRAMC_TWR_13                   (0xD <<  8) // (SDRAMC) Value : 13
+#define 	AT91C_SDRAMC_TWR_14                   (0xE <<  8) // (SDRAMC) Value : 14
+#define 	AT91C_SDRAMC_TWR_15                   (0xF <<  8) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TRC      (0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles
+#define 	AT91C_SDRAMC_TRC_0                    (0x0 << 12) // (SDRAMC) Value :  0
+#define 	AT91C_SDRAMC_TRC_1                    (0x1 << 12) // (SDRAMC) Value :  1
+#define 	AT91C_SDRAMC_TRC_2                    (0x2 << 12) // (SDRAMC) Value :  2
+#define 	AT91C_SDRAMC_TRC_3                    (0x3 << 12) // (SDRAMC) Value :  3
+#define 	AT91C_SDRAMC_TRC_4                    (0x4 << 12) // (SDRAMC) Value :  4
+#define 	AT91C_SDRAMC_TRC_5                    (0x5 << 12) // (SDRAMC) Value :  5
+#define 	AT91C_SDRAMC_TRC_6                    (0x6 << 12) // (SDRAMC) Value :  6
+#define 	AT91C_SDRAMC_TRC_7                    (0x7 << 12) // (SDRAMC) Value :  7
+#define 	AT91C_SDRAMC_TRC_8                    (0x8 << 12) // (SDRAMC) Value :  8
+#define 	AT91C_SDRAMC_TRC_9                    (0x9 << 12) // (SDRAMC) Value :  9
+#define 	AT91C_SDRAMC_TRC_10                   (0xA << 12) // (SDRAMC) Value : 10
+#define 	AT91C_SDRAMC_TRC_11                   (0xB << 12) // (SDRAMC) Value : 11
+#define 	AT91C_SDRAMC_TRC_12                   (0xC << 12) // (SDRAMC) Value : 12
+#define 	AT91C_SDRAMC_TRC_13                   (0xD << 12) // (SDRAMC) Value : 13
+#define 	AT91C_SDRAMC_TRC_14                   (0xE << 12) // (SDRAMC) Value : 14
+#define 	AT91C_SDRAMC_TRC_15                   (0xF << 12) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TRP      (0xF << 16) // (SDRAMC) Number of RAS Precharge Time Cycles
+#define 	AT91C_SDRAMC_TRP_0                    (0x0 << 16) // (SDRAMC) Value :  0
+#define 	AT91C_SDRAMC_TRP_1                    (0x1 << 16) // (SDRAMC) Value :  1
+#define 	AT91C_SDRAMC_TRP_2                    (0x2 << 16) // (SDRAMC) Value :  2
+#define 	AT91C_SDRAMC_TRP_3                    (0x3 << 16) // (SDRAMC) Value :  3
+#define 	AT91C_SDRAMC_TRP_4                    (0x4 << 16) // (SDRAMC) Value :  4
+#define 	AT91C_SDRAMC_TRP_5                    (0x5 << 16) // (SDRAMC) Value :  5
+#define 	AT91C_SDRAMC_TRP_6                    (0x6 << 16) // (SDRAMC) Value :  6
+#define 	AT91C_SDRAMC_TRP_7                    (0x7 << 16) // (SDRAMC) Value :  7
+#define 	AT91C_SDRAMC_TRP_8                    (0x8 << 16) // (SDRAMC) Value :  8
+#define 	AT91C_SDRAMC_TRP_9                    (0x9 << 16) // (SDRAMC) Value :  9
+#define 	AT91C_SDRAMC_TRP_10                   (0xA << 16) // (SDRAMC) Value : 10
+#define 	AT91C_SDRAMC_TRP_11                   (0xB << 16) // (SDRAMC) Value : 11
+#define 	AT91C_SDRAMC_TRP_12                   (0xC << 16) // (SDRAMC) Value : 12
+#define 	AT91C_SDRAMC_TRP_13                   (0xD << 16) // (SDRAMC) Value : 13
+#define 	AT91C_SDRAMC_TRP_14                   (0xE << 16) // (SDRAMC) Value : 14
+#define 	AT91C_SDRAMC_TRP_15                   (0xF << 16) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TRCD     (0xF << 20) // (SDRAMC) Number of RAS to CAS Delay Cycles
+#define 	AT91C_SDRAMC_TRCD_0                    (0x0 << 20) // (SDRAMC) Value :  0
+#define 	AT91C_SDRAMC_TRCD_1                    (0x1 << 20) // (SDRAMC) Value :  1
+#define 	AT91C_SDRAMC_TRCD_2                    (0x2 << 20) // (SDRAMC) Value :  2
+#define 	AT91C_SDRAMC_TRCD_3                    (0x3 << 20) // (SDRAMC) Value :  3
+#define 	AT91C_SDRAMC_TRCD_4                    (0x4 << 20) // (SDRAMC) Value :  4
+#define 	AT91C_SDRAMC_TRCD_5                    (0x5 << 20) // (SDRAMC) Value :  5
+#define 	AT91C_SDRAMC_TRCD_6                    (0x6 << 20) // (SDRAMC) Value :  6
+#define 	AT91C_SDRAMC_TRCD_7                    (0x7 << 20) // (SDRAMC) Value :  7
+#define 	AT91C_SDRAMC_TRCD_8                    (0x8 << 20) // (SDRAMC) Value :  8
+#define 	AT91C_SDRAMC_TRCD_9                    (0x9 << 20) // (SDRAMC) Value :  9
+#define 	AT91C_SDRAMC_TRCD_10                   (0xA << 20) // (SDRAMC) Value : 10
+#define 	AT91C_SDRAMC_TRCD_11                   (0xB << 20) // (SDRAMC) Value : 11
+#define 	AT91C_SDRAMC_TRCD_12                   (0xC << 20) // (SDRAMC) Value : 12
+#define 	AT91C_SDRAMC_TRCD_13                   (0xD << 20) // (SDRAMC) Value : 13
+#define 	AT91C_SDRAMC_TRCD_14                   (0xE << 20) // (SDRAMC) Value : 14
+#define 	AT91C_SDRAMC_TRCD_15                   (0xF << 20) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TRAS     (0xF << 24) // (SDRAMC) Number of RAS Active Time Cycles
+#define 	AT91C_SDRAMC_TRAS_0                    (0x0 << 24) // (SDRAMC) Value :  0
+#define 	AT91C_SDRAMC_TRAS_1                    (0x1 << 24) // (SDRAMC) Value :  1
+#define 	AT91C_SDRAMC_TRAS_2                    (0x2 << 24) // (SDRAMC) Value :  2
+#define 	AT91C_SDRAMC_TRAS_3                    (0x3 << 24) // (SDRAMC) Value :  3
+#define 	AT91C_SDRAMC_TRAS_4                    (0x4 << 24) // (SDRAMC) Value :  4
+#define 	AT91C_SDRAMC_TRAS_5                    (0x5 << 24) // (SDRAMC) Value :  5
+#define 	AT91C_SDRAMC_TRAS_6                    (0x6 << 24) // (SDRAMC) Value :  6
+#define 	AT91C_SDRAMC_TRAS_7                    (0x7 << 24) // (SDRAMC) Value :  7
+#define 	AT91C_SDRAMC_TRAS_8                    (0x8 << 24) // (SDRAMC) Value :  8
+#define 	AT91C_SDRAMC_TRAS_9                    (0x9 << 24) // (SDRAMC) Value :  9
+#define 	AT91C_SDRAMC_TRAS_10                   (0xA << 24) // (SDRAMC) Value : 10
+#define 	AT91C_SDRAMC_TRAS_11                   (0xB << 24) // (SDRAMC) Value : 11
+#define 	AT91C_SDRAMC_TRAS_12                   (0xC << 24) // (SDRAMC) Value : 12
+#define 	AT91C_SDRAMC_TRAS_13                   (0xD << 24) // (SDRAMC) Value : 13
+#define 	AT91C_SDRAMC_TRAS_14                   (0xE << 24) // (SDRAMC) Value : 14
+#define 	AT91C_SDRAMC_TRAS_15                   (0xF << 24) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TXSR     (0xF << 28) // (SDRAMC) Number of Command Recovery Time Cycles
+#define 	AT91C_SDRAMC_TXSR_0                    (0x0 << 28) // (SDRAMC) Value :  0
+#define 	AT91C_SDRAMC_TXSR_1                    (0x1 << 28) // (SDRAMC) Value :  1
+#define 	AT91C_SDRAMC_TXSR_2                    (0x2 << 28) // (SDRAMC) Value :  2
+#define 	AT91C_SDRAMC_TXSR_3                    (0x3 << 28) // (SDRAMC) Value :  3
+#define 	AT91C_SDRAMC_TXSR_4                    (0x4 << 28) // (SDRAMC) Value :  4
+#define 	AT91C_SDRAMC_TXSR_5                    (0x5 << 28) // (SDRAMC) Value :  5
+#define 	AT91C_SDRAMC_TXSR_6                    (0x6 << 28) // (SDRAMC) Value :  6
+#define 	AT91C_SDRAMC_TXSR_7                    (0x7 << 28) // (SDRAMC) Value :  7
+#define 	AT91C_SDRAMC_TXSR_8                    (0x8 << 28) // (SDRAMC) Value :  8
+#define 	AT91C_SDRAMC_TXSR_9                    (0x9 << 28) // (SDRAMC) Value :  9
+#define 	AT91C_SDRAMC_TXSR_10                   (0xA << 28) // (SDRAMC) Value : 10
+#define 	AT91C_SDRAMC_TXSR_11                   (0xB << 28) // (SDRAMC) Value : 11
+#define 	AT91C_SDRAMC_TXSR_12                   (0xC << 28) // (SDRAMC) Value : 12
+#define 	AT91C_SDRAMC_TXSR_13                   (0xD << 28) // (SDRAMC) Value : 13
+#define 	AT91C_SDRAMC_TXSR_14                   (0xE << 28) // (SDRAMC) Value : 14
+#define 	AT91C_SDRAMC_TXSR_15                   (0xF << 28) // (SDRAMC) Value : 15
+// -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register -------- 
+#define AT91C_SDRAMC_DA       (0x1 <<  0) // (SDRAMC) Decode Cycle Enable Bit
+#define 	AT91C_SDRAMC_DA_DISABLE              (0x0) // (SDRAMC) Disable Decode Cycle
+#define 	AT91C_SDRAMC_DA_ENABLE               (0x1) // (SDRAMC) Enable Decode Cycle
+// -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register -------- 
+#define AT91C_SDRAMC_LPCB     (0x3 <<  0) // (SDRAMC) Low-power Configurations
+#define 	AT91C_SDRAMC_LPCB_DISABLE              (0x0) // (SDRAMC) Disable Low Power Features
+#define 	AT91C_SDRAMC_LPCB_SELF_REFRESH         (0x1) // (SDRAMC) Enable SELF_REFRESH
+#define 	AT91C_SDRAMC_LPCB_POWER_DOWN           (0x2) // (SDRAMC) Enable POWER_DOWN
+#define 	AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN      (0x3) // (SDRAMC) Enable DEEP_POWER_DOWN
+#define AT91C_SDRAMC_PASR     (0x7 <<  4) // (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM)
+#define AT91C_SDRAMC_TCSR     (0x3 <<  8) // (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM)
+#define AT91C_SDRAMC_DS       (0x3 << 10) // (SDRAMC) Drive Strenght (only for Low Power SDRAM)
+#define AT91C_SDRAMC_TIMEOUT  (0x3 << 12) // (SDRAMC) Time to define when Low Power Mode is enabled
+#define 	AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES         (0x0 << 12) // (SDRAMC) Activate SDRAM Low Power Mode Immediately
+#define 	AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES        (0x1 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
+#define 	AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES       (0x2 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
+// -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- 
+#define AT91C_SDRAMC_RES      (0x1 <<  0) // (SDRAMC) Refresh Error Status
+// -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- 
+// -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- 
+// -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- 
+// -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register -------- 
+#define AT91C_SDRAMC_MD       (0x3 <<  0) // (SDRAMC) Memory Device Type
+#define 	AT91C_SDRAMC_MD_SDRAM                (0x0) // (SDRAMC) SDRAM Mode
+#define 	AT91C_SDRAMC_MD_LOW_POWER_SDRAM      (0x1) // (SDRAMC) SDRAM Low Power Mode
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Static Memory Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SMC {
+	AT91_REG	 SMC_SETUP0; 	//  Setup Register for CS 0
+	AT91_REG	 SMC_PULSE0; 	//  Pulse Register for CS 0
+	AT91_REG	 SMC_CYCLE0; 	//  Cycle Register for CS 0
+	AT91_REG	 SMC_CTRL0; 	//  Control Register for CS 0
+	AT91_REG	 SMC_SETUP1; 	//  Setup Register for CS 1
+	AT91_REG	 SMC_PULSE1; 	//  Pulse Register for CS 1
+	AT91_REG	 SMC_CYCLE1; 	//  Cycle Register for CS 1
+	AT91_REG	 SMC_CTRL1; 	//  Control Register for CS 1
+	AT91_REG	 SMC_SETUP2; 	//  Setup Register for CS 2
+	AT91_REG	 SMC_PULSE2; 	//  Pulse Register for CS 2
+	AT91_REG	 SMC_CYCLE2; 	//  Cycle Register for CS 2
+	AT91_REG	 SMC_CTRL2; 	//  Control Register for CS 2
+	AT91_REG	 SMC_SETUP3; 	//  Setup Register for CS 3
+	AT91_REG	 SMC_PULSE3; 	//  Pulse Register for CS 3
+	AT91_REG	 SMC_CYCLE3; 	//  Cycle Register for CS 3
+	AT91_REG	 SMC_CTRL3; 	//  Control Register for CS 3
+	AT91_REG	 SMC_SETUP4; 	//  Setup Register for CS 4
+	AT91_REG	 SMC_PULSE4; 	//  Pulse Register for CS 4
+	AT91_REG	 SMC_CYCLE4; 	//  Cycle Register for CS 4
+	AT91_REG	 SMC_CTRL4; 	//  Control Register for CS 4
+	AT91_REG	 SMC_SETUP5; 	//  Setup Register for CS 5
+	AT91_REG	 SMC_PULSE5; 	//  Pulse Register for CS 5
+	AT91_REG	 SMC_CYCLE5; 	//  Cycle Register for CS 5
+	AT91_REG	 SMC_CTRL5; 	//  Control Register for CS 5
+	AT91_REG	 SMC_SETUP6; 	//  Setup Register for CS 6
+	AT91_REG	 SMC_PULSE6; 	//  Pulse Register for CS 6
+	AT91_REG	 SMC_CYCLE6; 	//  Cycle Register for CS 6
+	AT91_REG	 SMC_CTRL6; 	//  Control Register for CS 6
+	AT91_REG	 SMC_SETUP7; 	//  Setup Register for CS 7
+	AT91_REG	 SMC_PULSE7; 	//  Pulse Register for CS 7
+	AT91_REG	 SMC_CYCLE7; 	//  Cycle Register for CS 7
+	AT91_REG	 SMC_CTRL7; 	//  Control Register for CS 7
+} AT91S_SMC, *AT91PS_SMC;
+#else
+#define SETUP0          (AT91_CAST(AT91_REG *) 	0x00000000) // (SETUP0)  Setup Register for CS 0
+#define PULSE0          (AT91_CAST(AT91_REG *) 	0x00000004) // (PULSE0)  Pulse Register for CS 0
+#define CYCLE0          (AT91_CAST(AT91_REG *) 	0x00000008) // (CYCLE0)  Cycle Register for CS 0
+#define CTRL0           (AT91_CAST(AT91_REG *) 	0x0000000C) // (CTRL0)  Control Register for CS 0
+#define SETUP1          (AT91_CAST(AT91_REG *) 	0x00000010) // (SETUP1)  Setup Register for CS 1
+#define PULSE1          (AT91_CAST(AT91_REG *) 	0x00000014) // (PULSE1)  Pulse Register for CS 1
+#define CYCLE1          (AT91_CAST(AT91_REG *) 	0x00000018) // (CYCLE1)  Cycle Register for CS 1
+#define CTRL1           (AT91_CAST(AT91_REG *) 	0x0000001C) // (CTRL1)  Control Register for CS 1
+#define SETUP2          (AT91_CAST(AT91_REG *) 	0x00000020) // (SETUP2)  Setup Register for CS 2
+#define PULSE2          (AT91_CAST(AT91_REG *) 	0x00000024) // (PULSE2)  Pulse Register for CS 2
+#define CYCLE2          (AT91_CAST(AT91_REG *) 	0x00000028) // (CYCLE2)  Cycle Register for CS 2
+#define CTRL2           (AT91_CAST(AT91_REG *) 	0x0000002C) // (CTRL2)  Control Register for CS 2
+#define SETUP3          (AT91_CAST(AT91_REG *) 	0x00000030) // (SETUP3)  Setup Register for CS 3
+#define PULSE3          (AT91_CAST(AT91_REG *) 	0x00000034) // (PULSE3)  Pulse Register for CS 3
+#define CYCLE3          (AT91_CAST(AT91_REG *) 	0x00000038) // (CYCLE3)  Cycle Register for CS 3
+#define CTRL3           (AT91_CAST(AT91_REG *) 	0x0000003C) // (CTRL3)  Control Register for CS 3
+#define SETUP4          (AT91_CAST(AT91_REG *) 	0x00000040) // (SETUP4)  Setup Register for CS 4
+#define PULSE4          (AT91_CAST(AT91_REG *) 	0x00000044) // (PULSE4)  Pulse Register for CS 4
+#define CYCLE4          (AT91_CAST(AT91_REG *) 	0x00000048) // (CYCLE4)  Cycle Register for CS 4
+#define CTRL4           (AT91_CAST(AT91_REG *) 	0x0000004C) // (CTRL4)  Control Register for CS 4
+#define SETUP5          (AT91_CAST(AT91_REG *) 	0x00000050) // (SETUP5)  Setup Register for CS 5
+#define PULSE5          (AT91_CAST(AT91_REG *) 	0x00000054) // (PULSE5)  Pulse Register for CS 5
+#define CYCLE5          (AT91_CAST(AT91_REG *) 	0x00000058) // (CYCLE5)  Cycle Register for CS 5
+#define CTRL5           (AT91_CAST(AT91_REG *) 	0x0000005C) // (CTRL5)  Control Register for CS 5
+#define SETUP6          (AT91_CAST(AT91_REG *) 	0x00000060) // (SETUP6)  Setup Register for CS 6
+#define PULSE6          (AT91_CAST(AT91_REG *) 	0x00000064) // (PULSE6)  Pulse Register for CS 6
+#define CYCLE6          (AT91_CAST(AT91_REG *) 	0x00000068) // (CYCLE6)  Cycle Register for CS 6
+#define CTRL6           (AT91_CAST(AT91_REG *) 	0x0000006C) // (CTRL6)  Control Register for CS 6
+#define SETUP7          (AT91_CAST(AT91_REG *) 	0x00000070) // (SETUP7)  Setup Register for CS 7
+#define PULSE7          (AT91_CAST(AT91_REG *) 	0x00000074) // (PULSE7)  Pulse Register for CS 7
+#define CYCLE7          (AT91_CAST(AT91_REG *) 	0x00000078) // (CYCLE7)  Cycle Register for CS 7
+#define CTRL7           (AT91_CAST(AT91_REG *) 	0x0000007C) // (CTRL7)  Control Register for CS 7
+
+#endif
+// -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x -------- 
+#define AT91C_SMC_NWESETUP    (0x3F <<  0) // (SMC) NWE Setup Length
+#define AT91C_SMC_NCSSETUPWR  (0x3F <<  8) // (SMC) NCS Setup Length in WRite Access
+#define AT91C_SMC_NRDSETUP    (0x3F << 16) // (SMC) NRD Setup Length
+#define AT91C_SMC_NCSSETUPRD  (0x3F << 24) // (SMC) NCS Setup Length in ReaD Access
+// -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x -------- 
+#define AT91C_SMC_NWEPULSE    (0x7F <<  0) // (SMC) NWE Pulse Length
+#define AT91C_SMC_NCSPULSEWR  (0x7F <<  8) // (SMC) NCS Pulse Length in WRite Access
+#define AT91C_SMC_NRDPULSE    (0x7F << 16) // (SMC) NRD Pulse Length
+#define AT91C_SMC_NCSPULSERD  (0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access
+// -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x -------- 
+#define AT91C_SMC_NWECYCLE    (0x1FF <<  0) // (SMC) Total Write Cycle Length
+#define AT91C_SMC_NRDCYCLE    (0x1FF << 16) // (SMC) Total Read Cycle Length
+// -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x -------- 
+#define AT91C_SMC_READMODE    (0x1 <<  0) // (SMC) Read Mode
+#define AT91C_SMC_WRITEMODE   (0x1 <<  1) // (SMC) Write Mode
+#define AT91C_SMC_NWAITM      (0x3 <<  4) // (SMC) NWAIT Mode
+#define 	AT91C_SMC_NWAITM_NWAIT_DISABLE        (0x0 <<  4) // (SMC) External NWAIT disabled.
+#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN  (0x2 <<  4) // (SMC) External NWAIT enabled in frozen mode.
+#define 	AT91C_SMC_NWAITM_NWAIT_ENABLE_READY   (0x3 <<  4) // (SMC) External NWAIT enabled in ready mode.
+#define AT91C_SMC_BAT         (0x1 <<  8) // (SMC) Byte Access Type
+#define 	AT91C_SMC_BAT_BYTE_SELECT          (0x0 <<  8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
+#define 	AT91C_SMC_BAT_BYTE_WRITE           (0x1 <<  8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
+#define AT91C_SMC_DBW         (0x3 << 12) // (SMC) Data Bus Width
+#define 	AT91C_SMC_DBW_WIDTH_EIGTH_BITS     (0x0 << 12) // (SMC) 8 bits.
+#define 	AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS   (0x1 << 12) // (SMC) 16 bits.
+#define 	AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (SMC) 32 bits.
+#define AT91C_SMC_TDF         (0xF << 16) // (SMC) Data Float Time.
+#define AT91C_SMC_TDFEN       (0x1 << 20) // (SMC) TDF Enabled.
+#define AT91C_SMC_PMEN        (0x1 << 24) // (SMC) Page Mode Enabled.
+#define AT91C_SMC_PS          (0x3 << 28) // (SMC) Page Size
+#define 	AT91C_SMC_PS_SIZE_FOUR_BYTES      (0x0 << 28) // (SMC) 4 bytes.
+#define 	AT91C_SMC_PS_SIZE_EIGHT_BYTES     (0x1 << 28) // (SMC) 8 bytes.
+#define 	AT91C_SMC_PS_SIZE_SIXTEEN_BYTES   (0x2 << 28) // (SMC) 16 bytes.
+#define 	AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (SMC) 32 bytes.
+// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x -------- 
+// -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x -------- 
+// -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x -------- 
+// -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x -------- 
+// -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR AHB Matrix Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_MATRIX {
+	AT91_REG	 MATRIX_MCFG0; 	//  Master Configuration Register 0 (ram96k)     
+	AT91_REG	 MATRIX_MCFG1; 	//  Master Configuration Register 1 (rom)    
+	AT91_REG	 MATRIX_MCFG2; 	//  Master Configuration Register 2 (hperiphs) 
+	AT91_REG	 MATRIX_MCFG3; 	//  Master Configuration Register 3 (ebi)
+	AT91_REG	 MATRIX_MCFG4; 	//  Master Configuration Register 4 (bridge)    
+	AT91_REG	 MATRIX_MCFG5; 	//  Master Configuration Register 5 (mailbox)    
+	AT91_REG	 MATRIX_MCFG6; 	//  Master Configuration Register 6 (ram16k)  
+	AT91_REG	 MATRIX_MCFG7; 	//  Master Configuration Register 7 (teak_prog)     
+	AT91_REG	 Reserved0[8]; 	// 
+	AT91_REG	 MATRIX_SCFG0; 	//  Slave Configuration Register 0 (ram96k)     
+	AT91_REG	 MATRIX_SCFG1; 	//  Slave Configuration Register 1 (rom)    
+	AT91_REG	 MATRIX_SCFG2; 	//  Slave Configuration Register 2 (hperiphs) 
+	AT91_REG	 MATRIX_SCFG3; 	//  Slave Configuration Register 3 (ebi)
+	AT91_REG	 MATRIX_SCFG4; 	//  Slave Configuration Register 4 (bridge)    
+	AT91_REG	 Reserved1[11]; 	// 
+	AT91_REG	 MATRIX_PRAS0; 	//  PRAS0 (ram0) 
+	AT91_REG	 MATRIX_PRBS0; 	//  PRBS0 (ram0) 
+	AT91_REG	 MATRIX_PRAS1; 	//  PRAS1 (ram1) 
+	AT91_REG	 MATRIX_PRBS1; 	//  PRBS1 (ram1) 
+	AT91_REG	 MATRIX_PRAS2; 	//  PRAS2 (ram2) 
+	AT91_REG	 MATRIX_PRBS2; 	//  PRBS2 (ram2) 
+	AT91_REG	 MATRIX_PRAS3; 	//  PRAS3 : usb_dev_hs
+	AT91_REG	 MATRIX_PRBS3; 	//  PRBS3 : usb_dev_hs
+	AT91_REG	 MATRIX_PRAS4; 	//  PRAS4 : ebi
+	AT91_REG	 MATRIX_PRBS4; 	//  PRBS4 : ebi
+	AT91_REG	 Reserved2[22]; 	// 
+	AT91_REG	 MATRIX_MRCR; 	//  Master Remp Control Register 
+	AT91_REG	 Reserved3[6]; 	// 
+	AT91_REG	 MATRIX_EBI; 	//  Slave 3 (ebi) Special Function Register
+	AT91_REG	 Reserved4[3]; 	// 
+	AT91_REG	 MATRIX_TEAKCFG; 	//  Slave 7 (teak_prog) Special Function Register
+	AT91_REG	 Reserved5[51]; 	// 
+	AT91_REG	 MATRIX_VERSION; 	//  Version Register
+} AT91S_MATRIX, *AT91PS_MATRIX;
+#else
+#define MATRIX_MCFG0    (AT91_CAST(AT91_REG *) 	0x00000000) // (MATRIX_MCFG0)  Master Configuration Register 0 (ram96k)     
+#define MATRIX_MCFG1    (AT91_CAST(AT91_REG *) 	0x00000004) // (MATRIX_MCFG1)  Master Configuration Register 1 (rom)    
+#define MATRIX_MCFG2    (AT91_CAST(AT91_REG *) 	0x00000008) // (MATRIX_MCFG2)  Master Configuration Register 2 (hperiphs) 
+#define MATRIX_MCFG3    (AT91_CAST(AT91_REG *) 	0x0000000C) // (MATRIX_MCFG3)  Master Configuration Register 3 (ebi)
+#define MATRIX_MCFG4    (AT91_CAST(AT91_REG *) 	0x00000010) // (MATRIX_MCFG4)  Master Configuration Register 4 (bridge)    
+#define MATRIX_MCFG5    (AT91_CAST(AT91_REG *) 	0x00000014) // (MATRIX_MCFG5)  Master Configuration Register 5 (mailbox)    
+#define MATRIX_MCFG6    (AT91_CAST(AT91_REG *) 	0x00000018) // (MATRIX_MCFG6)  Master Configuration Register 6 (ram16k)  
+#define MATRIX_MCFG7    (AT91_CAST(AT91_REG *) 	0x0000001C) // (MATRIX_MCFG7)  Master Configuration Register 7 (teak_prog)     
+#define MATRIX_SCFG0    (AT91_CAST(AT91_REG *) 	0x00000040) // (MATRIX_SCFG0)  Slave Configuration Register 0 (ram96k)     
+#define MATRIX_SCFG1    (AT91_CAST(AT91_REG *) 	0x00000044) // (MATRIX_SCFG1)  Slave Configuration Register 1 (rom)    
+#define MATRIX_SCFG2    (AT91_CAST(AT91_REG *) 	0x00000048) // (MATRIX_SCFG2)  Slave Configuration Register 2 (hperiphs) 
+#define MATRIX_SCFG3    (AT91_CAST(AT91_REG *) 	0x0000004C) // (MATRIX_SCFG3)  Slave Configuration Register 3 (ebi)
+#define MATRIX_SCFG4    (AT91_CAST(AT91_REG *) 	0x00000050) // (MATRIX_SCFG4)  Slave Configuration Register 4 (bridge)    
+#define MATRIX_PRAS0    (AT91_CAST(AT91_REG *) 	0x00000080) // (MATRIX_PRAS0)  PRAS0 (ram0) 
+#define MATRIX_PRBS0    (AT91_CAST(AT91_REG *) 	0x00000084) // (MATRIX_PRBS0)  PRBS0 (ram0) 
+#define MATRIX_PRAS1    (AT91_CAST(AT91_REG *) 	0x00000088) // (MATRIX_PRAS1)  PRAS1 (ram1) 
+#define MATRIX_PRBS1    (AT91_CAST(AT91_REG *) 	0x0000008C) // (MATRIX_PRBS1)  PRBS1 (ram1) 
+#define MATRIX_PRAS2    (AT91_CAST(AT91_REG *) 	0x00000090) // (MATRIX_PRAS2)  PRAS2 (ram2) 
+#define MATRIX_PRBS2    (AT91_CAST(AT91_REG *) 	0x00000094) // (MATRIX_PRBS2)  PRBS2 (ram2) 
+#define MATRIX_PRAS3    (AT91_CAST(AT91_REG *) 	0x00000098) // (MATRIX_PRAS3)  PRAS3 : usb_dev_hs
+#define MATRIX_PRBS3    (AT91_CAST(AT91_REG *) 	0x0000009C) // (MATRIX_PRBS3)  PRBS3 : usb_dev_hs
+#define MATRIX_PRAS4    (AT91_CAST(AT91_REG *) 	0x000000A0) // (MATRIX_PRAS4)  PRAS4 : ebi
+#define MATRIX_PRBS4    (AT91_CAST(AT91_REG *) 	0x000000A4) // (MATRIX_PRBS4)  PRBS4 : ebi
+#define MATRIX_MRCR     (AT91_CAST(AT91_REG *) 	0x00000100) // (MATRIX_MRCR)  Master Remp Control Register 
+#define MATRIX_EBI      (AT91_CAST(AT91_REG *) 	0x0000011C) // (MATRIX_EBI)  Slave 3 (ebi) Special Function Register
+#define MATRIX_TEAKCFG  (AT91_CAST(AT91_REG *) 	0x0000012C) // (MATRIX_TEAKCFG)  Slave 7 (teak_prog) Special Function Register
+#define MATRIX_VERSION  (AT91_CAST(AT91_REG *) 	0x000001FC) // (MATRIX_VERSION)  Version Register
+
+#endif
+// -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 -------- 
+#define AT91C_MATRIX_SLOT_CYCLE (0xFF <<  0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst
+#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type
+#define 	AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR           (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
+#define 	AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR         (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
+#define 	AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR        (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
+#define AT91C_MATRIX_FIXED_DEFMSTR0 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3                (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_LCDC                 (0x3 << 18) // (MATRIX) LCDC Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR0_DMA                  (0x4 << 18) // (MATRIX) DMA Master is Default Master
+// -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 -------- 
+#define AT91C_MATRIX_FIXED_DEFMSTR1 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3                (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR1_LCDC                 (0x3 << 18) // (MATRIX) LCDC Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR1_DMA                  (0x4 << 18) // (MATRIX) DMA Master is Default Master
+// -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 -------- 
+#define AT91C_MATRIX_FIXED_DEFMSTR2 (0x1 << 18) // (MATRIX) Fixed Index of Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+// -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 -------- 
+#define AT91C_MATRIX_FIXED_DEFMSTR3 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3                (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR3_LCDC                 (0x3 << 18) // (MATRIX) LCDC Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR3_DMA                  (0x4 << 18) // (MATRIX) DMA Master is Default Master
+// -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 -------- 
+#define AT91C_MATRIX_FIXED_DEFMSTR4 (0x3 << 18) // (MATRIX) Fixed Index of Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I              (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D              (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+#define 	AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3                (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
+// -------- MATRIX_PRAS0 : (MATRIX Offset: 0x80) PRAS0 Register -------- 
+#define AT91C_MATRIX_M0PR     (0x3 <<  0) // (MATRIX) ARM926EJ-S Instruction priority
+#define AT91C_MATRIX_M1PR     (0x3 <<  4) // (MATRIX) ARM926EJ-S Data priority
+#define AT91C_MATRIX_M2PR     (0x3 <<  8) // (MATRIX) PDC priority
+#define AT91C_MATRIX_M3PR     (0x3 << 12) // (MATRIX) LCDC priority
+#define AT91C_MATRIX_M4PR     (0x3 << 16) // (MATRIX) 2DGC priority
+#define AT91C_MATRIX_M5PR     (0x3 << 20) // (MATRIX) ISI priority
+#define AT91C_MATRIX_M6PR     (0x3 << 24) // (MATRIX) DMA priority
+#define AT91C_MATRIX_M7PR     (0x3 << 28) // (MATRIX) EMAC priority
+// -------- MATRIX_PRBS0 : (MATRIX Offset: 0x84) PRBS0 Register -------- 
+#define AT91C_MATRIX_M8PR     (0x3 <<  0) // (MATRIX) USB priority
+// -------- MATRIX_PRAS1 : (MATRIX Offset: 0x88) PRAS1 Register -------- 
+// -------- MATRIX_PRBS1 : (MATRIX Offset: 0x8c) PRBS1 Register -------- 
+// -------- MATRIX_PRAS2 : (MATRIX Offset: 0x90) PRAS2 Register -------- 
+// -------- MATRIX_PRBS2 : (MATRIX Offset: 0x94) PRBS2 Register -------- 
+// -------- MATRIX_PRAS3 : (MATRIX Offset: 0x98) PRAS3 Register -------- 
+// -------- MATRIX_PRBS3 : (MATRIX Offset: 0x9c) PRBS3 Register -------- 
+// -------- MATRIX_PRAS4 : (MATRIX Offset: 0xa0) PRAS4 Register -------- 
+// -------- MATRIX_PRBS4 : (MATRIX Offset: 0xa4) PRBS4 Register -------- 
+// -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register -------- 
+#define AT91C_MATRIX_RCA926I  (0x1 <<  0) // (MATRIX) Remap Command for ARM926EJ-S Instruction Master
+#define AT91C_MATRIX_RCA926D  (0x1 <<  1) // (MATRIX) Remap Command for ARM926EJ-S Data Master
+// -------- MATRIX_EBI : (MATRIX Offset: 0x11c) EBI (Slave 3) Special Function Register -------- 
+#define AT91C_MATRIX_CS1A     (0x1 <<  1) // (MATRIX) Chip Select 1 Assignment
+#define 	AT91C_MATRIX_CS1A_SMC                  (0x0 <<  1) // (MATRIX) Chip Select 1 is assigned to the Static Memory Controller.
+#define 	AT91C_MATRIX_CS1A_SDRAMC               (0x1 <<  1) // (MATRIX) Chip Select 1 is assigned to the SDRAM Controller.
+#define AT91C_MATRIX_CS3A     (0x1 <<  3) // (MATRIX) Chip Select 3 Assignment
+#define 	AT91C_MATRIX_CS3A_SMC                  (0x0 <<  3) // (MATRIX) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
+#define 	AT91C_MATRIX_CS3A_SM                   (0x1 <<  3) // (MATRIX) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
+#define AT91C_MATRIX_CS4A     (0x1 <<  4) // (MATRIX) Chip Select 4 Assignment
+#define 	AT91C_MATRIX_CS4A_SMC                  (0x0 <<  4) // (MATRIX) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
+#define 	AT91C_MATRIX_CS4A_CF                   (0x1 <<  4) // (MATRIX) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
+#define AT91C_MATRIX_CS5A     (0x1 <<  5) // (MATRIX) Chip Select 5 Assignment
+#define 	AT91C_MATRIX_CS5A_SMC                  (0x0 <<  5) // (MATRIX) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
+#define 	AT91C_MATRIX_CS5A_CF                   (0x1 <<  5) // (MATRIX) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
+#define AT91C_MATRIX_DBPUC    (0x1 <<  8) // (MATRIX) Data Bus Pull-up Configuration
+// -------- MATRIX_TEAKCFG : (MATRIX Offset: 0x12c) Slave 7 Special Function Register -------- 
+#define AT91C_TEAK_PROGRAM_ACCESS (0x1 <<  0) // (MATRIX) TEAK program memory access from AHB
+#define 	AT91C_TEAK_PROGRAM_ACCESS_DISABLED             (0x0) // (MATRIX) TEAK program access disabled
+#define 	AT91C_TEAK_PROGRAM_ACCESS_ENABLED              (0x1) // (MATRIX) TEAK program access enabled
+#define AT91C_TEAK_BOOT       (0x1 <<  1) // (MATRIX) TEAK program start from boot routine
+#define 	AT91C_TEAK_BOOT_DISABLED             (0x0 <<  1) // (MATRIX) TEAK program starts from boot routine disabled
+#define 	AT91C_TEAK_BOOT_ENABLED              (0x1 <<  1) // (MATRIX) TEAK program starts from boot routine enabled
+#define AT91C_TEAK_NRESET     (0x1 <<  2) // (MATRIX) active low TEAK reset
+#define 	AT91C_TEAK_NRESET_ENABLED              (0x0 <<  2) // (MATRIX) active low TEAK reset enabled
+#define 	AT91C_TEAK_NRESET_DISABLED             (0x1 <<  2) // (MATRIX) active low TEAK reset disabled
+#define AT91C_TEAK_LVECTORP   (0x3FFFF << 14) // (MATRIX) boot routine start address
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Chip Configuration Registers
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_CCFG {
+	AT91_REG	 Reserved0[3]; 	// 
+	AT91_REG	 CCFG_EBICSA; 	//  EBI Chip Select Assignement Register
+	AT91_REG	 Reserved1[55]; 	// 
+	AT91_REG	 CCFG_MATRIXVERSION; 	//  Version Register
+} AT91S_CCFG, *AT91PS_CCFG;
+#else
+#define CCFG_EBICSA     (AT91_CAST(AT91_REG *) 	0x0000000C) // (CCFG_EBICSA)  EBI Chip Select Assignement Register
+#define CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 	0x000000EC) // (CCFG_MATRIXVERSION)  Version Register
+
+#endif
+// -------- CCFG_EBICSA : (CCFG Offset: 0xc) EBI Chip Select Assignement Register -------- 
+#define AT91C_EBI_CS1A        (0x1 <<  1) // (CCFG) Chip Select 1 Assignment
+#define 	AT91C_EBI_CS1A_SMC                  (0x0 <<  1) // (CCFG) Chip Select 1 is assigned to the Static Memory Controller.
+#define 	AT91C_EBI_CS1A_SDRAMC               (0x1 <<  1) // (CCFG) Chip Select 1 is assigned to the SDRAM Controller.
+#define AT91C_EBI_CS3A        (0x1 <<  3) // (CCFG) Chip Select 3 Assignment
+#define 	AT91C_EBI_CS3A_SMC                  (0x0 <<  3) // (CCFG) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
+#define 	AT91C_EBI_CS3A_SM                   (0x1 <<  3) // (CCFG) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
+#define AT91C_EBI_CS4A        (0x1 <<  4) // (CCFG) Chip Select 4 Assignment
+#define 	AT91C_EBI_CS4A_SMC                  (0x0 <<  4) // (CCFG) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
+#define 	AT91C_EBI_CS4A_CF                   (0x1 <<  4) // (CCFG) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
+#define AT91C_EBI_CS5A        (0x1 <<  5) // (CCFG) Chip Select 5 Assignment
+#define 	AT91C_EBI_CS5A_SMC                  (0x0 <<  5) // (CCFG) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
+#define 	AT91C_EBI_CS5A_CF                   (0x1 <<  5) // (CCFG) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
+#define AT91C_EBI_DBPUC       (0x1 <<  8) // (CCFG) Data Bus Pull-up Configuration
+#define AT91C_EBI_SUPPLY      (0x1 << 16) // (CCFG) EBI supply selection
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PDC {
+	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
+	AT91_REG	 PDC_RCR; 	// Receive Counter Register
+	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
+	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+#else
+#define PDC_RPR         (AT91_CAST(AT91_REG *) 	0x00000000) // (PDC_RPR) Receive Pointer Register
+#define PDC_RCR         (AT91_CAST(AT91_REG *) 	0x00000004) // (PDC_RCR) Receive Counter Register
+#define PDC_TPR         (AT91_CAST(AT91_REG *) 	0x00000008) // (PDC_TPR) Transmit Pointer Register
+#define PDC_TCR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (PDC_TCR) Transmit Counter Register
+#define PDC_RNPR        (AT91_CAST(AT91_REG *) 	0x00000010) // (PDC_RNPR) Receive Next Pointer Register
+#define PDC_RNCR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PDC_RNCR) Receive Next Counter Register
+#define PDC_TNPR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
+#define PDC_TNCR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
+#define PDC_PTCR        (AT91_CAST(AT91_REG *) 	0x00000020) // (PDC_PTCR) PDC Transfer Control Register
+#define PDC_PTSR        (AT91_CAST(AT91_REG *) 	0x00000024) // (PDC_PTSR) PDC Transfer Status Register
+
+#endif
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN       (0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS      (0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN       (0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS      (0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_DBGU {
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved0[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved1[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+#else
+#define DBGU_CR         (AT91_CAST(AT91_REG *) 	0x00000000) // (DBGU_CR) Control Register
+#define DBGU_MR         (AT91_CAST(AT91_REG *) 	0x00000004) // (DBGU_MR) Mode Register
+#define DBGU_IER        (AT91_CAST(AT91_REG *) 	0x00000008) // (DBGU_IER) Interrupt Enable Register
+#define DBGU_IDR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (DBGU_IDR) Interrupt Disable Register
+#define DBGU_IMR        (AT91_CAST(AT91_REG *) 	0x00000010) // (DBGU_IMR) Interrupt Mask Register
+#define DBGU_CSR        (AT91_CAST(AT91_REG *) 	0x00000014) // (DBGU_CSR) Channel Status Register
+#define DBGU_RHR        (AT91_CAST(AT91_REG *) 	0x00000018) // (DBGU_RHR) Receiver Holding Register
+#define DBGU_THR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (DBGU_THR) Transmitter Holding Register
+#define DBGU_BRGR       (AT91_CAST(AT91_REG *) 	0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
+#define DBGU_CIDR       (AT91_CAST(AT91_REG *) 	0x00000040) // (DBGU_CIDR) Chip ID Register
+#define DBGU_EXID       (AT91_CAST(AT91_REG *) 	0x00000044) // (DBGU_EXID) Chip ID Extension Register
+#define DBGU_FNTR       (AT91_CAST(AT91_REG *) 	0x00000048) // (DBGU_FNTR) Force NTRST Register
+
+#endif
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX        (0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX        (0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN         (0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS        (0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN         (0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS        (0x1 <<  7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA       (0x1 <<  8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR          (0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE       (0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY        (0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY        (0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX        (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX        (0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE         (0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME        (0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE         (0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY      (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE       (0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF       (0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX      (0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX      (0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST  (0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_AIC {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+#else
+#define AIC_SMR         (AT91_CAST(AT91_REG *) 	0x00000000) // (AIC_SMR) Source Mode Register
+#define AIC_SVR         (AT91_CAST(AT91_REG *) 	0x00000080) // (AIC_SVR) Source Vector Register
+#define AIC_IVR         (AT91_CAST(AT91_REG *) 	0x00000100) // (AIC_IVR) IRQ Vector Register
+#define AIC_FVR         (AT91_CAST(AT91_REG *) 	0x00000104) // (AIC_FVR) FIQ Vector Register
+#define AIC_ISR         (AT91_CAST(AT91_REG *) 	0x00000108) // (AIC_ISR) Interrupt Status Register
+#define AIC_IPR         (AT91_CAST(AT91_REG *) 	0x0000010C) // (AIC_IPR) Interrupt Pending Register
+#define AIC_IMR         (AT91_CAST(AT91_REG *) 	0x00000110) // (AIC_IMR) Interrupt Mask Register
+#define AIC_CISR        (AT91_CAST(AT91_REG *) 	0x00000114) // (AIC_CISR) Core Interrupt Status Register
+#define AIC_IECR        (AT91_CAST(AT91_REG *) 	0x00000120) // (AIC_IECR) Interrupt Enable Command Register
+#define AIC_IDCR        (AT91_CAST(AT91_REG *) 	0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
+#define AIC_ICCR        (AT91_CAST(AT91_REG *) 	0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
+#define AIC_ISCR        (AT91_CAST(AT91_REG *) 	0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
+#define AIC_EOICR       (AT91_CAST(AT91_REG *) 	0x00000130) // (AIC_EOICR) End of Interrupt Command Register
+#define AIC_SPU         (AT91_CAST(AT91_REG *) 	0x00000134) // (AIC_SPU) Spurious Vector Register
+#define AIC_DCR         (AT91_CAST(AT91_REG *) 	0x00000138) // (AIC_DCR) Debug Control Register (Protect)
+#define AIC_FFER        (AT91_CAST(AT91_REG *) 	0x00000140) // (AIC_FFER) Fast Forcing Enable Register
+#define AIC_FFDR        (AT91_CAST(AT91_REG *) 	0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
+#define AIC_FFSR        (AT91_CAST(AT91_REG *) 	0x00000148) // (AIC_FFSR) Fast Forcing Status Register
+
+#endif
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR       (0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE     (0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  (0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   (0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       (0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    (0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ        (0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ        (0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT    (0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK    (0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PIO {
+	AT91_REG	 PIO_PER; 	// PIO Enable Register
+	AT91_REG	 PIO_PDR; 	// PIO Disable Register
+	AT91_REG	 PIO_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PIO_OER; 	// Output Enable Register
+	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIO_OSR; 	// Output Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PIO_SODR; 	// Set Output Data Register
+	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved3[1]; 	// 
+	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved4[1]; 	// 
+	AT91_REG	 PIO_ASR; 	// Select A Register
+	AT91_REG	 PIO_BSR; 	// Select B Register
+	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved5[9]; 	// 
+	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+#else
+#define PIO_PER         (AT91_CAST(AT91_REG *) 	0x00000000) // (PIO_PER) PIO Enable Register
+#define PIO_PDR         (AT91_CAST(AT91_REG *) 	0x00000004) // (PIO_PDR) PIO Disable Register
+#define PIO_PSR         (AT91_CAST(AT91_REG *) 	0x00000008) // (PIO_PSR) PIO Status Register
+#define PIO_OER         (AT91_CAST(AT91_REG *) 	0x00000010) // (PIO_OER) Output Enable Register
+#define PIO_ODR         (AT91_CAST(AT91_REG *) 	0x00000014) // (PIO_ODR) Output Disable Registerr
+#define PIO_OSR         (AT91_CAST(AT91_REG *) 	0x00000018) // (PIO_OSR) Output Status Register
+#define PIO_IFER        (AT91_CAST(AT91_REG *) 	0x00000020) // (PIO_IFER) Input Filter Enable Register
+#define PIO_IFDR        (AT91_CAST(AT91_REG *) 	0x00000024) // (PIO_IFDR) Input Filter Disable Register
+#define PIO_IFSR        (AT91_CAST(AT91_REG *) 	0x00000028) // (PIO_IFSR) Input Filter Status Register
+#define PIO_SODR        (AT91_CAST(AT91_REG *) 	0x00000030) // (PIO_SODR) Set Output Data Register
+#define PIO_CODR        (AT91_CAST(AT91_REG *) 	0x00000034) // (PIO_CODR) Clear Output Data Register
+#define PIO_ODSR        (AT91_CAST(AT91_REG *) 	0x00000038) // (PIO_ODSR) Output Data Status Register
+#define PIO_PDSR        (AT91_CAST(AT91_REG *) 	0x0000003C) // (PIO_PDSR) Pin Data Status Register
+#define PIO_IER         (AT91_CAST(AT91_REG *) 	0x00000040) // (PIO_IER) Interrupt Enable Register
+#define PIO_IDR         (AT91_CAST(AT91_REG *) 	0x00000044) // (PIO_IDR) Interrupt Disable Register
+#define PIO_IMR         (AT91_CAST(AT91_REG *) 	0x00000048) // (PIO_IMR) Interrupt Mask Register
+#define PIO_ISR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (PIO_ISR) Interrupt Status Register
+#define PIO_MDER        (AT91_CAST(AT91_REG *) 	0x00000050) // (PIO_MDER) Multi-driver Enable Register
+#define PIO_MDDR        (AT91_CAST(AT91_REG *) 	0x00000054) // (PIO_MDDR) Multi-driver Disable Register
+#define PIO_MDSR        (AT91_CAST(AT91_REG *) 	0x00000058) // (PIO_MDSR) Multi-driver Status Register
+#define PIO_PPUDR       (AT91_CAST(AT91_REG *) 	0x00000060) // (PIO_PPUDR) Pull-up Disable Register
+#define PIO_PPUER       (AT91_CAST(AT91_REG *) 	0x00000064) // (PIO_PPUER) Pull-up Enable Register
+#define PIO_PPUSR       (AT91_CAST(AT91_REG *) 	0x00000068) // (PIO_PPUSR) Pull-up Status Register
+#define PIO_ASR         (AT91_CAST(AT91_REG *) 	0x00000070) // (PIO_ASR) Select A Register
+#define PIO_BSR         (AT91_CAST(AT91_REG *) 	0x00000074) // (PIO_BSR) Select B Register
+#define PIO_ABSR        (AT91_CAST(AT91_REG *) 	0x00000078) // (PIO_ABSR) AB Select Status Register
+#define PIO_OWER        (AT91_CAST(AT91_REG *) 	0x000000A0) // (PIO_OWER) Output Write Enable Register
+#define PIO_OWDR        (AT91_CAST(AT91_REG *) 	0x000000A4) // (PIO_OWDR) Output Write Disable Register
+#define PIO_OWSR        (AT91_CAST(AT91_REG *) 	0x000000A8) // (PIO_OWSR) Output Write Status Register
+
+#endif
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Embedded Flash Controller 2.0
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_EFC {
+	AT91_REG	 EFC_FMR; 	// EFC Flash Mode Register
+	AT91_REG	 EFC_FCR; 	// EFC Flash Command Register
+	AT91_REG	 EFC_FSR; 	// EFC Flash Status Register
+	AT91_REG	 EFC_FRR; 	// EFC Flash Result Register
+	AT91_REG	 EFC_FVR; 	// EFC Flash Version Register
+} AT91S_EFC, *AT91PS_EFC;
+#else
+#define EFC_FMR         (AT91_CAST(AT91_REG *) 	0x00000000) // (EFC_FMR) EFC Flash Mode Register
+#define EFC_FCR         (AT91_CAST(AT91_REG *) 	0x00000004) // (EFC_FCR) EFC Flash Command Register
+#define EFC_FSR         (AT91_CAST(AT91_REG *) 	0x00000008) // (EFC_FSR) EFC Flash Status Register
+#define EFC_FRR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (EFC_FRR) EFC Flash Result Register
+#define EFC_FVR         (AT91_CAST(AT91_REG *) 	0x00000010) // (EFC_FVR) EFC Flash Version Register
+
+#endif
+// -------- EFC_FMR : (EFC Offset: 0x0) EFC Flash Mode Register -------- 
+#define AT91C_EFC_FRDY        (0x1 <<  0) // (EFC) Ready Interrupt Enable
+#define AT91C_EFC_FWS         (0xF <<  8) // (EFC) Flash Wait State.
+#define 	AT91C_EFC_FWS_0WS                  (0x0 <<  8) // (EFC) 0 Wait State
+#define 	AT91C_EFC_FWS_1WS                  (0x1 <<  8) // (EFC) 1 Wait State
+#define 	AT91C_EFC_FWS_2WS                  (0x2 <<  8) // (EFC) 2 Wait States
+#define 	AT91C_EFC_FWS_3WS                  (0x3 <<  8) // (EFC) 3 Wait States
+// -------- EFC_FCR : (EFC Offset: 0x4) EFC Flash Command Register -------- 
+#define AT91C_EFC_FCMD        (0xFF <<  0) // (EFC) Flash Command
+#define 	AT91C_EFC_FCMD_GETD                 (0x0) // (EFC) Get Flash Descriptor
+#define 	AT91C_EFC_FCMD_WP                   (0x1) // (EFC) Write Page
+#define 	AT91C_EFC_FCMD_WPL                  (0x2) // (EFC) Write Page and Lock
+#define 	AT91C_EFC_FCMD_EWP                  (0x3) // (EFC) Erase Page and Write Page
+#define 	AT91C_EFC_FCMD_EWPL                 (0x4) // (EFC) Erase Page and Write Page then Lock
+#define 	AT91C_EFC_FCMD_EA                   (0x5) // (EFC) Erase All
+#define 	AT91C_EFC_FCMD_EPL                  (0x6) // (EFC) Erase Plane
+#define 	AT91C_EFC_FCMD_EPA                  (0x7) // (EFC) Erase Pages
+#define 	AT91C_EFC_FCMD_SLB                  (0x8) // (EFC) Set Lock Bit
+#define 	AT91C_EFC_FCMD_CLB                  (0x9) // (EFC) Clear Lock Bit
+#define 	AT91C_EFC_FCMD_GLB                  (0xA) // (EFC) Get Lock Bit
+#define 	AT91C_EFC_FCMD_SFB                  (0xB) // (EFC) Set Fuse Bit
+#define 	AT91C_EFC_FCMD_CFB                  (0xC) // (EFC) Clear Fuse Bit
+#define 	AT91C_EFC_FCMD_GFB                  (0xD) // (EFC) Get Fuse Bit
+#define AT91C_EFC_FARG        (0xFFFF <<  8) // (EFC) Flash Command Argument
+#define AT91C_EFC_FKEY        (0xFF << 24) // (EFC) Flash Writing Protection Key
+// -------- EFC_FSR : (EFC Offset: 0x8) EFC Flash Status Register -------- 
+#define AT91C_EFC_FRDY_S      (0x1 <<  0) // (EFC) Flash Ready Status
+#define AT91C_EFC_FCMDE       (0x1 <<  1) // (EFC) Flash Command Error Status
+#define AT91C_EFC_LOCKE       (0x1 <<  2) // (EFC) Flash Lock Error Status
+// -------- EFC_FRR : (EFC Offset: 0xc) EFC Flash Result Register -------- 
+#define AT91C_EFC_FVALUE      (0x0 <<  0) // (EFC) Flash Result Value
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_CKGR {
+	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
+	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 CKGR_PLLAR; 	// PLL A Register
+	AT91_REG	 CKGR_PLLBR; 	// PLL B Register
+} AT91S_CKGR, *AT91PS_CKGR;
+#else
+#define CKGR_MOR        (AT91_CAST(AT91_REG *) 	0x00000000) // (CKGR_MOR) Main Oscillator Register
+#define CKGR_MCFR       (AT91_CAST(AT91_REG *) 	0x00000004) // (CKGR_MCFR) Main Clock  Frequency Register
+#define CKGR_PLLAR      (AT91_CAST(AT91_REG *) 	0x00000008) // (CKGR_PLLAR) PLL A Register
+#define CKGR_PLLBR      (AT91_CAST(AT91_REG *) 	0x0000000C) // (CKGR_PLLBR) PLL B Register
+
+#endif
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN     (0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS  (0x1 <<  1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT    (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF      (0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY    (0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- 
+#define AT91C_CKGR_DIVA       (0xFF <<  0) // (CKGR) Divider A Selected
+#define 	AT91C_CKGR_DIVA_0                    (0x0) // (CKGR) Divider A output is 0
+#define 	AT91C_CKGR_DIVA_BYPASS               (0x1) // (CKGR) Divider A is bypassed
+#define AT91C_CKGR_PLLACOUNT  (0x3F <<  8) // (CKGR) PLL A Counter
+#define AT91C_CKGR_OUTA       (0x3 << 14) // (CKGR) PLL A Output Frequency Range
+#define 	AT91C_CKGR_OUTA_0                    (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define 	AT91C_CKGR_OUTA_1                    (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define 	AT91C_CKGR_OUTA_2                    (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define 	AT91C_CKGR_OUTA_3                    (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define AT91C_CKGR_MULA       (0x7FF << 16) // (CKGR) PLL A Multiplier
+#define AT91C_CKGR_SRCA       (0x1 << 29) // (CKGR) 
+// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- 
+#define AT91C_CKGR_DIVB       (0xFF <<  0) // (CKGR) Divider B Selected
+#define 	AT91C_CKGR_DIVB_0                    (0x0) // (CKGR) Divider B output is 0
+#define 	AT91C_CKGR_DIVB_BYPASS               (0x1) // (CKGR) Divider B is bypassed
+#define AT91C_CKGR_PLLBCOUNT  (0x3F <<  8) // (CKGR) PLL B Counter
+#define AT91C_CKGR_OUTB       (0x3 << 14) // (CKGR) PLL B Output Frequency Range
+#define 	AT91C_CKGR_OUTB_0                    (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define 	AT91C_CKGR_OUTB_1                    (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define 	AT91C_CKGR_OUTB_2                    (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define 	AT91C_CKGR_OUTB_3                    (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define AT91C_CKGR_MULB       (0x7FF << 16) // (CKGR) PLL B Multiplier
+#define AT91C_CKGR_USBDIV     (0x3 << 28) // (CKGR) Divider for USB Clocks
+#define 	AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define 	AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define 	AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PMC {
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 PMC_PLLAR; 	// PLL A Register
+	AT91_REG	 PMC_PLLBR; 	// PLL B Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved2[3]; 	// 
+	AT91_REG	 PMC_PCKR[8]; 	// Programmable Clock Register
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+#else
+#define PMC_SCER        (AT91_CAST(AT91_REG *) 	0x00000000) // (PMC_SCER) System Clock Enable Register
+#define PMC_SCDR        (AT91_CAST(AT91_REG *) 	0x00000004) // (PMC_SCDR) System Clock Disable Register
+#define PMC_SCSR        (AT91_CAST(AT91_REG *) 	0x00000008) // (PMC_SCSR) System Clock Status Register
+#define PMC_PCER        (AT91_CAST(AT91_REG *) 	0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
+#define PMC_PCDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
+#define PMC_PCSR        (AT91_CAST(AT91_REG *) 	0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
+#define PMC_MCKR        (AT91_CAST(AT91_REG *) 	0x00000030) // (PMC_MCKR) Master Clock Register
+#define PMC_PCKR        (AT91_CAST(AT91_REG *) 	0x00000040) // (PMC_PCKR) Programmable Clock Register
+#define PMC_IER         (AT91_CAST(AT91_REG *) 	0x00000060) // (PMC_IER) Interrupt Enable Register
+#define PMC_IDR         (AT91_CAST(AT91_REG *) 	0x00000064) // (PMC_IDR) Interrupt Disable Register
+#define PMC_SR          (AT91_CAST(AT91_REG *) 	0x00000068) // (PMC_SR) Status Register
+#define PMC_IMR         (AT91_CAST(AT91_REG *) 	0x0000006C) // (PMC_IMR) Interrupt Mask Register
+
+#endif
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_PCK         (0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_OTG         (0x1 <<  5) // (PMC) USB OTG Clock
+#define AT91C_PMC_UHP         (0x1 <<  6) // (PMC) USB Host Port Clock
+#define AT91C_PMC_UDP         (0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0        (0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1        (0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2        (0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3        (0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- 
+// -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register -------- 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS         (0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLLA_CLK             (0x2) // (PMC) Clock from PLL A is selected
+#define 	AT91C_PMC_CSS_PLLB_CLK             (0x3) // (PMC) Clock from PLL B is selected
+#define AT91C_PMC_PRES        (0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
+#define AT91C_PMC_MDIV        (0x3 <<  8) // (PMC) Master Clock Division
+#define 	AT91C_PMC_MDIV_1                    (0x0 <<  8) // (PMC) The master clock and the processor clock are the same
+#define 	AT91C_PMC_MDIV_2                    (0x1 <<  8) // (PMC) The processor clock is twice as fast as the master clock
+#define 	AT91C_PMC_MDIV_3                    (0x2 <<  8) // (PMC) The processor clock is four times faster than the master clock
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS       (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCKA       (0x1 <<  1) // (PMC) PLL A Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCKB       (0x1 <<  2) // (PMC) PLL B Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY      (0x1 <<  3) // (PMC) Master Clock Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY     (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY     (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY     (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY     (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_RSTC {
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
+#else
+#define RSTC_RCR        (AT91_CAST(AT91_REG *) 	0x00000000) // (RSTC_RCR) Reset Control Register
+#define RSTC_RSR        (AT91_CAST(AT91_REG *) 	0x00000004) // (RSTC_RSR) Reset Status Register
+#define RSTC_RMR        (AT91_CAST(AT91_REG *) 	0x00000008) // (RSTC_RMR) Reset Mode Register
+
+#endif
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_RSTC_PROCRST    (0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_RSTC_ICERST     (0x1 <<  1) // (RSTC) ICE Interface Reset
+#define AT91C_RSTC_PERRST     (0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST     (0x1 <<  3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY        (0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_RSTC_URSTS      (0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_RSTC_RSTTYP     (0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_RSTC_RSTTYP_GENERAL              (0x0 <<  8) // (RSTC) General reset. Both VDDCORE and VDDBU rising.
+#define 	AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define AT91C_RSTC_NRSTL      (0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP      (0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_RSTC_URSTEN     (0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN    (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL      (0xF <<  8) // (RSTC) User Reset Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Shut Down Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SHDWC {
+	AT91_REG	 SHDWC_SHCR; 	// Shut Down Control Register
+	AT91_REG	 SHDWC_SHMR; 	// Shut Down Mode Register
+	AT91_REG	 SHDWC_SHSR; 	// Shut Down Status Register
+} AT91S_SHDWC, *AT91PS_SHDWC;
+#else
+#define SHDWC_SHCR      (AT91_CAST(AT91_REG *) 	0x00000000) // (SHDWC_SHCR) Shut Down Control Register
+#define SHDWC_SHMR      (AT91_CAST(AT91_REG *) 	0x00000004) // (SHDWC_SHMR) Shut Down Mode Register
+#define SHDWC_SHSR      (AT91_CAST(AT91_REG *) 	0x00000008) // (SHDWC_SHSR) Shut Down Status Register
+
+#endif
+// -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register -------- 
+#define AT91C_SHDWC_SHDW      (0x1 <<  0) // (SHDWC) Processor Reset
+#define AT91C_SHDWC_KEY       (0xFF << 24) // (SHDWC) Shut down KEY Password
+// -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register -------- 
+#define AT91C_SHDWC_WKMODE0   (0x3 <<  0) // (SHDWC) Wake Up 0 Mode Selection
+#define 	AT91C_SHDWC_WKMODE0_NONE                 (0x0) // (SHDWC) None. No detection is performed on the wake up input.
+#define 	AT91C_SHDWC_WKMODE0_HIGH                 (0x1) // (SHDWC) High Level.
+#define 	AT91C_SHDWC_WKMODE0_LOW                  (0x2) // (SHDWC) Low Level.
+#define 	AT91C_SHDWC_WKMODE0_ANYLEVEL             (0x3) // (SHDWC) Any level change.
+#define AT91C_SHDWC_CPTWK0    (0xF <<  4) // (SHDWC) Counter On Wake Up 0
+#define AT91C_SHDWC_WKMODE1   (0x3 <<  8) // (SHDWC) Wake Up 1 Mode Selection
+#define 	AT91C_SHDWC_WKMODE1_NONE                 (0x0 <<  8) // (SHDWC) None. No detection is performed on the wake up input.
+#define 	AT91C_SHDWC_WKMODE1_HIGH                 (0x1 <<  8) // (SHDWC) High Level.
+#define 	AT91C_SHDWC_WKMODE1_LOW                  (0x2 <<  8) // (SHDWC) Low Level.
+#define 	AT91C_SHDWC_WKMODE1_ANYLEVEL             (0x3 <<  8) // (SHDWC) Any level change.
+#define AT91C_SHDWC_CPTWK1    (0xF << 12) // (SHDWC) Counter On Wake Up 1
+#define AT91C_SHDWC_RTTWKEN   (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable
+#define AT91C_SHDWC_RTCWKEN   (0x1 << 17) // (SHDWC) Real Time Clock Wake Up Enable
+// -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register -------- 
+#define AT91C_SHDWC_WAKEUP0   (0x1 <<  0) // (SHDWC) Wake Up 0 Status
+#define AT91C_SHDWC_WAKEUP1   (0x1 <<  1) // (SHDWC) Wake Up 1 Status
+#define AT91C_SHDWC_FWKUP     (0x1 <<  2) // (SHDWC) Force Wake Up Status
+#define AT91C_SHDWC_RTTWK     (0x1 << 16) // (SHDWC) Real Time Timer wake Up
+#define AT91C_SHDWC_RTCWK     (0x1 << 17) // (SHDWC) Real Time Clock wake Up
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_RTTC {
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+#else
+#define RTTC_RTMR       (AT91_CAST(AT91_REG *) 	0x00000000) // (RTTC_RTMR) Real-time Mode Register
+#define RTTC_RTAR       (AT91_CAST(AT91_REG *) 	0x00000004) // (RTTC_RTAR) Real-time Alarm Register
+#define RTTC_RTVR       (AT91_CAST(AT91_REG *) 	0x00000008) // (RTTC_RTVR) Real-time Value Register
+#define RTTC_RTSR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (RTTC_RTSR) Real-time Status Register
+
+#endif
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_RTTC_RTPRES     (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN     (0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN  (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST     (0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_RTTC_ALMV       (0x0 <<  0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_RTTC_CRTV       (0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_RTTC_ALMS       (0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC     (0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PITC {
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+#else
+#define PITC_PIMR       (AT91_CAST(AT91_REG *) 	0x00000000) // (PITC_PIMR) Period Interval Mode Register
+#define PITC_PISR       (AT91_CAST(AT91_REG *) 	0x00000004) // (PITC_PISR) Period Interval Status Register
+#define PITC_PIVR       (AT91_CAST(AT91_REG *) 	0x00000008) // (PITC_PIVR) Period Interval Value Register
+#define PITC_PIIR       (AT91_CAST(AT91_REG *) 	0x0000000C) // (PITC_PIIR) Period Interval Image Register
+
+#endif
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_PITC_PIV        (0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN      (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN     (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_PITC_PITS       (0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_PITC_CPIV       (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT      (0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_WDTC {
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+#else
+#define WDTC_WDCR       (AT91_CAST(AT91_REG *) 	0x00000000) // (WDTC_WDCR) Watchdog Control Register
+#define WDTC_WDMR       (AT91_CAST(AT91_REG *) 	0x00000004) // (WDTC_WDMR) Watchdog Mode Register
+#define WDTC_WDSR       (AT91_CAST(AT91_REG *) 	0x00000008) // (WDTC_WDSR) Watchdog Status Register
+
+#endif
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_WDTC_WDRSTT     (0x1 <<  0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY        (0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_WDTC_WDV        (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN     (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN    (0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC    (0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS      (0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD        (0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT   (0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT  (0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_WDTC_WDUNF      (0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR      (0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_TC {
+	AT91_REG	 TC_CCR; 	// Channel Control Register
+	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TC_CV; 	// Counter Value
+	AT91_REG	 TC_RA; 	// Register A
+	AT91_REG	 TC_RB; 	// Register B
+	AT91_REG	 TC_RC; 	// Register C
+	AT91_REG	 TC_SR; 	// Status Register
+	AT91_REG	 TC_IER; 	// Interrupt Enable Register
+	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+#else
+#define TC_CCR          (AT91_CAST(AT91_REG *) 	0x00000000) // (TC_CCR) Channel Control Register
+#define TC_CMR          (AT91_CAST(AT91_REG *) 	0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
+#define TC_CV           (AT91_CAST(AT91_REG *) 	0x00000010) // (TC_CV) Counter Value
+#define TC_RA           (AT91_CAST(AT91_REG *) 	0x00000014) // (TC_RA) Register A
+#define TC_RB           (AT91_CAST(AT91_REG *) 	0x00000018) // (TC_RB) Register B
+#define TC_RC           (AT91_CAST(AT91_REG *) 	0x0000001C) // (TC_RC) Register C
+#define TC_SR           (AT91_CAST(AT91_REG *) 	0x00000020) // (TC_SR) Status Register
+#define TC_IER          (AT91_CAST(AT91_REG *) 	0x00000024) // (TC_IER) Interrupt Enable Register
+#define TC_IDR          (AT91_CAST(AT91_REG *) 	0x00000028) // (TC_IDR) Interrupt Disable Register
+#define TC_IMR          (AT91_CAST(AT91_REG *) 	0x0000002C) // (TC_IMR) Interrupt Mask Register
+
+#endif
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN        (0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS       (0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG        (0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS         (0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI         (0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST        (0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP      (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS       (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS       (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG      (0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG      (0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT         (0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG       (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG       (0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL      (0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG       (0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE         (0x1 << 15) // (TC) 
+#define AT91C_TC_ACPA         (0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA         (0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC         (0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB         (0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT        (0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG       (0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB         (0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC         (0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT        (0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG       (0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS        (0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS        (0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS         (0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS         (0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS         (0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS        (0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS        (0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRGS        (0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA       (0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA        (0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB        (0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_TCB {
+	AT91S_TC	 TCB_TC0; 	// TC Channel 0
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91S_TC	 TCB_TC1; 	// TC Channel 1
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91S_TC	 TCB_TC2; 	// TC Channel 2
+	AT91_REG	 Reserved2[4]; 	// 
+	AT91_REG	 TCB_BCR; 	// TC Block Control Register
+	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+#else
+#define TCB_BCR         (AT91_CAST(AT91_REG *) 	0x000000C0) // (TCB_BCR) TC Block Control Register
+#define TCB_BMR         (AT91_CAST(AT91_REG *) 	0x000000C4) // (TCB_BMR) TC Block Mode Register
+
+#endif
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC        (0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S     (0x3 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S     (0x3 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S     (0x3 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Multimedia Card Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_MCI {
+	AT91_REG	 MCI_CR; 	// MCI Control Register
+	AT91_REG	 MCI_MR; 	// MCI Mode Register
+	AT91_REG	 MCI_DTOR; 	// MCI Data Timeout Register
+	AT91_REG	 MCI_SDCR; 	// MCI SD Card Register
+	AT91_REG	 MCI_ARGR; 	// MCI Argument Register
+	AT91_REG	 MCI_CMDR; 	// MCI Command Register
+	AT91_REG	 MCI_BLKR; 	// MCI Block Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 MCI_RSPR[4]; 	// MCI Response Register
+	AT91_REG	 MCI_RDR; 	// MCI Receive Data Register
+	AT91_REG	 MCI_TDR; 	// MCI Transmit Data Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 MCI_SR; 	// MCI Status Register
+	AT91_REG	 MCI_IER; 	// MCI Interrupt Enable Register
+	AT91_REG	 MCI_IDR; 	// MCI Interrupt Disable Register
+	AT91_REG	 MCI_IMR; 	// MCI Interrupt Mask Register
+	AT91_REG	 Reserved2[43]; 	// 
+	AT91_REG	 MCI_VR; 	// MCI Version Register
+	AT91_REG	 MCI_RPR; 	// Receive Pointer Register
+	AT91_REG	 MCI_RCR; 	// Receive Counter Register
+	AT91_REG	 MCI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 MCI_TCR; 	// Transmit Counter Register
+	AT91_REG	 MCI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 MCI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 MCI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 MCI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 MCI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 MCI_PTSR; 	// PDC Transfer Status Register
+} AT91S_MCI, *AT91PS_MCI;
+#else
+#define MCI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (MCI_CR) MCI Control Register
+#define MCI_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (MCI_MR) MCI Mode Register
+#define MCI_DTOR        (AT91_CAST(AT91_REG *) 	0x00000008) // (MCI_DTOR) MCI Data Timeout Register
+#define MCI_SDCR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (MCI_SDCR) MCI SD Card Register
+#define MCI_ARGR        (AT91_CAST(AT91_REG *) 	0x00000010) // (MCI_ARGR) MCI Argument Register
+#define MCI_CMDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (MCI_CMDR) MCI Command Register
+#define MCI_BLKR        (AT91_CAST(AT91_REG *) 	0x00000018) // (MCI_BLKR) MCI Block Register
+#define MCI_RSPR        (AT91_CAST(AT91_REG *) 	0x00000020) // (MCI_RSPR) MCI Response Register
+#define MCI_RDR         (AT91_CAST(AT91_REG *) 	0x00000030) // (MCI_RDR) MCI Receive Data Register
+#define MCI_TDR         (AT91_CAST(AT91_REG *) 	0x00000034) // (MCI_TDR) MCI Transmit Data Register
+#define MCI_SR          (AT91_CAST(AT91_REG *) 	0x00000040) // (MCI_SR) MCI Status Register
+#define MCI_IER         (AT91_CAST(AT91_REG *) 	0x00000044) // (MCI_IER) MCI Interrupt Enable Register
+#define MCI_IDR         (AT91_CAST(AT91_REG *) 	0x00000048) // (MCI_IDR) MCI Interrupt Disable Register
+#define MCI_IMR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (MCI_IMR) MCI Interrupt Mask Register
+#define MCI_VR          (AT91_CAST(AT91_REG *) 	0x000000FC) // (MCI_VR) MCI Version Register
+
+#endif
+// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- 
+#define AT91C_MCI_MCIEN       (0x1 <<  0) // (MCI) Multimedia Interface Enable
+#define AT91C_MCI_MCIDIS      (0x1 <<  1) // (MCI) Multimedia Interface Disable
+#define AT91C_MCI_PWSEN       (0x1 <<  2) // (MCI) Power Save Mode Enable
+#define AT91C_MCI_PWSDIS      (0x1 <<  3) // (MCI) Power Save Mode Disable
+#define AT91C_MCI_SWRST       (0x1 <<  7) // (MCI) MCI Software reset
+// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- 
+#define AT91C_MCI_CLKDIV      (0xFF <<  0) // (MCI) Clock Divider
+#define AT91C_MCI_PWSDIV      (0x7 <<  8) // (MCI) Power Saving Divider
+#define AT91C_MCI_RDPROOF     (0x1 << 11) // (MCI) Read Proof Enable
+#define AT91C_MCI_WRPROOF     (0x1 << 12) // (MCI) Write Proof Enable
+#define AT91C_MCI_PDCFBYTE    (0x1 << 13) // (MCI) PDC Force Byte Transfer
+#define AT91C_MCI_PDCPADV     (0x1 << 14) // (MCI) PDC Padding Value
+#define AT91C_MCI_PDCMODE     (0x1 << 15) // (MCI) PDC Oriented Mode
+#define AT91C_MCI_BLKLEN      (0xFFFF << 16) // (MCI) Data Block Length
+// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- 
+#define AT91C_MCI_DTOCYC      (0xF <<  0) // (MCI) Data Timeout Cycle Number
+#define AT91C_MCI_DTOMUL      (0x7 <<  4) // (MCI) Data Timeout Multiplier
+#define 	AT91C_MCI_DTOMUL_1                    (0x0 <<  4) // (MCI) DTOCYC x 1
+#define 	AT91C_MCI_DTOMUL_16                   (0x1 <<  4) // (MCI) DTOCYC x 16
+#define 	AT91C_MCI_DTOMUL_128                  (0x2 <<  4) // (MCI) DTOCYC x 128
+#define 	AT91C_MCI_DTOMUL_256                  (0x3 <<  4) // (MCI) DTOCYC x 256
+#define 	AT91C_MCI_DTOMUL_1024                 (0x4 <<  4) // (MCI) DTOCYC x 1024
+#define 	AT91C_MCI_DTOMUL_4096                 (0x5 <<  4) // (MCI) DTOCYC x 4096
+#define 	AT91C_MCI_DTOMUL_65536                (0x6 <<  4) // (MCI) DTOCYC x 65536
+#define 	AT91C_MCI_DTOMUL_1048576              (0x7 <<  4) // (MCI) DTOCYC x 1048576
+// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- 
+#define AT91C_MCI_SCDSEL      (0x3 <<  0) // (MCI) SD Card Selector
+#define AT91C_MCI_SCDBUS      (0x1 <<  7) // (MCI) SDCard/SDIO Bus Width
+// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- 
+#define AT91C_MCI_CMDNB       (0x3F <<  0) // (MCI) Command Number
+#define AT91C_MCI_RSPTYP      (0x3 <<  6) // (MCI) Response Type
+#define 	AT91C_MCI_RSPTYP_NO                   (0x0 <<  6) // (MCI) No response
+#define 	AT91C_MCI_RSPTYP_48                   (0x1 <<  6) // (MCI) 48-bit response
+#define 	AT91C_MCI_RSPTYP_136                  (0x2 <<  6) // (MCI) 136-bit response
+#define AT91C_MCI_SPCMD       (0x7 <<  8) // (MCI) Special CMD
+#define 	AT91C_MCI_SPCMD_NONE                 (0x0 <<  8) // (MCI) Not a special CMD
+#define 	AT91C_MCI_SPCMD_INIT                 (0x1 <<  8) // (MCI) Initialization CMD
+#define 	AT91C_MCI_SPCMD_SYNC                 (0x2 <<  8) // (MCI) Synchronized CMD
+#define 	AT91C_MCI_SPCMD_IT_CMD               (0x4 <<  8) // (MCI) Interrupt command
+#define 	AT91C_MCI_SPCMD_IT_REP               (0x5 <<  8) // (MCI) Interrupt response
+#define AT91C_MCI_OPDCMD      (0x1 << 11) // (MCI) Open Drain Command
+#define AT91C_MCI_MAXLAT      (0x1 << 12) // (MCI) Maximum Latency for Command to respond
+#define AT91C_MCI_TRCMD       (0x3 << 16) // (MCI) Transfer CMD
+#define 	AT91C_MCI_TRCMD_NO                   (0x0 << 16) // (MCI) No transfer
+#define 	AT91C_MCI_TRCMD_START                (0x1 << 16) // (MCI) Start transfer
+#define 	AT91C_MCI_TRCMD_STOP                 (0x2 << 16) // (MCI) Stop transfer
+#define AT91C_MCI_TRDIR       (0x1 << 18) // (MCI) Transfer Direction
+#define AT91C_MCI_TRTYP       (0x7 << 19) // (MCI) Transfer Type
+#define 	AT91C_MCI_TRTYP_BLOCK                (0x0 << 19) // (MCI) MMC/SDCard Single Block Transfer type
+#define 	AT91C_MCI_TRTYP_MULTIPLE             (0x1 << 19) // (MCI) MMC/SDCard Multiple Block transfer type
+#define 	AT91C_MCI_TRTYP_STREAM               (0x2 << 19) // (MCI) MMC Stream transfer type
+#define 	AT91C_MCI_TRTYP_SDIO_BYTE            (0x4 << 19) // (MCI) SDIO Byte transfer type
+#define 	AT91C_MCI_TRTYP_SDIO_BLOCK           (0x5 << 19) // (MCI) SDIO Block transfer type
+#define AT91C_MCI_IOSPCMD     (0x3 << 24) // (MCI) SDIO Special Command
+#define 	AT91C_MCI_IOSPCMD_NONE                 (0x0 << 24) // (MCI) NOT a special command
+#define 	AT91C_MCI_IOSPCMD_SUSPEND              (0x1 << 24) // (MCI) SDIO Suspend Command
+#define 	AT91C_MCI_IOSPCMD_RESUME               (0x2 << 24) // (MCI) SDIO Resume Command
+// -------- MCI_BLKR : (MCI Offset: 0x18) MCI Block Register -------- 
+#define AT91C_MCI_BCNT        (0xFFFF <<  0) // (MCI) MMC/SDIO Block Count / SDIO Byte Count
+// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- 
+#define AT91C_MCI_CMDRDY      (0x1 <<  0) // (MCI) Command Ready flag
+#define AT91C_MCI_RXRDY       (0x1 <<  1) // (MCI) RX Ready flag
+#define AT91C_MCI_TXRDY       (0x1 <<  2) // (MCI) TX Ready flag
+#define AT91C_MCI_BLKE        (0x1 <<  3) // (MCI) Data Block Transfer Ended flag
+#define AT91C_MCI_DTIP        (0x1 <<  4) // (MCI) Data Transfer in Progress flag
+#define AT91C_MCI_NOTBUSY     (0x1 <<  5) // (MCI) Data Line Not Busy flag
+#define AT91C_MCI_ENDRX       (0x1 <<  6) // (MCI) End of RX Buffer flag
+#define AT91C_MCI_ENDTX       (0x1 <<  7) // (MCI) End of TX Buffer flag
+#define AT91C_MCI_SDIOIRQA    (0x1 <<  8) // (MCI) SDIO Interrupt for Slot A
+#define AT91C_MCI_SDIOIRQB    (0x1 <<  9) // (MCI) SDIO Interrupt for Slot B
+#define AT91C_MCI_SDIOIRQC    (0x1 << 10) // (MCI) SDIO Interrupt for Slot C
+#define AT91C_MCI_SDIOIRQD    (0x1 << 11) // (MCI) SDIO Interrupt for Slot D
+#define AT91C_MCI_RXBUFF      (0x1 << 14) // (MCI) RX Buffer Full flag
+#define AT91C_MCI_TXBUFE      (0x1 << 15) // (MCI) TX Buffer Empty flag
+#define AT91C_MCI_RINDE       (0x1 << 16) // (MCI) Response Index Error flag
+#define AT91C_MCI_RDIRE       (0x1 << 17) // (MCI) Response Direction Error flag
+#define AT91C_MCI_RCRCE       (0x1 << 18) // (MCI) Response CRC Error flag
+#define AT91C_MCI_RENDE       (0x1 << 19) // (MCI) Response End Bit Error flag
+#define AT91C_MCI_RTOE        (0x1 << 20) // (MCI) Response Time-out Error flag
+#define AT91C_MCI_DCRCE       (0x1 << 21) // (MCI) data CRC Error flag
+#define AT91C_MCI_DTOE        (0x1 << 22) // (MCI) Data timeout Error flag
+#define AT91C_MCI_OVRE        (0x1 << 30) // (MCI) Overrun flag
+#define AT91C_MCI_UNRE        (0x1 << 31) // (MCI) Underrun flag
+// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- 
+// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- 
+// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_TWI {
+	AT91_REG	 TWI_CR; 	// Control Register
+	AT91_REG	 TWI_MMR; 	// Master Mode Register
+	AT91_REG	 TWI_SMR; 	// Slave Mode Register
+	AT91_REG	 TWI_IADR; 	// Internal Address Register
+	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
+	AT91_REG	 Reserved0[3]; 	// 
+	AT91_REG	 TWI_SR; 	// Status Register
+	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
+	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TWI_RHR; 	// Receive Holding Register
+	AT91_REG	 TWI_THR; 	// Transmit Holding Register
+	AT91_REG	 Reserved1[50]; 	// 
+	AT91_REG	 TWI_RPR; 	// Receive Pointer Register
+	AT91_REG	 TWI_RCR; 	// Receive Counter Register
+	AT91_REG	 TWI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 TWI_TCR; 	// Transmit Counter Register
+	AT91_REG	 TWI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 TWI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 TWI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 TWI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 TWI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 TWI_PTSR; 	// PDC Transfer Status Register
+} AT91S_TWI, *AT91PS_TWI;
+#else
+#define TWI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (TWI_CR) Control Register
+#define TWI_MMR         (AT91_CAST(AT91_REG *) 	0x00000004) // (TWI_MMR) Master Mode Register
+#define TWI_SMR         (AT91_CAST(AT91_REG *) 	0x00000008) // (TWI_SMR) Slave Mode Register
+#define TWI_IADR        (AT91_CAST(AT91_REG *) 	0x0000000C) // (TWI_IADR) Internal Address Register
+#define TWI_CWGR        (AT91_CAST(AT91_REG *) 	0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
+#define TWI_SR          (AT91_CAST(AT91_REG *) 	0x00000020) // (TWI_SR) Status Register
+#define TWI_IER         (AT91_CAST(AT91_REG *) 	0x00000024) // (TWI_IER) Interrupt Enable Register
+#define TWI_IDR         (AT91_CAST(AT91_REG *) 	0x00000028) // (TWI_IDR) Interrupt Disable Register
+#define TWI_IMR         (AT91_CAST(AT91_REG *) 	0x0000002C) // (TWI_IMR) Interrupt Mask Register
+#define TWI_RHR         (AT91_CAST(AT91_REG *) 	0x00000030) // (TWI_RHR) Receive Holding Register
+#define TWI_THR         (AT91_CAST(AT91_REG *) 	0x00000034) // (TWI_THR) Transmit Holding Register
+
+#endif
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START       (0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP        (0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN        (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS       (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SVEN        (0x1 <<  4) // (TWI) TWI Slave mode Enabled
+#define AT91C_TWI_SVDIS       (0x1 <<  5) // (TWI) TWI Slave mode Disabled
+#define AT91C_TWI_SWRST       (0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ      (0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD       (0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR        (0x7F << 16) // (TWI) Device Address
+// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- 
+#define AT91C_TWI_SADR        (0x7F << 16) // (TWI) Slave Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV       (0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV       (0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV       (0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP_SLAVE (0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_TXCOMP_MASTER (0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY       (0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY_MASTER (0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_TXRDY_SLAVE (0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_SVREAD      (0x1 <<  3) // (TWI) Slave READ (used only in Slave mode)
+#define AT91C_TWI_SVACC       (0x1 <<  4) // (TWI) Slave ACCess (used only in Slave mode)
+#define AT91C_TWI_GACC        (0x1 <<  5) // (TWI) General Call ACcess (used only in Slave mode)
+#define AT91C_TWI_OVRE        (0x1 <<  6) // (TWI) Overrun Error (used only in Master and Multi-master mode)
+#define AT91C_TWI_NACK_SLAVE  (0x1 <<  8) // (TWI) Not Acknowledged
+#define AT91C_TWI_NACK_MASTER (0x1 <<  8) // (TWI) Not Acknowledged
+#define AT91C_TWI_ARBLST_MULTI_MASTER (0x1 <<  9) // (TWI) Arbitration Lost (used only in Multimaster mode)
+#define AT91C_TWI_SCLWS       (0x1 << 10) // (TWI) Clock Wait State (used only in Slave mode)
+#define AT91C_TWI_EOSACC      (0x1 << 11) // (TWI) End Of Slave ACCess (used only in Slave mode)
+#define AT91C_TWI_ENDRX       (0x1 << 12) // (TWI) End of Receiver Transfer
+#define AT91C_TWI_ENDTX       (0x1 << 13) // (TWI) End of Receiver Transfer
+#define AT91C_TWI_RXBUFF      (0x1 << 14) // (TWI) RXBUFF Interrupt
+#define AT91C_TWI_TXBUFE      (0x1 << 15) // (TWI) TXBUFE Interrupt
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_USART {
+	AT91_REG	 US_CR; 	// Control Register
+	AT91_REG	 US_MR; 	// Mode Register
+	AT91_REG	 US_IER; 	// Interrupt Enable Register
+	AT91_REG	 US_IDR; 	// Interrupt Disable Register
+	AT91_REG	 US_IMR; 	// Interrupt Mask Register
+	AT91_REG	 US_CSR; 	// Channel Status Register
+	AT91_REG	 US_RHR; 	// Receiver Holding Register
+	AT91_REG	 US_THR; 	// Transmitter Holding Register
+	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
+	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
+	AT91_REG	 Reserved0[5]; 	// 
+	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
+	AT91_REG	 US_NER; 	// Nb Errors Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 US_IF; 	// IRDA_FILTER Register
+	AT91_REG	 Reserved2[44]; 	// 
+	AT91_REG	 US_RPR; 	// Receive Pointer Register
+	AT91_REG	 US_RCR; 	// Receive Counter Register
+	AT91_REG	 US_TPR; 	// Transmit Pointer Register
+	AT91_REG	 US_TCR; 	// Transmit Counter Register
+	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+#else
+#define US_CR           (AT91_CAST(AT91_REG *) 	0x00000000) // (US_CR) Control Register
+#define US_MR           (AT91_CAST(AT91_REG *) 	0x00000004) // (US_MR) Mode Register
+#define US_IER          (AT91_CAST(AT91_REG *) 	0x00000008) // (US_IER) Interrupt Enable Register
+#define US_IDR          (AT91_CAST(AT91_REG *) 	0x0000000C) // (US_IDR) Interrupt Disable Register
+#define US_IMR          (AT91_CAST(AT91_REG *) 	0x00000010) // (US_IMR) Interrupt Mask Register
+#define US_CSR          (AT91_CAST(AT91_REG *) 	0x00000014) // (US_CSR) Channel Status Register
+#define US_RHR          (AT91_CAST(AT91_REG *) 	0x00000018) // (US_RHR) Receiver Holding Register
+#define US_THR          (AT91_CAST(AT91_REG *) 	0x0000001C) // (US_THR) Transmitter Holding Register
+#define US_BRGR         (AT91_CAST(AT91_REG *) 	0x00000020) // (US_BRGR) Baud Rate Generator Register
+#define US_RTOR         (AT91_CAST(AT91_REG *) 	0x00000024) // (US_RTOR) Receiver Time-out Register
+#define US_TTGR         (AT91_CAST(AT91_REG *) 	0x00000028) // (US_TTGR) Transmitter Time-guard Register
+#define US_FIDI         (AT91_CAST(AT91_REG *) 	0x00000040) // (US_FIDI) FI_DI_Ratio Register
+#define US_NER          (AT91_CAST(AT91_REG *) 	0x00000044) // (US_NER) Nb Errors Register
+#define US_IF           (AT91_CAST(AT91_REG *) 	0x0000004C) // (US_IF) IRDA_FILTER Register
+
+#endif
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_STTBRK       (0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK       (0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO        (0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA        (0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT        (0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK      (0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO        (0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN        (0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS       (0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN        (0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS       (0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_USMODE       (0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS         (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL         (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC         (0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP       (0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF         (0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9        (0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO         (0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER         (0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK        (0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK       (0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER     (0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER       (0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK        (0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT      (0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION    (0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK         (0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC         (0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC        (0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC        (0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC        (0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+#define AT91C_US_RI           (0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR          (0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD          (0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS          (0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SSC {
+	AT91_REG	 SSC_CR; 	// Control Register
+	AT91_REG	 SSC_CMR; 	// Clock Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
+	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
+	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
+	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
+	AT91_REG	 SSC_RHR; 	// Receive Holding Register
+	AT91_REG	 SSC_THR; 	// Transmit Holding Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
+	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 SSC_SR; 	// Status Register
+	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
+	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved3[44]; 	// 
+	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
+	AT91_REG	 SSC_RCR; 	// Receive Counter Register
+	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
+	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+#else
+#define SSC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (SSC_CR) Control Register
+#define SSC_CMR         (AT91_CAST(AT91_REG *) 	0x00000004) // (SSC_CMR) Clock Mode Register
+#define SSC_RCMR        (AT91_CAST(AT91_REG *) 	0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
+#define SSC_RFMR        (AT91_CAST(AT91_REG *) 	0x00000014) // (SSC_RFMR) Receive Frame Mode Register
+#define SSC_TCMR        (AT91_CAST(AT91_REG *) 	0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
+#define SSC_TFMR        (AT91_CAST(AT91_REG *) 	0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
+#define SSC_RHR         (AT91_CAST(AT91_REG *) 	0x00000020) // (SSC_RHR) Receive Holding Register
+#define SSC_THR         (AT91_CAST(AT91_REG *) 	0x00000024) // (SSC_THR) Transmit Holding Register
+#define SSC_RSHR        (AT91_CAST(AT91_REG *) 	0x00000030) // (SSC_RSHR) Receive Sync Holding Register
+#define SSC_TSHR        (AT91_CAST(AT91_REG *) 	0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
+#define SSC_SR          (AT91_CAST(AT91_REG *) 	0x00000040) // (SSC_SR) Status Register
+#define SSC_IER         (AT91_CAST(AT91_REG *) 	0x00000044) // (SSC_IER) Interrupt Enable Register
+#define SSC_IDR         (AT91_CAST(AT91_REG *) 	0x00000048) // (SSC_IDR) Interrupt Disable Register
+#define SSC_IMR         (AT91_CAST(AT91_REG *) 	0x0000004C) // (SSC_IMR) Interrupt Mask Register
+
+#endif
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN        (0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS       (0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN        (0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS       (0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST       (0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS         (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO         (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI         (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START       (0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY      (0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD      (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN      (0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP        (0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF        (0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB       (0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN       (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS        (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE      (0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF      (0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN       (0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY       (0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY     (0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX       (0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE      (0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY       (0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN       (0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX       (0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF      (0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN       (0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN       (0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA       (0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA       (0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SPI {
+	AT91_REG	 SPI_CR; 	// Control Register
+	AT91_REG	 SPI_MR; 	// Mode Register
+	AT91_REG	 SPI_RDR; 	// Receive Data Register
+	AT91_REG	 SPI_TDR; 	// Transmit Data Register
+	AT91_REG	 SPI_SR; 	// Status Register
+	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
+	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
+	AT91_REG	 Reserved1[48]; 	// 
+	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
+	AT91_REG	 SPI_RCR; 	// Receive Counter Register
+	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
+	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+#else
+#define SPI_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (SPI_CR) Control Register
+#define SPI_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (SPI_MR) Mode Register
+#define SPI_RDR         (AT91_CAST(AT91_REG *) 	0x00000008) // (SPI_RDR) Receive Data Register
+#define SPI_TDR         (AT91_CAST(AT91_REG *) 	0x0000000C) // (SPI_TDR) Transmit Data Register
+#define SPI_SR          (AT91_CAST(AT91_REG *) 	0x00000010) // (SPI_SR) Status Register
+#define SPI_IER         (AT91_CAST(AT91_REG *) 	0x00000014) // (SPI_IER) Interrupt Enable Register
+#define SPI_IDR         (AT91_CAST(AT91_REG *) 	0x00000018) // (SPI_IDR) Interrupt Disable Register
+#define SPI_IMR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (SPI_IMR) Interrupt Mask Register
+#define SPI_CSR         (AT91_CAST(AT91_REG *) 	0x00000030) // (SPI_CSR) Chip Select Register
+
+#endif
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN       (0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS      (0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST       (0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER    (0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR        (0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS          (0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC      (0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV        (0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS     (0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB         (0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS         (0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS      (0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD          (0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD          (0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS        (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF        (0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE        (0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF        (0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES       (0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX       (0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX       (0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF      (0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE      (0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR        (0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY     (0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS      (0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL        (0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA       (0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT       (0x1 <<  3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS        (0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR        (0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS       (0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT      (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_ADC {
+	AT91_REG	 ADC_CR; 	// ADC Control Register
+	AT91_REG	 ADC_MR; 	// ADC Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
+	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
+	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
+	AT91_REG	 ADC_SR; 	// ADC Status Register
+	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
+	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
+	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
+	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
+	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
+	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
+	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
+	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
+	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
+	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
+	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
+	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
+	AT91_REG	 Reserved1[44]; 	// 
+	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
+	AT91_REG	 ADC_RCR; 	// Receive Counter Register
+	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
+	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
+#else
+#define ADC_CR          (AT91_CAST(AT91_REG *) 	0x00000000) // (ADC_CR) ADC Control Register
+#define ADC_MR          (AT91_CAST(AT91_REG *) 	0x00000004) // (ADC_MR) ADC Mode Register
+#define ADC_CHER        (AT91_CAST(AT91_REG *) 	0x00000010) // (ADC_CHER) ADC Channel Enable Register
+#define ADC_CHDR        (AT91_CAST(AT91_REG *) 	0x00000014) // (ADC_CHDR) ADC Channel Disable Register
+#define ADC_CHSR        (AT91_CAST(AT91_REG *) 	0x00000018) // (ADC_CHSR) ADC Channel Status Register
+#define ADC_SR          (AT91_CAST(AT91_REG *) 	0x0000001C) // (ADC_SR) ADC Status Register
+#define ADC_LCDR        (AT91_CAST(AT91_REG *) 	0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
+#define ADC_IER         (AT91_CAST(AT91_REG *) 	0x00000024) // (ADC_IER) ADC Interrupt Enable Register
+#define ADC_IDR         (AT91_CAST(AT91_REG *) 	0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
+#define ADC_IMR         (AT91_CAST(AT91_REG *) 	0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
+#define ADC_CDR0        (AT91_CAST(AT91_REG *) 	0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
+#define ADC_CDR1        (AT91_CAST(AT91_REG *) 	0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
+#define ADC_CDR2        (AT91_CAST(AT91_REG *) 	0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
+#define ADC_CDR3        (AT91_CAST(AT91_REG *) 	0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
+#define ADC_CDR4        (AT91_CAST(AT91_REG *) 	0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
+#define ADC_CDR5        (AT91_CAST(AT91_REG *) 	0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
+#define ADC_CDR6        (AT91_CAST(AT91_REG *) 	0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
+#define ADC_CDR7        (AT91_CAST(AT91_REG *) 	0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
+
+#endif
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+#define AT91C_ADC_SWRST       (0x1 <<  0) // (ADC) Software Reset
+#define AT91C_ADC_START       (0x1 <<  1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+#define AT91C_ADC_TRGEN       (0x1 <<  0) // (ADC) Trigger Enable
+#define 	AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define 	AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL      (0x7 <<  1) // (ADC) Trigger Selection
+#define 	AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
+#define 	AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
+#define 	AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
+#define 	AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
+#define 	AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
+#define 	AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
+#define 	AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES      (0x1 <<  4) // (ADC) Resolution.
+#define 	AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
+#define 	AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP       (0x1 <<  5) // (ADC) Sleep Mode
+#define 	AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
+#define 	AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL     (0x3F <<  8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP     (0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM       (0xF << 24) // (ADC) Sample & Hold Time
+// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+#define AT91C_ADC_CH0         (0x1 <<  0) // (ADC) Channel 0
+#define AT91C_ADC_CH1         (0x1 <<  1) // (ADC) Channel 1
+#define AT91C_ADC_CH2         (0x1 <<  2) // (ADC) Channel 2
+#define AT91C_ADC_CH3         (0x1 <<  3) // (ADC) Channel 3
+#define AT91C_ADC_CH4         (0x1 <<  4) // (ADC) Channel 4
+#define AT91C_ADC_CH5         (0x1 <<  5) // (ADC) Channel 5
+#define AT91C_ADC_CH6         (0x1 <<  6) // (ADC) Channel 6
+#define AT91C_ADC_CH7         (0x1 <<  7) // (ADC) Channel 7
+// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+#define AT91C_ADC_EOC0        (0x1 <<  0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1        (0x1 <<  1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2        (0x1 <<  2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3        (0x1 <<  3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4        (0x1 <<  4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5        (0x1 <<  5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6        (0x1 <<  6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7        (0x1 <<  7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0       (0x1 <<  8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1       (0x1 <<  9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2       (0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3       (0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4       (0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5       (0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6       (0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7       (0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY        (0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE       (0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX       (0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF      (0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+#define AT91C_ADC_LDATA       (0x3FF <<  0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+#define AT91C_ADC_DATA        (0x3FF <<  0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_EMAC {
+	AT91_REG	 EMAC_NCR; 	// Network Control Register
+	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
+	AT91_REG	 EMAC_NSR; 	// Network Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
+	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
+	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
+	AT91_REG	 EMAC_RSR; 	// Receive Status Register
+	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
+	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
+	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
+	AT91_REG	 EMAC_PTR; 	// Pause Time Register
+	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
+	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
+	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
+	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
+	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
+	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
+	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
+	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
+	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
+	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
+	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
+	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
+	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
+	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
+	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
+	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
+	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
+	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
+	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
+	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
+	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
+	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
+	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
+	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
+	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
+	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
+	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
+	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
+	AT91_REG	 Reserved1[13]; 	// 
+	AT91_REG	 EMAC_REV; 	// Revision Register
+} AT91S_EMAC, *AT91PS_EMAC;
+#else
+#define EMAC_NCR        (AT91_CAST(AT91_REG *) 	0x00000000) // (EMAC_NCR) Network Control Register
+#define EMAC_NCFGR      (AT91_CAST(AT91_REG *) 	0x00000004) // (EMAC_NCFGR) Network Configuration Register
+#define EMAC_NSR        (AT91_CAST(AT91_REG *) 	0x00000008) // (EMAC_NSR) Network Status Register
+#define EMAC_TSR        (AT91_CAST(AT91_REG *) 	0x00000014) // (EMAC_TSR) Transmit Status Register
+#define EMAC_RBQP       (AT91_CAST(AT91_REG *) 	0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer
+#define EMAC_TBQP       (AT91_CAST(AT91_REG *) 	0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer
+#define EMAC_RSR        (AT91_CAST(AT91_REG *) 	0x00000020) // (EMAC_RSR) Receive Status Register
+#define EMAC_ISR        (AT91_CAST(AT91_REG *) 	0x00000024) // (EMAC_ISR) Interrupt Status Register
+#define EMAC_IER        (AT91_CAST(AT91_REG *) 	0x00000028) // (EMAC_IER) Interrupt Enable Register
+#define EMAC_IDR        (AT91_CAST(AT91_REG *) 	0x0000002C) // (EMAC_IDR) Interrupt Disable Register
+#define EMAC_IMR        (AT91_CAST(AT91_REG *) 	0x00000030) // (EMAC_IMR) Interrupt Mask Register
+#define EMAC_MAN        (AT91_CAST(AT91_REG *) 	0x00000034) // (EMAC_MAN) PHY Maintenance Register
+#define EMAC_PTR        (AT91_CAST(AT91_REG *) 	0x00000038) // (EMAC_PTR) Pause Time Register
+#define EMAC_PFR        (AT91_CAST(AT91_REG *) 	0x0000003C) // (EMAC_PFR) Pause Frames received Register
+#define EMAC_FTO        (AT91_CAST(AT91_REG *) 	0x00000040) // (EMAC_FTO) Frames Transmitted OK Register
+#define EMAC_SCF        (AT91_CAST(AT91_REG *) 	0x00000044) // (EMAC_SCF) Single Collision Frame Register
+#define EMAC_MCF        (AT91_CAST(AT91_REG *) 	0x00000048) // (EMAC_MCF) Multiple Collision Frame Register
+#define EMAC_FRO        (AT91_CAST(AT91_REG *) 	0x0000004C) // (EMAC_FRO) Frames Received OK Register
+#define EMAC_FCSE       (AT91_CAST(AT91_REG *) 	0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register
+#define EMAC_ALE        (AT91_CAST(AT91_REG *) 	0x00000054) // (EMAC_ALE) Alignment Error Register
+#define EMAC_DTF        (AT91_CAST(AT91_REG *) 	0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register
+#define EMAC_LCOL       (AT91_CAST(AT91_REG *) 	0x0000005C) // (EMAC_LCOL) Late Collision Register
+#define EMAC_ECOL       (AT91_CAST(AT91_REG *) 	0x00000060) // (EMAC_ECOL) Excessive Collision Register
+#define EMAC_TUND       (AT91_CAST(AT91_REG *) 	0x00000064) // (EMAC_TUND) Transmit Underrun Error Register
+#define EMAC_CSE        (AT91_CAST(AT91_REG *) 	0x00000068) // (EMAC_CSE) Carrier Sense Error Register
+#define EMAC_RRE        (AT91_CAST(AT91_REG *) 	0x0000006C) // (EMAC_RRE) Receive Ressource Error Register
+#define EMAC_ROV        (AT91_CAST(AT91_REG *) 	0x00000070) // (EMAC_ROV) Receive Overrun Errors Register
+#define EMAC_RSE        (AT91_CAST(AT91_REG *) 	0x00000074) // (EMAC_RSE) Receive Symbol Errors Register
+#define EMAC_ELE        (AT91_CAST(AT91_REG *) 	0x00000078) // (EMAC_ELE) Excessive Length Errors Register
+#define EMAC_RJA        (AT91_CAST(AT91_REG *) 	0x0000007C) // (EMAC_RJA) Receive Jabbers Register
+#define EMAC_USF        (AT91_CAST(AT91_REG *) 	0x00000080) // (EMAC_USF) Undersize Frames Register
+#define EMAC_STE        (AT91_CAST(AT91_REG *) 	0x00000084) // (EMAC_STE) SQE Test Error Register
+#define EMAC_RLE        (AT91_CAST(AT91_REG *) 	0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register
+#define EMAC_TPF        (AT91_CAST(AT91_REG *) 	0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register
+#define EMAC_HRB        (AT91_CAST(AT91_REG *) 	0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0]
+#define EMAC_HRT        (AT91_CAST(AT91_REG *) 	0x00000094) // (EMAC_HRT) Hash Address Top[63:32]
+#define EMAC_SA1L       (AT91_CAST(AT91_REG *) 	0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes
+#define EMAC_SA1H       (AT91_CAST(AT91_REG *) 	0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes
+#define EMAC_SA2L       (AT91_CAST(AT91_REG *) 	0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes
+#define EMAC_SA2H       (AT91_CAST(AT91_REG *) 	0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes
+#define EMAC_SA3L       (AT91_CAST(AT91_REG *) 	0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes
+#define EMAC_SA3H       (AT91_CAST(AT91_REG *) 	0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes
+#define EMAC_SA4L       (AT91_CAST(AT91_REG *) 	0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes
+#define EMAC_SA4H       (AT91_CAST(AT91_REG *) 	0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes
+#define EMAC_TID        (AT91_CAST(AT91_REG *) 	0x000000B8) // (EMAC_TID) Type ID Checking Register
+#define EMAC_TPQ        (AT91_CAST(AT91_REG *) 	0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register
+#define EMAC_USRIO      (AT91_CAST(AT91_REG *) 	0x000000C0) // (EMAC_USRIO) USER Input/Output Register
+#define EMAC_WOL        (AT91_CAST(AT91_REG *) 	0x000000C4) // (EMAC_WOL) Wake On LAN Register
+#define EMAC_REV        (AT91_CAST(AT91_REG *) 	0x000000FC) // (EMAC_REV) Revision Register
+
+#endif
+// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+#define AT91C_EMAC_LB         (0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB        (0x1 <<  1) // (EMAC) Loopback local. 
+#define AT91C_EMAC_RE         (0x1 <<  2) // (EMAC) Receive enable. 
+#define AT91C_EMAC_TE         (0x1 <<  3) // (EMAC) Transmit enable. 
+#define AT91C_EMAC_MPE        (0x1 <<  4) // (EMAC) Management port enable. 
+#define AT91C_EMAC_CLRSTAT    (0x1 <<  5) // (EMAC) Clear statistics registers. 
+#define AT91C_EMAC_INCSTAT    (0x1 <<  6) // (EMAC) Increment statistics registers. 
+#define AT91C_EMAC_WESTAT     (0x1 <<  7) // (EMAC) Write enable for statistics registers. 
+#define AT91C_EMAC_BP         (0x1 <<  8) // (EMAC) Back pressure. 
+#define AT91C_EMAC_TSTART     (0x1 <<  9) // (EMAC) Start Transmission. 
+#define AT91C_EMAC_THALT      (0x1 << 10) // (EMAC) Transmission Halt. 
+#define AT91C_EMAC_TPFR       (0x1 << 11) // (EMAC) Transmit pause frame 
+#define AT91C_EMAC_TZQ        (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+#define AT91C_EMAC_SPD        (0x1 <<  0) // (EMAC) Speed. 
+#define AT91C_EMAC_FD         (0x1 <<  1) // (EMAC) Full duplex. 
+#define AT91C_EMAC_JFRAME     (0x1 <<  3) // (EMAC) Jumbo Frames. 
+#define AT91C_EMAC_CAF        (0x1 <<  4) // (EMAC) Copy all frames. 
+#define AT91C_EMAC_NBC        (0x1 <<  5) // (EMAC) No broadcast. 
+#define AT91C_EMAC_MTI        (0x1 <<  6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI        (0x1 <<  7) // (EMAC) Unicast hash enable. 
+#define AT91C_EMAC_BIG        (0x1 <<  8) // (EMAC) Receive 1522 bytes. 
+#define AT91C_EMAC_EAE        (0x1 <<  9) // (EMAC) External address match enable. 
+#define AT91C_EMAC_CLK        (0x3 << 10) // (EMAC) 
+#define 	AT91C_EMAC_CLK_HCLK_8               (0x0 << 10) // (EMAC) HCLK divided by 8
+#define 	AT91C_EMAC_CLK_HCLK_16              (0x1 << 10) // (EMAC) HCLK divided by 16
+#define 	AT91C_EMAC_CLK_HCLK_32              (0x2 << 10) // (EMAC) HCLK divided by 32
+#define 	AT91C_EMAC_CLK_HCLK_64              (0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY        (0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PAE        (0x1 << 13) // (EMAC) 
+#define AT91C_EMAC_RBOF       (0x3 << 14) // (EMAC) 
+#define 	AT91C_EMAC_RBOF_OFFSET_0             (0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_1             (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_2             (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_3             (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE       (0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS      (0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD      (0x1 << 18) // (EMAC) 
+#define AT91C_EMAC_IRXFCS     (0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+#define AT91C_EMAC_LINKR      (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_MDIO       (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_IDLE       (0x1 <<  2) // (EMAC) 
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+#define AT91C_EMAC_UBR        (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_COL        (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RLES       (0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TGO        (0x1 <<  3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX        (0x1 <<  4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP       (0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_UND        (0x1 <<  6) // (EMAC) 
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+#define AT91C_EMAC_BNA        (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_REC        (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_OVR        (0x1 <<  2) // (EMAC) 
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+#define AT91C_EMAC_MFD        (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_RCOMP      (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RXUBR      (0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TXUBR      (0x1 <<  3) // (EMAC) 
+#define AT91C_EMAC_TUNDR      (0x1 <<  4) // (EMAC) 
+#define AT91C_EMAC_RLEX       (0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_TXERR      (0x1 <<  6) // (EMAC) 
+#define AT91C_EMAC_TCOMP      (0x1 <<  7) // (EMAC) 
+#define AT91C_EMAC_LINK       (0x1 <<  9) // (EMAC) 
+#define AT91C_EMAC_ROVR       (0x1 << 10) // (EMAC) 
+#define AT91C_EMAC_HRESP      (0x1 << 11) // (EMAC) 
+#define AT91C_EMAC_PFRE       (0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PTZ        (0x1 << 13) // (EMAC) 
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+#define AT91C_EMAC_DATA       (0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_CODE       (0x3 << 16) // (EMAC) 
+#define AT91C_EMAC_REGA       (0x1F << 18) // (EMAC) 
+#define AT91C_EMAC_PHYA       (0x1F << 23) // (EMAC) 
+#define AT91C_EMAC_RW         (0x3 << 28) // (EMAC) 
+#define AT91C_EMAC_SOF        (0x3 << 30) // (EMAC) 
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+#define AT91C_EMAC_RMII       (0x1 <<  0) // (EMAC) Reduce MII
+#define AT91C_EMAC_CLKEN      (0x1 <<  1) // (EMAC) Clock Enable
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+#define AT91C_EMAC_IP         (0xFFFF <<  0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG        (0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP        (0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1        (0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+#define AT91C_EMAC_REVREF     (0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_PARTREF    (0xFFFF << 16) // (EMAC) 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_UDP {
+	AT91_REG	 UDP_NUM; 	// Frame Number Register
+	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
+	AT91_REG	 UDP_FADDR; 	// Function Address Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
+	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
+	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
+	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
+	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
+	AT91_REG	 Reserved4[3]; 	// 
+	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
+#else
+#define UDP_FRM_NUM     (AT91_CAST(AT91_REG *) 	0x00000000) // (UDP_FRM_NUM) Frame Number Register
+#define UDP_GLBSTATE    (AT91_CAST(AT91_REG *) 	0x00000004) // (UDP_GLBSTATE) Global State Register
+#define UDP_FADDR       (AT91_CAST(AT91_REG *) 	0x00000008) // (UDP_FADDR) Function Address Register
+#define UDP_IER         (AT91_CAST(AT91_REG *) 	0x00000010) // (UDP_IER) Interrupt Enable Register
+#define UDP_IDR         (AT91_CAST(AT91_REG *) 	0x00000014) // (UDP_IDR) Interrupt Disable Register
+#define UDP_IMR         (AT91_CAST(AT91_REG *) 	0x00000018) // (UDP_IMR) Interrupt Mask Register
+#define UDP_ISR         (AT91_CAST(AT91_REG *) 	0x0000001C) // (UDP_ISR) Interrupt Status Register
+#define UDP_ICR         (AT91_CAST(AT91_REG *) 	0x00000020) // (UDP_ICR) Interrupt Clear Register
+#define UDP_RSTEP       (AT91_CAST(AT91_REG *) 	0x00000028) // (UDP_RSTEP) Reset Endpoint Register
+#define UDP_CSR         (AT91_CAST(AT91_REG *) 	0x00000030) // (UDP_CSR) Endpoint Control and Status Register
+#define UDP_FDR         (AT91_CAST(AT91_REG *) 	0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
+#define UDP_TXVC        (AT91_CAST(AT91_REG *) 	0x00000074) // (UDP_TXVC) Transceiver Control Register
+
+#endif
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+#define AT91C_UDP_FRM_NUM     (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR     (0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK      (0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+#define AT91C_UDP_FADDEN      (0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG       (0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_ESR         (0x1 <<  2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR     (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE      (0x1 <<  4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+#define AT91C_UDP_FADD        (0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN         (0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+#define AT91C_UDP_EPINT0      (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1      (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2      (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3      (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4      (0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5      (0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP      (0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM       (0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM      (0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT      (0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP      (0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+#define AT91C_UDP_ENDBUSRES   (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+#define AT91C_UDP_EP0         (0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1         (0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2         (0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3         (0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4         (0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5         (0x1 <<  5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+#define AT91C_UDP_TXCOMP      (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 (0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP     (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR    (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_STALLSENT   (0x1 <<  3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
+#define AT91C_UDP_TXPKTRDY    (0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL  (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR         (0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE      (0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE       (0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS       (0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT   (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+#define AT91C_UDP_TXVDIS      (0x1 <<  8) // (UDP) 
+#define AT91C_UDP_PUON        (0x1 <<  9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Host Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_UHP {
+	AT91_REG	 UHP_HcRevision; 	// Revision
+	AT91_REG	 UHP_HcControl; 	// Operating modes for the Host Controller
+	AT91_REG	 UHP_HcCommandStatus; 	// Command & status Register
+	AT91_REG	 UHP_HcInterruptStatus; 	// Interrupt Status Register
+	AT91_REG	 UHP_HcInterruptEnable; 	// Interrupt Enable Register
+	AT91_REG	 UHP_HcInterruptDisable; 	// Interrupt Disable Register
+	AT91_REG	 UHP_HcHCCA; 	// Pointer to the Host Controller Communication Area
+	AT91_REG	 UHP_HcPeriodCurrentED; 	// Current Isochronous or Interrupt Endpoint Descriptor
+	AT91_REG	 UHP_HcControlHeadED; 	// First Endpoint Descriptor of the Control list
+	AT91_REG	 UHP_HcControlCurrentED; 	// Endpoint Control and Status Register
+	AT91_REG	 UHP_HcBulkHeadED; 	// First endpoint register of the Bulk list
+	AT91_REG	 UHP_HcBulkCurrentED; 	// Current endpoint of the Bulk list
+	AT91_REG	 UHP_HcBulkDoneHead; 	// Last completed transfer descriptor
+	AT91_REG	 UHP_HcFmInterval; 	// Bit time between 2 consecutive SOFs
+	AT91_REG	 UHP_HcFmRemaining; 	// Bit time remaining in the current Frame
+	AT91_REG	 UHP_HcFmNumber; 	// Frame number
+	AT91_REG	 UHP_HcPeriodicStart; 	// Periodic Start
+	AT91_REG	 UHP_HcLSThreshold; 	// LS Threshold
+	AT91_REG	 UHP_HcRhDescriptorA; 	// Root Hub characteristics A
+	AT91_REG	 UHP_HcRhDescriptorB; 	// Root Hub characteristics B
+	AT91_REG	 UHP_HcRhStatus; 	// Root Hub Status register
+	AT91_REG	 UHP_HcRhPortStatus[2]; 	// Root Hub Port Status Register
+} AT91S_UHP, *AT91PS_UHP;
+#else
+#define HcRevision      (AT91_CAST(AT91_REG *) 	0x00000000) // (HcRevision) Revision
+#define HcControl       (AT91_CAST(AT91_REG *) 	0x00000004) // (HcControl) Operating modes for the Host Controller
+#define HcCommandStatus (AT91_CAST(AT91_REG *) 	0x00000008) // (HcCommandStatus) Command & status Register
+#define HcInterruptStatus (AT91_CAST(AT91_REG *) 	0x0000000C) // (HcInterruptStatus) Interrupt Status Register
+#define HcInterruptEnable (AT91_CAST(AT91_REG *) 	0x00000010) // (HcInterruptEnable) Interrupt Enable Register
+#define HcInterruptDisable (AT91_CAST(AT91_REG *) 	0x00000014) // (HcInterruptDisable) Interrupt Disable Register
+#define HcHCCA          (AT91_CAST(AT91_REG *) 	0x00000018) // (HcHCCA) Pointer to the Host Controller Communication Area
+#define HcPeriodCurrentED (AT91_CAST(AT91_REG *) 	0x0000001C) // (HcPeriodCurrentED) Current Isochronous or Interrupt Endpoint Descriptor
+#define HcControlHeadED (AT91_CAST(AT91_REG *) 	0x00000020) // (HcControlHeadED) First Endpoint Descriptor of the Control list
+#define HcControlCurrentED (AT91_CAST(AT91_REG *) 	0x00000024) // (HcControlCurrentED) Endpoint Control and Status Register
+#define HcBulkHeadED    (AT91_CAST(AT91_REG *) 	0x00000028) // (HcBulkHeadED) First endpoint register of the Bulk list
+#define HcBulkCurrentED (AT91_CAST(AT91_REG *) 	0x0000002C) // (HcBulkCurrentED) Current endpoint of the Bulk list
+#define HcBulkDoneHead  (AT91_CAST(AT91_REG *) 	0x00000030) // (HcBulkDoneHead) Last completed transfer descriptor
+#define HcFmInterval    (AT91_CAST(AT91_REG *) 	0x00000034) // (HcFmInterval) Bit time between 2 consecutive SOFs
+#define HcFmRemaining   (AT91_CAST(AT91_REG *) 	0x00000038) // (HcFmRemaining) Bit time remaining in the current Frame
+#define HcFmNumber      (AT91_CAST(AT91_REG *) 	0x0000003C) // (HcFmNumber) Frame number
+#define HcPeriodicStart (AT91_CAST(AT91_REG *) 	0x00000040) // (HcPeriodicStart) Periodic Start
+#define HcLSThreshold   (AT91_CAST(AT91_REG *) 	0x00000044) // (HcLSThreshold) LS Threshold
+#define HcRhDescriptorA (AT91_CAST(AT91_REG *) 	0x00000048) // (HcRhDescriptorA) Root Hub characteristics A
+#define HcRhDescriptorB (AT91_CAST(AT91_REG *) 	0x0000004C) // (HcRhDescriptorB) Root Hub characteristics B
+#define HcRhStatus      (AT91_CAST(AT91_REG *) 	0x00000050) // (HcRhStatus) Root Hub Status register
+#define HcRhPortStatus  (AT91_CAST(AT91_REG *) 	0x00000054) // (HcRhPortStatus) Root Hub Port Status Register
+
+#endif
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Image Sensor Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_ISI {
+	AT91_REG	 ISI_CR1; 	// Control Register 1
+	AT91_REG	 ISI_CR2; 	// Control Register 2
+	AT91_REG	 ISI_SR; 	// Status Register
+	AT91_REG	 ISI_IER; 	// Interrupt Enable Register
+	AT91_REG	 ISI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 ISI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 ISI_PSIZE; 	// Preview Size Register
+	AT91_REG	 ISI_PDECF; 	// Preview Decimation Factor Register
+	AT91_REG	 ISI_PFBD; 	// Preview Frame Buffer Address Register
+	AT91_REG	 ISI_CDBA; 	// Codec Dma Address Register
+	AT91_REG	 ISI_Y2RSET0; 	// Color Space Conversion Register
+	AT91_REG	 ISI_Y2RSET1; 	// Color Space Conversion Register
+	AT91_REG	 ISI_R2YSET0; 	// Color Space Conversion Register
+	AT91_REG	 ISI_R2YSET1; 	// Color Space Conversion Register
+	AT91_REG	 ISI_R2YSET2; 	// Color Space Conversion Register
+} AT91S_ISI, *AT91PS_ISI;
+#else
+#define ISI_CR1         (AT91_CAST(AT91_REG *) 	0x00000000) // (ISI_CR1) Control Register 1
+#define ISI_CR2         (AT91_CAST(AT91_REG *) 	0x00000004) // (ISI_CR2) Control Register 2
+#define ISI_SR          (AT91_CAST(AT91_REG *) 	0x00000008) // (ISI_SR) Status Register
+#define ISI_IER         (AT91_CAST(AT91_REG *) 	0x0000000C) // (ISI_IER) Interrupt Enable Register
+#define ISI_IDR         (AT91_CAST(AT91_REG *) 	0x00000010) // (ISI_IDR) Interrupt Disable Register
+#define ISI_IMR         (AT91_CAST(AT91_REG *) 	0x00000014) // (ISI_IMR) Interrupt Mask Register
+#define ISI_PSIZE       (AT91_CAST(AT91_REG *) 	0x00000020) // (ISI_PSIZE) Preview Size Register
+#define ISI_PDECF       (AT91_CAST(AT91_REG *) 	0x00000024) // (ISI_PDECF) Preview Decimation Factor Register
+#define ISI_PFBD        (AT91_CAST(AT91_REG *) 	0x00000028) // (ISI_PFBD) Preview Frame Buffer Address Register
+#define ISI_CDBA        (AT91_CAST(AT91_REG *) 	0x0000002C) // (ISI_CDBA) Codec Dma Address Register
+#define ISI_Y2RSET0     (AT91_CAST(AT91_REG *) 	0x00000030) // (ISI_Y2RSET0) Color Space Conversion Register
+#define ISI_Y2RSET1     (AT91_CAST(AT91_REG *) 	0x00000034) // (ISI_Y2RSET1) Color Space Conversion Register
+#define ISI_R2YSET0     (AT91_CAST(AT91_REG *) 	0x00000038) // (ISI_R2YSET0) Color Space Conversion Register
+#define ISI_R2YSET1     (AT91_CAST(AT91_REG *) 	0x0000003C) // (ISI_R2YSET1) Color Space Conversion Register
+#define ISI_R2YSET2     (AT91_CAST(AT91_REG *) 	0x00000040) // (ISI_R2YSET2) Color Space Conversion Register
+
+#endif
+// -------- ISI_CR1 : (ISI Offset: 0x0) ISI Control Register 1 -------- 
+#define AT91C_ISI_RST         (0x1 <<  0) // (ISI) Image sensor interface reset
+#define AT91C_ISI_DISABLE     (0x1 <<  1) // (ISI) image sensor disable.
+#define AT91C_ISI_HSYNC_POL   (0x1 <<  2) // (ISI) Horizontal synchronisation polarity
+#define AT91C_ISI_PIXCLK_POL  (0x1 <<  4) // (ISI) Pixel Clock Polarity
+#define AT91C_ISI_EMB_SYNC    (0x1 <<  6) // (ISI) Embedded synchronisation
+#define AT91C_ISI_CRC_SYNC    (0x1 <<  7) // (ISI) CRC correction
+#define AT91C_ISI_FULL        (0x1 << 12) // (ISI) Full mode is allowed
+#define AT91C_ISI_THMASK      (0x3 << 13) // (ISI) DMA Burst Mask
+#define 	AT91C_ISI_THMASK_4_8_16_BURST         (0x0 << 13) // (ISI) 4,8 and 16 AHB burst are allowed
+#define 	AT91C_ISI_THMASK_8_16_BURST           (0x1 << 13) // (ISI) 8 and 16 AHB burst are allowed
+#define 	AT91C_ISI_THMASK_16_BURST             (0x2 << 13) // (ISI) Only 16 AHB burst are allowed
+#define AT91C_ISI_CODEC_ON    (0x1 << 15) // (ISI) Enable the codec path
+#define AT91C_ISI_SLD         (0xFF << 16) // (ISI) Start of Line Delay
+#define AT91C_ISI_SFD         (0xFF << 24) // (ISI) Start of frame Delay
+// -------- ISI_CR2 : (ISI Offset: 0x4) ISI Control Register 2 -------- 
+#define AT91C_ISI_IM_VSIZE    (0x7FF <<  0) // (ISI) Vertical size of the Image sensor [0..2047]
+#define AT91C_ISI_GS_MODE     (0x1 << 11) // (ISI) Grayscale Memory Mode
+#define AT91C_ISI_RGB_MODE    (0x3 << 12) // (ISI) RGB mode
+#define 	AT91C_ISI_RGB_MODE_RGB_888              (0x0 << 12) // (ISI) RGB 8:8:8 24 bits
+#define 	AT91C_ISI_RGB_MODE_RGB_565              (0x1 << 12) // (ISI) RGB 5:6:5 16 bits
+#define 	AT91C_ISI_RGB_MODE_RGB_555              (0x2 << 12) // (ISI) RGB 5:5:5 16 bits
+#define AT91C_ISI_GRAYSCALE   (0x1 << 13) // (ISI) Grayscale Mode
+#define AT91C_ISI_RGB_SWAP    (0x1 << 14) // (ISI) RGB Swap
+#define AT91C_ISI_COL_SPACE   (0x1 << 15) // (ISI) Color space for the image data
+#define AT91C_ISI_IM_HSIZE    (0x7FF << 16) // (ISI) Horizontal size of the Image sensor [0..2047]
+#define 	AT91C_ISI_RGB_MODE_YCC_DEF              (0x0 << 28) // (ISI) Cb(i) Y(i) Cr(i) Y(i+1)
+#define 	AT91C_ISI_RGB_MODE_YCC_MOD1             (0x1 << 28) // (ISI) Cr(i) Y(i) Cb(i) Y(i+1)
+#define 	AT91C_ISI_RGB_MODE_YCC_MOD2             (0x2 << 28) // (ISI) Y(i) Cb(i) Y(i+1) Cr(i)
+#define 	AT91C_ISI_RGB_MODE_YCC_MOD3             (0x3 << 28) // (ISI) Y(i) Cr(i) Y(i+1) Cb(i)
+#define AT91C_ISI_RGB_CFG     (0x3 << 30) // (ISI) RGB configuration
+#define 	AT91C_ISI_RGB_CFG_RGB_DEF              (0x0 << 30) // (ISI) R/G(MSB)  G(LSB)/B  R/G(MSB)  G(LSB)/B
+#define 	AT91C_ISI_RGB_CFG_RGB_MOD1             (0x1 << 30) // (ISI) B/G(MSB)  G(LSB)/R  B/G(MSB)  G(LSB)/R
+#define 	AT91C_ISI_RGB_CFG_RGB_MOD2             (0x2 << 30) // (ISI) G(LSB)/R  B/G(MSB)  G(LSB)/R  B/G(MSB)
+#define 	AT91C_ISI_RGB_CFG_RGB_MOD3             (0x3 << 30) // (ISI) G(LSB)/B  R/G(MSB)  G(LSB)/B  R/G(MSB)
+// -------- ISI_SR : (ISI Offset: 0x8) ISI Status Register -------- 
+#define AT91C_ISI_SOF         (0x1 <<  0) // (ISI) Start of Frame
+#define AT91C_ISI_DIS         (0x1 <<  1) // (ISI) Image Sensor Interface disable
+#define AT91C_ISI_SOFTRST     (0x1 <<  2) // (ISI) Software Reset
+#define AT91C_ISI_CRC_ERR     (0x1 <<  4) // (ISI) CRC synchronisation error
+#define AT91C_ISI_FO_C_OVF    (0x1 <<  5) // (ISI) Fifo Codec Overflow 
+#define AT91C_ISI_FO_P_OVF    (0x1 <<  6) // (ISI) Fifo Preview Overflow 
+#define AT91C_ISI_FO_P_EMP    (0x1 <<  7) // (ISI) Fifo Preview Empty
+#define AT91C_ISI_FO_C_EMP    (0x1 <<  8) // (ISI) Fifo Codec Empty
+#define AT91C_ISI_FR_OVR      (0x1 <<  9) // (ISI) Frame rate overun
+// -------- ISI_IER : (ISI Offset: 0xc) ISI Interrupt Enable Register -------- 
+// -------- ISI_IDR : (ISI Offset: 0x10) ISI Interrupt Disable Register -------- 
+// -------- ISI_IMR : (ISI Offset: 0x14) ISI Interrupt Mask Register -------- 
+// -------- ISI_PSIZE : (ISI Offset: 0x20) ISI Preview Register -------- 
+#define AT91C_ISI_PREV_VSIZE  (0x3FF <<  0) // (ISI) Vertical size for the preview path
+#define AT91C_ISI_PREV_HSIZE  (0x3FF << 16) // (ISI) Horizontal size for the preview path
+// -------- ISI_Y2R_SET0 : (ISI Offset: 0x30) Color Space Conversion YCrCb to RGB Register -------- 
+#define AT91C_ISI_Y2R_C0      (0xFF <<  0) // (ISI) Color Space Conversion Matrix Coefficient C0
+#define AT91C_ISI_Y2R_C1      (0xFF <<  8) // (ISI) Color Space Conversion Matrix Coefficient C1
+#define AT91C_ISI_Y2R_C2      (0xFF << 16) // (ISI) Color Space Conversion Matrix Coefficient C2
+#define AT91C_ISI_Y2R_C3      (0xFF << 24) // (ISI) Color Space Conversion Matrix Coefficient C3
+// -------- ISI_Y2R_SET1 : (ISI Offset: 0x34) ISI Color Space Conversion YCrCb to RGB set 1 Register -------- 
+#define AT91C_ISI_Y2R_C4      (0x1FF <<  0) // (ISI) Color Space Conversion Matrix Coefficient C4
+#define AT91C_ISI_Y2R_YOFF    (0xFF << 12) // (ISI) Color Space Conversion Luninance default offset
+#define AT91C_ISI_Y2R_CROFF   (0xFF << 13) // (ISI) Color Space Conversion Red Chrominance default offset
+#define AT91C_ISI_Y2R_CBFF    (0xFF << 14) // (ISI) Color Space Conversion Luninance default offset
+// -------- ISI_R2Y_SET0 : (ISI Offset: 0x38) Color Space Conversion RGB to YCrCb set 0 register -------- 
+#define AT91C_ISI_R2Y_C0      (0x7F <<  0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C0
+#define AT91C_ISI_R2Y_C1      (0x7F <<  1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C1
+#define AT91C_ISI_R2Y_C2      (0x7F <<  3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C2
+#define AT91C_ISI_R2Y_ROFF    (0x1 <<  4) // (ISI) Color Space Conversion Red component offset
+// -------- ISI_R2Y_SET1 : (ISI Offset: 0x3c) Color Space Conversion RGB to YCrCb set 1 register -------- 
+#define AT91C_ISI_R2Y_C3      (0x7F <<  0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C3
+#define AT91C_ISI_R2Y_C4      (0x7F <<  1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C4
+#define AT91C_ISI_R2Y_C5      (0x7F <<  3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C5
+#define AT91C_ISI_R2Y_GOFF    (0x1 <<  4) // (ISI) Color Space Conversion Green component offset
+// -------- ISI_R2Y_SET2 : (ISI Offset: 0x40) Color Space Conversion RGB to YCrCb set 2 register -------- 
+#define AT91C_ISI_R2Y_C6      (0x7F <<  0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C6
+#define AT91C_ISI_R2Y_C7      (0x7F <<  1) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C7
+#define AT91C_ISI_R2Y_C8      (0x7F <<  3) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C8
+#define AT91C_ISI_R2Y_BOFF    (0x1 <<  4) // (ISI) Color Space Conversion Blue component offset
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM9XE512
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ========== 
+#define AT91C_SYS_GPBR  (AT91_CAST(AT91_REG *) 	0xFFFFFFFF) // (SYS) General Purpose Register
+// ========== Register definition for EBI peripheral ========== 
+#define AT91C_EBI_DUMMY (AT91_CAST(AT91_REG *) 	0xFFFFEA00) // (EBI) Dummy register - Do not use
+// ========== Register definition for HECC peripheral ========== 
+#define AT91C_HECC_VR   (AT91_CAST(AT91_REG *) 	0xFFFFE8FC) // (HECC)  ECC Version register
+#define AT91C_HECC_NPR  (AT91_CAST(AT91_REG *) 	0xFFFFE810) // (HECC)  ECC Parity N register
+#define AT91C_HECC_SR   (AT91_CAST(AT91_REG *) 	0xFFFFE808) // (HECC)  ECC Status register
+#define AT91C_HECC_PR   (AT91_CAST(AT91_REG *) 	0xFFFFE80C) // (HECC)  ECC Parity register
+#define AT91C_HECC_MR   (AT91_CAST(AT91_REG *) 	0xFFFFE804) // (HECC)  ECC Page size register
+#define AT91C_HECC_CR   (AT91_CAST(AT91_REG *) 	0xFFFFE800) // (HECC)  ECC reset register
+// ========== Register definition for SDRAMC peripheral ========== 
+#define AT91C_SDRAMC_MR (AT91_CAST(AT91_REG *) 	0xFFFFEA00) // (SDRAMC) SDRAM Controller Mode Register
+#define AT91C_SDRAMC_IMR (AT91_CAST(AT91_REG *) 	0xFFFFEA1C) // (SDRAMC) SDRAM Controller Interrupt Mask Register
+#define AT91C_SDRAMC_LPR (AT91_CAST(AT91_REG *) 	0xFFFFEA10) // (SDRAMC) SDRAM Controller Low Power Register
+#define AT91C_SDRAMC_ISR (AT91_CAST(AT91_REG *) 	0xFFFFEA20) // (SDRAMC) SDRAM Controller Interrupt Mask Register
+#define AT91C_SDRAMC_IDR (AT91_CAST(AT91_REG *) 	0xFFFFEA18) // (SDRAMC) SDRAM Controller Interrupt Disable Register
+#define AT91C_SDRAMC_CR (AT91_CAST(AT91_REG *) 	0xFFFFEA08) // (SDRAMC) SDRAM Controller Configuration Register
+#define AT91C_SDRAMC_TR (AT91_CAST(AT91_REG *) 	0xFFFFEA04) // (SDRAMC) SDRAM Controller Refresh Timer Register
+#define AT91C_SDRAMC_MDR (AT91_CAST(AT91_REG *) 	0xFFFFEA24) // (SDRAMC) SDRAM Memory Device Register
+#define AT91C_SDRAMC_HSR (AT91_CAST(AT91_REG *) 	0xFFFFEA0C) // (SDRAMC) SDRAM Controller High Speed Register
+#define AT91C_SDRAMC_IER (AT91_CAST(AT91_REG *) 	0xFFFFEA14) // (SDRAMC) SDRAM Controller Interrupt Enable Register
+// ========== Register definition for SMC peripheral ========== 
+#define AT91C_SMC_CTRL1 (AT91_CAST(AT91_REG *) 	0xFFFFEC1C) // (SMC)  Control Register for CS 1
+#define AT91C_SMC_PULSE7 (AT91_CAST(AT91_REG *) 	0xFFFFEC74) // (SMC)  Pulse Register for CS 7
+#define AT91C_SMC_PULSE6 (AT91_CAST(AT91_REG *) 	0xFFFFEC64) // (SMC)  Pulse Register for CS 6
+#define AT91C_SMC_SETUP4 (AT91_CAST(AT91_REG *) 	0xFFFFEC40) // (SMC)  Setup Register for CS 4
+#define AT91C_SMC_PULSE3 (AT91_CAST(AT91_REG *) 	0xFFFFEC34) // (SMC)  Pulse Register for CS 3
+#define AT91C_SMC_CYCLE5 (AT91_CAST(AT91_REG *) 	0xFFFFEC58) // (SMC)  Cycle Register for CS 5
+#define AT91C_SMC_CYCLE2 (AT91_CAST(AT91_REG *) 	0xFFFFEC28) // (SMC)  Cycle Register for CS 2
+#define AT91C_SMC_CTRL2 (AT91_CAST(AT91_REG *) 	0xFFFFEC2C) // (SMC)  Control Register for CS 2
+#define AT91C_SMC_CTRL0 (AT91_CAST(AT91_REG *) 	0xFFFFEC0C) // (SMC)  Control Register for CS 0
+#define AT91C_SMC_PULSE5 (AT91_CAST(AT91_REG *) 	0xFFFFEC54) // (SMC)  Pulse Register for CS 5
+#define AT91C_SMC_PULSE1 (AT91_CAST(AT91_REG *) 	0xFFFFEC14) // (SMC)  Pulse Register for CS 1
+#define AT91C_SMC_PULSE0 (AT91_CAST(AT91_REG *) 	0xFFFFEC04) // (SMC)  Pulse Register for CS 0
+#define AT91C_SMC_CYCLE7 (AT91_CAST(AT91_REG *) 	0xFFFFEC78) // (SMC)  Cycle Register for CS 7
+#define AT91C_SMC_CTRL4 (AT91_CAST(AT91_REG *) 	0xFFFFEC4C) // (SMC)  Control Register for CS 4
+#define AT91C_SMC_CTRL3 (AT91_CAST(AT91_REG *) 	0xFFFFEC3C) // (SMC)  Control Register for CS 3
+#define AT91C_SMC_SETUP7 (AT91_CAST(AT91_REG *) 	0xFFFFEC70) // (SMC)  Setup Register for CS 7
+#define AT91C_SMC_CTRL7 (AT91_CAST(AT91_REG *) 	0xFFFFEC7C) // (SMC)  Control Register for CS 7
+#define AT91C_SMC_SETUP1 (AT91_CAST(AT91_REG *) 	0xFFFFEC10) // (SMC)  Setup Register for CS 1
+#define AT91C_SMC_CYCLE0 (AT91_CAST(AT91_REG *) 	0xFFFFEC08) // (SMC)  Cycle Register for CS 0
+#define AT91C_SMC_CTRL5 (AT91_CAST(AT91_REG *) 	0xFFFFEC5C) // (SMC)  Control Register for CS 5
+#define AT91C_SMC_CYCLE1 (AT91_CAST(AT91_REG *) 	0xFFFFEC18) // (SMC)  Cycle Register for CS 1
+#define AT91C_SMC_CTRL6 (AT91_CAST(AT91_REG *) 	0xFFFFEC6C) // (SMC)  Control Register for CS 6
+#define AT91C_SMC_SETUP0 (AT91_CAST(AT91_REG *) 	0xFFFFEC00) // (SMC)  Setup Register for CS 0
+#define AT91C_SMC_PULSE4 (AT91_CAST(AT91_REG *) 	0xFFFFEC44) // (SMC)  Pulse Register for CS 4
+#define AT91C_SMC_SETUP5 (AT91_CAST(AT91_REG *) 	0xFFFFEC50) // (SMC)  Setup Register for CS 5
+#define AT91C_SMC_SETUP2 (AT91_CAST(AT91_REG *) 	0xFFFFEC20) // (SMC)  Setup Register for CS 2
+#define AT91C_SMC_CYCLE3 (AT91_CAST(AT91_REG *) 	0xFFFFEC38) // (SMC)  Cycle Register for CS 3
+#define AT91C_SMC_CYCLE6 (AT91_CAST(AT91_REG *) 	0xFFFFEC68) // (SMC)  Cycle Register for CS 6
+#define AT91C_SMC_SETUP6 (AT91_CAST(AT91_REG *) 	0xFFFFEC60) // (SMC)  Setup Register for CS 6
+#define AT91C_SMC_CYCLE4 (AT91_CAST(AT91_REG *) 	0xFFFFEC48) // (SMC)  Cycle Register for CS 4
+#define AT91C_SMC_PULSE2 (AT91_CAST(AT91_REG *) 	0xFFFFEC24) // (SMC)  Pulse Register for CS 2
+#define AT91C_SMC_SETUP3 (AT91_CAST(AT91_REG *) 	0xFFFFEC30) // (SMC)  Setup Register for CS 3
+// ========== Register definition for MATRIX peripheral ========== 
+#define AT91C_MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 	0xFFFFEE00) // (MATRIX)  Master Configuration Register 0 (ram96k)     
+#define AT91C_MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 	0xFFFFEE1C) // (MATRIX)  Master Configuration Register 7 (teak_prog)     
+#define AT91C_MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 	0xFFFFEE44) // (MATRIX)  Slave Configuration Register 1 (rom)    
+#define AT91C_MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 	0xFFFFEE10) // (MATRIX)  Master Configuration Register 4 (bridge)    
+#define AT91C_MATRIX_VERSION (AT91_CAST(AT91_REG *) 	0xFFFFEFFC) // (MATRIX)  Version Register
+#define AT91C_MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 	0xFFFFEE08) // (MATRIX)  Master Configuration Register 2 (hperiphs) 
+#define AT91C_MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 	0xFFFFEEA4) // (MATRIX)  PRBS4 : ebi
+#define AT91C_MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 	0xFFFFEE84) // (MATRIX)  PRBS0 (ram0) 
+#define AT91C_MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 	0xFFFFEE4C) // (MATRIX)  Slave Configuration Register 3 (ebi)
+#define AT91C_MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 	0xFFFFEE18) // (MATRIX)  Master Configuration Register 6 (ram16k)  
+#define AT91C_MATRIX_EBI (AT91_CAST(AT91_REG *) 	0xFFFFEF1C) // (MATRIX)  Slave 3 (ebi) Special Function Register
+#define AT91C_MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 	0xFFFFEE40) // (MATRIX)  Slave Configuration Register 0 (ram96k)     
+#define AT91C_MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 	0xFFFFEE9C) // (MATRIX)  PRBS3 : usb_dev_hs
+#define AT91C_MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 	0xFFFFEE98) // (MATRIX)  PRAS3 : usb_dev_hs
+#define AT91C_MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 	0xFFFFEE80) // (MATRIX)  PRAS0 (ram0) 
+#define AT91C_MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 	0xFFFFEE0C) // (MATRIX)  Master Configuration Register 3 (ebi)
+#define AT91C_MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 	0xFFFFEE88) // (MATRIX)  PRAS1 (ram1) 
+#define AT91C_MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 	0xFFFFEE90) // (MATRIX)  PRAS2 (ram2) 
+#define AT91C_MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 	0xFFFFEE48) // (MATRIX)  Slave Configuration Register 2 (hperiphs) 
+#define AT91C_MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 	0xFFFFEE14) // (MATRIX)  Master Configuration Register 5 (mailbox)    
+#define AT91C_MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 	0xFFFFEE04) // (MATRIX)  Master Configuration Register 1 (rom)    
+#define AT91C_MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 	0xFFFFEEA0) // (MATRIX)  PRAS4 : ebi
+#define AT91C_MATRIX_MRCR (AT91_CAST(AT91_REG *) 	0xFFFFEF00) // (MATRIX)  Master Remp Control Register 
+#define AT91C_MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 	0xFFFFEE94) // (MATRIX)  PRBS2 (ram2) 
+#define AT91C_MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 	0xFFFFEE50) // (MATRIX)  Slave Configuration Register 4 (bridge)    
+#define AT91C_MATRIX_TEAKCFG (AT91_CAST(AT91_REG *) 	0xFFFFEF2C) // (MATRIX)  Slave 7 (teak_prog) Special Function Register
+#define AT91C_MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 	0xFFFFEE8C) // (MATRIX)  PRBS1 (ram1) 
+// ========== Register definition for CCFG peripheral ========== 
+#define AT91C_CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 	0xFFFFEFFC) // (CCFG)  Version Register
+#define AT91C_CCFG_EBICSA (AT91_CAST(AT91_REG *) 	0xFFFFEF1C) // (CCFG)  EBI Chip Select Assignement Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_TCR  (AT91_CAST(AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR  (AT91_CAST(AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR  (AT91_CAST(AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR  (AT91_CAST(AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR  (AT91_CAST(AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR   (AT91_CAST(AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR   (AT91_CAST(AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR  (AT91_CAST(AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR  (AT91_CAST(AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_IVR   (AT91_CAST(AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR   (AT91_CAST(AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR   (AT91_CAST(AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR   (AT91_CAST(AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR   (AT91_CAST(AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR  (AT91_CAST(AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR  (AT91_CAST(AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR   (AT91_CAST(AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR   (AT91_CAST(AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER  (AT91_CAST(AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR  (AT91_CAST(AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR  (AT91_CAST(AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR  (AT91_CAST(AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR  (AT91_CAST(AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR  (AT91_CAST(AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU   (AT91_CAST(AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_ODR  (AT91_CAST(AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR  (AT91_CAST(AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER  (AT91_CAST(AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR  (AT91_CAST(AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR  (AT91_CAST(AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR  (AT91_CAST(AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR  (AT91_CAST(AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER  (AT91_CAST(AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR  (AT91_CAST(AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ========== 
+#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR  (AT91_CAST(AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR  (AT91_CAST(AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR  (AT91_CAST(AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR  (AT91_CAST(AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR  (AT91_CAST(AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR  (AT91_CAST(AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR  (AT91_CAST(AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER  (AT91_CAST(AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER  (AT91_CAST(AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for PIOC peripheral ========== 
+#define AT91C_PIOC_OWDR (AT91_CAST(AT91_REG *) 	0xFFFFF8A4) // (PIOC) Output Write Disable Register
+#define AT91C_PIOC_SODR (AT91_CAST(AT91_REG *) 	0xFFFFF830) // (PIOC) Set Output Data Register
+#define AT91C_PIOC_PPUER (AT91_CAST(AT91_REG *) 	0xFFFFF864) // (PIOC) Pull-up Enable Register
+#define AT91C_PIOC_CODR (AT91_CAST(AT91_REG *) 	0xFFFFF834) // (PIOC) Clear Output Data Register
+#define AT91C_PIOC_PSR  (AT91_CAST(AT91_REG *) 	0xFFFFF808) // (PIOC) PIO Status Register
+#define AT91C_PIOC_PDR  (AT91_CAST(AT91_REG *) 	0xFFFFF804) // (PIOC) PIO Disable Register
+#define AT91C_PIOC_ODR  (AT91_CAST(AT91_REG *) 	0xFFFFF814) // (PIOC) Output Disable Registerr
+#define AT91C_PIOC_PPUSR (AT91_CAST(AT91_REG *) 	0xFFFFF868) // (PIOC) Pull-up Status Register
+#define AT91C_PIOC_ABSR (AT91_CAST(AT91_REG *) 	0xFFFFF878) // (PIOC) AB Select Status Register
+#define AT91C_PIOC_IFSR (AT91_CAST(AT91_REG *) 	0xFFFFF828) // (PIOC) Input Filter Status Register
+#define AT91C_PIOC_OER  (AT91_CAST(AT91_REG *) 	0xFFFFF810) // (PIOC) Output Enable Register
+#define AT91C_PIOC_IMR  (AT91_CAST(AT91_REG *) 	0xFFFFF848) // (PIOC) Interrupt Mask Register
+#define AT91C_PIOC_ASR  (AT91_CAST(AT91_REG *) 	0xFFFFF870) // (PIOC) Select A Register
+#define AT91C_PIOC_MDDR (AT91_CAST(AT91_REG *) 	0xFFFFF854) // (PIOC) Multi-driver Disable Register
+#define AT91C_PIOC_OWSR (AT91_CAST(AT91_REG *) 	0xFFFFF8A8) // (PIOC) Output Write Status Register
+#define AT91C_PIOC_PER  (AT91_CAST(AT91_REG *) 	0xFFFFF800) // (PIOC) PIO Enable Register
+#define AT91C_PIOC_IDR  (AT91_CAST(AT91_REG *) 	0xFFFFF844) // (PIOC) Interrupt Disable Register
+#define AT91C_PIOC_MDER (AT91_CAST(AT91_REG *) 	0xFFFFF850) // (PIOC) Multi-driver Enable Register
+#define AT91C_PIOC_PDSR (AT91_CAST(AT91_REG *) 	0xFFFFF83C) // (PIOC) Pin Data Status Register
+#define AT91C_PIOC_MDSR (AT91_CAST(AT91_REG *) 	0xFFFFF858) // (PIOC) Multi-driver Status Register
+#define AT91C_PIOC_OWER (AT91_CAST(AT91_REG *) 	0xFFFFF8A0) // (PIOC) Output Write Enable Register
+#define AT91C_PIOC_BSR  (AT91_CAST(AT91_REG *) 	0xFFFFF874) // (PIOC) Select B Register
+#define AT91C_PIOC_PPUDR (AT91_CAST(AT91_REG *) 	0xFFFFF860) // (PIOC) Pull-up Disable Register
+#define AT91C_PIOC_IFDR (AT91_CAST(AT91_REG *) 	0xFFFFF824) // (PIOC) Input Filter Disable Register
+#define AT91C_PIOC_IER  (AT91_CAST(AT91_REG *) 	0xFFFFF840) // (PIOC) Interrupt Enable Register
+#define AT91C_PIOC_OSR  (AT91_CAST(AT91_REG *) 	0xFFFFF818) // (PIOC) Output Status Register
+#define AT91C_PIOC_ODSR (AT91_CAST(AT91_REG *) 	0xFFFFF838) // (PIOC) Output Data Status Register
+#define AT91C_PIOC_ISR  (AT91_CAST(AT91_REG *) 	0xFFFFF84C) // (PIOC) Interrupt Status Register
+#define AT91C_PIOC_IFER (AT91_CAST(AT91_REG *) 	0xFFFFF820) // (PIOC) Input Filter Enable Register
+// ========== Register definition for EFC peripheral ========== 
+#define AT91C_EFC_FVR   (AT91_CAST(AT91_REG *) 	0xFFFFFA10) // (EFC) EFC Flash Version Register
+#define AT91C_EFC_FCR   (AT91_CAST(AT91_REG *) 	0xFFFFFA04) // (EFC) EFC Flash Command Register
+#define AT91C_EFC_FMR   (AT91_CAST(AT91_REG *) 	0xFFFFFA00) // (EFC) EFC Flash Mode Register
+#define AT91C_EFC_FRR   (AT91_CAST(AT91_REG *) 	0xFFFFFA0C) // (EFC) EFC Flash Result Register
+#define AT91C_EFC_FSR   (AT91_CAST(AT91_REG *) 	0xFFFFFA08) // (EFC) EFC Flash Status Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_MOR  (AT91_CAST(AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLBR (AT91_CAST(AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL B Register
+#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+#define AT91C_CKGR_PLLAR (AT91_CAST(AT91_REG *) 	0xFFFFFC28) // (CKGR) PLL A Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_PCER  (AT91_CAST(AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR  (AT91_CAST(AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR  (AT91_CAST(AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_PLLAR (AT91_CAST(AT91_REG *) 	0xFFFFFC28) // (PMC) PLL A Register
+#define AT91C_PMC_PCDR  (AT91_CAST(AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR  (AT91_CAST(AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_MCFR  (AT91_CAST(AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER   (AT91_CAST(AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_MOR   (AT91_CAST(AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_PLLBR (AT91_CAST(AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL B Register
+#define AT91C_PMC_SCDR  (AT91_CAST(AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCSR  (AT91_CAST(AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_SCER  (AT91_CAST(AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_SR    (AT91_CAST(AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RCR  (AT91_CAST(AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR  (AT91_CAST(AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR  (AT91_CAST(AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for SHDWC peripheral ========== 
+#define AT91C_SHDWC_SHSR (AT91_CAST(AT91_REG *) 	0xFFFFFD18) // (SHDWC) Shut Down Status Register
+#define AT91C_SHDWC_SHMR (AT91_CAST(AT91_REG *) 	0xFFFFFD14) // (SHDWC) Shut Down Mode Register
+#define AT91C_SHDWC_SHCR (AT91_CAST(AT91_REG *) 	0xFFFFFD10) // (SHDWC) Shut Down Control Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_SR    (AT91_CAST(AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC    (AT91_CAST(AT91_REG *) 	0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER   (AT91_CAST(AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER   (AT91_CAST(AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR    (AT91_CAST(AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC    (AT91_CAST(AT91_REG *) 	0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_CMR   (AT91_CAST(AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR   (AT91_CAST(AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV    (AT91_CAST(AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA    (AT91_CAST(AT91_REG *) 	0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB    (AT91_CAST(AT91_REG *) 	0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC    (AT91_CAST(AT91_REG *) 	0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER   (AT91_CAST(AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR    (AT91_CAST(AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TC3 peripheral ========== 
+#define AT91C_TC3_IER   (AT91_CAST(AT91_REG *) 	0xFFFDC024) // (TC3) Interrupt Enable Register
+#define AT91C_TC3_RB    (AT91_CAST(AT91_REG *) 	0xFFFDC018) // (TC3) Register B
+#define AT91C_TC3_CMR   (AT91_CAST(AT91_REG *) 	0xFFFDC004) // (TC3) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC3_RC    (AT91_CAST(AT91_REG *) 	0xFFFDC01C) // (TC3) Register C
+#define AT91C_TC3_CCR   (AT91_CAST(AT91_REG *) 	0xFFFDC000) // (TC3) Channel Control Register
+#define AT91C_TC3_SR    (AT91_CAST(AT91_REG *) 	0xFFFDC020) // (TC3) Status Register
+#define AT91C_TC3_CV    (AT91_CAST(AT91_REG *) 	0xFFFDC010) // (TC3) Counter Value
+#define AT91C_TC3_RA    (AT91_CAST(AT91_REG *) 	0xFFFDC014) // (TC3) Register A
+#define AT91C_TC3_IDR   (AT91_CAST(AT91_REG *) 	0xFFFDC028) // (TC3) Interrupt Disable Register
+#define AT91C_TC3_IMR   (AT91_CAST(AT91_REG *) 	0xFFFDC02C) // (TC3) Interrupt Mask Register
+// ========== Register definition for TC4 peripheral ========== 
+#define AT91C_TC4_CMR   (AT91_CAST(AT91_REG *) 	0xFFFDC044) // (TC4) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC4_RC    (AT91_CAST(AT91_REG *) 	0xFFFDC05C) // (TC4) Register C
+#define AT91C_TC4_SR    (AT91_CAST(AT91_REG *) 	0xFFFDC060) // (TC4) Status Register
+#define AT91C_TC4_RB    (AT91_CAST(AT91_REG *) 	0xFFFDC058) // (TC4) Register B
+#define AT91C_TC4_IER   (AT91_CAST(AT91_REG *) 	0xFFFDC064) // (TC4) Interrupt Enable Register
+#define AT91C_TC4_CV    (AT91_CAST(AT91_REG *) 	0xFFFDC050) // (TC4) Counter Value
+#define AT91C_TC4_RA    (AT91_CAST(AT91_REG *) 	0xFFFDC054) // (TC4) Register A
+#define AT91C_TC4_IDR   (AT91_CAST(AT91_REG *) 	0xFFFDC068) // (TC4) Interrupt Disable Register
+#define AT91C_TC4_IMR   (AT91_CAST(AT91_REG *) 	0xFFFDC06C) // (TC4) Interrupt Mask Register
+#define AT91C_TC4_CCR   (AT91_CAST(AT91_REG *) 	0xFFFDC040) // (TC4) Channel Control Register
+// ========== Register definition for TC5 peripheral ========== 
+#define AT91C_TC5_RB    (AT91_CAST(AT91_REG *) 	0xFFFDC098) // (TC5) Register B
+#define AT91C_TC5_RA    (AT91_CAST(AT91_REG *) 	0xFFFDC094) // (TC5) Register A
+#define AT91C_TC5_CV    (AT91_CAST(AT91_REG *) 	0xFFFDC090) // (TC5) Counter Value
+#define AT91C_TC5_CCR   (AT91_CAST(AT91_REG *) 	0xFFFDC080) // (TC5) Channel Control Register
+#define AT91C_TC5_SR    (AT91_CAST(AT91_REG *) 	0xFFFDC0A0) // (TC5) Status Register
+#define AT91C_TC5_IER   (AT91_CAST(AT91_REG *) 	0xFFFDC0A4) // (TC5) Interrupt Enable Register
+#define AT91C_TC5_IDR   (AT91_CAST(AT91_REG *) 	0xFFFDC0A8) // (TC5) Interrupt Disable Register
+#define AT91C_TC5_RC    (AT91_CAST(AT91_REG *) 	0xFFFDC09C) // (TC5) Register C
+#define AT91C_TC5_IMR   (AT91_CAST(AT91_REG *) 	0xFFFDC0AC) // (TC5) Interrupt Mask Register
+#define AT91C_TC5_CMR   (AT91_CAST(AT91_REG *) 	0xFFFDC084) // (TC5) Channel Mode Register (Capture Mode / Waveform Mode)
+// ========== Register definition for TCB0 peripheral ========== 
+#define AT91C_TCB0_BMR  (AT91_CAST(AT91_REG *) 	0xFFFA00C4) // (TCB0) TC Block Mode Register
+#define AT91C_TCB0_BCR  (AT91_CAST(AT91_REG *) 	0xFFFA00C0) // (TCB0) TC Block Control Register
+// ========== Register definition for TCB1 peripheral ========== 
+#define AT91C_TCB1_BCR  (AT91_CAST(AT91_REG *) 	0xFFFDC0C0) // (TCB1) TC Block Control Register
+#define AT91C_TCB1_BMR  (AT91_CAST(AT91_REG *) 	0xFFFDC0C4) // (TCB1) TC Block Mode Register
+// ========== Register definition for PDC_MCI peripheral ========== 
+#define AT91C_MCI_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFA8114) // (PDC_MCI) Receive Next Counter Register
+#define AT91C_MCI_TCR   (AT91_CAST(AT91_REG *) 	0xFFFA810C) // (PDC_MCI) Transmit Counter Register
+#define AT91C_MCI_RCR   (AT91_CAST(AT91_REG *) 	0xFFFA8104) // (PDC_MCI) Receive Counter Register
+#define AT91C_MCI_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFA8118) // (PDC_MCI) Transmit Next Pointer Register
+#define AT91C_MCI_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFA8110) // (PDC_MCI) Receive Next Pointer Register
+#define AT91C_MCI_RPR   (AT91_CAST(AT91_REG *) 	0xFFFA8100) // (PDC_MCI) Receive Pointer Register
+#define AT91C_MCI_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFA811C) // (PDC_MCI) Transmit Next Counter Register
+#define AT91C_MCI_TPR   (AT91_CAST(AT91_REG *) 	0xFFFA8108) // (PDC_MCI) Transmit Pointer Register
+#define AT91C_MCI_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFA8124) // (PDC_MCI) PDC Transfer Status Register
+#define AT91C_MCI_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFA8120) // (PDC_MCI) PDC Transfer Control Register
+// ========== Register definition for MCI peripheral ========== 
+#define AT91C_MCI_RDR   (AT91_CAST(AT91_REG *) 	0xFFFA8030) // (MCI) MCI Receive Data Register
+#define AT91C_MCI_CMDR  (AT91_CAST(AT91_REG *) 	0xFFFA8014) // (MCI) MCI Command Register
+#define AT91C_MCI_VR    (AT91_CAST(AT91_REG *) 	0xFFFA80FC) // (MCI) MCI Version Register
+#define AT91C_MCI_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA8048) // (MCI) MCI Interrupt Disable Register
+#define AT91C_MCI_DTOR  (AT91_CAST(AT91_REG *) 	0xFFFA8008) // (MCI) MCI Data Timeout Register
+#define AT91C_MCI_TDR   (AT91_CAST(AT91_REG *) 	0xFFFA8034) // (MCI) MCI Transmit Data Register
+#define AT91C_MCI_IER   (AT91_CAST(AT91_REG *) 	0xFFFA8044) // (MCI) MCI Interrupt Enable Register
+#define AT91C_MCI_BLKR  (AT91_CAST(AT91_REG *) 	0xFFFA8018) // (MCI) MCI Block Register
+#define AT91C_MCI_MR    (AT91_CAST(AT91_REG *) 	0xFFFA8004) // (MCI) MCI Mode Register
+#define AT91C_MCI_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA804C) // (MCI) MCI Interrupt Mask Register
+#define AT91C_MCI_CR    (AT91_CAST(AT91_REG *) 	0xFFFA8000) // (MCI) MCI Control Register
+#define AT91C_MCI_ARGR  (AT91_CAST(AT91_REG *) 	0xFFFA8010) // (MCI) MCI Argument Register
+#define AT91C_MCI_SDCR  (AT91_CAST(AT91_REG *) 	0xFFFA800C) // (MCI) MCI SD Card Register
+#define AT91C_MCI_SR    (AT91_CAST(AT91_REG *) 	0xFFFA8040) // (MCI) MCI Status Register
+#define AT91C_MCI_RSPR  (AT91_CAST(AT91_REG *) 	0xFFFA8020) // (MCI) MCI Response Register
+// ========== Register definition for PDC_TWI0 peripheral ========== 
+#define AT91C_TWI0_PTSR (AT91_CAST(AT91_REG *) 	0xFFFAC124) // (PDC_TWI0) PDC Transfer Status Register
+#define AT91C_TWI0_RPR  (AT91_CAST(AT91_REG *) 	0xFFFAC100) // (PDC_TWI0) Receive Pointer Register
+#define AT91C_TWI0_RNCR (AT91_CAST(AT91_REG *) 	0xFFFAC114) // (PDC_TWI0) Receive Next Counter Register
+#define AT91C_TWI0_RCR  (AT91_CAST(AT91_REG *) 	0xFFFAC104) // (PDC_TWI0) Receive Counter Register
+#define AT91C_TWI0_PTCR (AT91_CAST(AT91_REG *) 	0xFFFAC120) // (PDC_TWI0) PDC Transfer Control Register
+#define AT91C_TWI0_TPR  (AT91_CAST(AT91_REG *) 	0xFFFAC108) // (PDC_TWI0) Transmit Pointer Register
+#define AT91C_TWI0_RNPR (AT91_CAST(AT91_REG *) 	0xFFFAC110) // (PDC_TWI0) Receive Next Pointer Register
+#define AT91C_TWI0_TNPR (AT91_CAST(AT91_REG *) 	0xFFFAC118) // (PDC_TWI0) Transmit Next Pointer Register
+#define AT91C_TWI0_TCR  (AT91_CAST(AT91_REG *) 	0xFFFAC10C) // (PDC_TWI0) Transmit Counter Register
+#define AT91C_TWI0_TNCR (AT91_CAST(AT91_REG *) 	0xFFFAC11C) // (PDC_TWI0) Transmit Next Counter Register
+// ========== Register definition for TWI0 peripheral ========== 
+#define AT91C_TWI0_THR  (AT91_CAST(AT91_REG *) 	0xFFFAC034) // (TWI0) Transmit Holding Register
+#define AT91C_TWI0_IDR  (AT91_CAST(AT91_REG *) 	0xFFFAC028) // (TWI0) Interrupt Disable Register
+#define AT91C_TWI0_SMR  (AT91_CAST(AT91_REG *) 	0xFFFAC008) // (TWI0) Slave Mode Register
+#define AT91C_TWI0_CWGR (AT91_CAST(AT91_REG *) 	0xFFFAC010) // (TWI0) Clock Waveform Generator Register
+#define AT91C_TWI0_IADR (AT91_CAST(AT91_REG *) 	0xFFFAC00C) // (TWI0) Internal Address Register
+#define AT91C_TWI0_RHR  (AT91_CAST(AT91_REG *) 	0xFFFAC030) // (TWI0) Receive Holding Register
+#define AT91C_TWI0_IER  (AT91_CAST(AT91_REG *) 	0xFFFAC024) // (TWI0) Interrupt Enable Register
+#define AT91C_TWI0_MMR  (AT91_CAST(AT91_REG *) 	0xFFFAC004) // (TWI0) Master Mode Register
+#define AT91C_TWI0_SR   (AT91_CAST(AT91_REG *) 	0xFFFAC020) // (TWI0) Status Register
+#define AT91C_TWI0_IMR  (AT91_CAST(AT91_REG *) 	0xFFFAC02C) // (TWI0) Interrupt Mask Register
+#define AT91C_TWI0_CR   (AT91_CAST(AT91_REG *) 	0xFFFAC000) // (TWI0) Control Register
+// ========== Register definition for PDC_TWI1 peripheral ========== 
+#define AT91C_TWI1_PTSR (AT91_CAST(AT91_REG *) 	0xFFFD8124) // (PDC_TWI1) PDC Transfer Status Register
+#define AT91C_TWI1_PTCR (AT91_CAST(AT91_REG *) 	0xFFFD8120) // (PDC_TWI1) PDC Transfer Control Register
+#define AT91C_TWI1_TNPR (AT91_CAST(AT91_REG *) 	0xFFFD8118) // (PDC_TWI1) Transmit Next Pointer Register
+#define AT91C_TWI1_TNCR (AT91_CAST(AT91_REG *) 	0xFFFD811C) // (PDC_TWI1) Transmit Next Counter Register
+#define AT91C_TWI1_RNPR (AT91_CAST(AT91_REG *) 	0xFFFD8110) // (PDC_TWI1) Receive Next Pointer Register
+#define AT91C_TWI1_RNCR (AT91_CAST(AT91_REG *) 	0xFFFD8114) // (PDC_TWI1) Receive Next Counter Register
+#define AT91C_TWI1_RPR  (AT91_CAST(AT91_REG *) 	0xFFFD8100) // (PDC_TWI1) Receive Pointer Register
+#define AT91C_TWI1_TCR  (AT91_CAST(AT91_REG *) 	0xFFFD810C) // (PDC_TWI1) Transmit Counter Register
+#define AT91C_TWI1_TPR  (AT91_CAST(AT91_REG *) 	0xFFFD8108) // (PDC_TWI1) Transmit Pointer Register
+#define AT91C_TWI1_RCR  (AT91_CAST(AT91_REG *) 	0xFFFD8104) // (PDC_TWI1) Receive Counter Register
+// ========== Register definition for TWI1 peripheral ========== 
+#define AT91C_TWI1_RHR  (AT91_CAST(AT91_REG *) 	0xFFFD8030) // (TWI1) Receive Holding Register
+#define AT91C_TWI1_IER  (AT91_CAST(AT91_REG *) 	0xFFFD8024) // (TWI1) Interrupt Enable Register
+#define AT91C_TWI1_CWGR (AT91_CAST(AT91_REG *) 	0xFFFD8010) // (TWI1) Clock Waveform Generator Register
+#define AT91C_TWI1_MMR  (AT91_CAST(AT91_REG *) 	0xFFFD8004) // (TWI1) Master Mode Register
+#define AT91C_TWI1_IADR (AT91_CAST(AT91_REG *) 	0xFFFD800C) // (TWI1) Internal Address Register
+#define AT91C_TWI1_THR  (AT91_CAST(AT91_REG *) 	0xFFFD8034) // (TWI1) Transmit Holding Register
+#define AT91C_TWI1_IMR  (AT91_CAST(AT91_REG *) 	0xFFFD802C) // (TWI1) Interrupt Mask Register
+#define AT91C_TWI1_SR   (AT91_CAST(AT91_REG *) 	0xFFFD8020) // (TWI1) Status Register
+#define AT91C_TWI1_IDR  (AT91_CAST(AT91_REG *) 	0xFFFD8028) // (TWI1) Interrupt Disable Register
+#define AT91C_TWI1_CR   (AT91_CAST(AT91_REG *) 	0xFFFD8000) // (TWI1) Control Register
+#define AT91C_TWI1_SMR  (AT91_CAST(AT91_REG *) 	0xFFFD8008) // (TWI1) Slave Mode Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_TCR   (AT91_CAST(AT91_REG *) 	0xFFFB010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFB0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFB0114) // (PDC_US0) Receive Next Counter Register
+#define AT91C_US0_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFB0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFB011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFB0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_RCR   (AT91_CAST(AT91_REG *) 	0xFFFB0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_TPR   (AT91_CAST(AT91_REG *) 	0xFFFB0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFB0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RPR   (AT91_CAST(AT91_REG *) 	0xFFFB0100) // (PDC_US0) Receive Pointer Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_RHR   (AT91_CAST(AT91_REG *) 	0xFFFB0018) // (US0) Receiver Holding Register
+#define AT91C_US0_NER   (AT91_CAST(AT91_REG *) 	0xFFFB0044) // (US0) Nb Errors Register
+#define AT91C_US0_IER   (AT91_CAST(AT91_REG *) 	0xFFFB0008) // (US0) Interrupt Enable Register
+#define AT91C_US0_CR    (AT91_CAST(AT91_REG *) 	0xFFFB0000) // (US0) Control Register
+#define AT91C_US0_THR   (AT91_CAST(AT91_REG *) 	0xFFFB001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_CSR   (AT91_CAST(AT91_REG *) 	0xFFFB0014) // (US0) Channel Status Register
+#define AT91C_US0_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFB0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFB0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFB0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_MR    (AT91_CAST(AT91_REG *) 	0xFFFB0004) // (US0) Mode Register
+#define AT91C_US0_IF    (AT91_CAST(AT91_REG *) 	0xFFFB004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFB0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB0010) // (US0) Interrupt Mask Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFB4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_RCR   (AT91_CAST(AT91_REG *) 	0xFFFB4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RPR   (AT91_CAST(AT91_REG *) 	0xFFFB4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFB4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TPR   (AT91_CAST(AT91_REG *) 	0xFFFB4108) // (PDC_US1) Transmit Pointer Register
+#define AT91C_US1_TCR   (AT91_CAST(AT91_REG *) 	0xFFFB410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFB4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFB411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFB4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFB4118) // (PDC_US1) Transmit Next Pointer Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_THR   (AT91_CAST(AT91_REG *) 	0xFFFB401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFB4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFB4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_MR    (AT91_CAST(AT91_REG *) 	0xFFFB4004) // (US1) Mode Register
+#define AT91C_US1_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFB4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CR    (AT91_CAST(AT91_REG *) 	0xFFFB4000) // (US1) Control Register
+#define AT91C_US1_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFB4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_RHR   (AT91_CAST(AT91_REG *) 	0xFFFB4018) // (US1) Receiver Holding Register
+#define AT91C_US1_IER   (AT91_CAST(AT91_REG *) 	0xFFFB4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_CSR   (AT91_CAST(AT91_REG *) 	0xFFFB4014) // (US1) Channel Status Register
+#define AT91C_US1_IF    (AT91_CAST(AT91_REG *) 	0xFFFB404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER   (AT91_CAST(AT91_REG *) 	0xFFFB4044) // (US1) Nb Errors Register
+// ========== Register definition for PDC_US2 peripheral ========== 
+#define AT91C_US2_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFB811C) // (PDC_US2) Transmit Next Counter Register
+#define AT91C_US2_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFB8114) // (PDC_US2) Receive Next Counter Register
+#define AT91C_US2_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFB8118) // (PDC_US2) Transmit Next Pointer Register
+#define AT91C_US2_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFB8120) // (PDC_US2) PDC Transfer Control Register
+#define AT91C_US2_TCR   (AT91_CAST(AT91_REG *) 	0xFFFB810C) // (PDC_US2) Transmit Counter Register
+#define AT91C_US2_RPR   (AT91_CAST(AT91_REG *) 	0xFFFB8100) // (PDC_US2) Receive Pointer Register
+#define AT91C_US2_TPR   (AT91_CAST(AT91_REG *) 	0xFFFB8108) // (PDC_US2) Transmit Pointer Register
+#define AT91C_US2_RCR   (AT91_CAST(AT91_REG *) 	0xFFFB8104) // (PDC_US2) Receive Counter Register
+#define AT91C_US2_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFB8124) // (PDC_US2) PDC Transfer Status Register
+#define AT91C_US2_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFB8110) // (PDC_US2) Receive Next Pointer Register
+// ========== Register definition for US2 peripheral ========== 
+#define AT91C_US2_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFB8024) // (US2) Receiver Time-out Register
+#define AT91C_US2_CSR   (AT91_CAST(AT91_REG *) 	0xFFFB8014) // (US2) Channel Status Register
+#define AT91C_US2_CR    (AT91_CAST(AT91_REG *) 	0xFFFB8000) // (US2) Control Register
+#define AT91C_US2_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFB8020) // (US2) Baud Rate Generator Register
+#define AT91C_US2_NER   (AT91_CAST(AT91_REG *) 	0xFFFB8044) // (US2) Nb Errors Register
+#define AT91C_US2_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFB8040) // (US2) FI_DI_Ratio Register
+#define AT91C_US2_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFB8028) // (US2) Transmitter Time-guard Register
+#define AT91C_US2_RHR   (AT91_CAST(AT91_REG *) 	0xFFFB8018) // (US2) Receiver Holding Register
+#define AT91C_US2_IDR   (AT91_CAST(AT91_REG *) 	0xFFFB800C) // (US2) Interrupt Disable Register
+#define AT91C_US2_THR   (AT91_CAST(AT91_REG *) 	0xFFFB801C) // (US2) Transmitter Holding Register
+#define AT91C_US2_MR    (AT91_CAST(AT91_REG *) 	0xFFFB8004) // (US2) Mode Register
+#define AT91C_US2_IMR   (AT91_CAST(AT91_REG *) 	0xFFFB8010) // (US2) Interrupt Mask Register
+#define AT91C_US2_IF    (AT91_CAST(AT91_REG *) 	0xFFFB804C) // (US2) IRDA_FILTER Register
+#define AT91C_US2_IER   (AT91_CAST(AT91_REG *) 	0xFFFB8008) // (US2) Interrupt Enable Register
+// ========== Register definition for PDC_US3 peripheral ========== 
+#define AT91C_US3_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFD0110) // (PDC_US3) Receive Next Pointer Register
+#define AT91C_US3_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFD0114) // (PDC_US3) Receive Next Counter Register
+#define AT91C_US3_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFD0124) // (PDC_US3) PDC Transfer Status Register
+#define AT91C_US3_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFD0120) // (PDC_US3) PDC Transfer Control Register
+#define AT91C_US3_TCR   (AT91_CAST(AT91_REG *) 	0xFFFD010C) // (PDC_US3) Transmit Counter Register
+#define AT91C_US3_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFD0118) // (PDC_US3) Transmit Next Pointer Register
+#define AT91C_US3_RCR   (AT91_CAST(AT91_REG *) 	0xFFFD0104) // (PDC_US3) Receive Counter Register
+#define AT91C_US3_TPR   (AT91_CAST(AT91_REG *) 	0xFFFD0108) // (PDC_US3) Transmit Pointer Register
+#define AT91C_US3_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFD011C) // (PDC_US3) Transmit Next Counter Register
+#define AT91C_US3_RPR   (AT91_CAST(AT91_REG *) 	0xFFFD0100) // (PDC_US3) Receive Pointer Register
+// ========== Register definition for US3 peripheral ========== 
+#define AT91C_US3_NER   (AT91_CAST(AT91_REG *) 	0xFFFD0044) // (US3) Nb Errors Register
+#define AT91C_US3_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFD0024) // (US3) Receiver Time-out Register
+#define AT91C_US3_IDR   (AT91_CAST(AT91_REG *) 	0xFFFD000C) // (US3) Interrupt Disable Register
+#define AT91C_US3_MR    (AT91_CAST(AT91_REG *) 	0xFFFD0004) // (US3) Mode Register
+#define AT91C_US3_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFD0040) // (US3) FI_DI_Ratio Register
+#define AT91C_US3_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFD0020) // (US3) Baud Rate Generator Register
+#define AT91C_US3_THR   (AT91_CAST(AT91_REG *) 	0xFFFD001C) // (US3) Transmitter Holding Register
+#define AT91C_US3_CR    (AT91_CAST(AT91_REG *) 	0xFFFD0000) // (US3) Control Register
+#define AT91C_US3_IF    (AT91_CAST(AT91_REG *) 	0xFFFD004C) // (US3) IRDA_FILTER Register
+#define AT91C_US3_IER   (AT91_CAST(AT91_REG *) 	0xFFFD0008) // (US3) Interrupt Enable Register
+#define AT91C_US3_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFD0028) // (US3) Transmitter Time-guard Register
+#define AT91C_US3_RHR   (AT91_CAST(AT91_REG *) 	0xFFFD0018) // (US3) Receiver Holding Register
+#define AT91C_US3_IMR   (AT91_CAST(AT91_REG *) 	0xFFFD0010) // (US3) Interrupt Mask Register
+#define AT91C_US3_CSR   (AT91_CAST(AT91_REG *) 	0xFFFD0014) // (US3) Channel Status Register
+// ========== Register definition for PDC_US4 peripheral ========== 
+#define AT91C_US4_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFD411C) // (PDC_US4) Transmit Next Counter Register
+#define AT91C_US4_RPR   (AT91_CAST(AT91_REG *) 	0xFFFD4100) // (PDC_US4) Receive Pointer Register
+#define AT91C_US4_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFD4114) // (PDC_US4) Receive Next Counter Register
+#define AT91C_US4_TPR   (AT91_CAST(AT91_REG *) 	0xFFFD4108) // (PDC_US4) Transmit Pointer Register
+#define AT91C_US4_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFD4120) // (PDC_US4) PDC Transfer Control Register
+#define AT91C_US4_TCR   (AT91_CAST(AT91_REG *) 	0xFFFD410C) // (PDC_US4) Transmit Counter Register
+#define AT91C_US4_RCR   (AT91_CAST(AT91_REG *) 	0xFFFD4104) // (PDC_US4) Receive Counter Register
+#define AT91C_US4_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFD4110) // (PDC_US4) Receive Next Pointer Register
+#define AT91C_US4_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFD4118) // (PDC_US4) Transmit Next Pointer Register
+#define AT91C_US4_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFD4124) // (PDC_US4) PDC Transfer Status Register
+// ========== Register definition for US4 peripheral ========== 
+#define AT91C_US4_BRGR  (AT91_CAST(AT91_REG *) 	0xFFFD4020) // (US4) Baud Rate Generator Register
+#define AT91C_US4_THR   (AT91_CAST(AT91_REG *) 	0xFFFD401C) // (US4) Transmitter Holding Register
+#define AT91C_US4_RTOR  (AT91_CAST(AT91_REG *) 	0xFFFD4024) // (US4) Receiver Time-out Register
+#define AT91C_US4_IMR   (AT91_CAST(AT91_REG *) 	0xFFFD4010) // (US4) Interrupt Mask Register
+#define AT91C_US4_NER   (AT91_CAST(AT91_REG *) 	0xFFFD4044) // (US4) Nb Errors Register
+#define AT91C_US4_TTGR  (AT91_CAST(AT91_REG *) 	0xFFFD4028) // (US4) Transmitter Time-guard Register
+#define AT91C_US4_FIDI  (AT91_CAST(AT91_REG *) 	0xFFFD4040) // (US4) FI_DI_Ratio Register
+#define AT91C_US4_MR    (AT91_CAST(AT91_REG *) 	0xFFFD4004) // (US4) Mode Register
+#define AT91C_US4_IER   (AT91_CAST(AT91_REG *) 	0xFFFD4008) // (US4) Interrupt Enable Register
+#define AT91C_US4_RHR   (AT91_CAST(AT91_REG *) 	0xFFFD4018) // (US4) Receiver Holding Register
+#define AT91C_US4_CR    (AT91_CAST(AT91_REG *) 	0xFFFD4000) // (US4) Control Register
+#define AT91C_US4_IF    (AT91_CAST(AT91_REG *) 	0xFFFD404C) // (US4) IRDA_FILTER Register
+#define AT91C_US4_IDR   (AT91_CAST(AT91_REG *) 	0xFFFD400C) // (US4) Interrupt Disable Register
+#define AT91C_US4_CSR   (AT91_CAST(AT91_REG *) 	0xFFFD4014) // (US4) Channel Status Register
+// ========== Register definition for PDC_SSC0 peripheral ========== 
+#define AT91C_SSC0_TNPR (AT91_CAST(AT91_REG *) 	0xFFFBC118) // (PDC_SSC0) Transmit Next Pointer Register
+#define AT91C_SSC0_TCR  (AT91_CAST(AT91_REG *) 	0xFFFBC10C) // (PDC_SSC0) Transmit Counter Register
+#define AT91C_SSC0_RNCR (AT91_CAST(AT91_REG *) 	0xFFFBC114) // (PDC_SSC0) Receive Next Counter Register
+#define AT91C_SSC0_RPR  (AT91_CAST(AT91_REG *) 	0xFFFBC100) // (PDC_SSC0) Receive Pointer Register
+#define AT91C_SSC0_TPR  (AT91_CAST(AT91_REG *) 	0xFFFBC108) // (PDC_SSC0) Transmit Pointer Register
+#define AT91C_SSC0_RCR  (AT91_CAST(AT91_REG *) 	0xFFFBC104) // (PDC_SSC0) Receive Counter Register
+#define AT91C_SSC0_RNPR (AT91_CAST(AT91_REG *) 	0xFFFBC110) // (PDC_SSC0) Receive Next Pointer Register
+#define AT91C_SSC0_PTCR (AT91_CAST(AT91_REG *) 	0xFFFBC120) // (PDC_SSC0) PDC Transfer Control Register
+#define AT91C_SSC0_TNCR (AT91_CAST(AT91_REG *) 	0xFFFBC11C) // (PDC_SSC0) Transmit Next Counter Register
+#define AT91C_SSC0_PTSR (AT91_CAST(AT91_REG *) 	0xFFFBC124) // (PDC_SSC0) PDC Transfer Status Register
+// ========== Register definition for SSC0 peripheral ========== 
+#define AT91C_SSC0_IMR  (AT91_CAST(AT91_REG *) 	0xFFFBC04C) // (SSC0) Interrupt Mask Register
+#define AT91C_SSC0_RFMR (AT91_CAST(AT91_REG *) 	0xFFFBC014) // (SSC0) Receive Frame Mode Register
+#define AT91C_SSC0_CR   (AT91_CAST(AT91_REG *) 	0xFFFBC000) // (SSC0) Control Register
+#define AT91C_SSC0_TFMR (AT91_CAST(AT91_REG *) 	0xFFFBC01C) // (SSC0) Transmit Frame Mode Register
+#define AT91C_SSC0_CMR  (AT91_CAST(AT91_REG *) 	0xFFFBC004) // (SSC0) Clock Mode Register
+#define AT91C_SSC0_IER  (AT91_CAST(AT91_REG *) 	0xFFFBC044) // (SSC0) Interrupt Enable Register
+#define AT91C_SSC0_RHR  (AT91_CAST(AT91_REG *) 	0xFFFBC020) // (SSC0) Receive Holding Register
+#define AT91C_SSC0_RCMR (AT91_CAST(AT91_REG *) 	0xFFFBC010) // (SSC0) Receive Clock ModeRegister
+#define AT91C_SSC0_SR   (AT91_CAST(AT91_REG *) 	0xFFFBC040) // (SSC0) Status Register
+#define AT91C_SSC0_RSHR (AT91_CAST(AT91_REG *) 	0xFFFBC030) // (SSC0) Receive Sync Holding Register
+#define AT91C_SSC0_THR  (AT91_CAST(AT91_REG *) 	0xFFFBC024) // (SSC0) Transmit Holding Register
+#define AT91C_SSC0_TCMR (AT91_CAST(AT91_REG *) 	0xFFFBC018) // (SSC0) Transmit Clock Mode Register
+#define AT91C_SSC0_IDR  (AT91_CAST(AT91_REG *) 	0xFFFBC048) // (SSC0) Interrupt Disable Register
+#define AT91C_SSC0_TSHR (AT91_CAST(AT91_REG *) 	0xFFFBC034) // (SSC0) Transmit Sync Holding Register
+// ========== Register definition for PDC_SPI0 peripheral ========== 
+#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 	0xFFFC8120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TCR  (AT91_CAST(AT91_REG *) 	0xFFFC810C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RPR  (AT91_CAST(AT91_REG *) 	0xFFFC8100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TPR  (AT91_CAST(AT91_REG *) 	0xFFFC8108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 	0xFFFC8124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 	0xFFFC8114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 	0xFFFC8118) // (PDC_SPI0) Transmit Next Pointer Register
+#define AT91C_SPI0_RCR  (AT91_CAST(AT91_REG *) 	0xFFFC8104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 	0xFFFC8110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 	0xFFFC811C) // (PDC_SPI0) Transmit Next Counter Register
+// ========== Register definition for SPI0 peripheral ========== 
+#define AT91C_SPI0_IDR  (AT91_CAST(AT91_REG *) 	0xFFFC8018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_TDR  (AT91_CAST(AT91_REG *) 	0xFFFC800C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_SR   (AT91_CAST(AT91_REG *) 	0xFFFC8010) // (SPI0) Status Register
+#define AT91C_SPI0_CR   (AT91_CAST(AT91_REG *) 	0xFFFC8000) // (SPI0) Control Register
+#define AT91C_SPI0_CSR  (AT91_CAST(AT91_REG *) 	0xFFFC8030) // (SPI0) Chip Select Register
+#define AT91C_SPI0_RDR  (AT91_CAST(AT91_REG *) 	0xFFFC8008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_MR   (AT91_CAST(AT91_REG *) 	0xFFFC8004) // (SPI0) Mode Register
+#define AT91C_SPI0_IER  (AT91_CAST(AT91_REG *) 	0xFFFC8014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_IMR  (AT91_CAST(AT91_REG *) 	0xFFFC801C) // (SPI0) Interrupt Mask Register
+// ========== Register definition for PDC_SPI1 peripheral ========== 
+#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 	0xFFFCC120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 	0xFFFCC110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RCR  (AT91_CAST(AT91_REG *) 	0xFFFCC104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_TPR  (AT91_CAST(AT91_REG *) 	0xFFFCC108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 	0xFFFCC124) // (PDC_SPI1) PDC Transfer Status Register
+#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 	0xFFFCC11C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_RPR  (AT91_CAST(AT91_REG *) 	0xFFFCC100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TCR  (AT91_CAST(AT91_REG *) 	0xFFFCC10C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 	0xFFFCC114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 	0xFFFCC118) // (PDC_SPI1) Transmit Next Pointer Register
+// ========== Register definition for SPI1 peripheral ========== 
+#define AT91C_SPI1_IER  (AT91_CAST(AT91_REG *) 	0xFFFCC014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_RDR  (AT91_CAST(AT91_REG *) 	0xFFFCC008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_SR   (AT91_CAST(AT91_REG *) 	0xFFFCC010) // (SPI1) Status Register
+#define AT91C_SPI1_IMR  (AT91_CAST(AT91_REG *) 	0xFFFCC01C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_TDR  (AT91_CAST(AT91_REG *) 	0xFFFCC00C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_IDR  (AT91_CAST(AT91_REG *) 	0xFFFCC018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_CSR  (AT91_CAST(AT91_REG *) 	0xFFFCC030) // (SPI1) Chip Select Register
+#define AT91C_SPI1_CR   (AT91_CAST(AT91_REG *) 	0xFFFCC000) // (SPI1) Control Register
+#define AT91C_SPI1_MR   (AT91_CAST(AT91_REG *) 	0xFFFCC004) // (SPI1) Mode Register
+// ========== Register definition for PDC_ADC peripheral ========== 
+#define AT91C_ADC_PTCR  (AT91_CAST(AT91_REG *) 	0xFFFE0120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TPR   (AT91_CAST(AT91_REG *) 	0xFFFE0108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_TCR   (AT91_CAST(AT91_REG *) 	0xFFFE010C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_RCR   (AT91_CAST(AT91_REG *) 	0xFFFE0104) // (PDC_ADC) Receive Counter Register
+#define AT91C_ADC_PTSR  (AT91_CAST(AT91_REG *) 	0xFFFE0124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_RNPR  (AT91_CAST(AT91_REG *) 	0xFFFE0110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RPR   (AT91_CAST(AT91_REG *) 	0xFFFE0100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TNCR  (AT91_CAST(AT91_REG *) 	0xFFFE011C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNCR  (AT91_CAST(AT91_REG *) 	0xFFFE0114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_TNPR  (AT91_CAST(AT91_REG *) 	0xFFFE0118) // (PDC_ADC) Transmit Next Pointer Register
+// ========== Register definition for ADC peripheral ========== 
+#define AT91C_ADC_CHDR  (AT91_CAST(AT91_REG *) 	0xFFFE0014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_CDR3  (AT91_CAST(AT91_REG *) 	0xFFFE003C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CR    (AT91_CAST(AT91_REG *) 	0xFFFE0000) // (ADC) ADC Control Register
+#define AT91C_ADC_IMR   (AT91_CAST(AT91_REG *) 	0xFFFE002C) // (ADC) ADC Interrupt Mask Register
+#define AT91C_ADC_CDR2  (AT91_CAST(AT91_REG *) 	0xFFFE0038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_SR    (AT91_CAST(AT91_REG *) 	0xFFFE001C) // (ADC) ADC Status Register
+#define AT91C_ADC_IER   (AT91_CAST(AT91_REG *) 	0xFFFE0024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CDR7  (AT91_CAST(AT91_REG *) 	0xFFFE004C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR0  (AT91_CAST(AT91_REG *) 	0xFFFE0030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5  (AT91_CAST(AT91_REG *) 	0xFFFE0044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CDR4  (AT91_CAST(AT91_REG *) 	0xFFFE0040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CHER  (AT91_CAST(AT91_REG *) 	0xFFFE0010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR  (AT91_CAST(AT91_REG *) 	0xFFFE0018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR    (AT91_CAST(AT91_REG *) 	0xFFFE0004) // (ADC) ADC Mode Register
+#define AT91C_ADC_CDR6  (AT91_CAST(AT91_REG *) 	0xFFFE0048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_LCDR  (AT91_CAST(AT91_REG *) 	0xFFFE0020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_CDR1  (AT91_CAST(AT91_REG *) 	0xFFFE0034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_IDR   (AT91_CAST(AT91_REG *) 	0xFFFE0028) // (ADC) ADC Interrupt Disable Register
+// ========== Register definition for EMACB peripheral ========== 
+#define AT91C_EMACB_USRIO (AT91_CAST(AT91_REG *) 	0xFFFC40C0) // (EMACB) USER Input/Output Register
+#define AT91C_EMACB_RSE (AT91_CAST(AT91_REG *) 	0xFFFC4074) // (EMACB) Receive Symbol Errors Register
+#define AT91C_EMACB_SCF (AT91_CAST(AT91_REG *) 	0xFFFC4044) // (EMACB) Single Collision Frame Register
+#define AT91C_EMACB_STE (AT91_CAST(AT91_REG *) 	0xFFFC4084) // (EMACB) SQE Test Error Register
+#define AT91C_EMACB_SA1H (AT91_CAST(AT91_REG *) 	0xFFFC409C) // (EMACB) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMACB_ROV (AT91_CAST(AT91_REG *) 	0xFFFC4070) // (EMACB) Receive Overrun Errors Register
+#define AT91C_EMACB_TBQP (AT91_CAST(AT91_REG *) 	0xFFFC401C) // (EMACB) Transmit Buffer Queue Pointer
+#define AT91C_EMACB_IMR (AT91_CAST(AT91_REG *) 	0xFFFC4030) // (EMACB) Interrupt Mask Register
+#define AT91C_EMACB_IER (AT91_CAST(AT91_REG *) 	0xFFFC4028) // (EMACB) Interrupt Enable Register
+#define AT91C_EMACB_REV (AT91_CAST(AT91_REG *) 	0xFFFC40FC) // (EMACB) Revision Register
+#define AT91C_EMACB_SA3L (AT91_CAST(AT91_REG *) 	0xFFFC40A8) // (EMACB) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMACB_ELE (AT91_CAST(AT91_REG *) 	0xFFFC4078) // (EMACB) Excessive Length Errors Register
+#define AT91C_EMACB_HRT (AT91_CAST(AT91_REG *) 	0xFFFC4094) // (EMACB) Hash Address Top[63:32]
+#define AT91C_EMACB_SA2L (AT91_CAST(AT91_REG *) 	0xFFFC40A0) // (EMACB) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMACB_RRE (AT91_CAST(AT91_REG *) 	0xFFFC406C) // (EMACB) Receive Ressource Error Register
+#define AT91C_EMACB_FRO (AT91_CAST(AT91_REG *) 	0xFFFC404C) // (EMACB) Frames Received OK Register
+#define AT91C_EMACB_TPQ (AT91_CAST(AT91_REG *) 	0xFFFC40BC) // (EMACB) Transmit Pause Quantum Register
+#define AT91C_EMACB_ISR (AT91_CAST(AT91_REG *) 	0xFFFC4024) // (EMACB) Interrupt Status Register
+#define AT91C_EMACB_TSR (AT91_CAST(AT91_REG *) 	0xFFFC4014) // (EMACB) Transmit Status Register
+#define AT91C_EMACB_RLE (AT91_CAST(AT91_REG *) 	0xFFFC4088) // (EMACB) Receive Length Field Mismatch Register
+#define AT91C_EMACB_USF (AT91_CAST(AT91_REG *) 	0xFFFC4080) // (EMACB) Undersize Frames Register
+#define AT91C_EMACB_WOL (AT91_CAST(AT91_REG *) 	0xFFFC40C4) // (EMACB) Wake On LAN Register
+#define AT91C_EMACB_TPF (AT91_CAST(AT91_REG *) 	0xFFFC408C) // (EMACB) Transmitted Pause Frames Register
+#define AT91C_EMACB_PTR (AT91_CAST(AT91_REG *) 	0xFFFC4038) // (EMACB) Pause Time Register
+#define AT91C_EMACB_TUND (AT91_CAST(AT91_REG *) 	0xFFFC4064) // (EMACB) Transmit Underrun Error Register
+#define AT91C_EMACB_MAN (AT91_CAST(AT91_REG *) 	0xFFFC4034) // (EMACB) PHY Maintenance Register
+#define AT91C_EMACB_RJA (AT91_CAST(AT91_REG *) 	0xFFFC407C) // (EMACB) Receive Jabbers Register
+#define AT91C_EMACB_SA4L (AT91_CAST(AT91_REG *) 	0xFFFC40B0) // (EMACB) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMACB_CSE (AT91_CAST(AT91_REG *) 	0xFFFC4068) // (EMACB) Carrier Sense Error Register
+#define AT91C_EMACB_HRB (AT91_CAST(AT91_REG *) 	0xFFFC4090) // (EMACB) Hash Address Bottom[31:0]
+#define AT91C_EMACB_ALE (AT91_CAST(AT91_REG *) 	0xFFFC4054) // (EMACB) Alignment Error Register
+#define AT91C_EMACB_SA1L (AT91_CAST(AT91_REG *) 	0xFFFC4098) // (EMACB) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMACB_NCR (AT91_CAST(AT91_REG *) 	0xFFFC4000) // (EMACB) Network Control Register
+#define AT91C_EMACB_FTO (AT91_CAST(AT91_REG *) 	0xFFFC4040) // (EMACB) Frames Transmitted OK Register
+#define AT91C_EMACB_ECOL (AT91_CAST(AT91_REG *) 	0xFFFC4060) // (EMACB) Excessive Collision Register
+#define AT91C_EMACB_DTF (AT91_CAST(AT91_REG *) 	0xFFFC4058) // (EMACB) Deferred Transmission Frame Register
+#define AT91C_EMACB_SA4H (AT91_CAST(AT91_REG *) 	0xFFFC40B4) // (EMACB) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMACB_FCSE (AT91_CAST(AT91_REG *) 	0xFFFC4050) // (EMACB) Frame Check Sequence Error Register
+#define AT91C_EMACB_TID (AT91_CAST(AT91_REG *) 	0xFFFC40B8) // (EMACB) Type ID Checking Register
+#define AT91C_EMACB_PFR (AT91_CAST(AT91_REG *) 	0xFFFC403C) // (EMACB) Pause Frames received Register
+#define AT91C_EMACB_IDR (AT91_CAST(AT91_REG *) 	0xFFFC402C) // (EMACB) Interrupt Disable Register
+#define AT91C_EMACB_SA3H (AT91_CAST(AT91_REG *) 	0xFFFC40AC) // (EMACB) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMACB_NSR (AT91_CAST(AT91_REG *) 	0xFFFC4008) // (EMACB) Network Status Register
+#define AT91C_EMACB_MCF (AT91_CAST(AT91_REG *) 	0xFFFC4048) // (EMACB) Multiple Collision Frame Register
+#define AT91C_EMACB_RBQP (AT91_CAST(AT91_REG *) 	0xFFFC4018) // (EMACB) Receive Buffer Queue Pointer
+#define AT91C_EMACB_RSR (AT91_CAST(AT91_REG *) 	0xFFFC4020) // (EMACB) Receive Status Register
+#define AT91C_EMACB_SA2H (AT91_CAST(AT91_REG *) 	0xFFFC40A4) // (EMACB) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMACB_NCFGR (AT91_CAST(AT91_REG *) 	0xFFFC4004) // (EMACB) Network Configuration Register
+#define AT91C_EMACB_LCOL (AT91_CAST(AT91_REG *) 	0xFFFC405C) // (EMACB) Late Collision Register
+// ========== Register definition for UDP peripheral ========== 
+#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 	0xFFFA4004) // (UDP) Global State Register
+#define AT91C_UDP_FDR   (AT91_CAST(AT91_REG *) 	0xFFFA4050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 	0xFFFA4028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 	0xFFFA4008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM   (AT91_CAST(AT91_REG *) 	0xFFFA4000) // (UDP) Frame Number Register
+#define AT91C_UDP_IDR   (AT91_CAST(AT91_REG *) 	0xFFFA4014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_IMR   (AT91_CAST(AT91_REG *) 	0xFFFA4018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_CSR   (AT91_CAST(AT91_REG *) 	0xFFFA4030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IER   (AT91_CAST(AT91_REG *) 	0xFFFA4010) // (UDP) Interrupt Enable Register
+#define AT91C_UDP_ICR   (AT91_CAST(AT91_REG *) 	0xFFFA4020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_TXVC  (AT91_CAST(AT91_REG *) 	0xFFFA4074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_ISR   (AT91_CAST(AT91_REG *) 	0xFFFA401C) // (UDP) Interrupt Status Register
+// ========== Register definition for UHP peripheral ========== 
+#define AT91C_UHP_HcInterruptStatus (AT91_CAST(AT91_REG *) 	0x0050000C) // (UHP) Interrupt Status Register
+#define AT91C_UHP_HcCommandStatus (AT91_CAST(AT91_REG *) 	0x00500008) // (UHP) Command & status Register
+#define AT91C_UHP_HcRhStatus (AT91_CAST(AT91_REG *) 	0x00500050) // (UHP) Root Hub Status register
+#define AT91C_UHP_HcInterruptDisable (AT91_CAST(AT91_REG *) 	0x00500014) // (UHP) Interrupt Disable Register
+#define AT91C_UHP_HcPeriodicStart (AT91_CAST(AT91_REG *) 	0x00500040) // (UHP) Periodic Start
+#define AT91C_UHP_HcControlCurrentED (AT91_CAST(AT91_REG *) 	0x00500024) // (UHP) Endpoint Control and Status Register
+#define AT91C_UHP_HcPeriodCurrentED (AT91_CAST(AT91_REG *) 	0x0050001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor
+#define AT91C_UHP_HcBulkHeadED (AT91_CAST(AT91_REG *) 	0x00500028) // (UHP) First endpoint register of the Bulk list
+#define AT91C_UHP_HcRevision (AT91_CAST(AT91_REG *) 	0x00500000) // (UHP) Revision
+#define AT91C_UHP_HcBulkCurrentED (AT91_CAST(AT91_REG *) 	0x0050002C) // (UHP) Current endpoint of the Bulk list
+#define AT91C_UHP_HcRhDescriptorB (AT91_CAST(AT91_REG *) 	0x0050004C) // (UHP) Root Hub characteristics B
+#define AT91C_UHP_HcControlHeadED (AT91_CAST(AT91_REG *) 	0x00500020) // (UHP) First Endpoint Descriptor of the Control list
+#define AT91C_UHP_HcFmRemaining (AT91_CAST(AT91_REG *) 	0x00500038) // (UHP) Bit time remaining in the current Frame
+#define AT91C_UHP_HcHCCA (AT91_CAST(AT91_REG *) 	0x00500018) // (UHP) Pointer to the Host Controller Communication Area
+#define AT91C_UHP_HcLSThreshold (AT91_CAST(AT91_REG *) 	0x00500044) // (UHP) LS Threshold
+#define AT91C_UHP_HcRhPortStatus (AT91_CAST(AT91_REG *) 	0x00500054) // (UHP) Root Hub Port Status Register
+#define AT91C_UHP_HcInterruptEnable (AT91_CAST(AT91_REG *) 	0x00500010) // (UHP) Interrupt Enable Register
+#define AT91C_UHP_HcFmNumber (AT91_CAST(AT91_REG *) 	0x0050003C) // (UHP) Frame number
+#define AT91C_UHP_HcFmInterval (AT91_CAST(AT91_REG *) 	0x00500034) // (UHP) Bit time between 2 consecutive SOFs
+#define AT91C_UHP_HcControl (AT91_CAST(AT91_REG *) 	0x00500004) // (UHP) Operating modes for the Host Controller
+#define AT91C_UHP_HcBulkDoneHead (AT91_CAST(AT91_REG *) 	0x00500030) // (UHP) Last completed transfer descriptor
+#define AT91C_UHP_HcRhDescriptorA (AT91_CAST(AT91_REG *) 	0x00500048) // (UHP) Root Hub characteristics A
+// ========== Register definition for HECC peripheral ========== 
+// ========== Register definition for HISI peripheral ========== 
+#define AT91C_HISI_PSIZE (AT91_CAST(AT91_REG *) 	0xFFFC0020) // (HISI) Preview Size Register
+#define AT91C_HISI_CR1  (AT91_CAST(AT91_REG *) 	0xFFFC0000) // (HISI) Control Register 1
+#define AT91C_HISI_R2YSET1 (AT91_CAST(AT91_REG *) 	0xFFFC003C) // (HISI) Color Space Conversion Register
+#define AT91C_HISI_CDBA (AT91_CAST(AT91_REG *) 	0xFFFC002C) // (HISI) Codec Dma Address Register
+#define AT91C_HISI_IDR  (AT91_CAST(AT91_REG *) 	0xFFFC0010) // (HISI) Interrupt Disable Register
+#define AT91C_HISI_R2YSET2 (AT91_CAST(AT91_REG *) 	0xFFFC0040) // (HISI) Color Space Conversion Register
+#define AT91C_HISI_Y2RSET1 (AT91_CAST(AT91_REG *) 	0xFFFC0034) // (HISI) Color Space Conversion Register
+#define AT91C_HISI_PFBD (AT91_CAST(AT91_REG *) 	0xFFFC0028) // (HISI) Preview Frame Buffer Address Register
+#define AT91C_HISI_CR2  (AT91_CAST(AT91_REG *) 	0xFFFC0004) // (HISI) Control Register 2
+#define AT91C_HISI_Y2RSET0 (AT91_CAST(AT91_REG *) 	0xFFFC0030) // (HISI) Color Space Conversion Register
+#define AT91C_HISI_PDECF (AT91_CAST(AT91_REG *) 	0xFFFC0024) // (HISI) Preview Decimation Factor Register
+#define AT91C_HISI_IMR  (AT91_CAST(AT91_REG *) 	0xFFFC0014) // (HISI) Interrupt Mask Register
+#define AT91C_HISI_IER  (AT91_CAST(AT91_REG *) 	0xFFFC000C) // (HISI) Interrupt Enable Register
+#define AT91C_HISI_R2YSET0 (AT91_CAST(AT91_REG *) 	0xFFFC0038) // (HISI) Color Space Conversion Register
+#define AT91C_HISI_SR   (AT91_CAST(AT91_REG *) 	0xFFFC0008) // (HISI) Status Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM9XE512
+// *****************************************************************************
+#define AT91C_PIO_PA0        (1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_SPI0_MISO (AT91C_PIO_PA0) //  SPI 0 Master In Slave
+#define AT91C_PA0_MCDB0    (AT91C_PIO_PA0) //  Multimedia Card B Data 0
+#define AT91C_PIO_PA1        (1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_SPI0_MOSI (AT91C_PIO_PA1) //  SPI 0 Master Out Slave
+#define AT91C_PA1_MCCDB    (AT91C_PIO_PA1) //  Multimedia Card B Command
+#define AT91C_PIO_PA10       (1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_MCDA2    (AT91C_PIO_PA10) //  Multimedia Card A Data 2
+#define AT91C_PA10_ETX2_0   (AT91C_PIO_PA10) //  Ethernet MAC Transmit Data 2
+#define AT91C_PIO_PA11       (1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_MCDA3    (AT91C_PIO_PA11) //  Multimedia Card A Data 3
+#define AT91C_PA11_ETX3_0   (AT91C_PIO_PA11) //  Ethernet MAC Transmit Data 3
+#define AT91C_PIO_PA12       (1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_ETX0     (AT91C_PIO_PA12) //  Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PA13       (1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_ETX1     (AT91C_PIO_PA13) //  Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PA14       (1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_ERX0     (AT91C_PIO_PA14) //  Ethernet MAC Receive Data 0
+#define AT91C_PIO_PA15       (1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_ERX1     (AT91C_PIO_PA15) //  Ethernet MAC Receive Data 1
+#define AT91C_PIO_PA16       (1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_ETXEN    (AT91C_PIO_PA16) //  Ethernet MAC Transmit Enable
+#define AT91C_PIO_PA17       (1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_ERXDV    (AT91C_PIO_PA17) //  Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PA18       (1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_ERXER    (AT91C_PIO_PA18) //  Ethernet MAC Receive Error
+#define AT91C_PIO_PA19       (1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_ETXCK    (AT91C_PIO_PA19) //  Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PIO_PA2        (1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_SPI0_SPCK (AT91C_PIO_PA2) //  SPI 0 Serial Clock
+#define AT91C_PIO_PA20       (1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_EMDC     (AT91C_PIO_PA20) //  Ethernet MAC Management Data Clock
+#define AT91C_PIO_PA21       (1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_EMDIO    (AT91C_PIO_PA21) //  Ethernet MAC Management Data Input/Output
+#define AT91C_PIO_PA22       (1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_ADTRG    (AT91C_PIO_PA22) //  ADC Trigger
+#define AT91C_PA22_ETXER    (AT91C_PIO_PA22) //  Ethernet MAC Transmikt Coding Error
+#define AT91C_PIO_PA23       (1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TWD0     (AT91C_PIO_PA23) //  TWI Two-wire Serial Data 0
+#define AT91C_PA23_ETX2_1   (AT91C_PIO_PA23) //  Ethernet MAC Transmit Data 2
+#define AT91C_PIO_PA24       (1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_TWCK0    (AT91C_PIO_PA24) //  TWI Two-wire Serial Clock 0
+#define AT91C_PA24_ETX3_1   (AT91C_PIO_PA24) //  Ethernet MAC Transmit Data 3
+#define AT91C_PIO_PA25       (1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_TCLK0    (AT91C_PIO_PA25) //  Timer Counter 0 external clock input
+#define AT91C_PA25_ERX2     (AT91C_PIO_PA25) //  Ethernet MAC Receive Data 2
+#define AT91C_PIO_PA26       (1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_TIOA0    (AT91C_PIO_PA26) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PA26_ERX3     (AT91C_PIO_PA26) //  Ethernet MAC Receive Data 3
+#define AT91C_PIO_PA27       (1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_TIOA1    (AT91C_PIO_PA27) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PA27_ERXCK    (AT91C_PIO_PA27) //  Ethernet MAC Receive Clock
+#define AT91C_PIO_PA28       (1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_TIOA2    (AT91C_PIO_PA28) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PA28_ECRS     (AT91C_PIO_PA28) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PA29       (1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_SCK1     (AT91C_PIO_PA29) //  USART 1 Serial Clock
+#define AT91C_PA29_ECOL     (AT91C_PIO_PA29) //  Ethernet MAC Collision Detected
+#define AT91C_PIO_PA3        (1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_SPI0_NPCS0 (AT91C_PIO_PA3) //  SPI 0 Peripheral Chip Select 0
+#define AT91C_PA3_MCDB3    (AT91C_PIO_PA3) //  Multimedia Card B Data 3
+#define AT91C_PIO_PA30       (1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_SCK2     (AT91C_PIO_PA30) //  USART 2 Serial Clock
+#define AT91C_PA30_RXD4     (AT91C_PIO_PA30) //  USART 4 Receive Data
+#define AT91C_PIO_PA31       (1 << 31) // Pin Controlled by PA31
+#define AT91C_PA31_SCK0     (AT91C_PIO_PA31) //  USART 0 Serial Clock
+#define AT91C_PA31_TXD4     (AT91C_PIO_PA31) //  USART 4 Transmit Data
+#define AT91C_PIO_PA4        (1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_RTS2     (AT91C_PIO_PA4) //  USART 2 Ready To Send
+#define AT91C_PA4_MCDB2    (AT91C_PIO_PA4) //  Multimedia Card B Data 2
+#define AT91C_PIO_PA5        (1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_CTS2     (AT91C_PIO_PA5) //  USART 2 Clear To Send
+#define AT91C_PA5_MCDB1    (AT91C_PIO_PA5) //  Multimedia Card B Data 1
+#define AT91C_PIO_PA6        (1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_MCDA0    (AT91C_PIO_PA6) //  Multimedia Card A Data 0
+#define AT91C_PIO_PA7        (1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_MCCDA    (AT91C_PIO_PA7) //  Multimedia Card A Command
+#define AT91C_PIO_PA8        (1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_MCCK     (AT91C_PIO_PA8) //  Multimedia Card Clock
+#define AT91C_PIO_PA9        (1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_MCDA1    (AT91C_PIO_PA9) //  Multimedia Card A Data 1
+#define AT91C_PIO_PB0        (1 <<  0) // Pin Controlled by PB0
+#define AT91C_PB0_SPI1_MISO (AT91C_PIO_PB0) //  SPI 1 Master In Slave
+#define AT91C_PB0_TIOA3    (AT91C_PIO_PB0) //  Timer Counter 3 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PB1        (1 <<  1) // Pin Controlled by PB1
+#define AT91C_PB1_SPI1_MOSI (AT91C_PIO_PB1) //  SPI 1 Master Out Slave
+#define AT91C_PB1_TIOB3    (AT91C_PIO_PB1) //  Timer Counter 3 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PB10       (1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_TXD3     (AT91C_PIO_PB10) //  USART 3 Transmit Data
+#define AT91C_PB10_ISI_D8   (AT91C_PIO_PB10) //  Image Sensor Data 8
+#define AT91C_PIO_PB11       (1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_RXD3     (AT91C_PIO_PB11) //  USART 3 Receive Data
+#define AT91C_PB11_ISI_D9   (AT91C_PIO_PB11) //  Image Sensor Data 9
+#define AT91C_PIO_PB12       (1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_TWD1     (AT91C_PIO_PB12) //  TWI Two-wire Serial Data 1
+#define AT91C_PB12_ISI_D10  (AT91C_PIO_PB12) //  Image Sensor Data 10
+#define AT91C_PIO_PB13       (1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_TWCK1    (AT91C_PIO_PB13) //  TWI Two-wire Serial Clock 1
+#define AT91C_PB13_ISI_D11  (AT91C_PIO_PB13) //  Image Sensor Data 11
+#define AT91C_PIO_PB14       (1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_DRXD     (AT91C_PIO_PB14) //  DBGU Debug Receive Data
+#define AT91C_PIO_PB15       (1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_DTXD     (AT91C_PIO_PB15) //  DBGU Debug Transmit Data
+#define AT91C_PIO_PB16       (1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_TK0      (AT91C_PIO_PB16) //  SSC0 Transmit Clock
+#define AT91C_PB16_TCLK3    (AT91C_PIO_PB16) //  Timer Counter 3 external clock input
+#define AT91C_PIO_PB17       (1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_TF0      (AT91C_PIO_PB17) //  SSC0 Transmit Frame Sync
+#define AT91C_PB17_TCLK4    (AT91C_PIO_PB17) //  Timer Counter 4 external clock input
+#define AT91C_PIO_PB18       (1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_TD0      (AT91C_PIO_PB18) //  SSC0 Transmit data
+#define AT91C_PB18_TIOB4    (AT91C_PIO_PB18) //  Timer Counter 4 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PB19       (1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_RD0      (AT91C_PIO_PB19) //  SSC0 Receive Data
+#define AT91C_PB19_TIOB5    (AT91C_PIO_PB19) //  Timer Counter 5 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PB2        (1 <<  2) // Pin Controlled by PB2
+#define AT91C_PB2_SPI1_SPCK (AT91C_PIO_PB2) //  SPI 1 Serial Clock
+#define AT91C_PB2_TIOA4    (AT91C_PIO_PB2) //  Timer Counter 4 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PB20       (1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_RK0      (AT91C_PIO_PB20) //  SSC0 Receive Clock
+#define AT91C_PB20_ISI_D0   (AT91C_PIO_PB20) //  Image Sensor Data 0
+#define AT91C_PIO_PB21       (1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_RF0      (AT91C_PIO_PB21) //  SSC0 Receive Frame Sync
+#define AT91C_PB21_ISI_D1   (AT91C_PIO_PB21) //  Image Sensor Data 1
+#define AT91C_PIO_PB22       (1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_DSR0     (AT91C_PIO_PB22) //  USART 0 Data Set ready
+#define AT91C_PB22_ISI_D2   (AT91C_PIO_PB22) //  Image Sensor Data 2
+#define AT91C_PIO_PB23       (1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_DCD0     (AT91C_PIO_PB23) //  USART 0 Data Carrier Detect
+#define AT91C_PB23_ISI_D3   (AT91C_PIO_PB23) //  Image Sensor Data 3
+#define AT91C_PIO_PB24       (1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_DTR0     (AT91C_PIO_PB24) //  USART 0 Data Terminal ready
+#define AT91C_PB24_ISI_D4   (AT91C_PIO_PB24) //  Image Sensor Data 4
+#define AT91C_PIO_PB25       (1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_RI0      (AT91C_PIO_PB25) //  USART 0 Ring Indicator
+#define AT91C_PB25_ISI_D5   (AT91C_PIO_PB25) //  Image Sensor Data 5
+#define AT91C_PIO_PB26       (1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_RTS0     (AT91C_PIO_PB26) //  USART 0 Ready To Send
+#define AT91C_PB26_ISI_D6   (AT91C_PIO_PB26) //  Image Sensor Data 6
+#define AT91C_PIO_PB27       (1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_CTS0     (AT91C_PIO_PB27) //  USART 0 Clear To Send
+#define AT91C_PB27_ISI_D7   (AT91C_PIO_PB27) //  Image Sensor Data 7
+#define AT91C_PIO_PB28       (1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_RTS1     (AT91C_PIO_PB28) //  USART 1 Ready To Send
+#define AT91C_PB28_ISI_PCK  (AT91C_PIO_PB28) //  Image Sensor Data Clock
+#define AT91C_PIO_PB29       (1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_CTS1     (AT91C_PIO_PB29) //  USART 1 Clear To Send
+#define AT91C_PB29_ISI_VSYNC (AT91C_PIO_PB29) //  Image Sensor Vertical Synchro
+#define AT91C_PIO_PB3        (1 <<  3) // Pin Controlled by PB3
+#define AT91C_PB3_SPI1_NPCS0 (AT91C_PIO_PB3) //  SPI 1 Peripheral Chip Select 0
+#define AT91C_PB3_TIOA5    (AT91C_PIO_PB3) //  Timer Counter 5 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PB30       (1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK0_0   (AT91C_PIO_PB30) //  PMC Programmable Clock Output 0
+#define AT91C_PB30_ISI_HSYNC (AT91C_PIO_PB30) //  Image Sensor Horizontal Synchro
+#define AT91C_PIO_PB31       (1 << 31) // Pin Controlled by PB31
+#define AT91C_PB31_PCK1_0   (AT91C_PIO_PB31) //  PMC Programmable Clock Output 1
+#define AT91C_PB31_ISI_MCK  (AT91C_PIO_PB31) //  Image Sensor Reference Clock
+#define AT91C_PIO_PB4        (1 <<  4) // Pin Controlled by PB4
+#define AT91C_PB4_TXD0     (AT91C_PIO_PB4) //  USART 0 Transmit Data
+#define AT91C_PIO_PB5        (1 <<  5) // Pin Controlled by PB5
+#define AT91C_PB5_RXD0     (AT91C_PIO_PB5) //  USART 0 Receive Data
+#define AT91C_PIO_PB6        (1 <<  6) // Pin Controlled by PB6
+#define AT91C_PB6_TXD1     (AT91C_PIO_PB6) //  USART 1 Transmit Data
+#define AT91C_PB6_TCLK1    (AT91C_PIO_PB6) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PB7        (1 <<  7) // Pin Controlled by PB7
+#define AT91C_PB7_RXD1     (AT91C_PIO_PB7) //  USART 1 Receive Data
+#define AT91C_PB7_TCLK2    (AT91C_PIO_PB7) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PB8        (1 <<  8) // Pin Controlled by PB8
+#define AT91C_PB8_TXD2     (AT91C_PIO_PB8) //  USART 2 Transmit Data
+#define AT91C_PIO_PB9        (1 <<  9) // Pin Controlled by PB9
+#define AT91C_PB9_RXD2     (AT91C_PIO_PB9) //  USART 2 Receive Data
+#define AT91C_PIO_PC0        (1 <<  0) // Pin Controlled by PC0
+#define AT91C_PC0_AD0      (AT91C_PIO_PC0) //  ADC Analog Input 0
+#define AT91C_PC0_SCK3     (AT91C_PIO_PC0) //  USART 3 Serial Clock
+#define AT91C_PIO_PC1        (1 <<  1) // Pin Controlled by PC1
+#define AT91C_PC1_AD1      (AT91C_PIO_PC1) //  ADC Analog Input 1
+#define AT91C_PC1_PCK0     (AT91C_PIO_PC1) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PC10       (1 << 10) // Pin Controlled by PC10
+#define AT91C_PC10_A25_CFRNW (AT91C_PIO_PC10) //  Address Bus[25]
+#define AT91C_PC10_CTS3     (AT91C_PIO_PC10) //  USART 3 Clear To Send
+#define AT91C_PIO_PC11       (1 << 11) // Pin Controlled by PC11
+#define AT91C_PC11_NCS2     (AT91C_PIO_PC11) //  Chip Select Line 2
+#define AT91C_PC11_SPI0_NPCS1 (AT91C_PIO_PC11) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PC12       (1 << 12) // Pin Controlled by PC12
+#define AT91C_PC12_IRQ0     (AT91C_PIO_PC12) //  External Interrupt 0
+#define AT91C_PC12_NCS7     (AT91C_PIO_PC12) //  Chip Select Line 7
+#define AT91C_PIO_PC13       (1 << 13) // Pin Controlled by PC13
+#define AT91C_PC13_FIQ      (AT91C_PIO_PC13) //  AIC Fast Interrupt Input
+#define AT91C_PC13_NCS6     (AT91C_PIO_PC13) //  Chip Select Line 6
+#define AT91C_PIO_PC14       (1 << 14) // Pin Controlled by PC14
+#define AT91C_PC14_NCS3_NANDCS (AT91C_PIO_PC14) //  Chip Select Line 3
+#define AT91C_PC14_IRQ2     (AT91C_PIO_PC14) //  External Interrupt 2
+#define AT91C_PIO_PC15       (1 << 15) // Pin Controlled by PC15
+#define AT91C_PC15_NWAIT    (AT91C_PIO_PC15) //  External Wait Signal
+#define AT91C_PC15_IRQ1     (AT91C_PIO_PC15) //  External Interrupt 1
+#define AT91C_PIO_PC16       (1 << 16) // Pin Controlled by PC16
+#define AT91C_PC16_D16      (AT91C_PIO_PC16) //  Data Bus[16]
+#define AT91C_PC16_SPI0_NPCS2 (AT91C_PIO_PC16) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PC17       (1 << 17) // Pin Controlled by PC17
+#define AT91C_PC17_D17      (AT91C_PIO_PC17) //  Data Bus[17]
+#define AT91C_PC17_SPI0_NPCS3 (AT91C_PIO_PC17) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PC18       (1 << 18) // Pin Controlled by PC18
+#define AT91C_PC18_D18      (AT91C_PIO_PC18) //  Data Bus[18]
+#define AT91C_PC18_SPI1_NPCS1_1 (AT91C_PIO_PC18) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PC19       (1 << 19) // Pin Controlled by PC19
+#define AT91C_PC19_D19      (AT91C_PIO_PC19) //  Data Bus[19]
+#define AT91C_PC19_SPI1_NPCS2_1 (AT91C_PIO_PC19) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PC2        (1 <<  2) // Pin Controlled by PC2
+#define AT91C_PC2_AD2      (AT91C_PIO_PC2) //  ADC Analog Input 2
+#define AT91C_PC2_PCK1     (AT91C_PIO_PC2) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PC20       (1 << 20) // Pin Controlled by PC20
+#define AT91C_PC20_D20      (AT91C_PIO_PC20) //  Data Bus[20]
+#define AT91C_PC20_SPI1_NPCS3_1 (AT91C_PIO_PC20) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PC21       (1 << 21) // Pin Controlled by PC21
+#define AT91C_PC21_D21      (AT91C_PIO_PC21) //  Data Bus[21]
+#define AT91C_PC21_EF100    (AT91C_PIO_PC21) //  Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PIO_PC22       (1 << 22) // Pin Controlled by PC22
+#define AT91C_PC22_D22      (AT91C_PIO_PC22) //  Data Bus[22]
+#define AT91C_PC22_TCLK5    (AT91C_PIO_PC22) //  Timer Counter 5 external clock input
+#define AT91C_PIO_PC23       (1 << 23) // Pin Controlled by PC23
+#define AT91C_PC23_D23      (AT91C_PIO_PC23) //  Data Bus[23]
+#define AT91C_PIO_PC24       (1 << 24) // Pin Controlled by PC24
+#define AT91C_PC24_D24      (AT91C_PIO_PC24) //  Data Bus[24]
+#define AT91C_PIO_PC25       (1 << 25) // Pin Controlled by PC25
+#define AT91C_PC25_D25      (AT91C_PIO_PC25) //  Data Bus[25]
+#define AT91C_PIO_PC26       (1 << 26) // Pin Controlled by PC26
+#define AT91C_PC26_D26      (AT91C_PIO_PC26) //  Data Bus[26]
+#define AT91C_PIO_PC27       (1 << 27) // Pin Controlled by PC27
+#define AT91C_PC27_D27      (AT91C_PIO_PC27) //  Data Bus[27]
+#define AT91C_PIO_PC28       (1 << 28) // Pin Controlled by PC28
+#define AT91C_PC28_D28      (AT91C_PIO_PC28) //  Data Bus[28]
+#define AT91C_PIO_PC29       (1 << 29) // Pin Controlled by PC29
+#define AT91C_PC29_D29      (AT91C_PIO_PC29) //  Data Bus[29]
+#define AT91C_PIO_PC3        (1 <<  3) // Pin Controlled by PC3
+#define AT91C_PC3_AD3      (AT91C_PIO_PC3) //  ADC Analog Input 3
+#define AT91C_PC3_SPI1_NPCS3_0 (AT91C_PIO_PC3) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PC30       (1 << 30) // Pin Controlled by PC30
+#define AT91C_PC30_D30      (AT91C_PIO_PC30) //  Data Bus[30]
+#define AT91C_PIO_PC31       (1 << 31) // Pin Controlled by PC31
+#define AT91C_PC31_D31      (AT91C_PIO_PC31) //  Data Bus[31]
+#define AT91C_PIO_PC4        (1 <<  4) // Pin Controlled by PC4
+#define AT91C_PC4_A23      (AT91C_PIO_PC4) //  Address Bus[23]
+#define AT91C_PC4_SPI1_NPCS2_0 (AT91C_PIO_PC4) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PC5        (1 <<  5) // Pin Controlled by PC5
+#define AT91C_PC5_A24      (AT91C_PIO_PC5) //  Address Bus[24]
+#define AT91C_PC5_SPI1_NPCS1_0 (AT91C_PIO_PC5) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PC6        (1 <<  6) // Pin Controlled by PC6
+#define AT91C_PC6_TIOB2    (AT91C_PIO_PC6) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PC6_CFCE1    (AT91C_PIO_PC6) //  Compact Flash Enable 1
+#define AT91C_PIO_PC7        (1 <<  7) // Pin Controlled by PC7
+#define AT91C_PC7_TIOB1    (AT91C_PIO_PC7) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PC7_CFCE2    (AT91C_PIO_PC7) //  Compact Flash Enable 2
+#define AT91C_PIO_PC8        (1 <<  8) // Pin Controlled by PC8
+#define AT91C_PC8_NCS4_CFCS0 (AT91C_PIO_PC8) //  Chip Select Line 4
+#define AT91C_PC8_RTS3     (AT91C_PIO_PC8) //  USART 3 Ready To Send
+#define AT91C_PIO_PC9        (1 <<  9) // Pin Controlled by PC9
+#define AT91C_PC9_NCS5_CFCS1 (AT91C_PIO_PC9) //  Chip Select Line 5
+#define AT91C_PC9_TIOB0    (AT91C_PIO_PC9) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM9XE512
+// *****************************************************************************
+#define AT91C_ID_FIQ    ( 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS    ( 1) // System Controller
+#define AT91C_ID_PIOA   ( 2) // Parallel IO Controller A
+#define AT91C_ID_PIOB   ( 3) // Parallel IO Controller B
+#define AT91C_ID_PIOC   ( 4) // Parallel IO Controller C
+#define AT91C_ID_ADC    ( 5) // ADC
+#define AT91C_ID_US0    ( 6) // USART 0
+#define AT91C_ID_US1    ( 7) // USART 1
+#define AT91C_ID_US2    ( 8) // USART 2
+#define AT91C_ID_MCI    ( 9) // Multimedia Card Interface 0
+#define AT91C_ID_UDP    (10) // USB Device Port
+#define AT91C_ID_TWI0   (11) // Two-Wire Interface 0
+#define AT91C_ID_SPI0   (12) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1   (13) // Serial Peripheral Interface 1
+#define AT91C_ID_SSC0   (14) // Serial Synchronous Controller 0
+#define AT91C_ID_TC0    (17) // Timer Counter 0
+#define AT91C_ID_TC1    (18) // Timer Counter 1
+#define AT91C_ID_TC2    (19) // Timer Counter 2
+#define AT91C_ID_UHP    (20) // USB Host Port
+#define AT91C_ID_EMAC   (21) // Ethernet Mac
+#define AT91C_ID_HISI   (22) // Image Sensor Interface
+#define AT91C_ID_US3    (23) // USART 3
+#define AT91C_ID_US4    (24) // USART 4
+#define AT91C_ID_TWI1   (25) // Two-Wire Interface 1
+#define AT91C_ID_TC3    (26) // Timer Counter 3
+#define AT91C_ID_TC4    (27) // Timer Counter 4
+#define AT91C_ID_TC5    (28) // Timer Counter 5
+#define AT91C_ID_IRQ0   (29) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1   (30) // Advanced Interrupt Controller (IRQ1)
+#define AT91C_ID_IRQ2   (31) // Advanced Interrupt Controller (IRQ2)
+#define AT91C_ALL_INT   (0xFFFE7FFF) // ALL VALID INTERRUPTS
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM9XE512
+// *****************************************************************************
+#define AT91C_BASE_SYS       (AT91_CAST(AT91PS_SYS) 	0xFFFFFD00) // (SYS) Base Address
+#define AT91C_BASE_EBI       (AT91_CAST(AT91PS_EBI) 	0xFFFFEA00) // (EBI) Base Address
+#define AT91C_BASE_HECC      (AT91_CAST(AT91PS_ECC) 	0xFFFFE800) // (HECC) Base Address
+#define AT91C_BASE_SDRAMC    (AT91_CAST(AT91PS_SDRAMC) 	0xFFFFEA00) // (SDRAMC) Base Address
+#define AT91C_BASE_SMC       (AT91_CAST(AT91PS_SMC) 	0xFFFFEC00) // (SMC) Base Address
+#define AT91C_BASE_MATRIX    (AT91_CAST(AT91PS_MATRIX) 	0xFFFFEE00) // (MATRIX) Base Address
+#define AT91C_BASE_CCFG      (AT91_CAST(AT91PS_CCFG) 	0xFFFFEF10) // (CCFG) Base Address
+#define AT91C_BASE_PDC_DBGU  (AT91_CAST(AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU      (AT91_CAST(AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_AIC       (AT91_CAST(AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PIOA      (AT91_CAST(AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB      (AT91_CAST(AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_PIOC      (AT91_CAST(AT91PS_PIO) 	0xFFFFF800) // (PIOC) Base Address
+#define AT91C_BASE_EFC       (AT91_CAST(AT91PS_EFC) 	0xFFFFFA00) // (EFC) Base Address
+#define AT91C_BASE_CKGR      (AT91_CAST(AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC       (AT91_CAST(AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC      (AT91_CAST(AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_SHDWC     (AT91_CAST(AT91PS_SHDWC) 	0xFFFFFD10) // (SHDWC) Base Address
+#define AT91C_BASE_RTTC      (AT91_CAST(AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC      (AT91_CAST(AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC      (AT91_CAST(AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_TC0       (AT91_CAST(AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1       (AT91_CAST(AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2       (AT91_CAST(AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TC3       (AT91_CAST(AT91PS_TC) 	0xFFFDC000) // (TC3) Base Address
+#define AT91C_BASE_TC4       (AT91_CAST(AT91PS_TC) 	0xFFFDC040) // (TC4) Base Address
+#define AT91C_BASE_TC5       (AT91_CAST(AT91PS_TC) 	0xFFFDC080) // (TC5) Base Address
+#define AT91C_BASE_TCB0      (AT91_CAST(AT91PS_TCB) 	0xFFFA0000) // (TCB0) Base Address
+#define AT91C_BASE_TCB1      (AT91_CAST(AT91PS_TCB) 	0xFFFDC000) // (TCB1) Base Address
+#define AT91C_BASE_PDC_MCI   (AT91_CAST(AT91PS_PDC) 	0xFFFA8100) // (PDC_MCI) Base Address
+#define AT91C_BASE_MCI       (AT91_CAST(AT91PS_MCI) 	0xFFFA8000) // (MCI) Base Address
+#define AT91C_BASE_PDC_TWI0  (AT91_CAST(AT91PS_PDC) 	0xFFFAC100) // (PDC_TWI0) Base Address
+#define AT91C_BASE_TWI0      (AT91_CAST(AT91PS_TWI) 	0xFFFAC000) // (TWI0) Base Address
+#define AT91C_BASE_PDC_TWI1  (AT91_CAST(AT91PS_PDC) 	0xFFFD8100) // (PDC_TWI1) Base Address
+#define AT91C_BASE_TWI1      (AT91_CAST(AT91PS_TWI) 	0xFFFD8000) // (TWI1) Base Address
+#define AT91C_BASE_PDC_US0   (AT91_CAST(AT91PS_PDC) 	0xFFFB0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0       (AT91_CAST(AT91PS_USART) 	0xFFFB0000) // (US0) Base Address
+#define AT91C_BASE_PDC_US1   (AT91_CAST(AT91PS_PDC) 	0xFFFB4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1       (AT91_CAST(AT91PS_USART) 	0xFFFB4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US2   (AT91_CAST(AT91PS_PDC) 	0xFFFB8100) // (PDC_US2) Base Address
+#define AT91C_BASE_US2       (AT91_CAST(AT91PS_USART) 	0xFFFB8000) // (US2) Base Address
+#define AT91C_BASE_PDC_US3   (AT91_CAST(AT91PS_PDC) 	0xFFFD0100) // (PDC_US3) Base Address
+#define AT91C_BASE_US3       (AT91_CAST(AT91PS_USART) 	0xFFFD0000) // (US3) Base Address
+#define AT91C_BASE_PDC_US4   (AT91_CAST(AT91PS_PDC) 	0xFFFD4100) // (PDC_US4) Base Address
+#define AT91C_BASE_US4       (AT91_CAST(AT91PS_USART) 	0xFFFD4000) // (US4) Base Address
+#define AT91C_BASE_PDC_SSC0  (AT91_CAST(AT91PS_PDC) 	0xFFFBC100) // (PDC_SSC0) Base Address
+#define AT91C_BASE_SSC0      (AT91_CAST(AT91PS_SSC) 	0xFFFBC000) // (SSC0) Base Address
+#define AT91C_BASE_PDC_SPI0  (AT91_CAST(AT91PS_PDC) 	0xFFFC8100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0      (AT91_CAST(AT91PS_SPI) 	0xFFFC8000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_SPI1  (AT91_CAST(AT91PS_PDC) 	0xFFFCC100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1      (AT91_CAST(AT91PS_SPI) 	0xFFFCC000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_ADC   (AT91_CAST(AT91PS_PDC) 	0xFFFE0100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC       (AT91_CAST(AT91PS_ADC) 	0xFFFE0000) // (ADC) Base Address
+#define AT91C_BASE_EMACB     (AT91_CAST(AT91PS_EMAC) 	0xFFFC4000) // (EMACB) Base Address
+#define AT91C_BASE_UDP       (AT91_CAST(AT91PS_UDP) 	0xFFFA4000) // (UDP) Base Address
+#define AT91C_BASE_UHP       (AT91_CAST(AT91PS_UHP) 	0x00500000) // (UHP) Base Address
+#define AT91C_BASE_HISI      (AT91_CAST(AT91PS_ISI) 	0xFFFC0000) // (HISI) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM9XE512
+// *****************************************************************************
+// IROM
+#define AT91C_IROM 	 (0x00100000) // Internal ROM base address
+#define AT91C_IROM_SIZE	 (0x00008000) // Internal ROM size in byte (32 Kbytes)
+// ISRAM
+#define AT91C_ISRAM	 (0x00300000) // Maximum IRAM Area : 32Kbyte base address
+#define AT91C_ISRAM_SIZE	 (0x00008000) // Maximum IRAM Area : 32Kbyte size in byte (32 Kbytes)
+// ISRAM_MIN
+#define AT91C_ISRAM_MIN	 (0x00300000) // Minimun IRAM Area : 32Kbyte base address
+#define AT91C_ISRAM_MIN_SIZE	 (0x00008000) // Minimun IRAM Area : 32Kbyte size in byte (32 Kbytes)
+// IFLASH
+#define AT91C_IFLASH	 (0x00200000) // Maximum IFLASH Area : 512Kbyte base address
+#define AT91C_IFLASH_SIZE	 (0x00080000) // Maximum IFLASH Area : 512Kbyte size in byte (512 Kbytes)
+#define AT91C_IFLASH_PAGE_SIZE	 (512) // Maximum IFLASH Area : 512Kbyte Page Size: 512 bytes
+#define AT91C_IFLASH_LOCK_REGION_SIZE	 (16384) // Maximum IFLASH Area : 512Kbyte Lock Region Size: 16 Kbytes
+#define AT91C_IFLASH_NB_OF_PAGES	 (1024) // Maximum IFLASH Area : 512Kbyte Number of Pages: 1024 bytes
+#define AT91C_IFLASH_NB_OF_LOCK_BITS	 (32) // Maximum IFLASH Area : 512Kbyte Number of Lock Bits: 32 bytes
+// EBI_CS0
+#define AT91C_EBI_CS0	 (0x10000000) // EBI Chip Select 0 base address
+#define AT91C_EBI_CS0_SIZE	 (0x10000000) // EBI Chip Select 0 size in byte (262144 Kbytes)
+// EBI_CS1
+#define AT91C_EBI_CS1	 (0x20000000) // EBI Chip Select 1 base address
+#define AT91C_EBI_CS1_SIZE	 (0x10000000) // EBI Chip Select 1 size in byte (262144 Kbytes)
+// EBI_SDRAM
+#define AT91C_EBI_SDRAM	 (0x20000000) // SDRAM on EBI Chip Select 1 base address
+#define AT91C_EBI_SDRAM_SIZE	 (0x10000000) // SDRAM on EBI Chip Select 1 size in byte (262144 Kbytes)
+// EBI_SDRAM_16BIT
+#define AT91C_EBI_SDRAM_16BIT	 (0x20000000) // SDRAM on EBI Chip Select 1 base address
+#define AT91C_EBI_SDRAM_16BIT_SIZE	 (0x02000000) // SDRAM on EBI Chip Select 1 size in byte (32768 Kbytes)
+// EBI_SDRAM_32BIT
+#define AT91C_EBI_SDRAM_32BIT	 (0x20000000) // SDRAM on EBI Chip Select 1 base address
+#define AT91C_EBI_SDRAM_32BIT_SIZE	 (0x04000000) // SDRAM on EBI Chip Select 1 size in byte (65536 Kbytes)
+// EBI_CS2
+#define AT91C_EBI_CS2	 (0x30000000) // EBI Chip Select 2 base address
+#define AT91C_EBI_CS2_SIZE	 (0x10000000) // EBI Chip Select 2 size in byte (262144 Kbytes)
+// EBI_CS3
+#define AT91C_EBI_CS3	 (0x40000000) // EBI Chip Select 3 base address
+#define AT91C_EBI_CS3_SIZE	 (0x10000000) // EBI Chip Select 3 size in byte (262144 Kbytes)
+// EBI_SM
+#define AT91C_EBI_SM	 (0x40000000) // SmartMedia on Chip Select 3 base address
+#define AT91C_EBI_SM_SIZE	 (0x10000000) // SmartMedia on Chip Select 3 size in byte (262144 Kbytes)
+// EBI_CS4
+#define AT91C_EBI_CS4	 (0x50000000) // EBI Chip Select 4 base address
+#define AT91C_EBI_CS4_SIZE	 (0x10000000) // EBI Chip Select 4 size in byte (262144 Kbytes)
+// EBI_CF0
+#define AT91C_EBI_CF0	 (0x50000000) // CompactFlash 0 on Chip Select 4 base address
+#define AT91C_EBI_CF0_SIZE	 (0x10000000) // CompactFlash 0 on Chip Select 4 size in byte (262144 Kbytes)
+// EBI_CS5
+#define AT91C_EBI_CS5	 (0x60000000) // EBI Chip Select 5 base address
+#define AT91C_EBI_CS5_SIZE	 (0x10000000) // EBI Chip Select 5 size in byte (262144 Kbytes)
+// EBI_CF1
+#define AT91C_EBI_CF1	 (0x60000000) // CompactFlash 1 on Chip Select 5 base address
+#define AT91C_EBI_CF1_SIZE	 (0x10000000) // CompactFlash 1 on Chip Select 5 size in byte (262144 Kbytes)
+// EBI_CS6
+#define AT91C_EBI_CS6	 (0x70000000) // EBI Chip Select 6 base address
+#define AT91C_EBI_CS6_SIZE	 (0x10000000) // EBI Chip Select 6 size in byte (262144 Kbytes)
+// EBI_CS7
+#define AT91C_EBI_CS7	 (0x80000000) // EBI Chip Select 7 base address
+#define AT91C_EBI_CS7_SIZE	 (0x10000000) // EBI Chip Select 7 size in byte (262144 Kbytes)
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/flash.icf b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/flash.icf
new file mode 100644
index 0000000..d1ff040
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/flash.icf
@@ -0,0 +1,48 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x200000;
+define symbol __ICFEDIT_region_ROM_end__     = 0x27FFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x300000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x307FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_startup__  = 0x100;
+define symbol __ICFEDIT_size_vectors__  = 0x100;
+define symbol __ICFEDIT_size_cstack__   = 0x1000;
+define symbol __ICFEDIT_size_svcstack__ = 0x60;
+define symbol __ICFEDIT_size_irqstack__ = 0x60;
+define symbol __ICFEDIT_size_heap__     = 0x0;
+/*-Exports-*/
+export symbol __ICFEDIT_region_ROM_start__;
+export symbol __ICFEDIT_region_ROM_end__;
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+export symbol __ICFEDIT_size_startup__;
+export symbol __ICFEDIT_size_vectors__;
+export symbol __ICFEDIT_size_cstack__;
+export symbol __ICFEDIT_size_svcstack__;
+export symbol __ICFEDIT_size_irqstack__;
+export symbol __ICFEDIT_size_heap__;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region STA_region = mem:[from __ICFEDIT_region_ROM_start__ size __ICFEDIT_size_startup__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_ROM_end__];
+define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+initialize by copy { section .vectors };
+do not initialize  { section .noinit };
+
+place in STA_region { section .cstartup };
+place in ROM_region { readonly };
+place in VEC_region { section .vectors };
+place in RAM_region { readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/sdram.icf b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/sdram.icf
new file mode 100644
index 0000000..4753f07
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/sdram.icf
@@ -0,0 +1,46 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_SDRAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_SDRAM_end__   = 0x21FFFFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x300000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x307FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_startup__  = 0x100;
+define symbol __ICFEDIT_size_vectors__  = 0x100;
+define symbol __ICFEDIT_size_cstack__   = 0x1000;
+define symbol __ICFEDIT_size_svcstack__ = 0x60;
+define symbol __ICFEDIT_size_irqstack__ = 0x60;
+define symbol __ICFEDIT_size_heap__     = 0x0;
+/*-Exports-*/
+export symbol __ICFEDIT_region_SDRAM_start__;
+export symbol __ICFEDIT_region_SDRAM_end__;
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+export symbol __ICFEDIT_size_startup__;
+export symbol __ICFEDIT_size_vectors__;
+export symbol __ICFEDIT_size_cstack__;
+export symbol __ICFEDIT_size_svcstack__;
+export symbol __ICFEDIT_size_irqstack__;
+export symbol __ICFEDIT_size_heap__;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region STA_region =   mem:[from __ICFEDIT_region_SDRAM_start__ size __ICFEDIT_size_startup__];
+define region SDRAM_region = mem:[from __ICFEDIT_region_SDRAM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_SDRAM_end__];
+define region VEC_region =   mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
+define region RAM_region =   mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { section .vectors };
+do not initialize  { section .noinit };
+
+place in STA_region { section .cstartup };
+place in VEC_region { section .vectors };
+place in SDRAM_region { readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/sram.icf b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/sram.icf
new file mode 100644
index 0000000..2544f86
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/at91sam9xe512/sram.icf
@@ -0,0 +1,36 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__   = 0x300000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x307FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_vectors__  = 0x100;
+define symbol __ICFEDIT_size_cstack__   = 0x800;
+define symbol __ICFEDIT_size_svcstack__ = 0x60;
+define symbol __ICFEDIT_size_irqstack__ = 0x60;
+define symbol __ICFEDIT_size_heap__     = 0x0;
+/*-Exports-*/
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+export symbol __ICFEDIT_size_vectors__;
+export symbol __ICFEDIT_size_cstack__;
+export symbol __ICFEDIT_size_svcstack__;
+export symbol __ICFEDIT_size_irqstack__;
+export symbol __ICFEDIT_size_heap__;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+do not initialize  { section .noinit };
+
+place in VEC_region { section .vectors };
+place in RAM_region { section .cstartup, readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board.h
new file mode 100644
index 0000000..697f61d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board.h
@@ -0,0 +1,428 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+/// \dir
+/// !Purpose
+///
+/// Definition and functions for using AT91SAM9XE-related features, such
+/// has PIO pins, memories, etc.
+///
+/// !Usage
+/// -# The code for booting the board is provided by board_cstartup.S and
+///    board_lowlevel.c.
+/// -# For using board PIOs, board characteristics (clock, etc.) and external
+///    components, see board.h.
+/// -# For manipulating memories (remapping, SDRAM, etc.), see board_memories.h.
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \unit
+/// !Purpose
+///
+/// Definition of AT91SAM9XE-EK characteristics, AT91SAM9XE-dependant PIOs and
+/// external components interfacing.
+///
+/// !Usage
+/// -# For operating frequency information, see "SAM9XE-EK - Operating frequencies".
+/// -# For using portable PIO definitions, see "SAM9XE-EK - PIO definitions".
+/// -# Several USB definitions are included here (see "SAM9XE-EK - USB device").
+/// -# For external components definitions, see "SAM79260-EK - External components".
+/// -# For memory-related definitions, see "SAM79260-EK - Memories".
+//------------------------------------------------------------------------------
+
+#ifndef BOARD_H
+#define BOARD_H
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#if defined(at91sam9xe128)
+    #include "at91sam9xe128/AT91SAM9XE128.h"
+#elif defined(at91sam9xe256)
+    #include "at91sam9xe256/AT91SAM9XE256.h"
+#elif defined(at91sam9xe512)
+    #include "at91sam9xe512/AT91SAM9XE512.h"
+#else
+    #error Board does not support the specified chip.
+#endif
+
+//------------------------------------------------------------------------------
+//         Definitions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \page "SAM9XE-EK - Board Description"
+/// This page lists several definition related to the board description.
+///
+/// !Definitions
+/// - BOARD_NAME
+
+/// Name of the board.
+#define BOARD_NAME              "AT91SAM9XE-EK"
+/// Board definition.
+#define at91sam9xeek
+/// Family definition.
+#define at91sam9xe
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \page "SAM9XE-EK - Operating frequencies"
+/// This page lists several definition related to the board operating frequency
+/// (when using the initialization done by board_lowlevel.c).
+///
+/// !Definitions
+/// - BOARD_MAINOSC
+/// - BOARD_MCK
+
+/// Frequency of the board main oscillator.
+#define BOARD_MAINOSC           18432000
+
+/// Master clock frequency (when using board_lowlevel.c).
+#define BOARD_MCK               ((18432000 * 97 / 9) / 2)
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \page "SAM9XE-EK - USB device"
+/// This page lists constants describing several characteristics (controller
+/// type, D+ pull-up type, etc.) of the USB device controller of the chip/board.
+///
+/// !Constants
+/// - BOARD_USB_UDP
+/// - BOARD_USB_PULLUP_INTERNAL
+/// - BOARD_USB_NUMENDPOINTS
+/// - BOARD_USB_ENDPOINTS_MAXPACKETSIZE
+/// - BOARD_USB_ENDPOINTS_BANKS
+/// - BOARD_USB_BMATTRIBUTES
+
+/// Chip has a UDP controller.
+#define BOARD_USB_UDP
+
+/// Indicates the D+ pull-up is internal to the USB controller.
+#define BOARD_USB_PULLUP_INTERNAL
+
+/// Number of endpoints in the USB controller.
+#define BOARD_USB_NUMENDPOINTS                  6
+
+/// Returns the maximum packet size of the given endpoint.
+#define BOARD_USB_ENDPOINTS_MAXPACKETSIZE(i)    ((i >= 4) ? 512 : 64)
+#define BOARD_USB_ENDPOINTS_MAXPACKETSIZE_FS    64
+
+/// Returns the number of FIFO banks for the given endpoint.
+#define BOARD_USB_ENDPOINTS_BANKS(i)            (((i == 0) || (i == 3)) ? 1 : 2)
+
+/// USB attributes configuration descriptor (bus or self powered, remote wakeup)
+#define BOARD_USB_BMATTRIBUTES                  USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \page "SAM9XE-EK - PIO definitions"
+/// This pages lists all the pio definitions contained in board.h. The constants
+/// are named using the following convention: PIN_* for a constant which defines
+/// a single Pin instance (but may include several PIOs sharing the same
+/// controller), and PINS_* for a list of Pin instances.
+///
+/// !DBGU
+/// - PINS_DBGU
+///
+/// !LEDs
+/// - PIN_LED_0
+/// - PIN_LED_1
+/// - PINS_LEDS
+/// - LED_POWER
+/// - LED_DS1
+///
+/// !Push buttons
+/// - PIN_PUSHBUTTON_1
+/// - PIN_PUSHBUTTON_2
+/// - PINS_PUSHBUTTONS
+/// - PUSHBUTTON_BP1
+/// - PUSHBUTTON_BP2
+///
+/// !USART0
+/// - PIN_USART0_RXD
+/// - PIN_USART0_TXD
+/// - PIN_USART0_SCK
+///
+/// !SPI0
+/// - PIN_SPI0_MISO
+/// - PIN_SPI0_MOSI
+/// - PIN_SPI0_SPCK
+/// - PINS_SPI0
+/// - PIN_SPI0_NPCS0
+/// - PIN_SPI0_NPCS1
+///
+/// !SSC
+/// - PINS_SSC_TX
+///
+/// !USB
+/// - PIN_USB_VBUS
+///
+/// !MCI
+/// - PINS_MCI
+///
+/// !TWI0
+/// - PINS_TWI0
+
+/// List of all DBGU pin definitions.
+#define PINS_DBGU  {(1<<14) | (1<<15), AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
+
+/// LED #0 pin definition.
+#define PIN_LED_0   {1 << 9, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}
+/// LED #1 pin definition.
+#define PIN_LED_1   {1 << 6, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}
+/// List of all LED definitions.
+#define PINS_LEDS   PIN_LED_0, PIN_LED_1
+/// Power LED index.
+#define LED_POWER       0
+/// DS1 LED index.
+#define LED_DS1         1
+
+/// Push button #1 pin definition.
+#define PIN_PUSHBUTTON_1  {1 << 30, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_PULLUP}
+/// Pusb button #2 pin definition.
+#define PIN_PUSHBUTTON_2  {1UL << 31, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_PULLUP}
+/// List of all pushbutton pin definitions.
+#define PINS_PUSHBUTTONS  PIN_PUSHBUTTON_1, PIN_PUSHBUTTON_2
+/// Push button #1 index.
+#define PUSHBUTTON_BP1   0
+/// Push button #2 index.
+#define PUSHBUTTON_BP2   1
+
+/// USART0 TXD pin definition.
+#define PIN_USART0_TXD  {1 << 4, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
+/// USART0 RXD pin definition.
+#define PIN_USART0_RXD  {1 << 5, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
+/// USART0 RTS pin definition.
+#define PIN_USART0_RTS  {1 << 26, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
+/// USART0 CTS pin definition.
+#define PIN_USART0_CTS  {1 << 27, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
+/// USART0 SCK pin definition.
+#define PIN_USART0_SCK  {1UL << 31, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
+
+/// SPI0 MISO pin definition.
+#define PIN_SPI0_MISO  {1 << 0, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_PULLUP}
+/// SPI0 MOSI pin definition.
+#define PIN_SPI0_MOSI  {1 << 1, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
+/// SPI0 SPCK pin definition.
+#define PIN_SPI0_SPCK  {1 << 2, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
+/// List of SPI0 pin definitions (MISO, MOSI & SPCK).
+#define PINS_SPI0      PIN_SPI0_MISO, PIN_SPI0_MOSI, PIN_SPI0_SPCK	
+/// SPI0 chip select 0 pin definition.
+#define PIN_SPI0_NPCS0 {AT91C_PA3_SPI0_NPCS0, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
+/// SPI0 chip select 1 pin definition.
+#define PIN_SPI0_NPCS1 {AT91C_PC11_SPI0_NPCS1, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}
+
+/// SSC transmitter pins definition.
+#define PINS_SSC_TX  {0x00038000, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
+
+/// USB VBus monitoring pin definition.
+#define PIN_USB_VBUS    {1 << 5, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_INPUT, PIO_DEFAULT}
+
+/// List of MCI pins definitions.
+#define PINS_MCI  {0x0000003B, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}, \
+                  {1 << 8, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
+
+/// TWI0 pins definition.
+#define PINS_TWI0  {0x01800000, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \page "SAM9XE-EK - External components"
+/// This page lists the definitions related to external on-board components
+/// located in the board.h file for the AT91SAM9XE-EK.
+///
+/// !AT45 Dataflash Card (A)
+/// - BOARD_AT45_A_SPI_BASE
+/// - BOARD_AT45_A_SPI_ID
+/// - BOARD_AT45_A_SPI_PINS
+/// - BOARD_AT45_A_SPI
+/// - BOARD_AT45_A_NPCS
+/// - BOARD_AT45_A_NPCS_PIN
+///
+/// !AT45 Dataflash (B)
+/// - BOARD_AT45_B_SPI_BASE
+/// - BOARD_AT45_B_SPI_ID
+/// - BOARD_AT45_B_SPI_PINS
+/// - BOARD_AT45_B_SPI
+/// - BOARD_AT45_B_NPCS
+/// - BOARD_AT45_B_NPCS_PIN
+///
+/// !SD Card
+/// - BOARD_SD_MCI_BASE
+/// - BOARD_SD_MCI_ID
+/// - BOARD_SD_PINS
+/// - BOARD_SD_SLOT
+///
+///
+/// !EMAC
+/// - AT91C_BASE_EMAC
+/// - BOARD_EMAC_POWER_ALWAYS_ON
+/// - BOARD_EMAC_MODE_RMII
+/// - BOARD_EMAC_PINS
+/// - BOARD_EMAC_PIN_TEST
+/// - BOARD_EMAC_PIN_RPTR
+/// - BOARD_EMAC_RST_PINS
+/// - BOARD_EMAC_RUN_PINS
+
+
+/// Base address of SPI peripheral connected to the dataflash.
+#define BOARD_AT45_A_SPI_BASE         AT91C_BASE_SPI0
+/// Identifier of SPI peripheral connected to the dataflash.
+#define BOARD_AT45_A_SPI_ID           AT91C_ID_SPI0
+/// Pins of the SPI peripheral connected to the dataflash.
+#define BOARD_AT45_A_SPI_PINS         PINS_SPI0
+/// Dataflahs SPI number.
+#define BOARD_AT45_A_SPI              0
+/// Chip select connected to the dataflash.
+#define BOARD_AT45_A_NPCS             0
+/// Chip select pin connected to the dataflash.
+#define BOARD_AT45_A_NPCS_PIN         PIN_SPI0_NPCS0
+
+/// Base address of SPI peripheral connected to the dataflash.
+#define BOARD_AT45_B_SPI_BASE         AT91C_BASE_SPI0
+/// Identifier of SPI peripheral connected to the dataflash.
+#define BOARD_AT45_B_SPI_ID           AT91C_ID_SPI0
+/// Pins of the SPI peripheral connected to the dataflash.
+#define BOARD_AT45_B_SPI_PINS         PINS_SPI0
+/// Dataflahs SPI number.
+#define BOARD_AT45_B_SPI              0
+/// Chip select connected to the dataflash.
+#define BOARD_AT45_B_NPCS             1
+/// Chip select pin connected to the dataflash.
+#define BOARD_AT45_B_NPCS_PIN         PIN_SPI0_NPCS1
+
+/// Base address of SPI peripheral connected to the serialflash.
+#define BOARD_AT26_A_SPI_BASE         AT91C_BASE_SPI0
+/// Identifier of SPI peripheral connected to the dataflash.
+#define BOARD_AT26_A_SPI_ID           AT91C_ID_SPI0
+/// Pins of the SPI peripheral connected to the dataflash.
+#define BOARD_AT26_A_SPI_PINS         PINS_SPI0
+/// Dataflahs SPI number.
+#define BOARD_AT26_A_SPI              0
+/// Chip select connected to the dataflash.
+#define BOARD_AT26_A_NPCS             0
+/// Chip select pin connected to the dataflash.
+#define BOARD_AT26_A_NPCS_PIN         PIN_SPI0_NPCS0
+
+/// Base address of the MCI peripheral connected to the SD card.
+#define BOARD_SD_MCI_BASE           AT91C_BASE_MCI
+/// Peripheral identifier of the MCI connected to the SD card.
+#define BOARD_SD_MCI_ID             AT91C_ID_MCI
+/// MCI pins that shall be configured to access the SD card.
+#define BOARD_SD_PINS               PINS_MCI
+/// MCI slot to which the SD card is connected to.
+#define BOARD_SD_SLOT               MCI_SD_SLOTB
+
+/// Board EMAC base address
+#if !defined(AT91C_BASE_EMAC) && defined(AT91C_BASE_EMACB)
+#define AT91C_BASE_EMAC             AT91C_BASE_EMACB
+#endif
+/// Board EMAC power control - ALWAYS ON
+#define BOARD_EMAC_POWER_ALWAYS_ON
+/// Board EMAC work mode - RMII/MII ( 1 / 0 )
+#define BOARD_EMAC_MODE_RMII        1
+/// The PIN list of PIO for EMAC
+#define BOARD_EMAC_PINS     { ((1<<19)|(1<<13)|(1<<12)|(1<<16)|(1<<15)|(1<<14)\
+                              |(1<<17)|(1<<18)|(1<<20)|(1<<21)|(1<<7)),\
+                              AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT},\
+                            { ((1<<11)|(1<<10)|(1<<26)|(1<<25)|(1<<27)|(1<<22)\
+                              |(1<<29)|(1<<28)),\
+                              AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}
+/// The power up reset latch PIO for PHY
+#define BOARD_EMAC_PIN_TEST   {(1<<17), AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}
+//#define BOARD_EMAC_PIN_RMII : connected to 3v3 (RMII)
+// We force the address
+// (1<<14) PHY address 0, (1<<15) PHY address 1 (PIO A, perih A)
+// (1<<25) PHY address 2, (1<<26) PHY address 3 (PIO A, perih B)
+#define BOARD_EMAC_PINS_PHYAD { ((1<<14)|(1<<15)),\
+                                AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT},\
+                              { ((1<<25)|(1<<26)),\
+                                AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}
+//#define BOARD_EMAC_PIN_10BT : not connected
+#define BOARD_EMAC_PIN_RPTR   {(1<<27), AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}
+/// The PIN Configure list for EMAC on power up reset
+#define BOARD_EMAC_RST_PINS BOARD_EMAC_PINS_PHYAD,\
+                            BOARD_EMAC_PIN_TEST,\
+                            BOARD_EMAC_PIN_RPTR
+/// The runtime pin configure list for EMAC
+#define BOARD_EMAC_RUN_PINS BOARD_EMAC_PINS
+
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \page "SAM9XE-EK - Memories"
+/// This page lists definitions related to external on-board memories.
+///
+/// !Embedded Flash
+/// - BOARD_FLASH_EEFC
+///
+/// !SDRAM
+/// - BOARD_SDRAM_SIZE
+/// - PINS_SDRAM
+///
+/// !Nandflash
+/// - PINS_NANDFLASH
+/// - BOARD_NF_COMMAND_ADDR
+/// - BOARD_NF_ADDRESS_ADDR
+/// - BOARD_NF_DATA_ADDR
+/// - BOARD_NF_CE_PIN
+/// - BOARD_NF_RB_PIN
+
+/// Indicates chip has an Enhanced EFC.
+#define BOARD_FLASH_EEFC
+/// Address of the IAP function in ROM.
+#define BOARD_FLASH_IAP_ADDRESS         0x100008
+
+/// Board SDRAM size
+#define BOARD_SDRAM_SIZE   0x02000000
+/// List of all SDRAM pins definitions.
+#define PINS_SDRAM  {0xFFFF0000, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
+
+
+/// Nandflash controller peripheral pins definition.
+#define PINS_NANDFLASH         BOARD_NF_CE_PIN, BOARD_NF_RB_PIN
+/// Nandflash chip enable pin definition.
+#define BOARD_NF_CE_PIN        {1 << 14, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT}
+/// Nandflash ready/busy pin definition.
+#define BOARD_NF_RB_PIN        {1 << 13, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_INPUT, PIO_PULLUP}
+/// Address for transferring command bytes to the nandflash.
+#define BOARD_NF_COMMAND_ADDR  0x40400000
+/// Address for transferring address bytes to the nandflash.
+#define BOARD_NF_ADDRESS_ADDR  0x40200000
+/// Address for transferring data bytes to the nandflash.
+#define BOARD_NF_DATA_ADDR     0x40000000
+
+/// Address for transferring command bytes to the norflash.
+#define BOARD_NORFLASH_ADDR  0x10000000
+//------------------------------------------------------------------------------
+
+#endif //#ifndef BOARD_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_cstartup_iar.s b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_cstartup_iar.s
new file mode 100644
index 0000000..5e4e147
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_cstartup_iar.s
@@ -0,0 +1,169 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "ISR_Support.h"
+
+/*
+     IAR startup file for AT91SAM9XE microcontrollers.
+ */
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION IRQ_STACK:DATA:NOROOT(2)
+        SECTION CSTACK:DATA:NOROOT(3)
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#define __ASSEMBLY__
+#include "board.h"
+
+//------------------------------------------------------------------------------
+//         Definitions
+//------------------------------------------------------------------------------
+
+#define ARM_MODE_ABT     0x17
+#define ARM_MODE_FIQ     0x11
+#define ARM_MODE_IRQ     0x12
+#define ARM_MODE_SVC     0x13
+#define ARM_MODE_SYS     0x1F
+
+#define I_BIT            0x80
+#define F_BIT            0x40
+
+//------------------------------------------------------------------------------
+//         Startup routine
+//------------------------------------------------------------------------------
+
+/*
+   Exception vectors
+ */
+        SECTION .vectors:CODE:NOROOT(2)
+
+        PUBLIC  resetVector
+        PUBLIC  irqHandler
+
+        EXTERN  Undefined_Handler
+        EXTERN  vPortYieldProcessor
+        EXTERN  Prefetch_Handler
+        EXTERN  Abort_Handler
+        EXTERN  FIQ_Handler
+
+        ARM
+
+__iar_init$$done:               ; The interrupt vector is not needed
+                                ; until after copy initialization is done
+
+resetVector:
+        ; All default exception handlers (except reset) are
+        ; defined as weak symbol definitions.
+        ; If a handler is defined by the application it will take precedence.
+        LDR     pc, =resetHandler        ; Reset
+        LDR     pc, Undefined_Addr       ; Undefined instructions
+        LDR     pc, SWI_Addr             ; Software interrupt (SWI/SVC)
+        LDR     pc, Prefetch_Addr        ; Prefetch abort
+        LDR     pc, Abort_Addr           ; Data abort
+        B       .                        ; RESERVED
+        LDR     pc, =irqHandler          ; IRQ
+        LDR     pc, FIQ_Addr             ; FIQ
+
+Undefined_Addr: DCD   Undefined_Handler
+SWI_Addr:       DCD   vPortYieldProcessor
+Prefetch_Addr:  DCD   Prefetch_Handler
+Abort_Addr:     DCD   Abort_Handler
+FIQ_Addr:       DCD   FIQ_Handler
+	
+/*
+   Handles incoming interrupt requests by branching to the corresponding
+   handler, as defined in the AIC. Supports interrupt nesting.
+ */
+irqHandler:
+		portSAVE_CONTEXT
+
+        /* Write in the IVR to support Protect Mode */
+        LDR     lr, =AT91C_BASE_AIC
+        LDR     r0, [r14, #AIC_IVR]
+        STR     lr, [r14, #AIC_IVR]
+
+        /* Branch to C portion of the interrupt handler */
+        MOV     lr, pc
+        BX      r0
+
+        /* Acknowledge interrupt */
+        LDR     lr, =AT91C_BASE_AIC
+        STR     lr, [r14, #AIC_EOICR]
+
+		portRESTORE_CONTEXT
+
+/*
+   After a reset, execution starts here, the mode is ARM, supervisor
+   with interrupts disabled.
+   Initializes the chip and branches to the main() function.
+ */
+        SECTION .cstartup:CODE:NOROOT(2)
+
+        PUBLIC  resetHandler
+        EXTERN  LowLevelInit
+        EXTERN  ?main
+        REQUIRE resetVector
+        ARM
+
+resetHandler:
+
+        /* Set pc to actual code location (i.e. not in remap zone) */
+	    LDR     pc, =label
+
+        /* Perform low-level initialization of the chip using LowLevelInit() */
+label:
+	    LDR     r0, =LowLevelInit
+        LDR     r4, =SFE(CSTACK)
+        MOV     sp, r4
+        MOV     lr, pc
+        BX      r0
+
+        /* Set up the interrupt stack pointer. */
+        MSR     cpsr_c, #ARM_MODE_IRQ | I_BIT | F_BIT      ; Change the mode
+        LDR     sp, =SFE(IRQ_STACK)
+
+        /* Set up the SVC stack pointer. */
+        MSR     cpsr_c, #ARM_MODE_SVC | F_BIT              ; Change the mode
+        LDR     sp, =SFE(CSTACK)
+
+        /* Branch to main() */
+        LDR     r0, =?main
+        MOV     lr, pc
+        BX      r0
+
+        /* Loop indefinitely when program is finished */
+loop4:
+        B       loop4
+
+        END
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_lowlevel.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_lowlevel.c
new file mode 100644
index 0000000..711f846
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_lowlevel.c
@@ -0,0 +1,194 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "board.h"
+#include "board_memories.h"
+
+//------------------------------------------------------------------------------
+//         Local definitions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \page "SAM9XE - Oscillator & PLL Parameters"
+/// This page lists the parameters which are set for the PLL and main
+/// oscillator configuration.
+///
+/// !Parameters
+/// - BOARD_OSCOUNT
+/// - BOARD_CKGR_PLLA
+/// - BOARD_PLLACOUNT
+/// - BOARD_MULA
+/// - BOARD_DIVA
+/// - BOARD_CKGR_PLLB
+/// - BOARD_PLLBCOUNT
+/// - BOARD_MULB
+/// - BOARD_DIVB
+/// - BOARD_USBDIV
+/// - BOARD_PRESCALER
+
+/// Main oscillator startup time (in number of slow clock ticks). 
+#define BOARD_OSCOUNT           (AT91C_CKGR_OSCOUNT & (64 << 8))
+
+/// PLLA frequency range.
+#define BOARD_CKGR_PLLA         (AT91C_CKGR_SRCA | AT91C_CKGR_OUTA_2)
+/// PLLA startup time (in number of slow clock ticks).
+#define BOARD_PLLACOUNT         (63 << 8)
+/// PLLA MUL value.
+#define BOARD_MULA              (AT91C_CKGR_MULA & (96 << 16))
+/// PLLA DIV value.
+#define BOARD_DIVA              (AT91C_CKGR_DIVA & 9)
+
+/// PLLB frequency range
+#define BOARD_CKGR_PLLB         AT91C_CKGR_OUTB_1
+/// PLLB startup time (in number of slow clock ticks).
+#define BOARD_PLLBCOUNT         BOARD_PLLACOUNT
+/// PLLB MUL value.
+#define BOARD_MULB              (124 << 16)
+/// PLLB DIV value.
+#define BOARD_DIVB              12
+
+/// USB PLL divisor value to obtain a 48MHz clock.
+#define BOARD_USBDIV            AT91C_CKGR_USBDIV_2
+/// Master clock prescaler value.
+#define BOARD_PRESCALER         AT91C_PMC_MDIV_2
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+//         Local functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Default spurious interrupt handler
+//------------------------------------------------------------------------------
+void DefaultSpuriousHandler(void)
+{
+    while (1);
+}
+
+//------------------------------------------------------------------------------
+/// Default handler for fast interrupt requests.
+//------------------------------------------------------------------------------
+void DefaultFiqHandler(void)
+{
+    while (1);
+}
+
+//------------------------------------------------------------------------------
+/// Default handler for standard interrupt requests.
+//------------------------------------------------------------------------------
+void DefaultIrqHandler(void)
+{
+    while (1);
+}
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Performs the low-level initialization of the chip.
+//------------------------------------------------------------------------------
+void LowLevelInit(void)
+{
+    unsigned char i;
+
+    // Set flash wait states
+    //----------------------
+    AT91C_BASE_EFC->EFC_FMR = 6 << 8;
+
+//#if !defined(sdram)
+    // Initialize main oscillator
+    //---------------------------
+    AT91C_BASE_PMC->PMC_MOR = BOARD_OSCOUNT | AT91C_CKGR_MOSCEN;
+    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));
+
+    // Initialize PLLA at 200MHz (198.656)
+    AT91C_BASE_PMC->PMC_PLLAR = BOARD_CKGR_PLLA
+                                | BOARD_PLLACOUNT
+                                | BOARD_MULA
+                                | BOARD_DIVA;
+    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA));
+
+    // Initialize PLLB for USB usage
+    AT91C_BASE_PMC->PMC_PLLBR = BOARD_USBDIV
+                                | BOARD_CKGR_PLLB
+                                | BOARD_PLLBCOUNT
+                                | BOARD_MULB
+                                | BOARD_DIVB;
+    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKB));
+
+    // Wait for the master clock if it was already initialized
+    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
+
+    // Switch to fast clock
+    //---------------------
+    // Switch to main oscillator + prescaler
+    AT91C_BASE_PMC->PMC_MCKR = BOARD_PRESCALER;
+    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
+
+    // Switch to PLL + prescaler
+    AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLLA_CLK;
+    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
+//#endif //#if !defined(sdram)
+
+    // Initialize AIC
+    //---------------
+    AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;
+    AT91C_BASE_AIC->AIC_SVR[0] = (unsigned int) DefaultFiqHandler;
+    for (i = 1; i < 31; i++) {
+
+        AT91C_BASE_AIC->AIC_SVR[i] = (unsigned int) DefaultIrqHandler;
+    }
+    AT91C_BASE_AIC->AIC_SPU = (unsigned int) DefaultSpuriousHandler;
+
+    // Unstack nested interrupts
+    for (i = 0; i < 8 ; i++) {
+
+        AT91C_BASE_AIC->AIC_EOICR = 0;
+    }
+
+    // Watchdog initialization
+    //------------------------
+    AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
+
+    // Remap
+    //------
+    BOARD_RemapRam();
+
+    // Disable RTT and PIT interrupts (potential problem when program A
+    // configures RTT, then program B wants to use PIT only, interrupts
+    // from the RTT will still occur since they both use AT91C_ID_SYS)
+    AT91C_BASE_RTTC->RTTC_RTMR &= ~(AT91C_RTTC_ALMIEN | AT91C_RTTC_RTTINCIEN);
+    AT91C_BASE_PITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_memories.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_memories.c
new file mode 100644
index 0000000..51a5721
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_memories.c
@@ -0,0 +1,304 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include 
+#include 
+
+//------------------------------------------------------------------------------
+//         Local macros
+//------------------------------------------------------------------------------
+
+/// Reads a register value. Useful to add trace information to read  accesses.
+#define READ(peripheral, register)          (peripheral->register)
+/// Writes data in a register. Useful to add trace information to write accesses.
+#define WRITE(peripheral, register, value)  (peripheral->register = value)
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Changes the mapping of the chip so that the remap area mirrors the
+/// internal ROM or the EBI CS0 (depending on the BMS input).
+//------------------------------------------------------------------------------
+void BOARD_RemapRom(void)
+{
+    WRITE(AT91C_BASE_MATRIX, MATRIX_MRCR, 0);
+}
+
+//------------------------------------------------------------------------------
+/// Changes the mapping of the chip so that the remap area mirrors the
+/// internal RAM.
+//------------------------------------------------------------------------------
+void BOARD_RemapRam(void)
+{
+    WRITE(AT91C_BASE_MATRIX,
+          MATRIX_MRCR,
+          (AT91C_MATRIX_RCA926I | AT91C_MATRIX_RCA926D));
+}
+
+//------------------------------------------------------------------------------
+/// Initialize and configure the external SDRAM.
+//------------------------------------------------------------------------------
+void BOARD_ConfigureSdram(void)
+{
+	volatile unsigned int i;
+	static const Pin pinsSdram = PINS_SDRAM;
+	volatile unsigned int *pSdram = (unsigned int *) AT91C_EBI_SDRAM;
+	
+	// Enable corresponding PIOs
+    PIO_Configure(&pinsSdram, 1);
+    
+	// Enable EBI chip select for the SDRAM
+	WRITE(AT91C_BASE_MATRIX, MATRIX_EBI, AT91C_MATRIX_CS1A_SDRAMC);
+	
+
+	// CFG Control Register
+	WRITE(AT91C_BASE_SDRAMC, SDRAMC_CR, AT91C_SDRAMC_NC_9
+                        				| AT91C_SDRAMC_NR_13 
+                        				| AT91C_SDRAMC_CAS_2 
+                        				| AT91C_SDRAMC_NB_4_BANKS
+                        				| AT91C_SDRAMC_DBW_32_BITS
+                        				| AT91C_SDRAMC_TWR_2
+                        				| AT91C_SDRAMC_TRC_7
+                        				| AT91C_SDRAMC_TRP_2
+                        				| AT91C_SDRAMC_TRCD_2
+                        				| AT91C_SDRAMC_TRAS_5
+                        				| AT91C_SDRAMC_TXSR_8);
+
+	for (i = 0; i < 1000; i++);
+
+	WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NOP_CMD);	// Perform NOP
+	pSdram[0] = 0x00000000;
+
+	WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_PRCGALL_CMD);	// Set PRCHG AL
+	pSdram[0] = 0x00000000;						// Perform PRCHG
+
+	for (i = 0; i < 10000; i++);
+
+	WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);	// Set 1st CBR
+	pSdram[1] = 0x00000001;						// Perform CBR
+
+	WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);	// Set 2 CBR
+	pSdram[2] = 0x00000002;						// Perform CBR
+
+	WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);	// Set 3 CBR
+	pSdram[3] = 0x00000003;					   // Perform CBR
+
+	WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);	// Set 4 CBR
+	pSdram[4] = 0x00000004;					  // Perform CBR
+
+	WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);	// Set 5 CBR
+	pSdram[5] = 0x00000005;					  // Perform CBR
+
+	WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);	// Set 6 CBR
+	pSdram[6] = 0x00000006;					// Perform CBR
+
+	WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);	// Set 7 CBR
+	pSdram[7] = 0x00000007;					// Perform CBR
+
+	WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);	// Set 8 CBR
+	pSdram[8] = 0x00000008;					// Perform CBR
+
+	WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD);		// Set LMR operation
+	pSdram[9] = 0xcafedede;					// Perform LMR burst=1, lat=2
+
+	WRITE(AT91C_BASE_SDRAMC, SDRAMC_TR, (BOARD_MCK * 7) / 1000000);		// Set Refresh Timer
+
+	WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NORMAL_CMD);	// Set Normal mode
+	pSdram[0] = 0x00000000;						// Perform Normal mode
+}
+
+//------------------------------------------------------------------------------
+/// Initialize and configure the SDRAM for a 48 MHz MCK (ROM code clock settings).
+//------------------------------------------------------------------------------
+void BOARD_ConfigureSdram48MHz(void)
+{
+    volatile unsigned int i;
+    static const Pin pinsSdram = PINS_SDRAM;
+    volatile unsigned int *pSdram = (unsigned int *) AT91C_EBI_SDRAM;
+    
+    // Enable corresponding PIOs
+    PIO_Configure(&pinsSdram, 1);
+    
+    // Enable EBI chip select for the SDRAM
+    WRITE(AT91C_BASE_MATRIX, MATRIX_EBI, AT91C_MATRIX_CS1A_SDRAMC);
+    
+
+    // CFG Control Register
+    WRITE(AT91C_BASE_SDRAMC, SDRAMC_CR, AT91C_SDRAMC_NC_9
+                                        | AT91C_SDRAMC_NR_13 
+                                        | AT91C_SDRAMC_CAS_2 
+                                        | AT91C_SDRAMC_NB_4_BANKS
+                                        | AT91C_SDRAMC_DBW_32_BITS
+                                        | AT91C_SDRAMC_TWR_1
+                                        | AT91C_SDRAMC_TRC_4
+                                        | AT91C_SDRAMC_TRP_1
+                                        | AT91C_SDRAMC_TRCD_1
+                                        | AT91C_SDRAMC_TRAS_2
+                                        | AT91C_SDRAMC_TXSR_3);
+
+    for (i = 0; i < 1000; i++);
+
+    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NOP_CMD); // Perform NOP
+    pSdram[0] = 0x00000000;
+
+    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_PRCGALL_CMD); // Set PRCHG AL
+    pSdram[0] = 0x00000000;                     // Perform PRCHG
+
+    for (i = 0; i < 10000; i++);
+
+    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 1st CBR
+    pSdram[1] = 0x00000001;                     // Perform CBR
+
+    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 2 CBR
+    pSdram[2] = 0x00000002;                     // Perform CBR
+
+    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 3 CBR
+    pSdram[3] = 0x00000003;                    // Perform CBR
+
+    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 4 CBR
+    pSdram[4] = 0x00000004;                   // Perform CBR
+
+    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 5 CBR
+    pSdram[5] = 0x00000005;                   // Perform CBR
+
+    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 6 CBR
+    pSdram[6] = 0x00000006;                 // Perform CBR
+
+    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 7 CBR
+    pSdram[7] = 0x00000007;                 // Perform CBR
+
+    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 8 CBR
+    pSdram[8] = 0x00000008;                 // Perform CBR
+
+    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD);     // Set LMR operation
+    pSdram[9] = 0xcafedede;                 // Perform LMR burst=1, lat=2
+
+    WRITE(AT91C_BASE_SDRAMC, SDRAMC_TR, (48000000 * 7) / 1000000);      // Set Refresh Timer
+
+    WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NORMAL_CMD);  // Set Normal mode
+    pSdram[0] = 0x00000000;                     // Perform Normal mode
+}
+
+//------------------------------------------------------------------------------
+/// Configures the EBI for NandFlash access. Pins must be configured after or
+/// before calling this function.
+//------------------------------------------------------------------------------
+void BOARD_ConfigureNandFlash(unsigned char busWidth)
+{
+    // Configure EBI
+    AT91C_BASE_MATRIX->MATRIX_EBI |= AT91C_MATRIX_CS3A_SM;
+
+    // Configure SMC
+    AT91C_BASE_SMC->SMC_SETUP3 = 0x00000000;
+    AT91C_BASE_SMC->SMC_PULSE3 = 0x00030003;
+    AT91C_BASE_SMC->SMC_CYCLE3 = 0x00050005;
+    AT91C_BASE_SMC->SMC_CTRL3  = 0x00002003;
+
+    if (busWidth == 8) {
+
+        AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;
+    }
+    else if (busWidth == 16) {
+ 
+        AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Configures the EBI for NandFlash access at 48MHz. Pins must be configured
+/// after or before calling this function.
+//------------------------------------------------------------------------------
+void BOARD_ConfigureNandFlash48MHz(unsigned char busWidth)
+{
+    // Configure EBI
+    AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM;
+
+    // Configure SMC
+    AT91C_BASE_SMC->SMC_SETUP3 = 0x00010001;
+    AT91C_BASE_SMC->SMC_PULSE3 = 0x04030302;
+    AT91C_BASE_SMC->SMC_CYCLE3 = 0x00070004;
+    AT91C_BASE_SMC->SMC_CTRL3  = (AT91C_SMC_READMODE
+                                 | AT91C_SMC_WRITEMODE
+                                 | AT91C_SMC_NWAITM_NWAIT_DISABLE
+                                 | ((0x1 << 16) & AT91C_SMC_TDF));
+    
+    if (busWidth == 8) {
+
+        AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;
+    }
+    else if (busWidth == 16) {
+ 
+        AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Configures the EBI for NorFlash access at 48MHz.
+/// \Param busWidth Bus width 
+//------------------------------------------------------------------------------
+void BOARD_ConfigureNorFlash48MHz(unsigned char busWidth)
+{
+    // Configure SMC
+    AT91C_BASE_SMC->SMC_SETUP0 = 0x00000001;
+    AT91C_BASE_SMC->SMC_PULSE0 = 0x07070703;
+    AT91C_BASE_SMC->SMC_CYCLE0 = 0x00070007;
+    AT91C_BASE_SMC->SMC_CTRL0  = (AT91C_SMC_READMODE
+                                  | AT91C_SMC_WRITEMODE
+                                  | AT91C_SMC_NWAITM_NWAIT_DISABLE
+                                  | ((0x1 << 16) & AT91C_SMC_TDF));
+                           
+    if (busWidth == 8) {
+
+        AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;
+    }
+    else if (busWidth == 16) {
+ 
+        AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;
+    }
+    else if (busWidth == 32) {
+ 
+        AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Set flash wait states in the EFC for 48MHz
+//------------------------------------------------------------------------------
+void BOARD_ConfigureFlash48MHz(void)
+{
+    // Set flash wait states
+    //----------------------
+    AT91C_BASE_EFC->EFC_FMR = 6 << 8;
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_memories.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_memories.h
new file mode 100644
index 0000000..8e2a677
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_memories.h
@@ -0,0 +1,54 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef BOARD_MEMORIES_H
+#define BOARD_MEMORIES_H
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+extern void BOARD_RemapRom(void);
+
+extern void BOARD_RemapRam(void);
+
+extern void BOARD_ConfigureSdram(void);
+
+extern void BOARD_ConfigureSdram48MHz(void);
+
+extern void BOARD_ConfigureNandFlash(unsigned char busWidth);
+
+extern void BOARD_ConfigureNandFlash48MHz(unsigned char busWidth);
+
+extern void BOARD_ConfigureNorFlash48MHz(unsigned char busWidth);
+
+extern void BOARD_ConfigureFlash48MHz(void);
+
+#endif //#ifndef BOARD_MEMORIES_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/ac97c/ac97c.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/ac97c/ac97c.c
new file mode 100644
index 0000000..0cbe25f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/ac97c/ac97c.c
@@ -0,0 +1,679 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "ac97c.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+
+//------------------------------------------------------------------------------
+//         Local constants
+//------------------------------------------------------------------------------
+
+/// Maximum size of one PDC buffer (in bytes).
+#define MAX_PDC_COUNTER	65535
+
+//------------------------------------------------------------------------------
+//         Local types
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// AC97 transfer descriptor. Tracks the status and parameters of a transfer
+/// on the AC97 bus.
+//------------------------------------------------------------------------------
+typedef struct _Ac97Transfer {
+
+	/// Buffer containing the slots to send.
+	unsigned char *pBuffer;
+	/// Total number of samples to send.
+	volatile unsigned int numSamples;
+	/// Optional callback function.
+	Ac97Callback callback;
+	/// Optional argument to the callback function.
+	void *pArg;
+
+} Ac97Transfer;
+
+//------------------------------------------------------------------------------
+/// AC97 controller driver structure. Monitors the status of transfers on all
+/// AC97 channels.
+//------------------------------------------------------------------------------
+typedef struct _Ac97c {
+
+    /// List of transfers occuring on each channel.
+	Ac97Transfer transfers[5];
+} Ac97c;
+
+//------------------------------------------------------------------------------
+//         Local variables
+//------------------------------------------------------------------------------
+
+/// Global AC97 controller instance.
+static Ac97c ac97c;
+
+//------------------------------------------------------------------------------
+//         Local functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Returns the size of one sample (in bytes) on the given channel.
+/// \param channel  Channel number.
+//------------------------------------------------------------------------------
+static unsigned char GetSampleSize(unsigned char channel)
+{
+    unsigned int size = 0;
+
+    SANITY_CHECK((channel == AC97C_CHANNEL_A)
+                 || (channel == AC97C_CHANNEL_B)
+                 || (channel == AC97C_CHANNEL_CODEC));
+
+    // Check selected channel
+    switch (channel) {
+        case AC97C_CHANNEL_CODEC: return 2;
+        case AC97C_CHANNEL_A: size = (AT91C_BASE_AC97C->AC97C_CAMR & AT91C_AC97C_SIZE) >> 16; break;
+        case AC97C_CHANNEL_B: size = (AT91C_BASE_AC97C->AC97C_CBMR & AT91C_AC97C_SIZE) >> 16; break;
+    }
+
+    // Compute size in bytes given SIZE field
+    if ((size & 2) != 0) {
+
+        return 2;
+    }
+    else {
+
+        return 4;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Interrupt service routine for Codec, is invoked by AC97C_Handler.
+//------------------------------------------------------------------------------
+static void CodecHandler(void)
+{
+    unsigned int status;
+    unsigned int data;
+    Ac97Transfer *pTransfer = &(ac97c.transfers[AC97C_CODEC_TRANSFER]);
+
+    // Read CODEC status register
+    status = AT91C_BASE_AC97C->AC97C_COSR;
+    status &= AT91C_BASE_AC97C->AC97C_COMR;
+
+    // A sample has been transmitted
+    if (status & AT91C_AC97C_TXRDY) {
+
+        pTransfer->numSamples--;
+
+        // If there are remaining samples, transmit one
+        if (pTransfer->numSamples > 0) {
+
+            data = *((unsigned int *) pTransfer->pBuffer);
+            AT91C_BASE_AC97C->AC97C_COMR &= ~(AT91C_AC97C_TXRDY);
+            AT91C_BASE_AC97C->AC97C_COTHR = data;
+
+            // Check if transfer is read or write
+            if ((data & AT91C_AC97C_READ) != 0) {
+    
+                AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_RXRDY;
+            }
+            else {
+            
+                pTransfer->pBuffer += sizeof(unsigned int);
+                AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_TXRDY;
+            }
+        }
+        // Transfer finished
+        else {
+
+            AT91C_BASE_AC97C->AC97C_IDR = AT91C_AC97C_COEVT;
+            AT91C_BASE_AC97C->AC97C_COMR &= ~(AT91C_AC97C_TXRDY);
+            if (pTransfer->callback) {
+
+                pTransfer->callback(pTransfer->pArg, 0, 0);
+            }
+        }   
+    }
+
+    // A sample has been received
+    if (status & AT91C_AC97C_RXRDY) {
+
+        // Store sample
+        data = AT91C_BASE_AC97C->AC97C_CORHR;
+        *((unsigned int *) pTransfer->pBuffer) = data;
+
+        pTransfer->pBuffer += sizeof(unsigned int);
+        pTransfer->numSamples--;
+
+        // Transfer finished
+        if (pTransfer->numSamples > 0) {
+
+            data = *((unsigned int *) pTransfer->pBuffer);
+            AT91C_BASE_AC97C->AC97C_COMR &= ~(AT91C_AC97C_RXRDY);
+            AT91C_BASE_AC97C->AC97C_COTHR = data;
+
+            // Check if transfer is read or write
+            if ((data & AT91C_AC97C_READ) != 0) {
+    
+                AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_RXRDY;
+            }
+            else {
+            
+                pTransfer->pBuffer += sizeof(unsigned int);
+                AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_TXRDY;
+            }
+        }
+        else {
+
+            AT91C_BASE_AC97C->AC97C_IDR = AT91C_AC97C_COEVT;
+            AT91C_BASE_AC97C->AC97C_COMR &= ~(AT91C_AC97C_RXRDY);
+            if (pTransfer->callback) {
+
+                pTransfer->callback(pTransfer->pArg, 0, 0);
+            }
+        }
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Interrupt service routine for channel A, is invoked by AC97C_Handler.
+//------------------------------------------------------------------------------
+static void ChannelAHandler(void)
+{
+    unsigned int status;
+    Ac97Transfer *pTransmit = &(ac97c.transfers[AC97C_CHANNEL_A_TRANSMIT]);
+    Ac97Transfer *pReceive = &(ac97c.transfers[AC97C_CHANNEL_A_RECEIVE]);
+
+    // Read channel A status register
+    status = AT91C_BASE_AC97C->AC97C_CASR;
+
+    // A buffer has been transmitted
+    if ((status & AT91C_AC97C_ENDTX) != 0) {
+
+        // Update transfer information
+        if (pTransmit->numSamples > MAX_PDC_COUNTER) {
+
+            pTransmit->numSamples -= MAX_PDC_COUNTER;
+        }
+        else {
+
+            pTransmit->numSamples = 0;
+        }
+
+        // Transmit new buffers if necessary
+        if (pTransmit->numSamples > MAX_PDC_COUNTER) {
+
+            // Fill next PDC
+            AT91C_BASE_AC97C->AC97C_TNPR = (unsigned int) pTransmit->pBuffer;
+            if (pTransmit->numSamples > 2 * MAX_PDC_COUNTER) {
+
+                AT91C_BASE_AC97C->AC97C_TNCR = MAX_PDC_COUNTER;
+                pTransmit->pBuffer += MAX_PDC_COUNTER * GetSampleSize(AC97C_CHANNEL_A);
+            }
+            else {
+
+                AT91C_BASE_AC97C->AC97C_TNCR = pTransmit->numSamples - MAX_PDC_COUNTER;
+            }
+        }
+        // Only one buffer remaining
+        else {
+
+            AT91C_BASE_AC97C->AC97C_CAMR &= ~AT91C_AC97C_ENDTX;
+            AT91C_BASE_AC97C->AC97C_CAMR |= AT91C_AC97C_TXBUFE;
+        }
+    }
+
+    // Transmit completed
+    if ((status & AT91C_AC97C_TXBUFE) != 0) {
+
+        pTransmit->numSamples = 0;
+        AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTDIS;
+        AT91C_BASE_AC97C->AC97C_CAMR &= ~AT91C_AC97C_TXBUFE;
+        if (pTransmit->callback) {
+
+            pTransmit->callback(pTransmit->pArg, 0, 0);
+        }
+    }
+
+    // A buffer has been received
+    if (status & AT91C_AC97C_ENDRX) {
+
+        if (pReceive->numSamples > MAX_PDC_COUNTER) {
+        
+            pReceive->numSamples -= MAX_PDC_COUNTER;
+        }
+        else {
+
+            pReceive->numSamples = 0;
+        }
+
+        // Transfer remaining samples
+        if (pReceive->numSamples > MAX_PDC_COUNTER) {
+
+            AT91C_BASE_AC97C->AC97C_RNPR = (unsigned int) pReceive->pBuffer;
+            if (pReceive->numSamples > 2 * MAX_PDC_COUNTER) {
+            
+                AT91C_BASE_AC97C->AC97C_RNCR = MAX_PDC_COUNTER;
+                pReceive->pBuffer += MAX_PDC_COUNTER * GetSampleSize(AC97C_CHANNEL_A);
+            }
+            else {
+
+                AT91C_BASE_AC97C->AC97C_RNCR = pReceive->numSamples - MAX_PDC_COUNTER;
+            }
+        }
+        // Only one buffer remaining
+        else {
+
+            AT91C_BASE_AC97C->AC97C_CAMR &= ~(AT91C_AC97C_ENDRX);
+            AT91C_BASE_AC97C->AC97C_CAMR |= AT91C_AC97C_RXBUFF;
+        }
+    }
+
+    // Receive complete
+    if ((status & AT91C_AC97C_RXBUFF) != 0) {
+
+        pReceive->numSamples = 0;
+        AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_RXTDIS;
+        AT91C_BASE_AC97C->AC97C_CAMR &= ~AT91C_AC97C_RXBUFF;
+        if (pReceive->callback) {
+
+            pReceive->callback(pReceive->pArg, 0, 0);
+        }
+    }
+}
+
+//------------------------------------------------------------------------------
+//         Exported functions
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+/// This handler function must be called by the AC97C interrupt service routine.
+/// Identifies which event was activated and calls the associated function.
+//------------------------------------------------------------------------------ 
+void AC97C_Handler(void)
+{
+    unsigned int status;
+
+    // Get the real interrupt source
+    status = AT91C_BASE_AC97C->AC97C_SR;
+    status &= AT91C_BASE_AC97C->AC97C_IMR;
+    
+    // Check if an event on the codec channel is active
+    if ((status & AT91C_AC97C_COEVT) != 0) {
+
+        CodecHandler();    
+    }
+    // Check if an event on channel A is active
+    if ((status & AT91C_AC97C_CAEVT) != 0) {
+
+        ChannelAHandler();  
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Starts a read or write transfer on the given channel
+/// \param channel particular channel (AC97C_CHANNEL_A or AC97C_CHANNEL_B).
+/// \param pBuffer buffer containing the slots to send.
+/// \param numSamples total number of samples to send.  
+/// \param callback optional callback function.
+/// \param pArg optional argument to the callback function.
+//------------------------------------------------------------------------------
+unsigned char AC97C_Transfer(
+    unsigned char channel,
+    unsigned char *pBuffer,
+    unsigned int numSamples,
+    Ac97Callback callback,
+    void *pArg)
+{
+    unsigned int size;
+    unsigned int data;
+    Ac97Transfer *pTransfer;
+
+    SANITY_CHECK(channel <= 5);
+    SANITY_CHECK(pBuffer);
+    SANITY_CHECK(numSamples > 0);
+
+    // Check that no transfer is pending on the channel
+    pTransfer = &(ac97c.transfers[channel]);
+    if (pTransfer->numSamples > 0) {
+
+        trace_LOG(trace_WARNING, "-W- AC97C_Transfer: Channel %d is busy\n\r", channel);
+        return AC97C_ERROR_BUSY;
+    }
+
+    // Fill transfer information
+    pTransfer->pBuffer = pBuffer;
+    pTransfer->numSamples = numSamples;
+    pTransfer->callback = callback;
+    pTransfer->pArg = pArg;
+
+    // Transmit or receive over codec channel
+    if (channel == AC97C_CODEC_TRANSFER) {
+
+        // Send command
+        data = *((unsigned int *) pTransfer->pBuffer); 
+        AT91C_BASE_AC97C->AC97C_COTHR = data;
+
+        // Check if transfer is read or write
+        if ((data & AT91C_AC97C_READ) != 0) {
+
+            AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_RXRDY;
+        }
+        else {
+        
+            pTransfer->pBuffer += sizeof(unsigned int);
+            AT91C_BASE_AC97C->AC97C_COMR |= AT91C_AC97C_TXRDY;
+        }
+
+        // Enable interrupts
+        AT91C_BASE_AC97C->AC97C_IER |= AT91C_AC97C_COEVT;
+    }
+    // Transmit over channel A
+    else if (channel == AC97C_CHANNEL_A_TRANSMIT) {
+
+        // Disable PDC
+        AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTDIS;
+
+        // Fill PDC buffers
+        size = min(pTransfer->numSamples, MAX_PDC_COUNTER);
+        AT91C_BASE_AC97C->AC97C_TPR = (unsigned int) pTransfer->pBuffer;
+        AT91C_BASE_AC97C->AC97C_TCR = size;
+        pTransfer->pBuffer += size * GetSampleSize(AC97C_CHANNEL_A);
+
+        size = min(pTransfer->numSamples - size, MAX_PDC_COUNTER);
+        if (size > 0) {
+
+            AT91C_BASE_AC97C->AC97C_TNPR = (unsigned int) pTransfer->pBuffer;
+            AT91C_BASE_AC97C->AC97C_TNCR = size;
+            pTransfer->pBuffer += size * GetSampleSize(AC97C_CHANNEL_A);
+        }
+
+        // Enable interrupts
+        AT91C_BASE_AC97C->AC97C_CAMR |= AT91C_AC97C_PDCEN | AT91C_AC97C_ENDTX;
+        AT91C_BASE_AC97C->AC97C_IER |= AT91C_AC97C_CAEVT;
+
+        // Start transfer
+        AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTEN;
+    }
+    // Receive over channel A
+    else if (channel == AC97C_CHANNEL_A_RECEIVE) {
+
+        // Disable PDC
+        AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_RXTDIS;
+
+        // Fill PDC buffers
+        size = min(pTransfer->numSamples, MAX_PDC_COUNTER);
+        AT91C_BASE_AC97C->AC97C_RPR = (unsigned int) pTransfer->pBuffer;
+        AT91C_BASE_AC97C->AC97C_RCR = size;
+        pTransfer->pBuffer += size * GetSampleSize(AC97C_CHANNEL_A);
+
+        size = min(pTransfer->numSamples - size, MAX_PDC_COUNTER);
+        if (size > 0) {
+
+            AT91C_BASE_AC97C->AC97C_RNPR = (unsigned int) pTransfer->pBuffer;
+            AT91C_BASE_AC97C->AC97C_RNCR = size;
+            pTransfer->pBuffer += size * GetSampleSize(AC97C_CHANNEL_A);
+        }
+
+        // Enable interrupts
+        AT91C_BASE_AC97C->AC97C_CAMR |= AT91C_AC97C_PDCEN | AT91C_AC97C_ENDRX;
+        AT91C_BASE_AC97C->AC97C_IER |= AT91C_AC97C_CAEVT;
+
+        // Start transfer
+        AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_RXTEN;
+    }
+
+    return 0;
+}
+
+//------------------------------------------------------------------------------
+/// Stop read or write transfer on the given channel.
+/// \param channel  Channel number.
+//------------------------------------------------------------------------------
+void AC97C_CancelTransfer(unsigned char channel)
+{    
+    unsigned int size = 0;
+    Ac97Transfer *pTransfer;
+
+    SANITY_CHECK(channel <= AC97C_CHANNEL_B_TRANSMIT);
+
+    // Save remaining size
+    pTransfer = &(ac97c.transfers[channel]);
+    size = pTransfer->numSamples;
+    pTransfer->numSamples = 0;
+
+    // Stop PDC
+    if (channel == AC97C_CHANNEL_A_TRANSMIT) {
+
+        AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTDIS;
+        size -= min(size, MAX_PDC_COUNTER) - AT91C_BASE_AC97C->AC97C_TCR;
+    }
+    if (channel == AC97C_CHANNEL_A_RECEIVE) {
+
+        AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_RXTDIS;
+        size -= min(size, MAX_PDC_COUNTER) - AT91C_BASE_AC97C->AC97C_RCR;
+    }
+
+    // Invoke callback if provided
+    if (pTransfer->callback) {
+
+        pTransfer->callback(pTransfer->pArg, AC97C_ERROR_STOPPED, size);
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Initializes the AC97 controller.
+//------------------------------------------------------------------------------
+void AC97C_Configure(void)
+{
+    unsigned char channel;
+
+    // Enable the AC97 controller peripheral clock
+    AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_AC97C);   
+    
+    // Enable the peripheral and variable rate adjustment
+    AT91C_BASE_AC97C->AC97C_MR = AT91C_AC97C_ENA  | AT91C_AC97C_VRA;
+
+    // Unassigns all input & output slots
+    AC97C_AssignInputSlots(0, 0xFFFF);
+    AC97C_AssignOutputSlots(0, 0xFFFF);
+
+    // Install the AC97C interrupt handler
+    AT91C_BASE_AC97C->AC97C_IDR = 0xFFFFFFFF;
+    AIC_ConfigureIT(AT91C_ID_AC97C, 0, AC97C_Handler);
+    AIC_EnableIT(AT91C_ID_AC97C);  
+
+    // Disable PDC transfers
+    AT91C_BASE_AC97C->AC97C_PTCR = AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS;
+
+    // Clear channel transfers
+    for (channel = 0; channel < AC97C_CHANNEL_B_TRANSMIT; channel++) {
+
+        ac97c.transfers[channel].numSamples = 0;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Configures the desired channel with the given value.
+/// \param channel  Channel number.
+/// \param cfg  Configuration value.
+//------------------------------------------------------------------------------
+void AC97C_ConfigureChannel(unsigned char channel, unsigned int cfg)
+{
+    SANITY_CHECK((channel == AC97C_CHANNEL_A) || (channel == AC97C_CHANNEL_B));
+
+    if (channel == AC97C_CHANNEL_A) {
+
+        AT91C_BASE_AC97C->AC97C_CAMR = cfg;
+    }
+    else {
+
+        AT91C_BASE_AC97C->AC97C_CBMR = cfg;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Assigns the desired input slots to a particular channel.
+/// \param channel  Channel number (or 0 to unassign slots).
+/// \param slots  Bitfield value of slots to assign.
+//------------------------------------------------------------------------------
+void AC97C_AssignInputSlots(unsigned char channel, unsigned int slots)
+{
+    unsigned int value;
+    unsigned int i;
+
+    SANITY_CHECK(channel <= AC97C_CHANNEL_B);
+
+    // Assign all slots
+    slots >>= 3;
+    for (i = 3; i < 15; i++) {
+
+        // Check if slots is selected
+        if (slots & 1) {
+
+            value = AT91C_BASE_AC97C->AC97C_ICA;
+            value &= ~(0x07 << ((i - 3) * 3));
+            value |= channel << ((i - 3) * 3);
+            AT91C_BASE_AC97C->AC97C_ICA = value;
+        }
+        slots >>= 1;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Assigns the desired output slots to a particular channel.
+/// \param channel  Channel number (or 0 to unassign slots).
+/// \param slots  Bitfield value of slots to assign.
+//------------------------------------------------------------------------------
+void AC97C_AssignOutputSlots(unsigned char channel, unsigned int slots)
+{
+    unsigned int value;
+    unsigned int i;
+
+    SANITY_CHECK(channel <= AC97C_CHANNEL_B);
+
+    // Assign all slots
+    slots >>= 3;
+    for (i = 3; i < 15; i++) {
+
+        // Check if slots is selected
+        if (slots & 1) {
+
+            value = AT91C_BASE_AC97C->AC97C_OCA;
+            value &= ~(0x07 << ((i - 3) * 3));
+            value |= channel << ((i - 3) * 3);
+            AT91C_BASE_AC97C->AC97C_OCA = value;
+        }
+        slots >>= 1;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Returns 1 if no transfer is currently pending on the given channel;
+/// otherwise, returns 0.
+/// \param channel  Channel number.
+//------------------------------------------------------------------------------
+unsigned char AC97C_IsFinished(unsigned char channel)
+{
+    SANITY_CHECK(channel <= AC97C_CHANNEL_B_TRANSMIT);
+
+	if (ac97c.transfers[channel].numSamples > 0) {
+
+		return 0;
+	}
+	else {
+
+		return 1;
+	}
+}
+
+//------------------------------------------------------------------------------
+/// Convenience function for synchronously sending commands to the codec.
+/// \param address  Register address.
+/// \param data  Command data.
+//------------------------------------------------------------------------------
+void AC97C_WriteCodec(unsigned char address, unsigned short data)
+{
+    unsigned int sample;
+
+    sample = (address << 16) | data;
+    AC97C_Transfer(AC97C_CODEC_TRANSFER, (unsigned char *) &sample, 1, 0, 0);
+    while (!AC97C_IsFinished(AC97C_CODEC_TRANSFER));
+}
+
+//------------------------------------------------------------------------------
+/// Convenience function for receiving data from the AC97 codec.
+/// \param address  Register address.
+//------------------------------------------------------------------------------
+unsigned short AC97C_ReadCodec(unsigned char address)
+{
+    unsigned int sample;
+
+    sample = AT91C_AC97C_READ | (address << 16);
+    AC97C_Transfer(AC97C_CODEC_TRANSFER, (unsigned char *) &sample, 1, 0, 0);
+	while (!AC97C_IsFinished(AC97C_CODEC_TRANSFER));
+
+    return sample;
+}
+            
+//------------------------------------------------------------------------------
+/// Sets the size in bits of one sample on the given channel.
+/// \param channel  Channel number.
+/// \param size  Size of one sample in bits (10, 16, 18 or 24).
+//------------------------------------------------------------------------------        
+void AC97C_SetChannelSize(unsigned char channel, unsigned char size)
+{
+    unsigned int bits = 0;
+
+    SANITY_CHECK((size == 10) || (size == 16) || (size == 18) || (size == 24));
+    SANITY_CHECK((channel == AC97C_CHANNEL_A) || (channel == AC97C_CHANNEL_B));
+
+    switch (size) {
+
+        case 10 : bits = AT91C_AC97C_SIZE_10_BITS; break;
+        case 16 : bits = AT91C_AC97C_SIZE_16_BITS; break;
+        case 18 : bits = AT91C_AC97C_SIZE_18_BITS; break;
+        case 20 : bits = AT91C_AC97C_SIZE_20_BITS; break;
+    }
+
+    if (channel == AC97C_CHANNEL_A) {
+
+        AT91C_BASE_AC97C->AC97C_CAMR &= ~(AT91C_AC97C_SIZE);
+        AT91C_BASE_AC97C->AC97C_CAMR |= bits;
+    }
+    else {
+
+        AT91C_BASE_AC97C->AC97C_CBMR &= ~(AT91C_AC97C_SIZE);
+        AT91C_BASE_AC97C->AC97C_CBMR |= bits;
+    }
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/ac97c/ac97c.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/ac97c/ac97c.h
new file mode 100644
index 0000000..77a7925
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/ac97c/ac97c.h
@@ -0,0 +1,100 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+
+#ifndef AC97C_H
+#define AC97C_H
+
+//------------------------------------------------------------------------------
+//         Constants
+//------------------------------------------------------------------------------
+
+/// The channel is already busy with a transfer.
+#define AC97C_ERROR_BUSY            1
+/// The transfer has been stopped by the user.
+#define AC97C_ERROR_STOPPED         2
+
+/// Codec channel index.
+#define AC97C_CHANNEL_CODEC	        0
+/// Channel A index.
+#define AC97C_CHANNEL_A	            1
+/// Channel B index.
+#define AC97C_CHANNEL_B	            2
+
+/// Codec transmit/receive transfer index.
+#define AC97C_CODEC_TRANSFER        0
+/// Channel A receive transfer index.
+#define AC97C_CHANNEL_A_RECEIVE     1
+/// Channel A transmit transfer index.
+#define AC97C_CHANNEL_A_TRANSMIT    2
+/// Channel B receive transfer index.
+#define AC97C_CHANNEL_B_RECEIVE     3
+/// Channel B transmit transfer index.
+#define AC97C_CHANNEL_B_TRANSMIT    4
+
+//------------------------------------------------------------------------------
+//         Types
+//------------------------------------------------------------------------------
+
+/// AC97C transfer callback function.
+typedef void (*Ac97Callback)(void *pArg,
+                             unsigned char status,
+                             unsigned int remaining);
+
+//------------------------------------------------------------------------------
+//         Exported functions
+//------------------------------------------------------------------------------
+
+extern void AC97C_Configure();
+
+extern void AC97C_ConfigureChannel(unsigned char channel, unsigned int cfg);
+
+extern void AC97C_AssignInputSlots(unsigned char channel, unsigned int slots);
+
+extern void AC97C_AssignOutputSlots(unsigned char channel, unsigned int slots);
+
+extern unsigned char AC97C_Transfer(
+				unsigned char channel,
+				unsigned char *pBuffer,
+				unsigned int numSamples,
+				Ac97Callback callback,
+				void *pArg);
+
+extern unsigned char AC97C_IsFinished(unsigned char channel);
+
+extern void AC97C_WriteCodec(unsigned char address, unsigned short data);
+
+extern unsigned short AC97C_ReadCodec(unsigned char address);
+
+extern void AC97C_SetChannelSize(unsigned char channel, unsigned char size);
+
+extern void AC97C_CancelTransfer(unsigned char channel);
+
+#endif //#ifndef AC97C_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/aes/aes.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/aes/aes.c
new file mode 100644
index 0000000..82586a2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/aes/aes.c
@@ -0,0 +1,196 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef trace_LEVEL
+    #define trace_LEVEL     1
+#endif
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "aes.h"
+#include 
+#include 
+#include 
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Configures the AES peripheral to encrypt/decrypt, start mode (manual, auto,
+/// PDC) and operating mode (ECB, CBC, OFB, CFB, CTR).
+/// \param cipher  Indicates if the peripheral should encrypt or decrypt data.
+/// \param smode  Start mode.
+/// \param opmode  Operating mode.
+//------------------------------------------------------------------------------
+void AES_Configure(
+    unsigned char cipher,
+    unsigned int smode,
+    unsigned int opmode)
+{
+    trace_LOG(trace_DEBUG, "-D- AES_Configure()\n\r");
+    SANITY_CHECK((cipher & 0xFFFFFFFE) == 0);
+    SANITY_CHECK((smode & 0xFFFFFCFF) == 0);
+    SANITY_CHECK((opmode & 0xFFFF8FFF) == 0);
+
+    // Reset the peripheral first
+    AT91C_BASE_AES->AES_CR = AT91C_AES_SWRST;
+
+    // Configure mode register
+    AT91C_BASE_AES->AES_MR = cipher | smode | opmode;
+}
+
+//------------------------------------------------------------------------------
+/// Sets the key used by the AES algorithm to cipher the plain text or
+/// decipher the encrypted text.
+/// \param pKey  Pointer to a 16-bytes cipher key.
+//------------------------------------------------------------------------------
+void AES_SetKey(const unsigned int *pKey)
+{
+    trace_LOG(trace_DEBUG, "-D- AES_SetKey()\n\r");
+    SANITY_CHECK(pKey);
+
+    AT91C_BASE_AES->AES_KEYWxR[0] = pKey[0];
+    AT91C_BASE_AES->AES_KEYWxR[1] = pKey[1];
+    AT91C_BASE_AES->AES_KEYWxR[2] = pKey[2];
+    AT91C_BASE_AES->AES_KEYWxR[3] = pKey[3];
+}
+
+//------------------------------------------------------------------------------
+/// Sets the initialization vector that is used to encrypt the plain text or
+/// decrypt the cipher text in chained block modes (CBC, CFB, OFB & CTR).
+/// \param pVector  Pointer to a 16-bytes initialization vector.
+//------------------------------------------------------------------------------
+void AES_SetVector(const unsigned int *pVector)
+{
+    trace_LOG(trace_DEBUG, "-D- AES_SetVector()\n\r");
+    SANITY_CHECK(pVector);
+
+    AT91C_BASE_AES->AES_IVxR[0] = pVector[0];
+    AT91C_BASE_AES->AES_IVxR[1] = pVector[1];
+    AT91C_BASE_AES->AES_IVxR[2] = pVector[2];
+    AT91C_BASE_AES->AES_IVxR[3] = pVector[3];
+}
+
+//------------------------------------------------------------------------------
+/// Sets the input data of the AES algorithm (i.e. plain text in cipher mode,
+/// ciphered text in decipher mode). If auto mode is active, the encryption is
+/// started automatically after writing the last word.
+/// \param pData  Pointer to the 16-bytes data to cipher/decipher.
+//------------------------------------------------------------------------------
+void AES_SetInputData(const unsigned int *pData)
+{
+    trace_LOG(trace_DEBUG, "-D- AES_SetInputData()\n\r");
+    SANITY_CHECK(pData);
+
+    AT91C_BASE_AES->AES_IDATAxR[0] = pData[0];
+    AT91C_BASE_AES->AES_IDATAxR[1] = pData[1];
+    AT91C_BASE_AES->AES_IDATAxR[2] = pData[2];
+    AT91C_BASE_AES->AES_IDATAxR[3] = pData[3];
+}
+
+//------------------------------------------------------------------------------
+/// Stores the result of the last AES operation (encrypt/decrypt) in the
+/// provided buffer.
+/// \param pData  Pointer to a 16-bytes buffer.
+//------------------------------------------------------------------------------
+void AES_GetOutputData(unsigned int *pData)
+{
+    trace_LOG(trace_DEBUG, "-D- AES_GetOutputData()\n\r");
+    SANITY_CHECK(pData);
+
+    pData[0] = AT91C_BASE_AES->AES_ODATAxR[0];
+    pData[1] = AT91C_BASE_AES->AES_ODATAxR[1];
+    pData[2] = AT91C_BASE_AES->AES_ODATAxR[2];
+    pData[3] = AT91C_BASE_AES->AES_ODATAxR[3];
+}
+
+//------------------------------------------------------------------------------
+/// Sets the input buffer to use when in PDC mode.
+/// \param pInput  Pointer to the input buffer.
+//------------------------------------------------------------------------------
+void AES_SetInputBuffer(const unsigned int *pInput)
+{
+    trace_LOG(trace_DEBUG, "-D- AES_SetInputBuffer()\n\r");
+    SANITY_CHECK(pInput);
+
+    AT91C_BASE_AES->AES_TPR = (unsigned int) pInput;
+    AT91C_BASE_AES->AES_TCR = 4;
+}
+
+//------------------------------------------------------------------------------
+/// Sets the output buffer to use when in PDC mode.
+/// \param pOutput  Pointer to the output buffer.
+//------------------------------------------------------------------------------
+void AES_SetOutputBuffer(unsigned int *pOutput)
+{
+    trace_LOG(trace_DEBUG, "-D- AES_SetOutputBuffer()\n\r");
+    SANITY_CHECK(pOutput);
+
+    AT91C_BASE_AES->AES_RPR = (unsigned int) pOutput;
+    AT91C_BASE_AES->AES_RCR = 4;
+}
+
+//------------------------------------------------------------------------------
+/// Starts the encryption/decryption process when in manual or PDC mode. In
+/// manual mode, the key and input data must have been entered using
+/// AES_SetKey() and AES_SetInputData(). In PDC mode, the key, input & output
+/// buffer must have been set using AES_SetKey(), AES_SetInputBuffer() and
+/// AES_SetOutputBuffer().
+//------------------------------------------------------------------------------
+void AES_Start(void)
+{
+    trace_LOG(trace_DEBUG, "AES_Start()\n\r");
+    SANITY_CHECK(((AT91C_BASE_AES->AES_MR & AT91C_AES_SMOD) == AT91C_AES_SMOD_MANUAL)
+                 || ((AT91C_BASE_AES->AES_MR & AT91C_AES_SMOD) == AT91C_AES_SMOD_PDC));
+
+    // Manual mode
+    if ((AT91C_BASE_AES->AES_MR & AT91C_AES_SMOD) == AT91C_AES_SMOD_MANUAL) {
+
+        AT91C_BASE_AES->AES_CR = AT91C_AES_START;
+    }
+    // PDC
+    else {
+
+        AT91C_BASE_AES->AES_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Returns the current value of the AES interrupt status register.
+//------------------------------------------------------------------------------
+unsigned int AES_GetStatus(void)
+{
+    trace_LOG(trace_DEBUG, "-D- AES_GetStatus()\n\r");
+
+    return AT91C_BASE_AES->AES_ISR;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/aes/aes.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/aes/aes.h
new file mode 100644
index 0000000..0f14f44
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/aes/aes.h
@@ -0,0 +1,59 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef AES_H
+#define AES_H
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+extern void AES_Configure(
+    unsigned char cipher,
+    unsigned int smode,
+    unsigned int opmode);
+
+extern void AES_SetKey(const unsigned int *pKey);
+
+extern void AES_SetVector(const unsigned int *pVector);
+
+extern void AES_SetInputData(const unsigned int *pData);
+
+extern void AES_GetOutputData(unsigned int *pData);
+
+extern void AES_SetInputBuffer(const unsigned int *pInput);
+
+extern void AES_SetOutputBuffer(unsigned int *pOutput);
+
+extern void AES_Start(void);
+
+extern unsigned int AES_GetStatus(void);
+
+#endif //#ifndef AES_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/aic/aic.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/aic/aic.c
new file mode 100644
index 0000000..ab6b7b2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/aic/aic.c
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "aic.h"
+#include 
+
+//------------------------------------------------------------------------------
+//         Exported functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Configures the interrupt associated with the given source, using the
+/// specified mode and interrupt handler.
+/// \param source  Interrupt source to configure.
+/// \param mode  Triggering mode of the interrupt.
+/// \param handler  Interrupt handler function.
+//------------------------------------------------------------------------------
+void AIC_ConfigureIT(unsigned int source,
+                            unsigned int mode,
+                            void (*handler)( void ))
+{
+    // Disable the interrupt first
+    AT91C_BASE_AIC->AIC_IDCR = 1 << source;
+
+    // Configure mode and handler
+    AT91C_BASE_AIC->AIC_SMR[source] = mode;
+    AT91C_BASE_AIC->AIC_SVR[source] = (unsigned int) handler;
+
+    // Clear interrupt
+    AT91C_BASE_AIC->AIC_ICCR = 1 << source;
+}
+
+//------------------------------------------------------------------------------
+/// Enables interrupts coming from the given (unique) source.
+/// \param source  Interrupt source to enable.
+//------------------------------------------------------------------------------
+void AIC_EnableIT(unsigned int source)
+{
+    AT91C_BASE_AIC->AIC_IECR = 1 << source;
+}
+
+//------------------------------------------------------------------------------
+/// Disables interrupts coming from the given (unique) source.
+/// \param source  Interrupt source to enable.
+//------------------------------------------------------------------------------
+void AIC_DisableIT(unsigned int source)
+{
+    AT91C_BASE_AIC->AIC_IDCR = 1 << source;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/aic/aic.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/aic/aic.h
new file mode 100644
index 0000000..64d1aef
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/aic/aic.h
@@ -0,0 +1,74 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+/// \dir
+/// !Purpose
+/// 
+/// Methods and definitions for configuring interrupts using the Advanced
+/// Interrupt Controller (AIC).
+/// 
+/// !Usage
+/// -# Configure an interrupt source using AIC_ConfigureIT
+/// -# Enable or disable interrupt generation of a particular source with
+///    AIC_EnableIT and AIC_DisableIT.
+//------------------------------------------------------------------------------
+
+#ifndef AIC_H
+#define AIC_H
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include 
+
+//------------------------------------------------------------------------------
+//         Definitions
+//------------------------------------------------------------------------------
+
+#ifndef AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL
+    /// Redefinition of missing constant.
+    #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE
+#endif
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+extern void AIC_ConfigureIT(unsigned int source,
+                                   unsigned int mode,
+                                   void (*handler)( void ));
+
+extern void AIC_EnableIT(unsigned int source);
+
+extern void AIC_DisableIT(unsigned int source);
+
+#endif //#ifndef AIC_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/can/can.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/can/can.c
new file mode 100644
index 0000000..18ab19d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/can/can.c
@@ -0,0 +1,1042 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include 
+#include 
+#include 
+#include 
+#include "can.h"
+
+//------------------------------------------------------------------------------
+//         Local definitions
+//------------------------------------------------------------------------------
+// CAN state
+#define CAN_DISABLED       0
+#define CAN_HALTED         1
+#define CAN_IDLE           2
+#define CAN_SENDING        3
+#define CAN_RECEIVING      4
+
+// MOT: Mailbox Object Type
+#define CAN_MOT_DISABLE    0 // Mailbox is disabled
+#define CAN_MOT_RECEPT     1 // Reception Mailbox
+#define CAN_MOT_RECEPT_OW  2 // Reception mailbox with overwrite
+#define CAN_MOT_TRANSMIT   3 // Transmit mailbox
+#define CAN_MOT_CONSUMER   4 // Consumer mailbox
+#define CAN_MOT_PRODUCER   5 // Producer mailbox
+
+//------------------------------------------------------------------------------
+//         Local variables
+//------------------------------------------------------------------------------
+#if defined (PINS_CAN_TRANSCEIVER_TXD)
+static const Pin pins_can_transceiver_txd[] = {PINS_CAN_TRANSCEIVER_TXD};
+#endif
+#if defined (PINS_CAN_TRANSCEIVER_RXD)
+static const Pin pins_can_transceiver_rxd[] = {PINS_CAN_TRANSCEIVER_RXD};
+#endif
+static const Pin pin_can_transceiver_rs   = PIN_CAN_TRANSCEIVER_RS;
+#if defined (PIN_CAN_TRANSCEIVER_RXEN)
+static const Pin pin_can_transceiver_rxen = PIN_CAN_TRANSCEIVER_RXEN;
+#endif
+
+static CanTransfer *pCAN0Transfer=NULL;
+#ifdef AT91C_BASE_CAN1
+static CanTransfer *pCAN1Transfer=NULL;
+#endif
+
+//------------------------------------------------------------------------------
+//         Local functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// CAN Error Detection
+/// \param status     error type
+/// \param can_number can nulber
+//------------------------------------------------------------------------------
+static void CAN_ErrorHandling( unsigned int status, unsigned char can_number)
+{
+    if( (status&AT91C_CAN_ERRA) ==  AT91C_CAN_ERRA) {
+        trace_LOG( trace_ERROR, "-E- (CAN) CAN is in active Error Active mode\n\r");
+    }
+    else if( (status&AT91C_CAN_ERRP) ==  AT91C_CAN_ERRP) {
+        trace_LOG( trace_ERROR, "-E- (CAN) CAN is in Error Passive mode\n\r");
+    }
+    else if( (status&AT91C_CAN_BOFF) ==  AT91C_CAN_BOFF) {
+        trace_LOG( trace_ERROR, "-E- (CAN) CAN is in Buff Off mode\n\r");
+        // CAN reset
+        trace_LOG( trace_ERROR, "-E- (CAN) CAN%d reset\n\r", can_number);
+        // CAN Controller Disable
+        if (can_number == 0) {
+            AT91C_BASE_CAN0->CAN_MR &= ~AT91C_CAN_CANEN;
+            // CAN Controller Enable
+            AT91C_BASE_CAN0->CAN_MR |= AT91C_CAN_CANEN;
+        }
+#ifdef AT91C_BASE_CAN1
+        else if (can_number == 1) {
+            AT91C_BASE_CAN1->CAN_MR &= ~AT91C_CAN_CANEN;
+            // CAN Controller Enable
+            AT91C_BASE_CAN1->CAN_MR |= AT91C_CAN_CANEN;
+        }
+#endif
+    }
+
+    // Error for Frame dataframe
+    // CRC error
+    if( (status&AT91C_CAN_CERR) ==  AT91C_CAN_CERR) {
+        trace_LOG( trace_ERROR, "-E- (CAN) CRC Error\n\r");
+    }
+    // Bit-stuffing error
+    else if( (status&AT91C_CAN_SERR) ==  AT91C_CAN_SERR) {
+        trace_LOG( trace_ERROR, "-E- (CAN) Stuffing Error\n\r");
+    }
+    // Bit error
+    else if( (status&AT91C_CAN_BERR) ==  AT91C_CAN_BERR) {
+        trace_LOG( trace_ERROR, "-E- (CAN) Bit Error\n\r");
+    }
+    // Form error
+    else if( (status&AT91C_CAN_FERR) ==  AT91C_CAN_FERR) {
+        trace_LOG( trace_ERROR, "-E- (CAN) Form Error\n\r");
+    }
+    // Acknowledgment error
+    else if( (status&AT91C_CAN_AERR) ==  AT91C_CAN_AERR) {
+        trace_LOG( trace_ERROR, "-E- (CAN) Acknowledgment Error\n\r");
+    }
+
+    // Error interrupt handler
+    // Represent the current status of the CAN bus and are not latched.
+    // See CAN, par. Error Interrupt Handler
+    // AT91C_CAN_WARN
+    // AT91C_CAN_ERRA
+}
+
+//------------------------------------------------------------------------------
+// Generic CAN Interrupt handler
+/// \param can_number can nulber
+//------------------------------------------------------------------------------
+static void CAN_Handler( unsigned char can_number ) 
+{
+    AT91PS_CAN base_can;
+    AT91PS_CAN_MB CAN_Mailbox;
+
+    unsigned int status;
+    unsigned int can_msr;
+    unsigned int* pCan_mcr;
+    unsigned int message_mode;
+    unsigned char numMailbox;
+    unsigned char state0;
+    unsigned char state1;
+
+    if( can_number == 0 ) {
+        base_can = AT91C_BASE_CAN0;
+        CAN_Mailbox = AT91C_BASE_CAN0_MB0;
+        state0 = pCAN0Transfer->state;
+    }
+#ifdef AT91C_BASE_CAN1
+    else {
+        base_can = AT91C_BASE_CAN1;
+        CAN_Mailbox = AT91C_BASE_CAN1_MB0;
+        state1 = pCAN1Transfer->state;
+    }
+#endif
+    status = (base_can->CAN_SR) & (base_can->CAN_IMR);
+    base_can->CAN_IDR = status;
+
+    trace_LOG( trace_DEBUG, "CAN0 status=0x%X\n\r", status);
+    if(status & AT91C_CAN_WAKEUP) {
+        if( can_number == 0 ) {
+            pCAN0Transfer->test_can = AT91C_TEST_OK;
+            pCAN0Transfer->state = CAN_IDLE;
+        }
+#ifdef AT91C_BASE_CAN1
+        else {
+            pCAN1Transfer->test_can = AT91C_TEST_OK;
+            pCAN1Transfer->state = CAN_IDLE;
+        }
+#endif
+    }
+    // Mailbox event ?
+    else if ((status&0x0000FFFF) != 0) {
+        trace_LOG( trace_DEBUG, "Mailbox event\n\r");
+
+        // Handle Mailbox interrupts
+        for (numMailbox = 0; numMailbox < NUM_MAILBOX_MAX; numMailbox++) {
+
+            can_msr = *(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x10+(0x20*numMailbox)));
+            if ((AT91C_CAN_MRDY & can_msr) == AT91C_CAN_MRDY) {
+                // Mailbox object type
+                message_mode =  ((*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x00+(0x20*numMailbox))))>>24)&0x7;
+                trace_LOG( trace_DEBUG, "message_mode 0x%X\n\r", message_mode);
+                trace_LOG( trace_DEBUG, "numMailbox 0x%X\n\r", numMailbox);
+
+                if( message_mode == 0 ) {
+                    trace_LOG( trace_ERROR, "-E-Error in MOT\n\r");
+                }
+                else if( ( message_mode == CAN_MOT_RECEPT ) 
+                      || ( message_mode == CAN_MOT_RECEPT_OW ) 
+                      || ( message_mode == CAN_MOT_PRODUCER ) ) {
+                    trace_LOG( trace_DEBUG, "Mailbox is in RECEPTION\n\r");
+                    trace_LOG( trace_DEBUG, "Length 0x%X\n\r", (can_msr>>16)&0xF);
+                    trace_LOG( trace_DEBUG, "CAN_MB_MID 0x%X\n\r", ((*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x08+(0x20*numMailbox)))&AT91C_CAN_MIDvA)>>18));
+
+                    trace_LOG( trace_DEBUG, "can_number %d\n\r", can_number);
+                    if( can_number == 0 ) {
+                        //CAN_MB_MDLx
+                        pCAN0Transfer->data_low_reg = 
+                           (*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x14+(0x20*numMailbox))));
+                        //CAN_MB_MDHx
+                        pCAN0Transfer->data_high_reg = 
+                           (*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x18+(0x20*numMailbox))));
+                        pCAN0Transfer->size = (can_msr>>16)&0xF;
+                        pCAN0Transfer->mailbox_number = numMailbox;
+                        state0 = CAN_IDLE;
+                    }
+#ifdef AT91C_BASE_CAN1
+                    else {
+                        //CAN_MB_MDLx
+                        pCAN1Transfer->data_low_reg = 
+                           (*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x14+(0x20*numMailbox))));
+                        //CAN_MB_MDHx
+                        pCAN1Transfer->data_high_reg = 
+                           (*(unsigned int*)((unsigned int)CAN_Mailbox+(unsigned int)(0x18+(0x20*numMailbox))));
+                        pCAN1Transfer->size = (can_msr>>16)&0xF;
+                        pCAN1Transfer->mailbox_number = numMailbox;
+                        state1 = CAN_IDLE;
+                    }
+#endif
+                    // Message Data has been received
+                    pCan_mcr = (unsigned int*)((unsigned int)CAN_Mailbox+0x1C+(0x20*numMailbox));
+                    *pCan_mcr = AT91C_CAN_MTCR;
+
+                }
+                else {
+                    trace_LOG( trace_DEBUG, "Mailbox is in TRANSMIT\n\r");
+                    trace_LOG( trace_DEBUG, "Length 0x%X\n\r", (can_msr>>16)&0xF);
+                    trace_LOG( trace_DEBUG, "can_number %d\n\r", can_number);
+                    if( can_number == 0 ) {
+                        state0 = CAN_IDLE;
+                    }
+                    else {
+                        state1 = CAN_IDLE;
+                    }
+                }
+            }
+        }
+        if( can_number == 0 ) {
+            pCAN0Transfer->state = state0;
+        }
+#ifdef AT91C_BASE_CAN1
+        else {
+            pCAN1Transfer->state = state1;
+        }
+#endif
+    }
+    if ((status&0xFFCF0000) != 0) {
+        CAN_ErrorHandling(status, 0);
+    }
+}
+
+//------------------------------------------------------------------------------
+/// CAN 0 Interrupt handler
+//------------------------------------------------------------------------------
+static void CAN0_Handler(void)
+{
+    CAN_Handler( 0 );
+}
+
+//------------------------------------------------------------------------------
+/// CAN 1 Interrupt handler
+//------------------------------------------------------------------------------
+#if defined AT91C_BASE_CAN1
+static void CAN1_Handler(void)
+{
+    CAN_Handler( 1 );
+}
+#endif
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Configure the corresponding mailbox
+/// \param pTransfer can transfer structure
+//------------------------------------------------------------------------------
+void CAN_InitMailboxRegisters( CanTransfer *pTransfer )
+{
+    AT91PS_CAN    base_can;
+    AT91PS_CAN_MB CAN_Mailbox;
+
+    if( pTransfer->can_number == 0 ) {
+        base_can = AT91C_BASE_CAN0;
+        CAN_Mailbox = AT91C_BASE_CAN0_MB0;
+    }
+#ifdef AT91C_BASE_CAN1
+    else {
+        base_can = AT91C_BASE_CAN1;
+        CAN_Mailbox = AT91C_BASE_CAN1_MB0;
+    }
+#endif
+    CAN_Mailbox = (AT91PS_CAN_MB)((unsigned int)CAN_Mailbox+(unsigned int)(0x20*pTransfer->mailbox_number));
+
+    pTransfer->mailbox_in_use |= 1<<(pTransfer->mailbox_number);
+    // MailBox Control Register
+    CAN_Mailbox->CAN_MB_MCR = 0x0;
+    // MailBox Mode Register
+    CAN_Mailbox->CAN_MB_MMR = 0x00;
+    // CAN Message Acceptance Mask Register
+    CAN_Mailbox->CAN_MB_MAM = pTransfer->acceptance_mask_reg;
+    // MailBox ID Register
+    // Disable the mailbox before writing to CAN_MIDx registers
+    if( pTransfer->identifier != 0 ) {
+        CAN_Mailbox->CAN_MB_MAM |= AT91C_CAN_MIDE;
+        CAN_Mailbox->CAN_MB_MID = pTransfer->identifier;
+    }
+    else {
+        CAN_Mailbox->CAN_MB_MAM &= ~AT91C_CAN_MIDE;
+    }
+    // MailBox Mode Register
+    CAN_Mailbox->CAN_MB_MMR = pTransfer->mode_reg;
+    // MailBox Data Low Register
+    CAN_Mailbox->CAN_MB_MDL = pTransfer->data_low_reg;
+    // MailBox Data High Register
+    CAN_Mailbox->CAN_MB_MDH = pTransfer->data_high_reg;
+    // MailBox Control Register
+    CAN_Mailbox->CAN_MB_MCR = pTransfer->control_reg;
+}
+
+//------------------------------------------------------------------------------
+/// Reset the MBx
+//------------------------------------------------------------------------------
+void CAN_ResetAllMailbox( void )
+{
+    unsigned char i;
+  
+#if defined (AT91C_BASE_CAN0_MB0)
+    CAN_ResetTransfer( pCAN0Transfer );
+    for( i=0; i<8; i++ ) {
+        pCAN0Transfer->can_number = 0;
+        pCAN0Transfer->mailbox_number = i;
+        pCAN0Transfer->mode_reg = AT91C_CAN_MOT_DIS;
+        pCAN0Transfer->acceptance_mask_reg = 0;
+        pCAN0Transfer->identifier = 0;
+        pCAN0Transfer->data_low_reg = 0x00000000;
+        pCAN0Transfer->data_high_reg = 0x00000000;
+        pCAN0Transfer->control_reg = 0x00000000;
+        CAN_InitMailboxRegisters( pCAN0Transfer );
+    }
+#endif
+#if defined (AT91C_BASE_CAN0_MB8)
+    for( i=0; i<8; i++ ) {
+        pCAN0Transfer->can_number = 0;
+        pCAN0Transfer->mailbox_number = i+8;
+        pCAN0Transfer->mode_reg = AT91C_CAN_MOT_DIS;
+        pCAN0Transfer->acceptance_mask_reg = 0;
+        pCAN0Transfer->identifier = 0;
+        pCAN0Transfer->data_low_reg = 0x00000000;
+        pCAN0Transfer->data_high_reg = 0x00000000;
+        pCAN0Transfer->control_reg = 0x00000000;
+        CAN_InitMailboxRegisters( pCAN0Transfer );
+    }
+#endif
+
+#if defined (AT91C_BASE_CAN1_MB0)
+    if( pCAN1Transfer != NULL ) {
+        CAN_ResetTransfer( pCAN1Transfer );
+        for( i=0; i<8; i++ ) {
+            pCAN1Transfer->can_number = 1;
+            pCAN1Transfer->mailbox_number = i;
+            pCAN1Transfer->mode_reg = AT91C_CAN_MOT_DIS;
+            pCAN1Transfer->acceptance_mask_reg = 0;
+            pCAN1Transfer->identifier = 0;
+            pCAN1Transfer->data_low_reg = 0x00000000;
+            pCAN1Transfer->data_high_reg = 0x00000000;
+            pCAN1Transfer->control_reg = 0x00000000;
+            CAN_InitMailboxRegisters( pCAN1Transfer );
+        }
+    }
+#endif
+#if defined (AT91C_BASE_CAN1_MB8)
+    if( pCAN1Transfer != NULL ) {
+        for( i=0; i<8; i++ ) {
+            pCAN1Transfer->can_number = 1;
+            pCAN1Transfer->mailbox_number = i+8;
+            pCAN1Transfer->mode_reg = AT91C_CAN_MOT_DIS;
+            pCAN1Transfer->acceptance_mask_reg = 0;
+            pCAN1Transfer->identifier = 0;
+            pCAN1Transfer->data_low_reg = 0x00000000;
+            pCAN1Transfer->data_high_reg = 0x00000000;
+            pCAN1Transfer->control_reg = 0x00000000;
+            CAN_InitMailboxRegisters( pCAN1Transfer );
+        }
+    }
+#endif
+
+}
+
+//------------------------------------------------------------------------------
+/// CAN reset Transfer descriptor
+/// \param pTransfer can transfer structure
+//------------------------------------------------------------------------------
+void CAN_ResetTransfer( CanTransfer *pTransfer )
+{
+    pTransfer->state = CAN_IDLE;
+    pTransfer->can_number = 0;
+    pTransfer->mailbox_number = 0;
+    pTransfer->test_can = 0;
+    pTransfer->mode_reg = 0;
+    pTransfer->acceptance_mask_reg = 0;
+    pTransfer->identifier = 0;
+    pTransfer->data_low_reg = 0;
+    pTransfer->data_high_reg = 0;
+    pTransfer->control_reg = 0;
+    pTransfer->mailbox_in_use = 0;
+    pTransfer->size = 0;
+}
+
+//------------------------------------------------------------------------------
+/// Wait for CAN synchronisation
+/// \return return 1 for good initialisation, otherwise return 0
+//------------------------------------------------------------------------------
+static unsigned char CAN_Synchronisation( void )
+{
+    unsigned int tick=0;
+
+    trace_LOG( trace_INFO, "CAN_Synchronisation\n\r");
+
+    pCAN0Transfer->test_can = AT91C_TEST_NOK;
+#ifdef AT91C_BASE_CAN1
+    if( pCAN1Transfer != NULL ) {
+        pCAN1Transfer->test_can = AT91C_TEST_NOK;
+    }
+#endif
+    // Enable CAN and Wait for WakeUp Interrupt
+    AT91C_BASE_CAN0->CAN_IER = AT91C_CAN_WAKEUP;
+    // CAN Controller Enable
+    AT91C_BASE_CAN0->CAN_MR = AT91C_CAN_CANEN;
+    // Enable Autobaud/Listen mode
+    // dangerous, CAN not answer in this mode
+
+     while( (pCAN0Transfer->test_can != AT91C_TEST_OK)
+         && (tick < AT91C_CAN_TIMEOUT) ) {
+        tick++;
+    }
+    if (tick == AT91C_CAN_TIMEOUT) {
+        trace_LOG( trace_ERROR, "-E- CAN0 Initialisations FAILED\n\r");
+        return 0;
+    } else {
+        trace_LOG( trace_INFO, "-I- CAN0 Initialisations Completed\n\r");
+    }
+
+#if defined AT91C_BASE_CAN1
+    if( pCAN1Transfer != NULL ) {
+        AT91C_BASE_CAN1->CAN_IER = AT91C_CAN_WAKEUP;
+        // CAN Controller Enable
+        AT91C_BASE_CAN1->CAN_MR = AT91C_CAN_CANEN;
+
+        tick = 0;
+        // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver
+        while( ((pCAN1Transfer->test_can != AT91C_TEST_OK)) 
+            && (tick < AT91C_CAN_TIMEOUT) ) {
+            tick++;
+        }
+
+        if (tick == AT91C_CAN_TIMEOUT) {
+            trace_LOG( trace_ERROR, "-E- CAN1 Initialisations FAILED\n\r");
+            return 0;
+        } else {
+            trace_LOG( trace_INFO, "-I- CAN1 Initialisations Completed\n\r");
+        }
+    }
+#endif
+    return 1;
+}
+
+//------------------------------------------------------------------------------
+/// Write a CAN transfer
+/// \param pTransfer can transfer structure
+/// \return return CAN_STATUS_SUCCESS if command passed, otherwise 
+///         return CAN_STATUS_LOCKED
+//------------------------------------------------------------------------------
+unsigned char CAN_Write( CanTransfer *pTransfer )
+{
+    AT91PS_CAN base_can;
+
+    if (pTransfer->state == CAN_RECEIVING)  {
+        pTransfer->state = CAN_IDLE;
+    }
+
+    if (pTransfer->state != CAN_IDLE)  {
+        return CAN_STATUS_LOCKED;
+    }
+
+    trace_LOG( trace_DEBUG, "CAN_Write\n\r");
+    pTransfer->state = CAN_SENDING;
+    if( pTransfer->can_number == 0 ) {
+        base_can = AT91C_BASE_CAN0;
+    }
+#ifdef AT91C_BASE_CAN1
+    else {
+        base_can = AT91C_BASE_CAN1;
+    }
+#endif
+    base_can->CAN_TCR = pTransfer->mailbox_in_use;
+    base_can->CAN_IER = pTransfer->mailbox_in_use;
+
+    return CAN_STATUS_SUCCESS;
+
+}
+
+
+//------------------------------------------------------------------------------
+/// Read a CAN transfer
+/// \param pTransfer can transfer structure
+/// \return return CAN_STATUS_SUCCESS if command passed, otherwise 
+///         return CAN_STATUS_LOCKED
+//------------------------------------------------------------------------------
+unsigned char CAN_Read( CanTransfer *pTransfer )
+{
+    AT91PS_CAN base_can;
+
+    if (pTransfer->state != CAN_IDLE)  {
+        return CAN_STATUS_LOCKED;
+    }
+
+    trace_LOG( trace_DEBUG, "CAN_Read\n\r");
+    pTransfer->state = CAN_RECEIVING;
+
+
+    if( pTransfer->can_number == 0 ) {
+        base_can = AT91C_BASE_CAN0;
+    }
+#ifdef AT91C_BASE_CAN1
+    else {
+        base_can = AT91C_BASE_CAN1;
+    }
+#endif
+    // enable interrupt
+    base_can->CAN_IER = pTransfer->mailbox_in_use;
+
+    return CAN_STATUS_SUCCESS;
+}
+
+//------------------------------------------------------------------------------
+/// Test if CAN is in IDLE state
+/// \param pTransfer can transfer structure
+/// \return return 0 if CAN is in IDLE, otherwise return 1
+//------------------------------------------------------------------------------
+unsigned char CAN_IsInIdle( CanTransfer *pTransfer )
+{
+  return( pTransfer->state != CAN_IDLE );
+}
+
+//------------------------------------------------------------------------------
+/// Basic CAN test without Interrupt
+//------------------------------------------------------------------------------
+void CAN_BasicTestSuiteWithoutInterrupt(void)
+{
+#if defined AT91C_BASE_CAN1
+    unsigned int status;
+    unsigned int tick=0;
+
+    trace_LOG( trace_INFO, "Without Interrupt ");
+    trace_LOG( trace_INFO, "CAN0 Mailbox 0 transmitting to CAN1 Mailbox 0\n\r");
+    // Init CAN0 Mailbox 0, transmit
+    CAN_ResetTransfer( pCAN0Transfer );
+    pCAN0Transfer->can_number = 0;
+    pCAN0Transfer->mailbox_number = 0;
+    pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | AT91C_CAN_PRIOR;
+    pCAN0Transfer->acceptance_mask_reg = 0x00000000;
+    pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x07<<18);
+    pCAN0Transfer->data_low_reg = 0x11223344;
+    pCAN0Transfer->data_high_reg = 0x01234567;
+    pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16));
+    CAN_InitMailboxRegisters( pCAN0Transfer );
+
+    // Init CAN1 Mailbox 0, receive, 
+    CAN_ResetTransfer( pCAN1Transfer );
+    pCAN1Transfer->can_number = 1;
+    pCAN1Transfer->mailbox_number = 0;
+    pCAN1Transfer->mode_reg = AT91C_CAN_MOT_RX;
+    pCAN1Transfer->acceptance_mask_reg = AT91C_CAN_MIDvA | AT91C_CAN_MIDvB;
+    pCAN1Transfer->identifier = AT91C_CAN_MIDvA & (0x07<<18);
+    pCAN1Transfer->data_low_reg = 0x00000000;
+    pCAN1Transfer->data_high_reg = 0x00000000;
+    pCAN1Transfer->control_reg = 0x00000000;
+    CAN_InitMailboxRegisters( pCAN1Transfer );
+
+    // Transfer Request for Mailbox 0
+    AT91C_BASE_CAN0->CAN_TCR = AT91C_CAN_MB0;
+
+    tick = 0;
+    do {
+        // CAN Message Status Register
+        status = AT91C_BASE_CAN0_MB0->CAN_MB_MSR;
+    }
+    while( !(status & AT91C_CAN_MRDY) && (++tick < AT91C_CAN_TIMEOUT) );
+
+    if (tick == AT91C_CAN_TIMEOUT) {
+        trace_LOG( trace_ERROR, "-E- Test FAILED\n\r");
+    } 
+    else {
+        trace_LOG( trace_DEBUG, "-I- Transfer completed: CAN1 Mailbox 0 MRDY flag has raised\n\r");
+        if( AT91C_BASE_CAN0_MB0->CAN_MB_MDL != AT91C_BASE_CAN1_MB0->CAN_MB_MDL ) {
+            trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");
+        }
+        else if( AT91C_BASE_CAN0_MB0->CAN_MB_MDH != AT91C_BASE_CAN1_MB0->CAN_MB_MDH ) {
+            trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");
+        }
+        else {
+            trace_LOG( trace_INFO, "Test passed\n\r");
+        }
+    }
+
+    CAN_ResetAllMailbox();
+
+    trace_LOG( trace_INFO, "Without Interrupt ");
+    trace_LOG( trace_INFO, "CAN0 Mailboxes 1 & 2 transmitting to CAN1 Mailbox 15\n\r");
+    // Init CAN0 Mailbox 1, transmit
+    CAN_ResetTransfer( pCAN0Transfer );
+    pCAN0Transfer->can_number = 0;
+    pCAN0Transfer->mailbox_number = 1;
+    pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | AT91C_CAN_PRIOR;
+    pCAN0Transfer->acceptance_mask_reg = 0x00000000;
+    pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x09<<18);      // ID 9
+    pCAN0Transfer->data_low_reg = 0xAABBCCDD;
+    pCAN0Transfer->data_high_reg = 0xCAFEDECA;
+    pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16)); // Mailbox Data Length Code
+    CAN_InitMailboxRegisters( pCAN0Transfer );
+
+    // Init CAN0 Mailbox 2, transmit
+    pCAN0Transfer->can_number = 0;
+    pCAN0Transfer->mailbox_number = 2;
+    pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | (AT91C_CAN_PRIOR-(1<<16));
+    pCAN0Transfer->acceptance_mask_reg = 0x00000000;
+    pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x0A<<18);      // ID 10
+    pCAN0Transfer->data_low_reg = 0x55667788;
+    pCAN0Transfer->data_high_reg = 0x99AABBCC;
+    pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16)); // Mailbox Data Length Code
+    CAN_InitMailboxRegisters( pCAN0Transfer );
+
+    // Init CAN1 Mailbox 15, reception with overwrite
+    CAN_ResetTransfer( pCAN1Transfer );
+    pCAN1Transfer->can_number = 1;
+    pCAN1Transfer->mailbox_number = 15;
+    pCAN1Transfer->mode_reg = AT91C_CAN_MOT_RXOVERWRITE;
+    pCAN1Transfer->acceptance_mask_reg = 0;
+    pCAN1Transfer->identifier = 0x0;
+    pCAN1Transfer->data_low_reg = 0x00000000;
+    pCAN1Transfer->data_high_reg = 0x00000000;
+    pCAN1Transfer->control_reg = 0x00000000;
+    CAN_InitMailboxRegisters( pCAN1Transfer );
+
+    // Ask Transmissions on Mailbox 1 & 2 --> AT91C_CAN_MRDY & AT91C_CAN_MMI raises for Mailbox 15 CAN_MB_SR
+    AT91C_BASE_CAN0->CAN_TCR = AT91C_CAN_MB1 | AT91C_CAN_MB2;
+    
+    // Wait for Last Transmit Mailbox
+    tick = 0;
+    do  {
+        status = AT91C_BASE_CAN1_MB15->CAN_MB_MSR;
+    }
+    while( !(status & AT91C_CAN_MMI) && (++tick < AT91C_CAN_TIMEOUT) );
+
+    if (tick == AT91C_CAN_TIMEOUT) {
+    }
+    else {
+        trace_LOG( trace_DEBUG, "-I- Transfer completed: CAN1 Mailbox 15 MRDY and MMI flags have raised\n\r");
+        if( AT91C_BASE_CAN0_MB1->CAN_MB_MDL != AT91C_BASE_CAN1_MB15->CAN_MB_MDL ) {
+            trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");
+        }
+        else if( AT91C_BASE_CAN0_MB1->CAN_MB_MDH != AT91C_BASE_CAN1_MB15->CAN_MB_MDH ) {
+            trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");
+        }
+        else {
+            trace_LOG( trace_INFO, "Test passed\n\r");
+        }
+    }
+
+    CAN_ResetAllMailbox();
+    trace_LOG( trace_INFO, "Without Interrupt ");
+    trace_LOG( trace_INFO, "CAN0 Mailboxes 1 & 2 transmitting to CAN1 Mailbox 15\n\r");
+    // Init CAN0 Mailbox 1, transmit
+    CAN_ResetTransfer( pCAN0Transfer );
+    pCAN0Transfer->can_number = 0;
+    pCAN0Transfer->mailbox_number = 1;
+    pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | AT91C_CAN_PRIOR;
+    pCAN0Transfer->acceptance_mask_reg = 0x00000000;
+    pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x09<<18);      // ID 9
+    pCAN0Transfer->data_low_reg = 0xAABBCCDD;
+    pCAN0Transfer->data_high_reg = 0xCAFEDECA;
+    pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16)); // Mailbox Data Length Code
+    CAN_InitMailboxRegisters( pCAN0Transfer );
+
+    // Init CAN0 Mailbox 2, transmit
+    pCAN0Transfer->can_number = 0;
+    pCAN0Transfer->mailbox_number = 2;
+    pCAN0Transfer->mode_reg = AT91C_CAN_MOT_TX | (AT91C_CAN_PRIOR-(1<<16));
+    pCAN0Transfer->acceptance_mask_reg = 0x00000000;
+    pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x0A<<18);      // ID 10
+    pCAN0Transfer->data_low_reg = 0x55667788;
+    pCAN0Transfer->data_high_reg = 0x99AABBCC;
+    pCAN0Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16)); // Mailbox Data Length Code
+    CAN_InitMailboxRegisters( pCAN0Transfer );
+
+    // Init CAN1 Mailbox 15, reception with overwrite
+    CAN_ResetTransfer( pCAN1Transfer );
+    pCAN1Transfer->can_number = 1;
+    pCAN1Transfer->mailbox_number = 15;
+    pCAN1Transfer->mode_reg = AT91C_CAN_MOT_RX;
+    pCAN1Transfer->acceptance_mask_reg = 0;
+    pCAN1Transfer->identifier = 0x0;
+    pCAN1Transfer->data_low_reg = 0x00000000;
+    pCAN1Transfer->data_high_reg = 0x00000000;
+    pCAN1Transfer->control_reg = 0x00000000;
+    CAN_InitMailboxRegisters( pCAN1Transfer );
+
+    // Ask Transmissions on Mailbox 1 & 2 --> AT91C_CAN_MRDY & AT91C_CAN_MMI raises for Mailbox 15 CAN_MB_SR
+    AT91C_BASE_CAN0->CAN_TCR = AT91C_CAN_MB1 | AT91C_CAN_MB2;
+    
+    // Wait for Last Transmit Mailbox
+    tick = 0;
+    do  {
+        status = AT91C_BASE_CAN1_MB15->CAN_MB_MSR;
+    }
+    while( !(status & AT91C_CAN_MMI) && (++tick < AT91C_CAN_TIMEOUT) );
+
+    if (tick == AT91C_CAN_TIMEOUT) {
+    trace_LOG( trace_ERROR, "-E- Test FAILED\n\r");
+    }
+    else {
+        trace_LOG( trace_DEBUG, "Transfer completed: CAN1 Mailbox 15 MRDY and MMI flags have raised\n\r");
+        trace_LOG( trace_DEBUG, "MB_MDL: 0x%X\n\r", AT91C_BASE_CAN1_MB15->CAN_MB_MDL);
+        trace_LOG( trace_DEBUG, "MB_MDLH: 0x%X\n\r", AT91C_BASE_CAN1_MB15->CAN_MB_MDH);
+        if( AT91C_BASE_CAN0_MB2->CAN_MB_MDL != AT91C_BASE_CAN1_MB15->CAN_MB_MDL ) {
+            trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");
+        }
+        else if( AT91C_BASE_CAN0_MB2->CAN_MB_MDH != AT91C_BASE_CAN1_MB15->CAN_MB_MDH ) {
+            trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");
+        }
+        else {
+            trace_LOG( trace_INFO, "Test passed\n\r");
+        }
+    }
+
+    CAN_ResetAllMailbox();
+    trace_LOG( trace_INFO, "Without Interrupt ");
+    trace_LOG( trace_INFO, "CAN0 Mailbox 3 asking for CAN1 Mailbox 3 transmission\n\r");
+    // Init CAN0 Mailbox 3, consumer mailbox
+    // Sends a remote frame and waits for an answer
+    CAN_ResetTransfer( pCAN0Transfer );
+    pCAN0Transfer->can_number = 0;
+    pCAN0Transfer->mailbox_number = 3;
+    pCAN0Transfer->mode_reg = AT91C_CAN_MOT_CONSUMER | AT91C_CAN_PRIOR;
+    pCAN0Transfer->acceptance_mask_reg = AT91C_CAN_MIDvA | AT91C_CAN_MIDvB;
+    pCAN0Transfer->identifier = AT91C_CAN_MIDvA & (0x0B<<18);     // ID 11
+    pCAN0Transfer->data_low_reg = 0x00000000;
+    pCAN0Transfer->data_high_reg = 0x00000000;
+    pCAN0Transfer->control_reg = 0x00000000;
+    CAN_InitMailboxRegisters( pCAN0Transfer );
+
+    // Init CAN1 Mailbox 3, porducer mailbox
+    // Waits to receive a Remote Frame before sending its contents
+    CAN_ResetTransfer( pCAN1Transfer );
+    pCAN1Transfer->can_number = 1;
+    pCAN1Transfer->mailbox_number = 3;
+    pCAN1Transfer->mode_reg = AT91C_CAN_MOT_PRODUCER | AT91C_CAN_PRIOR;
+    pCAN1Transfer->acceptance_mask_reg = 0;
+    pCAN1Transfer->identifier = AT91C_CAN_MIDvA & (0x0B<<18);     // ID 11
+    pCAN1Transfer->data_low_reg = 0xEEDDFF00;
+    pCAN1Transfer->data_high_reg = 0x34560022;
+    pCAN1Transfer->control_reg = (AT91C_CAN_MDLC & (0x8<<16));
+    CAN_InitMailboxRegisters( pCAN1Transfer );
+
+    // Ask Transmissions on Mailbox 3 --> AT91C_CAN_MRDY raises for Mailbox 3 CAN_MB_SR
+    AT91C_BASE_CAN1->CAN_TCR = AT91C_CAN_MB3;
+    AT91C_BASE_CAN0->CAN_TCR = AT91C_CAN_MB3;
+
+    // Wait for Last Transmit Mailbox
+    tick = 0;
+    do  {
+        status = AT91C_BASE_CAN0_MB3->CAN_MB_MSR;
+    }
+    while( !(status & AT91C_CAN_MRDY) && (++tick < AT91C_CAN_TIMEOUT) );
+
+    if (tick == AT91C_CAN_TIMEOUT) {
+        trace_LOG( trace_ERROR, "-E- Test FAILED\n\r");
+    }
+    else {
+        trace_LOG( trace_DEBUG, "-I- Transfer Completed: CAN0 & CAN1 Mailboxes 3 MRDY flags have raised\n\r");
+        if( AT91C_BASE_CAN0_MB3->CAN_MB_MDL != AT91C_BASE_CAN1_MB3->CAN_MB_MDL ) {
+            trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");
+        }
+        else if( AT91C_BASE_CAN0_MB3->CAN_MB_MDH != AT91C_BASE_CAN1_MB3->CAN_MB_MDH ) {
+            trace_LOG( trace_ERROR, "-E- Data Corrupted\n\r");
+        }
+        else {
+            trace_LOG( trace_INFO, "Test passed\n\r");
+        }
+    }
+#endif // AT91C_BASE_CAN1
+
+  return;
+}
+
+
+//------------------------------------------------------------------------------
+/// Disable CAN and enter in low power
+//------------------------------------------------------------------------------
+void CAN_disable( void )
+{
+    // Disable the interrupt on the interrupt controller
+    AIC_DisableIT(AT91C_ID_CAN0);
+    // disable all IT
+    AT91C_BASE_CAN0->CAN_IDR = 0x1FFFFFFF;
+#if defined AT91C_BASE_CAN1
+    AIC_DisableIT(AT91C_ID_CAN1);
+    // disable all IT
+    AT91C_BASE_CAN1->CAN_IDR = 0x1FFFFFFF;
+#endif
+
+    // Enable Low Power mode
+    AT91C_BASE_CAN0->CAN_MR |= AT91C_CAN_LPM;
+
+    // Disable CANs Transceivers
+    // Enter standby mode
+    PIO_Set(&pin_can_transceiver_rs);
+#if defined (PIN_CAN_TRANSCEIVER_RXEN)
+    // Enable ultra Low Power mode
+    PIO_Clear(&pin_can_transceiver_rxen);
+#endif
+
+    // Disable clock for CAN PIO
+    AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_PIOA);
+
+    // Disable the CAN0 controller peripheral clock
+    AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_CAN0);
+
+}
+
+//------------------------------------------------------------------------------
+/// baudrate calcul
+/// \param base_CAN CAN base address
+/// \param baudrate Baudrate value
+///                 allowed values: 1000, 800, 500, 250, 125, 50, 25, 10
+/// \return return 1 in success, otherwise return 0
+//------------------------------------------------------------------------------
+unsigned char CAN_BaudRateCalculate( AT91PS_CAN   base_CAN, 
+                                     unsigned int baudrate )
+{
+    unsigned int BRP;
+    unsigned int PROPAG;
+    unsigned int PHASE1;
+    unsigned int PHASE2;
+    unsigned int SJW;
+    unsigned int t1t2;
+
+    base_CAN->CAN_BR = 0;
+
+    BRP = (BOARD_MCK / (baudrate*1000*16))-1;
+    //trace_LOG( trace_DEBUG, "BRP = 0x%X\n\r", BRP);
+    // timing Delay:
+    // Delay Bus Driver: 50 ns
+    // Delay Receiver:   30 ns
+    // Delay Bus Line:  110 ns
+    if( (16*baudrate*2*(50+30+110)/1000000) >= 1) {
+        PROPAG = (16*baudrate*2*(50+30+110)/1000000)-1;
+    }
+    else {
+        PROPAG = 0;
+    }
+    //trace_LOG( trace_DEBUG, "PROPAG = 0x%X\n\r", PROPAG);
+
+    t1t2 = 15-(PROPAG+1);
+    //trace_LOG( trace_DEBUG, "t1t2 = 0x%X\n\r", t1t2);
+
+    if( (t1t2 & 0x01) == 0x01 ) {
+        // ODD
+        //trace_LOG( trace_DEBUG, "ODD\n\r");
+        PHASE1 = ((t1t2-1)/2)-1;
+        PHASE2 = PHASE1+1;
+    }
+    else {
+        // EVEN
+        //trace_LOG( trace_DEBUG, "EVEN\n\r");
+        PHASE1 = (t1t2/2)-1;
+        PHASE2 = PHASE1;
+    }
+    //trace_LOG( trace_DEBUG, "PHASE1 = 0x%X\n\r", PHASE1);
+    //trace_LOG( trace_DEBUG, "PHASE2 = 0x%X\n\r", PHASE2);
+
+    if( 1 > (4/(PHASE1+1)) ) {
+        //trace_LOG( trace_DEBUG, "4*Tcsc\n\r");
+        SJW = 3;
+    }
+    else {
+        //trace_LOG( trace_DEBUG, "Tphs1\n\r");
+        SJW = PHASE1;
+    }
+    //trace_LOG( trace_DEBUG, "SJW = 0x%X\n\r", SJW);
+    // Verif
+    if( BRP == 0 ) {
+        trace_LOG( trace_DEBUG, "BRP = 0 is not authorized\n\r");
+        return 0;
+    }
+    if( (PROPAG + PHASE1 + PHASE2) != 12 ) {
+        trace_LOG( trace_DEBUG, "(PROPAG + PHASE1 + PHASE2) != 12\n\r");
+        return 0;
+    }
+    base_CAN->CAN_BR = (AT91C_CAN_PHASE2 & (PHASE2 <<  0))
+                     + (AT91C_CAN_PHASE1 & (PHASE1 <<  4))
+                     + (AT91C_CAN_PROPAG & (PROPAG <<  8))
+                     + (AT91C_CAN_SYNC   & (SJW << 12))
+                     + (AT91C_CAN_BRP    & (BRP << 16))
+                     + (AT91C_CAN_SMP    & (0 << 24));
+    return 1;
+
+}
+
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+/// Init of the CAN peripheral
+/// \param baudrate Baudrate value
+///                 allowed values: 1000, 800, 500, 250, 125, 50, 25, 10
+/// \param canTransfer0 CAN0 structure transfer
+/// \param canTransfer1 CAN1 structure transfer
+/// \return return 1 if CAN has good baudrate and CAN is synchronized, 
+///         otherwise return 0
+//------------------------------------------------------------------------------
+unsigned char CAN_Init( unsigned int baudrate, 
+                        CanTransfer *canTransfer0, 
+                        CanTransfer *canTransfer1 ) 
+{
+    unsigned char ret;
+
+    // CAN Transmit Serial Data
+#if defined (PINS_CAN_TRANSCEIVER_TXD)
+    PIO_Configure(pins_can_transceiver_txd, PIO_LISTSIZE(pins_can_transceiver_txd));
+#endif
+#if defined (PINS_CAN_TRANSCEIVER_RXD)
+    // CAN Receive Serial Data
+    PIO_Configure(pins_can_transceiver_rxd, PIO_LISTSIZE(pins_can_transceiver_rxd));
+#endif
+    // CAN RS
+    PIO_Configure(&pin_can_transceiver_rs, PIO_LISTSIZE(pin_can_transceiver_rs));
+#if defined (PIN_CAN_TRANSCEIVER_RXEN)
+    // CAN RXEN
+    PIO_Configure(&pin_can_transceiver_rxen, PIO_LISTSIZE(pin_can_transceiver_rxen));
+#endif
+
+    // Enable clock for CAN PIO
+    AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOA);
+
+    // Enable the CAN0 controller peripheral clock
+    AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_CAN0);
+
+    // disable all IT
+    AT91C_BASE_CAN0->CAN_IDR = 0x1FFFFFFF;
+
+    // Enable CANs Transceivers
+#if defined (PIN_CAN_TRANSCEIVER_RXEN)
+    // Disable ultra Low Power mode
+    PIO_Set(&pin_can_transceiver_rxen);
+#endif
+    // Normal Mode (versus Standby mode)
+    PIO_Clear(&pin_can_transceiver_rs);
+
+    // Configure the AIC for CAN interrupts
+    AIC_ConfigureIT(AT91C_ID_CAN0, AT91C_AIC_PRIOR_HIGHEST, CAN0_Handler);
+
+    // Enable the interrupt on the interrupt controller
+    AIC_EnableIT(AT91C_ID_CAN0);
+
+    if( CAN_BaudRateCalculate(AT91C_BASE_CAN0, baudrate) == 0 ) {
+        // Baudrate problem
+        trace_LOG( trace_DEBUG, "Baudrate CAN0 problem\n\r");
+        return 0;
+    }
+
+    pCAN0Transfer = canTransfer0;
+
+#if defined AT91C_BASE_CAN1
+    if( canTransfer1 != NULL ) {
+        pCAN1Transfer = canTransfer1;
+        // Enable CAN1 Clocks
+        AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_CAN1);
+
+        // disable all IT
+        AT91C_BASE_CAN1->CAN_IDR = 0x1FFFFFFF;
+
+        // Configure the AIC for CAN interrupts
+        AIC_ConfigureIT(AT91C_ID_CAN1, AT91C_AIC_PRIOR_HIGHEST, CAN1_Handler);
+
+        // Enable the interrupt on the interrupt controller
+        AIC_EnableIT(AT91C_ID_CAN1);
+
+        if( CAN_BaudRateCalculate(AT91C_BASE_CAN1, baudrate) == 0 ) {
+            // Baudrate problem
+            trace_LOG( trace_DEBUG, "Baudrate CAN1 problem\n\r");
+            return 0;
+        }
+    }
+#endif
+    // Reset all mailbox
+    CAN_ResetAllMailbox();
+
+    // Enable the interrupt with all error cases
+    AT91C_BASE_CAN0->CAN_IER =  AT91C_CAN_CERR  // (CAN) CRC Error
+                             |  AT91C_CAN_SERR  // (CAN) Stuffing Error
+                             |  AT91C_CAN_BERR  // (CAN) Bit Error
+                             |  AT91C_CAN_FERR  // (CAN) Form Error
+                             |  AT91C_CAN_AERR; // (CAN) Acknowledgment Error
+
+#if defined AT91C_BASE_CAN1
+    if( canTransfer1 != NULL ) {
+        AT91C_BASE_CAN1->CAN_IER =  AT91C_CAN_CERR  // (CAN) CRC Error
+                                 |  AT91C_CAN_SERR  // (CAN) Stuffing Error
+                                 |  AT91C_CAN_BERR  // (CAN) Bit Error
+                                 |  AT91C_CAN_FERR  // (CAN) Form Error
+                                 |  AT91C_CAN_AERR; // (CAN) Acknowledgment Error
+    }
+#endif
+
+    // Wait for CAN synchronisation
+    if( CAN_Synchronisation( ) == 1 ) {
+        ret = 1;
+    }
+    else {
+        ret = 0;
+    }
+
+    return ret;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/can/can.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/can/can.h
new file mode 100644
index 0000000..63a83b3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/can/can.h
@@ -0,0 +1,113 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _CAN_H
+#define _CAN_H
+
+//------------------------------------------------------------------------------
+//      Definitions
+//------------------------------------------------------------------------------
+#define AT91C_CAN_TIMEOUT         100000
+
+#define AT91C_TEST_NOK                 0
+#define AT91C_TEST_OK                  1
+
+#define CAN_STATUS_SUCCESS             0
+#define CAN_STATUS_LOCKED              1
+#define CAN_STATUS_ABORTED             2
+#define CAN_STATUS_RESET               3
+
+#if defined (AT91C_BASE_CAN)
+    #define AT91C_BASE_CAN0      AT91C_BASE_CAN
+#endif
+#if defined (AT91C_ID_CAN)
+    #define AT91C_ID_CAN0        AT91C_ID_CAN
+#endif
+#if defined (AT91C_BASE_CAN_MB0)
+    #define AT91C_BASE_CAN0_MB0  AT91C_BASE_CAN_MB0
+    #define AT91C_BASE_CAN0_MB1  AT91C_BASE_CAN_MB1
+    #define AT91C_BASE_CAN0_MB2  AT91C_BASE_CAN_MB2
+    #define AT91C_BASE_CAN0_MB3  AT91C_BASE_CAN_MB3
+    #define AT91C_BASE_CAN0_MB4  AT91C_BASE_CAN_MB4
+    #define AT91C_BASE_CAN0_MB5  AT91C_BASE_CAN_MB5
+    #define AT91C_BASE_CAN0_MB6  AT91C_BASE_CAN_MB6
+    #define AT91C_BASE_CAN0_MB7  AT91C_BASE_CAN_MB7
+#endif
+#if defined (AT91C_BASE_CAN_MB8)
+    #define AT91C_BASE_CAN0_MB8   AT91C_BASE_CAN_MB8
+    #define AT91C_BASE_CAN0_MB9   AT91C_BASE_CAN_MB9
+    #define AT91C_BASE_CAN0_MB10  AT91C_BASE_CAN_MB10
+    #define AT91C_BASE_CAN0_MB11  AT91C_BASE_CAN_MB11
+    #define AT91C_BASE_CAN0_MB12  AT91C_BASE_CAN_MB12
+    #define AT91C_BASE_CAN0_MB13  AT91C_BASE_CAN_MB13
+    #define AT91C_BASE_CAN0_MB14  AT91C_BASE_CAN_MB14
+    #define AT91C_BASE_CAN0_MB15  AT91C_BASE_CAN_MB15
+#endif
+
+#define NUM_MAILBOX_MAX 16
+
+//------------------------------------------------------------------------------
+//         Types
+//------------------------------------------------------------------------------
+typedef struct
+{
+    volatile unsigned char state;
+    volatile unsigned char can_number;
+    volatile unsigned char mailbox_number;
+    volatile unsigned char test_can;
+    volatile unsigned int  mode_reg;
+    volatile unsigned int  acceptance_mask_reg;
+    volatile unsigned int  identifier;
+    volatile unsigned int  data_low_reg;
+    volatile unsigned int  data_high_reg;
+    volatile unsigned int  control_reg;
+    volatile unsigned int  mailbox_in_use;
+    volatile int           size;
+} CanTransfer;
+
+//------------------------------------------------------------------------------
+//         Exported functions
+//------------------------------------------------------------------------------
+extern unsigned char CAN_Init( unsigned int baudrate, 
+                               CanTransfer *canTransferRead, 
+                               CanTransfer *canTransferWrite );
+extern void CAN_BasicTestSuite(void);
+extern void CAN_disable( void );
+extern void CAN_ResetAllMailbox( void );
+extern void CAN_ResetTransfer( CanTransfer *pTransfer );
+extern void CAN_InitMailboxRegisters( CanTransfer *pTransfer );
+extern unsigned char CAN_IsInIdle( CanTransfer *pTransfer );
+
+extern unsigned char CAN_Write( CanTransfer *pTransfer );
+extern unsigned char CAN_Read( CanTransfer *pTransfer );
+
+extern void CAN_BasicTestSuiteWithoutInterrupt( void );
+extern unsigned char CAN_IsInIdle( CanTransfer *pTransfer );
+#endif // _CAN_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/dbgu/dbgu.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/dbgu/dbgu.c
new file mode 100644
index 0000000..3cb7af5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/dbgu/dbgu.c
@@ -0,0 +1,156 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+//      Headers
+//------------------------------------------------------------------------------
+
+#include "dbgu.h"
+#include 
+#include 
+            
+//------------------------------------------------------------------------------
+//      Exported functions
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+/// Initializes the DBGU with the given parameters, and enables both the
+/// transmitter and the receiver.
+/// \param mode  Operating mode to configure (see ).
+/// \param baudrate  Desired baudrate.
+/// \param mck  Frequency of the system master clock.
+//------------------------------------------------------------------------------
+void DBGU_Configure(unsigned int mode,
+                           unsigned int baudrate,
+                           unsigned int mck)
+{   
+    // Reset & disable receiver and transmitter, disable interrupts
+    AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RSTRX | AT91C_US_RSTTX;
+    AT91C_BASE_DBGU->DBGU_IDR = 0xFFFFFFFF;
+    
+    // Configure baud rate
+    AT91C_BASE_DBGU->DBGU_BRGR = mck / (baudrate * 16);
+    
+    // Configure mode register
+    AT91C_BASE_DBGU->DBGU_MR = mode;
+    
+    // Disable DMA channel
+    AT91C_BASE_DBGU->DBGU_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS;
+
+    // Enable receiver and transmitter
+    AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RXEN | AT91C_US_TXEN;
+}
+
+//------------------------------------------------------------------------------
+/// Outputs a character on the DBGU line.
+/// \param c  Character to send.
+//------------------------------------------------------------------------------
+static void DBGU_PutChar(unsigned char c)
+{
+    // Wait for the transmitter to be ready
+    while ((AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXEMPTY) == 0);
+    
+    // Send character
+    AT91C_BASE_DBGU->DBGU_THR = c;
+    
+    // Wait for the transfer to complete
+    while ((AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXEMPTY) == 0);
+}
+
+//------------------------------------------------------------------------------
+/// Reads and returns a character from the DBGU.
+//------------------------------------------------------------------------------
+unsigned char DBGU_GetChar()
+{
+    while ((AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_RXRDY) == 0);
+    return AT91C_BASE_DBGU->DBGU_RHR;
+}
+
+#ifndef NOFPUT
+
+#include 
+
+//------------------------------------------------------------------------------
+/// Implementation of fputc using the DBGU as the standard output. Required
+/// for printf().
+/// Returns the character written if successful, or -1 if the output stream is
+/// not stdout or stderr.
+/// \param c  Character to write.
+/// \param pStream  Output stream.
+//------------------------------------------------------------------------------
+signed int fputc(signed int c, FILE *pStream)
+{
+    if ((pStream == stdout) || (pStream == stderr)) {
+    
+        DBGU_PutChar(c);
+        return c;
+    }
+    else {
+
+        return EOF;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Implementation of fputs using the DBGU as the standard output. Required
+/// for printf(). Does NOT currently use the PDC.
+/// Returns the number of characters written if successful, or -1 if the output
+/// stream is not stdout or stderr.
+/// \param pStr  String to write.
+/// \param pStream  Output stream.
+//------------------------------------------------------------------------------
+signed int fputs(const char *pStr, FILE *pStream)
+{
+    signed int num = 0;
+
+    while (*pStr != 0) {
+
+        if (fputc(*pStr, pStream) == -1) {
+
+            return -1;
+        }
+        num++;
+        pStr++;
+    }
+
+    return num;
+}
+
+#undef putchar
+
+//------------------------------------------------------------------------------
+/// Outputs a character on the DBGU. Returns the character itself.
+/// \param c  Character to output.
+//------------------------------------------------------------------------------
+signed int putchar(signed int c)
+{
+    return fputc(c, stdout);
+}
+
+#endif //#ifndef NOFPUT
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/dbgu/dbgu.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/dbgu/dbgu.h
new file mode 100644
index 0000000..1893016
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/dbgu/dbgu.h
@@ -0,0 +1,72 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+/// \dir
+/// !Purpose
+/// 
+/// This module provides definitions and functions for using the DBGU.
+///
+/// !Usage
+/// 
+/// -# Enable the DBGU pins (see pio.h).
+/// -# Configure the DBGU using DBGU_Configure.
+///
+/// \note Unless specified, all the functions defined here operate synchronously;
+/// i.e. they all wait the data is sent/received before returning.
+//------------------------------------------------------------------------------
+
+#ifndef DBGU_H
+#define DBGU_H
+
+//------------------------------------------------------------------------------
+//         Definitions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \page Modes
+/// This page lists several common operating modes for the DBGU.
+/// !Modes
+/// - DBGU_STANDARD
+ 
+/// Standard operating mode (asynchronous, 8bit, no parity)
+#define DBGU_STANDARD           AT91C_US_PAR_NONE
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+//      Exported functions
+//------------------------------------------------------------------------------
+extern void DBGU_Configure(unsigned int mode,
+                           unsigned int baudrate,
+                           unsigned int mck);
+
+extern unsigned char DBGU_GetChar();
+
+#endif //#ifndef DBGU_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/eefc/eefc.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/eefc/eefc.c
new file mode 100644
index 0000000..cf0fdbe
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/eefc/eefc.c
@@ -0,0 +1,228 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef trace_LEVEL
+    #define trace_LEVEL trace_INFO
+#endif
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "eefc.h"
+
+#ifdef BOARD_FLASH_EEFC
+
+#include 
+#include 
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Enables the flash ready interrupt source on the EEFC peripheral.
+//------------------------------------------------------------------------------
+void EFC_EnableFrdyIt(void)
+{
+    AT91C_BASE_EFC->EFC_FMR |= AT91C_EFC_FRDY;
+}
+
+//------------------------------------------------------------------------------
+/// Disables the flash ready interrupt source on the EEFC peripheral.
+//------------------------------------------------------------------------------
+void EFC_DisableFrdyIt(void)
+{
+    AT91C_BASE_EFC->EFC_FMR &= ~AT91C_EFC_FRDY;
+}
+
+//------------------------------------------------------------------------------
+/// Translates the given address page and offset values. The resulting
+/// values are stored in the provided variables if they are not null.
+/// \param address  Address to translate.
+/// \param pPage  First page accessed.
+/// \param pOffset  Byte offset in first page.
+//------------------------------------------------------------------------------
+void EFC_TranslateAddress(
+    unsigned int address,
+    unsigned short *pPage,
+    unsigned short *pOffset)
+{
+    unsigned short page;
+    unsigned short offset;
+
+    SANITY_CHECK(address >= AT91C_IFLASH);
+    SANITY_CHECK(address <= (AT91C_IFLASH + AT91C_IFLASH_SIZE));
+
+    // Calculate page & offset
+    page = (address - AT91C_IFLASH) / AT91C_IFLASH_PAGE_SIZE;
+    offset = (address - AT91C_IFLASH) % AT91C_IFLASH_PAGE_SIZE;
+    trace_LOG(trace_DEBUG,
+              "-D- Translated 0x%08X to page=%d and offset=%d\n\r",
+              address, page, offset);
+
+    // Store values
+    if (pPage) {
+
+        *pPage = page;
+    }
+    if (pOffset) {
+
+        *pOffset = offset;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Computes the address of a flash access given the page and offset.
+/// \param page  Page number.
+/// \param offset  Byte offset inside page.
+/// \param pAddress  Computed address (optional).
+//------------------------------------------------------------------------------
+void EFC_ComputeAddress(
+    unsigned short page,
+    unsigned short offset,
+    unsigned int *pAddress)
+{
+    unsigned int address;
+
+    SANITY_CHECK(page <= AT91C_IFLASH_NB_OF_PAGES);
+    SANITY_CHECK(offset < AT91C_IFLASH_PAGE_SIZE);
+
+    // Compute address
+    address = AT91C_IFLASH + page * AT91C_IFLASH_PAGE_SIZE + offset;
+
+    // Store result
+    if (pAddress) {
+
+        *pAddress = address;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Starts the executing the given command on the EEFC. This function returns
+/// as soon as the command is started. It does NOT set the FMCN field automatically.
+/// \param command  Command to execute.
+/// \param argument  Command argument (should be 0 if not used).
+//------------------------------------------------------------------------------
+void EFC_StartCommand(unsigned char command, unsigned short argument)
+{
+    // Check command & argument
+    switch (command) {
+
+        case AT91C_EFC_FCMD_WP:
+        case AT91C_EFC_FCMD_WPL:
+        case AT91C_EFC_FCMD_EWP: 
+        case AT91C_EFC_FCMD_EWPL:
+        case AT91C_EFC_FCMD_EPL:
+        case AT91C_EFC_FCMD_EPA:
+        case AT91C_EFC_FCMD_SLB:
+        case AT91C_EFC_FCMD_CLB:
+            ASSERT(argument < AT91C_IFLASH_NB_OF_PAGES,
+                   "-F- Embedded flash has only %d pages\n\r",
+                   AT91C_IFLASH_NB_OF_PAGES);
+            break;
+
+        case AT91C_EFC_FCMD_SFB:
+        case AT91C_EFC_FCMD_CFB:
+            ASSERT(argument < EFC_NUM_GPNVMS, "-F- Embedded flash has only %d GPNVMs\n\r", EFC_NUM_GPNVMS);
+            break;
+
+        case AT91C_EFC_FCMD_GETD:
+        case AT91C_EFC_FCMD_EA:
+        case AT91C_EFC_FCMD_GLB:
+        case AT91C_EFC_FCMD_GFB:
+            ASSERT(argument == 0, "-F- Argument is meaningless for the given command.\n\r");
+            break;
+
+        default: ASSERT(0, "-F- Unknown command %d\n\r", command);
+    }
+
+    // Start commandEmbedded flash 
+    ASSERT((AT91C_BASE_EFC->EFC_FSR & AT91C_EFC_FRDY) == AT91C_EFC_FRDY, "-F- EEFC is not ready\n\r");
+    AT91C_BASE_EFC->EFC_FCR = (0x5A << 24) | (argument << 8) | command;
+}
+
+//------------------------------------------------------------------------------
+/// Performs the given command and wait until its completion (or an error).
+/// Returns 0 if successful; otherwise returns an error code.
+/// \param command  Command to perform.
+/// \param argument  Optional command argument.
+//------------------------------------------------------------------------------
+#ifdef __ICCARM__
+__ramfunc
+#else
+__attribute__ ((section (".ramfunc")))
+#endif
+unsigned char EFC_PerformCommand(unsigned char command, unsigned short argument)
+{
+    unsigned int status;
+
+#ifdef BOARD_FLASH_IAP_ADDRESS
+    // Pointer on IAP function in ROM
+    static void (*IAP_PerformCommand)(unsigned int);
+    IAP_PerformCommand = (void (*)(unsigned int)) *((unsigned int *) BOARD_FLASH_IAP_ADDRESS);
+
+    // Check if IAP function is implemented (opcode in SWI != 'b' or 'ldr') */
+    if ((((((unsigned long) IAP_PerformCommand >> 24) & 0xFF) != 0xEA) &&
+        (((unsigned long) IAP_PerformCommand >> 24) & 0xFF) != 0xE5)) {
+
+        IAP_PerformCommand((0x5A << 24) | (argument << 8) | command);
+        return (AT91C_BASE_EFC->EFC_FSR & (AT91C_EFC_LOCKE | AT91C_EFC_FCMDE));
+    }
+#endif
+
+    AT91C_BASE_EFC->EFC_FCR = (0x5A << 24) | (argument << 8) | command;
+    do {
+
+        status = AT91C_BASE_EFC->EFC_FSR;
+    }
+    while ((status & AT91C_EFC_FRDY) != AT91C_EFC_FRDY);
+
+    return (status & (AT91C_EFC_LOCKE | AT91C_EFC_FCMDE));
+}
+
+//------------------------------------------------------------------------------
+/// Returns the current status of the EEFC. Keep in mind that this function clears
+/// the value of some status bits (LOCKE, PROGE).
+//------------------------------------------------------------------------------
+unsigned int EFC_GetStatus(void)
+{
+    return AT91C_BASE_EFC->EFC_FSR;
+}
+
+//------------------------------------------------------------------------------
+/// Returns the result of the last executed command.
+//------------------------------------------------------------------------------
+unsigned int EFC_GetResult(void) {
+
+    return AT91C_BASE_EFC->EFC_FRR;
+}
+
+#endif //#ifdef BOARD_FLASH_EEFC
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/eefc/eefc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/eefc/eefc.h
new file mode 100644
index 0000000..277e4c7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/eefc/eefc.h
@@ -0,0 +1,133 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef EEFC_H
+#define EEFC_H
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include 
+
+#ifdef BOARD_FLASH_EEFC
+
+//------------------------------------------------------------------------------
+//         Constants
+//------------------------------------------------------------------------------
+
+/// Number of GPNVMs available on each chip.
+#if defined(at91sam7l64) || defined(at91sam7l128)
+
+    #define EFC_NUM_GPNVMS          2
+
+#elif defined(at91sam9xe128) || defined(at91sam9xe256) || defined(at91sam9xe512)
+
+    #define EFC_NUM_GPNVMS          17
+#endif
+
+//------------------------------------------------------------------------------
+//         Types
+//------------------------------------------------------------------------------
+
+// Needed when EEFC is integrated in MC.
+#if !defined(AT91C_BASE_EFC) && defined(AT91C_BASE_MC)
+typedef struct _AT91S_EFC {
+	AT91_REG	 EFC_FMR; 	// EFC Flash Mode Register
+	AT91_REG	 EFC_FCR; 	// EFC Flash Command Register
+	AT91_REG	 EFC_FSR; 	// EFC Flash Status Register
+	AT91_REG	 EFC_FRR; 	// EFC Flash Result Register
+	AT91_REG	 EFC_FVR; 	// EFC Flash Version Register
+} AT91S_EFC, *AT91PS_EFC;
+
+#define AT91C_EFC_FRDY              AT91C_MC_FRDY
+#define AT91C_EFC_FWS               AT91C_MC_FWS
+#define AT91C_EFC_FWS_0WS           AT91C_MC_FWS_0WS
+#define AT91C_EFC_FWS_1WS           AT91C_MC_FWS_1WS
+#define AT91C_EFC_FWS_2WS           AT91C_MC_FWS_2WS
+#define AT91C_EFC_FWS_3WS           AT91C_MC_FWS_3WS
+#define AT91C_EFC_FCMD              AT91C_MC_FCMD
+#define AT91C_EFC_FCMD_GETD         AT91C_MC_FCMD_GETD
+#define AT91C_EFC_FCMD_WP           AT91C_MC_FCMD_WP  
+#define AT91C_EFC_FCMD_WPL          AT91C_MC_FCMD_WPL 
+#define AT91C_EFC_FCMD_EWP          AT91C_MC_FCMD_EWP 
+#define AT91C_EFC_FCMD_EWPL         AT91C_MC_FCMD_EWPL
+#define AT91C_EFC_FCMD_EA           AT91C_MC_FCMD_EA  
+#define AT91C_EFC_FCMD_EPL          AT91C_MC_FCMD_EPL 
+#define AT91C_EFC_FCMD_EPA          AT91C_MC_FCMD_EPA 
+#define AT91C_EFC_FCMD_SLB          AT91C_MC_FCMD_SLB 
+#define AT91C_EFC_FCMD_CLB          AT91C_MC_FCMD_CLB 
+#define AT91C_EFC_FCMD_GLB          AT91C_MC_FCMD_GLB 
+#define AT91C_EFC_FCMD_SFB          AT91C_MC_FCMD_SFB 
+#define AT91C_EFC_FCMD_CFB          AT91C_MC_FCMD_CFB 
+#define AT91C_EFC_FCMD_GFB          AT91C_MC_FCMD_GFB 
+#define AT91C_EFC_FARG              AT91C_MC_FARG     
+#define AT91C_EFC_FKEY              AT91C_MC_FKEY     
+#define AT91C_EFC_FRDY_S            AT91C_MC_FRDY_S   
+#define AT91C_EFC_FCMDE             AT91C_MC_FCMDE   
+#define AT91C_EFC_LOCKE             AT91C_MC_LOCKE    
+#define AT91C_EFC_FVALUE            AT91C_MC_FVALUE   
+
+#define AT91C_BASE_EFC              (AT91_CAST(AT91PS_EFC) 	0xFFFFFF60)    
+
+#endif //#if !defined(AT91C_BASE_EFC) && defined(AT91C_BASE_MC)
+
+//------------------------------------------------------------------------------
+//         Functions
+//------------------------------------------------------------------------------
+
+extern void EFC_EnableFrdyIt(void);
+
+extern void EFC_DisableFrdyIt(void);
+
+extern void EFC_TranslateAddress(
+    unsigned int address,
+    unsigned short *pPage,
+    unsigned short *pOffset);
+
+extern void EFC_ComputeAddress(
+    unsigned short page,
+    unsigned short offset,
+    unsigned int *pAddress);
+
+extern void EFC_StartCommand(
+    unsigned char command,
+    unsigned short argument);
+
+extern unsigned char EFC_PerformCommand(
+    unsigned char command,
+    unsigned short argument);
+
+extern unsigned int EFC_GetStatus(void);
+
+extern unsigned int EFC_GetResult(void);
+
+#endif //#ifdef BOARD_FLASH_EEFC
+#endif //#ifndef EEFC_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/efc/efc.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/efc/efc.c
new file mode 100644
index 0000000..b4637c8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/efc/efc.c
@@ -0,0 +1,387 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef trace_LEVEL
+    #define trace_LEVEL trace_INFO
+#endif
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "efc.h"
+
+#ifdef BOARD_FLASH_EFC
+
+#include 
+#include 
+
+//------------------------------------------------------------------------------
+//         Local definitions
+//------------------------------------------------------------------------------
+
+// Round a number to the nearest integral value (number must have been
+// multiplied by 10, e.g. to round 10.3 enter 103).
+#define ROUND(n)    ((((n) % 10) >= 5) ? (((n) / 10) + 1) : ((n) / 10))
+
+// Returns the FMCN field value when manipulating lock bits, given MCK.
+#if defined(at91sam7a3)
+    #define FMCN_BITS(mck)      (ROUND((mck) / 100000) << 16) // <- Not correct according to the datasheet but it works
+#else
+    #define FMCN_BITS(mck)      (ROUND((mck) / 100000) << 16)
+#endif
+
+// Returns the FMCN field value when manipulating the rest of the flash.
+#define FMCN_FLASH(mck)         ((((mck) / 2000000) * 3) << 16)
+
+//------------------------------------------------------------------------------
+//         Local functions
+//------------------------------------------------------------------------------
+
+
+/// Master clock frequency, used to infer the value of the FMCN field.
+static unsigned int lMck;
+/// Calculated value of the FMCN field base on Master clock frequency.
+static unsigned int lMckFMCN;
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Sets the system master clock so the FMCN field of the EFC(s) can be
+/// programmed properly.
+/// \param mck  Master clock frequency in Hz.
+//------------------------------------------------------------------------------
+void EFC_SetMasterClock(unsigned int mck)
+{
+    lMck = mck;
+    lMckFMCN = FMCN_BITS(lMck);
+}
+
+//------------------------------------------------------------------------------
+/// Enables the given interrupt sources on an EFC peripheral.
+/// \param pEfc  Pointer to an AT91S_EFC structure.
+/// \param sources  Interrupt sources to enable.
+//------------------------------------------------------------------------------
+void EFC_EnableIt(AT91S_EFC *pEfc, unsigned int sources)
+{
+    SANITY_CHECK(pEfc);
+    SANITY_CHECK((sources & ~0x0000000D) == 0);
+
+    pEfc->EFC_FMR |= sources;
+}
+
+//------------------------------------------------------------------------------
+/// Disables the given interrupt sources on an EFC peripheral.
+/// \param pEfc  Pointer to an AT91S_EFC structure.
+/// \param sources  Interrupt sources to disable.
+//------------------------------------------------------------------------------
+void EFC_DisableIt(AT91S_EFC *pEfc, unsigned int sources)
+{
+    SANITY_CHECK(pEfc);
+    SANITY_CHECK((sources & ~(AT91C_MC_FRDY | AT91C_MC_LOCKE | AT91C_MC_PROGE)) == 0);
+
+    pEfc->EFC_FMR &= ~sources;
+}
+
+//------------------------------------------------------------------------------
+/// Enables or disable the "Erase before programming" feature of an EFC.
+/// \param pEfc  Pointer to an AT91S_EFC structure.
+/// \param enable  If 1, the feature is enabled; otherwise it is disabled.
+//------------------------------------------------------------------------------
+void EFC_SetEraseBeforeProgramming(AT91S_EFC *pEfc, unsigned char enable)
+{
+    SANITY_CHECK(pEfc);
+
+    if (enable) {
+
+        pEfc->EFC_FMR &= ~AT91C_MC_NEBP;
+    }
+    else {
+
+        pEfc->EFC_FMR |= AT91C_MC_NEBP;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Translates the given address into EFC, page and offset values. The resulting
+/// values are stored in the provided variables if they are not null.
+/// \param address  Address to translate.
+/// \param ppEfc  Pointer to target EFC peripheral.
+/// \param pPage  First page accessed.
+/// \param pOffset  Byte offset in first page.
+//------------------------------------------------------------------------------
+void EFC_TranslateAddress(
+    unsigned int address,
+    AT91S_EFC **ppEfc,
+    unsigned short *pPage,
+    unsigned short *pOffset)
+{
+    AT91S_EFC *pEfc;
+    unsigned short page;
+    unsigned short offset;
+
+    SANITY_CHECK(address >= AT91C_IFLASH);
+    SANITY_CHECK(address <= (AT91C_IFLASH + AT91C_IFLASH_SIZE));
+
+#if defined(AT91C_BASE_EFC0)
+    if (address >= (AT91C_IFLASH + AT91C_IFLASH_SIZE / 2)) {
+
+        pEfc = AT91C_BASE_EFC1;
+        page = (address - AT91C_IFLASH - AT91C_IFLASH_SIZE / 2) / AT91C_IFLASH_PAGE_SIZE;
+        offset = (address - AT91C_IFLASH - AT91C_IFLASH_SIZE / 2) % AT91C_IFLASH_PAGE_SIZE;
+    }
+    else {
+
+        pEfc = AT91C_BASE_EFC0;
+        page = (address - AT91C_IFLASH) / AT91C_IFLASH_PAGE_SIZE;
+        offset = (address - AT91C_IFLASH) % AT91C_IFLASH_PAGE_SIZE;
+    }
+#else
+    pEfc = AT91C_BASE_EFC;
+    page = (address - AT91C_IFLASH) / AT91C_IFLASH_PAGE_SIZE;
+    offset = (address - AT91C_IFLASH) % AT91C_IFLASH_PAGE_SIZE;
+#endif
+    trace_LOG(trace_DEBUG,
+              "-D- Translated 0x%08X to EFC=0x%08X, page=%d and offset=%d\n\r",
+              address, (unsigned int) pEfc, page, offset);
+
+    // Store values
+    if (ppEfc) {
+
+        *ppEfc = pEfc;
+    }
+    if (pPage) {
+
+        *pPage = page;
+    }
+    if (pOffset) {
+
+        *pOffset = offset;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Computes the address of a flash access given the EFC, page and offset.
+/// \param pEfc  Pointer to an AT91S_EFC structure.
+/// \param page  Page number.
+/// \param offset  Byte offset inside page.
+/// \param pAddress  Computed address (optional).
+//------------------------------------------------------------------------------
+void EFC_ComputeAddress(
+    AT91S_EFC *pEfc,
+    unsigned short page,
+    unsigned short offset,
+    unsigned int *pAddress)
+{
+    unsigned int address;
+
+    SANITY_CHECK(pEfc);
+#if defined(AT91C_BASE_EFC1)
+    SANITY_CHECK(page <= (AT91C_IFLASH_NB_OF_PAGES / 2));
+#else
+    SANITY_CHECK(page <= AT91C_IFLASH_NB_OF_PAGES);
+#endif
+    SANITY_CHECK(offset < AT91C_IFLASH_PAGE_SIZE);
+
+    // Compute address
+    address = AT91C_IFLASH + page * AT91C_IFLASH_PAGE_SIZE + offset;
+#if defined(AT91C_BASE_EFC1)
+    if (pEfc == AT91C_BASE_EFC1) {
+
+        address += AT91C_IFLASH_SIZE / 2;
+    }
+#endif
+
+    // Store result
+    if (pAddress) {
+
+        *pAddress = address;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Starts the executing the given command on an EFC. This function returns
+/// as soon as the command is started. It does NOT set the FMCN field automatically.
+/// \param pEfc  Pointer to an AT91S_EFC structure.
+/// \param command  Command to execute.
+/// \param argument  Command argument (should be 0 if not used).
+//------------------------------------------------------------------------------
+void EFC_StartCommand(
+    AT91S_EFC *pEfc,
+    unsigned char command,
+    unsigned short argument)
+{
+    SANITY_CHECK(pEfc);
+    ASSERT(lMck != 0, "-F- Master clock not set.\n\r");
+
+    // Check command & argument
+    switch (command) {
+
+        case AT91C_MC_FCMD_PROG_AND_LOCK:
+            ASSERT(0, "-F- Write and lock command cannot be carried out.\n\r");
+            break;
+
+        case AT91C_MC_FCMD_START_PROG:
+        case AT91C_MC_FCMD_LOCK:
+        case AT91C_MC_FCMD_UNLOCK:
+            ASSERT(argument < AT91C_IFLASH_NB_OF_PAGES,
+                   "-F- Maximum number of pages is %d (argument was %d)\n\r",
+                   AT91C_IFLASH_NB_OF_PAGES,
+                   argument);
+            break;
+
+#if (EFC_NUM_GPNVMS > 0)
+        case AT91C_MC_FCMD_SET_GP_NVM:
+        case AT91C_MC_FCMD_CLR_GP_NVM:
+            ASSERT(argument < EFC_NUM_GPNVMS, "-F- A maximum of %d GPNVMs are available on the chip.\n\r", EFC_NUM_GPNVMS);
+            break;
+#endif
+
+        case AT91C_MC_FCMD_ERASE_ALL:
+
+#if !defined(EFC_NO_SECURITY_BIT)
+        case AT91C_MC_FCMD_SET_SECURITY:
+#endif
+            ASSERT(argument == 0, "-F- Argument is meaningless for the given command\n\r");
+            break;
+
+        default: ASSERT(0, "-F- Unknown command %d\n\r", command);
+    }
+
+    // Set FMCN
+    switch (command) {
+
+        case AT91C_MC_FCMD_LOCK:
+        case AT91C_MC_FCMD_UNLOCK:
+#if (EFC_NUM_GPNVMS > 0)
+        case AT91C_MC_FCMD_SET_GP_NVM:
+        case AT91C_MC_FCMD_CLR_GP_NVM:
+#endif
+#if !defined(EFC_NO_SECURITY_BIT)
+        case AT91C_MC_FCMD_SET_SECURITY:
+#endif
+            pEfc->EFC_FMR = (pEfc->EFC_FMR & ~AT91C_MC_FMCN) | lMckFMCN;
+            break;
+
+        case AT91C_MC_FCMD_START_PROG:
+        case AT91C_MC_FCMD_ERASE_ALL:
+            pEfc->EFC_FMR = (pEfc->EFC_FMR & ~AT91C_MC_FMCN) | lMckFMCN;
+            break;
+    }
+
+    // Start command
+    ASSERT((pEfc->EFC_FSR & AT91C_MC_FRDY) != 0, "-F- Efc is not ready\n\r");
+    pEfc->EFC_FCR = (0x5A << 24) | (argument << 8) | command;
+}
+
+//------------------------------------------------------------------------------
+/// Performs the given command and wait until its completion (or an error).
+/// Returns 0 if successful; otherwise returns an error code.
+/// \param pEfc  Pointer to an AT91S_EFC structure.
+/// \param command  Command to perform.
+/// \param argument  Optional command argument.
+//------------------------------------------------------------------------------
+#ifdef __ICCARM__
+__ramfunc
+#else
+__attribute__ ((section (".ramfunc")))
+#endif
+unsigned char EFC_PerformCommand(
+    AT91S_EFC *pEfc,
+    unsigned char command,
+    unsigned short argument)
+{
+    unsigned int status;
+
+    // Set FMCN
+    switch (command) {
+
+        case AT91C_MC_FCMD_LOCK:
+        case AT91C_MC_FCMD_UNLOCK:
+#if (EFC_NUM_GPNVMS > 0)
+        case AT91C_MC_FCMD_SET_GP_NVM:
+        case AT91C_MC_FCMD_CLR_GP_NVM:
+#endif
+#if !defined(EFC_NO_SECURITY_BIT)
+        case AT91C_MC_FCMD_SET_SECURITY:
+#endif
+            pEfc->EFC_FMR = (pEfc->EFC_FMR & ~AT91C_MC_FMCN) | lMckFMCN;
+            break;
+
+        case AT91C_MC_FCMD_START_PROG:
+        case AT91C_MC_FCMD_ERASE_ALL:
+            pEfc->EFC_FMR = (pEfc->EFC_FMR & ~AT91C_MC_FMCN) | lMckFMCN;
+            break;
+    }
+
+#ifdef BOARD_FLASH_IAP_ADDRESS
+    // Pointer on IAP function in ROM
+    static void (*IAP_PerformCommand)(unsigned int, unsigned int);
+    unsigned int index = 0;
+#ifdef AT91C_BASE_EFC1
+    if (pEfc == AT91C_BASE_EFC1) {
+
+        index = 1;
+    }
+#endif
+    IAP_PerformCommand = (void (*)(unsigned int, unsigned int)) *((unsigned int *) BOARD_FLASH_IAP_ADDRESS);
+
+    // Check if IAP function is implemented (opcode in SWI != 'b' or 'ldr') */
+    if ((((((unsigned long) IAP_PerformCommand >> 24) & 0xFF) != 0xEA) &&
+        (((unsigned long) IAP_PerformCommand >> 24) & 0xFF) != 0xE5)) {
+
+        IAP_PerformCommand(index, (0x5A << 24) | (argument << 8) | command);
+        return (pEfc->EFC_FSR & (AT91C_MC_LOCKE | AT91C_MC_PROGE));
+    }
+#endif
+
+    pEfc->EFC_FCR = (0x5A << 24) | (argument << 8) | command;
+    do {
+
+        status = pEfc->EFC_FSR;
+    }
+    while ((status & AT91C_MC_FRDY) == 0);
+
+    return (status & (AT91C_MC_PROGE | AT91C_MC_LOCKE));
+}
+
+//------------------------------------------------------------------------------
+/// Returns the current status of an EFC. Keep in mind that this function clears
+/// the value of some status bits (LOCKE, PROGE).
+/// \param pEfc  Pointer to an AT91S_EFC structure.
+//------------------------------------------------------------------------------
+unsigned int EFC_GetStatus(AT91S_EFC *pEfc)
+{
+    return pEfc->EFC_FSR;
+}
+
+#endif //#ifdef BOARD_FLASH_EFC
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/efc/efc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/efc/efc.h
new file mode 100644
index 0000000..6487c66
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/efc/efc.h
@@ -0,0 +1,127 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef EFC_H
+#define EFC_H
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include 
+
+#ifdef BOARD_FLASH_EFC
+
+//------------------------------------------------------------------------------
+//         Constants
+//------------------------------------------------------------------------------
+
+/// Number of GPNVMs available on each chip.
+#if defined(at91sam7s16) || defined(at91sam7s161) || defined(at91sam7s32) \
+    || defined(at91sam7s321) || defined(at91sam7s64) || defined(at91sam7s128) \
+    || defined(at91sam7s256) || defined(at91sam7s512)
+
+    #define EFC_NUM_GPNVMS          2
+
+#elif defined(at91sam7se32) || defined(at91sam7se256) || defined(at91sam7se512) \
+      || defined(at91sam7x128) || defined(at91sam7x256) || defined(at91sam7x512) \
+      || defined(at91sam7xc128) || defined(at91sam7xc256) || defined(at91sam7xc512) \
+
+    #define EFC_NUM_GPNVMS          3
+
+#elif defined(at91sam7a3)
+
+    #define EFC_NUM_GPNVMS          0
+#endif
+
+// Missing FRDY bit for SAM7A3
+#if defined(at91sam7a3)
+    #define AT91C_MC_FRDY       (AT91C_MC_EOP | AT91C_MC_EOL)
+#endif
+
+// No security bit on SAM7A3
+#if defined(at91sam7a3)
+    #define EFC_NO_SECURITY_BIT
+#endif
+
+//------------------------------------------------------------------------------
+//         Types
+//------------------------------------------------------------------------------
+
+// For chips which do not define AT91S_EFC
+#if !defined(AT91C_BASE_EFC) && !defined(AT91C_BASE_EFC0)
+typedef struct _AT91S_EFC {
+
+    AT91_REG EFC_FMR;
+    AT91_REG EFC_FCR;
+    AT91_REG EFC_FSR;
+
+} AT91S_EFC, *AT91PS_EFC;
+	#define AT91C_BASE_EFC       (AT91_CAST(AT91PS_EFC)	0xFFFFFF60) 
+#endif	
+
+//------------------------------------------------------------------------------
+//         Functions
+//------------------------------------------------------------------------------
+
+extern void EFC_SetMasterClock(unsigned int mck);
+
+extern void EFC_EnableIt(AT91S_EFC *pEfc, unsigned int sources);
+
+extern void EFC_DisableIt(AT91S_EFC *pEfc, unsigned int sources);
+
+extern void EFC_SetEraseBeforeProgramming(AT91S_EFC *pEfc, unsigned char enable);
+
+extern void EFC_TranslateAddress(
+    unsigned int address,
+    AT91S_EFC **ppEfc,
+    unsigned short *pPage,
+    unsigned short *pOffset);
+
+extern void EFC_ComputeAddress(
+    AT91S_EFC *pEfc,
+    unsigned short page,
+    unsigned short offset,
+    unsigned int *pAddress);
+
+extern void EFC_StartCommand(
+    AT91S_EFC *pEfc,
+    unsigned char command,
+    unsigned short argument);
+
+extern unsigned char EFC_PerformCommand(
+    AT91S_EFC *pEfc,
+    unsigned char command,
+    unsigned short argument);
+
+extern unsigned int EFC_GetStatus(AT91S_EFC *pEfc);
+
+#endif //#ifdef BOARD_FLASH_EFC
+#endif //#ifndef EFC_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/emac/emac.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/emac/emac.c
new file mode 100644
index 0000000..bc78725
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/emac/emac.c
@@ -0,0 +1,833 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//-----------------------------------------------------------------------------
+//         Headers
+//-----------------------------------------------------------------------------
+#include 
+#include "emac.h"
+#include 
+#include 
+#include 
+
+//------------------------------------------------------------------------------
+//         Definitions
+//------------------------------------------------------------------------------
+/// The buffer addresses written into the descriptors must be aligned so the
+/// last few bits are zero.  These bits have special meaning for the EMAC
+/// peripheral and cannot be used as part of the address.
+#define EMAC_ADDRESS_MASK   ((unsigned int)0xFFFFFFFC)
+#define EMAC_LENGTH_FRAME   ((unsigned int)0x0FFF)    /// Length of frame mask
+
+// receive buffer descriptor bits
+#define EMAC_RX_OWNERSHIP_BIT   (1UL <<  0)
+#define EMAC_RX_WRAP_BIT        (1UL <<  1)
+#define EMAC_RX_SOF_BIT         (1UL << 14)
+#define EMAC_RX_EOF_BIT         (1UL << 15)
+
+// Transmit buffer descriptor bits
+#define EMAC_TX_LAST_BUFFER_BIT (1UL << 15)
+#define EMAC_TX_WRAP_BIT        (1UL << 30)
+#define EMAC_TX_USED_BIT        (1UL << 31)
+
+//-----------------------------------------------------------------------------
+// Circular buffer management
+//-----------------------------------------------------------------------------
+// Return count in buffer
+#define CIRC_CNT(head,tail,size) (((head) - (tail)) & ((size)-1))
+
+// Return space available, 0..size-1
+// We always leave one free char as a completely full buffer
+// has head == tail, which is the same as empty
+#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size))
+
+// Return count up to the end of the buffer.
+// Carefully avoid accessing head and tail more than once,
+// so they can change underneath us without returning inconsistent results
+#define CIRC_CNT_TO_END(head,tail,size) \
+   ({int end = (size) - (tail); \
+     int n = ((head) + end) & ((size)-1); \
+     n < end ? n : end;})
+
+// Return space available up to the end of the buffer
+#define CIRC_SPACE_TO_END(head,tail,size) \
+   ({int end = (size) - 1 - (head); \
+     int n = (end + (tail)) & ((size)-1); \
+     n <= end ? n : end+1;})
+
+// Increment head or tail
+#define CIRC_INC(headortail,size) \
+        headortail++;             \
+        if(headortail >= size) {  \
+            headortail = 0;       \
+        }
+
+#define CIRC_EMPTY(circ)     ((circ)->head == (circ)->tail)
+#define CIRC_CLEAR(circ)     ((circ)->head = (circ)->tail = 0)
+
+
+//------------------------------------------------------------------------------
+//      Structures
+//------------------------------------------------------------------------------
+#ifdef __ICCARM__          // IAR
+#pragma pack(4)            // IAR
+#define __attribute__(...) // IAR
+#endif                     // IAR
+/// Describes the type and attribute of Receive Transfer descriptor.
+typedef struct _EmacRxTDescriptor {
+    unsigned int addr;
+    unsigned int status;
+} __attribute__((packed, aligned(8))) EmacRxTDescriptor, *PEmacRxTDescriptor;
+
+/// Describes the type and attribute of Transmit Transfer descriptor.
+typedef struct _EmacTxTDescriptor {
+    unsigned int addr;
+    unsigned int status;
+} __attribute__((packed, aligned(8))) EmacTxTDescriptor, *PEmacTxTDescriptor;
+#ifdef __ICCARM__          // IAR
+#pragma pack()             // IAR
+#endif                     // IAR
+
+/// Descriptors for RX (required aligned by 8)
+typedef struct {
+   volatile EmacRxTDescriptor td[RX_BUFFERS];
+   EMAC_RxCallback rxCb; /// Callback function to be invoked once a frame has been received
+   unsigned short idx;
+} RxTd;
+
+/// Descriptors for TX (required aligned by 8)
+typedef struct {
+   volatile EmacTxTDescriptor td[TX_BUFFERS];
+   EMAC_TxCallback txCb[TX_BUFFERS];    /// Callback function to be invoked once TD has been processed
+   EMAC_WakeupCallback wakeupCb;        /// Callback function to be invoked once several TD have been released
+   unsigned short wakeupThreshold; /// Number of free TD before wakeupCb is invoked
+   unsigned short head;            /// Circular buffer head pointer incremented by the upper layer (buffer to be sent)
+   unsigned short tail;            /// Circular buffer head pointer incremented by the IT handler (buffer sent)
+} TxTd;
+
+//------------------------------------------------------------------------------
+//         Internal variables
+//------------------------------------------------------------------------------
+// Receive Transfer Descriptor buffer
+#ifdef __ICCARM__          // IAR
+#pragma data_alignment=8   // IAR
+#endif                     // IAR
+static volatile RxTd rxTd;
+// Transmit Transfer Descriptor buffer
+#ifdef __ICCARM__          // IAR
+#pragma data_alignment=8   // IAR
+#endif                     // IAR
+static volatile TxTd txTd;
+/// Send Buffer
+// Section 3.6 of AMBA 2.0 spec states that burst should not cross 1K Boundaries.
+// Receive buffer manager writes are burst of 2 words => 3 lsb bits of the address shall be set to 0
+#ifdef __ICCARM__          // IAR
+#pragma data_alignment=8   // IAR
+#endif                     // IAR
+static volatile unsigned char pTxBuffer[TX_BUFFERS * EMAC_TX_UNITSIZE] __attribute__((aligned(8)));
+
+#ifdef __ICCARM__          // IAR
+#pragma data_alignment=8   // IAR
+#endif                     // IAR
+/// Receive Buffer
+static volatile unsigned char pRxBuffer[RX_BUFFERS * EMAC_RX_UNITSIZE] __attribute__((aligned(8)));
+/// Statistics
+static volatile EmacStats EmacStatistics;
+
+//-----------------------------------------------------------------------------
+//         Internal functions
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+/// Wait PHY operation complete.
+/// Return 1 if the operation completed successfully.
+/// May be need to re-implemented to reduce CPU load.
+/// \param retry: the retry times, 0 to wait forever until complete.
+//-----------------------------------------------------------------------------
+static unsigned char EMAC_WaitPhy( unsigned int retry )
+{
+    unsigned int retry_count = 0;
+
+    while((AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE) == 0) {
+
+        // Dead LOOP!
+        if (retry == 0) {
+
+            continue;
+        }
+
+        // Timeout check
+        retry_count++;
+        if(retry_count >= retry) {
+
+            trace_LOG(trace_ERROR, "E: Wait PHY time out\n\r");
+            return 0;
+        }
+    }
+
+    return 1;
+}
+
+//-----------------------------------------------------------------------------
+//         Exported functions
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+//          PHY management functions
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+/// Set MDC clock according to current board clock. Per 802.3, MDC should be
+/// less then 2.5MHz.
+/// Return 1 if successfully, 0 if MDC clock not found.
+//-----------------------------------------------------------------------------
+unsigned char EMAC_SetMdcClock( unsigned int mck )
+{
+    int clock_dividor;
+
+    if (mck <= 20000000) {
+        clock_dividor = AT91C_EMAC_CLK_HCLK_8;          /// MDC clock = MCK/8
+    }
+    else if (mck <= 40000000) {
+        clock_dividor = AT91C_EMAC_CLK_HCLK_16;         /// MDC clock = MCK/16
+    }
+    else if (mck <= 80000000) {
+        clock_dividor = AT91C_EMAC_CLK_HCLK_32;         /// MDC clock = MCK/32
+    }
+    else if (mck <= 160000000) {
+        clock_dividor = AT91C_EMAC_CLK_HCLK_64;         /// MDC clock = MCK/64
+    }
+    else {
+        trace_LOG(trace_ERROR, "E: No valid MDC clock.\n\r");
+        return 0;
+    }
+    AT91C_BASE_EMAC->EMAC_NCFGR = (AT91C_BASE_EMAC->EMAC_NCFGR & (~AT91C_EMAC_CLK))
+                                 | clock_dividor;
+    return 1;
+}
+
+//-----------------------------------------------------------------------------
+/// Enable MDI with PHY
+//-----------------------------------------------------------------------------
+void EMAC_EnableMdio( void )
+{
+    AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
+}
+
+//-----------------------------------------------------------------------------
+/// Enable MDI with PHY
+//-----------------------------------------------------------------------------
+void EMAC_DisableMdio( void )
+{
+    AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
+}
+
+//-----------------------------------------------------------------------------
+/// Enable MII mode for EMAC, called once after autonegotiate
+//-----------------------------------------------------------------------------
+void EMAC_EnableMII( void )
+{
+    AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN;
+}
+
+//-----------------------------------------------------------------------------
+/// Enable RMII mode for EMAC, called once after autonegotiate
+//-----------------------------------------------------------------------------
+void EMAC_EnableRMII( void )
+{
+    AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN | AT91C_EMAC_RMII;
+}
+
+//-----------------------------------------------------------------------------
+/// Read PHY register.
+/// Return 1 if successfully, 0 if timeout.
+/// \param PhyAddress PHY Address
+/// \param Address Register Address
+/// \param pValue Pointer to a 32 bit location to store read data
+/// \param retry The retry times, 0 to wait forever until complete.
+//-----------------------------------------------------------------------------
+unsigned char EMAC_ReadPhy(unsigned char PhyAddress,
+                           unsigned char Address,
+                           unsigned int *pValue,
+                           unsigned int retry)
+{
+    AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01 << 30))
+                              | (AT91C_EMAC_CODE & (2 << 16))
+                              | (AT91C_EMAC_RW & (2 << 28))
+                              | (AT91C_EMAC_PHYA & ((PhyAddress & 0x1f) << 23))
+                              | (AT91C_EMAC_REGA & (Address << 18));
+
+    if ( EMAC_WaitPhy(retry) == 0 ) {
+
+        trace_LOG(trace_ERROR, "TimeOut EMAC_ReadPhy\n\r");
+        return 0;
+    }
+    *pValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );
+    return 1;
+}
+
+//-----------------------------------------------------------------------------
+/// Write PHY register
+/// Return 1 if successfully, 0 if timeout.
+/// \param PhyAddress PHY Address
+/// \param Address Register Address
+/// \param Value Data to write ( Actually 16 bit data )
+/// \param retry The retry times, 0 to wait forever until complete.
+//-----------------------------------------------------------------------------
+unsigned char EMAC_WritePhy(unsigned char PhyAddress,
+                            unsigned char Address,
+                            unsigned int  Value,
+                            unsigned int  retry)
+{
+    AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01 << 30))
+                              | (AT91C_EMAC_CODE & (2 << 16))
+                              | (AT91C_EMAC_RW & (1 << 28))
+                              | (AT91C_EMAC_PHYA & ((PhyAddress & 0x1f) << 23))
+                              | (AT91C_EMAC_REGA & (Address << 18))
+                              | (AT91C_EMAC_DATA & Value) ;
+    if ( EMAC_WaitPhy(retry) == 0 ) {
+
+        trace_LOG(trace_ERROR, "TimeOut EMAC_WritePhy\n\r");
+        return 0;
+    }
+    return 1;
+}
+
+//-----------------------------------------------------------------------------
+/// Setup the EMAC for the link : speed 100M/10M and Full/Half duplex
+/// \param speed        Link speed, 0 for 10M, 1 for 100M
+/// \param fullduplex   1 for Full Duplex mode
+//-----------------------------------------------------------------------------
+void EMAC_SetLinkSpeed(unsigned char speed, unsigned char fullduplex)
+{
+    unsigned int ncfgr;
+
+    ncfgr = AT91C_BASE_EMAC->EMAC_NCFGR;
+    ncfgr &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
+    if (speed) {
+
+        ncfgr |= AT91C_EMAC_SPD;
+    }
+    if (fullduplex) {
+
+        ncfgr |= AT91C_EMAC_FD;
+    }
+    AT91C_BASE_EMAC->EMAC_NCFGR = ncfgr;
+}
+
+
+
+//-----------------------------------------------------------------------------
+//          EMAC functions
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+/// EMAC Interrupt handler
+//-----------------------------------------------------------------------------
+void EMAC_Handler(void)
+{
+    volatile EmacTxTDescriptor *pTxTd;
+    volatile EMAC_TxCallback   *pTxCb;
+    unsigned int isr;
+    unsigned int rsr;
+    unsigned int tsr;
+    unsigned int rxStatusFlag;
+    unsigned int txStatusFlag;
+
+    //trace_LOG(trace_DEBUG, "EMAC_Handler\n\r");
+    isr = AT91C_BASE_EMAC->EMAC_ISR & AT91C_BASE_EMAC->EMAC_IMR;
+    rsr = AT91C_BASE_EMAC->EMAC_RSR;
+    tsr = AT91C_BASE_EMAC->EMAC_TSR;
+
+    // RX packet
+    if ((isr & AT91C_EMAC_RCOMP) || (rsr & AT91C_EMAC_REC)) {
+        rxStatusFlag = AT91C_EMAC_REC;
+
+        // Frame received
+        EmacStatistics.rx_packets++;
+
+        // Check OVR
+        if (rsr & AT91C_EMAC_OVR) {
+            rxStatusFlag |= AT91C_EMAC_OVR;
+            EmacStatistics.rx_ovrs++;
+        }
+        // Check BNA
+        if (rsr & AT91C_EMAC_BNA) {
+            rxStatusFlag |= AT91C_EMAC_BNA;
+            EmacStatistics.rx_bnas++;
+        }
+        // Clear status
+        AT91C_BASE_EMAC->EMAC_RSR |= rxStatusFlag;
+
+        // Invoke callbacks
+        if (rxTd.rxCb) {
+            rxTd.rxCb(rxStatusFlag);
+        }
+    }
+
+    // TX packet
+    if ((isr & AT91C_EMAC_TCOMP) || (tsr & AT91C_EMAC_COMP)) {
+
+        txStatusFlag = AT91C_EMAC_COMP;
+        EmacStatistics.tx_comp ++;
+
+        // A frame transmitted
+        // Check RLE
+        if (tsr & AT91C_EMAC_RLES) {
+            txStatusFlag |= AT91C_EMAC_RLES;
+            EmacStatistics.tx_errors++;
+        }
+        // Check COL
+        if (tsr & AT91C_EMAC_COL) {
+            txStatusFlag |= AT91C_EMAC_COL;
+            EmacStatistics.collisions++;
+        }
+        // Check BEX
+        if (tsr & AT91C_EMAC_BEX) {
+            txStatusFlag |= AT91C_EMAC_BEX;
+            EmacStatistics.tx_exausts++;
+        }
+        // Check UND
+        if (tsr & AT91C_EMAC_UND) {
+            txStatusFlag |= AT91C_EMAC_UND;
+            EmacStatistics.tx_underruns++;
+        }
+        // Clear status
+        AT91C_BASE_EMAC->EMAC_TSR |= txStatusFlag;
+
+        // Sanity check: Tx buffers have to be scheduled
+        ASSERT(!CIRC_EMPTY(&txTd),
+            "-F- EMAC Tx interrupt received meanwhile no TX buffers has been scheduled\n\r");
+
+        // Check the buffers
+        while (CIRC_CNT(txTd.head, txTd.tail, TX_BUFFERS)) {
+            pTxTd = txTd.td + txTd.tail;
+            pTxCb = txTd.txCb + txTd.tail;
+
+            // Exit if buffer has not been sent yet
+            if ((pTxTd->status & EMAC_TX_USED_BIT) == 0) {
+                break;
+            }
+
+            // Notify upper layer that packet has been sent
+            if (*pTxCb) {
+                (*pTxCb)(txStatusFlag);
+            }
+
+            CIRC_INC( txTd.tail, TX_BUFFERS );
+        }
+
+        // If a wakeup has been scheduled, notify upper layer that it can send
+        // other packets, send will be successfull.
+        if( (CIRC_SPACE(txTd.head, txTd.tail, TX_BUFFERS) >= txTd.wakeupThreshold)
+         &&  txTd.wakeupCb) {
+            txTd.wakeupCb();
+        }
+    }
+}
+
+//-----------------------------------------------------------------------------
+/// Initialize the EMAC with the emac controller address
+/// \param id     HW ID for power management
+/// \param pTxWakeUpfct Thresold TX Wakeup Callback
+/// \param pRxfct       RX Wakeup Callback
+/// \param pMacAddress  Mac Address
+/// \param enableCAF    enable AT91C_EMAC_CAF if needed by application
+/// \param enableNBC    AT91C_EMAC_NBC if needed by application
+//-----------------------------------------------------------------------------
+void EMAC_Init( unsigned char id, const unsigned char *pMacAddress,
+                unsigned char enableCAF, unsigned char enableNBC )
+{
+    int Index;
+    unsigned int Address;
+
+    // Check parameters
+    ASSERT(RX_BUFFERS * EMAC_RX_UNITSIZE > EMAC_FRAME_LENTGH_MAX,
+           "E: RX buffers too small\n\r");
+
+    trace_LOG(trace_DEBUG, "EMAC_Init\n\r");
+
+    // Power ON
+    AT91C_BASE_PMC->PMC_PCER = 1 << id;
+
+    // Disable TX & RX and more
+    AT91C_BASE_EMAC->EMAC_NCR = 0;
+
+    // disable
+    AT91C_BASE_EMAC->EMAC_IDR = ~0;
+
+    rxTd.idx = 0;
+    CIRC_CLEAR(&txTd);
+
+    // Setup the RX descriptors.
+    for(Index = 0; Index < RX_BUFFERS; Index++) {
+
+        Address = (unsigned int)(&(pRxBuffer[Index * EMAC_RX_UNITSIZE]));
+        // Remove EMAC_RX_OWNERSHIP_BIT and EMAC_RX_WRAP_BIT
+        rxTd.td[Index].addr = Address & EMAC_ADDRESS_MASK;
+        rxTd.td[Index].status = 0;
+    }
+    rxTd.td[RX_BUFFERS - 1].addr |= EMAC_RX_WRAP_BIT;
+
+    // Setup the TX descriptors.
+    for(Index = 0; Index < TX_BUFFERS; Index++) {
+
+        Address = (unsigned int)(&(pTxBuffer[Index * EMAC_TX_UNITSIZE]));
+        txTd.td[Index].addr = Address;
+        txTd.td[Index].status = EMAC_TX_USED_BIT;
+    }
+    txTd.td[TX_BUFFERS - 1].status = EMAC_TX_USED_BIT | EMAC_TX_WRAP_BIT;
+
+    // Set the MAC address
+    if( pMacAddress != (unsigned char *)0 ) {
+        AT91C_BASE_EMAC->EMAC_SA1L = ( ((unsigned int)pMacAddress[3] << 24)
+                                     | ((unsigned int)pMacAddress[2] << 16)
+                                     | ((unsigned int)pMacAddress[1] << 8 )
+                                     |                pMacAddress[0] );
+
+        AT91C_BASE_EMAC->EMAC_SA1H = ( ((unsigned int)pMacAddress[5] << 8 )
+                                     |                pMacAddress[4] );
+    }
+    // Now setup the descriptors
+    // Receive Buffer Queue Pointer Register
+    AT91C_BASE_EMAC->EMAC_RBQP = (unsigned int) (rxTd.td);
+    // Transmit Buffer Queue Pointer Register
+    AT91C_BASE_EMAC->EMAC_TBQP = (unsigned int) (txTd.td);
+
+    AT91C_BASE_EMAC->EMAC_NCR = AT91C_EMAC_CLRSTAT;
+
+    // Clear all status bits in the receive status register.
+    AT91C_BASE_EMAC->EMAC_RSR = (AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
+
+    // Clear all status bits in the transmit status register
+    AT91C_BASE_EMAC->EMAC_TSR = ( AT91C_EMAC_UBR | AT91C_EMAC_COL | AT91C_EMAC_RLES
+                                | AT91C_EMAC_BEX | AT91C_EMAC_COMP
+                                | AT91C_EMAC_UND );
+
+    // Clear interrupts
+    AT91C_BASE_EMAC->EMAC_ISR;
+
+    // Enable the copy of data into the buffers
+    // ignore broadcasts, and don't copy FCS.
+    AT91C_BASE_EMAC->EMAC_NCFGR |= (AT91C_EMAC_DRFCS | AT91C_EMAC_PAE);
+
+    if( enableCAF == EMAC_CAF_ENABLE ) {
+        AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_CAF;
+    }
+    if( enableNBC == EMAC_NBC_ENABLE ) {
+        AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_NBC;
+    }
+
+    // Enable Rx and Tx, plus the stats register.
+    AT91C_BASE_EMAC->EMAC_NCR |= (AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT);
+
+    // Setup the interrupts for TX (and errors)
+    AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RXUBR
+                              | AT91C_EMAC_TUNDR
+                              | AT91C_EMAC_RLEX
+                              | AT91C_EMAC_TXERR
+                              | AT91C_EMAC_TCOMP
+                              | AT91C_EMAC_ROVR
+                              | AT91C_EMAC_HRESP;
+
+}
+
+//-----------------------------------------------------------------------------
+/// Get the statstic information & reset it
+/// \param pStats   Pointer to EmacStats structure to copy the informations
+/// \param reset    Reset the statistics after copy it
+//-----------------------------------------------------------------------------
+void EMAC_GetStatistics(EmacStats *pStats, unsigned char reset)
+{
+    unsigned int ncrBackup = 0;
+
+    trace_LOG(trace_DEBUG, "EMAC_GetStatistics\n\r");
+
+    // Sanity check
+    if (pStats == (EmacStats *) 0) {
+        return;
+    }
+
+    ncrBackup = AT91C_BASE_EMAC->EMAC_NCR & (AT91C_EMAC_TE | AT91C_EMAC_RE);
+
+    // Disable TX/RX
+    AT91C_BASE_EMAC->EMAC_NCR = ncrBackup & ~(AT91C_EMAC_TE | AT91C_EMAC_RE);
+
+    // Copy the informations
+    memcpy(pStats, (void*)&EmacStatistics, sizeof(EmacStats));
+
+    // Reset the statistics
+    if (reset) {
+        memset((void*)&EmacStatistics, 0x00, sizeof(EmacStats));
+        AT91C_BASE_EMAC->EMAC_NCR = ncrBackup | AT91C_EMAC_CLRSTAT;
+    }
+
+    // restore NCR
+    AT91C_BASE_EMAC->EMAC_NCR = ncrBackup;
+}
+
+//-----------------------------------------------------------------------------
+/// Send a packet with EMAC.
+/// If the packet size is larger than transfer buffer size error returned.
+/// \param buffer   The buffer to be send
+/// \param size     The size of buffer to be send
+/// \param fEMAC_TxCallback Threshold Wakeup callback
+/// \param fWakeUpCb   TX Wakeup
+/// \return         OK, Busy or invalid packet
+//-----------------------------------------------------------------------------
+unsigned char EMAC_Send(void *pBuffer,
+                        unsigned int size,
+                        EMAC_TxCallback fEMAC_TxCallback)
+{
+    volatile EmacTxTDescriptor *pTxTd;
+    volatile EMAC_TxCallback   *pTxCb;
+
+    //trace_LOG(trace_DEBUG, "EMAC_Send\n\r");
+
+    // Check parameter
+    if (size > EMAC_TX_UNITSIZE) {
+
+        trace_LOG(trace_ERROR, "-E- EMAC driver does not split send packets.");
+        trace_LOG(trace_ERROR, " It can send %d bytes max in one packet (%u bytes requested)\n\r",
+            EMAC_TX_UNITSIZE, size);
+        return EMAC_TX_INVALID_PACKET;
+    }
+
+    // If no free TxTd, buffer can't be sent, schedule the wakeup callback
+    if( CIRC_SPACE(txTd.head, txTd.tail, TX_BUFFERS) == 0) {
+        return EMAC_TX_BUFFER_BUSY;
+
+    }
+
+    // Pointers to the current TxTd
+    pTxTd = txTd.td + txTd.head;
+    pTxCb = txTd.txCb + txTd.head;
+
+    // Sanity check
+    ASSERT((pTxTd->status & EMAC_TX_USED_BIT) != 0,
+        "-F- Buffer is still under EMAC control\n\r");
+
+    // Setup/Copy data to transmition buffer
+    if (pBuffer && size) {
+        // Driver manage the ring buffer
+        memcpy((void *)pTxTd->addr, pBuffer, size);
+    }
+
+    // Tx Callback
+    *pTxCb = fEMAC_TxCallback;
+
+    // Update TD status
+    // The buffer size defined is length of ethernet frame
+    // so it's always the last buffer of the frame.
+    if (txTd.head == TX_BUFFERS-1) {
+        pTxTd->status =
+            (size & EMAC_LENGTH_FRAME) | EMAC_TX_LAST_BUFFER_BIT | EMAC_TX_WRAP_BIT;
+    }
+    else {
+        pTxTd->status = (size & EMAC_LENGTH_FRAME) | EMAC_TX_LAST_BUFFER_BIT;
+    }
+
+    CIRC_INC(txTd.head, TX_BUFFERS)
+
+    // Tx packets count
+    EmacStatistics.tx_packets++;
+
+    // Now start to transmit if it is not already done
+    AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
+
+    return EMAC_TX_OK;
+}
+
+//-----------------------------------------------------------------------------
+/// Receive a packet with EMAC
+/// If not enough buffer for the packet, the remaining data is lost but right
+/// frame length is returned.
+/// \param pFrame           Buffer to store the frame
+/// \param frameSize        Size of the frame
+/// \param pRcvSize         Received size
+/// \return                 OK, no data, or frame too small
+//-----------------------------------------------------------------------------
+unsigned char EMAC_Poll(unsigned char *pFrame,
+                        unsigned int frameSize,
+                        unsigned int *pRcvSize)
+{
+    unsigned short bufferLength;
+    unsigned int   tmpFrameSize=0;
+    unsigned char  *pTmpFrame=0;
+    unsigned int   tmpIdx = rxTd.idx;
+    volatile EmacRxTDescriptor *pRxTd = rxTd.td + rxTd.idx;
+
+    ASSERT(pFrame, "F: EMAC_Poll\n\r");
+
+    char isFrame = 0;
+    // Set the default return value
+    *pRcvSize = 0;
+
+    // Process received RxTd
+    while ((pRxTd->addr & EMAC_RX_OWNERSHIP_BIT) == EMAC_RX_OWNERSHIP_BIT) {
+
+        // A start of frame has been received, discard previous fragments
+        if ((pRxTd->status & EMAC_RX_SOF_BIT) == EMAC_RX_SOF_BIT) {
+            // Skip previous fragment
+            while (tmpIdx != rxTd.idx) {
+                pRxTd = rxTd.td + rxTd.idx;
+                pRxTd->addr &= ~(EMAC_RX_OWNERSHIP_BIT);
+                CIRC_INC(rxTd.idx, RX_BUFFERS);
+            }
+            // Reset the temporary frame pointer
+            pTmpFrame = pFrame;
+            tmpFrameSize = 0;
+            // Start to gather buffers in a frame
+            isFrame = 1;
+        }
+
+        // Increment the pointer
+        CIRC_INC(tmpIdx, RX_BUFFERS);
+
+        // Copy data in the frame buffer
+        if (isFrame) {
+            if (tmpIdx == rxTd.idx) {
+                trace_LOG(trace_INFO,
+                    "I: no EOF (Invalid of buffers too small)\n\r");
+
+                do {
+
+                    pRxTd = rxTd.td + rxTd.idx;
+                    pRxTd->addr &= ~(EMAC_RX_OWNERSHIP_BIT);
+                    CIRC_INC(rxTd.idx, RX_BUFFERS);
+                } while(tmpIdx != rxTd.idx);
+                return EMAC_RX_NO_DATA;
+            }
+            // Copy the buffer into the application frame
+            bufferLength = EMAC_RX_UNITSIZE;
+            if ((tmpFrameSize + bufferLength) > frameSize) {
+                bufferLength = frameSize - tmpFrameSize;
+            }
+
+            memcpy(pTmpFrame, (void*)(pRxTd->addr & EMAC_ADDRESS_MASK), bufferLength);
+            pTmpFrame += bufferLength;
+            tmpFrameSize += bufferLength;
+
+            // An end of frame has been received, return the data
+            if ((pRxTd->status & EMAC_RX_EOF_BIT) == EMAC_RX_EOF_BIT) {
+                // Frame size from the EMAC
+                *pRcvSize = (pRxTd->status & EMAC_LENGTH_FRAME);
+
+                // Application frame buffer is too small all data have not been copied
+                if (tmpFrameSize < *pRcvSize) {
+                    printf("size req %u size allocated %u\n\r", *pRcvSize, frameSize);
+
+                    return EMAC_RX_FRAME_SIZE_TOO_SMALL;
+                }
+
+                trace_LOG(trace_INFO, "packet %d-%u (%u)\n\r", rxTd.idx, tmpIdx, *pRcvSize);
+                // All data have been copied in the application frame buffer => release TD
+                while (rxTd.idx != tmpIdx) {
+                    pRxTd = rxTd.td + rxTd.idx;
+                    pRxTd->addr &= ~(EMAC_RX_OWNERSHIP_BIT);
+                    CIRC_INC(rxTd.idx, RX_BUFFERS);
+                }
+                EmacStatistics.rx_packets++;
+                return EMAC_RX_OK;
+            }
+        }
+
+        // SOF has not been detected, skip the fragment
+        else {
+           pRxTd->addr &= ~(EMAC_RX_OWNERSHIP_BIT);
+           rxTd.idx = tmpIdx;
+        }
+
+        // Process the next buffer
+        pRxTd = rxTd.td + tmpIdx;
+    }
+
+    //trace_LOG(trace_DEBUG, "E");
+    return EMAC_RX_NO_DATA;
+}
+
+//-----------------------------------------------------------------------------
+/// Registers pRxCb callback. Callback will be invoked after the next received
+/// frame.
+/// When EMAC_Poll() returns EMAC_RX_NO_DATA the application task call EMAC_Set_RxCb()
+/// to register pRxCb() callback and enters suspend state. The callback is in charge
+/// to resume the task once a new frame has been received. The next time EMAC_Poll()
+/// is called, it will be successfull.
+/// \param pRxCb            Pointer to callback function
+//-----------------------------------------------------------------------------
+void EMAC_Set_RxCb(EMAC_RxCallback pRxCb)
+{
+    rxTd.rxCb = pRxCb;
+    AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP;
+}
+
+//-----------------------------------------------------------------------------
+/// Remove the RX callback function.
+/// This function is usually invoked from the RX callback itself. Once the callback
+/// has resumed the application task, there is no need to invoke the callback again.
+//-----------------------------------------------------------------------------
+void EMAC_Clear_RxCb(void)
+{
+    AT91C_BASE_EMAC->EMAC_IDR = AT91C_EMAC_RCOMP;
+    rxTd.rxCb = (EMAC_RxCallback) 0;
+}
+
+//-----------------------------------------------------------------------------
+/// Registers TX wakeup callback callback. Callback will be invoked once several
+/// transfer descriptors are available.
+/// When EMAC_Send() returns EMAC_TX_BUFFER_BUSY (all TD busy) the application
+/// task calls EMAC_Set_TxWakeUpCb() to register pTxWakeUpCb() callback and
+/// enters suspend state. The callback is in charge to resume the task once
+/// several TD have been released. The next time EMAC_Send() will be called, it
+/// shall be successfull.
+/// \param pTxWakeUpCb   Pointer to callback function
+/// \param threshold     Minimum number of available transfer descriptors before pTxWakeUpCb() is invoked
+/// \return              0= success, 1 = threshold exceeds nuber of transfer descriptors
+//-----------------------------------------------------------------------------
+char EMAC_Set_TxWakeUpCb(EMAC_WakeupCallback pTxWakeUpCb, unsigned short threshold)
+{
+    if (threshold <= TX_BUFFERS) {
+        txTd.wakeupCb = pTxWakeUpCb;
+        txTd.wakeupThreshold = threshold;
+        return 0;
+    }
+    return 1;
+}
+
+//-----------------------------------------------------------------------------
+/// Remove the TX wakeup callback function.
+/// This function is usually invoked from the TX wakeup callback itself. Once the callback
+/// has resumed the application task, there is no need to invoke the callback again.
+//-----------------------------------------------------------------------------
+void EMAC_Clear_TxWakeUpCb(void)
+{
+    txTd.wakeupCb = (EMAC_WakeupCallback) 0;
+}
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/emac/emac.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/emac/emac.h
new file mode 100644
index 0000000..992c908
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/emac/emac.h
@@ -0,0 +1,161 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+// peripherals/emac/emac.h
+
+#ifndef EMAC_H
+#define EMAC_H
+
+//-----------------------------------------------------------------------------
+/// \dir
+/// !Purpose
+///
+///     Definition of methods and structures for using EMAC
+///     
+/// !Usage
+///
+/// -# Initialize EMAC with EMAC_Init.
+/// -# Setup EMAC with EMAC_SetupTx, EMAC_SetupRx, EMAC_SetupMacAddress
+///    and EMAC_SetupStack. 
+/// -# Drive the EMAC status machine by EMAC_Task.
+/// -# EMAC_GetStatus give EMAC status machine current status 
+/// -# Send a packet to network with EMAC_SendPacket.
+/// -# Get a packet from network with EMAC_GetPacket.
+///
+//-----------------------------------------------------------------------------
+
+
+//-----------------------------------------------------------------------------
+//         Headers
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+//         Definitions
+//-----------------------------------------------------------------------------
+/// Number of buffer for RX, be carreful: MUST be 2^n
+#define RX_BUFFERS  16
+/// Number of buffer for TX, be carreful: MUST be 2^n
+#define TX_BUFFERS   8
+
+/// Buffer Size
+#define EMAC_RX_UNITSIZE            128     /// Fixed size for RX buffer
+#define EMAC_TX_UNITSIZE            1518    /// Size for ETH frame length
+
+// The MAC can support frame lengths up to 1536 bytes.
+#define EMAC_FRAME_LENTGH_MAX       1536
+
+
+//-----------------------------------------------------------------------------
+//         Types
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+/// Describes the statistics of the EMAC.
+//-----------------------------------------------------------------------------
+typedef struct _EmacStats {
+
+    // TX errors
+    unsigned int tx_packets;    /// Total Number of packets sent
+    unsigned int tx_comp;       /// Packet complete
+    unsigned int tx_errors;     /// TX errors ( Retry Limit Exceed )
+    unsigned int collisions;    /// Collision
+    unsigned int tx_exausts;    /// Buffer exhausted
+    unsigned int tx_underruns;  /// Under Run, not able to read from memory
+    // RX errors
+    unsigned int rx_packets;    /// Total Number of packets RX
+    unsigned int rx_eof;        /// No EOF error
+    unsigned int rx_ovrs;       /// Over Run, not able to store to memory
+    unsigned int rx_bnas;       /// Buffer is not available
+
+} EmacStats, *PEmacStats;
+
+//-----------------------------------------------------------------------------
+//         PHY Exported functions
+//-----------------------------------------------------------------------------
+extern unsigned char EMAC_SetMdcClock( unsigned int mck );
+
+extern void EMAC_EnableMdio( void );
+
+extern void EMAC_DisableMdio( void );
+
+extern void EMAC_EnableMII( void );
+
+extern void EMAC_EnableRMII( void );
+
+extern unsigned char EMAC_ReadPhy(unsigned char PhyAddress,
+                                  unsigned char Address,
+                                  unsigned int *pValue,
+                                  unsigned int retry);
+
+extern unsigned char EMAC_WritePhy(unsigned char PhyAddress,
+                                   unsigned char Address,
+                                   unsigned int Value,
+                                   unsigned int retry);
+
+extern void EMAC_SetLinkSpeed(unsigned char speed,
+                              unsigned char fullduplex);
+
+//-----------------------------------------------------------------------------
+//         EMAC Exported functions
+//-----------------------------------------------------------------------------
+/// Callback used by send function
+typedef void (*EMAC_TxCallback)(unsigned int status);
+typedef void (*EMAC_RxCallback)(unsigned int status);
+typedef void (*EMAC_WakeupCallback)(void);
+
+extern void EMAC_Init( unsigned char id, const unsigned char *pMacAddress,
+                unsigned char enableCAF, unsigned char enableNBC );
+#define EMAC_CAF_DISABLE  0
+#define EMAC_CAF_ENABLE   1
+#define EMAC_NBC_DISABLE  0
+#define EMAC_NBC_ENABLE   1
+
+extern void EMAC_Handler(void);
+
+extern unsigned char EMAC_Send(void *pBuffer, 
+                               unsigned int size, 
+                               EMAC_TxCallback fEMAC_TxCallback);
+/// Return for EMAC_Send function
+#define EMAC_TX_OK                     0
+#define EMAC_TX_BUFFER_BUSY            1
+#define EMAC_TX_INVALID_PACKET         2
+
+
+extern unsigned char EMAC_Poll(unsigned char *pFrame,
+                               unsigned int frameSize,
+                               unsigned int *pRcvSize);
+/// Return for EMAC_Poll function
+#define EMAC_RX_OK                   0
+#define EMAC_RX_NO_DATA              1
+#define EMAC_RX_FRAME_SIZE_TOO_SMALL 2
+
+extern void EMAC_GetStatistics(EmacStats *pStats, unsigned char reset);
+
+#endif // #ifndef EMAC_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/lcd/lcd.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/lcd/lcd.c
new file mode 100644
index 0000000..b5a8d69
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/lcd/lcd.c
@@ -0,0 +1,362 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "lcd.h"
+#include 
+#include 
+
+//------------------------------------------------------------------------------
+//         Exported functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Enables the LCD controller, after waiting for the specified number of
+/// frames.
+/// \param frames  Number of frames before the LCD is enabled.
+//------------------------------------------------------------------------------
+void LCD_Enable(unsigned int frames)
+{
+    ASSERT((frames & 0xFFFFFF80) == 0,
+           "LCD_Enable: Wrong frames value.\n\r");
+    AT91C_BASE_LCDC->LCDC_PWRCON = AT91C_LCDC_PWR | (frames << 1);
+}
+
+//------------------------------------------------------------------------------
+/// Disables the LCD controller, after waiting for the specified number of
+/// frames.
+/// \param frames  Number of frames before the LCD is shut down.
+//------------------------------------------------------------------------------
+void LCD_Disable(unsigned int frames)
+{
+    ASSERT((frames & 0xFFFFFF80) == 0,
+           "LCD_Disable: Wrong frames value.\n\r");
+    AT91C_BASE_LCDC->LCDC_PWRCON = frames << 1;
+}
+
+//------------------------------------------------------------------------------
+/// Enables the DMA of the LCD controller.
+//------------------------------------------------------------------------------
+void LCD_EnableDma()
+{
+    AT91C_BASE_LCDC->LCDC_DMACON = AT91C_LCDC_DMAEN;
+}
+
+//------------------------------------------------------------------------------
+/// Disables the DMA of the LCD controller.
+//------------------------------------------------------------------------------
+void LCD_DisableDma()
+{
+    AT91C_BASE_LCDC->LCDC_DMACON = 0;
+}
+
+//------------------------------------------------------------------------------
+/// Configures the internal clock of the LCD controller given the master clock of
+/// the system and the desired pixel clock in MHz.
+/// \param masterClock  Master clock frequency.
+/// \param pixelClock  Pixel clock frequency.
+//------------------------------------------------------------------------------
+void LCD_SetPixelClock(unsigned int masterClock, unsigned int pixelClock)
+{
+    AT91C_BASE_LCDC->LCDC_LCDCON1 = ((masterClock / (2 * pixelClock)) - 1) << 12;
+}
+
+//------------------------------------------------------------------------------
+/// Sets the type of display used with the LCD controller.
+/// \param displayType  Type of display used.
+//------------------------------------------------------------------------------
+void LCD_SetDisplayType(unsigned int displayType)
+{
+    unsigned int value;
+
+    ASSERT((displayType & ~AT91C_LCDC_DISTYPE) == 0,
+           "LCD_SetDisplayType: Wrong display type value.\n\r");
+
+    value = AT91C_BASE_LCDC->LCDC_LCDCON2;
+    value &= ~AT91C_LCDC_DISTYPE;
+    value |= displayType;
+    AT91C_BASE_LCDC->LCDC_LCDCON2 = value;
+}
+
+//------------------------------------------------------------------------------
+/// Sets the scan mode used by the LCD (either single scan or double-scan).
+/// \param scanMode  Scan mode to use.
+//------------------------------------------------------------------------------
+void LCD_SetScanMode(unsigned int scanMode)
+{
+    unsigned int value;
+
+    ASSERT((scanMode & ~AT91C_LCDC_SCANMOD) == 0,
+           "LCD_SetScanMode: Wrong scan mode value.\n\r");
+
+    value = AT91C_BASE_LCDC->LCDC_LCDCON2;
+    value &= ~AT91C_LCDC_SCANMOD;
+    value |= scanMode;
+    AT91C_BASE_LCDC->LCDC_LCDCON2 = value;
+}
+
+//------------------------------------------------------------------------------
+/// Sets the number of bits per pixel used by the LCD display.
+/// \param bitsPerPixel  Number of bits per pixel to use.
+//------------------------------------------------------------------------------
+void LCD_SetBitsPerPixel(unsigned int bitsPerPixel)
+{
+    unsigned int value;
+
+    ASSERT((bitsPerPixel & ~AT91C_LCDC_PIXELSIZE) == 0,
+           "LCD_SetScanMode: Wrong bitsPerPixel value.\n\r");
+
+    value = AT91C_BASE_LCDC->LCDC_LCDCON2;
+    value &= ~AT91C_LCDC_PIXELSIZE;
+    value |= bitsPerPixel;
+    AT91C_BASE_LCDC->LCDC_LCDCON2 = value;
+}
+
+//------------------------------------------------------------------------------
+/// Sets the LCDD, LCDVSYNC, LCDHSYNC, LCDDOTCLK and LCDDEN signal polarities.
+/// \param lcdd  LCDD signal polarity.
+/// \param lcdvsync  LCDVSYNC signal polarity.
+/// \param lcdhsync  LCDHSYNC signal polarity.
+/// \param lcddotclk  LCDDOTCLK signal polarity.
+/// \param lcdden  LCDDEN signal polarity.
+//------------------------------------------------------------------------------
+void LCD_SetPolarities(
+    unsigned int lcdd,
+    unsigned int lcdvsync,
+    unsigned int lcdhsync,
+    unsigned int lcddotclk,
+    unsigned int lcdden)
+{
+    unsigned int value;
+
+    ASSERT((lcdd & ~AT91C_LCDC_INVVD) == 0,
+           "LCD_SetPolarities: Wrong lcdd value.\n\r");
+    ASSERT((lcdvsync & ~AT91C_LCDC_INVFRAME) == 0,
+           "LCD_SetPolarities: Wrong lcdvsync value.\n\r");
+    ASSERT((lcdhsync & ~AT91C_LCDC_INVLINE) == 0,
+           "LCD_SetPolarities: Wrong lcdhsync value.\n\r");
+    ASSERT((lcddotclk & ~AT91C_LCDC_INVCLK) == 0,
+           "LCD_SetPolarities: Wrong lcddotclk value.\n\r");
+    ASSERT((lcdden & ~AT91C_LCDC_INVDVAL) == 0,
+           "LCD_SetPolarities: Wrong lcdden value.\n\r");
+
+    value = AT91C_BASE_LCDC->LCDC_LCDCON2;
+    value &= 0xFFFFE0FF;
+    value |= lcdd | lcdvsync | lcdhsync | lcddotclk | lcdden;
+    AT91C_BASE_LCDC->LCDC_LCDCON2 = value;
+}
+
+//------------------------------------------------------------------------------
+/// Sets the LCD clock mode, i.e. always active or active only during display
+/// period.
+/// \param clockMode  Clock mode to use.
+//------------------------------------------------------------------------------
+void LCD_SetClockMode(unsigned int clockMode)
+{
+    unsigned int value;
+
+    ASSERT((clockMode & ~AT91C_LCDC_CLKMOD) == 0,
+           "LCD_SetScanMode: Wrong scan mode value.\n\r");
+
+    value = AT91C_BASE_LCDC->LCDC_LCDCON2;
+    value &= ~AT91C_LCDC_CLKMOD;
+    value |= clockMode;
+    AT91C_BASE_LCDC->LCDC_LCDCON2 = value;
+}
+
+//------------------------------------------------------------------------------
+/// Sets the format of the frame buffer memory.
+/// \param format  Memory ordering format.
+//------------------------------------------------------------------------------
+void LCD_SetMemoryFormat(unsigned int format)
+{
+    unsigned int value;
+
+    ASSERT((format & ~AT91C_LCDC_MEMOR) == 0,
+           "LCD_SetMemoryFormat: Wrong memory format value.\n\r");
+
+    value = AT91C_BASE_LCDC->LCDC_LCDCON2;
+    value &= ~AT91C_LCDC_MEMOR;
+    value |= format;
+    AT91C_BASE_LCDC->LCDC_LCDCON2 = value;
+}
+
+//------------------------------------------------------------------------------
+/// Sets the size in pixel of the LCD display.
+/// \param width  Width in pixel of the LCD display.
+/// \param height  Height in pixel of the LCD display.
+//------------------------------------------------------------------------------
+void LCD_SetSize(unsigned int width, unsigned int height)
+{
+    ASSERT(((width - 1) & 0xFFFFF800) == 0,
+           "LCD_SetSize: Wrong width value.\n\r");
+    ASSERT(((height - 1) & 0xFFFFF800) == 0,
+           "LCD_SetSize: Wrong height value.\n\r");
+
+    AT91C_BASE_LCDC->LCDC_LCDFRCFG = ((width - 1) << 21) | (height - 1);
+}
+
+//------------------------------------------------------------------------------
+/// Sets the vertical timings of the LCD controller. Only meaningful when
+/// using a TFT display.
+/// \param vfp  Number of idle lines at the end of a frame.
+/// \param vbp  Number of idle lines at the beginning of a frame.
+/// \param vpw  Vertical synchronization pulse width in number of lines.
+/// \param vhdly  Delay between LCDVSYNC edge and LCDHSYNC rising edge, in
+///               LCDDOTCLK cycles.
+//------------------------------------------------------------------------------
+void LCD_SetVerticalTimings(
+    unsigned int vfp,
+    unsigned int vbp,
+    unsigned int vpw,
+    unsigned int vhdly)
+{
+    ASSERT((vfp & 0xFFFFFF00) == 0,
+           "LCD_SetVerticalTimings: Wrong vfp value.\n\r");
+    ASSERT((vbp & 0xFFFFFF00) == 0,
+           "LCD_SetVerticalTimings: Wrong vbp value.\n\r");
+    ASSERT(((vpw-1) & 0xFFFFFFC0) == 0,
+           "LCD_SetVerticalTimings: Wrong vpw value.\n\r");
+    ASSERT(((vhdly-1) & 0xFFFFFFF0) == 0,
+           "LCD_SetVerticalTimings: Wrong vhdly value.\n\r");
+
+    AT91C_BASE_LCDC->LCDC_TIM1 = vfp
+                                 | (vbp << 8)
+                                 | ((vpw-1) << 16)
+                                 | ((vhdly-1) << 24);
+}
+
+//------------------------------------------------------------------------------
+/// Sets the horizontal timings of the LCD controller. Meaningful for both
+/// STN and TFT displays.
+/// \param hbp  Number of idle LCDDOTCLK cycles at the beginning of a line.
+/// \param hpw  Width of the LCDHSYNC pulse, in LCDDOTCLK cycles.
+/// \param hfp  Number of idel LCDDOTCLK cycles at the end of a line.
+//------------------------------------------------------------------------------
+void LCD_SetHorizontalTimings(
+    unsigned int hbp,
+    unsigned int hpw,
+    unsigned int hfp)
+{
+    ASSERT(((hbp-1) & 0xFFFFFF00) == 0,
+           "LCD_SetHorizontalTimings: Wrong hbp value.\n\r");
+    ASSERT(((hpw-1) & 0xFFFFFFC0) == 0,
+           "LCD_SetHorizontalTimings: Wrong hpw value.\n\r");
+    ASSERT(((hfp-1) & 0xFFFFFF00) == 0,
+           "LCD_SetHorizontalTimings: Wrong hfp value.\n\r");
+
+    AT91C_BASE_LCDC->LCDC_TIM2 = (hbp-1) | ((hpw-1) << 8) | ((hfp-1) << 24);
+}
+
+//------------------------------------------------------------------------------
+/// Sets the address of the frame buffer in the LCD controller DMA. When using
+/// dual-scan mode, this is the upper frame buffer.
+/// \param address  Frame buffer address.
+//------------------------------------------------------------------------------
+void LCD_SetFrameBufferAddress(void *address)
+{
+    AT91C_BASE_LCDC->LCDC_BA1 = (unsigned int) address;
+}
+
+//------------------------------------------------------------------------------
+/// Sets the size in pixels of a frame (height * width * bpp).
+/// \param frameSize  Size of frame in pixels.
+//------------------------------------------------------------------------------
+void LCD_SetFrameSize(unsigned int frameSize)
+{
+    ASSERT((frameSize & 0xFF800000) == 0,
+           "LCD_SetFrameSize: Wrong frameSize value.\n\r");
+
+    AT91C_BASE_LCDC->LCDC_FRMCFG = frameSize | (AT91C_BASE_LCDC->LCDC_FRMCFG & 0xFF000000);
+}
+
+//------------------------------------------------------------------------------
+/// Sets the DMA controller burst length.
+/// \param burstLength  Desired burst length.
+//------------------------------------------------------------------------------
+void LCD_SetBurstLength(unsigned int burstLength)
+{
+    ASSERT(((burstLength-1) & 0xFFFFFF80) == 0,
+           "LCD_SetBurstLength: Wrong burstLength value.\n\r");
+
+    AT91C_BASE_LCDC->LCDC_FRMCFG &= 0x00FFFFFF;
+    AT91C_BASE_LCDC->LCDC_FRMCFG |= ((burstLength-1) << 24);
+
+    AT91C_BASE_LCDC->LCDC_FIFO = 2048 - (2 * burstLength + 3);
+}
+
+//------------------------------------------------------------------------------
+/// Sets the prescaler value of the contrast control PWM.
+/// \param prescaler  Desired prescaler value.
+//------------------------------------------------------------------------------
+void LCD_SetContrastPrescaler(unsigned int prescaler)
+{
+    ASSERT((prescaler & ~AT91C_LCDC_PS) == 0,
+           "LCD_SetContrastPrescaler: Wrong prescaler value\n\r");
+
+    AT91C_BASE_LCDC->LCDC_CTRSTCON &= ~AT91C_LCDC_PS;
+    AT91C_BASE_LCDC->LCDC_CTRSTCON |= prescaler;
+}
+
+//------------------------------------------------------------------------------
+/// Sets the polarity of the contrast PWM.
+/// \param polarity  PWM polarity
+//------------------------------------------------------------------------------
+void LCD_SetContrastPolarity(unsigned int polarity)
+{
+    ASSERT((polarity & ~AT91C_LCDC_POL) == 0,
+           "LCD_SetContrastPolarity: Wrong polarity value\n\r");
+
+    AT91C_BASE_LCDC->LCDC_CTRSTCON &= ~AT91C_LCDC_POL;
+    AT91C_BASE_LCDC->LCDC_CTRSTCON |= polarity;
+}
+
+//------------------------------------------------------------------------------
+/// Sets the threshold value of the constrast PWM.
+/// \param value  PWM threshold value.
+//------------------------------------------------------------------------------
+void LCD_SetContrastValue(unsigned int value)
+{
+    ASSERT((value & ~AT91C_LCDC_CVAL) == 0,
+           "LCD_SetContrastValue: Wrong value.\n\r");
+
+    AT91C_BASE_LCDC->LCDC_CTRSTVAL = value;
+}
+
+//------------------------------------------------------------------------------
+/// Enables the contrast PWM generator.
+//------------------------------------------------------------------------------
+void LCD_EnableContrast()
+{
+    AT91C_BASE_LCDC->LCDC_CTRSTCON |= AT91C_LCDC_ENA_PWMGEMENABLED;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/lcd/lcd.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/lcd/lcd.h
new file mode 100644
index 0000000..35d6be0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/lcd/lcd.h
@@ -0,0 +1,92 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef LCD_H
+#define LCD_H
+
+//------------------------------------------------------------------------------
+//         Exported functions
+//------------------------------------------------------------------------------
+
+extern void LCD_Enable(unsigned int frames);
+
+extern void LCD_Disable(unsigned int frames);
+
+extern void LCD_EnableDma();
+
+extern void LCD_DisableDma();
+
+extern void LCD_SetPixelClock(unsigned int masterClock, unsigned int pixelClock);
+
+extern void LCD_SetDisplayType(unsigned int displayType);
+
+extern void LCD_SetScanMode(unsigned int scanMode);
+
+extern void LCD_SetBitsPerPixel(unsigned int bitsPerPixel);
+
+extern void LCD_SetPolarities(
+    unsigned int lcdd,
+    unsigned int lcdvsync,
+    unsigned int lcdhsync,
+    unsigned int lcddotclk,
+    unsigned int lcdden);
+
+extern void LCD_SetClockMode(unsigned int clockMode);
+
+extern void LCD_SetMemoryFormat(unsigned int format);
+
+extern void LCD_SetSize(unsigned int width, unsigned int height);
+
+extern void LCD_SetVerticalTimings(
+    unsigned int vfp,
+    unsigned int vbp,
+    unsigned int vpw,
+    unsigned int vhdly);
+
+extern void LCD_SetHorizontalTimings(
+    unsigned int hbp,
+    unsigned int hpw,
+    unsigned int hfp);
+
+extern void LCD_SetFrameBufferAddress(void *address);
+
+extern void LCD_SetFrameSize(unsigned int frameSize);
+
+extern void LCD_SetBurstLength(unsigned int burstLength);
+
+extern void LCD_SetContrastPrescaler(unsigned int prescaler);
+
+extern void LCD_SetContrastPolarity(unsigned int polarity);
+
+extern void LCD_SetContrastValue(unsigned int value);
+
+extern void LCD_EnableContrast();
+
+#endif //#ifndef LCD_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/mci/mci.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/mci/mci.c
new file mode 100644
index 0000000..a442a51
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/mci/mci.c
@@ -0,0 +1,551 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support  -  ROUSSET  -
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2006, Atmel Corporation
+
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the disclaimer below in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "mci.h"
+#include 
+#include 
+
+//------------------------------------------------------------------------------
+//         Local constants
+//------------------------------------------------------------------------------
+
+/// Bit mask for status register errors.
+#define STATUS_ERRORS (AT91C_MCI_UNRE  \
+                       | AT91C_MCI_OVRE \
+                       | AT91C_MCI_DTOE \
+                       | AT91C_MCI_DCRCE \
+                       | AT91C_MCI_RTOE \
+                       | AT91C_MCI_RENDE \
+                       | AT91C_MCI_RCRCE \
+                       | AT91C_MCI_RDIRE \
+                       | AT91C_MCI_RINDE)
+
+/// MCI data timeout configuration with 1048576 MCK cycles between 2 data transfers.
+#define DTOR_1MEGA_CYCLES           (AT91C_MCI_DTOCYC | AT91C_MCI_DTOMUL)
+
+#define SDCARD_APP_OP_COND_CMD      (41 | AT91C_MCI_SPCMD_NONE  | AT91C_MCI_RSPTYP_48   | AT91C_MCI_TRCMD_NO )
+#define MMC_SEND_OP_COND_CMD        (1  | AT91C_MCI_TRCMD_NO    | AT91C_MCI_SPCMD_NONE  | AT91C_MCI_RSPTYP_48 | AT91C_MCI_OPDCMD)
+
+
+#define DISABLE    0    // Disable MCI interface
+#define ENABLE     1    // Enable MCI interface
+
+
+//------------------------------------------------------------------------------
+//         Local macros
+//------------------------------------------------------------------------------
+
+/// Used to write in PMC registers.
+#define WRITE_PMC(pPmc, regName, value)     pPmc->regName = (value)
+
+/// Used to write in MCI registers.
+#define WRITE_MCI(pMci, regName, value)     pMci->regName = (value)
+
+/// Used to read from MCI registers.
+#define READ_MCI(pMci, regName)             (pMci->regName)
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Enable/disable a MCI driver instance.
+/// \param pMci  Pointer to a MCI driver instance.
+/// \param enb  0 for disable MCI and 1 for enable MCI.
+//------------------------------------------------------------------------------
+void MCI_Enable(Mci *pMci, unsigned char enb)
+{
+	AT91S_MCI *pMciHw = pMci->pMciHw;
+
+	SANITY_CHECK(pMci);
+    SANITY_CHECK(pMci->pMciHw);
+
+    // Set the Control Register: Enable/Disable MCI interface clock
+    if(enb == DISABLE) {
+        WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS);
+    }
+    else {
+        WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIEN);
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Initializes a MCI driver instance and the underlying peripheral.
+/// \param pMci  Pointer to a MCI driver instance.
+/// \param pMciHw  Pointer to a MCI peripheral.
+/// \param mciId  MCI peripheral identifier.
+/// \param mode  Slot and type of connected card.
+//------------------------------------------------------------------------------
+void MCI_Init(
+    Mci *pMci,
+    AT91S_MCI *pMciHw,
+    unsigned char mciId,
+    unsigned int mode)
+{
+    unsigned short clkDiv;
+
+    SANITY_CHECK(pMci);
+    SANITY_CHECK(pMciHw);
+    SANITY_CHECK((mode == MCI_MMC_SLOTA) || (mode == MCI_MMC_SLOTB)
+                 || (mode == MCI_SD_SLOTA) || (mode == MCI_SD_SLOTB));
+
+    // Initialize the MCI driver structure
+    pMci->pMciHw = pMciHw;
+    pMci->mciId  = mciId;
+    pMci->semaphore = 1;
+    pMci->pCommand = 0;
+
+    // Enable the MCI clock
+    WRITE_PMC(AT91C_BASE_PMC, PMC_PCER, (1 << mciId));
+    
+     // Reset the MCI
+    WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_SWRST);
+
+    // Disable the MCI
+    WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_PWSDIS);
+
+    // Disable all the interrupts
+    WRITE_MCI(pMciHw, MCI_IDR, 0xFFFFFFFF);
+
+    // Set the Data Timeout Register
+    WRITE_MCI(pMciHw, MCI_DTOR, DTOR_1MEGA_CYCLES);
+
+    // Set the Mode Register: 400KHz for MCK = 48MHz (CLKDIV = 58)
+    clkDiv = (BOARD_MCK / (400000 * 2)) - 1;
+    WRITE_MCI(pMciHw, MCI_MR, (clkDiv | (AT91C_MCI_PWSDIV & (0x7 << 8))));
+
+    // Set the SDCard Register
+    WRITE_MCI(pMciHw, MCI_SDCR, mode);
+
+    // Enable the MCI and the Power Saving
+    WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIEN);
+
+    // Disable the MCI peripheral clock.
+    WRITE_PMC(AT91C_BASE_PMC, PMC_PCDR, (1 << mciId));
+}
+
+//------------------------------------------------------------------------------
+/// Close a MCI driver instance and the underlying peripheral.
+/// \param pMci  Pointer to a MCI driver instance.
+/// \param pMciHw  Pointer to a MCI peripheral.
+/// \param mciId  MCI peripheral identifier.
+//------------------------------------------------------------------------------
+void MCI_Close(Mci *pMci)
+{
+    AT91S_MCI *pMciHw = pMci->pMciHw;
+
+    SANITY_CHECK(pMci);
+    SANITY_CHECK(pMciHw);
+
+    // Initialize the MCI driver structure
+    pMci->semaphore = 1;
+    pMci->pCommand = 0;
+
+    // Disable the MCI peripheral clock.
+    WRITE_PMC(AT91C_BASE_PMC, PMC_PCDR, (1 << pMci->mciId));
+    
+    // Disable the MCI
+    WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS);
+
+    // Disable all the interrupts
+    WRITE_MCI(pMciHw, MCI_IDR, 0xFFFFFFFF);
+}
+
+//------------------------------------------------------------------------------
+/// Configure the  MCI CLKDIV in the MCI_MR register. The max. for MCI clock is 
+/// MCK/2 and corresponds to CLKDIV = 0
+/// \param pMci  Pointer to the low level MCI driver.
+/// \param mciSpeed  MCI clock speed in Hz.
+//------------------------------------------------------------------------------
+void MCI_SetSpeed(Mci *pMci, unsigned int mciSpeed)
+{
+    AT91S_MCI *pMciHw = pMci->pMciHw;
+    unsigned int mciMr;
+    unsigned short clkdiv;
+
+    SANITY_CHECK(pMci);
+    SANITY_CHECK(pMci->pMciHw);
+
+    // Set the Mode Register: 400KHz for MCK = 48MHz (CLKDIV = 58)
+    mciMr = READ_MCI(pMciHw, MCI_MR) & (~AT91C_MCI_CLKDIV);
+
+    // Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
+    // divided by (2*(CLKDIV+1))
+    if (mciSpeed > 0) {
+
+        clkdiv = (BOARD_MCK / (mciSpeed * 2));
+        if (clkdiv > 0) {
+
+            clkdiv -= 1;
+        }
+    }
+    else {
+
+        clkdiv = 0;
+    }
+
+    WRITE_MCI(pMciHw, MCI_MR, mciMr | clkdiv);
+}
+
+//------------------------------------------------------------------------------
+/// Configure the  MCI SDCBUS in the MCI_SDCR register. Only two modes available
+/// 
+/// \param pMci  Pointer to the low level MCI driver.
+/// \param busWidth  MCI bus width mode.
+//------------------------------------------------------------------------------
+void MCI_SetBusWidth(Mci *pMci, unsigned char busWidth)
+{
+    AT91S_MCI *pMciHw = pMci->pMciHw;
+    unsigned int mciSdcr;
+
+    SANITY_CHECK(pMci);
+    SANITY_CHECK(pMci->pMciHw);
+
+    mciSdcr = (READ_MCI(pMciHw, MCI_SDCR) & ~(AT91C_MCI_SCDBUS));
+
+    WRITE_MCI(pMciHw, MCI_SDCR, mciSdcr | busWidth);
+}
+
+//------------------------------------------------------------------------------
+/// Starts a MCI  transfer. This is a non blocking function. It will return
+/// as soon as the transfer is started.
+/// Return 0 if successful; otherwise returns MCI_ERROR_LOCK if the driver is
+/// already in use.
+/// \param pMci  Pointer to an MCI driver instance.
+/// \param pCommand  Pointer to the command to execute.
+//------------------------------------------------------------------------------
+unsigned char MCI_SendCommand(Mci *pMci, MciCmd *pCommand)
+{
+    AT91PS_MCI pMciHw = pMci->pMciHw;
+    unsigned int mciIer, mciMr;
+
+    SANITY_CHECK(pMci);
+    SANITY_CHECK(pMciHw);
+    SANITY_CHECK(pCommand);
+
+    // Try to acquire the MCI semaphore
+    if (pMci->semaphore == 0) {
+    
+        return MCI_ERROR_LOCK;
+    }
+    pMci->semaphore--;
+    // trace_LOG(trace_DEBUG, "MCI_SendCommand %x %d\n\r", READ_MCI(pMciHw, MCI_SR), pCommand->cmd & 0x3f);
+
+    // Command is now being executed
+    pMci->pCommand = pCommand;
+    pCommand->status = MCI_STATUS_PENDING;
+
+    // Enable the MCI clock
+    WRITE_PMC(AT91C_BASE_PMC, PMC_PCER, (1 << pMci->mciId));
+
+    //Disable MCI clock, for multi-block data transfer
+    MCI_Enable(pMci, DISABLE);
+
+    // Set PDC data transfer direction
+    if(pCommand->blockSize > 0) {
+        if(pCommand->isRead) {
+            WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_RXTEN);
+        }
+        else {
+            WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_TXTEN);
+        }
+    }
+    // Disable transmitter and receiver
+    WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS);
+
+    mciMr = READ_MCI(pMciHw, MCI_MR) & (~(AT91C_MCI_BLKLEN | AT91C_MCI_PDCMODE));
+
+    // Command with DATA stage
+    if (pCommand->blockSize > 0) {
+        // Enable PDC mode and set block size
+        if(pCommand->conTrans != MCI_CONTINUE_TRANSFER) {
+
+            WRITE_MCI(pMciHw, MCI_MR, mciMr | AT91C_MCI_PDCMODE | (pCommand->blockSize << 16));
+        }
+
+        // DATA transfer from card to host
+        if (pCommand->isRead) { 
+            WRITE_MCI(pMciHw, MCI_RPR, (int) pCommand->pData);
+
+            // If Multiblock command set the BLKR register
+            /* if (pCommand->nbBlock > 1) { 
+                WRITE_MCI(pMciHw, MCI_BLKR, pCommand->nbBlock | (pCommand->blockSize << 16));
+            }
+            else {
+                WRITE_MCI(pMciHw, MCI_BLKR, (pCommand->blockSize << 16));        		
+            }*/
+
+            // Sanity check
+            if (pCommand->nbBlock == 0)
+                pCommand->nbBlock = 1;
+            ////////
+            if ((pCommand->blockSize & 0x3) != 0) {
+                WRITE_MCI(pMciHw, MCI_RCR, (pCommand->nbBlock * pCommand->blockSize) / 4 + 1);
+            }
+            else {
+                WRITE_MCI(pMciHw, MCI_RCR, (pCommand->nbBlock * pCommand->blockSize) / 4);
+            }
+
+            WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_RXTEN);
+            mciIer = AT91C_MCI_ENDRX | STATUS_ERRORS;
+            // mciIer = AT91C_MCI_RXBUFF | STATUS_ERRORS;
+        }
+
+        // DATA transfer from host to card
+        else {
+            // Sanity check
+            if (pCommand->nbBlock == 0)
+                pCommand->nbBlock = 1;
+            WRITE_MCI(pMciHw, MCI_TPR, (int) pCommand->pData);
+            // Update the PDC counter
+            if ((pCommand->blockSize & 0x3) != 0) {
+                WRITE_MCI(pMciHw, MCI_TCR, (pCommand->nbBlock * pCommand->blockSize) / 4 + 1);
+            }
+            else {
+                WRITE_MCI(pMciHw, MCI_TCR, (pCommand->nbBlock * pCommand->blockSize) / 4);
+            }
+            // MCI_BLKE notifies the end of Multiblock command
+            mciIer = AT91C_MCI_BLKE | STATUS_ERRORS;
+        }
+    }
+    // No data transfer: stop at the end of the command
+    else {
+        WRITE_MCI(pMciHw, MCI_MR, mciMr);
+        mciIer = AT91C_MCI_CMDRDY | STATUS_ERRORS;
+    }
+    // Enable MCI clock
+    MCI_Enable(pMci, ENABLE);
+
+    // Send the command
+    if((pCommand->conTrans != MCI_CONTINUE_TRANSFER) 
+        || (pCommand->blockSize == 0)) {
+
+        WRITE_MCI(pMciHw, MCI_ARGR, pCommand->arg);
+        WRITE_MCI(pMciHw, MCI_CMDR, pCommand->cmd);
+    }
+
+    // In case of transmit, the PDC shall be enabled after sending the command
+    if ((pCommand->blockSize > 0) && !(pCommand->isRead)) {
+        WRITE_MCI(pMciHw, MCI_PTCR, AT91C_PDC_TXTEN);
+    }
+
+    // Ignore data error
+//    if (pCommand->blockSize == 0) {
+    {
+        mciIer &= ~(AT91C_MCI_UNRE | AT91C_MCI_OVRE \
+            | AT91C_MCI_DTOE | AT91C_MCI_DCRCE);
+    }
+
+    // Interrupt enable shall be done after PDC TXTEN and RXTEN
+    WRITE_MCI(pMciHw, MCI_IER, mciIer);
+
+    return 0;
+}
+
+//------------------------------------------------------------------------------
+/// Check NOTBUSY and DTIP bits of status register on the given MCI driver.
+/// Return value, 0 for bus ready, 1 for bus busy
+/// \param pMci  Pointer to a MCI driver instance.
+//------------------------------------------------------------------------------
+unsigned char MCI_CheckBusy(Mci *pMci)
+{
+    AT91S_MCI *pMciHw = pMci->pMciHw;
+    unsigned int status;
+
+    // Enable MCI clock
+    MCI_Enable(pMci, ENABLE);
+
+    status = READ_MCI(pMciHw, MCI_SR);
+    // trace_LOG(trace_DEBUG, "status %x\n\r",status);
+
+
+    if(((status & AT91C_MCI_NOTBUSY)!=0)
+        && ((status & AT91C_MCI_DTIP)==0)) {
+
+        // Disable MCI clock
+        MCI_Enable(pMci, DISABLE);
+
+        return 0;
+    }
+    else {
+        return 1;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Check BLKE bit of status register on the given MCI driver.
+/// \param pMci  Pointer to a MCI driver instance.
+//------------------------------------------------------------------------------
+unsigned char MCI_CheckBlke(Mci *pMci)
+{
+    AT91S_MCI *pMciHw = pMci->pMciHw;
+    unsigned int status;
+
+    status = READ_MCI(pMciHw, MCI_SR);
+    // trace_LOG(trace_DEBUG, "status %x\n\r",status);
+
+    if((status & AT91C_MCI_BLKE)!=0) {
+        return 0;
+    }
+    else {
+        return 1;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Processes pending events on the given MCI driver.
+/// \param pMci  Pointer to a MCI driver instance.
+//------------------------------------------------------------------------------
+void MCI_Handler(Mci *pMci)
+{
+    AT91S_MCI *pMciHw = pMci->pMciHw;
+    MciCmd *pCommand = pMci->pCommand;
+    unsigned int status;
+    unsigned char i;
+    #if defined(at91rm9200)
+    unsigned int mciCr, mciSdcr, mciMr, mciDtor;
+    #endif
+
+    SANITY_CHECK(pMci);
+    SANITY_CHECK(pMciHw);
+    SANITY_CHECK(pCommand);
+
+    // Read the status register
+    status = READ_MCI(pMciHw, MCI_SR) & READ_MCI(pMciHw, MCI_IMR);
+    // trace_LOG(trace_DEBUG, "status %x\n\r", status);
+
+    // Check if an error has occured
+    if ((status & STATUS_ERRORS) != 0) {
+
+        // Check error code
+        if ((status & STATUS_ERRORS) == AT91C_MCI_RTOE) {
+        
+            pCommand->status = MCI_STATUS_NORESPONSE;
+        }
+        // if the command is SEND_OP_COND the CRC error flag is always present
+        // (cf : R3 response)
+        else if (((status & STATUS_ERRORS) != AT91C_MCI_RCRCE)
+                  || ((pCommand->cmd != SDCARD_APP_OP_COND_CMD)
+                      && (pCommand->cmd != MMC_SEND_OP_COND_CMD))) {
+
+            pCommand->status = MCI_STATUS_ERROR;
+        }
+    }
+
+    // Check if a transfer has been completed
+    if (((status & AT91C_MCI_CMDRDY) != 0)
+        || ((status & AT91C_MCI_ENDRX) != 0)
+        || ((status & AT91C_MCI_RXBUFF) != 0)
+        || ((status & AT91C_MCI_ENDTX) != 0)
+        || ((status & AT91C_MCI_BLKE) != 0)
+        || ((status & AT91C_MCI_RTOE) != 0)) {
+
+        if (((status & AT91C_MCI_ENDRX) != 0)
+            || ((status & AT91C_MCI_RXBUFF) != 0)
+            || ((status & AT91C_MCI_ENDTX) != 0)) {
+
+            MCI_Enable(pMci, DISABLE);
+        }
+
+        /// On AT91RM9200-EK, if stop transmission, software reset MCI.
+        #if defined(at91rm9200)
+        if ((pCommand->cmd & AT91C_MCI_TRCMD_STOP) != 0) {
+            mciMr = READ_MCI(pMciHw, MCI_MR);
+            mciSdcr = READ_MCI(pMciHw, MCI_SDCR);
+            mciDtor = READ_MCI(pMciHw, MCI_DTOR);
+            WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_SWRST);
+            // trace_LOG(trace_DEBUG, "reset MCI\n\r");
+
+            WRITE_MCI(pMciHw, MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_PWSDIS);
+            WRITE_MCI(pMciHw, MCI_MR, mciMr);
+            WRITE_MCI(pMciHw, MCI_SDCR, mciSdcr);
+            WRITE_MCI(pMciHw, MCI_DTOR, mciDtor);
+        }
+        #endif
+
+        // If no error occured, the transfer is successful
+        if (pCommand->status == MCI_STATUS_PENDING) {
+            pCommand->status = 0;
+        }
+#if 0
+        if ((status & AT91C_MCI_CMDRDY) != 0)
+            trace_LOG(trace_DEBUG, ".");
+        if ((status & AT91C_MCI_ENDRX) != 0)
+            trace_LOG(trace_DEBUG, "<");
+        if ((status & AT91C_MCI_ENDTX) != 0)
+            trace_LOG(trace_DEBUG, "-");
+        if ((status & AT91C_MCI_BLKE) != 0)
+            trace_LOG(trace_DEBUG, ">");
+        trace_LOG(trace_DEBUG, "\n\r");
+#endif        
+        // Store the card response in the provided buffer
+        if (pCommand->pResp) {
+
+            for (i=0; i < pCommand->resSize; i++) {
+
+                pCommand->pResp[i] = READ_MCI(pMciHw, MCI_RSPR[0]);
+            }
+        }
+
+        // Disable interrupts
+        WRITE_MCI(pMciHw, MCI_IDR, READ_MCI(pMciHw, MCI_IMR));
+
+        // Release the semaphore
+        pMci->semaphore++;
+
+        // Invoke the callback associated with the current command (if any)
+        if (pCommand->callback) {
+            (pCommand->callback)(pCommand->status, pCommand);
+        }
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Returns 1 if the given MCI transfer is complete; otherwise returns 0.
+/// \param pCommand  Pointer to a MciCmd instance.
+//------------------------------------------------------------------------------
+unsigned char MCI_IsTxComplete(MciCmd *pCommand)
+{
+    if (pCommand->status != MCI_STATUS_PENDING) {
+        if (pCommand->status != 0)
+            printf("MCI_IsTxComplete %d\n\r", pCommand->status);
+        return 1;
+    }
+    else {
+        return 0;
+    }
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/mci/mci.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/mci/mci.h
new file mode 100644
index 0000000..e112fc6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/mci/mci.h
@@ -0,0 +1,159 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support  -  ROUSSET  -
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2006, Atmel Corporation
+
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the disclaimer below in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef MCI_H
+#define MCI_H
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include 
+
+//------------------------------------------------------------------------------
+//         Constants
+//------------------------------------------------------------------------------
+
+/// Transfer is pending.
+#define MCI_STATUS_PENDING      1
+/// Transfer has been aborted because an error occured.
+#define MCI_STATUS_ERROR        2
+/// Card did not answer command.
+#define MCI_STATUS_NORESPONSE   3
+
+/// MCI driver is currently in use.
+#define MCI_ERROR_LOCK    1
+
+/// MCI configuration with 1-bit data bus on slot A (for MMC cards).
+#define MCI_MMC_SLOTA	        0
+/// MCI configuration with 1-bit data bus on slot B (for MMC cards).
+#define MCI_MMC_SLOTB	        1
+/// MCI configuration with 4-bit data bus on slot A (for SD cards).
+#define MCI_SD_SLOTA	        AT91C_MCI_SCDBUS
+/// MCI configuration with 4-bit data bus on slot B (for SD cards).
+#define MCI_SD_SLOTB	        (AT91C_MCI_SCDBUS | 1)
+
+/// Start new data transfer
+#define MCI_NEW_TRANSFER        0
+/// Continue data transfer
+#define MCI_CONTINUE_TRANSFER   1
+
+/// MCI SD Bus Width 1-bit
+#define MCI_SDCBUS_1BIT (0 << 7)
+/// MCI SD Bus Width 4-bit
+#define MCI_SDCBUS_4BIT (1 << 7)
+
+//------------------------------------------------------------------------------
+//         Types
+//------------------------------------------------------------------------------
+
+/// MCI end-of-transfer callback function.
+typedef void (*MciCallback)(unsigned char status, void *pCommand);
+
+//------------------------------------------------------------------------------
+/// MCI Transfer Request prepared by the application upper layer. This structure
+/// is sent to the MCI_SendCommand function to start the transfer. At the end of 
+/// the transfer, the callback is invoked by the interrupt handler.
+//------------------------------------------------------------------------------
+typedef struct _MciCmd {
+
+    /// Command status.
+	volatile char status;
+    /// Command code.
+	unsigned int cmd;
+    /// Command argument.
+	unsigned int arg;
+    /// Data buffer.
+	unsigned char *pData;
+    /// Size of data buffer in bytes.
+	unsigned short blockSize;
+	/// Number of blocks to be transfered
+	unsigned short nbBlock;
+	/// Indicate if continue to transfer data
+	unsigned char conTrans;
+    /// Indicates if the command is a read operation.
+	unsigned char isRead;
+    /// Response buffer.
+    unsigned int  *pResp;
+    /// Size of SD card response in bytes.
+	unsigned char  resSize;
+	/// Optional user-provided callback function.
+	MciCallback callback;
+    /// Optional argument to the callback function.
+	void *pArg;
+
+} MciCmd;
+
+//------------------------------------------------------------------------------
+/// MCI driver structure. Holds the internal state of the MCI driver and
+/// prevents parallel access to a MCI peripheral.
+//------------------------------------------------------------------------------
+typedef struct {
+
+    /// Pointer to a MCI peripheral.
+	AT91S_MCI *pMciHw;
+    /// MCI peripheral identifier.
+    unsigned char mciId;
+    /// Pointer to currently executing command.
+	MciCmd *pCommand;
+	/// Mutex.
+	volatile char semaphore;
+
+} Mci;
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+extern void MCI_Init(
+    Mci *pMci,
+    AT91PS_MCI pMciHw,
+    unsigned char mciId,
+    unsigned int mode);
+
+extern void MCI_SetSpeed(Mci *pMci, unsigned int mciSpeed);
+
+extern unsigned char MCI_SendCommand(Mci *pMci, MciCmd *pMciCmd);
+
+extern void MCI_Handler(Mci *pMci);
+
+extern unsigned char MCI_IsTxComplete(MciCmd *pMciCmd);
+
+extern unsigned char MCI_CheckBusy(Mci *pMci);
+
+extern void MCI_Close(Mci *pMci);
+
+extern void MCI_SetBusWidth(Mci *pMci, unsigned char busWidth);
+
+#endif //#ifndef MCI_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pio/pio.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pio/pio.c
new file mode 100644
index 0000000..c874d2d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pio/pio.c
@@ -0,0 +1,336 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "pio.h"
+#include 
+
+//------------------------------------------------------------------------------
+//         Internal definitions
+//------------------------------------------------------------------------------
+/// \internal Returns the current value of a register.
+#define READ(peripheral, register)          (peripheral->register)
+/// \internal Modifies the current value of a register.
+#define WRITE(peripheral, register, value)  (peripheral->register = value)
+
+//------------------------------------------------------------------------------
+//         Internal functions
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+/// Configures one or more pin(s) of a PIO controller as being controlled by
+/// peripheral A. Optionally, the corresponding internal pull-up(s) can be
+/// enabled.
+/// \param pio  Pointer to a PIO controller.
+/// \param mask  Bitmask of one or more pin(s) to configure.
+/// \param enablePullUp  Indicates if the pin(s) internal pull-up shall be
+///                      configured.
+//------------------------------------------------------------------------------
+static void PIO_SetPeripheralA(AT91S_PIO *pio,
+                               unsigned int mask,
+                               unsigned char enablePullUp)
+{
+    // Disable interrupts on the pin(s)
+    WRITE(pio, PIO_IDR, mask);
+
+    // Enable the pull-up(s) if necessary
+    if (enablePullUp) {
+
+        WRITE(pio, PIO_PPUER, mask);
+    }
+    else {
+
+        WRITE(pio, PIO_PPUDR, mask);
+    }
+
+    // Configure pin
+    WRITE(pio, PIO_ASR, mask);
+    WRITE(pio, PIO_PDR, mask);
+}
+
+//------------------------------------------------------------------------------
+/// Configures one or more pin(s) of a PIO controller as being controlled by
+/// peripheral A. Optionally, the corresponding internal pull-up(s) can be
+/// enabled.
+/// \param pio  Pointer to a PIO controller.
+/// \param mask  Bitmask of one or more pin(s) to configure.
+/// \param enablePullUp  Indicates if the pin(s) internal pull-up shall be
+///                      configured.
+//------------------------------------------------------------------------------
+static void PIO_SetPeripheralB(AT91S_PIO *pio,
+                               unsigned int mask,
+                               unsigned char enablePullUp)
+{
+    // Disable interrupts on the pin(s)
+    WRITE(pio, PIO_IDR, mask);
+
+    // Enable the pull-up(s) if necessary
+    if (enablePullUp) {
+
+        WRITE(pio, PIO_PPUER, mask);
+    }
+    else {
+
+        WRITE(pio, PIO_PPUDR, mask);
+    }
+
+    // Configure pin
+    WRITE(pio, PIO_BSR, mask);
+    WRITE(pio, PIO_PDR, mask);
+}
+
+//------------------------------------------------------------------------------
+/// Configures one or more pin(s) or a PIO controller as inputs. Optionally,
+/// the corresponding internal pull-up(s) and glitch filter(s) can be
+/// enabled.
+/// \param pio  Pointer to a PIO controller.
+/// \param mask  Bitmask indicating which pin(s) to configure as input(s).
+/// \param enablePullUp  Indicates if the internal pull-up(s) must be enabled.
+/// \param enableFilter  Indicates if the glitch filter(s) must be enabled.
+//------------------------------------------------------------------------------
+static void PIO_SetInput(AT91S_PIO *pio,
+                         unsigned int mask,
+                         unsigned char enablePullUp,
+                         unsigned char enableFilter)
+{
+    // Disable interrupts
+    WRITE(pio, PIO_IDR, mask);
+
+    // Enable pull-up(s) if necessary
+    if (enablePullUp) {
+    
+        WRITE(pio, PIO_PPUER, mask);
+    }
+    else {
+    
+        WRITE(pio, PIO_PPUDR, mask);
+    }
+
+    // Enable filter(s) if necessary
+    if (enableFilter) {
+    
+        WRITE(pio, PIO_IFER, mask);
+    }
+    else {
+    
+        WRITE(pio, PIO_IFDR, mask);
+    }
+
+    // Configure pin as input
+    WRITE(pio, PIO_ODR, mask);
+    WRITE(pio, PIO_PER, mask);
+}
+
+//------------------------------------------------------------------------------
+/// Configures one or more pin(s) of a PIO controller as outputs, with the
+/// given default value. Optionally, the multi-drive feature can be enabled
+/// on the pin(s).
+/// \param pio  Pointer to a PIO controller.
+/// \param mask  Bitmask indicating which pin(s) to configure.
+/// \param defaultValue  Default level on the pin(s).
+/// \param enableMultiDrive  Indicates if the pin(s) shall be configured as
+///                          open-drain.
+/// \param enablePullUp  Indicates if the pin shall have its pull-up activated.
+//------------------------------------------------------------------------------
+static void PIO_SetOutput(AT91S_PIO *pio,
+                          unsigned int mask,
+                          unsigned char defaultValue,
+                          unsigned char enableMultiDrive,
+                          unsigned char enablePullUp)
+{
+    // Disable interrupts
+    WRITE(pio, PIO_IDR, mask);
+
+    // Enable pull-up(s) if necessary
+    if (enablePullUp) {
+    
+        WRITE(pio, PIO_PPUER, mask);
+    }
+    else {
+    
+        WRITE(pio, PIO_PPUDR, mask);
+    }
+
+    // Enable multi-drive if necessary
+    if (enableMultiDrive) {
+    
+        WRITE(pio, PIO_MDER, mask);
+    }
+    else {
+    
+        WRITE(pio, PIO_MDDR, mask);
+    }
+
+    // Set default value
+    if (defaultValue) {
+
+        WRITE(pio, PIO_SODR, mask);
+    }
+    else {
+
+        WRITE(pio, PIO_CODR, mask);
+    }
+
+    // Configure pin(s) as output(s)
+    WRITE(pio, PIO_OER, mask);
+    WRITE(pio, PIO_PER, mask);
+}
+
+//------------------------------------------------------------------------------
+//         Exported functions
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+/// Configures a list of Pin instances, which can either hold a single pin or a 
+/// group of pins, depending on the mask value; all pins are configured by this 
+/// function.
+/// Returns 1 if the configuration has been performed successfully; otherwise 0.
+/// \param list  Pointer to a list of Pin instances.
+/// \param size  Size of the Pin list (see ).
+//------------------------------------------------------------------------------
+unsigned char PIO_Configure(const Pin *list, unsigned int size)
+{
+    // Configure pins
+    while (size > 0) {
+    
+        switch (list->type) {
+    
+            case PIO_PERIPH_A:
+                PIO_SetPeripheralA(list->pio,
+                                   list->mask,
+                                   (list->attribute & PIO_PULLUP) ? 1 : 0);
+                break;
+    
+            case PIO_PERIPH_B:
+                PIO_SetPeripheralB(list->pio,
+                                   list->mask,
+                                   (list->attribute & PIO_PULLUP) ? 1 : 0);
+                break;
+    
+            case PIO_INPUT:
+                AT91C_BASE_PMC->PMC_PCER = 1 << list->id;
+                PIO_SetInput(list->pio,
+                             list->mask,
+                             (list->attribute & PIO_PULLUP) ? 1 : 0,
+                             (list->attribute & PIO_DEGLITCH)? 1 : 0);
+                break;
+    
+            case PIO_OUTPUT_0:
+            case PIO_OUTPUT_1:
+                PIO_SetOutput(list->pio,
+                              list->mask,
+                              (list->type == PIO_OUTPUT_1),
+                              (list->attribute & PIO_OPENDRAIN) ? 1 : 0,
+                              (list->attribute & PIO_PULLUP) ? 1 : 0);
+                break;
+    
+            default: return 0;
+        }
+
+        list++;
+        size--;
+    }
+
+    return 1;
+}
+
+//------------------------------------------------------------------------------
+/// Sets a high output level on one or more pin(s) (if configured as output(s)).
+/// \param pin  Pointer to a Pin instance describing one or more pins.
+//------------------------------------------------------------------------------
+void PIO_Set(const Pin *pin)
+{
+    WRITE(pin->pio, PIO_SODR, pin->mask);
+}
+
+//------------------------------------------------------------------------------
+/// Sets a low output level on one or more pin(s) (if configured as output(s)).
+/// \param pin  Pointer to a Pin instance describing one or more pins.
+//------------------------------------------------------------------------------
+void PIO_Clear(const Pin *pin)
+{
+    WRITE(pin->pio, PIO_CODR, pin->mask);
+}
+
+//------------------------------------------------------------------------------
+/// Returns 1 if one or more PIO of the given Pin instance currently have a high
+/// level; otherwise returns 0.
+/// \param pin  Pointer to a Pin instance describing one or more pins.
+//------------------------------------------------------------------------------
+unsigned char PIO_Get(const Pin *pin)
+{
+    unsigned int reg;
+    if ((pin->type == PIO_OUTPUT_0) || (pin->type == PIO_OUTPUT_1)) {
+
+        reg = READ(pin->pio, PIO_ODSR);
+    }
+    else {
+
+        reg = READ(pin->pio, PIO_PDSR);
+    }
+
+    if ((reg & pin->mask) == 0) {
+
+        return 0;
+    }
+    else {
+
+        return 1;
+    }
+}
+
+
+//------------------------------------------------------------------------------
+/// Returns 1 if one or more PIO of the given Pin data to be driven on the I/O line
+/// level; otherwise returns 0.
+/// \param pin  Pointer to a Pin instance describing one or more pins.
+//------------------------------------------------------------------------------
+unsigned char PIO_GetOutputDataStatus(const Pin *pin)
+{
+    if ((READ(pin->pio, PIO_ODSR) & pin->mask) == 0) {
+
+        return 0;
+    }
+    else {
+
+        return 1;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Returns the value of ISR for the PIO controller of the pin.
+/// Reading this register acknoledges all the ITs.
+/// \param pin  Pointer to a Pin instance describing one or more pins.
+//------------------------------------------------------------------------------
+unsigned int PIO_GetISR(const Pin *pin)
+{
+    return (READ(pin->pio, PIO_ISR));
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pio/pio.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pio/pio.h
new file mode 100644
index 0000000..e5721dc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pio/pio.h
@@ -0,0 +1,169 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+/// \dir
+/// !Purpose
+///
+///     Definition of methods and structures for using PIOs in a transparent
+///     way. The main purpose is to allow portability between several boards.
+///
+/// !Usage
+///
+///     -# To configure and use pins, see pio.h.
+///     -# To enable and use interrupt generation on PIO status change, see
+///      pio_it.h.
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \unit
+/// !Purpose
+/// 
+/// Simple & portable usage of PIO pins.
+/// 
+/// !Usage
+/// 
+/// -# Define a constant pin description array such as the following one:
+///    \code
+///       const Pin at91board_dbgu[] = {
+///            {AT91C_BASE_PIOA, (1 << 30), PIO_PERIPH_A, PIO_DEFAULT},
+///            {AT91C_BASE_PIOA, (1 << 31), PIO_PERIPH_A, PIO_DEFAULT},
+///        };
+///    \endcode
+///    Alternatively, constants defined in the piodefs.h header file of the
+///    board module can be used:
+///    \code
+///    const Pin at91board_dbgu[] = {PINS_DBGU};
+///    const Pin at91board_usart[] = {PIN_USART0_RXD, PIN_USART0_TXD};
+///    \endcode
+///    It is possible to group multiple pins if they share the same
+///    attributes, to save memory. Here is the previous DBGU example
+///    rewritten in such a way:
+///    \code
+///    const Pin at91board_dbgu[] = {
+///         {AT91C_BASE_PIOA, 0xC0000000, PIO_PERIPH_A, PIO_DEFAULT}
+///    };
+///    \endcode
+/// -# For pins configured as inputs, the PIO controller must be enabled
+///    in the PMC (*enabled by PIO_Configure at the moment*).
+/// -# Configure a pin array by calling PIO_Configure, using
+///    the PIO_LISTSIZE macro to calculate the array size if needed. Do not
+///    forget to check the return value for any error.
+/// -# Set and get the value of a pin using the PIO_Set, PIO_Clear and
+///    PIO_Get methods.
+//------------------------------------------------------------------------------
+ 
+#ifndef PIO_H
+#define PIO_H
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include 
+
+//------------------------------------------------------------------------------
+//         Definitions
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+/// \page "Pin types" 
+/// This page lists the available types for a Pin instance (in its type field).
+/// !Types
+/// - PIO_PERIPH_A 
+/// - PIO_PERIPH_B 
+/// - PIO_INPUT 
+/// - PIO_OUTPUT_0 
+/// - PIO_OUTPUT_1 
+
+/// The pin is controlled by the associated signal of peripheral A.
+#define PIO_PERIPH_A                0
+/// The pin is controlled by the associated signal of peripheral B.
+#define PIO_PERIPH_B                1
+/// The pin is an input.
+#define PIO_INPUT                   2
+/// The pin is an output and has a default level of 0.
+#define PIO_OUTPUT_0                3
+/// The pin is an output and has a default level of 1.
+#define PIO_OUTPUT_1                4
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \page "Pin attributes"
+/// This page lists the valid values for the attribute field of a Pin instance.
+/// !Attributes
+/// - PIO_DEFAULT
+/// - PIO_PULLUP
+/// - PIO_DEGLITCH
+/// - PIO_OPENDRAIN
+
+/// Default pin configuration (no attribute).
+#define PIO_DEFAULT                 (0 << 0)
+/// The internal pin pull-up is active.
+#define PIO_PULLUP                  (1 << 0)
+/// The internal glitch filter is active.
+#define PIO_DEGLITCH                (1 << 1)
+/// The pin is open-drain.
+#define PIO_OPENDRAIN               (1 << 2)
+//------------------------------------------------------------------------------
+
+/// Calculates the size of a Pin instances array. The array must be local (i.e.
+/// not a pointer), otherwise the computation will not be correct.
+#define PIO_LISTSIZE(list)    (sizeof(list) / sizeof(Pin))
+
+//------------------------------------------------------------------------------
+//         Types
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+/// Describes the type and attribute of one PIO pin or a group of similar pins.
+typedef struct {
+    /// Bitmask indicating which pin(s) to configure.
+    unsigned int mask; 
+    /// Pointer to the PIO controller which has the pin(s).
+    AT91S_PIO    *pio;
+    /// Peripheral ID of the PIO controller which has the pin(s).
+    unsigned char id;
+    /// Pin type (see "Pin types").
+    unsigned char type;
+    /// Pin attribute (see "Pin attributes").
+    unsigned char attribute;
+} Pin;
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+//         Exported functions
+//------------------------------------------------------------------------------
+extern unsigned char PIO_Configure(const Pin *list, unsigned int size);
+extern void PIO_Set(const Pin *pin );
+extern void PIO_Clear(const Pin *pin);
+extern unsigned char PIO_Get(const Pin *pin);
+extern unsigned int PIO_GetISR(const Pin *pin);
+extern unsigned char PIO_GetOutputDataStatus(const Pin *pin);
+
+#endif //#ifndef PIO_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pio/pio_it.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pio/pio_it.c
new file mode 100644
index 0000000..c58220c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pio/pio_it.c
@@ -0,0 +1,387 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/// Disable traces for this file
+#ifndef NOTRACE
+    #define NOTRACE
+#endif
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "pio_it.h"
+#include "pio.h"
+#include 
+#include 
+#include 
+#include 
+
+//------------------------------------------------------------------------------
+//         Local definitions
+//------------------------------------------------------------------------------
+
+/// Returns the current value of a register.
+#define READ(peripheral, register)          (peripheral->register)
+/// Modifies the current value of a register.
+#define WRITE(peripheral, register, value)  (peripheral->register = value)
+
+/// Maximum number of interrupt sources that can be defined.
+#define MAX_INTERRUPT_SOURCES       7
+
+//------------------------------------------------------------------------------
+//         Local types
+//------------------------------------------------------------------------------
+
+/// Describes a PIO interrupt source, including the PIO instance triggering the
+/// interrupt and the associated interrupt handler.
+typedef struct _InterruptSource {
+
+    /// Interrupt source pin.
+    const Pin *pPin;
+
+    /// Interrupt handler.
+    void (*handler)(const Pin *);
+
+} InterruptSource;
+
+//------------------------------------------------------------------------------
+//         Local variables
+//------------------------------------------------------------------------------
+
+/// List of interrupt sources.
+static InterruptSource pSources[MAX_INTERRUPT_SOURCES];
+
+/// Number of currently defined interrupt sources.
+static unsigned int numSources;
+
+//------------------------------------------------------------------------------
+//         Local functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Handles all interrupts on the given PIO controller.
+/// \param id  PIO controller ID.
+/// \param pBase  PIO controller base address.
+//------------------------------------------------------------------------------
+void PioInterruptHandler(unsigned int id, AT91S_PIO *pBase)
+{
+    unsigned int status;
+    unsigned int i;
+
+    // Check PIO controller status
+    status = pBase->PIO_ISR;
+    status &= pBase->PIO_IMR;
+    if (status != 0) {
+
+        trace_LOG(trace_DEBUG, "-D- PIO interrupt on PIO controller #%d\n\r", id);
+
+        // Check all sources
+        i = 0;
+        while (status != 0) {
+
+            // There cannot be an unconfigured source enabled.
+            SANITY_CHECK(i < numSources);
+
+            // Source if configured on PIOA
+            if (pSources[i].pPin->id == id) {
+
+                // Source has PIOs which have changed
+                if ((status & pSources[i].pPin->mask) != 0) {
+
+                    trace_LOG(trace_DEBUG, "-D- Interrupt source #%d triggered\n\r", i);
+
+                    pSources[i].handler(pSources[i].pPin);
+                    status &= ~(pSources[i].pPin->mask);
+                }
+            }
+            i++;
+        }
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Generic PIO interrupt handler. Single entry point for interrupts coming
+/// from any PIO controller (PIO A, B, C ...). Dispatches the interrupt to
+/// the user-configured handlers.
+//------------------------------------------------------------------------------
+void InterruptHandler()
+{
+#if defined(AT91C_ID_PIOA)
+    // Treat PIOA interrupts
+    PioInterruptHandler(AT91C_ID_PIOA, AT91C_BASE_PIOA);
+#endif
+
+#if defined(AT91C_ID_PIOB)
+    // Treat PIOB interrupts
+    PioInterruptHandler(AT91C_ID_PIOB, AT91C_BASE_PIOB);
+#endif
+
+#if defined(AT91C_ID_PIOC)
+    // Treat PIOC interrupts
+    PioInterruptHandler(AT91C_ID_PIOC, AT91C_BASE_PIOC);
+#endif
+
+#if defined(AT91C_ID_PIOD)
+    // Treat PIOD interrupts
+    PioInterruptHandler(AT91C_ID_PIOD, AT91C_BASE_PIOD);
+#endif
+
+#if defined(AT91C_ID_PIOE)
+    // Treat PIOE interrupts
+    PioInterruptHandler(AT91C_ID_PIOE, AT91C_BASE_PIOE);
+#endif
+
+#if defined(AT91C_ID_PIOABCD)
+    // Treat PIOABCD interrupts
+    #if !defined(AT91C_ID_PIOA)
+        PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOA);
+    #endif
+    #if !defined(AT91C_ID_PIOB)
+        PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOB);
+    #endif
+    #if !defined(AT91C_ID_PIOC)
+        PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOC);
+    #endif
+    #if !defined(AT91C_ID_PIOD)
+        PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOD);
+    #endif
+#endif
+
+#if defined(AT91C_ID_PIOABCDE)
+    // Treat PIOABCDE interrupts
+    #if !defined(AT91C_ID_PIOA)
+        PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOA);
+    #endif
+    #if !defined(AT91C_ID_PIOB)
+        PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOB);
+    #endif
+    #if !defined(AT91C_ID_PIOC)
+        PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOC);
+    #endif
+    #if !defined(AT91C_ID_PIOD)
+        PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOD);
+    #endif
+    #if !defined(AT91C_ID_PIOE)
+        PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOE);
+    #endif
+#endif
+
+#if defined(AT91C_ID_PIOCDE)
+    // Treat PIOCDE interrupts
+    #if !defined(AT91C_ID_PIOC)
+        PioInterruptHandler(AT91C_ID_PIOCDE, AT91C_BASE_PIOC);
+    #endif
+    #if !defined(AT91C_ID_PIOD)
+        PioInterruptHandler(AT91C_ID_PIOCDE, AT91C_BASE_PIOD);
+    #endif
+    #if !defined(AT91C_ID_PIOE)
+        PioInterruptHandler(AT91C_ID_PIOCDE, AT91C_BASE_PIOE);
+    #endif
+#endif
+
+}
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Initializes the PIO interrupt management logic.
+/// \param priority  PIO controller interrupts priority.
+//------------------------------------------------------------------------------
+void PIO_InitializeInterrupts(unsigned int priority)
+{
+    trace_LOG(trace_DEBUG, "-D- PIO_Initialize()\n\r");
+
+    SANITY_CHECK((priority & ~AT91C_AIC_PRIOR) == 0);
+
+    // Reset sources
+    numSources = 0;
+
+#ifdef AT91C_ID_PIOA
+    // Configure PIO interrupt sources
+    trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOA\n\r");
+    AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA;
+    AT91C_BASE_PIOA->PIO_ISR;
+    AT91C_BASE_PIOA->PIO_IDR = 0xFFFFFFFF;
+    AIC_ConfigureIT(AT91C_ID_PIOA, priority, InterruptHandler);
+    AIC_EnableIT(AT91C_ID_PIOA);
+#endif
+
+#ifdef AT91C_ID_PIOB
+    trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOB\n\r");
+    AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOB;
+    AT91C_BASE_PIOB->PIO_ISR;
+    AT91C_BASE_PIOB->PIO_IDR = 0xFFFFFFFF;
+    AIC_ConfigureIT(AT91C_ID_PIOB, priority, InterruptHandler);
+    AIC_EnableIT(AT91C_ID_PIOB);
+#endif
+
+#ifdef AT91C_ID_PIOC
+    trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOC\n\r");
+    AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOC;
+    AT91C_BASE_PIOC->PIO_ISR;
+    AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF;
+    AIC_ConfigureIT(AT91C_ID_PIOC, priority, InterruptHandler);
+    AIC_EnableIT(AT91C_ID_PIOC);
+#endif
+
+#ifdef AT91C_ID_PIOD
+    trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOD\n\r");
+    AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOD;
+    AT91C_BASE_PIOC->PIO_ISR;
+    AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF;
+    AIC_ConfigureIT(AT91C_ID_PIOD, priority, InterruptHandler);
+    AIC_EnableIT(AT91C_ID_PIOD);
+#endif
+
+#ifdef AT91C_ID_PIOE
+    trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOE\n\r");
+    AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOE;
+    AT91C_BASE_PIOC->PIO_ISR;
+    AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF;
+    AIC_ConfigureIT(AT91C_ID_PIOE, priority, InterruptHandler);
+    AIC_EnableIT(AT91C_ID_PIOE);
+#endif
+
+#if defined(AT91C_ID_PIOABCD)
+    // Treat PIOABCD interrupts
+    #if !defined(AT91C_ID_PIOA) \
+     && !defined(AT91C_ID_PIOB) \
+     && !defined(AT91C_ID_PIOC) \
+     && !defined(AT91C_ID_PIOD)
+
+        trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOABCD\n\r");
+        AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD;
+        AT91C_BASE_PIOA->PIO_ISR;
+        AT91C_BASE_PIOA->PIO_IDR = 0xFFFFFFFF;
+        AIC_ConfigureIT(AT91C_ID_PIOABCD, priority, InterruptHandler);
+        AIC_EnableIT(AT91C_ID_PIOABCD);
+    #endif
+#endif
+
+#if defined(AT91C_ID_PIOABCDE)
+    // Treat PIOABCDE interrupts
+    #if !defined(AT91C_ID_PIOA) \
+     && !defined(AT91C_ID_PIOB) \
+     && !defined(AT91C_ID_PIOC) \
+     && !defined(AT91C_ID_PIOD) \
+     && !defined(AT91C_ID_PIOE)
+
+        trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOABCDE\n\r");
+        AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCDE;
+        AT91C_BASE_PIOA->PIO_ISR;
+        AT91C_BASE_PIOA->PIO_IDR = 0xFFFFFFFF;
+        AIC_ConfigureIT(AT91C_ID_PIOABCDE, priority, InterruptHandler);
+        AIC_EnableIT(AT91C_ID_PIOABCDE);
+    #endif
+#endif
+
+#if defined(AT91C_ID_PIOCDE)
+    // Treat PIOCDE interrupts
+    #if !defined(AT91C_ID_PIOC) \
+     && !defined(AT91C_ID_PIOD) \
+     && !defined(AT91C_ID_PIOE)
+
+        trace_LOG(trace_DEBUG, "-D- PIO_Initialize: Configuring PIOC\n\r");
+        AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOCDE;
+        AT91C_BASE_PIOC->PIO_ISR;
+        AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF;
+        AIC_ConfigureIT(AT91C_ID_PIOCDE, priority, InterruptHandler);
+        AIC_EnableIT(AT91C_ID_PIOCDE);
+    #endif
+#endif
+}
+
+//------------------------------------------------------------------------------
+/// Configures an interrupt source.
+/// \param pPin  Interrupt source.
+/// \param handler  Desired interrupt handler for the source.
+//------------------------------------------------------------------------------
+void PIO_ConfigureIt(const Pin *pPin, void (*handler)(const Pin *))
+{
+    InterruptSource *pSource;
+
+    trace_LOG(trace_DEBUG, "-D- PIO_ConfigureIt()\n\r");
+
+    SANITY_CHECK(pPin);
+    ASSERT(numSources < MAX_INTERRUPT_SOURCES,
+           "-F- PIO_ConfigureIt: Increase MAX_INTERRUPT_SOURCES\n\r");
+
+    // Define new source
+    trace_LOG(trace_DEBUG, "-D- PIO_ConfigureIt: Defining new source #%d.\n\r", numSources);
+
+    pSource = &(pSources[numSources]);
+    pSource->pPin = pPin;
+    pSource->handler = handler;
+    numSources++;
+}
+
+//------------------------------------------------------------------------------
+/// Enables the given interrupt source if it has been configured.
+/// \param pPin  Interrupt source to enable.
+//------------------------------------------------------------------------------
+void PIO_EnableIt(const Pin *pPin)
+{
+    trace_LOG(trace_DEBUG, "-D- PIO_EnableIt()\n\r");
+
+    SANITY_CHECK(pPin);
+
+#ifndef NOASSERT
+    unsigned int i = 0;
+    unsigned char found = 0;
+    while ((i < numSources) && !found) {
+
+        if (pSources[i].pPin == pPin) {
+
+            found = 1;
+        }
+        i++;
+    }
+    ASSERT(found, "-F- PIO_EnableIt: Interrupt source has not been configured\n\r");
+#endif
+
+    pPin->pio->PIO_ISR;
+    pPin->pio->PIO_IER = pPin->mask;
+}
+
+//------------------------------------------------------------------------------
+/// Disables a given interrupt source.
+/// \param pPin  Interrupt source to disable.
+//------------------------------------------------------------------------------
+void PIO_DisableIt(const Pin *pPin)
+{
+    SANITY_CHECK(pPin);
+
+    trace_LOG(trace_DEBUG, "-D- PIO_DisableIt()\n\r");
+
+    pPin->pio->PIO_IDR = pPin->mask;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pio/pio_it.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pio/pio_it.h
new file mode 100644
index 0000000..6f462ac
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pio/pio_it.h
@@ -0,0 +1,61 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+/// \unit
+/// !Purpose
+/// 
+/// Configuration and handling of interrupts on PIO status changes.
+/// 
+/// !Usage
+/// 
+/// -# Configure an status change interrupt on one or more pin(s) with
+///    PIO_ConfigureIt.
+/// -# Enable & disable interrupts on pins using PIO_EnableIt and
+///    PIO_DisableIt.
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "pio.h"
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+extern void PIO_InitializeInterrupts(unsigned int priority);
+
+extern void PIO_ConfigureIt(const Pin *pPin, void (*handler)(const Pin *));
+
+extern void PIO_EnableIt(const Pin *pPin);
+
+extern void PIO_DisableIt(const Pin *pPin);
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pit/pit.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pit/pit.c
new file mode 100644
index 0000000..40c8e03
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pit/pit.c
@@ -0,0 +1,115 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "pit.h"
+#include 
+
+//------------------------------------------------------------------------------
+//         Exported functions
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+/// Initialize the System timer for a period in µsecond with a system clock
+/// freq in MHz
+/// \param period  Period in µsecond.
+/// \param pit_frequency  System clock frequency in MHz.
+//------------------------------------------------------------------------------
+void PIT_Init(unsigned int period,
+                     unsigned int pit_frequency)
+{
+    AT91C_BASE_PITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10
+    AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN;
+}
+
+//------------------------------------------------------------------------------
+/// Set the PIT Periodic Interval Value
+//------------------------------------------------------------------------------
+void PIT_SetPIV(unsigned int piv)
+{
+    AT91C_BASE_PITC->PITC_PIMR = piv | (AT91C_BASE_PITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));
+}
+
+//------------------------------------------------------------------------------
+/// Enable the PIT
+//------------------------------------------------------------------------------
+void PIT_Enable(void)
+{
+    AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN;
+}
+
+//----------------------------------------------------------------------------
+/// Enable PIT periodic interrupt
+//----------------------------------------------------------------------------
+void PIT_EnableIT(void)
+{
+    AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITIEN;
+}
+
+//------------------------------------------------------------------------------
+/// Disable PIT periodic interrupt
+//------------------------------------------------------------------------------
+void PIT_DisableIT(void)
+{
+    AT91C_BASE_PITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;
+}
+
+//------------------------------------------------------------------------------
+/// Read PIT mode register
+//------------------------------------------------------------------------------
+unsigned int PIT_GetMode(void)
+{
+    return(AT91C_BASE_PITC->PITC_PIMR);
+}
+
+//------------------------------------------------------------------------------
+/// Read PIT status register
+//------------------------------------------------------------------------------
+unsigned int PIT_GetStatus(void)
+{
+    return(AT91C_BASE_PITC->PITC_PISR);
+}
+
+//------------------------------------------------------------------------------
+/// Read PIT CPIV and PICNT without ressetting the counters
+//------------------------------------------------------------------------------
+unsigned int PIT_GetPIIR(void)
+{
+    return(AT91C_BASE_PITC->PITC_PIIR);
+}
+
+//------------------------------------------------------------------------------
+/// Read System timer CPIV and PICNT without ressetting the counters
+//------------------------------------------------------------------------------
+unsigned int PIT_GetPIVR(void)
+{
+    return(AT91C_BASE_PITC->PITC_PIVR);
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pit/pit.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pit/pit.h
new file mode 100644
index 0000000..8f62e25
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pit/pit.h
@@ -0,0 +1,74 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+/// \unit
+/// !Purpose
+///
+/// Configuration and handling of PIT.
+///
+/// !Usage
+///
+/// -# Initialize System timer for a period in µsecond with
+///    PIT_Init
+/// -# Set the PIT Periodic Interval Value with PIT_SetPIV
+/// -# Enable the PIT with PIT_Enable
+/// -# Enable & disable PIT interrupts using PIT_EnableInt and
+///    PIT_DisableInt
+/// -# Read PIT mode register
+///    PIT_GetMode
+/// -# Read PIT status register
+///    PIT_GetStatus
+/// -# Read PIT CPIV and PICNT without ressetting the counters
+///    PIT_GetPIIR
+/// -# Read System timer CPIV and PICNT without ressetting the counters
+///    PIT_GetPIVR
+//------------------------------------------------------------------------------
+
+#ifndef PIT_H
+#define PIT_H
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+//         Exported functions
+//------------------------------------------------------------------------------
+extern void PIT_Init(unsigned int period, unsigned int pit_frequency);
+extern void PIT_SetPIV(unsigned int piv);
+extern void PIT_Enable(void);
+extern void PIT_EnableIT(void);
+extern void PIT_DisableIT(void);
+extern unsigned int PIT_GetMode(void);
+extern unsigned int PIT_GetStatus(void);
+extern unsigned int PIT_GetPIIR(void);
+extern unsigned int PIT_GetPIVR(void);
+
+#endif //#ifndef PIT_H
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pmc/pmc.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pmc/pmc.c
new file mode 100644
index 0000000..c04fc31
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pmc/pmc.c
@@ -0,0 +1,133 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "pmc.h"
+#include 
+#include 
+#include 
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+#if defined(at91sam7l64) || defined(at91sam7l128)
+//------------------------------------------------------------------------------
+/// Sets the fast wake-up inputs that can get the device out of Wait mode.
+/// \param inputs  Fast wake-up inputs to enable.
+//------------------------------------------------------------------------------
+void PMC_SetFastWakeUpInputs(unsigned int inputs)
+{
+    SANITY_CHECK((inputs & ~0xFF) == 0);
+    AT91C_BASE_PMC->PMC_FSMR = inputs;
+}
+
+#if !defined(__ICCARM__)
+__attribute__ ((section (".ramfunc"))) // GCC
+#endif
+//------------------------------------------------------------------------------
+/// Disables the main oscillator, making the device enter Wait mode.
+//------------------------------------------------------------------------------
+void PMC_DisableMainOscillatorForWaitMode(void)
+{
+    AT91C_BASE_PMC->PMC_MOR = 0x37 << 16;
+    while ((AT91C_BASE_PMC->PMC_MOR & AT91C_PMC_MAINSELS) != AT91C_PMC_MAINSELS);
+}
+
+#endif
+
+#if defined(at91sam7l)
+//------------------------------------------------------------------------------
+/// Disables the main oscillator when NOT running on it.
+//------------------------------------------------------------------------------
+void PMC_DisableMainOscillator(void)
+{
+    AT91C_BASE_PMC->PMC_MOR = 0x37 << 16;
+    while ((AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MAINSELS) == AT91C_PMC_MAINSELS);
+}
+#endif
+
+//------------------------------------------------------------------------------
+/// Disables the processor clock, making the device enter Idle mode.
+//------------------------------------------------------------------------------
+void PMC_DisableProcessorClock(void)
+{
+    AT91C_BASE_PMC->PMC_SCDR = AT91C_PMC_PCK;
+    while ((AT91C_BASE_PMC->PMC_SCSR & AT91C_PMC_PCK) != AT91C_PMC_PCK);
+}
+
+//------------------------------------------------------------------------------
+/// Enables the clock of a peripheral. The peripheral ID (AT91C_ID_xxx) is used
+/// to identify which peripheral is targetted.
+/// Note that the ID must NOT be shifted (i.e. 1 << AT91C_ID_xxx).
+/// \param id  Peripheral ID (AT91C_ID_xxx).
+//------------------------------------------------------------------------------
+void PMC_EnablePeripheral(unsigned int id)
+{
+    SANITY_CHECK(id < 32);
+
+    if ((AT91C_BASE_PMC->PMC_PCSR & (1 << id)) == (1 << id)) {
+
+        trace_LOG(trace_INFO,
+                  "-I- PMC_EnablePeripheral: clock of peripheral"
+                  " %u is already enabled\n\r",
+                  id);
+    }
+    else {
+
+        AT91C_BASE_PMC->PMC_PCER = 1 << id;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Disables the clock of a peripheral. The peripheral ID (AT91C_ID_xxx) is used
+/// to identify which peripheral is targetted.
+/// Note that the ID must NOT be shifted (i.e. 1 << AT91C_ID_xxx).
+/// \param id  Peripheral ID (AT91C_ID_xxx).
+//------------------------------------------------------------------------------
+void PMC_DisablePeripheral(unsigned int id)
+{
+    SANITY_CHECK(id < 32);
+
+    if ((AT91C_BASE_PMC->PMC_PCSR & (1 << id)) != (1 << id)) {
+
+        trace_LOG(trace_INFO,
+                  "-I- PMC_DisablePeripheral: clock of peripheral"
+                  " %u is not enabled\n\r",
+                  id);
+    }
+    else {
+
+        AT91C_BASE_PMC->PMC_PCDR = 1 << id;
+    }
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pmc/pmc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pmc/pmc.h
new file mode 100644
index 0000000..5b885df
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pmc/pmc.h
@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef PMC_H
+#define PMC_H
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+#if defined(at91sam7l64) || defined(at91sam7l128)
+extern void PMC_SetFastWakeUpInputs(unsigned int inputs);
+extern void PMC_DisableMainOscillator(void);
+extern
+#ifdef __ICCARM__
+__ramfunc
+#endif
+void PMC_DisableMainOscillatorForWaitMode(void);
+#endif
+
+extern void PMC_DisableProcessorClock(void);
+
+extern void PMC_EnablePeripheral(unsigned int id);
+
+extern void PMC_DisablePeripheral(unsigned int id);
+#endif //#ifndef PMC_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pwmc/pwmc.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pwmc/pwmc.c
new file mode 100644
index 0000000..7bbe698
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pwmc/pwmc.c
@@ -0,0 +1,238 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "pwmc.h"
+#include 
+#include 
+#include 
+
+//------------------------------------------------------------------------------
+//         Local functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Finds a prescaler/divisor couple to generate the desired frequency from
+/// MCK.
+/// Returns the value to enter in PWMC_MR or 0 if the configuration cannot be
+/// met.
+/// \param frequency  Desired frequency in Hz.
+/// \param mck  Master clock frequency in Hz.
+//------------------------------------------------------------------------------
+static unsigned short FindClockConfiguration(
+    unsigned int frequency,
+    unsigned int mck)
+{
+    unsigned int divisors[11] = {1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024};
+    unsigned char divisor = 0;
+    unsigned int prescaler;
+
+    SANITY_CHECK(frequency < mck);
+
+    // Find prescaler and divisor values
+    prescaler = (mck / divisors[divisor]) / frequency;
+    while ((prescaler > 255) && (divisor < 11)) {
+
+        divisor++;
+        prescaler = (mck / divisors[divisor]) / frequency;
+    }
+
+    // Return result
+    if (divisor < 11) {
+
+        trace_LOG(trace_DEBUG, "-D- Found divisor=%u and prescaler=%u for freq=%uHz\n\r",
+                  divisors[divisor], prescaler, frequency);
+        return prescaler | (divisor << 8);
+    }
+    else {
+
+        return 0;
+    }
+}
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Configures PWM a channel with the given parameters.
+/// The PWM controller must have been clocked in the PMC prior to calling this
+/// function.
+/// \param channel  Channel number.
+/// \param prescaler  Channel prescaler.
+/// \param alignment  Channel alignment.
+/// \param polarity  Channel polarity.
+//------------------------------------------------------------------------------
+void PWMC_ConfigureChannel(
+    unsigned char channel,
+    unsigned int prescaler,
+    unsigned int alignment,
+    unsigned int polarity)
+{
+    SANITY_CHECK(prescaler < AT91C_PWMC_CPRE_MCKB);
+    SANITY_CHECK((alignment & ~AT91C_PWMC_CALG) == 0);
+    SANITY_CHECK((polarity & ~AT91C_PWMC_CPOL) == 0);
+
+    // Disable channel
+    AT91C_BASE_PWMC->PWMC_DIS = 1 << channel;
+
+    // Configure channel
+    AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CMR = prescaler | alignment | polarity;
+}
+
+//------------------------------------------------------------------------------
+/// Configures PWM clocks A & B to run at the given frequencies. This function
+/// finds the best MCK divisor and prescaler values automatically.
+/// \param clka  Desired clock A frequency (0 if not used).
+/// \param clkb  Desired clock B frequency (0 if not used).
+/// \param mck  Master clock frequency.
+//------------------------------------------------------------------------------
+void PWMC_ConfigureClocks(unsigned int clka, unsigned int clkb, unsigned int mck)
+{
+    unsigned int mode = 0;
+    unsigned int result;
+
+    // Clock A
+    if (clka != 0) {
+
+        result = FindClockConfiguration(clka, mck);
+        ASSERT(result != 0, "-F- Could not generate the desired PWM frequency (%uHz)\n\r", clka);
+        mode |= result;
+    }
+
+    // Clock B
+    if (clkb != 0) {
+
+        result = FindClockConfiguration(clkb, mck);
+        ASSERT(result != 0, "-F- Could not generate the desired PWM frequency (%uHz)\n\r", clkb);
+        mode |= (result << 16);
+    }
+
+    // Configure clocks
+    trace_LOG(trace_DEBUG, "-D- Setting PWMC_MR = 0x%08X\n\r", mode);
+    AT91C_BASE_PWMC->PWMC_MR = mode;
+}
+
+//------------------------------------------------------------------------------
+/// Sets the period value used by a PWM channel. This function writes directly
+/// to the CPRD register if the channel is disabled; otherwise, it uses the
+/// update register CUPD.
+/// \param channel  Channel number.
+/// \param period  Period value.
+//------------------------------------------------------------------------------
+void PWMC_SetPeriod(unsigned char channel, unsigned short period)
+{
+    // If channel is disabled, write to CPRD
+    if ((AT91C_BASE_PWMC->PWMC_SR & (1 << channel)) == 0) {
+
+        AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CPRDR = period;
+    }
+    // Otherwise use update register
+    else {
+
+        AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CMR |= AT91C_PWMC_CPD;
+        AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CUPDR = period;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Sets the duty cycle used by a PWM channel. This function writes directly to
+/// the CDTY register if the channel is disabled; otherwise it uses the
+/// update register CUPD.
+/// Note that the duty cycle must always be inferior or equal to the channel
+/// period.
+/// \param channel  Channel number.
+/// \param duty  Duty cycle value.
+//------------------------------------------------------------------------------
+void PWMC_SetDutyCycle(unsigned char channel, unsigned short duty)
+{
+    SANITY_CHECK(duty <= AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CPRDR);
+
+    // SAM7S errata
+#if defined(at91sam7s16) || defined(at91sam7s161) || defined(at91sam7s32) \
+    || defined(at91sam7s321) || defined(at91sam7s64) || defined(at91sam7s128) \
+    || defined(at91sam7s256) || defined(at91sam7s512)
+    ASSERT(duty > 0, "-F- Duty cycle value 0 is not permitted on SAM7S chips.\n\r");
+    ASSERT((duty > 1) || (AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CMR & AT91C_PWMC_CALG),
+           "-F- Duty cycle value 1 is not permitted in left-aligned mode on SAM7S chips.\n\r");
+#endif
+
+    // If channel is disabled, write to CDTY
+    if ((AT91C_BASE_PWMC->PWMC_SR & (1 << channel)) == 0) {
+
+        AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CDTYR = duty;
+    }
+    // Otherwise use update register
+    else {
+
+        AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CMR &= ~AT91C_PWMC_CPD;
+        AT91C_BASE_PWMC->PWMC_CH[channel].PWMC_CUPDR = duty;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Enables the given PWM channel. This does NOT enable the corresponding pin;
+/// this must be done in the user code.
+/// \param channel  Channel number.
+//------------------------------------------------------------------------------
+void PWMC_EnableChannel(unsigned char channel)
+{
+    AT91C_BASE_PWMC->PWMC_ENA = 1 << channel;
+}
+
+//------------------------------------------------------------------------------
+/// Disables the given PWM channel.
+/// \param channel  Channel number.
+//------------------------------------------------------------------------------
+void PWMC_DisableChannel(unsigned char channel)
+{
+    AT91C_BASE_PWMC->PWMC_DIS = 1 << channel;
+}
+
+//------------------------------------------------------------------------------
+/// Enables the period interrupt for the given PWM channel.
+/// \param channel  Channel number.
+//------------------------------------------------------------------------------
+void PWMC_EnableChannelIt(unsigned char channel)
+{
+    AT91C_BASE_PWMC->PWMC_IER = 1 << channel;
+}
+
+//------------------------------------------------------------------------------
+/// Disables the period interrupt for the given PWM channel.
+/// \param channel  Channel number.
+//------------------------------------------------------------------------------
+void PWMC_DisableChannelIt(unsigned char channel)
+{
+    AT91C_BASE_PWMC->PWMC_IDR = 1 << channel;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pwmc/pwmc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pwmc/pwmc.h
new file mode 100644
index 0000000..fd20abf
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/pwmc/pwmc.h
@@ -0,0 +1,61 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef PWMC_H
+#define PWMC_H
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+extern void PWMC_ConfigureChannel(
+    unsigned char channel,
+    unsigned int prescaler,
+    unsigned int alignment,
+    unsigned int polarity);
+
+extern void PWMC_ConfigureClocks
+    (unsigned int clka,
+     unsigned int clkb,
+     unsigned int mck);
+
+extern void PWMC_SetPeriod(unsigned char channel, unsigned short period);
+
+extern void PWMC_SetDutyCycle(unsigned char channel, unsigned short duty);
+
+extern void PWMC_EnableChannel(unsigned char channel);
+
+extern void PWMC_DisableChannel(unsigned char channel);
+
+extern void PWMC_EnableChannelIt(unsigned char channel);
+
+extern void PWMC_DisableChannelIt(unsigned char channel);
+
+#endif //#ifndef PWMC_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/rstc/rstc.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/rstc/rstc.c
new file mode 100644
index 0000000..6b93365
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/rstc/rstc.c
@@ -0,0 +1,188 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//-----------------------------------------------------------------------------
+//         Headers
+//-----------------------------------------------------------------------------
+
+#include 
+
+//-----------------------------------------------------------------------------
+//         Macros
+//-----------------------------------------------------------------------------
+
+/// WRITE_RSTC: Write RSTC register
+#define WRITE_RSTC(pRstc, regName, value) pRstc->regName = (value)
+
+/// READ_RSTC: Read RSTC registers
+#define READ_RSTC(pRstc, regName) (pRstc->regName)
+
+//-----------------------------------------------------------------------------
+//         Defines
+//-----------------------------------------------------------------------------
+
+/// Keywords to write to the reset registers
+#define RSTC_KEY_PASSWORD       (0xA5UL << 24)
+
+//-----------------------------------------------------------------------------
+//         Exported functions
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+/// Configure the mode of the RSTC peripheral.
+/// The configuration is computed by the lib (AT91C_RSTC_*).
+/// \param rstc  Pointer to an RSTC peripheral.
+/// \param rmr Desired mode configuration.
+//-----------------------------------------------------------------------------
+void RSTC_ConfigureMode(AT91PS_RSTC rstc, unsigned int rmr)
+{
+    rmr &= ~AT91C_RSTC_KEY;
+    WRITE_RSTC(rstc, RSTC_RMR, rmr | RSTC_KEY_PASSWORD);
+}
+
+//-----------------------------------------------------------------------------
+/// Enable/Disable the detection of a low level on the pin NRST as User Reset
+/// \param rstc   Pointer to an RSTC peripheral.
+/// \param enable 1 to enable & 0 to disable.
+//-----------------------------------------------------------------------------
+void RSTC_SetUserResetEnable(AT91PS_RSTC rstc, unsigned char enable)
+{
+    unsigned int rmr = READ_RSTC(rstc, RSTC_RMR) & (~AT91C_RSTC_KEY);
+    if (enable) {
+
+        rmr |=  AT91C_RSTC_URSTEN;
+    }
+    else {
+
+        rmr &= ~AT91C_RSTC_URSTEN;
+    }
+    WRITE_RSTC(rstc, RSTC_RMR, rmr | RSTC_KEY_PASSWORD);
+}
+
+//-----------------------------------------------------------------------------
+/// Enable/Disable the interrupt of a User Reset (USRTS bit in RSTC_RST).
+/// \param rstc   Pointer to an RSTC peripheral.
+/// \param enable 1 to enable & 0 to disable.
+//-----------------------------------------------------------------------------
+void RSTC_SetUserResetInterruptEnable(AT91PS_RSTC rstc, unsigned char enable)
+{
+    unsigned int rmr = READ_RSTC(rstc, RSTC_RMR) & (~AT91C_RSTC_KEY);
+    if (enable) {
+
+        rmr |=  AT91C_RSTC_URSTIEN;
+    }
+    else {
+
+        rmr &= ~AT91C_RSTC_URSTIEN;
+    }
+    WRITE_RSTC(rstc, RSTC_RMR, rmr | RSTC_KEY_PASSWORD);
+}
+
+//-----------------------------------------------------------------------------
+/// Setup the external reset length. The length is asserted during a time of
+/// pow(2, powl+1) Slow Clock(32KHz). The duration is between 60us and 2s.
+/// \param rstc   Pointer to an RSTC peripheral.
+/// \param powl   Power length defined.
+//-----------------------------------------------------------------------------
+void RSTC_SetExtResetLength(AT91PS_RSTC rstc, unsigned char powl)
+{
+    unsigned int rmr = READ_RSTC(rstc, RSTC_RMR);
+    rmr &= ~(AT91C_RSTC_KEY | AT91C_RSTC_ERSTL);
+    rmr |=  (powl << 8) & AT91C_RSTC_ERSTL;
+    WRITE_RSTC(rstc, RSTC_RMR, rmr | RSTC_KEY_PASSWORD);
+}
+
+
+//-----------------------------------------------------------------------------
+/// Resets the processor.
+/// \param rstc  Pointer to an RSTC peripheral.
+//-----------------------------------------------------------------------------
+void RSTC_ProcessorReset(AT91PS_RSTC rstc)
+{
+    WRITE_RSTC(rstc, RSTC_RCR, AT91C_RSTC_PROCRST | RSTC_KEY_PASSWORD);
+}
+
+//-----------------------------------------------------------------------------
+/// Resets the peripherals.
+/// \param rstc  Pointer to an RSTC peripheral.
+//-----------------------------------------------------------------------------
+void RSTC_PeripheralReset(AT91PS_RSTC rstc)
+{
+    WRITE_RSTC(rstc, RSTC_RCR, AT91C_RSTC_PERRST | RSTC_KEY_PASSWORD);
+}
+
+//-----------------------------------------------------------------------------
+/// Asserts the NRST pin for external resets.
+/// \param rstc  Pointer to an RSTC peripheral.
+//-----------------------------------------------------------------------------
+void RSTC_ExtReset(AT91PS_RSTC rstc)
+{
+    WRITE_RSTC(rstc, RSTC_RCR, AT91C_RSTC_EXTRST | RSTC_KEY_PASSWORD);
+}
+
+//-----------------------------------------------------------------------------
+/// Return NRST pin level ( 1 or 0 ).
+/// \param rstc  Pointer to an RSTC peripheral.
+//-----------------------------------------------------------------------------
+unsigned char RSTC_GetNrstLevel(AT91PS_RSTC rstc)
+{
+    if (READ_RSTC(rstc, RSTC_RSR) & AT91C_RSTC_NRSTL) {
+
+        return 1;
+    }
+    return 0;
+}
+
+//-----------------------------------------------------------------------------
+/// Returns 1 if at least one high-to-low transition of NRST (User Reset) has
+/// been detected since the last read of RSTC_RSR.
+/// \param rstc  Pointer to an RSTC peripheral.
+//-----------------------------------------------------------------------------
+unsigned char RSTC_IsUserReseetDetected(AT91PS_RSTC rstc)
+{
+    if (READ_RSTC(rstc, RSTC_RSR) & AT91C_RSTC_URSTS) {
+
+        return 1;
+    }
+    return 0;
+}
+
+//-----------------------------------------------------------------------------
+/// Return 1 if a software reset command is being performed by the reset
+/// controller. The reset controller is busy.
+/// \param rstc  Pointer to an RSTC peripheral.
+//-----------------------------------------------------------------------------
+unsigned char RSTC_IsBusy(AT91PS_RSTC rstc)
+{
+    if (READ_RSTC(rstc, RSTC_RSR) & AT91C_RSTC_SRCMP) {
+
+        return 1;
+    }
+    return 0;
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/rstc/rstc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/rstc/rstc.h
new file mode 100644
index 0000000..5306714
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/rstc/rstc.h
@@ -0,0 +1,58 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _RSTC_H
+#define _RSTC_H
+
+//-----------------------------------------------------------------------------
+//         Exported functions
+//-----------------------------------------------------------------------------
+
+extern void RSTC_ConfigureMode(AT91PS_RSTC rstc, unsigned int rmr);
+
+extern void RSTC_SetUserResetEnable(AT91PS_RSTC rstc, unsigned char enable);
+
+extern void RSTC_SetUserResetInterruptEnable(AT91PS_RSTC rstc,
+                                             unsigned char enable);
+
+extern void RSTC_SetExtResetLength(AT91PS_RSTC rstc, unsigned char powl);
+
+extern void RSTC_ProcessorReset(AT91PS_RSTC rstc);
+
+extern void RSTC_PeripheralReset(AT91PS_RSTC rstc);
+
+extern void RSTC_ExtReset(AT91PS_RSTC rstc);
+
+extern unsigned char RSTC_GetNrstLevel(AT91PS_RSTC rstc);
+
+extern unsigned char RSTC_IsUserReseetDetected(AT91PS_RSTC rstc);
+
+extern unsigned char RSTC_IsBusy(AT91PS_RSTC rstc);
+
+#endif // #ifndef _RSTC_H
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/rtc/rtc.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/rtc/rtc.c
new file mode 100644
index 0000000..841966e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/rtc/rtc.c
@@ -0,0 +1,338 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef trace_LEVEL
+	#define trace_LEVEL trace_INFO
+#endif
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "rtc.h"
+#include 
+#include 
+#include 
+
+//------------------------------------------------------------------------------
+//         Exported functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Sets the RTC in either 12- or 24-hour mode.
+/// \param mode  Hour mode.
+//------------------------------------------------------------------------------
+void RTC_SetHourMode(unsigned int mode)
+{
+	SANITY_CHECK((mode & 0xFFFFFFFE) == 0);
+
+    trace_LOG(trace_DEBUG, "-D- RTC_SetHourMode()\n\r");
+
+	AT91C_BASE_RTC->RTC_MR = mode;
+}
+
+//------------------------------------------------------------------------------
+/// Enables the selected interrupt sources of the RTC.
+/// \param sources  Interrupt sources to enable.
+//------------------------------------------------------------------------------
+void RTC_EnableIt(unsigned int sources)
+{
+    SANITY_CHECK((sources & ~0x1F) == 0);
+
+    trace_LOG(trace_DEBUG, "-D- RTC_EnableIt()\n\r");
+
+    AT91C_BASE_RTC->RTC_IER = sources;
+}
+
+//------------------------------------------------------------------------------
+/// Disables the selected interrupt sources of the RTC.
+/// \param sources  Interrupt sources to disable.
+//------------------------------------------------------------------------------
+void RTC_DisableIt(unsigned int sources)
+{
+    SANITY_CHECK((sources & ~0x1F) == 0);
+
+    trace_LOG(trace_DEBUG, "-D- RTC_DisableIt()\n\r");
+
+    AT91C_BASE_RTC->RTC_IDR = sources;
+}
+
+//------------------------------------------------------------------------------
+/// Sets the current time in the RTC.
+/// \param hour  Current hour.
+/// \param minute  Current minute.
+/// \param second  Current second.
+//------------------------------------------------------------------------------
+void RTC_SetTime(unsigned char hour, unsigned char minute, unsigned char second)
+{
+	unsigned int time;
+
+	SANITY_CHECK(hour < 24);
+	SANITY_CHECK(minute < 60);
+	SANITY_CHECK(second < 60);
+
+    trace_LOG(trace_DEBUG, "-D- RTC_SetTime(%02d:%02d:%02d)\n\r", hour, minute, second);
+
+	time = (second % 10) | ((second / 10) << 4)
+		   | ((minute % 10) << 8) | ((minute / 10) << 12);
+
+	// 12-hour mode
+	if ((AT91C_BASE_RTC->RTC_MR & AT91C_RTC_HRMOD) == AT91C_RTC_HRMOD) {
+
+		if (hour > 12) {
+
+			hour -= 12;
+			time |= AT91C_RTC_AMPM;
+		}
+	}
+
+	time |= ((hour % 10) << 16) | ((hour / 10) << 20);
+
+	// Set time
+	AT91C_BASE_RTC->RTC_CR |= AT91C_RTC_UPDTIM;
+	while ((AT91C_BASE_RTC->RTC_SR & AT91C_RTC_ACKUPD) != AT91C_RTC_ACKUPD);
+	AT91C_BASE_RTC->RTC_SCCR = AT91C_RTC_ACKUPD;
+	AT91C_BASE_RTC->RTC_TIMR = time;
+	AT91C_BASE_RTC->RTC_CR &= ~AT91C_RTC_UPDTIM;
+	SANITY_CHECK((AT91C_BASE_RTC->RTC_CR & AT91C_RTC_UPDTIM) != AT91C_RTC_UPDTIM);
+}
+
+//------------------------------------------------------------------------------
+/// Retrieves the current time as stored in the RTC in several variables.
+/// \param pHour  If not null, current hour is stored in this variable.
+/// \param pMinute  If not null, current minute is stored in this variable.
+/// \param pSecond  If not null, current second is stored in this variable.
+//------------------------------------------------------------------------------
+void RTC_GetTime(
+	unsigned char *pHour,
+	unsigned char *pMinute,
+	unsigned char *pSecond)
+{
+	unsigned int time;
+
+	SANITY_CHECK(pHour || pMinute || pSecond);
+
+    trace_LOG(trace_DEBUG, "-D- RTC_GetTime()\n\r");
+
+	// Get current RTC time
+	time = AT91C_BASE_RTC->RTC_TIMR;
+	while (time != AT91C_BASE_RTC->RTC_TIMR) {
+
+		time = AT91C_BASE_RTC->RTC_TIMR;
+	}
+
+	// Hour
+	if (pHour) {
+
+		*pHour = ((time & 0x00300000) >> 20) * 10
+				 + ((time & 0x000F0000) >> 16);
+		if ((time & AT91C_RTC_AMPM) == AT91C_RTC_AMPM) {
+
+			*pHour += 12;
+		}
+	}
+	
+	// Minute
+	if (pMinute) {
+
+		*pMinute = ((time & 0x00007000) >> 12) * 10
+				   + ((time & 0x00000F00) >> 8);
+	}
+
+	// Second
+	if (pSecond) {
+
+		*pSecond = ((time & 0x00000070) >> 4) * 10
+				   + (time & 0x0000000F);
+	}
+}
+
+//------------------------------------------------------------------------------
+/// Sets a time alarm on the RTC. The match is performed only on the provided
+/// variables; setting all pointers to 0 disables the time alarm.
+/// Note: in AM/PM mode, the hour value must have bit #7 set for PM, cleared for
+/// AM (as expected in the time registers).
+/// \param pHour  If not null, the time alarm will hour-match this value.
+/// \param pMinute  If not null, the time alarm will minute-match this value.
+/// \param pSecond  If not null, the time alarm will second-match this value.
+//------------------------------------------------------------------------------
+void RTC_SetTimeAlarm(
+	unsigned char *pHour,
+	unsigned char *pMinute,
+	unsigned char *pSecond)
+{
+	unsigned int alarm = 0;
+
+    SANITY_CHECK(!pHour || ((*pHour & 0x80) == 0));
+    SANITY_CHECK(!pMinute || (*pMinute < 60));
+    SANITY_CHECK(!pSecond || (*pSecond < 60));
+
+	trace_LOG(trace_DEBUG, "-D- RTC_SetTimeAlarm()\n\r");
+
+	// Hour
+	if (pHour) {
+
+		alarm |= AT91C_RTC_HOUREN | ((*pHour / 10) << 20) | ((*pHour % 10) << 16);
+	}
+
+	// Minute
+	if (pMinute) {
+
+		alarm |= AT91C_RTC_MINEN | ((*pMinute / 10) << 12) | ((*pMinute % 10) << 8);
+	}
+
+	// Second
+	if (pSecond) {
+
+		alarm |= AT91C_RTC_SECEN | ((*pSecond / 10) << 4) | (*pSecond % 10);
+	}
+
+	AT91C_BASE_RTC->RTC_TIMALR = alarm;
+}
+
+//------------------------------------------------------------------------------
+/// Retrieves the current year, month and day from the RTC. Month, day and week
+/// values are numbered starting at 1.
+/// \param pYear  Current year (optional).
+/// \param pMonth  Current month (optional).
+/// \param pDay  Current day (optional).
+/// \param pWeek  Current day in current week (optional).
+//------------------------------------------------------------------------------
+void RTC_GetDate(
+    unsigned short *pYear,
+    unsigned char *pMonth,
+    unsigned char *pDay,
+    unsigned char *pWeek)
+{
+    unsigned int date;
+
+    // Get current date (multiple reads are necessary to insure a stable value)
+    do {
+
+        date = AT91C_BASE_RTC->RTC_CALR;
+    }
+    while (date != AT91C_BASE_RTC->RTC_CALR);
+
+    // Retrieve year
+    if (pYear) {
+
+        *pYear = (((date  >> 4) & 0x7) * 1000)
+                 + ((date & 0xF) * 100)
+                 + (((date >> 12) & 0xF) * 10)
+                 + ((date >> 8) & 0xF);
+    }
+
+    // Retrieve month
+    if (pMonth) {
+
+        *pMonth = (((date >> 20) & 1) * 10) + ((date >> 16) & 0xF);
+    }
+
+    // Retrieve day
+    if (pDay) {
+
+        *pDay = (((date >> 28) & 0x3) * 10) + ((date >> 24) & 0xF);
+    }
+
+    // Retrieve week
+    if (pWeek) {
+
+        *pWeek = ((date >> 21) & 0x7);
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Sets the current year, month and day in the RTC. Month, day and week values
+/// must be numbered starting from 1.
+/// \param year  Current year.
+/// \param month  Current month.
+/// \param day  Current day.
+/// \param week  Day number in current week.
+//------------------------------------------------------------------------------
+void RTC_SetDate(
+    unsigned short year,
+    unsigned char month,
+    unsigned char day,
+    unsigned char week)
+{
+    unsigned int date;
+
+    SANITY_CHECK((year >= 1900) && (year <= 2099));
+    SANITY_CHECK((month >= 1) && (month <= 12));
+    SANITY_CHECK((day >= 1) && (day <= 31));
+    SANITY_CHECK((week >= 1) && (week <= 7));
+
+    // Convert values to date register value
+    date = ((year / 100) % 10)
+           | ((year / 1000) << 4)
+           | ((year % 10) << 8)
+           | (((year / 10) % 10) << 12)
+           | ((month % 10) << 16)
+           | ((month / 10) << 20)
+           | (week << 21)
+           | ((day % 10) << 24)
+           | ((day / 10) << 28);
+
+    // Update calendar register
+    AT91C_BASE_RTC->RTC_CR |= AT91C_RTC_UPDCAL;
+    while ((AT91C_BASE_RTC->RTC_SR & AT91C_RTC_ACKUPD) != AT91C_RTC_ACKUPD);
+    AT91C_BASE_RTC->RTC_SCCR = AT91C_RTC_ACKUPD;
+    AT91C_BASE_RTC->RTC_CALR = date;
+    AT91C_BASE_RTC->RTC_CR &= ~AT91C_RTC_UPDCAL;
+}
+
+//------------------------------------------------------------------------------
+/// Sets a date alarm in the RTC. The alarm will match only the provided values;
+/// passing a null-pointer disables the corresponding field match.
+/// \param pMonth  If not null, the RTC alarm will month-match this value.
+/// \param pDay  If not null, the RTC alarm will day-match this value.
+//------------------------------------------------------------------------------
+void RTC_SetDateAlarm(unsigned char *pMonth, unsigned char *pDay)
+{
+    unsigned int alarm = 0;
+
+    SANITY_CHECK(!pMonth || ((*pMonth >= 1) && (*pMonth <= 12)));
+    SANITY_CHECK(!pDay || ((*pDay >= 1) && (*pDay <= 31)));
+
+    trace_LOG(trace_DEBUG, "-D- RTC_SetDateAlarm()\n\r");
+
+    // Compute alarm field value
+    if (pMonth) {
+
+        alarm |= AT91C_RTC_MONTHEN | ((*pMonth / 10) << 20) | ((*pMonth % 10) << 16);
+    }
+    if (pDay) {
+
+        alarm |= AT91C_RTC_DATEEN | ((*pDay / 10) << 28) | ((*pDay % 10) << 24);
+    }
+
+    // Set alarm
+    AT91C_BASE_RTC->RTC_CALALR = alarm;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/rtc/rtc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/rtc/rtc.h
new file mode 100644
index 0000000..3fbbdcf
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/rtc/rtc.h
@@ -0,0 +1,73 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef RTC_H
+#define RTC_H
+
+//------------------------------------------------------------------------------
+//         Exported functions
+//------------------------------------------------------------------------------
+
+extern void RTC_SetHourMode(unsigned int mode);
+
+extern void RTC_EnableIt(unsigned int sources);
+
+extern void RTC_DisableIt(unsigned int sources);
+
+extern void RTC_SetTime(
+	unsigned char hour,
+	unsigned char minute,
+	unsigned char second);
+
+extern void RTC_GetTime(
+	unsigned char *pHour,
+	unsigned char *pMinute,
+	unsigned char *pSecond);
+
+extern void RTC_SetTimeAlarm(
+	unsigned char *pHour,
+	unsigned char *pMinute,
+	unsigned char *pSecond);
+
+void RTC_GetDate(
+    unsigned short *pYear,
+    unsigned char *pMonth,
+    unsigned char *pDay,
+    unsigned char *pWeek);
+
+extern void RTC_SetDate(
+    unsigned short year,
+    unsigned char month,
+    unsigned char day,
+    unsigned char week);
+
+extern void RTC_SetDateAlarm(unsigned char *pMonth, unsigned char *pDay);
+
+#endif //#ifndef RTC_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/rtt/rtt.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/rtt/rtt.c
new file mode 100644
index 0000000..5322108
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/rtt/rtt.c
@@ -0,0 +1,93 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "rtt.h"
+#include 
+
+//------------------------------------------------------------------------------
+//         Exported functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Changes the prescaler value of the given RTT and restarts it. This function
+/// disables RTT interrupt sources.
+/// \param rtt  Pointer to a AT91S_RTTC instance.
+/// \param prescaler  Prescaler value for the RTT.
+//------------------------------------------------------------------------------
+void RTT_SetPrescaler(AT91S_RTTC *rtt, unsigned short prescaler)
+{
+    rtt->RTTC_RTMR = (prescaler | AT91C_RTTC_RTTRST);
+}
+
+//------------------------------------------------------------------------------
+/// Returns the current value of the RTT timer value.
+/// \param rtt  Pointer to a AT91S_RTTC instance.
+//------------------------------------------------------------------------------
+unsigned int RTT_GetTime(AT91S_RTTC *rtt)
+{
+    return rtt->RTTC_RTVR;
+}
+
+//------------------------------------------------------------------------------
+/// Enables the specified RTT interrupt sources.
+/// \param rtt  Pointer to a AT91S_RTTC instance.
+/// \param sources  Bitmask of interrupts to enable.
+//------------------------------------------------------------------------------
+void RTT_EnableIT(AT91S_RTTC *rtt, unsigned int sources)
+{
+    ASSERT((sources & 0x0004FFFF) == 0,
+           "RTT_EnableIT: Wrong sources value.\n\r");
+    rtt->RTTC_RTMR |= sources;
+}
+
+//------------------------------------------------------------------------------
+/// Returns the status register value of the given RTT.
+/// \param rtt  Pointer to an AT91S_RTTC instance.
+//------------------------------------------------------------------------------
+unsigned int RTT_GetStatus(AT91S_RTTC *rtt)
+{
+    return rtt->RTTC_RTSR;
+}
+
+//------------------------------------------------------------------------------
+/// Configures the RTT to generate an alarm at the given time.
+/// \param pRtt  Pointer to an AT91S_RTTC instance.
+/// \param time  Alarm time.
+//------------------------------------------------------------------------------
+void RTT_SetAlarm(AT91S_RTTC *pRtt, unsigned int time)
+{
+    SANITY_CHECK(time > 0);
+
+    pRtt->RTTC_RTAR = time - 1;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/rtt/rtt.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/rtt/rtt.h
new file mode 100644
index 0000000..f92abe8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/rtt/rtt.h
@@ -0,0 +1,62 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef RTT_H
+#define RTT_H
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include 
+
+//------------------------------------------------------------------------------
+//         Definitions
+//------------------------------------------------------------------------------
+
+#ifndef AT91C_BASE_RTTC
+    #define AT91C_BASE_RTTC         AT91C_BASE_RTTC0
+#endif
+
+//------------------------------------------------------------------------------
+//         Exported functions
+//------------------------------------------------------------------------------
+
+extern void RTT_SetPrescaler(AT91S_RTTC *rtt, unsigned short prescaler);
+
+extern unsigned int RTT_GetTime(AT91S_RTTC *rtt);
+
+extern void RTT_EnableIT(AT91S_RTTC *rtt, unsigned int sources);
+
+extern unsigned int RTT_GetStatus(AT91S_RTTC *rtt);
+
+extern void RTT_SetAlarm(AT91S_RTTC *pRtt, unsigned int time);
+
+#endif //#ifndef RTT_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/slcdc/slcdc.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/slcdc/slcdc.c
new file mode 100644
index 0000000..4331ea8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/slcdc/slcdc.c
@@ -0,0 +1,192 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "slcdc.h"
+#include 
+#include 
+
+#include 
+
+//------------------------------------------------------------------------------
+//         Local definitions
+//------------------------------------------------------------------------------
+
+/// Size of SLCDC buffer in bytes.
+#define BUFFER_SIZE     320
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Initializes the Segment LCD controller.
+/// \param commons  Number of commons used by the display.
+/// \param segments  Number of segments used by the display.
+/// \param bias  Bias value.
+/// \param timeSetting  Buffer timing value.
+//------------------------------------------------------------------------------
+void SLCDC_Configure(
+    unsigned int commons,
+    unsigned int segments,
+    unsigned int bias,
+    unsigned int timeSetting)
+{
+    SANITY_CHECK((commons > 0) && (commons <= 10));
+    SANITY_CHECK((segments > 0) && (segments <= 40));
+    SANITY_CHECK((bias & ~AT91C_SLCDC_BIAS) == 0);
+	SANITY_CHECK((timeSetting & ~(0xF << 16)) == 0);  
+    SANITY_CHECK((timeSetting >> 16) < 0x0A);
+
+    // Enable peripheral clock
+    AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SLCD;
+    AT91C_BASE_SLCDC->SLCDC_MR = (commons - 1) | ((segments - 1) << 8) | bias | timeSetting;
+}
+
+//------------------------------------------------------------------------------
+/// Clears the SLCD display buffer.
+//------------------------------------------------------------------------------
+void SLCDC_Clear(void)
+{
+    memset((void *) AT91C_BASE_SLCDC->SLCDC_MEM, 0, BUFFER_SIZE);
+}
+
+//------------------------------------------------------------------------------
+/// Enables the SLCD controller.
+//------------------------------------------------------------------------------
+void SLCDC_Enable(void)
+{
+    AT91C_BASE_SLCDC->SLCDC_CR = AT91C_SLCDC_LCDEN;
+    while (AT91C_BASE_SLCDC -> SLCDC_SR != AT91C_SLCDC_ENA);
+}
+
+//------------------------------------------------------------------------------
+/// Disables the SLCD controller.
+//------------------------------------------------------------------------------
+void SLCDC_Disable(void)
+{
+    AT91C_BASE_SLCDC->SLCDC_CR = AT91C_SLCDC_LCDDIS;
+}
+
+//------------------------------------------------------------------------------
+/// Enables the SLCD low power mode.
+//------------------------------------------------------------------------------
+void SLCDC_EnableLowPowerMode(void)
+{
+    unsigned int value;
+
+    value = AT91C_BASE_SLCDC->SLCDC_MR;
+    value &= ~AT91C_SLCDC_LPMODE;
+    value |=AT91C_SLCDC_LPMODE;
+    AT91C_BASE_SLCDC->SLCDC_MR = value;
+}
+ 
+//------------------------------------------------------------------------------
+/// Disables the SLCD low power mode
+//------------------------------------------------------------------------------
+void SLCDC_DisableLowPowerMode(void)
+{
+    unsigned int value;
+
+    value = AT91C_BASE_SLCDC->SLCDC_MR;
+    value &= ~AT91C_SLCDC_LPMODE;
+    AT91C_BASE_SLCDC->SLCDC_MR = value;
+}
+
+//------------------------------------------------------------------------------
+/// Adjusts the frame frequency. Frequency = FsCLK / (prescaler * divider . NCOM)
+/// \param prescalerValue  Prescaler value
+/// \param dividerValue  Divider value
+//------------------------------------------------------------------------------
+void SLCDC_SetFrameFreq(unsigned int prescalerValue, unsigned int dividerValue)
+{
+    SANITY_CHECK((prescalerValue & ~AT91C_SLCDC_PRESC) == 0);
+    SANITY_CHECK((dividerValue & (~(0x07 << 8))) == 0);
+
+    AT91C_BASE_SLCDC->SLCDC_FRR = prescalerValue | dividerValue;
+}
+
+//------------------------------------------------------------------------------
+/// Sets the display mode (normal/force off/force on/blinking).
+/// \param mode  Display mode to be set
+//------------------------------------------------------------------------------
+void SLCDC_SetDisplayMode(unsigned int mode)
+{
+    unsigned int value;
+
+    SANITY_CHECK(mode < 8);
+           
+    value = AT91C_BASE_SLCDC->SLCDC_DR;
+    value &= ~AT91C_SLCDC_DISPMODE;
+    value |= mode;
+    AT91C_BASE_SLCDC->SLCDC_DR = value;
+}
+
+//------------------------------------------------------------------------------
+/// Adjusts the display blinking frequency.
+/// Blinking frequency = Frame Frequency / LCDBLKFREQ.
+/// \param frequency  Frequency value.
+//------------------------------------------------------------------------------
+void SLCDC_SetBlinkFreq(unsigned int frequency)
+{
+    unsigned int value;
+
+    SANITY_CHECK((frequency & ~(0xFF << 8)) == 0);
+
+    value = AT91C_BASE_SLCDC->SLCDC_DR;
+    value &= ~AT91C_SLCDC_BLKFREQ;
+    value |= frequency;           
+    AT91C_BASE_SLCDC->SLCDC_DR = frequency;
+}
+
+//------------------------------------------------------------------------------
+/// Enables the selected SLCDC interrupt sources.
+/// \param sources  Interrupt sources to enable.
+//------------------------------------------------------------------------------
+void SLCDC_EnableInterrupts(unsigned int sources)
+{
+    SANITY_CHECK((sources & 0xFFFFFFFA) == 0);
+
+    AT91C_BASE_SLCDC->SLCDC_IER = sources;
+}
+
+//------------------------------------------------------------------------------
+/// Disables the selected SLCDC interrupt sources.
+/// \param sources  Interrupt sources to disable.
+//------------------------------------------------------------------------------
+void SLCDC_DisableInterrupts(unsigned int sources)
+{
+    SANITY_CHECK((sources & 0xFFFFFFFA) == 0);
+
+    AT91C_BASE_SLCDC->SLCDC_IDR = sources;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/slcdc/slcdc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/slcdc/slcdc.h
new file mode 100644
index 0000000..63a8299
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/slcdc/slcdc.h
@@ -0,0 +1,71 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef SLCDC_H
+#define SLCDC_H
+
+//------------------------------------------------------------------------------
+//         Global definitions
+//------------------------------------------------------------------------------
+
+/// Number of segments in SLCD.
+#define S7LEKLCD_NUM_SEGMENTS       40
+/// Number of commons in SLCD.
+#define S7LEKLCD_NUM_COMMONS        10
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+extern void SLCDC_Configure(
+    unsigned int commons,
+    unsigned int segments,
+    unsigned int bias,
+    unsigned int timeSetting);
+
+extern void SLCDC_Clear(void);
+
+extern void SLCDC_Enable(void);
+
+extern void SLCDC_Disable(void);
+
+extern void SLCDC_SetFrameFreq(
+    unsigned int prescalerValue,
+    unsigned int dividerValue);
+
+extern void SLCDC_SetDisplayMode(unsigned int mode);
+
+extern void SLCDC_SetBlinkFreq(unsigned int frequency);
+
+extern void SLCDC_EnableInterrupts(unsigned int sources);
+
+extern void SLCDC_DisableInterrupts(unsigned int sources);
+
+#endif //#ifndef SLCDC_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/spi/spi.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/spi/spi.c
new file mode 100644
index 0000000..e77d28f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/spi/spi.c
@@ -0,0 +1,189 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "spi.h"
+
+//------------------------------------------------------------------------------
+//         Exported functions
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+/// Enables a SPI peripheral
+/// \param spi  Pointer to an AT91S_SPI instance.
+//------------------------------------------------------------------------------
+void SPI_Enable(AT91S_SPI *spi)
+{
+    spi->SPI_CR = AT91C_SPI_SPIEN;
+}
+
+//------------------------------------------------------------------------------
+/// Disables a SPI peripheral.
+/// \param spi  Pointer to an AT91S_SPI instance.
+//------------------------------------------------------------------------------
+void SPI_Disable(AT91S_SPI *spi)
+{
+    spi->SPI_CR = AT91C_SPI_SPIDIS;
+}
+
+//------------------------------------------------------------------------------
+/// Configures a SPI peripheral as specified. The configuration can be computed
+/// using several macros (see "SPI configuration macros") and the constants
+/// defined in LibV3 (AT91C_SPI_*).
+/// \param spi  Pointer to an AT91S_SPI instance.
+/// \param id  Peripheral ID of the SPI.
+/// \param configuration  Value of the SPI configuration register.
+//------------------------------------------------------------------------------
+void SPI_Configure(AT91S_SPI *spi,
+                          unsigned int id,
+                          unsigned int configuration)
+{
+    AT91C_BASE_PMC->PMC_PCER = 1 << id;
+    spi->SPI_CR = AT91C_SPI_SPIDIS | AT91C_SPI_SWRST;
+    spi->SPI_MR = configuration;
+}
+
+//------------------------------------------------------------------------------
+/// Configures a chip select of a SPI peripheral. The chip select configuration
+/// is computed using the definition provided by the LibV3 (AT91C_SPI_*).
+/// \param spi  Pointer to an AT91S_SPI instance.
+/// \param npcs  Chip select to configure (1, 2, 3 or 4).
+/// \param configuration  Desired chip select configuration.
+//------------------------------------------------------------------------------
+void SPI_ConfigureNPCS(AT91S_SPI *spi,
+                              unsigned int npcs,
+                              unsigned int configuration)
+{
+    spi->SPI_CSR[npcs] = configuration;
+}
+
+//------------------------------------------------------------------------------
+/// Sends data through a SPI peripheral. If the SPI is configured to use a fixed
+/// peripheral select, the npcs value is meaningless. Otherwise, it identifies
+/// the component which shall be addressed.
+/// \param spi  Pointer to an AT91S_SPI instance.
+/// \param npcs  Chip select of the component to address (1, 2, 3 or 4).
+/// \param data  Word of data to send.
+//------------------------------------------------------------------------------
+void SPI_Write(AT91S_SPI *spi, unsigned int npcs, unsigned short data)
+{
+    // Discard contents of RDR register
+    //volatile unsigned int discard = spi->SPI_RDR;
+
+    // Send data
+    while ((spi->SPI_SR & AT91C_SPI_TXEMPTY) == 0);
+    spi->SPI_TDR = data | SPI_PCS(npcs);
+    while ((spi->SPI_SR & AT91C_SPI_TDRE) == 0);
+}
+
+//------------------------------------------------------------------------------
+/// Sends the contents of buffer through a SPI peripheral, using the PDC to
+/// take care of the transfer.
+/// \param spi  Pointer to an AT91S_SPI instance.
+/// \param buffer  Data buffer to send.
+/// \param length  Length of the data buffer.
+//------------------------------------------------------------------------------
+unsigned char SPI_WriteBuffer(AT91S_SPI *spi,
+                                     void *buffer,
+                                     unsigned int length)
+{
+    // Check if first bank is free
+    if (spi->SPI_TCR == 0) {
+
+        spi->SPI_TPR = (unsigned int) buffer;
+        spi->SPI_TCR = length;
+        spi->SPI_PTCR = AT91C_PDC_TXTEN;
+        return 1;
+    }
+    // Check if second bank is free
+    else if (spi->SPI_TNCR == 0) {
+
+        spi->SPI_TNPR = (unsigned int) buffer;
+        spi->SPI_TNCR = length;
+        return 1;
+    }
+      
+    // No free banks
+    return 0;
+}
+
+//------------------------------------------------------------------------------
+/// Returns 1 if there is no pending write operation on the SPI; otherwise
+/// returns 0.
+/// \param pSpi  Pointer to an AT91S_SPI instance.
+//------------------------------------------------------------------------------
+unsigned char SPI_IsFinished(AT91S_SPI *pSpi)
+{
+    return ((pSpi->SPI_SR & AT91C_SPI_TXEMPTY) != 0);
+}
+
+//------------------------------------------------------------------------------
+/// Reads and returns the last word of data received by a SPI peripheral. This
+/// method must be called after a successful SPI_Write call.
+/// \param spi  Pointer to an AT91S_SPI instance.
+//------------------------------------------------------------------------------
+unsigned short SPI_Read(AT91S_SPI *spi)
+{
+    while ((spi->SPI_SR & AT91C_SPI_RDRF) == 0);
+    return spi->SPI_RDR & 0xFFFF;
+}
+
+//------------------------------------------------------------------------------
+/// Reads data from a SPI peripheral until the provided buffer is filled. This
+/// method does NOT need to be called after SPI_Write or SPI_WriteBuffer.
+/// \param spi  Pointer to an AT91S_SPI instance.
+/// \param buffer  Data buffer to store incoming bytes.
+/// \param length  Length in bytes of the data buffer.
+//------------------------------------------------------------------------------
+unsigned char SPI_ReadBuffer(AT91S_SPI *spi,
+                                    void *buffer,
+                                    unsigned int length)
+{
+    // Check if the first bank is free
+    if (spi->SPI_RCR == 0) {
+
+        spi->SPI_RPR = (unsigned int) buffer;
+        spi->SPI_RCR = length;
+        spi->SPI_PTCR = AT91C_PDC_RXTEN;
+        return 1;
+    }
+    // Check if second bank is free
+    else if (spi->SPI_RNCR == 0) {
+
+        spi->SPI_RNPR = (unsigned int) buffer;
+        spi->SPI_RNCR = length;
+        return 1;
+    }
+
+    // No free bank
+    return 0;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/spi/spi.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/spi/spi.h
new file mode 100644
index 0000000..39d803e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/spi/spi.h
@@ -0,0 +1,114 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+/// \dir
+/// !Purpose
+/// 
+/// Definitions for SPI peripheral usage.
+///
+/// !Usage
+///
+/// -# Enable the SPI pins required by the application (see pio.h).
+/// -# Configure the SPI using the SPI_Configure function. This enables the
+///    peripheral clock. The mode register is loaded with the given value.
+/// -# Configure all the necessary chip selects with SPI_ConfigureNPCS.
+/// -# Enable the SPI by calling SPI_Enable.
+/// -# Send/receive data using SPI_Write and SPI_Read. Note that SPI_Read
+///    must be called after SPI_Write to retrieve the last value read.
+/// -# Send/receive data using the PDC with the SPI_WriteBuffer and
+///    SPI_ReadBuffer functions.
+/// -# Disable the SPI by calling SPI_Disable.
+//------------------------------------------------------------------------------
+
+#ifndef SPI_H
+#define SPI_H
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include 
+
+//------------------------------------------------------------------------------
+//         Definitions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \page "SPI configuration macros"
+/// This page lists several macros which should be used when configuring a SPI
+/// peripheral.
+/// 
+/// !Macros
+/// - SPI_PCS
+/// - SPI_SCBR
+/// - SPI_DLYBS
+/// - SPI_DLYBCT
+
+/// Calculate the PCS field value given the chip select NPCS value
+#define SPI_PCS(npcs)       ((~(1 << npcs) & 0xF) << 16)
+
+/// Calculates the value of the CSR SCBR field given the baudrate and MCK.
+#define SPI_SCBR(baudrate, masterClock) \
+            ((unsigned int) (masterClock / baudrate) << 8)
+
+/// Calculates the value of the CSR DLYBS field given the desired delay (in ns)
+#define SPI_DLYBS(delay, masterClock) \
+            ((unsigned int) (((masterClock / 1000000) * delay) / 1000) << 16)
+
+/// Calculates the value of the CSR DLYBCT field given the desired delay (in ns)
+#define SPI_DLYBCT(delay, masterClock) \
+            ((unsigned int) (((masterClock / 1000000) * delay) / 32000) << 16)
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+//         Exported functions
+//------------------------------------------------------------------------------
+extern void SPI_Enable(AT91S_SPI *spi);
+extern void SPI_Disable(AT91S_SPI *spi);
+extern void SPI_Configure(AT91S_SPI *spi,
+                                 unsigned int id,
+                                 unsigned int configuration);
+extern void SPI_ConfigureNPCS(AT91S_SPI *spi,
+                                     unsigned int npcs,
+                                     unsigned int configuration);
+extern void SPI_Write(AT91S_SPI *spi, unsigned int npcs, unsigned short data);
+extern unsigned char SPI_WriteBuffer(AT91S_SPI *spi,
+                                            void *buffer,
+                                            unsigned int length);
+
+extern unsigned char SPI_IsFinished(AT91S_SPI *pSpi);
+
+extern unsigned short SPI_Read(AT91S_SPI *spi);
+extern unsigned char SPI_ReadBuffer(AT91S_SPI *spi,
+                                           void *buffer,
+                                           unsigned int length);
+
+#endif //#ifndef SPI_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/ssc/ssc.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/ssc/ssc.c
new file mode 100644
index 0000000..c0cb000
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/ssc/ssc.c
@@ -0,0 +1,243 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "ssc.h"
+#include 
+
+//------------------------------------------------------------------------------
+//         Exported functions
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+/// Configures a SSC peripheral. If the divided clock is not used, the master
+/// clock frequency can be set to 0.
+/// \note The emitter and transmitter are disabled by this function.
+/// \param ssc  Pointer to an AT91S_SSC instance.
+/// \param id  Peripheral ID of the SSC.
+//------------------------------------------------------------------------------
+void SSC_Configure(AT91S_SSC *ssc,
+                          unsigned int id,
+                          unsigned int bitRate,
+                          unsigned int masterClock)
+{
+    // Enable SSC peripheral clock
+    AT91C_BASE_PMC->PMC_PCER = 1 << id;
+
+    // Reset, disable receiver & transmitter
+    ssc->SSC_CR = AT91C_SSC_RXDIS | AT91C_SSC_TXDIS | AT91C_SSC_SWRST;
+    ssc->SSC_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS;
+
+    // Configure clock frequency
+    if (bitRate != 0) {
+    
+        ssc->SSC_CMR = masterClock / (2 * bitRate);
+    }
+    else {
+
+        ssc->SSC_CMR = 0;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Configures the transmitter of a SSC peripheral. Several macros can be used
+/// to compute the values of the Transmit Clock Mode Register (TCMR) and the
+/// Transmit Frame Mode Register (TFMR) (see "SSC configuration macros").
+/// \param ssc  Pointer to a AT91S_SSC instance.
+/// \param tcmr  Transmit Clock Mode Register value.
+/// \param tfmr  Transmit Frame Mode Register value.
+//------------------------------------------------------------------------------
+void SSC_ConfigureTransmitter(AT91S_SSC *ssc,
+                                     unsigned int tcmr,
+                                     unsigned int tfmr)
+{
+    ssc->SSC_TCMR = tcmr;
+    ssc->SSC_TFMR = tfmr;
+}
+
+//------------------------------------------------------------------------------
+/// Configures the receiver of a SSC peripheral. Several macros can be used
+/// to compute the values of the Receive Clock Mode Register (TCMR) and the
+/// Receive Frame Mode Register (TFMR) (see "SSC configuration macros").
+/// \param ssc  Pointer to a AT91S_SSC instance.
+/// \param rcmr  Receive Clock Mode Register value.
+/// \param rfmr  Receive Frame Mode Register value.
+//------------------------------------------------------------------------------
+void SSC_ConfigureReceiver(AT91S_SSC *ssc,
+                                  unsigned int rcmr,
+                                  unsigned int rfmr)
+{
+    ssc->SSC_RCMR = rcmr;
+    ssc->SSC_RFMR = rfmr;
+}
+
+//------------------------------------------------------------------------------
+/// Enables the transmitter of a SSC peripheral.
+/// \param ssc  Pointer to an AT91S_SSC instance.
+//------------------------------------------------------------------------------
+void SSC_EnableTransmitter(AT91S_SSC *ssc)
+{
+    ssc->SSC_CR = AT91C_SSC_TXEN;
+}
+
+//------------------------------------------------------------------------------
+/// Disables the transmitter of a SSC peripheral.
+/// \param ssc  Pointer to an AT91S_SSC instance.
+//------------------------------------------------------------------------------
+void SSC_DisableTransmitter(AT91S_SSC *ssc)
+{
+    ssc->SSC_CR = AT91C_SSC_TXDIS;
+}
+
+//------------------------------------------------------------------------------
+/// Enables the receiver of a SSC peripheral.
+/// \param ssc  Pointer to an AT91S_SSC instance.
+//------------------------------------------------------------------------------
+void SSC_EnableReceiver(AT91S_SSC *ssc)
+{
+    ssc->SSC_CR = AT91C_SSC_RXEN;
+}
+
+//------------------------------------------------------------------------------
+/// Disables the receiver of a SSC peripheral.
+/// \param ssc  Pointer to an AT91S_SSC instance.
+//------------------------------------------------------------------------------
+void SSC_DisableReceiver(AT91S_SSC *ssc)
+{
+    ssc->SSC_CR = AT91C_SSC_RXDIS;
+}
+
+//------------------------------------------------------------------------------
+/// Enables one or more interrupt sources of a SSC peripheral.
+/// \param ssc  Pointer to an AT91S_SSC instance.
+/// \param sources  Interrupt sources to enable.
+//------------------------------------------------------------------------------
+void SSC_EnableInterrupts(AT91S_SSC *ssc, unsigned int sources)
+{
+    ssc->SSC_IER = sources;
+}
+
+//------------------------------------------------------------------------------
+/// Disables one or more interrupt sources of a SSC peripheral.
+/// \param ssc  Pointer to an AT91S_SSC instance.
+/// \param sources  Interrupt source to disable.
+//------------------------------------------------------------------------------
+void SSC_DisableInterrupts(AT91S_SSC *ssc, unsigned int sources)
+{
+    ssc->SSC_IDR = sources;
+}
+
+//------------------------------------------------------------------------------
+/// Sends one data frame through a SSC peripheral. If another frame is currently
+/// being sent, this function waits for the previous transfer to complete.
+/// \param ssc  Pointer to an AT91S_SSC instance.
+/// \param frame  Data frame to send.
+//------------------------------------------------------------------------------
+void SSC_Write(AT91S_SSC *ssc, unsigned int frame)
+{
+    while ((ssc->SSC_SR & AT91C_SSC_TXRDY) == 0);
+    ssc->SSC_THR = frame;
+}
+
+//------------------------------------------------------------------------------
+/// Sends the contents of a data buffer a SSC peripheral, using the PDC. Returns
+/// true if the buffer has been queued for transmission; otherwise returns
+/// false.
+/// \param ssc  Pointer to an AT91S_SSC instance.
+/// \param buffer  Data buffer to send.
+/// \param length  Size of the data buffer.
+//------------------------------------------------------------------------------
+unsigned char SSC_WriteBuffer(AT91S_SSC *ssc,
+                                     void *buffer,
+                                     unsigned int length)
+{
+    // Check if first bank is free
+    if (ssc->SSC_TCR == 0) {
+
+        ssc->SSC_TPR = (unsigned int) buffer;
+        ssc->SSC_TCR = length;
+        ssc->SSC_PTCR = AT91C_PDC_TXTEN;
+        return 1;
+    }
+    // Check if second bank is free
+    else if (ssc->SSC_TNCR == 0) {
+
+        ssc->SSC_TNPR = (unsigned int) buffer;
+        ssc->SSC_TNCR = length;
+        return 1;
+    }
+      
+    // No free banks
+    return 0;
+}
+
+//------------------------------------------------------------------------------
+/// Waits until one frame is received on a SSC peripheral, and returns it.
+/// \param ssc  Pointer to an AT91S_SSC instance.
+//------------------------------------------------------------------------------
+unsigned int SSC_Read(AT91S_SSC *ssc)
+{
+    while ((ssc->SSC_SR & AT91C_SSC_RXRDY) == 0);
+    return ssc->SSC_RHR;
+}
+
+//------------------------------------------------------------------------------
+/// Reads data coming from a SSC peripheral receiver and stores it into the
+/// provided buffer. Returns true if the buffer has been queued for reception;
+/// otherwise returns false.
+/// \param ssc  Pointer to an AT91S_SSC instance.
+/// \param buffer  Data buffer used for reception.
+/// \param length  Size in bytes of the data buffer.
+//------------------------------------------------------------------------------
+unsigned char SSC_ReadBuffer(AT91S_SSC *ssc,
+                                    void *buffer,
+                                    unsigned int length)
+{
+    // Check if the first bank is free
+    if (ssc->SSC_RCR == 0) {
+
+        ssc->SSC_RPR = (unsigned int) buffer;
+        ssc->SSC_RCR = length;
+        ssc->SSC_PTCR = AT91C_PDC_RXTEN;
+        return 1;
+    }
+    // Check if second bank is free
+    else if (ssc->SSC_RNCR == 0) {
+
+        ssc->SSC_RNPR = (unsigned int) buffer;
+        ssc->SSC_RNCR = length;
+        return 1;
+    }
+
+    // No free bank
+    return 0;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/ssc/ssc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/ssc/ssc.h
new file mode 100644
index 0000000..4fade3a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/ssc/ssc.h
@@ -0,0 +1,133 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+/// \dir
+/// !Purpose
+///
+/// Set of functions and definition for using a SSC
+/// peripheral.
+///
+/// !Usage
+///
+/// -# Configure the SSC to operate at a specific frequency by calling
+///    SSC_Configure(). This function enables the peripheral clock of the SSC,
+///    but not its PIOs.
+/// -# Configure the transmitter and/or the receiver using the
+///    SSC_ConfigureTransmitter() and SSC_ConfigureEmitter() functions.
+/// -# Enable the PIOs or the transmitter and/or the received using
+///    CHIP_EnableSSCTransmitter() and CHIP_EnableSSCReceiver().
+/// -# Enable the transmitter and/or the receiver using SSC_EnableTransmitter()
+///    and SSC_EnableReceiver()
+/// -# Send data through the transmitter using SSC_Write() and SSC_WriteBuffer()
+/// -# Receive data from the receiver using SSC_Read() and SSC_ReadBuffer()
+/// -# Disable the transmitter and/or the receiver using SSC_DisableTransmitter()
+///    and SSC_DisableReceiver()
+//------------------------------------------------------------------------------
+
+#ifndef SSC_H
+#define SSC_H
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include 
+
+//------------------------------------------------------------------------------
+//         Definitions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \page "SSC configuration macros"
+/// This page lists several macros which are used when configuring a SSC
+/// peripheral.
+/// 
+/// !Macros
+/// - SSC_STTDLY
+/// - SSC_PERIOD
+/// - SSC_DATLEN
+/// - SSC_DATNB
+/// - SSC_FSLEN
+
+/// Calculates the value of the STTDLY field given the number of clock cycles
+/// before the first bit of a new frame is transmitted.
+#define SSC_STTDLY(bits)        (bits << 16)
+
+/// Calculates the value of the PERIOD field of the Transmit Clock Mode Register
+/// of an SSC interface, given the desired clock divider.
+#define SSC_PERIOD(divider)     (((divider / 2) - 1) << 24)
+
+/// Calculates the value of the DATLEN field of the Transmit Frame Mode Register
+/// of an SSC interface, given the number of bits in one sample.
+#define SSC_DATLEN(bits)        (bits - 1)
+
+/// Calculates the value of the DATNB field of the Transmit Frame Mode Register
+/// of an SSC interface, given the number of samples in one frame.
+#define SSC_DATNB(samples)      ((samples -1) << 8)
+
+/// Calculates the value of the FSLEN field of the Transmit Frame Mode Register
+/// of an SSC interface, given the number of transmit clock periods that the 
+/// frame sync signal should take.
+#define SSC_FSLEN(periods)      ((periods - 1) << 16)
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+//         Exported functions
+//------------------------------------------------------------------------------
+extern void SSC_Configure(AT91S_SSC *ssc,
+                                 unsigned int id,
+                                 unsigned int bitRate,
+                                 unsigned int masterClock);
+extern void SSC_ConfigureTransmitter(AT91S_SSC *ssc,
+                                            unsigned int tcmr,
+                                            unsigned int tfmr);
+extern void SSC_ConfigureReceiver(AT91S_SSC *ssc,
+                                         unsigned int rcmr,
+                                         unsigned int rfmr);
+
+extern void SSC_EnableTransmitter(AT91S_SSC *ssc);
+extern void SSC_DisableTransmitter(AT91S_SSC *ssc);
+extern void SSC_EnableReceiver(AT91S_SSC *ssc);
+extern void SSC_DisableReceiver(AT91S_SSC *ssc);
+
+extern void SSC_EnableInterrupts(AT91S_SSC *ssc, unsigned int sources);
+extern void SSC_DisableInterrupts(AT91S_SSC *ssc, unsigned int sources);
+
+extern void SSC_Write(AT91S_SSC *ssc, unsigned int frame);
+extern unsigned char SSC_WriteBuffer(AT91S_SSC *ssc,
+                                            void *buffer,
+                                            unsigned int length);
+extern unsigned int SSC_Read(AT91S_SSC *ssc);
+extern unsigned char SSC_ReadBuffer(AT91S_SSC *ssc,
+                                           void *buffer,
+                                           unsigned int length);
+
+#endif //#ifndef SSC_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/supc/supc.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/supc/supc.c
new file mode 100644
index 0000000..b63194c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/supc/supc.c
@@ -0,0 +1,223 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "supc.h"
+#include 
+#include 
+
+//------------------------------------------------------------------------------
+//         Local definitions
+//------------------------------------------------------------------------------
+
+/// Key value for the SUPC_MR register.
+#define SUPC_KEY            ((unsigned int) (0xA5 << 24))
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Enables the SLCD power supply.
+/// \param internal  If 1, the power supply is configured as internal; otherwise
+///                  it is set at external.
+//------------------------------------------------------------------------------
+void SUPC_EnableSlcd(unsigned char internal)
+{
+    if (internal) {
+
+         AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_LCDMODE) | AT91C_SUPC_LCDMODE_INTERNAL;
+    }
+    else {
+
+        AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_LCDMODE) | AT91C_SUPC_LCDMODE_EXTERNAL;
+    }
+    while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_LCDS) != AT91C_SUPC_LCDS);
+}
+
+//------------------------------------------------------------------------------
+/// Disables the SLCD power supply.
+//------------------------------------------------------------------------------
+void SUPC_DisableSlcd(void)
+{
+    AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_LCDMODE);
+    while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_LCDS) == AT91C_SUPC_LCDS);
+}
+
+//------------------------------------------------------------------------------
+/// Sets the output voltage of the SLCD charge pump.
+/// \param voltage  Output voltage.
+//------------------------------------------------------------------------------
+void SUPC_SetSlcdVoltage(unsigned int voltage)
+{
+    SANITY_CHECK((voltage & ~AT91C_SUPC_LCDOUT) == 0);
+    AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_LCDOUT) | voltage;
+}
+
+#if !defined(__ICCARM__)
+__attribute__ ((section (".ramfunc"))) // GCC
+#endif
+//------------------------------------------------------------------------------
+/// Enables the flash power supply with the given wake-up setting.
+/// \param time  Wake-up time.
+//------------------------------------------------------------------------------
+void SUPC_EnableFlash(unsigned int time)
+{
+    AT91C_BASE_SUPC->SUPC_FWUTR = time;
+    AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | AT91C_BASE_SUPC->SUPC_MR | AT91C_SUPC_FLASHON;
+    while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_FLASHS) != AT91C_SUPC_FLASHS);
+}
+
+#if !defined(__ICCARM__)
+__attribute__ ((section (".ramfunc"))) // GCC
+#endif
+//------------------------------------------------------------------------------
+/// Disables the flash power supply.
+//------------------------------------------------------------------------------
+void SUPC_DisableFlash(void)
+{
+    AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_FLASHON);
+    while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_FLASHS) == AT91C_SUPC_FLASHS);
+}
+
+//------------------------------------------------------------------------------
+/// Sets the voltage regulator output voltage.
+/// \param voltage  Voltage to set.
+//------------------------------------------------------------------------------
+void SUPC_SetVoltageOutput(unsigned int voltage)
+{
+    SANITY_CHECK((voltage & ~AT91C_SUPC_VRVDD) == 0);
+    AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_VRVDD) | voltage;
+}
+
+//------------------------------------------------------------------------------
+/// Puts the voltage regulator in deep mode.
+//------------------------------------------------------------------------------
+void SUPC_EnableDeepMode(void)
+{
+    AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | AT91C_BASE_SUPC->SUPC_MR | AT91C_SUPC_VRDEEP;
+}
+
+//------------------------------------------------------------------------------
+/// Puts the voltage regulator in normal mode.
+//------------------------------------------------------------------------------
+void SUPC_DisableDeepMode(void)
+{
+    AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_VRDEEP);
+}
+
+//-----------------------------------------------------------------------------
+/// Enables the backup SRAM power supply, so its data is saved while the device
+/// is in backup mode.
+//-----------------------------------------------------------------------------
+void SUPC_EnableSram(void)
+{
+    AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | AT91C_BASE_SUPC->SUPC_MR | AT91C_SUPC_SRAMON;
+}
+
+//-----------------------------------------------------------------------------
+/// Disables the backup SRAM power supply.
+//-----------------------------------------------------------------------------
+void SUPC_DisableSram(void)
+{
+    AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_SRAMON);
+}
+
+//-----------------------------------------------------------------------------
+/// Enables the RTC power supply.
+//-----------------------------------------------------------------------------
+void SUPC_EnableRtc(void)
+{
+    AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | AT91C_BASE_SUPC->SUPC_MR | AT91C_SUPC_RTCON;
+    while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_RTS) != AT91C_SUPC_RTS);
+}
+
+//-----------------------------------------------------------------------------
+/// Disables the RTC power supply.
+//-----------------------------------------------------------------------------
+void SUPC_DisableRtc(void)
+{
+    AT91C_BASE_SUPC->SUPC_MR = SUPC_KEY | (AT91C_BASE_SUPC->SUPC_MR & ~AT91C_SUPC_RTCON);
+    while ((AT91C_BASE_SUPC->SUPC_SR & AT91C_SUPC_RTS) == AT91C_SUPC_RTS);
+}
+
+//-----------------------------------------------------------------------------
+/// Sets the BOD sampling mode (or disables it).
+/// \param mode  BOD sampling mode.
+//-----------------------------------------------------------------------------
+void SUPC_SetBodSampling(unsigned int mode)
+{
+    SANITY_CHECK((mode & ~AT91C_SUPC_BODSMPL) == 0);
+    AT91C_BASE_SUPC->SUPC_BOMR &= ~AT91C_SUPC_BODSMPL;
+    AT91C_BASE_SUPC->SUPC_BOMR |= mode;
+}
+
+//------------------------------------------------------------------------------
+/// Disables the voltage regulator, which makes the device enter backup mode.
+//------------------------------------------------------------------------------
+void SUPC_DisableVoltageRegulator(void)
+{
+    AT91C_BASE_SUPC->SUPC_CR = SUPC_KEY | AT91C_SUPC_VROFF;
+    while (1);
+}
+
+//------------------------------------------------------------------------------
+/// Shuts the device down so it enters Off mode.
+//------------------------------------------------------------------------------
+void SUPC_Shutdown(void)
+{
+    AT91C_BASE_SUPC->SUPC_CR = SUPC_KEY | AT91C_SUPC_SHDW;
+    while (1);
+}
+
+//------------------------------------------------------------------------------
+/// Sets the wake-up sources when in backup mode.
+/// \param sources  Wake-up sources to enable.
+//------------------------------------------------------------------------------
+void SUPC_SetWakeUpSources(unsigned int sources)
+{
+    SANITY_CHECK((sources & ~0x0000000B) == 0);
+    AT91C_BASE_SUPC->SUPC_WUMR &= ~0x0000000B;
+    AT91C_BASE_SUPC->SUPC_WUMR |= sources;
+}
+
+//------------------------------------------------------------------------------
+/// Sets the wake-up inputs when in backup mode.
+/// \param inputs  Wake up inputs to enable.
+//------------------------------------------------------------------------------
+void SUPC_SetWakeUpInputs(unsigned int inputs)
+{
+    SANITY_CHECK((inputs & ~0xFFFF) == 0);
+    AT91C_BASE_SUPC->SUPC_WUIR &= ~0xFFFF;
+    AT91C_BASE_SUPC->SUPC_WUIR |= inputs;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/supc/supc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/supc/supc.h
new file mode 100644
index 0000000..f90df93
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/supc/supc.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef SUPC_H
+#define SUPC_H
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+extern void SUPC_EnableSlcd(unsigned char internal);
+
+extern void SUPC_DisableSlcd(void);
+
+extern void SUPC_SetSlcdVoltage(unsigned int voltage);
+
+extern
+#ifdef __ICCARM__
+__ramfunc // IAR
+#endif
+void SUPC_EnableFlash(unsigned int time);
+
+extern
+#ifdef __ICCARM__
+__ramfunc // IAR
+#endif
+void SUPC_DisableFlash(void);
+
+extern void SUPC_SetVoltageOutput(unsigned int voltage);
+
+extern void SUPC_EnableDeepMode(void);
+
+extern void SUPC_EnableSram(void);
+
+extern void SUPC_DisableSram(void);
+
+extern void SUPC_EnableRtc(void);
+
+extern void SUPC_DisableRtc(void);
+
+extern void SUPC_SetBodSampling(unsigned int mode);
+
+extern void SUPC_DisableDeepMode(void);
+
+extern void SUPC_DisableVoltageRegulator(void);
+
+extern void SUPC_Shutdown(void);
+
+extern void SUPC_SetWakeUpSources(unsigned int sources);
+
+extern void SUPC_SetWakeUpInputs(unsigned int inputs);
+
+#endif //#ifndef SUPC_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/tc/tc.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/tc/tc.c
new file mode 100644
index 0000000..2cce960
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/tc/tc.c
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "tc.h"
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Configures a Timer Counter to operate in the given mode. Timer is stopped
+/// after configuration and must be restarted with TC_Start().
+/// to obtain the target frequency.
+/// \param pTc  Pointer to an AT91S_TC instance.
+/// \param mode  Operating mode.
+//------------------------------------------------------------------------------
+void TC_Configure(AT91S_TC *pTc, unsigned int mode)
+{
+    // Disable TC clock
+    pTc->TC_CCR = AT91C_TC_CLKDIS;
+
+    // Disable interrupts
+    pTc->TC_IDR = 0xFFFFFFFF;
+
+    // Clear status register
+    pTc->TC_SR;
+
+    // Set mode
+    pTc->TC_CMR = mode;
+}
+
+//------------------------------------------------------------------------------
+/// Starts the timer clock.
+/// \param pTc  Pointer to an AT91S_TC instance.
+//------------------------------------------------------------------------------
+void TC_Start(AT91S_TC *pTc)
+{
+    pTc->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+}
+
+//------------------------------------------------------------------------------
+/// Stops the timer clock.
+/// \param pTc  Pointer to an AT91S_TC instance.
+//------------------------------------------------------------------------------
+void TC_Stop(AT91S_TC *pTc)
+{
+    pTc->TC_CCR = AT91C_TC_CLKDIS;
+}
+
+//------------------------------------------------------------------------------
+/// Finds the best MCK divisor given the timer frequency and MCK. The result
+/// is guaranteed to satisfy the following equation:
+///   (MCK / (DIV * 65536)) <= freq <= (MCK / DIV)
+/// with DIV being the highest possible value.
+/// Returns 1 if a divisor could be found; otherwise returns 0.
+/// \param freq  Desired timer frequency.
+/// \param mck  Master clock frequency.
+/// \param div  Divisor value.
+/// \param tcclks  TCCLKS field value for divisor.
+//------------------------------------------------------------------------------
+unsigned char TC_FindMckDivisor(
+    unsigned int freq,
+    unsigned int mck,
+    unsigned int *div,
+    unsigned int *tcclks)
+{
+    const unsigned int divisors[5] = {2, 8, 32, 128,
+#if defined(at91sam9260) || defined(at91sam9261) || defined(at91sam9263) \
+    || defined(at91sam9xe) || defined(at91sam9rl64) || defined(at91cap9)
+        BOARD_MCK / 32768};
+#else
+        1024};
+#endif
+    unsigned int index = 0;
+
+    // Satisfy lower bound
+    while (freq < ((mck / divisors[index]) / 65536)) {
+
+        index++;
+
+        // If no divisor can be found, return 0
+        if (index == 5) {
+
+            return 0;
+        }
+    }
+
+    // Try to maximise DIV while satisfying upper bound
+    while (index < 4) {
+
+        if (freq > (mck / divisors[index + 1])) {
+
+            break;
+        }
+        index++;
+    }
+
+    // Store results
+    if (div) {
+
+        *div = divisors[index];
+    }
+    if (tcclks) {
+
+        *tcclks = index;
+    }
+
+    return 1;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/tc/tc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/tc/tc.h
new file mode 100644
index 0000000..5e4e3ef
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/tc/tc.h
@@ -0,0 +1,60 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef TC_H
+#define TC_H
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include 
+
+#if !defined(AT91C_ID_TC0) && defined(AT91C_ID_TC012)
+    #define AT91C_ID_TC0 AT91C_ID_TC012
+#endif
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+extern void TC_Configure(AT91S_TC *pTc, unsigned int mode);
+
+extern void TC_Start(AT91S_TC *pTc);
+
+extern void TC_Stop(AT91S_TC *pTc);
+
+extern unsigned char TC_FindMckDivisor(
+    unsigned int freq,
+    unsigned int mck,
+    unsigned int *div,
+    unsigned int *tcclks);
+
+#endif //#ifndef TC_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/tdes/tdes.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/tdes/tdes.c
new file mode 100644
index 0000000..558d3d8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/tdes/tdes.c
@@ -0,0 +1,232 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef trace_LEVEL
+    #define trace_LEVEL     1
+#endif
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "tdes.h"
+#include 
+#include 
+#include 
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Configures the triple-DES peripheral to cipher/decipher, use single-DES or
+/// triple-DES, use two or three keys (when in triple-DES mode), start manually,
+/// automatically or via the PDC and use the given operating mode (ECB, CBC,
+/// CFB or OFB).
+/// \param cipher  Encrypts if 1, decrypts if 0.
+/// \param tdesmod  Single- or triple-DES mode.
+/// \param keymod  Use two or three keys (must be 0 in single-DES mode).
+/// \param smod  Start mode.
+/// \param opmod  Encryption/decryption mode.
+//------------------------------------------------------------------------------
+void TDES_Configure(
+    unsigned char cipher,
+    unsigned int tdesmod,
+    unsigned int keymod,
+    unsigned int smod,
+    unsigned int opmod)
+{
+    trace_LOG(trace_DEBUG, "-D- TDES_Configure()\n\r");
+    SANITY_CHECK((cipher & 0xFFFFFFFE) == 0);
+    SANITY_CHECK((tdesmod & 0xFFFFFFFD) == 0);
+    SANITY_CHECK((keymod & 0xFFFFFFEF) == 0);
+    SANITY_CHECK((smod & 0xFFFFFCFF) == 0);
+    SANITY_CHECK((opmod & 0xFFFFCFFF) == 0);
+
+    // Reset peripheral
+    AT91C_BASE_TDES->TDES_CR = AT91C_TDES_SWRST;
+
+    // Configure mode register
+    AT91C_BASE_TDES->TDES_MR = cipher | tdesmod | keymod | smod | opmod;
+}
+
+//------------------------------------------------------------------------------
+/// Starts the encryption or decryption process if the TDES peripheral is
+/// configured in manual or PDC mode.
+//------------------------------------------------------------------------------
+void TDES_Start(void)
+{
+    trace_LOG(trace_DEBUG, "-D- TDES_Start()\n\r");
+    SANITY_CHECK(((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_SMOD) == AT91C_TDES_SMOD_MANUAL)
+                 || ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_SMOD) == AT91C_TDES_SMOD_PDC));
+
+    // Manual mode
+    if ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_SMOD) == AT91C_TDES_SMOD_MANUAL) {
+
+        AT91C_BASE_TDES->TDES_CR = AT91C_TDES_START;
+    }
+    // PDC mode
+    else {
+
+        AT91C_BASE_TDES->TDES_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Returns the current status register value of the TDES peripheral.
+//------------------------------------------------------------------------------
+unsigned int TDES_GetStatus(void)
+{
+    trace_LOG(trace_DEBUG, "-D- TDES_GetStatus()\n\r");
+
+    return AT91C_BASE_TDES->TDES_ISR;
+}
+
+//------------------------------------------------------------------------------
+/// Sets the 64-bits keys (one, two or three depending on the configuration)
+/// that shall be used by the TDES algorithm.
+/// \param pKey1  Pointer to key #1.
+/// \param pKey2  Pointer to key #2 (shall be 0 in single-DES mode).
+/// \param pKey3  Pointer to key #3 (shall be 0 when using two keys).
+//------------------------------------------------------------------------------
+void TDES_SetKeys(
+    const unsigned int *pKey1,
+    const unsigned int *pKey2,
+    const unsigned int *pKey3)
+{
+    trace_LOG(trace_DEBUG, "-D- TDES_SetKeys()\n\r");
+    SANITY_CHECK(pKey1);
+    SANITY_CHECK((pKey2 && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == AT91C_TDES_TDESMOD))
+                 || (!pKey2 && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == 0)));
+    SANITY_CHECK((pKey3
+                  && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == AT91C_TDES_TDESMOD)
+                  && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_KEYMOD) == 0))
+                 ||
+                 (!pKey3
+                  && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == AT91C_TDES_TDESMOD)
+                  && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_KEYMOD) == AT91C_TDES_KEYMOD))
+                 ||
+                 (!pKey3
+                  && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_TDESMOD) == 0)
+                  && ((AT91C_BASE_TDES->TDES_MR & AT91C_TDES_KEYMOD) == 0)));
+
+    // Write key #1
+    if (pKey1) {
+
+        AT91C_BASE_TDES->TDES_KEY1WxR[0] = pKey1[0];
+        AT91C_BASE_TDES->TDES_KEY1WxR[1] = pKey1[1];
+    }
+
+    // Write key #2
+    if (pKey1) {
+
+        AT91C_BASE_TDES->TDES_KEY2WxR[0] = pKey2[0];
+        AT91C_BASE_TDES->TDES_KEY2WxR[1] = pKey2[1];
+    }
+
+    // Write key #2
+    if (pKey1) {
+
+        AT91C_BASE_TDES->TDES_KEY3WxR[0] = pKey3[0];
+        AT91C_BASE_TDES->TDES_KEY3WxR[1] = pKey3[1];
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Sets the input data to encrypt/decrypt using TDES.
+/// \param pInput  Pointer to the 64-bits input data.
+//------------------------------------------------------------------------------
+void TDES_SetInputData(const unsigned int *pInput)
+{
+    trace_LOG(trace_DEBUG, "-D- TDES_SetInputData()\n\r");
+    SANITY_CHECK(pInput);
+
+    AT91C_BASE_TDES->TDES_IDATAxR[0] = pInput[0];
+    AT91C_BASE_TDES->TDES_IDATAxR[1] = pInput[1];
+}
+
+//------------------------------------------------------------------------------
+/// Sets the input data buffer to encrypt/decrypt when in PDC mode.
+/// \param pInput  Pointer to the input data.
+/// \param size  Size of buffer in bytes.
+//------------------------------------------------------------------------------
+void TDES_SetInputBuffer(const unsigned int *pInput, unsigned int size)
+{
+    trace_LOG(trace_DEBUG, "-D- TDES_SetInputBuffer()\n\r");
+    SANITY_CHECK(pInput);
+    SANITY_CHECK((size > 0) && ((size % 8) == 0));
+
+    AT91C_BASE_TDES->TDES_TPR = (unsigned int) pInput;
+    AT91C_BASE_TDES->TDES_TCR = size / 4;
+}
+
+//------------------------------------------------------------------------------
+/// Stores the output data from the last TDES operation into the given 64-bits
+/// buffers.
+/// \param pOutput  Pointer to a 64-bits output buffer.
+//------------------------------------------------------------------------------
+void TDES_GetOutputData(unsigned int *pOutput)
+{
+    trace_LOG(trace_DEBUG, "-D- TDES_GetOutputData()\n\r");
+    SANITY_CHECK(pOutput);
+
+    pOutput[0] = AT91C_BASE_TDES->TDES_ODATAxR[0];
+    pOutput[1] = AT91C_BASE_TDES->TDES_ODATAxR[1];
+}
+
+//------------------------------------------------------------------------------
+/// Sets the output buffer which will receive the encrypted/decrypted data when
+/// using the PDC.
+/// \param pOutput  Pointer to the output data.
+/// \param size  Size of buffer in bytes.
+//------------------------------------------------------------------------------
+void TDES_SetOutputBuffer(unsigned int *pOutput, unsigned int size)
+{
+    trace_LOG(trace_DEBUG, "-D- TDES_SetOutputBuffer()\n\r");
+    SANITY_CHECK(pOutput);
+    SANITY_CHECK((size > 0) && ((size % 8) == 0));
+
+    AT91C_BASE_TDES->TDES_RPR = (unsigned int) pOutput;
+    AT91C_BASE_TDES->TDES_RCR = size / 4;
+}
+
+//------------------------------------------------------------------------------
+/// Sets the initialization vector to use when the TDES algorithm is configured
+/// in a chained block mode (CBC, CFB or OFB).
+/// \param pVector  Pointer to the 64-bits vector.
+//------------------------------------------------------------------------------
+void TDES_SetVector(const unsigned int *pVector)
+{
+    trace_LOG(trace_DEBUG, "-D- TDES_SetVector()\n\r");
+    SANITY_CHECK(pVector);
+
+    AT91C_BASE_TDES->TDES_IVxR[0] = pVector[0];
+    AT91C_BASE_TDES->TDES_IVxR[1] = pVector[1];
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/tdes/tdes.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/tdes/tdes.h
new file mode 100644
index 0000000..b73a634
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/tdes/tdes.h
@@ -0,0 +1,63 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef TDES_H
+#define TDES_H
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+extern void TDES_Configure(
+    unsigned char cipher,
+    unsigned int tdesmod,
+    unsigned int keymod,
+    unsigned int smod,
+    unsigned int opmod);
+
+extern void TDES_Start(void);
+
+extern unsigned int TDES_GetStatus(void);
+
+extern void TDES_SetKeys(
+    const unsigned int *pKey1,
+    const unsigned int *pKey2,
+    const unsigned int *pKey3);
+
+extern void TDES_SetInputData(const unsigned int *pInput);
+
+extern void TDES_SetInputBuffer(const unsigned int *pInput, unsigned int size);
+
+extern void TDES_GetOutputData(unsigned int *pOutput);
+
+extern void TDES_SetOutputBuffer(unsigned int *pOutput, unsigned int size);
+
+extern void TDES_SetVector(const unsigned int *pVector);
+
+#endif //#ifndef TDES_H
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/twi/twi.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/twi/twi.c
new file mode 100644
index 0000000..4312e7b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/twi/twi.c
@@ -0,0 +1,281 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef trace_LEVEL
+    #define trace_LEVEL  1
+#endif
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "twi.h"
+#include 
+#include 
+#include 
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Configures a TWI peripheral to operate in master mode, at the given
+/// frequency (in Hz). The duty cycle of the TWI clock is set to 50%.
+/// \param pTwi  Pointer to an AT91S_TWI instance.
+/// \param twck  Desired TWI clock frequency.
+/// \param mck  Master clock frequency.
+//------------------------------------------------------------------------------
+void TWI_Configure(AT91S_TWI *pTwi, unsigned int twck, unsigned int mck)
+{
+    unsigned int ckdiv = 0;
+    unsigned int cldiv;
+    unsigned char ok = 0;
+
+    trace_LOG(trace_DEBUG, "-D- TWI_Configure()\n\r");
+    SANITY_CHECK(pTwi);
+
+    // Reset the TWI
+    pTwi->TWI_CR = AT91C_TWI_SWRST;
+
+    // Set master mode
+    pTwi->TWI_CR = AT91C_TWI_MSEN;
+
+    // Configure clock
+    while (!ok) {
+        
+        cldiv = ((mck / (2 * twck)) - 3) / power(2, ckdiv);
+        if (cldiv <= 255) {
+
+            ok = 1;
+        }
+        else {
+
+            ckdiv++;
+        }
+    }
+
+    ASSERT(ckdiv < 8, "-F- Cannot find valid TWI clock parameters\n\r");
+    trace_LOG(trace_INFO, "-D- Using CKDIV = %u and CLDIV/CHDIV = %u\n\r", ckdiv, cldiv);
+    pTwi->TWI_CWGR = (ckdiv << 16) | (cldiv << 8) | cldiv;
+}
+
+//------------------------------------------------------------------------------
+/// Sends a STOP condition on the TWI.
+/// \param pTwi  Pointer to an AT91S_TWI instance.
+//------------------------------------------------------------------------------
+void TWI_Stop(AT91S_TWI *pTwi)
+{
+    SANITY_CHECK(pTwi);
+
+    pTwi->TWI_CR = AT91C_TWI_STOP;
+}
+
+//------------------------------------------------------------------------------
+/// Starts a read operation on the TWI bus with the specified slave, and returns
+/// immediately. Data must then be read using TWI_ReadByte() whenever a byte is
+/// available (poll using TWI_ByteReceived()).
+/// \param pTwi  Pointer to an AT91S_TWI instance.
+/// \param address  Slave address on the bus.
+/// \param iaddress  Optional internal address bytes.
+/// \param isize  Number of internal address bytes.
+//-----------------------------------------------------------------------------
+void TWI_StartRead(
+    AT91S_TWI *pTwi,
+    unsigned char address,
+    unsigned int iaddress,
+    unsigned char isize)
+{
+    trace_LOG(trace_DEBUG, "-D- TWI_StartRead()\n\r");
+    SANITY_CHECK(pTwi);
+    SANITY_CHECK((address & 0x80) == 0);
+    SANITY_CHECK((iaddress & 0xFF000000) == 0);
+    SANITY_CHECK(isize < 4);
+
+    // Set slave address and number of internal address bytes
+    pTwi->TWI_MMR = (isize << 8) | AT91C_TWI_MREAD | (address << 16);
+
+    // Set internal address bytes
+    pTwi->TWI_IADR = iaddress;
+
+    // Send START condition
+    pTwi->TWI_CR = AT91C_TWI_START;
+}
+
+//-----------------------------------------------------------------------------
+/// Reads a byte from the TWI bus. The read operation must have been started
+/// using TWI_StartRead() and a byte must be available (check with
+/// TWI_ByteReceived()).
+/// Returns the byte read.
+/// \param pTwi  Pointer to an AT91S_TWI instance.
+//-----------------------------------------------------------------------------
+unsigned char TWI_ReadByte(AT91S_TWI *pTwi)
+{
+    SANITY_CHECK(pTwi);
+
+    return pTwi->TWI_RHR;
+}
+
+//-----------------------------------------------------------------------------
+/// Sends a byte of data to one of the TWI slaves on the bus. This function
+/// must be called once before TWI_StartWrite() with the first byte of data
+/// to send, then it shall be called repeatedly after that to send the
+/// remaining bytes.
+/// \param pTwi  Pointer to an AT91S_TWI instance.
+/// \param byte  Byte to send.
+//-----------------------------------------------------------------------------
+void TWI_WriteByte(AT91S_TWI *pTwi, unsigned char byte)
+{
+    SANITY_CHECK(pTwi);
+
+    pTwi->TWI_THR = byte;
+}
+
+//-----------------------------------------------------------------------------
+/// Starts a write operation on the TWI to access the selected slave, then
+/// returns immediately. A byte of data must be provided to start the write;
+/// other bytes are written next.
+/// \param pTwi  Pointer to an AT91S_TWI instance.
+/// \param address  Address of slave to acccess on the bus.
+/// \param iaddress  Optional slave internal address.
+/// \param isize  Number of internal address bytes.
+/// \param byte  First byte to send.
+//-----------------------------------------------------------------------------
+void TWI_StartWrite(
+    AT91S_TWI *pTwi,
+    unsigned char address,
+    unsigned int iaddress,
+    unsigned char isize,
+    unsigned char byte)
+{
+    trace_LOG(trace_DEBUG, "-D- TWI_StartWrite()\n\r");
+    SANITY_CHECK(pTwi);
+    SANITY_CHECK((address & 0x80) == 0);
+    SANITY_CHECK((iaddress & 0xFF000000) == 0);
+    SANITY_CHECK(isize < 4);
+
+    // Set slave address and number of internal address bytes
+    pTwi->TWI_MMR = (isize << 8) | (address << 16);
+
+    // Set internal address bytes
+    pTwi->TWI_IADR = iaddress;
+
+    // Write first byte to send
+    TWI_WriteByte(pTwi, byte);
+}
+
+//-----------------------------------------------------------------------------
+/// Returns 1 if a byte has been received and can be read on the given TWI
+/// peripheral; otherwise, returns 0. This function resets the status register
+/// of the TWI.
+/// \param pTwi  Pointer to an AT91S_TWI instance.
+//-----------------------------------------------------------------------------
+unsigned char TWI_ByteReceived(AT91S_TWI *pTwi)
+{
+    return ((pTwi->TWI_SR & AT91C_TWI_RXRDY) == AT91C_TWI_RXRDY);
+}
+
+//-----------------------------------------------------------------------------
+/// Returns 1 if a byte has been sent, so another one can be stored for
+/// transmission; otherwise returns 0. This function clears the status register
+/// of the TWI.
+/// \param pTwi  Pointer to an AT91S_TWI instance.
+//-----------------------------------------------------------------------------
+unsigned char TWI_ByteSent(AT91S_TWI *pTwi)
+{
+    return ((pTwi->TWI_SR & AT91C_TWI_TXRDY) == AT91C_TWI_TXRDY);
+}
+
+//-----------------------------------------------------------------------------
+/// Returns 1 if the current transmission is complete (the STOP has been sent);
+/// otherwise returns 0.
+/// \param pTwi  Pointer to an AT91S_TWI instance.
+//-----------------------------------------------------------------------------
+unsigned char TWI_TransferComplete(AT91S_TWI *pTwi)
+{
+    return ((pTwi->TWI_SR & AT91C_TWI_TXCOMP) == AT91C_TWI_TXCOMP);
+}
+
+//-----------------------------------------------------------------------------
+/// Enables the selected interrupts sources on a TWI peripheral.
+/// \param pTwi  Pointer to an AT91S_TWI instance.
+/// \param sources  Bitwise OR of selected interrupt sources.
+//-----------------------------------------------------------------------------
+void TWI_EnableIt(AT91S_TWI *pTwi, unsigned int sources)
+{
+    SANITY_CHECK(pTwi);
+    SANITY_CHECK((sources & 0xFFFFFEF8) == 0);
+
+    pTwi->TWI_IER = sources;
+}
+
+//-----------------------------------------------------------------------------
+/// Disables the selected interrupts sources on a TWI peripheral.
+/// \param pTwi  Pointer to an AT91S_TWI instance.
+/// \param sources  Bitwise OR of selected interrupt sources.
+//-----------------------------------------------------------------------------
+void TWI_DisableIt(AT91S_TWI *pTwi, unsigned int sources)
+{
+    SANITY_CHECK(pTwi);
+    SANITY_CHECK((sources & 0xFFFFFEF8) == 0);
+
+    pTwi->TWI_IDR = sources;
+}
+
+//-----------------------------------------------------------------------------
+/// Returns the current status register of the given TWI peripheral. This
+/// resets the internal value of the status register, so further read may yield
+/// different values.
+/// \param pTwi  Pointer to an AT91S_TWI instance.
+//-----------------------------------------------------------------------------
+unsigned int TWI_GetStatus(AT91S_TWI *pTwi)
+{
+    SANITY_CHECK(pTwi);
+
+    return pTwi->TWI_SR;
+}
+
+//-----------------------------------------------------------------------------
+/// Returns the current status register of the given TWI peripheral, but
+/// masking interrupt sources which are not currently enabled.
+/// This resets the internal value of the status register, so further read may
+/// yield different values.
+/// \param pTwi  Pointer to an AT91S_TWI instance.
+//-----------------------------------------------------------------------------
+unsigned int TWI_GetMaskedStatus(AT91S_TWI *pTwi)
+{
+    unsigned int status;
+    
+    SANITY_CHECK(pTwi);
+    
+    status = pTwi->TWI_SR;
+    status &= pTwi->TWI_IMR;
+
+    return status;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/twi/twi.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/twi/twi.h
new file mode 100644
index 0000000..401126e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/twi/twi.h
@@ -0,0 +1,108 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef TWI_H
+#define TWI_H
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include 
+
+//------------------------------------------------------------------------------
+//         Global definitions
+//------------------------------------------------------------------------------
+
+// Missing AT91C_TWI_TXRDY definition.
+#ifndef AT91C_TWI_TXRDY
+    #define AT91C_TWI_TXRDY   AT91C_TWI_TXRDY_MASTER
+#endif
+
+// Missing AT91C_TWI_TXCOMP definition.
+#ifndef AT91C_TWI_TXCOMP
+    #define AT91C_TWI_TXCOMP  AT91C_TWI_TXCOMP_MASTER
+#endif
+
+//------------------------------------------------------------------------------
+//         Global macros
+//------------------------------------------------------------------------------
+
+/// Returns 1 if the TXRDY bit (ready to transmit data) is set in the given
+/// status register value.
+#define TWI_STATUS_TXRDY(status) ((status & AT91C_TWI_TXRDY) == AT91C_TWI_TXRDY)
+
+/// Returns 1 if the RXRDY bit (ready to receive data) is set in the given
+/// status register value.
+#define TWI_STATUS_RXRDY(status) ((status & AT91C_TWI_RXRDY) == AT91C_TWI_RXRDY)
+
+/// Returns 1 if the TXCOMP bit (transfer complete) is set in the given
+/// status register value.
+#define TWI_STATUS_TXCOMP(status) ((status & AT91C_TWI_TXCOMP) == AT91C_TWI_TXCOMP)
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+extern void TWI_Configure(AT91S_TWI *pTwi, unsigned int twck, unsigned int mck);
+
+extern void TWI_Stop(AT91S_TWI *pTwi);
+
+extern void TWI_StartRead(
+    AT91S_TWI *pTwi,
+    unsigned char address,
+    unsigned int iaddress,
+    unsigned char isize);
+
+extern unsigned char TWI_ReadByte(AT91S_TWI *pTwi);
+
+extern void TWI_WriteByte(AT91S_TWI *pTwi, unsigned char byte);
+
+extern void TWI_StartWrite(
+    AT91S_TWI *pTwi,
+    unsigned char address,
+    unsigned int iaddress,
+    unsigned char isize,
+    unsigned char byte);
+
+extern unsigned char TWI_ByteReceived(AT91S_TWI *pTwi);
+
+extern unsigned char TWI_ByteSent(AT91S_TWI *pTwi);
+
+extern unsigned char TWI_TransferComplete(AT91S_TWI *pTwi);
+
+extern void TWI_EnableIt(AT91S_TWI *pTwi, unsigned int sources);
+
+extern void TWI_DisableIt(AT91S_TWI *pTwi, unsigned int sources);
+
+extern unsigned int TWI_GetStatus(AT91S_TWI *pTwi);
+
+extern unsigned int TWI_GetMaskedStatus(AT91S_TWI *pTwi);
+
+#endif //#ifndef TWI_H
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/usart/usart.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/usart/usart.c
new file mode 100644
index 0000000..35e08e0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/usart/usart.c
@@ -0,0 +1,259 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "usart.h"
+#include 
+
+//------------------------------------------------------------------------------
+//         Exported functions
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+/// Configures an USART peripheral with the specified parameters.
+/// \param usart  Pointer to the USART peripheral to configure.
+/// \param mode  Desired value for the USART mode register (see the datasheet).
+/// \param baudrate  Baudrate at which the USART should operate (in Hz).
+/// \param masterClock  Frequency of the system master clock (in Hz).
+//------------------------------------------------------------------------------
+void USART_Configure(AT91S_USART *usart,
+                            unsigned int mode,
+                            unsigned int baudrate,
+                            unsigned int masterClock)
+{
+    // Reset and disable receiver & transmitter
+    usart->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX
+                   | AT91C_US_RXDIS | AT91C_US_TXDIS;
+
+    // Configure mode
+    usart->US_MR = mode;
+
+    // Configure baudrate
+    // Asynchronous, no oversampling
+    if (((mode & AT91C_US_SYNC) == 0)
+        && ((mode & AT91C_US_OVER) == 0)) {
+    
+        usart->US_BRGR = (masterClock / baudrate) / 16;
+    }
+    // TODO other modes
+}
+
+//------------------------------------------------------------------------------
+/// Enables or disables the transmitter of an USART peripheral.
+/// \param usart  Pointer to an USART peripheral
+/// \param enabled  If true, the transmitter is enabled; otherwise it is
+///                 disabled.
+//------------------------------------------------------------------------------
+void USART_SetTransmitterEnabled(AT91S_USART *usart,
+                                        unsigned char enabled)
+{
+    if (enabled) {
+
+        usart->US_CR = AT91C_US_TXEN;
+    }
+    else {
+
+        usart->US_CR = AT91C_US_TXDIS;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Enables or disables the receiver of an USART peripheral
+/// \param usart  Pointer to an USART peripheral
+/// \param enabled  If true, the receiver is enabled; otherwise it is disabled.
+//------------------------------------------------------------------------------
+void USART_SetReceiverEnabled(AT91S_USART *usart,
+                                     unsigned char enabled)
+{
+    if (enabled) {
+
+        usart->US_CR = AT91C_US_RXEN;
+    }
+    else {
+
+        usart->US_CR = AT91C_US_RXDIS;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Sends one packet of data through the specified USART peripheral. This
+/// function operates synchronously, so it only returns when the data has been
+/// actually sent.
+/// \param usart  Pointer to an USART peripheral.
+/// \param data  Data to send including 9nth bit and sync field if necessary (in
+///              the same format as the US_THR register in the datasheet).
+/// \param timeOut  Time out value (0 = no timeout).
+//------------------------------------------------------------------------------
+void USART_Write(
+    AT91S_USART *usart,
+    unsigned short data,
+    volatile unsigned int timeOut)
+{
+    if (timeOut == 0) {
+
+        while ((usart->US_CSR & AT91C_US_TXEMPTY) == 0);
+    }
+    else {
+
+        while ((usart->US_CSR & AT91C_US_TXEMPTY) == 0) {
+
+            if (timeOut == 0) {
+
+                trace_LOG(trace_ERROR, "-E- USART_Write: Timed out.\n\r");
+                return;
+            }
+            timeOut--;
+        }
+    }
+
+    usart->US_THR = data;
+}
+
+//------------------------------------------------------------------------------
+/// Sends the contents of a data buffer through the specified USART peripheral.
+/// This function returns immediately (1 if the buffer has been queued, 0
+/// otherwise); poll the ENDTX and TXBUFE bits of the USART status register
+/// to check for the transfer completion.
+/// \param usart  Pointer to an USART peripheral.
+/// \param buffer  Pointer to the data buffer to send.
+/// \param size  Size of the data buffer (in bytes).
+//------------------------------------------------------------------------------
+unsigned char USART_WriteBuffer(
+    AT91S_USART *usart,
+    void *buffer,
+    unsigned int size)
+{
+    // Check if the first PDC bank is free
+    if ((usart->US_TCR == 0) && (usart->US_TNCR == 0)) {
+
+        usart->US_TPR = (unsigned int) buffer;
+        usart->US_TCR = size;
+        usart->US_PTCR = AT91C_PDC_TXTEN;
+
+        return 1;
+    }
+    // Check if the second PDC bank is free
+    else if (usart->US_TNCR == 0) {
+
+        usart->US_TNPR = (unsigned int) buffer;
+        usart->US_TNCR = size;
+
+        return 1;
+    }
+    else {
+
+        return 0;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Reads and return a packet of data on the specified USART peripheral. This
+/// function operates asynchronously, so it waits until some data has been
+/// received.
+/// \param usart  Pointer to an USART peripheral.
+/// \param timeOut  Time out value (0 -> no timeout).
+//------------------------------------------------------------------------------
+unsigned short USART_Read(
+    AT91S_USART *usart,
+    volatile unsigned int timeOut)
+{
+    if (timeOut == 0) {
+
+        while ((usart->US_CSR & AT91C_US_RXRDY) == 0);
+    }
+    else {
+
+        while ((usart->US_CSR & AT91C_US_RXRDY) == 0) {
+
+            if (timeOut == 0) {
+
+                trace_LOG(trace_ERROR, "-E- USART_Read: Timed out.\n\r");
+                return 0;
+            }
+            timeOut--;
+        }
+    }
+
+    return usart->US_RHR;
+}
+
+//------------------------------------------------------------------------------
+/// Reads data from an USART peripheral, filling the provided buffer until it
+/// becomes full. This function returns immediately with 1 if the buffer has
+/// been queued for transmission; otherwise 0.
+/// \param usart  Pointer to an USART peripheral.
+/// \param buffer  Pointer to the buffer where the received data will be stored.
+/// \param size  Size of the data buffer (in bytes).
+//------------------------------------------------------------------------------
+unsigned char USART_ReadBuffer(AT91S_USART *usart,
+                                      void *buffer,
+                                      unsigned int size)
+{
+    // Check if the first PDC bank is free
+    if ((usart->US_RCR == 0) && (usart->US_RNCR == 0)) {
+
+        usart->US_RPR = (unsigned int) buffer;
+        usart->US_RCR = size;
+        usart->US_PTCR = AT91C_PDC_RXTEN;
+
+        return 1;
+    }
+    // Check if the second PDC bank is free
+    else if (usart->US_RNCR == 0) {
+
+        usart->US_RNPR = (unsigned int) buffer;
+        usart->US_RNCR = size;
+
+        return 1;
+    }
+    else {
+
+        return 0;
+    }
+}
+
+//------------------------------------------------------------------------------
+/// Returns 1 if some data has been received and can be read from an USART;
+/// otherwise returns 0.
+/// \param usart  Pointer to an AT91S_USART instance.
+//------------------------------------------------------------------------------
+unsigned char USART_IsDataAvailable(AT91S_USART *usart)
+{
+    if ((usart->US_CSR & AT91C_US_RXRDY) != 0) {
+
+        return 1;
+    }
+    else {
+
+        return 0;
+    }
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/usart/usart.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/usart/usart.h
new file mode 100644
index 0000000..3150ec0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/peripherals/usart/usart.h
@@ -0,0 +1,112 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+/// \dir
+/// !Purpose
+/// 
+/// This module provides several definitions and methods for using an USART
+/// peripheral.
+///
+/// !Usage
+/// -# Enable the USART peripheral clock in the PMC.
+/// -# Enable the required USART PIOs (see pio.h).
+/// -# Configure the UART by calling USART_Configure.
+/// -# Enable the transmitter and/or the receiver of the USART using
+///    USART_SetTransmitterEnabled and USART_SetReceiverEnabled.
+/// -# Send data through the USART using the USART_Write and
+///    USART_WriteBuffer methods.
+/// -# Receive data from the USART using the USART_Read and
+///    USART_ReadBuffer functions; the availability of data can be polled
+///    with USART_IsDataAvailable.
+/// -# Disable the transmitter and/or the receiver of the USART with
+///    USART_SetTransmitterEnabled and USART_SetReceiverEnabled.
+//------------------------------------------------------------------------------
+
+#ifndef USART_H
+#define USART_H
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include 
+
+//------------------------------------------------------------------------------
+//         Definitions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \page "USART modes"
+/// This page lists several common operating modes for an USART peripheral.
+/// 
+/// !Modes
+/// - USART_MODE_ASYNCHRONOUS
+
+/// Basic asynchronous mode, i.e. 8 bits no parity.
+#define USART_MODE_ASYNCHRONOUS     (AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE)
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+//         Exported functions
+//------------------------------------------------------------------------------
+
+extern void USART_Configure(
+    AT91S_USART *usart,
+    unsigned int mode,
+    unsigned int baudrate,
+    unsigned int masterClock);
+
+extern void USART_SetTransmitterEnabled(AT91S_USART *usart, unsigned char enabled);
+
+extern void USART_SetReceiverEnabled(AT91S_USART *usart, unsigned char enabled);
+
+extern void USART_Write(
+    AT91S_USART *usart, 
+    unsigned short data, 
+    volatile unsigned int timeOut);
+
+extern unsigned char USART_WriteBuffer(
+    AT91S_USART *usart,
+    void *buffer,
+    unsigned int size);
+
+extern unsigned short USART_Read(
+    AT91S_USART *usart, 
+    volatile unsigned int timeOut);
+
+extern unsigned char USART_ReadBuffer(
+    AT91S_USART *usart,
+    void *buffer,
+    unsigned int size);
+
+extern unsigned char USART_IsDataAvailable(AT91S_USART *usart);
+
+#endif //#ifndef USART_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/utility/assert.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/utility/assert.h
new file mode 100644
index 0000000..bb491e2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/utility/assert.h
@@ -0,0 +1,90 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*
+    Title: Assert
+
+    About: Purpose
+        Definition of the ASSERT() macro, which is used for runtime condition
+        verifying.
+
+    About: Usage
+        1 - Use  in your code to check the value of function parameters,
+            return values, etc. *Warning:* the ASSERT condition must not have
+            any side-effect; otherwise, the program may not work properly
+            anymore when assertions are disabled.
+        2 - Use SANITY_CHECK to perform checks with a default error message
+            (outputs the file and line number where the error occured). This 
+            reduces memory overhead caused by assertion error strings.
+        3 - Initialize the  to see failed assertions at run-time.
+        4 - Disable assertions by defining the NOASSERT symbol at compilation
+            time.
+*/
+
+#ifndef ASSERT_H
+#define ASSERT_H
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include 
+
+//------------------------------------------------------------------------------
+//         Definitions
+//------------------------------------------------------------------------------
+/*
+    Macro: ASSERT
+        Check that the given condition is true, otherwise displays an error
+        message and stops the program execution.
+
+    Parameters:
+        condition - Condition to verify.
+        string - Formatted string to output if the condition fails.
+        ... - Additional arguments depending on the formatted string.
+*/
+#if !defined(NOASSERT) && !defined(NOTRACE)
+
+    //char sanityError[] = "Sanity check failed at %s:%d\n\r";
+
+    #define ASSERT(condition, ...)  { \
+        if (!(condition)) { \
+            printf(__VA_ARGS__); \
+            while (1); \
+        } \
+    }
+    #define SANITY_ERROR            "Sanity check failed at %s:%d\n\r"
+    #define SANITY_CHECK(condition) ASSERT(condition, SANITY_ERROR, __FILE__, __LINE__)
+#else
+    #define ASSERT(...)
+    #define SANITY_CHECK(...)
+#endif
+
+#endif //#ifndef ASSERT_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/utility/led.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/utility/led.c
new file mode 100644
index 0000000..71af371
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/utility/led.c
@@ -0,0 +1,187 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*
+    Title: LED implementation
+
+    About: Purpose
+        Implementation of LED-related functionalities.
+*/
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "led.h"
+#include 
+#include 
+
+//------------------------------------------------------------------------------
+//         Internal variables
+//------------------------------------------------------------------------------
+
+#ifdef PINS_LEDS
+static const Pin pinsLeds[] = {PINS_LEDS};
+static const unsigned int numLeds = PIO_LISTSIZE(pinsLeds);
+#endif
+
+//------------------------------------------------------------------------------
+//         Exported functions
+//------------------------------------------------------------------------------
+/*
+    Function: LED_Configure
+        Configures the pin associated with the given LED number.
+
+    Parameters:
+        led - Number of the LED to configure.
+
+    Returns:
+        1 if the LED exists and has been configured; otherwise 0.
+*/
+unsigned char LED_Configure(unsigned int led)
+{
+#ifdef PINS_LEDS
+    // Check that LED exists
+    if (led >= numLeds) {
+
+        return 0;
+    }
+
+    // Configure LED
+    return (PIO_Configure(&pinsLeds[led], 1));
+#else
+    return 0;
+#endif
+}
+
+/*
+    Function: LED_Set
+        Turns a LED on.
+
+    Parameters:
+        led - Number of the LED to turn on.
+
+    Returns:
+        1 if the LED has been turned on; 0 otherwise.
+*/
+unsigned char LED_Set(unsigned int led)
+{
+#ifdef PINS_LEDS
+    // Check if LED exists
+    if (led >= numLeds) {
+
+        return 0;
+    }
+
+    // Turn LED on
+    if (pinsLeds[led].type == PIO_OUTPUT_0) {
+
+        PIO_Set(&pinsLeds[led]);
+    }
+    else {
+
+        PIO_Clear(&pinsLeds[led]);
+    }
+
+    return 1;
+#else
+    return 0;
+#endif
+}
+
+/*
+    Function: LED_Clear
+        Turns a LED off.
+
+    Parameters:
+        led - Number of the LED to turn off.
+
+    Returns:
+        1 if the LED has been turned off; 0 otherwise.
+*/
+unsigned char LED_Clear(unsigned int led)
+{
+#ifdef PINS_LEDS
+    // Check if LED exists
+    if (led >= numLeds) {
+
+        return 0;
+    }
+
+    // Turn LED off
+    if (pinsLeds[led].type == PIO_OUTPUT_0) {
+
+        PIO_Clear(&pinsLeds[led]);
+    }
+    else {
+
+        PIO_Set(&pinsLeds[led]);
+    }
+
+    return 1;
+#else
+    return 0;
+#endif
+}
+
+/*
+    Function: LED_Toggle
+        Toggles the current state of a LED.
+
+    Parameters:
+        led - Number of the LED to toggle.
+
+    Returns:
+        1 if the LED has been toggled; otherwise 0.
+*/
+unsigned char LED_Toggle(unsigned int led)
+{
+#ifdef PINS_LEDS
+    // Check if LED exists
+    if (led >= numLeds) {
+
+        return 0;
+    }
+
+    // Toggle LED
+    if (PIO_GetOutputDataStatus(&pinsLeds[led])) {
+
+        PIO_Clear(&pinsLeds[led]);
+    }
+    else {
+
+        PIO_Set(&pinsLeds[led]);
+    }
+
+    return 1;
+#else
+    return 0;
+#endif
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/utility/led.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/utility/led.h
new file mode 100644
index 0000000..2e44a9f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/utility/led.h
@@ -0,0 +1,66 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*
+    Title: LED
+
+    About: Purpose
+        Small set of functions for simple and portable LED usage.
+
+    About: Usage
+        1 - Configure one or more LEDs using  and
+            .
+        2 - Set, clear and toggle LEDs using ,  and
+            .
+        3 - Get the current status of a LED using .
+
+        LEDs are numbered starting from 0; the number of LEDs depend on the
+        board being used. All the functions defined here will compile properly
+        regardless of whether the LED is defined or not; they will simply
+        return 0 when a LED which does not exist is given as an argument.
+        Also, these functions take into account how each LED is connected on to
+        board; thus,  might change the level on the corresponding pin
+        to 0 or 1, but it will always light the LED on; same thing for the other
+        methods.
+*/
+
+#ifndef LED_H
+#define LED_H
+
+//------------------------------------------------------------------------------
+//         Exported functions
+//------------------------------------------------------------------------------
+
+extern unsigned char LED_Configure(unsigned int led);
+extern unsigned char LED_Set(unsigned int led);
+extern unsigned char LED_Clear(unsigned int led);
+extern unsigned char LED_Toggle(unsigned int led);
+
+#endif //#ifndef LED_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/utility/trace.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/utility/trace.h
new file mode 100644
index 0000000..10f9bd7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/Atmel/at91lib/utility/trace.h
@@ -0,0 +1,134 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*
+    Title: Trace
+
+    About: Purpose
+        Standard output methods for reporting debug information, warnings and
+        errors, which can be turned on/off.
+
+    About: Usage
+        1 - Initialize the DBGU using .
+        2 - Uses the  macro to output traces throughout the program.
+        3 - Turn off all traces by defining the NOTRACE symbol during
+            compilation.
+        4 - Disable a group of trace by changing the value of 
+            during compilation; traces with a level below  are not
+            generated.
+*/
+
+#ifndef TRACE_H
+#define TRACE_H
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#if !defined(NOTRACE)
+    #include 
+    #include 
+    #include 
+    #include 
+#endif
+
+//------------------------------------------------------------------------------
+//         Definitions
+//------------------------------------------------------------------------------
+/*
+    Constants: Trace levels
+        trace_FATAL - Indicates a major error which prevents the program from
+            going any further.
+        trace_ERROR - Indicates an error which may not stop the program
+            execution, but which indicates there is a problem with the code.
+        trace_WARNING - Indicates that a minor error has happened. In most case
+            it can be discarded safely; it may even be expected.
+        trace_INFO - Informational trace about the program execution. Should
+            enable the user to see the execution flow.
+        trace_DEBUG - Traces whose only purpose is for debugging the program,
+            and which do not produce meaningful information otherwise.
+*/
+#define trace_DEBUG                     0
+#define trace_INFO                      1
+#define trace_WARNING                   2
+#define trace_ERROR                     3
+#define trace_FATAL                     4
+
+/*
+    Constant: trace_LEVEL
+        Minimum level of traces that are output. By default, all traces are
+        output; change the value of this symbol during compilation for a more
+        restrictive behavior.
+*/
+#if !defined(trace_LEVEL)
+    #define trace_LEVEL                     0
+#endif
+
+/*
+    Macro: trace_CONFIGURE
+        Initializes the DBGU unless the NOTRACE symbol has been defined.
+
+    Parameters:
+        mode - DBGU mode.
+        baudrate - DBGU baudrate.
+        mck - Master clock frequency.
+*/
+#if !defined(NOTRACE)
+    #define trace_CONFIGURE(mode, baudrate, mck) { \
+        const Pin pinsDbgu[] = {PINS_DBGU}; \
+        PIO_Configure(pinsDbgu, PIO_LISTSIZE(pinsDbgu)); \
+        DBGU_Configure(mode, baudrate, mck); \
+    }
+#else
+    #define trace_CONFIGURE(...)
+#endif
+
+/*
+    Macro: trace_LOG
+        Outputs a formatted string using  if the log level is high
+        enough. Can be disabled by defining the NOTRACE symbol during
+        compilation.
+
+    Parameters:
+        level - Trace level (see ).
+        format - Formatted string to output.
+        ... - Additional parameters, depending on the formatted string.
+*/
+#if !defined(NOTRACE)
+    #define trace_LOG(level, ...) { \
+        if (level >= trace_LEVEL) { \
+            printf(__VA_ARGS__); \
+        } \
+    }
+#else
+    #define trace_LOG(...)
+#endif
+
+#endif //#ifndef TRACE_H
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/EULA.txt b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/EULA.txt
new file mode 100644
index 0000000..e5b3790
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/EULA.txt
@@ -0,0 +1,145 @@
+IMPORTANT. Read the following LMI Software License Agreement ("Agreement")
+completely.
+
+In summary, this license agreement allows you to use this software only on
+Luminary Micro microcontrollers, on an as-is basis, with no warranties.
+
+LUMINARY MICRO SOFTWARE LICENSE AGREEMENT
+
+This is a legal agreement between you (either as an individual or as an
+authorized representative of your employer) and Luminary Micro, Inc. ("LMI").
+It concerns your rights to use this file and any accompanying written materials
+(the "Software"). In consideration for LMI allowing you to access the Software,
+you are agreeing to be bound by the terms of this Agreement. If you do not
+agree to all of the terms of this Agreement, do not download the Software. If
+you change your mind later, stop using the Software and delete all copies of
+the Software in your possession or control. Any copies of the Software that you
+have already distributed, where permitted, and do not destroy will continue to
+be governed by this Agreement. Your prior use will also continue to be governed
+by this Agreement.
+
+1. LICENSE GRANT. LMI grants to you, free of charge, the non-exclusive,
+non-transferable rights solely and exclusively on or for LMI's microcontroller
+products: (1) to use and reproduce the Software, (2) to prepare derivative
+works of the Software, (3) to distribute the Software and derivative works
+thereof in source (human-readable) form and object (machine-readable) form, (4)
+to sublicense to others the right to use the distributed Software, (5) permit
+the Software and derivative works thereof to communicate with "viral open
+source" software (as defined below); provided however that you may not combine
+the two separate and independent works to form a larger program, and (6)
+combine the Software and derivative works thereof with "non-viral open source"
+software (as defined below). For the purposes of this Agreement, "viral open
+source" software means open source software made available on license terms,
+such as the GNU General Public License (GPL), that would alter the foregoing
+license grant restrictions if combined with the Software. For the purposes of
+this Agreement, "non-viral open source" software means open source software
+made available on license terms that would not alter the foregoing license
+grant restrictions if combined with the Software. For the avoidance of any
+doubt, the foregoing license grant does not permit you to combine the Software
+and derivative works thereof with "viral open-source" software in order to
+sublicense to others the right to use the combined software product. If you
+violate any of the terms or restrictions of this Agreement, LMI may immediately
+terminate this Agreement, and require that you stop using and delete all copies
+of the Software in your possession or control.
+
+2. COPYRIGHT. The Software is licensed to you, not sold. LMI owns the Software,
+and United States copyright laws and international treaty provisions protect
+the Software. Therefore, you must treat the Software like any other copyrighted
+material (e.g. a book or musical recording). You may not use or copy the
+Software for any other purpose than what is described in this Agreement. Except
+as expressly provided herein, LMI does not grant to you any express or implied
+rights under any LMI or third-party patents, copyrights, trademarks, or trade
+secrets. Additionally, you must reproduce and apply any copyright or other
+proprietary rights notices included on or embedded in the Software to any
+copies or derivative works made thereof, in whole or in part, if any.
+
+3. SUPPORT. LMI is NOT obligated to provide any support, upgrades or new
+releases of the Software. If you wish, you may contact LMI and report problems
+and provide suggestions regarding the Software. LMI has no obligation
+whatsoever to respond in any way to such a problem report or suggestion. LMI
+may make changes to the Software at any time, without any obligation to notify
+or provide updated versions of the Software to you.
+
+4. INDEMNITY. You agree to fully defend and indemnify LMI from any and all
+claims, liabilities, and costs (including reasonable attorney's fees) related
+to (1) your use (including your sub-licensee's use, if permitted) of the
+Software or (2) your violation of the terms and conditions of this Agreement.
+
+5. HIGH RISK ACTIVITIES. You acknowledge that the Software is not fault
+tolerant and is not designed, manufactured or intended by LMI for incorporation
+into products intended for use or resale in on-line control equipment in
+hazardous, dangerous to life or potentially life-threatening environments
+requiring fail-safe performance, such as in the operation of nuclear
+facilities, aircraft navigation or communication systems, air traffic control,
+direct life support machines or weapons systems, in which the failure of
+products could lead directly to death, personal injury or severe physical or
+environmental damage ("High Risk Activities"). You specifically represent and
+warrant that you will not use the Software or any derivative work of the
+Software for High Risk Activities.
+
+6. PRODUCT LABELING. You are not authorized to use any LMI trademarks, brand
+names, or logos.
+
+7. COMPLIANCE WITH LAWS; EXPORT RESTRICTIONS. You must use the Software in
+accordance with all applicable U.S. laws, regulations and statutes. You agree
+that neither you nor your licensees (if any) intend to or will, directly or
+indirectly, export or transmit the Software to any country in violation of U.S.
+export restrictions.
+
+8. GOVERNMENT USE. Use of the Software and any corresponding documentation, if
+any, is provided with RESTRICTED RIGHTS. Use, duplication or disclosure by the
+Government is subject to restrictions as set forth in subparagraph (c)(1)(ii)
+of The Rights in Technical Data and Computer Software clause at DFARS
+252.227-7013 or subparagraphs (c)(l) and (2) of the Commercial Computer
+Software--Restricted Rights at 48 CFR 52.227-19, as applicable. Manufacturer is
+Luminary Micro, Inc., 108 Wild Basin Road, Ste 350, Austin, Texas 78746.
+
+9. DISCLAIMER OF WARRANTY. TO THE MAXIMUM EXTENT PERMITTED BY LAW, LMI
+EXPRESSLY DISCLAIMS ANY WARRANTY FOR THE SOFTWARE. THE SOFTWARE IS PROVIDED "AS
+IS", WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING,
+WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+PARTICULAR PURPOSE, OR NON-INFRINGEMENT. YOU ASSUME THE ENTIRE RISK ARISING OUT
+OF THE USE OR PERFORMANCE OF THE SOFTWARE, OR ANY SYSTEMS YOU DESIGN USING THE
+SOFTWARE (IF ANY). NOTHING IN THIS AGREEMENT MAY BE CONSTRUED AS A WARRANTY OR
+REPRESENTATION BY LMI THAT THE SOFTWARE OR ANY DERIVATIVE WORK DEVELOPED WITH
+OR INCORPORATING THE SOFTWARE WILL BE FREE FROM INFRINGEMENT OF THE
+INTELLECTUAL PROPERTY RIGHTS OF THIRD PARTIES.
+
+10. LIMITATION OF LIABILITY. IN NO EVENT WILL LMI BE LIABLE, WHETHER IN
+CONTRACT, TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT,
+CONSEQUENTIAL OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR
+ANY LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS,
+SAVINGS, OR REVENUES TO THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW.
+
+11. CHOICE OF LAW; VENUE; LIMITATIONS. You agree that the statutes and laws of
+the United States and the State of Texas, USA, without regard to conflicts of
+laws principles, will apply to all matters relating to this Agreement or the
+Software, and you agree that any litigation will be subject to the exclusive
+jurisdiction of the state or federal courts in Austin, Travis County, Texas,
+USA. You agree that regardless of any statute or law to the contrary, any claim
+or cause of action arising out of or related to this Agreement or the Software
+must be filed within one (1) year after such claim or cause of action arose or
+be forever barred. YOU EXPRESSLY AGREE THAT YOU WAIVE YOUR INDIVIDUAL RIGHT TO
+A TRIAL BY JURY IN ANY COURT OF COMPETENT JURISDICTION FOR ANY ACTION, DISPUTE,
+CLAIM, OR CONTROVERSY CONCERNING THIS AGREEMENT OR FOR ANY ACTION, DISPUTE,
+CLAIM, OR CONTROVERSY ARISING OUT OF OR RELATING TO ANY INTERPRETATION,
+CONSTRUCTION, PERFORMANCE OR BREACH OF THIS AGREEMENT.
+
+12. ENTIRE AGREEMENT. This Agreement constitutes the entire agreement between
+you and LMI regarding the subject matter of this Agreement, and supersedes all
+prior communications, negotiations, understandings, agreements or
+representations, either written or oral, if any. This Agreement may only be
+amended in written form, executed by you and LMI.
+
+13. SEVERABILITY. If any provision of this Agreement is held for any reason to
+be invalid or unenforceable, then the remaining provisions of this Agreement
+will be unimpaired and, unless a modification or replacement of the invalid or
+unenforceable provision is further held to deprive you or LMI of a material
+benefit, in which case the Agreement will immediately terminate, the invalid or
+unenforceable provision will be replaced with a provision that is valid and
+enforceable and that comes closest to the intention underlying the invalid or
+unenforceable provision.
+
+14. NO WAIVER. The waiver by LMI of any breach of any provision of this
+Agreement will not operate or be construed as a waiver of any other or a
+subsequent breach of the same or a different provision.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/IAR/driverlib.a b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/IAR/driverlib.a
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diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/IAR/grlib.a b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/IAR/grlib.a
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diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/Keil/driverlib.lib b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/Keil/driverlib.lib
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diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/Keil/grlib.lib b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/Keil/grlib.lib
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diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/Rowley/libdriver.a b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/Rowley/libdriver.a
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index 0000000..bb089ef
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diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/Rowley/libgr.a b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/Rowley/libgr.a
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diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/adc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/adc.h
new file mode 100644
index 0000000..2eec710
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/adc.h
@@ -0,0 +1,142 @@
+//*****************************************************************************
+//
+// adc.h - ADC headers for using the ADC driver functions.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __ADC_H__
+#define __ADC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCSequenceConfigure as the ulTrigger
+// parameter.
+//
+//*****************************************************************************
+#define ADC_TRIGGER_PROCESSOR   0x00000000  // Processor event
+#define ADC_TRIGGER_COMP0       0x00000001  // Analog comparator 0 event
+#define ADC_TRIGGER_COMP1       0x00000002  // Analog comparator 1 event
+#define ADC_TRIGGER_COMP2       0x00000003  // Analog comparator 2 event
+#define ADC_TRIGGER_EXTERNAL    0x00000004  // External event
+#define ADC_TRIGGER_TIMER       0x00000005  // Timer event
+#define ADC_TRIGGER_PWM0        0x00000006  // PWM0 event
+#define ADC_TRIGGER_PWM1        0x00000007  // PWM1 event
+#define ADC_TRIGGER_PWM2        0x00000008  // PWM2 event
+#define ADC_TRIGGER_ALWAYS      0x0000000F  // Always event
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCSequenceStepConfigure as the ulConfig
+// parameter.
+//
+//*****************************************************************************
+#define ADC_CTL_TS              0x00000080  // Temperature sensor select
+#define ADC_CTL_IE              0x00000040  // Interrupt enable
+#define ADC_CTL_END             0x00000020  // Sequence end select
+#define ADC_CTL_D               0x00000010  // Differential select
+#define ADC_CTL_CH0             0x00000000  // Input channel 0
+#define ADC_CTL_CH1             0x00000001  // Input channel 1
+#define ADC_CTL_CH2             0x00000002  // Input channel 2
+#define ADC_CTL_CH3             0x00000003  // Input channel 3
+#define ADC_CTL_CH4             0x00000004  // Input channel 4
+#define ADC_CTL_CH5             0x00000005  // Input channel 5
+#define ADC_CTL_CH6             0x00000006  // Input channel 6
+#define ADC_CTL_CH7             0x00000007  // Input channel 7
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
+                           void (*pfnHandler)(void));
+extern void ADCIntUnregister(unsigned long ulBase,
+                             unsigned long ulSequenceNum);
+extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);
+extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);
+extern unsigned long ADCIntStatus(unsigned long ulBase,
+                                  unsigned long ulSequenceNum,
+                                  tBoolean bMasked);
+extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);
+extern void ADCSequenceEnable(unsigned long ulBase,
+                              unsigned long ulSequenceNum);
+extern void ADCSequenceDisable(unsigned long ulBase,
+                               unsigned long ulSequenceNum);
+extern void ADCSequenceConfigure(unsigned long ulBase,
+                                 unsigned long ulSequenceNum,
+                                 unsigned long ulTrigger,
+                                 unsigned long ulPriority);
+extern void ADCSequenceStepConfigure(unsigned long ulBase,
+                                     unsigned long ulSequenceNum,
+                                     unsigned long ulStep,
+                                     unsigned long ulConfig);
+extern long ADCSequenceOverflow(unsigned long ulBase,
+                                unsigned long ulSequenceNum);
+extern void ADCSequenceOverflowClear(unsigned long ulBase,
+                                     unsigned long ulSequenceNum);
+extern long ADCSequenceUnderflow(unsigned long ulBase,
+                                 unsigned long ulSequenceNum);
+extern void ADCSequenceUnderflowClear(unsigned long ulBase,
+                                      unsigned long ulSequenceNum);
+extern long ADCSequenceDataGet(unsigned long ulBase,
+                               unsigned long ulSequenceNum,
+                               unsigned long *pulBuffer);
+extern void ADCProcessorTrigger(unsigned long ulBase,
+                                unsigned long ulSequenceNum);
+extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,
+                                           unsigned long ulSequenceNum,
+                                           unsigned long ulFactor);
+extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
+                                               unsigned long ulSequenceNum,
+                                               unsigned long ulStep,
+                                               unsigned long ulConfig);
+extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,
+                                         unsigned long ulSequenceNum,
+                                         unsigned long *pulBuffer,
+                                         unsigned long ulCount);
+extern void ADCHardwareOversampleConfigure(unsigned long ulBase,
+                                           unsigned long ulFactor);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __ADC_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/arm-none-eabi-gcc/libdriver.a b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/arm-none-eabi-gcc/libdriver.a
new file mode 100644
index 0000000..5aab524
Binary files /dev/null and b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/arm-none-eabi-gcc/libdriver.a differ
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/arm-none-eabi-gcc/libgr.a b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/arm-none-eabi-gcc/libgr.a
new file mode 100644
index 0000000..4712250
Binary files /dev/null and b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/arm-none-eabi-gcc/libgr.a differ
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/can.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/can.h
new file mode 100644
index 0000000..b6c99b3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/can.h
@@ -0,0 +1,453 @@
+//*****************************************************************************
+//
+// can.h - Defines and Macros for the CAN controller.
+//
+// Copyright (c) 2006-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __CAN_H__
+#define __CAN_H__
+
+//*****************************************************************************
+//
+//! \addtogroup can_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Miscellaneous defines for Message ID Types
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! These are the flags used by the tCANMsgObject variable when calling the
+//! CANMessageSet() and CANMessageGet() functions.
+//
+//*****************************************************************************
+typedef enum
+{
+    //
+    //! This indicates that transmit interrupts should be enabled, or are
+    //! enabled.
+    //
+    MSG_OBJ_TX_INT_ENABLE =     0x00000001,
+
+    //
+    //! This indicates that receive interrupts should be enabled, or are
+    //! enabled.
+    //
+    MSG_OBJ_RX_INT_ENABLE =     0x00000002,
+
+    //
+    //! This indicates that a message object will use or is using an extended
+    //! identifier.
+    //
+    MSG_OBJ_EXTENDED_ID =       0x00000004,
+
+    //
+    //! This indicates that a message object will use or is using filtering
+    //! based on the object's message identifier.
+    //
+    MSG_OBJ_USE_ID_FILTER =     0x00000008,
+
+    //
+    //! This indicates that new data was available in the message object.
+    //
+    MSG_OBJ_NEW_DATA =          0x00000080,
+
+    //
+    //! This indicates that data was lost since this message object was last
+    //! read.
+    //
+    MSG_OBJ_DATA_LOST =         0x00000100,
+
+    //
+    //! This indicates that a message object will use or is using filtering
+    //! based on the direction of the transfer.  If the direction filtering is
+    //! used, then ID filtering must also be enabled.
+    //
+    MSG_OBJ_USE_DIR_FILTER =    (0x00000010 | MSG_OBJ_USE_ID_FILTER),
+
+    //
+    //! This indicates that a message object will use or is using message
+    //! identifier filtering based on the extended identifier.  If the extended
+    //! identifier filtering is used, then ID filtering must also be enabled.
+    //
+    MSG_OBJ_USE_EXT_FILTER =    (0x00000020 | MSG_OBJ_USE_ID_FILTER),
+
+    //
+    //! This indicates that a message object is a remote frame.
+    //
+    MSG_OBJ_REMOTE_FRAME =      0x00000040,
+
+    //
+    //! This indicates that a message object has no flags set.
+    //
+    MSG_OBJ_NO_FLAGS =          0x00000000
+}
+tCANObjFlags;
+
+//*****************************************************************************
+//
+//! This define is used with the #tCANObjFlags enumerated values to allow
+//! checking only status flags and not configuration flags.
+//
+//*****************************************************************************
+#define MSG_OBJ_STATUS_MASK     (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST)
+
+//*****************************************************************************
+//
+//! The structure used for encapsulating all the items associated with a CAN
+//! message object in the CAN controller.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The CAN message identifier used for 11 or 29 bit identifiers.
+    //
+    unsigned long ulMsgID;
+
+    //
+    //! The message identifier mask used when identifier filtering is enabled.
+    //
+    unsigned long ulMsgIDMask;
+
+    //
+    //! This value holds various status flags and settings specified by
+    //! tCANObjFlags.
+    //
+    unsigned long ulFlags;
+
+    //
+    //! This value is the number of bytes of data in the message object.
+    //
+    unsigned long ulMsgLen;
+
+    //
+    //! This is a pointer to the message object's data.
+    //
+    unsigned char *pucMsgData;
+}
+tCANMsgObject;
+
+//*****************************************************************************
+//
+//! This structure is used for encapsulating the values associated with setting
+//! up the bit timing for a CAN controller.  The structure is used when calling
+//! the CANGetBitTiming and CANSetBitTiming functions.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! This value holds the sum of the Synchronization, Propagation, and Phase
+    //! Buffer 1 segments, measured in time quanta.  The valid values for this
+    //! setting range from 2 to 16.
+    //
+    unsigned int uSyncPropPhase1Seg;
+
+    //
+    //! This value holds the Phase Buffer 2 segment in time quanta.  The valid
+    //! values for this setting range from 1 to 8.
+    //
+    unsigned int uPhase2Seg;
+
+    //
+    //! This value holds the Resynchronization Jump Width in time quanta.  The
+    //! valid values for this setting range from 1 to 4.
+    //
+    unsigned int uSJW;
+
+    //
+    //! This value holds the CAN_CLK divider used to determine time quanta.
+    //! The valid values for this setting range from 1 to 1023.
+    //
+    unsigned int uQuantumPrescaler;
+
+}
+tCANBitClkParms;
+
+//*****************************************************************************
+//
+//! This data type is used to identify the interrupt status register.  This is
+//! used when calling the CANIntStatus() function.
+//
+//*****************************************************************************
+typedef enum
+{
+    //
+    //! Read the CAN interrupt status information.
+    //
+    CAN_INT_STS_CAUSE,
+
+    //
+    //! Read a message object's interrupt status.
+    //
+    CAN_INT_STS_OBJECT
+}
+tCANIntStsReg;
+
+//*****************************************************************************
+//
+//! This data type is used to identify which of several status registers to
+//! read when calling the CANStatusGet() function.
+//
+//*****************************************************************************
+typedef enum
+{
+    //
+    //! Read the full CAN controller status.
+    //
+    CAN_STS_CONTROL,
+
+    //
+    //! Read the full 32-bit mask of message objects with a transmit request
+    //! set.
+    //
+    CAN_STS_TXREQUEST,
+
+    //
+    //! Read the full 32-bit mask of message objects with new data available.
+    //
+    CAN_STS_NEWDAT,
+
+    //
+    //! Read the full 32-bit mask of message objects that are enabled.
+    //
+    CAN_STS_MSGVAL
+}
+tCANStsReg;
+
+//*****************************************************************************
+//
+//! These definitions are used to specify interrupt sources to CANIntEnable()
+//! and CANIntDisable().
+//
+//*****************************************************************************
+typedef enum
+{
+    //
+    //! This flag is used to allow a CAN controller to generate error
+    //! interrupts.
+    //
+    CAN_INT_ERROR =             0x00000008,
+
+    //
+    //! This flag is used to allow a CAN controller to generate status
+    //! interrupts.
+    //
+    CAN_INT_STATUS =            0x00000004,
+
+    //
+    //! This flag is used to allow a CAN controller to generate any CAN
+    //! interrupts.  If this is not set, then no interrupts will be generated
+    //! by the CAN controller.
+    //
+    CAN_INT_MASTER =            0x00000002
+}
+tCANIntFlags;
+
+//*****************************************************************************
+//
+//! This definition is used to determine the type of message object that will
+//! be set up via a call to the CANMessageSet() API.
+//
+//*****************************************************************************
+typedef enum
+{
+    //
+    //! Transmit message object.
+    //
+    MSG_OBJ_TYPE_TX,
+
+    //
+    //! Transmit remote request message object
+    //
+    MSG_OBJ_TYPE_TX_REMOTE,
+
+    //
+    //! Receive message object.
+    //
+    MSG_OBJ_TYPE_RX,
+
+    //
+    //! Receive remote request message object.
+    //
+    MSG_OBJ_TYPE_RX_REMOTE,
+
+    //
+    //! Remote frame receive remote, with auto-transmit message object.
+    //
+    MSG_OBJ_TYPE_RXTX_REMOTE
+}
+tMsgObjType;
+
+//*****************************************************************************
+//
+//! The following enumeration contains all error or status indicators that can
+//! be returned when calling the CANStatusGet() function.
+//
+//*****************************************************************************
+typedef enum
+{
+    //
+    //! CAN controller has entered a Bus Off state.
+    //
+    CAN_STATUS_BUS_OFF =        0x00000080,
+
+    //
+    //! CAN controller error level has reached warning level.
+    //
+    CAN_STATUS_EWARN =          0x00000040,
+
+    //
+    //! CAN controller error level has reached error passive level.
+    //
+    CAN_STATUS_EPASS =          0x00000020,
+
+    //
+    //! A message was received successfully since the last read of this status.
+    //
+    CAN_STATUS_RXOK =           0x00000010,
+
+    //
+    //! A message was transmitted successfully since the last read of this
+    //! status.
+    //
+    CAN_STATUS_TXOK =           0x00000008,
+
+    //
+    //! This is the mask for the last error code field.
+    //
+    CAN_STATUS_LEC_MSK =        0x00000007,
+
+    //
+    //! There was no error.
+    //
+    CAN_STATUS_LEC_NONE =       0x00000000,
+
+    //
+    //! A bit stuffing error has occurred.
+    //
+    CAN_STATUS_LEC_STUFF =      0x00000001,
+
+    //
+    //! A formatting error has occurred.
+    //
+    CAN_STATUS_LEC_FORM =       0x00000002,
+
+    //
+    //! An acknowledge error has occurred.
+    //
+    CAN_STATUS_LEC_ACK =        0x00000003,
+
+    //
+    //! The bus remained a bit level of 1 for longer than is allowed.
+    //
+    CAN_STATUS_LEC_BIT1 =       0x00000004,
+
+    //
+    //! The bus remained a bit level of 0 for longer than is allowed.
+    //
+    CAN_STATUS_LEC_BIT0 =       0x00000005,
+
+    //
+    //! A CRC error has occurred.
+    //
+    CAN_STATUS_LEC_CRC =        0x00000006,
+
+    //
+    //! This is the mask for the CAN Last Error Code (LEC).
+    //
+    CAN_STATUS_LEC_MASK =       0x00000007
+}
+tCANStatusCtrl;
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void CANInit(unsigned long ulBase);
+extern void CANEnable(unsigned long ulBase);
+extern void CANDisable(unsigned long ulBase);
+extern void CANSetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms);
+extern void CANGetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms);
+extern unsigned long CANReadReg(unsigned long ulRegAddress);
+extern void CANWriteReg(unsigned long ulRegAddress, unsigned long ulRegValue);
+extern void CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
+                          tCANMsgObject *pMsgObject, tMsgObjType eMsgType);
+extern void CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
+                          tCANMsgObject *pMsgObject, tBoolean bClrPendingInt);
+extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg);
+extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID);
+extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
+extern void CANIntUnregister(unsigned long ulBase);
+extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr);
+extern unsigned long CANIntStatus(unsigned long ulBase,
+                                  tCANIntStsReg eIntStsReg);
+extern tBoolean CANRetryGet(unsigned long ulBase);
+extern void CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry);
+extern tBoolean CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount,
+                              unsigned long *pulTxCount);
+extern long CANGetIntNumber(unsigned long ulBase);
+extern void CANReadDataReg(unsigned char *pucData, unsigned long *pulRegister,
+                           int iSize);
+extern void CANWriteDataReg(unsigned char *pucData, unsigned long *pulRegister,
+                            int iSize);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif //  __CAN_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/comp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/comp.h
new file mode 100644
index 0000000..144a7f2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/comp.h
@@ -0,0 +1,134 @@
+//*****************************************************************************
+//
+// comp.h - Prototypes for the analog comparator driver.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __COMP_H__
+#define __COMP_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to ComparatorConfigure() as the ulConfig
+// parameter.  For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of
+// the values may be selected and combined together with values from the other
+// groups via a logical OR.
+//
+//*****************************************************************************
+#define COMP_TRIG_NONE          0x00000000  // No ADC trigger
+#define COMP_TRIG_HIGH          0x00000880  // Trigger when high
+#define COMP_TRIG_LOW           0x00000800  // Trigger when low
+#define COMP_TRIG_FALL          0x00000820  // Trigger on falling edge
+#define COMP_TRIG_RISE          0x00000840  // Trigger on rising edge
+#define COMP_TRIG_BOTH          0x00000860  // Trigger on both edges
+#define COMP_INT_HIGH           0x00000010  // Interrupt when high
+#define COMP_INT_LOW            0x00000000  // Interrupt when low
+#define COMP_INT_FALL           0x00000004  // Interrupt on falling edge
+#define COMP_INT_RISE           0x00000008  // Interrupt on rising edge
+#define COMP_INT_BOTH           0x0000000C  // Interrupt on both edges
+#define COMP_ASRCP_PIN          0x00000000  // Dedicated Comp+ pin
+#define COMP_ASRCP_PIN0         0x00000200  // Comp0+ pin
+#define COMP_ASRCP_REF          0x00000400  // Internal voltage reference
+#ifndef DEPRECATED
+#define COMP_OUTPUT_NONE        0x00000000  // No comparator output
+#endif
+#define COMP_OUTPUT_NORMAL      0x00000000  // Comparator output normal
+#define COMP_OUTPUT_INVERT      0x00000002  // Comparator output inverted
+
+//*****************************************************************************
+//
+// Values that can be passed to ComparatorSetRef() as the ulRef parameter.
+//
+//*****************************************************************************
+#define COMP_REF_OFF            0x00000000  // Turn off the internal reference
+#define COMP_REF_0V             0x00000300  // Internal reference of 0V
+#define COMP_REF_0_1375V        0x00000301  // Internal reference of 0.1375V
+#define COMP_REF_0_275V         0x00000302  // Internal reference of 0.275V
+#define COMP_REF_0_4125V        0x00000303  // Internal reference of 0.4125V
+#define COMP_REF_0_55V          0x00000304  // Internal reference of 0.55V
+#define COMP_REF_0_6875V        0x00000305  // Internal reference of 0.6875V
+#define COMP_REF_0_825V         0x00000306  // Internal reference of 0.825V
+#define COMP_REF_0_928125V      0x00000201  // Internal reference of 0.928125V
+#define COMP_REF_0_9625V        0x00000307  // Internal reference of 0.9625V
+#define COMP_REF_1_03125V       0x00000202  // Internal reference of 1.03125V
+#define COMP_REF_1_134375V      0x00000203  // Internal reference of 1.134375V
+#define COMP_REF_1_1V           0x00000308  // Internal reference of 1.1V
+#define COMP_REF_1_2375V        0x00000309  // Internal reference of 1.2375V
+#define COMP_REF_1_340625V      0x00000205  // Internal reference of 1.340625V
+#define COMP_REF_1_375V         0x0000030A  // Internal reference of 1.375V
+#define COMP_REF_1_44375V       0x00000206  // Internal reference of 1.44375V
+#define COMP_REF_1_5125V        0x0000030B  // Internal reference of 1.5125V
+#define COMP_REF_1_546875V      0x00000207  // Internal reference of 1.546875V
+#define COMP_REF_1_65V          0x0000030C  // Internal reference of 1.65V
+#define COMP_REF_1_753125V      0x00000209  // Internal reference of 1.753125V
+#define COMP_REF_1_7875V        0x0000030D  // Internal reference of 1.7875V
+#define COMP_REF_1_85625V       0x0000020A  // Internal reference of 1.85625V
+#define COMP_REF_1_925V         0x0000030E  // Internal reference of 1.925V
+#define COMP_REF_1_959375V      0x0000020B  // Internal reference of 1.959375V
+#define COMP_REF_2_0625V        0x0000030F  // Internal reference of 2.0625V
+#define COMP_REF_2_165625V      0x0000020D  // Internal reference of 2.165625V
+#define COMP_REF_2_26875V       0x0000020E  // Internal reference of 2.26875V
+#define COMP_REF_2_371875V      0x0000020F  // Internal reference of 2.371875V
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
+                                unsigned long ulConfig);
+extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);
+extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);
+extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,
+                                  void (*pfnHandler)(void));
+extern void ComparatorIntUnregister(unsigned long ulBase,
+                                    unsigned long ulComp);
+extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp);
+extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp);
+extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,
+                                    tBoolean bMasked);
+extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __COMP_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/cpu.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/cpu.h
new file mode 100644
index 0000000..e33baff
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/cpu.h
@@ -0,0 +1,61 @@
+//*****************************************************************************
+//
+// cpu.h - Prototypes for the CPU instruction wrapper functions.
+//
+// Copyright (c) 2006-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __CPU_H__
+#define __CPU_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes.
+//
+//*****************************************************************************
+extern unsigned long CPUcpsid(void);
+extern unsigned long CPUcpsie(void);
+extern void CPUwfi(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __CPU_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/debug.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/debug.h
new file mode 100644
index 0000000..e7acc85
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/debug.h
@@ -0,0 +1,57 @@
+//*****************************************************************************
+//
+// debug.h - Macros for assisting debug of the driver library.
+//
+// Copyright (c) 2006-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DEBUG_H__
+#define __DEBUG_H__
+
+//*****************************************************************************
+//
+// Prototype for the function that is called when an invalid argument is passed
+// to an API.  This is only used when doing a DEBUG build.
+//
+//*****************************************************************************
+extern void __error__(char *pcFilename, unsigned long ulLine);
+
+//*****************************************************************************
+//
+// The ASSERT macro, which does the actual assertion checking.  Typically, this
+// will be for procedure arguments.
+//
+//*****************************************************************************
+#ifdef DEBUG
+#define ASSERT(expr) {                                      \
+                         if(!(expr))                        \
+                         {                                  \
+                             __error__(__FILE__, __LINE__); \
+                         }                                  \
+                     }
+#else
+#define ASSERT(expr)
+#endif
+
+#endif // __DEBUG_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/ethernet.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/ethernet.h
new file mode 100644
index 0000000..f464e8c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/ethernet.h
@@ -0,0 +1,173 @@
+//*****************************************************************************
+//
+// ethernet.h - Defines and Macros for the ethernet module.
+//
+// Copyright (c) 2006-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __ETHERNET_H__
+#define __ETHERNET_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to EthernetConfigSet as the ulConfig value, and
+// returned from EthernetConfigGet.
+//
+//*****************************************************************************
+#define ETH_CFG_TS_TSEN         0x010000    // Enable Timestamp (CCP)
+#define ETH_CFG_RX_BADCRCDIS    0x000800    // Disable RX BAD CRC Packets
+#define ETH_CFG_RX_PRMSEN       0x000400    // Enable RX Promiscuous
+#define ETH_CFG_RX_AMULEN       0x000200    // Enable RX Multicast
+#define ETH_CFG_TX_DPLXEN       0x000010    // Enable TX Duplex Mode
+#define ETH_CFG_TX_CRCEN        0x000004    // Enable TX CRC Generation
+#define ETH_CFG_TX_PADEN        0x000002    // Enable TX Padding
+
+//*****************************************************************************
+//
+// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and
+// EthernetIntClear as the ulIntFlags parameter, and returned from
+// EthernetIntStatus.
+//
+//*****************************************************************************
+#define ETH_INT_PHY             0x040       // PHY Event/Interrupt
+#define ETH_INT_MDIO            0x020       // Management Transaction
+#define ETH_INT_RXER            0x010       // RX Error
+#define ETH_INT_RXOF            0x008       // RX FIFO Overrun
+#define ETH_INT_TX              0x004       // TX Complete
+#define ETH_INT_TXER            0x002       // TX Error
+#define ETH_INT_RX              0x001       // RX Complete
+
+//*****************************************************************************
+//
+// Helper Macros for Ethernet Processing
+//
+//*****************************************************************************
+//
+// htonl/ntohl - big endian/little endian byte swapping macros for
+// 32-bit (long) values
+//
+//*****************************************************************************
+#ifndef htonl
+    #define htonl(a)                    \
+        ((((a) >> 24) & 0x000000ff) |   \
+         (((a) >>  8) & 0x0000ff00) |   \
+         (((a) <<  8) & 0x00ff0000) |   \
+         (((a) << 24) & 0xff000000))
+#endif
+
+#ifndef ntohl
+    #define ntohl(a)    htonl((a))
+#endif
+
+//*****************************************************************************
+//
+// htons/ntohs - big endian/little endian byte swapping macros for
+// 16-bit (short) values
+//
+//*****************************************************************************
+#ifndef htons
+    #define htons(a)                \
+        ((((a) >> 8) & 0x00ff) |    \
+         (((a) << 8) & 0xff00))
+#endif
+
+#ifndef ntohs
+    #define ntohs(a)    htons((a))
+#endif
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk);
+extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig);
+extern unsigned long EthernetConfigGet(unsigned long ulBase);
+extern void EthernetMACAddrSet(unsigned long ulBase,
+                               unsigned char *pucMACAddr);
+extern void EthernetMACAddrGet(unsigned long ulBase,
+                               unsigned char *pucMACAddr);
+extern void EthernetEnable(unsigned long ulBase);
+extern void EthernetDisable(unsigned long ulBase);
+extern tBoolean EthernetPacketAvail(unsigned long ulBase);
+extern tBoolean EthernetSpaceAvail(unsigned long ulBase);
+extern long EthernetPacketGetNonBlocking(unsigned long ulBase,
+                                         unsigned char *pucBuf,
+                                         long lBufLen);
+extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf,
+                              long lBufLen);
+extern long EthernetPacketPutNonBlocking(unsigned long ulBase,
+                                         unsigned char *pucBuf,
+                                         long lBufLen);
+extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,
+                              long lBufLen);
+extern void EthernetIntRegister(unsigned long ulBase,
+                                void (*pfnHandler)(void));
+extern void EthernetIntUnregister(unsigned long ulBase);
+extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,
+                             unsigned long ulData);
+extern unsigned long EthernetPHYRead(unsigned long ulBase,
+                                     unsigned char ucRegAddr);
+
+//*****************************************************************************
+//
+// Several Ethernet APIs have been renamed, with the original function name
+// being deprecated.  These defines provide backward compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#include "sysctl.h"
+#define EthernetInit(a)                         \
+        EthernetInitExpClk(a, SysCtlClockGet())
+#define EthernetPacketNonBlockingGet(a, b, c) \
+        EthernetPacketGetNonBlocking(a, b, c)
+#define EthernetPacketNonBlockingPut(a, b, c) \
+        EthernetPacketPutNonBlocking(a, b, c)
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif //  __ETHERNET_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/gpio.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/gpio.h
new file mode 100644
index 0000000..9002d20
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/gpio.h
@@ -0,0 +1,156 @@
+//*****************************************************************************
+//
+// gpio.h - Defines and Macros for GPIO API.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __GPIO_H__
+#define __GPIO_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following values define the bit field for the ucPins argument to several
+// of the APIs.
+//
+//*****************************************************************************
+#define GPIO_PIN_0              0x00000001  // GPIO pin 0
+#define GPIO_PIN_1              0x00000002  // GPIO pin 1
+#define GPIO_PIN_2              0x00000004  // GPIO pin 2
+#define GPIO_PIN_3              0x00000008  // GPIO pin 3
+#define GPIO_PIN_4              0x00000010  // GPIO pin 4
+#define GPIO_PIN_5              0x00000020  // GPIO pin 5
+#define GPIO_PIN_6              0x00000040  // GPIO pin 6
+#define GPIO_PIN_7              0x00000080  // GPIO pin 7
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
+// returned from GPIODirModeGet.
+//
+//*****************************************************************************
+#define GPIO_DIR_MODE_IN        0x00000000  // Pin is a GPIO input
+#define GPIO_DIR_MODE_OUT       0x00000001  // Pin is a GPIO output
+#define GPIO_DIR_MODE_HW        0x00000002  // Pin is a peripheral function
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
+// returned from GPIOIntTypeGet.
+//
+//*****************************************************************************
+#define GPIO_FALLING_EDGE       0x00000000  // Interrupt on falling edge
+#define GPIO_RISING_EDGE        0x00000004  // Interrupt on rising edge
+#define GPIO_BOTH_EDGES         0x00000001  // Interrupt on both edges
+#define GPIO_LOW_LEVEL          0x00000002  // Interrupt on low level
+#define GPIO_HIGH_LEVEL         0x00000007  // Interrupt on high level
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,
+// and returned by GPIOPadConfigGet in the *pulStrength parameter.
+//
+//*****************************************************************************
+#define GPIO_STRENGTH_2MA       0x00000001  // 2mA drive strength
+#define GPIO_STRENGTH_4MA       0x00000002  // 4mA drive strength
+#define GPIO_STRENGTH_8MA       0x00000004  // 8mA drive strength
+#define GPIO_STRENGTH_8MA_SC    0x0000000C  // 8mA drive with slew rate control
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,
+// and returned by GPIOPadConfigGet in the *pulPadType parameter.
+//
+//*****************************************************************************
+#define GPIO_PIN_TYPE_STD       0x00000008  // Push-pull
+#define GPIO_PIN_TYPE_STD_WPU   0x0000000A  // Push-pull with weak pull-up
+#define GPIO_PIN_TYPE_STD_WPD   0x0000000C  // Push-pull with weak pull-down
+#define GPIO_PIN_TYPE_OD        0x00000009  // Open-drain
+#define GPIO_PIN_TYPE_OD_WPU    0x0000000B  // Open-drain with weak pull-up
+#define GPIO_PIN_TYPE_OD_WPD    0x0000000D  // Open-drain with weak pull-down
+#define GPIO_PIN_TYPE_ANALOG    0x00000000  // Analog comparator
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
+                           unsigned long ulPinIO);
+extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
+extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
+                           unsigned long ulIntType);
+extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
+extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
+                             unsigned long ulStrength,
+                             unsigned long ulPadType);
+extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
+                             unsigned long *pulStrength,
+                             unsigned long *pulPadType);
+extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);
+extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);
+extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPortIntRegister(unsigned long ulPort,
+                                void (*pfnIntHandler)(void));
+extern void GPIOPortIntUnregister(unsigned long ulPort);
+extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
+                         unsigned char ucVal);
+extern void GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort,
+                                    unsigned char ucPins);
+extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif //  __GPIO_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/grlib.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/grlib.h
new file mode 100644
index 0000000..b404f1a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/grlib.h
@@ -0,0 +1,1285 @@
+//*****************************************************************************
+//
+// grlib.h - Prototypes for the low level primitives provided by the graphics
+//           library.
+//
+// Copyright (c) 2007-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Graphics Library.
+//
+//*****************************************************************************
+
+#ifndef __GRLIB_H__
+#define __GRLIB_H__
+
+//*****************************************************************************
+//
+//! \addtogroup primitives_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! This structure defines the extents of a rectangle.  All points greater than
+//! or equal to the minimum and less than or equal to the maximum are part of
+//! the rectangle.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The minimum X coordinate of the rectangle.
+    //
+    short sXMin;
+
+    //
+    //! The minimum Y coordinate of the rectangle.
+    //
+    short sYMin;
+
+    //
+    //! The maximum X coordinate of the rectangle.
+    //
+    short sXMax;
+
+    //
+    //! The maximum Y coordinate of the rectangle.
+    //
+    short sYMax;
+}
+tRectangle;
+
+//*****************************************************************************
+//
+//! This structure defines the characteristics of a display driver.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The size of this structure.
+    //
+    long lSize;
+
+    //
+    //! A pointer to display driver-specific data.
+    //
+    void *pvDisplayData;
+
+    //
+    //! The width of this display.
+    //
+    unsigned short usWidth;
+
+    //
+    //! The height of this display.
+    //
+    unsigned short usHeight;
+
+    //
+    //! A pointer to the function to draw a pixel on this display.
+    //
+    void (*pfnPixelDraw)(void *pvDisplayData, long lX, long lY,
+                         unsigned long ulValue);
+
+    //
+    //! A pointer to the function to draw multiple pixels on this display.
+    //
+    void (*pfnPixelDrawMultiple)(void *pvDisplayData, long lX, long lY,
+                                 long lX0, long lCount, long lBPP,
+                                 const unsigned char *pucData,
+                                 const unsigned char *pucPalette);
+
+    //
+    //! A pointer to the function to draw a horizontal line on this display.
+    //
+    void (*pfnLineDrawH)(void *pvDisplayData, long lX1, long lX2, long lY,
+                         unsigned long ulValue);
+
+    //
+    //! A pointer to the function to draw a vertical line on this display.
+    //
+    void (*pfnLineDrawV)(void *pvDisplayData, long lX, long lY1, long lY2,
+                         unsigned long ulValue);
+
+    //
+    //! A pointer to the function to draw a filled rectangle on this display.
+    //
+    void (*pfnRectFill)(void *pvDisplayData, const tRectangle *pRect,
+                        unsigned long ulValue);
+
+    //
+    //! A pointer to the function to translate 24-bit RGB colors to
+    //! display-specific colors.
+    //
+    unsigned long (*pfnColorTranslate)(void *pvDisplayData,
+                                       unsigned long ulValue);
+
+    //
+    //! A pointer to the function to flush any cached drawing operations on
+    //! this display.
+    //
+    void (*pfnFlush)(void *pvDisplayData);
+}
+tDisplay;
+
+//*****************************************************************************
+//
+//! This structure describes a font used for drawing text onto the screen.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The format of the font.  Can be one of FONT_FMT_UNCOMPRESSED or
+    //! FONT_FMT_PIXEL_RLE.
+    //
+    unsigned char ucFormat;
+
+    //
+    //! The maximum width of a character; this is the width of the widest
+    //! character in the font, though any individual character may be narrower
+    //! than this width.
+    //
+    unsigned char ucMaxWidth;
+
+    //
+    //! The height of the character cell; this may be taller than the font data
+    //! for the characters (to provide inter-line spacing).
+    //
+    unsigned char ucHeight;
+
+    //
+    //! The offset between the top of the character cell and the baseline of
+    //! the glyph.  The baseline is the bottom row of a capital letter, below
+    //! which only the descenders of the lower case letters occur.
+    //
+    unsigned char ucBaseline;
+
+    //
+    //! The offset within pucData to the data for each character in the font.
+    //
+    unsigned short pusOffset[96];
+
+    //
+    //! A pointer to the data for the font.
+    //
+    const unsigned char *pucData;
+}
+tFont;
+
+//*****************************************************************************
+//
+//! Indicates that the font data is stored in an uncompressed format.
+//
+//*****************************************************************************
+#define FONT_FMT_UNCOMPRESSED   0x00
+
+//*****************************************************************************
+//
+//! Indicates that the font data is stored using a pixel-based RLE format.
+//
+//*****************************************************************************
+#define FONT_FMT_PIXEL_RLE      0x01
+
+//*****************************************************************************
+//
+//! Indicates that the image data is not compressed and represents each pixel
+//! with a single bit.
+//
+//*****************************************************************************
+#define IMAGE_FMT_1BPP_UNCOMP   0x01
+
+//*****************************************************************************
+//
+//! Indicates that the image data is not compressed and represents each pixel
+//! with four bits.
+//
+//*****************************************************************************
+#define IMAGE_FMT_4BPP_UNCOMP   0x04
+
+//*****************************************************************************
+//
+//! Indicates that the image data is not compressed and represents each pixel
+//! with eight bits.
+//
+//*****************************************************************************
+#define IMAGE_FMT_8BPP_UNCOMP   0x08
+
+//*****************************************************************************
+//
+//! Indicates that the image data is compressed and represents each pixel with
+//! a single bit.
+//
+//*****************************************************************************
+#define IMAGE_FMT_1BPP_COMP     0x81
+
+//*****************************************************************************
+//
+//! Indicates that the image data is compressed and represents each pixel with
+//! four bits.
+//
+//*****************************************************************************
+#define IMAGE_FMT_4BPP_COMP     0x84
+
+//*****************************************************************************
+//
+//! Indicates that the image data is compressed and represents each pixel with
+//! eight bits.
+//
+//*****************************************************************************
+#define IMAGE_FMT_8BPP_COMP     0x88
+
+//*****************************************************************************
+//
+//! This structure defines a drawing context to be used to draw onto the
+//! screen.  Multiple drawing contexts may exist at any time.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The size of this structure.
+    //
+    long lSize;
+
+    //
+    //! The screen onto which drawing operations are performed.
+    //
+    const tDisplay *pDisplay;
+
+    //
+    //! The clipping region to be used when drawing onto the screen.
+    //
+    tRectangle sClipRegion;
+
+    //
+    //! The color used to draw primitives onto the screen.
+    //
+    unsigned long ulForeground;
+
+    //
+    //! The background color used to draw primitives onto the screen.
+    //
+    unsigned long ulBackground;
+
+    //
+    //! The font used to render text onto the screen.
+    //
+    const tFont *pFont;
+}
+tContext;
+
+//*****************************************************************************
+//
+//! Sets the background color to be used.
+//!
+//! \param pContext is a pointer to the drawing context to modify.
+//! \param ulValue is the 24-bit RGB color to be used.
+//!
+//! This function sets the background color to be used for drawing operations
+//! in the specified drawing context.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#define GrContextBackgroundSet(pContext, ulValue)                        \
+        do                                                               \
+        {                                                                \
+            tContext *pC = pContext;                                     \
+            pC->ulBackground = DpyColorTranslate(pC->pDisplay, ulValue); \
+        }                                                                \
+        while(0)
+
+//*****************************************************************************
+//
+//! Sets the background color to be used.
+//!
+//! \param pContext is a pointer to the drawing context to modify.
+//! \param ulValue is the display driver-specific color to be used.
+//!
+//! This function sets the background color to be used for drawing operations
+//! in the specified drawing context, using a color that has been previously
+//! translated to a driver-specific color (for example, via
+//! DpyColorTranslate()).
+//!
+//! \return None.
+//
+//*****************************************************************************
+#define GrContextBackgroundSetTranslated(pContext, ulValue) \
+        do                                                  \
+        {                                                   \
+            tContext *pC = pContext;                        \
+            pC->ulBackground = ulValue;                     \
+        }                                                   \
+        while(0)
+
+//*****************************************************************************
+//
+//! Gets the width of the display being used by this drawing context.
+//!
+//! \param pContext is a pointer to the drawing context to query.
+//!
+//! This function returns the width of the display that is being used by this
+//! drawing context.
+//!
+//! \return Returns the width of the display in pixels.
+//
+//*****************************************************************************
+#define GrContextDpyWidthGet(pContext)      \
+        (DpyWidthGet((pContext)->pDisplay))
+
+//*****************************************************************************
+//
+//! Gets the height of the display being used by this drawing context.
+//!
+//! \param pContext is a pointer to the drawing context to query.
+//!
+//! This function returns the height of the display that is being used by this
+//! drawing context.
+//!
+//! \return Returns the height of the display in pixels.
+//
+//*****************************************************************************
+#define GrContextDpyHeightGet(pContext)      \
+        (DpyHeightGet((pContext)->pDisplay))
+
+//*****************************************************************************
+//
+//! Sets the font to be used.
+//!
+//! \param pContext is a pointer to the drawing context to modify.
+//! \param pFnt is a pointer to the font to be used.
+//!
+//! This function sets the font to be used for string drawing operations in the
+//! specified drawing context.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#define GrContextFontSet(pContext, pFnt) \
+        do                               \
+        {                                \
+            tContext *pC = pContext;     \
+            const tFont *pF = pFnt;      \
+            pC->pFont = pF;              \
+        }                                \
+        while(0)
+
+//*****************************************************************************
+//
+//! Sets the foreground color to be used.
+//!
+//! \param pContext is a pointer to the drawing context to modify.
+//! \param ulValue is the 24-bit RGB color to be used.
+//!
+//! This function sets the color to be used for drawing operations in the
+//! specified drawing context.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#define GrContextForegroundSet(pContext, ulValue)                        \
+        do                                                               \
+        {                                                                \
+            tContext *pC = pContext;                                     \
+            pC->ulForeground = DpyColorTranslate(pC->pDisplay, ulValue); \
+        }                                                                \
+        while(0)
+
+//*****************************************************************************
+//
+//! Sets the foreground color to be used.
+//!
+//! \param pContext is a pointer to the drawing context to modify.
+//! \param ulValue is the display driver-specific color to be used.
+//!
+//! This function sets the foreground color to be used for drawing operations
+//! in the specified drawing context, using a color that has been previously
+//! translated to a driver-specific color (for example, via
+//! DpyColorTranslate()).
+//!
+//! \return None.
+//
+//*****************************************************************************
+#define GrContextForegroundSetTranslated(pContext, ulValue) \
+        do                                                  \
+        {                                                   \
+            tContext *pC = pContext;                        \
+            pC->ulForeground = ulValue;                     \
+        }                                                   \
+        while(0)
+
+//*****************************************************************************
+//
+//! Flushes any cached drawing operations.
+//!
+//! \param pContext is a pointer to the drawing context to use.
+//!
+//! This function flushes any cached drawing operations.  For display drivers
+//! that draw into a local frame buffer before writing to the actual display,
+//! calling this function will cause the display to be updated to match the
+//! contents of the local frame buffer.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#define GrFlush(pContext)                  \
+        do                                 \
+        {                                  \
+            const tContext *pC = pContext; \
+            DpyFlush(pC->pDisplay);        \
+        }                                  \
+        while(0)
+
+//*****************************************************************************
+//
+//! Gets the baseline of a font.
+//!
+//! \param pFont is a pointer to the font to query.
+//!
+//! This function determines the baseline position of a font.  The baseline is
+//! the offset between the top of the font and the bottom of the capital
+//! letters.  The only font data that exists below the baseline are the
+//! descenders on some lower-case letters (such as ``y'').
+//!
+//! \return Returns the baseline of the font, in pixels.
+//
+//*****************************************************************************
+#define GrFontBaselineGet(pFont) \
+        ((pFont)->ucBaseline)
+
+//*****************************************************************************
+//
+//! Gets the height of a font.
+//!
+//! \param pFont is a pointer to the font to query.
+//!
+//! This function determines the height of a font.  The height is the offset
+//! between the top of the font and the bottom of the font, including any
+//! ascenders and descenders.
+//!
+//! \return Returns the height of the font, in pixels.
+//
+//*****************************************************************************
+#define GrFontHeightGet(pFont) \
+        ((pFont)->ucHeight)
+
+//*****************************************************************************
+//
+//! Gets the maximum width of a font.
+//!
+//! \param pFont is a pointer to the font to query.
+//!
+//! This function determines the maximum width of a font.  The maximum width is
+//! the width of the widest individual character in the font.
+//!
+//! \return Returns the maximum width of the font, in pixels.
+//
+//*****************************************************************************
+#define GrFontMaxWidthGet(pFont) \
+        ((pFont)->ucMaxWidth)
+
+//*****************************************************************************
+//
+//! Gets the number of colors in an image.
+//!
+//! \param pucImage is a pointer to the image to query.
+//!
+//! This function determines the number of colors in the palette of an image.
+//! This is only valid for 4bpp and 8bpp images; 1bpp images do not contain a
+//! palette.
+//!
+//! \return Returns the number of colors in the image.
+//
+//*****************************************************************************
+#define GrImageColorsGet(pucImage)           \
+        (((unsigned char *)pucImage)[5] + 1)
+
+//*****************************************************************************
+//
+//! Gets the height of an image.
+//!
+//! \param pucImage is a pointer to the image to query.
+//!
+//! This function determines the height of an image in pixels.
+//!
+//! \return Returns the height of the image in pixels.
+//
+//*****************************************************************************
+#define GrImageHeightGet(pucImage)          \
+        (*(unsigned short *)(pucImage + 3))
+
+//*****************************************************************************
+//
+//! Gets the width of an image.
+//!
+//! \param pucImage is a pointer to the image to query.
+//!
+//! This function determines the width of an image in pixels.
+//!
+//! \return Returns the width of the image in pixels.
+//
+//*****************************************************************************
+#define GrImageWidthGet(pucImage)           \
+        (*(unsigned short *)(pucImage + 1))
+
+//*****************************************************************************
+//
+//! Determines the size of the buffer for a 1 BPP off-screen image.
+//!
+//! \param lWidth is the width of the image in pixels.
+//! \param lHeight is the height of the image in pixels.
+//!
+//! This function determines the size of the memory buffer required to hold a
+//! 1 BPP off-screen image of the specified geometry.
+//!
+//! \return Returns the number of bytes required by the image.
+//
+//*****************************************************************************
+#define GrOffScreen1BPPSize(lWidth, lHeight) \
+        (5 + (((lWidth + 7) / 8) * lHeight))
+
+//*****************************************************************************
+//
+//! Determines the size of the buffer for a 4 BPP off-screen image.
+//!
+//! \param lWidth is the width of the image in pixels.
+//! \param lHeight is the height of the image in pixels.
+//!
+//! This function determines the size of the memory buffer required to hold a
+//! 4 BPP off-screen image of the specified geometry.
+//!
+//! \return Returns the number of bytes required by the image.
+//
+//*****************************************************************************
+#define GrOffScreen4BPPSize(lWidth, lHeight)            \
+        (6 + (16 * 3) + (((lWidth + 1) / 2) * lHeight))
+
+//*****************************************************************************
+//
+//! Determines the size of the buffer for an 8 BPP off-screen image.
+//!
+//! \param lWidth is the width of the image in pixels.
+//! \param lHeight is the height of the image in pixels.
+//!
+//! This function determines the size of the memory buffer required to hold an
+//! 8 BPP off-screen image of the specified geometry.
+//!
+//! \return Returns the number of bytes required by the image.
+//
+//*****************************************************************************
+#define GrOffScreen8BPPSize(lWidth, lHeight) \
+        (6 + (256 * 3) + (lWidth * lHeight))
+
+//*****************************************************************************
+//
+//! Draws a pixel.
+//!
+//! \param pContext is a pointer to the drawing context to use.
+//! \param lX is the X coordinate of the pixel.
+//! \param lY is the Y coordinate of the pixel.
+//!
+//! This function draws a pixel if it resides within the clipping region.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#define GrPixelDraw(pContext, lX, lY)                                 \
+        do                                                            \
+        {                                                             \
+            const tContext *pC = pContext;                            \
+            if((lX >= pC->sClipRegion.sXMin) &&                       \
+               (lX <= pC->sClipRegion.sXMax) &&                       \
+               (lY >= pC->sClipRegion.sYMin) &&                       \
+               (lY <= pC->sClipRegion.sYMax))                         \
+            {                                                         \
+                DpyPixelDraw(pC->pDisplay, lX, lY, pC->ulForeground); \
+            }                                                         \
+        }                                                             \
+        while(0)
+
+//*****************************************************************************
+//
+//! Gets the baseline of a string.
+//!
+//! \param pContext is a pointer to the drawing context to query.
+//!
+//! This function determines the baseline position of a string.  The baseline
+//! is the offset between the top of the string and the bottom of the capital
+//! letters.  The only string data that exists below the baseline are the
+//! descenders on some lower-case letters (such as ``y'').
+//!
+//! \return Returns the baseline of the string, in pixels.
+//
+//*****************************************************************************
+#define GrStringBaselineGet(pContext)   \
+        ((pContext)->pFont->ucBaseline)
+
+//*****************************************************************************
+//
+//! Draws a centered string.
+//!
+//! \param pContext is a pointer to the drawing context to use.
+//! \param pcString is a pointer to the string to be drawn.
+//! \param lLength is the number of characters from the string that should be
+//! drawn on the screen.
+//! \param lX is the X coordinate of the center of the string position on the
+//! screen.
+//! \param lY is the Y coordinate of the center of the string position on the
+//! screen.
+//! \param bOpaque is \b true if the background of each character should be
+//! drawn and \b false if it should not (leaving the background as is).
+//!
+//! This function draws a string of test on the screen centered upon the
+//! provided position.  The \e lLength parameter allows a portion of the
+//! string to be examined without having to insert a NULL character at the
+//! stopping point (which would not be possible if the string was located in
+//! flash); specifying a length of -1 will cause the entire string to be
+//! rendered (subject to clipping).
+//!
+//! \return None.
+//
+//*****************************************************************************
+#define GrStringDrawCentered(pContext, pcString, lLength, lX, lY, bOpaque)  \
+        do                                                                  \
+        {                                                                   \
+            const tContext *pC = pContext;                                  \
+            const char *pcStr = pcString;                                   \
+                                                                            \
+            GrStringDraw(pC, pcStr, lLength,                                \
+                         (lX) - (GrStringWidthGet(pC, pcStr, lLength) / 2), \
+                         (lY) - (pC->pFont->ucBaseline / 2), bOpaque);      \
+        }                                                                   \
+        while(0)
+
+//*****************************************************************************
+//
+//! Gets the height of a string.
+//!
+//! \param pContext is a pointer to the drawing context to query.
+//!
+//! This function determines the height of a string.  The height is the offset
+//! between the top of the string and the bottom of the string, including any
+//! ascenders and descenders.  Note that this will not account for the case
+//! where the string in question does not have any characters that use
+//! descenders but the font in the drawing context does contain characters with
+//! descenders.
+//!
+//! \return Returns the height of the string, in pixels.
+//
+//*****************************************************************************
+#define GrStringHeightGet(pContext)   \
+        ((pContext)->pFont->ucHeight)
+
+//*****************************************************************************
+//
+//! Gets the maximum width of a character in a string.
+//!
+//! \param pContext is a pointer to the drawing context to query.
+//!
+//! This function determines the maximum width of a character in a string.  The
+//! maximum width is the width of the widest individual character in the font
+//! used to render the string, which may be wider than the widest character
+//! that is used to render a particular string.
+//!
+//! \return Returns the maximum width of a character in a string, in pixels.
+//
+//*****************************************************************************
+#define GrStringMaxWidthGet(pContext)   \
+        ((pContext)->pFont->ucMaxWidth)
+
+//*****************************************************************************
+//
+// A set of color definitions.  This set is the subset of the X11 colors (from
+// rgb.txt) that are supported by typical web browsers.
+//
+//*****************************************************************************
+#define ClrAliceBlue            0x00F0F8FF
+#define ClrAntiqueWhite         0x00FAEBD7
+#define ClrAqua                 0x0000FFFF
+#define ClrAquamarine           0x007FFFD4
+#define ClrAzure                0x00F0FFFF
+#define ClrBeige                0x00F5F5DC
+#define ClrBisque               0x00FFE4C4
+#define ClrBlack                0x00000000
+#define ClrBlanchedAlmond       0x00FFEBCD
+#define ClrBlue                 0x000000FF
+#define ClrBlueViolet           0x008A2BE2
+#define ClrBrown                0x00A52A2A
+#define ClrBurlyWood            0x00DEB887
+#define ClrCadetBlue            0x005F9EA0
+#define ClrChartreuse           0x007FFF00
+#define ClrChocolate            0x00D2691E
+#define ClrCoral                0x00FF7F50
+#define ClrCornflowerBlue       0x006495ED
+#define ClrCornsilk             0x00FFF8DC
+#define ClrCrimson              0x00DC143C
+#define ClrCyan                 0x0000FFFF
+#define ClrDarkBlue             0x0000008B
+#define ClrDarkCyan             0x00008B8B
+#define ClrDarkGoldenrod        0x00B8860B
+#define ClrDarkGray             0x00A9A9A9
+#define ClrDarkGreen            0x00006400
+#define ClrDarkKhaki            0x00BDB76B
+#define ClrDarkMagenta          0x008B008B
+#define ClrDarkOliveGreen       0x00556B2F
+#define ClrDarkOrange           0x00FF8C00
+#define ClrDarkOrchid           0x009932CC
+#define ClrDarkRed              0x008B0000
+#define ClrDarkSalmon           0x00E9967A
+#define ClrDarkSeaGreen         0x008FBC8F
+#define ClrDarkSlateBlue        0x00483D8B
+#define ClrDarkSlateGray        0x002F4F4F
+#define ClrDarkTurquoise        0x0000CED1
+#define ClrDarkViolet           0x009400D3
+#define ClrDeepPink             0x00FF1493
+#define ClrDeepSkyBlue          0x0000BFFF
+#define ClrDimGray              0x00696969
+#define ClrDodgerBlue           0x001E90FF
+#define ClrFireBrick            0x00B22222
+#define ClrFloralWhite          0x00FFFAF0
+#define ClrForestGreen          0x00228B22
+#define ClrFuchsia              0x00FF00FF
+#define ClrGainsboro            0x00DCDCDC
+#define ClrGhostWhite           0x00F8F8FF
+#define ClrGold                 0x00FFD700
+#define ClrGoldenrod            0x00DAA520
+#define ClrGray                 0x00808080
+#define ClrGreen                0x00008000
+#define ClrGreenYellow          0x00ADFF2F
+#define ClrHoneydew             0x00F0FFF0
+#define ClrHotPink              0x00FF69B4
+#define ClrIndianRed            0x00CD5C5C
+#define ClrIndigo               0x004B0082
+#define ClrIvory                0x00FFFFF0
+#define ClrKhaki                0x00F0E68C
+#define ClrLavender             0x00E6E6FA
+#define ClrLavenderBlush        0x00FFF0F5
+#define ClrLawnGreen            0x007CFC00
+#define ClrLemonChiffon         0x00FFFACD
+#define ClrLightBlue            0x00ADD8E6
+#define ClrLightCoral           0x00F08080
+#define ClrLightCyan            0x00E0FFFF
+#define ClrLightGoldenrodYellow 0x00FAFAD2
+#define ClrLightGreen           0x0090EE90
+#define ClrLightGrey            0x00D3D3D3
+#define ClrLightPink            0x00FFB6C1
+#define ClrLightSalmon          0x00FFA07A
+#define ClrLightSeaGreen        0x0020B2AA
+#define ClrLightSkyBlue         0x0087CEFA
+#define ClrLightSlateGray       0x00778899
+#define ClrLightSteelBlue       0x00B0C4DE
+#define ClrLightYellow          0x00FFFFE0
+#define ClrLime                 0x0000FF00
+#define ClrLimeGreen            0x0032CD32
+#define ClrLinen                0x00FAF0E6
+#define ClrMagenta              0x00FF00FF
+#define ClrMaroon               0x00800000
+#define ClrMediumAquamarine     0x0066CDAA
+#define ClrMediumBlue           0x000000CD
+#define ClrMediumOrchid         0x00BA55D3
+#define ClrMediumPurple         0x009370DB
+#define ClrMediumSeaGreen       0x003CB371
+#define ClrMediumSlateBlue      0x007B68EE
+#define ClrMediumSpringGreen    0x0000FA9A
+#define ClrMediumTurquoise      0x0048D1CC
+#define ClrMediumVioletRed      0x00C71585
+#define ClrMidnightBlue         0x00191970
+#define ClrMintCream            0x00F5FFFA
+#define ClrMistyRose            0x00FFE4E1
+#define ClrMoccasin             0x00FFE4B5
+#define ClrNavajoWhite          0x00FFDEAD
+#define ClrNavy                 0x00000080
+#define ClrOldLace              0x00FDF5E6
+#define ClrOlive                0x00808000
+#define ClrOliveDrab            0x006B8E23
+#define ClrOrange               0x00FFA500
+#define ClrOrangeRed            0x00FF4500
+#define ClrOrchid               0x00DA70D6
+#define ClrPaleGoldenrod        0x00EEE8AA
+#define ClrPaleGreen            0x0098FB98
+#define ClrPaleTurquoise        0x00AFEEEE
+#define ClrPaleVioletRed        0x00DB7093
+#define ClrPapayaWhip           0x00FFEFD5
+#define ClrPeachPuff            0x00FFDAB9
+#define ClrPeru                 0x00CD853F
+#define ClrPink                 0x00FFC0CB
+#define ClrPlum                 0x00DDA0DD
+#define ClrPowderBlue           0x00B0E0E6
+#define ClrPurple               0x00800080
+#define ClrRed                  0x00FF0000
+#define ClrRosyBrown            0x00BC8F8F
+#define ClrRoyalBlue            0x004169E1
+#define ClrSaddleBrown          0x008B4513
+#define ClrSalmon               0x00FA8072
+#define ClrSandyBrown           0x00F4A460
+#define ClrSeaGreen             0x002E8B57
+#define ClrSeashell             0x00FFF5EE
+#define ClrSienna               0x00A0522D
+#define ClrSilver               0x00C0C0C0
+#define ClrSkyBlue              0x0087CEEB
+#define ClrSlateBlue            0x006A5ACD
+#define ClrSlateGray            0x00708090
+#define ClrSnow                 0x00FFFAFA
+#define ClrSpringGreen          0x0000FF7F
+#define ClrSteelBlue            0x004682B4
+#define ClrTan                  0x00D2B48C
+#define ClrTeal                 0x00008080
+#define ClrThistle              0x00D8BFD8
+#define ClrTomato               0x00FF6347
+#define ClrTurquoise            0x0040E0D0
+#define ClrViolet               0x00EE82EE
+#define ClrWheat                0x00F5DEB3
+#define ClrWhite                0x00FFFFFF
+#define ClrWhiteSmoke           0x00F5F5F5
+#define ClrYellow               0x00FFFF00
+#define ClrYellowGreen          0x009ACD32
+
+//*****************************************************************************
+//
+// Masks and shifts to aid in color format translation by drivers.
+//
+//*****************************************************************************
+#define ClrRedMask              0x00FF0000
+#define ClrRedShift             16
+#define ClrGreenMask            0x0000FF00
+#define ClrGreenShift           8
+#define ClrBlueMask             0x000000FF
+#define ClrBlueShift            0
+
+//*****************************************************************************
+//
+// Prototypes for the predefined fonts in the graphics library.  ..Cm.. is the
+// computer modern font, which is a serif font.  ..Cmsc.. is the computer
+// modern small-caps font, which is also a serif font.  ..Cmss.. is the
+// computer modern sans-serif font.
+//
+//*****************************************************************************
+extern const tFont g_sFontCm12;
+extern const tFont g_sFontCm12b;
+extern const tFont g_sFontCm12i;
+extern const tFont g_sFontCm14;
+extern const tFont g_sFontCm14b;
+extern const tFont g_sFontCm14i;
+extern const tFont g_sFontCm16;
+extern const tFont g_sFontCm16b;
+extern const tFont g_sFontCm16i;
+extern const tFont g_sFontCm18;
+extern const tFont g_sFontCm18b;
+extern const tFont g_sFontCm18i;
+extern const tFont g_sFontCm20;
+extern const tFont g_sFontCm20b;
+extern const tFont g_sFontCm20i;
+extern const tFont g_sFontCm22;
+extern const tFont g_sFontCm22b;
+extern const tFont g_sFontCm22i;
+extern const tFont g_sFontCm24;
+extern const tFont g_sFontCm24b;
+extern const tFont g_sFontCm24i;
+extern const tFont g_sFontCm26;
+extern const tFont g_sFontCm26b;
+extern const tFont g_sFontCm26i;
+extern const tFont g_sFontCm28;
+extern const tFont g_sFontCm28b;
+extern const tFont g_sFontCm28i;
+extern const tFont g_sFontCm30;
+extern const tFont g_sFontCm30b;
+extern const tFont g_sFontCm30i;
+extern const tFont g_sFontCm32;
+extern const tFont g_sFontCm32b;
+extern const tFont g_sFontCm32i;
+extern const tFont g_sFontCm34;
+extern const tFont g_sFontCm34b;
+extern const tFont g_sFontCm34i;
+extern const tFont g_sFontCm36;
+extern const tFont g_sFontCm36b;
+extern const tFont g_sFontCm36i;
+extern const tFont g_sFontCm38;
+extern const tFont g_sFontCm38b;
+extern const tFont g_sFontCm38i;
+extern const tFont g_sFontCm40;
+extern const tFont g_sFontCm40b;
+extern const tFont g_sFontCm40i;
+extern const tFont g_sFontCm42;
+extern const tFont g_sFontCm42b;
+extern const tFont g_sFontCm42i;
+extern const tFont g_sFontCm44;
+extern const tFont g_sFontCm44b;
+extern const tFont g_sFontCm44i;
+extern const tFont g_sFontCm46;
+extern const tFont g_sFontCm46b;
+extern const tFont g_sFontCm46i;
+extern const tFont g_sFontCm48;
+extern const tFont g_sFontCm48b;
+extern const tFont g_sFontCm48i;
+extern const tFont g_sFontCmsc12;
+extern const tFont g_sFontCmsc14;
+extern const tFont g_sFontCmsc16;
+extern const tFont g_sFontCmsc18;
+extern const tFont g_sFontCmsc20;
+extern const tFont g_sFontCmsc22;
+extern const tFont g_sFontCmsc24;
+extern const tFont g_sFontCmsc26;
+extern const tFont g_sFontCmsc28;
+extern const tFont g_sFontCmsc30;
+extern const tFont g_sFontCmsc32;
+extern const tFont g_sFontCmsc34;
+extern const tFont g_sFontCmsc36;
+extern const tFont g_sFontCmsc38;
+extern const tFont g_sFontCmsc40;
+extern const tFont g_sFontCmsc42;
+extern const tFont g_sFontCmsc44;
+extern const tFont g_sFontCmsc46;
+extern const tFont g_sFontCmsc48;
+extern const tFont g_sFontCmss12;
+extern const tFont g_sFontCmss12b;
+extern const tFont g_sFontCmss12i;
+extern const tFont g_sFontCmss14;
+extern const tFont g_sFontCmss14b;
+extern const tFont g_sFontCmss14i;
+extern const tFont g_sFontCmss16;
+extern const tFont g_sFontCmss16b;
+extern const tFont g_sFontCmss16i;
+extern const tFont g_sFontCmss18;
+extern const tFont g_sFontCmss18b;
+extern const tFont g_sFontCmss18i;
+extern const tFont g_sFontCmss20;
+extern const tFont g_sFontCmss20b;
+extern const tFont g_sFontCmss20i;
+extern const tFont g_sFontCmss22;
+extern const tFont g_sFontCmss22b;
+extern const tFont g_sFontCmss22i;
+extern const tFont g_sFontCmss24;
+extern const tFont g_sFontCmss24b;
+extern const tFont g_sFontCmss24i;
+extern const tFont g_sFontCmss26;
+extern const tFont g_sFontCmss26b;
+extern const tFont g_sFontCmss26i;
+extern const tFont g_sFontCmss28;
+extern const tFont g_sFontCmss28b;
+extern const tFont g_sFontCmss28i;
+extern const tFont g_sFontCmss30;
+extern const tFont g_sFontCmss30b;
+extern const tFont g_sFontCmss30i;
+extern const tFont g_sFontCmss32;
+extern const tFont g_sFontCmss32b;
+extern const tFont g_sFontCmss32i;
+extern const tFont g_sFontCmss34;
+extern const tFont g_sFontCmss34b;
+extern const tFont g_sFontCmss34i;
+extern const tFont g_sFontCmss36;
+extern const tFont g_sFontCmss36b;
+extern const tFont g_sFontCmss36i;
+extern const tFont g_sFontCmss38;
+extern const tFont g_sFontCmss38b;
+extern const tFont g_sFontCmss38i;
+extern const tFont g_sFontCmss40;
+extern const tFont g_sFontCmss40b;
+extern const tFont g_sFontCmss40i;
+extern const tFont g_sFontCmss42;
+extern const tFont g_sFontCmss42b;
+extern const tFont g_sFontCmss42i;
+extern const tFont g_sFontCmss44;
+extern const tFont g_sFontCmss44b;
+extern const tFont g_sFontCmss44i;
+extern const tFont g_sFontCmss46;
+extern const tFont g_sFontCmss46b;
+extern const tFont g_sFontCmss46i;
+extern const tFont g_sFontCmss48;
+extern const tFont g_sFontCmss48b;
+extern const tFont g_sFontCmss48i;
+extern const tFont g_sFontFixed6x8;
+
+//*****************************************************************************
+//
+//! Translates a 24-bit RGB color to a display driver-specific color.
+//!
+//! \param pDisplay is the pointer to the display driver structure for the
+//! display to operate upon.
+//! \param ulValue is the 24-bit RGB color.  The least-significant byte is the
+//! blue channel, the next byte is the green channel, and the third byte is the
+//! red channel.
+//!
+//! This function translates a 24-bit RGB color into a value that can be
+//! written into the display's frame buffer in order to reproduce that color,
+//! or the closest possible approximation of that color.
+//!
+//! \return Returns the display-driver specific color.
+//
+//*****************************************************************************
+#define DpyColorTranslate(pDisplay, ulValue)                                \
+        ((pDisplay)->pfnColorTranslate((pDisplay)->pvDisplayData, ulValue))
+
+//*****************************************************************************
+//
+//! Flushes cached drawing operations.
+//!
+//! \param pDisplay is the pointer to the display driver structure for the
+//! display to operate upon.
+//!
+//! This function flushes any cached drawing operations on a display.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#define DpyFlush(pDisplay)                   \
+        do                                   \
+        {                                    \
+            const tDisplay *pD = pDisplay;   \
+            pD->pfnFlush(pD->pvDisplayData); \
+        }                                    \
+        while(0)
+
+//*****************************************************************************
+//
+//! Gets the height of the display.
+//!
+//! \param pDisplay is a pointer to the display driver structure for the
+//! display to query.
+//!
+//! This function determines the height of the display.
+//!
+//! \return Returns the height of the display in pixels.
+//
+//*****************************************************************************
+#define DpyHeightGet(pDisplay) \
+        ((pDisplay)->usHeight)
+
+//*****************************************************************************
+//
+//! Draws a horizontal line on a display.
+//!
+//! \param pDisplay is the pointer to the display driver structure for the
+//! display to operate upon.
+//! \param lX1 is the starting X coordinate of the line.
+//! \param lX2 is the ending X coordinate of the line.
+//! \param lY is the Y coordinate of the line.
+//! \param ulValue is the color to draw the line.
+//!
+//! This function draws a horizontal line on a display.  This assumes that
+//! clipping has already been performed, and that both end points of the line
+//! are within the extents of the display.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#define DpyLineDrawH(pDisplay, lX1, lX2, lY, ulValue)                   \
+        do                                                              \
+        {                                                               \
+            const tDisplay *pD = pDisplay;                              \
+            pD->pfnLineDrawH(pD->pvDisplayData, lX1, lX2, lY, ulValue); \
+        }                                                               \
+        while(0)
+
+//*****************************************************************************
+//
+//! Draws a vertical line on a display.
+//!
+//! \param pDisplay is the pointer to the display driver structure for the
+//! display to operate upon.
+//! \param lX is the X coordinate of the line.
+//! \param lY1 is the starting Y coordinate of the line.
+//! \param lY2 is the ending Y coordinate of the line.
+//! \param ulValue is the color to draw the line.
+//!
+//! This function draws a vertical line on a display.  This assumes that
+//! clipping has already been performed, and that both end points of the line
+//! are within the extents of the display.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#define DpyLineDrawV(pDisplay, lX, lY1, lY2, ulValue)                   \
+        do                                                              \
+        {                                                               \
+            const tDisplay *pD = pDisplay;                              \
+            pD->pfnLineDrawV(pD->pvDisplayData, lX, lY1, lY2, ulValue); \
+        }                                                               \
+        while(0)
+
+//*****************************************************************************
+//
+//! Draws a pixel on a display.
+//!
+//! \param pDisplay is the pointer to the display driver structure for the
+//! display to operate upon.
+//! \param lX is the X coordinate of the pixel.
+//! \param lY is the Y coordinate of the pixel.
+//! \param ulValue is the color to draw the pixel.
+//!
+//! This function draws a pixel on a display.  This assumes that clipping has
+//! already been performed.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#define DpyPixelDraw(pDisplay, lX, lY, ulValue)                   \
+        do                                                        \
+        {                                                         \
+            const tDisplay *pD = pDisplay;                        \
+            pD->pfnPixelDraw(pD->pvDisplayData, lX, lY, ulValue); \
+        }                                                         \
+        while(0)
+
+//*****************************************************************************
+//
+//! Draws a horizontal sequence of pixels on a display.
+//!
+//! \param pDisplay is the pointer to the display driver structure for the
+//! display to operate upon.
+//! \param lX is the X coordinate of the first pixel.
+//! \param lY is the Y coordinate of the first pixel.
+//! \param lX0 is sub-pixel offset within the pixel data, which is valid for 1
+//! or 4 bit per pixel formats.
+//! \param lCount is the number of pixels to draw.
+//! \param lBPP is the number of bits per pixel; must be 1, 4, or 8.
+//! \param pucData is a pointer to the pixel data.  For 1 and 4 bit per pixel
+//! formats, the most significant bit(s) represent the left-most pixel.
+//! \param pucPalette is a pointer to the palette used to draw the pixels.
+//!
+//! This function draws a horizontal sequence of pixels on a display, using the
+//! supplied palette.  For 1 bit per pixel format, the palette contains
+//! pre-translated colors; for 4 and 8 bit per pixel formats, the palette
+//! contains 24-bit RGB values that must be translated before being written to
+//! the display.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#define DpyPixelDrawMultiple(pDisplay, lX, lY, lX0, lCount, lBPP, pucData,   \
+                             pucPalette)                                     \
+        do                                                                   \
+        {                                                                    \
+            const tDisplay *pD = pDisplay;                                   \
+            pD->pfnPixelDrawMultiple(pD->pvDisplayData, lX, lY, lX0, lCount, \
+                                     lBPP, pucData, pucPalette);             \
+        }                                                                    \
+        while(0)
+
+//*****************************************************************************
+//
+//! Fills a rectangle on a display.
+//!
+//! \param pDisplay is the pointer to the display driver structure for the
+//! display to operate upon.
+//! \param pRect is a pointer to the structure describing the rectangle to
+//! fill.
+//! \param ulValue is the color to fill the rectangle.
+//!
+//! This function fills a rectangle on the display.  This assumes that clipping
+//! has already been performed, and that all sides of the rectangle are within
+//! the extents of the display.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#define DpyRectFill(pDisplay, pRect, ulValue)                   \
+        do                                                      \
+        {                                                       \
+            const tDisplay *pD = pDisplay;                      \
+            pD->pfnRectFill(pD->pvDisplayData, pRect, ulValue); \
+        }                                                       \
+        while(0)
+
+//*****************************************************************************
+//
+//! Gets the width of the display.
+//!
+//! \param pDisplay is a pointer to the display driver structure for the
+//! display to query.
+//!
+//! This function determines the width of the display.
+//!
+//! \return Returns the width of the display in pixels.
+//
+//*****************************************************************************
+#define DpyWidthGet(pDisplay) \
+        ((pDisplay)->usWidth)
+
+//*****************************************************************************
+//
+// Prototypes for the graphics library functions.
+//
+//*****************************************************************************
+extern void GrCircleDraw(const tContext *pContext, long lX, long lY,
+                         long lRadius);
+extern void GrCircleFill(const tContext *pContext, long lX, long lY,
+                         long lRadius);
+extern void GrContextClipRegionSet(tContext *pContext, tRectangle *pRect);
+extern void GrContextInit(tContext *pContext, const tDisplay *pDisplay);
+extern void GrImageDraw(const tContext *pContext,
+                        const unsigned char *pucImage, long lX, long lY);
+extern void GrLineDraw(const tContext *pContext, long lX1, long lY1, long lX2,
+                       long lY2);
+extern void GrLineDrawH(const tContext *pContext, long lX1, long lX2, long lY);
+extern void GrLineDrawV(const tContext *pContext, long lX, long lY1, long lY2);
+extern void GrOffScreen1BPPInit(tDisplay *pDisplay, unsigned char *pucImage,
+                                long lWidth, long lHeight);
+extern void GrOffScreen4BPPInit(tDisplay *pDisplay, unsigned char *pucImage,
+                                long lWidth, long lHeight);
+extern void GrOffScreen4BPPPaletteSet(tDisplay *pDisplay,
+                                      unsigned long *pulPalette,
+                                      unsigned long ulOffset,
+                                      unsigned long ulCount);
+extern void GrOffScreen8BPPInit(tDisplay *pDisplay, unsigned char *pucImage,
+                                long lWidth, long lHeight);
+extern void GrOffScreen8BPPPaletteSet(tDisplay *pDisplay,
+                                      unsigned long *pulPalette,
+                                      unsigned long ulOffset,
+                                      unsigned long ulCount);
+extern void GrRectDraw(const tContext *pContext, const tRectangle *pRect);
+extern void GrRectFill(const tContext *pContext, const tRectangle *pRect);
+extern void GrStringDraw(const tContext *pContext, const char *pcString,
+                         long lLength, long lX, long lY,
+                         unsigned long bOpaque);
+extern long GrStringWidthGet(const tContext *pContext, const char *pcString,
+                             long lLength);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __GRLIB_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hibernate.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hibernate.h
new file mode 100644
index 0000000..d17bfbe
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hibernate.h
@@ -0,0 +1,131 @@
+//*****************************************************************************
+//
+// hibernate.h - API definition for the Hibernation module.
+//
+// Copyright (c) 2007-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HIBERNATE_H__
+#define __HIBERNATE_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Macros needed for selecting the clock source for HibernateClockSelect()
+//
+//*****************************************************************************
+#define HIBERNATE_CLOCK_SEL_RAW         0x04
+#define HIBERNATE_CLOCK_SEL_DIV128      0x00
+
+//*****************************************************************************
+//
+// Macros need to configure wake events for HibernateWakeSet()
+//
+//*****************************************************************************
+#define HIBERNATE_WAKE_PIN              0x10
+#define HIBERNATE_WAKE_RTC              0x08
+
+//*****************************************************************************
+//
+// Macros needed to configure low battery detect for HibernateLowBatSet()
+//
+//*****************************************************************************
+#define HIBERNATE_LOW_BAT_DETECT        0x20
+#define HIBERNATE_LOW_BAT_ABORT         0xA0
+
+//*****************************************************************************
+//
+// Macros defining interrupt source bits for the interrupt functions.
+//
+//*****************************************************************************
+#define HIBERNATE_INT_PIN_WAKE          0x08
+#define HIBERNATE_INT_LOW_BAT           0x04
+#define HIBERNATE_INT_RTC_MATCH_0       0x01
+#define HIBERNATE_INT_RTC_MATCH_1       0x02
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void HibernateEnableExpClk(unsigned long ulHibClk);
+extern void HibernateDisable(void);
+extern void HibernateClockSelect(unsigned long ulClockInput);
+extern void HibernateRTCEnable(void);
+extern void HibernateRTCDisable(void);
+extern void HibernateWakeSet(unsigned long ulWakeFlags);
+extern unsigned long HibernateWakeGet(void);
+extern void HibernateLowBatSet(unsigned long ulLowBatFlags);
+extern unsigned long HibernateLowBatGet(void);
+extern void HibernateRTCSet(unsigned long ulRTCValue);
+extern unsigned long HibernateRTCGet(void);
+extern void HibernateRTCMatch0Set(unsigned long ulMatch);
+extern unsigned long HibernateRTCMatch0Get(void);
+extern void HibernateRTCMatch1Set(unsigned long ulMatch);
+extern unsigned long HibernateRTCMatch1Get(void);
+extern void HibernateRTCTrimSet(unsigned long ulTrim);
+extern unsigned long HibernateRTCTrimGet(void);
+extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount);
+extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount);
+extern void HibernateRequest(void);
+extern void HibernateIntEnable(unsigned long ulIntFlags);
+extern void HibernateIntDisable(unsigned long ulIntFlags);
+extern void HibernateIntRegister(void (*pfnHandler)(void));
+extern void HibernateIntUnregister(void);
+extern unsigned long HibernateIntStatus(tBoolean bMasked);
+extern void HibernateIntClear(unsigned long ulIntFlags);
+extern unsigned int HibernateIsActive(void);
+
+//*****************************************************************************
+//
+// Several Hibernate module APIs have been renamed, with the original function
+// name being deprecated.  These defines provide backward compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#include "sysctl.h"
+#define HibernateEnable(a)                         \
+        HibernateEnableExpClk(a, SysCtlClockGet())
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // __HIBERNATE_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_adc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_adc.h
new file mode 100644
index 0000000..69427a3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_adc.h
@@ -0,0 +1,614 @@
+//*****************************************************************************
+//
+// hw_adc.h - Macros used when accessing the ADC hardware.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HW_ADC_H__
+#define __HW_ADC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the ADC register offsets.
+//
+//*****************************************************************************
+#define ADC_O_ACTSS             0x00000000  // Active sample register
+#define ADC_O_RIS               0x00000004  // Raw interrupt status register
+#define ADC_O_IM                0x00000008  // Interrupt mask register
+#define ADC_O_ISC               0x0000000C  // Interrupt status/clear register
+#define ADC_O_OSTAT             0x00000010  // Overflow status register
+#define ADC_O_EMUX              0x00000014  // Event multiplexer select reg.
+#define ADC_O_USTAT             0x00000018  // Underflow status register
+#define ADC_O_SSPRI             0x00000020  // Channel priority register
+#define ADC_O_PSSI              0x00000028  // Processor sample initiate reg.
+#define ADC_O_SAC               0x00000030  // Sample Averaging Control reg.
+#define ADC_O_SSMUX0            0x00000040  // Multiplexer select 0 register
+#define ADC_O_SSCTL0            0x00000044  // Sample sequence control 0 reg.
+#define ADC_O_SSFIFO0           0x00000048  // Result FIFO 0 register
+#define ADC_O_SSFSTAT0          0x0000004C  // FIFO 0 status register
+#define ADC_O_SSMUX1            0x00000060  // Multiplexer select 1 register
+#define ADC_O_SSCTL1            0x00000064  // Sample sequence control 1 reg.
+#define ADC_O_SSFIFO1           0x00000068  // Result FIFO 1 register
+#define ADC_O_SSFSTAT1          0x0000006C  // FIFO 1 status register
+#define ADC_O_SSMUX2            0x00000080  // Multiplexer select 2 register
+#define ADC_O_SSCTL2            0x00000084  // Sample sequence control 2 reg.
+#define ADC_O_SSFIFO2           0x00000088  // Result FIFO 2 register
+#define ADC_O_SSFSTAT2          0x0000008C  // FIFO 2 status register
+#define ADC_O_SSMUX3            0x000000A0  // Multiplexer select 3 register
+#define ADC_O_SSCTL3            0x000000A4  // Sample sequence control 3 reg.
+#define ADC_O_SSFIFO3           0x000000A8  // Result FIFO 3 register
+#define ADC_O_SSFSTAT3          0x000000AC  // FIFO 3 status register
+#define ADC_O_TMLB              0x00000100  // Test mode loopback register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_ACTSS register.
+//
+//*****************************************************************************
+#define ADC_ACTSS_ASEN3         0x00000008  // Sample sequence 3 enable
+#define ADC_ACTSS_ASEN2         0x00000004  // Sample sequence 2 enable
+#define ADC_ACTSS_ASEN1         0x00000002  // Sample sequence 1 enable
+#define ADC_ACTSS_ASEN0         0x00000001  // Sample sequence 0 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_RIS register.
+//
+//*****************************************************************************
+#define ADC_RIS_INR3            0x00000008  // Sample sequence 3 interrupt
+#define ADC_RIS_INR2            0x00000004  // Sample sequence 2 interrupt
+#define ADC_RIS_INR1            0x00000002  // Sample sequence 1 interrupt
+#define ADC_RIS_INR0            0x00000001  // Sample sequence 0 interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_IM register.
+//
+//*****************************************************************************
+#define ADC_IM_MASK3            0x00000008  // Sample sequence 3 mask
+#define ADC_IM_MASK2            0x00000004  // Sample sequence 2 mask
+#define ADC_IM_MASK1            0x00000002  // Sample sequence 1 mask
+#define ADC_IM_MASK0            0x00000001  // Sample sequence 0 mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_ISC register.
+//
+//*****************************************************************************
+#define ADC_ISC_IN3             0x00000008  // Sample sequence 3 interrupt
+#define ADC_ISC_IN2             0x00000004  // Sample sequence 2 interrupt
+#define ADC_ISC_IN1             0x00000002  // Sample sequence 1 interrupt
+#define ADC_ISC_IN0             0x00000001  // Sample sequence 0 interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_OSTAT register.
+//
+//*****************************************************************************
+#define ADC_OSTAT_OV3           0x00000008  // Sample sequence 3 overflow
+#define ADC_OSTAT_OV2           0x00000004  // Sample sequence 2 overflow
+#define ADC_OSTAT_OV1           0x00000002  // Sample sequence 1 overflow
+#define ADC_OSTAT_OV0           0x00000001  // Sample sequence 0 overflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_EMUX register.
+//
+//*****************************************************************************
+#define ADC_EMUX_EM3_M          0x0000F000  // Event mux 3 mask
+#define ADC_EMUX_EM3_PROCESSOR  0x00000000  // Processor event
+#define ADC_EMUX_EM3_COMP0      0x00001000  // Analog comparator 0 event
+#define ADC_EMUX_EM3_COMP1      0x00002000  // Analog comparator 1 event
+#define ADC_EMUX_EM3_COMP2      0x00003000  // Analog comparator 2 event
+#define ADC_EMUX_EM3_EXTERNAL   0x00004000  // External event
+#define ADC_EMUX_EM3_TIMER      0x00005000  // Timer event
+#define ADC_EMUX_EM3_PWM0       0x00006000  // PWM0 event
+#define ADC_EMUX_EM3_PWM1       0x00007000  // PWM1 event
+#define ADC_EMUX_EM3_PWM2       0x00008000  // PWM2 event
+#define ADC_EMUX_EM3_ALWAYS     0x0000F000  // Always event
+#define ADC_EMUX_EM2_M          0x00000F00  // Event mux 2 mask
+#define ADC_EMUX_EM2_PROCESSOR  0x00000000  // Processor event
+#define ADC_EMUX_EM2_COMP0      0x00000100  // Analog comparator 0 event
+#define ADC_EMUX_EM2_COMP1      0x00000200  // Analog comparator 1 event
+#define ADC_EMUX_EM2_COMP2      0x00000300  // Analog comparator 2 event
+#define ADC_EMUX_EM2_EXTERNAL   0x00000400  // External event
+#define ADC_EMUX_EM2_TIMER      0x00000500  // Timer event
+#define ADC_EMUX_EM2_PWM0       0x00000600  // PWM0 event
+#define ADC_EMUX_EM2_PWM1       0x00000700  // PWM1 event
+#define ADC_EMUX_EM2_PWM2       0x00000800  // PWM2 event
+#define ADC_EMUX_EM2_ALWAYS     0x00000F00  // Always event
+#define ADC_EMUX_EM1_M          0x000000F0  // Event mux 1 mask
+#define ADC_EMUX_EM1_PROCESSOR  0x00000000  // Processor event
+#define ADC_EMUX_EM1_COMP0      0x00000010  // Analog comparator 0 event
+#define ADC_EMUX_EM1_COMP1      0x00000020  // Analog comparator 1 event
+#define ADC_EMUX_EM1_COMP2      0x00000030  // Analog comparator 2 event
+#define ADC_EMUX_EM1_EXTERNAL   0x00000040  // External event
+#define ADC_EMUX_EM1_TIMER      0x00000050  // Timer event
+#define ADC_EMUX_EM1_PWM0       0x00000060  // PWM0 event
+#define ADC_EMUX_EM1_PWM1       0x00000070  // PWM1 event
+#define ADC_EMUX_EM1_PWM2       0x00000080  // PWM2 event
+#define ADC_EMUX_EM1_ALWAYS     0x000000F0  // Always event
+#define ADC_EMUX_EM0_M          0x0000000F  // Event mux 0 mask
+#define ADC_EMUX_EM0_PROCESSOR  0x00000000  // Processor event
+#define ADC_EMUX_EM0_COMP0      0x00000001  // Analog comparator 0 event
+#define ADC_EMUX_EM0_COMP1      0x00000002  // Analog comparator 1 event
+#define ADC_EMUX_EM0_COMP2      0x00000003  // Analog comparator 2 event
+#define ADC_EMUX_EM0_EXTERNAL   0x00000004  // External event
+#define ADC_EMUX_EM0_TIMER      0x00000005  // Timer event
+#define ADC_EMUX_EM0_PWM0       0x00000006  // PWM0 event
+#define ADC_EMUX_EM0_PWM1       0x00000007  // PWM1 event
+#define ADC_EMUX_EM0_PWM2       0x00000008  // PWM2 event
+#define ADC_EMUX_EM0_ALWAYS     0x0000000F  // Always event
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_USTAT register.
+//
+//*****************************************************************************
+#define ADC_USTAT_UV3           0x00000008  // Sample sequence 3 underflow
+#define ADC_USTAT_UV2           0x00000004  // Sample sequence 2 underflow
+#define ADC_USTAT_UV1           0x00000002  // Sample sequence 1 underflow
+#define ADC_USTAT_UV0           0x00000001  // Sample sequence 0 underflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_SSPRI register.
+//
+//*****************************************************************************
+#define ADC_SSPRI_SS3_M         0x00003000  // Sequencer 3 priority mask
+#define ADC_SSPRI_SS3_1ST       0x00000000  // First priority
+#define ADC_SSPRI_SS3_2ND       0x00001000  // Second priority
+#define ADC_SSPRI_SS3_3RD       0x00002000  // Third priority
+#define ADC_SSPRI_SS3_4TH       0x00003000  // Fourth priority
+#define ADC_SSPRI_SS2_M         0x00000300  // Sequencer 2 priority mask
+#define ADC_SSPRI_SS2_1ST       0x00000000  // First priority
+#define ADC_SSPRI_SS2_2ND       0x00000100  // Second priority
+#define ADC_SSPRI_SS2_3RD       0x00000200  // Third priority
+#define ADC_SSPRI_SS2_4TH       0x00000300  // Fourth priority
+#define ADC_SSPRI_SS1_M         0x00000030  // Sequencer 1 priority mask
+#define ADC_SSPRI_SS1_1ST       0x00000000  // First priority
+#define ADC_SSPRI_SS1_2ND       0x00000010  // Second priority
+#define ADC_SSPRI_SS1_3RD       0x00000020  // Third priority
+#define ADC_SSPRI_SS1_4TH       0x00000030  // Fourth priority
+#define ADC_SSPRI_SS0_M         0x00000003  // Sequencer 0 priority mask
+#define ADC_SSPRI_SS0_1ST       0x00000000  // First priority
+#define ADC_SSPRI_SS0_2ND       0x00000001  // Second priority
+#define ADC_SSPRI_SS0_3RD       0x00000002  // Third priority
+#define ADC_SSPRI_SS0_4TH       0x00000003  // Fourth priority
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_PSSI register.
+//
+//*****************************************************************************
+#define ADC_PSSI_SS3            0x00000008  // Trigger sample sequencer 3
+#define ADC_PSSI_SS2            0x00000004  // Trigger sample sequencer 2
+#define ADC_PSSI_SS1            0x00000002  // Trigger sample sequencer 1
+#define ADC_PSSI_SS0            0x00000001  // Trigger sample sequencer 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_SAC register.
+//
+//*****************************************************************************
+#define ADC_SAC_AVG_M           0x00000007  // Hardware Averaging Control.
+#define ADC_SAC_AVG_64X         0x00000006  // 64x hardware oversampling
+#define ADC_SAC_AVG_32X         0x00000005  // 32x hardware oversampling
+#define ADC_SAC_AVG_16X         0x00000004  // 16x hardware oversampling
+#define ADC_SAC_AVG_8X          0x00000003  // 8x hardware oversampling
+#define ADC_SAC_AVG_4X          0x00000002  // 4x hardware oversampling
+#define ADC_SAC_AVG_2X          0x00000001  // 2x hardware oversampling
+#define ADC_SAC_AVG_OFF         0x00000000  // No hardware oversampling
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_TMLB register.
+//
+//*****************************************************************************
+#define ADC_TMLB_CNT_M          0x000003C0  // Continuous Sample Counter.
+#define ADC_TMLB_CONT           0x00000020  // Continuation Sample Indicator.
+#define ADC_TMLB_DIFF           0x00000010  // Differential Sample Indicator.
+#define ADC_TMLB_TS             0x00000008  // Temp Sensor Sample Indicator.
+#define ADC_TMLB_MUX_M          0x00000007  // Analog Input Indicator.
+#define ADC_TMLB_LB             0x00000001  // Loopback control signals
+#define ADC_TMLB_CNT_S          6           // Sample counter shift
+#define ADC_TMLB_MUX_S          0           // Input channel number shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX0_MUX7_M       0x70000000  // 8th Sample Input Select.
+#define ADC_SSMUX0_MUX6_M       0x07000000  // 7th Sample Input Select.
+#define ADC_SSMUX0_MUX5_M       0x00700000  // 6th Sample Input Select.
+#define ADC_SSMUX0_MUX4_M       0x00070000  // 5th Sample Input Select.
+#define ADC_SSMUX0_MUX3_M       0x00007000  // 4th Sample Input Select.
+#define ADC_SSMUX0_MUX2_M       0x00000700  // 3rd Sample Input Select.
+#define ADC_SSMUX0_MUX1_M       0x00000070  // 2nd Sample Input Select.
+#define ADC_SSMUX0_MUX0_M       0x00000007  // 1st Sample Input Select.
+#define ADC_SSMUX0_MUX7_S       28
+#define ADC_SSMUX0_MUX6_S       24
+#define ADC_SSMUX0_MUX5_S       20
+#define ADC_SSMUX0_MUX4_S       16
+#define ADC_SSMUX0_MUX3_S       12
+#define ADC_SSMUX0_MUX2_S       8
+#define ADC_SSMUX0_MUX1_S       4
+#define ADC_SSMUX0_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL0_TS7          0x80000000  // 8th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE7          0x40000000  // 8th Sample Interrupt Enable.
+#define ADC_SSCTL0_END7         0x20000000  // 8th Sample is End of Sequence.
+#define ADC_SSCTL0_D7           0x10000000  // 8th Sample Diff Input Select.
+#define ADC_SSCTL0_TS6          0x08000000  // 7th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE6          0x04000000  // 7th Sample Interrupt Enable.
+#define ADC_SSCTL0_END6         0x02000000  // 7th Sample is End of Sequence.
+#define ADC_SSCTL0_D6           0x01000000  // 7th Sample Diff Input Select.
+#define ADC_SSCTL0_TS5          0x00800000  // 6th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE5          0x00400000  // 6th Sample Interrupt Enable.
+#define ADC_SSCTL0_END5         0x00200000  // 6th Sample is End of Sequence.
+#define ADC_SSCTL0_D5           0x00100000  // 6th Sample Diff Input Select.
+#define ADC_SSCTL0_TS4          0x00080000  // 5th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE4          0x00040000  // 5th Sample Interrupt Enable.
+#define ADC_SSCTL0_END4         0x00020000  // 5th Sample is End of Sequence.
+#define ADC_SSCTL0_D4           0x00010000  // 5th Sample Diff Input Select.
+#define ADC_SSCTL0_TS3          0x00008000  // 4th Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE3          0x00004000  // 4th Sample Interrupt Enable.
+#define ADC_SSCTL0_END3         0x00002000  // 4th Sample is End of Sequence.
+#define ADC_SSCTL0_D3           0x00001000  // 4th Sample Diff Input Select.
+#define ADC_SSCTL0_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE2          0x00000400  // 3rd Sample Interrupt Enable.
+#define ADC_SSCTL0_END2         0x00000200  // 3rd Sample is End of Sequence.
+#define ADC_SSCTL0_D2           0x00000100  // 3rd Sample Diff Input Select.
+#define ADC_SSCTL0_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE1          0x00000040  // 2nd Sample Interrupt Enable.
+#define ADC_SSCTL0_END1         0x00000020  // 2nd Sample is End of Sequence.
+#define ADC_SSCTL0_D1           0x00000010  // 2nd Sample Diff Input Select.
+#define ADC_SSCTL0_TS0          0x00000008  // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL0_IE0          0x00000004  // 1st Sample Interrupt Enable.
+#define ADC_SSCTL0_END0         0x00000002  // 1st Sample is End of Sequence.
+#define ADC_SSCTL0_D0           0x00000001  // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO0_DATA_M      0x000003FF  // Conversion Result Data.
+#define ADC_SSFIFO0_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT0_FULL       0x00001000  // FIFO Full.
+#define ADC_SSFSTAT0_EMPTY      0x00000100  // FIFO Empty.
+#define ADC_SSFSTAT0_HPTR_M     0x000000F0  // FIFO Head Pointer.
+#define ADC_SSFSTAT0_TPTR_M     0x0000000F  // FIFO Tail Pointer.
+#define ADC_SSFSTAT0_HPTR_S     4
+#define ADC_SSFSTAT0_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX1_MUX3_M       0x00007000  // 4th Sample Input Select.
+#define ADC_SSMUX1_MUX2_M       0x00000700  // 3rd Sample Input Select.
+#define ADC_SSMUX1_MUX1_M       0x00000070  // 2nd Sample Input Select.
+#define ADC_SSMUX1_MUX0_M       0x00000007  // 1st Sample Input Select.
+#define ADC_SSMUX1_MUX3_S       12
+#define ADC_SSMUX1_MUX2_S       8
+#define ADC_SSMUX1_MUX1_S       4
+#define ADC_SSMUX1_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL1_TS3          0x00008000  // 4th Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE3          0x00004000  // 4th Sample Interrupt Enable.
+#define ADC_SSCTL1_END3         0x00002000  // 4th Sample is End of Sequence.
+#define ADC_SSCTL1_D3           0x00001000  // 4th Sample Diff Input Select.
+#define ADC_SSCTL1_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE2          0x00000400  // 3rd Sample Interrupt Enable.
+#define ADC_SSCTL1_END2         0x00000200  // 3rd Sample is End of Sequence.
+#define ADC_SSCTL1_D2           0x00000100  // 3rd Sample Diff Input Select.
+#define ADC_SSCTL1_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE1          0x00000040  // 2nd Sample Interrupt Enable.
+#define ADC_SSCTL1_END1         0x00000020  // 2nd Sample is End of Sequence.
+#define ADC_SSCTL1_D1           0x00000010  // 2nd Sample Diff Input Select.
+#define ADC_SSCTL1_TS0          0x00000008  // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL1_IE0          0x00000004  // 1st Sample Interrupt Enable.
+#define ADC_SSCTL1_END0         0x00000002  // 1st Sample is End of Sequence.
+#define ADC_SSCTL1_D0           0x00000001  // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO1_DATA_M      0x000003FF  // Conversion Result Data.
+#define ADC_SSFIFO1_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT1_FULL       0x00001000  // FIFO Full.
+#define ADC_SSFSTAT1_EMPTY      0x00000100  // FIFO Empty.
+#define ADC_SSFSTAT1_HPTR_M     0x000000F0  // FIFO Head Pointer.
+#define ADC_SSFSTAT1_TPTR_M     0x0000000F  // FIFO Tail Pointer.
+#define ADC_SSFSTAT1_HPTR_S     4
+#define ADC_SSFSTAT1_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX2_MUX3_M       0x00007000  // 4th Sample Input Select.
+#define ADC_SSMUX2_MUX2_M       0x00000700  // 3rd Sample Input Select.
+#define ADC_SSMUX2_MUX1_M       0x00000070  // 2nd Sample Input Select.
+#define ADC_SSMUX2_MUX0_M       0x00000007  // 1st Sample Input Select.
+#define ADC_SSMUX2_MUX3_S       12
+#define ADC_SSMUX2_MUX2_S       8
+#define ADC_SSMUX2_MUX1_S       4
+#define ADC_SSMUX2_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL2_TS3          0x00008000  // 4th Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE3          0x00004000  // 4th Sample Interrupt Enable.
+#define ADC_SSCTL2_END3         0x00002000  // 4th Sample is End of Sequence.
+#define ADC_SSCTL2_D3           0x00001000  // 4th Sample Diff Input Select.
+#define ADC_SSCTL2_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE2          0x00000400  // 3rd Sample Interrupt Enable.
+#define ADC_SSCTL2_END2         0x00000200  // 3rd Sample is End of Sequence.
+#define ADC_SSCTL2_D2           0x00000100  // 3rd Sample Diff Input Select.
+#define ADC_SSCTL2_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE1          0x00000040  // 2nd Sample Interrupt Enable.
+#define ADC_SSCTL2_END1         0x00000020  // 2nd Sample is End of Sequence.
+#define ADC_SSCTL2_D1           0x00000010  // 2nd Sample Diff Input Select.
+#define ADC_SSCTL2_TS0          0x00000008  // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL2_IE0          0x00000004  // 1st Sample Interrupt Enable.
+#define ADC_SSCTL2_END0         0x00000002  // 1st Sample is End of Sequence.
+#define ADC_SSCTL2_D0           0x00000001  // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO2_DATA_M      0x000003FF  // Conversion Result Data.
+#define ADC_SSFIFO2_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT2_FULL       0x00001000  // FIFO Full.
+#define ADC_SSFSTAT2_EMPTY      0x00000100  // FIFO Empty.
+#define ADC_SSFSTAT2_HPTR_M     0x000000F0  // FIFO Head Pointer.
+#define ADC_SSFSTAT2_TPTR_M     0x0000000F  // FIFO Tail Pointer.
+#define ADC_SSFSTAT2_HPTR_S     4
+#define ADC_SSFSTAT2_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX3_MUX0_M       0x00000007  // 1st Sample Input Select.
+#define ADC_SSMUX3_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL3_TS0          0x00000008  // 1st Sample Temp Sensor Select.
+#define ADC_SSCTL3_IE0          0x00000004  // 1st Sample Interrupt Enable.
+#define ADC_SSCTL3_END0         0x00000002  // 1st Sample is End of Sequence.
+#define ADC_SSCTL3_D0           0x00000001  // 1st Sample Diff Input Select.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO3_DATA_M      0x000003FF  // Conversion Result Data.
+#define ADC_SSFIFO3_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT3_FULL       0x00001000  // FIFO Full.
+#define ADC_SSFSTAT3_EMPTY      0x00000100  // FIFO Empty.
+#define ADC_SSFSTAT3_HPTR_M     0x000000F0  // FIFO Head Pointer.
+#define ADC_SSFSTAT3_TPTR_M     0x0000000F  // FIFO Tail Pointer.
+#define ADC_SSFSTAT3_HPTR_S     4
+#define ADC_SSFSTAT3_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the ADC sequence register offsets.
+//
+//*****************************************************************************
+#define ADC_O_SEQ               0x00000040  // Offset to the first sequence
+#define ADC_O_SEQ_STEP          0x00000020  // Increment to the next sequence
+#define ADC_O_X_SSFSTAT         0x0000000C  // FIFO status register
+#define ADC_O_X_SSFIFO          0x00000008  // Result FIFO register
+#define ADC_O_X_SSCTL           0x00000004  // Sample sequence control register
+#define ADC_O_X_SSMUX           0x00000000  // Multiplexer select register
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_EMUX
+// register.
+//
+//*****************************************************************************
+#define ADC_EMUX_EM3_MASK       0x0000F000  // Event mux 3 mask
+#define ADC_EMUX_EM2_MASK       0x00000F00  // Event mux 2 mask
+#define ADC_EMUX_EM1_MASK       0x000000F0  // Event mux 1 mask
+#define ADC_EMUX_EM0_MASK       0x0000000F  // Event mux 0 mask
+#define ADC_EMUX_EM3_SHIFT      12          // The shift for the fourth event
+#define ADC_EMUX_EM2_SHIFT      8           // The shift for the third event
+#define ADC_EMUX_EM1_SHIFT      4           // The shift for the second event
+#define ADC_EMUX_EM0_SHIFT      0           // The shift for the first event
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_SSPRI
+// register.
+//
+//*****************************************************************************
+#define ADC_SSPRI_SS3_MASK      0x00003000  // Sequencer 3 priority mask
+#define ADC_SSPRI_SS2_MASK      0x00000300  // Sequencer 2 priority mask
+#define ADC_SSPRI_SS1_MASK      0x00000030  // Sequencer 1 priority mask
+#define ADC_SSPRI_SS0_MASK      0x00000003  // Sequencer 0 priority mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_SSMUX0,
+// ADC_SSMUX1, ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present
+// in all registers.
+//
+//*****************************************************************************
+#define ADC_SSMUX_MUX7_MASK     0x70000000  // 8th mux select mask
+#define ADC_SSMUX_MUX6_MASK     0x07000000  // 7th mux select mask
+#define ADC_SSMUX_MUX5_MASK     0x00700000  // 6th mux select mask
+#define ADC_SSMUX_MUX4_MASK     0x00070000  // 5th mux select mask
+#define ADC_SSMUX_MUX3_MASK     0x00007000  // 4th mux select mask
+#define ADC_SSMUX_MUX2_MASK     0x00000700  // 3rd mux select mask
+#define ADC_SSMUX_MUX1_MASK     0x00000070  // 2nd mux select mask
+#define ADC_SSMUX_MUX0_MASK     0x00000007  // 1st mux select mask
+#define ADC_SSMUX_MUX7_SHIFT    28
+#define ADC_SSMUX_MUX6_SHIFT    24
+#define ADC_SSMUX_MUX5_SHIFT    20
+#define ADC_SSMUX_MUX4_SHIFT    16
+#define ADC_SSMUX_MUX3_SHIFT    12
+#define ADC_SSMUX_MUX2_SHIFT    8
+#define ADC_SSMUX_MUX1_SHIFT    4
+#define ADC_SSMUX_MUX0_SHIFT    0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_SSCTL0,
+// ADC_SSCTL1, ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present
+// in all registers.
+//
+//*****************************************************************************
+#define ADC_SSCTL_TS7           0x80000000  // 8th temperature sensor select
+#define ADC_SSCTL_IE7           0x40000000  // 8th interrupt enable
+#define ADC_SSCTL_END7          0x20000000  // 8th sequence end select
+#define ADC_SSCTL_D7            0x10000000  // 8th differential select
+#define ADC_SSCTL_TS6           0x08000000  // 7th temperature sensor select
+#define ADC_SSCTL_IE6           0x04000000  // 7th interrupt enable
+#define ADC_SSCTL_END6          0x02000000  // 7th sequence end select
+#define ADC_SSCTL_D6            0x01000000  // 7th differential select
+#define ADC_SSCTL_TS5           0x00800000  // 6th temperature sensor select
+#define ADC_SSCTL_IE5           0x00400000  // 6th interrupt enable
+#define ADC_SSCTL_END5          0x00200000  // 6th sequence end select
+#define ADC_SSCTL_D5            0x00100000  // 6th differential select
+#define ADC_SSCTL_TS4           0x00080000  // 5th temperature sensor select
+#define ADC_SSCTL_IE4           0x00040000  // 5th interrupt enable
+#define ADC_SSCTL_END4          0x00020000  // 5th sequence end select
+#define ADC_SSCTL_D4            0x00010000  // 5th differential select
+#define ADC_SSCTL_TS3           0x00008000  // 4th temperature sensor select
+#define ADC_SSCTL_IE3           0x00004000  // 4th interrupt enable
+#define ADC_SSCTL_END3          0x00002000  // 4th sequence end select
+#define ADC_SSCTL_D3            0x00001000  // 4th differential select
+#define ADC_SSCTL_TS2           0x00000800  // 3rd temperature sensor select
+#define ADC_SSCTL_IE2           0x00000400  // 3rd interrupt enable
+#define ADC_SSCTL_END2          0x00000200  // 3rd sequence end select
+#define ADC_SSCTL_D2            0x00000100  // 3rd differential select
+#define ADC_SSCTL_TS1           0x00000080  // 2nd temperature sensor select
+#define ADC_SSCTL_IE1           0x00000040  // 2nd interrupt enable
+#define ADC_SSCTL_END1          0x00000020  // 2nd sequence end select
+#define ADC_SSCTL_D1            0x00000010  // 2nd differential select
+#define ADC_SSCTL_TS0           0x00000008  // 1st temperature sensor select
+#define ADC_SSCTL_IE0           0x00000004  // 1st interrupt enable
+#define ADC_SSCTL_END0          0x00000002  // 1st sequence end select
+#define ADC_SSCTL_D0            0x00000001  // 1st differential select
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_SSFIFO0,
+// ADC_SSFIFO1, ADC_SSFIFO2, and ADC_SSFIFO3 registers.
+//
+//*****************************************************************************
+#define ADC_SSFIFO_DATA_MASK    0x000003FF  // Sample data
+#define ADC_SSFIFO_DATA_SHIFT   0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_SSFSTAT0,
+// ADC_SSFSTAT1, ADC_SSFSTAT2, and ADC_SSFSTAT3 registers.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT_FULL        0x00001000  // FIFO is full
+#define ADC_SSFSTAT_EMPTY       0x00000100  // FIFO is empty
+#define ADC_SSFSTAT_HPTR        0x000000F0  // FIFO head pointer
+#define ADC_SSFSTAT_TPTR        0x0000000F  // FIFO tail pointer
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the loopback ADC
+// data.
+//
+//*****************************************************************************
+#define ADC_LB_CNT_MASK         0x000003C0  // Sample counter mask
+#define ADC_LB_CONT             0x00000020  // Continuation sample
+#define ADC_LB_DIFF             0x00000010  // Differential sample
+#define ADC_LB_TS               0x00000008  // Temperature sensor sample
+#define ADC_LB_MUX_MASK         0x00000007  // Input channel number mask
+#define ADC_LB_CNT_SHIFT        6           // Sample counter shift
+#define ADC_LB_MUX_SHIFT        0           // Input channel number shift
+
+#endif
+
+#endif // __HW_ADC_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_can.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_can.h
new file mode 100644
index 0000000..bc64f0d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_can.h
@@ -0,0 +1,757 @@
+//*****************************************************************************
+//
+// hw_can.h - Defines and macros used when accessing the can.
+//
+// Copyright (c) 2006-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HW_CAN_H__
+#define __HW_CAN_H__
+
+//*****************************************************************************
+//
+// The following are defines for the CAN register offsets.
+//
+//*****************************************************************************
+#define CAN_O_CTL               0x00000000  // Control register
+#define CAN_O_STS               0x00000004  // Status register
+#define CAN_O_ERR               0x00000008  // Error register
+#define CAN_O_BIT               0x0000000C  // Bit Timing register
+#define CAN_O_INT               0x00000010  // Interrupt register
+#define CAN_O_TST               0x00000014  // Test register
+#define CAN_O_BRPE              0x00000018  // Baud Rate Prescaler register
+#define CAN_O_IF1CRQ            0x00000020  // Interface 1 Command Request reg.
+#define CAN_O_IF1CMSK           0x00000024  // Interface 1 Command Mask reg.
+#define CAN_O_IF1MSK1           0x00000028  // Interface 1 Mask 1 register
+#define CAN_O_IF1MSK2           0x0000002C  // Interface 1 Mask 2 register
+#define CAN_O_IF1ARB1           0x00000030  // Interface 1 Arbitration 1 reg.
+#define CAN_O_IF1ARB2           0x00000034  // Interface 1 Arbitration 2 reg.
+#define CAN_O_IF1MCTL           0x00000038  // Interface 1 Message Control reg.
+#define CAN_O_IF1DA1            0x0000003C  // Interface 1 DataA 1 register
+#define CAN_O_IF1DA2            0x00000040  // Interface 1 DataA 2 register
+#define CAN_O_IF1DB1            0x00000044  // Interface 1 DataB 1 register
+#define CAN_O_IF1DB2            0x00000048  // Interface 1 DataB 2 register
+#define CAN_O_IF2CRQ            0x00000080  // Interface 2 Command Request reg.
+#define CAN_O_IF2CMSK           0x00000084  // Interface 2 Command Mask reg.
+#define CAN_O_IF2MSK1           0x00000088  // Interface 2 Mask 1 register
+#define CAN_O_IF2MSK2           0x0000008C  // Interface 2 Mask 2 register
+#define CAN_O_IF2ARB1           0x00000090  // Interface 2 Arbitration 1 reg.
+#define CAN_O_IF2ARB2           0x00000094  // Interface 2 Arbitration 2 reg.
+#define CAN_O_IF2MCTL           0x00000098  // Interface 2 Message Control reg.
+#define CAN_O_IF2DA1            0x0000009C  // Interface 2 DataA 1 register
+#define CAN_O_IF2DA2            0x000000A0  // Interface 2 DataA 2 register
+#define CAN_O_IF2DB1            0x000000A4  // Interface 2 DataB 1 register
+#define CAN_O_IF2DB2            0x000000A8  // Interface 2 DataB 2 register
+#define CAN_O_TXRQ1             0x00000100  // Transmission Request 1 register
+#define CAN_O_TXRQ2             0x00000104  // Transmission Request 2 register
+#define CAN_O_NWDA1             0x00000120  // New Data 1 register
+#define CAN_O_NWDA2             0x00000124  // New Data 2 register
+#define CAN_O_MSG1INT           0x00000140  // CAN Message 1 Interrupt Pending
+#define CAN_O_MSG2INT           0x00000144  // CAN Message 2 Interrupt Pending
+#define CAN_O_MSG1VAL           0x00000160  // CAN Message 1 Valid
+#define CAN_O_MSG2VAL           0x00000164  // CAN Message 2 Valid
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_CTL register.
+//
+//*****************************************************************************
+#define CAN_CTL_TEST            0x00000080  // Test mode enable
+#define CAN_CTL_CCE             0x00000040  // Configuration change enable
+#define CAN_CTL_DAR             0x00000020  // Disable automatic retransmission
+#define CAN_CTL_EIE             0x00000008  // Error interrupt enable
+#define CAN_CTL_SIE             0x00000004  // Status change interrupt enable
+#define CAN_CTL_IE              0x00000002  // Module interrupt enable
+#define CAN_CTL_INIT            0x00000001  // Initialization
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_STS register.
+//
+//*****************************************************************************
+#define CAN_STS_BOFF            0x00000080  // Bus Off status
+#define CAN_STS_EWARN           0x00000040  // Error Warning status
+#define CAN_STS_EPASS           0x00000020  // Error Passive status
+#define CAN_STS_RXOK            0x00000010  // Received Message Successful
+#define CAN_STS_TXOK            0x00000008  // Transmitted Message Successful
+#define CAN_STS_LEC_M           0x00000007  // Last Error Code
+#define CAN_STS_LEC_NONE        0x00000000  // No error
+#define CAN_STS_LEC_STUFF       0x00000001  // Stuff error
+#define CAN_STS_LEC_FORM        0x00000002  // Form(at) error
+#define CAN_STS_LEC_ACK         0x00000003  // Ack error
+#define CAN_STS_LEC_BIT1        0x00000004  // Bit 1 error
+#define CAN_STS_LEC_BIT0        0x00000005  // Bit 0 error
+#define CAN_STS_LEC_CRC         0x00000006  // CRC error
+#define CAN_STS_LEC_NOEVENT     0x00000007  // Unused
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_ERR register.
+//
+//*****************************************************************************
+#define CAN_ERR_RP              0x00008000  // Receive error passive status
+#define CAN_ERR_REC_M           0x00007F00  // Receive Error Counter.
+#define CAN_ERR_TEC_M           0x000000FF  // Transmit Error Counter.
+#define CAN_ERR_REC_S           8           // Receive error counter bit pos
+#define CAN_ERR_TEC_S           0           // Transmit error counter bit pos
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_BIT register.
+//
+//*****************************************************************************
+#define CAN_BIT_TSEG2_M         0x00007000  // Time Segment after Sample Point.
+#define CAN_BIT_TSEG1_M         0x00000F00  // Time Segment Before Sample
+                                            // Point.
+#define CAN_BIT_SJW_M           0x000000C0  // (Re)Synchronization Jump Width.
+#define CAN_BIT_BRP_M           0x0000003F  // Baud Rate Prescalar.
+#define CAN_BIT_TSEG2_S         12
+#define CAN_BIT_TSEG1_S         8
+#define CAN_BIT_SJW_S           6
+#define CAN_BIT_BRP_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_INT register.
+//
+//*****************************************************************************
+#define CAN_INT_INTID_M         0x0000FFFF  // Interrupt Identifier.
+#define CAN_INT_INTID_NONE      0x00000000  // No Interrupt Pending
+#define CAN_INT_INTID_STATUS    0x00008000  // Status Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_TST register.
+//
+//*****************************************************************************
+#define CAN_TST_RX              0x00000080  // CAN_RX pin status
+#define CAN_TST_TX_M            0x00000060  // Overide control of CAN_TX pin
+#define CAN_TST_TX_CANCTL       0x00000000  // CAN core controls CAN_TX
+#define CAN_TST_TX_SAMPLE       0x00000020  // Sample Point on CAN_TX
+#define CAN_TST_TX_DOMINANT     0x00000040  // Dominant value on CAN_TX
+#define CAN_TST_TX_RECESSIVE    0x00000060  // Recessive value on CAN_TX
+#define CAN_TST_LBACK           0x00000010  // Loop back mode
+#define CAN_TST_SILENT          0x00000008  // Silent mode
+#define CAN_TST_BASIC           0x00000004  // Basic mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_BRPE register.
+//
+//*****************************************************************************
+#define CAN_BRPE_BRPE_M         0x0000000F  // Baud Rate Prescalar Extension.
+#define CAN_BRPE_BRPE_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_TXRQ1 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ1_TXRQST_M      0x0000FFFF  // Transmission Request Bits.
+#define CAN_TXRQ1_TXRQST_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_TXRQ2 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ2_TXRQST_M      0x0000FFFF  // Transmission Request Bits.
+#define CAN_TXRQ2_TXRQST_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_NWDA1 register.
+//
+//*****************************************************************************
+#define CAN_NWDA1_NEWDAT_M      0x0000FFFF  // New Data Bits.
+#define CAN_NWDA1_NEWDAT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_NWDA2 register.
+//
+//*****************************************************************************
+#define CAN_NWDA2_NEWDAT_M      0x0000FFFF  // New Data Bits.
+#define CAN_NWDA2_NEWDAT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF1CRQ_BUSY         0x00008000  // Busy Flag.
+#define CAN_IF1CRQ_MNUM_M       0x0000003F  // Message Number.
+#define CAN_IF1CRQ_MNUM_RSVD    0x00000000  // 0 is not a valid message number;
+                                            // it is interpreted as 0x20, or
+                                            // object 32.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF1CMSK_WRNRD       0x00000080  // Write, Not Read.
+#define CAN_IF1CMSK_MASK        0x00000040  // Access Mask Bits.
+#define CAN_IF1CMSK_ARB         0x00000020  // Access Arbitration Bits.
+#define CAN_IF1CMSK_CONTROL     0x00000010  // Access Control Bits.
+#define CAN_IF1CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit.
+#define CAN_IF1CMSK_NEWDAT      0x00000004  // Access New Data.
+#define CAN_IF1CMSK_TXRQST      0x00000004  // Access Transmission Request.
+#define CAN_IF1CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3.
+#define CAN_IF1CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask.
+#define CAN_IF1MSK1_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK2_MXTD        0x00008000  // Mask Extended Identifier.
+#define CAN_IF1MSK2_MDIR        0x00004000  // Mask Message Direction.
+#define CAN_IF1MSK2_IDMSK_M     0x00001FFF  // Identifier Mask.
+#define CAN_IF1MSK2_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB1_ID_M        0x0000FFFF  // Message Identifier.
+#define CAN_IF1ARB1_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB2_MSGVAL      0x00008000  // Message Valid.
+#define CAN_IF1ARB2_XTD         0x00004000  // Extended Identifier.
+#define CAN_IF1ARB2_DIR         0x00002000  // Message Direction.
+#define CAN_IF1ARB2_ID_M        0x00001FFF  // Message Identifier.
+#define CAN_IF1ARB2_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF1MCTL_NEWDAT      0x00008000  // New Data.
+#define CAN_IF1MCTL_MSGLST      0x00004000  // Message Lost.
+#define CAN_IF1MCTL_INTPND      0x00002000  // Interrupt Pending.
+#define CAN_IF1MCTL_UMASK       0x00001000  // Use Acceptance Mask.
+#define CAN_IF1MCTL_TXIE        0x00000800  // Transmit Interrupt Enable.
+#define CAN_IF1MCTL_RXIE        0x00000400  // Receive Interrupt Enable.
+#define CAN_IF1MCTL_RMTEN       0x00000200  // Remote Enable.
+#define CAN_IF1MCTL_TXRQST      0x00000100  // Transmit Request.
+#define CAN_IF1MCTL_EOB         0x00000080  // End of Buffer.
+#define CAN_IF1MCTL_DLC_M       0x0000000F  // Data Length Code.
+#define CAN_IF1MCTL_DLC_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA1_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF1DA1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA2_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF1DA2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB1_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF1DB1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB2_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF1DB2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF2CRQ_BUSY         0x00008000  // Busy Flag.
+#define CAN_IF2CRQ_MNUM_M       0x0000003F  // Message Number.
+#define CAN_IF2CRQ_MNUM_RSVD    0x00000000  // 0 is not a valid message number;
+                                            // it is interpreted as 0x20, or
+                                            // object 32.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF2CMSK_WRNRD       0x00000080  // Write, Not Read.
+#define CAN_IF2CMSK_MASK        0x00000040  // Access Mask Bits.
+#define CAN_IF2CMSK_ARB         0x00000020  // Access Arbitration Bits.
+#define CAN_IF2CMSK_CONTROL     0x00000010  // Access Control Bits.
+#define CAN_IF2CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit.
+#define CAN_IF2CMSK_NEWDAT      0x00000004  // Access New Data.
+#define CAN_IF2CMSK_TXRQST      0x00000004  // Access Transmission Request.
+#define CAN_IF2CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3.
+#define CAN_IF2CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask.
+#define CAN_IF2MSK1_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK2_MXTD        0x00008000  // Mask Extended Identifier.
+#define CAN_IF2MSK2_MDIR        0x00004000  // Mask Message Direction.
+#define CAN_IF2MSK2_IDMSK_M     0x00001FFF  // Identifier Mask.
+#define CAN_IF2MSK2_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB1_ID_M        0x0000FFFF  // Message Identifier.
+#define CAN_IF2ARB1_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB2_MSGVAL      0x00008000  // Message Valid.
+#define CAN_IF2ARB2_XTD         0x00004000  // Extended Identifier.
+#define CAN_IF2ARB2_DIR         0x00002000  // Message Direction.
+#define CAN_IF2ARB2_ID_M        0x00001FFF  // Message Identifier.
+#define CAN_IF2ARB2_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF2MCTL_NEWDAT      0x00008000  // New Data.
+#define CAN_IF2MCTL_MSGLST      0x00004000  // Message Lost.
+#define CAN_IF2MCTL_INTPND      0x00002000  // Interrupt Pending.
+#define CAN_IF2MCTL_UMASK       0x00001000  // Use Acceptance Mask.
+#define CAN_IF2MCTL_TXIE        0x00000800  // Transmit Interrupt Enable.
+#define CAN_IF2MCTL_RXIE        0x00000400  // Receive Interrupt Enable.
+#define CAN_IF2MCTL_RMTEN       0x00000200  // Remote Enable.
+#define CAN_IF2MCTL_TXRQST      0x00000100  // Transmit Request.
+#define CAN_IF2MCTL_EOB         0x00000080  // End of Buffer.
+#define CAN_IF2MCTL_DLC_M       0x0000000F  // Data Length Code.
+#define CAN_IF2MCTL_DLC_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA1_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF2DA1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA2_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF2DA2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB1_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF2DB1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB2_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF2DB2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1INT register.
+//
+//*****************************************************************************
+#define CAN_MSG1INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits.
+#define CAN_MSG1INT_INTPND_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2INT register.
+//
+//*****************************************************************************
+#define CAN_MSG2INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits.
+#define CAN_MSG2INT_INTPND_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG1VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits.
+#define CAN_MSG1VAL_MSGVAL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG2VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits.
+#define CAN_MSG2VAL_MSGVAL_S    0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the CAN register offsets.
+//
+//*****************************************************************************
+#define CAN_O_MSGINT1           0x00000140  // Intr. Pending in Msg Obj 1 reg.
+#define CAN_O_MSGINT2           0x00000144  // Intr. Pending in Msg Obj 2 reg.
+#define CAN_O_MSGVAL1           0x00000160  // Message Valid in Msg Obj 1 reg.
+#define CAN_O_MSGVAL2           0x00000164  // Message Valid in Msg Obj 2 reg.
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values of the can
+// registers.
+//
+//*****************************************************************************
+#define CAN_RV_IF1MSK2          0x0000FFFF
+#define CAN_RV_IF1MSK1          0x0000FFFF
+#define CAN_RV_IF2MSK1          0x0000FFFF
+#define CAN_RV_IF2MSK2          0x0000FFFF
+#define CAN_RV_BIT              0x00002301
+#define CAN_RV_CTL              0x00000001
+#define CAN_RV_IF1CRQ           0x00000001
+#define CAN_RV_IF2CRQ           0x00000001
+#define CAN_RV_TXRQ2            0x00000000
+#define CAN_RV_IF2DB1           0x00000000
+#define CAN_RV_INT              0x00000000
+#define CAN_RV_IF1DB2           0x00000000
+#define CAN_RV_BRPE             0x00000000
+#define CAN_RV_IF2DA2           0x00000000
+#define CAN_RV_MSGVAL2          0x00000000
+#define CAN_RV_TXRQ1            0x00000000
+#define CAN_RV_IF1MCTL          0x00000000
+#define CAN_RV_IF1DB1           0x00000000
+#define CAN_RV_STS              0x00000000
+#define CAN_RV_MSGINT1          0x00000000
+#define CAN_RV_IF1DA2           0x00000000
+#define CAN_RV_TST              0x00000000
+#define CAN_RV_IF1ARB1          0x00000000
+#define CAN_RV_IF1ARB2          0x00000000
+#define CAN_RV_NWDA2            0x00000000
+#define CAN_RV_IF2CMSK          0x00000000
+#define CAN_RV_NWDA1            0x00000000
+#define CAN_RV_IF1DA1           0x00000000
+#define CAN_RV_IF2DA1           0x00000000
+#define CAN_RV_IF2MCTL          0x00000000
+#define CAN_RV_MSGVAL1          0x00000000
+#define CAN_RV_IF1CMSK          0x00000000
+#define CAN_RV_ERR              0x00000000
+#define CAN_RV_IF2ARB2          0x00000000
+#define CAN_RV_MSGINT2          0x00000000
+#define CAN_RV_IF2ARB1          0x00000000
+#define CAN_RV_IF2DB2           0x00000000
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_STS
+// register.
+//
+//*****************************************************************************
+#define CAN_STS_LEC_MSK         0x00000007  // Last Error Code
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_ERR
+// register.
+//
+//*****************************************************************************
+#define CAN_ERR_REC_MASK        0x00007F00  // Receive error counter status
+#define CAN_ERR_TEC_MASK        0x000000FF  // Transmit error counter status
+#define CAN_ERR_REC_SHIFT       8           // Receive error counter bit pos
+#define CAN_ERR_TEC_SHIFT       0           // Transmit error counter bit pos
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_BIT
+// register.
+//
+//*****************************************************************************
+#define CAN_BIT_TSEG2           0x00007000  // Time segment after sample point
+#define CAN_BIT_TSEG1           0x00000F00  // Time segment before sample point
+#define CAN_BIT_SJW             0x000000C0  // (Re)Synchronization jump width
+#define CAN_BIT_BRP             0x0000003F  // Baud rate prescaler
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_INT
+// register.
+//
+//*****************************************************************************
+#define CAN_INT_INTID_MSK       0x0000FFFF  // Interrupt Identifier
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_TST
+// register.
+//
+//*****************************************************************************
+#define CAN_TST_TX_MSK          0x00000060  // Overide control of CAN_TX pin
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_BRPE
+// register.
+//
+//*****************************************************************************
+#define CAN_BRPE_BRPE           0x0000000F  // Baud rate prescaler extension
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1CRQ
+// and CAN_IF1CRQ registers.
+// Note: All bits may not be available in all registers
+//
+//*****************************************************************************
+#define CAN_IFCRQ_BUSY          0x00008000  // Busy flag status
+#define CAN_IFCRQ_MNUM_MSK      0x0000003F  // Message Number
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1CMSK
+// and CAN_IF2CMSK registers.
+// Note: All bits may not be available in all registers
+//
+//*****************************************************************************
+#define CAN_IFCMSK_WRNRD        0x00000080  // Write, not Read
+#define CAN_IFCMSK_MASK         0x00000040  // Access Mask Bits
+#define CAN_IFCMSK_ARB          0x00000020  // Access Arbitration Bits
+#define CAN_IFCMSK_CONTROL      0x00000010  // Access Control Bits
+#define CAN_IFCMSK_CLRINTPND    0x00000008  // Clear interrupt pending Bit
+#define CAN_IFCMSK_TXRQST       0x00000004  // Access Tx request bit (WRNRD=1)
+#define CAN_IFCMSK_NEWDAT       0x00000004  // Access New Data bit (WRNRD=0)
+#define CAN_IFCMSK_DATAA        0x00000002  // DataA access - bytes 0 to 3
+#define CAN_IFCMSK_DATAB        0x00000001  // DataB access - bytes 4 to 7
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1MSK1
+// and CAN_IF2MSK1 registers.
+// Note: All bits may not be available in all registers
+//
+//*****************************************************************************
+#define CAN_IFMSK1_MSK          0x0000FFFF  // Identifier Mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1MSK2
+// and CAN_IF2MSK2 registers.
+// Note: All bits may not be available in all registers
+//
+//*****************************************************************************
+#define CAN_IFMSK2_MXTD         0x00008000  // Mask extended identifier
+#define CAN_IFMSK2_MDIR         0x00004000  // Mask message direction
+#define CAN_IFMSK2_MSK          0x00001FFF  // Mask identifier
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1ARB1
+// and CAN_IF2ARB1 registers.
+// Note: All bits may not be available in all registers
+//
+//*****************************************************************************
+#define CAN_IFARB1_ID           0x0000FFFF  // Identifier
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1ARB2
+// and CAN_IF2ARB2 registers.
+// Note: All bits may not be available in all registers
+//
+//*****************************************************************************
+#define CAN_IFARB2_MSGVAL       0x00008000  // Message valid
+#define CAN_IFARB2_XTD          0x00004000  // Extended identifier
+#define CAN_IFARB2_DIR          0x00002000  // Message direction
+#define CAN_IFARB2_ID           0x00001FFF  // Message identifier
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1MCTL
+// and CAN_IF2MCTL registers.
+// Note: All bits may not be available in all registers
+//
+//*****************************************************************************
+#define CAN_IFMCTL_NEWDAT       0x00008000  // New Data
+#define CAN_IFMCTL_MSGLST       0x00004000  // Message lost
+#define CAN_IFMCTL_INTPND       0x00002000  // Interrupt pending
+#define CAN_IFMCTL_UMASK        0x00001000  // Use acceptance mask
+#define CAN_IFMCTL_TXIE         0x00000800  // Transmit interrupt enable
+#define CAN_IFMCTL_RXIE         0x00000400  // Receive interrupt enable
+#define CAN_IFMCTL_RMTEN        0x00000200  // Remote enable
+#define CAN_IFMCTL_TXRQST       0x00000100  // Transmit request
+#define CAN_IFMCTL_EOB          0x00000080  // End of buffer
+#define CAN_IFMCTL_DLC          0x0000000F  // Data length code
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1DA1
+// and CAN_IF2DA1 registers.
+// Note: All bits may not be available in all registers
+//
+//*****************************************************************************
+#define CAN_IFDA1_DATA          0x0000FFFF  // Data - bytes 1 and 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1DA2
+// and CAN_IF2DA2 registers.
+// Note: All bits may not be available in all registers
+//
+//*****************************************************************************
+#define CAN_IFDA2_DATA          0x0000FFFF  // Data - bytes 3 and 2
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1DB1
+// and CAN_IF2DB1 registers.
+// Note: All bits may not be available in all registers
+//
+//*****************************************************************************
+#define CAN_IFDB1_DATA          0x0000FFFF  // Data - bytes 5 and 4
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1DB2
+// and CAN_IF2DB2 registers.
+// Note: All bits may not be available in all registers
+//
+//*****************************************************************************
+#define CAN_IFDB2_DATA          0x0000FFFF  // Data - bytes 7 and 6
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_TXRQ1
+// register.
+//
+//*****************************************************************************
+#define CAN_TXRQ1_TXRQST        0x0000FFFF  // Transmission Request Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_TXRQ2
+// register.
+//
+//*****************************************************************************
+#define CAN_TXRQ2_TXRQST        0x0000FFFF  // Transmission Request Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_NWDA1
+// register.
+//
+//*****************************************************************************
+#define CAN_NWDA1_NEWDATA       0x0000FFFF  // New Data Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_NWDA2
+// register.
+//
+//*****************************************************************************
+#define CAN_NWDA2_NEWDATA       0x0000FFFF  // New Data Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_MSGINT1
+// register.
+//
+//*****************************************************************************
+#define CAN_MSGINT1_INTPND      0x0000FFFF  // Interrupt Pending Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_MSGINT2
+// register.
+//
+//*****************************************************************************
+#define CAN_MSGINT2_INTPND      0x0000FFFF  // Interrupt Pending Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_MSGVAL1
+// register.
+//
+//*****************************************************************************
+#define CAN_MSGVAL1_MSGVAL      0x0000FFFF  // Message Valid Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_MSGVAL2
+// register.
+//
+//*****************************************************************************
+#define CAN_MSGVAL2_MSGVAL      0x0000FFFF  // Message Valid Bits
+
+#endif
+
+#endif // __HW_CAN_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_comp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_comp.h
new file mode 100644
index 0000000..2109bb7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_comp.h
@@ -0,0 +1,278 @@
+//*****************************************************************************
+//
+// hw_comp.h - Macros used when accessing the comparator hardware.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HW_COMP_H__
+#define __HW_COMP_H__
+
+//*****************************************************************************
+//
+// The following are defines for the comparator register offsets.
+//
+//*****************************************************************************
+#define COMP_O_ACMIS            0x00000000  // Analog Comparator Masked
+                                            // Interrupt Status
+#define COMP_O_ACRIS            0x00000004  // Analog Comparator Raw Interrupt
+                                            // Status
+#define COMP_O_ACINTEN          0x00000008  // Analog Comparator Interrupt
+                                            // Enable
+#define COMP_O_ACREFCTL         0x00000010  // Analog Comparator Reference
+                                            // Voltage Control
+#define COMP_O_ACSTAT0          0x00000020  // Comp0 status register
+#define COMP_O_ACCTL0           0x00000024  // Comp0 control register
+#define COMP_O_ACSTAT1          0x00000040  // Comp1 status register
+#define COMP_O_ACCTL1           0x00000044  // Comp1 control register
+#define COMP_O_ACSTAT2          0x00000060  // Comp2 status register
+#define COMP_O_ACCTL2           0x00000064  // Comp2 control register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACMIS register.
+//
+//*****************************************************************************
+#define COMP_ACMIS_IN2          0x00000004  // Comparator 2 Masked Interrupt
+                                            // Status.
+#define COMP_ACMIS_IN1          0x00000002  // Comparator 1 Masked Interrupt
+                                            // Status.
+#define COMP_ACMIS_IN0          0x00000001  // Comparator 0 Masked Interrupt
+                                            // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACRIS register.
+//
+//*****************************************************************************
+#define COMP_ACRIS_IN2          0x00000004  // Comparator 2 Interrupt Status.
+#define COMP_ACRIS_IN1          0x00000002  // Comparator 1 Interrupt Status.
+#define COMP_ACRIS_IN0          0x00000001  // Comparator 0 Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACINTEN register.
+//
+//*****************************************************************************
+#define COMP_ACINTEN_IN2        0x00000004  // Comparator 2 Interrupt Enable.
+#define COMP_ACINTEN_IN1        0x00000002  // Comparator 1 Interrupt Enable.
+#define COMP_ACINTEN_IN0        0x00000001  // Comparator 0 Interrupt Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACREFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_ACREFCTL_EN        0x00000200  // Resistor Ladder Enable.
+#define COMP_ACREFCTL_RNG       0x00000100  // Resistor Ladder Range.
+#define COMP_ACREFCTL_VREF_M    0x0000000F  // Resistor Ladder Voltage Ref.
+#define COMP_ACREFCTL_VREF_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT0_OVAL       0x00000002  // Comparator Output Value.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL0_TOEN        0x00000800  // Trigger Output Enable.
+#define COMP_ACCTL0_ASRCP_M     0x00000600  // Analog Source Positive.
+#define COMP_ACCTL0_ASRCP_PIN   0x00000000  // Pin value
+#define COMP_ACCTL0_ASRCP_PIN0  0x00000200  // Pin value of C0+
+#define COMP_ACCTL0_ASRCP_REF   0x00000400  // Internal voltage reference
+#define COMP_ACCTL0_TSLVAL      0x00000080  // Trigger Sense Level Value.
+#define COMP_ACCTL0_TSEN_M      0x00000060  // Trigger Sense.
+#define COMP_ACCTL0_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
+#define COMP_ACCTL0_TSEN_FALL   0x00000020  // Falling edge
+#define COMP_ACCTL0_TSEN_RISE   0x00000040  // Rising edge
+#define COMP_ACCTL0_TSEN_BOTH   0x00000060  // Either edge
+#define COMP_ACCTL0_ISLVAL      0x00000010  // Interrupt Sense Level Value.
+#define COMP_ACCTL0_ISEN_M      0x0000000C  // Interrupt Sense.
+#define COMP_ACCTL0_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
+#define COMP_ACCTL0_ISEN_FALL   0x00000004  // Falling edge
+#define COMP_ACCTL0_ISEN_RISE   0x00000008  // Rising edge
+#define COMP_ACCTL0_ISEN_BOTH   0x0000000C  // Either edge
+#define COMP_ACCTL0_CINV        0x00000002  // Comparator Output Invert.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT1_OVAL       0x00000002  // Comparator Output Value.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL1_TOEN        0x00000800  // Trigger Output Enable.
+#define COMP_ACCTL1_ASRCP_M     0x00000600  // Analog Source Positive.
+#define COMP_ACCTL1_ASRCP_PIN   0x00000000  // Pin value
+#define COMP_ACCTL1_ASRCP_PIN0  0x00000200  // Pin value of C0+
+#define COMP_ACCTL1_ASRCP_REF   0x00000400  // Internal voltage reference
+#define COMP_ACCTL1_TSLVAL      0x00000080  // Trigger Sense Level Value.
+#define COMP_ACCTL1_TSEN_M      0x00000060  // Trigger Sense.
+#define COMP_ACCTL1_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
+#define COMP_ACCTL1_TSEN_FALL   0x00000020  // Falling edge
+#define COMP_ACCTL1_TSEN_RISE   0x00000040  // Rising edge
+#define COMP_ACCTL1_TSEN_BOTH   0x00000060  // Either edge
+#define COMP_ACCTL1_ISLVAL      0x00000010  // Interrupt Sense Level Value.
+#define COMP_ACCTL1_ISEN_M      0x0000000C  // Interrupt Sense.
+#define COMP_ACCTL1_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
+#define COMP_ACCTL1_ISEN_FALL   0x00000004  // Falling edge
+#define COMP_ACCTL1_ISEN_RISE   0x00000008  // Rising edge
+#define COMP_ACCTL1_ISEN_BOTH   0x0000000C  // Either edge
+#define COMP_ACCTL1_CINV        0x00000002  // Comparator Output Invert.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT2 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT2_OVAL       0x00000002  // Comparator Output Value.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL2 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL2_TOEN        0x00000800  // Trigger Output Enable.
+#define COMP_ACCTL2_ASRCP_M     0x00000600  // Analog Source Positive.
+#define COMP_ACCTL2_ASRCP_PIN   0x00000000  // Pin value
+#define COMP_ACCTL2_ASRCP_PIN0  0x00000200  // Pin value of C0+
+#define COMP_ACCTL2_ASRCP_REF   0x00000400  // Internal voltage reference
+#define COMP_ACCTL2_TSLVAL      0x00000080  // Trigger Sense Level Value.
+#define COMP_ACCTL2_TSEN_M      0x00000060  // Trigger Sense.
+#define COMP_ACCTL2_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
+#define COMP_ACCTL2_TSEN_FALL   0x00000020  // Falling edge
+#define COMP_ACCTL2_TSEN_RISE   0x00000040  // Rising edge
+#define COMP_ACCTL2_TSEN_BOTH   0x00000060  // Either edge
+#define COMP_ACCTL2_ISLVAL      0x00000010  // Interrupt Sense Level Value.
+#define COMP_ACCTL2_ISEN_M      0x0000000C  // Interrupt Sense.
+#define COMP_ACCTL2_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
+#define COMP_ACCTL2_ISEN_FALL   0x00000004  // Falling edge
+#define COMP_ACCTL2_ISEN_RISE   0x00000008  // Rising edge
+#define COMP_ACCTL2_ISEN_BOTH   0x0000000C  // Either edge
+#define COMP_ACCTL2_CINV        0x00000002  // Comparator Output Invert.
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the comparator register offsets.
+//
+//*****************************************************************************
+#define COMP_O_MIS              0x00000000  // Interrupt status register
+#define COMP_O_RIS              0x00000004  // Raw interrupt status register
+#define COMP_O_INTEN            0x00000008  // Interrupt enable register
+#define COMP_O_REFCTL           0x00000010  // Reference voltage control reg.
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the COMP_MIS,
+// COMP_RIS, and COMP_INTEN registers.
+//
+//*****************************************************************************
+#define COMP_INT_2              0x00000004  // Comp2 interrupt
+#define COMP_INT_1              0x00000002  // Comp1 interrupt
+#define COMP_INT_0              0x00000001  // Comp0 interrupt
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the COMP_REFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_REFCTL_EN          0x00000200  // Reference voltage enable
+#define COMP_REFCTL_RNG         0x00000100  // Reference voltage range
+#define COMP_REFCTL_VREF_MASK   0x0000000F  // Reference voltage select mask
+#define COMP_REFCTL_VREF_SHIFT  0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the COMP_ACSTAT0,
+// COMP_ACSTAT1, and COMP_ACSTAT2 registers.
+//
+//*****************************************************************************
+#define COMP_ACSTAT_OVAL        0x00000002  // Comparator output value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the COMP_ACCTL0,
+// COMP_ACCTL1, and COMP_ACCTL2 registers.
+//
+//*****************************************************************************
+#define COMP_ACCTL_TMASK        0x00000800  // Trigger enable
+#define COMP_ACCTL_ASRCP_MASK   0x00000600  // Vin+ source select mask
+#define COMP_ACCTL_ASRCP_PIN    0x00000000  // Dedicated Comp+ pin
+#define COMP_ACCTL_ASRCP_PIN0   0x00000200  // Comp0+ pin
+#define COMP_ACCTL_ASRCP_REF    0x00000400  // Internal voltage reference
+#define COMP_ACCTL_ASRCP_RES    0x00000600  // Reserved
+#define COMP_ACCTL_OEN          0x00000100  // Comparator output enable
+#define COMP_ACCTL_TSVAL        0x00000080  // Trigger polarity select
+#define COMP_ACCTL_TSEN_MASK    0x00000060  // Trigger sense mask
+#define COMP_ACCTL_TSEN_LEVEL   0x00000000  // Trigger is level sense
+#define COMP_ACCTL_TSEN_FALL    0x00000020  // Trigger is falling edge
+#define COMP_ACCTL_TSEN_RISE    0x00000040  // Trigger is rising edge
+#define COMP_ACCTL_TSEN_BOTH    0x00000060  // Trigger is both edges
+#define COMP_ACCTL_ISLVAL       0x00000010  // Interrupt polarity select
+#define COMP_ACCTL_ISEN_MASK    0x0000000C  // Interrupt sense mask
+#define COMP_ACCTL_ISEN_LEVEL   0x00000000  // Interrupt is level sense
+#define COMP_ACCTL_ISEN_FALL    0x00000004  // Interrupt is falling edge
+#define COMP_ACCTL_ISEN_RISE    0x00000008  // Interrupt is rising edge
+#define COMP_ACCTL_ISEN_BOTH    0x0000000C  // Interrupt is both edges
+#define COMP_ACCTL_CINV         0x00000002  // Comparator output invert
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values for the comparator
+// registers.
+//
+//*****************************************************************************
+#define COMP_RV_ACCTL1          0x00000000  // Comp1 control register
+#define COMP_RV_ACSTAT2         0x00000000  // Comp2 status register
+#define COMP_RV_ACSTAT0         0x00000000  // Comp0 status register
+#define COMP_RV_RIS             0x00000000  // Raw interrupt status register
+#define COMP_RV_INTEN           0x00000000  // Interrupt enable register
+#define COMP_RV_ACCTL2          0x00000000  // Comp2 control register
+#define COMP_RV_MIS             0x00000000  // Interrupt status register
+#define COMP_RV_ACCTL0          0x00000000  // Comp0 control register
+#define COMP_RV_ACSTAT1         0x00000000  // Comp1 status register
+#define COMP_RV_REFCTL          0x00000000  // Reference voltage control reg.
+
+#endif
+
+#endif // __HW_COMP_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_ethernet.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_ethernet.h
new file mode 100644
index 0000000..dac2706
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_ethernet.h
@@ -0,0 +1,576 @@
+//*****************************************************************************
+//
+// hw_ethernet.h - Macros used when accessing the Ethernet hardware.
+//
+// Copyright (c) 2006-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HW_ETHERNET_H__
+#define __HW_ETHERNET_H__
+
+//*****************************************************************************
+//
+// The following are defines for the MAC register offsets in the Ethernet
+// Controller.
+//
+//*****************************************************************************
+#define MAC_O_RIS               0x00000000  // Ethernet MAC Raw Interrupt
+                                            // Status
+#define MAC_O_IACK              0x00000000  // Interrupt Acknowledge Register
+#define MAC_O_IM                0x00000004  // Interrupt Mask Register
+#define MAC_O_RCTL              0x00000008  // Receive Control Register
+#define MAC_O_TCTL              0x0000000C  // Transmit Control Register
+#define MAC_O_DATA              0x00000010  // Data Register
+#define MAC_O_IA0               0x00000014  // Individual Address Register 0
+#define MAC_O_IA1               0x00000018  // Individual Address Register 1
+#define MAC_O_THR               0x0000001C  // Threshold Register
+#define MAC_O_MCTL              0x00000020  // Management Control Register
+#define MAC_O_MDV               0x00000024  // Management Divider Register
+#define MAC_O_MTXD              0x0000002C  // Management Transmit Data Reg
+#define MAC_O_MRXD              0x00000030  // Management Receive Data Reg
+#define MAC_O_NP                0x00000034  // Number of Packets Register
+#define MAC_O_TR                0x00000038  // Transmission Request Register
+#define MAC_O_TS                0x0000003C  // Timer Support Register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_IACK register.
+//
+//*****************************************************************************
+#define MAC_IACK_PHYINT         0x00000040  // Clear PHY Interrupt
+#define MAC_IACK_MDINT          0x00000020  // Clear MDI Transaction Complete
+#define MAC_IACK_RXER           0x00000010  // Clear RX Error
+#define MAC_IACK_FOV            0x00000008  // Clear RX FIFO Overrun
+#define MAC_IACK_TXEMP          0x00000004  // Clear TX FIFO Empy
+#define MAC_IACK_TXER           0x00000002  // Clear TX Error
+#define MAC_IACK_RXINT          0x00000001  // Clear RX Packet Available
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_IM register.
+//
+//*****************************************************************************
+#define MAC_IM_PHYINTM          0x00000040  // Mask PHY Interrupt
+#define MAC_IM_MDINTM           0x00000020  // Mask MDI Transaction Complete
+#define MAC_IM_RXERM            0x00000010  // Mask RX Error
+#define MAC_IM_FOVM             0x00000008  // Mask RX FIFO Overrun
+#define MAC_IM_TXEMPM           0x00000004  // Mask TX FIFO Empy
+#define MAC_IM_TXERM            0x00000002  // Mask TX Error
+#define MAC_IM_RXINTM           0x00000001  // Mask RX Packet Available
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_RCTL register.
+//
+//*****************************************************************************
+#define MAC_RCTL_RSTFIFO        0x00000010  // Clear the Receive FIFO
+#define MAC_RCTL_BADCRC         0x00000008  // Reject Packets With Bad CRC
+#define MAC_RCTL_PRMS           0x00000004  // Enable Promiscuous Mode
+#define MAC_RCTL_AMUL           0x00000002  // Enable Multicast Packets
+#define MAC_RCTL_RXEN           0x00000001  // Enable Ethernet Receiver
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_TCTL register.
+//
+//*****************************************************************************
+#define MAC_TCTL_DUPLEX         0x00000010  // Enable Duplex mode
+#define MAC_TCTL_CRC            0x00000004  // Enable CRC Generation
+#define MAC_TCTL_PADEN          0x00000002  // Enable Automatic Padding
+#define MAC_TCTL_TXEN           0x00000001  // Enable Ethernet Transmitter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_IA0 register.
+//
+//*****************************************************************************
+#define MAC_IA0_MACOCT4_M       0xFF000000  // MAC Address Octet 4.
+#define MAC_IA0_MACOCT3_M       0x00FF0000  // MAC Address Octet 3.
+#define MAC_IA0_MACOCT2_M       0x0000FF00  // MAC Address Octet 2.
+#define MAC_IA0_MACOCT1_M       0x000000FF  // MAC Address Octet 1.
+#define MAC_IA0_MACOCT4_S       24
+#define MAC_IA0_MACOCT3_S       16
+#define MAC_IA0_MACOCT2_S       8
+#define MAC_IA0_MACOCT1_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_IA1 register.
+//
+//*****************************************************************************
+#define MAC_IA1_MACOCT6_M       0x0000FF00  // MAC Address Octet 6.
+#define MAC_IA1_MACOCT5_M       0x000000FF  // MAC Address Octet 5.
+#define MAC_IA1_MACOCT6_S       8
+#define MAC_IA1_MACOCT5_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_TXTH register.
+//
+//*****************************************************************************
+#define MAC_THR_THRESH_M        0x0000003F  // Threshold Value.
+#define MAC_THR_THRESH_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_MCTL register.
+//
+//*****************************************************************************
+#define MAC_MCTL_REGADR_M       0x000000F8  // MII Register Address.
+#define MAC_MCTL_WRITE          0x00000002  // Next MII Transaction is Write
+#define MAC_MCTL_START          0x00000001  // Start MII Transaction
+#define MAC_MCTL_REGADR_S       3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_MDV register.
+//
+//*****************************************************************************
+#define MAC_MDV_DIV_M           0x000000FF  // Clock Divider.
+#define MAC_MDV_DIV_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_MTXD register.
+//
+//*****************************************************************************
+#define MAC_MTXD_MDTX_M         0x0000FFFF  // MII Register Transmit Data.
+#define MAC_MTXD_MDTX_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_MRXD register.
+//
+//*****************************************************************************
+#define MAC_MRXD_MDRX_M         0x0000FFFF  // MII Register Receive Data.
+#define MAC_MRXD_MDRX_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_NP register.
+//
+//*****************************************************************************
+#define MAC_NP_NPR_M            0x0000003F  // Number of Packets in Receive
+                                            // FIFO.
+#define MAC_NP_NPR_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_TXRQ register.
+//
+//*****************************************************************************
+#define MAC_TR_NEWTX            0x00000001  // Start an Ethernet Transmission
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_TS register.
+//
+//*****************************************************************************
+#define MAC_TS_TSEN             0x00000001  // Enable Timestamp Logic
+
+//*****************************************************************************
+//
+// The following are defines for the Ethernet Controller PHY registers.
+//
+//*****************************************************************************
+#define PHY_MR24                0x00000018  // Ethernet PHY Management Register
+                                            // 24 -MDI/MDIX Control
+#define PHY_MR23                0x00000017  // Ethernet PHY Management Register
+                                            // 23 - LED Configuration
+#define PHY_MR19                0x00000013  // Ethernet PHY Management Register
+                                            // 19 - Transceiver Control
+#define PHY_MR18                0x00000012  // Ethernet PHY Management Register
+                                            // 18 - Diagnostic
+#define PHY_MR17                0x00000011  // Ethernet PHY Management Register
+                                            // 17 - Interrupt Control/Status
+#define PHY_MR16                0x00000010  // Ethernet PHY Management Register
+                                            // 16 - Vendor-Specific
+#define PHY_MR6                 0x00000006  // Ethernet PHY Management Register
+                                            // 6 - Auto-Negotiation Expansion
+#define PHY_MR5                 0x00000005  // Ethernet PHY Management Register
+                                            // 5 - Auto-Negotiation Link
+                                            // Partner Base Page Ability
+#define PHY_MR4                 0x00000004  // Ethernet PHY Management Register
+                                            // 4 - Auto-Negotiation
+                                            // Advertisement
+#define PHY_MR3                 0x00000003  // Ethernet PHY Management Register
+                                            // 3 - PHY Identifier 2
+#define PHY_MR2                 0x00000002  // Ethernet PHY Management Register
+                                            // 2 - PHY Identifier 1
+#define PHY_MR1                 0x00000001  // Ethernet PHY Management Register
+                                            // 1 - Status
+#define PHY_MR0                 0x00000000  // Ethernet PHY Management Register
+                                            // 0 - Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR0 register.
+//
+//*****************************************************************************
+#define PHY_MR0_RESET           0x00008000  // Reset Registers.
+#define PHY_MR0_LOOPBK          0x00004000  // Loopback Mode.
+#define PHY_MR0_SPEEDSL         0x00002000  // Speed Select.
+#define PHY_MR0_ANEGEN          0x00001000  // Auto-Negotiation Enable.
+#define PHY_MR0_PWRDN           0x00000800  // Power Down.
+#define PHY_MR0_ISO             0x00000400  // Isolate.
+#define PHY_MR0_RANEG           0x00000200  // Restart Auto-Negotiation.
+#define PHY_MR0_DUPLEX          0x00000100  // Set Duplex Mode.
+#define PHY_MR0_COLT            0x00000080  // Collision Test.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_RIS register.
+//
+//*****************************************************************************
+#define MAC_RIS_PHYINT          0x00000040  // PHY Interrupt.
+#define MAC_RIS_MDINT           0x00000020  // MII Transaction Complete.
+#define MAC_RIS_RXER            0x00000010  // Receive Error.
+#define MAC_RIS_FOV             0x00000008  // FIFO Overrrun.
+#define MAC_RIS_TXEMP           0x00000004  // Transmit FIFO Empty.
+#define MAC_RIS_TXER            0x00000002  // Transmit Error.
+#define MAC_RIS_RXINT           0x00000001  // Packet Received.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR1 register.
+//
+//*****************************************************************************
+#define PHY_MR1_100X_F          0x00004000  // 100BASE-TX Full-Duplex Mode.
+#define PHY_MR1_100X_H          0x00002000  // 100BASE-TX Half-Duplex Mode.
+#define PHY_MR1_10T_F           0x00001000  // 10BASE-T Full-Duplex Mode.
+#define PHY_MR1_10T_H           0x00000800  // 10BASE-T Half-Duplex Mode.
+#define PHY_MR1_MFPS            0x00000040  // Management Frames with Preamble
+                                            // Suppressed.
+#define PHY_MR1_ANEGC           0x00000020  // Auto-Negotiation Complete.
+#define PHY_MR1_RFAULT          0x00000010  // Remote Fault.
+#define PHY_MR1_ANEGA           0x00000008  // Auto-Negotiation.
+#define PHY_MR1_LINK            0x00000004  // Link Made.
+#define PHY_MR1_JAB             0x00000002  // Jabber Condition.
+#define PHY_MR1_EXTD            0x00000001  // Extended Capabilities.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR2 register.
+//
+//*****************************************************************************
+#define PHY_MR2_OUI_M           0x0000FFFF  // Organizationally Unique
+                                            // Identifier[21:6].
+#define PHY_MR2_OUI_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR3 register.
+//
+//*****************************************************************************
+#define PHY_MR3_OUI_M           0x0000FC00  // Organizationally Unique
+                                            // Identifier[5:0].
+#define PHY_MR3_MN_M            0x000003F0  // Model Number.
+#define PHY_MR3_RN_M            0x0000000F  // Revision Number.
+#define PHY_MR3_OUI_S           10
+#define PHY_MR3_MN_S            4
+#define PHY_MR3_RN_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR4 register.
+//
+//*****************************************************************************
+#define PHY_MR4_NP              0x00008000  // Next Page.
+#define PHY_MR4_RF              0x00002000  // Remote Fault.
+#define PHY_MR4_A3              0x00000100  // Technology Ability Field[3].
+#define PHY_MR4_A2              0x00000080  // Technology Ability Field[2].
+#define PHY_MR4_A1              0x00000040  // Technology Ability Field[1].
+#define PHY_MR4_A0              0x00000020  // Technology Ability Field[0].
+#define PHY_MR4_S_M             0x0000001F  // Selector Field.
+#define PHY_MR4_S_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR5 register.
+//
+//*****************************************************************************
+#define PHY_MR5_NP              0x00008000  // Next Page.
+#define PHY_MR5_ACK             0x00004000  // Acknowledge.
+#define PHY_MR5_RF              0x00002000  // Remote Fault.
+#define PHY_MR5_A_M             0x00001FE0  // Technology Ability Field.
+#define PHY_MR5_S_M             0x0000001F  // Selector Field.
+#define PHY_MR5_S_8023          0x00000001  // IEEE Std 802.3
+#define PHY_MR5_S_8029          0x00000002  // IEEE Std 802.9 ISLAN-16T
+#define PHY_MR5_S_8025          0x00000003  // IEEE Std 802.5
+#define PHY_MR5_S_1394          0x00000004  // IEEE Std 1394
+#define PHY_MR5_A_S             5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR6 register.
+//
+//*****************************************************************************
+#define PHY_MR6_PDF             0x00000010  // Parallel Detection Fault.
+#define PHY_MR6_LPNPA           0x00000008  // Link Partner is Next Page Able.
+#define PHY_MR6_PRX             0x00000002  // New Page Received.
+#define PHY_MR6_LPANEGA         0x00000001  // Link Partner is Auto-Negotiation
+                                            // Able.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_DATA register.
+//
+//*****************************************************************************
+#define MAC_DATA_TXDATA_M       0xFFFFFFFF  // Transmit FIFO Data.
+#define MAC_DATA_RXDATA_M       0xFFFFFFFF  // Receive FIFO Data.
+#define MAC_DATA_RXDATA_S       0
+#define MAC_DATA_TXDATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR16 register.
+//
+//*****************************************************************************
+#define PHY_MR16_RPTR           0x00008000  // Repeater Mode.
+#define PHY_MR16_INPOL          0x00004000  // Interrupt Polarity.
+#define PHY_MR16_TXHIM          0x00001000  // Transmit High Impedance Mode.
+#define PHY_MR16_SQEI           0x00000800  // SQE Inhibit Testing.
+#define PHY_MR16_NL10           0x00000400  // Natural Loopback Mode.
+#define PHY_MR16_APOL           0x00000020  // Auto-Polarity Disable.
+#define PHY_MR16_RVSPOL         0x00000010  // Receive Data Polarity.
+#define PHY_MR16_PCSBP          0x00000002  // PCS Bypass.
+#define PHY_MR16_RXCC           0x00000001  // Receive Clock Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR17 register.
+//
+//*****************************************************************************
+#define PHY_MR17_JABBER_IE      0x00008000  // Jabber Interrupt Enable.
+#define PHY_MR17_RXER_IE        0x00004000  // Receive Error Interrupt Enable.
+#define PHY_MR17_PRX_IE         0x00002000  // Page Received Interrupt Enable.
+#define PHY_MR17_PDF_IE         0x00001000  // Parallel Detection Fault
+                                            // Interrupt Enable.
+#define PHY_MR17_LPACK_IE       0x00000800  // LP Acknowledge Interrupt Enable.
+#define PHY_MR17_LSCHG_IE       0x00000400  // Link Status Change Interrupt
+                                            // Enable.
+#define PHY_MR17_RFAULT_IE      0x00000200  // Remote Fault Interrupt Enable.
+#define PHY_MR17_ANEGCOMP_IE    0x00000100  // Auto-Negotiation Complete
+                                            // Interrupt Enable.
+#define PHY_MR17_JABBER_INT     0x00000080  // Jabber Event Interrupt.
+#define PHY_MR17_RXER_INT       0x00000040  // Receive Error Interrupt.
+#define PHY_MR17_PRX_INT        0x00000020  // Page Receive Interrupt.
+#define PHY_MR17_PDF_INT        0x00000010  // Parallel Detection Fault
+                                            // Interrupt.
+#define PHY_MR17_LPACK_INT      0x00000008  // LP Acknowledge Interrupt.
+#define PHY_MR17_LSCHG_INT      0x00000004  // Link Status Change Interrupt.
+#define PHY_MR17_RFAULT_INT     0x00000002  // Remote Fault Interrupt.
+#define PHY_MR17_ANEGCOMP_INT   0x00000001  // Auto-Negotiation Complete
+                                            // Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR18 register.
+//
+//*****************************************************************************
+#define PHY_MR18_ANEGF          0x00001000  // Auto-Negotiation Failure.
+#define PHY_MR18_DPLX           0x00000800  // Duplex Mode.
+#define PHY_MR18_RATE           0x00000400  // Rate.
+#define PHY_MR18_RXSD           0x00000200  // Receive Detection.
+#define PHY_MR18_RX_LOCK        0x00000100  // Receive PLL Lock.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR19 register.
+//
+//*****************************************************************************
+#define PHY_MR19_TXO_M          0x0000C000  // Transmit Amplitude Selection.
+#define PHY_MR19_TXO_00DB       0x00000000  // Gain set for 0.0dB of insertion
+                                            // loss
+#define PHY_MR19_TXO_04DB       0x00004000  // Gain set for 0.4dB of insertion
+                                            // loss
+#define PHY_MR19_TXO_08DB       0x00008000  // Gain set for 0.8dB of insertion
+                                            // loss
+#define PHY_MR19_TXO_12DB       0x0000C000  // Gain set for 1.2dB of insertion
+                                            // loss
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR23 register.
+//
+//*****************************************************************************
+#define PHY_MR23_LED1_M         0x000000F0  // LED1 Source.
+#define PHY_MR23_LED1_LINK      0x00000000  // Link OK
+#define PHY_MR23_LED1_RXTX      0x00000010  // RX or TX Activity (Default LED1)
+#define PHY_MR23_LED1_TX        0x00000020  // TX Activity
+#define PHY_MR23_LED1_RX        0x00000030  // RX Activity
+#define PHY_MR23_LED1_COL       0x00000040  // Collision
+#define PHY_MR23_LED1_100       0x00000050  // 100BASE-TX mode
+#define PHY_MR23_LED1_10        0x00000060  // 10BASE-T mode
+#define PHY_MR23_LED1_DUPLEX    0x00000070  // Full-Duplex
+#define PHY_MR23_LED1_LINKACT   0x00000080  // Link OK & Blink=RX or TX
+                                            // Activity
+#define PHY_MR23_LED0_M         0x0000000F  // LED0 Source.
+#define PHY_MR23_LED0_LINK      0x00000000  // Link OK (Default LED0)
+#define PHY_MR23_LED0_RXTX      0x00000001  // RX or TX Activity
+#define PHY_MR23_LED0_TX        0x00000002  // TX Activity
+#define PHY_MR23_LED0_RX        0x00000003  // RX Activity
+#define PHY_MR23_LED0_COL       0x00000004  // Collision
+#define PHY_MR23_LED0_100       0x00000005  // 100BASE-TX mode
+#define PHY_MR23_LED0_10        0x00000006  // 10BASE-T mode
+#define PHY_MR23_LED0_DUPLEX    0x00000007  // Full-Duplex
+#define PHY_MR23_LED0_LINKACT   0x00000008  // Link OK & Blink=RX or TX
+                                            // Activity
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR24 register.
+//
+//*****************************************************************************
+#define PHY_MR24_PD_MODE        0x00000080  // Parallel Detection Mode.
+#define PHY_MR24_AUTO_SW        0x00000040  // Auto-Switching Enable.
+#define PHY_MR24_MDIX           0x00000020  // Auto-Switching Configuration.
+#define PHY_MR24_MDIX_CM        0x00000010  // Auto-Switching Complete.
+#define PHY_MR24_MDIX_SD_M      0x0000000F  // Auto-Switching Seed.
+#define PHY_MR24_MDIX_SD_S      0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the MAC register offsets in the
+// Ethernet Controller.
+//
+//*****************************************************************************
+#define MAC_O_IS                0x00000000  // Interrupt Status Register
+#define MAC_O_MADD              0x00000028  // Management Address Register
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values of the MAC
+// registers.
+//
+//*****************************************************************************
+#define MAC_RV_MDV              0x00000080
+#define MAC_RV_IM               0x0000007F
+#define MAC_RV_THR              0x0000003F
+#define MAC_RV_RCTL             0x00000008
+#define MAC_RV_IA0              0x00000000
+#define MAC_RV_TCTL             0x00000000
+#define MAC_RV_DATA             0x00000000
+#define MAC_RV_MRXD             0x00000000
+#define MAC_RV_TR               0x00000000
+#define MAC_RV_IS               0x00000000
+#define MAC_RV_NP               0x00000000
+#define MAC_RV_MCTL             0x00000000
+#define MAC_RV_MTXD             0x00000000
+#define MAC_RV_IA1              0x00000000
+#define MAC_RV_IACK             0x00000000
+#define MAC_RV_MADD             0x00000000
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_IS
+// register.
+//
+//*****************************************************************************
+#define MAC_IS_PHYINT           0x00000040  // PHY Interrupt
+#define MAC_IS_MDINT            0x00000020  // MDI Transaction Complete
+#define MAC_IS_RXER             0x00000010  // RX Error
+#define MAC_IS_FOV              0x00000008  // RX FIFO Overrun
+#define MAC_IS_TXEMP            0x00000004  // TX FIFO Empy
+#define MAC_IS_TXER             0x00000002  // TX Error
+#define MAC_IS_RXINT            0x00000001  // RX Packet Available
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_IA0
+// register.
+//
+//*****************************************************************************
+#define MAC_IA0_MACOCT4         0xFF000000  // 4th Octet of MAC address
+#define MAC_IA0_MACOCT3         0x00FF0000  // 3rd Octet of MAC address
+#define MAC_IA0_MACOCT2         0x0000FF00  // 2nd Octet of MAC address
+#define MAC_IA0_MACOCT1         0x000000FF  // 1st Octet of MAC address
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_IA1
+// register.
+//
+//*****************************************************************************
+#define MAC_IA1_MACOCT6         0x0000FF00  // 6th Octet of MAC address
+#define MAC_IA1_MACOCT5         0x000000FF  // 5th Octet of MAC address
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_TXTH
+// register.
+//
+//*****************************************************************************
+#define MAC_THR_THRESH          0x0000003F  // Transmit Threshold Value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_MCTL
+// register.
+//
+//*****************************************************************************
+#define MAC_MCTL_REGADR         0x000000F8  // Address for Next MII Transaction
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_MDV
+// register.
+//
+//*****************************************************************************
+#define MAC_MDV_DIV             0x000000FF  // Clock Divider for MDC for TX
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_MTXD
+// register.
+//
+//*****************************************************************************
+#define MAC_MTXD_MDTX           0x0000FFFF  // Data for Next MII Transaction
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_MRXD
+// register.
+//
+//*****************************************************************************
+#define MAC_MRXD_MDRX           0x0000FFFF  // Data Read from Last MII Trans.
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_NP
+// register.
+//
+//*****************************************************************************
+#define MAC_NP_NPR              0x0000003F  // Number of RX Frames in FIFO
+
+#endif
+
+#endif // __HW_ETHERNET_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_flash.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_flash.h
new file mode 100644
index 0000000..cbb7237
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_flash.h
@@ -0,0 +1,296 @@
+//*****************************************************************************
+//
+// hw_flash.h - Macros used when accessing the flash controller.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HW_FLASH_H__
+#define __HW_FLASH_H__
+
+//*****************************************************************************
+//
+// The following are defines for the FLASH register offsets.
+//
+//*****************************************************************************
+#define FLASH_FMA               0x400FD000  // Memory address register
+#define FLASH_FMD               0x400FD004  // Memory data register
+#define FLASH_FMC               0x400FD008  // Memory control register
+#define FLASH_FCRIS             0x400FD00C  // Raw interrupt status register
+#define FLASH_FCIM              0x400FD010  // Interrupt mask register
+#define FLASH_FCMISC            0x400FD014  // Interrupt status register
+#define FLASH_RMCTL             0x400FE0F0  // ROM Control
+#define FLASH_RMVER             0x400FE0F4  // ROM Version Register
+#define FLASH_FMPRE             0x400FE130  // FLASH read protect register
+#define FLASH_FMPPE             0x400FE134  // FLASH program protect register
+#define FLASH_USECRL            0x400FE140  // uSec reload register
+#define FLASH_USERDBG           0x400FE1D0  // User Debug
+#define FLASH_USERREG0          0x400FE1E0  // User Register 0
+#define FLASH_USERREG1          0x400FE1E4  // User Register 1
+#define FLASH_USERREG2          0x400FE1E8  // User Register 2
+#define FLASH_USERREG3          0x400FE1EC  // User Register 3
+#define FLASH_FMPRE0            0x400FE200  // FLASH read protect register 0
+#define FLASH_FMPRE1            0x400FE204  // FLASH read protect register 1
+#define FLASH_FMPRE2            0x400FE208  // FLASH read protect register 2
+#define FLASH_FMPRE3            0x400FE20C  // FLASH read protect register 3
+#define FLASH_FMPPE0            0x400FE400  // FLASH program protect register 0
+#define FLASH_FMPPE1            0x400FE404  // FLASH program protect register 1
+#define FLASH_FMPPE2            0x400FE408  // FLASH program protect register 2
+#define FLASH_FMPPE3            0x400FE40C  // FLASH program protect register 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY_M       0xFFFF0000  // FLASH write key mask
+#define FLASH_FMC_WRKEY         0xA4420000  // FLASH write key
+#define FLASH_FMC_COMT          0x00000008  // Commit user register
+#define FLASH_FMC_MERASE        0x00000004  // Mass erase FLASH
+#define FLASH_FMC_ERASE         0x00000002  // Erase FLASH page
+#define FLASH_FMC_WRITE         0x00000001  // Write FLASH word
+#define FLASH_FMC_WRKEY_S       16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCRIS register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PRIS        0x00000002  // Programming Raw Interrupt
+                                            // Status.
+#define FLASH_FCRIS_ARIS        0x00000001  // Access Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCIM register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PMASK        0x00000002  // Programming Interrupt Mask.
+#define FLASH_FCIM_AMASK        0x00000001  // Access Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMIS register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PMISC      0x00000002  // Programming Masked Interrupt
+                                            // Status and Clear.
+#define FLASH_FCMISC_AMISC      0x00000001  // Access Masked Interrupt Status
+                                            // and Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE and
+// FLASH_FMPPE registers.
+//
+//*****************************************************************************
+#define FLASH_FMP_BLOCK_31      0x80000000  // Enable for block 31
+#define FLASH_FMP_BLOCK_30      0x40000000  // Enable for block 30
+#define FLASH_FMP_BLOCK_29      0x20000000  // Enable for block 29
+#define FLASH_FMP_BLOCK_28      0x10000000  // Enable for block 28
+#define FLASH_FMP_BLOCK_27      0x08000000  // Enable for block 27
+#define FLASH_FMP_BLOCK_26      0x04000000  // Enable for block 26
+#define FLASH_FMP_BLOCK_25      0x02000000  // Enable for block 25
+#define FLASH_FMP_BLOCK_24      0x01000000  // Enable for block 24
+#define FLASH_FMP_BLOCK_23      0x00800000  // Enable for block 23
+#define FLASH_FMP_BLOCK_22      0x00400000  // Enable for block 22
+#define FLASH_FMP_BLOCK_21      0x00200000  // Enable for block 21
+#define FLASH_FMP_BLOCK_20      0x00100000  // Enable for block 20
+#define FLASH_FMP_BLOCK_19      0x00080000  // Enable for block 19
+#define FLASH_FMP_BLOCK_18      0x00040000  // Enable for block 18
+#define FLASH_FMP_BLOCK_17      0x00020000  // Enable for block 17
+#define FLASH_FMP_BLOCK_16      0x00010000  // Enable for block 16
+#define FLASH_FMP_BLOCK_15      0x00008000  // Enable for block 15
+#define FLASH_FMP_BLOCK_14      0x00004000  // Enable for block 14
+#define FLASH_FMP_BLOCK_13      0x00002000  // Enable for block 13
+#define FLASH_FMP_BLOCK_12      0x00001000  // Enable for block 12
+#define FLASH_FMP_BLOCK_11      0x00000800  // Enable for block 11
+#define FLASH_FMP_BLOCK_10      0x00000400  // Enable for block 10
+#define FLASH_FMP_BLOCK_9       0x00000200  // Enable for block 9
+#define FLASH_FMP_BLOCK_8       0x00000100  // Enable for block 8
+#define FLASH_FMP_BLOCK_7       0x00000080  // Enable for block 7
+#define FLASH_FMP_BLOCK_6       0x00000040  // Enable for block 6
+#define FLASH_FMP_BLOCK_5       0x00000020  // Enable for block 5
+#define FLASH_FMP_BLOCK_4       0x00000010  // Enable for block 4
+#define FLASH_FMP_BLOCK_3       0x00000008  // Enable for block 3
+#define FLASH_FMP_BLOCK_2       0x00000004  // Enable for block 2
+#define FLASH_FMP_BLOCK_1       0x00000002  // Enable for block 1
+#define FLASH_FMP_BLOCK_0       0x00000001  // Enable for block 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USECRL register.
+//
+//*****************************************************************************
+#define FLASH_USECRL_M          0x000000FF  // Microsecond Reload Value.
+#define FLASH_USECRL_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the erase size of the FLASH block that is
+// erased by an erase operation, and the protect size is the size of the FLASH
+// block that is protected by each protection register.
+//
+//*****************************************************************************
+#define FLASH_PROTECT_SIZE      0x00000800
+#define FLASH_ERASE_SIZE        0x00000400
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMA register.
+//
+//*****************************************************************************
+#define FLASH_FMA_OFFSET_M      0x0003FFFF  // Address Offset.
+#define FLASH_FMA_OFFSET_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMD register.
+//
+//*****************************************************************************
+#define FLASH_FMD_DATA_M        0xFFFFFFFF  // Data Value.
+#define FLASH_FMD_DATA_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERDBG register.
+//
+//*****************************************************************************
+#define FLASH_USERDBG_NW        0x80000000  // User Debug Not Written.
+#define FLASH_USERDBG_DATA_M    0x7FFFFFFC  // User Data.
+#define FLASH_USERDBG_DBG1      0x00000002  // Debug Control 1.
+#define FLASH_USERDBG_DBG0      0x00000001  // Debug Control 0.
+#define FLASH_USERDBG_DATA_S    2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG0 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG0_NW       0x80000000  // Not Written.
+#define FLASH_USERREG0_DATA_M   0x7FFFFFFF  // User Data.
+#define FLASH_USERREG0_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG1 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG1_NW       0x80000000  // Not Written.
+#define FLASH_USERREG1_DATA_M   0x7FFFFFFF  // User Data.
+#define FLASH_USERREG1_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_RMCTL register.
+//
+//*****************************************************************************
+#define FLASH_RMCTL_BA          0x00000001  // Boot Alias.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_RMVER register.
+//
+//*****************************************************************************
+#define FLASH_RMVER_CONT_M      0xFF000000  // ROM Contents.
+#define FLASH_RMVER_CONT_LM     0x00000000  // Boot Loader & DriverLib
+#define FLASH_RMVER_SIZE_M      0x00FF0000  // ROM Size.
+#define FLASH_RMVER_SIZE_11K    0x00000000  // 11KB Size
+#define FLASH_RMVER_VER_M       0x0000FF00  // ROM Version.
+#define FLASH_RMVER_REV_M       0x000000FF  // ROM Revision.
+#define FLASH_RMVER_VER_S       8
+#define FLASH_RMVER_REV_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG2 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG2_NW       0x80000000  // Not Written.
+#define FLASH_USERREG2_DATA_M   0x7FFFFFFF  // User Data.
+#define FLASH_USERREG2_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG3 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG3_NW       0x80000000  // Not Written.
+#define FLASH_USERREG3_DATA_M   0x7FFFFFFF  // User Data.
+#define FLASH_USERREG3_DATA_S   0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FLASH_FMC
+// register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY_MASK    0xFFFF0000  // FLASH write key mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FLASH_FCRIS
+// register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PROGRAM     0x00000002  // Programming status
+#define FLASH_FCRIS_ACCESS      0x00000001  // Invalid access status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FLASH_FCIM
+// register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PROGRAM      0x00000002  // Programming mask
+#define FLASH_FCIM_ACCESS       0x00000001  // Invalid access mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FLASH_FMIS
+// register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PROGRAM    0x00000002  // Programming status
+#define FLASH_FCMISC_ACCESS     0x00000001  // Invalid access status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FLASH_USECRL
+// register.
+//
+//*****************************************************************************
+#define FLASH_USECRL_MASK       0x000000FF  // Clock per uSec
+#define FLASH_USECRL_SHIFT      0
+
+#endif
+
+#endif // __HW_FLASH_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_gpio.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_gpio.h
new file mode 100644
index 0000000..3b4d598
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_gpio.h
@@ -0,0 +1,136 @@
+//*****************************************************************************
+//
+// hw_gpio.h - Defines and Macros for GPIO hardware.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HW_GPIO_H__
+#define __HW_GPIO_H__
+
+//*****************************************************************************
+//
+// The following are defines for the GPIO Register offsets.
+//
+//*****************************************************************************
+#define GPIO_O_DATA             0x00000000  // Data register.
+#define GPIO_O_DIR              0x00000400  // Data direction register.
+#define GPIO_O_IS               0x00000404  // Interrupt sense register.
+#define GPIO_O_IBE              0x00000408  // Interrupt both edges register.
+#define GPIO_O_IEV              0x0000040C  // Interrupt event register.
+#define GPIO_O_IM               0x00000410  // Interrupt mask register.
+#define GPIO_O_RIS              0x00000414  // Raw interrupt status register.
+#define GPIO_O_MIS              0x00000418  // Masked interrupt status reg.
+#define GPIO_O_ICR              0x0000041C  // Interrupt clear register.
+#define GPIO_O_AFSEL            0x00000420  // Mode control select register.
+#define GPIO_O_DR2R             0x00000500  // 2ma drive select register.
+#define GPIO_O_DR4R             0x00000504  // 4ma drive select register.
+#define GPIO_O_DR8R             0x00000508  // 8ma drive select register.
+#define GPIO_O_ODR              0x0000050C  // Open drain select register.
+#define GPIO_O_PUR              0x00000510  // Pull up select register.
+#define GPIO_O_PDR              0x00000514  // Pull down select register.
+#define GPIO_O_SLR              0x00000518  // Slew rate control enable reg.
+#define GPIO_O_DEN              0x0000051C  // Digital input enable register.
+#define GPIO_O_LOCK             0x00000520  // Lock register.
+#define GPIO_O_CR               0x00000524  // Commit register.
+#define GPIO_O_AMSEL            0x00000528  // GPIO Analog Mode Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_LOCK register.
+//
+//*****************************************************************************
+#define GPIO_LOCK_M             0xFFFFFFFF  // GPIO Lock.
+#define GPIO_LOCK_UNLOCKED      0x00000000  // GPIO_CR register is unlocked
+#define GPIO_LOCK_LOCKED        0x00000001  // GPIO_CR register is locked
+#define GPIO_LOCK_KEY           0x1ACCE551  // Unlocks the GPIO_CR register
+#define GPIO_LOCK_KEY_DD        0x4C4F434B  // Unlocks the GPIO_CR register on
+                                            // DustDevil-class devices and
+                                            // later.
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the GPIO Register offsets.
+//
+//*****************************************************************************
+#define GPIO_O_PeriphID4        0x00000FD0
+#define GPIO_O_PeriphID5        0x00000FD4
+#define GPIO_O_PeriphID6        0x00000FD8
+#define GPIO_O_PeriphID7        0x00000FDC
+#define GPIO_O_PeriphID0        0x00000FE0
+#define GPIO_O_PeriphID1        0x00000FE4
+#define GPIO_O_PeriphID2        0x00000FE8
+#define GPIO_O_PeriphID3        0x00000FEC
+#define GPIO_O_PCellID0         0x00000FF0
+#define GPIO_O_PCellID1         0x00000FF4
+#define GPIO_O_PCellID2         0x00000FF8
+#define GPIO_O_PCellID3         0x00000FFC
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the GPIO Register reset values.
+//
+//*****************************************************************************
+#define GPIO_RV_DEN             0x000000FF  // Digital input enable reg RV.
+#define GPIO_RV_PUR             0x000000FF  // Pull up select reg RV.
+#define GPIO_RV_DR2R            0x000000FF  // 2ma drive select reg RV.
+#define GPIO_RV_PCellID1        0x000000F0
+#define GPIO_RV_PCellID3        0x000000B1
+#define GPIO_RV_PeriphID0       0x00000061
+#define GPIO_RV_PeriphID1       0x00000010
+#define GPIO_RV_PCellID0        0x0000000D
+#define GPIO_RV_PCellID2        0x00000005
+#define GPIO_RV_PeriphID2       0x00000004
+#define GPIO_RV_LOCK            0x00000001  // Lock register RV.
+#define GPIO_RV_PeriphID7       0x00000000
+#define GPIO_RV_PDR             0x00000000  // Pull down select reg RV.
+#define GPIO_RV_IC              0x00000000  // Interrupt clear reg RV.
+#define GPIO_RV_SLR             0x00000000  // Slew rate control enable reg RV.
+#define GPIO_RV_ODR             0x00000000  // Open drain select reg RV.
+#define GPIO_RV_IBE             0x00000000  // Interrupt both edges reg RV.
+#define GPIO_RV_AFSEL           0x00000000  // Mode control select reg RV.
+#define GPIO_RV_IS              0x00000000  // Interrupt sense reg RV.
+#define GPIO_RV_IM              0x00000000  // Interrupt mask reg RV.
+#define GPIO_RV_PeriphID4       0x00000000
+#define GPIO_RV_PeriphID5       0x00000000
+#define GPIO_RV_DR8R            0x00000000  // 8ma drive select reg RV.
+#define GPIO_RV_RIS             0x00000000  // Raw interrupt status reg RV.
+#define GPIO_RV_DR4R            0x00000000  // 4ma drive select reg RV.
+#define GPIO_RV_IEV             0x00000000  // Intterupt event reg RV.
+#define GPIO_RV_DIR             0x00000000  // Data direction reg RV.
+#define GPIO_RV_PeriphID6       0x00000000
+#define GPIO_RV_PeriphID3       0x00000000
+#define GPIO_RV_DATA            0x00000000  // Data register reset value.
+#define GPIO_RV_MIS             0x00000000  // Masked interrupt status reg RV.
+
+#endif
+
+#endif // __HW_GPIO_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_hibernate.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_hibernate.h
new file mode 100644
index 0000000..4d2c6d1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_hibernate.h
@@ -0,0 +1,245 @@
+//*****************************************************************************
+//
+// hw_hibernate.h - Defines and Macros for the Hibernation module.
+//
+// Copyright (c) 2007-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HW_HIBERNATE_H__
+#define __HW_HIBERNATE_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Hibernation module register addresses.
+//
+//*****************************************************************************
+#define HIB_RTCC                0x400FC000  // Hibernate RTC counter
+#define HIB_RTCM0               0x400FC004  // Hibernate RTC match 0
+#define HIB_RTCM1               0x400FC008  // Hibernate RTC match 1
+#define HIB_RTCLD               0x400FC00C  // Hibernate RTC load
+#define HIB_CTL                 0x400FC010  // Hibernate RTC control
+#define HIB_IM                  0x400FC014  // Hibernate interrupt mask
+#define HIB_RIS                 0x400FC018  // Hibernate raw interrupt status
+#define HIB_MIS                 0x400FC01C  // Hibernate masked interrupt stat
+#define HIB_IC                  0x400FC020  // Hibernate interrupt clear
+#define HIB_RTCT                0x400FC024  // Hibernate RTC trim
+#define HIB_DATA                0x400FC030  // Hibernate data area
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the Hibernate RTC counter
+// register.
+//
+//*****************************************************************************
+#define HIB_RTCC_M              0xFFFFFFFF  // RTC Counter.
+#define HIB_RTCC_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the Hibernate RTC match 0
+// register.
+//
+//*****************************************************************************
+#define HIB_RTCM0_M             0xFFFFFFFF  // RTC Match 0.
+#define HIB_RTCM0_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the Hibernate RTC match 1
+// register.
+//
+//*****************************************************************************
+#define HIB_RTCM1_M             0xFFFFFFFF  // RTC Match 1.
+#define HIB_RTCM1_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the Hibernate RTC load
+// register.
+//
+//*****************************************************************************
+#define HIB_RTCLD_M             0xFFFFFFFF  // RTC Load.
+#define HIB_RTCLD_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the Hibernate control
+// register
+//
+//*****************************************************************************
+#define HIB_CTL_WRC             0x80000000  // Write Complete/Capable.
+#define HIB_CTL_VABORT          0x00000080  // low bat abort
+#define HIB_CTL_CLK32EN         0x00000040  // enable clock/oscillator
+#define HIB_CTL_LOWBATEN        0x00000020  // enable low battery detect
+#define HIB_CTL_PINWEN          0x00000010  // enable wake on WAKE pin
+#define HIB_CTL_RTCWEN          0x00000008  // enable wake on RTC match
+#define HIB_CTL_CLKSEL          0x00000004  // clock input selection
+#define HIB_CTL_HIBREQ          0x00000002  // request hibernation
+#define HIB_CTL_RTCEN           0x00000001  // RTC enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the Hibernate interrupt mask
+// reg.
+//
+//*****************************************************************************
+#define HIB_IM_EXTW             0x00000008  // wake from external pin interrupt
+#define HIB_IM_LOWBAT           0x00000004  // low battery interrupt
+#define HIB_IM_RTCALT1          0x00000002  // RTC match 1 interrupt
+#define HIB_IM_RTCALT0          0x00000001  // RTC match 0 interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the Hibernate raw interrupt
+// status.
+//
+//*****************************************************************************
+#define HIB_RIS_EXTW            0x00000008  // wake from external pin interrupt
+#define HIB_RIS_LOWBAT          0x00000004  // low battery interrupt
+#define HIB_RIS_RTCALT1         0x00000002  // RTC match 1 interrupt
+#define HIB_RIS_RTCALT0         0x00000001  // RTC Alert0 Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the Hibernate masked int
+// status.
+//
+//*****************************************************************************
+#define HIB_MIS_EXTW            0x00000008  // wake from external pin interrupt
+#define HIB_MIS_LOWBAT          0x00000004  // low battery interrupt
+#define HIB_MIS_RTCALT1         0x00000002  // RTC match 1 interrupt
+#define HIB_MIS_RTCALT0         0x00000001  // RTC Alert0 Masked Interrupt
+                                            // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the Hibernate interrupt
+// clear reg.
+//
+//*****************************************************************************
+#define HIB_IC_EXTW             0x00000008  // wake from external pin interrupt
+#define HIB_IC_LOWBAT           0x00000004  // low battery interrupt
+#define HIB_IC_RTCALT1          0x00000002  // RTC match 1 interrupt
+#define HIB_IC_RTCALT0          0x00000001  // RTC match 0 interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the Hibernate RTC trim
+// register.
+//
+//*****************************************************************************
+#define HIB_RTCT_TRIM_M         0x0000FFFF  // RTC Trim Value.
+#define HIB_RTCT_TRIM_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the Hibernate data register.
+//
+//*****************************************************************************
+#define HIB_DATA_RTD_M          0xFFFFFFFF  // Hibernation Module NV
+                                            // Registers[63:0].
+#define HIB_DATA_RTD_S          0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Hibernation module register
+// addresses.
+//
+//*****************************************************************************
+#define HIB_DATA_END            0x400FC130  // end of data area, exclusive
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the Hibernate RTC
+// counter register.
+//
+//*****************************************************************************
+#define HIB_RTCC_MASK           0xFFFFFFFF  // RTC counter mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the Hibernate RTC
+// match 0 register.
+//
+//*****************************************************************************
+#define HIB_RTCM0_MASK          0xFFFFFFFF  // RTC match 0 mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the Hibernate RTC
+// match 1 register.
+//
+//*****************************************************************************
+#define HIB_RTCM1_MASK          0xFFFFFFFF  // RTC match 1 mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the Hibernate RTC
+// load register.
+//
+//*****************************************************************************
+#define HIB_RTCLD_MASK          0xFFFFFFFF  // RTC load mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the Hibernate raw
+// interrupt status.
+//
+//*****************************************************************************
+#define HIB_RID_RTCALT0         0x00000001  // RTC match 0 interrupt
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the Hibernate
+// masked int status.
+//
+//*****************************************************************************
+#define HIB_MID_RTCALT0         0x00000001  // RTC match 0 interrupt
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the Hibernate RTC
+// trim register.
+//
+//*****************************************************************************
+#define HIB_RTCT_MASK           0x0000FFFF  // RTC trim mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the Hibernate
+// data register.
+//
+//*****************************************************************************
+#define HIB_DATA_MASK           0xFFFFFFFF  // NV memory data mask
+
+#endif
+
+#endif // __HW_HIBERNATE_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_i2c.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_i2c.h
new file mode 100644
index 0000000..2fa3623
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_i2c.h
@@ -0,0 +1,413 @@
+//*****************************************************************************
+//
+// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HW_I2C_H__
+#define __HW_I2C_H__
+
+//*****************************************************************************
+//
+// The following are defines for the offsets between the I2C master and slave
+// registers.
+//
+//*****************************************************************************
+#define I2C_O_MSA               0x00000000  // I2C Master Slave Address
+#define I2C_O_SOAR              0x00000000  // I2C Slave Own Address
+#define I2C_O_SCSR              0x00000004  // I2C Slave Control/Status
+#define I2C_O_MCS               0x00000004  // I2C Master Control/Status
+#define I2C_O_SDR               0x00000008  // I2C Slave Data
+#define I2C_O_MDR               0x00000008  // I2C Master Data
+#define I2C_O_MTPR              0x0000000C  // I2C Master Timer Period
+#define I2C_O_SIMR              0x0000000C  // I2C Slave Interrupt Mask
+#define I2C_O_SRIS              0x00000010  // I2C Slave Raw Interrupt Status
+#define I2C_O_MIMR              0x00000010  // I2C Master Interrupt Mask
+#define I2C_O_MRIS              0x00000014  // I2C Master Raw Interrupt Status
+#define I2C_O_SMIS              0x00000014  // I2C Slave Masked Interrupt
+                                            // Status
+#define I2C_O_SICR              0x00000018  // I2C Slave Interrupt Clear
+#define I2C_O_MMIS              0x00000018  // I2C Master Masked Interrupt
+                                            // Status
+#define I2C_O_MICR              0x0000001C  // I2C Master Interrupt Clear
+#define I2C_O_MCR               0x00000020  // I2C Master Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MSA register.
+//
+//*****************************************************************************
+#define I2C_MSA_SA_M            0x000000FE  // I2C Slave Address.
+#define I2C_MSA_RS              0x00000001  // Receive not Send
+#define I2C_MSA_SA_S            1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR register.
+//
+//*****************************************************************************
+#define I2C_SOAR_OAR_M          0x0000007F  // I2C Slave Own Address.
+#define I2C_SOAR_OAR_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SCSR register.
+//
+//*****************************************************************************
+#define I2C_SCSR_FBR            0x00000004  // First Byte Received.
+#define I2C_SCSR_TREQ           0x00000002  // Transmit Request.
+#define I2C_SCSR_DA             0x00000001  // Device Active.
+#define I2C_SCSR_RREQ           0x00000001  // Receive Request.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCS register.
+//
+//*****************************************************************************
+#define I2C_MCS_BUSBSY          0x00000040  // Bus Busy.
+#define I2C_MCS_IDLE            0x00000020  // I2C Idle.
+#define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost.
+#define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable.
+#define I2C_MCS_DATACK          0x00000008  // Acknowledge Data.
+#define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address.
+#define I2C_MCS_STOP            0x00000004  // Generate STOP.
+#define I2C_MCS_START           0x00000002  // Generate START.
+#define I2C_MCS_ERROR           0x00000002  // Error.
+#define I2C_MCS_RUN             0x00000001  // I2C Master Enable.
+#define I2C_MCS_BUSY            0x00000001  // I2C Busy.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SDR register.
+//
+//*****************************************************************************
+#define I2C_SDR_DATA_M          0x000000FF  // Data for Transfer.
+#define I2C_SDR_DATA_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MDR register.
+//
+//*****************************************************************************
+#define I2C_MDR_DATA_M          0x000000FF  // Data Transferred.
+#define I2C_MDR_DATA_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MTPR register.
+//
+//*****************************************************************************
+#define I2C_MTPR_TPR_M          0x000000FF  // SCL Clock Period.
+#define I2C_MTPR_TPR_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_STOPIM         0x00000004  // Stop Condition Interrupt Mask.
+#define I2C_SIMR_STARTIM        0x00000002  // Start Condition Interrupt Mask.
+#define I2C_SIMR_DATAIM         0x00000001  // Data Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_STOPRIS        0x00000004  // Stop Condition Raw Interrupt
+                                            // Status.
+#define I2C_SRIS_STARTRIS       0x00000002  // Start Condition Raw Interrupt
+                                            // Status.
+#define I2C_SRIS_DATARIS        0x00000001  // Data Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MIMR register.
+//
+//*****************************************************************************
+#define I2C_MIMR_IM             0x00000001  // Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MRIS register.
+//
+//*****************************************************************************
+#define I2C_MRIS_RIS            0x00000001  // Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_STOPMIS        0x00000004  // Stop Condition Masked Interrupt
+                                            // Status.
+#define I2C_SMIS_STARTMIS       0x00000002  // Start Condition Masked Interrupt
+                                            // Status.
+#define I2C_SMIS_DATAMIS        0x00000001  // Data Masked Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_STOPIC         0x00000004  // Stop Condition Interrupt Clear.
+#define I2C_SICR_STARTIC        0x00000002  // Start Condition Interrupt Clear.
+#define I2C_SICR_DATAIC         0x00000001  // Data Clear Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MMIS register.
+//
+//*****************************************************************************
+#define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MICR register.
+//
+//*****************************************************************************
+#define I2C_MICR_IC             0x00000001  // Interrupt Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR register.
+//
+//*****************************************************************************
+#define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable.
+#define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable.
+#define I2C_MCR_LPBK            0x00000001  // I2C Loopback.
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the offsets between the I2C master
+// and slave registers.
+//
+//*****************************************************************************
+#define I2C_O_SLAVE             0x00000800  // Offset from master to slave
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the I2C master register offsets.
+//
+//*****************************************************************************
+#define I2C_MASTER_O_SA         0x00000000  // Slave address register
+#define I2C_MASTER_O_CS         0x00000004  // Control and Status register
+#define I2C_MASTER_O_DR         0x00000008  // Data register
+#define I2C_MASTER_O_TPR        0x0000000C  // Timer period register
+#define I2C_MASTER_O_IMR        0x00000010  // Interrupt mask register
+#define I2C_MASTER_O_RIS        0x00000014  // Raw interrupt status register
+#define I2C_MASTER_O_MIS        0x00000018  // Masked interrupt status reg
+#define I2C_MASTER_O_MICR       0x0000001C  // Interrupt clear register
+#define I2C_MASTER_O_CR         0x00000020  // Configuration register
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the I2C slave register offsets.
+//
+//*****************************************************************************
+#define I2C_SLAVE_O_SICR        0x00000018  // Interrupt clear register
+#define I2C_SLAVE_O_MIS         0x00000014  // Masked interrupt status reg
+#define I2C_SLAVE_O_RIS         0x00000010  // Raw interrupt status register
+#define I2C_SLAVE_O_IM          0x0000000C  // Interrupt mask register
+#define I2C_SLAVE_O_DR          0x00000008  // Data register
+#define I2C_SLAVE_O_CSR         0x00000004  // Control/Status register
+#define I2C_SLAVE_O_OAR         0x00000000  // Own address register
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C master
+// slave address register.
+//
+//*****************************************************************************
+#define I2C_MASTER_SA_SA_MASK   0x000000FE  // Slave address
+#define I2C_MASTER_SA_RS        0x00000001  // Receive/send
+#define I2C_MASTER_SA_SA_SHIFT  1
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Control and Status register.
+//
+//*****************************************************************************
+#define I2C_MASTER_CS_BUS_BUSY  0x00000040  // Bus busy
+#define I2C_MASTER_CS_IDLE      0x00000020  // Idle
+#define I2C_MASTER_CS_ERR_MASK  0x0000001C
+#define I2C_MASTER_CS_BUSY      0x00000001  // Controller is TX/RX data
+#define I2C_MASTER_CS_ERROR     0x00000002  // Error occurred
+#define I2C_MASTER_CS_ADDR_ACK  0x00000004  // Address byte not acknowledged
+#define I2C_MASTER_CS_DATA_ACK  0x00000008  // Data byte not acknowledged
+#define I2C_MASTER_CS_ARB_LOST  0x00000010  // Lost arbitration
+#define I2C_MASTER_CS_ACK       0x00000008  // Acknowlegde
+#define I2C_MASTER_CS_STOP      0x00000004  // Stop
+#define I2C_MASTER_CS_START     0x00000002  // Start
+#define I2C_MASTER_CS_RUN       0x00000001  // Run
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the values used in determining the
+// contents of the I2C Master Timer Period register.
+//
+//*****************************************************************************
+#define I2C_SCL_FAST            400000      // SCL fast frequency
+#define I2C_SCL_STANDARD        100000      // SCL standard frequency
+#define I2C_MASTER_TPR_SCL_LP   0x00000006  // SCL low period
+#define I2C_MASTER_TPR_SCL_HP   0x00000004  // SCL high period
+#define I2C_MASTER_TPR_SCL      (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Interrupt Mask register.
+//
+//*****************************************************************************
+#define I2C_MASTER_IMR_IM       0x00000001  // Master interrupt mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Raw Interrupt Status register.
+//
+//*****************************************************************************
+#define I2C_MASTER_RIS_RIS      0x00000001  // Master raw interrupt status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Masked Interrupt Status register.
+//
+//*****************************************************************************
+#define I2C_MASTER_MIS_MIS      0x00000001  // Master masked interrupt status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Interrupt Clear register.
+//
+//*****************************************************************************
+#define I2C_MASTER_MICR_IC      0x00000001  // Master interrupt clear
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Configuration register.
+//
+//*****************************************************************************
+#define I2C_MASTER_CR_SFE       0x00000020  // Slave function enable
+#define I2C_MASTER_CR_MFE       0x00000010  // Master function enable
+#define I2C_MASTER_CR_LPBK      0x00000001  // Loopback enable
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave Own
+// Address register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F  // Slave address
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave
+// Control/Status register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_CSR_FBR       0x00000004  // First byte received from master
+#define I2C_SLAVE_CSR_TREQ      0x00000002  // Transmit request received
+#define I2C_SLAVE_CSR_DA        0x00000001  // Enable the device
+#define I2C_SLAVE_CSR_RREQ      0x00000001  // Receive data from I2C master
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave
+// Interrupt Mask register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_IMR_IM        0x00000001  // Slave interrupt mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave Raw
+// Interrupt Status register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_RIS_RIS       0x00000001  // Slave raw interrupt status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave
+// Masked Interrupt Status register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_MIS_MIS       0x00000001  // Slave masked interrupt status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave
+// Interrupt Clear register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_SICR_IC       0x00000001  // Slave interrupt clear
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SIMR
+// register.
+//
+//*****************************************************************************
+#define I2C_SIMR_IM             0x00000001  // Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SRIS
+// register.
+//
+//*****************************************************************************
+#define I2C_SRIS_RIS            0x00000001  // Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SMIS
+// register.
+//
+//*****************************************************************************
+#define I2C_SMIS_MIS            0x00000001  // Masked Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SICR
+// register.
+//
+//*****************************************************************************
+#define I2C_SICR_IC             0x00000001  // Clear Interrupt.
+
+#endif
+
+#endif // __HW_I2C_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_ints.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_ints.h
new file mode 100644
index 0000000..238a51a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_ints.h
@@ -0,0 +1,134 @@
+//*****************************************************************************
+//
+// hw_ints.h - Macros that define the interrupt assignment on Stellaris.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HW_INTS_H__
+#define __HW_INTS_H__
+
+//*****************************************************************************
+//
+// The following are defines for the fault assignments.
+//
+//*****************************************************************************
+#define FAULT_NMI               2           // NMI fault
+#define FAULT_HARD              3           // Hard fault
+#define FAULT_MPU               4           // MPU fault
+#define FAULT_BUS               5           // Bus fault
+#define FAULT_USAGE             6           // Usage fault
+#define FAULT_SVCALL            11          // SVCall
+#define FAULT_DEBUG             12          // Debug monitor
+#define FAULT_PENDSV            14          // PendSV
+#define FAULT_SYSTICK           15          // System Tick
+
+//*****************************************************************************
+//
+// The following are defines for the interrupt assignments.
+//
+//*****************************************************************************
+#define INT_GPIOA               16          // GPIO Port A
+#define INT_GPIOB               17          // GPIO Port B
+#define INT_GPIOC               18          // GPIO Port C
+#define INT_GPIOD               19          // GPIO Port D
+#define INT_GPIOE               20          // GPIO Port E
+#define INT_UART0               21          // UART0 Rx and Tx
+#define INT_UART1               22          // UART1 Rx and Tx
+#define INT_SSI0                23          // SSI0 Rx and Tx
+#define INT_I2C0                24          // I2C0 Master and Slave
+#define INT_PWM_FAULT           25          // PWM Fault
+#define INT_PWM0                26          // PWM Generator 0
+#define INT_PWM1                27          // PWM Generator 1
+#define INT_PWM2                28          // PWM Generator 2
+#define INT_QEI0                29          // Quadrature Encoder 0
+#define INT_ADC0                30          // ADC Sequence 0
+#define INT_ADC1                31          // ADC Sequence 1
+#define INT_ADC2                32          // ADC Sequence 2
+#define INT_ADC3                33          // ADC Sequence 3
+#define INT_WATCHDOG            34          // Watchdog timer
+#define INT_TIMER0A             35          // Timer 0 subtimer A
+#define INT_TIMER0B             36          // Timer 0 subtimer B
+#define INT_TIMER1A             37          // Timer 1 subtimer A
+#define INT_TIMER1B             38          // Timer 1 subtimer B
+#define INT_TIMER2A             39          // Timer 2 subtimer A
+#define INT_TIMER2B             40          // Timer 2 subtimer B
+#define INT_COMP0               41          // Analog Comparator 0
+#define INT_COMP1               42          // Analog Comparator 1
+#define INT_COMP2               43          // Analog Comparator 2
+#define INT_SYSCTL              44          // System Control (PLL, OSC, BO)
+#define INT_FLASH               45          // FLASH Control
+#define INT_GPIOF               46          // GPIO Port F
+#define INT_GPIOG               47          // GPIO Port G
+#define INT_GPIOH               48          // GPIO Port H
+#define INT_UART2               49          // UART2 Rx and Tx
+#define INT_SSI1                50          // SSI1 Rx and Tx
+#define INT_TIMER3A             51          // Timer 3 subtimer A
+#define INT_TIMER3B             52          // Timer 3 subtimer B
+#define INT_I2C1                53          // I2C1 Master and Slave
+#define INT_QEI1                54          // Quadrature Encoder 1
+#define INT_CAN0                55          // CAN0
+#define INT_CAN1                56          // CAN1
+#define INT_CAN2                57          // CAN2
+#define INT_ETH                 58          // Ethernet
+#define INT_HIBERNATE           59          // Hibernation module
+#define INT_USB0                60          // USB 0 Controller
+#define INT_PWM3                61          // PWM Generator 3
+#define INT_UDMA                62          // uDMA controller
+#define INT_UDMAERR             63          // uDMA Error
+
+//*****************************************************************************
+//
+// The following are defines for the total number of interrupts.
+//
+//*****************************************************************************
+#define NUM_INTERRUPTS          64
+
+//*****************************************************************************
+//
+// The following are defines for the total number of priority levels.
+//
+//*****************************************************************************
+#define NUM_PRIORITY            8
+#define NUM_PRIORITY_BITS       3
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the interrupt assignments.
+//
+//*****************************************************************************
+#define INT_SSI                 23          // SSI Rx and Tx
+#define INT_I2C                 24          // I2C Master and Slave
+#define INT_QEI                 29          // Quadrature Encoder
+
+#endif
+
+#endif // __HW_INTS_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_memmap.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_memmap.h
new file mode 100644
index 0000000..1f5e7db
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_memmap.h
@@ -0,0 +1,111 @@
+//*****************************************************************************
+//
+// hw_memmap.h - Macros defining the memory map of Stellaris.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HW_MEMMAP_H__
+#define __HW_MEMMAP_H__
+
+//*****************************************************************************
+//
+// The following are defines for the base address of the memories and
+// peripherals.
+//
+//*****************************************************************************
+#define FLASH_BASE              0x00000000  // FLASH memory
+#define SRAM_BASE               0x20000000  // SRAM memory
+#define WATCHDOG_BASE           0x40000000  // Watchdog
+#define GPIO_PORTA_BASE         0x40004000  // GPIO Port A
+#define GPIO_PORTB_BASE         0x40005000  // GPIO Port B
+#define GPIO_PORTC_BASE         0x40006000  // GPIO Port C
+#define GPIO_PORTD_BASE         0x40007000  // GPIO Port D
+#define SSI0_BASE               0x40008000  // SSI0
+#define SSI1_BASE               0x40009000  // SSI1
+#define UART0_BASE              0x4000C000  // UART0
+#define UART1_BASE              0x4000D000  // UART1
+#define UART2_BASE              0x4000E000  // UART2
+#define I2C0_MASTER_BASE        0x40020000  // I2C0 Master
+#define I2C0_SLAVE_BASE         0x40020800  // I2C0 Slave
+#define I2C1_MASTER_BASE        0x40021000  // I2C1 Master
+#define I2C1_SLAVE_BASE         0x40021800  // I2C1 Slave
+#define GPIO_PORTE_BASE         0x40024000  // GPIO Port E
+#define GPIO_PORTF_BASE         0x40025000  // GPIO Port F
+#define GPIO_PORTG_BASE         0x40026000  // GPIO Port G
+#define GPIO_PORTH_BASE         0x40027000  // GPIO Port H
+#define PWM_BASE                0x40028000  // PWM
+#define QEI0_BASE               0x4002C000  // QEI0
+#define QEI1_BASE               0x4002D000  // QEI1
+#define TIMER0_BASE             0x40030000  // Timer0
+#define TIMER1_BASE             0x40031000  // Timer1
+#define TIMER2_BASE             0x40032000  // Timer2
+#define TIMER3_BASE             0x40033000  // Timer3
+#define ADC_BASE                0x40038000  // ADC
+#define COMP_BASE               0x4003C000  // Analog comparators
+#define CAN0_BASE               0x40040000  // CAN0
+#define CAN1_BASE               0x40041000  // CAN1
+#define CAN2_BASE               0x40042000  // CAN2
+#define ETH_BASE                0x40048000  // Ethernet
+#define MAC_BASE                0x40048000  // Ethernet
+#define USB0_BASE               0x40050000  // USB 0 Controller
+#define GPIO_PORTA_AHB_BASE     0x40058000  // GPIO Port A (high speed)
+#define GPIO_PORTB_AHB_BASE     0x40059000  // GPIO Port B (high speed)
+#define GPIO_PORTC_AHB_BASE     0x4005A000  // GPIO Port C (high speed)
+#define GPIO_PORTD_AHB_BASE     0x4005B000  // GPIO Port D (high speed)
+#define GPIO_PORTE_AHB_BASE     0x4005C000  // GPIO Port E (high speed)
+#define GPIO_PORTF_AHB_BASE     0x4005D000  // GPIO Port F (high speed)
+#define GPIO_PORTG_AHB_BASE     0x4005E000  // GPIO Port G (high speed)
+#define GPIO_PORTH_AHB_BASE     0x4005F000  // GPIO Port H (high speed)
+#define HIB_BASE                0x400FC000  // Hibernation Module
+#define FLASH_CTRL_BASE         0x400FD000  // FLASH Controller
+#define SYSCTL_BASE             0x400FE000  // System Control
+#define UDMA_BASE               0x400FF000  // uDMA Controller
+#define ITM_BASE                0xE0000000  // Instrumentation Trace Macrocell
+#define DWT_BASE                0xE0001000  // Data Watchpoint and Trace
+#define FPB_BASE                0xE0002000  // FLASH Patch and Breakpoint
+#define NVIC_BASE               0xE000E000  // Nested Vectored Interrupt Ctrl
+#define TPIU_BASE               0xE0040000  // Trace Port Interface Unit
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the base address of the memories
+// and peripherals.
+//
+//*****************************************************************************
+#define SSI_BASE                0x40008000  // SSI
+#define I2C_MASTER_BASE         0x40020000  // I2C Master
+#define I2C_SLAVE_BASE          0x40020800  // I2C Slave
+#define QEI_BASE                0x4002C000  // QEI
+
+#endif
+
+#endif // __HW_MEMMAP_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_nvic.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_nvic.h
new file mode 100644
index 0000000..10b7ffc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_nvic.h
@@ -0,0 +1,1024 @@
+//*****************************************************************************
+//
+// hw_nvic.h - Macros used when accessing the NVIC hardware.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HW_NVIC_H__
+#define __HW_NVIC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the NVIC register addresses.
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE           0xE000E004  // Interrupt Controller Type Reg.
+#define NVIC_ST_CTRL            0xE000E010  // SysTick Control and Status Reg.
+#define NVIC_ST_RELOAD          0xE000E014  // SysTick Reload Value Register
+#define NVIC_ST_CURRENT         0xE000E018  // SysTick Current Value Register
+#define NVIC_ST_CAL             0xE000E01C  // SysTick Calibration Value Reg.
+#define NVIC_EN0                0xE000E100  // IRQ 0 to 31 Set Enable Register
+#define NVIC_EN1                0xE000E104  // IRQ 32 to 63 Set Enable Register
+#define NVIC_DIS0               0xE000E180  // IRQ 0 to 31 Clear Enable Reg.
+#define NVIC_DIS1               0xE000E184  // IRQ 32 to 63 Clear Enable Reg.
+#define NVIC_PEND0              0xE000E200  // IRQ 0 to 31 Set Pending Register
+#define NVIC_PEND1              0xE000E204  // IRQ 32 to 63 Set Pending Reg.
+#define NVIC_UNPEND0            0xE000E280  // IRQ 0 to 31 Clear Pending Reg.
+#define NVIC_UNPEND1            0xE000E284  // IRQ 32 to 63 Clear Pending Reg.
+#define NVIC_ACTIVE0            0xE000E300  // IRQ 0 to 31 Active Register
+#define NVIC_ACTIVE1            0xE000E304  // IRQ 32 to 63 Active Register
+#define NVIC_PRI0               0xE000E400  // IRQ 0 to 3 Priority Register
+#define NVIC_PRI1               0xE000E404  // IRQ 4 to 7 Priority Register
+#define NVIC_PRI2               0xE000E408  // IRQ 8 to 11 Priority Register
+#define NVIC_PRI3               0xE000E40C  // IRQ 12 to 15 Priority Register
+#define NVIC_PRI4               0xE000E410  // IRQ 16 to 19 Priority Register
+#define NVIC_PRI5               0xE000E414  // IRQ 20 to 23 Priority Register
+#define NVIC_PRI6               0xE000E418  // IRQ 24 to 27 Priority Register
+#define NVIC_PRI7               0xE000E41C  // IRQ 28 to 31 Priority Register
+#define NVIC_PRI8               0xE000E420  // IRQ 32 to 35 Priority Register
+#define NVIC_PRI9               0xE000E424  // IRQ 36 to 39 Priority Register
+#define NVIC_PRI10              0xE000E428  // IRQ 40 to 43 Priority Register
+#define NVIC_PRI11              0xE000E42C  // IRQ 44 to 47 Priority Register
+#define NVIC_CPUID              0xE000ED00  // CPUID Base Register
+#define NVIC_INT_CTRL           0xE000ED04  // Interrupt Control State Register
+#define NVIC_VTABLE             0xE000ED08  // Vector Table Offset Register
+#define NVIC_APINT              0xE000ED0C  // App. Int & Reset Control Reg.
+#define NVIC_SYS_CTRL           0xE000ED10  // System Control Register
+#define NVIC_CFG_CTRL           0xE000ED14  // Configuration Control Register
+#define NVIC_SYS_PRI1           0xE000ED18  // Sys. Handlers 4 to 7 Priority
+#define NVIC_SYS_PRI2           0xE000ED1C  // Sys. Handlers 8 to 11 Priority
+#define NVIC_SYS_PRI3           0xE000ED20  // Sys. Handlers 12 to 15 Priority
+#define NVIC_SYS_HND_CTRL       0xE000ED24  // System Handler Control and State
+#define NVIC_FAULT_STAT         0xE000ED28  // Configurable Fault Status Reg.
+#define NVIC_HFAULT_STAT        0xE000ED2C  // Hard Fault Status Register
+#define NVIC_DEBUG_STAT         0xE000ED30  // Debug Status Register
+#define NVIC_MM_ADDR            0xE000ED34  // Mem Manage Address Register
+#define NVIC_FAULT_ADDR         0xE000ED38  // Bus Fault Address Register
+#define NVIC_MPU_TYPE           0xE000ED90  // MPU Type Register
+#define NVIC_MPU_CTRL           0xE000ED94  // MPU Control Register
+#define NVIC_MPU_NUMBER         0xE000ED98  // MPU Region Number Register
+#define NVIC_MPU_BASE           0xE000ED9C  // MPU Region Base Address Register
+#define NVIC_MPU_ATTR           0xE000EDA0  // MPU Region Attribute & Size Reg.
+#define NVIC_DBG_CTRL           0xE000EDF0  // Debug Control and Status Reg.
+#define NVIC_DBG_XFER           0xE000EDF4  // Debug Core Reg. Transfer Select
+#define NVIC_DBG_DATA           0xE000EDF8  // Debug Core Register Data
+#define NVIC_DBG_INT            0xE000EDFC  // Debug Reset Interrupt Control
+#define NVIC_SW_TRIG            0xE000EF00  // Software Trigger Interrupt Reg.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE_LINES_M   0x0000001F  // Number of interrupt lines (x32)
+#define NVIC_INT_TYPE_LINES_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CTRL_COUNT      0x00010000  // Count flag
+#define NVIC_ST_CTRL_CLK_SRC    0x00000004  // Clock Source
+#define NVIC_ST_CTRL_INTEN      0x00000002  // Interrupt enable
+#define NVIC_ST_CTRL_ENABLE     0x00000001  // Counter mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
+//
+//*****************************************************************************
+#define NVIC_ST_RELOAD_M        0x00FFFFFF  // Counter load value
+#define NVIC_ST_RELOAD_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CURRENT
+// register.
+//
+//*****************************************************************************
+#define NVIC_ST_CURRENT_M       0x00FFFFFF  // Counter current value
+#define NVIC_ST_CURRENT_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CAL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CAL_NOREF       0x80000000  // No reference clock
+#define NVIC_ST_CAL_SKEW        0x40000000  // Clock skew
+#define NVIC_ST_CAL_ONEMS_M     0x00FFFFFF  // 1ms reference value
+#define NVIC_ST_CAL_ONEMS_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN0 register.
+//
+//*****************************************************************************
+#define NVIC_EN0_INT31          0x80000000  // Interrupt 31 enable
+#define NVIC_EN0_INT30          0x40000000  // Interrupt 30 enable
+#define NVIC_EN0_INT29          0x20000000  // Interrupt 29 enable
+#define NVIC_EN0_INT28          0x10000000  // Interrupt 28 enable
+#define NVIC_EN0_INT27          0x08000000  // Interrupt 27 enable
+#define NVIC_EN0_INT26          0x04000000  // Interrupt 26 enable
+#define NVIC_EN0_INT25          0x02000000  // Interrupt 25 enable
+#define NVIC_EN0_INT24          0x01000000  // Interrupt 24 enable
+#define NVIC_EN0_INT23          0x00800000  // Interrupt 23 enable
+#define NVIC_EN0_INT22          0x00400000  // Interrupt 22 enable
+#define NVIC_EN0_INT21          0x00200000  // Interrupt 21 enable
+#define NVIC_EN0_INT20          0x00100000  // Interrupt 20 enable
+#define NVIC_EN0_INT19          0x00080000  // Interrupt 19 enable
+#define NVIC_EN0_INT18          0x00040000  // Interrupt 18 enable
+#define NVIC_EN0_INT17          0x00020000  // Interrupt 17 enable
+#define NVIC_EN0_INT16          0x00010000  // Interrupt 16 enable
+#define NVIC_EN0_INT15          0x00008000  // Interrupt 15 enable
+#define NVIC_EN0_INT14          0x00004000  // Interrupt 14 enable
+#define NVIC_EN0_INT13          0x00002000  // Interrupt 13 enable
+#define NVIC_EN0_INT12          0x00001000  // Interrupt 12 enable
+#define NVIC_EN0_INT11          0x00000800  // Interrupt 11 enable
+#define NVIC_EN0_INT10          0x00000400  // Interrupt 10 enable
+#define NVIC_EN0_INT9           0x00000200  // Interrupt 9 enable
+#define NVIC_EN0_INT8           0x00000100  // Interrupt 8 enable
+#define NVIC_EN0_INT7           0x00000080  // Interrupt 7 enable
+#define NVIC_EN0_INT6           0x00000040  // Interrupt 6 enable
+#define NVIC_EN0_INT5           0x00000020  // Interrupt 5 enable
+#define NVIC_EN0_INT4           0x00000010  // Interrupt 4 enable
+#define NVIC_EN0_INT3           0x00000008  // Interrupt 3 enable
+#define NVIC_EN0_INT2           0x00000004  // Interrupt 2 enable
+#define NVIC_EN0_INT1           0x00000002  // Interrupt 1 enable
+#define NVIC_EN0_INT0           0x00000001  // Interrupt 0 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN1 register.
+//
+//*****************************************************************************
+#define NVIC_EN1_INT59          0x08000000  // Interrupt 59 enable
+#define NVIC_EN1_INT58          0x04000000  // Interrupt 58 enable
+#define NVIC_EN1_INT57          0x02000000  // Interrupt 57 enable
+#define NVIC_EN1_INT56          0x01000000  // Interrupt 56 enable
+#define NVIC_EN1_INT55          0x00800000  // Interrupt 55 enable
+#define NVIC_EN1_INT54          0x00400000  // Interrupt 54 enable
+#define NVIC_EN1_INT53          0x00200000  // Interrupt 53 enable
+#define NVIC_EN1_INT52          0x00100000  // Interrupt 52 enable
+#define NVIC_EN1_INT51          0x00080000  // Interrupt 51 enable
+#define NVIC_EN1_INT50          0x00040000  // Interrupt 50 enable
+#define NVIC_EN1_INT49          0x00020000  // Interrupt 49 enable
+#define NVIC_EN1_INT48          0x00010000  // Interrupt 48 enable
+#define NVIC_EN1_INT47          0x00008000  // Interrupt 47 enable
+#define NVIC_EN1_INT46          0x00004000  // Interrupt 46 enable
+#define NVIC_EN1_INT45          0x00002000  // Interrupt 45 enable
+#define NVIC_EN1_INT44          0x00001000  // Interrupt 44 enable
+#define NVIC_EN1_INT43          0x00000800  // Interrupt 43 enable
+#define NVIC_EN1_INT42          0x00000400  // Interrupt 42 enable
+#define NVIC_EN1_INT41          0x00000200  // Interrupt 41 enable
+#define NVIC_EN1_INT40          0x00000100  // Interrupt 40 enable
+#define NVIC_EN1_INT39          0x00000080  // Interrupt 39 enable
+#define NVIC_EN1_INT38          0x00000040  // Interrupt 38 enable
+#define NVIC_EN1_INT37          0x00000020  // Interrupt 37 enable
+#define NVIC_EN1_INT36          0x00000010  // Interrupt 36 enable
+#define NVIC_EN1_INT35          0x00000008  // Interrupt 35 enable
+#define NVIC_EN1_INT34          0x00000004  // Interrupt 34 enable
+#define NVIC_EN1_INT33          0x00000002  // Interrupt 33 enable
+#define NVIC_EN1_INT32          0x00000001  // Interrupt 32 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS0 register.
+//
+//*****************************************************************************
+#define NVIC_DIS0_INT31         0x80000000  // Interrupt 31 disable
+#define NVIC_DIS0_INT30         0x40000000  // Interrupt 30 disable
+#define NVIC_DIS0_INT29         0x20000000  // Interrupt 29 disable
+#define NVIC_DIS0_INT28         0x10000000  // Interrupt 28 disable
+#define NVIC_DIS0_INT27         0x08000000  // Interrupt 27 disable
+#define NVIC_DIS0_INT26         0x04000000  // Interrupt 26 disable
+#define NVIC_DIS0_INT25         0x02000000  // Interrupt 25 disable
+#define NVIC_DIS0_INT24         0x01000000  // Interrupt 24 disable
+#define NVIC_DIS0_INT23         0x00800000  // Interrupt 23 disable
+#define NVIC_DIS0_INT22         0x00400000  // Interrupt 22 disable
+#define NVIC_DIS0_INT21         0x00200000  // Interrupt 21 disable
+#define NVIC_DIS0_INT20         0x00100000  // Interrupt 20 disable
+#define NVIC_DIS0_INT19         0x00080000  // Interrupt 19 disable
+#define NVIC_DIS0_INT18         0x00040000  // Interrupt 18 disable
+#define NVIC_DIS0_INT17         0x00020000  // Interrupt 17 disable
+#define NVIC_DIS0_INT16         0x00010000  // Interrupt 16 disable
+#define NVIC_DIS0_INT15         0x00008000  // Interrupt 15 disable
+#define NVIC_DIS0_INT14         0x00004000  // Interrupt 14 disable
+#define NVIC_DIS0_INT13         0x00002000  // Interrupt 13 disable
+#define NVIC_DIS0_INT12         0x00001000  // Interrupt 12 disable
+#define NVIC_DIS0_INT11         0x00000800  // Interrupt 11 disable
+#define NVIC_DIS0_INT10         0x00000400  // Interrupt 10 disable
+#define NVIC_DIS0_INT9          0x00000200  // Interrupt 9 disable
+#define NVIC_DIS0_INT8          0x00000100  // Interrupt 8 disable
+#define NVIC_DIS0_INT7          0x00000080  // Interrupt 7 disable
+#define NVIC_DIS0_INT6          0x00000040  // Interrupt 6 disable
+#define NVIC_DIS0_INT5          0x00000020  // Interrupt 5 disable
+#define NVIC_DIS0_INT4          0x00000010  // Interrupt 4 disable
+#define NVIC_DIS0_INT3          0x00000008  // Interrupt 3 disable
+#define NVIC_DIS0_INT2          0x00000004  // Interrupt 2 disable
+#define NVIC_DIS0_INT1          0x00000002  // Interrupt 1 disable
+#define NVIC_DIS0_INT0          0x00000001  // Interrupt 0 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS1 register.
+//
+//*****************************************************************************
+#define NVIC_DIS1_INT59         0x08000000  // Interrupt 59 disable
+#define NVIC_DIS1_INT58         0x04000000  // Interrupt 58 disable
+#define NVIC_DIS1_INT57         0x02000000  // Interrupt 57 disable
+#define NVIC_DIS1_INT56         0x01000000  // Interrupt 56 disable
+#define NVIC_DIS1_INT55         0x00800000  // Interrupt 55 disable
+#define NVIC_DIS1_INT54         0x00400000  // Interrupt 54 disable
+#define NVIC_DIS1_INT53         0x00200000  // Interrupt 53 disable
+#define NVIC_DIS1_INT52         0x00100000  // Interrupt 52 disable
+#define NVIC_DIS1_INT51         0x00080000  // Interrupt 51 disable
+#define NVIC_DIS1_INT50         0x00040000  // Interrupt 50 disable
+#define NVIC_DIS1_INT49         0x00020000  // Interrupt 49 disable
+#define NVIC_DIS1_INT48         0x00010000  // Interrupt 48 disable
+#define NVIC_DIS1_INT47         0x00008000  // Interrupt 47 disable
+#define NVIC_DIS1_INT46         0x00004000  // Interrupt 46 disable
+#define NVIC_DIS1_INT45         0x00002000  // Interrupt 45 disable
+#define NVIC_DIS1_INT44         0x00001000  // Interrupt 44 disable
+#define NVIC_DIS1_INT43         0x00000800  // Interrupt 43 disable
+#define NVIC_DIS1_INT42         0x00000400  // Interrupt 42 disable
+#define NVIC_DIS1_INT41         0x00000200  // Interrupt 41 disable
+#define NVIC_DIS1_INT40         0x00000100  // Interrupt 40 disable
+#define NVIC_DIS1_INT39         0x00000080  // Interrupt 39 disable
+#define NVIC_DIS1_INT38         0x00000040  // Interrupt 38 disable
+#define NVIC_DIS1_INT37         0x00000020  // Interrupt 37 disable
+#define NVIC_DIS1_INT36         0x00000010  // Interrupt 36 disable
+#define NVIC_DIS1_INT35         0x00000008  // Interrupt 35 disable
+#define NVIC_DIS1_INT34         0x00000004  // Interrupt 34 disable
+#define NVIC_DIS1_INT33         0x00000002  // Interrupt 33 disable
+#define NVIC_DIS1_INT32         0x00000001  // Interrupt 32 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND0 register.
+//
+//*****************************************************************************
+#define NVIC_PEND0_INT31        0x80000000  // Interrupt 31 pend
+#define NVIC_PEND0_INT30        0x40000000  // Interrupt 30 pend
+#define NVIC_PEND0_INT29        0x20000000  // Interrupt 29 pend
+#define NVIC_PEND0_INT28        0x10000000  // Interrupt 28 pend
+#define NVIC_PEND0_INT27        0x08000000  // Interrupt 27 pend
+#define NVIC_PEND0_INT26        0x04000000  // Interrupt 26 pend
+#define NVIC_PEND0_INT25        0x02000000  // Interrupt 25 pend
+#define NVIC_PEND0_INT24        0x01000000  // Interrupt 24 pend
+#define NVIC_PEND0_INT23        0x00800000  // Interrupt 23 pend
+#define NVIC_PEND0_INT22        0x00400000  // Interrupt 22 pend
+#define NVIC_PEND0_INT21        0x00200000  // Interrupt 21 pend
+#define NVIC_PEND0_INT20        0x00100000  // Interrupt 20 pend
+#define NVIC_PEND0_INT19        0x00080000  // Interrupt 19 pend
+#define NVIC_PEND0_INT18        0x00040000  // Interrupt 18 pend
+#define NVIC_PEND0_INT17        0x00020000  // Interrupt 17 pend
+#define NVIC_PEND0_INT16        0x00010000  // Interrupt 16 pend
+#define NVIC_PEND0_INT15        0x00008000  // Interrupt 15 pend
+#define NVIC_PEND0_INT14        0x00004000  // Interrupt 14 pend
+#define NVIC_PEND0_INT13        0x00002000  // Interrupt 13 pend
+#define NVIC_PEND0_INT12        0x00001000  // Interrupt 12 pend
+#define NVIC_PEND0_INT11        0x00000800  // Interrupt 11 pend
+#define NVIC_PEND0_INT10        0x00000400  // Interrupt 10 pend
+#define NVIC_PEND0_INT9         0x00000200  // Interrupt 9 pend
+#define NVIC_PEND0_INT8         0x00000100  // Interrupt 8 pend
+#define NVIC_PEND0_INT7         0x00000080  // Interrupt 7 pend
+#define NVIC_PEND0_INT6         0x00000040  // Interrupt 6 pend
+#define NVIC_PEND0_INT5         0x00000020  // Interrupt 5 pend
+#define NVIC_PEND0_INT4         0x00000010  // Interrupt 4 pend
+#define NVIC_PEND0_INT3         0x00000008  // Interrupt 3 pend
+#define NVIC_PEND0_INT2         0x00000004  // Interrupt 2 pend
+#define NVIC_PEND0_INT1         0x00000002  // Interrupt 1 pend
+#define NVIC_PEND0_INT0         0x00000001  // Interrupt 0 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND1 register.
+//
+//*****************************************************************************
+#define NVIC_PEND1_INT59        0x08000000  // Interrupt 59 pend
+#define NVIC_PEND1_INT58        0x04000000  // Interrupt 58 pend
+#define NVIC_PEND1_INT57        0x02000000  // Interrupt 57 pend
+#define NVIC_PEND1_INT56        0x01000000  // Interrupt 56 pend
+#define NVIC_PEND1_INT55        0x00800000  // Interrupt 55 pend
+#define NVIC_PEND1_INT54        0x00400000  // Interrupt 54 pend
+#define NVIC_PEND1_INT53        0x00200000  // Interrupt 53 pend
+#define NVIC_PEND1_INT52        0x00100000  // Interrupt 52 pend
+#define NVIC_PEND1_INT51        0x00080000  // Interrupt 51 pend
+#define NVIC_PEND1_INT50        0x00040000  // Interrupt 50 pend
+#define NVIC_PEND1_INT49        0x00020000  // Interrupt 49 pend
+#define NVIC_PEND1_INT48        0x00010000  // Interrupt 48 pend
+#define NVIC_PEND1_INT47        0x00008000  // Interrupt 47 pend
+#define NVIC_PEND1_INT46        0x00004000  // Interrupt 46 pend
+#define NVIC_PEND1_INT45        0x00002000  // Interrupt 45 pend
+#define NVIC_PEND1_INT44        0x00001000  // Interrupt 44 pend
+#define NVIC_PEND1_INT43        0x00000800  // Interrupt 43 pend
+#define NVIC_PEND1_INT42        0x00000400  // Interrupt 42 pend
+#define NVIC_PEND1_INT41        0x00000200  // Interrupt 41 pend
+#define NVIC_PEND1_INT40        0x00000100  // Interrupt 40 pend
+#define NVIC_PEND1_INT39        0x00000080  // Interrupt 39 pend
+#define NVIC_PEND1_INT38        0x00000040  // Interrupt 38 pend
+#define NVIC_PEND1_INT37        0x00000020  // Interrupt 37 pend
+#define NVIC_PEND1_INT36        0x00000010  // Interrupt 36 pend
+#define NVIC_PEND1_INT35        0x00000008  // Interrupt 35 pend
+#define NVIC_PEND1_INT34        0x00000004  // Interrupt 34 pend
+#define NVIC_PEND1_INT33        0x00000002  // Interrupt 33 pend
+#define NVIC_PEND1_INT32        0x00000001  // Interrupt 32 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND0 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND0_INT31      0x80000000  // Interrupt 31 unpend
+#define NVIC_UNPEND0_INT30      0x40000000  // Interrupt 30 unpend
+#define NVIC_UNPEND0_INT29      0x20000000  // Interrupt 29 unpend
+#define NVIC_UNPEND0_INT28      0x10000000  // Interrupt 28 unpend
+#define NVIC_UNPEND0_INT27      0x08000000  // Interrupt 27 unpend
+#define NVIC_UNPEND0_INT26      0x04000000  // Interrupt 26 unpend
+#define NVIC_UNPEND0_INT25      0x02000000  // Interrupt 25 unpend
+#define NVIC_UNPEND0_INT24      0x01000000  // Interrupt 24 unpend
+#define NVIC_UNPEND0_INT23      0x00800000  // Interrupt 23 unpend
+#define NVIC_UNPEND0_INT22      0x00400000  // Interrupt 22 unpend
+#define NVIC_UNPEND0_INT21      0x00200000  // Interrupt 21 unpend
+#define NVIC_UNPEND0_INT20      0x00100000  // Interrupt 20 unpend
+#define NVIC_UNPEND0_INT19      0x00080000  // Interrupt 19 unpend
+#define NVIC_UNPEND0_INT18      0x00040000  // Interrupt 18 unpend
+#define NVIC_UNPEND0_INT17      0x00020000  // Interrupt 17 unpend
+#define NVIC_UNPEND0_INT16      0x00010000  // Interrupt 16 unpend
+#define NVIC_UNPEND0_INT15      0x00008000  // Interrupt 15 unpend
+#define NVIC_UNPEND0_INT14      0x00004000  // Interrupt 14 unpend
+#define NVIC_UNPEND0_INT13      0x00002000  // Interrupt 13 unpend
+#define NVIC_UNPEND0_INT12      0x00001000  // Interrupt 12 unpend
+#define NVIC_UNPEND0_INT11      0x00000800  // Interrupt 11 unpend
+#define NVIC_UNPEND0_INT10      0x00000400  // Interrupt 10 unpend
+#define NVIC_UNPEND0_INT9       0x00000200  // Interrupt 9 unpend
+#define NVIC_UNPEND0_INT8       0x00000100  // Interrupt 8 unpend
+#define NVIC_UNPEND0_INT7       0x00000080  // Interrupt 7 unpend
+#define NVIC_UNPEND0_INT6       0x00000040  // Interrupt 6 unpend
+#define NVIC_UNPEND0_INT5       0x00000020  // Interrupt 5 unpend
+#define NVIC_UNPEND0_INT4       0x00000010  // Interrupt 4 unpend
+#define NVIC_UNPEND0_INT3       0x00000008  // Interrupt 3 unpend
+#define NVIC_UNPEND0_INT2       0x00000004  // Interrupt 2 unpend
+#define NVIC_UNPEND0_INT1       0x00000002  // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT0       0x00000001  // Interrupt 0 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND1 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND1_INT59      0x08000000  // Interrupt 59 unpend
+#define NVIC_UNPEND1_INT58      0x04000000  // Interrupt 58 unpend
+#define NVIC_UNPEND1_INT57      0x02000000  // Interrupt 57 unpend
+#define NVIC_UNPEND1_INT56      0x01000000  // Interrupt 56 unpend
+#define NVIC_UNPEND1_INT55      0x00800000  // Interrupt 55 unpend
+#define NVIC_UNPEND1_INT54      0x00400000  // Interrupt 54 unpend
+#define NVIC_UNPEND1_INT53      0x00200000  // Interrupt 53 unpend
+#define NVIC_UNPEND1_INT52      0x00100000  // Interrupt 52 unpend
+#define NVIC_UNPEND1_INT51      0x00080000  // Interrupt 51 unpend
+#define NVIC_UNPEND1_INT50      0x00040000  // Interrupt 50 unpend
+#define NVIC_UNPEND1_INT49      0x00020000  // Interrupt 49 unpend
+#define NVIC_UNPEND1_INT48      0x00010000  // Interrupt 48 unpend
+#define NVIC_UNPEND1_INT47      0x00008000  // Interrupt 47 unpend
+#define NVIC_UNPEND1_INT46      0x00004000  // Interrupt 46 unpend
+#define NVIC_UNPEND1_INT45      0x00002000  // Interrupt 45 unpend
+#define NVIC_UNPEND1_INT44      0x00001000  // Interrupt 44 unpend
+#define NVIC_UNPEND1_INT43      0x00000800  // Interrupt 43 unpend
+#define NVIC_UNPEND1_INT42      0x00000400  // Interrupt 42 unpend
+#define NVIC_UNPEND1_INT41      0x00000200  // Interrupt 41 unpend
+#define NVIC_UNPEND1_INT40      0x00000100  // Interrupt 40 unpend
+#define NVIC_UNPEND1_INT39      0x00000080  // Interrupt 39 unpend
+#define NVIC_UNPEND1_INT38      0x00000040  // Interrupt 38 unpend
+#define NVIC_UNPEND1_INT37      0x00000020  // Interrupt 37 unpend
+#define NVIC_UNPEND1_INT36      0x00000010  // Interrupt 36 unpend
+#define NVIC_UNPEND1_INT35      0x00000008  // Interrupt 35 unpend
+#define NVIC_UNPEND1_INT34      0x00000004  // Interrupt 34 unpend
+#define NVIC_UNPEND1_INT33      0x00000002  // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT32      0x00000001  // Interrupt 32 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE0_INT31      0x80000000  // Interrupt 31 active
+#define NVIC_ACTIVE0_INT30      0x40000000  // Interrupt 30 active
+#define NVIC_ACTIVE0_INT29      0x20000000  // Interrupt 29 active
+#define NVIC_ACTIVE0_INT28      0x10000000  // Interrupt 28 active
+#define NVIC_ACTIVE0_INT27      0x08000000  // Interrupt 27 active
+#define NVIC_ACTIVE0_INT26      0x04000000  // Interrupt 26 active
+#define NVIC_ACTIVE0_INT25      0x02000000  // Interrupt 25 active
+#define NVIC_ACTIVE0_INT24      0x01000000  // Interrupt 24 active
+#define NVIC_ACTIVE0_INT23      0x00800000  // Interrupt 23 active
+#define NVIC_ACTIVE0_INT22      0x00400000  // Interrupt 22 active
+#define NVIC_ACTIVE0_INT21      0x00200000  // Interrupt 21 active
+#define NVIC_ACTIVE0_INT20      0x00100000  // Interrupt 20 active
+#define NVIC_ACTIVE0_INT19      0x00080000  // Interrupt 19 active
+#define NVIC_ACTIVE0_INT18      0x00040000  // Interrupt 18 active
+#define NVIC_ACTIVE0_INT17      0x00020000  // Interrupt 17 active
+#define NVIC_ACTIVE0_INT16      0x00010000  // Interrupt 16 active
+#define NVIC_ACTIVE0_INT15      0x00008000  // Interrupt 15 active
+#define NVIC_ACTIVE0_INT14      0x00004000  // Interrupt 14 active
+#define NVIC_ACTIVE0_INT13      0x00002000  // Interrupt 13 active
+#define NVIC_ACTIVE0_INT12      0x00001000  // Interrupt 12 active
+#define NVIC_ACTIVE0_INT11      0x00000800  // Interrupt 11 active
+#define NVIC_ACTIVE0_INT10      0x00000400  // Interrupt 10 active
+#define NVIC_ACTIVE0_INT9       0x00000200  // Interrupt 9 active
+#define NVIC_ACTIVE0_INT8       0x00000100  // Interrupt 8 active
+#define NVIC_ACTIVE0_INT7       0x00000080  // Interrupt 7 active
+#define NVIC_ACTIVE0_INT6       0x00000040  // Interrupt 6 active
+#define NVIC_ACTIVE0_INT5       0x00000020  // Interrupt 5 active
+#define NVIC_ACTIVE0_INT4       0x00000010  // Interrupt 4 active
+#define NVIC_ACTIVE0_INT3       0x00000008  // Interrupt 3 active
+#define NVIC_ACTIVE0_INT2       0x00000004  // Interrupt 2 active
+#define NVIC_ACTIVE0_INT1       0x00000002  // Interrupt 1 active
+#define NVIC_ACTIVE0_INT0       0x00000001  // Interrupt 0 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE1_INT59      0x08000000  // Interrupt 59 active
+#define NVIC_ACTIVE1_INT58      0x04000000  // Interrupt 58 active
+#define NVIC_ACTIVE1_INT57      0x02000000  // Interrupt 57 active
+#define NVIC_ACTIVE1_INT56      0x01000000  // Interrupt 56 active
+#define NVIC_ACTIVE1_INT55      0x00800000  // Interrupt 55 active
+#define NVIC_ACTIVE1_INT54      0x00400000  // Interrupt 54 active
+#define NVIC_ACTIVE1_INT53      0x00200000  // Interrupt 53 active
+#define NVIC_ACTIVE1_INT52      0x00100000  // Interrupt 52 active
+#define NVIC_ACTIVE1_INT51      0x00080000  // Interrupt 51 active
+#define NVIC_ACTIVE1_INT50      0x00040000  // Interrupt 50 active
+#define NVIC_ACTIVE1_INT49      0x00020000  // Interrupt 49 active
+#define NVIC_ACTIVE1_INT48      0x00010000  // Interrupt 48 active
+#define NVIC_ACTIVE1_INT47      0x00008000  // Interrupt 47 active
+#define NVIC_ACTIVE1_INT46      0x00004000  // Interrupt 46 active
+#define NVIC_ACTIVE1_INT45      0x00002000  // Interrupt 45 active
+#define NVIC_ACTIVE1_INT44      0x00001000  // Interrupt 44 active
+#define NVIC_ACTIVE1_INT43      0x00000800  // Interrupt 43 active
+#define NVIC_ACTIVE1_INT42      0x00000400  // Interrupt 42 active
+#define NVIC_ACTIVE1_INT41      0x00000200  // Interrupt 41 active
+#define NVIC_ACTIVE1_INT40      0x00000100  // Interrupt 40 active
+#define NVIC_ACTIVE1_INT39      0x00000080  // Interrupt 39 active
+#define NVIC_ACTIVE1_INT38      0x00000040  // Interrupt 38 active
+#define NVIC_ACTIVE1_INT37      0x00000020  // Interrupt 37 active
+#define NVIC_ACTIVE1_INT36      0x00000010  // Interrupt 36 active
+#define NVIC_ACTIVE1_INT35      0x00000008  // Interrupt 35 active
+#define NVIC_ACTIVE1_INT34      0x00000004  // Interrupt 34 active
+#define NVIC_ACTIVE1_INT33      0x00000002  // Interrupt 33 active
+#define NVIC_ACTIVE1_INT32      0x00000001  // Interrupt 32 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI0 register.
+//
+//*****************************************************************************
+#define NVIC_PRI0_INT3_M        0xFF000000  // Interrupt 3 priority mask
+#define NVIC_PRI0_INT2_M        0x00FF0000  // Interrupt 2 priority mask
+#define NVIC_PRI0_INT1_M        0x0000FF00  // Interrupt 1 priority mask
+#define NVIC_PRI0_INT0_M        0x000000FF  // Interrupt 0 priority mask
+#define NVIC_PRI0_INT3_S        24
+#define NVIC_PRI0_INT2_S        16
+#define NVIC_PRI0_INT1_S        8
+#define NVIC_PRI0_INT0_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_PRI1_INT7_M        0xFF000000  // Interrupt 7 priority mask
+#define NVIC_PRI1_INT6_M        0x00FF0000  // Interrupt 6 priority mask
+#define NVIC_PRI1_INT5_M        0x0000FF00  // Interrupt 5 priority mask
+#define NVIC_PRI1_INT4_M        0x000000FF  // Interrupt 4 priority mask
+#define NVIC_PRI1_INT7_S        24
+#define NVIC_PRI1_INT6_S        16
+#define NVIC_PRI1_INT5_S        8
+#define NVIC_PRI1_INT4_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_PRI2_INT11_M       0xFF000000  // Interrupt 11 priority mask
+#define NVIC_PRI2_INT10_M       0x00FF0000  // Interrupt 10 priority mask
+#define NVIC_PRI2_INT9_M        0x0000FF00  // Interrupt 9 priority mask
+#define NVIC_PRI2_INT8_M        0x000000FF  // Interrupt 8 priority mask
+#define NVIC_PRI2_INT11_S       24
+#define NVIC_PRI2_INT10_S       16
+#define NVIC_PRI2_INT9_S        8
+#define NVIC_PRI2_INT8_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_PRI3_INT15_M       0xFF000000  // Interrupt 15 priority mask
+#define NVIC_PRI3_INT14_M       0x00FF0000  // Interrupt 14 priority mask
+#define NVIC_PRI3_INT13_M       0x0000FF00  // Interrupt 13 priority mask
+#define NVIC_PRI3_INT12_M       0x000000FF  // Interrupt 12 priority mask
+#define NVIC_PRI3_INT15_S       24
+#define NVIC_PRI3_INT14_S       16
+#define NVIC_PRI3_INT13_S       8
+#define NVIC_PRI3_INT12_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI4 register.
+//
+//*****************************************************************************
+#define NVIC_PRI4_INT19_M       0xFF000000  // Interrupt 19 priority mask
+#define NVIC_PRI4_INT18_M       0x00FF0000  // Interrupt 18 priority mask
+#define NVIC_PRI4_INT17_M       0x0000FF00  // Interrupt 17 priority mask
+#define NVIC_PRI4_INT16_M       0x000000FF  // Interrupt 16 priority mask
+#define NVIC_PRI4_INT19_S       24
+#define NVIC_PRI4_INT18_S       16
+#define NVIC_PRI4_INT17_S       8
+#define NVIC_PRI4_INT16_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI5 register.
+//
+//*****************************************************************************
+#define NVIC_PRI5_INT23_M       0xFF000000  // Interrupt 23 priority mask
+#define NVIC_PRI5_INT22_M       0x00FF0000  // Interrupt 22 priority mask
+#define NVIC_PRI5_INT21_M       0x0000FF00  // Interrupt 21 priority mask
+#define NVIC_PRI5_INT20_M       0x000000FF  // Interrupt 20 priority mask
+#define NVIC_PRI5_INT23_S       24
+#define NVIC_PRI5_INT22_S       16
+#define NVIC_PRI5_INT21_S       8
+#define NVIC_PRI5_INT20_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI6 register.
+//
+//*****************************************************************************
+#define NVIC_PRI6_INT27_M       0xFF000000  // Interrupt 27 priority mask
+#define NVIC_PRI6_INT26_M       0x00FF0000  // Interrupt 26 priority mask
+#define NVIC_PRI6_INT25_M       0x0000FF00  // Interrupt 25 priority mask
+#define NVIC_PRI6_INT24_M       0x000000FF  // Interrupt 24 priority mask
+#define NVIC_PRI6_INT27_S       24
+#define NVIC_PRI6_INT26_S       16
+#define NVIC_PRI6_INT25_S       8
+#define NVIC_PRI6_INT24_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI7 register.
+//
+//*****************************************************************************
+#define NVIC_PRI7_INT31_M       0xFF000000  // Interrupt 31 priority mask
+#define NVIC_PRI7_INT30_M       0x00FF0000  // Interrupt 30 priority mask
+#define NVIC_PRI7_INT29_M       0x0000FF00  // Interrupt 29 priority mask
+#define NVIC_PRI7_INT28_M       0x000000FF  // Interrupt 28 priority mask
+#define NVIC_PRI7_INT31_S       24
+#define NVIC_PRI7_INT30_S       16
+#define NVIC_PRI7_INT29_S       8
+#define NVIC_PRI7_INT28_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI8 register.
+//
+//*****************************************************************************
+#define NVIC_PRI8_INT35_M       0xFF000000  // Interrupt 35 priority mask
+#define NVIC_PRI8_INT34_M       0x00FF0000  // Interrupt 34 priority mask
+#define NVIC_PRI8_INT33_M       0x0000FF00  // Interrupt 33 priority mask
+#define NVIC_PRI8_INT32_M       0x000000FF  // Interrupt 32 priority mask
+#define NVIC_PRI8_INT35_S       24
+#define NVIC_PRI8_INT34_S       16
+#define NVIC_PRI8_INT33_S       8
+#define NVIC_PRI8_INT32_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI9 register.
+//
+//*****************************************************************************
+#define NVIC_PRI9_INT39_M       0xFF000000  // Interrupt 39 priority mask
+#define NVIC_PRI9_INT38_M       0x00FF0000  // Interrupt 38 priority mask
+#define NVIC_PRI9_INT37_M       0x0000FF00  // Interrupt 37 priority mask
+#define NVIC_PRI9_INT36_M       0x000000FF  // Interrupt 36 priority mask
+#define NVIC_PRI9_INT39_S       24
+#define NVIC_PRI9_INT38_S       16
+#define NVIC_PRI9_INT37_S       8
+#define NVIC_PRI9_INT36_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI10 register.
+//
+//*****************************************************************************
+#define NVIC_PRI10_INT43_M      0xFF000000  // Interrupt 43 priority mask
+#define NVIC_PRI10_INT42_M      0x00FF0000  // Interrupt 42 priority mask
+#define NVIC_PRI10_INT41_M      0x0000FF00  // Interrupt 41 priority mask
+#define NVIC_PRI10_INT40_M      0x000000FF  // Interrupt 40 priority mask
+#define NVIC_PRI10_INT43_S      24
+#define NVIC_PRI10_INT42_S      16
+#define NVIC_PRI10_INT41_S      8
+#define NVIC_PRI10_INT40_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPUID register.
+//
+//*****************************************************************************
+#define NVIC_CPUID_IMP_M        0xFF000000  // Implementer
+#define NVIC_CPUID_VAR_M        0x00F00000  // Variant
+#define NVIC_CPUID_PARTNO_M     0x0000FFF0  // Processor part number
+#define NVIC_CPUID_REV_M        0x0000000F  // Revision
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_INT_CTRL_NMI_SET   0x80000000  // Pend a NMI
+#define NVIC_INT_CTRL_PEND_SV   0x10000000  // Pend a PendSV
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000  // Unpend a PendSV
+#define NVIC_INT_CTRL_ISR_PRE   0x00800000  // Debug interrupt handling
+#define NVIC_INT_CTRL_ISR_PEND  0x00400000  // Debug interrupt pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000  // Highest pending exception
+#define NVIC_INT_CTRL_RET_BASE  0x00000800  // Return to base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF  // Current active exception
+#define NVIC_INT_CTRL_VEC_PEN_S 12
+#define NVIC_INT_CTRL_VEC_ACT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_VTABLE register.
+//
+//*****************************************************************************
+#define NVIC_VTABLE_BASE        0x20000000  // Vector table base
+#define NVIC_VTABLE_OFFSET_M    0x1FFFFF00  // Vector table offset
+#define NVIC_VTABLE_OFFSET_S    8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_APINT register.
+//
+//*****************************************************************************
+#define NVIC_APINT_VECTKEY_M    0xFFFF0000  // Vector key mask
+#define NVIC_APINT_VECTKEY      0x05FA0000  // Vector key
+#define NVIC_APINT_ENDIANESS    0x00008000  // Data endianess
+#define NVIC_APINT_PRIGROUP_M   0x00000700  // Priority group
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split
+#define NVIC_APINT_SYSRESETREQ  0x00000004  // System reset request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002  // Clear active NMI/fault info
+#define NVIC_APINT_VECT_RESET   0x00000001  // System reset
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000  // Priority group 7.1 split
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010  // Wakeup on pend
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004  // Deep sleep enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002  // Sleep on ISR exit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100  // Ignore bus fault in NMI/fault
+#define NVIC_CFG_CTRL_DIV0      0x00000010  // Trap on divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008  // Trap on unaligned access
+#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004  // Allow deep interrupt trigger
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002  // Allow main interrupt trigger
+#define NVIC_CFG_CTRL_BASE_THR  0x00000001  // Thread state control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI1_RES_M     0xFF000000  // Priority of reserved handler
+#define NVIC_SYS_PRI1_USAGE_M   0x00FF0000  // Priority of usage fault handler
+#define NVIC_SYS_PRI1_BUS_M     0x0000FF00  // Priority of bus fault handler
+#define NVIC_SYS_PRI1_MEM_M     0x000000FF  // Priority of mem manage handler
+#define NVIC_SYS_PRI1_USAGE_S   16
+#define NVIC_SYS_PRI1_BUS_S     8
+#define NVIC_SYS_PRI1_MEM_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI2_SVC_M     0xFF000000  // Priority of SVCall handler
+#define NVIC_SYS_PRI2_RES_M     0x00FFFFFF  // Priority of reserved handlers
+#define NVIC_SYS_PRI2_SVC_S     24
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI3_TICK_M    0xFF000000  // Priority of Sys Tick handler
+#define NVIC_SYS_PRI3_PENDSV_M  0x00FF0000  // Priority of PendSV handler
+#define NVIC_SYS_PRI3_RES_M     0x0000FF00  // Priority of reserved handler
+#define NVIC_SYS_PRI3_DEBUG_M   0x000000FF  // Priority of debug handler
+#define NVIC_SYS_PRI3_TICK_S    24
+#define NVIC_SYS_PRI3_PENDSV_S  16
+#define NVIC_SYS_PRI3_DEBUG_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
+// register.
+//
+//*****************************************************************************
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000  // Usage fault enable
+#define NVIC_SYS_HND_CTRL_BUS   0x00020000  // Bus fault enable
+#define NVIC_SYS_HND_CTRL_MEM   0x00010000  // Mem manage fault enable
+#define NVIC_SYS_HND_CTRL_SVC   0x00008000  // SVCall is pended
+#define NVIC_SYS_HND_CTRL_BUSP  0x00004000  // Bus fault is pended
+#define NVIC_SYS_HND_CTRL_TICK  0x00000800  // Sys tick is active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400  // PendSV is active
+#define NVIC_SYS_HND_CTRL_MON   0x00000100  // Monitor is active
+#define NVIC_SYS_HND_CTRL_SVCA  0x00000080  // SVCall is active
+#define NVIC_SYS_HND_CTRL_USGA  0x00000008  // Usage fault is active
+#define NVIC_SYS_HND_CTRL_BUSA  0x00000002  // Bus fault is active
+#define NVIC_SYS_HND_CTRL_MEMA  0x00000001  // Mem manage is active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_STAT_DIV0    0x02000000  // Divide by zero fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000  // Unaligned access fault
+#define NVIC_FAULT_STAT_NOCP    0x00080000  // No coprocessor fault
+#define NVIC_FAULT_STAT_INVPC   0x00040000  // Invalid PC fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000  // Invalid state fault
+#define NVIC_FAULT_STAT_UNDEF   0x00010000  // Undefined instruction fault
+#define NVIC_FAULT_STAT_BFARV   0x00008000  // BFAR is valid
+#define NVIC_FAULT_STAT_BSTKE   0x00001000  // Stack bus fault
+#define NVIC_FAULT_STAT_BUSTKE  0x00000800  // Unstack bus fault
+#define NVIC_FAULT_STAT_IMPRE   0x00000400  // Imprecise data bus error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200  // Precise data bus error
+#define NVIC_FAULT_STAT_IBUS    0x00000100  // Instruction bus fault
+#define NVIC_FAULT_STAT_MMARV   0x00000080  // MMAR is valid
+#define NVIC_FAULT_STAT_MSTKE   0x00000010  // Stack access violation
+#define NVIC_FAULT_STAT_MUSTKE  0x00000008  // Unstack access violation
+#define NVIC_FAULT_STAT_DERR    0x00000002  // Data access violation
+#define NVIC_FAULT_STAT_IERR    0x00000001  // Instruction access violation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_HFAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_HFAULT_STAT_DBG    0x80000000  // Debug event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000  // Cannot execute fault handler
+#define NVIC_HFAULT_STAT_VECT   0x00000002  // Vector table read fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DEBUG_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_DEBUG_STAT_EXTRNL  0x00000010  // EDBGRQ asserted
+#define NVIC_DEBUG_STAT_VCATCH  0x00000008  // Vector catch
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004  // DWT match
+#define NVIC_DEBUG_STAT_BKPT    0x00000002  // Breakpoint instruction
+#define NVIC_DEBUG_STAT_HALTED  0x00000001  // Halt request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MM_ADDR register.
+//
+//*****************************************************************************
+#define NVIC_MM_ADDR_M          0xFFFFFFFF  // Data fault address
+#define NVIC_MM_ADDR_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_ADDR
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_ADDR_M       0xFFFFFFFF  // Data bus fault address
+#define NVIC_FAULT_ADDR_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000  // Number of I regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00  // Number of D regions
+#define NVIC_MPU_TYPE_SEPARATE  0x00000001  // Separate or unified MPU
+#define NVIC_MPU_TYPE_IREGION_S 16
+#define NVIC_MPU_TYPE_DREGION_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004  // MPU default region in priv mode
+#define NVIC_MPU_CTRL_HFNMIENA  0x00000002  // MPU enabled during faults
+#define NVIC_MPU_CTRL_ENABLE    0x00000001  // MPU enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_NUMBER
+// register.
+//
+//*****************************************************************************
+#define NVIC_MPU_NUMBER_M       0x000000FF  // MPU region to access
+#define NVIC_MPU_NUMBER_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE_ADDR_M    0xFFFFFFE0  // Base address mask
+#define NVIC_MPU_BASE_VALID     0x00000010  // Region number valid
+#define NVIC_MPU_BASE_REGION_M  0x0000000F  // Region number
+#define NVIC_MPU_BASE_ADDR_S    8
+#define NVIC_MPU_BASE_REGION_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR_M         0xFFFF0000  // Attributes
+#define NVIC_MPU_ATTR_AP_NO_NO  0x00000000  // prv: no access, usr: no access
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000  // Bufferable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000  // Cacheable
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000  // Shareable
+#define NVIC_MPU_ATTR_TEX_M     0x00380000  // Type extension mask
+#define NVIC_MPU_ATTR_AP_RW_NO  0x01000000  // prv: rw, usr: none
+#define NVIC_MPU_ATTR_AP_RW_RO  0x02000000  // prv: rw, usr: read-only
+#define NVIC_MPU_ATTR_AP_RW_RW  0x03000000  // prv: rw, usr: rw
+#define NVIC_MPU_ATTR_AP_RO_NO  0x05000000  // prv: ro, usr: none
+#define NVIC_MPU_ATTR_AP_RO_RO  0x06000000  // prv: ro, usr: ro
+#define NVIC_MPU_ATTR_AP_M      0x07000000  // Access permissions mask
+#define NVIC_MPU_ATTR_XN        0x10000000  // Execute disable
+#define NVIC_MPU_ATTR_SRD_M     0x0000FF00  // Sub-region disable mask
+#define NVIC_MPU_ATTR_SRD_0     0x00000100  // Sub-region 0 disable
+#define NVIC_MPU_ATTR_SRD_1     0x00000200  // Sub-region 1 disable
+#define NVIC_MPU_ATTR_SRD_2     0x00000400  // Sub-region 2 disable
+#define NVIC_MPU_ATTR_SRD_3     0x00000800  // Sub-region 3 disable
+#define NVIC_MPU_ATTR_SRD_4     0x00001000  // Sub-region 4 disable
+#define NVIC_MPU_ATTR_SRD_5     0x00002000  // Sub-region 5 disable
+#define NVIC_MPU_ATTR_SRD_6     0x00004000  // Sub-region 6 disable
+#define NVIC_MPU_ATTR_SRD_7     0x00008000  // Sub-region 7 disable
+#define NVIC_MPU_ATTR_SIZE_M    0x0000003E  // Region size mask
+#define NVIC_MPU_ATTR_SIZE_32B  0x00000008  // Region size 32 bytes
+#define NVIC_MPU_ATTR_SIZE_64B  0x0000000A  // Region size 64 bytes
+#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C  // Region size 128 bytes
+#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E  // Region size 256 bytes
+#define NVIC_MPU_ATTR_SIZE_512B 0x00000010  // Region size 512 bytes
+#define NVIC_MPU_ATTR_SIZE_1K   0x00000012  // Region size 1 Kbytes
+#define NVIC_MPU_ATTR_SIZE_2K   0x00000014  // Region size 2 Kbytes
+#define NVIC_MPU_ATTR_SIZE_4K   0x00000016  // Region size 4 Kbytes
+#define NVIC_MPU_ATTR_SIZE_8K   0x00000018  // Region size 8 Kbytes
+#define NVIC_MPU_ATTR_SIZE_16K  0x0000001A  // Region size 16 Kbytes
+#define NVIC_MPU_ATTR_SIZE_32K  0x0000001C  // Region size 32 Kbytes
+#define NVIC_MPU_ATTR_SIZE_64K  0x0000001E  // Region size 64 Kbytes
+#define NVIC_MPU_ATTR_SIZE_128K 0x00000020  // Region size 128 Kbytes
+#define NVIC_MPU_ATTR_SIZE_256K 0x00000022  // Region size 256 Kbytes
+#define NVIC_MPU_ATTR_SIZE_512K 0x00000024  // Region size 512 Kbytes
+#define NVIC_MPU_ATTR_SIZE_1M   0x00000026  // Region size 1 Mbytes
+#define NVIC_MPU_ATTR_SIZE_2M   0x00000028  // Region size 2 Mbytes
+#define NVIC_MPU_ATTR_SIZE_4M   0x0000002A  // Region size 4 Mbytes
+#define NVIC_MPU_ATTR_SIZE_8M   0x0000002C  // Region size 8 Mbytes
+#define NVIC_MPU_ATTR_SIZE_16M  0x0000002E  // Region size 16 Mbytes
+#define NVIC_MPU_ATTR_SIZE_32M  0x00000030  // Region size 32 Mbytes
+#define NVIC_MPU_ATTR_SIZE_64M  0x00000032  // Region size 64 Mbytes
+#define NVIC_MPU_ATTR_SIZE_128M 0x00000034  // Region size 128 Mbytes
+#define NVIC_MPU_ATTR_SIZE_256M 0x00000036  // Region size 256 Mbytes
+#define NVIC_MPU_ATTR_SIZE_512M 0x00000038  // Region size 512 Mbytes
+#define NVIC_MPU_ATTR_SIZE_1G   0x0000003A  // Region size 1 Gbytes
+#define NVIC_MPU_ATTR_SIZE_2G   0x0000003C  // Region size 2 Gbytes
+#define NVIC_MPU_ATTR_SIZE_4G   0x0000003E  // Region size 4 Gbytes
+#define NVIC_MPU_ATTR_ENABLE    0x00000001  // Region enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_DBG_CTRL_DBGKEY_M  0xFFFF0000  // Debug key mask
+#define NVIC_DBG_CTRL_DBGKEY    0xA05F0000  // Debug key
+#define NVIC_DBG_CTRL_MON_PEND  0x00008000  // Pend the monitor
+#define NVIC_DBG_CTRL_MON_REQ   0x00004000  // Monitor request
+#define NVIC_DBG_CTRL_MON_EN    0x00002000  // Debug monitor enable
+#define NVIC_DBG_CTRL_MONSTEP   0x00001000  // Monitor step the core
+#define NVIC_DBG_CTRL_S_SLEEP   0x00000400  // Core is sleeping
+#define NVIC_DBG_CTRL_S_HALT    0x00000200  // Core status on halt
+#define NVIC_DBG_CTRL_S_REGRDY  0x00000100  // Register read/write available
+#define NVIC_DBG_CTRL_S_LOCKUP  0x00000080  // Core is locked up
+#define NVIC_DBG_CTRL_C_RESET   0x00000010  // Reset the core
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008  // Mask interrupts when stepping
+#define NVIC_DBG_CTRL_C_STEP    0x00000004  // Step the core
+#define NVIC_DBG_CTRL_C_HALT    0x00000002  // Halt the core
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001  // Enable debug
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_XFER register.
+//
+//*****************************************************************************
+#define NVIC_DBG_XFER_REG_WNR   0x00010000  // Write or not read
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F  // Register
+#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask
+#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP
+#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP
+#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15
+#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14
+#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13
+#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12
+#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11
+#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10
+#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9
+#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8
+#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7
+#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6
+#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5
+#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4
+#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3
+#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2
+#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1
+#define NVIC_DBG_XFER_REG_R0    0x00000000  // Register R0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_DATA register.
+//
+//*****************************************************************************
+#define NVIC_DBG_DATA_M         0xFFFFFFFF  // Data temporary cache
+#define NVIC_DBG_DATA_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_INT register.
+//
+//*****************************************************************************
+#define NVIC_DBG_INT_HARDERR    0x00000400  // Debug trap on hard fault
+#define NVIC_DBG_INT_INTERR     0x00000200  // Debug trap on interrupt errors
+#define NVIC_DBG_INT_BUSERR     0x00000100  // Debug trap on bus error
+#define NVIC_DBG_INT_STATERR    0x00000080  // Debug trap on usage fault state
+#define NVIC_DBG_INT_CHKERR     0x00000040  // Debug trap on usage fault check
+#define NVIC_DBG_INT_NOCPERR    0x00000020  // Debug trap on coprocessor error
+#define NVIC_DBG_INT_MMERR      0x00000010  // Debug trap on mem manage fault
+#define NVIC_DBG_INT_RESET      0x00000008  // Core reset status
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004  // Clear pending core reset
+#define NVIC_DBG_INT_RSTPENDING 0x00000002  // Core reset is pending
+#define NVIC_DBG_INT_RSTVCATCH  0x00000001  // Reset vector catch
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SW_TRIG register.
+//
+//*****************************************************************************
+#define NVIC_SW_TRIG_INTID_M    0x000003FF  // Interrupt to trigger
+#define NVIC_SW_TRIG_INTID_S    0
+
+#endif // __HW_NVIC_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_pwm.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_pwm.h
new file mode 100644
index 0000000..59d93d1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_pwm.h
@@ -0,0 +1,677 @@
+//*****************************************************************************
+//
+// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HW_PWM_H__
+#define __HW_PWM_H__
+
+//*****************************************************************************
+//
+// The following are defines for the PWM Module Register offsets.
+//
+//*****************************************************************************
+#define PWM_O_CTL               0x00000000  // PWM Master Control register
+#define PWM_O_SYNC              0x00000004  // PWM Time Base Sync register
+#define PWM_O_ENABLE            0x00000008  // PWM Output Enable register
+#define PWM_O_INVERT            0x0000000C  // PWM Output Inversion register
+#define PWM_O_FAULT             0x00000010  // PWM Output Fault register
+#define PWM_O_INTEN             0x00000014  // PWM Interrupt Enable register
+#define PWM_O_RIS               0x00000018  // PWM Interrupt Raw Status reg.
+#define PWM_O_ISC               0x0000001C  // PWM Interrupt Status register
+#define PWM_O_STATUS            0x00000020  // PWM Status register
+#define PWM_O_FAULTVAL          0x00000024  // PWM Fault Condition Value
+#define PWM_O_0_CTL             0x00000040  // PWM0 Control
+#define PWM_O_0_INTEN           0x00000044  // PWM0 Interrupt and Trigger
+                                            // Enable
+#define PWM_O_0_RIS             0x00000048  // PWM0 Raw Interrupt Status
+#define PWM_O_0_ISC             0x0000004C  // PWM0 Interrupt Status and Clear
+#define PWM_O_0_LOAD            0x00000050  // PWM0 Load
+#define PWM_O_0_COUNT           0x00000054  // PWM0 Counter
+#define PWM_O_0_CMPA            0x00000058  // PWM0 Compare A
+#define PWM_O_0_CMPB            0x0000005C  // PWM0 Compare B
+#define PWM_O_0_GENA            0x00000060  // PWM0 Generator A Control
+#define PWM_O_0_GENB            0x00000064  // PWM0 Generator B Control
+#define PWM_O_0_DBCTL           0x00000068  // PWM0 Dead-Band Control
+#define PWM_O_0_DBRISE          0x0000006C  // PWM0 Dead-Band Rising-Edge Delay
+#define PWM_O_0_DBFALL          0x00000070  // PWM0 Dead-Band
+                                            // Falling-Edge-Delay
+#define PWM_O_0_FLTSRC0         0x00000074  // PWM0 Fault Source 0
+#define PWM_O_0_MINFLTPER       0x0000007C  // PWM0 Minimum Fault Period
+#define PWM_O_1_CTL             0x00000080  // PWM1 Control
+#define PWM_O_1_INTEN           0x00000084  // PWM1 Interrupt Enable
+#define PWM_O_1_RIS             0x00000088  // PWM1 Raw Interrupt Status
+#define PWM_O_1_ISC             0x0000008C  // PWM1 Interrupt Status and Clear
+#define PWM_O_1_LOAD            0x00000090  // PWM1 Load
+#define PWM_O_1_COUNT           0x00000094  // PWM1 Counter
+#define PWM_O_1_CMPA            0x00000098  // PWM1 Compare A
+#define PWM_O_1_CMPB            0x0000009C  // PWM1 Compare B
+#define PWM_O_1_GENA            0x000000A0  // PWM1 Generator A Control
+#define PWM_O_1_GENB            0x000000A4  // PWM1 Generator B Control
+#define PWM_O_1_DBCTL           0x000000A8  // PWM1 Dead-Band Control
+#define PWM_O_1_DBRISE          0x000000AC  // PWM1 Dead-Band Rising-Edge Delay
+#define PWM_O_1_DBFALL          0x000000B0  // PWM1 Dead-Band
+                                            // Falling-Edge-Delay
+#define PWM_O_1_FLTSRC0         0x000000B4  // PWM1 Fault Source 0
+#define PWM_O_1_MINFLTPER       0x000000BC  // PWM1 Minimum Fault Period
+#define PWM_O_2_CTL             0x000000C0  // PWM2 Control
+#define PWM_O_2_INTEN           0x000000C4  // PWM2 InterruptEnable
+#define PWM_O_2_RIS             0x000000C8  // PWM2 Raw Interrupt Status
+#define PWM_O_2_ISC             0x000000CC  // PWM2 Interrupt Status and Clear
+#define PWM_O_2_LOAD            0x000000D0  // PWM2 Load
+#define PWM_O_2_COUNT           0x000000D4  // PWM2 Counter
+#define PWM_O_2_CMPA            0x000000D8  // PWM2 Compare A
+#define PWM_O_2_CMPB            0x000000DC  // PWM2 Compare B
+#define PWM_O_2_GENA            0x000000E0  // PWM2 Generator A Control
+#define PWM_O_2_GENB            0x000000E4  // PWM2 Generator B Control
+#define PWM_O_2_DBCTL           0x000000E8  // PWM2 Dead-Band Control
+#define PWM_O_2_DBRISE          0x000000EC  // PWM2 Dead-Band Rising-Edge Delay
+#define PWM_O_2_DBFALL          0x000000F0  // PWM2 Dead-Band
+                                            // Falling-Edge-Delay
+#define PWM_O_2_FLTSRC0         0x000000F4  // PWM2 Fault Source 0
+#define PWM_O_2_MINFLTPER       0x000000FC  // PWM2 Minimum Fault Period
+#define PWM_O_3_CTL             0x00000100  // PWM3 Control
+#define PWM_O_3_INTEN           0x00000104  // PWM3 Interrupt and Trigger
+                                            // Enable
+#define PWM_O_3_RIS             0x00000108  // PWM3 Raw Interrupt Status
+#define PWM_O_3_ISC             0x0000010C  // PWM3 Interrupt Status and Clear
+#define PWM_O_3_LOAD            0x00000110  // PWM3 Load
+#define PWM_O_3_COUNT           0x00000114  // PWM3 Counter
+#define PWM_O_3_CMPA            0x00000118  // PWM3 Compare A
+#define PWM_O_3_CMPB            0x0000011C  // PWM3 Compare B
+#define PWM_O_3_GENA            0x00000120  // PWM3 Generator A Control
+#define PWM_O_3_GENB            0x00000124  // PWM3 Generator B Control
+#define PWM_O_3_DBCTL           0x00000128  // PWM3 Dead-Band Control
+#define PWM_O_3_DBRISE          0x0000012C  // PWM3 Dead-Band Rising-Edge Delay
+#define PWM_O_3_DBFALL          0x00000130  // PWM3 Dead-Band
+                                            // Falling-Edge-Delay
+#define PWM_O_3_FLTSRC0         0x00000134  // PWM3 Fault Source 0
+#define PWM_O_3_MINFLTPER       0x0000013C  // PWM3 Minimum Fault Period
+#define PWM_O_0_FLTSEN          0x00000800  // PWM0 Fault Pin Logic Sense
+#define PWM_O_0_FLTSTAT0        0x00000804  // PWM0 Fault Status 0
+#define PWM_O_1_FLTSEN          0x00000880  // PWM1 Fault Pin Logic Sense
+#define PWM_O_1_FLTSTAT0        0x00000884  // PWM1 Fault Status 0
+#define PWM_O_2_FLTSEN          0x00000900  // PWM2 Fault Pin Logic Sense
+#define PWM_O_2_FLTSTAT0        0x00000904  // PWM2 Fault Status 0
+#define PWM_O_3_FLTSEN          0x00000980  // PWM3 Fault Pin Logic Sense
+#define PWM_O_3_FLTSTAT0        0x00000984  // PWM3 Fault Status 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM Master Control
+// register.
+//
+//*****************************************************************************
+#define PWM_CTL_GLOBALSYNC3     0x00000008  // Update PWM Generator 3.
+#define PWM_CTL_GLOBALSYNC2     0x00000004  // Update PWM Generator 2.
+#define PWM_CTL_GLOBALSYNC1     0x00000002  // Update PWM Generator 1.
+#define PWM_CTL_GLOBALSYNC0     0x00000001  // Update PWM Generator 0.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM Time Base Sync
+// register.
+//
+//*****************************************************************************
+#define PWM_SYNC_SYNC3          0x00000008  // Reset generator 3 counter
+#define PWM_SYNC_SYNC2          0x00000004  // Reset generator 2 counter
+#define PWM_SYNC_SYNC1          0x00000002  // Reset generator 1 counter
+#define PWM_SYNC_SYNC0          0x00000001  // Reset generator 0 counter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM Output Enable
+// register.
+//
+//*****************************************************************************
+#define PWM_ENABLE_PWM7EN       0x00000080  // PWM7 pin enable
+#define PWM_ENABLE_PWM6EN       0x00000040  // PWM6 pin enable
+#define PWM_ENABLE_PWM5EN       0x00000020  // PWM5 pin enable
+#define PWM_ENABLE_PWM4EN       0x00000010  // PWM4 pin enable
+#define PWM_ENABLE_PWM3EN       0x00000008  // PWM3 pin enable
+#define PWM_ENABLE_PWM2EN       0x00000004  // PWM2 pin enable
+#define PWM_ENABLE_PWM1EN       0x00000002  // PWM1 pin enable
+#define PWM_ENABLE_PWM0EN       0x00000001  // PWM0 pin enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM Inversion register.
+//
+//*****************************************************************************
+#define PWM_INVERT_PWM7INV      0x00000080  // PWM7 pin invert
+#define PWM_INVERT_PWM6INV      0x00000040  // PWM6 pin invert
+#define PWM_INVERT_PWM5INV      0x00000020  // PWM5 pin invert
+#define PWM_INVERT_PWM4INV      0x00000010  // PWM4 pin invert
+#define PWM_INVERT_PWM3INV      0x00000008  // PWM3 pin invert
+#define PWM_INVERT_PWM2INV      0x00000004  // PWM2 pin invert
+#define PWM_INVERT_PWM1INV      0x00000002  // PWM1 pin invert
+#define PWM_INVERT_PWM0INV      0x00000001  // PWM0 pin invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM Fault register.
+//
+//*****************************************************************************
+#define PWM_FAULT_FAULT7        0x00000080  // PWM7 pin fault
+#define PWM_FAULT_FAULT6        0x00000040  // PWM6 pin fault
+#define PWM_FAULT_FAULT5        0x00000020  // PWM5 pin fault
+#define PWM_FAULT_FAULT4        0x00000010  // PWM4 pin fault
+#define PWM_FAULT_FAULT3        0x00000008  // PWM3 pin fault
+#define PWM_FAULT_FAULT2        0x00000004  // PWM2 pin fault
+#define PWM_FAULT_FAULT1        0x00000002  // PWM1 pin fault
+#define PWM_FAULT_FAULT0        0x00000001  // PWM0 pin fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM Status register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT3       0x00000008  // Fault3 Interrupt Status.
+#define PWM_STATUS_FAULT2       0x00000004  // Fault2 Interrupt Status.
+#define PWM_STATUS_FAULT1       0x00000002  // Fault1 Interrupt Status.
+#define PWM_STATUS_FAULT0       0x00000001  // Fault0 Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the PWM Generator standard offsets.
+//
+//*****************************************************************************
+#define PWM_O_X_CTL             0x00000000  // Gen Control Reg
+#define PWM_O_X_INTEN           0x00000004  // Gen Int/Trig Enable Reg
+#define PWM_O_X_RIS             0x00000008  // Gen Raw Int Status Reg
+#define PWM_O_X_ISC             0x0000000C  // Gen Int Status Reg
+#define PWM_O_X_LOAD            0x00000010  // Gen Load Reg
+#define PWM_O_X_COUNT           0x00000014  // Gen Counter Reg
+#define PWM_O_X_CMPA            0x00000018  // Gen Compare A Reg
+#define PWM_O_X_CMPB            0x0000001C  // Gen Compare B Reg
+#define PWM_O_X_GENA            0x00000020  // Gen Generator A Ctrl Reg
+#define PWM_O_X_GENB            0x00000024  // Gen Generator B Ctrl Reg
+#define PWM_O_X_DBCTL           0x00000028  // Gen Dead Band Ctrl Reg
+#define PWM_O_X_DBRISE          0x0000002C  // Gen DB Rising Edge Delay Reg
+#define PWM_O_X_DBFALL          0x00000030  // Gen DB Falling Edge Delay Reg
+#define PWM_O_X_FLTSRC0         0x00000034  // Fault pin, comparator condition
+#define PWM_O_X_MINFLTPER       0x0000003C  // Fault minimum period extension
+#define PWM_GEN_0_OFFSET        0x00000040  // PWM0 base
+#define PWM_GEN_1_OFFSET        0x00000080  // PWM1 base
+#define PWM_GEN_2_OFFSET        0x000000C0  // PWM2 base
+#define PWM_GEN_3_OFFSET        0x00000100  // PWM3 base
+
+//*****************************************************************************
+//
+// The following are defines for the PWM_X Control Register bit definitions.
+//
+//*****************************************************************************
+#define PWM_X_CTL_LATCH         0x00040000  // Latch Fault Input.
+#define PWM_X_CTL_MINFLTPER     0x00020000  // Minimum fault period enabled
+#define PWM_X_CTL_FLTSRC        0x00010000  // Fault Condition Source.
+#define PWM_X_CTL_DBFALLUPD_M   0x0000C000  // Specifies the update mode for
+                                            // the PWMnDBFALL register.
+#define PWM_X_CTL_DBFALLUPD_I   0x00000000  // Immediate
+#define PWM_X_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
+#define PWM_X_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
+#define PWM_X_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode.
+#define PWM_X_CTL_DBRISEUPD_I   0x00000000  // Immediate
+#define PWM_X_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
+#define PWM_X_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
+#define PWM_X_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode.
+#define PWM_X_CTL_DBCTLUPD_I    0x00000000  // Immediate
+#define PWM_X_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
+#define PWM_X_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
+#define PWM_X_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode.
+#define PWM_X_CTL_GENBUPD_I     0x00000000  // Immediate
+#define PWM_X_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
+#define PWM_X_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
+#define PWM_X_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode.
+#define PWM_X_CTL_GENAUPD_I     0x00000000  // Immediate
+#define PWM_X_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
+#define PWM_X_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
+#define PWM_X_CTL_CMPBUPD       0x00000020  // Update mode for comp B reg
+#define PWM_X_CTL_CMPAUPD       0x00000010  // Update mode for comp A reg
+#define PWM_X_CTL_LOADUPD       0x00000008  // Update mode for the load reg
+#define PWM_X_CTL_DEBUG         0x00000004  // Debug mode
+#define PWM_X_CTL_MODE          0x00000002  // Counter mode, down or up/down
+#define PWM_X_CTL_ENABLE        0x00000001  // Master enable for gen block
+
+//*****************************************************************************
+//
+// The following are defines for the PWM Generator extended offsets.
+//
+//*****************************************************************************
+#define PWM_O_X_FLTSEN          0x00000000  // Fault logic sense
+#define PWM_O_X_FLTSTAT0        0x00000004  // Pin and comparator status
+#define PWM_EXT_0_OFFSET        0x00000800  // PWM0 extended base
+#define PWM_EXT_1_OFFSET        0x00000880  // PWM1 extended base
+#define PWM_EXT_2_OFFSET        0x00000900  // PWM2 extended base
+#define PWM_EXT_3_OFFSET        0x00000980  // PWM3 extended base
+
+//*****************************************************************************
+//
+// The following are defines for the PWM_X Interrupt/Trigger Enable Register
+// bit definitions.
+//
+//*****************************************************************************
+#define PWM_X_INTEN_TRCMPBD     0x00002000  // Trig if COUNT = CMPA D
+#define PWM_X_INTEN_TRCMPBU     0x00001000  // Trig if COUNT = CMPA U
+#define PWM_X_INTEN_TRCMPAD     0x00000800  // Trig if COUNT = CMPA D
+#define PWM_X_INTEN_TRCMPAU     0x00000400  // Trig if COUNT = CMPA U
+#define PWM_X_INTEN_TRCNTLOAD   0x00000200  // Trig if COUNT = LOAD
+#define PWM_X_INTEN_TRCNTZERO   0x00000100  // Trig if COUNT = 0
+#define PWM_X_INTEN_INTCMPBD    0x00000020  // Int if COUNT = CMPA D
+#define PWM_X_INTEN_INTCMPBU    0x00000010  // Int if COUNT = CMPA U
+#define PWM_X_INTEN_INTCMPAD    0x00000008  // Int if COUNT = CMPA D
+#define PWM_X_INTEN_INTCMPAU    0x00000004  // Int if COUNT = CMPA U
+#define PWM_X_INTEN_INTCNTLOAD  0x00000002  // Int if COUNT = LOAD
+#define PWM_X_INTEN_INTCNTZERO  0x00000001  // Int if COUNT = 0
+
+//*****************************************************************************
+//
+// The following are defines for the PWM_X Raw Interrupt Status Register bit
+// definitions.
+//
+//*****************************************************************************
+#define PWM_X_RIS_INTCMPBD      0x00000020  // PWM_X_COUNT = PWM_X_CMPB D int
+#define PWM_X_RIS_INTCMPBU      0x00000010  // PWM_X_COUNT = PWM_X_CMPB U int
+#define PWM_X_RIS_INTCMPAD      0x00000008  // PWM_X_COUNT = PWM_X_CMPA D int
+#define PWM_X_RIS_INTCMPAU      0x00000004  // PWM_X_COUNT = PWM_X_CMPA U int
+#define PWM_X_RIS_INTCNTLOAD    0x00000002  // PWM_X_COUNT = PWM_X_LOAD int
+#define PWM_X_RIS_INTCNTZERO    0x00000001  // PWM_X_COUNT = 0 int
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INTEN register.
+//
+//*****************************************************************************
+#define PWM_INTEN_INTFAULT3     0x00080000  // Interrupt Fault 3.
+#define PWM_INTEN_INTFAULT2     0x00040000  // Interrupt Fault 2.
+#define PWM_INTEN_INTFAULT1     0x00020000  // Interrupt Fault 1.
+#define PWM_INTEN_INTFAULT      0x00010000  // Fault Interrupt Enable.
+#define PWM_INTEN_INTFAULT0     0x00010000  // Interrupt Fault 0.
+#define PWM_INTEN_INTPWM3       0x00000008  // PWM3 Interrupt Enable.
+#define PWM_INTEN_INTPWM2       0x00000004  // PWM2 Interrupt Enable.
+#define PWM_INTEN_INTPWM1       0x00000002  // PWM1 Interrupt Enable.
+#define PWM_INTEN_INTPWM0       0x00000001  // PWM0 Interrupt Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_RIS register.
+//
+//*****************************************************************************
+#define PWM_RIS_INTFAULT3       0x00080000  // Interrupt Fault PWM 3.
+#define PWM_RIS_INTFAULT2       0x00040000  // Interrupt Fault PWM 2.
+#define PWM_RIS_INTFAULT1       0x00020000  // Interrupt Fault PWM 1.
+#define PWM_RIS_INTFAULT0       0x00010000  // Interrupt Fault PWM 0.
+#define PWM_RIS_INTFAULT        0x00010000  // Fault Interrupt Asserted.
+#define PWM_RIS_INTPWM3         0x00000008  // PWM3 Interrupt Asserted.
+#define PWM_RIS_INTPWM2         0x00000004  // PWM2 Interrupt Asserted.
+#define PWM_RIS_INTPWM1         0x00000002  // PWM1 Interrupt Asserted.
+#define PWM_RIS_INTPWM0         0x00000001  // PWM0 Interrupt Asserted.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ISC register.
+//
+//*****************************************************************************
+#define PWM_ISC_INTFAULT3       0x00080000  // FAULT3 Interrupt Asserted.
+#define PWM_ISC_INTFAULT2       0x00040000  // FAULT2 Interrupt Asserted.
+#define PWM_ISC_INTFAULT1       0x00020000  // FAULT1 Interrupt Asserted.
+#define PWM_ISC_INTFAULT        0x00010000  // Fault Interrupt Asserted.
+#define PWM_ISC_INTFAULT0       0x00010000  // FAULT0 Interrupt Asserted.
+#define PWM_ISC_INTPWM3         0x00000008  // PWM3 Interrupt Status.
+#define PWM_ISC_INTPWM2         0x00000004  // PWM2 Interrupt Status.
+#define PWM_ISC_INTPWM1         0x00000002  // PWM1 Interrupt Status.
+#define PWM_ISC_INTPWM0         0x00000001  // PWM0 Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_ISC register.
+//
+//*****************************************************************************
+#define PWM_X_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt.
+#define PWM_X_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt.
+#define PWM_X_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt.
+#define PWM_X_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt.
+#define PWM_X_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt.
+#define PWM_X_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_LOAD register.
+//
+//*****************************************************************************
+#define PWM_X_LOAD_M            0x0000FFFF  // Counter Load Value.
+#define PWM_X_LOAD_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_COUNT register.
+//
+//*****************************************************************************
+#define PWM_X_COUNT_M           0x0000FFFF  // Counter Value.
+#define PWM_X_COUNT_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPA register.
+//
+//*****************************************************************************
+#define PWM_X_CMPA_M            0x0000FFFF  // Comparator A Value.
+#define PWM_X_CMPA_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPB register.
+//
+//*****************************************************************************
+#define PWM_X_CMPB_M            0x0000FFFF  // Comparator B Value.
+#define PWM_X_CMPB_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENA register.
+//
+//*****************************************************************************
+#define PWM_X_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down.
+#define PWM_X_GENA_ACTCMPBD_NONE \
+                                0x00000000  // Do nothing.
+#define PWM_X_GENA_ACTCMPBD_INV 0x00000400  // Invert the output signal.
+#define PWM_X_GENA_ACTCMPBD_ZERO \
+                                0x00000800  // Set the output signal to 0.
+#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00  // Set the output signal to 1.
+#define PWM_X_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up.
+#define PWM_X_GENA_ACTCMPBU_NONE \
+                                0x00000000  // Do nothing.
+#define PWM_X_GENA_ACTCMPBU_INV 0x00000100  // Invert the output signal.
+#define PWM_X_GENA_ACTCMPBU_ZERO \
+                                0x00000200  // Set the output signal to 0.
+#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300  // Set the output signal to 1.
+#define PWM_X_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down.
+#define PWM_X_GENA_ACTCMPAD_NONE \
+                                0x00000000  // Do nothing.
+#define PWM_X_GENA_ACTCMPAD_INV 0x00000040  // Invert the output signal.
+#define PWM_X_GENA_ACTCMPAD_ZERO \
+                                0x00000080  // Set the output signal to 0.
+#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0  // Set the output signal to 1.
+#define PWM_X_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up.
+#define PWM_X_GENA_ACTCMPAU_NONE \
+                                0x00000000  // Do nothing.
+#define PWM_X_GENA_ACTCMPAU_INV 0x00000010  // Invert the output signal.
+#define PWM_X_GENA_ACTCMPAU_ZERO \
+                                0x00000020  // Set the output signal to 0.
+#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030  // Set the output signal to 1.
+#define PWM_X_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=Load.
+#define PWM_X_GENA_ACTLOAD_NONE 0x00000000  // Do nothing.
+#define PWM_X_GENA_ACTLOAD_INV  0x00000004  // Invert the output signal.
+#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008  // Set the output signal to 0.
+#define PWM_X_GENA_ACTLOAD_ONE  0x0000000C  // Set the output signal to 1.
+#define PWM_X_GENA_ACTZERO_M    0x00000003  // Action for Counter=0.
+#define PWM_X_GENA_ACTZERO_NONE 0x00000000  // Do nothing.
+#define PWM_X_GENA_ACTZERO_INV  0x00000001  // Invert the output signal.
+#define PWM_X_GENA_ACTZERO_ZERO 0x00000002  // Set the output signal to 0.
+#define PWM_X_GENA_ACTZERO_ONE  0x00000003  // Set the output signal to 1.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENB register.
+//
+//*****************************************************************************
+#define PWM_X_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down.
+#define PWM_X_GENB_ACTCMPBD_NONE \
+                                0x00000000  // Do nothing.
+#define PWM_X_GENB_ACTCMPBD_INV 0x00000400  // Invert the output signal.
+#define PWM_X_GENB_ACTCMPBD_ZERO \
+                                0x00000800  // Set the output signal to 0.
+#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00  // Set the output signal to 1.
+#define PWM_X_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up.
+#define PWM_X_GENB_ACTCMPBU_NONE \
+                                0x00000000  // Do nothing.
+#define PWM_X_GENB_ACTCMPBU_INV 0x00000100  // Invert the output signal.
+#define PWM_X_GENB_ACTCMPBU_ZERO \
+                                0x00000200  // Set the output signal to 0.
+#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300  // Set the output signal to 1.
+#define PWM_X_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down.
+#define PWM_X_GENB_ACTCMPAD_NONE \
+                                0x00000000  // Do nothing.
+#define PWM_X_GENB_ACTCMPAD_INV 0x00000040  // Invert the output signal.
+#define PWM_X_GENB_ACTCMPAD_ZERO \
+                                0x00000080  // Set the output signal to 0.
+#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0  // Set the output signal to 1.
+#define PWM_X_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up.
+#define PWM_X_GENB_ACTCMPAU_NONE \
+                                0x00000000  // Do nothing.
+#define PWM_X_GENB_ACTCMPAU_INV 0x00000010  // Invert the output signal.
+#define PWM_X_GENB_ACTCMPAU_ZERO \
+                                0x00000020  // Set the output signal to 0.
+#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030  // Set the output signal to 1.
+#define PWM_X_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=Load.
+#define PWM_X_GENB_ACTLOAD_NONE 0x00000000  // Do nothing.
+#define PWM_X_GENB_ACTLOAD_INV  0x00000004  // Invert the output signal.
+#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008  // Set the output signal to 0.
+#define PWM_X_GENB_ACTLOAD_ONE  0x0000000C  // Set the output signal to 1.
+#define PWM_X_GENB_ACTZERO_M    0x00000003  // Action for Counter=0.
+#define PWM_X_GENB_ACTZERO_NONE 0x00000000  // Do nothing.
+#define PWM_X_GENB_ACTZERO_INV  0x00000001  // Invert the output signal.
+#define PWM_X_GENB_ACTZERO_ZERO 0x00000002  // Set the output signal to 0.
+#define PWM_X_GENB_ACTZERO_ONE  0x00000003  // Set the output signal to 1.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_X_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_X_DBRISE_DELAY_M    0x00000FFF  // Dead-Band Rise Delay.
+#define PWM_X_DBRISE_DELAY_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_X_DBFALL_DELAY_M    0x00000FFF  // Dead-Band Fall Delay.
+#define PWM_X_DBFALL_DELAY_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULTVAL register.
+//
+//*****************************************************************************
+#define PWM_FAULTVAL_PWM7       0x00000080  // PWM7 Fault Value.
+#define PWM_FAULTVAL_PWM6       0x00000040  // PWM6 Fault Value.
+#define PWM_FAULTVAL_PWM5       0x00000020  // PWM5 Fault Value.
+#define PWM_FAULTVAL_PWM4       0x00000010  // PWM4 Fault Value.
+#define PWM_FAULTVAL_PWM3       0x00000008  // PWM3 Fault Value.
+#define PWM_FAULTVAL_PWM2       0x00000004  // PWM2 Fault Value.
+#define PWM_FAULTVAL_PWM1       0x00000002  // PWM1 Fault Value.
+#define PWM_FAULTVAL_PWM0       0x00000001  // PWM0 Fault Value.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_X_MINFLTPER_M       0x0000FFFF  // Minimum Fault Period.
+#define PWM_X_MINFLTPER_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSEN_FAULT3     0x00000008  // Fault3 Sense.
+#define PWM_X_FLTSEN_FAULT2     0x00000004  // Fault2 Sense.
+#define PWM_X_FLTSEN_FAULT1     0x00000002  // Fault1 Sense.
+#define PWM_X_FLTSEN_FAULT0     0x00000001  // Fault0 Sense.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSRC0_FAULT3    0x00000008  // Fault3.
+#define PWM_X_FLTSRC0_FAULT2    0x00000004  // Fault2.
+#define PWM_X_FLTSRC0_FAULT1    0x00000002  // Fault1.
+#define PWM_X_FLTSRC0_FAULT0    0x00000001  // Fault0.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3.
+#define PWM_X_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2.
+#define PWM_X_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1.
+#define PWM_X_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0.
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the PWM Master
+// Control register.
+//
+//*****************************************************************************
+#define PWM_CTL_GLOBAL_SYNC2    0x00000004  // Global sync generator 2
+#define PWM_CTL_GLOBAL_SYNC1    0x00000002  // Global sync generator 1
+#define PWM_CTL_GLOBAL_SYNC0    0x00000001  // Global sync generator 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM Interrupt Register bit
+// definitions.
+//
+//*****************************************************************************
+#define PWM_INT_INTFAULT        0x00010000  // Fault interrupt pending
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the PWM Status
+// register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT        0x00000001  // Fault status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM_X Interrupt Status Register
+// bit definitions.
+//
+//*****************************************************************************
+#define PWM_X_INT_INTCMPBD      0x00000020  // PWM_X_COUNT = PWM_X_CMPB D rcvd
+#define PWM_X_INT_INTCMPBU      0x00000010  // PWM_X_COUNT = PWM_X_CMPB U rcvd
+#define PWM_X_INT_INTCMPAD      0x00000008  // PWM_X_COUNT = PWM_X_CMPA D rcvd
+#define PWM_X_INT_INTCMPAU      0x00000004  // PWM_X_COUNT = PWM_X_CMPA U rcvd
+#define PWM_X_INT_INTCNTLOAD    0x00000002  // PWM_X_COUNT = PWM_X_LOAD rcvd
+#define PWM_X_INT_INTCNTZERO    0x00000001  // PWM_X_COUNT = 0 received
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM_X Generator A/B Control
+// Register bit definitions.
+//
+//*****************************************************************************
+#define PWM_X_GEN_Y_ACTCMPBD    0x00000C00  // Act PWM_X_COUNT = PWM_X_CMPB D
+#define PWM_X_GEN_Y_ACTCMPBU    0x00000300  // Act PWM_X_COUNT = PWM_X_CMPB U
+#define PWM_X_GEN_Y_ACTCMPAD    0x000000C0  // Act PWM_X_COUNT = PWM_X_CMPA D
+#define PWM_X_GEN_Y_ACTCMPAU    0x00000030  // Act PWM_X_COUNT = PWM_X_CMPA U
+#define PWM_X_GEN_Y_ACTLOAD     0x0000000C  // Act PWM_X_COUNT = PWM_X_LOAD
+#define PWM_X_GEN_Y_ACTZERO     0x00000003  // Act PWM_X_COUNT = 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM_X Generator A/B Control
+// Register action definitions.
+//
+//*****************************************************************************
+#define PWM_GEN_ACT_ONE         0x00000003  // Set the output signal to one
+#define PWM_GEN_ACT_ZERO        0x00000002  // Set the output signal to zero
+#define PWM_GEN_ACT_INV         0x00000001  // Invert the output signal
+#define PWM_GEN_ACT_NONE        0x00000000  // Do nothing
+#define PWM_GEN_ACT_B_DN_SHIFT  10          // Shift amount for the B dn action
+#define PWM_GEN_ACT_B_UP_SHIFT  8           // Shift amount for the B up action
+#define PWM_GEN_ACT_A_DN_SHIFT  6           // Shift amount for the A dn action
+#define PWM_GEN_ACT_A_UP_SHIFT  4           // Shift amount for the A up action
+#define PWM_GEN_ACT_LOAD_SHIFT  2           // Shift amount for the load action
+#define PWM_GEN_ACT_ZERO_SHIFT  0           // Shift amount for the zero action
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM_X Dead Band Control
+// Register bit definitions.
+//
+//*****************************************************************************
+#define PWM_DBCTL_ENABLE        0x00000001  // Enable dead band insertion
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM Register reset values.
+//
+//*****************************************************************************
+#define PWM_RV_X_DBCTL          0x00000000  // Control the dead band generator
+#define PWM_RV_STATUS           0x00000000  // Status
+#define PWM_RV_X_ISC            0x00000000  // Interrupt status and clearing
+#define PWM_RV_X_RIS            0x00000000  // Raw interrupt status
+#define PWM_RV_X_CTL            0x00000000  // Master control of the PWM
+                                            // generator block
+#define PWM_RV_SYNC             0x00000000  // Counter synch for PWM generators
+#define PWM_RV_X_DBFALL         0x00000000  // The dead band falling edge delay
+                                            // count
+#define PWM_RV_X_INTEN          0x00000000  // Interrupt and trigger enable
+#define PWM_RV_X_LOAD           0x00000000  // The load value for the counter
+#define PWM_RV_X_GENA           0x00000000  // Controls PWM generator A
+#define PWM_RV_CTL              0x00000000  // Master control of the PWM module
+#define PWM_RV_FAULT            0x00000000  // Fault handling for the PWM
+                                            // output pins
+#define PWM_RV_RIS              0x00000000  // Raw interrupt status
+#define PWM_RV_X_CMPA           0x00000000  // The comparator A value
+#define PWM_RV_INVERT           0x00000000  // Inversion control for PWM output
+                                            // pins
+#define PWM_RV_X_DBRISE         0x00000000  // The dead band rising edge delay
+                                            // count
+#define PWM_RV_ENABLE           0x00000000  // Master enable for the PWM output
+                                            // pins
+#define PWM_RV_X_GENB           0x00000000  // Controls PWM generator B
+#define PWM_RV_X_CMPB           0x00000000  // The comparator B value
+#define PWM_RV_ISC              0x00000000  // Interrupt status and clearing
+#define PWM_RV_INTEN            0x00000000  // Interrupt enable
+#define PWM_RV_X_COUNT          0x00000000  // The current counter value
+
+#endif
+
+#endif // __HW_PWM_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_qei.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_qei.h
new file mode 100644
index 0000000..386fe0b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_qei.h
@@ -0,0 +1,199 @@
+//*****************************************************************************
+//
+// hw_qei.h - Macros used when accessing the QEI hardware.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HW_QEI_H__
+#define __HW_QEI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the QEI register offsets.
+//
+//*****************************************************************************
+#define QEI_O_CTL               0x00000000  // Configuration and control reg.
+#define QEI_O_STAT              0x00000004  // Status register
+#define QEI_O_POS               0x00000008  // Current position register
+#define QEI_O_MAXPOS            0x0000000C  // Maximum position register
+#define QEI_O_LOAD              0x00000010  // Velocity timer load register
+#define QEI_O_TIME              0x00000014  // Velocity timer register
+#define QEI_O_COUNT             0x00000018  // Velocity pulse count register
+#define QEI_O_SPEED             0x0000001C  // Velocity speed register
+#define QEI_O_INTEN             0x00000020  // Interrupt enable register
+#define QEI_O_RIS               0x00000024  // Raw interrupt status register
+#define QEI_O_ISC               0x00000028  // Interrupt status register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_CTL register.
+//
+//*****************************************************************************
+#define QEI_CTL_STALLEN         0x00001000  // Stall enable
+#define QEI_CTL_INVI            0x00000800  // Invert Index input
+#define QEI_CTL_INVB            0x00000400  // Invert PhB input
+#define QEI_CTL_INVA            0x00000200  // Invert PhA input
+#define QEI_CTL_VELDIV_M        0x000001C0  // Velocity predivider mask
+#define QEI_CTL_VELDIV_1        0x00000000  // Predivide by 1
+#define QEI_CTL_VELDIV_2        0x00000040  // Predivide by 2
+#define QEI_CTL_VELDIV_4        0x00000080  // Predivide by 4
+#define QEI_CTL_VELDIV_8        0x000000C0  // Predivide by 8
+#define QEI_CTL_VELDIV_16       0x00000100  // Predivide by 16
+#define QEI_CTL_VELDIV_32       0x00000140  // Predivide by 32
+#define QEI_CTL_VELDIV_64       0x00000180  // Predivide by 64
+#define QEI_CTL_VELDIV_128      0x000001C0  // Predivide by 128
+#define QEI_CTL_VELEN           0x00000020  // Velocity enable
+#define QEI_CTL_RESMODE         0x00000010  // Position counter reset mode
+#define QEI_CTL_CAPMODE         0x00000008  // Edge capture mode
+#define QEI_CTL_SIGMODE         0x00000004  // Encoder signaling mode
+#define QEI_CTL_SWAP            0x00000002  // Swap input signals
+#define QEI_CTL_ENABLE          0x00000001  // QEI enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_STAT register.
+//
+//*****************************************************************************
+#define QEI_STAT_DIRECTION      0x00000002  // Direction of rotation
+#define QEI_STAT_ERROR          0x00000001  // Signalling error detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_POS register.
+//
+//*****************************************************************************
+#define QEI_POS_M               0xFFFFFFFF  // Current encoder position
+#define QEI_POS_S               0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_MAXPOS register.
+//
+//*****************************************************************************
+#define QEI_MAXPOS_M            0xFFFFFFFF  // Maximum encoder position
+#define QEI_MAXPOS_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_LOAD register.
+//
+//*****************************************************************************
+#define QEI_LOAD_M              0xFFFFFFFF  // Velocity timer load value
+#define QEI_LOAD_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_TIME register.
+//
+//*****************************************************************************
+#define QEI_TIME_M              0xFFFFFFFF  // Velocity timer current value
+#define QEI_TIME_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_COUNT register.
+//
+//*****************************************************************************
+#define QEI_COUNT_M             0xFFFFFFFF  // Encoder running pulse count
+#define QEI_COUNT_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_SPEED register.
+//
+//*****************************************************************************
+#define QEI_SPEED_M             0xFFFFFFFF  // Encoder pulse count
+#define QEI_SPEED_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_INTEN register.
+//
+//*****************************************************************************
+#define QEI_INTEN_ERROR         0x00000008  // Phase error detected
+#define QEI_INTEN_DIR           0x00000004  // Direction change
+#define QEI_INTEN_TIMER         0x00000002  // Velocity timer expired
+#define QEI_INTEN_INDEX         0x00000001  // Index pulse detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_RIS register.
+//
+//*****************************************************************************
+#define QEI_RIS_ERROR           0x00000008  // Phase error detected
+#define QEI_RIS_DIR             0x00000004  // Direction change
+#define QEI_RIS_TIMER           0x00000002  // Velocity timer expired
+#define QEI_RIS_INDEX           0x00000001  // Index pulse detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_ISC register.
+//
+//*****************************************************************************
+#define QEI_ISC_ERROR           0x00000008  // Phase Error Interrupt.
+#define QEI_ISC_DIR             0x00000004  // Direction Change Interrupt.
+#define QEI_ISC_TIMER           0x00000002  // Velocity Timer Expired
+                                            // Interrupt.
+#define QEI_ISC_INDEX           0x00000001  // Index Pulse Interrupt.
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the QEI_ISC
+// register.
+//
+//*****************************************************************************
+#define QEI_INT_ERROR           0x00000008  // Phase error detected
+#define QEI_INT_DIR             0x00000004  // Direction change
+#define QEI_INT_TIMER           0x00000002  // Velocity timer expired
+#define QEI_INT_INDEX           0x00000001  // Index pulse detected
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values for the QEI
+// registers.
+//
+//*****************************************************************************
+#define QEI_RV_POS              0x00000000  // Current position register
+#define QEI_RV_LOAD             0x00000000  // Velocity timer load register
+#define QEI_RV_CTL              0x00000000  // Configuration and control reg.
+#define QEI_RV_RIS              0x00000000  // Raw interrupt status register
+#define QEI_RV_ISC              0x00000000  // Interrupt status register
+#define QEI_RV_SPEED            0x00000000  // Velocity speed register
+#define QEI_RV_INTEN            0x00000000  // Interrupt enable register
+#define QEI_RV_STAT             0x00000000  // Status register
+#define QEI_RV_COUNT            0x00000000  // Velocity pulse count register
+#define QEI_RV_MAXPOS           0x00000000  // Maximum position register
+#define QEI_RV_TIME             0x00000000  // Velocity timer register
+
+#endif
+
+#endif // __HW_QEI_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_ssi.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_ssi.h
new file mode 100644
index 0000000..f10fc55
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_ssi.h
@@ -0,0 +1,220 @@
+//*****************************************************************************
+//
+// hw_ssi.h - Macros used when accessing the SSI hardware.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HW_SSI_H__
+#define __HW_SSI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the SSI register offsets.
+//
+//*****************************************************************************
+#define SSI_O_CR0               0x00000000  // Control register 0
+#define SSI_O_CR1               0x00000004  // Control register 1
+#define SSI_O_DR                0x00000008  // Data register
+#define SSI_O_SR                0x0000000C  // Status register
+#define SSI_O_CPSR              0x00000010  // Clock prescale register
+#define SSI_O_IM                0x00000014  // Int mask set and clear register
+#define SSI_O_RIS               0x00000018  // Raw interrupt register
+#define SSI_O_MIS               0x0000001C  // Masked interrupt register
+#define SSI_O_ICR               0x00000020  // Interrupt clear register
+#define SSI_O_DMACTL            0x00000024  // SSI DMA Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI Control register 0.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR_M           0x0000FF00  // SSI Serial Clock Rate.
+#define SSI_CR0_SPH             0x00000080  // SSPCLKOUT phase
+#define SSI_CR0_SPO             0x00000040  // SSPCLKOUT polarity
+#define SSI_CR0_FRF_M           0x00000030  // Frame format mask
+#define SSI_CR0_FRF_MOTO        0x00000000  // Motorola SPI frame format
+#define SSI_CR0_FRF_TI          0x00000010  // TI sync serial frame format
+#define SSI_CR0_FRF_NMW         0x00000020  // National Microwire frame format
+#define SSI_CR0_DSS_M           0x0000000F  // SSI Data Size Select.
+#define SSI_CR0_DSS_4           0x00000003  // 4 bit data
+#define SSI_CR0_DSS_5           0x00000004  // 5 bit data
+#define SSI_CR0_DSS_6           0x00000005  // 6 bit data
+#define SSI_CR0_DSS_7           0x00000006  // 7 bit data
+#define SSI_CR0_DSS_8           0x00000007  // 8 bit data
+#define SSI_CR0_DSS_9           0x00000008  // 9 bit data
+#define SSI_CR0_DSS_10          0x00000009  // 10 bit data
+#define SSI_CR0_DSS_11          0x0000000A  // 11 bit data
+#define SSI_CR0_DSS_12          0x0000000B  // 12 bit data
+#define SSI_CR0_DSS_13          0x0000000C  // 13 bit data
+#define SSI_CR0_DSS_14          0x0000000D  // 14 bit data
+#define SSI_CR0_DSS_15          0x0000000E  // 15 bit data
+#define SSI_CR0_DSS_16          0x0000000F  // 16 bit data
+#define SSI_CR0_SCR_S           8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI Control register 1.
+//
+//*****************************************************************************
+#define SSI_CR1_SOD             0x00000008  // Slave mode output disable
+#define SSI_CR1_MS              0x00000004  // Master or slave mode select
+#define SSI_CR1_SSE             0x00000002  // Sync serial port enable
+#define SSI_CR1_LBM             0x00000001  // Loopback mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI Status register.
+//
+//*****************************************************************************
+#define SSI_SR_BSY              0x00000010  // SSI busy
+#define SSI_SR_RFF              0x00000008  // RX FIFO full
+#define SSI_SR_RNE              0x00000004  // RX FIFO not empty
+#define SSI_SR_TNF              0x00000002  // TX FIFO not full
+#define SSI_SR_TFE              0x00000001  // TX FIFO empty
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI clock prescale
+// register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_M      0x000000FF  // SSI Clock Prescale Divisor.
+#define SSI_CPSR_CPSDVSR_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DR register.
+//
+//*****************************************************************************
+#define SSI_DR_DATA_M           0x0000FFFF  // SSI Receive/Transmit Data.
+#define SSI_DR_DATA_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_IM register.
+//
+//*****************************************************************************
+#define SSI_IM_TXIM             0x00000008  // SSI Transmit FIFO Interrupt
+                                            // Mask.
+#define SSI_IM_RXIM             0x00000004  // SSI Receive FIFO Interrupt Mask.
+#define SSI_IM_RTIM             0x00000002  // SSI Receive Time-Out Interrupt
+                                            // Mask.
+#define SSI_IM_RORIM            0x00000001  // SSI Receive Overrun Interrupt
+                                            // Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_RIS register.
+//
+//*****************************************************************************
+#define SSI_RIS_TXRIS           0x00000008  // SSI Transmit FIFO Raw Interrupt
+                                            // Status.
+#define SSI_RIS_RXRIS           0x00000004  // SSI Receive FIFO Raw Interrupt
+                                            // Status.
+#define SSI_RIS_RTRIS           0x00000002  // SSI Receive Time-Out Raw
+                                            // Interrupt Status.
+#define SSI_RIS_RORRIS          0x00000001  // SSI Receive Overrun Raw
+                                            // Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_MIS register.
+//
+//*****************************************************************************
+#define SSI_MIS_TXMIS           0x00000008  // SSI Transmit FIFO Masked
+                                            // Interrupt Status.
+#define SSI_MIS_RXMIS           0x00000004  // SSI Receive FIFO Masked
+                                            // Interrupt Status.
+#define SSI_MIS_RTMIS           0x00000002  // SSI Receive Time-Out Masked
+                                            // Interrupt Status.
+#define SSI_MIS_RORMIS          0x00000001  // SSI Receive Overrun Masked
+                                            // Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_ICR register.
+//
+//*****************************************************************************
+#define SSI_ICR_RTIC            0x00000002  // SSI Receive Time-Out Interrupt
+                                            // Clear.
+#define SSI_ICR_RORIC           0x00000001  // SSI Receive Overrun Interrupt
+                                            // Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DMACTL register.
+//
+//*****************************************************************************
+#define SSI_DMACTL_TXDMAE       0x00000002  // Transmit DMA Enable.
+#define SSI_DMACTL_RXDMAE       0x00000001  // Receive DMA Enable.
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SSI Control
+// register 0.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR             0x0000FF00  // Serial clock rate
+#define SSI_CR0_FRF_MASK        0x00000030  // Frame format mask
+#define SSI_CR0_DSS             0x0000000F  // Data size select
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SSI clock
+// prescale register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_MASK   0x000000FF  // Clock prescale
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the SSI controller's FIFO size.
+//
+//*****************************************************************************
+#define TX_FIFO_SIZE            (8)         // Number of entries in the TX FIFO
+#define RX_FIFO_SIZE            (8)         // Number of entries in the RX FIFO
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the interrupt
+// mask set and clear, raw interrupt, masked interrupt, and interrupt clear
+// registers.
+//
+//*****************************************************************************
+#define SSI_INT_TXFF            0x00000008  // TX FIFO interrupt
+#define SSI_INT_RXFF            0x00000004  // RX FIFO interrupt
+#define SSI_INT_RXTO            0x00000002  // RX timeout interrupt
+#define SSI_INT_RXOR            0x00000001  // RX overrun interrupt
+
+#endif
+
+#endif // __HW_SSI_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_sysctl.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_sysctl.h
new file mode 100644
index 0000000..5d9877b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_sysctl.h
@@ -0,0 +1,1334 @@
+//*****************************************************************************
+//
+// hw_sysctl.h - Macros used when accessing the system control hardware.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HW_SYSCTL_H__
+#define __HW_SYSCTL_H__
+
+//*****************************************************************************
+//
+// The following are defines for the system control register addresses.
+//
+//*****************************************************************************
+#define SYSCTL_DID0             0x400FE000  // Device identification register 0
+#define SYSCTL_DID1             0x400FE004  // Device identification register 1
+#define SYSCTL_DC0              0x400FE008  // Device capabilities register 0
+#define SYSCTL_DC1              0x400FE010  // Device capabilities register 1
+#define SYSCTL_DC2              0x400FE014  // Device capabilities register 2
+#define SYSCTL_DC3              0x400FE018  // Device capabilities register 3
+#define SYSCTL_DC4              0x400FE01C  // Device capabilities register 4
+#define SYSCTL_DC5              0x400FE020  // Device capabilities register 5
+#define SYSCTL_DC6              0x400FE024  // Device capabilities register 6
+#define SYSCTL_DC7              0x400FE028  // Device capabilities register 7
+#define SYSCTL_PBORCTL          0x400FE030  // POR/BOR reset control register
+#define SYSCTL_LDOPCTL          0x400FE034  // LDO power control register
+#define SYSCTL_SRCR0            0x400FE040  // Software reset control reg 0
+#define SYSCTL_SRCR1            0x400FE044  // Software reset control reg 1
+#define SYSCTL_SRCR2            0x400FE048  // Software reset control reg 2
+#define SYSCTL_RIS              0x400FE050  // Raw interrupt status register
+#define SYSCTL_IMC              0x400FE054  // Interrupt mask/control register
+#define SYSCTL_MISC             0x400FE058  // Interrupt status register
+#define SYSCTL_RESC             0x400FE05C  // Reset cause register
+#define SYSCTL_RCC              0x400FE060  // Run-mode clock config register
+#define SYSCTL_PLLCFG           0x400FE064  // PLL configuration register
+#define SYSCTL_GPIOHSCTL        0x400FE06C  // GPIO High Speed Control
+#define SYSCTL_RCC2             0x400FE070  // Run-mode clock config register 2
+#define SYSCTL_MOSCCTL          0x400FE07C  // Main Oscillator Control
+#define SYSCTL_RCGC0            0x400FE100  // Run-mode clock gating register 0
+#define SYSCTL_RCGC1            0x400FE104  // Run-mode clock gating register 1
+#define SYSCTL_RCGC2            0x400FE108  // Run-mode clock gating register 2
+#define SYSCTL_SCGC0            0x400FE110  // Sleep-mode clock gating reg 0
+#define SYSCTL_SCGC1            0x400FE114  // Sleep-mode clock gating reg 1
+#define SYSCTL_SCGC2            0x400FE118  // Sleep-mode clock gating reg 2
+#define SYSCTL_DCGC0            0x400FE120  // Deep Sleep-mode clock gate reg 0
+#define SYSCTL_DCGC1            0x400FE124  // Deep Sleep-mode clock gate reg 1
+#define SYSCTL_DCGC2            0x400FE128  // Deep Sleep-mode clock gate reg 2
+#define SYSCTL_DSLPCLKCFG       0x400FE144  // Deep Sleep-mode clock config reg
+#define SYSCTL_CLKVCLR          0x400FE150  // Clock verifcation clear register
+#define SYSCTL_LDOARST          0x400FE160  // LDO reset control register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_VER_M       0x70000000  // DID0 version mask
+#define SYSCTL_DID0_VER_0       0x00000000  // DID0 version 0
+#define SYSCTL_DID0_VER_1       0x10000000  // DID0 version 1
+#define SYSCTL_DID0_CLASS_M     0x00FF0000  // Device Class
+#define SYSCTL_DID0_CLASS_SANDSTORM \
+                                0x00000000  // Sandstorm-class Device
+#define SYSCTL_DID0_CLASS_FURY  0x00010000  // Fury-class Device
+#define SYSCTL_DID0_CLASS_DUSTDEVIL \
+                                0x00030000  // DustDevil-class Device
+#define SYSCTL_DID0_MAJ_M       0x0000FF00  // Major revision mask
+#define SYSCTL_DID0_MAJ_REVA    0x00000000  // Revision A (initial device)
+#define SYSCTL_DID0_MAJ_REVB    0x00000100  // Revision B (first base layer
+                                            // revision)
+#define SYSCTL_DID0_MAJ_REVC    0x00000200  // Revision C (second base layer
+                                            // revision)
+#define SYSCTL_DID0_MIN_M       0x000000FF  // Minor revision mask
+#define SYSCTL_DID0_MIN_0       0x00000000  // Minor revision 0
+#define SYSCTL_DID0_MIN_1       0x00000001  // Minor revision 1
+#define SYSCTL_DID0_MIN_2       0x00000002  // Minor revision 2
+#define SYSCTL_DID0_MIN_3       0x00000003  // Minor revision 3
+#define SYSCTL_DID0_MIN_4       0x00000004  // Minor revision 4
+#define SYSCTL_DID0_MIN_5       0x00000005  // Minor revision 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_VER_M       0xF0000000  // DID1 Version.
+#define SYSCTL_DID1_VER_0       0x00000000  // Initial DID1 register format
+                                            // definition, indicating a
+                                            // Stellaris LM3Snnn device.
+#define SYSCTL_DID1_VER_1       0x10000000  // First revision of the DID1
+                                            // register format, indicating a
+                                            // Stellaris Fury-class device.
+#define SYSCTL_DID1_FAM_M       0x0F000000  // Family.
+#define SYSCTL_DID1_FAM_STELLARIS \
+                                0x00000000  // Stellaris family of
+                                            // microcontollers, that is, all
+                                            // devices with external part
+                                            // numbers starting with LM3S.
+#define SYSCTL_DID1_PRTNO_M     0x00FF0000  // Part number mask
+#define SYSCTL_DID1_PRTNO_101   0x00010000  // LM3S101
+#define SYSCTL_DID1_PRTNO_102   0x00020000  // LM3S102
+#define SYSCTL_DID1_PRTNO_300   0x00190000  // LM3S300
+#define SYSCTL_DID1_PRTNO_301   0x00110000  // LM3S301
+#define SYSCTL_DID1_PRTNO_308   0x001A0000  // LM3S308
+#define SYSCTL_DID1_PRTNO_310   0x00120000  // LM3S310
+#define SYSCTL_DID1_PRTNO_315   0x00130000  // LM3S315
+#define SYSCTL_DID1_PRTNO_316   0x00140000  // LM3S316
+#define SYSCTL_DID1_PRTNO_317   0x00170000  // LM3S317
+#define SYSCTL_DID1_PRTNO_328   0x00150000  // LM3S328
+#define SYSCTL_DID1_PRTNO_600   0x002A0000  // LM3S600
+#define SYSCTL_DID1_PRTNO_601   0x00210000  // LM3S601
+#define SYSCTL_DID1_PRTNO_608   0x002B0000  // LM3S608
+#define SYSCTL_DID1_PRTNO_610   0x00220000  // LM3S610
+#define SYSCTL_DID1_PRTNO_611   0x00230000  // LM3S611
+#define SYSCTL_DID1_PRTNO_612   0x00240000  // LM3S612
+#define SYSCTL_DID1_PRTNO_613   0x00250000  // LM3S613
+#define SYSCTL_DID1_PRTNO_615   0x00260000  // LM3S615
+#define SYSCTL_DID1_PRTNO_617   0x00280000  // LM3S617
+#define SYSCTL_DID1_PRTNO_618   0x00290000  // LM3S618
+#define SYSCTL_DID1_PRTNO_628   0x00270000  // LM3S628
+#define SYSCTL_DID1_PRTNO_800   0x00380000  // LM3S800
+#define SYSCTL_DID1_PRTNO_801   0x00310000  // LM3S801
+#define SYSCTL_DID1_PRTNO_808   0x00390000  // LM3S808
+#define SYSCTL_DID1_PRTNO_811   0x00320000  // LM3S811
+#define SYSCTL_DID1_PRTNO_812   0x00330000  // LM3S812
+#define SYSCTL_DID1_PRTNO_815   0x00340000  // LM3S815
+#define SYSCTL_DID1_PRTNO_817   0x00360000  // LM3S817
+#define SYSCTL_DID1_PRTNO_818   0x00370000  // LM3S818
+#define SYSCTL_DID1_PRTNO_828   0x00350000  // LM3S828
+#define SYSCTL_DID1_PRTNO_1110  0x00BF0000  // LM3S1110
+#define SYSCTL_DID1_PRTNO_1133  0x00C30000  // LM3S1133
+#define SYSCTL_DID1_PRTNO_1138  0x00C50000  // LM3S1138
+#define SYSCTL_DID1_PRTNO_1150  0x00C10000  // LM3S1150
+#define SYSCTL_DID1_PRTNO_1162  0x00C40000  // LM3S1162
+#define SYSCTL_DID1_PRTNO_1165  0x00C20000  // LM3S1165
+#define SYSCTL_DID1_PRTNO_1332  0x00C60000  // LM3S1332
+#define SYSCTL_DID1_PRTNO_1435  0x00BC0000  // LM3S1435
+#define SYSCTL_DID1_PRTNO_1439  0x00BA0000  // LM3S1439
+#define SYSCTL_DID1_PRTNO_1512  0x00BB0000  // LM3S1512
+#define SYSCTL_DID1_PRTNO_1538  0x00C70000  // LM3S1538
+#define SYSCTL_DID1_PRTNO_1601  0x00DB0000  // LM3S1601
+#define SYSCTL_DID1_PRTNO_1607  0x00060000  // LM3S1607
+#define SYSCTL_DID1_PRTNO_1608  0x00DA0000  // LM3S1608
+#define SYSCTL_DID1_PRTNO_1620  0x00C00000  // LM3S1620
+#define SYSCTL_DID1_PRTNO_1625  0x00030000  // LM3S1625
+#define SYSCTL_DID1_PRTNO_1626  0x00040000  // LM3S1626
+#define SYSCTL_DID1_PRTNO_1627  0x00050000  // LM3S1627
+#define SYSCTL_DID1_PRTNO_1635  0x00B30000  // LM3S1635
+#define SYSCTL_DID1_PRTNO_1637  0x00BD0000  // LM3S1637
+#define SYSCTL_DID1_PRTNO_1751  0x00B90000  // LM3S1751
+#define SYSCTL_DID1_PRTNO_1776  0x00100000  // LM3S1776
+#define SYSCTL_DID1_PRTNO_1850  0x00B40000  // LM3S1850
+#define SYSCTL_DID1_PRTNO_1911  0x00DD0000  // LM3S1911
+#define SYSCTL_DID1_PRTNO_1918  0x00DC0000  // LM3S1918
+#define SYSCTL_DID1_PRTNO_1937  0x00B70000  // LM3S1937
+#define SYSCTL_DID1_PRTNO_1958  0x00BE0000  // LM3S1958
+#define SYSCTL_DID1_PRTNO_1960  0x00B50000  // LM3S1960
+#define SYSCTL_DID1_PRTNO_1968  0x00B80000  // LM3S1968
+#define SYSCTL_DID1_PRTNO_2110  0x00510000  // LM3S2110
+#define SYSCTL_DID1_PRTNO_2139  0x00840000  // LM3S2139
+#define SYSCTL_DID1_PRTNO_2276  0x00390000  // LM3S2276
+#define SYSCTL_DID1_PRTNO_2410  0x00A20000  // LM3S2410
+#define SYSCTL_DID1_PRTNO_2412  0x00590000  // LM3S2412
+#define SYSCTL_DID1_PRTNO_2432  0x00560000  // LM3S2432
+#define SYSCTL_DID1_PRTNO_2533  0x005A0000  // LM3S2533
+#define SYSCTL_DID1_PRTNO_2601  0x00E10000  // LM3S2601
+#define SYSCTL_DID1_PRTNO_2608  0x00E00000  // LM3S2608
+#define SYSCTL_DID1_PRTNO_2616  0x00330000  // LM3S2616
+#define SYSCTL_DID1_PRTNO_2620  0x00570000  // LM3S2620
+#define SYSCTL_DID1_PRTNO_2637  0x00850000  // LM3S2637
+#define SYSCTL_DID1_PRTNO_2651  0x00530000  // LM3S2651
+#define SYSCTL_DID1_PRTNO_2671  0x00800000  // LM3S2671
+#define SYSCTL_DID1_PRTNO_2678  0x00500000  // LM3S2678
+#define SYSCTL_DID1_PRTNO_2730  0x00A40000  // LM3S2730
+#define SYSCTL_DID1_PRTNO_2739  0x00520000  // LM3S2739
+#define SYSCTL_DID1_PRTNO_2776  0x003A0000  // LM3S2776
+#define SYSCTL_DID1_PRTNO_2911  0x00E30000  // LM3S2911
+#define SYSCTL_DID1_PRTNO_2918  0x00E20000  // LM3S2918
+#define SYSCTL_DID1_PRTNO_2939  0x00540000  // LM3S2939
+#define SYSCTL_DID1_PRTNO_2948  0x008F0000  // LM3S2948
+#define SYSCTL_DID1_PRTNO_2950  0x00580000  // LM3S2950
+#define SYSCTL_DID1_PRTNO_2965  0x00550000  // LM3S2965
+#define SYSCTL_DID1_PRTNO_3651  0x00430000  // LM3S3651
+#define SYSCTL_DID1_PRTNO_3739  0x00440000  // LM3S3739
+#define SYSCTL_DID1_PRTNO_3748  0x00490000  // LM3S3748
+#define SYSCTL_DID1_PRTNO_3749  0x00450000  // LM3S3749
+#define SYSCTL_DID1_PRTNO_3759  0x00460000  // LM3S3759
+#define SYSCTL_DID1_PRTNO_3768  0x00480000  // LM3S3768
+#define SYSCTL_DID1_PRTNO_5632  0x00810000  // LM3S5632
+#define SYSCTL_DID1_PRTNO_5652  0x008A0000  // LM3S5652
+#define SYSCTL_DID1_PRTNO_5662  0x00910000  // LM3S5662
+#define SYSCTL_DID1_PRTNO_5732  0x00960000  // LM3S5732
+#define SYSCTL_DID1_PRTNO_5737  0x00970000  // LM3S5737
+#define SYSCTL_DID1_PRTNO_5739  0x00A00000  // LM3S5739
+#define SYSCTL_DID1_PRTNO_5747  0x00990000  // LM3S5747
+#define SYSCTL_DID1_PRTNO_5749  0x00A70000  // LM3S5749
+#define SYSCTL_DID1_PRTNO_5752  0x009A0000  // LM3S5752
+#define SYSCTL_DID1_PRTNO_5757  0x009B0000  // LM3S5757
+#define SYSCTL_DID1_PRTNO_5762  0x009C0000  // LM3S5762
+#define SYSCTL_DID1_PRTNO_5767  0x009D0000  // LM3S5767
+#define SYSCTL_DID1_PRTNO_5768  0x00A90000  // LM3S5768
+#define SYSCTL_DID1_PRTNO_5769  0x00A80000  // LM3S5769
+#define SYSCTL_DID1_PRTNO_6100  0x00A10000  // LM3S6100
+#define SYSCTL_DID1_PRTNO_6110  0x00740000  // LM3S6110
+#define SYSCTL_DID1_PRTNO_6420  0x00A50000  // LM3S6420
+#define SYSCTL_DID1_PRTNO_6422  0x00820000  // LM3S6422
+#define SYSCTL_DID1_PRTNO_6432  0x00750000  // LM3S6432
+#define SYSCTL_DID1_PRTNO_6537  0x00760000  // LM3S6537
+#define SYSCTL_DID1_PRTNO_6610  0x00710000  // LM3S6610
+#define SYSCTL_DID1_PRTNO_6611  0x00E70000  // LM3S6611
+#define SYSCTL_DID1_PRTNO_6618  0x00E60000  // LM3S6618
+#define SYSCTL_DID1_PRTNO_6633  0x00830000  // LM3S6633
+#define SYSCTL_DID1_PRTNO_6637  0x008B0000  // LM3S6637
+#define SYSCTL_DID1_PRTNO_6730  0x00A30000  // LM3S6730
+#define SYSCTL_DID1_PRTNO_6753  0x00770000  // LM3S6753
+#define SYSCTL_DID1_PRTNO_6911  0x00E90000  // LM3S6911
+#define SYSCTL_DID1_PRTNO_6918  0x00E80000  // LM3S6918
+#define SYSCTL_DID1_PRTNO_6938  0x00890000  // LM3S6938
+#define SYSCTL_DID1_PRTNO_6950  0x00720000  // LM3S6950
+#define SYSCTL_DID1_PRTNO_6952  0x00780000  // LM3S6952
+#define SYSCTL_DID1_PRTNO_6965  0x00730000  // LM3S6965
+#define SYSCTL_DID1_PRTNO_8530  0x00640000  // LM3S8530
+#define SYSCTL_DID1_PRTNO_8538  0x008E0000  // LM3S8538
+#define SYSCTL_DID1_PRTNO_8630  0x00610000  // LM3S8630
+#define SYSCTL_DID1_PRTNO_8730  0x00630000  // LM3S8730
+#define SYSCTL_DID1_PRTNO_8733  0x008D0000  // LM3S8733
+#define SYSCTL_DID1_PRTNO_8738  0x00860000  // LM3S8738
+#define SYSCTL_DID1_PRTNO_8930  0x00650000  // LM3S8930
+#define SYSCTL_DID1_PRTNO_8933  0x008C0000  // LM3S8933
+#define SYSCTL_DID1_PRTNO_8938  0x00880000  // LM3S8938
+#define SYSCTL_DID1_PRTNO_8962  0x00A60000  // LM3S8962
+#define SYSCTL_DID1_PRTNO_8970  0x00620000  // LM3S8970
+#define SYSCTL_DID1_PRTNO_8971  0x00D70000  // LM3S8971
+#define SYSCTL_DID1_PINCNT_M    0x0000E000  // Package Pin Count.
+#define SYSCTL_DID1_PINCNT_28   0x00000000  // 28 pin package
+#define SYSCTL_DID1_PINCNT_48   0x00002000  // 48 pin package
+#define SYSCTL_DID1_PINCNT_100  0x00004000  // 100 pin package
+#define SYSCTL_DID1_PINCNT_64   0x00006000  // 64 pin package
+#define SYSCTL_DID1_TEMP_M      0x000000E0  // Temperature range mask
+#define SYSCTL_DID1_TEMP_C      0x00000000  // Commercial temp range (0..70C)
+#define SYSCTL_DID1_TEMP_I      0x00000020  // Industrial temp range (-40..85C)
+#define SYSCTL_DID1_TEMP_E      0x00000040  // Extended temperature range (-40C
+                                            // to 105C)
+#define SYSCTL_DID1_PKG_M       0x00000018  // Package Type.
+#define SYSCTL_DID1_PKG_BGA     0x00000010  // BGA package
+#define SYSCTL_DID1_PKG_28SOIC  0x00000000  // 28-pin SOIC
+#define SYSCTL_DID1_PKG_48QFP   0x00000008  // 48-pin QFP
+#define SYSCTL_DID1_ROHS        0x00000004  // Part is RoHS compliant
+#define SYSCTL_DID1_QUAL_M      0x00000003  // Qualification status mask
+#define SYSCTL_DID1_QUAL_ES     0x00000000  // Engineering sample (unqualified)
+#define SYSCTL_DID1_QUAL_PP     0x00000001  // Pilot production (unqualified)
+#define SYSCTL_DID1_QUAL_FQ     0x00000002  // Fully qualified
+#define SYSCTL_DID1_PRTNO_S     16          // Part number shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC0_SRAMSZ_M     0xFFFF0000  // SRAM size mask
+#define SYSCTL_DC0_SRAMSZ_2KB   0x00070000  // 2 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_4KB   0x000F0000  // 4 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_8KB   0x001F0000  // 8 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_16KB  0x003F0000  // 16 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_32KB  0x007F0000  // 32 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_64KB  0x00FF0000  // 64 KB of SRAM
+#define SYSCTL_DC0_FLASHSZ_M    0x0000FFFF  // Flash size mask
+#define SYSCTL_DC0_FLASHSZ_8KB  0x00000003  // 8 KB of flash
+#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007  // 16 KB of flash
+#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F  // 32 KB of flash
+#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F  // 64 KB of flash
+#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F  // 96 KB of flash
+#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F  // 128 KB of flash
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F  // 256 KB of flash
+#define SYSCTL_DC0_SRAMSZ_S     16          // SRAM size shift
+#define SYSCTL_DC0_FLASHSZ_S    0           // Flash size shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_CAN2         0x04000000  // CAN2 module present
+#define SYSCTL_DC1_CAN1         0x02000000  // CAN1 module present
+#define SYSCTL_DC1_CAN0         0x01000000  // CAN0 module present
+#define SYSCTL_DC1_PWM          0x00100000  // PWM module present
+#define SYSCTL_DC1_ADC          0x00010000  // ADC module present
+#define SYSCTL_DC1_MINSYSDIV_M  0x0000F000  // System Clock Divider.
+#define SYSCTL_DC1_MINSYSDIV_50 0x00003000  // Specifies a 50-MHz CPU clock
+                                            // with a PLL divider of 4.
+#define SYSCTL_DC1_MINSYSDIV_25 0x00007000  // Specifies a 25-MHz clock with a
+                                            // PLL divider of 8.
+#define SYSCTL_DC1_MINSYSDIV_20 0x00009000  // Specifies a 20-MHz clock with a
+                                            // PLL divider of 10.
+#define SYSCTL_DC1_ADCSPD_M     0x00000F00  // ADC speed mask
+#define SYSCTL_DC1_ADCSPD_125K  0x00000000  // 125Ksps ADC
+#define SYSCTL_DC1_ADCSPD_250K  0x00000100  // 250Ksps ADC
+#define SYSCTL_DC1_ADCSPD_500K  0x00000200  // 500Ksps ADC
+#define SYSCTL_DC1_ADCSPD_1M    0x00000300  // 1Msps ADC
+#define SYSCTL_DC1_MPU          0x00000080  // Cortex-M3 MPU present
+#define SYSCTL_DC1_HIB          0x00000040  // Hibernation module present
+#define SYSCTL_DC1_TEMP         0x00000020  // Temperature sensor present
+#define SYSCTL_DC1_PLL          0x00000010  // PLL present
+#define SYSCTL_DC1_WDT          0x00000008  // Watchdog Timer Present.
+#define SYSCTL_DC1_SWO          0x00000004  // Serial wire output present
+#define SYSCTL_DC1_SWD          0x00000002  // Serial wire debug present
+#define SYSCTL_DC1_JTAG         0x00000001  // JTAG debug present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC2_COMP2        0x04000000  // Analog comparator 2 present
+#define SYSCTL_DC2_COMP1        0x02000000  // Analog comparator 1 present
+#define SYSCTL_DC2_COMP0        0x01000000  // Analog comparator 0 present
+#define SYSCTL_DC2_TIMER3       0x00080000  // Timer 3 present
+#define SYSCTL_DC2_TIMER2       0x00040000  // Timer 2 present
+#define SYSCTL_DC2_TIMER1       0x00020000  // Timer 1 present
+#define SYSCTL_DC2_TIMER0       0x00010000  // Timer 0 present
+#define SYSCTL_DC2_I2C1         0x00004000  // I2C 1 present
+#define SYSCTL_DC2_I2C0         0x00001000  // I2C 0 present
+#define SYSCTL_DC2_QEI1         0x00000200  // QEI 1 present
+#define SYSCTL_DC2_QEI0         0x00000100  // QEI 0 present
+#define SYSCTL_DC2_SSI1         0x00000020  // SSI 1 present
+#define SYSCTL_DC2_SSI0         0x00000010  // SSI 0 present
+#define SYSCTL_DC2_UART2        0x00000004  // UART 2 present
+#define SYSCTL_DC2_UART1        0x00000002  // UART 1 present
+#define SYSCTL_DC2_UART0        0x00000001  // UART 0 present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC3 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC3_32KHZ        0x80000000  // 32KHz Pin Present.
+#define SYSCTL_DC3_CCP5         0x20000000  // CCP5 pin present
+#define SYSCTL_DC3_CCP4         0x10000000  // CCP4 pin present
+#define SYSCTL_DC3_CCP3         0x08000000  // CCP3 pin present
+#define SYSCTL_DC3_CCP2         0x04000000  // CCP2 pin present
+#define SYSCTL_DC3_CCP1         0x02000000  // CCP1 pin present
+#define SYSCTL_DC3_CCP0         0x01000000  // CCP0 pin present
+#define SYSCTL_DC3_ADC7         0x00800000  // ADC7 pin present
+#define SYSCTL_DC3_ADC6         0x00400000  // ADC6 pin present
+#define SYSCTL_DC3_ADC5         0x00200000  // ADC5 pin present
+#define SYSCTL_DC3_ADC4         0x00100000  // ADC4 pin present
+#define SYSCTL_DC3_ADC3         0x00080000  // ADC3 pin present
+#define SYSCTL_DC3_ADC2         0x00040000  // ADC2 pin present
+#define SYSCTL_DC3_ADC1         0x00020000  // ADC1 pin present
+#define SYSCTL_DC3_ADC0         0x00010000  // ADC0 pin present
+#define SYSCTL_DC3_PWMFAULT     0x00008000  // PWM Fault Pin Present.
+#define SYSCTL_DC3_C2O          0x00004000  // C2o pin present
+#define SYSCTL_DC3_C2PLUS       0x00002000  // C2+ pin present
+#define SYSCTL_DC3_C2MINUS      0x00001000  // C2- pin present
+#define SYSCTL_DC3_C1O          0x00000800  // C1o pin present
+#define SYSCTL_DC3_C1PLUS       0x00000400  // C1+ pin present
+#define SYSCTL_DC3_C1MINUS      0x00000200  // C1- pin present
+#define SYSCTL_DC3_C0O          0x00000100  // C0o pin present
+#define SYSCTL_DC3_C0PLUS       0x00000080  // C0+ pin present
+#define SYSCTL_DC3_C0MINUS      0x00000040  // C0- pin present
+#define SYSCTL_DC3_PWM5         0x00000020  // PWM5 pin present
+#define SYSCTL_DC3_PWM4         0x00000010  // PWM4 pin present
+#define SYSCTL_DC3_PWM3         0x00000008  // PWM3 pin present
+#define SYSCTL_DC3_PWM2         0x00000004  // PWM2 pin present
+#define SYSCTL_DC3_PWM1         0x00000002  // PWM1 pin present
+#define SYSCTL_DC3_PWM0         0x00000001  // PWM0 pin present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC4 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC4_ETH          0x50000000  // Ethernet present
+#define SYSCTL_DC4_EPHY0        0x40000000  // Ethernet PHY0 Present.
+#define SYSCTL_DC4_EMAC0        0x10000000  // Ethernet MAC0 Present.
+#define SYSCTL_DC4_E1588        0x01000000  // 1588 Capable.
+#define SYSCTL_DC4_CCP7         0x00008000  // CCP7 Pin Present.
+#define SYSCTL_DC4_CCP6         0x00004000  // CCP6 Pin Present.
+#define SYSCTL_DC4_UDMA         0x00002000  // Micro-DMA is present.
+#define SYSCTL_DC4_ROM          0x00001000  // Internal Code ROM is present.
+#define SYSCTL_DC4_GPIOH        0x00000080  // GPIO port H present
+#define SYSCTL_DC4_GPIOG        0x00000040  // GPIO port G present
+#define SYSCTL_DC4_GPIOF        0x00000020  // GPIO port F present
+#define SYSCTL_DC4_GPIOE        0x00000010  // GPIO port E present
+#define SYSCTL_DC4_GPIOD        0x00000008  // GPIO port D present
+#define SYSCTL_DC4_GPIOC        0x00000004  // GPIO port C present
+#define SYSCTL_DC4_GPIOB        0x00000002  // GPIO port B present
+#define SYSCTL_DC4_GPIOA        0x00000001  // GPIO port A present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PBORCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PBORCTL_BORTIM_M 0x0000FFFC  // BOR Time Delay.
+#define SYSCTL_PBORCTL_BORIOR   0x00000002  // BOR interrupt or reset
+#define SYSCTL_PBORCTL_BORWT    0x00000001  // BOR wait and check for noise
+#define SYSCTL_PBORCTL_BORTIM_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDOPCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOPCTL_M        0x0000003F  // LDO Output Voltage.
+#define SYSCTL_LDOPCTL_2_55V    0x0000001F  // LDO output of 2.55V
+#define SYSCTL_LDOPCTL_2_60V    0x0000001E  // LDO output of 2.60V
+#define SYSCTL_LDOPCTL_2_65V    0x0000001D  // LDO output of 2.65V
+#define SYSCTL_LDOPCTL_2_70V    0x0000001C  // LDO output of 2.70V
+#define SYSCTL_LDOPCTL_2_75V    0x0000001B  // LDO output of 2.75V
+#define SYSCTL_LDOPCTL_2_25V    0x00000005  // LDO output of 2.25V
+#define SYSCTL_LDOPCTL_2_30V    0x00000004  // LDO output of 2.30V
+#define SYSCTL_LDOPCTL_2_35V    0x00000003  // LDO output of 2.35V
+#define SYSCTL_LDOPCTL_2_40V    0x00000002  // LDO output of 2.40V
+#define SYSCTL_LDOPCTL_2_45V    0x00000001  // LDO output of 2.45V
+#define SYSCTL_LDOPCTL_2_50V    0x00000000  // LDO output of 2.50V
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RESC register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_MOSCFAIL    0x00010000  // MOSC Failure Reset.
+#define SYSCTL_RESC_LDO         0x00000020  // LDO power OK lost reset
+#define SYSCTL_RESC_SW          0x00000010  // Software reset
+#define SYSCTL_RESC_WDT         0x00000008  // Watchdog Timer Reset.
+#define SYSCTL_RESC_BOR         0x00000004  // Brown-out reset
+#define SYSCTL_RESC_POR         0x00000002  // Power on reset
+#define SYSCTL_RESC_EXT         0x00000001  // External reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC_ACG          0x08000000  // Automatic clock gating
+#define SYSCTL_RCC_SYSDIV_M     0x07800000  // System Clock Divisor.
+#define SYSCTL_RCC_SYSDIV_2     0x00800000  // System clock /2
+#define SYSCTL_RCC_SYSDIV_3     0x01000000  // System clock /3
+#define SYSCTL_RCC_SYSDIV_4     0x01800000  // System clock /4
+#define SYSCTL_RCC_SYSDIV_5     0x02000000  // System clock /5
+#define SYSCTL_RCC_SYSDIV_6     0x02800000  // System clock /6
+#define SYSCTL_RCC_SYSDIV_7     0x03000000  // System clock /7
+#define SYSCTL_RCC_SYSDIV_8     0x03800000  // System clock /8
+#define SYSCTL_RCC_SYSDIV_9     0x04000000  // System clock /9
+#define SYSCTL_RCC_SYSDIV_10    0x04800000  // System clock /10
+#define SYSCTL_RCC_SYSDIV_11    0x05000000  // System clock /11
+#define SYSCTL_RCC_SYSDIV_12    0x05800000  // System clock /12
+#define SYSCTL_RCC_SYSDIV_13    0x06000000  // System clock /13
+#define SYSCTL_RCC_SYSDIV_14    0x06800000  // System clock /14
+#define SYSCTL_RCC_SYSDIV_15    0x07000000  // System clock /15
+#define SYSCTL_RCC_SYSDIV_16    0x07800000  // System clock /16
+#define SYSCTL_RCC_USESYSDIV    0x00400000  // Enable System Clock Divider.
+#define SYSCTL_RCC_USEPWMDIV    0x00100000  // Enable PWM Clock Divisor.
+#define SYSCTL_RCC_PWMDIV_M     0x000E0000  // PWM clock divider
+#define SYSCTL_RCC_PWMDIV_2     0x00000000  // PWM clock /2
+#define SYSCTL_RCC_PWMDIV_4     0x00020000  // PWM clock /4
+#define SYSCTL_RCC_PWMDIV_8     0x00040000  // PWM clock /8
+#define SYSCTL_RCC_PWMDIV_16    0x00060000  // PWM clock /16
+#define SYSCTL_RCC_PWMDIV_32    0x00080000  // PWM clock /32
+#define SYSCTL_RCC_PWMDIV_64    0x000A0000  // PWM clock /64
+#define SYSCTL_RCC_PWRDN        0x00002000  // PLL power down
+#define SYSCTL_RCC_OEN          0x00001000  // PLL Output Enable.
+#define SYSCTL_RCC_BYPASS       0x00000800  // PLL bypass
+#define SYSCTL_RCC_XTAL_M       0x000007C0  // Crystal attached to main osc
+#define SYSCTL_RCC_XTAL_1MHZ    0x00000000  // Using a 1MHz crystal
+#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040  // Using a 1.8432MHz crystal
+#define SYSCTL_RCC_XTAL_2MHZ    0x00000080  // Using a 2MHz crystal
+#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0  // Using a 2.4576MHz crystal
+#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100  // Using a 3.579545MHz crystal
+#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140  // Using a 3.6864MHz crystal
+#define SYSCTL_RCC_XTAL_4MHZ    0x00000180  // Using a 4MHz crystal
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0  // Using a 4.096MHz crystal
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200  // Using a 4.9152MHz crystal
+#define SYSCTL_RCC_XTAL_5MHZ    0x00000240  // Using a 5MHz crystal
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280  // Using a 5.12MHz crystal
+#define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  // Using a 6MHz crystal
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300  // Using a 6.144MHz crystal
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340  // Using a 7.3728MHz crystal
+#define SYSCTL_RCC_XTAL_8MHZ    0x00000380  // Using a 8MHz crystal
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0  // Using a 8.192MHz crystal
+#define SYSCTL_RCC_XTAL_10MHZ   0x00000400  // 10.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_12MHZ   0x00000440  // 12.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480  // 12.288 MHz
+#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0  // 13.56 MHz
+#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500  // 14.31818 MHz
+#define SYSCTL_RCC_XTAL_16MHZ   0x00000540  // 16.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580  // 16.384 MHz
+#define SYSCTL_RCC_PLLVER       0x00000400  // PLL verification timer enable
+#define SYSCTL_RCC_OSCSRC_M     0x00000030  // Oscillator input select
+#define SYSCTL_RCC_OSCSRC_MAIN  0x00000000  // Use the main oscillator
+#define SYSCTL_RCC_OSCSRC_INT   0x00000010  // Use the internal oscillator
+#define SYSCTL_RCC_OSCSRC_INT4  0x00000020  // Use the internal oscillator / 4
+#define SYSCTL_RCC_OSCSRC_30    0x00000030  // 30 KHz internal oscillator
+#define SYSCTL_RCC_IOSCVER      0x00000008  // Int. osc. verification timer en
+#define SYSCTL_RCC_MOSCVER      0x00000004  // Main osc. verification timer en
+#define SYSCTL_RCC_IOSCDIS      0x00000002  // Internal oscillator disable
+#define SYSCTL_RCC_MOSCDIS      0x00000001  // Main oscillator disable
+#define SYSCTL_RCC_SYSDIV_S     23          // Shift to the SYSDIV field
+#define SYSCTL_RCC_PWMDIV_S     17          // Shift to the PWMDIV field
+#define SYSCTL_RCC_XTAL_S       6           // Shift to the XTAL field
+#define SYSCTL_RCC_OSCSRC_S     4           // Shift to the OSCSRC field
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLCFG register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLCFG_OD_M      0x0000C000  // Output divider
+#define SYSCTL_PLLCFG_OD_1      0x00000000  // Output divider is 1
+#define SYSCTL_PLLCFG_OD_2      0x00004000  // Output divider is 2
+#define SYSCTL_PLLCFG_OD_4      0x00008000  // Output divider is 4
+#define SYSCTL_PLLCFG_F_M       0x00003FE0  // PLL F Value.
+#define SYSCTL_PLLCFG_R_M       0x0000001F  // PLL R Value.
+#define SYSCTL_PLLCFG_F_S       5
+#define SYSCTL_PLLCFG_R_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_USERCC2     0x80000000  // Use RCC2
+#define SYSCTL_RCC2_SYSDIV2_M   0x1F800000  // System clock divider
+#define SYSCTL_RCC2_SYSDIV2_2   0x00800000  // System clock /2
+#define SYSCTL_RCC2_SYSDIV2_3   0x01000000  // System clock /3
+#define SYSCTL_RCC2_SYSDIV2_4   0x01800000  // System clock /4
+#define SYSCTL_RCC2_SYSDIV2_5   0x02000000  // System clock /5
+#define SYSCTL_RCC2_SYSDIV2_6   0x02800000  // System clock /6
+#define SYSCTL_RCC2_SYSDIV2_7   0x03000000  // System clock /7
+#define SYSCTL_RCC2_SYSDIV2_8   0x03800000  // System clock /8
+#define SYSCTL_RCC2_SYSDIV2_9   0x04000000  // System clock /9
+#define SYSCTL_RCC2_SYSDIV2_10  0x04800000  // System clock /10
+#define SYSCTL_RCC2_SYSDIV2_11  0x05000000  // System clock /11
+#define SYSCTL_RCC2_SYSDIV2_12  0x05800000  // System clock /12
+#define SYSCTL_RCC2_SYSDIV2_13  0x06000000  // System clock /13
+#define SYSCTL_RCC2_SYSDIV2_14  0x06800000  // System clock /14
+#define SYSCTL_RCC2_SYSDIV2_15  0x07000000  // System clock /15
+#define SYSCTL_RCC2_SYSDIV2_16  0x07800000  // System clock /16
+#define SYSCTL_RCC2_SYSDIV2_17  0x08000000  // System clock /17
+#define SYSCTL_RCC2_SYSDIV2_18  0x08800000  // System clock /18
+#define SYSCTL_RCC2_SYSDIV2_19  0x09000000  // System clock /19
+#define SYSCTL_RCC2_SYSDIV2_20  0x09800000  // System clock /20
+#define SYSCTL_RCC2_SYSDIV2_21  0x0A000000  // System clock /21
+#define SYSCTL_RCC2_SYSDIV2_22  0x0A800000  // System clock /22
+#define SYSCTL_RCC2_SYSDIV2_23  0x0B000000  // System clock /23
+#define SYSCTL_RCC2_SYSDIV2_24  0x0B800000  // System clock /24
+#define SYSCTL_RCC2_SYSDIV2_25  0x0C000000  // System clock /25
+#define SYSCTL_RCC2_SYSDIV2_26  0x0C800000  // System clock /26
+#define SYSCTL_RCC2_SYSDIV2_27  0x0D000000  // System clock /27
+#define SYSCTL_RCC2_SYSDIV2_28  0x0D800000  // System clock /28
+#define SYSCTL_RCC2_SYSDIV2_29  0x0E000000  // System clock /29
+#define SYSCTL_RCC2_SYSDIV2_30  0x0E800000  // System clock /30
+#define SYSCTL_RCC2_SYSDIV2_31  0x0F000000  // System clock /31
+#define SYSCTL_RCC2_SYSDIV2_32  0x0F800000  // System clock /32
+#define SYSCTL_RCC2_SYSDIV2_33  0x10000000  // System clock /33
+#define SYSCTL_RCC2_SYSDIV2_34  0x10800000  // System clock /34
+#define SYSCTL_RCC2_SYSDIV2_35  0x11000000  // System clock /35
+#define SYSCTL_RCC2_SYSDIV2_36  0x11800000  // System clock /36
+#define SYSCTL_RCC2_SYSDIV2_37  0x12000000  // System clock /37
+#define SYSCTL_RCC2_SYSDIV2_38  0x12800000  // System clock /38
+#define SYSCTL_RCC2_SYSDIV2_39  0x13000000  // System clock /39
+#define SYSCTL_RCC2_SYSDIV2_40  0x13800000  // System clock /40
+#define SYSCTL_RCC2_SYSDIV2_41  0x14000000  // System clock /41
+#define SYSCTL_RCC2_SYSDIV2_42  0x14800000  // System clock /42
+#define SYSCTL_RCC2_SYSDIV2_43  0x15000000  // System clock /43
+#define SYSCTL_RCC2_SYSDIV2_44  0x15800000  // System clock /44
+#define SYSCTL_RCC2_SYSDIV2_45  0x16000000  // System clock /45
+#define SYSCTL_RCC2_SYSDIV2_46  0x16800000  // System clock /46
+#define SYSCTL_RCC2_SYSDIV2_47  0x17000000  // System clock /47
+#define SYSCTL_RCC2_SYSDIV2_48  0x17800000  // System clock /48
+#define SYSCTL_RCC2_SYSDIV2_49  0x18000000  // System clock /49
+#define SYSCTL_RCC2_SYSDIV2_50  0x18800000  // System clock /50
+#define SYSCTL_RCC2_SYSDIV2_51  0x19000000  // System clock /51
+#define SYSCTL_RCC2_SYSDIV2_52  0x19800000  // System clock /52
+#define SYSCTL_RCC2_SYSDIV2_53  0x1A000000  // System clock /53
+#define SYSCTL_RCC2_SYSDIV2_54  0x1A800000  // System clock /54
+#define SYSCTL_RCC2_SYSDIV2_55  0x1B000000  // System clock /55
+#define SYSCTL_RCC2_SYSDIV2_56  0x1B800000  // System clock /56
+#define SYSCTL_RCC2_SYSDIV2_57  0x1C000000  // System clock /57
+#define SYSCTL_RCC2_SYSDIV2_58  0x1C800000  // System clock /58
+#define SYSCTL_RCC2_SYSDIV2_59  0x1D000000  // System clock /59
+#define SYSCTL_RCC2_SYSDIV2_60  0x1D800000  // System clock /60
+#define SYSCTL_RCC2_SYSDIV2_61  0x1E000000  // System clock /61
+#define SYSCTL_RCC2_SYSDIV2_62  0x1E800000  // System clock /62
+#define SYSCTL_RCC2_SYSDIV2_63  0x1F000000  // System clock /63
+#define SYSCTL_RCC2_SYSDIV2_64  0x1F800000  // System clock /64
+#define SYSCTL_RCC2_USBPWRDN    0x00004000  // Power-Down USB PLL.
+#define SYSCTL_RCC2_PWRDN2      0x00002000  // PLL power down
+#define SYSCTL_RCC2_BYPASS2     0x00000800  // PLL bypass
+#define SYSCTL_RCC2_OSCSRC2_M   0x00000070  // System Clock Source.
+#define SYSCTL_RCC2_OSCSRC2_MO  0x00000000  // Use the main oscillator
+#define SYSCTL_RCC2_OSCSRC2_IO  0x00000010  // Use the internal oscillator
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020  // Use the internal oscillator / 4
+#define SYSCTL_RCC2_OSCSRC2_30  0x00000030  // Use the 30 KHz internal osc.
+#define SYSCTL_RCC2_OSCSRC2_32  0x00000070  // Use the 32 KHz external osc.
+#define SYSCTL_RCC2_SYSDIV2_S   23          // Shift to the SYSDIV2 field
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPCLKCFG_D_M   0x1F800000  // Divider Field Override.
+#define SYSCTL_DSLPCLKCFG_D_2   0x00800000  // System clock /2
+#define SYSCTL_DSLPCLKCFG_D_3   0x01000000  // System clock /3
+#define SYSCTL_DSLPCLKCFG_D_4   0x01800000  // System clock /4
+#define SYSCTL_DSLPCLKCFG_D_5   0x02000000  // System clock /5
+#define SYSCTL_DSLPCLKCFG_D_6   0x02800000  // System clock /6
+#define SYSCTL_DSLPCLKCFG_D_7   0x03000000  // System clock /7
+#define SYSCTL_DSLPCLKCFG_D_8   0x03800000  // System clock /8
+#define SYSCTL_DSLPCLKCFG_D_9   0x04000000  // System clock /9
+#define SYSCTL_DSLPCLKCFG_D_10  0x04800000  // System clock /10
+#define SYSCTL_DSLPCLKCFG_D_11  0x05000000  // System clock /11
+#define SYSCTL_DSLPCLKCFG_D_12  0x05800000  // System clock /12
+#define SYSCTL_DSLPCLKCFG_D_13  0x06000000  // System clock /13
+#define SYSCTL_DSLPCLKCFG_D_14  0x06800000  // System clock /14
+#define SYSCTL_DSLPCLKCFG_D_15  0x07000000  // System clock /15
+#define SYSCTL_DSLPCLKCFG_D_16  0x07800000  // System clock /16
+#define SYSCTL_DSLPCLKCFG_D_17  0x08000000  // System clock /17
+#define SYSCTL_DSLPCLKCFG_D_18  0x08800000  // System clock /18
+#define SYSCTL_DSLPCLKCFG_D_19  0x09000000  // System clock /19
+#define SYSCTL_DSLPCLKCFG_D_20  0x09800000  // System clock /20
+#define SYSCTL_DSLPCLKCFG_D_21  0x0A000000  // System clock /21
+#define SYSCTL_DSLPCLKCFG_D_22  0x0A800000  // System clock /22
+#define SYSCTL_DSLPCLKCFG_D_23  0x0B000000  // System clock /23
+#define SYSCTL_DSLPCLKCFG_D_24  0x0B800000  // System clock /24
+#define SYSCTL_DSLPCLKCFG_D_25  0x0C000000  // System clock /25
+#define SYSCTL_DSLPCLKCFG_D_26  0x0C800000  // System clock /26
+#define SYSCTL_DSLPCLKCFG_D_27  0x0D000000  // System clock /27
+#define SYSCTL_DSLPCLKCFG_D_28  0x0D800000  // System clock /28
+#define SYSCTL_DSLPCLKCFG_D_29  0x0E000000  // System clock /29
+#define SYSCTL_DSLPCLKCFG_D_30  0x0E800000  // System clock /30
+#define SYSCTL_DSLPCLKCFG_D_31  0x0F000000  // System clock /31
+#define SYSCTL_DSLPCLKCFG_D_32  0x0F800000  // System clock /32
+#define SYSCTL_DSLPCLKCFG_D_33  0x10000000  // System clock /33
+#define SYSCTL_DSLPCLKCFG_D_34  0x10800000  // System clock /34
+#define SYSCTL_DSLPCLKCFG_D_35  0x11000000  // System clock /35
+#define SYSCTL_DSLPCLKCFG_D_36  0x11800000  // System clock /36
+#define SYSCTL_DSLPCLKCFG_D_37  0x12000000  // System clock /37
+#define SYSCTL_DSLPCLKCFG_D_38  0x12800000  // System clock /38
+#define SYSCTL_DSLPCLKCFG_D_39  0x13000000  // System clock /39
+#define SYSCTL_DSLPCLKCFG_D_40  0x13800000  // System clock /40
+#define SYSCTL_DSLPCLKCFG_D_41  0x14000000  // System clock /41
+#define SYSCTL_DSLPCLKCFG_D_42  0x14800000  // System clock /42
+#define SYSCTL_DSLPCLKCFG_D_43  0x15000000  // System clock /43
+#define SYSCTL_DSLPCLKCFG_D_44  0x15800000  // System clock /44
+#define SYSCTL_DSLPCLKCFG_D_45  0x16000000  // System clock /45
+#define SYSCTL_DSLPCLKCFG_D_46  0x16800000  // System clock /46
+#define SYSCTL_DSLPCLKCFG_D_47  0x17000000  // System clock /47
+#define SYSCTL_DSLPCLKCFG_D_48  0x17800000  // System clock /48
+#define SYSCTL_DSLPCLKCFG_D_49  0x18000000  // System clock /49
+#define SYSCTL_DSLPCLKCFG_D_50  0x18800000  // System clock /50
+#define SYSCTL_DSLPCLKCFG_D_51  0x19000000  // System clock /51
+#define SYSCTL_DSLPCLKCFG_D_52  0x19800000  // System clock /52
+#define SYSCTL_DSLPCLKCFG_D_53  0x1A000000  // System clock /53
+#define SYSCTL_DSLPCLKCFG_D_54  0x1A800000  // System clock /54
+#define SYSCTL_DSLPCLKCFG_D_55  0x1B000000  // System clock /55
+#define SYSCTL_DSLPCLKCFG_D_56  0x1B800000  // System clock /56
+#define SYSCTL_DSLPCLKCFG_D_57  0x1C000000  // System clock /57
+#define SYSCTL_DSLPCLKCFG_D_58  0x1C800000  // System clock /58
+#define SYSCTL_DSLPCLKCFG_D_59  0x1D000000  // System clock /59
+#define SYSCTL_DSLPCLKCFG_D_60  0x1D800000  // System clock /60
+#define SYSCTL_DSLPCLKCFG_D_61  0x1E000000  // System clock /61
+#define SYSCTL_DSLPCLKCFG_D_62  0x1E800000  // System clock /62
+#define SYSCTL_DSLPCLKCFG_D_63  0x1F000000  // System clock /63
+#define SYSCTL_DSLPCLKCFG_D_64  0x1F800000  // System clock /64
+#define SYSCTL_DSLPCLKCFG_O_M   0x00000070  // Clock Source.
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000  // Do not override
+#define SYSCTL_DSLPCLKCFG_O_IO  0x00000010  // Use the internal oscillator
+#define SYSCTL_DSLPCLKCFG_O_30  0x00000030  // Use the 30 KHz internal osc.
+#define SYSCTL_DSLPCLKCFG_O_32  0x00000070  // Use the 32 KHz external osc.
+#define SYSCTL_DSLPCLKCFG_IOSC  0x00000001  // IOSC Clock Source.
+#define SYSCTL_DSLPCLKCFG_D_S   23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_CLKVCLR register.
+//
+//*****************************************************************************
+#define SYSCTL_CLKVCLR_VERCLR   0x00000001  // Clock Verification Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDOARST register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOARST_LDOARST  0x00000001  // LDO Reset.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR0_CAN2       0x04000000  // CAN2 Reset Control.
+#define SYSCTL_SRCR0_CAN1       0x02000000  // CAN1 Reset Control.
+#define SYSCTL_SRCR0_CAN0       0x01000000  // CAN0 Reset Control.
+#define SYSCTL_SRCR0_PWM        0x00100000  // PWM Reset Control.
+#define SYSCTL_SRCR0_ADC        0x00010000  // ADC0 Reset Control.
+#define SYSCTL_SRCR0_HIB        0x00000040  // HIB Reset Control.
+#define SYSCTL_SRCR0_WDT        0x00000008  // WDT Reset Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR1_COMP2      0x04000000  // Analog Comp 2 Reset Control.
+#define SYSCTL_SRCR1_COMP1      0x02000000  // Analog Comp 1 Reset Control.
+#define SYSCTL_SRCR1_COMP0      0x01000000  // Analog Comp 0 Reset Control.
+#define SYSCTL_SRCR1_TIMER3     0x00080000  // Timer 3 Reset Control.
+#define SYSCTL_SRCR1_TIMER2     0x00040000  // Timer 2 Reset Control.
+#define SYSCTL_SRCR1_TIMER1     0x00020000  // Timer 1 Reset Control.
+#define SYSCTL_SRCR1_TIMER0     0x00010000  // Timer 0 Reset Control.
+#define SYSCTL_SRCR1_I2C1       0x00004000  // I2C1 Reset Control.
+#define SYSCTL_SRCR1_I2C0       0x00001000  // I2C0 Reset Control.
+#define SYSCTL_SRCR1_QEI1       0x00000200  // QEI1 Reset Control.
+#define SYSCTL_SRCR1_QEI0       0x00000100  // QEI0 Reset Control.
+#define SYSCTL_SRCR1_SSI1       0x00000020  // SSI1 Reset Control.
+#define SYSCTL_SRCR1_SSI0       0x00000010  // SSI0 Reset Control.
+#define SYSCTL_SRCR1_UART2      0x00000004  // UART2 Reset Control.
+#define SYSCTL_SRCR1_UART1      0x00000002  // UART1 Reset Control.
+#define SYSCTL_SRCR1_UART0      0x00000001  // UART0 Reset Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR2_EPHY0      0x40000000  // PHY0 Reset Control.
+#define SYSCTL_SRCR2_EMAC0      0x10000000  // MAC0 Reset Control.
+#define SYSCTL_SRCR2_USB0       0x00010000  // USB0 Reset Control.
+#define SYSCTL_SRCR2_UDMA       0x00002000  // UDMA Reset Control.
+#define SYSCTL_SRCR2_GPIOH      0x00000080  // Port H Reset Control.
+#define SYSCTL_SRCR2_GPIOG      0x00000040  // Port G Reset Control.
+#define SYSCTL_SRCR2_GPIOF      0x00000020  // Port F Reset Control.
+#define SYSCTL_SRCR2_GPIOE      0x00000010  // Port E Reset Control.
+#define SYSCTL_SRCR2_GPIOD      0x00000008  // Port D Reset Control.
+#define SYSCTL_SRCR2_GPIOC      0x00000004  // Port C Reset Control.
+#define SYSCTL_SRCR2_GPIOB      0x00000002  // Port B Reset Control.
+#define SYSCTL_SRCR2_GPIOA      0x00000001  // Port A Reset Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RIS register.
+//
+//*****************************************************************************
+#define SYSCTL_RIS_MOSCPUPRIS   0x00000100  // MOSC Power Up Raw Interrupt
+                                            // Status.
+#define SYSCTL_RIS_USBPLLLRIS   0x00000080  // USB PLL Lock Raw Interrupt
+                                            // Status.
+#define SYSCTL_RIS_PLLLRIS      0x00000040  // PLL Lock Raw Interrupt Status.
+#define SYSCTL_RIS_CLRIS        0x00000020  // Current Limit Raw Interrupt
+                                            // Status.
+#define SYSCTL_RIS_IOFRIS       0x00000010  // Internal Oscillator Fault Raw
+                                            // Interrupt Status.
+#define SYSCTL_RIS_MOFRIS       0x00000008  // Main Oscillator Fault Raw
+                                            // Interrupt Status.
+#define SYSCTL_RIS_LDORIS       0x00000004  // LDO Power Unregulated Raw
+                                            // Interrupt Status.
+#define SYSCTL_RIS_BORRIS       0x00000002  // Brown-Out Reset Raw Interrupt
+                                            // Status.
+#define SYSCTL_RIS_PLLFRIS      0x00000001  // PLL Fault Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_IMC register.
+//
+//*****************************************************************************
+#define SYSCTL_IMC_MOSCPUPIM    0x00000100  // MOSC Power Up Interrupt Mask.
+#define SYSCTL_IMC_USBPLLLIM    0x00000080  // USB PLL Lock Interrupt Mask.
+#define SYSCTL_IMC_PLLLIM       0x00000040  // PLL Lock Interrupt Mask.
+#define SYSCTL_IMC_CLIM         0x00000020  // Current Limit Interrupt Mask.
+#define SYSCTL_IMC_IOFIM        0x00000010  // Internal Oscillator Fault
+                                            // Interrupt Mask.
+#define SYSCTL_IMC_MOFIM        0x00000008  // Main Oscillator Fault Interrupt
+                                            // Mask.
+#define SYSCTL_IMC_LDOIM        0x00000004  // LDO Power Unregulated Interrupt
+                                            // Mask.
+#define SYSCTL_IMC_BORIM        0x00000002  // Brown-Out Reset Interrupt Mask.
+#define SYSCTL_IMC_PLLFIM       0x00000001  // PLL Fault Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MISC register.
+//
+//*****************************************************************************
+#define SYSCTL_MISC_MOSCPUPMIS  0x00000100  // MOSC Power Up Masked Interrupt
+                                            // Status.
+#define SYSCTL_MISC_USBPLLLMIS  0x00000080  // USB PLL Lock Masked Interrupt
+                                            // Status.
+#define SYSCTL_MISC_PLLLMIS     0x00000040  // PLL Lock Masked Interrupt
+                                            // Status.
+#define SYSCTL_MISC_CLMIS       0x00000020  // Current Limit Masked Interrupt
+                                            // Status.
+#define SYSCTL_MISC_IOFMIS      0x00000010  // Internal Oscillator Fault Masked
+                                            // Interrupt Status.
+#define SYSCTL_MISC_MOFMIS      0x00000008  // Main Oscillator Fault Masked
+                                            // Interrupt Status.
+#define SYSCTL_MISC_LDOMIS      0x00000004  // LDO Power Unregulated Masked
+                                            // Interrupt Status.
+#define SYSCTL_MISC_BORMIS      0x00000002  // BOR Masked Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC0_CAN2       0x04000000  // CAN2 Clock Gating Control.
+#define SYSCTL_RCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control.
+#define SYSCTL_RCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control.
+#define SYSCTL_RCGC0_PWM        0x00100000  // PWM Clock Gating Control.
+#define SYSCTL_RCGC0_ADC        0x00010000  // ADC0 Clock Gating Control.
+#define SYSCTL_RCGC0_ADCSPD_M   0x00000F00  // ADC Sample Speed.
+#define SYSCTL_RCGC0_ADCSPD125K 0x00000000  // 125K samples/second
+#define SYSCTL_RCGC0_ADCSPD250K 0x00000100  // 250K samples/second
+#define SYSCTL_RCGC0_ADCSPD500K 0x00000200  // 500K samples/second
+#define SYSCTL_RCGC0_ADCSPD1M   0x00000300  // 1M samples/second
+#define SYSCTL_RCGC0_HIB        0x00000040  // HIB Clock Gating Control.
+#define SYSCTL_RCGC0_WDT        0x00000008  // WDT Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock
+                                            // Gating.
+#define SYSCTL_RCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock
+                                            // Gating.
+#define SYSCTL_RCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock
+                                            // Gating.
+#define SYSCTL_RCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control.
+#define SYSCTL_RCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control.
+#define SYSCTL_RCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control.
+#define SYSCTL_RCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control.
+#define SYSCTL_RCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control.
+#define SYSCTL_RCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control.
+#define SYSCTL_RCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control.
+#define SYSCTL_RCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control.
+#define SYSCTL_RCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control.
+#define SYSCTL_RCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control.
+#define SYSCTL_RCGC1_UART2      0x00000004  // UART2 Clock Gating Control.
+#define SYSCTL_RCGC1_UART1      0x00000002  // UART1 Clock Gating Control.
+#define SYSCTL_RCGC1_UART0      0x00000001  // UART0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control.
+#define SYSCTL_RCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control.
+#define SYSCTL_RCGC2_USB0       0x00010000  // USB0 Clock Gating Control.
+#define SYSCTL_RCGC2_UDMA       0x00002000  // UDMA Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOH      0x00000080  // Port H Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOG      0x00000040  // Port G Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOF      0x00000020  // Port F Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOE      0x00000010  // Port E Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOD      0x00000008  // Port D Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOC      0x00000004  // Port C Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOB      0x00000002  // Port B Clock Gating Control.
+#define SYSCTL_RCGC2_GPIOA      0x00000001  // Port A Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC0_CAN2       0x04000000  // CAN2 Clock Gating Control.
+#define SYSCTL_SCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control.
+#define SYSCTL_SCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control.
+#define SYSCTL_SCGC0_PWM        0x00100000  // PWM Clock Gating Control.
+#define SYSCTL_SCGC0_ADC        0x00010000  // ADC0 Clock Gating Control.
+#define SYSCTL_SCGC0_ADCSPD_M   0x00000F00  // ADC Sample Speed.
+#define SYSCTL_SCGC0_ADCSPD125K 0x00000000  // 125K samples/second
+#define SYSCTL_SCGC0_ADCSPD250K 0x00000100  // 250K samples/second
+#define SYSCTL_SCGC0_ADCSPD500K 0x00000200  // 500K samples/second
+#define SYSCTL_SCGC0_ADCSPD1M   0x00000300  // 1M samples/second
+#define SYSCTL_SCGC0_HIB        0x00000040  // HIB Clock Gating Control.
+#define SYSCTL_SCGC0_WDT        0x00000008  // WDT Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock
+                                            // Gating.
+#define SYSCTL_SCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock
+                                            // Gating.
+#define SYSCTL_SCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock
+                                            // Gating.
+#define SYSCTL_SCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control.
+#define SYSCTL_SCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control.
+#define SYSCTL_SCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control.
+#define SYSCTL_SCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control.
+#define SYSCTL_SCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control.
+#define SYSCTL_SCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control.
+#define SYSCTL_SCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control.
+#define SYSCTL_SCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control.
+#define SYSCTL_SCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control.
+#define SYSCTL_SCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control.
+#define SYSCTL_SCGC1_UART2      0x00000004  // UART2 Clock Gating Control.
+#define SYSCTL_SCGC1_UART1      0x00000002  // UART1 Clock Gating Control.
+#define SYSCTL_SCGC1_UART0      0x00000001  // UART0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control.
+#define SYSCTL_SCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control.
+#define SYSCTL_SCGC2_USB0       0x00010000  // USB0 Clock Gating Control.
+#define SYSCTL_SCGC2_UDMA       0x00002000  // UDMA Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOH      0x00000080  // Port H Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOG      0x00000040  // Port G Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOF      0x00000020  // Port F Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOE      0x00000010  // Port E Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOD      0x00000008  // Port D Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOC      0x00000004  // Port C Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOB      0x00000002  // Port B Clock Gating Control.
+#define SYSCTL_SCGC2_GPIOA      0x00000001  // Port A Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC0_CAN2       0x04000000  // CAN2 Clock Gating Control.
+#define SYSCTL_DCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control.
+#define SYSCTL_DCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control.
+#define SYSCTL_DCGC0_PWM        0x00100000  // PWM Clock Gating Control.
+#define SYSCTL_DCGC0_ADC        0x00010000  // ADC0 Clock Gating Control.
+#define SYSCTL_DCGC0_ADCSPD_M   0x00000F00  // ADC Sample Speed.
+#define SYSCTL_DCGC0_ADCSPD125K 0x00000000  // 125K samples/second
+#define SYSCTL_DCGC0_ADCSPD250K 0x00000100  // 250K samples/second
+#define SYSCTL_DCGC0_ADCSPD500K 0x00000200  // 500K samples/second
+#define SYSCTL_DCGC0_ADCSPD1M   0x00000300  // 1M samples/second
+#define SYSCTL_DCGC0_HIB        0x00000040  // HIB Clock Gating Control.
+#define SYSCTL_DCGC0_WDT        0x00000008  // WDT Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock
+                                            // Gating.
+#define SYSCTL_DCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock
+                                            // Gating.
+#define SYSCTL_DCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock
+                                            // Gating.
+#define SYSCTL_DCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control.
+#define SYSCTL_DCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control.
+#define SYSCTL_DCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control.
+#define SYSCTL_DCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control.
+#define SYSCTL_DCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control.
+#define SYSCTL_DCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control.
+#define SYSCTL_DCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control.
+#define SYSCTL_DCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control.
+#define SYSCTL_DCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control.
+#define SYSCTL_DCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control.
+#define SYSCTL_DCGC1_UART2      0x00000004  // UART2 Clock Gating Control.
+#define SYSCTL_DCGC1_UART1      0x00000002  // UART1 Clock Gating Control.
+#define SYSCTL_DCGC1_UART0      0x00000001  // UART0 Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control.
+#define SYSCTL_DCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control.
+#define SYSCTL_DCGC2_USB0       0x00010000  // USB0 Clock Gating Control.
+#define SYSCTL_DCGC2_UDMA       0x00002000  // UDMA Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOH      0x00000080  // Port H Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOG      0x00000040  // Port G Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOF      0x00000020  // Port F Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOE      0x00000010  // Port E Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOD      0x00000008  // Port D Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOC      0x00000004  // Port C Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOB      0x00000002  // Port B Clock Gating Control.
+#define SYSCTL_DCGC2_GPIOA      0x00000001  // Port A Clock Gating Control.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC5 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC5_PWMFAULT3    0x08000000  // PWM Fault 3 Pin Present.
+#define SYSCTL_DC5_PWMFAULT2    0x04000000  // PWM Fault 2 Pin Present.
+#define SYSCTL_DC5_PWMFAULT1    0x02000000  // PWM Fault 1 Pin Present.
+#define SYSCTL_DC5_PWMFAULT0    0x01000000  // PWM Fault 0 Pin Present.
+#define SYSCTL_DC5_PWMEFLT      0x00200000  // PWM Extended Fault feature is
+                                            // active.
+#define SYSCTL_DC5_PWMESYNC     0x00100000  // PWM Extended SYNC feature is
+                                            // active.
+#define SYSCTL_DC5_PWM7         0x00000080  // PWM7 Pin Present.
+#define SYSCTL_DC5_PWM6         0x00000040  // PWM6 Pin Present.
+#define SYSCTL_DC5_PWM5         0x00000020  // PWM5 Pin Present.
+#define SYSCTL_DC5_PWM4         0x00000010  // PWM4 Pin Present.
+#define SYSCTL_DC5_PWM3         0x00000008  // PWM3 Pin Present.
+#define SYSCTL_DC5_PWM2         0x00000004  // PWM2 Pin Present.
+#define SYSCTL_DC5_PWM1         0x00000002  // PWM1 Pin Present.
+#define SYSCTL_DC5_PWM0         0x00000001  // PWM0 Pin Present.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC6 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC6_USB0_M       0x00000003  // This specifies that USB0 is
+                                            // present and its capability.
+#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002  // USB is DEVICE or HOST
+#define SYSCTL_DC6_USB0_OTG     0x00000003  // USB is OTG
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_GPIOHSCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_GPIOHSCTL_PORTH  0x00000080  // Port H High-Speed.
+#define SYSCTL_GPIOHSCTL_PORTG  0x00000040  // Port G High-Speed.
+#define SYSCTL_GPIOHSCTL_PORTF  0x00000020  // Port F High-Speed.
+#define SYSCTL_GPIOHSCTL_PORTE  0x00000010  // Port E High-Speed.
+#define SYSCTL_GPIOHSCTL_PORTD  0x00000008  // Port D High-Speed.
+#define SYSCTL_GPIOHSCTL_PORTC  0x00000004  // Port C High-Speed.
+#define SYSCTL_GPIOHSCTL_PORTB  0x00000002  // Port B High-Speed.
+#define SYSCTL_GPIOHSCTL_PORTA  0x00000001  // Port A High-Speed.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_MOSCCTL_CVAL     0x00000001  // Clock Validation for MOSC.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC7 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC7_SSI1_TX      0x02000000  // SSI1 TX on uDMA Ch25.
+#define SYSCTL_DC7_SSI1_RX      0x01000000  // SSI1 RX on uDMA Ch24.
+#define SYSCTL_DC7_UART1_TX     0x00800000  // UART1 TX on uDMA Ch23.
+#define SYSCTL_DC7_UART1_RX     0x00400000  // UART1 RX on uDMA Ch22.
+#define SYSCTL_DC7_SSI0_TX      0x00000800  // SSI0 TX on uDMA Ch11.
+#define SYSCTL_DC7_SSI0_RX      0x00000400  // SSI0 RX on uDMA Ch10.
+#define SYSCTL_DC7_UART0_TX     0x00000200  // UART0 TX on uDMA Ch9.
+#define SYSCTL_DC7_UART0_RX     0x00000100  // UART0 RX on uDMA Ch8.
+#define SYSCTL_DC7_USB_EP3_TX   0x00000020  // USB EP3 TX on uDMA Ch5.
+#define SYSCTL_DC7_USB_EP3_RX   0x00000010  // USB EP3 RX on uDMA Ch4.
+#define SYSCTL_DC7_USB_EP2_TX   0x00000008  // USB EP2 TX on uDMA Ch3.
+#define SYSCTL_DC7_USB_EP2_RX   0x00000004  // USB EP2 RX on uDMA Ch2.
+#define SYSCTL_DC7_USB_EP1_TX   0x00000002  // USB EP1 TX on uDMA Ch1.
+#define SYSCTL_DC7_USB_EP1_RX   0x00000001  // USB EP1 RX on uDMA Ch0.
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the system control register
+// addresses.
+//
+//*****************************************************************************
+#define SYSCTL_USER0            0x400FE1E0  // NV User Register 0
+#define SYSCTL_USER1            0x400FE1E4  // NV User Register 1
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DID0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_VER_MASK    0x70000000  // DID0 version mask
+#define SYSCTL_DID0_CLASS_MASK  0x00FF0000  // Device Class
+#define SYSCTL_DID0_MAJ_MASK    0x0000FF00  // Major revision mask
+#define SYSCTL_DID0_MAJ_A       0x00000000  // Major revision A
+#define SYSCTL_DID0_MAJ_B       0x00000100  // Major revision B
+#define SYSCTL_DID0_MAJ_C       0x00000200  // Major revision C
+#define SYSCTL_DID0_MIN_MASK    0x000000FF  // Minor revision mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DID1
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_VER_MASK    0xF0000000  // Register version mask
+#define SYSCTL_DID1_FAM_MASK    0x0F000000  // Family mask
+#define SYSCTL_DID1_FAM_S       0x00000000  // Stellaris family
+#define SYSCTL_DID1_PRTNO_MASK  0x00FF0000  // Part number mask
+#define SYSCTL_DID1_PINCNT_MASK 0x0000E000  // Pin count
+#define SYSCTL_DID1_TEMP_MASK   0x000000E0  // Temperature range mask
+#define SYSCTL_DID1_PKG_MASK    0x00000018  // Package mask
+#define SYSCTL_DID1_QUAL_MASK   0x00000003  // Qualification status mask
+#define SYSCTL_DID1_PRTNO_SHIFT 16
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DC0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DC0_SRAMSZ_MASK  0xFFFF0000  // SRAM size mask
+#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF  // Flash size mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DC1
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_SYSDIV_MASK  0x0000F000  // Minimum system divider mask
+#define SYSCTL_DC1_ADCSPD_MASK  0x00000F00  // ADC speed mask
+#define SYSCTL_DC1_WDOG         0x00000008  // Watchdog present
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DC2
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DC2_I2C          0x00001000  // I2C present
+#define SYSCTL_DC2_QEI          0x00000100  // QEI present
+#define SYSCTL_DC2_SSI          0x00000010  // SSI present
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DC3
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DC3_MC_FAULT0    0x00008000  // MC0 fault pin present
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_PBORCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC  // BOR wait timer
+#define SYSCTL_PBORCTL_BOR_SH   2
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_LDOPCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOPCTL_MASK     0x0000003F  // Voltage adjust mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_SRCR0,
+// SYSCTL_RCGC0, SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.
+//
+//*****************************************************************************
+#define SYSCTL_SET0_CAN2        0x04000000  // CAN 2 module
+#define SYSCTL_SET0_CAN1        0x02000000  // CAN 1 module
+#define SYSCTL_SET0_CAN0        0x01000000  // CAN 0 module
+#define SYSCTL_SET0_PWM         0x00100000  // PWM module
+#define SYSCTL_SET0_ADC         0x00010000  // ADC module
+#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00  // ADC speed mask
+#define SYSCTL_SET0_ADCSPD_125K 0x00000000  // 125Ksps ADC
+#define SYSCTL_SET0_ADCSPD_250K 0x00000100  // 250Ksps ADC
+#define SYSCTL_SET0_ADCSPD_500K 0x00000200  // 500Ksps ADC
+#define SYSCTL_SET0_ADCSPD_1M   0x00000300  // 1Msps ADC
+#define SYSCTL_SET0_HIB         0x00000040  // Hibernation module
+#define SYSCTL_SET0_WDOG        0x00000008  // Watchdog module
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_SRCR1,
+// SYSCTL_RCGC1, SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.
+//
+//*****************************************************************************
+#define SYSCTL_SET1_COMP2       0x04000000  // Analog comparator module 2
+#define SYSCTL_SET1_COMP1       0x02000000  // Analog comparator module 1
+#define SYSCTL_SET1_COMP0       0x01000000  // Analog comparator module 0
+#define SYSCTL_SET1_TIMER3      0x00080000  // Timer module 3
+#define SYSCTL_SET1_TIMER2      0x00040000  // Timer module 2
+#define SYSCTL_SET1_TIMER1      0x00020000  // Timer module 1
+#define SYSCTL_SET1_TIMER0      0x00010000  // Timer module 0
+#define SYSCTL_SET1_I2C1        0x00002000  // I2C module 1
+#define SYSCTL_SET1_I2C0        0x00001000  // I2C module 0
+#define SYSCTL_SET1_I2C         0x00001000  // I2C module
+#define SYSCTL_SET1_QEI1        0x00000200  // QEI module 1
+#define SYSCTL_SET1_QEI         0x00000100  // QEI module
+#define SYSCTL_SET1_QEI0        0x00000100  // QEI module 0
+#define SYSCTL_SET1_SSI1        0x00000020  // SSI module 1
+#define SYSCTL_SET1_SSI0        0x00000010  // SSI module 0
+#define SYSCTL_SET1_SSI         0x00000010  // SSI module
+#define SYSCTL_SET1_UART2       0x00000004  // UART module 2
+#define SYSCTL_SET1_UART1       0x00000002  // UART module 1
+#define SYSCTL_SET1_UART0       0x00000001  // UART module 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_SRCR2,
+// SYSCTL_RCGC2, SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.
+//
+//*****************************************************************************
+#define SYSCTL_SET2_ETH         0x50000000  // ETH module
+#define SYSCTL_SET2_GPIOH       0x00000080  // GPIO H module
+#define SYSCTL_SET2_GPIOG       0x00000040  // GPIO G module
+#define SYSCTL_SET2_GPIOF       0x00000020  // GPIO F module
+#define SYSCTL_SET2_GPIOE       0x00000010  // GPIO E module
+#define SYSCTL_SET2_GPIOD       0x00000008  // GPIO D module
+#define SYSCTL_SET2_GPIOC       0x00000004  // GPIO C module
+#define SYSCTL_SET2_GPIOB       0x00000002  // GPIO B module
+#define SYSCTL_SET2_GPIOA       0x00000001  // GIPO A module
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RIS,
+// SYSCTL_IMC, and SYSCTL_IMS registers.
+//
+//*****************************************************************************
+#define SYSCTL_INT_PLL_LOCK     0x00000040  // PLL lock interrupt
+#define SYSCTL_INT_CUR_LIMIT    0x00000020  // Current limit interrupt
+#define SYSCTL_INT_IOSC_FAIL    0x00000010  // Internal oscillator failure int
+#define SYSCTL_INT_MOSC_FAIL    0x00000008  // Main oscillator failure int
+#define SYSCTL_INT_POR          0x00000004  // Power on reset interrupt
+#define SYSCTL_INT_BOR          0x00000002  // Brown out interrupt
+#define SYSCTL_INT_PLL_FAIL     0x00000001  // PLL failure interrupt
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RESC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_WDOG        0x00000008  // Watchdog reset
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RCC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC_SYSDIV_MASK  0x07800000  // System clock divider
+#define SYSCTL_RCC_USE_SYSDIV   0x00400000  // Use sytem clock divider
+#define SYSCTL_RCC_USE_PWMDIV   0x00100000  // Use PWM clock divider
+#define SYSCTL_RCC_PWMDIV_MASK  0x000E0000  // PWM clock divider
+#define SYSCTL_RCC_OE           0x00001000  // PLL output enable
+#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140  // Using a 3.6864 MHz crystal
+#define SYSCTL_RCC_XTAL_4MHz    0x00000180  // Using a 4 MHz crystal
+#define SYSCTL_RCC_XTAL_MASK    0x000003C0  // Crystal attached to main osc
+#define SYSCTL_RCC_OSCSRC_MASK  0x00000030  // Oscillator input select
+#define SYSCTL_RCC_SYSDIV_SHIFT 23          // Shift to the SYSDIV field
+#define SYSCTL_RCC_PWMDIV_SHIFT 17          // Shift to the PWMDIV field
+#define SYSCTL_RCC_XTAL_SHIFT   6           // Shift to the XTAL field
+#define SYSCTL_RCC_OSCSRC_SHIFT 4           // Shift to the OSCSRC field
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_PLLCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLCFG_OD_MASK   0x0000C000  // Output divider
+#define SYSCTL_PLLCFG_F_MASK    0x00003FE0  // PLL multiplier
+#define SYSCTL_PLLCFG_R_MASK    0x0000001F  // Input predivider
+#define SYSCTL_PLLCFG_F_SHIFT   5
+#define SYSCTL_PLLCFG_R_SHIFT   0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RCC2
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000  // System clock divider
+#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070  // Oscillator input select
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_DSLPCLKCFG register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPCLKCFG_D_MSK 0x1F800000  // Deep sleep system clock override
+#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070  // Deep sleep oscillator override
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_CLKVCLR register.
+//
+//*****************************************************************************
+#define SYSCTL_CLKVCLR_CLR      0x00000001  // Clear clock verification fault
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_LDOARST register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOARST_ARST     0x00000001  // Allow LDO to reset device
+
+#endif
+
+#endif // __HW_SYSCTL_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_timer.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_timer.h
new file mode 100644
index 0000000..2036d54
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_timer.h
@@ -0,0 +1,407 @@
+//*****************************************************************************
+//
+// hw_timer.h - Defines and macros used when accessing the timer.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HW_TIMER_H__
+#define __HW_TIMER_H__
+
+//*****************************************************************************
+//
+// The following are defines for the timer register offsets.
+//
+//*****************************************************************************
+#define TIMER_O_CFG             0x00000000  // Configuration register
+#define TIMER_O_TAMR            0x00000004  // TimerA mode register
+#define TIMER_O_TBMR            0x00000008  // TimerB mode register
+#define TIMER_O_CTL             0x0000000C  // Control register
+#define TIMER_O_IMR             0x00000018  // Interrupt mask register
+#define TIMER_O_RIS             0x0000001C  // Interrupt status register
+#define TIMER_O_MIS             0x00000020  // Masked interrupt status reg.
+#define TIMER_O_ICR             0x00000024  // Interrupt clear register
+#define TIMER_O_TAILR           0x00000028  // TimerA interval load register
+#define TIMER_O_TBILR           0x0000002C  // TimerB interval load register
+#define TIMER_O_TAMATCHR        0x00000030  // TimerA match register
+#define TIMER_O_TBMATCHR        0x00000034  // TimerB match register
+#define TIMER_O_TAPR            0x00000038  // TimerA prescale register
+#define TIMER_O_TBPR            0x0000003C  // TimerB prescale register
+#define TIMER_O_TAPMR           0x00000040  // TimerA prescale match register
+#define TIMER_O_TBPMR           0x00000044  // TimerB prescale match register
+#define TIMER_O_TAR             0x00000048  // TimerA register
+#define TIMER_O_TBR             0x0000004C  // TimerB register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_CFG register.
+//
+//*****************************************************************************
+#define TIMER_CFG_M             0x00000007  // GPTM Configuration.
+#define TIMER_CFG_16_BIT        0x00000004  // Two 16 bit timers
+#define TIMER_CFG_32_BIT_RTC    0x00000001  // 32 bit RTC
+#define TIMER_CFG_32_BIT_TIMER  0x00000000  // 32 bit timer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_CTL register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBPWML        0x00004000  // TimerB PWM output level invert
+#define TIMER_CTL_TBOTE         0x00002000  // TimerB output trigger enable
+#define TIMER_CTL_TBEVENT_POS   0x00000000  // TimerB event mode - pos edge
+#define TIMER_CTL_TBEVENT_NEG   0x00000400  // TimerB event mode - neg edge
+#define TIMER_CTL_TBEVENT_BOTH  0x00000C00  // TimerB event mode - both edges
+#define TIMER_CTL_TBEVENT_M     0x00000C00  // GPTM TimerB Event Mode.
+#define TIMER_CTL_TBSTALL       0x00000200  // TimerB stall enable
+#define TIMER_CTL_TBEN          0x00000100  // TimerB enable
+#define TIMER_CTL_TAPWML        0x00000040  // TimerA PWM output level invert
+#define TIMER_CTL_TAOTE         0x00000020  // TimerA output trigger enable
+#define TIMER_CTL_RTCEN         0x00000010  // RTC counter enable
+#define TIMER_CTL_TAEVENT_M     0x0000000C  // GPTM TimerA Event Mode.
+#define TIMER_CTL_TAEVENT_POS   0x00000000  // TimerA event mode - pos edge
+#define TIMER_CTL_TAEVENT_NEG   0x00000004  // TimerA event mode - neg edge
+#define TIMER_CTL_TAEVENT_BOTH  0x0000000C  // TimerA event mode - both edges
+#define TIMER_CTL_TASTALL       0x00000002  // TimerA stall enable
+#define TIMER_CTL_TAEN          0x00000001  // TimerA enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_IMR register.
+//
+//*****************************************************************************
+#define TIMER_IMR_CBEIM         0x00000400  // CaptureB event interrupt mask
+#define TIMER_IMR_CBMIM         0x00000200  // CaptureB match interrupt mask
+#define TIMER_IMR_TBTOIM        0x00000100  // TimerB time out interrupt mask
+#define TIMER_IMR_RTCIM         0x00000008  // RTC interrupt mask
+#define TIMER_IMR_CAEIM         0x00000004  // CaptureA event interrupt mask
+#define TIMER_IMR_CAMIM         0x00000002  // CaptureA match interrupt mask
+#define TIMER_IMR_TATOIM        0x00000001  // TimerA time out interrupt mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_RIS register.
+//
+//*****************************************************************************
+#define TIMER_RIS_CBERIS        0x00000400  // CaptureB event raw int status
+#define TIMER_RIS_CBMRIS        0x00000200  // CaptureB match raw int status
+#define TIMER_RIS_TBTORIS       0x00000100  // TimerB time out raw int status
+#define TIMER_RIS_RTCRIS        0x00000008  // RTC raw int status
+#define TIMER_RIS_CAERIS        0x00000004  // CaptureA event raw int status
+#define TIMER_RIS_CAMRIS        0x00000002  // CaptureA match raw int status
+#define TIMER_RIS_TATORIS       0x00000001  // TimerA time out raw int status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_ICR register.
+//
+//*****************************************************************************
+#define TIMER_ICR_CBECINT       0x00000400  // CaptureB event interrupt clear
+#define TIMER_ICR_CBMCINT       0x00000200  // CaptureB match interrupt clear
+#define TIMER_ICR_TBTOCINT      0x00000100  // TimerB time out interrupt clear
+#define TIMER_ICR_RTCCINT       0x00000008  // RTC interrupt clear
+#define TIMER_ICR_CAECINT       0x00000004  // CaptureA event interrupt clear
+#define TIMER_ICR_CAMCINT       0x00000002  // CaptureA match interrupt clear
+#define TIMER_ICR_TATOCINT      0x00000001  // TimerA time out interrupt clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_TAILR register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_TAILRH_M    0xFFFF0000  // GPTM TimerA Interval Load
+                                            // Register High.
+#define TIMER_TAILR_TAILRL_M    0x0000FFFF  // GPTM TimerA Interval Load
+                                            // Register Low.
+#define TIMER_TAILR_TAILRH_S    16
+#define TIMER_TAILR_TAILRL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_TBILR register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_TBILRL_M    0x0000FFFF  // GPTM TimerB Interval Load
+                                            // Register.
+#define TIMER_TBILR_TBILRL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_TAMATCHR register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMRH_M  0xFFFF0000  // GPTM TimerA Match Register High.
+#define TIMER_TAMATCHR_TAMRL_M  0x0000FFFF  // GPTM TimerA Match Register Low.
+#define TIMER_TAMATCHR_TAMRH_S  16
+#define TIMER_TAMATCHR_TAMRL_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_TBMATCHR register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMRL_M  0x0000FFFF  // GPTM TimerB Match Register Low.
+#define TIMER_TBMATCHR_TBMRL_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_TAR register.
+//
+//*****************************************************************************
+#define TIMER_TAR_TARH_M        0xFFFF0000  // GPTM TimerA Register High.
+#define TIMER_TAR_TARL_M        0x0000FFFF  // GPTM TimerA Register Low.
+#define TIMER_TAR_TARH_S        16
+#define TIMER_TAR_TARL_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_TBR register.
+//
+//*****************************************************************************
+#define TIMER_TBR_TBRL_M        0x0000FFFF  // GPTM TimerB.
+#define TIMER_TBR_TBRL_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMR register.
+//
+//*****************************************************************************
+#define TIMER_TAMR_TAAMS        0x00000008  // GPTM TimerA Alternate Mode
+                                            // Select.
+#define TIMER_TAMR_TACMR        0x00000004  // GPTM TimerA Capture Mode.
+#define TIMER_TAMR_TAMR_M       0x00000003  // GPTM TimerA Mode.
+#define TIMER_TAMR_TAMR_1_SHOT  0x00000001  // One-Shot Timer mode.
+#define TIMER_TAMR_TAMR_PERIOD  0x00000002  // Periodic Timer mode.
+#define TIMER_TAMR_TAMR_CAP     0x00000003  // Capture mode.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMR register.
+//
+//*****************************************************************************
+#define TIMER_TBMR_TBAMS        0x00000008  // GPTM TimerB Alternate Mode
+                                            // Select.
+#define TIMER_TBMR_TBCMR        0x00000004  // GPTM TimerB Capture Mode.
+#define TIMER_TBMR_TBMR_M       0x00000003  // GPTM TimerB Mode.
+#define TIMER_TBMR_TBMR_1_SHOT  0x00000001  // One-Shot Timer mode.
+#define TIMER_TBMR_TBMR_PERIOD  0x00000002  // Periodic Timer mode.
+#define TIMER_TBMR_TBMR_CAP     0x00000003  // Capture mode.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_MIS register.
+//
+//*****************************************************************************
+#define TIMER_MIS_CBEMIS        0x00000400  // GPTM CaptureB Event Masked
+                                            // Interrupt.
+#define TIMER_MIS_CBMMIS        0x00000200  // GPTM CaptureB Match Masked
+                                            // Interrupt.
+#define TIMER_MIS_TBTOMIS       0x00000100  // GPTM TimerB Time-Out Masked
+                                            // Interrupt.
+#define TIMER_MIS_RTCMIS        0x00000008  // GPTM RTC Masked Interrupt.
+#define TIMER_MIS_CAEMIS        0x00000004  // GPTM CaptureA Event Masked
+                                            // Interrupt.
+#define TIMER_MIS_CAMMIS        0x00000002  // GPTM CaptureA Match Masked
+                                            // Interrupt.
+#define TIMER_MIS_TATOMIS       0x00000001  // GPTM TimerA Time-Out Masked
+                                            // Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPR register.
+//
+//*****************************************************************************
+#define TIMER_TAPR_TAPSR_M      0x000000FF  // GPTM TimerA Prescale.
+#define TIMER_TAPR_TAPSR_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPR register.
+//
+//*****************************************************************************
+#define TIMER_TBPR_TBPSR_M      0x000000FF  // GPTM TimerB Prescale.
+#define TIMER_TBPR_TBPSR_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPMR register.
+//
+//*****************************************************************************
+#define TIMER_TAPMR_TAPSMR_M    0x000000FF  // GPTM TimerA Prescale Match.
+#define TIMER_TAPMR_TAPSMR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPMR register.
+//
+//*****************************************************************************
+#define TIMER_TBPMR_TBPSMR_M    0x000000FF  // GPTM TimerB Prescale Match.
+#define TIMER_TBPMR_TBPSMR_S    0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values of the timer
+// registers.
+//
+//*****************************************************************************
+#define TIMER_RV_TAILR          0xFFFFFFFF  // TimerA interval load reg RV
+#define TIMER_RV_TAR            0xFFFFFFFF  // TimerA register RV
+#define TIMER_RV_TAMATCHR       0xFFFFFFFF  // TimerA match register RV
+#define TIMER_RV_TBILR          0x0000FFFF  // TimerB interval load reg RV
+#define TIMER_RV_TBMATCHR       0x0000FFFF  // TimerB match register RV
+#define TIMER_RV_TBR            0x0000FFFF  // TimerB register RV
+#define TIMER_RV_TAPR           0x00000000  // TimerA prescale register RV
+#define TIMER_RV_CFG            0x00000000  // Configuration register RV
+#define TIMER_RV_TBPMR          0x00000000  // TimerB prescale match regi RV
+#define TIMER_RV_TAPMR          0x00000000  // TimerA prescale match reg RV
+#define TIMER_RV_CTL            0x00000000  // Control register RV
+#define TIMER_RV_ICR            0x00000000  // Interrupt clear register RV
+#define TIMER_RV_TBMR           0x00000000  // TimerB mode register RV
+#define TIMER_RV_MIS            0x00000000  // Masked interrupt status reg RV
+#define TIMER_RV_RIS            0x00000000  // Interrupt status register RV
+#define TIMER_RV_TBPR           0x00000000  // TimerB prescale register RV
+#define TIMER_RV_IMR            0x00000000  // Interrupt mask register RV
+#define TIMER_RV_TAMR           0x00000000  // TimerA mode register RV
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_CFG
+// register.
+//
+//*****************************************************************************
+#define TIMER_CFG_CFG_MSK       0x00000007  // Configuration options mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TnMR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TNMR_TNAMS        0x00000008  // Alternate mode select
+#define TIMER_TNMR_TNCMR        0x00000004  // Capture mode - count or time
+#define TIMER_TNMR_TNTMR_MSK    0x00000003  // Timer mode mask
+#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001  // Mode - one shot
+#define TIMER_TNMR_TNTMR_PERIOD 0x00000002  // Mode - periodic
+#define TIMER_TNMR_TNTMR_CAP    0x00000003  // Mode - capture
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_CTL
+// register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBEVENT_MSK   0x00000C00  // TimerB event mode mask
+#define TIMER_CTL_TAEVENT_MSK   0x0000000C  // TimerA event mode mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_MIS
+// register.
+//
+//*****************************************************************************
+#define TIMER_RIS_CBEMIS        0x00000400  // CaptureB event masked int status
+#define TIMER_RIS_CBMMIS        0x00000200  // CaptureB match masked int status
+#define TIMER_RIS_TBTOMIS       0x00000100  // TimerB time out masked int stat
+#define TIMER_RIS_RTCMIS        0x00000008  // RTC masked int status
+#define TIMER_RIS_CAEMIS        0x00000004  // CaptureA event masked int status
+#define TIMER_RIS_CAMMIS        0x00000002  // CaptureA match masked int status
+#define TIMER_RIS_TATOMIS       0x00000001  // TimerA time out masked int stat
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TAILR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_TAILRH      0xFFFF0000  // TimerB load val in 32 bit mode
+#define TIMER_TAILR_TAILRL      0x0000FFFF  // TimerA interval load value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TBILR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_TBILRL      0x0000FFFF  // TimerB interval load value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// TIMER_TAMATCHR register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMRH    0xFFFF0000  // TimerB match val in 32 bit mode
+#define TIMER_TAMATCHR_TAMRL    0x0000FFFF  // TimerA match value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// TIMER_TBMATCHR register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMRL    0x0000FFFF  // TimerB match load value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TnPR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TNPR_TNPSR        0x000000FF  // TimerN prescale value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TnPMR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TNPMR_TNPSMR      0x000000FF  // TimerN prescale match value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TAR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAR_TARH          0xFFFF0000  // TimerB val in 32 bit mode
+#define TIMER_TAR_TARL          0x0000FFFF  // TimerA value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TBR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBR_TBRL          0x0000FFFF  // TimerB value
+
+#endif
+
+#endif // __HW_TIMER_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_types.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_types.h
new file mode 100644
index 0000000..11da8e4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_types.h
@@ -0,0 +1,153 @@
+//*****************************************************************************
+//
+// hw_types.h - Common types and macros.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HW_TYPES_H__
+#define __HW_TYPES_H__
+
+//*****************************************************************************
+//
+// Define a boolean type, and values for true and false.
+//
+//*****************************************************************************
+typedef unsigned char tBoolean;
+
+#ifndef true
+#define true 1
+#endif
+
+#ifndef false
+#define false 0
+#endif
+
+//*****************************************************************************
+//
+// Macros for hardware access, both direct and via the bit-band region.
+//
+//*****************************************************************************
+#define HWREG(x)                                                              \
+        (*((volatile unsigned long *)(x)))
+#define HWREGH(x)                                                             \
+        (*((volatile unsigned short *)(x)))
+#define HWREGB(x)                                                             \
+        (*((volatile unsigned char *)(x)))
+#define HWREGBITW(x, b)                                                       \
+        HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 |                \
+              (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITH(x, b)                                                       \
+        HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 |               \
+               (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITB(x, b)                                                       \
+        HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 |               \
+               (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+
+//*****************************************************************************
+//
+// Helper Macros for determining silicon revisions, etc.
+//
+// These macros will be used by Driverlib at "run-time" to create necessary
+// conditional code blocks that will allow a single version of the Driverlib
+// "binary" code to support multiple(all) Stellaris silicon revisions.
+//
+// It is expected that these macros will be used inside of a standard 'C'
+// conditional block of code, e.g.
+//
+//     if(CLASS_IS_SANDSTORM)
+//     {
+//         do some Sandstorm-class specific code here.
+//     }
+//
+// By default, these macros will be defined as run-time checks of the
+// appropriate register(s) to allow creation of run-time conditional code
+// blocks for a common DriverLib across the entire Stellaris family.
+//
+// However, if code-space optimization is required, these macros can be "hard-
+// coded" for a specific version of Stellaris silicon.  Many compilers will
+// then detect the "hard-coded" conditionals, and appropriately optimize the
+// code blocks, eliminating any "unreachable" code.  This would result in
+// a smaller Driverlib, thus producing a smaller final application size, but
+// at the cost of limiting the Driverlib binary to a specific Stellaris
+// silicon revision.
+//
+//*****************************************************************************
+#ifndef CLASS_IS_SANDSTORM
+#define CLASS_IS_SANDSTORM                                                    \
+        (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_M) == SYSCTL_DID0_VER_0) ||   \
+         ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+          (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_SANDSTORM)))
+#endif
+
+#ifndef CLASS_IS_FURY
+#define CLASS_IS_FURY                                                        \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+         (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FURY))
+#endif
+
+#ifndef CLASS_IS_DUSTDEVIL
+#define CLASS_IS_DUSTDEVIL                                                   \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+         (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_DUSTDEVIL))
+#endif
+
+#ifndef REVISION_IS_A0
+#define REVISION_IS_A0                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+         (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_A2
+#define REVISION_IS_A2                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+         (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2))
+#endif
+
+#ifndef REVISION_IS_C1
+#define REVISION_IS_C1                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+         (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_1))
+#endif
+
+#ifndef REVISION_IS_C2
+#define REVISION_IS_C2                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+         (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_2))
+#endif
+
+//*****************************************************************************
+//
+// Deprecated silicon class and revision detection macros.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define DEVICE_IS_SANDSTORM     CLASS_IS_SANDSTORM
+#define DEVICE_IS_FURY          CLASS_IS_FURY
+#define DEVICE_IS_REVA2         REVISION_IS_A2
+#define DEVICE_IS_REVC1         REVISION_IS_C1
+#define DEVICE_IS_REVC2         REVISION_IS_C2
+#endif
+
+#endif // __HW_TYPES_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_uart.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_uart.h
new file mode 100644
index 0000000..3c67a55
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_uart.h
@@ -0,0 +1,341 @@
+//*****************************************************************************
+//
+// hw_uart.h - Macros and defines used when accessing the UART hardware
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HW_UART_H__
+#define __HW_UART_H__
+
+//*****************************************************************************
+//
+// The following are defines for the UART Register offsets.
+//
+//*****************************************************************************
+#define UART_O_DR               0x00000000  // Data Register
+#define UART_O_RSR              0x00000004  // Receive Status Register (read)
+#define UART_O_ECR              0x00000004  // Error Clear Register (write)
+#define UART_O_FR               0x00000018  // Flag Register (read only)
+#define UART_O_ILPR             0x00000020  // UART IrDA Low-Power Register
+#define UART_O_IBRD             0x00000024  // Integer Baud Rate Divisor Reg
+#define UART_O_FBRD             0x00000028  // Fractional Baud Rate Divisor Reg
+#define UART_O_LCRH             0x0000002C  // UART Line Control
+#define UART_O_CTL              0x00000030  // Control Register
+#define UART_O_IFLS             0x00000034  // Interrupt FIFO Level Select Reg
+#define UART_O_IM               0x00000038  // Interrupt Mask Set/Clear Reg
+#define UART_O_RIS              0x0000003C  // Raw Interrupt Status Register
+#define UART_O_MIS              0x00000040  // Masked Interrupt Status Register
+#define UART_O_ICR              0x00000044  // Interrupt Clear Register
+#define UART_O_DMACTL           0x00000048  // UART DMA Control
+
+//*****************************************************************************
+//
+// The following are defines for the Data Register bits
+//
+//*****************************************************************************
+#define UART_DR_OE              0x00000800  // Overrun Error
+#define UART_DR_BE              0x00000400  // Break Error
+#define UART_DR_PE              0x00000200  // Parity Error
+#define UART_DR_FE              0x00000100  // Framing Error
+#define UART_DR_DATA_M          0x000000FF  // Data Transmitted or Received.
+#define UART_DR_DATA_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the Receive Status Register bits
+//
+//*****************************************************************************
+#define UART_RSR_OE             0x00000008  // Overrun Error
+#define UART_RSR_BE             0x00000004  // Break Error
+#define UART_RSR_PE             0x00000002  // Parity Error
+#define UART_RSR_FE             0x00000001  // Framing Error
+
+//*****************************************************************************
+//
+// The following are defines for the Flag Register bits
+//
+//*****************************************************************************
+#define UART_FR_TXFE            0x00000080  // TX FIFO Empty
+#define UART_FR_RXFF            0x00000040  // RX FIFO Full
+#define UART_FR_TXFF            0x00000020  // TX FIFO Full
+#define UART_FR_RXFE            0x00000010  // RX FIFO Empty
+#define UART_FR_BUSY            0x00000008  // UART Busy
+
+//*****************************************************************************
+//
+// The following are defines for the Integer baud-rate divisor
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_M      0x0000FFFF  // Integer Baud-Rate Divisor.
+#define UART_IBRD_DIVINT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the Fractional baud-rate divisor
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_M     0x0000003F  // Fractional Baud-Rate Divisor.
+#define UART_FBRD_DIVFRAC_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the Control Register bits
+//
+//*****************************************************************************
+#define UART_CTL_RXE            0x00000200  // Receive Enable
+#define UART_CTL_TXE            0x00000100  // Transmit Enable
+#define UART_CTL_LBE            0x00000080  // Loopback Enable
+#define UART_CTL_SIRLP          0x00000004  // SIR (IrDA) Low Power Enable
+#define UART_CTL_SIREN          0x00000002  // SIR (IrDA) Enable
+#define UART_CTL_UARTEN         0x00000001  // UART Enable
+
+//*****************************************************************************
+//
+// The following are defines for the Interrupt FIFO Level Select Register bits
+//
+//*****************************************************************************
+#define UART_IFLS_RX_M          0x00000038  // RX FIFO Level Interrupt Mask
+#define UART_IFLS_RX1_8         0x00000000  // 1/8 Full
+#define UART_IFLS_RX2_8         0x00000008  // 1/4 Full
+#define UART_IFLS_RX4_8         0x00000010  // 1/2 Full
+#define UART_IFLS_RX6_8         0x00000018  // 3/4 Full
+#define UART_IFLS_RX7_8         0x00000020  // 7/8 Full
+#define UART_IFLS_TX_M          0x00000007  // TX FIFO Level Interrupt Mask
+#define UART_IFLS_TX1_8         0x00000000  // 1/8 Full
+#define UART_IFLS_TX2_8         0x00000001  // 1/4 Full
+#define UART_IFLS_TX4_8         0x00000002  // 1/2 Full
+#define UART_IFLS_TX6_8         0x00000003  // 3/4 Full
+#define UART_IFLS_TX7_8         0x00000004  // 7/8 Full
+
+//*****************************************************************************
+//
+// The following are defines for the Interrupt Mask Set/Clear Register bits
+//
+//*****************************************************************************
+#define UART_IM_OEIM            0x00000400  // Overrun Error Interrupt Mask
+#define UART_IM_BEIM            0x00000200  // Break Error Interrupt Mask
+#define UART_IM_PEIM            0x00000100  // Parity Error Interrupt Mask
+#define UART_IM_FEIM            0x00000080  // Framing Error Interrupt Mask
+#define UART_IM_RTIM            0x00000040  // Receive Timeout Interrupt Mask
+#define UART_IM_TXIM            0x00000020  // Transmit Interrupt Mask
+#define UART_IM_RXIM            0x00000010  // Receive Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the Raw Interrupt Status Register
+//
+//*****************************************************************************
+#define UART_RIS_OERIS          0x00000400  // Overrun Error Interrupt Status
+#define UART_RIS_BERIS          0x00000200  // Break Error Interrupt Status
+#define UART_RIS_PERIS          0x00000100  // Parity Error Interrupt Status
+#define UART_RIS_FERIS          0x00000080  // Framing Error Interrupt Status
+#define UART_RIS_RTRIS          0x00000040  // Receive Timeout Interrupt Status
+#define UART_RIS_TXRIS          0x00000020  // Transmit Interrupt Status
+#define UART_RIS_RXRIS          0x00000010  // Receive Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the Masked Interrupt Status Register
+//
+//*****************************************************************************
+#define UART_MIS_OEMIS          0x00000400  // Overrun Error Interrupt Status
+#define UART_MIS_BEMIS          0x00000200  // Break Error Interrupt Status
+#define UART_MIS_PEMIS          0x00000100  // Parity Error Interrupt Status
+#define UART_MIS_FEMIS          0x00000080  // Framing Error Interrupt Status
+#define UART_MIS_RTMIS          0x00000040  // Receive Timeout Interrupt Status
+#define UART_MIS_TXMIS          0x00000020  // Transmit Interrupt Status
+#define UART_MIS_RXMIS          0x00000010  // Receive Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the Interrupt Clear Register bits
+//
+//*****************************************************************************
+#define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear
+#define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear
+#define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear
+#define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear
+#define UART_ICR_RTIC           0x00000040  // Receive Timeout Interrupt Clear
+#define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear
+#define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ECR register.
+//
+//*****************************************************************************
+#define UART_ECR_DATA_M         0x000000FF  // Error Clear.
+#define UART_ECR_DATA_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCRH register.
+//
+//*****************************************************************************
+#define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select.
+#define UART_LCRH_WLEN_M        0x00000060  // UART Word Length.
+#define UART_LCRH_WLEN_5        0x00000000  // 5 bits (default)
+#define UART_LCRH_WLEN_6        0x00000020  // 6 bits
+#define UART_LCRH_WLEN_7        0x00000040  // 7 bits
+#define UART_LCRH_WLEN_8        0x00000060  // 8 bits
+#define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs.
+#define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select.
+#define UART_LCRH_EPS           0x00000004  // UART Even Parity Select.
+#define UART_LCRH_PEN           0x00000002  // UART Parity Enable.
+#define UART_LCRH_BRK           0x00000001  // UART Send Break.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ILPR register.
+//
+//*****************************************************************************
+#define UART_ILPR_ILPDVSR_M     0x000000FF  // IrDA Low-Power Divisor.
+#define UART_ILPR_ILPDVSR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DMACTL register.
+//
+//*****************************************************************************
+#define UART_DMACTL_DMAERR      0x00000004  // DMA on Error.
+#define UART_DMACTL_TXDMAE      0x00000002  // Transmit DMA Enable.
+#define UART_DMACTL_RXDMAE      0x00000001  // Receive DMA Enable.
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the UART Register offsets.
+//
+//*****************************************************************************
+#define UART_O_LCR_H            0x0000002C  // Line Control Register, HIGH byte
+#define UART_O_PeriphID4        0x00000FD0
+#define UART_O_PeriphID5        0x00000FD4
+#define UART_O_PeriphID6        0x00000FD8
+#define UART_O_PeriphID7        0x00000FDC
+#define UART_O_PeriphID0        0x00000FE0
+#define UART_O_PeriphID1        0x00000FE4
+#define UART_O_PeriphID2        0x00000FE8
+#define UART_O_PeriphID3        0x00000FEC
+#define UART_O_PCellID0         0x00000FF0
+#define UART_O_PCellID1         0x00000FF4
+#define UART_O_PCellID2         0x00000FF8
+#define UART_O_PCellID3         0x00000FFC
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Data Register bits
+//
+//*****************************************************************************
+#define UART_DR_DATA_MASK       0x000000FF  // UART data
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Integer baud-rate divisor
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_MASK   0x0000FFFF  // Integer baud-rate divisor
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Fractional baud-rate divisor
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_MASK  0x0000003F  // Fractional baud-rate divisor
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Line Control Register High bits
+//
+//*****************************************************************************
+#define UART_LCR_H_SPS          0x00000080  // Stick Parity Select
+#define UART_LCR_H_WLEN         0x00000060  // Word length
+#define UART_LCR_H_WLEN_5       0x00000000  // 5 bit data
+#define UART_LCR_H_WLEN_6       0x00000020  // 6 bit data
+#define UART_LCR_H_WLEN_7       0x00000040  // 7 bit data
+#define UART_LCR_H_WLEN_8       0x00000060  // 8 bit data
+#define UART_LCR_H_FEN          0x00000010  // Enable FIFO
+#define UART_LCR_H_STP2         0x00000008  // Two Stop Bits Select
+#define UART_LCR_H_EPS          0x00000004  // Even Parity Select
+#define UART_LCR_H_PEN          0x00000002  // Parity Enable
+#define UART_LCR_H_BRK          0x00000001  // Send Break
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Interrupt FIFO Level Select
+// Register bits
+//
+//*****************************************************************************
+#define UART_IFLS_RX_MASK       0x00000038  // RX FIFO level mask
+#define UART_IFLS_TX_MASK       0x00000007  // TX FIFO level mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Interrupt Clear Register bits
+//
+//*****************************************************************************
+#define UART_RSR_ANY            (UART_RSR_OE | UART_RSR_BE | UART_RSR_PE | \
+                                 UART_RSR_FE)
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Reset Values for UART
+// Registers.
+//
+//*****************************************************************************
+#define UART_RV_CTL             0x00000300
+#define UART_RV_PCellID1        0x000000F0
+#define UART_RV_PCellID3        0x000000B1
+#define UART_RV_FR              0x00000090
+#define UART_RV_PeriphID2       0x00000018
+#define UART_RV_IFLS            0x00000012
+#define UART_RV_PeriphID0       0x00000011
+#define UART_RV_PCellID0        0x0000000D
+#define UART_RV_PCellID2        0x00000005
+#define UART_RV_PeriphID3       0x00000001
+#define UART_RV_PeriphID4       0x00000000
+#define UART_RV_LCR_H           0x00000000
+#define UART_RV_PeriphID6       0x00000000
+#define UART_RV_DR              0x00000000
+#define UART_RV_RSR             0x00000000
+#define UART_RV_ECR             0x00000000
+#define UART_RV_PeriphID5       0x00000000
+#define UART_RV_RIS             0x00000000
+#define UART_RV_FBRD            0x00000000
+#define UART_RV_IM              0x00000000
+#define UART_RV_MIS             0x00000000
+#define UART_RV_ICR             0x00000000
+#define UART_RV_PeriphID1       0x00000000
+#define UART_RV_PeriphID7       0x00000000
+#define UART_RV_IBRD            0x00000000
+
+#endif
+
+#endif // __HW_UART_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_udma.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_udma.h
new file mode 100644
index 0000000..46dab8b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_udma.h
@@ -0,0 +1,312 @@
+//*****************************************************************************
+//
+// hw_udma.h - Macros for use in accessing the UDMA registers.
+//
+// Copyright (c) 2007-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HW_UDMA_H__
+#define __HW_UDMA_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Micro Direct Memory Access (uDMA) offsets.
+//
+//*****************************************************************************
+#define UDMA_STAT               0x400FF000  // DMA Status
+#define UDMA_CFG                0x400FF004  // DMA Configuration
+#define UDMA_CTLBASE            0x400FF008  // DMA Channel Control Base Pointer
+#define UDMA_ALTBASE            0x400FF00C  // DMA Alternate Channel Control
+                                            // Base Pointer
+#define UDMA_WAITSTAT           0x400FF010  // DMA Channel Wait on Request
+                                            // Status
+#define UDMA_SWREQ              0x400FF014  // DMA Channel Software Request
+#define UDMA_USEBURSTSET        0x400FF018  // DMA Channel Useburst Set
+#define UDMA_USEBURSTCLR        0x400FF01C  // DMA Channel Useburst Clear
+#define UDMA_REQMASKSET         0x400FF020  // DMA Channel Request Mask Set
+#define UDMA_REQMASKCLR         0x400FF024  // DMA Channel Request Mask Clear
+#define UDMA_ENASET             0x400FF028  // DMA Channel Enable Set
+#define UDMA_ENACLR             0x400FF02C  // DMA Channel Enable Clear
+#define UDMA_ALTSET             0x400FF030  // DMA Channel Primary Alternate
+                                            // Set
+#define UDMA_ALTCLR             0x400FF034  // DMA Channel Primary Alternate
+                                            // Clear
+#define UDMA_PRIOSET            0x400FF038  // DMA Channel Priority Set
+#define UDMA_PRIOCLR            0x400FF03C  // DMA Channel Priority Clear
+#define UDMA_ERRCLR             0x400FF04C  // DMA Bus Error Clear
+
+//*****************************************************************************
+//
+// Micro Direct Memory Access (uDMA) offsets.
+//
+//*****************************************************************************
+#define UDMA_O_SRCENDP          0x00000000  // DMA Channel Source Address End
+                                            // Pointer
+#define UDMA_O_DSTENDP          0x00000004  // DMA Channel Destination Address
+                                            // End Pointer
+#define UDMA_O_CHCTL            0x00000008  // DMA Channel Control Word
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
+//
+//*****************************************************************************
+#define UDMA_SRCENDP_ADDR_M     0xFFFFFFFF  // Source Address End Pointer.
+#define UDMA_SRCENDP_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_STAT register.
+//
+//*****************************************************************************
+#define UDMA_STAT_DMACHANS_M    0x001F0000  // Available DMA Channels Minus 1.
+#define UDMA_STAT_STATE_M       0x000000F0  // Control State Machine State.
+#define UDMA_STAT_STATE_IDLE    0x00000000  // Idle
+#define UDMA_STAT_STATE_RD_CTRL 0x00000010  // Reading channel controller data
+#define UDMA_STAT_STATE_RD_SRCENDP \
+                                0x00000020  // Reading source end pointer
+#define UDMA_STAT_STATE_RD_DSTENDP \
+                                0x00000030  // Reading destination end pointer
+#define UDMA_STAT_STATE_RD_SRCDAT \
+                                0x00000040  // Reading source data
+#define UDMA_STAT_STATE_WR_DSTDAT \
+                                0x00000050  // Writing destination data
+#define UDMA_STAT_STATE_WAIT    0x00000060  // Waiting for DMA request to clear
+#define UDMA_STAT_STATE_WR_CTRL 0x00000070  // Writing channel controller data
+#define UDMA_STAT_STATE_STALL   0x00000080  // Stalled
+#define UDMA_STAT_STATE_DONE    0x00000090  // Done
+#define UDMA_STAT_STATE_UNDEF   0x000000A0  // Undefined
+#define UDMA_STAT_MASTEN        0x00000001  // Master Enable.
+#define UDMA_STAT_DMACHANS_S    16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
+//
+//*****************************************************************************
+#define UDMA_DSTENDP_ADDR_M     0xFFFFFFFF  // Destination Address End Pointer.
+#define UDMA_DSTENDP_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CFG register.
+//
+//*****************************************************************************
+#define UDMA_CFG_MASTEN         0x00000001  // Controller Master Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CTLBASE register.
+//
+//*****************************************************************************
+#define UDMA_CTLBASE_ADDR_M     0xFFFFFC00  // Channel Control Base Address.
+#define UDMA_CTLBASE_ADDR_S     10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_CHCTL register.
+//
+//*****************************************************************************
+#define UDMA_CHCTL_DSTINC_M     0xC0000000  // Destination Address Increment.
+#define UDMA_CHCTL_DSTINC_8     0x00000000  // Byte
+#define UDMA_CHCTL_DSTINC_16    0x40000000  // Half-word
+#define UDMA_CHCTL_DSTINC_32    0x80000000  // Word
+#define UDMA_CHCTL_DSTINC_NONE  0xC0000000  // No increment
+#define UDMA_CHCTL_DSTSIZE_M    0x30000000  // Destination Data Size.
+#define UDMA_CHCTL_DSTSIZE_8    0x00000000  // Byte
+#define UDMA_CHCTL_DSTSIZE_16   0x10000000  // Half-word
+#define UDMA_CHCTL_DSTSIZE_32   0x20000000  // Word
+#define UDMA_CHCTL_SRCINC_M     0x0C000000  // Source Address Increment.
+#define UDMA_CHCTL_SRCINC_8     0x00000000  // Byte
+#define UDMA_CHCTL_SRCINC_16    0x04000000  // Half-word
+#define UDMA_CHCTL_SRCINC_32    0x08000000  // Word
+#define UDMA_CHCTL_SRCINC_NONE  0x0C000000  // No increment
+#define UDMA_CHCTL_SRCSIZE_M    0x03000000  // Source Data Size.
+#define UDMA_CHCTL_SRCSIZE_8    0x00000000  // Byte
+#define UDMA_CHCTL_SRCSIZE_16   0x01000000  // Half-word
+#define UDMA_CHCTL_SRCSIZE_32   0x02000000  // Word
+#define UDMA_CHCTL_ARBSIZE_M    0x0003C000  // Arbitration Size.
+#define UDMA_CHCTL_ARBSIZE_1    0x00000000  // 1 Transfer
+#define UDMA_CHCTL_ARBSIZE_2    0x00004000  // 2 Transfers
+#define UDMA_CHCTL_ARBSIZE_4    0x00008000  // 4 Transfers
+#define UDMA_CHCTL_ARBSIZE_8    0x0000C000  // 8 Transfers
+#define UDMA_CHCTL_ARBSIZE_16   0x00010000  // 16 Transfers
+#define UDMA_CHCTL_ARBSIZE_32   0x00014000  // 32 Transfers
+#define UDMA_CHCTL_ARBSIZE_64   0x00018000  // 64 Transfers
+#define UDMA_CHCTL_ARBSIZE_128  0x0001C000  // 128 Transfers
+#define UDMA_CHCTL_ARBSIZE_256  0x00020000  // 256 Transfers
+#define UDMA_CHCTL_ARBSIZE_512  0x00024000  // 512 Transfers
+#define UDMA_CHCTL_ARBSIZE_1024 0x00028000  // 1024 Transfers
+#define UDMA_CHCTL_XFERSIZE_M   0x00003FF0  // Transfer Size (minus 1).
+#define UDMA_CHCTL_NXTUSEBURST  0x00000008  // Next Useburst.
+#define UDMA_CHCTL_XFERMODE_M   0x00000007  // DMA Transfer Mode.
+#define UDMA_CHCTL_XFERMODE_STOP \
+                                0x00000000  // Stop
+#define UDMA_CHCTL_XFERMODE_BASIC \
+                                0x00000001  // Basic
+#define UDMA_CHCTL_XFERMODE_AUTO \
+                                0x00000002  // Auto-Request
+#define UDMA_CHCTL_XFERMODE_PINGPONG \
+                                0x00000003  // Ping-Pong
+#define UDMA_CHCTL_XFERMODE_MEM_SG \
+                                0x00000004  // Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_MEM_SGA \
+                                0x00000005  // Alternate Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SG \
+                                0x00000006  // Peripheral Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SGA \
+                                0x00000007  // Alternate Peripheral
+                                            // Scatter-Gather
+#define UDMA_CHCTL_XFERSIZE_S   4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTBASE register.
+//
+//*****************************************************************************
+#define UDMA_ALTBASE_ADDR_M     0xFFFFFFFF  // Alternate Channel Address
+                                            // Pointer.
+#define UDMA_ALTBASE_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_WAITSTAT register.
+//
+//*****************************************************************************
+#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF  // Channel [n] Wait Status.
+#define UDMA_WAITSTAT_WAITREQ_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_SWREQ register.
+//
+//*****************************************************************************
+#define UDMA_SWREQ_M            0xFFFFFFFF  // Channel [n] Software Request.
+#define UDMA_SWREQ_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTSET_SET_M  0xFFFFFFFF  // Channel [n] Useburst Set.
+#define UDMA_USEBURSTSET_SET__0 0x00000000  // No Effect
+#define UDMA_USEBURSTSET_SET__1 0x00000001  // Burst Only
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTCLR_CLR_M  0xFFFFFFFF  // Channel [n] Useburst Clear.
+#define UDMA_USEBURSTCLR_CLR__0 0x00000000  // No Effect
+#define UDMA_USEBURSTCLR_CLR__1 0x00000001  // Single and Burst
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKSET_SET_M   0xFFFFFFFF  // Channel [n] Request Mask Set.
+#define UDMA_REQMASKSET_SET__0  0x00000000  // No Effect
+#define UDMA_REQMASKSET_SET__1  0x00000001  // Masked
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKCLR_CLR_M   0xFFFFFFFF  // Channel [n] Request Mask Clear.
+#define UDMA_REQMASKCLR_CLR__0  0x00000000  // No Effect
+#define UDMA_REQMASKCLR_CLR__1  0x00000001  // Clear Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENASET register.
+//
+//*****************************************************************************
+#define UDMA_ENASET_SET_M       0xFFFFFFFF  // Channel [n] Enable Set.
+#define UDMA_ENASET_SET__0      0x00000000  // Disabled
+#define UDMA_ENASET_SET__1      0x00000001  // Enabled
+#define UDMA_ENASET_CHENSET_M   0xFFFFFFFF  // Channel [n] Enable Set.
+#define UDMA_ENASET_CHENSET__0  0x00000000  // No Effect
+#define UDMA_ENASET_CHENSET__1  0x00000001  // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENACLR register.
+//
+//*****************************************************************************
+#define UDMA_ENACLR_CLR_M       0xFFFFFFFF  // Clear Channel [n] Enable.
+#define UDMA_ENACLR_CLR__0      0x00000000  // No Effect
+#define UDMA_ENACLR_CLR__1      0x00000001  // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTSET register.
+//
+//*****************************************************************************
+#define UDMA_ALTSET_SET_M       0xFFFFFFFF  // Channel [n] Alternate Set.
+#define UDMA_ALTSET_SET__0      0x00000000  // No Effect
+#define UDMA_ALTSET_SET__1      0x00000001  // Alternate
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTCLR register.
+//
+//*****************************************************************************
+#define UDMA_ALTCLR_CLR_M       0xFFFFFFFF  // Channel [n] Alternate Clear.
+#define UDMA_ALTCLR_CLR__0      0x00000000  // No Effect
+#define UDMA_ALTCLR_CLR__1      0x00000001  // Primary
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOSET register.
+//
+//*****************************************************************************
+#define UDMA_PRIOSET_SET_M      0xFFFFFFFF  // Channel [n] Priority Set.
+#define UDMA_PRIOSET_SET__0     0x00000000  // No Effect
+#define UDMA_PRIOSET_SET__1     0x00000001  // High Priority
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOCLR register.
+//
+//*****************************************************************************
+#define UDMA_PRIOCLR_CLR_M      0xFFFFFFFF  // Channel [n] Priority Clear.
+#define UDMA_PRIOCLR_CLR__0     0x00000000  // No Effect
+#define UDMA_PRIOCLR_CLR__1     0x00000001  // Default Priority
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ERRCLR register.
+//
+//*****************************************************************************
+#define UDMA_ERRCLR_ERRCLR      0x00000001  // DMA Bus Error Status.
+
+#endif // __HW_UDMA_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_usb.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_usb.h
new file mode 100644
index 0000000..d6b91cd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_usb.h
@@ -0,0 +1,1309 @@
+//*****************************************************************************
+//
+// hw_usb.h - Macros for use in accessing the USB registers.
+//
+// Copyright (c) 2007-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HW_USB_H__
+#define __HW_USB_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Univeral Serial Bus (USB) Controller
+// offsets.
+//
+//*****************************************************************************
+#define USB_O_FADDR             0x00000000  // USB Device Functional Address
+#define USB_O_POWER             0x00000001  // USB Power
+#define USB_O_TXIS              0x00000002  // USB Transmit Interrupt Status
+#define USB_O_RXIS              0x00000004  // USB Receive Interrupt Status
+#define USB_O_TXIE              0x00000006  // USB Transmit Interrupt Enable
+#define USB_O_RXIE              0x00000008  // USB Receive Interrupt Enable
+#define USB_O_IS                0x0000000A  // USB General Interrupt Status
+#define USB_O_IE                0x0000000B  // USB Interrupt Enable
+#define USB_O_FRAME             0x0000000C  // USB Frame Value
+#define USB_O_EPIDX             0x0000000E  // USB Endpoint Index
+#define USB_O_TEST              0x0000000F  // USB Test Mode
+#define USB_O_FIFO0             0x00000020  // USB FIFO Endpoint 0
+#define USB_O_FIFO1             0x00000024  // USB FIFO Endpoint 1
+#define USB_O_FIFO2             0x00000028  // USB FIFO Endpoint 2
+#define USB_O_FIFO3             0x0000002C  // USB FIFO Endpoint 3
+#define USB_O_DEVCTL            0x00000060  // USB Device Control
+#define USB_O_TXFIFOSZ          0x00000062  // USB Transmit Dynamic FIFO Sizing
+#define USB_O_RXFIFOSZ          0x00000063  // USB Receive Dynamic FIFO Sizing
+#define USB_O_TXFIFOADD         0x00000064  // USB Transmit FIFO Start Address
+#define USB_O_RXFIFOADD         0x00000066  // USB Receive FIFO Start Address
+#define USB_O_CONTIM            0x0000007A  // USB Connect Timing
+#define USB_O_VPLEN             0x0000007B  // USB OTG VBus Pulse Timing
+#define USB_O_FSEOF             0x0000007D  // USB Full-Speed Last Transaction
+                                            // to End of Frame Timing
+#define USB_O_LSEOF             0x0000007E  // USB Low-Speed Last Transaction
+                                            // to End of Frame Timing
+#define USB_O_TXFUNCADDR0       0x00000080  // USB Transmit Functional Address
+                                            // Endpoint 0
+#define USB_O_TXHUBADDR0        0x00000082  // USB Transmit Hub Address
+                                            // Endpoint 0
+#define USB_O_TXHUBPORT0        0x00000083  // USB Transmit Hub Port Endpoint 0
+#define USB_O_TXFUNCADDR1       0x00000088  // USB Transmit Functional Address
+                                            // Endpoint 1
+#define USB_O_TXHUBADDR1        0x0000008A  // USB Transmit Hub Address
+                                            // Endpoint 1
+#define USB_O_TXHUBPORT1        0x0000008B  // USB Transmit Hub Port Endpoint 1
+#define USB_O_RXFUNCADDR1       0x0000008C  // USB Receive Functional Address
+                                            // Endpoint 1
+#define USB_O_RXHUBADDR1        0x0000008E  // USB Receive Hub Address Endpoint
+                                            // 1
+#define USB_O_RXHUBPORT1        0x0000008F  // USB Receive Hub Port Endpoint 1
+#define USB_O_TXFUNCADDR2       0x00000090  // USB Transmit Functional Address
+                                            // Endpoint 2
+#define USB_O_TXHUBADDR2        0x00000092  // USB Transmit Hub Address
+                                            // Endpoint 2
+#define USB_O_TXHUBPORT2        0x00000093  // USB Transmit Hub Port Endpoint 2
+#define USB_O_RXFUNCADDR2       0x00000094  // USB Receive Functional Address
+                                            // Endpoint 2
+#define USB_O_RXHUBADDR2        0x00000096  // USB Receive Hub Address Endpoint
+                                            // 2
+#define USB_O_RXHUBPORT2        0x00000097  // USB Receive Hub Port Endpoint 2
+#define USB_O_TXFUNCADDR3       0x00000098  // USB Transmit Functional Address
+                                            // Endpoint 3
+#define USB_O_TXHUBADDR3        0x0000009A  // USB Transmit Hub Address
+                                            // Endpoint 3
+#define USB_O_TXHUBPORT3        0x0000009B  // USB Transmit Hub Port Endpoint 3
+#define USB_O_RXFUNCADDR3       0x0000009C  // USB Receive Functional Address
+                                            // Endpoint 3
+#define USB_O_RXHUBADDR3        0x0000009E  // USB Receive Hub Address Endpoint
+                                            // 3
+#define USB_O_RXHUBPORT3        0x0000009F  // USB Receive Hub Port Endpoint 3
+#define USB_O_CSRL0             0x00000102  // USB Control and Status Endpoint
+                                            // 0 Low
+#define USB_O_CSRH0             0x00000103  // USB Control and Status Endpoint
+                                            // 0 High
+#define USB_O_COUNT0            0x00000108  // USB Receive Byte Count Endpoint
+                                            // 0
+#define USB_O_TYPE0             0x0000010A  // USB Type Endpoint 0
+#define USB_O_NAKLMT            0x0000010B  // USB NAK Limit
+#define USB_O_TXMAXP1           0x00000110  // USB Maximum Transmit Data
+                                            // Endpoint 1
+#define USB_O_TXCSRL1           0x00000112  // USB Transmit Control and Status
+                                            // Endpoint 1 Low
+#define USB_O_TXCSRH1           0x00000113  // USB Transmit Control and Status
+                                            // Endpoint 1 High
+#define USB_O_RXMAXP1           0x00000114  // USB Maximum Receive Data
+                                            // Endpoint 1
+#define USB_O_RXCSRL1           0x00000116  // USB Receive Control and Status
+                                            // Endpoint 1 Low
+#define USB_O_RXCSRH1           0x00000117  // USB Receive Control and Status
+                                            // Endpoint 1 High
+#define USB_O_RXCOUNT1          0x00000118  // USB Receive Byte Count Endpoint
+                                            // 1
+#define USB_O_TXTYPE1           0x0000011A  // USB Host Transmit Configure Type
+                                            // Endpoint 1
+#define USB_O_TXINTERVAL1       0x0000011B  // USB Host Transmit Interval
+                                            // Endpoint 1
+#define USB_O_RXTYPE1           0x0000011C  // USB Host Configure Receive Type
+                                            // Endpoint 1
+#define USB_O_RXINTERVAL1       0x0000011D  // USB Host Receive Polling
+                                            // Interval Endpoint 1
+#define USB_O_TXMAXP2           0x00000120  // USB Maximum Transmit Data
+                                            // Endpoint 2
+#define USB_O_TXCSRL2           0x00000122  // USB Transmit Control and Status
+                                            // Endpoint 2 Low
+#define USB_O_TXCSRH2           0x00000123  // USB Transmit Control and Status
+                                            // Endpoint 2 High
+#define USB_O_RXMAXP2           0x00000124  // USB Maximum Receive Data
+                                            // Endpoint 2
+#define USB_O_RXCSRL2           0x00000126  // USB Receive Control and Status
+                                            // Endpoint 2 Low
+#define USB_O_RXCSRH2           0x00000127  // USB Receive Control and Status
+                                            // Endpoint 2 High
+#define USB_O_RXCOUNT2          0x00000128  // USB Receive Byte Count Endpoint
+                                            // 2
+#define USB_O_TXTYPE2           0x0000012A  // USB Host Transmit Configure Type
+                                            // Endpoint 2
+#define USB_O_TXINTERVAL2       0x0000012B  // USB Host Transmit Interval
+                                            // Endpoint 2
+#define USB_O_RXTYPE2           0x0000012C  // USB Host Configure Receive Type
+                                            // Endpoint 2
+#define USB_O_RXINTERVAL2       0x0000012D  // USB Host Receive Polling
+                                            // Interval Endpoint 2
+#define USB_O_TXMAXP3           0x00000130  // USB Maximum Transmit Data
+                                            // Endpoint 3
+#define USB_O_TXCSRL3           0x00000132  // USB Transmit Control and Status
+                                            // Endpoint 3 Low
+#define USB_O_TXCSRH3           0x00000133  // USB Transmit Control and Status
+                                            // Endpoint 3 High
+#define USB_O_RXMAXP3           0x00000134  // USB Maximum Receive Data
+                                            // Endpoint 3
+#define USB_O_RXCSRL3           0x00000136  // USB Receive Control and Status
+                                            // Endpoint 3 Low
+#define USB_O_RXCSRH3           0x00000137  // USB Receive Control and Status
+                                            // Endpoint 3 High
+#define USB_O_RXCOUNT3          0x00000138  // USB Receive Byte Count Endpoint
+                                            // 3
+#define USB_O_TXTYPE3           0x0000013A  // USB Host Transmit Configure Type
+                                            // Endpoint 3
+#define USB_O_TXINTERVAL3       0x0000013B  // USB Host Transmit Interval
+                                            // Endpoint 3
+#define USB_O_RXTYPE3           0x0000013C  // USB Host Configure Receive Type
+                                            // Endpoint 3
+#define USB_O_RXINTERVAL3       0x0000013D  // USB Host Receive Polling
+                                            // Interval Endpoint 3
+#define USB_O_RQPKTCOUNT1       0x00000304  // USB Request Packet Count in
+                                            // Block Transfer Endpoint 1
+#define USB_O_RQPKTCOUNT2       0x00000308  // USB Request Packet Count in
+                                            // Block Transfer Endpoint 2
+#define USB_O_RQPKTCOUNT3       0x0000030C  // USB Request Packet Count in
+                                            // Block Transfer Endpoint 3
+#define USB_O_RXDPKTBUFDIS      0x00000340  // USB Receive Double Packet Buffer
+                                            // Disable
+#define USB_O_TXDPKTBUFDIS      0x00000342  // USB Transmit Double Packet
+                                            // Buffer Disable
+#define USB_O_EPC               0x00000400  // USB External Power Control
+#define USB_O_EPCRIS            0x00000404  // USB External Power Control Raw
+                                            // Interrupt Status
+#define USB_O_EPCIM             0x00000408  // USB External Power Control
+                                            // Interrupt Mask
+#define USB_O_EPCISC            0x0000040C  // USB External Power Control
+                                            // Interrupt Status and Clear
+#define USB_O_DRRIS             0x00000410  // USB Device Resume Raw Interrupt
+                                            // Status
+#define USB_O_DRIM              0x00000414  // USB Device Resume Interrupt Mask
+#define USB_O_DRISC             0x00000418  // USB Device Resume Interrupt
+                                            // Status and Clear
+#define USB_O_GPCS              0x0000041C  // USB General-Purpose Control and
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FADDR register.
+//
+//*****************************************************************************
+#define USB_FADDR_M             0x0000007F  // Function Address.
+#define USB_FADDR_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_POWER register.
+//
+//*****************************************************************************
+#define USB_POWER_ISOUP         0x00000080  // ISO Update.
+#define USB_POWER_SOFTCONN      0x00000040  // Soft Connect/Disconnect.
+#define USB_POWER_RESET         0x00000008  // Reset.
+#define USB_POWER_RESUME        0x00000004  // Resume Signaling.
+#define USB_POWER_SUSPEND       0x00000002  // Suspend Mode.
+#define USB_POWER_PWRDNPHY      0x00000001  // Power Down PHY.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIS register.
+//
+//*****************************************************************************
+#define USB_TXIS_EP3            0x00000008  // TX Endpoint 3 Interrupt.
+#define USB_TXIS_EP2            0x00000004  // TX Endpoint 2 Interrupt.
+#define USB_TXIS_EP1            0x00000002  // TX Endpoint 1 Interrupt.
+#define USB_TXIS_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIS register.
+//
+//*****************************************************************************
+#define USB_RXIS_EP3            0x00000008  // RX Endpoint 3 Interrupt.
+#define USB_RXIS_EP2            0x00000004  // RX Endpoint 2 Interrupt.
+#define USB_RXIS_EP1            0x00000002  // RX Endpoint 1 Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIE register.
+//
+//*****************************************************************************
+#define USB_TXIE_EP3            0x00000008  // TX Endpoint 3 Interrupt Enable.
+#define USB_TXIE_EP2            0x00000004  // TX Endpoint 2 Interrupt Enable.
+#define USB_TXIE_EP1            0x00000002  // TX Endpoint 1 Interrupt Enable.
+#define USB_TXIE_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt
+                                            // Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIE register.
+//
+//*****************************************************************************
+#define USB_RXIE_EP3            0x00000008  // RX Endpoint 3 Interrupt Enable.
+#define USB_RXIE_EP2            0x00000004  // RX Endpoint 2 Interrupt Enable.
+#define USB_RXIE_EP1            0x00000002  // RX Endpoint 1 Interrupt Enable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IS register.
+//
+//*****************************************************************************
+#define USB_IS_VBUSERR          0x00000080  // VBus Error.
+#define USB_IS_SESREQ           0x00000040  // Session Request.
+#define USB_IS_DISCON           0x00000020  // Session Disconnect.
+#define USB_IS_CONN             0x00000010  // Session Connect.
+#define USB_IS_SOF              0x00000008  // Start of Frame.
+#define USB_IS_BABBLE           0x00000004  // Babble Detected.
+#define USB_IS_RESET            0x00000004  // Reset Signal Detected.
+#define USB_IS_RESUME           0x00000002  // Resume Signal Detected.
+#define USB_IS_SUSPEND          0x00000001  // Suspend Signal Detected.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IE register.
+//
+//*****************************************************************************
+#define USB_IE_VBUSERR          0x00000080  // Enable VBUS Error Interrupt.
+#define USB_IE_SESREQ           0x00000040  // Enable Session Request
+                                            // Interrupt.
+#define USB_IE_DISCON           0x00000020  // Enable Disconnect Interrupt.
+#define USB_IE_CONN             0x00000010  // Enable Connect Interrupt.
+#define USB_IE_SOF              0x00000008  // Enable Start-of-Frame Interrupt.
+#define USB_IE_BABBLE           0x00000004  // Enable Babble Interrupt.
+#define USB_IE_RESET            0x00000004  // Enable Reset Interrupt.
+#define USB_IE_RESUME           0x00000002  // Enable Resume Interrupt.
+#define USB_IE_SUSPND           0x00000001  // Enable Suspend Interrupt.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FRAME register.
+//
+//*****************************************************************************
+#define USB_FRAME_M             0x000007FF  // Frame Number.
+#define USB_FRAME_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPIDX register.
+//
+//*****************************************************************************
+#define USB_EPIDX_EPIDX_M       0x0000000F  // Endpoint Index.
+#define USB_EPIDX_EPIDX_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TEST register.
+//
+//*****************************************************************************
+#define USB_TEST_FORCEH         0x00000080  // Force Host Mode.
+#define USB_TEST_FIFOACC        0x00000040  // FIFO Access.
+#define USB_TEST_FORCEFS        0x00000020  // Force Full Speed.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO0 register.
+//
+//*****************************************************************************
+#define USB_FIFO0_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO0_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO1 register.
+//
+//*****************************************************************************
+#define USB_FIFO1_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO1_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO2 register.
+//
+//*****************************************************************************
+#define USB_FIFO2_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO2_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO3 register.
+//
+//*****************************************************************************
+#define USB_FIFO3_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO3_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DEVCTL register.
+//
+//*****************************************************************************
+#define USB_DEVCTL_DEV          0x00000080  // Device Mode.
+#define USB_DEVCTL_FSDEV        0x00000040  // Full-Speed Device Detected.
+#define USB_DEVCTL_LSDEV        0x00000020  // Low-Speed Device Detected.
+#define USB_DEVCTL_VBUS_M       0x00000018  // VBus Level.
+#define USB_DEVCTL_VBUS_NONE    0x00000000  // Below SessionEnd
+#define USB_DEVCTL_VBUS_SEND    0x00000008  // Above SessionEnd, below AValid
+#define USB_DEVCTL_VBUS_AVALID  0x00000010  // Above AValid, below VBusValid
+#define USB_DEVCTL_VBUS_VALID   0x00000018  // Above VBusValid
+#define USB_DEVCTL_HOST         0x00000004  // Host Mode.
+#define USB_DEVCTL_HOSTREQ      0x00000002  // Host Request.
+#define USB_DEVCTL_SESSION      0x00000001  // Session Start/End.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_TXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support.
+#define USB_TXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size.
+#define USB_TXFIFOSZ_SIZE_8     0x00000000  // 8
+#define USB_TXFIFOSZ_SIZE_16    0x00000001  // 16
+#define USB_TXFIFOSZ_SIZE_32    0x00000002  // 32
+#define USB_TXFIFOSZ_SIZE_64    0x00000003  // 64
+#define USB_TXFIFOSZ_SIZE_128   0x00000004  // 128
+#define USB_TXFIFOSZ_SIZE_256   0x00000005  // 256
+#define USB_TXFIFOSZ_SIZE_512   0x00000006  // 512
+#define USB_TXFIFOSZ_SIZE_1024  0x00000007  // 1024
+#define USB_TXFIFOSZ_SIZE_2048  0x00000008  // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_RXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support.
+#define USB_RXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size.
+#define USB_RXFIFOSZ_SIZE_8     0x00000000  // 8
+#define USB_RXFIFOSZ_SIZE_16    0x00000001  // 16
+#define USB_RXFIFOSZ_SIZE_32    0x00000002  // 32
+#define USB_RXFIFOSZ_SIZE_64    0x00000003  // 64
+#define USB_RXFIFOSZ_SIZE_128   0x00000004  // 128
+#define USB_RXFIFOSZ_SIZE_256   0x00000005  // 256
+#define USB_RXFIFOSZ_SIZE_512   0x00000006  // 512
+#define USB_RXFIFOSZ_SIZE_1024  0x00000007  // 1024
+#define USB_RXFIFOSZ_SIZE_2048  0x00000008  // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_TXFIFOADD_ADDR_M    0x00001FFF  // Transmit/Receive Start Address.
+#define USB_TXFIFOADD_ADDR_0    0x00000000  // 0
+#define USB_TXFIFOADD_ADDR_8    0x00000001  // 8
+#define USB_TXFIFOADD_ADDR_16   0x00000002  // 16
+#define USB_TXFIFOADD_ADDR_32   0x00000003  // 32
+#define USB_TXFIFOADD_ADDR_64   0x00000004  // 64
+#define USB_TXFIFOADD_ADDR_128  0x00000005  // 128
+#define USB_TXFIFOADD_ADDR_256  0x00000006  // 256
+#define USB_TXFIFOADD_ADDR_512  0x00000007  // 512
+#define USB_TXFIFOADD_ADDR_1024 0x00000008  // 1024
+#define USB_TXFIFOADD_ADDR_2048 0x00000009  // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_RXFIFOADD_ADDR_M    0x00001FFF  // Transmit/Receive Start Address.
+#define USB_RXFIFOADD_ADDR_0    0x00000000  // 0
+#define USB_RXFIFOADD_ADDR_8    0x00000001  // 8
+#define USB_RXFIFOADD_ADDR_16   0x00000002  // 16
+#define USB_RXFIFOADD_ADDR_32   0x00000003  // 32
+#define USB_RXFIFOADD_ADDR_64   0x00000004  // 64
+#define USB_RXFIFOADD_ADDR_128  0x00000005  // 128
+#define USB_RXFIFOADD_ADDR_256  0x00000006  // 256
+#define USB_RXFIFOADD_ADDR_512  0x00000007  // 512
+#define USB_RXFIFOADD_ADDR_1024 0x00000008  // 1024
+#define USB_RXFIFOADD_ADDR_2048 0x00000009  // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CONTIM register.
+//
+//*****************************************************************************
+#define USB_CONTIM_WTCON_M      0x000000F0  // Connect Wait.
+#define USB_CONTIM_WTID_M       0x0000000F  // Wait ID.
+#define USB_CONTIM_WTCON_S      4
+#define USB_CONTIM_WTID_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FSEOF register.
+//
+//*****************************************************************************
+#define USB_FSEOF_FSEOFG_M      0x000000FF  // Full-Speed End-of-Frame Gap.
+#define USB_FSEOF_FSEOFG_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LSEOF register.
+//
+//*****************************************************************************
+#define USB_LSEOF_LSEOFG_M      0x000000FF  // Low-Speed End-of-Frame Gap.
+#define USB_LSEOF_LSEOFG_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR0_ADDR_M  0x0000007F  // Device Address.
+#define USB_TXFUNCADDR0_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR0_MULTTRAN 0x00000080  // Multiple Translators.
+#define USB_TXHUBADDR0_ADDR_M   0x0000007F  // Hub Address.
+#define USB_TXHUBADDR0_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT0_PORT_M   0x0000007F  // Hub Port.
+#define USB_TXHUBPORT0_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR1_ADDR_M  0x0000007F  // Device Address.
+#define USB_TXFUNCADDR1_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR1_MULTTRAN 0x00000080  // Multiple Translators.
+#define USB_TXHUBADDR1_ADDR_M   0x0000007F  // Hub Address.
+#define USB_TXHUBADDR1_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT1_PORT_M   0x0000007F  // Hub Port.
+#define USB_TXHUBPORT1_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR1_ADDR_M  0x0000007F  // Device Address.
+#define USB_RXFUNCADDR1_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR1_MULTTRAN 0x00000080  // Multiple Translators.
+#define USB_RXHUBADDR1_ADDR_M   0x0000007F  // Hub Address.
+#define USB_RXHUBADDR1_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT1_PORT_M   0x0000007F  // Hub Port.
+#define USB_RXHUBPORT1_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR2_ADDR_M  0x0000007F  // Device Address.
+#define USB_TXFUNCADDR2_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR2_MULTTRAN 0x00000080  // Multiple Translators.
+#define USB_TXHUBADDR2_ADDR_M   0x0000007F  // Hub Address.
+#define USB_TXHUBADDR2_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT2_PORT_M   0x0000007F  // Hub Port.
+#define USB_TXHUBPORT2_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR2_ADDR_M  0x0000007F  // Device Address.
+#define USB_RXFUNCADDR2_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR2_MULTTRAN 0x00000080  // Multiple Translators.
+#define USB_RXHUBADDR2_ADDR_M   0x0000007F  // Hub Address.
+#define USB_RXHUBADDR2_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT2_PORT_M   0x0000007F  // Hub Port.
+#define USB_RXHUBPORT2_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR3_ADDR_M  0x0000007F  // Device Address.
+#define USB_TXFUNCADDR3_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR3_MULTTRAN 0x00000080  // Multiple Translators.
+#define USB_TXHUBADDR3_ADDR_M   0x0000007F  // Hub Address.
+#define USB_TXHUBADDR3_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT3_PORT_M   0x0000007F  // Hub Port.
+#define USB_TXHUBPORT3_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR3_ADDR_M  0x0000007F  // Device Address.
+#define USB_RXFUNCADDR3_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR3_MULTTRAN 0x00000080  // Multiple Translators.
+#define USB_RXHUBADDR3_ADDR_M   0x0000007F  // Hub Address.
+#define USB_RXHUBADDR3_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT3_PORT_M   0x0000007F  // Hub Port.
+#define USB_RXHUBPORT3_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRL0 register.
+//
+//*****************************************************************************
+#define USB_CSRL0_NAKTO         0x00000080  // NAK Timeout.
+#define USB_CSRL0_SETENDC       0x00000080  // Setup End Clear.
+#define USB_CSRL0_STATUS        0x00000040  // Status Packet.
+#define USB_CSRL0_RXRDYC        0x00000040  // RXRDY Clear.
+#define USB_CSRL0_REQPKT        0x00000020  // Request Packet.
+#define USB_CSRL0_STALL         0x00000020  // Send Stall.
+#define USB_CSRL0_SETEND        0x00000010  // Setup End.
+#define USB_CSRL0_ERROR         0x00000010  // Error.
+#define USB_CSRL0_DATAEND       0x00000008  // Data End.
+#define USB_CSRL0_SETUP         0x00000008  // Setup Packet.
+#define USB_CSRL0_STALLED       0x00000004  // Endpoint Stalled.
+#define USB_CSRL0_TXRDY         0x00000002  // Transmit Packet Ready.
+#define USB_CSRL0_RXRDY         0x00000001  // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRH0 register.
+//
+//*****************************************************************************
+#define USB_CSRH0_DTWE          0x00000004  // Data Toggle Write Enable.
+#define USB_CSRH0_DT            0x00000002  // Data Toggle.
+#define USB_CSRH0_FLUSH         0x00000001  // Flush FIFO.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_COUNT0 register.
+//
+//*****************************************************************************
+#define USB_COUNT0_COUNT_M      0x0000007F  // Count.
+#define USB_COUNT0_COUNT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TYPE0 register.
+//
+//*****************************************************************************
+#define USB_TYPE0_SPEED_M       0x000000C0  // Operating Speed.
+#define USB_TYPE0_SPEED_FULL    0x00000080  // Full
+#define USB_TYPE0_SPEED_LOW     0x000000C0  // Low
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_NAKLMT register.
+//
+//*****************************************************************************
+#define USB_NAKLMT_NAKLMT_M     0x0000001F  // EP0 NAK Limit.
+#define USB_NAKLMT_NAKLMT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP1_MULT_M      0x0000F800  // Multiplier.
+#define USB_TXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_TXMAXP1_MULT_S      11
+#define USB_TXMAXP1_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL1_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL1_INCTX       0x00000080  // Incomplete Transmit.
+#define USB_TXCSRL1_CLRDT       0x00000040  // Clear Data Toggle.
+#define USB_TXCSRL1_STALLED     0x00000020  // Endpoint Stalled.
+#define USB_TXCSRL1_STALL       0x00000010  // Send Stall.
+#define USB_TXCSRL1_SETUP       0x00000010  // Setup Packet.
+#define USB_TXCSRL1_FLUSH       0x00000008  // Flush FIFO.
+#define USB_TXCSRL1_ERROR       0x00000004  // Error.
+#define USB_TXCSRL1_UNDRN       0x00000004  // Underrun.
+#define USB_TXCSRL1_FIFONE      0x00000002  // FIFO Not Empty.
+#define USB_TXCSRL1_TXRDY       0x00000001  // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH1_AUTOSET     0x00000080  // Auto Set.
+#define USB_TXCSRH1_ISO         0x00000040  // ISO.
+#define USB_TXCSRH1_MODE        0x00000020  // Mode.
+#define USB_TXCSRH1_DMAEN       0x00000010  // DMA Request Enable.
+#define USB_TXCSRH1_FDT         0x00000008  // Force Data Toggle.
+#define USB_TXCSRH1_DMAMOD      0x00000004  // DMA Request Mode.
+#define USB_TXCSRH1_DTWE        0x00000002  // Data Toggle Write Enable.
+#define USB_TXCSRH1_DT          0x00000001  // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP1_MULT_M      0x0000F800  // Multiplier.
+#define USB_RXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_RXMAXP1_MULT_S      11
+#define USB_RXMAXP1_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL1_CLRDT       0x00000080  // Clear Data Toggle.
+#define USB_RXCSRL1_STALLED     0x00000040  // Endpoint Stalled.
+#define USB_RXCSRL1_STALL       0x00000020  // Send Stall.
+#define USB_RXCSRL1_REQPKT      0x00000020  // Request Packet.
+#define USB_RXCSRL1_FLUSH       0x00000010  // Flush FIFO.
+#define USB_RXCSRL1_DATAERR     0x00000008  // Data Error.
+#define USB_RXCSRL1_NAKTO       0x00000008  // NAK Timeout.
+#define USB_RXCSRL1_OVER        0x00000004  // Overrun.
+#define USB_RXCSRL1_ERROR       0x00000004  // Error.
+#define USB_RXCSRL1_FULL        0x00000002  // FIFO Full.
+#define USB_RXCSRL1_RXRDY       0x00000001  // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH1_AUTOCL      0x00000080  // Auto Clear.
+#define USB_RXCSRH1_AUTORQ      0x00000040  // Auto Request.
+#define USB_RXCSRH1_ISO         0x00000040  // ISO.
+#define USB_RXCSRH1_DMAEN       0x00000020  // DMA Request Enable.
+#define USB_RXCSRH1_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH1_PIDERR      0x00000010  // PID Error.
+#define USB_RXCSRH1_DMAMOD      0x00000008  // DMA Request Mode.
+#define USB_RXCSRH1_DTWE        0x00000004  // Data Toggle Write Enable.
+#define USB_RXCSRH1_DT          0x00000002  // Data Toggle.
+#define USB_RXCSRH1_INCRX       0x00000001  // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT1_COUNT_M    0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT1_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE1_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_TXTYPE1_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE1_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE1_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE1_PROTO_M     0x00000030  // Protocol.
+#define USB_TXTYPE1_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE1_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE1_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE1_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE1_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL1_NAKLMT_M \
+                                0x000000FF  // NAK Limit.
+#define USB_TXINTERVAL1_TXPOLL_M \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL1_TXPOLL_S \
+                                0
+#define USB_TXINTERVAL1_NAKLMT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE1_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_RXTYPE1_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE1_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE1_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE1_PROTO_M     0x00000030  // Protocol.
+#define USB_RXTYPE1_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE1_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE1_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE1_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE1_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL1_TXPOLL_M \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL1_NAKLMT_M \
+                                0x000000FF  // NAK Limit.
+#define USB_RXINTERVAL1_TXPOLL_S \
+                                0
+#define USB_RXINTERVAL1_NAKLMT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP2_MULT_M      0x0000F800  // Multiplier.
+#define USB_TXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_TXMAXP2_MULT_S      11
+#define USB_TXMAXP2_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL2_INCTX       0x00000080  // Incomplete Transmit.
+#define USB_TXCSRL2_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL2_CLRDT       0x00000040  // Clear Data Toggle.
+#define USB_TXCSRL2_STALLED     0x00000020  // Endpoint Stalled.
+#define USB_TXCSRL2_SETUP       0x00000010  // Setup Packet.
+#define USB_TXCSRL2_STALL       0x00000010  // Send Stall.
+#define USB_TXCSRL2_FLUSH       0x00000008  // Flush FIFO.
+#define USB_TXCSRL2_ERROR       0x00000004  // Error.
+#define USB_TXCSRL2_UNDRN       0x00000004  // Underrun.
+#define USB_TXCSRL2_FIFONE      0x00000002  // FIFO Not Empty.
+#define USB_TXCSRL2_TXRDY       0x00000001  // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH2_AUTOSET     0x00000080  // Auto Set.
+#define USB_TXCSRH2_ISO         0x00000040  // ISO.
+#define USB_TXCSRH2_MODE        0x00000020  // Mode.
+#define USB_TXCSRH2_DMAEN       0x00000010  // DMA Request Enable.
+#define USB_TXCSRH2_FDT         0x00000008  // Force Data Toggle.
+#define USB_TXCSRH2_DMAMOD      0x00000004  // DMA Request Mode.
+#define USB_TXCSRH2_DTWE        0x00000002  // Data Toggle Write Enable.
+#define USB_TXCSRH2_DT          0x00000001  // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP2_MULT_M      0x0000F800  // Multiplier.
+#define USB_RXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_RXMAXP2_MULT_S      11
+#define USB_RXMAXP2_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL2_CLRDT       0x00000080  // Clear Data Toggle.
+#define USB_RXCSRL2_STALLED     0x00000040  // Endpoint Stalled.
+#define USB_RXCSRL2_REQPKT      0x00000020  // Request Packet.
+#define USB_RXCSRL2_STALL       0x00000020  // Send Stall.
+#define USB_RXCSRL2_FLUSH       0x00000010  // Flush FIFO.
+#define USB_RXCSRL2_DATAERR     0x00000008  // Data Error.
+#define USB_RXCSRL2_NAKTO       0x00000008  // NAK Timeout.
+#define USB_RXCSRL2_ERROR       0x00000004  // Error.
+#define USB_RXCSRL2_OVER        0x00000004  // Overrun.
+#define USB_RXCSRL2_FULL        0x00000002  // FIFO Full.
+#define USB_RXCSRL2_RXRDY       0x00000001  // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH2_AUTOCL      0x00000080  // Auto Clear.
+#define USB_RXCSRH2_AUTORQ      0x00000040  // Auto Request.
+#define USB_RXCSRH2_ISO         0x00000040  // ISO.
+#define USB_RXCSRH2_DMAEN       0x00000020  // DMA Request Enable.
+#define USB_RXCSRH2_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH2_PIDERR      0x00000010  // PID Error.
+#define USB_RXCSRH2_DMAMOD      0x00000008  // DMA Request Mode.
+#define USB_RXCSRH2_DTWE        0x00000004  // Data Toggle Write Enable.
+#define USB_RXCSRH2_DT          0x00000002  // Data Toggle.
+#define USB_RXCSRH2_INCRX       0x00000001  // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT2_COUNT_M    0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT2_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE2_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_TXTYPE2_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE2_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE2_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE2_PROTO_M     0x00000030  // Protocol.
+#define USB_TXTYPE2_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE2_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE2_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE2_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE2_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL2_TXPOLL_M \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL2_NAKLMT_M \
+                                0x000000FF  // NAK Limit.
+#define USB_TXINTERVAL2_NAKLMT_S \
+                                0
+#define USB_TXINTERVAL2_TXPOLL_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE2_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_RXTYPE2_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE2_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE2_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE2_PROTO_M     0x00000030  // Protocol.
+#define USB_RXTYPE2_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE2_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE2_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE2_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE2_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL2_TXPOLL_M \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL2_NAKLMT_M \
+                                0x000000FF  // NAK Limit.
+#define USB_RXINTERVAL2_TXPOLL_S \
+                                0
+#define USB_RXINTERVAL2_NAKLMT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP3_MULT_M      0x0000F800  // Multiplier.
+#define USB_TXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_TXMAXP3_MULT_S      11
+#define USB_TXMAXP3_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL3_INCTX       0x00000080  // Incomplete Transmit.
+#define USB_TXCSRL3_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL3_CLRDT       0x00000040  // Clear Data Toggle.
+#define USB_TXCSRL3_STALLED     0x00000020  // Endpoint Stalled.
+#define USB_TXCSRL3_SETUP       0x00000010  // Setup Packet.
+#define USB_TXCSRL3_STALL       0x00000010  // Send Stall.
+#define USB_TXCSRL3_FLUSH       0x00000008  // Flush FIFO.
+#define USB_TXCSRL3_ERROR       0x00000004  // Error.
+#define USB_TXCSRL3_UNDRN       0x00000004  // Underrun.
+#define USB_TXCSRL3_FIFONE      0x00000002  // FIFO Not Empty.
+#define USB_TXCSRL3_TXRDY       0x00000001  // Transmit Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH3_AUTOSET     0x00000080  // Auto Set.
+#define USB_TXCSRH3_ISO         0x00000040  // ISO.
+#define USB_TXCSRH3_MODE        0x00000020  // Mode.
+#define USB_TXCSRH3_DMAEN       0x00000010  // DMA Request Enable.
+#define USB_TXCSRH3_FDT         0x00000008  // Force Data Toggle.
+#define USB_TXCSRH3_DMAMOD      0x00000004  // DMA Request Mode.
+#define USB_TXCSRH3_DTWE        0x00000002  // Data Toggle Write Enable.
+#define USB_TXCSRH3_DT          0x00000001  // Data Toggle.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP3_MULT_M      0x0000F800  // Multiplier.
+#define USB_RXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_RXMAXP3_MULT_S      11
+#define USB_RXMAXP3_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL3_CLRDT       0x00000080  // Clear Data Toggle.
+#define USB_RXCSRL3_STALLED     0x00000040  // Endpoint Stalled.
+#define USB_RXCSRL3_STALL       0x00000020  // Send Stall.
+#define USB_RXCSRL3_REQPKT      0x00000020  // Request Packet.
+#define USB_RXCSRL3_FLUSH       0x00000010  // Flush FIFO.
+#define USB_RXCSRL3_DATAERR     0x00000008  // Data Error.
+#define USB_RXCSRL3_NAKTO       0x00000008  // NAK Timeout.
+#define USB_RXCSRL3_ERROR       0x00000004  // Error.
+#define USB_RXCSRL3_OVER        0x00000004  // Overrun.
+#define USB_RXCSRL3_FULL        0x00000002  // FIFO Full.
+#define USB_RXCSRL3_RXRDY       0x00000001  // Receive Packet Ready.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH3_AUTOCL      0x00000080  // Auto Clear.
+#define USB_RXCSRH3_AUTORQ      0x00000040  // Auto Request.
+#define USB_RXCSRH3_ISO         0x00000040  // ISO.
+#define USB_RXCSRH3_DMAEN       0x00000020  // DMA Request Enable.
+#define USB_RXCSRH3_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH3_PIDERR      0x00000010  // PID Error.
+#define USB_RXCSRH3_DMAMOD      0x00000008  // DMA Request Mode.
+#define USB_RXCSRH3_DTWE        0x00000004  // Data Toggle Write Enable.
+#define USB_RXCSRH3_DT          0x00000002  // Data Toggle.
+#define USB_RXCSRH3_INCRX       0x00000001  // Incomplete Receive.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT3_COUNT_M    0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT3_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE3_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_TXTYPE3_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE3_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE3_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE3_PROTO_M     0x00000030  // Protocol.
+#define USB_TXTYPE3_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE3_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE3_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE3_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE3_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL3_TXPOLL_M \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL3_NAKLMT_M \
+                                0x000000FF  // NAK Limit.
+#define USB_TXINTERVAL3_TXPOLL_S \
+                                0
+#define USB_TXINTERVAL3_NAKLMT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE3_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_RXTYPE3_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE3_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE3_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE3_PROTO_M     0x00000030  // Protocol.
+#define USB_RXTYPE3_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE3_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE3_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE3_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE3_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL3_TXPOLL_M \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL3_NAKLMT_M \
+                                0x000000FF  // NAK Limit.
+#define USB_RXINTERVAL3_TXPOLL_S \
+                                0
+#define USB_RXINTERVAL3_NAKLMT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT1_M       0x0000FFFF  // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT1_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT2_M       0x0000FFFF  // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT2_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT3_M       0x0000FFFF  // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT3_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_RXDPKTBUFDIS_EP3    0x00000008  // EP3 RX Double-Packet Buffer
+                                            // Disable.
+#define USB_RXDPKTBUFDIS_EP2    0x00000004  // EP2 RX Double-Packet Buffer
+                                            // Disable.
+#define USB_RXDPKTBUFDIS_EP1    0x00000002  // EP1 RX Double-Packet Buffer
+                                            // Disable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_TXDPKTBUFDIS_EP3    0x00000008  // EP3 TX Double-Packet Buffer
+                                            // Disable.
+#define USB_TXDPKTBUFDIS_EP2    0x00000004  // EP2 TX Double-Packet Buffer
+                                            // Disable.
+#define USB_TXDPKTBUFDIS_EP1    0x00000002  // EP1 TX Double-Packet Buffer
+                                            // Disable.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPC register.
+//
+//*****************************************************************************
+#define USB_EPC_PFLTACT_M       0x00000300  // Power Fault Action.
+#define USB_EPC_PFLTACT_UNCHG   0x00000000  // Unchanged
+#define USB_EPC_PFLTACT_TRIS    0x00000100  // Tristate
+#define USB_EPC_PFLTACT_LOW     0x00000200  // Low
+#define USB_EPC_PFLTACT_HIGH    0x00000300  // High
+#define USB_EPC_PFLTAEN         0x00000040  // Power Fault Action Enable.
+#define USB_EPC_PFLTSEN_HIGH    0x00000020  // Power Fault Sense.
+#define USB_EPC_PFLTEN          0x00000010  // Power Fault Input Enable.
+#define USB_EPC_EPENDE          0x00000004  // EPEN Drive Enable.
+#define USB_EPC_EPEN_M          0x00000003  // External Power Supply Enable
+                                            // Configuration.
+#define USB_EPC_EPEN_LOW        0x00000000  // Power Enable Active Low
+#define USB_EPC_EPEN_HIGH       0x00000001  // Power Enable Active High
+#define USB_EPC_EPEN_VBLOW      0x00000002  // Power Enable High if VBUS Low
+#define USB_EPC_EPEN_VBHIGH     0x00000003  // Power Enable High if VBUS High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCRIS register.
+//
+//*****************************************************************************
+#define USB_EPCRIS_PF           0x00000001  // USB Power Fault Interrupt
+                                            // Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCIM register.
+//
+//*****************************************************************************
+#define USB_EPCIM_PF            0x00000001  // USB Power Fault Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCISC register.
+//
+//*****************************************************************************
+#define USB_EPCISC_PF           0x00000001  // USB Power Fault Interrupt Status
+                                            // and Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRRIS register.
+//
+//*****************************************************************************
+#define USB_DRRIS_RESUME        0x00000001  // Resume Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRIM register.
+//
+//*****************************************************************************
+#define USB_DRIM_RESUME         0x00000001  // Resume Interrupt Mask.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRISC register.
+//
+//*****************************************************************************
+#define USB_DRISC_RESUME        0x00000001  // Resume Interrupt Status and
+                                            // Clear.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_GPCS register.
+//
+//*****************************************************************************
+#define USB_GPCS_DEVMOD         0x00000001  // Device Mode.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VPLEN register.
+//
+//*****************************************************************************
+#define USB_VPLEN_VPLEN_M       0x000000FF  // VBus Pulse Length.
+#define USB_VPLEN_VPLEN_S       0
+
+#endif // __HW_USB_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_watchdog.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_watchdog.h
new file mode 100644
index 0000000..5e8991b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/hw_watchdog.h
@@ -0,0 +1,179 @@
+//*****************************************************************************
+//
+// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HW_WATCHDOG_H__
+#define __HW_WATCHDOG_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Watchdog Timer register offsets.
+//
+//*****************************************************************************
+#define WDT_O_LOAD              0x00000000  // Load register
+#define WDT_O_VALUE             0x00000004  // Current value register
+#define WDT_O_CTL               0x00000008  // Control register
+#define WDT_O_ICR               0x0000000C  // Interrupt clear register
+#define WDT_O_RIS               0x00000010  // Raw interrupt status register
+#define WDT_O_MIS               0x00000014  // Masked interrupt status register
+#define WDT_O_TEST              0x00000418  // Test register
+#define WDT_O_LOCK              0x00000C00  // Lock register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_CTL register.
+//
+//*****************************************************************************
+#define WDT_CTL_RESEN           0x00000002  // Enable reset output
+#define WDT_CTL_INTEN           0x00000001  // Enable the WDT counter and int
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and
+// WDT_MIS registers.
+//
+//*****************************************************************************
+#define WDT_INT_TIMEOUT         0x00000001  // Watchdog timer expired
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_TEST register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL          0x00000100  // Watchdog stall enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_LOCK register.
+//
+//*****************************************************************************
+#define WDT_LOCK_M              0xFFFFFFFF  // Watchdog Lock.
+#define WDT_LOCK_UNLOCK         0x1ACCE551  // Unlocks the watchdog timer
+#define WDT_LOCK_LOCKED         0x00000001  // Watchdog timer is locked
+#define WDT_LOCK_UNLOCKED       0x00000000  // Watchdog timer is unlocked
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOAD register.
+//
+//*****************************************************************************
+#define WDT_LOAD_M              0xFFFFFFFF  // Watchdog Load Value.
+#define WDT_LOAD_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_VALUE register.
+//
+//*****************************************************************************
+#define WDT_VALUE_M             0xFFFFFFFF  // Watchdog Value.
+#define WDT_VALUE_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_ICR register.
+//
+//*****************************************************************************
+#define WDT_ICR_M               0xFFFFFFFF  // Watchdog Interrupt Clear.
+#define WDT_ICR_S               0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_RIS register.
+//
+//*****************************************************************************
+#define WDT_RIS_WDTRIS          0x00000001  // Watchdog Raw Interrupt Status.
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_MIS register.
+//
+//*****************************************************************************
+#define WDT_MIS_WDTMIS          0x00000001  // Watchdog Masked Interrupt
+                                            // Status.
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Watchdog Timer register
+// offsets.
+//
+//*****************************************************************************
+#define WDT_O_PeriphID4         0x00000FD0
+#define WDT_O_PeriphID5         0x00000FD4
+#define WDT_O_PeriphID6         0x00000FD8
+#define WDT_O_PeriphID7         0x00000FDC
+#define WDT_O_PeriphID0         0x00000FE0
+#define WDT_O_PeriphID1         0x00000FE4
+#define WDT_O_PeriphID2         0x00000FE8
+#define WDT_O_PeriphID3         0x00000FEC
+#define WDT_O_PCellID0          0x00000FF0
+#define WDT_O_PCellID1          0x00000FF4
+#define WDT_O_PCellID2          0x00000FF8
+#define WDT_O_PCellID3          0x00000FFC
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the WDT_TEST
+// register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL_EN       0x00000100  // Watchdog stall enable
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values for the WDT
+// registers.
+//
+//*****************************************************************************
+#define WDT_RV_VALUE            0xFFFFFFFF  // Current value register
+#define WDT_RV_LOAD             0xFFFFFFFF  // Load register
+#define WDT_RV_PCellID1         0x000000F0
+#define WDT_RV_PCellID3         0x000000B1
+#define WDT_RV_PeriphID1        0x00000018
+#define WDT_RV_PeriphID2        0x00000018
+#define WDT_RV_PCellID0         0x0000000D
+#define WDT_RV_PCellID2         0x00000005
+#define WDT_RV_PeriphID0        0x00000005
+#define WDT_RV_PeriphID3        0x00000001
+#define WDT_RV_PeriphID5        0x00000000
+#define WDT_RV_RIS              0x00000000  // Raw interrupt status register
+#define WDT_RV_CTL              0x00000000  // Control register
+#define WDT_RV_PeriphID4        0x00000000
+#define WDT_RV_PeriphID6        0x00000000
+#define WDT_RV_PeriphID7        0x00000000
+#define WDT_RV_LOCK             0x00000000  // Lock register
+#define WDT_RV_MIS              0x00000000  // Masked interrupt status register
+
+#endif
+
+#endif // __HW_WATCHDOG_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/i2c.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/i2c.h
new file mode 100644
index 0000000..50aeecd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/i2c.h
@@ -0,0 +1,156 @@
+//*****************************************************************************
+//
+// i2c.h - Prototypes for the I2C Driver.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __I2C_H__
+#define __I2C_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Defines for the API.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Interrupt defines.
+//
+//*****************************************************************************
+#define I2C_INT_MASTER          0x00000001
+#define I2C_INT_SLAVE           0x00000002
+
+//*****************************************************************************
+//
+// I2C Master commands.
+//
+//*****************************************************************************
+#define I2C_MASTER_CMD_SINGLE_SEND              0x00000007
+#define I2C_MASTER_CMD_SINGLE_RECEIVE           0x00000007
+#define I2C_MASTER_CMD_BURST_SEND_START         0x00000003
+#define I2C_MASTER_CMD_BURST_SEND_CONT          0x00000001
+#define I2C_MASTER_CMD_BURST_SEND_FINISH        0x00000005
+#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP    0x00000004
+#define I2C_MASTER_CMD_BURST_RECEIVE_START      0x0000000b
+#define I2C_MASTER_CMD_BURST_RECEIVE_CONT       0x00000009
+#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH     0x00000005
+#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP 0x00000005
+
+//*****************************************************************************
+//
+// I2C Master error status.
+//
+//*****************************************************************************
+#define I2C_MASTER_ERR_NONE     0
+#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
+#define I2C_MASTER_ERR_DATA_ACK 0x00000008
+#define I2C_MASTER_ERR_ARB_LOST 0x00000010
+
+//*****************************************************************************
+//
+// I2C Slave action requests
+//
+//*****************************************************************************
+#define I2C_SLAVE_ACT_NONE      0
+#define I2C_SLAVE_ACT_RREQ      0x00000001  // Master has sent data
+#define I2C_SLAVE_ACT_TREQ      0x00000002  // Master has requested data
+#define I2C_SLAVE_ACT_RREQ_FBR  0x00000005  // Master has sent first byte
+
+//*****************************************************************************
+//
+// Miscellaneous I2C driver definitions.
+//
+//*****************************************************************************
+#define I2C_MASTER_MAX_RETRIES  1000        // Number of retries
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));
+extern void I2CIntUnregister(unsigned long ulBase);
+extern tBoolean I2CMasterBusBusy(unsigned long ulBase);
+extern tBoolean I2CMasterBusy(unsigned long ulBase);
+extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);
+extern unsigned long I2CMasterDataGet(unsigned long ulBase);
+extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);
+extern void I2CMasterDisable(unsigned long ulBase);
+extern void I2CMasterEnable(unsigned long ulBase);
+extern unsigned long I2CMasterErr(unsigned long ulBase);
+extern void I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk,
+                                tBoolean bFast);
+extern void I2CMasterIntClear(unsigned long ulBase);
+extern void I2CMasterIntDisable(unsigned long ulBase);
+extern void I2CMasterIntEnable(unsigned long ulBase);
+extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void I2CMasterSlaveAddrSet(unsigned long ulBase,
+                                  unsigned char ucSlaveAddr,
+                                  tBoolean bReceive);
+extern unsigned long I2CSlaveDataGet(unsigned long ulBase);
+extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);
+extern void I2CSlaveDisable(unsigned long ulBase);
+extern void I2CSlaveEnable(unsigned long ulBase);
+extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);
+extern void I2CSlaveIntClear(unsigned long ulBase);
+extern void I2CSlaveIntDisable(unsigned long ulBase);
+extern void I2CSlaveIntEnable(unsigned long ulBase);
+extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern unsigned long I2CSlaveStatus(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Several I2C APIs have been renamed, with the original function name being
+// deprecated.  These defines provide backward compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#include "sysctl.h"
+#define I2CMasterInit(a, b)                         \
+        I2CMasterInitExpClk(a, SysCtlClockGet(), b)
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __I2C_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/interrupt.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/interrupt.h
new file mode 100644
index 0000000..feaaf1c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/interrupt.h
@@ -0,0 +1,77 @@
+//*****************************************************************************
+//
+// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Macro to generate an interrupt priority mask based on the number of bits
+// of priority supported by the hardware.
+//
+//*****************************************************************************
+#define INT_PRIORITY_MASK       ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern tBoolean IntMasterEnable(void);
+extern tBoolean IntMasterDisable(void);
+extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));
+extern void IntUnregister(unsigned long ulInterrupt);
+extern void IntPriorityGroupingSet(unsigned long ulBits);
+extern unsigned long IntPriorityGroupingGet(void);
+extern void IntPrioritySet(unsigned long ulInterrupt,
+                           unsigned char ucPriority);
+extern long IntPriorityGet(unsigned long ulInterrupt);
+extern void IntEnable(unsigned long ulInterrupt);
+extern void IntDisable(unsigned long ulInterrupt);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __INTERRUPT_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/lmi_flash.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/lmi_flash.h
new file mode 100644
index 0000000..e53883f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/lmi_flash.h
@@ -0,0 +1,78 @@
+//*****************************************************************************
+//
+// flash.h - Prototypes for the flash driver.
+//
+// Copyright (c) 2005-2007 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  Any use in violation
+// of the foregoing restrictions may subject the user to criminal sanctions
+// under applicable laws, as well as to civil liability for the breach of the
+// terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __FLASH_H__
+#define __FLASH_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to FlashProtectSet(), and returned by
+// FlashProtectGet().
+//
+//*****************************************************************************
+typedef enum
+{
+    FlashReadWrite,                         // Flash can be read and written
+    FlashReadOnly,                          // Flash can only be read
+    FlashExecuteOnly                        // Flash can only be executed
+}
+tFlashProtection;
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern unsigned long FlashUsecGet(void);
+extern void FlashUsecSet(unsigned long ulClocks);
+extern long FlashErase(unsigned long ulAddress);
+extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,
+                         unsigned long ulCount);
+extern tFlashProtection FlashProtectGet(unsigned long ulAddress);
+extern long FlashProtectSet(unsigned long ulAddress,
+                            tFlashProtection eProtect);
+extern long FlashProtectSave(void);
+extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1);
+extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1);
+extern long FlashUserSave(void);
+extern void FlashIntRegister(void (*pfnHandler)(void));
+extern void FlashIntUnregister(void);
+extern void FlashIntEnable(unsigned long ulIntFlags);
+extern void FlashIntDisable(unsigned long ulIntFlags);
+extern unsigned long FlashIntGetStatus(tBoolean bMasked);
+extern void FlashIntClear(unsigned long ulIntFlags);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __FLASH_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/lmi_timer.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/lmi_timer.h
new file mode 100644
index 0000000..0a0d545
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/lmi_timer.h
@@ -0,0 +1,137 @@
+//*****************************************************************************
+//
+// timer.h - Prototypes for the timer module
+//
+// Copyright (c) 2005-2007 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  Any use in violation
+// of the foregoing restrictions may subject the user to criminal sanctions
+// under applicable laws, as well as to civil liability for the breach of the
+// terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __TIMER_H__
+#define __TIMER_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerConfigure as the ulConfig parameter.
+//
+//*****************************************************************************
+#define TIMER_CFG_32_BIT_OS     0x00000001  // 32-bit one-shot timer
+#define TIMER_CFG_32_BIT_PER    0x00000002  // 32-bit periodic timer
+#define TIMER_CFG_32_RTC        0x01000000  // 32-bit RTC timer
+#define TIMER_CFG_16_BIT_PAIR   0x04000000  // Two 16-bit timers
+#define TIMER_CFG_A_ONE_SHOT    0x00000001  // Timer A one-shot timer
+#define TIMER_CFG_A_PERIODIC    0x00000002  // Timer A periodic timer
+#define TIMER_CFG_A_CAP_COUNT   0x00000003  // Timer A event counter
+#define TIMER_CFG_A_CAP_TIME    0x00000007  // Timer A event timer
+#define TIMER_CFG_A_PWM         0x0000000A  // Timer A PWM output
+#define TIMER_CFG_B_ONE_SHOT    0x00000100  // Timer B one-shot timer
+#define TIMER_CFG_B_PERIODIC    0x00000200  // Timer B periodic timer
+#define TIMER_CFG_B_CAP_COUNT   0x00000300  // Timer B event counter
+#define TIMER_CFG_B_CAP_TIME    0x00000700  // Timer B event timer
+#define TIMER_CFG_B_PWM         0x00000A00  // Timer B PWM output
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and
+// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
+//
+//*****************************************************************************
+#define TIMER_CAPB_EVENT        0x00000400  // CaptureB event interrupt
+#define TIMER_CAPB_MATCH        0x00000200  // CaptureB match interrupt
+#define TIMER_TIMB_TIMEOUT      0x00000100  // TimerB time out interrupt
+#define TIMER_RTC_MATCH         0x00000008  // RTC interrupt mask
+#define TIMER_CAPA_EVENT        0x00000004  // CaptureA event interrupt
+#define TIMER_CAPA_MATCH        0x00000002  // CaptureA match interrupt
+#define TIMER_TIMA_TIMEOUT      0x00000001  // TimerA time out interrupt
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerControlEvent as the ulEvent parameter.
+//
+//*****************************************************************************
+#define TIMER_EVENT_POS_EDGE    0x00000000  // Count positive edges
+#define TIMER_EVENT_NEG_EDGE    0x00000404  // Count negative edges
+#define TIMER_EVENT_BOTH_EDGES  0x00000C0C  // Count both edges
+
+//*****************************************************************************
+//
+// Values that can be passed to most of the timer APIs as the ulTimer
+// parameter.
+//
+//*****************************************************************************
+#define TIMER_A                 0x000000ff  // Timer A
+#define TIMER_B                 0x0000ff00  // Timer B
+#define TIMER_BOTH              0x0000ffff  // Timer Both
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);
+extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);
+extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);
+extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
+                              tBoolean bInvert);
+extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
+                                tBoolean bEnable);
+extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
+                              unsigned long ulEvent);
+extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
+                              tBoolean bStall);
+extern void TimerRTCEnable(unsigned long ulBase);
+extern void TimerRTCDisable(unsigned long ulBase);
+extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
+                             unsigned long ulValue);
+extern unsigned long TimerPrescaleGet(unsigned long ulBase,
+                                      unsigned long ulTimer);
+extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
+                                  unsigned long ulValue);
+extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,
+                                           unsigned long ulTimer);
+extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
+                         unsigned long ulValue);
+extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
+extern unsigned long TimerValueGet(unsigned long ulBase,
+                                   unsigned long ulTimer);
+extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
+                          unsigned long ulValue);
+extern unsigned long TimerMatchGet(unsigned long ulBase,
+                                   unsigned long ulTimer);
+extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
+                             void (*pfnHandler)(void));
+extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
+extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+extern void TimerQuiesce(unsigned long ulBase);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __TIMER_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/mpu.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/mpu.h
new file mode 100644
index 0000000..a52f501
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/mpu.h
@@ -0,0 +1,151 @@
+//*****************************************************************************
+//
+// mpu.h - Defines and Macros for the memory protection unit.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __MPU_H__
+#define __MPU_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Flags that can be passed to MPUEnable..
+//
+//*****************************************************************************
+#define MPU_CONFIG_PRIV_DEFAULT     4
+#define MPU_CONFIG_HARDFLT_NMI      2
+#define MPU_CONFIG_NONE             0
+
+//*****************************************************************************
+//
+// Flags for the region size to be passed to MPURegionSet.
+//
+//*****************************************************************************
+#define MPU_RGN_SIZE_32B            (4 << 1)
+#define MPU_RGN_SIZE_64B            (5 << 1)
+#define MPU_RGN_SIZE_128B           (6 << 1)
+#define MPU_RGN_SIZE_256B           (7 << 1)
+#define MPU_RGN_SIZE_512B           (8 << 1)
+
+#define MPU_RGN_SIZE_1K             (9 << 1)
+#define MPU_RGN_SIZE_2K             (10 << 1)
+#define MPU_RGN_SIZE_4K             (11 << 1)
+#define MPU_RGN_SIZE_8K             (12 << 1)
+#define MPU_RGN_SIZE_16K            (13 << 1)
+#define MPU_RGN_SIZE_32K            (14 << 1)
+#define MPU_RGN_SIZE_64K            (15 << 1)
+#define MPU_RGN_SIZE_128K           (16 << 1)
+#define MPU_RGN_SIZE_256K           (17 << 1)
+#define MPU_RGN_SIZE_512K           (18 << 1)
+
+#define MPU_RGN_SIZE_1M             (19 << 1)
+#define MPU_RGN_SIZE_2M             (20 << 1)
+#define MPU_RGN_SIZE_4M             (21 << 1)
+#define MPU_RGN_SIZE_8M             (22 << 1)
+#define MPU_RGN_SIZE_16M            (23 << 1)
+#define MPU_RGN_SIZE_32M            (24 << 1)
+#define MPU_RGN_SIZE_64M            (25 << 1)
+#define MPU_RGN_SIZE_128M           (26 << 1)
+#define MPU_RGN_SIZE_256M           (27 << 1)
+#define MPU_RGN_SIZE_512M           (28 << 1)
+
+#define MPU_RGN_SIZE_1G             (29 << 1)
+#define MPU_RGN_SIZE_2G             (30 << 1)
+#define MPU_RGN_SIZE_4G             (31 << 1)
+
+//*****************************************************************************
+//
+// Flags for the permissions to be passed to MPURegionSet.
+//
+//*****************************************************************************
+#define MPU_RGN_PERM_EXEC           0x00000000
+#define MPU_RGN_PERM_NOEXEC         0x10000000
+#define MPU_RGN_PERM_PRV_NO_USR_NO  0x00000000
+#define MPU_RGN_PERM_PRV_RW_USR_NO  0x01000000
+#define MPU_RGN_PERM_PRV_RW_USR_RO  0x02000000
+#define MPU_RGN_PERM_PRV_RW_USR_RW  0x03000000
+#define MPU_RGN_PERM_PRV_RO_USR_NO  0x05000000
+#define MPU_RGN_PERM_PRV_RO_USR_RO  0x06000000
+
+//*****************************************************************************
+//
+// Flags for the sub-region to be passed to MPURegionSet.
+//
+//*****************************************************************************
+#define MPU_SUB_RGN_DISABLE_0       0x00000100
+#define MPU_SUB_RGN_DISABLE_1       0x00000200
+#define MPU_SUB_RGN_DISABLE_2       0x00000400
+#define MPU_SUB_RGN_DISABLE_3       0x00000800
+#define MPU_SUB_RGN_DISABLE_4       0x00001000
+#define MPU_SUB_RGN_DISABLE_5       0x00002000
+#define MPU_SUB_RGN_DISABLE_6       0x00004000
+#define MPU_SUB_RGN_DISABLE_7       0x00008000
+
+//*****************************************************************************
+//
+// Flags to enable or disable a region, to be passed to MPURegionSet.
+//
+//*****************************************************************************
+#define MPU_RGN_ENABLE              1
+#define MPU_RGN_DISABLE             0
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void MPUEnable(unsigned long ulMPUConfig);
+extern void MPUDisable(void);
+extern unsigned long MPURegionCountGet(void);
+extern void MPURegionEnable(unsigned long ulRegion);
+extern void MPURegionDisable(unsigned long ulRegion);
+extern void MPURegionSet(unsigned long ulRegion, unsigned long ulAddr,
+                         unsigned long ulFlags);
+extern void MPURegionGet(unsigned long ulRegion, unsigned long *pulAddr,
+                         unsigned long *pulFlags);
+extern void MPUIntRegister(void (*pfnHandler)(void));
+extern void MPUIntUnregister(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif //  __MPU_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/pwm.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/pwm.h
new file mode 100644
index 0000000..cdb0725
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/pwm.h
@@ -0,0 +1,270 @@
+//*****************************************************************************
+//
+// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __PWM_H__
+#define __PWM_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following defines are passed to PWMGenConfigure() as the ulConfig
+// parameter and specify the configuration of the PWM generator.
+//
+//*****************************************************************************
+#define PWM_GEN_MODE_DOWN       0x00000000  // Down count mode
+#define PWM_GEN_MODE_UP_DOWN    0x00000002  // Up/Down count mode
+#define PWM_GEN_MODE_SYNC       0x00000038  // Synchronous updates
+#define PWM_GEN_MODE_NO_SYNC    0x00000000  // Immediate updates
+#define PWM_GEN_MODE_DBG_RUN    0x00000004  // Continue running in debug mode
+#define PWM_GEN_MODE_DBG_STOP   0x00000000  // Stop running in debug mode
+#define PWM_GEN_MODE_FAULT_LATCHED \
+                                0x00040000  // Fault is latched
+#define PWM_GEN_MODE_FAULT_UNLATCHED \
+                                0x00000000  // Fault is not latched
+#define PWM_GEN_MODE_FAULT_MINPER \
+                                0x00020000  // Enable min fault period
+#define PWM_GEN_MODE_FAULT_NO_MINPER \
+                                0x00000000  // Disable min fault period
+#define PWM_GEN_MODE_FAULT_EXT  0x00010000  // Enable extended fault support
+#define PWM_GEN_MODE_FAULT_LEGACY \
+                                0x00000000  // Disable extended fault support
+#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000  // Deadband updates occur
+                                            // immediately
+#define PWM_GEN_MODE_DB_SYNC_LOCAL \
+                                0x0000A800  // Deadband updates locally
+                                            // synchronized
+#define PWM_GEN_MODE_DB_SYNC_GLOBAL \
+                                0x0000FC00  // Deadband updates globally
+                                            // synchronized
+#define PWM_GEN_MODE_GEN_NO_SYNC \
+                                0x00000000  // Generator mode updates occur
+                                            // immediately
+#define PWM_GEN_MODE_GEN_SYNC_LOCAL \
+                                0x00000280  // Generator mode updates locally
+                                            // synchronized
+#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \
+                                0x000003C0  // Generator mode updates globally
+                                            // synchronized
+
+//*****************************************************************************
+//
+// Defines for enabling, disabling, and clearing PWM generator interrupts and
+// triggers.
+//
+//*****************************************************************************
+#define PWM_INT_CNT_ZERO        0x00000001  // Int if COUNT = 0
+#define PWM_INT_CNT_LOAD        0x00000002  // Int if COUNT = LOAD
+#define PWM_INT_CNT_AU          0x00000004  // Int if COUNT = CMPA U
+#define PWM_INT_CNT_AD          0x00000008  // Int if COUNT = CMPA D
+#define PWM_INT_CNT_BU          0x00000010  // Int if COUNT = CMPA U
+#define PWM_INT_CNT_BD          0x00000020  // Int if COUNT = CMPA D
+#define PWM_TR_CNT_ZERO         0x00000100  // Trig if COUNT = 0
+#define PWM_TR_CNT_LOAD         0x00000200  // Trig if COUNT = LOAD
+#define PWM_TR_CNT_AU           0x00000400  // Trig if COUNT = CMPA U
+#define PWM_TR_CNT_AD           0x00000800  // Trig if COUNT = CMPA D
+#define PWM_TR_CNT_BU           0x00001000  // Trig if COUNT = CMPA U
+#define PWM_TR_CNT_BD           0x00002000  // Trig if COUNT = CMPA D
+
+//*****************************************************************************
+//
+// Defines for enabling, disabling, and clearing PWM interrupts.
+//
+//*****************************************************************************
+#define PWM_INT_GEN_0           0x00000001  // Generator 0 interrupt
+#define PWM_INT_GEN_1           0x00000002  // Generator 1 interrupt
+#define PWM_INT_GEN_2           0x00000004  // Generator 2 interrupt
+#define PWM_INT_GEN_3           0x00000008  // Generator 3 interrupt
+#ifndef DEPRECATED
+#define PWM_INT_FAULT           0x00010000  // Fault interrupt
+#endif
+#define PWM_INT_FAULT0          0x00010000  // Fault0 interrupt
+#define PWM_INT_FAULT1          0x00020000  // Fault1 interrupt
+#define PWM_INT_FAULT2          0x00040000  // Fault2 interrupt
+#define PWM_INT_FAULT3          0x00080000  // Fault3 interrupt
+#define PWM_INT_FAULT_M         0x000F0000  // Fault interrupt source mask
+
+//*****************************************************************************
+//
+// Defines to identify the generators within a module.
+//
+//*****************************************************************************
+#define PWM_GEN_0               0x00000040  // Offset address of Gen0
+#define PWM_GEN_1               0x00000080  // Offset address of Gen1
+#define PWM_GEN_2               0x000000C0  // Offset address of Gen2
+#define PWM_GEN_3               0x00000100  // Offset address of Gen3
+
+#define PWM_GEN_0_BIT           0x00000001  // Bit-wise ID for Gen0
+#define PWM_GEN_1_BIT           0x00000002  // Bit-wise ID for Gen1
+#define PWM_GEN_2_BIT           0x00000004  // Bit-wise ID for Gen2
+#define PWM_GEN_3_BIT           0x00000008  // Bit-wise ID for Gen3
+
+#define PWM_GEN_EXT_0           0x00000800  // Offset of Gen0 ext address range
+#define PWM_GEN_EXT_1           0x00000880  // Offset of Gen1 ext address range
+#define PWM_GEN_EXT_2           0x00000900  // Offset of Gen2 ext address range
+#define PWM_GEN_EXT_3           0x00000980  // Offset of Gen3 ext address range
+
+//*****************************************************************************
+//
+// Defines to identify the outputs within a module.
+//
+//*****************************************************************************
+#define PWM_OUT_0               0x00000040  // Encoded offset address of PWM0
+#define PWM_OUT_1               0x00000041  // Encoded offset address of PWM1
+#define PWM_OUT_2               0x00000082  // Encoded offset address of PWM2
+#define PWM_OUT_3               0x00000083  // Encoded offset address of PWM3
+#define PWM_OUT_4               0x000000C4  // Encoded offset address of PWM4
+#define PWM_OUT_5               0x000000C5  // Encoded offset address of PWM5
+#define PWM_OUT_6               0x00000106  // Encoded offset address of PWM6
+#define PWM_OUT_7               0x00000107  // Encoded offset address of PWM7
+
+#define PWM_OUT_0_BIT           0x00000001  // Bit-wise ID for PWM0
+#define PWM_OUT_1_BIT           0x00000002  // Bit-wise ID for PWM1
+#define PWM_OUT_2_BIT           0x00000004  // Bit-wise ID for PWM2
+#define PWM_OUT_3_BIT           0x00000008  // Bit-wise ID for PWM3
+#define PWM_OUT_4_BIT           0x00000010  // Bit-wise ID for PWM4
+#define PWM_OUT_5_BIT           0x00000020  // Bit-wise ID for PWM5
+#define PWM_OUT_6_BIT           0x00000040  // Bit-wise ID for PWM6
+#define PWM_OUT_7_BIT           0x00000080  // Bit-wise ID for PWM7
+
+//*****************************************************************************
+//
+// Defines to identify each of the possible fault trigger conditions in
+// PWM_FAULT_GROUP_0
+//
+//*****************************************************************************
+#define PWM_FAULT_GROUP_0     0
+
+#define PWM_FAULT_FAULT0      0x00000001
+#define PWM_FAULT_FAULT1      0x00000002
+#define PWM_FAULT_FAULT2      0x00000004
+#define PWM_FAULT_FAULT3      0x00000008
+#define PWM_FAULT_ACMP0       0x00010000
+#define PWM_FAULT_ACMP1       0x00020000
+#define PWM_FAULT_ACMP2       0x00040000
+
+//*****************************************************************************
+//
+// Defines to identify the sense of each of the external FAULTn signals
+//
+//*****************************************************************************
+#define PWM_FAULT0_SENSE_HIGH   0x00000000
+#define PWM_FAULT0_SENSE_LOW    0x00000001
+#define PWM_FAULT1_SENSE_HIGH   0x00000000
+#define PWM_FAULT1_SENSE_LOW    0x00000002
+#define PWM_FAULT2_SENSE_HIGH   0x00000000
+#define PWM_FAULT2_SENSE_LOW    0x00000004
+#define PWM_FAULT3_SENSE_HIGH   0x00000000
+#define PWM_FAULT3_SENSE_LOW    0x00000008
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,
+                            unsigned long ulConfig);
+extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,
+                            unsigned long ulPeriod);
+extern unsigned long PWMGenPeriodGet(unsigned long ulBase,
+                                     unsigned long ulGen);
+extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);
+extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);
+extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,
+                             unsigned long ulWidth);
+extern unsigned long PWMPulseWidthGet(unsigned long ulBase,
+                                      unsigned long ulPWMOut);
+extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,
+                              unsigned short usRise, unsigned short usFall);
+extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);
+extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);
+extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);
+extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,
+                           tBoolean bEnable);
+extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,
+                            tBoolean bInvert);
+extern void PWMOutputFaultLevel(unsigned long ulBase,
+                                unsigned long ulPWMOutBits,
+                                tBoolean bDriveHigh);
+extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,
+                           tBoolean bFaultSuppress);
+extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,
+                              void (*pfnIntHandler)(void));
+extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);
+extern void PWMFaultIntRegister(unsigned long ulBase,
+                                void (*pfnIntHandler)(void));
+extern void PWMFaultIntUnregister(unsigned long ulBase);
+extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,
+                                unsigned long ulIntTrig);
+extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,
+                                 unsigned long ulIntTrig);
+extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,
+                                     tBoolean bMasked);
+extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,
+                           unsigned long ulInts);
+extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);
+extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);
+extern void PWMFaultIntClear(unsigned long ulBase);
+extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void PWMFaultIntClearExt(unsigned long ulBase,
+                                unsigned long ulFaultInts);
+extern void PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen,
+                                 unsigned long ulMinFaultPeriod,
+                                 unsigned long ulFaultSenses);
+extern void PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
+                                  unsigned long ulGroup,
+                                  unsigned long ulFaultTriggers);
+extern unsigned long PWMGenFaultTriggerGet(unsigned long ulBase,
+                                           unsigned long ulGen,
+                                           unsigned long ulGroup);
+extern unsigned long PWMGenFaultStatus(unsigned long ulBase,
+                                       unsigned long ulGen,
+                                       unsigned long ulGroup);
+extern void PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen,
+                             unsigned long ulGroup,
+                             unsigned long ulFaultTriggers);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __PWM_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/qei.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/qei.h
new file mode 100644
index 0000000..5d1f39c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/qei.h
@@ -0,0 +1,116 @@
+//*****************************************************************************
+//
+// qei.h - Prototypes for the Quadrature Encoder Driver.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __QEI_H__
+#define __QEI_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to QEIConfigure as the ulConfig paramater.
+//
+//*****************************************************************************
+#define QEI_CONFIG_CAPTURE_A    0x00000000  // Count on ChA edges only
+#define QEI_CONFIG_CAPTURE_A_B  0x00000008  // Count on ChA and ChB edges
+#define QEI_CONFIG_NO_RESET     0x00000000  // Do not reset on index pulse
+#define QEI_CONFIG_RESET_IDX    0x00000010  // Reset position on index pulse
+#define QEI_CONFIG_QUADRATURE   0x00000000  // ChA and ChB are quadrature
+#define QEI_CONFIG_CLOCK_DIR    0x00000004  // ChA and ChB are clock and dir
+#define QEI_CONFIG_NO_SWAP      0x00000000  // Do not swap ChA and ChB
+#define QEI_CONFIG_SWAP         0x00000002  // Swap ChA and ChB
+
+//*****************************************************************************
+//
+// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter.
+//
+//*****************************************************************************
+#define QEI_VELDIV_1            0x00000000  // Predivide by 1
+#define QEI_VELDIV_2            0x00000040  // Predivide by 2
+#define QEI_VELDIV_4            0x00000080  // Predivide by 4
+#define QEI_VELDIV_8            0x000000C0  // Predivide by 8
+#define QEI_VELDIV_16           0x00000100  // Predivide by 16
+#define QEI_VELDIV_32           0x00000140  // Predivide by 32
+#define QEI_VELDIV_64           0x00000180  // Predivide by 64
+#define QEI_VELDIV_128          0x000001C0  // Predivide by 128
+
+//*****************************************************************************
+//
+// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts
+// as the ulIntFlags parameter, and returned by QEIGetIntStatus.
+//
+//*****************************************************************************
+#define QEI_INTERROR            0x00000008  // Phase error detected
+#define QEI_INTDIR              0x00000004  // Direction change
+#define QEI_INTTIMER            0x00000002  // Velocity timer expired
+#define QEI_INTINDEX            0x00000001  // Index pulse detected
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void QEIEnable(unsigned long ulBase);
+extern void QEIDisable(unsigned long ulBase);
+extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig,
+                         unsigned long ulMaxPosition);
+extern unsigned long QEIPositionGet(unsigned long ulBase);
+extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition);
+extern long QEIDirectionGet(unsigned long ulBase);
+extern tBoolean QEIErrorGet(unsigned long ulBase);
+extern void QEIVelocityEnable(unsigned long ulBase);
+extern void QEIVelocityDisable(unsigned long ulBase);
+extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,
+                                 unsigned long ulPeriod);
+extern unsigned long QEIVelocityGet(unsigned long ulBase);
+extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
+extern void QEIIntUnregister(unsigned long ulBase);
+extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __QEI_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/rit128x96x4.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/rit128x96x4.h
new file mode 100644
index 0000000..eeec8e6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/rit128x96x4.h
@@ -0,0 +1,53 @@
+//*****************************************************************************
+//
+// rit128x96x4.h - Prototypes for the driver for the RITEK 128x96x4 graphical
+//                   OLED display.
+//
+// Copyright (c) 2007 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  Any use in violation
+// of the foregoing restrictions may subject the user to criminal sanctions
+// under applicable laws, as well as to civil liability for the breach of the
+// terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __RIT128X96X4_H__
+#define __RIT128X96X4_H__
+
+//*****************************************************************************
+//
+// Prototypes for the driver APIs.
+//
+//*****************************************************************************
+extern void RIT128x96x4Clear(void);
+extern void RIT128x96x4StringDraw(const char *pcStr,
+                                    unsigned long ulX,
+                                    unsigned long ulY,
+                                    unsigned char ucLevel);
+extern void RIT128x96x4ImageDraw(const unsigned char *pucImage,
+                                   unsigned long ulX,
+                                   unsigned long ulY,
+                                   unsigned long ulWidth,
+                                   unsigned long ulHeight);
+extern void RIT128x96x4Init(unsigned long ulFrequency);
+extern void RIT128x96x4Enable(unsigned long ulFrequency);
+extern void RIT128x96x4Disable(void);
+extern void RIT128x96x4DisplayOn(void);
+extern void RIT128x96x4DisplayOff(void);
+
+#endif // __RIT128X96X4_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/rom.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/rom.h
new file mode 100644
index 0000000..d066c68
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/rom.h
@@ -0,0 +1,1251 @@
+//*****************************************************************************
+//
+// rom.h - Macros to facilitate calling functions in the ROM.
+//
+// Copyright (c) 2007-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __ROM_H__
+#define __ROM_H__
+
+//*****************************************************************************
+//
+// Pointers to the main API tables.
+//
+//*****************************************************************************
+#define ROM_APITABLE            ((unsigned long *)0x01000010)
+#define ROM_VERSION             (ROM_APITABLE[0])
+#define ROM_UARTTABLE           ((unsigned long *)(ROM_APITABLE[1]))
+#define ROM_SSITABLE            ((unsigned long *)(ROM_APITABLE[2]))
+#define ROM_I2CTABLE            ((unsigned long *)(ROM_APITABLE[3]))
+#define ROM_GPIOTABLE           ((unsigned long *)(ROM_APITABLE[4]))
+#define ROM_ADCTABLE            ((unsigned long *)(ROM_APITABLE[5]))
+#define ROM_COMPARATORTABLE     ((unsigned long *)(ROM_APITABLE[6]))
+#define ROM_FLASHTABLE          ((unsigned long *)(ROM_APITABLE[7]))
+#define ROM_PWMTABLE            ((unsigned long *)(ROM_APITABLE[8]))
+#define ROM_QEITABLE            ((unsigned long *)(ROM_APITABLE[9]))
+#define ROM_SYSTICKTABLE        ((unsigned long *)(ROM_APITABLE[10]))
+#define ROM_TIMERTABLE          ((unsigned long *)(ROM_APITABLE[11]))
+#define ROM_WATCHDOGTABLE       ((unsigned long *)(ROM_APITABLE[12]))
+#define ROM_SYSCTLTABLE         ((unsigned long *)(ROM_APITABLE[13]))
+#define ROM_INTERRUPTTABLE      ((unsigned long *)(ROM_APITABLE[14]))
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the ADC API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_ADCSequenceDataGet                                                \
+        ((long (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum,                               \
+                   unsigned long *pulBuffer))ROM_ADCTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_ADCIntDisable                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum))ROM_ADCTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_ADCIntEnable                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum))ROM_ADCTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_ADCIntStatus                                                      \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulSequenceNum,                      \
+                            tBoolean bMasked))ROM_ADCTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_ADCIntClear                                                       \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum))ROM_ADCTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_ADCSequenceEnable                                                 \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum))ROM_ADCTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_ADCSequenceDisable                                                \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum))ROM_ADCTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_ADCSequenceConfigure                                              \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum,                               \
+                   unsigned long ulTrigger,                                   \
+                   unsigned long ulPriority))ROM_ADCTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_ADCSequenceStepConfigure                                          \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum,                               \
+                   unsigned long ulStep,                                      \
+                   unsigned long ulConfig))ROM_ADCTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_ADCSequenceOverflow                                               \
+        ((long (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum))ROM_ADCTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_ADCSequenceOverflowClear                                          \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum))ROM_ADCTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_ADCSequenceUnderflow                                              \
+        ((long (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum))ROM_ADCTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_ADCSequenceUnderflowClear                                         \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum))ROM_ADCTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_ADCProcessorTrigger                                               \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum))ROM_ADCTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_ADCHardwareOversampleConfigure                                    \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulFactor))ROM_ADCTABLE[14])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Comparator API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_ComparatorIntClear                                                \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulComp))ROM_COMPARATORTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_ComparatorConfigure                                               \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulComp,                                      \
+                   unsigned long ulConfig))ROM_COMPARATORTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_ComparatorRefSet                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulRef))ROM_COMPARATORTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_ComparatorValueGet                                                \
+        ((tBoolean (*)(unsigned long ulBase,                                  \
+                       unsigned long ulComp))ROM_COMPARATORTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_ComparatorIntEnable                                               \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulComp))ROM_COMPARATORTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_ComparatorIntDisable                                              \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulComp))ROM_COMPARATORTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_ComparatorIntStatus                                               \
+        ((tBoolean (*)(unsigned long ulBase,                                  \
+                       unsigned long ulComp,                                  \
+                       tBoolean bMasked))ROM_COMPARATORTABLE[6])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Flash API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_FlashProgram                                                      \
+        ((long (*)(unsigned long *pulData,                                    \
+                   unsigned long ulAddress,                                   \
+                   unsigned long ulCount))ROM_FLASHTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_FlashUsecGet                                                      \
+        ((unsigned long (*)(void))ROM_FLASHTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_FlashUsecSet                                                      \
+        ((void (*)(unsigned long ulClocks))ROM_FLASHTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_FlashErase                                                        \
+        ((long (*)(unsigned long ulAddress))ROM_FLASHTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_FlashProtectGet                                                   \
+        ((tFlashProtection (*)(unsigned long ulAddress))ROM_FLASHTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_FlashProtectSet                                                   \
+        ((long (*)(unsigned long ulAddress,                                   \
+                   tFlashProtection eProtect))ROM_FLASHTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_FlashProtectSave                                                  \
+        ((long (*)(void))ROM_FLASHTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_FlashUserGet                                                      \
+        ((long (*)(unsigned long *pulUser0,                                   \
+                   unsigned long *pulUser1))ROM_FLASHTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_FlashUserSet                                                      \
+        ((long (*)(unsigned long ulUser0,                                     \
+                   unsigned long ulUser1))ROM_FLASHTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_FlashUserSave                                                     \
+        ((long (*)(void))ROM_FLASHTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_FlashIntEnable                                                    \
+        ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_FlashIntDisable                                                   \
+        ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_FlashIntGetStatus                                                 \
+        ((unsigned long (*)(tBoolean bMasked))ROM_FLASHTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_FlashIntClear                                                     \
+        ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[13])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the GPIO API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_GPIOPinWrite                                                      \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins,                                      \
+                   unsigned char ucVal))ROM_GPIOTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_GPIODirModeSet                                                    \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins,                                      \
+                   unsigned long ulPinIO))ROM_GPIOTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_GPIODirModeGet                                                    \
+        ((unsigned long (*)(unsigned long ulPort,                             \
+                            unsigned char ucPin))ROM_GPIOTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_GPIOIntTypeSet                                                    \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins,                                      \
+                   unsigned long ulIntType))ROM_GPIOTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_GPIOIntTypeGet                                                    \
+        ((unsigned long (*)(unsigned long ulPort,                             \
+                            unsigned char ucPin))ROM_GPIOTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_GPIOPadConfigSet                                                  \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins,                                      \
+                   unsigned long ulStrength,                                  \
+                   unsigned long ulPadType))ROM_GPIOTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_GPIOPadConfigGet                                                  \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPin,                                       \
+                   unsigned long *pulStrength,                                \
+                   unsigned long *pulPadType))ROM_GPIOTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_GPIOPinIntEnable                                                  \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_GPIOPinIntDisable                                                 \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_GPIOPinIntStatus                                                  \
+        ((long (*)(unsigned long ulPort,                                      \
+                   tBoolean bMasked))ROM_GPIOTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_GPIOPinIntClear                                                   \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_GPIOPinRead                                                       \
+        ((long (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_GPIOPinTypeCAN                                                    \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_GPIOPinTypeComparator                                             \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_GPIOPinTypeGPIOInput                                              \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_GPIOPinTypeGPIOOutput                                             \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_GPIOPinTypeI2C                                                    \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_GPIOPinTypePWM                                                    \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_GPIOPinTypeQEI                                                    \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_GPIOPinTypeSSI                                                    \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_GPIOPinTypeTimer                                                  \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_GPIOPinTypeUART                                                   \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[21])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_GPIOPinTypeGPIOOutputOD                                           \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[22])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the I2C API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CMasterDataPut                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned char ucData))ROM_I2CTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CMasterInitExpClk                                               \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulI2CClk,                                    \
+                   tBoolean bFast))ROM_I2CTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CSlaveInit                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned char ucSlaveAddr))ROM_I2CTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CMasterEnable                                                   \
+        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CSlaveEnable                                                    \
+        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CMasterDisable                                                  \
+        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CSlaveDisable                                                   \
+        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CMasterIntEnable                                                \
+        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CSlaveIntEnable                                                 \
+        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CMasterIntDisable                                               \
+        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CSlaveIntDisable                                                \
+        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CMasterIntStatus                                                \
+        ((tBoolean (*)(unsigned long ulBase,                                  \
+                       tBoolean bMasked))ROM_I2CTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CSlaveIntStatus                                                 \
+        ((tBoolean (*)(unsigned long ulBase,                                  \
+                       tBoolean bMasked))ROM_I2CTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CMasterIntClear                                                 \
+        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CSlaveIntClear                                                  \
+        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CMasterSlaveAddrSet                                             \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned char ucSlaveAddr,                                 \
+                   tBoolean bReceive))ROM_I2CTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CMasterBusy                                                     \
+        ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CMasterBusBusy                                                  \
+        ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CMasterControl                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulCmd))ROM_I2CTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CMasterErr                                                      \
+        ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CMasterDataGet                                                  \
+        ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CSlaveStatus                                                    \
+        ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[21])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CSlaveDataPut                                                   \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned char ucData))ROM_I2CTABLE[22])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_I2CSlaveDataGet                                                   \
+        ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[23])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UpdateI2C                                                         \
+        ((void (*)(void))ROM_I2CTABLE[24])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Interrupt API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_IntEnable                                                         \
+        ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_IntDisable                                                        \
+        ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_IntPriorityGroupingSet                                            \
+        ((void (*)(unsigned long ulBits))ROM_INTERRUPTTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_IntPriorityGroupingGet                                            \
+        ((unsigned long (*)(void))ROM_INTERRUPTTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_IntPrioritySet                                                    \
+        ((void (*)(unsigned long ulInterrupt,                                 \
+                   unsigned char ucPriority))ROM_INTERRUPTTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_IntPriorityGet                                                    \
+        ((long (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[7])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the PWM API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_PWMPulseWidthSet                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulPWMOut,                                    \
+                   unsigned long ulWidth))ROM_PWMTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_PWMGenConfigure                                                   \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGen,                                       \
+                   unsigned long ulConfig))ROM_PWMTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_PWMGenPeriodSet                                                   \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGen,                                       \
+                   unsigned long ulPeriod))ROM_PWMTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_PWMGenPeriodGet                                                   \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulGen))ROM_PWMTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_PWMGenEnable                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGen))ROM_PWMTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_PWMGenDisable                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGen))ROM_PWMTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_PWMPulseWidthGet                                                  \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulPWMOut))ROM_PWMTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_PWMDeadBandEnable                                                 \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGen,                                       \
+                   unsigned short usRise,                                     \
+                   unsigned short usFall))ROM_PWMTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_PWMDeadBandDisable                                                \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGen))ROM_PWMTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_PWMSyncUpdate                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGenBits))ROM_PWMTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_PWMSyncTimeBase                                                   \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGenBits))ROM_PWMTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_PWMOutputState                                                    \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulPWMOutBits,                                \
+                   tBoolean bEnable))ROM_PWMTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_PWMOutputInvert                                                   \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulPWMOutBits,                                \
+                   tBoolean bInvert))ROM_PWMTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_PWMOutputFault                                                    \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulPWMOutBits,                                \
+                   tBoolean bFaultSuppress))ROM_PWMTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_PWMGenIntTrigEnable                                               \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGen,                                       \
+                   unsigned long ulIntTrig))ROM_PWMTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_PWMGenIntTrigDisable                                              \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGen,                                       \
+                   unsigned long ulIntTrig))ROM_PWMTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_PWMGenIntStatus                                                   \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulGen,                              \
+                            tBoolean bMasked))ROM_PWMTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_PWMGenIntClear                                                    \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGen,                                       \
+                   unsigned long ulInts))ROM_PWMTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_PWMIntEnable                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGenFault))ROM_PWMTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_PWMIntDisable                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGenFault))ROM_PWMTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_PWMFaultIntClear                                                  \
+        ((void (*)(unsigned long ulBase))ROM_PWMTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_PWMIntStatus                                                      \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            tBoolean bMasked))ROM_PWMTABLE[21])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the QEI API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_QEIPositionGet                                                    \
+        ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_QEIEnable                                                         \
+        ((void (*)(unsigned long ulBase))ROM_QEITABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_QEIDisable                                                        \
+        ((void (*)(unsigned long ulBase))ROM_QEITABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_QEIConfigure                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulConfig,                                    \
+                   unsigned long ulMaxPosition))ROM_QEITABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_QEIPositionSet                                                    \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulPosition))ROM_QEITABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_QEIDirectionGet                                                   \
+        ((long (*)(unsigned long ulBase))ROM_QEITABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_QEIErrorGet                                                       \
+        ((tBoolean (*)(unsigned long ulBase))ROM_QEITABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_QEIVelocityEnable                                                 \
+        ((void (*)(unsigned long ulBase))ROM_QEITABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_QEIVelocityDisable                                                \
+        ((void (*)(unsigned long ulBase))ROM_QEITABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_QEIVelocityConfigure                                              \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulPreDiv,                                    \
+                   unsigned long ulPeriod))ROM_QEITABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_QEIVelocityGet                                                    \
+        ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_QEIIntEnable                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_QEITABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_QEIIntDisable                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_QEITABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_QEIIntStatus                                                      \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            tBoolean bMasked))ROM_QEITABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_QEIIntClear                                                       \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_QEITABLE[14])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SSI API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SSIDataPut                                                        \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulData))ROM_SSITABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SSIConfigSetExpClk                                                \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSSIClk,                                    \
+                   unsigned long ulProtocol,                                  \
+                   unsigned long ulMode,                                      \
+                   unsigned long ulBitRate,                                   \
+                   unsigned long ulDataWidth))ROM_SSITABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SSIEnable                                                         \
+        ((void (*)(unsigned long ulBase))ROM_SSITABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SSIDisable                                                        \
+        ((void (*)(unsigned long ulBase))ROM_SSITABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SSIIntEnable                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_SSITABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SSIIntDisable                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_SSITABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SSIIntStatus                                                      \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            tBoolean bMasked))ROM_SSITABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SSIIntClear                                                       \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_SSITABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SSIDataPutNonBlocking                                             \
+        ((long (*)(unsigned long ulBase,                                      \
+                   unsigned long ulData))ROM_SSITABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SSIDataGet                                                        \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long *pulData))ROM_SSITABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SSIDataGetNonBlocking                                             \
+        ((long (*)(unsigned long ulBase,                                      \
+                   unsigned long *pulData))ROM_SSITABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UpdateSSI                                                         \
+        ((void (*)(void))ROM_SSITABLE[11])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SysCtl API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlSleep                                                       \
+        ((void (*)(void))ROM_SYSCTLTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlSRAMSizeGet                                                 \
+        ((unsigned long (*)(void))ROM_SYSCTLTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlFlashSizeGet                                                \
+        ((unsigned long (*)(void))ROM_SYSCTLTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlPinPresent                                                  \
+        ((tBoolean (*)(unsigned long ulPin))ROM_SYSCTLTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlPeripheralPresent                                           \
+        ((tBoolean (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlPeripheralReset                                             \
+        ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlPeripheralEnable                                            \
+        ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlPeripheralDisable                                           \
+        ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlPeripheralSleepEnable                                       \
+        ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlPeripheralSleepDisable                                      \
+        ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlPeripheralDeepSleepEnable                                   \
+        ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlPeripheralDeepSleepDisable                                  \
+        ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlPeripheralClockGating                                       \
+        ((void (*)(tBoolean bEnable))ROM_SYSCTLTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlIntEnable                                                   \
+        ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlIntDisable                                                  \
+        ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlIntClear                                                    \
+        ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlIntStatus                                                   \
+        ((unsigned long (*)(tBoolean bMasked))ROM_SYSCTLTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlLDOSet                                                      \
+        ((void (*)(unsigned long ulVoltage))ROM_SYSCTLTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlLDOGet                                                      \
+        ((unsigned long (*)(void))ROM_SYSCTLTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlReset                                                       \
+        ((void (*)(void))ROM_SYSCTLTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlDeepSleep                                                   \
+        ((void (*)(void))ROM_SYSCTLTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlResetCauseGet                                               \
+        ((unsigned long (*)(void))ROM_SYSCTLTABLE[21])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlResetCauseClear                                             \
+        ((void (*)(unsigned long ulCauses))ROM_SYSCTLTABLE[22])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlClockSet                                                    \
+        ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[23])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlClockGet                                                    \
+        ((unsigned long (*)(void))ROM_SYSCTLTABLE[24])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlPWMClockSet                                                 \
+        ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[25])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlPWMClockGet                                                 \
+        ((unsigned long (*)(void))ROM_SYSCTLTABLE[26])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlADCSpeedSet                                                 \
+        ((void (*)(unsigned long ulSpeed))ROM_SYSCTLTABLE[27])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlADCSpeedGet                                                 \
+        ((unsigned long (*)(void))ROM_SYSCTLTABLE[28])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlGPIOAHBEnable                                               \
+        ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[29])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysCtlGPIOAHBDisable                                              \
+        ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[30])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SysTick API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysTickValueGet                                                   \
+        ((unsigned long (*)(void))ROM_SYSTICKTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysTickEnable                                                     \
+        ((void (*)(void))ROM_SYSTICKTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysTickDisable                                                    \
+        ((void (*)(void))ROM_SYSTICKTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysTickIntEnable                                                  \
+        ((void (*)(void))ROM_SYSTICKTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysTickIntDisable                                                 \
+        ((void (*)(void))ROM_SYSTICKTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysTickPeriodSet                                                  \
+        ((void (*)(unsigned long ulPeriod))ROM_SYSTICKTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_SysTickPeriodGet                                                  \
+        ((unsigned long (*)(void))ROM_SYSTICKTABLE[6])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Timer API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_TimerIntClear                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_TIMERTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_TimerEnable                                                       \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulTimer))ROM_TIMERTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_TimerDisable                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulTimer))ROM_TIMERTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_TimerConfigure                                                    \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulConfig))ROM_TIMERTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_TimerControlLevel                                                 \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulTimer,                                     \
+                   tBoolean bInvert))ROM_TIMERTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_TimerControlTrigger                                               \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulTimer,                                     \
+                   tBoolean bEnable))ROM_TIMERTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_TimerControlEvent                                                 \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulTimer,                                     \
+                   unsigned long ulEvent))ROM_TIMERTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_TimerControlStall                                                 \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulTimer,                                     \
+                   tBoolean bStall))ROM_TIMERTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_TimerRTCEnable                                                    \
+        ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_TimerRTCDisable                                                   \
+        ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_TimerPrescaleSet                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulTimer,                                     \
+                   unsigned long ulValue))ROM_TIMERTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_TimerPrescaleGet                                                  \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulTimer))ROM_TIMERTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_TimerLoadSet                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulTimer,                                     \
+                   unsigned long ulValue))ROM_TIMERTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_TimerLoadGet                                                      \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulTimer))ROM_TIMERTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_TimerValueGet                                                     \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulTimer))ROM_TIMERTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_TimerMatchSet                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulTimer,                                     \
+                   unsigned long ulValue))ROM_TIMERTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_TimerMatchGet                                                     \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulTimer))ROM_TIMERTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_TimerIntEnable                                                    \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_TIMERTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_TimerIntDisable                                                   \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_TIMERTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_TimerIntStatus                                                    \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            tBoolean bMasked))ROM_TIMERTABLE[21])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the UART API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UARTCharPut                                                       \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned char ucData))ROM_UARTTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UARTParityModeSet                                                 \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulParity))ROM_UARTTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UARTParityModeGet                                                 \
+        ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UARTFIFOLevelSet                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulTxLevel,                                   \
+                   unsigned long ulRxLevel))ROM_UARTTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UARTFIFOLevelGet                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long *pulTxLevel,                                 \
+                   unsigned long *pulRxLevel))ROM_UARTTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UARTConfigSetExpClk                                               \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulUARTClk,                                   \
+                   unsigned long ulBaud,                                      \
+                   unsigned long ulConfig))ROM_UARTTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UARTConfigGetExpClk                                               \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulUARTClk,                                   \
+                   unsigned long *pulBaud,                                    \
+                   unsigned long *pulConfig))ROM_UARTTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UARTEnable                                                        \
+        ((void (*)(unsigned long ulBase))ROM_UARTTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UARTDisable                                                       \
+        ((void (*)(unsigned long ulBase))ROM_UARTTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UARTEnableSIR                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   tBoolean bLowPower))ROM_UARTTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UARTDisableSIR                                                    \
+        ((void (*)(unsigned long ulBase))ROM_UARTTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UARTCharsAvail                                                    \
+        ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UARTSpaceAvail                                                    \
+        ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UARTCharGetNonBlocking                                            \
+        ((long (*)(unsigned long ulBase))ROM_UARTTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UARTCharGet                                                       \
+        ((long (*)(unsigned long ulBase))ROM_UARTTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UARTCharPutNonBlocking                                            \
+        ((tBoolean (*)(unsigned long ulBase,                                  \
+                       unsigned char ucData))ROM_UARTTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UARTBreakCtl                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   tBoolean bBreakState))ROM_UARTTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UARTIntEnable                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_UARTTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UARTIntDisable                                                    \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_UARTTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UARTIntStatus                                                     \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            tBoolean bMasked))ROM_UARTTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UARTIntClear                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_UARTTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_UpdateUART                                                        \
+        ((void (*)(void))ROM_UARTTABLE[21])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Watchdog API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_WatchdogIntClear                                                  \
+        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_WatchdogRunning                                                   \
+        ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_WatchdogEnable                                                    \
+        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_WatchdogResetEnable                                               \
+        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_WatchdogResetDisable                                              \
+        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_WatchdogLock                                                      \
+        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_WatchdogUnlock                                                    \
+        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_WatchdogLockState                                                 \
+        ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_WatchdogReloadSet                                                 \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulLoadVal))ROM_WATCHDOGTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_WatchdogReloadGet                                                 \
+        ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_WatchdogValueGet                                                  \
+        ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_WatchdogIntEnable                                                 \
+        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_WatchdogIntStatus                                                 \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            tBoolean bMasked))ROM_WATCHDOGTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_WatchdogStallEnable                                               \
+        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0)
+#define ROM_WatchdogStallDisable                                              \
+        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[14])
+#endif
+
+#endif // __ROM_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/ssi.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/ssi.h
new file mode 100644
index 0000000..013aadb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/ssi.h
@@ -0,0 +1,128 @@
+//*****************************************************************************
+//
+// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __SSI_H__
+#define __SSI_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear
+// as the ulIntFlags parameter, and returned by SSIIntStatus.
+//
+//*****************************************************************************
+#define SSI_TXFF                0x00000008  // TX FIFO half empty or less
+#define SSI_RXFF                0x00000004  // RX FIFO half full or less
+#define SSI_RXTO                0x00000002  // RX timeout
+#define SSI_RXOR                0x00000001  // RX overrun
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIConfigSetExpClk.
+//
+//*****************************************************************************
+#define SSI_FRF_MOTO_MODE_0     0x00000000  // Moto fmt, polarity 0, phase 0
+#define SSI_FRF_MOTO_MODE_1     0x00000002  // Moto fmt, polarity 0, phase 1
+#define SSI_FRF_MOTO_MODE_2     0x00000001  // Moto fmt, polarity 1, phase 0
+#define SSI_FRF_MOTO_MODE_3     0x00000003  // Moto fmt, polarity 1, phase 1
+#define SSI_FRF_TI              0x00000010  // TI frame format
+#define SSI_FRF_NMW             0x00000020  // National MicroWire frame format
+
+#define SSI_MODE_MASTER         0x00000000  // SSI master
+#define SSI_MODE_SLAVE          0x00000001  // SSI slave
+#define SSI_MODE_SLAVE_OD       0x00000002  // SSI slave with output disabled
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIDMAEnable() and SSIDMADisable().
+//
+//*****************************************************************************
+#define SSI_DMA_TX              0x00000002  // Enable DMA for transmit
+#define SSI_DMA_RX              0x00000001  // Enable DMA for receive
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
+                               unsigned long ulProtocol, unsigned long ulMode,
+                               unsigned long ulBitRate,
+                               unsigned long ulDataWidth);
+extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData);
+extern long SSIDataGetNonBlocking(unsigned long ulBase,
+                                  unsigned long *pulData);
+extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);
+extern long SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData);
+extern void SSIDisable(unsigned long ulBase);
+extern void SSIEnable(unsigned long ulBase);
+extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
+extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void SSIIntUnregister(unsigned long ulBase);
+extern void SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
+extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
+
+//*****************************************************************************
+//
+// Several SSI APIs have been renamed, with the original function name being
+// deprecated.  These defines provide backward compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#include "sysctl.h"
+#define SSIConfig(a, b, c, d, e)                            \
+        SSIConfigSetExpClk(a, SysCtlClockGet(), b, c, d, e)
+#define SSIDataNonBlockingGet(a, b) \
+        SSIDataGetNonBlocking(a, b)
+#define SSIDataNonBlockingPut(a, b) \
+        SSIDataPutNonBlocking(a, b)
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SSI_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/sysctl.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/sysctl.h
new file mode 100644
index 0000000..55f847f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/sysctl.h
@@ -0,0 +1,391 @@
+//*****************************************************************************
+//
+// sysctl.h - Prototypes for the system control driver.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __SYSCTL_H__
+#define __SYSCTL_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the
+// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
+// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
+// ulPeripheral parameter.  The peripherals in the fourth group (upper nibble
+// is 3) can only be used with the SysCtlPeripheralPresent() API.
+//
+//*****************************************************************************
+#define SYSCTL_PERIPH_WDOG      0x00000008  // Watchdog
+#define SYSCTL_PERIPH_HIBERNATE 0x00000040  // Hibernation module
+#define SYSCTL_PERIPH_ADC       0x00100001  // ADC
+#define SYSCTL_PERIPH_PWM       0x00100010  // PWM
+#define SYSCTL_PERIPH_CAN0      0x00100100  // CAN 0
+#define SYSCTL_PERIPH_CAN1      0x00100200  // CAN 1
+#define SYSCTL_PERIPH_CAN2      0x00100400  // CAN 2
+#define SYSCTL_PERIPH_UART0     0x10000001  // UART 0
+#define SYSCTL_PERIPH_UART1     0x10000002  // UART 1
+#define SYSCTL_PERIPH_UART2     0x10000004  // UART 2
+#ifndef DEPRECATED
+#define SYSCTL_PERIPH_SSI       0x10000010  // SSI
+#endif
+#define SYSCTL_PERIPH_SSI0      0x10000010  // SSI 0
+#define SYSCTL_PERIPH_SSI1      0x10000020  // SSI 1
+#ifndef DEPRECATED
+#define SYSCTL_PERIPH_QEI       0x10000100  // QEI
+#endif
+#define SYSCTL_PERIPH_QEI0      0x10000100  // QEI 0
+#define SYSCTL_PERIPH_QEI1      0x10000200  // QEI 1
+#ifndef DEPRECATED
+#define SYSCTL_PERIPH_I2C       0x10001000  // I2C
+#endif
+#define SYSCTL_PERIPH_I2C0      0x10001000  // I2C 0
+#define SYSCTL_PERIPH_I2C1      0x10004000  // I2C 1
+#define SYSCTL_PERIPH_TIMER0    0x10100001  // Timer 0
+#define SYSCTL_PERIPH_TIMER1    0x10100002  // Timer 1
+#define SYSCTL_PERIPH_TIMER2    0x10100004  // Timer 2
+#define SYSCTL_PERIPH_TIMER3    0x10100008  // Timer 3
+#define SYSCTL_PERIPH_COMP0     0x10100100  // Analog comparator 0
+#define SYSCTL_PERIPH_COMP1     0x10100200  // Analog comparator 1
+#define SYSCTL_PERIPH_COMP2     0x10100400  // Analog comparator 2
+#define SYSCTL_PERIPH_GPIOA     0x20000001  // GPIO A
+#define SYSCTL_PERIPH_GPIOB     0x20000002  // GPIO B
+#define SYSCTL_PERIPH_GPIOC     0x20000004  // GPIO C
+#define SYSCTL_PERIPH_GPIOD     0x20000008  // GPIO D
+#define SYSCTL_PERIPH_GPIOE     0x20000010  // GPIO E
+#define SYSCTL_PERIPH_GPIOF     0x20000020  // GPIO F
+#define SYSCTL_PERIPH_GPIOG     0x20000040  // GPIO G
+#define SYSCTL_PERIPH_GPIOH     0x20000080  // GPIO H
+#define SYSCTL_PERIPH_UDMA      0x20002000  // uDMA
+#define SYSCTL_PERIPH_USB0      0x20100001  // USB0
+#define SYSCTL_PERIPH_ETH       0x20105000  // ETH
+#define SYSCTL_PERIPH_IEEE1588  0x20100100  // IEEE1588
+#define SYSCTL_PERIPH_PLL       0x30000010  // PLL
+#define SYSCTL_PERIPH_TEMP      0x30000020  // Temperature sensor
+#define SYSCTL_PERIPH_MPU       0x30000080  // Cortex-M3 MPU
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlPinPresent() API
+// as the ulPin parameter.
+//
+//*****************************************************************************
+#define SYSCTL_PIN_PWM0         0x00000001  // PWM0 pin
+#define SYSCTL_PIN_PWM1         0x00000002  // PWM1 pin
+#define SYSCTL_PIN_PWM2         0x00000004  // PWM2 pin
+#define SYSCTL_PIN_PWM3         0x00000008  // PWM3 pin
+#define SYSCTL_PIN_PWM4         0x00000010  // PWM4 pin
+#define SYSCTL_PIN_PWM5         0x00000020  // PWM5 pin
+#define SYSCTL_PIN_PWM6         0x00000040  // PWM6 pin
+#define SYSCTL_PIN_PWM7         0x00000080  // PWM7 pin
+#define SYSCTL_PIN_C0MINUS      0x00000040  // C0- pin
+#define SYSCTL_PIN_C0PLUS       0x00000080  // C0+ pin
+#define SYSCTL_PIN_C0O          0x00000100  // C0o pin
+#define SYSCTL_PIN_C1MINUS      0x00000200  // C1- pin
+#define SYSCTL_PIN_C1PLUS       0x00000400  // C1+ pin
+#define SYSCTL_PIN_C1O          0x00000800  // C1o pin
+#define SYSCTL_PIN_C2MINUS      0x00001000  // C2- pin
+#define SYSCTL_PIN_C2PLUS       0x00002000  // C2+ pin
+#define SYSCTL_PIN_C2O          0x00004000  // C2o pin
+#define SYSCTL_PIN_MC_FAULT0    0x00008000  // MC0 Fault pin
+#define SYSCTL_PIN_ADC0         0x00010000  // ADC0 pin
+#define SYSCTL_PIN_ADC1         0x00020000  // ADC1 pin
+#define SYSCTL_PIN_ADC2         0x00040000  // ADC2 pin
+#define SYSCTL_PIN_ADC3         0x00080000  // ADC3 pin
+#define SYSCTL_PIN_ADC4         0x00100000  // ADC4 pin
+#define SYSCTL_PIN_ADC5         0x00200000  // ADC5 pin
+#define SYSCTL_PIN_ADC6         0x00400000  // ADC6 pin
+#define SYSCTL_PIN_ADC7         0x00800000  // ADC7 pin
+#define SYSCTL_PIN_CCP0         0x01000000  // CCP0 pin
+#define SYSCTL_PIN_CCP1         0x02000000  // CCP1 pin
+#define SYSCTL_PIN_CCP2         0x04000000  // CCP2 pin
+#define SYSCTL_PIN_CCP3         0x08000000  // CCP3 pin
+#define SYSCTL_PIN_CCP4         0x10000000  // CCP4 pin
+#define SYSCTL_PIN_CCP5         0x20000000  // CCP5 pin
+#define SYSCTL_PIN_32KHZ        0x80000000  // 32kHz pin
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlLDOSet() API as
+// the ulVoltage value, or returned by the SysCtlLDOGet() API.
+//
+//*****************************************************************************
+#define SYSCTL_LDO_2_25V        0x00000005  // LDO output of 2.25V
+#define SYSCTL_LDO_2_30V        0x00000004  // LDO output of 2.30V
+#define SYSCTL_LDO_2_35V        0x00000003  // LDO output of 2.35V
+#define SYSCTL_LDO_2_40V        0x00000002  // LDO output of 2.40V
+#define SYSCTL_LDO_2_45V        0x00000001  // LDO output of 2.45V
+#define SYSCTL_LDO_2_50V        0x00000000  // LDO output of 2.50V
+#define SYSCTL_LDO_2_55V        0x0000001f  // LDO output of 2.55V
+#define SYSCTL_LDO_2_60V        0x0000001e  // LDO output of 2.60V
+#define SYSCTL_LDO_2_65V        0x0000001d  // LDO output of 2.65V
+#define SYSCTL_LDO_2_70V        0x0000001c  // LDO output of 2.70V
+#define SYSCTL_LDO_2_75V        0x0000001b  // LDO output of 2.75V
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlLDOConfigSet() API.
+//
+//*****************************************************************************
+#define SYSCTL_LDOCFG_ARST      0x00000001  // Allow LDO failure to reset
+#define SYSCTL_LDOCFG_NORST     0x00000000  // Do not reset on LDO failure
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlIntEnable(),
+// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask
+// by the SysCtlIntStatus() API.
+//
+//*****************************************************************************
+#define SYSCTL_INT_PLL_LOCK     0x00000040  // PLL lock interrupt
+#define SYSCTL_INT_CUR_LIMIT    0x00000020  // Current limit interrupt
+#define SYSCTL_INT_IOSC_FAIL    0x00000010  // Internal oscillator failure int
+#define SYSCTL_INT_MOSC_FAIL    0x00000008  // Main oscillator failure int
+#define SYSCTL_INT_POR          0x00000004  // Power on reset interrupt
+#define SYSCTL_INT_BOR          0x00000002  // Brown out interrupt
+#define SYSCTL_INT_PLL_FAIL     0x00000001  // PLL failure interrupt
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlResetCauseClear()
+// API or returned by the SysCtlResetCauseGet() API.
+//
+//*****************************************************************************
+#define SYSCTL_CAUSE_LDO        0x00000020  // LDO power not OK reset
+#define SYSCTL_CAUSE_SW         0x00000010  // Software reset
+#define SYSCTL_CAUSE_WDOG       0x00000008  // Watchdog reset
+#define SYSCTL_CAUSE_BOR        0x00000004  // Brown-out reset
+#define SYSCTL_CAUSE_POR        0x00000002  // Power on reset
+#define SYSCTL_CAUSE_EXT        0x00000001  // External reset
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlBrownOutConfigSet()
+// API as the ulConfig parameter.
+//
+//*****************************************************************************
+#define SYSCTL_BOR_RESET        0x00000002  // Reset instead of interrupting
+#define SYSCTL_BOR_RESAMPLE     0x00000001  // Resample BOR before asserting
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlPWMClockSet() API
+// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()
+// API.
+//
+//*****************************************************************************
+#define SYSCTL_PWMDIV_1         0x00000000  // PWM clock is processor clock /1
+#define SYSCTL_PWMDIV_2         0x00100000  // PWM clock is processor clock /2
+#define SYSCTL_PWMDIV_4         0x00120000  // PWM clock is processor clock /4
+#define SYSCTL_PWMDIV_8         0x00140000  // PWM clock is processor clock /8
+#define SYSCTL_PWMDIV_16        0x00160000  // PWM clock is processor clock /16
+#define SYSCTL_PWMDIV_32        0x00180000  // PWM clock is processor clock /32
+#define SYSCTL_PWMDIV_64        0x001A0000  // PWM clock is processor clock /64
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlADCSpeedSet() API
+// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()
+// API.
+//
+//*****************************************************************************
+#define SYSCTL_ADCSPEED_1MSPS   0x00000300  // 1,000,000 samples per second
+#define SYSCTL_ADCSPEED_500KSPS 0x00000200  // 500,000 samples per second
+#define SYSCTL_ADCSPEED_250KSPS 0x00000100  // 250,000 samples per second
+#define SYSCTL_ADCSPEED_125KSPS 0x00000000  // 125,000 samples per second
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlClockSet() API as
+// the ulConfig parameter.
+//
+//*****************************************************************************
+#define SYSCTL_SYSDIV_1         0x07800000  // Processor clock is osc/pll /1
+#define SYSCTL_SYSDIV_2         0x00C00000  // Processor clock is osc/pll /2
+#define SYSCTL_SYSDIV_3         0x01400000  // Processor clock is osc/pll /3
+#define SYSCTL_SYSDIV_4         0x01C00000  // Processor clock is osc/pll /4
+#define SYSCTL_SYSDIV_5         0x02400000  // Processor clock is osc/pll /5
+#define SYSCTL_SYSDIV_6         0x02C00000  // Processor clock is osc/pll /6
+#define SYSCTL_SYSDIV_7         0x03400000  // Processor clock is osc/pll /7
+#define SYSCTL_SYSDIV_8         0x03C00000  // Processor clock is osc/pll /8
+#define SYSCTL_SYSDIV_9         0x04400000  // Processor clock is osc/pll /9
+#define SYSCTL_SYSDIV_10        0x04C00000  // Processor clock is osc/pll /10
+#define SYSCTL_SYSDIV_11        0x05400000  // Processor clock is osc/pll /11
+#define SYSCTL_SYSDIV_12        0x05C00000  // Processor clock is osc/pll /12
+#define SYSCTL_SYSDIV_13        0x06400000  // Processor clock is osc/pll /13
+#define SYSCTL_SYSDIV_14        0x06C00000  // Processor clock is osc/pll /14
+#define SYSCTL_SYSDIV_15        0x07400000  // Processor clock is osc/pll /15
+#define SYSCTL_SYSDIV_16        0x07C00000  // Processor clock is osc/pll /16
+#define SYSCTL_SYSDIV_17        0x88400000  // Processor clock is osc/pll /17
+#define SYSCTL_SYSDIV_18        0x88C00000  // Processor clock is osc/pll /18
+#define SYSCTL_SYSDIV_19        0x89400000  // Processor clock is osc/pll /19
+#define SYSCTL_SYSDIV_20        0x89C00000  // Processor clock is osc/pll /20
+#define SYSCTL_SYSDIV_21        0x8A400000  // Processor clock is osc/pll /21
+#define SYSCTL_SYSDIV_22        0x8AC00000  // Processor clock is osc/pll /22
+#define SYSCTL_SYSDIV_23        0x8B400000  // Processor clock is osc/pll /23
+#define SYSCTL_SYSDIV_24        0x8BC00000  // Processor clock is osc/pll /24
+#define SYSCTL_SYSDIV_25        0x8C400000  // Processor clock is osc/pll /25
+#define SYSCTL_SYSDIV_26        0x8CC00000  // Processor clock is osc/pll /26
+#define SYSCTL_SYSDIV_27        0x8D400000  // Processor clock is osc/pll /27
+#define SYSCTL_SYSDIV_28        0x8DC00000  // Processor clock is osc/pll /28
+#define SYSCTL_SYSDIV_29        0x8E400000  // Processor clock is osc/pll /29
+#define SYSCTL_SYSDIV_30        0x8EC00000  // Processor clock is osc/pll /30
+#define SYSCTL_SYSDIV_31        0x8F400000  // Processor clock is osc/pll /31
+#define SYSCTL_SYSDIV_32        0x8FC00000  // Processor clock is osc/pll /32
+#define SYSCTL_SYSDIV_33        0x90400000  // Processor clock is osc/pll /33
+#define SYSCTL_SYSDIV_34        0x90C00000  // Processor clock is osc/pll /34
+#define SYSCTL_SYSDIV_35        0x91400000  // Processor clock is osc/pll /35
+#define SYSCTL_SYSDIV_36        0x91C00000  // Processor clock is osc/pll /36
+#define SYSCTL_SYSDIV_37        0x92400000  // Processor clock is osc/pll /37
+#define SYSCTL_SYSDIV_38        0x92C00000  // Processor clock is osc/pll /38
+#define SYSCTL_SYSDIV_39        0x93400000  // Processor clock is osc/pll /39
+#define SYSCTL_SYSDIV_40        0x93C00000  // Processor clock is osc/pll /40
+#define SYSCTL_SYSDIV_41        0x94400000  // Processor clock is osc/pll /41
+#define SYSCTL_SYSDIV_42        0x94C00000  // Processor clock is osc/pll /42
+#define SYSCTL_SYSDIV_43        0x95400000  // Processor clock is osc/pll /43
+#define SYSCTL_SYSDIV_44        0x95C00000  // Processor clock is osc/pll /44
+#define SYSCTL_SYSDIV_45        0x96400000  // Processor clock is osc/pll /45
+#define SYSCTL_SYSDIV_46        0x96C00000  // Processor clock is osc/pll /46
+#define SYSCTL_SYSDIV_47        0x97400000  // Processor clock is osc/pll /47
+#define SYSCTL_SYSDIV_48        0x97C00000  // Processor clock is osc/pll /48
+#define SYSCTL_SYSDIV_49        0x98400000  // Processor clock is osc/pll /49
+#define SYSCTL_SYSDIV_50        0x98C00000  // Processor clock is osc/pll /50
+#define SYSCTL_SYSDIV_51        0x99400000  // Processor clock is osc/pll /51
+#define SYSCTL_SYSDIV_52        0x99C00000  // Processor clock is osc/pll /52
+#define SYSCTL_SYSDIV_53        0x9A400000  // Processor clock is osc/pll /53
+#define SYSCTL_SYSDIV_54        0x9AC00000  // Processor clock is osc/pll /54
+#define SYSCTL_SYSDIV_55        0x9B400000  // Processor clock is osc/pll /55
+#define SYSCTL_SYSDIV_56        0x9BC00000  // Processor clock is osc/pll /56
+#define SYSCTL_SYSDIV_57        0x9C400000  // Processor clock is osc/pll /57
+#define SYSCTL_SYSDIV_58        0x9CC00000  // Processor clock is osc/pll /58
+#define SYSCTL_SYSDIV_59        0x9D400000  // Processor clock is osc/pll /59
+#define SYSCTL_SYSDIV_60        0x9DC00000  // Processor clock is osc/pll /60
+#define SYSCTL_SYSDIV_61        0x9E400000  // Processor clock is osc/pll /61
+#define SYSCTL_SYSDIV_62        0x9EC00000  // Processor clock is osc/pll /62
+#define SYSCTL_SYSDIV_63        0x9F400000  // Processor clock is osc/pll /63
+#define SYSCTL_SYSDIV_64        0x9FC00000  // Processor clock is osc/pll /64
+#define SYSCTL_USE_PLL          0x00000000  // System clock is the PLL clock
+#define SYSCTL_USE_OSC          0x00003800  // System clock is the osc clock
+#define SYSCTL_XTAL_1MHZ        0x00000000  // External crystal is 1MHz
+#define SYSCTL_XTAL_1_84MHZ     0x00000040  // External crystal is 1.8432MHz
+#define SYSCTL_XTAL_2MHZ        0x00000080  // External crystal is 2MHz
+#define SYSCTL_XTAL_2_45MHZ     0x000000C0  // External crystal is 2.4576MHz
+#define SYSCTL_XTAL_3_57MHZ     0x00000100  // External crystal is 3.579545MHz
+#define SYSCTL_XTAL_3_68MHZ     0x00000140  // External crystal is 3.6864MHz
+#define SYSCTL_XTAL_4MHZ        0x00000180  // External crystal is 4MHz
+#define SYSCTL_XTAL_4_09MHZ     0x000001C0  // External crystal is 4.096MHz
+#define SYSCTL_XTAL_4_91MHZ     0x00000200  // External crystal is 4.9152MHz
+#define SYSCTL_XTAL_5MHZ        0x00000240  // External crystal is 5MHz
+#define SYSCTL_XTAL_5_12MHZ     0x00000280  // External crystal is 5.12MHz
+#define SYSCTL_XTAL_6MHZ        0x000002C0  // External crystal is 6MHz
+#define SYSCTL_XTAL_6_14MHZ     0x00000300  // External crystal is 6.144MHz
+#define SYSCTL_XTAL_7_37MHZ     0x00000340  // External crystal is 7.3728MHz
+#define SYSCTL_XTAL_8MHZ        0x00000380  // External crystal is 8MHz
+#define SYSCTL_XTAL_8_19MHZ     0x000003C0  // External crystal is 8.192MHz
+#define SYSCTL_XTAL_10MHZ       0x00000400  // External crystal is 10 MHz
+#define SYSCTL_XTAL_12MHZ       0x00000440  // External crystal is 12 MHz
+#define SYSCTL_XTAL_12_2MHZ     0x00000480  // External crystal is 12.288 MHz
+#define SYSCTL_XTAL_13_5MHZ     0x000004C0  // External crystal is 13.56 MHz
+#define SYSCTL_XTAL_14_3MHZ     0x00000500  // External crystal is 14.31818 MHz
+#define SYSCTL_XTAL_16MHZ       0x00000540  // External crystal is 16 MHz
+#define SYSCTL_XTAL_16_3MHZ     0x00000580  // External crystal is 16.384 MHz
+#define SYSCTL_OSC_MAIN         0x00000000  // Oscillator source is main osc
+#define SYSCTL_OSC_INT          0x00000010  // Oscillator source is int. osc
+#define SYSCTL_OSC_INT4         0x00000020  // Oscillator source is int. osc /4
+#define SYSCTL_OSC_INT30        0x80000030  // Oscillator source is int. 30 KHz
+#define SYSCTL_OSC_EXT32        0x80000038  // Oscillator source is ext. 32 KHz
+#define SYSCTL_INT_OSC_DIS      0x00000002  // Disable internal oscillator
+#define SYSCTL_MAIN_OSC_DIS     0x00000001  // Disable main oscillator
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern unsigned long SysCtlSRAMSizeGet(void);
+extern unsigned long SysCtlFlashSizeGet(void);
+extern tBoolean SysCtlPinPresent(unsigned long ulPin);
+extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);
+extern void SysCtlPeripheralReset(unsigned long ulPeripheral);
+extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralClockGating(tBoolean bEnable);
+extern void SysCtlIntRegister(void (*pfnHandler)(void));
+extern void SysCtlIntUnregister(void);
+extern void SysCtlIntEnable(unsigned long ulInts);
+extern void SysCtlIntDisable(unsigned long ulInts);
+extern void SysCtlIntClear(unsigned long ulInts);
+extern unsigned long SysCtlIntStatus(tBoolean bMasked);
+extern void SysCtlLDOSet(unsigned long ulVoltage);
+extern unsigned long SysCtlLDOGet(void);
+extern void SysCtlLDOConfigSet(unsigned long ulConfig);
+extern void SysCtlReset(void);
+extern void SysCtlSleep(void);
+extern void SysCtlDeepSleep(void);
+extern unsigned long SysCtlResetCauseGet(void);
+extern void SysCtlResetCauseClear(unsigned long ulCauses);
+extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,
+                                    unsigned long ulDelay);
+extern void SysCtlDelay(unsigned long ulCount);
+extern void SysCtlClockSet(unsigned long ulConfig);
+extern unsigned long SysCtlClockGet(void);
+extern void SysCtlPWMClockSet(unsigned long ulConfig);
+extern unsigned long SysCtlPWMClockGet(void);
+extern void SysCtlADCSpeedSet(unsigned long ulSpeed);
+extern unsigned long SysCtlADCSpeedGet(void);
+extern void SysCtlIOSCVerificationSet(tBoolean bEnable);
+extern void SysCtlMOSCVerificationSet(tBoolean bEnable);
+extern void SysCtlPLLVerificationSet(tBoolean bEnable);
+extern void SysCtlClkVerificationClear(void);
+extern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral);
+extern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral);
+extern void SysCtlUSBPLLEnable(void);
+extern void SysCtlUSBPLLDisable(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SYSCTL_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/systick.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/systick.h
new file mode 100644
index 0000000..cdab807
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/systick.h
@@ -0,0 +1,67 @@
+//*****************************************************************************
+//
+// systick.h - Prototypes for the SysTick driver.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __SYSTICK_H__
+#define __SYSTICK_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void SysTickEnable(void);
+extern void SysTickDisable(void);
+extern void SysTickIntRegister(void (*pfnHandler)(void));
+extern void SysTickIntUnregister(void);
+extern void SysTickIntEnable(void);
+extern void SysTickIntDisable(void);
+extern void SysTickPeriodSet(unsigned long ulPeriod);
+extern unsigned long SysTickPeriodGet(void);
+extern unsigned long SysTickValueGet(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SYSTICK_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/timer.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/timer.h
new file mode 100644
index 0000000..34a6177
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/timer.h
@@ -0,0 +1,154 @@
+//*****************************************************************************
+//
+// timer.h - Prototypes for the timer module
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __TIMER_H__
+#define __TIMER_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerConfigure as the ulConfig parameter.
+//
+//*****************************************************************************
+#define TIMER_CFG_32_BIT_OS     0x00000001  // 32-bit one-shot timer
+#define TIMER_CFG_32_BIT_PER    0x00000002  // 32-bit periodic timer
+#define TIMER_CFG_32_RTC        0x01000000  // 32-bit RTC timer
+#define TIMER_CFG_16_BIT_PAIR   0x04000000  // Two 16-bit timers
+#define TIMER_CFG_A_ONE_SHOT    0x00000001  // Timer A one-shot timer
+#define TIMER_CFG_A_PERIODIC    0x00000002  // Timer A periodic timer
+#define TIMER_CFG_A_CAP_COUNT   0x00000003  // Timer A event counter
+#define TIMER_CFG_A_CAP_TIME    0x00000007  // Timer A event timer
+#define TIMER_CFG_A_PWM         0x0000000A  // Timer A PWM output
+#define TIMER_CFG_B_ONE_SHOT    0x00000100  // Timer B one-shot timer
+#define TIMER_CFG_B_PERIODIC    0x00000200  // Timer B periodic timer
+#define TIMER_CFG_B_CAP_COUNT   0x00000300  // Timer B event counter
+#define TIMER_CFG_B_CAP_TIME    0x00000700  // Timer B event timer
+#define TIMER_CFG_B_PWM         0x00000A00  // Timer B PWM output
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and
+// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
+//
+//*****************************************************************************
+#define TIMER_CAPB_EVENT        0x00000400  // CaptureB event interrupt
+#define TIMER_CAPB_MATCH        0x00000200  // CaptureB match interrupt
+#define TIMER_TIMB_TIMEOUT      0x00000100  // TimerB time out interrupt
+#define TIMER_RTC_MATCH         0x00000008  // RTC interrupt mask
+#define TIMER_CAPA_EVENT        0x00000004  // CaptureA event interrupt
+#define TIMER_CAPA_MATCH        0x00000002  // CaptureA match interrupt
+#define TIMER_TIMA_TIMEOUT      0x00000001  // TimerA time out interrupt
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerControlEvent as the ulEvent parameter.
+//
+//*****************************************************************************
+#define TIMER_EVENT_POS_EDGE    0x00000000  // Count positive edges
+#define TIMER_EVENT_NEG_EDGE    0x00000404  // Count negative edges
+#define TIMER_EVENT_BOTH_EDGES  0x00000C0C  // Count both edges
+
+//*****************************************************************************
+//
+// Values that can be passed to most of the timer APIs as the ulTimer
+// parameter.
+//
+//*****************************************************************************
+#define TIMER_A                 0x000000ff  // Timer A
+#define TIMER_B                 0x0000ff00  // Timer B
+#define TIMER_BOTH              0x0000ffff  // Timer Both
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);
+extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);
+extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);
+extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
+                              tBoolean bInvert);
+extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
+                                tBoolean bEnable);
+extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
+                              unsigned long ulEvent);
+extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
+                              tBoolean bStall);
+extern void TimerRTCEnable(unsigned long ulBase);
+extern void TimerRTCDisable(unsigned long ulBase);
+extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
+                             unsigned long ulValue);
+extern unsigned long TimerPrescaleGet(unsigned long ulBase,
+                                      unsigned long ulTimer);
+extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
+                         unsigned long ulValue);
+extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
+extern unsigned long TimerValueGet(unsigned long ulBase,
+                                   unsigned long ulTimer);
+extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
+                          unsigned long ulValue);
+extern unsigned long TimerMatchGet(unsigned long ulBase,
+                                   unsigned long ulTimer);
+extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
+                             void (*pfnHandler)(void));
+extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
+extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+
+//*****************************************************************************
+//
+// TimerQuiesce() has been deprecated.  SysCtlPeripheralReset() should be used
+// instead to return the timer to its reset state.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+extern void TimerQuiesce(unsigned long ulBase);
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __TIMER_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/uart.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/uart.h
new file mode 100644
index 0000000..eb286f8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/uart.h
@@ -0,0 +1,178 @@
+//*****************************************************************************
+//
+// uart.h - Defines and Macros for the UART.
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __UART_H__
+#define __UART_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
+// as the ulIntFlags parameter, and returned from UARTIntStatus.
+//
+//*****************************************************************************
+#define UART_INT_OE             0x400       // Overrun Error Interrupt Mask
+#define UART_INT_BE             0x200       // Break Error Interrupt Mask
+#define UART_INT_PE             0x100       // Parity Error Interrupt Mask
+#define UART_INT_FE             0x080       // Framing Error Interrupt Mask
+#define UART_INT_RT             0x040       // Receive Timeout Interrupt Mask
+#define UART_INT_TX             0x020       // Transmit Interrupt Mask
+#define UART_INT_RX             0x010       // Receive Interrupt Mask
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter
+// and returned by UARTConfigGetExpClk in the pulConfig parameter.
+// Additionally, the UART_CONFIG_PAR_* subset can be passed to
+// UARTParityModeSet as the ulParity parameter, and are returned by
+// UARTParityModeGet.
+//
+//*****************************************************************************
+#define UART_CONFIG_WLEN_MASK   0x00000060  // Mask for extracting word length
+#define UART_CONFIG_WLEN_8      0x00000060  // 8 bit data
+#define UART_CONFIG_WLEN_7      0x00000040  // 7 bit data
+#define UART_CONFIG_WLEN_6      0x00000020  // 6 bit data
+#define UART_CONFIG_WLEN_5      0x00000000  // 5 bit data
+#define UART_CONFIG_STOP_MASK   0x00000008  // Mask for extracting stop bits
+#define UART_CONFIG_STOP_ONE    0x00000000  // One stop bit
+#define UART_CONFIG_STOP_TWO    0x00000008  // Two stop bits
+#define UART_CONFIG_PAR_MASK    0x00000086  // Mask for extracting parity
+#define UART_CONFIG_PAR_NONE    0x00000000  // No parity
+#define UART_CONFIG_PAR_EVEN    0x00000006  // Even parity
+#define UART_CONFIG_PAR_ODD     0x00000002  // Odd parity
+#define UART_CONFIG_PAR_ONE     0x00000086  // Parity bit is one
+#define UART_CONFIG_PAR_ZERO    0x00000082  // Parity bit is zero
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and
+// returned by UARTFIFOLevelGet in the pulTxLevel.
+//
+//*****************************************************************************
+#define UART_FIFO_TX1_8         0x00000000  // Transmit interrupt at 1/8 Full
+#define UART_FIFO_TX2_8         0x00000001  // Transmit interrupt at 1/4 Full
+#define UART_FIFO_TX4_8         0x00000002  // Transmit interrupt at 1/2 Full
+#define UART_FIFO_TX6_8         0x00000003  // Transmit interrupt at 3/4 Full
+#define UART_FIFO_TX7_8         0x00000004  // Transmit interrupt at 7/8 Full
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and
+// returned by UARTFIFOLevelGet in the pulRxLevel.
+//
+//*****************************************************************************
+#define UART_FIFO_RX1_8         0x00000000  // Receive interrupt at 1/8 Full
+#define UART_FIFO_RX2_8         0x00000008  // Receive interrupt at 1/4 Full
+#define UART_FIFO_RX4_8         0x00000010  // Receive interrupt at 1/2 Full
+#define UART_FIFO_RX6_8         0x00000018  // Receive interrupt at 3/4 Full
+#define UART_FIFO_RX7_8         0x00000020  // Receive interrupt at 7/8 Full
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTDMAEnable() and UARTDMADisable().
+//
+//*****************************************************************************
+#define UART_DMA_ERR_RXSTOP     0x00000004  // Stop DMA receive if UART error
+#define UART_DMA_TX             0x00000002  // Enable DMA for transmit
+#define UART_DMA_RX             0x00000001  // Enable DMA for receive
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);
+extern unsigned long UARTParityModeGet(unsigned long ulBase);
+extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
+                             unsigned long ulRxLevel);
+extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
+                             unsigned long *pulRxLevel);
+extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
+                                unsigned long ulBaud, unsigned long ulConfig);
+extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
+                                unsigned long *pulBaud,
+                                unsigned long *pulConfig);
+extern void UARTEnable(unsigned long ulBase);
+extern void UARTDisable(unsigned long ulBase);
+extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower);
+extern void UARTDisableSIR(unsigned long ulBase);
+extern tBoolean UARTCharsAvail(unsigned long ulBase);
+extern tBoolean UARTSpaceAvail(unsigned long ulBase);
+extern long UARTCharGetNonBlocking(unsigned long ulBase);
+extern long UARTCharGet(unsigned long ulBase);
+extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase,
+                                       unsigned char ucData);
+extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);
+extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);
+extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
+extern void UARTIntUnregister(unsigned long ulBase);
+extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
+extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
+
+//*****************************************************************************
+//
+// Several UART APIs have been renamed, with the original function name being
+// deprecated.  These defines provide backward compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#include "sysctl.h"
+#define UARTConfigSet(a, b, c)                         \
+        UARTConfigSetExpClk(a, SysCtlClockGet(), b, c)
+#define UARTConfigGet(a, b, c)                         \
+        UARTConfigGetExpClk(a, SysCtlClockGet(), b, c)
+#define UARTCharNonBlockingGet(a) \
+        UARTCharGetNonBlocking(a)
+#define UARTCharNonBlockingPut(a, b) \
+        UARTCharPutNonBlocking(a, b)
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif //  __UART_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/ustdlib.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/ustdlib.c
new file mode 100644
index 0000000..e68b143
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/ustdlib.c
@@ -0,0 +1,670 @@
+//*****************************************************************************
+//
+// ustdlib.c - Simple standard library functions.
+//
+// Copyright (c) 2007 Luminary Micro, Inc.  All rights reserved.
+//
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  Any use in violation
+// of the foregoing restrictions may subject the user to criminal sanctions
+// under applicable laws, as well as to civil liability for the breach of the
+// terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+//*****************************************************************************
+
+#include 
+#include 
+#include "debug.h"
+
+//*****************************************************************************
+//
+//! \addtogroup utilities_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// A mapping from an integer between 0 and 15 to its ASCII character
+// equivalent.
+//
+//*****************************************************************************
+static const char * const g_pcHex = "0123456789abcdef";
+
+//*****************************************************************************
+//
+//! A simple vsnprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X.
+//!
+//! \param pcBuf points to the buffer where the converted string is stored.
+//! \param ulSize is the size of the buffer.
+//! \param pcString is the format string.
+//! \param vaArgP is the list of optional arguments, which depend on the
+//! contents of the format string.
+//!
+//! This function is very similar to the C library vsnprintf()
+//! function. Only the following formatting characters are supported:
+//!
+//! - \%c to print a character
+//! - \%d to print a decimal value
+//! - \%s to print a string
+//! - \%u to print an unsigned decimal value
+//! - \%x to print a hexadecimal value using lower case letters
+//! - \%X to print a hexadecimal value using lower case letters (not upper case
+//! letters as would typically be used)
+//! - \%\% to print out a \% character
+//!
+//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \%
+//! and the format character, which specifies the minimum number of characters
+//! to use for that value; if preceeded by a 0 then the extra characters will
+//! be filled with zeros instead of spaces.  For example, ``\%8d'' will use
+//! eight characters to print the decimal value with spaces added to reach
+//! eight; ``\%08d'' will use eight characters as well but will add zeros
+//! instead of spaces.
+//!
+//! The type of the arguments after \b pcString must match the requirements of
+//! the format string.  For example, if an integer was passed where a string
+//! was expected, an error of some kind will most likely occur.
+//!
+//! The \b ulSize parameter limits the number of characters that will be
+//! stored in the buffer pointed to by \b pcBuf to prevent the possibility
+//! of a buffer overflow.  The buffer size should be large enough to hold
+//! the expected converted output string, including the null termination
+//! character.
+//!
+//! The function will return the number of characters that would be
+//! converted as if there were no limit on the buffer size.  Therefore
+//! it is possible for the function to return a count that is greater than
+//! the specified buffer size.  If this happens, it means that the output
+//! was truncated.
+//!
+//! \return the number of characters that were to be stored, not including
+//! the NULL termination character, regardless of space in the buffer.
+//
+//*****************************************************************************
+int
+uvsnprintf(char *pcBuf, unsigned long ulSize, const char *pcString,
+           va_list vaArgP)
+{
+    unsigned long ulIdx, ulValue, ulCount, ulBase;
+    char *pcStr, cFill;
+    int iConvertCount = 0;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(pcString != 0);
+    ASSERT(pcBuf != 0);
+    ASSERT(ulSize != 0);
+
+    //
+    // Adjust buffer size limit to allow one space for null termination.
+    //
+    if(ulSize)
+    {
+        ulSize--;
+    }
+
+    //
+    // Initialize the count of characters converted.
+    //
+    iConvertCount = 0;
+
+    //
+    // Loop while there are more characters in the format string.
+    //
+    while(*pcString)
+    {
+        //
+        // Find the first non-% character, or the end of the string.
+        //
+        for(ulIdx = 0; (pcString[ulIdx] != '%') && (pcString[ulIdx] != '\0');
+            ulIdx++)
+        {
+        }
+
+        //
+        // Write this portion of the string to the output buffer.  If
+        // there are more characters to write than there is space in the
+        // buffer, then only write as much as will fit in the buffer.
+        //
+        if(ulIdx > ulSize)
+        {
+            strncpy(pcBuf, pcString, ulSize);
+            pcBuf += ulSize;
+            ulSize = 0;
+        }
+        else
+        {
+            strncpy(pcBuf, pcString, ulIdx);
+            pcBuf += ulIdx;
+            ulSize -= ulIdx;
+        }
+
+        //
+        // Update the conversion count.  This will be the number of
+        // characters that should have been written, even if there was
+        // not room in the buffer.
+        //
+        iConvertCount += ulIdx;
+
+        //
+        // Skip the portion of the format string that was written.
+        //
+        pcString += ulIdx;
+
+        //
+        // See if the next character is a %.
+        //
+        if(*pcString == '%')
+        {
+            //
+            // Skip the %.
+            //
+            pcString++;
+
+            //
+            // Set the digit count to zero, and the fill character to space
+            // (i.e. to the defaults).
+            //
+            ulCount = 0;
+            cFill = ' ';
+
+            //
+            // It may be necessary to get back here to process more characters.
+            // Goto's aren't pretty, but effective.  I feel extremely dirty for
+            // using not one but two of the beasts.
+            //
+again:
+
+            //
+            // Determine how to handle the next character.
+            //
+            switch(*pcString++)
+            {
+                //
+                // Handle the digit characters.
+                //
+                case '0':
+                case '1':
+                case '2':
+                case '3':
+                case '4':
+                case '5':
+                case '6':
+                case '7':
+                case '8':
+                case '9':
+                {
+                    //
+                    // If this is a zero, and it is the first digit, then the
+                    // fill character is a zero instead of a space.
+                    //
+                    if((pcString[-1] == '0') && (ulCount == 0))
+                    {
+                        cFill = '0';
+                    }
+
+                    //
+                    // Update the digit count.
+                    //
+                    ulCount *= 10;
+                    ulCount += pcString[-1] - '0';
+
+                    //
+                    // Get the next character.
+                    //
+                    goto again;
+                }
+
+                //
+                // Handle the %c command.
+                //
+                case 'c':
+                {
+                    //
+                    // Get the value from the varargs.
+                    //
+                    ulValue = va_arg(vaArgP, unsigned long);
+
+                    //
+                    // Copy the character to the output buffer, if
+                    // there is room.  Update the buffer size remaining.
+                    //
+                    if(ulSize != 0)
+                    {
+                        *pcBuf++ = (char)ulValue;
+                        ulSize--;
+                    }
+
+                    //
+                    // Update the conversion count.
+                    //
+                    iConvertCount++;
+
+                    //
+                    // This command has been handled.
+                    //
+                    break;
+                }
+
+                //
+                // Handle the %d command.
+                //
+                case 'd':
+                {
+                    //
+                    // Get the value from the varargs.
+                    //
+                    ulValue = va_arg(vaArgP, unsigned long);
+
+                    //
+                    // If the value is negative, make it positive and stick a
+                    // minus sign in the beginning of the buffer.
+                    //
+                    if((long)ulValue < 0)
+                    {
+                        ulValue = -(long)ulValue;
+
+                        if(ulSize != 0)
+                        {
+                            *pcBuf++ = '-';
+                            ulSize--;
+                        }
+
+                        //
+                        // Update the conversion count.
+                        //
+                        iConvertCount++;
+                    }
+
+                    //
+                    // Set the base to 10.
+                    //
+                    ulBase = 10;
+
+                    //
+                    // Convert the value to ASCII.
+                    //
+                    goto convert;
+                }
+
+                //
+                // Handle the %s command.
+                //
+                case 's':
+                {
+                    //
+                    // Get the string pointer from the varargs.
+                    //
+                    pcStr = va_arg(vaArgP, char *);
+
+                    //
+                    // Determine the length of the string.
+                    //
+                    for(ulIdx = 0; pcStr[ulIdx] != '\0'; ulIdx++)
+                    {
+                    }
+
+                    //
+                    // Copy the string to the output buffer.  Only copy
+                    // as much as will fit in the buffer.  Update the
+                    // output buffer pointer and the space remaining.
+                    //
+                    if(ulIdx > ulSize)
+                    {
+                        strncpy(pcBuf, pcStr, ulSize);
+                        pcBuf += ulSize;
+                        ulSize = 0;
+                    }
+                    else
+                    {
+                        strncpy(pcBuf, pcStr, ulIdx);
+                        pcBuf += ulIdx;
+                        ulSize -= ulIdx;
+                    }
+
+                    //
+                    // Update the conversion count.  This will be the number of
+                    // characters that should have been written, even if there
+                    // was not room in the buffer.
+                    //
+                    iConvertCount += ulIdx;
+
+                    //
+                    //
+                    // This command has been handled.
+                    //
+                    break;
+                }
+
+                //
+                // Handle the %u command.
+                //
+                case 'u':
+                {
+                    //
+                    // Get the value from the varargs.
+                    //
+                    ulValue = va_arg(vaArgP, unsigned long);
+
+                    //
+                    // Set the base to 10.
+                    //
+                    ulBase = 10;
+
+                    //
+                    // Convert the value to ASCII.
+                    //
+                    goto convert;
+                }
+
+                //
+                // Handle the %x and %X commands.  Note that they are treated
+                // identically; i.e. %X will use lower case letters for a-f
+                // instead of the upper case letters is should use.
+                //
+                case 'x':
+                case 'X':
+                {
+                    //
+                    // Get the value from the varargs.
+                    //
+                    ulValue = va_arg(vaArgP, unsigned long);
+
+                    //
+                    // Set the base to 16.
+                    //
+                    ulBase = 16;
+
+                    //
+                    // Determine the number of digits in the string version of
+                    // the value.
+                    //
+convert:
+                    for(ulIdx = 1;
+                        (((ulIdx * ulBase) <= ulValue) &&
+                         (((ulIdx * ulBase) / ulBase) == ulIdx));
+                        ulIdx *= ulBase, ulCount--)
+                    {
+                    }
+
+                    //
+                    // Provide additional padding at the beginning of the
+                    // string conversion if needed.
+                    //
+                    if((ulCount > 1) && (ulCount < 16))
+                    {
+                        for(ulCount--; ulCount; ulCount--)
+                        {
+                            //
+                            // Copy the character to the output buffer if
+                            // there is room.
+                            //
+                            if(ulSize != 0)
+                            {
+                                *pcBuf++ = cFill;
+                                ulSize--;
+                            }
+
+                            //
+                            // Update the conversion count.
+                            //
+                            iConvertCount++;
+                        }
+                    }
+
+                    //
+                    // Convert the value into a string.
+                    //
+                    for(; ulIdx; ulIdx /= ulBase)
+                    {
+                        //
+                        // Copy the character to the output buffer if
+                        // there is room.
+                        //
+                        if(ulSize != 0)
+                        {
+                            *pcBuf++ = g_pcHex[(ulValue / ulIdx) % ulBase];
+                            ulSize--;
+                        }
+
+                        //
+                        // Update the conversion count.
+                        //
+                        iConvertCount++;
+                    }
+
+                    //
+                    // This command has been handled.
+                    //
+                    break;
+                }
+
+                //
+                // Handle the %% command.
+                //
+                case '%':
+                {
+                    //
+                    // Simply write a single %.
+                    //
+                    if(ulSize != 0)
+                    {
+                        *pcBuf++ = pcString[-1];
+                        ulSize--;
+                    }
+
+                    //
+                    // Update the conversion count.
+                    //
+                    iConvertCount++;
+
+                    //
+                    // This command has been handled.
+                    //
+                    break;
+                }
+
+                //
+                // Handle all other commands.
+                //
+                default:
+                {
+                    //
+                    // Indicate an error.
+                    //
+                    if(ulSize >= 5)
+                    {
+                        strncpy(pcBuf, "ERROR", 5);
+                        pcBuf += 5;
+                        ulSize -= 5;
+                    }
+                    else
+                    {
+                        strncpy(pcBuf, "ERROR", ulSize);
+                        pcBuf += ulSize;
+                        ulSize = 0;
+                    }
+
+                    //
+                    // Update the conversion count.
+                    //
+                    iConvertCount += 5;
+
+                    //
+                    // This command has been handled.
+                    //
+                    break;
+                }
+            }
+        }
+    }
+
+    //
+    // Null terminate the string in the buffer.
+    //
+    *pcBuf = 0;
+    return(iConvertCount);
+}
+
+//*****************************************************************************
+//
+//! A simple sprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X.
+//!
+//! \param pcBuf is the buffer where the converted string is stored.
+//! \param pcString is the format string.
+//! \param ... are the optional arguments, which depend on the contents of the
+//! format string.
+//!
+//! This function is very similar to the C library sprintf() function.
+//! Only the following formatting characters are supported:
+//!
+//! - \%c to print a character
+//! - \%d to print a decimal value
+//! - \%s to print a string
+//! - \%u to print an unsigned decimal value
+//! - \%x to print a hexadecimal value using lower case letters
+//! - \%X to print a hexadecimal value using lower case letters (not upper case
+//! letters as would typically be used)
+//! - \%\% to print out a \% character
+//!
+//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \%
+//! and the format character, which specifies the minimum number of characters
+//! to use for that value; if preceeded by a 0 then the extra characters will
+//! be filled with zeros instead of spaces.  For example, ``\%8d'' will use
+//! eight characters to print the decimal value with spaces added to reach
+//! eight; ``\%08d'' will use eight characters as well but will add zeros
+//! instead of spaces.
+//!
+//! The type of the arguments after \b pcString must match the requirements of
+//! the format string.  For example, if an integer was passed where a string
+//! was expected, an error of some kind will most likely occur.
+//!
+//! The caller must ensure that the buffer pcBuf is large enough to hold the
+//! entire converted string, including the null termination character.
+//!
+//! \return The count of characters that were written to the output buffer,
+//! not including the NULL termination character.
+//
+//*****************************************************************************
+int
+usprintf(char *pcBuf, const char *pcString, ...)
+{
+    va_list vaArgP;
+    int iRet;
+
+    //
+    // Start the varargs processing.
+    //
+    va_start(vaArgP, pcString);
+
+    //
+    // Call vsnprintf to perform the conversion.  Use a
+    // large number for the buffer size.
+    //
+    iRet = uvsnprintf(pcBuf, 0xffff, pcString, vaArgP);
+
+    //
+    // End the varargs processing.
+    //
+    va_end(vaArgP);
+
+    //
+    // Return the conversion count.
+    //
+    return(iRet);
+}
+
+//*****************************************************************************
+//
+//! A simple snprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X.
+//!
+//! \param pcBuf is the buffer where the converted string is stored.
+//! \param ulSize is the size of the buffer.
+//! \param pcString is the format string.
+//! \param ... are the optional arguments, which depend on the contents of the
+//! format string.
+//!
+//! This function is very similar to the C library sprintf() function.
+//! Only the following formatting characters are supported:
+//!
+//! - \%c to print a character
+//! - \%d to print a decimal value
+//! - \%s to print a string
+//! - \%u to print an unsigned decimal value
+//! - \%x to print a hexadecimal value using lower case letters
+//! - \%X to print a hexadecimal value using lower case letters (not upper case
+//! letters as would typically be used)
+//! - \%\% to print out a \% character
+//!
+//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \%
+//! and the format character, which specifies the minimum number of characters
+//! to use for that value; if preceeded by a 0 then the extra characters will
+//! be filled with zeros instead of spaces.  For example, ``\%8d'' will use
+//! eight characters to print the decimal value with spaces added to reach
+//! eight; ``\%08d'' will use eight characters as well but will add zeros
+//! instead of spaces.
+//!
+//! The type of the arguments after \b pcString must match the requirements of
+//! the format string.  For example, if an integer was passed where a string
+//! was expected, an error of some kind will most likely occur.
+//!
+//! The function will copy at most \b ulSize - 1 characters into the
+//! buffer \b pcBuf.  One space is reserved in the buffer for the null
+//! termination character.
+//!
+//! The function will return the number of characters that would be
+//! converted as if there were no limit on the buffer size.  Therefore
+//! it is possible for the function to return a count that is greater than
+//! the specified buffer size.  If this happens, it means that the output
+//! was truncated.
+//!
+//! \return the number of characters that were to be stored, not including
+//! the NULL termination character, regardless of space in the buffer.
+//
+//*****************************************************************************
+int
+usnprintf(char *pcBuf, unsigned long ulSize, const char *pcString, ...)
+{
+int iRet;
+
+    va_list vaArgP;
+
+    //
+    // Start the varargs processing.
+    //
+    va_start(vaArgP, pcString);
+
+    //
+    // Call vsnprintf to perform the conversion.
+    //
+    iRet = uvsnprintf(pcBuf, ulSize, pcString, vaArgP);
+
+    //
+    // End the varargs processing.
+    //
+    va_end(vaArgP);
+
+    //
+    // Return the conversion count.
+    //
+    return(iRet);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/watchdog.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/watchdog.h
new file mode 100644
index 0000000..4816538
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/LuminaryMicro/watchdog.h
@@ -0,0 +1,75 @@
+//*****************************************************************************
+//
+// watchdog.h - Prototypes for the Watchdog Timer API
+//
+// Copyright (c) 2005-2008 Luminary Micro, Inc.  All rights reserved.
+// 
+// Software License Agreement
+// 
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+// 
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws.  All rights are reserved.  You may not combine
+// this software with "viral" open-source software in order to form a larger
+// program.  Any use in violation of the foregoing restrictions may subject
+// the user to criminal sanctions under applicable laws, as well as to civil
+// liability for the breach of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __WATCHDOG_H__
+#define __WATCHDOG_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern tBoolean WatchdogRunning(unsigned long ulBase);
+extern void WatchdogEnable(unsigned long ulBase);
+extern void WatchdogResetEnable(unsigned long ulBase);
+extern void WatchdogResetDisable(unsigned long ulBase);
+extern void WatchdogLock(unsigned long ulBase);
+extern void WatchdogUnlock(unsigned long ulBase);
+extern tBoolean WatchdogLockState(unsigned long ulBase);
+extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);
+extern unsigned long WatchdogReloadGet(unsigned long ulBase);
+extern unsigned long WatchdogValueGet(unsigned long ulBase);
+extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
+extern void WatchdogIntUnregister(unsigned long ulBase);
+extern void WatchdogIntEnable(unsigned long ulBase);
+extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void WatchdogIntClear(unsigned long ulBase);
+extern void WatchdogStallEnable(unsigned long ulBase);
+extern void WatchdogStallDisable(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __WATCHDOG_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/cortexm3_macro.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/cortexm3_macro.h
new file mode 100644
index 0000000..c67240e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/cortexm3_macro.h
@@ -0,0 +1,51 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : cortexm3_macro.h
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : Header file for cortexm3_macro.s.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __CORTEXM3_MACRO_H
+#define __CORTEXM3_MACRO_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_type.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void __WFI(void);
+void __WFE(void);
+void __SEV(void);
+void __ISB(void);
+void __DSB(void);
+void __DMB(void);
+void __SVC(void);
+u32 __MRS_CONTROL(void);
+void __MSR_CONTROL(u32 Control);
+void __SETPRIMASK(void);
+void __RESETPRIMASK(void);
+void __SETFAULTMASK(void);
+void __RESETFAULTMASK(void);
+void __BASEPRICONFIG(u32 NewPriority);
+u32 __GetBASEPRI(void);
+u16 __REV_HalfWord(u16 Data);
+u32 __REV_Word(u32 Data);
+
+#endif /* __CORTEXM3_MACRO_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/lcd.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/lcd.h
new file mode 100644
index 0000000..73f44b9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/lcd.h
@@ -0,0 +1,179 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : lcd.h
+* Author             : MCD Application Team
+* Date First Issued  : mm/dd/yyyy
+* Description        : This file contains all the functions prototypes for the
+*                      lcd software driver.
+********************************************************************************
+* History:
+* mm/dd/yyyy
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __LCD_H
+#define __LCD_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_lib.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* LCD Registers */
+#define R0             0x00
+#define R1             0x01
+#define R2             0x02
+#define R3             0x03
+#define R5             0x05
+#define R6             0x06
+#define R13            0x0D
+#define R14            0x0E
+#define R15            0x0F
+#define R16            0x10
+#define R17            0x11
+#define R18            0x12
+#define R19            0x13
+#define R20            0x14
+#define R21            0x15
+#define R22            0x16
+#define R23            0x17
+#define R24            0x18
+#define R25            0x19
+#define R26            0x1A
+#define R27            0x1B
+#define R28            0x1C
+#define R29            0x1D
+#define R30            0x1E
+#define R31            0x1F
+#define R32            0x20
+#define R36            0x24
+#define R37            0x25
+#define R40            0x28
+#define R43            0x2B
+#define R45            0x2D
+#define R49            0x31
+#define R50            0x32
+#define R51            0x33
+#define R52            0x34
+#define R53            0x35
+#define R55            0x37
+#define R59            0x3B
+#define R60            0x3C
+#define R61            0x3D
+#define R62            0x3E
+#define R63            0x3F
+#define R64            0x40
+#define R65            0x41
+#define R66            0x42
+#define R67            0x43
+#define R68            0x44
+#define R69            0x45
+#define R70            0x46
+#define R71            0x47
+#define R72            0x48
+#define R73            0x49
+#define R74            0x4A
+#define R75            0x4B
+#define R76            0x4C
+#define R77            0x4D
+#define R78            0x4E
+#define R79            0x4F
+#define R80            0x50
+#define R118           0x76
+#define R134           0x86
+#define R135           0x87
+#define R136           0x88
+#define R137           0x89
+#define R139           0x8B
+#define R140           0x8C
+#define R141           0x8D
+#define R143           0x8F
+#define R144           0x90
+#define R145           0x91
+#define R146           0x92
+#define R147           0x93
+#define R148           0x94
+#define R149           0x95
+#define R150           0x96
+#define R151           0x97
+#define R152           0x98
+#define R153           0x99
+#define R154           0x9A
+#define R157           0x9D
+#define R192           0xC0
+#define R193           0xC1
+
+/* LCD Control pins */
+#define CtrlPin_NCS    GPIO_Pin_2   /* PB.02 */
+#define CtrlPin_RS     GPIO_Pin_7   /* PD.07 */
+#define CtrlPin_NWR    GPIO_Pin_15  /* PD.15 */
+
+/* LCD color */
+#define White          0xFFFF
+#define Black          0x0000
+#define Blue           0x001F
+#define Orange         0x051F
+#define Red            0xF800
+#define Magenta        0xF81F
+#define Green          0x07E0
+#define Cyan           0x7FFF
+#define Yellow         0xFFE0
+
+#define Line0          0
+#define Line1          24
+#define Line2          48
+#define Line3          72
+#define Line4          96
+#define Line5          120
+#define Line6          144
+#define Line7          168
+#define Line8          192
+#define Line9          216
+
+#define Horizontal     0x00
+#define Vertical       0x01
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/*----- High layer function -----*/
+void LCD_Init(void);
+void LCD_SetTextColor(vu16 Color);
+void LCD_SetBackColor(vu16 Color);
+void LCD_ClearLine(u8 Line);
+void LCD_Clear(void);
+void LCD_SetCursor(u8 Xpos, u16 Ypos);
+void LCD_DrawChar(u8 Xpos, u16 Ypos, uc16 *c);
+void LCD_DisplayChar(u8 Line, u16 Column, u8 Ascii);
+void LCD_DisplayStringLine(u8 Line, u8 *ptr);
+void LCD_DisplayString(u8 Line, u8 *ptr);
+void LCD_ScrollText(u8 Line, u8 *ptr);
+void LCD_SetDisplayWindow(u8 Xpos, u16 Ypos, u8 Height, u16 Width);
+void LCD_DrawLine(u8 Xpos, u16 Ypos, u16 Length, u8 Direction);
+void LCD_DrawRect(u8 Xpos, u16 Ypos, u8 Height, u16 Width);
+void LCD_DrawCircle(u8 Xpos, u16 Ypos, u16 Radius);
+void LCD_DrawMonoPict(uc32 *Pict);
+void LCD_DrawBMP(u32 BmpAddress);
+
+/*----- Medium layer function -----*/
+void LCD_WriteReg(u8 LCD_Reg, u8 LCD_RegValue);
+u8 LCD_ReadReg(u8 LCD_Reg);
+void LCD_WriteRAM(u16 RGB_Code);
+u16  LCD_ReadRAM(void);
+void LCD_PowerOn(void);
+void LCD_DisplayOn(void);
+void LCD_DisplayOff(void);
+
+/*----- Low layer function -----*/
+void LCD_CtrlLinesConfig(void);
+void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u16 CtrlPins, BitAction BitVal);
+void LCD_SPIConfig(void);
+
+#endif /* __LCD_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/misc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/misc.h
new file mode 100644
index 0000000..e8b2dd7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/misc.h
@@ -0,0 +1,166 @@
+/**
+  ******************************************************************************
+  * @file  misc.h
+  * @author  MCD Application Team
+  * @version  V3.0.0
+  * @date  04/06/2009
+  * @brief  This file contains all the functions prototypes for the 
+  *         miscellaneous firmware library functions.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
© COPYRIGHT 2009 STMicroelectronics

+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MISC_H
+#define __MISC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup MISC
+  * @{
+  */
+
+/** @defgroup MISC_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  NVIC Init Structure definition  
+  */
+
+typedef struct
+{
+  uint8_t NVIC_IRQChannel;
+  uint8_t NVIC_IRQChannelPreemptionPriority;
+  uint8_t NVIC_IRQChannelSubPriority;
+  FunctionalState NVIC_IRQChannelCmd;
+} NVIC_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup Vector_Table_Base 
+  * @{
+  */
+
+#define NVIC_VectTab_RAM             ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
+                                  ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+  * @}
+  */
+
+/** @defgroup System_Low_Power 
+  * @{
+  */
+
+#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+                        ((LP) == NVIC_LP_SLEEPDEEP) || \
+                        ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+  * @}
+  */
+
+/** @defgroup Preemption_Priority_Group 
+  * @{
+  */
+
+#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /* 0 bits for pre-emption priority
+                                                          4 bits for subpriority */
+#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /* 1 bits for pre-emption priority
+                                                          3 bits for subpriority */
+#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /* 2 bits for pre-emption priority
+                                                          2 bits for subpriority */
+#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /* 3 bits for pre-emption priority
+                                                          1 bits for subpriority */
+#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /* 4 bits for pre-emption priority
+                                                          0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
+                                       ((GROUP) == NVIC_PriorityGroup_1) || \
+                                       ((GROUP) == NVIC_PriorityGroup_2) || \
+                                       ((GROUP) == NVIC_PriorityGroup_3) || \
+                                       ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x0007FFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup SysTick_clock_source 
+  * @{
+  */
+
+#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Exported_Functions
+  * @{
+  */
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#endif /* __MISC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/spi_flash.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/spi_flash.h
new file mode 100644
index 0000000..5bd8a96
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/spi_flash.h
@@ -0,0 +1,53 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : spi_flash.h
+* Author             : MCD Application Team
+* Date First Issued  : 02/05/2007
+* Description        : Header for spi_flash.c file.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __SPI_FLASH_H
+#define __SPI_FLASH_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_lib.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+#define Low     0x00  /* Chip Select line low */
+#define High    0x01  /* Chip Select line high */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/*----- High layer function -----*/
+void SPI_FLASH_Init(void);
+void SPI_FLASH_SectorErase(u32 SectorAddr);
+void SPI_FLASH_BulkErase(void);
+void SPI_FLASH_PageWrite(u8* pBuffer, u32 WriteAddr, u16 NumByteToWrite);
+void SPI_FLASH_BufferWrite(u8* pBuffer, u32 WriteAddr, u16 NumByteToWrite);
+void SPI_FLASH_BufferRead(u8* pBuffer, u32 ReadAddr, u16 NumByteToRead);
+u32 SPI_FLASH_ReadID(void);
+void SPI_FLASH_StartReadSequence(u32 ReadAddr);
+
+/*----- Low layer function -----*/
+u8 SPI_FLASH_ReadByte(void);
+void SPI_FLASH_ChipSelect(u8 State);
+u8 SPI_FLASH_SendByte(u8 byte);
+u16 SPI_FLASH_SendHalfWord(u16 HalfWord);
+void SPI_FLASH_WriteEnable(void);
+void SPI_FLASH_WaitForWriteEnd(void);
+
+#endif /* __SPI_FLASH_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_adc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_adc.h
new file mode 100644
index 0000000..8e90539
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_adc.h
@@ -0,0 +1,269 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_adc.h
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file contains all the functions prototypes for the
+*                      ADC firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_ADC_H
+#define __STM32F10x_ADC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* ADC Init structure definition */
+typedef struct
+{
+  u32 ADC_Mode;
+  FunctionalState ADC_ScanConvMode; 
+  FunctionalState ADC_ContinuousConvMode;
+  u32 ADC_ExternalTrigConv;
+  u32 ADC_DataAlign;
+  u8 ADC_NbrOfChannel;
+}ADC_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* ADC dual mode -------------------------------------------------------------*/
+#define ADC_Mode_Independent                       ((u32)0x00000000)
+#define ADC_Mode_RegInjecSimult                    ((u32)0x00010000)
+#define ADC_Mode_RegSimult_AlterTrig               ((u32)0x00020000)
+#define ADC_Mode_InjecSimult_FastInterl            ((u32)0x00030000)
+#define ADC_Mode_InjecSimult_SlowInterl            ((u32)0x00040000)
+#define ADC_Mode_InjecSimult                       ((u32)0x00050000)
+#define ADC_Mode_RegSimult                         ((u32)0x00060000)
+#define ADC_Mode_FastInterl                        ((u32)0x00070000)
+#define ADC_Mode_SlowInterl                        ((u32)0x00080000)
+#define ADC_Mode_AlterTrig                         ((u32)0x00090000)
+
+#define IS_ADC_MODE(MODE) ((MODE == ADC_Mode_Independent) || \
+                           (MODE == ADC_Mode_RegInjecSimult) || \
+                           (MODE == ADC_Mode_RegSimult_AlterTrig) || \
+                           (MODE == ADC_Mode_InjecSimult_FastInterl) || \
+                           (MODE == ADC_Mode_InjecSimult_SlowInterl) || \
+                           (MODE == ADC_Mode_InjecSimult) || \
+                           (MODE == ADC_Mode_RegSimult) || \
+                           (MODE == ADC_Mode_FastInterl) || \
+                           (MODE == ADC_Mode_SlowInterl) || \
+                           (MODE == ADC_Mode_AlterTrig))
+
+/* ADC extrenal trigger sources for regular channels conversion --------------*/
+#define ADC_ExternalTrigConv_T1_CC1                ((u32)0x00000000)
+#define ADC_ExternalTrigConv_T1_CC2                ((u32)0x00020000)
+#define ADC_ExternalTrigConv_T1_CC3                ((u32)0x00040000)
+#define ADC_ExternalTrigConv_T2_CC2                ((u32)0x00060000)
+#define ADC_ExternalTrigConv_T3_TRGO               ((u32)0x00080000)
+#define ADC_ExternalTrigConv_T4_CC4                ((u32)0x000A0000)
+#define ADC_ExternalTrigConv_Ext_IT11              ((u32)0x000C0000)
+#define ADC_ExternalTrigConv_None                  ((u32)0x000E0000)
+
+#define IS_ADC_EXT_TRIG(TRIG1) ((TRIG1 == ADC_ExternalTrigConv_T1_CC1) || \
+                                (TRIG1 == ADC_ExternalTrigConv_T1_CC2) || \
+                                (TRIG1 == ADC_ExternalTrigConv_T1_CC3) || \
+                                (TRIG1 == ADC_ExternalTrigConv_T2_CC2) || \
+                                (TRIG1 == ADC_ExternalTrigConv_T3_TRGO) || \
+                                (TRIG1 == ADC_ExternalTrigConv_T4_CC4) || \
+                                (TRIG1 == ADC_ExternalTrigConv_Ext_IT11) || \
+                                (TRIG1 == ADC_ExternalTrigConv_None))
+
+/* ADC data align ------------------------------------------------------------*/
+#define ADC_DataAlign_Right                        ((u32)0x00000000)
+#define ADC_DataAlign_Left                         ((u32)0x00000800)
+
+#define IS_ADC_DATA_ALIGN(ALIGN) ((ALIGN == ADC_DataAlign_Right) || \
+                                  (ALIGN == ADC_DataAlign_Left))
+
+/* ADC channels --------------------------------------------------------------*/
+#define ADC_Channel_0                               ((u8)0x00)
+#define ADC_Channel_1                               ((u8)0x01)
+#define ADC_Channel_2                               ((u8)0x02)
+#define ADC_Channel_3                               ((u8)0x03)
+#define ADC_Channel_4                               ((u8)0x04)
+#define ADC_Channel_5                               ((u8)0x05)
+#define ADC_Channel_6                               ((u8)0x06)
+#define ADC_Channel_7                               ((u8)0x07)
+#define ADC_Channel_8                               ((u8)0x08)
+#define ADC_Channel_9                               ((u8)0x09)
+#define ADC_Channel_10                              ((u8)0x0A)
+#define ADC_Channel_11                              ((u8)0x0B)
+#define ADC_Channel_12                              ((u8)0x0C)
+#define ADC_Channel_13                              ((u8)0x0D)
+#define ADC_Channel_14                              ((u8)0x0E)
+#define ADC_Channel_15                              ((u8)0x0F)
+#define ADC_Channel_16                              ((u8)0x10)
+#define ADC_Channel_17                              ((u8)0x11)
+
+#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL == ADC_Channel_0) || (CHANNEL == ADC_Channel_1) || \
+                                 (CHANNEL == ADC_Channel_2) || (CHANNEL == ADC_Channel_3) || \
+                                 (CHANNEL == ADC_Channel_4) || (CHANNEL == ADC_Channel_5) || \
+                                 (CHANNEL == ADC_Channel_6) || (CHANNEL == ADC_Channel_7) || \
+                                 (CHANNEL == ADC_Channel_8) || (CHANNEL == ADC_Channel_9) || \
+                                 (CHANNEL == ADC_Channel_10) || (CHANNEL == ADC_Channel_11) || \
+                                 (CHANNEL == ADC_Channel_12) || (CHANNEL == ADC_Channel_13) || \
+                                 (CHANNEL == ADC_Channel_14) || (CHANNEL == ADC_Channel_15) || \
+                                 (CHANNEL == ADC_Channel_16) || (CHANNEL == ADC_Channel_17))
+
+/* ADC sampling times --------------------------------------------------------*/
+#define ADC_SampleTime_1Cycles5                    ((u8)0x00)
+#define ADC_SampleTime_7Cycles5                    ((u8)0x01)
+#define ADC_SampleTime_13Cycles5                   ((u8)0x02)
+#define ADC_SampleTime_28Cycles5                   ((u8)0x03)
+#define ADC_SampleTime_41Cycles5                   ((u8)0x04)
+#define ADC_SampleTime_55Cycles5                   ((u8)0x05)
+#define ADC_SampleTime_71Cycles5                   ((u8)0x06)
+#define ADC_SampleTime_239Cycles5                  ((u8)0x07)
+
+#define IS_ADC_SAMPLE_TIME(TIME) ((TIME == ADC_SampleTime_1Cycles5) || \
+                                  (TIME == ADC_SampleTime_7Cycles5) || \
+                                  (TIME == ADC_SampleTime_13Cycles5) || \
+                                  (TIME == ADC_SampleTime_28Cycles5) || \
+                                  (TIME == ADC_SampleTime_41Cycles5) || \
+                                  (TIME == ADC_SampleTime_55Cycles5) || \
+                                  (TIME == ADC_SampleTime_71Cycles5) || \
+                                  (TIME == ADC_SampleTime_239Cycles5))
+
+/* ADC extrenal trigger sources for injected channels conversion -------------*/
+#define ADC_ExternalTrigInjecConv_T1_TRGO          ((u32)0x00000000)
+#define ADC_ExternalTrigInjecConv_T1_CC4           ((u32)0x00001000)
+#define ADC_ExternalTrigInjecConv_T2_TRGO          ((u32)0x00002000)
+#define ADC_ExternalTrigInjecConv_T2_CC1           ((u32)0x00003000)
+#define ADC_ExternalTrigInjecConv_T3_CC4           ((u32)0x00004000)
+#define ADC_ExternalTrigInjecConv_T4_TRGO          ((u32)0x00005000)
+#define ADC_ExternalTrigInjecConv_Ext_IT15         ((u32)0x00006000)
+#define ADC_ExternalTrigInjecConv_None             ((u32)0x00007000)
+
+#define IS_ADC_EXT_INJEC_TRIG(TRIG) ((TRIG == ADC_ExternalTrigInjecConv_T1_TRGO) || \
+                                     (TRIG == ADC_ExternalTrigInjecConv_T1_CC4) || \
+                                     (TRIG == ADC_ExternalTrigInjecConv_T2_TRGO) || \
+                                     (TRIG == ADC_ExternalTrigInjecConv_T2_CC1) || \
+                                     (TRIG == ADC_ExternalTrigInjecConv_T3_CC4) || \
+                                     (TRIG == ADC_ExternalTrigInjecConv_T4_TRGO) || \
+                                     (TRIG == ADC_ExternalTrigInjecConv_Ext_IT15) || \
+                                     (TRIG == ADC_ExternalTrigInjecConv_None))
+
+/* ADC injected channel selection --------------------------------------------*/
+#define ADC_InjectedChannel_1                       ((u8)0x14)
+#define ADC_InjectedChannel_2                       ((u8)0x18)
+#define ADC_InjectedChannel_3                       ((u8)0x1C)
+#define ADC_InjectedChannel_4                       ((u8)0x20)
+
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) ((CHANNEL == ADC_InjectedChannel_1) || \
+                                          (CHANNEL == ADC_InjectedChannel_2) || \
+                                          (CHANNEL == ADC_InjectedChannel_3) || \
+                                          (CHANNEL == ADC_InjectedChannel_4))
+
+/* ADC analog watchdog selection ---------------------------------------------*/
+#define ADC_AnalogWatchdog_SingleRegEnable         ((u32)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable       ((u32)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable  ((u32)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable            ((u32)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable          ((u32)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable    ((u32)0x00C00000)
+#define ADC_AnalogWatchdog_None                    ((u32)0x00000000)
+
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) ((WATCHDOG == ADC_AnalogWatchdog_SingleRegEnable) || \
+                                          (WATCHDOG == ADC_AnalogWatchdog_SingleInjecEnable) || \
+                                          (WATCHDOG == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
+                                          (WATCHDOG == ADC_AnalogWatchdog_AllRegEnable) || \
+                                          (WATCHDOG == ADC_AnalogWatchdog_AllInjecEnable) || \
+                                          (WATCHDOG == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
+                                          (WATCHDOG == ADC_AnalogWatchdog_None))
+
+/* ADC interrupts definition -------------------------------------------------*/
+#define ADC_IT_EOC                                 ((u16)0x0220)
+#define ADC_IT_AWD                                 ((u16)0x0140)
+#define ADC_IT_JEOC                                ((u16)0x0480)
+
+#define IS_ADC_IT(IT) (((IT & (u16)0xF81F) == 0x00) && (IT != 0x00))
+#define IS_ADC_GET_IT(IT) ((IT == ADC_IT_EOC) || (IT == ADC_IT_AWD) || \
+                           (IT == ADC_IT_JEOC))
+
+/* ADC flags definition ------------------------------------------------------*/
+#define ADC_FLAG_AWD                               ((u8)0x01)
+#define ADC_FLAG_EOC                               ((u8)0x02)
+#define ADC_FLAG_JEOC                              ((u8)0x04)
+#define ADC_FLAG_JSTRT                             ((u8)0x08)
+#define ADC_FLAG_STRT                              ((u8)0x10)
+
+#define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG & (u8)0xE0) == 0x00) && (FLAG != 0x00))
+#define IS_ADC_GET_FLAG(FLAG) ((FLAG == ADC_FLAG_AWD) || (FLAG == ADC_FLAG_EOC) || \
+                               (FLAG == ADC_FLAG_JEOC) || (FLAG == ADC_FLAG_JSTRT) || \
+                               (FLAG == ADC_FLAG_STRT))
+
+/* ADC thresholds ------------------------------------------------------------*/
+#define IS_ADC_THRESHOLD(THRESHOLD) (THRESHOLD <= 0xFFF)
+
+/* ADC injected offset -------------------------------------------------------*/
+#define IS_ADC_OFFSET(OFFSET) (OFFSET <= 0xFFF)
+
+/* ADC injected length -------------------------------------------------------*/
+#define IS_ADC_INJECTED_LENGTH(LENGTH) ((LENGTH >= 0x1) && (LENGTH <= 0x4))
+
+/* ADC injected rank ---------------------------------------------------------*/
+#define IS_ADC_INJECTED_RANK(RANK) ((RANK >= 0x1) && (RANK <= 0x4))
+
+/* ADC regular length --------------------------------------------------------*/
+#define IS_ADC_REGULAR_LENGTH(LENGTH) ((LENGTH >= 0x1) && (LENGTH <= 0x10))
+
+/* ADC regular rank ----------------------------------------------------------*/
+#define IS_ADC_REGULAR_RANK(RANK) ((RANK >= 0x1) && (RANK <= 0x10))
+
+/* ADC regular discontinuous mode number -------------------------------------*/
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) ((NUMBER >= 0x1) && (NUMBER <= 0x8))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void ADC_DeInit(ADC_TypeDef* ADCx);
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState);
+void ADC_ResetCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_StartCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+u16 ADC_GetConversionValue(ADC_TypeDef* ADCx);
+u32 ADC_GetDualModeConversionValue(void);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length);
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset);
+u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel);
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold, u16 LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel);
+void ADC_TempSensorCmd(FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT);
+
+#endif /*__STM32F10x_ADC_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_bkp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_bkp.h
new file mode 100644
index 0000000..82224d1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_bkp.h
@@ -0,0 +1,73 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_bkp.h
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file contains all the functions prototypes for the
+*                      BKP firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_BKP_H
+#define __STM32F10x_BKP_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Tamper Pin active level*/
+#define BKP_TamperPinLevel_High    ((u16)0x0000)
+#define BKP_TamperPinLevel_Low     ((u16)0x0001)
+
+#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) ((LEVEL == BKP_TamperPinLevel_High) || \
+                                        (LEVEL == BKP_TamperPinLevel_Low))
+
+/* Data Backup Register */
+#define BKP_DR1                    ((u16)0x0004)
+#define BKP_DR2                    ((u16)0x0008)
+#define BKP_DR3                    ((u16)0x000C)
+#define BKP_DR4                    ((u16)0x0010)
+#define BKP_DR5                    ((u16)0x0014)
+#define BKP_DR6                    ((u16)0x0018)
+#define BKP_DR7                    ((u16)0x001C)
+#define BKP_DR8                    ((u16)0x0020)
+#define BKP_DR9                    ((u16)0x0024)
+#define BKP_DR10                   ((u16)0x0028)
+
+#define IS_BKP_DR(DR) ((DR == BKP_DR1) ||  (DR == BKP_DR2) || (DR == BKP_DR3) || \
+                       (DR == BKP_DR4) ||  (DR == BKP_DR5) || (DR == BKP_DR6) || \
+                       (DR == BKP_DR7) ||  (DR == BKP_DR8) || (DR == BKP_DR9) || \
+                       (DR == BKP_DR10))
+
+#define IS_BKP_CALIBRATION_VALUE(VALUE) (VALUE <= 0x7F)
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void BKP_DeInit(void);
+void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel);
+void BKP_TamperPinCmd(FunctionalState NewState);
+void BKP_ITConfig(FunctionalState NewState);
+void BKP_RTCCalibrationClockOutputCmd(FunctionalState NewState);
+void BKP_SetRTCCalibrationValue(u8 CalibrationValue);
+void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data);
+u16 BKP_ReadBackupRegister(u16 BKP_DR);
+FlagStatus BKP_GetFlagStatus(void);
+void BKP_ClearFlag(void);
+ITStatus BKP_GetITStatus(void);
+void BKP_ClearITPendingBit(void);
+
+#endif /* __STM32F10x_BKP_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_can.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_can.h
new file mode 100644
index 0000000..bd7f538
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_can.h
@@ -0,0 +1,269 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_can.h
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file contains all the functions prototypes for the
+*                      CAN firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CAN_H
+#define __STM32F10x_CAN_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* CAN init structure definition */
+typedef struct
+{
+  FunctionalState CAN_TTCM;
+  FunctionalState CAN_ABOM;
+  FunctionalState CAN_AWUM;
+  FunctionalState CAN_NART;
+  FunctionalState CAN_RFLM;
+  FunctionalState CAN_TXFP;
+  u8 CAN_Mode;
+  u8 CAN_SJW;
+  u8 CAN_BS1;
+  u8 CAN_BS2;
+  u8 CAN_Clock;
+  u16 CAN_Prescaler;
+} CAN_InitTypeDef;
+
+/* CAN filter init structure definition */
+typedef struct
+{
+  u8 CAN_FilterNumber;
+  u8 CAN_FilterMode;
+  u8 CAN_FilterScale;
+  u16 CAN_FilterIdHigh;
+  u16 CAN_FilterIdLow;
+  u16 CAN_FilterMaskIdHigh;
+  u16 CAN_FilterMaskIdLow;
+  u16 CAN_FilterFIFOAssignment;
+  FunctionalState CAN_FilterActivation;
+} CAN_FilterInitTypeDef;
+
+/* CAN Tx message structure definition */
+typedef struct
+{
+  u32 StdId;
+  u32 ExtId;
+  u8 IDE;
+  u8 RTR;
+  u8 DLC;
+  u8 Data[8];
+} CanTxMsg;
+
+/* CAN Rx message structure definition */
+typedef struct
+{
+  u32 StdId;
+  u32 ExtId;
+  u8 IDE;
+  u8 RTR;
+  u8 DLC;
+  u8 Data[8];
+  u8 FMI;
+} CanRxMsg;
+
+/* Exported constants --------------------------------------------------------*/
+
+/* CAN sleep constants */
+#define CANINITFAILED              ((u8)0x00) /* CAN initialization failed */
+#define CANINITOK                  ((u8)0x01) /* CAN initialization failed */
+
+/* CAN operating mode */
+#define CAN_Mode_Normal             ((u8)0x00)  /* normal mode */
+#define CAN_Mode_LoopBack           ((u8)0x01)  /* loopback mode */
+#define CAN_Mode_Silent             ((u8)0x02)  /* silent mode */
+#define CAN_Mode_Silent_LoopBack    ((u8)0x03)  /* loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE) ((MODE == CAN_Mode_Normal) || (MODE == CAN_Mode_LoopBack)|| \
+                           (MODE == CAN_Mode_Silent) || (MODE == CAN_Mode_Silent_LoopBack))
+
+/* CAN synchronisation jump width */
+#define CAN_SJW_0tq                 ((u8)0x00)  /* 0 time quantum */
+#define CAN_SJW_1tq                 ((u8)0x01)  /* 1 time quantum */
+#define CAN_SJW_2tq                 ((u8)0x02)  /* 2 time quantum */
+#define CAN_SJW_3tq                 ((u8)0x03)  /* 3 time quantum */
+
+#define IS_CAN_SJW(SJW) ((SJW == CAN_SJW_0tq) || (SJW == CAN_SJW_1tq)|| \
+                         (SJW == CAN_SJW_2tq) || (SJW == CAN_SJW_3tq))
+
+/* time quantum in bit segment 1 */
+#define CAN_BS1_1tq                 ((u8)0x00)  /* 1 time quantum */
+#define CAN_BS1_2tq                 ((u8)0x01)  /* 2 time quantum */
+#define CAN_BS1_3tq                 ((u8)0x02)  /* 3 time quantum */
+#define CAN_BS1_4tq                 ((u8)0x03)  /* 4 time quantum */
+#define CAN_BS1_5tq                 ((u8)0x04)  /* 5 time quantum */
+#define CAN_BS1_6tq                 ((u8)0x05)  /* 6 time quantum */
+#define CAN_BS1_7tq                 ((u8)0x06)  /* 7 time quantum */
+#define CAN_BS1_8tq                 ((u8)0x07)  /* 8 time quantum */
+#define CAN_BS1_9tq                 ((u8)0x08)  /* 9 time quantum */
+#define CAN_BS1_10tq                ((u8)0x09)  /* 10 time quantum */
+#define CAN_BS1_11tq                ((u8)0x0A)  /* 11 time quantum */
+#define CAN_BS1_12tq                ((u8)0x0B)  /* 12 time quantum */
+#define CAN_BS1_13tq                ((u8)0x0C)  /* 13 time quantum */
+#define CAN_BS1_14tq                ((u8)0x0D)  /* 14 time quantum */
+#define CAN_BS1_15tq                ((u8)0x0E)  /* 15 time quantum */
+#define CAN_BS1_16tq                ((u8)0x0F)  /* 16 time quantum */
+
+#define IS_CAN_BS1(BS1) (BS1 <= CAN_BS1_16tq)
+
+/* time quantum in bit segment 2 */
+#define CAN_BS2_1tq                 ((u8)0x00)  /* 1 time quantum */
+#define CAN_BS2_2tq                 ((u8)0x01)  /* 2 time quantum */
+#define CAN_BS2_3tq                 ((u8)0x02)  /* 3 time quantum */
+#define CAN_BS2_4tq                 ((u8)0x03)  /* 4 time quantum */
+#define CAN_BS2_5tq                 ((u8)0x04)  /* 5 time quantum */
+#define CAN_BS2_6tq                 ((u8)0x05)  /* 6 time quantum */
+#define CAN_BS2_7tq                 ((u8)0x06)  /* 7 time quantum */
+#define CAN_BS2_8tq                 ((u8)0x07)  /* 8 time quantum */
+
+#define IS_CAN_BS2(BS2) (BS2 <= CAN_BS2_8tq)
+
+/* CAN clock selected */
+#define CAN_Clock_8MHz              ((u8)0x00)  /* 8MHz XTAL clock selected */
+#define CAN_Clock_APB               ((u8)0x01)  /* APB clock selected */
+
+#define IS_CAN_CLOCK(CLOCK) ((CLOCK == CAN_Clock_8MHz) || (CLOCK == CAN_Clock_APB))
+
+/* CAN clock prescaler */
+#define IS_CAN_PRESCALER(PRESCALER) ((PRESCALER >= 1) && (PRESCALER <= 1024))
+
+/* CAN filter number */
+#define IS_CAN_FILTER_NUMBER(NUMBER) (NUMBER <= 13)
+
+/* CAN filter mode */
+#define CAN_FilterMode_IdMask       ((u8)0x00)  /* id/mask mode */
+#define CAN_FilterMode_IdList       ((u8)0x01)  /* identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) ((MODE == CAN_FilterMode_IdMask) || \
+                                       (MODE == CAN_FilterMode_IdList))
+
+/* CAN filter scale */
+#define CAN_FilterScale_16bit       ((u8)0x00) /* 16-bit filter scale */
+#define CAN_FilterScale_32bit       ((u8)0x01) /* 2-bit filter scale */
+
+#define IS_CAN_FILTER_SCALE(SCALE) ((SCALE == CAN_FilterScale_16bit) || \
+                                         (SCALE == CAN_FilterScale_32bit))
+
+/* CAN filter FIFO assignation */
+#define CAN_FilterFIFO0             ((u8)0x00)  /* Filter FIFO 0 assignment for filter x */
+#define CAN_FilterFIFO1             ((u8)0x01)  /* Filter FIFO 1 assignment for filter x */
+
+#define IS_CAN_FILTER_FIFO(FIFO) ((FIFO == CAN_FilterFIFO0) || \
+                                       (FIFO == CAN_FilterFIFO1))
+
+/* CAN Tx */
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) (TRANSMITMAILBOX <= ((u8)0x02))
+#define IS_CAN_STDID(STDID)   (STDID <= ((u32)0x7FF))
+#define IS_CAN_EXTID(EXTID)   (EXTID <= ((u32)0x3FFFF))
+#define IS_CAN_DLC(DLC)       (DLC <= ((u8)0x08))
+
+/* CAN identifier type */
+#define CAN_ID_STD                 ((u32)0x00000000)  /* Standard Id */
+#define CAN_ID_EXT                 ((u32)0x00000004)  /* Extended Id */
+
+#define IS_CAN_IDTYPE(IDTYPE) ((IDTYPE == CAN_ID_STD) || (IDTYPE == CAN_ID_EXT))
+
+/* CAN remote transmission request */
+#define CAN_RTR_DATA                ((u32)0x00000000)  /* Data frame */
+#define CAN_RTR_REMOTE              ((u32)0x00000002)  /* Remote frame */
+
+#define IS_CAN_RTR(RTR) ((RTR == CAN_RTR_DATA) || (RTR == CAN_RTR_REMOTE))
+
+/* CAN transmit constants */
+#define CANTXFAILED                 ((u8)0x00) /* CAN transmission failed */
+#define CANTXOK                     ((u8)0x01) /* CAN transmission succeeded */
+#define CANTXPENDING                ((u8)0x02) /* CAN transmission pending */
+#define CAN_NO_MB                   ((u8)0x04) /* CAN cell did not provide an empty mailbox */
+
+/* CAN receive FIFO number constants */
+#define CAN_FIFO0                 ((u8)0x00) /* CAN FIFO0 used to receive */
+#define CAN_FIFO1                 ((u8)0x01) /* CAN FIFO1 used to receive */
+
+#define IS_CAN_FIFO(FIFO) ((FIFO == CAN_FIFO0) || (FIFO == CAN_FIFO1))
+
+/* CAN sleep constants */
+#define CANSLEEPFAILED              ((u8)0x00) /* CAN did not enter the sleep mode */
+#define CANSLEEPOK                  ((u8)0x01) /* CAN entered the sleep mode */
+
+/* CAN wake up constants */
+#define CANWAKEUPFAILED             ((u8)0x00) /* CAN did not leave the sleep mode */
+#define CANWAKEUPOK                 ((u8)0x01) /* CAN leaved the sleep mode */
+
+/* CAN flags */
+#define CAN_FLAG_EWG                ((u32)0x00000001) /* Error Warning Flag */
+#define CAN_FLAG_EPV                ((u32)0x00000002) /* Error Passive Flag */
+#define CAN_FLAG_BOF                ((u32)0x00000004) /* Bus-Off Flag */
+
+#define IS_CAN_FLAG(FLAG) ((FLAG == CAN_FLAG_EWG) || (FLAG == CAN_FLAG_EPV) ||\
+                           (FLAG == CAN_FLAG_BOF))
+
+/* CAN interrupts */
+#define CAN_IT_RQCP0                ((u8)0x05) /* Request completed mailbox 0 */
+#define CAN_IT_RQCP1                ((u8)0x06) /* Request completed mailbox 1 */
+#define CAN_IT_RQCP2                ((u8)0x07) /* Request completed mailbox 2 */
+#define CAN_IT_TME                  ((u32)0x00000001) /* Transmit mailbox empty */
+#define CAN_IT_FMP0                 ((u32)0x00000002) /* FIFO 0 message pending */
+#define CAN_IT_FF0                  ((u32)0x00000004) /* FIFO 0 full */
+#define CAN_IT_FOV0                 ((u32)0x00000008) /* FIFO 0 overrun */
+#define CAN_IT_FMP1                 ((u32)0x00000010) /* FIFO 1 message pending */
+#define CAN_IT_FF1                  ((u32)0x00000020) /* FIFO 1 full */
+#define CAN_IT_FOV1                 ((u32)0x00000040) /* FIFO 1 overrun */
+#define CAN_IT_EWG                  ((u32)0x00000100) /* Error warning */
+#define CAN_IT_EPV                  ((u32)0x00000200) /* Error passive */
+#define CAN_IT_BOF                  ((u32)0x00000400) /* Bus-off */
+#define CAN_IT_LEC                  ((u32)0x00000800) /* Last error code */
+#define CAN_IT_ERR                  ((u32)0x00008000) /* Error */
+#define CAN_IT_WKU                  ((u32)0x00010000) /* Wake-up */
+#define CAN_IT_SLK                  ((u32)0x00020000) /* Sleep */
+
+#define IS_CAN_IT(IT) ((IT == CAN_IT_RQCP0) || (IT == CAN_IT_RQCP1) ||\
+                       (IT == CAN_IT_RQCP2) || (IT == CAN_IT_TME)   ||\
+                       (IT == CAN_IT_FMP0)  || (IT == CAN_IT_FF0)   ||\
+                       (IT == CAN_IT_FOV0)  || (IT == CAN_IT_FMP1)  ||\
+                       (IT == CAN_IT_FF1)   || (IT == CAN_IT_FOV1)  ||\
+                       (IT == CAN_IT_EWG)   || (IT == CAN_IT_EPV)   ||\
+                       (IT == CAN_IT_BOF)   || (IT == CAN_IT_LEC)   ||\
+                       (IT == CAN_IT_ERR)   || (IT == CAN_IT_WKU)   ||\
+                       (IT == CAN_IT_SLK))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported function protypes ----------------------------------------------- */
+void CAN_DeInit(void);
+u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct);
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
+void CAN_ITConfig(u32 CAN_IT, FunctionalState NewState);
+u8 CAN_Transmit(CanTxMsg* TxMessage);
+u32 CAN_TransmitStatus(u8 TransmitMailbox);
+void CAN_CancelTransmit(u8 Mailbox);
+void CAN_FIFORelease(u8 FIFONumber);
+u8 CAN_MessagePending(u8 FIFONumber);
+void CAN_Receive(u8 FIFONumber, CanRxMsg* RxMessage);
+u8 CAN_Sleep(void);
+u8 CAN_WakeUp(void);
+FlagStatus CAN_GetFlagStatus(u32 CAN_FLAG);
+void CAN_ClearFlag(u32 CAN_FLAG);
+ITStatus CAN_GetITStatus(u32 CAN_IT);
+void CAN_ClearITPendingBit(u32 CAN_IT);
+
+#endif /* __STM32F10x_CAN_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_crc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_crc.h
new file mode 100644
index 0000000..ef33aa3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_crc.h
@@ -0,0 +1,85 @@
+/**
+  ******************************************************************************
+  * @file  stm32f10x_crc.h
+  * @author  MCD Application Team
+  * @version  V3.0.0
+  * @date  04/06/2009
+  * @brief  This file contains all the functions prototypes for the CRC firmware 
+  *         library.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
© COPYRIGHT 2009 STMicroelectronics

+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CRC_H
+#define __STM32F10x_CRC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CRC
+  * @{
+  */
+
+/** @defgroup CRC_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Functions
+  * @{
+  */
+
+void CRC_ResetDR(void);
+uint32_t CRC_CalcCRC(uint32_t Data);
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+void CRC_SetIDRegister(uint8_t IDValue);
+uint8_t CRC_GetIDRegister(void);
+
+#endif /* __STM32F10x_CRC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dac.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dac.h
new file mode 100644
index 0000000..59caa27
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dac.h
@@ -0,0 +1,261 @@
+/**
+  ******************************************************************************
+  * @file  stm32f10x_dac.h
+  * @author  MCD Application Team
+  * @version  V3.0.0
+  * @date  04/06/2009
+  * @brief  This file contains all the functions prototypes for the DAC firmware 
+  *         library.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
© COPYRIGHT 2009 STMicroelectronics

+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_DAC_H
+#define __STM32F10x_DAC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DAC
+  * @{
+  */
+
+/** @defgroup DAC_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  DAC Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t DAC_Trigger;
+  uint32_t DAC_WaveGeneration;
+  uint32_t DAC_LFSRUnmask_TriangleAmplitude;
+  uint32_t DAC_OutputBuffer; 
+}DAC_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup DAC_trigger_selection 
+  * @{
+  */
+
+#define DAC_Trigger_None                   ((uint32_t)0x00000000)
+#define DAC_Trigger_T6_TRGO                ((uint32_t)0x00000004)
+#define DAC_Trigger_T8_TRGO                ((uint32_t)0x0000000C)
+#define DAC_Trigger_T7_TRGO                ((uint32_t)0x00000014)
+#define DAC_Trigger_T5_TRGO                ((uint32_t)0x0000001C)
+#define DAC_Trigger_T2_TRGO                ((uint32_t)0x00000024)
+#define DAC_Trigger_T4_TRGO                ((uint32_t)0x0000002C)
+#define DAC_Trigger_Ext_IT9                ((uint32_t)0x00000034)
+#define DAC_Trigger_Software               ((uint32_t)0x0000003C)
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
+                                 ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
+                                 ((TRIGGER) == DAC_Trigger_Software))
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_wave_generation 
+  * @{
+  */
+
+#define DAC_WaveGeneration_None            ((uint32_t)0x00000000)
+#define DAC_WaveGeneration_Noise           ((uint32_t)0x00000040)
+#define DAC_WaveGeneration_Triangle        ((uint32_t)0x00000080)
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
+                                    ((WAVE) == DAC_WaveGeneration_Noise) || \
+                                    ((WAVE) == DAC_WaveGeneration_Triangle))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_noise_wave_generation_mask_triangle_wave_generation_max_amplitude 
+  * @{
+  */
+
+#define DAC_LFSRUnmask_Bit0                ((uint32_t)0x00000000)
+#define DAC_LFSRUnmask_Bits1_0             ((uint32_t)0x00000100)
+#define DAC_LFSRUnmask_Bits2_0             ((uint32_t)0x00000200)
+#define DAC_LFSRUnmask_Bits3_0             ((uint32_t)0x00000300)
+#define DAC_LFSRUnmask_Bits4_0             ((uint32_t)0x00000400)
+#define DAC_LFSRUnmask_Bits5_0             ((uint32_t)0x00000500)
+#define DAC_LFSRUnmask_Bits6_0             ((uint32_t)0x00000600)
+#define DAC_LFSRUnmask_Bits7_0             ((uint32_t)0x00000700)
+#define DAC_LFSRUnmask_Bits8_0             ((uint32_t)0x00000800)
+#define DAC_LFSRUnmask_Bits9_0             ((uint32_t)0x00000900)
+#define DAC_LFSRUnmask_Bits10_0            ((uint32_t)0x00000A00)
+#define DAC_LFSRUnmask_Bits11_0            ((uint32_t)0x00000B00)
+#define DAC_TriangleAmplitude_1            ((uint32_t)0x00000000)
+#define DAC_TriangleAmplitude_3            ((uint32_t)0x00000100)
+#define DAC_TriangleAmplitude_7            ((uint32_t)0x00000200)
+#define DAC_TriangleAmplitude_15           ((uint32_t)0x00000300)
+#define DAC_TriangleAmplitude_31           ((uint32_t)0x00000400)
+#define DAC_TriangleAmplitude_63           ((uint32_t)0x00000500)
+#define DAC_TriangleAmplitude_127          ((uint32_t)0x00000600)
+#define DAC_TriangleAmplitude_255          ((uint32_t)0x00000700)
+#define DAC_TriangleAmplitude_511          ((uint32_t)0x00000800)
+#define DAC_TriangleAmplitude_1023         ((uint32_t)0x00000900)
+#define DAC_TriangleAmplitude_2047         ((uint32_t)0x00000A00)
+#define DAC_TriangleAmplitude_4095         ((uint32_t)0x00000B00)
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_1) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_3) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_7) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_15) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_31) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_63) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_127) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_255) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_511) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_1023) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_2047) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_4095))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_output_buffer 
+  * @{
+  */
+
+#define DAC_OutputBuffer_Enable            ((uint32_t)0x00000000)
+#define DAC_OutputBuffer_Disable           ((uint32_t)0x00000002)
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
+                                           ((STATE) == DAC_OutputBuffer_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Channel_selection 
+  * @{
+  */
+
+#define DAC_Channel_1                      ((uint32_t)0x00000000)
+#define DAC_Channel_2                      ((uint32_t)0x00000010)
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
+                                 ((CHANNEL) == DAC_Channel_2))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data_alignement 
+  * @{
+  */
+
+#define DAC_Align_12b_R                    ((uint32_t)0x00000000)
+#define DAC_Align_12b_L                    ((uint32_t)0x00000004)
+#define DAC_Align_8b_R                     ((uint32_t)0x00000008)
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
+                             ((ALIGN) == DAC_Align_12b_L) || \
+                             ((ALIGN) == DAC_Align_8b_R))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_wave_generation 
+  * @{
+  */
+
+#define DAC_Wave_Noise                     ((uint32_t)0x00000040)
+#define DAC_Wave_Triangle                  ((uint32_t)0x00000080)
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
+                           ((WAVE) == DAC_Wave_Triangle))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data 
+  * @{
+  */
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) 
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Functions
+  * @{
+  */
+
+void DAC_DeInit(void);
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
+
+#endif /*__STM32F10x_DAC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dbgmcu.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dbgmcu.h
new file mode 100644
index 0000000..7af3b66
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dbgmcu.h
@@ -0,0 +1,100 @@
+/**
+  ******************************************************************************
+  * @file  stm32f10x_dbgmcu.h
+  * @author  MCD Application Team
+  * @version  V3.0.0
+  * @date  04/06/2009
+  * @brief  This file contains all the functions prototypes for the DBGMCU 
+  *         firmware library.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
© COPYRIGHT 2009 STMicroelectronics

+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_DBGMCU_H
+#define __STM32F10x_DBGMCU_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DBGMCU
+  * @{
+  */
+
+/** @defgroup DBGMCU_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Exported_Constants
+  * @{
+  */
+
+#define DBGMCU_SLEEP                 ((uint32_t)0x00000001)
+#define DBGMCU_STOP                  ((uint32_t)0x00000002)
+#define DBGMCU_STANDBY               ((uint32_t)0x00000004)
+#define DBGMCU_IWDG_STOP             ((uint32_t)0x00000100)
+#define DBGMCU_WWDG_STOP             ((uint32_t)0x00000200)
+#define DBGMCU_TIM1_STOP             ((uint32_t)0x00000400)
+#define DBGMCU_TIM2_STOP             ((uint32_t)0x00000800)
+#define DBGMCU_TIM3_STOP             ((uint32_t)0x00001000)
+#define DBGMCU_TIM4_STOP             ((uint32_t)0x00002000)
+#define DBGMCU_CAN1_STOP             ((uint32_t)0x00004000)
+#define DBGMCU_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00008000)
+#define DBGMCU_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00010000)
+#define DBGMCU_TIM8_STOP             ((uint32_t)0x00020000)
+#define DBGMCU_TIM5_STOP             ((uint32_t)0x00040000)
+#define DBGMCU_TIM6_STOP             ((uint32_t)0x00080000)
+#define DBGMCU_TIM7_STOP             ((uint32_t)0x00100000)
+
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFE000F8) == 0x00) && ((PERIPH) != 0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup DBGMCU_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Exported_Functions
+  * @{
+  */
+
+uint32_t DBGMCU_GetREVID(void);
+uint32_t DBGMCU_GetDEVID(void);
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
+#endif /* __STM32F10x_DBGMCU_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dma.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dma.h
new file mode 100644
index 0000000..95274ad
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dma.h
@@ -0,0 +1,224 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_dma.h
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file contains all the functions prototypes for the
+*                      DMA firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_DMA_H
+#define __STM32F10x_DMA_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* DMA Init structure definition */
+typedef struct
+{
+  u32 DMA_PeripheralBaseAddr;
+  u32 DMA_MemoryBaseAddr;	
+  u32 DMA_DIR;	
+  u32 DMA_BufferSize;   
+  u32 DMA_PeripheralInc; 
+  u32 DMA_MemoryInc;
+  u32 DMA_PeripheralDataSize;
+  u32 DMA_MemoryDataSize;
+  u32 DMA_Mode;  
+  u32 DMA_Priority; 
+  u32 DMA_M2M; 
+}DMA_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* DMA data transfer direction -----------------------------------------------*/
+#define DMA_DIR_PeripheralDST              ((u32)0x00000010)
+#define DMA_DIR_PeripheralSRC              ((u32)0x00000000)
+
+#define IS_DMA_DIR(DIR) ((DIR == DMA_DIR_PeripheralDST) || \
+                         (DIR == DMA_DIR_PeripheralSRC))
+
+/* DMA peripheral incremented mode -------------------------------------------*/
+#define DMA_PeripheralInc_Enable           ((u32)0x00000040)
+#define DMA_PeripheralInc_Disable          ((u32)0x00000000)
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) ((STATE == DMA_PeripheralInc_Enable) || \
+                                            (STATE == DMA_PeripheralInc_Disable))
+
+/* DMA memory incremented mode -----------------------------------------------*/
+#define DMA_MemoryInc_Enable               ((u32)0x00000080)
+#define DMA_MemoryInc_Disable              ((u32)0x00000000)
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) ((STATE == DMA_MemoryInc_Enable) || \
+                                        (STATE == DMA_MemoryInc_Disable))
+
+/* DMA peripheral data size --------------------------------------------------*/
+#define DMA_PeripheralDataSize_Byte        ((u32)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord    ((u32)0x00000100)
+#define DMA_PeripheralDataSize_Word        ((u32)0x00000200)
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) ((SIZE == DMA_PeripheralDataSize_Byte) || \
+                                           (SIZE == DMA_PeripheralDataSize_HalfWord) || \
+                                           (SIZE == DMA_PeripheralDataSize_Word))
+
+/* DMA memory data size ------------------------------------------------------*/
+#define DMA_MemoryDataSize_Byte            ((u32)0x00000000)
+#define DMA_MemoryDataSize_HalfWord        ((u32)0x00000400)
+#define DMA_MemoryDataSize_Word            ((u32)0x00000800)
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) ((SIZE == DMA_MemoryDataSize_Byte) || \
+                                       (SIZE == DMA_MemoryDataSize_HalfWord) || \
+                                       (SIZE == DMA_MemoryDataSize_Word))
+
+/* DMA circular/normal mode --------------------------------------------------*/
+#define DMA_Mode_Circular                  ((u32)0x00000020)
+#define DMA_Mode_Normal                    ((u32)0x00000000)
+
+#define IS_DMA_MODE(MODE) ((MODE == DMA_Mode_Circular) || (MODE == DMA_Mode_Normal))
+
+/* DMA priority level --------------------------------------------------------*/
+#define DMA_Priority_VeryHigh              ((u32)0x00003000)
+#define DMA_Priority_High                  ((u32)0x00002000)
+#define DMA_Priority_Medium                ((u32)0x00001000)
+#define DMA_Priority_Low                   ((u32)0x00000000)
+
+#define IS_DMA_PRIORITY(PRIORITY) ((PRIORITY == DMA_Priority_VeryHigh) || \
+                                   (PRIORITY == DMA_Priority_High) || \
+                                   (PRIORITY == DMA_Priority_Medium) || \
+                                   (PRIORITY == DMA_Priority_Low))
+
+/* DMA memory to memory ------------------------------------------------------*/
+#define DMA_M2M_Enable                     ((u32)0x00004000)
+#define DMA_M2M_Disable                    ((u32)0x00000000)
+
+#define IS_DMA_M2M_STATE(STATE) ((STATE == DMA_M2M_Enable) || (STATE == DMA_M2M_Disable))
+
+/* DMA interrupts definition -------------------------------------------------*/
+#define DMA_IT_TC                          ((u32)0x00000002)
+#define DMA_IT_HT                          ((u32)0x00000004)
+#define DMA_IT_TE                          ((u32)0x00000008)
+
+#define IS_DMA_CONFIG_IT(IT) (((IT & 0xFFFFFFF1) == 0x00) && (IT != 0x00))
+
+#define DMA_IT_GL1                         ((u32)0x00000001)
+#define DMA_IT_TC1                         ((u32)0x00000002)
+#define DMA_IT_HT1                         ((u32)0x00000004)
+#define DMA_IT_TE1                         ((u32)0x00000008)
+#define DMA_IT_GL2                         ((u32)0x00000010)
+#define DMA_IT_TC2                         ((u32)0x00000020)
+#define DMA_IT_HT2                         ((u32)0x00000040)
+#define DMA_IT_TE2                         ((u32)0x00000080)
+#define DMA_IT_GL3                         ((u32)0x00000100)
+#define DMA_IT_TC3                         ((u32)0x00000200)
+#define DMA_IT_HT3                         ((u32)0x00000400)
+#define DMA_IT_TE3                         ((u32)0x00000800)
+#define DMA_IT_GL4                         ((u32)0x00001000)
+#define DMA_IT_TC4                         ((u32)0x00002000)
+#define DMA_IT_HT4                         ((u32)0x00004000)
+#define DMA_IT_TE4                         ((u32)0x00008000)
+#define DMA_IT_GL5                         ((u32)0x00010000)
+#define DMA_IT_TC5                         ((u32)0x00020000)
+#define DMA_IT_HT5                         ((u32)0x00040000)
+#define DMA_IT_TE5                         ((u32)0x00080000)
+#define DMA_IT_GL6                         ((u32)0x00100000)
+#define DMA_IT_TC6                         ((u32)0x00200000)
+#define DMA_IT_HT6                         ((u32)0x00400000)
+#define DMA_IT_TE6                         ((u32)0x00800000)
+#define DMA_IT_GL7                         ((u32)0x01000000)
+#define DMA_IT_TC7                         ((u32)0x02000000)
+#define DMA_IT_HT7                         ((u32)0x04000000)
+#define DMA_IT_TE7                         ((u32)0x08000000)
+
+#define IS_DMA_CLEAR_IT(IT) (((IT & 0xF0000000) == 0x00) && (IT != 0x00))
+#define IS_DMA_GET_IT(IT) ((IT == DMA_IT_GL1) || (IT == DMA_IT_TC1) || \
+                           (IT == DMA_IT_HT1) || (IT == DMA_IT_TE1) || \
+                           (IT == DMA_IT_GL2) || (IT == DMA_IT_TC2) || \
+                           (IT == DMA_IT_HT2) || (IT == DMA_IT_TE2) || \
+                           (IT == DMA_IT_GL3) || (IT == DMA_IT_TC3) || \
+                           (IT == DMA_IT_HT3) || (IT == DMA_IT_TE3) || \
+                           (IT == DMA_IT_GL4) || (IT == DMA_IT_TC4) || \
+                           (IT == DMA_IT_HT4) || (IT == DMA_IT_TE4) || \
+                           (IT == DMA_IT_GL5) || (IT == DMA_IT_TC5) || \
+                           (IT == DMA_IT_HT5) || (IT == DMA_IT_TE5) || \
+                           (IT == DMA_IT_GL6) || (IT == DMA_IT_TC6) || \
+                           (IT == DMA_IT_HT6) || (IT == DMA_IT_TE6) || \
+                           (IT == DMA_IT_GL7) || (IT == DMA_IT_TC7) || \
+                           (IT == DMA_IT_HT7) || (IT == DMA_IT_TE7))
+
+/* DMA flags definition ------------------------------------------------------*/
+#define DMA_FLAG_GL1                       ((u32)0x00000001)
+#define DMA_FLAG_TC1                       ((u32)0x00000002)
+#define DMA_FLAG_HT1                       ((u32)0x00000004)
+#define DMA_FLAG_TE1                       ((u32)0x00000008)
+#define DMA_FLAG_GL2                       ((u32)0x00000010)
+#define DMA_FLAG_TC2                       ((u32)0x00000020)
+#define DMA_FLAG_HT2                       ((u32)0x00000040)
+#define DMA_FLAG_TE2                       ((u32)0x00000080)
+#define DMA_FLAG_GL3                       ((u32)0x00000100)
+#define DMA_FLAG_TC3                       ((u32)0x00000200)
+#define DMA_FLAG_HT3                       ((u32)0x00000400)
+#define DMA_FLAG_TE3                       ((u32)0x00000800)
+#define DMA_FLAG_GL4                       ((u32)0x00001000)
+#define DMA_FLAG_TC4                       ((u32)0x00002000)
+#define DMA_FLAG_HT4                       ((u32)0x00004000)
+#define DMA_FLAG_TE4                       ((u32)0x00008000)
+#define DMA_FLAG_GL5                       ((u32)0x00010000)
+#define DMA_FLAG_TC5                       ((u32)0x00020000)
+#define DMA_FLAG_HT5                       ((u32)0x00040000)
+#define DMA_FLAG_TE5                       ((u32)0x00080000)
+#define DMA_FLAG_GL6                       ((u32)0x00100000)
+#define DMA_FLAG_TC6                       ((u32)0x00200000)
+#define DMA_FLAG_HT6                       ((u32)0x00400000)
+#define DMA_FLAG_TE6                       ((u32)0x00800000)
+#define DMA_FLAG_GL7                       ((u32)0x01000000)
+#define DMA_FLAG_TC7                       ((u32)0x02000000)
+#define DMA_FLAG_HT7                       ((u32)0x04000000)
+#define DMA_FLAG_TE7                       ((u32)0x08000000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) (((FLAG & 0xF0000000) == 0x00) && (FLAG != 0x00))
+#define IS_DMA_GET_FLAG(FLAG) ((FLAG == DMA_FLAG_GL1) || (FLAG == DMA_FLAG_TC1) || \
+                               (FLAG == DMA_FLAG_HT1) || (FLAG == DMA_FLAG_TE1) || \
+                               (FLAG == DMA_FLAG_GL2) || (FLAG == DMA_FLAG_TC2) || \
+                               (FLAG == DMA_FLAG_HT2) || (FLAG == DMA_FLAG_TE2) || \
+                               (FLAG == DMA_FLAG_GL3) || (FLAG == DMA_FLAG_TC3) || \
+                               (FLAG == DMA_FLAG_HT3) || (FLAG == DMA_FLAG_TE3) || \
+                               (FLAG == DMA_FLAG_GL4) || (FLAG == DMA_FLAG_TC4) || \
+                               (FLAG == DMA_FLAG_HT4) || (FLAG == DMA_FLAG_TE4) || \
+                               (FLAG == DMA_FLAG_GL5) || (FLAG == DMA_FLAG_TC5) || \
+                               (FLAG == DMA_FLAG_HT5) || (FLAG == DMA_FLAG_TE5) || \
+                               (FLAG == DMA_FLAG_GL6) || (FLAG == DMA_FLAG_TC6) || \
+                               (FLAG == DMA_FLAG_HT6) || (FLAG == DMA_FLAG_TE6) || \
+                               (FLAG == DMA_FLAG_GL7) || (FLAG == DMA_FLAG_TC7) || \
+                               (FLAG == DMA_FLAG_HT7) || (FLAG == DMA_FLAG_TE7))
+
+/* DMA Buffer Size -----------------------------------------------------------*/
+#define IS_DMA_BUFFER_SIZE(SIZE) ((SIZE >= 0x1) && (SIZE < 0x10000))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx);
+void DMA_Init(DMA_Channel_TypeDef*  DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct);
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+void DMA_Cmd(DMA_Channel_TypeDef*  DMA_Channelx, FunctionalState NewState);
+void DMA_ITConfig(DMA_Channel_TypeDef*  DMA_Channelx, u32 DMA_IT, FunctionalState NewState);
+u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef*  DMA_Channelx);
+FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG);
+void DMA_ClearFlag(u32 DMA_FLAG);
+ITStatus DMA_GetITStatus(u32 DMA_IT);
+void DMA_ClearITPendingBit(u32 DMA_IT);
+
+#endif /*__STM32F10x_DMA_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_exti.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_exti.h
new file mode 100644
index 0000000..2c6d4b6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_exti.h
@@ -0,0 +1,111 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_exti.h
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file contains all the functions prototypes for the
+*                      EXTI firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_EXTI_H
+#define __STM32F10x_EXTI_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* EXTI mode enumeration -----------------------------------------------------*/
+typedef enum
+{
+  EXTI_Mode_Interrupt = 0x00,
+  EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef;
+
+#define IS_EXTI_MODE(MODE) ((MODE == EXTI_Mode_Interrupt) || (MODE == EXTI_Mode_Event))
+                            
+/* EXTI Trigger enumeration --------------------------------------------------*/
+typedef enum
+{
+  EXTI_Trigger_Rising = 0x08,
+  EXTI_Trigger_Falling = 0x0C,  
+  EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef;
+
+#define IS_EXTI_TRIGGER(TRIGGER) ((TRIGGER == EXTI_Trigger_Rising) || \
+                                  (TRIGGER == EXTI_Trigger_Falling) || \
+                                  (TRIGGER == EXTI_Trigger_Rising_Falling))
+
+/* EXTI Init Structure definition --------------------------------------------*/
+typedef struct
+{
+  u32 EXTI_Line;
+  EXTIMode_TypeDef EXTI_Mode;
+  EXTITrigger_TypeDef EXTI_Trigger;
+  FunctionalState EXTI_LineCmd;
+}EXTI_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* EXTI Lines ----------------------------------------------------------------*/
+#define EXTI_Line0       ((u32)0x00001)  /* External interrupt line 0 */
+#define EXTI_Line1       ((u32)0x00002)  /* External interrupt line 1 */
+#define EXTI_Line2       ((u32)0x00004)  /* External interrupt line 2 */
+#define EXTI_Line3       ((u32)0x00008)  /* External interrupt line 3 */
+#define EXTI_Line4       ((u32)0x00010)  /* External interrupt line 4 */
+#define EXTI_Line5       ((u32)0x00020)  /* External interrupt line 5 */
+#define EXTI_Line6       ((u32)0x00040)  /* External interrupt line 6 */
+#define EXTI_Line7       ((u32)0x00080)  /* External interrupt line 7 */
+#define EXTI_Line8       ((u32)0x00100)  /* External interrupt line 8 */
+#define EXTI_Line9       ((u32)0x00200)  /* External interrupt line 9 */
+#define EXTI_Line10      ((u32)0x00400)  /* External interrupt line 10 */
+#define EXTI_Line11      ((u32)0x00800)  /* External interrupt line 11 */
+#define EXTI_Line12      ((u32)0x01000)  /* External interrupt line 12 */
+#define EXTI_Line13      ((u32)0x02000)  /* External interrupt line 13 */
+#define EXTI_Line14      ((u32)0x04000)  /* External interrupt line 14 */
+#define EXTI_Line15      ((u32)0x08000)  /* External interrupt line 15 */
+#define EXTI_Line16      ((u32)0x10000)  /* External interrupt line 16
+                                            Connected to the PVD Output */
+#define EXTI_Line17      ((u32)0x20000)  /* External interrupt line 17 
+                                            Connected to the RTC Alarm event */
+#define EXTI_Line18      ((u32)0x40000)  /* External interrupt line 18 
+                                            Connected to the USB Wakeup from 
+                                            suspend event */
+
+#define IS_EXTI_LINE(LINE) (((LINE & (u32)0xFFF80000) == 0x00) && (LINE != (u16)0x00))
+
+#define IS_GET_EXTI_LINE(LINE) ((LINE == EXTI_Line0) || (LINE == EXTI_Line1) || \
+                            (LINE == EXTI_Line2) || (LINE == EXTI_Line3) || \
+                            (LINE == EXTI_Line4) || (LINE == EXTI_Line5) || \
+                            (LINE == EXTI_Line6) || (LINE == EXTI_Line7) || \
+                            (LINE == EXTI_Line8) || (LINE == EXTI_Line9) || \
+                            (LINE == EXTI_Line10) || (LINE == EXTI_Line11) || \
+                            (LINE == EXTI_Line12) || (LINE == EXTI_Line13) || \
+                            (LINE == EXTI_Line14) || (LINE == EXTI_Line15) || \
+                            (LINE == EXTI_Line16) || (LINE == EXTI_Line17) || \
+                            (LINE == EXTI_Line18))
+                                 
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void EXTI_DeInit(void);
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(u32 EXTI_Line);
+FlagStatus EXTI_GetFlagStatus(u32 EXTI_Line);
+void EXTI_ClearFlag(u32 EXTI_Line);
+ITStatus EXTI_GetITStatus(u32 EXTI_Line);
+void EXTI_ClearITPendingBit(u32 EXTI_Line);
+
+#endif /* __STM32F10x_EXTI_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_flash.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_flash.h
new file mode 100644
index 0000000..5daf2b6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_flash.h
@@ -0,0 +1,305 @@
+/**
+  ******************************************************************************
+  * @file  stm32f10x_flash.h
+  * @author  MCD Application Team
+  * @version  V3.0.0
+  * @date  04/06/2009
+  * @brief  This file contains all the functions prototypes for the FLASH 
+  *         firmware library.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
© COPYRIGHT 2009 STMicroelectronics

+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_FLASH_H
+#define __STM32F10x_FLASH_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */
+
+/** @defgroup FLASH_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  FLASH Status  
+  */
+
+typedef enum
+{ 
+  FLASH_BUSY = 1,
+  FLASH_ERROR_PG,
+  FLASH_ERROR_WRP,
+  FLASH_COMPLETE,
+  FLASH_TIMEOUT
+}FLASH_Status;
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Constants
+  * @{
+  */
+
+/** @defgroup Flash_Latency 
+  * @{
+  */
+
+#define FLASH_Latency_0                ((uint32_t)0x00000000)  /* FLASH Zero Latency cycle */
+#define FLASH_Latency_1                ((uint32_t)0x00000001)  /* FLASH One Latency cycle */
+#define FLASH_Latency_2                ((uint32_t)0x00000002)  /* FLASH Two Latency cycles */
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
+                                   ((LATENCY) == FLASH_Latency_1) || \
+                                   ((LATENCY) == FLASH_Latency_2))
+/**
+  * @}
+  */
+
+/** @defgroup Half_Cycle_Enable_Disable 
+  * @{
+  */
+
+#define FLASH_HalfCycleAccess_Enable   ((uint32_t)0x00000008)  /* FLASH Half Cycle Enable */
+#define FLASH_HalfCycleAccess_Disable  ((uint32_t)0x00000000)  /* FLASH Half Cycle Disable */
+#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
+                                               ((STATE) == FLASH_HalfCycleAccess_Disable)) 
+/**
+  * @}
+  */
+
+/** @defgroup Prefetch_Buffer_Enable_Disable 
+  * @{
+  */
+
+#define FLASH_PrefetchBuffer_Enable    ((uint32_t)0x00000010)  /* FLASH Prefetch Buffer Enable */
+#define FLASH_PrefetchBuffer_Disable   ((uint32_t)0x00000000)  /* FLASH Prefetch Buffer Disable */
+#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
+                                              ((STATE) == FLASH_PrefetchBuffer_Disable)) 
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_Write_Protection 
+  * @{
+  */
+
+/* Values to be used with STM32F10Xxx Medium-density devices: FLASH memory density
+   ranges between 32 and 128 Kbytes with page size equal to 1 Kbytes */
+#define FLASH_WRProt_Pages0to3         ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */
+#define FLASH_WRProt_Pages4to7         ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */
+#define FLASH_WRProt_Pages8to11        ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */
+#define FLASH_WRProt_Pages12to15       ((uint32_t)0x00000008) /* Write protection of page 12 to 15 */
+#define FLASH_WRProt_Pages16to19       ((uint32_t)0x00000010) /* Write protection of page 16 to 19 */
+#define FLASH_WRProt_Pages20to23       ((uint32_t)0x00000020) /* Write protection of page 20 to 23 */
+#define FLASH_WRProt_Pages24to27       ((uint32_t)0x00000040) /* Write protection of page 24 to 27 */
+#define FLASH_WRProt_Pages28to31       ((uint32_t)0x00000080) /* Write protection of page 28 to 31 */
+#define FLASH_WRProt_Pages32to35       ((uint32_t)0x00000100) /* Write protection of page 32 to 35 */
+#define FLASH_WRProt_Pages36to39       ((uint32_t)0x00000200) /* Write protection of page 36 to 39 */
+#define FLASH_WRProt_Pages40to43       ((uint32_t)0x00000400) /* Write protection of page 40 to 43 */
+#define FLASH_WRProt_Pages44to47       ((uint32_t)0x00000800) /* Write protection of page 44 to 47 */
+#define FLASH_WRProt_Pages48to51       ((uint32_t)0x00001000) /* Write protection of page 48 to 51 */
+#define FLASH_WRProt_Pages52to55       ((uint32_t)0x00002000) /* Write protection of page 52 to 55 */
+#define FLASH_WRProt_Pages56to59       ((uint32_t)0x00004000) /* Write protection of page 56 to 59 */
+#define FLASH_WRProt_Pages60to63       ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */
+#define FLASH_WRProt_Pages64to67       ((uint32_t)0x00010000) /* Write protection of page 64 to 67 */
+#define FLASH_WRProt_Pages68to71       ((uint32_t)0x00020000) /* Write protection of page 68 to 71 */
+#define FLASH_WRProt_Pages72to75       ((uint32_t)0x00040000) /* Write protection of page 72 to 75 */
+#define FLASH_WRProt_Pages76to79       ((uint32_t)0x00080000) /* Write protection of page 76 to 79 */
+#define FLASH_WRProt_Pages80to83       ((uint32_t)0x00100000) /* Write protection of page 80 to 83 */
+#define FLASH_WRProt_Pages84to87       ((uint32_t)0x00200000) /* Write protection of page 84 to 87 */
+#define FLASH_WRProt_Pages88to91       ((uint32_t)0x00400000) /* Write protection of page 88 to 91 */
+#define FLASH_WRProt_Pages92to95       ((uint32_t)0x00800000) /* Write protection of page 92 to 95 */
+#define FLASH_WRProt_Pages96to99       ((uint32_t)0x01000000) /* Write protection of page 96 to 99 */
+#define FLASH_WRProt_Pages100to103     ((uint32_t)0x02000000) /* Write protection of page 100 to 103 */
+#define FLASH_WRProt_Pages104to107     ((uint32_t)0x04000000) /* Write protection of page 104 to 107 */
+#define FLASH_WRProt_Pages108to111     ((uint32_t)0x08000000) /* Write protection of page 108 to 111 */
+#define FLASH_WRProt_Pages112to115     ((uint32_t)0x10000000) /* Write protection of page 112 to 115 */
+#define FLASH_WRProt_Pages116to119     ((uint32_t)0x20000000) /* Write protection of page 115 to 119 */
+#define FLASH_WRProt_Pages120to123     ((uint32_t)0x40000000) /* Write protection of page 120 to 123 */
+#define FLASH_WRProt_Pages124to127     ((uint32_t)0x80000000) /* Write protection of page 124 to 127 */
+
+/* Values to be used with STM32F10Xxx High-density devices: FLASH memory density
+   ranges between 256 and 512 Kbytes with page size equal to 2 Kbytes */
+#define FLASH_WRProt_Pages0to1         ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
+#define FLASH_WRProt_Pages2to3         ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
+#define FLASH_WRProt_Pages4to5         ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
+#define FLASH_WRProt_Pages6to7         ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
+#define FLASH_WRProt_Pages8to9         ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
+#define FLASH_WRProt_Pages10to11       ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
+#define FLASH_WRProt_Pages12to13       ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
+#define FLASH_WRProt_Pages14to15       ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
+#define FLASH_WRProt_Pages16to17       ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
+#define FLASH_WRProt_Pages18to19       ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
+#define FLASH_WRProt_Pages20to21       ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
+#define FLASH_WRProt_Pages22to23       ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
+#define FLASH_WRProt_Pages24to25       ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
+#define FLASH_WRProt_Pages26to27       ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
+#define FLASH_WRProt_Pages28to29       ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
+#define FLASH_WRProt_Pages30to31       ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
+#define FLASH_WRProt_Pages32to33       ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
+#define FLASH_WRProt_Pages34to35       ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
+#define FLASH_WRProt_Pages36to37       ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
+#define FLASH_WRProt_Pages38to39       ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
+#define FLASH_WRProt_Pages40to41       ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
+#define FLASH_WRProt_Pages42to43       ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
+#define FLASH_WRProt_Pages44to45       ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
+#define FLASH_WRProt_Pages46to47       ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
+#define FLASH_WRProt_Pages48to49       ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
+#define FLASH_WRProt_Pages50to51       ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
+#define FLASH_WRProt_Pages52to53       ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
+#define FLASH_WRProt_Pages54to55       ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
+#define FLASH_WRProt_Pages56to57       ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
+#define FLASH_WRProt_Pages58to59       ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
+#define FLASH_WRProt_Pages60to61       ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
+#define FLASH_WRProt_Pages62to255      ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */
+#define FLASH_WRProt_AllPages          ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */
+
+#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
+
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF))
+
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
+
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_IWatchdog 
+  * @{
+  */
+
+#define OB_IWDG_SW                     ((uint16_t)0x0001)  /* Software IWDG selected */
+#define OB_IWDG_HW                     ((uint16_t)0x0000)  /* Hardware IWDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_nRST_STOP 
+  * @{
+  */
+
+#define OB_STOP_NoRST                  ((uint16_t)0x0002) /* No reset generated when entering in STOP */
+#define OB_STOP_RST                    ((uint16_t)0x0000) /* Reset generated when entering in STOP */
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
+
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_nRST_STDBY 
+  * @{
+  */
+
+#define OB_STDBY_NoRST                 ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */
+#define OB_STDBY_RST                   ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Interrupts 
+  * @{
+  */
+
+#define FLASH_IT_ERROR                 ((uint32_t)0x00000400)  /* FPEC error interrupt source */
+#define FLASH_IT_EOP                   ((uint32_t)0x00001000)  /* End of FLASH Operation Interrupt source */
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Flags 
+  * @{
+  */
+
+#define FLASH_FLAG_BSY                 ((uint32_t)0x00000001)  /* FLASH Busy flag */
+#define FLASH_FLAG_EOP                 ((uint32_t)0x00000020)  /* FLASH End of Operation flag */
+#define FLASH_FLAG_PGERR               ((uint32_t)0x00000004)  /* FLASH Program error flag */
+#define FLASH_FLAG_WRPRTERR            ((uint32_t)0x00000010)  /* FLASH Write protected error flag */
+#define FLASH_FLAG_OPTERR              ((uint32_t)0x00000001)  /* FLASH Option Byte error flag */
+ 
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
+#define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
+                                  ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
+                                  ((FLAG) == FLASH_FLAG_OPTERR))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions
+  * @{
+  */
+
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_EraseOptionBytes(void);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
+uint32_t FLASH_GetUserOptionByte(void);
+uint32_t FLASH_GetWriteProtectionOptionByte(void);
+FlagStatus FLASH_GetReadOutProtectionStatus(void);
+FlagStatus FLASH_GetPrefetchBufferStatus(void);
+void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG);
+void FLASH_ClearFlag(uint16_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
+
+#endif /* __STM32F10x_FLASH_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_fsmc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_fsmc.h
new file mode 100644
index 0000000..c1ea587
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_fsmc.h
@@ -0,0 +1,598 @@
+/**
+  ******************************************************************************
+  * @file  stm32f10x_fsmc.h
+  * @author  MCD Application Team
+  * @version  V3.0.0
+  * @date  04/06/2009
+  * @brief  This file contains all the functions prototypes for the FSMC 
+  *         firmware library.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
© COPYRIGHT 2009 STMicroelectronics

+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_FSMC_H
+#define __STM32F10x_FSMC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup FSMC
+  * @{
+  */
+
+/** @defgroup FSMC_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  Timing parameters For NOR/SRAM Banks  
+  */
+
+typedef struct
+{
+  uint32_t FSMC_AddressSetupTime;
+  uint32_t FSMC_AddressHoldTime;
+  uint32_t FSMC_DataSetupTime;
+  uint32_t FSMC_BusTurnAroundDuration;
+  uint32_t FSMC_CLKDivision;
+  uint32_t FSMC_DataLatency;
+  uint32_t FSMC_AccessMode;
+}FSMC_NORSRAMTimingInitTypeDef;
+
+/** 
+  * @brief  FSMC NOR/SRAM Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t FSMC_Bank;
+  uint32_t FSMC_DataAddressMux;
+  uint32_t FSMC_MemoryType;
+  uint32_t FSMC_MemoryDataWidth;
+  uint32_t FSMC_BurstAccessMode;
+  uint32_t FSMC_WaitSignalPolarity;
+  uint32_t FSMC_WrapMode;
+  uint32_t FSMC_WaitSignalActive;
+  uint32_t FSMC_WriteOperation;
+  uint32_t FSMC_WaitSignal;
+  uint32_t FSMC_ExtendedMode;
+  uint32_t FSMC_WriteBurst;  
+  FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct;/* Timing Parameters for write and read access if the  ExtendedMode is not used*/
+  FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;/* Timing Parameters for write access if the  ExtendedMode is used*/
+}FSMC_NORSRAMInitTypeDef;
+
+/** 
+  * @brief  Timing parameters For FSMC NAND and PCCARD Banks
+  */
+
+typedef struct
+{
+  uint32_t FSMC_SetupTime;
+  uint32_t FSMC_WaitSetupTime;
+  uint32_t FSMC_HoldSetupTime;
+  uint32_t FSMC_HiZSetupTime;
+}FSMC_NAND_PCCARDTimingInitTypeDef;
+
+/** 
+  * @brief  FSMC NAND Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t FSMC_Bank;
+  uint32_t FSMC_Waitfeature;
+  uint32_t FSMC_MemoryDataWidth;
+  uint32_t FSMC_ECC;
+  uint32_t FSMC_ECCPageSize;
+  uint32_t FSMC_TCLRSetupTime;
+  uint32_t FSMC_TARSetupTime;  
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;/* FSMC Common Space Timing */ 
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct;/* FSMC Attribute Space Timing */
+}FSMC_NANDInitTypeDef;
+
+/** 
+  * @brief  FSMC PCCARD Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t FSMC_Waitfeature;
+  uint32_t FSMC_TCLRSetupTime;
+  uint32_t FSMC_TARSetupTime;  
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;/* FSMC Common Space Timing */
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct;  /* FSMC Attribute Space Timing */
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_IOSpaceTimingStruct;  /* FSMC IO Space Timing */
+}FSMC_PCCARDInitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup FSMC_Banks_definitions 
+  * @{
+  */
+
+#define FSMC_Bank1_NORSRAM1                             ((uint32_t)0x00000000)
+#define FSMC_Bank1_NORSRAM2                             ((uint32_t)0x00000002)
+#define FSMC_Bank1_NORSRAM3                             ((uint32_t)0x00000004)
+#define FSMC_Bank1_NORSRAM4                             ((uint32_t)0x00000006)
+#define FSMC_Bank2_NAND                                 ((uint32_t)0x00000010)
+#define FSMC_Bank3_NAND                                 ((uint32_t)0x00000100)
+#define FSMC_Bank4_PCCARD                               ((uint32_t)0x00001000)
+
+#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
+                                    ((BANK) == FSMC_Bank1_NORSRAM2) || \
+                                    ((BANK) == FSMC_Bank1_NORSRAM3) || \
+                                    ((BANK) == FSMC_Bank1_NORSRAM4))
+
+#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+                                 ((BANK) == FSMC_Bank3_NAND))
+
+#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+                                    ((BANK) == FSMC_Bank3_NAND) || \
+                                    ((BANK) == FSMC_Bank4_PCCARD))
+
+#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+                               ((BANK) == FSMC_Bank3_NAND) || \
+                               ((BANK) == FSMC_Bank4_PCCARD))
+/**
+  * @}
+  */
+
+/** @defgroup NOR_SRAM_Banks 
+  * @{
+  */
+
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing 
+  * @{
+  */
+
+#define FSMC_DataAddressMux_Disable                       ((uint32_t)0x00000000)
+#define FSMC_DataAddressMux_Enable                        ((uint32_t)0x00000002)
+#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
+                          ((MUX) == FSMC_DataAddressMux_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Memory_Type 
+  * @{
+  */
+
+#define FSMC_MemoryType_SRAM                            ((uint32_t)0x00000000)
+#define FSMC_MemoryType_PSRAM                           ((uint32_t)0x00000004)
+#define FSMC_MemoryType_NOR                             ((uint32_t)0x00000008)
+#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
+                                ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
+                                ((MEMORY) == FSMC_MemoryType_NOR))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Data_Width 
+  * @{
+  */
+
+#define FSMC_MemoryDataWidth_8b                         ((uint32_t)0x00000000)
+#define FSMC_MemoryDataWidth_16b                        ((uint32_t)0x00000010)
+#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
+                                     ((WIDTH) == FSMC_MemoryDataWidth_16b))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Burst_Access_Mode 
+  * @{
+  */
+
+#define FSMC_BurstAccessMode_Disable                    ((uint32_t)0x00000000) 
+#define FSMC_BurstAccessMode_Enable                     ((uint32_t)0x00000100)
+#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
+                                  ((STATE) == FSMC_BurstAccessMode_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Signal_Polarity 
+  * @{
+  */
+
+#define FSMC_WaitSignalPolarity_Low                     ((uint32_t)0x00000000)
+#define FSMC_WaitSignalPolarity_High                    ((uint32_t)0x00000200)
+#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
+                                         ((POLARITY) == FSMC_WaitSignalPolarity_High)) 
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wrap_Mode 
+  * @{
+  */
+
+#define FSMC_WrapMode_Disable                           ((uint32_t)0x00000000)
+#define FSMC_WrapMode_Enable                            ((uint32_t)0x00000400) 
+#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
+                                 ((MODE) == FSMC_WrapMode_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Timing 
+  * @{
+  */
+
+#define FSMC_WaitSignalActive_BeforeWaitState           ((uint32_t)0x00000000)
+#define FSMC_WaitSignalActive_DuringWaitState           ((uint32_t)0x00000800) 
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
+                                            ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Write_Operation 
+  * @{
+  */
+
+#define FSMC_WriteOperation_Disable                     ((uint32_t)0x00000000)
+#define FSMC_WriteOperation_Enable                      ((uint32_t)0x00001000)
+#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
+                                            ((OPERATION) == FSMC_WriteOperation_Enable))
+                              
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Signal 
+  * @{
+  */
+
+#define FSMC_WaitSignal_Disable                         ((uint32_t)0x00000000)
+#define FSMC_WaitSignal_Enable                          ((uint32_t)0x00002000) 
+#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
+                                      ((SIGNAL) == FSMC_WaitSignal_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Extended_Mode 
+  * @{
+  */
+
+#define FSMC_ExtendedMode_Disable                       ((uint32_t)0x00000000)
+#define FSMC_ExtendedMode_Enable                        ((uint32_t)0x00004000)
+
+#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
+                                     ((MODE) == FSMC_ExtendedMode_Enable)) 
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Write_Burst 
+  * @{
+  */
+
+#define FSMC_WriteBurst_Disable                         ((uint32_t)0x00000000)
+#define FSMC_WriteBurst_Enable                          ((uint32_t)0x00080000) 
+#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
+                                    ((BURST) == FSMC_WriteBurst_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Address_Setup_Time 
+  * @{
+  */
+
+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Address_Hold_Time 
+  * @{
+  */
+
+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Data_Setup_Time 
+  * @{
+  */
+
+#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Bus_Turn_around_Duration 
+  * @{
+  */
+
+#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_CLK_Division 
+  * @{
+  */
+
+#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Data_Latency 
+  * @{
+  */
+
+#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Access_Mode 
+  * @{
+  */
+
+#define FSMC_AccessMode_A                               ((uint32_t)0x00000000)
+#define FSMC_AccessMode_B                               ((uint32_t)0x10000000) 
+#define FSMC_AccessMode_C                               ((uint32_t)0x20000000)
+#define FSMC_AccessMode_D                               ((uint32_t)0x30000000)
+#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
+                                   ((MODE) == FSMC_AccessMode_B) || \
+                                   ((MODE) == FSMC_AccessMode_C) || \
+                                   ((MODE) == FSMC_AccessMode_D)) 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/** @defgroup NAND_and_PCCARD_Banks 
+  * @{
+  */
+
+/** @defgroup FSMC_Wait_feature 
+  * @{
+  */
+
+#define FSMC_Waitfeature_Disable                        ((uint32_t)0x00000000)
+#define FSMC_Waitfeature_Enable                         ((uint32_t)0x00000002)
+#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
+                                       ((FEATURE) == FSMC_Waitfeature_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Memory_Data_Width 
+  * @{
+  */ 
+#define FSMC_MemoryDataWidth_8b                         ((uint32_t)0x00000000)
+#define FSMC_MemoryDataWidth_16b                        ((uint32_t)0x00000010)
+#define IS_FSMC_DATA_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
+                                   ((WIDTH) == FSMC_MemoryDataWidth_16b))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_ECC 
+  * @{
+  */
+
+#define FSMC_ECC_Disable                                ((uint32_t)0x00000000)
+#define FSMC_ECC_Enable                                 ((uint32_t)0x00000040)
+#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
+                                  ((STATE) == FSMC_ECC_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_ECC_Page_Size 
+  * @{
+  */
+
+#define FSMC_ECCPageSize_256Bytes                       ((uint32_t)0x00000000)
+#define FSMC_ECCPageSize_512Bytes                       ((uint32_t)0x00020000)
+#define FSMC_ECCPageSize_1024Bytes                      ((uint32_t)0x00040000)
+#define FSMC_ECCPageSize_2048Bytes                      ((uint32_t)0x00060000)
+#define FSMC_ECCPageSize_4096Bytes                      ((uint32_t)0x00080000)
+#define FSMC_ECCPageSize_8192Bytes                      ((uint32_t)0x000A0000)
+#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_8192Bytes))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_TCLR_Setup_Time 
+  * @{
+  */
+
+#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_TAR_Setup_Time 
+  * @{
+  */
+
+#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Setup_Time 
+  * @{
+  */
+
+#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Setup_Time 
+  * @{
+  */
+
+#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Hold_Setup_Time 
+  * @{
+  */
+
+#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_HiZ_Setup_Time 
+  * @{
+  */
+
+#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Interrupt_sources 
+  * @{
+  */
+
+#define FSMC_IT_RisingEdge                              ((uint32_t)0x00000008)
+#define FSMC_IT_Level                                   ((uint32_t)0x00000010)
+#define FSMC_IT_FallingEdge                             ((uint32_t)0x00000020)
+#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
+#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
+                            ((IT) == FSMC_IT_Level) || \
+                            ((IT) == FSMC_IT_FallingEdge)) 
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Flags 
+  * @{
+  */
+
+#define FSMC_FLAG_RisingEdge                            ((uint32_t)0x00000001)
+#define FSMC_FLAG_Level                                 ((uint32_t)0x00000002)
+#define FSMC_FLAG_FallingEdge                           ((uint32_t)0x00000004)
+#define FSMC_FLAG_FEMPT                                 ((uint32_t)0x00000040)
+#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
+                                ((FLAG) == FSMC_FLAG_Level) || \
+                                ((FLAG) == FSMC_FLAG_FallingEdge) || \
+                                ((FLAG) == FSMC_FLAG_FEMPT))
+
+#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Exported_Functions
+  * @{
+  */
+
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
+void FSMC_NANDDeInit(uint32_t FSMC_Bank);
+void FSMC_PCCARDDeInit(void);
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+void FSMC_PCCARDCmd(FunctionalState NewState);
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+
+#endif /*__STM32F10x_FSMC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_gpio.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_gpio.h
new file mode 100644
index 0000000..8d6ef84
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_gpio.h
@@ -0,0 +1,195 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_gpio.h
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file contains all the functions prototypes for the
+*                      GPIO firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_GPIO_H
+#define __STM32F10x_GPIO_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Output Maximum frequency selection ----------------------------------------*/
+typedef enum
+{
+  GPIO_Speed_10MHz = 1,
+  GPIO_Speed_2MHz,
+  GPIO_Speed_50MHz
+}GPIOSpeed_TypeDef;
+
+#define IS_GPIO_SPEED(SPEED) ((SPEED == GPIO_Speed_10MHz) || (SPEED == GPIO_Speed_2MHz) || \
+                              (SPEED == GPIO_Speed_50MHz))
+
+/* Configuration Mode enumeration --------------------------------------------*/
+typedef enum
+{ GPIO_Mode_AIN = 0x0,
+  GPIO_Mode_IN_FLOATING = 0x04,
+  GPIO_Mode_IPD = 0x28,
+  GPIO_Mode_IPU = 0x48,
+  GPIO_Mode_Out_OD = 0x14,
+  GPIO_Mode_Out_PP = 0x10,
+  GPIO_Mode_AF_OD = 0x1C,
+  GPIO_Mode_AF_PP = 0x18
+}GPIOMode_TypeDef;
+
+#define IS_GPIO_MODE(MODE) ((MODE == GPIO_Mode_AIN) || (MODE == GPIO_Mode_IN_FLOATING) || \
+                            (MODE == GPIO_Mode_IPD) || (MODE == GPIO_Mode_IPU) || \
+                            (MODE == GPIO_Mode_Out_OD) || (MODE == GPIO_Mode_Out_PP) || \
+                            (MODE == GPIO_Mode_AF_OD) || (MODE == GPIO_Mode_AF_PP))
+
+/* GPIO Init structure definition */
+typedef struct
+{
+  u16 GPIO_Pin;
+  GPIOSpeed_TypeDef GPIO_Speed;
+  GPIOMode_TypeDef GPIO_Mode;
+}GPIO_InitTypeDef;
+
+/* Bit_SET and Bit_RESET enumeration -----------------------------------------*/
+typedef enum
+{ Bit_RESET = 0,
+  Bit_SET
+}BitAction;
+#define IS_GPIO_BIT_ACTION(ACTION) ((ACTION == Bit_RESET) || (ACTION == Bit_SET))
+
+/* Exported constants --------------------------------------------------------*/
+/* GPIO pins define ----------------------------------------------------------*/
+#define GPIO_Pin_0                 ((u16)0x0001)  /* Pin 0 selected */
+#define GPIO_Pin_1                 ((u16)0x0002)  /* Pin 1 selected */
+#define GPIO_Pin_2                 ((u16)0x0004)  /* Pin 2 selected */
+#define GPIO_Pin_3                 ((u16)0x0008)  /* Pin 3 selected */
+#define GPIO_Pin_4                 ((u16)0x0010)  /* Pin 4 selected */
+#define GPIO_Pin_5                 ((u16)0x0020)  /* Pin 5 selected */
+#define GPIO_Pin_6                 ((u16)0x0040)  /* Pin 6 selected */
+#define GPIO_Pin_7                 ((u16)0x0080)  /* Pin 7 selected */
+#define GPIO_Pin_8                 ((u16)0x0100)  /* Pin 8 selected */
+#define GPIO_Pin_9                 ((u16)0x0200)  /* Pin 9 selected */
+#define GPIO_Pin_10                ((u16)0x0400)  /* Pin 10 selected */
+#define GPIO_Pin_11                ((u16)0x0800)  /* Pin 11 selected */
+#define GPIO_Pin_12                ((u16)0x1000)  /* Pin 12 selected */
+#define GPIO_Pin_13                ((u16)0x2000)  /* Pin 13 selected */
+#define GPIO_Pin_14                ((u16)0x4000)  /* Pin 14 selected */
+#define GPIO_Pin_15                ((u16)0x8000)  /* Pin 15 selected */
+#define GPIO_Pin_All               ((u16)0xFFFF)  /* All pins selected */
+
+#define IS_GPIO_PIN(PIN) (((PIN & (u16)0x00) == 0x00) && (PIN != (u16)0x00))
+
+/* GPIO Remap define ---------------------------------------------------------*/
+#define GPIO_Remap_SPI1            ((u32)0x00000001)  /* SPI1 Alternate Function mapping */
+#define GPIO_Remap_I2C1            ((u32)0x00000002)  /* I2C1 Alternate Function mapping */
+#define GPIO_Remap_USART1          ((u32)0x00000004)  /* USART1 Alternate Function mapping */
+#define GPIO_Remap_USART2          ((u32)0x00000008)  /* USART2 Alternate Function mapping */
+#define GPIO_PartialRemap_USART3   ((u32)0x00140010)  /* USART3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART3      ((u32)0x00140030)  /* USART3 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM1     ((u32)0x00160040)  /* TIM1 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM1        ((u32)0x001600C0)  /* TIM1 Full Alternate Function mapping */
+#define GPIO_PartialRemap1_TIM2    ((u32)0x00180100)  /* TIM2 Partial1 Alternate Function mapping */
+#define GPIO_PartialRemap2_TIM2    ((u32)0x00180200)  /* TIM2 Partial2 Alternate Function mapping */
+#define GPIO_FullRemap_TIM2        ((u32)0x00180300)  /* TIM2 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM3     ((u32)0x001A0800)  /* TIM3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM3        ((u32)0x001A0C00)  /* TIM3 Full Alternate Function mapping */
+#define GPIO_Remap_TIM4            ((u32)0x00001000)  /* TIM4 Alternate Function mapping */
+#define GPIO_Remap1_CAN            ((u32)0x001D4000)  /* CAN Alternate Function mapping */
+#define GPIO_Remap2_CAN            ((u32)0x001D6000)  /* CAN Alternate Function mapping */
+#define GPIO_Remap_PD01            ((u32)0x00008000)  /* PD01 Alternate Function mapping */
+#define GPIO_Remap_SWJ_NoJTRST     ((u32)0x00300100)  /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
+#define GPIO_Remap_SWJ_JTAGDisable ((u32)0x00300200)  /* JTAG-DP Disabled and SW-DP Enabled */
+#define GPIO_Remap_SWJ_Disable     ((u32)0x00300400)  /* Full SWJ Disabled (JTAG-DP + SW-DP) */
+
+#define IS_GPIO_REMAP(REMAP) ((REMAP == GPIO_Remap_SPI1) || (REMAP == GPIO_Remap_I2C1) || \
+                              (REMAP == GPIO_Remap_USART1) || (REMAP == GPIO_Remap_USART2) || \
+                              (REMAP == GPIO_PartialRemap_USART3) || (REMAP == GPIO_FullRemap_USART3) || \
+                              (REMAP == GPIO_PartialRemap_TIM1) || (REMAP == GPIO_FullRemap_TIM1) || \
+                              (REMAP == GPIO_PartialRemap1_TIM2) || (REMAP == GPIO_PartialRemap2_TIM2) || \
+                              (REMAP == GPIO_FullRemap_TIM2) || (REMAP == GPIO_PartialRemap_TIM3) || \
+                              (REMAP == GPIO_FullRemap_TIM3) || (REMAP == GPIO_Remap_TIM4) || \
+                              (REMAP == GPIO_Remap1_CAN) || (REMAP == GPIO_Remap2_CAN) || \
+                              (REMAP == GPIO_Remap_PD01) || (REMAP == GPIO_Remap_SWJ_NoJTRST) || \
+                              (REMAP == GPIO_Remap_SWJ_JTAGDisable) || (REMAP == GPIO_Remap_SWJ_Disable))
+
+/* GPIO Port Sources ---------------------------------------------------------*/
+#define GPIO_PortSourceGPIOA       ((u8)0x00)
+#define GPIO_PortSourceGPIOB       ((u8)0x01)
+#define GPIO_PortSourceGPIOC       ((u8)0x02)
+#define GPIO_PortSourceGPIOD       ((u8)0x03)
+#define GPIO_PortSourceGPIOE       ((u8)0x04)
+
+#define IS_GPIO_PORT_SOURCE(PORTSOURCE) ((PORTSOURCE == GPIO_PortSourceGPIOA) || \
+                                         (PORTSOURCE == GPIO_PortSourceGPIOB) || \
+                                         (PORTSOURCE == GPIO_PortSourceGPIOC) || \
+                                         (PORTSOURCE == GPIO_PortSourceGPIOD) || \
+                                         (PORTSOURCE == GPIO_PortSourceGPIOE))
+
+/* GPIO Pin sources ----------------------------------------------------------*/
+#define GPIO_PinSource0            ((u8)0x00)
+#define GPIO_PinSource1            ((u8)0x01)
+#define GPIO_PinSource2            ((u8)0x02)
+#define GPIO_PinSource3            ((u8)0x03)
+#define GPIO_PinSource4            ((u8)0x04)
+#define GPIO_PinSource5            ((u8)0x05)
+#define GPIO_PinSource6            ((u8)0x06)
+#define GPIO_PinSource7            ((u8)0x07)
+#define GPIO_PinSource8            ((u8)0x08)
+#define GPIO_PinSource9            ((u8)0x09)
+#define GPIO_PinSource10           ((u8)0x0A)
+#define GPIO_PinSource11           ((u8)0x0B)
+#define GPIO_PinSource12           ((u8)0x0C)
+#define GPIO_PinSource13           ((u8)0x0D)
+#define GPIO_PinSource14           ((u8)0x0E)
+#define GPIO_PinSource15           ((u8)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) ((PINSOURCE == GPIO_PinSource0) || \
+                                       (PINSOURCE == GPIO_PinSource1) || \
+                                       (PINSOURCE == GPIO_PinSource2) || \
+                                       (PINSOURCE == GPIO_PinSource3) || \
+                                       (PINSOURCE == GPIO_PinSource4) || \
+                                       (PINSOURCE == GPIO_PinSource5) || \
+                                       (PINSOURCE == GPIO_PinSource6) || \
+                                       (PINSOURCE == GPIO_PinSource7) || \
+                                       (PINSOURCE == GPIO_PinSource8) || \
+                                       (PINSOURCE == GPIO_PinSource9) || \
+                                       (PINSOURCE == GPIO_PinSource10) || \
+                                       (PINSOURCE == GPIO_PinSource11) || \
+                                       (PINSOURCE == GPIO_PinSource12) || \
+                                       (PINSOURCE == GPIO_PinSource13) || \
+                                       (PINSOURCE == GPIO_PinSource14) || \
+                                       (PINSOURCE == GPIO_PinSource15))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+void GPIO_AFIODeInit(void);
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
+u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
+u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
+void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource);
+void GPIO_EventOutputCmd(FunctionalState NewState);
+void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState);
+void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource);
+
+#endif /* __STM32F10x_GPIO_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_i2c.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_i2c.h
new file mode 100644
index 0000000..d0d000c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_i2c.h
@@ -0,0 +1,286 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_i2c.h
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file contains all the functions prototypes for the
+*                      I2C firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_I2C_H
+#define __STM32F10x_I2C_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* I2C Init structure definition */
+typedef struct
+{
+  u16 I2C_Mode;
+  u16 I2C_DutyCycle;
+  u16 I2C_OwnAddress1;
+  u16 I2C_Ack;
+  u16 I2C_AcknowledgedAddress;
+  u32 I2C_ClockSpeed;
+}I2C_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* I2C modes */
+#define I2C_Mode_I2C                    ((u16)0x0000)
+#define I2C_Mode_SMBusDevice            ((u16)0x0002)
+#define I2C_Mode_SMBusHost              ((u16)0x000A)
+
+#define IS_I2C_MODE(MODE) ((MODE == I2C_Mode_I2C) || \
+                           (MODE == I2C_Mode_SMBusDevice) || \
+                           (MODE == I2C_Mode_SMBusHost))
+/* I2C duty cycle in fast mode */
+#define I2C_DutyCycle_16_9              ((u16)0x4000)
+#define I2C_DutyCycle_2                 ((u16)0xBFFF)
+
+#define IS_I2C_DUTY_CYCLE(CYCLE) ((CYCLE == I2C_DutyCycle_16_9) || \
+                                  (CYCLE == I2C_DutyCycle_2))
+
+/* I2C cknowledgementy */
+#define I2C_Ack_Enable                  ((u16)0x0400)
+#define I2C_Ack_Disable                 ((u16)0x0000)
+
+#define IS_I2C_ACK_STATE(STATE) ((STATE == I2C_Ack_Enable) || \
+                                 (STATE == I2C_Ack_Disable))
+
+/* I2C transfer direction */
+#define  I2C_Direction_Transmitter      ((u8)0x00)
+#define  I2C_Direction_Receiver         ((u8)0x01)
+
+#define IS_I2C_DIRECTION(DIRECTION) ((DIRECTION == I2C_Direction_Transmitter) || \
+                                     (DIRECTION == I2C_Direction_Receiver))
+
+/* I2C acknowledged address defines */
+#define I2C_AcknowledgedAddress_7bit    ((u16)0x4000)
+#define I2C_AcknowledgedAddress_10bit   ((u16)0xC000)
+
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) ((ADDRESS == I2C_AcknowledgedAddress_7bit) || \
+                                             (ADDRESS == I2C_AcknowledgedAddress_10bit))
+
+/* I2C registers */
+#define I2C_Register_CR1                ((u8)0x00)
+#define I2C_Register_CR2                ((u8)0x04)
+#define I2C_Register_OAR1               ((u8)0x08)
+#define I2C_Register_OAR2               ((u8)0x0C)
+#define I2C_Register_DR                 ((u8)0x10)
+#define I2C_Register_SR1                ((u8)0x14)
+#define I2C_Register_SR2                ((u8)0x18)
+#define I2C_Register_CCR                ((u8)0x1C)
+#define I2C_Register_TRISE              ((u8)0x20)
+
+#define IS_I2C_REGISTER(REGISTER) ((REGISTER == I2C_Register_CR1) || \
+                                   (REGISTER == I2C_Register_CR2) || \
+                                   (REGISTER == I2C_Register_OAR1) || \
+                                   (REGISTER == I2C_Register_OAR2) || \
+                                   (REGISTER == I2C_Register_DR) || \
+                                   (REGISTER == I2C_Register_SR1) || \
+                                   (REGISTER == I2C_Register_SR2) || \
+                                   (REGISTER == I2C_Register_CCR) || \
+                                   (REGISTER == I2C_Register_TRISE))
+
+/* I2C SMBus alert pin level */
+#define I2C_SMBusAlert_Low              ((u16)0x2000)
+#define I2C_SMBusAlert_High             ((u16)0xCFFF)
+
+#define IS_I2C_SMBUS_ALERT(ALERT) ((ALERT == I2C_SMBusAlert_Low) || \
+                                   (ALERT == I2C_SMBusAlert_High))
+
+/* I2C PEC position */
+#define I2C_PECPosition_Next            ((u16)0x0800)
+#define I2C_PECPosition_Current         ((u16)0xF7FF)
+
+#define IS_I2C_PEC_POSITION(POSITION) ((POSITION == I2C_PECPosition_Next) || \
+                                       (POSITION == I2C_PECPosition_Current))
+
+/* I2C interrupts definition */
+#define I2C_IT_BUF                      ((u16)0x0400)
+#define I2C_IT_EVT                      ((u16)0x0200)
+#define I2C_IT_ERR                      ((u16)0x0100)
+
+#define IS_I2C_CONFIG_IT(IT) (((IT & (u16)0xF8FF) == 0x00) && (IT != 0x00))
+
+/* I2C interrupts definition */
+#define I2C_IT_SMBALERT                 ((u32)0x10008000)
+#define I2C_IT_TIMEOUT                  ((u32)0x10004000)
+#define I2C_IT_PECERR                   ((u32)0x10001000)
+#define I2C_IT_OVR                      ((u32)0x10000800)
+#define I2C_IT_AF                       ((u32)0x10000400)
+#define I2C_IT_ARLO                     ((u32)0x10000200)
+#define I2C_IT_BERR                     ((u32)0x10000100)
+#define I2C_IT_TXE                      ((u32)0x00000080)
+#define I2C_IT_RXNE                     ((u32)0x00000040)
+#define I2C_IT_STOPF                    ((u32)0x60000010)
+#define I2C_IT_ADD10                    ((u32)0x20000008)
+#define I2C_IT_BTF                      ((u32)0x60000004)
+#define I2C_IT_ADDR                     ((u32)0xA0000002)
+#define I2C_IT_SB                       ((u32)0x20000001)
+
+#define IS_I2C_CLEAR_IT(IT) ((IT == I2C_IT_SMBALERT) || (IT == I2C_IT_TIMEOUT) || \
+                             (IT == I2C_IT_PECERR) || (IT == I2C_IT_OVR) || \
+                             (IT == I2C_IT_AF) || (IT == I2C_IT_ARLO) || \
+                             (IT == I2C_IT_BERR) || (IT == I2C_IT_STOPF) || \
+                             (IT == I2C_IT_ADD10) || (IT == I2C_IT_BTF) || \
+                             (IT == I2C_IT_ADDR) || (IT == I2C_IT_SB))
+
+#define IS_I2C_GET_IT(IT) ((IT == I2C_IT_SMBALERT) || (IT == I2C_IT_TIMEOUT) || \
+                           (IT == I2C_IT_PECERR) || (IT == I2C_IT_OVR) || \
+                           (IT == I2C_IT_AF) || (IT == I2C_IT_ARLO) || \
+                           (IT == I2C_IT_BERR) || (IT == I2C_IT_TXE) || \
+                           (IT == I2C_IT_RXNE) || (IT == I2C_IT_STOPF) || \
+                           (IT == I2C_IT_ADD10) || (IT == I2C_IT_BTF) || \
+                           (IT == I2C_IT_ADDR) || (IT == I2C_IT_SB))
+
+/* I2C flags definition */
+#define I2C_FLAG_DUALF                  ((u32)0x00800000)
+#define I2C_FLAG_SMBHOST                ((u32)0x00400000)
+#define I2C_FLAG_SMBDEFAULT             ((u32)0x00200000)
+#define I2C_FLAG_GENCALL                ((u32)0x00100000)
+#define I2C_FLAG_TRA                    ((u32)0x00040000)
+#define I2C_FLAG_BUSY                   ((u32)0x00020000)
+#define I2C_FLAG_MSL                    ((u32)0x00010000)
+#define I2C_FLAG_SMBALERT               ((u32)0x10008000)
+#define I2C_FLAG_TIMEOUT                ((u32)0x10004000)
+#define I2C_FLAG_PECERR                 ((u32)0x10001000)
+#define I2C_FLAG_OVR                    ((u32)0x10000800)
+#define I2C_FLAG_AF                     ((u32)0x10000400)
+#define I2C_FLAG_ARLO                   ((u32)0x10000200)
+#define I2C_FLAG_BERR                   ((u32)0x10000100)
+#define I2C_FLAG_TXE                    ((u32)0x00000080)
+#define I2C_FLAG_RXNE                   ((u32)0x00000040)
+#define I2C_FLAG_STOPF                  ((u32)0x60000010)
+#define I2C_FLAG_ADD10                  ((u32)0x20000008)
+#define I2C_FLAG_BTF                    ((u32)0x60000004)
+#define I2C_FLAG_ADDR                   ((u32)0xA0000002)
+#define I2C_FLAG_SB                     ((u32)0x20000001)
+
+#define IS_I2C_CLEAR_FLAG(FLAG) ((FLAG == I2C_FLAG_SMBALERT) || (FLAG == I2C_FLAG_TIMEOUT) || \
+                                 (FLAG == I2C_FLAG_PECERR) || (FLAG == I2C_FLAG_OVR) || \
+                                 (FLAG == I2C_FLAG_AF) || (FLAG == I2C_FLAG_ARLO) || \
+                                 (FLAG == I2C_FLAG_BERR) || (FLAG == I2C_FLAG_STOPF) || \
+                                 (FLAG == I2C_FLAG_ADD10) || (FLAG == I2C_FLAG_BTF) || \
+                                 (FLAG == I2C_FLAG_ADDR) || (FLAG == I2C_FLAG_SB))
+
+#define IS_I2C_GET_FLAG(FLAG) ((FLAG == I2C_FLAG_DUALF) || (FLAG == I2C_FLAG_SMBHOST) || \
+                               (FLAG == I2C_FLAG_SMBDEFAULT) || (FLAG == I2C_FLAG_GENCALL) || \
+                               (FLAG == I2C_FLAG_TRA) || (FLAG == I2C_FLAG_BUSY) || \
+                               (FLAG == I2C_FLAG_MSL) || (FLAG == I2C_FLAG_SMBALERT) || \
+                               (FLAG == I2C_FLAG_TIMEOUT) || (FLAG == I2C_FLAG_PECERR) || \
+							   (FLAG == I2C_FLAG_OVR) || (FLAG == I2C_FLAG_AF) || \
+							   (FLAG == I2C_FLAG_ARLO) || (FLAG == I2C_FLAG_BERR) || \
+							   (FLAG == I2C_FLAG_TXE) || (FLAG == I2C_FLAG_RXNE) || \
+							   (FLAG == I2C_FLAG_STOPF) || (FLAG == I2C_FLAG_ADD10) || \
+							   (FLAG == I2C_FLAG_BTF) || (FLAG == I2C_FLAG_ADDR) || \
+							   (FLAG == I2C_FLAG_SB))
+
+/* I2C Events */
+/* EV1 */
+#define  I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((u32)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+#define  I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED  ((u32)0x00020002) /* BUSY and ADDR flags */
+#define  I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((u32)0x00860080)  /* DUALF, TRA, BUSY and TXE flags */
+#define  I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((u32)0x00820000)  /* DUALF and BUSY flags */
+#define  I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((u32)0x00120000)  /* GENCALL and BUSY flags */
+
+/* EV2 */
+#define  I2C_EVENT_SLAVE_BYTE_RECEIVED  ((u32)0x00020040)  /* BUSY and RXNE flags */
+     
+/* EV3 */
+#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTED  ((u32)0x00060084)  /* TRA, BUSY, TXE and BTF flags */
+
+/* EV4 */
+#define  I2C_EVENT_SLAVE_STOP_DETECTED  ((u32)0x00000010)  /* STOPF flag */
+
+/* EV5 */
+#define  I2C_EVENT_MASTER_MODE_SELECT  ((u32)0x00030001)  /* BUSY, MSL and SB flag */
+
+/* EV6 */
+#define  I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED  ((u32)0x00070082)  /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define  I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED  ((u32)0x00030002)  /* BUSY, MSL and ADDR flags */
+
+/* EV7 */
+#define  I2C_EVENT_MASTER_BYTE_RECEIVED  ((u32)0x00030040)  /* BUSY, MSL and RXNE flags */
+
+/* EV8 */
+#define  I2C_EVENT_MASTER_BYTE_TRANSMITTED  ((u32)0x00070084)  /* TRA, BUSY, MSL, TXE and BTF flags */
+      
+/* EV9 */
+#define  I2C_EVENT_MASTER_MODE_ADDRESS10  ((u32)0x00030008)  /* BUSY, MSL and ADD10 flags */
+                                          
+/* EV3_1 */
+#define  I2C_EVENT_SLAVE_ACK_FAILURE  ((u32)0x00000400)  /* AF flag */
+
+#define IS_I2C_EVENT(EVENT) ((EVENT == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
+                             (EVENT == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
+                             (EVENT == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
+                             (EVENT == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
+                             (EVENT == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
+                             (EVENT == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
+                             (EVENT == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
+                             (EVENT == I2C_EVENT_SLAVE_STOP_DETECTED) || \
+                             (EVENT == I2C_EVENT_MASTER_MODE_SELECT) || \
+                             (EVENT == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
+                             (EVENT == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
+                             (EVENT == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
+                             (EVENT == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
+                             (EVENT == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
+                             (EVENT == I2C_EVENT_SLAVE_ACK_FAILURE))
+
+/* I2C own address1 -----------------------------------------------------------*/
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (ADDRESS1 <= 0x3FF)
+/* I2C clock speed ------------------------------------------------------------*/
+#define IS_I2C_CLOCK_SPEED(SPEED) ((SPEED >= 0x1) && (SPEED <= 400000))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, u8 Address);
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, u16 I2C_IT, FunctionalState NewState);
+void I2C_SendData(I2C_TypeDef* I2Cx, u8 Data);
+u8 I2C_ReceiveData(I2C_TypeDef* I2Cx);
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 I2C_Direction);
+u16 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register);
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, u16 I2C_SMBusAlert);
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx);
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, u16 I2C_PECPosition);
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+u8 I2C_GetPEC(I2C_TypeDef* I2Cx);
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, u16 I2C_DutyCycle);
+u32 I2C_GetLastEvent(I2C_TypeDef* I2Cx);
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, u32 I2C_EVENT);
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u32 I2C_FLAG);
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, u32 I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, u32 I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, u32 I2C_IT);
+
+#endif /*__STM32F10x_I2C_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_it.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_it.h
new file mode 100644
index 0000000..90ed398
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_it.h
@@ -0,0 +1,86 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_it.h
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file contains the headers of the interrupt handlers.
+********************************************************************************
+* History:
+* mm/dd/yyyy: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IT_H
+#define __STM32F10x_IT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_lib.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMIException(void);
+void HardFaultException(void);
+void MemManageException(void);
+void BusFaultException(void);
+void UsageFaultException(void);
+void DebugMonitor(void);
+void SVCHandler(void);
+void PendSVC(void);
+void SysTickHandler(void);
+void WWDG_IRQHandler(void);
+void PVD_IRQHandler(void);
+void TAMPER_IRQHandler(void);
+void RTC_IRQHandler(void);
+void FLASH_IRQHandler(void);
+void RCC_IRQHandler(void);
+void EXTI0_IRQHandler(void);
+void EXTI1_IRQHandler(void);
+void EXTI2_IRQHandler(void);
+void EXTI3_IRQHandler(void);
+void EXTI4_IRQHandler(void);
+void DMAChannel1_IRQHandler(void);
+void DMAChannel2_IRQHandler(void);
+void DMAChannel3_IRQHandler(void);
+void DMAChannel4_IRQHandler(void);
+void DMAChannel5_IRQHandler(void);
+void DMAChannel6_IRQHandler(void);
+void DMAChannel7_IRQHandler(void);
+void ADC_IRQHandler(void);
+void USB_HP_CAN_TX_IRQHandler(void);
+void USB_LP_CAN_RX0_IRQHandler(void);
+void CAN_RX1_IRQHandler(void);
+void CAN_SCE_IRQHandler(void);
+void EXTI9_5_IRQHandler(void);
+void TIM1_BRK_IRQHandler(void);
+void TIM1_UP_IRQHandler(void);
+void TIM1_TRG_COM_IRQHandler(void);
+void TIM1_CC_IRQHandler(void);
+void TIM2_IRQHandler(void);
+void TIM3_IRQHandler(void);
+void TIM4_IRQHandler(void);
+void I2C1_EV_IRQHandler(void);
+void I2C1_ER_IRQHandler(void);
+void I2C2_EV_IRQHandler(void);
+void I2C2_ER_IRQHandler(void);
+void SPI1_IRQHandler(void);
+void SPI2_IRQHandler(void);
+void USART1_IRQHandler(void);
+void USART2_IRQHandler(void);
+void USART3_IRQHandler(void);
+void EXTI15_10_IRQHandler(void);
+void RTCAlarm_IRQHandler(void);
+void USBWakeUp_IRQHandler(void);
+					 
+#endif /* __STM32F10x_IT_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_iwdg.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_iwdg.h
new file mode 100644
index 0000000..7cfc6ed
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_iwdg.h
@@ -0,0 +1,73 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_iwdg.h
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file contains all the functions prototypes for the
+*                      IWDG firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IWDG_H
+#define __STM32F10x_IWDG_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Write access to IWDG_PR and IWDG_RLR registers */
+#define IWDG_WriteAccess_Enable     ((u16)0x5555)
+#define IWDG_WriteAccess_Disable    ((u16)0x0000)
+
+#define IS_IWDG_WRITE_ACCESS(ACCESS) ((ACCESS == IWDG_WriteAccess_Enable) || \
+                                      (ACCESS == IWDG_WriteAccess_Disable))
+
+/* IWDG prescaler */
+#define IWDG_Prescaler_4            ((u8)0x00)
+#define IWDG_Prescaler_8            ((u8)0x01)
+#define IWDG_Prescaler_16           ((u8)0x02)
+#define IWDG_Prescaler_32           ((u8)0x03)
+#define IWDG_Prescaler_64           ((u8)0x04)
+#define IWDG_Prescaler_128          ((u8)0x05)
+#define IWDG_Prescaler_256          ((u8)0x06)
+
+#define IS_IWDG_PRESCALER(PRESCALER) ((PRESCALER == IWDG_Prescaler_4)  || \
+                                      (PRESCALER == IWDG_Prescaler_8)  || \
+                                      (PRESCALER == IWDG_Prescaler_16) || \
+                                      (PRESCALER == IWDG_Prescaler_32) || \
+                                      (PRESCALER == IWDG_Prescaler_64) || \
+                                      (PRESCALER == IWDG_Prescaler_128)|| \
+                                      (PRESCALER == IWDG_Prescaler_256))
+
+/* IWDG Flag */
+#define IWDG_FLAG_PVU               ((u16)0x0001)
+#define IWDG_FLAG_RVU               ((u16)0x0002)
+
+#define IS_IWDG_FLAG(FLAG) ((FLAG == IWDG_FLAG_PVU) || (FLAG == IWDG_FLAG_RVU))
+
+#define IS_IWDG_RELOAD(RELOAD) (RELOAD <= 0xFFF)
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void IWDG_WriteAccessCmd(u16 IWDG_WriteAccess);
+void IWDG_SetPrescaler(u8 IWDG_Prescaler);
+void IWDG_SetReload(u16 Reload);
+void IWDG_ReloadCounter(void);
+void IWDG_Enable(void);
+FlagStatus IWDG_GetFlagStatus(u16 IWDG_FLAG);
+
+#endif /* __STM32F10x_IWDG_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_lib.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_lib.h
new file mode 100644
index 0000000..26d4e41
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_lib.h
@@ -0,0 +1,112 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_lib.h
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file includes the peripherals header files in the
+*                      user application.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_LIB_H
+#define __STM32F10x_LIB_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+#ifdef _ADC
+  #include "stm32f10x_adc.h"
+#endif /*_ADC */
+
+#ifdef _BKP
+  #include "stm32f10x_bkp.h"
+#endif /*_BKP */
+
+#ifdef _CAN
+  #include "stm32f10x_can.h"
+#endif /*_CAN */
+
+#ifdef _DMA
+  #include "stm32f10x_dma.h"
+#endif /*_DMA */
+
+#ifdef _EXTI
+  #include "stm32f10x_exti.h"
+#endif /*_EXTI */
+
+#ifdef _FLASH
+  #include "stm32f10x_flash.h"
+#endif /*_FLASH */
+
+#ifdef _GPIO
+  #include "stm32f10x_gpio.h"
+#endif /*_GPIO */
+
+#ifdef _I2C
+  #include "stm32f10x_i2c.h"
+#endif /*_I2C */
+
+#ifdef _IWDG
+  #include "stm32f10x_iwdg.h"
+#endif /*_IWDG */
+
+#ifdef _NVIC
+  #include "stm32f10x_nvic.h"
+#endif /*_NVIC */
+
+#ifdef _PWR
+  #include "stm32f10x_pwr.h"
+#endif /*_PWR */
+
+#ifdef _RCC
+  #include "stm32f10x_rcc.h"
+#endif /*_RCC */
+
+#ifdef _RTC
+  #include "stm32f10x_rtc.h"
+#endif /*_RTC */
+
+#ifdef _SPI
+  #include "stm32f10x_spi.h"
+#endif /*_SPI */
+
+#ifdef _SysTick
+  #include "stm32f10x_systick.h"
+#endif /*_SysTick */
+
+#ifdef _TIM1
+  #include "stm32f10x_tim1.h"
+#endif /*_TIM1 */
+
+#ifdef _TIM
+  #include "stm32f10x_tim.h"
+#endif /*_TIM */
+
+#ifdef _USART
+  #include "stm32f10x_usart.h"
+#endif /*_USART */
+
+#ifdef _WWDG
+  #include "stm32f10x_wwdg.h"
+#endif /*_WWDG */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void debug(void);
+
+#endif /* __STM32F10x_LIB_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_map.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_map.h
new file mode 100644
index 0000000..f14f87a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_map.h
@@ -0,0 +1,870 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_map.h
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file contains all the peripheral register's definitions
+*                      and memory mapping.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_MAP_H
+#define __STM32F10x_MAP_H
+
+#ifndef EXT
+  #define EXT extern
+#endif /* EXT */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_conf.h"
+#include "stm32f10x_type.h"
+#include "cortexm3_macro.h"
+
+/* Exported types ------------------------------------------------------------*/
+/******************************************************************************/
+/*                          IP registers structures                           */
+/******************************************************************************/
+
+/*------------------------ Analog to Digital Converter -----------------------*/
+typedef struct
+{
+  vu32 SR;
+  vu32 CR1;
+  vu32 CR2;
+  vu32 SMPR1;
+  vu32 SMPR2;
+  vu32 JOFR1;
+  vu32 JOFR2;
+  vu32 JOFR3;
+  vu32 JOFR4;
+  vu32 HTR;
+  vu32 LTR;
+  vu32 SQR1;
+  vu32 SQR2;
+  vu32 SQR3;
+  vu32 JSQR;
+  vu32 JDR1;
+  vu32 JDR2;
+  vu32 JDR3;
+  vu32 JDR4;
+  vu32 DR;
+} ADC_TypeDef;
+
+/*------------------------ Backup Registers ----------------------------------*/
+typedef struct
+{
+  u32 RESERVED0;
+  vu16 DR1;
+  u16  RESERVED1;
+  vu16 DR2;
+  u16  RESERVED2;
+  vu16 DR3;
+  u16  RESERVED3;
+  vu16 DR4;
+  u16  RESERVED4;
+  vu16 DR5;
+  u16  RESERVED5;
+  vu16 DR6;
+  u16  RESERVED6;
+  vu16 DR7;
+  u16  RESERVED7;
+  vu16 DR8;
+  u16  RESERVED8;
+  vu16 DR9;
+  u16  RESERVED9;
+  vu16 DR10;
+  u16  RESERVED10;
+  vu16 RTCCR;
+  u16  RESERVED11;
+  vu16 CR;
+  u16  RESERVED12;
+  vu16 CSR;
+  u16  RESERVED13;
+} BKP_TypeDef;
+
+/*------------------------ Controller Area Network ---------------------------*/
+typedef struct
+{
+  vu32 TIR;
+  vu32 TDTR;
+  vu32 TDLR;
+  vu32 TDHR;
+} CAN_TxMailBox_TypeDef;
+
+typedef struct
+{
+  vu32 RIR;
+  vu32 RDTR;
+  vu32 RDLR;
+  vu32 RDHR;
+} CAN_FIFOMailBox_TypeDef;
+
+typedef struct
+{
+  vu32 FR0;
+  vu32 FR1;
+} CAN_FilterRegister_TypeDef;
+
+typedef struct
+{
+  vu32 MCR;
+  vu32 MSR;
+  vu32 TSR;
+  vu32 RF0R;
+  vu32 RF1R;
+  vu32 IER;
+  vu32 ESR;
+  vu32 BTR;
+  u32 RESERVED0[88];
+  CAN_TxMailBox_TypeDef sTxMailBox[3];
+  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
+  u32 RESERVED1[12];
+  vu32 FMR;
+  vu32 FM0R;
+  u32 RESERVED2[1];
+  vu32 FS0R;
+  u32 RESERVED3[1];
+  vu32 FFA0R;
+  u32 RESERVED4[1];
+  vu32 FA0R;
+  u32 RESERVED5[8];
+  CAN_FilterRegister_TypeDef sFilterRegister[14];
+} CAN_TypeDef;
+
+/*------------------------ DMA Controller ------------------------------------*/
+typedef struct
+{
+  vu32 CCR;
+  vu32 CNDTR;
+  vu32 CPAR;
+  vu32 CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  vu32 ISR;
+  vu32 IFCR;
+} DMA_TypeDef;
+
+/*------------------------ External Interrupt/Event Controller ---------------*/
+typedef struct
+{
+  vu32 IMR;
+  vu32 EMR;
+  vu32 RTSR;
+  vu32 FTSR;
+  vu32 SWIER;
+  vu32 PR;
+} EXTI_TypeDef;
+
+/*------------------------ FLASH and Option Bytes Registers ------------------*/
+typedef struct
+{
+  vu32 ACR;
+  vu32 KEYR;
+  vu32 OPTKEYR;
+  vu32 SR;
+  vu32 CR;
+  vu32 AR;
+  vu32 RESERVED;
+  vu32 OBR;
+  vu32 WRPR;
+} FLASH_TypeDef;
+
+typedef struct
+{
+  vu16 RDP;
+  vu16 USER;
+  vu16 Data0;
+  vu16 Data1;
+  vu16 WRP0;
+  vu16 WRP1;
+  vu16 WRP2;
+  vu16 WRP3;
+} OB_TypeDef;
+
+/*------------------------ General Purpose and Alternate Function IO ---------*/
+typedef struct
+{
+  vu32 CRL;
+  vu32 CRH;
+  vu32 IDR;
+  vu32 ODR;
+  vu32 BSRR;
+  vu32 BRR;
+  vu32 LCKR;
+} GPIO_TypeDef;
+
+typedef struct
+{
+  vu32 EVCR;
+  vu32 MAPR;
+  vu32 EXTICR[4];
+} AFIO_TypeDef;
+
+/*------------------------ Inter-integrated Circuit Interface ----------------*/
+typedef struct
+{
+  vu16 CR1;
+  u16 RESERVED0;
+  vu16 CR2;
+  u16 RESERVED1;
+  vu16 OAR1;
+  u16 RESERVED2;
+  vu16 OAR2;
+  u16 RESERVED3;
+  vu16 DR;
+  u16 RESERVED4;
+  vu16 SR1;
+  u16 RESERVED5;
+  vu16 SR2;
+  u16 RESERVED6;
+  vu16 CCR;
+  u16 RESERVED7;
+  vu16 TRISE;
+  u16 RESERVED8;
+} I2C_TypeDef;
+
+/*------------------------ Independent WATCHDOG ------------------------------*/
+typedef struct
+{
+  vu32 KR;
+  vu32 PR;
+  vu32 RLR;
+  vu32 SR;
+} IWDG_TypeDef;
+
+/*------------------------ Nested Vectored Interrupt Controller --------------*/
+typedef struct
+{
+  vu32 Enable[2];
+  u32 RESERVED0[30];
+  vu32 Disable[2];
+  u32 RSERVED1[30];
+  vu32 Set[2];
+  u32 RESERVED2[30];
+  vu32 Clear[2];
+  u32 RESERVED3[30];
+  vu32 Active[2];
+  u32 RESERVED4[62];
+  vu32 Priority[11];
+} NVIC_TypeDef;
+
+typedef struct
+{
+  vu32 CPUID;
+  vu32 IRQControlState;
+  vu32 ExceptionTableOffset;
+  vu32 AIRC;
+  vu32 SysCtrl;
+  vu32 ConfigCtrl;
+  vu32 SystemPriority[3];
+  vu32 SysHandlerCtrl;
+  vu32 ConfigFaultStatus;
+  vu32 HardFaultStatus;
+  vu32 DebugFaultStatus;
+  vu32 MemoryManageFaultAddr;
+  vu32 BusFaultAddr;
+} SCB_TypeDef;
+
+/*------------------------ Power Controller ----------------------------------*/
+typedef struct
+{
+  vu32 CR;
+  vu32 CSR;
+} PWR_TypeDef;
+
+/*------------------------ Reset and Clock Controller ------------------------*/
+typedef struct
+{
+  vu32 CR;
+  vu32 CFGR;
+  vu32 CIR;
+  vu32 APB2RSTR;
+  vu32 APB1RSTR;
+  vu32 AHBENR;
+  vu32 APB2ENR;
+  vu32 APB1ENR;
+  vu32 BDCR;
+  vu32 CSR;
+} RCC_TypeDef;
+
+/*------------------------ Real-Time Clock -----------------------------------*/
+typedef struct
+{
+  vu16 CRH;
+  u16 RESERVED0;
+  vu16 CRL;
+  u16 RESERVED1;
+  vu16 PRLH;
+  u16 RESERVED2;
+  vu16 PRLL;
+  u16 RESERVED3;
+  vu16 DIVH;
+  u16 RESERVED4;
+  vu16 DIVL;
+  u16 RESERVED5;
+  vu16 CNTH;
+  u16 RESERVED6;
+  vu16 CNTL;
+  u16 RESERVED7;
+  vu16 ALRH;
+  u16 RESERVED8;
+  vu16 ALRL;
+  u16 RESERVED9;
+} RTC_TypeDef;
+
+/*------------------------ Serial Peripheral Interface -----------------------*/
+typedef struct
+{
+  vu16 CR1;
+  u16 RESERVED0;
+  vu16 CR2;
+  u16 RESERVED1;
+  vu16 SR;
+  u16  RESERVED2;
+  vu16 DR;
+  u16  RESERVED3;
+  vu16 CRCPR;
+  u16 RESERVED4;
+  vu16 RXCRCR;
+  u16  RESERVED5;
+  vu16 TXCRCR;
+  u16  RESERVED6;
+  vu16 I2SCFGR;
+  u16  RESERVED7;
+  vu16 I2SPR;
+  u16 RESERVED8;
+
+} SPI_TypeDef;
+
+/*------------------------ SystemTick ----------------------------------------*/
+typedef struct
+{
+  vu32 CTRL;
+  vu32 LOAD;
+  vu32 VAL;
+  vuc32 CALIB;
+} SysTick_TypeDef;
+
+/*------------------------ Advanced Control Timer ----------------------------*/
+typedef struct
+{
+  vu16 CR1;
+  u16 RESERVED0;
+  vu16 CR2;
+  u16 RESERVED1;
+  vu16 SMCR;
+  u16 RESERVED2;
+  vu16 DIER;
+  u16 RESERVED3;
+  vu16 SR;
+  u16 RESERVED4;
+  vu16 EGR;
+  u16 RESERVED5;
+  vu16 CCMR1;
+  u16 RESERVED6;
+  vu16 CCMR2;
+  u16 RESERVED7;
+  vu16 CCER;
+  u16 RESERVED8;
+  vu16 CNT;
+  u16 RESERVED9;
+  vu16 PSC;
+  u16 RESERVED10;
+  vu16 ARR;
+  u16 RESERVED11;
+  vu16 RCR;
+  u16 RESERVED12;
+  vu16 CCR1;
+  u16 RESERVED13;
+  vu16 CCR2;
+  u16 RESERVED14;
+  vu16 CCR3;
+  u16 RESERVED15;
+  vu16 CCR4;
+  u16 RESERVED16;
+  vu16 BDTR;
+  u16 RESERVED17;
+  vu16 DCR;
+  u16 RESERVED18;
+  vu16 DMAR;
+  u16 RESERVED19;
+} TIM1_TypeDef;
+
+/*------------------------ General Purpose Timer -----------------------------*/
+typedef struct
+{
+  vu16 CR1;
+  u16 RESERVED0;
+  vu16 CR2;
+  u16 RESERVED1;
+  vu16 SMCR;
+  u16 RESERVED2;
+  vu16 DIER;
+  u16 RESERVED3;
+  vu16 SR;
+  u16 RESERVED4;
+  vu16 EGR;
+  u16 RESERVED5;
+  vu16 CCMR1;
+  u16 RESERVED6;
+  vu16 CCMR2;
+  u16 RESERVED7;
+  vu16 CCER;
+  u16 RESERVED8;
+  vu16 CNT;
+  u16 RESERVED9;
+  vu16 PSC;
+  u16 RESERVED10;
+  vu16 ARR;
+  u16 RESERVED11[3];
+  vu16 CCR1;
+  u16 RESERVED12;
+  vu16 CCR2;
+  u16 RESERVED13;
+  vu16 CCR3;
+  u16 RESERVED14;
+  vu16 CCR4;
+  u16 RESERVED15[3];
+  vu16 DCR;
+  u16 RESERVED16;
+  vu16 DMAR;
+  u16 RESERVED17;
+} TIM_TypeDef;
+
+/*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/
+typedef struct
+{
+  vu16 SR;
+  u16 RESERVED0;
+  vu16 DR;
+  u16 RESERVED1;
+  vu16 BRR;
+  u16 RESERVED2;
+  vu16 CR1;
+  u16 RESERVED3;
+  vu16 CR2;
+  u16 RESERVED4;
+  vu16 CR3;
+  u16 RESERVED5;
+  vu16 GTPR;
+  u16 RESERVED6;
+} USART_TypeDef;
+
+/*------------------------ Window WATCHDOG -----------------------------------*/
+typedef struct
+{
+  vu32 CR;
+  vu32 CFR;
+  vu32 SR;
+} WWDG_TypeDef;
+
+/******************************************************************************/
+/*                       Peripheral memory map                                */
+/******************************************************************************/
+/* Peripheral and SRAM base address in the alias region */
+#define PERIPH_BB_BASE        ((u32)0x42000000)
+#define SRAM_BB_BASE          ((u32)0x22000000)
+
+/* Peripheral and SRAM base address in the bit-band region */
+#define SRAM_BASE             ((u32)0x20000000)
+#define PERIPH_BASE           ((u32)0x40000000)
+
+/* Flash refisters base address */
+#define FLASH_BASE            ((u32)0x40022000)
+/* Flash Option Bytes base address */
+#define OB_BASE               ((u32)0x1FFFF800)
+
+/* Peripheral memory map */
+#define APB1PERIPH_BASE       PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
+#define CAN_BASE              (APB1PERIPH_BASE + 0x6400)
+#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
+
+#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
+
+#define DMA_BASE              (AHBPERIPH_BASE + 0x0000)
+#define DMA_Channel1_BASE     (AHBPERIPH_BASE + 0x0008)
+#define DMA_Channel2_BASE     (AHBPERIPH_BASE + 0x001C)
+#define DMA_Channel3_BASE     (AHBPERIPH_BASE + 0x0030)
+#define DMA_Channel4_BASE     (AHBPERIPH_BASE + 0x0044)
+#define DMA_Channel5_BASE     (AHBPERIPH_BASE + 0x0058)
+#define DMA_Channel6_BASE     (AHBPERIPH_BASE + 0x006C)
+#define DMA_Channel7_BASE     (AHBPERIPH_BASE + 0x0080)
+#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)
+
+/* System Control Space memory map */
+#define SCS_BASE              ((u32)0xE000E000)
+
+#define SysTick_BASE          (SCS_BASE + 0x0010)
+#define NVIC_BASE             (SCS_BASE + 0x0100)
+#define SCB_BASE              (SCS_BASE + 0x0D00)
+
+
+/******************************************************************************/
+/*                            IPs' declaration                                */
+/******************************************************************************/
+
+/*------------------- Non Debug Mode -----------------------------------------*/
+#ifndef DEBUG
+#ifdef _TIM2
+  #define TIM2                  ((TIM_TypeDef *) TIM2_BASE)
+#endif /*_TIM2 */
+
+#ifdef _TIM3
+  #define TIM3                  ((TIM_TypeDef *) TIM3_BASE)
+#endif /*_TIM3 */
+
+#ifdef _TIM4
+  #define TIM4                  ((TIM_TypeDef *) TIM4_BASE)
+#endif /*_TIM4 */
+
+#ifdef _RTC
+  #define RTC                   ((RTC_TypeDef *) RTC_BASE)
+#endif /*_RTC */
+
+#ifdef _WWDG
+  #define WWDG                  ((WWDG_TypeDef *) WWDG_BASE)
+#endif /*_WWDG */
+
+#ifdef _IWDG
+  #define IWDG                  ((IWDG_TypeDef *) IWDG_BASE)
+#endif /*_IWDG */
+
+#ifdef _SPI2
+  #define SPI2                  ((SPI_TypeDef *) SPI2_BASE)
+#endif /*_SPI2 */
+
+#ifdef _USART2
+  #define USART2                ((USART_TypeDef *) USART2_BASE)
+#endif /*_USART2 */
+
+#ifdef _USART3
+  #define USART3                ((USART_TypeDef *) USART3_BASE)
+#endif /*_USART3 */
+
+#ifdef _I2C1
+  #define I2C1                  ((I2C_TypeDef *) I2C1_BASE)
+#endif /*_I2C1 */
+
+#ifdef _I2C2
+  #define I2C2                  ((I2C_TypeDef *) I2C2_BASE)
+#endif /*_I2C2 */
+
+#ifdef _CAN
+  #define CAN                   ((CAN_TypeDef *) CAN_BASE)
+#endif /*_CAN */
+
+#ifdef _BKP
+  #define BKP                   ((BKP_TypeDef *) BKP_BASE)
+#endif /*_BKP */
+
+#ifdef _PWR
+  #define PWR                   ((PWR_TypeDef *) PWR_BASE)
+#endif /*_PWR */
+
+#ifdef _AFIO
+  #define AFIO                  ((AFIO_TypeDef *) AFIO_BASE)
+#endif /*_AFIO */
+
+#ifdef _EXTI
+  #define EXTI                  ((EXTI_TypeDef *) EXTI_BASE)
+#endif /*_EXTI */
+
+#ifdef _GPIOA
+  #define GPIOA                 ((GPIO_TypeDef *) GPIOA_BASE)
+#endif /*_GPIOA */
+
+#ifdef _GPIOB
+  #define GPIOB                 ((GPIO_TypeDef *) GPIOB_BASE)
+#endif /*_GPIOB */
+
+#ifdef _GPIOC
+  #define GPIOC                 ((GPIO_TypeDef *) GPIOC_BASE)
+#endif /*_GPIOC */
+
+#ifdef _GPIOD
+  #define GPIOD                 ((GPIO_TypeDef *) GPIOD_BASE)
+#endif /*_GPIOD */
+
+#ifdef _GPIOE
+  #define GPIOE                 ((GPIO_TypeDef *) GPIOE_BASE)
+#endif /*_GPIOE */
+
+#ifdef _ADC1
+  #define ADC1                  ((ADC_TypeDef *) ADC1_BASE)
+#endif /*_ADC1 */
+
+#ifdef _ADC2
+  #define ADC2                  ((ADC_TypeDef *) ADC2_BASE)
+#endif /*_ADC2 */
+
+#ifdef _TIM1
+  #define TIM1                  ((TIM1_TypeDef *) TIM1_BASE)
+#endif /*_TIM1 */
+
+#ifdef _SPI1
+  #define SPI1                  ((SPI_TypeDef *) SPI1_BASE)
+#endif /*_SPI1 */
+
+#ifdef _USART1
+  #define USART1                ((USART_TypeDef *) USART1_BASE)
+#endif /*_USART1 */
+
+#ifdef _DMA
+  #define DMA                   ((DMA_TypeDef *) DMA_BASE)
+#endif /*_DMA */
+
+#ifdef _DMA_Channel1
+  #define DMA_Channel1          ((DMA_Channel_TypeDef *) DMA_Channel1_BASE)
+#endif /*_DMA_Channel1 */
+
+#ifdef _DMA_Channel2
+  #define DMA_Channel2          ((DMA_Channel_TypeDef *) DMA_Channel2_BASE)
+#endif /*_DMA_Channel2 */
+
+#ifdef _DMA_Channel3
+  #define DMA_Channel3          ((DMA_Channel_TypeDef *) DMA_Channel3_BASE)
+#endif /*_DMA_Channel3 */
+
+#ifdef _DMA_Channel4
+  #define DMA_Channel4          ((DMA_Channel_TypeDef *) DMA_Channel4_BASE)
+#endif /*_DMA_Channel4 */
+
+#ifdef _DMA_Channel5
+  #define DMA_Channel5          ((DMA_Channel_TypeDef *) DMA_Channel5_BASE)
+#endif /*_DMA_Channel5 */
+
+#ifdef _DMA_Channel6
+  #define DMA_Channel6          ((DMA_Channel_TypeDef *) DMA_Channel6_BASE)
+#endif /*_DMA_Channel6 */
+
+#ifdef _DMA_Channel7
+  #define DMA_Channel7          ((DMA_Channel_TypeDef *) DMA_Channel7_BASE)
+#endif /*_DMA_Channel7 */
+
+#ifdef _FLASH
+  #define FLASH                 ((FLASH_TypeDef *) FLASH_BASE)
+  #define OB                    ((OB_TypeDef *) OB_BASE)
+#endif /*_FLASH */
+
+#ifdef _RCC
+  #define RCC                   ((RCC_TypeDef *) RCC_BASE)
+#endif /*_RCC */
+
+#ifdef _SysTick
+  #define SysTick               ((SysTick_TypeDef *) SysTick_BASE)
+#endif /*_SysTick */
+
+#ifdef _NVIC
+  #define NVIC                  ((NVIC_TypeDef *) NVIC_BASE)
+#endif /*_NVIC */
+
+#ifdef _SCB
+  #define SCB                   ((SCB_TypeDef *) SCB_BASE)
+#endif /*_SCB */
+/*----------------------  Debug Mode -----------------------------------------*/
+#else   /* DEBUG */
+#ifdef _TIM2
+  EXT TIM_TypeDef             *TIM2;
+#endif /*_TIM2 */
+
+#ifdef _TIM3
+  EXT TIM_TypeDef             *TIM3;
+#endif /*_TIM3 */
+
+#ifdef _TIM4
+  EXT TIM_TypeDef             *TIM4;
+#endif /*_TIM4 */
+
+#ifdef _RTC
+  EXT RTC_TypeDef             *RTC;
+#endif /*_RTC */
+
+#ifdef _WWDG
+  EXT WWDG_TypeDef            *WWDG;
+#endif /*_WWDG */
+
+#ifdef _IWDG
+  EXT IWDG_TypeDef            *IWDG;
+#endif /*_IWDG */
+
+#ifdef _SPI2
+  EXT SPI_TypeDef             *SPI2;
+#endif /*_SPI2 */
+
+#ifdef _USART2
+  EXT USART_TypeDef           *USART2;
+#endif /*_USART2 */
+
+#ifdef _USART3
+  EXT USART_TypeDef           *USART3;
+#endif /*_USART3 */
+
+#ifdef _I2C1
+  EXT I2C_TypeDef             *I2C1;
+#endif /*_I2C1 */
+
+#ifdef _I2C2
+  EXT I2C_TypeDef             *I2C2;
+#endif /*_I2C2 */
+
+#ifdef _CAN
+  EXT CAN_TypeDef             *CAN;
+#endif /*_CAN */
+
+#ifdef _BKP
+  EXT BKP_TypeDef             *BKP;
+#endif /*_BKP */
+
+#ifdef _PWR
+  EXT PWR_TypeDef             *PWR;
+#endif /*_PWR */
+
+#ifdef _AFIO
+  EXT AFIO_TypeDef            *AFIO;
+#endif /*_AFIO */
+
+#ifdef _EXTI
+  EXT EXTI_TypeDef            *EXTI;
+#endif /*_EXTI */
+
+#ifdef _GPIOA
+  EXT GPIO_TypeDef            *GPIOA;
+#endif /*_GPIOA */
+
+#ifdef _GPIOB
+  EXT GPIO_TypeDef            *GPIOB;
+#endif /*_GPIOB */
+
+#ifdef _GPIOC
+  EXT GPIO_TypeDef            *GPIOC;
+#endif /*_GPIOC */
+
+#ifdef _GPIOD
+  EXT GPIO_TypeDef            *GPIOD;
+#endif /*_GPIOD */
+
+#ifdef _GPIOE
+  EXT GPIO_TypeDef            *GPIOE;
+#endif /*_GPIOE */
+
+#ifdef _ADC1
+  EXT ADC_TypeDef             *ADC1;
+#endif /*_ADC1 */
+
+#ifdef _ADC2
+  EXT ADC_TypeDef             *ADC2;
+#endif /*_ADC2 */
+
+#ifdef _TIM1
+  EXT TIM1_TypeDef            *TIM1;
+#endif /*_TIM1 */
+
+#ifdef _SPI1
+  EXT SPI_TypeDef             *SPI1;
+#endif /*_SPI1 */
+
+#ifdef _USART1
+  EXT USART_TypeDef           *USART1;
+#endif /*_USART1 */
+
+#ifdef _DMA
+  EXT DMA_TypeDef             *DMA;
+#endif /*_DMA */
+
+#ifdef _DMA_Channel1
+  EXT DMA_Channel_TypeDef     *DMA_Channel1;
+#endif /*_DMA_Channel1 */
+
+#ifdef _DMA_Channel2
+  EXT DMA_Channel_TypeDef     *DMA_Channel2;
+#endif /*_DMA_Channel2 */
+
+#ifdef _DMA_Channel3
+  EXT DMA_Channel_TypeDef     *DMA_Channel3;
+#endif /*_DMA_Channel3 */
+
+#ifdef _DMA_Channel4
+  EXT DMA_Channel_TypeDef     *DMA_Channel4;
+#endif /*_DMA_Channel4 */
+
+#ifdef _DMA_Channel5
+  EXT DMA_Channel_TypeDef     *DMA_Channel5;
+#endif /*_DMA_Channel5 */
+
+#ifdef _DMA_Channel6
+  EXT DMA_Channel_TypeDef     *DMA_Channel6;
+#endif /*_DMA_Channel6 */
+
+#ifdef _DMA_Channel7
+  EXT DMA_Channel_TypeDef     *DMA_Channel7;
+#endif /*_DMA_Channel7 */
+
+#ifdef _FLASH
+  EXT FLASH_TypeDef            *FLASH;
+  EXT OB_TypeDef               *OB;
+#endif /*_FLASH */
+
+#ifdef _RCC
+  EXT RCC_TypeDef             *RCC;
+#endif /*_RCC */
+
+#ifdef _SysTick
+  EXT SysTick_TypeDef         *SysTick;
+#endif /*_SysTick */
+
+#ifdef _NVIC
+  EXT NVIC_TypeDef            *NVIC;
+#endif /*_NVIC */
+
+#ifdef _SCB
+  EXT SCB_TypeDef             *SCB;
+#endif /*_SCB */
+
+#endif  /* DEBUG */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __STM32F10x_MAP_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_nvic.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_nvic.h
new file mode 100644
index 0000000..5cfacf8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_nvic.h
@@ -0,0 +1,255 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_nvic.h
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file contains all the functions prototypes for the
+*                      NVIC firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_NVIC_H
+#define __STM32F10x_NVIC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* NVIC Init Structure definition */
+typedef struct
+{
+  u8 NVIC_IRQChannel;
+  u8 NVIC_IRQChannelPreemptionPriority;
+  u8 NVIC_IRQChannelSubPriority;
+  FunctionalState NVIC_IRQChannelCmd;
+} NVIC_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* IRQ Channels --------------------------------------------------------------*/
+#define WWDG_IRQChannel              ((u8)0x00)  /* Window WatchDog Interrupt */
+#define PVD_IRQChannel               ((u8)0x01)  /* PVD through EXTI Line detection Interrupt */
+#define TAMPER_IRQChannel            ((u8)0x02)  /* Tamper Interrupt */
+#define RTC_IRQChannel               ((u8)0x03)  /* RTC global Interrupt */
+#define FLASH_IRQChannel             ((u8)0x04)  /* FLASH global Interrupt */
+#define RCC_IRQChannel               ((u8)0x05)  /* RCC global Interrupt */
+#define EXTI0_IRQChannel             ((u8)0x06)  /* EXTI Line0 Interrupt */
+#define EXTI1_IRQChannel             ((u8)0x07)  /* EXTI Line1 Interrupt */
+#define EXTI2_IRQChannel             ((u8)0x08)  /* EXTI Line2 Interrupt */
+#define EXTI3_IRQChannel             ((u8)0x09)  /* EXTI Line3 Interrupt */
+#define EXTI4_IRQChannel             ((u8)0x0A)  /* EXTI Line4 Interrupt */
+#define DMAChannel1_IRQChannel       ((u8)0x0B)  /* DMA Channel 1 global Interrupt */
+#define DMAChannel2_IRQChannel       ((u8)0x0C)  /* DMA Channel 2 global Interrupt */
+#define DMAChannel3_IRQChannel       ((u8)0x0D)  /* DMA Channel 3 global Interrupt */
+#define DMAChannel4_IRQChannel       ((u8)0x0E)  /* DMA Channel 4 global Interrupt */
+#define DMAChannel5_IRQChannel       ((u8)0x0F)  /* DMA Channel 5 global Interrupt */
+#define DMAChannel6_IRQChannel       ((u8)0x10)  /* DMA Channel 6 global Interrupt */
+#define DMAChannel7_IRQChannel       ((u8)0x11)  /* DMA Channel 7 global Interrupt */
+#define ADC_IRQChannel               ((u8)0x12)  /* ADC global Interrupt */
+#define USB_HP_CAN_TX_IRQChannel     ((u8)0x13)  /* USB High Priority or CAN TX Interrupts */
+#define USB_LP_CAN_RX0_IRQChannel    ((u8)0x14)  /* USB Low Priority or CAN RX0 Interrupts */
+#define CAN_RX1_IRQChannel           ((u8)0x15)  /* CAN RX1 Interrupt */
+#define CAN_SCE_IRQChannel           ((u8)0x16)  /* CAN SCE Interrupt */
+#define EXTI9_5_IRQChannel           ((u8)0x17)  /* External Line[9:5] Interrupts */
+#define TIM1_BRK_IRQChannel          ((u8)0x18)  /* TIM1 Break Interrupt */
+#define TIM1_UP_IRQChannel           ((u8)0x19)  /* TIM1 Update Interrupt */
+#define TIM1_TRG_COM_IRQChannel      ((u8)0x1A)  /* TIM1 Trigger and Commutation Interrupt */
+#define TIM1_CC_IRQChannel           ((u8)0x1B)  /* TIM1 Capture Compare Interrupt */
+#define TIM2_IRQChannel              ((u8)0x1C)  /* TIM2 global Interrupt */
+#define TIM3_IRQChannel              ((u8)0x1D)  /* TIM3 global Interrupt */
+#define TIM4_IRQChannel              ((u8)0x1E)  /* TIM4 global Interrupt */
+#define I2C1_EV_IRQChannel           ((u8)0x1F)  /* I2C1 Event Interrupt */
+#define I2C1_ER_IRQChannel           ((u8)0x20)  /* I2C1 Error Interrupt */
+#define I2C2_EV_IRQChannel           ((u8)0x21)  /* I2C2 Event Interrupt */
+#define I2C2_ER_IRQChannel           ((u8)0x22)  /* I2C2 Error Interrupt */
+#define SPI1_IRQChannel              ((u8)0x23)  /* SPI1 global Interrupt */
+#define SPI2_IRQChannel              ((u8)0x24)  /* SPI2 global Interrupt */
+#define USART1_IRQChannel            ((u8)0x25)  /* USART1 global Interrupt */
+#define USART2_IRQChannel            ((u8)0x26)  /* USART2 global Interrupt */
+#define USART3_IRQChannel            ((u8)0x27)  /* USART3 global Interrupt */
+#define EXTI15_10_IRQChannel         ((u8)0x28)  /* External Line[15:10] Interrupts */
+#define RTCAlarm_IRQChannel          ((u8)0x29)  /* RTC Alarm through EXTI Line Interrupt */
+#define USBWakeUp_IRQChannel         ((u8)0x2A)  /* USB WakeUp from suspend through EXTI Line Interrupt */
+
+#define IS_NVIC_IRQ_CHANNEL(CHANNEL) ((CHANNEL == WWDG_IRQChannel) || \
+                                      (CHANNEL == PVD_IRQChannel) || \
+                                      (CHANNEL == TAMPER_IRQChannel) || \
+                                      (CHANNEL == RTC_IRQChannel) || \
+                                      (CHANNEL == FLASH_IRQChannel) || \
+                                      (CHANNEL == RCC_IRQChannel) || \
+                                      (CHANNEL == EXTI0_IRQChannel) || \
+                                      (CHANNEL == EXTI1_IRQChannel) || \
+                                      (CHANNEL == EXTI2_IRQChannel) || \
+                                      (CHANNEL == EXTI3_IRQChannel) || \
+                                      (CHANNEL == EXTI4_IRQChannel) || \
+                                      (CHANNEL == DMAChannel1_IRQChannel) || \
+                                      (CHANNEL == DMAChannel2_IRQChannel) || \
+                                      (CHANNEL == DMAChannel3_IRQChannel) || \
+                                      (CHANNEL == DMAChannel4_IRQChannel) || \
+                                      (CHANNEL == DMAChannel5_IRQChannel) || \
+                                      (CHANNEL == DMAChannel6_IRQChannel) || \
+                                      (CHANNEL == DMAChannel7_IRQChannel) || \
+                                      (CHANNEL == ADC_IRQChannel) || \
+                                      (CHANNEL == USB_HP_CAN_TX_IRQChannel) || \
+                                      (CHANNEL == USB_LP_CAN_RX0_IRQChannel) || \
+                                      (CHANNEL == CAN_RX1_IRQChannel) || \
+                                      (CHANNEL == CAN_SCE_IRQChannel) || \
+                                      (CHANNEL == EXTI9_5_IRQChannel) || \
+                                      (CHANNEL == TIM1_BRK_IRQChannel) || \
+                                      (CHANNEL == TIM1_UP_IRQChannel) || \
+                                      (CHANNEL == TIM1_TRG_COM_IRQChannel) || \
+                                      (CHANNEL == TIM1_CC_IRQChannel) || \
+                                      (CHANNEL == TIM2_IRQChannel) || \
+                                      (CHANNEL == TIM3_IRQChannel) || \
+                                      (CHANNEL == TIM4_IRQChannel) || \
+                                      (CHANNEL == I2C1_EV_IRQChannel) || \
+                                      (CHANNEL == I2C1_ER_IRQChannel) || \
+                                      (CHANNEL == I2C2_EV_IRQChannel) || \
+                                      (CHANNEL == I2C2_ER_IRQChannel) || \
+                                      (CHANNEL == SPI1_IRQChannel) || \
+                                      (CHANNEL == SPI2_IRQChannel) || \
+                                      (CHANNEL == USART1_IRQChannel) || \
+                                      (CHANNEL == USART2_IRQChannel) || \
+                                      (CHANNEL == USART3_IRQChannel) || \
+                                      (CHANNEL == EXTI15_10_IRQChannel) || \
+                                      (CHANNEL == RTCAlarm_IRQChannel) || \
+                                      (CHANNEL == USBWakeUp_IRQChannel))
+
+/* System Handlers -----------------------------------------------------------*/
+#define SystemHandler_NMI            ((u32)0x00001F) /* NMI Handler */
+#define SystemHandler_HardFault      ((u32)0x000000) /* Hard Fault Handler */
+#define SystemHandler_MemoryManage   ((u32)0x043430) /* Memory Manage Handler */
+#define SystemHandler_BusFault       ((u32)0x547931) /* Bus Fault Handler */
+#define SystemHandler_UsageFault     ((u32)0x24C232) /* Usage Fault Handler */
+#define SystemHandler_SVCall         ((u32)0x01FF40) /* SVCall Handler */
+#define SystemHandler_DebugMonitor   ((u32)0x0A0080) /* Debug Monitor Handler */
+#define SystemHandler_PSV            ((u32)0x02829C) /* PSV Handler */
+#define SystemHandler_SysTick        ((u32)0x02C39A) /* SysTick Handler */
+
+#define IS_CONFIG_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
+                                           (HANDLER == SystemHandler_BusFault) || \
+                                           (HANDLER == SystemHandler_UsageFault))
+
+#define IS_PRIORITY_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
+                                             (HANDLER == SystemHandler_BusFault) || \
+                                             (HANDLER == SystemHandler_UsageFault) || \
+                                             (HANDLER == SystemHandler_SVCall) || \
+                                             (HANDLER == SystemHandler_DebugMonitor) || \
+                                             (HANDLER == SystemHandler_PSV) || \
+                                             (HANDLER == SystemHandler_SysTick))
+
+#define IS_GET_PENDING_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
+                                                (HANDLER == SystemHandler_BusFault) || \
+                                                (HANDLER == SystemHandler_SVCall))
+
+#define IS_SET_PENDING_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_NMI) || \
+                                                (HANDLER == SystemHandler_PSV) || \
+                                                (HANDLER == SystemHandler_SysTick))
+
+#define IS_CLEAR_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_PSV) || \
+                                          (HANDLER == SystemHandler_SysTick))
+
+#define IS_GET_ACTIVE_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
+                                               (HANDLER == SystemHandler_BusFault) || \
+                                               (HANDLER == SystemHandler_UsageFault) || \
+                                               (HANDLER == SystemHandler_SVCall) || \
+                                               (HANDLER == SystemHandler_DebugMonitor) || \
+                                               (HANDLER == SystemHandler_PSV) || \
+                                               (HANDLER == SystemHandler_SysTick))
+
+#define IS_FAULT_SOURCE_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_HardFault) || \
+                                                 (HANDLER == SystemHandler_MemoryManage) || \
+                                                 (HANDLER == SystemHandler_BusFault) || \
+                                                 (HANDLER == SystemHandler_UsageFault) || \
+                                                 (HANDLER == SystemHandler_DebugMonitor)) 
+
+#define IS_FAULT_ADDRESS_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \
+                                                  (HANDLER == SystemHandler_BusFault))
+
+
+/* Vector Table Base ---------------------------------------------------------*/
+#define NVIC_VectTab_RAM             ((u32)0x20000000)
+#define NVIC_VectTab_FLASH           ((u32)0x00000000)
+
+#define IS_NVIC_VECTTAB(VECTTAB) ((VECTTAB == NVIC_VectTab_RAM) || \
+                                  (VECTTAB == NVIC_VectTab_FLASH))
+
+/* System Low Power ----------------------------------------------------------*/
+#define NVIC_LP_SEVONPEND            ((u8)0x10)
+#define NVIC_LP_SLEEPDEEP            ((u8)0x04)
+#define NVIC_LP_SLEEPONEXIT          ((u8)0x02)
+
+#define IS_NVIC_LP(LP) ((LP == NVIC_LP_SEVONPEND) || \
+                        (LP == NVIC_LP_SLEEPDEEP) || \
+                        (LP == NVIC_LP_SLEEPONEXIT))
+
+/* Preemption Priority Group -------------------------------------------------*/
+#define NVIC_PriorityGroup_0         ((u32)0x700) /* 0 bits for pre-emption priority
+                                                     4 bits for subpriority */
+#define NVIC_PriorityGroup_1         ((u32)0x600) /* 1 bits for pre-emption priority
+                                                     3 bits for subpriority */
+#define NVIC_PriorityGroup_2         ((u32)0x500) /* 2 bits for pre-emption priority
+                                                     2 bits for subpriority */
+#define NVIC_PriorityGroup_3         ((u32)0x400) /* 3 bits for pre-emption priority
+                                                     1 bits for subpriority */
+#define NVIC_PriorityGroup_4         ((u32)0x300) /* 4 bits for pre-emption priority
+                                                     0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) ((GROUP == NVIC_PriorityGroup_0) || \
+                                       (GROUP == NVIC_PriorityGroup_1) || \
+                                       (GROUP == NVIC_PriorityGroup_2) || \
+                                       (GROUP == NVIC_PriorityGroup_3) || \
+                                       (GROUP == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  (PRIORITY < 0x10)
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)  (PRIORITY < 0x10)
+#define IS_NVIC_OFFSET(OFFSET)  (OFFSET < 0x3FFFFF)
+#define IS_NVIC_BASE_PRI(PRI) ((PRI > 0x00) && (PRI < 0x10))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void NVIC_DeInit(void);
+void NVIC_SCBDeInit(void);
+void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SETPRIMASK(void);
+void NVIC_RESETPRIMASK(void);
+void NVIC_SETFAULTMASK(void);
+void NVIC_RESETFAULTMASK(void);
+void NVIC_BASEPRICONFIG(u32 NewPriority);
+u32 NVIC_GetBASEPRI(void);
+u16 NVIC_GetCurrentPendingIRQChannel(void);
+ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel);
+void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel);
+void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel);
+u16 NVIC_GetCurrentActiveHandler(void);
+ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel);
+u32 NVIC_GetCPUID(void);
+void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset);
+void NVIC_GenerateSystemReset(void);
+void NVIC_GenerateCoreReset(void);
+void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState);
+void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState);
+void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority,
+                                      u8 SystemHandlerSubPriority);
+ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler);
+void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler);
+void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler);
+ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler);
+u32 NVIC_GetFaultHandlerSources(u32 SystemHandler);
+u32 NVIC_GetFaultAddress(u32 SystemHandler);
+
+#endif /* __STM32F10x_NVIC_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_pwr.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_pwr.h
new file mode 100644
index 0000000..4bbc291
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_pwr.h
@@ -0,0 +1,81 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_pwr.h
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file contains all the functions prototypes for the
+*                      PWR firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_PWR_H
+#define __STM32F10x_PWR_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* PVD detection level */
+#define PWR_PVDLevel_2V2          ((u32)0x00000000)
+#define PWR_PVDLevel_2V3          ((u32)0x00000020)
+#define PWR_PVDLevel_2V4          ((u32)0x00000040)
+#define PWR_PVDLevel_2V5          ((u32)0x00000060)
+#define PWR_PVDLevel_2V6          ((u32)0x00000080)
+#define PWR_PVDLevel_2V7          ((u32)0x000000A0)
+#define PWR_PVDLevel_2V8          ((u32)0x000000C0)
+#define PWR_PVDLevel_2V9          ((u32)0x000000E0)
+
+#define IS_PWR_PVD_LEVEL(LEVEL) ((LEVEL == PWR_PVDLevel_2V2) || (LEVEL == PWR_PVDLevel_2V3)|| \
+                                 (LEVEL == PWR_PVDLevel_2V4) || (LEVEL == PWR_PVDLevel_2V5)|| \
+                                 (LEVEL == PWR_PVDLevel_2V6) || (LEVEL == PWR_PVDLevel_2V7)|| \
+                                 (LEVEL == PWR_PVDLevel_2V8) || (LEVEL == PWR_PVDLevel_2V9))
+
+/* Regulator state is STOP mode */
+#define PWR_Regulator_ON          ((u32)0x00000000)
+#define PWR_Regulator_LowPower    ((u32)0x00000001)
+
+#define IS_PWR_REGULATOR(REGULATOR) ((REGULATOR == PWR_Regulator_ON) || \
+                                     (REGULATOR == PWR_Regulator_LowPower))
+
+/* STOP mode entry */
+#define PWR_STOPEntry_WFI         ((u8)0x01)
+#define PWR_STOPEntry_WFE         ((u8)0x02)
+
+#define IS_PWR_STOP_ENTRY(ENTRY) ((ENTRY == PWR_STOPEntry_WFI) || (ENTRY == PWR_STOPEntry_WFE))
+ 
+/* PWR Flag */
+#define PWR_FLAG_WU               ((u32)0x00000001)
+#define PWR_FLAG_SB               ((u32)0x00000002)
+#define PWR_FLAG_PVDO             ((u32)0x00000004)
+
+#define IS_PWR_GET_FLAG(FLAG) ((FLAG == PWR_FLAG_WU) || (FLAG == PWR_FLAG_SB) || \
+                               (FLAG == PWR_FLAG_PVDO))
+#define IS_PWR_CLEAR_FLAG(FLAG) ((FLAG == PWR_FLAG_WU) || (FLAG == PWR_FLAG_SB))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void PWR_DeInit(void);
+void PWR_BackupAccessCmd(FunctionalState NewState);
+void PWR_PVDCmd(FunctionalState NewState);
+void PWR_PVDLevelConfig(u32 PWR_PVDLevel);
+void PWR_WakeUpPinCmd(FunctionalState NewState);
+void PWR_EnterSTOPMode(u32 PWR_Regulator, u8 PWR_STOPEntry);
+void PWR_EnterSTANDBYMode(void);
+FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG);
+void PWR_ClearFlag(u32 PWR_FLAG);
+
+#endif /* __STM32F10x_PWR_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_rcc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_rcc.h
new file mode 100644
index 0000000..b7d0aa3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_rcc.h
@@ -0,0 +1,276 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_rcc.h
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file contains all the functions prototypes for the
+*                      RCC firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_RCC_H
+#define __STM32F10x_RCC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+typedef struct
+{
+  u32 SYSCLK_Frequency;
+  u32 HCLK_Frequency;
+  u32 PCLK1_Frequency;
+  u32 PCLK2_Frequency;
+  u32 ADCCLK_Frequency;
+}RCC_ClocksTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* HSE configuration */
+#define RCC_HSE_OFF                      ((u32)0x00000000)
+#define RCC_HSE_ON                       ((u32)0x00010000)
+#define RCC_HSE_Bypass                   ((u32)0x00040000)
+
+#define IS_RCC_HSE(HSE) ((HSE == RCC_HSE_OFF) || (HSE == RCC_HSE_ON) || \
+                         (HSE == RCC_HSE_Bypass))
+
+/* PLL entry clock source */
+#define RCC_PLLSource_HSI_Div2           ((u32)0x00000000)
+#define RCC_PLLSource_HSE_Div1           ((u32)0x00010000)
+#define RCC_PLLSource_HSE_Div2           ((u32)0x00030000)
+
+#define IS_RCC_PLL_SOURCE(SOURCE) ((SOURCE == RCC_PLLSource_HSI_Div2) || \
+                                   (SOURCE == RCC_PLLSource_HSE_Div1) || \
+                                   (SOURCE == RCC_PLLSource_HSE_Div2))
+
+/* PLL multiplication factor */
+#define RCC_PLLMul_2                     ((u32)0x00000000)
+#define RCC_PLLMul_3                     ((u32)0x00040000)
+#define RCC_PLLMul_4                     ((u32)0x00080000)
+#define RCC_PLLMul_5                     ((u32)0x000C0000)
+#define RCC_PLLMul_6                     ((u32)0x00100000)
+#define RCC_PLLMul_7                     ((u32)0x00140000)
+#define RCC_PLLMul_8                     ((u32)0x00180000)
+#define RCC_PLLMul_9                     ((u32)0x001C0000)
+#define RCC_PLLMul_10                    ((u32)0x00200000)
+#define RCC_PLLMul_11                    ((u32)0x00240000)
+#define RCC_PLLMul_12                    ((u32)0x00280000)
+#define RCC_PLLMul_13                    ((u32)0x002C0000)
+#define RCC_PLLMul_14                    ((u32)0x00300000)
+#define RCC_PLLMul_15                    ((u32)0x00340000)
+#define RCC_PLLMul_16                    ((u32)0x00380000)
+
+#define IS_RCC_PLL_MUL(MUL) ((MUL == RCC_PLLMul_2) || (MUL == RCC_PLLMul_3)   ||\
+                             (MUL == RCC_PLLMul_4) || (MUL == RCC_PLLMul_5)   ||\
+                             (MUL == RCC_PLLMul_6) || (MUL == RCC_PLLMul_7)   ||\
+                             (MUL == RCC_PLLMul_8) || (MUL == RCC_PLLMul_9)   ||\
+                             (MUL == RCC_PLLMul_10) || (MUL == RCC_PLLMul_11) ||\
+                             (MUL == RCC_PLLMul_12) || (MUL == RCC_PLLMul_13) ||\
+                             (MUL == RCC_PLLMul_14) || (MUL == RCC_PLLMul_15) ||\
+                             (MUL == RCC_PLLMul_16))
+
+/* System clock source */
+#define RCC_SYSCLKSource_HSI             ((u32)0x00000000)
+#define RCC_SYSCLKSource_HSE             ((u32)0x00000001)
+#define RCC_SYSCLKSource_PLLCLK          ((u32)0x00000002)
+
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) ((SOURCE == RCC_SYSCLKSource_HSI) || \
+                                      (SOURCE == RCC_SYSCLKSource_HSE) || \
+                                      (SOURCE == RCC_SYSCLKSource_PLLCLK))
+
+/* AHB clock source */
+#define RCC_SYSCLK_Div1                  ((u32)0x00000000)
+#define RCC_SYSCLK_Div2                  ((u32)0x00000080)
+#define RCC_SYSCLK_Div4                  ((u32)0x00000090)
+#define RCC_SYSCLK_Div8                  ((u32)0x000000A0)
+#define RCC_SYSCLK_Div16                 ((u32)0x000000B0)
+#define RCC_SYSCLK_Div64                 ((u32)0x000000C0)
+#define RCC_SYSCLK_Div128                ((u32)0x000000D0)
+#define RCC_SYSCLK_Div256                ((u32)0x000000E0)
+#define RCC_SYSCLK_Div512                ((u32)0x000000F0)
+
+#define IS_RCC_HCLK(HCLK) ((HCLK == RCC_SYSCLK_Div1) || (HCLK == RCC_SYSCLK_Div2) || \
+                           (HCLK == RCC_SYSCLK_Div4) || (HCLK == RCC_SYSCLK_Div8) || \
+                           (HCLK == RCC_SYSCLK_Div16) || (HCLK == RCC_SYSCLK_Div64) || \
+                           (HCLK == RCC_SYSCLK_Div128) || (HCLK == RCC_SYSCLK_Div256) || \
+                           (HCLK == RCC_SYSCLK_Div512))
+
+/* APB1/APB2 clock source */
+#define RCC_HCLK_Div1                    ((u32)0x00000000)
+#define RCC_HCLK_Div2                    ((u32)0x00000400)
+#define RCC_HCLK_Div4                    ((u32)0x00000500)
+#define RCC_HCLK_Div8                    ((u32)0x00000600)
+#define RCC_HCLK_Div16                   ((u32)0x00000700)
+
+#define IS_RCC_PCLK(PCLK) ((PCLK == RCC_HCLK_Div1) || (PCLK == RCC_HCLK_Div2) || \
+                           (PCLK == RCC_HCLK_Div4) || (PCLK == RCC_HCLK_Div8) || \
+                           (PCLK == RCC_HCLK_Div16))
+
+/* RCC Interrupt source */
+#define RCC_IT_LSIRDY                    ((u8)0x01)
+#define RCC_IT_LSERDY                    ((u8)0x02)
+#define RCC_IT_HSIRDY                    ((u8)0x04)
+#define RCC_IT_HSERDY                    ((u8)0x08)
+#define RCC_IT_PLLRDY                    ((u8)0x10)
+#define RCC_IT_CSS                       ((u8)0x80)
+
+#define IS_RCC_IT(IT) (((IT & (u8)0xE0) == 0x00) && (IT != 0x00))
+#define IS_RCC_GET_IT(IT) ((IT == RCC_IT_LSIRDY) || (IT == RCC_IT_LSERDY) || \
+                           (IT == RCC_IT_HSIRDY) || (IT == RCC_IT_HSERDY) || \
+                           (IT == RCC_IT_PLLRDY) || (IT == RCC_IT_CSS))
+#define IS_RCC_CLEAR_IT(IT) (((IT & (u8)0x60) == 0x00) && (IT != 0x00))
+
+/* USB clock source */
+#define RCC_USBCLKSource_PLLCLK_1Div5    ((u8)0x00)
+#define RCC_USBCLKSource_PLLCLK_Div1     ((u8)0x01)
+
+#define IS_RCC_USBCLK_SOURCE(SOURCE) ((SOURCE == RCC_USBCLKSource_PLLCLK_1Div5) || \
+                                      (SOURCE == RCC_USBCLKSource_PLLCLK_Div1))
+
+/* ADC clock source */
+#define RCC_PCLK2_Div2                   ((u32)0x00000000)
+#define RCC_PCLK2_Div4                   ((u32)0x00004000)
+#define RCC_PCLK2_Div6                   ((u32)0x00008000)
+#define RCC_PCLK2_Div8                   ((u32)0x0000C000)
+
+#define IS_RCC_ADCCLK(ADCCLK) ((ADCCLK == RCC_PCLK2_Div2) || (ADCCLK == RCC_PCLK2_Div4) || \
+                               (ADCCLK == RCC_PCLK2_Div6) || (ADCCLK == RCC_PCLK2_Div8))
+
+/* LSE configuration */
+#define RCC_LSE_OFF                      ((u8)0x00)
+#define RCC_LSE_ON                       ((u8)0x01)
+#define RCC_LSE_Bypass                   ((u8)0x04)
+
+#define IS_RCC_LSE(LSE) ((LSE == RCC_LSE_OFF) || (LSE == RCC_LSE_ON) || \
+                         (LSE == RCC_LSE_Bypass))
+
+/* RTC clock source */
+#define RCC_RTCCLKSource_LSE             ((u32)0x00000100)
+#define RCC_RTCCLKSource_LSI             ((u32)0x00000200)
+#define RCC_RTCCLKSource_HSE_Div128      ((u32)0x00000300)
+
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) ((SOURCE == RCC_RTCCLKSource_LSE) || \
+                                      (SOURCE == RCC_RTCCLKSource_LSI) || \
+                                      (SOURCE == RCC_RTCCLKSource_HSE_Div128))
+
+/* AHB peripheral */
+#define RCC_AHBPeriph_DMA                ((u32)0x00000001)
+#define RCC_AHBPeriph_SRAM               ((u32)0x00000004)
+#define RCC_AHBPeriph_FLITF              ((u32)0x00000010)
+
+#define IS_RCC_AHB_PERIPH(PERIPH) (((PERIPH & 0xFFFFFFEA) == 0x00) && (PERIPH != 0x00))
+
+/* APB2 peripheral */
+#define RCC_APB2Periph_AFIO              ((u32)0x00000001)
+#define RCC_APB2Periph_GPIOA             ((u32)0x00000004)
+#define RCC_APB2Periph_GPIOB             ((u32)0x00000008)
+#define RCC_APB2Periph_GPIOC             ((u32)0x00000010)
+#define RCC_APB2Periph_GPIOD             ((u32)0x00000020)
+#define RCC_APB2Periph_GPIOE             ((u32)0x00000040)
+#define RCC_APB2Periph_ADC1              ((u32)0x00000200)
+#define RCC_APB2Periph_ADC2              ((u32)0x00000400)
+#define RCC_APB2Periph_TIM1              ((u32)0x00000800)
+#define RCC_APB2Periph_SPI1              ((u32)0x00001000)
+#define RCC_APB2Periph_USART1            ((u32)0x00004000)
+#define RCC_APB2Periph_ALL               ((u32)0x00005E7D)
+
+#define IS_RCC_APB2_PERIPH(PERIPH) (((PERIPH & 0xFFFFA182) == 0x00) && (PERIPH != 0x00))
+
+/* APB1 peripheral */
+#define RCC_APB1Periph_TIM2              ((u32)0x00000001)
+#define RCC_APB1Periph_TIM3              ((u32)0x00000002)
+#define RCC_APB1Periph_TIM4              ((u32)0x00000004)
+#define RCC_APB1Periph_WWDG              ((u32)0x00000800)
+#define RCC_APB1Periph_SPI2              ((u32)0x00004000)
+#define RCC_APB1Periph_USART2            ((u32)0x00020000)
+#define RCC_APB1Periph_USART3            ((u32)0x00040000)
+#define RCC_APB1Periph_I2C1              ((u32)0x00200000)
+#define RCC_APB1Periph_I2C2              ((u32)0x00400000)
+#define RCC_APB1Periph_USB               ((u32)0x00800000)
+#define RCC_APB1Periph_CAN               ((u32)0x02000000)
+#define RCC_APB1Periph_BKP               ((u32)0x08000000)
+#define RCC_APB1Periph_PWR               ((u32)0x10000000)
+#define RCC_APB1Periph_ALL               ((u32)0x1AE64807)
+
+#define IS_RCC_APB1_PERIPH(PERIPH) (((PERIPH & 0xE519B7F8) == 0x00) && (PERIPH != 0x00))
+
+/* Clock source to output on MCO pin */
+#define RCC_MCO_NoClock                  ((u8)0x00)
+#define RCC_MCO_SYSCLK                   ((u8)0x04)
+#define RCC_MCO_HSI                      ((u8)0x05)
+#define RCC_MCO_HSE                      ((u8)0x06)
+#define RCC_MCO_PLLCLK_Div2              ((u8)0x07)
+
+#define IS_RCC_MCO(MCO) ((MCO == RCC_MCO_NoClock) || (MCO == RCC_MCO_HSI) || \
+                         (MCO == RCC_MCO_SYSCLK)  || (MCO == RCC_MCO_HSE) || \
+                         (MCO == RCC_MCO_PLLCLK_Div2))
+
+/* RCC Flag */
+#define RCC_FLAG_HSIRDY                  ((u8)0x20)
+#define RCC_FLAG_HSERDY                  ((u8)0x31)
+#define RCC_FLAG_PLLRDY                  ((u8)0x39)
+#define RCC_FLAG_LSERDY                  ((u8)0x41)
+#define RCC_FLAG_LSIRDY                  ((u8)0x61)
+#define RCC_FLAG_PINRST                  ((u8)0x7A)
+#define RCC_FLAG_PORRST                  ((u8)0x7B)
+#define RCC_FLAG_SFTRST                  ((u8)0x7C)
+#define RCC_FLAG_IWDGRST                 ((u8)0x7D)
+#define RCC_FLAG_WWDGRST                 ((u8)0x7E)
+#define RCC_FLAG_LPWRRST                 ((u8)0x7F)
+
+#define IS_RCC_FLAG(FLAG) ((FLAG == RCC_FLAG_HSIRDY) || (FLAG == RCC_FLAG_HSERDY) || \
+                           (FLAG == RCC_FLAG_PLLRDY) || (FLAG == RCC_FLAG_LSERDY) || \
+                           (FLAG == RCC_FLAG_LSIRDY) || (FLAG == RCC_FLAG_PINRST) || \
+                           (FLAG == RCC_FLAG_PORRST) || (FLAG == RCC_FLAG_SFTRST) || \
+                           (FLAG == RCC_FLAG_IWDGRST)|| (FLAG == RCC_FLAG_WWDGRST)|| \
+                           (FLAG == RCC_FLAG_LPWRRST))
+
+#define IS_RCC_CALIBRATION_VALUE(VALUE) (VALUE <= 0x1F)
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void RCC_DeInit(void);
+void RCC_HSEConfig(u32 RCC_HSE);
+void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul);
+void RCC_PLLCmd(FunctionalState NewState);
+void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource);
+u8 RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(u32 RCC_HCLK);
+void RCC_PCLK1Config(u32 RCC_PCLK1);
+void RCC_PCLK2Config(u32 RCC_PCLK2);
+void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState);
+void RCC_USBCLKConfig(u32 RCC_USBCLKSource);
+void RCC_ADCCLKConfig(u32 RCC_ADCCLK);
+void RCC_LSEConfig(u32 RCC_LSE);
+void RCC_LSICmd(FunctionalState NewState);
+void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState);
+void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+void RCC_MCOConfig(u8 RCC_MCO);
+FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetITStatus(u8 RCC_IT);
+void RCC_ClearITPendingBit(u8 RCC_IT);
+
+#endif /* __STM32F10x_RCC_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_rtc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_rtc.h
new file mode 100644
index 0000000..6f8c4e0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_rtc.h
@@ -0,0 +1,75 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_rtc.h
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file contains all the functions prototypes for the
+*                      RTC firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_RTC_H
+#define __STM32F10x_RTC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* RTC interrupts define -----------------------------------------------------*/
+#define RTC_IT_OW            ((u16)0x0004)  /* Overflow interrupt */
+#define RTC_IT_ALR           ((u16)0x0002)  /* Alarm interrupt */
+#define RTC_IT_SEC           ((u16)0x0001)  /* Second interrupt */
+
+#define IS_RTC_IT(IT) (((IT & (u16)0xFFF8) == 0x00) && (IT != 0x00))
+
+#define IS_RTC_GET_IT(IT) ((IT == RTC_IT_OW) || (IT == RTC_IT_ALR) || \
+                           (IT == RTC_IT_SEC))
+                                                                     
+/* RTC interrupts flags ------------------------------------------------------*/
+#define RTC_FLAG_RTOFF       ((u16)0x0020)  /* RTC Operation OFF flag */
+#define RTC_FLAG_RSF         ((u16)0x0008)  /* Registers Synchronized flag */
+#define RTC_FLAG_OW          ((u16)0x0004)  /* Overflow flag */
+#define RTC_FLAG_ALR         ((u16)0x0002)  /* Alarm flag */
+#define RTC_FLAG_SEC         ((u16)0x0001)  /* Second flag */
+
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xFFF0) == 0x00) && (FLAG != 0x00))
+
+#define IS_RTC_GET_FLAG(FLAG) ((FLAG == RTC_FLAG_RTOFF) || (FLAG == RTC_FLAG_RSF) || \
+                               (FLAG == RTC_FLAG_OW) || (FLAG == RTC_FLAG_ALR) || \
+                               (FLAG == RTC_FLAG_SEC))
+
+#define IS_RTC_PRESCALER(PRESCALER) (PRESCALER <= 0xFFFFF)
+                           
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState);
+void RTC_EnterConfigMode(void);
+void RTC_ExitConfigMode(void);
+u32  RTC_GetCounter(void);
+void RTC_SetCounter(u32 CounterValue);
+u32  RTC_GetPrescaler(void);
+void RTC_SetPrescaler(u32 PrescalerValue);
+void RTC_SetAlarm(u32 AlarmValue);
+u32  RTC_GetDivider(void);
+void RTC_WaitForLastTask(void);
+void RTC_WaitForSynchro(void);
+FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG);
+void RTC_ClearFlag(u16 RTC_FLAG);
+ITStatus RTC_GetITStatus(u16 RTC_IT);
+void RTC_ClearITPendingBit(u16 RTC_IT);
+
+#endif /* __STM32F10x_RTC_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_sdio.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_sdio.h
new file mode 100644
index 0000000..4353fc1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_sdio.h
@@ -0,0 +1,486 @@
+/**
+  ******************************************************************************
+  * @file  stm32f10x_sdio.h
+  * @author  MCD Application Team
+  * @version  V3.0.0
+  * @date  04/06/2009
+  * @brief  This file contains all the functions prototypes for the SDIO 
+  *         firmware library.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
© COPYRIGHT 2009 STMicroelectronics

+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_SDIO_H
+#define __STM32F10x_SDIO_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SDIO
+  * @{
+  */
+
+/** @defgroup SDIO_Exported_Types
+  * @{
+  */
+
+typedef struct
+{
+  uint8_t SDIO_ClockDiv;
+  uint32_t SDIO_ClockEdge;
+  uint32_t SDIO_ClockBypass;
+  uint32_t SDIO_ClockPowerSave;
+  uint32_t SDIO_BusWide;
+  uint32_t SDIO_HardwareFlowControl;
+} SDIO_InitTypeDef;
+
+typedef struct
+{
+  uint32_t SDIO_Argument;
+  uint32_t SDIO_CmdIndex;
+  uint32_t SDIO_Response;
+  uint32_t SDIO_Wait;
+  uint32_t SDIO_CPSM;
+} SDIO_CmdInitTypeDef;
+
+typedef struct
+{
+  uint32_t SDIO_DataTimeOut;
+  uint32_t SDIO_DataLength;
+  uint32_t SDIO_DataBlockSize;
+  uint32_t SDIO_TransferDir;
+  uint32_t SDIO_TransferMode;
+  uint32_t SDIO_DPSM;
+} SDIO_DataInitTypeDef;
+
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_Exported_Constants
+  * @{
+  */
+
+/** @defgroup SDIO_Clock_Edge 
+  * @{
+  */
+
+#define SDIO_ClockEdge_Rising               ((uint32_t)0x00000000)
+#define SDIO_ClockEdge_Falling              ((uint32_t)0x00002000)
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
+                                  ((EDGE) == SDIO_ClockEdge_Falling))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Clock_Bypass 
+  * @{
+  */
+
+#define SDIO_ClockBypass_Disable             ((uint32_t)0x00000000)
+#define SDIO_ClockBypass_Enable              ((uint32_t)0x00000400)    
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
+                                     ((BYPASS) == SDIO_ClockBypass_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_Clock_Power_Save_ 
+  * @{
+  */
+
+#define SDIO_ClockPowerSave_Disable         ((uint32_t)0x00000000)
+#define SDIO_ClockPowerSave_Enable          ((uint32_t)0x00000200) 
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
+                                        ((SAVE) == SDIO_ClockPowerSave_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Bus_Wide 
+  * @{
+  */
+
+#define SDIO_BusWide_1b                     ((uint32_t)0x00000000)
+#define SDIO_BusWide_4b                     ((uint32_t)0x00000800)
+#define SDIO_BusWide_8b                     ((uint32_t)0x00001000)
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
+                                ((WIDE) == SDIO_BusWide_8b))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Hardware_Flow_Control_ 
+  * @{
+  */
+
+#define SDIO_HardwareFlowControl_Disable    ((uint32_t)0x00000000)
+#define SDIO_HardwareFlowControl_Enable     ((uint32_t)0x00004000)
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
+                                                ((CONTROL) == SDIO_HardwareFlowControl_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Power_State 
+  * @{
+  */
+
+#define SDIO_PowerState_OFF                 ((uint32_t)0x00000000)
+#define SDIO_PowerState_ON                  ((uint32_t)0x00000003)
+#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup SDIO_Interrupt_soucres 
+  * @{
+  */
+
+#define SDIO_IT_CCRCFAIL                    ((uint32_t)0x00000001)
+#define SDIO_IT_DCRCFAIL                    ((uint32_t)0x00000002)
+#define SDIO_IT_CTIMEOUT                    ((uint32_t)0x00000004)
+#define SDIO_IT_DTIMEOUT                    ((uint32_t)0x00000008)
+#define SDIO_IT_TXUNDERR                    ((uint32_t)0x00000010)
+#define SDIO_IT_RXOVERR                     ((uint32_t)0x00000020)
+#define SDIO_IT_CMDREND                     ((uint32_t)0x00000040)
+#define SDIO_IT_CMDSENT                     ((uint32_t)0x00000080)
+#define SDIO_IT_DATAEND                     ((uint32_t)0x00000100)
+#define SDIO_IT_STBITERR                    ((uint32_t)0x00000200)
+#define SDIO_IT_DBCKEND                     ((uint32_t)0x00000400)
+#define SDIO_IT_CMDACT                      ((uint32_t)0x00000800)
+#define SDIO_IT_TXACT                       ((uint32_t)0x00001000)
+#define SDIO_IT_RXACT                       ((uint32_t)0x00002000)
+#define SDIO_IT_TXFIFOHE                    ((uint32_t)0x00004000)
+#define SDIO_IT_RXFIFOHF                    ((uint32_t)0x00008000)
+#define SDIO_IT_TXFIFOF                     ((uint32_t)0x00010000)
+#define SDIO_IT_RXFIFOF                     ((uint32_t)0x00020000)
+#define SDIO_IT_TXFIFOE                     ((uint32_t)0x00040000)
+#define SDIO_IT_RXFIFOE                     ((uint32_t)0x00080000)
+#define SDIO_IT_TXDAVL                      ((uint32_t)0x00100000)
+#define SDIO_IT_RXDAVL                      ((uint32_t)0x00200000)
+#define SDIO_IT_SDIOIT                      ((uint32_t)0x00400000)
+#define SDIO_IT_CEATAEND                    ((uint32_t)0x00800000)
+#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_Command_Index_ 
+  * @{
+  */
+
+#define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Response_Type 
+  * @{
+  */
+
+#define SDIO_Response_No                    ((uint32_t)0x00000000)
+#define SDIO_Response_Short                 ((uint32_t)0x00000040)
+#define SDIO_Response_Long                  ((uint32_t)0x000000C0)
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
+                                    ((RESPONSE) == SDIO_Response_Short) || \
+                                    ((RESPONSE) == SDIO_Response_Long))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Wait_Interrupt_State 
+  * @{
+  */
+
+#define SDIO_Wait_No                        ((uint32_t)0x00000000) /* SDIO No Wait, TimeOut is enabled */
+#define SDIO_Wait_IT                        ((uint32_t)0x00000100) /* SDIO Wait Interrupt Request */
+#define SDIO_Wait_Pend                      ((uint32_t)0x00000200) /* SDIO Wait End of transfer */
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
+                            ((WAIT) == SDIO_Wait_Pend))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_CPSM_State 
+  * @{
+  */
+
+#define SDIO_CPSM_Disable                    ((uint32_t)0x00000000)
+#define SDIO_CPSM_Enable                     ((uint32_t)0x00000400)
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_Response_Registers 
+  * @{
+  */
+
+#define SDIO_RESP1                          ((uint32_t)0x00000000)
+#define SDIO_RESP2                          ((uint32_t)0x00000004)
+#define SDIO_RESP3                          ((uint32_t)0x00000008)
+#define SDIO_RESP4                          ((uint32_t)0x0000000C)
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
+                            ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Data_Length 
+  * @{
+  */
+
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Data_Block_Size 
+  * @{
+  */
+
+#define SDIO_DataBlockSize_1b               ((uint32_t)0x00000000)
+#define SDIO_DataBlockSize_2b               ((uint32_t)0x00000010)
+#define SDIO_DataBlockSize_4b               ((uint32_t)0x00000020)
+#define SDIO_DataBlockSize_8b               ((uint32_t)0x00000030)
+#define SDIO_DataBlockSize_16b              ((uint32_t)0x00000040)
+#define SDIO_DataBlockSize_32b              ((uint32_t)0x00000050)
+#define SDIO_DataBlockSize_64b              ((uint32_t)0x00000060)
+#define SDIO_DataBlockSize_128b             ((uint32_t)0x00000070)
+#define SDIO_DataBlockSize_256b             ((uint32_t)0x00000080)
+#define SDIO_DataBlockSize_512b             ((uint32_t)0x00000090)
+#define SDIO_DataBlockSize_1024b            ((uint32_t)0x000000A0)
+#define SDIO_DataBlockSize_2048b            ((uint32_t)0x000000B0)
+#define SDIO_DataBlockSize_4096b            ((uint32_t)0x000000C0)
+#define SDIO_DataBlockSize_8192b            ((uint32_t)0x000000D0)
+#define SDIO_DataBlockSize_16384b           ((uint32_t)0x000000E0)
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_2b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_4b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_8b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_16b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_32b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_64b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_128b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_256b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_512b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_1024b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_2048b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_4096b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_8192b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_16384b)) 
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Transfer_Direction 
+  * @{
+  */
+
+#define SDIO_TransferDir_ToCard             ((uint32_t)0x00000000)
+#define SDIO_TransferDir_ToSDIO             ((uint32_t)0x00000002)
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
+                                   ((DIR) == SDIO_TransferDir_ToSDIO))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Transfer_Type 
+  * @{
+  */
+
+#define SDIO_TransferMode_Block             ((uint32_t)0x00000000)
+#define SDIO_TransferMode_Stream            ((uint32_t)0x00000004)
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
+                                     ((MODE) == SDIO_TransferMode_Block))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_DPSM_State 
+  * @{
+  */
+
+#define SDIO_DPSM_Disable                    ((uint32_t)0x00000000)
+#define SDIO_DPSM_Enable                     ((uint32_t)0x00000001)
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Flags 
+  * @{
+  */
+
+#define SDIO_FLAG_CCRCFAIL                  ((uint32_t)0x00000001)
+#define SDIO_FLAG_DCRCFAIL                  ((uint32_t)0x00000002)
+#define SDIO_FLAG_CTIMEOUT                  ((uint32_t)0x00000004)
+#define SDIO_FLAG_DTIMEOUT                  ((uint32_t)0x00000008)
+#define SDIO_FLAG_TXUNDERR                  ((uint32_t)0x00000010)
+#define SDIO_FLAG_RXOVERR                   ((uint32_t)0x00000020)
+#define SDIO_FLAG_CMDREND                   ((uint32_t)0x00000040)
+#define SDIO_FLAG_CMDSENT                   ((uint32_t)0x00000080)
+#define SDIO_FLAG_DATAEND                   ((uint32_t)0x00000100)
+#define SDIO_FLAG_STBITERR                  ((uint32_t)0x00000200)
+#define SDIO_FLAG_DBCKEND                   ((uint32_t)0x00000400)
+#define SDIO_FLAG_CMDACT                    ((uint32_t)0x00000800)
+#define SDIO_FLAG_TXACT                     ((uint32_t)0x00001000)
+#define SDIO_FLAG_RXACT                     ((uint32_t)0x00002000)
+#define SDIO_FLAG_TXFIFOHE                  ((uint32_t)0x00004000)
+#define SDIO_FLAG_RXFIFOHF                  ((uint32_t)0x00008000)
+#define SDIO_FLAG_TXFIFOF                   ((uint32_t)0x00010000)
+#define SDIO_FLAG_RXFIFOF                   ((uint32_t)0x00020000)
+#define SDIO_FLAG_TXFIFOE                   ((uint32_t)0x00040000)
+#define SDIO_FLAG_RXFIFOE                   ((uint32_t)0x00080000)
+#define SDIO_FLAG_TXDAVL                    ((uint32_t)0x00100000)
+#define SDIO_FLAG_RXDAVL                    ((uint32_t)0x00200000)
+#define SDIO_FLAG_SDIOIT                    ((uint32_t)0x00400000)
+#define SDIO_FLAG_CEATAEND                  ((uint32_t)0x00800000)
+#define IS_SDIO_FLAG(FLAG) (((FLAG)  == SDIO_FLAG_CCRCFAIL) || \
+                            ((FLAG)  == SDIO_FLAG_DCRCFAIL) || \
+                            ((FLAG)  == SDIO_FLAG_CTIMEOUT) || \
+                            ((FLAG)  == SDIO_FLAG_DTIMEOUT) || \
+                            ((FLAG)  == SDIO_FLAG_TXUNDERR) || \
+                            ((FLAG)  == SDIO_FLAG_RXOVERR) || \
+                            ((FLAG)  == SDIO_FLAG_CMDREND) || \
+                            ((FLAG)  == SDIO_FLAG_CMDSENT) || \
+                            ((FLAG)  == SDIO_FLAG_DATAEND) || \
+                            ((FLAG)  == SDIO_FLAG_STBITERR) || \
+                            ((FLAG)  == SDIO_FLAG_DBCKEND) || \
+                            ((FLAG)  == SDIO_FLAG_CMDACT) || \
+                            ((FLAG)  == SDIO_FLAG_TXACT) || \
+                            ((FLAG)  == SDIO_FLAG_RXACT) || \
+                            ((FLAG)  == SDIO_FLAG_TXFIFOHE) || \
+                            ((FLAG)  == SDIO_FLAG_RXFIFOHF) || \
+                            ((FLAG)  == SDIO_FLAG_TXFIFOF) || \
+                            ((FLAG)  == SDIO_FLAG_RXFIFOF) || \
+                            ((FLAG)  == SDIO_FLAG_TXFIFOE) || \
+                            ((FLAG)  == SDIO_FLAG_RXFIFOE) || \
+                            ((FLAG)  == SDIO_FLAG_TXDAVL) || \
+                            ((FLAG)  == SDIO_FLAG_RXDAVL) || \
+                            ((FLAG)  == SDIO_FLAG_SDIOIT) || \
+                            ((FLAG)  == SDIO_FLAG_CEATAEND))
+
+#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
+
+#define IS_SDIO_GET_IT(IT) (((IT)  == SDIO_IT_CCRCFAIL) || \
+                            ((IT)  == SDIO_IT_DCRCFAIL) || \
+                            ((IT)  == SDIO_IT_CTIMEOUT) || \
+                            ((IT)  == SDIO_IT_DTIMEOUT) || \
+                            ((IT)  == SDIO_IT_TXUNDERR) || \
+                            ((IT)  == SDIO_IT_RXOVERR) || \
+                            ((IT)  == SDIO_IT_CMDREND) || \
+                            ((IT)  == SDIO_IT_CMDSENT) || \
+                            ((IT)  == SDIO_IT_DATAEND) || \
+                            ((IT)  == SDIO_IT_STBITERR) || \
+                            ((IT)  == SDIO_IT_DBCKEND) || \
+                            ((IT)  == SDIO_IT_CMDACT) || \
+                            ((IT)  == SDIO_IT_TXACT) || \
+                            ((IT)  == SDIO_IT_RXACT) || \
+                            ((IT)  == SDIO_IT_TXFIFOHE) || \
+                            ((IT)  == SDIO_IT_RXFIFOHF) || \
+                            ((IT)  == SDIO_IT_TXFIFOF) || \
+                            ((IT)  == SDIO_IT_RXFIFOF) || \
+                            ((IT)  == SDIO_IT_TXFIFOE) || \
+                            ((IT)  == SDIO_IT_RXFIFOE) || \
+                            ((IT)  == SDIO_IT_TXDAVL) || \
+                            ((IT)  == SDIO_IT_RXDAVL) || \
+                            ((IT)  == SDIO_IT_SDIOIT) || \
+                            ((IT)  == SDIO_IT_CEATAEND))
+
+#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Read_Wait_Mode 
+  * @{
+  */
+
+#define SDIO_ReadWaitMode_CLK               ((uint32_t)0x00000000)
+#define SDIO_ReadWaitMode_DATA2             ((uint32_t)0x00000001)
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
+                                     ((MODE) == SDIO_ReadWaitMode_DATA2))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Functions
+  * @{
+  */
+
+void SDIO_DeInit(void);
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_ClockCmd(FunctionalState NewState);
+void SDIO_SetPowerState(uint32_t SDIO_PowerState);
+uint32_t SDIO_GetPowerState(void);
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
+void SDIO_DMACmd(FunctionalState NewState);
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
+uint8_t SDIO_GetCommandResponse(void);
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+uint32_t SDIO_GetDataCounter(void);
+uint32_t SDIO_ReadData(void);
+void SDIO_WriteData(uint32_t Data);
+uint32_t SDIO_GetFIFOCount(void);
+void SDIO_StartSDIOReadWait(FunctionalState NewState);
+void SDIO_StopSDIOReadWait(FunctionalState NewState);
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
+void SDIO_SetSDIOOperation(FunctionalState NewState);
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
+void SDIO_CommandCompletionCmd(FunctionalState NewState);
+void SDIO_CEATAITCmd(FunctionalState NewState);
+void SDIO_SendCEATACmd(FunctionalState NewState);
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
+void SDIO_ClearFlag(uint32_t SDIO_FLAG);
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
+
+#endif /* __STM32F10x_SDIO_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_spi.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_spi.h
new file mode 100644
index 0000000..98c1477
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_spi.h
@@ -0,0 +1,452 @@
+/**
+  ******************************************************************************
+  * @file  stm32f10x_spi.h
+  * @author  MCD Application Team
+  * @version  V3.0.0
+  * @date  04/06/2009
+  * @brief  This file contains all the functions prototypes for the SPI firmware
+  *         library.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
© COPYRIGHT 2009 STMicroelectronics

+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_SPI_H
+#define __STM32F10x_SPI_H
+
+/* Includes ------------------------------------------------------------------*/
+//#include "stm32f10x.h"
+#include "stm32f10x_map.h"
+
+#define uint16_t unsigned short
+#define uint8_t unsigned char
+#define uint32_t unsigned long
+
+#define RCC_APB1Periph_SPI3	((uint32_t)0x00008000)
+#define SPI3_BASE			(APB1PERIPH_BASE + 0x3C00)
+#define SPI3				((SPI_TypeDef *) SPI3_BASE)
+#define GPIO_Remap_SPI3		( 1UL << 28UL )
+/** @addtogroup StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SPI
+  * @{
+  */
+
+/** @defgroup SPI_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief  SPI Init structure definition
+  */
+
+typedef struct
+{
+  uint16_t SPI_Direction;
+  uint16_t SPI_Mode;
+  uint16_t SPI_DataSize;
+  uint16_t SPI_CPOL;
+  uint16_t SPI_CPHA;
+  uint16_t SPI_NSS;
+  uint16_t SPI_BaudRatePrescaler;
+  uint16_t SPI_FirstBit;
+  uint16_t SPI_CRCPolynomial;
+}SPI_InitTypeDef;
+
+/**
+  * @brief  I2S Init structure definition
+  */
+
+typedef struct
+{
+  uint16_t I2S_Mode;
+  uint16_t I2S_Standard;
+  uint16_t I2S_DataFormat;
+  uint16_t I2S_MCLKOutput;
+  uint16_t I2S_AudioFreq;
+  uint16_t I2S_CPOL;
+}I2S_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Exported_Constants
+  * @{
+  */
+
+#define IS_SPI_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == SPI1_BASE) || \
+                                   ((*(uint32_t*)&(PERIPH)) == SPI2_BASE) || \
+                                   ((*(uint32_t*)&(PERIPH)) == SPI3_BASE))
+#define IS_SPI_23_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == SPI2_BASE) || \
+                                  ((*(uint32_t*)&(PERIPH)) == SPI3_BASE))
+
+/** @defgroup SPI_data_direction_mode
+  * @{
+  */
+
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
+#define SPI_Direction_2Lines_RxOnly     ((uint16_t)0x0400)
+#define SPI_Direction_1Line_Rx          ((uint16_t)0x8000)
+#define SPI_Direction_1Line_Tx          ((uint16_t)0xC000)
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
+                                     ((MODE) == SPI_Direction_2Lines_RxOnly) || \
+                                     ((MODE) == SPI_Direction_1Line_Rx) || \
+                                     ((MODE) == SPI_Direction_1Line_Tx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_master_slave_mode
+  * @{
+  */
+
+#define SPI_Mode_Master                 ((uint16_t)0x0104)
+#define SPI_Mode_Slave                  ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
+                           ((MODE) == SPI_Mode_Slave))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_data_size
+  * @{
+  */
+
+#define SPI_DataSize_16b                ((uint16_t)0x0800)
+#define SPI_DataSize_8b                 ((uint16_t)0x0000)
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
+                                   ((DATASIZE) == SPI_DataSize_8b))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Polarity
+  * @{
+  */
+
+#define SPI_CPOL_Low                    ((uint16_t)0x0000)
+#define SPI_CPOL_High                   ((uint16_t)0x0002)
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
+                           ((CPOL) == SPI_CPOL_High))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Phase
+  * @{
+  */
+
+#define SPI_CPHA_1Edge                  ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge                  ((uint16_t)0x0001)
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
+                           ((CPHA) == SPI_CPHA_2Edge))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Slave_Select_management
+  * @{
+  */
+
+#define SPI_NSS_Soft                    ((uint16_t)0x0200)
+#define SPI_NSS_Hard                    ((uint16_t)0x0000)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
+                         ((NSS) == SPI_NSS_Hard))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_BaudRate_Prescaler_
+  * @{
+  */
+
+#define SPI_BaudRatePrescaler_2         ((uint16_t)0x0000)
+#define SPI_BaudRatePrescaler_4         ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_8         ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_16        ((uint16_t)0x0018)
+#define SPI_BaudRatePrescaler_32        ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64        ((uint16_t)0x0028)
+#define SPI_BaudRatePrescaler_128       ((uint16_t)0x0030)
+#define SPI_BaudRatePrescaler_256       ((uint16_t)0x0038)
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_256))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_MSB_LSB_transmission
+  * @{
+  */
+
+#define SPI_FirstBit_MSB                ((uint16_t)0x0000)
+#define SPI_FirstBit_LSB                ((uint16_t)0x0080)
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
+                               ((BIT) == SPI_FirstBit_LSB))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Mode
+  * @{
+  */
+
+#define I2S_Mode_SlaveTx                ((uint16_t)0x0000)
+#define I2S_Mode_SlaveRx                ((uint16_t)0x0100)
+#define I2S_Mode_MasterTx               ((uint16_t)0x0200)
+#define I2S_Mode_MasterRx               ((uint16_t)0x0300)
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
+                           ((MODE) == I2S_Mode_SlaveRx) || \
+                           ((MODE) == I2S_Mode_MasterTx) || \
+                           ((MODE) == I2S_Mode_MasterRx) )
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Standard
+  * @{
+  */
+
+#define I2S_Standard_Phillips           ((uint16_t)0x0000)
+#define I2S_Standard_MSB                ((uint16_t)0x0010)
+#define I2S_Standard_LSB                ((uint16_t)0x0020)
+#define I2S_Standard_PCMShort           ((uint16_t)0x0030)
+#define I2S_Standard_PCMLong            ((uint16_t)0x00B0)
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
+                                   ((STANDARD) == I2S_Standard_MSB) || \
+                                   ((STANDARD) == I2S_Standard_LSB) || \
+                                   ((STANDARD) == I2S_Standard_PCMShort) || \
+                                   ((STANDARD) == I2S_Standard_PCMLong))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Data_Format
+  * @{
+  */
+
+#define I2S_DataFormat_16b              ((uint16_t)0x0000)
+#define I2S_DataFormat_16bextended      ((uint16_t)0x0001)
+#define I2S_DataFormat_24b              ((uint16_t)0x0003)
+#define I2S_DataFormat_32b              ((uint16_t)0x0005)
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
+                                    ((FORMAT) == I2S_DataFormat_16bextended) || \
+                                    ((FORMAT) == I2S_DataFormat_24b) || \
+                                    ((FORMAT) == I2S_DataFormat_32b))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_MCLK_Output
+  * @{
+  */
+
+#define I2S_MCLKOutput_Enable           ((uint16_t)0x0200)
+#define I2S_MCLKOutput_Disable          ((uint16_t)0x0000)
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
+                                    ((OUTPUT) == I2S_MCLKOutput_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Audio_Frequency
+  * @{
+  */
+
+#define I2S_AudioFreq_48k                ((uint16_t)48000)
+#define I2S_AudioFreq_44k                ((uint16_t)44100)
+#define I2S_AudioFreq_22k                ((uint16_t)22050)
+#define I2S_AudioFreq_16k                ((uint16_t)16000)
+#define I2S_AudioFreq_8k                 ((uint16_t)8000)
+#define I2S_AudioFreq_Default            ((uint16_t)2)
+#define IS_I2S_AUDIO_FREQ(FREQ) (((FREQ) == I2S_AudioFreq_48k) || \
+                                 ((FREQ) == I2S_AudioFreq_44k) || \
+                                 ((FREQ) == I2S_AudioFreq_22k) || \
+                                 ((FREQ) == I2S_AudioFreq_16k) || \
+                                 ((FREQ) == I2S_AudioFreq_8k)  || \
+                                 ((FREQ) == I2S_AudioFreq_Default))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Clock_Polarity
+  * @{
+  */
+
+#define I2S_CPOL_Low                    ((uint16_t)0x0000)
+#define I2S_CPOL_High                   ((uint16_t)0x0008)
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
+                           ((CPOL) == I2S_CPOL_High))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_DMA_transfer_requests
+  * @{
+  */
+
+#define SPI_I2S_DMAReq_Tx               ((uint16_t)0x0002)
+#define SPI_I2S_DMAReq_Rx               ((uint16_t)0x0001)
+#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_NSS_internal_software_mangement
+  * @{
+  */
+
+#define SPI_NSSInternalSoft_Set         ((uint16_t)0x0100)
+#define SPI_NSSInternalSoft_Reset       ((uint16_t)0xFEFF)
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
+                                       ((INTERNAL) == SPI_NSSInternalSoft_Reset))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_Transmit_Receive
+  * @{
+  */
+
+#define SPI_CRC_Tx                      ((uint8_t)0x00)
+#define SPI_CRC_Rx                      ((uint8_t)0x01)
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_direction_transmit_receive
+  * @{
+  */
+
+#define SPI_Direction_Rx                ((uint16_t)0xBFFF)
+#define SPI_Direction_Tx                ((uint16_t)0x4000)
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
+                                     ((DIRECTION) == SPI_Direction_Tx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_interrupts_definition
+  * @{
+  */
+
+#define SPI_I2S_IT_TXE                  ((uint8_t)0x71)
+#define SPI_I2S_IT_RXNE                 ((uint8_t)0x60)
+#define SPI_I2S_IT_ERR                  ((uint8_t)0x50)
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
+                                 ((IT) == SPI_I2S_IT_RXNE) || \
+                                 ((IT) == SPI_I2S_IT_ERR))
+#define SPI_I2S_IT_OVR                  ((uint8_t)0x56)
+#define SPI_IT_MODF                     ((uint8_t)0x55)
+#define SPI_IT_CRCERR                   ((uint8_t)0x54)
+#define I2S_IT_UDR                      ((uint8_t)0x53)
+#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
+                               ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \
+                               ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_flags_definition
+  * @{
+  */
+
+#define SPI_I2S_FLAG_RXNE               ((uint16_t)0x0001)
+#define SPI_I2S_FLAG_TXE                ((uint16_t)0x0002)
+#define I2S_FLAG_CHSIDE                 ((uint16_t)0x0004)
+#define I2S_FLAG_UDR                    ((uint16_t)0x0008)
+#define SPI_FLAG_CRCERR                 ((uint16_t)0x0010)
+#define SPI_FLAG_MODF                   ((uint16_t)0x0020)
+#define SPI_I2S_FLAG_OVR                ((uint16_t)0x0040)
+#define SPI_I2S_FLAG_BSY                ((uint16_t)0x0080)
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
+                                   ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
+                                   ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
+                                   ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_polynomial
+  * @{
+  */
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Exported_Functions
+  * @{
+  */
+
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+#endif /*__STM32F10x_SPI_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_systick.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_systick.h
new file mode 100644
index 0000000..7060805
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_systick.h
@@ -0,0 +1,68 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_systick.h
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file contains all the functions prototypes for the
+*                      SysTick firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_SYSTICK_H
+#define __STM32F10x_SYSTICK_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* SysTick clock source */
+#define SysTick_CLKSource_HCLK_Div8    ((u32)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK         ((u32)0x00000004)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) ((SOURCE == SysTick_CLKSource_HCLK) || \
+                                       (SOURCE == SysTick_CLKSource_HCLK_Div8))
+
+/* SysTick counter state */
+#define SysTick_Counter_Disable        ((u32)0xFFFFFFFE)
+#define SysTick_Counter_Enable         ((u32)0x00000001)
+#define SysTick_Counter_Clear          ((u32)0x00000000)
+
+#define IS_SYSTICK_COUNTER(COUNTER) ((COUNTER == SysTick_Counter_Disable) || \
+                                     (COUNTER == SysTick_Counter_Enable)  || \
+                                     (COUNTER == SysTick_Counter_Clear))
+
+/* SysTick Flag */
+#define SysTick_FLAG_COUNT             ((u8)0x30)
+#define SysTick_FLAG_SKEW              ((u8)0x5E)
+#define SysTick_FLAG_NOREF             ((u8)0x5F)
+
+#define IS_SYSTICK_FLAG(FLAG) ((FLAG == SysTick_FLAG_COUNT) || \
+                               (FLAG == SysTick_FLAG_SKEW)  || \
+                               (FLAG == SysTick_FLAG_NOREF))
+
+#define IS_SYSTICK_RELOAD(RELOAD) ((RELOAD > 0) || (RELOAD <= 0xFFFFFF))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void SysTick_CLKSourceConfig(u32 SysTick_CLKSource);
+void SysTick_SetReload(u32 Reload);
+void SysTick_CounterCmd(u32 SysTick_Counter);
+void SysTick_ITConfig(FunctionalState NewState);
+u32 SysTick_GetCounter(void);
+FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG);
+
+#endif /* __STM32F10x_SYSTICK_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_tim.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_tim.h
new file mode 100644
index 0000000..12f8378
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_tim.h
@@ -0,0 +1,513 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_tim.h
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file contains all the functions prototypes for the 
+*                      TIM firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_TIM_H
+#define __STM32F10x_TIM_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+
+/* TIM Base Init structure definition */
+typedef struct
+{
+  u16 TIM_Period;          /* Period value */
+  u16 TIM_Prescaler;       /* Prescaler value */
+  u16 TIM_ClockDivision;   /* Timer clock division */
+  u16 TIM_CounterMode;     /* Timer Counter mode */
+} TIM_TimeBaseInitTypeDef;
+
+/* TIM Output Compare Init structure definition */
+typedef struct
+{
+  u16 TIM_OCMode;          /* Timer Output Compare Mode */
+  u16 TIM_Channel;          /* Timer Channel */
+  u16 TIM_Pulse;           /* PWM or OC Channel pulse length */
+  u16 TIM_OCPolarity;       /* PWM, OCM or OPM Channel polarity */
+} TIM_OCInitTypeDef;
+
+/* TIM Input Capture Init structure definition */
+typedef struct
+{
+  u16 TIM_ICMode;            /* Timer Input Capture Mode */
+  u16 TIM_Channel;           /* Timer Channel */
+  u16 TIM_ICPolarity;        /* Input Capture polarity */ 
+  u16 TIM_ICSelection;       /* Input Capture selection */
+  u16 TIM_ICPrescaler;       /* Input Capture prescaler */
+  u8 TIM_ICFilter;          /* Input Capture filter */
+} TIM_ICInitTypeDef;
+
+/* Exported constants -------------------------------------------------------*/
+/* TIM Ouput Compare modes --------------------------------------------------*/
+#define TIM_OCMode_Timing                 ((u16)0x0000)
+#define TIM_OCMode_Active                 ((u16)0x0010)
+#define TIM_OCMode_Inactive               ((u16)0x0020)
+#define TIM_OCMode_Toggle                 ((u16)0x0030)
+#define TIM_OCMode_PWM1                   ((u16)0x0060)
+#define TIM_OCMode_PWM2                   ((u16)0x0070)
+
+#define IS_TIM_OC_MODE(MODE) ((MODE == TIM_OCMode_Timing) || \
+                              (MODE == TIM_OCMode_Active) || \
+                              (MODE == TIM_OCMode_Inactive) || \
+                              (MODE == TIM_OCMode_Toggle)|| \
+                              (MODE == TIM_OCMode_PWM1) || \
+                              (MODE == TIM_OCMode_PWM2))
+
+/* TIM Input Capture modes --------------------------------------------------*/
+#define TIM_ICMode_ICAP                   ((u16)0x0007)
+#define TIM_ICMode_PWMI                   ((u16)0x0006)
+
+#define IS_TIM_IC_MODE(MODE) ((MODE == TIM_ICMode_ICAP) || \
+                              (MODE == TIM_ICMode_PWMI))
+
+/* TIM One Pulse Mode -------------------------------------------------------*/
+#define TIM_OPMode_Single                 ((u16)0x0008)
+#define TIM_OPMode_Repetitive             ((u16)0x0000)
+
+#define IS_TIM_OPM_MODE(MODE) ((MODE == TIM_OPMode_Single) || \
+                               (MODE == TIM_OPMode_Repetitive))
+                             
+/* TIM Channel --------------------------------------------------------------*/
+#define TIM_Channel_1                     ((u16)0x0000)
+#define TIM_Channel_2                     ((u16)0x0001)
+#define TIM_Channel_3                     ((u16)0x0002)
+#define TIM_Channel_4                     ((u16)0x0003)
+
+#define IS_TIM_CHANNEL(CHANNEL) ((CHANNEL == TIM_Channel_1) || \
+                                 (CHANNEL == TIM_Channel_2) || \
+                                 (CHANNEL == TIM_Channel_3) || \
+                                 (CHANNEL == TIM_Channel_4))
+
+/* TIM Clock Division CKD ---------------------------------------------------*/
+#define TIM_CKD_DIV1                      ((u16)0x0000)
+#define TIM_CKD_DIV2                      ((u16)0x0100)
+#define TIM_CKD_DIV4                      ((u16)0x0200)
+
+#define IS_TIM_CKD_DIV(DIV) ((DIV == TIM_CKD_DIV1) || \
+                             (DIV == TIM_CKD_DIV2) || \
+                             (DIV == TIM_CKD_DIV4))
+
+/* TIM Counter Mode ---------------------------------------------------------*/
+#define TIM_CounterMode_Up                ((u16)0x0000)
+#define TIM_CounterMode_Down              ((u16)0x0010)
+#define TIM_CounterMode_CenterAligned1    ((u16)0x0020)
+#define TIM_CounterMode_CenterAligned2    ((u16)0x0040)
+#define TIM_CounterMode_CenterAligned3    ((u16)0x0060)
+
+#define IS_TIM_COUNTER_MODE(MODE) ((MODE == TIM_CounterMode_Up) ||  \
+                                   (MODE == TIM_CounterMode_Down) || \
+                                   (MODE == TIM_CounterMode_CenterAligned1) || \
+                                   (MODE == TIM_CounterMode_CenterAligned2) || \
+                                   (MODE == TIM_CounterMode_CenterAligned3))
+
+/* TIM Output Compare Polarity ----------------------------------------------*/
+#define TIM_OCPolarity_High               ((u16)0x0000)
+#define TIM_OCPolarity_Low                ((u16)0x0002)
+
+#define IS_TIM_OC_POLARITY(POLARITY) ((POLARITY == TIM_OCPolarity_High) || \
+                                     (POLARITY == TIM_OCPolarity_Low))
+
+/* TIM Input Capture Polarity -----------------------------------------------*/
+#define  TIM_ICPolarity_Rising            ((u16)0x0000)
+#define  TIM_ICPolarity_Falling           ((u16)0x0002)
+
+#define IS_TIM_IC_POLARITY(POLARITY) ((POLARITY == TIM_ICPolarity_Rising) || \
+                                     (POLARITY == TIM_ICPolarity_Falling))
+
+/* TIM Input Capture Channel  Selection -------------------------------------*/
+#define TIM_ICSelection_DirectTI          ((u16)0x0001)
+#define TIM_ICSelection_IndirectTI        ((u16)0x0002)
+#define TIM_ICSelection_TRGI              ((u16)0x0003)
+
+#define IS_TIM_IC_SELECTION(SELECTION) ((SELECTION == TIM_ICSelection_DirectTI) || \
+                                       (SELECTION == TIM_ICSelection_IndirectTI) || \
+                                       (SELECTION == TIM_ICSelection_TRGI))
+
+/* TIM Input Capture Prescaler ----------------------------------------------*/
+#define TIM_ICPSC_DIV1                    ((u16)0x0000)
+#define TIM_ICPSC_DIV2                    ((u16)0x0004)
+#define TIM_ICPSC_DIV4                    ((u16)0x0008)
+#define TIM_ICPSC_DIV8                    ((u16)0x000C)
+
+#define IS_TIM_IC_PRESCALER(PRESCALER) ((PRESCALER == TIM_ICPSC_DIV1) || \
+                                       (PRESCALER == TIM_ICPSC_DIV2) || \
+                                       (PRESCALER == TIM_ICPSC_DIV4) || \
+                                       (PRESCALER == TIM_ICPSC_DIV8))
+
+/* TIM Input Capture Filer Value ---------------------------------------------*/
+#define IS_TIM_IC_FILTER(ICFILTER) (ICFILTER <= 0xF)                                      
+
+/* TIM interrupt sources ----------------------------------------------------*/
+#define TIM_IT_Update                     ((u16)0x0001)
+#define TIM_IT_CC1                        ((u16)0x0002)
+#define TIM_IT_CC2                        ((u16)0x0004)
+#define TIM_IT_CC3                        ((u16)0x0008)
+#define TIM_IT_CC4                        ((u16)0x0010)
+#define TIM_IT_Trigger                    ((u16)0x0040)
+
+#define IS_TIM_IT(IT) (((IT & (u16)0xFFA0) == 0x0000) && (IT != 0x0000))
+
+#define IS_TIM_GET_IT(IT) ((IT == TIM_IT_Update) || \
+                           (IT == TIM_IT_CC1) || \
+                           (IT == TIM_IT_CC2) || \
+                           (IT == TIM_IT_CC3) || \
+                           (IT == TIM_IT_CC4) || \
+                           (IT == TIM_IT_Trigger))
+
+/* TIM DMA Base address -----------------------------------------------------*/
+#define TIM_DMABase_CR1                   ((u16)0x0000)
+#define TIM_DMABase_CR2                   ((u16)0x0001)
+#define TIM_DMABase_SMCR                  ((u16)0x0002)
+#define TIM_DMABase_DIER                  ((u16)0x0003)
+#define TIM_DMABase_SR                    ((u16)0x0004)
+#define TIM_DMABase_EGR                   ((u16)0x0005)
+#define TIM_DMABase_CCMR1                 ((u16)0x0006)
+#define TIM_DMABase_CCMR2                 ((u16)0x0007)
+#define TIM_DMABase_CCER                  ((u16)0x0008)
+#define TIM_DMABase_CNT                   ((u16)0x0009)
+#define TIM_DMABase_PSC                   ((u16)0x000A)
+#define TIM_DMABase_ARR                   ((u16)0x000B)
+#define TIM_DMABase_CCR1                  ((u16)0x000D)
+#define TIM_DMABase_CCR2                  ((u16)0x000E)
+#define TIM_DMABase_CCR3                  ((u16)0x000F)
+#define TIM_DMABase_CCR4                  ((u16)0x0010)
+#define TIM_DMABase_DCR                   ((u16)0x0012)
+
+#define IS_TIM_DMA_BASE(BASE) ((BASE == TIM_DMABase_CR1) || \
+                               (BASE == TIM_DMABase_CR2) || \
+                               (BASE == TIM_DMABase_SMCR) || \
+                               (BASE == TIM_DMABase_DIER) || \
+                               (BASE == TIM_DMABase_SR) || \
+                               (BASE == TIM_DMABase_EGR) || \
+                               (BASE == TIM_DMABase_CCMR1) || \
+                               (BASE == TIM_DMABase_CCMR2) || \
+                               (BASE == TIM_DMABase_CCER) || \
+                               (BASE == TIM_DMABase_CNT) || \
+                               (BASE == TIM_DMABase_PSC) || \
+                               (BASE == TIM_DMABase_ARR) || \
+                               (BASE == TIM_DMABase_CCR1) || \
+                               (BASE == TIM_DMABase_CCR2) || \
+                               (BASE == TIM_DMABase_CCR3) || \
+                               (BASE == TIM_DMABase_CCR4) || \
+                               (BASE == TIM_DMABase_DCR))
+
+/* TIM DMA Burst Length -----------------------------------------------------*/
+#define TIM_DMABurstLength_1Byte          ((u16)0x0000)
+#define TIM_DMABurstLength_2Bytes         ((u16)0x0100)
+#define TIM_DMABurstLength_3Bytes         ((u16)0x0200)
+#define TIM_DMABurstLength_4Bytes         ((u16)0x0300)
+#define TIM_DMABurstLength_5Bytes         ((u16)0x0400)
+#define TIM_DMABurstLength_6Bytes         ((u16)0x0500)
+#define TIM_DMABurstLength_7Bytes         ((u16)0x0600)
+#define TIM_DMABurstLength_8Bytes         ((u16)0x0700)
+#define TIM_DMABurstLength_9Bytes         ((u16)0x0800)
+#define TIM_DMABurstLength_10Bytes        ((u16)0x0900)
+#define TIM_DMABurstLength_11Bytes        ((u16)0x0A00)
+#define TIM_DMABurstLength_12Bytes        ((u16)0x0B00)
+#define TIM_DMABurstLength_13Bytes        ((u16)0x0C00)
+#define TIM_DMABurstLength_14Bytes        ((u16)0x0D00)
+#define TIM_DMABurstLength_15Bytes        ((u16)0x0E00)
+#define TIM_DMABurstLength_16Bytes        ((u16)0x0F00)
+#define TIM_DMABurstLength_17Bytes        ((u16)0x1000)
+#define TIM_DMABurstLength_18Bytes        ((u16)0x1100)
+
+#define IS_TIM_DMA_LENGTH(LENGTH) ((LENGTH == TIM_DMABurstLength_1Byte) || \
+                                   (LENGTH == TIM_DMABurstLength_2Bytes) || \
+                                   (LENGTH == TIM_DMABurstLength_3Bytes) || \
+                                   (LENGTH == TIM_DMABurstLength_4Bytes) || \
+                                   (LENGTH == TIM_DMABurstLength_5Bytes) || \
+                                   (LENGTH == TIM_DMABurstLength_6Bytes) || \
+                                   (LENGTH == TIM_DMABurstLength_7Bytes) || \
+                                   (LENGTH == TIM_DMABurstLength_8Bytes) || \
+                                   (LENGTH == TIM_DMABurstLength_9Bytes) || \
+                                   (LENGTH == TIM_DMABurstLength_10Bytes) || \
+                                   (LENGTH == TIM_DMABurstLength_11Bytes) || \
+                                   (LENGTH == TIM_DMABurstLength_12Bytes) || \
+                                   (LENGTH == TIM_DMABurstLength_13Bytes) || \
+                                   (LENGTH == TIM_DMABurstLength_14Bytes) || \
+                                   (LENGTH == TIM_DMABurstLength_15Bytes) || \
+                                   (LENGTH == TIM_DMABurstLength_16Bytes) || \
+                                   (LENGTH == TIM_DMABurstLength_17Bytes) || \
+                                   (LENGTH == TIM_DMABurstLength_18Bytes))
+                                                        
+/* TIM DMA sources ----------------------------------------------------------*/
+#define TIM_DMA_Update                    ((u16)0x0100)
+#define TIM_DMA_CC1                       ((u16)0x0200)
+#define TIM_DMA_CC2                       ((u16)0x0400)
+#define TIM_DMA_CC3                       ((u16)0x0800)
+#define TIM_DMA_CC4                       ((u16)0x1000)
+#define TIM_DMA_Trigger                   ((u16)0x4000)
+
+#define IS_TIM_DMA_SOURCE(SOURCE) (((SOURCE & (u16)0xA0FF) == 0x0000) && (SOURCE != 0x0000))
+
+/* TIM External Trigger Prescaler -------------------------------------------*/
+#define TIM_ExtTRGPSC_OFF                 ((u16)0x0000)
+#define TIM_ExtTRGPSC_DIV2                ((u16)0x1000) 
+#define TIM_ExtTRGPSC_DIV4                ((u16)0x2000)
+#define TIM_ExtTRGPSC_DIV8                ((u16)0x3000)
+
+#define IS_TIM_EXT_PRESCALER(PRESCALER) ((PRESCALER == TIM_ExtTRGPSC_OFF) || \
+                                         (PRESCALER == TIM_ExtTRGPSC_DIV2) || \
+                                         (PRESCALER == TIM_ExtTRGPSC_DIV4) || \
+                                         (PRESCALER == TIM_ExtTRGPSC_DIV8))
+
+/* TIM Input Trigger Selection ---------------------------------------------*/
+#define TIM_TS_ITR0                       ((u16)0x0000)
+#define TIM_TS_ITR1                       ((u16)0x0010)
+#define TIM_TS_ITR2                       ((u16)0x0020)
+#define TIM_TS_ITR3                       ((u16)0x0030)
+#define TIM_TS_TI1F_ED                    ((u16)0x0040)
+#define TIM_TS_TI1FP1                     ((u16)0x0050)
+#define TIM_TS_TI2FP2                     ((u16)0x0060)
+#define TIM_TS_ETRF                       ((u16)0x0070)
+
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM_TS_ITR0) || \
+                                             (SELECTION == TIM_TS_ITR1) || \
+                                             (SELECTION == TIM_TS_ITR2) || \
+                                             (SELECTION == TIM_TS_ITR3) || \
+                                             (SELECTION == TIM_TS_TI1F_ED) || \
+                                             (SELECTION == TIM_TS_TI1FP1) || \
+                                             (SELECTION == TIM_TS_TI2FP2) || \
+                                             (SELECTION == TIM_TS_ETRF))
+
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM_TS_ITR0) || \
+                                                      (SELECTION == TIM_TS_ITR1) || \
+                                                      (SELECTION == TIM_TS_ITR2) || \
+                                                      (SELECTION == TIM_TS_ITR3))
+
+#define IS_TIM_TIX_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM_TS_TI1F_ED) || \
+                                                 (SELECTION == TIM_TS_TI1FP1) || \
+                                                 (SELECTION == TIM_TS_TI2FP2))
+
+/* TIM External Trigger Polarity --------------------------------------------*/
+#define TIM_ExtTRGPolarity_Inverted       ((u16)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted    ((u16)0x0000)
+
+#define IS_TIM_EXT_POLARITY(POLARITY) ((POLARITY == TIM_ExtTRGPolarity_Inverted) || \
+                                       (POLARITY == TIM_ExtTRGPolarity_NonInverted)) 
+
+/* TIM Prescaler Reload Mode ------------------------------------------------*/
+#define TIM_PSCReloadMode_Update          ((u16)0x0000)
+#define TIM_PSCReloadMode_Immediate       ((u16)0x0001)
+
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) ((RELOAD == TIM_PSCReloadMode_Update) || \
+                                         (RELOAD == TIM_PSCReloadMode_Immediate))
+
+/* TIM Forced Action --------------------------------------------------------*/
+#define TIM_ForcedAction_Active           ((u16)0x0050)
+#define TIM_ForcedAction_InActive         ((u16)0x0040)
+
+#define IS_TIM_FORCED_ACTION(ACTION) ((ACTION == TIM_ForcedAction_Active) || \
+                                      (ACTION == TIM_ForcedAction_InActive))
+
+/* TIM Encoder Mode ---------------------------------------------------------*/ 
+#define TIM_EncoderMode_TI1               ((u16)0x0001)
+#define TIM_EncoderMode_TI2               ((u16)0x0002)
+#define TIM_EncoderMode_TI12              ((u16)0x0003)
+
+#define IS_TIM_ENCODER_MODE(MODE) ((MODE == TIM_EncoderMode_TI1) || \
+                                   (MODE == TIM_EncoderMode_TI2) || \
+                                   (MODE == TIM_EncoderMode_TI12))
+
+/* TIM Event Source ---------------------------------------------------------*/
+#define TIM_EventSource_Update            ((u16)0x0001)
+#define TIM_EventSource_CC1               ((u16)0x0002)
+#define TIM_EventSource_CC2               ((u16)0x0004)
+#define TIM_EventSource_CC3               ((u16)0x0008)
+#define TIM_EventSource_CC4               ((u16)0x0010)
+#define TIM_EventSource_Trigger           ((u16)0x0040)
+
+#define IS_TIM_EVENT_SOURCE(SOURCE) (((SOURCE & (u16)0xFFA0) == 0x0000) && (SOURCE != 0x0000))
+                                     
+
+/* TIM Update Source --------------------------------------------------------*/
+#define TIM_UpdateSource_Global           ((u16)0x0000)
+#define TIM_UpdateSource_Regular          ((u16)0x0001)
+
+#define IS_TIM_UPDATE_SOURCE(SOURCE) ((SOURCE == TIM_UpdateSource_Global) || \
+                                      (SOURCE == TIM_UpdateSource_Regular))
+
+/* TIM Ouput Compare Preload State ------------------------------------------*/
+#define TIM_OCPreload_Enable              ((u16)0x0008)
+#define TIM_OCPreload_Disable             ((u16)0x0000)
+
+#define IS_TIM_OCPRELOAD_STATE(STATE) ((STATE == TIM_OCPreload_Enable) || \
+                                       (STATE == TIM_OCPreload_Disable))
+
+/* TIM Ouput Compare Fast State ---------------------------------------------*/
+#define TIM_OCFast_Enable                 ((u16)0x0004)
+#define TIM_OCFast_Disable                ((u16)0x0000)
+
+#define IS_TIM_OCFAST_STATE(STATE) ((STATE == TIM_OCFast_Enable) || \
+                                    (STATE == TIM_OCFast_Disable))
+
+/* TIM Trigger Output Source ------------------------------------------------*/ 
+#define TIM_TRGOSource_Reset              ((u16)0x0000)
+#define TIM_TRGOSource_Enable             ((u16)0x0010)
+#define TIM_TRGOSource_Update             ((u16)0x0020)
+#define TIM_TRGOSource_OC1                ((u16)0x0030)
+#define TIM_TRGOSource_OC1Ref             ((u16)0x0040)
+#define TIM_TRGOSource_OC2Ref             ((u16)0x0050)
+#define TIM_TRGOSource_OC3Ref             ((u16)0x0060)
+#define TIM_TRGOSource_OC4Ref             ((u16)0x0070)
+
+#define IS_TIM_TRGO_SOURCE(SOURCE) ((SOURCE == TIM_TRGOSource_Reset) || \
+                                    (SOURCE == TIM_TRGOSource_Enable) || \
+                                    (SOURCE == TIM_TRGOSource_Update) || \
+                                    (SOURCE == TIM_TRGOSource_OC1) || \
+                                    (SOURCE == TIM_TRGOSource_OC1Ref) || \
+                                    (SOURCE == TIM_TRGOSource_OC2Ref) || \
+                                    (SOURCE == TIM_TRGOSource_OC3Ref) || \
+                                    (SOURCE == TIM_TRGOSource_OC4Ref))
+
+/* TIM Slave Mode -----------------------------------------------------------*/
+#define TIM_SlaveMode_Reset               ((u16)0x0004)
+#define TIM_SlaveMode_Gated               ((u16)0x0005)
+#define TIM_SlaveMode_Trigger             ((u16)0x0006)
+#define TIM_SlaveMode_External1           ((u16)0x0007)
+
+
+#define IS_TIM_SLAVE_MODE(MODE) ((MODE == TIM_SlaveMode_Reset) || \
+                                 (MODE == TIM_SlaveMode_Gated) || \
+                                 (MODE == TIM_SlaveMode_Trigger) || \
+                                 (MODE == TIM_SlaveMode_External1))
+
+/* TIM TIx External Clock Source --------------------------------------------*/
+#define TIM_TIxExternalCLK1Source_TI1     ((u16)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2     ((u16)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED   ((u16)0x0040)
+
+#define IS_TIM_TIXCLK_SOURCE(SOURCE) ((SOURCE == TIM_TIxExternalCLK1Source_TI1) || \
+                                      (SOURCE == TIM_TIxExternalCLK1Source_TI2) || \
+                                      (SOURCE == TIM_TIxExternalCLK1Source_TI1ED))
+
+
+/* TIM Master Slave Mode ----------------------------------------------------*/
+#define TIM_MasterSlaveMode_Enable        ((u16)0x0080)
+#define TIM_MasterSlaveMode_Disable       ((u16)0x0000)
+
+#define IS_TIM_MSM_STATE(STATE) ((STATE == TIM_MasterSlaveMode_Enable) || \
+                                 (STATE == TIM_MasterSlaveMode_Disable))
+
+/* TIM Flags ----------------------------------------------------------------*/
+#define TIM_FLAG_Update                   ((u16)0x0001)
+#define TIM_FLAG_CC1                      ((u16)0x0002)
+#define TIM_FLAG_CC2                      ((u16)0x0004)
+#define TIM_FLAG_CC3                      ((u16)0x0008)
+#define TIM_FLAG_CC4                      ((u16)0x0010)
+#define TIM_FLAG_Trigger                  ((u16)0x0040)
+#define TIM_FLAG_CC1OF                    ((u16)0x0200)
+#define TIM_FLAG_CC2OF                    ((u16)0x0400)
+#define TIM_FLAG_CC3OF                    ((u16)0x0800)
+#define TIM_FLAG_CC4OF                    ((u16)0x1000)
+
+#define IS_TIM_GET_FLAG(FLAG) ((FLAG == TIM_FLAG_Update) || \
+                               (FLAG == TIM_FLAG_CC1) || \
+                               (FLAG == TIM_FLAG_CC2) || \
+                               (FLAG == TIM_FLAG_CC3) || \
+                               (FLAG == TIM_FLAG_CC4) || \
+                               (FLAG == TIM_FLAG_Trigger) || \
+                               (FLAG == TIM_FLAG_CC1OF) || \
+                               (FLAG == TIM_FLAG_CC2OF) || \
+                               (FLAG == TIM_FLAG_CC3OF) || \
+                               (FLAG == TIM_FLAG_CC4OF))
+
+#define IS_TIM_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xE1A0) == 0x0000) && (FLAG != 0x0000)) 
+                                 
+
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+void TIM_DeInit(TIM_TypeDef* TIMx);
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_OCInit(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_ITConfig(TIM_TypeDef* TIMx, u16 TIM_IT, FunctionalState NewState);
+void TIM_DMAConfig(TIM_TypeDef* TIMx, u16 TIM_DMABase, u16 TIM_DMABurstLength);
+void TIM_DMACmd(TIM_TypeDef* TIMx, u16 TIM_DMASource, FunctionalState Newstate);
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource);
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_TIxExternalCLKSource, 
+                                u16 TIM_ICPolarity, u8 ICFilter);
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity, 
+                             u8 ExtTRGFilter);
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity, 
+                             u8 ExtTRGFilter);
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource);
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, u16 Prescaler, u16 TIM_PSCReloadMode);
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode);
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState Newstate);
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState Newstate);
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState Newstate);
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u16 TIM_EncoderMode, 
+                                u16 TIM_IC1Polarity, u16 TIM_IC2Polarity);
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, u16 TIM_EventSource);
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);  
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, u16 TIM_UpdateSource);
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState Newstate);
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, u16 TIM_OPMode);
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, u16 TIM_TRGOSource);
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, u16 TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, u16 TIM_MasterSlaveMode);
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, u16 Autoreload);
+void TIM_SetCompare1(TIM_TypeDef* TIMx, u16 Compare1);
+void TIM_SetCompare2(TIM_TypeDef* TIMx, u16 Compare2);
+void TIM_SetCompare3(TIM_TypeDef* TIMx, u16 Compare3);
+void TIM_SetCompare4(TIM_TypeDef* TIMx, u16 Compare4);
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC1Prescaler);
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC2Prescaler);
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC3Prescaler);
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC4Prescaler);
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, u16 TIM_CKD);
+u16 TIM_GetCapture1(TIM_TypeDef* TIMx);
+u16 TIM_GetCapture2(TIM_TypeDef* TIMx);
+u16 TIM_GetCapture3(TIM_TypeDef* TIMx);
+u16 TIM_GetCapture4(TIM_TypeDef* TIMx);
+u16 TIM_GetCounter(TIM_TypeDef* TIMx);
+u16 TIM_GetPrescaler(TIM_TypeDef* TIMx);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG); 
+void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG);
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT);
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT);
+
+#endif /*__STM32F10x_TIM_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_tim1.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_tim1.h
new file mode 100644
index 0000000..b83761d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_tim1.h
@@ -0,0 +1,644 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_tim1.h
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file contains all the functions prototypes for the 
+*                      TIM1 firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* mm/dd/yyyy: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_TIM1_H
+#define __STM32F10x_TIM1_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+
+/* TIM1 Time Base Init structure definition */
+typedef struct
+{
+  u16 TIM1_Prescaler;
+  u16 TIM1_CounterMode;
+  u16 TIM1_Period;
+  u16 TIM1_ClockDivision;
+  u8 TIM1_RepetitionCounter;
+} TIM1_TimeBaseInitTypeDef;
+
+/* TIM1 Output Compare Init structure definition */
+typedef struct
+{
+  u16 TIM1_OCMode;
+  u16 TIM1_OutputState;
+  u16 TIM1_OutputNState;
+  u16 TIM1_Pulse;
+  u16 TIM1_OCPolarity;
+  u16 TIM1_OCNPolarity;
+  u16 TIM1_OCIdleState;
+  u16 TIM1_OCNIdleState;
+} TIM1_OCInitTypeDef;
+
+/* TIM1 Input Capture Init structure definition */
+typedef struct
+{
+  u16 TIM1_Channel;
+  u16 TIM1_ICPolarity;
+  u16 TIM1_ICSelection;
+  u16 TIM1_ICPrescaler;
+  u8 TIM1_ICFilter;
+} TIM1_ICInitTypeDef;
+
+/* BDTR structure definition */
+typedef struct
+{
+  u16 TIM1_OSSRState;
+  u16 TIM1_OSSIState;
+  u16 TIM1_LOCKLevel; 
+  u16 TIM1_DeadTime;
+  u16 TIM1_Break;
+  u16 TIM1_BreakPolarity;
+  u16 TIM1_AutomaticOutput;
+} TIM1_BDTRInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* TIM1 Output Compare and PWM modes ----------------------------------------*/
+#define TIM1_OCMode_Timing                 ((u16)0x0000)
+#define TIM1_OCMode_Active                 ((u16)0x0010)
+#define TIM1_OCMode_Inactive               ((u16)0x0020)
+#define TIM1_OCMode_Toggle                 ((u16)0x0030)
+#define TIM1_OCMode_PWM1                   ((u16)0x0060)
+#define TIM1_OCMode_PWM2                   ((u16)0x0070)
+
+#define IS_TIM1_OC_MODE(MODE) ((MODE == TIM1_OCMode_Timing) || \
+                               (MODE == TIM1_OCMode_Active) || \
+                               (MODE == TIM1_OCMode_Inactive) || \
+                               (MODE == TIM1_OCMode_Toggle)|| \
+                               (MODE == TIM1_OCMode_PWM1) || \
+                               (MODE == TIM1_OCMode_PWM2))
+
+#define IS_TIM1_OCM(MODE)((MODE == TIM1_OCMode_Timing) || \
+                          (MODE == TIM1_OCMode_Active) || \
+                          (MODE == TIM1_OCMode_Inactive) || \
+                          (MODE == TIM1_OCMode_Toggle)|| \
+                          (MODE == TIM1_OCMode_PWM1) || \
+                          (MODE == TIM1_OCMode_PWM2) ||	\
+                          (MODE == TIM1_ForcedAction_Active) || \
+                          (MODE == TIM1_ForcedAction_InActive))
+/* TIM1 One Pulse Mode ------------------------------------------------------*/
+#define TIM1_OPMode_Single                 ((u16)0x0001)
+#define TIM1_OPMode_Repetitive             ((u16)0x0000)
+
+#define IS_TIM1_OPM_MODE(MODE) ((MODE == TIM1_OPMode_Single) || \
+                                (MODE == TIM1_OPMode_Repetitive))
+
+/* TIM1 Channel -------------------------------------------------------------*/
+#define TIM1_Channel_1                     ((u16)0x0000)
+#define TIM1_Channel_2                     ((u16)0x0001)
+#define TIM1_Channel_3                     ((u16)0x0002)
+#define TIM1_Channel_4                     ((u16)0x0003)
+
+#define IS_TIM1_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \
+                                  (CHANNEL == TIM1_Channel_2) || \
+                                  (CHANNEL == TIM1_Channel_3) || \
+                                  (CHANNEL == TIM1_Channel_4))
+
+#define IS_TIM1_PWMI_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \
+                                       (CHANNEL == TIM1_Channel_2))
+
+#define IS_TIM1_COMPLEMENTARY_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \
+                                                (CHANNEL == TIM1_Channel_2) || \
+                                                (CHANNEL == TIM1_Channel_3))
+/* TIM1 Clock Division CKD --------------------------------------------------*/
+#define TIM1_CKD_DIV1                      ((u16)0x0000)
+#define TIM1_CKD_DIV2                      ((u16)0x0100)
+#define TIM1_CKD_DIV4                      ((u16)0x0200)
+
+#define IS_TIM1_CKD_DIV(DIV) ((DIV == TIM1_CKD_DIV1) || \
+                              (DIV == TIM1_CKD_DIV2) || \
+                              (DIV == TIM1_CKD_DIV4))
+
+/* TIM1 Counter Mode --------------------------------------------------------*/
+#define TIM1_CounterMode_Up                ((u16)0x0000)
+#define TIM1_CounterMode_Down              ((u16)0x0010)
+#define TIM1_CounterMode_CenterAligned1    ((u16)0x0020)
+#define TIM1_CounterMode_CenterAligned2    ((u16)0x0040)
+#define TIM1_CounterMode_CenterAligned3    ((u16)0x0060)
+
+#define IS_TIM1_COUNTER_MODE(MODE) ((MODE == TIM1_CounterMode_Up) ||  \
+                                    (MODE == TIM1_CounterMode_Down) || \
+                                    (MODE == TIM1_CounterMode_CenterAligned1) || \
+                                    (MODE == TIM1_CounterMode_CenterAligned2) || \
+                                    (MODE == TIM1_CounterMode_CenterAligned3))
+
+/* TIM1 Output Compare Polarity ---------------------------------------------*/
+#define TIM1_OCPolarity_High               ((u16)0x0000)
+#define TIM1_OCPolarity_Low                ((u16)0x0001)
+
+#define IS_TIM1_OC_POLARITY(POLARITY) ((POLARITY == TIM1_OCPolarity_High) || \
+                                       (POLARITY == TIM1_OCPolarity_Low))
+
+/* TIM1 Output Compare N Polarity -------------------------------------------*/
+#define TIM1_OCNPolarity_High              ((u16)0x0000)
+#define TIM1_OCNPolarity_Low               ((u16)0x0001)
+
+#define IS_TIM1_OCN_POLARITY(POLARITY) ((POLARITY == TIM1_OCNPolarity_High) || \
+                                        (POLARITY == TIM1_OCNPolarity_Low))
+
+/* TIM1 Output Compare states -----------------------------------------------*/
+#define TIM1_OutputState_Disable           ((u16)0x0000)
+#define TIM1_OutputState_Enable            ((u16)0x0001)
+
+#define IS_TIM1_OUTPUT_STATE(STATE) ((STATE == TIM1_OutputState_Disable) || \
+                                     (STATE == TIM1_OutputState_Enable))
+
+/* TIM1 Output Compare N States ---------------------------------------------*/
+#define TIM1_OutputNState_Disable          ((u16)0x0000)
+#define TIM1_OutputNState_Enable           ((u16)0x0001)
+
+#define IS_TIM1_OUTPUTN_STATE(STATE) ((STATE == TIM1_OutputNState_Disable) || \
+                                      (STATE == TIM1_OutputNState_Enable))
+
+/* Break Input enable/disable -----------------------------------------------*/
+#define TIM1_Break_Enable                  ((u16)0x1000)
+#define TIM1_Break_Disable                 ((u16)0x0000)
+
+#define IS_TIM1_BREAK_STATE(STATE) ((STATE == TIM1_Break_Enable) || \
+                                    (STATE == TIM1_Break_Disable))
+
+/* Break Polarity -----------------------------------------------------------*/
+#define TIM1_BreakPolarity_Low             ((u16)0x0000)
+#define TIM1_BreakPolarity_High            ((u16)0x2000)
+
+#define IS_TIM1_BREAK_POLARITY(POLARITY) ((POLARITY == TIM1_BreakPolarity_Low) || \
+                                          (POLARITY == TIM1_BreakPolarity_High))
+
+/* TIM1 AOE Bit Set/Reset ---------------------------------------------------*/
+#define TIM1_AutomaticOutput_Enable        ((u16)0x4000)
+#define TIM1_AutomaticOutput_Disable       ((u16)0x0000)
+
+#define IS_TIM1_AUTOMATIC_OUTPUT_STATE(STATE) ((STATE == TIM1_AutomaticOutput_Enable) || \
+                                               (STATE == TIM1_AutomaticOutput_Disable))
+/* Lock levels --------------------------------------------------------------*/
+#define TIM1_LOCKLevel_OFF                 ((u16)0x0000)
+#define TIM1_LOCKLevel_1                   ((u16)0x0100)
+#define TIM1_LOCKLevel_2                   ((u16)0x0200)
+#define TIM1_LOCKLevel_3                   ((u16)0x0300)
+
+#define IS_TIM1_LOCK_LEVEL(LEVEL) ((LEVEL == TIM1_LOCKLevel_OFF) || \
+                                   (LEVEL == TIM1_LOCKLevel_1) || \
+                                   (LEVEL == TIM1_LOCKLevel_2) || \
+                                   (LEVEL == TIM1_LOCKLevel_3))
+
+/* OSSI: Off-State Selection for Idle mode states ---------------------------*/
+#define TIM1_OSSIState_Enable              ((u16)0x0400)
+#define TIM1_OSSIState_Disable             ((u16)0x0000)
+
+#define IS_TIM1_OSSI_STATE(STATE) ((STATE == TIM1_OSSIState_Enable) || \
+                                   (STATE == TIM1_OSSIState_Disable))
+
+/* OSSR: Off-State Selection for Run mode states ----------------------------*/
+#define TIM1_OSSRState_Enable              ((u16)0x0800)
+#define TIM1_OSSRState_Disable             ((u16)0x0000)
+
+#define IS_TIM1_OSSR_STATE(STATE) ((STATE == TIM1_OSSRState_Enable) || \
+                                   (STATE == TIM1_OSSRState_Disable))
+
+/* TIM1 Output Compare Idle State -------------------------------------------*/
+#define TIM1_OCIdleState_Set               ((u16)0x0001)
+#define TIM1_OCIdleState_Reset             ((u16)0x0000)
+
+#define IS_TIM1_OCIDLE_STATE(STATE) ((STATE == TIM1_OCIdleState_Set) || \
+                                     (STATE == TIM1_OCIdleState_Reset))
+
+/* TIM1 Output Compare N Idle State -----------------------------------------*/
+#define TIM1_OCNIdleState_Set              ((u16)0x0001)
+#define TIM1_OCNIdleState_Reset            ((u16)0x0000)
+
+#define IS_TIM1_OCNIDLE_STATE(STATE) ((STATE == TIM1_OCNIdleState_Set) || \
+                                      (STATE == TIM1_OCNIdleState_Reset))
+
+/* TIM1 Input Capture Polarity ----------------------------------------------*/
+#define  TIM1_ICPolarity_Rising            ((u16)0x0000)
+#define  TIM1_ICPolarity_Falling           ((u16)0x0001)
+
+#define IS_TIM1_IC_POLARITY(POLARITY) ((POLARITY == TIM1_ICPolarity_Rising) || \
+                                       (POLARITY == TIM1_ICPolarity_Falling))
+
+/* TIM1 Input Capture Selection ---------------------------------------------*/
+#define TIM1_ICSelection_DirectTI          ((u16)0x0001)
+#define TIM1_ICSelection_IndirectTI        ((u16)0x0002)
+#define TIM1_ICSelection_TRGI              ((u16)0x0003)
+
+#define IS_TIM1_IC_SELECTION(SELECTION) ((SELECTION == TIM1_ICSelection_DirectTI) || \
+                                         (SELECTION == TIM1_ICSelection_IndirectTI) || \
+                                         (SELECTION == TIM1_ICSelection_TRGI))
+
+/* TIM1 Input Capture Prescaler ---------------------------------------------*/
+#define TIM1_ICPSC_DIV1                    ((u16)0x0000)
+#define TIM1_ICPSC_DIV2                    ((u16)0x0004)
+#define TIM1_ICPSC_DIV4                    ((u16)0x0008)
+#define TIM1_ICPSC_DIV8                    ((u16)0x000C)
+
+#define IS_TIM1_IC_PRESCALER(PRESCALER) ((PRESCALER == TIM1_ICPSC_DIV1) || \
+                                         (PRESCALER == TIM1_ICPSC_DIV2) || \
+                                         (PRESCALER == TIM1_ICPSC_DIV4) || \
+                                         (PRESCALER == TIM1_ICPSC_DIV8))
+                                         
+/* TIM1 Input Capture Filer Value ---------------------------------------------*/
+#define IS_TIM1_IC_FILTER(ICFILTER) (ICFILTER <= 0xF)                                              
+
+/* TIM1 interrupt sources ---------------------------------------------------*/
+#define TIM1_IT_Update                     ((u16)0x0001)
+#define TIM1_IT_CC1                        ((u16)0x0002)
+#define TIM1_IT_CC2                        ((u16)0x0004)
+#define TIM1_IT_CC3                        ((u16)0x0008)
+#define TIM1_IT_CC4                        ((u16)0x0010)
+#define TIM1_IT_COM                        ((u16)0x0020)
+#define TIM1_IT_Trigger                    ((u16)0x0040)
+#define TIM1_IT_Break                      ((u16)0x0080)
+
+#define IS_TIM1_IT(IT) (((IT & (u16)0xFF00) == 0x0000) && (IT != 0x0000))
+
+#define IS_TIM1_GET_IT(IT) ((IT == TIM1_IT_Update) || \
+                            (IT == TIM1_IT_CC1) || \
+                            (IT == TIM1_IT_CC2) || \
+                            (IT == TIM1_IT_CC3) || \
+                            (IT == TIM1_IT_CC4) || \
+                            (IT == TIM1_IT_COM) || \
+                            (IT == TIM1_IT_Trigger) || \
+                            (IT == TIM1_IT_Break))
+
+/* TIM1 DMA Base address ----------------------------------------------------*/
+#define TIM1_DMABase_CR1                   ((u16)0x0000)
+#define TIM1_DMABase_CR2                   ((u16)0x0001)
+#define TIM1_DMABase_SMCR                  ((u16)0x0002)
+#define TIM1_DMABase_DIER                  ((u16)0x0003)
+#define TIM1_DMABase_SR                    ((u16)0x0004)
+#define TIM1_DMABase_EGR                   ((u16)0x0005)
+#define TIM1_DMABase_CCMR1                 ((u16)0x0006)
+#define TIM1_DMABase_CCMR2                 ((u16)0x0007)
+#define TIM1_DMABase_CCER                  ((u16)0x0008)
+#define TIM1_DMABase_CNT                   ((u16)0x0009)
+#define TIM1_DMABase_PSC                   ((u16)0x000A)
+#define TIM1_DMABase_ARR                   ((u16)0x000B)
+#define TIM1_DMABase_RCR                   ((u16)0x000C)
+#define TIM1_DMABase_CCR1                  ((u16)0x000D)
+#define TIM1_DMABase_CCR2                  ((u16)0x000E)
+#define TIM1_DMABase_CCR3                  ((u16)0x000F)
+#define TIM1_DMABase_CCR4                  ((u16)0x0010)
+#define TIM1_DMABase_BDTR                  ((u16)0x0011)
+#define TIM1_DMABase_DCR                   ((u16)0x0012)
+
+#define IS_TIM1_DMA_BASE(BASE) ((BASE == TIM1_DMABase_CR1) || \
+                                (BASE == TIM1_DMABase_CR2) || \
+                                (BASE == TIM1_DMABase_SMCR) || \
+                                (BASE == TIM1_DMABase_DIER) || \
+                                (BASE == TIM1_DMABase_SR) || \
+                                (BASE == TIM1_DMABase_EGR) || \
+                                (BASE == TIM1_DMABase_CCMR1) || \
+                                (BASE == TIM1_DMABase_CCMR2) || \
+                                (BASE == TIM1_DMABase_CCER) || \
+                                (BASE == TIM1_DMABase_CNT) || \
+                                (BASE == TIM1_DMABase_PSC) || \
+                                (BASE == TIM1_DMABase_ARR) || \
+                                (BASE == TIM1_DMABase_RCR) || \
+                                (BASE == TIM1_DMABase_CCR1) || \
+                                (BASE == TIM1_DMABase_CCR2) || \
+                                (BASE == TIM1_DMABase_CCR3) || \
+                                (BASE == TIM1_DMABase_CCR4) || \
+                                (BASE == TIM1_DMABase_BDTR) || \
+                                (BASE == TIM1_DMABase_DCR))
+
+/* TIM1 DMA Burst Length ----------------------------------------------------*/
+#define TIM1_DMABurstLength_1Byte          ((u16)0x0000)
+#define TIM1_DMABurstLength_2Bytes         ((u16)0x0100)
+#define TIM1_DMABurstLength_3Bytes         ((u16)0x0200)
+#define TIM1_DMABurstLength_4Bytes         ((u16)0x0300)
+#define TIM1_DMABurstLength_5Bytes         ((u16)0x0400)
+#define TIM1_DMABurstLength_6Bytes         ((u16)0x0500)
+#define TIM1_DMABurstLength_7Bytes         ((u16)0x0600)
+#define TIM1_DMABurstLength_8Bytes         ((u16)0x0700)
+#define TIM1_DMABurstLength_9Bytes         ((u16)0x0800)
+#define TIM1_DMABurstLength_10Bytes        ((u16)0x0900)
+#define TIM1_DMABurstLength_11Bytes        ((u16)0x0A00)
+#define TIM1_DMABurstLength_12Bytes        ((u16)0x0B00)
+#define TIM1_DMABurstLength_13Bytes        ((u16)0x0C00)
+#define TIM1_DMABurstLength_14Bytes        ((u16)0x0D00)
+#define TIM1_DMABurstLength_15Bytes        ((u16)0x0E00)
+#define TIM1_DMABurstLength_16Bytes        ((u16)0x0F00)
+#define TIM1_DMABurstLength_17Bytes        ((u16)0x1000)
+#define TIM1_DMABurstLength_18Bytes        ((u16)0x1100)
+
+#define IS_TIM1_DMA_LENGTH(LENGTH) ((LENGTH == TIM1_DMABurstLength_1Byte) || \
+                                    (LENGTH == TIM1_DMABurstLength_2Bytes) || \
+                                    (LENGTH == TIM1_DMABurstLength_3Bytes) || \
+                                    (LENGTH == TIM1_DMABurstLength_4Bytes) || \
+                                    (LENGTH == TIM1_DMABurstLength_5Bytes) || \
+                                    (LENGTH == TIM1_DMABurstLength_6Bytes) || \
+                                    (LENGTH == TIM1_DMABurstLength_7Bytes) || \
+                                    (LENGTH == TIM1_DMABurstLength_8Bytes) || \
+                                    (LENGTH == TIM1_DMABurstLength_9Bytes) || \
+                                    (LENGTH == TIM1_DMABurstLength_10Bytes) || \
+                                    (LENGTH == TIM1_DMABurstLength_11Bytes) || \
+                                    (LENGTH == TIM1_DMABurstLength_12Bytes) || \
+                                    (LENGTH == TIM1_DMABurstLength_13Bytes) || \
+                                    (LENGTH == TIM1_DMABurstLength_14Bytes) || \
+                                    (LENGTH == TIM1_DMABurstLength_15Bytes) || \
+                                    (LENGTH == TIM1_DMABurstLength_16Bytes) || \
+                                    (LENGTH == TIM1_DMABurstLength_17Bytes) || \
+                                    (LENGTH == TIM1_DMABurstLength_18Bytes))
+
+/* TIM1 DMA sources ---------------------------------------------------------*/
+#define TIM1_DMA_Update                    ((u16)0x0100)
+#define TIM1_DMA_CC1                       ((u16)0x0200)
+#define TIM1_DMA_CC2                       ((u16)0x0400)
+#define TIM1_DMA_CC3                       ((u16)0x0800)
+#define TIM1_DMA_CC4                       ((u16)0x1000)
+#define TIM1_DMA_COM                       ((u16)0x2000)
+#define TIM1_DMA_Trigger                   ((u16)0x4000)
+
+#define IS_TIM1_DMA_SOURCE(SOURCE) (((SOURCE & (u16)0x80FF) == 0x0000) && (SOURCE != 0x0000))
+
+/* TIM1 External Trigger Prescaler ------------------------------------------*/
+#define TIM1_ExtTRGPSC_OFF                 ((u16)0x0000)
+#define TIM1_ExtTRGPSC_DIV2                ((u16)0x1000)
+#define TIM1_ExtTRGPSC_DIV4                ((u16)0x2000)
+#define TIM1_ExtTRGPSC_DIV8                ((u16)0x3000)
+
+#define IS_TIM1_EXT_PRESCALER(PRESCALER) ((PRESCALER == TIM1_ExtTRGPSC_OFF) || \
+                                          (PRESCALER == TIM1_ExtTRGPSC_DIV2) || \
+                                          (PRESCALER == TIM1_ExtTRGPSC_DIV4) || \
+                                          (PRESCALER == TIM1_ExtTRGPSC_DIV8))
+
+/* TIM1 Internal Trigger Selection ------------------------------------------*/
+#define TIM1_TS_ITR0                       ((u16)0x0000)
+#define TIM1_TS_ITR1                       ((u16)0x0010)
+#define TIM1_TS_ITR2                       ((u16)0x0020)
+#define TIM1_TS_ITR3                       ((u16)0x0030)
+#define TIM1_TS_TI1F_ED	                   ((u16)0x0040)
+#define TIM1_TS_TI1FP1                     ((u16)0x0050)
+#define TIM1_TS_TI2FP2                     ((u16)0x0060)
+#define TIM1_TS_ETRF                       ((u16)0x0070)
+
+#define IS_TIM1_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_ITR0) || \
+                                              (SELECTION == TIM1_TS_ITR1) || \
+                                              (SELECTION == TIM1_TS_ITR2) || \
+                                              (SELECTION == TIM1_TS_ITR3) || \
+                                              (SELECTION == TIM1_TS_TI1F_ED) || \
+                                              (SELECTION == TIM1_TS_TI1FP1) || \
+                                              (SELECTION == TIM1_TS_TI2FP2) || \
+                                              (SELECTION == TIM1_TS_ETRF))
+
+#define IS_TIM1_INTERNAL_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_ITR0) || \
+                                                       (SELECTION == TIM1_TS_ITR1) || \
+                                                       (SELECTION == TIM1_TS_ITR2) || \
+                                                       (SELECTION == TIM1_TS_ITR3))
+
+#define IS_TIM1_TIX_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_TI1F_ED) || \
+                                                  (SELECTION == TIM1_TS_TI1FP1) || \
+                                                  (SELECTION == TIM1_TS_TI2FP2))
+
+/* TIM1 External Trigger Polarity -------------------------------------------*/
+#define TIM1_ExtTRGPolarity_Inverted       ((u16)0x8000)
+#define TIM1_ExtTRGPolarity_NonInverted    ((u16)0x0000)
+
+#define IS_TIM1_EXT_POLARITY(POLARITY) ((POLARITY == TIM1_ExtTRGPolarity_Inverted) || \
+                                        (POLARITY == TIM1_ExtTRGPolarity_NonInverted))
+
+/* TIM1 Prescaler Reload Mode -----------------------------------------------*/
+#define TIM1_PSCReloadMode_Update          ((u16)0x0000)
+#define TIM1_PSCReloadMode_Immediate       ((u16)0x0001)
+
+#define IS_TIM1_PRESCALER_RELOAD(RELOAD) ((RELOAD == TIM1_PSCReloadMode_Update) || \
+                                          (RELOAD == TIM1_PSCReloadMode_Immediate))
+
+/* TIM1 Forced Action -------------------------------------------------------*/
+#define TIM1_ForcedAction_Active           ((u16)0x0050)
+#define TIM1_ForcedAction_InActive         ((u16)0x0040)
+
+#define IS_TIM1_FORCED_ACTION(ACTION) ((ACTION == TIM1_ForcedAction_Active) || \
+                                       (ACTION == TIM1_ForcedAction_InActive))
+
+/* TIM1 Encoder Mode --------------------------------------------------------*/ 
+#define TIM1_EncoderMode_TI1               ((u16)0x0001)
+#define TIM1_EncoderMode_TI2               ((u16)0x0002)
+#define TIM1_EncoderMode_TI12              ((u16)0x0003)
+
+#define IS_TIM1_ENCODER_MODE(MODE) ((MODE == TIM1_EncoderMode_TI1) || \
+                                    (MODE == TIM1_EncoderMode_TI2) || \
+                                    (MODE == TIM1_EncoderMode_TI12))
+
+/* TIM1 Event Source --------------------------------------------------------*/
+#define TIM1_EventSource_Update            ((u16)0x0001)
+#define TIM1_EventSource_CC1               ((u16)0x0002)
+#define TIM1_EventSource_CC2               ((u16)0x0004)
+#define TIM1_EventSource_CC3               ((u16)0x0008)
+#define TIM1_EventSource_CC4               ((u16)0x0010)
+#define TIM1_EventSource_COM               ((u16)0x0020)
+#define TIM1_EventSource_Trigger           ((u16)0x0040)
+#define TIM1_EventSource_Break             ((u16)0x0080)
+
+#define IS_TIM1_EVENT_SOURCE(SOURCE) (((SOURCE & (u16)0xFF00) == 0x0000) && (SOURCE != 0x0000))
+                                      
+
+/* TIM1 Update Source -------------------------------------------------------*/
+#define TIM1_UpdateSource_Global           ((u16)0x0000)
+#define TIM1_UpdateSource_Regular          ((u16)0x0001)
+
+#define IS_TIM1_UPDATE_SOURCE(SOURCE) ((SOURCE == TIM1_UpdateSource_Global) || \
+                                       (SOURCE == TIM1_UpdateSource_Regular))
+
+/* TIM1 Ouput Compare Preload State ------------------------------------------*/
+#define TIM1_OCPreload_Enable              ((u16)0x0001)
+#define TIM1_OCPreload_Disable             ((u16)0x0000)
+
+#define IS_TIM1_OCPRELOAD_STATE(STATE) ((STATE == TIM1_OCPreload_Enable) || \
+                                        (STATE == TIM1_OCPreload_Disable))
+
+/* TIM1 Ouput Compare Fast State ---------------------------------------------*/
+#define TIM1_OCFast_Enable                 ((u16)0x0001)
+#define TIM1_OCFast_Disable                ((u16)0x0000)
+
+#define IS_TIM1_OCFAST_STATE(STATE) ((STATE == TIM1_OCFast_Enable) || \
+                                     (STATE == TIM1_OCFast_Disable))
+
+/* TIM1 Trigger Output Source -----------------------------------------------*/ 
+#define TIM1_TRGOSource_Reset              ((u16)0x0000)
+#define TIM1_TRGOSource_Enable             ((u16)0x0010)
+#define TIM1_TRGOSource_Update             ((u16)0x0020)
+#define TIM1_TRGOSource_OC1                ((u16)0x0030)
+#define TIM1_TRGOSource_OC1Ref             ((u16)0x0040)
+#define TIM1_TRGOSource_OC2Ref             ((u16)0x0050)
+#define TIM1_TRGOSource_OC3Ref             ((u16)0x0060)
+#define TIM1_TRGOSource_OC4Ref             ((u16)0x0070)
+
+#define IS_TIM1_TRGO_SOURCE(SOURCE) ((SOURCE == TIM1_TRGOSource_Reset) || \
+                                     (SOURCE == TIM1_TRGOSource_Enable) || \
+                                     (SOURCE == TIM1_TRGOSource_Update) || \
+                                     (SOURCE == TIM1_TRGOSource_OC1) || \
+                                     (SOURCE == TIM1_TRGOSource_OC1Ref) || \
+                                     (SOURCE == TIM1_TRGOSource_OC2Ref) || \
+                                     (SOURCE == TIM1_TRGOSource_OC3Ref) || \
+                                     (SOURCE == TIM1_TRGOSource_OC4Ref))
+
+/* TIM1 Slave Mode ----------------------------------------------------------*/
+#define TIM1_SlaveMode_Reset               ((u16)0x0004)
+#define TIM1_SlaveMode_Gated               ((u16)0x0005)
+#define TIM1_SlaveMode_Trigger             ((u16)0x0006)
+#define TIM1_SlaveMode_External1           ((u16)0x0007)
+
+#define IS_TIM1_SLAVE_MODE(MODE) ((MODE == TIM1_SlaveMode_Reset) || \
+                                  (MODE == TIM1_SlaveMode_Gated) || \
+                                  (MODE == TIM1_SlaveMode_Trigger) || \
+                                  (MODE == TIM1_SlaveMode_External1))
+
+/* TIM1 TIx External Clock Source -------------------------------------------*/
+#define TIM1_TIxExternalCLK1Source_TI1     ((u16)0x0050)
+#define TIM1_TIxExternalCLK1Source_TI2     ((u16)0x0060)
+#define TIM1_TIxExternalCLK1Source_TI1ED   ((u16)0x0040)
+
+#define IS_TIM1_TIXCLK_SOURCE(SOURCE) ((SOURCE == TIM1_TIxExternalCLK1Source_TI1) || \
+                                       (SOURCE == TIM1_TIxExternalCLK1Source_TI2) || \
+                                       (SOURCE == TIM1_TIxExternalCLK1Source_TI1ED))
+
+/* TIM1 Master Slave Mode ---------------------------------------------------*/
+#define TIM1_MasterSlaveMode_Enable        ((u16)0x0001)
+#define TIM1_MasterSlaveMode_Disable       ((u16)0x0000)
+
+#define IS_TIM1_MSM_STATE(STATE) ((STATE == TIM1_MasterSlaveMode_Enable) || \
+                                  (STATE == TIM1_MasterSlaveMode_Disable))
+
+/* TIM1 Flags ---------------------------------------------------------------*/
+#define TIM1_FLAG_Update                   ((u16)0x0001)
+#define TIM1_FLAG_CC1                      ((u16)0x0002)
+#define TIM1_FLAG_CC2                      ((u16)0x0004)
+#define TIM1_FLAG_CC3                      ((u16)0x0008)
+#define TIM1_FLAG_CC4                      ((u16)0x0010)
+#define TIM1_FLAG_COM                      ((u16)0x0020)
+#define TIM1_FLAG_Trigger                  ((u16)0x0040)
+#define TIM1_FLAG_Break                    ((u16)0x0080)
+#define TIM1_FLAG_CC1OF                    ((u16)0x0200)
+#define TIM1_FLAG_CC2OF                    ((u16)0x0400)
+#define TIM1_FLAG_CC3OF                    ((u16)0x0800)
+#define TIM1_FLAG_CC4OF                    ((u16)0x1000)
+
+#define IS_TIM1_GET_FLAG(FLAG) ((FLAG == TIM1_FLAG_Update) || \
+                                (FLAG == TIM1_FLAG_CC1) || \
+                                (FLAG == TIM1_FLAG_CC2) || \
+                                (FLAG == TIM1_FLAG_CC3) || \
+                                (FLAG == TIM1_FLAG_CC4) || \
+                                (FLAG == TIM1_FLAG_COM) || \
+                                (FLAG == TIM1_FLAG_Trigger) || \
+                                (FLAG == TIM1_FLAG_Break) || \
+                                (FLAG == TIM1_FLAG_CC1OF) || \
+                                (FLAG == TIM1_FLAG_CC2OF) || \
+                                (FLAG == TIM1_FLAG_CC3OF) || \
+                                (FLAG == TIM1_FLAG_CC4OF))
+
+#define IS_TIM1_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xE100) == 0x0000) && (FLAG != 0x0000))
+                                  
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+void TIM1_DeInit(void);
+void TIM1_TimeBaseInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct);
+void TIM1_OC1Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
+void TIM1_OC2Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
+void TIM1_OC3Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
+void TIM1_OC4Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
+void TIM1_BDTRConfig(TIM1_BDTRInitTypeDef *TIM1_BDTRInitStruct);
+void TIM1_ICInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct);
+void TIM1_PWMIConfig(TIM1_ICInitTypeDef* TIM1_ICInitStruct);
+void TIM1_TimeBaseStructInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct);
+void TIM1_OCStructInit(TIM1_OCInitTypeDef* TIM1_OCInitStruct);
+void TIM1_ICStructInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct);
+void TIM1_BDTRStructInit(TIM1_BDTRInitTypeDef* TIM1_BDTRInitStruct);
+void TIM1_Cmd(FunctionalState NewState);
+void TIM1_CtrlPWMOutputs(FunctionalState Newstate);
+void TIM1_ITConfig(u16 TIM1_IT, FunctionalState NewState);
+void TIM1_DMAConfig(u16 TIM1_DMABase, u16 TIM1_DMABurstLength);
+void TIM1_DMACmd(u16 TIM1_DMASource, FunctionalState Newstate);
+void TIM1_InternalClockConfig(void);
+void TIM1_ETRClockMode1Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity, 
+                             u16 ExtTRGFilter);
+void TIM1_ETRClockMode2Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity, 
+                             u16 ExtTRGFilter);
+void TIM1_ITRxExternalClockConfig(u16 TIM1_InputTriggerSource);
+void TIM1_TIxExternalClockConfig(u16 TIM1_TIxExternalCLKSource, u16 TIM1_ICPolarity, 
+                                u8 ICFilter);
+void TIM1_SelectInputTrigger(u16 TIM1_InputTriggerSource);
+void TIM1_UpdateDisableConfig(FunctionalState Newstate);
+void TIM1_UpdateRequestConfig(u8 TIM1_UpdateSource);
+void TIM1_SelectHallSensor(FunctionalState Newstate);
+void TIM1_SelectOnePulseMode(u16 TIM1_OPMode);
+void TIM1_SelectOutputTrigger(u16 TIM1_TRGOSource);
+void TIM1_SelectSlaveMode(u16 TIM1_SlaveMode);
+void TIM1_SelectMasterSlaveMode(u16 TIM1_MasterSlaveMode);
+void TIM1_EncoderInterfaceConfig(u16 TIM1_EncoderMode, u16 TIM1_IC1Polarity, 
+                                u16 TIM1_IC2Polarity);
+void TIM1_PrescalerConfig(u16 Prescaler, u16 TIM1_PSCReloadMode);
+void TIM1_CounterModeConfig(u16 TIM1_CounterMode);
+void TIM1_ForcedOC1Config(u16 TIM1_ForcedAction);
+void TIM1_ForcedOC2Config(u16 TIM1_ForcedAction);
+void TIM1_ForcedOC3Config(u16 TIM1_ForcedAction);
+void TIM1_ForcedOC4Config(u16 TIM1_ForcedAction);
+void TIM1_ARRPreloadConfig(FunctionalState Newstate);
+void TIM1_SelectCOM(FunctionalState Newstate);
+void TIM1_SelectCCDMA(FunctionalState Newstate);
+void TIM1_CCPreloadControl(FunctionalState Newstate);
+void TIM1_OC1PreloadConfig(u16 TIM1_OCPreload);
+void TIM1_OC2PreloadConfig(u16 TIM1_OCPreload);
+void TIM1_OC3PreloadConfig(u16 TIM1_OCPreload);
+void TIM1_OC4PreloadConfig(u16 TIM1_OCPreload);
+void TIM1_OC1FastConfig(u16 TIM1_OCFast);
+void TIM1_OC2FastConfig(u16 TIM1_OCFast);
+void TIM1_OC3FastConfig(u16 TIM1_OCFast);
+void TIM1_OC4FastConfig(u16 TIM1_OCFast);
+void TIM1_GenerateEvent(u16 TIM1_EventSource);
+void TIM1_OC1PolarityConfig(u16 TIM1_OCPolarity);
+void TIM1_OC1NPolarityConfig(u16 TIM1_OCPolarity);
+void TIM1_OC2PolarityConfig(u16 TIM1_OCPolarity);
+void TIM1_OC2NPolarityConfig(u16 TIM1_OCPolarity);
+void TIM1_OC3PolarityConfig(u16 TIM1_OCPolarity);
+void TIM1_OC3NPolarityConfig(u16 TIM1_OCPolarity);
+void TIM1_OC4PolarityConfig(u16 TIM1_OCPolarity);
+void TIM1_CCxCmd(u16 TIM1_Channel, FunctionalState Newstate);
+void TIM1_CCxNCmd(u16 TIM1_Channel, FunctionalState Newstate);
+void TIM1_SelectOCxM(u16 TIM1_Channel, u16 TIM1_OCMode);
+void TIM1_SetAutoreload(u16 Autoreload);
+void TIM1_SetCompare1(u16 Compare1);
+void TIM1_SetCompare2(u16 Compare2);
+void TIM1_SetCompare3(u16 Compare3);
+void TIM1_SetCompare4(u16 Compare4);
+void TIM1_SetIC1Prescaler(u16 TIM1_IC1Prescaler);
+void TIM1_SetIC2Prescaler(u16 TIM1_IC2Prescaler);
+void TIM1_SetIC3Prescaler(u16 TIM1_IC3Prescaler);
+void TIM1_SetIC4Prescaler(u16 TIM1_IC4Prescaler);
+void TIM1_SetClockDivision(u16 TIM1_CKD);
+u16 TIM1_GetCapture1(void);
+u16 TIM1_GetCapture2(void);
+u16 TIM1_GetCapture3(void);
+u16 TIM1_GetCapture4(void);
+u16 TIM1_GetCounter(void);
+u16 TIM1_GetPrescaler(void);
+FlagStatus TIM1_GetFlagStatus(u16 TIM1_FLAG); 
+void TIM1_ClearFlag(u16 TIM1_Flag);
+ITStatus TIM1_GetITStatus(u16 TIM1_IT);
+void TIM1_ClearITPendingBit(u16 TIM1_IT);
+
+#endif /*__STM32F10x_TIM1_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_type.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_type.h
new file mode 100644
index 0000000..d6e83a9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_type.h
@@ -0,0 +1,76 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_type.h
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file contains all the common data types used for the
+*                      STM32F10x firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_TYPE_H
+#define __STM32F10x_TYPE_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+typedef signed long  s32;
+typedef signed short s16;
+typedef signed char  s8;
+
+typedef volatile signed long  vs32;
+typedef volatile signed short vs16;
+typedef volatile signed char  vs8;
+
+typedef unsigned long  u32;
+typedef unsigned short u16;
+typedef unsigned char  u8;
+
+typedef unsigned long  const uc32;  /* Read Only */
+typedef unsigned short const uc16;  /* Read Only */
+typedef unsigned char  const uc8;   /* Read Only */
+
+typedef volatile unsigned long  vu32;
+typedef volatile unsigned short vu16;
+typedef volatile unsigned char  vu8;
+
+typedef volatile unsigned long  const vuc32;  /* Read Only */
+typedef volatile unsigned short const vuc16;  /* Read Only */
+typedef volatile unsigned char  const vuc8;   /* Read Only */
+
+typedef enum {FALSE = 0, TRUE = !FALSE} bool;
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) ((STATE == DISABLE) || (STATE == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+#define U8_MAX     ((u8)255)
+#define S8_MAX     ((s8)127)
+#define S8_MIN     ((s8)-128)
+#define U16_MAX    ((u16)65535u)
+#define S16_MAX    ((s16)32767)
+#define S16_MIN    ((s16)-32768)
+#define U32_MAX    ((u32)4294967295uL)
+#define S32_MAX    ((s32)2147483647)
+#define S32_MIN    ((s32)2147483648uL)
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __STM32F10x_TYPE_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_usart.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_usart.h
new file mode 100644
index 0000000..e8c44aa
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_usart.h
@@ -0,0 +1,219 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_usart.h
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file contains all the functions prototypes for the
+*                      USART firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_USART_H
+#define __STM32F10x_USART_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* UART Init Structure definition */
+typedef struct
+{
+  u32 USART_BaudRate;
+  u16 USART_WordLength;
+  u16 USART_StopBits;
+  u16 USART_Parity;
+  u16 USART_HardwareFlowControl;
+  u16 USART_Mode;
+  u16 USART_Clock;
+  u16 USART_CPOL;
+  u16 USART_CPHA;
+  u16 USART_LastBit;
+} USART_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* USART Word Length ---------------------------------------------------------*/
+#define USART_WordLength_8b                  ((u16)0x0000)
+#define USART_WordLength_9b                  ((u16)0x1000)
+
+#define IS_USART_WORD_LENGTH(LENGTH) ((LENGTH == USART_WordLength_8b) || \
+                                      (LENGTH == USART_WordLength_9b))
+
+/* USART Stop Bits -----------------------------------------------------------*/
+#define USART_StopBits_1                     ((u16)0x0000)
+#define USART_StopBits_0_5                   ((u16)0x1000)
+#define USART_StopBits_2                     ((u16)0x2000)
+#define USART_StopBits_1_5                   ((u16)0x3000)
+
+#define IS_USART_STOPBITS(STOPBITS) ((STOPBITS == USART_StopBits_1) || \
+                                     (STOPBITS == USART_StopBits_0_5) || \
+                                     (STOPBITS == USART_StopBits_2) || \
+                                     (STOPBITS == USART_StopBits_1_5))
+/* USART Parity --------------------------------------------------------------*/
+#define USART_Parity_No                      ((u16)0x0000)
+#define USART_Parity_Even                    ((u16)0x0400)
+#define USART_Parity_Odd                     ((u16)0x0600) 
+
+#define IS_USART_PARITY(PARITY) ((PARITY == USART_Parity_No) || \
+                                 (PARITY == USART_Parity_Even) || \
+                                 (PARITY == USART_Parity_Odd))
+
+/* USART Hardware Flow Control -----------------------------------------------*/
+#define USART_HardwareFlowControl_None       ((u16)0x0000)
+#define USART_HardwareFlowControl_RTS        ((u16)0x0100)
+#define USART_HardwareFlowControl_CTS        ((u16)0x0200)
+#define USART_HardwareFlowControl_RTS_CTS    ((u16)0x0300)
+
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
+                              ((CONTROL == USART_HardwareFlowControl_None) || \
+                               (CONTROL == USART_HardwareFlowControl_RTS) || \
+                               (CONTROL == USART_HardwareFlowControl_CTS) || \
+                               (CONTROL == USART_HardwareFlowControl_RTS_CTS))
+
+/* USART Mode ----------------------------------------------------------------*/
+#define USART_Mode_Rx                        ((u16)0x0004)
+#define USART_Mode_Tx                        ((u16)0x0008)
+
+#define IS_USART_MODE(MODE) (((MODE & (u16)0xFFF3) == 0x00) && (MODE != (u16)0x00))
+
+/* USART Clock ---------------------------------------------------------------*/
+#define USART_Clock_Disable                  ((u16)0x0000)
+#define USART_Clock_Enable                   ((u16)0x0800)
+
+#define IS_USART_CLOCK(CLOCK) ((CLOCK == USART_Clock_Disable) || \
+                               (CLOCK == USART_Clock_Enable))
+
+/* USART Clock Polarity ------------------------------------------------------*/
+#define USART_CPOL_Low                       ((u16)0x0000)
+#define USART_CPOL_High                      ((u16)0x0400)
+
+#define IS_USART_CPOL(CPOL) ((CPOL == USART_CPOL_Low) || (CPOL == USART_CPOL_High))
+                               
+/* USART Clock Phase ---------------------------------------------------------*/
+#define USART_CPHA_1Edge                     ((u16)0x0000)
+#define USART_CPHA_2Edge                     ((u16)0x0200)
+#define IS_USART_CPHA(CPHA) ((CPHA == USART_CPHA_1Edge) || (CPHA == USART_CPHA_2Edge))
+
+/* USART Last Bit ------------------------------------------------------------*/
+#define USART_LastBit_Disable                ((u16)0x0000)
+#define USART_LastBit_Enable                 ((u16)0x0100)
+
+#define IS_USART_LASTBIT(LASTBIT) ((LASTBIT == USART_LastBit_Disable) || \
+                                   (LASTBIT == USART_LastBit_Enable))
+
+/* USART Interrupt definition ------------------------------------------------*/
+#define USART_IT_PE                          ((u16)0x0028)
+#define USART_IT_TXE                         ((u16)0x0727)
+#define USART_IT_TC                          ((u16)0x0626)
+#define USART_IT_RXNE                        ((u16)0x0525)
+#define USART_IT_IDLE                        ((u16)0x0424)
+#define USART_IT_LBD                         ((u16)0x0846)
+#define USART_IT_CTS                         ((u16)0x096A)
+#define USART_IT_ERR                         ((u16)0x0060)
+#define USART_IT_ORE                         ((u16)0x0360)
+#define USART_IT_NE                          ((u16)0x0260)
+#define USART_IT_FE                          ((u16)0x0160)
+
+#define IS_USART_CONFIG_IT(IT) ((IT == USART_IT_PE) || (IT == USART_IT_TXE) || \
+                               (IT == USART_IT_TC) || (IT == USART_IT_RXNE) || \
+                               (IT == USART_IT_IDLE) || (IT == USART_IT_LBD) || \
+                               (IT == USART_IT_CTS) || (IT == USART_IT_ERR))
+
+#define IS_USART_IT(IT) ((IT == USART_IT_PE) || (IT == USART_IT_TXE) || \
+                         (IT == USART_IT_TC) || (IT == USART_IT_RXNE) || \
+                         (IT == USART_IT_IDLE) || (IT == USART_IT_LBD) || \
+                         (IT == USART_IT_CTS) || (IT == USART_IT_ORE) || \
+                         (IT == USART_IT_NE) || (IT == USART_IT_FE))
+
+/* USART DMA Requests --------------------------------------------------------*/
+#define USART_DMAReq_Tx                      ((u16)0x0080)
+#define USART_DMAReq_Rx                      ((u16)0x0040)
+
+#define IS_USART_DMAREQ(DMAREQ) (((DMAREQ & (u16)0xFF3F) == 0x00) && (DMAREQ != (u16)0x00))
+
+/* USART WakeUp methods ------------------------------------------------------*/
+#define USART_WakeUp_IdleLine                ((u16)0x0000)
+#define USART_WakeUp_AddressMark             ((u16)0x0800)
+
+#define IS_USART_WAKEUP(WAKEUP) ((WAKEUP == USART_WakeUp_IdleLine) || \
+                                 (WAKEUP == USART_WakeUp_AddressMark))
+
+/* USART LIN Break Detection Length ------------------------------------------*/
+#define USART_LINBreakDetectLength_10b      ((u16)0x0000)
+#define USART_LINBreakDetectLength_11b      ((u16)0x0020)
+
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
+                               ((LENGTH == USART_LINBreakDetectLength_10b) || \
+                                (LENGTH == USART_LINBreakDetectLength_11b))
+
+/* USART IrDA Low Power ------------------------------------------------------*/
+#define USART_IrDAMode_LowPower              ((u16)0x0004)
+#define USART_IrDAMode_Normal                ((u16)0x0000)
+
+#define IS_USART_IRDA_MODE(MODE) ((MODE == USART_IrDAMode_LowPower) || \
+                                  (MODE == USART_IrDAMode_Normal))
+
+/* USART Flags ---------------------------------------------------------------*/
+#define USART_FLAG_CTS                       ((u16)0x0200)
+#define USART_FLAG_LBD                       ((u16)0x0100)
+#define USART_FLAG_TXE                       ((u16)0x0080)
+#define USART_FLAG_TC                        ((u16)0x0040)
+#define USART_FLAG_RXNE                      ((u16)0x0020)
+#define USART_FLAG_IDLE                      ((u16)0x0010)
+#define USART_FLAG_ORE                       ((u16)0x0008)
+#define USART_FLAG_NE                        ((u16)0x0004)
+#define USART_FLAG_FE                        ((u16)0x0002)
+#define USART_FLAG_PE                        ((u16)0x0001)
+
+#define IS_USART_FLAG(FLAG) ((FLAG == USART_FLAG_PE) || (FLAG == USART_FLAG_TXE) || \
+                             (FLAG == USART_FLAG_TC) || (FLAG == USART_FLAG_RXNE) || \
+                             (FLAG == USART_FLAG_IDLE) || (FLAG == USART_FLAG_LBD) || \
+                             (FLAG == USART_FLAG_CTS) || (FLAG == USART_FLAG_ORE) || \
+                             (FLAG == USART_FLAG_NE) || (FLAG == USART_FLAG_FE))
+ 
+#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xFC00) == 0x00) && (FLAG != (u16)0x00))
+
+#define IS_USART_ADDRESS(ADDRESS) (ADDRESS <= 0xF)
+#define IS_USART_DATA(DATA) (DATA <= 0x1FF)
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void USART_DeInit(USART_TypeDef* USARTx);
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState);
+void USART_DMACmd(USART_TypeDef* USARTx, u16 USART_DMAReq, FunctionalState NewState);
+void USART_SetAddress(USART_TypeDef* USARTx, u8 USART_Address);
+void USART_WakeUpConfig(USART_TypeDef* USARTx, u16 USART_WakeUp);
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, u16 USART_LINBreakDetectLength);
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SendData(USART_TypeDef* USARTx, u16 Data);
+u16 USART_ReceiveData(USART_TypeDef* USARTx);
+void USART_SendBreak(USART_TypeDef* USARTx);
+void USART_SetGuardTime(USART_TypeDef* USARTx, u8 USART_GuardTime);
+void USART_SetPrescaler(USART_TypeDef* USARTx, u8 USART_Prescaler);
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_IrDAConfig(USART_TypeDef* USARTx, u16 USART_IrDAMode);
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, u16 USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, u16 USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, u16 USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, u16 USART_IT);
+
+#endif /* __STM32F10x_USART_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_wwdg.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_wwdg.h
new file mode 100644
index 0000000..2230b58
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_wwdg.h
@@ -0,0 +1,58 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_wwdg.h
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file contains all the functions prototypes for the
+*                      WWDG firmware library.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_WWDG_H
+#define __STM32F10x_WWDG_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* WWDG Prescaler */
+#define WWDG_Prescaler_1    ((u32)0x00000000)
+#define WWDG_Prescaler_2    ((u32)0x00000080)
+#define WWDG_Prescaler_4    ((u32)0x00000100)
+#define WWDG_Prescaler_8    ((u32)0x00000180)
+
+#define IS_WWDG_PRESCALER(PRESCALER) ((PRESCALER == WWDG_Prescaler_1) || \
+                                      (PRESCALER == WWDG_Prescaler_2) || \
+                                      (PRESCALER == WWDG_Prescaler_4) || \
+                                      (PRESCALER == WWDG_Prescaler_8))
+
+#define IS_WWDG_WINDOW_VALUE(VALUE) (VALUE <= 0x7F)
+
+#define IS_WWDG_COUNTER(COUNTER) ((COUNTER >= 0x40) && (COUNTER <= 0x7F))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void WWDG_DeInit(void);
+void WWDG_SetPrescaler(u32 WWDG_Prescaler);
+void WWDG_SetWindowValue(u8 WindowValue);
+void WWDG_EnableIT(void);
+void WWDG_SetCounter(u8 Counter);
+void WWDG_Enable(u8 Counter);
+FlagStatus WWDG_GetFlagStatus(void);
+void WWDG_ClearFlag(void);
+
+#endif /* __STM32F10x_WWDG_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth.h
new file mode 100644
index 0000000..11f15b0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth.h
@@ -0,0 +1,1118 @@
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name          : stm32fxxx_eth.h
+* Author             : MCD Application Team
+* Version            : V0.0.1
+* Date               : 12/17/2008
+* Desciption         : This file contains all the functions prototypes for the
+*                      ETHERNET firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32FXXX_ETH_H
+#define __STM32FXXX_ETH_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32fxxx_eth_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* ETHERNET MAC Init structure definition */
+typedef struct {
+  /* MAC ----------------------------------*/
+  u32             ETH_AutoNegotiation;           /* Selects or not the AutoNegotiation with the external PHY */
+  u32             ETH_Watchdog;                  /* Enable/disable Watchdog timer */
+  u32             ETH_Jabber;                    /* Enable/disable Jabber timer */
+  u32             ETH_JumboFrame;                /* Enable/disable Jumbo frame */
+  u32             ETH_InterFrameGap;             /* Selects minimum IFG between frames during transmission */
+  u32             ETH_CarrierSense;              /* Enable/disable Carrier Sense */
+  u32             ETH_Speed;                     /* Indicates the Ethernet speed: 10/100 Mbps */
+  u32             ETH_ReceiveOwn;                /* Enable/disable the reception of frames when the TX_EN signal is asserted in Half-Duplex mode */
+  u32             ETH_LoopbackMode;              /* Enable/disable internal MAC MII Loopback mode */
+  u32             ETH_Mode;                      /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode */
+  u32             ETH_ChecksumOffload;           /* Enable/disable the calculation of complement sum of all received Ethernet frame payloads */
+  u32             ETH_RetryTransmission;         /* Enable/disable the MAC attempt retries transmission, based on the settings of BL, when a colision occurs (Half-Duplex mode) */
+  u32             ETH_AutomaticPadCRCStrip;      /* Enable/disable Automatic MAC Pad/CRC Stripping */
+  u32             ETH_BackOffLimit;              /* Selects the BackOff limit value */
+  u32             ETH_DeferralCheck;             /* Enable/disable deferral check function (Half-Duplex mode) */
+  u32             ETH_ReceiveAll;                /* Enable/disable all frames reception by the MAC (No fitering)*/
+  u32             ETH_SourceAddrFilter;          /* Selects EnableNormal/EnableInverse/disable Source Address Filter comparison */
+  u32             ETH_PassControlFrames;         /* Selects None/All/FilterPass of all control frames (including unicast and multicast PAUSE frames) */
+  u32             ETH_BroadcastFramesReception;  /* Enable/disable reception of Broadcast Frames */
+  u32             ETH_DestinationAddrFilter;     /* Selects EnableNormal/EnableInverse destination filter for both unicast and multicast frames */
+  u32             ETH_PromiscuousMode;           /* Enable/disable Promiscuous Mode */
+  u32             ETH_MulticastFramesFilter;     /* Selects the Multicast Frames filter: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter */
+  u32             ETH_UnicastFramesFilter;       /* Selects the Unicast Frames filter: HashTableFilter/PerfectFilter/PerfectHashTableFilter  */
+  u32             ETH_HashTableHigh;             /* This field contains the higher 32 bits of Hash table.  */
+  u32             ETH_HashTableLow;              /* This field contains the lower 32 bits of Hash table.  */
+  u32             ETH_PauseTime;                 /* This field holds the value to be used in the Pause Time field in the transmit control frame */
+  u32             ETH_ZeroQuantaPause;           /* Enable/disable the automatic generation of Zero-Quanta Pause Control frames */
+  u32             ETH_PauseLowThreshold;         /* This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Frame */
+  u32             ETH_UnicastPauseFrameDetect;   /* Enable/disable MAC to detect the Pause frames (with MAC Address0 unicast address and unique multicast address) */
+  u32             ETH_ReceiveFlowControl;        /* Enable/disable the MAC to decode the received Pause frame and disable its transmitter for a specified (Pause Time) time */
+  u32             ETH_TransmitFlowControl;       /* Enable/disable the MAC to transmit Pause frames (Full-Duplex mode) or the MAC back-pressure operation (Half-Duplex mode) */
+  u32             ETH_VLANTagComparison;         /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for comparison and filtering */
+  u32             ETH_VLANTagIdentifier;         /* VLAN tag identifier for receive frames */
+
+  /* DMA --------------------------*/
+  u32             ETH_DropTCPIPChecksumErrorFrame; /* Enable/disable Dropping of TCP/IP Checksum Error Frames */
+  u32             ETH_ReceiveStoreForward;         /* Enable/disable Receive store and forward */
+  u32             ETH_FlushReceivedFrame;          /* Enable/disable flushing of received frames */
+  u32             ETH_TransmitStoreForward;        /* Enable/disable Transmit store and forward */
+  u32             ETH_TransmitThresholdControl;    /* Selects the Transmit Threshold Control */
+  u32             ETH_ForwardErrorFrames;          /* Enable/disable forward to DMA of all frames except runt error frames */
+  u32             ETH_ForwardUndersizedGoodFrames; /* Enable/disable Rx FIFO to forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC) */
+  u32             ETH_ReceiveThresholdControl;     /* Selects the threshold level of the Receive FIFO */
+  u32             ETH_SecondFrameOperate;          /* Enable/disable the DMA process of a second frame of Transmit	data even before status for first frame is obtained */
+  u32             ETH_AddressAlignedBeats;         /* Enable/disable Address Aligned Beats */
+  u32             ETH_FixedBurst;                  /* Enable/disable the AHB Master interface fixed burst transfers */
+  u32             ETH_RxDMABurstLength;            /* Indicate the maximum number of beats to be transferred in one Rx DMA transaction */
+  u32             ETH_TxDMABurstLength;            /* Indicate the maximum number of beats to be transferred in one Tx DMA transaction */
+  u32             ETH_DescriptorSkipLength;        /* Specifies the number of word to skip between two unchained descriptors (Ring mode) */
+  u32             ETH_DMAArbitration;              /* Selects DMA Tx/Rx arbitration */
+}ETH_InitTypeDef;
+
+/*----------------------------------------------------------------------------*/
+/*                          DMA descriptors types                             */
+/*----------------------------------------------------------------------------*/
+/* ETHERNET DMA Desciptors data structure definition  */
+typedef struct  {
+  volatile u32   Status;                /* Status */
+  volatile u32   ControlBufferSize;     /* Control and Buffer1, Buffer2 lengths */
+  volatile u32   Buffer1Addr;           /* Buffer1 address pointer */
+  volatile u32   Buffer2NextDescAddr;   /* Buffer2 or next descriptor address pointer */
+} ETH_DMADESCTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------*/
+/*                         ETHERNET Frames defines                            */
+/*----------------------------------------------------------------------------*/
+/* ENET Buffers setting */
+#define ETH_MAX_PACKET_SIZE    1520    /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER               14    /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC                   4    /* Ethernet CRC */
+#define ETH_EXTRA                 2    /* Extra bytes in some cases */
+#define VLAN_TAG                  4    /* optional 802.1q VLAN Tag */
+#define MIN_ETH_PAYLOAD          46    /* Minimum Ethernet payload size */
+#define MAX_ETH_PAYLOAD        1500    /* Maximum Ethernet payload size */
+#define JUMBO_FRAME_PAYLOAD    9000    /* Jumbo frame payload size */
+
+/*--------------------------------------------------------*/
+/*   Ethernet DMA descriptors registers bits definition   */
+/*--------------------------------------------------------*/
+/* DMA Tx Desciptor ---------------------------------------------------------*/
+/*-----------------------------------------------------------------------------------------------
+  TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |                                         |
+  -----------------------------------------------------------------------------------------------
+  TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
+  -----------------------------------------------------------------------------------------------
+  TDES2 |                         Buffer1 Address [31:0]                                         |
+  -----------------------------------------------------------------------------------------------
+  TDES3 |                   Buffer2 Address [31:0] / Next Desciptor Address [31:0]               |
+  ----------------------------------------------------------------------------------------------*/
+
+/* Bit definition of TDES0 register: DMA Tx descriptor status register */
+#define ETH_DMATxDesc_OWN   (0x80000000UL)  /* OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATxDesc_IC    ((u32)0x40000000)  /* Interrupt on Completion */
+#define ETH_DMATxDesc_LS    ((u32)0x20000000)  /* Last Segment */
+#define ETH_DMATxDesc_FS    ((u32)0x10000000)  /* First Segment */
+#define ETH_DMATxDesc_DC    ((u32)0x08000000)  /* Disable CRC */
+#define ETH_DMATxDesc_DP    ((u32)0x04000000)  /* Disable Padding */
+#define ETH_DMATxDesc_TTSE  ((u32)0x02000000)  /* Transmit Time Stamp Enable */
+#define ETH_DMATxDesc_CIC   ((u32)0x00C00000)  /* Checksum Insertion Control: 4 cases */
+  #define ETH_DMATxDesc_CIC_ByPass              ((u32)0x00000000)  /* Do Nothing: Checksum Engine is bypassed */
+  #define ETH_DMATxDesc_CIC_IPV4Header          ((u32)0x00400000)  /* IPV4 header Checksum Insertion */
+  #define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment  ((u32)0x00800000)  /* TCP/UDP/ICMP Checksum Insertion calculated over segment only */
+  #define ETH_DMATxDesc_CIC_TCPUDPICMP_Full     ((u32)0x00C00000)  /* TCP/UDP/ICMP Checksum Insertion fully calculated */
+#define ETH_DMATxDesc_TER   ((u32)0x00200000)  /* Transmit End of Ring */
+#define ETH_DMATxDesc_TCH   ((u32)0x00100000)  /* Second Address Chained */
+#define ETH_DMATxDesc_TTSS  ((u32)0x00020000)  /* Tx Time Stamp Status */
+#define ETH_DMATxDesc_IHE   ((u32)0x00010000)  /* IP Header Error */
+#define ETH_DMATxDesc_ES    ((u32)0x00008000)  /* Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
+#define ETH_DMATxDesc_JT    ((u32)0x00004000)  /* Jabber Timeout */
+#define ETH_DMATxDesc_FF    ((u32)0x00002000)  /* Frame Flushed: DMA/MTL flushed the frame due to SW flush */
+#define ETH_DMATxDesc_PCE   ((u32)0x00001000)  /* Payload Checksum Error */
+#define ETH_DMATxDesc_LCA   ((u32)0x00000800)  /* Loss of Carrier: carrier lost during tramsmission */
+#define ETH_DMATxDesc_NC    ((u32)0x00000400)  /* No Carrier: no carrier signal from the tranceiver */
+#define ETH_DMATxDesc_LCO   ((u32)0x00000200)  /* Late Collision: transmission aborted due to collision */
+#define ETH_DMATxDesc_EC    ((u32)0x00000100)  /* Excessive Collision: transmission aborted after 16 collisions */
+#define ETH_DMATxDesc_VF    ((u32)0x00000080)  /* VLAN Frame */
+#define ETH_DMATxDesc_CC    ((u32)0x00000078)  /* Collision Count */
+#define ETH_DMATxDesc_ED    ((u32)0x00000004)  /* Excessive Deferral */
+#define ETH_DMATxDesc_UF    ((u32)0x00000002)  /* Underflow Error: late data arrival from the memory */
+#define ETH_DMATxDesc_DB    ((u32)0x00000001)  /* Deferred Bit */
+
+/* Bit definition of TDES1 register */
+#define ETH_DMATxDesc_TBS2  ((u32)0x1FFF0000)  /* Transmit Buffer2 Size */
+#define ETH_DMATxDesc_TBS1  ((u32)0x00001FFF)  /* Transmit Buffer1 Size */
+
+/* Bit definition of TDES2 register */
+#define ETH_DMATxDesc_B1AP  ((u32)0xFFFFFFFF)  /* Buffer1 Address Pointer */
+
+/* Bit definition of TDES3 register */
+#define ETH_DMATxDesc_B2AP  ((u32)0xFFFFFFFF)  /* Buffer2 Address Pointer */
+
+/* DMA Rx descriptor ---------------------------------------------------------*/
+/*---------------------------------------------------------------------------------------------------------------------
+  RDES0 | OWN(31) |                                             Status [30:0]                                          |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES2 |                                       Buffer1 Address [31:0]                                                 |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES3 |                          Buffer2 Address [31:0] / Next Desciptor Address [31:0]                              |
+  --------------------------------------------------------------------------------------------------------------------*/
+
+/* Bit definition of RDES0 register: DMA Rx descriptor status register */
+#define ETH_DMARxDesc_OWN         ((u32)0x80000000)  /* OWN bit: descriptor is owned by DMA engine  */
+#define ETH_DMARxDesc_AFM         ((u32)0x40000000)  /* DA Filter Fail for the rx frame  */
+#define ETH_DMARxDesc_FL          ((u32)0x3FFF0000)  /* Receive descriptor frame length  */
+#define ETH_DMARxDesc_ES          ((u32)0x00008000)  /* Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
+#define ETH_DMARxDesc_DE          ((u32)0x00004000)  /* Desciptor error: no more descriptors for receive frame  */
+#define ETH_DMARxDesc_SAF         ((u32)0x00002000)  /* SA Filter Fail for the received frame */
+#define ETH_DMARxDesc_LE          ((u32)0x00001000)  /* Frame size not matching with length field */
+#define ETH_DMARxDesc_OE          ((u32)0x00000800)  /* Overflow Error: Frame was damaged due to buffer overflow */
+#define ETH_DMARxDesc_VLAN        ((u32)0x00000400)  /* VLAN Tag: received frame is a VLAN frame */
+#define ETH_DMARxDesc_FS          ((u32)0x00000200)  /* First descriptor of the frame  */
+#define ETH_DMARxDesc_LS          ((u32)0x00000100)  /* Last descriptor of the frame  */
+#define ETH_DMARxDesc_IPV4HCE     ((u32)0x00000080)  /* IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error   */
+#define ETH_DMARxDesc_RxLongFrame ((u32)0x00000080)  /* (Giant Frame)Rx - frame is longer than 1518/1522   */
+#define ETH_DMARxDesc_LC          ((u32)0x00000040)  /* Late collision occurred during reception   */
+#define ETH_DMARxDesc_FT          ((u32)0x00000020)  /* Frame type - Ethernet, otherwise 802.3    */
+#define ETH_DMARxDesc_RWT         ((u32)0x00000010)  /* Receive Watchdog Timeout: watchdog timer expired during reception    */
+#define ETH_DMARxDesc_RE          ((u32)0x00000008)  /* Receive error: error reported by MII interface  */
+#define ETH_DMARxDesc_DBE         ((u32)0x00000004)  /* Dribble bit error: frame contains non int multiple of 8 bits  */
+#define ETH_DMARxDesc_CE          ((u32)0x00000002)  /* CRC error */
+#define ETH_DMARxDesc_MAMPCE      ((u32)0x00000001)  /* Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
+
+/* Bit definition of RDES1 register */
+#define ETH_DMARxDesc_DIC   ((u32)0x80000000)  /* Disable Interrupt on Completion */
+#define ETH_DMARxDesc_RBS2  ((u32)0x1FFF0000)  /* Receive Buffer2 Size */
+#define ETH_DMARxDesc_RER   ((u32)0x00008000)  /* Receive End of Ring */
+#define ETH_DMARxDesc_RCH   ((u32)0x00004000)  /* Second Address Chained */
+#define ETH_DMARxDesc_RBS1  ((u32)0x00001FFF)  /* Receive Buffer1 Size */
+
+/* Bit definition of RDES2 register */
+#define ETH_DMARxDesc_B1AP  ((u32)0xFFFFFFFF)  /* Buffer1 Address Pointer */
+
+/* Bit definition of RDES3 register */
+#define ETH_DMARxDesc_B2AP  ((u32)0xFFFFFFFF)  /* Buffer2 Address Pointer */
+
+/*----------------------------------------------------------------------------*/
+/*                   Desciption of common PHY registers                      */
+/*----------------------------------------------------------------------------*/
+/* PHY Read/write Timeouts */
+#define PHY_READ_TO                     ((u32)0x0004FFFF)
+#define PHY_WRITE_TO                    ((u32)0x0004FFFF)
+
+/* PHY Reset Delay */
+#define PHY_ResetDelay                  ((u32)0x000FFFFF)
+
+/* PHY Config Delay */
+#define PHY_ConfigDelay                 ((u32)0x00FFFFFF)
+
+/* PHY Register address */
+#define PHY_BCR                          0          /* Tranceiver Basic Control Register */
+#define PHY_BSR                          1          /* Tranceiver Basic Status Register */
+
+/* PHY basic Control register */
+#define PHY_Reset                       ((u16)0x8000)      /* PHY Reset */
+#define PHY_Loopback                    ((u16)0x4000)      /* Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((u16)0x2100)      /* Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((u16)0x2000)      /* Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((u16)0x0100)      /* Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M              ((u16)0x0000)      /* Set the half-duplex mode at 10 Mb/s */
+#define PHY_AutoNegotiation             ((u16)0x1000)      /* Enable auto-negotiation function */
+#define PHY_Restart_AutoNegotiation     ((u16)0x0200)      /* Restart auto-negotiation function */
+#define PHY_Powerdown                   ((u16)0x0800)      /* Select the power down mode */
+#define PHY_Isolate                     ((u16)0x0400)      /* Isolate PHY from MII */
+
+/* PHY basic status register */
+#define PHY_AutoNego_Complete           ((u16)0x0020)      /* Auto-Negotioation process completed */
+#define PHY_Linked_Status               ((u16)0x0004)      /* Valid link established */
+#define PHY_Jabber_detection            ((u16)0x0002)      /* Jabber condition detected */
+
+/* The PHY status register value change from a PHY to another so the user have to update
+   this value depending on the used external PHY */
+/* For LAN8700 */
+//#define PHY_SR                           31         /* Tranceiver Status Register */
+/* For DP83848 */
+#define PHY_SR                           16      /* Tranceiver Status Register */
+
+/* PHY status register */
+/* The Speed and Duplex mask values change from a PHY to another so the user have to update
+   this value depending on the used external PHY */
+/* For LAN8700 */
+//#define PHY_Speed_Status            ((u16)0x0004)       /* Configured information of Speed: 10Mbps */
+//#define PHY_Duplex_Status           ((u16)0x0010)       /* Configured information of Duplex: Full-duplex */
+/* For DP83848 */
+#define PHY_Speed_Status            ((u16)0x0002)    /* Configured information of Speed: 10Mbps */
+#define PHY_Duplex_Status           ((u16)0x0004)    /* Configured information of Duplex: Full-duplex */
+
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
+#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \
+                             ((REG) == PHY_BSR) || \
+                             ((REG) == PHY_SR))
+
+/*----------------------------------------------------------------------------*/
+/*                                 MAC defines                                */
+/*----------------------------------------------------------------------------*/
+/* ETHERNET AutoNegotiation --------------------------------------------------*/
+#define ETH_AutoNegotiation_Enable     ((u32)0x00000001)
+#define ETH_AutoNegotiation_Disable    ((u32)0x00000000)
+
+#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \
+                                     ((CMD) == ETH_AutoNegotiation_Disable))
+
+/* ETHERNET watchdog ---------------------------------------------------------*/
+#define ETH_Watchdog_Enable       ((u32)0x00000000)
+#define ETH_Watchdog_Disable      ((u32)0x00800000)
+
+#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \
+                              ((CMD) == ETH_Watchdog_Disable))
+
+/* ETHERNET Jabber -----------------------------------------------------------*/
+#define ETH_Jabber_Enable    ((u32)0x00000000)
+#define ETH_Jabber_Disable   ((u32)0x00400000)
+
+#define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \
+                            ((CMD) == ETH_Jabber_Disable))
+
+/* ETHERNET Jumbo Frame ------------------------------------------------------*/
+#define ETH_JumboFrame_Enable     ((u32)0x00100000)
+#define ETH_JumboFrame_Disable    ((u32)0x00000000)
+
+#define IS_ETH_JUMBO_FRAME(CMD) (((CMD) == ETH_JumboFrame_Enable) || \
+                                 ((CMD) == ETH_JumboFrame_Disable))
+
+/* ETHERNET Inter Frame Gap --------------------------------------------------*/
+#define ETH_InterFrameGap_96Bit   ((u32)0x00000000)  /* minimum IFG between frames during transmission is 96Bit */
+#define ETH_InterFrameGap_88Bit   ((u32)0x00020000)  /* minimum IFG between frames during transmission is 88Bit */
+#define ETH_InterFrameGap_80Bit   ((u32)0x00040000)  /* minimum IFG between frames during transmission is 80Bit */
+#define ETH_InterFrameGap_72Bit   ((u32)0x00060000)  /* minimum IFG between frames during transmission is 72Bit */
+#define ETH_InterFrameGap_64Bit   ((u32)0x00080000)  /* minimum IFG between frames during transmission is 64Bit */
+#define ETH_InterFrameGap_56Bit   ((u32)0x000A0000)  /* minimum IFG between frames during transmission is 56Bit */
+#define ETH_InterFrameGap_48Bit   ((u32)0x000C0000)  /* minimum IFG between frames during transmission is 48Bit */
+#define ETH_InterFrameGap_40Bit   ((u32)0x000E0000)  /* minimum IFG between frames during transmission is 40Bit */
+
+#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_88Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_80Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_72Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_64Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_56Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_48Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_40Bit))
+
+/* ETHERNET Carrier Sense ----------------------------------------------------*/
+#define ETH_CarrierSense_Enable   ((u32)0x00000000)
+#define ETH_CarrierSense_Disable  ((u32)0x00010000)
+
+#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \
+                                   ((CMD) == ETH_CarrierSense_Disable))
+
+/* ETHERNET Speed ------------------------------------------------------------*/
+#define ETH_Speed_10M        ((u32)0x00000000)
+#define ETH_Speed_100M       ((u32)0x00004000)
+
+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \
+                             ((SPEED) == ETH_Speed_100M))
+
+/* ETHERNET Receive Own ------------------------------------------------------*/
+#define ETH_ReceiveOwn_Enable     ((u32)0x00000000)
+#define ETH_ReceiveOwn_Disable    ((u32)0x00002000)
+
+#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \
+                                 ((CMD) == ETH_ReceiveOwn_Disable))
+
+/* ETHERNET Loop back Mode ---------------------------------------------------*/
+#define ETH_LoopbackMode_Enable        ((u32)0x00001000)
+#define ETH_LoopbackMode_Disable       ((u32)0x00000000)
+
+#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \
+                                   ((CMD) == ETH_LoopbackMode_Disable))
+
+/* ETHERNET Duplex mode ------------------------------------------------------*/
+#define ETH_Mode_FullDuplex       ((u32)0x00000800)
+#define ETH_Mode_HalfDuplex       ((u32)0x00000000)
+
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \
+                                  ((MODE) == ETH_Mode_HalfDuplex))
+
+/* ETHERNET Checksum Offload -------------------------------------------------*/
+#define ETH_ChecksumOffload_Enable     ((u32)0x00000400)
+#define ETH_ChecksumOffload_Disable    ((u32)0x00000000)
+
+#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \
+                                      ((CMD) == ETH_ChecksumOffload_Disable))
+
+/* ETHERNET Retry Transmission -----------------------------------------------*/
+#define ETH_RetryTransmission_Enable   ((u32)0x00000000)
+#define ETH_RetryTransmission_Disable  ((u32)0x00000200)
+
+#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \
+                                        ((CMD) == ETH_RetryTransmission_Disable))
+
+/* ETHERNET Automatic Pad/CRC Strip ------------------------------------------*/
+#define ETH_AutomaticPadCRCStrip_Enable     ((u32)0x00000080)
+#define ETH_AutomaticPadCRCStrip_Disable    ((u32)0x00000000)
+
+#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \
+                                            ((CMD) == ETH_AutomaticPadCRCStrip_Disable))
+
+/* ETHERNET Back-Off limit ---------------------------------------------------*/
+#define ETH_BackOffLimit_10  ((u32)0x00000000)
+#define ETH_BackOffLimit_8   ((u32)0x00000020)
+#define ETH_BackOffLimit_4   ((u32)0x00000040)
+#define ETH_BackOffLimit_1   ((u32)0x00000060)
+
+#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \
+                                     ((LIMIT) == ETH_BackOffLimit_8) || \
+                                     ((LIMIT) == ETH_BackOffLimit_4) || \
+                                     ((LIMIT) == ETH_BackOffLimit_1))
+
+/* ETHERNET Deferral Check ---------------------------------------------------*/
+#define ETH_DeferralCheck_Enable       ((u32)0x00000010)
+#define ETH_DeferralCheck_Disable      ((u32)0x00000000)
+
+#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \
+                                    ((CMD) == ETH_DeferralCheck_Disable))
+
+/* ETHERNET Receive All ------------------------------------------------------*/
+#define ETH_ReceiveAll_Enable     ((u32)0x80000000)
+#define ETH_ReceiveAll_Disable    ((u32)0x00000000)
+
+#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \
+                                 ((CMD) == ETH_ReceiveAll_Disable))
+
+/* ETHERNET Source Addr Filter ------------------------------------------------*/
+#define ETH_SourceAddrFilter_Normal_Enable       ((u32)0x00000200)
+#define ETH_SourceAddrFilter_Inverse_Enable      ((u32)0x00000300)
+#define ETH_SourceAddrFilter_Disable             ((u32)0x00000000)
+
+#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \
+                                        ((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \
+                                        ((CMD) == ETH_SourceAddrFilter_Disable))
+
+/* ETHERNET Pass Control Frames ----------------------------------------------*/
+#define ETH_PassControlFrames_BlockAll                ((u32)0x00000040)  /* MAC filters all control frames from reaching the application */
+#define ETH_PassControlFrames_ForwardAll              ((u32)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_PassControlFrames_ForwardPassedAddrFilter ((u32)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */
+
+#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \
+                                     ((PASS) == ETH_PassControlFrames_ForwardAll) || \
+                                     ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter))
+
+/* ETHERNET Broadcast Frames Reception ---------------------------------------*/
+#define ETH_BroadcastFramesReception_Enable      ((u32)0x00000000)
+#define ETH_BroadcastFramesReception_Disable     ((u32)0x00000020)
+
+#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \
+                                                ((CMD) == ETH_BroadcastFramesReception_Disable))
+
+/* ETHERNET Destination Addr Filter ------------------------------------------*/
+#define ETH_DestinationAddrFilter_Normal    ((u32)0x00000000)
+#define ETH_DestinationAddrFilter_Inverse   ((u32)0x00000008)
+
+#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \
+                                                ((FILTER) == ETH_DestinationAddrFilter_Inverse))
+
+/* ETHERNET Promiscuous Mode -------------------------------------------------*/
+#define ETH_PromiscuousMode_Enable     ((u32)0x00000001)
+#define ETH_PromiscuousMode_Disable    ((u32)0x00000000)
+
+#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \
+                                      ((CMD) == ETH_PromiscuousMode_Disable))
+
+/* ETHERNET multicast frames filter --------------------------------------------*/
+#define ETH_MulticastFramesFilter_PerfectHashTable    ((u32)0x00000404)
+#define ETH_MulticastFramesFilter_HashTable           ((u32)0x00000004)
+#define ETH_MulticastFramesFilter_Perfect             ((u32)0x00000000)
+#define ETH_MulticastFramesFilter_None                ((u32)0x00000010)
+
+#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \
+                                                ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \
+                                                ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \
+                                                ((FILTER) == ETH_MulticastFramesFilter_None))
+
+/* ETHERNET unicast frames filter --------------------------------------------*/
+#define ETH_UnicastFramesFilter_PerfectHashTable ((u32)0x00000402)
+#define ETH_UnicastFramesFilter_HashTable        ((u32)0x00000002)
+#define ETH_UnicastFramesFilter_Perfect          ((u32)0x00000000)
+
+#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \
+                                              ((FILTER) == ETH_UnicastFramesFilter_HashTable) || \
+                                              ((FILTER) == ETH_UnicastFramesFilter_Perfect))
+
+/* ETHERNET Pause Time ------------------------------------------------*/
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
+
+/* ETHERNET Zero Quanta Pause ------------------------------------------------*/
+#define ETH_ZeroQuantaPause_Enable     ((u32)0x00000000)
+#define ETH_ZeroQuantaPause_Disable    ((u32)0x00000080)
+
+#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZeroQuantaPause_Enable) || \
+                                      ((CMD) == ETH_ZeroQuantaPause_Disable))
+
+/* ETHERNET Pause Low Threshold ----------------------------------------------*/
+#define ETH_PauseLowThreshold_Minus4        ((u32)0x00000000)  /* Pause time minus 4 slot times */
+#define ETH_PauseLowThreshold_Minus28       ((u32)0x00000010)  /* Pause time minus 28 slot times */
+#define ETH_PauseLowThreshold_Minus144      ((u32)0x00000020)  /* Pause time minus 144 slot times */
+#define ETH_PauseLowThreshold_Minus256      ((u32)0x00000030)  /* Pause time minus 256 slot times */
+
+#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \
+                                               ((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \
+                                               ((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \
+                                               ((THRESHOLD) == ETH_PauseLowThreshold_Minus256))
+
+/* ETHERNET Unicast Pause Frame Detect ---------------------------------------*/
+#define ETH_UnicastPauseFrameDetect_Enable  ((u32)0x00000008)
+#define ETH_UnicastPauseFrameDetect_Disable ((u32)0x00000000)
+
+#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \
+                                                ((CMD) == ETH_UnicastPauseFrameDetect_Disable))
+
+/* ETHERNET Receive Flow Control ---------------------------------------------*/
+#define ETH_ReceiveFlowControl_Enable       ((u32)0x00000004)
+#define ETH_ReceiveFlowControl_Disable      ((u32)0x00000000)
+
+#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \
+                                         ((CMD) == ETH_ReceiveFlowControl_Disable))
+
+/* ETHERNET Transmit Flow Control --------------------------------------------*/
+#define ETH_TransmitFlowControl_Enable      ((u32)0x00000002)
+#define ETH_TransmitFlowControl_Disable     ((u32)0x00000000)
+
+#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \
+                                          ((CMD) == ETH_TransmitFlowControl_Disable))
+
+/* ETHERNET VLAN Tag Comparison ----------------------------------------------*/
+#define ETH_VLANTagComparison_12Bit    ((u32)0x00010000)
+#define ETH_VLANTagComparison_16Bit    ((u32)0x00000000)
+
+#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \
+                                                ((COMPARISON) == ETH_VLANTagComparison_16Bit))
+
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
+
+/* ETHERNET MAC Flags ---------------------------------------------------*/
+#define ETH_MAC_FLAG_TST     ((u32)0x00000200)  /* Time stamp trigger flag (on MAC) */
+#define ETH_MAC_FLAG_MMCT    ((u32)0x00000040)  /* MMC transmit flag  */
+#define ETH_MAC_FLAG_MMCR    ((u32)0x00000020)  /* MMC receive flag */
+#define ETH_MAC_FLAG_MMC     ((u32)0x00000010)  /* MMC flag (on MAC) */
+#define ETH_MAC_FLAG_PMT     ((u32)0x00000008)  /* PMT flag (on MAC) */
+
+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
+                                   ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
+                                   ((FLAG) == ETH_MAC_FLAG_PMT))
+
+/* ETHERNET MAC Interrupts ---------------------------------------------------*/
+#define ETH_MAC_IT_TST       ((u32)0x00000200)  /* Time stamp trigger interrupt (on MAC) */
+#define ETH_MAC_IT_MMCT      ((u32)0x00000040)  /* MMC transmit interrupt */
+#define ETH_MAC_IT_MMCR      ((u32)0x00000020)  /* MMC receive interrupt */
+#define ETH_MAC_IT_MMC       ((u32)0x00000010)  /* MMC interrupt (on MAC) */
+#define ETH_MAC_IT_PMT       ((u32)0x00000008)  /* PMT interrupt (on MAC) */
+
+#define IS_ETH_MAC_IT(IT) ((((IT) & (u32)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
+                               ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
+                               ((IT) == ETH_MAC_IT_PMT))
+
+/* ETHERNET MAC addresses ----------------------------------------------------*/
+#define ETH_MAC_Address0     ((u32)0x00000000)
+#define ETH_MAC_Address1     ((u32)0x00000008)
+#define ETH_MAC_Address2     ((u32)0x00000010)
+#define ETH_MAC_Address3     ((u32)0x00000018)
+
+#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \
+                                         ((ADDRESS) == ETH_MAC_Address1) || \
+                                         ((ADDRESS) == ETH_MAC_Address2) || \
+                                         ((ADDRESS) == ETH_MAC_Address3))
+
+#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \
+                                        ((ADDRESS) == ETH_MAC_Address2) || \
+                                        ((ADDRESS) == ETH_MAC_Address3))
+
+/* ETHERNET MAC addresses filter: SA/DA filed of received frames ------------*/
+#define ETH_MAC_AddressFilter_SA       ((u32)0x00000000)
+#define ETH_MAC_AddressFilter_DA       ((u32)0x00000008)
+
+#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \
+                                           ((FILTER) == ETH_MAC_AddressFilter_DA))
+
+/* ETHERNET MAC addresses filter: Mask bytes ---------------------------------*/
+#define ETH_MAC_AddressMask_Byte6      ((u32)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MAC_AddressMask_Byte5      ((u32)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MAC_AddressMask_Byte4      ((u32)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MAC_AddressMask_Byte3      ((u32)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MAC_AddressMask_Byte2      ((u32)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MAC_AddressMask_Byte1      ((u32)0x01000000)  /* Mask MAC Address low reg bits [70] */
+
+#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \
+                                       ((MASK) == ETH_MAC_AddressMask_Byte5) || \
+                                       ((MASK) == ETH_MAC_AddressMask_Byte4) || \
+                                       ((MASK) == ETH_MAC_AddressMask_Byte3) || \
+                                       ((MASK) == ETH_MAC_AddressMask_Byte2) || \
+                                       ((MASK) == ETH_MAC_AddressMask_Byte1))
+
+/*----------------------------------------------------------------------------*/
+/*                     Ethernet DMA Desciptors defines                       */
+/*----------------------------------------------------------------------------*/
+/* ETHERNET DMA Tx descriptor flags  --------------------------------------------------------*/
+#define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \
+                                         ((FLAG) == ETH_DMATxDesc_IC) || \
+                                         ((FLAG) == ETH_DMATxDesc_LS) || \
+                                         ((FLAG) == ETH_DMATxDesc_FS) || \
+                                         ((FLAG) == ETH_DMATxDesc_DC) || \
+                                         ((FLAG) == ETH_DMATxDesc_DP) || \
+                                         ((FLAG) == ETH_DMATxDesc_TTSE) || \
+                                         ((FLAG) == ETH_DMATxDesc_TER) || \
+                                         ((FLAG) == ETH_DMATxDesc_TCH) || \
+                                         ((FLAG) == ETH_DMATxDesc_TTSS) || \
+                                         ((FLAG) == ETH_DMATxDesc_IHE) || \
+                                         ((FLAG) == ETH_DMATxDesc_ES) || \
+                                         ((FLAG) == ETH_DMATxDesc_JT) || \
+                                         ((FLAG) == ETH_DMATxDesc_FF) || \
+                                         ((FLAG) == ETH_DMATxDesc_PCE) || \
+                                         ((FLAG) == ETH_DMATxDesc_LCA) || \
+                                         ((FLAG) == ETH_DMATxDesc_NC) || \
+                                         ((FLAG) == ETH_DMATxDesc_LCO) || \
+                                         ((FLAG) == ETH_DMATxDesc_EC) || \
+                                         ((FLAG) == ETH_DMATxDesc_VF) || \
+                                         ((FLAG) == ETH_DMATxDesc_CC) || \
+                                         ((FLAG) == ETH_DMATxDesc_ED) || \
+                                         ((FLAG) == ETH_DMATxDesc_UF) || \
+                                         ((FLAG) == ETH_DMATxDesc_DB))
+
+/* ETHERNET DMA Tx descriptor segment ----------------------------------------*/
+#define ETH_DMATxDesc_LastSegment      ((u32)0x40000000)  /* Last Segment */
+#define ETH_DMATxDesc_FirstSegment     ((u32)0x20000000)  /* First Segment */
+
+#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \
+                                            ((SEGMENT) == ETH_DMATxDesc_FirstSegment))
+
+/* ETHERNET DMA Tx descriptor Checksum Insertion Control  --------------------*/
+#define ETH_DMATxDesc_ChecksumByPass             ((u32)0x00000000)   /* Checksum engine bypass */
+#define ETH_DMATxDesc_ChecksumIPV4Header         ((u32)0x00400000)   /* IPv4 header checksum insertion  */
+#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment  ((u32)0x00800000)   /* TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
+#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull     ((u32)0x00C00000)   /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */
+
+#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \
+                                              ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \
+                                              ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \
+                                              ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull))
+
+/* ETHERNET DMA Tx Desciptor buffer size */
+#define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
+
+/* ETHERNET DMA Rx descriptor flags  --------------------------------------------------------*/
+#define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \
+                                         ((FLAG) == ETH_DMARxDesc_AFM) || \
+                                         ((FLAG) == ETH_DMARxDesc_ES) || \
+                                         ((FLAG) == ETH_DMARxDesc_DE) || \
+                                         ((FLAG) == ETH_DMARxDesc_SAF) || \
+                                         ((FLAG) == ETH_DMARxDesc_LE) || \
+                                         ((FLAG) == ETH_DMARxDesc_OE) || \
+                                         ((FLAG) == ETH_DMARxDesc_VLAN) || \
+                                         ((FLAG) == ETH_DMARxDesc_FS) || \
+                                         ((FLAG) == ETH_DMARxDesc_LS) || \
+                                         ((FLAG) == ETH_DMARxDesc_IPV4HCE) || \
+                                         ((FLAG) == ETH_DMARxDesc_RxLongFrame) || \
+                                         ((FLAG) == ETH_DMARxDesc_LC) || \
+                                         ((FLAG) == ETH_DMARxDesc_FT) || \
+                                         ((FLAG) == ETH_DMARxDesc_RWT) || \
+                                         ((FLAG) == ETH_DMARxDesc_RE) || \
+                                         ((FLAG) == ETH_DMARxDesc_DBE) || \
+                                         ((FLAG) == ETH_DMARxDesc_CE) || \
+                                         ((FLAG) == ETH_DMARxDesc_MAMPCE))
+
+/* ETHERNET DMA Rx descriptor buffers  ---------------------------------------*/
+#define ETH_DMARxDesc_Buffer1     ((u32)0x00000000)  /* DMA Rx Desc Buffer1 */
+#define ETH_DMARxDesc_Buffer2     ((u32)0x00000001)  /* DMA Rx Desc Buffer2 */
+
+#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \
+                                          ((BUFFER) == ETH_DMARxDesc_Buffer2))
+
+/*----------------------------------------------------------------------------*/
+/*                          Ethernet DMA defines                              */
+/*----------------------------------------------------------------------------*/
+/* ETHERNET Drop TCP/IP Checksum Error Frame ---------------------------------*/
+#define ETH_DropTCPIPChecksumErrorFrame_Enable   ((u32)0x00000000)
+#define ETH_DropTCPIPChecksumErrorFrame_Disable  ((u32)0x04000000)
+
+#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \
+                                               ((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable))
+
+/* ETHERNET Receive Store Forward --------------------------------------------*/
+#define ETH_ReceiveStoreForward_Enable      ((u32)0x02000000)
+#define ETH_ReceiveStoreForward_Disable     ((u32)0x00000000)
+
+#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \
+                                           ((CMD) == ETH_ReceiveStoreForward_Disable))
+
+/* ETHERNET Flush Received Frame ---------------------------------------------*/
+#define ETH_FlushReceivedFrame_Enable       ((u32)0x00000000)
+#define ETH_FlushReceivedFrame_Disable      ((u32)0x01000000)
+
+#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \
+                                         ((CMD) == ETH_FlushReceivedFrame_Disable))
+
+/* ETHERNET Transmit Store Forward -------------------------------------------*/
+#define ETH_TransmitStoreForward_Enable     ((u32)0x00200000)
+#define ETH_TransmitStoreForward_Disable    ((u32)0x00000000)
+
+#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \
+                                            ((CMD) == ETH_TransmitStoreForward_Disable))
+
+/* ETHERNET Transmit Threshold Control ---------------------------------------*/
+#define ETH_TransmitThresholdControl_64Bytes     ((u32)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_TransmitThresholdControl_128Bytes    ((u32)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_TransmitThresholdControl_192Bytes    ((u32)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_TransmitThresholdControl_256Bytes    ((u32)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_TransmitThresholdControl_40Bytes     ((u32)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_TransmitThresholdControl_32Bytes     ((u32)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_TransmitThresholdControl_24Bytes     ((u32)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_TransmitThresholdControl_16Bytes     ((u32)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+
+#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes))
+
+/* ETHERNET Forward Error Frames ---------------------------------------------*/
+#define ETH_ForwardErrorFrames_Enable       ((u32)0x00000080)
+#define ETH_ForwardErrorFrames_Disable      ((u32)0x00000000)
+
+#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \
+                                          ((CMD) == ETH_ForwardErrorFrames_Disable))
+
+/* ETHERNET Forward Undersized Good Frames -----------------------------------*/
+#define ETH_ForwardUndersizedGoodFrames_Enable   ((u32)0x00000040)
+#define ETH_ForwardUndersizedGoodFrames_Disable  ((u32)0x00000000)
+
+#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \
+                                                    ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable))
+
+/* ETHERNET Receive Threshold Control ----------------------------------------*/
+#define ETH_ReceiveThresholdControl_64Bytes      ((u32)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_ReceiveThresholdControl_32Bytes      ((u32)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_ReceiveThresholdControl_96Bytes      ((u32)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_ReceiveThresholdControl_128Bytes     ((u32)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
+
+#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \
+                                                     ((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \
+                                                     ((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \
+                                                     ((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes))
+
+/* ETHERNET Second Frame Operate ---------------------------------------------*/
+#define ETH_SecondFrameOperate_Enable       ((u32)0x00000004)
+#define ETH_SecondFrameOperate_Disable      ((u32)0x00000000)
+
+#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \
+                                          ((CMD) == ETH_SecondFrameOperate_Disable))
+
+/* ETHERNET Address Aligned Beats --------------------------------------------*/
+#define ETH_AddressAlignedBeats_Enable      ((u32)0x02000000)
+#define ETH_AddressAlignedBeats_Disable     ((u32)0x00000000)
+
+#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \
+                                           ((CMD) == ETH_AddressAlignedBeats_Disable))
+
+/* ETHERNET Fixed Burst ------------------------------------------------------*/
+#define ETH_FixedBurst_Enable     ((u32)0x00010000)
+#define ETH_FixedBurst_Disable    ((u32)0x00000000)
+
+#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \
+                                 ((CMD) == ETH_FixedBurst_Disable))
+
+/* ETHERNET Rx DMA Burst Length ----------------------------------------------*/
+#define ETH_RxDMABurstLength_1Beat     ((u32)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_RxDMABurstLength_2Beat     ((u32)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_RxDMABurstLength_4Beat     ((u32)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RxDMABurstLength_8Beat     ((u32)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RxDMABurstLength_16Beat    ((u32)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RxDMABurstLength_32Beat    ((u32)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+
+#define ETH_RxDMABurstLength_4xPBL_4Beat    ((u32)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RxDMABurstLength_4xPBL_8Beat    ((u32)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RxDMABurstLength_4xPBL_16Beat   ((u32)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RxDMABurstLength_4xPBL_32Beat   ((u32)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RxDMABurstLength_4xPBL_64Beat   ((u32)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_RxDMABurstLength_4xPBL_128Beat  ((u32)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+
+#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_2Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_8Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_16Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_32Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat))
+
+/* ETHERNET Tx DMA Burst Length ----------------------------------------------*/
+#define ETH_TxDMABurstLength_1Beat     ((u32)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_TxDMABurstLength_2Beat     ((u32)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_TxDMABurstLength_4Beat     ((u32)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TxDMABurstLength_8Beat     ((u32)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TxDMABurstLength_16Beat    ((u32)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TxDMABurstLength_32Beat    ((u32)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+
+#define ETH_TxDMABurstLength_4xPBL_4Beat    ((u32)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TxDMABurstLength_4xPBL_8Beat    ((u32)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TxDMABurstLength_4xPBL_16Beat   ((u32)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TxDMABurstLength_4xPBL_32Beat   ((u32)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TxDMABurstLength_4xPBL_64Beat   ((u32)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_TxDMABurstLength_4xPBL_128Beat  ((u32)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+
+#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_2Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_8Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_16Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_32Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat))
+
+/* ETHERNET DMA Desciptor SkipLength */
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
+
+/* ETHERNET DMA Arbitration --------------------------------------------------*/
+#define ETH_DMAArbitration_RoundRobin_RxTx_1_1   ((u32)0x00000000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_2_1   ((u32)0x00004000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_3_1   ((u32)0x00008000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_4_1   ((u32)0x0000C000)
+#define ETH_DMAArbitration_RxPriorTx             ((u32)0x00000002)
+
+#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \
+                                                       ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \
+                                                       ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \
+                                                       ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \
+                                                       ((RATIO) == ETH_DMAArbitration_RxPriorTx))
+
+/* ETHERNET DMA Flags ---------------------------------------------------*/
+#define ETH_DMA_FLAG_TST     ((u32)0x20000000)  /* Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_FLAG_PMT     ((u32)0x10000000)  /* PMT interrupt (on DMA) */
+#define ETH_DMA_FLAG_MMC     ((u32)0x08000000)  /* MMC interrupt (on DMA) */
+
+#define ETH_DMA_FLAG_DataTransferError ((u32)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMA_FLAG_ReadWriteError    ((u32)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */
+#define ETH_DMA_FLAG_AccessError       ((u32)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMA_FLAG_NIS     ((u32)0x00010000)  /* Normal interrupt summary flag */
+#define ETH_DMA_FLAG_AIS     ((u32)0x00008000)  /* Abnormal interrupt summary flag */
+#define ETH_DMA_FLAG_ER      ((u32)0x00004000)  /* Early receive flag */
+#define ETH_DMA_FLAG_FBE     ((u32)0x00002000)  /* Fatal bus error flag */
+#define ETH_DMA_FLAG_ET      ((u32)0x00000400)  /* Early transmit flag */
+#define ETH_DMA_FLAG_RWT     ((u32)0x00000200)  /* Receive watchdog timeout flag */
+#define ETH_DMA_FLAG_RPS     ((u32)0x00000100)  /* Receive process stopped flag */
+#define ETH_DMA_FLAG_RBU     ((u32)0x00000080)  /* Receive buffer unavailable flag */
+#define ETH_DMA_FLAG_R       ((u32)0x00000040)  /* Receive flag */
+#define ETH_DMA_FLAG_TU      ((u32)0x00000020)  /* Underflow flag */
+#define ETH_DMA_FLAG_RO      ((u32)0x00000010)  /* Overflow flag */
+#define ETH_DMA_FLAG_TJT     ((u32)0x00000008)  /* Transmit jabber timeout flag */
+#define ETH_DMA_FLAG_TBU     ((u32)0x00000004)  /* Transmit buffer unavailable flag */
+#define ETH_DMA_FLAG_TPS     ((u32)0x00000002)  /* Transmit process stopped flag */
+#define ETH_DMA_FLAG_T       ((u32)0x00000001)  /* Transmit flag */
+
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (u32)0xFFFE1800) == 0x00) && ((FLAG) != 0x00))
+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
+                                   ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \
+                                   ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \
+                                   ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
+                                   ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
+                                   ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
+                                   ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
+                                   ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
+                                   ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
+                                   ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
+                                   ((FLAG) == ETH_DMA_FLAG_T))
+
+/* ETHERNET DMA Interrupts ---------------------------------------------------*/
+#define ETH_DMA_IT_TST       ((u32)0x20000000)  /* Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_IT_PMT       ((u32)0x10000000)  /* PMT interrupt (on DMA) */
+#define ETH_DMA_IT_MMC       ((u32)0x08000000)  /* MMC interrupt (on DMA) */
+
+#define ETH_DMA_IT_NIS       ((u32)0x00010000)  /* Normal interrupt summary */
+#define ETH_DMA_IT_AIS       ((u32)0x00008000)  /* Abnormal interrupt summary */
+#define ETH_DMA_IT_ER        ((u32)0x00004000)  /* Early receive interrupt */
+#define ETH_DMA_IT_FBE       ((u32)0x00002000)  /* Fatal bus error interrupt */
+#define ETH_DMA_IT_ET        ((u32)0x00000400)  /* Early transmit interrupt */
+#define ETH_DMA_IT_RWT       ((u32)0x00000200)  /* Receive watchdog timeout interrupt */
+#define ETH_DMA_IT_RPS       ((u32)0x00000100)  /* Receive process stopped interrupt */
+#define ETH_DMA_IT_RBU       ((u32)0x00000080)  /* Receive buffer unavailable interrupt */
+#define ETH_DMA_IT_R         ((u32)0x00000040)  /* Receive interrupt */
+#define ETH_DMA_IT_TU        ((u32)0x00000020)  /* Underflow interrupt */
+#define ETH_DMA_IT_RO        ((u32)0x00000010)  /* Overflow interrupt */
+#define ETH_DMA_IT_TJT       ((u32)0x00000008)  /* Transmit jabber timeout interrupt */
+#define ETH_DMA_IT_TBU       ((u32)0x00000004)  /* Transmit buffer unavailable interrupt */
+#define ETH_DMA_IT_TPS       ((u32)0x00000002)  /* Transmit process stopped interrupt */
+#define ETH_DMA_IT_T         ((u32)0x00000001)  /* Transmit interrupt */
+
+#define IS_ETH_DMA_IT(IT) ((((IT) & (u32)0xFFFE1800) == 0x00) && ((IT) != 0x00))
+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
+                               ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
+                               ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
+                               ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
+                               ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
+                               ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
+                               ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
+                               ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
+                               ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
+
+/* ETHERNET DMA transmit process state  --------------------------------------------------------*/
+#define ETH_DMA_TransmitProcess_Stopped     ((u32)0x00000000)  /* Stopped - Reset or Stop Tx Command issued */
+#define ETH_DMA_TransmitProcess_Fetching    ((u32)0x00100000)  /* Running - fetching the Tx descriptor */
+#define ETH_DMA_TransmitProcess_Waiting     ((u32)0x00200000)  /* Running - waiting for status */
+#define ETH_DMA_TransmitProcess_Reading     ((u32)0x00300000)  /* Running - reading the data from host memory */
+#define ETH_DMA_TransmitProcess_Suspended   ((u32)0x00600000)  /* Suspended - Tx Desciptor unavailabe */
+#define ETH_DMA_TransmitProcess_Closing     ((u32)0x00700000)  /* Running - closing Rx descriptor */
+
+/* ETHERNET DMA receive process state  --------------------------------------------------------*/
+#define ETH_DMA_ReceiveProcess_Stopped      ((u32)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMA_ReceiveProcess_Fetching     ((u32)0x00020000)  /* Running - fetching the Rx descriptor */
+#define ETH_DMA_ReceiveProcess_Waiting      ((u32)0x00060000)  /* Running - waiting for packet */
+#define ETH_DMA_ReceiveProcess_Suspended    ((u32)0x00080000)  /* Suspended - Rx Desciptor unavailable */
+#define ETH_DMA_ReceiveProcess_Closing      ((u32)0x000A0000)  /* Running - closing descriptor */
+#define ETH_DMA_ReceiveProcess_Queuing      ((u32)0x000E0000)  /* Running - queuing the recieve frame into host memory */
+
+/* ETHERNET DMA overflow  --------------------------------------------------------*/
+#define ETH_DMA_Overflow_RxFIFOCounter      ((u32)0x10000000)  /* Overflow bit for FIFO overflow counter */
+#define ETH_DMA_Overflow_MissedFrameCounter ((u32)0x00010000)  /* Overflow bit for missed frame counter */
+
+#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \
+                                           ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter))
+
+/*----------------------------------------------------------------------------*/
+/*                          Ethernet PMT defines                              */
+/*----------------------------------------------------------------------------*/
+/* ETHERNET PMT Flags --------------------------------------------------------*/
+#define ETH_PMT_FLAG_WUFFRPR      ((u32)0x80000000)  /* Wake-Up Frame Filter Register Poniter Reset */
+#define ETH_PMT_FLAG_WUFR         ((u32)0x00000040)  /* Wake-Up Frame Received */
+#define ETH_PMT_FLAG_MPR          ((u32)0x00000020)  /* Magic Packet Received */
+
+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
+                                   ((FLAG) == ETH_PMT_FLAG_MPR))
+
+/*----------------------------------------------------------------------------*/
+/*                          Ethernet MMC defines                              */
+/*----------------------------------------------------------------------------*/
+/* ETHERNET MMC Tx Interrupts */
+#define ETH_MMC_IT_TGF       ((u32)0x00200000)  /* When Tx good frame counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFMSC    ((u32)0x00008000)  /* When Tx good multi col counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFSC     ((u32)0x00004000)  /* When Tx good single col counter reaches half the maximum value */
+
+/* ETHERNET MMC Rx Interrupts */
+#define ETH_MMC_IT_RGUF      ((u32)0x10020000)  /* When Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMC_IT_RFAE      ((u32)0x10000040)  /* When Rx alignment error counter reaches half the maximum value */
+#define ETH_MMC_IT_RFCE      ((u32)0x10000020)  /* When Rx crc error counter reaches half the maximum value */
+
+#define IS_ETH_MMC_IT(IT) (((((IT) & (u32)0xFFDF3FFF) == 0x00) || (((IT) & (u32)0xEFFDFF9F) == 0x00)) && \
+                           ((IT) != 0x00))
+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
+                               ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
+                               ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
+
+/* ETHERNET MMC Registers */
+#define ETH_MMCCR            ((u32)0x00000100)  /* MMC CR register */
+#define ETH_MMCRIR           ((u32)0x00000104)  /* MMC RIR register */
+#define ETH_MMCTIR           ((u32)0x00000108)  /* MMC TIR register */
+#define ETH_MMCRIMR          ((u32)0x0000010C)  /* MMC RIMR register */
+#define ETH_MMCTIMR          ((u32)0x00000110)  /* MMC TIMR register */
+#define ETH_MMCTGFSCCR       ((u32)0x0000014C)  /* MMC TGFSCCR register */
+#define ETH_MMCTGFMSCCR      ((u32)0x00000150)  /* MMC TGFMSCCR register */
+#define ETH_MMCTGFCR         ((u32)0x00000168)  /* MMC TGFCR register */
+#define ETH_MMCRFCECR        ((u32)0x00000194)  /* MMC RFCECR register */
+#define ETH_MMCRFAECR        ((u32)0x00000198)  /* MMC RFAECR register */
+#define ETH_MMCRGUFCR        ((u32)0x000001C4)  /* MMC RGUFCR register */
+
+/* ETHERNET MMC registers */
+#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR)  || ((REG) == ETH_MMCRIR) || \
+                                  ((REG) == ETH_MMCTIR)  || ((REG) == ETH_MMCRIMR) || \
+                                  ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \
+                                  ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \
+                                  ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \
+                                  ((REG) == ETH_MMCRGUFCR))
+
+/*----------------------------------------------------------------------------*/
+/*                          Ethernet PTP defines                              */
+/*----------------------------------------------------------------------------*/
+/* ETHERNET PTP time update method -------------------------------------------*/
+#define ETH_PTP_FineUpdate        ((u32)0x00000001)  /* Fine Update method */
+#define ETH_PTP_CoarseUpdate      ((u32)0x00000000)  /* Coarse Update method */
+
+#define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \
+                                   ((UPDATE) == ETH_PTP_CoarseUpdate))
+
+/* ETHERNET PTP Flags --------------------------------------------------------*/
+#define ETH_PTP_FLAG_TSARU        ((u32)0x00000020)  /* Addend Register Update */
+#define ETH_PTP_FLAG_TSITE        ((u32)0x00000010)  /* Time Stamp Interrupt Trigger */
+#define ETH_PTP_FLAG_TSSTU        ((u32)0x00000008)  /* Time Stamp Update */
+#define ETH_PTP_FLAG_TSSTI        ((u32)0x00000004)  /* Time Stamp Initialize */
+
+#define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \
+                                   ((FLAG) == ETH_PTP_FLAG_TSITE) || \
+				                   ((FLAG) == ETH_PTP_FLAG_TSSTU) || \
+                                   ((FLAG) == ETH_PTP_FLAG_TSSTI))
+
+/* ETHERNET PTP subsecond increment */
+#define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF)
+
+/* ETHERNET PTP time sign ----------------------------------------------------*/
+#define ETH_PTP_PositiveTime      ((u32)0x00000000)  /* Positive time value */
+#define ETH_PTP_NegativeTime      ((u32)0x80000000)  /* Negative time value */
+
+#define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \
+                                    ((SIGN) == ETH_PTP_NegativeTime))
+
+/* ETHERNET PTP time stamp low update */
+#define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF)
+
+/* ETHERNET PTP registers */
+#define ETH_PTPTSCR     ((u32)0x00000700)  /* PTP TSCR register */
+#define ETH_PTPSSIR     ((u32)0x00000704)  /* PTP SSIR register */
+#define ETH_PTPTSHR     ((u32)0x00000708)  /* PTP TSHR register */
+#define ETH_PTPTSLR     ((u32)0x0000070C)  /* PTP TSLR register */
+#define ETH_PTPTSHUR    ((u32)0x00000710)  /* PTP TSHUR register */
+#define ETH_PTPTSLUR    ((u32)0x00000714)  /* PTP TSLUR register */
+#define ETH_PTPTSAR     ((u32)0x00000718)  /* PTP TSAR register */
+#define ETH_PTPTTHR     ((u32)0x0000071C)  /* PTP TTHR register */
+#define ETH_PTPTTLR     ((u32)0x00000720)  /* PTP TTLR register */
+
+#define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \
+                                  ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \
+								  ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \
+								  ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \
+								  ((REG) == ETH_PTPTTLR))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void ETH_DeInit(void);
+u32 ETH_Init(ETH_InitTypeDef* ETH_InitStruct, u16 PHYAddress);
+void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct);
+void ETH_SoftwareReset(void);
+FlagStatus ETH_GetSoftwareResetStatus(void);
+void  ETH_Start(void);
+u32 ETH_HandleTxPkt(u32 addr, u16 FrameLength);
+u32 ETH_HandleRxPkt(u32 addr);
+
+
+u32 ETH_GetRxPktSize(void);
+void ETH_DropRxPkt(void);
+
+/*---------------------------------  PHY  ------------------------------------*/
+u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg);
+u32 ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue);
+u32 ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState);
+/*---------------------------------  MAC  ------------------------------------*/
+void ETH_MACTransmissionCmd(FunctionalState NewState);
+void ETH_MACReceptionCmd(FunctionalState NewState);
+FlagStatus ETH_GetFlowControlBusyStatus(void);
+void ETH_InitiatePauseControlFrame(void);
+void ETH_BackPressureActivationCmd(FunctionalState NewState);
+FlagStatus ETH_GetMACFlagStatus(u32 ETH_MAC_FLAG);
+ITStatus ETH_GetMACITStatus(u32 ETH_MAC_IT);
+void ETH_MACITConfig(u32 ETH_MAC_IT, FunctionalState NewState);
+void ETH_MACAddressConfig(u32 MacAddr, u8 *Addr);
+void ETH_GetMACAddress(u32 MacAddr, u8 *Addr);
+void ETH_MACAddressPerfectFilterCmd(u32 MacAddr, FunctionalState NewState);
+void ETH_MACAddressFilterConfig(u32 MacAddr, u32 Filter);
+void ETH_MACAddressMaskBytesFilterConfig(u32 MacAddr, u32 MaskByte);
+/*-----------------------  DMA Tx/Rx descriptors  ----------------------------*/
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff, u32 TxBuffCount);
+void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, u32 TxBuffCount);
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, u32 ETH_DMATxDescFlag);
+u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc);
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc);
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_FrameSegment);
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_Checksum);
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 BufferSize1, u32 BufferSize2);
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff, u32 RxBuffCount);
+void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff1, u8 *RxBuff2, u32 RxBuffCount);
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, u32 ETH_DMARxDescFlag);
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc);
+u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc);
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
+void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
+void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
+u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, u32 DMARxDesc_Buffer);
+/*---------------------------------  DMA  ------------------------------------*/
+FlagStatus ETH_GetDMAFlagStatus(u32 ETH_DMA_FLAG);
+void ETH_DMAClearFlag(u32 ETH_DMA_FLAG);
+ITStatus ETH_GetDMAITStatus(u32 ETH_DMA_IT);
+void ETH_DMAClearITPendingBit(u32 ETH_DMA_IT);
+u32 ETH_GetTransmitProcessState(void);
+u32 ETH_GetReceiveProcessState(void);
+void ETH_FlushTransmitFIFO(void);
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void);
+void ETH_DMATransmissionCmd(FunctionalState NewState);
+void ETH_DMAReceptionCmd(FunctionalState NewState);
+void ETH_DMAITConfig(u32 ETH_DMA_IT, FunctionalState NewState);
+FlagStatus ETH_GetDMAOverflowStatus(u32 ETH_DMA_Overflow);
+u32 ETH_GetRxOverflowMissedFrameCounter(void);
+u32 ETH_GetBufferUnavailableMissedFrameCounter(void);
+u32 ETH_GetCurrentTxDescStartAddress(void);
+u32 ETH_GetCurrentRxDescStartAddress(void);
+u32 ETH_GetCurrentTxBufferAddress(void);
+u32 ETH_GetCurrentRxBufferAddress(void);
+void ETH_ResumeDMATransmission(void);
+void ETH_ResumeDMAReception(void);
+/*---------------------------------  PMT  ------------------------------------*/
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void);
+void ETH_SetWakeUpFrameFilterRegister(u32 *Buffer);
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState);
+FlagStatus ETH_GetPMTFlagStatus(u32 ETH_PMT_FLAG);
+void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState);
+void ETH_MagicPacketDetectionCmd(FunctionalState NewState);
+void ETH_PowerDownCmd(FunctionalState NewState);
+/*---------------------------------  MMC  ------------------------------------*/
+void ETH_MMCCounterFreezeCmd(FunctionalState NewState);
+void ETH_MMCResetOnReadCmd(FunctionalState NewState);
+void ETH_MMCCounterRolloverCmd(FunctionalState NewState);
+void ETH_MMCCountersReset(void);
+void ETH_MMCITConfig(u32 ETH_MMC_IT, FunctionalState NewState);
+ITStatus ETH_GetMMCITStatus(u32 ETH_MMC_IT);
+u32 ETH_GetMMCRegister(u32 ETH_MMCReg);
+/*---------------------------------  PTP  ------------------------------------*/
+u32 ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, u32 *PTPTxTab);
+u32 ETH_HandlePTPRxPkt(u8 *ppkt, u32 *PTPRxTab);
+void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, u32 TxBuffCount);
+void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, u8 *RxBuff, u32 RxBuffCount);
+void ETH_EnablePTPTimeStampAddend(void);
+void ETH_EnablePTPTimeStampInterruptTrigger(void);
+void ETH_EnablePTPTimeStampUpdate(void);
+void ETH_InitializePTPTimeStamp(void);
+void ETH_PTPUpdateMethodConfig(u32 UpdateMethod);
+void ETH_PTPTimeStampCmd(FunctionalState NewState);
+FlagStatus ETH_GetPTPFlagStatus(u32 ETH_PTP_FLAG);
+void ETH_SetPTPSubSecondIncrement(u32 SubSecondValue);
+void ETH_SetPTPTimeStampUpdate(u32 Sign, u32 SecondValue, u32 SubSecondValue);
+void ETH_SetPTPTimeStampAddend(u32 Value);
+void ETH_SetPTPTargetTime(u32 HighValue, u32 LowValue);
+u32 ETH_GetPTPRegister(u32 ETH_PTPReg);
+
+#endif /* __STM32FXXX_ETH_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_conf.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_conf.h
new file mode 100644
index 0000000..93f7fb3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_conf.h
@@ -0,0 +1,58 @@
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name          : stm32f_eth_conf.h
+* Author             : MCD Application Team
+* Version            : VX.Y.Z
+* Date               : mm/dd/2008
+* Description        : ETHERNET firmware library configuration file.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F_ETH_CONF_H
+#define __STM32F_ETH_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_type.h"
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to compile the ETHERNET firmware library in DEBUG mode,
+   this will expanse the "assert_param" macro in the firmware library code (see 
+   "Exported macro" section below) */
+/*#define ETH_DEBUG    1*/
+
+/* Comment the line below to disable the specific peripheral inclusion */
+/************************************* ETHERNET *******************************/
+#define _ETH_MAC
+//#define _ETH_PTP
+//#define _ETH_MMC
+#define _ETH_DMA
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  ETH_DEBUG
+/*******************************************************************************
+* Macro Name     : eth_assert_param
+* Description    : The eth_assert_param macro is used for ethernet function's parameters
+*                  check.
+*                  It is used only if the ethernet library is compiled in DEBUG mode. 
+* Input          : - expr: If expr is false, it calls assert_failed function
+*                    which reports the name of the source file and the source
+*                    line number of the call that failed. 
+*                    If expr is true, it returns no value.
+* Return         : None
+*******************************************************************************/ 
+  #define eth_assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(u8* file, u32 line);
+#else
+  #define eth_assert_param(expr) ((void)0)
+#endif /* ETH_DEBUG */
+
+#endif /* __STM32F_ETH_CONF_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_lib.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_lib.h
new file mode 100644
index 0000000..a501d70
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_lib.h
@@ -0,0 +1,39 @@
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name          : stm32fxxx_eth_lib.h
+* Author             : MCD Application Team
+* Version            : V2.0.2
+* Date               : 07/11/2008
+* Description        : This file includes the peripherals header files in the
+*                      user application.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32FXXX_ETH_LIB_H
+#define __STM32FXXX_ETH_LIB_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32fxxx_eth_map.h"
+
+#ifdef _ETH_MAC
+//RP_Modif
+  #include "ipport.h"
+  #include "netbuf.h"
+  #include "stm32fxxx_eth.h"
+#endif /*_ETH_MAC */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void eth_debug(void);
+
+#endif /* __STM32FXXX_ETH_LIB_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_map.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_map.h
new file mode 100644
index 0000000..cae9ce0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_map.h
@@ -0,0 +1,593 @@
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name          : stm32fxxx_eth_map.h
+* Author             : MCD Application Team
+* Version            : VX.Y.Z
+* Date               : mm/dd/2008
+* Description        : This file contains all ETHERNET peripheral register's
+*                      definitions and memory mapping.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32FXXX_ETH_MAP_H
+#define __STM32FXXX_ETH_MAP_H
+
+#ifndef EXT
+  #define EXT extern
+#endif /* EXT */
+
+/* Includes ------------------------------------------------------------------*/
+
+#include "stm32fxxx_eth_conf.h"
+#include "stm32f10x_type.h"
+
+/* Exported types ------------------------------------------------------------*/
+/******************************************************************************/
+/*                Ethernet Peripheral registers structures                    */
+/******************************************************************************/
+
+typedef struct
+{
+  vu32 MACCR;
+  vu32 MACFFR;
+  vu32 MACHTHR;
+  vu32 MACHTLR;
+  vu32 MACMIIAR;
+  vu32 MACMIIDR;
+  vu32 MACFCR;
+  vu32 MACVLANTR;
+  vu32 RESERVED0[2];
+  vu32 MACRWUFFR;
+  vu32 MACPMTCSR;
+  vu32 RESERVED1[2];
+  vu32 MACSR;
+  vu32 MACIMR;
+  vu32 MACA0HR;
+  vu32 MACA0LR;
+  vu32 MACA1HR;
+  vu32 MACA1LR;
+  vu32 MACA2HR;
+  vu32 MACA2LR;
+  vu32 MACA3HR;
+  vu32 MACA3LR;
+} ETH_MAC_TypeDef;
+
+typedef struct
+{
+  vu32 MMCCR;
+  vu32 MMCRIR;
+  vu32 MMCTIR;
+  vu32 MMCRIMR;
+  vu32 MMCTIMR;
+  vu32 RESERVED0[14];
+  vu32 MMCTGFSCCR;
+  vu32 MMCTGFMSCCR;
+  vu32 RESERVED1[5];
+  vu32 MMCTGFCR;
+  vu32 RESERVED2[10];
+  vu32 MMCRFCECR;
+  vu32 MMCRFAER;
+  vu32 RESERVED3[10];
+  vu32 MMCRGUFCR;
+} ETH_MMC_TypeDef;
+
+typedef struct
+{
+  vu32 PTPTSCR;
+  vu32 PTPSSIR;
+  vu32 PTPTSHR;
+  vu32 PTPTSLR;
+  vu32 PTPTSHUR;
+  vu32 PTPTSLUR;
+  vu32 PTPTSAR;
+  vu32 PTPTTHR;
+  vu32 PTPTTLR;
+} ETH_PTP_TypeDef;
+
+typedef struct
+{
+  vu32 DMABMR;
+  vu32 DMATPDR;
+  vu32 DMARPDR;
+  vu32 DMARDLAR;
+  vu32 DMATDLAR;
+  vu32 DMASR;
+  vu32 DMAOMR;
+  vu32 DMAIER;
+  vu32 DMAMFBOCR;
+  vu32 RESERVED0[9];
+  vu32 DMACHTDR;
+  vu32 DMACHRDR;
+  vu32 DMACHTBAR;
+  vu32 DMACHRBAR;
+} ETH_DMA_TypeDef;
+
+/******************************************************************************/
+/*                Ethernet MAC Registers bits definitions                     */
+/******************************************************************************/
+//#define  IPNAME_REGNAME_BITNAME   /* BIT MASK */
+
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD      ((u32)0x00800000)  /* Watchdog disable */
+#define ETH_MACCR_JD      ((u32)0x00400000)  /* Jabber disable */
+#define ETH_MACCR_JFE     ((u32)0x00100000)  /* Jumbo frame enable */
+#define ETH_MACCR_IFG     ((u32)0x000E0000)  /* Inter-frame gap */
+  #define ETH_MACCR_IFG_96Bit     ((u32)0x00000000)  /* Minimum IFG between frames during transmission is 96Bit */
+  #define ETH_MACCR_IFG_88Bit     ((u32)0x00020000)  /* Minimum IFG between frames during transmission is 88Bit */
+  #define ETH_MACCR_IFG_80Bit     ((u32)0x00040000)  /* Minimum IFG between frames during transmission is 80Bit */
+  #define ETH_MACCR_IFG_72Bit     ((u32)0x00060000)  /* Minimum IFG between frames during transmission is 72Bit */
+  #define ETH_MACCR_IFG_64Bit     ((u32)0x00080000)  /* Minimum IFG between frames during transmission is 64Bit */
+  #define ETH_MACCR_IFG_56Bit     ((u32)0x000A0000)  /* Minimum IFG between frames during transmission is 56Bit */
+  #define ETH_MACCR_IFG_48Bit     ((u32)0x000C0000)  /* Minimum IFG between frames during transmission is 48Bit */
+  #define ETH_MACCR_IFG_40Bit     ((u32)0x000E0000)  /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD     ((u32)0x00010000)  /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES     ((u32)0x00004000)  /* Fast ethernet speed */
+#define ETH_MACCR_ROD     ((u32)0x00002000)  /* Receive own disable */
+#define ETH_MACCR_LM      ((u32)0x00001000)  /* loopback mode */
+#define ETH_MACCR_DM      ((u32)0x00000800)  /* Duplex mode */
+#define ETH_MACCR_IPCO    ((u32)0x00000400)  /* IP Checksum offload */
+#define ETH_MACCR_RD      ((u32)0x00000200)  /* Retry disable */
+#define ETH_MACCR_APCS    ((u32)0x00000080)  /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL      ((u32)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
+  #define ETH_MACCR_BL_10    ((u32)0x00000000)  /* k = min (n, 10) */
+  #define ETH_MACCR_BL_8     ((u32)0x00000020)  /* k = min (n, 8) */
+  #define ETH_MACCR_BL_4     ((u32)0x00000040)  /* k = min (n, 4) */
+  #define ETH_MACCR_BL_1     ((u32)0x00000060)  /* k = min (n, 1) */
+#define ETH_MACCR_DC      ((u32)0x00000010)  /* Defferal check */
+#define ETH_MACCR_TE      ((u32)0x00000008)  /* Transmitter enable */
+#define ETH_MACCR_RE      ((u32)0x00000004)  /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA     ((u32)0x80000000)  /* Receive all */
+#define ETH_MACFFR_HPF    ((u32)0x00000400)  /* Hash or perfect filter */
+#define ETH_MACFFR_SAF    ((u32)0x00000200)  /* Source address filter enable */
+#define ETH_MACFFR_SAIF   ((u32)0x00000100)  /* SA inverse filtering */
+#define ETH_MACFFR_PCF    ((u32)0x000000C0)  /* Pass control frames: 3 cases */
+  #define ETH_MACFFR_PCF_BlockAll                ((u32)0x00000040)  /* MAC filters all control frames from reaching the application */
+  #define ETH_MACFFR_PCF_ForwardAll              ((u32)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
+  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((u32)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACFFR_BFD    ((u32)0x00000020)  /* Broadcast frame disable */
+#define ETH_MACFFR_PAM 	  ((u32)0x00000010)  /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF   ((u32)0x00000008)  /* DA Inverse filtering */
+#define ETH_MACFFR_HM     ((u32)0x00000004)  /* Hash multicast */
+#define ETH_MACFFR_HU     ((u32)0x00000002)  /* Hash unicast */
+#define ETH_MACFFR_PM     ((u32)0x00000001)  /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH   ((u32)0xFFFFFFFF)  /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL   ((u32)0xFFFFFFFF)  /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA   ((u32)0x0000F800)  /* Physical layer address */
+#define ETH_MACMIIAR_MR   ((u32)0x000007C0)  /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR   ((u32)0x0000001C)  /* CR clock range: 6 cases */
+  #define ETH_MACMIIAR_CR_Div42   ((u32)0x00000000)  /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
+  #define ETH_MACMIIAR_CR_Div16   ((u32)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+  #define ETH_MACMIIAR_CR_Div26   ((u32)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+#define ETH_MACMIIAR_MW   ((u32)0x00000002)  /* MII write */
+#define ETH_MACMIIAR_MB   ((u32)0x00000001)  /* MII busy */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD   ((u32)0x0000FFFF)  /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT     ((u32)0xFFFF0000)  /* Pause time */
+#define ETH_MACFCR_ZQPD   ((u32)0x00000080)  /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT    ((u32)0x00000030)  /* Pause low threshold: 4 cases */
+  #define ETH_MACFCR_PLT_Minus4   ((u32)0x00000000)  /* Pause time minus 4 slot times */
+  #define ETH_MACFCR_PLT_Minus28  ((u32)0x00000010)  /* Pause time minus 28 slot times */
+  #define ETH_MACFCR_PLT_Minus144 ((u32)0x00000020)  /* Pause time minus 144 slot times */
+  #define ETH_MACFCR_PLT_Minus256 ((u32)0x00000030)  /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD   ((u32)0x00000008)  /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE   ((u32)0x00000004)  /* Receive flow control enable */
+#define ETH_MACFCR_TFCE   ((u32)0x00000002)  /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA ((u32)0x00000001)  /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC ((u32)0x00010000)  /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI ((u32)0x0000FFFF)  /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+#define ETH_MACRWUFFR_D   ((u32)0xFFFFFFFF)  /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+                              RSVD - Filter1 Command - RSVD - Filter0 Command
+   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */
+#define ETH_MACPMTCSR_WFFRPR ((u32)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU     ((u32)0x00000200)  /* Global Unicast */
+#define ETH_MACPMTCSR_WFR    ((u32)0x00000040)  /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR    ((u32)0x00000020)  /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE    ((u32)0x00000004)  /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE    ((u32)0x00000002)  /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD     ((u32)0x00000001)  /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS      ((u32)0x00000200)  /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS     ((u32)0x00000040)  /* MMC transmit status */
+#define ETH_MACSR_MMMCRS    ((u32)0x00000020)  /* MMC receive status */
+#define ETH_MACSR_MMCS      ((u32)0x00000010)  /* MMC status */
+#define ETH_MACSR_PMTS      ((u32)0x00000008)  /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM     ((u32)0x00000200)  /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM     ((u32)0x00000008)  /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H   ((u32)0x0000FFFF)  /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L   ((u32)0xFFFFFFFF)  /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE       ((u32)0x80000000)  /* Address enable */
+#define ETH_MACA1HR_SA       ((u32)0x40000000)  /* Source address */
+#define ETH_MACA1HR_MBC      ((u32)0x3F000000)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+  #define ETH_MACA1HR_MBC_HBits15_8    ((u32)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_HBits7_0     ((u32)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA1HR_MBC_LBits31_24   ((u32)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA1HR_MBC_LBits23_16   ((u32)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA1HR_MBC_LBits15_8    ((u32)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_LBits7_0     ((u32)0x01000000)  /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACA1HR_MACA1H   ((u32)0x0000FFFF)  /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L   ((u32)0xFFFFFFFF)  /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE       ((u32)0x80000000)  /* Address enable */
+#define ETH_MACA2HR_SA       ((u32)0x40000000)  /* Source address */
+#define ETH_MACA2HR_MBC      ((u32)0x3F000000)  /* Mask byte control */
+  #define ETH_MACA2HR_MBC_HBits15_8    ((u32)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_HBits7_0     ((u32)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA2HR_MBC_LBits31_24   ((u32)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA2HR_MBC_LBits23_16   ((u32)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA2HR_MBC_LBits15_8    ((u32)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_LBits7_0     ((u32)0x01000000)  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H   ((u32)0x0000FFFF)  /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L   ((u32)0xFFFFFFFF)  /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE       ((u32)0x80000000)  /* Address enable */
+#define ETH_MACA3HR_SA       ((u32)0x40000000)  /* Source address */
+#define ETH_MACA3HR_MBC      ((u32)0x3F000000)  /* Mask byte control */
+  #define ETH_MACA2HR_MBC_HBits15_8    ((u32)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_HBits7_0     ((u32)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA2HR_MBC_LBits31_24   ((u32)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA2HR_MBC_LBits23_16   ((u32)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA2HR_MBC_LBits15_8    ((u32)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_LBits7_0     ((u32)0x01000000)  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H   ((u32)0x0000FFFF)  /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L   ((u32)0xFFFFFFFF)  /* MAC address3 low */
+
+/******************************************************************************/
+/*                Ethernet MMC Registers bits definition                      */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCF        ((u32)0x00000008)  /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR        ((u32)0x00000004)  /* Reset on Read */
+#define ETH_MMCCR_CSR        ((u32)0x00000002)  /* Counter Stop Rollover */
+#define ETH_MMCCR_CR         ((u32)0x00000001)  /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS     ((u32)0x00020000)  /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES     ((u32)0x00000040)  /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES     ((u32)0x00000020)  /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS      ((u32)0x00200000)  /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS   ((u32)0x00008000)  /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS    ((u32)0x00004000)  /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM    ((u32)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM    ((u32)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM    ((u32)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM     ((u32)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM  ((u32)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM   ((u32)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC     ((u32)0xFFFFFFFF)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC   ((u32)0xFFFFFFFF)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC    ((u32)0xFFFFFFFF)  /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC  ((u32)0xFFFFFFFF)  /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC  ((u32)0xFFFFFFFF)  /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC  ((u32)0xFFFFFFFF)  /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/*               Ethernet PTP Registers bits definition                       */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSARU    ((u32)0x00000020)  /* Addend register update */
+#define ETH_PTPTSCR_TSITE    ((u32)0x00000010)  /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU    ((u32)0x00000008)  /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI    ((u32)0x00000004)  /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU    ((u32)0x00000002)  /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE      ((u32)0x00000001)  /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI    ((u32)0x000000FF)  /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS      ((u32)0xFFFFFFFF)  /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS    ((u32)0x80000000)  /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS     ((u32)0x7FFFFFFF)  /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS    ((u32)0xFFFFFFFF)  /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS  ((u32)0x80000000)  /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS   ((u32)0x7FFFFFFF)  /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA      ((u32)0xFFFFFFFF)  /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH     ((u32)0xFFFFFFFF)  /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL     ((u32)0xFFFFFFFF)  /* Target time stamp low */
+
+/******************************************************************************/
+/*                 Ethernet DMA Registers bits definition                     */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB       ((u32)0x02000000)  /* Address-Aligned beats */
+#define ETH_DMABMR_FPM        ((u32)0x01000000)  /* 4xPBL mode */
+#define ETH_DMABMR_USP       ((u32)0x00800000)  /* Use separate PBL */
+#define ETH_DMABMR_RDP       ((u32)0x007E0000)  /* RxDMA PBL */
+  /* Values to be confirmed: maybe they are inversed */
+  #define ETH_DMABMR_RDP_1Beat    ((u32)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+  #define ETH_DMABMR_RDP_2Beat    ((u32)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+  #define ETH_DMABMR_RDP_4Beat    ((u32)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_8Beat    ((u32)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_16Beat   ((u32)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_32Beat   ((u32)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+  #define ETH_DMABMR_RDP_4xPBL_4Beat   ((u32)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_4xPBL_8Beat   ((u32)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_4xPBL_16Beat  ((u32)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_4xPBL_32Beat  ((u32)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+  #define ETH_DMABMR_RDP_4xPBL_64Beat  ((u32)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+  #define ETH_DMABMR_RDP_4xPBL_128Beat ((u32)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_DMABMR_FB        ((u32)0x00010000)  /* Fixed Burst */
+#define ETH_DMABMR_RTPR      ((u32)0x0000C000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_1_1     ((u32)0x00000000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_2_1     ((u32)0x00004000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_3_1     ((u32)0x00008000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_4_1     ((u32)0x0000C000)  /* Rx Tx priority ratio */
+#define ETH_DMABMR_PBL    ((u32)0x00003F00)  /* Programmable burst length */
+  /* Values to be confirmed: maybe they are inversed */
+  #define ETH_DMABMR_PBL_1Beat    ((u32)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+  #define ETH_DMABMR_PBL_2Beat    ((u32)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+  #define ETH_DMABMR_PBL_4Beat    ((u32)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_8Beat    ((u32)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_16Beat   ((u32)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_32Beat   ((u32)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+  #define ETH_DMABMR_PBL_4xPBL_4Beat   ((u32)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_4xPBL_8Beat   ((u32)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_4xPBL_16Beat  ((u32)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_4xPBL_32Beat  ((u32)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+  #define ETH_DMABMR_PBL_4xPBL_64Beat  ((u32)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+  #define ETH_DMABMR_PBL_4xPBL_128Beat ((u32)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_DSL       ((u32)0x0000007C)  /* Descriptor Skip Length */
+#define ETH_DMABMR_DA        ((u32)0x00000002)  /* DMA arbitration scheme */
+#define ETH_DMABMR_SR        ((u32)0x00000001)  /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD      ((u32)0xFFFFFFFF)  /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD      ((u32)0xFFFFFFFF)  /* Receive poll demand  */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL     ((u32)0xFFFFFFFF)  /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL     ((u32)0xFFFFFFFF)  /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS       ((u32)0x20000000)  /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS       ((u32)0x10000000)  /* PMT status */
+#define ETH_DMASR_MMCS       ((u32)0x08000000)  /* MMC status */
+#define ETH_DMASR_EBS        ((u32)0x03800000)  /* Error bits status */
+  /* combination with EBS[2:0] for GetFlagStatus function */
+  #define ETH_DMASR_EBS_DescAccess      ((u32)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
+  #define ETH_DMASR_EBS_ReadTransf      ((u32)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */
+  #define ETH_DMASR_EBS_DataTransfTx    ((u32)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS         ((u32)0x00700000)  /* Transmit process state */
+  #define ETH_DMASR_TPS_Stopped         ((u32)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */
+  #define ETH_DMASR_TPS_Fetching        ((u32)0x00100000)  /* Running - fetching the Tx descriptor */
+  #define ETH_DMASR_TPS_Waiting         ((u32)0x00200000)  /* Running - waiting for status */
+  #define ETH_DMASR_TPS_Reading         ((u32)0x00300000)  /* Running - reading the data from host memory */
+  #define ETH_DMASR_TPS_Suspended       ((u32)0x00600000)  /* Suspended - Tx Descriptor unavailabe */
+  #define ETH_DMASR_TPS_Closing         ((u32)0x00700000)  /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS         ((u32)0x000E0000)  /* Receive process state */
+  #define ETH_DMASR_RPS_Stopped         ((u32)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
+  #define ETH_DMASR_RPS_Fetching        ((u32)0x00020000)  /* Running - fetching the Rx descriptor */
+  #define ETH_DMASR_RPS_Waiting         ((u32)0x00060000)  /* Running - waiting for packet */
+  #define ETH_DMASR_RPS_Suspended       ((u32)0x00080000)  /* Suspended - Rx Descriptor unavailable */
+  #define ETH_DMASR_RPS_Closing         ((u32)0x000A0000)  /* Running - closing descriptor */
+  #define ETH_DMASR_RPS_Queuing         ((u32)0x000E0000)  /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS        ((u32)0x00010000)  /* Normal interrupt summary */
+#define ETH_DMASR_AIS        ((u32)0x00008000)  /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS        ((u32)0x00004000)  /* Early receive status */
+#define ETH_DMASR_FBES       ((u32)0x00002000)  /* Fatal bus error status */
+#define ETH_DMASR_ETS        ((u32)0x00000400)  /* Early transmit status */
+#define ETH_DMASR_RWTS       ((u32)0x00000200)  /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS       ((u32)0x00000100)  /* Receive process stopped status */
+#define ETH_DMASR_RBUS       ((u32)0x00000080)  /* Receive buffer unavailable status */
+#define ETH_DMASR_RS         ((u32)0x00000040)  /* Receive status */
+#define ETH_DMASR_TUS        ((u32)0x00000020)  /* Transmit underflow status */
+#define ETH_DMASR_ROS        ((u32)0x00000010)  /* Receive overflow status */
+#define ETH_DMASR_TJTS       ((u32)0x00000008)  /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS       ((u32)0x00000004)  /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS       ((u32)0x00000002)  /* Transmit process stopped status */
+#define ETH_DMASR_TS         ((u32)0x00000001)  /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD    ((u32)0x04000000)  /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF       ((u32)0x02000000)  /* Receive store and forward */
+#define ETH_DMAOMR_DFRF      ((u32)0x01000000)  /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF       ((u32)0x00200000)  /* Transmit store and forward */
+#define ETH_DMAOMR_FTF       ((u32)0x00100000)  /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC       ((u32)0x0001C000)  /* Transmit threshold control */
+  #define ETH_DMAOMR_TTC_64Bytes       ((u32)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+  #define ETH_DMAOMR_TTC_128Bytes      ((u32)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+  #define ETH_DMAOMR_TTC_192Bytes      ((u32)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+  #define ETH_DMAOMR_TTC_256Bytes      ((u32)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+  #define ETH_DMAOMR_TTC_40Bytes       ((u32)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+  #define ETH_DMAOMR_TTC_32Bytes       ((u32)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+  #define ETH_DMAOMR_TTC_24Bytes       ((u32)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+  #define ETH_DMAOMR_TTC_16Bytes       ((u32)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST        ((u32)0x00002000)  /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF       ((u32)0x00000080)  /* Forward error frames */
+#define ETH_DMAOMR_FUGF      ((u32)0x00000040)  /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC       ((u32)0x00000018)  /* receive threshold control */
+  #define ETH_DMAOMR_RTC_64Bytes       ((u32)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
+  #define ETH_DMAOMR_RTC_32Bytes       ((u32)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
+  #define ETH_DMAOMR_RTC_96Bytes       ((u32)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
+  #define ETH_DMAOMR_RTC_128Bytes      ((u32)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF       ((u32)0x00000004)  /* operate on second frame */
+#define ETH_DMAOMR_SR        ((u32)0x00000002)  /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE      ((u32)0x00010000)  /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE      ((u32)0x00008000)  /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE      ((u32)0x00004000)  /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE     ((u32)0x00002000)  /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE      ((u32)0x00000400)  /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE     ((u32)0x00000200)  /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE     ((u32)0x00000100)  /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE     ((u32)0x00000080)  /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE       ((u32)0x00000040)  /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE      ((u32)0x00000020)  /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE      ((u32)0x00000010)  /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE     ((u32)0x00000008)  /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE     ((u32)0x00000004)  /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE     ((u32)0x00000002)  /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE       ((u32)0x00000001)  /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC   ((u32)0x10000000)  /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA    ((u32)0x0FFE0000)  /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC   ((u32)0x00010000)  /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC    ((u32)0x0000FFFF)  /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP   ((u32)0xFFFFFFFF)  /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP   ((u32)0xFFFFFFFF)  /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP  ((u32)0xFFFFFFFF)  /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP  ((u32)0xFFFFFFFF)  /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/*                                      Macros                                */
+/******************************************************************************/
+#define  SET_BIT(REG, BIT)   ((REG) |= (BIT))
+#define  CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+#define  READ_BIT(REG, BIT)  ((REG) & (BIT))
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+/* ETHERNET registers base address */
+#define ETH_BASE             ((u32)0x40028000)
+#define ETH_MAC_BASE         (ETH_BASE)
+#define ETH_MMC_BASE         (ETH_BASE + 0x0100)
+#define ETH_PTP_BASE         (ETH_BASE + 0x0700)
+#define ETH_DMA_BASE         (ETH_BASE + 0x1000)
+
+/******************************************************************************/
+/*                         Peripheral declaration                             */
+/******************************************************************************/
+
+/*------------------------ Non Debug Mode ------------------------------------*/
+#ifndef ETH_DEBUG
+#ifdef _ETH_MAC
+  #define ETH_MAC            ((ETH_MAC_TypeDef *) ETH_MAC_BASE)
+#endif /*_ETH_MAC */
+
+#ifdef _ETH_MMC
+  #define ETH_MMC            ((ETH_MMC_TypeDef *) ETH_MMC_BASE)
+#endif /*_ETH_MMC */
+
+#ifdef _ETH_PTP
+  #define ETH_PTP            ((ETH_PTP_TypeDef *) ETH_PTP_BASE)
+#endif /*_ETH_PTP */
+
+#ifdef _ETH_DMA
+  #define ETH_DMA            ((ETH_DMA_TypeDef *) ETH_DMA_BASE)
+#endif /*_ETH_DMA */
+
+/*------------------------ Debug Mode ----------------------------------------*/
+#else   /* ETH_DEBUG */
+#ifdef _ETH_MAC
+  EXT ETH_MAC_TypeDef        *ETH_MAC;
+#endif /*_ETH_MAC */
+
+#ifdef _ETH_MMC
+  EXT ETH_MMC_TypeDef        *ETH_MMC;
+#endif /*_ETH_MMC */
+
+#ifdef _ETH_PTP
+  EXT ETH_PTP_TypeDef        *ETH_PTP;
+#endif /*_ETH_PTP */
+
+#ifdef _ETH_DMA
+  EXT ETH_DMA_TypeDef        *ETH_DMA;
+#endif /*_ETH_DMA */
+
+#endif  /* ETH_DEBUG */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __STM32FXXX_ETH_MAP_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/cortexm3_macro_iar.s b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/cortexm3_macro_iar.s
new file mode 100644
index 0000000..cb20961
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/cortexm3_macro_iar.s
@@ -0,0 +1,278 @@
+;******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+;* File Name          : cortexm3_macro.s
+;* Author             : MCD Application Team
+;* Date First Issued  : 02/19/2007
+;* Description        : Instruction wrappers for special Cortex-M3 instructions.
+;*******************************************************************************
+; History:
+; 04/02/2007: V0.2
+; 02/19/2007: V0.1
+;*******************************************************************************
+; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+    
+  SECTION .text:CODE(2)
+
+  ; Exported functions
+  EXPORT __WFI
+  EXPORT __WFE
+  EXPORT __SEV
+  EXPORT __ISB
+  EXPORT __DSB
+  EXPORT __DMB
+  EXPORT __SVC
+  EXPORT __MRS_CONTROL
+  EXPORT __MSR_CONTROL
+  EXPORT __MRS_PSP
+  EXPORT __MSR_PSP
+  EXPORT __MRS_MSP
+  EXPORT __MSR_MSP
+  EXPORT __SETPRIMASK
+  EXPORT __RESETPRIMASK
+  EXPORT __SETFAULTMASK
+  EXPORT __RESETFAULTMASK
+  EXPORT __BASEPRICONFIG
+  EXPORT __GetBASEPRI
+  EXPORT __REV_HalfWord
+  EXPORT __REV_Word  
+
+;*******************************************************************************
+; Function Name  : __WFI
+; Description    : Assembler function for the WFI instruction.
+; Input          : None
+; Return         : None
+;*******************************************************************************
+__WFI 
+ 
+    WFI
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __WFE
+; Description    : Assembler function for the WFE instruction.
+; Input          : None
+; Return         : None
+;*******************************************************************************
+__WFE
+
+    WFE
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __SEV
+; Description    : Assembler function for the SEV instruction.
+; Input          : None
+; Return         : None
+;*******************************************************************************
+__SEV
+
+    SEV
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __ISB
+; Description    : Assembler function for the ISB instruction.
+; Input          : None
+; Return         : None
+;*******************************************************************************
+__ISB
+
+    ISB
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __DSB
+; Description    : Assembler function for the DSB instruction.
+; Input          : None
+; Return         : None
+;*******************************************************************************
+__DSB
+
+    DSB
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __DMB
+; Description    : Assembler function for the DMB instruction.
+; Input          : None
+; Return         : None
+;*******************************************************************************
+__DMB
+
+    DMB
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __SVC
+; Description    : Assembler function for the SVC instruction.
+; Input          : None
+; Return         : None
+;*******************************************************************************
+__SVC
+
+    SVC 0x01
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __MRS_CONTROL
+; Description    : Assembler function for the MRS instruction.
+; Input          : None
+; Return         : - r0 : Cortex-M3 CONTROL register value.
+;*******************************************************************************
+__MRS_CONTROL
+
+  MRS r0, CONTROL
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __MSR_CONTROL
+; Description    : Assembler function for the MSR instruction.
+; Input          : - r0 : Cortex-M3 CONTROL register new value.  
+; Return         : None
+;*******************************************************************************
+__MSR_CONTROL
+
+  MSR CONTROL, r0
+  ISB
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __MRS_PSP
+; Description    : Assembler function for the MRS instruction.
+; Input          : None
+; Return         : - r0 : Process Stack value.
+;*******************************************************************************
+__MRS_PSP
+
+  MRS r0, PSP
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __MSR_PSP
+; Description    : Assembler function for the MSR instruction.
+; Input          : - r0 : Process Stack new value.
+; Return         : None
+;*******************************************************************************
+__MSR_PSP
+
+    MSR PSP, r0 ; set Process Stack value
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __MRS_MSP
+; Description    : Assembler function for the MRS instruction.
+; Input          : None
+; Return         : - r0 : Main Stack value.
+;*******************************************************************************
+__MRS_MSP
+
+  MRS r0, MSP
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __MSR_MSP
+; Description    : Assembler function for the MSR instruction.
+; Input          : - r0 : Main Stack new value.
+; Return         : None
+;*******************************************************************************
+__MSR_MSP
+
+    MSR MSP, r0 ; set Main Stack value
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __SETPRIMASK
+; Description    : Assembler function to set the PRIMASK.
+; Input          : None 
+; Return         : None
+;*******************************************************************************
+__SETPRIMASK
+
+  CPSID i
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __RESETPRIMASK
+; Description    : Assembler function to reset the PRIMASK.
+; Input          : None 
+; Return         : None
+;*******************************************************************************
+__RESETPRIMASK
+
+  CPSIE i
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __SETFAULTMASK
+; Description    : Assembler function to set the FAULTMASK.
+; Input          : None 
+; Return         : None
+;*******************************************************************************
+__SETFAULTMASK
+
+  CPSID f
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __RESETFAULTMASK
+; Description    : Assembler function to reset the FAULTMASK.
+; Input          : None 
+; Return         : None
+;*******************************************************************************
+__RESETFAULTMASK
+
+  CPSIE f
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __BASEPRICONFIG
+; Description    : Assembler function to set the Base Priority.
+; Input          : - r0 : Base Priority new value  
+; Return         : None
+;*******************************************************************************
+__BASEPRICONFIG
+
+  MSR BASEPRI, r0
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __GetBASEPRI
+; Description    : Assembler function to get the Base Priority value.
+; Input          : None 
+; Return         : - r0 : Base Priority value 
+;*******************************************************************************
+__GetBASEPRI
+
+  MRS r0, BASEPRI_MAX
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __REV_HalfWord
+; Description    : Reverses the byte order in HalfWord(16-bit) input variable.
+; Input          : - r0 : specifies the input variable
+; Return         : - r0 : holds tve variable value after byte reversing.
+;*******************************************************************************
+__REV_HalfWord 
+ 
+  REV16 r0, r0
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __REV_Word
+; Description    : Reverses the byte order in Word(32-bit) input variable.
+; Input          : - r0 : specifies the input variable
+; Return         : - r0 : holds tve variable value after byte reversing.
+;*******************************************************************************
+__REV_Word 
+ 
+  REV r0, r0
+  BX r14
+  
+  END
+  
+;******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE*****
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/cortexm3_macro_rvds.s b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/cortexm3_macro_rvds.s
new file mode 100644
index 0000000..4032f21
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/cortexm3_macro_rvds.s
@@ -0,0 +1,284 @@
+;******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+;* File Name          : cortexm3_macro.s
+;* Author             : MCD Application Team
+;* Date First Issued  : 09/29/2006
+;* Description        : Instruction wrappers for special Cortex-M3 instructions.
+;*******************************************************************************
+; History:
+; 05/21/2007: V0.3
+; 04/02/2007: V0.2
+; 02/05/2007: V0.1
+; 09/29/2006: V0.01
+;*******************************************************************************
+; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+    
+  THUMB
+  REQUIRE8
+  PRESERVE8
+    
+  AREA |.text|, CODE, READONLY, ALIGN=2
+
+  ; Exported functions
+  EXPORT __WFI
+  EXPORT __WFE
+  EXPORT __SEV
+  EXPORT __ISB
+  EXPORT __DSB
+  EXPORT __DMB
+  EXPORT __SVC
+  EXPORT __MRS_CONTROL
+  EXPORT __MSR_CONTROL
+  EXPORT __MRS_PSP
+  EXPORT __MSR_PSP
+  EXPORT __MRS_MSP
+  EXPORT __MSR_MSP   
+  EXPORT __SETPRIMASK
+  EXPORT __RESETPRIMASK
+  EXPORT __SETFAULTMASK
+  EXPORT __RESETFAULTMASK
+  EXPORT __BASEPRICONFIG
+  EXPORT __GetBASEPRI
+  EXPORT __REV_HalfWord
+  EXPORT __REV_Word
+
+;*******************************************************************************
+; Function Name  : __WFI
+; Description    : Assembler function for the WFI instruction.
+; Input          : None
+; Return         : None
+;*******************************************************************************
+__WFI 
+ 
+    WFI
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __WFE
+; Description    : Assembler function for the WFE instruction.
+; Input          : None
+; Return         : None
+;*******************************************************************************
+__WFE
+
+    WFE
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __SEV
+; Description    : Assembler function for the SEV instruction.
+; Input          : None
+; Return         : None
+;*******************************************************************************
+__SEV
+
+    SEV
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __ISB
+; Description    : Assembler function for the ISB instruction.
+; Input          : None
+; Return         : None
+;*******************************************************************************
+__ISB
+
+    ISB
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __DSB
+; Description    : Assembler function for the DSB instruction.
+; Input          : None
+; Return         : None
+;*******************************************************************************
+__DSB
+
+    DSB
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __DMB
+; Description    : Assembler function for the DMB instruction.
+; Input          : None
+; Return         : None
+;*******************************************************************************
+__DMB
+
+    DMB
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __SVC
+; Description    : Assembler function for the SVC instruction.
+; Input          : None
+; Return         : None
+;*******************************************************************************
+__SVC
+
+    SVC 0x01
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __MRS_CONTROL
+; Description    : Assembler function for the MRS instruction.
+; Input          : None
+; Return         : - r0 : Cortex-M3 CONTROL register value.
+;*******************************************************************************
+__MRS_CONTROL
+
+  MRS r0, CONTROL
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __MSR_CONTROL
+; Description    : Assembler function for the MSR instruction.
+; Input          : - r0 : Cortex-M3 CONTROL register new value.  
+; Return         : None
+;*******************************************************************************
+__MSR_CONTROL
+
+  MSR CONTROL, r0
+  ISB
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __MRS_PSP
+; Description    : Assembler function for the MRS instruction.
+; Input          : None
+; Return         : - r0 : Process Stack value.
+;*******************************************************************************
+__MRS_PSP
+
+  MRS r0, PSP
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __MSR_PSP
+; Description    : Assembler function for the MSR instruction.
+; Input          : - r0 : Process Stack new value.  
+; Return         : None
+;*******************************************************************************
+__MSR_PSP 
+ 
+    MSR PSP, r0 ; set Process Stack value
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __MRS_MSP
+; Description    : Assembler function for the MRS instruction.
+; Input          : None
+; Return         : - r0 : Main Stack value.
+;*******************************************************************************
+__MRS_MSP
+
+  MRS r0, MSP
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __MSR_MSP
+; Description    : Assembler function for the MSR instruction.
+; Input          : - r0 : Main Stack new value.  
+; Return         : None
+;*******************************************************************************
+__MSR_MSP 
+ 
+    MSR MSP, r0 ; set Main Stack value
+    BX r14
+
+;*******************************************************************************
+; Function Name  : __SETPRIMASK
+; Description    : Assembler function to set the PRIMASK.
+; Input          : None 
+; Return         : None
+;*******************************************************************************
+__SETPRIMASK
+
+  CPSID i
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __RESETPRIMASK
+; Description    : Assembler function to reset the PRIMASK.
+; Input          : None 
+; Return         : None
+;*******************************************************************************
+__RESETPRIMASK
+
+  CPSIE i
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __SETFAULTMASK
+; Description    : Assembler function to set the FAULTMASK.
+; Input          : None 
+; Return         : None
+;*******************************************************************************
+__SETFAULTMASK
+
+  CPSID f
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __RESETFAULTMASK
+; Description    : Assembler function to reset the FAULTMASK.
+; Input          : None 
+; Return         : None
+;*******************************************************************************
+__RESETFAULTMASK
+
+  CPSIE f
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __BASEPRICONFIG
+; Description    : Assembler function to set the Base Priority.
+; Input          : - r0 : Base Priority new value  
+; Return         : None
+;*******************************************************************************
+__BASEPRICONFIG
+
+  MSR BASEPRI, r0
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __GetBASEPRI
+; Description    : Assembler function to get the Base Priority value.
+; Input          : None 
+; Return         : - r0 : Base Priority value 
+;*******************************************************************************
+__GetBASEPRI
+
+  MRS r0, BASEPRI_MAX
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __REV_HalfWord
+; Description    : Reverses the byte order in HalfWord(16-bit) input variable.
+; Input          : - r0 : specifies the input variable
+; Return         : - r0 : holds tve variable value after byte reversing.
+;*******************************************************************************
+__REV_HalfWord 
+ 
+  REV16 r0, r0
+  BX r14
+
+;*******************************************************************************
+; Function Name  : __REV_Word
+; Description    : Reverses the byte order in Word(32-bit) input variable.
+; Input          : - r0 : specifies the input variable
+; Return         : - r0 : holds tve variable value after byte reversing.
+;*******************************************************************************
+__REV_Word 
+ 
+  REV r0, r0
+  BX r14
+    
+  END
+  
+;******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE*****
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/lcd.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/lcd.c
new file mode 100644
index 0000000..55a6e86
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/lcd.c
@@ -0,0 +1,1305 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : lcd.c
+* Author             : MCD Application Team
+* Date First Issued  : mm/dd/yyyy
+* Description        : This file includes the LCD driver for AM-240320LTNQW00H
+*                      liquid Crystal Display Module of STM32F10x-EVAL.
+********************************************************************************
+* History:
+* mm/dd/yyyy
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_type.h"
+#include "lcd.h"
+#include "spi_flash.h"
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+     /* ASCII Table: each character is 16 column (16dots large)
+        and 24 raw (24 dots high) */
+     const uc16 ASCII_Table[] =
+       {
+         /* Space ' ' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '!' */
+         0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, 0x0000,
+         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '"' */
+         0x0000, 0x0000, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC,
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '#' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C60, 0x0C60,
+         0x0C60, 0x0630, 0x0630, 0x1FFE, 0x1FFE, 0x0630, 0x0738, 0x0318,
+         0x1FFE, 0x1FFE, 0x0318, 0x0318, 0x018C, 0x018C, 0x018C, 0x0000,
+         /* '$' */
+         0x0000, 0x0080, 0x03E0, 0x0FF8, 0x0E9C, 0x1C8C, 0x188C, 0x008C,
+         0x0098, 0x01F8, 0x07E0, 0x0E80, 0x1C80, 0x188C, 0x188C, 0x189C,
+         0x0CB8, 0x0FF0, 0x03E0, 0x0080, 0x0080, 0x0000, 0x0000, 0x0000,
+         /* '%' */
+         0x0000, 0x0000, 0x0000, 0x180E, 0x0C1B, 0x0C11, 0x0611, 0x0611,
+         0x0311, 0x0311, 0x019B, 0x018E, 0x38C0, 0x6CC0, 0x4460, 0x4460,
+         0x4430, 0x4430, 0x4418, 0x6C18, 0x380C, 0x0000, 0x0000, 0x0000,
+         /* '&' */
+         0x0000, 0x01E0, 0x03F0, 0x0738, 0x0618, 0x0618, 0x0330, 0x01F0,
+         0x00F0, 0x00F8, 0x319C, 0x330E, 0x1E06, 0x1C06, 0x1C06, 0x3F06,
+         0x73FC, 0x21F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* ''' */
+         0x0000, 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '(' */
+         0x0000, 0x0200, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x0060, 0x0060,
+         0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,
+         0x0060, 0x0060, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0200, 0x0000,
+         /* ')' */
+         0x0000, 0x0020, 0x0060, 0x00C0, 0x0180, 0x0180, 0x0300, 0x0300,
+         0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,
+         0x0300, 0x0300, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0020, 0x0000,
+         /* '*' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
+         0x06D8, 0x07F8, 0x01E0, 0x0330, 0x0738, 0x0000, 0x0000, 0x0000,
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '+' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
+         0x0180, 0x0180, 0x0180, 0x3FFC, 0x3FFC, 0x0180, 0x0180, 0x0180,
+         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* ',' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         0x0000, 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000,
+         /* '-' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         0x0000, 0x0000, 0x0000, 0x0000, 0x07E0, 0x07E0, 0x0000, 0x0000,
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '.' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '/' */
+         0x0000, 0x0C00, 0x0C00, 0x0600, 0x0600, 0x0600, 0x0300, 0x0300,
+         0x0300, 0x0380, 0x0180, 0x0180, 0x0180, 0x00C0, 0x00C0, 0x00C0,
+         0x0060, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '0' */
+         0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x180C, 0x180C, 0x180C,
+         0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C18, 0x0E38,
+         0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '1' */
+         0x0000, 0x0100, 0x0180, 0x01C0, 0x01F0, 0x0198, 0x0188, 0x0180,
+         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '2' */
+         0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x1800,
+         0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,
+         0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '3' */
+         0x0000, 0x01E0, 0x07F8, 0x0E18, 0x0C0C, 0x0C0C, 0x0C00, 0x0600,
+         0x03C0, 0x07C0, 0x0C00, 0x1800, 0x1800, 0x180C, 0x180C, 0x0C18,
+         0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '4' */
+         0x0000, 0x0C00, 0x0E00, 0x0F00, 0x0F00, 0x0D80, 0x0CC0, 0x0C60,
+         0x0C60, 0x0C30, 0x0C18, 0x0C0C, 0x3FFC, 0x3FFC, 0x0C00, 0x0C00,
+         0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '5' */
+         0x0000, 0x0FF8, 0x0FF8, 0x0018, 0x0018, 0x000C, 0x03EC, 0x07FC,
+         0x0E1C, 0x1C00, 0x1800, 0x1800, 0x1800, 0x180C, 0x0C1C, 0x0E18,
+         0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '6' */
+         0x0000, 0x07C0, 0x0FF0, 0x1C38, 0x1818, 0x0018, 0x000C, 0x03CC,
+         0x0FEC, 0x0E3C, 0x1C1C, 0x180C, 0x180C, 0x180C, 0x1C18, 0x0E38,
+         0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '7' */
+         0x0000, 0x1FFC, 0x1FFC, 0x0C00, 0x0600, 0x0600, 0x0300, 0x0380,
+         0x0180, 0x01C0, 0x00C0, 0x00E0, 0x0060, 0x0060, 0x0070, 0x0030,
+         0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '8' */
+         0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x0C18, 0x0C18, 0x0638,
+         0x07F0, 0x07F0, 0x0C18, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C38,
+         0x0FF8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '9' */
+         0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C1C, 0x180C, 0x180C, 0x180C,
+         0x1C1C, 0x1E38, 0x1BF8, 0x19E0, 0x1800, 0x0C00, 0x0C00, 0x0E1C,
+         0x07F8, 0x01F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* ':' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* ';' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, 0x0000,
+         /* '<' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         0x1000, 0x1C00, 0x0F80, 0x03E0, 0x00F8, 0x0018, 0x00F8, 0x03E0,
+         0x0F80, 0x1C00, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '=' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         0x1FF8, 0x0000, 0x0000, 0x0000, 0x1FF8, 0x0000, 0x0000, 0x0000,
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '>' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         0x0008, 0x0038, 0x01F0, 0x07C0, 0x1F00, 0x1800, 0x1F00, 0x07C0,
+         0x01F0, 0x0038, 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '?' */
+         0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x0C00,
+         0x0600, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x0000, 0x0000,
+         0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '@' */
+         0x0000, 0x0000, 0x07E0, 0x1818, 0x2004, 0x29C2, 0x4A22, 0x4411,
+         0x4409, 0x4409, 0x4409, 0x2209, 0x1311, 0x0CE2, 0x4002, 0x2004,
+         0x1818, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'A' */
+         0x0000, 0x0380, 0x0380, 0x06C0, 0x06C0, 0x06C0, 0x0C60, 0x0C60,
+         0x1830, 0x1830, 0x1830, 0x3FF8, 0x3FF8, 0x701C, 0x600C, 0x600C,
+         0xC006, 0xC006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'B' */
+         0x0000, 0x03FC, 0x0FFC, 0x0C0C, 0x180C, 0x180C, 0x180C, 0x0C0C,
+         0x07FC, 0x0FFC, 0x180C, 0x300C, 0x300C, 0x300C, 0x300C, 0x180C,
+         0x1FFC, 0x07FC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'C' */
+         0x0000, 0x07C0, 0x1FF0, 0x3838, 0x301C, 0x700C, 0x6006, 0x0006,
+         0x0006, 0x0006, 0x0006, 0x0006, 0x0006, 0x6006, 0x700C, 0x301C,
+         0x1FF0, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'D' */
+         0x0000, 0x03FE, 0x0FFE, 0x0E06, 0x1806, 0x1806, 0x3006, 0x3006,
+         0x3006, 0x3006, 0x3006, 0x3006, 0x3006, 0x1806, 0x1806, 0x0E06,
+         0x0FFE, 0x03FE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'E' */
+         0x0000, 0x3FFC, 0x3FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
+         0x1FFC, 0x1FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
+         0x3FFC, 0x3FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'F' */
+         0x0000, 0x3FF8, 0x3FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
+         0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
+         0x0018, 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'G' */
+         0x0000, 0x0FE0, 0x3FF8, 0x783C, 0x600E, 0xE006, 0xC007, 0x0003,
+         0x0003, 0xFE03, 0xFE03, 0xC003, 0xC007, 0xC006, 0xC00E, 0xF03C,
+         0x3FF8, 0x0FE0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'H' */
+         0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
+         0x3FFC, 0x3FFC, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
+         0x300C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'I' */
+         0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'J' */
+         0x0000, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,
+         0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0618, 0x0618, 0x0738,
+         0x03F0, 0x01E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'K' */
+         0x0000, 0x3006, 0x1806, 0x0C06, 0x0606, 0x0306, 0x0186, 0x00C6,
+         0x0066, 0x0076, 0x00DE, 0x018E, 0x0306, 0x0606, 0x0C06, 0x1806,
+         0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'L' */
+         0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
+         0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
+         0x1FF8, 0x1FF8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'M' */
+         0x0000, 0xE00E, 0xF01E, 0xF01E, 0xF01E, 0xD836, 0xD836, 0xD836,
+         0xD836, 0xCC66, 0xCC66, 0xCC66, 0xC6C6, 0xC6C6, 0xC6C6, 0xC6C6,
+         0xC386, 0xC386, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'N' */
+         0x0000, 0x300C, 0x301C, 0x303C, 0x303C, 0x306C, 0x306C, 0x30CC,
+         0x30CC, 0x318C, 0x330C, 0x330C, 0x360C, 0x360C, 0x3C0C, 0x3C0C,
+         0x380C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'O' */
+         0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xC003, 0xC003,
+         0xC003, 0xC003, 0xC003, 0xC003, 0xC003, 0x6006, 0x700E, 0x381C,
+         0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'P' */
+         0x0000, 0x0FFC, 0x1FFC, 0x380C, 0x300C, 0x300C, 0x300C, 0x300C,
+         0x180C, 0x1FFC, 0x07FC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
+         0x000C, 0x000C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'Q' */
+         0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xE003, 0xC003,
+         0xC003, 0xC003, 0xC003, 0xC003, 0xE007, 0x6306, 0x3F0E, 0x3C1C,
+         0x3FF8, 0xF7E0, 0xC000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'R' */
+         0x0000, 0x0FFE, 0x1FFE, 0x3806, 0x3006, 0x3006, 0x3006, 0x3806,
+         0x1FFE, 0x07FE, 0x0306, 0x0606, 0x0C06, 0x1806, 0x1806, 0x3006,
+         0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'S' */
+         0x0000, 0x03E0, 0x0FF8, 0x0C1C, 0x180C, 0x180C, 0x000C, 0x001C,
+         0x03F8, 0x0FE0, 0x1E00, 0x3800, 0x3006, 0x3006, 0x300E, 0x1C1C,
+         0x0FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'T' */
+         0x0000, 0x7FFE, 0x7FFE, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'U' */
+         0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
+         0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x1818,
+         0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'V' */
+         0x0000, 0x6003, 0x3006, 0x3006, 0x3006, 0x180C, 0x180C, 0x180C,
+         0x0C18, 0x0C18, 0x0E38, 0x0630, 0x0630, 0x0770, 0x0360, 0x0360,
+         0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'W' */
+         0x0000, 0x6003, 0x61C3, 0x61C3, 0x61C3, 0x3366, 0x3366, 0x3366,
+         0x3366, 0x3366, 0x3366, 0x1B6C, 0x1B6C, 0x1B6C, 0x1A2C, 0x1E3C,
+         0x0E38, 0x0E38, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'X' */
+         0x0000, 0xE00F, 0x700C, 0x3018, 0x1830, 0x0C70, 0x0E60, 0x07C0,
+         0x0380, 0x0380, 0x03C0, 0x06E0, 0x0C70, 0x1C30, 0x1818, 0x300C,
+         0x600E, 0xE007, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'Y' */
+         0x0000, 0xC003, 0x6006, 0x300C, 0x381C, 0x1838, 0x0C30, 0x0660,
+         0x07E0, 0x03C0, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'Z' */
+         0x0000, 0x7FFC, 0x7FFC, 0x6000, 0x3000, 0x1800, 0x0C00, 0x0600,
+         0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, 0x000C, 0x0006,
+         0x7FFE, 0x7FFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '[' */
+         0x0000, 0x03E0, 0x03E0, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,
+         0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,
+         0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x03E0, 0x03E0, 0x0000,
+         /* '\' */
+         0x0000, 0x0030, 0x0030, 0x0060, 0x0060, 0x0060, 0x00C0, 0x00C0,
+         0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0300, 0x0300, 0x0300,
+         0x0600, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* ']' */
+         0x0000, 0x03E0, 0x03E0, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,
+         0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,
+         0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x03E0, 0x03E0, 0x0000,
+         /* '^' */
+         0x0000, 0x0000, 0x01C0, 0x01C0, 0x0360, 0x0360, 0x0360, 0x0630,
+         0x0630, 0x0C18, 0x0C18, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '_' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         0x0000, 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* ''' */
+         0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0000,
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'a' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03F0, 0x07F8,
+         0x0C1C, 0x0C0C, 0x0F00, 0x0FF0, 0x0CF8, 0x0C0C, 0x0C0C, 0x0F1C,
+         0x0FF8, 0x18F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'b' */
+         0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x03D8, 0x0FF8,
+         0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,
+         0x0FF8, 0x03D8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'c' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x07F0,
+         0x0E30, 0x0C18, 0x0018, 0x0018, 0x0018, 0x0018, 0x0C18, 0x0E30,
+         0x07F0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'd' */
+         0x0000, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1BC0, 0x1FF0,
+         0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,
+         0x1FF0, 0x1BC0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'e' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,
+         0x0C30, 0x1818, 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x1838, 0x1C30,
+         0x0FF0, 0x07C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'f' */
+         0x0000, 0x0F80, 0x0FC0, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,
+         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
+         0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'g' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0DE0, 0x0FF8,
+         0x0E18, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0E18,
+         0x0FF8, 0x0DE0, 0x0C00, 0x0C0C, 0x061C, 0x07F8, 0x01F0, 0x0000,
+         /* 'h' */
+         0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x07D8, 0x0FF8,
+         0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,
+         0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'i' */
+         0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
+         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
+         0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'j' */
+         0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
+         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
+         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00F8, 0x0078, 0x0000,
+         /* 'k' */
+         0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0C0C, 0x060C,
+         0x030C, 0x018C, 0x00CC, 0x006C, 0x00FC, 0x019C, 0x038C, 0x030C,
+         0x060C, 0x0C0C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'l' */
+         0x0000, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
+         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
+         0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'm' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3C7C, 0x7EFF,
+         0xE3C7, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183,
+         0xC183, 0xC183, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'n' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0798, 0x0FF8,
+         0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,
+         0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'o' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,
+         0x0C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C30,
+         0x0FF0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'p' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03D8, 0x0FF8,
+         0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,
+         0x0FF8, 0x03D8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0000,
+         /* 'q' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1BC0, 0x1FF0,
+         0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,
+         0x1FF0, 0x1BC0, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x0000,
+         /* 'r' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x07B0, 0x03F0,
+         0x0070, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,
+         0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 's' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03E0, 0x03F0,
+         0x0E38, 0x0C18, 0x0038, 0x03F0, 0x07C0, 0x0C00, 0x0C18, 0x0E38,
+         0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 't' */
+         0x0000, 0x0000, 0x0080, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,
+         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
+         0x07C0, 0x0780, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'u' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1818, 0x1818,
+         0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C38,
+         0x1FF0, 0x19E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'v' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x180C, 0x0C18,
+         0x0C18, 0x0C18, 0x0630, 0x0630, 0x0630, 0x0360, 0x0360, 0x0360,
+         0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'w' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x41C1, 0x41C1,
+         0x61C3, 0x6363, 0x6363, 0x6363, 0x3636, 0x3636, 0x3636, 0x1C1C,
+         0x1C1C, 0x1C1C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'x' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x381C, 0x1C38,
+         0x0C30, 0x0660, 0x0360, 0x0360, 0x0360, 0x0360, 0x0660, 0x0C30,
+         0x1C38, 0x381C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* 'y' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3018, 0x1830,
+         0x1830, 0x1870, 0x0C60, 0x0C60, 0x0CE0, 0x06C0, 0x06C0, 0x0380,
+         0x0380, 0x0380, 0x0180, 0x0180, 0x01C0, 0x00F0, 0x0070, 0x0000,
+         /* 'z' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1FFC, 0x1FFC,
+         0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,
+         0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         /* '{' */
+         0x0000, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
+         0x00C0, 0x0060, 0x0060, 0x0030, 0x0060, 0x0040, 0x00C0, 0x00C0,
+         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0000, 0x0000,
+         /* '|' */
+         0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000,
+         /* '}' */
+         0x0000, 0x0060, 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0180,
+         0x0180, 0x0300, 0x0300, 0x0600, 0x0300, 0x0100, 0x0180, 0x0180,
+         0x0180, 0x0180, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0000, 0x0000,
+         /* '~' */
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         0x10F0, 0x1FF8, 0x0F08, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+      };
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+  /* Global variables to set the written text color */
+static  vu16 TextColor = 0x0000, BackColor = 0xFFFF;
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+static u32 StrLength(u8 *Str);
+
+/*******************************************************************************
+* Function Name  : LCD_Init
+* Description    : Initializes LCD.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void LCD_Init(void)
+{
+/* Configure the LCD Control pins --------------------------------------------*/
+  LCD_CtrlLinesConfig();
+
+/* Configure the SPI2 interface ----------------------------------------------*/
+  LCD_SPIConfig();
+
+/* Enable the LCD Oscillator -------------------------------------------------*/
+  LCD_WriteReg(R1, 0x10);
+  LCD_WriteReg(R0, 0xA0);
+  LCD_WriteReg(R3, 0x01);
+  vTaskDelay( 10 / portTICK_PERIOD_MS ); /* Delay 10 ms */
+  LCD_WriteReg(R3, 0x00);
+  LCD_WriteReg(R43, 0x04);
+
+  LCD_WriteReg(R40, 0x18);
+  LCD_WriteReg(R26, 0x05);
+  LCD_WriteReg(R37, 0x05);
+  LCD_WriteReg(R25, 0x00);
+
+/* LCD Power On --------------------------------------------------------------*/
+  LCD_WriteReg(R28, 0x73);
+  LCD_WriteReg(R36, 0x74);
+  LCD_WriteReg(R30, 0x01);
+  LCD_WriteReg(R24, 0xC1);
+  vTaskDelay( 10 / portTICK_PERIOD_MS ); /* Delay 10 ms */
+  LCD_WriteReg(R24, 0xE1);
+  LCD_WriteReg(R24, 0xF1);
+  vTaskDelay( 60 / portTICK_PERIOD_MS ); /* Delay 60 ms */
+  LCD_WriteReg(R24, 0xF5);
+  vTaskDelay( 60 / portTICK_PERIOD_MS ); /* Delay 60 ms */
+  LCD_WriteReg(R27, 0x09);
+  vTaskDelay( 10 / portTICK_PERIOD_MS ); /* Delay 10 ms */
+  LCD_WriteReg(R31, 0x11);
+  LCD_WriteReg(R32, 0x0E);
+  LCD_WriteReg(R30, 0x81);
+  vTaskDelay( 10 / portTICK_PERIOD_MS ); /* Delay 10 ms */
+
+/* Chip Set ------------------------------------------------------------------*/
+  LCD_WriteReg(R157, 0x00);
+  LCD_WriteReg(R192, 0x00);
+
+  LCD_WriteReg(R14, 0x00);
+  LCD_WriteReg(R15, 0x00);
+  LCD_WriteReg(R16, 0x00);
+  LCD_WriteReg(R17, 0x00);
+  LCD_WriteReg(R18, 0x00);
+  LCD_WriteReg(R19, 0x00);
+  LCD_WriteReg(R20, 0x00);
+  LCD_WriteReg(R21, 0x00);
+  LCD_WriteReg(R22, 0x00);
+  LCD_WriteReg(R23, 0x00);
+
+  LCD_WriteReg(R52, 0x01);
+  LCD_WriteReg(R53, 0x00);
+
+  LCD_WriteReg(R75, 0x00);
+  LCD_WriteReg(R76, 0x00);
+  LCD_WriteReg(R78, 0x00);
+  LCD_WriteReg(R79, 0x00);
+  LCD_WriteReg(R80, 0x00);
+
+  LCD_WriteReg(R60, 0x00);
+  LCD_WriteReg(R61, 0x00);
+  LCD_WriteReg(R62, 0x01);
+  LCD_WriteReg(R63, 0x3F);
+  LCD_WriteReg(R64, 0x02);
+  LCD_WriteReg(R65, 0x02);
+  LCD_WriteReg(R66, 0x00);
+  LCD_WriteReg(R67, 0x00);
+  LCD_WriteReg(R68, 0x00);
+  LCD_WriteReg(R69, 0x00);
+  LCD_WriteReg(R70, 0xEF);
+  LCD_WriteReg(R71, 0x00);
+  LCD_WriteReg(R72, 0x00);
+  LCD_WriteReg(R73, 0x01);
+  LCD_WriteReg(R74, 0x3F);
+
+  LCD_WriteReg(R29, 0x08);  /* R29:Gate scan direction setting */
+
+  LCD_WriteReg(R134, 0x00);
+  LCD_WriteReg(R135, 0x30);
+  LCD_WriteReg(R136, 0x02);
+  LCD_WriteReg(R137, 0x05);
+
+  LCD_WriteReg(R141, 0x01);  /* R141:Register set-up mode for one line clock */
+  LCD_WriteReg(R139, 0x20);  /* R139:One line SYSCLK number in one-line */
+  LCD_WriteReg(R51, 0x01);  /* R51:N line inversion setting */
+  LCD_WriteReg(R55, 0x01);  /* R55:Scanning method setting */
+  LCD_WriteReg(R118, 0x00);
+
+/* Gamma Set -----------------------------------------------------------------*/
+  LCD_WriteReg(R143, 0x10);
+  LCD_WriteReg(R144, 0x67);
+  LCD_WriteReg(R145, 0x07);
+  LCD_WriteReg(R146, 0x65);
+  LCD_WriteReg(R147, 0x07);
+  LCD_WriteReg(R148, 0x01);
+  LCD_WriteReg(R149, 0x76);
+  LCD_WriteReg(R150, 0x56);
+  LCD_WriteReg(R151, 0x00);
+  LCD_WriteReg(R152, 0x06);
+  LCD_WriteReg(R153, 0x03);
+  LCD_WriteReg(R154, 0x00);
+
+/* Display On ----------------------------------------------------------------*/
+  LCD_WriteReg(R1, 0x50);
+  LCD_WriteReg(R5, 0x04);
+
+  LCD_WriteReg(R0, 0x80);
+  LCD_WriteReg(R59, 0x01);
+  vTaskDelay( 40 / portTICK_PERIOD_MS );  /* Delay 40 ms */
+  LCD_WriteReg(R0, 0x20);
+}
+
+/*******************************************************************************
+* Function Name  : LCD_SetTextColor
+* Description    : Sets the Text color.
+* Input          : - Color: specifies the Text color code RGB(5-6-5).
+* Output         : - TextColor: Text color global variable used by LCD_DrawChar
+*                  and LCD_DrawPicture functions.
+* Return         : None
+*******************************************************************************/
+void LCD_SetTextColor(vu16 Color)
+{
+  TextColor = Color;
+}
+
+/*******************************************************************************
+* Function Name  : LCD_SetBackColor
+* Description    : Sets the Background color.
+* Input          : - Color: specifies the Background color code RGB(5-6-5).
+* Output         : - BackColor: Background color global variable used by
+*                  LCD_DrawChar and LCD_DrawPicture functions.
+* Return         : None
+*******************************************************************************/
+void LCD_SetBackColor(vu16 Color)
+{
+  BackColor = Color;
+}
+
+/*******************************************************************************
+* Function Name  : LCD_ClearLine
+* Description    : Clears the selected line.
+* Input          : - Line: the Line to be cleared.
+*                    This parameter can be one of the following values:
+*                       - Linex: where x can be 0..9
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void LCD_ClearLine(u8 Line)
+{
+  LCD_DisplayStringLine(Line, "                    ");
+}
+
+/*******************************************************************************
+* Function Name  : LCD_Clear
+* Description    : Clears the hole LCD.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void LCD_Clear(void)
+{
+  u32 index = 0;
+
+  LCD_SetCursor(0x00, 0x013F);
+
+  for(index = 0; index < 0x12C00; index++)
+  {
+    LCD_WriteRAM(White);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : LCD_SetCursor
+* Description    : Sets the cursor position.
+* Input          : - Xpos: specifies the X position.
+*                  - Ypos: specifies the Y position.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void LCD_SetCursor(u8 Xpos, u16 Ypos)
+{
+  LCD_WriteReg(R66, Xpos);
+  LCD_WriteReg(R67, ((Ypos & 0x100)>> 8));
+  LCD_WriteReg(R68, (Ypos & 0xFF));
+}
+
+/*******************************************************************************
+* Function Name  : LCD_DrawChar
+* Description    : Draws a character on LCD.
+* Input          : - Xpos: the Line where to display the character shape.
+*                    This parameter can be one of the following values:
+*                       - Linex: where x can be 0..9
+*                  - Ypos: start column address.
+*                  - c: pointer to the character data.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void LCD_DrawChar(u8 Xpos, u16 Ypos, uc16 *c)
+{
+  u32 index = 0, i = 0;
+  u8 Xaddress = 0;
+
+  Xaddress = Xpos;
+
+  LCD_SetCursor(Xaddress, Ypos);
+
+  for(index = 0; index < 24; index++)
+  {
+    for(i = 0; i < 16; i++)
+    {
+      if((c[index] & (1 << i)) == 0x00)
+      {
+        LCD_WriteRAM(BackColor);
+      }
+      else
+      {
+        LCD_WriteRAM(TextColor);
+      }
+    }
+    Xaddress++;
+    LCD_SetCursor(Xaddress, Ypos);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : LCD_DisplayChar
+* Description    : Displays one character (16dots width, 24dots height).
+* Input          : - Line: the Line where to display the character shape .
+*                    This parameter can be one of the following values:
+*                       - Linex: where x can be 0..9
+*                  - Column: start column address.
+*                  - Ascii: character ascii code, must be between 0x20 and 0x7E.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void LCD_DisplayChar(u8 Line, u16 Column, u8 Ascii)
+{
+  Ascii -= 32;
+  LCD_DrawChar(Line, Column, &ASCII_Table[Ascii * 24]);
+}
+
+/*******************************************************************************
+* Function Name  : LCD_DisplayStringLine
+* Description    : Displays a maximum of 20 char on the LCD.
+* Input          : - Line: the Line where to display the character shape .
+*                    This parameter can be one of the following values:
+*                       - Linex: where x can be 0..9
+*                  - *ptr: pointer to string to display on LCD.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void LCD_DisplayStringLine(u8 Line, u8 *ptr)
+{
+  u32 i = 0;
+  u16 refcolumn = 319;
+
+  /* Send the string character by character on lCD */
+  while ((*ptr != 0) & (i < 20))
+  {
+    /* Display one character on LCD */
+    LCD_DisplayChar(Line, refcolumn, *ptr);
+    /* Decrement the column position by 16 */
+    refcolumn -= 16;
+    /* Point on the next character */
+    ptr++;
+    /* Increment the character counter */
+    i++;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : LCD_DisplayString
+* Description    : Displays a maximum of 200 char on the LCD.
+* Input          : - Line: the starting Line where to display the character shape.
+*                    This parameter can be one of the following values:
+*                       - Linex: where x can be 0..9
+*                  - *ptr: pointer to string to display on LCD.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void LCD_DisplayString(u8 Line, u8 *ptr)
+{
+  u32 i = 0, column = 0, index = 0, spaceindex = 0;
+  u16 refcolumn = 319;
+  u32 length = 0;
+
+  /* Get the string length */
+  length = StrLength(ptr);
+  if(length > 200)
+  {
+    /* Set the Cursor position */
+    LCD_SetCursor(Line, 0x013F);
+    /* Clear the Selected Line */
+    LCD_ClearLine(Line);
+    LCD_DisplayStringLine(Line, "   String too long  ");
+  }
+  else
+  {
+    /* Set the Cursor position */
+    LCD_SetCursor(Line, 0x013F);
+    /* Clear the Selected Line */
+    LCD_ClearLine(Line);
+
+    while(length--)
+    {
+      if(index == 20)
+      {
+        if(*ptr == 0x20)
+        {
+          ptr++;
+        }
+        else
+        {
+          for(i = 0; i < spaceindex; i++)
+          {
+            LCD_DisplayChar(Line, column, ' ');
+            column -= 16;
+          }
+          ptr -= (spaceindex - 1);
+          length += (spaceindex - 1);
+        }
+        Line += 24;
+        /* Clear the Selected Line */
+        LCD_ClearLine(Line);
+        refcolumn = 319;
+        index = 0;
+      }
+      /* Display one character on LCD */
+      LCD_DisplayChar(Line, refcolumn, *ptr);
+
+      /* Increment character number in one line */
+      index++;
+
+      /* Decrement the column position by 16 */
+      refcolumn -= 16;
+      /* Point on the next character */
+      ptr++;
+      /* Increment the number of character after the last space */
+      spaceindex++;
+      if(*ptr == 0x20)
+      {
+        spaceindex = 0;
+        column = refcolumn - 16;
+      }
+    }
+  }
+}
+
+/*******************************************************************************
+* Function Name  : LCD_ScrollText
+* Description    :
+* Input          :
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void LCD_ScrollText(u8 Line, u8 *ptr)
+{
+  u32 i = 0, length = 0, x = 0;
+  u16 refcolumn = 319;
+
+  /* Get the string length */
+  length = StrLength(ptr);
+
+  while(1)
+  {
+    /* Send the string character by character on lCD */
+    while ((*ptr != 0) & (i < 20))
+    {
+      /* Display one character on LCD */
+      LCD_DisplayChar(Line, refcolumn, *ptr);
+      /* Decrement the column position by 16 */
+      refcolumn -= 16;
+      /* Point on the next character */
+      ptr++;
+      /* Increment the character counter */
+      i++;
+    }
+    vTaskDelay( 100 / portTICK_PERIOD_MS );
+    i = 0;
+    //LCD_ClearLine(Line);
+    ptr -= length;
+    x++;
+    if(refcolumn < 16)
+    {
+      x = 0;
+    }
+    refcolumn = 319 - (x * 16);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : LCD_SetDisplayWindow
+* Description    : Sets a display window
+* Input          : - Xpos: specifies the X position.
+*                  - Ypos: specifies the Y position.
+*                  - Height: display window height.
+*                  - Width: display window width.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void LCD_SetDisplayWindow(u8 Xpos, u16 Ypos, u8 Height, u16 Width)
+{
+  LCD_WriteReg(R1, 0xD0);
+  LCD_WriteReg(R5, 0x14);
+
+  LCD_WriteReg(R69, Xpos);
+  LCD_WriteReg(R70, (Xpos + Height + 1));
+
+  LCD_WriteReg(R71, ((Ypos & 0x100)>> 8));
+  LCD_WriteReg(R72, (Ypos & 0xFF));
+
+  LCD_WriteReg(R73, (((Ypos + Width + 1) & 0x100)>> 8));
+  LCD_WriteReg(R74, ((Ypos + Width + 1) & 0xFF));
+
+  LCD_SetCursor(Xpos, Ypos);
+}
+
+/*******************************************************************************
+* Function Name  : LCD_DrawLine
+* Description    : Displays a line.
+* Input          : - Xpos: specifies the X position.
+*                  - Ypos: specifies the Y position.
+*                  - Length: line length.
+*                  - Direction: line direction.
+*                    This parameter can be one of the following values: Vertical
+*                    or Horizontal.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void LCD_DrawLine(u8 Xpos, u16 Ypos, u16 Length, u8 Direction)
+{
+  u32 i = 0;
+
+  LCD_SetCursor(Xpos, Ypos);
+
+  if(Direction == Horizontal)
+  {
+    for(i = 0; i < Length; i++)
+    {
+      LCD_WriteRAM(TextColor);
+    }
+  }
+  else
+  {
+   for(i = 0; i < Length; i++)
+    {
+
+      LCD_WriteRAM(TextColor);
+      Xpos++;
+      LCD_SetCursor(Xpos, Ypos);
+    }
+  }
+}
+
+/*******************************************************************************
+* Function Name  : LCD_DrawRect
+* Description    : Displays a rectangle.
+* Input          : - Xpos: specifies the X position.
+*                  - Ypos: specifies the Y position.
+*                  - Height: display rectangle height.
+*                  - Width: display rectangle width.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void LCD_DrawRect(u8 Xpos, u16 Ypos, u8 Height, u16 Width)
+{
+  LCD_DrawLine(Xpos, Ypos, Width, Horizontal);
+  LCD_DrawLine((Xpos + Height), Ypos, Width, Horizontal);
+
+  LCD_DrawLine(Xpos, Ypos, Height, Vertical);
+  LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, Vertical);
+}
+
+/*******************************************************************************
+* Function Name  : LCD_DrawCircle
+* Description    : Displays a circle.
+* Input          : - Xpos: specifies the X position.
+*                  - Ypos: specifies the Y position.
+*                  - Height: display rectangle height.
+*                  - Width: display rectangle width.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void LCD_DrawCircle(u8 Xpos, u16 Ypos, u16 Radius)
+{
+  s32	D;	/* Decision Variable */
+  u32	CurX;	/* Current X Value */
+  u32	CurY;	/* Current Y Value */
+
+  D = 3 - (Radius << 1);
+  CurX = 0;
+  CurY = Radius;
+
+  while (CurX <= CurY)
+  {
+    LCD_SetCursor(Xpos + CurX, Ypos + CurY);
+    LCD_WriteRAM(TextColor);
+    LCD_SetCursor(Xpos + CurX, Ypos - CurY);
+    LCD_WriteRAM(TextColor);
+    LCD_SetCursor(Xpos - CurX, Ypos + CurY);
+    LCD_WriteRAM(TextColor);
+    LCD_SetCursor(Xpos - CurX, Ypos - CurY);
+    LCD_WriteRAM(TextColor);
+    LCD_SetCursor(Xpos + CurY, Ypos + CurX);
+    LCD_WriteRAM(TextColor);
+    LCD_SetCursor(Xpos + CurY, Ypos - CurX);
+    LCD_WriteRAM(TextColor);
+    LCD_SetCursor(Xpos - CurY, Ypos + CurX);
+    LCD_WriteRAM(TextColor);
+    LCD_SetCursor(Xpos - CurY, Ypos - CurX);
+    LCD_WriteRAM(TextColor);
+
+    if (D < 0)
+    {
+      D += (CurX << 2) + 6;
+    }
+    else
+    {
+      D += ((CurX - CurY) << 2) + 10;
+      CurY--;
+    }
+    CurX++;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : LCD_DrawMonoPict
+* Description    : Displays a monocolor picture.
+* Input          : - Pict: pointer to the picture array.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void LCD_DrawMonoPict(uc32 *Pict)
+{
+  u32 index = 0, i = 0;
+
+  LCD_SetCursor(0, 319);
+
+  for(index = 0; index < 2400; index++)
+  {
+    for(i = 0; i < 32; i++)
+    {
+      if((Pict[index] & (1 << i)) == 0x00)
+      {
+        LCD_WriteRAM(BackColor);
+      }
+      else
+      {
+        LCD_WriteRAM(TextColor);
+      }
+    }
+  }
+}
+
+/*******************************************************************************
+* Function Name  : LCD_DrawBMP
+* Description    : Displays a bitmap picture loaded in the SPI Flash.
+* Input          : - BmpAddress: Bmp picture address in the SPI Flash.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void LCD_DrawBMP(u32 BmpAddress)
+{
+  u32 i = 0;
+
+  LCD_WriteReg(R1, 0xD0);
+  LCD_WriteReg(R5, 0x04);
+
+  LCD_SetCursor(239, 0x013F);
+
+  SPI_FLASH_StartReadSequence(BmpAddress);
+
+  /* Disable SPI1  */
+  SPI_Cmd(SPI1, DISABLE);
+  /* SPI in 16-bit mode */
+  SPI_DataSizeConfig(SPI1, SPI_DataSize_16b);
+  /* Enable SPI1  */
+  SPI_Cmd(SPI1, ENABLE);
+
+  for(i = 0; i < 76800; i++)
+  {
+    LCD_WriteRAM(__REV_HalfWord(SPI_FLASH_SendHalfWord(0xA5A5)));
+  }
+
+  /* Deselect the FLASH: Chip Select high */
+  SPI_FLASH_ChipSelect(1);
+
+  /* Disable SPI1  */
+  SPI_Cmd(SPI1, DISABLE);
+  /* SPI in 8-bit mode */
+  SPI_DataSizeConfig(SPI1, SPI_DataSize_8b);
+  /* Enable SPI1  */
+  SPI_Cmd(SPI1, ENABLE);
+}
+
+/*******************************************************************************
+* Function Name  : LCD_WriteReg
+* Description    : Writes to the selected LCD register.
+* Input          : - LCD_Reg: address of the selected register.
+*                  - LCD_RegValue: value to write to the selected register.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void LCD_WriteReg(u8 LCD_Reg, u8 LCD_RegValue)
+{
+  u16 tmp = 0;
+
+  LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_RESET);
+  LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_RESET);
+  LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET);
+
+  tmp = LCD_Reg << 8;
+  tmp |= LCD_RegValue;
+
+  SPI_SendData(SPI2, tmp);
+  while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
+  {
+  }
+
+  LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET);
+}
+
+/*******************************************************************************
+* Function Name  : LCD_ReadReg
+* Description    : Reads the selected LCD Register.
+* Input          : None
+* Output         : None
+* Return         : LCD Register Value.
+*******************************************************************************/
+u8 LCD_ReadReg(u8 LCD_Reg)
+{
+  u16 tmp = 0;
+
+  LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_RESET);
+  LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_RESET);
+  LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET);
+
+  while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
+  {
+  }
+  SPI_SendData(SPI2, LCD_Reg);
+
+  LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_SET);
+
+  while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
+  {
+  }
+  SPI_SendData(SPI2, 0xFF);
+
+  while(SPI_GetFlagStatus(SPI2, SPI_FLAG_RXNE)== RESET)
+  {
+  }
+  tmp = SPI_ReceiveData(SPI2);
+
+  LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET);
+  return tmp;
+}
+
+/*******************************************************************************
+* Function Name  : LCD_WriteRAM
+* Description    : Writes to the LCD RAM.
+* Input          : - RGB_Code: the pixel color in RGB mode (5-6-5).
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void LCD_WriteRAM(u16 RGB_Code)
+{
+  LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_RESET);
+  LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_SET);
+  LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET);
+
+  SPI_SendData(SPI2, RGB_Code);
+  while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
+  {
+  }
+
+  LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET);
+}
+
+/*******************************************************************************
+* Function Name  : LCD_ReadRAM
+* Description    : Reads the LCD RAM.
+* Input          : None
+* Output         : None
+* Return         : LCD RAM Value.
+*******************************************************************************/
+u16  LCD_ReadRAM(void)
+{
+  u16 tmp = 0;
+
+  LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_SET);
+  LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_SET);
+  LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET);
+
+  while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
+  {
+  }
+  SPI_SendData(SPI2, 0xFF);
+  while(SPI_GetFlagStatus(SPI2, SPI_FLAG_RXNE)==RESET)
+  {
+  }
+  tmp = SPI_ReceiveData(SPI2);
+
+  LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET);
+
+  return tmp;
+}
+
+/*******************************************************************************
+* Function Name  : LCD_PowerOn
+* Description    :
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void LCD_PowerOn(void)
+{
+  /* Power On Set */
+  LCD_WriteReg(R28, 0x73);
+  LCD_WriteReg(R36, 0x74);
+  LCD_WriteReg(R30, 0x01);
+  LCD_WriteReg(R24, 0xC1);
+  vTaskDelay( 10 / portTICK_PERIOD_MS ); /* Delay 10 ms */
+  LCD_WriteReg(R24, 0xE1);
+  LCD_WriteReg(R24, 0xF1);
+  vTaskDelay( 60 / portTICK_PERIOD_MS ); /* Delay 60 ms */
+  LCD_WriteReg(R24, 0xF5);
+  vTaskDelay( 60 / portTICK_PERIOD_MS ); /* Delay 60 ms */
+  LCD_WriteReg(R27, 0x09);
+  vTaskDelay( 10 / portTICK_PERIOD_MS ); /* Delay 10 ms */
+  LCD_WriteReg(R31, 0x11);
+  LCD_WriteReg(R32, 0x0E);
+  LCD_WriteReg(R30, 0x81);
+  vTaskDelay( 10 / portTICK_PERIOD_MS ); /* Delay 10 ms */
+}
+
+/*******************************************************************************
+* Function Name  : LCD_DisplayOn
+* Description    : Enables the Display.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void LCD_DisplayOn(void)
+{
+  LCD_WriteReg(R1, 0x50);
+  LCD_WriteReg(R5, 0x04);
+
+  /* Display On */
+  LCD_WriteReg(R0, 0x80);
+  LCD_WriteReg(R59, 0x01);
+  vTaskDelay( 40 / portTICK_PERIOD_MS );                 /* Delay 40 ms */
+  LCD_WriteReg(R0, 0x20);
+}
+
+/*******************************************************************************
+* Function Name  : LCD_DisplayOff
+* Description    : Disables the Display.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void LCD_DisplayOff(void)
+{
+  /* Display Off */
+  LCD_WriteReg(R0, 0xA0);
+  vTaskDelay( 40 / portTICK_PERIOD_MS );                 /* Delay 40 ms */
+  LCD_WriteReg(R59, 0x00);
+}
+
+/*******************************************************************************
+* Function Name  : LCD_CtrlLinesConfig
+* Description    : Configures LCD control lines in Output Push-Pull mode.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void LCD_CtrlLinesConfig(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  /* Configure NCS (PB.02) in Output Push-Pull mode */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+  GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+  /* Configure NWR(RNW), RS (PD.15, PD.07) in Output Push-Pull mode */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_15;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+}
+
+/*******************************************************************************
+* Function Name  : LCD_CtrlLinesWrite
+* Description    : Sets or reset LCD control lines.
+* Input          : - GPIOx: where x can be B or D to select the GPIO peripheral.
+*                  - CtrlPins: the Control line. This parameter can be:
+*                       - CtrlPin_NCS: Chip Select pin (PB.02)
+*                       - CtrlPin_NWR: Read/Write Selection pin (PD.15)
+*                       - CtrlPin_RS: Register/RAM Selection pin (PD.07)
+*                  - BitVal: specifies the value to be written to the selected bit.
+*                    This parameter can be:
+*                       - Bit_RESET: to clear the port pin
+*                       - Bit_SET: to set the port pin
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u16 CtrlPins, BitAction BitVal)
+{
+  /* Set or Reset the control line */
+  GPIO_WriteBit(GPIOx, CtrlPins, BitVal);
+}
+
+/*******************************************************************************
+* Function Name  : LCD_SPIConfig
+* Description    : Configures the SPI2 interface.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void LCD_SPIConfig(void)
+{
+  SPI_InitTypeDef    SPI_InitStructure;
+  GPIO_InitTypeDef   GPIO_InitStructure;
+
+  /* Enable GPIOA clock */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
+
+  /* Enable SPI2 clock  */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
+
+  /* Configure SPI2 pins: NSS, SCK, MISO and MOSI */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+  /* SPI2 Config */
+  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
+  SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b;
+  SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
+  SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
+  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
+  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+  SPI_Init(SPI2, &SPI_InitStructure);
+
+  /* SPI2 enable */
+  SPI_Cmd(SPI2, ENABLE);
+}
+
+/*******************************************************************************
+* Function Name  : StrLength
+* Description    : Returns length of string.
+* Input          : - Str: Character Pointer.
+* Output         : None
+* Return         : String length.
+*******************************************************************************/
+static u32 StrLength(u8 *Str)
+{
+  u32 Index = 0;
+
+  /* Increment the Index unless the end of string */
+  for(Index = 0; *Str != '\0'; Str++, Index++)
+  {
+  }
+
+  return Index;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/misc.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/misc.c
new file mode 100644
index 0000000..4378727
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/misc.c
@@ -0,0 +1,230 @@
+/**
+  ******************************************************************************
+  * @file  misc.c
+  * @author  MCD Application Team
+  * @version  V3.0.0
+  * @date  04/06/2009
+  * @brief  This file provides all the miscellaneous firmware functions.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
© COPYRIGHT 2009 STMicroelectronics

+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "misc.h"
+
+/** @addtogroup StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup MISC 
+  * @brief MISC driver modules
+  * @{
+  */
+
+/** @defgroup MISC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/** @defgroup MISC_Private_Defines
+  * @{
+  */
+
+#define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Configures the priority grouping: pre-emption priority and 
+  *         subpriority.
+  * @param NVIC_PriorityGroup: specifies the priority grouping bits length. 
+  *   This parameter can be one of the following values:
+  * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
+  *                            4 bits for subpriority
+  * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
+  *                            3 bits for subpriority
+  * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
+  *                            2 bits for subpriority
+  * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
+  *                            1 bits for subpriority
+  * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
+  *                            0 bits for subpriority
+  * @retval : None
+  */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+  
+  /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+  SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+  * @brief  Initializes the NVIC peripheral according to the specified
+  *   parameters in the NVIC_InitStruct.
+  * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure
+  *   that contains the configuration information for the
+  *   specified NVIC peripheral.
+  * @retval : None
+  */
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+  uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));  
+  assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+    
+  if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+  {
+    /* Compute the Corresponding IRQ Priority --------------------------------*/    
+    tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
+    tmppre = (0x4 - tmppriority);
+    tmpsub = tmpsub >> tmppriority;
+
+    tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+    tmppriority |=  NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
+    tmppriority = tmppriority << 0x04;
+        
+    NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+    
+    /* Enable the Selected IRQ Channels --------------------------------------*/
+    NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+  else
+  {
+    /* Disable the Selected IRQ Channels -------------------------------------*/
+    NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+}
+
+/**
+  * @brief  Sets the vector table location and Offset.
+  * @param NVIC_VectTab: specifies if the vector table is in RAM or
+  *   FLASH memory.
+  *   This parameter can be one of the following values:
+  * @arg NVIC_VectTab_RAM
+  * @arg NVIC_VectTab_FLASH
+  * @param Offset: Vector Table base offset field. 
+  *   This value must be a multiple of 0x100.
+  * @retval : None
+  */
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{ 
+  /* Check the parameters */
+  assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
+  assert_param(IS_NVIC_OFFSET(Offset));  
+   
+  SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+  * @brief  Selects the condition for the system to enter low power mode.
+  * @param LowPowerMode: Specifies the new mode for the system to enter
+  *   low power mode.
+  *   This parameter can be one of the following values:
+  * @arg NVIC_LP_SEVONPEND
+  * @arg NVIC_LP_SLEEPDEEP
+  * @arg NVIC_LP_SLEEPONEXIT
+  * @param NewState: new state of LP condition.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_LP(LowPowerMode));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  
+  
+  if (NewState != DISABLE)
+  {
+    SCB->SCR |= LowPowerMode;
+  }
+  else
+  {
+    SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+  }
+}
+
+/**
+  * @brief  Configures the SysTick clock source.
+  * @param SysTick_CLKSource: specifies the SysTick clock source.
+  *   This parameter can be one of the following values:
+  * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8
+  *   selected as SysTick clock source.
+  * @arg SysTick_CLKSource_HCLK: AHB clock selected as
+  *   SysTick clock source.
+  * @retval : None
+  */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+  if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+  {
+    SysTick->CTRL |= SysTick_CLKSource_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_adc.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_adc.c
new file mode 100644
index 0000000..caf94a2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_adc.c
@@ -0,0 +1,1321 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_adc.c
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file provides all the ADC firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_adc.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ADC ADON mask */
+#define CR2_ADON_Set               ((u32)0x00000001)
+#define CR2_ADON_Reset             ((u32)0xFFFFFFFE)
+
+/* ADC DMA mask */
+#define CR2_DMA_Set                ((u16)0x0100)
+#define CR2_DMA_Reset              ((u16)0xFEFF)
+
+/* ADC RSTCAL mask */
+#define CR2_RSTCAL_Set             ((u16)0x0008)
+
+/* ADC CAL mask */
+#define CR2_CAL_Set                ((u16)0x0004)
+
+/* ADC SWSTRT mask */
+#define CR2_SWSTRT_Set             ((u32)0x00400000)
+
+/* ADC DISCNUM mask */
+#define CR1_DISCNUM_Reset          ((u32)0xFFFF1FFF)
+
+/* ADC DISCEN mask */
+#define CR1_DISCEN_Set             ((u32)0x00000800)
+#define CR1_DISCEN_Reset           ((u32)0xFFFFF7FF)
+
+/* ADC EXTTRIG mask */
+#define CR2_EXTTRIG_Set            ((u32)0x00100000)
+#define CR2_EXTTRIG_Reset          ((u32)0xFFEFFFFF)
+
+/* ADC Software start mask */
+#define CR2_EXTTRIG_SWSTRT_Set     ((u32)0x00500000)
+#define CR2_EXTTRIG_SWSTRT_Reset   ((u32)0xFFAFFFFF)
+
+/* ADC JAUTO mask */
+#define CR1_JAUTO_Set              ((u32)0x00000400)
+#define CR1_JAUTO_Reset            ((u32)0xFFFFFBFF)
+
+/* ADC JDISCEN mask */
+#define CR1_JDISCEN_Set            ((u32)0x00001000)
+#define CR1_JDISCEN_Reset          ((u32)0xFFFFEFFF)
+
+/* ADC JEXTSEL mask */
+#define CR2_JEXTSEL_Reset          ((u32)0xFFFF8FFF)
+
+/* ADC JEXTTRIG mask */
+#define CR2_JEXTTRIG_Set           ((u32)0x00008000)
+#define CR2_JEXTTRIG_Reset         ((u32)0xFFFF7FFF)
+
+/* ADC JSWSTRT mask */
+#define CR2_JSWSTRT_Set            ((u32)0x00200000)
+
+/* ADC injected software start mask */
+#define CR2_JEXTTRIG_JSWSTRT_Set   ((u32)0x00208000)
+#define CR2_JEXTTRIG_JSWSTRT_Reset ((u32)0xFFDF7FFF)
+
+/* ADC AWDCH mask */
+#define CR1_AWDCH_Reset            ((u32)0xFFFFFFE0)
+
+/* ADC SQx mask */
+#define SQR3_SQ_Set                ((u8)0x1F)
+#define SQR2_SQ_Set                ((u8)0x1F)
+#define SQR1_SQ_Set                ((u8)0x1F)
+
+/* ADC JSQx mask */
+#define JSQR_JSQ_Set               ((u8)0x1F)
+
+/* ADC JL mask */
+#define JSQR_JL_Reset              ((u32)0xFFCFFFFF)
+
+/* ADC SMPx mask */
+#define SMPR1_SMP_Set              ((u8)0x07)
+#define SMPR2_SMP_Set              ((u8)0x07)
+
+/* ADC Analog watchdog enable mode mask */
+#define CR1_AWDMode_Reset          ((u32)0xFF3FFDFF)
+
+/* ADC TSPD mask */
+#define CR2_TSPD_Set               ((u32)0x00800000)
+#define CR2_TSPD_Reset             ((u32)0xFF7FFFFF)
+
+/* ADC JDRx registers= offset */
+#define JDR_Offset                 ((u8)0x28)
+
+/* ADC registers Masks */
+#define CR1_CLEAR_Mask             ((u32)0xFFF0FEFF)
+#define CR2_CLEAR_Mask             ((u32)0xFFF1F7FD)
+#define SQR1_CLEAR_Mask            ((u32)0xFF0FFFFF)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : ADC_DeInit
+* Description    : Deinitializes the ADCx peripheral registers to their default
+*                  reset values.
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_DeInit(ADC_TypeDef* ADCx)
+{
+  switch (*(u32*)&ADCx)
+  {
+    case ADC1_BASE:
+      /* Enable ADC1 reset state */
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
+      /* Release ADC1 from reset state */
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
+      break;
+    
+    case ADC2_BASE:
+      /* Enable ADC2 reset state */
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
+      /* Release ADC2 from reset state */
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);
+      break;
+
+    default:
+      break;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ADC_Init
+* Description    : Initializes the ADCx according to the specified parameters
+*                  in the ADC_InitStruct.
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - ADC_InitStruct: pointer to a ADC_InitTypeDef structure that
+*                    contains the configuration information for the specified
+*                    ADC peripheral.
+* Output         : None
+* Return         : None
+******************************************************************************/
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
+{
+  u32 tmpreg1 = 0;
+  u8 tmpreg2 = 0;
+
+  /* Check the parameters */
+  assert(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));
+  assert(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
+  assert(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));  		    
+  assert(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));   
+  assert(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); 
+  assert(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));
+
+  /*---------------------------- ADCx CR1 Configuration -----------------*/
+  /* Get the ADCx CR1 value */
+  tmpreg1 = ADCx->CR1;
+  /* Clear DUALMODE and SCAN bits */
+  tmpreg1 &= CR1_CLEAR_Mask;
+  /* Configure ADCx: Dual mode and scan conversion mode */
+  /* Set DUALMODE bits according to ADC_Mode value */
+  /* Set SCAN bit according to ADC_ScanConvMode value */
+  tmpreg1 |= (u32)(ADC_InitStruct->ADC_Mode | ((u32)ADC_InitStruct->ADC_ScanConvMode << 8));
+  /* Write to ADCx CR1 */
+  ADCx->CR1 = tmpreg1;
+
+  /*---------------------------- ADCx CR2 Configuration -----------------*/
+  /* Get the ADCx CR2 value */
+  tmpreg1 = ADCx->CR2;
+  /* Clear CONT, ALIGN and EXTTRIG bits */
+  tmpreg1 &= CR2_CLEAR_Mask;
+  /* Configure ADCx: external trigger event and continuous conversion mode */
+  /* Set ALIGN bit according to ADC_DataAlign value */
+  /* Set EXTTRIG bits according to ADC_ExternalTrigConv value */
+  /* Set CONT bit according to ADC_ContinuousConvMode value */
+  tmpreg1 |= (u32)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
+            ((u32)ADC_InitStruct->ADC_ContinuousConvMode << 1));
+  /* Write to ADCx CR2 */
+  ADCx->CR2 = tmpreg1;
+
+  /*---------------------------- ADCx SQR1 Configuration -----------------*/
+  /* Get the ADCx SQR1 value */
+  tmpreg1 = ADCx->SQR1;
+  /* Clear L bits */
+  tmpreg1 &= SQR1_CLEAR_Mask;
+  /* Configure ADCx: regular channel sequence length */
+  /* Set L bits according to ADC_NbrOfChannel value */
+  tmpreg2 |= (ADC_InitStruct->ADC_NbrOfChannel - 1);
+  tmpreg1 |= ((u32)tmpreg2 << 20);
+  /* Write to ADCx SQR1 */
+  ADCx->SQR1 = tmpreg1;
+}
+
+/*******************************************************************************
+* Function Name  : ADC_StructInit
+* Description    : Fills each ADC_InitStruct member with its default value.
+* Input          : ADC_InitStruct : pointer to a ADC_InitTypeDef structure
+*                  which will be initialized.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
+{
+  /* Reset ADC init structure parameters values */
+  /* Initialize the ADC_Mode member */
+  ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;
+
+  /* initialize the ADC_ScanConvMode member */
+  ADC_InitStruct->ADC_ScanConvMode = DISABLE;
+
+  /* Initialize the ADC_ContinuousConvMode member */
+  ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
+
+  /* Initialize the ADC_ExternalTrigConv member */
+  ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
+
+  /* Initialize the ADC_DataAlign member */
+  ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
+
+  /* Initialize the ADC_NbrOfChannel member */
+  ADC_InitStruct->ADC_NbrOfChannel = 1;
+}
+
+/*******************************************************************************
+* Function Name  : ADC_Cmd
+* Description    : Enables or disables the specified ADC peripheral.
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - NewState: new state of the ADCx peripheral. This parameter
+*                    can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the ADON bit to wake up the ADC from power down mode */
+    ADCx->CR2 |= CR2_ADON_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC peripheral */
+    ADCx->CR2 &= CR2_ADON_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ADC_DMACmd
+* Description    : Enables or disables the specified ADC DMA request.
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - NewState: new state of the selected ADC DMA transfer.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC DMA request */
+    ADCx->CR2 |= CR2_DMA_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC DMA request */
+    ADCx->CR2 &= CR2_DMA_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ADC_ITConfig
+* Description    : Enables or disables the specified ADC interrupts.
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - ADC_IT: specifies the ADC interrupts sources to be enabled
+*                    or disabled. 
+*                    This parameter can be any combination of the following values:
+*                       - ADC_IT_EOC: End of conversion interrupt mask
+*                       - ADC_IT_AWD: Analog watchdog interrupt mask
+*                       - ADC_IT_JEOC: End of injected conversion interrupt mask
+*                  - NewState: new state of the specified ADC interrupts.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState)
+{
+  u8 itmask = 0;
+
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+  assert(IS_ADC_IT(ADC_IT));
+
+  /* Get the ADC IT index */
+  itmask = (u8)ADC_IT;
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC interrupts */
+    ADCx->CR1 |= itmask;
+  }
+  else
+  {
+    /* Disable the selected ADC interrupts */
+    ADCx->CR1 &= (~(u32)itmask);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ADC_ResetCalibration
+* Description    : Resets the ADC calibration registers.
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_ResetCalibration(ADC_TypeDef* ADCx)
+{
+  /* Resets the selected ADC calibartion registers */  
+  ADCx->CR2 |= CR2_RSTCAL_Set;
+}
+
+/*******************************************************************************
+* Function Name  : ADC_GetResetCalibrationStatus
+* Description    : Gets the ADC reset calibration registers status.
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* Output         : None
+* Return         : The new state of ADC Reset Calibration registers (SET or RESET).
+*******************************************************************************/
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the status of RSTCAL bit */
+  if ((ADCx->CR2 & CR2_RSTCAL_Set) != (u16)RESET)
+  {
+    /* RSTCAL bit is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* RSTCAL bit is reset */
+    bitstatus = RESET;
+  }
+  /* Return the RSTCAL bit status */
+  return  bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : ADC_StartCalibration
+* Description    : Starts the calibration process.
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_StartCalibration(ADC_TypeDef* ADCx)
+{
+  /* Enable the selected ADC calibration process */  
+  ADCx->CR2 |= CR2_CAL_Set;
+}
+
+/*******************************************************************************
+* Function Name  : ADC_GetCalibrationStatus
+* Description    : Gets the ADC calibration status.
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* Output         : None
+* Return         : The new state of ADC calibration (SET or RESET).
+*******************************************************************************/
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the status of CAL bit */
+  if ((ADCx->CR2 & CR2_CAL_Set) != (u16)RESET)
+  {
+    /* CAL bit is set: calibration on going */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* CAL bit is reset: end of calibration */
+    bitstatus = RESET;
+  }
+  /* Return the CAL bit status */
+  return  bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : ADC_SoftwareStartConvCmd
+* Description    : Enables or disables the ADC software start conversion .
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - NewState: new state of the selected ADC software start conversion.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC conversion on external event */
+	/* Starts the selected ADC conversion */
+	ADCx->CR2 |= CR2_EXTTRIG_SWSTRT_Set;
+  }
+  else
+  {
+    /* Stops the selected ADC conversion */
+    /* Disable the selected ADC conversion on external event */
+	ADCx->CR2 &= CR2_EXTTRIG_SWSTRT_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ADC_GetSoftwareStartConvStatus
+* Description    : Gets the ADC Software start conversion Status.
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* Output         : None
+* Return         : The new state of ADC software start conversion (SET or RESET).
+*******************************************************************************/
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the status of SWSTRT bit */
+  if ((ADCx->CR2 & CR2_SWSTRT_Set) != (u32)RESET)
+  {
+    /* SWSTRT bit is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SWSTRT bit is reset */
+    bitstatus = RESET;
+  }
+  /* Return the SWSTRT bit status */
+  return  bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : ADC_DiscModeChannelCountConfig
+* Description    : Configures the discontinuous mode for the selected ADC regular
+*                  group channel.
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - Number: specifies the discontinuous mode regular channel
+*                    count value. This mumber must be between 1 and 8.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number)
+{
+  u32 tmpreg1 = 0;
+  u8 tmpreg2 = 0;
+
+  /* Check the parameters */
+  assert(IS_ADC_REGULAR_DISC_NUMBER(Number));
+
+  /* Get the old register value */
+  tmpreg1 = ADCx->CR1;
+  /* Clear the old discontinuous mode channel count */
+  tmpreg1 &= CR1_DISCNUM_Reset;
+  /* Set the discontinuous mode channel count */
+  tmpreg2 = Number - 1;
+  tmpreg1 |= ((u32)tmpreg2 << 13);
+  /* Store the new register value */
+  ADCx->CR1 = tmpreg1;
+}
+
+/*******************************************************************************
+* Function Name  : ADC_DiscModeCmd
+* Description    : Enables or disables the discontinuous mode on regular group
+*                  channel for the specified ADC
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - NewState: new state of the selected ADC discontinuous mode
+*                    on regular group channel.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC regular discontinuous mode */
+    ADCx->CR1 |= CR1_DISCEN_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC regular discontinuous mode */
+    ADCx->CR1 &= CR1_DISCEN_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ADC_RegularChannelConfig
+* Description    : Configures for the selected ADC regular channel its corresponding
+*                  rank in the sequencer and its sample time.
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - ADC_Channel: the ADC channel to configure. 
+*                    This parameter can be one of the following values:
+*                       - ADC_Channel_0: ADC Channel0 selected
+*                       - ADC_Channel_1: ADC Channel1 selected
+*                       - ADC_Channel_2: ADC Channel2 selected
+*                       - ADC_Channel_3: ADC Channel3 selected
+*                       - ADC_Channel_4: ADC Channel4 selected
+*                       - ADC_Channel_5: ADC Channel5 selected
+*                       - ADC_Channel_6: ADC Channel6 selected
+*                       - ADC_Channel_7: ADC Channel7 selected
+*                       - ADC_Channel_8: ADC Channel8 selected
+*                       - ADC_Channel_9: ADC Channel9 selected
+*                       - ADC_Channel_10: ADC Channel10 selected
+*                       - ADC_Channel_11: ADC Channel11 selected
+*                       - ADC_Channel_12: ADC Channel12 selected
+*                       - ADC_Channel_13: ADC Channel13 selected
+*                       - ADC_Channel_14: ADC Channel14 selected
+*                       - ADC_Channel_15: ADC Channel15 selected
+*                       - ADC_Channel_16: ADC Channel16 selected
+*                       - ADC_Channel_17: ADC Channel17 selected
+*                  - Rank: The rank in the regular group sequencer. This parameter
+*                    must be between 1 to 16.
+*                  - ADC_SampleTime: The sample time value to be set for the
+*                    selected channel. 
+*                    This parameter can be one of the following values:
+*                       - ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
+*                       - ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
+*                       - ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
+*                       - ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles	
+*                       - ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles	
+*                       - ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles	
+*                       - ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles	
+*                       - ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles	
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime)
+{
+  u32 tmpreg1 = 0, tmpreg2 = 0;
+
+  /* Check the parameters */
+  assert(IS_ADC_CHANNEL(ADC_Channel));
+  assert(IS_ADC_REGULAR_RANK(Rank));
+  assert(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+
+  /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
+  if (ADC_Channel > ADC_Channel_9)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR1;
+    /* Calculate the mask to clear */
+    tmpreg2 = (u32)SMPR1_SMP_Set << (3 * (ADC_Channel - 10));
+    /* Clear the old discontinuous mode channel count */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (u32)ADC_SampleTime << (3 * (ADC_Channel - 10));
+    /* Set the discontinuous mode channel count */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR1 = tmpreg1;
+  }
+  else /* ADC_Channel include in ADC_Channel_[0..9] */
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR2;
+    /* Calculate the mask to clear */
+    tmpreg2 = (u32)SMPR2_SMP_Set << (3 * ADC_Channel);
+    /* Clear the old discontinuous mode channel count */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel);
+    /* Set the discontinuous mode channel count */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR2 = tmpreg1;
+  }
+  /* For Rank 1 to 6 */
+  if (Rank < 7)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SQR3;
+    /* Calculate the mask to clear */
+    tmpreg2 = (u32)SQR3_SQ_Set << (5 * (Rank - 1));
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 1));
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SQR3 = tmpreg1;
+  }
+  /* For Rank 7 to 12 */
+  else if (Rank < 13)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SQR2;
+    /* Calculate the mask to clear */
+    tmpreg2 = (u32)SQR2_SQ_Set << (5 * (Rank - 7));
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 7));
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SQR2 = tmpreg1;
+  }
+  /* For Rank 13 to 16 */
+  else
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SQR1;
+    /* Calculate the mask to clear */
+    tmpreg2 = (u32)SQR1_SQ_Set << (5 * (Rank - 13));
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 13));
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SQR1 = tmpreg1;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ADC_ExternalTrigConvCmd
+* Description    : Enables or disables the ADCx conversion through external trigger.
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - NewState: new state of the selected ADC external trigger
+*                    start of conversion.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC conversion on external event */
+    ADCx->CR2 |= CR2_EXTTRIG_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC conversion on external event */
+    ADCx->CR2 &= CR2_EXTTRIG_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ADC_GetConversionValue
+* Description    : Returns the last ADC conversion result data for regular channel.
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* Output         : None
+* Return         : The Data conversion value.
+*******************************************************************************/
+u16 ADC_GetConversionValue(ADC_TypeDef* ADCx)
+{
+  /* Return the selected ADC conversion value */
+  return (u16) ADCx->DR;
+}
+
+/*******************************************************************************
+* Function Name  : ADC_GetDualModeConversionValue
+* Description    : Returns the last ADCs conversion result data in dual mode.
+* Output         : None
+* Return         : The Data conversion value.
+*******************************************************************************/
+u32 ADC_GetDualModeConversionValue(void)
+{
+  /* Return the dual mode conversion value */
+  return ADC1->DR;
+}
+
+/*******************************************************************************
+* Function Name  : ADC_AutoInjectedConvCmd
+* Description    : Enables or disables the automatic injected group conversion
+*                  after regular one.
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - NewState: new state of the selected ADC auto injected
+*                    conversion
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC automatic injected group conversion */
+    ADCx->CR1 |= CR1_JAUTO_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC automatic injected group conversion */
+    ADCx->CR1 &= CR1_JAUTO_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ADC_InjectedDiscModeCmd
+* Description    : Enables or disables the discontinuous mode for injected group
+*                  channel for the specified ADC
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - NewState: new state of the selected ADC discontinuous mode
+*                    on injected group channel.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC injected discontinuous mode */
+    ADCx->CR1 |= CR1_JDISCEN_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC injected discontinuous mode */
+    ADCx->CR1 &= CR1_JDISCEN_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ADC_ExternalTrigInjectedConvConfig
+* Description    : Configures the external trigger for injected channels conversion.
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - ADC_ExternalTrigInjecConv: specifies the ADC trigger to
+*                    start injected conversion. 
+*                    This parameter can be one of the following values:
+*                       - ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event 
+*                         selected
+*                       - ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture
+*                         compare4 selected
+*                       - ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event
+*                         selected
+*                       - ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture
+*                         compare1 selected
+*                       - ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture
+*                         compare4 selected
+*                       - ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event
+*                         selected 
+*                       - ADC_ExternalTrigInjecConv_Ext_Interrupt15: External
+*                         interrupt 15 event selected
+*                       - ADC_ExternalTrigInjecConv_None: Injected conversion
+*                         started by software and not by external trigger
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv)
+{
+  u32 tmpreg = 0;
+
+  /* Check the parameters */
+  assert(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
+
+  /* Get the old register value */
+  tmpreg = ADCx->CR2;
+  /* Clear the old external event selection for injected group */
+  tmpreg &= CR2_JEXTSEL_Reset;
+  /* Set the external event selection for injected group */
+  tmpreg |= ADC_ExternalTrigInjecConv;
+  /* Store the new register value */
+  ADCx->CR2 = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name  : ADC_ExternalTrigInjectedConvCmd
+* Description    : Enables or disables the ADCx injected channels conversion
+*                  through external trigger
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - NewState: new state of the selected ADC external trigger
+*                    start of injected conversion.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC external event selection for injected group */
+    ADCx->CR2 |= CR2_JEXTTRIG_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC external event selection for injected group */
+    ADCx->CR2 &= CR2_JEXTTRIG_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ADC_SoftwareStartInjectedConvCmd
+* Description    : Enables or disables the start of the injected channels conversion.
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - NewState: new state of the selected ADC software start
+*                    injected conversion.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC external event selection for injected group */
+    /* Starts the selected ADC injected conversion */
+    ADCx->CR2 |= CR2_JEXTTRIG_JSWSTRT_Set;
+  }
+  else
+  {
+    /* Stops the selected ADC injected conversion */
+    /* Disable the selected ADC external event selection for injected group */
+	ADCx->CR2 &= CR2_JEXTTRIG_JSWSTRT_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ADC_GetSoftwareStartInjectedConvCmdStatus
+* Description    : Gets the ADC Software start injected conversion Status.
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* Output         : None
+* Return         : The new state of ADC software start injected conversion (SET or RESET).
+*******************************************************************************/
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the status of JSWSTRT bit */
+  if ((ADCx->CR2 & CR2_JSWSTRT_Set) != (u32)RESET)
+  {
+    /* JSWSTRT bit is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* JSWSTRT bit is reset */
+    bitstatus = RESET;
+  }
+  /* Return the JSWSTRT bit status */
+  return  bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : ADC_InjectedChannelConfig
+* Description    : Configures for the selected ADC injected channel its corresponding
+*                  rank in the sequencer and its sample time.
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - ADC_Channel: the ADC channel to configure. 
+*                    This parameter can be one of the following values:
+*                       - ADC_Channel_0: ADC Channel0 selected
+*                       - ADC_Channel_1: ADC Channel1 selected
+*                       - ADC_Channel_2: ADC Channel2 selected
+*                       - ADC_Channel_3: ADC Channel3 selected
+*                       - ADC_Channel_4: ADC Channel4 selected
+*                       - ADC_Channel_5: ADC Channel5 selected
+*                       - ADC_Channel_6: ADC Channel6 selected
+*                       - ADC_Channel_7: ADC Channel7 selected
+*                       - ADC_Channel_8: ADC Channel8 selected
+*                       - ADC_Channel_9: ADC Channel9 selected
+*                       - ADC_Channel_10: ADC Channel10 selected
+*                       - ADC_Channel_11: ADC Channel11 selected
+*                       - ADC_Channel_12: ADC Channel12 selected
+*                       - ADC_Channel_13: ADC Channel13 selected
+*                       - ADC_Channel_14: ADC Channel14 selected
+*                       - ADC_Channel_15: ADC Channel15 selected
+*                       - ADC_Channel_16: ADC Channel16 selected
+*                       - ADC_Channel_17: ADC Channel17 selected
+*                  - Rank: The rank in the injected group sequencer. This parameter
+*                    must be between 1 to 4.
+*                  - ADC_SampleTime: The sample time value to be set for the
+*                    selected channel. 
+*                    This parameter can be one of the following values:
+*                       - ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
+*                       - ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
+*                       - ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
+*                       - ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles	
+*                       - ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles	
+*                       - ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles	
+*                       - ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles	
+*                       - ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles	
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime)
+{
+  u32 tmpreg1 = 0, tmpreg2 = 0;
+  u8 tmpreg3 = 0;
+
+  /* Check the parameters */
+  assert(IS_ADC_CHANNEL(ADC_Channel));
+  assert(IS_ADC_INJECTED_RANK(Rank));
+  assert(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+
+  /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
+  if (ADC_Channel > ADC_Channel_9)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR1;
+    /* Calculate the mask to clear */
+    tmpreg2 = (u32)SMPR1_SMP_Set << (3*(ADC_Channel - 10));
+    /* Clear the old discontinuous mode channel count */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (u32)ADC_SampleTime << (3*(ADC_Channel - 10));
+    /* Set the discontinuous mode channel count */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR1 = tmpreg1;
+  }
+  else /* ADC_Channel include in ADC_Channel_[0..9] */
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR2;
+    /* Calculate the mask to clear */
+    tmpreg2 = (u32)SMPR2_SMP_Set << (3 * ADC_Channel);
+    /* Clear the old discontinuous mode channel count */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel);
+    /* Set the discontinuous mode channel count */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR2 = tmpreg1;
+  }
+
+  /* Rank configuration */
+  /* Get the old register value */
+  tmpreg1 = ADCx->JSQR;
+  /* Get JL value: Number = JL+1 */
+  tmpreg3 =  (u8)((tmpreg1 & (u32)~JSQR_JL_Reset)>> 20);
+  /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
+  tmpreg2 = (u32)JSQR_JSQ_Set << (5 * ((Rank + 3) - (tmpreg3 + 1)));
+  /* Clear the old JSQx bits for the selected rank */
+  tmpreg1 &= ~tmpreg2;
+  /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
+  tmpreg2 = (u32)ADC_Channel << (5 * ((Rank + 3) - (tmpreg3 + 1)));
+  /* Set the JSQx bits for the selected rank */
+  tmpreg1 |= tmpreg2;
+  /* Store the new register value */
+  ADCx->JSQR = tmpreg1;
+}
+
+/*******************************************************************************
+* Function Name  : ADC_InjectedSequencerLengthConfig
+* Description    : Configures the sequencer for injected channels
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - Length: The sequencer length. 
+*                    This parameter must be a number between 1 to 4.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length)
+{
+  u32 tmpreg1 = 0;
+  u8 tmpreg2 = 0;
+
+  /* Check the parameters */
+  assert(IS_ADC_INJECTED_LENGTH(Length));
+  
+  /* Get the old register value */
+  tmpreg1 = ADCx->JSQR;
+  /* Clear the old injected sequnence lenght JL bits */
+  tmpreg1 &= JSQR_JL_Reset;
+  /* Set the injected sequnence lenght JL bits */
+  tmpreg2 = Length - 1; 
+  tmpreg1 |= (u32)tmpreg2 << 20;
+  /* Store the new register value */
+  ADCx->JSQR = tmpreg1;
+}
+
+/*******************************************************************************
+* Function Name  : ADC_SetInjectedOffset
+* Description    : Set the injected channels conversion value offset
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - ADC_InjectedChannel: the ADC injected channel to set its
+*                    offset. 
+*                    This parameter can be one of the following values:
+*                       - ADC_InjectedChannel_1: Injected Channel1 selected
+*                       - ADC_InjectedChannel_2: Injected Channel2 selected
+*                       - ADC_InjectedChannel_3: Injected Channel3 selected
+*                       - ADC_InjectedChannel_4: Injected Channel4 selected
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset)
+{
+  /* Check the parameters */
+  assert(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+  assert(IS_ADC_OFFSET(Offset));  
+
+  /* Set the selected injected channel data offset */
+  *((u32 *)((*(u32*)&ADCx) + ADC_InjectedChannel)) = (u32)Offset;
+}
+
+/*******************************************************************************
+* Function Name  : ADC_GetInjectedConversionValue
+* Description    : Returns the ADC conversion result data for the selected
+*                  injected channel
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - ADC_InjectedChannel: the converted ADC injected channel.
+*                    This parameter can be one of the following values:
+*                       - ADC_InjectedChannel_1: Injected Channel1 selected
+*                       - ADC_InjectedChannel_2: Injected Channel2 selected
+*                       - ADC_InjectedChannel_3: Injected Channel3 selected
+*                       - ADC_InjectedChannel_4: Injected Channel4 selected
+* Output         : None
+* Return         : The Data conversion value.
+*******************************************************************************/
+u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel)
+{
+  /* Check the parameters */
+  assert(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+
+  /* Returns the selected injected channel conversion data value */
+  return (u16) (*(u32*) (((*(u32*)&ADCx) + ADC_InjectedChannel + JDR_Offset)));
+}
+
+/*******************************************************************************
+* Function Name  : ADC_AnalogWatchdogCmd
+* Description    : Enables or disables the analog watchdog on single/all regular
+*                  or injected channels
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - ADC_AnalogWatchdog: the ADC analog watchdog configuration.
+*                    This parameter can be one of the following values:
+*                       - ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on
+*                         a single regular channel
+*                       - ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on
+*                         a single injected channel
+*                       - ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog 
+*                         watchdog on a single regular or injected channel
+*                       - ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on
+*                         all regular channel
+*                       - ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on
+*                         all injected channel
+*                       - ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog
+*                         on all regular and injected channels
+*                       - ADC_AnalogWatchdog_None: No channel guarded by the
+*                         analog watchdog
+* Output         : None
+* Return         : None	  
+*******************************************************************************/
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog)
+{
+  u32 tmpreg = 0;
+
+  /* Check the parameters */
+  assert(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
+
+  /* Get the old register value */
+  tmpreg = ADCx->CR1;
+  /* Clear AWDEN, AWDENJ and AWDSGL bits */
+  tmpreg &= CR1_AWDMode_Reset;
+  /* Set the analog watchdog enable mode */
+  tmpreg |= ADC_AnalogWatchdog;
+  /* Store the new register value */
+  ADCx->CR1 = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name  : ADC_AnalogWatchdogThresholdsConfig
+* Description    : Configures the High and low thresholds of the analog watchdog.
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - HighThreshold: the ADC analog watchdog High threshold value.
+*                    This parameter must be a 12bit value.
+*                  - LowThreshold: the ADC analog watchdog Low threshold value.
+*                    This parameter must be a 12bit value.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold,
+                                        u16 LowThreshold)
+{
+  /* Check the parameters */
+  assert(IS_ADC_THRESHOLD(HighThreshold));
+  assert(IS_ADC_THRESHOLD(LowThreshold));
+
+  /* Set the ADCx high threshold */
+  ADCx->HTR = HighThreshold;
+  /* Set the ADCx low threshold */
+  ADCx->LTR = LowThreshold;
+}
+
+/*******************************************************************************
+* Function Name  : ADC_AnalogWatchdogSingleChannelConfig
+* Description    : Configures the analog watchdog guarded single channel
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - ADC_Channel: the ADC channel to configure for the analog
+*                    watchdog. 
+*                    This parameter can be one of the following values:
+*                       - ADC_Channel_0: ADC Channel0 selected
+*                       - ADC_Channel_1: ADC Channel1 selected
+*                       - ADC_Channel_2: ADC Channel2 selected
+*                       - ADC_Channel_3: ADC Channel3 selected
+*                       - ADC_Channel_4: ADC Channel4 selected
+*                       - ADC_Channel_5: ADC Channel5 selected
+*                       - ADC_Channel_6: ADC Channel6 selected
+*                       - ADC_Channel_7: ADC Channel7 selected
+*                       - ADC_Channel_8: ADC Channel8 selected
+*                       - ADC_Channel_9: ADC Channel9 selected
+*                       - ADC_Channel_10: ADC Channel10 selected
+*                       - ADC_Channel_11: ADC Channel11 selected
+*                       - ADC_Channel_12: ADC Channel12 selected
+*                       - ADC_Channel_13: ADC Channel13 selected
+*                       - ADC_Channel_14: ADC Channel14 selected
+*                       - ADC_Channel_15: ADC Channel15 selected
+*                       - ADC_Channel_16: ADC Channel16 selected
+*                       - ADC_Channel_17: ADC Channel17 selected
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel)
+{
+  u32 tmpreg = 0;
+
+  /* Check the parameters */
+  assert(IS_ADC_CHANNEL(ADC_Channel));
+
+  /* Get the old register value */
+  tmpreg = ADCx->CR1;
+  /* Clear the Analog watchdog channel select bits */
+  tmpreg &= CR1_AWDCH_Reset;
+  /* Set the Analog watchdog channel */
+  tmpreg |= ADC_Channel;
+  /* Store the new register value */
+  ADCx->CR1 = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name  : ADC_TempSensorCmd
+* Description    : Enables or disables the temperature sensor.
+* Input          : - NewState: new state of the temperature sensor.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_TempSensorCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the temperature sensor  */
+    ADC1->CR2 |= CR2_TSPD_Set;
+  }
+  else
+  {
+    /* Disable the temperature sensor */
+	ADC1->CR2 &= CR2_TSPD_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ADC_GetFlagStatus
+* Description    : Checks whether the specified ADC flag is set or not.
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - ADC_FLAG: specifies the flag to check. 
+*                    This parameter can be one of the following values:
+*                       - ADC_FLAG_AWD: Analog watchdog flag
+*                       - ADC_FLAG_EOC: End of conversion flag
+*                       - ADC_FLAG_JEOC: End of injected group conversion flag
+*                       - ADC_FLAG_JSTRT: Start of injected group conversion flag
+*                       - ADC_FLAG_STRT: Start of regular group conversion flag
+* Output         : None
+* Return         : The new state of ADC_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert(IS_ADC_GET_FLAG(ADC_FLAG));
+
+  /* Check the status of the specified ADC flag */
+  if ((ADCx->SR & ADC_FLAG) != (u8)RESET)
+  {
+    /* ADC_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* ADC_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the ADC_FLAG status */
+  return  bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : ADC_ClearFlag
+* Description    : Clears the ADCx's pending flags.
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - ADC_FLAG: specifies the flag to clear. 
+*                    This parameter can be any combination of the following values:
+*                       - ADC_FLAG_AWD: Analog watchdog flag
+*                       - ADC_FLAG_EOC: End of conversion flag
+*                       - ADC_FLAG_JEOC: End of injected group conversion flag
+*                       - ADC_FLAG_JSTRT: Start of injected group conversion flag
+*                       - ADC_FLAG_STRT: Start of regular group conversion flag
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG)
+{
+  /* Check the parameters */
+  assert(IS_ADC_CLEAR_FLAG(ADC_FLAG));
+
+  /* Clear the selected ADC flags */
+  ADCx->SR &= ~(u32)ADC_FLAG;
+}
+
+/*******************************************************************************
+* Function Name  : ADC_GetITStatus
+* Description    : Checks whether the specified ADC interrupt has occurred or not.
+* Input          : - ADCx: where x can be 1 or 2 to select the ADC peripheral.
+*                  - ADC_IT: specifies the ADC interrupt source to check. 
+*                    This parameter can be one of the following values:
+*                       - ADC_IT_EOC: End of conversion interrupt mask
+*                       - ADC_IT_AWD: Analog watchdog interrupt mask
+*                       - ADC_IT_JEOC: End of injected conversion interrupt mask
+* Output         : None
+* Return         : The new state of ADC_IT (SET or RESET).
+*******************************************************************************/
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT)
+{
+  ITStatus bitstatus = RESET;
+  u8 itmask = 0, enablestatus;
+
+  /* Check the parameters */
+  assert(IS_ADC_GET_IT(ADC_IT));
+
+  /* Get the ADC IT index */
+  itmask = (u8)(ADC_IT >> 8);
+
+  /* Get the ADC_IT enable bit status */
+  enablestatus = (ADCx->CR1 & (u8)ADC_IT) ;
+
+  /* Check the status of the specified ADC interrupt */
+  if (((ADCx->SR & itmask) != (u8)RESET) && enablestatus)
+  {
+    /* ADC_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* ADC_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the ADC_IT status */
+  return  bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : ADC_ClearITPendingBit
+* Description    : Clears the ADC’s interrupt pending bits.
+* Input          : - ADC_IT: specifies the ADC interrupt pending bit to clear.
+*                    This parameter can be any combination of the following values:
+*                       - ADC_IT_EOC: End of conversion interrupt mask
+*                       - ADC_IT_AWD: Analog watchdog interrupt mask
+*                       - ADC_IT_JEOC: End of injected conversion interrupt mask
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT)
+{
+  u8 itmask = 0;
+
+  /* Check the parameters */
+  assert(IS_ADC_IT(ADC_IT));
+
+  /* Get the ADC IT index */
+  itmask = (u8)(ADC_IT >> 8);
+
+  /* Clear the selected ADC interrupt pending bits */
+  ADCx->SR &= ~(u32)itmask;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_bkp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_bkp.c
new file mode 100644
index 0000000..a8616e0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_bkp.c
@@ -0,0 +1,263 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_bkp.c
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file provides all the BKP firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_bkp.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ------------ BKP registers bit address in the alias region ----------- */
+#define BKP_OFFSET        (BKP_BASE - PERIPH_BASE)
+
+/* --- RTCCR Register ---*/
+/* Alias word address of CCO bit */
+#define RTCCR_OFFSET      (BKP_OFFSET + 0x2C)
+#define CCO_BitNumber     0x07
+#define RTCCR_CCO_BB      (PERIPH_BB_BASE + (RTCCR_OFFSET * 32) + (CCO_BitNumber * 4))
+
+/* --- CR Register ---*/
+/* Alias word address of TPAL bit */
+#define CR_OFFSET         (BKP_OFFSET + 0x30)
+#define TPAL_BitNumber    0x01
+#define CR_TPAL_BB        (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
+
+/* Alias word address of TPE bit */
+#define TPE_BitNumber     0x00
+#define CR_TPE_BB         (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+/* Alias word address of TPIE bit */
+#define CSR_OFFSET        (BKP_OFFSET + 0x34)
+#define TPIE_BitNumber    0x02
+#define CSR_TPIE_BB       (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
+
+/* Alias word address of TIF bit */
+#define TIF_BitNumber     0x09
+#define CSR_TIF_BB        (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
+
+/* Alias word address of TEF bit */
+#define TEF_BitNumber     0x08
+#define CSR_TEF_BB        (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
+
+
+/* ---------------------- BKP registers bit mask ------------------------ */
+/* RTCCR register bit mask */
+#define RTCCR_CAL_Mask    ((u16)0xFF80)
+
+/* CSR register bit mask */
+#define CSR_CTE_Set       ((u16)0x0001)
+#define CSR_CTI_Set       ((u16)0x0002)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : BKP_DeInit
+* Description    : Deinitializes the BKP peripheral registers to their default
+*                  reset values.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void BKP_DeInit(void)
+{
+  RCC_BackupResetCmd(ENABLE);
+  RCC_BackupResetCmd(DISABLE);
+}
+
+/*******************************************************************************
+* Function Name  : BKP_TamperPinLevelConfig
+* Description    : Configures the Tamper Pin active level.
+* Input          : - BKP_TamperPinLevel: specifies the Tamper Pin active level.
+*                    This parameter can be one of the following values:
+*                       - BKP_TamperPinLevel_High: Tamper pin active on high level
+*                       - BKP_TamperPinLevel_Low: Tamper pin active on low level
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel)
+{
+  /* Check the parameters */
+  assert(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
+
+  *(vu32 *) CR_TPAL_BB = BKP_TamperPinLevel;
+}
+
+/*******************************************************************************
+* Function Name  : BKP_TamperPinCmd
+* Description    : Enables or disables the Tamper Pin activation.
+* Input          : - NewState: new state of the Tamper Pin activation.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void BKP_TamperPinCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  *(vu32 *) CR_TPE_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name  : BKP_ITConfig
+* Description    : Enables or disables the Tamper Pin Interrupt.
+* Input          : - NewState: new state of the Tamper Pin Interrupt.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void BKP_ITConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  *(vu32 *) CSR_TPIE_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name  : BKP_RTCCalibrationClockOutputCmd
+* Description    : Enables or disables the output of the Calibration Clock.
+* Input          : - NewState: new state of the Calibration Clock output.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void BKP_RTCCalibrationClockOutputCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  *(vu32 *) RTCCR_CCO_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name  : BKP_SetRTCCalibrationValue
+* Description    : Sets RTC Clock Calibration value.
+* Input          : - CalibrationValue: specifies the RTC Clock Calibration value.
+*                    This parameter must be a number between 0 and 0x7F.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void BKP_SetRTCCalibrationValue(u8 CalibrationValue)
+{
+  u16 tmpreg = 0;
+
+  /* Check the parameters */
+  assert(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
+
+  tmpreg = BKP->RTCCR;
+
+  /* Clear CAL[6:0] bits */
+  tmpreg &= RTCCR_CAL_Mask;
+
+  /* Set CAL[6:0] bits according to CalibrationValue value */
+  tmpreg |= CalibrationValue;
+
+  /* Store the new value */
+  BKP->RTCCR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name  : BKP_WriteBackupRegister
+* Description    : Writes user data to the specified Data Backup Register.
+* Input          : - BKP_DR: specifies the Data Backup Register.
+*                    This parameter can be BKP_DRx where x:[1, 10]
+*                  - Data: data to write
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data)
+{
+  /* Check the parameters */
+  assert(IS_BKP_DR(BKP_DR));
+
+  *(vu16 *) (BKP_BASE + BKP_DR) = Data;
+}
+
+/*******************************************************************************
+* Function Name  : BKP_ReadBackupRegister
+* Description    : Reads data from the specified Data Backup Register.
+* Input          : - BKP_DR: specifies the Data Backup Register.
+*                    This parameter can be BKP_DRx where x:[1, 10]
+* Output         : None
+* Return         : The content of the specified Data Backup Register
+*******************************************************************************/
+u16 BKP_ReadBackupRegister(u16 BKP_DR)
+{
+  /* Check the parameters */
+  assert(IS_BKP_DR(BKP_DR));
+
+  return (*(vu16 *) (BKP_BASE + BKP_DR));
+}
+
+/*******************************************************************************
+* Function Name  : BKP_GetFlagStatus
+* Description    : Checks whether the Tamper Pin Event flag is set or not.
+* Input          : None
+* Output         : None
+* Return         : The new state of the Tamper Pin Event flag (SET or RESET).
+*******************************************************************************/
+FlagStatus BKP_GetFlagStatus(void)
+{
+  return (FlagStatus)(*(vu32 *) CSR_TEF_BB);
+}
+
+/*******************************************************************************
+* Function Name  : BKP_ClearFlag
+* Description    : Clears Tamper Pin Event pending flag.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void BKP_ClearFlag(void)
+{
+  /* Set CTE bit to clear Tamper Pin Event flag */
+  BKP->CSR |= CSR_CTE_Set;
+}
+
+/*******************************************************************************
+* Function Name  : BKP_GetITStatus
+* Description    : Checks whether the Tamper Pin Interrupt has occurred or not.
+* Input          : None
+* Output         : None
+* Return         : The new state of the Tamper Pin Interrupt (SET or RESET).
+*******************************************************************************/
+ITStatus BKP_GetITStatus(void)
+{
+  return (ITStatus)(*(vu32 *) CSR_TIF_BB);
+}
+
+/*******************************************************************************
+* Function Name  : BKP_ClearITPendingBit
+* Description    : Clears Tamper Pin Interrupt pending bit.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void BKP_ClearITPendingBit(void)
+{
+  /* Set CTI bit to clear Tamper Pin Interrupt pending bit */
+  BKP->CSR |= CSR_CTI_Set;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_can.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_can.c
new file mode 100644
index 0000000..3457f0d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_can.c
@@ -0,0 +1,873 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_can.c
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file provides all the CAN firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_can.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+
+/* Private define ------------------------------------------------------------*/
+/* CAN Master Control Register bits */
+#define CAN_MCR_INRQ     ((u32)0x00000001) /* Initialization request */
+#define CAN_MCR_SLEEP    ((u32)0x00000002) /* Sleep mode request */
+#define CAN_MCR_TXFP     ((u32)0x00000004) /* Transmit FIFO priority */
+#define CAN_MCR_RFLM     ((u32)0x00000008) /* Receive FIFO locked mode */
+#define CAN_MCR_NART     ((u32)0x00000010) /* No automatic retransmission */
+#define CAN_MCR_AWUM     ((u32)0x00000020) /* Automatic wake up mode */
+#define CAN_MCR_ABOM     ((u32)0x00000040) /* Automatic bus-off management */
+#define CAN_MCR_TTCM     ((u32)0x00000080) /* time triggered communication */
+
+/* CAN Master Status Register bits */
+#define CAN_MSR_INAK     ((u32)0x00000001)    /* Initialization acknowledge */
+#define CAN_MSR_WKUI     ((u32)0x00000008)    /* Wake-up interrupt */
+#define CAN_MSR_SLAKI    ((u32)0x00000010)    /* Sleep acknowledge interrupt */
+
+/* CAN Transmit Status Register bits */
+#define CAN_TSR_RQCP0    ((u32)0x00000001)    /* Request completed mailbox0 */
+#define CAN_TSR_TXOK0    ((u32)0x00000002)    /* Transmission OK of mailbox0 */
+#define CAN_TSR_ABRQ0    ((u32)0x00000080)    /* Abort request for mailbox0 */
+#define CAN_TSR_RQCP1    ((u32)0x00000100)    /* Request completed mailbox1 */
+#define CAN_TSR_TXOK1    ((u32)0x00000200)    /* Transmission OK of mailbox1 */
+#define CAN_TSR_ABRQ1    ((u32)0x00008000)    /* Abort request for mailbox1 */
+#define CAN_TSR_RQCP2    ((u32)0x00010000)    /* Request completed mailbox2 */
+#define CAN_TSR_TXOK2    ((u32)0x00020000)    /* Transmission OK of mailbox2 */
+#define CAN_TSR_ABRQ2    ((u32)0x00800000)    /* Abort request for mailbox2 */
+#define CAN_TSR_TME0     ((u32)0x04000000)    /* Transmit mailbox 0 empty */
+#define CAN_TSR_TME1     ((u32)0x08000000)    /* Transmit mailbox 1 empty */
+#define CAN_TSR_TME2     ((u32)0x10000000)    /* Transmit mailbox 2 empty */
+
+/* CAN Receive FIFO 0 Register bits */
+#define CAN_RF0R_FULL0   ((u32)0x00000008)    /* FIFO 0 full */
+#define CAN_RF0R_FOVR0   ((u32)0x00000010)    /* FIFO 0 overrun */
+#define CAN_RF0R_RFOM0   ((u32)0x00000020)    /* Release FIFO 0 output mailbox */
+
+/* CAN Receive FIFO 1 Register bits */
+#define CAN_RF1R_FULL1   ((u32)0x00000008)    /* FIFO 1 full */
+#define CAN_RF1R_FOVR1   ((u32)0x00000010)    /* FIFO 1 overrun */
+#define CAN_RF1R_RFOM1   ((u32)0x00000020)    /* Release FIFO 1 output mailbox */
+
+/* CAN Error Status Register bits */
+#define CAN_ESR_EWGF     ((u32)0x00000001)    /* Error warning flag */
+#define CAN_ESR_EPVF     ((u32)0x00000002)    /* Error passive flag */
+#define CAN_ESR_BOFF     ((u32)0x00000004)    /* Bus-off flag */
+
+/* CAN Mailbox Transmit Request */
+#define CAN_TMIDxR_TXRQ    ((u32)0x00000001) /* Transmit mailbox request */
+
+/* CAN Filter Master Register bits */
+#define CAN_FMR_FINIT ((u32)0x00000001) /* Filter init mode */
+
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static ITStatus CheckITStatus(u32 CAN_Reg, u32 It_Bit);
+
+/* Private functions ---------------------------------------------------------*/
+/*******************************************************************************
+* Function Name  : CAN_DeInit
+* Description    : Deinitializes the CAN peripheral registers to their default
+*                  reset values.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CAN_DeInit(void)
+{
+  /* Enable CAN reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, ENABLE);
+  /* Release CAN from reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, DISABLE);
+}
+
+/*******************************************************************************
+* Function Name  : CAN_Init
+* Description    : Initializes the CAN peripheral according to the specified
+*                  parameters in the CAN_InitStruct.
+* Input          : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
+                   contains the configuration information for the CAN peripheral.
+* Output         : None.
+* Return         : Constant indicates initialization succeed which will be 
+*                  CANINITFAILED or CANINITOK.
+*******************************************************************************/
+u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct)
+{
+  u8 InitStatus = 0;
+
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
+  assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
+  assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
+  assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
+  assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
+  assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
+  assert(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
+  assert(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
+  assert(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
+  assert(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
+  assert(IS_CAN_CLOCK(CAN_InitStruct->CAN_Clock));
+  assert(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
+
+  /* Request initialisation */
+  CAN->MCR = CAN_MCR_INRQ;
+
+  /* ...and check acknowledged */
+  if ((CAN->MSR & CAN_MSR_INAK) == 0)
+  {
+    InitStatus = CANINITFAILED;
+  }
+  else
+  {
+    /* Set the time triggered communication mode */
+    if (CAN_InitStruct->CAN_TTCM == ENABLE)
+    {
+      CAN->MCR |= CAN_MCR_TTCM;
+    }
+    else
+    {
+      CAN->MCR &= ~CAN_MCR_TTCM;
+    }
+
+    /* Set the automatic bus-off management */
+    if (CAN_InitStruct->CAN_ABOM == ENABLE)
+    {
+      CAN->MCR |= CAN_MCR_ABOM;
+    }
+    else
+    {
+      CAN->MCR &= ~CAN_MCR_ABOM;
+    }
+
+    /* Set the automatic wake-up mode */
+    if (CAN_InitStruct->CAN_AWUM == ENABLE)
+    {
+      CAN->MCR |= CAN_MCR_AWUM;
+    }
+    else
+    {
+      CAN->MCR &= ~CAN_MCR_AWUM;
+    }
+
+    /* Set the no automatic retransmission */
+    if (CAN_InitStruct->CAN_NART == ENABLE)
+    {
+      CAN->MCR |= CAN_MCR_NART;
+    }
+    else
+    {
+      CAN->MCR &= ~CAN_MCR_NART;
+    }
+
+    /* Set the receive FIFO locked mode */
+    if (CAN_InitStruct->CAN_RFLM == ENABLE)
+    {
+      CAN->MCR |= CAN_MCR_RFLM;
+    }
+    else
+    {
+      CAN->MCR &= ~CAN_MCR_RFLM;
+    }
+
+    /* Set the transmit FIFO priority */
+    if (CAN_InitStruct->CAN_TXFP == ENABLE)
+    {
+      CAN->MCR |= CAN_MCR_TXFP;
+    }
+    else
+    {
+      CAN->MCR &= ~CAN_MCR_TXFP;
+    }
+
+    /* Set the bit timing register */
+    CAN->BTR = (u32)((u32)CAN_InitStruct->CAN_Mode << 30) | ((u32)CAN_InitStruct->CAN_SJW << 24) |
+               ((u32)CAN_InitStruct->CAN_BS1 << 16) | ((u32)CAN_InitStruct->CAN_BS2 << 20) |
+               ((u32)CAN_InitStruct->CAN_Clock << 15) | ((u32)CAN_InitStruct->CAN_Prescaler - 1);
+
+    InitStatus = CANINITOK;
+
+    /* Request leave initialisation */
+    CAN->MCR &= ~CAN_MCR_INRQ;
+
+    /* ...and check acknowledged */
+    if ((CAN->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+    {
+      InitStatus = CANINITFAILED;
+    }
+  }
+
+  /* At this step, return the status of initialization */
+  return InitStatus;
+}
+
+/*******************************************************************************
+* Function Name  : CAN_FilterInit
+* Description    : Initializes the CAN peripheral according to the specified
+*                  parameters in the CAN_FilterInitStruct.
+* Input          : CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef
+*                  structure that contains the configuration information.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
+{
+  u16 FilterNumber_BitPos = 0;
+
+  /* Check the parameters */
+  assert(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
+  assert(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
+  assert(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
+  assert(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
+  assert(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
+
+  FilterNumber_BitPos = (u16)((u16)0x0001 << ((u16)CAN_FilterInitStruct->CAN_FilterNumber));
+
+  /* Initialisation mode for the filter */
+  CAN->FMR |= CAN_FMR_FINIT;
+
+  /* Filter Deactivation */
+  CAN->FA0R &= ~(u32)FilterNumber_BitPos;
+
+  /* Filter Scale */
+  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
+  {
+    /* 16-bit scale for the filter */
+    CAN->FS0R &= ~(u32)FilterNumber_BitPos;
+
+    /* First 16-bit identifier and First 16-bit mask */
+    /* Or First 16-bit identifier and Second 16-bit identifier */
+    CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR0 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
+        ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdLow);
+
+    /* Second 16-bit identifier and Second 16-bit mask */
+    /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+    CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+        ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdHigh);
+  }
+  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
+  {
+    /* 32-bit scale for the filter */
+    CAN->FS0R |= FilterNumber_BitPos;
+
+    /* 32-bit identifier or First 32-bit identifier */
+    CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR0 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
+        ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdLow);
+
+    /* 32-bit mask or Second 32-bit identifier */
+    CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+        ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdLow);
+
+  }
+
+  /* Filter Mode */
+  if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
+  {
+    /*Id/Mask mode for the filter*/
+    CAN->FM0R &= ~(u32)FilterNumber_BitPos;
+  }
+  else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+  {
+    /*Identifier list mode for the filter*/
+    CAN->FM0R |= (u32)FilterNumber_BitPos;
+  }
+
+  /* Filter FIFO assignment */
+  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0)
+  {
+    /* FIFO 0 assignation for the filter */
+    CAN->FFA0R &= ~(u32)FilterNumber_BitPos;
+  }
+  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1)
+  {
+    /* FIFO 1 assignation for the filter */
+    CAN->FFA0R |= (u32)FilterNumber_BitPos;
+  }
+  
+  /* Filter activation */
+  if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
+  {
+    CAN->FA0R |= FilterNumber_BitPos;
+  }
+
+  /* Leave the initialisation mode for the filter */
+  CAN->FMR &= ~CAN_FMR_FINIT;
+}
+
+/*******************************************************************************
+* Function Name  : CAN_StructInit
+* Description    : Fills each CAN_InitStruct member with its default value.
+* Input          : CAN_InitStruct: pointer to a CAN_InitTypeDef structure which
+*                  will be initialized.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
+{
+  /* Reset CAN init structure parameters values */
+
+  /* Initialize the time triggered communication mode */
+  CAN_InitStruct->CAN_TTCM = DISABLE;
+
+  /* Initialize the automatic bus-off management */
+  CAN_InitStruct->CAN_ABOM = DISABLE;
+
+  /* Initialize the automatic wake-up mode */
+  CAN_InitStruct->CAN_AWUM = DISABLE;
+
+  /* Initialize the no automatic retransmission */
+  CAN_InitStruct->CAN_NART = DISABLE;
+
+  /* Initialize the receive FIFO locked mode */
+  CAN_InitStruct->CAN_RFLM = DISABLE;
+
+  /* Initialize the transmit FIFO priority */
+  CAN_InitStruct->CAN_TXFP = DISABLE;
+
+  /* Initialize the CAN_Mode member */
+  CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
+
+  /* Initialize the CAN_SJW member */
+  CAN_InitStruct->CAN_SJW = CAN_SJW_0tq;
+
+  /* Initialize the CAN_BS1 member */
+  CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
+
+  /* Initialize the CAN_BS2 member */
+  CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
+
+  /* Initialize the CAN_Clock member */
+  CAN_InitStruct->CAN_Clock = CAN_Clock_APB;
+
+  /* Initialize the CAN_Prescaler member */
+  CAN_InitStruct->CAN_Prescaler = 1;
+}
+
+/*******************************************************************************
+* Function Name  : CAN_ITConfig
+* Description    : Enables or disables the CAN interrupts.
+* Input          : - CAN_IT: specifies the CAN interrupt sources to be enabled or
+*                    disabled.
+*                  - NewState: new state of the CAN interrupts.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CAN_ITConfig(u32 CAN_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_CAN_IT(CAN_IT));
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected CAN interrupt */
+    CAN->IER |= CAN_IT;
+  }
+  else
+  {
+    /* Disable the selected CAN interrupt */
+    CAN->IER &= ~CAN_IT;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : CAN_Transmit
+* Description    : Initiates the transmission of a message.
+* Input          : TxMessage: pointer to a structure which contains CAN Id, CAN
+*                  DLC and CAN datas.
+* Output         : None.
+* Return         : The number of the mailbox that is used for transmission
+*                  or CAN_NO_MB if there is no empty mailbox.
+*******************************************************************************/
+u8 CAN_Transmit(CanTxMsg* TxMessage)
+{
+  u8 TransmitMailbox = 0;
+
+  /* Check the parameters */
+  assert(IS_CAN_STDID(TxMessage->StdId));
+  assert(IS_CAN_EXTID(TxMessage->StdId));
+  assert(IS_CAN_IDTYPE(TxMessage->IDE));
+  assert(IS_CAN_RTR(TxMessage->RTR));
+  assert(IS_CAN_DLC(TxMessage->DLC));
+
+  /* Select one empty transmit mailbox */
+  if ((CAN->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+  {
+    TransmitMailbox = 0;
+  }
+  else if ((CAN->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+  {
+    TransmitMailbox = 1;
+  }
+  else if ((CAN->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
+  {
+    TransmitMailbox = 2;
+  }
+  else
+  {
+    TransmitMailbox = CAN_NO_MB;
+  }
+
+  if (TransmitMailbox != CAN_NO_MB)
+  {
+    /* Set up the Id */
+    TxMessage->StdId &= (u32)0x000007FF;
+    TxMessage->StdId = TxMessage->StdId << 21;
+    TxMessage->ExtId &= (u32)0x0003FFFF;
+    TxMessage->ExtId <<= 3;
+
+    CAN->sTxMailBox[TransmitMailbox].TIR &= CAN_TMIDxR_TXRQ;
+    CAN->sTxMailBox[TransmitMailbox].TIR |= (TxMessage->StdId | TxMessage->ExtId |
+                                            TxMessage->IDE | TxMessage->RTR);
+
+    /* Set up the DLC */
+    TxMessage->DLC &= (u8)0x0000000F;
+    CAN->sTxMailBox[TransmitMailbox].TDTR &= (u32)0xFFFFFFF0;
+    CAN->sTxMailBox[TransmitMailbox].TDTR |= TxMessage->DLC;
+
+    /* Set up the data field */
+    CAN->sTxMailBox[TransmitMailbox].TDLR = (((u32)TxMessage->Data[3] << 24) | ((u32)TxMessage->Data[2] << 16) |
+                                            ((u32)TxMessage->Data[1] << 8) | ((u32)TxMessage->Data[0]));
+    CAN->sTxMailBox[TransmitMailbox].TDHR = (((u32)TxMessage->Data[7] << 24) | ((u32)TxMessage->Data[6] << 16) |
+                                            ((u32)TxMessage->Data[5] << 8) | ((u32)TxMessage->Data[4]));
+
+    /* Request transmission */
+    CAN->sTxMailBox[TransmitMailbox].TIR |= CAN_TMIDxR_TXRQ;
+  }
+
+  return TransmitMailbox;
+}
+
+/*******************************************************************************
+* Function Name  : CAN_TransmitStatus
+* Description    : Check the transmission of a message.
+* Input          : TransmitMailbox: the number of the mailbox that is used for
+*                  transmission.
+* Output         : None.
+* Return         : CANTXOK if the CAN driver transmits the message, CANTXFAILED
+*                  in an other case.
+*******************************************************************************/
+u32 CAN_TransmitStatus(u8 TransmitMailbox)
+{
+  /* RQCP, TXOK and TME bits */
+  u32 State = 0;
+
+  /* Check the parameters */
+  assert(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
+
+  switch (TransmitMailbox)
+  {
+    case (0): State |= ((CAN->TSR & CAN_TSR_RQCP0) << 2);
+      State |= ((CAN->TSR & CAN_TSR_TXOK0) >> 0);
+      State |= ((CAN->TSR & CAN_TSR_TME0) >> 26);
+      break;
+    case (1): State |= ((CAN->TSR & CAN_TSR_RQCP1) >> 6);
+      State |= ((CAN->TSR & CAN_TSR_TXOK1) >> 8);
+      State |= ((CAN->TSR & CAN_TSR_TME1) >> 27);
+      break;
+    case (2): State |= ((CAN->TSR & CAN_TSR_RQCP2) >> 14);
+      State |= ((CAN->TSR & CAN_TSR_TXOK2) >> 16);
+      State |= ((CAN->TSR & CAN_TSR_TME2) >> 28);
+      break;
+    default:
+      State = CANTXFAILED;
+      break;
+  }
+
+  switch (State)
+  {
+      /* transmit pending  */
+    case (0x0): State = CANTXPENDING;
+      break;
+      /* transmit failed  */
+    case (0x5): State = CANTXFAILED;
+      break;
+      /* transmit succedeed  */
+    case (0x7): State = CANTXOK;
+      break;
+    default:
+      State = CANTXFAILED;
+      break;
+  }
+
+  return State;
+}
+
+/*******************************************************************************
+* Function Name  : CAN_CancelTransmit
+* Description    : Cancels a transmit request.
+* Input          : Mailbox number.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CAN_CancelTransmit(u8 Mailbox)
+{
+  /* Check the parameters */
+  assert(IS_CAN_TRANSMITMAILBOX(Mailbox));
+
+  /* abort transmission */
+  switch (Mailbox)
+  {
+    case (0): CAN->TSR |= CAN_TSR_ABRQ0;
+      break;
+    case (1): CAN->TSR |= CAN_TSR_ABRQ1;
+      break;
+    case (2): CAN->TSR |= CAN_TSR_ABRQ2;
+      break;
+    default:
+      break;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : CAN_FIFORelease
+* Description    : Release a FIFO.
+* Input          : FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CAN_FIFORelease(u8 FIFONumber)
+{
+  /* Check the parameters */
+  assert(IS_CAN_FIFO(FIFONumber));
+
+  /* Release FIFO0 */
+  if (FIFONumber == CAN_FIFO0)
+  {
+    CAN->RF0R = CAN_RF0R_RFOM0;
+  }
+  /* Release FIFO1 */
+  else /* FIFONumber == CAN_FIFO1 */
+  {
+    CAN->RF1R = CAN_RF1R_RFOM1;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : CAN_MessagePending
+* Description    : Return the number of pending messages.
+* Input          : FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+* Output         : None.
+* Return         : NbMessage which is the number of pending message.
+*******************************************************************************/
+u8 CAN_MessagePending(u8 FIFONumber)
+{
+  u8 MessagePending=0;
+
+  /* Check the parameters */
+  assert(IS_CAN_FIFO(FIFONumber));
+
+  if (FIFONumber == CAN_FIFO0)
+  {
+    MessagePending = (u8)(CAN->RF0R&(u32)0x03);
+  }
+  else if (FIFONumber == CAN_FIFO1)
+  {
+    MessagePending = (u8)(CAN->RF1R&(u32)0x03);
+  }
+  else
+  {
+    MessagePending = 0;
+  }
+  return MessagePending;
+}
+
+/*******************************************************************************
+* Function Name  : CAN_Receive
+* Description    : Receives a message.
+* Input          : FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+* Output         : RxMessage: pointer to a structure which contains CAN Id,
+*                  CAN DLC, CAN datas and FMI number.
+* Return         : None.
+*******************************************************************************/
+void CAN_Receive(u8 FIFONumber, CanRxMsg* RxMessage)
+{
+  /* Check the parameters */
+  assert(IS_CAN_FIFO(FIFONumber));
+
+  /* Get the Id */
+  RxMessage->StdId = (u32)0x000007FF & (CAN->sFIFOMailBox[FIFONumber].RIR >> 21);
+  RxMessage->ExtId = (u32)0x0003FFFF & (CAN->sFIFOMailBox[FIFONumber].RIR >> 3);
+
+  RxMessage->IDE = (u32)0x00000004 & CAN->sFIFOMailBox[FIFONumber].RIR;
+  RxMessage->RTR = (u32)0x00000002 & CAN->sFIFOMailBox[FIFONumber].RIR;
+
+  /* Get the DLC */
+  RxMessage->DLC = (u32)0x0000000F & CAN->sFIFOMailBox[FIFONumber].RDTR;
+
+  /* Get the FMI */
+  RxMessage->FMI = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDTR >> 8);
+
+  /* Get the data field */
+  RxMessage->Data[0] = (u32)0x000000FF & CAN->sFIFOMailBox[FIFONumber].RDLR;
+  RxMessage->Data[1] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 8);
+  RxMessage->Data[2] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 16);
+  RxMessage->Data[3] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 24);
+
+  RxMessage->Data[4] = (u32)0x000000FF & CAN->sFIFOMailBox[FIFONumber].RDHR;
+  RxMessage->Data[5] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 8);
+  RxMessage->Data[6] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 16);
+  RxMessage->Data[7] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 24);
+
+  /* Release the FIFO */
+  CAN_FIFORelease(FIFONumber);
+}
+
+/*******************************************************************************
+* Function Name  : CAN_Sleep
+* Description    : Enters the low power mode.
+* Input          : None.
+* Output         : None.
+* Return         : CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case.
+*******************************************************************************/
+u8 CAN_Sleep(void)
+{
+  u8 SleepStatus = 0;
+
+  /* Sleep mode entering request */
+  CAN->MCR |= CAN_MCR_SLEEP;
+  SleepStatus = CANSLEEPOK;
+
+  /* Sleep mode status */
+  if ((CAN->MCR&CAN_MCR_SLEEP) == 0)
+  {
+    /* Sleep mode not entered */
+    SleepStatus = CANSLEEPFAILED;
+  }
+
+  /* At this step, sleep mode status */
+  return SleepStatus;
+}
+
+/*******************************************************************************
+* Function Name  : CAN_WakeUp
+* Description    : Wakes the CAN up.
+* Input          : None.
+* Output         : None.
+* Return         : CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other
+*                  case.
+*******************************************************************************/
+u8 CAN_WakeUp(void)
+{
+  u8 WakeUpStatus = 0;
+
+  /* Wake up request */
+  CAN->MCR &= ~CAN_MCR_SLEEP;
+  WakeUpStatus = CANWAKEUPFAILED;
+
+  /* Sleep mode status */
+  if ((CAN->MCR&CAN_MCR_SLEEP) == 0)
+  {
+    /* Sleep mode exited */
+    WakeUpStatus = CANWAKEUPOK;
+  }
+
+  /* At this step, sleep mode status */
+  return WakeUpStatus;
+}
+
+/*******************************************************************************
+* Function Name  : CAN_GetFlagStatus
+* Description    : Checks whether the CAN flag is set or not.
+* Input          : CAN_FLAG: specifies the flag to check.
+* Output         : None.
+* Return         : The new state of CAN_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus CAN_GetFlagStatus(u32 CAN_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert(IS_CAN_FLAG(CAN_FLAG));
+
+  /* Check the status of the specified CAN flag */
+  if ((CAN->ESR & CAN_FLAG) != (u32)RESET)
+  {
+    /* CAN_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* CAN_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the CAN_FLAG status */
+  return  bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : CAN_ClearFlag
+* Description    : Clears the CAN's pending flags.
+* Input          : CAN_FLAG: specifies the flag to clear.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CAN_ClearFlag(u32 CAN_FLAG)
+{
+  /* Check the parameters */
+  assert(IS_CAN_FLAG(CAN_FLAG));
+
+  /* Clear the selected CAN flags */
+  CAN->ESR &= ~CAN_FLAG;
+}
+
+/*******************************************************************************
+* Function Name  : CAN_GetITStatus
+* Description    : Checks whether the CAN interrupt has occurred or not.
+* Input          : CAN_IT: specifies the CAN interrupt source to check.
+* Output         : None.
+* Return         : The new state of CAN_IT (SET or RESET).
+*******************************************************************************/
+ITStatus CAN_GetITStatus(u32 CAN_IT)
+{
+  ITStatus pendingbitstatus = RESET;
+
+  /* Check the parameters */
+  assert(IS_CAN_IT(CAN_IT));
+
+  switch (CAN_IT)
+  {
+    case CAN_IT_RQCP0:
+      pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP0);
+      break;
+    case CAN_IT_RQCP1:
+      pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP1);
+      break;
+    case CAN_IT_RQCP2:
+      pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP2);
+      break;
+    case CAN_IT_FF0:
+      pendingbitstatus = CheckITStatus(CAN->RF0R, CAN_RF0R_FULL0);
+      break;
+    case CAN_IT_FOV0:
+      pendingbitstatus = CheckITStatus(CAN->RF0R, CAN_RF0R_FOVR0);
+      break;
+    case CAN_IT_FF1:
+      pendingbitstatus = CheckITStatus(CAN->RF1R, CAN_RF1R_FULL1);
+      break;
+    case CAN_IT_FOV1:
+      pendingbitstatus = CheckITStatus(CAN->RF1R, CAN_RF1R_FOVR1);
+      break;
+    case CAN_IT_EWG:
+      pendingbitstatus = CheckITStatus(CAN->ESR, CAN_ESR_EWGF);
+      break;
+    case CAN_IT_EPV:
+      pendingbitstatus = CheckITStatus(CAN->ESR, CAN_ESR_EPVF);
+      break;
+    case CAN_IT_BOF:
+      pendingbitstatus = CheckITStatus(CAN->ESR, CAN_ESR_BOFF);
+      break;
+    case CAN_IT_SLK:
+      pendingbitstatus = CheckITStatus(CAN->MSR, CAN_MSR_SLAKI);
+      break;
+    case CAN_IT_WKU:
+      pendingbitstatus = CheckITStatus(CAN->MSR, CAN_MSR_WKUI);
+      break;
+
+    default :
+      pendingbitstatus = RESET;
+      break;
+  }
+
+  /* Return the CAN_IT status */
+  return  pendingbitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : CAN_ClearITPendingBit
+* Description    : Clears the CAN’s interrupt pending bits.
+* Input          : CAN_IT: specifies the interrupt pending bit to clear.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CAN_ClearITPendingBit(u32 CAN_IT)
+{
+  /* Check the parameters */
+  assert(IS_CAN_IT(CAN_IT));
+
+  switch (CAN_IT)
+  {
+    case CAN_IT_RQCP0:
+      CAN->TSR = CAN_TSR_RQCP0; /* rc_w1*/
+      break;
+    case CAN_IT_RQCP1:
+      CAN->TSR = CAN_TSR_RQCP1; /* rc_w1*/
+      break;
+    case CAN_IT_RQCP2:
+      CAN->TSR = CAN_TSR_RQCP2; /* rc_w1*/
+      break;
+    case CAN_IT_FF0:
+      CAN->RF0R = CAN_RF0R_FULL0; /* rc_w1*/
+      break;
+    case CAN_IT_FOV0:
+      CAN->RF0R = CAN_RF0R_FOVR0; /* rc_w1*/
+      break;
+    case CAN_IT_FF1:
+      CAN->RF1R = CAN_RF1R_FULL1; /* rc_w1*/
+      break;
+    case CAN_IT_FOV1:
+      CAN->RF1R = CAN_RF1R_FOVR1; /* rc_w1*/
+      break;
+    case CAN_IT_EWG:
+      CAN->ESR &= ~ CAN_ESR_EWGF; /* rw */
+      break;
+    case CAN_IT_EPV:
+      CAN->ESR &= ~ CAN_ESR_EPVF; /* rw */
+      break;
+    case CAN_IT_BOF:
+      CAN->ESR &= ~ CAN_ESR_BOFF; /* rw */
+      break;
+    case CAN_IT_WKU:
+      CAN->MSR = CAN_MSR_WKUI;  /* rc_w1*/
+      break;
+    case CAN_IT_SLK:
+      CAN->MSR = CAN_MSR_SLAKI;  /* rc_w1*/
+      break;
+    default :
+      break;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : CheckITStatus
+* Description    : Checks whether the CAN interrupt has occurred or not.
+* Input          : CAN_Reg: specifies the CAN interrupt register to check.
+*                  It_Bit: specifies the interrupt source bit to check.
+* Output         : None.
+* Return         : The new state of the CAN Interrupt (SET or RESET).
+*******************************************************************************/
+static ITStatus CheckITStatus(u32 CAN_Reg, u32 It_Bit)
+{
+  ITStatus pendingbitstatus = RESET;
+
+  if ((CAN_Reg & It_Bit) != (u32)RESET)
+  {
+    /* CAN_IT is set */
+    pendingbitstatus = SET;
+  }
+  else
+  {
+    /* CAN_IT is reset */
+    pendingbitstatus = RESET;
+  }
+
+  return pendingbitstatus;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_crc.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_crc.c
new file mode 100644
index 0000000..b0663fa
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_crc.c
@@ -0,0 +1,164 @@
+/**
+  ******************************************************************************
+  * @file  stm32f10x_crc.c
+  * @author  MCD Application Team
+  * @version  V3.0.0
+  * @date  04/06/2009
+  * @brief  This file provides all the CRC firmware functions.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
© COPYRIGHT 2009 STMicroelectronics

+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_crc.h"
+
+/** @addtogroup StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CRC 
+  * @brief CRC driver modules
+  * @{
+  */
+
+/** @defgroup CRC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Defines
+  * @{
+  */
+
+/* CR register bit mask */
+
+#define CR_RESET_Set    ((uint32_t)0x00000001)
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Resets the CRC Data register (DR).
+  * @param  None
+  * @retval : None
+  */
+void CRC_ResetDR(void)
+{
+  /* Reset CRC generator */
+  CRC->CR = CR_RESET_Set;
+}
+
+/**
+  * @brief  Computes the 32-bit CRC of a given data word(32-bit).
+  * @param Data: data word(32-bit) to compute its CRC
+  * @retval : 32-bit CRC
+  */
+uint32_t CRC_CalcCRC(uint32_t Data)
+{
+  CRC->DR = Data;
+  
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Computes the 32-bit CRC of a given buffer of data word(32-bit).
+  * @param pBuffer: pointer to the buffer containing the data to be 
+  *   computed
+  * @param BufferLength: length of the buffer to be computed					
+  * @retval : 32-bit CRC
+  */
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index = 0;
+  
+  for(index = 0; index < BufferLength; index++)
+  {
+    CRC->DR = pBuffer[index];
+  }
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Returns the current CRC value.
+  * @param  None
+  * @retval : 32-bit CRC
+  */
+uint32_t CRC_GetCRC(void)
+{
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Stores a 8-bit data in the Independent Data(ID) register.
+  * @param IDValue: 8-bit value to be stored in the ID register 					
+  * @retval : None
+  */
+void CRC_SetIDRegister(uint8_t IDValue)
+{
+  CRC->IDR = IDValue;
+}
+
+/**
+  * @brief  Returns the 8-bit data stored in the Independent Data(ID) register
+  * @param  None
+  * @retval : 8-bit value of the ID register 
+  */
+uint8_t CRC_GetIDRegister(void)
+{
+  return (CRC->IDR);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_dac.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_dac.c
new file mode 100644
index 0000000..4b196dc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_dac.c
@@ -0,0 +1,412 @@
+/**
+  ******************************************************************************
+  * @file  stm32f10x_dac.c
+  * @author  MCD Application Team
+  * @version  V3.0.0
+  * @date  04/06/2009
+  * @brief  This file provides all the DAC firmware functions.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
© COPYRIGHT 2009 STMicroelectronics

+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_dac.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DAC 
+  * @brief DAC driver modules
+  * @{
+  */ 
+
+/** @defgroup DAC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_Defines
+  * @{
+  */
+
+/* DAC EN mask */
+#define CR_EN_Set                  ((uint32_t)0x00000001)
+
+/* DAC DMAEN mask */
+#define CR_DMAEN_Set               ((uint32_t)0x00001000)
+
+/* CR register Mask */
+#define CR_CLEAR_Mask              ((uint32_t)0x00000FFE)
+
+/* DAC SWTRIG mask */
+#define SWTRIGR_SWTRIG_Set         ((uint32_t)0x00000001)
+
+/* DAC Dual Channels SWTRIG masks */
+#define DUAL_SWTRIG_Set            ((uint32_t)0x00000003)
+#define DUAL_SWTRIG_Reset          ((uint32_t)0xFFFFFFFC)
+
+/* DHR registers offsets */
+#define DHR12R1_Offset             ((uint32_t)0x00000008)
+#define DHR12R2_Offset             ((uint32_t)0x00000014)
+#define DHR12RD_Offset             ((uint32_t)0x00000020)
+
+/* DOR register offset */
+#define DOR_Offset                 ((uint32_t)0x0000002C)
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the DAC peripheral registers to their default
+  *   reset values.
+  * @param  None
+  * @retval : None
+  */
+void DAC_DeInit(void)
+{
+  /* Enable DAC reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
+  /* Release DAC from reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
+}
+
+/**
+  * @brief  Initializes the DAC peripheral according to the specified 
+  *   parameters in the DAC_InitStruct.
+  * @param DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  * @arg DAC_Channel_1: DAC Channel1 selected
+  * @arg DAC_Channel_2: DAC Channel2 selected
+  * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
+  *   contains the configuration information for the specified
+  *   DAC channel.
+  * @retval : None
+  */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0;
+  /* Check the DAC parameters */
+  assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
+  assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
+  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
+/*---------------------------- DAC CR Configuration --------------------------*/
+  /* Get the DAC CR value */
+  tmpreg1 = DAC->CR;
+  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+  tmpreg1 &= ~(CR_CLEAR_Mask << DAC_Channel);
+  /* Configure for the selected DAC channel: buffer output, trigger, wave genration,
+     mask/amplitude for wave genration */
+  /* Set TSELx and TENx bits according to DAC_Trigger value */
+  /* Set WAVEx bits according to DAC_WaveGeneration value */
+  /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ 
+  /* Set BOFFx bit according to DAC_OutputBuffer value */   
+  tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
+             DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
+  /* Calculate CR register value depending on DAC_Channel */
+  tmpreg1 |= tmpreg2 << DAC_Channel;
+  /* Write to DAC CR */
+  DAC->CR = tmpreg1;
+}
+
+/**
+  * @brief  Fills each DAC_InitStruct member with its default value.
+  * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure
+  *   which will be initialized.
+  * @retval : None
+  */
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
+{
+/*--------------- Reset DAC init structure parameters values -----------------*/
+  /* Initialize the DAC_Trigger member */
+  DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
+  /* Initialize the DAC_WaveGeneration member */
+  DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
+  /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
+  DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
+  /* Initialize the DAC_OutputBuffer member */
+  DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+}
+
+/**
+  * @brief  Enables or disables the specified DAC channel.
+  * @param DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  * @arg DAC_Channel_1: DAC Channel1 selected
+  * @arg DAC_Channel_2: DAC Channel2 selected
+  * @param NewState: new state of the DAC channel. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel */
+    DAC->CR |= CR_EN_Set << DAC_Channel;
+  }
+  else
+  {
+    /* Disable the selected DAC channel */
+    DAC->CR &= ~(CR_EN_Set << DAC_Channel);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified DAC channel DMA request.
+  * @param DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  * @arg DAC_Channel_1: DAC Channel1 selected
+  * @arg DAC_Channel_2: DAC Channel2 selected
+  * @param NewState: new state of the selected DAC channel DMA request.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel DMA request */
+    DAC->CR |= CR_DMAEN_Set << DAC_Channel;
+  }
+  else
+  {
+    /* Disable the selected DAC channel DMA request */
+    DAC->CR &= ~(CR_DMAEN_Set << DAC_Channel);
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel software trigger.
+  * @param DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  * @arg DAC_Channel_1: DAC Channel1 selected
+  * @arg DAC_Channel_2: DAC Channel2 selected
+  * @param NewState: new state of the selected DAC channel software trigger.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for the selected DAC channel */
+    DAC->SWTRIGR |= SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4);
+  }
+  else
+  {
+    /* Disable software trigger for the selected DAC channel */
+    DAC->SWTRIGR &= ~(SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4));
+  }
+}
+
+/**
+  * @brief  Enables or disables simultaneously the two DAC channels software
+  *   triggers.
+  * @param NewState: new state of the DAC channels software triggers.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for both DAC channels */
+    DAC->SWTRIGR |= DUAL_SWTRIG_Set ;
+  }
+  else
+  {
+    /* Disable software trigger for both DAC channels */
+    DAC->SWTRIGR &= DUAL_SWTRIG_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel wave generation.
+  * @param DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  * @arg DAC_Channel_1: DAC Channel1 selected
+  * @arg DAC_Channel_2: DAC Channel2 selected
+  * @param DAC_Wave: Specifies the wave type to enable or disable.
+  *   This parameter can be one of the following values:
+  * @arg DAC_Wave_Noise: noise wave generation
+  * @arg DAC_Wave_Triangle: triangle wave generation
+  * @param NewState: new state of the selected DAC channel wave generation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_WAVE(DAC_Wave)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected wave generation for the selected DAC channel */
+    DAC->CR |= DAC_Wave << DAC_Channel;
+  }
+  else
+  {
+    /* Disable the selected wave generation for the selected DAC channel */
+    DAC->CR &= ~(DAC_Wave << DAC_Channel);
+  }
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel1.
+  * @param DAC_Align: Specifies the data alignement for DAC channel1.
+  *   This parameter can be one of the following values:
+  * @arg DAC_Align_8b_R: 8bit right data alignement selected
+  * @arg DAC_Align_12b_L: 12bit left data alignement selected
+  * @arg DAC_Align_12b_R: 12bit right data alignement selected
+  * @param Data : Data to be loaded in the selected data holding 
+  *   register.
+  * @retval : None
+  */
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data));
+  /* Set the DAC channel1 selected data holding register */
+  *((__IO uint32_t *)(DAC_BASE + DHR12R1_Offset + DAC_Align)) = (uint32_t)Data;
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel2.
+  * @param DAC_Align: Specifies the data alignement for DAC channel2.
+  *   This parameter can be one of the following values:
+  * @arg DAC_Align_8b_R: 8bit right data alignement selected
+  * @arg DAC_Align_12b_L: 12bit left data alignement selected
+  * @arg DAC_Align_12b_R: 12bit right data alignement selected
+  * @param Data : Data to be loaded in the selected data holding 
+  *   register.
+  * @retval : None
+  */
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data));
+  /* Set the DAC channel2 selected data holding register */
+  *((__IO uint32_t *)(DAC_BASE + DHR12R2_Offset + DAC_Align)) = (uint32_t)Data;
+}
+
+/**
+  * @brief  Set the specified data holding register value for dual channel
+  *   DAC.
+  * @param DAC_Align: Specifies the data alignement for dual channel DAC.
+  *   This parameter can be one of the following values:
+  * @arg DAC_Align_8b_R: 8bit right data alignement selected
+  * @arg DAC_Align_12b_L: 12bit left data alignement selected
+  * @arg DAC_Align_12b_R: 12bit right data alignement selected
+  * @param Data2: Data for DAC Channel2 to be loaded in the selected data 
+  *   holding register.
+  * @param Data1: Data for DAC Channel1 to be loaded in the selected data 
+  *   holding register.
+  * @retval : None
+  */
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
+{
+  uint32_t data = 0;
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data1));
+  assert_param(IS_DAC_DATA(Data2));
+  
+  /* Calculate and set dual DAC data holding register value */
+  if (DAC_Align == DAC_Align_8b_R)
+  {
+    data = ((uint32_t)Data2 << 8) | Data1; 
+  }
+  else
+  {
+    data = ((uint32_t)Data2 << 16) | Data1;
+  }
+  /* Set the dual DAC selected data holding register */
+  *((__IO uint32_t *)(DAC_BASE + DHR12RD_Offset + DAC_Align)) = data;
+}
+
+/**
+  * @brief  Returns the last data output value of the selected DAC cahnnel.
+  * @param DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  * @arg DAC_Channel_1: DAC Channel1 selected
+  * @arg DAC_Channel_2: DAC Channel2 selected
+  * @retval : The selected DAC channel data output value.
+  */
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  /* Returns the DAC channel data output register value */
+  return (uint16_t) (*(__IO uint32_t*)(DAC_BASE + DOR_Offset + ((uint32_t)DAC_Channel >> 2)));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_dbgmcu.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_dbgmcu.c
new file mode 100644
index 0000000..d64262d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_dbgmcu.c
@@ -0,0 +1,152 @@
+/**
+  ******************************************************************************
+  * @file  stm32f10x_dbgmcu.c
+  * @author  MCD Application Team
+  * @version  V3.0.0
+  * @date  04/06/2009
+  * @brief  This file provides all the DBGMCU firmware functions.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
© COPYRIGHT 2009 STMicroelectronics

+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_dbgmcu.h"
+
+/** @addtogroup StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DBGMCU 
+  * @brief DBGMCU driver modules
+  * @{
+  */ 
+
+/** @defgroup DBGMCU_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Private_Defines
+  * @{
+  */
+
+#define IDCODE_DEVID_Mask    ((uint32_t)0x00000FFF)
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Returns the device revision identifier.
+  * @param  None
+  * @retval : Device revision identifier
+  */
+uint32_t DBGMCU_GetREVID(void)
+{
+   return(DBGMCU->IDCODE >> 16);
+}
+
+/**
+  * @brief  Returns the device identifier.
+  * @param  None
+  * @retval : Device identifier
+  */
+uint32_t DBGMCU_GetDEVID(void)
+{
+   return(DBGMCU->IDCODE & IDCODE_DEVID_Mask);
+}
+
+/**
+  * @brief  Configures the specified peripheral and low power mode behavior
+  *   when the MCU under Debug mode.
+  * @param DBGMCU_Periph: specifies the peripheral and low power mode.
+  *   This parameter can be any combination of the following values:
+  * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode              
+  * @arg DBGMCU_STOP: Keep debugger connection during STOP mode               
+  * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode            
+  * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted          
+  * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted          
+  * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted          
+  * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted          
+  * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted          
+  * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted          
+  * @arg DBGMCU_CAN1_STOP: Debug CAN 1 stopped when Core is halted           
+  * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is 
+  *                                 halted
+  * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is 
+  *                                 halted
+  * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted          
+  * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted          
+  * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted          
+  * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted          
+  * @param NewState: new state of the specified peripheral in Debug mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    DBGMCU->CR |= DBGMCU_Periph;
+  }
+  else
+  {
+    DBGMCU->CR &= ~DBGMCU_Periph;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_dma.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_dma.c
new file mode 100644
index 0000000..30239b7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_dma.c
@@ -0,0 +1,503 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_dma.c
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file provides all the DMA firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_dma.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* DMA ENABLE mask */
+#define CCR_ENABLE_Set          ((u32)0x00000001)
+#define CCR_ENABLE_Reset        ((u32)0xFFFFFFFE)
+
+/* DMA Channelx interrupt pending bit masks */
+#define DMA_Channel1_IT_Mask    ((u32)0x0000000F)
+#define DMA_Channel2_IT_Mask    ((u32)0x000000F0)
+#define DMA_Channel3_IT_Mask    ((u32)0x00000F00)
+#define DMA_Channel4_IT_Mask    ((u32)0x0000F000)
+#define DMA_Channel5_IT_Mask    ((u32)0x000F0000)
+#define DMA_Channel6_IT_Mask    ((u32)0x00F00000)
+#define DMA_Channel7_IT_Mask    ((u32)0x0F000000)
+
+/* DMA registers Masks */
+#define CCR_CLEAR_Mask          ((u32)0xFFFF800F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : DMA_DeInit
+* Description    : Deinitializes the DMA Channelx registers to their default reset
+*                  values.
+* Input          : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA
+*                    Channel.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx)
+{
+  /* DMA Channelx disable */
+  DMA_Cmd(DMA_Channelx, DISABLE);
+
+  /* Reset Channelx control register */
+  DMA_Channelx->CCR  = 0;
+  
+  /* Reset Channelx remaining bytes register */
+  DMA_Channelx->CNDTR = 0;
+  
+  /* Reset Channelx peripheral address register */
+  DMA_Channelx->CPAR  = 0;
+  
+  /* Reset Channelx memory address register */
+  DMA_Channelx->CMAR = 0;
+
+  switch (*(u32*)&DMA_Channelx)
+  {
+    case DMA_Channel1_BASE:
+      /* Reset interrupt pending bits for Channel1 */
+      DMA->IFCR |= DMA_Channel1_IT_Mask;
+      break;
+
+    case DMA_Channel2_BASE:
+      /* Reset interrupt pending bits for Channel2 */
+      DMA->IFCR |= DMA_Channel2_IT_Mask;
+      break;
+
+    case DMA_Channel3_BASE:
+      /* Reset interrupt pending bits for Channel3 */
+      DMA->IFCR |= DMA_Channel3_IT_Mask;
+      break;
+
+    case DMA_Channel4_BASE:
+      /* Reset interrupt pending bits for Channel4 */
+      DMA->IFCR |= DMA_Channel4_IT_Mask;
+      break;
+
+    case DMA_Channel5_BASE:
+      /* Reset interrupt pending bits for Channel5 */
+      DMA->IFCR |= DMA_Channel5_IT_Mask;
+      break;
+
+    case DMA_Channel6_BASE:
+      /* Reset interrupt pending bits for Channel6 */
+      DMA->IFCR |= DMA_Channel6_IT_Mask;
+      break;
+
+    case DMA_Channel7_BASE:
+      /* Reset interrupt pending bits for Channel7 */
+      DMA->IFCR |= DMA_Channel7_IT_Mask;
+      break;
+
+    default:
+      break;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : DMA_Init
+* Description    : Initializes the DMA Channelx according to the specified
+*                  parameters in the DMA_InitStruct.
+* Input          : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA
+*                    Channel.
+*                  - DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
+*                    contains the configuration information for the specified
+*                    DMA Channel.
+* Output         : None
+* Return         : None
+******************************************************************************/
+void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct)
+{
+  u32 tmpreg = 0;
+
+  /* Check the parameters */
+  assert(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
+  assert(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));	   
+  assert(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));  
+  assert(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));   
+  assert(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
+  assert(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
+  assert(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
+  assert(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
+  assert(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
+
+/*--------------------------- DMA Channelx CCR Configuration -----------------*/
+  /* Get the DMA_Channelx CCR value */
+  tmpreg = DMA_Channelx->CCR;
+  /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRCULAR and DIR bits */
+  tmpreg &= CCR_CLEAR_Mask;
+  /* Configure DMA Channelx: data transfer, data size, priority level and mode */
+  /* Set DIR bit according to DMA_DIR value */
+  /* Set CIRCULAR bit according to DMA_Mode value */
+  /* Set PINC bit according to DMA_PeripheralInc value */
+  /* Set MINC bit according to DMA_MemoryInc value */
+  /* Set PSIZE bits according to DMA_PeripheralDataSize value */
+  /* Set MSIZE bits according to DMA_MemoryDataSize value */
+  /* Set PL bits according to DMA_Priority value */
+  /* Set the MEM2MEM bit according to DMA_M2M value */
+  tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
+            DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
+            DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
+            DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
+  /* Write to DMA Channelx CCR */
+  DMA_Channelx->CCR = tmpreg;
+
+/*--------------------------- DMA Channelx CNBTR Configuration ---------------*/
+  /* Write to DMA Channelx CNBTR */
+  DMA_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
+
+/*--------------------------- DMA Channelx CPAR Configuration ----------------*/
+  /* Write to DMA Channelx CPAR */
+  DMA_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
+
+/*--------------------------- DMA Channelx CMAR Configuration ----------------*/
+  /* Write to DMA Channelx CMAR */
+  DMA_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
+}
+
+/*******************************************************************************
+* Function Name  : DMA_StructInit
+* Description    : Fills each DMA_InitStruct member with its default value.
+* Input          : - DMA_InitStruct : pointer to a DMA_InitTypeDef structure
+*                    which will be initialized.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
+{
+/*-------------- Reset DMA init structure parameters values ------------------*/
+  /* Initialize the DMA_PeripheralBaseAddr member */
+  DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
+
+  /* Initialize the DMA_MemoryBaseAddr member */
+  DMA_InitStruct->DMA_MemoryBaseAddr = 0;
+
+  /* Initialize the DMA_DIR member */
+  DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
+
+  /* Initialize the DMA_BufferSize member */
+  DMA_InitStruct->DMA_BufferSize = 0;
+
+  /* Initialize the DMA_PeripheralInc member */
+  DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+
+  /* Initialize the DMA_MemoryInc member */
+  DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
+
+  /* Initialize the DMA_PeripheralDataSize member */
+  DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+
+  /* Initialize the DMA_MemoryDataSize member */
+  DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+
+  /* Initialize the DMA_Mode member */
+  DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
+
+  /* Initialize the DMA_Priority member */
+  DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
+
+  /* Initialize the DMA_M2M member */
+  DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
+}
+
+/*******************************************************************************
+* Function Name  : DMA_Cmd
+* Description    : Enables or disables the specified DMA Channel.
+* Input          : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA
+*                    Channel.
+*                  - NewState: new state of the DMAx Channel. 
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void DMA_Cmd(DMA_Channel_TypeDef*  DMA_Channelx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Channelx */
+    DMA_Channelx->CCR |= CCR_ENABLE_Set;
+  }
+  else
+  {
+    /* Disable the selected DMA Channelx */
+    DMA_Channelx->CCR &= CCR_ENABLE_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : DMA_ITConfig
+* Description    : Enables or disables the specified DMA interrupts.
+* Input          : - DMA_IT: specifies the DMA interrupts sources to be enabled
+*                    or disabled. 
+*                    This parameter can be any combination of the following values:
+*                       - DMA_IT_TC:  Transfer complete interrupt mask
+*                       - DMA_IT_HT:  Half transfer interrupt mask
+*                       - DMA_IT_TE:  Transfer error interrupt mask
+*                  - NewState: new state of the specified DMA interrupts.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void DMA_ITConfig(DMA_Channel_TypeDef* DMA_Channelx, u32 DMA_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_DMA_CONFIG_IT(DMA_IT));
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA interrupts */
+    DMA_Channelx->CCR |= DMA_IT;
+  }
+  else
+  {
+    /* Disable the selected DMA interrupts */
+    DMA_Channelx->CCR &= ~DMA_IT;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : DMA_GetCurrDataCounter
+* Description    : Returns the number of remaining data units in the current
+*                  DMA Channel transfer.
+* Input          : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA
+*                    Channel.
+* Output         : None
+* Return         : The number of remaining data units in the current DMA Channel
+*                  transfer..
+*******************************************************************************/
+u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef*  DMA_Channelx)
+{
+  /* Return the current memory address value for Channelx */
+  return ((u16)(DMA_Channelx->CNDTR));
+}
+
+/*******************************************************************************
+* Function Name  : DMA_GetFlagStatus
+* Description    : Checks whether the specified DMA flag is set or not.
+* Input          : - DMA_FLAG: specifies the flag to check. 
+*                    This parameter can be one of the following values:
+*                       - DMA_FLAG_GL1: Channel1 global flag.
+*                       - DMA_FLAG_TC1: Channel1 transfer complete flag.
+*                       - DMA_FLAG_HT1: Channel1 half transfer flag.
+*                       - DMA_FLAG_TE1: Channel1 transfer error flag.
+*                       - DMA_FLAG_GL2: Channel2 global flag.
+*                       - DMA_FLAG_TC2: Channel2 transfer complete flag.
+*                       - DMA_FLAG_HT2: Channel2 half transfer flag.
+*                       - DMA_FLAG_TE2: Channel2 transfer error flag.
+*                       - DMA_FLAG_GL3: Channel3 global flag.
+*                       - DMA_FLAG_TC3: Channel3 transfer complete flag.
+*                       - DMA_FLAG_HT3: Channel3 half transfer flag.
+*                       - DMA_FLAG_TE3: Channel3 transfer error flag.
+*                       - DMA_FLAG_GL4: Channel4 global flag.
+*                       - DMA_FLAG_TC4: Channel4 transfer complete flag.
+*                       - DMA_FLAG_HT4: Channel4 half transfer flag.
+*                       - DMA_FLAG_TE4: Channel4 transfer error flag.
+*                       - DMA_FLAG_GL5: Channel5 global flag.
+*                       - DMA_FLAG_TC5: Channel5 transfer complete flag.
+*                       - DMA_FLAG_HT5: Channel5 half transfer flag.
+*                       - DMA_FLAG_TE5: Channel5 transfer error flag.
+*                       - DMA_FLAG_GL6: Channel6 global flag.
+*                       - DMA_FLAG_TC6: Channel6 transfer complete flag.
+*                       - DMA_FLAG_HT6: Channel6 half transfer flag.
+*                       - DMA_FLAG_TE6: Channel6 transfer error flag.
+*                       - DMA_FLAG_GL7: Channel7 global flag.
+*                       - DMA_FLAG_TC7: Channel7 transfer complete flag.
+*                       - DMA_FLAG_HT7: Channel7 half transfer flag.
+*                       - DMA_FLAG_TE7: Channel7 transfer error flag.
+* Output         : None
+* Return         : The new state of DMA_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert(IS_DMA_GET_FLAG(DMA_FLAG));
+
+  /* Check the status of the specified DMA flag */
+  if ((DMA->ISR & DMA_FLAG) != (u32)RESET)
+  {
+    /* DMA_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DMA_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DMA_FLAG status */
+  return  bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : DMA_ClearFlag
+* Description    : Clears the DMA's pending flags.
+* Input          : - DMA_FLAG: specifies the flag to clear. 
+*                    This parameter can be any combination of the following values:
+*                       - DMA_FLAG_GL1: Channel1 global flag.
+*                       - DMA_FLAG_TC1: Channel1 transfer complete flag.
+*                       - DMA_FLAG_HT1: Channel1 half transfer flag.
+*                       - DMA_FLAG_TE1: Channel1 transfer error flag.
+*                       - DMA_FLAG_GL2: Channel2 global flag.
+*                       - DMA_FLAG_TC2: Channel2 transfer complete flag.
+*                       - DMA_FLAG_HT2: Channel2 half transfer flag.
+*                       - DMA_FLAG_TE2: Channel2 transfer error flag.
+*                       - DMA_FLAG_GL3: Channel3 global flag.
+*                       - DMA_FLAG_TC3: Channel3 transfer complete flag.
+*                       - DMA_FLAG_HT3: Channel3 half transfer flag.
+*                       - DMA_FLAG_TE3: Channel3 transfer error flag.
+*                       - DMA_FLAG_GL4: Channel4 global flag.
+*                       - DMA_FLAG_TC4: Channel4 transfer complete flag.
+*                       - DMA_FLAG_HT4: Channel4 half transfer flag.
+*                       - DMA_FLAG_TE4: Channel4 transfer error flag.
+*                       - DMA_FLAG_GL5: Channel5 global flag.
+*                       - DMA_FLAG_TC5: Channel5 transfer complete flag.
+*                       - DMA_FLAG_HT5: Channel5 half transfer flag.
+*                       - DMA_FLAG_TE5: Channel5 transfer error flag.
+*                       - DMA_FLAG_GL6: Channel6 global flag.
+*                       - DMA_FLAG_TC6: Channel6 transfer complete flag.
+*                       - DMA_FLAG_HT6: Channel6 half transfer flag.
+*                       - DMA_FLAG_TE6: Channel6 transfer error flag.
+*                       - DMA_FLAG_GL7: Channel7 global flag.
+*                       - DMA_FLAG_TC7: Channel7 transfer complete flag.
+*                       - DMA_FLAG_HT7: Channel7 half transfer flag.
+*                       - DMA_FLAG_TE7: Channel7 transfer error flag.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void DMA_ClearFlag(u32 DMA_FLAG)
+{
+  /* Check the parameters */
+  assert(IS_DMA_CLEAR_FLAG(DMA_FLAG));
+
+  /* Clear the selected DMA flags */
+  DMA->IFCR = DMA_FLAG;
+}
+
+/*******************************************************************************
+* Function Name  : DMA_GetITStatus
+* Description    : Checks whether the specified DMA interrupt has occurred or not.
+* Input          : - DMA_IT: specifies the DMA interrupt source to check. 
+*                    This parameter can be one of the following values:
+*                       - DMA_IT_GL1: Channel1 global interrupt.
+*                       - DMA_IT_TC1: Channel1 transfer complete interrupt.
+*                       - DMA_IT_HT1: Channel1 half transfer interrupt.
+*                       - DMA_IT_TE1: Channel1 transfer error interrupt.
+*                       - DMA_IT_GL2: Channel2 global interrupt.
+*                       - DMA_IT_TC2: Channel2 transfer complete interrupt.
+*                       - DMA_IT_HT2: Channel2 half transfer interrupt.
+*                       - DMA_IT_TE2: Channel2 transfer error interrupt.
+*                       - DMA_IT_GL3: Channel3 global interrupt.
+*                       - DMA_IT_TC3: Channel3 transfer complete interrupt.
+*                       - DMA_IT_HT3: Channel3 half transfer interrupt.
+*                       - DMA_IT_TE3: Channel3 transfer error interrupt.
+*                       - DMA_IT_GL4: Channel4 global interrupt.
+*                       - DMA_IT_TC4: Channel4 transfer complete interrupt.
+*                       - DMA_IT_HT4: Channel4 half transfer interrupt.
+*                       - DMA_IT_TE4: Channel4 transfer error interrupt.
+*                       - DMA_IT_GL5: Channel5 global interrupt.
+*                       - DMA_IT_TC5: Channel5 transfer complete interrupt.
+*                       - DMA_IT_HT5: Channel5 half transfer interrupt.
+*                       - DMA_IT_TE5: Channel5 transfer error interrupt.
+*                       - DMA_IT_GL6: Channel6 global interrupt.
+*                       - DMA_IT_TC6: Channel6 transfer complete interrupt.
+*                       - DMA_IT_HT6: Channel6 half transfer interrupt.
+*                       - DMA_IT_TE6: Channel6 transfer error interrupt.
+*                       - DMA_IT_GL7: Channel7 global interrupt.
+*                       - DMA_IT_TC7: Channel7 transfer complete interrupt.
+*                       - DMA_IT_HT7: Channel7 half transfer interrupt.
+*                       - DMA_IT_TE7: Channel7 transfer error interrupt.
+* Output         : None
+* Return         : The new state of DMA_IT (SET or RESET).
+*******************************************************************************/
+ITStatus DMA_GetITStatus(u32 DMA_IT)
+{
+  ITStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert(IS_DMA_GET_IT(DMA_IT));
+
+  /* Check the status of the specified DMA interrupt */
+  if ((DMA->ISR & DMA_IT) != (u32)RESET)
+  {
+    /* DMA_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DMA_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DMA_IT status */
+  return  bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : DMA_ClearITPendingBit
+* Description    : Clears the DMA’s interrupt pending bits.
+* Input          : - DMA_IT: specifies the DMA interrupt pending bit to clear.
+*                    This parameter can be any combination of the following values:
+*                       - DMA_IT_GL1: Channel1 global interrupt.
+*                       - DMA_IT_TC1: Channel1 transfer complete interrupt.
+*                       - DMA_IT_HT1: Channel1 half transfer interrupt.
+*                       - DMA_IT_TE1: Channel1 transfer error interrupt.
+*                       - DMA_IT_GL2: Channel2 global interrupt.
+*                       - DMA_IT_TC2: Channel2 transfer complete interrupt.
+*                       - DMA_IT_HT2: Channel2 half transfer interrupt.
+*                       - DMA_IT_TE2: Channel2 transfer error interrupt.
+*                       - DMA_IT_GL3: Channel3 global interrupt.
+*                       - DMA_IT_TC3: Channel3 transfer complete interrupt.
+*                       - DMA_IT_HT3: Channel3 half transfer interrupt.
+*                       - DMA_IT_TE3: Channel3 transfer error interrupt.
+*                       - DMA_IT_GL4: Channel4 global interrupt.
+*                       - DMA_IT_TC4: Channel4 transfer complete interrupt.
+*                       - DMA_IT_HT4: Channel4 half transfer interrupt.
+*                       - DMA_IT_TE4: Channel4 transfer error interrupt.
+*                       - DMA_IT_GL5: Channel5 global interrupt.
+*                       - DMA_IT_TC5: Channel5 transfer complete interrupt.
+*                       - DMA_IT_HT5: Channel5 half transfer interrupt.
+*                       - DMA_IT_TE5: Channel5 transfer error interrupt.
+*                       - DMA_IT_GL6: Channel6 global interrupt.
+*                       - DMA_IT_TC6: Channel6 transfer complete interrupt.
+*                       - DMA_IT_HT6: Channel6 half transfer interrupt.
+*                       - DMA_IT_TE6: Channel6 transfer error interrupt.
+*                       - DMA_IT_GL7: Channel7 global interrupt.
+*                       - DMA_IT_TC7: Channel7 transfer complete interrupt.
+*                       - DMA_IT_HT7: Channel7 half transfer interrupt.
+*                       - DMA_IT_TE7: Channel7 transfer error interrupt.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void DMA_ClearITPendingBit(u32 DMA_IT)
+{
+  /* Check the parameters */
+  assert(IS_DMA_CLEAR_IT(DMA_IT));
+
+  /* Clear the selected DMA interrupt pending bits */
+  DMA->IFCR = DMA_IT;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_exti.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_exti.c
new file mode 100644
index 0000000..811d94b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_exti.c
@@ -0,0 +1,219 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_exti.c
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file provides all the EXTI firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_exti.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define EXTI_LineNone    ((u32)0x00000)  /* No interrupt selected */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : EXTI_DeInit
+* Description    : Deinitializes the EXTI peripheral registers to their default 
+*                  reset values.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void EXTI_DeInit(void)
+{
+  EXTI->IMR = 0x00000000;
+  EXTI->EMR = 0x00000000;
+  EXTI->RTSR = 0x00000000; 
+  EXTI->FTSR = 0x00000000; 
+  EXTI->PR = 0x0007FFFF;
+}
+
+/*******************************************************************************
+* Function Name  : EXTI_Init
+* Description    : Initializes the EXTI peripheral according to the specified
+*                  parameters in the EXTI_InitStruct.
+* Input          : - EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
+*                    that contains the configuration information for the EXTI
+*                    peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+  /* Check the parameters */
+  assert(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+  assert(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+  assert(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));  
+  assert(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+     
+  if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+  {
+    *(u32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Mode)|= EXTI_InitStruct->EXTI_Line;
+
+    /* Clear Rising Falling edge configuration */
+    EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
+    EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
+    
+    /* Select the trigger for the selected external interrupts */
+    if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+    {
+      /* Rising Falling edge */
+      EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
+      EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
+    }
+    else
+    {
+      *(u32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Trigger)|= EXTI_InitStruct->EXTI_Line;
+    }
+  }
+  else
+  {
+    /* Disable the selected external lines */
+    *(u32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Mode)&= ~EXTI_InitStruct->EXTI_Line;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : EXTI_StructInit
+* Description    : Fills each EXTI_InitStruct member with its reset value.
+* Input          : - EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
+*                    which will be initialized.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+  EXTI_InitStruct->EXTI_Line = EXTI_LineNone;
+  EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+  EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+  EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/*******************************************************************************
+* Function Name  : EXTI_GenerateSWInterrupt
+* Description    : Generates a Software interrupt.
+* Input          : - EXTI_Line: specifies the EXTI lines to be enabled or
+*                    disabled.
+*                    This parameter can be:
+*                       - EXTI_Linex: External interrupt line x where x(0..18)
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void EXTI_GenerateSWInterrupt(u32 EXTI_Line)
+{
+  /* Check the parameters */
+  assert(IS_EXTI_LINE(EXTI_Line));
+  
+  EXTI->SWIER |= EXTI_Line;
+}
+
+/*******************************************************************************
+* Function Name  : EXTI_GetFlagStatus
+* Description    : Checks whether the specified EXTI line flag is set or not.
+* Input          : - EXTI_Line: specifies the EXTI lines flag to check.
+*                    This parameter can be:
+*                       - EXTI_Linex: External interrupt line x where x(0..18)
+* Output         : None
+* Return         : The new state of EXTI_Line (SET or RESET).
+*******************************************************************************/
+FlagStatus EXTI_GetFlagStatus(u32 EXTI_Line)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert(IS_GET_EXTI_LINE(EXTI_Line));
+  
+  if ((EXTI->PR & EXTI_Line) != (u32)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : EXTI_ClearFlag
+* Description    : Clears the EXTI’s line pending flags.
+* Input          : - EXTI_Line: specifies the EXTI lines flags to clear.
+*                    This parameter can be:
+*                       - EXTI_Linex: External interrupt line x where x(0..18)
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void EXTI_ClearFlag(u32 EXTI_Line)
+{
+  /* Check the parameters */
+  assert(IS_EXTI_LINE(EXTI_Line));
+  
+  EXTI->PR = EXTI_Line;
+}
+
+/*******************************************************************************
+* Function Name  : EXTI_GetITStatus
+* Description    : Checks whether the specified EXTI line is asserted or not.
+* Input          : - EXTI_Line: specifies the EXTI lines to check.
+*                    This parameter can be:
+*                       - EXTI_Linex: External interrupt line x where x(0..18)
+* Output         : None
+* Return         : The new state of EXTI_Line (SET or RESET).
+*******************************************************************************/
+ITStatus EXTI_GetITStatus(u32 EXTI_Line)
+{
+  ITStatus bitstatus = RESET;
+  u32 enablestatus = 0;
+
+  /* Check the parameters */
+  assert(IS_GET_EXTI_LINE(EXTI_Line));
+  
+  enablestatus =  EXTI->IMR & EXTI_Line;
+
+  if (((EXTI->PR & EXTI_Line) != (u32)RESET) && enablestatus)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : EXTI_ClearITPendingBit
+* Description    : Clears the EXTI’s line pending bits.
+* Input          : - EXTI_Line: specifies the EXTI lines to clear.
+*                    This parameter can be:
+*                       - EXTI_Linex: External interrupt line x where x(0..18)
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void EXTI_ClearITPendingBit(u32 EXTI_Line)
+{
+  /* Check the parameters */
+  assert(IS_EXTI_LINE(EXTI_Line));
+  
+  EXTI->PR = EXTI_Line;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_flash.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_flash.c
new file mode 100644
index 0000000..1d966e4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_flash.c
@@ -0,0 +1,881 @@
+/**
+  ******************************************************************************
+  * @file  stm32f10x_flash.c
+  * @author  MCD Application Team
+  * @version  V3.0.0
+  * @date  04/06/2009
+  * @brief  This file provides all the FLASH firmware functions.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
© COPYRIGHT 2009 STMicroelectronics

+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_flash.h"
+
+/** @addtogroup StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup FLASH 
+  * @brief FLASH driver modules
+  * @{
+  */ 
+
+/** @defgroup FLASH_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Private_Defines
+  * @{
+  */ 
+
+/* Flash Access Control Register bits */
+#define ACR_LATENCY_Mask         ((uint32_t)0x00000038)
+#define ACR_HLFCYA_Mask          ((uint32_t)0xFFFFFFF7)
+#define ACR_PRFTBE_Mask          ((uint32_t)0xFFFFFFEF)
+
+/* Flash Access Control Register bits */
+#define ACR_PRFTBS_Mask          ((uint32_t)0x00000020) 
+
+/* Flash Control Register bits */
+#define CR_PG_Set                ((uint32_t)0x00000001)
+#define CR_PG_Reset              ((uint32_t)0x00001FFE) 
+#define CR_PER_Set               ((uint32_t)0x00000002)
+#define CR_PER_Reset             ((uint32_t)0x00001FFD)
+#define CR_MER_Set               ((uint32_t)0x00000004)
+#define CR_MER_Reset             ((uint32_t)0x00001FFB)
+#define CR_OPTPG_Set             ((uint32_t)0x00000010)
+#define CR_OPTPG_Reset           ((uint32_t)0x00001FEF)
+#define CR_OPTER_Set             ((uint32_t)0x00000020)
+#define CR_OPTER_Reset           ((uint32_t)0x00001FDF)
+#define CR_STRT_Set              ((uint32_t)0x00000040)
+#define CR_LOCK_Set              ((uint32_t)0x00000080)
+
+/* FLASH Mask */
+#define RDPRT_Mask               ((uint32_t)0x00000002)
+#define WRP0_Mask                ((uint32_t)0x000000FF)
+#define WRP1_Mask                ((uint32_t)0x0000FF00)
+#define WRP2_Mask                ((uint32_t)0x00FF0000)
+#define WRP3_Mask                ((uint32_t)0xFF000000)
+
+/* FLASH Keys */
+#define RDP_Key                  ((uint16_t)0x00A5)
+#define FLASH_KEY1               ((uint32_t)0x45670123)
+#define FLASH_KEY2               ((uint32_t)0xCDEF89AB)
+
+/* Delay definition */   
+#define EraseTimeout             ((uint32_t)0x00000FFF)
+#define ProgramTimeout           ((uint32_t)0x0000000F)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Private_FunctionPrototypes
+  * @{
+  */
+
+static void delay(void);
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Sets the code latency value.
+  * @param FLASH_Latency: specifies the FLASH Latency value.
+  *   This parameter can be one of the following values:
+  * @arg FLASH_Latency_0: FLASH Zero Latency cycle
+  * @arg FLASH_Latency_1: FLASH One Latency cycle
+  * @arg FLASH_Latency_2: FLASH Two Latency cycles
+  * @retval : None
+  */
+void FLASH_SetLatency(uint32_t FLASH_Latency)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_FLASH_LATENCY(FLASH_Latency));
+  
+  /* Read the ACR register */
+  tmpreg = FLASH->ACR;  
+  
+  /* Sets the Latency value */
+  tmpreg &= ACR_LATENCY_Mask;
+  tmpreg |= FLASH_Latency;
+  
+  /* Write the ACR register */
+  FLASH->ACR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Half cycle flash access.
+  * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.
+  *   This parameter can be one of the following values:
+  * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
+  * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
+  * @retval : None
+  */
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess));
+  
+  /* Enable or disable the Half cycle access */
+  FLASH->ACR &= ACR_HLFCYA_Mask;
+  FLASH->ACR |= FLASH_HalfCycleAccess;
+}
+
+/**
+  * @brief  Enables or disables the Prefetch Buffer.
+  * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status.
+  *   This parameter can be one of the following values:
+  * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
+  * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
+  * @retval : None
+  */
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer));
+  
+  /* Enable or disable the Prefetch Buffer */
+  FLASH->ACR &= ACR_PRFTBE_Mask;
+  FLASH->ACR |= FLASH_PrefetchBuffer;
+}
+
+/**
+  * @brief  Unlocks the FLASH Program Erase Controller.
+  * @param  None
+  * @retval : None
+  */
+void FLASH_Unlock(void)
+{
+  /* Authorize the FPEC Access */
+  FLASH->KEYR = FLASH_KEY1;
+  FLASH->KEYR = FLASH_KEY2;
+}
+
+/**
+  * @brief  Locks the FLASH Program Erase Controller.
+  * @param  None
+  * @retval : None
+  */
+void FLASH_Lock(void)
+{
+  /* Set the Lock Bit to lock the FPEC and the FCR */
+  FLASH->CR |= CR_LOCK_Set;
+}
+
+/**
+  * @brief  Erases a specified FLASH page.
+  * @param Page_Address: The page address to be erased.
+  * @retval : FLASH Status: The returned value can be: FLASH_BUSY, 
+  *   FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or 
+  *   FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Page_Address));
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(EraseTimeout);
+  
+  if(status == FLASH_COMPLETE)
+  { 
+    /* if the previous operation is completed, proceed to erase the page */
+    FLASH->CR|= CR_PER_Set;
+    FLASH->AR = Page_Address; 
+    FLASH->CR|= CR_STRT_Set;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+    if(status != FLASH_BUSY)
+    {
+      /* if the erase operation is completed, disable the PER Bit */
+      FLASH->CR &= CR_PER_Reset;
+    }
+  }
+  /* Return the Erase Status */
+  return status;
+}
+
+/**
+  * @brief  Erases all FLASH pages.
+  * @param  None
+  * @retval : FLASH Status: The returned value can be: FLASH_BUSY, 
+  *   FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or 
+  *   FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_EraseAllPages(void)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(EraseTimeout);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* if the previous operation is completed, proceed to erase all pages */
+     FLASH->CR |= CR_MER_Set;
+     FLASH->CR |= CR_STRT_Set;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+    if(status != FLASH_BUSY)
+    {
+      /* if the erase operation is completed, disable the MER Bit */
+      FLASH->CR &= CR_MER_Reset;
+    }
+  }	   
+  /* Return the Erase Status */
+  return status;
+}
+
+/**
+  * @brief  Erases the FLASH option bytes.
+  * @param  None
+  * @retval : FLASH Status: The returned value can be: FLASH_BUSY, 
+  *   FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or 
+  *   FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_EraseOptionBytes(void)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(EraseTimeout);
+  if(status == FLASH_COMPLETE)
+  {
+    /* Authorize the small information block programming */
+    FLASH->OPTKEYR = FLASH_KEY1;
+    FLASH->OPTKEYR = FLASH_KEY2;
+    
+    /* if the previous operation is completed, proceed to erase the option bytes */
+    FLASH->CR |= CR_OPTER_Set;
+    FLASH->CR |= CR_STRT_Set;
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+    
+    if(status == FLASH_COMPLETE)
+    {
+      /* if the erase operation is completed, disable the OPTER Bit */
+      FLASH->CR &= CR_OPTER_Reset;
+       
+      /* Enable the Option Bytes Programming operation */
+      FLASH->CR |= CR_OPTPG_Set;
+      /* Enable the readout access */
+      OB->RDP= RDP_Key; 
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(ProgramTimeout);
+ 
+      if(status != FLASH_BUSY)
+      {
+        /* if the program operation is completed, disable the OPTPG Bit */
+        FLASH->CR &= CR_OPTPG_Reset;
+      }
+    }
+    else
+    {
+      if (status != FLASH_BUSY)
+      {
+        /* Disable the OPTPG Bit */
+        FLASH->CR &= CR_OPTPG_Reset;
+      }
+    }  
+  }
+  /* Return the erase status */
+  return status;
+}
+
+/**
+  * @brief  Programs a word at a specified address.
+  * @param Address: specifies the address to be programmed.
+  * @param Data: specifies the data to be programmed.
+  * @retval : FLASH Status: The returned value can be: FLASH_BUSY, 
+  *   FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or 
+  *   FLASH_TIMEOUT. 
+  */
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(ProgramTimeout);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* if the previous operation is completed, proceed to program the new first 
+    half word */
+    FLASH->CR |= CR_PG_Set;
+  
+    *(__IO uint16_t*)Address = (uint16_t)Data;
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+ 
+    if(status == FLASH_COMPLETE)
+    {
+      /* if the previous operation is completed, proceed to program the new second 
+      half word */
+      *(__IO uint16_t*)(Address + 2) = Data >> 16;
+    
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(ProgramTimeout);
+        
+      if(status != FLASH_BUSY)
+      {
+        /* Disable the PG Bit */
+        FLASH->CR &= CR_PG_Reset;
+      }
+    }
+    else
+    {
+      if (status != FLASH_BUSY)
+      {
+        /* Disable the PG Bit */
+        FLASH->CR &= CR_PG_Reset;
+      }
+     }
+  }
+  /* Return the Program Status */
+  return status;
+}
+
+/**
+  * @brief  Programs a half word at a specified address.
+  * @param Address: specifies the address to be programmed.
+  * @param Data: specifies the data to be programmed.
+  * @retval : FLASH Status: The returned value can be: FLASH_BUSY, 
+  *   FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or 
+  *   FLASH_TIMEOUT. 
+  */
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(ProgramTimeout);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* if the previous operation is completed, proceed to program the new data */
+    FLASH->CR |= CR_PG_Set;
+  
+    *(__IO uint16_t*)Address = Data;
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+    if(status != FLASH_BUSY)
+    {
+      /* if the program operation is completed, disable the PG Bit */
+      FLASH->CR &= CR_PG_Reset;
+    }
+  } 
+  /* Return the Program Status */
+  return status;
+}
+
+/**
+  * @brief  Programs a half word at a specified Option Byte Data address.
+  * @param Address: specifies the address to be programmed.
+  *   This parameter can be 0x1FFFF804 or 0x1FFFF806. 
+  * @param Data: specifies the data to be programmed.
+  * @retval : FLASH Status: The returned value can be: FLASH_BUSY, 
+  *   FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or 
+  *   FLASH_TIMEOUT. 
+  */
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  /* Check the parameters */
+  assert_param(IS_OB_DATA_ADDRESS(Address));
+  status = FLASH_WaitForLastOperation(ProgramTimeout);
+  if(status == FLASH_COMPLETE)
+  {
+    /* Authorize the small information block programming */
+    FLASH->OPTKEYR = FLASH_KEY1;
+    FLASH->OPTKEYR = FLASH_KEY2;
+    /* Enables the Option Bytes Programming operation */
+    FLASH->CR |= CR_OPTPG_Set; 
+    *(__IO uint16_t*)Address = Data;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+    if(status != FLASH_BUSY)
+    {
+      /* if the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= CR_OPTPG_Reset;
+    }
+  }    
+  /* Return the Option Byte Data Program Status */
+  return status;
+}
+
+/**
+  * @brief  Write protects the desired pages
+  * @param FLASH_Pages: specifies the address of the pages to be 
+  *   write protected. This parameter can be:
+  * @arg For STM32F10Xxx Medium-density devices (FLASH page size equal to 1 KB)
+  * A value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages124to127
+  * @arg For STM32F10Xxx High-density devices (FLASH page size equal to 2 KB) 
+  * A value between FLASH_WRProt_Pages0to1 and  FLASH_WRProt_Pages60to61 
+  * or FLASH_WRProt_Pages62to255 
+  * @arg FLASH_WRProt_AllPages
+  * @retval : FLASH Status: The returned value can be: FLASH_BUSY, 
+  *   FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or 
+  *   FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)
+{
+  uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+  
+  FLASH_Status status = FLASH_COMPLETE;
+  
+  /* Check the parameters */
+  assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages));
+  
+  FLASH_Pages = (uint32_t)(~FLASH_Pages);
+  WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask);
+  WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8);
+  WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16);
+  WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24);
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(ProgramTimeout);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* Authorizes the small information block programming */
+    FLASH->OPTKEYR = FLASH_KEY1;
+    FLASH->OPTKEYR = FLASH_KEY2;
+    FLASH->CR |= CR_OPTPG_Set;
+    if(WRP0_Data != 0xFF)
+    {
+      OB->WRP0 = WRP0_Data;
+      
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(ProgramTimeout);
+    }
+    if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
+    {
+      OB->WRP1 = WRP1_Data;
+      
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(ProgramTimeout);
+    }
+    if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
+    {
+      OB->WRP2 = WRP2_Data;
+      
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(ProgramTimeout);
+    }
+    
+    if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF))
+    {
+      OB->WRP3 = WRP3_Data;
+     
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(ProgramTimeout);
+    }
+          
+    if(status != FLASH_BUSY)
+    {
+      /* if the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= CR_OPTPG_Reset;
+    }
+  } 
+  /* Return the write protection operation Status */
+  return status;       
+}
+
+/**
+  * @brief  Enables or disables the read out protection.
+  *   If the user has already programmed the other option bytes before 
+  *   calling this function, he must re-program them since this 
+  *   function erases all option bytes.
+  * @param Newstate: new state of the ReadOut Protection.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : FLASH Status: The returned value can be: FLASH_BUSY, 
+  *   FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or 
+  *   FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  status = FLASH_WaitForLastOperation(EraseTimeout);
+  if(status == FLASH_COMPLETE)
+  {
+    /* Authorizes the small information block programming */
+    FLASH->OPTKEYR = FLASH_KEY1;
+    FLASH->OPTKEYR = FLASH_KEY2;
+    FLASH->CR |= CR_OPTER_Set;
+    FLASH->CR |= CR_STRT_Set;
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+    if(status == FLASH_COMPLETE)
+    {
+      /* if the erase operation is completed, disable the OPTER Bit */
+      FLASH->CR &= CR_OPTER_Reset;
+      /* Enable the Option Bytes Programming operation */
+      FLASH->CR |= CR_OPTPG_Set; 
+      if(NewState != DISABLE)
+      {
+        OB->RDP = 0x00;
+      }
+      else
+      {
+        OB->RDP = RDP_Key;  
+      }
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(EraseTimeout); 
+    
+      if(status != FLASH_BUSY)
+      {
+        /* if the program operation is completed, disable the OPTPG Bit */
+        FLASH->CR &= CR_OPTPG_Reset;
+      }
+    }
+    else 
+    {
+      if(status != FLASH_BUSY)
+      {
+        /* Disable the OPTER Bit */
+        FLASH->CR &= CR_OPTER_Reset;
+      }
+    }
+  }
+  /* Return the protection operation Status */
+  return status;      
+}
+
+/**
+  * @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP /
+  *   RST_STDBY.
+  * @param OB_IWDG: Selects the IWDG mode
+  *   This parameter can be one of the following values:
+  * @arg OB_IWDG_SW: Software IWDG selected
+  * @arg OB_IWDG_HW: Hardware IWDG selected
+  * @param OB_STOP: Reset event when entering STOP mode.
+  *   This parameter can be one of the following values:
+  * @arg OB_STOP_NoRST: No reset generated when entering in STOP
+  * @arg OB_STOP_RST: Reset generated when entering in STOP
+  * @param OB_STDBY: Reset event when entering Standby mode.
+  *   This parameter can be one of the following values:
+  * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
+  * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+  * @retval : FLASH Status: The returned value can be: FLASH_BUSY, 
+  *   FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or 
+  *   FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
+{
+  FLASH_Status status = FLASH_COMPLETE; 
+  /* Check the parameters */
+  assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+  assert_param(IS_OB_STOP_SOURCE(OB_STOP));
+  assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+  /* Authorize the small information block programming */
+  FLASH->OPTKEYR = FLASH_KEY1;
+  FLASH->OPTKEYR = FLASH_KEY2;
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(ProgramTimeout);
+  
+  if(status == FLASH_COMPLETE)
+  {  
+    /* Enable the Option Bytes Programming operation */
+    FLASH->CR |= CR_OPTPG_Set; 
+           
+    OB->USER = ( OB_IWDG | OB_STOP |OB_STDBY) | (uint16_t)0xF8; 
+  
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+    if(status != FLASH_BUSY)
+    {
+      /* if the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= CR_OPTPG_Reset;
+    }
+  }    
+  /* Return the Option Byte program Status */
+  return status;
+}
+
+/**
+  * @brief  Returns the FLASH User Option Bytes values.
+  * @param  None
+  * @retval : The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
+  *   and RST_STDBY(Bit2).
+  */
+uint32_t FLASH_GetUserOptionByte(void)
+{
+  /* Return the User Option Byte */
+  return (uint32_t)(FLASH->OBR >> 2);
+}
+
+/**
+  * @brief  Returns the FLASH Write Protection Option Bytes Register value.
+  * @param  None
+  * @retval : The FLASH Write Protection  Option Bytes Register value
+  */
+uint32_t FLASH_GetWriteProtectionOptionByte(void)
+{
+  /* Return the Falsh write protection Register value */
+  return (uint32_t)(FLASH->WRPR);
+}
+
+/**
+  * @brief  Checks whether the FLASH Read Out Protection Status is set 
+  *   or not.
+  * @param  None
+  * @retval : FLASH ReadOut Protection Status(SET or RESET)
+  */
+FlagStatus FLASH_GetReadOutProtectionStatus(void)
+{
+  FlagStatus readoutstatus = RESET;
+  if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)
+  {
+    readoutstatus = SET;
+  }
+  else
+  {
+    readoutstatus = RESET;
+  }
+  return readoutstatus;
+}
+
+/**
+  * @brief  Checks whether the FLASH Prefetch Buffer status is set or not.
+  * @param  None
+  * @retval : FLASH Prefetch Buffer Status (SET or RESET).
+  */
+FlagStatus FLASH_GetPrefetchBufferStatus(void)
+{
+  FlagStatus bitstatus = RESET;
+  
+  if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
+  return bitstatus; 
+}
+
+/**
+  * @brief  Enables or disables the specified FLASH interrupts.
+  * @param FLASH_IT: specifies the FLASH interrupt sources to be 
+  *   enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  * @arg FLASH_IT_ERROR: FLASH Error Interrupt
+  * @arg FLASH_IT_EOP: FLASH end of operation Interrupt
+  * @param NewState: new state of the specified Flash interrupts.
+  *   This parameter can be: ENABLE or DISABLE.      
+  * @retval : None 
+  */
+void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_IT(FLASH_IT)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if(NewState != DISABLE)
+  {
+    /* Enable the interrupt sources */
+    FLASH->CR |= FLASH_IT;
+  }
+  else
+  {
+    /* Disable the interrupt sources */
+    FLASH->CR &= ~(uint32_t)FLASH_IT;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified FLASH flag is set or not.
+  * @param FLASH_FLAG: specifies the FLASH flag to check.
+  *   This parameter can be one of the following values:
+  * @arg FLASH_FLAG_BSY: FLASH Busy flag           
+  * @arg FLASH_FLAG_PGERR: FLASH Program error flag       
+  * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag      
+  * @arg FLASH_FLAG_EOP: FLASH End of Operation flag           
+  * @arg FLASH_FLAG_OPTERR:  FLASH Option Byte error flag     
+  * @retval : The new state of FLASH_FLAG (SET or RESET).
+  */
+FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
+  if(FLASH_FLAG == FLASH_FLAG_OPTERR) 
+  {
+    if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
+    {
+      bitstatus = SET;
+    }
+    else
+    {
+      bitstatus = RESET;
+    }
+  }
+  else
+  {
+   if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
+    {
+      bitstatus = SET;
+    }
+    else
+    {
+      bitstatus = RESET;
+    }
+  }
+  /* Return the new state of FLASH_FLAG (SET or RESET) */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the FLASH’s pending flags.
+  * @param FLASH_FLAG: specifies the FLASH flags to clear.
+  *   This parameter can be any combination of the following values:
+  * @arg FLASH_FLAG_BSY: FLASH Busy flag           
+  * @arg FLASH_FLAG_PGERR: FLASH Program error flag       
+  * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag      
+  * @arg FLASH_FLAG_EOP: FLASH End of Operation flag           
+  * @retval : None
+  */
+void FLASH_ClearFlag(uint16_t FLASH_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
+  
+  /* Clear the flags */
+  FLASH->SR = FLASH_FLAG;
+}
+
+/**
+  * @brief  Returns the FLASH Status.
+  * @param  None
+  * @retval : FLASH Status: The returned value can be: FLASH_BUSY, 
+  *   FLASH_ERROR_PG, FLASH_ERROR_WRP or FLASH_COMPLETE
+  */
+FLASH_Status FLASH_GetStatus(void)
+{
+  FLASH_Status flashstatus = FLASH_COMPLETE;
+  
+  if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) 
+  {
+    flashstatus = FLASH_BUSY;
+  }
+  else 
+  {  
+    if(FLASH->SR & FLASH_FLAG_PGERR)
+    { 
+      flashstatus = FLASH_ERROR_PG;
+    }
+    else 
+    {
+      if(FLASH->SR & FLASH_FLAG_WRPRTERR)
+      {
+        flashstatus = FLASH_ERROR_WRP;
+      }
+      else
+      {
+        flashstatus = FLASH_COMPLETE;
+      }
+    }
+  }
+  /* Return the Flash Status */
+  return flashstatus;
+}
+
+/**
+  * @brief  Waits for a Flash operation to complete or a TIMEOUT to occur.
+  * @param Timeout: FLASH progamming Timeout
+  * @retval : FLASH Status: The returned value can be: FLASH_BUSY, 
+  *   FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or 
+  *   FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
+{ 
+  FLASH_Status status = FLASH_COMPLETE;
+   
+  /* Check for the Flash Status */
+  status = FLASH_GetStatus();
+  /* Wait for a Flash operation to complete or a TIMEOUT to occur */
+  while((status == FLASH_BUSY) && (Timeout != 0x00))
+  {
+    delay();
+    status = FLASH_GetStatus();
+    Timeout--;
+  }
+  if(Timeout == 0x00 )
+  {
+    status = FLASH_TIMEOUT;
+  }
+  /* Return the operation status */
+  return status;
+}
+
+/**
+  * @brief  Inserts a time delay.
+  * @param  None
+  * @retval : None
+  */
+static void delay(void)
+{
+  __IO uint32_t i = 0;
+  for(i = 0xFF; i != 0; i--)
+  {
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_fsmc.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_fsmc.c
new file mode 100644
index 0000000..020711b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_fsmc.c
@@ -0,0 +1,865 @@
+/**
+  ******************************************************************************
+  * @file  stm32f10x_fsmc.c
+  * @author  MCD Application Team
+  * @version  V3.0.0
+  * @date  04/06/2009
+  * @brief  This file provides all the FSMC firmware functions.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
© COPYRIGHT 2009 STMicroelectronics

+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_fsmc.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup FSMC 
+  * @brief FSMC driver modules
+  * @{
+  */ 
+
+/** @defgroup FSMC_Private_TypesDefinitions
+  * @{
+  */ 
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Private_Defines
+  * @{
+  */
+
+/* --------------------- FSMC registers bit mask ---------------------------- */
+
+/* FSMC BCRx Mask */
+#define BCR_MBKEN_Set                       ((uint32_t)0x00000001)
+#define BCR_MBKEN_Reset                     ((uint32_t)0x000FFFFE)
+#define BCR_FACCEN_Set                      ((uint32_t)0x00000040)
+
+/* FSMC PCRx Mask */
+#define PCR_PBKEN_Set                       ((uint32_t)0x00000004)
+#define PCR_PBKEN_Reset                     ((uint32_t)0x000FFFFB)
+#define PCR_ECCEN_Set                       ((uint32_t)0x00000040)
+#define PCR_ECCEN_Reset                     ((uint32_t)0x000FFFBF)
+#define PCR_MemoryType_NAND                 ((uint32_t)0x00000008)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the FSMC NOR/SRAM Banks registers to their default 
+  *   reset values.
+  * @param FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  
+  * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 
+  * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 
+  * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 
+  * @retval : None
+  */
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
+{
+  /* Check the parameter */
+  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
+  
+  /* FSMC_Bank1_NORSRAM1 */
+  if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
+  {
+    FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;    
+  }
+  /* FSMC_Bank1_NORSRAM2,  FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
+  else
+  {   
+    FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; 
+  }
+  FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
+  FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;  
+}
+
+/**
+  * @brief  Deinitializes the FSMC NAND Banks registers to their default 
+  *   reset values.
+  * @param FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND 
+  * @retval : None
+  */
+void FSMC_NANDDeInit(uint32_t FSMC_Bank)
+{
+  /* Check the parameter */
+  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+  
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    /* Set the FSMC_Bank2 registers to their reset values */
+    FSMC_Bank2->PCR2 = 0x00000018;
+    FSMC_Bank2->SR2 = 0x00000040;
+    FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
+    FSMC_Bank2->PATT2 = 0xFCFCFCFC;  
+  }
+  /* FSMC_Bank3_NAND */  
+  else
+  {
+    /* Set the FSMC_Bank3 registers to their reset values */
+    FSMC_Bank3->PCR3 = 0x00000018;
+    FSMC_Bank3->SR3 = 0x00000040;
+    FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
+    FSMC_Bank3->PATT3 = 0xFCFCFCFC; 
+  }  
+}
+
+/**
+  * @brief  Deinitializes the FSMC PCCARD Bank registers to their default 
+  *   reset values.
+  * @param  None                       
+  * @retval : None
+  */
+void FSMC_PCCARDDeInit(void)
+{
+  /* Set the FSMC_Bank4 registers to their reset values */
+  FSMC_Bank4->PCR4 = 0x00000018; 
+  FSMC_Bank4->SR4 = 0x00000000;	
+  FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
+  FSMC_Bank4->PATT4 = 0xFCFCFCFC;
+  FSMC_Bank4->PIO4 = 0xFCFCFCFC;
+}
+
+/**
+  * @brief  Initializes the FSMC NOR/SRAM Banks according to the 
+  *   specified parameters in the FSMC_NORSRAMInitStruct.
+  * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
+  *   structure that contains the configuration information for 
+  *   the FSMC NOR/SRAM specified Banks.                       
+  * @retval : None
+  */
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
+  assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
+  assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
+  assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
+  assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
+  assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
+  assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
+  assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
+  assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
+  assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
+  assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
+  assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));  
+  assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
+  assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
+  assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
+  assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
+  assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
+  assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
+  assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); 
+  
+  /* Bank1 NOR/SRAM control register configuration */ 
+  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 
+            (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
+            FSMC_NORSRAMInitStruct->FSMC_MemoryType |
+            FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
+            FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
+            FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
+            FSMC_NORSRAMInitStruct->FSMC_WrapMode |
+            FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
+            FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
+            FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
+            FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
+            FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
+  if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
+  {
+    FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
+  }
+  /* Bank1 NOR/SRAM timing register configuration */
+  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = 
+            (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
+             FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
+            
+    
+  /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
+  if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
+  {
+    assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
+    assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
+    assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
+    assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
+    assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
+    assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
+    FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 
+              (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
+               FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
+  }
+  else
+  {
+    FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
+  }
+}
+
+/**
+  * @brief  Initializes the FSMC NAND Banks according to the specified 
+  *   parameters in the FSMC_NANDInitStruct.
+  * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef 
+  *   structure that contains the configuration information for 
+  *   the FSMC NAND specified Banks.                       
+  * @retval : None
+  */
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
+{
+  uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; 
+    
+  /* Check the parameters */
+  assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
+  assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
+  assert_param( IS_FSMC_DATA_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
+  assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
+  assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
+  assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
+  assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
+  
+  /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
+  tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
+            PCR_MemoryType_NAND |
+            FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
+            FSMC_NANDInitStruct->FSMC_ECC |
+            FSMC_NANDInitStruct->FSMC_ECCPageSize |
+            (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
+            (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
+            
+  /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
+  tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
+            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); 
+            
+  /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
+  tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
+            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+  
+  if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    /* FSMC_Bank2_NAND registers configuration */
+    FSMC_Bank2->PCR2 = tmppcr;
+    FSMC_Bank2->PMEM2 = tmppmem;
+    FSMC_Bank2->PATT2 = tmppatt;
+  }
+  else
+  {
+    /* FSMC_Bank3_NAND registers configuration */
+    FSMC_Bank3->PCR3 = tmppcr;
+    FSMC_Bank3->PMEM3 = tmppmem;
+    FSMC_Bank3->PATT3 = tmppatt;
+  }
+}
+
+/**
+  * @brief  Initializes the FSMC PCCARD Bank according to the specified 
+  *   parameters in the FSMC_PCCARDInitStruct.
+  * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
+  *   structure that contains the configuration information for 
+  *   the FSMC PCCARD Bank.                       
+  * @retval : None
+  */
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
+  assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
+  assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
+ 
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
+  
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
+  
+  /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
+  FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
+                     FSMC_MemoryDataWidth_16b |  
+                     (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
+                     (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
+            
+  /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
+  FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
+                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); 
+            
+  /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
+  FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
+                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);	
+            
+  /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
+  FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
+                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);             
+}
+
+/**
+  * @brief  Fills each FSMC_NORSRAMInitStruct member with its default value.
+  * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef 
+  *   structure which will be initialized.
+  * @retval : None
+  */
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
+{  
+  /* Reset NOR/SRAM Init structure parameters values */
+  FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
+  FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
+  FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
+  FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+  FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
+  FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; 
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
+}
+
+/**
+  * @brief  Fills each FSMC_NANDInitStruct member with its default value.
+  * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef 
+  *   structure which will be initialized.
+  * @retval : None
+  */
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
+{ 
+  /* Reset NAND Init structure parameters values */
+  FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
+  FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
+  FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+  FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
+  FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
+  FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
+  FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;	  
+}
+
+/**
+  * @brief  Fills each FSMC_PCCARDInitStruct member with its default value.
+  * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef 
+  *   structure which will be initialized.
+  * @retval : None
+  */
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
+{
+  /* Reset PCCARD Init structure parameters values */
+  FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
+  FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
+  FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;	
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+}
+
+/**
+  * @brief  Enables or disables the specified NOR/SRAM Memory Bank.
+  * @param FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  
+  * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 
+  * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 
+  * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 
+  * @param NewState: new state of the FSMC_Bank.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
+    FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
+  }
+  else
+  {
+    /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
+    FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified NAND Memory Bank.
+  * @param FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  * @param NewState: new state of the FSMC_Bank.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
+    }
+    else
+    {
+      FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
+    }
+  }
+  else
+  {
+    /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
+    }
+    else
+    {
+      FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
+    }
+  }
+}
+
+/**
+  * @brief  Enables or disables the PCCARD Memory Bank.
+  * @param NewState: new state of the PCCARD Memory Bank.  
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void FSMC_PCCARDCmd(FunctionalState NewState)
+{
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
+    FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
+  }
+  else
+  {
+    /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
+    FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the FSMC NAND ECC feature.
+  * @param FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  * @param NewState: new state of the FSMC NAND ECC feature.  
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
+    }
+    else
+    {
+      FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
+    }
+  }
+  else
+  {
+    /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
+    }
+    else
+    {
+      FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
+    }
+  }
+}
+
+/**
+  * @brief  Returns the error correction code register value.
+  * @param FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  * @retval : The Error Correction Code (ECC) value.
+  */
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
+{
+  uint32_t eccval = 0x00000000;
+  
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    /* Get the ECCR2 register value */
+    eccval = FSMC_Bank2->ECCR2;
+  }
+  else
+  {
+    /* Get the ECCR3 register value */
+    eccval = FSMC_Bank3->ECCR3;
+  }
+  /* Return the error correction code value */
+  return(eccval);
+}
+
+/**
+  * @brief  Enables or disables the specified FSMC interrupts.
+  * @param FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+  * @param FSMC_IT: specifies the FSMC interrupt sources to be
+  *   enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
+  * @arg FSMC_IT_Level: Level edge detection interrupt.
+  * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
+  * @param NewState: new state of the specified FSMC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
+{
+  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+  assert_param(IS_FSMC_IT(FSMC_IT));	
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected FSMC_Bank2 interrupts */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      FSMC_Bank2->SR2 |= FSMC_IT;
+    }
+    /* Enable the selected FSMC_Bank3 interrupts */
+    else if (FSMC_Bank == FSMC_Bank3_NAND)
+    {
+      FSMC_Bank3->SR3 |= FSMC_IT;
+    }
+    /* Enable the selected FSMC_Bank4 interrupts */
+    else
+    {
+      FSMC_Bank4->SR4 |= FSMC_IT;    
+    }
+  }
+  else
+  {
+    /* Disable the selected FSMC_Bank2 interrupts */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      
+      FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
+    }
+    /* Disable the selected FSMC_Bank3 interrupts */
+    else if (FSMC_Bank == FSMC_Bank3_NAND)
+    {
+      FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
+    }
+    /* Disable the selected FSMC_Bank4 interrupts */
+    else
+    {
+      FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;    
+    }
+  }
+}
+
+/**
+  * @brief  Checks whether the specified FSMC flag is set or not.
+  * @param FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+  * @param FSMC_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
+  * @arg FSMC_FLAG_Level: Level detection Flag.
+  * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
+  * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. 
+  * @retval : The new state of FSMC_FLAG (SET or RESET).
+  */
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tmpsr = 0x00000000;
+  
+  /* Check the parameters */
+  assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
+  assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
+  
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    tmpsr = FSMC_Bank2->SR2;
+  }  
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
+  {
+    tmpsr = FSMC_Bank3->SR3;
+  }
+  /* FSMC_Bank4_PCCARD*/
+  else
+  {
+    tmpsr = FSMC_Bank4->SR4;
+  } 
+  
+  /* Get the flag status */
+  if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the FSMC’s pending flags.
+  * @param FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+  * @param FSMC_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination of the following values:
+  * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
+  * @arg FSMC_FLAG_Level: Level detection Flag.
+  * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
+  * @retval : None
+  */
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
+{
+ /* Check the parameters */
+  assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
+  assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
+    
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    FSMC_Bank2->SR2 &= ~FSMC_FLAG; 
+  }  
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
+  {
+    FSMC_Bank3->SR3 &= ~FSMC_FLAG;
+  }
+  /* FSMC_Bank4_PCCARD*/
+  else
+  {
+    FSMC_Bank4->SR4 &= ~FSMC_FLAG;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified FSMC interrupt has occurred or not.
+  * @param FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+  * @param FSMC_IT: specifies the FSMC interrupt source to check.
+  *   This parameter can be one of the following values:
+  * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
+  * @arg FSMC_IT_Level: Level edge detection interrupt.
+  * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. 
+  * @retval : The new state of FSMC_IT (SET or RESET).
+  */
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; 
+  
+  /* Check the parameters */
+  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+  assert_param(IS_FSMC_GET_IT(FSMC_IT));
+  
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    tmpsr = FSMC_Bank2->SR2;
+  }  
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
+  {
+    tmpsr = FSMC_Bank3->SR3;
+  }
+  /* FSMC_Bank4_PCCARD*/
+  else
+  {
+    tmpsr = FSMC_Bank4->SR4;
+  } 
+  
+  itstatus = tmpsr & FSMC_IT;
+  
+  itenable = tmpsr & (FSMC_IT >> 3);
+  if ((itstatus != (uint32_t)RESET)  && (itenable != (uint32_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus; 
+}
+
+/**
+  * @brief  Clears the FSMC’s interrupt pending bits.
+  * @param FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+  * @param FSMC_IT: specifies the interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
+  * @arg FSMC_IT_Level: Level edge detection interrupt.
+  * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
+  * @retval : None
+  */
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+  assert_param(IS_FSMC_IT(FSMC_IT));
+    
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); 
+  }  
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
+  {
+    FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
+  }
+  /* FSMC_Bank4_PCCARD*/
+  else
+  {
+    FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
+  }
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_gpio.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_gpio.c
new file mode 100644
index 0000000..571a00d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_gpio.c
@@ -0,0 +1,515 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_gpio.c
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file provides all the GPIO firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_gpio.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define AFIO_OFFSET                 (AFIO_BASE - PERIPH_BASE)
+
+/* --- EVENTCR Register ---*/
+/* Alias word address of EVOE bit */
+#define EVCR_OFFSET                 (AFIO_OFFSET + 0x00)
+#define EVOE_BitNumber              ((u8)0x07)
+#define EVCR_EVOE_BB                (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
+
+#define EVCR_PORTPINCONFIG_MASK     ((u16)0xFF80)
+#define LSB_MASK                    ((u16)0xFFFF)
+#define DBGAFR_POSITION_MASK        ((u32)0x000F0000)
+#define DBGAFR_SWJCFG_MASK          ((u32)0xF8FFFFFF)
+#define DBGAFR_LOCATION_MASK        ((u32)0x00200000)
+#define DBGAFR_NUMBITS_MASK         ((u32)0x00100000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : GPIO_DeInit
+* Description    : Deinitializes the GPIOx peripheral registers to their default
+*                  reset values.
+* Input          : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
+{
+  switch (*(u32*)&GPIOx)
+  {
+    case GPIOA_BASE:
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
+      break;
+
+    case GPIOB_BASE:
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
+      break;
+
+    case GPIOC_BASE:
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
+      break;
+
+    case GPIOD_BASE:
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
+      break;
+      
+    case GPIOE_BASE:
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
+      break;            
+
+    default:
+      break;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : GPIO_AFIODeInit
+* Description    : Deinitializes the Alternate Functions (remap, event control
+*                  and EXTI configuration) registers to their default reset
+*                  values.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void GPIO_AFIODeInit(void)
+{
+  RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
+  RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
+}
+
+/*******************************************************************************
+* Function Name  : GPIO_Init
+* Description    : Initializes the GPIOx peripheral according to the specified
+*                  parameters in the GPIO_InitStruct.
+* Input          : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
+*                  - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
+*                    contains the configuration information for the specified GPIO
+*                    peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
+{
+  u32 currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
+  u32 tmpreg = 0x00, pinmask = 0x00;
+
+  /* Check the parameters */
+  assert(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+  assert(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));  
+  
+/*---------------------------- GPIO Mode Configuration -----------------------*/
+  currentmode = ((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x0F);
+
+  if ((((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x10)) != 0x00)
+  { 
+    /* Check the parameters */
+    assert(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
+    /* Output mode */
+    currentmode |= (u32)GPIO_InitStruct->GPIO_Speed;
+  }
+
+/*---------------------------- GPIO CRL Configuration ------------------------*/
+  /* Configure the eight low port pins */
+  if (((u32)GPIO_InitStruct->GPIO_Pin & ((u32)0x00FF)) != 0x00)
+  {
+    tmpreg = GPIOx->CRL;
+
+    for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+    {
+      pos = ((u32)0x01) << pinpos;
+      /* Get the port pins position */
+      currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+
+      if (currentpin == pos)
+      {
+        pos = pinpos << 2;
+        /* Clear the corresponding low control register bits */
+        pinmask = ((u32)0x0F) << pos;
+        tmpreg &= ~pinmask;
+
+        /* Write the mode configuration in the corresponding bits */
+        tmpreg |= (currentmode << pos);
+
+        /* Reset the corresponding ODR bit */
+        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+        {
+          GPIOx->BRR = (((u32)0x01) << pinpos);
+        }
+        /* Set the corresponding ODR bit */
+        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+        {
+          GPIOx->BSRR = (((u32)0x01) << pinpos);
+        }
+      }
+    }
+    GPIOx->CRL = tmpreg;
+    tmpreg = 0;
+  }
+
+/*---------------------------- GPIO CRH Configuration ------------------------*/
+  /* Configure the eight high port pins */
+  if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
+  {
+    tmpreg = GPIOx->CRH;
+    for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+    {
+      pos = (((u32)0x01) << (pinpos + 0x08));
+      /* Get the port pins position */
+      currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
+      if (currentpin == pos)
+      {
+        pos = pinpos << 2;
+        /* Clear the corresponding high control register bits */
+        pinmask = ((u32)0x0F) << pos;
+        tmpreg &= ~pinmask;
+
+        /* Write the mode configuration in the corresponding bits */
+        tmpreg |= (currentmode << pos);
+
+        /* Reset the corresponding ODR bit */
+        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+        {
+          GPIOx->BRR = (((u32)0x01) << (pinpos + 0x08));
+        }
+        /* Set the corresponding ODR bit */
+        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+        {
+          GPIOx->BSRR = (((u32)0x01) << (pinpos + 0x08));
+        }
+      }
+    }
+    GPIOx->CRH = tmpreg;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : GPIO_StructInit
+* Description    : Fills each GPIO_InitStruct member with its default value.
+* Input          : - GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure
+*                    which will be initialized.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
+{
+  /* Reset GPIO init structure parameters values */
+  GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;
+  GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
+  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
+}
+
+/*******************************************************************************
+* Function Name  : GPIO_ReadInputDataBit
+* Description    : Reads the specified input port pin.
+* Input          : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
+*                : - GPIO_Pin:  specifies the port bit to read.
+*                    This parameter can be GPIO_Pin_x where x can be (0..15).
+* Output         : None
+* Return         : The input port pin value.
+*******************************************************************************/
+u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
+{
+  u8 bitstatus = 0x00;
+  
+  /* Check the parameters */
+  assert(IS_GPIO_PIN(GPIO_Pin)); 
+  
+  if ((GPIOx->IDR & GPIO_Pin) != (u32)Bit_RESET)
+  {
+    bitstatus = (u8)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (u8)Bit_RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : GPIO_ReadInputData
+* Description    : Reads the specified GPIO input data port.
+* Input          : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
+* Output         : None
+* Return         : GPIO input data port value.
+*******************************************************************************/
+u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
+{
+  return ((u16)GPIOx->IDR);
+}
+
+/*******************************************************************************
+* Function Name  : GPIO_ReadOutputDataBit
+* Description    : Reads the specified output data port bit.
+* Input          : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
+*                : - GPIO_Pin:  specifies the port bit to read.
+*                    This parameter can be GPIO_Pin_x where x can be (0..15).
+* Output         : None
+* Return         : The output port pin value.
+*******************************************************************************/
+u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
+{
+  u8 bitstatus = 0x00;
+
+  /* Check the parameters */
+  assert(IS_GPIO_PIN(GPIO_Pin)); 
+  
+  if ((GPIOx->ODR & GPIO_Pin) != (u32)Bit_RESET)
+  {
+    bitstatus = (u8)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (u8)Bit_RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : GPIO_ReadOutputData
+* Description    : Reads the specified GPIO output data port.
+* Input          : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
+* Output         : None
+* Return         : GPIO output data port value.
+*******************************************************************************/
+u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
+{
+  return ((u16)GPIOx->ODR);
+}
+
+/*******************************************************************************
+* Function Name  : GPIO_WriteBit
+* Description    : Sets or clears the selected data port bit.
+* Input          : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
+*                  - GPIO_Pin: specifies the port bit to be written.
+*                    This parameter can be GPIO_Pin_x where x can be (0..15).
+*                  - BitVal: specifies the value to be written to the selected bit.
+*                    This parameter can be one of the BitAction enum values:
+*                       - Bit_RESET: to clear the port pin
+*                       - Bit_SET: to set the port pin
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal)
+{
+  /* Check the parameters */
+  assert(IS_GPIO_PIN(GPIO_Pin));
+  assert(IS_GPIO_BIT_ACTION(BitVal)); 
+  
+  if (BitVal != Bit_RESET)
+  {
+    GPIOx->BSRR = GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BRR = GPIO_Pin;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : GPIO_Write
+* Description    : Writes data to the specified GPIO data port.
+* Input          : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
+*                  - PortVal: specifies the value to be written to the port output
+*                    data register.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal)
+{
+  GPIOx->ODR = PortVal;
+}
+
+/*******************************************************************************
+* Function Name  : GPIO_PinLockConfig
+* Description    : Locks GPIO Pins configuration registers.
+* Input          : - GPIOx: where x can be (A..E) to select the GPIO peripheral.
+*                  - GPIO_Pin: specifies the port bit to be written.
+*                    This parameter can be GPIO_Pin_x where x can be (0..15).
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
+{
+  u32 tmp = 0x00010000;
+  
+  /* Check the parameters */
+  assert(IS_GPIO_PIN(GPIO_Pin));
+  
+  tmp |= GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKK bit */
+  GPIOx->LCKR =  GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LCKR = tmp;
+  /* Read LCKK bit*/
+  tmp = GPIOx->LCKR;
+  /* Read LCKK bit*/
+  tmp = GPIOx->LCKR;
+}
+
+/*******************************************************************************
+* Function Name  : GPIO_EventOutputConfig
+* Description    : Selects the GPIO pin used as Event output.
+* Input          : - GPIO_PortSource: selects the GPIO port to be used as source
+*                    for Event output.
+*                    This parameter can be GPIO_PortSourceGPIOx where x can be
+*                    (A..E).
+*                  - GPIO_PinSource: specifies the pin for the Event output.
+*                    This parameter can be GPIO_PinSourcex where x can be (0..15).
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource)
+{
+  u32 tmpreg = 0x00;
+
+  /* Check the parameters */
+  assert(IS_GPIO_PORT_SOURCE(GPIO_PortSource));
+  assert(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+    
+  tmpreg = AFIO->EVCR;
+  /* Clear the PORT[6:4] and PIN[3:0] bits */
+  tmpreg &= EVCR_PORTPINCONFIG_MASK;
+  tmpreg |= (u32)GPIO_PortSource << 0x04;
+  tmpreg |= GPIO_PinSource;
+
+  AFIO->EVCR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name  : GPIO_EventOutputCmd
+* Description    : Enables or disables the Event Output.
+* Input          : - NewState: new state of the Event output.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void GPIO_EventOutputCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(vu32 *) EVCR_EVOE_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name  : GPIO_PinRemapConfig
+* Description    : Changes the mapping of the specified pin.
+* Input          : - GPIO_Remap: selects the pin to remap.
+*                    This parameter can be one of the following values:
+*                       - GPIO_Remap_SPI1
+*                       - GPIO_Remap_I2C1
+*                       - GPIO_Remap_USART1
+*                       - GPIO_Remap_USART2
+*                       - GPIO_PartialRemap_USART3
+*                       - GPIO_FullRemap_USART3
+*                       - GPIO_PartialRemap_TIM1
+*                       - GPIO_FullRemap_TIM1
+*                       - GPIO_PartialRemap1_TIM2
+*                       - GPIO_PartialRemap2_TIM2
+*                       - GPIO_FullRemap_TIM2
+*                       - GPIO_PartialRemap_TIM3
+*                       - GPIO_FullRemap_TIM3
+*                       - GPIO_Remap_TIM4
+*                       - GPIO_Remap1_CAN
+*                       - GPIO_Remap2_CAN
+*                       - GPIO_Remap_PD01
+*                       - GPIO_Remap_SWJ_NoJTRST
+*                       - GPIO_Remap_SWJ_JTAGDisable
+*                       - GPIO_Remap_SWJ_Disable
+*                  - NewState: new state of the port pin remapping.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState)
+{
+  u32 tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
+
+  /* Check the parameters */
+  assert(IS_GPIO_REMAP(GPIO_Remap));
+  assert(IS_FUNCTIONAL_STATE(NewState));  
+  
+  tmpreg = AFIO->MAPR;
+
+  tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
+  tmp = GPIO_Remap & LSB_MASK;
+
+  if ((GPIO_Remap & DBGAFR_LOCATION_MASK) == DBGAFR_LOCATION_MASK)
+  {
+    tmpreg &= DBGAFR_SWJCFG_MASK;
+  }
+  else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
+  {
+    tmp1 = ((u32)0x03) << tmpmask;
+    tmpreg &= ~tmp1;
+  }
+  else
+  {
+    tmpreg &= ~tmp;
+  }
+
+  if (NewState != DISABLE)
+  {
+    if ((GPIO_Remap & DBGAFR_LOCATION_MASK) == DBGAFR_LOCATION_MASK)
+    {
+      tmpreg |= (tmp << 0x10);
+    }
+    else
+    {
+      tmpreg |= tmp;
+    }
+  }
+  AFIO->MAPR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name  : GPIO_EXTILineConfig
+* Description    : Selects the GPIO pin used as EXTI Line.
+* Input          : - GPIO_PortSource: selects the GPIO port to be used as
+*                    source for EXTI lines.
+*                  - GPIO_PinSource: specifies the EXTI line to be configured.
+*                   This parameter can be GPIO_PinSourcex where x can be (0..15).
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource)
+{
+  u32 tmp = 0x00;
+
+  /* Check the parameters */
+  assert(IS_GPIO_PORT_SOURCE(GPIO_PortSource));
+  assert(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+  
+  tmp = ((u32)0x0F) << (0x04 * (GPIO_PinSource & (u8)0x03));
+
+  AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
+  AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((u32)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (u8)0x03)));
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_i2c.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_i2c.c
new file mode 100644
index 0000000..2809b83
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_i2c.c
@@ -0,0 +1,1186 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_i2c.c
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file provides all the I2C firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_i2c.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* I2C SPE mask */
+#define CR1_PE_Set              ((u16)0x0001)
+#define CR1_PE_Reset            ((u16)0xFFFE)
+
+/* I2C DMAEN mask */
+#define CR2_DMAEN_Set           ((u16)0x0800)
+#define CR2_DMAEN_Reset         ((u16)0xF7FF)
+
+/* I2C LAST mask */
+#define CR2_LAST_Set            ((u16)0x1000)
+#define CR2_LAST_Reset          ((u16)0xEFFF)
+
+/* I2C START mask */
+#define CR1_START_Set           ((u16)0x0100)
+#define CR1_START_Reset         ((u16)0xFEFF)
+
+/* I2C STOP mask */
+#define CR1_STOP_Set            ((u16)0x0200)
+#define CR1_STOP_Reset          ((u16)0xFDFF)
+
+/* I2C ACK mask */
+#define CR1_ACK_Set             ((u16)0x0400)
+#define CR1_ACK_Reset           ((u16)0xFBFF)
+
+/* I2C ENGC mask */
+#define CR1_ENGC_Set            ((u16)0x0040)
+#define CR1_ENGC_Reset          ((u16)0xFFBF)
+
+/* I2C ADD0 mask */
+#define OAR1_ADD0_Set           ((u16)0x0001)
+#define OAR1_ADD0_Reset         ((u16)0xFFFE)
+
+/* I2C SWRST mask */
+#define CR1_SWRST_Set           ((u16)0x8000)
+#define CR1_SWRST_Reset         ((u16)0x7FFF)
+
+/* I2C PEC mask */
+#define CR1_PEC_Set             ((u16)0x1000)
+
+/* I2C ENPEC mask */
+#define CR1_ENPEC_Set           ((u16)0x0020)
+#define CR1_ENPEC_Reset         ((u16)0xFFDF)
+
+/* I2C ENARP mask */
+#define CR1_ENARP_Set           ((u16)0x0010)
+#define CR1_ENARP_Reset         ((u16)0xFFEF)
+
+/* I2C NOSTRETCH mask */
+#define CR1_NOSTRETCH_Set       ((u16)0x0080)
+#define CR1_NOSTRETCH_Reset     ((u16)0xFF7F)
+
+/* I2C ENDUAL mask */
+#define OAR2_ENDUAL_Set         ((u16)0x0001)
+#define OAR2_ENDUAL_Reset       ((u16)0xFFFE)
+
+/* I2C F/S mask */
+#define CCR_FS_Set              ((u16)0x8000)
+
+/* I2C ADD2 mask */
+#define OAR2_ADD2_Reset         ((u16)0xFF01)
+
+/* I2C FREQ mask */
+#define CR2_FREQ_Reset          ((u16)0xFFC0)
+
+/* I2C CCR mask */
+#define CCR_CCR_Set             ((u16)0x0FFF)
+
+/* I2C FLAG mask */
+#define I2C_FLAG_Mask           ((u32)0x00FFFFFF)
+
+/* I2C registers Masks */
+#define CR1_CLEAR_Mask          ((u16)0xFBF5)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : I2C_DeInit
+* Description    : Deinitializes the I2Cx peripheral registers to their default
+*                  reset values.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void I2C_DeInit(I2C_TypeDef* I2Cx)
+{
+  switch (*(u32*)&I2Cx)
+  {
+    case I2C1_BASE:
+      /* Enable I2C1 reset state */
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
+      /* Release I2C1 from reset state */
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
+      break;
+
+    case I2C2_BASE:
+      /* Enable I2C2 reset state */
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
+      /* Release I2C2 from reset state */
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
+      break;
+
+    default:
+      break;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : I2C_Init
+* Description    : Initializes the I2Cx according to the specified parameters
+*                  in the I2C_InitStruct.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
+*                    contains the configuration information for the specified
+*                    I2C peripheral.
+* Output         : None
+* Return         : None
+******************************************************************************/
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
+{
+  u16 tmpreg = 0, freqrange = 0;
+  u16 result = 0x04;
+  u32 pclk1clock = 12000000;
+  RCC_ClocksTypeDef  RCC_Clocks;
+
+  /* Check the parameters */
+  assert(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
+  assert(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
+  assert(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
+  assert(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
+  assert(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
+  assert(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
+
+/*---------------------------- I2Cx CR2 Configuration ------------------------*/
+  /* Get the I2Cx CR2 value */
+  tmpreg = I2Cx->CR2;
+  /* Clear frequency FREQ[5:0] bits */
+  tmpreg &= CR2_FREQ_Reset;
+  /* Get PCLK1Clock frequency value */
+  RCC_GetClocksFreq(&RCC_Clocks);
+  pclk1clock = RCC_Clocks.PCLK1_Frequency;
+  /* Set frequency bits depending on PCLK1Clock value */
+  freqrange = (u16)(pclk1clock / 1000000);
+  tmpreg |= freqrange;
+  /* Write to I2Cx CR2 */
+  I2Cx->CR2 = tmpreg;
+
+/*---------------------------- I2Cx CCR Configuration ------------------------*/
+  /* Disable I2Cx to configure TRISE */
+  I2C_Cmd(I2Cx, DISABLE);
+
+  /* Reset tmpreg value */
+  /* Clear F/S, DUTY and CCR[11:0] bits */
+  tmpreg = 0;
+
+  /* Configure speed in standard mode */
+  if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
+  {
+    /* Standard mode speed calculate */
+    result = (u16)(pclk1clock / (I2C_InitStruct->I2C_ClockSpeed << 1));
+    /* Test if CCR value is under 0x4*/
+    if (result < 0x04)
+    {
+      /* Set minimum allowed value */
+      result = 0x04;  
+    }
+    /* Set speed value for standard mode */
+    tmpreg |= result;	  
+    /* Set Maximum Rise Time: ((1000/(1000000000/pclk1clock))+1 */
+    I2Cx->TRISE = freqrange + 1; 
+  }
+  /* Configure speed in fast mode */
+  else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
+  {
+    if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
+    {
+      /* Fast mode speed calculate: Tlow/Thigh = 2 */
+      result = (u16)(pclk1clock / (I2C_InitStruct->I2C_ClockSpeed * 3));
+    }
+    else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
+    {
+      /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
+      result = (u16)(pclk1clock / (I2C_InitStruct->I2C_ClockSpeed * 25));
+      /* Set DUTY bit */
+      result |= I2C_DutyCycle_16_9;
+    }
+    /* Test if CCR value is under 0x1*/
+    if ((result & CCR_CCR_Set) == 0)
+    {
+      /* Set minimum allowed value */
+      result |= (u16)0x0001;  
+    }
+    /* Set speed value and set F/S bit for fast mode */
+    tmpreg |= result | CCR_FS_Set;
+    /* Set Maximum Rise Time: ((300/(1000000000/pclk1clock))+1 */
+    I2Cx->TRISE = (u16)(((freqrange * 300) / 1000) + 1);  
+  }
+  /* Write to I2Cx CCR */
+  I2Cx->CCR = tmpreg;
+
+  /* Enable I2Cx */
+  I2C_Cmd(I2Cx, ENABLE);
+
+/*---------------------------- I2Cx CR1 Configuration ------------------------*/
+  /* Get the I2Cx CR1 value */
+  tmpreg = I2Cx->CR1;
+  /* Clear ACK, SMBTYPE and  SMBUS bits */
+  tmpreg &= CR1_CLEAR_Mask;
+  /* Configure I2Cx: mode and acknowledgement */
+  /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
+  /* Set ACK bit according to I2C_Ack value */
+  tmpreg |= (u16)((u32)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
+  /* Write to I2Cx CR1 */
+  I2Cx->CR1 = tmpreg;
+
+/*---------------------------- I2Cx OAR1 Configuration -----------------------*/
+  /* Set I2Cx Own Address1 and acknowledged address */
+  I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
+}
+
+/*******************************************************************************
+* Function Name  : I2C_StructInit
+* Description    : Fills each I2C_InitStruct member with its default value.
+* Input          : - I2C_InitStruct: pointer to a I2C_InitTypeDef structure
+*                    which will be initialized.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
+{
+/*---------------- Reset I2C init structure parameters values ----------------*/
+  /* Initialize the I2C_Mode member */
+  I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
+
+  /* Initialize the I2C_DutyCycle member */
+  I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
+
+  /* Initialize the I2C_OwnAddress1 member */
+  I2C_InitStruct->I2C_OwnAddress1 = 0;
+
+  /* Initialize the I2C_Ack member */
+  I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
+
+  /* Initialize the I2C_AcknowledgedAddress member */
+  I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+
+  /* initialize the I2C_ClockSpeed member */
+  I2C_InitStruct->I2C_ClockSpeed = 5000;
+}
+
+/*******************************************************************************
+* Function Name  : I2C_Cmd
+* Description    : Enables or disables the specified I2C peripheral.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - NewState: new state of the I2Cx peripheral. This parameter
+*                    can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C peripheral */
+    I2Cx->CR1 |= CR1_PE_Set;
+  }
+  else
+  {
+    /* Disable the selected I2C peripheral */
+    I2Cx->CR1 &= CR1_PE_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : I2C_DMACmd
+* Description    : Enables or disables the specified I2C DMA requests.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - NewState: new state of the I2C DMA transfer.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C DMA requests */
+    I2Cx->CR2 |= CR2_DMAEN_Set;
+  }
+  else
+  {
+    /* Disable the selected I2C DMA requests */
+    I2Cx->CR2 &= CR2_DMAEN_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : I2C_DMALastTransferCmd
+* Description    : Specifies that the next DMA transfer is the last one.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - NewState: new state of the I2C DMA last transfer.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Next DMA end of transfer is the last transfer */
+    I2Cx->CR2 |= CR2_LAST_Set;
+  }
+  else
+  {
+    /* Next DMA end of transfer is not the last transfer */
+    I2Cx->CR2 &= CR2_LAST_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : I2C_GenerateSTART
+* Description    : Generates I2Cx communication START condition.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - NewState: new state of the I2C START condition generation.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None.
+*******************************************************************************/
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Generate a START condition */
+    I2Cx->CR1 |= CR1_START_Set;
+  }
+  else
+  {
+    /* Disable the START condition generation */
+    I2Cx->CR1 &= CR1_START_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : I2C_GenerateSTOP
+* Description    : Generates I2Cx communication STOP condition.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - NewState: new state of the I2C STOP condition generation.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None.
+*******************************************************************************/
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Generate a STOP condition */
+    I2Cx->CR1 |= CR1_STOP_Set;
+  }
+  else
+  {
+    /* Disable the STOP condition generation */
+    I2Cx->CR1 &= CR1_STOP_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : I2C_AcknowledgeConfig
+* Description    : Enables or disables the specified I2C acknowledge feature.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - NewState: new state of the I2C Acknowledgement.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None.
+*******************************************************************************/
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the acknowledgement */
+    I2Cx->CR1 |= CR1_ACK_Set;
+  }
+  else
+  {
+    /* Disable the acknowledgement */
+    I2Cx->CR1 &= CR1_ACK_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : I2C_OwnAddress2Config
+* Description    : Configures the specified I2C own address2.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - Address: specifies the 7bit I2C own address2.
+* Output         : None
+* Return         : None.
+*******************************************************************************/
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, u8 Address)
+{
+  u16 tmpreg = 0;
+
+  /* Get the old register value */
+  tmpreg = I2Cx->OAR2;
+  /* Reset I2Cx Own address2 bit [7:1] */
+  tmpreg &= OAR2_ADD2_Reset;
+  /* Set I2Cx Own address2 */
+  tmpreg |= (u16)(Address & (u16)0x00FE);
+  /* Store the new register value */
+  I2Cx->OAR2 = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name  : I2C_DualAddressCmd
+* Description    : Enables or disables the specified I2C dual addressing mode.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - NewState: new state of the I2C dual addressing mode.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable dual addressing mode */
+    I2Cx->OAR2 |= OAR2_ENDUAL_Set;
+  }
+  else
+  {
+    /* Disable dual addressing mode */
+    I2Cx->OAR2 &= OAR2_ENDUAL_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : I2C_GeneralCallCmd
+* Description    : Enables or disables the specified I2C general call feature.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - NewState: new state of the I2C General call.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable generall call */
+    I2Cx->CR1 |= CR1_ENGC_Set;
+  }
+  else
+  {
+    /* Disable generall call */
+    I2Cx->CR1 &= CR1_ENGC_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : I2C_ITConfig
+* Description    : Enables or disables the specified I2C interrupts.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - I2C_IT: specifies the I2C interrupts sources to be enabled
+*                    or disabled. 
+*                    This parameter can be any combination of the following values:
+*                       - I2C_IT_BUF: Buffer interrupt mask
+*                       - I2C_IT_EVT: Event interrupt mask
+*                       - I2C_IT_ERR: Error interrupt mask
+*                  - NewState: new state of the specified I2C interrupts.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void I2C_ITConfig(I2C_TypeDef* I2Cx, u16 I2C_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+  assert(IS_I2C_CONFIG_IT(I2C_IT));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C interrupts */
+    I2Cx->CR2 |= I2C_IT;
+  }
+  else
+  {
+    /* Disable the selected I2C interrupts */
+    I2Cx->CR2 &= (u16)~I2C_IT;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : I2C_SendData
+* Description    : Sends a data byte through the I2Cx peripheral.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - Data: Byte to be transmitted..
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void I2C_SendData(I2C_TypeDef* I2Cx, u8 Data)
+{
+  /* Write in the DR register the data to be sent */
+  I2Cx->DR = Data;
+}
+
+/*******************************************************************************
+* Function Name  : I2C_ReceiveData
+* Description    : Returns the most recent received data by the I2Cx peripheral.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* Output         : None
+* Return         : The value of the received data.
+*******************************************************************************/
+u8 I2C_ReceiveData(I2C_TypeDef* I2Cx)
+{
+  /* Return the data in the DR register */
+  return (u8)I2Cx->DR;
+}
+
+/*******************************************************************************
+* Function Name  : I2C_Send7bitAddress
+* Description    : Transmits the address byte to select the slave device.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - Address: specifies the slave address which will be transmitted
+*                  - Direction: specifies whether the I2C device will be a
+*                    Transmitter or a Receiver. 
+*                    This parameter can be one of the following values
+*                       - I2C_Direction_Transmitter: Transmitter mode
+*                       - I2C_Direction_Receiver: Receiver mode
+* Output         : None
+* Return         : None.
+*******************************************************************************/
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 I2C_Direction)
+{
+  /* Check the parameters */
+  assert(IS_I2C_DIRECTION(I2C_Direction));
+
+  /* Test on the direction to set/reset the read/write bit */
+  if (I2C_Direction != I2C_Direction_Transmitter)
+  {
+    /* Set the address ADD0 bit0 for read */
+    Address |= OAR1_ADD0_Set;
+  }
+  else
+  {
+    /* Reset the address bit0 for write */
+    Address &= OAR1_ADD0_Reset;
+  }
+  /* Send the address */
+  I2Cx->DR = Address;
+}
+
+/*******************************************************************************
+* Function Name  : I2C_ReadRegister
+* Description    : Reads the specified I2C register and returns its value.
+* Input1         : - I2C_Register: specifies the register to read.
+*                    This parameter can be one of the following values:
+*                       - I2C_Register_CR1:  CR1 register.
+*                       - I2C_Register_CR2:   CR2 register.
+*                       - I2C_Register_OAR1:  OAR1 register.
+*                       - I2C_Register_OAR2:  OAR2 register.
+*                       - I2C_Register_DR:    DR register.
+*                       - I2C_Register_SR1:   SR1 register.
+*                       - I2C_Register_SR2:   SR2 register.
+*                       - I2C_Register_CCR:   CCR register.
+*                       - I2C_Register_TRISE: TRISE register.
+* Output         : None
+* Return         : The value of the read register.
+*******************************************************************************/
+u16 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register)
+{
+  /* Check the parameters */
+  assert(IS_I2C_REGISTER(I2C_Register));
+
+  /* Return the selected register value */
+  return (*(u16 *)(*((u32 *)&I2Cx) + I2C_Register));
+}
+
+/*******************************************************************************
+* Function Name  : I2C_SoftwareResetCmd
+* Description    : Enables or disables the specified I2C software reset.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - NewState: new state of the I2C software reset.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Peripheral under reset */
+    I2Cx->CR1 |= CR1_SWRST_Set;
+  }
+  else
+  {
+    /* Peripheral not under reset */
+    I2Cx->CR1 &= CR1_SWRST_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : I2C_SMBusAlertConfig
+* Description    : Drives the SMBusAlert pin high or low for the specified I2C.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - I2C_SMBusAlert: specifies SMBAlert pin level. 
+*                    This parameter can be one of the following values:
+*                       - I2C_SMBusAlert_Low: SMBAlert pin driven low
+*                       - I2C_SMBusAlert_High: SMBAlert pin driven high
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, u16 I2C_SMBusAlert)
+{
+  /* Check the parameters */
+  assert(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
+
+  if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
+  {
+    /* Drive the SMBusAlert pin Low */
+    I2Cx->CR1 |= I2C_SMBusAlert_Low;
+  }
+  else
+  {
+    /* Drive the SMBusAlert pin High  */
+    I2Cx->CR1 &= I2C_SMBusAlert_High;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : I2C_TransmitPEC
+* Description    : Enables the specified I2C PEC transfer.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx)
+{
+  /* Enable the selected I2C PEC transmission */
+  I2Cx->CR1 |= CR1_PEC_Set;
+}
+
+/*******************************************************************************
+* Function Name  : I2C_PECPositionConfig
+* Description    : Selects the specified I2C PEC position.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - I2C_PECPosition: specifies the PEC position. 
+*                    This parameter can be one of the following values:
+*                       - I2C_PECPosition_Next: PEC bit indicates that current
+*                         byte is PEC
+*                       - I2C_PECPosition_Current: PEC bit indicates that the
+*                         next byte is PEC
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, u16 I2C_PECPosition)
+{
+  /* Check the parameters */
+  assert(IS_I2C_PEC_POSITION(I2C_PECPosition));
+
+  if (I2C_PECPosition == I2C_PECPosition_Next)
+  {
+    /* PEC indicates that the next byte in shift register is PEC */
+    I2Cx->CR1 |= I2C_PECPosition_Next;
+  }
+  else
+  {
+    /* PEC indicates that the current byte in shift register is PEC */
+    I2Cx->CR1 &= I2C_PECPosition_Current;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : I2C_CalculatePEC
+* Description    : Enables or disables the PEC value calculation of the
+*                  transfered bytes.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - NewState: new state of the I2Cx PEC value calculation.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C PEC calculation */
+    I2Cx->CR1 |= CR1_ENPEC_Set;
+  }
+  else
+  {
+    /* Disable the selected I2C PEC calculation */
+    I2Cx->CR1 &= CR1_ENPEC_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : I2C_GetPEC
+* Description    : Returns the PEC value for the specified I2C.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* Output         : None
+* Return         : The PEC value.
+*******************************************************************************/
+u8 I2C_GetPEC(I2C_TypeDef* I2Cx)
+{
+  u8 pec;
+
+  /* Get the PEC value */
+  pec = (I2Cx->SR2) >> 8;
+  /* Return the selected I2C PEC register value */
+  return pec;
+}
+
+/*******************************************************************************
+* Function Name  : I2C_ARPCmd
+* Description    : Enables or disables the specified I2C ARP.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - NewState: new state of the I2Cx ARP. 
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C ARP */
+    I2Cx->CR1 |= CR1_ENARP_Set;
+  }
+  else
+  {
+    /* Disable the selected I2C ARP */
+    I2Cx->CR1 &= CR1_ENARP_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : I2C_StretchClockCmd
+* Description    : Enables or disables the specified I2C Clock stretching.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - NewState: new state of the I2Cx Clock stretching.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState == DISABLE)
+  {
+    /* Enable the selected I2C Clock stretching */
+    I2Cx->CR1 |= CR1_NOSTRETCH_Set;
+  }
+  else
+  {
+    /* Disable the selected I2C Clock stretching */
+    I2Cx->CR1 &= CR1_NOSTRETCH_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : I2C_FastModeDutyCycleConfig
+* Description    : Selects the specified I2C fast mode duty cycle.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - I2C_DutyCycle: specifies the fast mode duty cycle.
+*                    This parameter can be one of the following values:
+*                       - I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
+*                       - I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, u16 I2C_DutyCycle)
+{
+  /* Check the parameters */
+  assert(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
+
+  if (I2C_DutyCycle != I2C_DutyCycle_16_9)
+  {
+    /* I2C fast mode Tlow/Thigh=2 */
+    I2Cx->CCR &= I2C_DutyCycle_2;
+  }
+  else
+  {
+    /* I2C fast mode Tlow/Thigh=16/9 */
+    I2Cx->CCR |= I2C_DutyCycle_16_9;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : I2C_GetLastEvent
+* Description    : Returns the Last I2C Event.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* Output         : None
+* Return         : The last event
+*******************************************************************************/
+u32 I2C_GetLastEvent(I2C_TypeDef* I2Cx)
+{
+  u32 LastEvent = 0;
+  u32 Flag1 = 0, Flag2 = 0;
+
+  Flag1 = I2Cx->SR1;
+  Flag2 = I2Cx->SR2;
+  Flag2 = Flag2 << 16;
+
+  /* Get the last event value from I2C status register */
+  LastEvent = (Flag1 | Flag2) & I2C_FLAG_Mask;
+
+  /* Return status */
+  return LastEvent;
+}
+
+/*******************************************************************************
+* Function Name  : I2C_CheckEvent
+* Description    : Checks whether the Last I2C Event is equal to the one passed
+*                  as parameter.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - I2C_EVENT: specifies the event to be checked. 
+*                    This parameter can be one of the following values:
+*                       - I2C_EVENT_SLAVE_ADDRESS_MATCHED   : EV1
+*                       - I2C_EVENT_SLAVE_BYTE_RECEIVED     : EV2
+*                       - I2C_EVENT_SLAVE_BYTE_TRANSMITTED  : EV3
+*                       - I2C_EVENT_SLAVE_ACK_FAILURE       : EV3-1
+*                       - I2C_EVENT_MASTER_MODE_SELECT      : EV5
+*                       - I2C_EVENT_MASTER_MODE_SELECTED    : EV6
+*                       - I2C_EVENT_MASTER_BYTE_RECEIVED    : EV7
+*                       - I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8
+*                       - I2C_EVENT_MASTER_MODE_ADDRESS10   : EV9
+*                       - I2C_EVENT_SLAVE_STOP_DETECTED     : EV4
+* Output         : None
+* Return         : An ErrorStatus enumuration value:
+*                       - SUCCESS: Last event is equal to the I2C_Event
+*                       - ERROR: Last event is different from the I2C_Event
+*******************************************************************************/
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, u32 I2C_EVENT)
+{
+  u32 LastEvent = 0;
+  u32 Flag1 = 0, Flag2 = 0;
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert(IS_I2C_EVENT(I2C_EVENT));
+
+  Flag1 = I2Cx->SR1;
+  Flag2 = I2Cx->SR2;
+  Flag2 = Flag2 << 16;
+
+  /* Get the last event value from I2C status register */
+  LastEvent = (Flag1 | Flag2) & I2C_FLAG_Mask;
+
+  /* Check whether the last event is equal to I2C_EVENT */
+  if (LastEvent == I2C_EVENT )
+  {
+    /* SUCCESS: last event is equal to I2C_EVENT */
+    status = SUCCESS;
+  }
+  else
+  {
+    /* ERROR: last event is different from I2C_EVENT */
+    status = ERROR;
+  }
+
+  /* Return status */
+  return status;
+}
+
+/*******************************************************************************
+* Function Name  : I2C_GetFlagStatus
+* Description    : Checks whether the specified I2C flag is set or not.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - I2C_FLAG: specifies the flag to check. 
+*                    This parameter can be one of the following values:
+*                       - I2C_FLAG_DUALF: Dual flag (Slave mode)
+*                       - I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
+*                       - I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
+*                       - I2C_FLAG_GENCALL: General call header flag (Slave mode)
+*                       - I2C_FLAG_TRA: Transmitter/Receiver flag
+*                       - I2C_FLAG_BUSY: Bus busy flag
+*                       - I2C_FLAG_MSL: Master/Slave flag
+*                       - I2C_FLAG_SMBALERT: SMBus Alert flag
+*                       - I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+*                       - I2C_FLAG_PECERR: PEC error in reception flag
+*                       - I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+*                       - I2C_FLAG_AF: Acknowledge failure flag
+*                       - I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+*                       - I2C_FLAG_BERR: Bus error flag
+*                       - I2C_FLAG_TXE: Data register empty flag (Transmitter)
+*                       - I2C_FLAG_RXNE: Data register not empty (Receiver) flag
+*                       - I2C_FLAG_STOPF: Stop detection flag (Slave mode)
+*                       - I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
+*                       - I2C_FLAG_BTF: Byte transfer finished flag
+*                       - I2C_FLAG_ADDR: Address sent flag (Master mode) “ADSL”
+*                                        Address matched flag (Slave mode)”ENDAD”
+*                       - I2C_FLAG_SB: Start bit flag (Master mode)
+* Output         : None
+* Return         : The new state of I2C_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u32 I2C_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  u32 i2cstatus = 0;
+  u32 Flag1 = 0, Flag2 = 0;
+
+  /* Check the parameters */
+  assert(IS_I2C_GET_FLAG(I2C_FLAG));
+
+  /* Read the I2Cx status register */
+  Flag1 = I2Cx->SR1;
+  Flag2 = I2Cx->SR2;
+  Flag2 = (Flag2 & I2C_FLAG_Mask) << 16;
+
+  /* Get the I2C status value */
+  i2cstatus = Flag1 | Flag2;
+
+  /* Get bit[27:0] of the flag */
+  I2C_FLAG &= I2C_FLAG_Mask;
+
+  /* Check the status of the specified I2C flag */
+  if ((i2cstatus & I2C_FLAG) != (u32)RESET)
+  {
+    /* I2C_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* I2C_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the I2C_FLAG status */
+  return  bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : I2C_ClearFlag
+* Description    : Clears the I2Cx's pending flags.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - I2C_FLAG: specifies the flag to clear. 
+*                    This parameter can be one of the following values:
+*                       - I2C_FLAG_SMBALERT: SMBus Alert flag
+*                       - I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+*                       - I2C_FLAG_PECERR: PEC error in reception flag
+*                       - I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+*                       - I2C_FLAG_AF: Acknowledge failure flag
+*                       - I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+*                       - I2C_FLAG_BERR: Bus error flag
+*                       - I2C_FLAG_STOPF: Stop detection flag (Slave mode)
+*                       - I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
+*                       - I2C_FLAG_BTF: Byte transfer finished flag
+*                       - I2C_FLAG_ADDR: Address sent flag (Master mode) “ADSL”
+*                                        Address matched flag (Slave mode)”ENDAD”
+*                       - I2C_FLAG_SB: Start bit flag (Master mode)
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, u32 I2C_FLAG)
+{
+  u32 flagpos = 0;
+  u8 flagindex = 0;
+
+  /* Check the parameters */
+  assert(IS_I2C_CLEAR_FLAG(I2C_FLAG));
+
+  /* Get the I2C flag position */
+  flagpos = I2C_FLAG & I2C_FLAG_Mask;
+
+  /* Get the I2C flag index */
+  flagindex = I2C_FLAG >> 28;
+
+  /* Clear the flag by writing 0 */
+  if (flagindex == 1)
+  {
+    /* Clear the selected I2C flag */
+    I2Cx->SR1 &= ~flagpos;
+  }
+  /* Flags that need a read of the SR1 register to be cleared */
+  else if (flagindex == 2)
+  {
+    /* Read the SR1 register */
+    (void)I2Cx->SR1;
+  }
+  /* Flags that need a read of SR1 and a write on CR2 registers to be cleared */
+  else if (flagindex == 6)
+  {
+    /* Read the SR1 register */
+    (void)I2Cx->SR1;
+
+    /* Write on the CR1 register */
+    I2Cx->CR1 |= CR1_PE_Set;
+  }
+  /* Flags that need a read of SR1 and a write on CR2 registers to be cleared */
+  else /*flagindex == 0xA*/
+  {
+    /* Read the SR1 register */
+    (void)I2Cx->SR1;
+
+    /* Read the SR2 register */
+    (void)I2Cx->SR2;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : I2C_GetITStatus
+* Description    : Checks whether the specified I2C interrupt has occurred or not.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - I2C_IT: specifies the interrupt source to check. 
+*                    This parameter can be one of the following values:
+*                       - I2C_IT_SMBALERT: SMBus Alert flag
+*                       - I2C_IT_TIMEOUT: Timeout or Tlow error flag
+*                       - I2C_IT_PECERR: PEC error in reception flag
+*                       - I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
+*                       - I2C_IT_AF: Acknowledge failure flag
+*                       - I2C_IT_ARLO: Arbitration lost flag (Master mode)
+*                       - I2C_IT_BERR: Bus error flag
+*                       - I2C_IT_TXE: Data register empty flag (Transmitter)
+*                       - I2C_IT_RXNE: Data register not empty (Receiver) flag
+*                       - I2C_IT_STOPF: Stop detection flag (Slave mode)
+*                       - I2C_IT_ADD10: 10-bit header sent flag (Master mode)
+*                       - I2C_IT_BTF: Byte transfer finished flag
+*                       - I2C_IT_ADDR: Address sent flag (Master mode) “ADSL”
+*                                        Address matched flag (Slave mode)”ENDAD”
+*                       - I2C_IT_SB: Start bit flag (Master mode)
+* Output         : None
+* Return         : The new state of I2C_IT (SET or RESET).
+*******************************************************************************/
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, u32 I2C_IT)
+{
+  ITStatus bitstatus = RESET;
+  u32 i2cstatus = 0;
+  u32 Flag1 = 0, Flag2 = 0;
+
+  /* Check the parameters */
+  assert(IS_I2C_GET_IT(I2C_IT));
+
+  /* Read the I2Cx status register */
+  Flag1 = I2Cx->SR1;
+  Flag2 = I2Cx->SR2;
+  Flag2 = (Flag2 & I2C_FLAG_Mask) << 16;
+
+  /* Get the I2C status value */
+  i2cstatus = Flag1 | Flag2;
+
+  /* Get bit[27:0] of the flag */
+  I2C_IT &= I2C_FLAG_Mask;
+
+  /* Check the status of the specified I2C flag */
+  if ((i2cstatus & I2C_IT) != (u32)RESET)
+  {
+    /* I2C_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* I2C_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the I2C_IT status */
+  return  bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : I2C_ClearITPendingBit
+* Description    : Clears the I2Cx’s interrupt pending bits.
+* Input          : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+*                  - I2C_IT: specifies the interrupt pending to clear. 
+*                    This parameter can be one of the following values:
+*                       - I2C_IT_SMBALERT: SMBus Alert flag
+*                       - I2C_IT_TIMEOUT: Timeout or Tlow error flag
+*                       - I2C_IT_PECERR: PEC error in reception flag
+*                       - I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
+*                       - I2C_IT_AF: Acknowledge failure flag
+*                       - I2C_IT_ARLO: Arbitration lost flag (Master mode)
+*                       - I2C_IT_BERR: Bus error flag
+*                       - I2C_IT_STOPF: Stop detection flag (Slave mode)
+*                       - I2C_IT_ADD10: 10-bit header sent flag (Master mode)
+*                       - I2C_IT_BTF: Byte transfer finished flag
+*                       - I2C_IT_ADDR: Address sent flag (Master mode) “ADSL”
+*                                        Address matched flag (Slave mode)”ENDAD”
+*                       - I2C_IT_SB: Start bit flag (Master mode)
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, u32 I2C_IT)
+{
+  u32 flagpos = 0;
+  u8 flagindex = 0;
+
+  /* Check the parameters */
+  assert(IS_I2C_CLEAR_IT(I2C_IT));
+
+  /* Get the I2C flag position */
+  flagpos = I2C_IT & I2C_FLAG_Mask;
+
+  /* Get the I2C flag index */
+  flagindex = I2C_IT >> 28;
+
+  /* Clear the flag by writing 0 */
+  if (flagindex == 1)
+  {
+    /* Clear the selected I2C flag */
+    I2Cx->SR1 &= ~flagpos;
+  }
+  /* Flags that need a read of the SR1 register to be cleared */
+  else if (flagindex == 2)
+  {
+    /* Read the SR1 register */
+    (void)I2Cx->SR1;
+  }
+  /* Flags that need a read of SR1 and a write on CR2 registers to be cleared */
+  else if (flagindex == 6)
+  {
+    /* Read the SR1 register */
+    (void)I2Cx->SR1;
+
+    /* Write on the CR1 register */
+    I2Cx->CR1 |= CR1_PE_Set;
+  }
+  /* Flags that need a read of SR1 and a write on CR2 registers to be cleared */
+  else /*flagindex == 0xA*/
+  {
+    /* Read the SR1 register */
+    (void)I2Cx->SR1;
+
+    /* Read the SR2 register */
+    (void)I2Cx->SR2;
+  }
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_iwdg.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_iwdg.c
new file mode 100644
index 0000000..496e68d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_iwdg.c
@@ -0,0 +1,152 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_iwdg.c
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file provides all the IWDG firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_iwdg.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ---------------------- IWDG registers bit mask ------------------------ */
+/* KR register bit mask */
+#define KR_Reload    ((u16)0xAAAA)
+#define KR_Enable    ((u16)0xCCCC)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : IWDG_WriteAccessCmd
+* Description    : Enables or disables write access to IWDG_PR and IWDG_RLR
+*                  registers.
+* Input          : - IWDG_WriteAccess: new state of write access to IWDG_PR and
+*                    IWDG_RLR registers.
+*                    This parameter can be one of the following values:
+*                       - IWDG_WriteAccess_Enable: Enable write access to 
+*                         IWDG_PR and IWDG_RLR registers
+*                       - IWDG_WriteAccess_Disable: Disable write access to
+*                         IWDG_PR and IWDG_RLR registers
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void IWDG_WriteAccessCmd(u16 IWDG_WriteAccess)
+{
+  /* Check the parameters */
+  assert(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
+
+  IWDG->KR = IWDG_WriteAccess;
+}
+
+/*******************************************************************************
+* Function Name  : IWDG_SetPrescaler
+* Description    : Sets IWDG Prescaler value.
+* Input          : - IWDG_Prescaler: specifies the IWDG Prescaler value.
+*                    This parameter can be one of the following values:
+*                       - IWDG_Prescaler_4: IWDG prescaler set to 4
+*                       - IWDG_Prescaler_8: IWDG prescaler set to 8
+*                       - IWDG_Prescaler_16: IWDG prescaler set to 16
+*                       - IWDG_Prescaler_32: IWDG prescaler set to 32
+*                       - IWDG_Prescaler_64: IWDG prescaler set to 64
+*                       - IWDG_Prescaler_128: IWDG prescaler set to 128
+*                       - IWDG_Prescaler_256: IWDG prescaler set to 256
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void IWDG_SetPrescaler(u8 IWDG_Prescaler)
+{
+  /* Check the parameters */
+  assert(IS_IWDG_PRESCALER(IWDG_Prescaler));
+
+  IWDG->PR = IWDG_Prescaler;
+}
+
+/*******************************************************************************
+* Function Name  : IWDG_SetReload
+* Description    : Sets IWDG Reload value.
+* Input          : - Reload: specifies the IWDG Reload value.
+*                    This parameter must be a number between 0 and 0x0FFF.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void IWDG_SetReload(u16 Reload)
+{
+  /* Check the parameters */
+  assert(IS_IWDG_RELOAD(Reload));
+
+  IWDG->RLR = Reload;
+}
+
+/*******************************************************************************
+* Function Name  : IWDG_ReloadCounter
+* Description    : Reloads IWDG counter with value defined in the reload register
+*                  (write access to IWDG_PR and IWDG_RLR registers disabled).
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void IWDG_ReloadCounter(void)
+{
+  IWDG->KR = KR_Reload;
+}
+
+/*******************************************************************************
+* Function Name  : IWDG_Enable
+* Description    : Enables IWDG (write access to IWDG_PR and IWDG_RLR registers
+*                  disabled).
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void IWDG_Enable(void)
+{
+  IWDG->KR = KR_Enable;
+}
+
+/*******************************************************************************
+* Function Name  : IWDG_GetFlagStatus
+* Description    : Checks whether the specified IWDG flag is set or not.
+* Input          : - IWDG_FLAG: specifies the flag to check.
+*                    This parameter can be one of the following values:
+*                       - IWDG_FLAG_PVU: Prescaler Value Update on going
+*                       - IWDG_FLAG_RVU: Reload Value Update on going
+* Output         : None
+* Return         : The new state of IWDG_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus IWDG_GetFlagStatus(u16 IWDG_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert(IS_IWDG_FLAG(IWDG_FLAG));
+
+  if ((IWDG->SR & IWDG_FLAG) != (u32)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_lib.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_lib.c
new file mode 100644
index 0000000..7df2cb8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_lib.c
@@ -0,0 +1,221 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_lib.c
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file provides all peripherals pointers initialization.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+#define EXT
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_lib.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+#ifdef DEBUG
+/*******************************************************************************
+* Function Name  : debug
+* Description    : This function initialize peripherals pointers.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void debug(void)
+{
+
+/************************************* ADC ************************************/
+#ifdef _ADC1
+  ADC1 = (ADC_TypeDef *)  ADC1_BASE;
+#endif /*_ADC1 */
+
+#ifdef _ADC2
+  ADC2 = (ADC_TypeDef *)  ADC2_BASE;
+#endif /*_ADC2 */
+
+/************************************* BKP ************************************/
+#ifdef _BKP
+  BKP = (BKP_TypeDef *)  BKP_BASE;
+#endif /*_BKP */
+
+/************************************* CAN ************************************/
+#ifdef _CAN
+  CAN = (CAN_TypeDef *)  CAN_BASE;
+#endif /*_CAN */
+
+/************************************* DMA ************************************/
+#ifdef _DMA
+  DMA = (DMA_TypeDef *)  DMA_BASE;
+#endif /*_DMA */
+
+#ifdef _DMA_Channel1
+  DMA_Channel1 = (DMA_Channel_TypeDef *)  DMA_Channel1_BASE;
+#endif /*_DMA_Channel1 */
+
+#ifdef _DMA_Channel2
+  DMA_Channel2 = (DMA_Channel_TypeDef *)  DMA_Channel2_BASE;
+#endif /*_DMA_Channel2 */
+
+#ifdef _DMA_Channel3
+  DMA_Channel3 = (DMA_Channel_TypeDef *)  DMA_Channel3_BASE;
+#endif /*_DMA_Channel3 */
+
+#ifdef _DMA_Channel4
+  DMA_Channel4 = (DMA_Channel_TypeDef *)  DMA_Channel4_BASE;
+#endif /*_DMA_Channel4 */
+
+#ifdef _DMA_Channel5
+  DMA_Channel5 = (DMA_Channel_TypeDef *)  DMA_Channel5_BASE;
+#endif /*_DMA_Channel5 */
+
+#ifdef _DMA_Channel6
+  DMA_Channel6 = (DMA_Channel_TypeDef *)  DMA_Channel6_BASE;
+#endif /*_DMA_Channel6 */
+
+#ifdef _DMA_Channel7
+  DMA_Channel7 = (DMA_Channel_TypeDef *)  DMA_Channel7_BASE;
+#endif /*_DMA_Channel7 */
+
+/************************************* EXTI ***********************************/
+#ifdef _EXTI
+  EXTI = (EXTI_TypeDef *)  EXTI_BASE;
+#endif /*_EXTI */
+
+/************************************* FLASH and Option Bytes *****************/
+#ifdef _FLASH
+  FLASH = (FLASH_TypeDef *)  FLASH_BASE;
+  OB = (OB_TypeDef *)  OB_BASE;
+#endif /*_FLASH */
+
+/************************************* GPIO ***********************************/
+#ifdef _GPIOA
+  GPIOA = (GPIO_TypeDef *)  GPIOA_BASE;
+#endif /*_GPIOA */
+
+#ifdef _GPIOB
+  GPIOB = (GPIO_TypeDef *)  GPIOB_BASE;
+#endif /*_GPIOB */
+
+#ifdef _GPIOC
+  GPIOC = (GPIO_TypeDef *)  GPIOC_BASE;
+#endif /*_GPIOC */
+
+#ifdef _GPIOD
+  GPIOD = (GPIO_TypeDef *)  GPIOD_BASE;
+#endif /*_GPIOD */
+
+#ifdef _GPIOE
+  GPIOE = (GPIO_TypeDef *)  GPIOE_BASE;
+#endif /*_GPIOE */
+
+#ifdef _AFIO
+  AFIO = (AFIO_TypeDef *)  AFIO_BASE;
+#endif /*_AFIO */
+
+/************************************* I2C ************************************/
+#ifdef _I2C1
+  I2C1 = (I2C_TypeDef *)  I2C1_BASE;
+#endif /*_I2C1 */
+
+#ifdef _I2C2
+  I2C2 = (I2C_TypeDef *)  I2C2_BASE;
+#endif /*_I2C2 */
+
+/************************************* IWDG ***********************************/
+#ifdef _IWDG
+  IWDG = (IWDG_TypeDef *) IWDG_BASE;
+#endif /*_IWDG */
+
+/************************************* NVIC ***********************************/
+#ifdef _NVIC
+  NVIC = (NVIC_TypeDef *)  NVIC_BASE;
+#endif /*_NVIC */
+
+#ifdef _SCB
+  SCB = (SCB_TypeDef *)  SCB_BASE;
+#endif /*_SCB */
+
+/************************************* PWR ************************************/
+#ifdef _PWR
+  PWR = (PWR_TypeDef *)  PWR_BASE;
+#endif /*_PWR */
+
+/************************************* RCC ************************************/
+#ifdef _RCC
+  RCC = (RCC_TypeDef *)  RCC_BASE;
+#endif /*_RCC */
+
+/************************************* RTC ************************************/
+#ifdef _RTC
+  RTC = (RTC_TypeDef *)  RTC_BASE;
+#endif /*_RTC */
+
+/************************************* SPI ************************************/
+#ifdef _SPI1
+  SPI1 = (SPI_TypeDef *)  SPI1_BASE;
+#endif /*_SPI1 */
+
+#ifdef _SPI2
+  SPI2 = (SPI_TypeDef *)  SPI2_BASE;
+#endif /*_SPI2 */
+
+/************************************* SysTick ********************************/
+#ifdef _SysTick
+  SysTick = (SysTick_TypeDef *)  SysTick_BASE;
+#endif /*_SysTick */
+
+/************************************* TIM1 ***********************************/
+#ifdef _TIM1
+  TIM1 = (TIM1_TypeDef *)  TIM1_BASE;
+#endif /*_TIM1 */
+
+/************************************* TIM ************************************/
+#ifdef _TIM2
+  TIM2 = (TIM_TypeDef *)  TIM2_BASE;
+#endif /*_TIM2 */
+
+#ifdef _TIM3
+  TIM3 = (TIM_TypeDef *)  TIM3_BASE;
+#endif /*_TIM3 */
+
+#ifdef _TIM4
+  TIM4 = (TIM_TypeDef *)  TIM4_BASE;
+#endif /*_TIM4 */
+
+/************************************* USART **********************************/
+#ifdef _USART1
+  USART1 = (USART_TypeDef *) USART1_BASE;
+#endif /*_USART1 */
+
+#ifdef _USART2
+  USART2 = (USART_TypeDef *) USART2_BASE;
+#endif /*_USART2 */
+
+#ifdef _USART3
+  USART3 = (USART_TypeDef *) USART3_BASE;
+#endif /*_USART3 */
+
+/************************************* WWDG ***********************************/
+#ifdef _WWDG
+  WWDG = (WWDG_TypeDef *)  WWDG_BASE;
+#endif /*_WWDG */
+}
+#endif
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_nvic.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_nvic.c
new file mode 100644
index 0000000..79bb867
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_nvic.c
@@ -0,0 +1,755 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_nvic.c
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file provides all the NVIC firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_nvic.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define AIRC_VECTKEY_MASK    ((u32)0x05FA0000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : NVIC_DeInit
+* Description    : Deinitializes the NVIC peripheral registers to their default
+*                  reset values.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_DeInit(void)
+{
+  u32 index = 0;
+  
+  NVIC->Disable[0] = 0xFFFFFFFF;
+  NVIC->Disable[1] = 0x000007FF;
+  NVIC->Clear[0] = 0xFFFFFFFF;
+  NVIC->Clear[1] = 0x000007FF;
+  
+  for(index = 0; index < 0x0B; index++)
+  {
+     NVIC->Priority[index] = 0x00000000;
+  } 
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_SCBDeInit
+* Description    : Deinitializes the SCB peripheral registers to their default 
+*                  reset values.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_SCBDeInit(void)
+{
+  u32 index = 0x00;
+  
+  SCB->IRQControlState = 0x0A000000;
+  SCB->ExceptionTableOffset = 0x00000000;
+  SCB->AIRC = AIRC_VECTKEY_MASK;
+  SCB->SysCtrl = 0x00000000;
+  SCB->ConfigCtrl = 0x00000000;
+  for(index = 0; index < 0x03; index++)
+  {
+     SCB->SystemPriority[index] = 0;
+  }
+  SCB->SysHandlerCtrl = 0x00000000;
+  SCB->ConfigFaultStatus = 0xFFFFFFFF;
+  SCB->HardFaultStatus = 0xFFFFFFFF;
+  SCB->DebugFaultStatus = 0xFFFFFFFF;
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_PriorityGroupConfig
+* Description    : Configures the priority grouping: pre-emption priority
+*                  and subpriority.
+* Input          : - NVIC_PriorityGroup: specifies the priority grouping bits
+*                    length. This parameter can be one of the following values:
+*                       - NVIC_PriorityGroup_0: 0 bits for pre-emption priority
+*                         4 bits for subpriority
+*                       - NVIC_PriorityGroup_1: 1 bits for pre-emption priority
+*                         3 bits for subpriority
+*                       - NVIC_PriorityGroup_2: 2 bits for pre-emption priority
+*                         2 bits for subpriority
+*                       - NVIC_PriorityGroup_3: 3 bits for pre-emption priority
+*                         1 bits for subpriority
+*                       - NVIC_PriorityGroup_4: 4 bits for pre-emption priority
+*                         0 bits for subpriority
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup)
+{
+  /* Check the parameters */
+  assert(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+  
+  /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+  SCB->AIRC = AIRC_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_Init
+* Description    : Initializes the NVIC peripheral according to the specified
+*                  parameters in the NVIC_InitStruct.
+* Input          : - NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure
+*                    that contains the configuration information for the
+*                    specified NVIC peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+  u32 tmppriority = 0x00, tmpreg = 0x00, tmpmask = 0x00;
+  u32 tmppre = 0, tmpsub = 0x0F;
+
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+  assert(IS_NVIC_IRQ_CHANNEL(NVIC_InitStruct->NVIC_IRQChannel));
+  assert(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));  
+  assert(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+    
+  if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+  {
+    /* Compute the Corresponding IRQ Priority --------------------------------*/    
+    tmppriority = (0x700 - (SCB->AIRC & (u32)0x700))>> 0x08;
+    tmppre = (0x4 - tmppriority);
+    tmpsub = tmpsub >> tmppriority;
+    
+    tmppriority = (u32)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+    tmppriority |=  NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
+
+    tmppriority = tmppriority << 0x04;
+    tmppriority = ((u32)tmppriority) << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08);
+    
+    tmpreg = NVIC->Priority[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)];
+    tmpmask = (u32)0xFF << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08);
+    tmpreg &= ~tmpmask;
+    tmppriority &= tmpmask;  
+    tmpreg |= tmppriority;
+
+    NVIC->Priority[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)] = tmpreg;
+    
+    /* Enable the Selected IRQ Channels --------------------------------------*/
+    NVIC->Enable[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] =
+      (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F);
+  }
+  else
+  {
+    /* Disable the Selected IRQ Channels -------------------------------------*/
+    NVIC->Disable[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] =
+      (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_StructInit
+* Description    : Fills each NVIC_InitStruct member with its default value.
+* Input          : - NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure which
+*                    will be initialized.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+  /* NVIC_InitStruct members default value */
+  NVIC_InitStruct->NVIC_IRQChannel = 0x00;
+  NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority = 0x00;
+  NVIC_InitStruct->NVIC_IRQChannelSubPriority = 0x00;
+  NVIC_InitStruct->NVIC_IRQChannelCmd = DISABLE;
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_SETPRIMASK
+* Description    : Enables the PRIMASK priority: Raises the execution priority to 0.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_SETPRIMASK(void)
+{
+  __SETPRIMASK();
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_RESETPRIMASK
+* Description    : Disables the PRIMASK priority.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_RESETPRIMASK(void)
+{
+  __RESETPRIMASK();
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_SETFAULTMASK
+* Description    : Enables the FAULTMASK priority: Raises the execution priority to -1.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_SETFAULTMASK(void)
+{
+  __SETFAULTMASK();
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_RESETFAULTMASK
+* Description    : Disables the FAULTMASK priority.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_RESETFAULTMASK(void)
+{
+  __RESETFAULTMASK();
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_BASEPRICONFIG
+* Description    : The execution priority can be changed from 15 (lowest 
+                   configurable priority) to 1.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_BASEPRICONFIG(u32 NewPriority)
+{
+  /* Check the parameters */
+  assert(IS_NVIC_BASE_PRI(NewPriority));
+  
+  __BASEPRICONFIG(NewPriority << 0x04);
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_GetBASEPRI
+* Description    : Returns the BASEPRI mask value.
+* Input          : None
+* Output         : None
+* Return         : BASEPRI register value
+*******************************************************************************/
+u32 NVIC_GetBASEPRI(void)
+{
+  return (__GetBASEPRI());
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_GetCurrentPendingIRQChannel
+* Description    : Returns the current pending IRQ channel identifier.
+* Input          : None
+* Output         : None
+* Return         : Pending IRQ Channel Identifier.
+*******************************************************************************/
+u16 NVIC_GetCurrentPendingIRQChannel(void)
+{
+  return ((u16)((SCB->IRQControlState & (u32)0x003FF000) >> 0x0C));
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_GetIRQChannelPendingBitStatus
+* Description    : Checks whether the specified IRQ Channel pending bit is set
+*                  or not.
+* Input          : - NVIC_IRQChannel: specifies the interrupt pending bit to check.
+* Output         : None
+* Return         : The new state of IRQ Channel pending bit(SET or RESET).
+*******************************************************************************/
+ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel)
+{
+  ITStatus pendingirqstatus = RESET;
+  u32 tmp = 0x00;
+  
+  /* Check the parameters */
+  assert(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
+  
+  tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F));
+
+  if (((NVIC->Set[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp)
+  {
+    pendingirqstatus = SET;
+  }
+  else
+  {
+    pendingirqstatus = RESET;
+  }
+  return pendingirqstatus;
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_SetIRQChannelPendingBit
+* Description    : Sets the NVIC’s interrupt pending bit.
+* Input          : - NVIC_IRQChannel: specifies the interrupt pending bit to Set.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel)
+{
+  /* Check the parameters */
+  assert(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
+  
+  *(u32*)0xE000EF00 = (u32)NVIC_IRQChannel;
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_ClearIRQChannelPendingBit
+* Description    : Clears the NVIC’s interrupt pending bit.
+* Input          : - NVIC_IRQChannel: specifies the interrupt pending bit to clear.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel)
+{
+  /* Check the parameters */
+  assert(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
+  
+  NVIC->Clear[(NVIC_IRQChannel >> 0x05)] = (u32)0x01 << (NVIC_IRQChannel & (u32)0x1F);
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_GetCurrentActiveHandler
+* Description    : Returns the current active Handler (IRQ Channel and
+*                  SystemHandler) identifier.
+* Input          : None
+* Output         : None
+* Return         : Active Handler Identifier.
+*******************************************************************************/
+u16 NVIC_GetCurrentActiveHandler(void)
+{
+  return ((u16)(SCB->IRQControlState & (u32)0x3FF));
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_GetIRQChannelActiveBitStatus
+* Description    : Checks whether the specified IRQ Channel active bit is set
+*                  or not.
+* Input          : - NVIC_IRQChannel: specifies the interrupt active bit to check.
+* Output         : None
+* Return         : The new state of IRQ Channel active bit(SET or RESET).
+*******************************************************************************/
+ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel)
+{
+  ITStatus activeirqstatus = RESET;
+  u32 tmp = 0x00;
+
+  /* Check the parameters */
+  assert(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
+  
+  tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F));
+
+  if (((NVIC->Active[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp )
+  {
+    activeirqstatus = SET;
+  }
+  else
+  {
+    activeirqstatus = RESET;
+  }
+  return activeirqstatus;
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_GetCPUID
+* Description    : Returns the ID number, the version number and the implementation
+*                  details of the Cortex-M3 core.
+* Input          : None
+* Output         : None
+* Return         : CPU ID.
+*******************************************************************************/
+u32 NVIC_GetCPUID(void)
+{
+  return (SCB->CPUID);
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_SetVectorTable
+* Description    : Sets the vector table location and Offset.
+* Input          : - NVIC_VectTab: specifies if the vector table is in RAM or
+*                    code memory.
+*                    This parameter can be one of the following values:
+*                       - NVIC_VectTab_RAM
+*                       - NVIC_VectTab_FLASH
+*                  - Offset: Vector Table base offset field.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset)
+{ 
+  /* Check the parameters */
+  assert(IS_NVIC_VECTTAB(NVIC_VectTab));
+  assert(IS_NVIC_OFFSET(Offset));  
+   
+  SCB->ExceptionTableOffset = (((u32)Offset << 0x07) & (u32)0x1FFFFF80);
+
+  SCB->ExceptionTableOffset |= NVIC_VectTab;
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_GenerateSystemReset
+* Description    : Generates a system reset.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_GenerateSystemReset(void)
+{
+  SCB->AIRC = AIRC_VECTKEY_MASK | (u32)0x04;
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_GenerateCoreReset
+* Description    : Generates a Core (Core + NVIC) reset.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_GenerateCoreReset(void)
+{
+  SCB->AIRC = AIRC_VECTKEY_MASK | (u32)0x01;
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_SystemLPConfig
+* Description    : Selects the condition for the system to enter low power mode.
+* Input          : - LowPowerMode: Specifies the new mode for the system to enter
+*                    low power mode.
+*                    This parameter can be one of the following values:
+*                       - NVIC_LP_SEVONPEND
+*                       - NVIC_LP_SLEEPDEEP
+*                       - NVIC_LP_SLEEPONEXIT
+*                  - NewState: new state of LP condition.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_NVIC_LP(LowPowerMode));
+  assert(IS_FUNCTIONAL_STATE(NewState));  
+  
+  if (NewState != DISABLE)
+  {
+    SCB->SysCtrl |= LowPowerMode;
+  }
+  else
+  {
+    SCB->SysCtrl &= (u32)(~(u32)LowPowerMode);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_SystemHandlerConfig
+* Description    : Enables or disables the specified System Handlers.
+* Input          : - SystemHandler: specifies the system handler to be enabled
+*                    or disabled.
+*                    This parameter can be one of the following values:
+*                       - SystemHandler_MemoryManage
+*                       - SystemHandler_BusFault
+*                       - SystemHandler_UsageFault
+*                  - NewState: new state of  specified System Handlers.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState)
+{
+  u32 tmpreg = 0x00;
+
+  /* Check the parameters */
+  assert(IS_CONFIG_SYSTEM_HANDLER(SystemHandler));
+  assert(IS_FUNCTIONAL_STATE(NewState)); 
+  
+  tmpreg =  (u32)0x01 << (SystemHandler & (u32)0x1F);
+
+  if (NewState != DISABLE)
+  {
+    SCB->SysHandlerCtrl |= tmpreg;
+  }
+  else
+  {
+    SCB->SysHandlerCtrl &= ~tmpreg;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_SystemHandlerPriorityConfig
+* Description    : Configures the specified System Handlers priority.
+* Input          : - SystemHandler: specifies the system handler to be
+*                    enabled or disabled.
+*                    This parameter can be one of the following values:
+*                       - SystemHandler_MemoryManage
+*                       - SystemHandler_BusFault
+*                       - SystemHandler_UsageFault
+*                       - SystemHandler_SVCall
+*                       - SystemHandler_DebugMonitor
+*                       - SystemHandler_PSV
+*                       - SystemHandler_SysTick
+*                  - SystemHandlerPreemptionPriority: new priority group of the
+*                    specified system handlers.
+*                  - SystemHandlerSubPriority: new sub priority of the specified
+*                    system handlers.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority,
+                                      u8 SystemHandlerSubPriority)
+{
+  u32 tmp1 = 0x00, tmp2 = 0xFF, handlermask = 0x00;
+  u32 tmppriority = 0x00;
+
+  /* Check the parameters */
+  assert(IS_PRIORITY_SYSTEM_HANDLER(SystemHandler));
+  assert(IS_NVIC_PREEMPTION_PRIORITY(SystemHandlerPreemptionPriority));  
+  assert(IS_NVIC_SUB_PRIORITY(SystemHandlerSubPriority));
+    
+  tmppriority = (0x700 - (SCB->AIRC & (u32)0x700))>> 0x08;
+  tmp1 = (0x4 - tmppriority);
+  tmp2 = tmp2 >> tmppriority;
+    
+  tmppriority = (u32)SystemHandlerPreemptionPriority << tmp1;
+  tmppriority |=  SystemHandlerSubPriority & tmp2;
+
+  tmppriority = tmppriority << 0x04;
+  tmp1 = SystemHandler & (u32)0xC0;
+  tmp1 = tmp1 >> 0x06; 
+  tmp2 = (SystemHandler >> 0x08) & (u32)0x03;
+  tmppriority = tmppriority << (tmp2 * 0x08);
+  handlermask = (u32)0xFF << (tmp2 * 0x08);
+  
+  SCB->SystemPriority[tmp1] &= ~handlermask;
+  SCB->SystemPriority[tmp1] |= tmppriority;
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_GetSystemHandlerPendingBitStatus
+* Description    : Checks whether the specified System handlers pending bit is
+*                  set or not.
+* Input          : - SystemHandler: specifies the system handler pending bit to
+*                    check.
+*                    This parameter can be one of the following values:
+*                       - SystemHandler_MemoryManage
+*                       - SystemHandler_BusFault
+*                       - SystemHandler_SVCall
+* Output         : None
+* Return         : The new state of System Handler pending bit(SET or RESET).
+*******************************************************************************/
+ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler)
+{
+  ITStatus bitstatus  = RESET;
+  u32 tmp = 0x00, tmppos = 0x00;
+
+  /* Check the parameters */
+  assert(IS_GET_PENDING_SYSTEM_HANDLER(SystemHandler));
+  
+  tmppos = (SystemHandler >> 0x0A);
+  tmppos &= (u32)0x0F;
+
+  tmppos = (u32)0x01 << tmppos;
+
+  tmp = SCB->SysHandlerCtrl & tmppos;
+
+  if (tmp == tmppos)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_SetSystemHandlerPendingBit
+* Description    : Sets System Handler pending bit.
+* Input          : - SystemHandler: specifies the system handler pending bit
+*                    to be set.
+*                    This parameter can be one of the following values:
+*                       - SystemHandler_NMI
+*                       - SystemHandler_PSV
+*                       - SystemHandler_SysTick
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler)
+{
+  u32 tmp = 0x00;
+
+  /* Check the parameters */
+  assert(IS_SET_PENDING_SYSTEM_HANDLER(SystemHandler));
+  
+  /* Get the System Handler pending bit position */
+  tmp = SystemHandler & (u32)0x1F;
+  /* Set the corresponding System Handler pending bit */
+  SCB->IRQControlState |= ((u32)0x01 << tmp);
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_ClearSystemHandlerPendingBit
+* Description    : Clears System Handler pending bit.
+* Input          : - SystemHandler: specifies the system handler pending bit to
+*                    be clear.
+*                    This parameter can be one of the following values:
+*                       - SystemHandler_PSV
+*                       - SystemHandler_SysTick
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler)
+{
+  u32 tmp = 0x00;
+
+  /* Check the parameters */
+  assert(IS_CLEAR_SYSTEM_HANDLER(SystemHandler));
+  
+  /* Get the System Handler pending bit position */
+  tmp = SystemHandler & (u32)0x1F;
+  /* Clear the corresponding System Handler pending bit */
+  SCB->IRQControlState |= ((u32)0x01 << (tmp - 0x01));
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_GetSystemHandlerActiveBitStatus
+* Description    : Checks whether the specified System handlers active bit is
+*                  set or not.
+* Input          : - SystemHandler: specifies the system handler active bit to
+*                    check.
+*                    This parameter can be one of the following values:
+*                       - SystemHandler_MemoryManage
+*                       - SystemHandler_BusFault
+*                       - SystemHandler_UsageFault
+*                       - SystemHandler_SVCall
+*                       - SystemHandler_DebugMonitor
+*                       - SystemHandler_PSV
+*                       - SystemHandler_SysTick
+* Output         : None
+* Return         : The new state of System Handler active bit(SET or RESET).
+*******************************************************************************/
+ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler)
+{
+  ITStatus bitstatus  = RESET;
+
+  u32 tmp = 0x00, tmppos = 0x00;
+
+  /* Check the parameters */
+  assert(IS_GET_ACTIVE_SYSTEM_HANDLER(SystemHandler));
+  
+  tmppos = (SystemHandler >> 0x0E) & (u32)0x0F;
+
+  tmppos = (u32)0x01 << tmppos;
+
+  tmp = SCB->SysHandlerCtrl & tmppos;
+
+  if (tmp == tmppos)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_GetFaultHandlerSources
+* Description    : Returns the system fault handlers sources.
+* Input          : - SystemHandler: specifies the system handler to get its fault
+*                    sources.
+*                    This parameter can be one of the following values:
+*                       - SystemHandler_HardFault
+*                       - SystemHandler_MemoryManage
+*                       - SystemHandler_BusFault
+*                       - SystemHandler_UsageFault
+*                       - SystemHandler_DebugMonitor
+* Output         : None
+* Return         : Source of the fault handler.
+*******************************************************************************/
+u32 NVIC_GetFaultHandlerSources(u32 SystemHandler)
+{
+  u32 faultsources = 0x00;
+  u32 tmpreg = 0x00, tmppos = 0x00;
+
+  /* Check the parameters */
+  assert(IS_FAULT_SOURCE_SYSTEM_HANDLER(SystemHandler));
+  
+  tmpreg = (SystemHandler >> 0x12) & (u32)0x03;
+  tmppos = (SystemHandler >> 0x14) & (u32)0x03;
+
+  if (tmpreg == 0x00)
+  {
+    faultsources = SCB->HardFaultStatus;
+  }
+  else if (tmpreg == 0x01)
+  {
+    faultsources = SCB->ConfigFaultStatus >> (tmppos * 0x08);
+    if (tmppos != 0x02)
+    {
+      faultsources &= (u32)0x0F;
+    }
+    else
+    {
+      faultsources &= (u32)0xFF;
+    }
+  }
+  else
+  {
+    faultsources = SCB->DebugFaultStatus;
+  }
+  return faultsources;
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_GetFaultAddress
+* Description    : Returns the address of the location that generated a fault
+*                  handler.
+* Input          : - SystemHandler: specifies the system handler to get its
+*                    fault address.
+*                    This parameter can be one of the following values:
+*                       - SystemHandler_MemoryManage
+*                       - SystemHandler_BusFault
+* Output         : None
+* Return         : Fault address.
+*******************************************************************************/
+u32 NVIC_GetFaultAddress(u32 SystemHandler)
+{
+  u32 faultaddress = 0x00;
+  u32 tmp = 0x00;
+
+  /* Check the parameters */
+  assert(IS_FAULT_ADDRESS_SYSTEM_HANDLER(SystemHandler));
+  
+  tmp = (SystemHandler >> 0x16) & (u32)0x01;
+
+  if (tmp == 0x00)
+  {
+    faultaddress = SCB->MemoryManageFaultAddr;
+  }
+  else
+  {
+    faultaddress = SCB->BusFaultAddr;
+  }
+  return faultaddress;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_pwr.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_pwr.c
new file mode 100644
index 0000000..26b6dcc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_pwr.c
@@ -0,0 +1,283 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_pwr.c
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file provides all the PWR firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_pwr.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* --------- PWR registers bit address in the alias region ---------- */
+#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+/* Alias word address of DBP bit */
+#define CR_OFFSET                (PWR_OFFSET + 0x00)
+#define DBP_BitNumber            0x08
+#define CR_DBP_BB                (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BitNumber           0x04
+#define CR_PVDE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+/* Alias word address of EWUP bit */
+#define CSR_OFFSET               (PWR_OFFSET + 0x04)
+#define EWUP_BitNumber           0x08
+#define CSR_EWUP_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
+
+/* ------------------ PWR registers bit mask ------------------------ */
+/* CR register bit mask */
+#define CR_PDDS_Set              ((u32)0x00000002)
+#define CR_DS_Mask               ((u32)0xFFFFFFFC)
+#define CR_CWUF_Set              ((u32)0x00000004)
+#define CR_PLS_Mask              ((u32)0xFFFFFF1F)
+
+/* --------- Cortex System Control register bit mask ---------------- */
+/* Cortex System Control register address */
+#define SCB_SysCtrl              ((u32)0xE000ED10)
+/* SLEEPDEEP bit mask */
+#define SysCtrl_SLEEPDEEP_Set    ((u32)0x00000004)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : PWR_DeInit
+* Description    : Deinitializes the PWR peripheral registers to their default
+*                  reset values.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void PWR_DeInit(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
+}
+
+/*******************************************************************************
+* Function Name  : PWR_BackupAccessCmd
+* Description    : Enables or disables access to the RTC and backup registers.
+* Input          : - NewState: new state of the access to the RTC and backup
+*                    registers. This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void PWR_BackupAccessCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  *(vu32 *) CR_DBP_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name  : PWR_PVDCmd
+* Description    : Enables or disables the Power Voltage Detector(PVD).
+* Input          : - NewState: new state of the PVD.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void PWR_PVDCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  *(vu32 *) CR_PVDE_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name  : PWR_PVDLevelConfig
+* Description    : Configures the value detected by the Power Voltage Detector(PVD).
+* Input          : - PWR_PVDLevel: specifies the PVD detection level
+*                    This parameter can be one of the following values:
+*                       - PWR_PVDLevel_2V2: PVD detection level set to 2.2V
+*                       - PWR_PVDLevel_2V3: PVD detection level set to 2.3V
+*                       - PWR_PVDLevel_2V4: PVD detection level set to 2.4V
+*                       - PWR_PVDLevel_2V5: PVD detection level set to 2.5V
+*                       - PWR_PVDLevel_2V6: PVD detection level set to 2.6V
+*                       - PWR_PVDLevel_2V7: PVD detection level set to 2.7V
+*                       - PWR_PVDLevel_2V8: PVD detection level set to 2.8V
+*                       - PWR_PVDLevel_2V9: PVD detection level set to 2.9V
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void PWR_PVDLevelConfig(u32 PWR_PVDLevel)
+{
+  u32 tmpreg = 0;
+
+  /* Check the parameters */
+  assert(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+
+  tmpreg = PWR->CR;
+
+  /* Clear PLS[7:5] bits */
+  tmpreg &= CR_PLS_Mask;
+
+  /* Set PLS[7:5] bits according to PWR_PVDLevel value */
+  tmpreg |= PWR_PVDLevel;
+
+  /* Store the new value */
+  PWR->CR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name  : PWR_WakeUpPinCmd
+* Description    : Enables or disables the WakeUp Pin functionality.
+* Input          : - NewState: new state of the WakeUp Pin functionality.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void PWR_WakeUpPinCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  *(vu32 *) CSR_EWUP_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name  : PWR_EnterSTOPMode
+* Description    : Enters STOP mode.
+* Input          : - PWR_Regulator: specifies the regulator state in STOP mode.
+*                    This parameter can be one of the following values:
+*                       - PWR_Regulator_ON: STOP mode with regulator ON
+*                       - PWR_Regulator_LowPower: STOP mode with
+*                         regulator in low power mode
+*                  - PWR_STOPEntry: specifies if STOP mode in entered with WFI or 
+*                    WFE instruction.
+*                    This parameter can be one of the following values:
+*                       - PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
+*                       - PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void PWR_EnterSTOPMode(u32 PWR_Regulator, u8 PWR_STOPEntry)
+{
+  u32 tmpreg = 0;
+
+  /* Check the parameters */
+  assert(IS_PWR_REGULATOR(PWR_Regulator));
+  assert(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+  
+  /* Select the regulator state in STOP mode ---------------------------------*/
+  tmpreg = PWR->CR;
+
+  /* Clear PDDS and LPDS bits */
+  tmpreg &= CR_DS_Mask;
+
+  /* Set LPDS bit according to PWR_Regulator value */
+  tmpreg |= PWR_Regulator;
+
+  /* Store the new value */
+  PWR->CR = tmpreg;
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  *(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
+  
+  /* Select STOP mode entry --------------------------------------------------*/
+  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+  {   
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE();
+  }
+}
+
+/*******************************************************************************
+* Function Name  : PWR_EnterSTANDBYMode
+* Description    : Enters STANDBY mode.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void PWR_EnterSTANDBYMode(void)
+{
+  /* Clear Wake-up flag */
+  PWR->CR |= CR_CWUF_Set;
+
+  /* Select STANDBY mode */
+  PWR->CR |= CR_PDDS_Set;
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  *(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
+
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+/*******************************************************************************
+* Function Name  : PWR_GetFlagStatus
+* Description    : Checks whether the specified PWR flag is set or not.
+* Input          : - PWR_FLAG: specifies the flag to check.
+*                    This parameter can be one of the following values:
+*                       - PWR_FLAG_WU: Wake Up flag
+*                       - PWR_FLAG_SB: StandBy flag
+*                       - PWR_FLAG_PVDO: PVD Output
+* Output         : None
+* Return         : The new state of PWR_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert(IS_PWR_GET_FLAG(PWR_FLAG));
+  
+  if ((PWR->CSR & PWR_FLAG) != (u32)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : PWR_ClearFlag
+* Description    : Clears the PWR's pending flags.
+* Input          : - PWR_FLAG: specifies the flag to clear.
+*                    This parameter can be one of the following values:
+*                       - PWR_FLAG_WU: Wake Up flag
+*                       - PWR_FLAG_SB: StandBy flag
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void PWR_ClearFlag(u32 PWR_FLAG)
+{
+  /* Check the parameters */
+  assert(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+         
+  PWR->CR |=  PWR_FLAG << 2;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_rcc.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_rcc.c
new file mode 100644
index 0000000..1cd00bd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_rcc.c
@@ -0,0 +1,1069 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_rcc.c
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file provides all the RCC firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+/* Alias word address of HSION bit */
+#define CR_OFFSET                 (RCC_OFFSET + 0x00)
+#define HSION_BitNumber           0x00
+#define CR_HSION_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
+
+/* Alias word address of PLLON bit */
+#define PLLON_BitNumber           0x18
+#define CR_PLLON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
+
+/* Alias word address of CSSON bit */
+#define CSSON_BitNumber           0x13
+#define CR_CSSON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
+
+/* --- CFGR Register ---*/
+/* Alias word address of USBPRE bit */
+#define CFGR_OFFSET               (RCC_OFFSET + 0x04)
+#define USBPRE_BitNumber          0x16
+#define CFGR_USBPRE_BB            (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
+
+/* --- BDCR Register ---*/
+/* Alias word address of RTCEN bit */
+#define BDCR_OFFSET               (RCC_OFFSET + 0x20)
+#define RTCEN_BitNumber           0x0F
+#define BDCR_RTCEN_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
+
+/* Alias word address of BDRST bit */
+#define BDRST_BitNumber           0x10
+#define BDCR_BDRST_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
+
+/* --- CSR Register ---*/
+/* Alias word address of LSION bit */
+#define CSR_OFFSET                (RCC_OFFSET + 0x24)
+#define LSION_BitNumber           0x00
+#define CSR_LSION_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
+
+/* ---------------------- RCC registers bit mask ------------------------ */
+/* CR register bit mask */
+#define CR_HSEBYP_Reset           ((u32)0xFFFBFFFF)
+#define CR_HSEBYP_Set             ((u32)0x00040000)
+#define CR_HSEON_Reset            ((u32)0xFFFEFFFF)
+#define CR_HSEON_Set              ((u32)0x00010000)
+#define CR_HSITRIM_Mask           ((u32)0xFFFFFF07)
+
+/* CFGR register bit mask */
+#define CFGR_PLL_Mask             ((u32)0xFFC0FFFF)
+#define CFGR_PLLMull_Mask         ((u32)0x003C0000)
+#define CFGR_PLLSRC_Mask          ((u32)0x00010000)
+#define CFGR_PLLXTPRE_Mask        ((u32)0x00020000)
+#define CFGR_SWS_Mask             ((u32)0x0000000C)
+#define CFGR_SW_Mask              ((u32)0xFFFFFFFC)
+#define CFGR_HPRE_Reset_Mask      ((u32)0xFFFFFF0F)
+#define CFGR_HPRE_Set_Mask        ((u32)0x000000F0)
+#define CFGR_PPRE1_Reset_Mask     ((u32)0xFFFFF8FF)
+#define CFGR_PPRE1_Set_Mask       ((u32)0x00000700)
+#define CFGR_PPRE2_Reset_Mask     ((u32)0xFFFFC7FF)
+#define CFGR_PPRE2_Set_Mask       ((u32)0x00003800)
+#define CFGR_ADCPRE_Reset_Mask    ((u32)0xFFFF3FFF)
+#define CFGR_ADCPRE_Set_Mask      ((u32)0x0000C000)
+
+/* CSR register bit mask */
+#define CSR_RVMF_Set              ((u32)0x01000000)
+
+/* RCC Flag Mask */
+#define FLAG_Mask                 ((u8)0x1F)
+
+/* Typical Value of the HSI in Hz */
+#define HSI_Value                 ((u32)8000000)
+
+/* BDCR register base address */
+#define BDCR_BASE                 (PERIPH_BASE + BDCR_OFFSET)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static uc8 APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+static uc8 ADCPrescTable[4] = {2, 4, 6, 8};
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : RCC_DeInit
+* Description    : Deinitializes the RCC peripheral registers to their default
+*                  reset values.
+*                   - The HSITRIM[4:0] bits in RCC_CR register are not modified
+*                     by this function.
+*                   - The RCC_BDCR and RCC_CSR registers are not reset by this
+*                     function.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_DeInit(void)
+{
+  /* Disable APB2 Peripheral Reset */
+  RCC->APB2RSTR = 0x00000000;
+
+  /* Disable APB1 Peripheral Reset */
+  RCC->APB1RSTR = 0x00000000;
+
+  /* FLITF and SRAM Clock ON */
+  RCC->AHBENR = 0x00000014;
+
+  /* Disable APB2 Peripheral Clock */
+  RCC->APB2ENR = 0x00000000;
+
+  /* Disable APB1 Peripheral Clock */
+  RCC->APB1ENR = 0x00000000;
+
+  /* Set HSION bit */
+  RCC->CR |= (u32)0x00000001;
+
+  /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits*/
+  RCC->CFGR &= 0xF8FF0000;
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= 0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
+  RCC->CFGR &= 0xFF80FFFF;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+}
+
+/*******************************************************************************
+* Function Name  : RCC_HSEConfig
+* Description    : Configures the External High Speed oscillator (HSE).
+* Input          : - RCC_HSE: specifies the new state of the HSE.
+*                    This parameter can be one of the following values:
+*                       - RCC_HSE_OFF: HSE oscillator OFF
+*                       - RCC_HSE_ON: HSE oscillator ON
+*                       - RCC_HSE_Bypass: HSE oscillator bypassed with external
+*                         clock
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_HSEConfig(u32 RCC_HSE)
+{
+  /* Check the parameters */
+  assert(IS_RCC_HSE(RCC_HSE));
+
+  /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
+  /* Reset HSEON bit */
+  RCC->CR &= CR_HSEON_Reset;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= CR_HSEBYP_Reset;
+
+  /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
+  switch(RCC_HSE)
+  {
+    case RCC_HSE_ON:
+      /* Set HSEON bit */
+      RCC->CR |= CR_HSEON_Set;
+      break;
+      
+    case RCC_HSE_Bypass:
+      /* Set HSEBYP and HSEON bits */
+      RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
+      break;            
+      
+    default:
+      break;      
+  }
+}
+
+/*******************************************************************************
+* Function Name  : RCC_AdjustHSICalibrationValue
+* Description    : Adjusts the Internal High Speed oscillator (HSI) calibration
+*                  value.
+* Input          : - HSICalibrationValue: specifies the calibration trimming value.
+*                    This parameter must be a number between 0 and 0x1F.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue)
+{
+  u32 tmpreg = 0;
+
+  /* Check the parameters */
+  assert(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
+
+  tmpreg = RCC->CR;
+
+  /* Clear HSITRIM[7:3] bits */
+  tmpreg &= CR_HSITRIM_Mask;
+
+  /* Set the HSITRIM[7:3] bits according to HSICalibrationValue value */
+  tmpreg |= (u32)HSICalibrationValue << 3;
+
+  /* Store the new value */
+  RCC->CR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name  : RCC_HSICmd
+* Description    : Enables or disables the Internal High Speed oscillator (HSI).
+*                  HSI can not be stopped if it is used directly or through the 
+*                  PLL as system clock, or if a Flash programmation is on going.
+* Input          : - NewState: new state of the HSI.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_HSICmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  *(vu32 *) CR_HSION_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name  : RCC_PLLConfig
+* Description    : Configures the PLL clock source and multiplication factor.
+*                  This function must be used only when the PLL is disabled.
+* Input          : - RCC_PLLSource: specifies the PLL entry clock source.
+*                    This parameter can be one of the following values:
+*                       - RCC_PLLSource_HSI_Div2: HSI oscillator clock divided
+*                         by 2 selected as PLL clock entry
+*                       - RCC_PLLSource_HSE_Div1: HSE oscillator clock selected
+*                         as PLL clock entry
+*                       - RCC_PLLSource_HSE_Div2: HSE oscillator clock divided
+*                         by 2 selected as PLL clock entry
+*                  - RCC_PLLMul: specifies the PLL multiplication factor.
+*                    This parameter can be RCC_PLLMul_x where x:[2,16]
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul)
+{
+  u32 tmpreg = 0;
+
+  /* Check the parameters */
+  assert(IS_RCC_PLL_SOURCE(RCC_PLLSource));
+  assert(IS_RCC_PLL_MUL(RCC_PLLMul));
+
+  tmpreg = RCC->CFGR;
+
+  /* Clear PLLSRC, PLLXTPRE and PLLMUL[21:18] bits */
+  tmpreg &= CFGR_PLL_Mask;
+
+  /* Set the PLL configuration bits */
+  tmpreg |= RCC_PLLSource | RCC_PLLMul;
+
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name  : RCC_PLLCmd
+* Description    : Enables or disables the PLL.
+*                  The PLL can not be disabled if it is used as system clock.
+* Input          : - NewState: new state of the PLL.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_PLLCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  *(vu32 *) CR_PLLON_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name  : RCC_SYSCLKConfig
+* Description    : Configures the system clock (SYSCLK).
+* Input          : - RCC_SYSCLKSource: specifies the clock source used as system
+*                    clock. This parameter can be one of the following values:
+*                       - RCC_SYSCLKSource_HSI: HSI selected as system clock
+*                       - RCC_SYSCLKSource_HSE: HSE selected as system clock
+*                       - RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource)
+{
+  u32 tmpreg = 0;
+
+  /* Check the parameters */
+  assert(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
+
+  tmpreg = RCC->CFGR;
+
+  /* Clear SW[1:0] bits */
+  tmpreg &= CFGR_SW_Mask;
+
+  /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
+  tmpreg |= RCC_SYSCLKSource;
+
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name  : RCC_GetSYSCLKSource
+* Description    : Returns the clock source used as system clock.
+* Input          : None
+* Output         : None
+* Return         : The clock source used as system clock. The returned value can
+*                  be one of the following:
+*                       - 0x00: HSI used as system clock
+*                       - 0x04: HSE used as system clock
+*                       - 0x08: PLL used as system clock
+*******************************************************************************/
+u8 RCC_GetSYSCLKSource(void)
+{
+  return ((u8)(RCC->CFGR & CFGR_SWS_Mask));
+}
+
+/*******************************************************************************
+* Function Name  : RCC_HCLKConfig
+* Description    : Configures the AHB clock (HCLK).
+* Input          : - RCC_HCLK: defines the AHB clock. This clock is derived
+*                    from the system clock (SYSCLK).
+*                    This parameter can be one of the following values:
+*                       - RCC_SYSCLK_Div1: AHB clock = SYSCLK
+*                       - RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
+*                       - RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
+*                       - RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
+*                       - RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
+*                       - RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
+*                       - RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
+*                       - RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
+*                       - RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_HCLKConfig(u32 RCC_HCLK)
+{
+  u32 tmpreg = 0;
+
+  /* Check the parameters */
+  assert(IS_RCC_HCLK(RCC_HCLK));
+
+  tmpreg = RCC->CFGR;
+
+  /* Clear HPRE[7:4] bits */
+  tmpreg &= CFGR_HPRE_Reset_Mask;
+
+  /* Set HPRE[7:4] bits according to RCC_HCLK value */
+  tmpreg |= RCC_HCLK;
+
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name  : RCC_PCLK1Config
+* Description    : Configures the Low Speed APB clock (PCLK1).
+* Input          : - RCC_PCLK1: defines the APB1 clock. This clock is derived
+*                    from the AHB clock (HCLK).
+*                    This parameter can be one of the following values:
+*                       - RCC_HCLK_Div1: APB1 clock = HCLK
+*                       - RCC_HCLK_Div2: APB1 clock = HCLK/2
+*                       - RCC_HCLK_Div4: APB1 clock = HCLK/4
+*                       - RCC_HCLK_Div8: APB1 clock = HCLK/8
+*                       - RCC_HCLK_Div16: APB1 clock = HCLK/16
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_PCLK1Config(u32 RCC_PCLK1)
+{
+  u32 tmpreg = 0;
+
+  /* Check the parameters */
+  assert(IS_RCC_PCLK(RCC_PCLK1));
+
+  tmpreg = RCC->CFGR;
+
+  /* Clear PPRE1[10:8] bits */
+  tmpreg &= CFGR_PPRE1_Reset_Mask;
+
+  /* Set PPRE1[10:8] bits according to RCC_PCLK1 value */
+  tmpreg |= RCC_PCLK1;
+
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name  : RCC_PCLK2Config
+* Description    : Configures the High Speed APB clock (PCLK2).
+* Input          : - RCC_PCLK2: defines the APB2 clock. This clock is derived
+*                    from the AHB clock (HCLK).
+*                    This parameter can be one of the following values:
+*                       - RCC_HCLK_Div1: APB2 clock = HCLK
+*                       - RCC_HCLK_Div2: APB2 clock = HCLK/2
+*                       - RCC_HCLK_Div4: APB2 clock = HCLK/4
+*                       - RCC_HCLK_Div8: APB2 clock = HCLK/8
+*                       - RCC_HCLK_Div16: APB2 clock = HCLK/16
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_PCLK2Config(u32 RCC_PCLK2)
+{
+  u32 tmpreg = 0;
+
+  /* Check the parameters */
+  assert(IS_RCC_PCLK(RCC_PCLK2));
+
+  tmpreg = RCC->CFGR;
+
+  /* Clear PPRE2[13:11] bits */
+  tmpreg &= CFGR_PPRE2_Reset_Mask;
+
+  /* Set PPRE2[13:11] bits according to RCC_PCLK2 value */
+  tmpreg |= RCC_PCLK2 << 3;
+
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name  : RCC_ITConfig
+* Description    : Enables or disables the specified RCC interrupts.
+* Input          : - RCC_IT: specifies the RCC interrupt sources to be enabled
+*                    or disabled.
+*                    This parameter can be any combination of the following values:
+*                       - RCC_IT_LSIRDY: LSI ready interrupt
+*                       - RCC_IT_LSERDY: LSE ready interrupt
+*                       - RCC_IT_HSIRDY: HSI ready interrupt
+*                       - RCC_IT_HSERDY: HSE ready interrupt
+*                       - RCC_IT_PLLRDY: PLL ready interrupt
+*                  - NewState: new state of the specified RCC interrupts.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_RCC_IT(RCC_IT));
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
+    *(vu8 *) 0x40021009 |= RCC_IT;
+  }
+  else
+  {
+    /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
+    *(vu8 *) 0x40021009 &= ~(u32)RCC_IT;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : RCC_USBCLKConfig
+* Description    : Configures the USB clock (USBCLK).
+* Input          : - RCC_USBCLKSource: specifies the USB clock source. This clock
+*                    is derived from the PLL output.
+*                    This parameter can be one of the following values:
+*                       - RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5
+*                         selected as USB clock source
+*                       - RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB
+*                         clock source
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_USBCLKConfig(u32 RCC_USBCLKSource)
+{
+  /* Check the parameters */
+  assert(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
+
+  *(vu32 *) CFGR_USBPRE_BB = RCC_USBCLKSource;
+}
+
+/*******************************************************************************
+* Function Name  : RCC_ADCCLKConfig
+* Description    : Configures the ADC clock (ADCCLK).
+* Input          : - RCC_ADCCLK: defines the ADC clock. This clock is derived
+*                    from the APB2 clock (PCLK2).
+*                    This parameter can be one of the following values:
+*                       - RCC_PCLK2_Div2: ADC clock = PCLK2/2
+*                       - RCC_PCLK2_Div4: ADC clock = PCLK2/4
+*                       - RCC_PCLK2_Div6: ADC clock = PCLK2/6
+*                       - RCC_PCLK2_Div8: ADC clock = PCLK2/8
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_ADCCLKConfig(u32 RCC_ADCCLK)
+{
+  u32 tmpreg = 0;
+
+  /* Check the parameters */
+  assert(IS_RCC_ADCCLK(RCC_ADCCLK));
+
+  tmpreg = RCC->CFGR;
+
+  /* Clear ADCPRE[15:14] bits */
+  tmpreg &= CFGR_ADCPRE_Reset_Mask;
+
+  /* Set ADCPRE[15:14] bits according to RCC_ADCCLK value */
+  tmpreg |= RCC_ADCCLK;
+
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name  : RCC_LSEConfig
+* Description    : Configures the External Low Speed oscillator (LSE).
+* Input          : - RCC_LSE: specifies the new state of the LSE.
+*                    This parameter can be one of the following values:
+*                       - RCC_LSE_OFF: LSE oscillator OFF
+*                       - RCC_LSE_ON: LSE oscillator ON
+*                       - RCC_LSE_Bypass: LSE oscillator bypassed with external
+*                         clock
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_LSEConfig(u32 RCC_LSE)
+{
+  /* Check the parameters */
+  assert(IS_RCC_LSE(RCC_LSE));
+
+  /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
+  /* Reset LSEON bit */
+  *(vu8 *) BDCR_BASE = RCC_LSE_OFF;
+
+  /* Reset LSEBYP bit */
+  *(vu8 *) BDCR_BASE = RCC_LSE_OFF;
+
+  /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
+  switch(RCC_LSE)
+  {
+    case RCC_LSE_ON:
+      /* Set LSEON bit */
+      *(vu8 *) BDCR_BASE = RCC_LSE_ON;
+      break;
+      
+    case RCC_LSE_Bypass:
+      /* Set LSEBYP and LSEON bits */
+      *(vu8 *) BDCR_BASE = RCC_LSE_Bypass | RCC_LSE_ON;
+      break;            
+      
+    default:
+      break;      
+  }
+}
+
+/*******************************************************************************
+* Function Name  : RCC_LSICmd
+* Description    : Enables or disables the Internal Low Speed oscillator (LSI).
+*                  LSI can not be disabled if the IWDG is running.
+* Input          : - NewState: new state of the LSI.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_LSICmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  *(vu32 *) CSR_LSION_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name  : RCC_RTCCLKConfig
+* Description    : Configures the RTC clock (RTCCLK).
+*                  Once the RTC clock is selected it can’t be changed unless the
+*                  Backup domain is reset.
+* Input          : - RCC_RTCCLKSource: specifies the RTC clock source.
+*                    This parameter can be one of the following values:
+*                       - RCC_RTCCLKSource_LSE: LSE oscillator clock used as RTC
+*                         clock
+*                       - RCC_RTCCLKSource_LSI: LSI oscillator clock used as RTC
+*                         clock
+*                       - RCC_RTCCLKSource_HSE_Div128: HSE oscillator clock divided
+*                         by 128 used as RTC clock
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource)
+{
+  /* Check the parameters */
+  assert(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
+
+  /* Select the RTC clock source */
+  RCC->BDCR |= RCC_RTCCLKSource;
+}
+
+/*******************************************************************************
+* Function Name  : RCC_RTCCLKCmd
+* Description    : Enables or disables the RTC clock.
+*                  This function must be used only after the RTC clock was
+*                  selected using the RCC_RTCCLKConfig function.
+* Input          : - NewState: new state of the RTC clock.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_RTCCLKCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  *(vu32 *) BDCR_RTCEN_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name  : RCC_GetClocksFreq
+* Description    : Returns the frequencies of different on chip clocks.
+* Input          : - RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which
+*                    will hold the clocks frequencies.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
+{
+  u32 tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & CFGR_SWS_Mask;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      RCC_Clocks->SYSCLK_Frequency = HSI_Value;
+      break;
+
+    case 0x04:  /* HSE used as system clock */
+      RCC_Clocks->SYSCLK_Frequency = HSE_Value;
+      break;
+
+    case 0x08:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
+      pllmull = ( pllmull >> 18) + 2;
+
+      pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
+
+      if (pllsource == 0x00)
+      {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
+      }
+      else
+      {/* HSE selected as PLL clock entry */
+
+        if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET)
+        {/* HSE oscillator clock divided by 2 */
+
+          RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
+        }
+        else
+        {
+          RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
+        }
+      }
+      break;
+
+    default:
+      RCC_Clocks->SYSCLK_Frequency = HSI_Value;
+      break;
+  }
+
+  /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
+  /* Get HCLK prescaler */
+  tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
+  tmp = tmp >> 4;
+  presc = APBAHBPrescTable[tmp];
+
+  /* HCLK clock frequency */
+  RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
+
+  /* Get PCLK1 prescaler */
+  tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
+  tmp = tmp >> 8;
+  presc = APBAHBPrescTable[tmp];
+
+  /* PCLK1 clock frequency */
+  RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+
+  /* Get PCLK2 prescaler */
+  tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
+  tmp = tmp >> 11;
+  presc = APBAHBPrescTable[tmp];
+
+  /* PCLK2 clock frequency */
+  RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+
+  /* Get ADCCLK prescaler */
+  tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
+  tmp = tmp >> 14;
+  presc = ADCPrescTable[tmp];
+
+  /* ADCCLK clock frequency */
+  RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
+}
+
+/*******************************************************************************
+* Function Name  : RCC_AHBPeriphClockCmd
+* Description    : Enables or disables the AHB peripheral clock.
+* Input          : - RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
+*                    This parameter can be any combination of the following values:
+*                       - RCC_AHBPeriph_DMA
+*                       - RCC_AHBPeriph_SRAM
+*                       - RCC_AHBPeriph_FLITF
+*                    SRAM and FLITF clock can be disabled only during sleep mode.
+*                  - NewState: new state of the specified peripheral clock.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->AHBENR |= RCC_AHBPeriph;
+  }
+  else
+  {
+    RCC->AHBENR &= ~RCC_AHBPeriph;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : RCC_APB2PeriphClockCmd
+* Description    : Enables or disables the High Speed APB (APB2) peripheral clock.
+* Input          : - RCC_APB2Periph: specifies the APB2 peripheral to gates its
+*                    clock.
+*                    This parameter can be any combination of the following values:
+*                       - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB
+*                         RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE
+*                         RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1
+*                         RCC_APB2Periph_SPI1, RCC_APB2Periph_USART1, RCC_APB2Periph_ALL
+*                  - NewState: new state of the specified peripheral clock.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->APB2ENR |= RCC_APB2Periph;
+  }
+  else
+  {
+    RCC->APB2ENR &= ~RCC_APB2Periph;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : RCC_APB1PeriphClockCmd
+* Description    : Enables or disables the Low Speed APB (APB1) peripheral clock.
+* Input          : - RCC_APB1Periph: specifies the APB1 peripheral to gates its
+*                    clock.
+*                    This parameter can be any combination of the following values:
+*                       - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4
+*                         RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_USART2
+*                         RCC_APB1Periph_USART3, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2
+*                         RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP
+*                         RCC_APB1Periph_PWR, RCC_APB1Periph_ALL
+*                  - NewState: new state of the specified peripheral clock.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->APB1ENR |= RCC_APB1Periph;
+  }
+  else
+  {
+    RCC->APB1ENR &= ~RCC_APB1Periph;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : RCC_APB2PeriphResetCmd
+* Description    : Forces or releases High Speed APB (APB2) peripheral reset.
+* Input          : - RCC_APB2Periph: specifies the APB2 peripheral to reset.
+*                    This parameter can be any combination of the following values:
+*                       - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB
+*                         RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE
+*                         RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1
+*                         RCC_APB2Periph_SPI1, RCC_APB2Periph_USART1, RCC_APB2Periph_ALL
+*                  - NewState: new state of the specified peripheral reset.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->APB2RSTR |= RCC_APB2Periph;
+  }
+  else
+  {
+    RCC->APB2RSTR &= ~RCC_APB2Periph;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : RCC_APB1PeriphResetCmd
+* Description    : Forces or releases Low Speed APB (APB1) peripheral reset.
+* Input          : - RCC_APB1Periph: specifies the APB1 peripheral to reset.
+*                    This parameter can be any combination of the following values:
+*                       - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4
+*                         RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_USART2
+*                         RCC_APB1Periph_USART3, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2
+*                         RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP
+*                         RCC_APB1Periph_PWR, RCC_APB1Periph_ALL
+*                  - NewState: new state of the specified peripheral clock.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->APB1RSTR |= RCC_APB1Periph;
+  }
+  else
+  {
+    RCC->APB1RSTR &= ~RCC_APB1Periph;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : RCC_BackupResetCmd
+* Description    : Forces or releases the Backup domain reset.
+* Input          : - NewState: new state of the Backup domain reset.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_BackupResetCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  *(vu32 *) BDCR_BDRST_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name  : RCC_ClockSecuritySystemCmd
+* Description    : Enables or disables the Clock Security System.
+* Input          : - NewState: new state of the Clock Security System..
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  *(vu32 *) CR_CSSON_BB = (u32)NewState;
+}
+
+/*******************************************************************************
+* Function Name  : RCC_MCOConfig
+* Description    : Selects the clock source to output on MCO pin.
+* Input          : - RCC_MCO: specifies the clock source to output.
+*                    This parameter can be one of the following values:
+*                       - RCC_MCO_NoClock: No clock selected
+*                       - RCC_MCO_SYSCLK: System clock selected
+*                       - RCC_MCO_HSI: HSI oscillator clock selected
+*                       - RCC_MCO_HSE: HSE oscillator clock selected
+*                       - RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_MCOConfig(u8 RCC_MCO)
+{
+  /* Check the parameters */
+  assert(IS_RCC_MCO(RCC_MCO));
+
+  /* Perform Byte access to MCO[26:24] bits to select the MCO source */
+  *(vu8 *) 0x40021007 = RCC_MCO;
+}
+
+/*******************************************************************************
+* Function Name  : RCC_GetFlagStatus
+* Description    : Checks whether the specified RCC flag is set or not.
+* Input          : - RCC_FLAG: specifies the flag to check.
+*                    This parameter can be one of the following values:
+*                       - RCC_FLAG_HSIRDY: HSI oscillator clock ready
+*                       - RCC_FLAG_HSERDY: HSE oscillator clock ready
+*                       - RCC_FLAG_PLLRDY: PLL clock ready
+*                       - RCC_FLAG_LSERDY: LSE oscillator clock ready
+*                       - RCC_FLAG_LSIRDY: LSI oscillator clock ready
+*                       - RCC_FLAG_PINRST: Pin reset
+*                       - RCC_FLAG_PORRST: POR/PDR reset
+*                       - RCC_FLAG_SFTRST: Software reset
+*                       - RCC_FLAG_IWDGRST: Independent Watchdog reset
+*                       - RCC_FLAG_WWDGRST: Window Watchdog reset
+*                       - RCC_FLAG_LPWRRST: Low Power reset
+* Output         : None
+* Return         : The new state of RCC_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG)
+{
+  u32 tmp = 0;
+  u32 statusreg = 0;
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert(IS_RCC_FLAG(RCC_FLAG));
+
+  /* Get the RCC register index */
+  tmp = RCC_FLAG >> 5;
+
+  if (tmp == 1)               /* The flag to check is in CR register */
+  {
+    statusreg = RCC->CR;
+  }
+  else if (tmp == 2)          /* The flag to check is in BDCR register */
+  {
+    statusreg = RCC->BDCR;
+  }
+  else                       /* The flag to check is in CSR register */
+  {
+    statusreg = RCC->CSR;
+  }
+
+  /* Get the flag position */
+  tmp = RCC_FLAG & FLAG_Mask;
+
+  if ((statusreg & ((u32)1 << tmp)) != (u32)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : RCC_ClearFlag
+* Description    : Clears the RCC reset flags.
+*                  The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
+*                  RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,
+*                  RCC_FLAG_LPWRRST
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_ClearFlag(void)
+{
+  /* Set RVMF bit to clear the reset flags */
+  RCC->CSR |= CSR_RVMF_Set;
+}
+
+/*******************************************************************************
+* Function Name  : RCC_GetITStatus
+* Description    : Checks whether the specified RCC interrupt has occurred or not.
+* Input          : - RCC_IT: specifies the RCC interrupt source to check.
+*                    This parameter can be one of the following values:
+*                       - RCC_IT_LSIRDY: LSI ready interrupt
+*                       - RCC_IT_LSERDY: LSE ready interrupt
+*                       - RCC_IT_HSIRDY: HSI ready interrupt
+*                       - RCC_IT_HSERDY: HSE ready interrupt
+*                       - RCC_IT_PLLRDY: PLL ready interrupt
+*                       - RCC_IT_CSS: Clock Security System interrupt
+* Output         : None
+* Return         : The new state of RCC_IT (SET or RESET).
+*******************************************************************************/
+ITStatus RCC_GetITStatus(u8 RCC_IT)
+{
+  ITStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert(IS_RCC_GET_IT(RCC_IT));
+
+  /* Check the status of the specified RCC interrupt */
+  if ((RCC->CIR & RCC_IT) != (u32)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  /* Return the RCC_IT status */
+  return  bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : RCC_ClearITPendingBit
+* Description    : Clears the RCC’s interrupt pending bits.
+* Input          : - RCC_IT: specifies the interrupt pending bit to clear.
+*                    This parameter can be any combination of the following values:
+*                       - RCC_IT_LSIRDY: LSI ready interrupt
+*                       - RCC_IT_LSERDY: LSE ready interrupt
+*                       - RCC_IT_HSIRDY: HSI ready interrupt
+*                       - RCC_IT_HSERDY: HSE ready interrupt
+*                       - RCC_IT_PLLRDY: PLL ready interrupt
+*                       - RCC_IT_CSS: Clock Security System interrupt
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RCC_ClearITPendingBit(u8 RCC_IT)
+{
+  /* Check the parameters */
+  assert(IS_RCC_CLEAR_IT(RCC_IT));
+
+  /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
+     pending bits */
+  *(vu8 *) 0x4002100A = RCC_IT;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_rtc.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_rtc.c
new file mode 100644
index 0000000..2163791
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_rtc.c
@@ -0,0 +1,342 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_rtc.c
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file provides all the RTC firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_rtc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define CRL_CNF_Set      ((u16)0x0010)      /* Configuration Flag Enable Mask */
+#define CRL_CNF_Reset    ((u16)0xFFEF)      /* Configuration Flag Disable Mask */
+#define RTC_LSB_Mask     ((u32)0x0000FFFF)  /* RTC LSB Mask */
+#define RTC_MSB_Mask     ((u32)0xFFFF0000)  /* RTC MSB Mask */
+#define PRLH_MSB_Mask    ((u32)0x000F0000)  /* RTC Prescaler MSB Mask */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : RTC_ITConfig
+* Description    : Enables or disables the specified RTC interrupts.
+* Input          : - RTC_IT: specifies the RTC interrupts sources to be enabled
+*                    or disabled.
+*                    This parameter can be any combination of the following values:
+*                       - RTC_IT_OW: Overflow interrupt
+*                       - RTC_IT_ALR: Alarm interrupt
+*                       - RTC_IT_SEC: Second interrupt
+*                  - NewState: new state of the specified RTC interrupts.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_RTC_IT(RTC_IT));  
+  assert(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    RTC->CRH |= RTC_IT;
+  }
+  else
+  {
+    RTC->CRH &= (u16)~RTC_IT;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : RTC_EnterConfigMode
+* Description    : Enters the RTC configuration mode.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RTC_EnterConfigMode(void)
+{
+  /* Set the CNF flag to enter in the Configuration Mode */
+  RTC->CRL |= CRL_CNF_Set;
+}
+
+/*******************************************************************************
+* Function Name  : RTC_ExitConfigMode
+* Description    : Exits from the RTC configuration mode.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RTC_ExitConfigMode(void)
+{
+  /* Reset the CNF flag to exit from the Configuration Mode */
+  RTC->CRL &= CRL_CNF_Reset;
+}
+
+/*******************************************************************************
+* Function Name  : RTC_GetCounter
+* Description    : Gets the RTC counter value.
+* Input          : None
+* Output         : None
+* Return         : RTC counter value.
+*******************************************************************************/
+u32 RTC_GetCounter(void)
+{
+  u16 tmp = 0;
+  tmp = RTC->CNTL;
+
+  return (((u32)RTC->CNTH << 16 ) | tmp) ;
+}
+
+/*******************************************************************************
+* Function Name  : RTC_SetCounter
+* Description    : Sets the RTC counter value.
+* Input          : - CounterValue: RTC counter new value.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RTC_SetCounter(u32 CounterValue)
+{ 
+  RTC_EnterConfigMode();
+
+  /* Set RTC COUNTER MSB word */
+  RTC->CNTH = (CounterValue & RTC_MSB_Mask) >> 16;
+  /* Set RTC COUNTER LSB word */
+  RTC->CNTL = (CounterValue & RTC_LSB_Mask);
+
+  RTC_ExitConfigMode();
+}
+
+/*******************************************************************************
+* Function Name  : RTC_GetPrescaler
+* Description    : Gets the RTC prescaler value.
+* Input          : None
+* Output         : None
+* Return         : RTC prescaler value.
+*******************************************************************************/
+u32 RTC_GetPrescaler(void)
+{
+  u32 tmp = 0x00;
+
+  tmp = ((u32)RTC->PRLH & (u32)0x000F) << 0x10;
+  tmp |= RTC->PRLL;
+
+  return tmp;
+}
+
+/*******************************************************************************
+* Function Name  : RTC_SetPrescaler
+* Description    : Sets the RTC prescaler value.
+* Input          : - PrescalerValue: RTC prescaler new value.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RTC_SetPrescaler(u32 PrescalerValue)
+{
+  /* Check the parameters */
+  assert(IS_RTC_PRESCALER(PrescalerValue));
+  
+  RTC_EnterConfigMode();
+
+  /* Set RTC PRESCALER MSB word */
+  RTC->PRLH = (PrescalerValue & PRLH_MSB_Mask) >> 0x10;
+  /* Set RTC PRESCALER LSB word */
+  RTC->PRLL = (PrescalerValue & RTC_LSB_Mask);
+
+  RTC_ExitConfigMode();
+}
+
+/*******************************************************************************
+* Function Name  : RTC_SetAlarm
+* Description    : Sets the RTC alarm value.
+* Input          : - AlarmValue: RTC alarm new value.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RTC_SetAlarm(u32 AlarmValue)
+{  
+  RTC_EnterConfigMode();
+
+  /* Set the ALARM MSB word */
+  RTC->ALRH = (AlarmValue & RTC_MSB_Mask) >> 16;
+  /* Set the ALARM LSB word */
+  RTC->ALRL = (AlarmValue & RTC_LSB_Mask);
+
+  RTC_ExitConfigMode();
+}
+
+/*******************************************************************************
+* Function Name  : RTC_GetDivider
+* Description    : Gets the RTC divider value.
+* Input          : None
+* Output         : None
+* Return         : RTC Divider value.
+*******************************************************************************/
+u32 RTC_GetDivider(void)
+{
+  u32 tmp = 0x00;
+
+  tmp = ((u32)RTC->DIVH & (u32)0x000F) << 0x10;
+  tmp |= RTC->DIVL;
+
+  return tmp;
+}
+
+/*******************************************************************************
+* Function Name  : RTC_WaitForLastTask
+* Description    : Waits until last write operation on RTC registers has finished.
+*                  This function must be called before any write to RTC registers.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RTC_WaitForLastTask(void)
+{
+  /* Loop until RTOFF flag is set */
+  while ((RTC->CRL & RTC_FLAG_RTOFF) == (u16)RESET)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : RTC_WaitForSynchro
+* Description    : Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
+*                  are synchronized with RTC APB clock.
+*                  This function must be called before any read operation after
+*                  an APB reset or an APB clock stop.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RTC_WaitForSynchro(void)
+{
+  /* Clear RSF flag */
+  RTC->CRL &= (u16)~RTC_FLAG_RSF;
+
+  /* Loop until RSF flag is set */
+  while ((RTC->CRL & RTC_FLAG_RSF) == (u16)RESET)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : RTC_GetFlagStatus
+* Description    : Checks whether the specified RTC flag is set or not.
+* Input          : - RTC_FLAG: specifies the flag to check.
+*                    This parameter can be one the following values:
+*                       - RTC_FLAG_RTOFF: RTC Operation OFF flag
+*                       - RTC_FLAG_RSF: Registers Synchronized flag
+*                       - RTC_FLAG_OW: Overflow flag
+*                       - RTC_FLAG_ALR: Alarm flag
+*                       - RTC_FLAG_SEC: Second flag
+* Output         : None
+* Return         : The new state of RTC_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert(IS_RTC_GET_FLAG(RTC_FLAG)); 
+  
+  if ((RTC->CRL & RTC_FLAG) != (u16)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : RTC_ClearFlag
+* Description    : Clears the RTC’s pending flags.
+* Input          : - RTC_FLAG: specifies the flag to clear.
+*                    This parameter can be any combination of the following values:
+*                       - RTC_FLAG_RSF: Registers Synchronized flag. This flag
+*                         is cleared only after an APB reset or an APB Clock stop.
+*                       - RTC_FLAG_OW: Overflow flag
+*                       - RTC_FLAG_ALR: Alarm flag
+*                       - RTC_FLAG_SEC: Second flag
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RTC_ClearFlag(u16 RTC_FLAG)
+{
+  /* Check the parameters */
+  assert(IS_RTC_CLEAR_FLAG(RTC_FLAG)); 
+    
+  /* Clear the coressponding RTC flag */
+  RTC->CRL &= (u16)~RTC_FLAG;
+}
+
+/*******************************************************************************
+* Function Name  : RTC_GetITStatus
+* Description    : Checks whether the specified RTC interrupt has occured or not.
+* Input          : - RTC_IT: specifies the RTC interrupts sources to check.
+*                    This parameter can be one of the following values:
+*                       - RTC_IT_OW: Overflow interrupt
+*                       - RTC_IT_ALR: Alarm interrupt
+*                       - RTC_IT_SEC: Second interrupt
+* Output         : None
+* Return         : The new state of the RTC_IT (SET or RESET).
+*******************************************************************************/
+ITStatus RTC_GetITStatus(u16 RTC_IT)
+{
+  ITStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert(IS_RTC_GET_IT(RTC_IT)); 
+  
+  bitstatus = (ITStatus)((RTC->CRL & RTC_IT) != (u16)RESET);
+
+  if (((RTC->CRH & RTC_IT) != (u16)RESET) && bitstatus)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : RTC_ClearITPendingBit
+* Description    : Clears the RTC’s interrupt pending bits.
+* Input          : - RTC_IT: specifies the interrupt pending bit to clear.
+*                    This parameter can be any combination of the following values:
+*                       - RTC_IT_OW: Overflow interrupt
+*                       - RTC_IT_ALR: Alarm interrupt
+*                       - RTC_IT_SEC: Second interrupt
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void RTC_ClearITPendingBit(u16 RTC_IT)
+{
+  /* Check the parameters */
+  assert(IS_RTC_IT(RTC_IT));  
+  
+  /* Clear the coressponding RTC pending bit */
+  RTC->CRL &= (u16)~RTC_IT;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_sdio.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_sdio.c
new file mode 100644
index 0000000..04c876e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_sdio.c
@@ -0,0 +1,806 @@
+/**
+  ******************************************************************************
+  * @file  stm32f10x_sdio.c
+  * @author  MCD Application Team
+  * @version  V3.0.0
+  * @date  04/06/2009
+  * @brief  This file provides all the SDIO firmware functions.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
© COPYRIGHT 2009 STMicroelectronics

+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_sdio.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup SDIO 
+  * @brief SDIO driver modules
+  * @{
+  */ 
+
+/** @defgroup SDIO_Private_TypesDefinitions
+  * @{
+  */ 
+
+/* ------------ SDIO registers bit address in the alias region ----------- */
+#define SDIO_OFFSET                (SDIO_BASE - PERIPH_BASE)
+
+/* --- CLKCR Register ---*/
+
+/* Alias word address of CLKEN bit */
+#define CLKCR_OFFSET              (SDIO_OFFSET + 0x04)
+#define CLKEN_BitNumber           0x08
+#define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
+
+/* --- CMD Register ---*/
+
+/* Alias word address of SDIOSUSPEND bit */
+#define CMD_OFFSET                (SDIO_OFFSET + 0x0C)
+#define SDIOSUSPEND_BitNumber     0x0B
+#define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
+
+/* Alias word address of ENCMDCOMPL bit */
+#define ENCMDCOMPL_BitNumber      0x0C
+#define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
+
+/* Alias word address of NIEN bit */
+#define NIEN_BitNumber            0x0D
+#define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
+
+/* Alias word address of ATACMD bit */
+#define ATACMD_BitNumber          0x0E
+#define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
+
+/* --- DCTRL Register ---*/
+
+/* Alias word address of DMAEN bit */
+#define DCTRL_OFFSET              (SDIO_OFFSET + 0x2C)
+#define DMAEN_BitNumber           0x03
+#define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
+
+/* Alias word address of RWSTART bit */
+#define RWSTART_BitNumber         0x08
+#define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
+
+/* Alias word address of RWSTOP bit */
+#define RWSTOP_BitNumber          0x09
+#define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
+
+/* Alias word address of RWMOD bit */
+#define RWMOD_BitNumber           0x0A
+#define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
+
+/* Alias word address of SDIOEN bit */
+#define SDIOEN_BitNumber          0x0B
+#define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
+
+/* ---------------------- SDIO registers bit mask ------------------------ */
+
+/* --- CLKCR Register ---*/
+
+/* CLKCR register clear mask */
+#define CLKCR_CLEAR_MASK         ((uint32_t)0xFFFF8100) 
+
+/* --- PWRCTRL Register ---*/
+
+/* SDIO PWRCTRL Mask */
+#define PWR_PWRCTRL_MASK         ((uint32_t)0xFFFFFFFC)
+
+/* --- DCTRL Register ---*/
+
+/* SDIO DCTRL Clear Mask */
+#define DCTRL_CLEAR_MASK         ((uint32_t)0xFFFFFF08)
+
+/* --- CMD Register ---*/
+
+/* CMD Register clear mask */
+#define CMD_CLEAR_MASK           ((uint32_t)0xFFFFF800)
+
+/* SDIO RESP Registers Address */
+#define SDIO_RESP_ADDR           ((uint32_t)(SDIO_BASE + 0x14))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the SDIO peripheral registers to their default
+  *   reset values.
+  * @param  None
+  * @retval : None
+  */
+void SDIO_DeInit(void)
+{
+  SDIO->POWER = 0x00000000;
+  SDIO->CLKCR = 0x00000000;
+  SDIO->ARG = 0x00000000;
+  SDIO->CMD = 0x00000000;
+  SDIO->DTIMER = 0x00000000;
+  SDIO->DLEN = 0x00000000;
+  SDIO->DCTRL = 0x00000000;
+  SDIO->ICR = 0x00C007FF;
+  SDIO->MASK = 0x00000000;
+}
+
+/**
+  * @brief  Initializes the SDIO peripheral according to the specified 
+  *   parameters in the SDIO_InitStruct.
+  * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure 
+  *   that contains the configuration information for the SDIO 
+  *   peripheral.
+  * @retval : None
+  */
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
+{
+  uint32_t tmpreg = 0;
+    
+  /* Check the parameters */
+  assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
+  assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
+  assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
+  assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
+  assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); 
+   
+/*---------------------------- SDIO CLKCR Configuration ------------------------*/  
+  /* Get the SDIO CLKCR value */
+  tmpreg = SDIO->CLKCR;
+  
+  /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
+  tmpreg &= CLKCR_CLEAR_MASK;
+  
+  /* Set CLKDIV bits according to SDIO_ClockDiv value */
+  /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
+  /* Set BYPASS bit according to SDIO_ClockBypass value */
+  /* Set WIDBUS bits according to SDIO_BusWide value */
+  /* Set NEGEDGE bits according to SDIO_ClockEdge value */
+  /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
+  tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv  | SDIO_InitStruct->SDIO_ClockPowerSave |
+             SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
+             SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); 
+  
+  /* Write to SDIO CLKCR */
+  SDIO->CLKCR = tmpreg;
+}
+
+/**
+  * @brief  Fills each SDIO_InitStruct member with its default value.
+  * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which 
+  *   will be initialized.
+  * @retval : None
+  */
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
+{
+  /* SDIO_InitStruct members default value */
+  SDIO_InitStruct->SDIO_ClockDiv = 0x00;
+  SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
+  SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
+  SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
+  SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
+  SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
+}
+
+/**
+  * @brief  Enables or disables the SDIO Clock.
+  * @param NewState: new state of the SDIO Clock.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void SDIO_ClockCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Sets the power status of the controller.
+  * @param SDIO_PowerState: new state of the Power state. 
+  *   This parameter can be one of the following values:
+  * @arg SDIO_PowerState_OFF
+  * @arg SDIO_PowerState_ON
+  * @retval : None
+  */
+void SDIO_SetPowerState(uint32_t SDIO_PowerState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
+  
+  SDIO->POWER &= PWR_PWRCTRL_MASK;
+  SDIO->POWER |= SDIO_PowerState;
+}
+
+/**
+  * @brief  Gets the power status of the controller.
+  * @param  None
+  * @retval : Power status of the controller. The returned value can
+  *   be one of the following:
+  * - 0x00: Power OFF
+  * - 0x02: Power UP
+  * - 0x03: Power ON 
+  */
+uint32_t SDIO_GetPowerState(void)
+{
+  return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
+}
+
+/**
+  * @brief  Enables or disables the SDIO interrupts.
+  * @param SDIO_IT: specifies the SDIO interrupt sources to be 
+  *   enabled or disabled.
+  *   This parameter can be one or a combination of the following values:
+  * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  * @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  * @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  * @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  * @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                        bus mode interrupt
+  * @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  * @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
+  * @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
+  * @arg SDIO_IT_RXACT:    Data receive in progress interrupt
+  * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  * @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
+  * @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
+  * @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  * @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
+  * @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  * @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
+  * @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 
+  *                        interrupt
+  * @param NewState: new state of the specified SDIO interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None 
+  */
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_IT(SDIO_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the SDIO interrupts */
+    SDIO->MASK |= SDIO_IT;
+  }
+  else
+  {
+    /* Disable the SDIO interrupts */
+    SDIO->MASK &= ~SDIO_IT;
+  } 
+}
+
+/**
+  * @brief  Enables or disables the SDIO DMA request.
+  * @param NewState: new state of the selected SDIO DMA request.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void SDIO_DMACmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Initializes the SDIO Command according to the specified 
+  *   parameters in the SDIO_CmdInitStruct and send the command.
+  * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef 
+  *   structure that contains the configuration information 
+  *   for the SDIO command.
+  * @retval : None
+  */
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
+  assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
+  assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
+  assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
+  
+/*---------------------------- SDIO ARG Configuration ------------------------*/
+  /* Set the SDIO Argument value */
+  SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
+  
+/*---------------------------- SDIO CMD Configuration ------------------------*/  
+  /* Get the SDIO CMD value */
+  tmpreg = SDIO->CMD;
+  /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
+  tmpreg &= CMD_CLEAR_MASK;
+  /* Set CMDINDEX bits according to SDIO_CmdIndex value */
+  /* Set WAITRESP bits according to SDIO_Response value */
+  /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
+  /* Set CPSMEN bits according to SDIO_CPSM value */
+  tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
+           | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
+  
+  /* Write to SDIO CMD */
+  SDIO->CMD = tmpreg;
+}
+
+/**
+  * @brief  Fills each SDIO_CmdInitStruct member with its default value.
+  * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef 
+  *   structure which will be initialized.
+  * @retval : None
+  */
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
+{
+  /* SDIO_CmdInitStruct members default value */
+  SDIO_CmdInitStruct->SDIO_Argument = 0x00;
+  SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
+  SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
+  SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
+}
+
+/**
+  * @brief  Returns command index of last command for which response 
+  *   received.
+  * @param  None
+  * @retval : Returns the command index of the last command response received.
+  */
+uint8_t SDIO_GetCommandResponse(void)
+{
+  return (uint8_t)(SDIO->RESPCMD);
+}
+
+/**
+  * @brief  Returns response received from the card for the last command.
+  * @param SDIO_RESP: Specifies the SDIO response register. 
+  *   This parameter can be one of the following values:
+  * @arg SDIO_RESP1: Response Register 1
+  * @arg SDIO_RESP2: Response Register 2
+  * @arg SDIO_RESP3: Response Register 3
+  * @arg SDIO_RESP4: Response Register 4
+  * @retval : The Corresponding response register value.
+  */
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_RESP(SDIO_RESP));
+  
+  return (*(__IO uint32_t *)(SDIO_RESP_ADDR + SDIO_RESP)); 
+}
+
+/**
+  * @brief  Initializes the SDIO data path according to the specified 
+  *   parameters in the SDIO_DataInitStruct.
+  * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef 
+  *   structure that contains the configuration information 
+  *   for the SDIO command.
+  * @retval : None
+  */
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
+  assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
+  assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
+  assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
+  assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
+
+/*---------------------------- SDIO DTIMER Configuration ---------------------*/
+  /* Set the SDIO Data TimeOut value */
+  SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
+
+/*---------------------------- SDIO DLEN Configuration -----------------------*/
+  /* Set the SDIO DataLength value */
+  SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
+
+/*---------------------------- SDIO DCTRL Configuration ----------------------*/  
+  /* Get the SDIO DCTRL value */
+  tmpreg = SDIO->DCTRL;
+  /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
+  tmpreg &= DCTRL_CLEAR_MASK;
+  /* Set DEN bit according to SDIO_DPSM value */
+  /* Set DTMODE bit according to SDIO_TransferMode value */
+  /* Set DTDIR bit according to SDIO_TransferDir value */
+  /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
+  tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
+           | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
+
+  /* Write to SDIO DCTRL */
+  SDIO->DCTRL = tmpreg;
+}
+
+/**
+  * @brief  Fills each SDIO_DataInitStruct member with its default value.
+  * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef 
+  *   structure which will be initialized.
+  * @retval : None
+  */
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+{
+  /* SDIO_DataInitStruct members default value */
+  SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
+  SDIO_DataInitStruct->SDIO_DataLength = 0x00;
+  SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
+  SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
+  SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;  
+  SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
+}
+
+/**
+  * @brief  Returns number of remaining data bytes to be transferred.
+  * @param  None
+  * @retval : Number of remaining data bytes to be transferred
+  */
+uint32_t SDIO_GetDataCounter(void)
+{ 
+  return SDIO->DCOUNT;
+}
+
+/**
+  * @brief  Read one data word from Rx FIFO.
+  * @param  None
+  * @retval : Data received
+  */
+uint32_t SDIO_ReadData(void)
+{ 
+  return SDIO->FIFO;
+}
+
+/**
+  * @brief  Write one data word to Tx FIFO.
+  * @param Data: 32-bit data word to write.
+  * @retval : None
+  */
+void SDIO_WriteData(uint32_t Data)
+{ 
+  SDIO->FIFO = Data;
+}
+
+/**
+  * @brief  Returns the number of words left to be written to or read
+  *   from FIFO.	
+  * @param  None
+  * @retval : Remaining number of words.
+  */
+uint32_t SDIO_GetFIFOCount(void)
+{ 
+  return SDIO->FIFOCNT;
+}
+
+/**
+  * @brief  Starts the SD I/O Read Wait operation.	
+  * @param NewState: new state of the Start SDIO Read Wait operation. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void SDIO_StartSDIOReadWait(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
+}
+
+/**
+  * @brief  Stops the SD I/O Read Wait operation.	
+  * @param NewState: new state of the Stop SDIO Read Wait operation. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void SDIO_StopSDIOReadWait(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
+}
+
+/**
+  * @brief  Sets one of the two options of inserting read wait interval.
+  * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
+  *   This parametre can be:
+  * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
+  * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
+  * @retval : None
+  */
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
+  
+  *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
+}
+
+/**
+  * @brief  Enables or disables the SD I/O Mode Operation.
+  * @param NewState: new state of SDIO specific operation. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void SDIO_SetSDIOOperation(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the SD I/O Mode suspend command sending.
+  * @param NewState: new state of the SD I/O Mode suspend command.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the command completion signal.
+  * @param NewState: new state of command completion signal. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void SDIO_CommandCompletionCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the CE-ATA interrupt.
+  * @param NewState: new state of CE-ATA interrupt. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void SDIO_CEATAITCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
+}
+
+/**
+  * @brief  Sends CE-ATA command (CMD61).
+  * @param NewState: new state of CE-ATA command. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void SDIO_SendCEATACmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Checks whether the specified SDIO flag is set or not.
+  * @param SDIO_FLAG: specifies the flag to check. 
+  *   This parameter can be one of the following values:
+  * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+  * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+  * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+  * @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
+  * @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
+  * @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
+  * @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide 
+  *                          bus mode.
+  * @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  * @arg SDIO_FLAG_CMDACT:   Command transfer in progress
+  * @arg SDIO_FLAG_TXACT:    Data transmit in progress
+  * @arg SDIO_FLAG_RXACT:    Data receive in progress
+  * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+  * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
+  * @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
+  * @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
+  * @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
+  * @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
+  * @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
+  * @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
+  * @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
+  * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+  * @retval : The new state of SDIO_FLAG (SET or RESET).
+  */
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
+{ 
+  FlagStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_SDIO_FLAG(SDIO_FLAG));
+  
+  if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the SDIO's pending flags.
+  * @param SDIO_FLAG: specifies the flag to clear.  
+  *   This parameter can be one or a combination of the following values:
+  * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+  * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+  * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+  * @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
+  * @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
+  * @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
+  * @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide 
+  *                          bus mode
+  * @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  * @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
+  * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+  * @retval : None
+  */
+void SDIO_ClearFlag(uint32_t SDIO_FLAG)
+{ 
+  /* Check the parameters */
+  assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
+   
+  SDIO->ICR = SDIO_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified SDIO interrupt has occurred or not.
+  * @param SDIO_IT: specifies the SDIO interrupt source to check. 
+  *   This parameter can be one of the following values:
+  * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  * @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  * @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  * @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  * @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                        bus mode interrupt
+  * @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  * @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
+  * @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
+  * @arg SDIO_IT_RXACT:    Data receive in progress interrupt
+  * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  * @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
+  * @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
+  * @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  * @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
+  * @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  * @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
+  * @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 
+  *                        interrupt
+  * @retval : The new state of SDIO_IT (SET or RESET).
+  */
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
+{ 
+  ITStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_SDIO_GET_IT(SDIO_IT));
+  if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)  
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the SDIO’s interrupt pending bits.
+  * @param SDIO_IT: specifies the interrupt pending bit to clear. 
+  *   This parameter can be one or a combination of the following values:
+  * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  * @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  * @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  * @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  * @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                        bus mode interrupt
+  * @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
+  * @retval : None
+  */
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
+{ 
+  /* Check the parameters */
+  assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
+   
+  SDIO->ICR = SDIO_IT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_spi.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_spi.c
new file mode 100644
index 0000000..8aadc09
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_spi.c
@@ -0,0 +1,836 @@
+/**
+  ******************************************************************************
+  * @file  stm32f10x_spi.c
+  * @author  MCD Application Team
+  * @version  V3.0.0
+  * @date  04/06/2009
+  * @brief  This file provides all the SPI firmware functions.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
© COPYRIGHT 2009 STMicroelectronics

+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_spi.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup SPI 
+  * @brief SPI driver modules
+  * @{
+  */ 
+
+/** @defgroup SPI_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup SPI_Private_Defines
+  * @{
+  */
+
+/* SPI SPE mask */
+#define CR1_SPE_Set          ((uint16_t)0x0040)
+#define CR1_SPE_Reset        ((uint16_t)0xFFBF)
+
+/* I2S I2SE mask */
+#define I2SCFGR_I2SE_Set     ((uint16_t)0x0400)
+#define I2SCFGR_I2SE_Reset   ((uint16_t)0xFBFF)
+
+/* SPI CRCNext mask */
+#define CR1_CRCNext_Set      ((uint16_t)0x1000)
+
+/* SPI CRCEN mask */
+#define CR1_CRCEN_Set        ((uint16_t)0x2000)
+#define CR1_CRCEN_Reset      ((uint16_t)0xDFFF)
+
+/* SPI SSOE mask */
+#define CR2_SSOE_Set         ((uint16_t)0x0004)
+#define CR2_SSOE_Reset       ((uint16_t)0xFFFB)
+
+/* SPI registers Masks */
+#define CR1_CLEAR_Mask       ((uint16_t)0x3040)
+#define I2SCFGR_CLEAR_Mask   ((uint16_t)0xF040)
+
+/* SPI or I2S mode selection masks */
+#define SPI_Mode_Select      ((uint16_t)0xF7FF)
+#define I2S_Mode_Select      ((uint16_t)0x0800) 
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the SPIx peripheral registers to their default
+  *   reset values (Affects also the I2Ss).
+  * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @retval : None
+  */
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  
+  switch (*(uint32_t*)&SPIx)
+  {
+    case SPI1_BASE:
+      /* Enable SPI1 reset state */
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
+      /* Release SPI1 from reset state */
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
+      break;
+    case SPI2_BASE:
+      /* Enable SPI2 reset state */
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
+      /* Release SPI2 from reset state */
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
+      break;
+    case SPI3_BASE:
+      /* Enable SPI3 reset state */
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
+      /* Release SPI3 from reset state */
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  Initializes the SPIx peripheral according to the specified 
+  *   parameters in the SPI_InitStruct.
+  * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
+  *   contains the configuration information for the specified
+  *   SPI peripheral.
+  * @retval : None
+  */
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
+{
+  uint16_t tmpreg = 0;
+  
+  /* check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));   
+  
+  /* Check the SPI parameters */
+  assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
+  assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
+  assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
+  assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
+  assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
+  assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
+  assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
+  assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
+  assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
+/*---------------------------- SPIx CR1 Configuration ------------------------*/
+  /* Get the SPIx CR1 value */
+  tmpreg = SPIx->CR1;
+  /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
+  tmpreg &= CR1_CLEAR_Mask;
+  /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
+     master/salve mode, CPOL and CPHA */
+  /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
+  /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
+  /* Set LSBFirst bit according to SPI_FirstBit value */
+  /* Set BR bits according to SPI_BaudRatePrescaler value */
+  /* Set CPOL bit according to SPI_CPOL value */
+  /* Set CPHA bit according to SPI_CPHA value */
+  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
+                  SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |  
+                  SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |  
+                  SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
+  /* Write to SPIx CR1 */
+  SPIx->CR1 = tmpreg;
+  
+  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+  SPIx->I2SCFGR &= SPI_Mode_Select;		
+/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+  /* Write to SPIx CRCPOLY */
+  SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
+}
+
+/**
+  * @brief  Initializes the SPIx peripheral according to the specified 
+  *   parameters in the I2S_InitStruct.
+  * @param SPIx: where x can be  2 or 3 to select the SPI peripheral
+  *   (configured in I2S mode).
+  * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
+  *   contains the configuration information for the specified
+  *   SPI peripheral configured in I2S mode.
+  * @retval : None
+  */
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
+{
+  uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+  uint32_t tmp = 0;
+  RCC_ClocksTypeDef RCC_Clocks;
+   
+  /* Check the I2S parameters */
+  assert_param(IS_SPI_23_PERIPH(SPIx));
+  assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
+  assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
+  assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
+  assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
+  assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
+  assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));  
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
+  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+  SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; 
+  SPIx->I2SPR = 0x0002;
+  
+  /* Get the I2SCFGR register value */
+  tmpreg = SPIx->I2SCFGR;
+  
+  /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+  if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
+  {
+    i2sodd = (uint16_t)0;
+    i2sdiv = (uint16_t)2;   
+  }
+  /* If the requested audio frequency is not the default, compute the prescaler */
+  else
+  {
+    /* Check the frame length (For the Prescaler computing) */
+    if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
+    {
+      /* Packet length is 16 bits */
+      packetlength = 1;
+    }
+    else
+    {
+      /* Packet length is 32 bits */
+      packetlength = 2;
+    }
+    /* Get System Clock frequency */
+    RCC_GetClocksFreq(&RCC_Clocks);
+    
+    /* Compute the Real divider depending on the MCLK output state with a flaoting point */
+    if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
+    {
+      /* MCLK output is enabled */
+      tmp = (uint16_t)(((10 * RCC_Clocks.SYSCLK_Frequency) / (256 * I2S_InitStruct->I2S_AudioFreq)) + 5);
+    }
+    else
+    {
+      /* MCLK output is disabled */
+      tmp = (uint16_t)(((10 * RCC_Clocks.SYSCLK_Frequency) / (32 * packetlength * I2S_InitStruct->I2S_AudioFreq)) + 5);
+    }
+    
+    /* Remove the flaoting point */
+    tmp = tmp/10;  
+      
+    /* Check the parity of the divider */
+    i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+   
+    /* Compute the i2sdiv prescaler */
+    i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+   
+    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+    i2sodd = (uint16_t) (i2sodd << 8);
+  }
+  
+  /* Test if the divider is 1 or 0 */
+  if ((i2sdiv < 2) || (i2sdiv > 0xFF))
+  {
+    /* Set the default values */
+    i2sdiv = 2;
+    i2sodd = 0;
+  }
+  /* Write to SPIx I2SPR register the computed value */
+  SPIx->I2SPR = (uint16_t)(i2sdiv | i2sodd | I2S_InitStruct->I2S_MCLKOutput);  
+ 
+  /* Configure the I2S with the SPI_InitStruct values */
+  tmpreg |= (uint16_t)(I2S_Mode_Select | I2S_InitStruct->I2S_Mode | \
+                  I2S_InitStruct->I2S_Standard | I2S_InitStruct->I2S_DataFormat | \
+                  I2S_InitStruct->I2S_CPOL);
+ 
+  /* Write to SPIx I2SCFGR */
+  SPIx->I2SCFGR = tmpreg;
+}
+
+/**
+  * @brief  Fills each SPI_InitStruct member with its default value.
+  * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure
+  *   which will be initialized.
+  * @retval : None
+  */
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
+{
+/*--------------- Reset SPI init structure parameters values -----------------*/
+  /* Initialize the SPI_Direction member */
+  SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+  /* initialize the SPI_Mode member */
+  SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
+  /* initialize the SPI_DataSize member */
+  SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
+  /* Initialize the SPI_CPOL member */
+  SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
+  /* Initialize the SPI_CPHA member */
+  SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
+  /* Initialize the SPI_NSS member */
+  SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
+  /* Initialize the SPI_BaudRatePrescaler member */
+  SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+  /* Initialize the SPI_FirstBit member */
+  SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
+  /* Initialize the SPI_CRCPolynomial member */
+  SPI_InitStruct->SPI_CRCPolynomial = 7;
+}
+
+/**
+  * @brief  Fills each I2S_InitStruct member with its default value.
+  * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure
+  *   which will be initialized.
+  * @retval : None
+  */
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
+{
+/*--------------- Reset I2S init structure parameters values -----------------*/
+  /* Initialize the I2S_Mode member */
+  I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
+  
+  /* Initialize the I2S_Standard member */
+  I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
+  
+  /* Initialize the I2S_DataFormat member */
+  I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
+  
+  /* Initialize the I2S_MCLKOutput member */
+  I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
+  
+  /* Initialize the I2S_AudioFreq member */
+  I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
+  
+  /* Initialize the I2S_CPOL member */
+  I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
+}
+
+/**
+  * @brief  Enables or disables the specified SPI peripheral.
+  * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param NewState: new state of the SPIx peripheral. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI peripheral */
+    SPIx->CR1 |= CR1_SPE_Set;
+  }
+  else
+  {
+    /* Disable the selected SPI peripheral */
+    SPIx->CR1 &= CR1_SPE_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified SPI peripheral (in I2S mode).
+  * @param SPIx: where x can be 2 or 3 to select the SPI peripheral.
+  * @param NewState: new state of the SPIx peripheral. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_23_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI peripheral (in I2S mode) */
+    SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
+  }
+  else
+  {
+    /* Disable the selected SPI peripheral (in I2S mode) */
+    SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified SPI/I2S interrupts.
+  * @param SPIx: where x can be :
+  *   1, 2 or 3 in SPI mode 
+  *   2 or 3 in I2S mode
+  * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be 
+  *   enabled or disabled. 
+  *   This parameter can be one of the following values:
+  * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
+  * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
+  * @arg SPI_I2S_IT_ERR: Error interrupt mask
+  * @param NewState: new state of the specified SPI/I2S interrupt.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
+{
+  uint16_t itpos = 0, itmask = 0 ;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
+  /* Get the SPI/I2S IT index */
+  itpos = SPI_I2S_IT >> 4;
+  /* Set the IT mask */
+  itmask = (uint16_t)((uint16_t)1 << itpos);
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI/I2S interrupt */
+    SPIx->CR2 |= itmask;
+  }
+  else
+  {
+    /* Disable the selected SPI/I2S interrupt */
+    SPIx->CR2 &= (uint16_t)~itmask;
+  }
+}
+
+/**
+  * @brief  Enables or disables the SPIx/I2Sx DMA interface.
+  * @param SPIx: where x can be :
+  *   1, 2 or 3 in SPI mode 
+  *   2 or 3 in I2S mode
+  * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request 
+  *   to be enabled or disabled. 
+  *   This parameter can be any combination of the following values:
+  * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
+  * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
+  * @param NewState: new state of the selected SPI/I2S DMA transfer 
+  *   request.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI/I2S DMA requests */
+    SPIx->CR2 |= SPI_I2S_DMAReq;
+  }
+  else
+  {
+    /* Disable the selected SPI/I2S DMA requests */
+    SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
+  }
+}
+
+/**
+  * @brief  Transmits a Data through the SPIx/I2Sx peripheral.
+  * @param SPIx: where x can be :
+  *   1, 2 or 3 in SPI mode 
+  *   2 or 3 in I2S mode
+  * @param Data : Data to be transmitted..
+  * @retval : None
+  */
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  
+  /* Write in the DR register the data to be sent */
+  SPIx->DR = Data;
+}
+
+/**
+  * @brief  Returns the most recent received data by the SPIx/I2Sx peripheral. 
+  * @param SPIx: where x can be :
+  *   1, 2 or 3 in SPI mode 
+  *   2 or 3 in I2S mode
+  * @retval : The value of the received data.
+  */
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  
+  /* Return the data in the DR register */
+  return SPIx->DR;
+}
+
+/**
+  * @brief  Configures internally by software the NSS pin for the selected 
+  *   SPI.
+  * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
+  *   This parameter can be one of the following values:
+  * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
+  * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
+  * @retval : None
+  */
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
+  if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
+  {
+    /* Set NSS pin internally by software */
+    SPIx->CR1 |= SPI_NSSInternalSoft_Set;
+  }
+  else
+  {
+    /* Reset NSS pin internally by software */
+    SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the SS output for the selected SPI.
+  * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param NewState: new state of the SPIx SS output. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI SS output */
+    SPIx->CR2 |= CR2_SSOE_Set;
+  }
+  else
+  {
+    /* Disable the selected SPI SS output */
+    SPIx->CR2 &= CR2_SSOE_Reset;
+  }
+}
+
+/**
+  * @brief  Configures the data size for the selected SPI.
+  * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param SPI_DataSize: specifies the SPI data size.
+  *   This parameter can be one of the following values:
+  * @arg SPI_DataSize_16b: Set data frame format to 16bit
+  * @arg SPI_DataSize_8b: Set data frame format to 8bit
+  * @retval : None
+  */
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_DATASIZE(SPI_DataSize));
+  /* Clear DFF bit */
+  SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
+  /* Set new DFF bit value */
+  SPIx->CR1 |= SPI_DataSize;
+}
+
+/**
+  * @brief  Transmit the SPIx CRC value.
+  * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @retval : None
+  */
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  
+  /* Enable the selected SPI CRC transmission */
+  SPIx->CR1 |= CR1_CRCNext_Set;
+}
+
+/**
+  * @brief  Enables or disables the CRC value calculation of the
+  *   transfered bytes.
+  * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param NewState: new state of the SPIx CRC value calculation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI CRC calculation */
+    SPIx->CR1 |= CR1_CRCEN_Set;
+  }
+  else
+  {
+    /* Disable the selected SPI CRC calculation */
+    SPIx->CR1 &= CR1_CRCEN_Reset;
+  }
+}
+
+/**
+  * @brief  Returns the transmit or the receive CRC register value for
+  *   the specified SPI.
+  * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param SPI_CRC: specifies the CRC register to be read.
+  *   This parameter can be one of the following values:
+  * @arg SPI_CRC_Tx: Selects Tx CRC register
+  * @arg SPI_CRC_Rx: Selects Rx CRC register
+  * @retval : The selected CRC register value..
+  */
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
+{
+  uint16_t crcreg = 0;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_CRC(SPI_CRC));
+  if (SPI_CRC != SPI_CRC_Rx)
+  {
+    /* Get the Tx CRC register */
+    crcreg = SPIx->TXCRCR;
+  }
+  else
+  {
+    /* Get the Rx CRC register */
+    crcreg = SPIx->RXCRCR;
+  }
+  /* Return the selected CRC register */
+  return crcreg;
+}
+
+/**
+  * @brief  Returns the CRC Polynomial register value for the specified SPI.
+  * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @retval : The CRC Polynomial register value.
+  */
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  
+  /* Return the CRC polynomial register */
+  return SPIx->CRCPR;
+}
+
+/**
+  * @brief  Selects the data transfer direction in bi-directional mode
+  *   for the specified SPI.
+  * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param SPI_Direction: specifies the data transfer direction in
+  *   bi-directional mode. 
+  *   This parameter can be one of the following values:
+  * @arg SPI_Direction_Tx: Selects Tx transmission direction
+  * @arg SPI_Direction_Rx: Selects Rx receive direction
+  * @retval : None
+  */
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_DIRECTION(SPI_Direction));
+  if (SPI_Direction == SPI_Direction_Tx)
+  {
+    /* Set the Tx only mode */
+    SPIx->CR1 |= SPI_Direction_Tx;
+  }
+  else
+  {
+    /* Set the Rx only mode */
+    SPIx->CR1 &= SPI_Direction_Rx;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified SPI/I2S flag is set or not.
+  * @param SPIx: where x can be :
+  *   1, 2 or 3 in SPI mode 
+  *   2 or 3 in I2S mode
+  * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check. 
+  *   This parameter can be one of the following values:
+  * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
+  * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
+  * @arg SPI_I2S_FLAG_BSY: Busy flag.
+  * @arg SPI_I2S_FLAG_OVR: Overrun flag.
+  * @arg SPI_FLAG_MODF: Mode Fault flag.
+  * @arg SPI_FLAG_CRCERR: CRC Error flag.
+  * @arg I2S_FLAG_UDR: Underrun Error flag.
+  * @arg I2S_FLAG_CHSIDE: Channel Side flag.
+  * @retval : The new state of SPI_I2S_FLAG (SET or RESET).
+  */
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
+  /* Check the status of the specified SPI/I2S flag */
+  if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
+  {
+    /* SPI_I2S_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SPI_I2S_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the SPI_I2S_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the SPIx CRC Error (CRCERR) flag.
+  * @param SPIx: where x can be :
+  *   1, 2 or 3 in SPI mode 
+  * @param SPI_I2S_FLAG: specifies the SPI flag to clear. 
+  *   This function clears only CRCERR flag.
+  * @note
+  *   - OVR (OverRun error) flag is cleared by software sequence: a read 
+  *     operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read 
+  *     operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
+  *   - UDR (UnderRun error) flag is cleared by a read operation to 
+  *     SPI_SR register (SPI_I2S_GetFlagStatus()).
+  *   - MODF (Mode Fault) flag is cleared by software sequence: a read/write 
+  *     operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a 
+  *     write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
+  * @retval : None
+  */
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
+    
+    /* Clear the selected SPI CRC Error (CRCERR) flag */
+    SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified SPI/I2S interrupt has occurred or not.
+  * @param SPIx: where x can be :
+  *   1, 2 or 3 in SPI mode 
+  *   2 or 3 in I2S mode
+  * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. 
+  *   This parameter can be one of the following values:
+  * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
+  * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
+  * @arg SPI_I2S_IT_OVR: Overrun interrupt.
+  * @arg SPI_IT_MODF: Mode Fault interrupt.
+  * @arg SPI_IT_CRCERR: CRC Error interrupt.
+  * @arg I2S_IT_UDR: Underrun Error interrupt.
+  * @retval : The new state of SPI_I2S_IT (SET or RESET).
+  */
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint16_t itpos = 0, itmask = 0, enablestatus = 0;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
+  /* Get the SPI/I2S IT index */
+  itpos = (uint16_t)((uint16_t)0x01 << (SPI_I2S_IT & (uint8_t)0x0F));
+  /* Get the SPI/I2S IT mask */
+  itmask = SPI_I2S_IT >> 4;
+  /* Set the IT mask */
+  itmask = (uint16_t)((uint16_t)0x01 << itmask);
+  /* Get the SPI_I2S_IT enable bit status */
+  enablestatus = (SPIx->CR2 & itmask) ;
+  /* Check the status of the specified SPI/I2S interrupt */
+  if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
+  {
+    /* SPI_I2S_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SPI_I2S_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the SPI_I2S_IT status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
+  * @param SPIx: where x can be :
+  *   1, 2 or 3 in SPI mode 
+  * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
+  *   This function clears only CRCERR intetrrupt pending bit.   
+  * @note
+  *   - OVR (OverRun Error) interrupt pending bit is cleared by software 
+  *     sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) 
+  *     followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
+  *   - UDR (UnderRun Error) interrupt pending bit is cleared by a read 
+  *     operation to SPI_SR register (SPI_I2S_GetITStatus()).
+  *   - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
+  *     a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) 
+  *     followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable 
+  *     the SPI).
+  * @retval : None
+  */
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
+{
+  uint16_t itpos = 0;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
+  /* Get the SPI IT index */
+  itpos = (uint16_t)((uint16_t)0x01 << (SPI_I2S_IT & (uint8_t)0x0F));
+  /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
+  SPIx->SR = (uint16_t)~itpos;
+}
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_systick.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_systick.c
new file mode 100644
index 0000000..6f7a27e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_systick.c
@@ -0,0 +1,195 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_systick.c
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file provides all the SysTick firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_systick.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ---------------------- SysTick registers bit mask -------------------- */
+/* CTRL TICKINT Mask */
+#define CTRL_TICKINT_Set      ((u32)0x00000002)
+#define CTRL_TICKINT_Reset    ((u32)0xFFFFFFFD)
+
+/* SysTick Flag Mask */
+#define FLAG_Mask             ((u8)0x1F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : SysTick_CLKSourceConfig
+* Description    : Configures the SysTick clock source.
+* Input          : - SysTick_CLKSource: specifies the SysTick clock source.
+*                    This parameter can be one of the following values:
+*                       - SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8
+*                         selected as SysTick clock source.
+*                       - SysTick_CLKSource_HCLK: AHB clock selected as
+*                         SysTick clock source.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SysTick_CLKSourceConfig(u32 SysTick_CLKSource)
+{
+  /* Check the parameters */
+  assert(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+
+  if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+  {
+    SysTick->CTRL |= SysTick_CLKSource_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : SysTick_SetReload
+* Description    : Sets SysTick Reload value.
+* Input          : - Reload: SysTick Reload new value.
+*                    This parameter must be a number between 1 and 0xFFFFFF.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SysTick_SetReload(u32 Reload)
+{
+  /* Check the parameters */
+  assert(IS_SYSTICK_RELOAD(Reload));
+
+  SysTick->LOAD = Reload;
+}
+
+/*******************************************************************************
+* Function Name  : SysTick_CounterCmd
+* Description    : Enables or disables the SysTick counter.
+* Input          : - SysTick_Counter: new state of the SysTick counter.
+*                    This parameter can be one of the following values:
+*                       - SysTick_Counter_Disable: Disable counter
+*                       - SysTick_Counter_Enable: Enable counter
+*                       - SysTick_Counter_Clear: Clear counter value to 0
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SysTick_CounterCmd(u32 SysTick_Counter)
+{
+  /* Check the parameters */
+  assert(IS_SYSTICK_COUNTER(SysTick_Counter));
+
+  if (SysTick_Counter == SysTick_Counter_Clear)
+  {
+    SysTick->VAL = SysTick_Counter_Clear;
+  }
+  else
+  {
+    if (SysTick_Counter == SysTick_Counter_Enable)
+    {
+      SysTick->CTRL |= SysTick_Counter_Enable;
+    }
+    else
+    {
+      SysTick->CTRL &= SysTick_Counter_Disable;
+    }
+  }
+}
+
+/*******************************************************************************
+* Function Name  : SysTick_ITConfig
+* Description    : Enables or disables the SysTick Interrupt.
+* Input          : - NewState: new state of the SysTick Interrupt.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SysTick_ITConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    SysTick->CTRL |= CTRL_TICKINT_Set;
+  }
+  else
+  {
+    SysTick->CTRL &= CTRL_TICKINT_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : SysTick_GetCounter
+* Description    : Gets SysTick counter value.
+* Input          : None
+* Output         : None
+* Return         : SysTick current value
+*******************************************************************************/
+u32 SysTick_GetCounter(void)
+{
+  return(SysTick->VAL);
+}
+
+/*******************************************************************************
+* Function Name  : SysTick_GetFlagStatus
+* Description    : Checks whether the specified SysTick flag is set or not.
+* Input          : - SysTick_FLAG: specifies the flag to check.
+*                    This parameter can be one of the following values:
+*                       - SysTick_FLAG_COUNT
+*                       - SysTick_FLAG_SKEW
+*                       - SysTick_FLAG_NOREF
+* Output         : None
+* Return         : None
+*******************************************************************************/
+FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG)
+{
+  u32 tmp = 0;
+  u32 statusreg = 0;
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert(IS_SYSTICK_FLAG(SysTick_FLAG));
+
+  /* Get the SysTick register index */
+  tmp = SysTick_FLAG >> 5;
+
+  if (tmp == 1) /* The flag to check is in CTRL register */
+  {
+    statusreg = SysTick->CTRL;
+  }
+  else          /* The flag to check is in CALIB register */
+  {
+    statusreg = SysTick->CALIB;
+  }
+
+  /* Get the flag position */
+  tmp = SysTick_FLAG & FLAG_Mask;
+
+  if ((statusreg & ((u32)1 << tmp)) != (u32)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_tim.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_tim.c
new file mode 100644
index 0000000..5fd374e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_tim.c
@@ -0,0 +1,2348 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_tim.c
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file provides all the TIM firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_tim.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ---------------------- TIM registers bit mask ------------------------ */
+#define CR1_CEN_Set                 ((u16)0x0001)
+#define CR1_CEN_Reset               ((u16)0x03FE)
+#define CR1_UDIS_Set                ((u16)0x0002)
+#define CR1_UDIS_Reset              ((u16)0x03FD)
+#define CR1_URS_Set                 ((u16)0x0004)
+#define CR1_URS_Reset               ((u16)0x03FB)
+#define CR1_OPM_Mask                ((u16)0x03F7)
+#define CR1_CounterMode_Mask        ((u16)0x039F)
+#define CR1_ARPE_Set                ((u16)0x0080)
+#define CR1_ARPE_Reset              ((u16)0x037F)
+#define CR1_CKD_Mask                ((u16)0x00FF)
+
+#define CR2_CCDS_Set                ((u16)0x0008)
+#define CR2_CCDS_Reset              ((u16)0x0007)
+#define CR2_MMS_Mask                ((u16)0x0080)
+#define CR2_TI1S_Set                ((u16)0x0080)
+#define CR2_TI1S_Reset              ((u16)0xFF70)
+
+#define SMCR_SMS_Mask               ((u16)0xFFF0)
+#define SMCR_ETR_Mask               ((u16)0x00F7)
+#define SMCR_TS_Mask                ((u16)0xFF87)
+#define SMCR_MSM_Mask               ((u16)0xFF77)
+#define SMCR_ECE_Set                ((u16)0x4000)
+
+#define CCMR_CC13S_Mask             ((u16)0x7F7C)
+#define CCMR_CC24S_Mask             ((u16)0x7C7F)
+#define CCMR_TI13Direct_Set         ((u16)0x0001)
+#define CCMR_TI24Direct_Set         ((u16)0x0100)
+#define CCMR_OC13FE_Mask            ((u16)0x7F7B)
+#define CCMR_OC24FE_Mask            ((u16)0x7B7F)
+#define CCMR_OC13PE_Mask            ((u16)0x7F77)
+#define CCMR_OC24PE_Mask            ((u16)0x777F)
+#define CCMR_OCM13_Mask             ((u16)0x7F0F)
+#define CCMR_OCM24_Mask             ((u16)0x0F7F)
+#define CCMR_IC13PSC_Mask           ((u16)0xFFF3)
+#define CCMR_IC24PSC_Mask           ((u16)0xF3FF)
+#define CCMR_IC13F_Mask             ((u16)0xFF0F)
+#define CCMR_IC24F_Mask             ((u16)0x0FFF)
+#define CCER_CC1P_Mask              ((u16)0xFFFD)
+
+#define CCER_CC2P_Mask              ((u16)0xFFDF)
+#define CCER_CC3P_Mask              ((u16)0xFDFF)
+#define CCER_CC4P_Mask              ((u16)0xDFFF)
+
+#define CCRE_CC1E_Set               ((u16)0x0001)
+#define CCRE_CC1E_Reset             ((u16)0xFFFE)
+#define CCRE_CC1E_Mask              ((u16)0xFFFE)
+
+#define CCRE_CC2E_Set               ((u16)0x0010)
+#define CCRE_CC2E_Reset             ((u16)0xFFEF)
+#define CCRE_CC2E_Mask              ((u16)0xFFEF)
+
+#define CCRE_CC3E_Set               ((u16)0x0100)
+#define CCRE_CC3E_Reset             ((u16)0xFEFF)
+
+#define CCRE_CC4E_Set               ((u16)0x1000)
+#define CCRE_CC4E_Reset             ((u16)0xEFFF)
+#define CCRE_CC4E_Mask              ((u16)0xEFFF)
+
+#define DCR_DMA_Mask                ((u16)0x0000)
+
+/* TIM private Masks */
+#define TIM_Period_Reset_Mask       ((u16)0x0000)
+#define TIM_Prescaler_Reset_Mask    ((u16)0x0000)
+#define TIM_Pulse_Reset_Mask        ((u16)0x0000)
+#define TIM_ICFilter_Mask           ((u8)0x00)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static uc16 Tab_OCModeMask[4] = {0xFF00, 0x00FF, 0xFF00, 0x00FF};
+static uc16 Tab_PolarityMask[4] = {CCER_CC1P_Mask, CCER_CC2P_Mask, CCER_CC3P_Mask, CCER_CC4P_Mask};
+
+/* Private function prototypes -----------------------------------------------*/
+static void PWMI_Config(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+static void TI1_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
+                       u8 TIM_ICFilter);
+static void TI2_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
+                       u8 TIM_ICFilter);
+static void TI3_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
+                       u8 TIM_ICFilter);
+static void TI4_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
+                       u8 TIM_ICFilter);
+static void ETR_Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, 
+                       u16 TIM_ExtTRGPolarity, u8 ExtTRGFilter);
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : TIM_DeInit
+* Description    : Deinitializes the TIMx peripheral registers to their default
+*                  reset values.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_DeInit(TIM_TypeDef* TIMx)
+{  
+  switch (*(u32*)&TIMx)
+  {
+    case TIM2_BASE:
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
+      break;
+ 
+    case TIM3_BASE:
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
+      break;
+ 
+    case TIM4_BASE:
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
+      break;
+ 
+    default:
+      break;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : TIM_TimeBaseInit
+* Description    : Initializes the TIMx Time Base Unit peripheral according to 
+*                  the specified parameters in the TIM_TimeBaseInitStruct.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
+*                   structure that contains the configuration information for
+*                   the specified TIM peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+  /* Check the parameters */
+  assert(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
+  assert(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
+  
+  /* Set the Autoreload value */
+  TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
+
+  /* Set the Prescaler value */
+  TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
+
+  /* Select the Counter Mode and set the clock division */
+  TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;
+  TIMx->CR1 |= (u32)TIM_TimeBaseInitStruct->TIM_ClockDivision |
+               TIM_TimeBaseInitStruct->TIM_CounterMode;
+}
+/*******************************************************************************
+* Function Name  : TIM_OCInit
+* Description    : Initializes the TIMx peripheral according to the specified
+*                  parameters in the TIM_OCInitStruct.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+*                    that contains the configuration information for the specified
+*                    TIM peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_OCInit(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  u32 tmpccmrx = 0, tmpccer = 0;
+  
+  /* Check the parameters */
+  assert(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+  assert(IS_TIM_CHANNEL(TIM_OCInitStruct->TIM_Channel));
+  assert(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+
+  tmpccer = TIMx->CCER;
+
+  if ((TIM_OCInitStruct->TIM_Channel == (u16)TIM_Channel_1) ||
+      (TIM_OCInitStruct->TIM_Channel == (u16)TIM_Channel_2))
+  {
+    tmpccmrx = TIMx->CCMR1;
+    
+    /* Reset the Output Compare Bits */
+    tmpccmrx &= Tab_OCModeMask[TIM_OCInitStruct->TIM_Channel];
+
+    /* Set the Output Polarity level */
+    tmpccer &= Tab_PolarityMask[TIM_OCInitStruct->TIM_Channel];
+
+    if (TIM_OCInitStruct->TIM_Channel == TIM_Channel_1)
+    {
+      /* Disable the Channel 1: Reset the CCE Bit */
+      TIMx->CCER &= CCRE_CC1E_Reset;
+
+      /* Select the Output Compare Mode */
+      tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+
+      /* Set the Capture Compare Register value */
+      TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
+
+      /* Set the Capture Compare Enable Bit */
+      tmpccer |= CCRE_CC1E_Set;
+
+      /* Set the Capture Compare Polarity */
+      tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
+    }
+    else /* TIM_Channel_2 */
+    {
+      /* Disable the Channel 2: Reset the CCE Bit */
+      TIMx->CCER &= CCRE_CC2E_Reset;
+
+      /* Select the Output Compare Mode */
+      tmpccmrx |= (u32)TIM_OCInitStruct->TIM_OCMode << 8;
+
+      /* Set the Capture Compare Register value */
+      TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
+
+      /* Set the Capture Compare Enable Bit */
+      tmpccer |= CCRE_CC2E_Set;
+
+      /* Set the Capture Compare Polarity */
+      tmpccer |= (u32)TIM_OCInitStruct->TIM_OCPolarity << 4;
+    }
+
+    TIMx->CCMR1 = (u16)tmpccmrx;
+  }
+  else 
+  {
+    if ((TIM_OCInitStruct->TIM_Channel == TIM_Channel_3) ||
+        (TIM_OCInitStruct->TIM_Channel == TIM_Channel_4))
+    { 
+      tmpccmrx = TIMx->CCMR2;
+
+      /* Reset the Output Compare Bits */
+      tmpccmrx &= Tab_OCModeMask[TIM_OCInitStruct->TIM_Channel];
+
+      /* Set the Output Polarity level */
+      tmpccer &= Tab_PolarityMask[TIM_OCInitStruct->TIM_Channel];
+
+      if (TIM_OCInitStruct->TIM_Channel == TIM_Channel_3)
+      {
+        /* Disable the Channel 3: Reset the CCE Bit */
+        TIMx->CCER &= CCRE_CC3E_Reset;
+
+        /* Select the Output Compare Mode */
+        tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+
+        /* Set the Capture Compare Register value */
+        TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
+
+        /* Set the Capture Compare Enable Bit */
+        tmpccer |= CCRE_CC3E_Set;
+
+        /* Set the Capture Compare Polarity */
+        tmpccer |= (u32)TIM_OCInitStruct->TIM_OCPolarity << 8;
+      }
+      else  /* TIM_Channel_4 */
+      {
+        /* Disable the Channel 4: Reset the CCE Bit */
+        TIMx->CCER &= CCRE_CC4E_Reset;
+
+       /* Select the Output Compare Mode */
+        tmpccmrx |= (u32)TIM_OCInitStruct->TIM_OCMode << 8;
+
+        /* Set the Capture Compare Register value */
+        TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
+
+        /* Set the Capture Compare Enable Bit */
+        tmpccer |= CCRE_CC4E_Set;
+
+        /* Set the Capture Compare Polarity */
+        tmpccer |= (u32)TIM_OCInitStruct->TIM_OCPolarity << 12;
+      }
+
+      TIMx->CCMR2 = (u16)tmpccmrx;
+    }
+  }
+  
+  TIMx->CCER = (u16)tmpccer;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_ICInit
+* Description    : Initializes the TIMx peripheral according to the specified
+*                  parameters in the TIM_ICInitStruct.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
+*                    that contains the configuration information for the specified
+*                    TIM peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+  /* Check the parameters */
+  assert(IS_TIM_IC_MODE(TIM_ICInitStruct->TIM_ICMode));
+  assert(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
+  assert(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
+  assert(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
+  assert(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
+  assert(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
+  
+  if (TIM_ICInitStruct->TIM_ICMode == TIM_ICMode_ICAP)
+  {
+    if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+    {
+      /* TI1 Configuration */
+      TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+                 TIM_ICInitStruct->TIM_ICSelection,
+                 TIM_ICInitStruct->TIM_ICFilter);
+
+      /* Set the Input Capture Prescaler value */
+      TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+    else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
+    {
+      /* TI2 Configuration */
+      TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+                 TIM_ICInitStruct->TIM_ICSelection,
+                 TIM_ICInitStruct->TIM_ICFilter);
+
+      /* Set the Input Capture Prescaler value */
+      TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+    else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
+    {
+      /* TI3 Configuration */
+      TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+                 TIM_ICInitStruct->TIM_ICSelection,
+                 TIM_ICInitStruct->TIM_ICFilter);
+
+      /* Set the Input Capture Prescaler value */
+      TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+    else /* TIM_Channel_4 */
+    {
+      /* TI4 Configuration */
+      TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+                 TIM_ICInitStruct->TIM_ICSelection,
+                 TIM_ICInitStruct->TIM_ICFilter);
+
+      /* Set the Input Capture Prescaler value */
+      TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+  }
+  else
+  {
+    PWMI_Config(TIMx, TIM_ICInitStruct);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : TIM_TimeBaseStructInit
+* Description    : Fills each TIM_TimeBaseInitStruct member with its default value.
+* Input          : - TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
+*                    structure which will be initialized.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+  /* Set the default configuration */
+  TIM_TimeBaseInitStruct->TIM_Period = TIM_Period_Reset_Mask;
+  TIM_TimeBaseInitStruct->TIM_Prescaler = TIM_Prescaler_Reset_Mask;
+  TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
+  TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_OCStructInit
+* Description    : Fills each TIM_OCInitStruct member with its default value.
+* Input          : - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+*                    which will be initialized.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  /* Set the default configuration */
+  TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
+  TIM_OCInitStruct->TIM_Channel = TIM_Channel_1;
+  TIM_OCInitStruct->TIM_Pulse = TIM_Pulse_Reset_Mask;
+  TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_ICStructInit
+* Description    : Fills each TIM_InitStruct member with its default value.
+* Input          : - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
+*                    which will be initialized.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+  /* Set the default configuration */
+  TIM_ICInitStruct->TIM_ICMode = TIM_ICMode_ICAP;
+  TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
+  TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
+  TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
+  TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
+  TIM_ICInitStruct->TIM_ICFilter = TIM_ICFilter_Mask;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_Cmd
+* Description    : Enables or disables the specified TIM peripheral.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIMx peripheral.
+*                  - Newstate: new state of the TIMx peripheral.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the TIM Counter */
+    TIMx->CR1 |= CR1_CEN_Set;
+  }
+  else
+  {
+    /* Disable the TIM Counter */
+    TIMx->CR1 &= CR1_CEN_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : TIM_ITConfig
+* Description    : Enables or disables the TIMx interrupts.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_IT: specifies the TIM interrupts sources to be enabled
+*                    or disabled.
+*                    This parameter can be any combination of the following values:
+*                       - TIM_IT_Update: Timer update Interrupt
+*                       - TIM_IT_CC1: Capture Compare 1 Interrupt
+*                       - TIM_IT_CC2: Capture Compare 2 Interrupt
+*                       - TIM_IT_CC3: Capture Compare 3 Interrupt
+*                       - TIM_IT_CC4: Capture Compare 4 Interrupt
+*                       - TIM_IT_Trigger: Trigger Interrupt
+*                  - Newstate: new state of the specified TIMx interrupts.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_ITConfig(TIM_TypeDef* TIMx, u16 TIM_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_TIM_IT(TIM_IT));
+  assert(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the Interrupt sources */
+    TIMx->DIER |= TIM_IT;
+  }
+  else
+  {
+    /* Disable the Interrupt sources */
+    TIMx->DIER &= (u16)(~TIM_IT);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : TIM_DMAConfig
+* Description    : Configures the TIMx’s DMA interface.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_DMABase: DMA Base address.
+*                    This parameter can be one of the following values:
+*                       - TIM_DMABase_CR1, TIM_DMABase_CR2, TIM_DMABase_SMCR,
+*                         TIM_DMABase_DIER, TIM_DMABase_SR, TIM_DMABase_EGR,
+*                         TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
+*                         TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
+*                         TIM_DMABase_CCR1, TIM_DMABase_CCR2, TIM_DMABase_CCR3,
+*                         TIM_DMABase_CCR4, TIM_DMABase_DCR.
+*                  - TIM_DMABurstLength: DMA Burst length.
+*                    This parameter can be one value between:
+*                    TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_DMAConfig(TIM_TypeDef* TIMx, u16 TIM_DMABase, u16 TIM_DMABurstLength)
+{
+  u32 tmpdcr = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_DMA_BASE(TIM_DMABase));
+  assert(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
+  
+  tmpdcr = TIMx->DCR;
+
+  /* Reset the DBA and the DBL Bits */
+  tmpdcr &= DCR_DMA_Mask;
+
+  /* Set the DMA Base and the DMA Burst Length */
+  tmpdcr |= TIM_DMABase | TIM_DMABurstLength;
+
+  TIMx->DCR = (u16)tmpdcr;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_DMACmd
+* Description    : Enables or disables the TIMx’s DMA Requests.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_DMASources: specifies the DMA Request sources.
+*                    This parameter can be any combination of the following values:
+*                       - TIM_DMA_CC1: Capture Compare 1 DMA source
+*                       - TIM_DMA_CC2: Capture Compare 2 DMA source
+*                       - TIM_DMA_CC3: Capture Compare 3 DMA source
+*                       - TIM_DMA_CC4: Capture Compare 4 DMA source
+*                       - TIM_DMA_Trigger: Trigger DMA source
+*                  - Newstate: new state of the DMA Request sources.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_DMACmd(TIM_TypeDef* TIMx, u16 TIM_DMASource, FunctionalState Newstate)
+{
+  u32 tmpdier = 0;
+  
+  /* Check the parameters */
+  assert(IS_TIM_DMA_SOURCE(TIM_DMASource));
+  assert(IS_FUNCTIONAL_STATE(Newstate));
+
+  tmpdier = TIMx->DIER;
+
+  if (Newstate != DISABLE)
+  {
+    /* Enable the DMA sources */
+    tmpdier |= TIM_DMASource;
+  }
+  else
+  {
+    /* Disable the DMA sources */
+    tmpdier &= (u16)(~TIM_DMASource);
+  }
+  TIMx->DIER = (u16)tmpdier;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_InternalClockConfig
+* Description    : Configures the TIMx interrnal Clock
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
+{
+  /* Disable slave mode to clock the prescaler directly with the internal clock */
+  TIMx->SMCR &=  SMCR_SMS_Mask;
+}
+/*******************************************************************************
+* Function Name  : TIM_ITRxExternalClockConfig
+* Description    : Configures the TIMx Internal Trigger as External Clock
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_ITRSource: Trigger source.
+*                    This parameter can be one of the following values:
+*                       - TIM_TS_ITR0: Internal Trigger 0
+*                       - TIM_TS_ITR1: Internal Trigger 1
+*                       - TIM_TS_ITR2: Internal Trigger 2
+*                       - TIM_TS_ITR3: Internal Trigger 3
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource)
+{
+  /* Check the parameters */
+  assert(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
+
+  /* Select the Internal Trigger */
+  TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
+
+  /* Select the External clock mode1 */
+  TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+/*******************************************************************************
+* Function Name  : TIM_TIxExternalClockConfig
+* Description    : Configures the TIMx Trigger as External Clock
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_TIxExternalCLKSource: Trigger source.
+*                    This parameter can be one of the following values:
+*                       - TIM_TS_TI1F_ED: TI1 Edge Detector
+*                       - TIM_TS_TI1FP1: Filtered Timer Input 1
+*                       - TIM_TS_TI2FP2: Filtered Timer Input 2
+*                  - TIM_ICPolarity: specifies the TIx Polarity.
+*                    This parameter can be:
+*                       - TIM_ICPolarity_Rising
+*                       - TIM_ICPolarity_Falling
+*                   - ICFilter : specifies the filter value.
+*                     This parameter must be a value between 0x0 and 0xF.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_TIxExternalCLKSource,
+                                u16 TIM_ICPolarity, u8 ICFilter)
+{
+  /* Check the parameters */
+  assert(IS_TIM_TIX_TRIGGER_SELECTION(TIM_TIxExternalCLKSource));
+  assert(IS_TIM_IC_POLARITY(TIM_ICPolarity));
+  assert(IS_TIM_IC_FILTER(ICFilter));
+
+  /* Configure the Timer Input Clock Source */
+  if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
+  {
+    TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+  }
+  else
+  {
+    TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+  }
+
+  /* Select the Trigger source */
+  TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
+
+  /* Select the External clock mode1 */
+  TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_ETRClockMode1Config
+* Description    : Configures the External clock Mode1
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+*                    It can be one of the following values:
+*                       - TIM_ExtTRGPSC_OFF
+*                       - TIM_ExtTRGPSC_DIV2
+*                       - TIM_ExtTRGPSC_DIV4
+*                       - TIM_ExtTRGPSC_DIV8.
+*                  - TIM_ExtTRGPolarity: The external Trigger Polarity.
+*                    It can be one of the following values:
+*                       - TIM_ExtTRGPolarity_Inverted
+*                       - TIM_ExtTRGPolarity_NonInverted
+*                  - ExtTRGFilter: External Trigger Filter.
+*                    This parameter must be a value between 0x00 and 0x0F
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,
+                             u8 ExtTRGFilter)
+{
+  /* Check the parameters */
+  assert(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+  assert(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+
+  /* Configure the ETR Clock source */
+  ETR_Config(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+
+  /* Select the External clock mode1 */
+  TIMx->SMCR &= SMCR_SMS_Mask;
+  TIMx->SMCR |= TIM_SlaveMode_External1;
+
+  /* Select the Trigger selection : ETRF */
+  TIMx->SMCR &= SMCR_TS_Mask;
+  TIMx->SMCR |= TIM_TS_ETRF;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_ETRClockMode2Config
+* Description    : Configures the External clock Mode2
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+*                    It can be one of the following values:
+*                       - TIM_ExtTRGPSC_OFF
+*                       - TIM_ExtTRGPSC_DIV2
+*                       - TIM_ExtTRGPSC_DIV4
+*                       - TIM_ExtTRGPSC_DIV8
+*                  - TIM_ExtTRGPolarity: The external Trigger Polarity.
+*                    It can be one of the following values:
+*                       - TIM_ExtTRGPolarity_Inverted
+*                       - TIM_ExtTRGPolarity_NonInverted
+*                  - ExtTRGFilter: External Trigger Filter.
+*                    This parameter must be a value between 0x00 and 0x0F
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, 
+                             u16 TIM_ExtTRGPolarity, u8 ExtTRGFilter)
+{
+  /* Check the parameters */
+  assert(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+  assert(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+
+  /* Configure the ETR Clock source */
+  ETR_Config(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+
+  /* Enable the External clock mode2 */
+  TIMx->SMCR |= SMCR_ECE_Set;
+}
+/*******************************************************************************
+* Function Name  : TIM_SelectInputTrigger
+* Description    : Selects the Input Trigger source
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_InputTriggerSource: The Input Trigger source.
+*                    This parameter can be one of the following values:
+*                       - TIM_TS_ITR0: Internal Trigger 0
+*                       - TIM_TS_ITR1: Internal Trigger 1
+*                       - TIM_TS_ITR2: Internal Trigger 2
+*                       - TIM_TS_ITR3: Internal Trigger 3
+*                       - TIM_TS_TI1F_ED: TI1 Edge Detector
+*                       - TIM_TS_TI1FP1: Filtered Timer Input 1
+*                       - TIM_TS_TI2FP2: Filtered Timer Input 2
+*                       - TIM_TS_ETRF: External Trigger input
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource)
+{
+  u32 tmpsmcr = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
+
+  tmpsmcr = TIMx->SMCR;
+
+  /* Select the Tgigger Source */
+  tmpsmcr &= SMCR_TS_Mask;
+  tmpsmcr |= TIM_InputTriggerSource;
+
+  TIMx->SMCR = (u16)tmpsmcr;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_PrescalerConfig
+* Description    : Configures the TIMx Prescaler.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - Prescaler: specifies the Prescaler Register value
+*                  - TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
+*                    This parameter can be one of the following values:
+*                       - TIM_PSCReloadMode_Update: The Prescaler is loaded at
+*                         the update event.
+*                       - TIM_PSCReloadMode_Immediate: The Prescaler is loaded
+*                         immediatly.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, u16 Prescaler, u16 TIM_PSCReloadMode)
+{
+  /* Check the parameters */
+  assert(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
+
+  /* Set the Prescaler value */
+  TIMx->PSC = Prescaler;
+
+  /* Set or reset the UG Bit */
+  if (TIM_PSCReloadMode == TIM_PSCReloadMode_Immediate)
+  {
+    TIMx->EGR |= TIM_EventSource_Update;
+  }
+  else
+  {
+    TIMx->EGR &= TIM_EventSource_Update;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : TIM_CounterModeConfig
+* Description    : Specifies the TIMx Counter Mode to be used.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_CounterMode: specifies the Counter Mode to be used
+*                    This parameter can be one of the following values:
+*                       - TIM_CounterMode_Up: TIM Up Counting Mode
+*                       - TIM_CounterMode_Down: TIM Down Counting Mode
+*                       - TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
+*                       - TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
+*                       - TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode)
+{
+  u32 tmpcr1 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_COUNTER_MODE(TIM_CounterMode));
+
+  tmpcr1 = TIMx->CR1;
+
+  /* Reset the CMS and DIR Bits */
+  tmpcr1 &= CR1_CounterMode_Mask;
+
+  /* Set the Counter Mode */
+  tmpcr1 |= TIM_CounterMode;
+
+  TIMx->CR1 = (u16)tmpcr1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_ForcedOC1Config
+* Description    : Forces the TIMx output 1 waveform to active or inactive level.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_ForcedAction: specifies the forced Action to be set to
+*                    the output waveform.
+*                    This parameter can be one of the following values:
+*                       - TIM_ForcedAction_Active: Force active level on OC1REF
+*                       - TIM_ForcedAction_InActive: Force inactive level on
+*                         OC1REF.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction)
+{
+  u32 tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OCM Bits */
+  tmpccmr1 &= CCMR_OCM13_Mask;
+
+  /* Configure The Forced output Mode */
+  tmpccmr1 |= TIM_ForcedAction;
+
+  TIMx->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_ForcedOC2Config
+* Description    : Forces the TIMx output 2 waveform to active or inactive level.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_ForcedAction: specifies the forced Action to be set to
+*                    the output waveform.
+*                    This parameter can be one of the following values:
+*                       - TIM_ForcedAction_Active: Force active level on OC2REF
+*                       - TIM_ForcedAction_InActive: Force inactive level on
+*                         OC2REF.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction)
+{
+  u32 tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OCM Bits */
+  tmpccmr1 &= CCMR_OCM24_Mask;
+
+  /* Configure The Forced output Mode */
+  tmpccmr1 |= (u16)(TIM_ForcedAction << 8);
+
+  TIMx->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_ForcedOC3Config
+* Description    : Forces the TIMx output 3 waveform to active or inactive level.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_ForcedAction: specifies the forced Action to be set to
+*                    the output waveform.
+*                    This parameter can be one of the following values:
+*                       - TIM_ForcedAction_Active: Force active level on OC3REF
+*                       - TIM_ForcedAction_InActive: Force inactive level on
+*                         OC3REF.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction)
+{
+  u32 tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the OCM Bits */
+  tmpccmr2 &= CCMR_OCM13_Mask;
+
+  /* Configure The Forced output Mode */
+  tmpccmr2 |= TIM_ForcedAction;
+
+  TIMx->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_ForcedOC4Config
+* Description    : Forces the TIMx output 4 waveform to active or inactive level.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_ForcedAction: specifies the forced Action to be set to
+*                    the output waveform.
+*                    This parameter can be one of the following values:
+*                       - TIM_ForcedAction_Active: Force active level on OC4REF
+*                       - TIM_ForcedAction_InActive: Force inactive level on
+*                         OC4REF.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction)
+{
+  u32 tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the OCM Bits */
+  tmpccmr2 &= CCMR_OCM24_Mask;
+
+  /* Configure The Forced output Mode */
+  tmpccmr2 |= (u16)(TIM_ForcedAction << 8);
+
+  TIMx->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_ARRPreloadConfig
+* Description    : Enables or disables TIMx peripheral Preload register on ARR.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - Newstate: new state of the TIMx peripheral Preload register
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState Newstate)
+{
+  u32 tmpcr1 = 0;
+  
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(Newstate));
+
+  tmpcr1 = TIMx->CR1;
+
+  if (Newstate != DISABLE)
+  {
+    /* Set the ARR Preload Bit */
+    tmpcr1 |= CR1_ARPE_Set;
+  }
+  else
+  {
+    /* Reset the ARR Preload Bit */
+    tmpcr1 &= CR1_ARPE_Reset;
+  }
+
+  TIMx->CR1 = (u16)tmpcr1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_SelectCCDMA
+* Description    : Selects the TIMx peripheral Capture Compare DMA source.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - Newstate: new state of the Capture Compare DMA source
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState Newstate)
+{
+  u32 tmpcr2 = 0;
+
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(Newstate));
+
+  tmpcr2 = TIMx->CR2;
+
+  if (Newstate != DISABLE)
+  {
+    /* Set the CCDS Bit */
+    tmpcr2 |= CR2_CCDS_Set;
+  }
+  else
+  {
+    /* Reset the CCDS Bit */
+    tmpcr2 &= CR2_CCDS_Reset;
+  }
+
+  TIMx->CR2 = (u16)tmpcr2;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_OC1PreloadConfig
+* Description    : Enables or disables the TIMx peripheral Preload register on CCR1.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_OCPreload: new state of the TIMx peripheral Preload
+*                    register
+*                    This parameter can be one of the following values:
+*                       - TIM_OCPreload_Enable
+*                       - TIM_OCPreload_Disable
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload)
+{
+  u32 tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OCPE Bit */
+  tmpccmr1 &= CCMR_OC13PE_Mask;
+
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr1 |= TIM_OCPreload;
+
+  TIMx->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_OC2PreloadConfig
+* Description    : Enables or disables the TIMx peripheral Preload register on CCR2.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_OCPreload: new state of the TIMx peripheral Preload
+*                    register
+*                    This parameter can be one of the following values:
+*                       - TIM_OCPreload_Enable
+*                       - TIM_OCPreload_Disable
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload)
+{
+  u32 tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OCPE Bit */
+  tmpccmr1 &= CCMR_OC24PE_Mask;
+
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr1 |= (u16)(TIM_OCPreload << 8);
+
+  TIMx->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_OC3PreloadConfig
+* Description    : Enables or disables the TIMx peripheral Preload register on CCR3.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_OCPreload: new state of the TIMx peripheral Preload
+*                    register
+*                    This parameter can be one of the following values:
+*                       - TIM_OCPreload_Enable
+*                       - TIM_OCPreload_Disable
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload)
+{
+  u32 tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the OCPE Bit */
+  tmpccmr2 &= CCMR_OC13PE_Mask;
+
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr2 |= TIM_OCPreload;
+
+  TIMx->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_OC4PreloadConfig
+* Description    : Enables or disables the TIMx peripheral Preload register on CCR4.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_OCPreload: new state of the TIMx peripheral Preload
+*                    register
+*                    This parameter can be one of the following values:
+*                       - TIM_OCPreload_Enable
+*                       - TIM_OCPreload_Disable
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload)
+{
+  u32 tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the OCPE Bit */
+  tmpccmr2 &= CCMR_OC24PE_Mask;
+
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr2 |= (u16)(TIM_OCPreload << 8);
+
+  TIMx->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_OC1FastConfig
+* Description    : Configures the TIMx Output Compare 1 Fast feature.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+*                    This parameter can be one of the following values:
+*                       - TIM_OCFast_Enable
+*                       - TIM_OCFast_Disable
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast)
+{
+  u32 tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_OCFAST_STATE(TIM_OCFast));
+
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OCFE Bit */
+  tmpccmr1 &= CCMR_OC13FE_Mask;
+
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr1 |= TIM_OCFast;
+
+  TIMx->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_OC2FastConfig
+* Description    : Configures the TIMx Output Compare 2 Fast feature.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+*                    This parameter can be one of the following values:
+*                       - TIM_OCFast_Enable
+*                       - TIM_OCFast_Disable
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast)
+{
+  u32 tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_OCFAST_STATE(TIM_OCFast));
+
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OCFE Bit */
+  tmpccmr1 &= CCMR_OC24FE_Mask;
+
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr1 |= (u16)(TIM_OCFast << 8);
+
+  TIMx->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_OC3FastConfig
+* Description    : Configures the TIMx Output Compare 3 Fast feature.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+*                    This parameter can be one of the following values:
+*                       - TIM_OCFast_Enable
+*                       - TIM_OCFast_Disable
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast)
+{
+  u32 tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_OCFAST_STATE(TIM_OCFast));
+
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the OCFE Bit */
+  tmpccmr2 &= CCMR_OC13FE_Mask;
+
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr2 |= TIM_OCFast;
+
+  TIMx->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_OC4FastConfig
+* Description    : Configures the TIMx Output Compare 4 Fast feature.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+*                    This parameter can be one of the following values:
+*                       - TIM_OCFast_Enable
+*                       - TIM_OCFast_Disable
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast)
+{
+  u32 tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_OCFAST_STATE(TIM_OCFast));
+
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the OCFE Bit */
+  tmpccmr2 &= CCMR_OC24FE_Mask;
+
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr2 |= (u16)(TIM_OCFast << 8);
+
+  TIMx->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_UpdateDisableConfig
+* Description    : Enables or Disables the TIMx Update event.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - Newstate: new state of the TIMx peripheral Preload register
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState Newstate)
+{
+  u32 tmpcr1 = 0;
+
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(Newstate));
+
+  tmpcr1 = TIMx->CR1;
+
+  if (Newstate != DISABLE)
+  {
+    /* Set the Update Disable Bit */
+    tmpcr1 |= CR1_UDIS_Set;
+  }
+  else
+  {
+    /* Reset the Update Disable Bit */
+    tmpcr1 &= CR1_UDIS_Reset;
+  }
+
+  TIMx->CR1 = (u16)tmpcr1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_EncoderInterfaceConfig
+* Description    : Configures the TIMx Encoder Interface.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_EncoderMode: specifies the TIMx Encoder Mode.
+*                    This parameter can be one of the following values:
+*                       - TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge
+*                         depending on TI2FP2 level.
+*                       - TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge
+*                         depending on TI1FP1 level.
+*                       - TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and
+*                         TI2FP2 edges depending on the level of the other input.
+*                  - TIM_IC1Polarity: specifies the IC1 Polarity
+*                    This parmeter can be one of the following values:
+*                        - TIM_ICPolarity_Falling
+*                        - TIM_ICPolarity_Rising
+*                  - TIM_IC2Polarity: specifies the IC2 Polarity
+*                    This parmeter can be one of the following values:
+*                       - TIM_ICPolarity_Falling
+*                       - TIM_ICPolarity_Rising
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u16 TIM_EncoderMode,
+                                u16 TIM_IC1Polarity, u16 TIM_IC2Polarity)
+{
+  u32 tmpsmcr = 0;
+  u32 tmpccmr1 = 0;
+  u32 tmpccer = 0;
+    
+  /* Check the parameters */
+  assert(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
+  assert(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
+  assert(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
+
+  tmpsmcr = TIMx->SMCR;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Set the encoder Mode */
+  tmpsmcr &= SMCR_SMS_Mask;
+  tmpsmcr |= TIM_EncoderMode;
+
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask;
+  tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set;
+
+  /* Set the TI1 and the TI2 Polarities */
+  tmpccer &= CCER_CC1P_Mask & CCER_CC2P_Mask;
+  tmpccer |= (TIM_IC1Polarity | (u16)((u16)TIM_IC2Polarity << 4));
+
+  TIMx->SMCR = (u16)tmpsmcr;
+
+  TIMx->CCMR1 = (u16)tmpccmr1;
+
+  TIMx->CCER = (u16)tmpccer;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_GenerateEvent
+* Description    : Configures the TIMx event to be generate by software.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_EventSource: specifies the event source.
+*                    This parameter can be one or more of the following values:
+*                       - TIM_EventSource_Update: Timer update Event source
+*                       - TIM_EventSource_CC1: Timer Capture Compare 1 Event source
+*                       - TIM_EventSource_CC2: Timer Capture Compare 2 Event source
+*                       - TIM_EventSource_CC3: Timer Capture Compare 3 Event source
+*                       - TIM_EventSource_CC4: Timer Capture Compare 4 Event source
+*                       - TIM_EventSource_Trigger: Timer Trigger Event source
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, u16 TIM_EventSource)
+{
+  /* Check the parameters */
+  assert(IS_TIM_EVENT_SOURCE(TIM_EventSource));
+
+  /* Set the event sources */
+  TIMx->EGR |= TIM_EventSource;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_OC1PolarityConfig
+* Description    : Configures the TIMx channel 1 polarity.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_OCPolarity: specifies the OC1 Polarity
+*                    This parmeter can be one of the following values:
+*                       - TIM_OCPolarity_High: Output Compare active high
+*                       - TIM_OCPolarity_Low: Output Compare active low
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity)
+{
+  u32 tmpccer = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+  tmpccer = TIMx->CCER;
+
+  /* Set or Reset the CC1P Bit */
+  tmpccer &= CCER_CC1P_Mask;
+  tmpccer |= TIM_OCPolarity;
+
+  TIMx->CCER = (u16)tmpccer;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_OC2PolarityConfig
+* Description    : Configures the TIMx channel 2 polarity.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_OCPolarity: specifies the OC2 Polarity
+*                    This parmeter can be one of the following values:
+*                       - TIM_OCPolarity_High: Output Compare active high
+*                       - TIM_OCPolarity_Low: Output Compare active low
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity)
+{
+  u32 tmpccer = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+  tmpccer = TIMx->CCER;
+
+  /* Set or Reset the CC2P Bit */
+  tmpccer &= CCER_CC2P_Mask;
+  tmpccer |= (u16)((u16)TIM_OCPolarity << 4);
+
+  TIMx->CCER = (u16)tmpccer;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_OC3PolarityConfig
+* Description    : Configures the TIMx channel 3 polarity.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_OCPolarity: specifies the OC3 Polarity
+*                    This parmeter can be one of the following values:
+*                       - TIM_OCPolarity_High: Output Compare active high
+*                       - TIM_OCPolarity_Low: Output Compare active low
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity)
+{
+  u32 tmpccer = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+  tmpccer = TIMx->CCER;
+
+  /* Set or Reset the CC3P Bit */
+  tmpccer &= CCER_CC3P_Mask;
+  tmpccer |= (u16)((u16)TIM_OCPolarity << 8);
+
+  TIMx->CCER = (u16)tmpccer;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_OC4PolarityConfig
+* Description    : Configures the TIMx channel 4 polarity.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_OCPolarity: specifies the OC4 Polarity
+*                    This parmeter can be one of the following values:
+*                       - TIM_OCPolarity_High: Output Compare active high
+*                       - TIM_OCPolarity_Low: Output Compare active low
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity)
+{
+  u32 tmpccer = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+  tmpccer = TIMx->CCER;
+
+  /* Set or Reset the CC4P Bit */
+  tmpccer &= CCER_CC4P_Mask;
+  tmpccer |= (u16)((u16)TIM_OCPolarity << 12);
+
+  TIMx->CCER = (u16)tmpccer;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_UpdateRequestConfig
+* Description    : Configures the TIMx Update Request Interrupt source.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_UpdateSource: specifies the Update source.
+*                    This parameter can be one of the following values:
+*                       - TIM_UpdateSource_Regular
+*                       - TIM_UpdateSource_Global
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, u16 TIM_UpdateSource)
+{
+  u32 tmpcr1 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
+
+  tmpcr1 = TIMx->CR1;
+
+  if (TIM_UpdateSource == TIM_UpdateSource_Regular)
+  {
+    /* Set the URS Bit */
+    tmpcr1 |= CR1_URS_Set;
+  }
+  else
+  {
+    /* Reset the URS Bit */
+    tmpcr1 &= CR1_URS_Reset;
+  }
+  TIMx->CR1 = (u16)tmpcr1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_SelectHallSensor
+* Description    : Enables or disables the TIMx’s Hall sensor interface.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - Newstate: new state of the TIMx Hall sensor interface.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState Newstate)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(Newstate));
+
+  if (Newstate != DISABLE)
+  {
+    /* Set the TI1S Bit */
+    TIMx->CR2 |= CR2_TI1S_Set;
+  }
+  else
+  {
+    /* Reset the TI1S Bit */
+    TIMx->CR2 &= CR2_TI1S_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : TIM_SelectOnePulseMode
+* Description    : Selects the TIMx’s One Pulse Mode.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_OPMode: specifies the OPM Mode to be used.
+*                    This parameter can be one of the following values:
+*                       - TIM_OPMode_Single
+*                       - TIM_OPMode_Repetitive
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, u16 TIM_OPMode)
+{
+  u32 tmpcr1 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_OPM_MODE(TIM_OPMode));
+
+  tmpcr1 = TIMx->CR1;
+
+  /* Reset the OPM Bit */
+  tmpcr1 &= CR1_OPM_Mask;
+
+  /* Configure the OPM Mode */
+  tmpcr1 |= TIM_OPMode;
+
+  TIMx->CR1 = (u16)tmpcr1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_SelectOutputTrigger
+* Description    : Selects the TIMx Trigger Output Mode.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_TRGOSource: specifies the Trigger Output source.
+*                    This paramter can be one of the following values:
+*                       - TIM_TRGOSource_Reset
+*                       - TIM_TRGOSource_Enable
+*                       - TIM_TRGOSource_Update
+*                       - TIM_TRGOSource_OC1
+*                       - TIM_TRGOSource_OC1Ref
+*                       - TIM_TRGOSource_OC2Ref
+*                       - TIM_TRGOSource_OC3Ref
+*                       - TIM_TRGOSource_OC4Ref
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, u16 TIM_TRGOSource)
+{
+  u32 tmpcr2 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
+
+  tmpcr2 = TIMx->CR2;
+  /* Reset the MMS Bits */
+  tmpcr2 &= CR2_MMS_Mask;
+
+  /* Select the TRGO source */
+  tmpcr2 |=  TIM_TRGOSource;
+
+  TIMx->CR2 = (u16)tmpcr2;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_SelectSlaveMode
+* Description    : Selects the TIMx Slave Mode.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_SlaveMode: specifies the Timer Slave Mode.
+*                    This paramter can be one of the following values:
+*                       - TIM_SlaveMode_Reset
+*                       - TIM_SlaveMode_Gated
+*                       - TIM_SlaveMode_Trigger
+*                       - TIM_SlaveMode_External1
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, u16 TIM_SlaveMode)
+{
+  u32 tmpsmcr = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
+
+  tmpsmcr = TIMx->SMCR;
+
+  /* Reset the SMS Bits */
+  tmpsmcr &= SMCR_SMS_Mask;
+
+  /* Select the Slave Mode */
+  tmpsmcr |= TIM_SlaveMode;
+
+  TIMx->SMCR = (u16)tmpsmcr;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_SelectMasterSlaveMode
+* Description    : Sets or Resets the TIMx Master/Slave Mode.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
+*                    This paramter can be one of the following values:
+*                       - TIM_MasterSlaveMode_Enable: synchronization between the
+*                         current timer and its slaves (through TRGO).
+*                       - TIM_MasterSlaveMode_Disable: No action
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, u16 TIM_MasterSlaveMode)
+{
+  u32 tmpsmcr = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
+
+  tmpsmcr = TIMx->SMCR;
+
+  /* Set or Reset the MSM Bit */
+  tmpsmcr &= SMCR_MSM_Mask;
+  tmpsmcr |= TIM_MasterSlaveMode;
+
+  TIMx->SMCR = (u16)tmpsmcr;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_SetAutoreload
+* Description    : Sets the TIMx Autoreload Register value
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - Autoreload: specifies the Autoreload register new value.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, u16 Autoreload)
+{
+  /* Set the Autoreload Register value */
+  TIMx->ARR = Autoreload;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_SetCompare1
+* Description    : Sets the TIMx Capture Compare1 Register value
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - Compare1: specifies the Capture Compare1 register new value.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_SetCompare1(TIM_TypeDef* TIMx, u16 Compare1)
+{
+  /* Set the Capture Compare1 Register value */
+  TIMx->CCR1 = Compare1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_SetCompare2
+* Description    : Sets the TIMx Capture Compare2 Register value
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - Compare2: specifies the Capture Compare2 register new value.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_SetCompare2(TIM_TypeDef* TIMx, u16 Compare2)
+{
+  /* Set the Capture Compare2 Register value */
+  TIMx->CCR2 = Compare2;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_SetCompare3
+* Description    : Sets the TIMx Capture Compare3 Register value
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - Compare3: specifies the Capture Compare3 register new value.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_SetCompare3(TIM_TypeDef* TIMx, u16 Compare3)
+{
+  /* Set the Capture Compare3 Register value */
+  TIMx->CCR3 = Compare3;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_SetCompare4
+* Description    : Sets the TIMx Capture Compare4 Register value
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - Compare4: specifies the Capture Compare4 register new value.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_SetCompare4(TIM_TypeDef* TIMx, u16 Compare4)
+{
+  /* Set the Capture Compare4 Register value */
+  TIMx->CCR4 = Compare4;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_SetIC1Prescaler
+* Description    : Sets the TIMx Input Capture 1 prescaler.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_IC1Prescaler: specifies the Input Capture1 prescaler
+*                    new value.
+*                    This parameter can be one of the following values:
+*                       - TIM_ICPSC_DIV1: no prescaler
+*                       - TIM_ICPSC_DIV2: capture is done once every 2 events
+*                       - TIM_ICPSC_DIV4: capture is done once every 4 events
+*                       - TIM_ICPSC_DIV8: capture is done once every 8 events
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC1Prescaler)
+{
+  u32 tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_IC_PRESCALER(TIM_IC1Prescaler));
+
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the IC1PSC Bits */
+  tmpccmr1 &= CCMR_IC13PSC_Mask;
+
+  /* Set the IC1PSC value */
+  tmpccmr1 |= TIM_IC1Prescaler;
+
+  TIMx->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_SetIC2Prescaler
+* Description    : Sets the TIMx Input Capture 2 prescaler.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_IC2Prescaler: specifies the Input Capture2 prescaler
+*                    new value.
+*                    This parameter can be one of the following values:
+*                       - TIM_ICPSC_DIV1: no prescaler
+*                       - TIM_ICPSC_DIV2: capture is done once every 2 events
+*                       - TIM_ICPSC_DIV4: capture is done once every 4 events
+*                       - TIM_ICPSC_DIV8: capture is done once every 8 events
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC2Prescaler)
+{
+  u32 tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_IC_PRESCALER(TIM_IC2Prescaler));
+
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the IC2PSC Bits */
+  tmpccmr1 &= CCMR_IC24PSC_Mask;
+
+  /* Set the IC2PSC value */
+  tmpccmr1 |= (u16)((u16)TIM_IC2Prescaler << 8);
+
+  TIMx->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_SetIC3Prescaler
+* Description    : Sets the TIMx Input Capture 3 prescaler.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_IC3Prescaler: specifies the Input Capture3 prescaler
+*                    new value.
+*                    This parameter can be one of the following values:
+*                       - TIM_ICPSC_DIV1: no prescaler
+*                       - TIM_ICPSC_DIV2: capture is done once every 2 events
+*                       - TIM_ICPSC_DIV4: capture is done once every 4 events
+*                       - TIM_ICPSC_DIV8: capture is done once every 8 events
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC3Prescaler)
+{
+  u32 tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_IC_PRESCALER(TIM_IC3Prescaler));
+
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the IC3PSC Bits */
+  tmpccmr2 &= CCMR_IC13PSC_Mask;
+
+  /* Set the IC3PSC value */
+  tmpccmr2 |= TIM_IC3Prescaler;
+
+  TIMx->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_SetIC4Prescaler
+* Description    : Sets the TIMx Input Capture 4 prescaler.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_IC4Prescaler: specifies the Input Capture4 prescaler
+*                    new value.
+*                    This parameter can be one of the following values:
+*                      - TIM_ICPSC_DIV1: no prescaler
+*                      - TIM_ICPSC_DIV2: capture is done once every 2 events
+*                      - TIM_ICPSC_DIV4: capture is done once every 4 events
+*                      - TIM_ICPSC_DIV8: capture is done once every 8 events
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC4Prescaler)
+{
+  u32 tmpccmr2 = 0;
+   
+  /* Check the parameters */
+  assert(IS_TIM_IC_PRESCALER(TIM_IC4Prescaler));
+
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the IC4PSC Bits */
+  tmpccmr2 &= CCMR_IC24PSC_Mask;
+
+  /* Set the IC4PSC value */
+  tmpccmr2 |= (u16)((u16)TIM_IC4Prescaler << 8);
+
+  TIMx->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_SetClockDivision
+* Description    : Sets the TIMx Clock Division value.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_CKD: specifies the clock division value.
+*                    This parameter can be one of the following value:
+*                       - TIM_CKD_DIV1: TDTS = Tck_tim
+*                       - TIM_CKD_DIV2: TDTS = 2*Tck_tim
+*                       - TIM_CKD_DIV4: TDTS = 4*Tck_tim
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, u16 TIM_CKD)
+{
+  u32 tmpcr1 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM_CKD_DIV(TIM_CKD));
+
+  tmpcr1 = TIMx->CR1;
+
+  /* Reset the CKD Bits */
+  tmpcr1 &= CR1_CKD_Mask;
+
+  /* Set the CKD value */
+  tmpcr1 |= TIM_CKD;
+
+  TIMx->CR1 = (u16)tmpcr1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_GetCapture1
+* Description    : Gets the TIMx Input Capture 1 value.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* Output         : None
+* Return         : Capture Compare 1 Register value.
+*******************************************************************************/
+u16 TIM_GetCapture1(TIM_TypeDef* TIMx)
+{
+  /* Get the Capture 1 Register value */
+  return TIMx->CCR1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_GetCapture2
+* Description    : Gets the TIMx Input Capture 2 value.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* Output         : None
+* Return         : Capture Compare 2 Register value.
+*******************************************************************************/
+u16 TIM_GetCapture2(TIM_TypeDef* TIMx)
+{
+  /* Get the Capture 2 Register value */
+  return TIMx->CCR2;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_GetCapture3
+* Description    : Gets the TIMx Input Capture 3 value.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* Output         : None
+* Return         : Capture Compare 3 Register value.
+*******************************************************************************/
+u16 TIM_GetCapture3(TIM_TypeDef* TIMx)
+{
+  /* Get the Capture 3 Register value */
+  return TIMx->CCR3;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_GetCapture4
+* Description    : Gets the TIMx Input Capture 4 value.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* Output         : None
+* Return         : Capture Compare 4 Register value.
+*******************************************************************************/
+u16 TIM_GetCapture4(TIM_TypeDef* TIMx)
+{
+  /* Get the Capture 4 Register value */
+  return TIMx->CCR4;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_GetCounter
+* Description    : Gets the TIMx Counter value.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* Output         : None
+* Return         : Counter Register value.
+*******************************************************************************/
+u16 TIM_GetCounter(TIM_TypeDef* TIMx)
+{
+  /* Get the Counter Register value */
+  return TIMx->CNT;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_GetPrescaler
+* Description    : Gets the TIMx Prescaler value.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+* Output         : None
+* Return         : Prescaler Register value.
+*******************************************************************************/
+u16 TIM_GetPrescaler(TIM_TypeDef* TIMx)
+{
+  /* Get the Prescaler Register value */
+  return TIMx->PSC;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_GetFlagStatus
+* Description    : Checks whether the specified TIMx flag is set or not.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_FLAG: specifies the flag to check.
+*                    This parameter can be one of the following values:
+*                       - TIM_FLAG_Update: Timer update Flag
+*                       - TIM_FLAG_CC1: Timer Capture Compare 1 Flag
+*                       - TIM_FLAG_CC2: Timer Capture Compare 2 Flag
+*                       - TIM_FLAG_CC3: Timer Capture Compare 3 Flag
+*                       - TIM_FLAG_CC4: Timer Capture Compare 4 Flag
+*                       - TIM_FLAG_Trigger: Timer Trigger Flag
+*                       - TIM_FLAG_CC1OF: Timer Capture Compare 1 overcapture Flag
+*                       - TIM_FLAG_CC2OF: Timer Capture Compare 2 overcapture Flag
+*                       - TIM_FLAG_CC3OF: Timer Capture Compare 3 overcapture Flag
+*                       - TIM_FLAG_CC4OF: Timer Capture Compare 4 overcapture Flag
+* Output         : None
+* Return         : The new state of TIM_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert(IS_TIM_GET_FLAG(TIM_FLAG));
+
+  if ((TIMx->SR & TIM_FLAG) != (u16)RESET )
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_ClearFlag
+* Description    : Clears the TIMx's pending flags.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_FLAG: specifies the flag bit to clear.
+*                    This parameter can be any combination of the following values:
+*                       - TIM_FLAG_Update: Timer update Flag
+*                       - TIM_FLAG_CC1: Timer Capture Compare 1 Flag
+*                       - TIM_FLAG_CC2: Timer Capture Compare 2 Flag
+*                       - TIM_FLAG_CC3: Timer Capture Compare 3 Flag
+*                       - TIM_FLAG_CC4: Timer Capture Compare 4 Flag
+*                       - TIM_FLAG_Trigger: Timer Trigger Flag
+*                       - TIM_FLAG_CC1OF: Timer Capture Compare 1 overcapture Flag
+*                       - TIM_FLAG_CC2OF: Timer Capture Compare 2 overcapture Flag
+*                       - TIM_FLAG_CC3OF: Timer Capture Compare 3 overcapture Flag
+*                       - TIM_FLAG_CC4OF: Timer Capture Compare 4 overcapture Flag
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG)
+{
+  /* Check the parameters */
+  assert(IS_TIM_CLEAR_FLAG(TIM_FLAG));
+
+  /* Clear the flags */
+  TIMx->SR &= (u16)~TIM_FLAG;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_GetITStatus
+* Description    : Checks whether the TIMx interrupt has occurred or not.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_IT: specifies the TIM interrupt source to check.
+*                    This parameter can be one of the following values:
+*                         - TIM_IT_Update: Timer update Interrupt source
+*                         - TIM_IT_CC1: Timer Capture Compare 1 Interrupt source
+*                         - TIM_IT_CC2: Timer Capture Compare 2 Interrupt source
+*                         - TIM_IT_CC3: Timer Capture Compare 3 Interrupt source
+*                         - TIM_IT_CC4: Timer Capture Compare 4 Interrupt source
+*                         - TIM_IT_Trigger: Timer Trigger Interrupt source
+* Output         : None
+* Return         : The new state of the TIM_IT(SET or RESET).
+*******************************************************************************/
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT)
+{
+  ITStatus bitstatus = RESET;
+  
+  u16 itstatus = 0x0, itenable = 0x0;
+
+  /* Check the parameters */
+  assert(IS_TIM_GET_IT(TIM_IT));
+  
+  itstatus = TIMx->SR & TIM_IT;
+  
+  itenable = TIMx->DIER & TIM_IT;
+
+  if ((itstatus != (u16)RESET)  && (itenable != (u16)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : TIM_ClearITPendingBit
+* Description    : Clears the TIMx's interrupt pending bits.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_IT: specifies the pending bit to clear.
+*                    This parameter can be any combination of the following values:
+*                       - TIM_IT_Update: Timer update Interrupt source
+*                       - TIM_IT_CC1: Timer Capture Compare 1 Interrupt source
+*                       - TIM_IT_CC2: Timer Capture Compare 2 Interrupt source
+*                       - TIM_IT_CC3: Timer Capture Compare 3 Interrupt source
+*                       - TIM_IT_CC4: Timer Capture Compare 4 Interrupt source
+*                       - TIM_IT_Trigger: Timer Trigger Interrupt source
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT)
+{
+  /* Check the parameters */
+  assert(IS_TIM_IT(TIM_IT));
+  
+  /* Clear the IT pending Bit */
+  TIMx->SR &= (u16)~TIM_IT;
+}
+
+/*******************************************************************************
+* Function Name  : PWMInput_Config
+* Description    : Configures the TIM peripheral according to the specified
+*                  parameters in the TIM_ICInitStruct to measure an external PWM
+*                  signal.
+* Input          : - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
+*                    that contains the configuration information for the specified
+*                    TIM peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+static void PWMI_Config(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+  u8 ICPolarity = TIM_ICPolarity_Rising;
+  u8 ICSelection = TIM_ICSelection_DirectTI;
+
+  /* Select the Opposite Input Polarity */
+  if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
+  {
+    ICPolarity = TIM_ICPolarity_Falling;
+  }
+  else
+  {
+    ICPolarity = TIM_ICPolarity_Rising;
+  }
+
+  /* Select the Opposite Input */
+  if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
+  {
+    ICSelection = TIM_ICSelection_IndirectTI;
+  }
+  else
+  {
+    ICSelection = TIM_ICSelection_DirectTI;
+  }
+
+  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+  {
+    /* TI1 Configuration */
+    TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+
+    /* TI2 Configuration */
+    TI2_Config(TIMx, ICPolarity, ICSelection, TIM_ICInitStruct->TIM_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+  else
+  {	 
+    /* TI1 Configuration */
+    TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+
+    /* TI2 Configuration */
+    TI1_Config(TIMx, ICPolarity, ICSelection, TIM_ICInitStruct->TIM_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : TI1_Config
+* Description    : Configure the TI1 as Input.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_ICPolarity : The Input Polarity.
+*                    This parameter can be one of the following values:
+*                       - TIM_ICPolarity_Rising
+*                       - TIM_ICPolarity_Falling
+*                  - TIM_ICSelection: specifies the input to be used.
+*                    This parameter can be one of the following values:
+*                       - TIM_ICSelection_DirectTI: TIM Input 1 is selected to
+*                         be connected to IC1.
+*                       - TIM_ICSelection_IndirectTI: TIM Input 1 is selected to
+*                         be connected to IC2.
+*                       - TIM_ICSelection_TRGI: TIM Input 1 is selected to be
+*                         connected to TRGI.
+*                  - TIM_ICFilter: Specifies the Input Capture Filter.
+*                    This parameter must be a value between 0x00 and 0x0F.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+static void TI1_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
+                       u8 TIM_ICFilter)
+{
+  u32 tmpccmr1 = 0, tmpccer = 0;
+
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Disable the Channel 1: Reset the CCE Bit */
+  TIMx->CCER &= CCRE_CC1E_Reset;
+
+  /* Select the Input and set the filter */
+  tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
+  tmpccmr1 |= TIM_ICSelection | (u16)((u16)TIM_ICFilter << 4);
+
+  /* Select the Polarity  and set the CCE Bit */
+  tmpccer &= CCER_CC1P_Mask & CCRE_CC1E_Mask;
+  tmpccer |= TIM_ICPolarity | CCRE_CC1E_Set;
+
+  TIMx->CCMR1 = 0x0000;
+  TIMx->CCMR1 = (u16)tmpccmr1;
+  TIMx->CCER = (u16)tmpccer;
+}
+
+/*******************************************************************************
+* Function Name  : TI2_Config
+* Description    : Configure the TI2 as Input.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_ICPolarity : The Input Polarity.
+*                    This parameter can be one of the following values:
+*                       - TIM_ICPolarity_Rising
+*                       - TIM_ICPolarity_Falling
+*                  - TIM_ICSelection: specifies the input to be used.
+*                    This parameter can be one of the following values:
+*                       - TIM_ICSelection_DirectTI: TIM Input 2 is selected to
+*                         be connected to IC2.
+*                       - TIM_ICSelection_IndirectTI: TIM Input 2 is selected to
+*                         be connected to IC1.
+*                       - TIM_ICSelection_TRGI: TIM Input 2 is selected to be
+*                         connected to TRGI.
+*                  - TIM_ICFilter: Specifies the Input Capture Filter.
+*                    This parameter must be a value between 0x00 and 0x0F.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+static void TI2_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
+                       u8 TIM_ICFilter)
+{
+  u32 tmpccmr1 = 0, tmpccer = 0, tmp = 0;
+
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+  tmp = (u16)((u16)TIM_ICPolarity << 4);
+
+  /* Disable the Channel 2: Reset the CCE Bit */
+  TIMx->CCER &= CCRE_CC2E_Reset;
+
+  /* Select the Input and set the filter */
+  tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
+  tmpccmr1 |= (u16)((u16)TIM_ICFilter << 12);
+  tmpccmr1 |= (u16)((u16)TIM_ICSelection << 8);
+
+  /* Select the Polarity  and set the CCE Bit */
+  tmpccer &= CCER_CC2P_Mask & CCRE_CC2E_Mask;
+  tmpccer |=  tmp | CCRE_CC2E_Set;
+
+  TIMx->CCMR1 = (u16)tmpccmr1 ;
+  TIMx->CCER = (u16)tmpccer;
+}
+
+/*******************************************************************************
+* Function Name  : TI3_Config
+* Description    : Configure the TI3 as Input.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_ICPolarity : The Input Polarity.
+*                    This parameter can be one of the following values:
+*                       - TIM_ICPolarity_Rising
+*                       - TIM_ICPolarity_Falling
+*                  - TIM_ICSelection: specifies the input to be used.
+*                    This parameter can be one of the following values:
+*                       - TIM_ICSelection_DirectTI: TIM Input 3 is selected to
+*                         be connected to IC3.
+*                       - TIM_ICSelection_IndirectTI: TIM Input 3 is selected to
+*                         be connected to IC4.
+*                       - TIM_ICSelection_TRGI: TIM Input 3 is selected to be
+*                         connected to TRGI.
+*                  - TIM_ICFilter: Specifies the Input Capture Filter.
+*                    This parameter must be a value between 0x00 and 0x0F.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+static void TI3_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
+                       u8 TIM_ICFilter)
+{
+  u32 tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+  tmp = (u16)((u16)TIM_ICPolarity << 8);
+
+  /* Disable the Channel 3: Reset the CCE Bit */
+  TIMx->CCER &= CCRE_CC3E_Reset;
+
+  /* Select the Input and set the filter */
+  tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
+  tmpccmr2 |= TIM_ICSelection | (u16)((u16)TIM_ICFilter << 4);
+
+  /* Select the Polarity  and set the CCE Bit */
+  tmpccer &= CCER_CC1P_Mask & CCRE_CC1E_Mask;
+  tmpccer |= tmp | CCRE_CC3E_Set;
+
+  TIMx->CCMR2 = (u16)tmpccmr2;
+  TIMx->CCER = (u16)tmpccer;
+}
+
+/*******************************************************************************
+* Function Name  : TI4_Config
+* Description    : Configure the TI1 as Input.
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_ICPolarity : The Input Polarity.
+*                    This parameter can be one of the following values:
+*                       - TIM_ICPolarity_Rising
+*                       - TIM_ICPolarity_Falling
+*                  - TIM_ICSelection: specifies the input to be used.
+*                    This parameter can be one of the following values:
+*                       - TIM_ICSelection_DirectTI: TIM Input 4 is selected to
+*                         be connected to IC4.
+*                       - TIM_ICSelection_IndirectTI: TIM Input 4 is selected to
+*                         be connected to IC3.
+*                       - TIM_ICSelection_TRGI: TIM Input 4 is selected to be
+*                         connected to TRGI.
+*                  - TIM_ICFilter: Specifies the Input Capture Filter.
+*                    This parameter must be a value between 0x00 and 0x0F.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+static void TI4_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
+                       u8 TIM_ICFilter)
+{
+  u32 tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+  tmp = (u16)((u16)TIM_ICPolarity << 12);
+
+  /* Disable the Channel 4: Reset the CCE Bit */
+  TIMx->CCER &= CCRE_CC4E_Reset;
+
+  /* Select the Input and set the filter */
+  tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
+  tmpccmr2 |= (u16)((u16)TIM_ICSelection << 8) | (u16)((u16)TIM_ICFilter << 12);
+
+  /* Select the Polarity  and set the CCE Bit */
+  tmpccer &= CCER_CC4P_Mask & CCRE_CC4E_Mask;
+  tmpccer |= tmp | CCRE_CC4E_Set;
+
+  TIMx->CCMR2 = (u16)tmpccmr2;
+  TIMx->CCER = (u16)tmpccer ;
+}
+
+/*******************************************************************************
+* Function Name  : ETR_Config
+* Description    : Configure the External Trigger
+* Input          : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
+*                  - TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+*                    This parameter can be one of the following values:
+*                       - TIM_ExtTRGPSC_OFF
+*                       - TIM_ExtTRGPSC_DIV2
+*                       - TIM_ExtTRGPSC_DIV4
+*                       - TIM_ExtTRGPSC_DIV8
+*                  - TIM_ExtTRGPolarity: The external Trigger Polarity.
+*                    This parameter can be one of the following values:
+*                       - TIM_ExtTRGPolarity_Inverted
+*                       - TIM_ExtTRGPolarity_NonInverted
+*                  - ExtTRGFilter: External Trigger Filter.
+*                    This parameter must be a value between 0x00 and 0x0F.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+static void ETR_Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,
+                       u8 ExtTRGFilter)
+{
+  u32 tmpsmcr = 0;
+
+  tmpsmcr = TIMx->SMCR;
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr &= SMCR_ETR_Mask;
+  tmpsmcr |= TIM_ExtTRGPrescaler | TIM_ExtTRGPolarity | (u16)((u16)ExtTRGFilter << 8);
+
+  TIMx->SMCR = (u16)tmpsmcr;
+}
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_tim1.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_tim1.c
new file mode 100644
index 0000000..deac420
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_tim1.c
@@ -0,0 +1,2664 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_tim1.c
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file provides all the TIM1 software functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* mm/dd/yyyy: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_tim1.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* ------------ TIM1 registers bit address in the alias region ----------- */
+#define TIM1_OFFSET    (TIM1_BASE - PERIPH_BASE)
+
+/* --- TIM1 CR1 Register ---*/
+/* Alias word address of CEN bit */
+#define CR1_OFFSET        (TIM1_OFFSET + 0x00)
+#define CEN_BitNumber     0x00
+#define CR1_CEN_BB        (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (CEN_BitNumber * 4))
+
+/* Alias word address of UDIS bit */
+#define UDIS_BitNumber    0x01
+#define CR1_UDIS_BB       (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (UDIS_BitNumber * 4))
+
+/* Alias word address of URS bit */
+#define URS_BitNumber     0x02
+#define CR1_URS_BB        (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (URS_BitNumber * 4))
+
+/* Alias word address of OPM bit */
+#define OPM_BitNumber     0x03
+#define CR1_OPM_BB        (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (OPM_BitNumber * 4))
+
+/* Alias word address of ARPE bit */
+#define ARPE_BitNumber    0x07
+#define CR1_ARPE_BB       (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (ARPE_BitNumber * 4))
+
+/* --- TIM1 CR2 Register --- */
+/* Alias word address of CCPC bit */
+#define CR2_OFFSET        (TIM1_OFFSET + 0x04)
+#define CCPC_BitNumber    0x00
+#define CR2_CCPC_BB       (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCPC_BitNumber * 4))
+
+/* Alias word address of CCUS bit */
+#define CCUS_BitNumber    0x02
+#define CR2_CCUS_BB       (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCUS_BitNumber * 4))
+
+/* Alias word address of CCDS bit */
+#define CCDS_BitNumber    0x03
+#define CR2_CCDS_BB       (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCDS_BitNumber * 4))
+
+/* Alias word address of TI1S bit */
+#define TI1S_BitNumber    0x07
+#define CR2_TI1S_BB       (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (TI1S_BitNumber * 4))
+
+/* Alias word address of OIS1 bit */
+#define OIS1_BitNumber    0x08
+#define CR2_OIS1_BB       (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS1_BitNumber * 4))
+
+/* Alias word address of OIS1N bit */
+#define OIS1N_BitNumber   0x09
+#define CR2_OIS1N_BB      (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS1N_BitNumber * 4))
+
+/* Alias word address of OIS2 bit */
+#define OIS2_BitNumber    0x0A
+#define CR2_OIS2_BB      (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS2_BitNumber * 4))
+
+/* Alias word address of OIS2N bit */
+#define OIS2N_BitNumber   0x0B
+#define CR2_OIS2N_BB      (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS2N_BitNumber * 4))
+
+/* Alias word address of OIS3 bit */
+#define OIS3_BitNumber    0x0C
+#define CR2_OIS3_BB       (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS3_BitNumber * 4))
+
+/* Alias word address of OIS3N bit */
+#define OIS3N_BitNumber   0x0D
+#define CR2_OIS3N_BB      (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS3N_BitNumber * 4))
+
+/* Alias word address of OIS4 bit */
+#define OIS4_BitNumber    0x0E
+#define CR2_OIS4_BB       (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS4_BitNumber * 4))
+
+/* --- TIM1 SMCR Register --- */
+/* Alias word address of MSM bit */
+#define SMCR_OFFSET       (TIM1_OFFSET + 0x08)
+#define MSM_BitNumber     0x07
+#define SMCR_MSM_BB       (PERIPH_BB_BASE + (SMCR_OFFSET * 32) + (MSM_BitNumber * 4))
+
+/* Alias word address of ECE bit */
+#define ECE_BitNumber     0x0E
+#define SMCR_ECE_BB       (PERIPH_BB_BASE + (SMCR_OFFSET * 32) + (ECE_BitNumber * 4))
+
+/* --- TIM1 EGR Register --- */
+/* Alias word address of UG bit */
+#define EGR_OFFSET        (TIM1_OFFSET + 0x14)
+#define UG_BitNumber      0x00
+#define EGR_UG_BB         (PERIPH_BB_BASE + (EGR_OFFSET * 32) + (UG_BitNumber * 4))
+
+/* --- TIM1 CCER Register --- */
+/* Alias word address of CC1E bit */
+#define CCER_OFFSET       (TIM1_OFFSET + 0x20)
+#define CC1E_BitNumber    0x00
+#define CCER_CC1E_BB      (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1E_BitNumber * 4))
+
+/* Alias word address of CC1P bit */
+#define CC1P_BitNumber    0x01
+#define CCER_CC1P_BB      (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1P_BitNumber * 4))
+
+/* Alias word address of CC1NE bit */
+#define CC1NE_BitNumber   0x02
+#define CCER_CC1NE_BB     (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1NE_BitNumber * 4))
+
+/* Alias word address of CC1NP bit */
+#define CC1NP_BitNumber   0x03
+#define CCER_CC1NP_BB     (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1NP_BitNumber * 4))
+
+/* Alias word address of CC2E bit */
+#define CC2E_BitNumber    0x04
+#define CCER_CC2E_BB      (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2E_BitNumber * 4))
+
+/* Alias word address of CC2P bit */
+#define CC2P_BitNumber    0x05
+#define CCER_CC2P_BB      (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2P_BitNumber * 4))
+
+/* Alias word address of CC2NE bit */
+#define CC2NE_BitNumber   0x06
+#define CCER_CC2NE_BB     (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2NE_BitNumber * 4))
+
+/* Alias word address of CC2NP bit */
+#define CC2NP_BitNumber   0x07
+#define CCER_CC2NP_BB     (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2NP_BitNumber * 4))
+
+/* Alias word address of CC3E bit */
+#define CC3E_BitNumber    0x08
+#define CCER_CC3E_BB      (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3E_BitNumber * 4))
+
+/* Alias word address of CC3P bit */
+#define CC3P_BitNumber    0x09
+#define CCER_CC3P_BB      (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3P_BitNumber * 4))
+
+/* Alias word address of CC3NE bit */
+#define CC3NE_BitNumber   0x0A
+#define CCER_CC3NE_BB     (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3NE_BitNumber * 4))
+
+/* Alias word address of CC3NP bit */
+#define CC3NP_BitNumber   0x0B
+#define CCER_CC3NP_BB     (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3NP_BitNumber * 4))
+
+/* Alias word address of CC4E bit */
+#define CC4E_BitNumber    0x0C
+#define CCER_CC4E_BB      (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC4E_BitNumber * 4))
+
+/* Alias word address of CC4P bit */
+#define CC4P_BitNumber    0x0D
+#define CCER_CC4P_BB      (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC4P_BitNumber * 4))
+
+/* --- TIM1 BDTR Register --- */
+/* Alias word address of MOE bit */
+#define BDTR_OFFSET       (TIM1_OFFSET + 0x44)
+#define MOE_BitNumber     0x0F
+#define BDTR_MOE_BB       (PERIPH_BB_BASE + (BDTR_OFFSET * 32) + (MOE_BitNumber * 4))
+
+/* --- TIM1 CCMR1 Register --- */
+/* Alias word address of OC1FE bit */
+#define CCMR1_OFFSET      (TIM1_OFFSET + 0x18)
+#define OC1FE_BitNumber   0x02
+#define CCMR1_OC1FE_BB    (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1FE_BitNumber * 4))
+
+/* Alias word address of OC1PE bit */
+#define OC1PE_BitNumber   0x03
+#define CCMR1_OC1PE_BB    (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1PE_BitNumber * 4))
+
+/* Alias word address of OC2FE bit */
+#define OC2FE_BitNumber   0x0A
+#define CCMR1_OC2FE_BB    (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC2FE_BitNumber * 4))
+
+/* Alias word address of OC2PE bit */
+#define OC2PE_BitNumber   0x0B
+#define CCMR1_OC2PE_BB    (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC2PE_BitNumber * 4))
+
+/* --- TIM1 CCMR2 Register ---- */
+/* Alias word address of OC3FE bit */
+#define CCMR2_OFFSET      (TIM1_OFFSET + 0x1C)
+#define OC3FE_BitNumber   0x02
+#define CCMR2_OC3FE_BB    (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC3FE_BitNumber * 4))
+
+/* Alias word address of OC3PE bit */
+#define OC3PE_BitNumber   0x03
+#define CCMR2_OC3PE_BB    (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC3PE_BitNumber * 4))
+
+/* Alias word address of OC4FE bit */
+#define OC4FE_BitNumber   0x0A
+#define CCMR2_OC4FE_BB    (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC4FE_BitNumber * 4))
+
+/* Alias word address of OC4PE bit */
+#define OC4PE_BitNumber   0x0B
+#define CCMR2_OC4PE_BB    (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC4PE_BitNumber * 4))
+
+/* --------------------- TIM1 registers bit mask ------------------------- */
+/* TIM1 CR1 Mask */
+#define CR1_CounterMode_Mask                ((u16)0x039F)
+#define CR1_CKD_Mask                        ((u16)0x00FF)
+
+/* TIM1 CR2 Mask */
+#define CR2_MMS_Mask                        ((u16)0x0080)
+
+/* TIM1 SMCR Mask */
+#define SMCR_SMS_Mask                       ((u16)0xFFF0)
+#define SMCR_ETR_Mask                       ((u16)0x40F7)
+#define SMCR_TS_Mask                        ((u16)0xFF87)
+#define SMCR_ECE_Set                        ((u16)0x0001)
+
+/* TIM1 CCMRx Mask */
+#define CCMR_CC13S_Mask                     ((u16)0xFFFC)
+#define CCMR_CC24S_Mask                     ((u16)0xFCFF)
+#define CCMR_TI13Direct_Set                 ((u16)0x0001)
+#define CCMR_TI24Direct_Set                 ((u16)0x0100)
+#define CCMR_OCM13_Mask                     ((u16)0x7F0F)
+#define CCMR_OCM24_Mask                     ((u16)0x0F7F)
+#define CCMR_IC13PSC_Mask                   ((u16)0xFFF3)
+#define CCMR_IC24PSC_Mask                   ((u16)0xF3FF)
+#define CCMR_IC13F_Mask                     ((u16)0xFF0F)
+#define CCMR_IC24F_Mask                     ((u16)0x0FFF)
+#define OC13Mode_Mask		                ((u16)0xFF00)
+#define OC24Mode_Mask		                ((u16)0x00FF)
+
+/* TIM1 CCER Set/Reset Bit */
+#define CCER_CCE_Set                        ((u16)0x0001)
+#define CCER_CCE_Reset                      ((u16)0x0000)
+
+/* TIM1 DMA Mask */
+#define DCR_DMA_Mask                        ((u16)0x0000)
+
+/* TIM1 private Masks */
+#define TIM1_Period_Reset_Mask               ((u16)0xFFFF)
+#define TIM1_Prescaler_Reset_Mask            ((u16)0x0000)
+#define TIM1_RepetitionCounter_Reset_Mask    ((u16)0x0000)
+#define TIM1_Pulse_Reset_Mask                ((u16)0x0000)
+#define TIM1_ICFilter_Mask                   ((u8)0x00)
+#define TIM1_DeadTime_Reset_Mask             ((u16)0x0000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void ETR_Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,
+                       u16 ExtTRGFilter);
+static void TI1_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
+                       u8 TIM1_ICFilter);
+static void TI2_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
+                       u8 TIM1_ICFilter);
+static void TI3_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
+                       u8 TIM1_ICFilter);
+static void TI4_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
+                       u8 TIM1_ICFilter);
+
+/*******************************************************************************
+* Function Name  : TIM1_DeInit
+* Description    : Deinitializes the TIM1 peripheral registers to their default
+*                  reset values.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_DeInit(void)
+{
+  RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
+  RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_TimeBaseInit
+* Description    : Initializes the TIM1 Time Base Unit according to the specified
+*                  parameters in the TIM1_TimeBaseInitStruct.
+* Input          : - TIM1_TimeBaseInitStruct: pointer to a TIM1_TimeBaseInitTypeDef
+*                    structure that contains the configuration information for
+*                    the specified TIM1 peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_TimeBaseInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct)
+{
+ /* Check the parameters */
+  assert(IS_TIM1_COUNTER_MODE(TIM1_TimeBaseInitStruct->TIM1_CounterMode));
+  assert(IS_TIM1_CKD_DIV(TIM1_TimeBaseInitStruct->TIM1_ClockDivision));
+
+  /* Set the Autoreload value */
+  TIM1->ARR = TIM1_TimeBaseInitStruct->TIM1_Period ;
+
+  /* Set the Prescaler value */
+  TIM1->PSC = TIM1_TimeBaseInitStruct->TIM1_Prescaler;
+
+  /* Select the Counter Mode and set the clock division */
+  TIM1->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;
+  TIM1->CR1 |= (u32)TIM1_TimeBaseInitStruct->TIM1_ClockDivision |
+               TIM1_TimeBaseInitStruct->TIM1_CounterMode;
+
+  /* Set the Repetition Counter value */
+  TIM1->RCR = TIM1_TimeBaseInitStruct->TIM1_RepetitionCounter;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_OC1Init
+* Description    : Initializes the TIM1 Channel1 according to the specified
+*                  parameters in the TIM1_OCInitStruct.
+* Input          : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
+*                    contains the configuration information for the TIM1 peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_OC1Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
+{
+  u16 tmpccmr = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
+  assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
+  assert(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState));
+  assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
+  assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity));
+  assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
+  assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState)); 
+
+  tmpccmr = TIM1->CCMR1;
+
+  /* Disable the Channel 1: Reset the CCE Bit */
+  *(vu32 *) CCER_CC1E_BB = CCER_CCE_Reset;
+
+  /* Reset the Output Compare Bits */
+   tmpccmr &= OC13Mode_Mask;
+
+  /* Set the Ouput Compare Mode */
+  tmpccmr |= TIM1_OCInitStruct->TIM1_OCMode;
+
+  TIM1->CCMR1 = tmpccmr;
+
+  /* Set the Output State */
+  *(vu32 *) CCER_CC1E_BB = TIM1_OCInitStruct->TIM1_OutputState;
+
+  /* Set the Output N State */
+  *(vu32 *) CCER_CC1NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
+
+  /* Set the Output Polarity */
+  *(vu32 *) CCER_CC1P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
+
+  /* Set the Output N Polarity */
+  *(vu32 *) CCER_CC1NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
+
+  /* Set the Output Idle state */
+  *(vu32 *) CR2_OIS1_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
+
+  /* Set the Output N Idle state */
+  *(vu32 *) CR2_OIS1N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
+
+  /* Set the Pulse value */
+  TIM1->CCR1 = TIM1_OCInitStruct->TIM1_Pulse;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_OC2Init
+* Description    : Initializes the TIM1 Channel2 according to the specified
+*                  parameters in the TIM1_OCInitStruct.
+* Input          : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
+*                    contains the configuration information for the TIM1 peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_OC2Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
+{
+  u32 tmpccmr = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
+  assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
+  assert(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState));
+  assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
+  assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity));
+  assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
+  assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState));
+
+  tmpccmr = TIM1->CCMR1;
+
+  /* Disable the Channel 2: Reset the CCE Bit */
+  *(vu32 *) CCER_CC2E_BB = CCER_CCE_Reset;
+
+  /* Reset the Output Compare Bits */
+   tmpccmr &= OC24Mode_Mask;
+
+  /* Set the Ouput Compare Mode */
+  tmpccmr |= (u32)TIM1_OCInitStruct->TIM1_OCMode << 8;
+
+  TIM1->CCMR1 = (u16)tmpccmr;
+
+  /* Set the Output State */
+  *(vu32 *) CCER_CC2E_BB = TIM1_OCInitStruct->TIM1_OutputState;
+
+  /* Set the Output N State */
+  *(vu32 *) CCER_CC2NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
+
+  /* Set the Output Polarity */
+  *(vu32 *) CCER_CC2P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
+
+  /* Set the Output N Polarity */
+  *(vu32 *) CCER_CC2NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
+
+  /* Set the Output Idle state */
+  *(vu32 *) CR2_OIS2_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
+
+  /* Set the Output N Idle state */
+  *(vu32 *) CR2_OIS2N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
+
+  /* Set the Pulse value */
+  TIM1->CCR2 = TIM1_OCInitStruct->TIM1_Pulse;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_OC3Init
+* Description    : Initializes the TIM1 Channel3 according to the specified
+*                  parameters in the TIM1_OCInitStruct.
+* Input          : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
+*                    contains the configuration information for the TIM1 peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_OC3Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
+{
+  u16 tmpccmr = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
+  assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
+  assert(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState));
+  assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
+  assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity));
+  assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
+  assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState));
+
+  tmpccmr = TIM1->CCMR2;
+
+  /* Disable the Channel 3: Reset the CCE Bit */
+  *(vu32 *) CCER_CC3E_BB = CCER_CCE_Reset;
+
+  /* Reset the Output Compare Bits */
+   tmpccmr &= OC13Mode_Mask;
+
+  /* Set the Ouput Compare Mode */
+  tmpccmr |= TIM1_OCInitStruct->TIM1_OCMode;
+
+  TIM1->CCMR2 = tmpccmr;
+
+  /* Set the Output State */
+  *(vu32 *) CCER_CC3E_BB = TIM1_OCInitStruct->TIM1_OutputState;
+
+  /* Set the Output N State */
+  *(vu32 *) CCER_CC3NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;
+
+  /* Set the Output Polarity */
+  *(vu32 *) CCER_CC3P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
+
+  /* Set the Output N Polarity */
+  *(vu32 *) CCER_CC3NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;
+
+  /* Set the Output Idle state */
+  *(vu32 *) CR2_OIS3_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
+
+  /* Set the Output N Idle state */
+  *(vu32 *) CR2_OIS3N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;
+
+  /* Set the Pulse value */
+  TIM1->CCR3 = TIM1_OCInitStruct->TIM1_Pulse;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_OC4Init
+* Description    : Initializes the TIM1 Channel4 according to the specified
+*                  parameters in the TIM1_OCInitStruct.
+* Input          : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that
+*                    contains the configuration information for the TIM1 peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_OC4Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
+{
+  u32 tmpccmr = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));
+  assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));
+  assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));
+  assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));
+
+  tmpccmr = TIM1->CCMR2;
+
+  /* Disable the Channel 4: Reset the CCE Bit */
+  *(vu32 *) CCER_CC4E_BB = CCER_CCE_Reset;
+
+  /* Reset the Output Compare Bits */
+   tmpccmr &= OC24Mode_Mask;
+
+  /* Set the Ouput Compare Mode */
+  tmpccmr |= (u32)TIM1_OCInitStruct->TIM1_OCMode << 8;
+
+  TIM1->CCMR2 = (u16)tmpccmr;
+
+  /* Set the Output State */
+  *(vu32 *) CCER_CC4E_BB = TIM1_OCInitStruct->TIM1_OutputState;
+
+  /* Set the Output Polarity */
+  *(vu32 *) CCER_CC4P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;
+
+  /* Set the Output Idle state */
+  *(vu32 *) CR2_OIS4_BB = TIM1_OCInitStruct->TIM1_OCIdleState;
+
+  /* Set the Pulse value */
+  TIM1->CCR4 = TIM1_OCInitStruct->TIM1_Pulse;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_BDTRConfig
+* Description    : Configures the: Break feature, dead time, Lock level, the OSSI,
+*                  the OSSR State and the AOE(automatic output enable).
+* Input          : - TIM1_BDTRInitStruct: pointer to a TIM1_BDTRInitTypeDef
+*                    structure that contains the BDTR Register configuration
+*                    information for the TIM1 peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_BDTRConfig(TIM1_BDTRInitTypeDef *TIM1_BDTRInitStruct)
+{
+  u16 tmpbdtr = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM1_OSSR_STATE(TIM1_BDTRInitStruct->TIM1_OSSRState));
+  assert(IS_TIM1_OSSI_STATE(TIM1_BDTRInitStruct->TIM1_OSSIState));
+  assert(IS_TIM1_LOCK_LEVEL(TIM1_BDTRInitStruct->TIM1_LOCKLevel));
+  assert(IS_TIM1_BREAK_STATE(TIM1_BDTRInitStruct->TIM1_Break));
+  assert(IS_TIM1_BREAK_POLARITY(TIM1_BDTRInitStruct->TIM1_BreakPolarity));
+  assert(IS_TIM1_AUTOMATIC_OUTPUT_STATE(TIM1_BDTRInitStruct->TIM1_AutomaticOutput));
+
+  tmpbdtr = TIM1->BDTR;
+
+  /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
+     the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+  tmpbdtr = (u32)TIM1_BDTRInitStruct->TIM1_OSSRState | TIM1_BDTRInitStruct->TIM1_OSSIState |
+             TIM1_BDTRInitStruct->TIM1_LOCKLevel | TIM1_BDTRInitStruct->TIM1_DeadTime |
+			 TIM1_BDTRInitStruct->TIM1_Break | TIM1_BDTRInitStruct->TIM1_BreakPolarity |
+             TIM1_BDTRInitStruct->TIM1_AutomaticOutput;
+
+  TIM1->BDTR = tmpbdtr;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_ICInit
+* Description    : Initializes the TIM1 peripheral according to the specified
+*                  parameters in the TIM1_ICInitStruct.
+* Input          : - TIM1_ICInitStruct: pointer to a TIM1_ICInitTypeDef structure
+*                    that contains the configuration information for the specified
+*                    TIM1 peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_ICInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_CHANNEL(TIM1_ICInitStruct->TIM1_Channel));
+  assert(IS_TIM1_IC_POLARITY(TIM1_ICInitStruct->TIM1_ICPolarity));
+  assert(IS_TIM1_IC_SELECTION(TIM1_ICInitStruct->TIM1_ICSelection));
+  assert(IS_TIM1_IC_PRESCALER(TIM1_ICInitStruct->TIM1_ICPrescaler));
+  assert(IS_TIM1_IC_FILTER(TIM1_ICInitStruct->TIM1_ICFilter));
+
+  if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_1)
+  {
+    /* TI1 Configuration */
+    TI1_Config(TIM1_ICInitStruct->TIM1_ICPolarity,
+               TIM1_ICInitStruct->TIM1_ICSelection,
+               TIM1_ICInitStruct->TIM1_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
+  }
+  else if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_2)
+  {
+    /* TI2 Configuration */
+    TI2_Config(TIM1_ICInitStruct->TIM1_ICPolarity,
+               TIM1_ICInitStruct->TIM1_ICSelection,
+               TIM1_ICInitStruct->TIM1_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM1_SetIC2Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
+  }
+  else if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_3)
+  {
+    /* TI3 Configuration */
+    TI3_Config(TIM1_ICInitStruct->TIM1_ICPolarity,
+               TIM1_ICInitStruct->TIM1_ICSelection,
+               TIM1_ICInitStruct->TIM1_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM1_SetIC3Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
+  }
+  else
+  {
+    /* TI4 Configuration */
+    TI4_Config(TIM1_ICInitStruct->TIM1_ICPolarity,
+               TIM1_ICInitStruct->TIM1_ICSelection,
+               TIM1_ICInitStruct->TIM1_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM1_SetIC4Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_PWMIConfig
+* Description    : Configures the TIM1 peripheral in PWM Input Mode according 
+*                  to the specified parameters in the TIM1_ICInitStruct.
+* Input          : - TIM1_ICInitStruct: pointer to a TIM1_ICInitTypeDef structure
+*                    that contains the configuration information for the specified
+*                    TIM1 peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_PWMIConfig(TIM1_ICInitTypeDef* TIM1_ICInitStruct)
+{
+  u8 ICPolarity = TIM1_ICPolarity_Rising;
+  u8 ICSelection = TIM1_ICSelection_DirectTI;
+
+  /* Check the parameters */
+  assert(IS_TIM1_PWMI_CHANNEL(TIM1_ICInitStruct->TIM1_Channel));
+  assert(IS_TIM1_IC_POLARITY(TIM1_ICInitStruct->TIM1_ICPolarity));
+  assert(IS_TIM1_IC_SELECTION(TIM1_ICInitStruct->TIM1_ICSelection));
+  assert(IS_TIM1_IC_PRESCALER(TIM1_ICInitStruct->TIM1_ICPrescaler));
+
+  /* Select the Opposite Input Polarity */
+  if (TIM1_ICInitStruct->TIM1_ICPolarity == TIM1_ICPolarity_Rising)
+  {
+    ICPolarity = TIM1_ICPolarity_Falling;
+  }
+  else
+  {
+    ICPolarity = TIM1_ICPolarity_Rising;
+  }
+
+  /* Select the Opposite Input */
+  if (TIM1_ICInitStruct->TIM1_ICSelection == TIM1_ICSelection_DirectTI)
+  {
+    ICSelection = TIM1_ICSelection_IndirectTI;
+  }
+  else
+  {
+    ICSelection = TIM1_ICSelection_DirectTI;
+  }
+
+  if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_1)
+  {
+    /* TI1 Configuration */
+    TI1_Config(TIM1_ICInitStruct->TIM1_ICPolarity, TIM1_ICInitStruct->TIM1_ICSelection,
+               TIM1_ICInitStruct->TIM1_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
+
+    /* TI2 Configuration */
+    TI2_Config(ICPolarity, ICSelection, TIM1_ICInitStruct->TIM1_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM1_SetIC2Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
+  }
+  else
+  {	 
+    /* TI2 Configuration */
+    TI2_Config(TIM1_ICInitStruct->TIM1_ICPolarity, TIM1_ICInitStruct->TIM1_ICSelection,
+               TIM1_ICInitStruct->TIM1_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM1_SetIC2Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
+
+    /* TI1 Configuration */
+    TI1_Config(ICPolarity, ICSelection, TIM1_ICInitStruct->TIM1_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);
+  }
+}
+/*******************************************************************************
+* Function Name  : TIM1_OCStructInit
+* Description    : Fills each TIM1_OCInitStruct member with its default value.
+* Input          : - TIM1_OCInitStruct : pointer to a TIM1_OCInitTypeDef structure
+*                    which will be initialized.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_OCStructInit(TIM1_OCInitTypeDef* TIM1_OCInitStruct)
+{
+  /* Set the default configuration */
+  TIM1_OCInitStruct->TIM1_OCMode = TIM1_OCMode_Timing;
+  TIM1_OCInitStruct->TIM1_OutputState = TIM1_OutputState_Disable;
+  TIM1_OCInitStruct->TIM1_OutputNState = TIM1_OutputNState_Disable;
+  TIM1_OCInitStruct->TIM1_Pulse = TIM1_Pulse_Reset_Mask;
+  TIM1_OCInitStruct->TIM1_OCPolarity = TIM1_OCPolarity_High;
+  TIM1_OCInitStruct->TIM1_OCNPolarity = TIM1_OCPolarity_High;
+  TIM1_OCInitStruct->TIM1_OCIdleState = TIM1_OCIdleState_Reset;
+  TIM1_OCInitStruct->TIM1_OCNIdleState = TIM1_OCNIdleState_Reset;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_ICStructInit
+* Description    : Fills each TIM1_ICInitStruct member with its default value.
+* Input          : - TIM1_ICInitStruct : pointer to a TIM1_ICInitTypeDef structure
+*                    which will be initialized.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_ICStructInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct)
+{
+  /* Set the default configuration */
+  TIM1_ICInitStruct->TIM1_Channel = TIM1_Channel_1;
+  TIM1_ICInitStruct->TIM1_ICSelection = TIM1_ICSelection_DirectTI;
+  TIM1_ICInitStruct->TIM1_ICPolarity = TIM1_ICPolarity_Rising;
+  TIM1_ICInitStruct->TIM1_ICPrescaler = TIM1_ICPSC_DIV1;
+  TIM1_ICInitStruct->TIM1_ICFilter = TIM1_ICFilter_Mask;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_TimeBaseStructInit
+* Description    : Fills each TIM1_TimeBaseInitStruct member with its default value.
+* Input          : - TIM1_TimeBaseInitStruct : pointer to a TIM1_TimeBaseInitTypeDef
+*                    structure which will be initialized.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_TimeBaseStructInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct)
+{
+  /* Set the default configuration */
+  TIM1_TimeBaseInitStruct->TIM1_Period = TIM1_Period_Reset_Mask;
+  TIM1_TimeBaseInitStruct->TIM1_Prescaler = TIM1_Prescaler_Reset_Mask;
+  TIM1_TimeBaseInitStruct->TIM1_ClockDivision = TIM1_CKD_DIV1;
+  TIM1_TimeBaseInitStruct->TIM1_CounterMode = TIM1_CounterMode_Up;
+  TIM1_TimeBaseInitStruct->TIM1_RepetitionCounter = TIM1_RepetitionCounter_Reset_Mask;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_BDTRStructInit
+* Description    : Fills each TIM1_BDTRInitStruct member with its default value.
+* Input          : - TIM1_BDTRInitStruct : pointer to a TIM1_BDTRInitTypeDef
+*                    structure which will be initialized.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_BDTRStructInit(TIM1_BDTRInitTypeDef* TIM1_BDTRInitStruct)
+{
+  /* Set the default configuration */
+  TIM1_BDTRInitStruct->TIM1_OSSRState = TIM1_OSSRState_Disable;
+  TIM1_BDTRInitStruct->TIM1_OSSIState = TIM1_OSSIState_Disable;
+  TIM1_BDTRInitStruct->TIM1_LOCKLevel = TIM1_LOCKLevel_OFF;
+  TIM1_BDTRInitStruct->TIM1_DeadTime = TIM1_DeadTime_Reset_Mask;
+  TIM1_BDTRInitStruct->TIM1_Break = TIM1_Break_Disable;
+  TIM1_BDTRInitStruct->TIM1_BreakPolarity = TIM1_BreakPolarity_Low;
+  TIM1_BDTRInitStruct->TIM1_AutomaticOutput = TIM1_AutomaticOutput_Disable;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_Cmd
+* Description    : Enables or disables the TIM1 peripheral.
+* Input          : - Newstate: new state of the TIM1 peripheral.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  /* set or Reset the CEN Bit */
+  *(vu32 *) CR1_CEN_BB = (u16)NewState;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_CtrlPWMOutputs
+* Description    : Enables or disables the TIM1 peripheral Main Outputs.
+* Input          : - Newstate: new state of the TIM1 peripheral Main Outputs.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_CtrlPWMOutputs(FunctionalState Newstate)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(Newstate));
+
+  /* Set or Reset the MOE Bit */
+  *(vu32 *) BDTR_MOE_BB = (u16)Newstate;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_ITConfig
+* Description    : Enables or disables the specified TIM1 interrupts.
+* Input          : - TIM1_IT: specifies the TIM1 interrupts sources to be enabled
+*                    or disabled.
+*                    This parameter can be any combination of the following values:
+*                       - TIM1_IT_Update: TIM1 update Interrupt source
+*                       - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
+*                       - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
+*                       - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
+*                       - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
+*                       - TIM1_IT_CCUpdate: TIM1 Capture Compare Update Interrupt
+*                         source
+*                       - TIM1_IT_Trigger: TIM1 Trigger Interrupt source
+*                       - TIM1_IT_Break: TIM1 Break Interrupt source
+*                  - Newstate: new state of the TIM1 interrupts.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_ITConfig(u16 TIM1_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_IT(TIM1_IT));
+  assert(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState == ENABLE)
+  {
+    /* Enable the Interrupt sources */
+    TIM1->DIER |= TIM1_IT;
+  }
+  else
+  {
+    /* Disable the Interrupt sources */
+    TIM1->DIER &= (u16)~TIM1_IT;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_DMAConfig
+* Description    : Configures the TIM1’s DMA interface.
+* Input          : - TIM1_DMABase: DMA Base address.
+*                    This parameter can be one of the following values:
+*                       - TIM1_DMABase_CR1, TIM1_DMABase_CR2, TIM1_DMABase_SMCR,
+*                         TIM1_DMABase_DIER, TIM1_DMABase_SR, TIM1_DMABase_EGR,
+*                         TIM1_DMABase_CCMR1, TIM1_DMABase_CCMR2, TIM1_DMABase_CCER,
+*                         TIM1_DMABase_CNT, TIM1_DMABase_PSC, TIM1_DMABase_ARR,
+*                         TIM1_DMABase_RCR, TIM1_DMABase_CCR1, TIM1_DMABase_CCR2,
+*                         TIM1_DMABase_CCR3, TIM1_DMABase_CCR4, TIM1_DMABase_BDTR,
+*                         TIM1_DMABase_DCR.
+*                   - TIM1_DMABurstLength: DMA Burst length.
+*                     This parameter can be one value between:
+*                     TIM1_DMABurstLength_1Byte and TIM1_DMABurstLength_18Bytes.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_DMAConfig(u16 TIM1_DMABase, u16 TIM1_DMABurstLength)
+{
+  u32 tmpdcr = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM1_DMA_BASE(TIM1_DMABase));
+  assert(IS_TIM1_DMA_LENGTH(TIM1_DMABurstLength));
+
+  tmpdcr = TIM1->DCR;
+
+  /* Reset the DBA and the DBL Bits */
+  tmpdcr &= DCR_DMA_Mask;
+
+  /* Set the DMA Base and the DMA Burst Length */
+  tmpdcr |= TIM1_DMABase | TIM1_DMABurstLength;
+
+  TIM1->DCR = (u16)tmpdcr;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_DMACmd
+* Description    : Enables or disables the TIM1’s DMA Requests.
+* Input          : - TIM1_DMASources: specifies the DMA Request sources.
+*                    This parameter can be any combination of the following values:
+*                       - TIM1_DMA_Update: TIM1 update Interrupt source
+*                       - TIM1_DMA_CC1: TIM1 Capture Compare 1 DMA source
+*                       - TIM1_DMA_CC2: TIM1 Capture Compare 2 DMA source
+*                       - TIM1_DMA_CC3: TIM1 Capture Compare 3 DMA source
+*                       - TIM1_DMA_CC4: TIM1 Capture Compare 4 DMA source
+*                       - TIM1_DMA_COM: TIM1 Capture Compare Update DMA
+*                         source
+*                       - TIM1_DMA_Trigger: TIM1 Trigger DMA source
+*                  - Newstate: new state of the DMA Request sources.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_DMACmd(u16 TIM1_DMASource, FunctionalState Newstate)
+{
+  u32 tmpdier = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM1_DMA_SOURCE(TIM1_DMASource));
+  assert(IS_FUNCTIONAL_STATE(Newstate));
+
+  tmpdier = TIM1->DIER;
+
+  if (Newstate == ENABLE)
+  {
+    /* Enable the DMA sources */
+    tmpdier |= TIM1_DMASource;
+  }
+  else
+  {
+    /* Disable the DMA sources */
+    tmpdier &= (u16)~TIM1_DMASource;
+  }
+  TIM1->DIER = (u16)tmpdier;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_InternalClockConfig
+* Description    : Configures the TIM1 interrnal Clock
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_InternalClockConfig(void)
+{
+  /* Disable slave mode to clock the prescaler directly with the internal clock */
+  TIM1->SMCR &=  SMCR_SMS_Mask;
+}
+/*******************************************************************************
+* Function Name  : TIM1_ETRClockMode1Config
+* Description    : Configures the TIM1 External clock Mode1
+* Input          : - TIM1_ExtTRGPrescaler: The external Trigger Prescaler.
+*                    It can be one of the following values:
+*                       - TIM1_ExtTRGPSC_OFF
+*                       - TIM1_ExtTRGPSC_DIV2
+*                       - TIM1_ExtTRGPSC_DIV4
+*                       - TIM1_ExtTRGPSC_DIV8.
+*                  - TIM1_ExtTRGPolarity: The external Trigger Polarity.
+*                    It can be one of the following values:
+*                       - TIM1_ExtTRGPolarity_Inverted
+*                       - TIM1_ExtTRGPolarity_NonInverted
+*                  - ExtTRGFilter: External Trigger Filter.
+*                    This parameter must be a value between 0x00 and 0x0F
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_ETRClockMode1Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,
+                             u16 ExtTRGFilter)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_EXT_PRESCALER(TIM1_ExtTRGPrescaler));
+  assert(IS_TIM1_EXT_POLARITY(TIM1_ExtTRGPolarity));
+
+  /* Configure the ETR Clock source */
+  ETR_Config(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter);
+
+  /* Select the External clock mode1 */
+  TIM1->SMCR &= SMCR_SMS_Mask;
+  TIM1->SMCR |= TIM1_SlaveMode_External1;
+  
+  /* Select the Trigger selection : ETRF */
+  TIM1->SMCR &= SMCR_TS_Mask;
+  TIM1->SMCR |= TIM1_TS_ETRF;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_ETRClockMode2Config
+* Description    : Configures the TIM1 External clock Mode2
+* Input          : - TIM1_ExtTRGPrescaler: The external Trigger Prescaler.
+*                    It can be one of the following values:
+*                       - TIM1_ExtTRGPSC_OFF
+*                       - TIM1_ExtTRGPSC_DIV2
+*                       - TIM1_ExtTRGPSC_DIV4
+*                       - TIM1_ExtTRGPSC_DIV8
+*                  - TIM1_ExtTRGPolarity: The external Trigger Polarity.
+*                    It can be one of the following values:
+*                       - TIM1_ExtTRGPolarity_Inverted
+*                       - TIM1_ExtTRGPolarity_NonInverted
+*                  - ExtTRGFilter: External Trigger Filter.
+*                    This parameter must be a value between 0x00 and 0x0F
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_ETRClockMode2Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,
+                             u16 ExtTRGFilter)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_EXT_PRESCALER(TIM1_ExtTRGPrescaler));
+  assert(IS_TIM1_EXT_POLARITY(TIM1_ExtTRGPolarity));
+
+  /* Configure the ETR Clock source */
+  ETR_Config(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter);
+
+  /* Enable the External clock mode2 */
+  *(vu32 *) SMCR_ECE_BB = SMCR_ECE_Set;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_ITRxExternalClockConfig
+* Description    : Configures the TIM1 Internal Trigger as External Clock
+* Input          : - TIM1_ITRSource: Internal Trigger source.
+*                    This parameter can be one of the following values:
+*                       - TIM1_TS_ITR0: Internal Trigger 0
+*                       - TIM1_TS_ITR1: Internal Trigger 1
+*                       - TIM1_TS_ITR2: Internal Trigger 2
+*                       - TIM1_TS_ITR3: Internal Trigger 3
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_ITRxExternalClockConfig(u16 TIM1_InputTriggerSource)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_INTERNAL_TRIGGER_SELECTION(TIM1_InputTriggerSource));
+  
+  /* Select the Internal Trigger */
+  TIM1_SelectInputTrigger(TIM1_InputTriggerSource);
+
+  /* Select the External clock mode1 */
+  TIM1->SMCR |= TIM1_SlaveMode_External1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_TIxExternalClockConfig
+* Description    : Configures the TIM1 Trigger as External Clock
+* Input          : - TIM1_TIxExternalCLKSource: Trigger source.
+*                    This parameter can be one of the following values:
+*                       - TIM1_TS_TI1F_ED: TI1 Edge Detector
+*                       - TIM1_TS_TI1FP1: Filtered TIM1 Input 1
+*                       - TIM1_TS_TI2FP2: Filtered TIM1 Input 2
+*                  - TIM1_ICPolarity: specifies the TIx Polarity.
+*                    This parameter can be:
+*                       - TIM1_ICPolarity_Rising
+*                       - TIM1_ICPolarity_Falling
+*                   - ICFilter : specifies the filter value.
+*                     This parameter must be a value between 0x0 and 0xF.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_TIxExternalClockConfig(u16 TIM1_TIxExternalCLKSource,
+                                u16 TIM1_ICPolarity, u8 ICFilter)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_TIX_TRIGGER_SELECTION(TIM1_TIxExternalCLKSource));
+  assert(IS_TIM1_IC_POLARITY(TIM1_ICPolarity));
+  assert(IS_TIM1_IC_FILTER(ICFilter));
+
+  /* Configure the TIM1 Input Clock Source */
+  if (TIM1_TIxExternalCLKSource == TIM1_TIxExternalCLK1Source_TI2)
+  {
+    TI2_Config(TIM1_ICPolarity, TIM1_ICSelection_DirectTI, ICFilter);
+  }
+  else
+  {
+    TI1_Config(TIM1_ICPolarity, TIM1_ICSelection_DirectTI, ICFilter);
+  }
+
+  /* Select the Trigger source */
+  TIM1_SelectInputTrigger(TIM1_TIxExternalCLKSource);
+
+  /* Select the External clock mode1 */
+  TIM1->SMCR |= TIM1_SlaveMode_External1;
+}
+/*******************************************************************************
+* Function Name  : TIM1_SelectInputTrigger
+* Description    : Selects the TIM1 Input Trigger source
+* Input          : - TIM1_InputTriggerSource: The Trigger source.
+*                    This parameter can be one of the following values:
+*                       - TIM1_TS_ITR0: Internal Trigger 0
+*                       - TIM1_TS_ITR1: Internal Trigger 1
+*                       - TIM1_TS_ITR2: Internal Trigger 2
+*                       - TIM1_TS_ITR3: Internal Trigger 3
+*                       - TIM1_TS_TI1F_ED: TI1 Edge Detector
+*                       - TIM1_TS_TI1FP1: Filtered Timer Input 1
+*                       - TIM1_TS_TI2FP2: Filtered Timer Input 2
+*                       - TIM1_TS_ETRF: External Trigger input
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_SelectInputTrigger(u16 TIM1_InputTriggerSource)
+{
+  u32 tmpsmcr = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM1_TRIGGER_SELECTION(TIM1_InputTriggerSource));
+
+  tmpsmcr = TIM1->SMCR;
+
+  /* Select the Tgigger Source */
+  tmpsmcr &= SMCR_TS_Mask;
+  tmpsmcr |= TIM1_InputTriggerSource;
+
+  TIM1->SMCR = (u16)tmpsmcr;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_UpdateDisableConfig
+* Description    : Enables or Disables the TIM1 Update event.
+* Input          : - Newstate: new state of the TIM1 peripheral Preload register
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_UpdateDisableConfig(FunctionalState Newstate)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(Newstate));
+
+  /* Set or Reset the UDIS Bit */
+  *(vu32 *) CR1_UDIS_BB = (u16)Newstate;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_UpdateRequestConfig
+* Description    : Selects the TIM1 Update Request Interrupt source.
+* Input          : - TIM1_UpdateSource: specifies the Update source.
+*                    This parameter can be one of the following values:
+*                       - TIM1_UpdateSource_Regular
+*                       - TIM1_UpdateSource_Global
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_UpdateRequestConfig(u8 TIM1_UpdateSource)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_UPDATE_SOURCE(TIM1_UpdateSource));
+
+  /* Set or Reset the URS Bit */
+  *(vu32 *) CR1_URS_BB = TIM1_UpdateSource;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_SelectHallSensor
+* Description    : Enables or disables the TIM1’s Hall sensor interface.
+* Input          : - Newstate: new state of the TIM1 Hall sensor interface
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_SelectHallSensor(FunctionalState Newstate)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(Newstate));
+
+  /* Set or Reset the TI1S Bit */
+  *(vu32 *) CR2_TI1S_BB = (u16)Newstate;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_SelectOPM
+* Description    : Enables or disables the TIM1’s One Pulse Mode.
+* Input          : - TIM1_OPMode: specifies the OPM Mode to be used.
+*                    This parameter can be one of the following values:
+*                    - TIM1_OPMode_Single
+*                    - TIM1_OPMode_Repetitive
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_SelectOnePulseMode(u16 TIM1_OPMode)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_OPM_MODE(TIM1_OPMode));
+
+  /* Set or Reset the OPM Bit */
+  *(vu32 *) CR1_OPM_BB = TIM1_OPMode;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_SelectOutputTrigger
+* Description    : Selects the TIM1 Trigger Output Mode.
+* Input          : - TIM1_TRGOSource: specifies the Trigger Output source.
+*                    This paramter can be one of the following values:
+*                       - TIM1_TRGOSource_Reset
+*                       - TIM1_TRGOSource_Enable
+*                       - TIM1_TRGOSource_Update
+*                       - TIM1_TRGOSource_OC1
+*                       - TIM1_TRGOSource_OC1Ref
+*                       - TIM1_TRGOSource_OC2Ref
+*                       - TIM1_TRGOSource_OC3Ref
+*                       - TIM1_TRGOSource_OC4Ref
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_SelectOutputTrigger(u16 TIM1_TRGOSource)
+{
+  u32 tmpcr2 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM1_TRGO_SOURCE(TIM1_TRGOSource));
+
+  tmpcr2 = TIM1->CR2;
+
+  /* Reset the MMS Bits */
+  tmpcr2 &= CR2_MMS_Mask;
+
+  /* Select the TRGO source */
+  tmpcr2 |=  TIM1_TRGOSource;
+
+  TIM1->CR2 = (u16)tmpcr2;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_SelectSlaveMode
+* Description    : Selects the TIM1 Slave Mode.
+* Input          : - TIM1_SlaveMode: specifies the TIM1 Slave Mode.
+*                    This paramter can be one of the following values:
+*                       - TIM1_SlaveMode_Reset
+*                       - TIM1_SlaveMode_Gated
+*                       - TIM1_SlaveMode_Trigger
+*                       - TIM1_SlaveMode_External1
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_SelectSlaveMode(u16 TIM1_SlaveMode)
+{
+  u32 tmpsmcr = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM1_SLAVE_MODE(TIM1_SlaveMode));
+
+  tmpsmcr = TIM1->SMCR;
+
+  /* Reset the SMS Bits */
+  tmpsmcr &= SMCR_SMS_Mask;
+
+  /* Select the Slave Mode */
+  tmpsmcr |= TIM1_SlaveMode;
+
+  TIM1->SMCR = (u16)tmpsmcr;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_SelectMasterSlaveMode
+* Description    : Sets or Resets the TIM1 Master/Slave Mode.
+* Input          : - TIM1_MasterSlaveMode: specifies the TIM1 Master Slave Mode.
+*                    This paramter can be one of the following values:
+*                       - TIM1_MasterSlaveMode_Enable: synchronization between
+*                         the current timer and its slaves (through TRGO).
+*                       - TIM1_MasterSlaveMode_Disable: No action
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_SelectMasterSlaveMode(u16 TIM1_MasterSlaveMode)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_MSM_STATE(TIM1_MasterSlaveMode));
+
+  /* Set or Reset the MSM Bit */
+  *(vu32 *) SMCR_MSM_BB = TIM1_MasterSlaveMode;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_EncoderInterfaceConfig
+* Description    : Configures the TIM1 Encoder Interface.
+* Input          : - TIM1_EncoderMode: specifies the TIM1 Encoder Mode.
+*                    This parameter can be one of the following values:
+*                       - TIM1_EncoderMode_TI1: Counter counts on TI1FP1 edge
+*                         depending on TI2FP2 level.
+*                       - TIM1_EncoderMode_TI2: Counter counts on TI2FP2 edge
+*                         depending on TI1FP1 level.
+*                       - TIM1_EncoderMode_TI12: Counter counts on both TI1FP1 and
+*                         TI2FP2 edges depending on the level of the other input.
+*                  - TIM1_IC1Polarity: specifies the IC1 Polarity
+*                    This parmeter can be one of the following values:
+*                       - TIM1_ICPolarity_Falling
+*                       - TIM1_ICPolarity_Rising
+*                  - TIM1_IC2Polarity: specifies the IC2 Polarity
+*                    This parmeter can be one of the following values:
+*                       - TIM1_ICPolarity_Falling
+*                       - TIM1_ICPolarity_Rising
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_EncoderInterfaceConfig(u16 TIM1_EncoderMode, u16 TIM1_IC1Polarity,
+                                u16 TIM1_IC2Polarity)
+{
+  u32 tmpsmcr = 0;
+  u32 tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM1_ENCODER_MODE(TIM1_EncoderMode));
+  assert(IS_TIM1_IC_POLARITY(TIM1_IC1Polarity));
+  assert(IS_TIM1_IC_POLARITY(TIM1_IC2Polarity));
+
+  tmpsmcr = TIM1->SMCR;
+  tmpccmr1 = TIM1->CCMR1;
+
+  /* Set the encoder Mode */
+  tmpsmcr &= SMCR_SMS_Mask;
+  tmpsmcr |= TIM1_EncoderMode;
+
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask;
+  tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set;
+
+  /* Set the TI1 and the TI2 Polarities */
+  *(vu32 *) CCER_CC1P_BB = TIM1_IC1Polarity;
+  *(vu32 *) CCER_CC2P_BB = TIM1_IC2Polarity;
+
+  TIM1->SMCR = (u16)tmpsmcr;
+
+  TIM1->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_PrescalerConfig
+* Description    : Configures the TIM1 Prescaler.
+* Input          : - Prescaler: specifies the Prescaler Register value
+*                  - TIM1_PSCReloadMode: specifies the TIM1 Prescaler Reload mode.
+*                    This parmeter can be one of the following values:
+*                       - TIM1_PSCReloadMode_Update: The Prescaler is loaded at
+*                         the update event.
+*                       - TIM1_PSCReloadMode_Immediate: The Prescaler is loaded
+*                         immediatly.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_PrescalerConfig(u16 Prescaler, u16 TIM1_PSCReloadMode)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_PRESCALER_RELOAD(TIM1_PSCReloadMode));
+
+  /* Set the Prescaler value */
+  TIM1->PSC = Prescaler;
+
+  /* Set or reset the UG Bit */
+  *(vu32 *) EGR_UG_BB = TIM1_PSCReloadMode;
+}
+/*******************************************************************************
+* Function Name  : TIM1_CounterModeConfig
+* Description    : Specifies the TIM1 Counter Mode to be used.
+* Input          : - TIM1_CounterMode: specifies the Counter Mode to be used
+*                    This parameter can be one of the following values:
+*                       - TIM1_CounterMode_Up: TIM1 Up Counting Mode
+*                       - TIM1_CounterMode_Down: TIM1 Down Counting Mode
+*                       - TIM1_CounterMode_CenterAligned1: TIM1 Center Aligned Mode1
+*                       - TIM1_CounterMode_CenterAligned2: TIM1 Center Aligned Mode2
+*                       - TIM1_CounterMode_CenterAligned3: TIM1 Center Aligned Mode3
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_CounterModeConfig(u16 TIM1_CounterMode)
+{
+  u32 tmpcr1 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM1_COUNTER_MODE(TIM1_CounterMode));
+
+  tmpcr1 = TIM1->CR1;
+
+  /* Reset the CMS and DIR Bits */
+  tmpcr1 &= CR1_CounterMode_Mask;
+
+  /* Set the Counter Mode */
+  tmpcr1 |= TIM1_CounterMode;
+
+  TIM1->CR1 = (u16)tmpcr1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_ForcedOC1Config
+* Description    : Forces the TIM1 Channel1 output waveform to active or inactive 
+*                  level.
+* Input          : - TIM1_ForcedAction: specifies the forced Action to be set to
+*                    the output waveform.
+*                    This parameter can be one of the following values:
+*                       - TIM1_ForcedAction_Active: Force active level on OC1REF
+*                       - TIM1_ForcedAction_InActive: Force inactive level on
+*                         OC1REF.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_ForcedOC1Config(u16 TIM1_ForcedAction)
+{
+  u32 tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction));
+
+  tmpccmr1 = TIM1->CCMR1;
+
+  /* Reset the OCM Bits */
+  tmpccmr1 &= CCMR_OCM13_Mask;
+
+  /* Configure The Forced output Mode */
+  tmpccmr1 |= TIM1_ForcedAction;
+
+  TIM1->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_ForcedOC2Config
+* Description    : Forces the TIM1 Channel2 output waveform to active or inactive 
+*                  level.
+* Input          : - TIM1_ForcedAction: specifies the forced Action to be set to
+*                    the output waveform.
+*                    This parameter can be one of the following values:
+*                       - TIM1_ForcedAction_Active: Force active level on OC2REF
+*                       - TIM1_ForcedAction_InActive: Force inactive level on
+*                         OC2REF.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_ForcedOC2Config(u16 TIM1_ForcedAction)
+{
+  u32 tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction));
+
+  tmpccmr1 = TIM1->CCMR1;
+
+  /* Reset the OCM Bits */
+  tmpccmr1 &= CCMR_OCM24_Mask;
+
+  /* Configure The Forced output Mode */
+  tmpccmr1 |= (u32)TIM1_ForcedAction << 8;
+
+  TIM1->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_ForcedOC3Config
+* Description    : Forces the TIM1 Channel3 output waveform to active or inactive 
+*                  level.
+* Input          : - TIM1_ForcedAction: specifies the forced Action to be set to
+*                    the output waveform.
+*                    This parameter can be one of the following values:
+*                       - TIM1_ForcedAction_Active: Force active level on OC3REF
+*                       - TIM1_ForcedAction_InActive: Force inactive level on
+*                         OC3REF.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_ForcedOC3Config(u16 TIM1_ForcedAction)
+{
+  u32 tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction));
+
+  tmpccmr2 = TIM1->CCMR2;
+
+  /* Reset the OCM Bits */
+  tmpccmr2 &= CCMR_OCM13_Mask;
+
+  /* Configure The Forced output Mode */
+  tmpccmr2 |= TIM1_ForcedAction;
+
+  TIM1->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_ForcedOC4Config
+* Description    : Forces the TIM1 Channel4 output waveform to active or inactive 
+*                  level.
+* Input          : - TIM1_ForcedAction: specifies the forced Action to be set to
+*                    the output waveform.
+*                    This parameter can be one of the following values:
+*                       - TIM1_ForcedAction_Active: Force active level on OC4REF
+*                       - TIM1_ForcedAction_InActive: Force inactive level on
+*                         OC4REF.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_ForcedOC4Config(u16 TIM1_ForcedAction)
+{
+  u32 tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction));
+
+  tmpccmr2 = TIM1->CCMR1;
+
+  /* Reset the OCM Bits */
+  tmpccmr2 &= CCMR_OCM24_Mask;
+
+  /* Configure The Forced output Mode */
+  tmpccmr2 |= (u16)((u16)TIM1_ForcedAction << 8);
+
+  TIM1->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_ARRPreloadConfig
+* Description    : Enables or disables TIM1 peripheral Preload register on ARR.
+* Input          : - Newstate: new state of the TIM1 peripheral Preload register
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_ARRPreloadConfig(FunctionalState Newstate)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(Newstate));
+
+  /* Set or Reset the ARPE Bit */
+  *(vu32 *) CR1_ARPE_BB = (u16)Newstate;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_SelectCOM
+* Description    : Selects the TIM1 peripheral Commutation event.
+* Input          : - Newstate: new state of the Commutation event.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_SelectCOM(FunctionalState Newstate)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(Newstate));
+
+  /* Set or Reset the CCUS Bit */
+  *(vu32 *) CR2_CCUS_BB = (u16)Newstate;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_SelectCCDMA
+* Description    : Selects the TIM1 peripheral Capture Compare DMA source.
+* Input          : - Newstate: new state of the Capture Compare DMA source
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_SelectCCDMA(FunctionalState Newstate)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(Newstate));
+
+  /* Set or Reset the CCDS Bit */
+  *(vu32 *) CR2_CCDS_BB = (u16)Newstate;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_CCPreloadControl
+* Description    : Sets or Resets the TIM1 peripheral Capture Compare Preload 
+*                  Control bit.
+* Input          : - Newstate: new state of the Capture Compare Preload Control bit
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_CCPreloadControl(FunctionalState Newstate)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(Newstate));
+
+  /* Set or Reset the CCPC Bit */
+  *(vu32 *) CR2_CCPC_BB = (u16)Newstate;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_OC1PreloadConfig
+* Description    : Enables or disables the TIM1 peripheral Preload Register on CCR1.
+* Input          : - TIM1_OCPreload: new state of the Capture Compare Preload
+*                    register.
+*                    This parameter can be one of the following values:
+*                       - TIM1_OCPreload_Enable
+*                       - TIM1_OCPreload_Disable
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_OC1PreloadConfig(u16 TIM1_OCPreload)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload));
+
+  /* Set or Reset the OC1PE Bit */
+  *(vu32 *) CCMR1_OC1PE_BB = (u16)TIM1_OCPreload;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_OC2PreloadConfig
+* Description    : Enables or disables the TIM1 peripheral Preload Register on CCR2.
+* Input          : - TIM1_OCPreload: new state of the Capture Compare Preload
+*                    register.
+*                    This parameter can be one of the following values:
+*                       - TIM1_OCPreload_Enable
+*                       - TIM1_OCPreload_Disable
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_OC2PreloadConfig(u16 TIM1_OCPreload)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload));
+
+  /* Set or Reset the OC2PE Bit */
+  *(vu32 *) CCMR1_OC2PE_BB = (u16)TIM1_OCPreload;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_OC3PreloadConfig
+* Description    : Enables or disables the TIM1 peripheral Preload Register on CCR3.
+* Input          : - TIM1_OCPreload: new state of the Capture Compare Preload
+*                    register.
+*                    This parameter can be one of the following values:
+*                       - TIM1_OCPreload_Enable
+*                       - TIM1_OCPreload_Disable
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_OC3PreloadConfig(u16 TIM1_OCPreload)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload));
+
+  /* Set or Reset the OC3PE Bit */
+  *(vu32 *) CCMR2_OC3PE_BB = (u16)TIM1_OCPreload;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_OC4PreloadConfig
+* Description    : Enables or disables the TIM1 peripheral Preload Register on CCR4.
+* Input          : - TIM1_OCPreload: new state of the Capture Compare Preload
+*                    register.
+*                    This parameter can be one of the following values:
+*                       - TIM1_OCPreload_Enable
+*                       - TIM1_OCPreload_Disable
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_OC4PreloadConfig(u16 TIM1_OCPreload)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload));
+
+  /* Set or Reset the OC4PE Bit */
+  *(vu32 *) CCMR2_OC4PE_BB = (u16)TIM1_OCPreload;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_OC1FastConfig
+* Description    : Configures the TIM1 Capture Compare 1 Fast feature.
+* Input          : - TIM1_OCFast: new state of the Output Compare Fast Enable bit.
+*                    This parameter can be one of the following values:
+*                       - TIM1_OCFast_Enable
+*                       - TIM1_OCFast_Disable
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_OC1FastConfig(u16 TIM1_OCFast)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast));
+
+  /* Set or Reset the OC1FE Bit */
+  *(vu32 *) CCMR1_OC1FE_BB = (u16)TIM1_OCFast;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_OC2FastConfig
+* Description    : Configures the TIM1 Capture Compare Fast feature.
+* Input          : - TIM1_OCFast: new state of the Output Compare Fast Enable bit.
+*                    This parameter can be one of the following values:
+*                       - TIM1_OCFast_Enable
+*                       - TIM1_OCFast_Disable
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_OC2FastConfig(u16 TIM1_OCFast)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast));
+
+  /* Set or Reset the OC2FE Bit */
+  *(vu32 *) CCMR1_OC2FE_BB = (u16)TIM1_OCFast;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_OC3FastConfig
+* Description    : Configures the TIM1 Capture Compare Fast feature.
+* Input          : - TIM1_OCFast: new state of the Output Compare Fast Enable bit.
+*                    This parameter can be one of the following values:
+*                       - TIM1_OCFast_Enable
+*                       - TIM1_OCFast_Disable
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_OC3FastConfig(u16 TIM1_OCFast)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast));
+
+  /* Set or Reset the OC3FE Bit */
+  *(vu32 *) CCMR2_OC3FE_BB = (u16)TIM1_OCFast;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_OC4FastConfig
+* Description    : Configures the TIM1 Capture Compare Fast feature.
+* Input          : - TIM1_OCFast: new state of the Output Compare Fast Enable bit.
+*                    This parameter can be one of the following values:
+*                       - TIM1_OCFast_Enable
+*                       - TIM1_OCFast_Disable
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_OC4FastConfig(u16 TIM1_OCFast)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast));
+
+  /* Set or Reset the OC4FE Bit */
+  *(vu32 *) CCMR2_OC4FE_BB = (u16)TIM1_OCFast;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_GenerateEvent
+* Description    : Configures the TIM1 event to be generate by software.
+* Input          : - TIM1_EventSource: specifies the event source.
+*                    This parameter can be one or more of the following values:
+*                       - TIM1_EventSource_Update: TIM1 update Event source
+*                       - TIM1_EventSource_CC1: TIM1 Capture Compare 1 Event source
+*                       - TIM1_EventSource_CC2: TIM1 Capture Compare 2 Event source
+*                       - TIM1_EventSource_CC3: TIM1 Capture Compare 3 Event source
+*                       - TIM1_EventSource_CC4: TIM1 Capture Compare 4 Event source
+*                       - TIM1_EventSource_COM: TIM1 COM Event source
+*                       - TIM1_EventSource_Trigger: TIM1 Trigger Event source
+*                       - TIM1_EventSourceBreak: TIM1 Break Event source
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_GenerateEvent(u16 TIM1_EventSource)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_EVENT_SOURCE(TIM1_EventSource));
+
+  /* Set the event sources */
+  TIM1->EGR |= TIM1_EventSource;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_OC1PolarityConfig
+* Description    : Configures the TIM1 Channel 1 polarity.
+* Input          : - TIM1_OCPolarity: specifies the OC1 Polarity
+*                    This parmeter can be one of the following values:
+*                       - TIM1_OCPolarity_High: Output Compare active high
+*                       - TIM1_OCPolarity_Low: Output Compare active low
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_OC1PolarityConfig(u16 TIM1_OCPolarity)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
+
+  /* Set or Reset the CC1P Bit */
+  *(vu32 *) CCER_CC1P_BB = (u16)TIM1_OCPolarity;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_OC1NPolarityConfig
+* Description    : Configures the TIM1 Channel 1N polarity.
+* Input          : - TIM1_OCPolarity: specifies the OC1N Polarity
+*                    This parmeter can be one of the following values:
+*                       - TIM1_OCPolarity_High: Output Compare active high
+*                       - TIM1_OCPolarity_Low: Output Compare active low
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_OC1NPolarityConfig(u16 TIM1_OCPolarity)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
+
+  /* Set or Reset the CC3P Bit */
+  *(vu32 *) CCER_CC1NP_BB = (u16)TIM1_OCPolarity;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_OC2PolarityConfig
+* Description    : Configures the TIM1 Channel 2 polarity.
+* Input          : - TIM1_OCPolarity: specifies the OC2 Polarity
+*                    This parmeter can be one of the following values:
+*                       - TIM1_OCPolarity_High: Output Compare active high
+*                       - TIM1_OCPolarity_Low: Output Compare active low
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_OC2PolarityConfig(u16 TIM1_OCPolarity)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
+
+  /* Set or Reset the CC2P Bit */
+  *(vu32 *) CCER_CC2P_BB = (u16)TIM1_OCPolarity;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_OC2NPolarityConfig
+* Description    : Configures the TIM1 Channel 2N polarity.
+* Input          : - TIM1_OCPolarity: specifies the OC2N Polarity
+*                    This parmeter can be one of the following values:
+*                       - TIM1_OCPolarity_High: Output Compare active high
+*                       - TIM1_OCPolarity_Low: Output Compare active low
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_OC2NPolarityConfig(u16 TIM1_OCPolarity)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
+
+  /* Set or Reset the CC3P Bit */
+  *(vu32 *) CCER_CC2NP_BB = (u16)TIM1_OCPolarity;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_OC3PolarityConfig
+* Description    : Configures the TIM1 Channel 3 polarity.
+* Input          : - TIM1_OCPolarity: specifies the OC3 Polarity
+*                    This parmeter can be one of the following values:
+*                       - TIM1_OCPolarity_High: Output Compare active high
+*                       - TIM1_OCPolarity_Low: Output Compare active low
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_OC3PolarityConfig(u16 TIM1_OCPolarity)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
+
+  /* Set or Reset the CC3P Bit */
+  *(vu32 *) CCER_CC3P_BB = (u16)TIM1_OCPolarity;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_OC3NPolarityConfig
+* Description    : Configures the TIM1 Channel 3N polarity.
+* Input          : - TIM1_OCPolarity: specifies the OC3N Polarity
+*                    This parmeter can be one of the following values:
+*                       - TIM1_OCPolarity_High: Output Compare active high
+*                       - TIM1_OCPolarity_Low: Output Compare active low
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_OC3NPolarityConfig(u16 TIM1_OCPolarity)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
+
+  /* Set or Reset the CC3P Bit */
+  *(vu32 *) CCER_CC3NP_BB = (u16)TIM1_OCPolarity;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_OC4PolarityConfig
+* Description    : Configures the TIM1 Channel 4 polarity.
+* Input          : - TIM1_OCPolarity: specifies the OC4 Polarity
+*                    This parmeter can be one of the following values:
+*                       - TIM1_OCPolarity_High: Output Compare active high
+*                       - TIM1_OCPolarity_Low: Output Compare active low
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_OC4PolarityConfig(u16 TIM1_OCPolarity)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
+
+  /* Set or Reset the CC4P Bit */
+  *(vu32 *) CCER_CC4P_BB = (u16)TIM1_OCPolarity;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_CCxCmd
+* Description    : Enables or disables the TIM1 Capture Compare Channel x.
+* Input          : - TIM1_Channel: specifies the TIM1 Channel
+*                    This parmeter can be one of the following values:
+*                       - TIM1_Channel1: TIM1 Channel1
+*                       - TIM1_Channel2: TIM1 Channel2
+*                       - TIM1_Channel3: TIM1 Channel3
+*                       - TIM1_Channel4: TIM1 Channel4
+*                 - Newstate: specifies the TIM1 Channel CCxE bit new state.
+*                   This parameter can be: ENABLE or DISABLE. 
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_CCxCmd(u16 TIM1_Channel, FunctionalState Newstate)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_CHANNEL(TIM1_Channel));
+  assert(IS_FUNCTIONAL_STATE(Newstate));
+
+  if(TIM1_Channel == TIM1_Channel_1)
+  {
+    /* Set or Reset the CC1E Bit */
+    *(vu32 *) CCER_CC1E_BB = (u16)Newstate;  
+  }
+  else if(TIM1_Channel == TIM1_Channel_2)
+  {
+    /* Set or Reset the CC2E Bit */
+    *(vu32 *) CCER_CC2E_BB = (u16)Newstate;
+  }
+  else if(TIM1_Channel == TIM1_Channel_3)
+  {
+    /* Set or Reset the CC3E Bit */
+    *(vu32 *) CCER_CC3E_BB = (u16)Newstate;
+  }
+  else
+  {
+    /* Set or Reset the CC4E Bit */
+    *(vu32 *) CCER_CC4E_BB = (u16)Newstate;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_CCxNCmd
+* Description    : Enables or disables the TIM1 Capture Compare Channel xN.
+* Input          : - TIM1_Channel: specifies the TIM1 Channel
+*                    This parmeter can be one of the following values:
+*                       - TIM1_Channel1: TIM1 Channel1
+*                       - TIM1_Channel2: TIM1 Channel2
+*                       - TIM1_Channel3: TIM1 Channel3
+*                 - Newstate: specifies the TIM1 Channel CCxNE bit new state.
+*                   This parameter can be: ENABLE or DISABLE. 
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_CCxNCmd(u16 TIM1_Channel, FunctionalState Newstate)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_COMPLEMENTARY_CHANNEL(TIM1_Channel));
+  assert(IS_FUNCTIONAL_STATE(Newstate));
+
+  if(TIM1_Channel == TIM1_Channel_1)
+  {
+    /* Set or Reset the CC1NE Bit */
+    *(vu32 *) CCER_CC1NE_BB = (u16)Newstate;  
+  }
+  else if(TIM1_Channel == TIM1_Channel_2)
+  {
+    /* Set or Reset the CC2NE Bit */
+    *(vu32 *) CCER_CC2NE_BB = (u16)Newstate;
+  }
+  else 
+  {
+    /* Set or Reset the CC3NE Bit */
+    *(vu32 *) CCER_CC3NE_BB = (u16)Newstate;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_SelectOCxM
+* Description    : Selects the TIM1 Ouput Compare Mode.
+*                  This function disables the selected channel before changing 
+*                  the Ouput Compare Mode. User has to enable this channel using
+*                  TIM1_CCxCmd and TIM1_CCxNCmd functions.
+* Input          : - TIM1_Channel: specifies the TIM1 Channel
+*                    This parmeter can be one of the following values:
+*                       - TIM1_Channel1: TIM1 Channel1
+*                       - TIM1_Channel2: TIM1 Channel2
+*                       - TIM1_Channel3: TIM1 Channel3
+*                       - TIM1_Channel4: TIM1 Channel4
+*                  - TIM1_OCMode: specifies the TIM1 Output Compare Mode.
+*                    This paramter can be one of the following values:
+*                       - TIM1_OCMode_Timing
+*                       - TIM1_OCMode_Active
+*                       - TIM1_OCMode_Toggle
+*                       - TIM1_OCMode_PWM1
+*                       - TIM1_OCMode_PWM2
+*                       - TIM1_ForcedAction_Active
+*                       - TIM1_ForcedAction_InActive
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_SelectOCxM(u16 TIM1_Channel, u16 TIM1_OCMode)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_CHANNEL(TIM1_Channel));
+  assert(IS_TIM1_OCM(TIM1_OCMode));
+
+  if(TIM1_Channel == TIM1_Channel_1)
+  {
+    /* Disable the Channel 1: Reset the CCE Bit */
+    *(vu32 *) CCER_CC1E_BB = CCER_CCE_Reset;
+
+    /* Reset the Output Compare Bits */
+    TIM1->CCMR1 &= OC13Mode_Mask;
+
+    /* Set the Ouput Compare Mode */
+    TIM1->CCMR1 |= TIM1_OCMode;
+  }
+  else if(TIM1_Channel == TIM1_Channel_2)
+  {
+    /* Disable the Channel 2: Reset the CCE Bit */
+    *(vu32 *) CCER_CC2E_BB = CCER_CCE_Reset;
+
+    /* Reset the Output Compare Bits */
+    TIM1->CCMR1 &= OC24Mode_Mask;
+
+    /* Set the Ouput Compare Mode */
+    TIM1->CCMR1 |= (u16)((u16)TIM1_OCMode << 8);
+  }
+  else if(TIM1_Channel == TIM1_Channel_3)
+  {
+    /* Disable the Channel 3: Reset the CCE Bit */
+    *(vu32 *) CCER_CC3E_BB = CCER_CCE_Reset;
+
+    /* Reset the Output Compare Bits */
+    TIM1->CCMR2 &= OC13Mode_Mask;
+
+    /* Set the Ouput Compare Mode */
+    TIM1->CCMR2 |= TIM1_OCMode;
+  }
+  else
+  {
+    /* Disable the Channel 4: Reset the CCE Bit */
+    *(vu32 *) CCER_CC4E_BB = CCER_CCE_Reset;
+
+    /* Reset the Output Compare Bits */
+    TIM1->CCMR2 &= OC24Mode_Mask;
+
+    /* Set the Ouput Compare Mode */
+    TIM1->CCMR2 |= (u16)((u16)TIM1_OCMode << 8);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_SetAutoreload
+* Description    : Sets the TIM1 Autoreload Register value.
+* Input          : - Autoreload: specifies the Autoreload register new value.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_SetAutoreload(u16 Autoreload)
+{
+  /* Set the Autoreload Register value */
+  TIM1->ARR = Autoreload;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_SetCompare1
+* Description    : Sets the TIM1 Capture Compare1 Register value.
+* Input          : - Compare1: specifies the Capture Compare1 register new value.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_SetCompare1(u16 Compare1)
+{
+  /* Set the Capture Compare1 Register value */
+  TIM1->CCR1 = Compare1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_SetCompare2
+* Description    : Sets the TIM1 Capture Compare2 Register value.
+* Input          : - Compare2: specifies the Capture Compare2 register new value.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_SetCompare2(u16 Compare2)
+{
+  /* Set the Capture Compare2 Register value */
+  TIM1->CCR2 = Compare2;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_SetCompare3
+* Description    : Sets the TIM1 Capture Compare3 Register value.
+* Input          : - Compare3: specifies the Capture Compare3 register new value.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_SetCompare3(u16 Compare3)
+{
+  /* Set the Capture Compare3 Register value */
+  TIM1->CCR3 = Compare3;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_SetCompare4
+* Description    : Sets the TIM1 Capture Compare4 Register value.
+* Input          : - Compare4: specifies the Capture Compare4 register new value.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_SetCompare4(u16 Compare4)
+{
+  /* Set the Capture Compare4 Register value */
+  TIM1->CCR4 = Compare4;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_SetIC1Prescaler
+* Description    : Sets the TIM1 Input Capture 1 prescaler.
+* Input          : - TIM1_IC1Prescaler: specifies the Input Capture prescaler
+*                    new value.
+*                    This parameter can be one of the following values:
+*                       - TIM1_ICPSC_DIV1: no prescaler
+*                       - TIM1_ICPSC_DIV2: capture is done once every 2 events
+*                       - TIM1_ICPSC_DIV4: capture is done once every 4 events
+*                       - TIM1_ICPSC_DIV8: capture is done once every 8 events
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_SetIC1Prescaler(u16 TIM1_IC1Prescaler)
+{
+  u32 tmpccmr1 = 0;
+  
+  /* Check the parameters */
+  assert(IS_TIM1_IC_PRESCALER(TIM1_IC1Prescaler));
+
+  tmpccmr1 = TIM1->CCMR1;
+
+  /* Reset the IC1PSC Bits */
+  tmpccmr1 &= CCMR_IC13PSC_Mask;
+
+  /* Set the IC1PSC value */
+  tmpccmr1 |= TIM1_IC1Prescaler;
+
+  TIM1->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_SetIC2Prescaler
+* Description    : Sets the TIM1 Input Capture 2 prescaler.
+* Input          : - TIM1_IC2Prescaler: specifies the Input Capture prescaler
+*                    new value.
+*                    This parameter can be one of the following values:
+*                       - TIM1_ICPSC_DIV1: no prescaler
+*                       - TIM1_ICPSC_DIV2: capture is done once every 2 events
+*                       - TIM1_ICPSC_DIV4: capture is done once every 4 events
+*                       - TIM1_ICPSC_DIV8: capture is done once every 8 events
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_SetIC2Prescaler(u16 TIM1_IC2Prescaler)
+{
+  u32 tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM1_IC_PRESCALER(TIM1_IC2Prescaler));
+
+  tmpccmr1 = TIM1->CCMR1;
+
+  /* Reset the IC2PSC Bits */
+  tmpccmr1 &= CCMR_IC24PSC_Mask;
+
+  /* Set the IC2PSC value */
+  tmpccmr1 |= (u16)((u16)TIM1_IC2Prescaler << 8);
+
+  TIM1->CCMR1 = (u16)tmpccmr1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_SetIC3Prescaler
+* Description    : Sets the TIM1 Input Capture 3 prescaler.
+* Input          : - TIM1_IC3Prescaler: specifies the Input Capture prescaler
+*                    new value.
+*                    This parameter can be one of the following values:
+*                       - TIM1_ICPSC_DIV1: no prescaler
+*                       - TIM1_ICPSC_DIV2: capture is done once every 2 events
+*                       - TIM1_ICPSC_DIV4: capture is done once every 4 events
+*                       - TIM1_ICPSC_DIV8: capture is done once every 8 events
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_SetIC3Prescaler(u16 TIM1_IC3Prescaler)
+{
+  u32 tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM1_IC_PRESCALER(TIM1_IC3Prescaler));
+
+  tmpccmr2 = TIM1->CCMR2;
+
+  /* Reset the IC3PSC Bits */
+  tmpccmr2 &= CCMR_IC13PSC_Mask;
+
+  /* Set the IC3PSC value */
+  tmpccmr2 |= TIM1_IC3Prescaler;
+
+  TIM1->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_SetIC4Prescaler
+* Description    : Sets the TIM1 Input Capture 4 prescaler.
+* Input          : - TIM1_IC4Prescaler: specifies the Input Capture prescaler
+*                    new value.
+*                    This parameter can be one of the following values:
+*                       - TIM1_ICPSC_DIV1: no prescaler
+*                       - TIM1_ICPSC_DIV2: capture is done once every 2 events
+*                       - TIM1_ICPSC_DIV4: capture is done once every 4 events
+*                       - TIM1_ICPSC_DIV8: capture is done once every 8 events
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_SetIC4Prescaler(u16 TIM1_IC4Prescaler)
+{
+  u32 tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM1_IC_PRESCALER(TIM1_IC4Prescaler));
+
+  tmpccmr2 = TIM1->CCMR2;
+
+  /* Reset the IC4PSC Bits */
+  tmpccmr2 &= CCMR_IC24PSC_Mask;
+
+  /* Set the IC4PSC value */
+  tmpccmr2 |= (u16)((u16)TIM1_IC4Prescaler << 8);
+
+  TIM1->CCMR2 = (u16)tmpccmr2;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_SetClockDivision
+* Description    : Sets the TIM1 Clock Division value.
+* Input          : - TIM1_CKD: specifies the clock division value.
+*                    This parameter can be one of the following value:
+*                       - TIM1_CKD_DIV1: TDTS = Tck_tim
+*                       - TIM1_CKD_DIV2: TDTS = 2*Tck_tim
+*                       - TIM1_CKD_DIV4: TDTS = 4*Tck_tim
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_SetClockDivision(u16 TIM1_CKD)
+{
+  u32 tmpcr1 = 0;
+
+  /* Check the parameters */
+  assert(IS_TIM1_CKD_DIV(TIM1_CKD));
+
+  tmpcr1 = TIM1->CR1;
+
+  /* Reset the CKD Bits */
+  tmpcr1 &= CR1_CKD_Mask;
+
+  /* Set the CKD value */
+  tmpcr1 |= TIM1_CKD;
+
+  TIM1->CR1 = (u16)tmpcr1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_GetCapture1
+* Description    : Gets the TIM1 Input Capture 1 value.
+* Input          : None
+* Output         : None
+* Return         : Capture Compare 1 Register value.
+*******************************************************************************/
+u16 TIM1_GetCapture1(void)
+{
+  /* Get the Capture 1 Register value */
+  return TIM1->CCR1;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_GetCapture2
+* Description    : Gets the TIM1 Input Capture 2 value.
+* Input          : None
+* Output         : None
+* Return         : Capture Compare 2 Register value.
+*******************************************************************************/
+u16 TIM1_GetCapture2(void)
+{
+  /* Get the Capture 2 Register value */
+  return TIM1->CCR2;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_GetCapture3
+* Description    : Gets the TIM1 Input Capture 3 value.
+* Input          : None
+* Output         : None
+* Return         : Capture Compare 3 Register value.
+*******************************************************************************/
+u16 TIM1_GetCapture3(void)
+{
+  /* Get the Capture 3 Register value */
+  return TIM1->CCR3;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_GetCapture4
+* Description    : Gets the TIM1 Input Capture 4 value.
+* Input          : None
+* Output         : None
+* Return         : Capture Compare 4 Register value.
+*******************************************************************************/
+u16 TIM1_GetCapture4(void)
+{
+  /* Get the Capture 4 Register value */
+  return TIM1->CCR4;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_GetCounter
+* Description    : Gets the TIM1 Counter value.
+* Input          : None
+* Output         : None
+* Return         : Counter Register value.
+*******************************************************************************/
+u16 TIM1_GetCounter(void)
+{
+  /* Get the Counter Register value */
+  return TIM1->CNT;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_GetPrescaler
+* Description    : Gets the TIM1 Prescaler value.
+* Input          : None
+* Output         : None
+* Return         : Prescaler Register value.
+*******************************************************************************/
+u16 TIM1_GetPrescaler(void)
+{
+  /* Get the Prescaler Register value */
+  return TIM1->PSC;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_GetFlagStatus
+* Description    : Checks whether the specified TIM1 flag is set or not.
+* Input          : - TIM1_FLAG: specifies the flag to check.
+*                    This parameter can be one of the following values:
+*                       - TIM1_FLAG_Update: TIM1 update Flag
+*                       - TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag
+*                       - TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag
+*                       - TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag
+*                       - TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag
+*                       - TIM1_FLAG_COM: TIM1 Commutation Flag
+*                       - TIM1_FLAG_Trigger: TIM1 Trigger Flag
+*                       - TIM1_FLAG_Break: TIM1 Break Flag
+*                       - TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag
+*                       - TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag
+*                       - TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag
+*                       - TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag
+* Output         : None
+* Return         : The new state of TIM1_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus TIM1_GetFlagStatus(u16 TIM1_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert(IS_TIM1_GET_FLAG(TIM1_FLAG));
+
+  if ((TIM1->SR & TIM1_FLAG) != (u16)RESET )
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_ClearFlag
+* Description    : Clears the TIM1’s pending flags.
+* Input          : - TIM1_FLAG: specifies the flag to clear.
+*                    This parameter can be any combination of the following values:
+*                       - TIM1_FLAG_Update: TIM1 update Flag
+*                       - TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag
+*                       - TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag
+*                       - TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag
+*                       - TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag
+*                       - TIM1_FLAG_COM: TIM1 Commutation Flag
+*                       - TIM1_FLAG_Trigger: TIM1 Trigger Flag
+*                       - TIM1_FLAG_Break: TIM1 Break Flag
+*                       - TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag
+*                       - TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag
+*                       - TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag
+*                       - TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_ClearFlag(u16 TIM1_FLAG)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_CLEAR_FLAG(TIM1_FLAG));
+
+  /* Clear the flags */
+  TIM1->SR &= (u16)~TIM1_FLAG;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_GetITStatus
+* Description    : Checks whether the TIM1 interrupt has occurred or not.
+* Input          : - TIM1_IT: specifies the TIM1 interrupt source to check.
+*                    This parameter can be one of the following values:
+*                       - TIM1_IT_Update: TIM1 update Interrupt source
+*                       - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
+*                       - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
+*                       - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
+*                       - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
+*                       - TIM1_IT_COM: TIM1 Commutation Interrupt
+*                         source
+*                       - TIM1_IT_Trigger: TIM1 Trigger Interrupt source
+*                       - TIM1_IT_Break: TIM1 Break Interrupt source
+* Output         : None
+* Return         : The new state of the TIM1_IT(SET or RESET).
+*******************************************************************************/
+ITStatus TIM1_GetITStatus(u16 TIM1_IT)
+{
+  ITStatus bitstatus = RESET;
+  
+  u16 TIM1_itStatus = 0x0, TIM1_itEnable = 0x0;
+
+  /* Check the parameters */
+  assert(IS_TIM1_GET_IT(TIM1_IT));
+  
+  TIM1_itStatus = TIM1->SR & TIM1_IT;
+  
+  TIM1_itEnable = TIM1->DIER & TIM1_IT;
+
+  if ((TIM1_itStatus != (u16)RESET ) && (TIM1_itEnable != (u16)RESET ))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : TIM1_ClearITPendingBit
+* Description    : Clears the TIM1's interrupt pending bits.
+* Input          : - TIM1_IT: specifies the pending bit to clear.
+*                    This parameter can be any combination of the following values:
+*                       - TIM1_IT_Update: TIM1 update Interrupt source
+*                       - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
+*                       - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
+*                       - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
+*                       - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
+*                       - TIM1_IT_COM: TIM1 Commutation Interrupt
+*                         source
+*                       - TIM1_IT_Trigger: TIM1 Trigger Interrupt source
+*                       - TIM1_IT_Break: TIM1 Break Interrupt source
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM1_ClearITPendingBit(u16 TIM1_IT)
+{
+  /* Check the parameters */
+  assert(IS_TIM1_IT(TIM1_IT));
+
+  /* Clear the IT pending Bit */
+  TIM1->SR &= (u16)~TIM1_IT;
+}
+
+/*******************************************************************************
+* Function Name  : TI1_Config
+* Description    : Configure the TI1 as Input.
+* Input          : - TIM1_ICPolarity : The Input Polarity.
+*                    This parameter can be one of the following values:
+*                       - TIM1_ICPolarity_Rising
+*                       - TIM1_ICPolarity_Falling
+*                  - TIM1_ICSelection: specifies the input to be used.
+*                    This parameter can be one of the following values:
+*                       - TIM1_ICSelection_DirectTI: TIM1 Input 1 is selected to
+*                         be connected to IC1.
+*                       - TIM1_ICSelection_IndirectTI: TIM1 Input 1 is selected to
+*                         be connected to IC2.
+*                       - TIM1_ICSelection_TRGI:TIM1 Input 1 is selected to be
+*                         connected to TRGI.
+*                  - TIM1_ICFilter: Specifies the Input Capture Filter.
+*                    This parameter must be a value between 0x00 and 0x0F.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+static void TI1_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
+                       u8 TIM1_ICFilter)
+{
+  u32 tmpccmr1 = 0;
+
+  tmpccmr1 = TIM1->CCMR1;
+
+  /* Disable the Channel 1: Reset the CCE Bit */
+  *(vu32 *) CCER_CC1E_BB = CCER_CCE_Reset;
+
+  /* Select the Input and set the filter */
+  tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
+  tmpccmr1 |= (u16)TIM1_ICSelection | (u16)((u16)TIM1_ICFilter << 4);
+
+  TIM1->CCMR1 = (u16)tmpccmr1;
+
+  /* Select the Polarity */
+  *(vu32 *) CCER_CC1P_BB = TIM1_ICPolarity;
+
+  /* Set the CCE Bit */
+  *(vu32 *) CCER_CC1E_BB = CCER_CCE_Set;
+}
+
+/*******************************************************************************
+* Function Name  : TI2_Config
+* Description    : Configure the TI2 as Input.
+* Input          : - TIM1_ICPolarity : The Input Polarity.
+*                    This parameter can be one of the following values:
+*                       - TIM1_ICPolarity_Rising
+*                       - TIM1_ICPolarity_Falling
+*                  - TIM1_ICSelection: specifies the input to be used.
+*                    This parameter can be one of the following values:
+*                       - TIM1_ICSelection_DirectTI: TIM1 Input 2 is selected to
+*                         be connected to IC2.
+*                       - TIM1_ICSelection_IndirectTI: TIM1 Input 2 is selected to
+*                         be connected to IC1.
+*                       - TIM1_ICSelection_TRGI: TIM1 Input 2 is selected to be
+*                         connected to TRGI.
+*                  - TIM1_ICFilter: Specifies the Input Capture Filter.
+*                    This parameter must be a value between 0x00 and 0x0F.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+static void TI2_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
+                       u8 TIM1_ICFilter)
+{
+  u32 tmpccmr1 = 0;
+
+  tmpccmr1 = TIM1->CCMR1;
+
+  /* Disable the Channel 2: Reset the CCE Bit */
+  *(vu32 *) CCER_CC2E_BB = CCER_CCE_Reset;
+
+  /* Select the Input and set the filter */
+  tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
+  tmpccmr1 |= (u16)((u16)TIM1_ICSelection << 8) | (u16)((u16)TIM1_ICFilter <<12);
+
+  TIM1->CCMR1 = (u16)tmpccmr1;
+
+  /* Select the Polarity */
+  *(vu32 *) CCER_CC2P_BB = TIM1_ICPolarity;
+
+  /* Set the CCE Bit */
+  *(vu32 *) CCER_CC2E_BB = CCER_CCE_Set;
+
+}
+
+/*******************************************************************************
+* Function Name  : TI3_Config
+* Description    : Configure the TI3 as Input.
+* Input          : - TIM1_ICPolarity : The Input Polarity.
+*                    This parameter can be one of the following values:
+*                       - TIM1_ICPolarity_Rising
+*                       - TIM1_ICPolarity_Falling
+*                  - TIM1_ICSelection: specifies the input to be used.
+*                    This parameter can be one of the following values:
+*                       - TIM1_ICSelection_DirectTI: TIM1 Input 3 is selected to
+*                         be connected to IC3.
+*                       - TIM1_ICSelection_IndirectTI: TIM1 Input 3 is selected to
+*                         be connected to IC4.
+*                       - TIM1_ICSelection_TRGI: TIM1 Input 3 is selected to be
+*                         connected to TRGI.
+*                  - TIM1_ICFilter: Specifies the Input Capture Filter.
+*                    This parameter must be a value between 0x00 and 0x0F.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+static void TI3_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
+                       u8 TIM1_ICFilter)
+{
+  u32 tmpccmr2 = 0;
+
+  tmpccmr2 = TIM1->CCMR2;
+
+  /* Disable the Channel 3: Reset the CCE Bit */
+  *(vu32 *) CCER_CC3E_BB = CCER_CCE_Reset;
+
+  /* Select the Input and set the filter */
+  tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
+  tmpccmr2 |= (u16)TIM1_ICSelection | (u16)((u16)TIM1_ICFilter << 4);
+
+  TIM1->CCMR2 = (u16)tmpccmr2;
+
+  /* Select the Polarity */
+  *(vu32 *) CCER_CC3P_BB = TIM1_ICPolarity;
+
+  /* Set the CCE Bit */
+  *(vu32 *) CCER_CC3E_BB = CCER_CCE_Set;
+}
+
+/*******************************************************************************
+* Function Name  : TI4_Config
+* Description    : Configure the TI4 as Input.
+* Input          : - TIM1_ICPolarity : The Input Polarity.
+*                    This parameter can be one of the following values:
+*                       - TIM1_ICPolarity_Rising
+*                       - TIM1_ICPolarity_Falling
+*                  - TIM1_ICSelection: specifies the input to be used.
+*                    This parameter can be one of the following values:
+*                       - TIM1_ICSelection_DirectTI: TIM1 Input 4 is selected to
+*                         be connected to IC4.
+*                       - TIM1_ICSelection_IndirectTI: TIM1 Input 4 is selected to
+*                         be connected to IC3.
+*                       - TIM1_ICSelection_TRGI: TIM1 Input 4 is selected to be
+*                         connected to TRGI.
+*                  - TIM1_ICFilter: Specifies the Input Capture Filter.
+*                    This parameter must be a value between 0x00 and 0x0F.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+static void TI4_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,
+                       u8 TIM1_ICFilter)
+{
+  u32 tmpccmr2 = 0;
+
+  tmpccmr2 = TIM1->CCMR2;
+  
+  /* Disable the Channel 4: Reset the CCE Bit */
+  *(vu32 *) CCER_CC4E_BB = CCER_CCE_Reset;
+
+  /* Select the Input and set the filter */
+  tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
+  tmpccmr2 |= (u16)((u16)TIM1_ICSelection << 8) | (u16)((u16)TIM1_ICFilter << 12);
+
+  TIM1->CCMR2 = (u16)tmpccmr2;
+
+  /* Select the Polarity */
+  *(vu32 *) CCER_CC4P_BB = TIM1_ICPolarity;
+
+  /* Set the CCE Bit */
+  *(vu32 *) CCER_CC4E_BB = CCER_CCE_Set;
+}
+
+/*******************************************************************************
+* Function Name  : ETR_Config
+* Description    : Configure the External Trigger
+* Input          : - TIM1_ExtTRGPrescaler: The external Trigger Prescaler.
+*                    This parameter can be one of the following values:
+*                       - TIM1_ExtTRGPSC_OFF
+*                       - TIM1_ExtTRGPSC_DIV2
+*                       - TIM1_ExtTRGPSC_DIV4
+*                       - TIM1_ExtTRGPSC_DIV8
+*                  - TIM1_ExtTRGPolarity: The external Trigger Polarity.
+*                    This parameter can be one of the following values:
+*                       - TIM1_ExtTRGPolarity_Inverted
+*                       - TIM1_ExtTRGPolarity_NonInverted
+*                  - ExtTRGFilter: External Trigger Filter.
+*                    This parameter must be a value between 0x00 and 0x0F.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+static void ETR_Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,
+                       u16 ExtTRGFilter)
+{
+  u32 tmpsmcr = 0;
+
+  tmpsmcr = TIM1->SMCR;
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr &= SMCR_ETR_Mask;
+  tmpsmcr |= TIM1_ExtTRGPrescaler | TIM1_ExtTRGPolarity | (u16)((u16)ExtTRGFilter << 8);
+
+  TIM1->SMCR = (u16)tmpsmcr;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_usart.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_usart.c
new file mode 100644
index 0000000..7bc288a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_usart.c
@@ -0,0 +1,852 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_usart.c
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file provides all the USART firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_usart.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* USART RUN Mask */
+#define CR1_RUN_Set               ((u16)0x2000)  /* USART Enable Mask */
+#define CR1_RUN_Reset             ((u16)0xDFFF)  /* USART Disable Mask */
+
+#define CR2_Address_Mask          ((u16)0xFFF0)  /* USART address Mask */
+
+/* USART RWU Mask */
+#define CR1_RWU_Set               ((u16)0x0002)  /* USART mute mode Enable Mask */
+#define CR1_RWU_Reset             ((u16)0xFFFD)  /* USART mute mode Enable Mask */
+
+#define USART_IT_Mask             ((u16)0x001F)  /* USART Interrupt Mask */
+
+/* USART LIN Mask */
+#define CR2_LINE_Set              ((u16)0x4000)  /* USART LIN Enable Mask */
+#define CR2_LINE_Reset            ((u16)0xBFFF)  /* USART LIN Disable Mask */
+
+#define CR1_SBK_Set               ((u16)0x0001)  /* USART Break Character send Mask */
+
+/* USART SC Mask */
+#define CR3_SCEN_Set              ((u16)0x0020)  /* USART SC Enable Mask */
+#define CR3_SCEN_Reset            ((u16)0xFFDF)  /* USART SC Disable Mask */
+
+/* USART SC NACK Mask */
+#define CR3_NACK_Set              ((u16)0x0010)  /* USART SC NACK Enable Mask */
+#define CR3_NACK_Reset            ((u16)0xFFEF)  /* USART SC NACK Disable Mask */
+
+/* USART Half-Duplex Mask */
+#define CR3_HDSEL_Set             ((u16)0x0008)  /* USART Half-Duplex Enable Mask */
+#define CR3_HDSEL_Reset           ((u16)0xFFF7)  /* USART Half-Duplex Disable Mask */
+
+/* USART IrDA Mask */
+#define CR3_IRLP_Mask             ((u16)0xFFFB)  /* USART IrDA LowPower mode Mask */
+
+/* USART LIN Break detection */
+#define CR3_LBDL_Mask             ((u16)0xFFDF)  /* USART LIN Break detection Mask */
+
+/* USART WakeUp Method  */
+#define CR3_WAKE_Mask             ((u16)0xF7FF)  /* USART WakeUp Method Mask */
+
+/* USART IrDA Mask */
+#define CR3_IREN_Set              ((u16)0x0002)  /* USART IrDA Enable Mask */
+#define CR3_IREN_Reset            ((u16)0xFFFD)  /* USART IrDA Disable Mask */
+
+#define GTPR_LSB_Mask             ((u16)0x00FF)  /* Guard Time Register LSB Mask */
+#define GTPR_MSB_Mask             ((u16)0xFF00)  /* Guard Time Register MSB Mask */
+
+#define CR1_CLEAR_Mask            ((u16)0xE9F3)  /* USART CR1 Mask */
+#define CR2_CLEAR_Mask            ((u16)0xC0FF)  /* USART CR2 Mask */
+#define CR3_CLEAR_Mask            ((u16)0xFCFF)  /* USART CR3 Mask */
+
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : USART_DeInit
+* Description    : Deinitializes the USARTx peripheral registers to their
+*                  default reset values.
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART
+*                    peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USART_DeInit(USART_TypeDef* USARTx)
+{
+  switch (*(u32*)&USARTx)
+  {
+    case USART1_BASE:
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
+      break;
+
+    case USART2_BASE:
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
+      break;
+
+    case USART3_BASE:
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
+      break;
+
+    default:
+      break;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : USART_Init
+* Description    : Initializes the USARTx peripheral according to the specified
+*                  parameters in the USART_InitStruct .
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+*                  - USART_InitStruct: pointer to a USART_InitTypeDef structure
+*                    that contains the configuration information for the
+*                    specified USART peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
+{
+  u32 tmpreg = 0x00, apbclock = 0x00;
+  u32 integerdivider = 0x00;
+  u32 fractionaldivider = 0x00;
+  RCC_ClocksTypeDef RCC_ClocksStatus;
+
+  /* Check the parameters */
+  assert(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
+  assert(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
+  assert(IS_USART_PARITY(USART_InitStruct->USART_Parity));
+  assert(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
+  assert(IS_USART_MODE(USART_InitStruct->USART_Mode));
+  assert(IS_USART_CLOCK(USART_InitStruct->USART_Clock));
+  assert(IS_USART_CPOL(USART_InitStruct->USART_CPOL));
+  assert(IS_USART_CPHA(USART_InitStruct->USART_CPHA));
+  assert(IS_USART_LASTBIT(USART_InitStruct->USART_LastBit));              
+  
+/*---------------------------- USART CR2 Configuration -----------------------*/
+  tmpreg = USARTx->CR2;
+  /* Clear STOP[13:12], CLKEN, CPOL, CPHA and LBCL bits */
+  tmpreg &= CR2_CLEAR_Mask;
+
+  /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
+  /* Set STOP[13:12] bits according to USART_Mode value */
+  /* Set CPOL bit according to USART_CPOL value */
+  /* Set CPHA bit according to USART_CPHA value */
+  /* Set LBCL bit according to USART_LastBit value */
+  tmpreg |= (u32)USART_InitStruct->USART_StopBits | USART_InitStruct->USART_Clock |
+            USART_InitStruct->USART_CPOL | USART_InitStruct->USART_CPHA |
+            USART_InitStruct->USART_LastBit;
+
+  /* Write to USART CR2 */
+  USARTx->CR2 = (u16)tmpreg;
+
+/*---------------------------- USART CR1 Configuration -----------------------*/
+  tmpreg = 0x00;
+  tmpreg = USARTx->CR1;
+  /* Clear M, PCE, PS, TE and RE bits */
+  tmpreg &= CR1_CLEAR_Mask;
+
+  /* Configure the USART Word Length, Parity and mode ----------------------- */
+  /* Set the M bits according to USART_WordLength value */
+  /* Set PCE and PS bits according to USART_Parity value */
+  /* Set TE and RE bits according to USART_Mode value */
+  tmpreg |= (u32)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
+            USART_InitStruct->USART_Mode;
+
+  /* Write to USART CR1 */
+  USARTx->CR1 = (u16)tmpreg;
+
+/*---------------------------- USART CR3 Configuration -----------------------*/
+  tmpreg = 0x00;
+  tmpreg = USARTx->CR3;
+  /* Clear CTSE and RTSE bits */
+  tmpreg &= CR3_CLEAR_Mask;
+
+  /* Configure the USART HFC -------------------------------------------------*/
+  /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
+  tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
+
+  /* Write to USART CR3 */
+  USARTx->CR3 = (u16)tmpreg;
+
+/*---------------------------- USART BRR Configuration -----------------------*/
+  tmpreg = 0x00;
+
+  /* Configure the USART Baud Rate -------------------------------------------*/
+  RCC_GetClocksFreq(&RCC_ClocksStatus);
+  if ((*(u32*)&USARTx) == USART1_BASE)
+  {
+    apbclock = RCC_ClocksStatus.PCLK2_Frequency;
+  }
+  else
+  {
+    apbclock = RCC_ClocksStatus.PCLK1_Frequency;
+  }
+
+  /* Determine the integer part */
+  integerdivider = ((0x19 * apbclock) / (0x04 * (USART_InitStruct->USART_BaudRate)));
+  tmpreg = (integerdivider / 0x64) << 0x04;
+
+  /* Determine the fractional part */
+  fractionaldivider = integerdivider - (0x64 * (tmpreg >> 0x04));
+  tmpreg |= ((((fractionaldivider * 0x10) + 0x32) / 0x64)) & ((u8)0x0F);
+
+  /* Write to USART BRR */
+  USARTx->BRR = (u16)tmpreg;
+}
+
+/*******************************************************************************
+* Function Name  : USART_StructInit
+* Description    : Fills each USART_InitStruct member with its default value.
+* Input          : - USART_InitStruct: pointer to a USART_InitTypeDef structure
+*                    which will be initialized.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
+{
+  /* USART_InitStruct members default value */
+  USART_InitStruct->USART_BaudRate = 0x2580; /* 9600 Baud */
+  USART_InitStruct->USART_WordLength = USART_WordLength_8b;
+  USART_InitStruct->USART_StopBits = USART_StopBits_1;
+  USART_InitStruct->USART_Parity = USART_Parity_No ;
+  USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+  USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+  USART_InitStruct->USART_Clock = USART_Clock_Disable;
+  USART_InitStruct->USART_CPOL = USART_CPOL_Low;
+  USART_InitStruct->USART_CPHA = USART_CPHA_1Edge;
+  USART_InitStruct->USART_LastBit = USART_LastBit_Disable;
+}
+
+/*******************************************************************************
+* Function Name  : USART_Cmd
+* Description    : Enables or disables the specified USART peripheral.
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART
+*                    peripheral.
+*                : - NewState: new state of the USARTx peripheral.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected USART by setting the RUN bit in the CR1 register */
+    USARTx->CR1 |= CR1_RUN_Set;
+  }
+  else
+  {
+    /* Disable the selected USART by clearing the RUN bit in the CR1 register */
+    USARTx->CR1 &= CR1_RUN_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : USART_ITConfig
+* Description    : Enables or disables the specified USART interrupts.
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART
+*                    peripheral.
+*                  - USART_IT: specifies the USART interrupt sources to be
+*                    enabled or disabled.
+*                    This parameter can be one of the following values:
+*                       - USART_IT_PE
+*                       - USART_IT_TXE
+*                       - USART_IT_TC
+*                       - USART_IT_RXNE
+*                       - USART_IT_IDLE
+*                       - USART_IT_LBD
+*                       - USART_IT_CTS
+*                       - USART_IT_ERR
+*                  - NewState: new state of the specified USARTx interrupts.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState)
+{
+  u32 usartreg = 0x00, itpos = 0x00, itmask = 0x00;
+  u32 address = 0x00;
+
+  /* Check the parameters */
+  assert(IS_USART_CONFIG_IT(USART_IT));  
+  assert(IS_FUNCTIONAL_STATE(NewState));
+  
+  /* Get the USART register index */
+  usartreg = (((u8)USART_IT) >> 0x05);
+
+  /* Get the interrupt position */
+  itpos = USART_IT & USART_IT_Mask;
+
+  itmask = (((u32)0x01) << itpos);
+  address = *(u32*)&(USARTx);
+
+  if (usartreg == 0x01) /* The IT  is in CR1 register */
+  {
+    address += 0x0C;
+  }
+  else if (usartreg == 0x02) /* The IT  is in CR2 register */
+  {
+    address += 0x10;
+  }
+  else /* The IT  is in CR3 register */
+  {
+    address += 0x14; 
+  }
+  if (NewState != DISABLE)
+  {
+    *(u32*)address  |= itmask;
+  }
+  else
+  {
+    *(u32*)address &= ~itmask;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : USART_DMACmd
+* Description    : Enables or disables the USART’s DMA interface.
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART
+*                    peripheral.
+*                  - USART_DMAReq: specifies the DMA request.
+*                    This parameter can be any combination of the following values:
+*                       - USART_DMAReq_Tx
+*                       - USART_DMAReq_Rx
+*                  - NewState: new state of the DMA Request sources.
+*                   This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USART_DMACmd(USART_TypeDef* USARTx, u16 USART_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_USART_DMAREQ(USART_DMAReq));  
+  assert(IS_FUNCTIONAL_STATE(NewState)); 
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA transfer for selected requests by setting the DMAT and/or
+    DMAR bits in the USART CR3 register */
+    USARTx->CR3 |= USART_DMAReq;
+  }
+  else
+  {
+    /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
+    DMAR bits in the USART CR3 register */
+    USARTx->CR3 &= (u16)~USART_DMAReq;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : USART_SetAddress
+* Description    : Sets the address of the USART node.
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART
+*                    peripheral.
+*                  - USART_Address: Indicates the address of the USART node.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USART_SetAddress(USART_TypeDef* USARTx, u8 USART_Address)
+{
+  /* Check the parameters */
+  assert(IS_USART_ADDRESS(USART_Address)); 
+    
+  /* Clear the USART address */
+  USARTx->CR2 &= CR2_Address_Mask;
+  /* Set the USART address node */
+  USARTx->CR2 |= USART_Address;
+}
+
+/*******************************************************************************
+* Function Name  : USART_WakeUpConfig
+* Description    : Selects the USART WakeUp method.
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART
+*                    peripheral.
+*                  - USART_WakeUp: specifies the USART wakeup method.
+*                    This parameter can be one of the following values:
+*                        - USART_WakeUp_IdleLine
+*                        - USART_WakeUp_AddressMark
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USART_WakeUpConfig(USART_TypeDef* USARTx, u16 USART_WakeUp)
+{
+  /* Check the parameters */
+  assert(IS_USART_WAKEUP(USART_WakeUp));
+  
+  USARTx->CR1 &= CR3_WAKE_Mask;
+  USARTx->CR1 |= USART_WakeUp;
+}
+
+/*******************************************************************************
+* Function Name  : USART_ReceiverWakeUpCmd
+* Description    : Determines if the USART is in mute mode or not.
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART
+*                    peripheral.
+*                  - NewState: new state of the USART mode.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState)); 
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the mute mode USART by setting the RWU bit in the CR1 register */
+    USARTx->CR1 |= CR1_RWU_Set;
+  }
+  else
+  {
+    /* Disable the mute mode USART by clearing the RWU bit in the CR1 register */
+    USARTx->CR1 &= CR1_RWU_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : USART_LINBreakDetectLengthConfig
+* Description    : Sets the USART LIN Break detection length.
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART
+*                    peripheral.
+*                  - USART_LINBreakDetectLength: specifies the LIN break
+*                    detection length.
+*                    This parameter can be one of the following values:
+*                       - USART_LINBreakDetectLength_10b
+*                       - USART_LINBreakDetectLength_11b
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, u16 USART_LINBreakDetectLength)
+{
+  /* Check the parameters */
+  assert(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
+  
+  USARTx->CR2 &= CR3_LBDL_Mask;
+  USARTx->CR2 |= USART_LINBreakDetectLength;  
+}
+
+/*******************************************************************************
+* Function Name  : USART_LINCmd
+* Description    : Enables or disables the USART’s LIN mode.
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART
+*                    peripheral.
+*                  - NewState: new state of the USART LIN mode.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the LIN mode by setting the LINE bit in the CR2 register */
+    USARTx->CR2 |= CR2_LINE_Set;
+  }
+  else
+  {
+    /* Disable the LIN mode by clearing the LINE bit in the CR2 register */
+    USARTx->CR2 &= CR2_LINE_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : USART_SendData
+* Description    : Transmits signle data through the USARTx peripheral.
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART
+*                    peripheral.
+*                  - Data: the data to transmit.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USART_SendData(USART_TypeDef* USARTx, u16 Data)
+{
+  /* Check the parameters */
+  assert(IS_USART_DATA(Data)); 
+    
+  /* Transmit Data */
+  USARTx->DR = (Data & (u16)0x01FF);
+}
+
+/*******************************************************************************
+* Function Name  : USART_ReceiveData
+* Description    : Returns the most recent received data by the USARTx peripheral.
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART
+*                    peripheral.
+* Output         : None
+* Return         : The received data.
+*******************************************************************************/
+u16 USART_ReceiveData(USART_TypeDef* USARTx)
+{
+  /* Receive Data */
+  return (u16)(USARTx->DR & (u16)0x01FF);
+}
+
+/*******************************************************************************
+* Function Name  : USART_SendBreak
+* Description    : Transmits break characters.
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART
+*                    peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USART_SendBreak(USART_TypeDef* USARTx)
+{
+  /* Send break characters */
+  USARTx->CR1 |= CR1_SBK_Set;
+}
+
+/*******************************************************************************
+* Function Name  : USART_SetGuardTime
+* Description    : Sets the specified USART guard time.
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART
+*                    peripheral.
+*                  - USART_GuardTime: specifies the guard time.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USART_SetGuardTime(USART_TypeDef* USARTx, u8 USART_GuardTime)
+{    
+  /* Clear the USART Guard time */
+  USARTx->GTPR &= GTPR_LSB_Mask;
+  /* Set the USART guard time */
+  USARTx->GTPR |= (u16)((u16)USART_GuardTime << 0x08);
+}
+
+/*******************************************************************************
+* Function Name  : USART_SetPrescaler
+* Description    : Sets the system clock prescaler.
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART
+*                    peripheral.
+*                  - USART_Prescaler: specifies the prescaler clock.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USART_SetPrescaler(USART_TypeDef* USARTx, u8 USART_Prescaler)
+{ 
+  /* Clear the USART prescaler */
+  USARTx->GTPR &= GTPR_MSB_Mask;
+  /* Set the USART prescaler */
+  USARTx->GTPR |= USART_Prescaler;
+}
+
+/*******************************************************************************
+* Function Name  : USART_SmartCardCmd
+* Description    : Enables or disables the USART’s Smart Card mode.
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART
+*                    peripheral.
+*                  - NewState: new state of the Smart Card mode.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+    
+  if (NewState != DISABLE)
+  {
+    /* Enable the SC mode by setting the SCEN bit in the CR3 register */
+    USARTx->CR3 |= CR3_SCEN_Set;
+  }
+  else
+  {
+    /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
+    USARTx->CR3 &= CR3_SCEN_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : USART_SmartCardNACKCmd
+* Description    : Enables or disables NACK transmission.
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART
+*                    peripheral.
+*                  - NewState: new state of the NACK transmission.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+   
+  if (NewState != DISABLE)
+  {
+    /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
+    USARTx->CR3 |= CR3_NACK_Set;
+  }
+  else
+  {
+    /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
+    USARTx->CR3 &= CR3_NACK_Reset;
+  }
+
+}
+
+/*******************************************************************************
+* Function Name  : USART_HalfDuplexCmd
+* Description    : Enables or disables the USART’s Half Duplex communication.
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART
+*                    peripheral.
+*                  - NewState: new state of the USART Communication.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+    USARTx->CR3 |= CR3_HDSEL_Set;
+  }
+  else
+  {
+    /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
+    USARTx->CR3 &= CR3_HDSEL_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : USART_IrDAConfig
+* Description    : Configures the USART’s IrDA interface.
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART
+*                    peripheral.
+*                  - USART_IrDAMode: specifies the IrDA mode.
+*                    This parameter can be one of the following values:
+*                       - USART_IrDAMode_LowPower
+*                       - USART_IrDAMode_Normal
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USART_IrDAConfig(USART_TypeDef* USARTx, u16 USART_IrDAMode)
+{
+  /* Check the parameters */
+  assert(IS_USART_IRDA_MODE(USART_IrDAMode));
+    
+  USARTx->CR3 &= CR3_IRLP_Mask;
+  USARTx->CR3 |= USART_IrDAMode;
+}
+
+/*******************************************************************************
+* Function Name  : USART_IrDACmd
+* Description    : Enables or disables the USART’s IrDA interface.
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART
+*                    peripheral.
+*                  - NewState: new state of the IrDA mode.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert(IS_FUNCTIONAL_STATE(NewState));
+    
+  if (NewState != DISABLE)
+  {
+    /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
+    USARTx->CR3 |= CR3_IREN_Set;
+  }
+  else
+  {
+    /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
+    USARTx->CR3 &= CR3_IREN_Reset;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : USART_GetFlagStatus
+* Description    : Checks whether the specified USART flag is set or not.
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART
+*                    peripheral.
+*                  - USART_FLAG: specifies the flag to check.
+*                    This parameter can be one of the following values:
+*                       - USART_FLAG_CTS
+*                       - USART_FLAG_LBD
+*                       - USART_FLAG_TXE
+*                       - USART_FLAG_TC
+*                       - USART_FLAG_RXNE
+*                       - USART_FLAG_IDLE
+*                       - USART_FLAG_ORE
+*                       - USART_FLAG_NE
+*                       - USART_FLAG_FE
+*                       - USART_FLAG_PE
+* Output         : None
+* Return         : The new state of USART_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, u16 USART_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert(IS_USART_FLAG(USART_FLAG));
+  
+  if ((USARTx->SR & USART_FLAG) != (u16)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : USART_ClearFlag
+* Description    : Clears the USARTx's pending flags.
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART
+*                    peripheral.
+*                  - USART_FLAG: specifies the flag to clear.
+*                    This parameter can be any combination of the following values:
+*                       - USART_FLAG_CTS
+*                       - USART_FLAG_LBD
+*                       - USART_FLAG_TXE
+*                       - USART_FLAG_TC
+*                       - USART_FLAG_RXNE
+*                       - USART_FLAG_IDLE
+*                       - USART_FLAG_ORE
+*                       - USART_FLAG_NE
+*                       - USART_FLAG_FE
+*                       - USART_FLAG_PE
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USART_ClearFlag(USART_TypeDef* USARTx, u16 USART_FLAG)
+{
+  /* Check the parameters */
+  assert(IS_USART_CLEAR_FLAG(USART_FLAG));
+   
+  USARTx->SR &= (u16)~USART_FLAG;
+}
+
+/*******************************************************************************
+* Function Name  : USART_GetITStatus
+* Description    : Checks whether the specified USART interrupt has occurred or not.
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART
+*                    peripheral.
+*                  - USART_IT: specifies the USART interrupt source to check.
+*                    This parameter can be one of the following values:
+*                       - USART_IT_PE
+*                       - USART_IT_TXE
+*                       - USART_IT_TC
+*                       - USART_IT_RXNE
+*                       - USART_IT_IDLE
+*                       - USART_IT_LBD
+*                       - USART_IT_CTS
+*                       - USART_IT_ORE
+*                       - USART_IT_NE
+*                       - USART_IT_FE
+* Output         : None
+* Return         : The new state of USART_IT (SET or RESET).
+*******************************************************************************/
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, u16 USART_IT)
+{
+  u32 bitpos = 0x00, itmask = 0x00, usartreg = 0;
+  ITStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert(IS_USART_IT(USART_IT));
+  
+  /* Get the USART register index */
+  usartreg = (((u8)USART_IT) >> 0x05);
+
+  /* Get the interrupt position */
+  itmask = USART_IT & USART_IT_Mask;
+
+  itmask = (u32)0x01 << itmask;
+  
+  if (usartreg == 0x01) /* The IT  is in CR1 register */
+  {
+    itmask &= USARTx->CR1;
+  }
+  else if (usartreg == 0x02) /* The IT  is in CR2 register */
+  {
+    itmask &= USARTx->CR2;
+  }
+  else /* The IT  is in CR3 register */
+  {
+    itmask &= USARTx->CR3;
+  }
+  
+  bitpos = USART_IT >> 0x08;
+
+  bitpos = (u32)0x01 << bitpos;
+  bitpos &= USARTx->SR;
+
+  if ((itmask != (u16)RESET)&&(bitpos != (u16)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : USART_ClearITPendingBit
+* Description    : Clears the USARTx’s interrupt pending bits.
+* Input          : - USARTx: where x can be 1, 2 or 3 to select the USART
+*                    peripheral.
+*                  - USART_IT: specifies the interrupt pending bit to clear.
+*                    This parameter can be one of the following values:
+*                       - USART_IT_PE
+*                       - USART_IT_TXE
+*                       - USART_IT_TC
+*                       - USART_IT_RXNE
+*                       - USART_IT_IDLE
+*                       - USART_IT_LBD
+*                       - USART_IT_CTS
+*                       - USART_IT_ORE
+*                       - USART_IT_NE
+*                       - USART_IT_FE
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, u16 USART_IT)
+{
+  u32 bitpos = 0x00, itmask = 0x00;
+  
+  /* Check the parameters */
+  assert(IS_USART_IT(USART_IT));
+  
+  bitpos = USART_IT >> 0x08;
+
+  itmask = (u32)0x01 << bitpos;
+  USARTx->SR &= ~itmask;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_wwdg.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_wwdg.c
new file mode 100644
index 0000000..e1cb58d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_wwdg.c
@@ -0,0 +1,194 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : stm32f10x_wwdg.c
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : This file provides all the WWDG firmware functions.
+********************************************************************************
+* History:
+* 04/02/2007: V0.2
+* 02/05/2007: V0.1
+* 09/29/2006: V0.01
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_wwdg.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ----------- WWDG registers bit address in the alias region ----------- */
+#define WWDG_OFFSET       (WWDG_BASE - PERIPH_BASE)
+
+/* Alias word address of EWI bit */
+#define CFR_OFFSET        (WWDG_OFFSET + 0x04)
+#define EWI_BitNumber     0x09
+#define CFR_EWI_BB        (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
+
+/* Alias word address of EWIF bit */
+#define SR_OFFSET         (WWDG_OFFSET + 0x08)
+#define EWIF_BitNumber    0x00
+#define SR_EWIF_BB        (PERIPH_BB_BASE + (SR_OFFSET * 32) + (EWIF_BitNumber * 4))
+
+/* --------------------- WWDG registers bit mask ------------------------ */
+/* CR register bit mask */
+#define CR_WDGA_Set       ((u32)0x00000080)
+
+/* CFR register bit mask */
+#define CFR_WDGTB_Mask    ((u32)0xFFFFFE7F)
+#define CFR_W_Mask        ((u32)0xFFFFFF80)
+
+#define BIT_Mask          ((u8)0x7F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : WWDG_DeInit
+* Description    : Deinitializes the WWDG  peripheral registers to their default
+*                  reset values.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void WWDG_DeInit(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
+}
+
+/*******************************************************************************
+* Function Name  : WWDG_SetPrescaler
+* Description    : Sets the WWDG Prescaler.
+* Input          : - WWDG_Prescaler: specifies the WWDG Prescaler.
+*                    This parameter can be one of the following values:
+*                       - WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
+*                       - WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
+*                       - WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
+*                       - WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void WWDG_SetPrescaler(u32 WWDG_Prescaler)
+{
+  u32 tmpreg = 0;
+
+  /* Check the parameters */
+  assert(IS_WWDG_PRESCALER(WWDG_Prescaler));
+
+  /* Clear WDGTB[8:7] bits */
+  tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
+
+  /* Set WDGTB[8:7] bits according to WWDG_Prescaler value */
+  tmpreg |= WWDG_Prescaler;
+
+  /* Store the new value */
+  WWDG->CFR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name  : WWDG_SetWindowValue
+* Description    : Sets the WWDG window value.
+* Input          : - WindowValue: specifies the window value to be compared to
+*                    the downcounter.
+*                    This parameter value must be lower than 0x80.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void WWDG_SetWindowValue(u8 WindowValue)
+{
+  u32 tmpreg = 0;
+
+  /* Check the parameters */
+  assert(IS_WWDG_WINDOW_VALUE(WindowValue));
+
+  /* Clear W[6:0] bits */
+  tmpreg = WWDG->CFR & CFR_W_Mask;
+
+  /* Set W[6:0] bits according to WindowValue value */
+  tmpreg |= WindowValue & BIT_Mask;
+
+  /* Store the new value */
+  WWDG->CFR = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name  : WWDG_EnableIT
+* Description    : Enables the WWDG Early Wakeup interrupt(EWI).
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void WWDG_EnableIT(void)
+{
+  *(vu32 *) CFR_EWI_BB = (u32)ENABLE;
+}
+
+/*******************************************************************************
+* Function Name  : WWDG_SetCounter
+* Description    : Sets the WWDG counter value.
+* Input          : - Counter: specifies the watchdog counter value.
+*                    This parameter must be a number between 0x40 and 0x7F.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void WWDG_SetCounter(u8 Counter)
+{
+  /* Check the parameters */
+  assert(IS_WWDG_COUNTER(Counter));
+
+  /* Write to T[6:0] bits to configure the counter value, no need to do
+     a read-modify-write; writing a 0 to WDGA bit does nothing */
+  WWDG->CR = Counter & BIT_Mask;
+}
+
+/*******************************************************************************
+* Function Name  : WWDG_Enable
+* Description    : Enables WWDG and load the counter value.
+*                  - Counter: specifies the watchdog counter value.
+*                    This parameter must be a number between 0x40 and 0x7F.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void WWDG_Enable(u8 Counter)
+{
+  /* Check the parameters */
+  assert(IS_WWDG_COUNTER(Counter));
+
+  WWDG->CR = CR_WDGA_Set | Counter;
+}
+
+/*******************************************************************************
+* Function Name  : WWDG_GetFlagStatus
+* Description    : Checks whether the Early Wakeup interrupt flag is set or not.
+* Input          : None
+* Output         : None
+* Return         : The new state of the Early Wakeup interrupt flag (SET or RESET)
+*******************************************************************************/
+FlagStatus WWDG_GetFlagStatus(void)
+{
+  return (FlagStatus)(*(vu32 *) SR_EWIF_BB);
+}
+
+/*******************************************************************************
+* Function Name  : WWDG_ClearFlag
+* Description    : Clears Early Wakeup interrupt flag.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void WWDG_ClearFlag(void)
+{
+  WWDG->SR = (u32)RESET;
+}
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32fxxx_eth.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32fxxx_eth.c
new file mode 100644
index 0000000..29d03b8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32fxxx_eth.c
@@ -0,0 +1,3321 @@
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name          : stm32fxxx_eth.c
+* Author             : MCD Application Team
+* Version            : V1.0.0
+* Date               : 12/17/2008
+* Updates            : 05/2009 Driver optimization.
+*                      - No copy. DMA directly uses Stack packets.
+* Desciption        : This file provides all the ETHERNET firmware functions.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* For the delays. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32fxxx_eth.h"
+#include "stm32f10x_rcc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */
+ETH_DMADESCTypeDef  *DMATxDescToSet;
+ETH_DMADESCTypeDef  *DMARxDescToGet;
+
+ETH_DMADESCTypeDef  *DMAPTPTxDescToSet;
+ETH_DMADESCTypeDef  *DMAPTPRxDescToGet;
+
+/* ETHERNET MAC address offsets */
+#define ETH_MAC_AddrHighBase   (ETH_MAC_BASE + 0x40)  /* ETHERNET MAC address high offset */
+#define ETH_MAC_AddrLowBase    (ETH_MAC_BASE + 0x44)  /* ETHERNET MAC address low offset */
+
+/* ETHERNET MACMIIAR register Mask */
+#define MACMIIAR_CR_Mask    ((u32)0xFFFFFFE3)
+/* ETHERNET MACCR register Mask */
+#define MACCR_CLEAR_Mask    ((u32)0xFF20810F)
+/* ETHERNET MACFCR register Mask */
+#define MACFCR_CLEAR_Mask   ((u32)0x0000FF41)
+/* ETHERNET DMAOMR register Mask */
+#define DMAOMR_CLEAR_Mask   ((u32)0xF8DE3F23)
+
+/* ETHERNET Remote Wake-up frame register length */
+#define ETH_WakeupRegisterLength      8
+
+/* ETHERNET Missed frames counter Shift */
+#define  ETH_DMA_RxOverflowMissedFramesCounterShift     17
+
+/* ETHERNET DMA Tx descriptors Collision Count Shift */
+#define  ETH_DMATxDesc_CollisionCountShift        3
+/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
+#define  ETH_DMATxDesc_BufferSize2Shift           16
+/* ETHERNET DMA Rx descriptors Frame Length Shift */
+#define  ETH_DMARxDesc_FrameLengthShift           16
+/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
+#define  ETH_DMARxDesc_Buffer2SizeShift           16
+
+/* ETHERNET errors */
+#define  ETH_ERROR              ((u32)0)
+#define  ETH_SUCCESS            ((u32)1)
+
+#define ethFIVE_SECONDS			( 5000 / portTICK_PERIOD_MS )
+#define ethHUNDRED_MS			( 100 / portTICK_PERIOD_MS )
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : ETH_DeInit
+* Desciption     : Deinitializes the ETHERNET peripheral registers to their
+*                  default reset values.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_DeInit(void)
+{
+//  RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, ENABLE);
+//  RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, DISABLE);
+}
+
+/*******************************************************************************
+* Function Name  : ETH_Init
+* Desciption     : Initializes the ETHERNET peripheral according to the specified
+*                  parameters in the ETH_InitStruct .
+* Input          : - ETH_InitStruct: pointer to a ETH_InitTypeDef structure
+*                    that contains the configuration information for the
+*                    specified ETHERNET peripheral.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+u32 ETH_Init(ETH_InitTypeDef* ETH_InitStruct, u16 PHYAddress)
+{
+  u32 RegValue = 0, tmpreg = 0;
+  RCC_ClocksTypeDef  rcc_clocks;
+  u32 hclk = 60000000;
+  u32 timeout = 0;
+
+  /* Check the parameters */
+  /* MAC --------------------------*/
+  eth_assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation));
+  eth_assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog));
+  eth_assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber));
+  eth_assert_param(IS_ETH_JUMBO_FRAME(ETH_InitStruct->ETH_JumboFrame));
+  eth_assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap));
+  eth_assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense));
+  eth_assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed));
+  eth_assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn));
+  eth_assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode));
+  eth_assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode));
+  eth_assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload));
+  eth_assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission));
+  eth_assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip));
+  eth_assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit));
+  eth_assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck));
+  eth_assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll));
+  eth_assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter));
+  eth_assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames));
+  eth_assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception));
+  eth_assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter));
+  eth_assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode));
+  eth_assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter));
+  eth_assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter));
+  eth_assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime));
+  eth_assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause));
+  eth_assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold));
+  eth_assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect));
+  eth_assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl));
+  eth_assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl));
+  eth_assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison));
+  eth_assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier));
+  /* DMA --------------------------*/
+  eth_assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame));
+  eth_assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward));
+  eth_assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame));
+  eth_assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward));
+  eth_assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl));
+  eth_assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames));
+  eth_assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames));
+  eth_assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl));
+  eth_assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate));
+  eth_assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats));
+  eth_assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst));
+  eth_assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength));
+  eth_assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength));
+  eth_assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength));
+  eth_assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration));
+
+/*--------------------------------- MAC Config -------------------------------*/
+/*----------------------- ETHERNET MACMIIAR Configuration --------------------*/
+  /* Get the ETHERNET MACMIIAR value */
+  tmpreg = ETH_MAC->MACMIIAR;
+  /* Clear CSR Clock Range CR[2:0] bits */
+  tmpreg &= MACMIIAR_CR_Mask;
+  /* Get hclk frequency value */
+  RCC_GetClocksFreq(&rcc_clocks);
+  hclk = rcc_clocks.HCLK_Frequency;
+
+  /* Set CR bits depending on hclk value */
+  if((hclk >= 20000000)&&(hclk < 35000000))
+  {
+    /* CSR Clock Range between 20-35 MHz */
+    tmpreg |= (u32)ETH_MACMIIAR_CR_Div16;
+  }
+  else if((hclk >= 35000000)&&(hclk < 60000000))
+  {
+    /* CSR Clock Range between 35-60 MHz */
+    tmpreg |= (u32)ETH_MACMIIAR_CR_Div26;
+  }
+  else /* ((hclk >= 60000000)&&(hclk <= 72000000)) */
+  {
+    /* CSR Clock Range between 60-72 MHz */
+    tmpreg |= (u32)ETH_MACMIIAR_CR_Div42;
+  }
+  /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
+  ETH_MAC->MACMIIAR = (u32)tmpreg;
+
+/*--------------------- PHY initialization and configuration -----------------*/
+  /* Put the PHY in reset mode */
+  if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset)))
+  {
+    /* Return ERROR in case of write timeout */
+    return ETH_ERROR;
+  }
+
+  /* Delay to assure PHY reset */
+  vTaskDelay( 250 / portTICK_PERIOD_MS );
+
+  if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)
+  {
+    /* We wait for linked satus... */
+	timeout = 0;
+    do
+    {
+      /* Wait 100ms before checking for a link again. */
+      vTaskDelay( ethHUNDRED_MS );
+	  timeout++;
+
+	  /* Don't wait any longer than 5 seconds. */
+    } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < ( ethFIVE_SECONDS / ethHUNDRED_MS ) ) );
+
+    /* Return ERROR in case of timeout */
+    if(timeout == ( ethFIVE_SECONDS / ethHUNDRED_MS ))
+    {
+      return ETH_ERROR;
+    }
+
+    /* Enable Auto-Negotiation */
+    if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation)))
+    {
+      /* Return ERROR in case of write timeout */
+      return ETH_ERROR;
+    }
+
+    /* Reset Timeout counter */
+    timeout = 0;
+
+    /* Wait until the autonegotiation will be completed */
+    do
+    {
+      /* Wait 100ms before checking for negotiation to complete. */
+      vTaskDelay( ethHUNDRED_MS );
+	  timeout++;
+
+	  /* Don't wait longer than 5 seconds. */
+    } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < ( ethFIVE_SECONDS / ethHUNDRED_MS ) ) );
+
+    /* Return ERROR in case of timeout */
+    if(timeout == ( ethFIVE_SECONDS / ethHUNDRED_MS ))
+    {
+      return ETH_ERROR;
+    }
+
+    /* Reset Timeout counter */
+    timeout = 0;
+
+    /* Read the result of the autonegotiation */
+    RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR);
+
+    /* Configure the MAC with the Duplex Mode fixed by the autonegotiation process */
+    if((RegValue & PHY_Duplex_Status) != (u32)RESET)
+    {
+      /* Set Ethernet duplex mode to FullDuplex following the autonegotiation */
+      ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
+
+    }
+    else
+    {
+      /* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */
+      ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
+    }
+    /* Configure the MAC with the speed fixed by the autonegotiation process */
+    if(RegValue & PHY_Speed_Status)
+    {
+      /* Set Ethernet speed to 100M following the autonegotiation */
+      ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
+    }
+    else
+    {
+      /* Set Ethernet speed to 10M following the autonegotiation */
+      ETH_InitStruct->ETH_Speed = ETH_Speed_100M;
+    }
+  }
+//  else
+  {
+    if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((u16)(ETH_InitStruct->ETH_Mode >> 3) |
+                                                   (u16)(ETH_InitStruct->ETH_Speed >> 1))))
+    {
+      /* Return ERROR in case of write timeout */
+      return ETH_ERROR;
+    }
+
+    vTaskDelay( 250 / portTICK_PERIOD_MS );
+  }
+
+/*------------------------- ETHERNET MACCR Configuration ---------------------*/
+  /* Get the ETHERNET MACCR value */
+  tmpreg = ETH_MAC->MACCR;
+  /* Clear WD, PCE, PS, TE and RE bits */
+  tmpreg &= MACCR_CLEAR_Mask;
+
+  /* Set the WD bit according to ETH_Watchdog value */
+  /* Set the JD: bit according to ETH_Jabber value */
+  /* Set the JE bit according to ETH_JumboFrame value */
+  /* Set the IFG bit according to ETH_InterFrameGap value */
+  /* Set the DCRS bit according to ETH_CarrierSense value */
+  /* Set the FES bit according to ETH_Speed value */
+  /* Set the DO bit according to ETH_ReceiveOwn value */
+  /* Set the LM bit according to ETH_LoopbackMode value */
+  /* Set the DM bit according to ETH_Mode value */
+  /* Set the IPC bit according to ETH_ChecksumOffload value */
+  /* Set the DR bit according to ETH_RetryTransmission value */
+  /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */
+  /* Set the BL bit according to ETH_BackOffLimit value */
+  /* Set the DC bit according to ETH_DeferralCheck value */
+  tmpreg |= (u32)(ETH_InitStruct->ETH_Watchdog |
+                  ETH_InitStruct->ETH_Jabber |
+                  ETH_InitStruct->ETH_JumboFrame |
+                  ETH_InitStruct->ETH_InterFrameGap |
+                  ETH_InitStruct->ETH_CarrierSense |
+                  ETH_InitStruct->ETH_Speed |
+                  ETH_InitStruct->ETH_ReceiveOwn |
+                  ETH_InitStruct->ETH_LoopbackMode |
+                  ETH_InitStruct->ETH_Mode |
+                  ETH_InitStruct->ETH_ChecksumOffload |
+                  ETH_InitStruct->ETH_RetryTransmission |
+                  ETH_InitStruct->ETH_AutomaticPadCRCStrip |
+                  ETH_InitStruct->ETH_BackOffLimit |
+                  ETH_InitStruct->ETH_DeferralCheck);
+
+  /* Write to ETHERNET MACCR */
+  ETH_MAC->MACCR = (u32)tmpreg;
+
+/*------------------------ ETHERNET MACFFR Configuration ---------------------*/
+  /* Set the RA bit according to ETH_ReceiveAll value */
+  /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */
+  /* Set the PCF bit according to ETH_PassControlFrames value */
+  /* Set the DBF bit according to ETH_BroadcastFramesReception value */
+  /* Set the DAIF bit according to ETH_DestinationAddrFilter value */
+  /* Set the PR bit according to ETH_PromiscuousMode value */
+  /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */
+  /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */
+  /* Write to ETHERNET MACFFR */
+  ETH_MAC->MACFFR = (u32)(ETH_InitStruct->ETH_ReceiveAll |
+                          ETH_InitStruct->ETH_SourceAddrFilter |
+                          ETH_InitStruct->ETH_PassControlFrames |
+                          ETH_InitStruct->ETH_BroadcastFramesReception |
+                          ETH_InitStruct->ETH_DestinationAddrFilter |
+                          ETH_InitStruct->ETH_PromiscuousMode |
+                          ETH_InitStruct->ETH_MulticastFramesFilter |
+                          ETH_InitStruct->ETH_UnicastFramesFilter);
+
+/*---------------- ETHERNET MACHTHR and MACHTLR Configuration ----------------*/
+  /* Write to ETHERNET MACHTHR */
+  ETH_MAC->MACHTHR = (u32)ETH_InitStruct->ETH_HashTableHigh;
+  /* Write to ETHERNET MACHTLR */
+  ETH_MAC->MACHTLR = (u32)ETH_InitStruct->ETH_HashTableLow;
+
+/*------------------------ ETHERNET MACFCR Configuration ---------------------*/
+  /* Get the ETHERNET MACFCR value */
+  tmpreg = ETH_MAC->MACFCR;
+  /* Clear xx bits */
+  tmpreg &= MACFCR_CLEAR_Mask;
+
+  /* Set the PT bit according to ETH_PauseTime value */
+  /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */
+  /* Set the PLT bit according to ETH_PauseLowThreshold value */
+  /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */
+  /* Set the RFE bit according to ETH_ReceiveFlowControl value */
+  /* Set the TFE bit according to ETH_TransmitFlowControl value */
+  tmpreg |= (u32)((ETH_InitStruct->ETH_PauseTime << 16) |
+                   ETH_InitStruct->ETH_ZeroQuantaPause |
+                   ETH_InitStruct->ETH_PauseLowThreshold |
+                   ETH_InitStruct->ETH_UnicastPauseFrameDetect |
+                   ETH_InitStruct->ETH_ReceiveFlowControl |
+                   ETH_InitStruct->ETH_TransmitFlowControl);
+
+  /* Write to ETHERNET MACFCR */
+  ETH_MAC->MACFCR = (u32)tmpreg;
+
+/*------------------------ ETHERNET MACVLANTR Configuration ------------------*/
+  /* Set the ETV bit according to ETH_VLANTagComparison value */
+  /* Set the VL bit according to ETH_VLANTagIdentifier value */
+  ETH_MAC->MACVLANTR = (u32)(ETH_InitStruct->ETH_VLANTagComparison |
+                             ETH_InitStruct->ETH_VLANTagIdentifier);
+
+#ifdef _ETH_DMA
+/*--------------------------------- DMA Config -------------------------------*/
+/*------------------------ ETHERNET DMAOMR Configuration ---------------------*/
+  /* Get the ETHERNET DMAOMR value */
+  tmpreg = ETH_DMA->DMAOMR;
+  /* Clear xx bits */
+  tmpreg &= DMAOMR_CLEAR_Mask;
+
+  /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */
+  /* Set the RSF bit according to ETH_ReceiveStoreForward value */
+  /* Set the DFF bit according to ETH_FlushReceivedFrame value */
+  /* Set the TSF bit according to ETH_TransmitStoreForward value */
+  /* Set the TTC bit according to ETH_TransmitThresholdControl value */
+  /* Set the FEF bit according to ETH_ForwardErrorFrames value */
+  /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */
+  /* Set the RTC bit according to ETH_ReceiveThresholdControl value */
+  /* Set the OSF bit according to ETH_SecondFrameOperate value */
+  tmpreg |= (u32)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame |
+                  ETH_InitStruct->ETH_ReceiveStoreForward |
+                  ETH_InitStruct->ETH_FlushReceivedFrame |
+                  ETH_InitStruct->ETH_TransmitStoreForward |
+                  ETH_InitStruct->ETH_TransmitThresholdControl |
+                  ETH_InitStruct->ETH_ForwardErrorFrames |
+                  ETH_InitStruct->ETH_ForwardUndersizedGoodFrames |
+                  ETH_InitStruct->ETH_ReceiveThresholdControl |
+                  ETH_InitStruct->ETH_SecondFrameOperate);
+
+  /* Write to ETHERNET DMAOMR */
+  ETH_DMA->DMAOMR = (u32)tmpreg;
+
+/*------------------------ ETHERNET DMABMR Configuration ---------------------*/
+  /* Set the AAL bit according to ETH_AddressAlignedBeats value */
+  /* Set the FB bit according to ETH_FixedBurst value */
+  /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */
+  /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */
+  /* Set the DSL bit according to ETH_DesciptorSkipLength value */
+  /* Set the PR and DA bits according to ETH_DMAArbitration value */
+  ETH_DMA->DMABMR = (u32)(ETH_InitStruct->ETH_AddressAlignedBeats |
+                          ETH_InitStruct->ETH_FixedBurst |
+                          ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
+                          ETH_InitStruct->ETH_TxDMABurstLength |
+                         (ETH_InitStruct->ETH_DescriptorSkipLength << 2) |
+                          ETH_InitStruct->ETH_DMAArbitration |
+				                  ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
+#endif /* _ETH_DMA */
+
+  /* Return Ethernet configuration success */
+  return ETH_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_StructInit
+* Desciption    : Fills each ETH_InitStruct member with its default value.
+* Input          : - ETH_InitStruct: pointer to a ETH_InitTypeDef structure
+*                    which will be initialized.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct)
+{
+  /* ETH_InitStruct members default value */
+  /*------------------------   MAC   -----------------------------------*/
+  ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable;
+  ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable;
+  ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable;
+  ETH_InitStruct->ETH_JumboFrame = ETH_JumboFrame_Disable;
+  ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit;
+  ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable;
+  ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
+  ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable;
+  ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable;
+  ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
+  ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;
+  ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable;
+  ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
+  ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10;
+  ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable;
+  ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable;
+  ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;
+  ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll;
+  ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
+  ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;
+  ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
+  ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
+  ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
+  ETH_InitStruct->ETH_HashTableHigh = 0x0;
+  ETH_InitStruct->ETH_HashTableLow = 0x0;
+  ETH_InitStruct->ETH_PauseTime = 0x0;
+  ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;
+  ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;
+  ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
+  ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;
+  ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;
+  ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;
+  ETH_InitStruct->ETH_VLANTagIdentifier = 0x0;
+
+#ifdef _ETH_DMA
+/*------------------------   DMA   -----------------------------------*/
+  ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable;
+  ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
+  ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable;
+  ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
+  ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes;
+  ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
+  ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
+  ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;
+  ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;
+  ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
+  ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable;
+  ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat;
+  ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat;
+  ETH_InitStruct->ETH_DescriptorSkipLength = 0x0;
+  ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;
+
+#endif /* _ETH_DMA */
+}
+
+/*******************************************************************************
+* Function Name  : ETH_Start
+* Desciption     : Enables ENET MAC and DMA reception/transmission
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_Start(void)
+{
+  /* Enable transmit state machine of the MAC for transmission on the MII */
+  ETH_MACTransmissionCmd(ENABLE);
+  /* Flush Transmit FIFO */
+  ETH_FlushTransmitFIFO();
+  /* Enable receive state machine of the MAC for reception from the MII */
+  ETH_MACReceptionCmd(ENABLE);
+
+#ifdef _ETH_DMA
+  /* Start DMA transmission */
+  ETH_DMATransmissionCmd(ENABLE);
+  /* Start DMA reception */
+  ETH_DMAReceptionCmd(ENABLE);
+#endif /* _ETH_DMA */
+}
+
+#ifdef _ETH_DMA
+/*******************************************************************************
+* Function Name  : ETH_HandleTxPkt
+* Desciption     : Transmits a packet, from application buffer, pointed by ppkt.
+* Input          : - ppkt: pointer to application packet Buffer.
+*                  - FrameLength: Tx Packet size.
+* Output         : None
+* Return         : ETH_ERROR: in case of Tx desc owned by DMA
+*                  ETH_SUCCESS: for correct transmission
+*******************************************************************************/
+u32 ETH_HandleTxPkt(u32 addr, u16 FrameLength)
+{
+
+  // Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset)
+  if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (u32)RESET)
+  {
+    // Return ERROR: OWN bit set
+    return ETH_ERROR;
+  }
+
+  //Set the DMA buffer address to send to the Packet we received from stack
+  DMATxDescToSet->Buffer1Addr = (u32)addr;
+
+  // Setting the Frame Length: bits[12:0]
+  DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1);
+
+  // Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor)
+  DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
+
+  // Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA
+  DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
+
+  // When Tx Buffer unavailable flag is set: clear it and resume transmission
+  if ((ETH_DMA->DMASR & ETH_DMASR_TBUS) != (u32)RESET)
+  {
+    // Clear TBUS ETHERNET DMA flag
+    ETH_DMA->DMASR = ETH_DMASR_TBUS;
+    // Resume DMA transmission
+    ETH_DMA->DMATPDR = 0;
+  }
+
+  // Update the ETHERNET DMA global Tx descriptor with next Tx decriptor
+  // Chained Mode
+  if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (u32)RESET)
+  {
+    // Selects the next DMA Tx descriptor list for next buffer to send
+    DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr);
+  }
+  else // Ring Mode
+  {
+    if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (u32)RESET)
+    {
+      // Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used
+      DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMATDLAR);
+    }
+    else
+    {
+      // Selects the next DMA Tx descriptor list for next buffer to send
+      DMATxDescToSet = (ETH_DMADESCTypeDef*) ((u32)DMATxDescToSet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));
+    }
+  }
+
+
+  // Return SUCCESS
+  return ETH_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_HandleRxPkt
+* Desciption     : Receives a packet and copies it to memory pointed by ppkt.
+* Input          : None
+* Output         : ppkt: pointer on application receive buffer.
+* Return         : ETH_ERROR: if there is error in reception
+*                  Received packet size: if packet reception is correct
+*******************************************************************************/
+u32 ETH_HandleRxPkt(u32 addr)
+{
+  // Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset)
+  if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (u32)RESET)
+  {
+    // Return error: OWN bit set
+    return ETH_ERROR;
+  }
+
+  //Set the buffer address to rcv frame for the same descriptor (reserved packet)
+  DMARxDescToGet->Buffer1Addr = addr;
+
+  if(addr) {
+   // Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA
+   DMARxDescToGet->Status = ETH_DMARxDesc_OWN;
+  }
+
+  // Update the ETHERNET DMA global Rx descriptor with next Rx decriptor
+  // Chained Mode
+  if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (u32)RESET)
+  {
+    // Selects the next DMA Rx descriptor list for next buffer to read
+    DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
+  }
+  else // Ring Mode
+  {
+    if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (u32)RESET)
+    {
+      // Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMARDLAR);
+    }
+    else
+    {
+      // Selects the next DMA Rx descriptor list for next buffer to read
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) ((u32)DMARxDescToGet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));
+    }
+  }
+
+  return(1);
+}
+
+
+/*******************************************************************************
+* Function Name  : ETH_GetRxPktSize
+* Desciption     : Get the size of received the received packet.
+* Input          : None
+* Output         : None
+* Return         : Rx packet size
+*******************************************************************************/
+u32 ETH_GetRxPktSize(void)
+{
+  u32 FrameLength = 0;
+
+  //Test DMARxDescToGet is not NULL
+  if(DMARxDescToGet)
+  {
+    /* Get the size of the packet: including 4 bytes of the CRC */
+    FrameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet);
+
+  }
+
+ /* Return Frame Length */
+ return FrameLength;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_DropRxPkt
+* Desciption     : Drop a Received packet (too small packet, etc...)
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_DropRxPkt(void)
+{
+
+  // Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA
+  DMARxDescToGet->Status = ETH_DMARxDesc_OWN;
+
+
+  // Chained Mode
+  if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (u32)RESET)
+  {
+    // Selects the next DMA Rx descriptor list for next buffer read
+    DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
+  }
+  else // Ring Mode
+  {
+    if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (u32)RESET)
+    {
+      // Selects the next DMA Rx descriptor list for next buffer read: this will
+      //   be the first Rx descriptor in this case
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMARDLAR);
+    }
+    else
+    {
+      // Selects the next DMA Rx descriptor list for next buffer read
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) ((u32)DMARxDescToGet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));
+    }
+  }
+}
+
+#endif /* _ETH_DMA */
+/*---------------------------------  PHY  ------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : ETH_ReadPHYRegister
+* Desciption     : Read a PHY register
+* Input          : - PHYAddress: PHY device address, is the index of one of supported
+*                    32 PHY devices.
+*                    This parameter can be one of the following values: 0,..,31
+*                  - PHYReg: PHY register address, is the index of one of the 32
+*                    PHY register.
+*                    This parameter can be one of the following values:
+*                       - PHY_BCR    : Tranceiver Basic Control Register
+*                       - PHY_BSR    : Tranceiver Basic Status Register
+*                       - PHY_SR     : Tranceiver Status Register
+*                       - More PHY register could be read depending on the used PHY
+* Output         : None
+* Return         : ETH_ERROR: in case of timeout
+*                  Data read from the selected PHY register: for correct read
+*******************************************************************************/
+u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg)
+{
+  u32 tmpreg = 0;
+  u32 timeout = 0;
+
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
+  eth_assert_param(IS_ETH_PHY_REG(PHYReg));
+
+  /* Get the ETHERNET MACMIIAR value */
+  tmpreg = ETH_MAC->MACMIIAR;
+  /* Keep only the CSR Clock Range CR[2:0] bits value */
+  tmpreg &= ~MACMIIAR_CR_Mask;
+
+  /* Prepare the MII address register value */
+  tmpreg |=(((u32)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
+  tmpreg |=(((u32)PHYReg<<6) & ETH_MACMIIAR_MR);      /* Set the PHY register address */
+  tmpreg &= ~ETH_MACMIIAR_MW;                         /* Set the read mode */
+  tmpreg |= ETH_MACMIIAR_MB;						  /* Set the MII Busy bit */
+
+  /* Write the result value into the MII Address register */
+  ETH_MAC->MACMIIAR = tmpreg;
+
+  /* Check for the Busy flag */
+  do
+  {
+    timeout++;
+    tmpreg = ETH_MAC->MACMIIAR;
+  } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (u32)PHY_READ_TO));
+
+  /* Return ERROR in case of timeout */
+  if(timeout == PHY_READ_TO)
+  {
+    return (u16)ETH_ERROR;
+  }
+
+  /* Return data register value */
+  return (u16)(ETH_MAC->MACMIIDR);
+}
+
+/*******************************************************************************
+* Function Name  : ETH_WritePHYRegister
+* Desciption     : Write to a PHY register
+* Input          : - PHYAddress: PHY device address, is the index of one of supported
+*                    32 PHY devices.
+*                    This parameter can be one of the following values: 0,..,31
+*                  - PHYReg: PHY register address, is the index of one of the 32
+*                    PHY register.
+*                    This parameter can be one of the following values:
+*                       - PHY_BCR    : Tranceiver Control Register
+*                       - More PHY register could be written depending on the used PHY
+*                  - PHYValue: the value to write
+* Output         : None
+* Return         : ETH_ERROR: in case of timeout
+*                  ETH_SUCCESS: for correct read
+*******************************************************************************/
+u32 ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue)
+{
+  u32 tmpreg = 0;
+  u32 timeout = 0;
+
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
+  eth_assert_param(IS_ETH_PHY_REG(PHYReg));
+
+  /* Get the ETHERNET MACMIIAR value */
+  tmpreg = ETH_MAC->MACMIIAR;
+  /* Keep only the CSR Clock Range CR[2:0] bits value */
+  tmpreg &= ~MACMIIAR_CR_Mask;
+
+  /* Prepare the MII register address value */
+  tmpreg |=(((u32)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
+  tmpreg |=(((u32)PHYReg<<6) & ETH_MACMIIAR_MR);      /* Set the PHY register address */
+  tmpreg |= ETH_MACMIIAR_MW;                          /* Set the write mode */
+  tmpreg |= ETH_MACMIIAR_MB;			              /* Set the MII Busy bit */
+
+  /* Give the value to the MII data register */
+  ETH_MAC->MACMIIDR = PHYValue;
+
+  /* Write the result value into the MII Address register */
+  ETH_MAC->MACMIIAR = tmpreg;
+
+  /* Check for the Busy flag */
+  do
+  {
+    timeout++;
+    tmpreg = ETH_MAC->MACMIIAR;
+  } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (u32)PHY_WRITE_TO));
+
+  /* Return ERROR in case of timeout */
+  if(timeout == PHY_WRITE_TO)
+  {
+    return ETH_ERROR;
+  }
+
+  /* Return SUCCESS */
+  return ETH_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_PHYLoopBackCmd
+* Desciption     : Enables or disables the PHY loopBack mode.
+* Input          : - PHYAddress: PHY device address, is the index of one of supported
+*                    32 PHY devices.
+*                    This parameter can be one of the following values:
+*                  - NewState: new state of the PHY loopBack mode.
+*                    This parameter can be: ENABLE or DISABLE.
+*                  Note: Don't be confused with ETH_MACLoopBackCmd function
+*                        which enables internal loopback at MII level
+* Output         : None
+* Return         : None
+*******************************************************************************/
+u32 ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState)
+{
+  u16 tmpreg = 0;
+
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Get the PHY configuration to update it */
+  tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR);
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the PHY loopback mode */
+    tmpreg |= PHY_Loopback;
+  }
+  else
+  {
+    /* Disable the PHY loopback mode: normal mode */
+    tmpreg &= (u16)(~(u16)PHY_Loopback);
+  }
+
+  /* Update the PHY control register with the new configuration */
+  if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (u32)RESET)
+  {
+    return ETH_SUCCESS;
+  }
+  else
+  {
+    /* Return SUCCESS */
+    return ETH_ERROR;
+  }
+}
+
+/*---------------------------------  MAC  ------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : ETH_MACTransmissionCmd
+* Desciption     : Enables or disables the MAC transmission.
+* Input          : - NewState: new state of the MAC transmission.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_MACTransmissionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC transmission */
+    ETH_MAC->MACCR |= ETH_MACCR_TE;
+  }
+  else
+  {
+    /* Disable the MAC transmission */
+    ETH_MAC->MACCR &= ~ETH_MACCR_TE;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_MACReceptionCmd
+* Desciption     : Enables or disables the MAC reception.
+* Input          : - NewState: new state of the MAC reception.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_MACReceptionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC reception */
+    ETH_MAC->MACCR |= ETH_MACCR_RE;
+  }
+  else
+  {
+    /* Disable the MAC reception */
+    ETH_MAC->MACCR &= ~ETH_MACCR_RE;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetFlowControlBusyStatus
+* Desciption     : Checks whether the ETHERNET flow control busy bit is set or not.
+* Input          : None
+* Output         : None
+* Return         : The new state of flow control busy status bit (SET or RESET).
+*******************************************************************************/
+FlagStatus ETH_GetFlowControlBusyStatus(void)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* The Flow Control register should not be written to until this bit is cleared */
+  if ((ETH_MAC->MACFCR & ETH_MACFCR_FCBBPA) != (u32)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_InitiatePauseControlFrame
+* Desciption     : Initiate a Pause Control Frame (Full-duplex only).
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_InitiatePauseControlFrame(void)
+{
+  /* When Set In full duplex MAC initiates pause control frame */
+  ETH_MAC->MACFCR |= ETH_MACFCR_FCBBPA;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_BackPressureActivationCmd
+* Desciption     : Enables or disables the MAC BackPressure operation activation (Half-duplex only).
+* Input          : - NewState: new state of the MAC BackPressure operation activation.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_BackPressureActivationCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Activate the MAC BackPressure operation */
+    /* In Half duplex: during backpressure, when the MAC receives a new frame,
+    the transmitter starts sending a JAM pattern resulting in a collision */
+    ETH_MAC->MACFCR |= ETH_MACFCR_FCBBPA;
+  }
+  else
+  {
+    /* Desactivate the MAC BackPressure operation */
+    ETH_MAC->MACFCR &= ~ETH_MACFCR_FCBBPA;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetMACFlagStatus
+* Desciption     : Checks whether the specified ETHERNET MAC flag is set or not.
+* Input          : - ETH_MAC_FLAG: specifies the flag to check.
+*                    This parameter can be one of the following values:
+*                       - ETH_MAC_FLAG_TST  : Time stamp trigger flag
+*                       - ETH_MAC_FLAG_MMCT : MMC transmit flag
+*                       - ETH_MAC_FLAG_MMCR : MMC receive flag
+*                       - ETH_MAC_FLAG_MMC  : MMC flag
+*                       - ETH_MAC_FLAG_PMT  : PMT flag
+* Output         : None
+* Return         : The new state of ETHERNET MAC flag (SET or RESET).
+*******************************************************************************/
+FlagStatus ETH_GetMACFlagStatus(u32 ETH_MAC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG));
+
+  if ((ETH_MAC->MACSR & ETH_MAC_FLAG) != (u32)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetMACITStatus
+* Desciption     : Checks whether the specified ETHERNET MAC interrupt has occurred or not.
+* Input          : - ETH_MAC_IT: specifies the interrupt source to check.
+*                    This parameter can be one of the following values:
+*                       - ETH_MAC_IT_TST   : Time stamp trigger interrupt
+*                       - ETH_MAC_IT_MMCT : MMC transmit interrupt
+*                       - ETH_MAC_IT_MMCR : MMC receive interrupt
+*                       - ETH_MAC_IT_MMC  : MMC interrupt
+*                       - ETH_MAC_IT_PMT  : PMT interrupt
+* Output         : None
+* Return         : The new state of ETHERNET MAC interrupt (SET or RESET).
+*******************************************************************************/
+ITStatus ETH_GetMACITStatus(u32 ETH_MAC_IT)
+{
+  ITStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT));
+
+  if ((ETH_MAC->MACSR & ETH_MAC_IT) != (u32)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_MACITConfig
+* Desciption     : Enables or disables the specified ETHERNET MAC interrupts.
+* Input          : - ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be
+*                    enabled or disabled.
+*                    This parameter can be any combination of the following values:
+*                       - ETH_MAC_IT_TST : Time stamp trigger interrupt
+*                       - ETH_MAC_IT_PMT : PMT interrupt
+*                  - NewState: new state of the specified ETHERNET MAC interrupts.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_MACITConfig(u32 ETH_MAC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_MAC_IT(ETH_MAC_IT));
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ETHERNET MAC interrupts */
+    ETH_MAC->MACIMR &= (~(u32)ETH_MAC_IT);
+  }
+  else
+  {
+    /* Disable the selected ETHERNET MAC interrupts */
+    ETH_MAC->MACIMR |= ETH_MAC_IT;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_MACAddressConfig
+* Desciption     : Configures the selected MAC address.
+* Input          : - MacAddr: The MAC addres to configure.
+*                    This parameter can be one of the following values:
+*                     - ETH_MAC_Address0 : MAC Address0
+*                     - ETH_MAC_Address1 : MAC Address1
+*                     - ETH_MAC_Address2 : MAC Address2
+*                     - ETH_MAC_Address3 : MAC Address3
+*                  - Addr: Pointer on MAC address buffer data (6 bytes).
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_MACAddressConfig(u32 MacAddr, u8 *Addr)
+{
+  u32 tmpreg;
+
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
+
+  /* Calculate the selectecd MAC address high register */
+  tmpreg = ((u32)Addr[5] << 8) | (u32)Addr[4];
+
+  /* Load the selectecd MAC address high register */
+  (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) = tmpreg;
+
+  /* Calculate the selectecd MAC address low register */
+  tmpreg = ((u32)Addr[3] << 24) | ((u32)Addr[2] << 16) | ((u32)Addr[1] << 8) | Addr[0];
+
+  /* Load the selectecd MAC address low register */
+  (*(vu32 *) (ETH_MAC_AddrLowBase + MacAddr)) = tmpreg;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetMACAddress
+* Desciption     : Get the selected MAC address.
+* Input          : - MacAddr: The MAC addres to return.
+*                    This parameter can be one of the following values:
+*                     - ETH_MAC_Address0 : MAC Address0
+*                     - ETH_MAC_Address1 : MAC Address1
+*                     - ETH_MAC_Address2 : MAC Address2
+*                     - ETH_MAC_Address3 : MAC Address3
+*                  - Addr: Pointer on MAC address buffer data (6 bytes).
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_GetMACAddress(u32 MacAddr, u8 *Addr)
+{
+  u32 tmpreg;
+
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
+
+  /* Get the selectecd MAC address high register */
+  tmpreg =(*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr));
+
+  /* Calculate the selectecd MAC address buffer */
+  Addr[5] = ((tmpreg >> 8) & (u8)0xFF);
+  Addr[4] = (tmpreg & (u8)0xFF);
+
+  /* Load the selectecd MAC address low register */
+  tmpreg =(*(vu32 *) (ETH_MAC_AddrLowBase + MacAddr));
+
+  /* Calculate the selectecd MAC address buffer */
+  Addr[3] = ((tmpreg >> 24) & (u8)0xFF);
+  Addr[2] = ((tmpreg >> 16) & (u8)0xFF);
+  Addr[1] = ((tmpreg >> 8 ) & (u8)0xFF);
+  Addr[0] = (tmpreg & (u8)0xFF);
+}
+
+/*******************************************************************************
+* Function Name  : ETH_MACAddressPerfectFilterCmd
+* Desciption     : Enables or disables the Address filter module uses the specified
+*                  ETHERNET MAC address for perfect filtering
+* Input          : - MacAddr: specifies the ETHERNET MAC address to be used for prfect filtering.
+*                    This parameter can be one of the following values:
+*                     - ETH_MAC_Address1 : MAC Address1
+*                     - ETH_MAC_Address2 : MAC Address2
+*                     - ETH_MAC_Address3 : MAC Address3
+*                  - NewState: new state of the specified ETHERNET MAC address use.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_MACAddressPerfectFilterCmd(u32 MacAddr, FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ETHERNET MAC address for perfect filtering */
+    (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_AE;
+  }
+  else
+  {
+    /* Disable the selected ETHERNET MAC address for perfect filtering */
+    (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(u32)ETH_MACA1HR_AE);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_MACAddressFilterConfig
+* Desciption     : Set the filter type for the specified ETHERNET MAC address
+* Input          : - MacAddr: specifies the ETHERNET MAC address
+*                    This parameter can be one of the following values:
+*                     - ETH_MAC_Address1 : MAC Address1
+*                     - ETH_MAC_Address2 : MAC Address2
+*                     - ETH_MAC_Address3 : MAC Address3
+*                  - Filter: specifies the used frame received field for comparaison
+*                    This parameter can be one of the following values:
+*                     - ETH_MAC_AddressFilter_SA : MAC Address is used to compare
+*                       with the SA fields of the received frame.
+*                     - ETH_MAC_AddressFilter_DA : MAC Address is used to compare
+*                       with the DA fields of the received frame.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_MACAddressFilterConfig(u32 MacAddr, u32 Filter)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
+  eth_assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter));
+
+  if (Filter != ETH_MAC_AddressFilter_DA)
+  {
+    /* The selected ETHERNET MAC address is used to compare with the SA fields of the
+       received frame. */
+    (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_SA;
+  }
+  else
+  {
+    /* The selected ETHERNET MAC address is used to compare with the DA fields of the
+       received frame. */
+    (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(u32)ETH_MACA1HR_SA);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_MACAddressMaskBytesFilterConfig
+* Desciption     : Set the filter type for the specified ETHERNET MAC address
+* Input          : - MacAddr: specifies the ETHERNET MAC address
+*                    This parameter can be one of the following values:
+*                     - ETH_MAC_Address1 : MAC Address1
+*                     - ETH_MAC_Address2 : MAC Address2
+*                     - ETH_MAC_Address3 : MAC Address3
+*                  - MaskByte: specifies the used address bytes for comparaison
+*                    This parameter can be any combination of the following values:
+*                     - ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8].
+*                     - ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0].
+*                     - ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24].
+*                     - ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16].
+*                     - ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8].
+*                     - ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0].
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_MACAddressMaskBytesFilterConfig(u32 MacAddr, u32 MaskByte)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
+  eth_assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte));
+
+  /* Clear MBC bits in the selected MAC address  high register */
+  (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(u32)ETH_MACA1HR_MBC);
+
+  /* Set the selected Filetr mask bytes */
+  (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) |= MaskByte;
+}
+
+/*------------------------  DMA Tx/Rx Desciptors ----------------------------*/
+#ifdef _ETH_DMA
+/*******************************************************************************
+* Function Name  : ETH_DMATxDescChainInit
+* Desciption     : Initializes the DMA Tx descriptors in chain mode.
+* Input          : - DMATxDescTab: Pointer on the first Tx desc list
+*                  - TxBuff: Pointer on the first TxBuffer list
+*                  - TxBuffCount: Number of the used Tx desc in the list
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8* TxBuff, u32 TxBuffCount)
+{
+  u32 i = 0;
+  ETH_DMADESCTypeDef *DMATxDesc;
+
+  /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
+  DMATxDescToSet = DMATxDescTab;
+
+  /* Fill each DMATxDesc descriptor with the right values */
+  for(i=0; i < TxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Tx Desc list */
+    DMATxDesc = DMATxDescTab + i;
+
+    /* Set Second Address Chained bit */
+    DMATxDesc->Status = ETH_DMATxDesc_TCH;
+
+    /* Set Buffer1 address pointer */
+    DMATxDesc->Buffer1Addr = (u32)*((u32*)TxBuff + i);
+
+    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
+    if(i < (TxBuffCount-1))
+    {
+      /* Set next descriptor address register with next descriptor base address */
+      DMATxDesc->Buffer2NextDescAddr = (u32)(DMATxDescTab+i+1);
+    }
+    else
+    {
+      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
+      DMATxDesc->Buffer2NextDescAddr = (u32) DMATxDescTab;
+    }
+  }
+
+  /* Set Transmit Desciptor List Address Register */
+  ETH_DMA->DMATDLAR = (u32) DMATxDescTab;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_DMATxDescRingInit
+* Desciption     : Initializes the DMA Tx descriptors in ring mode.
+* Input          : - DMATxDescTab: Pointer on the first Tx desc list
+*                  - TxBuff1: Pointer on the first TxBuffer1 list
+*                  - TxBuff2: Pointer on the first TxBuffer2 list
+*                  - TxBuffCount: Number of the used Tx desc in the list
+*                Note: see decriptor skip length defined in ETH_DMA_InitStruct
+                       for the number of Words to skip between two unchained descriptors.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, u32 TxBuffCount)
+{
+  u32 i = 0;
+  ETH_DMADESCTypeDef *DMATxDesc;
+
+  /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
+  DMATxDescToSet = DMATxDescTab;
+
+  /* Fill each DMATxDesc descriptor with the right values */
+  for(i=0; i < TxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Tx Desc list */
+    DMATxDesc = DMATxDescTab + i;
+
+    /* Set Buffer1 address pointer */
+    DMATxDesc->Buffer1Addr = (u32)(&TxBuff1[i*ETH_MAX_PACKET_SIZE]);
+
+    /* Set Buffer2 address pointer */
+    DMATxDesc->Buffer2NextDescAddr = (u32)(&TxBuff2[i*ETH_MAX_PACKET_SIZE]);
+
+    /* Set Transmit End of Ring bit for last descriptor: The DMA returns to the base
+       address of the list, creating a Desciptor Ring */
+    if(i == (TxBuffCount-1))
+    {
+      /* Set Transmit End of Ring bit */
+      DMATxDesc->Status = ETH_DMATxDesc_TER;
+    }
+  }
+
+  /* Set Transmit Desciptor List Address Register */
+  ETH_DMA->DMATDLAR =  (u32) DMATxDescTab;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetDMATxDescFlagStatus
+* Desciption     : Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
+* Input          : - DMATxDesc: pointer on a DMA Tx descriptor
+*                  - ETH_DMATxDescFlag: specifies the flag to check.
+*                    This parameter can be one of the following values:
+*                       - ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine
+*                       - ETH_DMATxDesc_IC  : Interrupt on completetion
+*                       - ETH_DMATxDesc_LS  : Last Segment
+*                       - ETH_DMATxDesc_FS  : First Segment
+*                       - ETH_DMATxDesc_DC  : Disable CRC
+*                       - ETH_DMATxDesc_DP  : Disable Pad
+*                       - ETH_DMATxDesc_TTSE: Transmit Time Stamp	Enable
+*                       - ETH_DMATxDesc_TER : Transmit End of Ring
+*                       - ETH_DMATxDesc_TCH : Second Address Chained
+*                       - ETH_DMATxDesc_TTSS: Tx Time Stamp Status
+*                       - ETH_DMATxDesc_IHE : IP Header Error
+*                       - ETH_DMATxDesc_ES  : Error summary
+*                       - ETH_DMATxDesc_JT  : Jabber Timeout
+*                       - ETH_DMATxDesc_FF  : Frame Flushed: DMA/MTL flushed the frame due to SW flush
+*                       - ETH_DMATxDesc_PCE : Payload Checksum Error
+*                       - ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during tramsmission
+*                       - ETH_DMATxDesc_NC  : No Carrier: no carrier signal from the tranceiver
+*                       - ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision
+*                       - ETH_DMATxDesc_EC  : Excessive Collision: transmission aborted after 16 collisions
+*                       - ETH_DMATxDesc_VF  : VLAN Frame
+*                       - ETH_DMATxDesc_CC  : Collision Count
+*                       - ETH_DMATxDesc_ED  : Excessive Deferral
+*                       - ETH_DMATxDesc_UF  : Underflow Error: late data arrival from the memory
+*                       - ETH_DMATxDesc_DB  : Deferred Bit
+* Output         : None
+* Return         : The new state of ETH_DMATxDescFlag (SET or RESET).
+*******************************************************************************/
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, u32 ETH_DMATxDescFlag)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag));
+
+  if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (u32)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetDMATxDescCollisionCount
+* Desciption     : Returns the specified ETHERNET DMA Tx Desc collision count.
+* Input          : - DMATxDesc: pointer on a DMA Tx descriptor
+* Output         : None
+* Return         : The Transmit descriptor collision counter value.
+*******************************************************************************/
+u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc)
+{
+  /* Return the Receive descriptor frame length */
+  return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATxDesc_CollisionCountShift);
+}
+
+/*******************************************************************************
+* Function Name  : ETH_SetDMATxDescOwnBit
+* Desciption     : Set the specified DMA Tx Desc Own bit.
+* Input          : - DMATxDesc: Pointer on a Tx desc
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc)
+{
+  /* Set the DMA Tx Desc Own bit */
+  DMATxDesc->Status |= ETH_DMATxDesc_OWN;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_DMATxDescTransmitITConfig
+* Desciption     : Enables or disables the specified DMA Tx Desc Transmit interrupt.
+* Input          : - DMATxDesc: Pointer on a Tx desc
+*                  - NewState: new state of the DMA Tx Desc transmit interrupt.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA Tx Desc Transmit interrupt */
+    DMATxDesc->Status |= ETH_DMATxDesc_IC;
+  }
+  else
+  {
+    /* Disable the DMA Tx Desc Transmit interrupt */
+    DMATxDesc->Status &=(~(u32)ETH_DMATxDesc_IC);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_DMATxDescFrameSegmentConfig
+* Desciption     : Enables or disables the specified DMA Tx Desc Transmit interrupt.
+* Input          : - DMATxDesc: Pointer on a Tx desc
+*                  - FrameSegment: specifies is the actual Tx desc contain last or first segment.
+*                    This parameter can be one of the following values:
+*                       - ETH_DMATxDesc_LastSegment  : actual Tx desc contain last segment
+*                       - ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_FrameSegment)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment));
+
+  /* Selects the DMA Tx Desc Frame segment */
+  DMATxDesc->Status |= DMATxDesc_FrameSegment;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_DMATxDescChecksumInsertionConfig
+* Desciption     : Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
+* Input          : - DMATxDesc: pointer on a DMA Tx descriptor
+*                  - Checksum: specifies is the DMA Tx desc checksum insertion.
+*                    This parameter can be one of the following values:
+*                       - ETH_DMATxDesc_ChecksumByPass : Checksum bypass
+*                       - ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum
+*                       - ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
+*                       - ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header
+* Output         : None
+* Return         : The Transmit descriptor collision.
+*******************************************************************************/
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_Checksum)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum));
+
+  /* Set the selected DMA Tx desc checksum insertion control */
+  DMATxDesc->Status |= DMATxDesc_Checksum;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_DMATxDescCRCCmd
+* Desciption     : Enables or disables the DMA Tx Desc CRC.
+* Input          : - DMATxDesc: pointer on a DMA Tx descriptor
+*                  - NewState: new state of the specified DMA Tx Desc CRC.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Tx Desc CRC */
+    DMATxDesc->Status &= (~(u32)ETH_DMATxDesc_DC);
+  }
+  else
+  {
+    /* Disable the selected DMA Tx Desc CRC */
+    DMATxDesc->Status |= ETH_DMATxDesc_DC;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_DMATxDescEndOfRingCmd
+* Desciption     : Enables or disables the DMA Tx Desc end of ring.
+* Input          : - DMATxDesc: pointer on a DMA Tx descriptor
+*                  - NewState: new state of the specified DMA Tx Desc end of ring.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : NoneH
+* Return         : None
+*******************************************************************************/
+void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Tx Desc end of ring */
+    DMATxDesc->Status |= ETH_DMATxDesc_TER;
+  }
+  else
+  {
+    /* Disable the selected DMA Tx Desc end of ring */
+    DMATxDesc->Status &= (~(u32)ETH_DMATxDesc_TER);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_DMATxDescSecondAddressChainedCmd
+* Desciption     : Enables or disables the DMA Tx Desc second address chained.
+* Input          : - DMATxDesc: pointer on a DMA Tx descriptor
+*                  - NewState: new state of the specified DMA Tx Desc second address chained.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Tx Desc second address chained */
+    DMATxDesc->Status |= ETH_DMATxDesc_TCH;
+  }
+  else
+  {
+    /* Disable the selected DMA Tx Desc second address chained */
+    DMATxDesc->Status &=(~(u32)ETH_DMATxDesc_TCH);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_DMATxDescShortFramePaddingCmd
+* Desciption     : Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes.
+* Input          : - DMATxDesc: pointer on a DMA Tx descriptor
+*                  - NewState: new state of the specified DMA Tx Desc padding for
+*                    frame shorter than 64 bytes.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */
+    DMATxDesc->Status &= (~(u32)ETH_DMATxDesc_DP);
+  }
+  else
+  {
+    /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/
+    DMATxDesc->Status |= ETH_DMATxDesc_DP;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_DMATxDescTimeStampCmd
+* Desciption     : Enables or disables the DMA Tx Desc time stamp.
+* Input          : - DMATxDesc: pointer on a DMA Tx descriptor
+*                  - NewState: new state of the specified DMA Tx Desc time stamp.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Tx Desc time stamp */
+    DMATxDesc->Status |= ETH_DMATxDesc_TTSE;
+  }
+  else
+  {
+    /* Disable the selected DMA Tx Desc time stamp */
+    DMATxDesc->Status &=(~(u32)ETH_DMATxDesc_TTSE);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_DMATxDescBufferSizeConfig
+* Desciption     : Configures the specified DMA Tx Desc buffer1 and buffer2 sizes.
+* Input          : - DMATxDesc: Pointer on a Tx desc
+*                  - BufferSize1: specifies the Tx desc buffer1 size.
+*                  - BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used).
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 BufferSize1, u32 BufferSize2)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1));
+  eth_assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2));
+
+  /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */
+  DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATxDesc_BufferSize2Shift));
+}
+
+/*******************************************************************************
+* Function Name  : ETH_DMARxDescChainInit
+* Desciption     : Initializes the DMA Rx descriptors in chain mode.
+* Input          : - DMARxDescTab: Pointer on the first Rx desc list
+*                  - RxBuff: Pointer on the first RxBuffer list
+*                  - RxBuffCount: Number of the used Rx desc in the list
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff, u32 RxBuffCount)
+{
+  u32 i = 0;
+  ETH_DMADESCTypeDef *DMARxDesc;
+
+  /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
+  DMARxDescToGet = DMARxDescTab;
+
+  /* Fill each DMARxDesc descriptor with the right values */
+  for(i=0; i < RxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Rx Desc list */
+    DMARxDesc = DMARxDescTab+i;
+
+    /* Set Own bit of the Rx descriptor Status */
+    DMARxDesc->Status = ETH_DMARxDesc_OWN;
+//    DMARxDesc->Status = 0;
+
+    /* Set Buffer1 size and Second Address Chained bit */
+    DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (u32)ETH_MAX_PACKET_SIZE;
+
+    /* Set Buffer1 address pointer */
+    DMARxDesc->Buffer1Addr = (u32)*((u32*)RxBuff + i);
+
+    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
+    if(i < (RxBuffCount-1))
+    {
+      /* Set next descriptor address register with next descriptor base address */
+      DMARxDesc->Buffer2NextDescAddr = (u32)(DMARxDescTab+i+1);
+    }
+    else
+    {
+      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
+      DMARxDesc->Buffer2NextDescAddr = (u32)(DMARxDescTab);
+    }
+  }
+
+  /* Set Receive Desciptor List Address Register */
+  ETH_DMA->DMARDLAR = (u32) DMARxDescTab;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_DMARxDescRingInit
+* Desciption     : Initializes the DMA Rx descriptors in ring mode.
+* Input          : - DMARxDescTab: Pointer on the first Rx desc list
+*                  - RxBuff1: Pointer on the first RxBuffer1 list
+*                  - RxBuff2: Pointer on the first RxBuffer2 list
+*                  - RxBuffCount: Number of the used Rx desc in the list
+*                Note: see decriptor skip length defined in ETH_DMA_InitStruct
+                       for the number of Words to skip between two unchained descriptors.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff1, u8 *RxBuff2, u32 RxBuffCount)
+{
+  u32 i = 0;
+  ETH_DMADESCTypeDef *DMARxDesc;
+
+  /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
+  DMARxDescToGet = DMARxDescTab;
+
+  /* Fill each DMARxDesc descriptor with the right values */
+  for(i=0; i < RxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Rx Desc list */
+    DMARxDesc = DMARxDescTab+i;
+
+    /* Set Own bit of the Rx descriptor Status */
+    DMARxDesc->Status = ETH_DMARxDesc_OWN;
+
+    /* Set Buffer1 size */
+    DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE;
+
+    /* Set Buffer1 address pointer */
+    DMARxDesc->Buffer1Addr = (u32)(&RxBuff1[i*ETH_MAX_PACKET_SIZE]);
+
+    /* Set Buffer2 address pointer */
+    DMARxDesc->Buffer2NextDescAddr = (u32)(&RxBuff2[i*ETH_MAX_PACKET_SIZE]);
+
+    /* Set Receive End of Ring bit for last descriptor: The DMA returns to the base
+       address of the list, creating a Desciptor Ring */
+    if(i == (RxBuffCount-1))
+    {
+      /* Set Receive End of Ring bit */
+      DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;
+    }
+  }
+
+  /* Set Receive Desciptor List Address Register */
+  ETH_DMA->DMARDLAR = (u32) DMARxDescTab;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetDMARxDescFlagStatus
+* Desciption     : Checks whether the specified ETHERNET Rx Desc flag is set or not.
+* Input          : - DMARxDesc: pointer on a DMA Rx descriptor
+*                  - ETH_DMARxDescFlag: specifies the flag to check.
+*                    This parameter can be one of the following values:
+*                       - ETH_DMARxDesc_OWN:         OWN bit: descriptor is owned by DMA engine
+*                       - ETH_DMARxDesc_AFM:         DA Filter Fail for the rx frame
+*                       - ETH_DMARxDesc_ES:          Error summary
+*                       - ETH_DMARxDesc_DE:          Desciptor error: no more descriptors for receive frame
+*                       - ETH_DMARxDesc_SAF:         SA Filter Fail for the received frame
+*                       - ETH_DMARxDesc_LE:          Frame size not matching with length field
+*                       - ETH_DMARxDesc_OE:          Overflow Error: Frame was damaged due to buffer overflow
+*                       - ETH_DMARxDesc_VLAN:        VLAN Tag: received frame is a VLAN frame
+*                       - ETH_DMARxDesc_FS:          First descriptor of the frame
+*                       - ETH_DMARxDesc_LS:          Last descriptor of the frame
+*                       - ETH_DMARxDesc_IPV4HCE:     IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error
+*                       - ETH_DMARxDesc_RxLongFrame: (Giant Frame)Rx - frame is longer than 1518/1522
+*                       - ETH_DMARxDesc_LC:          Late collision occurred during reception
+*                       - ETH_DMARxDesc_FT:          Frame type - Ethernet, otherwise 802.3
+*                       - ETH_DMARxDesc_RWT:         Receive Watchdog Timeout: watchdog timer expired during reception
+*                       - ETH_DMARxDesc_RE:          Receive error: error reported by MII interface
+*                       - ETH_DMARxDesc_DE:          Dribble bit error: frame contains non int multiple of 8 bits
+*                       - ETH_DMARxDesc_CE:          CRC error
+*                       - ETH_DMARxDesc_MAMPCE:      Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error
+* Output         : None
+* Return         : The new state of ETH_DMARxDescFlag (SET or RESET).
+*******************************************************************************/
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, u32 ETH_DMARxDescFlag)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag));
+
+  if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (u32)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_SetDMARxDescOwnBit
+* Desciption     : Set the specified DMA Rx Desc Own bit.
+* Input          : - DMARxDesc: Pointer on a Rx desc
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc)
+{
+  /* Set the DMA Rx Desc Own bit */
+  DMARxDesc->Status |= ETH_DMARxDesc_OWN;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetDMARxDescFrameLength
+* Desciption     : Returns the specified DMA Rx Desc frame length.
+* Input          : - DMARxDesc: pointer on a DMA Rx descriptor
+* Output         : None
+* Return         : The Rx descriptor received frame length.
+*******************************************************************************/
+u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc)
+{
+  /* Return the Receive descriptor frame length */
+  return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift);
+}
+
+/*******************************************************************************
+* Function Name  : ETH_DMARxDescReceiveITConfig
+* Desciption     : Enables or disables the specified DMA Rx Desc receive interrupt.
+* Input          : - DMARxDesc: Pointer on a Rx desc
+*                  - NewState: new state of the specified DMA Rx Desc interrupt.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA Rx Desc receive interrupt */
+    DMARxDesc->ControlBufferSize &=(~(u32)ETH_DMARxDesc_DIC);
+  }
+  else
+  {
+    /* Disable the DMA Rx Desc receive interrupt */
+    DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_DMARxDescEndOfRingCmd
+* Desciption     : Enables or disables the DMA Rx Desc end of ring.
+* Input          : - DMARxDesc: pointer on a DMA Rx descriptor
+*                  - NewState: new state of the specified DMA Rx Desc end of ring.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Rx Desc end of ring */
+    DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;
+  }
+  else
+  {
+    /* Disable the selected DMA Rx Desc end of ring */
+    DMARxDesc->ControlBufferSize &=(~(u32)ETH_DMARxDesc_RER);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_DMARxDescSecondAddressChainedCmd
+* Desciption     : Enables or disables the DMA Rx Desc second address chained.
+* Input          : - DMARxDesc: pointer on a DMA Rx descriptor
+*                  - NewState: new state of the specified DMA Rx Desc second address chained.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Rx Desc second address chained */
+    DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH;
+  }
+  else
+  {
+    /* Disable the selected DMA Rx Desc second address chained */
+    DMARxDesc->ControlBufferSize &=(~(u32)ETH_DMARxDesc_RCH);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetDMARxDescBufferSize
+* Desciption     : Returns the specified ETHERNET DMA Rx Desc buffer size.
+* Input          : - DMARxDesc: pointer on a DMA Rx descriptor
+*                  - DMARxDesc_Buffer: specifies the DMA Rx Desc buffer.
+*                    This parameter can be any one of the following values:
+*                       - ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1
+*                       - ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2
+* Output         : None
+* Return         : The Receive descriptor frame length.
+*******************************************************************************/
+u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, u32 DMARxDesc_Buffer)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer));
+
+  if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1)
+  {
+    /* Return the DMA Rx Desc buffer2 size */
+    return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARxDesc_Buffer2SizeShift);
+  }
+  else
+  {
+    /* Return the DMA Rx Desc buffer1 size */
+    return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1);
+  }
+}
+
+/*---------------------------------  DMA  ------------------------------------*/
+/*******************************************************************************
+* Function Name  : ETH_SoftwareReset
+* Desciption     : Resets all MAC subsystem internal registers and logic.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_SoftwareReset(void)
+{
+  /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
+  /* After reset all the registers holds their respective reset values */
+  ETH_DMA->DMABMR |= ETH_DMABMR_SR;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetSoftwareResetStatus
+* Desciption     : Checks whether the ETHERNET software reset bit is set or not.
+* Input          : None
+* Output         : None
+* Return         : The new state of DMA Bus Mode register SR bit (SET or RESET).
+*******************************************************************************/
+FlagStatus ETH_GetSoftwareResetStatus(void)
+{
+  FlagStatus bitstatus = RESET;
+
+  if((ETH_DMA->DMABMR & ETH_DMABMR_SR) != (u32)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetDMAFlagStatus
+* Desciption     : Checks whether the specified ETHERNET DMA flag is set or not.
+* Input          : - ETH_DMA_IT: specifies the flag to check.
+*                    This parameter can be one of the following values:
+*                       - ETH_DMA_FLAG_TST : Time-stamp trigger flag
+*                       - ETH_DMA_FLAG_PMT : PMT flag
+*                       - ETH_DMA_FLAG_MMC : MMC flag
+*                       - ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access
+*                       - ETH_DMA_FLAG_ReadWriteError    : Error bits 0-write trnsf, 1-read transfr
+*                       - ETH_DMA_FLAG_AccessError       : Error bits 0-Rx DMA, 1-Tx DMA
+*                       - ETH_DMA_FLAG_NIS : Normal interrupt summary flag
+*                       - ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag
+*                       - ETH_DMA_FLAG_ER  : Early receive flag
+*                       - ETH_DMA_FLAG_FBE : Fatal bus error flag
+*                       - ETH_DMA_FLAG_ET  : Early transmit flag
+*                       - ETH_DMA_FLAG_RWT : Receive watchdog timeout flag
+*                       - ETH_DMA_FLAG_RPS : Receive process stopped flag
+*                       - ETH_DMA_FLAG_RBU : Receive buffer unavailable flag
+*                       - ETH_DMA_FLAG_R   : Receive flag
+*                       - ETH_DMA_FLAG_TU  : Underflow flag
+*                       - ETH_DMA_FLAG_RO  : Overflow flag
+*                       - ETH_DMA_FLAG_TJT : Transmit jabber timeout flag
+*                       - ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag
+*                       - ETH_DMA_FLAG_TPS : Transmit process stopped flag
+*                       - ETH_DMA_FLAG_T   : Transmit flag
+* Output         : None
+* Return         : The new state of ETH_DMA_FLAG (SET or RESET).
+*******************************************************************************/
+FlagStatus ETH_GetDMAFlagStatus(u32 ETH_DMA_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG));
+
+  if ((ETH_DMA->DMASR & ETH_DMA_FLAG) != (u32)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_DMAClearFlag
+* Desciption     : Clears the ETHERNET?s DMA pending flag.
+* Input          : - ETH_DMA_FLAG: specifies the flag to clear.
+*                    This parameter can be any combination of the following values:
+*                       - ETH_DMA_FLAG_NIS : Normal interrupt summary flag
+*                       - ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag
+*                       - ETH_DMA_FLAG_ER  : Early receive flag
+*                       - ETH_DMA_FLAG_FBE : Fatal bus error flag
+*                       - ETH_DMA_FLAG_ETI : Early transmit flag
+*                       - ETH_DMA_FLAG_RWT : Receive watchdog timeout flag
+*                       - ETH_DMA_FLAG_RPS : Receive process stopped flag
+*                       - ETH_DMA_FLAG_RBU : Receive buffer unavailable flag
+*                       - ETH_DMA_FLAG_R   : Receive flag
+*                       - ETH_DMA_FLAG_TU  : Transmit Underflow flag
+*                       - ETH_DMA_FLAG_RO  : Receive Overflow flag
+*                       - ETH_DMA_FLAG_TJT : Transmit jabber timeout flag
+*                       - ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag
+*                       - ETH_DMA_FLAG_TPS : Transmit process stopped flag
+*                       - ETH_DMA_FLAG_T   : Transmit flag
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_DMAClearFlag(u32 ETH_DMA_FLAG)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG));
+
+  /* Clear the selected ETHERNET DMA FLAG */
+  ETH_DMA->DMASR = (u32) ETH_DMA_FLAG;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetDMAITStatus
+* Desciption     : Checks whether the specified ETHERNET DMA interrupt has occured or not.
+* Input          : - ETH_DMA_IT: specifies the interrupt source to check.
+*                    This parameter can be one of the following values:
+*                       - ETH_DMA_IT_TST : Time-stamp trigger interrupt
+*                       - ETH_DMA_IT_PMT : PMT interrupt
+*                       - ETH_DMA_IT_MMC : MMC interrupt
+*                       - ETH_DMA_IT_NIS : Normal interrupt summary
+*                       - ETH_DMA_IT_AIS : Abnormal interrupt summary
+*                       - ETH_DMA_IT_ER  : Early receive interrupt
+*                       - ETH_DMA_IT_FBE : Fatal bus error interrupt
+*                       - ETH_DMA_IT_ET  : Early transmit interrupt
+*                       - ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
+*                       - ETH_DMA_IT_RPS : Receive process stopped interrupt
+*                       - ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
+*                       - ETH_DMA_IT_R   : Receive interrupt
+*                       - ETH_DMA_IT_TU  : Underflow interrupt
+*                       - ETH_DMA_IT_RO  : Overflow interrupt
+*                       - ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
+*                       - ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
+*                       - ETH_DMA_IT_TPS : Transmit process stopped interrupt
+*                       - ETH_DMA_IT_T   : Transmit interrupt
+* Output         : None
+* Return         : The new state of ETH_DMA_IT (SET or RESET).
+*******************************************************************************/
+ITStatus ETH_GetDMAITStatus(u32 ETH_DMA_IT)
+{
+  ITStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT));
+
+  if ((ETH_DMA->DMASR & ETH_DMA_IT) != (u32)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_DMAClearITPendingBit
+* Desciption     : Clears the ETHERNET?s DMA IT pending bit.
+* Input          : - ETH_DMA_IT: specifies the interrupt pending bit to clear.
+*                    This parameter can be any combination of the following values:
+*                       - ETH_DMA_IT_NIS : Normal interrupt summary
+*                       - ETH_DMA_IT_AIS : Abnormal interrupt summary
+*                       - ETH_DMA_IT_ER  : Early receive interrupt
+*                       - ETH_DMA_IT_FBE : Fatal bus error interrupt
+*                       - ETH_DMA_IT_ETI : Early transmit interrupt
+*                       - ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
+*                       - ETH_DMA_IT_RPS : Receive process stopped interrupt
+*                       - ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
+*                       - ETH_DMA_IT_R   : Receive interrupt
+*                       - ETH_DMA_IT_TU  : Transmit Underflow interrupt
+*                       - ETH_DMA_IT_RO  : Receive Overflow interrupt
+*                       - ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
+*                       - ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
+*                       - ETH_DMA_IT_TPS : Transmit process stopped interrupt
+*                       - ETH_DMA_IT_T   : Transmit interrupt
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_DMAClearITPendingBit(u32 ETH_DMA_IT)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
+
+  /* Clear the selected ETHERNET DMA IT */
+  ETH_DMA->DMASR = (u32) ETH_DMA_IT;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetDMATransmitProcessState
+* Desciption     : Returns the ETHERNET DMA Transmit Process State.
+* Input          : None
+* Output         : None
+* Return         : The new ETHERNET DMA Transmit Process State:
+*                  This can be one of the following values:
+*                     - ETH_DMA_TransmitProcess_Stopped   : Stopped - Reset or Stop Tx Command issued
+*                     - ETH_DMA_TransmitProcess_Fetching  : Running - fetching the Tx descriptor
+*                     - ETH_DMA_TransmitProcess_Waiting   : Running - waiting for status
+*                     - ETH_DMA_TransmitProcess_Reading   : unning - reading the data from host memory
+*                     - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe
+*                     - ETH_DMA_TransmitProcess_Closing   : Running - closing Rx descriptor
+*******************************************************************************/
+u32 ETH_GetTransmitProcessState(void)
+{
+  return ((u32)(ETH_DMA->DMASR & ETH_DMASR_TS));
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetDMAReceiveProcessState
+* Desciption     : Returns the ETHERNET DMA Receive Process State.
+* Input          : None
+* Output         : None
+* Return         : The new ETHERNET DMA Receive Process State:
+*                  This can be one of the following values:
+*                     - ETH_DMA_ReceiveProcess_Stopped   : Stopped - Reset or Stop Rx Command issued
+*                     - ETH_DMA_ReceiveProcess_Fetching  : Running - fetching the Rx descriptor
+*                     - ETH_DMA_ReceiveProcess_Waiting   : Running - waiting for packet
+*                     - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable
+*                     - ETH_DMA_ReceiveProcess_Closing   : Running - closing descriptor
+*                     - ETH_DMA_ReceiveProcess_Queuing   : Running - queuing the recieve frame into host memory
+*******************************************************************************/
+u32 ETH_GetReceiveProcessState(void)
+{
+  return ((u32)(ETH_DMA->DMASR & ETH_DMASR_RS));
+}
+
+/*******************************************************************************
+* Function Name  : ETH_FlushTransmitFIFO
+* Desciption     : Clears the ETHERNET transmit FIFO.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_FlushTransmitFIFO(void)
+{
+  /* Set the Flush Transmit FIFO bit */
+  ETH_DMA->DMAOMR |= ETH_DMAOMR_FTF;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetFlushTransmitFIFOStatus
+* Desciption     : Checks whether the ETHERNET transmit FIFO bit is cleared or not.
+* Input          : None
+* Output         : None
+* Return         : The new state of ETHERNET flush transmit FIFO bit (SET or RESET).
+*******************************************************************************/
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void)
+{
+  FlagStatus bitstatus = RESET;
+
+  if ((ETH_DMA->DMAOMR & ETH_DMAOMR_FTF) != (u32)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_DMATransmissionCmd
+* Desciption     : Enables or disables the DMA transmission.
+* Input          : - NewState: new state of the DMA transmission.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_DMATransmissionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA transmission */
+    ETH_DMA->DMAOMR |= ETH_DMAOMR_ST;
+  }
+  else
+  {
+    /* Disable the DMA transmission */
+    ETH_DMA->DMAOMR &= ~ETH_DMAOMR_ST;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_DMAReceptionCmd
+* Desciption     : Enables or disables the DMA reception.
+* Input          : - NewState: new state of the DMA reception.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_DMAReceptionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA reception */
+    ETH_DMA->DMAOMR |= ETH_DMAOMR_SR;
+  }
+  else
+  {
+    /* Disable the DMA reception */
+    ETH_DMA->DMAOMR &= ~ETH_DMAOMR_SR;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_DMAITConfig
+* Desciption     : Enables or disables the specified ETHERNET DMA interrupts.
+* Input          : - ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be
+*                    enabled or disabled.
+*                    This parameter can be any combination of the following values:
+*                       - ETH_DMA_IT_NIS : Normal interrupt summary
+*                       - ETH_DMA_IT_AIS : Abnormal interrupt summary
+*                       - ETH_DMA_IT_ER  : Early receive interrupt
+*                       - ETH_DMA_IT_FBE : Fatal bus error interrupt
+*                       - ETH_DMA_IT_ET  : Early transmit interrupt
+*                       - ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
+*                       - ETH_DMA_IT_RPS : Receive process stopped interrupt
+*                       - ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
+*                       - ETH_DMA_IT_R   : Receive interrupt
+*                       - ETH_DMA_IT_TU  : Underflow interrupt
+*                       - ETH_DMA_IT_RO  : Overflow interrupt
+*                       - ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
+*                       - ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
+*                       - ETH_DMA_IT_TPS : Transmit process stopped interrupt
+*                       - ETH_DMA_IT_T   : Transmit interrupt
+*                  - NewState: new state of the specified ETHERNET DMA interrupts.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_DMAITConfig(u32 ETH_DMA_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ETHERNET DMA interrupts */
+    ETH_DMA->DMAIER |= ETH_DMA_IT;
+  }
+  else
+  {
+    /* Disable the selected ETHERNET DMA interrupts */
+    ETH_DMA->DMAIER &=(~(u32)ETH_DMA_IT);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetDMAOverflowStatus
+* Desciption     : Checks whether the specified ETHERNET DMA overflow flag is set or not.
+* Input          : - ETH_DMA_Overflow: specifies the DMA overflow flag to check.
+*                    This parameter can be one of the following values:
+*                       - ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflow Counter
+*                       - ETH_DMA_Overflow_MissedFrameCounter : Overflow for Missed Frame Counter
+* Output         : None
+* Return         : The new state of ETHERNET DMA overflow Flag (SET or RESET).
+*******************************************************************************/
+FlagStatus ETH_GetDMAOverflowStatus(u32 ETH_DMA_Overflow)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow));
+
+  if ((ETH_DMA->DMAMFBOCR & ETH_DMA_Overflow) != (u32)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetRxOverflowMissedFrameCounter
+* Desciption     : Get the ETHERNET DMA Rx Overflow Missed Frame Counter value.
+* Input          : None
+* Output         : None
+* Return         : The value of Rx overflow Missed Frame Counter.
+*******************************************************************************/
+u32 ETH_GetRxOverflowMissedFrameCounter(void)
+{
+  return ((u32)((ETH_DMA->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RxOverflowMissedFramesCounterShift));
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetBufferUnavailableMissedFrameCounter
+* Desciption     : Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value.
+* Input          : None
+* Output         : None
+* Return         : The value of Buffer unavailable Missed Frame Counter.
+*******************************************************************************/
+u32 ETH_GetBufferUnavailableMissedFrameCounter(void)
+{
+  return ((u32)(ETH_DMA->DMAMFBOCR) & ETH_DMAMFBOCR_MFC);
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetCurrentTxDescStartAddress
+* Desciption     : Get the ETHERNET DMA DMACHTDR register value.
+* Input          : None
+* Output         : None
+* Return         : The value of the current Tx desc start address.
+*******************************************************************************/
+u32 ETH_GetCurrentTxDescStartAddress(void)
+{
+  return ((u32)(ETH_DMA->DMACHTDR));
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetCurrentRxDescStartAddress
+* Desciption     : Get the ETHERNET DMA DMACHRDR register value.
+* Input          : None
+* Output         : None
+* Return         : The value of the current Rx desc start address.
+*******************************************************************************/
+u32 ETH_GetCurrentRxDescStartAddress(void)
+{
+  return ((u32)(ETH_DMA->DMACHRDR));
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetCurrentTxBufferAddress
+* Desciption     : Get the ETHERNET DMA DMACHTBAR register value.
+* Input          : None
+* Output         : None
+* Return         : The value of the current Tx desc buffer address.
+*******************************************************************************/
+u32 ETH_GetCurrentTxBufferAddress(void)
+{
+  return ((u32)(ETH_DMA->DMACHTBAR));
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetCurrentRxBufferAddress
+* Desciption     : Get the ETHERNET DMA DMACHRBAR register value.
+* Input          : None
+* Output         : None
+* Return         : The value of the current Rx desc buffer address.
+*******************************************************************************/
+u32 ETH_GetCurrentRxBufferAddress(void)
+{
+  return ((u32)(ETH_DMA->DMACHRBAR));
+}
+
+/*******************************************************************************
+* Function Name  : ETH_ResumeDMATransmission
+* Desciption     : Resumes the DMA Transmission by writing to the DmaTxPollDemand
+*                  register: (the data written could be anything). This forces
+*                  the DMA to resume transmission.
+* Input          : None
+* Output         : None
+* Return         : None.
+*******************************************************************************/
+void ETH_ResumeDMATransmission(void)
+{
+  ETH_DMA->DMATPDR = 0;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_ResumeDMAReception
+* Desciption     : Resumes the DMA Transmission by writing to the DmaRxPollDemand
+*                  register: (the data written could be anything). This forces
+*                  the DMA to resume reception.
+* Input          : None
+* Output         : None
+* Return         : None.
+*******************************************************************************/
+void ETH_ResumeDMAReception(void)
+{
+  ETH_DMA->DMARPDR = 0;
+}
+
+#endif /* _ETH_DMA */
+/*---------------------------------  PMT  ------------------------------------*/
+/*******************************************************************************
+* Function Name  : ETH_ResetWakeUpFrameFilterRegisterPointer
+* Desciption     : Reset Wakeup frame filter register pointer.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void)
+{
+  /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */
+  ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_SetWakeUpFrameFilterRegister
+* Desciption     : Populates the remote wakeup frame registers.
+* Input          : - Buffer: Pointer on remote WakeUp Frame Filter Register buffer
+*                    data (8 words).
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_SetWakeUpFrameFilterRegister(u32 *Buffer)
+{
+  u32 i = 0;
+
+  /* Fill Remote Wake-up Frame Filter register with Buffer data */
+  for(i =0; iMACRWUFFR = Buffer[i];
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GlobalUnicastWakeUpCmd
+* Desciption     : Enables or disables any unicast packet filtered by the MAC
+*                 (DAF) address recognition to be a wake-up frame.
+* Input          : - NewState: new state of the MAC Global Unicast Wake-Up.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC Global Unicast Wake-Up */
+    ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_GU;
+  }
+  else
+  {
+    /* Disable the MAC Global Unicast Wake-Up */
+    ETH_MAC->MACPMTCSR &= ~ETH_MACPMTCSR_GU;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetPMTFlagStatus
+* Desciption     : Checks whether the specified ETHERNET PMT flag is set or not.
+* Input          : - ETH_PMT_FLAG: specifies the flag to check.
+*                    This parameter can be one of the following values:
+*                       - ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset
+*                       - ETH_PMT_FLAG_WUFR    : Wake-Up Frame Received
+*                       - ETH_PMT_FLAG_MPR     : Magic Packet Received
+* Output         : None
+* Return         : The new state of ETHERNET PMT Flag (SET or RESET).
+*******************************************************************************/
+FlagStatus ETH_GetPMTFlagStatus(u32 ETH_PMT_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG));
+
+  if ((ETH_MAC->MACPMTCSR & ETH_PMT_FLAG) != (u32)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_WakeUpFrameDetectionCmd
+* Desciption     : Enables or disables the MAC Wake-Up Frame Detection.
+* Input          : - NewState: new state of the MAC Wake-Up Frame Detection.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC Wake-Up Frame Detection */
+    ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_WFE;
+  }
+  else
+  {
+    /* Disable the MAC Wake-Up Frame Detection */
+    ETH_MAC->MACPMTCSR &= ~ETH_MACPMTCSR_WFE;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_MagicPacketDetectionCmd
+* Desciption     : Enables or disables the MAC Magic Packet Detection.
+* Input          : - NewState: new state of the MAC Magic Packet Detection.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_MagicPacketDetectionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC Magic Packet Detection */
+    ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_MPE;
+  }
+  else
+  {
+    /* Disable the MAC Magic Packet Detection */
+    ETH_MAC->MACPMTCSR &= ~ETH_MACPMTCSR_MPE;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_PowerDownCmd
+* Desciption     : Enables or disables the MAC Power Down.
+* Input          : - NewState: new state of the MAC Power Down.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_PowerDownCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC Power Down */
+    /* This puts the MAC in power down mode */
+    ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_PD;
+  }
+  else
+  {
+    /* Disable the MAC Power Down */
+    ETH_MAC->MACPMTCSR &= ~ETH_MACPMTCSR_PD;
+  }
+}
+
+/*---------------------------------  MMC  ------------------------------------*/
+#ifdef _ETH_MMC
+
+/*******************************************************************************
+* Function Name  : ETH_MMCCounterFreezeCmd
+* Desciption     : Enables or disables the MMC Counter Freeze.
+* Input          : - NewState: new state of the MMC Counter Freeze.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_MMCCounterFreezeCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the MMC Counter Freeze */
+    ETH_MMC->MMCCR |= ETH_MMCCR_MCF;
+  }
+  else
+  {
+    /* Disable the MMC Counter Freeze */
+    ETH_MMC->MMCCR &= ~ETH_MMCCR_MCF;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_MMCResetOnReadCmd
+* Desciption     : Enables or disables the MMC Reset On Read.
+* Input          : - NewState: new state of the MMC Reset On Read.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_MMCResetOnReadCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the MMC Counter reset on read */
+    ETH_MMC->MMCCR |= ETH_MMCCR_ROR;
+  }
+  else
+  {
+    /* Disable the MMC Counter reset on read */
+    ETH_MMC->MMCCR &= ~ETH_MMCCR_ROR;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_MMCCounterRolloverCmd
+* Desciption     : Enables or disables the MMC Counter Stop Rollover.
+* Input          : - NewState: new state of the MMC Counter Stop Rollover.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_MMCCounterRolloverCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Disable the MMC Counter Stop Rollover  */
+    ETH_MMC->MMCCR &= ~ETH_MMCCR_CSR;
+  }
+  else
+  {
+    /* Enable the MMC Counter Stop Rollover */
+    ETH_MMC->MMCCR |= ETH_MMCCR_CSR;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_MMCCountersReset
+* Desciption     : Resets the MMC Counters.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_MMCCountersReset(void)
+{
+  /* Resets the MMC Counters */
+  ETH_MMC->MMCCR |= ETH_MMCCR_CR;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_MMCITConfig
+* Desciption     : Enables or disables the specified ETHERNET MMC interrupts.
+* Input          : - ETH_MMC_IT: specifies the ETHERNET MMC interrupt
+*                    sources to be enabled or disabled.
+*                    This parameter can be any combination of Tx interrupt or
+*                    any combination of Rx interrupt (but not both)of the following values:
+*                       - ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value
+*                       - ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
+*                       - ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
+*                       - ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value
+*                       - ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value
+*                       - ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value
+*                  - NewState: new state of the specified ETHERNET MMC interrupts.
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_MMCITConfig(u32 ETH_MMC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_MMC_IT(ETH_MMC_IT));
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if ((ETH_MMC_IT & (u32)0x10000000) != (u32)RESET)
+  {
+    /* Remove egister mak from IT */
+    ETH_MMC_IT &= 0xEFFFFFFF;
+
+    /* ETHERNET MMC Rx interrupts selected */
+    if (NewState != DISABLE)
+    {
+      /* Enable the selected ETHERNET MMC interrupts */
+      ETH_MMC->MMCRIMR &=(~(u32)ETH_MMC_IT);
+    }
+    else
+    {
+      /* Disable the selected ETHERNET MMC interrupts */
+      ETH_MMC->MMCRIMR |= ETH_MMC_IT;
+    }
+  }
+  else
+  {
+    /* ETHERNET MMC Tx interrupts selected */
+    if (NewState != DISABLE)
+    {
+      /* Enable the selected ETHERNET MMC interrupts */
+      ETH_MMC->MMCTIMR &=(~(u32)ETH_MMC_IT);
+    }
+    else
+    {
+      /* Disable the selected ETHERNET MMC interrupts */
+      ETH_MMC->MMCTIMR |= ETH_MMC_IT;
+    }
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetMMCITStatus
+* Desciption     : Checks whether the specified ETHERNET MMC IT is set or not.
+* Input          : - ETH_MMC_IT: specifies the ETHERNET MMC interrupt.
+*                    This parameter can be one of the following values:
+*                       - ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value
+*                       - ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value
+*                       - ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value
+*                       - ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value
+*                       - ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value
+*                       - ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value
+* Output         : None
+* Return         : The value of ETHERNET MMC IT (SET or RESET).
+*******************************************************************************/
+ITStatus ETH_GetMMCITStatus(u32 ETH_MMC_IT)
+{
+  ITStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT));
+
+  if ((ETH_MMC_IT & (u32)0x10000000) != (u32)RESET)
+  {
+    /* ETHERNET MMC Rx interrupts selected */
+    /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */
+    if ((((ETH_MMC->MMCRIR & ETH_MMC_IT) != (u32)RESET)) && ((ETH_MMC->MMCRIMR & ETH_MMC_IT) != (u32)RESET))
+    {
+      bitstatus = SET;
+    }
+    else
+    {
+      bitstatus = RESET;
+    }
+  }
+  else
+  {
+    /* ETHERNET MMC Tx interrupts selected */
+    /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */
+    if ((((ETH_MMC->MMCTIR & ETH_MMC_IT) != (u32)RESET)) && ((ETH_MMC->MMCRIMR & ETH_MMC_IT) != (u32)RESET))
+    {
+      bitstatus = SET;
+    }
+    else
+    {
+      bitstatus = RESET;
+    }
+  }
+
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetMMCRegister
+* Desciption     : Get the specified ETHERNET MMC register value.
+* Input          : - ETH_MMCReg: specifies the ETHERNET MMC register.
+*                    This parameter can be one of the following values:
+*                       - ETH_MMCCR      : MMC CR register
+*                       - ETH_MMCRIR     : MMC RIR register
+*                       - ETH_MMCTIR     : MMC TIR register
+*                       - ETH_MMCRIMR    : MMC RIMR register
+*                       - ETH_MMCTIMR    : MMC TIMR register
+*                       - ETH_MMCTGFSCCR : MMC TGFSCCR register
+*                       - ETH_MMCTGFMSCCR: MMC TGFMSCCR register
+*                       - ETH_MMCTGFCR   : MMC TGFCR register
+*                       - ETH_MMCRFCECR  : MMC RFCECR register
+*                       - ETH_MMCRFAECR  : MMC RFAECR register
+*                       - ETH_MMCRGUFCR  : MMC RGUFCRregister
+* Output         : None
+* Return         : The value of ETHERNET MMC Register value.
+*******************************************************************************/
+u32 ETH_GetMMCRegister(u32 ETH_MMCReg)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg));
+
+  /* Return the selected register value */
+  return (*(vu32 *)(ETH_MAC_BASE + ETH_MMCReg));
+}
+#endif /* _ETH_MMC */
+
+/*---------------------------------  PTP  ------------------------------------*/
+#ifdef _ETH_PTP
+
+/*******************************************************************************
+* Function Name  : ETH_EnablePTPTimeStampAddend
+* Desciption     : Updated the PTP block for fine correction with the Time Stamp
+*                  Addend register value.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_EnablePTPTimeStampAddend(void)
+{
+  /* Enable the PTP block update with the Time Stamp Addend register value */
+  ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSARU;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_EnablePTPTimeStampInterruptTrigger
+* Desciption     : Enable the PTP Time Stamp interrupt trigger
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_EnablePTPTimeStampInterruptTrigger(void)
+{
+  /* Enable the PTP target time interrupt */
+  ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSITE;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_EnablePTPTimeStampUpdate
+* Desciption     : Updated the PTP system time with the Time Stamp Update register
+*                  value.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_EnablePTPTimeStampUpdate(void)
+{
+  /* Enable the PTP system time update with the Time Stamp Update register value */
+  ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSSTU;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_InitializePTPTimeStamp
+* Desciption     : Initialize the PTP Time Stamp
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_InitializePTPTimeStamp(void)
+{
+  /* Initialize the PTP Time Stamp */
+  ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSSTI;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_PTPUpdateMethodConfig
+* Desciption     : Selects the PTP Update method
+* Input          : - UpdateMethod: the PTP Update method
+*                    This parameter can be one of the following values:
+*                       - ETH_PTP_FineUpdate   : Fine Update method
+*                       - ETH_PTP_CoarseUpdate : Coarse Update method
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_PTPUpdateMethodConfig(u32 UpdateMethod)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_PTP_UPDATE(UpdateMethod));
+
+  if (UpdateMethod != ETH_PTP_CoarseUpdate)
+  {
+    /* Enable the PTP Fine Update method */
+    ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSFCU;
+  }
+  else
+  {
+    /* Disable the PTP Coarse Update method */
+    ETH_PTP->PTPTSCR &= (~(u32)ETH_PTPTSCR_TSFCU);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_PTPTimeStampCmd
+* Desciption     : Enables or disables the PTP time stamp for transmit and receive frames.
+* Input          : - NewState: new state of the PTP time stamp for transmit and receive frames
+*                    This parameter can be: ENABLE or DISABLE.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_PTPTimeStampCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the PTP time stamp for transmit and receive frames */
+    ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSE;
+  }
+  else
+  {
+    /* Disable the PTP time stamp for transmit and receive frames */
+    ETH_PTP->PTPTSCR &= (~(u32)ETH_PTPTSCR_TSE);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetPTPFlagStatus
+* Desciption     : Checks whether the specified ETHERNET PTP flag is set or not.
+* Input          : - ETH_PTP_FLAG: specifies the flag to check.
+*                    This parameter can be one of the following values:
+*                       - ETH_PTP_FLAG_TSARU : Addend Register Update
+*                       - ETH_PTP_FLAG_TSITE : Time Stamp Interrupt Trigger Enable
+*                       - ETH_PTP_FLAG_TSSTU : Time Stamp Update
+*                       - ETH_PTP_FLAG_TSSTI  : Time Stamp Initialize
+* Output         : None
+* Return         : The new state of ETHERNET PTP Flag (SET or RESET).
+*******************************************************************************/
+FlagStatus ETH_GetPTPFlagStatus(u32 ETH_PTP_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_PTP_GET_FLAG(ETH_PTP_FLAG));
+
+  if ((ETH_PTP->PTPTSCR & ETH_PTP_FLAG) != (u32)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_SetPTPSubSecondIncrement
+* Desciption     : Sets the system time Sub-Second Increment value.
+* Input          : - SubSecondValue: specifies the PTP Sub-Second Increment Register value.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_SetPTPSubSecondIncrement(u32 SubSecondValue)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_PTP_SUBSECOND_INCREMENT(SubSecondValue));
+
+  /* Set the PTP Sub-Second Increment Register */
+  ETH_PTP->PTPSSIR = SubSecondValue;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_SetPTPTimeStampUpdate
+* Desciption     : Sets the Time Stamp update sign and values.
+* Input          : - Sign: specifies the PTP Time update value sign.
+*                    This parameter can be one of the following values:
+*                       - ETH_PTP_PositiveTime : positive time value.
+*                       - ETH_PTP_NegativeTime : negative time value.
+*                  - SecondValue: specifies the PTP Time update second value.
+*                  - SubSecondValue: specifies the PTP Time update sub-second value.
+*                    this is a 31 bit value. bit32 correspond to the sign.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_SetPTPTimeStampUpdate(u32 Sign, u32 SecondValue, u32 SubSecondValue)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_PTP_TIME_SIGN(Sign));
+  eth_assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue));
+
+  /* Set the PTP Time Update High Register */
+  ETH_PTP->PTPTSHUR = SecondValue;
+
+  /* Set the PTP Time Update Low Register with sign */
+  ETH_PTP->PTPTSLUR = Sign | SubSecondValue;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_SetPTPTimeStampAddend
+* Desciption     : Sets the Time Stamp Addend value.
+* Input          : - Value: specifies the PTP Time Stamp Addend Register value.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_SetPTPTimeStampAddend(u32 Value)
+{
+  /* Set the PTP Time Stamp Addend Register */
+  ETH_PTP->PTPTSAR = Value;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_SetPTPTargetTime
+* Desciption     : Sets the Target Time registers values.
+* Input          : - HighValue: specifies the PTP Target Time High Register value.
+*                  - LowValue: specifies the PTP Target Time Low Register value.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_SetPTPTargetTime(u32 HighValue, u32 LowValue)
+{
+  /* Set the PTP Target Time High Register */
+  ETH_PTP->PTPTTHR = HighValue;
+  /* Set the PTP Target Time Low Register */
+  ETH_PTP->PTPTTLR = LowValue;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_GetPTPRegister
+* Desciption     : Get the specified ETHERNET PTP register value.
+* Input          : - ETH_PTPReg: specifies the ETHERNET PTP register.
+*                    This parameter can be one of the following values:
+*                       - ETH_PTPTSCR  : Sub-Second Increment Register
+*                       - ETH_PTPSSIR  : Sub-Second Increment Register
+*                       - ETH_PTPTSHR  : Time Stamp High Register
+*                       - ETH_PTPTSLR  : Time Stamp Low Register
+*                       - ETH_PTPTSHUR : Time Stamp High Update Register
+*                       - ETH_PTPTSLUR : Time Stamp Low Update Register
+*                       - ETH_PTPTSAR  : Time Stamp Addend Register
+*                       - ETH_PTPTTHR  : Target Time High Register
+*                       - ETH_PTPTTLR  : Target Time Low Register
+* Output         : None
+* Return         : The value of ETHERNET PTP Register value.
+*******************************************************************************/
+u32 ETH_GetPTPRegister(u32 ETH_PTPReg)
+{
+  /* Check the parameters */
+  eth_assert_param(IS_ETH_PTP_REGISTER(ETH_PTPReg));
+
+  /* Return the selected register value */
+  return (*(vu32 *)(ETH_MAC_BASE + ETH_PTPReg));
+}
+
+/*******************************************************************************
+* Function Name  : ETH_DMAPTPTxDescChainInit
+* Desciption     : Initializes the DMA Tx descriptors in chain mode with PTP.
+* Input          : - DMATxDescTab: Pointer on the first Tx desc list
+*                  - DMAPTPTxDescTab: Pointer on the first PTP Tx desc list
+*                  - TxBuff: Pointer on the first TxBuffer list
+*                  - TxBuffCount: Number of the used Tx desc in the list
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, u32 TxBuffCount)
+{
+  u32 i = 0;
+  ETH_DMADESCTypeDef *DMATxDesc;
+
+  /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
+  DMATxDescToSet = DMATxDescTab;
+  DMAPTPTxDescToSet = DMAPTPTxDescTab;
+
+  /* Fill each DMATxDesc descriptor with the right values */
+  for(i=0; i < TxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Tx Desc list */
+    DMATxDesc = DMATxDescTab+i;
+
+    /* Set Second Address Chained bit and enable PTP */
+    DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE;
+
+    /* Set Buffer1 address pointer */
+    DMATxDesc->Buffer1Addr =(u32)(&TxBuff[i*ETH_MAX_PACKET_SIZE]);
+
+    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
+    if(i < (TxBuffCount-1))
+    {
+      /* Set next descriptor address register with next descriptor base address */
+      DMATxDesc->Buffer2NextDescAddr = (u32)(DMATxDescTab+i+1);
+    }
+    else
+    {
+      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
+      DMATxDesc->Buffer2NextDescAddr = (u32) DMATxDescTab;
+    }
+
+	/* make DMAPTPTxDescTab points to the same addresses as DMATxDescTab */
+	(&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr;
+	(&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr;
+  }
+
+  /* Store on the last DMAPTPTxDescTab desc status record the first list address */
+  (&DMAPTPTxDescTab[i-1])->Status = (u32) DMAPTPTxDescTab;
+
+  /* Set Transmit Desciptor List Address Register */
+  ETH_DMA->DMATDLAR = (u32) DMATxDescTab;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_DMAPTPRxDescChainInit
+* Desciption     : Initializes the DMA Rx descriptors in chain mode.
+* Input          : - DMARxDescTab: Pointer on the first Rx desc list
+*                  - DMAPTPRxDescTab: Pointer on the first PTP Rx desc list
+*                  - RxBuff: Pointer on the first RxBuffer list
+*                  - RxBuffCount: Number of the used Rx desc in the list
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, u8 *RxBuff, u32 RxBuffCount)
+{
+  u32 i = 0;
+  ETH_DMADESCTypeDef *DMARxDesc;
+
+  /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
+  DMARxDescToGet = DMARxDescTab;
+  DMAPTPRxDescToGet = DMAPTPRxDescTab;
+
+  /* Fill each DMARxDesc descriptor with the right values */
+  for(i=0; i < RxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Rx Desc list */
+    DMARxDesc = DMARxDescTab+i;
+
+    /* Set Own bit of the Rx descriptor Status */
+    DMARxDesc->Status = ETH_DMARxDesc_OWN;
+
+    /* Set Buffer1 size and Second Address Chained bit */
+    DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (u32)ETH_MAX_PACKET_SIZE;
+
+    /* Set Buffer1 address pointer */
+    DMARxDesc->Buffer1Addr = (u32)(&RxBuff[i*ETH_MAX_PACKET_SIZE]);
+
+    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
+    if(i < (RxBuffCount-1))
+    {
+      /* Set next descriptor address register with next descriptor base address */
+      DMARxDesc->Buffer2NextDescAddr = (u32)(DMARxDescTab+i+1);
+    }
+    else
+    {
+      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
+      DMARxDesc->Buffer2NextDescAddr = (u32)(DMARxDescTab);
+    }
+
+	/* Make DMAPTPRxDescTab points to the same addresses as DMARxDescTab */
+	(&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr;
+	(&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr;
+  }
+
+  /* Store on the last DMAPTPRxDescTab desc status record the first list address */
+  (&DMAPTPRxDescTab[i-1])->Status = (u32) DMAPTPRxDescTab;
+
+  /* Set Receive Desciptor List Address Register */
+  ETH_DMA->DMARDLAR = (u32) DMARxDescTab;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_HandlePTPTxPkt
+* Desciption     : Transmits a packet, from application buffer, pointed by ppkt with
+*                  Time Stamp values.
+* Input          : - ppkt: pointer to application packet Buffer.
+*                  - FrameLength: Tx Packet size.
+*                  - PTPTxTab: Pointer on the first PTP Tx table to store Time stamp values.
+* Output         : None
+* Return         : ETH_ERROR: in case of Tx desc owned by DMA
+*                  ETH_SUCCESS: for correct transmission
+*******************************************************************************/
+u32 ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, u32 *PTPTxTab)
+{
+  u32 offset = 0, timeout = 0;
+
+  /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
+  if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (u32)RESET)
+  {
+    /* Return ERROR: OWN bit set */
+    return ETH_ERROR;
+  }
+
+  /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */
+  for(offset=0; offsetBuffer1Addr) + offset)) = (*(ppkt + offset));
+  }
+
+  /* Setting the Frame Length: bits[12:0] */
+  DMATxDescToSet->ControlBufferSize = (FrameLength & (u32)0x1FFF);
+
+  /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */
+  DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
+
+  /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
+  DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
+
+  /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
+  if ((ETH_DMA->DMASR & ETH_DMASR_TBUS) != (u32)RESET)
+  {
+    /* Clear TBUS ETHERNET DMA flag */
+    ETH_DMA->DMASR = ETH_DMASR_TBUS;
+    /* Resume DMA transmission*/
+    ETH_DMA->DMATPDR = 0;
+  }
+
+  /* Wait for ETH_DMATxDesc_TTSS flag to be set */
+  do
+  {
+    timeout++;
+  } while (!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF));
+
+  /* Return ERROR in case of timeout */
+  if(timeout == PHY_READ_TO)
+  {
+    return ETH_ERROR;
+  }
+
+  *PTPTxTab++ = DMATxDescToSet->Buffer1Addr;
+  *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr;
+
+  /* Update the ENET DMA current descriptor */
+  /* Chained Mode */
+  if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (u32)RESET)
+  {
+    /* Selects the next DMA Tx descriptor list for next buffer read */
+    DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Buffer2NextDescAddr);
+
+    if(DMAPTPTxDescToSet->Status != 0)
+    {
+      DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Status);
+    }
+    else
+    {
+      DMAPTPTxDescToSet++;
+    }
+  }
+  else /* Ring Mode */
+  {
+    if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (u32)RESET)
+    {
+      /* Selects the next DMA Tx descriptor list for next buffer read: this will
+         be the first Tx descriptor in this case */
+      DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMATDLAR);
+      DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMATDLAR);
+    }
+    else
+    {
+      /* Selects the next DMA Tx descriptor list for next buffer read */
+      DMATxDescToSet = (ETH_DMADESCTypeDef*) ((u32)DMATxDescToSet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));
+      DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) ((u32)DMAPTPTxDescToSet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));
+    }
+  }
+
+  /* Return SUCCESS */
+  return ETH_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : ETH_HandlePTPRxPkt
+* Desciption     : Receives a packet and copies it to memory pointed by ppkt with
+*                 Time Stamp values.
+* Input          : - PTPRxTab: Pointer on the first PTP Rx table to store Time stamp values.
+* Output         : ppkt: pointer on application receive buffer.
+* Return         : ETH_ERROR: if there is error in reception
+*                  Received packet size: if packet reception is correct
+*******************************************************************************/
+u32 ETH_HandlePTPRxPkt(u8 *ppkt, u32 *PTPRxTab)
+{
+  u32 offset = 0, FrameLength = 0;
+
+  /* Check if the descriptor is owned by the ENET or CPU */
+  if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (u32)RESET)
+  {
+    /* Return error: OWN bit set */
+    return ETH_ERROR;
+  }
+
+  if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (u32)RESET) &&
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (u32)RESET) &&
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (u32)RESET))
+  {
+    /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
+    FrameLength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4;
+
+    /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */
+    for(offset=0; offsetBuffer1Addr) + offset));
+    }
+  }
+  else
+  {
+    /* Return ERROR */
+    FrameLength = ETH_ERROR;
+  }
+
+  /* When Rx Buffer unavailable flag is set: clear it and resume reception */
+  if ((ETH_DMA->DMASR & ETH_DMASR_RBUS) != (u32)RESET)
+  {
+    /* Clear RBUS ETHERNET DMA flag */
+    ETH_DMA->DMASR = ETH_DMASR_RBUS;
+    /* Resume DMA reception */
+    ETH_DMA->DMARPDR = 0;
+  }
+
+  *PTPRxTab++ = DMARxDescToGet->Buffer1Addr;
+  *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr;
+
+  /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
+  DMARxDescToGet->Status |= ETH_DMARxDesc_OWN;
+
+  /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */
+  /* Chained Mode */
+  if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (u32)RESET)
+  {
+    /* Selects the next DMA Rx descriptor list for next buffer read */
+    DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Buffer2NextDescAddr);
+
+    if(DMAPTPRxDescToGet->Status != 0)
+    {
+      DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Status);
+    }
+    else
+    {
+      DMAPTPRxDescToGet++;
+    }
+  }
+  else /* Ring Mode */
+  {
+    if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (u32)RESET)
+    {
+      /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMARDLAR);
+    }
+    else
+    {
+      /* Selects the next DMA Rx descriptor list for next buffer to read */
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) ((u32)DMARxDescToGet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));
+    }
+  }
+
+  /* Return Frame Length/ERROR */
+  return (FrameLength);
+}
+
+#endif /* _ETH_PTP */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32fxxx_eth_lib.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32fxxx_eth_lib.c
new file mode 100644
index 0000000..c777fea
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32fxxx_eth_lib.c
@@ -0,0 +1,58 @@
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name          : stm32fxxx_eth_lib.c
+* Author             : MCD Application Team
+* Version            : V2.0.2
+* Date               : 07/11/2008
+* Description        : This file provides all peripherals pointers initialization.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+#define EXT
+#include "stm32f10x_lib.h"
+/* Includes ------------------------------------------------------------------*/
+#include "stm32fxxx_eth_lib.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+#ifdef ETH_DEBUG
+/*******************************************************************************
+* Function Name  : ethernet_debug
+* Description    : This function initialize peripherals pointers.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void eth_debug(void)
+{
+/********************************** ETHERNET **********************************/
+#ifdef _ETH_MAC
+  ETH_MAC = ((ETH_MAC_TypeDef *) ETH_MAC_BASE);
+#endif /*_ETH_MAC */
+
+#ifdef _ETH_MMC
+  ETH_MMC = ((ETH_MMC_TypeDef *) ETH_MMC_BASE);
+#endif /*_ETH_MMC */
+
+#ifdef _ETH_PTP
+  ETH_PTP = ((ETH_PTP_TypeDef *) ETH_PTP_BASE);
+#endif /*_ETH_PTP */
+
+#ifdef _ETH_DMA
+  ETH_DMA = ((ETH_DMA_TypeDef *) ETH_DMA_BASE);
+#endif /*_ETH_DMA */
+}
+
+#endif  /* ETH_DEBUG*/
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/version.txt b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/version.txt
new file mode 100644
index 0000000..72d3001
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/drivers/ST/STM32F10xFWLib/version.txt
@@ -0,0 +1,22 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name          : version.txt
+* Author             : MCD Application Team
+* Date First Issued  : 09/29/2006
+* Description        : Version file for STM32F10x Firmware Library.
+********************************************************************************
+
+* 04/02/2007: V0.2
+===================
+  Updated version
+  
+* 02/05/2007 : V0.1
+===================
+  Updated version
+
+* 09/29/2006 : V0.01
+===================
+  Created.
+
+******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE******
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/Makefile.include b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/Makefile.include
new file mode 100644
index 0000000..43ba247
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/Makefile.include
@@ -0,0 +1,47 @@
+
+
+ifdef APPS
+  APPDIRS = $(foreach APP, $(APPS), ../apps/$(APP))
+  -include $(foreach APP, $(APPS), ../apps/$(APP)/Makefile.$(APP))
+  CFLAGS += $(addprefix -I../apps/,$(APPS))
+endif
+
+ifndef CCDEP
+  CCDEP = $(CC)
+endif
+ifndef CCDEPCFLAGS
+  CCDEPCFLAGS = $(CFLAGS)
+endif
+ifndef OBJECTDIR
+  OBJECTDIR = obj
+endif
+
+ifeq (${wildcard $(OBJECTDIR)},)
+  DUMMY := ${shell mkdir $(OBJECTDIR)}
+endif
+
+
+vpath %.c . ../uip ../lib $(APPDIRS)
+
+$(OBJECTDIR)/%.o: %.c
+	$(CC) $(CFLAGS) -c $< -o $@
+
+$(OBJECTDIR)/%.d: %.c
+	@set -e; rm -f $@; \
+	$(CCDEP) -MM $(CCDEPCFLAGS) $< > $@.$$$$; \
+	sed 's,\($*\)\.o[ :]*,$(OBJECTDIR)/\1.o $@ : ,g' < $@.$$$$ > $@; \
+	rm -f $@.$$$$
+
+UIP_SOURCES=uip.c uip_arp.c uiplib.c psock.c timer.c uip-neighbor.c
+
+
+ifneq ($(MAKECMDGOALS),clean)
+-include $(addprefix $(OBJECTDIR)/,$(UIP_SOURCES:.c=.d) \
+                                   $(APP_SOURCES:.c=.d))
+endif
+
+uip.a: ${addprefix $(OBJECTDIR)/, $(UIP_SOURCES:.c=.o)}
+	$(AR) rcf $@ $^
+
+apps.a: ${addprefix $(OBJECTDIR)/, $(APP_SOURCES:.c=.o)}
+	$(AR) rcf $@ $^
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/clock-arch.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/clock-arch.h
new file mode 100644
index 0000000..cde657b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/clock-arch.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $
+ */
+
+#ifndef __CLOCK_ARCH_H__
+#define __CLOCK_ARCH_H__
+
+#include "FreeRTOS.h"
+
+typedef unsigned long clock_time_t;
+#define CLOCK_CONF_SECOND configTICK_RATE_HZ
+
+#endif /* __CLOCK_ARCH_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/clock.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/clock.h
new file mode 100644
index 0000000..dae6874
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/clock.h
@@ -0,0 +1,88 @@
+/**
+ * \defgroup clock Clock interface
+ *
+ * The clock interface is the interface between the \ref timer "timer library"
+ * and the platform specific clock functionality. The clock
+ * interface must be implemented for each platform that uses the \ref
+ * timer "timer library".
+ *
+ * The clock interface does only one this: it measures time. The clock
+ * interface provides a macro, CLOCK_SECOND, which corresponds to one
+ * second of system time.
+ *
+ * \sa \ref timer "Timer library"
+ *
+ * @{
+ */
+
+/*
+ * Copyright (c) 2004, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: clock.h,v 1.3 2006/06/11 21:46:39 adam Exp $
+ */
+#ifndef __CLOCK_H__
+#define __CLOCK_H__
+
+#include "clock-arch.h"
+
+/**
+ * Initialize the clock library.
+ *
+ * This function initializes the clock library and should be called
+ * from the main() function of the system.
+ *
+ */
+void clock_init(void);
+
+/**
+ * Get the current clock time.
+ *
+ * This function returns the current system clock time.
+ *
+ * \return The current clock time, measured in system ticks.
+ */
+clock_time_t clock_time(void);
+
+/**
+ * A second, measured in system clock time.
+ *
+ * \hideinitializer
+ */
+#ifdef CLOCK_CONF_SECOND
+#define CLOCK_SECOND CLOCK_CONF_SECOND
+#else
+#define CLOCK_SECOND (clock_time_t)32
+#endif
+
+#endif /* __CLOCK_H__ */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/lc-addrlabels.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/lc-addrlabels.h
new file mode 100644
index 0000000..9dff03d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/lc-addrlabels.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2004-2005, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: lc-addrlabels.h,v 1.3 2006/06/12 08:00:30 adam Exp $
+ */
+
+/**
+ * \addtogroup lc
+ * @{
+ */
+
+/**
+ * \file
+ * Implementation of local continuations based on the "Labels as
+ * values" feature of gcc
+ * \author
+ * Adam Dunkels 
+ *
+ * This implementation of local continuations is based on a special
+ * feature of the GCC C compiler called "labels as values". This
+ * feature allows assigning pointers with the address of the code
+ * corresponding to a particular C label.
+ *
+ * For more information, see the GCC documentation:
+ * http://gcc.gnu.org/onlinedocs/gcc/Labels-as-Values.html
+ *
+ * Thanks to dividuum for finding the nice local scope label
+ * implementation.
+ */
+
+#ifndef __LC_ADDRLABELS_H__
+#define __LC_ADDRLABELS_H__
+
+/** \hideinitializer */
+typedef void * lc_t;
+
+#define LC_INIT(s) s = NULL
+
+
+#define LC_RESUME(s)                            \
+  do {                                          \
+    if(s != NULL) {                             \
+      goto *s;                                  \
+    }                                           \
+  } while(0)
+
+#define LC_SET(s)                               \
+  do { ({ __label__ resume; resume: (s) = &&resume; }); }while(0)
+
+#define LC_END(s)
+
+#endif /* __LC_ADDRLABELS_H__ */
+
+/**  @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/lc-switch.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/lc-switch.h
new file mode 100644
index 0000000..17c8811
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/lc-switch.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2004-2005, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: lc-switch.h,v 1.2 2006/06/12 08:00:30 adam Exp $
+ */
+
+/**
+ * \addtogroup lc
+ * @{
+ */
+
+/**
+ * \file
+ * Implementation of local continuations based on switch() statment
+ * \author Adam Dunkels 
+ *
+ * This implementation of local continuations uses the C switch()
+ * statement to resume execution of a function somewhere inside the
+ * function's body. The implementation is based on the fact that
+ * switch() statements are able to jump directly into the bodies of
+ * control structures such as if() or while() statmenets.
+ *
+ * This implementation borrows heavily from Simon Tatham's coroutines
+ * implementation in C:
+ * http://www.chiark.greenend.org.uk/~sgtatham/coroutines.html
+ */
+
+#ifndef __LC_SWITCH_H__
+#define __LC_SWTICH_H__
+
+/* WARNING! lc implementation using switch() does not work if an
+   LC_SET() is done within another switch() statement! */
+
+/** \hideinitializer */
+typedef unsigned short lc_t;
+
+#define LC_INIT(s) s = 0;
+
+#define LC_RESUME(s) switch(s) { case 0:
+
+#define LC_SET(s) s = __LINE__; case __LINE__:
+
+#define LC_END(s) }
+
+#endif /* __LC_SWITCH_H__ */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/lc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/lc.h
new file mode 100644
index 0000000..3ad83cd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/lc.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2004-2005, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: lc.h,v 1.2 2006/06/12 08:00:30 adam Exp $
+ */
+
+/**
+ * \addtogroup pt
+ * @{
+ */
+
+/**
+ * \defgroup lc Local continuations
+ * @{
+ *
+ * Local continuations form the basis for implementing protothreads. A
+ * local continuation can be set in a specific function to
+ * capture the state of the function. After a local continuation has
+ * been set can be resumed in order to restore the state of the
+ * function at the point where the local continuation was set.
+ *
+ *
+ */
+
+/**
+ * \file lc.h
+ * Local continuations
+ * \author
+ * Adam Dunkels 
+ *
+ */
+
+#ifdef DOXYGEN
+/**
+ * Initialize a local continuation.
+ *
+ * This operation initializes the local continuation, thereby
+ * unsetting any previously set continuation state.
+ *
+ * \hideinitializer
+ */
+#define LC_INIT(lc)
+
+/**
+ * Set a local continuation.
+ *
+ * The set operation saves the state of the function at the point
+ * where the operation is executed. As far as the set operation is
+ * concerned, the state of the function does not include the
+ * call-stack or local (automatic) variables, but only the program
+ * counter and such CPU registers that needs to be saved.
+ *
+ * \hideinitializer
+ */
+#define LC_SET(lc)
+
+/**
+ * Resume a local continuation.
+ *
+ * The resume operation resumes a previously set local continuation, thus
+ * restoring the state in which the function was when the local
+ * continuation was set. If the local continuation has not been
+ * previously set, the resume operation does nothing.
+ *
+ * \hideinitializer
+ */
+#define LC_RESUME(lc)
+
+/**
+ * Mark the end of local continuation usage.
+ *
+ * The end operation signifies that local continuations should not be
+ * used any more in the function. This operation is not needed for
+ * most implementations of local continuation, but is required by a
+ * few implementations.
+ *
+ * \hideinitializer
+ */
+#define LC_END(lc)
+
+/**
+ * \var typedef lc_t;
+ *
+ * The local continuation type.
+ *
+ * \hideinitializer
+ */
+#endif /* DOXYGEN */
+
+#ifndef __LC_H__
+#define __LC_H__
+
+#ifdef LC_CONF_INCLUDE
+#include LC_CONF_INCLUDE
+#else
+#include "lc-switch.h"
+#endif /* LC_CONF_INCLUDE */
+
+#endif /* __LC_H__ */
+
+/** @} */
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/psock.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/psock.c
new file mode 100644
index 0000000..d29ef01
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/psock.c
@@ -0,0 +1,374 @@
+/*
+ * Copyright (c) 2004, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: psock.c,v 1.1 2007/01/04 11:06:40 adamdunkels Exp $
+ */
+#include 
+#include 
+
+#include "uipopt.h"
+#include "psock.h"
+#include "uip.h"
+
+#define STATE_NONE				0
+#define STATE_ACKED				1
+#define STATE_READ				2
+#define STATE_BLOCKED_NEWDATA	3
+#define STATE_BLOCKED_CLOSE		4
+#define STATE_BLOCKED_SEND		5
+#define STATE_DATA_SENT			6
+
+/*
+ * Return value of the buffering functions that indicates that a
+ * buffer was not filled by incoming data.
+ *
+ */
+#define BUF_NOT_FULL	0
+#define BUF_NOT_FOUND	0
+
+/*
+ * Return value of the buffering functions that indicates that a
+ * buffer was completely filled by incoming data.
+ *
+ */
+#define BUF_FULL	1
+
+/*
+ * Return value of the buffering functions that indicates that an
+ * end-marker byte was found.
+ *
+ */
+#define BUF_FOUND	2
+
+/*---------------------------------------------------------------------------*/
+static void buf_setup( struct psock_buf *buf, u8_t *bufptr, u16_t bufsize )
+{
+	buf->ptr = bufptr;
+	buf->left = bufsize;
+}
+
+/*---------------------------------------------------------------------------*/
+static u8_t buf_bufdata( struct psock_buf *buf, u16_t len, u8_t **dataptr, u16_t *datalen )
+{
+	( void ) len;
+
+	if( *datalen < buf->left )
+	{
+		memcpy( buf->ptr, *dataptr, *datalen );
+		buf->ptr += *datalen;
+		buf->left -= *datalen;
+		*dataptr += *datalen;
+		*datalen = 0;
+		return BUF_NOT_FULL;
+	}
+	else if( *datalen == buf->left )
+	{
+		memcpy( buf->ptr, *dataptr, *datalen );
+		buf->ptr += *datalen;
+		buf->left = 0;
+		*dataptr += *datalen;
+		*datalen = 0;
+		return BUF_FULL;
+	}
+	else
+	{
+		memcpy( buf->ptr, *dataptr, buf->left );
+		buf->ptr += buf->left;
+		*datalen -= buf->left;
+		*dataptr += buf->left;
+		buf->left = 0;
+		return BUF_FULL;
+	}
+}
+
+/*---------------------------------------------------------------------------*/
+static u8_t buf_bufto( register struct psock_buf *buf, u8_t endmarker, register u8_t **dataptr, register u16_t *datalen )
+{
+	u8_t	c;
+	while( buf->left > 0 && *datalen > 0 )
+	{
+		c = *buf->ptr = **dataptr;
+		++ *dataptr;
+		++buf->ptr;
+		-- *datalen;
+		--buf->left;
+
+		if( c == endmarker )
+		{
+			return BUF_FOUND;
+		}
+	}
+
+	if( *datalen == 0 )
+	{
+		return BUF_NOT_FOUND;
+	}
+
+	while( *datalen > 0 )
+	{
+		c = **dataptr;
+		-- *datalen;
+		++ *dataptr;
+
+		if( c == endmarker )
+		{
+			return BUF_FOUND | BUF_FULL;
+		}
+	}
+
+	return BUF_FULL;
+}
+
+/*---------------------------------------------------------------------------*/
+static char send_data( register struct psock *s )
+{
+	if( s->state != STATE_DATA_SENT || uip_rexmit() )
+	{
+		if( s->sendlen > uip_mss() )
+		{
+			uip_send( s->sendptr, uip_mss() );
+		}
+		else
+		{
+			uip_send( s->sendptr, s->sendlen );
+		}
+
+		s->state = STATE_DATA_SENT;
+		return 1;
+	}
+
+	return 0;
+}
+
+/*---------------------------------------------------------------------------*/
+static char data_acked( register struct psock *s )
+{
+	if( s->state == STATE_DATA_SENT && uip_acked() )
+	{
+		if( s->sendlen > uip_mss() )
+		{
+			s->sendlen -= uip_mss();
+			s->sendptr += uip_mss();
+		}
+		else
+		{
+			s->sendptr += s->sendlen;
+			s->sendlen = 0;
+		}
+
+		s->state = STATE_ACKED;
+		return 1;
+	}
+
+	return 0;
+}
+
+/*---------------------------------------------------------------------------*/
+PT_THREAD( psock_send ( register struct psock *s, const char *buf, unsigned int len ) )
+{
+	PT_BEGIN( &s->psockpt );
+
+	/* If there is no data to send, we exit immediately. */
+	if( len == 0 )
+	{
+		PT_EXIT( &s->psockpt );
+	}
+
+	/* Save the length of and a pointer to the data that is to be
+     sent. */
+	s->sendptr = ( u8_t * ) buf;
+	s->sendlen = len;
+
+	s->state = STATE_NONE;
+
+	/* We loop here until all data is sent. The s->sendlen variable is
+     updated by the data_sent() function. */
+	while( s->sendlen > 0 )
+	{
+		/*
+     * The condition for this PT_WAIT_UNTIL is a little tricky: the
+     * protothread will wait here until all data has been acknowledged
+     * (data_acked() returns true) and until all data has been sent
+     * (send_data() returns true). The two functions data_acked() and
+     * send_data() must be called in succession to ensure that all
+     * data is sent. Therefore the & operator is used instead of the
+     * && operator, which would cause only the data_acked() function
+     * to be called when it returns false.
+     */
+		PT_WAIT_UNTIL( &s->psockpt, data_acked(s) & send_data(s) );
+	}
+
+	s->state = STATE_NONE;
+
+	PT_END( &s->psockpt );
+}
+
+/*---------------------------------------------------------------------------*/
+PT_THREAD( psock_generator_send ( register struct psock *s, unsigned short ( *generate ) ( void * ), void *arg ) )
+{
+	PT_BEGIN( &s->psockpt );
+
+	/* Ensure that there is a generator function to call. */
+	if( generate == NULL )
+	{
+		PT_EXIT( &s->psockpt );
+	}
+
+	/* Call the generator function to generate the data in the
+     uip_appdata buffer. */
+	s->sendlen = generate( arg );
+	s->sendptr = uip_appdata;
+
+	s->state = STATE_NONE;
+	do
+	{
+		/* Call the generator function again if we are called to perform a
+       retransmission. */
+		if( uip_rexmit() )
+		{
+			generate( arg );
+		}
+
+		/* Wait until all data is sent and acknowledged. */
+		PT_WAIT_UNTIL( &s->psockpt, data_acked(s) & send_data(s) );
+	} while( s->sendlen > 0 );
+
+	s->state = STATE_NONE;
+
+	PT_END( &s->psockpt );
+}
+
+/*---------------------------------------------------------------------------*/
+u16_t psock_datalen( struct psock *psock )
+{
+	return psock->bufsize - psock->buf.left;
+}
+
+/*---------------------------------------------------------------------------*/
+char psock_newdata( struct psock *s )
+{
+	if( s->readlen > 0 )
+	{
+		/* There is data in the uip_appdata buffer that has not yet been
+       read with the PSOCK_READ functions. */
+		return 1;
+	}
+	else if( s->state == STATE_READ )
+	{
+		/* All data in uip_appdata buffer already consumed. */
+		s->state = STATE_BLOCKED_NEWDATA;
+		return 0;
+	}
+	else if( uip_newdata() )
+	{
+		/* There is new data that has not been consumed. */
+		return 1;
+	}
+	else
+	{
+		/* There is no new data. */
+		return 0;
+	}
+}
+
+/*---------------------------------------------------------------------------*/
+PT_THREAD( psock_readto ( register struct psock *psock, unsigned char c ) )
+{
+	PT_BEGIN( &psock->psockpt );
+
+	buf_setup( &psock->buf, ( u8_t * ) psock->bufptr, psock->bufsize );
+
+	/* XXX: Should add buf_checkmarker() before do{} loop, if
+     incoming data has been handled while waiting for a write. */
+	do
+	{
+		if( psock->readlen == 0 )
+		{
+			PT_WAIT_UNTIL( &psock->psockpt, psock_newdata(psock) );
+			psock->state = STATE_READ;
+			psock->readptr = ( u8_t * ) uip_appdata;
+			psock->readlen = uip_datalen();
+		}
+	} while( (buf_bufto(&psock->buf, c, &psock->readptr, &psock->readlen) & BUF_FOUND) == 0 );
+
+	if( psock_datalen(psock) == 0 )
+	{
+		psock->state = STATE_NONE;
+		PT_RESTART( &psock->psockpt );
+	}
+
+	PT_END( &psock->psockpt );
+}
+
+/*---------------------------------------------------------------------------*/
+PT_THREAD( psock_readbuf ( register struct psock *psock ) )
+{
+	PT_BEGIN( &psock->psockpt );
+
+	buf_setup( &psock->buf, ( u8_t * ) psock->bufptr, psock->bufsize );
+
+	/* XXX: Should add buf_checkmarker() before do{} loop, if
+     incoming data has been handled while waiting for a write. */
+	do
+	{
+		if( psock->readlen == 0 )
+		{
+			PT_WAIT_UNTIL( &psock->psockpt, psock_newdata(psock) );
+			printf( "Waited for newdata\n" );
+			psock->state = STATE_READ;
+			psock->readptr = ( u8_t * ) uip_appdata;
+			psock->readlen = uip_datalen();
+		}
+	} while( buf_bufdata(&psock->buf, psock->bufsize, &psock->readptr, &psock->readlen) != BUF_FULL );
+
+	if( psock_datalen(psock) == 0 )
+	{
+		psock->state = STATE_NONE;
+		PT_RESTART( &psock->psockpt );
+	}
+
+	PT_END( &psock->psockpt );
+}
+
+/*---------------------------------------------------------------------------*/
+void psock_init( register struct psock *psock, char *buffer, unsigned int buffersize )
+{
+	psock->state = STATE_NONE;
+	psock->readlen = 0;
+	psock->bufptr = buffer;
+	psock->bufsize = buffersize;
+	buf_setup( &psock->buf, ( u8_t * ) buffer, buffersize );
+	PT_INIT( &psock->pt );
+	PT_INIT( &psock->psockpt );
+}
+
+/*---------------------------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/psock.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/psock.h
new file mode 100644
index 0000000..8d41258
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/psock.h
@@ -0,0 +1,380 @@
+/*
+ * Copyright (c) 2004, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: psock.h,v 1.3 2006/06/12 08:00:30 adam Exp $
+ */
+
+/**
+ * \defgroup psock Protosockets library
+ * @{
+ *
+ * The protosocket library provides an interface to the uIP stack that is
+ * similar to the traditional BSD socket interface. Unlike programs
+ * written for the ordinary uIP event-driven interface, programs
+ * written with the protosocket library are executed in a sequential
+ * fashion and does not have to be implemented as explicit state
+ * machines.
+ *
+ * Protosockets only work with TCP connections.
+ *
+ * The protosocket library uses \ref pt protothreads to provide
+ * sequential control flow. This makes the protosockets lightweight in
+ * terms of memory, but also means that protosockets inherits the
+ * functional limitations of protothreads. Each protosocket lives only
+ * within a single function. Automatic variables (stack variables) are
+ * not retained across a protosocket library function call.
+ *
+ * \note Because the protosocket library uses protothreads, local
+ * variables will not always be saved across a call to a protosocket
+ * library function. It is therefore advised that local variables are
+ * used with extreme care.
+ *
+ * The protosocket library provides functions for sending data without
+ * having to deal with retransmissions and acknowledgements, as well
+ * as functions for reading data without having to deal with data
+ * being split across more than one TCP segment.
+ *
+ * Because each protosocket runs as a protothread, the protosocket has to be
+ * started with a call to PSOCK_BEGIN() at the start of the function
+ * in which the protosocket is used. Similarly, the protosocket protothread can
+ * be terminated by a call to PSOCK_EXIT().
+ *
+ */
+
+/**
+ * \file
+ * Protosocket library header file
+ * \author
+ * Adam Dunkels 
+ *
+ */
+
+#ifndef __PSOCK_H__
+#define __PSOCK_H__
+
+#include "uipopt.h"
+#include "pt.h"
+
+ /*
+ * The structure that holds the state of a buffer.
+ *
+ * This structure holds the state of a uIP buffer. The structure has
+ * no user-visible elements, but is used through the functions
+ * provided by the library.
+ *
+ */
+struct psock_buf {
+  u8_t *ptr;
+  unsigned short left;
+};
+
+/**
+ * The representation of a protosocket.
+ *
+ * The protosocket structrure is an opaque structure with no user-visible
+ * elements.
+ */
+struct psock {
+  struct pt pt, psockpt; /* Protothreads - one that's using the psock
+			    functions, and one that runs inside the
+			    psock functions. */
+  const u8_t *sendptr;   /* Pointer to the next data to be sent. */
+  u8_t *readptr;         /* Pointer to the next data to be read. */
+  
+  char *bufptr;          /* Pointer to the buffer used for buffering
+			    incoming data. */
+  
+  u16_t sendlen;         /* The number of bytes left to be sent. */
+  u16_t readlen;         /* The number of bytes left to be read. */
+
+  struct psock_buf buf;  /* The structure holding the state of the
+			    input buffer. */
+  unsigned int bufsize;  /* The size of the input buffer. */
+  
+  unsigned char state;   /* The state of the protosocket. */
+};
+
+void psock_init(struct psock *psock, char *buffer, unsigned int buffersize);
+/**
+ * Initialize a protosocket.
+ *
+ * This macro initializes a protosocket and must be called before the
+ * protosocket is used. The initialization also specifies the input buffer
+ * for the protosocket.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket to be
+ * initialized
+ *
+ * \param buffer (char *) A pointer to the input buffer for the
+ * protosocket.
+ *
+ * \param buffersize (unsigned int) The size of the input buffer.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_INIT(psock, buffer, buffersize) \
+  psock_init(psock, buffer, buffersize)
+
+/**
+ * Start the protosocket protothread in a function.
+ *
+ * This macro starts the protothread associated with the protosocket and
+ * must come before other protosocket calls in the function it is used.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket to be
+ * started.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_BEGIN(psock) PT_BEGIN(&((psock)->pt))
+
+PT_THREAD(psock_send(struct psock *psock, const char *buf, unsigned int len));
+/**
+ * Send data.
+ *
+ * This macro sends data over a protosocket. The protosocket protothread blocks
+ * until all data has been sent and is known to have been received by
+ * the remote end of the TCP connection.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket over which
+ * data is to be sent.
+ *
+ * \param data (char *) A pointer to the data that is to be sent.
+ *
+ * \param datalen (unsigned int) The length of the data that is to be
+ * sent.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_SEND(psock, data, datalen)		\
+    PT_WAIT_THREAD(&((psock)->pt), psock_send(psock, data, datalen))
+
+/**
+ * \brief      Send a null-terminated string.
+ * \param psock Pointer to the protosocket.
+ * \param str  The string to be sent.
+ *
+ *             This function sends a null-terminated string over the
+ *             protosocket.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_SEND_STR(psock, str)      		\
+    PT_WAIT_THREAD(&((psock)->pt), psock_send(psock, str, strlen(str)))
+
+PT_THREAD(psock_generator_send(struct psock *psock,
+				unsigned short (*f)(void *), void *arg));
+
+/**
+ * \brief      Generate data with a function and send it
+ * \param psock Pointer to the protosocket.
+ * \param generator Pointer to the generator function
+ * \param arg   Argument to the generator function
+ *
+ *             This function generates data and sends it over the
+ *             protosocket. This can be used to dynamically generate
+ *             data for a transmission, instead of generating the data
+ *             in a buffer beforehand. This function reduces the need for
+ *             buffer memory. The generator function is implemented by
+ *             the application, and a pointer to the function is given
+ *             as an argument with the call to PSOCK_GENERATOR_SEND().
+ *
+ *             The generator function should place the generated data
+ *             directly in the uip_appdata buffer, and return the
+ *             length of the generated data. The generator function is
+ *             called by the protosocket layer when the data first is
+ *             sent, and once for every retransmission that is needed.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_GENERATOR_SEND(psock, generator, arg)     \
+    PT_WAIT_THREAD(&((psock)->pt),					\
+		   psock_generator_send(psock, generator, arg))
+
+
+/**
+ * Close a protosocket.
+ *
+ * This macro closes a protosocket and can only be called from within the
+ * protothread in which the protosocket lives.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket that is to
+ * be closed.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_CLOSE(psock) uip_close()
+
+PT_THREAD(psock_readbuf(struct psock *psock));
+/**
+ * Read data until the buffer is full.
+ *
+ * This macro will block waiting for data and read the data into the
+ * input buffer specified with the call to PSOCK_INIT(). Data is read
+ * until the buffer is full..
+ *
+ * \param psock (struct psock *) A pointer to the protosocket from which
+ * data should be read.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_READBUF(psock)				\
+  PT_WAIT_THREAD(&((psock)->pt), psock_readbuf(psock))
+
+PT_THREAD(psock_readto(struct psock *psock, unsigned char c));
+/**
+ * Read data up to a specified character.
+ *
+ * This macro will block waiting for data and read the data into the
+ * input buffer specified with the call to PSOCK_INIT(). Data is only
+ * read until the specifieed character appears in the data stream.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket from which
+ * data should be read.
+ *
+ * \param c (char) The character at which to stop reading.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_READTO(psock, c)				\
+  PT_WAIT_THREAD(&((psock)->pt), psock_readto(psock, c))
+
+/**
+ * The length of the data that was previously read.
+ *
+ * This macro returns the length of the data that was previously read
+ * using PSOCK_READTO() or PSOCK_READ().
+ *
+ * \param psock (struct psock *) A pointer to the protosocket holding the data.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_DATALEN(psock) psock_datalen(psock)
+
+u16_t psock_datalen(struct psock *psock);
+
+/**
+ * Exit the protosocket's protothread.
+ *
+ * This macro terminates the protothread of the protosocket and should
+ * almost always be used in conjunction with PSOCK_CLOSE().
+ *
+ * \sa PSOCK_CLOSE_EXIT()
+ *
+ * \param psock (struct psock *) A pointer to the protosocket.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_EXIT(psock) PT_EXIT(&((psock)->pt))
+
+/**
+ * Close a protosocket and exit the protosocket's protothread.
+ *
+ * This macro closes a protosocket and exits the protosocket's protothread.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_CLOSE_EXIT(psock)		\
+  do {						\
+    PSOCK_CLOSE(psock);			\
+    PSOCK_EXIT(psock);			\
+  } while(0)
+
+/**
+ * Declare the end of a protosocket's protothread.
+ *
+ * This macro is used for declaring that the protosocket's protothread
+ * ends. It must always be used together with a matching PSOCK_BEGIN()
+ * macro.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_END(psock) PT_END(&((psock)->pt))
+
+char psock_newdata(struct psock *s);
+
+/**
+ * Check if new data has arrived on a protosocket.
+ *
+ * This macro is used in conjunction with the PSOCK_WAIT_UNTIL()
+ * macro to check if data has arrived on a protosocket.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_NEWDATA(psock) psock_newdata(psock)
+
+/**
+ * Wait until a condition is true.
+ *
+ * This macro blocks the protothread until the specified condition is
+ * true. The macro PSOCK_NEWDATA() can be used to check if new data
+ * arrives when the protosocket is waiting.
+ *
+ * Typically, this macro is used as follows:
+ *
+ \code
+ PT_THREAD(thread(struct psock *s, struct timer *t))
+ {
+   PSOCK_BEGIN(s);
+
+   PSOCK_WAIT_UNTIL(s, PSOCK_NEWADATA(s) || timer_expired(t));
+   
+   if(PSOCK_NEWDATA(s)) {
+     PSOCK_READTO(s, '\n');
+   } else {
+     handle_timed_out(s);
+   }
+   
+   PSOCK_END(s);
+ }
+ \endcode
+ *
+ * \param psock (struct psock *) A pointer to the protosocket.
+ * \param condition The condition to wait for.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_WAIT_UNTIL(psock, condition)    \
+  PT_WAIT_UNTIL(&((psock)->pt), (condition));
+
+#define PSOCK_WAIT_THREAD(psock, condition)   \
+  PT_WAIT_THREAD(&((psock)->pt), (condition))
+
+#endif /* __PSOCK_H__ */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/pt.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/pt.h
new file mode 100644
index 0000000..00ddd44
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/pt.h
@@ -0,0 +1,323 @@
+/*
+ * Copyright (c) 2004-2005, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: pt.h,v 1.2 2006/06/12 08:00:30 adam Exp $
+ */
+
+/**
+ * \addtogroup pt
+ * @{
+ */
+
+/**
+ * \file
+ * Protothreads implementation.
+ * \author
+ * Adam Dunkels 
+ *
+ */
+
+#ifndef __PT_H__
+#define __PT_H__
+
+#include "lc.h"
+
+struct pt {
+  lc_t lc;
+};
+
+#define PT_WAITING 0
+#define PT_EXITED  1
+#define PT_ENDED   2
+#define PT_YIELDED 3
+
+/**
+ * \name Initialization
+ * @{
+ */
+
+/**
+ * Initialize a protothread.
+ *
+ * Initializes a protothread. Initialization must be done prior to
+ * starting to execute the protothread.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \sa PT_SPAWN()
+ *
+ * \hideinitializer
+ */
+#define PT_INIT(pt)   LC_INIT((pt)->lc)
+
+/** @} */
+
+/**
+ * \name Declaration and definition
+ * @{
+ */
+
+/**
+ * Declaration of a protothread.
+ *
+ * This macro is used to declare a protothread. All protothreads must
+ * be declared with this macro.
+ *
+ * \param name_args The name and arguments of the C function
+ * implementing the protothread.
+ *
+ * \hideinitializer
+ */
+#define PT_THREAD(name_args) char name_args
+
+/**
+ * Declare the start of a protothread inside the C function
+ * implementing the protothread.
+ *
+ * This macro is used to declare the starting point of a
+ * protothread. It should be placed at the start of the function in
+ * which the protothread runs. All C statements above the PT_BEGIN()
+ * invokation will be executed each time the protothread is scheduled.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \hideinitializer
+ */
+#define PT_BEGIN(pt) { char PT_YIELD_FLAG = 1; LC_RESUME((pt)->lc)
+
+/**
+ * Declare the end of a protothread.
+ *
+ * This macro is used for declaring that a protothread ends. It must
+ * always be used together with a matching PT_BEGIN() macro.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \hideinitializer
+ */
+#define PT_END(pt) LC_END((pt)->lc); PT_YIELD_FLAG = 0; \
+                   PT_INIT(pt); return PT_ENDED; }
+
+/** @} */
+
+/**
+ * \name Blocked wait
+ * @{
+ */
+
+/**
+ * Block and wait until condition is true.
+ *
+ * This macro blocks the protothread until the specified condition is
+ * true.
+ *
+ * \param pt A pointer to the protothread control structure.
+ * \param condition The condition.
+ *
+ * \hideinitializer
+ */
+#define PT_WAIT_UNTIL(pt, condition)	        \
+  do {						\
+    LC_SET((pt)->lc);				\
+    if(!(condition)) {				\
+      return PT_WAITING;			\
+    }						\
+  } while(0)
+
+/**
+ * Block and wait while condition is true.
+ *
+ * This function blocks and waits while condition is true. See
+ * PT_WAIT_UNTIL().
+ *
+ * \param pt A pointer to the protothread control structure.
+ * \param cond The condition.
+ *
+ * \hideinitializer
+ */
+#define PT_WAIT_WHILE(pt, cond)  PT_WAIT_UNTIL((pt), !(cond))
+
+/** @} */
+
+/**
+ * \name Hierarchical protothreads
+ * @{
+ */
+
+/**
+ * Block and wait until a child protothread completes.
+ *
+ * This macro schedules a child protothread. The current protothread
+ * will block until the child protothread completes.
+ *
+ * \note The child protothread must be manually initialized with the
+ * PT_INIT() function before this function is used.
+ *
+ * \param pt A pointer to the protothread control structure.
+ * \param thread The child protothread with arguments
+ *
+ * \sa PT_SPAWN()
+ *
+ * \hideinitializer
+ */
+#define PT_WAIT_THREAD(pt, thread) PT_WAIT_WHILE((pt), PT_SCHEDULE(thread))
+
+/**
+ * Spawn a child protothread and wait until it exits.
+ *
+ * This macro spawns a child protothread and waits until it exits. The
+ * macro can only be used within a protothread.
+ *
+ * \param pt A pointer to the protothread control structure.
+ * \param child A pointer to the child protothread's control structure.
+ * \param thread The child protothread with arguments
+ *
+ * \hideinitializer
+ */
+#define PT_SPAWN(pt, child, thread)		\
+  do {						\
+    PT_INIT((child));				\
+    PT_WAIT_THREAD((pt), (thread));		\
+  } while(0)
+
+/** @} */
+
+/**
+ * \name Exiting and restarting
+ * @{
+ */
+
+/**
+ * Restart the protothread.
+ *
+ * This macro will block and cause the running protothread to restart
+ * its execution at the place of the PT_BEGIN() call.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \hideinitializer
+ */
+#define PT_RESTART(pt)				\
+  do {						\
+    PT_INIT(pt);				\
+    return PT_WAITING;			\
+  } while(0)
+
+/**
+ * Exit the protothread.
+ *
+ * This macro causes the protothread to exit. If the protothread was
+ * spawned by another protothread, the parent protothread will become
+ * unblocked and can continue to run.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \hideinitializer
+ */
+#define PT_EXIT(pt)				\
+  do {						\
+    PT_INIT(pt);				\
+    return PT_EXITED;			\
+  } while(0)
+
+/** @} */
+
+/**
+ * \name Calling a protothread
+ * @{
+ */
+
+/**
+ * Schedule a protothread.
+ *
+ * This function shedules a protothread. The return value of the
+ * function is non-zero if the protothread is running or zero if the
+ * protothread has exited.
+ *
+ * \param f The call to the C function implementing the protothread to
+ * be scheduled
+ *
+ * \hideinitializer
+ */
+#define PT_SCHEDULE(f) ((f) == PT_WAITING)
+
+/** @} */
+
+/**
+ * \name Yielding from a protothread
+ * @{
+ */
+
+/**
+ * Yield from the current protothread.
+ *
+ * This function will yield the protothread, thereby allowing other
+ * processing to take place in the system.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \hideinitializer
+ */
+#define PT_YIELD(pt)				\
+  do {						\
+    PT_YIELD_FLAG = 0;				\
+    LC_SET((pt)->lc);				\
+    if(PT_YIELD_FLAG == 0) {			\
+      return PT_YIELDED;			\
+    }						\
+  } while(0)
+
+/**
+ * \brief      Yield from the protothread until a condition occurs.
+ * \param pt   A pointer to the protothread control structure.
+ * \param cond The condition.
+ *
+ *             This function will yield the protothread, until the
+ *             specified condition evaluates to true.
+ *
+ *
+ * \hideinitializer
+ */
+#define PT_YIELD_UNTIL(pt, cond)		\
+  do {						\
+    PT_YIELD_FLAG = 0;				\
+    LC_SET((pt)->lc);				\
+    if((PT_YIELD_FLAG == 0) || !(cond)) {	\
+      return PT_YIELDED;			\
+    }						\
+  } while(0)
+
+/** @} */
+
+#endif /* __PT_H__ */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/timer.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/timer.c
new file mode 100644
index 0000000..9a63653
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/timer.c
@@ -0,0 +1,130 @@
+/**
+ * \addtogroup timer
+ * @{
+ */
+
+/**
+ * \file
+ * Timer library implementation.
+ * \author
+ * Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2004, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: timer.c,v 1.2 2006/06/12 08:00:30 adam Exp $
+ */
+#include "clock.h"
+#include "uip_timer.h"
+
+/*---------------------------------------------------------------------------*/
+
+/**
+ * Set a timer.
+ *
+ * This function is used to set a timer for a time sometime in the
+ * future. The function timer_expired() will evaluate to true after
+ * the timer has expired.
+ *
+ * \param t A pointer to the timer
+ * \param interval The interval before the timer expires.
+ *
+ */
+void timer_set( struct timer *t, clock_time_t interval )
+{
+	t->interval = interval;
+	t->start = clock_time();
+}
+
+/*---------------------------------------------------------------------------*/
+
+/**
+ * Reset the timer with the same interval.
+ *
+ * This function resets the timer with the same interval that was
+ * given to the timer_set() function. The start point of the interval
+ * is the exact time that the timer last expired. Therefore, this
+ * function will cause the timer to be stable over time, unlike the
+ * timer_rester() function.
+ *
+ * \param t A pointer to the timer.
+ *
+ * \sa timer_restart()
+ */
+void timer_reset( struct timer *t )
+{
+	t->start += t->interval;
+}
+
+/*---------------------------------------------------------------------------*/
+
+/**
+ * Restart the timer from the current point in time
+ *
+ * This function restarts a timer with the same interval that was
+ * given to the timer_set() function. The timer will start at the
+ * current time.
+ *
+ * \note A periodic timer will drift if this function is used to reset
+ * it. For preioric timers, use the timer_reset() function instead.
+ *
+ * \param t A pointer to the timer.
+ *
+ * \sa timer_reset()
+ */
+void timer_restart( struct timer *t )
+{
+	t->start = clock_time();
+}
+
+/*---------------------------------------------------------------------------*/
+
+/**
+ * Check if a timer has expired.
+ *
+ * This function tests if a timer has expired and returns true or
+ * false depending on its status.
+ *
+ * \param t A pointer to the timer
+ *
+ * \return Non-zero if the timer has expired, zero otherwise.
+ *
+ */
+int timer_expired( struct timer *t )
+{
+	return( clock_time_t ) ( clock_time() - t->start ) >= ( clock_time_t ) t->interval;
+}
+
+/*---------------------------------------------------------------------------*/
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/timer.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/timer.h
new file mode 100644
index 0000000..e28e3ca
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/timer.h
@@ -0,0 +1,86 @@
+/**
+ * \defgroup timer Timer library
+ *
+ * The timer library provides functions for setting, resetting and
+ * restarting timers, and for checking if a timer has expired. An
+ * application must "manually" check if its timers have expired; this
+ * is not done automatically.
+ *
+ * A timer is declared as a \c struct \c timer and all access to the
+ * timer is made by a pointer to the declared timer.
+ *
+ * \note The timer library uses the \ref clock "Clock library" to
+ * measure time. Intervals should be specified in the format used by
+ * the clock library.
+ *
+ * @{
+ */
+
+
+/**
+ * \file
+ * Timer library header file.
+ * \author
+ * Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2004, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: timer.h,v 1.3 2006/06/11 21:46:39 adam Exp $
+ */
+#ifndef __TIMER_H__
+#define __TIMER_H__
+
+#include "clock.h"
+
+/**
+ * A timer.
+ *
+ * This structure is used for declaring a timer. The timer must be set
+ * with timer_set() before it can be used.
+ *
+ * \hideinitializer
+ */
+struct timer {
+  clock_time_t start;
+  clock_time_t interval;
+};
+
+void timer_set(struct timer *t, clock_time_t interval);
+void timer_reset(struct timer *t);
+void timer_restart(struct timer *t);
+int timer_expired(struct timer *t);
+
+#endif /* __TIMER_H__ */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-fw.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-fw.h
new file mode 100644
index 0000000..e854ece
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-fw.h
@@ -0,0 +1,176 @@
+/**
+ * \addtogroup uipfw
+ * @{
+ */
+
+/**
+ * \file
+ * uIP packet forwarding header file.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2004, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: uip-fw.h,v 1.2 2006/06/12 08:00:30 adam Exp $
+ */
+#ifndef __UIP_FW_H__
+#define __UIP_FW_H__
+
+#include "uip.h"
+
+/**
+ * Representation of a uIP network interface.
+ */
+struct uip_fw_netif {
+  struct uip_fw_netif *next;  /**< Pointer to the next interface when
+				 linked in a list. */
+  u16_t ipaddr[2];            /**< The IP address of this interface. */
+  u16_t netmask[2];           /**< The netmask of the interface. */
+  u8_t (* output)(void);
+                              /**< A pointer to the function that
+				 sends a packet. */
+};
+
+/**
+ * Intantiating macro for a uIP network interface.
+ *
+ * Example:
+ \code
+ struct uip_fw_netif slipnetif =
+   {UIP_FW_NETIF(192,168,76,1, 255,255,255,0, slip_output)};
+ \endcode
+ * \param ip1,ip2,ip3,ip4 The IP address of the network interface.
+ *
+ * \param nm1,nm2,nm3,nm4 The netmask of the network interface.
+ *
+ * \param outputfunc A pointer to the output function of the network interface.
+ *
+ * \hideinitializer
+ */
+#define UIP_FW_NETIF(ip1,ip2,ip3,ip4, nm1,nm2,nm3,nm4, outputfunc) \
+        NULL, \
+	{HTONS((ip1 << 8) | ip2), HTONS((ip3 << 8) | ip4)}, \
+	{HTONS((nm1 << 8) | nm2), HTONS((nm3 << 8) | nm4)}, \
+        outputfunc
+
+/**
+ * Set the IP address of a network interface.
+ *
+ * \param netif A pointer to the uip_fw_netif structure for the network interface.
+ *
+ * \param addr A pointer to an IP address.
+ *
+ * \hideinitializer
+ */
+#define uip_fw_setipaddr(netif, addr) \
+        do { (netif)->ipaddr[0] = ((u16_t *)(addr))[0]; \
+             (netif)->ipaddr[1] = ((u16_t *)(addr))[1]; } while(0)
+/**
+ * Set the netmask of a network interface.
+ *
+ * \param netif A pointer to the uip_fw_netif structure for the network interface.
+ *
+ * \param addr A pointer to an IP address representing the netmask.
+ *
+ * \hideinitializer
+ */
+#define uip_fw_setnetmask(netif, addr) \
+        do { (netif)->netmask[0] = ((u16_t *)(addr))[0]; \
+             (netif)->netmask[1] = ((u16_t *)(addr))[1]; } while(0)
+
+void uip_fw_init(void);
+u8_t uip_fw_forward(void);
+u8_t uip_fw_output(void);
+void uip_fw_register(struct uip_fw_netif *netif);
+void uip_fw_default(struct uip_fw_netif *netif);
+void uip_fw_periodic(void);
+
+
+/**
+ * A non-error message that indicates that a packet should be
+ * processed locally.
+ *
+ * \hideinitializer
+ */
+#define UIP_FW_LOCAL     0
+
+/**
+ * A non-error message that indicates that something went OK.
+ *
+ * \hideinitializer
+ */
+#define UIP_FW_OK        0
+
+/**
+ * A non-error message that indicates that a packet was forwarded.
+ *
+ * \hideinitializer
+ */
+#define UIP_FW_FORWARDED 1
+
+/**
+ * A non-error message that indicates that a zero-length packet
+ * transmission was attempted, and that no packet was sent.
+ *
+ * \hideinitializer
+ */
+#define UIP_FW_ZEROLEN   2
+
+/**
+ * An error message that indicates that a packet that was too large
+ * for the outbound network interface was detected.
+ *
+ * \hideinitializer
+ */
+#define UIP_FW_TOOLARGE  3
+
+/**
+ * An error message that indicates that no suitable interface could be
+ * found for an outbound packet.
+ *
+ * \hideinitializer
+ */
+#define UIP_FW_NOROUTE   4
+
+/**
+ * An error message that indicates that a packet that should be
+ * forwarded or output was dropped.
+ *
+ * \hideinitializer
+ */
+#define UIP_FW_DROPPED   5
+
+
+#endif /* __UIP_FW_H__ */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-neighbor.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-neighbor.h
new file mode 100644
index 0000000..aca096f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-neighbor.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2006, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * $Id: uip-neighbor.h,v 1.2 2006/06/12 08:00:30 adam Exp $
+ */
+
+/**
+ * \file
+ *         Header file for database of link-local neighbors, used by
+ *         IPv6 code and to be used by future ARP code.
+ * \author
+ *         Adam Dunkels 
+ */
+
+#ifndef __UIP_NEIGHBOR_H__
+#define __UIP_NEIGHBOR_H__
+
+#include "uip.h"
+
+struct uip_neighbor_addr {
+#if UIP_NEIGHBOR_CONF_ADDRTYPE
+  UIP_NEIGHBOR_CONF_ADDRTYPE addr;
+#else
+  struct uip_eth_addr addr;
+#endif
+};
+
+void uip_neighbor_init(void);
+void uip_neighbor_add(uip_ipaddr_t ipaddr, struct uip_neighbor_addr *addr);
+void uip_neighbor_update(uip_ipaddr_t ipaddr);
+struct uip_neighbor_addr *uip_neighbor_lookup(uip_ipaddr_t ipaddr);
+void uip_neighbor_periodic(void);
+
+#endif /* __UIP-NEIGHBOR_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-split.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-split.c
new file mode 100644
index 0000000..6828f3c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-split.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2004, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: uip-split.c,v 1.2 2006/06/12 08:00:30 adam Exp $
+ */
+#include 
+
+#include "uip-split.h"
+#include "uip.h"
+#include "uip-fw.h"
+#include "uip_arch.h"
+
+#define BUF ( ( struct uip_tcpip_hdr * ) &uip_buf[UIP_LLH_LEN] )
+
+/*-----------------------------------------------------------------------------*/
+void uip_split_output( void )
+{
+	u16_t	tcplen, len1, len2;
+
+	/* We only try to split maximum sized TCP segments. */
+	if( BUF->proto == UIP_PROTO_TCP && uip_len == UIP_BUFSIZE - UIP_LLH_LEN )
+	{
+		tcplen = uip_len - UIP_TCPIP_HLEN;
+
+		/* Split the segment in two. If the original packet length was
+       odd, we make the second packet one byte larger. */
+		len1 = len2 = tcplen / 2;
+		if( len1 + len2 < tcplen )
+		{
+			++len2;
+		}
+
+		/* Create the first packet. This is done by altering the length
+       field of the IP header and updating the checksums. */
+		uip_len = len1 + UIP_TCPIP_HLEN;
+		#if UIP_CONF_IPV6
+
+		/* For IPv6, the IP length field does not include the IPv6 IP header
+       length. */
+		BUF->len[0] = ( (uip_len - UIP_IPH_LEN) >> 8 );
+		BUF->len[1] = ( (uip_len - UIP_IPH_LEN) & 0xff );
+		#else /* UIP_CONF_IPV6 */
+		BUF->len[0] = uip_len >> 8;
+		BUF->len[1] = uip_len & 0xff;
+		#endif /* UIP_CONF_IPV6 */
+
+		/* Recalculate the TCP checksum. */
+		BUF->tcpchksum = 0;
+		BUF->tcpchksum = ~( uip_tcpchksum() );
+
+		#if !UIP_CONF_IPV6
+
+		/* Recalculate the IP checksum. */
+		BUF->ipchksum = 0;
+		BUF->ipchksum = ~( uip_ipchksum() );
+		#endif /* UIP_CONF_IPV6 */
+
+		/* Transmit the first packet. */
+
+		/*    uip_fw_output();*/
+
+		//    tcpip_output();
+
+		/* Now, create the second packet. To do this, it is not enough to
+       just alter the length field, but we must also update the TCP
+       sequence number and point the uip_appdata to a new place in
+       memory. This place is detemined by the length of the first
+       packet (len1). */
+		uip_len = len2 + UIP_TCPIP_HLEN;
+		#if UIP_CONF_IPV6
+
+		/* For IPv6, the IP length field does not include the IPv6 IP header
+       length. */
+		BUF->len[0] = ( (uip_len - UIP_IPH_LEN) >> 8 );
+		BUF->len[1] = ( (uip_len - UIP_IPH_LEN) & 0xff );
+		#else /* UIP_CONF_IPV6 */
+		BUF->len[0] = uip_len >> 8;
+		BUF->len[1] = uip_len & 0xff;
+		#endif /* UIP_CONF_IPV6 */
+
+		/*    uip_appdata += len1;*/
+		memcpy( uip_appdata, ( u8_t * ) uip_appdata + len1, len2 );
+
+		uip_add32( BUF->seqno, len1 );
+		BUF->seqno[0] = uip_acc32[0];
+		BUF->seqno[1] = uip_acc32[1];
+		BUF->seqno[2] = uip_acc32[2];
+		BUF->seqno[3] = uip_acc32[3];
+
+		/* Recalculate the TCP checksum. */
+		BUF->tcpchksum = 0;
+		BUF->tcpchksum = ~( uip_tcpchksum() );
+
+		#if !UIP_CONF_IPV6
+
+		/* Recalculate the IP checksum. */
+		BUF->ipchksum = 0;
+		BUF->ipchksum = ~( uip_ipchksum() );
+		#endif /* UIP_CONF_IPV6 */
+
+		/* Transmit the second packet. */
+
+		/*    uip_fw_output();*/
+
+		//    tcpip_output();
+	}
+	else
+	{
+		/*    uip_fw_output();*/
+
+		//    tcpip_output();
+	}
+}
+
+/*-----------------------------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-split.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-split.h
new file mode 100644
index 0000000..446e192
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip-split.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2004, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: uip-split.h,v 1.2 2006/06/12 08:00:30 adam Exp $
+ */
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \defgroup uipsplit uIP TCP throughput booster hack
+ * @{
+ *
+ * The basic uIP TCP implementation only allows each TCP connection to
+ * have a single TCP segment in flight at any given time. Because of
+ * the delayed ACK algorithm employed by most TCP receivers, uIP's
+ * limit on the amount of in-flight TCP segments seriously reduces the
+ * maximum achievable throughput for sending data from uIP.
+ *
+ * The uip-split module is a hack which tries to remedy this
+ * situation. By splitting maximum sized outgoing TCP segments into
+ * two, the delayed ACK algorithm is not invoked at TCP
+ * receivers. This improves the throughput when sending data from uIP
+ * by orders of magnitude.
+ *
+ * The uip-split module uses the uip-fw module (uIP IP packet
+ * forwarding) for sending packets. Therefore, the uip-fw module must
+ * be set up with the appropriate network interfaces for this module
+ * to work.
+ */
+
+
+/**
+ * \file
+ * Module for splitting outbound TCP segments in two to avoid the
+ * delayed ACK throughput degradation.
+ * \author
+ * Adam Dunkels 
+ *
+ */
+
+#ifndef __UIP_SPLIT_H__
+#define __UIP_SPLIT_H__
+
+/**
+ * Handle outgoing packets.
+ *
+ * This function inspects an outgoing packet in the uip_buf buffer and
+ * sends it out using the uip_fw_output() function. If the packet is a
+ * full-sized TCP segment it will be split into two segments and
+ * transmitted separately. This function should be called instead of
+ * the actual device driver output function, or the uip_fw_output()
+ * function.
+ *
+ * The headers of the outgoing packet is assumed to be in the uip_buf
+ * buffer and the payload is assumed to be wherever uip_appdata
+ * points. The length of the outgoing packet is assumed to be in the
+ * uip_len variable.
+ *
+ */
+void uip_split_output(void);
+
+#endif /* __UIP_SPLIT_H__ */
+
+/** @} */
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip.c
new file mode 100644
index 0000000..1c07f35
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip.c
@@ -0,0 +1,2233 @@
+#define DEBUG_PRINTF( ... )		/*printf(__VA_ARGS__)*/
+
+/**
+ * \defgroup uip The uIP TCP/IP stack
+ * @{
+ *
+ * uIP is an implementation of the TCP/IP protocol stack intended for
+ * small 8-bit and 16-bit microcontrollers.
+ *
+ * uIP provides the necessary protocols for Internet communication,
+ * with a very small code footprint and RAM requirements - the uIP
+ * code size is on the order of a few kilobytes and RAM usage is on
+ * the order of a few hundred bytes.
+ */
+
+/**
+ * \file
+ * The uIP TCP/IP stack code.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip.c,v 1.65 2006/06/11 21:46:39 adam Exp $
+ *
+ */
+
+/*
+ * uIP is a small implementation of the IP, UDP and TCP protocols (as
+ * well as some basic ICMP stuff). The implementation couples the IP,
+ * UDP, TCP and the application layers very tightly. To keep the size
+ * of the compiled code down, this code frequently uses the goto
+ * statement. While it would be possible to break the uip_process()
+ * function into many smaller functions, this would increase the code
+ * size because of the overhead of parameter passing and the fact that
+ * the optimier would not be as efficient.
+ *
+ * The principle is that we have a small buffer, called the uip_buf,
+ * in which the device driver puts an incoming packet. The TCP/IP
+ * stack parses the headers in the packet, and calls the
+ * application. If the remote host has sent data to the application,
+ * this data is present in the uip_buf and the application read the
+ * data from there. It is up to the application to put this data into
+ * a byte stream if needed. The application will not be fed with data
+ * that is out of sequence.
+ *
+ * If the application whishes to send data to the peer, it should put
+ * its data into the uip_buf. The uip_appdata pointer points to the
+ * first available byte. The TCP/IP stack will calculate the
+ * checksums, and fill in the necessary header fields and finally send
+ * the packet back to the peer.
+*/
+#include "uip.h"
+#include "uipopt.h"
+#include "uip_arch.h"
+#include "uip_arp.h"
+#include "FreeRTOS.h"
+
+#if UIP_CONF_IPV6
+	#include "uip-neighbor.h"
+#endif /* UIP_CONF_IPV6 */
+
+#include 
+
+/*---------------------------------------------------------------------------*/
+
+/* Variable definitions. */
+
+/* The IP address of this host. If it is defined to be fixed (by
+   setting UIP_FIXEDADDR to 1 in uipopt.h), the address is set
+   here. Otherwise, the address */
+#if UIP_FIXEDADDR > 0
+const uip_ipaddr_t			uip_hostaddr = { HTONS( (UIP_IPADDR0 << 8) | UIP_IPADDR1 ), HTONS( (UIP_IPADDR2 << 8) | UIP_IPADDR3 ) };
+const uip_ipaddr_t			uip_draddr = { HTONS( (UIP_DRIPADDR0 << 8) | UIP_DRIPADDR1 ), HTONS( (UIP_DRIPADDR2 << 8) | UIP_DRIPADDR3 ) };
+const uip_ipaddr_t			uip_netmask = { HTONS( (UIP_NETMASK0 << 8) | UIP_NETMASK1 ), HTONS( (UIP_NETMASK2 << 8) | UIP_NETMASK3 ) };
+#else
+uip_ipaddr_t				uip_hostaddr, uip_draddr, uip_netmask;
+#endif /* UIP_FIXEDADDR */
+
+static const uip_ipaddr_t	all_ones_addr =
+#if UIP_CONF_IPV6
+{ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff };
+#else /* UIP_CONF_IPV6 */
+{
+	0xffff, 0xffff
+};
+#endif /* UIP_CONF_IPV6 */
+static const uip_ipaddr_t	all_zeroes_addr =
+#if UIP_CONF_IPV6
+{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 };
+#else /* UIP_CONF_IPV6 */
+{
+	0x0000, 0x0000
+};
+#endif /* UIP_CONF_IPV6 */
+
+#if UIP_FIXEDETHADDR
+const struct uip_eth_addr	uip_ethaddr = { { UIP_ETHADDR0, UIP_ETHADDR1, UIP_ETHADDR2, UIP_ETHADDR3, UIP_ETHADDR4, UIP_ETHADDR5 } };
+#else
+struct uip_eth_addr			uip_ethaddr = { { 0, 0, 0, 0, 0, 0 } };
+#endif
+#ifndef UIP_CONF_EXTERNAL_BUFFER
+	#ifdef __ICCARM__
+		#pragma data_alignment = 4
+u8_t uip_buf[UIP_BUFSIZE + 2];	/* The packet buffer that contains incoming packets. */
+	#else
+u8_t				uip_buf[UIP_BUFSIZE + 2] ALIGN_STRUCT_END;	/* The packet buffer that contains incoming packets. */
+	#endif
+#endif /* UIP_CONF_EXTERNAL_BUFFER */
+
+void				*uip_appdata;				/* The uip_appdata pointer points to
+				    application data. */
+void				*uip_sappdata;				/* The uip_appdata pointer points to
+				    the application data which is to
+				    be sent. */
+#if UIP_URGDATA > 0
+void				*uip_urgdata;				/* The uip_urgdata pointer points to
+   				    urgent data (out-of-band data), if
+   				    present. */
+u16_t				uip_urglen, uip_surglen;
+#endif /* UIP_URGDATA > 0 */
+
+u16_t				uip_len, uip_slen;
+
+/* The uip_len is either 8 or 16 bits,
+				depending on the maximum packet
+				size. */
+u8_t				uip_flags;					/* The uip_flags variable is used for
+				communication between the TCP/IP stack
+				and the application program. */
+struct uip_conn		*uip_conn;					/* uip_conn always points to the current
+				connection. */
+
+struct uip_conn		uip_conns[UIP_CONNS];
+
+/* The uip_conns array holds all TCP
+				connections. */
+u16_t				uip_listenports[UIP_LISTENPORTS];
+
+/* The uip_listenports list all currently
+				listning ports. */
+#if UIP_UDP
+struct uip_udp_conn *uip_udp_conn;
+struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS];
+#endif /* UIP_UDP */
+
+static u16_t		ipid;						/* Ths ipid variable is an increasing
+				number that is used for the IP ID
+				field. */
+
+void uip_setipid( u16_t id )
+{
+	ipid = id;
+}
+
+static u8_t		iss[4];							/* The iss variable is used for the TCP
+				initial sequence number. */
+
+#if UIP_ACTIVE_OPEN
+static u16_t	lastport;						/* Keeps track of the last port used for
+				a new connection. */
+#endif /* UIP_ACTIVE_OPEN */
+
+/* Temporary variables. */
+u8_t			uip_acc32[4];
+static u8_t		c, opt;
+static u16_t	tmp16;
+
+/* Structures and definitions. */
+#define TCP_FIN								0x01
+#define TCP_SYN								0x02
+#define TCP_RST								0x04
+#define TCP_PSH								0x08
+#define TCP_ACK								0x10
+#define TCP_URG								0x20
+#define TCP_CTL								0x3f
+
+#define TCP_OPT_END							0	/* End of TCP options list */
+#define TCP_OPT_NOOP						1	/* "No-operation" TCP option */
+#define TCP_OPT_MSS							2	/* Maximum segment size TCP option */
+
+#define TCP_OPT_MSS_LEN						4	/* Length of TCP MSS option. */
+
+#define ICMP_ECHO_REPLY						0
+#define ICMP_ECHO							8
+
+#define ICMP6_ECHO_REPLY					129
+#define ICMP6_ECHO							128
+#define ICMP6_NEIGHBOR_SOLICITATION			135
+#define ICMP6_NEIGHBOR_ADVERTISEMENT		136
+
+#define ICMP6_FLAG_S						( 1 << 6 )
+#define ICMP6_OPTION_SOURCE_LINK_ADDRESS	1
+#define ICMP6_OPTION_TARGET_LINK_ADDRESS	2
+
+/* Macros. */
+#define BUF		( ( struct uip_tcpip_hdr * ) &uip_buf[UIP_LLH_LEN] )
+#define FBUF	( ( struct uip_tcpip_hdr * ) &uip_reassbuf[0] )
+#define ICMPBUF ( ( struct uip_icmpip_hdr * ) &uip_buf[UIP_LLH_LEN] )
+#define UDPBUF	( ( struct uip_udpip_hdr * ) &uip_buf[UIP_LLH_LEN] )
+#if UIP_STATISTICS == 1
+struct uip_stats	uip_stat;
+	#define UIP_STAT( s )	s
+#else
+	#define UIP_STAT( s )
+#endif /* UIP_STATISTICS == 1 */
+
+#if UIP_LOGGING == 1
+	#include 
+void	uip_log( char *msg );
+	#define UIP_LOG( m )	uip_log( m )
+#else
+	#define UIP_LOG( m )
+#endif /* UIP_LOGGING == 1 */
+
+#if !UIP_ARCH_ADD32
+void uip_add32( u8_t *op32, u16_t op16 )
+{
+	uip_acc32[3] = op32[3] + ( op16 & 0xff );
+	uip_acc32[2] = op32[2] + ( op16 >> 8 );
+	uip_acc32[1] = op32[1];
+	uip_acc32[0] = op32[0];
+
+	if( uip_acc32[2] < (op16 >> 8) )
+	{
+		++uip_acc32[1];
+		if( uip_acc32[1] == 0 )
+		{
+			++uip_acc32[0];
+		}
+	}
+
+	if( uip_acc32[3] < (op16 & 0xff) )
+	{
+		++uip_acc32[2];
+		if( uip_acc32[2] == 0 )
+		{
+			++uip_acc32[1];
+			if( uip_acc32[1] == 0 )
+			{
+				++uip_acc32[0];
+			}
+		}
+	}
+}
+
+#endif /* UIP_ARCH_ADD32 */
+
+#if !UIP_ARCH_CHKSUM
+
+/*---------------------------------------------------------------------------*/
+static u16_t chksum( u16_t sum, const u8_t *data, u16_t len )
+{
+	u16_t		t;
+	const u8_t	*dataptr;
+	const u8_t	*last_byte;
+
+	dataptr = data;
+	last_byte = data + len - 1;
+
+	while( dataptr < last_byte )
+	{				/* At least two more bytes */
+		t = ( dataptr[0] << 8 ) + dataptr[1];
+		sum += t;
+		if( sum < t )
+		{
+			sum++;	/* carry */
+		}
+
+		dataptr += 2;
+	}
+
+	if( dataptr == last_byte )
+	{
+		t = ( dataptr[0] << 8 ) + 0;
+		sum += t;
+		if( sum < t )
+		{
+			sum++;	/* carry */
+		}
+	}
+
+	/* Return sum in host byte order. */
+	return sum;
+}
+
+/*---------------------------------------------------------------------------*/
+u16_t uip_chksum( u16_t *data, u16_t len )
+{
+	return htons( chksum(0, ( u8_t * ) data, len) );
+}
+
+/*---------------------------------------------------------------------------*/
+	#ifndef UIP_ARCH_IPCHKSUM
+u16_t uip_ipchksum( void )
+{
+	u16_t	sum;
+
+	sum = chksum( 0, &uip_buf[UIP_LLH_LEN], UIP_IPH_LEN );
+	DEBUG_PRINTF( "uip_ipchksum: sum 0x%04x\n", sum );
+	return( sum == 0 ) ? 0xffff : htons( sum );
+}
+
+	#endif
+
+/*---------------------------------------------------------------------------*/
+static u16_t upper_layer_chksum( u8_t proto )
+{
+	u16_t	upper_layer_len;
+	u16_t	sum;
+
+		#if UIP_CONF_IPV6
+	upper_layer_len = ( ((u16_t) (BUF->len[0]) << 8) + BUF->len[1] );
+		#else /* UIP_CONF_IPV6 */
+	upper_layer_len = ( ((u16_t) (BUF->len[0]) << 8) + BUF->len[1] ) - UIP_IPH_LEN;
+		#endif /* UIP_CONF_IPV6 */
+
+	/* First sum pseudoheader. */
+
+	/* IP protocol and length fields. This addition cannot carry. */
+	sum = upper_layer_len + proto;
+
+	/* Sum IP source and destination addresses. */
+	sum = chksum( sum, ( u8_t * ) &BUF->srcipaddr[0], 2 * sizeof(uip_ipaddr_t) );
+
+	/* Sum TCP header and data. */
+	sum = chksum( sum, &uip_buf[UIP_IPH_LEN + UIP_LLH_LEN], upper_layer_len );
+
+	return( sum == 0 ) ? 0xffff : htons( sum );
+}
+
+/*---------------------------------------------------------------------------*/
+	#if UIP_CONF_IPV6
+u16_t uip_icmp6chksum( void )
+{
+	return upper_layer_chksum( UIP_PROTO_ICMP6 );
+}
+
+	#endif /* UIP_CONF_IPV6 */
+
+/*---------------------------------------------------------------------------*/
+u16_t uip_tcpchksum( void )
+{
+	return upper_layer_chksum( UIP_PROTO_TCP );
+}
+
+/*---------------------------------------------------------------------------*/
+	#if UIP_UDP_CHECKSUMS
+u16_t uip_udpchksum( void )
+{
+	return upper_layer_chksum( UIP_PROTO_UDP );
+}
+
+	#endif /* UIP_UDP_CHECKSUMS */
+#endif /* UIP_ARCH_CHKSUM */
+
+/*---------------------------------------------------------------------------*/
+void uip_init( void )
+{
+	for( c = 0; c < UIP_LISTENPORTS; ++c )
+	{
+		uip_listenports[c] = 0;
+	}
+
+	for( c = 0; c < UIP_CONNS; ++c )
+	{
+		uip_conns[c].tcpstateflags = UIP_CLOSED;
+	}
+
+	#if UIP_ACTIVE_OPEN
+	lastport = 1024;
+	#endif /* UIP_ACTIVE_OPEN */
+
+	#if UIP_UDP
+	for( c = 0; c < UIP_UDP_CONNS; ++c )
+	{
+		uip_udp_conns[c].lport = 0;
+	}
+
+	#endif /* UIP_UDP */
+
+	/* IPv4 initialization. */
+	#if UIP_FIXEDADDR == 0
+
+	/*  uip_hostaddr[0] = uip_hostaddr[1] = 0;*/
+	#endif /* UIP_FIXEDADDR */
+}
+
+/*---------------------------------------------------------------------------*/
+#if UIP_ACTIVE_OPEN
+struct uip_conn *uip_connect( uip_ipaddr_t *ripaddr, u16_t rport )
+{
+	register struct uip_conn	*conn, *cconn;
+
+	/* Find an unused local port. */
+again:
+	++lastport;
+
+	if( lastport >= 32000 )
+	{
+		lastport = 4096;
+	}
+
+	/* Check if this port is already in use, and if so try to find
+     another one. */
+	for( c = 0; c < UIP_CONNS; ++c )
+	{
+		conn = &uip_conns[c];
+		if( conn->tcpstateflags != UIP_CLOSED && conn->lport == htons(lastport) )
+		{
+			goto again;
+		}
+	}
+
+	conn = 0;
+	for( c = 0; c < UIP_CONNS; ++c )
+	{
+		cconn = &uip_conns[c];
+		if( cconn->tcpstateflags == UIP_CLOSED )
+		{
+			conn = cconn;
+			break;
+		}
+
+		if( cconn->tcpstateflags == UIP_TIME_WAIT )
+		{
+			if( conn == 0 || cconn->timer > conn->timer )
+			{
+				conn = cconn;
+			}
+		}
+	}
+
+	if( conn == 0 )
+	{
+		return 0;
+	}
+
+	conn->tcpstateflags = UIP_SYN_SENT;
+
+	conn->snd_nxt[0] = iss[0];
+	conn->snd_nxt[1] = iss[1];
+	conn->snd_nxt[2] = iss[2];
+	conn->snd_nxt[3] = iss[3];
+
+	conn->initialmss = conn->mss = UIP_TCP_MSS;
+
+	conn->len = 1;		/* TCP length of the SYN is one. */
+	conn->nrtx = 0;
+	conn->timer = 1;	/* Send the SYN next time around. */
+	conn->rto = UIP_RTO;
+	conn->sa = 0;
+	conn->sv = 16;		/* Initial value of the RTT variance. */
+	conn->lport = htons( lastport );
+	conn->rport = rport;
+	uip_ipaddr_copy( &conn->ripaddr, ripaddr );
+
+	return conn;
+}
+
+#endif /* UIP_ACTIVE_OPEN */
+
+/*---------------------------------------------------------------------------*/
+#if UIP_UDP
+struct uip_udp_conn *uip_udp_new( uip_ipaddr_t *ripaddr, u16_t rport )
+{
+	register struct uip_udp_conn	*conn;
+
+	/* Find an unused local port. */
+again:
+	++lastport;
+
+	if( lastport >= 32000 )
+	{
+		lastport = 4096;
+	}
+
+	for( c = 0; c < UIP_UDP_CONNS; ++c )
+	{
+		if( uip_udp_conns[c].lport == htons(lastport) )
+		{
+			goto again;
+		}
+	}
+
+	conn = 0;
+	for( c = 0; c < UIP_UDP_CONNS; ++c )
+	{
+		if( uip_udp_conns[c].lport == 0 )
+		{
+			conn = &uip_udp_conns[c];
+			break;
+		}
+	}
+
+	if( conn == 0 )
+	{
+		return 0;
+	}
+
+	conn->lport = HTONS( lastport );
+	conn->rport = rport;
+	if( ripaddr == NULL )
+	{
+		memset( conn->ripaddr, 0, sizeof(uip_ipaddr_t) );
+	}
+	else
+	{
+		uip_ipaddr_copy( &conn->ripaddr, ripaddr );
+	}
+
+	conn->ttl = UIP_TTL;
+
+	return conn;
+}
+
+#endif /* UIP_UDP */
+
+/*---------------------------------------------------------------------------*/
+void uip_unlisten( u16_t port )
+{
+	for( c = 0; c < UIP_LISTENPORTS; ++c )
+	{
+		if( uip_listenports[c] == port )
+		{
+			uip_listenports[c] = 0;
+			return;
+		}
+	}
+}
+
+/*---------------------------------------------------------------------------*/
+void uip_listen( u16_t port )
+{
+	for( c = 0; c < UIP_LISTENPORTS; ++c )
+	{
+		if( uip_listenports[c] == 0 )
+		{
+			uip_listenports[c] = port;
+			return;
+		}
+	}
+}
+
+/*---------------------------------------------------------------------------*/
+
+/* XXX: IP fragment reassembly: not well-tested. */
+#if UIP_REASSEMBLY && !UIP_CONF_IPV6
+	#define UIP_REASS_BUFSIZE	( UIP_BUFSIZE - UIP_LLH_LEN )
+static u8_t			uip_reassbuf[UIP_REASS_BUFSIZE];
+static u8_t			uip_reassbitmap[UIP_REASS_BUFSIZE / ( 8 * 8 )];
+static const u8_t	bitmap_bits[8] = { 0xff, 0x7f, 0x3f, 0x1f, 0x0f, 0x07, 0x03, 0x01 };
+static u16_t		uip_reasslen;
+static u8_t			uip_reassflags;
+	#define UIP_REASS_FLAG_LASTFRAG 0x01
+static u8_t			uip_reasstmr;
+
+	#define IP_MF	0x20
+
+static u8_t uip_reass( void )
+{
+	u16_t	offset, len;
+	u16_t	i;
+
+	/* If ip_reasstmr is zero, no packet is present in the buffer, so we
+     write the IP header of the fragment into the reassembly
+     buffer. The timer is updated with the maximum age. */
+	if( uip_reasstmr == 0 )
+	{
+		memcpy( uip_reassbuf, &BUF->vhl, UIP_IPH_LEN );
+		uip_reasstmr = UIP_REASS_MAXAGE;
+		uip_reassflags = 0;
+
+		/* Clear the bitmap. */
+		memset( uip_reassbitmap, 0, sizeof(uip_reassbitmap) );
+	}
+
+	/* Check if the incoming fragment matches the one currently present
+     in the reasembly buffer. If so, we proceed with copying the
+     fragment into the buffer. */
+	if
+	(
+		BUF->srcipaddr[0] == FBUF->srcipaddr[0] &&
+		BUF->srcipaddr[1] == FBUF->srcipaddr[1] &&
+		BUF->destipaddr[0] == FBUF->destipaddr[0] &&
+		BUF->destipaddr[1] == FBUF->destipaddr[1] &&
+		BUF->ipid[0] == FBUF->ipid[0] &&
+		BUF->ipid[1] == FBUF->ipid[1]
+	)
+	{
+		len = ( BUF->len[0] << 8 ) + BUF->len[1] - ( BUF->vhl & 0x0f ) * 4;
+		offset = ( ((BUF->ipoffset[0] & 0x3f) << 8) + BUF->ipoffset[1] ) * 8;
+
+		/* If the offset or the offset + fragment length overflows the
+       reassembly buffer, we discard the entire packet. */
+		if( offset > UIP_REASS_BUFSIZE || offset + len > UIP_REASS_BUFSIZE )
+		{
+			uip_reasstmr = 0;
+			goto nullreturn;
+		}
+
+		/* Copy the fragment into the reassembly buffer, at the right
+       offset. */
+		memcpy( &uip_reassbuf[UIP_IPH_LEN + offset], ( char * ) BUF + ( int ) ((BUF->vhl & 0x0f) * 4), len );
+
+		/* Update the bitmap. */
+		if( offset / (8 * 8) == (offset + len) / (8 * 8) )
+		{
+			/* If the two endpoints are in the same byte, we only update
+	 that byte. */
+			uip_reassbitmap[offset / ( 8 * 8 )] |= bitmap_bits[( offset / 8 ) & 7] &~bitmap_bits[( (offset + len) / 8 ) & 7];
+		}
+		else
+		{
+			/* If the two endpoints are in different bytes, we update the
+	 bytes in the endpoints and fill the stuff inbetween with
+	 0xff. */
+			uip_reassbitmap[offset / ( 8 * 8 )] |= bitmap_bits[( offset / 8 ) & 7];
+			for( i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i )
+			{
+				uip_reassbitmap[i] = 0xff;
+			}
+
+			uip_reassbitmap[( offset + len ) / ( 8 * 8 )] |= ~bitmap_bits[( (offset + len) / 8 ) & 7];
+		}
+
+		/* If this fragment has the More Fragments flag set to zero, we
+       know that this is the last fragment, so we can calculate the
+       size of the entire packet. We also set the
+       IP_REASS_FLAG_LASTFRAG flag to indicate that we have received
+       the final fragment. */
+		if( (BUF->ipoffset[0] & IP_MF) == 0 )
+		{
+			uip_reassflags |= UIP_REASS_FLAG_LASTFRAG;
+			uip_reasslen = offset + len;
+		}
+
+		/* Finally, we check if we have a full packet in the buffer. We do
+       this by checking if we have the last fragment and if all bits
+       in the bitmap are set. */
+		if( uip_reassflags & UIP_REASS_FLAG_LASTFRAG )
+		{
+			/* Check all bytes up to and including all but the last byte in
+	 the bitmap. */
+			for( i = 0; i < uip_reasslen / (8 * 8) - 1; ++i )
+			{
+				if( uip_reassbitmap[i] != 0xff )
+				{
+					goto nullreturn;
+				}
+			}
+
+			/* Check the last byte in the bitmap. It should contain just the
+	 right amount of bits. */
+			if( uip_reassbitmap[uip_reasslen / (8 * 8)] != (u8_t)~bitmap_bits[uip_reasslen / 8 & 7] )
+			{
+				goto nullreturn;
+			}
+
+			/* If we have come this far, we have a full packet in the
+	 buffer, so we allocate a pbuf and copy the packet into it. We
+	 also reset the timer. */
+			uip_reasstmr = 0;
+			memcpy( BUF, FBUF, uip_reasslen );
+
+			/* Pretend to be a "normal" (i.e., not fragmented) IP packet
+	 from now on. */
+			BUF->ipoffset[0] = BUF->ipoffset[1] = 0;
+			BUF->len[0] = uip_reasslen >> 8;
+			BUF->len[1] = uip_reasslen & 0xff;
+			BUF->ipchksum = 0;
+			BUF->ipchksum = ~( uip_ipchksum() );
+
+			return uip_reasslen;
+		}
+	}
+
+nullreturn:
+	return 0;
+}
+
+#endif /* UIP_REASSEMBLY */
+
+/*---------------------------------------------------------------------------*/
+static void uip_add_rcv_nxt( u16_t n )
+{
+	uip_add32( uip_conn->rcv_nxt, n );
+	uip_conn->rcv_nxt[0] = uip_acc32[0];
+	uip_conn->rcv_nxt[1] = uip_acc32[1];
+	uip_conn->rcv_nxt[2] = uip_acc32[2];
+	uip_conn->rcv_nxt[3] = uip_acc32[3];
+}
+
+/*---------------------------------------------------------------------------*/
+void uip_process( u8_t flag )
+{
+	register struct uip_conn	*uip_connr = uip_conn;
+
+	#if UIP_UDP
+	if( flag == UIP_UDP_SEND_CONN )
+	{
+		goto udp_send;
+	}
+
+	#endif /* UIP_UDP */
+
+	uip_sappdata = uip_appdata = &uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN];
+
+	/* Check if we were invoked because of a poll request for a
+     particular connection. */
+	if( flag == UIP_POLL_REQUEST )
+	{
+		if( (uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_ESTABLISHED && !uip_outstanding(uip_connr) )
+		{
+			uip_flags = UIP_POLL;
+			UIP_APPCALL();
+			goto appsend;
+		}
+
+		goto drop;
+
+		/* Check if we were invoked because of the perodic timer fireing. */
+	}
+	else if( flag == UIP_TIMER )
+	{
+		#if UIP_REASSEMBLY
+		if( uip_reasstmr != 0 )
+		{
+			--uip_reasstmr;
+		}
+
+		#endif /* UIP_REASSEMBLY */
+
+		/* Increase the initial sequence number. */
+		if( ++iss[3] == 0 )
+		{
+			if( ++iss[2] == 0 )
+			{
+				if( ++iss[1] == 0 )
+				{
+					++iss[0];
+				}
+			}
+		}
+
+		/* Reset the length variables. */
+		uip_len = 0;
+		uip_slen = 0;
+
+		/* Check if the connection is in a state in which we simply wait
+       for the connection to time out. If so, we increase the
+       connection's timer and remove the connection if it times
+       out. */
+		if( uip_connr->tcpstateflags == UIP_TIME_WAIT || uip_connr->tcpstateflags == UIP_FIN_WAIT_2 )
+		{
+			++( uip_connr->timer );
+			if( uip_connr->timer == UIP_TIME_WAIT_TIMEOUT )
+			{
+				uip_connr->tcpstateflags = UIP_CLOSED;
+			}
+		}
+		else if( uip_connr->tcpstateflags != UIP_CLOSED )
+		{
+			/* If the connection has outstanding data, we increase the
+	 connection's timer and see if it has reached the RTO value
+	 in which case we retransmit. */
+			if( uip_outstanding(uip_connr) )
+			{
+				uip_connr->timer = uip_connr->timer - 1;
+				if( uip_connr->timer == 0 )
+				{
+					if
+					(
+						uip_connr->nrtx == UIP_MAXRTX ||
+						(
+							(uip_connr->tcpstateflags == UIP_SYN_SENT || uip_connr->tcpstateflags == UIP_SYN_RCVD) &&
+							uip_connr->nrtx == UIP_MAXSYNRTX
+						)
+					)
+					{
+						uip_connr->tcpstateflags = UIP_CLOSED;
+
+						/* We call UIP_APPCALL() with uip_flags set to
+	       UIP_TIMEDOUT to inform the application that the
+	       connection has timed out. */
+						uip_flags = UIP_TIMEDOUT;
+						UIP_APPCALL();
+
+						/* We also send a reset packet to the remote host. */
+						BUF->flags = TCP_RST | TCP_ACK;
+						goto tcp_send_nodata;
+					}
+
+					/* Exponential backoff. */
+					uip_connr->timer = UIP_RTO << ( uip_connr->nrtx > 4 ? 4 : uip_connr->nrtx );
+					++( uip_connr->nrtx );
+
+					/* Ok, so we need to retransmit. We do this differently
+	     depending on which state we are in. In ESTABLISHED, we
+	     call upon the application so that it may prepare the
+	     data for the retransmit. In SYN_RCVD, we resend the
+	     SYNACK that we sent earlier and in LAST_ACK we have to
+	     retransmit our FINACK. */
+					UIP_STAT( ++uip_stat.tcp.rexmit );
+					switch( uip_connr->tcpstateflags & UIP_TS_MASK )
+					{
+						case UIP_SYN_RCVD:
+							/* In the SYN_RCVD state, we should retransmit our
+               SYNACK. */
+							goto tcp_send_synack;
+
+							#if UIP_ACTIVE_OPEN
+
+						case UIP_SYN_SENT:
+							/* In the SYN_SENT state, we retransmit out SYN. */
+							BUF->flags = 0;
+							goto tcp_send_syn;
+							#endif /* UIP_ACTIVE_OPEN */
+
+						case UIP_ESTABLISHED:
+							/* In the ESTABLISHED state, we call upon the application
+               to do the actual retransmit after which we jump into
+               the code for sending out the packet (the apprexmit
+               label). */
+							uip_flags = UIP_REXMIT;
+							UIP_APPCALL();
+							goto apprexmit;
+
+						case UIP_FIN_WAIT_1:
+						case UIP_CLOSING:
+						case UIP_LAST_ACK:
+							/* In all these states we should retransmit a FINACK. */
+							goto tcp_send_finack;
+					}
+				}
+			}
+			else if( (uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_ESTABLISHED )
+			{
+				/* If there was no need for a retransmission, we poll the
+           application for new data. */
+				uip_flags = UIP_POLL;
+				UIP_APPCALL();
+				goto appsend;
+			}
+		}
+
+		goto drop;
+	}
+
+	#if UIP_UDP
+	if( flag == UIP_UDP_TIMER )
+	{
+		if( uip_udp_conn->lport != 0 )
+		{
+			uip_conn = NULL;
+			uip_sappdata = uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPUDPH_LEN];
+			uip_len = uip_slen = 0;
+			uip_flags = UIP_POLL;
+			UIP_UDP_APPCALL();
+			goto udp_send;
+		}
+		else
+		{
+			goto drop;
+		}
+	}
+
+	#endif
+
+	/* This is where the input processing starts. */
+	UIP_STAT( ++uip_stat.ip.recv );
+
+	/* Start of IP input header processing code. */
+	#if UIP_CONF_IPV6
+
+	/* Check validity of the IP header. */
+	if( (BUF->vtc & 0xf0) != 0x60 )
+	{					/* IP version and header length. */
+		UIP_STAT( ++uip_stat.ip.drop );
+		UIP_STAT( ++uip_stat.ip.vhlerr );
+		UIP_LOG( "ipv6: invalid version." );
+		goto drop;
+	}
+
+	#else /* UIP_CONF_IPV6 */
+
+	/* Check validity of the IP header. */
+	if( BUF->vhl != 0x45 )
+	{					/* IP version and header length. */
+		UIP_STAT( ++uip_stat.ip.drop );
+		UIP_STAT( ++uip_stat.ip.vhlerr );
+		UIP_LOG( "ip: invalid version or header length." );
+		goto drop;
+	}
+
+	#endif /* UIP_CONF_IPV6 */
+
+	/* Check the size of the packet. If the size reported to us in
+     uip_len is smaller the size reported in the IP header, we assume
+     that the packet has been corrupted in transit. If the size of
+     uip_len is larger than the size reported in the IP packet header,
+     the packet has been padded and we set uip_len to the correct
+     value.. */
+	if( (BUF->len[0] << 8) + BUF->len[1] <= uip_len )
+	{
+		uip_len = ( BUF->len[0] << 8 ) + BUF->len[1];
+		#if UIP_CONF_IPV6
+		uip_len += 40;	/* The length reported in the IPv6 header is the
+		      length of the payload that follows the
+		      header. However, uIP uses the uip_len variable
+		      for holding the size of the entire packet,
+		      including the IP header. For IPv4 this is not a
+		      problem as the length field in the IPv4 header
+		      contains the length of the entire packet. But
+		      for IPv6 we need to add the size of the IPv6
+		      header (40 bytes). */
+		#endif /* UIP_CONF_IPV6 */
+	}
+	else
+	{
+		UIP_LOG( "ip: packet shorter than reported in IP header." );
+		goto drop;
+	}
+
+	#if !UIP_CONF_IPV6
+
+	/* Check the fragment flag. */
+	if( (BUF->ipoffset[0] & 0x3f) != 0 || BUF->ipoffset[1] != 0 )
+	{
+			#if UIP_REASSEMBLY
+		uip_len = uip_reass();
+		if( uip_len == 0 )
+		{
+			goto drop;
+		}
+
+			#else /* UIP_REASSEMBLY */
+		UIP_STAT( ++uip_stat.ip.drop );
+		UIP_STAT( ++uip_stat.ip.fragerr );
+		UIP_LOG( "ip: fragment dropped." );
+		goto drop;
+			#endif /* UIP_REASSEMBLY */
+	}
+
+	#endif /* UIP_CONF_IPV6 */
+
+	if( uip_ipaddr_cmp(uip_hostaddr, all_zeroes_addr) )
+	{
+		/* If we are configured to use ping IP address configuration and
+       hasn't been assigned an IP address yet, we accept all ICMP
+       packets. */
+		#if UIP_PINGADDRCONF && !UIP_CONF_IPV6
+		if( BUF->proto == UIP_PROTO_ICMP )
+		{
+			UIP_LOG( "ip: possible ping config packet received." );
+			goto icmp_input;
+		}
+		else
+		{
+			UIP_LOG( "ip: packet dropped since no address assigned." );
+			goto drop;
+		}
+
+		#endif /* UIP_PINGADDRCONF */
+	}
+	else
+	{
+		/* If IP broadcast support is configured, we check for a broadcast
+       UDP packet, which may be destined to us. */
+		#if UIP_BROADCAST
+		DEBUG_PRINTF( "UDP IP checksum 0x%04x\n", uip_ipchksum() );
+		if( BUF->proto == UIP_PROTO_UDP && uip_ipaddr_cmp(BUF->destipaddr, all_ones_addr) /*&&
+	 uip_ipchksum() == 0xffff*/ )
+		{
+			goto udp_input;
+		}
+
+		#endif /* UIP_BROADCAST */
+
+		/* Check if the packet is destined for our IP address. */
+		#if !UIP_CONF_IPV6
+		if( !uip_ipaddr_cmp(BUF->destipaddr, uip_hostaddr) )
+		{
+			UIP_STAT( ++uip_stat.ip.drop );
+			goto drop;
+		}
+
+		#else /* UIP_CONF_IPV6 */
+
+		/* For IPv6, packet reception is a little trickier as we need to
+       make sure that we listen to certain multicast addresses (all
+       hosts multicast address, and the solicited-node multicast
+       address) as well. However, we will cheat here and accept all
+       multicast packets that are sent to the ff02::/16 addresses. */
+		if( !uip_ipaddr_cmp(BUF->destipaddr, uip_hostaddr) && BUF->destipaddr[0] != HTONS(0xff02) )
+		{
+			UIP_STAT( ++uip_stat.ip.drop );
+			goto drop;
+		}
+
+		#endif /* UIP_CONF_IPV6 */
+	}
+
+	#if !UIP_CONF_IPV6
+	if( uip_ipchksum() != 0xffff )
+	{					/* Compute and check the IP header
+				    checksum. */
+		UIP_STAT( ++uip_stat.ip.drop );
+		UIP_STAT( ++uip_stat.ip.chkerr );
+		UIP_LOG( "ip: bad checksum." );
+		goto drop;
+	}
+
+	#endif /* UIP_CONF_IPV6 */
+
+	if( BUF->proto == UIP_PROTO_TCP )
+	{					/* Check for TCP packet. If so,
+				       proceed with TCP input
+				       processing. */
+		goto tcp_input;
+	}
+
+	#if UIP_UDP
+	if( BUF->proto == UIP_PROTO_UDP )
+	{
+		goto udp_input;
+	}
+
+	#endif /* UIP_UDP */
+
+	#if !UIP_CONF_IPV6
+
+	/* ICMPv4 processing code follows. */
+	if( BUF->proto != UIP_PROTO_ICMP )
+	{					/* We only allow ICMP packets from
+					here. */
+		UIP_STAT( ++uip_stat.ip.drop );
+		UIP_STAT( ++uip_stat.ip.protoerr );
+		UIP_LOG( "ip: neither tcp nor icmp." );
+		goto drop;
+	}
+
+		#if UIP_PINGADDRCONF
+	icmp_input :
+		#endif /* UIP_PINGADDRCONF */
+	UIP_STAT( ++uip_stat.icmp.recv );
+
+	/* ICMP echo (i.e., ping) processing. This is simple, we only change
+     the ICMP type from ECHO to ECHO_REPLY and adjust the ICMP
+     checksum before we return the packet. */
+	if( ICMPBUF->type != ICMP_ECHO )
+	{
+		UIP_STAT( ++uip_stat.icmp.drop );
+		UIP_STAT( ++uip_stat.icmp.typeerr );
+		UIP_LOG( "icmp: not icmp echo." );
+		goto drop;
+	}
+
+	/* If we are configured to use ping IP address assignment, we use
+     the destination IP address of this ping packet and assign it to
+     ourself. */
+		#if UIP_PINGADDRCONF
+	if( (uip_hostaddr[0] | uip_hostaddr[1]) == 0 )
+	{
+		uip_hostaddr[0] = BUF->destipaddr[0];
+		uip_hostaddr[1] = BUF->destipaddr[1];
+	}
+
+		#endif /* UIP_PINGADDRCONF */
+
+	ICMPBUF->type = ICMP_ECHO_REPLY;
+
+	if( ICMPBUF->icmpchksum >= HTONS(0xffff - (ICMP_ECHO << 8)) )
+	{
+		ICMPBUF->icmpchksum += HTONS( ICMP_ECHO << 8 ) + 1;
+	}
+	else
+	{
+		ICMPBUF->icmpchksum += HTONS( ICMP_ECHO << 8 );
+	}
+
+	/* Swap IP addresses. */
+	uip_ipaddr_copy( BUF->destipaddr, BUF->srcipaddr );
+	uip_ipaddr_copy( BUF->srcipaddr, uip_hostaddr );
+
+	UIP_STAT( ++uip_stat.icmp.sent );
+	goto send;
+
+	/* End of IPv4 input header processing code. */
+	#else /* !UIP_CONF_IPV6 */
+
+	/* This is IPv6 ICMPv6 processing code. */
+	DEBUG_PRINTF( "icmp6_input: length %d\n", uip_len );
+
+	if( BUF->proto != UIP_PROTO_ICMP6 )
+	{					/* We only allow ICMPv6 packets from
+					 here. */
+		UIP_STAT( ++uip_stat.ip.drop );
+		UIP_STAT( ++uip_stat.ip.protoerr );
+		UIP_LOG( "ip: neither tcp nor icmp6." );
+		goto drop;
+	}
+
+	UIP_STAT( ++uip_stat.icmp.recv );
+
+	/* If we get a neighbor solicitation for our address we should send
+     a neighbor advertisement message back. */
+	if( ICMPBUF->type == ICMP6_NEIGHBOR_SOLICITATION )
+	{
+		if( uip_ipaddr_cmp(ICMPBUF->icmp6data, uip_hostaddr) )
+		{
+			if( ICMPBUF->options[0] == ICMP6_OPTION_SOURCE_LINK_ADDRESS )
+			{
+				/* Save the sender's address in our neighbor list. */
+				uip_neighbor_add( ICMPBUF->srcipaddr, &(ICMPBUF->options[2]) );
+			}
+
+			/* We should now send a neighbor advertisement back to where the
+	 neighbor solicication came from. */
+			ICMPBUF->type = ICMP6_NEIGHBOR_ADVERTISEMENT;
+			ICMPBUF->flags = ICMP6_FLAG_S;	/* Solicited flag. */
+
+			ICMPBUF->reserved1 = ICMPBUF->reserved2 = ICMPBUF->reserved3 = 0;
+
+			uip_ipaddr_copy( ICMPBUF->destipaddr, ICMPBUF->srcipaddr );
+			uip_ipaddr_copy( ICMPBUF->srcipaddr, uip_hostaddr );
+			ICMPBUF->options[0] = ICMP6_OPTION_TARGET_LINK_ADDRESS;
+			ICMPBUF->options[1] = 1;		/* Options length, 1 = 8 bytes. */
+			memcpy( &(ICMPBUF->options[2]), &uip_ethaddr, sizeof(uip_ethaddr) );
+			ICMPBUF->icmpchksum = 0;
+			ICMPBUF->icmpchksum = ~uip_icmp6chksum();
+			goto send;
+		}
+
+		goto drop;
+	}
+	else if( ICMPBUF->type == ICMP6_ECHO )
+	{
+		/* ICMP echo (i.e., ping) processing. This is simple, we only
+       change the ICMP type from ECHO to ECHO_REPLY and update the
+       ICMP checksum before we return the packet. */
+		ICMPBUF->type = ICMP6_ECHO_REPLY;
+
+		uip_ipaddr_copy( BUF->destipaddr, BUF->srcipaddr );
+		uip_ipaddr_copy( BUF->srcipaddr, uip_hostaddr );
+		ICMPBUF->icmpchksum = 0;
+		ICMPBUF->icmpchksum = ~uip_icmp6chksum();
+
+		UIP_STAT( ++uip_stat.icmp.sent );
+		goto send;
+	}
+	else
+	{
+		DEBUG_PRINTF( "Unknown icmp6 message type %d\n", ICMPBUF->type );
+		UIP_STAT( ++uip_stat.icmp.drop );
+		UIP_STAT( ++uip_stat.icmp.typeerr );
+		UIP_LOG( "icmp: unknown ICMP message." );
+		goto drop;
+	}
+
+	/* End of IPv6 ICMP processing. */
+	#endif /* !UIP_CONF_IPV6 */
+
+	#if UIP_UDP
+
+	/* UDP input processing. */
+	udp_input :
+	/* UDP processing is really just a hack. We don't do anything to the
+     UDP/IP headers, but let the UDP application do all the hard
+     work. If the application sets uip_slen, it has a packet to
+     send. */
+		#if UIP_UDP_CHECKSUMS
+	uip_len = uip_len - UIP_IPUDPH_LEN;
+	uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPUDPH_LEN];
+	if( UDPBUF->udpchksum != 0 && uip_udpchksum() != 0xffff )
+	{
+		UIP_STAT( ++uip_stat.udp.drop );
+		UIP_STAT( ++uip_stat.udp.chkerr );
+		UIP_LOG( "udp: bad checksum." );
+		goto drop;
+	}
+
+		#else /* UIP_UDP_CHECKSUMS */
+	uip_len = uip_len - UIP_IPUDPH_LEN;
+		#endif /* UIP_UDP_CHECKSUMS */
+
+	/* Demultiplex this UDP packet between the UDP "connections". */
+	for( uip_udp_conn = &uip_udp_conns[0]; uip_udp_conn < &uip_udp_conns[UIP_UDP_CONNS]; ++uip_udp_conn )
+	{
+		/* If the local UDP port is non-zero, the connection is considered
+       to be used. If so, the local port number is checked against the
+       destination port number in the received packet. If the two port
+       numbers match, the remote port number is checked if the
+       connection is bound to a remote port. Finally, if the
+       connection is bound to a remote IP address, the source IP
+       address of the packet is checked. */
+		if
+		(
+			uip_udp_conn->lport != 0 &&
+			UDPBUF->destport == uip_udp_conn->lport &&
+			(uip_udp_conn->rport == 0 || UDPBUF->srcport == uip_udp_conn->rport) &&
+			(
+				uip_ipaddr_cmp(uip_udp_conn->ripaddr, all_zeroes_addr) ||
+				uip_ipaddr_cmp(uip_udp_conn->ripaddr, all_ones_addr) ||
+				uip_ipaddr_cmp(BUF->srcipaddr, uip_udp_conn->ripaddr)
+			)
+		)
+		{
+			goto udp_found;
+		}
+	}
+
+	UIP_LOG( "udp: no matching connection found" );
+	goto drop;
+
+udp_found:
+	UIP_STAT( ++uip_stat.udp.recv );
+	uip_conn = NULL;
+	uip_flags = UIP_NEWDATA;
+	uip_sappdata = uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPUDPH_LEN];
+	uip_slen = 0;
+	UIP_UDP_APPCALL();
+udp_send:
+	if( uip_slen == 0 )
+	{
+		goto drop;
+	}
+
+	uip_len = uip_slen + UIP_IPUDPH_LEN;
+
+		#if UIP_CONF_IPV6
+
+	/* For IPv6, the IP length field does not include the IPv6 IP header
+     length. */
+	BUF->len[0] = ( (uip_len - UIP_IPH_LEN) >> 8 );
+	BUF->len[1] = ( (uip_len - UIP_IPH_LEN) & 0xff );
+		#else /* UIP_CONF_IPV6 */
+	BUF->len[0] = ( uip_len >> 8 );
+	BUF->len[1] = ( uip_len & 0xff );
+		#endif /* UIP_CONF_IPV6 */
+
+	BUF->ttl = uip_udp_conn->ttl;
+	BUF->proto = UIP_PROTO_UDP;
+
+	UDPBUF->udplen = HTONS( uip_slen + UIP_UDPH_LEN );
+	UDPBUF->udpchksum = 0;
+
+	BUF->srcport = uip_udp_conn->lport;
+	BUF->destport = uip_udp_conn->rport;
+
+	uip_ipaddr_copy( BUF->srcipaddr, uip_hostaddr );
+	uip_ipaddr_copy( BUF->destipaddr, uip_udp_conn->ripaddr );
+
+	uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPTCPH_LEN];
+
+		#if UIP_UDP_CHECKSUMS
+
+	/* Calculate UDP checksum. */
+	UDPBUF->udpchksum = ~( uip_udpchksum() );
+	if( UDPBUF->udpchksum == 0 )
+	{
+		UDPBUF->udpchksum = 0xffff;
+	}
+
+		#endif /* UIP_UDP_CHECKSUMS */
+	UIP_STAT( ++uip_stat.udp.sent );
+	goto ip_send_nolen;
+	#endif /* UIP_UDP */
+
+	/* TCP input processing. */
+	tcp_input : UIP_STAT( ++uip_stat.tcp.recv );
+
+	/* Start of TCP input header processing code. */
+	if( uip_tcpchksum() != 0xffff )
+	{	/* Compute and check the TCP
+				       checksum. */
+		UIP_STAT( ++uip_stat.tcp.drop );
+		UIP_STAT( ++uip_stat.tcp.chkerr );
+		UIP_LOG( "tcp: bad checksum." );
+		goto drop;
+	}
+
+	/* Demultiplex this segment. */
+
+	/* First check any active connections. */
+	for( uip_connr = &uip_conns[0]; uip_connr <= &uip_conns[UIP_CONNS - 1]; ++uip_connr )
+	{
+		if
+		(
+			uip_connr->tcpstateflags != UIP_CLOSED &&
+			BUF->destport == uip_connr->lport &&
+			BUF->srcport == uip_connr->rport &&
+			uip_ipaddr_cmp(BUF->srcipaddr, uip_connr->ripaddr)
+		)
+		{
+			goto found;
+		}
+	}
+
+	/* If we didn't find and active connection that expected the packet,
+     either this packet is an old duplicate, or this is a SYN packet
+     destined for a connection in LISTEN. If the SYN flag isn't set,
+     it is an old packet and we send a RST. */
+	if( (BUF->flags & TCP_CTL) != TCP_SYN )
+	{
+		goto reset;
+	}
+
+	tmp16 = BUF->destport;
+
+	/* Next, check listening connections. */
+	for( c = 0; c < UIP_LISTENPORTS; ++c )
+	{
+		if( tmp16 == uip_listenports[c] )
+		{
+			goto found_listen;
+		}
+	}
+
+	/* No matching connection found, so we send a RST packet. */
+	UIP_STAT( ++uip_stat.tcp.synrst );
+reset:
+	/* We do not send resets in response to resets. */
+	if( BUF->flags & TCP_RST )
+	{
+		goto drop;
+	}
+
+	UIP_STAT( ++uip_stat.tcp.rst );
+
+	BUF->flags = TCP_RST | TCP_ACK;
+	uip_len = UIP_IPTCPH_LEN;
+	BUF->tcpoffset = 5 << 4;
+
+	/* Flip the seqno and ackno fields in the TCP header. */
+	c = BUF->seqno[3];
+	BUF->seqno[3] = BUF->ackno[3];
+	BUF->ackno[3] = c;
+
+	c = BUF->seqno[2];
+	BUF->seqno[2] = BUF->ackno[2];
+	BUF->ackno[2] = c;
+
+	c = BUF->seqno[1];
+	BUF->seqno[1] = BUF->ackno[1];
+	BUF->ackno[1] = c;
+
+	c = BUF->seqno[0];
+	BUF->seqno[0] = BUF->ackno[0];
+	BUF->ackno[0] = c;
+
+	/* We also have to increase the sequence number we are
+     acknowledging. If the least significant byte overflowed, we need
+     to propagate the carry to the other bytes as well. */
+	if( ++BUF->ackno[3] == 0 )
+	{
+		if( ++BUF->ackno[2] == 0 )
+		{
+			if( ++BUF->ackno[1] == 0 )
+			{
+				++BUF->ackno[0];
+			}
+		}
+	}
+
+	/* Swap port numbers. */
+	tmp16 = BUF->srcport;
+	BUF->srcport = BUF->destport;
+	BUF->destport = tmp16;
+
+	/* Swap IP addresses. */
+	uip_ipaddr_copy( BUF->destipaddr, BUF->srcipaddr );
+	uip_ipaddr_copy( BUF->srcipaddr, uip_hostaddr );
+
+	/* And send out the RST packet! */
+	goto tcp_send_noconn;
+
+	/* This label will be jumped to if we matched the incoming packet
+     with a connection in LISTEN. In that case, we should create a new
+     connection and send a SYNACK in return. */
+found_listen:
+	/* First we check if there are any connections avaliable. Unused
+     connections are kept in the same table as used connections, but
+     unused ones have the tcpstate set to CLOSED. Also, connections in
+     TIME_WAIT are kept track of and we'll use the oldest one if no
+     CLOSED connections are found. Thanks to Eddie C. Dost for a very
+     nice algorithm for the TIME_WAIT search. */
+	uip_connr = 0;
+	for( c = 0; c < UIP_CONNS; ++c )
+	{
+		if( uip_conns[c].tcpstateflags == UIP_CLOSED )
+		{
+			uip_connr = &uip_conns[c];
+			break;
+		}
+
+		if( uip_conns[c].tcpstateflags == UIP_TIME_WAIT )
+		{
+			if( uip_connr == 0 || uip_conns[c].timer > uip_connr->timer )
+			{
+				uip_connr = &uip_conns[c];
+			}
+		}
+	}
+
+	if( uip_connr == 0 )
+	{
+		/* All connections are used already, we drop packet and hope that
+       the remote end will retransmit the packet at a time when we
+       have more spare connections. */
+		UIP_STAT( ++uip_stat.tcp.syndrop );
+		UIP_LOG( "tcp: found no unused connections." );
+		goto drop;
+	}
+
+	uip_conn = uip_connr;
+
+	/* Fill in the necessary fields for the new connection. */
+	uip_connr->rto = uip_connr->timer = UIP_RTO;
+	uip_connr->sa = 0;
+	uip_connr->sv = 4;
+	uip_connr->nrtx = 0;
+	uip_connr->lport = BUF->destport;
+	uip_connr->rport = BUF->srcport;
+	uip_ipaddr_copy( uip_connr->ripaddr, BUF->srcipaddr );
+	uip_connr->tcpstateflags = UIP_SYN_RCVD;
+
+	uip_connr->snd_nxt[0] = iss[0];
+	uip_connr->snd_nxt[1] = iss[1];
+	uip_connr->snd_nxt[2] = iss[2];
+	uip_connr->snd_nxt[3] = iss[3];
+	uip_connr->len = 1;
+
+	/* rcv_nxt should be the seqno from the incoming packet + 1. */
+	uip_connr->rcv_nxt[3] = BUF->seqno[3];
+	uip_connr->rcv_nxt[2] = BUF->seqno[2];
+	uip_connr->rcv_nxt[1] = BUF->seqno[1];
+	uip_connr->rcv_nxt[0] = BUF->seqno[0];
+	uip_add_rcv_nxt( 1 );
+
+	/* Parse the TCP MSS option, if present. */
+	if( (BUF->tcpoffset & 0xf0) > 0x50 )
+	{
+		for( c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2; )
+		{
+			opt = uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + c];
+			if( opt == TCP_OPT_END )
+			{
+				/* End of options. */
+				break;
+			}
+			else if( opt == TCP_OPT_NOOP )
+			{
+				++c;
+
+				/* NOP option. */
+			}
+			else if( opt == TCP_OPT_MSS && uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == TCP_OPT_MSS_LEN )
+			{
+				/* An MSS option with the right option length. */
+				tmp16 = ( (u16_t) uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8 ) | ( u16_t ) uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN + 3 + c];
+				uip_connr->initialmss = uip_connr->mss = tmp16 > UIP_TCP_MSS ? UIP_TCP_MSS : tmp16;
+
+				/* And we are done processing options. */
+				break;
+			}
+			else
+			{
+				/* All other options have a length field, so that we easily
+	   can skip past them. */
+				if( uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0 )
+				{
+					/* If the length field is zero, the options are malformed
+	     and we don't process them further. */
+					break;
+				}
+
+				c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c];
+			}
+		}
+	}
+
+	/* Our response will be a SYNACK. */
+	#if UIP_ACTIVE_OPEN
+	tcp_send_synack : BUF->flags = TCP_ACK;
+
+tcp_send_syn:
+	BUF->flags |= TCP_SYN;
+	#else /* UIP_ACTIVE_OPEN */
+	tcp_send_synack : BUF->flags = TCP_SYN | TCP_ACK;
+	#endif /* UIP_ACTIVE_OPEN */
+
+	/* We send out the TCP Maximum Segment Size option with our
+     SYNACK. */
+	BUF->optdata[0] = TCP_OPT_MSS;
+	BUF->optdata[1] = TCP_OPT_MSS_LEN;
+	BUF->optdata[2] = ( UIP_TCP_MSS ) / 256;
+	BUF->optdata[3] = ( UIP_TCP_MSS ) & 255;
+	uip_len = UIP_IPTCPH_LEN + TCP_OPT_MSS_LEN;
+	BUF->tcpoffset = ( (UIP_TCPH_LEN + TCP_OPT_MSS_LEN) / 4 ) << 4;
+	goto tcp_send;
+
+	/* This label will be jumped to if we found an active connection. */
+found:
+	uip_conn = uip_connr;
+	uip_flags = 0;
+
+	/* We do a very naive form of TCP reset processing; we just accept
+     any RST and kill our connection. We should in fact check if the
+     sequence number of this reset is wihtin our advertised window
+     before we accept the reset. */
+	if( BUF->flags & TCP_RST )
+	{
+		uip_connr->tcpstateflags = UIP_CLOSED;
+		UIP_LOG( "tcp: got reset, aborting connection." );
+		uip_flags = UIP_ABORT;
+		UIP_APPCALL();
+		goto drop;
+	}
+
+	/* Calculated the length of the data, if the application has sent
+     any data to us. */
+	c = ( BUF->tcpoffset >> 4 ) << 2;
+
+	/* uip_len will contain the length of the actual TCP data. This is
+     calculated by subtracing the length of the TCP header (in
+     c) and the length of the IP header (20 bytes). */
+	uip_len = uip_len - c - UIP_IPH_LEN;
+
+	/* First, check if the sequence number of the incoming packet is
+     what we're expecting next. If not, we send out an ACK with the
+     correct numbers in. */
+	if( !(((uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_SYN_SENT) && ((BUF->flags & TCP_CTL) == (TCP_SYN | TCP_ACK))) )
+	{
+		if
+		(
+			(uip_len > 0 || ((BUF->flags & (TCP_SYN | TCP_FIN)) != 0)) &&
+			(
+				BUF->seqno[0] != uip_connr->rcv_nxt[0] ||
+				BUF->seqno[1] != uip_connr->rcv_nxt[1] ||
+				BUF->seqno[2] != uip_connr->rcv_nxt[2] ||
+				BUF->seqno[3] != uip_connr->rcv_nxt[3]
+			)
+		)
+		{
+			goto tcp_send_ack;
+		}
+	}
+
+	/* Next, check if the incoming segment acknowledges any outstanding
+     data. If so, we update the sequence number, reset the length of
+     the outstanding data, calculate RTT estimations, and reset the
+     retransmission timer. */
+	if( (BUF->flags & TCP_ACK) && uip_outstanding(uip_connr) )
+	{
+		uip_add32( uip_connr->snd_nxt, uip_connr->len );
+
+		if
+		(
+			BUF->ackno[0] == uip_acc32[0] &&
+			BUF->ackno[1] == uip_acc32[1] &&
+			BUF->ackno[2] == uip_acc32[2] &&
+			BUF->ackno[3] == uip_acc32[3]
+		)
+		{
+			/* Update sequence number. */
+			uip_connr->snd_nxt[0] = uip_acc32[0];
+			uip_connr->snd_nxt[1] = uip_acc32[1];
+			uip_connr->snd_nxt[2] = uip_acc32[2];
+			uip_connr->snd_nxt[3] = uip_acc32[3];
+
+			/* Do RTT estimation, unless we have done retransmissions. */
+			if( uip_connr->nrtx == 0 )
+			{
+				signed char m;
+				m = uip_connr->rto - uip_connr->timer;
+
+				/* This is taken directly from VJs original code in his paper */
+				m = m - ( uip_connr->sa >> 3 );
+				uip_connr->sa += m;
+				if( m < 0 )
+				{
+					m = -m;
+				}
+
+				m = m - ( uip_connr->sv >> 2 );
+				uip_connr->sv += m;
+				uip_connr->rto = ( uip_connr->sa >> 3 ) + uip_connr->sv;
+			}
+
+			/* Set the acknowledged flag. */
+			uip_flags = UIP_ACKDATA;
+
+			/* Reset the retransmission timer. */
+			uip_connr->timer = uip_connr->rto;
+
+			/* Reset length of outstanding data. */
+			uip_connr->len = 0;
+		}
+	}
+
+	/* Do different things depending on in what state the connection is. */
+	switch( uip_connr->tcpstateflags & UIP_TS_MASK )
+	{
+		/* CLOSED and LISTEN are not handled here. CLOSE_WAIT is not
+	implemented, since we force the application to close when the
+	peer sends a FIN (hence the application goes directly from
+	ESTABLISHED to LAST_ACK). */
+		case UIP_SYN_RCVD:
+			/* In SYN_RCVD we have sent out a SYNACK in response to a SYN, and
+       we are waiting for an ACK that acknowledges the data we sent
+       out the last time. Therefore, we want to have the UIP_ACKDATA
+       flag set. If so, we enter the ESTABLISHED state. */
+			if( uip_flags & UIP_ACKDATA )
+			{
+				uip_connr->tcpstateflags = UIP_ESTABLISHED;
+				uip_flags = UIP_CONNECTED;
+				uip_connr->len = 0;
+				if( uip_len > 0 )
+				{
+					uip_flags |= UIP_NEWDATA;
+					uip_add_rcv_nxt( uip_len );
+				}
+
+				uip_slen = 0;
+				UIP_APPCALL();
+				goto appsend;
+			}
+
+			goto drop;
+			#if UIP_ACTIVE_OPEN
+
+		case UIP_SYN_SENT:
+			/* In SYN_SENT, we wait for a SYNACK that is sent in response to
+       our SYN. The rcv_nxt is set to sequence number in the SYNACK
+       plus one, and we send an ACK. We move into the ESTABLISHED
+       state. */
+			if( (uip_flags & UIP_ACKDATA) && (BUF->flags & TCP_CTL) == (TCP_SYN | TCP_ACK) )
+			{
+				/* Parse the TCP MSS option, if present. */
+				if( (BUF->tcpoffset & 0xf0) > 0x50 )
+				{
+					for( c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2; )
+					{
+						opt = uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN + c];
+						if( opt == TCP_OPT_END )
+						{
+							/* End of options. */
+							break;
+						}
+						else if( opt == TCP_OPT_NOOP )
+						{
+							++c;
+
+							/* NOP option. */
+						}
+						else if( opt == TCP_OPT_MSS && uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == TCP_OPT_MSS_LEN )
+						{
+							/* An MSS option with the right option length. */
+							tmp16 = ( uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8 ) | uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 3 + c];
+							uip_connr->initialmss = uip_connr->mss = tmp16 > UIP_TCP_MSS ? UIP_TCP_MSS : tmp16;
+
+							/* And we are done processing options. */
+							break;
+						}
+						else
+						{
+							/* All other options have a length field, so that we easily
+	       can skip past them. */
+							if( uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0 )
+							{
+								/* If the length field is zero, the options are malformed
+		 and we don't process them further. */
+								break;
+							}
+
+							c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c];
+						}
+					}
+				}
+
+				uip_connr->tcpstateflags = UIP_ESTABLISHED;
+				uip_connr->rcv_nxt[0] = BUF->seqno[0];
+				uip_connr->rcv_nxt[1] = BUF->seqno[1];
+				uip_connr->rcv_nxt[2] = BUF->seqno[2];
+				uip_connr->rcv_nxt[3] = BUF->seqno[3];
+				uip_add_rcv_nxt( 1 );
+				uip_flags = UIP_CONNECTED | UIP_NEWDATA;
+				uip_connr->len = 0;
+				uip_len = 0;
+				uip_slen = 0;
+				UIP_APPCALL();
+				goto appsend;
+			}
+
+			/* Inform the application that the connection failed */
+			uip_flags = UIP_ABORT;
+			UIP_APPCALL();
+
+			/* The connection is closed after we send the RST */
+			uip_conn->tcpstateflags = UIP_CLOSED;
+			goto reset;
+			#endif /* UIP_ACTIVE_OPEN */
+
+		case UIP_ESTABLISHED:
+			/* In the ESTABLISHED state, we call upon the application to feed
+    data into the uip_buf. If the UIP_ACKDATA flag is set, the
+    application should put new data into the buffer, otherwise we are
+    retransmitting an old segment, and the application should put that
+    data into the buffer.
+
+    If the incoming packet is a FIN, we should close the connection on
+    this side as well, and we send out a FIN and enter the LAST_ACK
+    state. We require that there is no outstanding data; otherwise the
+    sequence numbers will be screwed up. */
+			if( BUF->flags & TCP_FIN && !(uip_connr->tcpstateflags & UIP_STOPPED) )
+			{
+				if( uip_outstanding(uip_connr) )
+				{
+					goto drop;
+				}
+
+				uip_add_rcv_nxt( 1 + uip_len );
+				uip_flags |= UIP_CLOSE;
+				if( uip_len > 0 )
+				{
+					uip_flags |= UIP_NEWDATA;
+				}
+
+				UIP_APPCALL();
+				uip_connr->len = 1;
+				uip_connr->tcpstateflags = UIP_LAST_ACK;
+				uip_connr->nrtx = 0;
+	tcp_send_finack:
+				BUF->flags = TCP_FIN | TCP_ACK;
+				goto tcp_send_nodata;
+			}
+
+			/* Check the URG flag. If this is set, the segment carries urgent
+       data that we must pass to the application. */
+			if( (BUF->flags & TCP_URG) != 0 )
+			{
+				#if UIP_URGDATA > 0
+				uip_urglen = ( BUF->urgp[0] << 8 ) | BUF->urgp[1];
+				if( uip_urglen > uip_len )
+				{
+					/* There is more urgent data in the next segment to come. */
+					uip_urglen = uip_len;
+				}
+
+				uip_add_rcv_nxt( uip_urglen );
+				uip_len -= uip_urglen;
+				uip_urgdata = uip_appdata;
+				uip_appdata += uip_urglen;
+			}
+			else
+			{
+				uip_urglen = 0;
+				#else /* UIP_URGDATA > 0 */
+				uip_appdata = ( ( char * ) uip_appdata ) + ( (BUF->urgp[0] << 8) | BUF->urgp[1] );
+				uip_len -= ( BUF->urgp[0] << 8 ) | BUF->urgp[1];
+				#endif /* UIP_URGDATA > 0 */
+			}
+
+			/* If uip_len > 0 we have TCP data in the packet, and we flag this
+       by setting the UIP_NEWDATA flag and update the sequence number
+       we acknowledge. If the application has stopped the dataflow
+       using uip_stop(), we must not accept any data packets from the
+       remote host. */
+			if( uip_len > 0 && !(uip_connr->tcpstateflags & UIP_STOPPED) )
+			{
+				uip_flags |= UIP_NEWDATA;
+				uip_add_rcv_nxt( uip_len );
+			}
+
+			/* Check if the available buffer space advertised by the other end
+       is smaller than the initial MSS for this connection. If so, we
+       set the current MSS to the window size to ensure that the
+       application does not send more data than the other end can
+       handle.
+
+       If the remote host advertises a zero window, we set the MSS to
+       the initial MSS so that the application will send an entire MSS
+       of data. This data will not be acknowledged by the receiver,
+       and the application will retransmit it. This is called the
+       "persistent timer" and uses the retransmission mechanim.
+    */
+			tmp16 = ( (u16_t) BUF->wnd[0] << 8 ) + ( u16_t ) BUF->wnd[1];
+			if( tmp16 > (uip_connr->initialmss * FRAME_MULTIPLE) || tmp16 == 0 )
+			{
+				tmp16 = uip_connr->initialmss * FRAME_MULTIPLE;
+			}
+
+			uip_connr->mss = tmp16;
+
+			/* If this packet constitutes an ACK for outstanding data (flagged
+       by the UIP_ACKDATA flag, we should call the application since it
+       might want to send more data. If the incoming packet had data
+       from the peer (as flagged by the UIP_NEWDATA flag), the
+       application must also be notified.
+
+       When the application is called, the global variable uip_len
+       contains the length of the incoming data. The application can
+       access the incoming data through the global pointer
+       uip_appdata, which usually points UIP_IPTCPH_LEN + UIP_LLH_LEN
+       bytes into the uip_buf array.
+
+       If the application wishes to send any data, this data should be
+       put into the uip_appdata and the length of the data should be
+       put into uip_len. If the application don't have any data to
+       send, uip_len must be set to 0. */
+			if( uip_flags & (UIP_NEWDATA | UIP_ACKDATA) )
+			{
+				uip_slen = 0;
+				UIP_APPCALL();
+
+	appsend:
+				if( uip_flags & UIP_ABORT )
+				{
+					uip_slen = 0;
+					uip_connr->tcpstateflags = UIP_CLOSED;
+					BUF->flags = TCP_RST | TCP_ACK;
+					goto tcp_send_nodata;
+				}
+
+				if( uip_flags & UIP_CLOSE )
+				{
+					uip_slen = 0;
+					uip_connr->len = 1;
+					uip_connr->tcpstateflags = UIP_FIN_WAIT_1;
+					uip_connr->nrtx = 0;
+					BUF->flags = TCP_FIN | TCP_ACK;
+					goto tcp_send_nodata;
+				}
+
+				/* If uip_slen > 0, the application has data to be sent. */
+				if( uip_slen > 0 )
+				{
+					/* If the connection has acknowledged data, the contents of
+	   the ->len variable should be discarded. */
+					if( (uip_flags & UIP_ACKDATA) != 0 )
+					{
+						uip_connr->len = 0;
+					}
+
+					/* If the ->len variable is non-zero the connection has
+	   already data in transit and cannot send anymore right
+	   now. */
+					if( uip_connr->len == 0 )
+					{
+						/* The application cannot send more than what is allowed by
+	     the mss (the minumum of the MSS and the available
+	     window). */
+						if( uip_slen > uip_connr->mss )
+						{
+							uip_slen = uip_connr->mss;
+						}
+
+						/* Remember how much data we send out now so that we know
+	     when everything has been acknowledged. */
+						uip_connr->len = uip_slen;
+					}
+					else
+					{
+						/* If the application already had unacknowledged data, we
+	     make sure that the application does not send (i.e.,
+	     retransmit) out more than it previously sent out. */
+						uip_slen = uip_connr->len;
+					}
+				}
+
+				uip_connr->nrtx = 0;
+	apprexmit:
+				uip_appdata = uip_sappdata;
+
+				/* If the application has data to be sent, or if the incoming
+         packet had new data in it, we must send out a packet. */
+				if( uip_slen > 0 && uip_connr->len > 0 )
+				{
+					/* Add the length of the IP and TCP headers. */
+					uip_len = uip_connr->len + UIP_TCPIP_HLEN;
+
+					/* We always set the ACK flag in response packets. */
+					BUF->flags = TCP_ACK | TCP_PSH;
+
+					/* Send the packet. */
+					goto tcp_send_noopts;
+				}
+
+				/* If there is no data to send, just send out a pure ACK if
+	 there is newdata. */
+				if( uip_flags & UIP_NEWDATA )
+				{
+					uip_len = UIP_TCPIP_HLEN;
+					BUF->flags = TCP_ACK;
+					goto tcp_send_noopts;
+				}
+			}
+
+			goto drop;
+
+		case UIP_LAST_ACK:
+			/* We can close this connection if the peer has acknowledged our
+       FIN. This is indicated by the UIP_ACKDATA flag. */
+			if( uip_flags & UIP_ACKDATA )
+			{
+				uip_connr->tcpstateflags = UIP_CLOSED;
+				uip_flags = UIP_CLOSE;
+				UIP_APPCALL();
+			}
+
+			break;
+
+		case UIP_FIN_WAIT_1:
+			/* The application has closed the connection, but the remote host
+       hasn't closed its end yet. Thus we do nothing but wait for a
+       FIN from the other side. */
+			if( uip_len > 0 )
+			{
+				uip_add_rcv_nxt( uip_len );
+			}
+
+			if( BUF->flags & TCP_FIN )
+			{
+				if( uip_flags & UIP_ACKDATA )
+				{
+					uip_connr->tcpstateflags = UIP_TIME_WAIT;
+					uip_connr->timer = 0;
+					uip_connr->len = 0;
+				}
+				else
+				{
+					uip_connr->tcpstateflags = UIP_CLOSING;
+				}
+
+				uip_add_rcv_nxt( 1 );
+				uip_flags = UIP_CLOSE;
+				UIP_APPCALL();
+				goto tcp_send_ack;
+			}
+			else if( uip_flags & UIP_ACKDATA )
+			{
+				uip_connr->tcpstateflags = UIP_FIN_WAIT_2;
+				uip_connr->len = 0;
+				goto drop;
+			}
+
+			if( uip_len > 0 )
+			{
+				goto tcp_send_ack;
+			}
+
+			goto drop;
+
+		case UIP_FIN_WAIT_2:
+			if( uip_len > 0 )
+			{
+				uip_add_rcv_nxt( uip_len );
+			}
+
+			if( BUF->flags & TCP_FIN )
+			{
+				uip_connr->tcpstateflags = UIP_TIME_WAIT;
+				uip_connr->timer = 0;
+				uip_add_rcv_nxt( 1 );
+				uip_flags = UIP_CLOSE;
+				UIP_APPCALL();
+				goto tcp_send_ack;
+			}
+
+			if( uip_len > 0 )
+			{
+				goto tcp_send_ack;
+			}
+
+			goto drop;
+
+		case UIP_TIME_WAIT:
+			goto tcp_send_ack;
+
+		case UIP_CLOSING:
+			if( uip_flags & UIP_ACKDATA )
+			{
+				uip_connr->tcpstateflags = UIP_TIME_WAIT;
+				uip_connr->timer = 0;
+			}
+	}
+
+	goto drop;
+
+	/* We jump here when we are ready to send the packet, and just want
+     to set the appropriate TCP sequence numbers in the TCP header. */
+tcp_send_ack:
+	BUF->flags = TCP_ACK;
+tcp_send_nodata:
+	uip_len = UIP_IPTCPH_LEN;
+tcp_send_noopts:
+	BUF->tcpoffset = ( UIP_TCPH_LEN / 4 ) << 4;
+tcp_send:
+	/* We're done with the input processing. We are now ready to send a
+     reply. Our job is to fill in all the fields of the TCP and IP
+     headers before calculating the checksum and finally send the
+     packet. */
+	BUF->ackno[0] = uip_connr->rcv_nxt[0];
+	BUF->ackno[1] = uip_connr->rcv_nxt[1];
+	BUF->ackno[2] = uip_connr->rcv_nxt[2];
+	BUF->ackno[3] = uip_connr->rcv_nxt[3];
+
+	BUF->seqno[0] = uip_connr->snd_nxt[0];
+	BUF->seqno[1] = uip_connr->snd_nxt[1];
+	BUF->seqno[2] = uip_connr->snd_nxt[2];
+	BUF->seqno[3] = uip_connr->snd_nxt[3];
+
+	BUF->proto = UIP_PROTO_TCP;
+
+	BUF->srcport = uip_connr->lport;
+	BUF->destport = uip_connr->rport;
+
+	uip_ipaddr_copy( BUF->srcipaddr, uip_hostaddr );
+	uip_ipaddr_copy( BUF->destipaddr, uip_connr->ripaddr );
+
+	if( uip_connr->tcpstateflags & UIP_STOPPED )
+	{
+		/* If the connection has issued uip_stop(), we advertise a zero
+       window so that the remote host will stop sending data. */
+		BUF->wnd[0] = BUF->wnd[1] = 0;
+	}
+	else
+	{
+		BUF->wnd[0] = ( (UIP_RECEIVE_WINDOW) >> 8 );
+		BUF->wnd[1] = ( (UIP_RECEIVE_WINDOW) & 0xff );
+	}
+
+tcp_send_noconn:
+	BUF->ttl = UIP_TTL;
+	#if UIP_CONF_IPV6
+
+	/* For IPv6, the IP length field does not include the IPv6 IP header
+     length. */
+	BUF->len[0] = ( (uip_len - UIP_IPH_LEN) >> 8 );
+	BUF->len[1] = ( (uip_len - UIP_IPH_LEN) & 0xff );
+	#else /* UIP_CONF_IPV6 */
+	BUF->len[0] = ( uip_len >> 8 );
+	BUF->len[1] = ( uip_len & 0xff );
+	#endif /* UIP_CONF_IPV6 */
+
+	BUF->urgp[0] = BUF->urgp[1] = 0;
+
+	/* Calculate TCP checksum. */
+	BUF->tcpchksum = 0;
+	BUF->tcpchksum = ~( uip_tcpchksum() );
+
+	#if UIP_UDP
+	ip_send_nolen :
+	#endif
+	#if UIP_CONF_IPV6
+	BUF->vtc = 0x60;
+	BUF->tcflow = 0x00;
+	BUF->flow = 0x00;
+	#else /* UIP_CONF_IPV6 */
+	BUF->vhl = 0x45;
+	BUF->tos = 0;
+	BUF->ipoffset[0] = BUF->ipoffset[1] = 0;
+	++ipid;
+	BUF->ipid[0] = ipid >> 8;
+	BUF->ipid[1] = ipid & 0xff;
+
+	/* Calculate IP checksum. */
+	BUF->ipchksum = 0;
+	BUF->ipchksum = ~( uip_ipchksum() );
+	DEBUG_PRINTF( "uip ip_send_nolen: chkecum 0x%04x\n", uip_ipchksum() );
+	#endif /* UIP_CONF_IPV6 */
+
+	UIP_STAT( ++uip_stat.tcp.sent );
+send:
+	DEBUG_PRINTF( "Sending packet with length %d (%d)\n", uip_len, (BUF->len[0] << 8) | BUF->len[1] );
+
+	UIP_STAT( ++uip_stat.ip.sent );
+
+	/* Return and let the caller do the actual transmission. */
+	uip_flags = 0;
+	return;
+drop:
+	uip_len = 0;
+	uip_flags = 0;
+	return;
+}
+
+/*---------------------------------------------------------------------------*/
+u16_t htons( u16_t val )
+{
+	return HTONS( val );
+}
+
+/*---------------------------------------------------------------------------*/
+void uip_send( const void *data, int len )
+{
+	if( len > 0 )
+	{
+		uip_slen = len;
+		if( data != uip_sappdata )
+		{
+			memcpy( uip_sappdata, (data), uip_slen );
+		}
+	}
+}
+
+/*---------------------------------------------------------------------------*/
+int uip_fast_send( int xARP )
+{
+	( void ) xARP;
+	#if NOT_YET_COMPLETE
+
+	u16_t		tcplen, len1 = 0, uiAccumulatedLen = 0, len_previous = 0, split_len;
+	int			iSplitNo = 0;
+	extern int	uip_low_level_output( unsigned char *pcBuf, int ilen );
+
+	if( xARP == pdTRUE )
+	{
+		if( BUF->proto == UIP_PROTO_TCP && uip_slen > 1 )
+		{
+			tcplen = uip_len - UIP_TCPIP_HLEN;
+
+			if( tcplen > UIP_TCP_MSS )
+			{
+				split_len = UIP_TCP_MSS;
+			}
+			else
+			{
+				split_len = tcplen / 2;
+			}
+
+			while( tcplen > 0 )
+			{
+				uiAccumulatedLen += len1;
+
+				if( tcplen > split_len )
+				{
+					len1 = split_len;
+					tcplen -= split_len;
+				}
+				else
+				{
+					len1 = tcplen;
+					tcplen = 0;
+				}
+
+				uip_len = len1 + UIP_TCPIP_HLEN;
+				BUF->len[0] = uip_len >> 8;
+				BUF->len[1] = uip_len & 0xff;
+				if( iSplitNo == 0 )
+				{
+					iSplitNo++;
+
+					/* Create the first packet. This is done by altering the length
+					field of the IP header and updating the checksums. */
+				}
+				else
+				{
+					/* Now, create the second packet. To do this, it is not enough to
+					just alter the length field, but we must also update the TCP
+					sequence number and point the uip_appdata to a new place in
+					memory. This place is determined by the length of the first
+					packet (len1). */
+
+					/*    uip_appdata += len1;*/
+					memcpy( uip_appdata, ( u8_t * ) uip_appdata + uiAccumulatedLen, len1 );
+					uip_add32( BUF->seqno, len_previous );
+					BUF->seqno[0] = uip_acc32[0];
+					BUF->seqno[1] = uip_acc32[1];
+					BUF->seqno[2] = uip_acc32[2];
+					BUF->seqno[3] = uip_acc32[3];
+				}
+
+				/* Recalculate the TCP checksum. */
+				BUF->tcpchksum = 0;
+				BUF->tcpchksum = ~( uip_tcpchksum() );
+
+				/* Recalculate the IP checksum. */
+				BUF->ipchksum = 0;
+				BUF->ipchksum = ~( uip_ipchksum() );
+
+				/* Transmit the packet. */
+				uip_arp_out();
+				uip_low_level_output( uip_buf, uip_len );
+
+				len_previous = len1;
+			}
+		}
+		else
+		{
+			uip_arp_out();
+			uip_low_level_output( uip_buf, uip_len );
+		}
+	}
+	else
+	{
+		uip_low_level_output( uip_buf, uip_len );
+	}
+
+	#endif
+	return 1;
+}
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip.h
new file mode 100644
index 0000000..e432d90
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip.h
@@ -0,0 +1,1642 @@
+
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \file
+ * Header file for the uIP TCP/IP stack.
+ * \author Adam Dunkels 
+ *
+ * The uIP TCP/IP stack header file contains definitions for a number
+ * of C macros that are used by uIP programs as well as internal uIP
+ * structures, TCP/IP header structures and function declarations.
+ *
+ */
+
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip.h,v 1.40 2006/06/08 07:12:07 adam Exp $
+ *
+ */
+
+#ifndef __UIP_H__
+#define __UIP_H__
+
+#include "uipopt.h"
+
+/**
+ * Repressentation of an IP address.
+ *
+ */
+typedef u16_t uip_ip4addr_t[2];
+typedef u16_t uip_ip6addr_t[8];
+#if UIP_CONF_IPV6
+typedef uip_ip6addr_t uip_ipaddr_t;
+#else /* UIP_CONF_IPV6 */
+typedef uip_ip4addr_t uip_ipaddr_t;
+#endif /* UIP_CONF_IPV6 */
+
+/*---------------------------------------------------------------------------*/
+/* First, the functions that should be called from the
+ * system. Initialization, the periodic timer and incoming packets are
+ * handled by the following three functions.
+ */
+
+/**
+ * \defgroup uipconffunc uIP configuration functions
+ * @{
+ *
+ * The uIP configuration functions are used for setting run-time
+ * parameters in uIP such as IP addresses.
+ */
+
+/**
+ * Set the IP address of this host.
+ *
+ * The IP address is represented as a 4-byte array where the first
+ * octet of the IP address is put in the first member of the 4-byte
+ * array.
+ *
+ * Example:
+ \code
+
+ uip_ipaddr_t addr;
+
+ uip_ipaddr(&addr, 192,168,1,2);
+ uip_sethostaddr(&addr);
+
+ \endcode
+ * \param addr A pointer to an IP address of type uip_ipaddr_t;
+ *
+ * \sa uip_ipaddr()
+ *
+ * \hideinitializer
+ */
+#define uip_sethostaddr(addr) uip_ipaddr_copy(uip_hostaddr, (addr))
+
+/**
+ * Get the IP address of this host.
+ *
+ * The IP address is represented as a 4-byte array where the first
+ * octet of the IP address is put in the first member of the 4-byte
+ * array.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t hostaddr;
+
+ uip_gethostaddr(&hostaddr);
+ \endcode
+ * \param addr A pointer to a uip_ipaddr_t variable that will be
+ * filled in with the currently configured IP address.
+ *
+ * \hideinitializer
+ */
+#define uip_gethostaddr(addr) uip_ipaddr_copy((addr), uip_hostaddr)
+
+/**
+ * Set the default router's IP address.
+ *
+ * \param addr A pointer to a uip_ipaddr_t variable containing the IP
+ * address of the default router.
+ *
+ * \sa uip_ipaddr()
+ *
+ * \hideinitializer
+ */
+#define uip_setdraddr(addr) uip_ipaddr_copy(uip_draddr, (addr))
+
+/**
+ * Set the netmask.
+ *
+ * \param addr A pointer to a uip_ipaddr_t variable containing the IP
+ * address of the netmask.
+ *
+ * \sa uip_ipaddr()
+ *
+ * \hideinitializer
+ */
+#define uip_setnetmask(addr) uip_ipaddr_copy(uip_netmask, (addr))
+
+
+/**
+ * Get the default router's IP address.
+ *
+ * \param addr A pointer to a uip_ipaddr_t variable that will be
+ * filled in with the IP address of the default router.
+ *
+ * \hideinitializer
+ */
+#define uip_getdraddr(addr) uip_ipaddr_copy((addr), uip_draddr)
+
+/**
+ * Get the netmask.
+ *
+ * \param addr A pointer to a uip_ipaddr_t variable that will be
+ * filled in with the value of the netmask.
+ *
+ * \hideinitializer
+ */
+#define uip_getnetmask(addr) uip_ipaddr_copy((addr), uip_netmask)
+
+/** @} */
+
+/**
+ * \defgroup uipinit uIP initialization functions
+ * @{
+ *
+ * The uIP initialization functions are used for booting uIP.
+ */
+
+/**
+ * uIP initialization function.
+ *
+ * This function should be called at boot up to initilize the uIP
+ * TCP/IP stack.
+ */
+void uip_init(void);
+
+/**
+ * uIP initialization function.
+ *
+ * This function may be used at boot time to set the initial ip_id.
+ */
+void uip_setipid(u16_t id);
+
+/** @} */
+
+/**
+ * \defgroup uipdevfunc uIP device driver functions
+ * @{
+ *
+ * These functions are used by a network device driver for interacting
+ * with uIP.
+ */
+
+/**
+ * Process an incoming packet.
+ *
+ * This function should be called when the device driver has received
+ * a packet from the network. The packet from the device driver must
+ * be present in the uip_buf buffer, and the length of the packet
+ * should be placed in the uip_len variable.
+ *
+ * When the function returns, there may be an outbound packet placed
+ * in the uip_buf packet buffer. If so, the uip_len variable is set to
+ * the length of the packet. If no packet is to be sent out, the
+ * uip_len variable is set to 0.
+ *
+ * The usual way of calling the function is presented by the source
+ * code below.
+ \code
+  uip_len = devicedriver_poll();
+  if(uip_len > 0) {
+    uip_input();
+    if(uip_len > 0) {
+      devicedriver_send();
+    }
+  }
+ \endcode
+ *
+ * \note If you are writing a uIP device driver that needs ARP
+ * (Address Resolution Protocol), e.g., when running uIP over
+ * Ethernet, you will need to call the uIP ARP code before calling
+ * this function:
+ \code
+  #define BUF ((struct uip_eth_hdr *)&uip_buf[0])
+  uip_len = ethernet_devicedrver_poll();
+  if(uip_len > 0) {
+    if(BUF->type == HTONS(UIP_ETHTYPE_IP)) {
+      uip_arp_ipin();
+      uip_input();
+      if(uip_len > 0) {
+        uip_arp_out();
+	ethernet_devicedriver_send();
+      }
+    } else if(BUF->type == HTONS(UIP_ETHTYPE_ARP)) {
+      uip_arp_arpin();
+      if(uip_len > 0) {
+	ethernet_devicedriver_send();
+      }
+    }
+ \endcode
+ *
+ * \hideinitializer
+ */
+#define uip_input()        uip_process(UIP_DATA)
+
+/**
+ * Periodic processing for a connection identified by its number.
+ *
+ * This function does the necessary periodic processing (timers,
+ * polling) for a uIP TCP conneciton, and should be called when the
+ * periodic uIP timer goes off. It should be called for every
+ * connection, regardless of whether they are open of closed.
+ *
+ * When the function returns, it may have an outbound packet waiting
+ * for service in the uIP packet buffer, and if so the uip_len
+ * variable is set to a value larger than zero. The device driver
+ * should be called to send out the packet.
+ *
+ * The ususal way of calling the function is through a for() loop like
+ * this:
+ \code
+  for(i = 0; i < UIP_CONNS; ++i) {
+    uip_periodic(i);
+    if(uip_len > 0) {
+      devicedriver_send();
+    }
+  }
+ \endcode
+ *
+ * \note If you are writing a uIP device driver that needs ARP
+ * (Address Resolution Protocol), e.g., when running uIP over
+ * Ethernet, you will need to call the uip_arp_out() function before
+ * calling the device driver:
+ \code
+  for(i = 0; i < UIP_CONNS; ++i) {
+    uip_periodic(i);
+    if(uip_len > 0) {
+      uip_arp_out();
+      ethernet_devicedriver_send();
+    }
+  }
+ \endcode
+ *
+ * \param conn The number of the connection which is to be periodically polled.
+ *
+ * \hideinitializer
+ */
+#define uip_periodic(conn) do { uip_conn = &uip_conns[conn]; \
+                                uip_process(UIP_TIMER); } while (0)
+
+/**
+ *
+ *
+ */
+#define uip_conn_active(conn) (uip_conns[conn].tcpstateflags != UIP_CLOSED)
+
+/**
+ * Perform periodic processing for a connection identified by a pointer
+ * to its structure.
+ *
+ * Same as uip_periodic() but takes a pointer to the actual uip_conn
+ * struct instead of an integer as its argument. This function can be
+ * used to force periodic processing of a specific connection.
+ *
+ * \param conn A pointer to the uip_conn struct for the connection to
+ * be processed.
+ *
+ * \hideinitializer
+ */
+#define uip_periodic_conn(conn) do { uip_conn = conn; \
+                                     uip_process(UIP_TIMER); } while (0)
+
+/**
+ * Reuqest that a particular connection should be polled.
+ *
+ * Similar to uip_periodic_conn() but does not perform any timer
+ * processing. The application is polled for new data.
+ *
+ * \param conn A pointer to the uip_conn struct for the connection to
+ * be processed.
+ *
+ * \hideinitializer
+ */
+#define uip_poll_conn(conn) do { uip_conn = conn; \
+                                 uip_process(UIP_POLL_REQUEST); } while (0)
+
+
+#if UIP_UDP
+/**
+ * Periodic processing for a UDP connection identified by its number.
+ *
+ * This function is essentially the same as uip_periodic(), but for
+ * UDP connections. It is called in a similar fashion as the
+ * uip_periodic() function:
+ \code
+  for(i = 0; i < UIP_UDP_CONNS; i++) {
+    uip_udp_periodic(i);
+    if(uip_len > 0) {
+      devicedriver_send();
+    }
+  }
+ \endcode
+ *
+ * \note As for the uip_periodic() function, special care has to be
+ * taken when using uIP together with ARP and Ethernet:
+ \code
+  for(i = 0; i < UIP_UDP_CONNS; i++) {
+    uip_udp_periodic(i);
+    if(uip_len > 0) {
+      uip_arp_out();
+      ethernet_devicedriver_send();
+    }
+  }
+ \endcode
+ *
+ * \param conn The number of the UDP connection to be processed.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_periodic(conn) do { uip_udp_conn = &uip_udp_conns[conn]; \
+                                uip_process(UIP_UDP_TIMER); } while (0)
+
+/**
+ * Periodic processing for a UDP connection identified by a pointer to
+ * its structure.
+ *
+ * Same as uip_udp_periodic() but takes a pointer to the actual
+ * uip_conn struct instead of an integer as its argument. This
+ * function can be used to force periodic processing of a specific
+ * connection.
+ *
+ * \param conn A pointer to the uip_udp_conn struct for the connection
+ * to be processed.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_periodic_conn(conn) do { uip_udp_conn = conn; \
+                                         uip_process(UIP_UDP_TIMER); } while (0)
+
+
+#endif /* UIP_UDP */
+
+/**
+ * The uIP packet buffer.
+ *
+ * The uip_buf array is used to hold incoming and outgoing
+ * packets. The device driver should place incoming data into this
+ * buffer. When sending data, the device driver should read the link
+ * level headers and the TCP/IP headers from this buffer. The size of
+ * the link level headers is configured by the UIP_LLH_LEN define.
+ *
+ * \note The application data need not be placed in this buffer, so
+ * the device driver must read it from the place pointed to by the
+ * uip_appdata pointer as illustrated by the following example:
+ \code
+ void
+ devicedriver_send(void)
+ {
+    hwsend(&uip_buf[0], UIP_LLH_LEN);
+    if(uip_len <= UIP_LLH_LEN + UIP_TCPIP_HLEN) {
+      hwsend(&uip_buf[UIP_LLH_LEN], uip_len - UIP_LLH_LEN);
+    } else {
+      hwsend(&uip_buf[UIP_LLH_LEN], UIP_TCPIP_HLEN);
+      hwsend(uip_appdata, uip_len - UIP_TCPIP_HLEN - UIP_LLH_LEN);
+    }
+ }
+ \endcode
+ */
+#ifndef UIP_CONF_EXTERNAL_BUFFER
+	extern u8_t uip_buf[UIP_BUFSIZE+2];
+#else
+	extern unsigned char *uip_buf;
+#endif
+
+/** @} */
+
+/*---------------------------------------------------------------------------*/
+/* Functions that are used by the uIP application program. Opening and
+ * closing connections, sending and receiving data, etc. is all
+ * handled by the functions below.
+*/
+/**
+ * \defgroup uipappfunc uIP application functions
+ * @{
+ *
+ * Functions used by an application running of top of uIP.
+ */
+
+/**
+ * Start listening to the specified port.
+ *
+ * \note Since this function expects the port number in network byte
+ * order, a conversion using HTONS() or htons() is necessary.
+ *
+ \code
+ uip_listen(HTONS(80));
+ \endcode
+ *
+ * \param port A 16-bit port number in network byte order.
+ */
+void uip_listen(u16_t port);
+
+/**
+ * Stop listening to the specified port.
+ *
+ * \note Since this function expects the port number in network byte
+ * order, a conversion using HTONS() or htons() is necessary.
+ *
+ \code
+ uip_unlisten(HTONS(80));
+ \endcode
+ *
+ * \param port A 16-bit port number in network byte order.
+ */
+void uip_unlisten(u16_t port);
+
+/**
+ * Connect to a remote host using TCP.
+ *
+ * This function is used to start a new connection to the specified
+ * port on the specied host. It allocates a new connection identifier,
+ * sets the connection to the SYN_SENT state and sets the
+ * retransmission timer to 0. This will cause a TCP SYN segment to be
+ * sent out the next time this connection is periodically processed,
+ * which usually is done within 0.5 seconds after the call to
+ * uip_connect().
+ *
+ * \note This function is avaliable only if support for active open
+ * has been configured by defining UIP_ACTIVE_OPEN to 1 in uipopt.h.
+ *
+ * \note Since this function requires the port number to be in network
+ * byte order, a conversion using HTONS() or htons() is necessary.
+ *
+ \code
+ uip_ipaddr_t ipaddr;
+
+ uip_ipaddr(&ipaddr, 192,168,1,2);
+ uip_connect(&ipaddr, HTONS(80));
+ \endcode
+ *
+ * \param ripaddr The IP address of the remote hot.
+ *
+ * \param port A 16-bit port number in network byte order.
+ *
+ * \return A pointer to the uIP connection identifier for the new connection,
+ * or NULL if no connection could be allocated.
+ *
+ */
+struct uip_conn *uip_connect(uip_ipaddr_t *ripaddr, u16_t port);
+
+
+
+/**
+ * \internal
+ *
+ * Check if a connection has outstanding (i.e., unacknowledged) data.
+ *
+ * \param conn A pointer to the uip_conn structure for the connection.
+ *
+ * \hideinitializer
+ */
+#define uip_outstanding(conn) ((conn)->len)
+
+/**
+ * Send data on the current connection.
+ *
+ * This function is used to send out a single segment of TCP
+ * data. Only applications that have been invoked by uIP for event
+ * processing can send data.
+ *
+ * The amount of data that actually is sent out after a call to this
+ * funcion is determined by the maximum amount of data TCP allows. uIP
+ * will automatically crop the data so that only the appropriate
+ * amount of data is sent. The function uip_mss() can be used to query
+ * uIP for the amount of data that actually will be sent.
+ *
+ * \note This function does not guarantee that the sent data will
+ * arrive at the destination. If the data is lost in the network, the
+ * application will be invoked with the uip_rexmit() event being
+ * set. The application will then have to resend the data using this
+ * function.
+ *
+ * \param data A pointer to the data which is to be sent.
+ *
+ * \param len The maximum amount of data bytes to be sent.
+ *
+ * \hideinitializer
+ */
+void uip_send(const void *data, int len);
+
+/**
+ * The length of any incoming data that is currently avaliable (if avaliable)
+ * in the uip_appdata buffer.
+ *
+ * The test function uip_data() must first be used to check if there
+ * is any data available at all.
+ *
+ * \hideinitializer
+ */
+/*void uip_datalen(void);*/
+#define uip_datalen()       uip_len
+
+/**
+ * The length of any out-of-band data (urgent data) that has arrived
+ * on the connection.
+ *
+ * \note The configuration parameter UIP_URGDATA must be set for this
+ * function to be enabled.
+ *
+ * \hideinitializer
+ */
+#define uip_urgdatalen()    uip_urglen
+
+/**
+ * Close the current connection.
+ *
+ * This function will close the current connection in a nice way.
+ *
+ * \hideinitializer
+ */
+#define uip_close()         (uip_flags = UIP_CLOSE)
+
+/**
+ * Abort the current connection.
+ *
+ * This function will abort (reset) the current connection, and is
+ * usually used when an error has occured that prevents using the
+ * uip_close() function.
+ *
+ * \hideinitializer
+ */
+#define uip_abort()         (uip_flags = UIP_ABORT)
+
+/**
+ * Tell the sending host to stop sending data.
+ *
+ * This function will close our receiver's window so that we stop
+ * receiving data for the current connection.
+ *
+ * \hideinitializer
+ */
+#define uip_stop()          (uip_conn->tcpstateflags |= UIP_STOPPED)
+
+/**
+ * Find out if the current connection has been previously stopped with
+ * uip_stop().
+ *
+ * \hideinitializer
+ */
+#define uip_stopped(conn)   ((conn)->tcpstateflags & UIP_STOPPED)
+
+/**
+ * Restart the current connection, if is has previously been stopped
+ * with uip_stop().
+ *
+ * This function will open the receiver's window again so that we
+ * start receiving data for the current connection.
+ *
+ * \hideinitializer
+ */
+#define uip_restart()         do { uip_flags |= UIP_NEWDATA; \
+                                   uip_conn->tcpstateflags &= ~UIP_STOPPED; \
+                              } while(0)
+
+
+/* uIP tests that can be made to determine in what state the current
+   connection is, and what the application function should do. */
+
+/**
+ * Is the current connection a UDP connection?
+ *
+ * This function checks whether the current connection is a UDP connection.
+ *
+ * \hideinitializer
+ *
+ */
+#define uip_udpconnection() (uip_conn == NULL)
+
+/**
+ * Is new incoming data available?
+ *
+ * Will reduce to non-zero if there is new data for the application
+ * present at the uip_appdata pointer. The size of the data is
+ * avaliable through the uip_len variable.
+ *
+ * \hideinitializer
+ */
+#define uip_newdata()   (uip_flags & UIP_NEWDATA)
+
+/**
+ * Has previously sent data been acknowledged?
+ *
+ * Will reduce to non-zero if the previously sent data has been
+ * acknowledged by the remote host. This means that the application
+ * can send new data.
+ *
+ * \hideinitializer
+ */
+#define uip_acked()   (uip_flags & UIP_ACKDATA)
+
+/**
+ * Has the connection just been connected?
+ *
+ * Reduces to non-zero if the current connection has been connected to
+ * a remote host. This will happen both if the connection has been
+ * actively opened (with uip_connect()) or passively opened (with
+ * uip_listen()).
+ *
+ * \hideinitializer
+ */
+#define uip_connected() (uip_flags & UIP_CONNECTED)
+
+/**
+ * Has the connection been closed by the other end?
+ *
+ * Is non-zero if the connection has been closed by the remote
+ * host. The application may then do the necessary clean-ups.
+ *
+ * \hideinitializer
+ */
+#define uip_closed()    (uip_flags & UIP_CLOSE)
+
+/**
+ * Has the connection been aborted by the other end?
+ *
+ * Non-zero if the current connection has been aborted (reset) by the
+ * remote host.
+ *
+ * \hideinitializer
+ */
+#define uip_aborted()    (uip_flags & UIP_ABORT)
+
+/**
+ * Has the connection timed out?
+ *
+ * Non-zero if the current connection has been aborted due to too many
+ * retransmissions.
+ *
+ * \hideinitializer
+ */
+#define uip_timedout()    (uip_flags & UIP_TIMEDOUT)
+
+/**
+ * Do we need to retransmit previously data?
+ *
+ * Reduces to non-zero if the previously sent data has been lost in
+ * the network, and the application should retransmit it. The
+ * application should send the exact same data as it did the last
+ * time, using the uip_send() function.
+ *
+ * \hideinitializer
+ */
+#define uip_rexmit()     (uip_flags & UIP_REXMIT)
+
+/**
+ * Is the connection being polled by uIP?
+ *
+ * Is non-zero if the reason the application is invoked is that the
+ * current connection has been idle for a while and should be
+ * polled.
+ *
+ * The polling event can be used for sending data without having to
+ * wait for the remote host to send data.
+ *
+ * \hideinitializer
+ */
+#define uip_poll()       (uip_flags & UIP_POLL)
+
+/**
+ * Get the initial maxium segment size (MSS) of the current
+ * connection.
+ *
+ * \hideinitializer
+ */
+#define uip_initialmss()             (uip_conn->initialmss)
+
+/**
+ * Get the current maxium segment size that can be sent on the current
+ * connection.
+ *
+ * The current maxiumum segment size that can be sent on the
+ * connection is computed from the receiver's window and the MSS of
+ * the connection (which also is available by calling
+ * uip_initialmss()).
+ *
+ * \hideinitializer
+ */
+#define uip_mss()             (uip_conn->mss)
+
+/**
+ * Set up a new UDP connection.
+ *
+ * This function sets up a new UDP connection. The function will
+ * automatically allocate an unused local port for the new
+ * connection. However, another port can be chosen by using the
+ * uip_udp_bind() call, after the uip_udp_new() function has been
+ * called.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t addr;
+ struct uip_udp_conn *c;
+
+ uip_ipaddr(&addr, 192,168,2,1);
+ c = uip_udp_new(&addr, HTONS(12345));
+ if(c != NULL) {
+   uip_udp_bind(c, HTONS(12344));
+ }
+ \endcode
+ * \param ripaddr The IP address of the remote host.
+ *
+ * \param rport The remote port number in network byte order.
+ *
+ * \return The uip_udp_conn structure for the new connection or NULL
+ * if no connection could be allocated.
+ */
+struct uip_udp_conn *uip_udp_new(uip_ipaddr_t *ripaddr, u16_t rport);
+
+/**
+ * Removed a UDP connection.
+ *
+ * \param conn A pointer to the uip_udp_conn structure for the connection.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_remove(conn) (conn)->lport = 0
+
+/**
+ * Bind a UDP connection to a local port.
+ *
+ * \param conn A pointer to the uip_udp_conn structure for the
+ * connection.
+ *
+ * \param port The local port number, in network byte order.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_bind(conn, port) (conn)->lport = port
+
+/**
+ * Send a UDP datagram of length len on the current connection.
+ *
+ * This function can only be called in response to a UDP event (poll
+ * or newdata). The data must be present in the uip_buf buffer, at the
+ * place pointed to by the uip_appdata pointer.
+ *
+ * \param len The length of the data in the uip_buf buffer.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_send(len) uip_send((char *)uip_appdata, len)
+
+/** @} */
+
+/* uIP convenience and converting functions. */
+
+/**
+ * \defgroup uipconvfunc uIP conversion functions
+ * @{
+ *
+ * These functions can be used for converting between different data
+ * formats used by uIP.
+ */
+
+/**
+ * Construct an IP address from four bytes.
+ *
+ * This function constructs an IP address of the type that uIP handles
+ * internally from four bytes. The function is handy for specifying IP
+ * addresses to use with e.g. the uip_connect() function.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr;
+ struct uip_conn *c;
+
+ uip_ipaddr(&ipaddr, 192,168,1,2);
+ c = uip_connect(&ipaddr, HTONS(80));
+ \endcode
+ *
+ * \param addr A pointer to a uip_ipaddr_t variable that will be
+ * filled in with the IP address.
+ *
+ * \param addr0 The first octet of the IP address.
+ * \param addr1 The second octet of the IP address.
+ * \param addr2 The third octet of the IP address.
+ * \param addr3 The forth octet of the IP address.
+ *
+ * \hideinitializer
+ */
+#define uip_ipaddr(addr, addr0,addr1,addr2,addr3) do { \
+                     ((u16_t *)(addr))[0] = HTONS(((addr0) << 8) | (addr1)); \
+                     ((u16_t *)(addr))[1] = HTONS(((addr2) << 8) | (addr3)); \
+                  } while(0)
+
+/**
+ * Construct an IPv6 address from eight 16-bit words.
+ *
+ * This function constructs an IPv6 address.
+ *
+ * \hideinitializer
+ */
+#define uip_ip6addr(addr, addr0,addr1,addr2,addr3,addr4,addr5,addr6,addr7) do { \
+                     ((u16_t *)(addr))[0] = HTONS((addr0)); \
+                     ((u16_t *)(addr))[1] = HTONS((addr1)); \
+                     ((u16_t *)(addr))[2] = HTONS((addr2)); \
+                     ((u16_t *)(addr))[3] = HTONS((addr3)); \
+                     ((u16_t *)(addr))[4] = HTONS((addr4)); \
+                     ((u16_t *)(addr))[5] = HTONS((addr5)); \
+                     ((u16_t *)(addr))[6] = HTONS((addr6)); \
+                     ((u16_t *)(addr))[7] = HTONS((addr7)); \
+                  } while(0)
+
+/**
+ * Copy an IP address to another IP address.
+ *
+ * Copies an IP address from one place to another.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr1, ipaddr2;
+
+ uip_ipaddr(&ipaddr1, 192,16,1,2);
+ uip_ipaddr_copy(&ipaddr2, &ipaddr1);
+ \endcode
+ *
+ * \param dest The destination for the copy.
+ * \param src The source from where to copy.
+ *
+ * \hideinitializer
+ */
+#if !UIP_CONF_IPV6
+#define uip_ipaddr_copy(dest, src) do { \
+                     ((u16_t *)dest)[0] = ((u16_t *)src)[0]; \
+                     ((u16_t *)dest)[1] = ((u16_t *)src)[1]; \
+                  } while(0)
+#else /* !UIP_CONF_IPV6 */
+#define uip_ipaddr_copy(dest, src) memcpy(dest, src, sizeof(uip_ip6addr_t))
+#endif /* !UIP_CONF_IPV6 */
+
+/**
+ * Compare two IP addresses
+ *
+ * Compares two IP addresses.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr1, ipaddr2;
+
+ uip_ipaddr(&ipaddr1, 192,16,1,2);
+ if(uip_ipaddr_cmp(&ipaddr2, &ipaddr1)) {
+    printf("They are the same");
+ }
+ \endcode
+ *
+ * \param addr1 The first IP address.
+ * \param addr2 The second IP address.
+ *
+ * \hideinitializer
+ */
+#if !UIP_CONF_IPV6
+#define uip_ipaddr_cmp(addr1, addr2) (((u16_t *)addr1)[0] == ((u16_t *)addr2)[0] && \
+				      ((u16_t *)addr1)[1] == ((u16_t *)addr2)[1])
+#else /* !UIP_CONF_IPV6 */
+#define uip_ipaddr_cmp(addr1, addr2) (memcmp(addr1, addr2, sizeof(uip_ip6addr_t)) == 0)
+#endif /* !UIP_CONF_IPV6 */
+
+/**
+ * Compare two IP addresses with netmasks
+ *
+ * Compares two IP addresses with netmasks. The masks are used to mask
+ * out the bits that are to be compared.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr1, ipaddr2, mask;
+
+ uip_ipaddr(&mask, 255,255,255,0);
+ uip_ipaddr(&ipaddr1, 192,16,1,2);
+ uip_ipaddr(&ipaddr2, 192,16,1,3);
+ if(uip_ipaddr_maskcmp(&ipaddr1, &ipaddr2, &mask)) {
+    printf("They are the same");
+ }
+ \endcode
+ *
+ * \param addr1 The first IP address.
+ * \param addr2 The second IP address.
+ * \param mask The netmask.
+ *
+ * \hideinitializer
+ */
+#define uip_ipaddr_maskcmp(addr1, addr2, mask) \
+                          (((((u16_t *)addr1)[0] & ((u16_t *)mask)[0]) == \
+                            (((u16_t *)addr2)[0] & ((u16_t *)mask)[0])) && \
+                           ((((u16_t *)addr1)[1] & ((u16_t *)mask)[1]) == \
+                            (((u16_t *)addr2)[1] & ((u16_t *)mask)[1])))
+
+
+/**
+ * Mask out the network part of an IP address.
+ *
+ * Masks out the network part of an IP address, given the address and
+ * the netmask.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr1, ipaddr2, netmask;
+
+ uip_ipaddr(&ipaddr1, 192,16,1,2);
+ uip_ipaddr(&netmask, 255,255,255,0);
+ uip_ipaddr_mask(&ipaddr2, &ipaddr1, &netmask);
+ \endcode
+ *
+ * In the example above, the variable "ipaddr2" will contain the IP
+ * address 192.168.1.0.
+ *
+ * \param dest Where the result is to be placed.
+ * \param src The IP address.
+ * \param mask The netmask.
+ *
+ * \hideinitializer
+ */
+#define uip_ipaddr_mask(dest, src, mask) do { \
+                     ((u16_t *)dest)[0] = ((u16_t *)src)[0] & ((u16_t *)mask)[0]; \
+                     ((u16_t *)dest)[1] = ((u16_t *)src)[1] & ((u16_t *)mask)[1]; \
+                  } while(0)
+
+/**
+ * Pick the first octet of an IP address.
+ *
+ * Picks out the first octet of an IP address.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr;
+ u8_t octet;
+
+ uip_ipaddr(&ipaddr, 1,2,3,4);
+ octet = uip_ipaddr1(&ipaddr);
+ \endcode
+ *
+ * In the example above, the variable "octet" will contain the value 1.
+ *
+ * \hideinitializer
+ */
+#define uip_ipaddr1(addr) (htons(((u16_t *)(addr))[0]) >> 8)
+
+/**
+ * Pick the second octet of an IP address.
+ *
+ * Picks out the second octet of an IP address.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr;
+ u8_t octet;
+
+ uip_ipaddr(&ipaddr, 1,2,3,4);
+ octet = uip_ipaddr2(&ipaddr);
+ \endcode
+ *
+ * In the example above, the variable "octet" will contain the value 2.
+ *
+ * \hideinitializer
+ */
+#define uip_ipaddr2(addr) (htons(((u16_t *)(addr))[0]) & 0xff)
+
+/**
+ * Pick the third octet of an IP address.
+ *
+ * Picks out the third octet of an IP address.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr;
+ u8_t octet;
+
+ uip_ipaddr(&ipaddr, 1,2,3,4);
+ octet = uip_ipaddr3(&ipaddr);
+ \endcode
+ *
+ * In the example above, the variable "octet" will contain the value 3.
+ *
+ * \hideinitializer
+ */
+#define uip_ipaddr3(addr) (htons(((u16_t *)(addr))[1]) >> 8)
+
+/**
+ * Pick the fourth octet of an IP address.
+ *
+ * Picks out the fourth octet of an IP address.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr;
+ u8_t octet;
+
+ uip_ipaddr(&ipaddr, 1,2,3,4);
+ octet = uip_ipaddr4(&ipaddr);
+ \endcode
+ *
+ * In the example above, the variable "octet" will contain the value 4.
+ *
+ * \hideinitializer
+ */
+#define uip_ipaddr4(addr) (htons(((u16_t *)(addr))[1]) & 0xff)
+
+/**
+ * Convert 16-bit quantity from host byte order to network byte order.
+ *
+ * This macro is primarily used for converting constants from host
+ * byte order to network byte order. For converting variables to
+ * network byte order, use the htons() function instead.
+ *
+ * \hideinitializer
+ */
+#ifndef HTONS
+#   if UIP_BYTE_ORDER == UIP_BIG_ENDIAN
+#      define HTONS(n) (n)
+#   else /* UIP_BYTE_ORDER == UIP_BIG_ENDIAN */
+#      define HTONS(n) (u16_t)((((u16_t) (n)) << 8) | (((u16_t) (n)) >> 8))
+#   endif /* UIP_BYTE_ORDER == UIP_BIG_ENDIAN */
+#else
+#error "HTONS already defined!"
+#endif /* HTONS */
+
+/**
+ * Convert 16-bit quantity from host byte order to network byte order.
+ *
+ * This function is primarily used for converting variables from host
+ * byte order to network byte order. For converting constants to
+ * network byte order, use the HTONS() macro instead.
+ */
+#ifndef htons
+u16_t htons(u16_t val);
+#endif /* htons */
+#ifndef ntohs
+#define ntohs htons
+#endif
+
+/** @} */
+
+/**
+ * Pointer to the application data in the packet buffer.
+ *
+ * This pointer points to the application data when the application is
+ * called. If the application wishes to send data, the application may
+ * use this space to write the data into before calling uip_send().
+ */
+extern void *uip_appdata;
+
+#if UIP_URGDATA > 0
+/* u8_t *uip_urgdata:
+ *
+ * This pointer points to any urgent data that has been received. Only
+ * present if compiled with support for urgent data (UIP_URGDATA).
+ */
+extern void *uip_urgdata;
+#endif /* UIP_URGDATA > 0 */
+
+
+/**
+ * \defgroup uipdrivervars Variables used in uIP device drivers
+ * @{
+ *
+ * uIP has a few global variables that are used in device drivers for
+ * uIP.
+ */
+
+/**
+ * The length of the packet in the uip_buf buffer.
+ *
+ * The global variable uip_len holds the length of the packet in the
+ * uip_buf buffer.
+ *
+ * When the network device driver calls the uIP input function,
+ * uip_len should be set to the length of the packet in the uip_buf
+ * buffer.
+ *
+ * When sending packets, the device driver should use the contents of
+ * the uip_len variable to determine the length of the outgoing
+ * packet.
+ *
+ */
+extern u16_t uip_len;
+
+/** @} */
+
+#if UIP_URGDATA > 0
+extern u16_t uip_urglen, uip_surglen;
+#endif /* UIP_URGDATA > 0 */
+
+
+/**
+ * Representation of a uIP TCP connection.
+ *
+ * The uip_conn structure is used for identifying a connection. All
+ * but one field in the structure are to be considered read-only by an
+ * application. The only exception is the appstate field whos purpose
+ * is to let the application store application-specific state (e.g.,
+ * file pointers) for the connection. The type of this field is
+ * configured in the "uipopt.h" header file.
+ */
+struct uip_conn {
+  uip_ipaddr_t ripaddr;   /**< The IP address of the remote host. */
+
+  u16_t lport;        /**< The local TCP port, in network byte order. */
+  u16_t rport;        /**< The local remote TCP port, in network byte
+			 order. */
+
+  u8_t rcv_nxt[4];    /**< The sequence number that we expect to
+			 receive next. */
+  u8_t snd_nxt[4];    /**< The sequence number that was last sent by
+                         us. */
+  u16_t len;          /**< Length of the data that was previously sent. */
+  u16_t mss;          /**< Current maximum segment size for the
+			 connection. */
+  u16_t initialmss;   /**< Initial maximum segment size for the
+			 connection. */
+  u8_t sa;            /**< Retransmission time-out calculation state
+			 variable. */
+  u8_t sv;            /**< Retransmission time-out calculation state
+			 variable. */
+  u8_t rto;           /**< Retransmission time-out. */
+  u8_t tcpstateflags; /**< TCP state and flags. */
+  u8_t timer;         /**< The retransmission timer. */
+  u8_t nrtx;          /**< The number of retransmissions for the last
+			 segment sent. */
+
+  /** The application state. */
+  uip_tcp_appstate_t appstate;
+};
+
+
+/**
+ * Pointer to the current TCP connection.
+ *
+ * The uip_conn pointer can be used to access the current TCP
+ * connection.
+ */
+extern struct uip_conn *uip_conn;
+/* The array containing all uIP connections. */
+extern struct uip_conn uip_conns[UIP_CONNS];
+/**
+ * \addtogroup uiparch
+ * @{
+ */
+
+/**
+ * 4-byte array used for the 32-bit sequence number calculations.
+ */
+extern u8_t uip_acc32[4];
+
+/** @} */
+
+
+#if UIP_UDP
+/**
+ * Representation of a uIP UDP connection.
+ */
+struct uip_udp_conn {
+  uip_ipaddr_t ripaddr;   /**< The IP address of the remote peer. */
+  u16_t lport;        /**< The local port number in network byte order. */
+  u16_t rport;        /**< The remote port number in network byte order. */
+  u8_t  ttl;          /**< Default time-to-live. */
+
+  /** The application state. */
+  uip_udp_appstate_t appstate;
+};
+
+/**
+ * The current UDP connection.
+ */
+extern struct uip_udp_conn *uip_udp_conn;
+extern struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS];
+#endif /* UIP_UDP */
+
+/**
+ * The structure holding the TCP/IP statistics that are gathered if
+ * UIP_STATISTICS is set to 1.
+ *
+ */
+struct uip_stats {
+  struct {
+    uip_stats_t drop;     /**< Number of dropped packets at the IP
+			     layer. */
+    uip_stats_t recv;     /**< Number of received packets at the IP
+			     layer. */
+    uip_stats_t sent;     /**< Number of sent packets at the IP
+			     layer. */
+    uip_stats_t vhlerr;   /**< Number of packets dropped due to wrong
+			     IP version or header length. */
+    uip_stats_t hblenerr; /**< Number of packets dropped due to wrong
+			     IP length, high byte. */
+    uip_stats_t lblenerr; /**< Number of packets dropped due to wrong
+			     IP length, low byte. */
+    uip_stats_t fragerr;  /**< Number of packets dropped since they
+			     were IP fragments. */
+    uip_stats_t chkerr;   /**< Number of packets dropped due to IP
+			     checksum errors. */
+    uip_stats_t protoerr; /**< Number of packets dropped since they
+			     were neither ICMP, UDP nor TCP. */
+  } ip;                   /**< IP statistics. */
+  struct {
+    uip_stats_t drop;     /**< Number of dropped ICMP packets. */
+    uip_stats_t recv;     /**< Number of received ICMP packets. */
+    uip_stats_t sent;     /**< Number of sent ICMP packets. */
+    uip_stats_t typeerr;  /**< Number of ICMP packets with a wrong
+			     type. */
+  } icmp;                 /**< ICMP statistics. */
+  struct {
+    uip_stats_t drop;     /**< Number of dropped TCP segments. */
+    uip_stats_t recv;     /**< Number of recived TCP segments. */
+    uip_stats_t sent;     /**< Number of sent TCP segments. */
+    uip_stats_t chkerr;   /**< Number of TCP segments with a bad
+			     checksum. */
+    uip_stats_t ackerr;   /**< Number of TCP segments with a bad ACK
+			     number. */
+    uip_stats_t rst;      /**< Number of recevied TCP RST (reset) segments. */
+    uip_stats_t rexmit;   /**< Number of retransmitted TCP segments. */
+    uip_stats_t syndrop;  /**< Number of dropped SYNs due to too few
+			     connections was avaliable. */
+    uip_stats_t synrst;   /**< Number of SYNs for closed ports,
+			     triggering a RST. */
+  } tcp;                  /**< TCP statistics. */
+#if UIP_UDP
+  struct {
+    uip_stats_t drop;     /**< Number of dropped UDP segments. */
+    uip_stats_t recv;     /**< Number of recived UDP segments. */
+    uip_stats_t sent;     /**< Number of sent UDP segments. */
+    uip_stats_t chkerr;   /**< Number of UDP segments with a bad
+			     checksum. */
+  } udp;                  /**< UDP statistics. */
+#endif /* UIP_UDP */
+};
+
+/**
+ * The uIP TCP/IP statistics.
+ *
+ * This is the variable in which the uIP TCP/IP statistics are gathered.
+ */
+extern struct uip_stats uip_stat;
+
+
+/*---------------------------------------------------------------------------*/
+/* All the stuff below this point is internal to uIP and should not be
+ * used directly by an application or by a device driver.
+ */
+/*---------------------------------------------------------------------------*/
+/* u8_t uip_flags:
+ *
+ * When the application is called, uip_flags will contain the flags
+ * that are defined in this file. Please read below for more
+ * infomation.
+ */
+extern u8_t uip_flags;
+
+/* The following flags may be set in the global variable uip_flags
+   before calling the application callback. The UIP_ACKDATA,
+   UIP_NEWDATA, and UIP_CLOSE flags may both be set at the same time,
+   whereas the others are mutualy exclusive. Note that these flags
+   should *NOT* be accessed directly, but only through the uIP
+   functions/macros. */
+
+#define UIP_ACKDATA   1     /* Signifies that the outstanding data was
+			       acked and the application should send
+			       out new data instead of retransmitting
+			       the last data. */
+#define UIP_NEWDATA   2     /* Flags the fact that the peer has sent
+			       us new data. */
+#define UIP_REXMIT    4     /* Tells the application to retransmit the
+			       data that was last sent. */
+#define UIP_POLL      8     /* Used for polling the application, to
+			       check if the application has data that
+			       it wants to send. */
+#define UIP_CLOSE     16    /* The remote host has closed the
+			       connection, thus the connection has
+			       gone away. Or the application signals
+			       that it wants to close the
+			       connection. */
+#define UIP_ABORT     32    /* The remote host has aborted the
+			       connection, thus the connection has
+			       gone away. Or the application signals
+			       that it wants to abort the
+			       connection. */
+#define UIP_CONNECTED 64    /* We have got a connection from a remote
+                               host and have set up a new connection
+                               for it, or an active connection has
+                               been successfully established. */
+
+#define UIP_TIMEDOUT  128   /* The connection has been aborted due to
+			       too many retransmissions. */
+
+/* uip_process(flag):
+ *
+ * The actual uIP function which does all the work.
+ */
+void uip_process(u8_t flag);
+
+/* The following flags are passed as an argument to the uip_process()
+   function. They are used to distinguish between the two cases where
+   uip_process() is called. It can be called either because we have
+   incoming data that should be processed, or because the periodic
+   timer has fired. These values are never used directly, but only in
+   the macrose defined in this file. */
+
+#define UIP_DATA          1     /* Tells uIP that there is incoming
+				   data in the uip_buf buffer. The
+				   length of the data is stored in the
+				   global variable uip_len. */
+#define UIP_TIMER         2     /* Tells uIP that the periodic timer
+				   has fired. */
+#define UIP_POLL_REQUEST  3     /* Tells uIP that a connection should
+				   be polled. */
+#define UIP_UDP_SEND_CONN 4     /* Tells uIP that a UDP datagram
+				   should be constructed in the
+				   uip_buf buffer. */
+#if UIP_UDP
+#define UIP_UDP_TIMER     5
+#endif /* UIP_UDP */
+
+/* The TCP states used in the uip_conn->tcpstateflags. */
+#define UIP_CLOSED      0
+#define UIP_SYN_RCVD    1
+#define UIP_SYN_SENT    2
+#define UIP_ESTABLISHED 3
+#define UIP_FIN_WAIT_1  4
+#define UIP_FIN_WAIT_2  5
+#define UIP_CLOSING     6
+#define UIP_TIME_WAIT   7
+#define UIP_LAST_ACK    8
+#define UIP_TS_MASK     15
+
+#define UIP_STOPPED      16
+
+/* The TCP and IP headers. */
+
+#ifdef __ICCARM__
+	#pragma pack(1)
+#endif
+
+struct uip_tcpip_hdr {
+#if UIP_CONF_IPV6
+  /* IPv6 header. */
+  u8_t vtc,
+    tcflow;
+  u16_t flow;
+  u8_t len[2];
+  u8_t proto, ttl;
+  uip_ip6addr_t srcipaddr, destipaddr;
+#else /* UIP_CONF_IPV6 */
+  /* IPv4 header. */
+  u8_t vhl,
+    tos,
+    len[2],
+    ipid[2],
+    ipoffset[2],
+    ttl,
+    proto;
+  u16_t ipchksum;
+  u16_t srcipaddr[2],
+    destipaddr[2];
+#endif /* UIP_CONF_IPV6 */
+
+  /* TCP header. */
+  u16_t srcport,
+    destport;
+  u8_t seqno[4],
+    ackno[4],
+    tcpoffset,
+    flags,
+    wnd[2];
+  u16_t tcpchksum;
+  u8_t urgp[2];
+  u8_t optdata[4];
+} PACK_STRUCT_END;
+
+#ifdef __ICCARM__
+	#pragma pack()
+#endif
+
+/* The ICMP and IP headers. */
+#ifdef __ICCARM__
+	#pragma pack(1)
+#endif
+
+struct uip_icmpip_hdr {
+#if UIP_CONF_IPV6
+  /* IPv6 header. */
+  u8_t vtc,
+    tcf;
+  u16_t flow;
+  u8_t len[2];
+  u8_t proto, ttl;
+  uip_ip6addr_t srcipaddr, destipaddr;
+#else /* UIP_CONF_IPV6 */
+  /* IPv4 header. */
+  u8_t vhl,
+    tos,
+    len[2],
+    ipid[2],
+    ipoffset[2],
+    ttl,
+    proto;
+  u16_t ipchksum;
+  u16_t srcipaddr[2],
+    destipaddr[2];
+#endif /* UIP_CONF_IPV6 */
+
+  /* ICMP (echo) header. */
+  u8_t type, icode;
+  u16_t icmpchksum;
+#if !UIP_CONF_IPV6
+  u16_t id, seqno;
+#else /* !UIP_CONF_IPV6 */
+  u8_t flags, reserved1, reserved2, reserved3;
+  u8_t icmp6data[16];
+  u8_t options[1];
+#endif /* !UIP_CONF_IPV6 */
+} PACK_STRUCT_END;
+
+#ifdef __ICCARM__
+	#pragma pack()
+#endif
+
+
+/* The UDP and IP headers. */
+#ifdef __ICCARM__
+	#pragma pack(1)
+#endif
+
+struct uip_udpip_hdr {
+#if UIP_CONF_IPV6
+  /* IPv6 header. */
+  u8_t vtc,
+    tcf;
+  u16_t flow;
+  u8_t len[2];
+  u8_t proto, ttl;
+  uip_ip6addr_t srcipaddr, destipaddr;
+#else /* UIP_CONF_IPV6 */
+  /* IP header. */
+  u8_t vhl,
+    tos,
+    len[2],
+    ipid[2],
+    ipoffset[2],
+    ttl,
+    proto;
+  u16_t ipchksum;
+  u16_t srcipaddr[2],
+    destipaddr[2];
+#endif /* UIP_CONF_IPV6 */
+
+  /* UDP header. */
+  u16_t srcport,
+    destport;
+  u16_t udplen;
+  u16_t udpchksum;
+} PACK_STRUCT_END;
+
+#ifdef __ICCARM__
+	#pragma pack()
+#endif
+
+
+
+/**
+ * The buffer size available for user data in the \ref uip_buf buffer.
+ *
+ * This macro holds the available size for user data in the \ref
+ * uip_buf buffer. The macro is intended to be used for checking
+ * bounds of available user data.
+ *
+ * Example:
+ \code
+ snprintf(uip_appdata, UIP_APPDATA_SIZE, "%u\n", i);
+ \endcode
+ *
+ * \hideinitializer
+ */
+#define UIP_APPDATA_SIZE (UIP_BUFSIZE - UIP_LLH_LEN - UIP_TCPIP_HLEN)
+
+
+#define UIP_PROTO_ICMP  1
+#define UIP_PROTO_TCP   6
+#define UIP_PROTO_UDP   17
+#define UIP_PROTO_ICMP6 58
+
+/* Header sizes. */
+#if UIP_CONF_IPV6
+#define UIP_IPH_LEN    40
+#else /* UIP_CONF_IPV6 */
+#define UIP_IPH_LEN    20    /* Size of IP header */
+#endif /* UIP_CONF_IPV6 */
+#define UIP_UDPH_LEN    8    /* Size of UDP header */
+#define UIP_TCPH_LEN   20    /* Size of TCP header */
+#define UIP_IPUDPH_LEN (UIP_UDPH_LEN + UIP_IPH_LEN)    /* Size of IP +
+							  UDP
+							  header */
+#define UIP_IPTCPH_LEN (UIP_TCPH_LEN + UIP_IPH_LEN)    /* Size of IP +
+							  TCP
+							  header */
+#define UIP_TCPIP_HLEN UIP_IPTCPH_LEN
+
+
+#if UIP_FIXEDADDR
+extern const uip_ipaddr_t uip_hostaddr, uip_netmask, uip_draddr;
+#else /* UIP_FIXEDADDR */
+extern uip_ipaddr_t uip_hostaddr, uip_netmask, uip_draddr;
+#endif /* UIP_FIXEDADDR */
+
+
+
+/**
+ * Representation of a 48-bit Ethernet address.
+ */
+#ifdef __ICCARM__
+	#pragma pack(1)
+#endif
+
+struct uip_eth_addr {
+  u8_t addr[6];
+} PACK_STRUCT_END;
+
+#ifdef __ICCARM__
+	#pragma pack()
+#endif
+
+/**
+ * Calculate the Internet checksum over a buffer.
+ *
+ * The Internet checksum is the one's complement of the one's
+ * complement sum of all 16-bit words in the buffer.
+ *
+ * See RFC1071.
+ *
+ * \param buf A pointer to the buffer over which the checksum is to be
+ * computed.
+ *
+ * \param len The length of the buffer over which the checksum is to
+ * be computed.
+ *
+ * \return The Internet checksum of the buffer.
+ */
+u16_t uip_chksum(u16_t *buf, u16_t len);
+
+/**
+ * Calculate the IP header checksum of the packet header in uip_buf.
+ *
+ * The IP header checksum is the Internet checksum of the 20 bytes of
+ * the IP header.
+ *
+ * \return The IP header checksum of the IP header in the uip_buf
+ * buffer.
+ */
+u16_t uip_ipchksum(void);
+
+/**
+ * Calculate the TCP checksum of the packet in uip_buf and uip_appdata.
+ *
+ * The TCP checksum is the Internet checksum of data contents of the
+ * TCP segment, and a pseudo-header as defined in RFC793.
+ *
+ * \return The TCP checksum of the TCP segment in uip_buf and pointed
+ * to by uip_appdata.
+ */
+u16_t uip_tcpchksum(void);
+
+/**
+ * Calculate the UDP checksum of the packet in uip_buf and uip_appdata.
+ *
+ * The UDP checksum is the Internet checksum of data contents of the
+ * UDP segment, and a pseudo-header as defined in RFC768.
+ *
+ * \return The UDP checksum of the UDP segment in uip_buf and pointed
+ * to by uip_appdata.
+ */
+u16_t uip_udpchksum(void);
+
+/**
+ * Work out the fasted way of sending the data to the low level driver.
+ */
+int uip_fast_send( int xARP );
+
+#endif /* __UIP_H__ */
+
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_arch.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_arch.h
new file mode 100644
index 0000000..5ea4578
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_arch.h
@@ -0,0 +1,138 @@
+/**
+ * \addtogroup uip
+ * {@
+ */
+
+/**
+ * \defgroup uiparch Architecture specific uIP functions
+ * @{
+ *
+ * The functions in the architecture specific module implement the IP
+ * check sum and 32-bit additions.
+ *
+ * The IP checksum calculation is the most computationally expensive
+ * operation in the TCP/IP stack and it therefore pays off to
+ * implement this in efficient assembler. The purpose of the uip-arch
+ * module is to let the checksum functions to be implemented in
+ * architecture specific assembler.
+ *
+ */
+
+/**
+ * \file
+ * Declarations of architecture specific functions.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip_arch.h,v 1.2 2006/06/07 09:15:19 adam Exp $
+ *
+ */
+
+#ifndef __UIP_ARCH_H__
+#define __UIP_ARCH_H__
+
+#include "uip.h"
+
+/**
+ * Carry out a 32-bit addition.
+ *
+ * Because not all architectures for which uIP is intended has native
+ * 32-bit arithmetic, uIP uses an external C function for doing the
+ * required 32-bit additions in the TCP protocol processing. This
+ * function should add the two arguments and place the result in the
+ * global variable uip_acc32.
+ *
+ * \note The 32-bit integer pointed to by the op32 parameter and the
+ * result in the uip_acc32 variable are in network byte order (big
+ * endian).
+ *
+ * \param op32 A pointer to a 4-byte array representing a 32-bit
+ * integer in network byte order (big endian).
+ *
+ * \param op16 A 16-bit integer in host byte order.
+ */
+void uip_add32(u8_t *op32, u16_t op16);
+
+/**
+ * Calculate the Internet checksum over a buffer.
+ *
+ * The Internet checksum is the one's complement of the one's
+ * complement sum of all 16-bit words in the buffer.
+ *
+ * See RFC1071.
+ *
+ * \note This function is not called in the current version of uIP,
+ * but future versions might make use of it.
+ *
+ * \param buf A pointer to the buffer over which the checksum is to be
+ * computed.
+ *
+ * \param len The length of the buffer over which the checksum is to
+ * be computed.
+ *
+ * \return The Internet checksum of the buffer.
+ */
+u16_t uip_chksum(u16_t *buf, u16_t len);
+
+/**
+ * Calculate the IP header checksum of the packet header in uip_buf.
+ *
+ * The IP header checksum is the Internet checksum of the 20 bytes of
+ * the IP header.
+ *
+ * \return The IP header checksum of the IP header in the uip_buf
+ * buffer.
+ */
+u16_t uip_ipchksum(void);
+
+/**
+ * Calculate the TCP checksum of the packet in uip_buf and uip_appdata.
+ *
+ * The TCP checksum is the Internet checksum of data contents of the
+ * TCP segment, and a pseudo-header as defined in RFC793.
+ *
+ * \note The uip_appdata pointer that points to the packet data may
+ * point anywhere in memory, so it is not possible to simply calculate
+ * the Internet checksum of the contents of the uip_buf buffer.
+ *
+ * \return The TCP checksum of the TCP segment in uip_buf and pointed
+ * to by uip_appdata.
+ */
+u16_t uip_tcpchksum(void);
+
+u16_t uip_udpchksum(void);
+
+/** @} */
+/** @} */
+
+#endif /* __UIP_ARCH_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_arp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_arp.c
new file mode 100644
index 0000000..d105226
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_arp.c
@@ -0,0 +1,466 @@
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \defgroup uiparp uIP Address Resolution Protocol
+ * @{
+ *
+ * The Address Resolution Protocol ARP is used for mapping between IP
+ * addresses and link level addresses such as the Ethernet MAC
+ * addresses. ARP uses broadcast queries to ask for the link level
+ * address of a known IP address and the host which is configured with
+ * the IP address for which the query was meant, will respond with its
+ * link level address.
+ *
+ * \note This ARP implementation only supports Ethernet.
+ */
+
+/**
+ * \file
+ * Implementation of the ARP Address Resolution Protocol.
+ * \author Adam Dunkels 
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip_arp.c,v 1.8 2006/06/02 23:36:21 adam Exp $
+ *
+ */
+#include "uip_arp.h"
+
+#include 
+
+#ifdef __ICCARM__
+	#pragma pack( 1 )
+#endif
+struct arp_hdr
+{
+	struct uip_eth_hdr	ethhdr;
+	u16_t				hwtype;
+	u16_t				protocol;
+	u8_t				hwlen;
+	u8_t				protolen;
+	u16_t				opcode;
+	struct uip_eth_addr shwaddr;
+	u16_t				sipaddr[2];
+	struct uip_eth_addr dhwaddr;
+	u16_t				dipaddr[2];
+} PACK_STRUCT_END;
+
+#ifdef __ICCARM__
+	#pragma pack()
+#endif
+#ifdef __ICCARM__
+	#pragma pack( 1 )
+#endif
+struct ethip_hdr
+{
+	struct uip_eth_hdr	ethhdr;
+
+	/* IP header. */
+	u8_t				vhl, tos, len[2], ipid[2], ipoffset[2], ttl, proto;
+	u16_t				ipchksum;
+	u16_t				srcipaddr[2], destipaddr[2];
+} PACK_STRUCT_END;
+
+#ifdef __ICCARM__
+	#pragma pack()
+#endif
+#define ARP_REQUEST		1
+#define ARP_REPLY		2
+
+#define ARP_HWTYPE_ETH	1
+
+struct arp_entry
+{
+	u16_t				ipaddr[2];
+	struct uip_eth_addr ethaddr;
+	u8_t				time;
+};
+
+static const struct uip_eth_addr	broadcast_ethaddr = { { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff } };
+static const u16_t					broadcast_ipaddr[2] = { 0xffff, 0xffff };
+
+static struct arp_entry				arp_table[UIP_ARPTAB_SIZE];
+static u16_t						ipaddr[2];
+static u8_t							i, c;
+
+static u8_t							arptime;
+static u8_t							tmpage;
+
+#define BUF		( ( struct arp_hdr * ) &uip_buf[0] )
+#define IPBUF	( ( struct ethip_hdr * ) &uip_buf[0] )
+
+/*-----------------------------------------------------------------------------------*/
+
+/**
+ * Initialize the ARP module.
+ *
+ */
+
+/*-----------------------------------------------------------------------------------*/
+void uip_arp_init( void )
+{
+	for( i = 0; i < UIP_ARPTAB_SIZE; ++i )
+	{
+		memset( arp_table[i].ipaddr, 0, 4 );
+	}
+}
+
+/*-----------------------------------------------------------------------------------*/
+
+/**
+ * Periodic ARP processing function.
+ *
+ * This function performs periodic timer processing in the ARP module
+ * and should be called at regular intervals. The recommended interval
+ * is 10 seconds between the calls.
+ *
+ */
+
+/*-----------------------------------------------------------------------------------*/
+void uip_arp_timer( void )
+{
+	struct arp_entry	*tabptr;
+
+	++arptime;
+	for( i = 0; i < UIP_ARPTAB_SIZE; ++i )
+	{
+		tabptr = &arp_table[i];
+		if( (tabptr->ipaddr[0] | tabptr->ipaddr[1]) != 0 && arptime - tabptr->time >= UIP_ARP_MAXAGE )
+		{
+			memset( tabptr->ipaddr, 0, 4 );
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------------------*/
+static void uip_arp_update( u16_t *ipaddr, struct uip_eth_addr *ethaddr )
+{
+	register struct arp_entry	*tabptr;
+
+	/* Walk through the ARP mapping table and try to find an entry to
+     update. If none is found, the IP -> MAC address mapping is
+     inserted in the ARP table. */
+	for( i = 0; i < UIP_ARPTAB_SIZE; ++i )
+	{
+		tabptr = &arp_table[i];
+
+		/* Only check those entries that are actually in use. */
+		if( tabptr->ipaddr[0] != 0 && tabptr->ipaddr[1] != 0 )
+		{
+			/* Check if the source IP address of the incoming packet matches
+         the IP address in this ARP table entry. */
+			if( ipaddr[0] == tabptr->ipaddr[0] && ipaddr[1] == tabptr->ipaddr[1] )
+			{
+				/* An old entry found, update this and return. */
+				memcpy( tabptr->ethaddr.addr, ethaddr->addr, 6 );
+				tabptr->time = arptime;
+
+				return;
+			}
+		}
+	}
+
+	/* If we get here, no existing ARP table entry was found, so we
+     create one. */
+
+	/* First, we try to find an unused entry in the ARP table. */
+	for( i = 0; i < UIP_ARPTAB_SIZE; ++i )
+	{
+		tabptr = &arp_table[i];
+		if( tabptr->ipaddr[0] == 0 && tabptr->ipaddr[1] == 0 )
+		{
+			break;
+		}
+	}
+
+	/* If no unused entry is found, we try to find the oldest entry and
+     throw it away. */
+	if( i == UIP_ARPTAB_SIZE )
+	{
+		tmpage = 0;
+		c = 0;
+		for( i = 0; i < UIP_ARPTAB_SIZE; ++i )
+		{
+			tabptr = &arp_table[i];
+			if( arptime - tabptr->time > tmpage )
+			{
+				tmpage = arptime - tabptr->time;
+				c = i;
+			}
+		}
+
+		i = c;
+		tabptr = &arp_table[i];
+	}
+
+	/* Now, i is the ARP table entry which we will fill with the new
+     information. */
+	memcpy( tabptr->ipaddr, ipaddr, 4 );
+	memcpy( tabptr->ethaddr.addr, ethaddr->addr, 6 );
+	tabptr->time = arptime;
+}
+
+/*-----------------------------------------------------------------------------------*/
+
+/**
+ * ARP processing for incoming IP packets
+ *
+ * This function should be called by the device driver when an IP
+ * packet has been received. The function will check if the address is
+ * in the ARP cache, and if so the ARP cache entry will be
+ * refreshed. If no ARP cache entry was found, a new one is created.
+ *
+ * This function expects an IP packet with a prepended Ethernet header
+ * in the uip_buf[] buffer, and the length of the packet in the global
+ * variable uip_len.
+ */
+
+/*-----------------------------------------------------------------------------------*/
+#if 1
+void uip_arp_ipin( void )
+{
+	uip_len -= sizeof( struct uip_eth_hdr );
+
+	/* Only insert/update an entry if the source IP address of the
+     incoming IP packet comes from a host on the local network. */
+	if( (IPBUF->srcipaddr[0] & uip_netmask[0]) != (uip_hostaddr[0] & uip_netmask[0]) )
+	{
+		return;
+	}
+
+	if( (IPBUF->srcipaddr[1] & uip_netmask[1]) != (uip_hostaddr[1] & uip_netmask[1]) )
+	{
+		return;
+	}
+
+	uip_arp_update( IPBUF->srcipaddr, &(IPBUF->ethhdr.src) );
+
+	return;
+}
+
+#endif /* 0 */
+
+/*-----------------------------------------------------------------------------------*/
+
+/**
+ * ARP processing for incoming ARP packets.
+ *
+ * This function should be called by the device driver when an ARP
+ * packet has been received. The function will act differently
+ * depending on the ARP packet type: if it is a reply for a request
+ * that we previously sent out, the ARP cache will be filled in with
+ * the values from the ARP reply. If the incoming ARP packet is an ARP
+ * request for our IP address, an ARP reply packet is created and put
+ * into the uip_buf[] buffer.
+ *
+ * When the function returns, the value of the global variable uip_len
+ * indicates whether the device driver should send out a packet or
+ * not. If uip_len is zero, no packet should be sent. If uip_len is
+ * non-zero, it contains the length of the outbound packet that is
+ * present in the uip_buf[] buffer.
+ *
+ * This function expects an ARP packet with a prepended Ethernet
+ * header in the uip_buf[] buffer, and the length of the packet in the
+ * global variable uip_len.
+ */
+
+/*-----------------------------------------------------------------------------------*/
+void uip_arp_arpin( void )
+{
+	if( uip_len < sizeof(struct arp_hdr) )
+	{
+		uip_len = 0;
+		return;
+	}
+
+	uip_len = 0;
+
+	switch( BUF->opcode )
+	{
+		case HTONS( ARP_REQUEST ):
+			/* ARP request. If it asked for our address, we send out a
+       reply. */
+			if( uip_ipaddr_cmp(BUF->dipaddr, uip_hostaddr) )
+			{
+				/* First, we register the one who made the request in our ARP
+	 table, since it is likely that we will do more communication
+	 with this host in the future. */
+				uip_arp_update( BUF->sipaddr, &BUF->shwaddr );
+
+				/* The reply opcode is 2. */
+				BUF->opcode = HTONS( 2 );
+
+				memcpy( BUF->dhwaddr.addr, BUF->shwaddr.addr, 6 );
+				memcpy( BUF->shwaddr.addr, uip_ethaddr.addr, 6 );
+				memcpy( BUF->ethhdr.src.addr, uip_ethaddr.addr, 6 );
+				memcpy( BUF->ethhdr.dest.addr, BUF->dhwaddr.addr, 6 );
+
+				BUF->dipaddr[0] = BUF->sipaddr[0];
+				BUF->dipaddr[1] = BUF->sipaddr[1];
+				BUF->sipaddr[0] = uip_hostaddr[0];
+				BUF->sipaddr[1] = uip_hostaddr[1];
+
+				BUF->ethhdr.type = HTONS( UIP_ETHTYPE_ARP );
+				uip_len = sizeof( struct arp_hdr );
+			}
+
+			break;
+
+		case HTONS( ARP_REPLY ):
+			/* ARP reply. We insert or update the ARP table if it was meant
+       for us. */
+			if( uip_ipaddr_cmp(BUF->dipaddr, uip_hostaddr) )
+			{
+				uip_arp_update( BUF->sipaddr, &BUF->shwaddr );
+			}
+
+			break;
+	}
+
+	return;
+}
+
+/*-----------------------------------------------------------------------------------*/
+
+/**
+ * Prepend Ethernet header to an outbound IP packet and see if we need
+ * to send out an ARP request.
+ *
+ * This function should be called before sending out an IP packet. The
+ * function checks the destination IP address of the IP packet to see
+ * what Ethernet MAC address that should be used as a destination MAC
+ * address on the Ethernet.
+ *
+ * If the destination IP address is in the local network (determined
+ * by logical ANDing of netmask and our IP address), the function
+ * checks the ARP cache to see if an entry for the destination IP
+ * address is found. If so, an Ethernet header is prepended and the
+ * function returns. If no ARP cache entry is found for the
+ * destination IP address, the packet in the uip_buf[] is replaced by
+ * an ARP request packet for the IP address. The IP packet is dropped
+ * and it is assumed that they higher level protocols (e.g., TCP)
+ * eventually will retransmit the dropped packet.
+ *
+ * If the destination IP address is not on the local network, the IP
+ * address of the default router is used instead.
+ *
+ * When the function returns, a packet is present in the uip_buf[]
+ * buffer, and the length of the packet is in the global variable
+ * uip_len.
+ */
+
+/*-----------------------------------------------------------------------------------*/
+void uip_arp_out( void )
+{
+	struct arp_entry	*tabptr;
+
+	/* Find the destination IP address in the ARP table and construct
+     the Ethernet header. If the destination IP addres isn't on the
+     local network, we use the default router's IP address instead.
+
+     If not ARP table entry is found, we overwrite the original IP
+     packet with an ARP request for the IP address. */
+
+	/* First check if destination is a local broadcast. */
+	if( uip_ipaddr_cmp(IPBUF->destipaddr, broadcast_ipaddr) )
+	{
+		memcpy( IPBUF->ethhdr.dest.addr, broadcast_ethaddr.addr, 6 );
+	}
+	else
+	{
+		/* Check if the destination address is on the local network. */
+		if( !uip_ipaddr_maskcmp(IPBUF->destipaddr, uip_hostaddr, uip_netmask) )
+		{
+			/* Destination address was not on the local network, so we need to
+	 use the default router's IP address instead of the destination
+	 address when determining the MAC address. */
+			uip_ipaddr_copy( ipaddr, uip_draddr );
+		}
+		else
+		{
+			/* Else, we use the destination IP address. */
+			uip_ipaddr_copy( ipaddr, IPBUF->destipaddr );
+		}
+
+		for( i = 0; i < UIP_ARPTAB_SIZE; ++i )
+		{
+			tabptr = &arp_table[i];
+			if( uip_ipaddr_cmp(ipaddr, tabptr->ipaddr) )
+			{
+				break;
+			}
+		}
+
+		if( i == UIP_ARPTAB_SIZE )
+		{
+			/* The destination address was not in our ARP table, so we
+	 overwrite the IP packet with an ARP request. */
+			memset( BUF->ethhdr.dest.addr, 0xff, 6 );
+			memset( BUF->dhwaddr.addr, 0x00, 6 );
+			memcpy( BUF->ethhdr.src.addr, uip_ethaddr.addr, 6 );
+			memcpy( BUF->shwaddr.addr, uip_ethaddr.addr, 6 );
+
+			uip_ipaddr_copy( BUF->dipaddr, ipaddr );
+			uip_ipaddr_copy( BUF->sipaddr, uip_hostaddr );
+			BUF->opcode = HTONS( ARP_REQUEST ); /* ARP request. */
+			BUF->hwtype = HTONS( ARP_HWTYPE_ETH );
+			BUF->protocol = HTONS( UIP_ETHTYPE_IP );
+			BUF->hwlen = 6;
+			BUF->protolen = 4;
+			BUF->ethhdr.type = HTONS( UIP_ETHTYPE_ARP );
+
+			uip_appdata = &uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN];
+
+			uip_len = sizeof( struct arp_hdr );
+			return;
+		}
+
+		/* Build an ethernet header. */
+		memcpy( IPBUF->ethhdr.dest.addr, tabptr->ethaddr.addr, 6 );
+	}
+
+	memcpy( IPBUF->ethhdr.src.addr, uip_ethaddr.addr, 6 );
+
+	IPBUF->ethhdr.type = HTONS( UIP_ETHTYPE_IP );
+
+	uip_len += sizeof( struct uip_eth_hdr );
+}
+
+/*-----------------------------------------------------------------------------------*/
+
+/** @} */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_arp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_arp.h
new file mode 100644
index 0000000..b6b2b66
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_arp.h
@@ -0,0 +1,152 @@
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \addtogroup uiparp
+ * @{
+ */
+
+/**
+ * \file
+ * Macros and definitions for the ARP module.
+ * \author Adam Dunkels 
+ */
+
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip_arp.h,v 1.5 2006/06/11 21:46:39 adam Exp $
+ *
+ */
+
+#ifndef __UIP_ARP_H__
+#define __UIP_ARP_H__
+
+#include "uip.h"
+
+
+extern struct uip_eth_addr uip_ethaddr;
+
+/**
+ * The Ethernet header.
+ */
+#ifdef __ICCARM__
+	#pragma pack(1)
+#endif
+
+struct uip_eth_hdr {
+  struct uip_eth_addr dest;
+  struct uip_eth_addr src;
+  u16_t type;
+}PACK_STRUCT_END;
+
+#ifdef __ICCARM__
+	#pragma pack()
+#endif
+
+#define UIP_ETHTYPE_ARP 0x0806
+#define UIP_ETHTYPE_IP  0x0800
+#define UIP_ETHTYPE_IP6 0x86dd
+
+
+/* The uip_arp_init() function must be called before any of the other
+   ARP functions. */
+void uip_arp_init(void);
+
+/* The uip_arp_ipin() function should be called whenever an IP packet
+   arrives from the Ethernet. This function refreshes the ARP table or
+   inserts a new mapping if none exists. The function assumes that an
+   IP packet with an Ethernet header is present in the uip_buf buffer
+   and that the length of the packet is in the uip_len variable. */
+void uip_arp_ipin(void);
+//#define uip_arp_ipin()
+
+/* The uip_arp_arpin() should be called when an ARP packet is received
+   by the Ethernet driver. This function also assumes that the
+   Ethernet frame is present in the uip_buf buffer. When the
+   uip_arp_arpin() function returns, the contents of the uip_buf
+   buffer should be sent out on the Ethernet if the uip_len variable
+   is > 0. */
+void uip_arp_arpin(void);
+
+/* The uip_arp_out() function should be called when an IP packet
+   should be sent out on the Ethernet. This function creates an
+   Ethernet header before the IP header in the uip_buf buffer. The
+   Ethernet header will have the correct Ethernet MAC destination
+   address filled in if an ARP table entry for the destination IP
+   address (or the IP address of the default router) is present. If no
+   such table entry is found, the IP packet is overwritten with an ARP
+   request and we rely on TCP to retransmit the packet that was
+   overwritten. In any case, the uip_len variable holds the length of
+   the Ethernet frame that should be transmitted. */
+void uip_arp_out(void);
+
+/* The uip_arp_timer() function should be called every ten seconds. It
+   is responsible for flushing old entries in the ARP table. */
+void uip_arp_timer(void);
+
+/** @} */
+
+/**
+ * \addtogroup uipconffunc
+ * @{
+ */
+
+
+/**
+ * Specifiy the Ethernet MAC address.
+ *
+ * The ARP code needs to know the MAC address of the Ethernet card in
+ * order to be able to respond to ARP queries and to generate working
+ * Ethernet headers.
+ *
+ * \note This macro only specifies the Ethernet MAC address to the ARP
+ * code. It cannot be used to change the MAC address of the Ethernet
+ * card.
+ *
+ * \param eaddr A pointer to a struct uip_eth_addr containing the
+ * Ethernet MAC address of the Ethernet card.
+ *
+ * \hideinitializer
+ */
+#define uip_setethaddr(eaddr) do {uip_ethaddr.addr[0] = eaddr.addr[0]; \
+                              uip_ethaddr.addr[1] = eaddr.addr[1];\
+                              uip_ethaddr.addr[2] = eaddr.addr[2];\
+                              uip_ethaddr.addr[3] = eaddr.addr[3];\
+                              uip_ethaddr.addr[4] = eaddr.addr[4];\
+                              uip_ethaddr.addr[5] = eaddr.addr[5];} while(0)
+
+/** @} */
+/** @} */
+
+#endif /* __UIP_ARP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_timer.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_timer.h
new file mode 100644
index 0000000..e28e3ca
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uip_timer.h
@@ -0,0 +1,86 @@
+/**
+ * \defgroup timer Timer library
+ *
+ * The timer library provides functions for setting, resetting and
+ * restarting timers, and for checking if a timer has expired. An
+ * application must "manually" check if its timers have expired; this
+ * is not done automatically.
+ *
+ * A timer is declared as a \c struct \c timer and all access to the
+ * timer is made by a pointer to the declared timer.
+ *
+ * \note The timer library uses the \ref clock "Clock library" to
+ * measure time. Intervals should be specified in the format used by
+ * the clock library.
+ *
+ * @{
+ */
+
+
+/**
+ * \file
+ * Timer library header file.
+ * \author
+ * Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2004, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: timer.h,v 1.3 2006/06/11 21:46:39 adam Exp $
+ */
+#ifndef __TIMER_H__
+#define __TIMER_H__
+
+#include "clock.h"
+
+/**
+ * A timer.
+ *
+ * This structure is used for declaring a timer. The timer must be set
+ * with timer_set() before it can be used.
+ *
+ * \hideinitializer
+ */
+struct timer {
+  clock_time_t start;
+  clock_time_t interval;
+};
+
+void timer_set(struct timer *t, clock_time_t interval);
+void timer_reset(struct timer *t);
+void timer_restart(struct timer *t);
+int timer_expired(struct timer *t);
+
+#endif /* __TIMER_H__ */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uiplib.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uiplib.c
new file mode 100644
index 0000000..afedc0d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uiplib.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2004, Adam Dunkels and the Swedish Institute of
+ * Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * $Id: uiplib.c,v 1.2 2006/06/12 08:00:31 adam Exp $
+ *
+ */
+#include "uip.h"
+#include "uiplib.h"
+
+/*-----------------------------------------------------------------------------------*/
+unsigned char uiplib_ipaddrconv( char *addrstr, unsigned char *ipaddr )
+{
+	unsigned char	tmp;
+	char			c;
+	unsigned char	i, j;
+
+	tmp = 0;
+
+	for( i = 0; i < 4; ++i )
+	{
+		j = 0;
+		do
+		{
+			c = *addrstr;
+			++j;
+			if( j > 4 )
+			{
+				return 0;
+			}
+
+			if( c == '.' || c == 0 )
+			{
+				*ipaddr = tmp;
+				++ipaddr;
+				tmp = 0;
+			}
+			else if( c >= '0' && c <= '9' )
+			{
+				tmp = ( tmp * 10 ) + ( c - '0' );
+			}
+			else
+			{
+				return 0;
+			}
+
+			++addrstr;
+		} while( c != '.' && c != 0 );
+	}
+
+	return 1;
+}
+
+/*-----------------------------------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uiplib.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uiplib.h
new file mode 100644
index 0000000..6eb0c66
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uiplib.h
@@ -0,0 +1,71 @@
+/**
+ * \file
+ * Various uIP library functions.
+ * \author
+ * Adam Dunkels 
+ *
+ */
+
+/*
+ * Copyright (c) 2002, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * $Id: uiplib.h,v 1.1 2006/06/07 09:15:19 adam Exp $
+ *
+ */
+#ifndef __UIPLIB_H__
+#define __UIPLIB_H__
+
+/**
+ * \addtogroup uipconvfunc
+ * @{
+ */
+
+/**
+ * Convert a textual representation of an IP address to a numerical representation.
+ *
+ * This function takes a textual representation of an IP address in
+ * the form a.b.c.d and converts it into a 4-byte array that can be
+ * used by other uIP functions.
+ *
+ * \param addrstr A pointer to a string containing the IP address in
+ * textual form.
+ *
+ * \param addr A pointer to a 4-byte array that will be filled in with
+ * the numerical representation of the address.
+ *
+ * \retval 0 If the IP address could not be parsed.
+ * \retval Non-zero If the IP address was parsed.
+ */
+unsigned char uiplib_ipaddrconv(char *addrstr, unsigned char *addr);
+
+/** @} */
+
+#endif /* __UIPLIB_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uipopt.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uipopt.h
new file mode 100644
index 0000000..cc01001
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeRTOS-uIP/uipopt.h
@@ -0,0 +1,535 @@
+/**
+ * \defgroup uipopt Configuration options for uIP
+ * @{
+ *
+ * uIP is configured using the per-project configuration file
+ * uipopt.h. This file contains all compile-time options for uIP and
+ * should be tweaked to match each specific project. The uIP
+ * distribution contains a documented example "uipopt.h" that can be
+ * copied and modified for each project.
+ *
+ * \note Most of the configuration options in the uipopt.h should not
+ * be changed, but rather the per-project uip-conf.h file.
+ */
+
+/**
+ * \file
+ * Configuration options for uIP.
+ * \author Adam Dunkels 
+ *
+ * This file is used for tweaking various configuration options for
+ * uIP. You should make a copy of this file into one of your project's
+ * directories instead of editing this example "uipopt.h" file that
+ * comes with the uIP distribution.
+ */
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uipopt.h,v 1.4 2006/06/12 08:00:31 adam Exp $
+ *
+ */
+
+#ifndef __UIPOPT_H__
+#define __UIPOPT_H__
+
+#ifndef UIP_LITTLE_ENDIAN
+#define UIP_LITTLE_ENDIAN  3412
+#endif /* UIP_LITTLE_ENDIAN */
+#ifndef UIP_BIG_ENDIAN
+#define UIP_BIG_ENDIAN     1234
+#endif /* UIP_BIG_ENDIAN */
+
+#include "uip-conf.h"
+
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \name Static configuration options
+ * @{
+ *
+ * These configuration options can be used for setting the IP address
+ * settings statically, but only if UIP_FIXEDADDR is set to 1. The
+ * configuration options for a specific node includes IP address,
+ * netmask and default router as well as the Ethernet address. The
+ * netmask, default router and Ethernet address are appliciable only
+ * if uIP should be run over Ethernet.
+ *
+ * All of these should be changed to suit your project.
+*/
+
+/**
+ * Determines if uIP should use a fixed IP address or not.
+ *
+ * If uIP should use a fixed IP address, the settings are set in the
+ * uipopt.h file. If not, the macros uip_sethostaddr(),
+ * uip_setdraddr() and uip_setnetmask() should be used instead.
+ *
+ * \hideinitializer
+ */
+#define UIP_FIXEDADDR    0
+
+/**
+ * Ping IP address asignment.
+ *
+ * uIP uses a "ping" packets for setting its own IP address if this
+ * option is set. If so, uIP will start with an empty IP address and
+ * the destination IP address of the first incoming "ping" (ICMP echo)
+ * packet will be used for setting the hosts IP address.
+ *
+ * \note This works only if UIP_FIXEDADDR is 0.
+ *
+ * \hideinitializer
+ */
+#ifdef UIP_CONF_PINGADDRCONF
+#define UIP_PINGADDRCONF UIP_CONF_PINGADDRCONF
+#else /* UIP_CONF_PINGADDRCONF */
+#define UIP_PINGADDRCONF 0
+#endif /* UIP_CONF_PINGADDRCONF */
+
+
+/**
+ * Specifies if the uIP ARP module should be compiled with a fixed
+ * Ethernet MAC address or not.
+ *
+ * If this configuration option is 0, the macro uip_setethaddr() can
+ * be used to specify the Ethernet address at run-time.
+ *
+ * \hideinitializer
+ */
+#define UIP_FIXEDETHADDR 0
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+/**
+ * \name IP configuration options
+ * @{
+ *
+ */
+/**
+ * The IP TTL (time to live) of IP packets sent by uIP.
+ *
+ * This should normally not be changed.
+ */
+#define UIP_TTL         64
+
+/**
+ * Turn on support for IP packet reassembly.
+ *
+ * uIP supports reassembly of fragmented IP packets. This features
+ * requires an additonal amount of RAM to hold the reassembly buffer
+ * and the reassembly code size is approximately 700 bytes.  The
+ * reassembly buffer is of the same size as the uip_buf buffer
+ * (configured by UIP_BUFSIZE).
+ *
+ * \note IP packet reassembly is not heavily tested.
+ *
+ * \hideinitializer
+ */
+#define UIP_REASSEMBLY 0
+
+/**
+ * The maximum time an IP fragment should wait in the reassembly
+ * buffer before it is dropped.
+ *
+ */
+#define UIP_REASS_MAXAGE 40
+
+/** @} */
+
+/*------------------------------------------------------------------------------*/
+/**
+ * \name UDP configuration options
+ * @{
+ */
+
+/**
+ * Toggles wether UDP support should be compiled in or not.
+ *
+ * \hideinitializer
+ */
+#ifdef UIP_CONF_UDP
+#define UIP_UDP UIP_CONF_UDP
+#else /* UIP_CONF_UDP */
+#define UIP_UDP           0
+#endif /* UIP_CONF_UDP */
+
+/**
+ * Toggles if UDP checksums should be used or not.
+ *
+ * \note Support for UDP checksums is currently not included in uIP,
+ * so this option has no function.
+ *
+ * \hideinitializer
+ */
+#ifdef UIP_CONF_UDP_CHECKSUMS
+#define UIP_UDP_CHECKSUMS UIP_CONF_UDP_CHECKSUMS
+#else
+#define UIP_UDP_CHECKSUMS 0
+#endif
+
+/**
+ * The maximum amount of concurrent UDP connections.
+ *
+ * \hideinitializer
+ */
+#ifdef UIP_CONF_UDP_CONNS
+#define UIP_UDP_CONNS UIP_CONF_UDP_CONNS
+#else /* UIP_CONF_UDP_CONNS */
+#define UIP_UDP_CONNS    10
+#endif /* UIP_CONF_UDP_CONNS */
+
+/**
+ * The name of the function that should be called when UDP datagrams arrive.
+ *
+ * \hideinitializer
+ */
+
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+/**
+ * \name TCP configuration options
+ * @{
+ */
+
+/**
+ * Determines if support for opening connections from uIP should be
+ * compiled in.
+ *
+ * If the applications that are running on top of uIP for this project
+ * do not need to open outgoing TCP connections, this configration
+ * option can be turned off to reduce the code size of uIP.
+ *
+ * \hideinitializer
+ */
+#define UIP_ACTIVE_OPEN 1
+
+/**
+ * The maximum number of simultaneously open TCP connections.
+ *
+ * Since the TCP connections are statically allocated, turning this
+ * configuration knob down results in less RAM used. Each TCP
+ * connection requires approximatly 30 bytes of memory.
+ *
+ * \hideinitializer
+ */
+#ifndef UIP_CONF_MAX_CONNECTIONS
+#define UIP_CONNS       10
+#else /* UIP_CONF_MAX_CONNECTIONS */
+#define UIP_CONNS UIP_CONF_MAX_CONNECTIONS
+#endif /* UIP_CONF_MAX_CONNECTIONS */
+
+
+/**
+ * The maximum number of simultaneously listening TCP ports.
+ *
+ * Each listening TCP port requires 2 bytes of memory.
+ *
+ * \hideinitializer
+ */
+#ifndef UIP_CONF_MAX_LISTENPORTS
+#define UIP_LISTENPORTS 20
+#else /* UIP_CONF_MAX_LISTENPORTS */
+#define UIP_LISTENPORTS UIP_CONF_MAX_LISTENPORTS
+#endif /* UIP_CONF_MAX_LISTENPORTS */
+
+/**
+ * Determines if support for TCP urgent data notification should be
+ * compiled in.
+ *
+ * Urgent data (out-of-band data) is a rarely used TCP feature that
+ * very seldom would be required.
+ *
+ * \hideinitializer
+ */
+#define UIP_URGDATA      0
+
+/**
+ * The initial retransmission timeout counted in timer pulses.
+ *
+ * This should not be changed.
+ */
+#define UIP_RTO         3
+
+/**
+ * The maximum number of times a segment should be retransmitted
+ * before the connection should be aborted.
+ *
+ * This should not be changed.
+ */
+#define UIP_MAXRTX      8
+
+/**
+ * The maximum number of times a SYN segment should be retransmitted
+ * before a connection request should be deemed to have been
+ * unsuccessful.
+ *
+ * This should not need to be changed.
+ */
+#define UIP_MAXSYNRTX      5
+
+/**
+ * The TCP maximum segment size.
+ *
+ * This is should not be to set to more than
+ * UIP_BUFSIZE - UIP_LLH_LEN - UIP_TCPIP_HLEN.
+ */
+#define UIP_TCP_MSS     (UIP_BUFSIZE - UIP_LLH_LEN - UIP_TCPIP_HLEN)
+
+/**
+ * The size of the advertised receiver's window.
+ *
+ * Should be set low (i.e., to the size of the uip_buf buffer) is the
+ * application is slow to process incoming data, or high (32768 bytes)
+ * if the application processes data quickly.
+ *
+ * \hideinitializer
+ */
+#ifndef UIP_CONF_RECEIVE_WINDOW
+#define UIP_RECEIVE_WINDOW UIP_TCP_MSS
+#else
+#define UIP_RECEIVE_WINDOW UIP_CONF_RECEIVE_WINDOW
+#endif
+
+/**
+ * How long a connection should stay in the TIME_WAIT state.
+ *
+ * This configiration option has no real implication, and it should be
+ * left untouched.
+ */
+#define UIP_TIME_WAIT_TIMEOUT 120
+
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+/**
+ * \name ARP configuration options
+ * @{
+ */
+
+/**
+ * The size of the ARP table.
+ *
+ * This option should be set to a larger value if this uIP node will
+ * have many connections from the local network.
+ *
+ * \hideinitializer
+ */
+#ifdef UIP_CONF_ARPTAB_SIZE
+#define UIP_ARPTAB_SIZE UIP_CONF_ARPTAB_SIZE
+#else
+#define UIP_ARPTAB_SIZE 8
+#endif
+
+/**
+ * The maxium age of ARP table entries measured in 10ths of seconds.
+ *
+ * An UIP_ARP_MAXAGE of 120 corresponds to 20 minutes (BSD
+ * default).
+ */
+#define UIP_ARP_MAXAGE 120
+
+/** @} */
+
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \name General configuration options
+ * @{
+ */
+
+/**
+ * The size of the uIP packet buffer.
+ *
+ * The uIP packet buffer should not be smaller than 60 bytes, and does
+ * not need to be larger than 1500 bytes. Lower size results in lower
+ * TCP throughput, larger size results in higher TCP throughput.
+ *
+ * \hideinitializer
+ */
+#ifndef UIP_CONF_BUFFER_SIZE
+#define UIP_BUFSIZE     1500
+#else /* UIP_CONF_BUFFER_SIZE */
+#define UIP_BUFSIZE UIP_CONF_BUFFER_SIZE
+#endif /* UIP_CONF_BUFFER_SIZE */
+
+
+/**
+ * Determines if statistics support should be compiled in.
+ *
+ * The statistics is useful for debugging and to show the user.
+ *
+ * \hideinitializer
+ */
+#ifndef UIP_CONF_STATISTICS
+#define UIP_STATISTICS  0
+#else /* UIP_CONF_STATISTICS */
+#define UIP_STATISTICS UIP_CONF_STATISTICS
+#endif /* UIP_CONF_STATISTICS */
+
+/**
+ * Determines if logging of certain events should be compiled in.
+ *
+ * This is useful mostly for debugging. The function uip_log()
+ * must be implemented to suit the architecture of the project, if
+ * logging is turned on.
+ *
+ * \hideinitializer
+ */
+#ifndef UIP_CONF_LOGGING
+#define UIP_LOGGING     0
+#else /* UIP_CONF_LOGGING */
+#define UIP_LOGGING     UIP_CONF_LOGGING
+#endif /* UIP_CONF_LOGGING */
+
+/**
+ * Broadcast support.
+ *
+ * This flag configures IP broadcast support. This is useful only
+ * together with UDP.
+ *
+ * \hideinitializer
+ *
+ */
+#ifndef UIP_CONF_BROADCAST
+#define UIP_BROADCAST 0
+#else /* UIP_CONF_BROADCAST */
+#define UIP_BROADCAST UIP_CONF_BROADCAST
+#endif /* UIP_CONF_BROADCAST */
+
+/**
+ * Print out a uIP log message.
+ *
+ * This function must be implemented by the module that uses uIP, and
+ * is called by uIP whenever a log message is generated.
+ */
+void uip_log(char *msg);
+
+/**
+ * The link level header length.
+ *
+ * This is the offset into the uip_buf where the IP header can be
+ * found. For Ethernet, this should be set to 14. For SLIP, this
+ * should be set to 0.
+ *
+ * \hideinitializer
+ */
+#ifdef UIP_CONF_LLH_LEN
+#define UIP_LLH_LEN UIP_CONF_LLH_LEN
+#else /* UIP_CONF_LLH_LEN */
+#define UIP_LLH_LEN     14
+#endif /* UIP_CONF_LLH_LEN */
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+/**
+ * \name CPU architecture configuration
+ * @{
+ *
+ * The CPU architecture configuration is where the endianess of the
+ * CPU on which uIP is to be run is specified. Most CPUs today are
+ * little endian, and the most notable exception are the Motorolas
+ * which are big endian. The BYTE_ORDER macro should be changed to
+ * reflect the CPU architecture on which uIP is to be run.
+ */
+
+/**
+ * The byte order of the CPU architecture on which uIP is to be run.
+ *
+ * This option can be either BIG_ENDIAN (Motorola byte order) or
+ * LITTLE_ENDIAN (Intel byte order).
+ *
+ * \hideinitializer
+ */
+#define UIP_BYTE_ORDER     UIP_CONF_BYTE_ORDER
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \name Appication specific configurations
+ * @{
+ *
+ * An uIP application is implemented using a single application
+ * function that is called by uIP whenever a TCP/IP event occurs. The
+ * name of this function must be registered with uIP at compile time
+ * using the UIP_APPCALL definition.
+ *
+ * uIP applications can store the application state within the
+ * uip_conn structure by specifying the type of the application
+ * structure by typedef:ing the type uip_tcp_appstate_t and uip_udp_appstate_t.
+ *
+ * The file containing the definitions must be included in the
+ * uipopt.h file.
+ *
+ * The following example illustrates how this can look.
+ \code
+
+void httpd_appcall(void);
+#define UIP_APPCALL     httpd_appcall
+
+struct httpd_state {
+  u8_t state;
+  u16_t count;
+  char *dataptr;
+  char *script;
+};
+typedef struct httpd_state uip_tcp_appstate_t
+ \endcode
+ */
+
+/**
+ * \var #define UIP_APPCALL
+ *
+ * The name of the application function that uIP should call in
+ * response to TCP/IP events.
+ *
+ */
+
+/**
+ * \var typedef uip_tcp_appstate_t
+ *
+ * The type of the application state that is to be stored in the
+ * uip_conn structure. This usually is typedef:ed to a struct holding
+ * application state information.
+ */
+
+/**
+ * \var typedef uip_udp_appstate_t
+ *
+ * The type of the application state that is to be stored in the
+ * uip_conn structure. This usually is typedef:ed to a struct holding
+ * application state information.
+ */
+/** @} */
+/** @} */
+
+#endif /* __UIPOPT_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/http-strings.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/http-strings.c
new file mode 100644
index 0000000..a3771dd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/http-strings.c
@@ -0,0 +1,486 @@
+const char	http_http[8] = /* "http://" */ { 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, };
+const char	http_200[5] = /* "200 " */ { 0x32, 0x30, 0x30, 0x20, };
+const char	http_301[5] = /* "301 " */ { 0x33, 0x30, 0x31, 0x20, };
+const char	http_302[5] = /* "302 " */ { 0x33, 0x30, 0x32, 0x20, };
+const char	http_get[5] = /* "GET " */ { 0x47, 0x45, 0x54, 0x20, };
+const char	http_10[9] = /* "HTTP/1.0" */ { 0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, };
+const char	http_11[9] = /* "HTTP/1.1" */ { 0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, };
+const char	http_content_type[15] =
+
+/* "content-type: " */
+{ 0x63,
+	0x6f,
+	0x6e,
+	0x74,
+	0x65,
+	0x6e,
+	0x74,
+	0x2d,
+	0x74,
+	0x79,
+	0x70,
+	0x65,
+	0x3a,
+	0x20,
+};
+const char	http_texthtml[10] = /* "text/html" */ { 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, };
+const char	http_location[11] = /* "location: " */ { 0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, };
+const char	http_host[7] = /* "host: " */ { 0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, };
+const char	http_crnl[3] = /* "\r\n" */ { 0xd, 0xa, };
+const char	http_index_html[12] = /* "/index.html" */ { 0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, };
+const char	http_404_html[10] = /* "/404.html" */ { 0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, };
+const char	http_referer[9] = /* "Referer:" */ { 0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, };
+const char	http_header_200[84] =
+
+/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */
+{ 0x48,
+	0x54,
+	0x54,
+	0x50,
+	0x2f,
+	0x31,
+	0x2e,
+	0x30,
+	0x20,
+	0x32,
+	0x30,
+	0x30,
+	0x20,
+	0x4f,
+	0x4b,
+	0xd,
+	0xa,
+	0x53,
+	0x65,
+	0x72,
+	0x76,
+	0x65,
+	0x72,
+	0x3a,
+	0x20,
+	0x75,
+	0x49,
+	0x50,
+	0x2f,
+	0x31,
+	0x2e,
+	0x30,
+	0x20,
+	0x68,
+	0x74,
+	0x74,
+	0x70,
+	0x3a,
+	0x2f,
+	0x2f,
+	0x77,
+	0x77,
+	0x77,
+	0x2e,
+	0x73,
+	0x69,
+	0x63,
+	0x73,
+	0x2e,
+	0x73,
+	0x65,
+	0x2f,
+	0x7e,
+	0x61,
+	0x64,
+	0x61,
+	0x6d,
+	0x2f,
+	0x75,
+	0x69,
+	0x70,
+	0x2f,
+	0xd,
+	0xa,
+	0x43,
+	0x6f,
+	0x6e,
+	0x6e,
+	0x65,
+	0x63,
+	0x74,
+	0x69,
+	0x6f,
+	0x6e,
+	0x3a,
+	0x20,
+	0x63,
+	0x6c,
+	0x6f,
+	0x73,
+	0x65,
+	0xd,
+	0xa,
+};
+const char	http_header_404[91] =
+
+/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */
+{ 0x48,
+	0x54,
+	0x54,
+	0x50,
+	0x2f,
+	0x31,
+	0x2e,
+	0x30,
+	0x20,
+	0x34,
+	0x30,
+	0x34,
+	0x20,
+	0x4e,
+	0x6f,
+	0x74,
+	0x20,
+	0x66,
+	0x6f,
+	0x75,
+	0x6e,
+	0x64,
+	0xd,
+	0xa,
+	0x53,
+	0x65,
+	0x72,
+	0x76,
+	0x65,
+	0x72,
+	0x3a,
+	0x20,
+	0x75,
+	0x49,
+	0x50,
+	0x2f,
+	0x31,
+	0x2e,
+	0x30,
+	0x20,
+	0x68,
+	0x74,
+	0x74,
+	0x70,
+	0x3a,
+	0x2f,
+	0x2f,
+	0x77,
+	0x77,
+	0x77,
+	0x2e,
+	0x73,
+	0x69,
+	0x63,
+	0x73,
+	0x2e,
+	0x73,
+	0x65,
+	0x2f,
+	0x7e,
+	0x61,
+	0x64,
+	0x61,
+	0x6d,
+	0x2f,
+	0x75,
+	0x69,
+	0x70,
+	0x2f,
+	0xd,
+	0xa,
+	0x43,
+	0x6f,
+	0x6e,
+	0x6e,
+	0x65,
+	0x63,
+	0x74,
+	0x69,
+	0x6f,
+	0x6e,
+	0x3a,
+	0x20,
+	0x63,
+	0x6c,
+	0x6f,
+	0x73,
+	0x65,
+	0xd,
+	0xa,
+};
+const char	http_content_type_plain[29] =
+
+/* "Content-type: text/plain\r\n\r\n" */
+{ 0x43,
+	0x6f,
+	0x6e,
+	0x74,
+	0x65,
+	0x6e,
+	0x74,
+	0x2d,
+	0x74,
+	0x79,
+	0x70,
+	0x65,
+	0x3a,
+	0x20,
+	0x74,
+	0x65,
+	0x78,
+	0x74,
+	0x2f,
+	0x70,
+	0x6c,
+	0x61,
+	0x69,
+	0x6e,
+	0xd,
+	0xa,
+	0xd,
+	0xa,
+};
+const char	http_content_type_html[28] =
+
+/* "Content-type: text/html\r\n\r\n" */
+{ 0x43,
+	0x6f,
+	0x6e,
+	0x74,
+	0x65,
+	0x6e,
+	0x74,
+	0x2d,
+	0x74,
+	0x79,
+	0x70,
+	0x65,
+	0x3a,
+	0x20,
+	0x74,
+	0x65,
+	0x78,
+	0x74,
+	0x2f,
+	0x68,
+	0x74,
+	0x6d,
+	0x6c,
+	0xd,
+	0xa,
+	0xd,
+	0xa,
+};
+const char	http_content_type_css[27] =
+
+/* "Content-type: text/css\r\n\r\n" */
+{ 0x43,
+	0x6f,
+	0x6e,
+	0x74,
+	0x65,
+	0x6e,
+	0x74,
+	0x2d,
+	0x74,
+	0x79,
+	0x70,
+	0x65,
+	0x3a,
+	0x20,
+	0x74,
+	0x65,
+	0x78,
+	0x74,
+	0x2f,
+	0x63,
+	0x73,
+	0x73,
+	0xd,
+	0xa,
+	0xd,
+	0xa,
+};
+const char	http_content_type_text[28] =
+
+/* "Content-type: text/text\r\n\r\n" */
+{ 0x43,
+	0x6f,
+	0x6e,
+	0x74,
+	0x65,
+	0x6e,
+	0x74,
+	0x2d,
+	0x74,
+	0x79,
+	0x70,
+	0x65,
+	0x3a,
+	0x20,
+	0x74,
+	0x65,
+	0x78,
+	0x74,
+	0x2f,
+	0x74,
+	0x65,
+	0x78,
+	0x74,
+	0xd,
+	0xa,
+	0xd,
+	0xa,
+};
+const char	http_content_type_png[28] =
+
+/* "Content-type: image/png\r\n\r\n" */
+{ 0x43,
+	0x6f,
+	0x6e,
+	0x74,
+	0x65,
+	0x6e,
+	0x74,
+	0x2d,
+	0x74,
+	0x79,
+	0x70,
+	0x65,
+	0x3a,
+	0x20,
+	0x69,
+	0x6d,
+	0x61,
+	0x67,
+	0x65,
+	0x2f,
+	0x70,
+	0x6e,
+	0x67,
+	0xd,
+	0xa,
+	0xd,
+	0xa,
+};
+const char	http_content_type_gif[28] =
+
+/* "Content-type: image/gif\r\n\r\n" */
+{ 0x43,
+	0x6f,
+	0x6e,
+	0x74,
+	0x65,
+	0x6e,
+	0x74,
+	0x2d,
+	0x74,
+	0x79,
+	0x70,
+	0x65,
+	0x3a,
+	0x20,
+	0x69,
+	0x6d,
+	0x61,
+	0x67,
+	0x65,
+	0x2f,
+	0x67,
+	0x69,
+	0x66,
+	0xd,
+	0xa,
+	0xd,
+	0xa,
+};
+const char	http_content_type_jpg[29] =
+
+/* "Content-type: image/jpeg\r\n\r\n" */
+{ 0x43,
+	0x6f,
+	0x6e,
+	0x74,
+	0x65,
+	0x6e,
+	0x74,
+	0x2d,
+	0x74,
+	0x79,
+	0x70,
+	0x65,
+	0x3a,
+	0x20,
+	0x69,
+	0x6d,
+	0x61,
+	0x67,
+	0x65,
+	0x2f,
+	0x6a,
+	0x70,
+	0x65,
+	0x67,
+	0xd,
+	0xa,
+	0xd,
+	0xa,
+};
+const char	http_content_type_binary[43] =
+
+/* "Content-type: application/octet-stream\r\n\r\n" */
+{ 0x43,
+	0x6f,
+	0x6e,
+	0x74,
+	0x65,
+	0x6e,
+	0x74,
+	0x2d,
+	0x74,
+	0x79,
+	0x70,
+	0x65,
+	0x3a,
+	0x20,
+	0x61,
+	0x70,
+	0x70,
+	0x6c,
+	0x69,
+	0x63,
+	0x61,
+	0x74,
+	0x69,
+	0x6f,
+	0x6e,
+	0x2f,
+	0x6f,
+	0x63,
+	0x74,
+	0x65,
+	0x74,
+	0x2d,
+	0x73,
+	0x74,
+	0x72,
+	0x65,
+	0x61,
+	0x6d,
+	0xd,
+	0xa,
+	0xd,
+	0xa,
+};
+const char	http_html[6] = /* ".html" */ { 0x2e, 0x68, 0x74, 0x6d, 0x6c, };
+const char	http_shtml[7] = /* ".shtml" */ { 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, };
+const char	http_htm[5] = /* ".htm" */ { 0x2e, 0x68, 0x74, 0x6d, };
+const char	http_css[5] = /* ".css" */ { 0x2e, 0x63, 0x73, 0x73, };
+const char	http_png[5] = /* ".png" */ { 0x2e, 0x70, 0x6e, 0x67, };
+const char	http_gif[5] = /* ".gif" */ { 0x2e, 0x67, 0x69, 0x66, };
+const char	http_jpg[5] = /* ".jpg" */ { 0x2e, 0x6a, 0x70, 0x67, };
+const char	http_text[5] = /* ".txt" */ { 0x2e, 0x74, 0x78, 0x74, };
+const char	http_txt[5] = /* ".txt" */ { 0x2e, 0x74, 0x78, 0x74, };
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/http-strings.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/http-strings.h
new file mode 100644
index 0000000..19ad23d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/http-strings.h
@@ -0,0 +1,34 @@
+extern const char	http_http[8];
+extern const char	http_200[5];
+extern const char	http_301[5];
+extern const char	http_302[5];
+extern const char	http_get[5];
+extern const char	http_10[9];
+extern const char	http_11[9];
+extern const char	http_content_type[15];
+extern const char	http_texthtml[10];
+extern const char	http_location[11];
+extern const char	http_host[7];
+extern const char	http_crnl[3];
+extern const char	http_index_html[12];
+extern const char	http_404_html[10];
+extern const char	http_referer[9];
+extern const char	http_header_200[84];
+extern const char	http_header_404[91];
+extern const char	http_content_type_plain[29];
+extern const char	http_content_type_html[28];
+extern const char	http_content_type_css[27];
+extern const char	http_content_type_text[28];
+extern const char	http_content_type_png[28];
+extern const char	http_content_type_gif[28];
+extern const char	http_content_type_jpg[29];
+extern const char	http_content_type_binary[43];
+extern const char	http_html[6];
+extern const char	http_shtml[7];
+extern const char	http_htm[5];
+extern const char	http_css[5];
+extern const char	http_png[5];
+extern const char	http_gif[5];
+extern const char	http_jpg[5];
+extern const char	http_text[5];
+extern const char	http_txt[5];
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-cgi.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-cgi.c
new file mode 100644
index 0000000..23851d3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-cgi.c
@@ -0,0 +1,169 @@
+/**
+ * \addtogroup httpd
+ * @{
+ */
+
+/**
+ * \file
+ *         Web server script interface
+ * \author
+ *         Adam Dunkels 
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2006, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $
+ *
+ */
+#include "net/uip.h"
+#include "net/psock.h"
+#include "httpd.h"
+#include "httpd-cgi.h"
+#include "httpd-fs.h"
+
+#include 
+#include 
+
+HTTPD_CGI_CALL( file, "file-stats", file_stats );
+HTTPD_CGI_CALL( tcp, "tcp-connections", tcp_stats );
+HTTPD_CGI_CALL( net, "net-stats", net_stats );
+
+static const struct httpd_cgi_call	*calls[] = { &file, &tcp, &net, NULL };
+
+/*---------------------------------------------------------------------------*/
+static PT_THREAD( nullfunction ( struct httpd_state *s, char *ptr ) )
+{
+	PSOCK_BEGIN( &s->sout );
+	PSOCK_END( &s->sout );
+}
+
+/*---------------------------------------------------------------------------*/
+httpd_cgifunction httpd_cgi( char *name )
+{
+	const struct httpd_cgi_call **f;
+
+	/* Find the matching name in the table, return the function. */
+	for( f = calls; *f != NULL; ++f )
+	{
+		if( strncmp((*f)->name, name, strlen((*f)->name)) == 0 )
+		{
+			return( *f )->function;
+		}
+	}
+
+	return nullfunction;
+}
+
+/*---------------------------------------------------------------------------*/
+static unsigned short generate_file_stats( void *arg )
+{
+	char	*f = ( char * ) arg;
+	return snprintf( ( char * ) uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f) );
+}
+
+/*---------------------------------------------------------------------------*/
+static PT_THREAD( file_stats ( struct httpd_state *s, char *ptr ) )
+{
+	PSOCK_BEGIN( &s->sout );
+
+	PSOCK_GENERATOR_SEND( &s->sout, generate_file_stats, strchr(ptr, ' ') + 1 );
+
+	PSOCK_END( &s->sout );
+}
+
+/*---------------------------------------------------------------------------*/
+static const char	closed[] = /*  "CLOSED",*/ { 0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0 };
+static const char	syn_rcvd[] = /*  "SYN-RCVD",*/ { 0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56, 0x44, 0 };
+static const char	syn_sent[] = /*  "SYN-SENT",*/ { 0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e, 0x54, 0 };
+static const char	established[] = /*  "ESTABLISHED",*/ { 0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48, 0x45, 0x44, 0 };
+static const char	fin_wait_1[] = /*  "FIN-WAIT-1",*/ { 0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, 0x54, 0x2d, 0x31, 0 };
+static const char	fin_wait_2[] = /*  "FIN-WAIT-2",*/ { 0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, 0x54, 0x2d, 0x32, 0 };
+static const char	closing[] = /*  "CLOSING",*/ { 0x43, 0x4c, 0x4f, 0x53, 0x49, 0x4e, 0x47, 0 };
+static const char	time_wait[] = /*  "TIME-WAIT,"*/ { 0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41, 0x49, 0x54, 0 };
+static const char	last_ack[] = /*  "LAST-ACK"*/ { 0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43, 0x4b, 0 };
+
+static const char	*states[] = { closed, syn_rcvd, syn_sent, established, fin_wait_1, fin_wait_2, closing, time_wait, last_ack };
+
+static unsigned short generate_tcp_stats( void *arg )
+{
+	struct uip_conn		*conn;
+	struct httpd_state	*s = ( struct httpd_state * ) arg;
+
+	conn = &uip_conns[s->count];
+	return snprintf( ( char * ) uip_appdata, UIP_APPDATA_SIZE,
+					 "%d%u.%u.%u.%u:%u%s%u%u%c %c\r\n", htons(conn->lport),
+					 htons(conn->ripaddr[0]) >> 8, htons(conn->ripaddr[0]) & 0xff, htons(conn->ripaddr[1]) >> 8,
+					 htons(conn->ripaddr[1]) & 0xff, htons(conn->rport), states[conn->tcpstateflags & UIP_TS_MASK], conn->nrtx, conn->timer,
+					 (uip_outstanding(conn)) ? '*' : ' ', (uip_stopped(conn)) ? '!' : ' ' );
+}
+
+/*---------------------------------------------------------------------------*/
+static PT_THREAD( tcp_stats ( struct httpd_state *s, char *ptr ) )
+{
+	PSOCK_BEGIN( &s->sout );
+
+	for( s->count = 0; s->count < UIP_CONNS; ++s->count )
+	{
+		if( (uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED )
+		{
+			PSOCK_GENERATOR_SEND( &s->sout, generate_tcp_stats, s );
+		}
+	}
+
+	PSOCK_END( &s->sout );
+}
+
+/*---------------------------------------------------------------------------*/
+static unsigned short generate_net_stats( void *arg )
+{
+	struct httpd_state	*s = ( struct httpd_state * ) arg;
+	return snprintf( ( char * ) uip_appdata, UIP_APPDATA_SIZE, "%5u\n", (( uip_stats_t * ) &uip_stat)[s->count] );
+}
+
+static PT_THREAD( net_stats ( struct httpd_state *s, char *ptr ) )
+{
+	PSOCK_BEGIN( &s->sout );
+
+#if UIP_STATISTICS
+	for( s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t); ++s->count )
+	{
+		PSOCK_GENERATOR_SEND( &s->sout, generate_net_stats, s );
+	}
+
+#endif /* UIP_STATISTICS */
+
+	PSOCK_END( &s->sout );
+}
+
+/*---------------------------------------------------------------------------*/
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-cgi.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-cgi.h
new file mode 100644
index 0000000..99b61fe
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-cgi.h
@@ -0,0 +1,85 @@
+/**
+ * \addtogroup httpd
+ * @{
+ */
+
+/**
+ * \file
+ *         Web server script interface header file
+ * \author
+ *         Adam Dunkels 
+ *
+ */
+
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $
+ *
+ */
+#ifndef __HTTPD_CGI_H__
+#define __HTTPD_CGI_H__
+
+#include "net/psock.h"
+#include "httpd.h"
+
+typedef				PT_THREAD( (*httpd_cgifunction) ( struct httpd_state *, char * ) );
+
+httpd_cgifunction	httpd_cgi( char *name );
+
+struct httpd_cgi_call
+{
+	const char				*name;
+	const httpd_cgifunction function;
+};
+
+/**
+ * \brief      HTTPD CGI function declaration
+ * \param name The C variable name of the function
+ * \param str  The string name of the function, used in the script file
+ * \param function A pointer to the function that implements it
+ *
+ *             This macro is used for declaring a HTTPD CGI
+ *             function. This function is then added to the list of
+ *             HTTPD CGI functions with the httpd_cgi_add() function.
+ *
+ * \hideinitializer
+ */
+#define HTTPD_CGI_CALL( name, str, function )						  \
+	static	  PT_THREAD( function ( struct httpd_state *, char * ) ); \
+	static const struct httpd_cgi_call					name =		  \
+	{																  \
+		str, function												  \
+	}
+
+void httpd_cgi_init( void );
+#endif /* __HTTPD_CGI_H__ */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-fs.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-fs.c
new file mode 100644
index 0000000..12084ce
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-fs.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $
+ */
+#include "httpd.h"
+#include "httpd-fs.h"
+#include "httpd-fsdata.h"
+
+#ifndef NULL
+#define NULL	0
+#endif /* NULL */
+
+#include "httpd-fsdata.c"
+
+#if HTTPD_FS_STATISTICS
+static u16_t	count[HTTPD_FS_NUMFILES];
+#endif /* HTTPD_FS_STATISTICS */
+
+/*-----------------------------------------------------------------------------------*/
+static u8_t httpd_fs_strcmp( const char *str1, const char *str2 )
+{
+	u8_t	i;
+	i = 0;
+loop:
+	if( str2[i] == 0 || str1[i] == '\r' || str1[i] == '\n' )
+	{
+		return 0;
+	}
+
+	if( str1[i] != str2[i] )
+	{
+		return 1;
+	}
+
+	++i;
+	goto loop;
+}
+
+/*-----------------------------------------------------------------------------------*/
+int httpd_fs_open( const char *name, struct httpd_fs_file *file )
+{
+#if HTTPD_FS_STATISTICS
+	u16_t								i = 0;
+#endif /* HTTPD_FS_STATISTICS */
+	struct httpd_fsdata_file_noconst	*f;
+
+	for( f = ( struct httpd_fsdata_file_noconst * ) HTTPD_FS_ROOT; f != NULL; f = ( struct httpd_fsdata_file_noconst * ) f->next )
+	{
+		if( httpd_fs_strcmp(name, f->name) == 0 )
+		{
+			file->data = f->data;
+			file->len = f->len;
+#if HTTPD_FS_STATISTICS
+			++count[i];
+#endif /* HTTPD_FS_STATISTICS */
+			return 1;
+		}
+
+#if HTTPD_FS_STATISTICS
+		++i;
+#endif /* HTTPD_FS_STATISTICS */
+	}
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------------------*/
+void httpd_fs_init( void )
+{
+#if HTTPD_FS_STATISTICS
+	u16_t	i;
+	for( i = 0; i < HTTPD_FS_NUMFILES; i++ )
+	{
+		count[i] = 0;
+	}
+
+#endif /* HTTPD_FS_STATISTICS */
+}
+
+/*-----------------------------------------------------------------------------------*/
+#if HTTPD_FS_STATISTICS
+u16_t httpd_fs_count( char *name )
+{
+	struct httpd_fsdata_file_noconst	*f;
+	u16_t								i;
+
+	i = 0;
+	for( f = ( struct httpd_fsdata_file_noconst * ) HTTPD_FS_ROOT; f != NULL; f = ( struct httpd_fsdata_file_noconst * ) f->next )
+	{
+		if( httpd_fs_strcmp(name, f->name) == 0 )
+		{
+			return count[i];
+		}
+
+		++i;
+	}
+
+	return 0;
+}
+
+#endif /* HTTPD_FS_STATISTICS */
+
+/*-----------------------------------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-fs.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-fs.h
new file mode 100644
index 0000000..afc6bbc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-fs.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $
+ */
+#ifndef __HTTPD_FS_H__
+#define __HTTPD_FS_H__
+
+#define HTTPD_FS_STATISTICS 1
+
+struct httpd_fs_file
+{
+	char	*data;
+	int		len;
+};
+
+/* file must be allocated by caller and will be filled in
+   by the function. */
+int		httpd_fs_open( const char *name, struct httpd_fs_file *file );
+
+#ifdef HTTPD_FS_STATISTICS
+#if HTTPD_FS_STATISTICS == 1
+u16_t	httpd_fs_count( char *name );
+#endif /* HTTPD_FS_STATISTICS */
+#endif /* HTTPD_FS_STATISTICS */
+
+void	httpd_fs_init( void );
+#endif /* __HTTPD_FS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-fsdata.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-fsdata.h
new file mode 100644
index 0000000..6fe210c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd-fsdata.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ * $Id: httpd-fsdata.h,v 1.1 2006/06/17 22:41:14 adamdunkels Exp $
+ */
+#ifndef __HTTPD_FSDATA_H__
+#define __HTTPD_FSDATA_H__
+
+struct httpd_fsdata_file {
+  const struct httpd_fsdata_file *next;
+  const char *name;
+  const char *data;
+  const int len;
+#ifdef HTTPD_FS_STATISTICS
+#if HTTPD_FS_STATISTICS == 1
+  u16_t count;
+#endif /* HTTPD_FS_STATISTICS */
+#endif /* HTTPD_FS_STATISTICS */
+};
+
+struct httpd_fsdata_file_noconst {
+  struct httpd_fsdata_file *next;
+  char *name;
+  char *data;
+  int len;
+#ifdef HTTPD_FS_STATISTICS
+#if HTTPD_FS_STATISTICS == 1
+  u16_t count;
+#endif /* HTTPD_FS_STATISTICS */
+#endif /* HTTPD_FS_STATISTICS */
+};
+
+#endif /* __HTTPD_FSDATA_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd.c
new file mode 100644
index 0000000..99564a9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd.c
@@ -0,0 +1,400 @@
+/**
+ * \addtogroup apps
+ * @{
+ */
+
+/**
+ * \defgroup httpd Web server
+ * @{
+ * The uIP web server is a very simplistic implementation of an HTTP
+ * server. It can serve web pages and files from a read-only ROM
+ * filesystem, and provides a very small scripting language.
+
+ */
+
+/**
+ * \file
+ *         Web server
+ * \author
+ *         Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2004, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $
+ */
+#include "net/uip.h"
+#include "apps/httpd/httpd.h"
+#include "apps/httpd/httpd-fs.h"
+#include "apps/httpd/httpd-cgi.h"
+#include "apps/httpd/http-strings.h"
+
+#include 
+
+#define STATE_WAITING	0
+#define STATE_OUTPUT	1
+
+#define ISO_nl			0x0a
+#define ISO_space		0x20
+#define ISO_bang		0x21
+#define ISO_percent		0x25
+#define ISO_period		0x2e
+#define ISO_slash		0x2f
+#define ISO_colon		0x3a
+
+/*---------------------------------------------------------------------------*/
+static unsigned short generate_part_of_file( void *state )
+{
+	struct httpd_state	*s = ( struct httpd_state * ) state;
+
+	if( s->file.len > uip_mss() )
+	{
+		s->len = uip_mss();
+	}
+	else
+	{
+		s->len = s->file.len;
+	}
+
+	memcpy( uip_appdata, s->file.data, s->len );
+
+	return s->len;
+}
+
+/*---------------------------------------------------------------------------*/
+static PT_THREAD( send_file ( struct httpd_state *s ) )
+{
+	PSOCK_BEGIN( &s->sout );
+
+	( void ) PT_YIELD_FLAG;
+	
+	do
+	{
+		PSOCK_GENERATOR_SEND( &s->sout, generate_part_of_file, s );
+		s->file.len -= s->len;
+		s->file.data += s->len;
+	} while( s->file.len > 0 );
+
+	PSOCK_END( &s->sout );
+}
+
+/*---------------------------------------------------------------------------*/
+static PT_THREAD( send_part_of_file ( struct httpd_state *s ) )
+{
+	PSOCK_BEGIN( &s->sout );
+	( void ) PT_YIELD_FLAG;
+	
+	PSOCK_SEND( &s->sout, s->file.data, s->len );
+
+	PSOCK_END( &s->sout );
+}
+
+/*---------------------------------------------------------------------------*/
+static void next_scriptstate( struct httpd_state *s )
+{
+	char	*p;
+	p = strchr( s->scriptptr, ISO_nl ) + 1;
+	s->scriptlen -= ( unsigned short ) ( p - s->scriptptr );
+	s->scriptptr = p;
+}
+
+/*---------------------------------------------------------------------------*/
+static PT_THREAD( handle_script ( struct httpd_state *s ) )
+{
+	char	*ptr;
+
+	PT_BEGIN( &s->scriptpt );
+	( void ) PT_YIELD_FLAG;
+	while( s->file.len > 0 )
+	{
+		/* Check if we should start executing a script. */
+		if( *s->file.data == ISO_percent && *(s->file.data + 1) == ISO_bang )
+		{
+			s->scriptptr = s->file.data + 3;
+			s->scriptlen = s->file.len - 3;
+			if( *(s->scriptptr - 1) == ISO_colon )
+			{
+				httpd_fs_open( s->scriptptr + 1, &s->file );
+				PT_WAIT_THREAD( &s->scriptpt, send_file(s) );
+			}
+			else
+			{
+				PT_WAIT_THREAD( &s->scriptpt, httpd_cgi(s->scriptptr) (s, s->scriptptr) );
+			}
+
+			next_scriptstate( s );
+
+			/* The script is over, so we reset the pointers and continue
+	 		sending the rest of the file. */
+			s->file.data = s->scriptptr;
+			s->file.len = s->scriptlen;
+		}
+		else
+		{
+			/* See if we find the start of script marker in the block of HTML
+	 to be sent. */
+			if( s->file.len > uip_mss() )
+			{
+				s->len = uip_mss();
+			}
+			else
+			{
+				s->len = s->file.len;
+			}
+
+			if( *s->file.data == ISO_percent )
+			{
+				ptr = strchr( s->file.data + 1, ISO_percent );
+			}
+			else
+			{
+				ptr = strchr( s->file.data, ISO_percent );
+			}
+
+			if( ptr != NULL && ptr != s->file.data )
+			{
+				s->len = ( int ) ( ptr - s->file.data );
+				if( s->len >= uip_mss() )
+				{
+					s->len = uip_mss();
+				}
+			}
+
+			PT_WAIT_THREAD( &s->scriptpt, send_part_of_file(s) );
+			s->file.data += s->len;
+			s->file.len -= s->len;
+		}
+	}
+
+	PT_END( &s->scriptpt );
+}
+
+/*---------------------------------------------------------------------------*/
+static PT_THREAD( send_headers ( struct httpd_state *s, const char *statushdr ) )
+{
+	char	*ptr;
+
+	PSOCK_BEGIN( &s->sout );
+	( void ) PT_YIELD_FLAG;
+	PSOCK_SEND_STR( &s->sout, statushdr );
+
+	ptr = strrchr( s->filename, ISO_period );
+	if( ptr == NULL )
+	{
+		PSOCK_SEND_STR( &s->sout, http_content_type_binary );
+	}
+	else if( strncmp(http_html, ptr, 5) == 0 || strncmp(http_shtml, ptr, 6) == 0 )
+	{
+		PSOCK_SEND_STR( &s->sout, http_content_type_html );
+	}
+	else if( strncmp(http_css, ptr, 4) == 0 )
+	{
+		PSOCK_SEND_STR( &s->sout, http_content_type_css );
+	}
+	else if( strncmp(http_png, ptr, 4) == 0 )
+	{
+		PSOCK_SEND_STR( &s->sout, http_content_type_png );
+	}
+	else if( strncmp(http_gif, ptr, 4) == 0 )
+	{
+		PSOCK_SEND_STR( &s->sout, http_content_type_gif );
+	}
+	else if( strncmp(http_jpg, ptr, 4) == 0 )
+	{
+		PSOCK_SEND_STR( &s->sout, http_content_type_jpg );
+	}
+	else
+	{
+		PSOCK_SEND_STR( &s->sout, http_content_type_plain );
+	}
+
+	PSOCK_END( &s->sout );
+}
+
+/*---------------------------------------------------------------------------*/
+static PT_THREAD( handle_output ( struct httpd_state *s ) )
+{
+	char	*ptr;
+
+	PT_BEGIN( &s->outputpt );
+	( void ) PT_YIELD_FLAG;
+	if( !httpd_fs_open(s->filename, &s->file) )
+	{
+		httpd_fs_open( http_404_html, &s->file );
+		strcpy( s->filename, http_404_html );
+		PT_WAIT_THREAD( &s->outputpt, send_headers(s, http_header_404) );
+		PT_WAIT_THREAD( &s->outputpt, send_file(s) );
+	}
+	else
+	{
+		PT_WAIT_THREAD( &s->outputpt, send_headers(s, http_header_200) );
+		ptr = strchr( s->filename, ISO_period );
+		if( ptr != NULL && strncmp(ptr, http_shtml, 6) == 0 )
+		{
+			PT_INIT( &s->scriptpt );
+			PT_WAIT_THREAD( &s->outputpt, handle_script(s) );
+		}
+		else
+		{
+			PT_WAIT_THREAD( &s->outputpt, send_file(s) );
+		}
+	}
+
+	PSOCK_CLOSE( &s->sout );
+	PT_END( &s->outputpt );
+}
+
+/*---------------------------------------------------------------------------*/
+static PT_THREAD( handle_input ( struct httpd_state *s ) )
+{
+	PSOCK_BEGIN( &s->sin );
+	( void ) PT_YIELD_FLAG;
+	PSOCK_READTO( &s->sin, ISO_space );
+
+	if( strncmp(s->inputbuf, http_get, 4) != 0 )
+	{
+		PSOCK_CLOSE_EXIT( &s->sin );
+	}
+
+	PSOCK_READTO( &s->sin, ISO_space );
+
+	if( s->inputbuf[0] != ISO_slash )
+	{
+		PSOCK_CLOSE_EXIT( &s->sin );
+	}
+
+	if( s->inputbuf[1] == ISO_space )
+	{
+		strncpy( s->filename, http_index_html, sizeof(s->filename) );
+	}
+	else
+	{
+		s->inputbuf[PSOCK_DATALEN( &s->sin ) - 1] = 0;
+		
+		/* Process any form input being sent to the server. */
+		#if UIP_CONF_PROCESS_HTTPD_FORMS == 1
+		{
+			extern void vApplicationProcessFormInput( char *pcInputString );
+			vApplicationProcessFormInput( s->inputbuf );
+		}
+		#endif
+		
+		strncpy( s->filename, &s->inputbuf[0], sizeof(s->filename) );
+	}
+
+	/*  httpd_log_file(uip_conn->ripaddr, s->filename);*/
+	s->state = STATE_OUTPUT;
+
+	while( 1 )
+	{
+		PSOCK_READTO( &s->sin, ISO_nl );
+
+		if( strncmp(s->inputbuf, http_referer, 8) == 0 )
+		{
+			s->inputbuf[PSOCK_DATALEN( &s->sin ) - 2] = 0;
+
+			/*      httpd_log(&s->inputbuf[9]);*/
+		}
+	}
+
+	PSOCK_END( &s->sin );
+}
+
+/*---------------------------------------------------------------------------*/
+static void handle_connection( struct httpd_state *s )
+{
+	handle_input( s );
+	if( s->state == STATE_OUTPUT )
+	{
+		handle_output( s );
+	}
+}
+
+/*---------------------------------------------------------------------------*/
+void httpd_appcall( void )
+{
+	struct httpd_state	*s = ( struct httpd_state * ) &( uip_conn->appstate );
+
+	if( uip_closed() || uip_aborted() || uip_timedout() )
+	{
+	}
+	else if( uip_connected() )
+	{
+		PSOCK_INIT( &s->sin, s->inputbuf, sizeof(s->inputbuf) - 1 );
+		PSOCK_INIT( &s->sout, s->inputbuf, sizeof(s->inputbuf) - 1 );
+		PT_INIT( &s->outputpt );
+		s->state = STATE_WAITING;
+
+		/*    timer_set(&s->timer, CLOCK_SECOND * 100);*/
+		s->timer = 0;
+		handle_connection( s );
+	}
+	else if( s != NULL )
+	{
+		if( uip_poll() )
+		{
+			++s->timer;
+			if( s->timer >= 20 )
+			{
+				uip_abort();
+			}
+		}
+		else
+		{
+			s->timer = 0;
+		}
+
+		handle_connection( s );
+	}
+	else
+	{
+		uip_abort();
+	}
+}
+
+/*---------------------------------------------------------------------------*/
+
+/**
+ * \brief      Initialize the web server
+ *
+ *             This function initializes the web server and should be
+ *             called at system boot-up.
+ */
+void httpd_init( void )
+{
+	uip_listen( HTONS(80) );
+}
+
+/*---------------------------------------------------------------------------*/
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd.h
new file mode 100644
index 0000000..cd2b891
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/httpd.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2001-2005, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $
+ *
+ */
+#ifndef __HTTPD_H__
+#define __HTTPD_H__
+
+#include "net/psock.h"
+#include "httpd-fs.h"
+
+struct httpd_state
+{
+	unsigned char			timer;
+	struct psock			sin, sout;
+	struct pt				outputpt, scriptpt;
+	char					inputbuf[50];
+	char					filename[20];
+	char					state;
+	struct httpd_fs_file	file;
+	int						len;
+	char					*scriptptr;
+	int						scriptlen;
+
+	unsigned short			count;
+};
+
+void	httpd_init( void );
+void	httpd_appcall( void );
+
+void	httpd_log( char *msg );
+void	httpd_log_file( u16_t *requester, char *file );
+#endif /* __HTTPD_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/makefsdata b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/makefsdata
new file mode 100644
index 0000000..b2109ab
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/apps/httpd/makefsdata
@@ -0,0 +1,78 @@
+#!/usr/bin/perl
+
+open(OUTPUT, "> httpd-fsdata.c");
+
+chdir("httpd-fs");
+
+opendir(DIR, ".");
+@files =  grep { !/^\./ && !/(CVS|~)/ } readdir(DIR);
+closedir(DIR);
+
+foreach $file (@files) {  
+   
+    if(-d $file && $file !~ /^\./) {
+	print "Processing directory $file\n";
+	opendir(DIR, $file);
+	@newfiles =  grep { !/^\./ && !/(CVS|~)/ } readdir(DIR);
+	closedir(DIR);
+	printf "Adding files @newfiles\n";
+	@files = (@files, map { $_ = "$file/$_" } @newfiles);
+	next;
+    }
+}
+
+foreach $file (@files) {
+    if(-f $file) {
+	
+	print "Adding file $file\n";
+	
+	open(FILE, $file) || die "Could not open file $file\n";
+
+	$file =~ s-^-/-;
+	$fvar = $file;
+	$fvar =~ s-/-_-g;
+	$fvar =~ s-\.-_-g;
+	# for AVR, add PROGMEM here
+	print(OUTPUT "static const unsigned char data".$fvar."[] = {\n");
+	print(OUTPUT "\t/* $file */\n\t");
+	for($j = 0; $j < length($file); $j++) {
+	    printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1)));
+	}
+	printf(OUTPUT "0,\n");
+	
+	
+	$i = 0;        
+	while(read(FILE, $data, 1)) {
+	    if($i == 0) {
+		print(OUTPUT "\t");
+	    }
+	    printf(OUTPUT "%#02x, ", unpack("C", $data));
+	    $i++;
+	    if($i == 10) {
+		print(OUTPUT "\n");
+		$i = 0;
+	    }
+	}
+	print(OUTPUT "0};\n\n");
+	close(FILE);
+	push(@fvars, $fvar);
+	push(@pfiles, $file);
+    }
+}
+
+for($i = 0; $i < @fvars; $i++) {
+    $file = $pfiles[$i];
+    $fvar = $fvars[$i];
+
+    if($i == 0) {
+        $prevfile = "NULL";
+    } else {
+        $prevfile = "file" . $fvars[$i - 1];
+    }
+    print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, ");
+    print(OUTPUT "data$fvar + ". (length($file) + 1) .", ");
+    print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n");
+}
+
+print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n");
+print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n");
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/clock-arch.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/clock-arch.h
new file mode 100644
index 0000000..293e026
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/clock-arch.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $
+ */
+
+#ifndef __CLOCK_ARCH_H__
+#define __CLOCK_ARCH_H__
+
+#include "FreeRTOS.h"
+
+typedef TickType_t clock_time_t;
+#define CLOCK_CONF_SECOND configTICK_RATE_HZ
+
+#endif /* __CLOCK_ARCH_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/lc-switch.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/lc-switch.h
new file mode 100644
index 0000000..17c8811
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/lc-switch.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2004-2005, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: lc-switch.h,v 1.2 2006/06/12 08:00:30 adam Exp $
+ */
+
+/**
+ * \addtogroup lc
+ * @{
+ */
+
+/**
+ * \file
+ * Implementation of local continuations based on switch() statment
+ * \author Adam Dunkels 
+ *
+ * This implementation of local continuations uses the C switch()
+ * statement to resume execution of a function somewhere inside the
+ * function's body. The implementation is based on the fact that
+ * switch() statements are able to jump directly into the bodies of
+ * control structures such as if() or while() statmenets.
+ *
+ * This implementation borrows heavily from Simon Tatham's coroutines
+ * implementation in C:
+ * http://www.chiark.greenend.org.uk/~sgtatham/coroutines.html
+ */
+
+#ifndef __LC_SWITCH_H__
+#define __LC_SWTICH_H__
+
+/* WARNING! lc implementation using switch() does not work if an
+   LC_SET() is done within another switch() statement! */
+
+/** \hideinitializer */
+typedef unsigned short lc_t;
+
+#define LC_INIT(s) s = 0;
+
+#define LC_RESUME(s) switch(s) { case 0:
+
+#define LC_SET(s) s = __LINE__; case __LINE__:
+
+#define LC_END(s) }
+
+#endif /* __LC_SWITCH_H__ */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/lc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/lc.h
new file mode 100644
index 0000000..3ad83cd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/lc.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2004-2005, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: lc.h,v 1.2 2006/06/12 08:00:30 adam Exp $
+ */
+
+/**
+ * \addtogroup pt
+ * @{
+ */
+
+/**
+ * \defgroup lc Local continuations
+ * @{
+ *
+ * Local continuations form the basis for implementing protothreads. A
+ * local continuation can be set in a specific function to
+ * capture the state of the function. After a local continuation has
+ * been set can be resumed in order to restore the state of the
+ * function at the point where the local continuation was set.
+ *
+ *
+ */
+
+/**
+ * \file lc.h
+ * Local continuations
+ * \author
+ * Adam Dunkels 
+ *
+ */
+
+#ifdef DOXYGEN
+/**
+ * Initialize a local continuation.
+ *
+ * This operation initializes the local continuation, thereby
+ * unsetting any previously set continuation state.
+ *
+ * \hideinitializer
+ */
+#define LC_INIT(lc)
+
+/**
+ * Set a local continuation.
+ *
+ * The set operation saves the state of the function at the point
+ * where the operation is executed. As far as the set operation is
+ * concerned, the state of the function does not include the
+ * call-stack or local (automatic) variables, but only the program
+ * counter and such CPU registers that needs to be saved.
+ *
+ * \hideinitializer
+ */
+#define LC_SET(lc)
+
+/**
+ * Resume a local continuation.
+ *
+ * The resume operation resumes a previously set local continuation, thus
+ * restoring the state in which the function was when the local
+ * continuation was set. If the local continuation has not been
+ * previously set, the resume operation does nothing.
+ *
+ * \hideinitializer
+ */
+#define LC_RESUME(lc)
+
+/**
+ * Mark the end of local continuation usage.
+ *
+ * The end operation signifies that local continuations should not be
+ * used any more in the function. This operation is not needed for
+ * most implementations of local continuation, but is required by a
+ * few implementations.
+ *
+ * \hideinitializer
+ */
+#define LC_END(lc)
+
+/**
+ * \var typedef lc_t;
+ *
+ * The local continuation type.
+ *
+ * \hideinitializer
+ */
+#endif /* DOXYGEN */
+
+#ifndef __LC_H__
+#define __LC_H__
+
+#ifdef LC_CONF_INCLUDE
+#include LC_CONF_INCLUDE
+#else
+#include "lc-switch.h"
+#endif /* LC_CONF_INCLUDE */
+
+#endif /* __LC_H__ */
+
+/** @} */
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/pack_struct_end.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/pack_struct_end.h
new file mode 100644
index 0000000..a23febe
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/pack_struct_end.h
@@ -0,0 +1,33 @@
+#ifdef __GNUC__
+	__attribute__( (packed) );
+#endif
+
+#ifdef _SH
+	#ifdef __RENESAS__
+		;
+		#pragma unpack
+	#endif
+#endif
+
+#ifdef __RX
+	#ifdef __RENESAS__
+		;
+		/* Nothing to do. */
+	#endif
+#endif
+
+
+#ifdef __ICCRX__
+	;
+	#pragma pack()
+#endif
+
+#ifdef __ICCARM__
+	;
+	#pragma pack()
+#endif
+
+
+#ifdef __CC_ARM
+	;
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/pack_struct_start.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/pack_struct_start.h
new file mode 100644
index 0000000..49a4dc9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/pack_struct_start.h
@@ -0,0 +1,34 @@
+#ifdef __GNUC__
+
+/* Nothing to do here. */
+;
+#endif
+
+/* Used by SH2A port. */
+#ifdef _SH
+	#ifdef __RENESAS__
+		#pragma pack 1
+	#endif
+#endif
+
+
+#ifdef __RX
+	#ifdef __RENESAS__
+		/* Nothing to do. */
+	#endif
+#endif
+
+
+#ifdef __ICCRX__
+	#pragma pack(1)
+#endif
+
+
+#ifdef __ICCARM__
+	#pragma pack(1)
+#endif
+
+#ifdef __CC_ARM
+	__packed
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/psock.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/psock.h
new file mode 100644
index 0000000..8d41258
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/psock.h
@@ -0,0 +1,380 @@
+/*
+ * Copyright (c) 2004, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: psock.h,v 1.3 2006/06/12 08:00:30 adam Exp $
+ */
+
+/**
+ * \defgroup psock Protosockets library
+ * @{
+ *
+ * The protosocket library provides an interface to the uIP stack that is
+ * similar to the traditional BSD socket interface. Unlike programs
+ * written for the ordinary uIP event-driven interface, programs
+ * written with the protosocket library are executed in a sequential
+ * fashion and does not have to be implemented as explicit state
+ * machines.
+ *
+ * Protosockets only work with TCP connections.
+ *
+ * The protosocket library uses \ref pt protothreads to provide
+ * sequential control flow. This makes the protosockets lightweight in
+ * terms of memory, but also means that protosockets inherits the
+ * functional limitations of protothreads. Each protosocket lives only
+ * within a single function. Automatic variables (stack variables) are
+ * not retained across a protosocket library function call.
+ *
+ * \note Because the protosocket library uses protothreads, local
+ * variables will not always be saved across a call to a protosocket
+ * library function. It is therefore advised that local variables are
+ * used with extreme care.
+ *
+ * The protosocket library provides functions for sending data without
+ * having to deal with retransmissions and acknowledgements, as well
+ * as functions for reading data without having to deal with data
+ * being split across more than one TCP segment.
+ *
+ * Because each protosocket runs as a protothread, the protosocket has to be
+ * started with a call to PSOCK_BEGIN() at the start of the function
+ * in which the protosocket is used. Similarly, the protosocket protothread can
+ * be terminated by a call to PSOCK_EXIT().
+ *
+ */
+
+/**
+ * \file
+ * Protosocket library header file
+ * \author
+ * Adam Dunkels 
+ *
+ */
+
+#ifndef __PSOCK_H__
+#define __PSOCK_H__
+
+#include "uipopt.h"
+#include "pt.h"
+
+ /*
+ * The structure that holds the state of a buffer.
+ *
+ * This structure holds the state of a uIP buffer. The structure has
+ * no user-visible elements, but is used through the functions
+ * provided by the library.
+ *
+ */
+struct psock_buf {
+  u8_t *ptr;
+  unsigned short left;
+};
+
+/**
+ * The representation of a protosocket.
+ *
+ * The protosocket structrure is an opaque structure with no user-visible
+ * elements.
+ */
+struct psock {
+  struct pt pt, psockpt; /* Protothreads - one that's using the psock
+			    functions, and one that runs inside the
+			    psock functions. */
+  const u8_t *sendptr;   /* Pointer to the next data to be sent. */
+  u8_t *readptr;         /* Pointer to the next data to be read. */
+  
+  char *bufptr;          /* Pointer to the buffer used for buffering
+			    incoming data. */
+  
+  u16_t sendlen;         /* The number of bytes left to be sent. */
+  u16_t readlen;         /* The number of bytes left to be read. */
+
+  struct psock_buf buf;  /* The structure holding the state of the
+			    input buffer. */
+  unsigned int bufsize;  /* The size of the input buffer. */
+  
+  unsigned char state;   /* The state of the protosocket. */
+};
+
+void psock_init(struct psock *psock, char *buffer, unsigned int buffersize);
+/**
+ * Initialize a protosocket.
+ *
+ * This macro initializes a protosocket and must be called before the
+ * protosocket is used. The initialization also specifies the input buffer
+ * for the protosocket.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket to be
+ * initialized
+ *
+ * \param buffer (char *) A pointer to the input buffer for the
+ * protosocket.
+ *
+ * \param buffersize (unsigned int) The size of the input buffer.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_INIT(psock, buffer, buffersize) \
+  psock_init(psock, buffer, buffersize)
+
+/**
+ * Start the protosocket protothread in a function.
+ *
+ * This macro starts the protothread associated with the protosocket and
+ * must come before other protosocket calls in the function it is used.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket to be
+ * started.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_BEGIN(psock) PT_BEGIN(&((psock)->pt))
+
+PT_THREAD(psock_send(struct psock *psock, const char *buf, unsigned int len));
+/**
+ * Send data.
+ *
+ * This macro sends data over a protosocket. The protosocket protothread blocks
+ * until all data has been sent and is known to have been received by
+ * the remote end of the TCP connection.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket over which
+ * data is to be sent.
+ *
+ * \param data (char *) A pointer to the data that is to be sent.
+ *
+ * \param datalen (unsigned int) The length of the data that is to be
+ * sent.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_SEND(psock, data, datalen)		\
+    PT_WAIT_THREAD(&((psock)->pt), psock_send(psock, data, datalen))
+
+/**
+ * \brief      Send a null-terminated string.
+ * \param psock Pointer to the protosocket.
+ * \param str  The string to be sent.
+ *
+ *             This function sends a null-terminated string over the
+ *             protosocket.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_SEND_STR(psock, str)      		\
+    PT_WAIT_THREAD(&((psock)->pt), psock_send(psock, str, strlen(str)))
+
+PT_THREAD(psock_generator_send(struct psock *psock,
+				unsigned short (*f)(void *), void *arg));
+
+/**
+ * \brief      Generate data with a function and send it
+ * \param psock Pointer to the protosocket.
+ * \param generator Pointer to the generator function
+ * \param arg   Argument to the generator function
+ *
+ *             This function generates data and sends it over the
+ *             protosocket. This can be used to dynamically generate
+ *             data for a transmission, instead of generating the data
+ *             in a buffer beforehand. This function reduces the need for
+ *             buffer memory. The generator function is implemented by
+ *             the application, and a pointer to the function is given
+ *             as an argument with the call to PSOCK_GENERATOR_SEND().
+ *
+ *             The generator function should place the generated data
+ *             directly in the uip_appdata buffer, and return the
+ *             length of the generated data. The generator function is
+ *             called by the protosocket layer when the data first is
+ *             sent, and once for every retransmission that is needed.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_GENERATOR_SEND(psock, generator, arg)     \
+    PT_WAIT_THREAD(&((psock)->pt),					\
+		   psock_generator_send(psock, generator, arg))
+
+
+/**
+ * Close a protosocket.
+ *
+ * This macro closes a protosocket and can only be called from within the
+ * protothread in which the protosocket lives.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket that is to
+ * be closed.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_CLOSE(psock) uip_close()
+
+PT_THREAD(psock_readbuf(struct psock *psock));
+/**
+ * Read data until the buffer is full.
+ *
+ * This macro will block waiting for data and read the data into the
+ * input buffer specified with the call to PSOCK_INIT(). Data is read
+ * until the buffer is full..
+ *
+ * \param psock (struct psock *) A pointer to the protosocket from which
+ * data should be read.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_READBUF(psock)				\
+  PT_WAIT_THREAD(&((psock)->pt), psock_readbuf(psock))
+
+PT_THREAD(psock_readto(struct psock *psock, unsigned char c));
+/**
+ * Read data up to a specified character.
+ *
+ * This macro will block waiting for data and read the data into the
+ * input buffer specified with the call to PSOCK_INIT(). Data is only
+ * read until the specifieed character appears in the data stream.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket from which
+ * data should be read.
+ *
+ * \param c (char) The character at which to stop reading.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_READTO(psock, c)				\
+  PT_WAIT_THREAD(&((psock)->pt), psock_readto(psock, c))
+
+/**
+ * The length of the data that was previously read.
+ *
+ * This macro returns the length of the data that was previously read
+ * using PSOCK_READTO() or PSOCK_READ().
+ *
+ * \param psock (struct psock *) A pointer to the protosocket holding the data.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_DATALEN(psock) psock_datalen(psock)
+
+u16_t psock_datalen(struct psock *psock);
+
+/**
+ * Exit the protosocket's protothread.
+ *
+ * This macro terminates the protothread of the protosocket and should
+ * almost always be used in conjunction with PSOCK_CLOSE().
+ *
+ * \sa PSOCK_CLOSE_EXIT()
+ *
+ * \param psock (struct psock *) A pointer to the protosocket.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_EXIT(psock) PT_EXIT(&((psock)->pt))
+
+/**
+ * Close a protosocket and exit the protosocket's protothread.
+ *
+ * This macro closes a protosocket and exits the protosocket's protothread.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_CLOSE_EXIT(psock)		\
+  do {						\
+    PSOCK_CLOSE(psock);			\
+    PSOCK_EXIT(psock);			\
+  } while(0)
+
+/**
+ * Declare the end of a protosocket's protothread.
+ *
+ * This macro is used for declaring that the protosocket's protothread
+ * ends. It must always be used together with a matching PSOCK_BEGIN()
+ * macro.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_END(psock) PT_END(&((psock)->pt))
+
+char psock_newdata(struct psock *s);
+
+/**
+ * Check if new data has arrived on a protosocket.
+ *
+ * This macro is used in conjunction with the PSOCK_WAIT_UNTIL()
+ * macro to check if data has arrived on a protosocket.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_NEWDATA(psock) psock_newdata(psock)
+
+/**
+ * Wait until a condition is true.
+ *
+ * This macro blocks the protothread until the specified condition is
+ * true. The macro PSOCK_NEWDATA() can be used to check if new data
+ * arrives when the protosocket is waiting.
+ *
+ * Typically, this macro is used as follows:
+ *
+ \code
+ PT_THREAD(thread(struct psock *s, struct timer *t))
+ {
+   PSOCK_BEGIN(s);
+
+   PSOCK_WAIT_UNTIL(s, PSOCK_NEWADATA(s) || timer_expired(t));
+   
+   if(PSOCK_NEWDATA(s)) {
+     PSOCK_READTO(s, '\n');
+   } else {
+     handle_timed_out(s);
+   }
+   
+   PSOCK_END(s);
+ }
+ \endcode
+ *
+ * \param psock (struct psock *) A pointer to the protosocket.
+ * \param condition The condition to wait for.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_WAIT_UNTIL(psock, condition)    \
+  PT_WAIT_UNTIL(&((psock)->pt), (condition));
+
+#define PSOCK_WAIT_THREAD(psock, condition)   \
+  PT_WAIT_THREAD(&((psock)->pt), (condition))
+
+#endif /* __PSOCK_H__ */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/pt.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/pt.h
new file mode 100644
index 0000000..00ddd44
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/pt.h
@@ -0,0 +1,323 @@
+/*
+ * Copyright (c) 2004-2005, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: pt.h,v 1.2 2006/06/12 08:00:30 adam Exp $
+ */
+
+/**
+ * \addtogroup pt
+ * @{
+ */
+
+/**
+ * \file
+ * Protothreads implementation.
+ * \author
+ * Adam Dunkels 
+ *
+ */
+
+#ifndef __PT_H__
+#define __PT_H__
+
+#include "lc.h"
+
+struct pt {
+  lc_t lc;
+};
+
+#define PT_WAITING 0
+#define PT_EXITED  1
+#define PT_ENDED   2
+#define PT_YIELDED 3
+
+/**
+ * \name Initialization
+ * @{
+ */
+
+/**
+ * Initialize a protothread.
+ *
+ * Initializes a protothread. Initialization must be done prior to
+ * starting to execute the protothread.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \sa PT_SPAWN()
+ *
+ * \hideinitializer
+ */
+#define PT_INIT(pt)   LC_INIT((pt)->lc)
+
+/** @} */
+
+/**
+ * \name Declaration and definition
+ * @{
+ */
+
+/**
+ * Declaration of a protothread.
+ *
+ * This macro is used to declare a protothread. All protothreads must
+ * be declared with this macro.
+ *
+ * \param name_args The name and arguments of the C function
+ * implementing the protothread.
+ *
+ * \hideinitializer
+ */
+#define PT_THREAD(name_args) char name_args
+
+/**
+ * Declare the start of a protothread inside the C function
+ * implementing the protothread.
+ *
+ * This macro is used to declare the starting point of a
+ * protothread. It should be placed at the start of the function in
+ * which the protothread runs. All C statements above the PT_BEGIN()
+ * invokation will be executed each time the protothread is scheduled.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \hideinitializer
+ */
+#define PT_BEGIN(pt) { char PT_YIELD_FLAG = 1; LC_RESUME((pt)->lc)
+
+/**
+ * Declare the end of a protothread.
+ *
+ * This macro is used for declaring that a protothread ends. It must
+ * always be used together with a matching PT_BEGIN() macro.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \hideinitializer
+ */
+#define PT_END(pt) LC_END((pt)->lc); PT_YIELD_FLAG = 0; \
+                   PT_INIT(pt); return PT_ENDED; }
+
+/** @} */
+
+/**
+ * \name Blocked wait
+ * @{
+ */
+
+/**
+ * Block and wait until condition is true.
+ *
+ * This macro blocks the protothread until the specified condition is
+ * true.
+ *
+ * \param pt A pointer to the protothread control structure.
+ * \param condition The condition.
+ *
+ * \hideinitializer
+ */
+#define PT_WAIT_UNTIL(pt, condition)	        \
+  do {						\
+    LC_SET((pt)->lc);				\
+    if(!(condition)) {				\
+      return PT_WAITING;			\
+    }						\
+  } while(0)
+
+/**
+ * Block and wait while condition is true.
+ *
+ * This function blocks and waits while condition is true. See
+ * PT_WAIT_UNTIL().
+ *
+ * \param pt A pointer to the protothread control structure.
+ * \param cond The condition.
+ *
+ * \hideinitializer
+ */
+#define PT_WAIT_WHILE(pt, cond)  PT_WAIT_UNTIL((pt), !(cond))
+
+/** @} */
+
+/**
+ * \name Hierarchical protothreads
+ * @{
+ */
+
+/**
+ * Block and wait until a child protothread completes.
+ *
+ * This macro schedules a child protothread. The current protothread
+ * will block until the child protothread completes.
+ *
+ * \note The child protothread must be manually initialized with the
+ * PT_INIT() function before this function is used.
+ *
+ * \param pt A pointer to the protothread control structure.
+ * \param thread The child protothread with arguments
+ *
+ * \sa PT_SPAWN()
+ *
+ * \hideinitializer
+ */
+#define PT_WAIT_THREAD(pt, thread) PT_WAIT_WHILE((pt), PT_SCHEDULE(thread))
+
+/**
+ * Spawn a child protothread and wait until it exits.
+ *
+ * This macro spawns a child protothread and waits until it exits. The
+ * macro can only be used within a protothread.
+ *
+ * \param pt A pointer to the protothread control structure.
+ * \param child A pointer to the child protothread's control structure.
+ * \param thread The child protothread with arguments
+ *
+ * \hideinitializer
+ */
+#define PT_SPAWN(pt, child, thread)		\
+  do {						\
+    PT_INIT((child));				\
+    PT_WAIT_THREAD((pt), (thread));		\
+  } while(0)
+
+/** @} */
+
+/**
+ * \name Exiting and restarting
+ * @{
+ */
+
+/**
+ * Restart the protothread.
+ *
+ * This macro will block and cause the running protothread to restart
+ * its execution at the place of the PT_BEGIN() call.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \hideinitializer
+ */
+#define PT_RESTART(pt)				\
+  do {						\
+    PT_INIT(pt);				\
+    return PT_WAITING;			\
+  } while(0)
+
+/**
+ * Exit the protothread.
+ *
+ * This macro causes the protothread to exit. If the protothread was
+ * spawned by another protothread, the parent protothread will become
+ * unblocked and can continue to run.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \hideinitializer
+ */
+#define PT_EXIT(pt)				\
+  do {						\
+    PT_INIT(pt);				\
+    return PT_EXITED;			\
+  } while(0)
+
+/** @} */
+
+/**
+ * \name Calling a protothread
+ * @{
+ */
+
+/**
+ * Schedule a protothread.
+ *
+ * This function shedules a protothread. The return value of the
+ * function is non-zero if the protothread is running or zero if the
+ * protothread has exited.
+ *
+ * \param f The call to the C function implementing the protothread to
+ * be scheduled
+ *
+ * \hideinitializer
+ */
+#define PT_SCHEDULE(f) ((f) == PT_WAITING)
+
+/** @} */
+
+/**
+ * \name Yielding from a protothread
+ * @{
+ */
+
+/**
+ * Yield from the current protothread.
+ *
+ * This function will yield the protothread, thereby allowing other
+ * processing to take place in the system.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \hideinitializer
+ */
+#define PT_YIELD(pt)				\
+  do {						\
+    PT_YIELD_FLAG = 0;				\
+    LC_SET((pt)->lc);				\
+    if(PT_YIELD_FLAG == 0) {			\
+      return PT_YIELDED;			\
+    }						\
+  } while(0)
+
+/**
+ * \brief      Yield from the protothread until a condition occurs.
+ * \param pt   A pointer to the protothread control structure.
+ * \param cond The condition.
+ *
+ *             This function will yield the protothread, until the
+ *             specified condition evaluates to true.
+ *
+ *
+ * \hideinitializer
+ */
+#define PT_YIELD_UNTIL(pt, cond)		\
+  do {						\
+    PT_YIELD_FLAG = 0;				\
+    LC_SET((pt)->lc);				\
+    if((PT_YIELD_FLAG == 0) || !(cond)) {	\
+      return PT_YIELDED;			\
+    }						\
+  } while(0)
+
+/** @} */
+
+#endif /* __PT_H__ */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uip.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uip.h
new file mode 100644
index 0000000..3a0ed19
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uip.h
@@ -0,0 +1,2184 @@
+
+					 /**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \file
+ * Header file for the uIP TCP/IP stack.
+ * \author  Adam Dunkels 
+ * \author  Julien Abeille  (IPv6 related code)
+ * \author  Mathilde Durvy  (IPv6 related code)
+ *
+ * The uIP TCP/IP stack header file contains definitions for a number
+ * of C macros that are used by uIP programs as well as internal uIP
+ * structures, TCP/IP header structures and function declarations.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip.h,v 1.24 2009/04/06 13:18:50 nvt-se Exp $
+ *
+ */
+#ifndef __UIP_H__
+#define __UIP_H__
+
+#include "net/uipopt.h"
+#include "uip-conf.h"
+
+/**
+ * Representation of an IP address.
+ *
+ */
+#if UIP_CONF_IPV6 != 0
+	typedef union uip_ip6addr_t
+	{
+		u8_t	u8[16]; /* Initializer, must come first!!! */
+		u16_t	u16[8];
+	} uip_ip6addr_t;
+
+	typedef uip_ip6addr_t	uip_ipaddr_t;
+#else /* UIP_CONF_IPV6 */
+	#ifdef __CC_ARM
+		__packed /* The ARM compiler insists on this being packed, but with other compilers packing it generates a warning as it will be packed anyway. */
+	#endif
+
+	typedef union			uip_ip4addr_t
+	{
+		u8_t	u8[4];	/* Initializer, must come first!!! */
+		u16_t	u16[2];
+	} uip_ip4addr_t;
+	typedef uip_ip4addr_t	uip_ipaddr_t;
+#endif /* UIP_CONF_IPV6 */
+
+/*---------------------------------------------------------------------------*/
+
+/** \brief 16 bit 802.15.4 address */
+struct uip_802154_shortaddr
+{
+	u8_t	addr[2];
+};
+
+/** \brief 64 bit 802.15.4 address */
+struct uip_802154_longaddr
+{
+	u8_t	addr[8];
+};
+
+/** \brief 802.11 address */
+struct uip_80211_addr
+{
+	u8_t	addr[6];
+};
+
+/** \brief 802.3 address */
+#include "net/pack_struct_start.h"
+struct uip_eth_addr
+{
+	u8_t	addr[6];
+}
+#include "net/pack_struct_end.h"
+
+#ifdef UIP_CONF_LL_802154
+
+	/** \brief 802.15.4 address */
+	typedef struct uip_802154_longaddr	uip_lladdr_t;
+	#define UIP_802154_SHORTADDR_LEN	2
+	#define UIP_802154_LONGADDR_LEN		8
+	#define UIP_LLADDR_LEN				UIP_802154_LONGADDR_LEN
+#else /*UIP_CONF_LL_802154*/
+	#ifdef UIP_CONF_LL_80211
+		/** \brief 802.11 address */
+		typedef struct uip_80211_addr	uip_lladdr_t;
+		#define UIP_LLADDR_LEN	6
+	#else /*UIP_CONF_LL_80211*/
+
+		/** \brief Ethernet address */
+		typedef struct uip_eth_addr uip_lladdr_t;
+
+		#define UIP_LLADDR_LEN	6
+	#endif /*UIP_CONF_LL_80211*/
+#endif /*UIP_CONF_LL_802154*/
+
+//_RB_#include "net/tcpip.h"
+
+/*---------------------------------------------------------------------------*/
+
+/* First, the functions that should be called from the
+ * system. Initialization, the periodic timer, and incoming packets are
+ * handled by the following three functions.
+ */
+
+/**
+ * \defgroup uipconffunc uIP configuration functions
+ * @{
+ *
+ * The uIP configuration functions are used for setting run-time
+ * parameters in uIP such as IP addresses.
+ */
+
+/**
+ * Set the IP address of this host.
+ *
+ * The IP address is represented as a 4-byte array where the first
+ * octet of the IP address is put in the first member of the 4-byte
+ * array.
+ *
+ * Example:
+ \code
+
+ uip_ipaddr_t addr;
+
+ uip_ipaddr(&addr, 192,168,1,2);
+ uip_sethostaddr(&addr);
+
+ \endcode
+ * \param addr A pointer to an IP address of type uip_ipaddr_t;
+ *
+ * \sa uip_ipaddr()
+ *
+ * \hideinitializer
+ */
+#define uip_sethostaddr( addr ) uip_ipaddr_copy( &uip_hostaddr, (addr) )
+
+/**
+ * Get the IP address of this host.
+ *
+ * The IP address is represented as a 4-byte array where the first
+ * octet of the IP address is put in the first member of the 4-byte
+ * array.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t hostaddr;
+
+ uip_gethostaddr(&hostaddr);
+ \endcode
+ * \param addr A pointer to a uip_ipaddr_t variable that will be
+ * filled in with the currently configured IP address.
+ *
+ * \hideinitializer
+ */
+#define uip_gethostaddr( addr ) uip_ipaddr_copy( (addr), &uip_hostaddr )
+
+/**
+ * Set the default router's IP address.
+ *
+ * \param addr A pointer to a uip_ipaddr_t variable containing the IP
+ * address of the default router.
+ *
+ * \sa uip_ipaddr()
+ *
+ * \hideinitializer
+ */
+#define uip_setdraddr( addr )	uip_ipaddr_copy( &uip_draddr, (addr) )
+
+/**
+ * Set the netmask.
+ *
+ * \param addr A pointer to a uip_ipaddr_t variable containing the IP
+ * address of the netmask.
+ *
+ * \sa uip_ipaddr()
+ *
+ * \hideinitializer
+ */
+#define uip_setnetmask( addr )	uip_ipaddr_copy( &uip_netmask, (addr) )
+
+/**
+ * Get the default router's IP address.
+ *
+ * \param addr A pointer to a uip_ipaddr_t variable that will be
+ * filled in with the IP address of the default router.
+ *
+ * \hideinitializer
+ */
+#define uip_getdraddr( addr )	uip_ipaddr_copy( (addr), &uip_draddr )
+
+/**
+ * Get the netmask.
+ *
+ * \param addr A pointer to a uip_ipaddr_t variable that will be
+ * filled in with the value of the netmask.
+ *
+ * \hideinitializer
+ */
+#define uip_getnetmask( addr )	uip_ipaddr_copy( (addr), &uip_netmask )
+
+/** @} */
+
+/**
+ * \defgroup uipinit uIP initialization functions
+ * @{
+ *
+ * The uIP initialization functions are used for booting uIP.
+ */
+
+/**
+ * uIP initialization function.
+ *
+ * This function should be called at boot up to initilize the uIP
+ * TCP/IP stack.
+ */
+void	uip_init( void );
+
+/**
+ * uIP initialization function.
+ *
+ * This function may be used at boot time to set the initial ip_id.
+ */
+void	uip_setipid( u16_t id );
+
+/** @} */
+
+/**
+ * \defgroup uipdevfunc uIP device driver functions
+ * @{
+ *
+ * These functions are used by a network device driver for interacting
+ * with uIP.
+ */
+
+/**
+ * Process an incoming packet.
+ *
+ * This function should be called when the device driver has received
+ * a packet from the network. The packet from the device driver must
+ * be present in the uip_buf buffer, and the length of the packet
+ * should be placed in the uip_len variable.
+ *
+ * When the function returns, there may be an outbound packet placed
+ * in the uip_buf packet buffer. If so, the uip_len variable is set to
+ * the length of the packet. If no packet is to be sent out, the
+ * uip_len variable is set to 0.
+ *
+ * The usual way of calling the function is presented by the source
+ * code below.
+ \code
+ uip_len = devicedriver_poll();
+ if(uip_len > 0) {
+ uip_input();
+ if(uip_len > 0) {
+ devicedriver_send();
+ }
+ }
+ \endcode
+ *
+ * \note If you are writing a uIP device driver that needs ARP
+ * (Address Resolution Protocol), e.g., when running uIP over
+ * Ethernet, you will need to call the uIP ARP code before calling
+ * this function:
+ \code
+ #define BUF ((struct uip_eth_hdr *)&uip_buf[0])
+ uip_len = ethernet_devicedrver_poll();
+ if(uip_len > 0) {
+ if(BUF->type == HTONS(UIP_ETHTYPE_IP)) {
+ uip_arp_ipin();
+ uip_input();
+ if(uip_len > 0) {
+ uip_arp_out();
+ ethernet_devicedriver_send();
+ }
+ } else if(BUF->type == HTONS(UIP_ETHTYPE_ARP)) {
+ uip_arp_arpin();
+ if(uip_len > 0) {
+ ethernet_devicedriver_send();
+ }
+ }
+ \endcode
+ *
+ * \hideinitializer
+ */
+#define uip_input() uip_process( UIP_DATA )
+
+/**
+ * Periodic processing for a connection identified by its number.
+ *
+ * This function does the necessary periodic processing (timers,
+ * polling) for a uIP TCP conneciton, and should be called when the
+ * periodic uIP timer goes off. It should be called for every
+ * connection, regardless of whether they are open of closed.
+ *
+ * When the function returns, it may have an outbound packet waiting
+ * for service in the uIP packet buffer, and if so the uip_len
+ * variable is set to a value larger than zero. The device driver
+ * should be called to send out the packet.
+ *
+ * The usual way of calling the function is through a for() loop like
+ * this:
+ \code
+ for(i = 0; i < UIP_CONNS; ++i) {
+ uip_periodic(i);
+ if(uip_len > 0) {
+ devicedriver_send();
+ }
+ }
+ \endcode
+ *
+ * \note If you are writing a uIP device driver that needs ARP
+ * (Address Resolution Protocol), e.g., when running uIP over
+ * Ethernet, you will need to call the uip_arp_out() function before
+ * calling the device driver:
+ \code
+ for(i = 0; i < UIP_CONNS; ++i) {
+ uip_periodic(i);
+ if(uip_len > 0) {
+ uip_arp_out();
+ ethernet_devicedriver_send();
+ }
+ }
+ \endcode
+ *
+ * \param conn The number of the connection which is to be periodically polled.
+ *
+ * \hideinitializer
+ */
+#ifdef UIP_TCP
+#define uip_periodic( conn )		 \
+	do								 \
+	{								 \
+		uip_conn = &uip_conns[conn]; \
+		uip_process( UIP_TIMER );	 \
+	} while( 0 )
+
+/**
+ *
+ *
+ */
+#define uip_conn_active( conn ) ( uip_conns[conn].tcpstateflags != UIP_CLOSED )
+
+/**
+ * Perform periodic processing for a connection identified by a pointer
+ * to its structure.
+ *
+ * Same as uip_periodic() but takes a pointer to the actual uip_conn
+ * struct instead of an integer as its argument. This function can be
+ * used to force periodic processing of a specific connection.
+ *
+ * \param conn A pointer to the uip_conn struct for the connection to
+ * be processed.
+ *
+ * \hideinitializer
+ */
+#define uip_periodic_conn( conn ) \
+	do							  \
+	{							  \
+		uip_conn = conn;		  \
+		uip_process( UIP_TIMER ); \
+	} while( 0 )
+
+/**
+ * Request that a particular connection should be polled.
+ *
+ * Similar to uip_periodic_conn() but does not perform any timer
+ * processing. The application is polled for new data.
+ *
+ * \param conn A pointer to the uip_conn struct for the connection to
+ * be processed.
+ *
+ * \hideinitializer
+ */
+#define uip_poll_conn( conn )			 \
+	do									 \
+	{									 \
+		uip_conn = conn;				 \
+		uip_process( UIP_POLL_REQUEST ); \
+	} while( 0 )
+#endif /* UIP_TCP */
+
+#ifdef UIP_UDP
+
+/**
+ * Periodic processing for a UDP connection identified by its number.
+ *
+ * This function is essentially the same as uip_periodic(), but for
+ * UDP connections. It is called in a similar fashion as the
+ * uip_periodic() function:
+ \code
+ for(i = 0; i < UIP_UDP_CONNS; i++) {
+ uip_udp_periodic(i);
+ if(uip_len > 0) {
+ devicedriver_send();
+ }
+ }
+ \endcode
+ *
+ * \note As for the uip_periodic() function, special care has to be
+ * taken when using uIP together with ARP and Ethernet:
+ \code
+ for(i = 0; i < UIP_UDP_CONNS; i++) {
+ uip_udp_periodic(i);
+ if(uip_len > 0) {
+ uip_arp_out();
+ ethernet_devicedriver_send();
+ }
+ }
+ \endcode
+ *
+ * \param conn The number of the UDP connection to be processed.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_periodic( conn )			 \
+	do										 \
+	{										 \
+		uip_udp_conn = &uip_udp_conns[conn]; \
+		uip_process( UIP_UDP_TIMER );		 \
+	} while( 0 )
+
+/**
+ * Periodic processing for a UDP connection identified by a pointer to
+ * its structure.
+ *
+ * Same as uip_udp_periodic() but takes a pointer to the actual
+ * uip_conn struct instead of an integer as its argument. This
+ * function can be used to force periodic processing of a specific
+ * connection.
+ *
+ * \param conn A pointer to the uip_udp_conn struct for the connection
+ * to be processed.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_periodic_conn( conn ) \
+	do								  \
+	{								  \
+		uip_udp_conn = conn;		  \
+		uip_process( UIP_UDP_TIMER ); \
+	} while( 0 )
+#endif /* UIP_UDP */
+
+					/** \brief Abandon the reassembly of the current packet */
+					void	uip_reass_over( void );
+
+/**
+ * The uIP packet buffer.
+ *
+ * The uip_buf array is used to hold incoming and outgoing
+ * packets. The device driver should place incoming data into this
+ * buffer. When sending data, the device driver should read the link
+ * level headers and the TCP/IP headers from this buffer. The size of
+ * the link level headers is configured by the UIP_LLH_LEN define.
+ *
+ * \note The application data need not be placed in this buffer, so
+ * the device driver must read it from the place pointed to by the
+ * uip_appdata pointer as illustrated by the following example:
+ \code
+ void
+ devicedriver_send(void)
+ {
+ hwsend(&uip_buf[0], UIP_LLH_LEN);
+ if(uip_len <= UIP_LLH_LEN + UIP_TCPIP_HLEN) {
+ hwsend(&uip_buf[UIP_LLH_LEN], uip_len - UIP_LLH_LEN);
+ } else {
+ hwsend(&uip_buf[UIP_LLH_LEN], UIP_TCPIP_HLEN);
+ hwsend(uip_appdata, uip_len - UIP_TCPIP_HLEN - UIP_LLH_LEN);
+ }
+ }
+ \endcode
+*/
+#ifndef UIP_CONF_EXTERNAL_BUFFER
+CCIF extern u8_t			uip_buf[UIP_BUFSIZE + 2];
+#else
+CCIF extern unsigned char *uip_buf;
+#endif
+
+/** @} */
+
+/*---------------------------------------------------------------------------*/
+
+/* Functions that are used by the uIP application program. Opening and
+ * closing connections, sending and receiving data, etc. is all
+ * handled by the functions below.
+ */
+
+/**
+ * \defgroup uipappfunc uIP application functions
+ * @{
+ *
+ * Functions used by an application running of top of uIP.
+ */
+
+/**
+ * Start listening to the specified port.
+ *
+ * \note Since this function expects the port number in network byte
+ * order, a conversion using HTONS() or htons() is necessary.
+ *
+ \code
+ uip_listen(HTONS(80));
+ \endcode
+ *
+ * \param port A 16-bit port number in network byte order.
+ */
+void						uip_listen( u16_t port );
+
+/**
+ * Stop listening to the specified port.
+ *
+ * \note Since this function expects the port number in network byte
+ * order, a conversion using HTONS() or htons() is necessary.
+ *
+ \code
+ uip_unlisten(HTONS(80));
+ \endcode
+ *
+ * \param port A 16-bit port number in network byte order.
+ */
+void						uip_unlisten( u16_t port );
+
+/**
+ * Connect to a remote host using TCP.
+ *
+ * This function is used to start a new connection to the specified
+ * port on the specified host. It allocates a new connection identifier,
+ * sets the connection to the SYN_SENT state and sets the
+ * retransmission timer to 0. This will cause a TCP SYN segment to be
+ * sent out the next time this connection is periodically processed,
+ * which usually is done within 0.5 seconds after the call to
+ * uip_connect().
+ *
+ * \note This function is available only if support for active open
+ * has been configured by defining UIP_ACTIVE_OPEN to 1 in uipopt.h.
+ *
+ * \note Since this function requires the port number to be in network
+ * byte order, a conversion using HTONS() or htons() is necessary.
+ *
+ \code
+ uip_ipaddr_t ipaddr;
+
+ uip_ipaddr(&ipaddr, 192,168,1,2);
+ uip_connect(&ipaddr, HTONS(80));
+ \endcode
+ *
+ * \param ripaddr The IP address of the remote host.
+ *
+ * \param port A 16-bit port number in network byte order.
+ *
+ * \return A pointer to the uIP connection identifier for the new connection,
+ * or NULL if no connection could be allocated.
+ *
+ */
+struct uip_conn				*uip_connect( uip_ipaddr_t *ripaddr, u16_t port );
+
+/**
+ * \internal
+ *
+ * Check if a connection has outstanding (i.e., unacknowledged) data.
+ *
+ * \param conn A pointer to the uip_conn structure for the connection.
+ *
+ * \hideinitializer
+ */
+#define uip_outstanding( conn ) ( (conn)->len )
+
+/**
+ * Send data on the current connection.
+ *
+ * This function is used to send out a single segment of TCP
+ * data. Only applications that have been invoked by uIP for event
+ * processing can send data.
+ *
+ * The amount of data that actually is sent out after a call to this
+ * function is determined by the maximum amount of data TCP allows. uIP
+ * will automatically crop the data so that only the appropriate
+ * amount of data is sent. The function uip_mss() can be used to query
+ * uIP for the amount of data that actually will be sent.
+ *
+ * \note This function does not guarantee that the sent data will
+ * arrive at the destination. If the data is lost in the network, the
+ * application will be invoked with the uip_rexmit() event being
+ * set. The application will then have to resend the data using this
+ * function.
+ *
+ * \param data A pointer to the data which is to be sent.
+ *
+ * \param len The maximum amount of data bytes to be sent.
+ *
+ * \hideinitializer
+ */
+CCIF void	uip_send( const void *data, int len );
+
+/**
+ * The length of any incoming data that is currently available (if available)
+ * in the uip_appdata buffer.
+ *
+ * The test function uip_data() must first be used to check if there
+ * is any data available at all.
+ *
+ * \hideinitializer
+ */
+
+/*void uip_datalen(void);*/
+#define uip_datalen()	uip_len
+
+/**
+ * The length of any out-of-band data (urgent data) that has arrived
+ * on the connection.
+ *
+ * \note The configuration parameter UIP_URGDATA must be set for this
+ * function to be enabled.
+ *
+ * \hideinitializer
+ */
+#define uip_urgdatalen()	uip_urglen
+
+/**
+ * Close the current connection.
+ *
+ * This function will close the current connection in a nice way.
+ *
+ * \hideinitializer
+ */
+#define uip_close() ( uip_flags = UIP_CLOSE )
+
+/**
+ * Abort the current connection.
+ *
+ * This function will abort (reset) the current connection, and is
+ * usually used when an error has occurred that prevents using the
+ * uip_close() function.
+ *
+ * \hideinitializer
+ */
+#define uip_abort() ( uip_flags = UIP_ABORT )
+
+/**
+ * Tell the sending host to stop sending data.
+ *
+ * This function will close our receiver's window so that we stop
+ * receiving data for the current connection.
+ *
+ * \hideinitializer
+ */
+#define uip_stop()	( uip_conn->tcpstateflags |= UIP_STOPPED )
+
+/**
+ * Find out if the current connection has been previously stopped with
+ * uip_stop().
+ *
+ * \hideinitializer
+ */
+#define uip_stopped( conn ) ( (conn)->tcpstateflags & UIP_STOPPED )
+
+/**
+ * Restart the current connection, if is has previously been stopped
+ * with uip_stop().
+ *
+ * This function will open the receiver's window again so that we
+ * start receiving data for the current connection.
+ *
+ * \hideinitializer
+ */
+#define uip_restart()							 \
+	do											 \
+	{											 \
+		uip_flags |= UIP_NEWDATA;				 \
+		uip_conn->tcpstateflags &= ~UIP_STOPPED; \
+	} while( 0 )
+
+	/* uIP tests that can be made to determine in what state the current
+   connection is, and what the application function should do. */
+
+/**
+ * Is the current connection a UDP connection?
+ *
+ * This function checks whether the current connection is a UDP connection.
+ *
+ * \hideinitializer
+ *
+ */
+#define uip_udpconnection() ( uip_conn == NULL )
+
+/**
+ * Is new incoming data available?
+ *
+ * Will reduce to non-zero if there is new data for the application
+ * present at the uip_appdata pointer. The size of the data is
+ * available through the uip_len variable.
+ *
+ * \hideinitializer
+ */
+#define uip_newdata()	( uip_flags & UIP_NEWDATA )
+
+/**
+ * Has previously sent data been acknowledged?
+ *
+ * Will reduce to non-zero if the previously sent data has been
+ * acknowledged by the remote host. This means that the application
+ * can send new data.
+ *
+ * \hideinitializer
+ */
+#define uip_acked() ( uip_flags & UIP_ACKDATA )
+
+/**
+ * Has the connection just been connected?
+ *
+ * Reduces to non-zero if the current connection has been connected to
+ * a remote host. This will happen both if the connection has been
+ * actively opened (with uip_connect()) or passively opened (with
+ * uip_listen()).
+ *
+ * \hideinitializer
+ */
+#define uip_connected() ( uip_flags & UIP_CONNECTED )
+
+/**
+ * Has the connection been closed by the other end?
+ *
+ * Is non-zero if the connection has been closed by the remote
+ * host. The application may then do the necessary clean-ups.
+ *
+ * \hideinitializer
+ */
+#define uip_closed()	( uip_flags & UIP_CLOSE )
+
+/**
+ * Has the connection been aborted by the other end?
+ *
+ * Non-zero if the current connection has been aborted (reset) by the
+ * remote host.
+ *
+ * \hideinitializer
+ */
+#define uip_aborted()	( uip_flags & UIP_ABORT )
+
+/**
+ * Has the connection timed out?
+ *
+ * Non-zero if the current connection has been aborted due to too many
+ * retransmissions.
+ *
+ * \hideinitializer
+ */
+#define uip_timedout()	( uip_flags & UIP_TIMEDOUT )
+
+/**
+ * Do we need to retransmit previously data?
+ *
+ * Reduces to non-zero if the previously sent data has been lost in
+ * the network, and the application should retransmit it. The
+ * application should send the exact same data as it did the last
+ * time, using the uip_send() function.
+ *
+ * \hideinitializer
+ */
+#define uip_rexmit()	( uip_flags & UIP_REXMIT )
+
+/**
+ * Is the connection being polled by uIP?
+ *
+ * Is non-zero if the reason the application is invoked is that the
+ * current connection has been idle for a while and should be
+ * polled.
+ *
+ * The polling event can be used for sending data without having to
+ * wait for the remote host to send data.
+ *
+ * \hideinitializer
+ */
+#define uip_poll()	( uip_flags & UIP_POLL )
+
+/**
+ * Get the initial maximum segment size (MSS) of the current
+ * connection.
+ *
+ * \hideinitializer
+ */
+#define uip_initialmss()	( uip_conn->initialmss )
+
+/**
+ * Get the current maximum segment size that can be sent on the current
+ * connection.
+ *
+ * The current maximum segment size that can be sent on the
+ * connection is computed from the receiver's window and the MSS of
+ * the connection (which also is available by calling
+ * uip_initialmss()).
+ *
+ * \hideinitializer
+ */
+#define uip_mss()	( uip_conn->mss )
+	/**
+ * Set up a new UDP connection.
+ *
+ * This function sets up a new UDP connection. The function will
+ * automatically allocate an unused local port for the new
+ * connection. However, another port can be chosen by using the
+ * uip_udp_bind() call, after the uip_udp_new() function has been
+ * called.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t addr;
+ struct uip_udp_conn *c;
+
+ uip_ipaddr(&addr, 192,168,2,1);
+ c = uip_udp_new(&addr, HTONS(12345));
+ if(c != NULL) {
+ uip_udp_bind(c, HTONS(12344));
+ }
+ \endcode
+ * \param ripaddr The IP address of the remote host.
+ *
+ * \param rport The remote port number in network byte order.
+ *
+ * \return The uip_udp_conn structure for the new connection or NULL
+ * if no connection could be allocated.
+ */
+	struct uip_udp_conn *uip_udp_new( const uip_ipaddr_t *ripaddr, u16_t rport );
+
+/**
+ * Removed a UDP connection.
+ *
+ * \param conn A pointer to the uip_udp_conn structure for the connection.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_remove( conn )	( conn )->lport = 0
+
+/**
+ * Bind a UDP connection to a local port.
+ *
+ * \param conn A pointer to the uip_udp_conn structure for the
+ * connection.
+ *
+ * \param port The local port number, in network byte order.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_bind( conn, port )	( conn )->lport = port
+
+/**
+ * Send a UDP datagram of length len on the current connection.
+ *
+ * This function can only be called in response to a UDP event (poll
+ * or newdata). The data must be present in the uip_buf buffer, at the
+ * place pointed to by the uip_appdata pointer.
+ *
+ * \param len The length of the data in the uip_buf buffer.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_send( len ) uip_send( ( char * ) uip_appdata, len )
+
+/** @} */
+
+/* uIP convenience and converting functions. */
+
+/**
+ * \defgroup uipconvfunc uIP conversion functions
+ * @{
+ *
+ * These functions can be used for converting between different data
+ * formats used by uIP.
+ */
+
+/**
+ * Convert an IP address to four bytes separated by commas.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr;
+ printf("ipaddr=%d.%d.%d.%d\n", uip_ipaddr_to_quad(&ipaddr));
+ \endcode
+ *
+ * \param a A pointer to a uip_ipaddr_t.
+ * \hideinitializer
+ */
+#define uip_ipaddr_to_quad( a ) ( a )->u8[0], ( a )->u8[1], ( a )->u8[2], ( a )->u8[3]
+
+/**
+ * Construct an IP address from four bytes.
+ *
+ * This function constructs an IP address of the type that uIP handles
+ * internally from four bytes. The function is handy for specifying IP
+ * addresses to use with e.g. the uip_connect() function.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr;
+ struct uip_conn *c;
+
+ uip_ipaddr(&ipaddr, 192,168,1,2);
+ c = uip_connect(&ipaddr, HTONS(80));
+ \endcode
+ *
+ * \param addr A pointer to a uip_ipaddr_t variable that will be
+ * filled in with the IP address.
+ *
+ * \param addr0 The first octet of the IP address.
+ * \param addr1 The second octet of the IP address.
+ * \param addr2 The third octet of the IP address.
+ * \param addr3 The forth octet of the IP address.
+ *
+ * \hideinitializer
+ */
+#define uip_ipaddr( addr, addr0, addr1, addr2, addr3 ) \
+	do												   \
+	{												   \
+		( addr )->u8[0] = addr0;					   \
+		( addr )->u8[1] = addr1;					   \
+		( addr )->u8[2] = addr2;					   \
+		( addr )->u8[3] = addr3;					   \
+	} while( 0 )
+
+/**
+ * Construct an IPv6 address from eight 16-bit words.
+ *
+ * This function constructs an IPv6 address.
+ *
+ * \hideinitializer
+ */
+#define uip_ip6addr( addr, addr0, addr1, addr2, addr3, addr4, addr5, addr6, addr7 ) \
+	do																				\
+	{																				\
+		( addr )->u16[0] = HTONS( addr0 );											\
+		( addr )->u16[1] = HTONS( addr1 );											\
+		( addr )->u16[2] = HTONS( addr2 );											\
+		( addr )->u16[3] = HTONS( addr3 );											\
+		( addr )->u16[4] = HTONS( addr4 );											\
+		( addr )->u16[5] = HTONS( addr5 );											\
+		( addr )->u16[6] = HTONS( addr6 );											\
+		( addr )->u16[7] = HTONS( addr7 );											\
+	} while( 0 )	/**
+ * Construct an IPv6 address from eight 8-bit words.
+ *
+ * This function constructs an IPv6 address.
+ *
+ * \hideinitializer
+ */
+#define uip_ip6addr_u8	( addr, addr0, addr1, addr2, addr3, addr4, addr5, addr6, addr7, addr8, addr9, addr10, addr11, addr12, addr13, addr14, \
+						 addr15 ) do																										  \
+	{\
+		( addr )->u8[0] = addr0;																											  \
+		( addr )->u8[1] = addr1;																											  \
+		( addr )->u8[2] = addr2;																											  \
+		( addr )->u8[3] = addr3;																											  \
+		( addr )->u8[4] = addr4;																											  \
+		( addr )->u8[5] = addr5;																											  \
+		( addr )->u8[6] = addr6;																											  \
+		( addr )->u8[7] = addr7;																											  \
+		( addr )->u8[8] = addr8;																											  \
+		( addr )->u8[9] = addr9;																											  \
+		( addr )->u8[10] = addr10;																											  \
+		( addr )->u8[11] = addr11;																											  \
+		( addr )->u8[12] = addr12;																											  \
+		( addr )->u8[13] = addr13;																											  \
+		( addr )->u8[14] = addr14;																											  \
+		( addr )->u8[15] = addr15;																											  \
+	} while( 0 )
+			/**
+ * Copy an IP address to another IP address.
+ *
+ * Copies an IP address from one place to another.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr1, ipaddr2;
+
+ uip_ipaddr(&ipaddr1, 192,16,1,2);
+ uip_ipaddr_copy(&ipaddr2, &ipaddr1);
+ \endcode
+ *
+ * \param dest The destination for the copy.
+ * \param src The source from where to copy.
+ *
+ * \hideinitializer
+ */
+#ifndef uip_ipaddr_copy
+	#define uip_ipaddr_copy( dest, src ) 	\
+	do										\
+	{										\
+		(dest)->u8[0] = (src)->u8[0];		\
+		(dest)->u8[1] = (src)->u8[1];		\
+		(dest)->u8[2] = (src)->u8[2];		\
+		(dest)->u8[3] = (src)->u8[3];		\
+	} while( 0 )	
+#endif
+
+			/**
+ * Compare two IP addresses
+ *
+ * Compares two IP addresses.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr1, ipaddr2;
+
+ uip_ipaddr(&ipaddr1, 192,16,1,2);
+ if(uip_ipaddr_cmp(&ipaddr2, &ipaddr1)) {
+ printf("They are the same");
+ }
+ \endcode
+ *
+ * \param addr1 The first IP address.
+ * \param addr2 The second IP address.
+ *
+ * \hideinitializer
+ */
+#if !UIP_CONF_IPV6
+#define uip_ipaddr_cmp( addr1, addr2 )	( (addr1)->u16[0] == (addr2)->u16[0] && (addr1)->u16[1] == (addr2)->u16[1] )
+#else /* !UIP_CONF_IPV6 */
+#define uip_ipaddr_cmp( addr1, addr2 )	( memcmp(addr1, addr2, sizeof(uip_ip6addr_t)) == 0 )
+#endif /* !UIP_CONF_IPV6 */
+
+			/**
+ * Compare two IP addresses with netmasks
+ *
+ * Compares two IP addresses with netmasks. The masks are used to mask
+ * out the bits that are to be compared.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr1, ipaddr2, mask;
+
+ uip_ipaddr(&mask, 255,255,255,0);
+ uip_ipaddr(&ipaddr1, 192,16,1,2);
+ uip_ipaddr(&ipaddr2, 192,16,1,3);
+ if(uip_ipaddr_maskcmp(&ipaddr1, &ipaddr2, &mask)) {
+ printf("They are the same");
+ }
+ \endcode
+ *
+ * \param addr1 The first IP address.
+ * \param addr2 The second IP address.
+ * \param mask The netmask.
+ *
+ * \hideinitializer
+ */
+#if !UIP_CONF_IPV6
+#define uip_ipaddr_maskcmp( addr1, addr2, mask )																	  \
+		(																											  \
+			(((( u16_t * ) addr1)[0] & (( u16_t * ) mask)[0]) == ((( u16_t * ) addr2)[0] & (( u16_t * ) mask)[0])) && \
+			(((( u16_t * ) addr1)[1] & (( u16_t * ) mask)[1]) == ((( u16_t * ) addr2)[1] & (( u16_t * ) mask)[1]))	  \
+		)
+#else
+#define uip_ipaddr_prefixcmp( addr1, addr2, length )	( memcmp(addr1, addr2, length >> 3) == 0 )
+#endif
+
+			/**
+ * Check if an address is a broadcast address for a network.
+ *
+ * Checks if an address is the broadcast address for a network. The
+ * network is defined by an IP address that is on the network and the
+ * network's netmask.
+ *
+ * \param addr The IP address.
+ * \param netaddr The network's IP address.
+ * \param netmask The network's netmask.
+ *
+ * \hideinitializer
+ */
+
+			/*#define uip_ipaddr_isbroadcast(addr, netaddr, netmask)
+  ((uip_ipaddr_t *)(addr)).u16 & ((uip_ipaddr_t *)(addr)).u16*/
+
+/**
+ * Mask out the network part of an IP address.
+ *
+ * Masks out the network part of an IP address, given the address and
+ * the netmask.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr1, ipaddr2, netmask;
+
+ uip_ipaddr(&ipaddr1, 192,16,1,2);
+ uip_ipaddr(&netmask, 255,255,255,0);
+ uip_ipaddr_mask(&ipaddr2, &ipaddr1, &netmask);
+ \endcode
+ *
+ * In the example above, the variable "ipaddr2" will contain the IP
+ * address 192.168.1.0.
+ *
+ * \param dest Where the result is to be placed.
+ * \param src The IP address.
+ * \param mask The netmask.
+ *
+ * \hideinitializer
+ */
+#define uip_ipaddr_mask( dest, src, mask )											\
+	do																				\
+	{																				\
+		( ( u16_t * ) dest )[0] = ( ( u16_t * ) src )[0] & ( ( u16_t * ) mask )[0]; \
+		( ( u16_t * ) dest )[1] = ( ( u16_t * ) src )[1] & ( ( u16_t * ) mask )[1]; \
+	} while( 0 )
+
+/**
+ * Pick the first octet of an IP address.
+ *
+ * Picks out the first octet of an IP address.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr;
+ u8_t octet;
+
+ uip_ipaddr(&ipaddr, 1,2,3,4);
+ octet = uip_ipaddr1(&ipaddr);
+ \endcode
+ *
+ * In the example above, the variable "octet" will contain the value 1.
+ *
+ * \hideinitializer
+ */
+#define uip_ipaddr1( addr ) ( (addr)->u8[0] )
+
+/**
+ * Pick the second octet of an IP address.
+ *
+ * Picks out the second octet of an IP address.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr;
+ u8_t octet;
+
+ uip_ipaddr(&ipaddr, 1,2,3,4);
+ octet = uip_ipaddr2(&ipaddr);
+ \endcode
+ *
+ * In the example above, the variable "octet" will contain the value 2.
+ *
+ * \hideinitializer
+ */
+#define uip_ipaddr2( addr ) ( (addr)->u8[1] )
+
+/**
+ * Pick the third octet of an IP address.
+ *
+ * Picks out the third octet of an IP address.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr;
+ u8_t octet;
+
+ uip_ipaddr(&ipaddr, 1,2,3,4);
+ octet = uip_ipaddr3(&ipaddr);
+ \endcode
+ *
+ * In the example above, the variable "octet" will contain the value 3.
+ *
+ * \hideinitializer
+ */
+#define uip_ipaddr3( addr ) ( (addr)->u8[2] )
+
+/**
+ * Pick the fourth octet of an IP address.
+ *
+ * Picks out the fourth octet of an IP address.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr;
+ u8_t octet;
+
+ uip_ipaddr(&ipaddr, 1,2,3,4);
+ octet = uip_ipaddr4(&ipaddr);
+ \endcode
+ *
+ * In the example above, the variable "octet" will contain the value 4.
+ *
+ * \hideinitializer
+ */
+#define uip_ipaddr4( addr ) ( (addr)->u8[3] )
+				/**
+ * Convert 16-bit quantity from host byte order to network byte order.
+ *
+ * This macro is primarily used for converting constants from host
+ * byte order to network byte order. For converting variables to
+ * network byte order, use the htons() function instead.
+ *
+ * \hideinitializer
+ */
+#ifndef HTONS
+#if UIP_BYTE_ORDER == UIP_BIG_ENDIAN
+#define HTONS( n )	( n )
+#define HTONL( n )	( n )
+#else /* UIP_BYTE_ORDER == UIP_BIG_ENDIAN */
+#define HTONS( n )	( u16_t ) ( (((u16_t) (n)) << 8) | (((u16_t) (n)) >> 8) )
+#define HTONL( n )	( ((u32_t) HTONS(n) << 16) | HTONS((u32_t) (n) >> 16) )
+#endif /* UIP_BYTE_ORDER == UIP_BIG_ENDIAN */
+#else
+#error "HTONS already defined!"
+#endif /* HTONS */
+
+				/**
+ * Convert 16-bit quantity from host byte order to network byte order.
+ *
+ * This function is primarily used for converting variables from host
+ * byte order to network byte order. For converting constants to
+ * network byte order, use the HTONS() macro instead.
+ */
+#ifndef htons
+	CCIF u16_t	htons( u16_t val );
+#endif /* htons */
+
+#ifndef ntohs
+	#define ntohs	htons
+#endif
+
+#ifndef htonl
+	CCIF u32_t	htonl( u32_t val );
+#endif /* htonl */
+
+#ifndef ntohl
+	#define ntohl	htonl
+#endif
+
+/** @} */
+
+/**
+ * Pointer to the application data in the packet buffer.
+ *
+ * This pointer points to the application data when the application is
+ * called. If the application wishes to send data, the application may
+ * use this space to write the data into before calling uip_send().
+ */
+CCIF extern void	*uip_appdata;
+
+#if UIP_URGDATA > 0
+
+/* u8_t *uip_urgdata:
+ *
+ * This pointer points to any urgent data that has been received. Only
+ * present if compiled with support for urgent data (UIP_URGDATA).
+ */
+extern void			*uip_urgdata;
+#endif /* UIP_URGDATA > 0 */
+
+/**
+ * \defgroup uipdrivervars Variables used in uIP device drivers
+ * @{
+ *
+ * uIP has a few global variables that are used in device drivers for
+ * uIP.
+ */
+
+/**
+ * The length of the packet in the uip_buf buffer.
+ *
+ * The global variable uip_len holds the length of the packet in the
+ * uip_buf buffer.
+ *
+ * When the network device driver calls the uIP input function,
+ * uip_len should be set to the length of the packet in the uip_buf
+ * buffer.
+ *
+ * When sending packets, the device driver should use the contents of
+ * the uip_len variable to determine the length of the outgoing
+ * packet.
+ *
+ */
+CCIF extern u16_t	uip_len;
+
+/**
+ * The length of the extension headers
+ */
+extern u8_t			uip_ext_len;
+
+/** @} */
+#if UIP_URGDATA > 0
+extern u16_t		uip_urglen, uip_surglen;
+#endif /* UIP_URGDATA > 0 */
+
+/**
+ * Representation of a uIP TCP connection.
+ *
+ * The uip_conn structure is used for identifying a connection. All
+ * but one field in the structure are to be considered read-only by an
+ * application. The only exception is the appstate field whose purpose
+ * is to let the application store application-specific state (e.g.,
+ * file pointers) for the connection. The type of this field is
+ * configured in the "uipopt.h" header file.
+ */
+struct uip_conn
+{
+	uip_ipaddr_t		ripaddr;		/**< The IP address of the remote host. */
+
+	u16_t				lport;			/**< The local TCP port, in network byte order. */
+	u16_t				rport;			/**< The local remote TCP port, in network byte
+			 order. */
+
+	u8_t				rcv_nxt[4];		/**< The sequence number that we expect to
+			 receive next. */
+	u8_t				snd_nxt[4];		/**< The sequence number that was last sent by
+                         us. */
+	u16_t				len;			/**< Length of the data that was previously sent. */
+	u16_t				mss;			/**< Current maximum segment size for the
+			 connection. */
+	u16_t				initialmss;		/**< Initial maximum segment size for the
+			 connection. */
+	u8_t				sa;				/**< Retransmission time-out calculation state
+			 variable. */
+	u8_t				sv;				/**< Retransmission time-out calculation state
+			 variable. */
+	u8_t				rto;			/**< Retransmission time-out. */
+	u8_t				tcpstateflags;	/**< TCP state and flags. */
+	u8_t				timer;			/**< The retransmission timer. */
+	u8_t				nrtx;			/**< The number of retransmissions for the last
+			 segment sent. */
+
+	/** The application state. */
+	uip_tcp_appstate_t	appstate;
+};
+
+/**
+ * Pointer to the current TCP connection.
+ *
+ * The uip_conn pointer can be used to access the current TCP
+ * connection.
+ */
+CCIF extern struct uip_conn *uip_conn;
+#ifdef UIP_TCP
+
+/* The array containing all uIP connections. */
+CCIF extern struct uip_conn uip_conns[UIP_CONNS];
+#endif
+
+/**
+ * \addtogroup uiparch
+ * @{
+ */
+
+/**
+ * 4-byte array used for the 32-bit sequence number calculations.
+ */
+extern u8_t					uip_acc32[4];
+
+/** @} */
+#if UIP_UDP == 1
+/**
+ * Representation of a uIP UDP connection.
+ */
+struct uip_udp_conn
+{
+	uip_ipaddr_t		ripaddr;	/**< The IP address of the remote peer. */
+	u16_t				lport;		/**< The local port number in network byte order. */
+	u16_t				rport;		/**< The remote port number in network byte order. */
+	u8_t				ttl;		/**< Default time-to-live. */
+
+	/** The application state. */
+	uip_udp_appstate_t	appstate;
+};
+
+/**
+ * The current UDP connection.
+ */
+extern struct uip_udp_conn	*uip_udp_conn;
+extern struct uip_udp_conn	uip_udp_conns[UIP_UDP_CONNS];
+#endif /* UIP_UDP */
+
+struct uip_router
+{
+	int ( *activate ) ( void );
+	int ( *deactivate ) ( void );
+	uip_ipaddr_t * ( *lookup ) ( uip_ipaddr_t *destipaddr, uip_ipaddr_t *nexthop );
+};
+
+#ifdef UIP_CONF_ROUTER
+extern const struct uip_router	*uip_router;
+
+/**
+ * uIP routing driver registration function.
+ */
+void							uip_router_register( const struct uip_router *router );
+#endif /*UIP_CONF_ROUTER*/
+
+#ifdef UIP_CONF_ICMP6
+struct uip_icmp6_conn
+{
+	uip_icmp6_appstate_t	appstate;
+};
+extern struct uip_icmp6_conn	uip_icmp6_conns;
+#endif /*UIP_CONF_ICMP6*/
+
+/**
+ * The uIP TCP/IP statistics.
+ *
+ * This is the variable in which the uIP TCP/IP statistics are gathered.
+ */
+#if UIP_STATISTICS == 1
+extern struct uip_stats			uip_stat;
+#define UIP_STAT( s )	s
+#else
+#define UIP_STAT( s )
+#endif /* UIP_STATISTICS == 1 */
+
+/**
+ * The structure holding the TCP/IP statistics that are gathered if
+ * UIP_STATISTICS is set to 1.
+ *
+ */
+struct uip_stats
+{
+	struct
+	{
+		uip_stats_t recv;		/**< Number of received packets at the IP
+			     layer. */
+		uip_stats_t sent;		/**< Number of sent packets at the IP
+			     layer. */
+		uip_stats_t forwarded;	/**< Number of forwarded packets at the IP
+			     layer. */
+		uip_stats_t drop;		/**< Number of dropped packets at the IP
+			     layer. */
+		uip_stats_t vhlerr;		/**< Number of packets dropped due to wrong
+			     IP version or header length. */
+		uip_stats_t hblenerr;	/**< Number of packets dropped due to wrong
+			     IP length, high byte. */
+		uip_stats_t lblenerr;	/**< Number of packets dropped due to wrong
+			     IP length, low byte. */
+		uip_stats_t fragerr;	/**< Number of packets dropped since they
+			     were IP fragments. */
+		uip_stats_t chkerr;		/**< Number of packets dropped due to IP
+			     checksum errors. */
+		uip_stats_t protoerr;	/**< Number of packets dropped since they
+			     were neither ICMP, UDP nor TCP. */
+	} ip;						/**< IP statistics. */
+	struct
+	{
+		uip_stats_t recv;		/**< Number of received ICMP packets. */
+		uip_stats_t sent;		/**< Number of sent ICMP packets. */
+		uip_stats_t drop;		/**< Number of dropped ICMP packets. */
+		uip_stats_t typeerr;	/**< Number of ICMP packets with a wrong
+			     type. */
+		uip_stats_t chkerr;		/**< Number of ICMP packets with a bad
+			     checksum. */
+	} icmp;						/**< ICMP statistics. */
+#ifdef UIP_TCP
+	struct
+	{
+		uip_stats_t recv;		/**< Number of recived TCP segments. */
+		uip_stats_t sent;		/**< Number of sent TCP segments. */
+		uip_stats_t drop;		/**< Number of dropped TCP segments. */
+		uip_stats_t chkerr;		/**< Number of TCP segments with a bad
+			     checksum. */
+		uip_stats_t ackerr;		/**< Number of TCP segments with a bad ACK
+			     number. */
+		uip_stats_t rst;		/**< Number of recevied TCP RST (reset) segments. */
+		uip_stats_t rexmit;		/**< Number of retransmitted TCP segments. */
+		uip_stats_t syndrop;	/**< Number of dropped SYNs due to too few
+			     connections was avaliable. */
+		uip_stats_t synrst;		/**< Number of SYNs for closed ports,
+			     triggering a RST. */
+	} tcp;						/**< TCP statistics. */
+#endif
+#ifdef UIP_UDP
+	struct
+	{
+		uip_stats_t drop;		/**< Number of dropped UDP segments. */
+		uip_stats_t recv;		/**< Number of recived UDP segments. */
+		uip_stats_t sent;		/**< Number of sent UDP segments. */
+		uip_stats_t chkerr;		/**< Number of UDP segments with a bad
+			     checksum. */
+	} udp;						/**< UDP statistics. */
+#endif /* UIP_UDP */
+#if UIP_CONF_IPV6 != 0
+	struct
+	{
+		uip_stats_t drop;		/**< Number of dropped ND6 packets. */
+		uip_stats_t recv;		/**< Number of recived ND6 packets */
+		uip_stats_t sent;		/**< Number of sent ND6 packets */
+	} nd6;
+#endif /*UIP_CONF_IPV6*/
+};
+
+/*---------------------------------------------------------------------------*/
+
+/* All the stuff below this point is internal to uIP and should not be
+ * used directly by an application or by a device driver.
+ */
+
+/*---------------------------------------------------------------------------*/
+
+/* u8_t uip_flags:
+ *
+ * When the application is called, uip_flags will contain the flags
+ * that are defined in this file. Please read below for more
+ * information.
+ */
+CCIF extern u8_t	uip_flags;
+
+/* The following flags may be set in the global variable uip_flags
+   before calling the application callback. The UIP_ACKDATA,
+   UIP_NEWDATA, and UIP_CLOSE flags may both be set at the same time,
+   whereas the others are mutually exclusive. Note that these flags
+   should *NOT* be accessed directly, but only through the uIP
+   functions/macros. */
+#define UIP_ACKDATA		1		/* Signifies that the outstanding data was
+			       acked and the application should send
+			       out new data instead of retransmitting
+			       the last data. */
+#define UIP_NEWDATA		2		/* Flags the fact that the peer has sent
+			       us new data. */
+#define UIP_REXMIT		4		/* Tells the application to retransmit the
+			       data that was last sent. */
+#define UIP_POLL		8		/* Used for polling the application, to
+			       check if the application has data that
+			       it wants to send. */
+#define UIP_CLOSE		16		/* The remote host has closed the
+			       connection, thus the connection has
+			       gone away. Or the application signals
+			       that it wants to close the
+			       connection. */
+#define UIP_ABORT		32		/* The remote host has aborted the
+			       connection, thus the connection has
+			       gone away. Or the application signals
+			       that it wants to abort the
+			       connection. */
+#define UIP_CONNECTED	64		/* We have got a connection from a remote
+                               host and have set up a new connection
+                               for it, or an active connection has
+                               been successfully established. */
+
+#define UIP_TIMEDOUT	128		/* The connection has been aborted due to
+			       too many retransmissions. */
+
+/**
+ * \brief process the options within a hop by hop or destination option header
+ * \retval 0: nothing to send,
+ * \retval 1: drop pkt
+ * \retval 2: ICMP error message to send
+*/
+
+/*static u8_t
+uip_ext_hdr_options_process(); */
+
+/* uip_process(flag):
+ *
+ * The actual uIP function which does all the work.
+ */
+void	uip_process( u8_t flag );
+
+/* The following flags are passed as an argument to the uip_process()
+   function. They are used to distinguish between the two cases where
+   uip_process() is called. It can be called either because we have
+   incoming data that should be processed, or because the periodic
+   timer has fired. These values are never used directly, but only in
+   the macros defined in this file. */
+#define UIP_DATA			1	/* Tells uIP that there is incoming
+				   data in the uip_buf buffer. The
+				   length of the data is stored in the
+				   global variable uip_len. */
+#define UIP_TIMER			2	/* Tells uIP that the periodic timer
+				   has fired. */
+#define UIP_POLL_REQUEST	3	/* Tells uIP that a connection should
+				   be polled. */
+#define UIP_UDP_SEND_CONN	4	/* Tells uIP that a UDP datagram
+				   should be constructed in the
+				   uip_buf buffer. */
+#ifdef UIP_UDP
+#define UIP_UDP_TIMER	5
+#endif /* UIP_UDP */
+
+/* The TCP states used in the uip_conn->tcpstateflags. */
+#define UIP_CLOSED		0
+#define UIP_SYN_RCVD	1
+#define UIP_SYN_SENT	2
+#define UIP_ESTABLISHED 3
+#define UIP_FIN_WAIT_1	4
+#define UIP_FIN_WAIT_2	5
+#define UIP_CLOSING		6
+#define UIP_TIME_WAIT	7
+#define UIP_LAST_ACK	8
+#define UIP_TS_MASK		15
+
+#define UIP_STOPPED		16
+
+/* The TCP and IP headers. */
+#include "net/pack_struct_start.h"
+struct uip_tcpip_hdr
+{
+#if UIP_CONF_IPV6 != 0
+	/* IPv6 header. */
+	u8_t			vtc, tcflow;
+	u16_t			flow;
+	u8_t			len[2];
+	u8_t			proto, ttl;
+	uip_ip6addr_t	srcipaddr, destipaddr;
+#else /* UIP_CONF_IPV6 */
+	/* IPv4 header. */
+	u8_t			vhl, tos, len[2], ipid[2], ipoffset[2], ttl, proto;
+	u16_t			ipchksum;
+	uip_ipaddr_t	srcipaddr, destipaddr;
+#endif /* UIP_CONF_IPV6 */
+
+	/* TCP header. */
+	u16_t			srcport, destport;
+	u8_t			seqno[4], ackno[4], tcpoffset, flags, wnd[2];
+	u16_t			tcpchksum;
+	u8_t			urgp[2];
+	u8_t			optdata[4];
+}
+#include "net/pack_struct_end.h"
+
+/* The ICMP and IP headers. */
+#include "net/pack_struct_start.h"
+struct uip_icmpip_hdr
+{
+#if UIP_CONF_IPV6 != 0
+	/* IPv6 header. */
+	u8_t			vtc, tcf;
+	u16_t			flow;
+	u8_t			len[2];
+	u8_t			proto, ttl;
+	uip_ip6addr_t	srcipaddr, destipaddr;
+#else /* UIP_CONF_IPV6 */
+	/* IPv4 header. */
+	u8_t			vhl, tos, len[2], ipid[2], ipoffset[2], ttl, proto;
+	u16_t			ipchksum;
+	uip_ipaddr_t	srcipaddr, destipaddr;
+#endif /* UIP_CONF_IPV6 */
+
+	/* ICMP header. */
+	u8_t			type, icode;
+	u16_t			icmpchksum;
+#if !UIP_CONF_IPV6
+	u16_t			id, seqno;
+	u8_t			payload[1];
+#endif /* !UIP_CONF_IPV6 */
+}
+
+#include "net/pack_struct_end.h"
+
+/* The UDP and IP headers. */
+#include "net/pack_struct_start.h"
+struct uip_udpip_hdr
+{
+#if UIP_CONF_IPV6 != 0
+	/* IPv6 header. */
+	u8_t			vtc, tcf;
+	u16_t			flow;
+	u8_t			len[2];
+	u8_t			proto, ttl;
+	uip_ip6addr_t	srcipaddr, destipaddr;
+#else /* UIP_CONF_IPV6 */
+	/* IP header. */
+	u8_t			vhl, tos, len[2], ipid[2], ipoffset[2], ttl, proto;
+	u16_t			ipchksum;
+	uip_ipaddr_t	srcipaddr, destipaddr;
+#endif /* UIP_CONF_IPV6 */
+
+	/* UDP header. */
+	u16_t			srcport, destport;
+	u16_t			udplen;
+	u16_t			udpchksum;
+}
+
+#include "net/pack_struct_end.h"
+
+/*
+ * In IPv6 the length of the L3 headers before the transport header is
+ * not fixed, due to the possibility to include extension option headers
+ * after the IP header. hence we split here L3 and L4 headers
+ */
+
+/* The IP header */
+struct uip_ip_hdr
+{
+#if UIP_CONF_IPV6 != 0
+	/* IPV6 header */
+	u8_t			vtc;
+	u8_t			tcflow;
+	u16_t			flow;
+	u8_t			len[2];
+	u8_t			proto, ttl;
+	uip_ip6addr_t	srcipaddr, destipaddr;
+#else /* UIP_CONF_IPV6 */
+	/* IPV4 header */
+	u8_t			vhl, tos, len[2], ipid[2], ipoffset[2], ttl, proto;
+	u16_t			ipchksum;
+	uip_ipaddr_t	srcipaddr, destipaddr;
+#endif /* UIP_CONF_IPV6 */
+};
+
+/*
+ * IPv6 extension option headers: we are able to process
+ * the 4 extension headers defined in RFC2460 (IPv6):
+ * - Hop by hop option header, destination option header:
+ *   These two are not used by any core IPv6 protocol, hence
+ *   we just read them and go to the next. They convey options,
+ *   the options defined in RFC2460 are Pad1 and PadN, which do
+ *   some padding, and that we do not need to read (the length
+ *   field in the header is enough)
+ * - Routing header: this one is most notably used by MIPv6,
+ *   which we do not implement, hence we just read it and go
+ *   to the next
+ * - Fragmentation header: we read this header and are able to
+ *   reassemble packets
+ *
+ * We do not offer any means to send packets with extension headers
+ *
+ * We do not implement Authentication and ESP headers, which are
+ * used in IPSec and defined in RFC4302,4303,4305,4385
+ */
+
+/* common header part */
+struct uip_ext_hdr
+{
+	u8_t	next;
+	u8_t	len;
+};
+
+/* Hop by Hop option header */
+struct uip_hbho_hdr
+{
+	u8_t	next;
+	u8_t	len;
+};
+
+/* destination option header */
+struct uip_desto_hdr
+{
+	u8_t	next;
+	u8_t	len;
+};
+
+/* We do not define structures for PAD1 and PADN options */
+
+/*
+ * routing header
+ * the routing header as 4 common bytes, then routing header type
+ * specific data there are several types of routing header. Type 0 was
+ * deprecated as per RFC5095 most notable other type is 2, used in
+ * RFC3775 (MIPv6) here we do not implement MIPv6, so we just need to
+ * parse the 4 first bytes
+ */
+struct uip_routing_hdr
+{
+	u8_t	next;
+	u8_t	len;
+	u8_t	routing_type;
+	u8_t	seg_left;
+};
+
+/* fragmentation header */
+struct uip_frag_hdr
+{
+	u8_t	next;
+	u8_t	res;
+	u16_t	offsetresmore;
+	u32_t	id;
+};
+
+/*
+ * an option within the destination or hop by hop option headers
+ * it contains type an length, which is true for all options but PAD1
+ */
+struct uip_ext_hdr_opt
+{
+	u8_t	type;
+	u8_t	len;
+};
+
+/* PADN option */
+struct uip_ext_hdr_opt_padn
+{
+	u8_t	opt_type;
+	u8_t	opt_len;
+};
+
+/* TCP header */
+struct uip_tcp_hdr
+{
+	u16_t	srcport;
+	u16_t	destport;
+	u8_t	seqno[4];
+	u8_t	ackno[4];
+	u8_t	tcpoffset;
+	u8_t	flags;
+	u8_t	wnd[2];
+	u16_t	tcpchksum;
+	u8_t	urgp[2];
+	u8_t	optdata[4];
+};
+
+/* The ICMP headers. */
+struct uip_icmp_hdr
+{
+	u8_t	type, icode;
+	u16_t	icmpchksum;
+#if !UIP_CONF_IPV6
+	u16_t	id, seqno;
+#endif /* !UIP_CONF_IPV6 */
+};
+
+/* The UDP headers. */
+struct uip_udp_hdr
+{
+	u16_t	srcport;
+	u16_t	destport;
+	u16_t	udplen;
+	u16_t	udpchksum;
+};
+
+/**
+ * The buffer size available for user data in the \ref uip_buf buffer.
+ *
+ * This macro holds the available size for user data in the \ref
+ * uip_buf buffer. The macro is intended to be used for checking
+ * bounds of available user data.
+ *
+ * Example:
+ \code
+ snprintf(uip_appdata, UIP_APPDATA_SIZE, "%u\n", i);
+ \endcode
+ *
+ * \hideinitializer
+ */
+#define UIP_APPDATA_SIZE	( UIP_BUFSIZE - UIP_LLH_LEN - UIP_TCPIP_HLEN )
+#define UIP_APPDATA_PTR		( void * ) &uip_buf[UIP_LLH_LEN + UIP_TCPIP_HLEN]
+
+#define UIP_PROTO_ICMP		1
+#define UIP_PROTO_TCP		6
+#define UIP_PROTO_UDP		17
+#define UIP_PROTO_ICMP6		58
+
+#if UIP_CONF_IPV6 != 0
+
+/** @{ */
+
+/** \brief  extension headers types */
+#define UIP_PROTO_HBHO		0
+#define UIP_PROTO_DESTO		60
+#define UIP_PROTO_ROUTING	43
+#define UIP_PROTO_FRAG		44
+#define UIP_PROTO_NONE		59
+
+/** @} */
+
+/** @{ */
+
+/** \brief  Destination and Hop By Hop extension headers option types */
+#define UIP_EXT_HDR_OPT_PAD1	0
+#define UIP_EXT_HDR_OPT_PADN	1
+
+/** @} */
+
+/** @{ */
+
+/**
+ * \brief Bitmaps for extension header processing
+ *
+ * When processing extension headers, we should record somehow which one we
+ * see, because you cannot have twice the same header, except for destination
+ * We store all this in one u8_t bitmap one bit for each header expected. The
+ * order in the bitmap is the order recommended in RFC2460
+ */
+#define UIP_EXT_HDR_BITMAP_HBHO		0x01
+#define UIP_EXT_HDR_BITMAP_DESTO1	0x02
+#define UIP_EXT_HDR_BITMAP_ROUTING	0x04
+#define UIP_EXT_HDR_BITMAP_FRAG		0x08
+#define UIP_EXT_HDR_BITMAP_AH		0x10
+#define UIP_EXT_HDR_BITMAP_ESP		0x20
+#define UIP_EXT_HDR_BITMAP_DESTO2	0x40
+
+/** @} */
+#endif /* UIP_CONF_IPV6 */
+
+/* Header sizes. */
+#if UIP_CONF_IPV6 != 0
+#define UIP_IPH_LEN		40
+#define UIP_FRAGH_LEN	8
+#else /* UIP_CONF_IPV6 */
+#define UIP_IPH_LEN 20		/* Size of IP header */
+#endif /* UIP_CONF_IPV6 */
+
+#define UIP_UDPH_LEN	8	/* Size of UDP header */
+#define UIP_TCPH_LEN	20	/* Size of TCP header */
+#ifdef UIP_IPH_LEN
+#define UIP_ICMPH_LEN	4	/* Size of ICMP header */
+#endif
+#define UIP_IPUDPH_LEN	( UIP_UDPH_LEN + UIP_IPH_LEN )	/* Size of IP +
+                        * UDP
+							   * header */
+#define UIP_IPTCPH_LEN	( UIP_TCPH_LEN + UIP_IPH_LEN )	/* Size of IP +
+							   * TCP
+							   * header */
+#define UIP_TCPIP_HLEN	UIP_IPTCPH_LEN
+#define UIP_IPICMPH_LEN ( UIP_IPH_LEN + UIP_ICMPH_LEN ) /* size of ICMP
+                                                         + IP header */
+#define UIP_LLIPH_LEN	( UIP_LLH_LEN + UIP_IPH_LEN )	/* size of L2
+                                                        + IP header */
+#if UIP_CONF_IPV6 != 0
+
+/**
+ * The sums below are quite used in ND. When used for uip_buf, we
+ * include link layer length when used for uip_len, we do not, hence
+ * we need values with and without LLH_LEN we do not use capital
+ * letters as these values are variable
+ */
+#define uip_l2_l3_hdr_len		( UIP_LLH_LEN + UIP_IPH_LEN + uip_ext_len )
+#define uip_l2_l3_icmp_hdr_len	( UIP_LLH_LEN + UIP_IPH_LEN + uip_ext_len + UIP_ICMPH_LEN )
+#define uip_l3_hdr_len			( UIP_IPH_LEN + uip_ext_len )
+#define uip_l3_icmp_hdr_len		( UIP_IPH_LEN + uip_ext_len + UIP_ICMPH_LEN )
+#endif /*UIP_CONF_IPV6*/
+
+#ifdef UIP_FIXEDADDR
+CCIF extern const uip_ipaddr_t	uip_hostaddr, uip_netmask, uip_draddr;
+#else /* UIP_FIXEDADDR */
+CCIF extern uip_ipaddr_t		uip_hostaddr, uip_netmask, uip_draddr;
+#endif /* UIP_FIXEDADDR */
+CCIF extern const uip_ipaddr_t	uip_broadcast_addr;
+CCIF extern const uip_ipaddr_t	uip_all_zeroes_addr;
+
+#ifdef UIP_FIXEDETHADDR
+CCIF extern const uip_lladdr_t	uip_lladdr;
+#else
+CCIF extern uip_lladdr_t		uip_lladdr;
+#endif
+#if UIP_CONF_IPV6 != 0
+
+/**
+ * \brief Is IPv6 address a the unspecified address
+ * a is of type uip_ipaddr_t
+ */
+#define uip_is_addr_unspecified( a ) \
+		(							 \
+			(((a)->u16[0]) == 0) &&	 \
+			(((a)->u16[1]) == 0) &&	 \
+			(((a)->u16[2]) == 0) &&	 \
+			(((a)->u16[3]) == 0) &&	 \
+			(((a)->u16[4]) == 0) &&	 \
+			(((a)->u16[5]) == 0) &&	 \
+			(((a)->u16[6]) == 0) &&	 \
+			(((a)->u16[7]) == 0)	 \
+		)
+
+/** \brief Is IPv6 address a the link local all-nodes multicast address */
+#define uip_is_addr_linklocal_allnodes_mcast( a ) \
+		(										  \
+			(((a)->u8[0]) == 0xff) &&			  \
+			(((a)->u8[1]) == 0x02) &&			  \
+			(((a)->u16[1]) == 0) &&				  \
+			(((a)->u16[2]) == 0) &&				  \
+			(((a)->u16[3]) == 0) &&				  \
+			(((a)->u16[4]) == 0) &&				  \
+			(((a)->u16[5]) == 0) &&				  \
+			(((a)->u16[6]) == 0) &&				  \
+			(((a)->u8[14]) == 0) &&				  \
+			(((a)->u8[15]) == 0x01)				  \
+		)
+
+/** \brief set IP address a to unspecified */
+#define uip_create_unspecified( a ) uip_ip6addr( a, 0, 0, 0, 0, 0, 0, 0, 0 )
+
+/** \brief set IP address a to the link local all-nodes multicast address */
+#define uip_create_linklocal_allnodes_mcast( a )	uip_ip6addr( a, 0xff02, 0, 0, 0, 0, 0, 0, 0x0001 )
+
+/** \brief set IP address a to the link local all-routers multicast address */
+#define uip_create_linklocal_allrouters_mcast( a )	uip_ip6addr( a, 0xff02, 0, 0, 0, 0, 0, 0, 0x0002 )
+
+/**
+ * \brief  is addr (a) a solicited node multicast address, see RFC3513
+ *  a is of type uip_ipaddr_t*
+ */
+#define uip_is_addr_solicited_node( a ) \
+		(								\
+			(((a)->u8[0]) == 0xFF) &&	\
+			(((a)->u8[1]) == 0x02) &&	\
+			(((a)->u16[1]) == 0) &&		\
+			(((a)->u16[2]) == 0) &&		\
+			(((a)->u16[3]) == 0) &&		\
+			(((a)->u16[4]) == 0) &&		\
+			(((a)->u16[5]) == 1) &&		\
+			(((a)->u8[12]) == 0xFF)		\
+		)
+
+/**
+ * \briefput in b the solicited node address corresponding to address a
+ * both a and b are of type uip_ipaddr_t*
+ * */
+#define uip_create_solicited_node( a, b ) \
+	( ((b)->u8[0]) = 0xFF );			  \
+	( ((b)->u8[1]) = 0x02 );			  \
+	( ((b)->u16[1]) = 0 );				  \
+	( ((b)->u16[2]) = 0 );				  \
+	( ((b)->u16[3]) = 0 );				  \
+	( ((b)->u16[4]) = 0 );				  \
+	( ((b)->u8[10]) = 0 );				  \
+	( ((b)->u8[11]) = 0x01 );			  \
+	( ((b)->u8[12]) = 0xFF );			  \
+	( ((b)->u8[13]) = ((a)->u8[13]) );	  \
+	( ((b)->u16[7]) = ((a)->u16[7]) )
+
+/**
+ * \brief is addr (a) a link local unicast address, see RFC3513
+ *  i.e. is (a) on prefix FE80::/10
+ *  a is of type uip_ipaddr_t*
+ */
+#define uip_is_addr_link_local( a ) ( (((a)->u8[0]) == 0xFE) && (((a)->u8[1]) == 0x80) )
+
+/**
+ * \brief was addr (a) forged based on the mac address m
+ * a type is uip_ipaddr_t
+ * m type is uiplladdr_t
+ */
+#ifdef UIP_CONF_LL_802154
+#define uip_is_addr_mac_addr_based( a, m )				 \
+		(												 \
+			(((a)->u8[8]) == (((m)->addr[0]) ^ 0x02)) && \
+			(((a)->u8[9]) == (m)->addr[1]) &&			 \
+			(((a)->u8[10]) == (m)->addr[2]) &&			 \
+			(((a)->u8[11]) == (m)->addr[3]) &&			 \
+			(((a)->u8[12]) == (m)->addr[4]) &&			 \
+			(((a)->u8[13]) == (m)->addr[5]) &&			 \
+			(((a)->u8[14]) == (m)->addr[6]) &&			 \
+			(((a)->u8[15]) == (m)->addr[7])				 \
+		)
+#else
+#define uip_is_addr_mac_addr_based( a, m )				 \
+		(												 \
+			(((a)->u8[8]) == (((m)->addr[0]) | 0x02)) && \
+			(((a)->u8[9]) == (m)->addr[1]) &&			 \
+			(((a)->u8[10]) == (m)->addr[2]) &&			 \
+			(((a)->u8[11]) == 0xff) &&					 \
+			(((a)->u8[12]) == 0xfe) &&					 \
+			(((a)->u8[13]) == (m)->addr[3]) &&			 \
+			(((a)->u8[14]) == (m)->addr[4]) &&			 \
+			(((a)->u8[15]) == (m)->addr[5])				 \
+		)
+#endif /*UIP_CONF_LL_802154*/
+
+/**
+ * \brief is address a multicast address, see RFC 3513
+ * a is of type uip_ipaddr_t*
+ * */
+#define uip_is_addr_mcast( a )	( ((a)->u8[0]) == 0xFF )
+
+/**
+ * \brief is group-id of multicast address a
+ * the all nodes group-id
+ */
+#define uip_is_mcast_group_id_all_nodes( a ) \
+		(									 \
+			(((a)->u16[1]) == 0) &&			 \
+			(((a)->u16[2]) == 0) &&			 \
+			(((a)->u16[3]) == 0) &&			 \
+			(((a)->u16[4]) == 0) &&			 \
+			(((a)->u16[5]) == 0) &&			 \
+			(((a)->u16[6]) == 0) &&			 \
+			(((a)->u8[14]) == 0) &&			 \
+			(((a)->u8[15]) == 1)			 \
+		)
+
+/**
+ * \brief is group-id of multicast address a
+ * the all routers group-id
+ */
+#define uip_is_mcast_group_id_all_routers( a ) \
+		(									   \
+			(((a)->u16[1]) == 0) &&			   \
+			(((a)->u16[2]) == 0) &&			   \
+			(((a)->u16[3]) == 0) &&			   \
+			(((a)->u16[4]) == 0) &&			   \
+			(((a)->u16[5]) == 0) &&			   \
+			(((a)->u16[6]) == 0) &&			   \
+			(((a)->u8[14]) == 0) &&			   \
+			(((a)->u8[15]) == 2)			   \
+		)
+#endif /*UIP_CONF_IPV6*/
+
+/**
+ * Calculate the Internet checksum over a buffer.
+ *
+ * The Internet checksum is the one's complement of the one's
+ * complement sum of all 16-bit words in the buffer.
+ *
+ * See RFC1071.
+ *
+ * \param buf A pointer to the buffer over which the checksum is to be
+ * computed.
+ *
+ * \param len The length of the buffer over which the checksum is to
+ * be computed.
+ *
+ * \return The Internet checksum of the buffer.
+ */
+u16_t	uip_chksum( u16_t *buf, u16_t len );
+
+/**
+ * Calculate the IP header checksum of the packet header in uip_buf.
+ *
+ * The IP header checksum is the Internet checksum of the 20 bytes of
+ * the IP header.
+ *
+ * \return The IP header checksum of the IP header in the uip_buf
+ * buffer.
+ */
+u16_t	uip_ipchksum( void );
+
+/**
+ * Calculate the TCP checksum of the packet in uip_buf and uip_appdata.
+ *
+ * The TCP checksum is the Internet checksum of data contents of the
+ * TCP segment, and a pseudo-header as defined in RFC793.
+ *
+ * \return The TCP checksum of the TCP segment in uip_buf and pointed
+ * to by uip_appdata.
+ */
+u16_t	uip_tcpchksum( void );
+
+/**
+ * Calculate the UDP checksum of the packet in uip_buf and uip_appdata.
+ *
+ * The UDP checksum is the Internet checksum of data contents of the
+ * UDP segment, and a pseudo-header as defined in RFC768.
+ *
+ * \return The UDP checksum of the UDP segment in uip_buf and pointed
+ * to by uip_appdata.
+ */
+u16_t	uip_udpchksum( void );
+
+/**
+ * Calculate the ICMP checksum of the packet in uip_buf.
+ *
+ * \return The ICMP checksum of the ICMP packet in uip_buf
+ */
+u16_t	uip_icmp6chksum( void );
+
+/* Events that can get posted to the uIP event queue.  These are events
+originating from the Ethernet interface or from a timer. */
+#define uipETHERNET_RX_EVENT		0x01UL
+#define	uipETHERNET_TX_EVENT		0x02UL
+#define uipARP_TIMER_EVENT			0x04UL
+#define uipPERIODIC_TIMER_EVENT		0x08UL
+#define uipAPPLICATION_SEND_EVENT	0x10UL
+
+
+#endif /* __UIP_H__ */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uip_arch.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uip_arch.h
new file mode 100644
index 0000000..9ee3757
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uip_arch.h
@@ -0,0 +1,138 @@
+/**
+ * \addtogroup uip
+ * {@
+ */
+
+/**
+ * \defgroup uiparch Architecture specific uIP functions
+ * @{
+ *
+ * The functions in the architecture specific module implement the IP
+ * check sum and 32-bit additions.
+ *
+ * The IP checksum calculation is the most computationally expensive
+ * operation in the TCP/IP stack and it therefore pays off to
+ * implement this in efficient assembler. The purpose of the uip-arch
+ * module is to let the checksum functions to be implemented in
+ * architecture specific assembler.
+ *
+ */
+
+/**
+ * \file
+ * Declarations of architecture specific functions.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip_arch.h,v 1.1 2006/06/17 22:41:19 adamdunkels Exp $
+ *
+ */
+
+#ifndef __UIP_ARCH_H__
+#define __UIP_ARCH_H__
+
+#include "net/uip.h"
+
+/**
+ * Carry out a 32-bit addition.
+ *
+ * Because not all architectures for which uIP is intended has native
+ * 32-bit arithmetic, uIP uses an external C function for doing the
+ * required 32-bit additions in the TCP protocol processing. This
+ * function should add the two arguments and place the result in the
+ * global variable uip_acc32.
+ *
+ * \note The 32-bit integer pointed to by the op32 parameter and the
+ * result in the uip_acc32 variable are in network byte order (big
+ * endian).
+ *
+ * \param op32 A pointer to a 4-byte array representing a 32-bit
+ * integer in network byte order (big endian).
+ *
+ * \param op16 A 16-bit integer in host byte order.
+ */
+void uip_add32(u8_t *op32, u16_t op16);
+
+/**
+ * Calculate the Internet checksum over a buffer.
+ *
+ * The Internet checksum is the one's complement of the one's
+ * complement sum of all 16-bit words in the buffer.
+ *
+ * See RFC1071.
+ *
+ * \note This function is not called in the current version of uIP,
+ * but future versions might make use of it.
+ *
+ * \param buf A pointer to the buffer over which the checksum is to be
+ * computed.
+ *
+ * \param len The length of the buffer over which the checksum is to
+ * be computed.
+ *
+ * \return The Internet checksum of the buffer.
+ */
+u16_t uip_chksum(u16_t *buf, u16_t len);
+
+/**
+ * Calculate the IP header checksum of the packet header in uip_buf.
+ *
+ * The IP header checksum is the Internet checksum of the 20 bytes of
+ * the IP header.
+ *
+ * \return The IP header checksum of the IP header in the uip_buf
+ * buffer.
+ */
+u16_t uip_ipchksum(void);
+
+/**
+ * Calculate the TCP checksum of the packet in uip_buf and uip_appdata.
+ *
+ * The TCP checksum is the Internet checksum of data contents of the
+ * TCP segment, and a pseudo-header as defined in RFC793.
+ *
+ * \note The uip_appdata pointer that points to the packet data may
+ * point anywhere in memory, so it is not possible to simply calculate
+ * the Internet checksum of the contents of the uip_buf buffer.
+ *
+ * \return The TCP checksum of the TCP segment in uip_buf and pointed
+ * to by uip_appdata.
+ */
+u16_t uip_tcpchksum(void);
+
+u16_t uip_udpchksum(void);
+
+/** @} */
+/** @} */
+
+#endif /* __UIP_ARCH_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uip_arp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uip_arp.h
new file mode 100644
index 0000000..e04d353
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uip_arp.h
@@ -0,0 +1,149 @@
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \addtogroup uiparp
+ * @{
+ */
+
+/**
+ * \file
+ * Macros and definitions for the ARP module.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip_arp.h,v 1.2 2006/08/26 23:58:45 oliverschmidt Exp $
+ *
+ */
+#ifndef __UIP_ARP_H__
+#define __UIP_ARP_H__
+
+#include "net/uip.h"
+
+CCIF extern struct uip_eth_addr uip_ethaddr;
+
+/**
+ * The Ethernet header.
+ */
+#include "net/pack_struct_start.h"
+struct uip_eth_hdr
+{
+	struct uip_eth_addr dest;
+	struct uip_eth_addr src;
+	u16_t				type;
+}
+
+#include "net/pack_struct_end.h"
+
+#define UIP_ETHTYPE_ARP		0x0806
+#define UIP_ETHTYPE_IP		0x0800
+#define UIP_ETHTYPE_IPV6	0x86dd
+
+/* The uip_arp_init() function must be called before any of the other
+   ARP functions. */
+void	uip_arp_init( void );
+
+/* The uip_arp_ipin() function should be called whenever an IP packet
+   arrives from the Ethernet. This function refreshes the ARP table or
+   inserts a new mapping if none exists. The function assumes that an
+   IP packet with an Ethernet header is present in the uip_buf buffer
+   and that the length of the packet is in the uip_len variable. */
+
+/*void uip_arp_ipin(void);*/
+#define uip_arp_ipin()
+
+/* The uip_arp_arpin() should be called when an ARP packet is received
+   by the Ethernet driver. This function also assumes that the
+   Ethernet frame is present in the uip_buf buffer. When the
+   uip_arp_arpin() function returns, the contents of the uip_buf
+   buffer should be sent out on the Ethernet if the uip_len variable
+   is > 0. */
+void	uip_arp_arpin( void );
+
+/* The uip_arp_out() function should be called when an IP packet
+   should be sent out on the Ethernet. This function creates an
+   Ethernet header before the IP header in the uip_buf buffer. The
+   Ethernet header will have the correct Ethernet MAC destination
+   address filled in if an ARP table entry for the destination IP
+   address (or the IP address of the default router) is present. If no
+   such table entry is found, the IP packet is overwritten with an ARP
+   request and we rely on TCP to retransmit the packet that was
+   overwritten. In any case, the uip_len variable holds the length of
+   the Ethernet frame that should be transmitted. */
+void	uip_arp_out( void );
+
+/* The uip_arp_timer() function should be called every ten seconds. It
+   is responsible for flushing old entries in the ARP table. */
+void	uip_arp_timer( void );
+
+/** @} */
+
+/**
+ * \addtogroup uipconffunc
+ * @{
+ */
+
+/**
+ * Specifiy the Ethernet MAC address.
+ *
+ * The ARP code needs to know the MAC address of the Ethernet card in
+ * order to be able to respond to ARP queries and to generate working
+ * Ethernet headers.
+ *
+ * \note This macro only specifies the Ethernet MAC address to the ARP
+ * code. It cannot be used to change the MAC address of the Ethernet
+ * card.
+ *
+ * \param eaddr A pointer to a struct uip_eth_addr containing the
+ * Ethernet MAC address of the Ethernet card.
+ *
+ * \hideinitializer
+ */
+#define uip_setethaddr( eaddr )				 \
+	do										 \
+	{										 \
+		uip_ethaddr.addr[0] = eaddr.addr[0]; \
+		uip_ethaddr.addr[1] = eaddr.addr[1]; \
+		uip_ethaddr.addr[2] = eaddr.addr[2]; \
+		uip_ethaddr.addr[3] = eaddr.addr[3]; \
+		uip_ethaddr.addr[4] = eaddr.addr[4]; \
+		uip_ethaddr.addr[5] = eaddr.addr[5]; \
+	} while( 0 )
+
+	/** @} */
+#endif /* __UIP_ARP_H__ */
+
+	/** @} */
+	
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uipopt.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uipopt.h
new file mode 100644
index 0000000..ddf6a24
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/net/uipopt.h
@@ -0,0 +1,695 @@
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \defgroup uipopt Configuration options for uIP
+ * @{
+ *
+ * uIP is configured using the per-project configuration file
+ * "uipopt.h". This file contains all compile-time options for uIP and
+ * should be tweaked to match each specific project. The uIP
+ * distribution contains a documented example "uipopt.h" that can be
+ * copied and modified for each project.
+ *
+ * \note Contiki does not use the uipopt.h file to configure uIP, but
+ * uses a per-port uip-conf.h file that should be edited instead.
+ */
+
+/**
+ * \file
+ * Configuration options for uIP.
+ * \author Adam Dunkels 
+ *
+ * This file is used for tweaking various configuration options for
+ * uIP. You should make a copy of this file into one of your project's
+ * directories instead of editing this example "uipopt.h" file that
+ * comes with the uIP distribution.
+ */
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uipopt.h,v 1.11 2009/04/10 00:37:48 adamdunkels Exp $
+ *
+ */
+#ifndef __UIPOPT_H__
+#define __UIPOPT_H__
+
+#ifndef UIP_LITTLE_ENDIAN
+#define UIP_LITTLE_ENDIAN	3412
+#endif /* UIP_LITTLE_ENDIAN */
+#ifndef UIP_BIG_ENDIAN
+#define UIP_BIG_ENDIAN	1234
+#endif /* UIP_BIG_ENDIAN */
+
+#include "uip-conf.h"
+//_RB_#include "contiki-conf.h"
+
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \defgroup uipoptstaticconf Static configuration options
+ * @{
+ *
+ * These configuration options can be used for setting the IP address
+ * settings statically, but only if UIP_FIXEDADDR is set to 1. The
+ * configuration options for a specific node includes IP address,
+ * netmask and default router as well as the Ethernet address. The
+ * netmask, default router and Ethernet address are applicable only
+ * if uIP should be run over Ethernet.
+ *
+ * This options are meaningful only for the IPv4 code.
+ *
+ * All of these should be changed to suit your project.
+ */
+
+/**
+ * Determines if uIP should use a fixed IP address or not.
+ *
+ * If uIP should use a fixed IP address, the settings are set in the
+ * uipopt.h file. If not, the macros uip_sethostaddr(),
+ * uip_setdraddr() and uip_setnetmask() should be used instead.
+ *
+ * \hideinitializer
+ */
+#ifdef UIP_CONF_FIXEDADDR
+#define UIP_FIXED_ADDR UIP_CONF_FIXEDADDR
+#define UIP_FIXEDADDR	1
+#endif
+
+/**
+ * Ping IP address assignment.
+ *
+ * uIP uses a "ping" packets for setting its own IP address if this
+ * option is set. If so, uIP will start with an empty IP address and
+ * the destination IP address of the first incoming "ping" (ICMP echo)
+ * packet will be used for setting the hosts IP address.
+ *
+ * \note This works only if UIP_FIXEDADDR is 0.
+ *
+ * \hideinitializer
+ */
+#ifdef UIP_CONF_PINGADDRCONF
+#define UIP_PINGADDRCONF	UIP_CONF_PINGADDRCONF
+#else /* UIP_CONF_PINGADDRCONF */
+#define UIP_PINGADDRCONF	0
+#endif /* UIP_CONF_PINGADDRCONF */
+
+/**
+ * Specifies if the uIP ARP module should be compiled with a fixed
+ * Ethernet MAC address or not.
+ *
+ * If this configuration option is 0, the macro uip_setethaddr() can
+ * be used to specify the Ethernet address at run-time.
+ *
+ * \hideinitializer
+ */
+#define UIP_FIXEDETHADDR	0
+
+/** @} */
+
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \defgroup uipoptip IP configuration options
+ * @{
+ *
+ */
+
+/**
+ * The IP TTL (time to live) of IP packets sent by uIP.
+ *
+ * This should normally not be changed.
+ */
+#define UIP_TTL 64
+
+/**
+ * The maximum time an IP fragment should wait in the reassembly
+ * buffer before it is dropped.
+ *
+ */
+#define UIP_REASS_MAXAGE	60	/*60s*/
+
+/**
+ * Turn on support for IP packet reassembly.
+ *
+ * uIP supports reassembly of fragmented IP packets. This features
+ * requires an additional amount of RAM to hold the reassembly buffer
+ * and the reassembly code size is approximately 700 bytes.  The
+ * reassembly buffer is of the same size as the uip_buf buffer
+ * (configured by UIP_BUFSIZE).
+ *
+ * \note IP packet reassembly is not heavily tested.
+ *
+ * \hideinitializer
+ */
+#ifdef UIP_CONF_REASSEMBLY
+#define UIP_REASSEMBLY	UIP_CONF_REASSEMBLY
+#else /* UIP_CONF_REASSEMBLY */
+#define UIP_REASSEMBLY	0
+#endif /* UIP_CONF_REASSEMBLY */
+
+/** @} */
+
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \defgroup uipoptipv6 IPv6 configuration options
+ * @{
+ *
+ */
+
+/** The maximum transmission unit at the IP Layer*/
+#define UIP_LINK_MTU	1280
+
+#ifndef UIP_CONF_IPV6
+
+/** Do we use IPv6 or not (default: no) */
+#define UIP_CONF_IPV6	0
+#endif
+#ifndef UIP_CONF_IPV6_QUEUE_PKT
+
+/** Do we do per %neighbor queuing during address resolution (default: no) */
+#define UIP_CONF_IPV6_QUEUE_PKT 0
+#endif
+#ifndef UIP_CONF_IPV6_CHECKS
+
+/** Do we do IPv6 consistency checks (highly recommended, default: yes) */
+#define UIP_CONF_IPV6_CHECKS	1
+#endif
+#ifndef UIP_CONF_IPV6_REASSEMBLY
+
+/** Do we do IPv6 fragmentation (default: no) */
+#define UIP_CONF_IPV6_REASSEMBLY	0
+#endif
+#ifndef UIP_CONF_NETIF_MAX_ADDRESSES
+
+/** Default number of IPv6 addresses associated to the node's interface */
+#define UIP_CONF_NETIF_MAX_ADDRESSES	3
+#endif
+#ifndef UIP_CONF_ND6_MAX_PREFIXES
+
+/** Default number of IPv6 prefixes associated to the node's interface */
+#define UIP_CONF_ND6_MAX_PREFIXES	3
+#endif
+#ifndef UIP_CONF_ND6_MAX_NEIGHBORS
+
+/** Default number of neighbors that can be stored in the %neighbor cache */
+#define UIP_CONF_ND6_MAX_NEIGHBORS	4
+#endif
+#ifndef UIP_CONF_ND6_MAX_DEFROUTERS
+
+/** Minimum number of default routers */
+#define UIP_CONF_ND6_MAX_DEFROUTERS 2
+#endif
+
+/** @} */
+
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \defgroup uipoptudp UDP configuration options
+ * @{
+ *
+ * \note The UDP support in uIP is still not entirely complete; there
+ * is no support for sending or receiving broadcast or multicast
+ * packets, but it works well enough to support a number of vital
+ * applications such as DNS queries, though
+ */
+
+/**
+ * Toggles whether UDP support should be compiled in or not.
+ *
+ * \hideinitializer
+ */
+#ifdef UIP_CONF_UDP
+#define UIP_UDP UIP_CONF_UDP
+#else /* UIP_CONF_UDP */
+#define UIP_UDP 0
+#endif /* UIP_CONF_UDP */
+
+/**
+ * Toggles if UDP checksums should be used or not.
+ *
+ * \note Support for UDP checksums is currently not included in uIP,
+ * so this option has no function.
+ *
+ * \hideinitializer
+ */
+#ifdef UIP_CONF_UDP_CHECKSUMS
+#define UIP_UDP_CHECKSUMS	UIP_CONF_UDP_CHECKSUMS
+#else
+#define UIP_UDP_CHECKSUMS	0
+#endif
+
+/**
+ * The maximum amount of concurrent UDP connections.
+ *
+ * \hideinitializer
+ */
+#ifdef UIP_CONF_UDP_CONNS
+#define UIP_UDP_CONNS	UIP_CONF_UDP_CONNS
+#else /* UIP_CONF_UDP_CONNS */
+#define UIP_UDP_CONNS	10
+#endif /* UIP_CONF_UDP_CONNS */
+
+/**
+ * The name of the function that should be called when UDP datagrams arrive.
+ *
+ * \hideinitializer
+ */
+
+/** @} */
+
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \defgroup uipopttcp TCP configuration options
+ * @{
+ */
+
+/**
+ * Toggles whether UDP support should be compiled in or not.
+ *
+ * \hideinitializer
+ */
+#ifdef UIP_CONF_TCP
+#define UIP_TCP UIP_CONF_TCP
+#else /* UIP_CONF_UDP */
+#define UIP_TCP 1
+#endif /* UIP_CONF_UDP */
+
+/**
+ * Determines if support for opening connections from uIP should be
+ * compiled in.
+ *
+ * If the applications that are running on top of uIP for this project
+ * do not need to open outgoing TCP connections, this configuration
+ * option can be turned off to reduce the code size of uIP.
+ *
+ * \hideinitializer
+ */
+#ifndef UIP_CONF_ACTIVE_OPEN
+#define UIP_ACTIVE_OPEN 1
+#else /* UIP_CONF_ACTIVE_OPEN */
+#define UIP_ACTIVE_OPEN UIP_CONF_ACTIVE_OPEN
+#endif /* UIP_CONF_ACTIVE_OPEN */
+
+/**
+ * The maximum number of simultaneously open TCP connections.
+ *
+ * Since the TCP connections are statically allocated, turning this
+ * configuration knob down results in less RAM used. Each TCP
+ * connection requires approximately 30 bytes of memory.
+ *
+ * \hideinitializer
+ */
+#ifndef UIP_CONF_MAX_CONNECTIONS
+#define UIP_CONNS	10
+#else /* UIP_CONF_MAX_CONNECTIONS */
+#define UIP_CONNS	UIP_CONF_MAX_CONNECTIONS
+#endif /* UIP_CONF_MAX_CONNECTIONS */
+
+/**
+ * The maximum number of simultaneously listening TCP ports.
+ *
+ * Each listening TCP port requires 2 bytes of memory.
+ *
+ * \hideinitializer
+ */
+#ifndef UIP_CONF_MAX_LISTENPORTS
+#define UIP_LISTENPORTS 20
+#else /* UIP_CONF_MAX_LISTENPORTS */
+#define UIP_LISTENPORTS UIP_CONF_MAX_LISTENPORTS
+#endif /* UIP_CONF_MAX_LISTENPORTS */
+
+/**
+ * Determines if support for TCP urgent data notification should be
+ * compiled in.
+ *
+ * Urgent data (out-of-band data) is a rarely used TCP feature that
+ * very seldom would be required.
+ *
+ * \hideinitializer
+ */
+#define UIP_URGDATA 0
+
+/**
+ * The initial retransmission timeout counted in timer pulses.
+ *
+ * This should not be changed.
+ */
+#define UIP_RTO 3
+
+/**
+ * The maximum number of times a segment should be retransmitted
+ * before the connection should be aborted.
+ *
+ * This should not be changed.
+ */
+#define UIP_MAXRTX	8
+
+/**
+ * The maximum number of times a SYN segment should be retransmitted
+ * before a connection request should be deemed to have been
+ * unsuccessful.
+ *
+ * This should not need to be changed.
+ */
+#define UIP_MAXSYNRTX	5
+
+/**
+ * The TCP maximum segment size.
+ *
+ * This is should not be to set to more than
+ * UIP_BUFSIZE - UIP_LLH_LEN - UIP_TCPIP_HLEN.
+ */
+#ifdef UIP_CONF_TCP_MSS
+#define UIP_TCP_MSS UIP_CONF_TCP_MSS
+#else
+#define UIP_TCP_MSS ( UIP_BUFSIZE - UIP_LLH_LEN - UIP_TCPIP_HLEN )
+#endif
+
+/**
+ * The size of the advertised receiver's window.
+ *
+ * Should be set low (i.e., to the size of the uip_buf buffer) if the
+ * application is slow to process incoming data, or high (32768 bytes)
+ * if the application processes data quickly.
+ *
+ * \hideinitializer
+ */
+#ifndef UIP_CONF_RECEIVE_WINDOW
+#define UIP_RECEIVE_WINDOW	UIP_TCP_MSS
+#else
+#define UIP_RECEIVE_WINDOW	UIP_CONF_RECEIVE_WINDOW
+#endif
+
+/**
+ * How long a connection should stay in the TIME_WAIT state.
+ *
+ * This configuration option has no real implication, and it should be
+ * left untouched.
+ */
+#define UIP_TIME_WAIT_TIMEOUT	120
+
+/** @} */
+
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \defgroup uipoptarp ARP configuration options
+ * @{
+ */
+
+/**
+ * The size of the ARP table.
+ *
+ * This option should be set to a larger value if this uIP node will
+ * have many connections from the local network.
+ *
+ * \hideinitializer
+ */
+#ifdef UIP_CONF_ARPTAB_SIZE
+#define UIP_ARPTAB_SIZE UIP_CONF_ARPTAB_SIZE
+#else
+#define UIP_ARPTAB_SIZE 8
+#endif
+
+/**
+ * The maximum age of ARP table entries measured in 10ths of seconds.
+ *
+ * An UIP_ARP_MAXAGE of 120 corresponds to 20 minutes (BSD
+ * default).
+ */
+#define UIP_ARP_MAXAGE	120
+
+/** @} */
+
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \defgroup uipoptmac layer 2 options (for ipv6)
+ * @{
+ */
+#define UIP_DEFAULT_PREFIX_LEN	64
+
+/** @} */
+
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \defgroup uipoptsics 6lowpan options (for ipv6)
+ * @{
+ */
+
+/**
+ * Timeout for packet reassembly at the 6lowpan layer
+ * (should be < 60s)
+ */
+#ifdef SICSLOWPAN_CONF_MAXAGE
+#define SICSLOWPAN_REASS_MAXAGE SICSLOWPAN_CONF_MAXAGE
+#else
+#define SICSLOWPAN_REASS_MAXAGE 20
+#endif
+
+/**
+ * Do we compress the IP header or not (default: no)
+ */
+#ifndef SICSLOWPAN_CONF_COMPRESSION
+#define SICSLOWPAN_CONF_COMPRESSION 0
+#endif
+
+/**
+ * If we use IPHC compression, how many address contexts do we support
+ */
+#ifndef SICSLOWPAN_CONF_MAX_ADDR_CONTEXTS
+#define SICSLOWPAN_CONF_MAX_ADDR_CONTEXTS	1
+#endif
+
+/**
+ * Do we support 6lowpan fragmentation
+ */
+#ifndef SICSLOWPAN_CONF_FRAG
+#define SICSLOWPAN_CONF_FRAG	0
+#endif
+
+/** @} */
+
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \defgroup uipoptgeneral General configuration options
+ * @{
+ */
+
+/**
+ * The size of the uIP packet buffer.
+ *
+ * The uIP packet buffer should not be smaller than 60 bytes, and does
+ * not need to be larger than 1514 bytes. Lower size results in lower
+ * TCP throughput, larger size results in higher TCP throughput.
+ *
+ * \hideinitializer
+ */
+#ifndef UIP_CONF_BUFFER_SIZE
+#define UIP_BUFSIZE UIP_LINK_MTU + UIP_LLH_LEN
+#else /* UIP_CONF_BUFFER_SIZE */
+#define UIP_BUFSIZE UIP_CONF_BUFFER_SIZE
+#endif /* UIP_CONF_BUFFER_SIZE */
+
+/**
+ * Determines if statistics support should be compiled in.
+ *
+ * The statistics is useful for debugging and to show the user.
+ *
+ * \hideinitializer
+ */
+#ifndef UIP_CONF_STATISTICS
+#define UIP_STATISTICS	0
+#else /* UIP_CONF_STATISTICS */
+#define UIP_STATISTICS	UIP_CONF_STATISTICS
+#endif /* UIP_CONF_STATISTICS */
+
+/**
+ * Determines if logging of certain events should be compiled in.
+ *
+ * This is useful mostly for debugging. The function uip_log()
+ * must be implemented to suit the architecture of the project, if
+ * logging is turned on.
+ *
+ * \hideinitializer
+ */
+#ifndef UIP_CONF_LOGGING
+#define UIP_LOGGING 0
+#else /* UIP_CONF_LOGGING */
+#define UIP_LOGGING UIP_CONF_LOGGING
+#endif /* UIP_CONF_LOGGING */
+
+/**
+ * Broadcast support.
+ *
+ * This flag configures IP broadcast support. This is useful only
+ * together with UDP.
+ *
+ * \hideinitializer
+ *
+ */
+#ifndef UIP_CONF_BROADCAST
+#define UIP_BROADCAST	0
+#else /* UIP_CONF_BROADCAST */
+#define UIP_BROADCAST	UIP_CONF_BROADCAST
+#endif /* UIP_CONF_BROADCAST */
+
+/**
+ * Print out a uIP log message.
+ *
+ * This function must be implemented by the module that uses uIP, and
+ * is called by uIP whenever a log message is generated.
+ */
+void	uip_log( char *msg );
+
+/**
+ * The link level header length.
+ *
+ * This is the offset into the uip_buf where the IP header can be
+ * found. For Ethernet, this should be set to 14. For SLIP, this
+ * should be set to 0.
+ *
+ * \note we probably won't use this constant for other link layers than
+ * ethernet as they have variable header length (this is due to variable
+ * number and type of address fields and to optional security features)
+ * E.g.: 802.15.4 -> 2 + (1/2*4/8) + 0/5/6/10/14
+ *       802.11 -> 4 + (6*3/4) + 2
+ * \hideinitializer
+ */
+#ifdef UIP_CONF_LLH_LEN
+#define UIP_LLH_LEN UIP_CONF_LLH_LEN
+#else /* UIP_LLH_LEN */
+#define UIP_LLH_LEN 14
+#endif /* UIP_CONF_LLH_LEN */
+
+/** @} */
+
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \defgroup uipoptcpu CPU architecture configuration
+ * @{
+ *
+ * The CPU architecture configuration is where the endianess of the
+ * CPU on which uIP is to be run is specified. Most CPUs today are
+ * little endian, and the most notable exception are the Motorolas
+ * which are big endian. The BYTE_ORDER macro should be changed to
+ * reflect the CPU architecture on which uIP is to be run.
+ */
+
+/**
+ * The byte order of the CPU architecture on which uIP is to be run.
+ *
+ * This option can be either UIP_BIG_ENDIAN (Motorola byte order) or
+ * UIP_LITTLE_ENDIAN (Intel byte order).
+ *
+ * \hideinitializer
+ */
+#ifdef UIP_CONF_BYTE_ORDER
+#define UIP_BYTE_ORDER	UIP_CONF_BYTE_ORDER
+#else /* UIP_CONF_BYTE_ORDER */
+#define UIP_BYTE_ORDER	UIP_LITTLE_ENDIAN
+#endif /* UIP_CONF_BYTE_ORDER */
+
+/** @} */
+
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \defgroup uipoptapp Application specific configurations
+ * @{
+ *
+ * An uIP application is implemented using a single application
+ * function that is called by uIP whenever a TCP/IP event occurs. The
+ * name of this function must be registered with uIP at compile time
+ * using the UIP_APPCALL definition.
+ *
+ * uIP applications can store the application state within the
+ * uip_conn structure by specifying the type of the application
+ * structure by typedef:ing the type uip_tcp_appstate_t and uip_udp_appstate_t.
+ *
+ * The file containing the definitions must be included in the
+ * uipopt.h file.
+ *
+ * The following example illustrates how this can look.
+ \code
+
+ void httpd_appcall(void);
+ #define UIP_APPCALL     httpd_appcall
+
+ struct httpd_state {
+ u8_t state;
+ u16_t count;
+ char *dataptr;
+ char *script;
+ };
+ typedef struct httpd_state uip_tcp_appstate_t
+ \endcode
+*/
+
+/**
+ * \var #define UIP_APPCALL
+ *
+ * The name of the application function that uIP should call in
+ * response to TCP/IP events.
+ *
+ */
+
+/**
+ * \var typedef uip_tcp_appstate_t
+ *
+ * The type of the application state that is to be stored in the
+ * uip_conn structure. This usually is typedef:ed to a struct holding
+ * application state information.
+ */
+
+/**
+ * \var typedef uip_udp_appstate_t
+ *
+ * The type of the application state that is to be stored in the
+ * uip_conn structure. This usually is typedef:ed to a struct holding
+ * application state information.
+ */
+
+/** @} */
+#endif /* __UIPOPT_H__ */
+
+/** @} */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/psock.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/psock.c
new file mode 100644
index 0000000..1f224b6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/psock.c
@@ -0,0 +1,338 @@
+/*
+ * Copyright (c) 2004, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: psock.c,v 1.2 2006/06/12 08:00:30 adam Exp $
+ */
+
+#include 
+#include 
+
+#include "net/uipopt.h"
+#include "net/psock.h"
+#include "net/uip.h"
+
+#define STATE_NONE 0
+#define STATE_ACKED 1
+#define STATE_READ 2
+#define STATE_BLOCKED_NEWDATA 3
+#define STATE_BLOCKED_CLOSE 4
+#define STATE_BLOCKED_SEND 5
+#define STATE_DATA_SENT 6
+
+/*
+ * Return value of the buffering functions that indicates that a
+ * buffer was not filled by incoming data.
+ *
+ */
+#define BUF_NOT_FULL 0
+#define BUF_NOT_FOUND 0
+
+/*
+ * Return value of the buffering functions that indicates that a
+ * buffer was completely filled by incoming data.
+ *
+ */
+#define BUF_FULL 1
+
+/*
+ * Return value of the buffering functions that indicates that an
+ * end-marker byte was found.
+ *
+ */
+#define BUF_FOUND 2
+
+/*---------------------------------------------------------------------------*/
+static void
+buf_setup(struct psock_buf *buf,
+	  u8_t *bufptr, u16_t bufsize)
+{
+  buf->ptr = bufptr;
+  buf->left = bufsize;
+}
+/*---------------------------------------------------------------------------*/
+static u8_t
+buf_bufdata(struct psock_buf *buf, u16_t len,
+	    u8_t **dataptr, u16_t *datalen)
+{
+  ( void ) len;
+  if(*datalen < buf->left) {
+    memcpy(buf->ptr, *dataptr, *datalen);
+    buf->ptr += *datalen;
+    buf->left -= *datalen;
+    *dataptr += *datalen;
+    *datalen = 0;
+    return BUF_NOT_FULL;
+  } else if(*datalen == buf->left) {
+    memcpy(buf->ptr, *dataptr, *datalen);
+    buf->ptr += *datalen;
+    buf->left = 0;
+    *dataptr += *datalen;
+    *datalen = 0;
+    return BUF_FULL;
+  } else {
+    memcpy(buf->ptr, *dataptr, buf->left);
+    buf->ptr += buf->left;
+    *datalen -= buf->left;
+    *dataptr += buf->left;
+    buf->left = 0;
+    return BUF_FULL;
+  }
+}
+/*---------------------------------------------------------------------------*/
+static u8_t
+buf_bufto(register struct psock_buf *buf, u8_t endmarker,
+	  register u8_t **dataptr, register u16_t *datalen)
+{
+  u8_t c;
+  while(buf->left > 0 && *datalen > 0) {
+    c = *buf->ptr = **dataptr;
+    ++*dataptr;
+    ++buf->ptr;
+    --*datalen;
+    --buf->left;
+
+    if(c == endmarker) {
+      return BUF_FOUND;
+    }
+  }
+
+  if(*datalen == 0) {
+    return BUF_NOT_FOUND;
+  }
+
+  while(*datalen > 0) {
+    c = **dataptr;
+    --*datalen;
+    ++*dataptr;
+
+    if(c == endmarker) {
+      return BUF_FOUND | BUF_FULL;
+    }
+  }
+
+  return BUF_FULL;
+}
+/*---------------------------------------------------------------------------*/
+static char
+send_data(register struct psock *s)
+{
+  if(s->state != STATE_DATA_SENT || uip_rexmit()) {
+    if(s->sendlen > uip_mss()) {
+      uip_send(s->sendptr, uip_mss());
+    } else {
+      uip_send(s->sendptr, s->sendlen);
+    }
+    s->state = STATE_DATA_SENT;
+    return 1;
+  }
+  return 0;
+}
+/*---------------------------------------------------------------------------*/
+static char
+data_acked(register struct psock *s)
+{
+  if(s->state == STATE_DATA_SENT && uip_acked()) {
+    if(s->sendlen > uip_mss()) {
+      s->sendlen -= uip_mss();
+      s->sendptr += uip_mss();
+    } else {
+      s->sendptr += s->sendlen;
+      s->sendlen = 0;
+    }
+    s->state = STATE_ACKED;
+    return 1;
+  }
+  return 0;
+}
+/*---------------------------------------------------------------------------*/
+PT_THREAD(psock_send(register struct psock *s, const char *buf,
+		     unsigned int len))
+{
+  PT_BEGIN(&s->psockpt);
+  ( void ) PT_YIELD_FLAG;
+  /* If there is no data to send, we exit immediately. */
+  if(len == 0) {
+    PT_EXIT(&s->psockpt);
+  }
+
+  /* Save the length of and a pointer to the data that is to be
+     sent. */
+  s->sendptr = (unsigned char*)buf;
+  s->sendlen = (unsigned short)len;
+
+  s->state = STATE_NONE;
+
+  /* We loop here until all data is sent. The s->sendlen variable is
+     updated by the data_sent() function. */
+  while(s->sendlen > 0) {
+
+    /*
+     * The condition for this PT_WAIT_UNTIL is a little tricky: the
+     * protothread will wait here until all data has been acknowledged
+     * (data_acked() returns true) and until all data has been sent
+     * (send_data() returns true). The two functions data_acked() and
+     * send_data() must be called in succession to ensure that all
+     * data is sent. Therefore the & operator is used instead of the
+     * && operator, which would cause only the data_acked() function
+     * to be called when it returns false.
+     */
+    PT_WAIT_UNTIL(&s->psockpt, data_acked(s) & send_data(s));
+  }
+
+  s->state = STATE_NONE;
+
+  PT_END(&s->psockpt);
+}
+/*---------------------------------------------------------------------------*/
+PT_THREAD(psock_generator_send(register struct psock *s,
+			       unsigned short (*generate)(void *), void *arg))
+{
+  PT_BEGIN(&s->psockpt);
+  ( void ) PT_YIELD_FLAG;
+  /* Ensure that there is a generator function to call. */
+  if(generate == NULL) {
+    PT_EXIT(&s->psockpt);
+  }
+
+  /* Call the generator function to generate the data in the
+     uip_appdata buffer. */
+  s->sendlen = generate(arg);
+  s->sendptr = uip_appdata;
+
+  s->state = STATE_NONE;
+  do {
+    /* Call the generator function again if we are called to perform a
+       retransmission. */
+    if(uip_rexmit()) {
+      generate(arg);
+    }
+    /* Wait until all data is sent and acknowledged. */
+    PT_WAIT_UNTIL(&s->psockpt, data_acked(s) & send_data(s));
+  } while(s->sendlen > 0);
+
+  s->state = STATE_NONE;
+
+  PT_END(&s->psockpt);
+}
+/*---------------------------------------------------------------------------*/
+u16_t
+psock_datalen(struct psock *psock)
+{
+  return psock->bufsize - psock->buf.left;
+}
+/*---------------------------------------------------------------------------*/
+char
+psock_newdata(struct psock *s)
+{
+  if(s->readlen > 0) {
+    /* There is data in the uip_appdata buffer that has not yet been
+       read with the PSOCK_READ functions. */
+    return 1;
+  } else if(s->state == STATE_READ) {
+    /* All data in uip_appdata buffer already consumed. */
+    s->state = STATE_BLOCKED_NEWDATA;
+    return 0;
+  } else if(uip_newdata()) {
+    /* There is new data that has not been consumed. */
+    return 1;
+  } else {
+    /* There is no new data. */
+    return 0;
+  }
+}
+/*---------------------------------------------------------------------------*/
+PT_THREAD(psock_readto(register struct psock *psock, unsigned char c))
+{
+  PT_BEGIN(&psock->psockpt);
+  ( void ) PT_YIELD_FLAG;
+  buf_setup(&psock->buf, (unsigned char*)psock->bufptr, psock->bufsize);
+
+  /* XXX: Should add buf_checkmarker() before do{} loop, if
+     incoming data has been handled while waiting for a write. */
+
+  do {
+    if(psock->readlen == 0) {
+      PT_WAIT_UNTIL(&psock->psockpt, psock_newdata(psock));
+      psock->state = STATE_READ;
+      psock->readptr = (u8_t *)uip_appdata;
+      psock->readlen = uip_datalen();
+    }
+  } while((buf_bufto(&psock->buf, c,
+		     &psock->readptr,
+		     &psock->readlen) & BUF_FOUND) == 0);
+
+  if(psock_datalen(psock) == 0) {
+    psock->state = STATE_NONE;
+    PT_RESTART(&psock->psockpt);
+  }
+  PT_END(&psock->psockpt);
+}
+/*---------------------------------------------------------------------------*/
+PT_THREAD(psock_readbuf(register struct psock *psock))
+{
+  PT_BEGIN(&psock->psockpt);
+  ( void ) PT_YIELD_FLAG;
+  buf_setup(&psock->buf, (unsigned char * ) psock->bufptr, psock->bufsize);
+
+  /* XXX: Should add buf_checkmarker() before do{} loop, if
+     incoming data has been handled while waiting for a write. */
+
+  do {
+    if(psock->readlen == 0) {
+      PT_WAIT_UNTIL(&psock->psockpt, psock_newdata(psock));
+      psock->state = STATE_READ;
+      psock->readptr = (u8_t *)uip_appdata;
+      psock->readlen = uip_datalen();
+    }
+  } while(buf_bufdata(&psock->buf, psock->bufsize,
+			 &psock->readptr,
+			 &psock->readlen) != BUF_FULL);
+
+  if(psock_datalen(psock) == 0) {
+    psock->state = STATE_NONE;
+    PT_RESTART(&psock->psockpt);
+  }
+  PT_END(&psock->psockpt);
+}
+/*---------------------------------------------------------------------------*/
+void
+psock_init(register struct psock *psock, char *buffer, unsigned int buffersize)
+{
+  psock->state = STATE_NONE;
+  psock->readlen = 0;
+  psock->bufptr = buffer;
+  psock->bufsize = buffersize;
+  buf_setup(&psock->buf, (unsigned char*) buffer, buffersize);
+  PT_INIT(&psock->pt);
+  PT_INIT(&psock->psockpt);
+}
+/*---------------------------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/sys/clock.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/sys/clock.h
new file mode 100644
index 0000000..9f93583
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/sys/clock.h
@@ -0,0 +1,115 @@
+/** \addtogroup sys
+ * @{
+ */
+
+/**
+ * \defgroup clock Clock library
+ *
+ * The clock library is the interface between Contiki and the platform
+ * specific clock functionality. The clock library performs a single
+ * function: measuring time. Additionally, the clock library provides
+ * a macro, CLOCK_SECOND, which corresponds to one second of system
+ * time.
+ *
+ * \note The clock library need in many cases not be used
+ * directly. Rather, the \ref timer "timer library" or the \ref etimer
+ * "event timers" should be used.
+ *
+ * \sa \ref timer "Timer library"
+ * \sa \ref etimer "Event timers"
+ *
+ * @{
+ */
+
+/*
+ * Copyright (c) 2004, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the Contiki operating system.
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: clock.h,v 1.11 2009/01/24 15:20:11 adamdunkels Exp $
+ */
+#ifndef __CLOCK_H__
+#define __CLOCK_H__
+
+#include "net/clock-arch.h"
+
+//_RB_#include "contiki-conf.h"
+#if 0	/* XXX problems with signedness and use in timer_expired(). #if:ed it out for now. */
+
+/**
+ * Check if a clock time value is less than another clock time value.
+ *
+ * This macro checks if a clock time value is less than another clock
+ * time value. This macro is needed to correctly handle wrap-around of
+ * clock time values.
+ *
+ */
+#define CLOCK_LT( a, b )	( (clock_time_t) ((a) - (b)) < ((clock_time_t) (~((clock_time_t) 0)) >> 1) )
+#endif /* 0 */
+
+/**
+ * Initialize the clock library.
+ *
+ * This function initializes the clock library and should be called
+ * from the main() function of the system.
+ *
+ */
+void				clock_init( void );
+
+/**
+ * Get the current clock time.
+ *
+ * This function returns the current system clock time.
+ *
+ * \return The current clock time, measured in system ticks.
+ */
+CCIF clock_time_t	clock_time( void );
+
+void				clock_delay( unsigned int );
+
+/**
+ * A second, measured in system clock time.
+ *
+ * \hideinitializer
+ */
+#ifdef CLOCK_CONF_SECOND
+#define CLOCK_SECOND	CLOCK_CONF_SECOND
+#else
+#define CLOCK_SECOND	( clock_time_t ) 32
+#endif
+int					clock_fine_max( void );
+unsigned short		clock_fine( void );
+
+CCIF unsigned long	clock_seconds( void );
+#endif /* __CLOCK_H__ */
+
+/** @} */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/sys/pt.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/sys/pt.h
new file mode 100644
index 0000000..b0b9408
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/sys/pt.h
@@ -0,0 +1,335 @@
+/*
+ * Copyright (c) 2004-2005, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the Contiki operating system.
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: pt.h,v 1.3 2008/10/14 12:46:39 nvt-se Exp $
+ */
+
+/**
+ * \addtogroup pt
+ * @{
+ */
+
+/**
+ * \file
+ * Protothreads implementation.
+ * \author
+ * Adam Dunkels 
+ *
+ */
+#ifndef __PT_H__
+#define __PT_H__
+
+#include "sys/lc.h"
+
+struct pt
+{
+	lc_t	lc;
+};
+
+#define PT_WAITING	0
+#define PT_YIELDED	1
+#define PT_EXITED	2
+#define PT_ENDED	3
+
+/**
+ * \name Initialization
+ * @{
+ */
+
+/**
+ * Initialize a protothread.
+ *
+ * Initializes a protothread. Initialization must be done prior to
+ * starting to execute the protothread.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \sa PT_SPAWN()
+ *
+ * \hideinitializer
+ */
+#define PT_INIT( pt )	LC_INIT( (pt)->lc )
+
+/** @} */
+
+/**
+ * \name Declaration and definition
+ * @{
+ */
+
+/**
+ * Declaration of a protothread.
+ *
+ * This macro is used to declare a protothread. All protothreads must
+ * be declared with this macro.
+ *
+ * \param name_args The name and arguments of the C function
+ * implementing the protothread.
+ *
+ * \hideinitializer
+ */
+#define PT_THREAD( name_args )	char name_args
+
+/**
+ * Declare the start of a protothread inside the C function
+ * implementing the protothread.
+ *
+ * This macro is used to declare the starting point of a
+ * protothread. It should be placed at the start of the function in
+ * which the protothread runs. All C statements above the PT_BEGIN()
+ * invokation will be executed each time the protothread is scheduled.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \hideinitializer
+ */
+#define PT_BEGIN( pt )			   \
+	{							   \
+		char	PT_YIELD_FLAG = 1; \
+		LC_RESUME( (pt)->lc )
+
+/**
+ * Declare the end of a protothread.
+ *
+ * This macro is used for declaring that a protothread ends. It must
+ * always be used together with a matching PT_BEGIN() macro.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \hideinitializer
+ */
+#define PT_END( pt )	\
+	LC_END( (pt)->lc ); \
+	PT_YIELD_FLAG = 0;	\
+	PT_INIT( pt );		\
+	return PT_ENDED;	\
+}
+
+/** @} */
+
+/**
+ * \name Blocked wait
+ * @{
+ */
+
+/**
+ * Block and wait until condition is true.
+ *
+ * This macro blocks the protothread until the specified condition is
+ * true.
+ *
+ * \param pt A pointer to the protothread control structure.
+ * \param condition The condition.
+ *
+ * \hideinitializer
+ */
+#define PT_WAIT_UNTIL( pt, condition ) \
+	do								   \
+	{								   \
+		LC_SET( (pt)->lc );			   \
+		if( !(condition) )			   \
+		{							   \
+			return PT_WAITING;		   \
+		}							   \
+	} while( 0 )
+
+/**
+ * Block and wait while condition is true.
+ *
+ * This function blocks and waits while condition is true. See
+ * PT_WAIT_UNTIL().
+ *
+ * \param pt A pointer to the protothread control structure.
+ * \param cond The condition.
+ *
+ * \hideinitializer
+ */
+#define PT_WAIT_WHILE( pt, cond )	PT_WAIT_UNTIL( (pt), !(cond) )
+	/** @} */
+
+	/**
+ * \name Hierarchical protothreads
+ * @{
+ */
+
+/**
+ * Block and wait until a child protothread completes.
+ *
+ * This macro schedules a child protothread. The current protothread
+ * will block until the child protothread completes.
+ *
+ * \note The child protothread must be manually initialized with the
+ * PT_INIT() function before this function is used.
+ *
+ * \param pt A pointer to the protothread control structure.
+ * \param thread The child protothread with arguments
+ *
+ * \sa PT_SPAWN()
+ *
+ * \hideinitializer
+ */
+#define PT_WAIT_THREAD( pt, thread )	PT_WAIT_WHILE( (pt), PT_SCHEDULE(thread) )
+
+/**
+ * Spawn a child protothread and wait until it exits.
+ *
+ * This macro spawns a child protothread and waits until it exits. The
+ * macro can only be used within a protothread.
+ *
+ * \param pt A pointer to the protothread control structure.
+ * \param child A pointer to the child protothread's control structure.
+ * \param thread The child protothread with arguments
+ *
+ * \hideinitializer
+ */
+#define PT_SPAWN( pt, child, thread )	  \
+	do									  \
+	{									  \
+		PT_INIT( (child) );				  \
+		PT_WAIT_THREAD( (pt), (thread) ); \
+	} while( 0 )
+
+		/** @} */
+
+		/**
+ * \name Exiting and restarting
+ * @{
+ */
+
+/**
+ * Restart the protothread.
+ *
+ * This macro will block and cause the running protothread to restart
+ * its execution at the place of the PT_BEGIN() call.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \hideinitializer
+ */
+#define PT_RESTART( pt )   \
+	do					   \
+	{					   \
+		PT_INIT( pt );	   \
+		return PT_WAITING; \
+	} while( 0 )
+
+/**
+ * Exit the protothread.
+ *
+ * This macro causes the protothread to exit. If the protothread was
+ * spawned by another protothread, the parent protothread will become
+ * unblocked and can continue to run.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \hideinitializer
+ */
+#define PT_EXIT( pt )	  \
+	do					  \
+	{					  \
+		PT_INIT( pt );	  \
+		return PT_EXITED; \
+	} while( 0 )
+				/** @} */
+
+				/**
+ * \name Calling a protothread
+ * @{
+ */
+
+/**
+ * Schedule a protothread.
+ *
+ * This function schedules a protothread. The return value of the
+ * function is non-zero if the protothread is running or zero if the
+ * protothread has exited.
+ *
+ * \param f The call to the C function implementing the protothread to
+ * be scheduled
+ *
+ * \hideinitializer
+ */
+#define PT_SCHEDULE( f )	( (f) < PT_EXITED )
+				/** @} */
+
+				/**
+ * \name Yielding from a protothread
+ * @{
+ */
+
+/**
+ * Yield from the current protothread.
+ *
+ * This function will yield the protothread, thereby allowing other
+ * processing to take place in the system.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \hideinitializer
+ */
+#define PT_YIELD( pt )			 \
+	do							 \
+	{							 \
+		PT_YIELD_FLAG = 0;		 \
+		LC_SET( (pt)->lc );		 \
+		if( PT_YIELD_FLAG == 0 ) \
+		{						 \
+			return PT_YIELDED;	 \
+		}						 \
+	} while( 0 )
+
+/**
+ * \brief      Yield from the protothread until a condition occurs.
+ * \param pt   A pointer to the protothread control structure.
+ * \param cond The condition.
+ *
+ *             This function will yield the protothread, until the
+ *             specified condition evaluates to true.
+ *
+ *
+ * \hideinitializer
+ */
+#define PT_YIELD_UNTIL( pt, cond )			  \
+	do										  \
+	{										  \
+		PT_YIELD_FLAG = 0;					  \
+		LC_SET( (pt)->lc );					  \
+		if( (PT_YIELD_FLAG == 0) || !(cond) ) \
+		{									  \
+			return PT_YIELDED;				  \
+		}									  \
+	} while( 0 )
+						/** @} */
+#endif /* __PT_H__ */
+
+						/** @} */
+						
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/sys/timer.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/sys/timer.h
new file mode 100644
index 0000000..1d87e7e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/sys/timer.h
@@ -0,0 +1,101 @@
+/** \addtogroup sys
+ * @{ */
+
+/**
+ * \defgroup timer Timer library
+ *
+ * The Contiki kernel does not provide support for timed
+ * events. Rather, an application that wants to use timers needs to
+ * explicitly use the timer library.
+ *
+ * The timer library provides functions for setting, resetting and
+ * restarting timers, and for checking if a timer has expired. An
+ * application must "manually" check if its timers have expired; this
+ * is not done automatically.
+ *
+ * A timer is declared as a \c struct \c timer and all access to the
+ * timer is made by a pointer to the declared timer.
+ *
+ * \note The timer library is not able to post events when a timer
+ * expires. The \ref etimer "Event timers" should be used for this
+ * purpose.
+ *
+ * \note The timer library uses the \ref clock "Clock library" to
+ * measure time. Intervals should be specified in the format used by
+ * the clock library.
+ *
+ * \sa \ref etimer "Event timers"
+ *
+ * @{
+ */
+
+/**
+ * \file
+ * Timer library header file.
+ * \author
+ * Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2004, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the Contiki operating system.
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: timer.h,v 1.2 2008/09/21 08:58:05 adamdunkels Exp $
+ */
+#ifndef __TIMER_H__
+#define __TIMER_H__
+
+#include "sys/clock.h"
+
+/**
+ * A timer.
+ *
+ * This structure is used for declaring a timer. The timer must be set
+ * with timer_set() before it can be used.
+ *
+ * \hideinitializer
+ */
+struct timer
+{
+	clock_time_t	start;
+	clock_time_t	interval;
+};
+
+void			timer_set( struct timer *t, clock_time_t interval );
+void			timer_reset( struct timer *t );
+void			timer_restart( struct timer *t );
+int				timer_expired( struct timer *t );
+clock_time_t	timer_remaining( struct timer *t );
+#endif /* __TIMER_H__ */
+
+/** @} */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/timer.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/timer.c
new file mode 100644
index 0000000..e520391
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/timer.c
@@ -0,0 +1,151 @@
+/**
+ * \addtogroup timer
+ * @{
+ */
+
+/**
+ * \file
+ * Timer library implementation.
+ * \author
+ * Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2004, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the Contiki operating system.
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: timer.c,v 1.5 2009/01/24 15:20:11 adamdunkels Exp $
+ */
+
+//_RB_#include "contiki-conf.h"
+#include "uip-conf.h"
+#include "net/clock-arch.h"
+#include "sys/clock.h"
+#include "sys/timer.h"
+
+/*---------------------------------------------------------------------------*/
+
+/**
+ * Set a timer.
+ *
+ * This function is used to set a timer for a time sometime in the
+ * future. The function timer_expired() will evaluate to true after
+ * the timer has expired.
+ *
+ * \param t A pointer to the timer
+ * \param interval The interval before the timer expires.
+ *
+ */
+void timer_set( struct timer *t, clock_time_t interval )
+{
+	t->interval = interval;
+	t->start = clock_time();
+}
+
+/*---------------------------------------------------------------------------*/
+
+/**
+ * Reset the timer with the same interval.
+ *
+ * This function resets the timer with the same interval that was
+ * given to the timer_set() function. The start point of the interval
+ * is the exact time that the timer last expired. Therefore, this
+ * function will cause the timer to be stable over time, unlike the
+ * timer_restart() function.
+ *
+ * \param t A pointer to the timer.
+ *
+ * \sa timer_restart()
+ */
+void timer_reset( struct timer *t )
+{
+	t->start += t->interval;
+}
+
+/*---------------------------------------------------------------------------*/
+
+/**
+ * Restart the timer from the current point in time
+ *
+ * This function restarts a timer with the same interval that was
+ * given to the timer_set() function. The timer will start at the
+ * current time.
+ *
+ * \note A periodic timer will drift if this function is used to reset
+ * it. For preioric timers, use the timer_reset() function instead.
+ *
+ * \param t A pointer to the timer.
+ *
+ * \sa timer_reset()
+ */
+void timer_restart( struct timer *t )
+{
+	t->start = clock_time();
+}
+
+/*---------------------------------------------------------------------------*/
+
+/**
+ * Check if a timer has expired.
+ *
+ * This function tests if a timer has expired and returns true or
+ * false depending on its status.
+ *
+ * \param t A pointer to the timer
+ *
+ * \return Non-zero if the timer has expired, zero otherwise.
+ *
+ */
+int timer_expired( struct timer *t )
+{
+	return( clock_time_t ) ( clock_time() - t->start ) >= ( clock_time_t ) t->interval;
+}
+
+/*---------------------------------------------------------------------------*/
+
+/**
+ * The time until the timer expires
+ *
+ * This function returns the time until the timer expires.
+ *
+ * \param t A pointer to the timer
+ *
+ * \return The time until the timer expires
+ *
+ */
+clock_time_t timer_remaining( struct timer *t )
+{
+	return t->start + t->interval - clock_time();
+}
+
+/*---------------------------------------------------------------------------*/
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/uip.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/uip.c
new file mode 100644
index 0000000..78c6713
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/uip.c
@@ -0,0 +1,2143 @@
+//#define DEBUG_PRINTF( ... ) /*printf(__VA_ARGS__)*/
+
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \file
+ * The uIP TCP/IP stack code.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *	notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *	notice, this list of conditions and the following disclaimer in the
+ *	documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *	products derived from this software without specific prior
+ *	written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip.c,v 1.15 2008/10/15 08:08:32 adamdunkels Exp $
+ *
+ */
+
+/*
+ * uIP is a small implementation of the IP, UDP and TCP protocols (as
+ * well as some basic ICMP stuff). The implementation couples the IP,
+ * UDP, TCP and the application layers very tightly. To keep the size
+ * of the compiled code down, this code frequently uses the goto
+ * statement. While it would be possible to break the uip_process()
+ * function into many smaller functions, this would increase the code
+ * size because of the overhead of parameter passing and the fact that
+ * the optimier would not be as efficient.
+ *
+ * The principle is that we have a small buffer, called the uip_buf,
+ * in which the device driver puts an incoming packet. The TCP/IP
+ * stack parses the headers in the packet, and calls the
+ * application. If the remote host has sent data to the application,
+ * this data is present in the uip_buf and the application read the
+ * data from there. It is up to the application to put this data into
+ * a byte stream if needed. The application will not be fed with data
+ * that is out of sequence.
+ *
+ * If the application whishes to send data to the peer, it should put
+ * its data into the uip_buf. The uip_appdata pointer points to the
+ * first available byte. The TCP/IP stack will calculate the
+ * checksums, and fill in the necessary header fields and finally send
+ * the packet back to the peer.
+*/
+#include "net/uip.h"
+#include "net/uipopt.h"
+#include "net/uip_arp.h"
+#include "net/uip_arch.h"
+
+/* If UIP_CONF_IPV6 is defined, we compile the uip6.c file instead of this one.
+Therefore this #ifndef removes the entire compilation output of the uip.c file */
+#if !UIP_CONF_IPV6
+
+#if UIP_CONF_IPV6
+	#include "net/uip-neighbor.h"
+#endif /* UIP_CONF_IPV6 */
+
+#include 
+
+/*---------------------------------------------------------------------------*/
+
+/* Variable definitions. */
+
+/* The IP address of this host. If it is defined to be fixed (by setting
+UIP_FIXEDADDR to 1 in uipopt.h), the address is set here. Otherwise, the address */
+#if UIP_FIXEDADDR > 0
+	const uip_ipaddr_t	uip_hostaddr = { UIP_IPADDR0, UIP_IPADDR1, UIP_IPADDR2, UIP_IPADDR3 };
+	const uip_ipaddr_t	uip_draddr = { UIP_DRIPADDR0, UIP_DRIPADDR1, UIP_DRIPADDR2, UIP_DRIPADDR3 };
+	const uip_ipaddr_t	uip_netmask = { UIP_NETMASK0, UIP_NETMASK1, UIP_NETMASK2, UIP_NETMASK3 };
+#else
+	uip_ipaddr_t uip_hostaddr, uip_draddr, uip_netmask;
+#endif /* UIP_FIXEDADDR */
+
+const uip_ipaddr_t	uip_broadcast_addr =
+#if UIP_CONF_IPV6
+	{ { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff } };
+#else /* UIP_CONF_IPV6 */
+	{ {	0xff, 0xff, 0xff, 0xff } };
+#endif /* UIP_CONF_IPV6 */
+
+const uip_ipaddr_t uip_all_zeroes_addr = { { 0x0, /* rest is 0 */ } };
+
+#if UIP_FIXEDETHADDR
+	const struct uip_eth_addr uip_ethaddr = { { UIP_ETHADDR0, UIP_ETHADDR1, UIP_ETHADDR2, UIP_ETHADDR3, UIP_ETHADDR4, UIP_ETHADDR5 } };
+#else
+	struct uip_eth_addr uip_ethaddr = { { 0, 0, 0, 0, 0, 0 } };
+#endif
+
+#ifndef UIP_CONF_EXTERNAL_BUFFER
+	/* The packet buffer that contains incoming packets. */
+	u8_t uip_buf[ UIP_BUFSIZE + 2 ];
+#endif /* UIP_CONF_EXTERNAL_BUFFER */
+
+/* The uip_appdata pointer points to application data. */
+void *uip_appdata;
+
+/* The uip_appdata pointer points to the application data which is to be sent. */
+void *uip_sappdata;
+
+#if UIP_URGDATA > 0
+	/* The uip_urgdata pointer points to urgent data (out-of-band data), if
+	present. */
+	void *uip_urgdata;
+	u16_t uip_urglen, uip_surglen;
+#endif /* UIP_URGDATA > 0 */
+
+/* The uip_len is either 8 or 16 bits, depending on the maximum packet size. */
+u16_t uip_len, uip_slen;
+
+/* The uip_flags variable is used for communication between the TCP/IP stack
+and the application program. */
+u8_t uip_flags;
+
+/* uip_conn always points to the current connection. */
+struct uip_conn	*uip_conn;
+struct uip_conn	uip_conns[ UIP_CONNS ];
+
+/* The uip_conns array holds all TCP connections. */
+u16_t uip_listenports[UIP_LISTENPORTS];
+
+/* The uip_listenports list all currently listning ports. */
+#if UIP_UDP
+	struct uip_udp_conn *uip_udp_conn;
+	struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS];
+#endif /* UIP_UDP */
+
+/* Ths ipid variable is an increasing number that is used for the IP ID	field. */
+static u16_t ipid;
+
+void uip_setipid( u16_t id )
+{
+	ipid = id;
+}
+
+/* The iss variable is used for the TCP	initial sequence number. */
+static u8_t	iss[ 4 ];
+
+#if UIP_ACTIVE_OPEN
+	/* Keeps track of the last port used for a new connection. */
+	static u16_t	lastport;
+#endif /* UIP_ACTIVE_OPEN */
+
+/* Temporary variables. */
+u8_t uip_acc32[ 4 ];
+static u8_t	c, opt;
+static u16_t tmp16;
+
+/* Structures and definitions. */
+#define TCP_FIN								0x01
+#define TCP_SYN								0x02
+#define TCP_RST								0x04
+#define TCP_PSH								0x08
+#define TCP_ACK								0x10
+#define TCP_URG								0x20
+#define TCP_CTL								0x3f
+
+#define TCP_OPT_END							0	/* End of TCP options list */
+#define TCP_OPT_NOOP						1	/* "No-operation" TCP option */
+#define TCP_OPT_MSS							2	/* Maximum segment size TCP option */
+
+#define TCP_OPT_MSS_LEN						4	/* Length of TCP MSS option. */
+
+#define ICMP_ECHO_REPLY						0
+#define ICMP_ECHO							8
+
+#define ICMP_DEST_UNREACHABLE				3
+#define ICMP_PORT_UNREACHABLE				3
+
+#define ICMP6_ECHO_REPLY					129
+#define ICMP6_ECHO							128
+#define ICMP6_NEIGHBOR_SOLICITATION			135
+#define ICMP6_NEIGHBOR_ADVERTISEMENT		136
+
+#define ICMP6_FLAG_S						( 1 << 6 )
+#define ICMP6_OPTION_SOURCE_LINK_ADDRESS	1
+#define ICMP6_OPTION_TARGET_LINK_ADDRESS	2
+
+/* Macros. */
+#define BUF		( ( struct uip_tcpip_hdr * ) &uip_buf[UIP_LLH_LEN] )
+#define FBUF	( ( struct uip_tcpip_hdr * ) &uip_reassbuf[0] )
+#define ICMPBUF ( ( struct uip_icmpip_hdr * ) &uip_buf[UIP_LLH_LEN] )
+#define UDPBUF	( ( struct uip_udpip_hdr * ) &uip_buf[UIP_LLH_LEN] )
+
+#if UIP_STATISTICS == 1
+	struct uip_stats	uip_stat;
+	#define UIP_STAT( s )	s
+#else
+	#define UIP_STAT( s )
+#endif /* UIP_STATISTICS == 1 */
+
+#if UIP_LOGGING == 1
+	#include 
+	void	uip_log( char *msg );
+	#define UIP_LOG( m )	uip_log( m )
+#else
+	#define UIP_LOG( m )
+#endif /* UIP_LOGGING == 1 */
+
+#if !UIP_ARCH_ADD32
+	void uip_add32( u8_t *op32, u16_t op16 )
+	{
+		uip_acc32[3] = op32[3] + ( op16 & 0xff );
+		uip_acc32[2] = op32[2] + ( op16 >> 8 );
+		uip_acc32[1] = op32[1];
+		uip_acc32[0] = op32[0];
+
+		if( uip_acc32[2] < (op16 >> 8) )
+		{
+			++uip_acc32[1];
+			if( uip_acc32[1] == 0 )
+			{
+				++uip_acc32[0];
+			}
+		}
+
+		if( uip_acc32[3] < (op16 & 0xff) )
+		{
+			++uip_acc32[2];
+			if( uip_acc32[2] == 0 )
+			{
+				++uip_acc32[1];
+				if( uip_acc32[1] == 0 )
+				{
+					++uip_acc32[0];
+				}
+			}
+		}
+	}
+/*---------------------------------------------------------------------------*/
+#endif /* UIP_ARCH_ADD32 */
+
+#if !UIP_ARCH_CHKSUM
+
+	static u16_t chksum( u16_t sum, const u8_t *data, u16_t len )
+	{
+		u16_t		t;
+		const u8_t	*dataptr;
+		const u8_t	*last_byte;
+
+		dataptr = data;
+		last_byte = data + len - 1;
+
+		while( dataptr < last_byte )
+		{
+			/* At least two more bytes */
+			t = ( dataptr[ 0 ] << 8 ) + dataptr[ 1 ];
+			sum += t;
+			if( sum < t )
+			{
+				sum++;	/* carry */
+			}
+
+			dataptr += 2;
+		}
+
+		if( dataptr == last_byte )
+		{
+			t = ( dataptr[ 0 ] << 8 ) + 0;
+			sum += t;
+			if( sum < t )
+			{
+				sum++;	/* carry */
+			}
+		}
+
+		/* Return sum in host byte order. */
+		return sum;
+	}
+	/*---------------------------------------------------------------------------*/
+
+	u16_t uip_chksum( u16_t *data, u16_t len )
+	{
+		return htons( chksum( 0, ( u8_t * ) data, len ) );
+	}
+	/*---------------------------------------------------------------------------*/
+
+	#ifndef UIP_ARCH_IPCHKSUM
+		u16_t uip_ipchksum( void )
+		{
+			u16_t	sum;
+
+			sum = chksum( 0, &uip_buf[UIP_LLH_LEN], UIP_IPH_LEN );
+
+			//DEBUG_PRINTF( "uip_ipchksum: sum 0x%04x\n", sum );
+			return( sum == 0 ) ? 0xffff : htons( sum );
+		}
+	#endif
+	/*---------------------------------------------------------------------------*/
+
+	static u16_t upper_layer_chksum( u8_t proto )
+	{
+		u16_t	upper_layer_len;
+		u16_t	sum;
+
+		#if UIP_CONF_IPV6
+			upper_layer_len = ( ((u16_t) (BUF->len[ 0 ]) << 8) + BUF->len[ 1 ] );
+		#else /* UIP_CONF_IPV6 */
+			upper_layer_len = ( ((u16_t) (BUF->len[ 0 ]) << 8) + BUF->len[ 1 ] ) - UIP_IPH_LEN;
+		#endif /* UIP_CONF_IPV6 */
+
+		/* First sum pseudoheader. */
+
+		/* IP protocol and length fields. This addition cannot carry. */
+		sum = upper_layer_len + proto;
+
+		/* Sum IP source and destination addresses. */
+		sum = chksum( sum, ( u8_t * ) &BUF->srcipaddr, 2 * sizeof(uip_ipaddr_t) );
+
+		/* Sum TCP header and data. */
+		sum = chksum( sum, &uip_buf[UIP_IPH_LEN + UIP_LLH_LEN], upper_layer_len );
+
+		return( sum == 0 ) ? 0xffff : htons( sum );
+	}
+	/*---------------------------------------------------------------------------*/
+
+	#if UIP_CONF_IPV6
+		u16_t uip_icmp6chksum( void )
+		{
+			return upper_layer_chksum( UIP_PROTO_ICMP6 );
+		}
+	#endif /* UIP_CONF_IPV6 */
+	/*---------------------------------------------------------------------------*/
+
+	u16_t uip_tcpchksum( void )
+	{
+		return upper_layer_chksum( UIP_PROTO_TCP );
+	}
+	/*---------------------------------------------------------------------------*/
+
+	#if UIP_UDP_CHECKSUMS
+		u16_t uip_udpchksum( void )
+		{
+			return upper_layer_chksum( UIP_PROTO_UDP );
+		}
+	#endif /* UIP_UDP_CHECKSUMS */
+
+#endif /* UIP_ARCH_CHKSUM */
+/*---------------------------------------------------------------------------*/
+
+void uip_init( void )
+{
+	for( c = 0; c < UIP_LISTENPORTS; ++c )
+	{
+		uip_listenports[ c ] = 0;
+	}
+
+	for( c = 0; c < UIP_CONNS; ++c )
+	{
+		uip_conns[ c ].tcpstateflags = UIP_CLOSED;
+	}
+
+	#if UIP_ACTIVE_OPEN
+		lastport = 1024;
+	#endif /* UIP_ACTIVE_OPEN */
+
+	#if UIP_UDP
+		for( c = 0; c < UIP_UDP_CONNS; ++c )
+		{
+			uip_udp_conns[ c ].lport = 0;
+		}
+	#endif /* UIP_UDP */
+
+	/* IPv4 initialization. */
+	#if UIP_FIXEDADDR == 0
+		/*  uip_hostaddr[ 0 ] = uip_hostaddr[ 1 ] = 0;*/
+	#endif /* UIP_FIXEDADDR */
+}
+/*---------------------------------------------------------------------------*/
+
+#if UIP_ACTIVE_OPEN
+	struct uip_conn *uip_connect( uip_ipaddr_t *ripaddr, u16_t rport )
+	{
+		register struct uip_conn	*conn, *cconn;
+
+		/* Find an unused local port. */
+	again:
+		++lastport;
+
+		if( lastport >= 32000 )
+		{
+			lastport = 4096;
+		}
+
+		/* Check if this port is already in use, and if so try to find
+		 another one. */
+		for( c = 0; c < UIP_CONNS; ++c )
+		{
+			conn = &uip_conns[ c ];
+			if( conn->tcpstateflags != UIP_CLOSED && conn->lport == htons(lastport) )
+			{
+				goto again;
+			}
+		}
+
+		conn = 0;
+		for( c = 0; c < UIP_CONNS; ++c )
+		{
+			cconn = &uip_conns[ c ];
+			if( cconn->tcpstateflags == UIP_CLOSED )
+			{
+				conn = cconn;
+				break;
+			}
+
+			if( cconn->tcpstateflags == UIP_TIME_WAIT )
+			{
+				if( conn == 0 || cconn->timer > conn->timer )
+				{
+					conn = cconn;
+				}
+			}
+		}
+
+		if( conn == 0 )
+		{
+			return 0;
+		}
+
+		conn->tcpstateflags = UIP_SYN_SENT;
+
+		conn->snd_nxt[ 0 ] = iss[ 0 ];
+		conn->snd_nxt[ 1 ] = iss[ 1 ];
+		conn->snd_nxt[ 2 ] = iss[ 2 ];
+		conn->snd_nxt[ 3 ] = iss[ 3 ];
+
+		conn->initialmss = conn->mss = UIP_TCP_MSS;
+
+		conn->len = 1;		/* TCP length of the SYN is one. */
+		conn->nrtx = 0;
+		conn->timer = 1;	/* Send the SYN next time around. */
+		conn->rto = UIP_RTO;
+		conn->sa = 0;
+		conn->sv = 16;		/* Initial value of the RTT variance. */
+		conn->lport = htons( lastport );
+		conn->rport = rport;
+		uip_ipaddr_copy( &conn->ripaddr, ripaddr );
+
+		return conn;
+	}
+/*---------------------------------------------------------------------------*/
+#endif /* UIP_ACTIVE_OPEN */
+
+#if UIP_UDP
+	struct uip_udp_conn *uip_udp_new( const uip_ipaddr_t *ripaddr, u16_t rport )
+	{
+		register struct uip_udp_conn	*conn;
+
+		/* Find an unused local port. */
+	again:
+		++lastport;
+
+		if( lastport >= 32000 )
+		{
+			lastport = 4096;
+		}
+
+		for( c = 0; c < UIP_UDP_CONNS; ++c )
+		{
+			if( uip_udp_conns[ c ].lport == htons(lastport) )
+			{
+				goto again;
+			}
+		}
+
+		conn = 0;
+		for( c = 0; c < UIP_UDP_CONNS; ++c )
+		{
+			if( uip_udp_conns[ c ].lport == 0 )
+			{
+				conn = &uip_udp_conns[ c ];
+				break;
+			}
+		}
+
+		if( conn == 0 )
+		{
+			return 0;
+		}
+
+		conn->lport = HTONS( lastport );
+		conn->rport = rport;
+		if( ripaddr == NULL )
+		{
+			memset( &conn->ripaddr, 0, sizeof(uip_ipaddr_t) );
+		}
+		else
+		{
+			uip_ipaddr_copy( &conn->ripaddr, ripaddr );
+		}
+
+		conn->ttl = UIP_TTL;
+
+		return conn;
+	}
+/*---------------------------------------------------------------------------*/
+#endif /* UIP_UDP */
+
+void uip_unlisten( u16_t port )
+{
+	for( c = 0; c < UIP_LISTENPORTS; ++c )
+	{
+		if( uip_listenports[ c ] == port )
+		{
+			uip_listenports[ c ] = 0;
+			return;
+		}
+	}
+}
+/*---------------------------------------------------------------------------*/
+
+void uip_listen( u16_t port )
+{
+	for( c = 0; c < UIP_LISTENPORTS; ++c )
+	{
+		if( uip_listenports[ c ] == 0 )
+		{
+			uip_listenports[ c ] = port;
+			return;
+		}
+	}
+}
+/*---------------------------------------------------------------------------*/
+
+/* XXX: IP fragment reassembly: not well-tested. */
+#if UIP_REASSEMBLY && !UIP_CONF_IPV6
+	#define UIP_REASS_BUFSIZE	( UIP_BUFSIZE - UIP_LLH_LEN )
+	static u8_t			uip_reassbuf[UIP_REASS_BUFSIZE];
+	static u8_t			uip_reassbitmap[UIP_REASS_BUFSIZE / ( 8 * 8 )];
+	static const u8_t	bitmap_bits[8] = { 0xff, 0x7f, 0x3f, 0x1f, 0x0f, 0x07, 0x03, 0x01 };
+	static u16_t		uip_reasslen;
+	static u8_t			uip_reassflags;
+	#define UIP_REASS_FLAG_LASTFRAG 0x01
+	static u8_t			uip_reasstmr;
+
+	#define IP_MF	0x20
+
+	static u8_t uip_reass( void )
+	{
+		u16_t	offset, len;
+		u16_t	i;
+
+		/* If ip_reasstmr is zero, no packet is present in the buffer, so we
+		 write the IP header of the fragment into the reassembly
+		 buffer. The timer is updated with the maximum age. */
+		if( uip_reasstmr == 0 )
+		{
+			memcpy( uip_reassbuf, &BUF->vhl, UIP_IPH_LEN );
+			uip_reasstmr = UIP_REASS_MAXAGE;
+			uip_reassflags = 0;
+
+			/* Clear the bitmap. */
+			memset( uip_reassbitmap, 0, sizeof(uip_reassbitmap) );
+		}
+
+		/* Check if the incoming fragment matches the one currently present
+		 in the reasembly buffer. If so, we proceed with copying the
+		 fragment into the buffer. */
+		if
+		(
+			BUF->srcipaddr[ 0 ] == FBUF->srcipaddr[ 0 ] &&
+			BUF->srcipaddr[ 1 ] == FBUF->srcipaddr[ 1 ] &&
+			BUF->destipaddr[ 0 ] == FBUF->destipaddr[ 0 ] &&
+			BUF->destipaddr[ 1 ] == FBUF->destipaddr[ 1 ] &&
+			BUF->ipid[ 0 ] == FBUF->ipid[ 0 ] &&
+			BUF->ipid[ 1 ] == FBUF->ipid[ 1 ]
+		)
+		{
+			len = ( BUF->len[ 0 ] << 8 ) + BUF->len[ 1 ] - ( BUF->vhl & 0x0f ) * 4;
+			offset = ( ((BUF->ipoffset[ 0 ] & 0x3f) << 8) + BUF->ipoffset[ 1 ] ) * 8;
+
+			/* If the offset or the offset + fragment length overflows the
+		   reassembly buffer, we discard the entire packet. */
+			if( offset > UIP_REASS_BUFSIZE || offset + len > UIP_REASS_BUFSIZE )
+			{
+				uip_reasstmr = 0;
+				goto nullreturn;
+			}
+
+			/* Copy the fragment into the reassembly buffer, at the right
+			offset. */
+			memcpy( &uip_reassbuf[UIP_IPH_LEN + offset], ( char * ) BUF + ( int ) ((BUF->vhl & 0x0f) * 4), len );
+
+			/* Update the bitmap. */
+			if( offset / (8 * 8) == (offset + len) / (8 * 8) )
+			{
+				/* If the two endpoints are in the same byte, we only update
+				that byte. */
+				uip_reassbitmap[offset / ( 8 * 8 )] |= bitmap_bits[( offset / 8 ) & 7] &~bitmap_bits[( (offset + len) / 8 ) & 7];
+			}
+			else
+			{
+				/* If the two endpoints are in different bytes, we update the
+				bytes in the endpoints and fill the stuff inbetween with
+				0xff. */
+				uip_reassbitmap[offset / ( 8 * 8 )] |= bitmap_bits[( offset / 8 ) & 7];
+				for( i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i )
+				{
+					uip_reassbitmap[i] = 0xff;
+				}
+
+				uip_reassbitmap[( offset + len ) / ( 8 * 8 )] |= ~bitmap_bits[( (offset + len) / 8 ) & 7];
+			}
+
+			/* If this fragment has the More Fragments flag set to zero, we
+			know that this is the last fragment, so we can calculate the
+			size of the entire packet. We also set the
+			IP_REASS_FLAG_LASTFRAG flag to indicate that we have received
+			the final fragment. */
+			if( (BUF->ipoffset[ 0 ] & IP_MF) == 0 )
+			{
+				uip_reassflags |= UIP_REASS_FLAG_LASTFRAG;
+				uip_reasslen = offset + len;
+			}
+
+			/* Finally, we check if we have a full packet in the buffer. We do
+			this by checking if we have the last fragment and if all bits
+			in the bitmap are set. */
+			if( uip_reassflags & UIP_REASS_FLAG_LASTFRAG )
+			{
+				/* Check all bytes up to and including all but the last byte in
+				the bitmap. */
+				for( i = 0; i < uip_reasslen / (8 * 8) - 1; ++i )
+				{
+					if( uip_reassbitmap[i] != 0xff )
+					{
+						goto nullreturn;
+					}
+				}
+
+				/* Check the last byte in the bitmap. It should contain just the
+				right amount of bits. */
+				if( uip_reassbitmap[uip_reasslen / (8 * 8)] != (u8_t)~bitmap_bits[uip_reasslen / 8 & 7] )
+				{
+					goto nullreturn;
+				}
+
+				/* If we have come this far, we have a full packet in the
+				buffer, so we allocate a pbuf and copy the packet into it. We
+				also reset the timer. */
+				uip_reasstmr = 0;
+				memcpy( BUF, FBUF, uip_reasslen );
+
+				/* Pretend to be a "normal" (i.e., not fragmented) IP packet
+				from now on. */
+				BUF->ipoffset[ 0 ] = BUF->ipoffset[ 1 ] = 0;
+				BUF->len[ 0 ] = uip_reasslen >> 8;
+				BUF->len[ 1 ] = uip_reasslen & 0xff;
+				BUF->ipchksum = 0;
+				BUF->ipchksum = ~( uip_ipchksum() );
+
+				return uip_reasslen;
+			}
+		}
+
+	nullreturn:
+
+		return 0;
+	}
+/*---------------------------------------------------------------------------*/
+#endif /* UIP_REASSEMBLY */
+
+
+static void uip_add_rcv_nxt( u16_t n )
+{
+	uip_add32( uip_conn->rcv_nxt, n );
+	uip_conn->rcv_nxt[ 0 ] = uip_acc32[ 0 ];
+	uip_conn->rcv_nxt[ 1 ] = uip_acc32[ 1 ];
+	uip_conn->rcv_nxt[ 2 ] = uip_acc32[ 2 ];
+	uip_conn->rcv_nxt[ 3 ] = uip_acc32[ 3 ];
+}
+/*---------------------------------------------------------------------------*/
+
+void uip_process( u8_t flag )
+{
+	register struct uip_conn	*uip_connr = uip_conn;
+
+	#if UIP_UDP
+		if( flag == UIP_UDP_SEND_CONN )
+		{
+			goto udp_send;
+		}
+	#endif /* UIP_UDP */
+
+	uip_sappdata = uip_appdata = &uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN];
+
+	/* Check if we were invoked because of a poll request for a
+	 particular connection. */
+	if( flag == UIP_POLL_REQUEST )
+	{
+		if( (uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_ESTABLISHED && !uip_outstanding(uip_connr) )
+		{
+			uip_flags = UIP_POLL;
+			UIP_APPCALL();
+			goto appsend;
+		}
+
+		goto drop;
+
+		/* Check if we were invoked because of the perodic timer fireing. */
+	}
+	else if( flag == UIP_TIMER )
+	{
+		#if UIP_REASSEMBLY
+			if( uip_reasstmr != 0 )
+			{
+				--uip_reasstmr;
+			}
+		#endif /* UIP_REASSEMBLY */
+
+		/* Increase the initial sequence number. */
+		if( ++iss[ 3 ] == 0 )
+		{
+			if( ++iss[ 2 ] == 0 )
+			{
+				if( ++iss[ 1 ] == 0 )
+				{
+					++iss[ 0 ];
+				}
+			}
+		}
+
+		/* Reset the length variables. */
+		uip_len = 0;
+		uip_slen = 0;
+
+		/* Check if the connection is in a state in which we simply wait
+		for the connection to time out. If so, we increase the
+		connection's timer and remove the connection if it times
+		out. */
+		if( uip_connr->tcpstateflags == UIP_TIME_WAIT || uip_connr->tcpstateflags == UIP_FIN_WAIT_2 )
+		{
+			++( uip_connr->timer );
+			if( uip_connr->timer == UIP_TIME_WAIT_TIMEOUT )
+			{
+				uip_connr->tcpstateflags = UIP_CLOSED;
+			}
+		}
+		else if( uip_connr->tcpstateflags != UIP_CLOSED )
+		{
+			/* If the connection has outstanding data, we increase the
+			connection's timer and see if it has reached the RTO value
+			in which case we retransmit. */
+			if( uip_outstanding(uip_connr) )
+			{
+				if( uip_connr->timer-- == 0 )
+				{
+					if
+					(
+						uip_connr->nrtx == UIP_MAXRTX ||
+						(
+							(uip_connr->tcpstateflags == UIP_SYN_SENT || uip_connr->tcpstateflags == UIP_SYN_RCVD) &&
+							uip_connr->nrtx == UIP_MAXSYNRTX
+						)
+					)
+					{
+						uip_connr->tcpstateflags = UIP_CLOSED;
+
+						/* We call UIP_APPCALL() with uip_flags set to
+						UIP_TIMEDOUT to inform the application that the
+						connection has timed out. */
+						uip_flags = UIP_TIMEDOUT;
+						UIP_APPCALL();
+
+						/* We also send a reset packet to the remote host. */
+						BUF->flags = TCP_RST | TCP_ACK;
+						goto tcp_send_nodata;
+					}
+
+					/* Exponential backoff. */
+					uip_connr->timer = UIP_RTO << ( uip_connr->nrtx > 4 ? 4 : uip_connr->nrtx );
+					++( uip_connr->nrtx );
+
+					/* Ok, so we need to retransmit. We do this differently
+					depending on which state we are in. In ESTABLISHED, we
+					call upon the application so that it may prepare the
+					data for the retransmit. In SYN_RCVD, we resend the
+					SYNACK that we sent earlier and in LAST_ACK we have to
+					retransmit our FINACK. */
+							UIP_STAT( ++uip_stat.tcp.rexmit );
+					switch( uip_connr->tcpstateflags & UIP_TS_MASK )
+					{
+						case UIP_SYN_RCVD:
+							/* In the SYN_RCVD state, we should retransmit our
+			   				SYNACK. */
+							goto tcp_send_synack;
+
+						#if UIP_ACTIVE_OPEN
+							case UIP_SYN_SENT:
+								/* In the SYN_SENT state, we retransmit out SYN. */
+								BUF->flags = 0;
+								goto tcp_send_syn;
+						#endif /* UIP_ACTIVE_OPEN */
+
+						case UIP_ESTABLISHED:
+							/* In the ESTABLISHED state, we call upon the application
+							to do the actual retransmit after which we jump into
+							the code for sending out the packet (the apprexmit
+							label). */
+							uip_flags = UIP_REXMIT;
+							UIP_APPCALL();
+							goto apprexmit;
+
+						case UIP_FIN_WAIT_1:
+						case UIP_CLOSING:
+						case UIP_LAST_ACK:
+							/* In all these states we should retransmit a FINACK. */
+							goto tcp_send_finack;
+					}
+				}
+			}
+			else if( (uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_ESTABLISHED )
+			{
+				/* If there was no need for a retransmission, we poll the
+				application for new data. */
+				uip_flags = UIP_POLL;
+				UIP_APPCALL();
+				goto appsend;
+			}
+		}
+
+		goto drop;
+	}
+
+	#if UIP_UDP
+		if( flag == UIP_UDP_TIMER )
+		{
+			if( uip_udp_conn->lport != 0 )
+			{
+				uip_conn = NULL;
+				uip_sappdata = uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPUDPH_LEN];
+				uip_len = uip_slen = 0;
+				uip_flags = UIP_POLL;
+				UIP_UDP_APPCALL();
+				goto udp_send;
+			}
+			else
+			{
+				goto drop;
+			}
+		}
+	#endif
+
+	/* This is where the input processing starts. */
+	UIP_STAT( ++uip_stat.ip.recv );
+
+	/* Start of IP input header processing code. */
+	#if UIP_CONF_IPV6
+		/* Check validity of the IP header. */
+		if( (BUF->vtc & 0xf0) != 0x60 )
+		{					/* IP version and header length. */
+			UIP_STAT( ++uip_stat.ip.drop );
+			UIP_STAT( ++uip_stat.ip.vhlerr );
+			UIP_LOG( "ipv6: invalid version." );
+			goto drop;
+		}
+
+	#else /* UIP_CONF_IPV6 */
+		/* Check validity of the IP header. */
+		if( BUF->vhl != 0x45 )
+		{					/* IP version and header length. */
+			UIP_STAT( ++uip_stat.ip.drop );
+			UIP_STAT( ++uip_stat.ip.vhlerr );
+			UIP_LOG( "ip: invalid version or header length." );
+			goto drop;
+		}
+
+	#endif /* UIP_CONF_IPV6 */
+
+	/* Check the size of the packet. If the size reported to us in
+	uip_len is smaller the size reported in the IP header, we assume
+	that the packet has been corrupted in transit. If the size of
+	uip_len is larger than the size reported in the IP packet header,
+	the packet has been padded and we set uip_len to the correct
+	value.. */
+	if( (BUF->len[ 0 ] << 8) + BUF->len[ 1 ] <= uip_len )
+	{
+		uip_len = ( BUF->len[ 0 ] << 8 ) + BUF->len[ 1 ];
+		#if UIP_CONF_IPV6
+			/* The length reported in the IPv6 header is the
+			length of the payload that follows the
+			header. However, uIP uses the uip_len variable
+			for holding the size of the entire packet,
+			including the IP header. For IPv4 this is not a
+			problem as the length field in the IPv4 header
+			contains the length of the entire packet. But
+			for IPv6 we need to add the size of the IPv6
+			header (40 bytes). */
+			uip_len += 40;
+		#endif /* UIP_CONF_IPV6 */
+	}
+	else
+	{
+		UIP_LOG( "ip: packet shorter than reported in IP header." );
+		goto drop;
+	}
+
+	#if !UIP_CONF_IPV6
+		/* Check the fragment flag. */
+		if( (BUF->ipoffset[ 0 ] & 0x3f) != 0 || BUF->ipoffset[ 1 ] != 0 )
+		{
+			#if UIP_REASSEMBLY
+				uip_len = uip_reass();
+				if( uip_len == 0 )
+				{
+					goto drop;
+				}
+			#else /* UIP_REASSEMBLY */
+				UIP_STAT( ++uip_stat.ip.drop );
+				UIP_STAT( ++uip_stat.ip.fragerr );
+				UIP_LOG( "ip: fragment dropped." );
+				goto drop;
+			#endif /* UIP_REASSEMBLY */
+		}
+	#endif /* UIP_CONF_IPV6 */
+
+	if( uip_ipaddr_cmp(&uip_hostaddr, &uip_all_zeroes_addr) )
+	{
+		/* If we are configured to use ping IP address configuration and
+		hasn't been assigned an IP address yet, we accept all ICMP
+		packets. */
+		#if UIP_PINGADDRCONF && !UIP_CONF_IPV6
+			if( BUF->proto == UIP_PROTO_ICMP )
+			{
+				UIP_LOG( "ip: possible ping config packet received." );
+				goto icmp_input;
+			}
+			else
+			{
+				UIP_LOG( "ip: packet dropped since no address assigned." );
+				goto drop;
+			}
+		#endif /* UIP_PINGADDRCONF */
+	}
+	else
+	{
+		/* If IP broadcast support is configured, we check for a broadcast
+		UDP packet, which may be destined to us. */
+		#if UIP_BROADCAST
+			//DEBUG_PRINTF( "UDP IP checksum 0x%04x\n", uip_ipchksum() );
+			if( BUF->proto == UIP_PROTO_UDP && uip_ipaddr_cmp(&BUF->destipaddr, &uip_broadcast_addr) /*&& uip_ipchksum() == 0xffff*/ )
+			{
+				goto udp_input;
+			}
+		#endif /* UIP_BROADCAST */
+
+		/* Check if the packet is destined for our IP address. */
+		#if !UIP_CONF_IPV6
+			if( !uip_ipaddr_cmp(&BUF->destipaddr, &uip_hostaddr) )
+			{
+				UIP_STAT( ++uip_stat.ip.drop );
+				goto drop;
+			}
+		#else /* UIP_CONF_IPV6 */
+			/* For IPv6, packet reception is a little trickier as we need to
+			make sure that we listen to certain multicast addresses (all
+			hosts multicast address, and the solicited-node multicast
+			address) as well. However, we will cheat here and accept all
+			multicast packets that are sent to the ff02::/16 addresses. */
+			if( !uip_ipaddr_cmp(&BUF->destipaddr, &uip_hostaddr) && BUF->destipaddr.u16[ 0 ] != HTONS(0xff02) )
+			{
+				UIP_STAT( ++uip_stat.ip.drop );
+				goto drop;
+			}
+		#endif /* UIP_CONF_IPV6 */
+	}
+
+	#if !UIP_CONF_IPV6
+		if( uip_ipchksum() != 0xffff )
+		{
+			/* Compute and check the IP header checksum. */
+			UIP_STAT( ++uip_stat.ip.drop );
+			UIP_STAT( ++uip_stat.ip.chkerr );
+			UIP_LOG( "ip: bad checksum." );
+			goto drop;
+		}
+	#endif /* UIP_CONF_IPV6 */
+
+	if( BUF->proto == UIP_PROTO_TCP )
+	{
+		/* Check for TCP packet. If so, proceed with TCP input processing. */
+		goto tcp_input;
+	}
+
+	#if UIP_UDP
+		if( BUF->proto == UIP_PROTO_UDP )
+		{
+			goto udp_input;
+		}
+	#endif /* UIP_UDP */
+
+	#if !UIP_CONF_IPV6
+		/* ICMPv4 processing code follows. */
+		if( BUF->proto != UIP_PROTO_ICMP )
+		{
+			/* We only allow ICMP packets from here. */
+			UIP_STAT( ++uip_stat.ip.drop );
+			UIP_STAT( ++uip_stat.ip.protoerr );
+			UIP_LOG( "ip: neither tcp nor icmp." );
+			goto drop;
+		}
+
+		#if UIP_PINGADDRCONF
+			icmp_input :
+		#endif /* UIP_PINGADDRCONF */
+
+		UIP_STAT( ++uip_stat.icmp.recv );
+
+		/* ICMP echo (i.e., ping) processing. This is simple, we only change
+		 the ICMP type from ECHO to ECHO_REPLY and adjust the ICMP
+		 checksum before we return the packet. */
+		if( ICMPBUF->type != ICMP_ECHO )
+		{
+			UIP_STAT( ++uip_stat.icmp.drop );
+			UIP_STAT( ++uip_stat.icmp.typeerr );
+			UIP_LOG( "icmp: not icmp echo." );
+			goto drop;
+		}
+
+		/* If we are configured to use ping IP address assignment, we use
+		 the destination IP address of this ping packet and assign it to
+		 ourself. */
+		#if UIP_PINGADDRCONF
+			if( uip_ipaddr_cmp(&uip_hostaddr, &uip_all_zeroes_addr) )
+			{
+				uip_hostaddr = BUF->destipaddr;
+			}
+		#endif /* UIP_PINGADDRCONF */
+
+		ICMPBUF->type = ICMP_ECHO_REPLY;
+
+		if( ICMPBUF->icmpchksum >= HTONS(0xffff - (ICMP_ECHO << 8)) )
+		{
+			ICMPBUF->icmpchksum += HTONS( ICMP_ECHO << 8 ) + 1;
+		}
+		else
+		{
+			ICMPBUF->icmpchksum += HTONS( ICMP_ECHO << 8 );
+		}
+
+		/* Swap IP addresses. */
+		uip_ipaddr_copy( &BUF->destipaddr, &BUF->srcipaddr );
+		uip_ipaddr_copy( &BUF->srcipaddr, &uip_hostaddr );
+
+		UIP_STAT( ++uip_stat.icmp.sent );
+		BUF->ttl = UIP_TTL;
+		goto ip_send_nolen;
+
+		/* End of IPv4 input header processing code. */
+
+	#else /* !UIP_CONF_IPV6 */
+
+		/* This is IPv6 ICMPv6 processing code. */
+
+		//DEBUG_PRINTF( "icmp6_input: length %d\n", uip_len );
+		if( BUF->proto != UIP_PROTO_ICMP6 )
+		{
+			/* We only allow ICMPv6 packets from here. */
+			UIP_STAT( ++uip_stat.ip.drop );
+			UIP_STAT( ++uip_stat.ip.protoerr );
+			UIP_LOG( "ip: neither tcp nor icmp6." );
+			goto drop;
+		}
+
+		UIP_STAT( ++uip_stat.icmp.recv );
+
+		/* If we get a neighbor solicitation for our address we should send
+		 a neighbor advertisement message back. */
+		if( ICMPBUF->type == ICMP6_NEIGHBOR_SOLICITATION )
+		{
+			if( uip_ipaddr_cmp(&ICMPBUF->icmp6data, &uip_hostaddr) )
+			{
+				if( ICMPBUF->options[ 0 ] == ICMP6_OPTION_SOURCE_LINK_ADDRESS )
+				{
+					/* Save the sender's address in our neighbor list. */
+					uip_neighbor_add( &ICMPBUF->srcipaddr, &(ICMPBUF->options[ 2 ]) );
+				}
+
+				/* We should now send a neighbor advertisement back to where the
+				neighbor solicication came from. */
+				ICMPBUF->type = ICMP6_NEIGHBOR_ADVERTISEMENT;
+				ICMPBUF->flags = ICMP6_FLAG_S;	/* Solicited flag. */
+
+				ICMPBUF->reserved1 = ICMPBUF->reserved2 = ICMPBUF->reserved3 = 0;
+
+				uip_ipaddr_copy( &ICMPBUF->destipaddr, &ICMPBUF->srcipaddr );
+				uip_ipaddr_copy( &ICMPBUF->srcipaddr, &uip_hostaddr );
+				ICMPBUF->options[ 0 ] = ICMP6_OPTION_TARGET_LINK_ADDRESS;
+				ICMPBUF->options[ 1 ] = 1;		/* Options length, 1 = 8 bytes. */
+				memcpy( &(ICMPBUF->options[ 2 ]), &uip_ethaddr, sizeof(uip_ethaddr) );
+				ICMPBUF->icmpchksum = 0;
+				ICMPBUF->icmpchksum = ~uip_icmp6chksum();
+
+				goto send;
+			}
+
+			goto drop;
+		}
+		else if( ICMPBUF->type == ICMP6_ECHO )
+		{
+			/* ICMP echo (i.e., ping) processing. This is simple, we only
+			change the ICMP type from ECHO to ECHO_REPLY and update the
+			ICMP checksum before we return the packet. */
+			ICMPBUF->type = ICMP6_ECHO_REPLY;
+
+			uip_ipaddr_copy( &BUF->destipaddr, &BUF->srcipaddr );
+			uip_ipaddr_copy( &BUF->srcipaddr, &uip_hostaddr );
+			ICMPBUF->icmpchksum = 0;
+			ICMPBUF->icmpchksum = ~uip_icmp6chksum();
+
+			UIP_STAT( ++uip_stat.icmp.sent );
+			goto send;
+		}
+		else
+		{
+			//DEBUG_PRINTF( "Unknown icmp6 message type %d\n", ICMPBUF->type );
+			UIP_STAT( ++uip_stat.icmp.drop );
+			UIP_STAT( ++uip_stat.icmp.typeerr );
+			UIP_LOG( "icmp: unknown ICMP message." );
+			goto drop;
+		}
+
+		/* End of IPv6 ICMP processing. */
+	#endif /* !UIP_CONF_IPV6 */
+
+	#if UIP_UDP
+		/* UDP input processing. */
+		udp_input :
+		/* UDP processing is really just a hack. We don't do anything to the
+		 UDP/IP headers, but let the UDP application do all the hard
+		 work. If the application sets uip_slen, it has a packet to
+		 send. */
+		#if UIP_UDP_CHECKSUMS
+			uip_len = uip_len - UIP_IPUDPH_LEN;
+			uip_appdata = &uip_buf[ UIP_LLH_LEN + UIP_IPUDPH_LEN ];
+			if( UDPBUF->udpchksum != 0 && uip_udpchksum() != 0xffff )
+			{
+				UIP_STAT( ++uip_stat.udp.drop );
+				UIP_STAT( ++uip_stat.udp.chkerr );
+				UIP_LOG( "udp: bad checksum." );
+				goto drop;
+			}
+
+		#else /* UIP_UDP_CHECKSUMS */
+			uip_len = uip_len - UIP_IPUDPH_LEN;
+		#endif /* UIP_UDP_CHECKSUMS */
+
+		/* Demultiplex this UDP packet between the UDP "connections". */
+		for( uip_udp_conn = &uip_udp_conns[ 0 ]; uip_udp_conn < &uip_udp_conns[UIP_UDP_CONNS]; ++uip_udp_conn )
+		{
+			/* If the local UDP port is non-zero, the connection is considered
+		   to be used. If so, the local port number is checked against the
+		   destination port number in the received packet. If the two port
+		   numbers match, the remote port number is checked if the
+		   connection is bound to a remote port. Finally, if the
+		   connection is bound to a remote IP address, the source IP
+		   address of the packet is checked. */
+			if
+			(
+				uip_udp_conn->lport != 0 &&
+				UDPBUF->destport == uip_udp_conn->lport &&
+				(uip_udp_conn->rport == 0 || UDPBUF->srcport == uip_udp_conn->rport) &&
+				(
+					uip_ipaddr_cmp(&uip_udp_conn->ripaddr, &uip_all_zeroes_addr) ||
+					uip_ipaddr_cmp(&uip_udp_conn->ripaddr, &uip_broadcast_addr) ||
+					uip_ipaddr_cmp(&BUF->srcipaddr, &uip_udp_conn->ripaddr)
+				)
+			)
+			{
+				goto udp_found;
+			}
+		}
+
+		UIP_LOG( "udp: no matching connection found" );
+
+		#if UIP_CONF_ICMP_DEST_UNREACH && !UIP_CONF_IPV6
+
+		/* Copy fields from packet header into payload of this ICMP packet. */
+		memcpy( &(ICMPBUF->payload[ 0 ]), ICMPBUF, UIP_IPH_LEN + 8 );
+
+		/* Set the ICMP type and code. */
+		ICMPBUF->type = ICMP_DEST_UNREACHABLE;
+		ICMPBUF->icode = ICMP_PORT_UNREACHABLE;
+
+		/* Calculate the ICMP checksum. */
+		ICMPBUF->icmpchksum = 0;
+		ICMPBUF->icmpchksum = ~uip_chksum( ( u16_t * ) &(ICMPBUF->type), 36 );
+
+		/* Set the IP destination address to be the source address of the
+		 original packet. */
+		uip_ipaddr_copy( &BUF->destipaddr, &BUF->srcipaddr );
+
+		/* Set our IP address as the source address. */
+		uip_ipaddr_copy( &BUF->srcipaddr, &uip_hostaddr );
+
+		/* The size of the ICMP destination unreachable packet is 36 + the
+		 size of the IP header (20) = 56. */
+		uip_len = 36 + UIP_IPH_LEN;
+		ICMPBUF->len[ 0 ] = 0;
+		ICMPBUF->len[ 1 ] = ( u8_t ) uip_len;
+		ICMPBUF->ttl = UIP_TTL;
+		ICMPBUF->proto = UIP_PROTO_ICMP;
+
+		goto ip_send_nolen;
+	#else /* UIP_CONF_ICMP_DEST_UNREACH */
+		goto drop;
+	#endif /* UIP_CONF_ICMP_DEST_UNREACH */
+
+	udp_found : uip_conn = NULL;
+	uip_flags = UIP_NEWDATA;
+	uip_sappdata = uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPUDPH_LEN];
+	uip_slen = 0;
+	UIP_UDP_APPCALL();
+
+udp_send:
+	if( uip_slen == 0 )
+	{
+		goto drop;
+	}
+
+	uip_len = uip_slen + UIP_IPUDPH_LEN;
+
+	#if UIP_CONF_IPV6
+		/* For IPv6, the IP length field does not include the IPv6 IP header
+		 length. */
+		BUF->len[ 0 ] = ( (uip_len - UIP_IPH_LEN) >> 8 );
+		BUF->len[ 1 ] = ( (uip_len - UIP_IPH_LEN) & 0xff );
+	#else /* UIP_CONF_IPV6 */
+		BUF->len[ 0 ] = ( uip_len >> 8 );
+		BUF->len[ 1 ] = ( uip_len & 0xff );
+	#endif /* UIP_CONF_IPV6 */
+
+	BUF->ttl = uip_udp_conn->ttl;
+	BUF->proto = UIP_PROTO_UDP;
+
+	UDPBUF->udplen = HTONS( uip_slen + UIP_UDPH_LEN );
+	UDPBUF->udpchksum = 0;
+
+	BUF->srcport = uip_udp_conn->lport;
+	BUF->destport = uip_udp_conn->rport;
+
+	uip_ipaddr_copy( &BUF->srcipaddr, &uip_hostaddr );
+	uip_ipaddr_copy( &BUF->destipaddr, &uip_udp_conn->ripaddr );
+
+	uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPTCPH_LEN];
+
+	#if UIP_UDP_CHECKSUMS
+		/* Calculate UDP checksum. */
+		UDPBUF->udpchksum = ~( uip_udpchksum() );
+		if( UDPBUF->udpchksum == 0 )
+		{
+			UDPBUF->udpchksum = 0xffff;
+		}
+	#endif /* UIP_UDP_CHECKSUMS */
+		goto ip_send_nolen;
+	#endif /* UIP_UDP */
+
+	/* TCP input processing. */
+	tcp_input : UIP_STAT( ++uip_stat.tcp.recv );
+
+	/* Start of TCP input header processing code. */
+	if( uip_tcpchksum() != 0xffff )
+	{
+		/* Compute and check the TCP checksum. */
+		UIP_STAT( ++uip_stat.tcp.drop );
+		UIP_STAT( ++uip_stat.tcp.chkerr );
+		UIP_LOG( "tcp: bad checksum." );
+		goto drop;
+	}
+
+	/* Demultiplex this segment. */
+
+	/* First check any active connections. */
+	for( uip_connr = &uip_conns[ 0 ]; uip_connr <= &uip_conns[UIP_CONNS - 1]; ++uip_connr )
+	{
+		if
+		(
+			uip_connr->tcpstateflags != UIP_CLOSED &&
+			BUF->destport == uip_connr->lport &&
+			BUF->srcport == uip_connr->rport &&
+			uip_ipaddr_cmp(&BUF->srcipaddr, &uip_connr->ripaddr)
+		)
+		{
+			goto found;
+		}
+	}
+
+	/* If we didn't find and active connection that expected the packet,
+	either this packet is an old duplicate, or this is a SYN packet
+	destined for a connection in LISTEN. If the SYN flag isn't set,
+	it is an old packet and we send a RST. */
+	if( (BUF->flags & TCP_CTL) != TCP_SYN )
+	{
+		goto reset;
+	}
+
+	tmp16 = BUF->destport;
+
+	/* Next, check listening connections. */
+	for( c = 0; c < UIP_LISTENPORTS; ++c )
+	{
+		if( tmp16 == uip_listenports[ c ] )
+		{
+			goto found_listen;
+		}
+	}
+
+	/* No matching connection found, so we send a RST packet. */
+	UIP_STAT( ++uip_stat.tcp.synrst );
+
+reset:
+	/* We do not send resets in response to resets. */
+	if( BUF->flags & TCP_RST )
+	{
+		goto drop;
+	}
+
+	UIP_STAT( ++uip_stat.tcp.rst );
+
+	BUF->flags = TCP_RST | TCP_ACK;
+	uip_len = UIP_IPTCPH_LEN;
+	BUF->tcpoffset = 5 << 4;
+
+	/* Flip the seqno and ackno fields in the TCP header. */
+	c = BUF->seqno[ 3 ];
+	BUF->seqno[ 3 ] = BUF->ackno[ 3 ];
+	BUF->ackno[ 3 ] = c;
+
+	c = BUF->seqno[ 2 ];
+	BUF->seqno[ 2 ] = BUF->ackno[ 2 ];
+	BUF->ackno[ 2 ] = c;
+
+	c = BUF->seqno[ 1 ];
+	BUF->seqno[ 1 ] = BUF->ackno[ 1 ];
+	BUF->ackno[ 1 ] = c;
+
+	c = BUF->seqno[ 0 ];
+	BUF->seqno[ 0 ] = BUF->ackno[ 0 ];
+	BUF->ackno[ 0 ] = c;
+
+	/* We also have to increase the sequence number we are
+	acknowledging. If the least significant byte overflowed, we need
+	to propagate the carry to the other bytes as well. */
+	if( ++BUF->ackno[ 3 ] == 0 )
+	{
+		if( ++BUF->ackno[ 2 ] == 0 )
+		{
+			if( ++BUF->ackno[ 1 ] == 0 )
+			{
+				++BUF->ackno[ 0 ];
+			}
+		}
+	}
+
+	/* Swap port numbers. */
+	tmp16 = BUF->srcport;
+	BUF->srcport = BUF->destport;
+	BUF->destport = tmp16;
+
+	/* Swap IP addresses. */
+	uip_ipaddr_copy( &BUF->destipaddr, &BUF->srcipaddr );
+	uip_ipaddr_copy( &BUF->srcipaddr, &uip_hostaddr );
+
+	/* And send out the RST packet! */
+	goto tcp_send_noconn;
+
+	/* This label will be jumped to if we matched the incoming packet
+	with a connection in LISTEN. In that case, we should create a new
+	connection and send a SYNACK in return. */
+found_listen:
+	/* First we check if there are any connections avaliable. Unused
+	connections are kept in the same table as used connections, but
+	unused ones have the tcpstate set to CLOSED. Also, connections in
+	TIME_WAIT are kept track of and we'll use the oldest one if no
+	CLOSED connections are found. Thanks to Eddie C. Dost for a very
+	nice algorithm for the TIME_WAIT search. */
+	uip_connr = 0;
+	for( c = 0; c < UIP_CONNS; ++c )
+	{
+		if( uip_conns[ c ].tcpstateflags == UIP_CLOSED )
+		{
+			uip_connr = &uip_conns[ c ];
+			break;
+		}
+
+		if( uip_conns[ c ].tcpstateflags == UIP_TIME_WAIT )
+		{
+			if( uip_connr == 0 || uip_conns[ c ].timer > uip_connr->timer )
+			{
+				uip_connr = &uip_conns[ c ];
+			}
+		}
+	}
+
+	if( uip_connr == 0 )
+	{
+		/* All connections are used already, we drop packet and hope that
+		the remote end will retransmit the packet at a time when we
+		have more spare connections. */
+		UIP_STAT( ++uip_stat.tcp.syndrop );
+		UIP_LOG( "tcp: found no unused connections." );
+		goto drop;
+	}
+
+	uip_conn = uip_connr;
+
+	/* Fill in the necessary fields for the new connection. */
+	uip_connr->rto = uip_connr->timer = UIP_RTO;
+	uip_connr->sa = 0;
+	uip_connr->sv = 4;
+	uip_connr->nrtx = 0;
+	uip_connr->lport = BUF->destport;
+	uip_connr->rport = BUF->srcport;
+	uip_ipaddr_copy( &uip_connr->ripaddr, &BUF->srcipaddr );
+	uip_connr->tcpstateflags = UIP_SYN_RCVD;
+
+	uip_connr->snd_nxt[ 0 ] = iss[ 0 ];
+	uip_connr->snd_nxt[ 1 ] = iss[ 1 ];
+	uip_connr->snd_nxt[ 2 ] = iss[ 2 ];
+	uip_connr->snd_nxt[ 3 ] = iss[ 3 ];
+	uip_connr->len = 1;
+
+	/* rcv_nxt should be the seqno from the incoming packet + 1. */
+	uip_connr->rcv_nxt[ 3 ] = BUF->seqno[ 3 ];
+	uip_connr->rcv_nxt[ 2 ] = BUF->seqno[ 2 ];
+	uip_connr->rcv_nxt[ 1 ] = BUF->seqno[ 1 ];
+	uip_connr->rcv_nxt[ 0 ] = BUF->seqno[ 0 ];
+	uip_add_rcv_nxt( 1 );
+
+	/* Parse the TCP MSS option, if present. */
+	if( (BUF->tcpoffset & 0xf0) > 0x50 )
+	{
+		for( c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2; )
+		{
+			opt = uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + c];
+			if( opt == TCP_OPT_END )
+			{
+				/* End of options. */
+				break;
+			}
+			else if( opt == TCP_OPT_NOOP )
+			{
+				++c;
+
+				/* NOP option. */
+			}
+			else if( opt == TCP_OPT_MSS && uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == TCP_OPT_MSS_LEN )
+			{
+				/* An MSS option with the right option length. */
+				tmp16 = ( (u16_t) uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8 ) | ( u16_t ) uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN + 3 + c];
+				uip_connr->initialmss = uip_connr->mss = tmp16 > UIP_TCP_MSS ? UIP_TCP_MSS : tmp16;
+
+				/* And we are done processing options. */
+				break;
+			}
+			else
+			{
+				/* All other options have a length field, so that we easily
+				can skip past them. */
+				if( uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0 )
+				{
+					/* If the length field is zero, the options are malformed
+					and we don't process them further. */
+					break;
+				}
+
+				c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c];
+			}
+		}
+	}
+
+	/* Our response will be a SYNACK. */
+	#if UIP_ACTIVE_OPEN
+		tcp_send_synack : BUF->flags = TCP_ACK;
+tcp_send_syn:
+		BUF->flags |= TCP_SYN;
+	#else /* UIP_ACTIVE_OPEN */
+		tcp_send_synack : BUF->flags = TCP_SYN | TCP_ACK;
+	#endif /* UIP_ACTIVE_OPEN */
+
+	/* We send out the TCP Maximum Segment Size option with our
+	SYNACK. */
+	BUF->optdata[ 0 ] = TCP_OPT_MSS;
+	BUF->optdata[ 1 ] = TCP_OPT_MSS_LEN;
+	BUF->optdata[ 2 ] = ( UIP_TCP_MSS ) / 256;
+	BUF->optdata[ 3 ] = ( UIP_TCP_MSS ) & 255;
+	uip_len = UIP_IPTCPH_LEN + TCP_OPT_MSS_LEN;
+	BUF->tcpoffset = ( (UIP_TCPH_LEN + TCP_OPT_MSS_LEN) / 4 ) << 4;
+	goto tcp_send;
+
+	/* This label will be jumped to if we found an active connection. */
+found:
+	uip_conn = uip_connr;
+	uip_flags = 0;
+
+	/* We do a very naive form of TCP reset processing; we just accept
+	any RST and kill our connection. We should in fact check if the
+	sequence number of this reset is wihtin our advertised window
+	before we accept the reset. */
+	if( BUF->flags & TCP_RST )
+	{
+		uip_connr->tcpstateflags = UIP_CLOSED;
+		UIP_LOG( "tcp: got reset, aborting connection." );
+		uip_flags = UIP_ABORT;
+		UIP_APPCALL();
+		goto drop;
+	}
+
+	/* Calculate the length of the data, if the application has sent
+	any data to us. */
+	c = ( BUF->tcpoffset >> 4 ) << 2;
+
+	/* uip_len will contain the length of the actual TCP data. This is
+	calculated by subtracing the length of the TCP header (in
+	c) and the length of the IP header (20 bytes). */
+	uip_len = uip_len - c - UIP_IPH_LEN;
+
+	/* First, check if the sequence number of the incoming packet is
+	what we're expecting next. If not, we send out an ACK with the
+	correct numbers in. */
+	if( !(((uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_SYN_SENT) && ((BUF->flags & TCP_CTL) == (TCP_SYN | TCP_ACK))) )
+	{
+		if
+		(
+			(uip_len > 0 || ((BUF->flags & (TCP_SYN | TCP_FIN)) != 0)) &&
+			(
+				BUF->seqno[ 0 ] != uip_connr->rcv_nxt[ 0 ] ||
+				BUF->seqno[ 1 ] != uip_connr->rcv_nxt[ 1 ] ||
+				BUF->seqno[ 2 ] != uip_connr->rcv_nxt[ 2 ] ||
+				BUF->seqno[ 3 ] != uip_connr->rcv_nxt[ 3 ]
+			)
+		)
+		{
+			goto tcp_send_ack;
+		}
+	}
+
+	/* Next, check if the incoming segment acknowledges any outstanding
+	data. If so, we update the sequence number, reset the length of
+	the outstanding data, calculate RTT estimations, and reset the
+	retransmission timer. */
+	if( (BUF->flags & TCP_ACK) && uip_outstanding(uip_connr) )
+	{
+		uip_add32( uip_connr->snd_nxt, uip_connr->len );
+
+		if
+		(
+			BUF->ackno[ 0 ] == uip_acc32[ 0 ] &&
+			BUF->ackno[ 1 ] == uip_acc32[ 1 ] &&
+			BUF->ackno[ 2 ] == uip_acc32[ 2 ] &&
+			BUF->ackno[ 3 ] == uip_acc32[ 3 ]
+		)
+		{
+			/* Update sequence number. */
+			uip_connr->snd_nxt[ 0 ] = uip_acc32[ 0 ];
+			uip_connr->snd_nxt[ 1 ] = uip_acc32[ 1 ];
+			uip_connr->snd_nxt[ 2 ] = uip_acc32[ 2 ];
+			uip_connr->snd_nxt[ 3 ] = uip_acc32[ 3 ];
+
+			/* Do RTT estimation, unless we have done retransmissions. */
+			if( uip_connr->nrtx == 0 )
+			{
+				signed char m;
+				m = uip_connr->rto - uip_connr->timer;
+
+				/* This is taken directly from VJs original code in his paper */
+				m = m - ( uip_connr->sa >> 3 );
+				uip_connr->sa += m;
+				if( m < 0 )
+				{
+					m = -m;
+				}
+
+				m = m - ( uip_connr->sv >> 2 );
+				uip_connr->sv += m;
+				uip_connr->rto = ( uip_connr->sa >> 3 ) + uip_connr->sv;
+			}
+
+			/* Set the acknowledged flag. */
+			uip_flags = UIP_ACKDATA;
+
+			/* Reset the retransmission timer. */
+			uip_connr->timer = uip_connr->rto;
+
+			/* Reset length of outstanding data. */
+			uip_connr->len = 0;
+		}
+	}
+
+	/* Do different things depending on in what state the connection is. */
+	switch( uip_connr->tcpstateflags & UIP_TS_MASK )
+	{
+		/* CLOSED and LISTEN are not handled here. CLOSE_WAIT is not
+		implemented, since we force the application to close when the
+		peer sends a FIN (hence the application goes directly from
+		ESTABLISHED to LAST_ACK). */
+		case UIP_SYN_RCVD:
+			/* In SYN_RCVD we have sent out a SYNACK in response to a SYN, and
+	   		we are waiting for an ACK that acknowledges the data we sent
+	   		out the last time. Therefore, we want to have the UIP_ACKDATA
+	   		flag set. If so, we enter the ESTABLISHED state. */
+			if( uip_flags & UIP_ACKDATA )
+			{
+				uip_connr->tcpstateflags = UIP_ESTABLISHED;
+				uip_flags = UIP_CONNECTED;
+				uip_connr->len = 0;
+				if( uip_len > 0 )
+				{
+					uip_flags |= UIP_NEWDATA;
+					uip_add_rcv_nxt( uip_len );
+				}
+
+				uip_slen = 0;
+				UIP_APPCALL();
+				goto appsend;
+			}
+
+			goto drop;
+
+		#if UIP_ACTIVE_OPEN
+			case UIP_SYN_SENT:
+				/* In SYN_SENT, we wait for a SYNACK that is sent in response to
+				our SYN. The rcv_nxt is set to sequence number in the SYNACK
+				plus one, and we send an ACK. We move into the ESTABLISHED
+				state. */
+				if( (uip_flags & UIP_ACKDATA) && (BUF->flags & TCP_CTL) == (TCP_SYN | TCP_ACK) )
+				{
+					/* Parse the TCP MSS option, if present. */
+					if( (BUF->tcpoffset & 0xf0) > 0x50 )
+					{
+						for( c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2; )
+						{
+							opt = uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN + c];
+							if( opt == TCP_OPT_END )
+							{
+								/* End of options. */
+								break;
+							}
+							else if( opt == TCP_OPT_NOOP )
+							{
+								++c;
+
+								/* NOP option. */
+							}
+							else if( opt == TCP_OPT_MSS && uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == TCP_OPT_MSS_LEN )
+							{
+								/* An MSS option with the right option length. */
+								tmp16 = ( uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8 ) | uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 3 + c];
+								uip_connr->initialmss = uip_connr->mss = tmp16 > UIP_TCP_MSS ? UIP_TCP_MSS : tmp16;
+
+								/* And we are done processing options. */
+								break;
+							}
+							else
+							{
+								/* All other options have a length field, so that we easily
+								can skip past them. */
+								if( uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0 )
+								{
+									/* If the length field is zero, the options are malformed
+									and we don't process them further. */
+									break;
+								}
+
+								c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c];
+							}
+						}
+					}
+
+					uip_connr->tcpstateflags = UIP_ESTABLISHED;
+					uip_connr->rcv_nxt[ 0 ] = BUF->seqno[ 0 ];
+					uip_connr->rcv_nxt[ 1 ] = BUF->seqno[ 1 ];
+					uip_connr->rcv_nxt[ 2 ] = BUF->seqno[ 2 ];
+					uip_connr->rcv_nxt[ 3 ] = BUF->seqno[ 3 ];
+					uip_add_rcv_nxt( 1 );
+					uip_flags = UIP_CONNECTED | UIP_NEWDATA;
+					uip_connr->len = 0;
+					uip_len = 0;
+					uip_slen = 0;
+					UIP_APPCALL();
+					goto appsend;
+				}
+
+				/* Inform the application that the connection failed */
+				uip_flags = UIP_ABORT;
+				UIP_APPCALL();
+
+				/* The connection is closed after we send the RST */
+				uip_conn->tcpstateflags = UIP_CLOSED;
+				goto reset;
+		#endif /* UIP_ACTIVE_OPEN */
+
+		case UIP_ESTABLISHED:
+			/* In the ESTABLISHED state, we call upon the application to feed
+			data into the uip_buf. If the UIP_ACKDATA flag is set, the
+			application should put new data into the buffer, otherwise we are
+			retransmitting an old segment, and the application should put that
+			data into the buffer.
+
+			If the incoming packet is a FIN, we should close the connection on
+			this side as well, and we send out a FIN and enter the LAST_ACK
+			state. We require that there is no outstanding data; otherwise the
+			sequence numbers will be screwed up. */
+			if( BUF->flags & TCP_FIN && !(uip_connr->tcpstateflags & UIP_STOPPED) )
+			{
+				if( uip_outstanding(uip_connr) )
+				{
+					goto drop;
+				}
+
+				uip_add_rcv_nxt( 1 + uip_len );
+				uip_flags |= UIP_CLOSE;
+				if( uip_len > 0 )
+				{
+					uip_flags |= UIP_NEWDATA;
+				}
+
+				UIP_APPCALL();
+				uip_connr->len = 1;
+				uip_connr->tcpstateflags = UIP_LAST_ACK;
+				uip_connr->nrtx = 0;
+	tcp_send_finack:
+				BUF->flags = TCP_FIN | TCP_ACK;
+				goto tcp_send_nodata;
+			}
+
+			/* Check the URG flag. If this is set, the segment carries urgent
+			data that we must pass to the application. */
+			if( (BUF->flags & TCP_URG) != 0 )
+			{
+				#if UIP_URGDATA > 0
+					uip_urglen = ( BUF->urgp[ 0 ] << 8 ) | BUF->urgp[ 1 ];
+					if( uip_urglen > uip_len )
+					{
+						/* There is more urgent data in the next segment to come. */
+						uip_urglen = uip_len;
+					}
+
+					uip_add_rcv_nxt( uip_urglen );
+					uip_len -= uip_urglen;
+					uip_urgdata = uip_appdata;
+					uip_appdata += uip_urglen;
+					}
+					else
+					{
+					uip_urglen = 0;
+				#else /* UIP_URGDATA > 0 */
+					uip_appdata = ( ( char * ) uip_appdata ) + ( (BUF->urgp[ 0 ] << 8) | BUF->urgp[ 1 ] );
+					uip_len -= ( BUF->urgp[ 0 ] << 8 ) | BUF->urgp[ 1 ];
+				#endif /* UIP_URGDATA > 0 */
+			}
+
+			/* If uip_len > 0 we have TCP data in the packet, and we flag this
+			by setting the UIP_NEWDATA flag and update the sequence number
+			we acknowledge. If the application has stopped the dataflow
+			using uip_stop(), we must not accept any data packets from the
+			remote host. */
+			if( uip_len > 0 && !(uip_connr->tcpstateflags & UIP_STOPPED) )
+			{
+				uip_flags |= UIP_NEWDATA;
+				uip_add_rcv_nxt( uip_len );
+			}
+
+			/* Check if the available buffer space advertised by the other end
+			is smaller than the initial MSS for this connection. If so, we
+			set the current MSS to the window size to ensure that the
+			application does not send more data than the other end can
+			handle.
+
+			If the remote host advertises a zero window, we set the MSS to
+			the initial MSS so that the application will send an entire MSS
+			of data. This data will not be acknowledged by the receiver,
+			and the application will retransmit it. This is called the
+			"persistent timer" and uses the retransmission mechanim.
+			*/
+			tmp16 = ( (u16_t) BUF->wnd[ 0 ] << 8 ) + ( u16_t ) BUF->wnd[ 1 ];
+			if( tmp16 > uip_connr->initialmss || tmp16 == 0 )
+			{
+				tmp16 = uip_connr->initialmss;
+			}
+
+			uip_connr->mss = tmp16;
+
+			/* If this packet constitutes an ACK for outstanding data (flagged
+			by the UIP_ACKDATA flag, we should call the application since it
+			might want to send more data. If the incoming packet had data
+			from the peer (as flagged by the UIP_NEWDATA flag), the
+			application must also be notified.
+
+			When the application is called, the global variable uip_len
+			contains the length of the incoming data. The application can
+			access the incoming data through the global pointer
+			uip_appdata, which usually points UIP_IPTCPH_LEN + UIP_LLH_LEN
+			bytes into the uip_buf array.
+
+			If the application wishes to send any data, this data should be
+			put into the uip_appdata and the length of the data should be
+			put into uip_len. If the application don't have any data to
+			send, uip_len must be set to 0. */
+			if( uip_flags & (UIP_NEWDATA | UIP_ACKDATA) )
+			{
+				uip_slen = 0;
+				UIP_APPCALL();
+
+appsend:
+				if( uip_flags & UIP_ABORT )
+				{
+					uip_slen = 0;
+					uip_connr->tcpstateflags = UIP_CLOSED;
+					BUF->flags = TCP_RST | TCP_ACK;
+					goto tcp_send_nodata;
+				}
+
+				if( uip_flags & UIP_CLOSE )
+				{
+					uip_slen = 0;
+					uip_connr->len = 1;
+					uip_connr->tcpstateflags = UIP_FIN_WAIT_1;
+					uip_connr->nrtx = 0;
+					BUF->flags = TCP_FIN | TCP_ACK;
+					goto tcp_send_nodata;
+				}
+
+				/* If uip_slen > 0, the application has data to be sent. */
+				if( uip_slen > 0 )
+				{
+					/* If the connection has acknowledged data, the contents of
+	   				the ->len variable should be discarded. */
+					if( (uip_flags & UIP_ACKDATA) != 0 )
+					{
+						uip_connr->len = 0;
+					}
+
+					/* If the ->len variable is non-zero the connection has
+	   				already data in transit and cannot send anymore right
+	   				now. */
+					if( uip_connr->len == 0 )
+					{
+						/* The application cannot send more than what is allowed by
+		 				the mss (the minumum of the MSS and the available
+		 				window). */
+						if( uip_slen > uip_connr->mss )
+						{
+							uip_slen = uip_connr->mss;
+						}
+
+						/* Remember how much data we send out now so that we know
+		 				when everything has been acknowledged. */
+						uip_connr->len = uip_slen;
+					}
+					else
+					{
+						/* If the application already had unacknowledged data, we
+		 				make sure that the application does not send (i.e.,
+		 				retransmit) out more than it previously sent out. */
+						uip_slen = uip_connr->len;
+					}
+				}
+
+				uip_connr->nrtx = 0;
+apprexmit:
+				uip_appdata = uip_sappdata;
+
+				/* If the application has data to be sent, or if the incoming
+		 		packet had new data in it, we must send out a packet. */
+				if( uip_slen > 0 && uip_connr->len > 0 )
+				{
+					/* Add the length of the IP and TCP headers. */
+					uip_len = uip_connr->len + UIP_TCPIP_HLEN;
+
+					/* We always set the ACK flag in response packets. */
+					BUF->flags = TCP_ACK | TCP_PSH;
+
+					/* Send the packet. */
+					goto tcp_send_noopts;
+				}
+
+				/* If there is no data to send, just send out a pure ACK if
+				there is newdata. */
+				if( uip_flags & UIP_NEWDATA )
+				{
+					uip_len = UIP_TCPIP_HLEN;
+					BUF->flags = TCP_ACK;
+					goto tcp_send_noopts;
+				}
+			}
+
+			goto drop;
+
+		case UIP_LAST_ACK:
+			/* We can close this connection if the peer has acknowledged our
+			FIN. This is indicated by the UIP_ACKDATA flag. */
+			if( uip_flags & UIP_ACKDATA )
+			{
+				uip_connr->tcpstateflags = UIP_CLOSED;
+				uip_flags = UIP_CLOSE;
+				UIP_APPCALL();
+			}
+
+			break;
+
+		case UIP_FIN_WAIT_1:
+			/* The application has closed the connection, but the remote host
+			hasn't closed its end yet. Thus we do nothing but wait for a
+			FIN from the other side. */
+			if( uip_len > 0 )
+			{
+				uip_add_rcv_nxt( uip_len );
+			}
+
+			if( BUF->flags & TCP_FIN )
+			{
+				if( uip_flags & UIP_ACKDATA )
+				{
+					uip_connr->tcpstateflags = UIP_TIME_WAIT;
+					uip_connr->timer = 0;
+					uip_connr->len = 0;
+				}
+				else
+				{
+					uip_connr->tcpstateflags = UIP_CLOSING;
+				}
+
+				uip_add_rcv_nxt( 1 );
+				uip_flags = UIP_CLOSE;
+				UIP_APPCALL();
+				goto tcp_send_ack;
+			}
+			else if( uip_flags & UIP_ACKDATA )
+			{
+				uip_connr->tcpstateflags = UIP_FIN_WAIT_2;
+				uip_connr->len = 0;
+				goto drop;
+			}
+
+			if( uip_len > 0 )
+			{
+				goto tcp_send_ack;
+			}
+
+			goto drop;
+
+		case UIP_FIN_WAIT_2:
+			if( uip_len > 0 )
+			{
+				uip_add_rcv_nxt( uip_len );
+			}
+
+			if( BUF->flags & TCP_FIN )
+			{
+				uip_connr->tcpstateflags = UIP_TIME_WAIT;
+				uip_connr->timer = 0;
+				uip_add_rcv_nxt( 1 );
+				uip_flags = UIP_CLOSE;
+				UIP_APPCALL();
+				goto tcp_send_ack;
+			}
+
+			if( uip_len > 0 )
+			{
+				goto tcp_send_ack;
+			}
+
+			goto drop;
+
+		case UIP_TIME_WAIT:
+			goto tcp_send_ack;
+
+		case UIP_CLOSING:
+			if( uip_flags & UIP_ACKDATA )
+			{
+				uip_connr->tcpstateflags = UIP_TIME_WAIT;
+				uip_connr->timer = 0;
+			}
+	}
+
+	goto drop;
+
+	/* We jump here when we are ready to send the packet, and just want
+	 to set the appropriate TCP sequence numbers in the TCP header. */
+tcp_send_ack:
+	BUF->flags = TCP_ACK;
+
+tcp_send_nodata:
+	uip_len = UIP_IPTCPH_LEN;
+
+tcp_send_noopts:
+	BUF->tcpoffset = ( UIP_TCPH_LEN / 4 ) << 4;
+
+	/* We're done with the input processing. We are now ready to send a
+	reply. Our job is to fill in all the fields of the TCP and IP
+	headers before calculating the checksum and finally send the
+	packet. */
+tcp_send:
+	BUF->ackno[ 0 ] = uip_connr->rcv_nxt[ 0 ];
+	BUF->ackno[ 1 ] = uip_connr->rcv_nxt[ 1 ];
+	BUF->ackno[ 2 ] = uip_connr->rcv_nxt[ 2 ];
+	BUF->ackno[ 3 ] = uip_connr->rcv_nxt[ 3 ];
+
+	BUF->seqno[ 0 ] = uip_connr->snd_nxt[ 0 ];
+	BUF->seqno[ 1 ] = uip_connr->snd_nxt[ 1 ];
+	BUF->seqno[ 2 ] = uip_connr->snd_nxt[ 2 ];
+	BUF->seqno[ 3 ] = uip_connr->snd_nxt[ 3 ];
+
+	BUF->proto = UIP_PROTO_TCP;
+
+	BUF->srcport = uip_connr->lport;
+	BUF->destport = uip_connr->rport;
+
+	uip_ipaddr_copy( &BUF->srcipaddr, &uip_hostaddr );
+	uip_ipaddr_copy( &BUF->destipaddr, &uip_connr->ripaddr );
+
+	if( uip_connr->tcpstateflags & UIP_STOPPED )
+	{
+		/* If the connection has issued uip_stop(), we advertise a zero
+		window so that the remote host will stop sending data. */
+		BUF->wnd[ 0 ] = BUF->wnd[ 1 ] = 0;
+	}
+	else
+	{
+		BUF->wnd[ 0 ] = ( (UIP_RECEIVE_WINDOW) >> 8 );
+		BUF->wnd[ 1 ] = ( (UIP_RECEIVE_WINDOW) & 0xff );
+	}
+
+tcp_send_noconn:
+
+	BUF->ttl = UIP_TTL;
+
+	#if UIP_CONF_IPV6
+		/* For IPv6, the IP length field does not include the IPv6 IP header
+		 length. */
+		BUF->len[ 0 ] = ( (uip_len - UIP_IPH_LEN) >> 8 );
+		BUF->len[ 1 ] = ( (uip_len - UIP_IPH_LEN) & 0xff );
+	#else /* UIP_CONF_IPV6 */
+		BUF->len[ 0 ] = ( uip_len >> 8 );
+		BUF->len[ 1 ] = ( uip_len & 0xff );
+	#endif /* UIP_CONF_IPV6 */
+
+	BUF->urgp[ 0 ] = BUF->urgp[ 1 ] = 0;
+
+	/* Calculate TCP checksum. */
+	BUF->tcpchksum = 0;
+	BUF->tcpchksum = ~( uip_tcpchksum() );
+
+ip_send_nolen:
+	#if UIP_CONF_IPV6
+		BUF->vtc = 0x60;
+		BUF->tcflow = 0x00;
+		BUF->flow = 0x00;
+	#else /* UIP_CONF_IPV6 */
+		BUF->vhl = 0x45;
+		BUF->tos = 0;
+		BUF->ipoffset[ 0 ] = BUF->ipoffset[ 1 ] = 0;
+		++ipid;
+		BUF->ipid[ 0 ] = ipid >> 8;
+		BUF->ipid[ 1 ] = ipid & 0xff;
+
+		/* Calculate IP checksum. */
+		BUF->ipchksum = 0;
+		BUF->ipchksum = ~( uip_ipchksum() );
+
+		//DEBUG_PRINTF( "uip ip_send_nolen: chkecum 0x%04x\n", uip_ipchksum() );
+	#endif /* UIP_CONF_IPV6 */
+
+	UIP_STAT( ++uip_stat.tcp.sent );
+
+	#if UIP_CONF_IPV6
+send :
+	#endif /* UIP_CONF_IPV6 */
+
+	//DEBUG_PRINTF( "Sending packet with length %d (%d)\n", uip_len, (BUF->len[ 0 ] << 8) | BUF->len[ 1 ] );
+	UIP_STAT( ++uip_stat.ip.sent );
+
+	/* Return and let the caller do the actual transmission. */
+	uip_flags = 0;
+	return;
+
+drop:
+	uip_len = 0;
+	uip_flags = 0;
+	return;
+}
+/*---------------------------------------------------------------------------*/
+
+u16_t htons( u16_t val )
+{
+	return HTONS( val );
+}
+
+u32_t htonl( u32_t val )
+{
+	return HTONL( val );
+}
+/*---------------------------------------------------------------------------*/
+
+void uip_send( const void *data, int len )
+{
+	int copylen;
+
+	#define MIN( a, b ) ( (a) < (b) ? (a) : (b) )
+
+	copylen = MIN( len, UIP_BUFSIZE - UIP_LLH_LEN - UIP_TCPIP_HLEN - ( int )
+					   (( char * ) uip_sappdata - ( char * ) &uip_buf[UIP_LLH_LEN + UIP_TCPIP_HLEN]) );
+	if( copylen > 0 )
+	{
+		uip_slen = copylen;
+		if( data != uip_sappdata )
+		{
+			memcpy( uip_sappdata, (data), uip_slen );
+		}
+	}
+}
+/*---------------------------------------------------------------------------*/
+
+/** @} */
+#endif /* UIP_CONF_IPV6 */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/uip_arp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/uip_arp.c
new file mode 100644
index 0000000..ab84419
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/FreeTCPIP/uip_arp.c
@@ -0,0 +1,475 @@
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \defgroup uiparp uIP Address Resolution Protocol
+ * @{
+ *
+ * The Address Resolution Protocol ARP is used for mapping between IP
+ * addresses and link level addresses such as the Ethernet MAC
+ * addresses. ARP uses broadcast queries to ask for the link level
+ * address of a known IP address and the host which is configured with
+ * the IP address for which the query was meant, will respond with its
+ * link level address.
+ *
+ * \note This ARP implementation only supports Ethernet.
+ */
+
+/**
+ * \file
+ * Implementation of the ARP Address Resolution Protocol.
+ * \author Adam Dunkels 
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip_arp.c,v 1.5 2008/02/07 01:35:00 adamdunkels Exp $
+ *
+ */
+#include "net/uip_arp.h"
+
+#include 
+
+#include "net/pack_struct_start.h"
+struct arp_hdr
+{
+	struct uip_eth_hdr	ethhdr;
+	u16_t				hwtype;
+	u16_t				protocol;
+	u8_t				hwlen;
+	u8_t				protolen;
+	u16_t				opcode;
+	struct uip_eth_addr shwaddr;
+	uip_ipaddr_t		sipaddr;
+	struct uip_eth_addr dhwaddr;
+	uip_ipaddr_t		dipaddr;
+}
+
+#include "net/pack_struct_end.h"
+
+#include "net/pack_struct_start.h"
+
+struct ethip_hdr
+{
+	struct uip_eth_hdr	ethhdr;
+
+	/* IP header. */
+	u8_t				vhl, tos, len[2], ipid[2], ipoffset[2], ttl, proto;
+	u16_t				ipchksum;
+	uip_ipaddr_t		srcipaddr, destipaddr;
+}
+
+#include "net/pack_struct_end.h"
+
+#define ARP_REQUEST		1
+#define ARP_REPLY		2
+
+#define ARP_HWTYPE_ETH	1
+
+struct arp_entry
+{
+	uip_ipaddr_t		ipaddr;
+	struct uip_eth_addr ethaddr;
+	u8_t				time;
+};
+
+static const struct uip_eth_addr	broadcast_ethaddr = { { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff } };
+
+static struct arp_entry				arp_table[UIP_ARPTAB_SIZE];
+static uip_ipaddr_t					ipaddr;
+static u8_t							i, c;
+
+static u8_t							arptime;
+static u8_t							tmpage;
+
+#define BUF		( ( struct arp_hdr * ) &uip_buf[0] )
+#define IPBUF	( ( struct ethip_hdr * ) &uip_buf[0] )
+
+#ifdef DEBUG
+	#undef DEBUG
+#endif
+#define DEBUG	0
+#if DEBUG
+#include 
+#define PRINTF( ... )	printf( __VA_ARGS__ )
+#else
+
+//#define PRINTF( ... )
+#endif
+
+/*-----------------------------------------------------------------------------------*/
+
+/**
+ * Initialize the ARP module.
+ *
+ */
+
+/*-----------------------------------------------------------------------------------*/
+void uip_arp_init( void )
+{
+	for( i = 0; i < UIP_ARPTAB_SIZE; ++i )
+	{
+		memset( &arp_table[i].ipaddr, 0, 4 );
+	}
+}
+
+/*-----------------------------------------------------------------------------------*/
+
+/**
+ * Periodic ARP processing function.
+ *
+ * This function performs periodic timer processing in the ARP module
+ * and should be called at regular intervals. The recommended interval
+ * is 10 seconds between the calls.
+ *
+ */
+
+/*-----------------------------------------------------------------------------------*/
+void uip_arp_timer( void )
+{
+	struct arp_entry	*tabptr;
+
+	++arptime;
+	for( i = 0; i < UIP_ARPTAB_SIZE; ++i )
+	{
+		tabptr = &arp_table[i];
+		if( uip_ipaddr_cmp(&tabptr->ipaddr, &uip_all_zeroes_addr) && arptime - tabptr->time >= UIP_ARP_MAXAGE )
+		{
+			memset( &tabptr->ipaddr, 0, 4 );
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------------------*/
+static void uip_arp_update( uip_ipaddr_t *ipaddr, struct uip_eth_addr *ethaddr )
+{
+	register struct arp_entry	*tabptr;
+
+	/* Walk through the ARP mapping table and try to find an entry to
+     update. If none is found, the IP -> MAC address mapping is
+     inserted in the ARP table. */
+	for( i = 0; i < UIP_ARPTAB_SIZE; ++i )
+	{
+		tabptr = &arp_table[i];
+
+		/* Only check those entries that are actually in use. */
+		if( !uip_ipaddr_cmp(&tabptr->ipaddr, &uip_all_zeroes_addr) )
+		{
+			/* Check if the source IP address of the incoming packet matches
+         the IP address in this ARP table entry. */
+			if( uip_ipaddr_cmp(ipaddr, &tabptr->ipaddr) )
+			{
+				/* An old entry found, update this and return. */
+				memcpy( tabptr->ethaddr.addr, ethaddr->addr, 6 );
+				tabptr->time = arptime;
+
+				return;
+			}
+		}
+	}
+
+	/* If we get here, no existing ARP table entry was found, so we
+     create one. */
+
+	/* First, we try to find an unused entry in the ARP table. */
+	for( i = 0; i < UIP_ARPTAB_SIZE; ++i )
+	{
+		tabptr = &arp_table[i];
+		if( uip_ipaddr_cmp(&tabptr->ipaddr, &uip_all_zeroes_addr) )
+		{
+			break;
+		}
+	}
+
+	/* If no unused entry is found, we try to find the oldest entry and
+     throw it away. */
+	if( i == UIP_ARPTAB_SIZE )
+	{
+		tmpage = 0;
+		c = 0;
+		for( i = 0; i < UIP_ARPTAB_SIZE; ++i )
+		{
+			tabptr = &arp_table[i];
+			if( arptime - tabptr->time > tmpage )
+			{
+				tmpage = arptime - tabptr->time;
+				c = i;
+			}
+		}
+
+		i = c;
+		tabptr = &arp_table[i];
+	}
+
+	/* Now, i is the ARP table entry which we will fill with the new
+     information. */
+	uip_ipaddr_copy( &tabptr->ipaddr, ipaddr );
+	memcpy( tabptr->ethaddr.addr, ethaddr->addr, 6 );
+	tabptr->time = arptime;
+}
+
+/*-----------------------------------------------------------------------------------*/
+
+/**
+ * ARP processing for incoming IP packets
+ *
+ * This function should be called by the device driver when an IP
+ * packet has been received. The function will check if the address is
+ * in the ARP cache, and if so the ARP cache entry will be
+ * refreshed. If no ARP cache entry was found, a new one is created.
+ *
+ * This function expects an IP packet with a prepended Ethernet header
+ * in the uip_buf[] buffer, and the length of the packet in the global
+ * variable uip_len.
+ */
+
+/*-----------------------------------------------------------------------------------*/
+#if 0
+void uip_arp_ipin( void )
+{
+	uip_len -= sizeof( struct uip_eth_hdr );
+
+	/* Only insert/update an entry if the source IP address of the
+     incoming IP packet comes from a host on the local network. */
+	if( (IPBUF->srcipaddr[0] & uip_netmask[0]) != (uip_hostaddr[0] & uip_netmask[0]) )
+	{
+		return;
+	}
+
+	if( (IPBUF->srcipaddr[1] & uip_netmask[1]) != (uip_hostaddr[1] & uip_netmask[1]) )
+	{
+		return;
+	}
+
+	uip_arp_update( IPBUF->srcipaddr, &(IPBUF->ethhdr.src) );
+
+	return;
+}
+
+#endif /* 0 */
+
+/*-----------------------------------------------------------------------------------*/
+
+/**
+ * ARP processing for incoming ARP packets.
+ *
+ * This function should be called by the device driver when an ARP
+ * packet has been received. The function will act differently
+ * depending on the ARP packet type: if it is a reply for a request
+ * that we previously sent out, the ARP cache will be filled in with
+ * the values from the ARP reply. If the incoming ARP packet is an ARP
+ * request for our IP address, an ARP reply packet is created and put
+ * into the uip_buf[] buffer.
+ *
+ * When the function returns, the value of the global variable uip_len
+ * indicates whether the device driver should send out a packet or
+ * not. If uip_len is zero, no packet should be sent. If uip_len is
+ * non-zero, it contains the length of the outbound packet that is
+ * present in the uip_buf[] buffer.
+ *
+ * This function expects an ARP packet with a prepended Ethernet
+ * header in the uip_buf[] buffer, and the length of the packet in the
+ * global variable uip_len.
+ */
+
+/*-----------------------------------------------------------------------------------*/
+void uip_arp_arpin( void )
+{
+	if( uip_len < sizeof(struct arp_hdr) )
+	{
+		uip_len = 0;
+		return;
+	}
+
+	uip_len = 0;
+
+	switch( BUF->opcode )
+	{
+		case HTONS( ARP_REQUEST ):
+			/* ARP request. If it asked for our address, we send out a
+       		reply. */
+
+			/*    if(BUF->dipaddr[0] == uip_hostaddr[0] &&
+	  		BUF->dipaddr[1] == uip_hostaddr[1]) {*/
+
+			//PRINTF( "uip_arp_arpin: request for %d.%d.%d.%d (we are %d.%d.%d.%d)\n", BUF->dipaddr.u8[0], BUF->dipaddr.u8[1], BUF->dipaddr.u8[2],			
+			//BUF->dipaddr.u8[3], uip_hostaddr.u8[0], uip_hostaddr.u8[1], uip_hostaddr.u8[2], uip_hostaddr.u8[3] );
+			if( uip_ipaddr_cmp(&BUF->dipaddr, &uip_hostaddr) )
+			{
+				/* First, we register the one who made the request in our ARP
+				table, since it is likely that we will do more communication
+				with this host in the future. */
+				uip_arp_update( &BUF->sipaddr, &BUF->shwaddr );
+
+				BUF->opcode = HTONS( ARP_REPLY );
+
+				memcpy( BUF->dhwaddr.addr, BUF->shwaddr.addr, 6 );
+				memcpy( BUF->shwaddr.addr, uip_ethaddr.addr, 6 );
+				memcpy( BUF->ethhdr.src.addr, uip_ethaddr.addr, 6 );
+				memcpy( BUF->ethhdr.dest.addr, BUF->dhwaddr.addr, 6 );
+
+				uip_ipaddr_copy( &BUF->dipaddr, &BUF->sipaddr );
+				uip_ipaddr_copy( &BUF->sipaddr, &uip_hostaddr );
+
+				BUF->ethhdr.type = HTONS( UIP_ETHTYPE_ARP );
+				uip_len = sizeof( struct arp_hdr );
+			}
+
+			break;
+
+		case HTONS( ARP_REPLY ):
+			/* ARP reply. We insert or update the ARP table if it was meant
+			for us. */
+			if( uip_ipaddr_cmp(&BUF->dipaddr, &uip_hostaddr) )
+			{
+				uip_arp_update( &BUF->sipaddr, &BUF->shwaddr );
+			}
+
+			break;
+	}
+
+	return;
+}
+
+/*-----------------------------------------------------------------------------------*/
+
+/**
+ * Prepend Ethernet header to an outbound IP packet and see if we need
+ * to send out an ARP request.
+ *
+ * This function should be called before sending out an IP packet. The
+ * function checks the destination IP address of the IP packet to see
+ * what Ethernet MAC address that should be used as a destination MAC
+ * address on the Ethernet.
+ *
+ * If the destination IP address is in the local network (determined
+ * by logical ANDing of netmask and our IP address), the function
+ * checks the ARP cache to see if an entry for the destination IP
+ * address is found. If so, an Ethernet header is prepended and the
+ * function returns. If no ARP cache entry is found for the
+ * destination IP address, the packet in the uip_buf[] is replaced by
+ * an ARP request packet for the IP address. The IP packet is dropped
+ * and it is assumed that they higher level protocols (e.g., TCP)
+ * eventually will retransmit the dropped packet.
+ *
+ * If the destination IP address is not on the local network, the IP
+ * address of the default router is used instead.
+ *
+ * When the function returns, a packet is present in the uip_buf[]
+ * buffer, and the length of the packet is in the global variable
+ * uip_len.
+ */
+
+/*-----------------------------------------------------------------------------------*/
+void uip_arp_out( void )
+{
+	struct arp_entry	*tabptr;
+
+	/* Find the destination IP address in the ARP table and construct
+     the Ethernet header. If the destination IP addres isn't on the
+     local network, we use the default router's IP address instead.
+
+     If not ARP table entry is found, we overwrite the original IP
+     packet with an ARP request for the IP address. */
+
+	/* First check if destination is a local broadcast. */
+	if( uip_ipaddr_cmp(&IPBUF->destipaddr, &uip_broadcast_addr) )
+	{
+		memcpy( IPBUF->ethhdr.dest.addr, broadcast_ethaddr.addr, 6 );
+	}
+	else
+	{
+		/* Check if the destination address is on the local network. */
+		if( !uip_ipaddr_maskcmp(&IPBUF->destipaddr, &uip_hostaddr, &uip_netmask) )
+		{
+			/* Destination address was not on the local network, so we need to
+	 use the default router's IP address instead of the destination
+	 address when determining the MAC address. */
+			uip_ipaddr_copy( &ipaddr, &uip_draddr );
+		}
+		else
+		{
+			/* Else, we use the destination IP address. */
+			uip_ipaddr_copy( &ipaddr, &IPBUF->destipaddr );
+		}
+
+		for( i = 0; i < UIP_ARPTAB_SIZE; ++i )
+		{
+			tabptr = &arp_table[i];
+			if( uip_ipaddr_cmp(&ipaddr, &tabptr->ipaddr) )
+			{
+				break;
+			}
+		}
+
+		if( i == UIP_ARPTAB_SIZE )
+		{
+			/* The destination address was not in our ARP table, so we
+	 overwrite the IP packet with an ARP request. */
+			memset( BUF->ethhdr.dest.addr, 0xff, 6 );
+			memset( BUF->dhwaddr.addr, 0x00, 6 );
+			memcpy( BUF->ethhdr.src.addr, uip_ethaddr.addr, 6 );
+			memcpy( BUF->shwaddr.addr, uip_ethaddr.addr, 6 );
+
+			uip_ipaddr_copy( &BUF->dipaddr, &ipaddr );
+			uip_ipaddr_copy( &BUF->sipaddr, &uip_hostaddr );
+			BUF->opcode = HTONS( ARP_REQUEST ); /* ARP request. */
+			BUF->hwtype = HTONS( ARP_HWTYPE_ETH );
+			BUF->protocol = HTONS( UIP_ETHTYPE_IP );
+			BUF->hwlen = 6;
+			BUF->protolen = 4;
+			BUF->ethhdr.type = HTONS( UIP_ETHTYPE_ARP );
+
+			uip_appdata = &uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN];
+
+			uip_len = sizeof( struct arp_hdr );
+			return;
+		}
+
+		/* Build an ethernet header. */
+		memcpy( IPBUF->ethhdr.dest.addr, tabptr->ethaddr.addr, 6 );
+	}
+
+	memcpy( IPBUF->ethhdr.src.addr, uip_ethaddr.addr, 6 );
+
+	IPBUF->ethhdr.type = HTONS( UIP_ETHTYPE_IP );
+
+	uip_len += sizeof( struct uip_eth_hdr );
+}
+
+/*-----------------------------------------------------------------------------------*/
+
+/** @} */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/Legacy-directory-only-see-FreeRTOS-Plus-TCP.url b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/Legacy-directory-only-see-FreeRTOS-Plus-TCP.url
new file mode 100644
index 0000000..d9919c9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/Legacy-directory-only-see-FreeRTOS-Plus-TCP.url
@@ -0,0 +1,6 @@
+[InternetShortcut]
+URL=http://www.freertos.org/tcp
+IDList=
+HotKey=0
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,2
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/FILES b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/FILES
new file mode 100644
index 0000000..2b65731
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/FILES
@@ -0,0 +1,13 @@
+api/      - The code for the high-level wrapper API. Not needed if
+            you use the lowel-level call-back/raw API.
+
+core/     - The core of the TPC/IP stack; protocol implementations,
+            memory and buffer management, and the low-level raw API.
+	    
+include/  - lwIP include files.
+
+netif/    - Generic network interface device drivers are kept here,
+            as well as the ARP module.
+
+For more information on the various subdirectories, check the FILES
+file in each directory.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/api/api_lib.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/api/api_lib.c
new file mode 100644
index 0000000..917a2ec
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/api/api_lib.c
@@ -0,0 +1,722 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* This is the part of the API that is linked with
+   the application */
+
+#include "lwip/opt.h"
+#include "lwip/api.h"
+#include "lwip/api_msg.h"
+#include "lwip/memp.h"
+
+
+struct
+netbuf *netbuf_new(void)
+{
+  struct netbuf *buf;
+
+  buf = memp_malloc(MEMP_NETBUF);
+  if (buf != NULL) {
+    buf->p = NULL;
+    buf->ptr = NULL;
+    return buf;
+  } else {
+    return NULL;
+  }
+}
+
+void
+netbuf_delete(struct netbuf *buf)
+{
+  if (buf != NULL) {
+    if (buf->p != NULL) {
+      pbuf_free(buf->p);
+      buf->p = buf->ptr = NULL;
+    }
+    memp_free(MEMP_NETBUF, buf);
+  }
+}
+
+void *
+netbuf_alloc(struct netbuf *buf, u16_t size)
+{
+  /* Deallocate any previously allocated memory. */
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = pbuf_alloc(PBUF_TRANSPORT, size, PBUF_RAM);
+  if (buf->p == NULL) {
+     return NULL;
+  }
+  buf->ptr = buf->p;
+  return buf->p->payload;
+}
+
+void
+netbuf_free(struct netbuf *buf)
+{
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = buf->ptr = NULL;
+}
+
+void
+netbuf_ref(struct netbuf *buf, void *dataptr, u16_t size)
+{
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF);
+  buf->p->payload = dataptr;
+  buf->p->len = buf->p->tot_len = size;
+  buf->ptr = buf->p;
+}
+
+void
+netbuf_chain(struct netbuf *head, struct netbuf *tail)
+{
+  pbuf_chain(head->p, tail->p);
+  head->ptr = head->p;
+  memp_free(MEMP_NETBUF, tail);
+}
+
+u16_t
+netbuf_len(struct netbuf *buf)
+{
+  return buf->p->tot_len;
+}
+
+err_t
+netbuf_data(struct netbuf *buf, void **dataptr, u16_t *len)
+{
+  if (buf->ptr == NULL) {
+    return ERR_BUF;
+  }
+  *dataptr = buf->ptr->payload;
+  *len = buf->ptr->len;
+  return ERR_OK;
+}
+
+s8_t
+netbuf_next(struct netbuf *buf)
+{
+  if (buf->ptr->next == NULL) {
+    return -1;
+  }
+  buf->ptr = buf->ptr->next;
+  if (buf->ptr->next == NULL) {
+    return 1;
+  }
+  return 0;
+}
+
+void
+netbuf_first(struct netbuf *buf)
+{
+  buf->ptr = buf->p;
+}
+
+void
+netbuf_copy_partial(struct netbuf *buf, void *dataptr, u16_t len, u16_t offset)
+{
+  struct pbuf *p;
+  u16_t i, left;
+
+  left = 0;
+
+  if(buf == NULL || dataptr == NULL) {
+    return;
+  }
+  
+  /* This implementation is bad. It should use bcopy
+     instead. */
+  for(p = buf->p; left < len && p != NULL; p = p->next) {
+    if (offset != 0 && offset >= p->len) {
+      offset -= p->len;
+    } else {    
+      for(i = offset; i < p->len; ++i) {
+  ((u8_t *)dataptr)[left] = ((u8_t *)p->payload)[i];
+  if (++left >= len) {
+    return;
+  }
+      }
+      offset = 0;
+    }
+  }
+}
+
+void
+netbuf_copy(struct netbuf *buf, void *dataptr, u16_t len)
+{
+  netbuf_copy_partial(buf, dataptr, len, 0);
+}
+
+struct ip_addr *
+netbuf_fromaddr(struct netbuf *buf)
+{
+  return buf->fromaddr;
+}
+
+u16_t
+netbuf_fromport(struct netbuf *buf)
+{
+  return buf->fromport;
+}
+
+struct
+netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u16_t proto,
+                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len))
+{
+  struct netconn *conn;
+  struct api_msg *msg;
+
+  conn = memp_malloc(MEMP_NETCONN);
+  if (conn == NULL) {
+    return NULL;
+  }
+  
+  conn->err = ERR_OK;
+  conn->type = t;
+  conn->pcb.tcp = NULL;
+
+  if ((conn->mbox = sys_mbox_new()) == SYS_MBOX_NULL) {
+    memp_free(MEMP_NETCONN, conn);
+    return NULL;
+  }
+  conn->recvmbox = SYS_MBOX_NULL;
+  conn->acceptmbox = SYS_MBOX_NULL;
+  conn->sem = sys_sem_new(0);
+  if (conn->sem == SYS_SEM_NULL) {
+    memp_free(MEMP_NETCONN, conn);
+    return NULL;
+  }
+  conn->state = NETCONN_NONE;
+  conn->socket = 0;
+  conn->callback = callback;
+  conn->recv_avail = 0;
+
+  if((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    memp_free(MEMP_NETCONN, conn);
+    return NULL;
+  }
+  
+  msg->type = API_MSG_NEWCONN;
+  msg->msg.msg.bc.port = proto; /* misusing the port field */
+  msg->msg.conn = conn;
+  api_msg_post(msg);  
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+
+  if ( conn->err != ERR_OK ) {
+    memp_free(MEMP_NETCONN, conn);
+    return NULL;
+  }
+
+  return conn;
+}
+
+
+struct
+netconn *netconn_new(enum netconn_type t)
+{
+  return netconn_new_with_proto_and_callback(t,0,NULL);
+}
+
+struct
+netconn *netconn_new_with_callback(enum netconn_type t,
+                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len))
+{
+  return netconn_new_with_proto_and_callback(t,0,callback);
+}
+
+
+err_t
+netconn_delete(struct netconn *conn)
+{
+  struct api_msg *msg;
+  void *mem;
+  
+  if (conn == NULL) {
+    return ERR_OK;
+  }
+  
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return ERR_MEM;
+  }
+  
+  msg->type = API_MSG_DELCONN;
+  msg->msg.conn = conn;
+  api_msg_post(msg);  
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+
+  /* Drain the recvmbox. */
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+    while (sys_arch_mbox_fetch(conn->recvmbox, &mem, 1) != SYS_ARCH_TIMEOUT) {
+      if (conn->type == NETCONN_TCP) {
+        if(mem != NULL)
+          pbuf_free((struct pbuf *)mem);
+      } else {
+        netbuf_delete((struct netbuf *)mem);
+      }
+    }
+    sys_mbox_free(conn->recvmbox);
+    conn->recvmbox = SYS_MBOX_NULL;
+  }
+ 
+
+  /* Drain the acceptmbox. */
+  if (conn->acceptmbox != SYS_MBOX_NULL) {
+    while (sys_arch_mbox_fetch(conn->acceptmbox, &mem, 1) != SYS_ARCH_TIMEOUT) {
+      netconn_delete((struct netconn *)mem);
+    }
+    
+    sys_mbox_free(conn->acceptmbox);
+    conn->acceptmbox = SYS_MBOX_NULL;
+  }
+
+  sys_mbox_free(conn->mbox);
+  conn->mbox = SYS_MBOX_NULL;
+  if (conn->sem != SYS_SEM_NULL) {
+    sys_sem_free(conn->sem);
+  }
+  /*  conn->sem = SYS_SEM_NULL;*/
+  memp_free(MEMP_NETCONN, conn);
+  return ERR_OK;
+}
+
+enum netconn_type
+netconn_type(struct netconn *conn)
+{
+  return conn->type;
+}
+
+err_t
+netconn_peer(struct netconn *conn, struct ip_addr *addr,
+       u16_t *port)
+{
+  switch (conn->type) {
+  case NETCONN_RAW:
+    /* return an error as connecting is only a helper for upper layers */
+    return ERR_CONN;
+  case NETCONN_UDPLITE:
+  case NETCONN_UDPNOCHKSUM:
+  case NETCONN_UDP:
+    if (conn->pcb.udp == NULL ||
+  ((conn->pcb.udp->flags & UDP_FLAGS_CONNECTED) == 0))
+     return ERR_CONN;
+    *addr = (conn->pcb.udp->remote_ip);
+    *port = conn->pcb.udp->remote_port;
+    break;
+  case NETCONN_TCP:
+    if (conn->pcb.tcp == NULL)
+      return ERR_CONN;
+    *addr = (conn->pcb.tcp->remote_ip);
+    *port = conn->pcb.tcp->remote_port;
+    break;
+  }
+  return (conn->err = ERR_OK);
+}
+
+err_t
+netconn_addr(struct netconn *conn, struct ip_addr **addr,
+       u16_t *port)
+{
+  switch (conn->type) {
+  case NETCONN_RAW:
+    *addr = &(conn->pcb.raw->local_ip);
+    *port = conn->pcb.raw->protocol;
+    break;
+  case NETCONN_UDPLITE:
+  case NETCONN_UDPNOCHKSUM:
+  case NETCONN_UDP:
+    *addr = &(conn->pcb.udp->local_ip);
+    *port = conn->pcb.udp->local_port;
+    break;
+  case NETCONN_TCP:
+    *addr = &(conn->pcb.tcp->local_ip);
+    *port = conn->pcb.tcp->local_port;
+    break;
+  }
+  return (conn->err = ERR_OK);
+}
+
+err_t
+netconn_bind(struct netconn *conn, struct ip_addr *addr,
+      u16_t port)
+{
+  struct api_msg *msg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  if (conn->type != NETCONN_TCP &&
+     conn->recvmbox == SYS_MBOX_NULL) {
+    if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) {
+      return ERR_MEM;
+    }
+  }
+  
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return (conn->err = ERR_MEM);
+  }
+  msg->type = API_MSG_BIND;
+  msg->msg.conn = conn;
+  msg->msg.msg.bc.ipaddr = addr;
+  msg->msg.msg.bc.port = port;
+  api_msg_post(msg);
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+}
+
+
+err_t
+netconn_connect(struct netconn *conn, struct ip_addr *addr,
+       u16_t port)
+{
+  struct api_msg *msg;
+  
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+
+  if (conn->recvmbox == SYS_MBOX_NULL) {
+    if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) {
+      return ERR_MEM;
+    }
+  }
+  
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return ERR_MEM;
+  }
+  msg->type = API_MSG_CONNECT;
+  msg->msg.conn = conn;  
+  msg->msg.msg.bc.ipaddr = addr;
+  msg->msg.msg.bc.port = port;
+  api_msg_post(msg);
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+}
+
+err_t
+netconn_disconnect(struct netconn *conn)
+{
+  struct api_msg *msg;
+  
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return ERR_MEM;
+  }
+  msg->type = API_MSG_DISCONNECT;
+  msg->msg.conn = conn;  
+  api_msg_post(msg);
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+
+}
+
+err_t
+netconn_listen(struct netconn *conn)
+{
+  struct api_msg *msg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  if (conn->acceptmbox == SYS_MBOX_NULL) {
+    conn->acceptmbox = sys_mbox_new();
+    if (conn->acceptmbox == SYS_MBOX_NULL) {
+      return ERR_MEM;
+    }
+  }
+  
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return (conn->err = ERR_MEM);
+  }
+  msg->type = API_MSG_LISTEN;
+  msg->msg.conn = conn;
+  api_msg_post(msg);
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+}
+
+struct netconn *
+netconn_accept(struct netconn *conn)
+{
+  struct netconn *newconn;
+  
+  if (conn == NULL) {
+    return NULL;
+  }
+  
+  sys_mbox_fetch(conn->acceptmbox, (void *)&newconn);
+  /* Register event with callback */
+  if (conn->callback)
+      (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, 0);
+  
+  return newconn;
+}
+
+struct netbuf *
+netconn_recv(struct netconn *conn)
+{
+  struct api_msg *msg;
+  struct netbuf *buf;
+  struct pbuf *p;
+  u16_t len;
+    
+  if (conn == NULL) {
+    return NULL;
+  }
+  
+  if (conn->recvmbox == SYS_MBOX_NULL) {
+    conn->err = ERR_CONN;
+    return NULL;
+  }
+
+  if (conn->err != ERR_OK) {
+    return NULL;
+  }
+
+  if (conn->type == NETCONN_TCP) {
+    if (conn->pcb.tcp->state == LISTEN) {
+      conn->err = ERR_CONN;
+      return NULL;
+    }
+
+
+    buf = memp_malloc(MEMP_NETBUF);
+
+    if (buf == NULL) {
+      conn->err = ERR_MEM;
+      return NULL;
+    }
+    
+    sys_mbox_fetch(conn->recvmbox, (void *)&p);
+
+    if (p != NULL)
+    {
+        len = p->tot_len;
+        conn->recv_avail -= len;
+    }
+    else
+        len = 0;
+    
+    /* Register event with callback */
+      if (conn->callback)
+        (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, len);
+
+    /* If we are closed, we indicate that we no longer wish to receive
+       data by setting conn->recvmbox to SYS_MBOX_NULL. */
+    if (p == NULL) {
+      memp_free(MEMP_NETBUF, buf);
+      sys_mbox_free(conn->recvmbox);
+      conn->recvmbox = SYS_MBOX_NULL;
+      return NULL;
+    }
+
+    buf->p = p;
+    buf->ptr = p;
+    buf->fromport = 0;
+    buf->fromaddr = NULL;
+
+    /* Let the stack know that we have taken the data. */
+    if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+      conn->err = ERR_MEM;
+      return buf;
+    }
+    msg->type = API_MSG_RECV;
+    msg->msg.conn = conn;
+    if (buf != NULL) {
+      msg->msg.msg.len = buf->p->tot_len;
+    } else {
+      msg->msg.msg.len = 1;
+    }
+    api_msg_post(msg);
+
+    sys_mbox_fetch(conn->mbox, NULL);
+    memp_free(MEMP_API_MSG, msg);
+  } else {
+    sys_mbox_fetch(conn->recvmbox, (void *)&buf);
+  conn->recv_avail -= buf->p->tot_len;
+    /* Register event with callback */
+    if (conn->callback)
+        (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, buf->p->tot_len);
+  }
+
+  
+
+    
+  LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_recv: received %p (err %d)\n", (void *)buf, conn->err));
+
+
+  return buf;
+}
+
+err_t
+netconn_send(struct netconn *conn, struct netbuf *buf)
+{
+  struct api_msg *msg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  if (conn->err != ERR_OK) {
+    return conn->err;
+  }
+
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return (conn->err = ERR_MEM);
+  }
+
+  LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_send: sending %d bytes\n", buf->p->tot_len));
+  msg->type = API_MSG_SEND;
+  msg->msg.conn = conn;
+  msg->msg.msg.p = buf->p;
+  api_msg_post(msg);
+
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+}
+
+err_t
+netconn_write(struct netconn *conn, void *dataptr, u16_t size, u8_t copy)
+{
+  struct api_msg *msg;
+  u16_t len;
+  
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  if (conn->err != ERR_OK) {
+    return conn->err;
+  }
+
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return (conn->err = ERR_MEM);
+  }
+  msg->type = API_MSG_WRITE;
+  msg->msg.conn = conn;
+        
+
+  conn->state = NETCONN_WRITE;
+  while (conn->err == ERR_OK && size > 0) {
+    msg->msg.msg.w.dataptr = dataptr;
+    msg->msg.msg.w.copy = copy;
+    
+    if (conn->type == NETCONN_TCP) {
+      if (tcp_sndbuf(conn->pcb.tcp) == 0) {
+  sys_sem_wait(conn->sem);
+  if (conn->err != ERR_OK) {
+    goto ret;
+  }
+      }
+      if (size > tcp_sndbuf(conn->pcb.tcp)) {
+  /* We cannot send more than one send buffer's worth of data at a
+     time. */
+  len = tcp_sndbuf(conn->pcb.tcp);
+      } else {
+  len = size;
+      }
+    } else {
+      len = size;
+    }
+    
+    LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_write: writing %d bytes (%d)\n", len, copy));
+    msg->msg.msg.w.len = len;
+    api_msg_post(msg);
+    sys_mbox_fetch(conn->mbox, NULL);    
+    if (conn->err == ERR_OK) {
+      dataptr = (void *)((u8_t *)dataptr + len);
+      size -= len;
+    } else if (conn->err == ERR_MEM) {
+      conn->err = ERR_OK;
+      sys_sem_wait(conn->sem);
+    } else {
+      goto ret;
+    }
+  }
+ ret:
+  memp_free(MEMP_API_MSG, msg);
+  conn->state = NETCONN_NONE;
+  
+  return conn->err;
+}
+
+err_t
+netconn_close(struct netconn *conn)
+{
+  struct api_msg *msg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return (conn->err = ERR_MEM);
+  }
+
+  conn->state = NETCONN_CLOSE;
+ again:
+  msg->type = API_MSG_CLOSE;
+  msg->msg.conn = conn;
+  api_msg_post(msg);
+  sys_mbox_fetch(conn->mbox, NULL);
+  if (conn->err == ERR_MEM &&
+     conn->sem != SYS_SEM_NULL) {
+    sys_sem_wait(conn->sem);
+    goto again;
+  }
+  conn->state = NETCONN_NONE;
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+}
+
+err_t
+netconn_err(struct netconn *conn)
+{
+  return conn->err;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/api/api_msg.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/api/api_msg.c
new file mode 100644
index 0000000..36a7fc1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/api/api_msg.c
@@ -0,0 +1,807 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+#include "lwip/arch.h"
+#include "lwip/api_msg.h"
+#include "lwip/memp.h"
+#include "lwip/sys.h"
+#include "lwip/tcpip.h"
+
+#if LWIP_RAW
+static u8_t
+recv_raw(void *arg, struct raw_pcb *pcb, struct pbuf *p,
+    struct ip_addr *addr)
+{
+  struct netbuf *buf;
+  struct netconn *conn;
+
+  conn = arg;
+  if (!conn) return 0;
+
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+    if (!(buf = memp_malloc(MEMP_NETBUF))) {
+      return 0;
+    }
+    pbuf_ref(p);
+    buf->p = p;
+    buf->ptr = p;
+    buf->fromaddr = addr;
+    buf->fromport = pcb->protocol;
+
+    conn->recv_avail += p->tot_len;
+    /* Register event with callback */
+    if (conn->callback)
+        (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len);
+    sys_mbox_post(conn->recvmbox, buf);
+  }
+
+  return 0; /* do not eat the packet */
+}
+#endif
+#if LWIP_UDP
+static void
+recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p,
+   struct ip_addr *addr, u16_t port)
+{
+  struct netbuf *buf;
+  struct netconn *conn;
+
+  conn = arg;
+  
+  if (conn == NULL) {
+    pbuf_free(p);
+    return;
+  }
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+    buf = memp_malloc(MEMP_NETBUF);
+    if (buf == NULL) {
+      pbuf_free(p);
+      return;
+    } else {
+      buf->p = p;
+      buf->ptr = p;
+      buf->fromaddr = addr;
+      buf->fromport = port;
+    }
+
+  conn->recv_avail += p->tot_len;
+    /* Register event with callback */
+    if (conn->callback)
+        (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len);
+    sys_mbox_post(conn->recvmbox, buf);
+  }
+}
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+
+static err_t
+recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
+{
+  struct netconn *conn;
+  u16_t len;
+  
+  conn = arg;
+
+  if (conn == NULL) {
+    pbuf_free(p);
+    return ERR_VAL;
+  }
+
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+        
+    conn->err = err;
+    if (p != NULL) {
+        len = p->tot_len;
+        conn->recv_avail += len;
+    }
+    else
+        len = 0;
+    /* Register event with callback */
+    if (conn->callback)
+        (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, len);
+    sys_mbox_post(conn->recvmbox, p);
+  }  
+  return ERR_OK;
+}
+
+
+static err_t
+poll_tcp(void *arg, struct tcp_pcb *pcb)
+{
+  struct netconn *conn;
+
+  conn = arg;
+  if (conn != NULL &&
+     (conn->state == NETCONN_WRITE || conn->state == NETCONN_CLOSE) &&
+     conn->sem != SYS_SEM_NULL) {
+    sys_sem_signal(conn->sem);
+  }
+  return ERR_OK;
+}
+
+static err_t
+sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len)
+{
+  struct netconn *conn;
+
+  conn = arg;
+  if (conn != NULL && conn->sem != SYS_SEM_NULL) {
+    sys_sem_signal(conn->sem);
+  }
+
+  if (conn && conn->callback)
+      if (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT)
+          (*conn->callback)(conn, NETCONN_EVT_SENDPLUS, len);
+  
+  return ERR_OK;
+}
+
+static void
+err_tcp(void *arg, err_t err)
+{
+  struct netconn *conn;
+
+  conn = arg;
+
+  conn->pcb.tcp = NULL;
+
+  
+  conn->err = err;
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+    /* Register event with callback */
+    if (conn->callback)
+      (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);
+    sys_mbox_post(conn->recvmbox, NULL);
+  }
+  if (conn->mbox != SYS_MBOX_NULL) {
+    sys_mbox_post(conn->mbox, NULL);
+  }
+  if (conn->acceptmbox != SYS_MBOX_NULL) {
+     /* Register event with callback */
+    if (conn->callback)
+      (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);
+    sys_mbox_post(conn->acceptmbox, NULL);
+  }
+  if (conn->sem != SYS_SEM_NULL) {
+    sys_sem_signal(conn->sem);
+  }
+}
+
+static void
+setup_tcp(struct netconn *conn)
+{
+  struct tcp_pcb *pcb;
+  
+  pcb = conn->pcb.tcp;
+  tcp_arg(pcb, conn);
+  tcp_recv(pcb, recv_tcp);
+  tcp_sent(pcb, sent_tcp);
+  tcp_poll(pcb, poll_tcp, 4);
+  tcp_err(pcb, err_tcp);
+}
+
+static err_t
+accept_function(void *arg, struct tcp_pcb *newpcb, err_t err)
+{
+  sys_mbox_t mbox;
+  struct netconn *newconn;
+  struct netconn *conn;
+  
+#if API_MSG_DEBUG
+#if TCP_DEBUG
+  tcp_debug_print_state(newpcb->state);
+#endif /* TCP_DEBUG */
+#endif /* API_MSG_DEBUG */
+  conn = (struct netconn *)arg;
+  mbox = conn->acceptmbox;
+  newconn = memp_malloc(MEMP_NETCONN);
+  if (newconn == NULL) {
+    return ERR_MEM;
+  }
+  newconn->recvmbox = sys_mbox_new();
+  if (newconn->recvmbox == SYS_MBOX_NULL) {
+    memp_free(MEMP_NETCONN, newconn);
+    return ERR_MEM;
+  }
+  newconn->mbox = sys_mbox_new();
+  if (newconn->mbox == SYS_MBOX_NULL) {
+    sys_mbox_free(newconn->recvmbox);
+    memp_free(MEMP_NETCONN, newconn);
+    return ERR_MEM;
+  }
+  newconn->sem = sys_sem_new(0);
+  if (newconn->sem == SYS_SEM_NULL) {
+    sys_mbox_free(newconn->recvmbox);
+    sys_mbox_free(newconn->mbox);
+    memp_free(MEMP_NETCONN, newconn);
+    return ERR_MEM;
+  }
+  /* Allocations were OK, setup the PCB etc */
+  newconn->type = NETCONN_TCP;
+  newconn->pcb.tcp = newpcb;
+  setup_tcp(newconn);
+  newconn->acceptmbox = SYS_MBOX_NULL;
+  newconn->err = err;
+  /* Register event with callback */
+  if (conn->callback)
+  {
+    (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);
+  }
+  /* We have to set the callback here even though
+   * the new socket is unknown. Mark the socket as -1. */
+  newconn->callback = conn->callback;
+  newconn->socket = -1;
+  newconn->recv_avail = 0;
+  
+  sys_mbox_post(mbox, newconn);
+  return ERR_OK;
+}
+#endif /* LWIP_TCP */
+
+static void
+do_newconn(struct api_msg_msg *msg)
+{
+   if(msg->conn->pcb.tcp != NULL) {
+   /* This "new" connection already has a PCB allocated. */
+   /* Is this an error condition? Should it be deleted? 
+      We currently just are happy and return. */
+     sys_mbox_post(msg->conn->mbox, NULL);
+     return;
+   }
+
+   msg->conn->err = ERR_OK;
+
+   /* Allocate a PCB for this connection */
+   switch(msg->conn->type) {
+#if LWIP_RAW
+   case NETCONN_RAW:
+      msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field */
+      raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
+     break;
+#endif
+#if LWIP_UDP
+   case NETCONN_UDPLITE:
+      msg->conn->pcb.udp = udp_new();
+      if(msg->conn->pcb.udp == NULL) {
+         msg->conn->err = ERR_MEM;
+         break;
+      }
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+   case NETCONN_UDPNOCHKSUM:
+      msg->conn->pcb.udp = udp_new();
+      if(msg->conn->pcb.udp == NULL) {
+         msg->conn->err = ERR_MEM;
+         break;
+      }
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+   case NETCONN_UDP:
+      msg->conn->pcb.udp = udp_new();
+      if(msg->conn->pcb.udp == NULL) {
+         msg->conn->err = ERR_MEM;
+         break;
+      }
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+   case NETCONN_TCP:
+      msg->conn->pcb.tcp = tcp_new();
+      if(msg->conn->pcb.tcp == NULL) {
+         msg->conn->err = ERR_MEM;
+         break;
+      }
+      setup_tcp(msg->conn);
+      break;
+#endif
+   }
+   
+  
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+
+static void
+do_delconn(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      raw_remove(msg->conn->pcb.raw);
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:
+      msg->conn->pcb.udp->recv_arg = NULL;
+      udp_remove(msg->conn->pcb.udp);
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP      
+    case NETCONN_TCP:
+      if (msg->conn->pcb.tcp->state == LISTEN) {
+  tcp_arg(msg->conn->pcb.tcp, NULL);
+  tcp_accept(msg->conn->pcb.tcp, NULL);  
+  tcp_close(msg->conn->pcb.tcp);
+      } else {
+  tcp_arg(msg->conn->pcb.tcp, NULL);
+  tcp_sent(msg->conn->pcb.tcp, NULL);
+  tcp_recv(msg->conn->pcb.tcp, NULL);  
+  tcp_poll(msg->conn->pcb.tcp, NULL, 0);
+  tcp_err(msg->conn->pcb.tcp, NULL);
+  if (tcp_close(msg->conn->pcb.tcp) != ERR_OK) {
+    tcp_abort(msg->conn->pcb.tcp);
+  }
+      }
+#endif
+    default:  
+    break;
+    }
+  }
+  /* Trigger select() in socket layer */
+  if (msg->conn->callback)
+  {
+      (*msg->conn->callback)(msg->conn, NETCONN_EVT_RCVPLUS, 0);
+      (*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDPLUS, 0);
+  }
+  
+  if (msg->conn->mbox != SYS_MBOX_NULL) {
+    sys_mbox_post(msg->conn->mbox, NULL);
+  }
+}
+
+static void
+do_bind(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp == NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */
+      raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      msg->conn->pcb.udp = udp_new();
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+    case NETCONN_UDPNOCHKSUM:
+      msg->conn->pcb.udp = udp_new();
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+    case NETCONN_UDP:
+      msg->conn->pcb.udp = udp_new();
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP      
+    case NETCONN_TCP:
+      msg->conn->pcb.tcp = tcp_new();
+      setup_tcp(msg->conn);
+#endif /* LWIP_TCP */
+    default:  
+    break;
+    }
+  }
+  switch (msg->conn->type) {
+#if LWIP_RAW
+  case NETCONN_RAW:
+    msg->conn->err = raw_bind(msg->conn->pcb.raw,msg->msg.bc.ipaddr);
+    break;
+#endif
+#if LWIP_UDP
+  case NETCONN_UDPLITE:
+    /* FALLTHROUGH */
+  case NETCONN_UDPNOCHKSUM:
+    /* FALLTHROUGH */
+  case NETCONN_UDP:
+    msg->conn->err = udp_bind(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port);
+    break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+  case NETCONN_TCP:
+    msg->conn->err = tcp_bind(msg->conn->pcb.tcp,
+            msg->msg.bc.ipaddr, msg->msg.bc.port);
+#endif /* LWIP_TCP */
+  default:
+    break;
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+#if LWIP_TCP
+
+static err_t
+do_connected(void *arg, struct tcp_pcb *pcb, err_t err)
+{
+  struct netconn *conn;
+
+  conn = arg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+  
+  conn->err = err;
+  if (conn->type == NETCONN_TCP && err == ERR_OK) {
+    setup_tcp(conn);
+  }    
+  sys_mbox_post(conn->mbox, NULL);
+  return ERR_OK;
+}
+#endif  
+
+static void
+do_connect(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp == NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */
+      raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      msg->conn->pcb.udp = udp_new();
+      if (msg->conn->pcb.udp == NULL) {
+  msg->conn->err = ERR_MEM;
+  sys_mbox_post(msg->conn->mbox, NULL);
+  return;
+      }
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+    case NETCONN_UDPNOCHKSUM:
+      msg->conn->pcb.udp = udp_new();
+      if (msg->conn->pcb.udp == NULL) {
+  msg->conn->err = ERR_MEM;
+  sys_mbox_post(msg->conn->mbox, NULL);
+  return;
+      }
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+    case NETCONN_UDP:
+      msg->conn->pcb.udp = udp_new();
+      if (msg->conn->pcb.udp == NULL) {
+  msg->conn->err = ERR_MEM;
+  sys_mbox_post(msg->conn->mbox, NULL);
+  return;
+      }
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP      
+    case NETCONN_TCP:
+      msg->conn->pcb.tcp = tcp_new();      
+      if (msg->conn->pcb.tcp == NULL) {
+  msg->conn->err = ERR_MEM;
+  sys_mbox_post(msg->conn->mbox, NULL);
+  return;
+      }
+#endif
+    default:
+      break;
+    }
+  }
+  switch (msg->conn->type) {
+#if LWIP_RAW
+  case NETCONN_RAW:
+    raw_connect(msg->conn->pcb.raw, msg->msg.bc.ipaddr);
+    sys_mbox_post(msg->conn->mbox, NULL);
+    break;
+#endif
+#if LWIP_UDP
+  case NETCONN_UDPLITE:
+    /* FALLTHROUGH */
+  case NETCONN_UDPNOCHKSUM:
+    /* FALLTHROUGH */
+  case NETCONN_UDP:
+    udp_connect(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port);
+    sys_mbox_post(msg->conn->mbox, NULL);
+    break;
+#endif 
+#if LWIP_TCP      
+  case NETCONN_TCP:
+    /*    tcp_arg(msg->conn->pcb.tcp, msg->conn);*/
+    setup_tcp(msg->conn);
+    tcp_connect(msg->conn->pcb.tcp, msg->msg.bc.ipaddr, msg->msg.bc.port,
+    do_connected);
+    /*tcp_output(msg->conn->pcb.tcp);*/
+#endif
+
+  default:
+    break;
+  }
+}
+
+static void
+do_disconnect(struct api_msg_msg *msg)
+{
+
+  switch (msg->conn->type) {
+#if LWIP_RAW
+  case NETCONN_RAW:
+    /* Do nothing as connecting is only a helper for upper lwip layers */
+    break;
+#endif
+#if LWIP_UDP
+  case NETCONN_UDPLITE:
+    /* FALLTHROUGH */
+  case NETCONN_UDPNOCHKSUM:
+    /* FALLTHROUGH */
+  case NETCONN_UDP:
+    udp_disconnect(msg->conn->pcb.udp);
+    break;
+#endif 
+  case NETCONN_TCP:
+    break;
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+
+static void
+do_listen(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen RAW: cannot listen for RAW.\n"));
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:
+      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen UDP: cannot listen for UDP.\n"));
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP      
+    case NETCONN_TCP:
+      msg->conn->pcb.tcp = tcp_listen(msg->conn->pcb.tcp);
+      if (msg->conn->pcb.tcp == NULL) {
+  msg->conn->err = ERR_MEM;
+      } else {
+  if (msg->conn->acceptmbox == SYS_MBOX_NULL) {
+    msg->conn->acceptmbox = sys_mbox_new();
+    if (msg->conn->acceptmbox == SYS_MBOX_NULL) {
+      msg->conn->err = ERR_MEM;
+      break;
+    }
+  }
+  tcp_arg(msg->conn->pcb.tcp, msg->conn);
+  tcp_accept(msg->conn->pcb.tcp, accept_function);
+      }
+#endif
+    default:
+      break;
+    }
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+static void
+do_accept(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept RAW: cannot accept for RAW.\n"));
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:    
+      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept UDP: cannot accept for UDP.\n"));
+      break;
+#endif /* LWIP_UDP */
+    case NETCONN_TCP:
+      break;
+    }
+  }
+}
+
+static void
+do_send(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      raw_send(msg->conn->pcb.raw, msg->msg.p);
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:
+      udp_send(msg->conn->pcb.udp, msg->msg.p);
+      break;
+#endif /* LWIP_UDP */
+    case NETCONN_TCP:
+      break;
+    }
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+static void
+do_recv(struct api_msg_msg *msg)
+{
+#if LWIP_TCP
+  if (msg->conn->pcb.tcp != NULL) {
+    if (msg->conn->type == NETCONN_TCP) {
+      tcp_recved(msg->conn->pcb.tcp, msg->msg.len);
+    }
+  }
+#endif  
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+static void
+do_write(struct api_msg_msg *msg)
+{
+#if LWIP_TCP  
+  err_t err;
+#endif  
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      msg->conn->err = ERR_VAL;
+      break;
+#endif
+#if LWIP_UDP 
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:
+      msg->conn->err = ERR_VAL;
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP 
+    case NETCONN_TCP:      
+      err = tcp_write(msg->conn->pcb.tcp, msg->msg.w.dataptr,
+                      msg->msg.w.len, msg->msg.w.copy);
+      /* This is the Nagle algorithm: inhibit the sending of new TCP
+   segments when new outgoing data arrives from the user if any
+   previously transmitted data on the connection remains
+   unacknowledged. */
+      if(err == ERR_OK && (msg->conn->pcb.tcp->unacked == NULL ||
+        (msg->conn->pcb.tcp->flags & TF_NODELAY) || 
+        (msg->conn->pcb.tcp->snd_queuelen) > 1)) {
+          tcp_output(msg->conn->pcb.tcp);
+      }
+      msg->conn->err = err;
+      if (msg->conn->callback)
+          if (err == ERR_OK)
+          {
+              if (tcp_sndbuf(msg->conn->pcb.tcp) <= TCP_SNDLOWAT)
+                  (*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDMINUS, msg->msg.w.len);
+          }
+#endif
+    default:
+      break;
+    }
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+static void
+do_close(struct api_msg_msg *msg)
+{
+  err_t err;
+
+  err = ERR_OK;
+
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+    case NETCONN_TCP:
+      if (msg->conn->pcb.tcp->state == LISTEN) {
+        err = tcp_close(msg->conn->pcb.tcp);
+      }
+      else if (msg->conn->pcb.tcp->state == CLOSE_WAIT) {
+        err = tcp_output(msg->conn->pcb.tcp);
+      }
+      msg->conn->err = err;      
+#endif
+    default:      
+      break;
+    }
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+typedef void (* api_msg_decode)(struct api_msg_msg *msg);
+static api_msg_decode decode[API_MSG_MAX] = {
+  do_newconn,
+  do_delconn,
+  do_bind,
+  do_connect,
+  do_disconnect,
+  do_listen,
+  do_accept,
+  do_send,
+  do_recv,
+  do_write,
+  do_close
+  };
+void
+api_msg_input(struct api_msg *msg)
+{  
+  decode[msg->type](&(msg->msg));
+}
+
+void
+api_msg_post(struct api_msg *msg)
+{
+  tcpip_apimsg(msg);
+}
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/api/err.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/api/err.c
new file mode 100644
index 0000000..cc63678
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/api/err.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/err.h"
+
+#ifdef LWIP_DEBUG
+
+static char *err_strerr[] = {"Ok.",
+           "Out of memory error.",
+           "Buffer error.",
+           "Connection aborted.",
+           "Connection reset.",
+           "Connection closed.",
+           "Not connected.",
+           "Illegal value.",
+           "Illegal argument.",
+           "Routing problem.",
+           "Address in use."
+};
+
+
+char *
+lwip_strerr(err_t err)
+{
+  return err_strerr[-err];
+
+}
+
+
+#endif /* LWIP_DEBUG */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/api/sockets.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/api/sockets.c
new file mode 100644
index 0000000..26e6d86
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/api/sockets.c
@@ -0,0 +1,1362 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ * Improved by Marc Boucher  and David Haas 
+ *
+ */
+
+#include 
+#include 
+
+#include "lwip/opt.h"
+#include "lwip/api.h"
+#include "lwip/arch.h"
+#include "lwip/sys.h"
+
+#include "lwip/sockets.h"
+
+#define NUM_SOCKETS MEMP_NUM_NETCONN
+
+struct lwip_socket {
+  struct netconn *conn;
+  struct netbuf *lastdata;
+  u16_t lastoffset;
+  u16_t rcvevent;
+  u16_t sendevent;
+  u16_t  flags;
+  int err;
+};
+
+struct lwip_select_cb
+{
+    struct lwip_select_cb *next;
+    fd_set *readset;
+    fd_set *writeset;
+    fd_set *exceptset;
+    int sem_signalled;
+    sys_sem_t sem;
+};
+
+static struct lwip_socket sockets[NUM_SOCKETS];
+static struct lwip_select_cb *select_cb_list = 0;
+
+static sys_sem_t socksem = 0;
+static sys_sem_t selectsem = 0;
+
+static void
+event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len);
+
+static int err_to_errno_table[11] = {
+    0,      /* ERR_OK    0      No error, everything OK. */
+    ENOMEM,    /* ERR_MEM  -1      Out of memory error.     */
+    ENOBUFS,    /* ERR_BUF  -2      Buffer error.            */
+    ECONNABORTED,  /* ERR_ABRT -3      Connection aborted.      */
+    ECONNRESET,    /* ERR_RST  -4      Connection reset.        */
+    ESHUTDOWN,    /* ERR_CLSD -5      Connection closed.       */
+    ENOTCONN,    /* ERR_CONN -6      Not connected.           */
+    EINVAL,    /* ERR_VAL  -7      Illegal value.           */
+    EIO,    /* ERR_ARG  -8      Illegal argument.        */
+    EHOSTUNREACH,  /* ERR_RTE  -9      Routing problem.         */
+    EADDRINUSE    /* ERR_USE  -10     Address in use.          */
+};
+
+#define ERR_TO_ERRNO_TABLE_SIZE \
+  (sizeof(err_to_errno_table)/sizeof(err_to_errno_table[0]))
+
+#define err_to_errno(err) \
+  (-(err) >= 0 && -(err) < ERR_TO_ERRNO_TABLE_SIZE ? \
+    err_to_errno_table[-(err)] : EIO)
+
+#ifdef ERRNO
+#define set_errno(err) errno = (err)
+#else
+#define set_errno(err)
+#endif
+
+#define sock_set_errno(sk, e) do { \
+      sk->err = (e); \
+      set_errno(sk->err); \
+} while (0)
+
+
+static struct lwip_socket *
+get_socket(int s)
+{
+  struct lwip_socket *sock;
+
+  if ((s < 0) || (s > NUM_SOCKETS)) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): invalid\n", s));
+    set_errno(EBADF);
+    return NULL;
+  }
+
+  sock = &sockets[s];
+
+  if (!sock->conn) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): not active\n", s));
+    set_errno(EBADF);
+    return NULL;
+  }
+
+  return sock;
+}
+
+static int
+alloc_socket(struct netconn *newconn)
+{
+  int i;
+
+  if (!socksem)
+      socksem = sys_sem_new(1);
+
+  /* Protect socket array */
+  sys_sem_wait(socksem);
+
+  /* allocate a new socket identifier */
+  for(i = 0; i < NUM_SOCKETS; ++i) {
+    if (!sockets[i].conn) {
+      sockets[i].conn = newconn;
+      sockets[i].lastdata = NULL;
+      sockets[i].lastoffset = 0;
+      sockets[i].rcvevent = 0;
+      sockets[i].sendevent = 1; /* TCP send buf is empty */
+      sockets[i].flags = 0;
+      sockets[i].err = 0;
+      sys_sem_signal(socksem);
+      return i;
+    }
+  }
+  sys_sem_signal(socksem);
+  return -1;
+}
+
+int
+lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen)
+{
+  struct lwip_socket *sock;
+  struct netconn *newconn;
+  struct ip_addr naddr;
+  u16_t port;
+  int newsock;
+  struct sockaddr_in sin;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d)...\n", s));
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  newconn = netconn_accept(sock->conn);
+
+  /* get the IP address and port of the remote host */
+  netconn_peer(newconn, &naddr, &port);
+
+  memset(&sin, 0, sizeof(sin));
+  sin.sin_len = sizeof(sin);
+  sin.sin_family = AF_INET;
+  sin.sin_port = htons(port);
+  sin.sin_addr.s_addr = naddr.addr;
+
+  if (*addrlen > sizeof(sin))
+      *addrlen = sizeof(sin);
+
+  memcpy(addr, &sin, *addrlen);
+
+  newsock = alloc_socket(newconn);
+  if (newsock == -1) {
+    netconn_delete(newconn);
+  sock_set_errno(sock, ENOBUFS);
+  return -1;
+  }
+  newconn->callback = event_callback;
+  sock = get_socket(newsock);
+
+  sys_sem_wait(socksem);
+  sock->rcvevent += -1 - newconn->socket;
+  newconn->socket = newsock;
+  sys_sem_signal(socksem);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d addr=", s, newsock));
+  ip_addr_debug_print(SOCKETS_DEBUG, &naddr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", port));
+
+  sock_set_errno(sock, 0);
+  return newsock;
+}
+
+int
+lwip_bind(int s, struct sockaddr *name, socklen_t namelen)
+{
+  struct lwip_socket *sock;
+  struct ip_addr local_addr;
+  u16_t local_port;
+  err_t err;
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  local_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr;
+  local_port = ((struct sockaddr_in *)name)->sin_port;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d, addr=", s));
+  ip_addr_debug_print(SOCKETS_DEBUG, &local_addr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(local_port)));
+
+  err = netconn_bind(sock->conn, &local_addr, ntohs(local_port));
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) succeeded\n", s));
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_close(int s)
+{
+  struct lwip_socket *sock;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_close(%d)\n", s));
+  if (!socksem)
+      socksem = sys_sem_new(1);
+
+  /* We cannot allow multiple closes of the same socket. */
+  sys_sem_wait(socksem);
+
+  sock = get_socket(s);
+  if (!sock) {
+      sys_sem_signal(socksem);
+      set_errno(EBADF);
+      return -1;
+  }
+
+  netconn_delete(sock->conn);
+  if (sock->lastdata) {
+    netbuf_delete(sock->lastdata);
+  }
+  sock->lastdata = NULL;
+  sock->lastoffset = 0;
+  sock->conn = NULL;
+  sys_sem_signal(socksem);
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_connect(int s, struct sockaddr *name, socklen_t namelen)
+{
+  struct lwip_socket *sock;
+  err_t err;
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  if (((struct sockaddr_in *)name)->sin_family == AF_UNSPEC) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, AF_UNSPEC)\n", s));
+    err = netconn_disconnect(sock->conn);
+  } else {
+    struct ip_addr remote_addr;
+    u16_t remote_port;
+
+    remote_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr;
+    remote_port = ((struct sockaddr_in *)name)->sin_port;
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, addr=", s));
+    ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr);
+    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(remote_port)));
+
+    err = netconn_connect(sock->conn, &remote_addr, ntohs(remote_port));
+   }
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) succeeded\n", s));
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_listen(int s, int backlog)
+{
+  struct lwip_socket *sock;
+  err_t err;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d, backlog=%d)\n", s, backlog));
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  err = netconn_listen(sock->conn);
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d) failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_recvfrom(int s, void *mem, int len, unsigned int flags,
+        struct sockaddr *from, socklen_t *fromlen)
+{
+  struct lwip_socket *sock;
+  struct netbuf *buf;
+  u16_t buflen, copylen;
+  struct ip_addr *addr;
+  u16_t port;
+
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d, %p, %d, 0x%x, ..)\n", s, mem, len, flags));
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  /* Check if there is data left from the last recv operation. */
+  if (sock->lastdata) {
+    buf = sock->lastdata;
+  } else {
+    /* If this is non-blocking call, then check first */
+    if (((flags & MSG_DONTWAIT) || (sock->flags & O_NONBLOCK))
+  && !sock->rcvevent)
+    {
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): returning EWOULDBLOCK\n", s));
+      sock_set_errno(sock, EWOULDBLOCK);
+      return -1;
+    }
+
+    /* No data was left from the previous operation, so we try to get
+       some from the network. */
+    buf = netconn_recv(sock->conn);
+
+    if (!buf) {
+      /* We should really do some error checking here. */
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): buf == NULL!\n", s));
+      sock_set_errno(sock, 0);
+      return 0;
+    }
+  }
+
+  buflen = netbuf_len(buf);
+
+  buflen -= sock->lastoffset;
+
+  if (len > buflen) {
+    copylen = buflen;
+  } else {
+    copylen = len;
+  }
+
+  /* copy the contents of the received buffer into
+     the supplied memory pointer mem */
+  netbuf_copy_partial(buf, mem, copylen, sock->lastoffset);
+
+  /* Check to see from where the data was. */
+  if (from && fromlen) {
+    struct sockaddr_in sin;
+
+    addr = netbuf_fromaddr(buf);
+    port = netbuf_fromport(buf);
+
+    memset(&sin, 0, sizeof(sin));
+    sin.sin_len = sizeof(sin);
+    sin.sin_family = AF_INET;
+    sin.sin_port = htons(port);
+    sin.sin_addr.s_addr = addr->addr;
+
+    if (*fromlen > sizeof(sin))
+      *fromlen = sizeof(sin);
+
+    memcpy(from, &sin, *fromlen);
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s));
+    ip_addr_debug_print(SOCKETS_DEBUG, addr);
+    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, copylen));
+  } else {
+#if SOCKETS_DEBUG
+    addr = netbuf_fromaddr(buf);
+    port = netbuf_fromport(buf);
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s));
+    ip_addr_debug_print(SOCKETS_DEBUG, addr);
+    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, copylen));
+#endif
+
+  }
+
+  /* If this is a TCP socket, check if there is data left in the
+     buffer. If so, it should be saved in the sock structure for next
+     time around. */
+  if (netconn_type(sock->conn) == NETCONN_TCP && buflen - copylen > 0) {
+    sock->lastdata = buf;
+    sock->lastoffset += copylen;
+  } else {
+    sock->lastdata = NULL;
+    sock->lastoffset = 0;
+    netbuf_delete(buf);
+  }
+
+
+  sock_set_errno(sock, 0);
+  return copylen;
+}
+
+int
+lwip_read(int s, void *mem, int len)
+{
+  return lwip_recvfrom(s, mem, len, 0, NULL, NULL);
+}
+
+int
+lwip_recv(int s, void *mem, int len, unsigned int flags)
+{
+  return lwip_recvfrom(s, mem, len, flags, NULL, NULL);
+}
+
+int
+lwip_send(int s, void *data, int size, unsigned int flags)
+{
+  struct lwip_socket *sock;
+  struct netbuf *buf;
+  err_t err;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d, data=%p, size=%d, flags=0x%x)\n", s, data, size, flags));
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  switch (netconn_type(sock->conn)) {
+  case NETCONN_RAW:
+  case NETCONN_UDP:
+  case NETCONN_UDPLITE:
+  case NETCONN_UDPNOCHKSUM:
+    /* create a buffer */
+    buf = netbuf_new();
+
+    if (!buf) {
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) ENOBUFS\n", s));
+      sock_set_errno(sock, ENOBUFS);
+      return -1;
+    }
+
+    /* make the buffer point to the data that should
+       be sent */
+    netbuf_ref(buf, data, size);
+
+    /* send the data */
+    err = netconn_send(sock->conn, buf);
+
+    /* deallocated the buffer */
+    netbuf_delete(buf);
+    break;
+  case NETCONN_TCP:
+    err = netconn_write(sock->conn, data, size, NETCONN_COPY);
+    break;
+  default:
+    err = ERR_ARG;
+    break;
+  }
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) ok size=%d\n", s, size));
+  sock_set_errno(sock, 0);
+  return size;
+}
+
+int
+lwip_sendto(int s, void *data, int size, unsigned int flags,
+       struct sockaddr *to, socklen_t tolen)
+{
+  struct lwip_socket *sock;
+  struct ip_addr remote_addr, addr;
+  u16_t remote_port, port;
+  int ret,connected;
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  /* get the peer if currently connected */
+  connected = (netconn_peer(sock->conn, &addr, &port) == ERR_OK);
+
+  remote_addr.addr = ((struct sockaddr_in *)to)->sin_addr.s_addr;
+  remote_port = ((struct sockaddr_in *)to)->sin_port;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_sendto(%d, data=%p, size=%d, flags=0x%x to=", s, data, size, flags));
+  ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", ntohs(remote_port)));
+
+  netconn_connect(sock->conn, &remote_addr, ntohs(remote_port));
+
+  ret = lwip_send(s, data, size, flags);
+
+  /* reset the remote address and port number
+     of the connection */
+  if (connected)
+    netconn_connect(sock->conn, &addr, port);
+  else
+  netconn_disconnect(sock->conn);
+  return ret;
+}
+
+int
+lwip_socket(int domain, int type, int protocol)
+{
+  struct netconn *conn;
+  int i;
+
+  /* create a netconn */
+  switch (type) {
+  case SOCK_RAW:
+    conn = netconn_new_with_proto_and_callback(NETCONN_RAW, protocol, event_callback);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_RAW, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+    break;
+  case SOCK_DGRAM:
+    conn = netconn_new_with_callback(NETCONN_UDP, event_callback);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_DGRAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+    break;
+  case SOCK_STREAM:
+    conn = netconn_new_with_callback(NETCONN_TCP, event_callback);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_STREAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+    break;
+  default:
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%d, %d/UNKNOWN, %d) = -1\n", domain, type, protocol));
+    set_errno(EINVAL);
+    return -1;
+  }
+
+  if (!conn) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("-1 / ENOBUFS (could not create netconn)\n"));
+    set_errno(ENOBUFS);
+    return -1;
+  }
+
+  i = alloc_socket(conn);
+
+  if (i == -1) {
+    netconn_delete(conn);
+  set_errno(ENOBUFS);
+  return -1;
+  }
+  conn->socket = i;
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("%d\n", i));
+  set_errno(0);
+  return i;
+}
+
+int
+lwip_write(int s, void *data, int size)
+{
+   return lwip_send(s, data, size, 0);
+}
+
+
+static int
+lwip_selscan(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset)
+{
+    int i, nready = 0;
+    fd_set lreadset, lwriteset, lexceptset;
+    struct lwip_socket *p_sock;
+
+    FD_ZERO(&lreadset);
+    FD_ZERO(&lwriteset);
+    FD_ZERO(&lexceptset);
+
+    /* Go through each socket in each list to count number of sockets which
+       currently match */
+    for(i = 0; i < maxfdp1; i++)
+    {
+        if (FD_ISSET(i, readset))
+        {
+            /* See if netconn of this socket is ready for read */
+            p_sock = get_socket(i);
+            if (p_sock && (p_sock->lastdata || p_sock->rcvevent))
+            {
+                FD_SET(i, &lreadset);
+		LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for reading\n", i));
+                nready++;
+            }
+        }
+        if (FD_ISSET(i, writeset))
+        {
+            /* See if netconn of this socket is ready for write */
+            p_sock = get_socket(i);
+            if (p_sock && p_sock->sendevent)
+            {
+                FD_SET(i, &lwriteset);
+		LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for writing\n", i));
+                nready++;
+            }
+        }
+    }
+    *readset = lreadset;
+    *writeset = lwriteset;
+    FD_ZERO(exceptset);
+
+    return nready;
+}
+
+
+
+int
+lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
+               struct timeval *timeout)
+{
+    int i;
+    int nready;
+    fd_set lreadset, lwriteset, lexceptset;
+    u32_t msectimeout;
+    struct lwip_select_cb select_cb;
+    struct lwip_select_cb *p_selcb;
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select(%d, %p, %p, %p, tvsec=%ld tvusec=%ld)\n", maxfdp1, (void *)readset, (void *) writeset, (void *) exceptset, timeout ? timeout->tv_sec : -1L, timeout ? timeout->tv_usec : -1L));
+
+    select_cb.next = 0;
+    select_cb.readset = readset;
+    select_cb.writeset = writeset;
+    select_cb.exceptset = exceptset;
+    select_cb.sem_signalled = 0;
+
+    /* Protect ourselves searching through the list */
+    if (!selectsem)
+        selectsem = sys_sem_new(1);
+    sys_sem_wait(selectsem);
+
+    if (readset)
+        lreadset = *readset;
+    else
+        FD_ZERO(&lreadset);
+    if (writeset)
+        lwriteset = *writeset;
+    else
+        FD_ZERO(&lwriteset);
+    if (exceptset)
+        lexceptset = *exceptset;
+    else
+        FD_ZERO(&lexceptset);
+
+    /* Go through each socket in each list to count number of sockets which
+       currently match */
+    nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset);
+
+    /* If we don't have any current events, then suspend if we are supposed to */
+    if (!nready)
+    {
+        if (timeout && timeout->tv_sec == 0 && timeout->tv_usec == 0)
+        {
+            sys_sem_signal(selectsem);
+            if (readset)
+                FD_ZERO(readset);
+            if (writeset)
+                FD_ZERO(writeset);
+            if (exceptset)
+                FD_ZERO(exceptset);
+
+	    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: no timeout, returning 0\n"));
+	    set_errno(0);
+
+            return 0;
+        }
+
+        /* add our semaphore to list */
+        /* We don't actually need any dynamic memory. Our entry on the
+         * list is only valid while we are in this function, so it's ok
+         * to use local variables */
+
+        select_cb.sem = sys_sem_new(0);
+        /* Note that we are still protected */
+        /* Put this select_cb on top of list */
+        select_cb.next = select_cb_list;
+        select_cb_list = &select_cb;
+
+        /* Now we can safely unprotect */
+        sys_sem_signal(selectsem);
+
+        /* Now just wait to be woken */
+        if (timeout == 0)
+            /* Wait forever */
+            msectimeout = 0;
+        else
+            msectimeout =  ((timeout->tv_sec * 1000) + ((timeout->tv_usec + 500)/1000));
+
+        i = sys_sem_wait_timeout(select_cb.sem, msectimeout);
+
+        /* Take us off the list */
+        sys_sem_wait(selectsem);
+        if (select_cb_list == &select_cb)
+            select_cb_list = select_cb.next;
+        else
+            for (p_selcb = select_cb_list; p_selcb; p_selcb = p_selcb->next)
+                if (p_selcb->next == &select_cb)
+                {
+                    p_selcb->next = select_cb.next;
+                    break;
+                }
+
+        sys_sem_signal(selectsem);
+
+        sys_sem_free(select_cb.sem);
+        if (i == 0)             /* Timeout */
+        {
+            if (readset)
+                FD_ZERO(readset);
+            if (writeset)
+                FD_ZERO(writeset);
+            if (exceptset)
+                FD_ZERO(exceptset);
+
+	    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: timeout expired\n"));
+	    set_errno(0);
+
+            return 0;
+        }
+
+        if (readset)
+            lreadset = *readset;
+        else
+            FD_ZERO(&lreadset);
+        if (writeset)
+            lwriteset = *writeset;
+        else
+            FD_ZERO(&lwriteset);
+        if (exceptset)
+            lexceptset = *exceptset;
+        else
+            FD_ZERO(&lexceptset);
+
+        /* See what's set */
+        nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset);
+    }
+    else
+        sys_sem_signal(selectsem);
+
+    if (readset)
+        *readset = lreadset;
+    if (writeset)
+        *writeset = lwriteset;
+    if (exceptset)
+        *exceptset = lexceptset;
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: nready=%d\n", nready));
+    set_errno(0);
+
+    return nready;
+}
+
+
+static void
+event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len)
+{
+    int s;
+    struct lwip_socket *sock;
+    struct lwip_select_cb *scb;
+
+    /* Get socket */
+    if (conn)
+    {
+        s = conn->socket;
+        if (s < 0)
+        {
+            /* Data comes in right away after an accept, even though
+             * the server task might not have created a new socket yet.
+             * Just count down (or up) if that's the case and we
+             * will use the data later. Note that only receive events
+             * can happen before the new socket is set up. */
+            if (evt == NETCONN_EVT_RCVPLUS)
+                conn->socket--;
+            return;
+        }
+
+        sock = get_socket(s);
+        if (!sock)
+            return;
+    }
+    else
+        return;
+
+    if (!selectsem)
+        selectsem = sys_sem_new(1);
+
+    sys_sem_wait(selectsem);
+    /* Set event as required */
+    switch (evt)
+    {
+      case NETCONN_EVT_RCVPLUS:
+        sock->rcvevent++;
+        break;
+      case NETCONN_EVT_RCVMINUS:
+        sock->rcvevent--;
+        break;
+      case NETCONN_EVT_SENDPLUS:
+        sock->sendevent = 1;
+        break;
+      case NETCONN_EVT_SENDMINUS:
+        sock->sendevent = 0;
+        break;
+    }
+    sys_sem_signal(selectsem);
+
+    /* Now decide if anyone is waiting for this socket */
+    /* NOTE: This code is written this way to protect the select link list
+       but to avoid a deadlock situation by releasing socksem before
+       signalling for the select. This means we need to go through the list
+       multiple times ONLY IF a select was actually waiting. We go through
+       the list the number of waiting select calls + 1. This list is
+       expected to be small. */
+    while (1)
+    {
+        sys_sem_wait(selectsem);
+        for (scb = select_cb_list; scb; scb = scb->next)
+        {
+            if (scb->sem_signalled == 0)
+            {
+                /* Test this select call for our socket */
+                if (scb->readset && FD_ISSET(s, scb->readset))
+                    if (sock->rcvevent)
+                        break;
+                if (scb->writeset && FD_ISSET(s, scb->writeset))
+                    if (sock->sendevent)
+                        break;
+            }
+        }
+        if (scb)
+        {
+            scb->sem_signalled = 1;
+            sys_sem_signal(selectsem);
+            sys_sem_signal(scb->sem);
+        } else {
+            sys_sem_signal(selectsem);
+            break;
+        }
+    }
+
+}
+
+
+
+
+int lwip_shutdown(int s, int how)
+{
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_shutdown(%d, how=%d)\n", s, how));
+  return lwip_close(s); /* XXX temporary hack until proper implementation */
+}
+
+int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen)
+{
+  struct lwip_socket *sock;
+  struct sockaddr_in sin;
+  struct ip_addr naddr;
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  memset(&sin, 0, sizeof(sin));
+  sin.sin_len = sizeof(sin);
+  sin.sin_family = AF_INET;
+
+  /* get the IP address and port of the remote host */
+  netconn_peer(sock->conn, &naddr, &sin.sin_port);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getpeername(%d, addr=", s));
+  ip_addr_debug_print(SOCKETS_DEBUG, &naddr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%d)\n", sin.sin_port));
+
+  sin.sin_port = htons(sin.sin_port);
+  sin.sin_addr.s_addr = naddr.addr;
+
+  if (*namelen > sizeof(sin))
+      *namelen = sizeof(sin);
+
+  memcpy(name, &sin, *namelen);
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen)
+{
+  struct lwip_socket *sock;
+  struct sockaddr_in sin;
+  struct ip_addr *naddr;
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  memset(&sin, 0, sizeof(sin));
+  sin.sin_len = sizeof(sin);
+  sin.sin_family = AF_INET;
+
+  /* get the IP address and port of the remote host */
+  netconn_addr(sock->conn, &naddr, &sin.sin_port);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockname(%d, addr=", s));
+  ip_addr_debug_print(SOCKETS_DEBUG, naddr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%d)\n", sin.sin_port));
+
+  sin.sin_port = htons(sin.sin_port);
+  sin.sin_addr.s_addr = naddr->addr;
+
+  if (*namelen > sizeof(sin))
+      *namelen = sizeof(sin);
+
+  memcpy(name, &sin, *namelen);
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen)
+{
+  int err = 0;
+  struct lwip_socket *sock = get_socket(s);
+
+  if(!sock) {
+   	set_errno(EBADF);
+    return -1;
+  }
+
+  if( NULL == optval || NULL == optlen ) {
+    sock_set_errno( sock, EFAULT );
+    return -1;
+  }
+
+  /* Do length and type checks for the various options first, to keep it readable. */
+  switch( level ) {
+   
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+      switch(optname) {
+         
+      case SO_ACCEPTCONN:
+      case SO_BROADCAST:
+      /* UNIMPL case SO_DEBUG: */
+      /* UNIMPL case SO_DONTROUTE: */
+      case SO_ERROR:
+      case SO_KEEPALIVE:
+      /* UNIMPL case SO_OOBINLINE: */
+      /* UNIMPL case SO_RCVBUF: */
+      /* UNIMPL case SO_SNDBUF: */
+      /* UNIMPL case SO_RCVLOWAT: */
+      /* UNIMPL case SO_SNDLOWAT: */
+#if SO_REUSE
+      case SO_REUSEADDR:
+      case SO_REUSEPORT:
+#endif /* SO_REUSE */
+      case SO_TYPE:
+      /* UNIMPL case SO_USELOOPBACK: */
+        if( *optlen < sizeof(int) ) {
+          err = EINVAL;
+        }
+          break;
+
+      default:
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", s, optname));
+        err = ENOPROTOOPT;
+      }  /* switch */
+      break;
+                     
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+      switch(optname) {
+      /* UNIMPL case IP_HDRINCL: */
+      /* UNIMPL case IP_RCVDSTADDR: */
+      /* UNIMPL case IP_RCVIF: */
+      case IP_TTL:
+      case IP_TOS:
+        if( *optlen < sizeof(int) ) {
+          err = EINVAL;
+        }
+        break;
+
+      default:
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", s, optname));
+        err = ENOPROTOOPT;
+      }  /* switch */
+      break;
+         
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+      if( *optlen < sizeof(int) ) {
+        err = EINVAL;
+        break;
+    }
+      
+      /* If this is no TCP socket, ignore any options. */
+      if ( sock->conn->type != NETCONN_TCP ) return 0;
+
+      switch( optname ) {
+      case TCP_NODELAY:
+      case TCP_KEEPALIVE:
+        break;
+         
+      default:
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", s, optname));
+        err = ENOPROTOOPT;
+      }  /* switch */
+      break;
+
+/* UNDEFINED LEVEL */
+  default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", s, level, optname));
+      err = ENOPROTOOPT;
+  }  /* switch */
+
+   
+  if( 0 != err ) {
+    sock_set_errno(sock, err);
+    return -1;
+  }
+   
+
+
+  /* Now do the actual option processing */
+
+  switch(level) {
+   
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch( optname ) {
+
+    /* The option flags */
+    case SO_ACCEPTCONN:
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_KEEPALIVE:
+    /* UNIMPL case SO_OOBINCLUDE: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    /*case SO_USELOOPBACK: UNIMPL */
+      *(int*)optval = sock->conn->pcb.tcp->so_options & optname;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, optname=0x%x, ..) = %s\n", s, optname, (*(int*)optval?"on":"off")));
+      break;
+
+    case SO_TYPE:
+      switch (sock->conn->type) {
+      case NETCONN_RAW:
+        *(int*)optval = SOCK_RAW;
+        break;
+      case NETCONN_TCP:
+        *(int*)optval = SOCK_STREAM;
+        break;
+      case NETCONN_UDP:
+      case NETCONN_UDPLITE:
+      case NETCONN_UDPNOCHKSUM:
+        *(int*)optval = SOCK_DGRAM;
+        break;
+      default: /* unrecognized socket type */
+        *(int*)optval = sock->conn->type;
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE): unrecognized socket type %d\n", s, *(int *)optval));
+      }  /* switch */
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE) = %d\n", s, *(int *)optval));
+      break;
+
+    case SO_ERROR:
+      *(int *)optval = sock->err;
+      sock->err = 0;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_ERROR) = %d\n", s, *(int *)optval));
+      break;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch( optname ) {
+    case IP_TTL:
+      *(int*)optval = sock->conn->pcb.tcp->ttl;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TTL) = %d\n", s, *(int *)optval));
+      break;
+    case IP_TOS:
+      *(int*)optval = sock->conn->pcb.tcp->tos;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TOS) = %d\n", s, *(int *)optval));
+      break;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    switch( optname ) {
+    case TCP_NODELAY:
+      *(int*)optval = (sock->conn->pcb.tcp->flags & TF_NODELAY);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_NODELAY) = %s\n", s, (*(int*)optval)?"on":"off") );
+      break;
+    case TCP_KEEPALIVE:
+      *(int*)optval = (int)sock->conn->pcb.tcp->keepalive;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPALIVE) = %d\n", s, *(int *)optval));
+      break;
+    }  /* switch */
+    break;
+  }
+
+
+  sock_set_errno(sock, err);
+  return err ? -1 : 0;
+}
+
+int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen)
+{
+  struct lwip_socket *sock = get_socket(s);
+  int err = 0;
+
+  if(!sock) {
+   	set_errno(EBADF);
+    return -1;
+  }
+
+  if( NULL == optval ) {
+    sock_set_errno( sock, EFAULT );
+    return -1;
+  }
+
+
+  /* Do length and type checks for the various options first, to keep it readable. */
+  switch( level ) {
+
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch(optname) {
+
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_KEEPALIVE:
+    /* UNIMPL case SO_OOBINLINE: */
+    /* UNIMPL case SO_RCVBUF: */
+    /* UNIMPL case SO_SNDBUF: */
+    /* UNIMPL case SO_RCVLOWAT: */
+    /* UNIMPL case SO_SNDLOWAT: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    /* UNIMPL case SO_USELOOPBACK: */
+      if( optlen < sizeof(int) ) {
+        err = EINVAL;
+      }
+      break;
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch(optname) {
+    /* UNIMPL case IP_HDRINCL: */
+    /* UNIMPL case IP_RCVDSTADDR: */
+    /* UNIMPL case IP_RCVIF: */
+    case IP_TTL:
+    case IP_TOS:
+      if( optlen < sizeof(int) ) {
+        err = EINVAL;
+      }
+        break;
+      default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    if( optlen < sizeof(int) ) {
+      err = EINVAL;
+        break;
+    }
+
+    /* If this is no TCP socket, ignore any options. */
+    if ( sock->conn->type != NETCONN_TCP ) return 0;
+
+    switch( optname ) {
+    case TCP_NODELAY:
+    case TCP_KEEPALIVE:
+      break;
+
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch */
+    break;
+
+/* UNDEFINED LEVEL */      
+  default:
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", s, level, optname));
+    err = ENOPROTOOPT;
+  }  /* switch */
+
+
+  if( 0 != err ) {
+    sock_set_errno(sock, err);
+    return -1;
+  }
+
+
+
+  /* Now do the actual option processing */
+
+  switch(level) {
+
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch(optname) {
+
+    /* The option flags */
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_KEEPALIVE:
+    /* UNIMPL case SO_OOBINCLUDE: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    /* UNIMPL case SO_USELOOPBACK: */
+      if ( *(int*)optval ) {
+        sock->conn->pcb.tcp->so_options |= optname;
+      } else {
+        sock->conn->pcb.tcp->so_options &= ~optname;
+      }
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, optname=0x%x, ..) -> %s\n", s, optname, (*(int*)optval?"on":"off")));
+      break;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch( optname ) {
+    case IP_TTL:
+      sock->conn->pcb.tcp->ttl = (u8_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TTL, ..) -> %u\n", s, sock->conn->pcb.tcp->ttl));
+      break;
+    case IP_TOS:
+      sock->conn->pcb.tcp->tos = (u8_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TOS, ..)-> %u\n", s, sock->conn->pcb.tcp->tos));
+      break;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    switch( optname ) {
+    case TCP_NODELAY:
+      if ( *(int*)optval ) {
+        sock->conn->pcb.tcp->flags |= TF_NODELAY;
+      } else {
+        sock->conn->pcb.tcp->flags &= ~TF_NODELAY;
+      }
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_NODELAY) -> %s\n", s, (*(int *)optval)?"on":"off") );
+      break;
+    case TCP_KEEPALIVE:
+      sock->conn->pcb.tcp->keepalive = (u32_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) -> %lu\n", s, sock->conn->pcb.tcp->keepalive));
+      break;
+    }  /* switch */
+    break;
+  }  /* switch */
+
+  sock_set_errno(sock, err);
+  return err ? -1 : 0;
+}
+
+int lwip_ioctl(int s, long cmd, void *argp)
+{
+  struct lwip_socket *sock = get_socket(s);
+
+  if(!sock) {
+   	set_errno(EBADF);
+    return -1;
+  }
+
+  switch (cmd) {
+  case FIONREAD:
+    if (!argp) {
+      sock_set_errno(sock, EINVAL);
+      return -1;
+    }
+
+    *((u16_t*)argp) = sock->conn->recv_avail;
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONREAD, %p) = %u\n", s, argp, *((u16_t*)argp)));
+    sock_set_errno(sock, 0);
+    return 0;
+
+  case FIONBIO:
+    if (argp && *(u32_t*)argp)
+      sock->flags |= O_NONBLOCK;
+    else
+      sock->flags &= ~O_NONBLOCK;
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONBIO, %d)\n", s, !!(sock->flags & O_NONBLOCK)));
+    sock_set_errno(sock, 0);
+    return 0;
+
+  default:
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, UNIMPL: 0x%lx, %p)\n", s, cmd, argp));
+    sock_set_errno(sock, ENOSYS); /* not yet implemented */
+    return -1;
+  }
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/api/tcpip.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/api/tcpip.c
new file mode 100644
index 0000000..db86cf4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/api/tcpip.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/sys.h"
+
+#include "lwip/memp.h"
+#include "lwip/pbuf.h"
+
+#include "lwip/ip.h"
+#include "lwip/ip_frag.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/tcpip.h"
+
+static void (* tcpip_init_done)(void *arg) = NULL;
+static void *tcpip_init_done_arg;
+static sys_mbox_t mbox;
+
+#if LWIP_TCP
+static int tcpip_tcp_timer_active = 0;
+
+static void
+tcpip_tcp_timer(void *arg)
+{
+  (void)arg;
+
+  /* call TCP timer handler */
+  tcp_tmr();
+  /* timer still needed? */
+  if (tcp_active_pcbs || tcp_tw_pcbs) {
+    /* restart timer */
+    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
+  } else {
+    /* disable timer */
+    tcpip_tcp_timer_active = 0;
+  }
+}
+
+#if !NO_SYS
+void
+tcp_timer_needed(void)
+{
+  /* timer is off but needed again? */
+  if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) {
+    /* enable and start timer */
+    tcpip_tcp_timer_active = 1;
+    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
+  }
+}
+#endif /* !NO_SYS */
+#endif /* LWIP_TCP */
+
+#if IP_REASSEMBLY
+static void
+ip_timer(void *data)
+{
+  LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: ip_reass_tmr()\n"));
+  ip_reass_tmr();
+  sys_timeout(1000, ip_timer, NULL);
+}
+#endif
+
+static void
+tcpip_thread(void *arg)
+{
+  struct tcpip_msg *msg;
+
+  (void)arg;
+
+  ip_init();
+#if LWIP_UDP  
+  udp_init();
+#endif
+#if LWIP_TCP
+  tcp_init();
+#endif
+#if IP_REASSEMBLY
+  sys_timeout(1000, ip_timer, NULL);
+#endif
+  if (tcpip_init_done != NULL) {
+    tcpip_init_done(tcpip_init_done_arg);
+  }
+
+  while (1) {                          /* MAIN Loop */
+    sys_mbox_fetch(mbox, (void *)&msg);
+    switch (msg->type) {
+    case TCPIP_MSG_API:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: API message %p\n", (void *)msg));
+      api_msg_input(msg->msg.apimsg);
+      break;
+    case TCPIP_MSG_INPUT:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: IP packet %p\n", (void *)msg));
+      ip_input(msg->msg.inp.p, msg->msg.inp.netif);
+      break;
+    case TCPIP_MSG_CALLBACK:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg));
+      msg->msg.cb.f(msg->msg.cb.ctx);
+      break;
+    default:
+      break;
+    }
+    memp_free(MEMP_TCPIP_MSG, msg);
+  }
+}
+
+err_t
+tcpip_input(struct pbuf *p, struct netif *inp)
+{
+  struct tcpip_msg *msg;
+  
+  msg = memp_malloc(MEMP_TCPIP_MSG);
+  if (msg == NULL) {
+    pbuf_free(p);    
+    return ERR_MEM;  
+  }
+  
+  msg->type = TCPIP_MSG_INPUT;
+  msg->msg.inp.p = p;
+  msg->msg.inp.netif = inp;
+  sys_mbox_post(mbox, msg);
+  return ERR_OK;
+}
+
+err_t
+tcpip_callback(void (*f)(void *ctx), void *ctx)
+{
+  struct tcpip_msg *msg;
+  
+  msg = memp_malloc(MEMP_TCPIP_MSG);
+  if (msg == NULL) {
+    return ERR_MEM;  
+  }
+  
+  msg->type = TCPIP_MSG_CALLBACK;
+  msg->msg.cb.f = f;
+  msg->msg.cb.ctx = ctx;
+  sys_mbox_post(mbox, msg);
+  return ERR_OK;
+}
+
+void
+tcpip_apimsg(struct api_msg *apimsg)
+{
+  struct tcpip_msg *msg;
+  msg = memp_malloc(MEMP_TCPIP_MSG);
+  if (msg == NULL) {
+    memp_free(MEMP_API_MSG, apimsg);
+    return;
+  }
+  msg->type = TCPIP_MSG_API;
+  msg->msg.apimsg = apimsg;
+  sys_mbox_post(mbox, msg);
+}
+
+void
+tcpip_init(void (* initfunc)(void *), void *arg)
+{
+  tcpip_init_done = initfunc;
+  tcpip_init_done_arg = arg;
+  mbox = sys_mbox_new();
+  sys_thread_new(tcpip_thread, NULL, TCPIP_THREAD_PRIO);
+}
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/dhcp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/dhcp.c
new file mode 100644
index 0000000..47f65c2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/dhcp.c
@@ -0,0 +1,1464 @@
+/**
+ * @file
+ *
+ * Dynamic Host Configuration Protocol client
+ */
+
+/*
+ *
+ * Copyright (c) 2001-2004 Leon Woestenberg 
+ * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is a contribution to the lwIP TCP/IP stack.
+ * The Swedish Institute of Computer Science and Adam Dunkels
+ * are specifically granted permission to redistribute this
+ * source code.
+ *
+ * Author: Leon Woestenberg 
+ *
+ * This is a DHCP client for the lwIP TCP/IP stack. It aims to conform
+ * with RFC 2131 and RFC 2132.
+ *
+ * TODO:
+ * - Proper parsing of DHCP messages exploiting file/sname field overloading.
+ * - Add JavaDoc style documentation (API, internals).
+ * - Support for interfaces other than Ethernet (SLIP, PPP, ...)
+ *
+ * Please coordinate changes and requests with Leon Woestenberg
+ * 
+ *
+ * Integration with your code:
+ *
+ * In lwip/dhcp.h
+ * #define DHCP_COARSE_TIMER_SECS (recommended 60 which is a minute)
+ * #define DHCP_FINE_TIMER_MSECS (recommended 500 which equals TCP coarse timer)
+ *
+ * Then have your application call dhcp_coarse_tmr() and
+ * dhcp_fine_tmr() on the defined intervals.
+ *
+ * dhcp_start(struct netif *netif);
+ * starts a DHCP client instance which configures the interface by
+ * obtaining an IP address lease and maintaining it.
+ *
+ * Use dhcp_release(netif) to end the lease and use dhcp_stop(netif)
+ * to remove the DHCP client.
+ *
+ */
+ 
+#include 
+ 
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+#include "lwip/udp.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/inet.h"
+#include "netif/etharp.h"
+
+#include "lwip/sys.h"
+#include "lwip/opt.h"
+#include "lwip/dhcp.h"
+
+#if LWIP_DHCP /* don't build if not configured for use in lwipopt.h */
+
+/** global transaction identifier, must be
+ *  unique for each DHCP request. We simply increment, starting
+ *  with this value (easy to match with a packet analyzer) */
+static u32_t xid = 0xABCD0000;
+
+/** DHCP client state machine functions */
+static void dhcp_handle_ack(struct netif *netif);
+static void dhcp_handle_nak(struct netif *netif);
+static void dhcp_handle_offer(struct netif *netif);
+
+static err_t dhcp_discover(struct netif *netif);
+static err_t dhcp_select(struct netif *netif);
+static void dhcp_check(struct netif *netif);
+static void dhcp_bind(struct netif *netif);
+static err_t dhcp_decline(struct netif *netif);
+static err_t dhcp_rebind(struct netif *netif);
+static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state);
+
+/** receive, unfold, parse and free incoming messages */
+static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port);
+static err_t dhcp_unfold_reply(struct dhcp *dhcp);
+static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type);
+static u8_t dhcp_get_option_byte(u8_t *ptr);
+#if 0
+static u16_t dhcp_get_option_short(u8_t *ptr);
+#endif
+static u32_t dhcp_get_option_long(u8_t *ptr);
+static void dhcp_free_reply(struct dhcp *dhcp);
+
+/** set the DHCP timers */
+static void dhcp_timeout(struct netif *netif);
+static void dhcp_t1_timeout(struct netif *netif);
+static void dhcp_t2_timeout(struct netif *netif);
+
+/** build outgoing messages */
+/** create a DHCP request, fill in common headers */
+static err_t dhcp_create_request(struct netif *netif);
+/** free a DHCP request */
+static void dhcp_delete_request(struct netif *netif);
+/** add a DHCP option (type, then length in bytes) */
+static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len);
+/** add option values */
+static void dhcp_option_byte(struct dhcp *dhcp, u8_t value);
+static void dhcp_option_short(struct dhcp *dhcp, u16_t value);
+static void dhcp_option_long(struct dhcp *dhcp, u32_t value);
+/** always add the DHCP options trailer to end and pad */
+static void dhcp_option_trailer(struct dhcp *dhcp);
+
+/**
+ * Back-off the DHCP client (because of a received NAK response).
+ *
+ * Back-off the DHCP client because of a received NAK. Receiving a
+ * NAK means the client asked for something non-sensible, for
+ * example when it tries to renew a lease obtained on another network.
+ *
+ * We back-off and will end up restarting a fresh DHCP negotiation later.
+ *
+ * @param state pointer to DHCP state structure
+ */
+static void dhcp_handle_nak(struct netif *netif) {
+  struct dhcp *dhcp = netif->dhcp;
+  u16_t msecs = 10 * 1000;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_nak(netif=%p) %c%c%"U16_F"\n", 
+    (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_handle_nak(): set request timeout %"U16_F" msecs\n", msecs));
+  dhcp_set_state(dhcp, DHCP_BACKING_OFF);
+}
+
+/**
+ * Checks if the offered IP address is already in use.
+ *
+ * It does so by sending an ARP request for the offered address and
+ * entering CHECKING state. If no ARP reply is received within a small
+ * interval, the address is assumed to be free for use by us.
+ */
+static void dhcp_check(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (s16_t)netif->name[0],
+    (s16_t)netif->name[1]));
+  /* create an ARP query for the offered IP address, expecting that no host
+     responds, as the IP address should not be in use. */
+  result = etharp_query(netif, &dhcp->offered_ip_addr, NULL);
+  if (result != ERR_OK) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_check: could not perform ARP query\n"));
+  }
+  dhcp->tries++;
+  msecs = 500;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_check(): set request timeout %"U16_F" msecs\n", msecs));
+  dhcp_set_state(dhcp, DHCP_CHECKING);
+}
+
+/**
+ * Remember the configuration offered by a DHCP server.
+ *
+ * @param state pointer to DHCP state structure
+ */
+static void dhcp_handle_offer(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  /* obtain the server address */
+  u8_t *option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SERVER_ID);
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_offer(netif=%p) %c%c%"U16_F"\n",
+    (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+  if (option_ptr != NULL)
+  {
+    dhcp->server_ip_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): server 0x%08"X32_F"\n", dhcp->server_ip_addr.addr));
+    /* remember offered address */
+    ip_addr_set(&dhcp->offered_ip_addr, (struct ip_addr *)&dhcp->msg_in->yiaddr);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08"X32_F"\n", dhcp->offered_ip_addr.addr));
+
+    dhcp_select(netif);
+  }
+}
+
+/**
+ * Select a DHCP server offer out of all offers.
+ *
+ * Simply select the first offer received.
+ *
+ * @param netif the netif under DHCP control
+ * @return lwIP specific error (see error.h)
+ */
+static err_t dhcp_select(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u32_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_select(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK)
+  {
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_REQUEST);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, 576);
+
+    /* MUST request the offered IP address */
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+
+    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
+
+    dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/);
+    dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK);
+    dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER);
+    dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST);
+    dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER);
+
+    dhcp_option_trailer(dhcp);
+    /* shrink the pbuf to the actual content length */
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    /* TODO: we really should bind to a specific local interface here
+       but we cannot specify an unconfigured netif as it is addressless */
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    /* send broadcast to any DHCP server */
+    udp_connect(dhcp->pcb, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+    udp_send(dhcp->pcb, dhcp->p_out);
+    /* reconnect to any (or to server here?!) */
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_select: REQUESTING\n"));
+    dhcp_set_state(dhcp, DHCP_REQUESTING);
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_select: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 4 ? dhcp->tries * 1000 : 4 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_select(): set request timeout %"U32_F" msecs\n", msecs));
+  return result;
+}
+
+/**
+ * The DHCP timer that checks for lease renewal/rebind timeouts.
+ *
+ */
+void dhcp_coarse_tmr()
+{
+  struct netif *netif = netif_list;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_coarse_tmr()\n"));
+  /* iterate through all network interfaces */
+  while (netif != NULL) {
+    /* only act on DHCP configured interfaces */
+    if (netif->dhcp != NULL) {
+      /* timer is active (non zero), and triggers (zeroes) now? */
+      if (netif->dhcp->t2_timeout-- == 1) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n"));
+        /* this clients' rebind timeout triggered */
+        dhcp_t2_timeout(netif);
+      /* timer is active (non zero), and triggers (zeroes) now */
+      } else if (netif->dhcp->t1_timeout-- == 1) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n"));
+        /* this clients' renewal timeout triggered */
+        dhcp_t1_timeout(netif);
+      }
+    }
+    /* proceed to next netif */
+    netif = netif->next;
+  }
+}
+
+/**
+ * DHCP transaction timeout handling
+ *
+ * A DHCP server is expected to respond within a short period of time.
+ * This timer checks whether an outstanding DHCP request is timed out.
+ * 
+ */
+void dhcp_fine_tmr()
+{
+  struct netif *netif = netif_list;
+  /* loop through netif's */
+  while (netif != NULL) {
+    /* only act on DHCP configured interfaces */
+    if (netif->dhcp != NULL) {
+      /* timer is active (non zero), and is about to trigger now */      
+      if (netif->dhcp->request_timeout > 1) {
+        netif->dhcp->request_timeout--;
+      }
+      else if (netif->dhcp->request_timeout == 1) {
+        netif->dhcp->request_timeout--;
+        /* { netif->dhcp->request_timeout == 0 } */
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_fine_tmr(): request timeout\n"));
+        /* this clients' request timeout triggered */
+        dhcp_timeout(netif);
+      }
+    }
+    /* proceed to next network interface */
+    netif = netif->next;
+  }
+}
+
+/**
+ * A DHCP negotiation transaction, or ARP request, has timed out.
+ *
+ * The timer that was started with the DHCP or ARP request has
+ * timed out, indicating no response was received in time.
+ *
+ * @param netif the netif under DHCP control
+ *
+ */
+static void dhcp_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_timeout()\n"));
+  /* back-off period has passed, or server selection timed out */
+  if ((dhcp->state == DHCP_BACKING_OFF) || (dhcp->state == DHCP_SELECTING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_timeout(): restarting discovery\n"));
+    dhcp_discover(netif);
+  /* receiving the requested lease timed out */
+  } else if (dhcp->state == DHCP_REQUESTING) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REQUESTING, DHCP request timed out\n"));
+    if (dhcp->tries <= 5) {
+      dhcp_select(netif);
+    } else {
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REQUESTING, releasing, restarting\n"));
+      dhcp_release(netif);
+      dhcp_discover(netif);
+    }
+  /* received no ARP reply for the offered address (which is good) */
+  } else if (dhcp->state == DHCP_CHECKING) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): CHECKING, ARP request timed out\n"));
+    if (dhcp->tries <= 1) {
+      dhcp_check(netif);
+    /* no ARP replies on the offered address,
+       looks like the IP address is indeed free */
+    } else {
+      /* bind the interface to the offered address */
+      dhcp_bind(netif);
+    }
+  }
+  /* did not get response to renew request? */
+  else if (dhcp->state == DHCP_RENEWING) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): RENEWING, DHCP request timed out\n"));
+    /* just retry renewal */
+    /* note that the rebind timer will eventually time-out if renew does not work */
+    dhcp_renew(netif);
+  /* did not get response to rebind request? */
+  } else if (dhcp->state == DHCP_REBINDING) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REBINDING, DHCP request timed out\n"));
+    if (dhcp->tries <= 8) {
+      dhcp_rebind(netif);
+    } else {
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): RELEASING, DISCOVERING\n"));
+      dhcp_release(netif);
+      dhcp_discover(netif);
+    }
+  }
+}
+
+/**
+ * The renewal period has timed out.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void dhcp_t1_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_t1_timeout()\n"));
+  if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) {
+    /* just retry to renew - note that the rebind timer (t2) will
+     * eventually time-out if renew tries fail. */
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t1_timeout(): must renew\n"));
+    dhcp_renew(netif);
+  }
+}
+
+/**
+ * The rebind period has timed out.
+ *
+ */
+static void dhcp_t2_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t2_timeout()\n"));
+  if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) {
+    /* just retry to rebind */
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t2_timeout(): must rebind\n"));
+    dhcp_rebind(netif);
+  }
+}
+
+/**
+ *
+ * @param netif the netif under DHCP control
+ */
+static void dhcp_handle_ack(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  u8_t *option_ptr;
+  /* clear options we might not get from the ACK */
+  dhcp->offered_sn_mask.addr = 0;
+  dhcp->offered_gw_addr.addr = 0;
+  dhcp->offered_bc_addr.addr = 0;
+
+  /* lease time given? */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_LEASE_TIME);
+  if (option_ptr != NULL) {
+    /* remember offered lease time */
+    dhcp->offered_t0_lease = dhcp_get_option_long(option_ptr + 2);
+  }
+  /* renewal period given? */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T1);
+  if (option_ptr != NULL) {
+    /* remember given renewal period */
+    dhcp->offered_t1_renew = dhcp_get_option_long(option_ptr + 2);
+  } else {
+    /* calculate safe periods for renewal */
+    dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2;
+  }
+
+  /* renewal period given? */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T2);
+  if (option_ptr != NULL) {
+    /* remember given rebind period */
+    dhcp->offered_t2_rebind = dhcp_get_option_long(option_ptr + 2);
+  } else {
+    /* calculate safe periods for rebinding */
+    dhcp->offered_t2_rebind = dhcp->offered_t0_lease;
+  }
+
+  /* (y)our internet address */
+  ip_addr_set(&dhcp->offered_ip_addr, &dhcp->msg_in->yiaddr);
+
+/**
+ * Patch #1308
+ * TODO: we must check if the file field is not overloaded by DHCP options!
+ */
+#if 0
+  /* boot server address */
+  ip_addr_set(&dhcp->offered_si_addr, &dhcp->msg_in->siaddr);
+  /* boot file name */
+  if (dhcp->msg_in->file[0]) {
+    dhcp->boot_file_name = mem_malloc(strlen(dhcp->msg_in->file) + 1);
+    strcpy(dhcp->boot_file_name, dhcp->msg_in->file);
+  }
+#endif
+
+  /* subnet mask */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SUBNET_MASK);
+  /* subnet mask given? */
+  if (option_ptr != NULL) {
+    dhcp->offered_sn_mask.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+  }
+
+  /* gateway router */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_ROUTER);
+  if (option_ptr != NULL) {
+    dhcp->offered_gw_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+  }
+
+  /* broadcast address */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_BROADCAST);
+  if (option_ptr != NULL) {
+    dhcp->offered_bc_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+  }
+  
+  /* DNS servers */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_DNS_SERVER);
+  if (option_ptr != NULL) {
+    u8_t n;
+    dhcp->dns_count = dhcp_get_option_byte(&option_ptr[1]) / (u32_t)sizeof(struct ip_addr);
+    /* limit to at most DHCP_MAX_DNS DNS servers */
+    if (dhcp->dns_count > DHCP_MAX_DNS)
+      dhcp->dns_count = DHCP_MAX_DNS;
+    for (n = 0; n < dhcp->dns_count; n++) {
+      dhcp->offered_dns_addr[n].addr = htonl(dhcp_get_option_long(&option_ptr[2 + n * 4]));
+    }
+  }
+}
+
+/**
+ * Start DHCP negotiation for a network interface.
+ *
+ * If no DHCP client instance was attached to this interface,
+ * a new client is created first. If a DHCP client instance
+ * was already present, it restarts negotiation.
+ *
+ * @param netif The lwIP network interface
+ * @return lwIP error code
+ * - ERR_OK - No error
+ * - ERR_MEM - Out of memory
+ *
+ */
+err_t dhcp_start(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result = ERR_OK;
+
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_start(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+  netif->flags &= ~NETIF_FLAG_DHCP;
+
+  /* no DHCP client attached yet? */
+  if (dhcp == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting new DHCP client\n"));
+    dhcp = mem_malloc(sizeof(struct dhcp));
+    if (dhcp == NULL) {
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n"));
+      return ERR_MEM;
+    }
+    /* store this dhcp client in the netif */
+    netif->dhcp = dhcp;
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): allocated dhcp"));
+  /* already has DHCP client attached */
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE | 3, ("dhcp_start(): restarting DHCP configuration\n"));
+  }
+    
+  /* clear data structure */
+  memset(dhcp, 0, sizeof(struct dhcp));
+  /* allocate UDP PCB */
+  dhcp->pcb = udp_new();
+  if (dhcp->pcb == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG  | DBG_TRACE, ("dhcp_start(): could not obtain pcb\n"));
+    mem_free((void *)dhcp);
+    netif->dhcp = dhcp = NULL;
+    return ERR_MEM;
+  }
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n"));
+  /* (re)start the DHCP negotiation */
+  result = dhcp_discover(netif);
+  if (result != ERR_OK) {
+    /* free resources allocated above */
+    dhcp_stop(netif);
+    return ERR_MEM;
+  }
+  netif->flags |= NETIF_FLAG_DHCP;
+  return result;
+}
+
+/**
+ * Inform a DHCP server of our manual configuration.
+ *
+ * This informs DHCP servers of our fixed IP address configuration
+ * by sending an INFORM message. It does not involve DHCP address
+ * configuration, it is just here to be nice to the network.
+ *
+ * @param netif The lwIP network interface
+ *
+ */
+void dhcp_inform(struct netif *netif)
+{
+  struct dhcp *dhcp;
+  err_t result = ERR_OK;
+  dhcp = mem_malloc(sizeof(struct dhcp));
+  if (dhcp == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform(): could not allocate dhcp\n"));
+    return;
+  }
+  netif->dhcp = dhcp;
+  memset(dhcp, 0, sizeof(struct dhcp));
+
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_inform(): allocated dhcp\n"));
+  dhcp->pcb = udp_new();
+  if (dhcp->pcb == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform(): could not obtain pcb"));
+    mem_free((void *)dhcp);
+    return;
+  }
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_inform(): created new udp pcb\n"));
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_INFORM);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    /* TODO: use netif->mtu ?! */
+    dhcp_option_short(dhcp, 576);
+
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    udp_connect(dhcp->pcb, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_inform: INFORMING\n"));
+    udp_send(dhcp->pcb, dhcp->p_out);
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    dhcp_delete_request(netif);
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform: could not allocate DHCP request\n"));
+  }
+
+  if (dhcp != NULL)
+  {
+    if (dhcp->pcb != NULL) udp_remove(dhcp->pcb);
+    dhcp->pcb = NULL;
+    mem_free((void *)dhcp);
+    netif->dhcp = NULL;
+  }
+}
+
+#if DHCP_DOES_ARP_CHECK
+/**
+ * Match an ARP reply with the offered IP address.
+ *
+ * @param addr The IP address we received a reply from
+ *
+ */
+void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr)
+{
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_arp_reply()\n"));
+  /* is a DHCP client doing an ARP check? */
+  if ((netif->dhcp != NULL) && (netif->dhcp->state == DHCP_CHECKING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08"X32_F"\n", addr->addr));
+    /* did a host respond with the address we
+       were offered by the DHCP server? */
+    if (ip_addr_cmp(addr, &netif->dhcp->offered_ip_addr)) {
+      /* we will not accept the offered address */
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE | 1, ("dhcp_arp_reply(): arp reply matched with offered address, declining\n"));
+      dhcp_decline(netif);
+    }
+  }
+}
+
+/**
+ * Decline an offered lease.
+ *
+ * Tell the DHCP server we do not accept the offered address.
+ * One reason to decline the lease is when we find out the address
+ * is already in use by another host (through ARP).
+ */
+static err_t dhcp_decline(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result = ERR_OK;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_decline()\n"));
+  dhcp_set_state(dhcp, DHCP_BACKING_OFF);
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK)
+  {
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_DECLINE);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, 576);
+
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+
+    dhcp_option_trailer(dhcp);
+    /* resize pbuf to reflect true size of options */
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    /* @todo: should we really connect here? we are performing sendto() */
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    /* per section 4.4.4, broadcast DECLINE messages */
+    udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_decline: BACKING OFF\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_decline: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = 10*1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+   LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_decline(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+#endif
+
+
+/**
+ * Start the DHCP process, discover a DHCP server.
+ *
+ */
+static err_t dhcp_discover(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result = ERR_OK;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_discover()\n"));
+  ip_addr_set(&dhcp->offered_ip_addr, IP_ADDR_ANY);
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK)
+  {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: making request\n"));
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_DISCOVER);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, 576);
+
+    dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/);
+    dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK);
+    dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER);
+    dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST);
+    dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER);
+
+    dhcp_option_trailer(dhcp);
+
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: realloc()ing\n"));
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    /* set receive callback function with netif as user data */
+    udp_recv(dhcp->pcb, dhcp_recv, netif);
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, DHCP_SERVER_PORT)\n"));
+    udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: deleting()ing\n"));
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover: SELECTING\n"));
+    dhcp_set_state(dhcp, DHCP_SELECTING);
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_discover: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 4 ? (dhcp->tries + 1) * 1000 : 10 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+
+/**
+ * Bind the interface to the offered IP address.
+ *
+ * @param netif network interface to bind to the offered address
+ */
+static void dhcp_bind(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  struct ip_addr sn_mask, gw_addr;
+  LWIP_ASSERT("dhcp_bind: netif != NULL", netif != NULL);
+  LWIP_ASSERT("dhcp_bind: dhcp != NULL", dhcp != NULL);
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_bind(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+
+  /* temporary DHCP lease? */
+  if (dhcp->offered_t1_renew != 0xffffffffUL) {
+    /* set renewal period timer */
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t1 renewal timer %"U32_F" secs\n", dhcp->offered_t1_renew));
+    dhcp->t1_timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
+    if (dhcp->t1_timeout == 0) dhcp->t1_timeout = 1;
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t1_renew*1000));
+  }
+  /* set renewal period timer */
+  if (dhcp->offered_t2_rebind != 0xffffffffUL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t2 rebind timer %"U32_F" secs\n", dhcp->offered_t2_rebind));
+    dhcp->t2_timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
+    if (dhcp->t2_timeout == 0) dhcp->t2_timeout = 1;
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t2_rebind*1000));
+  }
+  /* copy offered network mask */
+  ip_addr_set(&sn_mask, &dhcp->offered_sn_mask);
+
+  /* subnet mask not given? */
+  /* TODO: this is not a valid check. what if the network mask is 0? */
+  if (sn_mask.addr == 0) {
+    /* choose a safe subnet mask given the network class */
+    u8_t first_octet = ip4_addr1(&sn_mask);
+    if (first_octet <= 127) sn_mask.addr = htonl(0xff000000);
+    else if (first_octet >= 192) sn_mask.addr = htonl(0xffffff00);
+    else sn_mask.addr = htonl(0xffff0000);
+  }
+
+  ip_addr_set(&gw_addr, &dhcp->offered_gw_addr);
+  /* gateway address not given? */
+  if (gw_addr.addr == 0) {
+    /* copy network address */
+    gw_addr.addr = (dhcp->offered_ip_addr.addr & sn_mask.addr);
+    /* use first host address on network as gateway */
+    gw_addr.addr |= htonl(0x00000001);
+  }
+
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): IP: 0x%08"X32_F"\n", dhcp->offered_ip_addr.addr));
+  netif_set_ipaddr(netif, &dhcp->offered_ip_addr);
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): SN: 0x%08"X32_F"\n", sn_mask.addr));
+  netif_set_netmask(netif, &sn_mask);
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): GW: 0x%08"X32_F"\n", gw_addr.addr));
+  netif_set_gw(netif, &gw_addr);
+  /* bring the interface up */
+  netif_set_up(netif);
+  /* netif is now bound to DHCP leased address */
+  dhcp_set_state(dhcp, DHCP_BOUND);
+}
+
+/**
+ * Renew an existing DHCP lease at the involved DHCP server.
+ *
+ * @param netif network interface which must renew its lease
+ */
+err_t dhcp_renew(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_renew()\n"));
+  dhcp_set_state(dhcp, DHCP_RENEWING);
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_REQUEST);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    /* TODO: use netif->mtu in some way */
+    dhcp_option_short(dhcp, 576);
+
+#if 0
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+#endif
+
+#if 0
+    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
+#endif
+    /* append DHCP message trailer */
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT);
+    udp_send(dhcp->pcb, dhcp->p_out);
+    dhcp_delete_request(netif);
+
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew: RENEWING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_renew: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  /* back-off on retries, but to a maximum of 20 seconds */
+  msecs = dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+   LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+/**
+ * Rebind with a DHCP server for an existing DHCP lease.
+ *
+ * @param netif network interface which must rebind with a DHCP server
+ */
+static err_t dhcp_rebind(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind()\n"));
+  dhcp_set_state(dhcp, DHCP_REBINDING);
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK)
+  {
+
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_REQUEST);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, 576);
+
+#if 0
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+
+    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
+#endif
+
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    /* set remote IP association to any DHCP server */
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    /* broadcast to server */
+    udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind: REBINDING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_rebind: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+   LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+/**
+ * Release a DHCP lease.
+ *
+ * @param netif network interface which must release its lease
+ */
+err_t dhcp_release(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_release()\n"));
+
+  /* idle DHCP client */
+  dhcp_set_state(dhcp, DHCP_OFF);
+  /* clean old DHCP offer */
+  dhcp->server_ip_addr.addr = 0;
+  dhcp->offered_ip_addr.addr = dhcp->offered_sn_mask.addr = 0;
+  dhcp->offered_gw_addr.addr = dhcp->offered_bc_addr.addr = 0;
+  dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0;
+  dhcp->dns_count = 0;
+  
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_RELEASE);
+
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT);
+    udp_send(dhcp->pcb, dhcp->p_out);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release: RELEASED, DHCP_OFF\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_release: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release(): set request timeout %"U16_F" msecs\n", msecs));
+  /* bring the interface down */
+  netif_set_down(netif);
+  /* remove IP address from interface */
+  netif_set_ipaddr(netif, IP_ADDR_ANY);
+  netif_set_gw(netif, IP_ADDR_ANY);
+  netif_set_netmask(netif, IP_ADDR_ANY);
+  
+  /* TODO: netif_down(netif); */
+  return result;
+}
+/**
+ * Remove the DHCP client from the interface.
+ *
+ * @param netif The network interface to stop DHCP on
+ */
+void dhcp_stop(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_ASSERT("dhcp_stop: netif != NULL", netif != NULL);
+
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_stop()\n"));
+  /* netif is DHCP configured? */
+  if (dhcp != NULL)
+  {
+    if (dhcp->pcb != NULL)
+    {
+      udp_remove(dhcp->pcb);
+      dhcp->pcb = NULL;
+    }
+    if (dhcp->p != NULL)
+    {
+      pbuf_free(dhcp->p);
+      dhcp->p = NULL;
+    }
+    /* free unfolded reply */
+    dhcp_free_reply(dhcp);
+    mem_free((void *)dhcp);
+    netif->dhcp = NULL;
+  }
+}
+
+/*
+ * Set the DHCP state of a DHCP client.
+ *
+ * If the state changed, reset the number of tries.
+ *
+ * TODO: we might also want to reset the timeout here?
+ */
+static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state)
+{
+  if (new_state != dhcp->state)
+  {
+    dhcp->state = new_state;
+    dhcp->tries = 0;
+  }
+}
+
+/*
+ * Concatenate an option type and length field to the outgoing
+ * DHCP message.
+ *
+ */
+static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len)
+{
+  LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = option_type;
+  dhcp->msg_out->options[dhcp->options_out_len++] = option_len;
+}
+/*
+ * Concatenate a single byte to the outgoing DHCP message.
+ *
+ */
+static void dhcp_option_byte(struct dhcp *dhcp, u8_t value)
+{
+  LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len < DHCP_OPTIONS_LEN", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = value;
+}
+static void dhcp_option_short(struct dhcp *dhcp, u16_t value)
+{
+  LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0xff00U) >> 8;
+  dhcp->msg_out->options[dhcp->options_out_len++] =  value & 0x00ffU;
+}
+static void dhcp_option_long(struct dhcp *dhcp, u32_t value)
+{
+  LWIP_ASSERT("dhcp_option_long: dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0xff000000UL) >> 24;
+  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x00ff0000UL) >> 16;
+  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x0000ff00UL) >> 8;
+  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x000000ffUL);
+}
+
+/**
+ * Extract the DHCP message and the DHCP options.
+ *
+ * Extract the DHCP message and the DHCP options, each into a contiguous
+ * piece of memory. As a DHCP message is variable sized by its options,
+ * and also allows overriding some fields for options, the easy approach
+ * is to first unfold the options into a conitguous piece of memory, and
+ * use that further on.
+ *
+ */
+static err_t dhcp_unfold_reply(struct dhcp *dhcp)
+{
+  struct pbuf *p = dhcp->p;
+  u8_t *ptr;
+  u16_t i;
+  u16_t j = 0;
+  LWIP_ASSERT("dhcp->p != NULL", dhcp->p != NULL);
+  /* free any left-overs from previous unfolds */
+  dhcp_free_reply(dhcp);
+  /* options present? */
+  if (dhcp->p->tot_len > (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN))
+  {
+    dhcp->options_in_len = dhcp->p->tot_len - (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN);
+    dhcp->options_in = mem_malloc(dhcp->options_in_len);
+    if (dhcp->options_in == NULL)
+    {
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->options\n"));
+      return ERR_MEM;
+    }
+  }
+  dhcp->msg_in = mem_malloc(sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN);
+  if (dhcp->msg_in == NULL)
+  {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->msg_in\n"));
+    mem_free((void *)dhcp->options_in);
+    dhcp->options_in = NULL;
+    return ERR_MEM;
+  }
+
+  ptr = (u8_t *)dhcp->msg_in;
+  /* proceed through struct dhcp_msg */
+  for (i = 0; i < sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN; i++)
+  {
+    *ptr++ = ((u8_t *)p->payload)[j++];
+    /* reached end of pbuf? */
+    if (j == p->len)
+    {
+      /* proceed to next pbuf in chain */
+      p = p->next;
+      j = 0;
+    }
+  }
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %"U16_F" bytes into dhcp->msg_in[]\n", i));
+  if (dhcp->options_in != NULL) {
+    ptr = (u8_t *)dhcp->options_in;
+    /* proceed through options */
+    for (i = 0; i < dhcp->options_in_len; i++) {
+      *ptr++ = ((u8_t *)p->payload)[j++];
+      /* reached end of pbuf? */
+      if (j == p->len) {
+        /* proceed to next pbuf in chain */
+        p = p->next;
+        j = 0;
+      }
+    }
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %"U16_F" bytes to dhcp->options_in[]\n", i));
+  }
+  return ERR_OK;
+}
+
+/**
+ * Free the incoming DHCP message including contiguous copy of
+ * its DHCP options.
+ *
+ */
+static void dhcp_free_reply(struct dhcp *dhcp)
+{
+  if (dhcp->msg_in != NULL) {
+    mem_free((void *)dhcp->msg_in);
+    dhcp->msg_in = NULL;
+  }
+  if (dhcp->options_in) {
+    mem_free((void *)dhcp->options_in);
+    dhcp->options_in = NULL;
+    dhcp->options_in_len = 0;
+  }
+  LWIP_DEBUGF(DHCP_DEBUG, ("dhcp_free_reply(): free'd\n"));
+}
+
+
+/**
+ * If an incoming DHCP message is in response to us, then trigger the state machine
+ */
+static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port)
+{
+  struct netif *netif = (struct netif *)arg;
+  struct dhcp *dhcp = netif->dhcp;
+  struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload;
+  u8_t *options_ptr;
+  u8_t msg_type;
+  u8_t i;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_recv(pbuf = %p) from DHCP server %"U16_F".%"U16_F".%"U16_F".%"U16_F" port %"U16_F"\n", (void*)p,
+    (u16_t)(ntohl(addr->addr) >> 24 & 0xff), (u16_t)(ntohl(addr->addr) >> 16 & 0xff),
+    (u16_t)(ntohl(addr->addr) >>  8 & 0xff), (u16_t)(ntohl(addr->addr) & 0xff), port));
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->len = %"U16_F"\n", p->len));
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->tot_len = %"U16_F"\n", p->tot_len));
+  /* prevent warnings about unused arguments */
+  (void)pcb; (void)addr; (void)port;
+  dhcp->p = p;
+  /* TODO: check packet length before reading them */
+  if (reply_msg->op != DHCP_BOOTREPLY) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("not a DHCP reply message, but type %"U16_F"\n", (u16_t)reply_msg->op));
+    pbuf_free(p);
+    dhcp->p = NULL;
+    return;
+  }
+  /* iterate through hardware address and match against DHCP message */
+  for (i = 0; i < netif->hwaddr_len; i++) {
+    if (netif->hwaddr[i] != reply_msg->chaddr[i]) {
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("netif->hwaddr[%"U16_F"]==%02"X16_F" != reply_msg->chaddr[%"U16_F"]==%02"X16_F"\n",
+        (u16_t)i, (u16_t)netif->hwaddr[i], (u16_t)i, (u16_t)reply_msg->chaddr[i]));
+      pbuf_free(p);
+      dhcp->p = NULL;
+      return;
+    }
+  }
+  /* match transaction ID against what we expected */
+  if (ntohl(reply_msg->xid) != dhcp->xid) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("transaction id mismatch reply_msg->xid(%"X32_F")!=dhcp->xid(%"X32_F")\n",ntohl(reply_msg->xid),dhcp->xid));
+    pbuf_free(p);
+    dhcp->p = NULL;
+    return;
+  }
+  /* option fields could be unfold? */
+  if (dhcp_unfold_reply(dhcp) != ERR_OK) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("problem unfolding DHCP message - too short on memory?\n"));
+    pbuf_free(p);
+    dhcp->p = NULL;
+    return;
+  }
+
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n"));
+  /* obtain pointer to DHCP message type */
+  options_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_MESSAGE_TYPE);
+  if (options_ptr == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_OPTION_MESSAGE_TYPE option not found\n"));
+    pbuf_free(p);
+    dhcp->p = NULL;
+    return;
+  }
+
+  /* read DHCP message type */
+  msg_type = dhcp_get_option_byte(options_ptr + 2);
+  /* message type is DHCP ACK? */
+  if (msg_type == DHCP_ACK) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_ACK received\n"));
+    /* in requesting state? */
+    if (dhcp->state == DHCP_REQUESTING) {
+      dhcp_handle_ack(netif);
+      dhcp->request_timeout = 0;
+#if DHCP_DOES_ARP_CHECK
+      /* check if the acknowledged lease address is already in use */
+      dhcp_check(netif);
+#else
+      /* bind interface to the acknowledged lease address */
+      dhcp_bind(netif);
+#endif
+    }
+    /* already bound to the given lease address? */
+    else if ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING)) {
+      dhcp->request_timeout = 0;
+      dhcp_bind(netif);
+    }
+  }
+  /* received a DHCP_NAK in appropriate state? */
+  else if ((msg_type == DHCP_NAK) &&
+    ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REQUESTING) ||
+     (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING  ))) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_NAK received\n"));
+    dhcp->request_timeout = 0;
+    dhcp_handle_nak(netif);
+  }
+  /* received a DHCP_OFFER in DHCP_SELECTING state? */
+  else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_SELECTING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_OFFER received in DHCP_SELECTING state\n"));
+    dhcp->request_timeout = 0;
+    /* remember offered lease */
+    dhcp_handle_offer(netif);
+  }
+  pbuf_free(p);
+  dhcp->p = NULL;
+}
+
+
+static err_t dhcp_create_request(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  u16_t i;
+  LWIP_ASSERT("dhcp_create_request: dhcp->p_out == NULL", dhcp->p_out == NULL);
+  LWIP_ASSERT("dhcp_create_request: dhcp->msg_out == NULL", dhcp->msg_out == NULL);
+  dhcp->p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM);
+  if (dhcp->p_out == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_create_request(): could not allocate pbuf\n"));
+    return ERR_MEM;
+  }
+  /* give unique transaction identifier to this request */
+  dhcp->xid = xid++;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("transaction id xid++(%"X32_F") dhcp->xid(%"U32_F")\n",xid,dhcp->xid));
+
+  dhcp->msg_out = (struct dhcp_msg *)dhcp->p_out->payload;
+
+  dhcp->msg_out->op = DHCP_BOOTREQUEST;
+  /* TODO: make link layer independent */
+  dhcp->msg_out->htype = DHCP_HTYPE_ETH;
+  /* TODO: make link layer independent */
+  dhcp->msg_out->hlen = DHCP_HLEN_ETH;
+  dhcp->msg_out->hops = 0;
+  dhcp->msg_out->xid = htonl(dhcp->xid);
+  dhcp->msg_out->secs = 0;
+  dhcp->msg_out->flags = 0;
+  dhcp->msg_out->ciaddr.addr = netif->ip_addr.addr;
+  dhcp->msg_out->yiaddr.addr = 0;
+  dhcp->msg_out->siaddr.addr = 0;
+  dhcp->msg_out->giaddr.addr = 0;
+  for (i = 0; i < DHCP_CHADDR_LEN; i++) {
+    /* copy netif hardware address, pad with zeroes */
+    dhcp->msg_out->chaddr[i] = (i < netif->hwaddr_len) ? netif->hwaddr[i] : 0/* pad byte*/;
+  }
+  for (i = 0; i < DHCP_SNAME_LEN; i++) dhcp->msg_out->sname[i] = 0;
+  for (i = 0; i < DHCP_FILE_LEN; i++) dhcp->msg_out->file[i] = 0;
+  dhcp->msg_out->cookie = htonl(0x63825363UL);
+  dhcp->options_out_len = 0;
+  /* fill options field with an incrementing array (for debugging purposes) */
+  for (i = 0; i < DHCP_OPTIONS_LEN; i++) dhcp->msg_out->options[i] = i;
+  return ERR_OK;
+}
+
+static void dhcp_delete_request(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_ASSERT("dhcp_free_msg: dhcp->p_out != NULL", dhcp->p_out != NULL);
+  LWIP_ASSERT("dhcp_free_msg: dhcp->msg_out != NULL", dhcp->msg_out != NULL);
+  pbuf_free(dhcp->p_out);
+  dhcp->p_out = NULL;
+  dhcp->msg_out = NULL;
+}
+
+/**
+ * Add a DHCP message trailer
+ *
+ * Adds the END option to the DHCP message, and if
+ * necessary, up to three padding bytes.
+ */
+
+static void dhcp_option_trailer(struct dhcp *dhcp)
+{
+  LWIP_ASSERT("dhcp_option_trailer: dhcp->msg_out != NULL\n", dhcp->msg_out != NULL);
+  LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = DHCP_OPTION_END;
+  /* packet is too small, or not 4 byte aligned? */
+  while ((dhcp->options_out_len < DHCP_MIN_OPTIONS_LEN) || (dhcp->options_out_len & 3)) {
+    /* LWIP_DEBUGF(DHCP_DEBUG,("dhcp_option_trailer:dhcp->options_out_len=%"U16_F", DHCP_OPTIONS_LEN=%"U16_F, dhcp->options_out_len, DHCP_OPTIONS_LEN)); */
+    LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+    /* add a fill/padding byte */
+    dhcp->msg_out->options[dhcp->options_out_len++] = 0;
+  }
+}
+
+/**
+ * Find the offset of a DHCP option inside the DHCP message.
+ *
+ * @param client DHCP client
+ * @param option_type
+ *
+ * @return a byte offset into the UDP message where the option was found, or
+ * zero if the given option was not found.
+ */
+static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type)
+{
+  u8_t overload = DHCP_OVERLOAD_NONE;
+
+  /* options available? */
+  if ((dhcp->options_in != NULL) && (dhcp->options_in_len > 0)) {
+    /* start with options field */
+    u8_t *options = (u8_t *)dhcp->options_in;
+    u16_t offset = 0;
+    /* at least 1 byte to read and no end marker, then at least 3 bytes to read? */
+    while ((offset < dhcp->options_in_len) && (options[offset] != DHCP_OPTION_END)) {
+      /* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%"U16_F", q->len=%"U16_F, msg_offset, q->len)); */
+      /* are the sname and/or file field overloaded with options? */
+      if (options[offset] == DHCP_OPTION_OVERLOAD) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("overloaded message detected\n"));
+        /* skip option type and length */
+        offset += 2;
+        overload = options[offset++];
+      }
+      /* requested option found */
+      else if (options[offset] == option_type) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset %"U16_F" in options\n", offset));
+        return &options[offset];
+      /* skip option */
+      } else {
+         LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %"U16_F" in options\n", options[offset]));
+        /* skip option type */
+        offset++;
+        /* skip option length, and then length bytes */
+        offset += 1 + options[offset];
+      }
+    }
+    /* is this an overloaded message? */
+    if (overload != DHCP_OVERLOAD_NONE) {
+      u16_t field_len;
+      if (overload == DHCP_OVERLOAD_FILE) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded file field\n"));
+        options = (u8_t *)&dhcp->msg_in->file;
+        field_len = DHCP_FILE_LEN;
+      } else if (overload == DHCP_OVERLOAD_SNAME) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded sname field\n"));
+        options = (u8_t *)&dhcp->msg_in->sname;
+        field_len = DHCP_SNAME_LEN;
+      /* TODO: check if else if () is necessary */
+      } else {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded sname and file field\n"));
+        options = (u8_t *)&dhcp->msg_in->sname;
+        field_len = DHCP_FILE_LEN + DHCP_SNAME_LEN;
+      }
+      offset = 0;
+
+      /* at least 1 byte to read and no end marker */
+      while ((offset < field_len) && (options[offset] != DHCP_OPTION_END)) {
+        if (options[offset] == option_type) {
+           LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset=%"U16_F"\n", offset));
+          return &options[offset];
+        /* skip option */
+        } else {
+          LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("skipping option %"U16_F"\n", options[offset]));
+          /* skip option type */
+          offset++;
+          offset += 1 + options[offset];
+        }
+      }
+    }
+  }
+  return NULL;
+}
+
+/**
+ * Return the byte of DHCP option data.
+ *
+ * @param client DHCP client.
+ * @param ptr pointer obtained by dhcp_get_option_ptr().
+ *
+ * @return byte value at the given address.
+ */
+static u8_t dhcp_get_option_byte(u8_t *ptr)
+{
+  LWIP_DEBUGF(DHCP_DEBUG, ("option byte value=%"U16_F"\n", (u16_t)(*ptr)));
+  return *ptr;
+}
+
+#if 0
+/**
+ * Return the 16-bit value of DHCP option data.
+ *
+ * @param client DHCP client.
+ * @param ptr pointer obtained by dhcp_get_option_ptr().
+ *
+ * @return byte value at the given address.
+ */
+static u16_t dhcp_get_option_short(u8_t *ptr)
+{
+  u16_t value;
+  value = *ptr++ << 8;
+  value |= *ptr;
+  LWIP_DEBUGF(DHCP_DEBUG, ("option short value=%"U16_F"\n", value));
+  return value;
+}
+#endif
+
+/**
+ * Return the 32-bit value of DHCP option data.
+ *
+ * @param client DHCP client.
+ * @param ptr pointer obtained by dhcp_get_option_ptr().
+ *
+ * @return byte value at the given address.
+ */
+static u32_t dhcp_get_option_long(u8_t *ptr)
+{
+  u32_t value;
+  value = (u32_t)(*ptr++) << 24;
+  value |= (u32_t)(*ptr++) << 16;
+  value |= (u32_t)(*ptr++) << 8;
+  value |= (u32_t)(*ptr++);
+  LWIP_DEBUGF(DHCP_DEBUG, ("option long value=%"U32_F"\n", value));
+  return value;
+}
+
+#endif /* LWIP_DHCP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/inet.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/inet.c
new file mode 100644
index 0000000..d9d52c5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/inet.c
@@ -0,0 +1,537 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+/* inet.c
+ *
+ * Functions common to all TCP/IP modules, such as the Internet checksum and the
+ * byte order functions.
+ *
+ */
+
+
+#include "lwip/opt.h"
+
+#include "lwip/arch.h"
+
+#include "lwip/def.h"
+#include "lwip/inet.h"
+
+#include "lwip/sys.h"
+
+/* These are some reference implementations of the checksum algorithm, with the
+ * aim of being simple, correct and fully portable. Checksumming is the
+ * first thing you would want to optimize for your platform. If you create
+ * your own version, link it in and in your sys_arch.h put:
+ * 
+ * #define LWIP_CHKSUM  
+*/
+#ifndef LWIP_CHKSUM
+#define LWIP_CHKSUM lwip_standard_chksum
+
+#if 1 /* Version A */
+/**
+ * lwip checksum
+ *
+ * @param dataptr points to start of data to be summed at any boundary
+ * @param len length of data to be summed
+ * @return host order (!) lwip checksum (non-inverted Internet sum) 
+ *
+ * @note accumulator size limits summable length to 64k
+ * @note host endianess is irrelevant (p3 RFC1071)
+ */
+static u16_t
+lwip_standard_chksum(void *dataptr, u16_t len)
+{
+  u32_t acc;
+  u16_t src;
+  u8_t *octetptr;
+
+  acc = 0;
+  /* dataptr may be at odd or even addresses */
+  octetptr = (u8_t*)dataptr;
+  while (len > 1)
+  {
+    /* declare first octet as most significant
+       thus assume network order, ignoring host order */
+    src = (*octetptr) << 8;
+    octetptr++;
+    /* declare second octet as least significant */
+    src |= (*octetptr);
+    octetptr++;
+    acc += src;
+    len -= 2;
+  }
+  if (len > 0)
+  {
+    /* accumulate remaining octet */
+    src = (*octetptr) << 8;
+    acc += src;
+  }
+  /* add deferred carry bits */
+  acc = (acc >> 16) + (acc & 0x0000ffffUL);
+  if ((acc & 0xffff0000) != 0) {
+    acc = (acc >> 16) + (acc & 0x0000ffffUL);
+  }
+  /* This maybe a little confusing: reorder sum using htons()
+     instead of ntohs() since it has a little less call overhead.
+     The caller must invert bits for Internet sum ! */
+  return htons((u16_t)acc);
+}
+#endif
+
+#if 0 /* Version B */
+/*
+ * Curt McDowell
+ * Broadcom Corp.
+ * csm@broadcom.com
+ *
+ * IP checksum two bytes at a time with support for
+ * unaligned buffer.
+ * Works for len up to and including 0x20000.
+ * by Curt McDowell, Broadcom Corp. 12/08/2005
+ */
+
+static u16_t
+lwip_standard_chksum(void *dataptr, int len)
+{
+  u8_t *pb = dataptr;
+  u16_t *ps, t = 0;
+  u32_t sum = 0;
+  int odd = ((u32_t)pb & 1);
+
+  /* Get aligned to u16_t */
+  if (odd && len > 0) {
+    ((u8_t *)&t)[1] = *pb++;
+    len--;
+  }
+
+  /* Add the bulk of the data */
+  ps = (u16_t *)pb;
+  while (len > 1) {
+    sum += *ps++;
+    len -= 2;
+  }
+
+  /* Consume left-over byte, if any */
+  if (len > 0)
+    ((u8_t *)&t)[0] = *(u8_t *)ps;;
+
+  /* Add end bytes */
+  sum += t;
+
+  /*  Fold 32-bit sum to 16 bits */
+  while (sum >> 16)
+    sum = (sum & 0xffff) + (sum >> 16);
+
+  /* Swap if alignment was odd */
+  if (odd)
+    sum = ((sum & 0xff) << 8) | ((sum & 0xff00) >> 8);
+
+  return sum;
+}
+#endif
+
+#if 0 /* Version C */
+/**
+ * An optimized checksum routine. Basically, it uses loop-unrolling on
+ * the checksum loop, treating the head and tail bytes specially, whereas
+ * the inner loop acts on 8 bytes at a time. 
+ *
+ * @arg start of buffer to be checksummed. May be an odd byte address.
+ * @len number of bytes in the buffer to be checksummed.
+ * 
+ * by Curt McDowell, Broadcom Corp. December 8th, 2005
+ */
+
+static u16_t
+lwip_standard_chksum(void *dataptr, int len)
+{
+  u8_t *pb = dataptr;
+  u16_t *ps, t = 0;
+  u32_t *pl;
+  u32_t sum = 0, tmp;
+  /* starts at odd byte address? */
+  int odd = ((u32_t)pb & 1);
+
+  if (odd && len > 0) {
+    ((u8_t *)&t)[1] = *pb++;
+    len--;
+  }
+
+  ps = (u16_t *)pb;
+
+  if (((u32_t)ps & 3) && len > 1) {
+    sum += *ps++;
+    len -= 2;
+  }
+
+  pl = (u32_t *)ps;
+
+  while (len > 7)  {
+    tmp = sum + *pl++;          /* ping */
+    if (tmp < sum)
+      tmp++;                    /* add back carry */
+
+    sum = tmp + *pl++;          /* pong */
+    if (sum < tmp)
+      sum++;                    /* add back carry */
+
+    len -= 8;
+  }
+
+  /* make room in upper bits */
+  sum = (sum >> 16) + (sum & 0xffff);
+
+  ps = (u16_t *)pl;
+
+  /* 16-bit aligned word remaining? */
+  while (len > 1) {
+    sum += *ps++;
+    len -= 2;
+  }
+
+  /* dangling tail byte remaining? */
+  if (len > 0)                  /* include odd byte */
+    ((u8_t *)&t)[0] = *(u8_t *)ps;
+
+  sum += t;                     /* add end bytes */
+
+  while (sum >> 16)             /* combine halves */
+    sum = (sum >> 16) + (sum & 0xffff);
+
+  if (odd)
+    sum = ((sum & 0xff) << 8) | ((sum & 0xff00) >> 8);
+
+  return sum;
+}
+#endif
+
+#endif /* LWIP_CHKSUM */
+
+/* inet_chksum_pseudo:
+ *
+ * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
+ */
+
+u16_t
+inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u16_t proto_len)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped;
+
+  acc = 0;
+  swapped = 0;
+  /* iterate through all pbuf in chain */
+  for(q = p; q != NULL; q = q->next) {
+    LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n",
+      (void *)q, (void *)q->next));
+    acc += LWIP_CHKSUM(q->payload, q->len);
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/
+    while (acc >> 16) {
+      acc = (acc & 0xffffUL) + (acc >> 16);
+    }
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8);
+    }
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/
+  }
+
+  if (swapped) {
+    acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8);
+  }
+  acc += (src->addr & 0xffffUL);
+  acc += ((src->addr >> 16) & 0xffffUL);
+  acc += (dest->addr & 0xffffUL);
+  acc += ((dest->addr >> 16) & 0xffffUL);
+  acc += (u32_t)htons((u16_t)proto);
+  acc += (u32_t)htons(proto_len);
+
+  while (acc >> 16) {
+    acc = (acc & 0xffffUL) + (acc >> 16);
+  }
+  LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc));
+  return (u16_t)~(acc & 0xffffUL);
+}
+
+/* inet_chksum:
+ *
+ * Calculates the Internet checksum over a portion of memory. Used primarily for IP
+ * and ICMP.
+ */
+
+u16_t
+inet_chksum(void *dataptr, u16_t len)
+{
+  u32_t acc;
+
+  acc = LWIP_CHKSUM(dataptr, len);
+  while (acc >> 16) {
+    acc = (acc & 0xffff) + (acc >> 16);
+  }
+  return (u16_t)~(acc & 0xffff);
+}
+
+u16_t
+inet_chksum_pbuf(struct pbuf *p)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped;
+
+  acc = 0;
+  swapped = 0;
+  for(q = p; q != NULL; q = q->next) {
+    acc += LWIP_CHKSUM(q->payload, q->len);
+    while (acc >> 16) {
+      acc = (acc & 0xffffUL) + (acc >> 16);
+    }
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = (acc & 0x00ffUL << 8) | (acc & 0xff00UL >> 8);
+    }
+  }
+
+  if (swapped) {
+    acc = ((acc & 0x00ffUL) << 8) | ((acc & 0xff00UL) >> 8);
+  }
+  return (u16_t)~(acc & 0xffffUL);
+}
+
+/* Here for now until needed in other places in lwIP */
+#ifndef isprint
+#define in_range(c, lo, up)  ((u8_t)c >= lo && (u8_t)c <= up)
+#define isprint(c)           in_range(c, 0x20, 0x7f)
+#define isdigit(c)           in_range(c, '0', '9')
+#define isxdigit(c)          (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F'))
+#define islower(c)           in_range(c, 'a', 'z')
+#define isspace(c)           (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v')
+#endif    
+    
+/*
+ * Ascii internet address interpretation routine.
+ * The value returned is in network order.
+ */
+
+u32_t
+inet_addr(const char *cp)
+{
+  struct in_addr val;
+
+  if (inet_aton(cp, &val)) {
+    return (val.s_addr);
+  }
+  return (INADDR_NONE);
+}
+
+/*
+ * Check whether "cp" is a valid ascii representation
+ * of an Internet address and convert to a binary address.
+ * Returns 1 if the address is valid, 0 if not.
+ * This replaces inet_addr, the return value from which
+ * cannot distinguish between failure and a local broadcast address.
+ */
+int
+inet_aton(const char *cp, struct in_addr *addr)
+{
+  u32_t val;
+  int base, n, c;
+  u32_t parts[4];
+  u32_t *pp = parts;
+
+  c = *cp;
+  for (;;) {
+    /*
+     * Collect number up to ``.''.
+     * Values are specified as for C:
+     * 0x=hex, 0=octal, 1-9=decimal.
+     */
+    if (!isdigit(c))
+      return (0);
+    val = 0;
+    base = 10;
+    if (c == '0') {
+      c = *++cp;
+      if (c == 'x' || c == 'X') {
+        base = 16;
+        c = *++cp;
+      } else
+        base = 8;
+    }
+    for (;;) {
+      if (isdigit(c)) {
+        val = (val * base) + (int)(c - '0');
+        c = *++cp;
+      } else if (base == 16 && isxdigit(c)) {
+        val = (val << 4) | (int)(c + 10 - (islower(c) ? 'a' : 'A'));
+        c = *++cp;
+      } else
+        break;
+    }
+    if (c == '.') {
+      /*
+       * Internet format:
+       *  a.b.c.d
+       *  a.b.c   (with c treated as 16 bits)
+       *  a.b (with b treated as 24 bits)
+       */
+      if (pp >= parts + 3)
+        return (0);
+      *pp++ = val;
+      c = *++cp;
+    } else
+      break;
+  }
+  /*
+   * Check for trailing characters.
+   */
+  if (c != '\0' && (!isprint(c) || !isspace(c)))
+    return (0);
+  /*
+   * Concoct the address according to
+   * the number of parts specified.
+   */
+  n = pp - parts + 1;
+  switch (n) {
+
+  case 0:
+    return (0);       /* initial nondigit */
+
+  case 1:             /* a -- 32 bits */
+    break;
+
+  case 2:             /* a.b -- 8.24 bits */
+    if (val > 0xffffff)
+      return (0);
+    val |= parts[0] << 24;
+    break;
+
+  case 3:             /* a.b.c -- 8.8.16 bits */
+    if (val > 0xffff)
+      return (0);
+    val |= (parts[0] << 24) | (parts[1] << 16);
+    break;
+
+  case 4:             /* a.b.c.d -- 8.8.8.8 bits */
+    if (val > 0xff)
+      return (0);
+    val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8);
+    break;
+  }
+  if (addr)
+    addr->s_addr = htonl(val);
+  return (1);
+}
+
+/* Convert numeric IP address into decimal dotted ASCII representation.
+ * returns ptr to static buffer; not reentrant!
+ */
+char *
+inet_ntoa(struct in_addr addr)
+{
+  static char str[16];
+  u32_t s_addr = addr.s_addr;
+  char inv[3];
+  char *rp;
+  u8_t *ap;
+  u8_t rem;
+  u8_t n;
+  u8_t i;
+
+  rp = str;
+  ap = (u8_t *)&s_addr;
+  for(n = 0; n < 4; n++) {
+    i = 0;
+    do {
+      rem = *ap % (u8_t)10;
+      *ap /= (u8_t)10;
+      inv[i++] = '0' + rem;
+    } while(*ap);
+    while(i--)
+      *rp++ = inv[i];
+    *rp++ = '.';
+    ap++;
+  }
+  *--rp = 0;
+  return str;
+}
+
+/*
+ * These are reference implementations of the byte swapping functions.
+ * Again with the aim of being simple, correct and fully portable.
+ * Byte swapping is the second thing you would want to optimize. You will
+ * need to port it to your architecture and in your cc.h:
+ * 
+ * #define LWIP_PLATFORM_BYTESWAP 1
+ * #define LWIP_PLATFORM_HTONS(x) 
+ * #define LWIP_PLATFORM_HTONL(x) 
+ *
+ * Note ntohs() and ntohl() are merely references to the htonx counterparts.
+ */
+
+#ifndef BYTE_ORDER
+#error BYTE_ORDER is not defined
+#endif
+#if (LWIP_PLATFORM_BYTESWAP == 0) && (BYTE_ORDER == LITTLE_ENDIAN)
+
+u16_t
+htons(u16_t n)
+{
+  return ((n & 0xff) << 8) | ((n & 0xff00) >> 8);
+}
+
+u16_t
+ntohs(u16_t n)
+{
+  return htons(n);
+}
+
+u32_t
+htonl(u32_t n)
+{
+  return ((n & 0xff) << 24) |
+    ((n & 0xff00) << 8) |
+    ((n & 0xff0000) >> 8) |
+    ((n & 0xff000000) >> 24);
+}
+
+u32_t
+ntohl(u32_t n)
+{
+  return htonl(n);
+}
+
+#endif /* (LWIP_PLATFORM_BYTESWAP == 0) && (BYTE_ORDER == LITTLE_ENDIAN) */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/inet6.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/inet6.c
new file mode 100644
index 0000000..aebc6f3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/inet6.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+/* inet6.c
+ *
+ * Functions common to all TCP/IP modules, such as the Internet checksum and the
+ * byte order functions.
+ *
+ */
+
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/inet.h"
+
+
+
+/* chksum:
+ *
+ * Sums up all 16 bit words in a memory portion. Also includes any odd byte.
+ * This function is used by the other checksum functions.
+ *
+ * For now, this is not optimized. Must be optimized for the particular processor
+ * arcitecture on which it is to run. Preferebly coded in assembler.
+ */
+
+static u32_t
+chksum(void *dataptr, u16_t len)
+{
+  u16_t *sdataptr = dataptr;
+  u32_t acc;
+  
+  
+  for(acc = 0; len > 1; len -= 2) {
+    acc += *sdataptr++;
+  }
+
+  /* add up any odd byte */
+  if (len == 1) {
+    acc += htons((u16_t)(*(u8_t *)dataptr) << 8);
+  }
+
+  return acc;
+
+}
+
+/* inet_chksum_pseudo:
+ *
+ * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
+ */
+
+u16_t
+inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u32_t proto_len)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped, i;
+
+  acc = 0;
+  swapped = 0;
+  for(q = p; q != NULL; q = q->next) {    
+    acc += chksum(q->payload, q->len);
+    while (acc >> 16) {
+      acc = (acc & 0xffff) + (acc >> 16);
+    }
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+    }
+  }
+
+  if (swapped) {
+    acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+  }
+  
+  for(i = 0; i < 8; i++) {
+    acc += ((u16_t *)src->addr)[i] & 0xffff;
+    acc += ((u16_t *)dest->addr)[i] & 0xffff;
+    while (acc >> 16) {
+      acc = (acc & 0xffff) + (acc >> 16);
+    }
+  }
+  acc += (u16_t)htons((u16_t)proto);
+  acc += ((u16_t *)&proto_len)[0] & 0xffff;
+  acc += ((u16_t *)&proto_len)[1] & 0xffff;
+
+  while (acc >> 16) {
+    acc = (acc & 0xffff) + (acc >> 16);
+  }
+  return ~(acc & 0xffff);
+}
+
+/* inet_chksum:
+ *
+ * Calculates the Internet checksum over a portion of memory. Used primarely for IP
+ * and ICMP.
+ */
+
+u16_t
+inet_chksum(void *dataptr, u16_t len)
+{
+  u32_t acc, sum;
+
+  acc = chksum(dataptr, len);
+  sum = (acc & 0xffff) + (acc >> 16);
+  sum += (sum >> 16);
+  return ~(sum & 0xffff);
+}
+
+u16_t
+inet_chksum_pbuf(struct pbuf *p)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped;
+  
+  acc = 0;
+  swapped = 0;
+  for(q = p; q != NULL; q = q->next) {
+    acc += chksum(q->payload, q->len);
+    while (acc >> 16) {
+      acc = (acc & 0xffff) + (acc >> 16);
+    }    
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = (acc & 0xff << 8) | (acc & 0xff00 >> 8);
+    }
+  }
+ 
+  if (swapped) {
+    acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+  }
+  return ~(acc & 0xffff);
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/ipv4/icmp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/ipv4/icmp.c
new file mode 100644
index 0000000..e4028b1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/ipv4/icmp.c
@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* Some ICMP messages should be passed to the transport protocols. This
+   is not implemented. */
+
+#include 
+
+#include "lwip/opt.h"
+#include "lwip/icmp.h"
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+#include "lwip/def.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+
+void
+icmp_input(struct pbuf *p, struct netif *inp)
+{
+  u8_t type;
+  u8_t code;
+  struct icmp_echo_hdr *iecho;
+  struct ip_hdr *iphdr;
+  struct ip_addr tmpaddr;
+  u16_t hlen;
+
+  ICMP_STATS_INC(icmp.recv);
+  snmp_inc_icmpinmsgs();
+
+
+  iphdr = p->payload;
+  hlen = IPH_HL(iphdr) * 4;
+  if (pbuf_header(p, -((s16_t)hlen)) || (p->tot_len < sizeof(u16_t)*2)) {
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len));
+    pbuf_free(p);
+    ICMP_STATS_INC(icmp.lenerr);
+    snmp_inc_icmpinerrors();
+    return;
+  }
+
+  type = *((u8_t *)p->payload);
+  code = *(((u8_t *)p->payload)+1);
+  switch (type) {
+  case ICMP_ECHO:
+    /* broadcast or multicast destination address? */
+    if (ip_addr_isbroadcast(&iphdr->dest, inp) || ip_addr_ismulticast(&iphdr->dest)) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast or broadcast pings\n"));
+      ICMP_STATS_INC(icmp.err);
+      pbuf_free(p);
+      return;
+    }
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
+    if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n"));
+      pbuf_free(p);
+      ICMP_STATS_INC(icmp.lenerr);
+      snmp_inc_icmpinerrors();
+
+      return;
+    }
+    iecho = p->payload;
+    if (inet_chksum_pbuf(p) != 0) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n"));
+      pbuf_free(p);
+      ICMP_STATS_INC(icmp.chkerr);
+      snmp_inc_icmpinerrors();
+      return;
+    }
+    tmpaddr.addr = iphdr->src.addr;
+    iphdr->src.addr = iphdr->dest.addr;
+    iphdr->dest.addr = tmpaddr.addr;
+    ICMPH_TYPE_SET(iecho, ICMP_ER);
+    /* adjust the checksum */
+    if (iecho->chksum >= htons(0xffff - (ICMP_ECHO << 8))) {
+      iecho->chksum += htons(ICMP_ECHO << 8) + 1;
+    } else {
+      iecho->chksum += htons(ICMP_ECHO << 8);
+    }
+    ICMP_STATS_INC(icmp.xmit);
+    /* increase number of messages attempted to send */
+    snmp_inc_icmpoutmsgs();
+    /* increase number of echo replies attempted to send */
+    snmp_inc_icmpoutechoreps();
+
+    pbuf_header(p, hlen);
+    ip_output_if(p, &(iphdr->src), IP_HDRINCL,
+     IPH_TTL(iphdr), 0, IP_PROTO_ICMP, inp);
+    break;
+  default:
+  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n", (s16_t)type, (s16_t)code));
+    ICMP_STATS_INC(icmp.proterr);
+    ICMP_STATS_INC(icmp.drop);
+  }
+  pbuf_free(p);
+}
+
+void
+icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  struct icmp_dur_hdr *idur;
+
+  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
+  /* ICMP header + IP header + 8 bytes of data */
+
+  iphdr = p->payload;
+
+  idur = q->payload;
+  ICMPH_TYPE_SET(idur, ICMP_DUR);
+  ICMPH_CODE_SET(idur, t);
+
+  memcpy((u8_t *)q->payload + 8, p->payload, IP_HLEN + 8);
+
+  /* calculate checksum */
+  idur->chksum = 0;
+  idur->chksum = inet_chksum(idur, q->len);
+  ICMP_STATS_INC(icmp.xmit);
+  /* increase number of messages attempted to send */
+  snmp_inc_icmpoutmsgs();
+  /* increase number of destination unreachable messages attempted to send */
+  snmp_inc_icmpoutdestunreachs();
+
+  ip_output(q, NULL, &(iphdr->src),
+      ICMP_TTL, 0, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+#if IP_FORWARD
+void
+icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  struct icmp_te_hdr *tehdr;
+
+  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
+
+  iphdr = p->payload;
+  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded from "));
+  ip_addr_debug_print(ICMP_DEBUG, &(iphdr->src));
+  LWIP_DEBUGF(ICMP_DEBUG, (" to "));
+  ip_addr_debug_print(ICMP_DEBUG, &(iphdr->dest));
+  LWIP_DEBUGF(ICMP_DEBUG, ("\n"));
+
+  tehdr = q->payload;
+  ICMPH_TYPE_SET(tehdr, ICMP_TE);
+  ICMPH_CODE_SET(tehdr, t);
+
+  /* copy fields from original packet */
+  memcpy((u8_t *)q->payload + 8, (u8_t *)p->payload, IP_HLEN + 8);
+
+  /* calculate checksum */
+  tehdr->chksum = 0;
+  tehdr->chksum = inet_chksum(tehdr, q->len);
+  ICMP_STATS_INC(icmp.xmit);
+  /* increase number of messages attempted to send */
+  snmp_inc_icmpoutmsgs();
+  /* increase number of destination unreachable messages attempted to send */
+  snmp_inc_icmpouttimeexcds();
+  ip_output(q, NULL, &(iphdr->src),
+      ICMP_TTL, 0, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+#endif /* IP_FORWARD */
+
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/ipv4/ip.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/ipv4/ip.c
new file mode 100644
index 0000000..31d29a9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/ipv4/ip.c
@@ -0,0 +1,515 @@
+/* @file
+ *
+ * This is the IP layer implementation for incoming and outgoing IP traffic.
+ * 
+ * @see ip_frag.c
+ *
+ */
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/ip.h"
+#include "lwip/ip_frag.h"
+#include "lwip/inet.h"
+#include "lwip/netif.h"
+#include "lwip/icmp.h"
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+
+#include "lwip/snmp.h"
+#if LWIP_DHCP
+#  include "lwip/dhcp.h"
+#endif /* LWIP_DHCP */
+
+/**
+ * Initializes the IP layer.
+ */
+
+void
+ip_init(void)
+{
+#if IP_FRAG
+  ip_frag_init();
+#endif
+}
+
+/**
+ * Finds the appropriate network interface for a given IP address. It
+ * searches the list of network interfaces linearly. A match is found
+ * if the masked IP address of the network interface equals the masked
+ * IP address given to the function.
+ */
+
+struct netif *
+ip_route(struct ip_addr *dest)
+{
+  struct netif *netif;
+
+  /* iterate through netifs */
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+    /* network mask matches? */
+    if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) {
+      /* return netif on which to forward IP packet */
+      return netif;
+    }
+  }
+  /* no matching netif found, use default netif */
+  return netif_default;
+}
+#if IP_FORWARD
+
+/**
+ * Forwards an IP packet. It finds an appropriate route for the
+ * packet, decrements the TTL value of the packet, adjusts the
+ * checksum and outputs the packet on the appropriate interface.
+ */
+
+static struct netif *
+ip_forward(struct pbuf *p, struct ip_hdr *iphdr, struct netif *inp)
+{
+  struct netif *netif;
+
+  PERF_START;
+  /* Find network interface where to forward this IP packet to. */
+  netif = ip_route((struct ip_addr *)&(iphdr->dest));
+  if (netif == NULL) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_forward: no forwarding route for 0x%"X32_F" found\n",
+                      iphdr->dest.addr));
+    snmp_inc_ipoutnoroutes();
+    return (struct netif *)NULL;
+  }
+  /* Do not forward packets onto the same network interface on which
+   * they arrived. */
+  if (netif == inp) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_forward: not bouncing packets back on incoming interface.\n"));
+    snmp_inc_ipoutnoroutes();
+    return (struct netif *)NULL;
+  }
+
+  /* decrement TTL */
+  IPH_TTL_SET(iphdr, IPH_TTL(iphdr) - 1);
+  /* send ICMP if TTL == 0 */
+  if (IPH_TTL(iphdr) == 0) {
+    snmp_inc_ipinhdrerrors();
+    /* Don't send ICMP messages in response to ICMP messages */
+    if (IPH_PROTO(iphdr) != IP_PROTO_ICMP) {
+      icmp_time_exceeded(p, ICMP_TE_TTL);
+    }
+    return (struct netif *)NULL;
+  }
+
+  /* Incrementally update the IP checksum. */
+  if (IPH_CHKSUM(iphdr) >= htons(0xffff - 0x100)) {
+    IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100) + 1);
+  } else {
+    IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100));
+  }
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to 0x%"X32_F"\n",
+                    iphdr->dest.addr));
+
+  IP_STATS_INC(ip.fw);
+  IP_STATS_INC(ip.xmit);
+  snmp_inc_ipforwdatagrams();
+
+  PERF_STOP("ip_forward");
+  /* transmit pbuf on chosen interface */
+  netif->output(netif, p, (struct ip_addr *)&(iphdr->dest));
+  return netif;
+}
+#endif /* IP_FORWARD */
+
+/**
+ * This function is called by the network interface device driver when
+ * an IP packet is received. The function does the basic checks of the
+ * IP header such as packet size being at least larger than the header
+ * size etc. If the packet was not destined for us, the packet is
+ * forwarded (using ip_forward). The IP checksum is always checked.
+ *
+ * Finally, the packet is sent to the upper layer protocol input function.
+ * 
+ * 
+ * 
+ */
+
+err_t
+ip_input(struct pbuf *p, struct netif *inp) {
+  struct ip_hdr *iphdr;
+  struct netif *netif;
+  u16_t iphdrlen;
+
+  IP_STATS_INC(ip.recv);
+  snmp_inc_ipinreceives();
+
+  /* identify the IP header */
+  iphdr = p->payload;
+  if (IPH_V(iphdr) != 4) {
+    LWIP_DEBUGF(IP_DEBUG | 1, ("IP packet dropped due to bad version number %"U16_F"\n", IPH_V(iphdr)));
+    ip_debug_print(p);
+    pbuf_free(p);
+    IP_STATS_INC(ip.err);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipinhdrerrors();
+    return ERR_OK;
+  }
+  /* obtain IP header length in number of 32-bit words */
+  iphdrlen = IPH_HL(iphdr);
+  /* calculate IP header length in bytes */
+  iphdrlen *= 4;
+
+  /* header length exceeds first pbuf length? */
+  if (iphdrlen > p->len) {
+    LWIP_DEBUGF(IP_DEBUG | 2, ("IP header (len %"U16_F") does not fit in first pbuf (len %"U16_F"), IP packet droppped.\n",
+      iphdrlen, p->len));
+    /* free (drop) packet pbufs */
+    pbuf_free(p);
+    IP_STATS_INC(ip.lenerr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipindiscards();
+    return ERR_OK;
+  }
+
+  /* verify checksum */
+#if CHECKSUM_CHECK_IP
+  if (inet_chksum(iphdr, iphdrlen) != 0) {
+
+    LWIP_DEBUGF(IP_DEBUG | 2, ("Checksum (0x%"X16_F") failed, IP packet dropped.\n", inet_chksum(iphdr, iphdrlen)));
+    ip_debug_print(p);
+    pbuf_free(p);
+    IP_STATS_INC(ip.chkerr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipinhdrerrors();
+    return ERR_OK;
+  }
+#endif
+
+  /* Trim pbuf. This should have been done at the netif layer,
+   * but we'll do it anyway just to be sure that its done. */
+  pbuf_realloc(p, ntohs(IPH_LEN(iphdr)));
+
+  /* match packet against an interface, i.e. is this packet for us? */
+  for (netif = netif_list; netif != NULL; netif = netif->next) {
+
+    LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest 0x%"X32_F" netif->ip_addr 0x%"X32_F" (0x%"X32_F", 0x%"X32_F", 0x%"X32_F")\n",
+      iphdr->dest.addr, netif->ip_addr.addr,
+      iphdr->dest.addr & netif->netmask.addr,
+      netif->ip_addr.addr & netif->netmask.addr,
+      iphdr->dest.addr & ~(netif->netmask.addr)));
+
+    /* interface is up and configured? */
+    if ((netif_is_up(netif)) && (!ip_addr_isany(&(netif->ip_addr))))
+    {
+      /* unicast to this interface address? */
+      if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr)) ||
+         /* or broadcast on this interface network address? */
+         ip_addr_isbroadcast(&(iphdr->dest), netif)) {
+        LWIP_DEBUGF(IP_DEBUG, ("ip_input: packet accepted on interface %c%c\n",
+          netif->name[0], netif->name[1]));
+        /* break out of for loop */
+        break;
+      }
+    }
+  }
+#if LWIP_DHCP
+  /* Pass DHCP messages regardless of destination address. DHCP traffic is addressed
+   * using link layer addressing (such as Ethernet MAC) so we must not filter on IP.
+   * According to RFC 1542 section 3.1.1, referred by RFC 2131).
+   */
+  if (netif == NULL) {
+    /* remote port is DHCP server? */
+    if (IPH_PROTO(iphdr) == IP_PROTO_UDP) {
+      LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: UDP packet to DHCP client port %"U16_F"\n",
+        ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest)));
+      if (ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest) == DHCP_CLIENT_PORT) {
+        LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: DHCP packet accepted.\n"));
+        netif = inp;
+      }
+    }
+  }
+#endif /* LWIP_DHCP */
+  /* packet not for us? */
+  if (netif == NULL) {
+    /* packet not for us, route or discard */
+    LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: packet not for us.\n"));
+#if IP_FORWARD
+    /* non-broadcast packet? */
+    if (!ip_addr_isbroadcast(&(iphdr->dest), inp)) {
+      /* try to forward IP packet on (other) interfaces */
+      ip_forward(p, iphdr, inp);
+    }
+    else
+#endif /* IP_FORWARD */
+    {
+      snmp_inc_ipinaddrerrors();
+      snmp_inc_ipindiscards();
+    }
+    pbuf_free(p);
+    return ERR_OK;
+  }
+  /* packet consists of multiple fragments? */
+  if ((IPH_OFFSET(iphdr) & htons(IP_OFFMASK | IP_MF)) != 0) {
+#if IP_REASSEMBLY /* packet fragment reassembly code present? */
+    LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip_reass()\n",
+      ntohs(IPH_ID(iphdr)), p->tot_len, ntohs(IPH_LEN(iphdr)), !!(IPH_OFFSET(iphdr) & htons(IP_MF)), (ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)*8));
+    /* reassemble the packet*/
+    p = ip_reass(p);
+    /* packet not fully reassembled yet? */
+    if (p == NULL) {
+      return ERR_OK;
+    }
+    iphdr = p->payload;
+#else /* IP_REASSEMBLY == 0, no packet fragment reassembly code present */
+    pbuf_free(p);
+    LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since it was fragmented (0x%"X16_F") (while IP_REASSEMBLY == 0).\n",
+      ntohs(IPH_OFFSET(iphdr))));
+    IP_STATS_INC(ip.opterr);
+    IP_STATS_INC(ip.drop);
+    /* unsupported protocol feature */
+    snmp_inc_ipinunknownprotos();
+    return ERR_OK;
+#endif /* IP_REASSEMBLY */
+  }
+
+#if IP_OPTIONS == 0 /* no support for IP options in the IP header? */
+  if (iphdrlen > IP_HLEN) {
+    LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since there were IP options (while IP_OPTIONS == 0).\n"));
+    pbuf_free(p);
+    IP_STATS_INC(ip.opterr);
+    IP_STATS_INC(ip.drop);
+    /* unsupported protocol feature */
+    snmp_inc_ipinunknownprotos();
+    return ERR_OK;
+  }
+#endif /* IP_OPTIONS == 0 */
+
+  /* send to upper layers */
+  LWIP_DEBUGF(IP_DEBUG, ("ip_input: \n"));
+  ip_debug_print(p);
+  LWIP_DEBUGF(IP_DEBUG, ("ip_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len));
+
+#if LWIP_RAW
+  /* raw input did not eat the packet? */
+  if (raw_input(p, inp) == 0) {
+#endif /* LWIP_RAW */
+
+  switch (IPH_PROTO(iphdr)) {
+#if LWIP_UDP
+  case IP_PROTO_UDP:
+  case IP_PROTO_UDPLITE:
+    snmp_inc_ipindelivers();
+    udp_input(p, inp);
+    break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+  case IP_PROTO_TCP:
+    snmp_inc_ipindelivers();
+    tcp_input(p, inp);
+    break;
+#endif /* LWIP_TCP */
+  case IP_PROTO_ICMP:
+    snmp_inc_ipindelivers();
+    icmp_input(p, inp);
+    break;
+  default:
+    /* send ICMP destination protocol unreachable unless is was a broadcast */
+    if (!ip_addr_isbroadcast(&(iphdr->dest), inp) &&
+        !ip_addr_ismulticast(&(iphdr->dest))) {
+      p->payload = iphdr;
+      icmp_dest_unreach(p, ICMP_DUR_PROTO);
+    }
+    pbuf_free(p);
+
+    LWIP_DEBUGF(IP_DEBUG | 2, ("Unsupported transport protocol %"U16_F"\n", IPH_PROTO(iphdr)));
+
+    IP_STATS_INC(ip.proterr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipinunknownprotos();
+  }
+#if LWIP_RAW
+  } /* LWIP_RAW */
+#endif
+  return ERR_OK;
+}
+
+/**
+ * Sends an IP packet on a network interface. This function constructs
+ * the IP header and calculates the IP header checksum. If the source
+ * IP address is NULL, the IP address of the outgoing network
+ * interface is filled in as source address.
+ *
+ * @note ip_id: RFC791 "some host may be able to simply use
+ *  unique identifiers independent of destination"
+ */
+
+err_t
+ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+             u8_t ttl, u8_t tos,
+             u8_t proto, struct netif *netif)
+{
+  struct ip_hdr *iphdr;
+  static u16_t ip_id = 0;
+
+  snmp_inc_ipoutrequests();
+
+  if (dest != IP_HDRINCL) {
+    if (pbuf_header(p, IP_HLEN)) {
+      LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: not enough room for IP header in pbuf\n"));
+
+      IP_STATS_INC(ip.err);
+      snmp_inc_ipoutdiscards();
+      return ERR_BUF;
+    }
+
+    iphdr = p->payload;
+
+    IPH_TTL_SET(iphdr, ttl);
+    IPH_PROTO_SET(iphdr, proto);
+
+    ip_addr_set(&(iphdr->dest), dest);
+
+    IPH_VHLTOS_SET(iphdr, 4, IP_HLEN / 4, tos);
+    IPH_LEN_SET(iphdr, htons(p->tot_len));
+    IPH_OFFSET_SET(iphdr, htons(IP_DF));
+    IPH_ID_SET(iphdr, htons(ip_id));
+    ++ip_id;
+
+    if (ip_addr_isany(src)) {
+      ip_addr_set(&(iphdr->src), &(netif->ip_addr));
+    } else {
+      ip_addr_set(&(iphdr->src), src);
+    }
+
+    IPH_CHKSUM_SET(iphdr, 0);
+#if CHECKSUM_GEN_IP
+    IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
+#endif
+  } else {
+    iphdr = p->payload;
+    dest = &(iphdr->dest);
+  }
+
+#if IP_FRAG
+  /* don't fragment if interface has mtu set to 0 [loopif] */
+  if (netif->mtu && (p->tot_len > netif->mtu))
+    return ip_frag(p,netif,dest);
+#endif
+
+  IP_STATS_INC(ip.xmit);
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c%"U16_F"\n", netif->name[0], netif->name[1], netif->num));
+  ip_debug_print(p);
+
+  LWIP_DEBUGF(IP_DEBUG, ("netif->output()"));
+
+  return netif->output(netif, p, dest);
+}
+
+/**
+ * Simple interface to ip_output_if. It finds the outgoing network
+ * interface and calls upon ip_output_if to do the actual work.
+ */
+
+err_t
+ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+          u8_t ttl, u8_t tos, u8_t proto)
+{
+  struct netif *netif;
+
+  if ((netif = ip_route(dest)) == NULL) {
+    LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: No route to 0x%"X32_F"\n", dest->addr));
+
+    IP_STATS_INC(ip.rterr);
+    snmp_inc_ipoutnoroutes();
+    return ERR_RTE;
+  }
+
+  return ip_output_if(p, src, dest, ttl, tos, proto, netif);
+}
+
+#if IP_DEBUG
+void
+ip_debug_print(struct pbuf *p)
+{
+  struct ip_hdr *iphdr = p->payload;
+  u8_t *payload;
+
+  payload = (u8_t *)iphdr + IP_HLEN;
+
+  LWIP_DEBUGF(IP_DEBUG, ("IP header:\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" |%2"S16_F" |  0x%02"X16_F" |     %5"U16_F"     | (v, hl, tos, len)\n",
+                    IPH_V(iphdr),
+                    IPH_HL(iphdr),
+                    IPH_TOS(iphdr),
+                    ntohs(IPH_LEN(iphdr))));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|    %5"U16_F"      |%"U16_F"%"U16_F"%"U16_F"|    %4"U16_F"   | (id, flags, offset)\n",
+                    ntohs(IPH_ID(iphdr)),
+                    ntohs(IPH_OFFSET(iphdr)) >> 15 & 1,
+                    ntohs(IPH_OFFSET(iphdr)) >> 14 & 1,
+                    ntohs(IPH_OFFSET(iphdr)) >> 13 & 1,
+                    ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3"U16_F"  |  %3"U16_F"  |    0x%04"X16_F"     | (ttl, proto, chksum)\n",
+                    IPH_TTL(iphdr),
+                    IPH_PROTO(iphdr),
+                    ntohs(IPH_CHKSUM(iphdr))));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  | (src)\n",
+                    ip4_addr1(&iphdr->src),
+                    ip4_addr2(&iphdr->src),
+                    ip4_addr3(&iphdr->src),
+                    ip4_addr4(&iphdr->src)));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  | (dest)\n",
+                    ip4_addr1(&iphdr->dest),
+                    ip4_addr2(&iphdr->dest),
+                    ip4_addr3(&iphdr->dest),
+                    ip4_addr4(&iphdr->dest)));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+}
+#endif /* IP_DEBUG */
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/ipv4/ip_addr.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/ipv4/ip_addr.c
new file mode 100644
index 0000000..56b1cd7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/ipv4/ip_addr.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/ip_addr.h"
+#include "lwip/inet.h"
+#include "lwip/netif.h"
+
+#define IP_ADDR_ANY_VALUE 0x00000000UL
+#define IP_ADDR_BROADCAST_VALUE 0xffffffffUL
+
+/* used by IP_ADDR_ANY and IP_ADDR_BROADCAST in ip_addr.h */
+const struct ip_addr ip_addr_any = { IP_ADDR_ANY_VALUE };
+const struct ip_addr ip_addr_broadcast = { IP_ADDR_BROADCAST_VALUE };
+
+/* Determine if an address is a broadcast address on a network interface 
+ * 
+ * @param addr address to be checked
+ * @param netif the network interface against which the address is checked
+ * @return returns non-zero if the address is a broadcast address
+ *
+ */
+
+u8_t ip_addr_isbroadcast(struct ip_addr *addr, struct netif *netif)
+{
+  u32_t addr2test;
+
+  addr2test = addr->addr;
+  /* all ones (broadcast) or all zeroes (old skool broadcast) */
+  if ((~addr2test == IP_ADDR_ANY_VALUE) ||
+      (addr2test == IP_ADDR_ANY_VALUE))
+    return 1;
+  /* no broadcast support on this network interface? */
+  else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0)
+    /* the given address cannot be a broadcast address
+     * nor can we check against any broadcast addresses */
+    return 0;
+  /* address matches network interface address exactly? => no broadcast */
+  else if (addr2test == netif->ip_addr.addr)
+    return 0;
+  /*  on the same (sub) network... */
+  else if (ip_addr_netcmp(addr, &(netif->ip_addr), &(netif->netmask))
+         /* ...and host identifier bits are all ones? =>... */
+          && ((addr2test & ~netif->netmask.addr) ==
+           (IP_ADDR_BROADCAST_VALUE & ~netif->netmask.addr)))
+    /* => network broadcast address */
+    return 1;
+  else
+    return 0;
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/ipv4/ip_frag.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/ipv4/ip_frag.c
new file mode 100644
index 0000000..0256a50
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/ipv4/ip_frag.c
@@ -0,0 +1,388 @@
+/* @file
+ * 
+ * This is the IP packet segmentation and reassembly implementation.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Jani Monoses  
+ * original reassembly code by Adam Dunkels 
+ * 
+ */
+
+#include 
+
+#include "lwip/opt.h"
+#include "lwip/ip.h"
+#include "lwip/ip_frag.h"
+#include "lwip/netif.h"
+#include "lwip/snmp.h"
+#include "lwip/stats.h"
+
+static u8_t ip_reassbuf[IP_HLEN + IP_REASS_BUFSIZE];
+static u8_t ip_reassbitmap[IP_REASS_BUFSIZE / (8 * 8) + 1];
+static const u8_t bitmap_bits[8] = { 0xff, 0x7f, 0x3f, 0x1f,
+  0x0f, 0x07, 0x03, 0x01
+};
+static u16_t ip_reasslen;
+static u8_t ip_reassflags;
+#define IP_REASS_FLAG_LASTFRAG 0x01
+
+static u8_t ip_reasstmr;
+
+/*
+ * Copy len bytes from offset in pbuf to buffer 
+ *
+ * helper used by both ip_reass and ip_frag
+ */
+static struct pbuf *
+copy_from_pbuf(struct pbuf *p, u16_t * offset,
+           u8_t * buffer, u16_t len)
+{
+  u16_t l;
+
+  p->payload = (u8_t *)p->payload + *offset;
+  p->len -= *offset;
+  while (len) {
+    l = len < p->len ? len : p->len;
+    memcpy(buffer, p->payload, l);
+    buffer += l;
+    len -= l;
+    if (len)
+      p = p->next;
+    else
+      *offset = l;
+  }
+  return p;
+}
+
+
+/**
+ * Initializes IP reassembly and fragmentation states.
+ */
+void
+ip_frag_init(void)
+{
+  ip_reasstmr = 0;
+  ip_reassflags = 0;
+  ip_reasslen = 0;
+  memset(ip_reassbitmap, 0, sizeof(ip_reassbitmap));
+}
+
+/**
+ * Reassembly timer base function
+ * for both NO_SYS == 0 and 1 (!).
+ *
+ * Should be called every 1000 msec.
+ */
+void
+ip_reass_tmr(void)
+{
+  if (ip_reasstmr > 0) {
+    ip_reasstmr--;
+    LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer dec %"U16_F"\n",(u16_t)ip_reasstmr));
+    if (ip_reasstmr == 0) {
+      /* reassembly timed out */
+      snmp_inc_ipreasmfails();
+    }
+  }
+}
+
+/**
+ * Reassembles incoming IP fragments into an IP datagram.
+ *
+ * @param p points to a pbuf chain of the fragment
+ * @return NULL if reassembly is incomplete, ? otherwise
+ */
+struct pbuf *
+ip_reass(struct pbuf *p)
+{
+  struct pbuf *q;
+  struct ip_hdr *fraghdr, *iphdr;
+  u16_t offset, len;
+  u16_t i;
+
+  IPFRAG_STATS_INC(ip_frag.recv);
+  snmp_inc_ipreasmreqds();
+
+  iphdr = (struct ip_hdr *) ip_reassbuf;
+  fraghdr = (struct ip_hdr *) p->payload;
+  /* If ip_reasstmr is zero, no packet is present in the buffer, so we
+     write the IP header of the fragment into the reassembly
+     buffer. The timer is updated with the maximum age. */
+  if (ip_reasstmr == 0) {
+    LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: new packet\n"));
+    memcpy(iphdr, fraghdr, IP_HLEN);
+    ip_reasstmr = IP_REASS_MAXAGE;
+    ip_reassflags = 0;
+    /* Clear the bitmap. */
+    memset(ip_reassbitmap, 0, sizeof(ip_reassbitmap));
+  }
+
+  /* Check if the incoming fragment matches the one currently present
+     in the reasembly buffer. If so, we proceed with copying the
+     fragment into the buffer. */
+  if (ip_addr_cmp(&iphdr->src, &fraghdr->src) &&
+      ip_addr_cmp(&iphdr->dest, &fraghdr->dest) &&
+      IPH_ID(iphdr) == IPH_ID(fraghdr)) {
+    LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: matching previous fragment ID=%"X16_F"\n",
+      ntohs(IPH_ID(fraghdr))));
+    IPFRAG_STATS_INC(ip_frag.cachehit);
+    /* Find out the offset in the reassembly buffer where we should
+       copy the fragment. */
+    len = ntohs(IPH_LEN(fraghdr)) - IPH_HL(fraghdr) * 4;
+    offset = (ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) * 8;
+
+    /* If the offset or the offset + fragment length overflows the
+       reassembly buffer, we discard the entire packet. */
+    if ((offset > IP_REASS_BUFSIZE) || ((offset + len) > IP_REASS_BUFSIZE)) {
+      LWIP_DEBUGF(IP_REASS_DEBUG,
+       ("ip_reass: fragment outside of buffer (%"S16_F":%"S16_F"/%"S16_F").\n", offset,
+        offset + len, IP_REASS_BUFSIZE));
+      ip_reasstmr = 0;
+      snmp_inc_ipreasmfails();
+      goto nullreturn;
+    }
+
+    /* Copy the fragment into the reassembly buffer, at the right
+       offset. */
+    LWIP_DEBUGF(IP_REASS_DEBUG,
+     ("ip_reass: copying with offset %"S16_F" into %"S16_F":%"S16_F"\n", offset,
+      IP_HLEN + offset, IP_HLEN + offset + len));
+    i = IPH_HL(fraghdr) * 4;
+    copy_from_pbuf(p, &i, &ip_reassbuf[IP_HLEN + offset], len);
+
+    /* Update the bitmap. */
+    if (offset / (8 * 8) == (offset + len) / (8 * 8)) {
+      LWIP_DEBUGF(IP_REASS_DEBUG,
+       ("ip_reass: updating single byte in bitmap.\n"));
+      /* If the two endpoints are in the same byte, we only update that byte. */
+      LWIP_ASSERT("offset / (8 * 8) < sizeof(ip_reassbitmap)",
+                   offset / (8 * 8) < sizeof(ip_reassbitmap));
+      ip_reassbitmap[offset / (8 * 8)] |=
+        bitmap_bits[(offset / 8) & 7] &
+        ~bitmap_bits[((offset + len) / 8) & 7];
+    } else {
+      /* If the two endpoints are in different bytes, we update the
+         bytes in the endpoints and fill the stuff inbetween with
+         0xff. */
+      LWIP_ASSERT("offset / (8 * 8) < sizeof(ip_reassbitmap)",
+                   offset / (8 * 8) < sizeof(ip_reassbitmap));
+      ip_reassbitmap[offset / (8 * 8)] |= bitmap_bits[(offset / 8) & 7];
+      LWIP_DEBUGF(IP_REASS_DEBUG,
+       ("ip_reass: updating many bytes in bitmap (%"S16_F":%"S16_F").\n",
+        1 + offset / (8 * 8), (offset + len) / (8 * 8)));
+      for (i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) {
+        ip_reassbitmap[i] = 0xff;
+      }
+      LWIP_ASSERT("(offset + len) / (8 * 8) < sizeof(ip_reassbitmap)",
+                   (offset + len) / (8 * 8) < sizeof(ip_reassbitmap));
+      ip_reassbitmap[(offset + len) / (8 * 8)] |=
+        ~bitmap_bits[((offset + len) / 8) & 7];
+    }
+
+    /* If this fragment has the More Fragments flag set to zero, we
+       know that this is the last fragment, so we can calculate the
+       size of the entire packet. We also set the
+       IP_REASS_FLAG_LASTFRAG flag to indicate that we have received
+       the final fragment. */
+
+    if ((ntohs(IPH_OFFSET(fraghdr)) & IP_MF) == 0) {
+      ip_reassflags |= IP_REASS_FLAG_LASTFRAG;
+      ip_reasslen = offset + len;
+      LWIP_DEBUGF(IP_REASS_DEBUG,
+       ("ip_reass: last fragment seen, total len %"S16_F"\n",
+        ip_reasslen));
+    }
+
+    /* Finally, we check if we have a full packet in the buffer. We do
+       this by checking if we have the last fragment and if all bits
+       in the bitmap are set. */
+    if (ip_reassflags & IP_REASS_FLAG_LASTFRAG) {
+      /* Check all bytes up to and including all but the last byte in
+         the bitmap. */
+      LWIP_ASSERT("ip_reasslen / (8 * 8) - 1 < sizeof(ip_reassbitmap)",
+                   ip_reasslen / (8 * 8) - 1 < ((u16_t) sizeof(ip_reassbitmap)));
+      for (i = 0; i < ip_reasslen / (8 * 8) - 1; ++i) {
+        if (ip_reassbitmap[i] != 0xff) {
+          LWIP_DEBUGF(IP_REASS_DEBUG,
+           ("ip_reass: last fragment seen, bitmap %"S16_F"/%"S16_F" failed (%"X16_F")\n",
+            i, ip_reasslen / (8 * 8) - 1, ip_reassbitmap[i]));
+          goto nullreturn;
+        }
+      }
+      /* Check the last byte in the bitmap. It should contain just the
+         right amount of bits. */
+      LWIP_ASSERT("ip_reasslen / (8 * 8) < sizeof(ip_reassbitmap)",
+                   ip_reasslen / (8 * 8) < sizeof(ip_reassbitmap));
+      if (ip_reassbitmap[ip_reasslen / (8 * 8)] !=
+        (u8_t) ~ bitmap_bits[ip_reasslen / 8 & 7]) {
+         LWIP_DEBUGF(IP_REASS_DEBUG,
+          ("ip_reass: last fragment seen, bitmap %"S16_F" didn't contain %"X16_F" (%"X16_F")\n",
+        ip_reasslen / (8 * 8), ~bitmap_bits[ip_reasslen / 8 & 7],
+        ip_reassbitmap[ip_reasslen / (8 * 8)]));
+        goto nullreturn;
+      }
+
+      /* Pretend to be a "normal" (i.e., not fragmented) IP packet
+         from now on. */
+      ip_reasslen += IP_HLEN;
+
+      IPH_LEN_SET(iphdr, htons(ip_reasslen));
+      IPH_OFFSET_SET(iphdr, 0);
+      IPH_CHKSUM_SET(iphdr, 0);
+      IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
+
+      /* If we have come this far, we have a full packet in the
+         buffer, so we allocate a pbuf and copy the packet into it. We
+         also reset the timer. */
+      ip_reasstmr = 0;
+      pbuf_free(p);
+      p = pbuf_alloc(PBUF_LINK, ip_reasslen, PBUF_POOL);
+      if (p != NULL) {
+        i = 0;
+        for (q = p; q != NULL; q = q->next) {
+          /* Copy enough bytes to fill this pbuf in the chain. The
+             available data in the pbuf is given by the q->len variable. */
+          LWIP_DEBUGF(IP_REASS_DEBUG,
+           ("ip_reass: memcpy from %p (%"S16_F") to %p, %"S16_F" bytes\n",
+            (void *)&ip_reassbuf[i], i, q->payload,
+            q->len > ip_reasslen - i ? ip_reasslen - i : q->len));
+          memcpy(q->payload, &ip_reassbuf[i],
+            q->len > ip_reasslen - i ? ip_reasslen - i : q->len);
+          i += q->len;
+        }
+        IPFRAG_STATS_INC(ip_frag.fw);
+        snmp_inc_ipreasmoks();
+      } else {
+        LWIP_DEBUGF(IP_REASS_DEBUG,
+          ("ip_reass: pbuf_alloc(PBUF_LINK, ip_reasslen=%"U16_F", PBUF_POOL) failed\n", ip_reasslen));
+        IPFRAG_STATS_INC(ip_frag.memerr);
+        snmp_inc_ipreasmfails();
+      }
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: p %p\n", (void*)p));
+      return p;
+    }
+  }
+
+nullreturn:
+  IPFRAG_STATS_INC(ip_frag.drop);
+  pbuf_free(p);
+  return NULL;
+}
+
+static u8_t buf[MEM_ALIGN_SIZE(IP_FRAG_MAX_MTU)];
+
+/**
+ * Fragment an IP datagram if too large for the netif.
+ *
+ * Chop the datagram in MTU sized chunks and send them in order
+ * by using a fixed size static memory buffer (PBUF_ROM)
+ */
+err_t 
+ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest)
+{
+  struct pbuf *rambuf;
+  struct pbuf *header;
+  struct ip_hdr *iphdr;
+  u16_t nfb = 0;
+  u16_t left, cop;
+  u16_t mtu = netif->mtu;
+  u16_t ofo, omf;
+  u16_t last;
+  u16_t poff = IP_HLEN;
+  u16_t tmp;
+
+  /* Get a RAM based MTU sized pbuf */
+  rambuf = pbuf_alloc(PBUF_LINK, 0, PBUF_REF);
+  if (rambuf == NULL) {
+    LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_frag: pbuf_alloc(PBUF_LINK, 0, PBUF_REF) failed\n"));
+    return ERR_MEM;
+  }
+  rambuf->tot_len = rambuf->len = mtu;
+  rambuf->payload = MEM_ALIGN((void *)buf);
+
+  /* Copy the IP header in it */
+  iphdr = rambuf->payload;
+  memcpy(iphdr, p->payload, IP_HLEN);
+
+  /* Save original offset */
+  tmp = ntohs(IPH_OFFSET(iphdr));
+  ofo = tmp & IP_OFFMASK;
+  omf = tmp & IP_MF;
+
+  left = p->tot_len - IP_HLEN;
+
+  while (left) {
+    last = (left <= mtu - IP_HLEN);
+
+    /* Set new offset and MF flag */
+    ofo += nfb;
+    tmp = omf | (IP_OFFMASK & (ofo));
+    if (!last)
+      tmp = tmp | IP_MF;
+    IPH_OFFSET_SET(iphdr, htons(tmp));
+
+    /* Fill this fragment */
+    nfb = (mtu - IP_HLEN) / 8;
+    cop = last ? left : nfb * 8;
+
+    p = copy_from_pbuf(p, &poff, (u8_t *) iphdr + IP_HLEN, cop);
+
+    /* Correct header */
+    IPH_LEN_SET(iphdr, htons(cop + IP_HLEN));
+    IPH_CHKSUM_SET(iphdr, 0);
+    IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
+
+    if (last)
+      pbuf_realloc(rambuf, left + IP_HLEN);
+    /* This part is ugly: we alloc a RAM based pbuf for 
+     * the link level header for each chunk and then 
+     * free it.A PBUF_ROM style pbuf for which pbuf_header
+     * worked would make things simpler.
+     */
+    header = pbuf_alloc(PBUF_LINK, 0, PBUF_RAM);
+    if (header != NULL) {
+      pbuf_chain(header, rambuf);
+      netif->output(netif, header, dest);
+      IPFRAG_STATS_INC(ip_frag.xmit);
+      snmp_inc_ipfragcreates();
+      pbuf_free(header);
+    } else {
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_frag: pbuf_alloc() for header failed\n"));
+      pbuf_free(rambuf);      
+      return ERR_MEM;    
+    }
+    left -= cop;
+  }
+  pbuf_free(rambuf);
+  snmp_inc_ipfragoks();
+  return ERR_OK;
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/mem.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/mem.c
new file mode 100644
index 0000000..4d4cb1d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/mem.c
@@ -0,0 +1,414 @@
+/** @file
+ *
+ * Dynamic memory manager
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include 
+
+#include "lwip/arch.h"
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+
+#include "lwip/sys.h"
+
+#include "lwip/stats.h"
+
+#if (MEM_LIBC_MALLOC == 0)
+/* lwIP replacement for your libc malloc() */
+
+struct mem {
+  mem_size_t next, prev;
+#if MEM_ALIGNMENT == 1
+  u8_t used;
+#elif MEM_ALIGNMENT == 2
+  u16_t used;
+#elif MEM_ALIGNMENT == 4
+  u32_t used;
+#elif MEM_ALIGNMENT == 8
+  u64_t used;
+#else
+#error "unhandled MEM_ALIGNMENT size"
+#endif /* MEM_ALIGNMENT */
+};
+
+static struct mem *ram_end;
+#if 1
+/* Adam original */
+static u8_t ram[MEM_SIZE + sizeof(struct mem) + MEM_ALIGNMENT];
+#else
+/* Christiaan alignment fix */
+static u8_t *ram;
+static struct mem ram_heap[1 + ( (MEM_SIZE + sizeof(struct mem) - 1) / sizeof(struct mem))];
+#endif
+
+#define MIN_SIZE 12
+#if 0 /* this one does not align correctly for some, resulting in crashes */
+#define SIZEOF_STRUCT_MEM (unsigned int)MEM_ALIGN_SIZE(sizeof(struct mem))
+#else
+#define SIZEOF_STRUCT_MEM (sizeof(struct mem) + \
+                          (((sizeof(struct mem) % MEM_ALIGNMENT) == 0)? 0 : \
+                          (4 - (sizeof(struct mem) % MEM_ALIGNMENT))))
+#endif
+
+static struct mem *lfree;   /* pointer to the lowest free block */
+
+static sys_sem_t mem_sem;
+
+static void
+plug_holes(struct mem *mem)
+{
+  struct mem *nmem;
+  struct mem *pmem;
+
+  LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram);
+  LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end);
+  LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0);
+
+  /* plug hole forward */
+  LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE", mem->next <= MEM_SIZE);
+
+  nmem = (struct mem *)&ram[mem->next];
+  if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) {
+    if (lfree == nmem) {
+      lfree = mem;
+    }
+    mem->next = nmem->next;
+    ((struct mem *)&ram[nmem->next])->prev = (u8_t *)mem - ram;
+  }
+
+  /* plug hole backward */
+  pmem = (struct mem *)&ram[mem->prev];
+  if (pmem != mem && pmem->used == 0) {
+    if (lfree == mem) {
+      lfree = pmem;
+    }
+    pmem->next = mem->next;
+    ((struct mem *)&ram[mem->next])->prev = (u8_t *)pmem - ram;
+  }
+}
+
+void
+mem_init(void)
+{
+  struct mem *mem;
+
+#if 1
+  /* Adam original */
+#else
+  /* Christiaan alignment fix */
+  ram = (u8_t*)ram_heap;
+#endif
+  memset(ram, 0, MEM_SIZE);
+  mem = (struct mem *)ram;
+  mem->next = MEM_SIZE;
+  mem->prev = 0;
+  mem->used = 0;
+  ram_end = (struct mem *)&ram[MEM_SIZE];
+  ram_end->used = 1;
+  ram_end->next = MEM_SIZE;
+  ram_end->prev = MEM_SIZE;
+
+  mem_sem = sys_sem_new(1);
+
+  lfree = (struct mem *)ram;
+
+#if MEM_STATS
+  lwip_stats.mem.avail = MEM_SIZE;
+#endif /* MEM_STATS */
+}
+
+void
+mem_free(void *rmem)
+{
+  struct mem *mem;
+
+  if (rmem == NULL) {
+    LWIP_DEBUGF(MEM_DEBUG | DBG_TRACE | 2, ("mem_free(p == NULL) was called.\n"));
+    return;
+  }
+
+  sys_sem_wait(mem_sem);
+
+  LWIP_ASSERT("mem_free: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
+    (u8_t *)rmem < (u8_t *)ram_end);
+
+  if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
+    LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_free: illegal memory\n"));
+#if MEM_STATS
+    ++lwip_stats.mem.err;
+#endif /* MEM_STATS */
+    sys_sem_signal(mem_sem);
+    return;
+  }
+  mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM);
+
+  LWIP_ASSERT("mem_free: mem->used", mem->used);
+
+  mem->used = 0;
+
+  if (mem < lfree) {
+    lfree = mem;
+  }
+
+#if MEM_STATS
+  lwip_stats.mem.used -= mem->next - ((u8_t *)mem - ram);
+
+#endif /* MEM_STATS */
+  plug_holes(mem);
+  sys_sem_signal(mem_sem);
+}
+
+void *
+mem_realloc(void *rmem, mem_size_t newsize)
+{
+  mem_size_t size;
+  mem_size_t ptr, ptr2;
+  struct mem *mem, *mem2;
+
+  /* Expand the size of the allocated memory region so that we can
+     adjust for alignment. */
+  if ((newsize % MEM_ALIGNMENT) != 0) {
+   newsize += MEM_ALIGNMENT - ((newsize + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT);
+  }
+
+  if (newsize > MEM_SIZE) {
+    return NULL;
+  }
+
+  sys_sem_wait(mem_sem);
+
+  LWIP_ASSERT("mem_realloc: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
+   (u8_t *)rmem < (u8_t *)ram_end);
+
+  if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
+    LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_realloc: illegal memory\n"));
+    return rmem;
+  }
+  mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM);
+
+  ptr = (u8_t *)mem - ram;
+
+  size = mem->next - ptr - SIZEOF_STRUCT_MEM;
+#if MEM_STATS
+  lwip_stats.mem.used -= (size - newsize);
+#endif /* MEM_STATS */
+
+  if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE < size) {
+    ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize;
+    mem2 = (struct mem *)&ram[ptr2];
+    mem2->used = 0;
+    mem2->next = mem->next;
+    mem2->prev = ptr;
+    mem->next = ptr2;
+    if (mem2->next != MEM_SIZE) {
+      ((struct mem *)&ram[mem2->next])->prev = ptr2;
+    }
+
+    plug_holes(mem2);
+  }
+  sys_sem_signal(mem_sem);
+  return rmem;
+}
+
+#if 1
+/**
+ * Adam's mem_malloc(), suffers from bug #17922
+ * Set if to 0 for alternative mem_malloc().
+ */
+void *
+mem_malloc(mem_size_t size)
+{
+  mem_size_t ptr, ptr2;
+  struct mem *mem, *mem2;
+
+  if (size == 0) {
+    return NULL;
+  }
+
+  /* Expand the size of the allocated memory region so that we can
+     adjust for alignment. */
+  if ((size % MEM_ALIGNMENT) != 0) {
+    size += MEM_ALIGNMENT - ((size + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT);
+  }
+
+  if (size > MEM_SIZE) {
+    return NULL;
+  }
+
+  sys_sem_wait(mem_sem);
+
+  for (ptr = (u8_t *)lfree - ram; ptr < MEM_SIZE; ptr = ((struct mem *)&ram[ptr])->next) {
+    mem = (struct mem *)&ram[ptr];
+    if (!mem->used &&
+       mem->next - (ptr + SIZEOF_STRUCT_MEM) >= size + SIZEOF_STRUCT_MEM) {
+      ptr2 = ptr + SIZEOF_STRUCT_MEM + size;
+      mem2 = (struct mem *)&ram[ptr2];
+
+      mem2->prev = ptr;
+      mem2->next = mem->next;
+      mem->next = ptr2;
+      if (mem2->next != MEM_SIZE) {
+        ((struct mem *)&ram[mem2->next])->prev = ptr2;
+      }
+
+      mem2->used = 0;
+      mem->used = 1;
+#if MEM_STATS
+      lwip_stats.mem.used += (size + SIZEOF_STRUCT_MEM);
+      /*      if (lwip_stats.mem.max < lwip_stats.mem.used) {
+        lwip_stats.mem.max = lwip_stats.mem.used;
+        } */
+      if (lwip_stats.mem.max < ptr2) {
+        lwip_stats.mem.max = ptr2;
+      }
+#endif /* MEM_STATS */
+
+      if (mem == lfree) {
+        /* Find next free block after mem */
+        while (lfree->used && lfree != ram_end) {
+          lfree = (struct mem *)&ram[lfree->next];
+        }
+        LWIP_ASSERT("mem_malloc: !lfree->used", !lfree->used);
+      }
+      sys_sem_signal(mem_sem);
+      LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.",
+       (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end);
+      LWIP_ASSERT("mem_malloc: allocated memory properly aligned.",
+       (unsigned long)((u8_t *)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0);
+      return (u8_t *)mem + SIZEOF_STRUCT_MEM;
+    }
+  }
+  LWIP_DEBUGF(MEM_DEBUG | 2, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size));
+#if MEM_STATS
+  ++lwip_stats.mem.err;
+#endif /* MEM_STATS */
+  sys_sem_signal(mem_sem);
+  return NULL;
+}
+#else
+/**
+ * Adam's mem_malloc() plus solution for bug #17922
+ */
+void *
+mem_malloc(mem_size_t size)
+{
+  mem_size_t ptr, ptr2;
+  struct mem *mem, *mem2;
+
+  if (size == 0) {
+    return NULL;
+  }
+
+  /* Expand the size of the allocated memory region so that we can
+     adjust for alignment. */
+  if ((size % MEM_ALIGNMENT) != 0) {
+    size += MEM_ALIGNMENT - ((size + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT);
+  }
+
+  if (size > MEM_SIZE) {
+    return NULL;
+  }
+
+  sys_sem_wait(mem_sem);
+
+  for (ptr = (u8_t *)lfree - ram; ptr < MEM_SIZE - size; ptr = ((struct mem *)&ram[ptr])->next) {
+    mem = (struct mem *)&ram[ptr];
+
+    if (!mem->used) {
+
+      ptr2 = ptr + SIZEOF_STRUCT_MEM + size;
+
+      if (mem->next - (ptr + (2*SIZEOF_STRUCT_MEM)) >= size) {
+        /* split large block, create empty remainder */
+        mem->next = ptr2;
+        mem->used = 1;
+        /* create mem2 struct */
+        mem2 = (struct mem *)&ram[ptr2];
+        mem2->used = 0;
+        mem2->next = mem->next;
+        mem2->prev = ptr;
+
+        if (mem2->next != MEM_SIZE) {
+          ((struct mem *)&ram[mem2->next])->prev = ptr2;
+        }
+      }
+      else if (mem->next - (ptr + SIZEOF_STRUCT_MEM) > size) {
+        /* near fit, no split, no mem2 creation,
+           round up to mem->next */
+        ptr2 = mem->next;
+        mem->used = 1;
+      }
+      else if (mem->next - (ptr + SIZEOF_STRUCT_MEM) == size) {
+        /* exact fit, do not split, no mem2 creation */
+        mem->next = ptr2;
+        mem->used = 1;
+      }
+
+      if (mem->used) {
+#if MEM_STATS
+        lwip_stats.mem.used += (size + SIZEOF_STRUCT_MEM);
+        if (lwip_stats.mem.max < ptr2) {
+          lwip_stats.mem.max = ptr2;
+        }
+#endif /* MEM_STATS */
+        if (mem == lfree) {
+          /* Find next free block after mem */
+          while (lfree->used && lfree != ram_end) {
+            lfree = (struct mem *)&ram[lfree->next];
+          }
+          LWIP_ASSERT("mem_malloc: !lfree->used", !lfree->used);
+        }
+        sys_sem_signal(mem_sem);
+        LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.",
+         (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end);
+        LWIP_ASSERT("mem_malloc: allocated memory properly aligned.",
+         (unsigned long)((u8_t *)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0);
+        return (u8_t *)mem + SIZEOF_STRUCT_MEM;
+      }
+    }
+  }
+  LWIP_DEBUGF(MEM_DEBUG | 2, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size));
+#if MEM_STATS
+  ++lwip_stats.mem.err;
+#endif /* MEM_STATS */
+  sys_sem_signal(mem_sem);
+  return NULL;
+}
+#endif
+
+#endif /* MEM_LIBC_MALLOC == 0 */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/memp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/memp.c
new file mode 100644
index 0000000..3912009
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/memp.c
@@ -0,0 +1,238 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/memp.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/udp.h"
+#include "lwip/raw.h"
+#include "lwip/tcp.h"
+#include "lwip/api.h"
+#include "lwip/api_msg.h"
+#include "lwip/tcpip.h"
+
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+
+struct memp {
+  struct memp *next;
+};
+
+#define MEMP_SIZE MEM_ALIGN_SIZE(sizeof(struct memp))
+
+static struct memp *memp_tab[MEMP_MAX];
+
+static const u16_t memp_sizes[MEMP_MAX] = {
+  MEM_ALIGN_SIZE(sizeof(struct pbuf)),
+  MEM_ALIGN_SIZE(sizeof(struct raw_pcb)),
+  MEM_ALIGN_SIZE(sizeof(struct udp_pcb)),
+  MEM_ALIGN_SIZE(sizeof(struct tcp_pcb)),
+  MEM_ALIGN_SIZE(sizeof(struct tcp_pcb_listen)),
+  MEM_ALIGN_SIZE(sizeof(struct tcp_seg)),
+  MEM_ALIGN_SIZE(sizeof(struct netbuf)),
+  MEM_ALIGN_SIZE(sizeof(struct netconn)),
+  MEM_ALIGN_SIZE(sizeof(struct api_msg)),
+  MEM_ALIGN_SIZE(sizeof(struct tcpip_msg)),
+  MEM_ALIGN_SIZE(sizeof(struct sys_timeo))
+};
+
+static const u16_t memp_num[MEMP_MAX] = {
+  MEMP_NUM_PBUF,
+  MEMP_NUM_RAW_PCB,
+  MEMP_NUM_UDP_PCB,
+  MEMP_NUM_TCP_PCB,
+  MEMP_NUM_TCP_PCB_LISTEN,
+  MEMP_NUM_TCP_SEG,
+  MEMP_NUM_NETBUF,
+  MEMP_NUM_NETCONN,
+  MEMP_NUM_API_MSG,
+  MEMP_NUM_TCPIP_MSG,
+  MEMP_NUM_SYS_TIMEOUT
+};
+
+#define MEMP_TYPE_SIZE(qty, type) \
+  ((qty) * (MEMP_SIZE + MEM_ALIGN_SIZE(sizeof(type))))
+
+static u8_t memp_memory[MEM_ALIGNMENT - 1 + 
+  MEMP_TYPE_SIZE(MEMP_NUM_PBUF, struct pbuf) +
+  MEMP_TYPE_SIZE(MEMP_NUM_RAW_PCB, struct raw_pcb) +
+  MEMP_TYPE_SIZE(MEMP_NUM_UDP_PCB, struct udp_pcb) +
+  MEMP_TYPE_SIZE(MEMP_NUM_TCP_PCB, struct tcp_pcb) +
+  MEMP_TYPE_SIZE(MEMP_NUM_TCP_PCB_LISTEN, struct tcp_pcb_listen) +
+  MEMP_TYPE_SIZE(MEMP_NUM_TCP_SEG, struct tcp_seg) +
+  MEMP_TYPE_SIZE(MEMP_NUM_NETBUF, struct netbuf) +
+  MEMP_TYPE_SIZE(MEMP_NUM_NETCONN, struct netconn) +
+  MEMP_TYPE_SIZE(MEMP_NUM_API_MSG, struct api_msg) +
+  MEMP_TYPE_SIZE(MEMP_NUM_TCPIP_MSG, struct tcpip_msg) +
+  MEMP_TYPE_SIZE(MEMP_NUM_SYS_TIMEOUT, struct sys_timeo)];
+
+#if !SYS_LIGHTWEIGHT_PROT
+static sys_sem_t mutex;
+#endif
+
+#if MEMP_SANITY_CHECK
+static int
+memp_sanity(void)
+{
+  s16_t i, c;
+  struct memp *m, *n;
+
+  for (i = 0; i < MEMP_MAX; i++) {
+    for (m = memp_tab[i]; m != NULL; m = m->next) {
+      c = 1;
+      for (n = memp_tab[i]; n != NULL; n = n->next) {
+        if (n == m && --c < 0) {
+          return 0; /* LW was: abort(); */
+        }
+      }
+    }
+  }
+  return 1;
+}
+#endif /* MEMP_SANITY_CHECK*/
+
+void
+memp_init(void)
+{
+  struct memp *memp;
+  u16_t i, j;
+
+#if MEMP_STATS
+  for (i = 0; i < MEMP_MAX; ++i) {
+    lwip_stats.memp[i].used = lwip_stats.memp[i].max =
+      lwip_stats.memp[i].err = 0;
+    lwip_stats.memp[i].avail = memp_num[i];
+  }
+#endif /* MEMP_STATS */
+
+  memp = MEM_ALIGN(memp_memory);
+  for (i = 0; i < MEMP_MAX; ++i) {
+    memp_tab[i] = NULL;
+    for (j = 0; j < memp_num[i]; ++j) {
+      memp->next = memp_tab[i];
+      memp_tab[i] = memp;
+      memp = (struct memp *)((u8_t *)memp + MEMP_SIZE + memp_sizes[i]);
+    }
+  }
+
+#if !SYS_LIGHTWEIGHT_PROT
+  mutex = sys_sem_new(1);
+#endif
+}
+
+void *
+memp_malloc(memp_t type)
+{
+  struct memp *memp;
+  void *mem;
+#if SYS_LIGHTWEIGHT_PROT
+  SYS_ARCH_DECL_PROTECT(old_level);
+#endif
+ 
+  LWIP_ASSERT("memp_malloc: type < MEMP_MAX", type < MEMP_MAX);
+
+#if SYS_LIGHTWEIGHT_PROT
+  SYS_ARCH_PROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */  
+  sys_sem_wait(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */  
+
+  memp = memp_tab[type];
+  
+  if (memp != NULL) {    
+    memp_tab[type] = memp->next;    
+    memp->next = NULL;
+#if MEMP_STATS
+    ++lwip_stats.memp[type].used;
+    if (lwip_stats.memp[type].used > lwip_stats.memp[type].max) {
+      lwip_stats.memp[type].max = lwip_stats.memp[type].used;
+    }
+#endif /* MEMP_STATS */
+    mem = (u8_t *)memp + MEMP_SIZE;
+    LWIP_ASSERT("memp_malloc: memp properly aligned",
+                ((mem_ptr_t)memp % MEM_ALIGNMENT) == 0);
+  } else {
+    LWIP_DEBUGF(MEMP_DEBUG | 2, ("memp_malloc: out of memory in pool %"S16_F"\n", type));
+#if MEMP_STATS
+    ++lwip_stats.memp[type].err;
+#endif /* MEMP_STATS */
+    mem = NULL;
+  }
+
+#if SYS_LIGHTWEIGHT_PROT
+  SYS_ARCH_UNPROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */
+  sys_sem_signal(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */  
+
+  return mem;
+}
+
+void
+memp_free(memp_t type, void *mem)
+{
+  struct memp *memp;
+#if SYS_LIGHTWEIGHT_PROT
+  SYS_ARCH_DECL_PROTECT(old_level);
+#endif /* SYS_LIGHTWEIGHT_PROT */  
+
+  if (mem == NULL) {
+    return;
+  }
+
+  memp = (struct memp *)((u8_t *)mem - MEMP_SIZE);
+
+#if SYS_LIGHTWEIGHT_PROT
+  SYS_ARCH_PROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */  
+  sys_sem_wait(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */  
+
+#if MEMP_STATS
+  lwip_stats.memp[type].used--; 
+#endif /* MEMP_STATS */
+  
+  memp->next = memp_tab[type]; 
+  memp_tab[type] = memp;
+
+#if MEMP_SANITY_CHECK
+  LWIP_ASSERT("memp sanity", memp_sanity());
+#endif  
+
+#if SYS_LIGHTWEIGHT_PROT
+  SYS_ARCH_UNPROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */
+  sys_sem_signal(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */  
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/netif.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/netif.c
new file mode 100644
index 0000000..0a78661
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/netif.c
@@ -0,0 +1,325 @@
+/**
+ * @file
+ *
+ * lwIP network interface abstraction
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/tcp.h"
+#include "lwip/snmp.h"
+
+struct netif *netif_list = NULL;
+struct netif *netif_default = NULL;
+
+/**
+ * Add a network interface to the list of lwIP netifs.
+ *
+ * @param netif a pre-allocated netif structure
+ * @param ipaddr IP address for the new netif
+ * @param netmask network mask for the new netif
+ * @param gw default gateway IP address for the new netif
+ * @param state opaque data passed to the new netif
+ * @param init callback function that initializes the interface
+ * @param input callback function that is called to pass
+ * ingress packets up in the protocol layer stack.
+ *
+ * @return netif, or NULL if failed.
+ */
+struct netif *
+netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
+  struct ip_addr *gw,
+  void *state,
+  err_t (* init)(struct netif *netif),
+  err_t (* input)(struct pbuf *p, struct netif *netif))
+{
+  static s16_t netifnum = 0;
+
+  /* reset new interface configuration state */
+  netif->ip_addr.addr = 0;
+  netif->netmask.addr = 0;
+  netif->gw.addr = 0;
+  netif->flags = 0;
+#if LWIP_DHCP
+  /* netif not under DHCP control by default */
+  netif->dhcp = NULL;
+#endif
+  /* remember netif specific state information data */
+  netif->state = state;
+  netif->num = netifnum++;
+  netif->input = input;
+
+  netif_set_addr(netif, ipaddr, netmask, gw);
+
+  /* call user specified initialization function for netif */
+  if (init(netif) != ERR_OK) {
+    return NULL;
+  }
+
+  /* add this netif to the list */
+  netif->next = netif_list;
+  netif_list = netif;
+  snmp_inc_iflist();
+
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP addr ",
+    netif->name[0], netif->name[1]));
+  ip_addr_debug_print(NETIF_DEBUG, ipaddr);
+  LWIP_DEBUGF(NETIF_DEBUG, (" netmask "));
+  ip_addr_debug_print(NETIF_DEBUG, netmask);
+  LWIP_DEBUGF(NETIF_DEBUG, (" gw "));
+  ip_addr_debug_print(NETIF_DEBUG, gw);
+  LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
+  return netif;
+}
+
+void
+netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask,
+    struct ip_addr *gw)
+{
+  netif_set_ipaddr(netif, ipaddr);
+  netif_set_netmask(netif, netmask);
+  netif_set_gw(netif, gw);
+}
+
+void netif_remove(struct netif * netif)
+{
+  if ( netif == NULL ) return;
+
+  snmp_delete_ipaddridx_tree(netif);
+
+  /*  is it the first netif? */
+  if (netif_list == netif) {
+    netif_list = netif->next;
+    snmp_dec_iflist();
+  }
+  else {
+    /*  look for netif further down the list */
+    struct netif * tmpNetif;
+    for (tmpNetif = netif_list; tmpNetif != NULL; tmpNetif = tmpNetif->next) {
+      if (tmpNetif->next == netif) {
+        tmpNetif->next = netif->next;
+        snmp_dec_iflist();
+        break;
+      }
+    }
+    if (tmpNetif == NULL)
+      return; /*  we didn't find any netif today */
+  }
+  /* this netif is default? */
+  if (netif_default == netif)
+    /* reset default netif */
+    netif_default = NULL;
+  LWIP_DEBUGF( NETIF_DEBUG, ("netif_remove: removed netif\n") );
+}
+
+struct netif *
+netif_find(char *name)
+{
+  struct netif *netif;
+  u8_t num;
+
+  if (name == NULL) {
+    return NULL;
+  }
+
+  num = name[2] - '0';
+
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+    if (num == netif->num &&
+       name[0] == netif->name[0] &&
+       name[1] == netif->name[1]) {
+      LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: found %c%c\n", name[0], name[1]));
+      return netif;
+    }
+  }
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: didn't find %c%c\n", name[0], name[1]));
+  return NULL;
+}
+
+void
+netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr)
+{
+  /* TODO: Handling of obsolete pcbs */
+  /* See:  http://mail.gnu.org/archive/html/lwip-users/2003-03/msg00118.html */
+#if LWIP_TCP
+  struct tcp_pcb *pcb;
+  struct tcp_pcb_listen *lpcb;
+
+  /* address is actually being changed? */
+  if ((ip_addr_cmp(ipaddr, &(netif->ip_addr))) == 0)
+  {
+    /* extern struct tcp_pcb *tcp_active_pcbs; defined by tcp.h */
+    LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: netif address being changed\n"));
+    pcb = tcp_active_pcbs;
+    while (pcb != NULL) {
+      /* PCB bound to current local interface address? */
+      if (ip_addr_cmp(&(pcb->local_ip), &(netif->ip_addr))) {
+        /* this connection must be aborted */
+        struct tcp_pcb *next = pcb->next;
+        LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb));
+        tcp_abort(pcb);
+        pcb = next;
+      } else {
+        pcb = pcb->next;
+      }
+    }
+    for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+      /* PCB bound to current local interface address? */
+      if (ip_addr_cmp(&(lpcb->local_ip), &(netif->ip_addr))) {
+        /* The PCB is listening to the old ipaddr and
+         * is set to listen to the new one instead */
+        ip_addr_set(&(lpcb->local_ip), ipaddr);
+      }
+    }
+  }
+#endif
+  snmp_delete_ipaddridx_tree(netif);
+  snmp_delete_iprteidx_tree(0,netif);
+  /* set new IP address to netif */
+  ip_addr_set(&(netif->ip_addr), ipaddr);
+  snmp_insert_ipaddridx_tree(netif);
+  snmp_insert_iprteidx_tree(0,netif);
+
+#if 0 /* only allowed for Ethernet interfaces TODO: how can we check? */
+  /** For Ethernet network interfaces, we would like to send a
+   *  "gratuitous ARP"; this is an ARP packet sent by a node in order
+   *  to spontaneously cause other nodes to update an entry in their
+   *  ARP cache. From RFC 3220 "IP Mobility Support for IPv4" section 4.6.
+   */ 
+  etharp_query(netif, ipaddr, NULL);
+#endif
+  LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: IP address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+    netif->name[0], netif->name[1],
+    ip4_addr1(&netif->ip_addr),
+    ip4_addr2(&netif->ip_addr),
+    ip4_addr3(&netif->ip_addr),
+    ip4_addr4(&netif->ip_addr)));
+}
+
+void
+netif_set_gw(struct netif *netif, struct ip_addr *gw)
+{
+  ip_addr_set(&(netif->gw), gw);
+  LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: GW address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+    netif->name[0], netif->name[1],
+    ip4_addr1(&netif->gw),
+    ip4_addr2(&netif->gw),
+    ip4_addr3(&netif->gw),
+    ip4_addr4(&netif->gw)));
+}
+
+void
+netif_set_netmask(struct netif *netif, struct ip_addr *netmask)
+{
+  snmp_delete_iprteidx_tree(0, netif);
+  /* set new netmask to netif */
+  ip_addr_set(&(netif->netmask), netmask);
+  snmp_insert_iprteidx_tree(0, netif);
+  LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: netmask of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+    netif->name[0], netif->name[1],
+    ip4_addr1(&netif->netmask),
+    ip4_addr2(&netif->netmask),
+    ip4_addr3(&netif->netmask),
+    ip4_addr4(&netif->netmask)));
+}
+
+void
+netif_set_default(struct netif *netif)
+{
+  if (netif == NULL)
+  {
+    /* remove default route */
+    snmp_delete_iprteidx_tree(1, netif);
+  }
+  else
+  {
+    /* install default route */
+    snmp_insert_iprteidx_tree(1, netif);
+  }
+  netif_default = netif;
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n",
+           netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\''));
+}
+
+/**
+ * Bring an interface up, available for processing
+ * traffic.
+ * 
+ * @note: Enabling DHCP on a down interface will make it come
+ * up once configured.
+ * 
+ * @see dhcp_start()
+ */ 
+void netif_set_up(struct netif *netif)
+{
+  netif->flags |= NETIF_FLAG_UP;
+#if LWIP_SNMP
+  snmp_get_sysuptime(&netif->ts);
+#endif
+}
+
+/**
+ * Ask if an interface is up
+ */ 
+u8_t netif_is_up(struct netif *netif)
+{
+  return (netif->flags & NETIF_FLAG_UP)?1:0;
+}
+
+/**
+ * Bring an interface down, disabling any traffic processing.
+ *
+ * @note: Enabling DHCP on a down interface will make it come
+ * up once configured.
+ * 
+ * @see dhcp_start()
+ */ 
+void netif_set_down(struct netif *netif)
+{
+  netif->flags &= ~NETIF_FLAG_UP;
+#if LWIP_SNMP
+  snmp_get_sysuptime(&netif->ts);
+#endif
+}
+
+void
+netif_init(void)
+{
+  netif_list = netif_default = NULL;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/pbuf.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/pbuf.c
new file mode 100644
index 0000000..1f6516d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/pbuf.c
@@ -0,0 +1,964 @@
+/**
+ * @file
+ * Packet buffer management
+ *
+ * Packets are built from the pbuf data structure. It supports dynamic
+ * memory allocation for packet contents or can reference externally
+ * managed packet contents both in RAM and ROM. Quick allocation for
+ * incoming packets is provided through pools with fixed sized pbufs.
+ *
+ * A packet may span over multiple pbufs, chained as a singly linked
+ * list. This is called a "pbuf chain".
+ *
+ * Multiple packets may be queued, also using this singly linked list.
+ * This is called a "packet queue".
+ * 
+ * So, a packet queue consists of one or more pbuf chains, each of
+ * which consist of one or more pbufs. Currently, queues are only
+ * supported in a limited section of lwIP, this is the etharp queueing
+ * code. Outside of this section no packet queues are supported yet.
+ * 
+ * The differences between a pbuf chain and a packet queue are very
+ * precise but subtle. 
+ *
+ * The last pbuf of a packet has a ->tot_len field that equals the
+ * ->len field. It can be found by traversing the list. If the last
+ * pbuf of a packet has a ->next field other than NULL, more packets
+ * are on the queue.
+ *
+ * Therefore, looping through a pbuf of a single packet, has an
+ * loop end condition (tot_len == p->len), NOT (next == NULL).
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include 
+
+#include "lwip/opt.h"
+#include "lwip/stats.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include "arch/perf.h"
+
+static u8_t pbuf_pool_memory[MEM_ALIGNMENT - 1 + PBUF_POOL_SIZE * MEM_ALIGN_SIZE(PBUF_POOL_BUFSIZE + sizeof(struct pbuf))];
+
+#if !SYS_LIGHTWEIGHT_PROT
+static volatile u8_t pbuf_pool_free_lock, pbuf_pool_alloc_lock;
+static sys_sem_t pbuf_pool_free_sem;
+#endif
+
+static struct pbuf *pbuf_pool = NULL;
+
+/**
+ * Initializes the pbuf module.
+ *
+ * A large part of memory is allocated for holding the pool of pbufs.
+ * The size of the individual pbufs in the pool is given by the size
+ * parameter, and the number of pbufs in the pool by the num parameter.
+ *
+ * After the memory has been allocated, the pbufs are set up. The
+ * ->next pointer in each pbuf is set up to point to the next pbuf in
+ * the pool.
+ *
+ */
+void
+pbuf_init(void)
+{
+  struct pbuf *p, *q = NULL;
+  u16_t i;
+
+  pbuf_pool = (struct pbuf *)MEM_ALIGN(pbuf_pool_memory);
+
+#if PBUF_STATS
+  lwip_stats.pbuf.avail = PBUF_POOL_SIZE;
+#endif /* PBUF_STATS */
+
+  /* Set up ->next pointers to link the pbufs of the pool together */
+  p = pbuf_pool;
+
+  for(i = 0; i < PBUF_POOL_SIZE; ++i) {
+    p->next = (struct pbuf *)((u8_t *)p + PBUF_POOL_BUFSIZE + sizeof(struct pbuf));
+    p->len = p->tot_len = PBUF_POOL_BUFSIZE;
+    p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf)));
+    p->flags = PBUF_FLAG_POOL;
+    q = p;
+    p = p->next;
+  }
+
+  /* The ->next pointer of last pbuf is NULL to indicate that there
+     are no more pbufs in the pool */
+  q->next = NULL;
+
+#if !SYS_LIGHTWEIGHT_PROT
+  pbuf_pool_alloc_lock = 0;
+  pbuf_pool_free_lock = 0;
+  pbuf_pool_free_sem = sys_sem_new(1);
+#endif
+}
+
+/**
+ * @internal only called from pbuf_alloc()
+ */
+static struct pbuf *
+pbuf_pool_alloc(void)
+{
+  struct pbuf *p = NULL;
+
+  SYS_ARCH_DECL_PROTECT(old_level);
+  SYS_ARCH_PROTECT(old_level);
+
+#if !SYS_LIGHTWEIGHT_PROT
+  /* Next, check the actual pbuf pool, but if the pool is locked, we
+     pretend to be out of buffers and return NULL. */
+  if (pbuf_pool_free_lock) {
+#if PBUF_STATS
+    ++lwip_stats.pbuf.alloc_locked;
+#endif /* PBUF_STATS */
+    return NULL;
+  }
+  pbuf_pool_alloc_lock = 1;
+  if (!pbuf_pool_free_lock) {
+#endif /* SYS_LIGHTWEIGHT_PROT */
+    p = pbuf_pool;
+    if (p) {
+      pbuf_pool = p->next;
+    }
+#if !SYS_LIGHTWEIGHT_PROT
+#if PBUF_STATS
+  } else {
+    ++lwip_stats.pbuf.alloc_locked;
+#endif /* PBUF_STATS */
+  }
+  pbuf_pool_alloc_lock = 0;
+#endif /* SYS_LIGHTWEIGHT_PROT */
+
+#if PBUF_STATS
+  if (p != NULL) {
+    ++lwip_stats.pbuf.used;
+    if (lwip_stats.pbuf.used > lwip_stats.pbuf.max) {
+      lwip_stats.pbuf.max = lwip_stats.pbuf.used;
+    }
+  }
+#endif /* PBUF_STATS */
+
+  SYS_ARCH_UNPROTECT(old_level);
+  return p;
+}
+
+
+/**
+ * Allocates a pbuf of the given type (possibly a chain for PBUF_POOL type).
+ *
+ * The actual memory allocated for the pbuf is determined by the
+ * layer at which the pbuf is allocated and the requested size
+ * (from the size parameter).
+ *
+ * @param flag this parameter decides how and where the pbuf
+ * should be allocated as follows:
+ *
+ * - PBUF_RAM: buffer memory for pbuf is allocated as one large
+ *             chunk. This includes protocol headers as well.
+ * - PBUF_ROM: no buffer memory is allocated for the pbuf, even for
+ *             protocol headers. Additional headers must be prepended
+ *             by allocating another pbuf and chain in to the front of
+ *             the ROM pbuf. It is assumed that the memory used is really
+ *             similar to ROM in that it is immutable and will not be
+ *             changed. Memory which is dynamic should generally not
+ *             be attached to PBUF_ROM pbufs. Use PBUF_REF instead.
+ * - PBUF_REF: no buffer memory is allocated for the pbuf, even for
+ *             protocol headers. It is assumed that the pbuf is only
+ *             being used in a single thread. If the pbuf gets queued,
+ *             then pbuf_take should be called to copy the buffer.
+ * - PBUF_POOL: the pbuf is allocated as a pbuf chain, with pbufs from
+ *              the pbuf pool that is allocated during pbuf_init().
+ *
+ * @return the allocated pbuf. If multiple pbufs where allocated, this
+ * is the first pbuf of a pbuf chain.
+ */
+struct pbuf *
+pbuf_alloc(pbuf_layer l, u16_t length, pbuf_flag flag)
+{
+  struct pbuf *p, *q, *r;
+  u16_t offset;
+  s32_t rem_len; /* remaining length */
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%"U16_F")\n", length));
+
+  /* determine header offset */
+  offset = 0;
+  switch (l) {
+  case PBUF_TRANSPORT:
+    /* add room for transport (often TCP) layer header */
+    offset += PBUF_TRANSPORT_HLEN;
+    /* FALLTHROUGH */
+  case PBUF_IP:
+    /* add room for IP layer header */
+    offset += PBUF_IP_HLEN;
+    /* FALLTHROUGH */
+  case PBUF_LINK:
+    /* add room for link layer header */
+    offset += PBUF_LINK_HLEN;
+    break;
+  case PBUF_RAW:
+    break;
+  default:
+    LWIP_ASSERT("pbuf_alloc: bad pbuf layer", 0);
+    return NULL;
+  }
+
+  switch (flag) {
+  case PBUF_POOL:
+    /* allocate head of pbuf chain into p */
+    p = pbuf_pool_alloc();
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc: allocated pbuf %p\n", (void *)p));
+    if (p == NULL) {
+#if PBUF_STATS
+      ++lwip_stats.pbuf.err;
+#endif /* PBUF_STATS */
+      return NULL;
+    }
+    p->next = NULL;
+
+    /* make the payload pointer point 'offset' bytes into pbuf data memory */
+    p->payload = MEM_ALIGN((void *)((u8_t *)p + (sizeof(struct pbuf) + offset)));
+    LWIP_ASSERT("pbuf_alloc: pbuf p->payload properly aligned",
+            ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
+    /* the total length of the pbuf chain is the requested size */
+    p->tot_len = length;
+    /* set the length of the first pbuf in the chain */
+    p->len = length > PBUF_POOL_BUFSIZE - offset? PBUF_POOL_BUFSIZE - offset: length;
+    /* set reference count (needed here in case we fail) */
+    p->ref = 1;
+
+    /* now allocate the tail of the pbuf chain */
+
+    /* remember first pbuf for linkage in next iteration */
+    r = p;
+    /* remaining length to be allocated */
+    rem_len = length - p->len;
+    /* any remaining pbufs to be allocated? */
+    while (rem_len > 0) {
+      q = pbuf_pool_alloc();
+      if (q == NULL) {
+       LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_alloc: Out of pbufs in pool.\n"));
+#if PBUF_STATS
+        ++lwip_stats.pbuf.err;
+#endif /* PBUF_STATS */
+        /* free chain so far allocated */
+        pbuf_free(p);
+        /* bail out unsuccesfully */
+        return NULL;
+      }
+      q->next = NULL;
+      /* make previous pbuf point to this pbuf */
+      r->next = q;
+      /* set total length of this pbuf and next in chain */
+      q->tot_len = rem_len;
+      /* this pbuf length is pool size, unless smaller sized tail */
+      q->len = rem_len > PBUF_POOL_BUFSIZE? PBUF_POOL_BUFSIZE: rem_len;
+      q->payload = (void *)((u8_t *)q + sizeof(struct pbuf));
+      LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned",
+              ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0);
+      q->ref = 1;
+      /* calculate remaining length to be allocated */
+      rem_len -= q->len;
+      /* remember this pbuf for linkage in next iteration */
+      r = q;
+    }
+    /* end of chain */
+    /*r->next = NULL;*/
+
+    break;
+  case PBUF_RAM:
+    /* If pbuf is to be allocated in RAM, allocate memory for it. */
+    p = mem_malloc(MEM_ALIGN_SIZE(sizeof(struct pbuf) + offset) + MEM_ALIGN_SIZE(length));
+    if (p == NULL) {
+      return NULL;
+    }
+    /* Set up internal structure of the pbuf. */
+    p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf) + offset));
+    p->len = p->tot_len = length;
+    p->next = NULL;
+    p->flags = PBUF_FLAG_RAM;
+
+    LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned",
+           ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
+    break;
+  /* pbuf references existing (non-volatile static constant) ROM payload? */
+  case PBUF_ROM:
+  /* pbuf references existing (externally allocated) RAM payload? */
+  case PBUF_REF:
+    /* only allocate memory for the pbuf structure */
+    p = memp_malloc(MEMP_PBUF);
+    if (p == NULL) {
+      LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_alloc: Could not allocate MEMP_PBUF for PBUF_%s.\n", flag == PBUF_ROM?"ROM":"REF"));
+
+      return NULL;
+    }
+    /* caller must set this field properly, afterwards */
+    p->payload = NULL;
+    p->len = p->tot_len = length;
+    p->next = NULL;
+    p->flags = (flag == PBUF_ROM? PBUF_FLAG_ROM: PBUF_FLAG_REF);
+    break;
+  default:
+    LWIP_ASSERT("pbuf_alloc: erroneous flag", 0);
+    return NULL;
+  }
+  /* set reference count */
+  p->ref = 1;
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p));
+  return p;
+}
+
+
+#if PBUF_STATS
+#define DEC_PBUF_STATS do { --lwip_stats.pbuf.used; } while (0)
+#else /* PBUF_STATS */
+#define DEC_PBUF_STATS
+#endif /* PBUF_STATS */
+
+#define PBUF_POOL_FAST_FREE(p)  do {                                    \
+                                  p->next = pbuf_pool;                  \
+                                  pbuf_pool = p;                        \
+                                  DEC_PBUF_STATS;                       \
+                                } while (0)
+
+#if SYS_LIGHTWEIGHT_PROT
+#define PBUF_POOL_FREE(p)  do {                                         \
+                                SYS_ARCH_DECL_PROTECT(old_level);       \
+                                SYS_ARCH_PROTECT(old_level);            \
+                                PBUF_POOL_FAST_FREE(p);                 \
+                                SYS_ARCH_UNPROTECT(old_level);          \
+                               } while (0)
+#else /* SYS_LIGHTWEIGHT_PROT */
+#define PBUF_POOL_FREE(p)  do {                                         \
+                             sys_sem_wait(pbuf_pool_free_sem);          \
+                             PBUF_POOL_FAST_FREE(p);                    \
+                             sys_sem_signal(pbuf_pool_free_sem);        \
+                           } while (0)
+#endif /* SYS_LIGHTWEIGHT_PROT */
+
+/**
+ * Shrink a pbuf chain to a desired length.
+ *
+ * @param p pbuf to shrink.
+ * @param new_len desired new length of pbuf chain
+ *
+ * Depending on the desired length, the first few pbufs in a chain might
+ * be skipped and left unchanged. The new last pbuf in the chain will be
+ * resized, and any remaining pbufs will be freed.
+ *
+ * @note If the pbuf is ROM/REF, only the ->tot_len and ->len fields are adjusted.
+ * @note May not be called on a packet queue.
+ *
+ * @bug Cannot grow the size of a pbuf (chain) (yet).
+ */
+void
+pbuf_realloc(struct pbuf *p, u16_t new_len)
+{
+  struct pbuf *q;
+  u16_t rem_len; /* remaining length */
+  s16_t grow;
+
+  LWIP_ASSERT("pbuf_realloc: sane p->flags", p->flags == PBUF_FLAG_POOL ||
+              p->flags == PBUF_FLAG_ROM ||
+              p->flags == PBUF_FLAG_RAM ||
+              p->flags == PBUF_FLAG_REF);
+
+  /* desired length larger than current length? */
+  if (new_len >= p->tot_len) {
+    /* enlarging not yet supported */
+    return;
+  }
+
+  /* the pbuf chain grows by (new_len - p->tot_len) bytes
+   * (which may be negative in case of shrinking) */
+  grow = new_len - p->tot_len;
+
+  /* first, step over any pbufs that should remain in the chain */
+  rem_len = new_len;
+  q = p;
+  /* should this pbuf be kept? */
+  while (rem_len > q->len) {
+    /* decrease remaining length by pbuf length */
+    rem_len -= q->len;
+    /* decrease total length indicator */
+    q->tot_len += grow;
+    /* proceed to next pbuf in chain */
+    q = q->next;
+  }
+  /* we have now reached the new last pbuf (in q) */
+  /* rem_len == desired length for pbuf q */
+
+  /* shrink allocated memory for PBUF_RAM */
+  /* (other types merely adjust their length fields */
+  if ((q->flags == PBUF_FLAG_RAM) && (rem_len != q->len)) {
+    /* reallocate and adjust the length of the pbuf that will be split */
+    mem_realloc(q, (u8_t *)q->payload - (u8_t *)q + rem_len);
+  }
+  /* adjust length fields for new last pbuf */
+  q->len = rem_len;
+  q->tot_len = q->len;
+
+  /* any remaining pbufs in chain? */
+  if (q->next != NULL) {
+    /* free remaining pbufs in chain */
+    pbuf_free(q->next);
+  }
+  /* q is last packet in chain */
+  q->next = NULL;
+
+}
+
+/**
+ * Adjusts the payload pointer to hide or reveal headers in the payload.
+ *
+ * Adjusts the ->payload pointer so that space for a header
+ * (dis)appears in the pbuf payload.
+ *
+ * The ->payload, ->tot_len and ->len fields are adjusted.
+ *
+ * @param hdr_size_inc Number of bytes to increment header size which
+ * increases the size of the pbuf. New space is on the front.
+ * (Using a negative value decreases the header size.)
+ * If hdr_size_inc is 0, this function does nothing and returns succesful.
+ *
+ * PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so
+ * the call will fail. A check is made that the increase in header size does
+ * not move the payload pointer in front of the start of the buffer.
+ * @return non-zero on failure, zero on success.
+ *
+ */
+u8_t
+pbuf_header(struct pbuf *p, s16_t header_size_increment)
+{
+  u16_t flags;
+  void *payload;
+
+  LWIP_ASSERT("p != NULL", p != NULL);
+  if ((header_size_increment == 0) || (p == NULL)) return 0;
+ 
+  flags = p->flags;
+  /* remember current payload pointer */
+  payload = p->payload;
+
+  /* pbuf types containing payloads? */
+  if (flags == PBUF_FLAG_RAM || flags == PBUF_FLAG_POOL) {
+    /* set new payload pointer */
+    p->payload = (u8_t *)p->payload - header_size_increment;
+    /* boundary check fails? */
+    if ((u8_t *)p->payload < (u8_t *)p + sizeof(struct pbuf)) {
+      LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_header: failed as %p < %p (not enough space for new header size)\n",
+        (void *)p->payload,
+        (void *)(p + 1)));\
+      /* restore old payload pointer */
+      p->payload = payload;
+      /* bail out unsuccesfully */
+      return 1;
+    }
+  /* pbuf types refering to external payloads? */
+  } else if (flags == PBUF_FLAG_REF || flags == PBUF_FLAG_ROM) {
+    /* hide a header in the payload? */
+    if ((header_size_increment < 0) && (header_size_increment - p->len <= 0)) {
+      /* increase payload pointer */
+      p->payload = (u8_t *)p->payload - header_size_increment;
+    } else {
+      /* cannot expand payload to front (yet!)
+       * bail out unsuccesfully */
+      return 1;
+    }
+  }
+  /* modify pbuf length fields */
+  p->len += header_size_increment;
+  p->tot_len += header_size_increment;
+
+  LWIP_DEBUGF( PBUF_DEBUG, ("pbuf_header: old %p new %p (%"S16_F")\n",
+    (void *)payload, (void *)p->payload, header_size_increment));
+
+  return 0;
+}
+
+/**
+ * Dereference a pbuf chain or queue and deallocate any no-longer-used
+ * pbufs at the head of this chain or queue.
+ *
+ * Decrements the pbuf reference count. If it reaches zero, the pbuf is
+ * deallocated.
+ *
+ * For a pbuf chain, this is repeated for each pbuf in the chain,
+ * up to the first pbuf which has a non-zero reference count after
+ * decrementing. So, when all reference counts are one, the whole
+ * chain is free'd.
+ *
+ * @param pbuf The pbuf (chain) to be dereferenced.
+ *
+ * @return the number of pbufs that were de-allocated
+ * from the head of the chain.
+ *
+ * @note MUST NOT be called on a packet queue (Not verified to work yet).
+ * @note the reference counter of a pbuf equals the number of pointers
+ * that refer to the pbuf (or into the pbuf).
+ *
+ * @internal examples:
+ *
+ * Assuming existing chains a->b->c with the following reference
+ * counts, calling pbuf_free(a) results in:
+ * 
+ * 1->2->3 becomes ...1->3
+ * 3->3->3 becomes 2->3->3
+ * 1->1->2 becomes ......1
+ * 2->1->1 becomes 1->1->1
+ * 1->1->1 becomes .......
+ *
+ */
+u8_t
+pbuf_free(struct pbuf *p)
+{
+  u16_t flags;
+  struct pbuf *q;
+  u8_t count;
+  SYS_ARCH_DECL_PROTECT(old_level);
+
+  LWIP_ASSERT("p != NULL", p != NULL);
+
+  /* if assertions are disabled, proceed with debug output */
+  if (p == NULL) {
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_free(p == NULL) was called.\n"));
+    return 0;
+  }
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_free(%p)\n", (void *)p));
+
+  PERF_START;
+
+  LWIP_ASSERT("pbuf_free: sane flags",
+    p->flags == PBUF_FLAG_RAM || p->flags == PBUF_FLAG_ROM ||
+    p->flags == PBUF_FLAG_REF || p->flags == PBUF_FLAG_POOL);
+
+  count = 0;
+  /* Since decrementing ref cannot be guaranteed to be a single machine operation
+   * we must protect it. Also, the later test of ref must be protected.
+   */
+  SYS_ARCH_PROTECT(old_level);
+  /* de-allocate all consecutive pbufs from the head of the chain that
+   * obtain a zero reference count after decrementing*/
+  while (p != NULL) {
+    /* all pbufs in a chain are referenced at least once */
+    LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0);
+    /* decrease reference count (number of pointers to pbuf) */
+    p->ref--;
+    /* this pbuf is no longer referenced to? */
+    if (p->ref == 0) {
+      /* remember next pbuf in chain for next iteration */
+      q = p->next;
+      LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: deallocating %p\n", (void *)p));
+      flags = p->flags;
+      /* is this a pbuf from the pool? */
+      if (flags == PBUF_FLAG_POOL) {
+        p->len = p->tot_len = PBUF_POOL_BUFSIZE;
+        p->payload = (void *)((u8_t *)p + sizeof(struct pbuf));
+        PBUF_POOL_FREE(p);
+      /* is this a ROM or RAM referencing pbuf? */
+      } else if (flags == PBUF_FLAG_ROM || flags == PBUF_FLAG_REF) {
+        memp_free(MEMP_PBUF, p);
+      /* flags == PBUF_FLAG_RAM */
+      } else {
+        mem_free(p);
+      }
+      count++;
+      /* proceed to next pbuf */
+      p = q;
+    /* p->ref > 0, this pbuf is still referenced to */
+    /* (and so the remaining pbufs in chain as well) */
+    } else {
+      LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, (u16_t)p->ref));
+      /* stop walking through the chain */
+      p = NULL;
+    }
+  }
+  SYS_ARCH_UNPROTECT(old_level);
+  PERF_STOP("pbuf_free");
+  /* return number of de-allocated pbufs */
+
+  return count;
+}
+
+/**
+ * Count number of pbufs in a chain
+ *
+ * @param p first pbuf of chain
+ * @return the number of pbufs in a chain
+ */
+
+u8_t
+pbuf_clen(struct pbuf *p)
+{
+  u8_t len;
+
+  len = 0;
+  while (p != NULL) {
+    ++len;
+    p = p->next;
+  }
+  return len;
+}
+
+/**
+ * Increment the reference count of the pbuf.
+ *
+ * @param p pbuf to increase reference counter of
+ *
+ */
+void
+pbuf_ref(struct pbuf *p)
+{
+  SYS_ARCH_DECL_PROTECT(old_level);
+  /* pbuf given? */
+  if (p != NULL) {
+    SYS_ARCH_PROTECT(old_level);
+    ++(p->ref);
+    SYS_ARCH_UNPROTECT(old_level);
+  }
+}
+
+/**
+ * Concatenate two pbufs (each may be a pbuf chain) and take over
+ * the caller's reference of the tail pbuf.
+ * 
+ * @note The caller MAY NOT reference the tail pbuf afterwards.
+ * Use pbuf_chain() for that purpose.
+ * 
+ * @see pbuf_chain()
+ */
+
+void
+pbuf_cat(struct pbuf *h, struct pbuf *t)
+{
+  struct pbuf *p;
+
+  LWIP_ASSERT("h != NULL (programmer violates API)", h != NULL);
+  LWIP_ASSERT("t != NULL (programmer violates API)", t != NULL);
+  if ((h == NULL) || (t == NULL)) return;
+
+  /* proceed to last pbuf of chain */
+  for (p = h; p->next != NULL; p = p->next) {
+    /* add total length of second chain to all totals of first chain */
+    p->tot_len += t->tot_len;
+  }
+  /* { p is last pbuf of first h chain, p->next == NULL } */
+  LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len);
+  LWIP_ASSERT("p->next == NULL", p->next == NULL);
+  /* add total length of second chain to last pbuf total of first chain */
+  p->tot_len += t->tot_len;
+  /* chain last pbuf of head (p) with first of tail (t) */
+  p->next = t;
+  /* p->next now references t, but the caller will drop its reference to t,
+   * so netto there is no change to the reference count of t.
+   */
+}
+
+/**
+ * Chain two pbufs (or pbuf chains) together.
+ * 
+ * The caller MUST call pbuf_free(t) once it has stopped
+ * using it. Use pbuf_cat() instead if you no longer use t.
+ * 
+ * @param h head pbuf (chain)
+ * @param t tail pbuf (chain)
+ * @note The pbufs MUST belong to the same packet.
+ * @note MAY NOT be called on a packet queue.
+ *
+ * The ->tot_len fields of all pbufs of the head chain are adjusted.
+ * The ->next field of the last pbuf of the head chain is adjusted.
+ * The ->ref field of the first pbuf of the tail chain is adjusted.
+ *
+ */
+void
+pbuf_chain(struct pbuf *h, struct pbuf *t)
+{
+  pbuf_cat(h, t);
+  /* t is now referenced by h */
+  pbuf_ref(t);
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t));
+}
+
+/* For packet queueing. Note that queued packets MUST be dequeued first
+ * using pbuf_dequeue() before calling other pbuf_() functions. */
+#if ARP_QUEUEING
+/**
+ * Add a packet to the end of a queue.
+ *
+ * @param q pointer to first packet on the queue
+ * @param n packet to be queued
+ *
+ * Both packets MUST be given, and must be different.
+ */
+void
+pbuf_queue(struct pbuf *p, struct pbuf *n)
+{
+#if PBUF_DEBUG /* remember head of queue */
+  struct pbuf *q = p;
+#endif
+  /* programmer stupidity checks */
+  LWIP_ASSERT("p == NULL in pbuf_queue: this indicates a programmer error\n", p != NULL);
+  LWIP_ASSERT("n == NULL in pbuf_queue: this indicates a programmer error\n", n != NULL);
+  LWIP_ASSERT("p == n in pbuf_queue: this indicates a programmer error\n", p != n);
+  if ((p == NULL) || (n == NULL) || (p == n)){
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_HALT | 3, ("pbuf_queue: programmer argument error\n"));
+    return;
+  }
+
+  /* iterate through all packets on queue */
+  while (p->next != NULL) {
+/* be very picky about pbuf chain correctness */
+#if PBUF_DEBUG
+    /* iterate through all pbufs in packet */
+    while (p->tot_len != p->len) {
+      /* make sure invariant condition holds */
+      LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len);
+      /* make sure each packet is complete */
+      LWIP_ASSERT("p->next != NULL", p->next != NULL);
+      p = p->next;
+      /* { p->tot_len == p->len => p is last pbuf of a packet } */
+    }
+    /* { p is last pbuf of a packet } */
+    /* proceed to next packet on queue */
+#endif
+    /* proceed to next pbuf */
+    if (p->next != NULL) p = p->next;
+  }
+  /* { p->tot_len == p->len and p->next == NULL } ==>
+   * { p is last pbuf of last packet on queue } */
+  /* chain last pbuf of queue with n */
+  p->next = n;
+  /* n is now referenced to by the (packet p in the) queue */
+  pbuf_ref(n);
+#if PBUF_DEBUG
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2,
+    ("pbuf_queue: newly queued packet %p sits after packet %p in queue %p\n",
+    (void *)n, (void *)p, (void *)q));
+#endif
+}
+
+/**
+ * Remove a packet from the head of a queue.
+ *
+ * The caller MUST reference the remainder of the queue (as returned). The
+ * caller MUST NOT call pbuf_ref() as it implicitly takes over the reference
+ * from p.
+ * 
+ * @param p pointer to first packet on the queue which will be dequeued.
+ * @return first packet on the remaining queue (NULL if no further packets).
+ *
+ */
+struct pbuf *
+pbuf_dequeue(struct pbuf *p)
+{
+  struct pbuf *q;
+  LWIP_ASSERT("p != NULL", p != NULL);
+
+  /* iterate through all pbufs in packet p */
+  while (p->tot_len != p->len) {
+    /* make sure invariant condition holds */
+    LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len);
+    /* make sure each packet is complete */
+    LWIP_ASSERT("p->next != NULL", p->next != NULL);
+    p = p->next;
+  }
+  /* { p->tot_len == p->len } => p is the last pbuf of the first packet */
+  /* remember next packet on queue in q */
+  q = p->next;
+  /* dequeue packet p from queue */
+  p->next = NULL;
+  /* any next packet on queue? */
+  if (q != NULL) {
+    /* although q is no longer referenced by p, it MUST be referenced by
+     * the caller, who is maintaining this packet queue. So, we do not call
+     * pbuf_free(q) here, resulting in an implicit pbuf_ref(q) for the caller. */
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: first remaining packet on queue is %p\n", (void *)q));
+  } else {
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: no further packets on queue\n"));
+  }
+  return q;
+}
+#endif
+
+/**
+ *
+ * Create PBUF_POOL (or PBUF_RAM) copies of PBUF_REF pbufs.
+ *
+ * Used to queue packets on behalf of the lwIP stack, such as
+ * ARP based queueing.
+ *
+ * Go through a pbuf chain and replace any PBUF_REF buffers
+ * with PBUF_POOL (or PBUF_RAM) pbufs, each taking a copy of
+ * the referenced data.
+ *
+ * @note You MUST explicitly use p = pbuf_take(p);
+ * The pbuf you give as argument, may have been replaced
+ * by a (differently located) copy through pbuf_take()!
+ *
+ * @note Any replaced pbufs will be freed through pbuf_free().
+ * This may deallocate them if they become no longer referenced.
+ *
+ * @param p Head of pbuf chain to process
+ *
+ * @return Pointer to head of pbuf chain
+ */
+struct pbuf *
+pbuf_take(struct pbuf *p)
+{
+  struct pbuf *q , *prev, *head;
+  LWIP_ASSERT("pbuf_take: p != NULL\n", p != NULL);
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_take(%p)\n", (void*)p));
+
+  prev = NULL;
+  head = p;
+  /* iterate through pbuf chain */
+  do
+  {
+    /* pbuf is of type PBUF_REF? */
+    if (p->flags == PBUF_FLAG_REF) {
+      LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE, ("pbuf_take: encountered PBUF_REF %p\n", (void *)p));
+      /* allocate a pbuf (w/ payload) fully in RAM */
+      /* PBUF_POOL buffers are faster if we can use them */
+      if (p->len <= PBUF_POOL_BUFSIZE) {
+        q = pbuf_alloc(PBUF_RAW, p->len, PBUF_POOL);
+        if (q == NULL) {
+          LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_POOL\n"));
+        }
+      } else {
+        /* no replacement pbuf yet */
+        q = NULL;
+        LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: PBUF_POOL too small to replace PBUF_REF\n"));
+      }
+      /* no (large enough) PBUF_POOL was available? retry with PBUF_RAM */
+      if (q == NULL) {
+        q = pbuf_alloc(PBUF_RAW, p->len, PBUF_RAM);
+        if (q == NULL) {
+          LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_RAM\n"));
+        }
+      }
+      /* replacement pbuf could be allocated? */
+      if (q != NULL)
+      {
+        /* copy p to q */
+        /* copy successor */
+        q->next = p->next;
+        /* remove linkage from original pbuf */
+        p->next = NULL;
+        /* remove linkage to original pbuf */
+        if (prev != NULL) {
+          /* prev->next == p at this point */
+          LWIP_ASSERT("prev->next == p", prev->next == p);
+          /* break chain and insert new pbuf instead */
+          prev->next = q;
+        /* prev == NULL, so we replaced the head pbuf of the chain */
+        } else {
+          head = q;
+        }
+        /* copy pbuf payload */
+        memcpy(q->payload, p->payload, p->len);
+        q->tot_len = p->tot_len;
+        q->len = p->len;
+        /* in case p was the first pbuf, it is no longer refered to by
+         * our caller, as the caller MUST do p = pbuf_take(p);
+         * in case p was not the first pbuf, it is no longer refered to
+         * by prev. we can safely free the pbuf here.
+         * (note that we have set p->next to NULL already so that
+         * we will not free the rest of the chain by accident.)
+         */
+        pbuf_free(p);
+        /* do not copy ref, since someone else might be using the old buffer */
+        LWIP_DEBUGF(PBUF_DEBUG, ("pbuf_take: replaced PBUF_REF %p with %p\n", (void *)p, (void *)q));
+        p = q;
+      } else {
+        /* deallocate chain */
+        pbuf_free(head);
+        LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_take: failed to allocate replacement pbuf for %p\n", (void *)p));
+        return NULL;
+      }
+    /* p->flags != PBUF_FLAG_REF */
+    } else {
+      LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: skipping pbuf not of type PBUF_REF\n"));
+    }
+    /* remember this pbuf */
+    prev = p;
+    /* proceed to next pbuf in original chain */
+    p = p->next;
+  } while (p);
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: end of chain reached.\n"));
+
+  return head;
+}
+
+/**
+ * Dechains the first pbuf from its succeeding pbufs in the chain.
+ *
+ * Makes p->tot_len field equal to p->len.
+ * @param p pbuf to dechain
+ * @return remainder of the pbuf chain, or NULL if it was de-allocated.
+ * @note May not be called on a packet queue.
+ */
+struct pbuf *
+pbuf_dechain(struct pbuf *p)
+{
+  struct pbuf *q;
+  u8_t tail_gone = 1;
+  /* tail */
+  q = p->next;
+  /* pbuf has successor in chain? */
+  if (q != NULL) {
+    /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */
+    LWIP_ASSERT("p->tot_len == p->len + q->tot_len", q->tot_len == p->tot_len - p->len);
+    /* enforce invariant if assertion is disabled */
+    q->tot_len = p->tot_len - p->len;
+    /* decouple pbuf from remainder */
+    p->next = NULL;
+    /* total length of pbuf p is its own length only */
+    p->tot_len = p->len;
+    /* q is no longer referenced by p, free it */
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE, ("pbuf_dechain: unreferencing %p\n", (void *)q));
+    tail_gone = pbuf_free(q);
+    if (tail_gone > 0) {
+      LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE,
+                  ("pbuf_dechain: deallocated %p (as it is no longer referenced)\n", (void *)q));
+    }
+    /* return remaining tail or NULL if deallocated */
+  }
+  /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */
+  LWIP_ASSERT("p->tot_len == p->len", p->tot_len == p->len);
+  return (tail_gone > 0? NULL: q);
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/raw.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/raw.c
new file mode 100644
index 0000000..b0e18b0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/raw.c
@@ -0,0 +1,326 @@
+/**
+ * @file
+ * 
+ * Implementation of raw protocol PCBs for low-level handling of
+ * different types of protocols besides (or overriding) those
+ * already available in lwIP.
+ *
+ */
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include 
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/memp.h"
+#include "lwip/inet.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/raw.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+#include "lwip/snmp.h"
+
+#if LWIP_RAW
+
+/** The list of RAW PCBs */
+static struct raw_pcb *raw_pcbs = NULL;
+
+void
+raw_init(void)
+{
+  raw_pcbs = NULL;
+}
+
+/**
+ * Determine if in incoming IP packet is covered by a RAW PCB
+ * and if so, pass it to a user-provided receive callback function.
+ *
+ * Given an incoming IP datagram (as a chain of pbufs) this function
+ * finds a corresponding RAW PCB and calls the corresponding receive
+ * callback function.
+ *
+ * @param pbuf pbuf to be demultiplexed to a RAW PCB.
+ * @param netif network interface on which the datagram was received.
+ * @Return - 1 if the packet has been eaten by a RAW PCB receive
+ *           callback function. The caller MAY NOT not reference the
+ *           packet any longer, and MAY NOT call pbuf_free().
+ * @return - 0 if packet is not eaten (pbuf is still referenced by the
+ *           caller).
+ *
+ */
+u8_t
+raw_input(struct pbuf *p, struct netif *inp)
+{
+  struct raw_pcb *pcb;
+  struct ip_hdr *iphdr;
+  s16_t proto;
+  u8_t eaten = 0;
+
+  iphdr = p->payload;
+  proto = IPH_PROTO(iphdr);
+
+  pcb = raw_pcbs;
+  /* loop through all raw pcbs until the packet is eaten by one */
+  /* this allows multiple pcbs to match against the packet by design */
+  while ((eaten == 0) && (pcb != NULL)) {
+    if (pcb->protocol == proto) {
+      /* receive callback function available? */
+      if (pcb->recv != NULL) {
+        /* the receive callback function did not eat the packet? */
+        if (pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src)) != 0)
+        {
+          /* receive function ate the packet */
+          p = NULL;
+          eaten = 1;
+        }
+      }
+      /* no receive callback function was set for this raw PCB */
+      /* drop the packet */
+    }
+    pcb = pcb->next;
+  }
+  return eaten;
+}
+
+/**
+ * Bind a RAW PCB.
+ *
+ * @param pcb RAW PCB to be bound with a local address ipaddr.
+ * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to
+ * bind to all local interfaces.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_USE. The specified IP address is already bound to by
+ * another RAW PCB.
+ *
+ * @see raw_disconnect()
+ */
+err_t
+raw_bind(struct raw_pcb *pcb, struct ip_addr *ipaddr)
+{
+  ip_addr_set(&pcb->local_ip, ipaddr);
+  return ERR_OK;
+}
+
+/**
+ * Connect an RAW PCB. This function is required by upper layers
+ * of lwip. Using the raw api you could use raw_sendto() instead
+ *
+ * This will associate the RAW PCB with the remote address.
+ *
+ * @param pcb RAW PCB to be connected with remote address ipaddr and port.
+ * @param ipaddr remote IP address to connect with.
+ *
+ * @return lwIP error code
+ *
+ * @see raw_disconnect() and raw_sendto()
+ */
+err_t
+raw_connect(struct raw_pcb *pcb, struct ip_addr *ipaddr)
+{
+  ip_addr_set(&pcb->remote_ip, ipaddr);
+  return ERR_OK;
+}
+
+
+/**
+ * Set the callback function for received packets that match the
+ * raw PCB's protocol and binding. 
+ * 
+ * The callback function MUST either
+ * - eat the packet by calling pbuf_free() and returning non-zero. The
+ *   packet will not be passed to other raw PCBs or other protocol layers.
+ * - not free the packet, and return zero. The packet will be matched
+ *   against further PCBs and/or forwarded to another protocol layers.
+ * 
+ * @return non-zero if the packet was free()d, zero if the packet remains
+ * available for others.
+ */
+void
+raw_recv(struct raw_pcb *pcb,
+         u8_t (* recv)(void *arg, struct raw_pcb *upcb, struct pbuf *p,
+                      struct ip_addr *addr),
+         void *recv_arg)
+{
+  /* remember recv() callback and user data */
+  pcb->recv = recv;
+  pcb->recv_arg = recv_arg;
+}
+
+/**
+ * Send the raw IP packet to the given address. Note that actually you cannot
+ * modify the IP headers (this is inconsistent with the receive callback where
+ * you actually get the IP headers), you can only specify the IP payload here.
+ * It requires some more changes in lwIP. (there will be a raw_send() function
+ * then.)
+ *
+ * @param pcb the raw pcb which to send
+ * @param p the IP payload to send
+ * @param ipaddr the destination address of the IP packet
+ *
+ */
+err_t
+raw_sendto(struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr)
+{
+  err_t err;
+  struct netif *netif;
+  struct ip_addr *src_ip;
+  struct pbuf *q; /* q will be sent down the stack */
+  
+  LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_sendto\n"));
+  
+  /* not enough space to add an IP header to first pbuf in given p chain? */
+  if (pbuf_header(p, IP_HLEN)) {
+    /* allocate header in new pbuf */
+    q = pbuf_alloc(PBUF_IP, 0, PBUF_RAM);
+    /* new header pbuf could not be allocated? */
+    if (q == NULL) {
+      LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 2, ("raw_sendto: could not allocate header\n"));
+      return ERR_MEM;
+    }
+    /* chain header q in front of given pbuf p */
+    pbuf_chain(q, p);
+    /* { first pbuf q points to header pbuf } */
+    LWIP_DEBUGF(RAW_DEBUG, ("raw_sendto: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
+  }  else {
+    /* first pbuf q equals given pbuf */
+    q = p;
+    pbuf_header(q, -IP_HLEN);
+  }
+  
+  if ((netif = ip_route(ipaddr)) == NULL) {
+    LWIP_DEBUGF(RAW_DEBUG | 1, ("raw_sendto: No route to 0x%"X32_F"\n", ipaddr->addr));
+#if RAW_STATS
+    /*    ++lwip_stats.raw.rterr;*/
+#endif /* RAW_STATS */
+    /* free any temporary header pbuf allocated by pbuf_header() */
+    if (q != p) {
+      pbuf_free(q);
+    }
+    return ERR_RTE;
+  }
+
+  if (ip_addr_isany(&pcb->local_ip)) {
+    /* use outgoing network interface IP address as source address */
+    src_ip = &(netif->ip_addr);
+  } else {
+    /* use RAW PCB local IP address as source address */
+    src_ip = &(pcb->local_ip);
+  }
+
+  err = ip_output_if (q, src_ip, ipaddr, pcb->ttl, pcb->tos, pcb->protocol, netif);
+
+  /* did we chain a header earlier? */
+  if (q != p) {
+    /* free the header */
+    pbuf_free(q);
+  }
+  return err;
+}
+
+/**
+ * Send the raw IP packet to the address given by raw_connect()
+ *
+ * @param pcb the raw pcb which to send
+ * @param p the IP payload to send
+ * @param ipaddr the destination address of the IP packet
+ *
+ */
+err_t
+raw_send(struct raw_pcb *pcb, struct pbuf *p)
+{
+  return raw_sendto(pcb, p, &pcb->remote_ip);
+}
+
+/**
+ * Remove an RAW PCB.
+ *
+ * @param pcb RAW PCB to be removed. The PCB is removed from the list of
+ * RAW PCB's and the data structure is freed from memory.
+ *
+ * @see raw_new()
+ */
+void
+raw_remove(struct raw_pcb *pcb)
+{
+  struct raw_pcb *pcb2;
+  /* pcb to be removed is first in list? */
+  if (raw_pcbs == pcb) {
+    /* make list start at 2nd pcb */
+    raw_pcbs = raw_pcbs->next;
+    /* pcb not 1st in list */
+  } else for(pcb2 = raw_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
+    /* find pcb in raw_pcbs list */
+    if (pcb2->next != NULL && pcb2->next == pcb) {
+      /* remove pcb from list */
+      pcb2->next = pcb->next;
+    }
+  }
+  memp_free(MEMP_RAW_PCB, pcb);
+}
+
+/**
+ * Create a RAW PCB.
+ *
+ * @return The RAW PCB which was created. NULL if the PCB data structure
+ * could not be allocated.
+ *
+ * @param proto the protocol number of the IPs payload (e.g. IP_PROTO_ICMP)
+ *
+ * @see raw_remove()
+ */
+struct raw_pcb *
+raw_new(u16_t proto) {
+  struct raw_pcb *pcb;
+
+  LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_new\n"));
+
+  pcb = memp_malloc(MEMP_RAW_PCB);
+  /* could allocate RAW PCB? */
+  if (pcb != NULL) {
+    /* initialize PCB to all zeroes */
+    memset(pcb, 0, sizeof(struct raw_pcb));
+    pcb->protocol = proto;
+    pcb->ttl = RAW_TTL;
+    pcb->next = raw_pcbs;
+    raw_pcbs = pcb;
+  }
+  return pcb;
+}
+
+#endif /* LWIP_RAW */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/snmp/asn1_dec.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/snmp/asn1_dec.c
new file mode 100644
index 0000000..a556edd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/snmp/asn1_dec.c
@@ -0,0 +1,652 @@
+/**
+ * @file
+ * Abstract Syntax Notation One (ISO 8824, 8825) decoding
+ *
+ * @todo not optimised (yet), favor correctness over speed, favor speed over size
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP
+#include "lwip/snmp_asn1.h"
+
+/**
+ * Retrieves type field from incoming pbuf chain.
+ *
+ * @param p points to a pbuf holding an ASN1 coded type field
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded type field
+ * @param type return ASN1 type
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ */
+err_t
+snmp_asn1_dec_type(struct pbuf *p, u16_t ofs, u8_t *type)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+      *type = *msg_ptr;
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Decodes length field from incoming pbuf chain into host length.
+ *
+ * @param p points to a pbuf holding an ASN1 coded length
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded length
+ * @param octets_used returns number of octets used by the length code
+ * @param length return host order length, upto 64k
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ */
+err_t
+snmp_asn1_dec_length(struct pbuf *p, u16_t ofs, u8_t *octets_used, u16_t *length)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+
+      if (*msg_ptr < 0x80)
+      {
+        /* primitive definite length format */
+        *octets_used = 1;
+        *length = *msg_ptr;
+        return ERR_OK;
+      }
+      else if (*msg_ptr == 0x80)
+      {
+        /* constructed indefinite length format, termination with two zero octets */
+        u8_t zeros;
+        u8_t i;
+
+        *length = 0;
+        zeros = 0;
+        while (zeros != 2)
+        {
+          i = 2;
+          while (i > 0)
+          {
+            i--;
+            (*length) += 1;
+            ofs += 1;
+            if (ofs >= plen)
+            {
+              /* next octet in next pbuf */
+              p = p->next;
+              if (p == NULL) { return ERR_ARG; }
+              msg_ptr = p->payload;
+              plen += p->len;
+            }
+            else
+            {
+              /* next octet in same pbuf */
+              msg_ptr++;
+            }
+            if (*msg_ptr == 0)
+            {
+              zeros++;
+              if (zeros == 2)
+              {
+                /* stop while (i > 0) */
+                i = 0;
+              }
+            }
+            else
+            {
+              zeros = 0;
+            }
+          }
+        }
+        *octets_used = 1;
+        return ERR_OK;
+      }
+      else if (*msg_ptr == 0x81)
+      {
+        /* constructed definite length format, one octet */
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+        *length = *msg_ptr;
+        *octets_used = 2;
+        return ERR_OK;
+      }
+      else if (*msg_ptr == 0x82)
+      {
+        u8_t i;
+
+        /* constructed definite length format, two octets */
+        i = 2;
+        while (i > 0)
+        {
+          i--;
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+          if (i == 0)
+          {
+            /* least significant length octet */
+            *length |= *msg_ptr;
+          }
+          else
+          {
+            /* most significant length octet */
+            *length = (*msg_ptr) << 8;
+          }
+        }
+        *octets_used = 3;
+        return ERR_OK;
+      }
+      else
+      {
+        /* constructed definite length format 3..127 octets, this is too big (>64k) */
+        /**  @todo: do we need to accept inefficient codings with many leading zero's? */
+        *octets_used = 1 + ((*msg_ptr) & 0x7f);
+        return ERR_ARG;
+      }
+    }
+    p = p->next;
+  }
+
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Decodes positive integer (counter, gauge, timeticks) into u32_t.
+ *
+ * @param p points to a pbuf holding an ASN1 coded integer
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded integer
+ * @param len length of the coded integer field
+ * @param value return host order integer
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ *
+ * @note ASN coded integers are _always_ signed. E.g. +0xFFFF is coded
+ * as 0x00,0xFF,0xFF. Note the leading sign octet. A positive value
+ * of 0xFFFFFFFF is preceded with 0x00 and the length is 5 octets!!
+ */
+err_t
+snmp_asn1_dec_u32t(struct pbuf *p, u16_t ofs, u16_t len, u32_t *value)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+      if ((len > 0) && (len < 6))
+      {
+        /* start from zero */
+        *value = 0;
+        if (*msg_ptr & 0x80)
+        {
+          /* negative, expecting zero sign bit! */
+          return ERR_ARG;
+        }
+        else
+        {
+          /* positive */
+          if ((len > 1) && (*msg_ptr == 0))
+          {
+            /* skip leading "sign byte" octet 0x00 */
+            len--;
+            ofs += 1;
+            if (ofs >= plen)
+            {
+              /* next octet in next pbuf */
+              p = p->next;
+              if (p == NULL) { return ERR_ARG; }
+              msg_ptr = p->payload;
+              plen += p->len;
+            }
+            else
+            {
+              /* next octet in same pbuf */
+              msg_ptr++;
+            }
+          }
+        }
+        /* OR octets with value */
+        while (len > 1)
+        {
+          len--;
+          *value |= *msg_ptr;
+          *value <<= 8;
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+        }
+        *value |= *msg_ptr;
+        return ERR_OK;
+      }
+      else
+      {
+        return ERR_ARG;
+      }
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Decodes integer into s32_t.
+ *
+ * @param p points to a pbuf holding an ASN1 coded integer
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded integer
+ * @param len length of the coded integer field
+ * @param value return host order integer
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ *
+ * @note ASN coded integers are _always_ signed!
+ */
+err_t
+snmp_asn1_dec_s32t(struct pbuf *p, u16_t ofs, u16_t len, s32_t *value)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+  u8_t *lsb_ptr = (u8_t*)value;
+  u8_t sign;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+      if ((len > 0) && (len < 5))
+      {
+        if (*msg_ptr & 0x80)
+        {
+          /* negative, start from -1 */
+          *value = -1;
+          sign = 1;
+        }
+        else
+        {
+          /* positive, start from 0 */
+          *value = 0;
+          sign = 0;
+        }
+        /* OR/AND octets with value */
+        while (len > 1)
+        {
+          len--;
+          if (sign)
+          {
+            *lsb_ptr &= *msg_ptr;
+            *value <<= 8;
+            *lsb_ptr |= 255;
+          }
+          else
+          {
+            *lsb_ptr |= *msg_ptr;
+            *value <<= 8;
+          }
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+        }
+        if (sign)
+        {
+          *lsb_ptr &= *msg_ptr;
+        }
+        else
+        {
+          *lsb_ptr |= *msg_ptr;
+        }
+        return ERR_OK;
+      }
+      else
+      {
+        return ERR_ARG;
+      }
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Decodes object identifier from incoming message into array of s32_t.
+ *
+ * @param p points to a pbuf holding an ASN1 coded object identifier
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded object identifier
+ * @param len length of the coded object identifier
+ * @param oid return object identifier struct
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ */
+err_t
+snmp_asn1_dec_oid(struct pbuf *p, u16_t ofs, u16_t len, struct snmp_obj_id *oid)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+  s32_t *oid_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+
+      oid->len = 0;
+      oid_ptr = &oid->id[0];
+      if (len > 0)
+      {
+        /* first compressed octet */
+        if (*msg_ptr == 0x2B)
+        {
+          /* (most) common case 1.3 (iso.org) */
+          *oid_ptr = 1;
+          oid_ptr++;
+          *oid_ptr = 3;
+          oid_ptr++;
+        }
+        else if (*msg_ptr < 40)
+        {
+          *oid_ptr = 0;
+          oid_ptr++;
+          *oid_ptr = *msg_ptr;
+          oid_ptr++;
+        }
+        else if (*msg_ptr < 80)
+        {
+          *oid_ptr = 1;
+          oid_ptr++;
+          *oid_ptr = (*msg_ptr) - 40;
+          oid_ptr++;
+        }
+        else
+        {
+          *oid_ptr = 2;
+          oid_ptr++;
+          *oid_ptr = (*msg_ptr) - 80;
+          oid_ptr++;
+        }
+        oid->len = 2;
+      }
+      else
+      {
+        /* accepting zero length identifiers e.g. for
+           getnext operation. uncommon but valid */
+        return ERR_OK;
+      }
+      len--;
+      if (len > 0)
+      {
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+      }
+      while ((len > 0) && (oid->len < LWIP_SNMP_OBJ_ID_LEN))
+      {
+        /* sub-identifier uses multiple octets */
+        if (*msg_ptr & 0x80)
+        {
+          s32_t sub_id = 0;
+
+          while ((*msg_ptr & 0x80) && (len > 1))
+          {
+            len--;
+            sub_id = (sub_id << 7) + (*msg_ptr & ~0x80);
+            ofs += 1;
+            if (ofs >= plen)
+            {
+              /* next octet in next pbuf */
+              p = p->next;
+              if (p == NULL) { return ERR_ARG; }
+              msg_ptr = p->payload;
+              plen += p->len;
+            }
+            else
+            {
+              /* next octet in same pbuf */
+              msg_ptr++;
+            }
+          }
+          if (!(*msg_ptr & 0x80) && (len > 0))
+          {
+            /* last octet sub-identifier */
+            len--;
+            sub_id = (sub_id << 7) + *msg_ptr;
+            *oid_ptr = sub_id;
+          }
+        }
+        else
+        {
+          /* !(*msg_ptr & 0x80) sub-identifier uses single octet */
+          len--;
+          *oid_ptr = *msg_ptr;
+        }
+        if (len > 0)
+        {
+          /* remaining oid bytes available ... */
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+        }
+        oid_ptr++;
+        oid->len++;
+      }
+      if (len == 0)
+      {
+        /* len == 0, end of oid */
+        return ERR_OK;
+      }
+      else
+      {
+        /* len > 0, oid->len == LWIP_SNMP_OBJ_ID_LEN or malformed encoding */
+        return ERR_ARG;
+      }
+
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Decodes (copies) raw data (ip-addresses, octet strings, opaque encoding)
+ * from incoming message into array.
+ *
+ * @param p points to a pbuf holding an ASN1 coded raw data
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded raw data
+ * @param len length of the coded raw data (zero is valid, e.g. empty string!)
+ * @param raw_len length of the raw return value
+ * @param raw return raw bytes
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ */
+err_t
+snmp_asn1_dec_raw(struct pbuf *p, u16_t ofs, u16_t len, u16_t raw_len, u8_t *raw)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  if (len > 0)
+  {
+    plen = 0;
+    while (p != NULL)
+    {
+      base = plen;
+      plen += p->len;
+      if (ofs < plen)
+      {
+        msg_ptr = p->payload;
+        msg_ptr += ofs - base;
+        if (raw_len >= len)
+        {
+          while (len > 1)
+          {
+            /* copy len - 1 octets */
+            len--;
+            *raw = *msg_ptr;
+            raw++;
+            ofs += 1;
+            if (ofs >= plen)
+            {
+              /* next octet in next pbuf */
+              p = p->next;
+              if (p == NULL) { return ERR_ARG; }
+              msg_ptr = p->payload;
+              plen += p->len;
+            }
+            else
+            {
+              /* next octet in same pbuf */
+              msg_ptr++;
+            }
+          }
+          /* copy last octet */
+          *raw = *msg_ptr;
+          return ERR_OK;
+        }
+        else
+        {
+          /* raw_len < len, not enough dst space */
+          return ERR_ARG;
+        }
+      }
+      p = p->next;
+    }
+    /* p == NULL, ofs >= plen */
+    return ERR_ARG;
+  }
+  else
+  {
+    /* len == 0, empty string */
+    return ERR_OK;
+  }
+}
+
+#endif /* LWIP_SNMP */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/snmp/asn1_enc.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/snmp/asn1_enc.c
new file mode 100644
index 0000000..80f8d37
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/snmp/asn1_enc.c
@@ -0,0 +1,610 @@
+/**
+ * @file
+ * Abstract Syntax Notation One (ISO 8824, 8825) encoding
+ *
+ * @todo not optimised (yet), favor correctness over speed, favor speed over size
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP
+#include "lwip/snmp_asn1.h"
+
+/**
+ * Returns octet count for length.
+ *
+ * @param length
+ * @param octets_needed points to the return value
+ */
+void
+snmp_asn1_enc_length_cnt(u16_t length, u8_t *octets_needed)
+{
+  if (length < 0x80U)
+  {
+    *octets_needed = 1;
+  }
+  else if (length < 0x100U)
+  {
+    *octets_needed = 2;
+  }
+  else
+  {
+    *octets_needed = 3;
+  }
+}
+
+/**
+ * Returns octet count for an u32_t.
+ *
+ * @param value
+ * @param octets_needed points to the return value
+ *
+ * @note ASN coded integers are _always_ signed. E.g. +0xFFFF is coded
+ * as 0x00,0xFF,0xFF. Note the leading sign octet. A positive value
+ * of 0xFFFFFFFF is preceded with 0x00 and the length is 5 octets!!
+ */
+void
+snmp_asn1_enc_u32t_cnt(u32_t value, u16_t *octets_needed)
+{
+  if (value < 0x80UL)
+  {
+    *octets_needed = 1;
+  }
+  else if (value < 0x8000UL)
+  {
+    *octets_needed = 2;
+  }
+  else if (value < 0x800000UL)
+  {
+    *octets_needed = 3;
+  }
+  else if (value < 0x80000000UL)
+  {
+    *octets_needed = 4;
+  }
+  else
+  {
+    *octets_needed = 5;
+  }
+}
+
+/**
+ * Returns octet count for an s32_t.
+ *
+ * @param value
+ * @param octets_needed points to the return value
+ *
+ * @note ASN coded integers are _always_ signed.
+ */
+void
+snmp_asn1_enc_s32t_cnt(s32_t value, u16_t *octets_needed)
+{
+  if (value < 0)
+  {
+    value = ~value;
+  }
+  if (value < 0x80L)
+  {
+    *octets_needed = 1;
+  }
+  else if (value < 0x8000L)
+  {
+    *octets_needed = 2;
+  }
+  else if (value < 0x800000L)
+  {
+    *octets_needed = 3;
+  }
+  else
+  {
+    *octets_needed = 4;
+  }
+}
+
+/**
+ * Returns octet count for an object identifier.
+ *
+ * @param ident_len object identifier array length
+ * @param ident points to object identifier array
+ * @param octets_needed points to the return value
+ */
+void
+snmp_asn1_enc_oid_cnt(u8_t ident_len, s32_t *ident, u16_t *octets_needed)
+{
+  s32_t sub_id;
+  u8_t cnt;
+
+  cnt = 0;
+  if (ident_len > 1)
+  {
+    /* compressed prefix in one octet */
+    cnt++;
+    ident_len -= 2;
+    ident += 2;
+  }
+  while(ident_len > 0)
+  {
+    ident_len--;
+    sub_id = *ident;
+
+    sub_id >>= 7;
+    cnt++;
+    while(sub_id > 0)
+    {
+      sub_id >>= 7;
+      cnt++;
+    }
+    ident++;
+  }
+  *octets_needed = cnt;
+}
+
+/**
+ * Encodes ASN type field into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode value into
+ * @param ofs points to the offset within the pbuf chain
+ * @param type input ASN1 type
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ */
+err_t
+snmp_asn1_enc_type(struct pbuf *p, u16_t ofs, u8_t type)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+      *msg_ptr = type;
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Encodes host order length field into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode length into
+ * @param ofs points to the offset within the pbuf chain
+ * @param length is the host order length to be encoded
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ */
+err_t
+snmp_asn1_enc_length(struct pbuf *p, u16_t ofs, u16_t length)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+
+      if (length < 0x80)
+      {
+        *msg_ptr = length;
+        return ERR_OK;
+      }
+      else if (length < 0x100)
+      {
+        *msg_ptr = 0x81;
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+        *msg_ptr = length;
+        return ERR_OK;
+      }
+      else
+      {
+        u8_t i;
+
+        /* length >= 0x100 && length <= 0xFFFF */
+        *msg_ptr = 0x82;
+        i = 2;
+        while (i > 0)
+        {
+          i--;
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+          if (i == 0)
+          {
+            /* least significant length octet */
+            *msg_ptr = length;
+          }
+          else
+          {
+            /* most significant length octet */
+            *msg_ptr = length >> 8;
+          }
+        }
+        return ERR_OK;
+      }
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Encodes u32_t (counter, gauge, timeticks) into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode value into
+ * @param ofs points to the offset within the pbuf chain
+ * @param octets_needed encoding length (from snmp_asn1_enc_u32t_cnt())
+ * @param value is the host order u32_t value to be encoded
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ *
+ * @see snmp_asn1_enc_u32t_cnt()
+ */
+err_t
+snmp_asn1_enc_u32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, u32_t value)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+
+      if (octets_needed == 5)
+      {
+        /* not enough bits in 'value' add leading 0x00 */
+        octets_needed--;
+        *msg_ptr = 0x00;
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+      }
+      while (octets_needed > 1)
+      {
+        octets_needed--;
+        *msg_ptr = value >> (octets_needed << 3);
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+      }
+      /* (only) one least significant octet */
+      *msg_ptr = value;
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Encodes s32_t integer into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode value into
+ * @param ofs points to the offset within the pbuf chain
+ * @param octets_needed encoding length (from snmp_asn1_enc_s32t_cnt())
+ * @param value is the host order s32_t value to be encoded
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ *
+ * @see snmp_asn1_enc_s32t_cnt()
+ */
+err_t
+snmp_asn1_enc_s32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, s32_t value)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+
+      while (octets_needed > 1)
+      {
+        octets_needed--;
+        *msg_ptr = value >> (octets_needed << 3);
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+      }
+      /* (only) one least significant octet */
+      *msg_ptr = value;
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Encodes object identifier into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode oid into
+ * @param ofs points to the offset within the pbuf chain
+ * @param ident_len object identifier array length
+ * @param ident points to object identifier array
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ */
+err_t
+snmp_asn1_enc_oid(struct pbuf *p, u16_t ofs, u8_t ident_len, s32_t *ident)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+
+      if (ident_len > 1)
+      {
+        if ((ident[0] == 1) && (ident[1] == 3))
+        {
+          /* compressed (most common) prefix .iso.org */
+          *msg_ptr = 0x2b;
+        }
+        else
+        {
+          /* calculate prefix */
+          *msg_ptr = (ident[0] * 40) + ident[1];
+        }
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+        ident_len -= 2;
+        ident += 2;
+      }
+      else
+      {
+/* @bug:  allow empty varbinds for symmetry (we must decode them for getnext), allow partial compression??  */
+        /* ident_len <= 1, at least we need zeroDotZero (0.0) (ident_len == 2) */
+        return ERR_ARG;
+      }
+      while (ident_len > 0)
+      {
+        s32_t sub_id;
+        u8_t shift, tail;
+
+        ident_len--;
+        sub_id = *ident;
+        tail = 0;
+        shift = 28;
+        while(shift > 0)
+        {
+          u8_t code;
+
+          code = sub_id >> shift;
+          if ((code != 0) || (tail != 0))
+          {
+            tail = 1;
+            *msg_ptr = code | 0x80;
+            ofs += 1;
+            if (ofs >= plen)
+            {
+              /* next octet in next pbuf */
+              p = p->next;
+              if (p == NULL) { return ERR_ARG; }
+              msg_ptr = p->payload;
+              plen += p->len;
+            }
+            else
+            {
+              /* next octet in same pbuf */
+              msg_ptr++;
+            }
+          }
+          shift -= 7;
+        }
+        *msg_ptr = (u8_t)sub_id & 0x7F;
+        if (ident_len > 0)
+        {
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+        }
+        /* proceed to next sub-identifier */
+        ident++;
+      }
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Encodes raw data (octet string, opaque) into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode raw data into
+ * @param ofs points to the offset within the pbuf chain
+ * @param raw_len raw data length
+ * @param raw points raw data
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ */
+err_t
+snmp_asn1_enc_raw(struct pbuf *p, u16_t ofs, u8_t raw_len, u8_t *raw)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+
+      while (raw_len > 1)
+      {
+        /* copy raw_len - 1 octets */
+        raw_len--;
+        *msg_ptr = *raw;
+        raw++;
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+      }
+      if (raw_len > 0)
+      {
+        /* copy last or single octet */
+        *msg_ptr = *raw;
+      }
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+#endif /* LWIP_SNMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/snmp/mib2.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/snmp/mib2.c
new file mode 100644
index 0000000..035c8b1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/snmp/mib2.c
@@ -0,0 +1,4021 @@
+/**
+ * @file
+ * Management Information Base II (RFC1213) objects and functions.
+ *
+ * @note the object identifiers for this MIB-2 and private MIB tree
+ * must be kept in sorted ascending order. This to ensure correct getnext operation.
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "arch/cc.h"
+#include "lwip/opt.h"
+
+#if LWIP_SNMP
+#include "lwip/snmp.h"
+#include "lwip/netif.h"
+#include "netif/etharp.h"
+#include "lwip/ip.h"
+#include "lwip/ip_frag.h"
+#include "lwip/tcp.h"
+#include "lwip/udp.h"
+#include "lwip/snmp_asn1.h"
+#include "lwip/snmp_structs.h"
+
+/**
+ * IANA assigned enterprise ID for lwIP is 26381
+ * @see http://www.iana.org/assignments/enterprise-numbers
+ *
+ * @note this enterprise ID is assigned to the lwIP project,
+ * all object identifiers living under this ID are assigned
+ * by the lwIP maintainers (contact Christiaan Simons)!
+ * @note don't change this define, use snmp_set_sysobjid()
+ *
+ * If you need to create your own private MIB you'll need
+ * to apply for your own enterprise ID with IANA:
+ * http://www.iana.org/numbers.html
+ */
+#define SNMP_ENTERPRISE_ID 26381
+#define SNMP_SYSOBJID_LEN 7
+#define SNMP_SYSOBJID {1, 3, 6, 1, 4, 1, SNMP_ENTERPRISE_ID}
+
+#ifndef SNMP_SYSSERVICES
+#define SNMP_SYSSERVICES ((1 << 6) | (1 << 3) | ((IP_FORWARD) << 2))
+#endif
+
+static void system_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void system_get_value(struct obj_def *od, u16_t len, void *value);
+static u8_t system_set_test(struct obj_def *od, u16_t len, void *value);
+static void system_set_value(struct obj_def *od, u16_t len, void *value);
+static void interfaces_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void interfaces_get_value(struct obj_def *od, u16_t len, void *value);
+static void ifentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void ifentry_get_value(struct obj_def *od, u16_t len, void *value);
+static void atentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void atentry_get_value(struct obj_def *od, u16_t len, void *value);
+static void ip_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void ip_get_value(struct obj_def *od, u16_t len, void *value);
+static u8_t ip_set_test(struct obj_def *od, u16_t len, void *value);
+static void ip_addrentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void ip_addrentry_get_value(struct obj_def *od, u16_t len, void *value);
+static void ip_rteentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void ip_rteentry_get_value(struct obj_def *od, u16_t len, void *value);
+static void ip_ntomentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void ip_ntomentry_get_value(struct obj_def *od, u16_t len, void *value);
+static void icmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void icmp_get_value(struct obj_def *od, u16_t len, void *value);
+#if LWIP_TCP
+static void tcp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void tcp_get_value(struct obj_def *od, u16_t len, void *value);
+static void tcpconnentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void tcpconnentry_get_value(struct obj_def *od, u16_t len, void *value);
+#endif
+static void udp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void udp_get_value(struct obj_def *od, u16_t len, void *value);
+static void udpentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void udpentry_get_value(struct obj_def *od, u16_t len, void *value);
+static void snmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void snmp_get_value(struct obj_def *od, u16_t len, void *value);
+static u8_t snmp_set_test(struct obj_def *od, u16_t len, void *value);
+static void snmp_set_value(struct obj_def *od, u16_t len, void *value);
+
+
+/* snmp .1.3.6.1.2.1.11 */
+const mib_scalar_node snmp_scalar = {
+  &snmp_get_object_def,
+  &snmp_get_value,
+  &snmp_set_test,
+  &snmp_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t snmp_ids[28] = {
+  1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+  17, 18, 19, 20, 21, 22, 24, 25, 26, 27, 28, 29, 30
+};
+struct mib_node* const snmp_nodes[28] = {
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar
+};
+const struct mib_array_node snmp = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  28,
+  snmp_ids,
+  snmp_nodes
+};
+
+/* dot3 and EtherLike MIB not planned. (transmission .1.3.6.1.2.1.10) */
+/* historical (some say hysterical). (cmot .1.3.6.1.2.1.9) */
+/* lwIP has no EGP, thus may not implement it. (egp .1.3.6.1.2.1.8) */
+
+/* udp .1.3.6.1.2.1.7 */
+/** index root node for udpTable */
+struct mib_list_rootnode udp_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t udpentry_ids[2] = { 1, 2 };
+struct mib_node* const udpentry_nodes[2] = {
+  (struct mib_node* const)&udp_root, (struct mib_node* const)&udp_root,
+};
+const struct mib_array_node udpentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  2,
+  udpentry_ids,
+  udpentry_nodes
+};
+
+s32_t udptable_id = 1;
+struct mib_node* udptable_node = (struct mib_node* const)&udpentry;
+struct mib_ram_array_node udptable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &udptable_id,
+  &udptable_node
+};
+
+const mib_scalar_node udp_scalar = {
+  &udp_get_object_def,
+  &udp_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t udp_ids[5] = { 1, 2, 3, 4, 5 };
+struct mib_node* const udp_nodes[5] = {
+  (struct mib_node* const)&udp_scalar, (struct mib_node* const)&udp_scalar,
+  (struct mib_node* const)&udp_scalar, (struct mib_node* const)&udp_scalar,
+  (struct mib_node* const)&udptable
+};
+const struct mib_array_node udp = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  5,
+  udp_ids,
+  udp_nodes
+};
+
+/* tcp .1.3.6.1.2.1.6 */
+#if LWIP_TCP
+/* only if the TCP protocol is available may implement this group */
+/** index root node for tcpConnTable */
+struct mib_list_rootnode tcpconntree_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t tcpconnentry_ids[5] = { 1, 2, 3, 4, 5 };
+struct mib_node* const tcpconnentry_nodes[5] = {
+  (struct mib_node* const)&tcpconntree_root, (struct mib_node* const)&tcpconntree_root,
+  (struct mib_node* const)&tcpconntree_root, (struct mib_node* const)&tcpconntree_root,
+  (struct mib_node* const)&tcpconntree_root
+};
+const struct mib_array_node tcpconnentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  5,
+  tcpconnentry_ids,
+  tcpconnentry_nodes
+};
+
+s32_t tcpconntable_id = 1;
+struct mib_node* tcpconntable_node = (struct mib_node* const)&tcpconnentry;
+struct mib_ram_array_node tcpconntable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+/** @todo update maxlength when inserting / deleting from table
+   0 when table is empty, 1 when more than one entry */
+  0,
+  &tcpconntable_id,
+  &tcpconntable_node
+};
+
+const mib_scalar_node tcp_scalar = {
+  &tcp_get_object_def,
+  &tcp_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t tcp_ids[15] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
+struct mib_node* const tcp_nodes[15] = {
+  (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar,
+  (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar,
+  (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar,
+  (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar,
+  (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar,
+  (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar,
+  (struct mib_node* const)&tcpconntable, (struct mib_node* const)&tcp_scalar,
+  (struct mib_node* const)&tcp_scalar
+};
+const struct mib_array_node tcp = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  15,
+  tcp_ids,
+  tcp_nodes
+};
+#endif
+
+/* icmp .1.3.6.1.2.1.5 */
+const mib_scalar_node icmp_scalar = {
+  &icmp_get_object_def,
+  &icmp_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t icmp_ids[26] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 };
+struct mib_node* const icmp_nodes[26] = {
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar
+};
+const struct mib_array_node icmp = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  26,
+  icmp_ids,
+  icmp_nodes
+};
+
+/** index root node for ipNetToMediaTable */
+struct mib_list_rootnode ipntomtree_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t ipntomentry_ids[4] = { 1, 2, 3, 4 };
+struct mib_node* const ipntomentry_nodes[4] = {
+  (struct mib_node* const)&ipntomtree_root, (struct mib_node* const)&ipntomtree_root,
+  (struct mib_node* const)&ipntomtree_root, (struct mib_node* const)&ipntomtree_root
+};
+const struct mib_array_node ipntomentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  4,
+  ipntomentry_ids,
+  ipntomentry_nodes
+};
+
+s32_t ipntomtable_id = 1;
+struct mib_node* ipntomtable_node = (struct mib_node* const)&ipntomentry;
+struct mib_ram_array_node ipntomtable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &ipntomtable_id,
+  &ipntomtable_node
+};
+
+/** index root node for ipRouteTable */
+struct mib_list_rootnode iprtetree_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t iprteentry_ids[13] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 };
+struct mib_node* const iprteentry_nodes[13] = {
+  (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root,
+  (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root,
+  (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root,
+  (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root,
+  (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root,
+  (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root,
+  (struct mib_node* const)&iprtetree_root
+};
+const struct mib_array_node iprteentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  13,
+  iprteentry_ids,
+  iprteentry_nodes
+};
+
+s32_t iprtetable_id = 1;
+struct mib_node* iprtetable_node = (struct mib_node* const)&iprteentry;
+struct mib_ram_array_node iprtetable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &iprtetable_id,
+  &iprtetable_node
+};
+
+/** index root node for ipAddrTable */
+struct mib_list_rootnode ipaddrtree_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t ipaddrentry_ids[5] = { 1, 2, 3, 4, 5 };
+struct mib_node* const ipaddrentry_nodes[5] = {
+  (struct mib_node* const)&ipaddrtree_root,
+  (struct mib_node* const)&ipaddrtree_root,
+  (struct mib_node* const)&ipaddrtree_root,
+  (struct mib_node* const)&ipaddrtree_root,
+  (struct mib_node* const)&ipaddrtree_root
+};
+const struct mib_array_node ipaddrentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  5,
+  ipaddrentry_ids,
+  ipaddrentry_nodes
+};
+
+s32_t ipaddrtable_id = 1;
+struct mib_node* ipaddrtable_node = (struct mib_node* const)&ipaddrentry;
+struct mib_ram_array_node ipaddrtable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &ipaddrtable_id,
+  &ipaddrtable_node
+};
+
+/* ip .1.3.6.1.2.1.4 */
+const mib_scalar_node ip_scalar = {
+  &ip_get_object_def,
+  &ip_get_value,
+  &ip_set_test,
+  &noleafs_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t ip_ids[23] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 };
+struct mib_node* const ip_nodes[23] = {
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ipaddrtable,
+  (struct mib_node* const)&iprtetable, (struct mib_node* const)&ipntomtable,
+  (struct mib_node* const)&ip_scalar
+};
+const struct mib_array_node ip = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  23,
+  ip_ids,
+  ip_nodes
+};
+
+/** index root node for atTable */
+struct mib_list_rootnode arptree_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t atentry_ids[3] = { 1, 2, 3 };
+struct mib_node* const atentry_nodes[3] = {
+  (struct mib_node* const)&arptree_root,
+  (struct mib_node* const)&arptree_root,
+  (struct mib_node* const)&arptree_root
+};
+const struct mib_array_node atentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  3,
+  atentry_ids,
+  atentry_nodes
+};
+
+const s32_t attable_id = 1;
+struct mib_node* const attable_node = (struct mib_node* const)&atentry;
+const struct mib_array_node attable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  1,
+  &attable_id,
+  &attable_node
+};
+
+/* at .1.3.6.1.2.1.3 */
+s32_t at_id = 1;
+struct mib_node* at_node = (struct mib_node* const)&attable;
+struct mib_ram_array_node at = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &at_id,
+  &at_node
+};
+
+/** index root node for ifTable */
+struct mib_list_rootnode iflist_root = {
+  &ifentry_get_object_def,
+  &ifentry_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t ifentry_ids[22] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 };
+struct mib_node* const ifentry_nodes[22] = {
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root
+};
+const struct mib_array_node ifentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  22,
+  ifentry_ids,
+  ifentry_nodes
+};
+
+s32_t iftable_id = 1;
+struct mib_node* iftable_node = (struct mib_node* const)&ifentry;
+struct mib_ram_array_node iftable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &iftable_id,
+  &iftable_node
+};
+
+/* interfaces .1.3.6.1.2.1.2 */
+const mib_scalar_node interfaces_scalar = {
+  &interfaces_get_object_def,
+  &interfaces_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t interfaces_ids[2] = { 1, 2 };
+struct mib_node* const interfaces_nodes[2] = {
+  (struct mib_node* const)&interfaces_scalar, (struct mib_node* const)&iftable
+};
+const struct mib_array_node interfaces = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  2,
+  interfaces_ids,
+  interfaces_nodes
+};
+
+
+/*             0 1 2 3 4 5 6 */
+/* system .1.3.6.1.2.1.1 */
+const mib_scalar_node sys_tem_scalar = {
+  &system_get_object_def,
+  &system_get_value,
+  &system_set_test,
+  &system_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t sys_tem_ids[7] = { 1, 2, 3, 4, 5, 6, 7 };
+struct mib_node* const sys_tem_nodes[7] = {
+  (struct mib_node* const)&sys_tem_scalar, (struct mib_node* const)&sys_tem_scalar,
+  (struct mib_node* const)&sys_tem_scalar, (struct mib_node* const)&sys_tem_scalar,
+  (struct mib_node* const)&sys_tem_scalar, (struct mib_node* const)&sys_tem_scalar,
+  (struct mib_node* const)&sys_tem_scalar
+};
+/* work around name issue with 'sys_tem', some compiler(s?) seem to reserve 'system' */
+const struct mib_array_node sys_tem = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  7,
+  sys_tem_ids,
+  sys_tem_nodes
+};
+
+/* mib-2 .1.3.6.1.2.1 */
+#if LWIP_TCP
+#define MIB2_GROUPS 8
+#else
+#define MIB2_GROUPS 7
+#endif
+const s32_t mib2_ids[MIB2_GROUPS] =
+{
+  1,
+  2,
+  3,
+  4,
+  5,
+#if LWIP_TCP
+  6,
+#endif
+  7,
+  11
+};
+struct mib_node* const mib2_nodes[MIB2_GROUPS] = {
+  (struct mib_node* const)&sys_tem,
+  (struct mib_node* const)&interfaces,
+  (struct mib_node* const)&at,
+  (struct mib_node* const)&ip,
+  (struct mib_node* const)&icmp,
+#if LWIP_TCP
+  (struct mib_node* const)&tcp,
+#endif
+  (struct mib_node* const)&udp,
+  (struct mib_node* const)&snmp
+};
+
+const struct mib_array_node mib2 = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  MIB2_GROUPS,
+  mib2_ids,
+  mib2_nodes
+};
+
+/* mgmt .1.3.6.1.2 */
+const s32_t mgmt_ids[1] = { 1 };
+struct mib_node* const mgmt_nodes[1] = { (struct mib_node* const)&mib2 };
+const struct mib_array_node mgmt = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  1,
+  mgmt_ids,
+  mgmt_nodes
+};
+
+/* internet .1.3.6.1 */
+#if SNMP_PRIVATE_MIB
+s32_t internet_ids[2] = { 2, 4 };
+struct mib_node* const internet_nodes[2] = { (struct mib_node* const)&mgmt, (struct mib_node* const)&private };
+const struct mib_array_node internet = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  2,
+  internet_ids,
+  internet_nodes
+};
+#else
+const s32_t internet_ids[1] = { 2 };
+struct mib_node* const internet_nodes[1] = { (struct mib_node* const)&mgmt };
+const struct mib_array_node internet = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  1,
+  internet_ids,
+  internet_nodes
+};
+#endif
+
+/** mib-2.system.sysObjectID  */
+static struct snmp_obj_id sysobjid = {SNMP_SYSOBJID_LEN, SNMP_SYSOBJID};
+/** enterprise ID for generic TRAPs, .iso.org.dod.internet.mgmt.mib-2.snmp */
+static struct snmp_obj_id snmpgrp_id = {7,{1,3,6,1,2,1,11}};
+/** mib-2.system.sysServices */
+static const s32_t sysservices = SNMP_SYSSERVICES;
+
+/** mib-2.system.sysDescr */
+static const u8_t sysdescr_len_default = 4;
+static const u8_t sysdescr_default[] = "lwIP";
+static u8_t* sysdescr_len_ptr = (u8_t*)&sysdescr_len_default;
+static u8_t* sysdescr_ptr = (u8_t*)&sysdescr_default[0];
+/** mib-2.system.sysContact */
+static const u8_t syscontact_len_default = 0;
+static const u8_t syscontact_default[] = "";
+static u8_t* syscontact_len_ptr = (u8_t*)&syscontact_len_default;
+static u8_t* syscontact_ptr = (u8_t*)&syscontact_default[0];
+/** mib-2.system.sysName */
+static const u8_t sysname_len_default = 8;
+static const u8_t sysname_default[] = "FQDN-unk";
+static u8_t* sysname_len_ptr = (u8_t*)&sysname_len_default;
+static u8_t* sysname_ptr = (u8_t*)&sysname_default[0];
+/** mib-2.system.sysLocation */
+static const u8_t syslocation_len_default = 0;
+static const u8_t syslocation_default[] = "";
+static u8_t* syslocation_len_ptr = (u8_t*)&syslocation_len_default;
+static u8_t* syslocation_ptr = (u8_t*)&syslocation_default[0];
+/** mib-2.snmp.snmpEnableAuthenTraps */
+static const u8_t snmpenableauthentraps_default = 2; /* disabled */
+static u8_t* snmpenableauthentraps_ptr = (u8_t*)&snmpenableauthentraps_default;
+
+/** mib-2.interfaces.ifTable.ifEntry.ifSpecific (zeroDotZero) */
+static const struct snmp_obj_id ifspecific = {2, {0, 0}};
+/** mib-2.ip.ipRouteTable.ipRouteEntry.ipRouteInfo (zeroDotZero) */
+static const struct snmp_obj_id iprouteinfo = {2, {0, 0}};
+
+
+
+/* mib-2.system counter(s) */
+static u32_t sysuptime = 0;
+
+/* mib-2.ip counter(s) */
+static u32_t ipinreceives = 0,
+             ipinhdrerrors = 0,
+             ipinaddrerrors = 0,
+             ipforwdatagrams = 0,
+             ipinunknownprotos = 0,
+             ipindiscards = 0,
+             ipindelivers = 0,
+             ipoutrequests = 0,
+             ipoutdiscards = 0,
+             ipoutnoroutes = 0,
+             ipreasmreqds = 0,
+             ipreasmoks = 0,
+             ipreasmfails = 0,
+             ipfragoks = 0,
+             ipfragfails = 0,
+             ipfragcreates = 0,
+             iproutingdiscards = 0;
+/* mib-2.icmp counter(s) */
+static u32_t icmpinmsgs = 0,
+             icmpinerrors = 0,
+             icmpindestunreachs = 0,
+             icmpintimeexcds = 0,
+             icmpinparmprobs = 0,
+             icmpinsrcquenchs = 0,
+             icmpinredirects = 0,
+             icmpinechos = 0,
+             icmpinechoreps = 0,
+             icmpintimestamps = 0,
+             icmpintimestampreps = 0,
+             icmpinaddrmasks = 0,
+             icmpinaddrmaskreps = 0,
+             icmpoutmsgs = 0,
+             icmpouterrors = 0,
+             icmpoutdestunreachs = 0,
+             icmpouttimeexcds = 0,
+             icmpoutparmprobs = 0,
+             icmpoutsrcquenchs = 0,
+             icmpoutredirects = 0,
+             icmpoutechos = 0,
+             icmpoutechoreps = 0,
+             icmpouttimestamps = 0,
+             icmpouttimestampreps = 0,
+             icmpoutaddrmasks = 0,
+             icmpoutaddrmaskreps = 0;
+/* mib-2.tcp counter(s) */
+static u32_t tcpactiveopens = 0,
+             tcppassiveopens = 0,
+             tcpattemptfails = 0,
+             tcpestabresets = 0,
+             tcpinsegs = 0,
+             tcpoutsegs = 0,
+             tcpretranssegs = 0,
+             tcpinerrs = 0,
+             tcpoutrsts = 0;
+/* mib-2.udp counter(s) */
+static u32_t udpindatagrams = 0,
+             udpnoports = 0,
+             udpinerrors = 0,
+             udpoutdatagrams = 0;
+/* mib-2.snmp counter(s) */
+static u32_t snmpinpkts = 0,
+             snmpoutpkts = 0,
+             snmpinbadversions = 0,
+             snmpinbadcommunitynames = 0,
+             snmpinbadcommunityuses = 0,
+             snmpinasnparseerrs = 0,
+             snmpintoobigs = 0,
+             snmpinnosuchnames = 0,
+             snmpinbadvalues = 0,
+             snmpinreadonlys = 0,
+             snmpingenerrs = 0,
+             snmpintotalreqvars = 0,
+             snmpintotalsetvars = 0,
+             snmpingetrequests = 0,
+             snmpingetnexts = 0,
+             snmpinsetrequests = 0,
+             snmpingetresponses = 0,
+             snmpintraps = 0,
+             snmpouttoobigs = 0,
+             snmpoutnosuchnames = 0,
+             snmpoutbadvalues = 0,
+             snmpoutgenerrs = 0,
+             snmpoutgetrequests = 0,
+             snmpoutgetnexts = 0,
+             snmpoutsetrequests = 0,
+             snmpoutgetresponses = 0,
+             snmpouttraps = 0;
+
+
+
+/* prototypes of the following functions are in lwip/src/include/lwip/snmp.h */
+/**
+ * Copy octet string.
+ *
+ * @param dst points to destination
+ * @param src points to source
+ * @param n number of octets to copy.
+ */
+void ocstrncpy(u8_t *dst, u8_t *src, u8_t n)
+{
+  while (n > 0)
+  {
+    n--;
+    *dst++ = *src++;
+  }
+}
+
+/**
+ * Copy object identifier (s32_t) array.
+ *
+ * @param dst points to destination
+ * @param src points to source
+ * @param n number of sub identifiers to copy.
+ */
+void objectidncpy(s32_t *dst, s32_t *src, u8_t n)
+{
+  while(n > 0)
+  {
+    n--;
+    *dst++ = *src++;
+  }
+}
+
+/**
+ * Initializes sysDescr pointers.
+ *
+ * @param str if non-NULL then copy str pointer
+ * @param strlen points to string length, excluding zero terminator
+ */
+void snmp_set_sysdesr(u8_t *str, u8_t *strlen)
+{
+  if (str != NULL)
+  {
+    sysdescr_ptr = str;
+    sysdescr_len_ptr = strlen;
+  }
+}
+
+void snmp_get_sysobjid_ptr(struct snmp_obj_id **oid)
+{
+  *oid = &sysobjid;
+}
+
+/**
+ * Initializes sysObjectID value.
+ *
+ * @param oid points to stuct snmp_obj_id to copy
+ */
+void snmp_set_sysobjid(struct snmp_obj_id *oid)
+{
+  sysobjid = *oid;
+}
+
+/**
+ * Must be called at regular 10 msec interval from a timer interrupt
+ * or signal handler depending on your runtime environment.
+ */
+void snmp_inc_sysuptime(void)
+{
+  sysuptime++;
+}
+
+void snmp_get_sysuptime(u32_t *value)
+{
+  *value = sysuptime;
+}
+
+/**
+ * Initializes sysContact pointers,
+ * e.g. ptrs to non-volatile memory external to lwIP.
+ *
+ * @param str if non-NULL then copy str pointer
+ * @param strlen points to string length, excluding zero terminator
+ */
+void snmp_set_syscontact(u8_t *ocstr, u8_t *ocstrlen)
+{
+  if (ocstr != NULL)
+  {
+    syscontact_ptr = ocstr;
+    syscontact_len_ptr = ocstrlen;
+  }
+}
+
+/**
+ * Initializes sysName pointers,
+ * e.g. ptrs to non-volatile memory external to lwIP.
+ *
+ * @param str if non-NULL then copy str pointer
+ * @param strlen points to string length, excluding zero terminator
+ */
+void snmp_set_sysname(u8_t *ocstr, u8_t *ocstrlen)
+{
+  if (ocstr != NULL)
+  {
+    sysname_ptr = ocstr;
+    sysname_len_ptr = ocstrlen;
+  }
+}
+
+/**
+ * Initializes sysLocation pointers,
+ * e.g. ptrs to non-volatile memory external to lwIP.
+ *
+ * @param str if non-NULL then copy str pointer
+ * @param strlen points to string length, excluding zero terminator
+ */
+void snmp_set_syslocation(u8_t *ocstr, u8_t *ocstrlen)
+{
+  if (ocstr != NULL)
+  {
+    syslocation_ptr = ocstr;
+    syslocation_len_ptr = ocstrlen;
+  }
+}
+
+
+void snmp_add_ifinoctets(struct netif *ni, u32_t value)
+{
+  ni->ifinoctets += value;
+}
+
+void snmp_inc_ifinucastpkts(struct netif *ni)
+{
+  (ni->ifinucastpkts)++;
+}
+
+void snmp_inc_ifinnucastpkts(struct netif *ni)
+{
+  (ni->ifinnucastpkts)++;
+}
+
+void snmp_inc_ifindiscards(struct netif *ni)
+{
+  (ni->ifindiscards)++;
+}
+
+void snmp_add_ifoutoctets(struct netif *ni, u32_t value)
+{
+  ni->ifoutoctets += value;
+}
+
+void snmp_inc_ifoutucastpkts(struct netif *ni)
+{
+  (ni->ifoutucastpkts)++;
+}
+
+void snmp_inc_ifoutnucastpkts(struct netif *ni)
+{
+  (ni->ifoutnucastpkts)++;
+}
+
+void snmp_inc_ifoutdiscards(struct netif *ni)
+{
+  (ni->ifoutdiscards)++;
+}
+
+void snmp_inc_iflist(void)
+{
+  struct mib_list_node *if_node = NULL;
+
+  snmp_mib_node_insert(&iflist_root, iflist_root.count + 1, &if_node);
+  /* enable getnext traversal on filled table */
+  iftable.maxlength = 1;
+}
+
+void snmp_dec_iflist(void)
+{
+  snmp_mib_node_delete(&iflist_root, iflist_root.tail);
+  /* disable getnext traversal on empty table */
+  if(iflist_root.count == 0) iftable.maxlength = 0;
+}
+
+/**
+ * Inserts ARP table indexes (.xIfIndex.xNetAddress)
+ * into arp table index trees (both atTable and ipNetToMediaTable).
+ */
+void snmp_insert_arpidx_tree(struct netif *ni, struct ip_addr *ip)
+{
+  struct mib_list_rootnode *at_rn;
+  struct mib_list_node *at_node;
+  struct ip_addr hip;
+  s32_t arpidx[5];
+  u8_t level, tree;
+
+  LWIP_ASSERT("ni != NULL", ni != NULL);
+  snmp_netiftoifindex(ni, &arpidx[0]);
+  hip.addr = ntohl(ip->addr);
+  snmp_iptooid(&hip, &arpidx[1]);
+
+  for (tree = 0; tree < 2; tree++)
+  {
+    if (tree == 0)
+    {
+      at_rn = &arptree_root;
+    }
+    else
+    {
+      at_rn = &ipntomtree_root;
+    }
+    for (level = 0; level < 5; level++)
+    {
+      at_node = NULL;
+      snmp_mib_node_insert(at_rn, arpidx[level], &at_node);
+      if ((level != 4) && (at_node != NULL))
+      {
+        if (at_node->nptr == NULL)
+        {
+          at_rn = snmp_mib_lrn_alloc();
+          at_node->nptr = (struct mib_node*)at_rn;
+          if (at_rn != NULL)
+          {
+            if (level == 3)
+            {
+              if (tree == 0)
+              {
+                at_rn->get_object_def = atentry_get_object_def;
+                at_rn->get_value = atentry_get_value;
+              }
+              else
+              {
+                at_rn->get_object_def = ip_ntomentry_get_object_def;
+                at_rn->get_value = ip_ntomentry_get_value;
+              }
+              at_rn->set_test = noleafs_set_test;
+              at_rn->set_value = noleafs_set_value;
+            }
+          }
+          else
+          {
+            /* at_rn == NULL, malloc failure */
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_arpidx_tree() insert failed, mem full"));
+            break;
+          }
+        }
+        else
+        {
+          at_rn = (struct mib_list_rootnode*)at_node->nptr;
+        }
+      }
+    }
+  }
+  /* enable getnext traversal on filled tables */
+  at.maxlength = 1;
+  ipntomtable.maxlength = 1;
+}
+
+/**
+ * Removes ARP table indexes (.xIfIndex.xNetAddress)
+ * from arp table index trees.
+ */
+void snmp_delete_arpidx_tree(struct netif *ni, struct ip_addr *ip)
+{
+  struct mib_list_rootnode *at_rn, *next, *del_rn[5];
+  struct mib_list_node *at_n, *del_n[5];
+  struct ip_addr hip;
+  s32_t arpidx[5];
+  u8_t fc, tree, level, del_cnt;
+
+  snmp_netiftoifindex(ni, &arpidx[0]);
+  hip.addr = ntohl(ip->addr);
+  snmp_iptooid(&hip, &arpidx[1]);
+
+  for (tree = 0; tree < 2; tree++)
+  {
+    /* mark nodes for deletion */
+    if (tree == 0)
+    {
+      at_rn = &arptree_root;
+    }
+    else
+    {
+      at_rn = &ipntomtree_root;
+    }
+    level = 0;
+    del_cnt = 0;
+    while ((level < 5) && (at_rn != NULL))
+    {
+      fc = snmp_mib_node_find(at_rn, arpidx[level], &at_n);
+      if (fc == 0)
+      {
+        /* arpidx[level] does not exist */
+        del_cnt = 0;
+        at_rn = NULL;
+      }
+      else if (fc == 1)
+      {
+        del_rn[del_cnt] = at_rn;
+        del_n[del_cnt] = at_n;
+        del_cnt++;
+        at_rn = (struct mib_list_rootnode*)(at_n->nptr);
+      }
+      else if (fc == 2)
+      {
+        /* reset delete (2 or more childs) */
+        del_cnt = 0;
+        at_rn = (struct mib_list_rootnode*)(at_n->nptr);
+      }
+      level++;
+    }
+    /* delete marked index nodes */
+    while (del_cnt > 0)
+    {
+      del_cnt--;
+
+      at_rn = del_rn[del_cnt];
+      at_n = del_n[del_cnt];
+
+      next = snmp_mib_node_delete(at_rn, at_n);
+      if (next != NULL)
+      {
+        LWIP_ASSERT("next_count == 0",next->count == 0);
+        snmp_mib_lrn_free(next);
+      }
+    }
+  }
+  /* disable getnext traversal on empty tables */
+  if(arptree_root.count == 0) at.maxlength = 0;
+  if(ipntomtree_root.count == 0) ipntomtable.maxlength = 0;
+}
+
+void snmp_inc_ipinreceives(void)
+{
+  ipinreceives++;
+}
+
+void snmp_inc_ipinhdrerrors(void)
+{
+  ipinhdrerrors++;
+}
+
+void snmp_inc_ipinaddrerrors(void)
+{
+  ipinaddrerrors++;
+}
+
+void snmp_inc_ipforwdatagrams(void)
+{
+  ipforwdatagrams++;
+}
+
+void snmp_inc_ipinunknownprotos(void)
+{
+  ipinunknownprotos++;
+}
+
+void snmp_inc_ipindiscards(void)
+{
+  ipindiscards++;
+}
+
+void snmp_inc_ipindelivers(void)
+{
+  ipindelivers++;
+}
+
+void snmp_inc_ipoutrequests(void)
+{
+  ipoutrequests++;
+}
+
+void snmp_inc_ipoutdiscards(void)
+{
+  ipoutdiscards++;
+}
+
+void snmp_inc_ipoutnoroutes(void)
+{
+  ipoutnoroutes++;
+}
+
+void snmp_inc_ipreasmreqds(void)
+{
+  ipreasmreqds++;
+}
+
+void snmp_inc_ipreasmoks(void)
+{
+  ipreasmoks++;
+}
+
+void snmp_inc_ipreasmfails(void)
+{
+  ipreasmfails++;
+}
+
+void snmp_inc_ipfragoks(void)
+{
+  ipfragoks++;
+}
+
+void snmp_inc_ipfragfails(void)
+{
+  ipfragfails++;
+}
+
+void snmp_inc_ipfragcreates(void)
+{
+  ipfragcreates++;
+}
+
+void snmp_inc_iproutingdiscards(void)
+{
+  iproutingdiscards++;
+}
+
+/**
+ * Inserts ipAddrTable indexes (.ipAdEntAddr)
+ * into index tree.
+ */
+void snmp_insert_ipaddridx_tree(struct netif *ni)
+{
+  struct mib_list_rootnode *ipa_rn;
+  struct mib_list_node *ipa_node;
+  struct ip_addr ip;
+  s32_t ipaddridx[4];
+  u8_t level;
+
+  LWIP_ASSERT("ni != NULL", ni != NULL);
+  ip.addr = ntohl(ni->ip_addr.addr);
+  snmp_iptooid(&ip, &ipaddridx[0]);
+
+  level = 0;
+  ipa_rn = &ipaddrtree_root;
+  while (level < 4)
+  {
+    ipa_node = NULL;
+    snmp_mib_node_insert(ipa_rn, ipaddridx[level], &ipa_node);
+    if ((level != 3) && (ipa_node != NULL))
+    {
+      if (ipa_node->nptr == NULL)
+      {
+        ipa_rn = snmp_mib_lrn_alloc();
+        ipa_node->nptr = (struct mib_node*)ipa_rn;
+        if (ipa_rn != NULL)
+        {
+          if (level == 2)
+          {
+            ipa_rn->get_object_def = ip_addrentry_get_object_def;
+            ipa_rn->get_value = ip_addrentry_get_value;
+            ipa_rn->set_test = noleafs_set_test;
+            ipa_rn->set_value = noleafs_set_value;
+          }
+        }
+        else
+        {
+          /* ipa_rn == NULL, malloc failure */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_ipaddridx_tree() insert failed, mem full"));
+          break;
+        }
+      }
+      else
+      {
+        ipa_rn = (struct mib_list_rootnode*)ipa_node->nptr;
+      }
+    }
+    level++;
+  }
+  /* enable getnext traversal on filled table */
+  ipaddrtable.maxlength = 1;
+}
+
+/**
+ * Removes ipAddrTable indexes (.ipAdEntAddr)
+ * from index tree.
+ */
+void snmp_delete_ipaddridx_tree(struct netif *ni)
+{
+  struct mib_list_rootnode *ipa_rn, *next, *del_rn[4];
+  struct mib_list_node *ipa_n, *del_n[4];
+  struct ip_addr ip;
+  s32_t ipaddridx[4];
+  u8_t fc, level, del_cnt;
+
+  LWIP_ASSERT("ni != NULL", ni != NULL);
+  ip.addr = ntohl(ni->ip_addr.addr);
+  snmp_iptooid(&ip, &ipaddridx[0]);
+
+  /* mark nodes for deletion */
+  level = 0;
+  del_cnt = 0;
+  ipa_rn = &ipaddrtree_root;
+  while ((level < 4) && (ipa_rn != NULL))
+  {
+    fc = snmp_mib_node_find(ipa_rn, ipaddridx[level], &ipa_n);
+    if (fc == 0)
+    {
+      /* ipaddridx[level] does not exist */
+      del_cnt = 0;
+      ipa_rn = NULL;
+    }
+    else if (fc == 1)
+    {
+      del_rn[del_cnt] = ipa_rn;
+      del_n[del_cnt] = ipa_n;
+      del_cnt++;
+      ipa_rn = (struct mib_list_rootnode*)(ipa_n->nptr);
+    }
+    else if (fc == 2)
+    {
+      /* reset delete (2 or more childs) */
+      del_cnt = 0;
+      ipa_rn = (struct mib_list_rootnode*)(ipa_n->nptr);
+    }
+    level++;
+  }
+  /* delete marked index nodes */
+  while (del_cnt > 0)
+  {
+    del_cnt--;
+
+    ipa_rn = del_rn[del_cnt];
+    ipa_n = del_n[del_cnt];
+
+    next = snmp_mib_node_delete(ipa_rn, ipa_n);
+    if (next != NULL)
+    {
+      LWIP_ASSERT("next_count == 0",next->count == 0);
+      snmp_mib_lrn_free(next);
+    }
+  }
+  /* disable getnext traversal on empty table */
+  if (ipaddrtree_root.count == 0) ipaddrtable.maxlength = 0;
+}
+
+/**
+ * Inserts ipRouteTable indexes (.ipRouteDest)
+ * into index tree.
+ *
+ * @param dflt non-zero for the default rte, zero for network rte
+ * @param netif points to network interface for this rte
+ *
+ * @todo record sysuptime for _this_ route when it is installed
+ *   (needed for ipRouteAge) in the netif.
+ */
+void snmp_insert_iprteidx_tree(u8_t dflt, struct netif *ni)
+{
+  u8_t insert = 0;
+  struct ip_addr dst;
+
+  if (dflt != 0)
+  {
+    /* the default route 0.0.0.0 */
+    dst.addr = 0;
+    insert = 1;
+  }
+  else
+  {
+    /* route to the network address */
+    dst.addr = ntohl(ni->ip_addr.addr & ni->netmask.addr);
+    /* exclude 0.0.0.0 network (reserved for default rte) */
+    if (dst.addr != 0) insert = 1;
+  }
+  if (insert)
+  {
+    struct mib_list_rootnode *iprte_rn;
+    struct mib_list_node *iprte_node;
+    s32_t iprteidx[4];
+    u8_t level;
+
+    snmp_iptooid(&dst, &iprteidx[0]);
+    level = 0;
+    iprte_rn = &iprtetree_root;
+    while (level < 4)
+    {
+      iprte_node = NULL;
+      snmp_mib_node_insert(iprte_rn, iprteidx[level], &iprte_node);
+      if ((level != 3) && (iprte_node != NULL))
+      {
+        if (iprte_node->nptr == NULL)
+        {
+          iprte_rn = snmp_mib_lrn_alloc();
+          iprte_node->nptr = (struct mib_node*)iprte_rn;
+          if (iprte_rn != NULL)
+          {
+            if (level == 2)
+            {
+              iprte_rn->get_object_def = ip_rteentry_get_object_def;
+              iprte_rn->get_value = ip_rteentry_get_value;
+              iprte_rn->set_test = noleafs_set_test;
+              iprte_rn->set_value = noleafs_set_value;
+            }
+          }
+          else
+          {
+            /* iprte_rn == NULL, malloc failure */
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_iprteidx_tree() insert failed, mem full"));
+            break;
+          }
+        }
+        else
+        {
+          iprte_rn = (struct mib_list_rootnode*)iprte_node->nptr;
+        }
+      }
+      level++;
+    }
+  }
+  /* enable getnext traversal on filled table */
+  iprtetable.maxlength = 1;
+}
+
+/**
+ * Removes ipRouteTable indexes (.ipRouteDest)
+ * from index tree.
+ *
+ * @param dflt non-zero for the default rte, zero for network rte
+ * @param netif points to network interface for this rte or NULL
+ *   for default route to be removed.
+ */
+void snmp_delete_iprteidx_tree(u8_t dflt, struct netif *ni)
+{
+  u8_t delete = 0;
+  struct ip_addr dst;
+
+  if (dflt != 0)
+  {
+    /* the default route 0.0.0.0 */
+    dst.addr = 0;
+    delete = 1;
+  }
+  else
+  {
+    /* route to the network address */
+    dst.addr = ntohl(ni->ip_addr.addr & ni->netmask.addr);
+    /* exclude 0.0.0.0 network (reserved for default rte) */
+    if (dst.addr != 0) delete = 1;
+  }
+  if (delete)
+  {
+    struct mib_list_rootnode *iprte_rn, *next, *del_rn[4];
+    struct mib_list_node *iprte_n, *del_n[4];
+    s32_t iprteidx[4];
+    u8_t fc, level, del_cnt;
+
+    snmp_iptooid(&dst, &iprteidx[0]);
+    /* mark nodes for deletion */
+    level = 0;
+    del_cnt = 0;
+    iprte_rn = &iprtetree_root;
+    while ((level < 4) && (iprte_rn != NULL))
+    {
+      fc = snmp_mib_node_find(iprte_rn, iprteidx[level], &iprte_n);
+      if (fc == 0)
+      {
+        /* iprteidx[level] does not exist */
+        del_cnt = 0;
+        iprte_rn = NULL;
+      }
+      else if (fc == 1)
+      {
+        del_rn[del_cnt] = iprte_rn;
+        del_n[del_cnt] = iprte_n;
+        del_cnt++;
+        iprte_rn = (struct mib_list_rootnode*)(iprte_n->nptr);
+      }
+      else if (fc == 2)
+      {
+        /* reset delete (2 or more childs) */
+        del_cnt = 0;
+        iprte_rn = (struct mib_list_rootnode*)(iprte_n->nptr);
+      }
+      level++;
+    }
+    /* delete marked index nodes */
+    while (del_cnt > 0)
+    {
+      del_cnt--;
+
+      iprte_rn = del_rn[del_cnt];
+      iprte_n = del_n[del_cnt];
+
+      next = snmp_mib_node_delete(iprte_rn, iprte_n);
+      if (next != NULL)
+      {
+        LWIP_ASSERT("next_count == 0",next->count == 0);
+        snmp_mib_lrn_free(next);
+      }
+    }
+  }
+  /* disable getnext traversal on empty table */
+  if (iprtetree_root.count == 0) iprtetable.maxlength = 0;
+}
+
+
+void snmp_inc_icmpinmsgs(void)
+{
+  icmpinmsgs++;
+}
+
+void snmp_inc_icmpinerrors(void)
+{
+  icmpinerrors++;
+}
+
+void snmp_inc_icmpindestunreachs(void)
+{
+  icmpindestunreachs++;
+}
+
+void snmp_inc_icmpintimeexcds(void)
+{
+  icmpintimeexcds++;
+}
+
+void snmp_inc_icmpinparmprobs(void)
+{
+  icmpinparmprobs++;
+}
+
+void snmp_inc_icmpinsrcquenchs(void)
+{
+  icmpinsrcquenchs++;
+}
+
+void snmp_inc_icmpinredirects(void)
+{
+  icmpinredirects++;
+}
+
+void snmp_inc_icmpinechos(void)
+{
+  icmpinechos++;
+}
+
+void snmp_inc_icmpinechoreps(void)
+{
+  icmpinechoreps++;
+}
+
+void snmp_inc_icmpintimestamps(void)
+{
+  icmpintimestamps++;
+}
+
+void snmp_inc_icmpintimestampreps(void)
+{
+  icmpintimestampreps++;
+}
+
+void snmp_inc_icmpinaddrmasks(void)
+{
+  icmpinaddrmasks++;
+}
+
+void snmp_inc_icmpinaddrmaskreps(void)
+{
+  icmpinaddrmaskreps++;
+}
+
+void snmp_inc_icmpoutmsgs(void)
+{
+  icmpoutmsgs++;
+}
+
+void snmp_inc_icmpouterrors(void)
+{
+  icmpouterrors++;
+}
+
+void snmp_inc_icmpoutdestunreachs(void)
+{
+  icmpoutdestunreachs++;
+}
+
+void snmp_inc_icmpouttimeexcds(void)
+{
+  icmpouttimeexcds++;
+}
+
+void snmp_inc_icmpoutparmprobs(void)
+{
+  icmpoutparmprobs++;
+}
+
+void snmp_inc_icmpoutsrcquenchs(void)
+{
+  icmpoutsrcquenchs++;
+}
+
+void snmp_inc_icmpoutredirects(void)
+{
+  icmpoutredirects++;
+}
+
+void snmp_inc_icmpoutechos(void)
+{
+  icmpoutechos++;
+}
+
+void snmp_inc_icmpoutechoreps(void)
+{
+  icmpoutechoreps++;
+}
+
+void snmp_inc_icmpouttimestamps(void)
+{
+  icmpouttimestamps++;
+}
+
+void snmp_inc_icmpouttimestampreps(void)
+{
+  icmpouttimestampreps++;
+}
+
+void snmp_inc_icmpoutaddrmasks(void)
+{
+  icmpoutaddrmasks++;
+}
+
+void snmp_inc_icmpoutaddrmaskreps(void)
+{
+  icmpoutaddrmaskreps++;
+}
+
+void snmp_inc_tcpactiveopens(void)
+{
+  tcpactiveopens++;
+}
+
+void snmp_inc_tcppassiveopens(void)
+{
+  tcppassiveopens++;
+}
+
+void snmp_inc_tcpattemptfails(void)
+{
+  tcpattemptfails++;
+}
+
+void snmp_inc_tcpestabresets(void)
+{
+  tcpestabresets++;
+}
+
+void snmp_inc_tcpinsegs(void)
+{
+  tcpinsegs++;
+}
+
+void snmp_inc_tcpoutsegs(void)
+{
+  tcpoutsegs++;
+}
+
+void snmp_inc_tcpretranssegs(void)
+{
+  tcpretranssegs++;
+}
+
+void snmp_inc_tcpinerrs(void)
+{
+  tcpinerrs++;
+}
+
+void snmp_inc_tcpoutrsts(void)
+{
+  tcpoutrsts++;
+}
+
+void snmp_inc_udpindatagrams(void)
+{
+  udpindatagrams++;
+}
+
+void snmp_inc_udpnoports(void)
+{
+  udpnoports++;
+}
+
+void snmp_inc_udpinerrors(void)
+{
+  udpinerrors++;
+}
+
+void snmp_inc_udpoutdatagrams(void)
+{
+  udpoutdatagrams++;
+}
+
+/**
+ * Inserts udpTable indexes (.udpLocalAddress.udpLocalPort)
+ * into index tree.
+ */
+void snmp_insert_udpidx_tree(struct udp_pcb *pcb)
+{
+  struct mib_list_rootnode *udp_rn;
+  struct mib_list_node *udp_node;
+  struct ip_addr ip;
+  s32_t udpidx[5];
+  u8_t level;
+
+  LWIP_ASSERT("pcb != NULL", pcb != NULL);
+  ip.addr = ntohl(pcb->local_ip.addr);
+  snmp_iptooid(&ip, &udpidx[0]);
+  udpidx[4] = pcb->local_port;
+
+  udp_rn = &udp_root;
+  for (level = 0; level < 5; level++)
+  {
+    udp_node = NULL;
+    snmp_mib_node_insert(udp_rn, udpidx[level], &udp_node);
+    if ((level != 4) && (udp_node != NULL))
+    {
+      if (udp_node->nptr == NULL)
+      {
+        udp_rn = snmp_mib_lrn_alloc();
+        udp_node->nptr = (struct mib_node*)udp_rn;
+        if (udp_rn != NULL)
+        {
+          if (level == 3)
+          {
+            udp_rn->get_object_def = udpentry_get_object_def;
+            udp_rn->get_value = udpentry_get_value;
+            udp_rn->set_test = noleafs_set_test;
+            udp_rn->set_value = noleafs_set_value;
+          }
+        }
+        else
+        {
+          /* udp_rn == NULL, malloc failure */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_udpidx_tree() insert failed, mem full"));
+          break;
+        }
+      }
+      else
+      {
+        udp_rn = (struct mib_list_rootnode*)udp_node->nptr;
+      }
+    }
+  }
+  udptable.maxlength = 1;
+}
+
+/**
+ * Removes udpTable indexes (.udpLocalAddress.udpLocalPort)
+ * from index tree.
+ */
+void snmp_delete_udpidx_tree(struct udp_pcb *pcb)
+{
+  struct mib_list_rootnode *udp_rn, *next, *del_rn[5];
+  struct mib_list_node *udp_n, *del_n[5];
+  struct ip_addr ip;
+  s32_t udpidx[5];
+  u8_t bindings, fc, level, del_cnt;
+
+  LWIP_ASSERT("pcb != NULL", pcb != NULL);
+  ip.addr = ntohl(pcb->local_ip.addr);
+  snmp_iptooid(&ip, &udpidx[0]);
+  udpidx[4] = pcb->local_port;
+
+  /* count PCBs for a given binding
+     (e.g. when reusing ports or for temp output PCBs) */
+  bindings = 0;
+  pcb = udp_pcbs;
+  while ((pcb != NULL))
+  {
+    if ((pcb->local_ip.addr == ip.addr) &&
+        (pcb->local_port == udpidx[4]))
+    {
+      bindings++;
+    }
+    pcb = pcb->next;
+  }
+  if (bindings == 1)
+  {
+    /* selectively remove */
+    /* mark nodes for deletion */
+    level = 0;
+    del_cnt = 0;
+    udp_rn = &udp_root;
+    while ((level < 5) && (udp_rn != NULL))
+    {
+      fc = snmp_mib_node_find(udp_rn, udpidx[level], &udp_n);
+      if (fc == 0)
+      {
+        /* udpidx[level] does not exist */
+        del_cnt = 0;
+        udp_rn = NULL;
+      }
+      else if (fc == 1)
+      {
+        del_rn[del_cnt] = udp_rn;
+        del_n[del_cnt] = udp_n;
+        del_cnt++;
+        udp_rn = (struct mib_list_rootnode*)(udp_n->nptr);
+      }
+      else if (fc == 2)
+      {
+        /* reset delete (2 or more childs) */
+        del_cnt = 0;
+        udp_rn = (struct mib_list_rootnode*)(udp_n->nptr);
+      }
+      level++;
+    }
+    /* delete marked index nodes */
+    while (del_cnt > 0)
+    {
+      del_cnt--;
+
+      udp_rn = del_rn[del_cnt];
+      udp_n = del_n[del_cnt];
+
+      next = snmp_mib_node_delete(udp_rn, udp_n);
+      if (next != NULL)
+      {
+        LWIP_ASSERT("next_count == 0",next->count == 0);
+        snmp_mib_lrn_free(next);
+      }
+    }
+  }
+  /* disable getnext traversal on empty table */
+  if (udp_root.count == 0) udptable.maxlength = 0;
+}
+
+
+void snmp_inc_snmpinpkts(void)
+{
+  snmpinpkts++;
+}
+
+void snmp_inc_snmpoutpkts(void)
+{
+  snmpoutpkts++;
+}
+
+void snmp_inc_snmpinbadversions(void)
+{
+  snmpinbadversions++;
+}
+
+void snmp_inc_snmpinbadcommunitynames(void)
+{
+  snmpinbadcommunitynames++;
+}
+
+void snmp_inc_snmpinbadcommunityuses(void)
+{
+  snmpinbadcommunityuses++;
+}
+
+void snmp_inc_snmpinasnparseerrs(void)
+{
+  snmpinasnparseerrs++;
+}
+
+void snmp_inc_snmpintoobigs(void)
+{
+  snmpintoobigs++;
+}
+
+void snmp_inc_snmpinnosuchnames(void)
+{
+  snmpinnosuchnames++;
+}
+
+void snmp_inc_snmpinbadvalues(void)
+{
+  snmpinbadvalues++;
+}
+
+void snmp_inc_snmpinreadonlys(void)
+{
+  snmpinreadonlys++;
+}
+
+void snmp_inc_snmpingenerrs(void)
+{
+  snmpingenerrs++;
+}
+
+void snmp_add_snmpintotalreqvars(u8_t value)
+{
+  snmpintotalreqvars += value;
+}
+
+void snmp_add_snmpintotalsetvars(u8_t value)
+{
+  snmpintotalsetvars += value;
+}
+
+void snmp_inc_snmpingetrequests(void)
+{
+  snmpingetrequests++;
+}
+
+void snmp_inc_snmpingetnexts(void)
+{
+  snmpingetnexts++;
+}
+
+void snmp_inc_snmpinsetrequests(void)
+{
+  snmpinsetrequests++;
+}
+
+void snmp_inc_snmpingetresponses(void)
+{
+  snmpingetresponses++;
+}
+
+void snmp_inc_snmpintraps(void)
+{
+  snmpintraps++;
+}
+
+void snmp_inc_snmpouttoobigs(void)
+{
+  snmpouttoobigs++;
+}
+
+void snmp_inc_snmpoutnosuchnames(void)
+{
+  snmpoutnosuchnames++;
+}
+
+void snmp_inc_snmpoutbadvalues(void)
+{
+  snmpoutbadvalues++;
+}
+
+void snmp_inc_snmpoutgenerrs(void)
+{
+  snmpoutgenerrs++;
+}
+
+void snmp_inc_snmpoutgetrequests(void)
+{
+  snmpoutgetrequests++;
+}
+
+void snmp_inc_snmpoutgetnexts(void)
+{
+  snmpoutgetnexts++;
+}
+
+void snmp_inc_snmpoutsetrequests(void)
+{
+  snmpoutsetrequests++;
+}
+
+void snmp_inc_snmpoutgetresponses(void)
+{
+  snmpoutgetresponses++;
+}
+
+void snmp_inc_snmpouttraps(void)
+{
+  snmpouttraps++;
+}
+
+void snmp_get_snmpgrpid_ptr(struct snmp_obj_id **oid)
+{
+  *oid = &snmpgrp_id;
+}
+
+void snmp_set_snmpenableauthentraps(u8_t *value)
+{
+  if (value != NULL)
+  {
+    snmpenableauthentraps_ptr = value;
+  }
+}
+
+void snmp_get_snmpenableauthentraps(u8_t *value)
+{
+  *value = *snmpenableauthentraps_ptr;
+}
+
+void
+noleafs_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  if (ident_len){}
+  if (ident){}
+  od->instance = MIB_OBJECT_NONE;
+}
+
+void
+noleafs_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  if (od){}
+  if (len){}
+  if (value){}
+}
+
+u8_t
+noleafs_set_test(struct obj_def *od, u16_t len, void *value)
+{
+  if (od){}
+  if (len){}
+  if (value){}
+  /* can't set */
+  return 0;
+}
+
+void
+noleafs_set_value(struct obj_def *od, u16_t len, void *value)
+{
+  if (od){}
+  if (len){}
+  if (value){}
+}
+
+
+/**
+ * Returns systems object definitions.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.0 (object id trailer)
+ * @param od points to object definition.
+ */
+static void
+system_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  u8_t id;
+
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def system.%"U16_F".0\n",(u16_t)id));
+    switch (id)
+    {
+      case 1: /* sysDescr */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = *sysdescr_len_ptr;
+        break;
+      case 2: /* sysObjectID */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID);
+        od->v_len = sysobjid.len * sizeof(s32_t);
+        break;
+      case 3: /* sysUpTime */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 4: /* sysContact */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = *syscontact_len_ptr;
+        break;
+      case 5: /* sysName */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = *sysname_len_ptr;
+        break;
+      case 6: /* sysLocation */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = *syslocation_len_ptr;
+        break;
+      case 7: /* sysServices */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("system_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("system_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+/**
+ * Returns system object value.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.0 (object id trailer)
+ * @param len return value space (in bytes)
+ * @param value points to (varbind) space to copy value into.
+ */
+static void
+system_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* sysDescr */
+      ocstrncpy(value,sysdescr_ptr,len);
+      break;
+    case 2: /* sysObjectID */
+      objectidncpy((s32_t*)value,(s32_t*)sysobjid.id,len / sizeof(s32_t));
+      break;
+    case 3: /* sysUpTime */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = sysuptime;
+      }
+      break;
+    case 4: /* sysContact */
+      ocstrncpy(value,syscontact_ptr,len);
+      break;
+    case 5: /* sysName */
+      ocstrncpy(value,sysname_ptr,len);
+      break;
+    case 6: /* sysLocation */
+      ocstrncpy(value,syslocation_ptr,len);
+      break;
+    case 7: /* sysServices */
+      {
+        s32_t *sint_ptr = value;
+        *sint_ptr = sysservices;
+      }
+      break;
+  };
+}
+
+static u8_t
+system_set_test(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id, set_ok;
+
+  if (value) {}
+  set_ok = 0;
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 4: /* sysContact */
+      if ((syscontact_ptr != syscontact_default) &&
+          (len <= 255))
+      {
+        set_ok = 1;
+      }
+      break;
+    case 5: /* sysName */
+      if ((sysname_ptr != sysname_default) &&
+          (len <= 255))
+      {
+        set_ok = 1;
+      }
+      break;
+    case 6: /* sysLocation */
+      if ((syslocation_ptr != syslocation_default) &&
+          (len <= 255))
+      {
+        set_ok = 1;
+      }
+      break;
+  };
+  return set_ok;
+}
+
+static void
+system_set_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 4: /* sysContact */
+      ocstrncpy(syscontact_ptr,value,len);
+      *syscontact_len_ptr = len;
+      break;
+    case 5: /* sysName */
+      ocstrncpy(sysname_ptr,value,len);
+      *sysname_len_ptr = len;
+      break;
+    case 6: /* sysLocation */
+      ocstrncpy(syslocation_ptr,value,len);
+      *syslocation_len_ptr = len;
+      break;
+  };
+}
+
+/**
+ * Returns interfaces.ifnumber object definition.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.index
+ * @param od points to object definition.
+ */
+static void
+interfaces_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    od->instance = MIB_OBJECT_SCALAR;
+    od->access = MIB_OBJECT_READ_ONLY;
+    od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+    od->v_len = sizeof(s32_t);
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("interfaces_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+/**
+ * Returns interfaces.ifnumber object value.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.0 (object id trailer)
+ * @param len return value space (in bytes)
+ * @param value points to (varbind) space to copy value into.
+ */
+static void
+interfaces_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  if (len){}
+  if (od->id_inst_ptr[0] == 1)
+  {
+    s32_t *sint_ptr = value;
+    *sint_ptr = iflist_root.count;
+  }
+}
+
+/**
+ * Returns ifentry object definitions.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.index
+ * @param od points to object definition.
+ */
+static void
+ifentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  u8_t id;
+
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def ifentry.%"U16_F"\n",(u16_t)id));
+    switch (id)
+    {
+      case 1: /* ifIndex */
+      case 3: /* ifType */
+      case 4: /* ifMtu */
+      case 8: /* ifOperStatus */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 2: /* ifDescr */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        /** @todo this should be some sort of sizeof(struct netif.name) */
+        od->v_len = 2;
+        break;
+      case 5: /* ifSpeed */
+      case 21: /* ifOutQLen */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 6: /* ifPhysAddress */
+        {
+          struct netif *netif;
+
+          snmp_ifindextonetif(ident[1], &netif);
+          od->instance = MIB_OBJECT_TAB;
+          od->access = MIB_OBJECT_READ_ONLY;
+          od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+          od->v_len = netif->hwaddr_len;
+        }
+        break;
+      case 7: /* ifAdminStatus */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 9: /* ifLastChange */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 10: /* ifInOctets */
+      case 11: /* ifInUcastPkts */
+      case 12: /* ifInNUcastPkts */
+      case 13: /* ifInDiscarts */
+      case 14: /* ifInErrors */
+      case 15: /* ifInUnkownProtos */
+      case 16: /* ifOutOctets */
+      case 17: /* ifOutUcastPkts */
+      case 18: /* ifOutNUcastPkts */
+      case 19: /* ifOutDiscarts */
+      case 20: /* ifOutErrors */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 22: /* ifSpecific */
+        /** @note returning zeroDotZero (0.0) no media specific MIB support */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID);
+        od->v_len = ifspecific.len * sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ifentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("ifentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+/**
+ * Returns ifentry object value.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.0 (object id trailer)
+ * @param len return value space (in bytes)
+ * @param value points to (varbind) space to copy value into.
+ */
+static void
+ifentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  struct netif *netif;
+  u8_t id;
+
+  snmp_ifindextonetif(od->id_inst_ptr[1], &netif);
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* ifIndex */
+      {
+        s32_t *sint_ptr = value;
+        *sint_ptr = od->id_inst_ptr[1];
+      }
+      break;
+    case 2: /* ifDescr */
+      ocstrncpy(value,(u8_t*)netif->name,len);
+      break;
+    case 3: /* ifType */
+      {
+        s32_t *sint_ptr = value;
+        *sint_ptr = netif->link_type;
+      }
+      break;
+    case 4: /* ifMtu */
+      {
+        s32_t *sint_ptr = value;
+        *sint_ptr = netif->mtu;
+      }
+      break;
+    case 5: /* ifSpeed */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->link_speed;
+      }
+      break;
+    case 6: /* ifPhysAddress */
+      ocstrncpy(value,netif->hwaddr,len);
+      break;
+    case 7: /* ifAdminStatus */
+    case 8: /* ifOperStatus */
+      {
+        s32_t *sint_ptr = value;
+        if (netif_is_up(netif))
+        {
+          *sint_ptr = 1;
+        }
+        else
+        {
+          *sint_ptr = 2;
+        }
+      }
+      break;
+    case 9: /* ifLastChange */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ts;
+      }
+      break;
+    case 10: /* ifInOctets */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifinoctets;
+      }
+      break;
+    case 11: /* ifInUcastPkts */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifinucastpkts;
+      }
+      break;
+    case 12: /* ifInNUcastPkts */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifinnucastpkts;
+      }
+      break;
+    case 13: /* ifInDiscarts */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifindiscards;
+      }
+      break;
+    case 14: /* ifInErrors */
+    case 15: /* ifInUnkownProtos */
+      /** @todo add these counters! */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = 0;
+      }
+      break;
+    case 16: /* ifOutOctets */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifoutoctets;
+      }
+      break;
+    case 17: /* ifOutUcastPkts */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifoutucastpkts;
+      }
+      break;
+    case 18: /* ifOutNUcastPkts */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifoutnucastpkts;
+      }
+      break;
+    case 19: /* ifOutDiscarts */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifoutdiscards;
+      }
+      break;
+    case 20: /* ifOutErrors */
+       /** @todo add this counter! */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = 0;
+      }
+      break;
+    case 21: /* ifOutQLen */
+      /** @todo figure out if this must be 0 (no queue) or 1? */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = 0;
+      }
+      break;
+    case 22: /* ifSpecific */
+      objectidncpy((s32_t*)value,(s32_t*)ifspecific.id,len / sizeof(s32_t));
+      break;
+  };
+}
+
+/**
+ * Returns atentry object definitions.
+ *
+ * @param ident_len the address length (6)
+ * @param ident points to objectname.atifindex.atnetaddress
+ * @param od points to object definition.
+ */
+static void
+atentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (5) */
+  ident_len += 5;
+  ident -= 5;
+
+  if (ident_len == 6)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    switch (ident[0])
+    {
+      case 1: /* atIfIndex */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 2: /* atPhysAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = sizeof(struct eth_addr);
+        break;
+      case 3: /* atNetAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("atentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    }
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("atentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+atentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+  struct eth_addr* ethaddr_ret;
+  struct ip_addr* ipaddr_ret;
+  struct ip_addr ip;
+  struct netif *netif;
+
+  if (len) {}
+
+  snmp_ifindextonetif(od->id_inst_ptr[1], &netif);
+  snmp_oidtoip(&od->id_inst_ptr[2], &ip);
+  ip.addr = htonl(ip.addr);
+
+  if (etharp_find_addr(netif, &ip, ðaddr_ret, &ipaddr_ret) > -1)
+  {
+    id = od->id_inst_ptr[0];
+    switch (id)
+    {
+      case 1: /* atIfIndex */
+        {
+          s32_t *sint_ptr = value;
+          *sint_ptr = od->id_inst_ptr[1];
+        }
+        break;
+      case 2: /* atPhysAddress */
+        {
+          struct eth_addr *dst = value;
+
+          *dst = *ethaddr_ret;
+        }
+        break;
+      case 3: /* atNetAddress */
+        {
+          struct ip_addr *dst = value;
+
+          *dst = *ipaddr_ret;
+        }
+        break;
+    }
+  }
+}
+
+static void
+ip_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  u8_t id;
+
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def ip.%"U16_F".0\n",(u16_t)id));
+    switch (id)
+    {
+      case 1: /* ipForwarding */
+      case 2: /* ipDefaultTTL */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 3: /* ipInReceives */
+      case 4: /* ipInHdrErrors */
+      case 5: /* ipInAddrErrors */
+      case 6: /* ipForwDatagrams */
+      case 7: /* ipInUnknownProtos */
+      case 8: /* ipInDiscards */
+      case 9: /* ipInDelivers */
+      case 10: /* ipOutRequests */
+      case 11: /* ipOutDiscards */
+      case 12: /* ipOutNoRoutes */
+      case 14: /* ipReasmReqds */
+      case 15: /* ipReasmOKs */
+      case 16: /* ipReasmFails */
+      case 17: /* ipFragOKs */
+      case 18: /* ipFragFails */
+      case 19: /* ipFragCreates */
+      case 23: /* ipRoutingDiscards */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 13: /* ipReasmTimeout */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+ip_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+
+  if (len) {}
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* ipForwarding */
+      {
+        s32_t *sint_ptr = value;
+#if IP_FORWARD
+        /* forwarding */
+        *sint_ptr = 1;
+#else
+        /* not-forwarding */
+        *sint_ptr = 2;
+#endif
+      }
+      break;
+    case 2: /* ipDefaultTTL */
+      {
+        s32_t *sint_ptr = value;
+        *sint_ptr = IP_DEFAULT_TTL;
+      }
+      break;
+    case 3: /* ipInReceives */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipinreceives;
+      }
+      break;
+    case 4: /* ipInHdrErrors */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipinhdrerrors;
+      }
+      break;
+    case 5: /* ipInAddrErrors */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipinaddrerrors;
+      }
+      break;
+    case 6: /* ipForwDatagrams */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipforwdatagrams;
+      }
+      break;
+    case 7: /* ipInUnknownProtos */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipinunknownprotos;
+      }
+      break;
+    case 8: /* ipInDiscards */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipindiscards;
+      }
+      break;
+    case 9: /* ipInDelivers */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipindelivers;
+      }
+      break;
+    case 10: /* ipOutRequests */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipoutrequests;
+      }
+      break;
+    case 11: /* ipOutDiscards */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipoutdiscards;
+      }
+      break;
+    case 12: /* ipOutNoRoutes */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipoutnoroutes;
+      }
+      break;
+    case 13: /* ipReasmTimeout */
+      {
+        s32_t *sint_ptr = value;
+#if IP_REASSEMBLY
+        *sint_ptr = IP_REASS_MAXAGE;
+#else
+        *sint_ptr = 0;
+#endif
+      }
+      break;
+    case 14: /* ipReasmReqds */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipreasmreqds;
+      }
+      break;
+    case 15: /* ipReasmOKs */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipreasmoks;
+      }
+      break;
+    case 16: /* ipReasmFails */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipreasmfails;
+      }
+      break;
+    case 17: /* ipFragOKs */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipfragoks;
+      }
+      break;
+    case 18: /* ipFragFails */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipfragfails;
+      }
+      break;
+    case 19: /* ipFragCreates */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipfragcreates;
+      }
+      break;
+    case 23: /* ipRoutingDiscards */
+      /** @todo can lwIP discard routes at all?? hardwire this to 0?? */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = iproutingdiscards;
+      }
+      break;
+  };
+}
+
+/**
+ * Test ip object value before setting.
+ *
+ * @param od is the object definition
+ * @param len return value space (in bytes)
+ * @param value points to (varbind) space to copy value from.
+ *
+ * @note we allow set if the value matches the hardwired value,
+ *   otherwise return badvalue.
+ */
+static u8_t
+ip_set_test(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id, set_ok;
+  s32_t *sint_ptr = value;
+
+  if (len) {}
+  set_ok = 0;
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* ipForwarding */
+#if IP_FORWARD
+      /* forwarding */
+      if (*sint_ptr == 1)
+#else
+      /* not-forwarding */
+      if (*sint_ptr == 2)
+#endif
+      {
+        set_ok = 1;
+      }
+      break;
+    case 2: /* ipDefaultTTL */
+      if (*sint_ptr == IP_DEFAULT_TTL)
+      {
+        set_ok = 1;
+      }
+      break;
+  };
+  return set_ok;
+}
+
+static void
+ip_addrentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (4) */
+  ident_len += 4;
+  ident -= 4;
+
+  if (ident_len == 5)
+  {
+    u8_t id;
+
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    switch (id)
+    {
+      case 1: /* ipAdEntAddr */
+      case 3: /* ipAdEntNetMask */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      case 2: /* ipAdEntIfIndex */
+      case 4: /* ipAdEntBcastAddr */
+      case 5: /* ipAdEntReasmMaxSize */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_addrentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    }
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_addrentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+ip_addrentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+  u16_t ifidx;
+  struct ip_addr ip;
+  struct netif *netif = netif_list;
+
+  if (len) {}
+  snmp_oidtoip(&od->id_inst_ptr[1], &ip);
+  ip.addr = htonl(ip.addr);
+  ifidx = 0;
+  while ((netif != NULL) && !ip_addr_cmp(&ip, &netif->ip_addr))
+  {
+    netif = netif->next;
+    ifidx++;
+  }
+
+  if (netif != NULL)
+  {
+    id = od->id_inst_ptr[0];
+    switch (id)
+    {
+      case 1: /* ipAdEntAddr */
+        {
+          struct ip_addr *dst = value;
+          *dst = netif->ip_addr;
+        }
+        break;
+      case 2: /* ipAdEntIfIndex */
+        {
+          s32_t *sint_ptr = value;
+          *sint_ptr = ifidx + 1;
+        }
+        break;
+      case 3: /* ipAdEntNetMask */
+        {
+          struct ip_addr *dst = value;
+          *dst = netif->netmask;
+        }
+        break;
+      case 4: /* ipAdEntBcastAddr */
+        {
+          s32_t *sint_ptr = value;
+
+          /* lwIP oddity, there's no broadcast
+            address in the netif we can rely on */
+          *sint_ptr = ip_addr_broadcast.addr & 1;
+        }
+        break;
+      case 5: /* ipAdEntReasmMaxSize */
+        {
+          s32_t *sint_ptr = value;
+#if IP_REASSEMBLY
+          *sint_ptr = (IP_HLEN + IP_REASS_BUFSIZE);
+#else
+          /** @todo returning MTU would be a bad thing and
+             returning a wild guess like '576' isn't good either */
+          *sint_ptr = 0;
+#endif
+        }
+        break;
+    }
+  }
+}
+
+/**
+ * @note
+ * lwIP IP routing is currently using the network addresses in netif_list.
+ * if no suitable network IP is found in netif_list, the default_netif is used.
+ */
+static void
+ip_rteentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  u8_t id;
+
+  /* return to object name, adding index depth (4) */
+  ident_len += 4;
+  ident -= 4;
+
+  if (ident_len == 5)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    switch (id)
+    {
+      case 1: /* ipRouteDest */
+      case 7: /* ipRouteNextHop */
+      case 11: /* ipRouteMask */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      case 2: /* ipRouteIfIndex */
+      case 3: /* ipRouteMetric1 */
+      case 4: /* ipRouteMetric2 */
+      case 5: /* ipRouteMetric3 */
+      case 6: /* ipRouteMetric4 */
+      case 8: /* ipRouteType */
+      case 10: /* ipRouteAge */
+      case 12: /* ipRouteMetric5 */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 9: /* ipRouteProto */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 13: /* ipRouteInfo */
+        /** @note returning zeroDotZero (0.0) no routing protocol specific MIB */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID);
+        od->v_len = iprouteinfo.len * sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_rteentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    }
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_rteentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+ip_rteentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  struct netif *netif;
+  struct ip_addr dest;
+  s32_t *ident;
+  u8_t id;
+
+  ident = od->id_inst_ptr;
+  snmp_oidtoip(&ident[1], &dest);
+  dest.addr = htonl(dest.addr);
+
+  if (dest.addr == 0)
+  {
+    /* ip_route() uses default netif for default route */
+    netif = netif_default;
+  }
+  else
+  {
+    /* not using ip_route(), need exact match! */
+    netif = netif_list;
+    while ((netif != NULL) &&
+            !ip_addr_netcmp(&dest, &(netif->ip_addr), &(netif->netmask)) )
+    {
+      netif = netif->next;
+    }
+  }
+  if (netif != NULL)
+  {
+    id = ident[0];
+    switch (id)
+    {
+      case 1: /* ipRouteDest */
+        {
+          struct ip_addr *dst = value;
+
+          if (dest.addr == 0)
+          {
+            /* default rte has 0.0.0.0 dest */
+            dst->addr = 0;
+          }
+          else
+          {
+            /* netifs have netaddress dest */
+            dst->addr = netif->ip_addr.addr & netif->netmask.addr;
+          }
+        }
+        break;
+      case 2: /* ipRouteIfIndex */
+        {
+          s32_t *sint_ptr = value;
+
+          snmp_netiftoifindex(netif, sint_ptr);
+        }
+        break;
+      case 3: /* ipRouteMetric1 */
+        {
+          s32_t *sint_ptr = value;
+
+          if (dest.addr == 0)
+          {
+            /* default rte has metric 1 */
+            *sint_ptr = 1;
+          }
+          else
+          {
+            /* other rtes have metric 0 */
+            *sint_ptr = 0;
+          }
+        }
+        break;
+      case 4: /* ipRouteMetric2 */
+      case 5: /* ipRouteMetric3 */
+      case 6: /* ipRouteMetric4 */
+      case 12: /* ipRouteMetric5 */
+        {
+          s32_t *sint_ptr = value;
+          /* not used */
+          *sint_ptr = -1;
+        }
+        break;
+      case 7: /* ipRouteNextHop */
+        {
+          struct ip_addr *dst = value;
+
+          if (dest.addr == 0)
+          {
+            /* default rte: gateway */
+            *dst = netif->gw;
+          }
+          else
+          {
+            /* other rtes: netif ip_addr  */
+            *dst = netif->ip_addr;
+          }
+        }
+        break;
+      case 8: /* ipRouteType */
+        {
+          s32_t *sint_ptr = value;
+
+          if (dest.addr == 0)
+          {
+            /* default rte is indirect */
+            *sint_ptr = 4;
+          }
+          else
+          {
+            /* other rtes are direct */
+            *sint_ptr = 3;
+          }
+        }
+        break;
+      case 9: /* ipRouteProto */
+        {
+          s32_t *sint_ptr = value;
+          /* locally defined routes */
+          *sint_ptr = 2;
+        }
+        break;
+      case 10: /* ipRouteAge */
+        {
+          s32_t *sint_ptr = value;
+          /** @todo (sysuptime - timestamp last change) / 100
+              @see snmp_insert_iprteidx_tree() */
+          *sint_ptr = 0;
+        }
+        break;
+      case 11: /* ipRouteMask */
+        {
+          struct ip_addr *dst = value;
+
+          if (dest.addr == 0)
+          {
+            /* default rte use 0.0.0.0 mask */
+            dst->addr = 0;
+          }
+          else
+          {
+            /* other rtes use netmask */
+            *dst = netif->netmask;
+          }
+        }
+        break;
+      case 13: /* ipRouteInfo */
+        objectidncpy((s32_t*)value,(s32_t*)iprouteinfo.id,len / sizeof(s32_t));
+        break;
+    }
+  }
+}
+
+static void
+ip_ntomentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (5) */
+  ident_len += 5;
+  ident -= 5;
+
+  if (ident_len == 6)
+  {
+    u8_t id;
+
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    switch (id)
+    {
+      case 1: /* ipNetToMediaIfIndex */
+      case 4: /* ipNetToMediaType */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 2: /* ipNetToMediaPhysAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = sizeof(struct eth_addr);
+        break;
+      case 3: /* ipNetToMediaNetAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_ntomentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    }
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_ntomentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+ip_ntomentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+  struct eth_addr* ethaddr_ret;
+  struct ip_addr* ipaddr_ret;
+  struct ip_addr ip;
+  struct netif *netif;
+
+  if (len) {}
+
+  snmp_ifindextonetif(od->id_inst_ptr[1], &netif);
+  snmp_oidtoip(&od->id_inst_ptr[2], &ip);
+  ip.addr = htonl(ip.addr);
+
+  if (etharp_find_addr(netif, &ip, ðaddr_ret, &ipaddr_ret) > -1)
+  {
+    id = od->id_inst_ptr[0];
+    switch (id)
+    {
+      case 1: /* ipNetToMediaIfIndex */
+        {
+          s32_t *sint_ptr = value;
+          *sint_ptr = od->id_inst_ptr[1];
+        }
+        break;
+      case 2: /* ipNetToMediaPhysAddress */
+        {
+          struct eth_addr *dst = value;
+
+          *dst = *ethaddr_ret;
+        }
+        break;
+      case 3: /* ipNetToMediaNetAddress */
+        {
+          struct ip_addr *dst = value;
+
+          *dst = *ipaddr_ret;
+        }
+        break;
+      case 4: /* ipNetToMediaType */
+        {
+          s32_t *sint_ptr = value;
+          /* dynamic (?) */
+          *sint_ptr = 3;
+        }
+        break;
+    }
+  }
+}
+
+static void
+icmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if ((ident_len == 2) &&
+      (ident[0] > 0) && (ident[0] < 27))
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    od->instance = MIB_OBJECT_SCALAR;
+    od->access = MIB_OBJECT_READ_ONLY;
+    od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+    od->v_len = sizeof(u32_t);
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("icmp_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+icmp_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u32_t *uint_ptr = value;
+  u8_t id;
+
+  if (len){}
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* icmpInMsgs */
+      *uint_ptr = icmpinmsgs;
+      break;
+    case 2: /* icmpInErrors */
+      *uint_ptr = icmpinerrors;
+      break;
+    case 3: /* icmpInDestUnreachs */
+      *uint_ptr = icmpindestunreachs;
+      break;
+    case 4: /* icmpInTimeExcds */
+      *uint_ptr = icmpintimeexcds;
+      break;
+    case 5: /* icmpInParmProbs */
+      *uint_ptr = icmpinparmprobs;
+      break;
+    case 6: /* icmpInSrcQuenchs */
+      *uint_ptr = icmpinsrcquenchs;
+      break;
+    case 7: /* icmpInRedirects */
+      *uint_ptr = icmpinredirects;
+      break;
+    case 8: /* icmpInEchos */
+      *uint_ptr = icmpinechos;
+      break;
+    case 9: /* icmpInEchoReps */
+      *uint_ptr = icmpinechoreps;
+      break;
+    case 10: /* icmpInTimestamps */
+      *uint_ptr = icmpintimestamps;
+      break;
+    case 11: /* icmpInTimestampReps */
+      *uint_ptr = icmpintimestampreps;
+      break;
+    case 12: /* icmpInAddrMasks */
+      *uint_ptr = icmpinaddrmasks;
+      break;
+    case 13: /* icmpInAddrMaskReps */
+      *uint_ptr = icmpinaddrmaskreps;
+      break;
+    case 14: /* icmpOutMsgs */
+      *uint_ptr = icmpoutmsgs;
+      break;
+    case 15: /* icmpOutErrors */
+      *uint_ptr = icmpouterrors;
+      break;
+    case 16: /* icmpOutDestUnreachs */
+      *uint_ptr = icmpoutdestunreachs;
+      break;
+    case 17: /* icmpOutTimeExcds */
+      *uint_ptr = icmpouttimeexcds;
+      break;
+    case 18: /* icmpOutParmProbs */
+      *uint_ptr = icmpoutparmprobs;
+      break;
+    case 19: /* icmpOutSrcQuenchs */
+      *uint_ptr = icmpoutsrcquenchs;
+      break;
+    case 20: /* icmpOutRedirects */
+      *uint_ptr = icmpoutredirects;
+      break;
+    case 21: /* icmpOutEchos */
+      *uint_ptr = icmpoutechos;
+      break;
+    case 22: /* icmpOutEchoReps */
+      *uint_ptr = icmpoutechoreps;
+      break;
+    case 23: /* icmpOutTimestamps */
+      *uint_ptr = icmpouttimestamps;
+      break;
+    case 24: /* icmpOutTimestampReps */
+      *uint_ptr = icmpouttimestampreps;
+      break;
+    case 25: /* icmpOutAddrMasks */
+      *uint_ptr = icmpoutaddrmasks;
+      break;
+    case 26: /* icmpOutAddrMaskReps */
+      *uint_ptr = icmpoutaddrmaskreps;
+      break;
+  }
+}
+
+#if LWIP_TCP
+/** @todo tcp grp */
+static void
+tcp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  u8_t id;
+
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def tcp.%"U16_F".0\n",(u16_t)id));
+
+    switch (id)
+    {
+      case 1: /* tcpRtoAlgorithm */
+      case 2: /* tcpRtoMin */
+      case 3: /* tcpRtoMax */
+      case 4: /* tcpMaxConn */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 5: /* tcpActiveOpens */
+      case 6: /* tcpPassiveOpens */
+      case 7: /* tcpAttemptFails */
+      case 8: /* tcpEstabResets */
+      case 10: /* tcpInSegs */
+      case 11: /* tcpOutSegs */
+      case 12: /* tcpRetransSegs */
+      case 14: /* tcpInErrs */
+      case 15: /* tcpOutRsts */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 9: /* tcpCurrEstab */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE);
+        od->v_len = sizeof(u32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcp_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcp_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+tcp_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u32_t *uint_ptr = value;
+  s32_t *sint_ptr = value;
+  u8_t id;
+
+  if (len){}
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* tcpRtoAlgorithm, vanj(4) */
+      *sint_ptr = 4;
+      break;
+    case 2: /* tcpRtoMin */
+      /* @todo not the actual value, a guess,
+          needs to be calculated */
+      *sint_ptr = 1000;
+      break;
+    case 3: /* tcpRtoMax */
+      /* @todo not the actual value, a guess,
+         needs to be calculated */
+      *sint_ptr = 60000;
+      break;
+    case 4: /* tcpMaxConn */
+      *sint_ptr = MEMP_NUM_TCP_PCB;
+      break;
+    case 5: /* tcpActiveOpens */
+      *uint_ptr = tcpactiveopens;
+      break;
+    case 6: /* tcpPassiveOpens */
+      *uint_ptr = tcppassiveopens;
+      break;
+    case 7: /* tcpAttemptFails */
+      *uint_ptr = tcpattemptfails;
+      break;
+    case 8: /* tcpEstabResets */
+      *uint_ptr = tcpestabresets;
+      break;
+    case 9: /* tcpCurrEstab */
+      {
+        u16_t tcpcurrestab = 0;
+        struct tcp_pcb *pcb = tcp_active_pcbs;
+        while (pcb != NULL)
+        {
+          if ((pcb->state == ESTABLISHED) ||
+              (pcb->state == CLOSE_WAIT))
+          {
+            tcpcurrestab++;
+          }
+          pcb = pcb->next;
+        }
+        *uint_ptr = tcpcurrestab;
+      }
+      break;
+    case 10: /* tcpInSegs */
+      *uint_ptr = tcpinsegs;
+      break;
+    case 11: /* tcpOutSegs */
+      *uint_ptr = tcpoutsegs;
+      break;
+    case 12: /* tcpRetransSegs */
+      *uint_ptr = tcpretranssegs;
+      break;
+    case 14: /* tcpInErrs */
+      *uint_ptr = tcpinerrs;
+      break;
+    case 15: /* tcpOutRsts */
+      *uint_ptr = tcpoutrsts;
+      break;
+  }
+}
+
+static void
+tcpconnentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (10) */
+  ident_len += 10;
+  ident -= 10;
+
+  if (ident_len == 11)
+  {
+    u8_t id;
+
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def tcp.%"U16_F".0\n",(u16_t)id));
+
+    switch (id)
+    {
+      case 1: /* tcpConnState */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 2: /* tcpConnLocalAddress */
+      case 4: /* tcpConnRemAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      case 3: /* tcpConnLocalPort */
+      case 5: /* tcpConnRemPort */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcpconnentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcpconnentry_get_object_def: no such object\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+tcpconnentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  struct ip_addr lip, rip;
+  u16_t lport, rport;
+  s32_t *ident;
+
+  ident = od->id_inst_ptr;
+  snmp_oidtoip(&ident[1], &lip);
+  lip.addr = htonl(lip.addr);
+  lport = ident[5];
+  snmp_oidtoip(&ident[6], &rip);
+  rip.addr = htonl(rip.addr);
+  rport = ident[10];
+
+  /** @todo find matching PCB */
+}
+#endif
+
+static void
+udp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if ((ident_len == 2) &&
+      (ident[0] > 0) && (ident[0] < 6))
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    od->instance = MIB_OBJECT_SCALAR;
+    od->access = MIB_OBJECT_READ_ONLY;
+    od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+    od->v_len = sizeof(u32_t);
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("udp_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+udp_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u32_t *uint_ptr = value;
+  u8_t id;
+
+  if (len){}
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* udpInDatagrams */
+      *uint_ptr = udpindatagrams;
+      break;
+    case 2: /* udpNoPorts */
+      *uint_ptr = udpnoports;
+      break;
+    case 3: /* udpInErrors */
+      *uint_ptr = udpinerrors;
+      break;
+    case 4: /* udpOutDatagrams */
+      *uint_ptr = udpoutdatagrams;
+      break;
+  }
+}
+
+static void
+udpentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (5) */
+  ident_len += 5;
+  ident -= 5;
+
+  if (ident_len == 6)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    switch (ident[0])
+    {
+      case 1: /* udpLocalAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      case 2: /* udpLocalPort */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("udpentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    }
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("udpentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+udpentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+  struct udp_pcb *pcb;
+  struct ip_addr ip;
+  u16_t port;
+
+  if (len){}
+  snmp_oidtoip(&od->id_inst_ptr[1], &ip);
+  ip.addr = htonl(ip.addr);
+  port = od->id_inst_ptr[5];
+
+  pcb = udp_pcbs;
+  while ((pcb != NULL) &&
+         !((pcb->local_ip.addr == ip.addr) &&
+           (pcb->local_port == port)))
+  {
+    pcb = pcb->next;
+  }
+
+  if (pcb != NULL)
+  {
+    id = od->id_inst_ptr[0];
+    switch (id)
+    {
+      case 1: /* udpLocalAddress */
+        {
+          struct ip_addr *dst = value;
+          *dst = pcb->local_ip;
+        }
+        break;
+      case 2: /* udpLocalPort */
+        {
+          s32_t *sint_ptr = value;
+          *sint_ptr = pcb->local_port;
+        }
+        break;
+    }
+  }
+}
+
+static void
+snmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    u8_t id;
+
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    switch (id)
+    {
+      case 1: /* snmpInPkts */
+      case 2: /* snmpOutPkts */
+      case 3: /* snmpInBadVersions */
+      case 4: /* snmpInBadCommunityNames */
+      case 5: /* snmpInBadCommunityUses */
+      case 6: /* snmpInASNParseErrs */
+      case 8: /* snmpInTooBigs */
+      case 9: /* snmpInNoSuchNames */
+      case 10: /* snmpInBadValues */
+      case 11: /* snmpInReadOnlys */
+      case 12: /* snmpInGenErrs */
+      case 13: /* snmpInTotalReqVars */
+      case 14: /* snmpInTotalSetVars */
+      case 15: /* snmpInGetRequests */
+      case 16: /* snmpInGetNexts */
+      case 17: /* snmpInSetRequests */
+      case 18: /* snmpInGetResponses */
+      case 19: /* snmpInTraps */
+      case 20: /* snmpOutTooBigs */
+      case 21: /* snmpOutNoSuchNames */
+      case 22: /* snmpOutBadValues */
+      case 24: /* snmpOutGenErrs */
+      case 25: /* snmpOutGetRequests */
+      case 26: /* snmpOutGetNexts */
+      case 27: /* snmpOutSetRequests */
+      case 28: /* snmpOutGetResponses */
+      case 29: /* snmpOutTraps */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 30: /* snmpEnableAuthenTraps */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+snmp_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u32_t *uint_ptr = value;
+  u8_t id;
+
+  if (len){}
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+      case 1: /* snmpInPkts */
+        *uint_ptr = snmpinpkts;
+        break;
+      case 2: /* snmpOutPkts */
+        *uint_ptr = snmpoutpkts;
+        break;
+      case 3: /* snmpInBadVersions */
+        *uint_ptr = snmpinbadversions;
+        break;
+      case 4: /* snmpInBadCommunityNames */
+        *uint_ptr = snmpinbadcommunitynames;
+        break;
+      case 5: /* snmpInBadCommunityUses */
+        *uint_ptr = snmpinbadcommunityuses;
+        break;
+      case 6: /* snmpInASNParseErrs */
+        *uint_ptr = snmpinasnparseerrs;
+        break;
+      case 8: /* snmpInTooBigs */
+        *uint_ptr = snmpintoobigs;
+        break;
+      case 9: /* snmpInNoSuchNames */
+        *uint_ptr = snmpinnosuchnames;
+        break;
+      case 10: /* snmpInBadValues */
+        *uint_ptr = snmpinbadvalues;
+        break;
+      case 11: /* snmpInReadOnlys */
+        *uint_ptr = snmpinreadonlys;
+        break;
+      case 12: /* snmpInGenErrs */
+        *uint_ptr = snmpingenerrs;
+        break;
+      case 13: /* snmpInTotalReqVars */
+        *uint_ptr = snmpintotalreqvars;
+        break;
+      case 14: /* snmpInTotalSetVars */
+        *uint_ptr = snmpintotalsetvars;
+        break;
+      case 15: /* snmpInGetRequests */
+        *uint_ptr = snmpingetrequests;
+        break;
+      case 16: /* snmpInGetNexts */
+        *uint_ptr = snmpingetnexts;
+        break;
+      case 17: /* snmpInSetRequests */
+        *uint_ptr = snmpinsetrequests;
+        break;
+      case 18: /* snmpInGetResponses */
+        *uint_ptr = snmpingetresponses;
+        break;
+      case 19: /* snmpInTraps */
+        *uint_ptr = snmpintraps;
+        break;
+      case 20: /* snmpOutTooBigs */
+        *uint_ptr = snmpouttoobigs;
+        break;
+      case 21: /* snmpOutNoSuchNames */
+        *uint_ptr = snmpoutnosuchnames;
+        break;
+      case 22: /* snmpOutBadValues */
+        *uint_ptr = snmpoutbadvalues;
+        break;
+      case 24: /* snmpOutGenErrs */
+        *uint_ptr = snmpoutgenerrs;
+        break;
+      case 25: /* snmpOutGetRequests */
+        *uint_ptr = snmpoutgetrequests;
+        break;
+      case 26: /* snmpOutGetNexts */
+        *uint_ptr = snmpoutgetnexts;
+        break;
+      case 27: /* snmpOutSetRequests */
+        *uint_ptr = snmpoutsetrequests;
+        break;
+      case 28: /* snmpOutGetResponses */
+        *uint_ptr = snmpoutgetresponses;
+        break;
+      case 29: /* snmpOutTraps */
+        *uint_ptr = snmpouttraps;
+        break;
+      case 30: /* snmpEnableAuthenTraps */
+        *uint_ptr = *snmpenableauthentraps_ptr;
+        break;
+  };
+}
+
+/**
+ * Test snmp object value before setting.
+ *
+ * @param od is the object definition
+ * @param len return value space (in bytes)
+ * @param value points to (varbind) space to copy value from.
+ */
+static u8_t
+snmp_set_test(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id, set_ok;
+
+  if (len) {}
+  set_ok = 0;
+  id = od->id_inst_ptr[0];
+  if (id == 30)
+  {
+    /* snmpEnableAuthenTraps */
+    s32_t *sint_ptr = value;
+
+    if (snmpenableauthentraps_ptr != &snmpenableauthentraps_default)
+    {
+      /* we should have writable non-volatile mem here */
+      if ((*sint_ptr == 1) || (*sint_ptr == 2))
+      {
+        set_ok = 1;
+      }
+    }
+    else
+    {
+      /* const or hardwired value */
+      if (*sint_ptr == snmpenableauthentraps_default)
+      {
+        set_ok = 1;
+      }
+    }
+  }
+  return set_ok;
+}
+
+static void
+snmp_set_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+
+  if (len) {}
+  id = od->id_inst_ptr[0];
+  if (id == 30)
+  {
+    /* snmpEnableAuthenTraps */
+    s32_t *sint_ptr = value;
+    *snmpenableauthentraps_ptr = *sint_ptr;
+  }
+}
+
+#endif /* LWIP_SNMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/snmp/mib_structs.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/snmp/mib_structs.c
new file mode 100644
index 0000000..1fad588
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/snmp/mib_structs.c
@@ -0,0 +1,1185 @@
+/**
+ * @file
+ * MIB tree access/construction functions.
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP
+#include "lwip/snmp_structs.h"
+#include "lwip/mem.h"
+
+
+
+/** .iso.org.dod.internet address prefix, @see snmp_iso_*() */
+const s32_t prefix[4] = {1, 3, 6, 1};
+
+#define NODE_STACK_SIZE (LWIP_SNMP_OBJ_ID_LEN)
+/** node stack entry (old news?) */
+struct nse
+{
+  /** right child */
+  struct mib_node* r_ptr;
+  /** right child identifier */
+  s32_t r_id;
+  /** right child next level */
+  u8_t r_nl;
+};
+static u8_t node_stack_cnt = 0;
+static struct nse node_stack[NODE_STACK_SIZE];
+
+/**
+ * Pushes nse struct onto stack.
+ */
+static void
+push_node(struct nse* node)
+{
+  LWIP_ASSERT("node_stack_cnt < NODE_STACK_SIZE",node_stack_cnt < NODE_STACK_SIZE);
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("push_node() node=%p id=%"S32_F"\n",(void*)(node->r_ptr),node->r_id));
+  if (node_stack_cnt < NODE_STACK_SIZE)
+  {
+    node_stack[node_stack_cnt] = *node;
+    node_stack_cnt++;
+  }
+}
+
+/**
+ * Pops nse struct from stack.
+ */
+static void
+pop_node(struct nse* node)
+{
+  if (node_stack_cnt > 0)
+  {
+    node_stack_cnt--;
+    *node = node_stack[node_stack_cnt];
+  }
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("pop_node() node=%p id=%"S32_F"\n",(void *)(node->r_ptr),node->r_id));
+}
+
+/**
+ * Conversion from ifIndex to lwIP netif
+ * @param ifindex is a s32_t object sub-identifier
+ * @param netif points to returned netif struct pointer
+ */
+void
+snmp_ifindextonetif(s32_t ifindex, struct netif **netif)
+{
+  struct netif *nif = netif_list;
+  u16_t i, ifidx;
+
+  ifidx = ifindex - 1;
+  i = 0;
+  while ((nif != NULL) && (i < ifidx))
+  {
+    nif = nif->next;
+    i++;
+  }
+  *netif = nif;
+}
+
+/**
+ * Conversion from lwIP netif to ifIndex
+ * @param netif points to a netif struct
+ * @param ifindex points to s32_t object sub-identifier
+ */
+void
+snmp_netiftoifindex(struct netif *netif, s32_t *ifidx)
+{
+  struct netif *nif = netif_list;
+  u16_t i;
+
+  i = 0;
+  while (nif != netif)
+  {
+    nif = nif->next;
+    i++;
+  }
+  *ifidx = i+1;
+}
+
+/**
+ * Conversion from oid to lwIP ip_addr
+ * @param ident points to s32_t ident[4] input
+ * @param ip points to output struct
+ */
+void
+snmp_oidtoip(s32_t *ident, struct ip_addr *ip)
+{
+  u32_t ipa;
+
+  ipa = ident[0];
+  ipa <<= 8;
+  ipa |= ident[1];
+  ipa <<= 8;
+  ipa |= ident[2];
+  ipa <<= 8;
+  ipa |= ident[3];
+  ip->addr = ipa;
+}
+
+/**
+ * Conversion from lwIP ip_addr to oid
+ * @param ip points to input struct
+ * @param ident points to s32_t ident[4] output
+ */
+void
+snmp_iptooid(struct ip_addr *ip, s32_t *ident)
+{
+  u32_t ipa;
+
+  ipa = ip->addr;
+  ident[0] = (ipa >> 24) & 0xff;
+  ident[1] = (ipa >> 16) & 0xff;
+  ident[2] = (ipa >> 8) & 0xff;
+  ident[3] = ipa & 0xff;
+}
+
+struct mib_list_node *
+snmp_mib_ln_alloc(s32_t id)
+{
+  struct mib_list_node *ln;
+
+  ln = (struct mib_list_node *)mem_malloc(sizeof(struct mib_list_node));
+  if (ln != NULL)
+  {
+    ln->prev = NULL;
+    ln->next = NULL;
+    ln->objid = id;
+    ln->nptr = NULL;
+  }
+  return ln;
+}
+
+void
+snmp_mib_ln_free(struct mib_list_node *ln)
+{
+  mem_free(ln);
+}
+
+struct mib_list_rootnode *
+snmp_mib_lrn_alloc(void)
+{
+  struct mib_list_rootnode *lrn;
+
+  lrn = (struct mib_list_rootnode*)mem_malloc(sizeof(struct mib_list_rootnode));
+  if (lrn != NULL)
+  {
+    lrn->get_object_def = noleafs_get_object_def;
+    lrn->get_value = noleafs_get_value;
+    lrn->set_test = noleafs_set_test;
+    lrn->set_value = noleafs_set_value;
+    lrn->node_type = MIB_NODE_LR;
+    lrn->maxlength = 0;
+    lrn->head = NULL;
+    lrn->tail = NULL;
+    lrn->count = 0;
+  }
+  return lrn;
+}
+
+void
+snmp_mib_lrn_free(struct mib_list_rootnode *lrn)
+{
+  mem_free(lrn);
+}
+
+/**
+ * Inserts node in idx list in a sorted
+ * (ascending order) fashion and
+ * allocates the node if needed.
+ *
+ * @param rn points to the root node
+ * @param objid is the object sub identifier
+ * @param insn points to a pointer to the inserted node
+ *   used for constructing the tree.
+ * @return -1 if failed, 1 if inserted, 2 if present.
+ */
+s8_t
+snmp_mib_node_insert(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **insn)
+{
+  struct mib_list_node *nn;
+  s8_t insert;
+
+  LWIP_ASSERT("rn != NULL",rn != NULL);
+
+  /* -1 = malloc failure, 0 = not inserted, 1 = inserted, 2 = was present */
+  insert = 0;
+  if (rn->head == NULL)
+  {
+    /* empty list, add first node */
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc empty list objid==%"S32_F"\n",objid));
+    nn = snmp_mib_ln_alloc(objid);
+    if (nn != NULL)
+    {
+      rn->head = nn;
+      rn->tail = nn;
+      *insn = nn;
+      insert = 1;
+    }
+    else
+    {
+      insert = -1;
+    }
+  }
+  else
+  {
+    struct mib_list_node *n;
+    /* at least one node is present */
+    n = rn->head;
+    while ((n != NULL) && (insert == 0))
+    {
+      if (n->objid == objid)
+      {
+        /* node is already there */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("node already there objid==%"S32_F"\n",objid));
+        *insn = n;
+        insert = 2;
+      }
+      else if (n->objid < objid)
+      {
+        if (n->next == NULL)
+        {
+          /* alloc and insert at the tail */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc ins tail objid==%"S32_F"\n",objid));
+          nn = snmp_mib_ln_alloc(objid);
+          if (nn != NULL)
+          {
+            nn->next = NULL;
+            nn->prev = n;
+            n->next = nn;
+            rn->tail = nn;
+            *insn = nn;
+            insert = 1;
+          }
+          else
+          {
+            /* insertion failure */
+            insert = -1;
+          }
+        }
+        else
+        {
+          /* there's more to explore: traverse list */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("traverse list\n"));
+          n = n->next;
+        }
+      }
+      else
+      {
+        /* n->objid > objid */
+        /* alloc and insert between n->prev and n */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc ins n->prev, objid==%"S32_F", n\n",objid));
+        nn = snmp_mib_ln_alloc(objid);
+        if (nn != NULL)
+        {
+          if (n->prev == NULL)
+          {
+            /* insert at the head */
+            nn->next = n;
+            nn->prev = NULL;
+            rn->head = nn;
+            n->prev = nn;
+          }
+          else
+          {
+            /* insert in the middle */
+            nn->next = n;
+            nn->prev = n->prev;
+            n->prev->next = nn;
+            n->prev = nn;
+          }
+          *insn = nn;
+          insert = 1;
+        }
+        else
+        {
+          /* insertion failure */
+          insert = -1;
+        }
+      }
+    }
+  }
+  if (insert == 1)
+  {
+    rn->count += 1;
+  }
+  LWIP_ASSERT("insert != 0",insert != 0);
+  return insert;
+}
+
+/**
+ * Finds node in idx list and returns deletion mark.
+ *
+ * @param rn points to the root node
+ * @param objid  is the object sub identifier
+ * @param fn returns pointer to found node
+ * @return 0 if not found, 1 if deletable,
+ *   2 can't delete (2 or more children), 3 not a list_node
+ */
+s8_t
+snmp_mib_node_find(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **fn)
+{
+  s8_t fc;
+  struct mib_list_node *n;
+
+  LWIP_ASSERT("rn != NULL",rn != NULL);
+  n = rn->head;
+  while ((n != NULL) && (n->objid != objid))
+  {
+    n = n->next;
+  }
+  if (n == NULL)
+  {
+    fc = 0;
+  }
+  else if (n->nptr == NULL)
+  {
+    /* leaf, can delete node */
+    fc = 1;
+  }
+  else
+  {
+    struct mib_list_rootnode *rn;
+
+    if (n->nptr->node_type == MIB_NODE_LR)
+    {
+      rn = (struct mib_list_rootnode *)n->nptr;
+      if (rn->count > 1)
+      {
+        /* can't delete node */
+        fc = 2;
+      }
+      else
+      {
+        /* count <= 1, can delete node */
+        fc = 1;
+      }
+    }
+    else
+    {
+      /* other node type */
+      fc = 3;
+    }
+  }
+  *fn = n;
+  return fc;
+}
+
+/**
+ * Removes node from idx list
+ * if it has a single child left.
+ *
+ * @param rn points to the root node
+ * @param n points to the node to delete
+ * @return the nptr to be freed by caller
+ */
+struct mib_list_rootnode *
+snmp_mib_node_delete(struct mib_list_rootnode *rn, struct mib_list_node *n)
+{
+  struct mib_list_rootnode *next;
+
+  LWIP_ASSERT("rn != NULL",rn != NULL);
+  LWIP_ASSERT("n != NULL",n != NULL);
+
+  /* caller must remove this sub-tree */
+  next = (struct mib_list_rootnode*)(n->nptr);
+  rn->count -= 1;
+
+  if (n == rn->head)
+  {
+    rn->head = n->next;
+    if (n->next != NULL)
+    {
+      /* not last node, new list begin */
+      n->next->prev = NULL;
+    }
+  }
+  else if (n == rn->tail)
+  {
+    rn->tail = n->prev;
+    if (n->prev != NULL)
+    {
+      /* not last node, new list end */
+      n->prev->next = NULL;
+    }
+  }
+  else
+  {
+    /* node must be in the middle */
+    n->prev->next = n->next;
+    n->next->prev = n->prev;
+  }
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("free list objid==%"S32_F"\n",n->objid));
+  snmp_mib_ln_free(n);
+  if (rn->count == 0)
+  {
+    rn->head = NULL;
+    rn->tail = NULL;
+  }
+  return next;
+}
+
+
+
+/**
+ * Searches tree for the supplied (scalar?) object identifier.
+ *
+ * @param node points to the root of the tree ('.internet')
+ * @param ident_len the length of the supplied object identifier
+ * @param ident points to the array of sub identifiers
+ * @param np points to the found object instance (rerurn)
+ * @return pointer to the requested parent (!) node if success, NULL otherwise
+ */
+struct mib_node *
+snmp_search_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_name_ptr *np)
+{
+  u8_t node_type, ext_level;
+
+  ext_level = 0;
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("node==%p *ident==%"S32_F"\n",(void*)node,*ident));
+  while (node != NULL)
+  {
+    node_type = node->node_type;
+    if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA))
+    {
+      struct mib_array_node *an;
+      u16_t i;
+
+      if (ident_len > 0)
+      {
+        /* array node (internal ROM or RAM, fixed length) */
+        an = (struct mib_array_node *)node;
+        i = 0;
+        while ((i < an->maxlength) && (an->objid[i] != *ident))
+        {
+          i++;
+        }
+        if (i < an->maxlength)
+        {
+          /* found it, if available proceed to child, otherwise inspect leaf */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("an->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,an->objid[i],*ident));
+          if (an->nptr[i] == NULL)
+          {
+            /* a scalar leaf OR table,
+               inspect remaining instance number / table index */
+            np->ident_len = ident_len;
+            np->ident = ident;
+            return (struct mib_node*)an;
+          }
+          else
+          {
+            /* follow next child pointer */
+            ident++;
+            ident_len--;
+            node = an->nptr[i];
+          }
+        }
+        else
+        {
+          /* search failed, identifier mismatch (nosuchname) */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("an search failed *ident==%"S32_F"\n",*ident));
+          return NULL;
+        }
+      }
+      else
+      {
+        /* search failed, short object identifier (nosuchname) */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("an search failed, short object identifier\n"));
+        return NULL;
+      }
+    }
+    else if(node_type == MIB_NODE_LR)
+    {
+      struct mib_list_rootnode *lrn;
+      struct mib_list_node *ln;
+
+      if (ident_len > 0)
+      {
+        /* list root node (internal 'RAM', variable length) */
+        lrn = (struct mib_list_rootnode *)node;
+        ln = lrn->head;
+        /* iterate over list, head to tail */
+        while ((ln != NULL) && (ln->objid != *ident))
+        {
+          ln = ln->next;
+        }
+        if (ln != NULL)
+        {
+          /* found it, proceed to child */;
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln->objid==%"S32_F" *ident==%"S32_F"\n",ln->objid,*ident));
+          if (ln->nptr == NULL)
+          {
+            np->ident_len = ident_len;
+            np->ident = ident;
+            return (struct mib_node*)lrn;
+          }
+          else
+          {
+            /* follow next child pointer */
+            ident_len--;
+            ident++;
+            node = ln->nptr;
+          }
+        }
+        else
+        {
+          /* search failed */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln search failed *ident==%"S32_F"\n",*ident));
+          return NULL;
+        }
+      }
+      else
+      {
+        /* search failed, short object identifier (nosuchname) */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln search failed, short object identifier\n"));
+        return NULL;
+      }
+    }
+    else if(node_type == MIB_NODE_EX)
+    {
+      struct mib_external_node *en;
+      u16_t i, len;
+
+      if (ident_len > 0)
+      {
+        /* external node (addressing and access via functions) */
+        en = (struct mib_external_node *)node;
+
+        i = 0;
+        len = en->level_length(en->addr_inf,ext_level);
+        while ((i < len) && (en->ident_cmp(en->addr_inf,ext_level,i,*ident) != 0))
+        {
+          i++;
+        }
+        if (i < len)
+        {
+          s32_t debug_id;
+
+          en->get_objid(en->addr_inf,ext_level,i,&debug_id);
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("en->objid==%"S32_F" *ident==%"S32_F"\n",debug_id,*ident));
+          if ((ext_level + 1) == en->tree_levels)
+          {
+            np->ident_len = ident_len;
+            np->ident = ident;
+            return (struct mib_node*)en;
+          }
+          else
+          {
+            /* found it, proceed to child */
+            ident_len--;
+            ident++;
+            ext_level++;
+          }
+        }
+        else
+        {
+          /* search failed */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("en search failed *ident==%"S32_F"\n",*ident));
+          return NULL;
+        }
+      }
+      else
+      {
+        /* search failed, short object identifier (nosuchname) */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("en search failed, short object identifier\n"));
+        return NULL;
+      }
+    }
+    else if (node_type == MIB_NODE_SC)
+    {
+      mib_scalar_node *sn;
+
+      sn = (mib_scalar_node *)node;
+      if ((ident_len == 1) && (*ident == 0))
+      {
+        np->ident_len = ident_len;
+        np->ident = ident;
+        return (struct mib_node*)sn;
+      }
+      else
+      {
+        /* search failed, short object identifier (nosuchname) */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed, invalid object identifier length\n"));
+        return NULL;
+      }
+    }
+    else
+    {
+      /* unknown node_type */
+      LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed node_type %"U16_F" unkown\n",(u16_t)node_type));
+      return NULL;
+    }
+  }
+  /* done, found nothing */
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed node==%p\n",(void*)node));
+  return NULL;
+}
+
+/**
+ * Test table for presence of at least one table entry.
+ */
+static u8_t
+empty_table(struct mib_node *node)
+{
+  u8_t node_type;
+  u8_t empty = 0;
+
+  if (node != NULL)
+  {
+    node_type = node->node_type;
+    if (node_type == MIB_NODE_LR)
+    {
+      struct mib_list_rootnode *lrn;
+      lrn = (struct mib_list_rootnode *)node;
+      if ((lrn->count == 0) || (lrn->head == NULL))
+      {
+        empty = 1;
+      }
+    }
+    else if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA))
+    {
+      struct mib_array_node *an;
+      an = (struct mib_array_node *)node;
+      if ((an->maxlength == 0) || (an->nptr == NULL))
+      {
+        empty = 1;
+      }
+    }
+    else if (node_type == MIB_NODE_EX)
+    {
+      struct mib_external_node *en;
+      en = (struct mib_external_node *)node;
+      if (en->tree_levels == 0)
+      {
+        empty = 1;
+      }
+    }
+  }
+  return empty;
+}
+
+/**
+ * Tree expansion.
+ */
+struct mib_node *
+snmp_expand_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret)
+{
+  u8_t node_type, ext_level, climb_tree;
+
+  ext_level = 0;
+  /* reset node stack */
+  node_stack_cnt = 0;
+  while (node != NULL)
+  {
+    climb_tree = 0;
+    node_type = node->node_type;
+    if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA))
+    {
+      struct mib_array_node *an;
+      u16_t i;
+
+      /* array node (internal ROM or RAM, fixed length) */
+      an = (struct mib_array_node *)node;
+      if (ident_len > 0)
+      {
+        i = 0;
+        while ((i < an->maxlength) && (an->objid[i] < *ident))
+        {
+          i++;
+        }
+        if (i < an->maxlength)
+        {
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("an->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,an->objid[i],*ident));
+          /* add identifier to oidret */
+          oidret->id[oidret->len] = an->objid[i];
+          (oidret->len)++;
+
+          if (an->nptr[i] == NULL)
+          {
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("leaf node\n"));
+            /* leaf node (e.g. in a fixed size table) */
+            if (an->objid[i] > *ident)
+            {
+              return (struct mib_node*)an;
+            }
+            else if ((i + 1) < an->maxlength)
+            {
+              /* an->objid[i] == *ident */
+              (oidret->len)--;
+              oidret->id[oidret->len] = an->objid[i + 1];
+              (oidret->len)++;
+              return (struct mib_node*)an;
+            }
+            else
+            {
+              /* (i + 1) == an->maxlength */
+              (oidret->len)--;
+              climb_tree = 1;
+            }
+          }
+          else
+          {
+            u8_t j;
+            struct nse cur_node;
+
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("non-leaf node\n"));
+            /* non-leaf, store right child ptr and id */
+            j = i + 1;
+            while ((j < an->maxlength) && (empty_table(an->nptr[j])))
+            {
+              j++;
+            }
+            if (j < an->maxlength)
+            {
+              cur_node.r_ptr = an->nptr[j];
+              cur_node.r_id = an->objid[j];
+              cur_node.r_nl = 0;
+            }
+            else
+            {
+              cur_node.r_ptr = NULL;
+            }
+            push_node(&cur_node);
+            if (an->objid[i] == *ident)
+            {
+              ident_len--;
+              ident++;
+            }
+            else
+            {
+              /* an->objid[i] < *ident */
+              ident_len = 0;
+            }
+            /* follow next child pointer */
+            node = an->nptr[i];
+          }
+        }
+        else
+        {
+          /* i == an->maxlength */
+          climb_tree = 1;
+        }
+      }
+      else
+      {
+        u8_t j;
+        /* ident_len == 0, complete with leftmost '.thing' */
+        j = 0;
+        while ((j < an->maxlength) && empty_table(an->nptr[j]))
+        {
+          j++;
+        }
+        if (j < an->maxlength)
+        {
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("left an->objid[j]==%"S32_F"\n",an->objid[j]));
+          oidret->id[oidret->len] = an->objid[j];
+          (oidret->len)++;
+          if (an->nptr[j] == NULL)
+          {
+            /* leaf node */
+            return (struct mib_node*)an;
+          }
+          else
+          {
+            /* no leaf, continue */
+            node = an->nptr[j];
+          }
+        }
+        else
+        {
+          /* j == an->maxlength */
+          climb_tree = 1;
+        }
+      }
+    }
+    else if(node_type == MIB_NODE_LR)
+    {
+      struct mib_list_rootnode *lrn;
+      struct mib_list_node *ln;
+
+      /* list root node (internal 'RAM', variable length) */
+      lrn = (struct mib_list_rootnode *)node;
+      if (ident_len > 0)
+      {
+        ln = lrn->head;
+        /* iterate over list, head to tail */
+        while ((ln != NULL) && (ln->objid < *ident))
+        {
+          ln = ln->next;
+        }
+        if (ln != NULL)
+        {
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln->objid==%"S32_F" *ident==%"S32_F"\n",ln->objid,*ident));
+          oidret->id[oidret->len] = ln->objid;
+          (oidret->len)++;
+          if (ln->nptr == NULL)
+          {
+            /* leaf node */
+            if (ln->objid > *ident)
+            {
+              return (struct mib_node*)lrn;
+            }
+            else if (ln->next != NULL)
+            {
+              /* ln->objid == *ident */
+              (oidret->len)--;
+              oidret->id[oidret->len] = ln->next->objid;
+              (oidret->len)++;
+              return (struct mib_node*)lrn;
+            }
+            else
+            {
+              /* ln->next == NULL */
+              (oidret->len)--;
+              climb_tree = 1;
+            }
+          }
+          else
+          {
+            struct mib_list_node *jn;
+            struct nse cur_node;
+
+            /* non-leaf, store right child ptr and id */
+            jn = ln->next;
+            while ((jn != NULL) && empty_table(jn->nptr))
+            {
+              jn = jn->next;
+            }
+            if (jn != NULL)
+            {
+              cur_node.r_ptr = jn->nptr;
+              cur_node.r_id = jn->objid;
+              cur_node.r_nl = 0;
+            }
+            else
+            {
+              cur_node.r_ptr = NULL;
+            }
+            push_node(&cur_node);
+            if (ln->objid == *ident)
+            {
+              ident_len--;
+              ident++;
+            }
+            else
+            {
+              /* ln->objid < *ident */
+              ident_len = 0;
+            }
+            /* follow next child pointer */
+            node = ln->nptr;
+          }
+
+        }
+        else
+        {
+          /* ln == NULL */
+          climb_tree = 1;
+        }
+      }
+      else
+      {
+        struct mib_list_node *jn;
+        /* ident_len == 0, complete with leftmost '.thing' */
+        jn = lrn->head;
+        while ((jn != NULL) && empty_table(jn->nptr))
+        {
+          jn = jn->next;
+        }
+        if (jn != NULL)
+        {
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("left jn->objid==%"S32_F"\n",jn->objid));
+          oidret->id[oidret->len] = jn->objid;
+          (oidret->len)++;
+          if (jn->nptr == NULL)
+          {
+            /* leaf node */
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("jn->nptr == NULL\n"));
+            return (struct mib_node*)lrn;
+          }
+          else
+          {
+            /* no leaf, continue */
+            node = jn->nptr;
+          }
+        }
+        else
+        {
+          /* jn == NULL */
+          climb_tree = 1;
+        }
+      }
+    }
+    else if(node_type == MIB_NODE_EX)
+    {
+      struct mib_external_node *en;
+      s32_t ex_id;
+
+      /* external node (addressing and access via functions) */
+      en = (struct mib_external_node *)node;
+      if (ident_len > 0)
+      {
+        u16_t i, len;
+
+        i = 0;
+        len = en->level_length(en->addr_inf,ext_level);
+        while ((i < len) && (en->ident_cmp(en->addr_inf,ext_level,i,*ident) < 0))
+        {
+          i++;
+        }
+        if (i < len)
+        {
+          /* add identifier to oidret */
+          en->get_objid(en->addr_inf,ext_level,i,&ex_id);
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("en->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,ex_id,*ident));
+          oidret->id[oidret->len] = ex_id;
+          (oidret->len)++;
+
+          if ((ext_level + 1) == en->tree_levels)
+          {
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("leaf node\n"));
+            /* leaf node */
+            if (ex_id > *ident)
+            {
+              return (struct mib_node*)en;
+            }
+            else if ((i + 1) < len)
+            {
+              /* ex_id == *ident */
+              en->get_objid(en->addr_inf,ext_level,i + 1,&ex_id);
+              (oidret->len)--;
+              oidret->id[oidret->len] = ex_id;
+              (oidret->len)++;
+              return (struct mib_node*)en;
+            }
+            else
+            {
+              /* (i + 1) == len */
+              (oidret->len)--;
+              climb_tree = 1;
+            }
+          }
+          else
+          {
+            u8_t j;
+            struct nse cur_node;
+
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("non-leaf node\n"));
+            /* non-leaf, store right child ptr and id */
+            j = i + 1;
+            if (j < len)
+            {
+              /* right node is the current external node */
+              cur_node.r_ptr = node;
+              en->get_objid(en->addr_inf,ext_level,j,&cur_node.r_id);
+              cur_node.r_nl = ext_level + 1;
+            }
+            else
+            {
+              cur_node.r_ptr = NULL;
+            }
+            push_node(&cur_node);
+            if (en->ident_cmp(en->addr_inf,ext_level,i,*ident) == 0)
+            {
+              ident_len--;
+              ident++;
+            }
+            else
+            {
+              /* external id < *ident */
+              ident_len = 0;
+            }
+            /* proceed to child */
+            ext_level++;
+          }
+        }
+        else
+        {
+          /* i == len (en->level_len()) */
+          climb_tree = 1;
+        }
+      }
+      else
+      {
+        /* ident_len == 0, complete with leftmost '.thing' */
+        en->get_objid(en->addr_inf,ext_level,0,&ex_id);
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("left en->objid==%"S32_F"\n",ex_id));
+        oidret->id[oidret->len] = ex_id;
+        (oidret->len)++;
+        if ((ext_level + 1) == en->tree_levels)
+        {
+          /* leaf node */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("(ext_level + 1) == en->tree_levels\n"));
+          return (struct mib_node*)en;
+        }
+        else
+        {
+          /* no leaf, proceed to child */
+          ext_level++;
+        }
+      }
+    }
+    else if(node_type == MIB_NODE_SC)
+    {
+      mib_scalar_node *sn;
+
+      /* scalar node  */
+      sn = (mib_scalar_node *)node;
+      if (ident_len > 0)
+      {
+        /* at .0 */
+        climb_tree = 1;
+      }
+      else
+      {
+        /* ident_len == 0, complete object identifier */
+        oidret->id[oidret->len] = 0;
+        (oidret->len)++;
+        /* leaf node */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("completed scalar leaf\n"));
+        return (struct mib_node*)sn;
+      }
+    }
+    else
+    {
+      /* unknown/unhandled node_type */
+      LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed node_type %"U16_F" unkown\n",(u16_t)node_type));
+      return NULL;
+    }
+
+    if (climb_tree)
+    {
+      struct nse child;
+
+      /* find right child ptr */
+      child.r_ptr = NULL;
+      child.r_id = 0;
+      child.r_nl = 0;
+      while ((node_stack_cnt > 0) && (child.r_ptr == NULL))
+      {
+        pop_node(&child);
+        /* trim returned oid */
+        (oidret->len)--;
+      }
+      if (child.r_ptr != NULL)
+      {
+        /* incoming ident is useless beyond this point */
+        ident_len = 0;
+        oidret->id[oidret->len] = child.r_id;
+        oidret->len++;
+        node = child.r_ptr;
+        ext_level = child.r_nl;
+      }
+      else
+      {
+        /* tree ends here ... */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed, tree ends here\n"));
+        return NULL;
+      }
+    }
+  }
+  /* done, found nothing */
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed node==%p\n",(void*)node));
+  return NULL;
+}
+
+/**
+ * Test object identifier for the iso.org.dod.internet prefix.
+ *
+ * @param ident_len the length of the supplied object identifier
+ * @param ident points to the array of sub identifiers
+ * @return 1 if it matches, 0 otherwise
+ */
+u8_t
+snmp_iso_prefix_tst(u8_t ident_len, s32_t *ident)
+{
+  if ((ident_len > 3) &&
+      (ident[0] == 1) && (ident[1] == 3) &&
+      (ident[2] == 6) && (ident[3] == 1))
+  {
+    return 1;
+  }
+  else
+  {
+    return 0;
+  }
+}
+
+/**
+ * Expands object identifier to the iso.org.dod.internet
+ * prefix for use in getnext operation.
+ *
+ * @param ident_len the length of the supplied object identifier
+ * @param ident points to the array of sub identifiers
+ * @param oidret points to returned expanded object identifier
+ * @return 1 if it matches, 0 otherwise
+ *
+ * @note ident_len 0 is allowed, expanding to the first known object id!!
+ */
+u8_t
+snmp_iso_prefix_expand(u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret)
+{
+  const s32_t *prefix_ptr;
+  s32_t *ret_ptr;
+  u8_t i;
+
+  i = 0;
+  prefix_ptr = &prefix[0];
+  ret_ptr = &oidret->id[0];
+  ident_len = ((ident_len < 4)?ident_len:4);
+  while ((i < ident_len) && ((*ident) <= (*prefix_ptr)))
+  {
+    *ret_ptr++ = *prefix_ptr++;
+    ident++;
+    i++;
+  }
+  if (i == ident_len)
+  {
+    /* match, complete missing bits */
+    while (i < 4)
+    {
+      *ret_ptr++ = *prefix_ptr++;
+      i++;
+    }
+    oidret->len = i;
+    return 1;
+  }
+  else
+  {
+    /* i != ident_len */
+    return 0;
+  }
+}
+
+#endif /* LWIP_SNMP */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/snmp/msg_in.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/snmp/msg_in.c
new file mode 100644
index 0000000..1999d13
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/snmp/msg_in.c
@@ -0,0 +1,1458 @@
+/**
+ * @file
+ * SNMP input message processing (RFC1157).
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP
+#include 
+#include "arch/cc.h"
+#include "lwip/ip_addr.h"
+#include "lwip/mem.h"
+#include "lwip/udp.h"
+#include "lwip/stats.h"
+
+#include "lwip/snmp.h"
+#include "lwip/snmp_asn1.h"
+#include "lwip/snmp_msg.h"
+#include "lwip/snmp_structs.h"
+
+
+/* public (non-static) constants */
+/** SNMP v1 == 0 */
+const s32_t snmp_version = 0;
+/** default SNMP community string */
+const char snmp_publiccommunity[7] = "public";
+
+/* statically allocated buffers for SNMP_CONCURRENT_REQUESTS */
+#if (SNMP_CONCURRENT_REQUESTS == 0)
+#error "need at least one snmp_msg_pstat"
+#endif
+struct snmp_msg_pstat msg_input_list[SNMP_CONCURRENT_REQUESTS];
+/* UDP Protocol Control Block */
+struct udp_pcb *snmp1_pcb = NULL;
+
+static void snmp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port);
+static err_t snmp_pdu_header_check(struct pbuf *p, u16_t ofs, u16_t pdu_len, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat);
+static err_t snmp_pdu_dec_varbindlist(struct pbuf *p, u16_t ofs, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat);
+
+
+/**
+ * Starts SNMP Agent.
+ * Allocates UDP pcb and binds it to IP_ADDR_ANY port 161.
+ */
+void
+snmp_init(void)
+{
+  struct snmp_msg_pstat *msg_ps;
+  u8_t i;
+
+  snmp1_pcb = udp_new();
+  if (snmp1_pcb != NULL)
+  {
+    udp_recv(snmp1_pcb, snmp_recv, (void *)SNMP_IN_PORT);
+    udp_bind(snmp1_pcb, IP_ADDR_ANY, SNMP_IN_PORT);
+  }
+  msg_ps = &msg_input_list[0];
+  for (i=0; istate = SNMP_MSG_EMPTY;
+    msg_ps->error_index = 0;
+    msg_ps->error_status = SNMP_ES_NOERROR;
+    msg_ps++;
+  }
+  trap_msg.pcb = snmp1_pcb;
+  /* The coldstart trap will only be output
+     if our outgoing interface is up & configured  */
+  snmp_coldstart_trap();
+}
+
+static void
+snmp_error_response(struct snmp_msg_pstat *msg_ps, u8_t error)
+{
+  snmp_varbind_list_free(&msg_ps->outvb);
+  msg_ps->outvb = msg_ps->invb;
+  msg_ps->invb.head = NULL;
+  msg_ps->invb.tail = NULL;
+  msg_ps->invb.count = 0;
+  msg_ps->error_status = error;
+  msg_ps->error_index = 1 + msg_ps->vb_idx;
+  snmp_send_response(msg_ps);
+  snmp_varbind_list_free(&msg_ps->outvb);
+  msg_ps->state = SNMP_MSG_EMPTY;
+}
+
+static void
+snmp_ok_response(struct snmp_msg_pstat *msg_ps)
+{
+  err_t err_ret;
+
+  err_ret = snmp_send_response(msg_ps);
+  if (err_ret == ERR_MEM)
+  {
+    /* serious memory problem, can't return tooBig */
+#if LWIP_STATS
+    LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event pbufs.used = %"U16_F"\n",lwip_stats.pbuf.used));
+#endif
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event = %"S32_F"\n",msg_ps->error_status));
+  }
+  /* free varbinds (if available) */
+  snmp_varbind_list_free(&msg_ps->invb);
+  snmp_varbind_list_free(&msg_ps->outvb);
+  msg_ps->state = SNMP_MSG_EMPTY;
+}
+
+/**
+ * Service an internal or external event for SNMP GET.
+ *
+ * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1)
+ * @param msg_ps points to the assosicated message process state
+ */
+static void
+snmp_msg_get_event(u8_t request_id, struct snmp_msg_pstat *msg_ps)
+{
+  LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_get_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state));
+
+  if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF)
+  {
+    struct mib_external_node *en;
+    struct snmp_name_ptr np;
+
+    /* get_object_def() answer*/
+    en = msg_ps->ext_mib_node;
+    np = msg_ps->ext_name_ptr;
+
+    /* translate answer into a known lifeform */
+    en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def);
+    if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE)
+    {
+      msg_ps->state = SNMP_MSG_EXTERNAL_GET_VALUE;
+      en->get_value_q(request_id, &msg_ps->ext_object_def);
+    }
+    else
+    {
+      en->get_object_def_pc(request_id, np.ident_len, np.ident);
+      /* search failed, object id points to unknown object (nosuchname) */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_VALUE)
+  {
+    struct mib_external_node *en;
+    struct snmp_varbind *vb;
+
+    /* get_value() answer */
+    en = msg_ps->ext_mib_node;
+
+    /* allocate output varbind */
+    vb = (struct snmp_varbind *)mem_malloc(sizeof(struct snmp_varbind));
+    LWIP_ASSERT("vb != NULL",vb != NULL);
+    if (vb != NULL)
+    {
+      vb->next = NULL;
+      vb->prev = NULL;
+
+      /* move name from invb to outvb */
+      vb->ident = msg_ps->vb_ptr->ident;
+      vb->ident_len = msg_ps->vb_ptr->ident_len;
+      /* ensure this memory is refereced once only */
+      msg_ps->vb_ptr->ident = NULL;
+      msg_ps->vb_ptr->ident_len = 0;
+
+      vb->value_type = msg_ps->ext_object_def.asn_type;
+      vb->value_len =  msg_ps->ext_object_def.v_len;
+      if (vb->value_len > 0)
+      {
+        vb->value = mem_malloc(vb->value_len);
+        LWIP_ASSERT("vb->value != NULL",vb->value != NULL);
+        if (vb->value != NULL)
+        {
+          en->get_value_a(request_id, &msg_ps->ext_object_def, vb->value_len, vb->value);
+          snmp_varbind_tail_add(&msg_ps->outvb, vb);
+          /* search again (if vb_idx < msg_ps->invb.count) */
+          msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+          msg_ps->vb_idx += 1;
+        }
+        else
+        {
+          en->get_value_pc(request_id, &msg_ps->ext_object_def);
+          LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: no variable space\n"));
+          msg_ps->vb_ptr->ident = vb->ident;
+          msg_ps->vb_ptr->ident_len = vb->ident_len;
+          mem_free(vb);
+          snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+        }
+      }
+      else
+      {
+        /* vb->value_len == 0, empty value (e.g. empty string) */
+        en->get_value_a(request_id, &msg_ps->ext_object_def, 0, NULL);
+        vb->value = NULL;
+        snmp_varbind_tail_add(&msg_ps->outvb, vb);
+        /* search again (if vb_idx < msg_ps->invb.count) */
+        msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+        msg_ps->vb_idx += 1;
+      }
+    }
+    else
+    {
+      en->get_value_pc(request_id, &msg_ps->ext_object_def);
+      LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: no outvb space\n"));
+      snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+    }
+  }
+
+  while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+         (msg_ps->vb_idx < msg_ps->invb.count))
+  {
+    struct mib_node *mn;
+    struct snmp_name_ptr np;
+
+    if (msg_ps->vb_idx == 0)
+    {
+      msg_ps->vb_ptr = msg_ps->invb.head;
+    }
+    else
+    {
+      msg_ps->vb_ptr = msg_ps->vb_ptr->next;
+    }
+    /** test object identifier for .iso.org.dod.internet prefix */
+    if (snmp_iso_prefix_tst(msg_ps->vb_ptr->ident_len,  msg_ps->vb_ptr->ident))
+    {
+      mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4,
+                             msg_ps->vb_ptr->ident + 4, &np);
+    }
+    else
+    {
+      mn = NULL;
+    }
+    if (mn != NULL)
+    {
+      if (mn->node_type == MIB_NODE_EX)
+      {
+        /* external object */
+        struct mib_external_node *en = (struct mib_external_node*)mn;
+
+        msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF;
+        /* save en && args in msg_ps!! */
+        msg_ps->ext_mib_node = en;
+        msg_ps->ext_name_ptr = np;
+
+        en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident);
+      }
+      else
+      {
+        /* internal object */
+        struct obj_def object_def;
+
+        msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF;
+        mn->get_object_def(np.ident_len, np.ident, &object_def);
+        if (object_def.instance != MIB_OBJECT_NONE)
+        {
+          mn = mn;
+        }
+        else
+        {
+          /* search failed, object id points to unknown object (nosuchname) */
+          mn =  NULL;
+        }
+        if (mn != NULL)
+        {
+          struct snmp_varbind *vb;
+
+          msg_ps->state = SNMP_MSG_INTERNAL_GET_VALUE;
+          /* allocate output varbind */
+          vb = (struct snmp_varbind *)mem_malloc(sizeof(struct snmp_varbind));
+          LWIP_ASSERT("vb != NULL",vb != NULL);
+          if (vb != NULL)
+          {
+            vb->next = NULL;
+            vb->prev = NULL;
+
+            /* move name from invb to outvb */
+            vb->ident = msg_ps->vb_ptr->ident;
+            vb->ident_len = msg_ps->vb_ptr->ident_len;
+            /* ensure this memory is refereced once only */
+            msg_ps->vb_ptr->ident = NULL;
+            msg_ps->vb_ptr->ident_len = 0;
+
+            vb->value_type = object_def.asn_type;
+            vb->value_len = object_def.v_len;
+            if (vb->value_len > 0)
+            {
+              vb->value = mem_malloc(vb->value_len);
+              LWIP_ASSERT("vb->value != NULL",vb->value != NULL);
+              if (vb->value != NULL)
+              {
+                mn->get_value(&object_def, vb->value_len, vb->value);
+                snmp_varbind_tail_add(&msg_ps->outvb, vb);
+                msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+                msg_ps->vb_idx += 1;
+              }
+              else
+              {
+                LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: couldn't allocate variable space\n"));
+                msg_ps->vb_ptr->ident = vb->ident;
+                msg_ps->vb_ptr->ident_len = vb->ident_len;
+                mem_free(vb);
+                snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+              }
+            }
+            else
+            {
+              /* vb->value_len == 0, empty value (e.g. empty string) */
+              vb->value = NULL;
+              snmp_varbind_tail_add(&msg_ps->outvb, vb);
+              msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+              msg_ps->vb_idx += 1;
+            }
+          }
+          else
+          {
+            LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: couldn't allocate outvb space\n"));
+            snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+          }
+        }
+      }
+    }
+    if (mn == NULL)
+    {
+      /* mn == NULL, noSuchName */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+      (msg_ps->vb_idx == msg_ps->invb.count))
+  {
+    snmp_ok_response(msg_ps);
+  }
+}
+
+/**
+ * Service an internal or external event for SNMP GETNEXT.
+ *
+ * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1)
+ * @param msg_ps points to the assosicated message process state
+ */
+static void
+snmp_msg_getnext_event(u8_t request_id, struct snmp_msg_pstat *msg_ps)
+{
+  LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_getnext_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state));
+
+  if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF)
+  {
+    struct mib_external_node *en;
+
+    /* get_object_def() answer*/
+    en = msg_ps->ext_mib_node;
+
+    /* translate answer into a known lifeform */
+    en->get_object_def_a(request_id, 1, &msg_ps->ext_oid.id[msg_ps->ext_oid.len - 1], &msg_ps->ext_object_def);
+    if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE)
+    {
+      msg_ps->state = SNMP_MSG_EXTERNAL_GET_VALUE;
+      en->get_value_q(request_id, &msg_ps->ext_object_def);
+    }
+    else
+    {
+      en->get_object_def_pc(request_id, 1, &msg_ps->ext_oid.id[msg_ps->ext_oid.len - 1]);
+      /* search failed, object id points to unknown object (nosuchname) */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_VALUE)
+  {
+    struct mib_external_node *en;
+    struct snmp_varbind *vb;
+
+    /* get_value() answer */
+    en = msg_ps->ext_mib_node;
+
+    vb = snmp_varbind_alloc(&msg_ps->ext_oid,
+                            msg_ps->ext_object_def.asn_type,
+                            msg_ps->ext_object_def.v_len);
+    if (vb != NULL)
+    {
+      en->get_value_a(request_id, &msg_ps->ext_object_def, vb->value_len, vb->value);
+      snmp_varbind_tail_add(&msg_ps->outvb, vb);
+      msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+      msg_ps->vb_idx += 1;
+    }
+    else
+    {
+      en->get_value_pc(request_id, &msg_ps->ext_object_def);
+      LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_getnext_event: couldn't allocate outvb space\n"));
+      snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+    }
+  }
+
+  while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+         (msg_ps->vb_idx < msg_ps->invb.count))
+  {
+    struct mib_node *mn;
+    struct snmp_obj_id oid;
+
+    if (msg_ps->vb_idx == 0)
+    {
+      msg_ps->vb_ptr = msg_ps->invb.head;
+    }
+    else
+    {
+      msg_ps->vb_ptr = msg_ps->vb_ptr->next;
+    }
+    if (snmp_iso_prefix_expand(msg_ps->vb_ptr->ident_len, msg_ps->vb_ptr->ident, &oid))
+    {
+      if (msg_ps->vb_ptr->ident_len > 3)
+      {
+        /* can offset ident_len and ident */
+        mn = snmp_expand_tree((struct mib_node*)&internet,
+                              msg_ps->vb_ptr->ident_len - 4,
+                              msg_ps->vb_ptr->ident + 4, &oid);
+      }
+      else
+      {
+        /* can't offset ident_len -4, ident + 4 */
+        mn = snmp_expand_tree((struct mib_node*)&internet, 0, NULL, &oid);
+      }
+    }
+    else
+    {
+      mn = NULL;
+    }
+    if (mn != NULL)
+    {
+      if (mn->node_type == MIB_NODE_EX)
+      {
+        /* external object */
+        struct mib_external_node *en = (struct mib_external_node*)mn;
+
+        msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF;
+        /* save en && args in msg_ps!! */
+        msg_ps->ext_mib_node = en;
+        msg_ps->ext_oid = oid;
+
+        en->get_object_def_q(en->addr_inf, request_id, 1, &oid.id[oid.len - 1]);
+      }
+      else
+      {
+        /* internal object */
+        struct obj_def object_def;
+        struct snmp_varbind *vb;
+
+        msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF;
+        mn->get_object_def(1, &oid.id[oid.len - 1], &object_def);
+
+        vb = snmp_varbind_alloc(&oid, object_def.asn_type, object_def.v_len);
+        if (vb != NULL)
+        {
+          msg_ps->state = SNMP_MSG_INTERNAL_GET_VALUE;
+          mn->get_value(&object_def, object_def.v_len, vb->value);
+          snmp_varbind_tail_add(&msg_ps->outvb, vb);
+          msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+          msg_ps->vb_idx += 1;
+        }
+        else
+        {
+          LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv couldn't allocate outvb space\n"));
+          snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+        }
+      }
+    }
+    if (mn == NULL)
+    {
+      /* mn == NULL, noSuchName */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+      (msg_ps->vb_idx == msg_ps->invb.count))
+  {
+    snmp_ok_response(msg_ps);
+  }
+}
+
+/**
+ * Service an internal or external event for SNMP SET.
+ *
+ * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1)
+ * @param msg_ps points to the assosicated message process state
+ */
+static void
+snmp_msg_set_event(u8_t request_id, struct snmp_msg_pstat *msg_ps)
+{
+  LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_set_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state));
+
+  if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF)
+  {
+    struct mib_external_node *en;
+    struct snmp_name_ptr np;
+
+    /* get_object_def() answer*/
+    en = msg_ps->ext_mib_node;
+    np = msg_ps->ext_name_ptr;
+
+    /* translate answer into a known lifeform */
+    en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def);
+    if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE)
+    {
+      msg_ps->state = SNMP_MSG_EXTERNAL_SET_TEST;
+      en->set_test_q(request_id, &msg_ps->ext_object_def);
+    }
+    else
+    {
+      en->get_object_def_pc(request_id, np.ident_len, np.ident);
+      /* search failed, object id points to unknown object (nosuchname) */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  else if (msg_ps->state == SNMP_MSG_EXTERNAL_SET_TEST)
+  {
+    struct mib_external_node *en;
+    struct snmp_name_ptr np;
+
+    /* set_test() answer*/
+    en = msg_ps->ext_mib_node;
+    np = msg_ps->ext_name_ptr;
+
+    if (msg_ps->ext_object_def.access == MIB_OBJECT_READ_WRITE)
+    {
+       if ((msg_ps->ext_object_def.asn_type == msg_ps->vb_ptr->value_type) &&
+           (en->set_test_a(request_id,&msg_ps->ext_object_def,
+                           msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value) != 0))
+      {
+        msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+        msg_ps->vb_idx += 1;
+      }
+      else
+      {
+        en->set_test_pc(request_id,&msg_ps->ext_object_def);
+        /* bad value */
+        snmp_error_response(msg_ps,SNMP_ES_BADVALUE);
+      }
+    }
+    else
+    {
+      en->set_test_pc(request_id,&msg_ps->ext_object_def);
+      /* object not available for set */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF_S)
+  {
+    struct mib_external_node *en;
+    struct snmp_name_ptr np;
+
+    /* get_object_def() answer*/
+    en = msg_ps->ext_mib_node;
+    np = msg_ps->ext_name_ptr;
+
+    /* translate answer into a known lifeform */
+    en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def);
+    if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE)
+    {
+      msg_ps->state = SNMP_MSG_EXTERNAL_SET_VALUE;
+      en->set_value_q(request_id, &msg_ps->ext_object_def,
+                      msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value);
+    }
+    else
+    {
+      en->get_object_def_pc(request_id, np.ident_len, np.ident);
+      /* set_value failed, object has disappeared for some odd reason?? */
+      snmp_error_response(msg_ps,SNMP_ES_GENERROR);
+    }
+  }
+  else if (msg_ps->state == SNMP_MSG_EXTERNAL_SET_VALUE)
+  {
+    struct mib_external_node *en;
+
+    /** set_value_a() @todo: use reply value?? */
+    en = msg_ps->ext_mib_node;
+    en->set_value_a(request_id, &msg_ps->ext_object_def, 0, NULL);
+
+    /** @todo use set_value_pc() if toobig */
+    msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE;
+    msg_ps->vb_idx += 1;
+  }
+
+  /* test all values before setting */
+  while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+         (msg_ps->vb_idx < msg_ps->invb.count))
+  {
+    struct mib_node *mn;
+    struct snmp_name_ptr np;
+
+    if (msg_ps->vb_idx == 0)
+    {
+      msg_ps->vb_ptr = msg_ps->invb.head;
+    }
+    else
+    {
+      msg_ps->vb_ptr = msg_ps->vb_ptr->next;
+    }
+    /** test object identifier for .iso.org.dod.internet prefix */
+    if (snmp_iso_prefix_tst(msg_ps->vb_ptr->ident_len,  msg_ps->vb_ptr->ident))
+    {
+      mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4,
+                             msg_ps->vb_ptr->ident + 4, &np);
+    }
+    else
+    {
+      mn = NULL;
+    }
+    if (mn != NULL)
+    {
+      if (mn->node_type == MIB_NODE_EX)
+      {
+        /* external object */
+        struct mib_external_node *en = (struct mib_external_node*)mn;
+
+        msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF;
+        /* save en && args in msg_ps!! */
+        msg_ps->ext_mib_node = en;
+        msg_ps->ext_name_ptr = np;
+
+        en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident);
+      }
+      else
+      {
+        /* internal object */
+        struct obj_def object_def;
+
+        msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF;
+        mn->get_object_def(np.ident_len, np.ident, &object_def);
+        if (object_def.instance != MIB_OBJECT_NONE)
+        {
+          mn = mn;
+        }
+        else
+        {
+          /* search failed, object id points to unknown object (nosuchname) */
+          mn = NULL;
+        }
+        if (mn != NULL)
+        {
+          msg_ps->state = SNMP_MSG_INTERNAL_SET_TEST;
+
+          if (object_def.access == MIB_OBJECT_READ_WRITE)
+          {
+            if ((object_def.asn_type == msg_ps->vb_ptr->value_type) &&
+                (mn->set_test(&object_def,msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value) != 0))
+            {
+              msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+              msg_ps->vb_idx += 1;
+            }
+            else
+            {
+              /* bad value */
+              snmp_error_response(msg_ps,SNMP_ES_BADVALUE);
+            }
+          }
+          else
+          {
+            /* object not available for set */
+            snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+          }
+        }
+      }
+    }
+    if (mn == NULL)
+    {
+      /* mn == NULL, noSuchName */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+
+  if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+      (msg_ps->vb_idx == msg_ps->invb.count))
+  {
+    msg_ps->vb_idx = 0;
+    msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE;
+  }
+
+  /* set all values "atomically" (be as "atomic" as possible) */
+  while ((msg_ps->state == SNMP_MSG_INTERNAL_SET_VALUE) &&
+         (msg_ps->vb_idx < msg_ps->invb.count))
+  {
+    struct mib_node *mn;
+    struct snmp_name_ptr np;
+
+    if (msg_ps->vb_idx == 0)
+    {
+      msg_ps->vb_ptr = msg_ps->invb.head;
+    }
+    else
+    {
+      msg_ps->vb_ptr = msg_ps->vb_ptr->next;
+    }
+    /* skip iso prefix test, was done previously while settesting() */
+    mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4,
+                           msg_ps->vb_ptr->ident + 4, &np);
+    /* check if object is still available
+       (e.g. external hot-plug thingy present?) */
+    if (mn != NULL)
+    {
+      if (mn->node_type == MIB_NODE_EX)
+      {
+        /* external object */
+        struct mib_external_node *en = (struct mib_external_node*)mn;
+
+        msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF_S;
+        /* save en && args in msg_ps!! */
+        msg_ps->ext_mib_node = en;
+        msg_ps->ext_name_ptr = np;
+
+        en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident);
+      }
+      else
+      {
+        /* internal object */
+        struct obj_def object_def;
+
+        msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF_S;
+        mn->get_object_def(np.ident_len, np.ident, &object_def);
+        msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE;
+        mn->set_value(&object_def,msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value);
+        msg_ps->vb_idx += 1;
+      }
+    }
+  }
+  if ((msg_ps->state == SNMP_MSG_INTERNAL_SET_VALUE) &&
+      (msg_ps->vb_idx == msg_ps->invb.count))
+  {
+    /* simply echo the input if we can set it
+       @todo do we need to return the actual value?
+       e.g. if value is silently modified or behaves sticky? */
+    msg_ps->outvb = msg_ps->invb;
+    msg_ps->invb.head = NULL;
+    msg_ps->invb.tail = NULL;
+    msg_ps->invb.count = 0;
+    snmp_ok_response(msg_ps);
+  }
+}
+
+
+/**
+ * Handle one internal or external event.
+ * Called for one async event. (recv external/private answer)
+ *
+ * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1)
+ */
+void
+snmp_msg_event(u8_t request_id)
+{
+  struct snmp_msg_pstat *msg_ps;
+
+  if (request_id < SNMP_CONCURRENT_REQUESTS)
+  {
+    msg_ps = &msg_input_list[request_id];
+    if (msg_ps->rt == SNMP_ASN1_PDU_GET_NEXT_REQ)
+    {
+      snmp_msg_getnext_event(request_id, msg_ps);
+    }
+    else if (msg_ps->rt == SNMP_ASN1_PDU_GET_REQ)
+    {
+      snmp_msg_get_event(request_id, msg_ps);
+    }
+    else if(msg_ps->rt == SNMP_ASN1_PDU_SET_REQ)
+    {
+      snmp_msg_set_event(request_id, msg_ps);
+    }
+  }
+}
+
+
+/* lwIP UDP receive callback function */
+static void
+snmp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port)
+{
+  struct udp_hdr *udphdr;
+
+  /* suppress unused argument warning */
+  if (arg);
+  /* peek in the UDP header (goto IP payload) */
+  pbuf_header(p, UDP_HLEN);
+  udphdr = p->payload;
+
+  /* check if datagram is really directed at us (including broadcast requests) */
+  if ((pcb == snmp1_pcb) && (ntohs(udphdr->dest) == 161))
+  {
+    struct snmp_msg_pstat *msg_ps;
+    u8_t req_idx;
+
+    /* traverse input message process list, look for SNMP_MSG_EMPTY */
+    msg_ps = &msg_input_list[0];
+    req_idx = 0;
+    while ((req_idxstate != SNMP_MSG_EMPTY))
+    {
+      req_idx++;
+      msg_ps++;
+    }
+    if (req_idx != SNMP_CONCURRENT_REQUESTS)
+    {
+      err_t err_ret;
+      u16_t payload_len;
+      u16_t payload_ofs;
+      u16_t varbind_ofs = 0;
+
+      /* accepting request */
+      snmp_inc_snmpinpkts();
+      /* record used 'protocol control block' */
+      msg_ps->pcb = pcb;
+      /* source address (network order) */
+      msg_ps->sip = *addr;
+      /* source port (host order (lwIP oddity)) */
+      msg_ps->sp = port;
+      /* read UDP payload length from UDP header */
+      payload_len = ntohs(udphdr->len) - UDP_HLEN;
+
+      /* adjust to UDP payload */
+      payload_ofs = UDP_HLEN;
+
+      /* check total length, version, community, pdu type */
+      err_ret = snmp_pdu_header_check(p, payload_ofs, payload_len, &varbind_ofs, msg_ps);
+      if (((msg_ps->rt == SNMP_ASN1_PDU_GET_REQ) ||
+           (msg_ps->rt == SNMP_ASN1_PDU_GET_NEXT_REQ) ||
+           (msg_ps->rt == SNMP_ASN1_PDU_SET_REQ)) &&
+          ((msg_ps->error_status == SNMP_ES_NOERROR) &&
+           (msg_ps->error_index == 0)) )
+      {
+        /* Only accept requests and requests without error (be robust) */
+        err_ret = err_ret;
+      }
+      else
+      {
+        /* Reject response and trap headers or error requests as input! */
+        err_ret = ERR_ARG;
+      }
+      if (err_ret == ERR_OK)
+      {
+        LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv ok, community %s\n", msg_ps->community));
+
+        /* Builds a list of variable bindings. Copy the varbinds from the pbuf
+          chain to glue them when these are divided over two or more pbuf's. */
+        err_ret = snmp_pdu_dec_varbindlist(p, varbind_ofs, &varbind_ofs, msg_ps);
+        if ((err_ret == ERR_OK) && (msg_ps->invb.count > 0))
+        {
+          /* we've decoded the incoming message, release input msg now */
+          pbuf_free(p);
+
+          msg_ps->error_status = SNMP_ES_NOERROR;
+          msg_ps->error_index = 0;
+          /* find object for each variable binding */
+          msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+          /* first variable binding from list to inspect */
+          msg_ps->vb_idx = 0;
+
+          LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv varbind cnt=%"U16_F"\n",(u16_t)msg_ps->invb.count));
+
+          /* handle input event and as much objects as possible in one go */
+          snmp_msg_event(req_idx);
+        }
+        else
+        {
+          /* varbind-list decode failed, or varbind list empty.
+             drop request silently, do not return error!
+             (errors are only returned for a specific varbind failure) */
+          pbuf_free(p);
+          LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_pdu_dec_varbindlist() failed\n"));
+        }
+      }
+      else
+      {
+        /* header check failed
+           drop request silently, do not return error! */
+        pbuf_free(p);
+        LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_pdu_header_check() failed\n"));
+      }
+    }
+    else
+    {
+      /* exceeding number of concurrent requests */
+      pbuf_free(p);
+    }
+  }
+  else
+  {
+    /* datagram not for us */
+    pbuf_free(p);
+  }
+}
+
+/**
+ * Checks and decodes incoming SNMP message header, logs header errors.
+ *
+ * @param p points to pbuf chain of SNMP message (UDP payload)
+ * @param ofs points to first octet of SNMP message
+ * @param pdu_len the length of the UDP payload
+ * @param ofs_ret returns the ofset of the variable bindings
+ * @param m_stat points to the current message request state return
+ * @return
+ * - ERR_OK SNMP header is sane and accepted
+ * - ERR_ARG SNMP header is either malformed or rejected
+ */
+static err_t
+snmp_pdu_header_check(struct pbuf *p, u16_t ofs, u16_t pdu_len, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat)
+{
+  err_t derr;
+  u16_t len, ofs_base;
+  u8_t  len_octets;
+  u8_t  type;
+  s32_t version;
+
+  ofs_base = ofs;
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) ||
+      (pdu_len != (1 + len_octets + len)) ||
+      (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)))
+  {
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets);
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)))
+  {
+    /* can't decode or no integer (version) */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &version);
+  if (derr != ERR_OK)
+  {
+    /* can't decode */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  if (version != 0)
+  {
+    /* not version 1 */
+    snmp_inc_snmpinbadversions();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets + len);
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR)))
+  {
+    /* can't decode or no octet string (community) */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, SNMP_COMMUNITY_STR_LEN, m_stat->community);
+  if (derr != ERR_OK)
+  {
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  /* add zero terminator */
+  len = ((len < (SNMP_COMMUNITY_STR_LEN))?(len):(SNMP_COMMUNITY_STR_LEN));
+  m_stat->community[len] = 0;
+  m_stat->com_strlen = len;
+  if (strncmp(snmp_publiccommunity, (const char*)m_stat->community, SNMP_COMMUNITY_STR_LEN) != 0)
+  {
+    /** @todo: move this if we need to check more names */
+    snmp_inc_snmpinbadcommunitynames();
+    snmp_authfail_trap();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets + len);
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if (derr != ERR_OK)
+  {
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  switch(type)
+  {
+    case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_REQ):
+      /* GetRequest PDU */
+      snmp_inc_snmpingetrequests();
+      derr = ERR_OK;
+      break;
+    case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_NEXT_REQ):
+      /* GetNextRequest PDU */
+      snmp_inc_snmpingetnexts();
+      derr = ERR_OK;
+      break;
+    case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_RESP):
+      /* GetResponse PDU */
+      snmp_inc_snmpingetresponses();
+      derr = ERR_ARG;
+      break;
+    case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_SET_REQ):
+      /* SetRequest PDU */
+      snmp_inc_snmpinsetrequests();
+      derr = ERR_OK;
+      break;
+    case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_TRAP):
+      /* Trap PDU */
+      snmp_inc_snmpintraps();
+      derr = ERR_ARG;
+      break;
+    default:
+      snmp_inc_snmpinasnparseerrs();
+      derr = ERR_ARG;
+      break;
+  }
+  if (derr != ERR_OK)
+  {
+    /* unsupported input PDU for this agent (no parse error) */
+    return ERR_ARG;
+  }
+  m_stat->rt = type & 0x1F;
+  ofs += (1 + len_octets);
+  if (len != (pdu_len - (ofs - ofs_base)))
+  {
+    /* decoded PDU length does not equal actual payload length */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)))
+  {
+    /* can't decode or no integer (request ID) */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->rid);
+  if (derr != ERR_OK)
+  {
+    /* can't decode */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets + len);
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)))
+  {
+    /* can't decode or no integer (error-status) */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  /* must be noError (0) for incoming requests.
+     log errors for mib-2 completeness and for debug purposes */
+  derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->error_status);
+  if (derr != ERR_OK)
+  {
+    /* can't decode */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  switch (m_stat->error_status)
+  {
+    case SNMP_ES_TOOBIG:
+      snmp_inc_snmpintoobigs();
+      break;
+    case SNMP_ES_NOSUCHNAME:
+      snmp_inc_snmpinnosuchnames();
+      break;
+    case SNMP_ES_BADVALUE:
+      snmp_inc_snmpinbadvalues();
+      break;
+    case SNMP_ES_READONLY:
+      snmp_inc_snmpinreadonlys();
+      break;
+    case SNMP_ES_GENERROR:
+      snmp_inc_snmpingenerrs();
+      break;
+  }
+  ofs += (1 + len_octets + len);
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)))
+  {
+    /* can't decode or no integer (error-index) */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  /* must be 0 for incoming requests.
+     decode anyway to catch bad integers (and dirty tricks) */
+  derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->error_index);
+  if (derr != ERR_OK)
+  {
+    /* can't decode */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets + len);
+  *ofs_ret = ofs;
+  return ERR_OK;
+}
+
+static err_t
+snmp_pdu_dec_varbindlist(struct pbuf *p, u16_t ofs, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat)
+{
+  err_t derr;
+  u16_t len, vb_len;
+  u8_t  len_octets;
+  u8_t type;
+
+  /* variable binding list */
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &vb_len);
+  if ((derr != ERR_OK) ||
+      (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)))
+  {
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets);
+
+  /* start with empty list */
+  m_stat->invb.count = 0;
+  m_stat->invb.head = NULL;
+  m_stat->invb.tail = NULL;
+
+  while (vb_len > 0)
+  {
+    struct snmp_obj_id oid, oid_value;
+    struct snmp_varbind *vb;
+
+    snmp_asn1_dec_type(p, ofs, &type);
+    derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+    if ((derr != ERR_OK) ||
+        (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)) ||
+        (len <= 0) || (len > vb_len))
+    {
+      snmp_inc_snmpinasnparseerrs();
+      /* free varbinds (if available) */
+      snmp_varbind_list_free(&m_stat->invb);
+      return ERR_ARG;
+    }
+    ofs += (1 + len_octets);
+    vb_len -= (1 + len_octets);
+
+    snmp_asn1_dec_type(p, ofs, &type);
+    derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+    if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID)))
+    {
+      /* can't decode object name length */
+      snmp_inc_snmpinasnparseerrs();
+      /* free varbinds (if available) */
+      snmp_varbind_list_free(&m_stat->invb);
+      return ERR_ARG;
+    }
+    derr = snmp_asn1_dec_oid(p, ofs + 1 + len_octets, len, &oid);
+    if (derr != ERR_OK)
+    {
+      /* can't decode object name */
+      snmp_inc_snmpinasnparseerrs();
+      /* free varbinds (if available) */
+      snmp_varbind_list_free(&m_stat->invb);
+      return ERR_ARG;
+    }
+    ofs += (1 + len_octets + len);
+    vb_len -= (1 + len_octets + len);
+
+    snmp_asn1_dec_type(p, ofs, &type);
+    derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+    if (derr != ERR_OK)
+    {
+      /* can't decode object value length */
+      snmp_inc_snmpinasnparseerrs();
+      /* free varbinds (if available) */
+      snmp_varbind_list_free(&m_stat->invb);
+      return ERR_ARG;
+    }
+
+    switch (type)
+    {
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG):
+        vb = snmp_varbind_alloc(&oid, type, sizeof(s32_t));
+        if (vb != NULL)
+        {
+          s32_t *vptr = vb->value;
+
+          derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, vptr);
+          snmp_varbind_tail_add(&m_stat->invb, vb);
+        }
+        else
+        {
+          derr = ERR_ARG;
+        }
+        break;
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS):
+        vb = snmp_varbind_alloc(&oid, type, sizeof(u32_t));
+        if (vb != NULL)
+        {
+          u32_t *vptr = vb->value;
+
+          derr = snmp_asn1_dec_u32t(p, ofs + 1 + len_octets, len, vptr);
+          snmp_varbind_tail_add(&m_stat->invb, vb);
+        }
+        else
+        {
+          derr = ERR_ARG;
+        }
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE):
+        vb = snmp_varbind_alloc(&oid, type, len);
+        if (vb != NULL)
+        {
+          derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, vb->value_len, vb->value);
+          snmp_varbind_tail_add(&m_stat->invb, vb);
+        }
+        else
+        {
+          derr = ERR_ARG;
+        }
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL):
+        vb = snmp_varbind_alloc(&oid, type, 0);
+        if (vb != NULL)
+        {
+          snmp_varbind_tail_add(&m_stat->invb, vb);
+          derr = ERR_OK;
+        }
+        else
+        {
+          derr = ERR_ARG;
+        }
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID):
+        derr = snmp_asn1_dec_oid(p, ofs + 1 + len_octets, len, &oid_value);
+        if (derr == ERR_OK)
+        {
+          vb = snmp_varbind_alloc(&oid, type, oid_value.len * sizeof(s32_t));
+          if (vb != NULL)
+          {
+            u8_t i = oid_value.len;
+            s32_t *vptr = vb->value;
+
+            while(i > 0)
+            {
+              i--;
+              vptr[i] = oid_value.id[i];
+            }
+            snmp_varbind_tail_add(&m_stat->invb, vb);
+            derr = ERR_OK;
+          }
+          else
+          {
+            derr = ERR_ARG;
+          }
+        }
+        break;
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR):
+        if (len == 4)
+        {
+          /* must be exactly 4 octets! */
+          vb = snmp_varbind_alloc(&oid, type, 4);
+          if (vb != NULL)
+          {
+            derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, vb->value_len, vb->value);
+            snmp_varbind_tail_add(&m_stat->invb, vb);
+          }
+          else
+          {
+            derr = ERR_ARG;
+          }
+        }
+        else
+        {
+          derr = ERR_ARG;
+        }
+        break;
+      default:
+        derr = ERR_ARG;
+        break;
+    }
+    if (derr != ERR_OK)
+    {
+      snmp_inc_snmpinasnparseerrs();
+      /* free varbinds (if available) */
+      snmp_varbind_list_free(&m_stat->invb);
+      return ERR_ARG;
+    }
+    ofs += (1 + len_octets + len);
+    vb_len -= (1 + len_octets + len);
+  }
+
+  if (m_stat->rt == SNMP_ASN1_PDU_SET_REQ)
+  {
+    snmp_add_snmpintotalsetvars(m_stat->invb.count);
+  }
+  else
+  {
+    snmp_add_snmpintotalreqvars(m_stat->invb.count);
+  }
+
+  *ofs_ret = ofs;
+  return ERR_OK;
+}
+
+struct snmp_varbind*
+snmp_varbind_alloc(struct snmp_obj_id *oid, u8_t type, u8_t len)
+{
+  struct snmp_varbind *vb;
+
+  vb = (struct snmp_varbind *)mem_malloc(sizeof(struct snmp_varbind));
+  LWIP_ASSERT("vb != NULL",vb != NULL);
+  if (vb != NULL)
+  {
+    u8_t i;
+
+    vb->next = NULL;
+    vb->prev = NULL;
+    i = oid->len;
+    vb->ident_len = i;
+    if (i > 0)
+    {
+      /* allocate array of s32_t for our object identifier */
+      vb->ident = (s32_t*)mem_malloc(sizeof(s32_t) * i);
+      LWIP_ASSERT("vb->ident != NULL",vb->ident != NULL);
+      if (vb->ident == NULL)
+      {
+        mem_free(vb);
+        return NULL;
+      }
+      while(i > 0)
+      {
+        i--;
+        vb->ident[i] = oid->id[i];
+      }
+    }
+    else
+    {
+      /* i == 0, pass zero length object identifier */
+      vb->ident = NULL;
+    }
+    vb->value_type = type;
+    vb->value_len = len;
+    if (len > 0)
+    {
+      /* allocate raw bytes for our object value */
+      vb->value = mem_malloc(len);
+      LWIP_ASSERT("vb->value != NULL",vb->value != NULL);
+      if (vb->value == NULL)
+      {
+        if (vb->ident != NULL)
+        {
+          mem_free(vb->ident);
+        }
+        mem_free(vb);
+        return NULL;
+      }
+    }
+    else
+    {
+      /* ASN1_NUL type, or zero length ASN1_OC_STR */
+      vb->value = NULL;
+    }
+  }
+  return vb;
+}
+
+void
+snmp_varbind_free(struct snmp_varbind *vb)
+{
+  if (vb->value != NULL )
+  {
+    mem_free(vb->value);
+  }
+  if (vb->ident != NULL )
+  {
+    mem_free(vb->ident);
+  }
+  mem_free(vb);
+}
+
+void
+snmp_varbind_list_free(struct snmp_varbind_root *root)
+{
+  struct snmp_varbind *vb, *prev;
+
+  vb = root->tail;
+  while ( vb != NULL )
+  {
+    prev = vb->prev;
+    snmp_varbind_free(vb);
+    vb = prev;
+  }
+  root->count = 0;
+  root->head = NULL;
+  root->tail = NULL;
+}
+
+void
+snmp_varbind_tail_add(struct snmp_varbind_root *root, struct snmp_varbind *vb)
+{
+  if (root->count == 0)
+  {
+    /* add first varbind to list */
+    root->head = vb;
+    root->tail = vb;
+  }
+  else
+  {
+    /* add nth varbind to list tail */
+    root->tail->next = vb;
+    vb->prev = root->tail;
+    root->tail = vb;
+  }
+  root->count += 1;
+}
+
+struct snmp_varbind*
+snmp_varbind_tail_remove(struct snmp_varbind_root *root)
+{
+  struct snmp_varbind* vb;
+
+  if (root->count > 0)
+  {
+    /* remove tail varbind */
+    vb = root->tail;
+    root->tail = vb->prev;
+    vb->prev->next = NULL;
+    root->count -= 1;
+  }
+  else
+  {
+    /* nothing to remove */
+    vb = NULL;
+  }
+  return vb;
+}
+
+#endif /* LWIP_SNMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/snmp/msg_out.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/snmp/msg_out.c
new file mode 100644
index 0000000..0da70de
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/snmp/msg_out.c
@@ -0,0 +1,687 @@
+/**
+ * @file
+ * SNMP output message processing (RFC1157).
+ *
+ * Output responses and traps are build in two passes:
+ *
+ * Pass 0: iterate over the output message backwards to determine encoding lengths
+ * Pass 1: the actual forward encoding of internal form into ASN1
+ *
+ * The single-pass encoding method described by Comer & Stevens
+ * requires extra buffer space and copying for reversal of the packet.
+ * The buffer requirement can be prohibitively large for big payloads
+ * (>= 484) therefore we use the two encoding passes.
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP
+#include "arch/cc.h"
+#include "lwip/udp.h"
+#include "lwip/netif.h"
+
+#include "lwip/snmp.h"
+#include "lwip/snmp_asn1.h"
+#include "lwip/snmp_msg.h"
+
+struct snmp_trap_dst
+{
+  /* destination IP address in network order */
+  struct ip_addr dip;
+  /* set to 0 when disabled, >0 when enabled */
+  u8_t enable;
+};
+#if (SNMP_TRAP_DESTINATIONS == 0)
+#error "need at least one trap destination"
+#endif
+struct snmp_trap_dst trap_dst[SNMP_TRAP_DESTINATIONS];
+
+/** TRAP message structure */
+struct snmp_msg_trap trap_msg;
+
+static u16_t snmp_resp_header_sum(struct snmp_msg_pstat *m_stat, u16_t vb_len);
+static u16_t snmp_trap_header_sum(struct snmp_msg_trap *m_trap, u16_t vb_len);
+static u16_t snmp_varbind_list_sum(struct snmp_varbind_root *root);
+
+static u16_t snmp_resp_header_enc(struct snmp_msg_pstat *m_stat, struct pbuf *p);
+static u16_t snmp_trap_header_enc(struct snmp_msg_trap *m_trap, struct pbuf *p);
+static u16_t snmp_varbind_list_enc(struct snmp_varbind_root *root, struct pbuf *p, u16_t ofs);
+
+/**
+ * Sets enable switch for this trap destination.
+ * @param dst_idx index in 0 .. SNMP_TRAP_DESTINATIONS-1
+ * @param enable switch if 0 destination is disabled >0 enabled.
+ */
+void
+snmp_trap_dst_enable(u8_t dst_idx, u8_t enable)
+{
+  if (dst_idx < SNMP_TRAP_DESTINATIONS)
+  {
+    trap_dst[dst_idx].enable = enable;
+  }
+}
+
+/**
+ * Sets IPv4 address for this trap destination.
+ * @param dst_idx index in 0 .. SNMP_TRAP_DESTINATIONS-1
+ * @param dst IPv4 address in host order.
+ */
+void
+snmp_trap_dst_ip_set(u8_t dst_idx, struct ip_addr *dst)
+{
+  if (dst_idx < SNMP_TRAP_DESTINATIONS)
+  {
+    trap_dst[dst_idx].dip.addr = htonl(dst->addr);
+  }
+}
+
+/**
+ * Sends a 'getresponse' message to the request originator.
+ *
+ * @param m_stat points to the current message request state source
+ * @return ERR_OK when success, ERR_MEM if we're out of memory
+ *
+ * @note the caller is responsible for filling in outvb in the m_stat
+ * and provide error-status and index (except for tooBig errors) ...
+ */
+err_t
+snmp_send_response(struct snmp_msg_pstat *m_stat)
+{
+  struct snmp_varbind_root emptyvb = {NULL, NULL, 0, 0, 0};
+  struct pbuf *p;
+  u16_t tot_len;
+  err_t err;
+
+  /* pass 0, calculate length fields */
+  tot_len = snmp_varbind_list_sum(&m_stat->outvb);
+  tot_len = snmp_resp_header_sum(m_stat, tot_len);
+
+  /* try allocating pbuf(s) for complete response */
+  p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL);
+  if (p == NULL)
+  {
+    LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() tooBig\n"));
+
+    /* can't construct reply, return error-status tooBig */
+    m_stat->error_status = SNMP_ES_TOOBIG;
+    m_stat->error_index = 0;
+    /* pass 0, recalculate lengths, for empty varbind-list */
+    tot_len = snmp_varbind_list_sum(&emptyvb);
+    tot_len = snmp_resp_header_sum(m_stat, tot_len);
+    /* retry allocation once for header and empty varbind-list */
+    p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL);
+  }
+  if (p != NULL)
+  {
+    /* first pbuf alloc try or retry alloc success */
+    u16_t ofs;
+
+    LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() p != NULL\n"));
+
+    /* pass 1, size error, encode packet ino the pbuf(s) */
+    ofs = snmp_resp_header_enc(m_stat, p);
+    if (m_stat->error_status == SNMP_ES_TOOBIG)
+    {
+      snmp_varbind_list_enc(&emptyvb, p, ofs);
+    }
+    else
+    {
+      snmp_varbind_list_enc(&m_stat->outvb, p, ofs);
+    }
+
+    switch (m_stat->error_status)
+    {
+      case SNMP_ES_TOOBIG:
+        snmp_inc_snmpouttoobigs();
+        break;
+      case SNMP_ES_NOSUCHNAME:
+        snmp_inc_snmpoutnosuchnames();
+        break;
+      case SNMP_ES_BADVALUE:
+        snmp_inc_snmpoutbadvalues();
+        break;
+      case SNMP_ES_GENERROR:
+        snmp_inc_snmpoutgenerrs();
+        break;
+    }
+    snmp_inc_snmpoutgetresponses();
+    snmp_inc_snmpoutpkts();
+
+    /** @todo do we need separate rx and tx pcbs for threaded case? */
+    /** connect to the originating source */
+    udp_connect(m_stat->pcb, &m_stat->sip, m_stat->sp);
+    err = udp_send(m_stat->pcb, p);
+    if (err == ERR_MEM)
+    {
+      /** @todo release some memory, retry and return tooBig? tooMuchHassle? */
+      err = ERR_MEM;
+    }
+    else
+    {
+      err = ERR_OK;
+    }
+    /** disassociate remote address and port with this pcb */
+    udp_disconnect(m_stat->pcb);
+
+    pbuf_free(p);
+    LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() done\n"));
+    return err;
+  }
+  else
+  {
+    /* first pbuf alloc try or retry alloc failed
+       very low on memory, couldn't return tooBig */
+    return ERR_MEM;
+  }
+}
+
+
+/**
+ * Sends an generic or enterprise specific trap message.
+ *
+ * @param generic_trap is the trap code
+ * @param eoid points to enterprise object identifier
+ * @param specific_trap used for enterprise traps when generic_trap == 6
+ * @return ERR_OK when success, ERR_MEM if we're out of memory
+ *
+ * @note the caller is responsible for filling in outvb in the trap_msg
+ * @note the use of the enterpise identifier field
+ * is per RFC1215.
+ * Use .iso.org.dod.internet.mgmt.mib-2.snmp for generic traps
+ * and .iso.org.dod.internet.private.enterprises.yourenterprise
+ * (sysObjectID) for specific traps.
+ */
+err_t
+snmp_send_trap(s8_t generic_trap, struct snmp_obj_id *eoid, s32_t specific_trap)
+{
+  struct snmp_trap_dst *td;
+  struct netif *dst_if;
+  struct ip_addr dst_ip;
+  struct pbuf *p;
+  u16_t i,tot_len;
+
+  for (i=0, td = &trap_dst[0]; ienable != 0) && (td->dip.addr != 0))
+    {
+      /* network order trap destination */
+      trap_msg.dip.addr = td->dip.addr;
+      /* lookup current source address for this dst */
+      dst_if = ip_route(&td->dip);
+      dst_ip.addr = ntohl(dst_if->ip_addr.addr);
+      trap_msg.sip_raw[0] = dst_ip.addr >> 24;
+      trap_msg.sip_raw[1] = dst_ip.addr >> 16;
+      trap_msg.sip_raw[2] = dst_ip.addr >> 8;
+      trap_msg.sip_raw[3] = dst_ip.addr;
+      trap_msg.gen_trap = generic_trap;
+      trap_msg.spc_trap = specific_trap;
+      if (generic_trap == SNMP_GENTRAP_ENTERPRISESPC)
+      {
+        /* enterprise-Specific trap */
+        trap_msg.enterprise = eoid;
+      }
+      else
+      {
+        /* generic (MIB-II) trap */
+        snmp_get_snmpgrpid_ptr(&trap_msg.enterprise);
+      }
+      snmp_get_sysuptime(&trap_msg.ts);
+
+      /* pass 0, calculate length fields */
+      tot_len = snmp_varbind_list_sum(&trap_msg.outvb);
+      tot_len = snmp_trap_header_sum(&trap_msg, tot_len);
+
+      /* allocate pbuf(s) */
+      p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL);
+      if (p != NULL)
+      {
+        u16_t ofs;
+
+        /* pass 1, encode packet ino the pbuf(s) */
+        ofs = snmp_trap_header_enc(&trap_msg, p);
+        snmp_varbind_list_enc(&trap_msg.outvb, p, ofs);
+
+        snmp_inc_snmpouttraps();
+        snmp_inc_snmpoutpkts();
+
+        /** connect to the TRAP destination */
+        udp_connect(trap_msg.pcb, &trap_msg.dip, SNMP_TRAP_PORT);
+        udp_send(trap_msg.pcb, p);
+        /** disassociate remote address and port with this pcb */
+        udp_disconnect(trap_msg.pcb);
+
+        pbuf_free(p);
+      }
+      else
+      {
+        return ERR_MEM;
+      }
+    }
+  }
+  return ERR_OK;
+}
+
+void
+snmp_coldstart_trap(void)
+{
+  trap_msg.outvb.head = NULL;
+  trap_msg.outvb.tail = NULL;
+  trap_msg.outvb.count = 0;
+  snmp_send_trap(SNMP_GENTRAP_COLDSTART, NULL, 0);
+}
+
+void
+snmp_authfail_trap(void)
+{
+  u8_t enable;
+  snmp_get_snmpenableauthentraps(&enable);
+  if (enable == 1)
+  {
+    trap_msg.outvb.head = NULL;
+    trap_msg.outvb.tail = NULL;
+    trap_msg.outvb.count = 0;
+    snmp_send_trap(SNMP_GENTRAP_AUTHFAIL, NULL, 0);
+  }
+}
+
+/**
+ * Sums response header field lengths from tail to head and
+ * returns resp_header_lengths for second encoding pass.
+ *
+ * @param vb_len varbind-list length
+ * @param rhl points to returned header lengths
+ * @return the required lenght for encoding the response header
+ */
+static u16_t
+snmp_resp_header_sum(struct snmp_msg_pstat *m_stat, u16_t vb_len)
+{
+  u16_t tot_len;
+  struct snmp_resp_header_lengths *rhl;
+
+  rhl = &m_stat->rhl;
+  tot_len = vb_len;
+  snmp_asn1_enc_s32t_cnt(m_stat->error_index, &rhl->erridxlen);
+  snmp_asn1_enc_length_cnt(rhl->erridxlen, &rhl->erridxlenlen);
+  tot_len += 1 + rhl->erridxlenlen + rhl->erridxlen;
+
+  snmp_asn1_enc_s32t_cnt(m_stat->error_status, &rhl->errstatlen);
+  snmp_asn1_enc_length_cnt(rhl->errstatlen, &rhl->errstatlenlen);
+  tot_len += 1 + rhl->errstatlenlen + rhl->errstatlen;
+
+  snmp_asn1_enc_s32t_cnt(m_stat->rid, &rhl->ridlen);
+  snmp_asn1_enc_length_cnt(rhl->ridlen, &rhl->ridlenlen);
+  tot_len += 1 + rhl->ridlenlen + rhl->ridlen;
+
+  rhl->pdulen = tot_len;
+  snmp_asn1_enc_length_cnt(rhl->pdulen, &rhl->pdulenlen);
+  tot_len += 1 + rhl->pdulenlen;
+
+  rhl->comlen = m_stat->com_strlen;
+  snmp_asn1_enc_length_cnt(rhl->comlen, &rhl->comlenlen);
+  tot_len += 1 + rhl->comlenlen + rhl->comlen;
+
+  snmp_asn1_enc_s32t_cnt(snmp_version, &rhl->verlen);
+  snmp_asn1_enc_length_cnt(rhl->verlen, &rhl->verlenlen);
+  tot_len += 1 + rhl->verlen + rhl->verlenlen;
+
+  rhl->seqlen = tot_len;
+  snmp_asn1_enc_length_cnt(rhl->seqlen, &rhl->seqlenlen);
+  tot_len += 1 + rhl->seqlenlen;
+
+  return tot_len;
+}
+
+/**
+ * Sums trap header field lengths from tail to head and
+ * returns trap_header_lengths for second encoding pass.
+ *
+ * @param vb_len varbind-list length
+ * @param thl points to returned header lengths
+ * @return the required lenght for encoding the trap header
+ */
+static u16_t
+snmp_trap_header_sum(struct snmp_msg_trap *m_trap, u16_t vb_len)
+{
+  u16_t tot_len;
+  struct snmp_trap_header_lengths *thl;
+
+  thl = &m_trap->thl;
+  tot_len = vb_len;
+
+  snmp_asn1_enc_u32t_cnt(m_trap->ts, &thl->tslen);
+  snmp_asn1_enc_length_cnt(thl->tslen, &thl->tslenlen);
+  tot_len += 1 + thl->tslen + thl->tslenlen;
+
+  snmp_asn1_enc_s32t_cnt(m_trap->spc_trap, &thl->strplen);
+  snmp_asn1_enc_length_cnt(thl->strplen, &thl->strplenlen);
+  tot_len += 1 + thl->strplen + thl->strplenlen;
+
+  snmp_asn1_enc_s32t_cnt(m_trap->gen_trap, &thl->gtrplen);
+  snmp_asn1_enc_length_cnt(thl->gtrplen, &thl->gtrplenlen);
+  tot_len += 1 + thl->gtrplen + thl->gtrplenlen;
+
+  thl->aaddrlen = 4;
+  snmp_asn1_enc_length_cnt(thl->aaddrlen, &thl->aaddrlenlen);
+  tot_len += 1 + thl->aaddrlen + thl->aaddrlenlen;
+
+  snmp_asn1_enc_oid_cnt(m_trap->enterprise->len, &m_trap->enterprise->id[0], &thl->eidlen);
+  snmp_asn1_enc_length_cnt(thl->eidlen, &thl->eidlenlen);
+  tot_len += 1 + thl->eidlen + thl->eidlenlen;
+
+  thl->pdulen = tot_len;
+  snmp_asn1_enc_length_cnt(thl->pdulen, &thl->pdulenlen);
+  tot_len += 1 + thl->pdulenlen;
+
+  thl->comlen = sizeof(snmp_publiccommunity) - 1;
+  snmp_asn1_enc_length_cnt(thl->comlen, &thl->comlenlen);
+  tot_len += 1 + thl->comlenlen + thl->comlen;
+
+  snmp_asn1_enc_s32t_cnt(snmp_version, &thl->verlen);
+  snmp_asn1_enc_length_cnt(thl->verlen, &thl->verlenlen);
+  tot_len += 1 + thl->verlen + thl->verlenlen;
+
+  thl->seqlen = tot_len;
+  snmp_asn1_enc_length_cnt(thl->seqlen, &thl->seqlenlen);
+  tot_len += 1 + thl->seqlenlen;
+
+  return tot_len;
+}
+
+/**
+ * Sums varbind lengths from tail to head and
+ * annotates lengths in varbind for second encoding pass.
+ *
+ * @param root points to the root of the variable binding list
+ * @return the required lenght for encoding the variable bindings
+ */
+static u16_t
+snmp_varbind_list_sum(struct snmp_varbind_root *root)
+{
+  struct snmp_varbind *vb;
+  u32_t *uint_ptr;
+  s32_t *sint_ptr;
+  u16_t tot_len;
+
+  tot_len = 0;
+  vb = root->tail;
+  while ( vb != NULL )
+  {
+    /* encoded value lenght depends on type */
+    switch (vb->value_type)
+    {
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG):
+        sint_ptr = vb->value;
+        snmp_asn1_enc_s32t_cnt(*sint_ptr, &vb->vlen);
+        break;
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS):
+        uint_ptr = vb->value;
+        snmp_asn1_enc_u32t_cnt(*uint_ptr, &vb->vlen);
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR):
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE):
+        vb->vlen = vb->value_len;
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID):
+        sint_ptr = vb->value;
+        snmp_asn1_enc_oid_cnt(vb->value_len / sizeof(s32_t), sint_ptr, &vb->vlen);
+        break;
+      default:
+        /* unsupported type */
+        vb->vlen = 0;
+        break;
+    };
+    /* encoding length of value length field */
+    snmp_asn1_enc_length_cnt(vb->vlen, &vb->vlenlen);
+    snmp_asn1_enc_oid_cnt(vb->ident_len, vb->ident, &vb->olen);
+    snmp_asn1_enc_length_cnt(vb->olen, &vb->olenlen);
+
+    vb->seqlen = 1 + vb->vlenlen + vb->vlen;
+    vb->seqlen += 1 + vb->olenlen + vb->olen;
+    snmp_asn1_enc_length_cnt(vb->seqlen, &vb->seqlenlen);
+
+    /* varbind seq */
+    tot_len += 1 + vb->seqlenlen + vb->seqlen;
+
+    vb = vb->prev;
+  }
+
+  /* varbind-list seq */
+  root->seqlen = tot_len;
+  snmp_asn1_enc_length_cnt(root->seqlen, &root->seqlenlen);
+  tot_len += 1 + root->seqlenlen;
+
+  return tot_len;
+}
+
+/**
+ * Encodes response header from head to tail.
+ */
+static u16_t
+snmp_resp_header_enc(struct snmp_msg_pstat *m_stat, struct pbuf *p)
+{
+  u16_t ofs;
+
+  ofs = 0;
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.seqlen);
+  ofs += m_stat->rhl.seqlenlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.verlen);
+  ofs += m_stat->rhl.verlenlen;
+  snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.verlen, snmp_version);
+  ofs += m_stat->rhl.verlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.comlen);
+  ofs += m_stat->rhl.comlenlen;
+  snmp_asn1_enc_raw(p, ofs, m_stat->rhl.comlen, m_stat->community);
+  ofs += m_stat->rhl.comlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_RESP));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.pdulen);
+  ofs += m_stat->rhl.pdulenlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.ridlen);
+  ofs += m_stat->rhl.ridlenlen;
+  snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.ridlen, m_stat->rid);
+  ofs += m_stat->rhl.ridlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.errstatlen);
+  ofs += m_stat->rhl.errstatlenlen;
+  snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.errstatlen, m_stat->error_status);
+  ofs += m_stat->rhl.errstatlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.erridxlen);
+  ofs += m_stat->rhl.erridxlenlen;
+  snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.erridxlen, m_stat->error_index);
+  ofs += m_stat->rhl.erridxlen;
+
+  return ofs;
+}
+
+/**
+ * Encodes trap header from head to tail.
+ */
+static u16_t
+snmp_trap_header_enc(struct snmp_msg_trap *m_trap, struct pbuf *p)
+{
+  u16_t ofs;
+
+  ofs = 0;
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.seqlen);
+  ofs += m_trap->thl.seqlenlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.verlen);
+  ofs += m_trap->thl.verlenlen;
+  snmp_asn1_enc_s32t(p, ofs, m_trap->thl.verlen, snmp_version);
+  ofs += m_trap->thl.verlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.comlen);
+  ofs += m_trap->thl.comlenlen;
+  snmp_asn1_enc_raw(p, ofs, m_trap->thl.comlen, (u8_t *)&snmp_publiccommunity[0]);
+  ofs += m_trap->thl.comlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_TRAP));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.pdulen);
+  ofs += m_trap->thl.pdulenlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.eidlen);
+  ofs += m_trap->thl.eidlenlen;
+  snmp_asn1_enc_oid(p, ofs, m_trap->enterprise->len, &m_trap->enterprise->id[0]);
+  ofs += m_trap->thl.eidlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.aaddrlen);
+  ofs += m_trap->thl.aaddrlenlen;
+  snmp_asn1_enc_raw(p, ofs, m_trap->thl.aaddrlen, &m_trap->sip_raw[0]);
+  ofs += m_trap->thl.aaddrlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.gtrplen);
+  ofs += m_trap->thl.gtrplenlen;
+  snmp_asn1_enc_u32t(p, ofs, m_trap->thl.gtrplen, m_trap->gen_trap);
+  ofs += m_trap->thl.gtrplen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.strplen);
+  ofs += m_trap->thl.strplenlen;
+  snmp_asn1_enc_u32t(p, ofs, m_trap->thl.strplen, m_trap->spc_trap);
+  ofs += m_trap->thl.strplen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.tslen);
+  ofs += m_trap->thl.tslenlen;
+  snmp_asn1_enc_u32t(p, ofs, m_trap->thl.tslen, m_trap->ts);
+  ofs += m_trap->thl.tslen;
+
+  return ofs;
+}
+
+/**
+ * Encodes varbind list from head to tail.
+ */
+static u16_t
+snmp_varbind_list_enc(struct snmp_varbind_root *root, struct pbuf *p, u16_t ofs)
+{
+  struct snmp_varbind *vb;
+  s32_t *sint_ptr;
+  u32_t *uint_ptr;
+  u8_t *raw_ptr;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, root->seqlen);
+  ofs += root->seqlenlen;
+
+  vb = root->head;
+  while ( vb != NULL )
+  {
+    snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ));
+    ofs += 1;
+    snmp_asn1_enc_length(p, ofs, vb->seqlen);
+    ofs += vb->seqlenlen;
+
+    snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID));
+    ofs += 1;
+    snmp_asn1_enc_length(p, ofs, vb->olen);
+    ofs += vb->olenlen;
+    snmp_asn1_enc_oid(p, ofs, vb->ident_len, &vb->ident[0]);
+    ofs += vb->olen;
+
+    snmp_asn1_enc_type(p, ofs, vb->value_type);
+    ofs += 1;
+    snmp_asn1_enc_length(p, ofs, vb->vlen);
+    ofs += vb->vlenlen;
+
+    switch (vb->value_type)
+    {
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG):
+        sint_ptr = vb->value;
+        snmp_asn1_enc_s32t(p, ofs, vb->vlen, *sint_ptr);
+        break;
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS):
+        uint_ptr = vb->value;
+        snmp_asn1_enc_u32t(p, ofs, vb->vlen, *uint_ptr);
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE):
+        raw_ptr = vb->value;
+        snmp_asn1_enc_raw(p, ofs, vb->vlen, raw_ptr);
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL):
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID):
+        sint_ptr = vb->value;
+        snmp_asn1_enc_oid(p, ofs, vb->value_len / sizeof(s32_t), sint_ptr);
+        break;
+      default:
+        /* unsupported type */
+        break;
+    };
+    ofs += vb->vlen;
+    vb = vb->next;
+  }
+  return ofs;
+}
+
+#endif /* LWIP_SNMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/stats.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/stats.c
new file mode 100644
index 0000000..e3cf4a3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/stats.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include 
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+
+
+#if LWIP_STATS
+struct stats_ lwip_stats;
+
+void
+stats_init(void)
+{
+  memset(&lwip_stats, 0, sizeof(struct stats_));
+}
+#if LWIP_STATS_DISPLAY
+void
+stats_display_proto(struct stats_proto *proto, char *name)
+{
+  LWIP_PLATFORM_DIAG(("\n%s\n\t", name));
+  LWIP_PLATFORM_DIAG(("xmit: %"S16_F"\n\t", proto->xmit)); 
+  LWIP_PLATFORM_DIAG(("rexmit: %"S16_F"\n\t", proto->rexmit)); 
+  LWIP_PLATFORM_DIAG(("recv: %"S16_F"\n\t", proto->recv)); 
+  LWIP_PLATFORM_DIAG(("fw: %"S16_F"\n\t", proto->fw)); 
+  LWIP_PLATFORM_DIAG(("drop: %"S16_F"\n\t", proto->drop)); 
+  LWIP_PLATFORM_DIAG(("chkerr: %"S16_F"\n\t", proto->chkerr)); 
+  LWIP_PLATFORM_DIAG(("lenerr: %"S16_F"\n\t", proto->lenerr)); 
+  LWIP_PLATFORM_DIAG(("memerr: %"S16_F"\n\t", proto->memerr)); 
+  LWIP_PLATFORM_DIAG(("rterr: %"S16_F"\n\t", proto->rterr)); 
+  LWIP_PLATFORM_DIAG(("proterr: %"S16_F"\n\t", proto->proterr)); 
+  LWIP_PLATFORM_DIAG(("opterr: %"S16_F"\n\t", proto->opterr)); 
+  LWIP_PLATFORM_DIAG(("err: %"S16_F"\n\t", proto->err)); 
+  LWIP_PLATFORM_DIAG(("cachehit: %"S16_F"\n", proto->cachehit)); 
+}
+
+void
+stats_display_pbuf(struct stats_pbuf *pbuf)
+{
+  LWIP_PLATFORM_DIAG(("\nPBUF\n\t"));
+  LWIP_PLATFORM_DIAG(("avail: %"S16_F"\n\t", pbuf->avail)); 
+  LWIP_PLATFORM_DIAG(("used: %"S16_F"\n\t", pbuf->used)); 
+  LWIP_PLATFORM_DIAG(("max: %"S16_F"\n\t", pbuf->max)); 
+  LWIP_PLATFORM_DIAG(("err: %"S16_F"\n\t", pbuf->err)); 
+  LWIP_PLATFORM_DIAG(("alloc_locked: %"S16_F"\n\t", pbuf->alloc_locked)); 
+  LWIP_PLATFORM_DIAG(("refresh_locked: %"S16_F"\n", pbuf->refresh_locked)); 
+}
+
+void
+stats_display_mem(struct stats_mem *mem, char *name)
+{
+  LWIP_PLATFORM_DIAG(("\n MEM %s\n\t", name));
+  LWIP_PLATFORM_DIAG(("avail: %"MEM_SIZE_F"\n\t", mem->avail)); 
+  LWIP_PLATFORM_DIAG(("used: %"MEM_SIZE_F"\n\t", mem->used)); 
+  LWIP_PLATFORM_DIAG(("max: %"MEM_SIZE_F"\n\t", mem->max)); 
+  LWIP_PLATFORM_DIAG(("err: %"MEM_SIZE_F"\n", mem->err));
+  
+}
+
+void
+stats_display(void)
+{
+  s16_t i;
+  char * memp_names[] = {"PBUF", "RAW_PCB", "UDP_PCB", "TCP_PCB", "TCP_PCB_LISTEN",
+        "TCP_SEG", "NETBUF", "NETCONN", "API_MSG", "TCP_MSG", "TIMEOUT"};
+  stats_display_proto(&lwip_stats.link, "LINK");
+  stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG");
+  stats_display_proto(&lwip_stats.ip, "IP");
+  stats_display_proto(&lwip_stats.icmp, "ICMP");
+  stats_display_proto(&lwip_stats.udp, "UDP");
+  stats_display_proto(&lwip_stats.tcp, "TCP");
+  stats_display_pbuf(&lwip_stats.pbuf);
+  stats_display_mem(&lwip_stats.mem, "HEAP");
+  for (i = 0; i < MEMP_MAX; i++) {
+    stats_display_mem(&lwip_stats.memp[i], memp_names[i]);
+  }
+  
+}
+#endif /* LWIP_STATS_DISPLAY */
+#endif /* LWIP_STATS */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/sys.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/sys.c
new file mode 100644
index 0000000..2ecb880
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/sys.c
@@ -0,0 +1,294 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/sys.h"
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/memp.h"
+
+#if (NO_SYS == 0)
+
+struct sswt_cb
+{
+    s16_t timeflag;
+    sys_sem_t *psem;
+};
+
+
+
+void
+sys_mbox_fetch(sys_mbox_t mbox, void **msg)
+{
+  u32_t time;
+  struct sys_timeouts *timeouts;
+  struct sys_timeo *tmptimeout;
+  sys_timeout_handler h;
+  void *arg;
+
+
+ again:
+  timeouts = sys_arch_timeouts();
+
+  if (!timeouts || !timeouts->next) {
+    sys_arch_mbox_fetch(mbox, msg, 0);
+  } else {
+    if (timeouts->next->time > 0) {
+      time = sys_arch_mbox_fetch(mbox, msg, timeouts->next->time);
+    } else {
+      time = SYS_ARCH_TIMEOUT;
+    }
+
+    if (time == SYS_ARCH_TIMEOUT) {
+      /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message
+   could be fetched. We should now call the timeout handler and
+   deallocate the memory allocated for the timeout. */
+      tmptimeout = timeouts->next;
+      timeouts->next = tmptimeout->next;
+      h = tmptimeout->h;
+      arg = tmptimeout->arg;
+      memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
+      if (h != NULL) {
+        LWIP_DEBUGF(SYS_DEBUG, ("smf calling h=%p(%p)\n", (void *)h, (void *)arg));
+      	h(arg);
+      }
+
+      /* We try again to fetch a message from the mbox. */
+      goto again;
+    } else {
+      /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout
+   occured. The time variable is set to the number of
+   milliseconds we waited for the message. */
+      if (time <= timeouts->next->time) {
+  timeouts->next->time -= time;
+      } else {
+  timeouts->next->time = 0;
+      }
+    }
+
+  }
+}
+
+void
+sys_sem_wait(sys_sem_t sem)
+{
+  u32_t time;
+  struct sys_timeouts *timeouts;
+  struct sys_timeo *tmptimeout;
+  sys_timeout_handler h;
+  void *arg;
+
+  /*  while (sys_arch_sem_wait(sem, 1000) == 0);
+      return;*/
+
+ again:
+
+  timeouts = sys_arch_timeouts();
+
+  if (!timeouts || !timeouts->next) {
+    sys_arch_sem_wait(sem, 0);
+  } else {
+    if (timeouts->next->time > 0) {
+      time = sys_arch_sem_wait(sem, timeouts->next->time);
+    } else {
+      time = SYS_ARCH_TIMEOUT;
+    }
+
+    if (time == SYS_ARCH_TIMEOUT) {
+      /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message
+   could be fetched. We should now call the timeout handler and
+   deallocate the memory allocated for the timeout. */
+      tmptimeout = timeouts->next;
+      timeouts->next = tmptimeout->next;
+      h = tmptimeout->h;
+      arg = tmptimeout->arg;
+      memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
+      if (h != NULL) {
+        LWIP_DEBUGF(SYS_DEBUG, ("ssw h=%p(%p)\n", (void *)h, (void *)arg));
+        h(arg);
+      }
+
+
+      /* We try again to fetch a message from the mbox. */
+      goto again;
+    } else {
+      /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout
+   occured. The time variable is set to the number of
+   milliseconds we waited for the message. */
+      if (time <= timeouts->next->time) {
+  timeouts->next->time -= time;
+      } else {
+  timeouts->next->time = 0;
+      }
+    }
+
+  }
+}
+
+void
+sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg)
+{
+  struct sys_timeouts *timeouts;
+  struct sys_timeo *timeout, *t;
+
+  timeout = memp_malloc(MEMP_SYS_TIMEOUT);
+  if (timeout == NULL) {
+    return;
+  }
+  timeout->next = NULL;
+  timeout->h = h;
+  timeout->arg = arg;
+  timeout->time = msecs;
+
+  timeouts = sys_arch_timeouts();
+
+  LWIP_DEBUGF(SYS_DEBUG, ("sys_timeout: %p msecs=%"U32_F" h=%p arg=%p\n",
+    (void *)timeout, msecs, (void *)h, (void *)arg));
+
+  LWIP_ASSERT("sys_timeout: timeouts != NULL", timeouts != NULL);
+
+  if (timeouts->next == NULL) {
+    timeouts->next = timeout;
+    return;
+  }
+
+  if (timeouts->next->time > msecs) {
+    timeouts->next->time -= msecs;
+    timeout->next = timeouts->next;
+    timeouts->next = timeout;
+  } else {
+    for(t = timeouts->next; t != NULL; t = t->next) {
+      timeout->time -= t->time;
+      if (t->next == NULL || t->next->time > timeout->time) {
+        if (t->next != NULL) {
+          t->next->time -= timeout->time;
+        }
+        timeout->next = t->next;
+        t->next = timeout;
+        break;
+      }
+    }
+  }
+
+}
+
+/* Go through timeout list (for this task only) and remove the first matching entry,
+   even though the timeout has not triggered yet.
+*/
+
+void
+sys_untimeout(sys_timeout_handler h, void *arg)
+{
+    struct sys_timeouts *timeouts;
+    struct sys_timeo *prev_t, *t;
+
+    timeouts = sys_arch_timeouts();
+
+    if (timeouts->next == NULL)
+        return;
+
+    for (t = timeouts->next, prev_t = NULL; t != NULL; prev_t = t, t = t->next)
+    {
+        if ((t->h == h) && (t->arg == arg))
+        {
+            /* We have a match */
+            /* Unlink from previous in list */
+            if (prev_t == NULL)
+                timeouts->next = t->next;
+            else
+                prev_t->next = t->next;
+            /* If not the last one, add time of this one back to next */
+            if (t->next != NULL)
+                t->next->time += t->time;
+            memp_free(MEMP_SYS_TIMEOUT, t);
+            return;
+        }
+    }
+    return;
+}
+
+
+
+
+
+static void
+sswt_handler(void *arg)
+{
+    struct sswt_cb *sswt_cb = (struct sswt_cb *) arg;
+
+    /* Timeout. Set flag to TRUE and signal semaphore */
+    sswt_cb->timeflag = 1;
+    sys_sem_signal(*(sswt_cb->psem));
+}
+
+/* Wait for a semaphore with timeout (specified in ms) */
+/* timeout = 0: wait forever */
+/* Returns 0 on timeout. 1 otherwise */
+
+int
+sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout)
+{
+    struct sswt_cb sswt_cb;
+
+    sswt_cb.psem = &sem;
+    sswt_cb.timeflag = 0;
+
+    /* If timeout is zero, then just wait forever */
+    if (timeout > 0)
+        /* Create a timer and pass it the address of our flag */
+        sys_timeout(timeout, sswt_handler, &sswt_cb);
+    sys_sem_wait(sem);
+    /* Was it a timeout? */
+    if (sswt_cb.timeflag)
+    {
+        /* timeout */
+        return 0;
+    } else {
+        /* Not a timeout. Remove timeout entry */
+        sys_untimeout(sswt_handler, &sswt_cb);
+        return 1;
+    }
+
+}
+
+
+void
+sys_msleep(u32_t ms)
+{
+  sys_sem_t delaysem = sys_sem_new(0);
+
+  sys_sem_wait_timeout(delaysem, ms);
+
+  sys_sem_free(delaysem);
+}
+
+
+#endif /* NO_SYS */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/tcp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/tcp.c
new file mode 100644
index 0000000..5b69ee7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/tcp.c
@@ -0,0 +1,1182 @@
+/**
+ * @file
+ *
+ * Transmission Control Protocol for IP
+ *
+ * This file contains common functions for the TCP implementation, such as functinos
+ * for manipulating the data structures and the TCP timer functions. TCP functions
+ * related to input and output is found in tcp_in.c and tcp_out.c respectively.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include 
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/snmp.h"
+
+#include "lwip/tcp.h"
+#if LWIP_TCP
+
+/* Incremented every coarse grained timer shot (typically every 500 ms). */
+u32_t tcp_ticks;
+const u8_t tcp_backoff[13] =
+    { 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7};
+
+/* The TCP PCB lists. */
+
+/** List of all TCP PCBs in LISTEN state */
+union tcp_listen_pcbs_t tcp_listen_pcbs;
+/** List of all TCP PCBs that are in a state in which
+ * they accept or send data. */
+struct tcp_pcb *tcp_active_pcbs;  
+/** List of all TCP PCBs in TIME-WAIT state */
+struct tcp_pcb *tcp_tw_pcbs;
+
+struct tcp_pcb *tcp_tmp_pcb;
+
+static u8_t tcp_timer;
+static u16_t tcp_new_port(void);
+
+/**
+ * Initializes the TCP layer.
+ */
+void
+tcp_init(void)
+{
+  /* Clear globals. */
+  tcp_listen_pcbs.listen_pcbs = NULL;
+  tcp_active_pcbs = NULL;
+  tcp_tw_pcbs = NULL;
+  tcp_tmp_pcb = NULL;
+  
+  /* initialize timer */
+  tcp_ticks = 0;
+  tcp_timer = 0;
+  
+}
+
+/**
+ * Called periodically to dispatch TCP timers.
+ *
+ */
+void
+tcp_tmr(void)
+{
+  /* Call tcp_fasttmr() every 250 ms */
+  tcp_fasttmr();
+
+  if (++tcp_timer & 1) {
+    /* Call tcp_tmr() every 500 ms, i.e., every other timer
+       tcp_tmr() is called. */
+    tcp_slowtmr();
+  }
+}
+
+/**
+ * Closes the connection held by the PCB.
+ *
+ */
+err_t
+tcp_close(struct tcp_pcb *pcb)
+{
+  err_t err;
+
+#if TCP_DEBUG
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in "));
+  tcp_debug_print_state(pcb->state);
+#endif /* TCP_DEBUG */
+
+  switch (pcb->state) {
+  case CLOSED:
+    /* Closing a pcb in the CLOSED state might seem erroneous,
+     * however, it is in this state once allocated and as yet unused
+     * and the user needs some way to free it should the need arise.
+     * Calling tcp_close() with a pcb that has already been closed, (i.e. twice)
+     * or for a pcb that has been used and then entered the CLOSED state 
+     * is erroneous, but this should never happen as the pcb has in those cases
+     * been freed, and so any remaining handles are bogus. */
+    err = ERR_OK;
+    memp_free(MEMP_TCP_PCB, pcb);
+    pcb = NULL;
+    break;
+  case LISTEN:
+    err = ERR_OK;
+    tcp_pcb_remove((struct tcp_pcb **)&tcp_listen_pcbs.pcbs, pcb);
+    memp_free(MEMP_TCP_PCB_LISTEN, pcb);
+    pcb = NULL;
+    break;
+  case SYN_SENT:
+    err = ERR_OK;
+    tcp_pcb_remove(&tcp_active_pcbs, pcb);
+    memp_free(MEMP_TCP_PCB, pcb);
+    pcb = NULL;
+    snmp_inc_tcpattemptfails();
+    break;
+  case SYN_RCVD:
+    err = tcp_send_ctrl(pcb, TCP_FIN);
+    if (err == ERR_OK) {
+      snmp_inc_tcpattemptfails();
+      pcb->state = FIN_WAIT_1;
+    }
+    break;
+  case ESTABLISHED:
+    err = tcp_send_ctrl(pcb, TCP_FIN);
+    if (err == ERR_OK) {
+      snmp_inc_tcpestabresets();
+      pcb->state = FIN_WAIT_1;
+    }
+    break;
+  case CLOSE_WAIT:
+    err = tcp_send_ctrl(pcb, TCP_FIN);
+    if (err == ERR_OK) {
+      snmp_inc_tcpestabresets();
+      pcb->state = LAST_ACK;
+    }
+    break;
+  default:
+    /* Has already been closed, do nothing. */
+    err = ERR_OK;
+    pcb = NULL;
+    break;
+  }
+
+  if (pcb != NULL && err == ERR_OK) {
+    err = tcp_output(pcb);
+  }
+  return err;
+}
+
+/**
+ * Aborts a connection by sending a RST to the remote host and deletes
+ * the local protocol control block. This is done when a connection is
+ * killed because of shortage of memory.
+ *
+ */
+void
+tcp_abort(struct tcp_pcb *pcb)
+{
+  u32_t seqno, ackno;
+  u16_t remote_port, local_port;
+  struct ip_addr remote_ip, local_ip;
+#if LWIP_CALLBACK_API  
+  void (* errf)(void *arg, err_t err);
+#endif /* LWIP_CALLBACK_API */
+  void *errf_arg;
+
+  
+  /* Figure out on which TCP PCB list we are, and remove us. If we
+     are in an active state, call the receive function associated with
+     the PCB with a NULL argument, and send an RST to the remote end. */
+  if (pcb->state == TIME_WAIT) {
+    tcp_pcb_remove(&tcp_tw_pcbs, pcb);
+    memp_free(MEMP_TCP_PCB, pcb);
+  } else {
+    seqno = pcb->snd_nxt;
+    ackno = pcb->rcv_nxt;
+    ip_addr_set(&local_ip, &(pcb->local_ip));
+    ip_addr_set(&remote_ip, &(pcb->remote_ip));
+    local_port = pcb->local_port;
+    remote_port = pcb->remote_port;
+#if LWIP_CALLBACK_API
+    errf = pcb->errf;
+#endif /* LWIP_CALLBACK_API */
+    errf_arg = pcb->callback_arg;
+    tcp_pcb_remove(&tcp_active_pcbs, pcb);
+    if (pcb->unacked != NULL) {
+      tcp_segs_free(pcb->unacked);
+    }
+    if (pcb->unsent != NULL) {
+      tcp_segs_free(pcb->unsent);
+    }
+#if TCP_QUEUE_OOSEQ    
+    if (pcb->ooseq != NULL) {
+      tcp_segs_free(pcb->ooseq);
+    }
+#endif /* TCP_QUEUE_OOSEQ */
+    memp_free(MEMP_TCP_PCB, pcb);
+    TCP_EVENT_ERR(errf, errf_arg, ERR_ABRT);
+    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abort: sending RST\n"));
+    tcp_rst(seqno, ackno, &local_ip, &remote_ip, local_port, remote_port);
+  }
+}
+
+/**
+ * Binds the connection to a local portnumber and IP address. If the
+ * IP address is not given (i.e., ipaddr == NULL), the IP address of
+ * the outgoing network interface is used instead.
+ *
+ */
+
+err_t
+tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
+{
+  struct tcp_pcb *cpcb;
+
+  if (port == 0) {
+    port = tcp_new_port();
+  }
+  /* Check if the address already is in use. */
+  for(cpcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs;
+      cpcb != NULL; cpcb = cpcb->next) {
+    if (cpcb->local_port == port) {
+      if (ip_addr_isany(&(cpcb->local_ip)) ||
+        ip_addr_isany(ipaddr) ||
+        ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
+          return ERR_USE;
+      }
+    }
+  }
+  for(cpcb = tcp_active_pcbs;
+      cpcb != NULL; cpcb = cpcb->next) {
+    if (cpcb->local_port == port) {
+      if (ip_addr_isany(&(cpcb->local_ip)) ||
+   ip_addr_isany(ipaddr) ||
+   ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
+  return ERR_USE;
+      }
+    }
+  }
+
+  if (!ip_addr_isany(ipaddr)) {
+    pcb->local_ip = *ipaddr;
+  }
+  pcb->local_port = port;
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %"U16_F"\n", port));
+  return ERR_OK;
+}
+#if LWIP_CALLBACK_API
+static err_t
+tcp_accept_null(void *arg, struct tcp_pcb *pcb, err_t err)
+{
+  (void)arg;
+  (void)pcb;
+  (void)err;
+
+  return ERR_ABRT;
+}
+#endif /* LWIP_CALLBACK_API */
+
+/**
+ * Set the state of the connection to be LISTEN, which means that it
+ * is able to accept incoming connections. The protocol control block
+ * is reallocated in order to consume less memory. Setting the
+ * connection to LISTEN is an irreversible process.
+ *
+ */
+struct tcp_pcb *
+tcp_listen(struct tcp_pcb *pcb)
+{
+  struct tcp_pcb_listen *lpcb;
+
+  /* already listening? */
+  if (pcb->state == LISTEN) {
+    return pcb;
+  }
+  lpcb = memp_malloc(MEMP_TCP_PCB_LISTEN);
+  if (lpcb == NULL) {
+    return NULL;
+  }
+  lpcb->callback_arg = pcb->callback_arg;
+  lpcb->local_port = pcb->local_port;
+  lpcb->state = LISTEN;
+  lpcb->so_options = pcb->so_options;
+  lpcb->so_options |= SOF_ACCEPTCONN;
+  lpcb->ttl = pcb->ttl;
+  lpcb->tos = pcb->tos;
+  ip_addr_set(&lpcb->local_ip, &pcb->local_ip);
+  memp_free(MEMP_TCP_PCB, pcb);
+#if LWIP_CALLBACK_API
+  lpcb->accept = tcp_accept_null;
+#endif /* LWIP_CALLBACK_API */
+  TCP_REG(&tcp_listen_pcbs.listen_pcbs, lpcb);
+  return (struct tcp_pcb *)lpcb;
+}
+
+/**
+ * This function should be called by the application when it has
+ * processed the data. The purpose is to advertise a larger window
+ * when the data has been processed.
+ *
+ */
+void
+tcp_recved(struct tcp_pcb *pcb, u16_t len)
+{
+  if ((u32_t)pcb->rcv_wnd + len > TCP_WND) {
+    pcb->rcv_wnd = TCP_WND;
+  } else {
+    pcb->rcv_wnd += len;
+  }
+  if (!(pcb->flags & TF_ACK_DELAY) &&
+     !(pcb->flags & TF_ACK_NOW)) {
+    /*
+     * We send an ACK here (if one is not already pending, hence
+     * the above tests) as tcp_recved() implies that the application
+     * has processed some data, and so we can open the receiver's
+     * window to allow more to be transmitted.  This could result in
+     * two ACKs being sent for each received packet in some limited cases
+     * (where the application is only receiving data, and is slow to
+     * process it) but it is necessary to guarantee that the sender can
+     * continue to transmit.
+     */
+    tcp_ack(pcb);
+  } 
+  else if (pcb->flags & TF_ACK_DELAY && pcb->rcv_wnd >= TCP_WND/2) {
+    /* If we can send a window update such that there is a full
+     * segment available in the window, do so now.  This is sort of
+     * nagle-like in its goals, and tries to hit a compromise between
+     * sending acks each time the window is updated, and only sending
+     * window updates when a timer expires.  The "threshold" used
+     * above (currently TCP_WND/2) can be tuned to be more or less
+     * aggressive  */
+    tcp_ack_now(pcb);
+  }
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: recveived %"U16_F" bytes, wnd %"U16_F" (%"U16_F").\n",
+         len, pcb->rcv_wnd, TCP_WND - pcb->rcv_wnd));
+}
+
+/**
+ * A nastly hack featuring 'goto' statements that allocates a
+ * new TCP local port.
+ */
+static u16_t
+tcp_new_port(void)
+{
+  struct tcp_pcb *pcb;
+#ifndef TCP_LOCAL_PORT_RANGE_START
+#define TCP_LOCAL_PORT_RANGE_START 4096
+#define TCP_LOCAL_PORT_RANGE_END   0x7fff
+#endif
+  static u16_t port = TCP_LOCAL_PORT_RANGE_START;
+  
+ again:
+  if (++port > TCP_LOCAL_PORT_RANGE_END) {
+    port = TCP_LOCAL_PORT_RANGE_START;
+  }
+  
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->local_port == port) {
+      goto again;
+    }
+  }
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->local_port == port) {
+      goto again;
+    }
+  }
+  for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->local_port == port) {
+      goto again;
+    }
+  }
+  return port;
+}
+
+/**
+ * Connects to another host. The function given as the "connected"
+ * argument will be called when the connection has been established.
+ *
+ */
+err_t
+tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port,
+      err_t (* connected)(void *arg, struct tcp_pcb *tpcb, err_t err))
+{
+  u32_t optdata;
+  err_t ret;
+  u32_t iss;
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %"U16_F"\n", port));
+  if (ipaddr != NULL) {
+    pcb->remote_ip = *ipaddr;
+  } else {
+    return ERR_VAL;
+  }
+  pcb->remote_port = port;
+  if (pcb->local_port == 0) {
+    pcb->local_port = tcp_new_port();
+  }
+  iss = tcp_next_iss();
+  pcb->rcv_nxt = 0;
+  pcb->snd_nxt = iss;
+  pcb->lastack = iss - 1;
+  pcb->snd_lbb = iss - 1;
+  pcb->rcv_wnd = TCP_WND;
+  pcb->snd_wnd = TCP_WND;
+  pcb->mss = TCP_MSS;
+  pcb->cwnd = 1;
+  pcb->ssthresh = pcb->mss * 10;
+  pcb->state = SYN_SENT;
+#if LWIP_CALLBACK_API  
+  pcb->connected = connected;
+#endif /* LWIP_CALLBACK_API */  
+  TCP_REG(&tcp_active_pcbs, pcb);
+
+  snmp_inc_tcpactiveopens();
+  
+  /* Build an MSS option */
+  optdata = htonl(((u32_t)2 << 24) | 
+      ((u32_t)4 << 16) | 
+      (((u32_t)pcb->mss / 256) << 8) |
+      (pcb->mss & 255));
+
+  ret = tcp_enqueue(pcb, NULL, 0, TCP_SYN, 0, (u8_t *)&optdata, 4);
+  if (ret == ERR_OK) { 
+    tcp_output(pcb);
+  }
+  return ret;
+} 
+
+/**
+ * Called every 500 ms and implements the retransmission timer and the timer that
+ * removes PCBs that have been in TIME-WAIT for enough time. It also increments
+ * various timers such as the inactivity timer in each PCB.
+ */
+void
+tcp_slowtmr(void)
+{
+  struct tcp_pcb *pcb, *pcb2, *prev;
+  u32_t eff_wnd;
+  u8_t pcb_remove;      /* flag if a PCB should be removed */
+  err_t err;
+
+  err = ERR_OK;
+
+  ++tcp_ticks;
+
+  /* Steps through all of the active PCBs. */
+  prev = NULL;
+  pcb = tcp_active_pcbs;
+  if (pcb == NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n"));
+  }
+  while (pcb != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n"));
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN);
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT);
+
+    pcb_remove = 0;
+
+    if (pcb->state == SYN_SENT && pcb->nrtx == TCP_SYNMAXRTX) {
+      ++pcb_remove;
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n"));
+    }
+    else if (pcb->nrtx == TCP_MAXRTX) {
+      ++pcb_remove;
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n"));
+    } else {
+      ++pcb->rtime;
+      if (pcb->unacked != NULL && pcb->rtime >= pcb->rto) {
+
+        /* Time for a retransmission. */
+        LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_slowtmr: rtime %"U16_F" pcb->rto %"U16_F"\n",
+          pcb->rtime, pcb->rto));
+
+        /* Double retransmission time-out unless we are trying to
+         * connect to somebody (i.e., we are in SYN_SENT). */
+        if (pcb->state != SYN_SENT) {
+          pcb->rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[pcb->nrtx];
+        }
+        /* Reduce congestion window and ssthresh. */
+        eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd);
+        pcb->ssthresh = eff_wnd >> 1;
+        if (pcb->ssthresh < pcb->mss) {
+          pcb->ssthresh = pcb->mss * 2;
+        }
+        pcb->cwnd = pcb->mss;
+        LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"U16_F" ssthresh %"U16_F"\n",
+                                pcb->cwnd, pcb->ssthresh));
+ 
+        /* The following needs to be called AFTER cwnd is set to one mss - STJ */
+        tcp_rexmit_rto(pcb);
+     }
+    }
+    /* Check if this PCB has stayed too long in FIN-WAIT-2 */
+    if (pcb->state == FIN_WAIT_2) {
+      if ((u32_t)(tcp_ticks - pcb->tmr) >
+        TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) {
+        ++pcb_remove;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in FIN-WAIT-2\n"));
+      }
+    }
+
+   /* Check if KEEPALIVE should be sent */
+   if((pcb->so_options & SOF_KEEPALIVE) && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) {
+      if((u32_t)(tcp_ticks - pcb->tmr) > (pcb->keepalive + TCP_MAXIDLE) / TCP_SLOW_INTERVAL)  {
+         LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to %"U16_F".%"U16_F".%"U16_F".%"U16_F".\n",
+                                 ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+                                 ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip)));
+
+         tcp_abort(pcb);
+      }
+      else if((u32_t)(tcp_ticks - pcb->tmr) > (pcb->keepalive + pcb->keep_cnt * TCP_KEEPINTVL) / TCP_SLOW_INTERVAL) {
+         tcp_keepalive(pcb);
+         pcb->keep_cnt++;
+      }
+   }
+
+    /* If this PCB has queued out of sequence data, but has been
+       inactive for too long, will drop the data (it will eventually
+       be retransmitted). */
+#if TCP_QUEUE_OOSEQ    
+    if (pcb->ooseq != NULL &&
+       (u32_t)tcp_ticks - pcb->tmr >=
+       pcb->rto * TCP_OOSEQ_TIMEOUT) {
+      tcp_segs_free(pcb->ooseq);
+      pcb->ooseq = NULL;
+      LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n"));
+    }
+#endif /* TCP_QUEUE_OOSEQ */
+
+    /* Check if this PCB has stayed too long in SYN-RCVD */
+    if (pcb->state == SYN_RCVD) {
+      if ((u32_t)(tcp_ticks - pcb->tmr) >
+        TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) {
+        ++pcb_remove;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n"));
+      }
+    }
+
+    /* Check if this PCB has stayed too long in LAST-ACK */
+    if (pcb->state == LAST_ACK) {
+      if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
+        ++pcb_remove;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n"));
+      }
+    }
+
+    /* If the PCB should be removed, do it. */
+    if (pcb_remove) {
+      tcp_pcb_purge(pcb);      
+      /* Remove PCB from tcp_active_pcbs list. */
+      if (prev != NULL) {
+  LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs);
+        prev->next = pcb->next;
+      } else {
+        /* This PCB was the first. */
+        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb);
+        tcp_active_pcbs = pcb->next;
+      }
+
+      TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_ABRT);
+
+      pcb2 = pcb->next;
+      memp_free(MEMP_TCP_PCB, pcb);
+      pcb = pcb2;
+    } else {
+
+      /* We check if we should poll the connection. */
+      ++pcb->polltmr;
+      if (pcb->polltmr >= pcb->pollinterval) {
+        pcb->polltmr = 0;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n"));
+        TCP_EVENT_POLL(pcb, err);
+        if (err == ERR_OK) {
+          tcp_output(pcb);
+        }
+      }
+      
+      prev = pcb;
+      pcb = pcb->next;
+    }
+  }
+
+  
+  /* Steps through all of the TIME-WAIT PCBs. */
+  prev = NULL;    
+  pcb = tcp_tw_pcbs;
+  while (pcb != NULL) {
+    LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+    pcb_remove = 0;
+
+    /* Check if this PCB has stayed long enough in TIME-WAIT */
+    if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
+      ++pcb_remove;
+    }
+    
+
+
+    /* If the PCB should be removed, do it. */
+    if (pcb_remove) {
+      tcp_pcb_purge(pcb);      
+      /* Remove PCB from tcp_tw_pcbs list. */
+      if (prev != NULL) {
+  LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs);
+        prev->next = pcb->next;
+      } else {
+        /* This PCB was the first. */
+        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb);
+        tcp_tw_pcbs = pcb->next;
+      }
+      pcb2 = pcb->next;
+      memp_free(MEMP_TCP_PCB, pcb);
+      pcb = pcb2;
+    } else {
+      prev = pcb;
+      pcb = pcb->next;
+    }
+  }
+}
+
+/**
+ * Is called every TCP_FAST_INTERVAL (250 ms) and sends delayed ACKs.
+ */
+void
+tcp_fasttmr(void)
+{
+  struct tcp_pcb *pcb;
+
+  /* send delayed ACKs */  
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->flags & TF_ACK_DELAY) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n"));
+      tcp_ack_now(pcb);
+      pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
+    }
+  }
+}
+
+/**
+ * Deallocates a list of TCP segments (tcp_seg structures).
+ *
+ */
+u8_t
+tcp_segs_free(struct tcp_seg *seg)
+{
+  u8_t count = 0;
+  struct tcp_seg *next;
+  while (seg != NULL) {
+    next = seg->next;
+    count += tcp_seg_free(seg);
+    seg = next;
+  }
+  return count;
+}
+
+/**
+ * Frees a TCP segment.
+ *
+ */
+u8_t
+tcp_seg_free(struct tcp_seg *seg)
+{
+  u8_t count = 0;
+  
+  if (seg != NULL) {
+    if (seg->p != NULL) {
+      count = pbuf_free(seg->p);
+#if TCP_DEBUG
+      seg->p = NULL;
+#endif /* TCP_DEBUG */
+    }
+    memp_free(MEMP_TCP_SEG, seg);
+  }
+  return count;
+}
+
+/**
+ * Sets the priority of a connection.
+ *
+ */
+void
+tcp_setprio(struct tcp_pcb *pcb, u8_t prio)
+{
+  pcb->prio = prio;
+}
+#if TCP_QUEUE_OOSEQ
+
+/**
+ * Returns a copy of the given TCP segment.
+ *
+ */ 
+struct tcp_seg *
+tcp_seg_copy(struct tcp_seg *seg)
+{
+  struct tcp_seg *cseg;
+
+  cseg = memp_malloc(MEMP_TCP_SEG);
+  if (cseg == NULL) {
+    return NULL;
+  }
+  memcpy((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg)); 
+  pbuf_ref(cseg->p);
+  return cseg;
+}
+#endif
+
+#if LWIP_CALLBACK_API
+static err_t
+tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
+{
+  arg = arg;
+  if (p != NULL) {
+    pbuf_free(p);
+  } else if (err == ERR_OK) {
+    return tcp_close(pcb);
+  }
+  return ERR_OK;
+}
+#endif /* LWIP_CALLBACK_API */
+
+static void
+tcp_kill_prio(u8_t prio)
+{
+  struct tcp_pcb *pcb, *inactive;
+  u32_t inactivity;
+  u8_t mprio;
+
+
+  mprio = TCP_PRIO_MAX;
+  
+  /* We kill the oldest active connection that has lower priority than
+     prio. */
+  inactivity = 0;
+  inactive = NULL;
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->prio <= prio &&
+       pcb->prio <= mprio &&
+       (u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
+      inactivity = tcp_ticks - pcb->tmr;
+      inactive = pcb;
+      mprio = pcb->prio;
+    }
+  }
+  if (inactive != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n",
+           (void *)inactive, inactivity));
+    tcp_abort(inactive);
+  }      
+}
+
+
+static void
+tcp_kill_timewait(void)
+{
+  struct tcp_pcb *pcb, *inactive;
+  u32_t inactivity;
+
+  inactivity = 0;
+  inactive = NULL;
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
+      inactivity = tcp_ticks - pcb->tmr;
+      inactive = pcb;
+    }
+  }
+  if (inactive != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n",
+           (void *)inactive, inactivity));
+    tcp_abort(inactive);
+  }      
+}
+
+
+
+struct tcp_pcb *
+tcp_alloc(u8_t prio)
+{
+  struct tcp_pcb *pcb;
+  u32_t iss;
+  
+  pcb = memp_malloc(MEMP_TCP_PCB);
+  if (pcb == NULL) {
+    /* Try killing oldest connection in TIME-WAIT. */
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n"));
+    tcp_kill_timewait();
+    pcb = memp_malloc(MEMP_TCP_PCB);
+    if (pcb == NULL) {
+      tcp_kill_prio(prio);    
+      pcb = memp_malloc(MEMP_TCP_PCB);
+    }
+  }
+  if (pcb != NULL) {
+    memset(pcb, 0, sizeof(struct tcp_pcb));
+    pcb->prio = TCP_PRIO_NORMAL;
+    pcb->snd_buf = TCP_SND_BUF;
+    pcb->snd_queuelen = 0;
+    pcb->rcv_wnd = TCP_WND;
+    pcb->tos = 0;
+    pcb->ttl = TCP_TTL;
+    pcb->mss = TCP_MSS;
+    pcb->rto = 3000 / TCP_SLOW_INTERVAL;
+    pcb->sa = 0;
+    pcb->sv = 3000 / TCP_SLOW_INTERVAL;
+    pcb->rtime = 0;
+    pcb->cwnd = 1;
+    iss = tcp_next_iss();
+    pcb->snd_wl2 = iss;
+    pcb->snd_nxt = iss;
+    pcb->snd_max = iss;
+    pcb->lastack = iss;
+    pcb->snd_lbb = iss;   
+    pcb->tmr = tcp_ticks;
+
+    pcb->polltmr = 0;
+
+#if LWIP_CALLBACK_API
+    pcb->recv = tcp_recv_null;
+#endif /* LWIP_CALLBACK_API */  
+    
+    /* Init KEEPALIVE timer */
+    pcb->keepalive = TCP_KEEPDEFAULT;
+    pcb->keep_cnt = 0;
+  }
+  return pcb;
+}
+
+/**
+ * Creates a new TCP protocol control block but doesn't place it on
+ * any of the TCP PCB lists.
+ *
+ * @internal: Maybe there should be a idle TCP PCB list where these
+ * PCBs are put on. We can then implement port reservation using
+ * tcp_bind(). Currently, we lack this (BSD socket type of) feature.
+ */
+
+struct tcp_pcb *
+tcp_new(void)
+{
+  return tcp_alloc(TCP_PRIO_NORMAL);
+}
+
+/*
+ * tcp_arg():
+ *
+ * Used to specify the argument that should be passed callback
+ * functions.
+ *
+ */ 
+
+void
+tcp_arg(struct tcp_pcb *pcb, void *arg)
+{  
+  pcb->callback_arg = arg;
+}
+#if LWIP_CALLBACK_API
+
+/**
+ * Used to specify the function that should be called when a TCP
+ * connection receives data.
+ *
+ */ 
+void
+tcp_recv(struct tcp_pcb *pcb,
+   err_t (* recv)(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err))
+{
+  pcb->recv = recv;
+}
+
+/**
+ * Used to specify the function that should be called when TCP data
+ * has been successfully delivered to the remote host.
+ *
+ */ 
+
+void
+tcp_sent(struct tcp_pcb *pcb,
+   err_t (* sent)(void *arg, struct tcp_pcb *tpcb, u16_t len))
+{
+  pcb->sent = sent;
+}
+
+/**
+ * Used to specify the function that should be called when a fatal error
+ * has occured on the connection.
+ *
+ */ 
+void
+tcp_err(struct tcp_pcb *pcb,
+   void (* errf)(void *arg, err_t err))
+{
+  pcb->errf = errf;
+}
+
+/**
+ * Used for specifying the function that should be called when a
+ * LISTENing connection has been connected to another host.
+ *
+ */ 
+void
+tcp_accept(struct tcp_pcb *pcb,
+     err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err))
+{
+  ((struct tcp_pcb_listen *)pcb)->accept = accept;
+}
+#endif /* LWIP_CALLBACK_API */
+
+
+/**
+ * Used to specify the function that should be called periodically
+ * from TCP. The interval is specified in terms of the TCP coarse
+ * timer interval, which is called twice a second.
+ *
+ */ 
+void
+tcp_poll(struct tcp_pcb *pcb,
+   err_t (* poll)(void *arg, struct tcp_pcb *tpcb), u8_t interval)
+{
+#if LWIP_CALLBACK_API
+  pcb->poll = poll;
+#endif /* LWIP_CALLBACK_API */  
+  pcb->pollinterval = interval;
+}
+
+/**
+ * Purges a TCP PCB. Removes any buffered data and frees the buffer memory.
+ *
+ */
+void
+tcp_pcb_purge(struct tcp_pcb *pcb)
+{
+  if (pcb->state != CLOSED &&
+     pcb->state != TIME_WAIT &&
+     pcb->state != LISTEN) {
+
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n"));
+    
+    if (pcb->unsent != NULL) {    
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: not all data sent\n"));
+    }
+    if (pcb->unacked != NULL) {    
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n"));
+    }
+#if TCP_QUEUE_OOSEQ /* LW */
+    if (pcb->ooseq != NULL) {    
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n"));
+    }
+    
+    tcp_segs_free(pcb->ooseq);
+    pcb->ooseq = NULL;
+#endif /* TCP_QUEUE_OOSEQ */
+    tcp_segs_free(pcb->unsent);
+    tcp_segs_free(pcb->unacked);
+    pcb->unacked = pcb->unsent = NULL;
+  }
+}
+
+/**
+ * Purges the PCB and removes it from a PCB list. Any delayed ACKs are sent first.
+ *
+ */
+void
+tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb)
+{
+  TCP_RMV(pcblist, pcb);
+
+  tcp_pcb_purge(pcb);
+  
+  /* if there is an outstanding delayed ACKs, send it */
+  if (pcb->state != TIME_WAIT &&
+     pcb->state != LISTEN &&
+     pcb->flags & TF_ACK_DELAY) {
+    pcb->flags |= TF_ACK_NOW;
+    tcp_output(pcb);
+  }  
+  pcb->state = CLOSED;
+
+  LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane());
+}
+
+/**
+ * Calculates a new initial sequence number for new connections.
+ *
+ */
+u32_t
+tcp_next_iss(void)
+{
+  static u32_t iss = 6510;
+  
+  iss += tcp_ticks;       /* XXX */
+  return iss;
+}
+
+#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
+void
+tcp_debug_print(struct tcp_hdr *tcphdr)
+{
+  LWIP_DEBUGF(TCP_DEBUG, ("TCP header:\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|    %5"U16_F"      |    %5"U16_F"      | (src port, dest port)\n",
+         ntohs(tcphdr->src), ntohs(tcphdr->dest)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|           %010"U32_F"          | (seq no)\n",
+          ntohl(tcphdr->seqno)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|           %010"U32_F"          | (ack no)\n",
+         ntohl(tcphdr->ackno)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("| %2"U16_F" |   |%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"|     %5"U16_F"     | (hdrlen, flags (",
+       TCPH_HDRLEN(tcphdr),
+         TCPH_FLAGS(tcphdr) >> 5 & 1,
+         TCPH_FLAGS(tcphdr) >> 4 & 1,
+         TCPH_FLAGS(tcphdr) >> 3 & 1,
+         TCPH_FLAGS(tcphdr) >> 2 & 1,
+         TCPH_FLAGS(tcphdr) >> 1 & 1,
+         TCPH_FLAGS(tcphdr) & 1,
+         ntohs(tcphdr->wnd)));
+  tcp_debug_print_flags(TCPH_FLAGS(tcphdr));
+  LWIP_DEBUGF(TCP_DEBUG, ("), win)\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|    0x%04"X16_F"     |     %5"U16_F"     | (chksum, urgp)\n",
+         ntohs(tcphdr->chksum), ntohs(tcphdr->urgp)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+}
+
+void
+tcp_debug_print_state(enum tcp_state s)
+{
+  LWIP_DEBUGF(TCP_DEBUG, ("State: "));
+  switch (s) {
+  case CLOSED:
+    LWIP_DEBUGF(TCP_DEBUG, ("CLOSED\n"));
+    break;
+ case LISTEN:
+   LWIP_DEBUGF(TCP_DEBUG, ("LISTEN\n"));
+   break;
+  case SYN_SENT:
+    LWIP_DEBUGF(TCP_DEBUG, ("SYN_SENT\n"));
+    break;
+  case SYN_RCVD:
+    LWIP_DEBUGF(TCP_DEBUG, ("SYN_RCVD\n"));
+    break;
+  case ESTABLISHED:
+    LWIP_DEBUGF(TCP_DEBUG, ("ESTABLISHED\n"));
+    break;
+  case FIN_WAIT_1:
+    LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_1\n"));
+    break;
+  case FIN_WAIT_2:
+    LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_2\n"));
+    break;
+  case CLOSE_WAIT:
+    LWIP_DEBUGF(TCP_DEBUG, ("CLOSE_WAIT\n"));
+    break;
+  case CLOSING:
+    LWIP_DEBUGF(TCP_DEBUG, ("CLOSING\n"));
+    break;
+  case LAST_ACK:
+    LWIP_DEBUGF(TCP_DEBUG, ("LAST_ACK\n"));
+    break;
+  case TIME_WAIT:
+    LWIP_DEBUGF(TCP_DEBUG, ("TIME_WAIT\n"));
+   break;
+  }
+}
+
+void
+tcp_debug_print_flags(u8_t flags)
+{
+  if (flags & TCP_FIN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("FIN "));
+  }
+  if (flags & TCP_SYN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("SYN "));
+  }
+  if (flags & TCP_RST) {
+    LWIP_DEBUGF(TCP_DEBUG, ("RST "));
+  }
+  if (flags & TCP_PSH) {
+    LWIP_DEBUGF(TCP_DEBUG, ("PSH "));
+  }
+  if (flags & TCP_ACK) {
+    LWIP_DEBUGF(TCP_DEBUG, ("ACK "));
+  }
+  if (flags & TCP_URG) {
+    LWIP_DEBUGF(TCP_DEBUG, ("URG "));
+  }
+  if (flags & TCP_ECE) {
+    LWIP_DEBUGF(TCP_DEBUG, ("ECE "));
+  }
+  if (flags & TCP_CWR) {
+    LWIP_DEBUGF(TCP_DEBUG, ("CWR "));
+  }
+}
+
+void
+tcp_debug_print_pcbs(void)
+{
+  struct tcp_pcb *pcb;
+  LWIP_DEBUGF(TCP_DEBUG, ("Active PCB states:\n"));
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ",
+                       pcb->local_port, pcb->remote_port,
+                       pcb->snd_nxt, pcb->rcv_nxt));
+    tcp_debug_print_state(pcb->state);
+  }    
+  LWIP_DEBUGF(TCP_DEBUG, ("Listen PCB states:\n"));
+  for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ",
+                       pcb->local_port, pcb->remote_port,
+                       pcb->snd_nxt, pcb->rcv_nxt));
+    tcp_debug_print_state(pcb->state);
+  }    
+  LWIP_DEBUGF(TCP_DEBUG, ("TIME-WAIT PCB states:\n"));
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ",
+                       pcb->local_port, pcb->remote_port,
+                       pcb->snd_nxt, pcb->rcv_nxt));
+    tcp_debug_print_state(pcb->state);
+  }    
+}
+
+s16_t
+tcp_pcbs_sane(void)
+{
+  struct tcp_pcb *pcb;
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != CLOSED", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != LISTEN", pcb->state != LISTEN);
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
+  }
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_ASSERT("tcp_pcbs_sane: tw pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+  }
+  return 1;
+}
+#endif /* TCP_DEBUG */
+#endif /* LWIP_TCP */
+
+
+
+
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/tcp_in.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/tcp_in.c
new file mode 100644
index 0000000..f711266
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/tcp_in.c
@@ -0,0 +1,1211 @@
+/**
+ * @file
+ *
+ * Transmission Control Protocol, incoming traffic
+ *
+ * The input processing functions of the TCP layer.
+ *
+ * These functions are generally called in the order (ip_input() ->)
+ * tcp_input() -> * tcp_process() -> tcp_receive() (-> application).
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/def.h"
+#include "lwip/opt.h"
+
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+
+#include "lwip/inet.h"
+#include "lwip/tcp.h"
+
+#include "lwip/stats.h"
+#include "arch/perf.h"
+#include "lwip/snmp.h"
+
+#if LWIP_TCP
+/* These variables are global to all functions involved in the input
+   processing of TCP segments. They are set by the tcp_input()
+   function. */
+static struct tcp_seg inseg;
+static struct tcp_hdr *tcphdr;
+static struct ip_hdr *iphdr;
+static u32_t seqno, ackno;
+static u8_t flags;
+static u16_t tcplen;
+
+static u8_t recv_flags;
+static struct pbuf *recv_data;
+
+struct tcp_pcb *tcp_input_pcb;
+
+/* Forward declarations. */
+static err_t tcp_process(struct tcp_pcb *pcb);
+static u8_t tcp_receive(struct tcp_pcb *pcb);
+static void tcp_parseopt(struct tcp_pcb *pcb);
+
+static err_t tcp_listen_input(struct tcp_pcb_listen *pcb);
+static err_t tcp_timewait_input(struct tcp_pcb *pcb);
+
+/* tcp_input:
+ *
+ * The initial input processing of TCP. It verifies the TCP header, demultiplexes
+ * the segment between the PCBs and passes it on to tcp_process(), which implements
+ * the TCP finite state machine. This function is called by the IP layer (in
+ * ip_input()).
+ */
+
+void
+tcp_input(struct pbuf *p, struct netif *inp)
+{
+  struct tcp_pcb *pcb, *prev;
+  struct tcp_pcb_listen *lpcb;
+  u8_t hdrlen;
+  err_t err;
+
+  PERF_START;
+
+  TCP_STATS_INC(tcp.recv);
+  snmp_inc_tcpinsegs();
+
+  iphdr = p->payload;
+  tcphdr = (struct tcp_hdr *)((u8_t *)p->payload + IPH_HL(iphdr) * 4);
+
+#if TCP_INPUT_DEBUG
+  tcp_debug_print(tcphdr);
+#endif
+
+  /* remove header from payload */
+  if (pbuf_header(p, -((s16_t)(IPH_HL(iphdr) * 4))) || (p->tot_len < sizeof(struct tcp_hdr))) {
+    /* drop short packets */
+    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet (%"U16_F" bytes) discarded\n", p->tot_len));
+    TCP_STATS_INC(tcp.lenerr);
+    TCP_STATS_INC(tcp.drop);
+    pbuf_free(p);
+    return;
+  }
+
+  /* Don't even process incoming broadcasts/multicasts. */
+  if (ip_addr_isbroadcast(&(iphdr->dest), inp) ||
+      ip_addr_ismulticast(&(iphdr->dest))) {
+    snmp_inc_tcpinerrs();
+    pbuf_free(p);
+    return;
+  }
+
+#if CHECKSUM_CHECK_TCP
+  /* Verify TCP checksum. */
+  if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
+      (struct ip_addr *)&(iphdr->dest),
+      IP_PROTO_TCP, p->tot_len) != 0) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packet discarded due to failing checksum 0x%04"X16_F"\n",
+        inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), (struct ip_addr *)&(iphdr->dest),
+      IP_PROTO_TCP, p->tot_len)));
+#if TCP_DEBUG
+    tcp_debug_print(tcphdr);
+#endif /* TCP_DEBUG */
+    TCP_STATS_INC(tcp.chkerr);
+    TCP_STATS_INC(tcp.drop);
+    snmp_inc_tcpinerrs();
+    pbuf_free(p);
+    return;
+  }
+#endif
+
+  /* Move the payload pointer in the pbuf so that it points to the
+     TCP data instead of the TCP header. */
+  hdrlen = TCPH_HDRLEN(tcphdr);
+  pbuf_header(p, -(hdrlen * 4));
+
+  /* Convert fields in TCP header to host byte order. */
+  tcphdr->src = ntohs(tcphdr->src);
+  tcphdr->dest = ntohs(tcphdr->dest);
+  seqno = tcphdr->seqno = ntohl(tcphdr->seqno);
+  ackno = tcphdr->ackno = ntohl(tcphdr->ackno);
+  tcphdr->wnd = ntohs(tcphdr->wnd);
+
+  flags = TCPH_FLAGS(tcphdr) & TCP_FLAGS;
+  tcplen = p->tot_len + ((flags & TCP_FIN || flags & TCP_SYN)? 1: 0);
+
+  /* Demultiplex an incoming segment. First, we check if it is destined
+     for an active connection. */
+  prev = NULL;
+
+
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
+    LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN);
+    if (pcb->remote_port == tcphdr->src &&
+       pcb->local_port == tcphdr->dest &&
+       ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) &&
+       ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) {
+
+      /* Move this PCB to the front of the list so that subsequent
+         lookups will be faster (we exploit locality in TCP segment
+         arrivals). */
+      LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb);
+      if (prev != NULL) {
+        prev->next = pcb->next;
+        pcb->next = tcp_active_pcbs;
+        tcp_active_pcbs = pcb;
+      }
+      LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb);
+      break;
+    }
+    prev = pcb;
+  }
+
+  if (pcb == NULL) {
+    /* If it did not go to an active connection, we check the connections
+       in the TIME-WAIT state. */
+    for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+      LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+      if (pcb->remote_port == tcphdr->src &&
+         pcb->local_port == tcphdr->dest &&
+         ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) &&
+         ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) {
+        /* We don't really care enough to move this PCB to the front
+           of the list since we are not very likely to receive that
+           many segments for connections in TIME-WAIT. */
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for TIME_WAITing connection.\n"));
+        tcp_timewait_input(pcb);
+        pbuf_free(p);
+        return;
+      }
+    }
+
+  /* Finally, if we still did not get a match, we check all PCBs that
+     are LISTENing for incoming connections. */
+    prev = NULL;
+    for(lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+      if ((ip_addr_isany(&(lpcb->local_ip)) ||
+        ip_addr_cmp(&(lpcb->local_ip), &(iphdr->dest))) &&
+        lpcb->local_port == tcphdr->dest) {
+        /* Move this PCB to the front of the list so that subsequent
+           lookups will be faster (we exploit locality in TCP segment
+           arrivals). */
+        if (prev != NULL) {
+          ((struct tcp_pcb_listen *)prev)->next = lpcb->next;
+                /* our successor is the remainder of the listening list */
+          lpcb->next = tcp_listen_pcbs.listen_pcbs;
+                /* put this listening pcb at the head of the listening list */
+          tcp_listen_pcbs.listen_pcbs = lpcb;
+        }
+
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for LISTENing connection.\n"));
+        tcp_listen_input(lpcb);
+        pbuf_free(p);
+        return;
+      }
+      prev = (struct tcp_pcb *)lpcb;
+    }
+  }
+
+#if TCP_INPUT_DEBUG
+  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("+-+-+-+-+-+-+-+-+-+-+-+-+-+- tcp_input: flags "));
+  tcp_debug_print_flags(TCPH_FLAGS(tcphdr));
+  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n"));
+#endif /* TCP_INPUT_DEBUG */
+
+
+  if (pcb != NULL) {
+    /* The incoming segment belongs to a connection. */
+#if TCP_INPUT_DEBUG
+#if TCP_DEBUG
+    tcp_debug_print_state(pcb->state);
+#endif /* TCP_DEBUG */
+#endif /* TCP_INPUT_DEBUG */
+
+    /* Set up a tcp_seg structure. */
+    inseg.next = NULL;
+    inseg.len = p->tot_len;
+    inseg.dataptr = p->payload;
+    inseg.p = p;
+    inseg.tcphdr = tcphdr;
+
+    recv_data = NULL;
+    recv_flags = 0;
+
+    tcp_input_pcb = pcb;
+    err = tcp_process(pcb);
+    tcp_input_pcb = NULL;
+    /* A return value of ERR_ABRT means that tcp_abort() was called
+       and that the pcb has been freed. If so, we don't do anything. */
+    if (err != ERR_ABRT) {
+      if (recv_flags & TF_RESET) {
+        /* TF_RESET means that the connection was reset by the other
+           end. We then call the error callback to inform the
+           application that the connection is dead before we
+           deallocate the PCB. */
+        TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_RST);
+        tcp_pcb_remove(&tcp_active_pcbs, pcb);
+        memp_free(MEMP_TCP_PCB, pcb);
+            } else if (recv_flags & TF_CLOSED) {
+        /* The connection has been closed and we will deallocate the
+           PCB. */
+        tcp_pcb_remove(&tcp_active_pcbs, pcb);
+        memp_free(MEMP_TCP_PCB, pcb);
+            } else {
+        err = ERR_OK;
+        /* If the application has registered a "sent" function to be
+           called when new send buffer space is available, we call it
+           now. */
+        if (pcb->acked > 0) {
+          TCP_EVENT_SENT(pcb, pcb->acked, err);
+        }
+
+        if (recv_data != NULL) {
+          /* Notify application that data has been received. */
+          TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err);
+        }
+
+        /* If a FIN segment was received, we call the callback
+           function with a NULL buffer to indicate EOF. */
+        if (recv_flags & TF_GOT_FIN) {
+          TCP_EVENT_RECV(pcb, NULL, ERR_OK, err);
+        }
+        /* If there were no errors, we try to send something out. */
+        if (err == ERR_OK) {
+          tcp_output(pcb);
+        }
+      }
+    }
+
+
+    /* give up our reference to inseg.p */
+    if (inseg.p != NULL)
+    {
+      pbuf_free(inseg.p);
+      inseg.p = NULL;
+    }
+#if TCP_INPUT_DEBUG
+#if TCP_DEBUG
+    tcp_debug_print_state(pcb->state);
+#endif /* TCP_DEBUG */
+#endif /* TCP_INPUT_DEBUG */
+
+  } else {
+
+    /* If no matching PCB was found, send a TCP RST (reset) to the
+       sender. */
+    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_input: no PCB match found, resetting.\n"));
+    if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) {
+      TCP_STATS_INC(tcp.proterr);
+      TCP_STATS_INC(tcp.drop);
+      tcp_rst(ackno, seqno + tcplen,
+        &(iphdr->dest), &(iphdr->src),
+        tcphdr->dest, tcphdr->src);
+    }
+    pbuf_free(p);
+  }
+
+  LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane());
+  PERF_STOP("tcp_input");
+}
+
+/* tcp_listen_input():
+ *
+ * Called by tcp_input() when a segment arrives for a listening
+ * connection.
+ */
+
+static err_t
+tcp_listen_input(struct tcp_pcb_listen *pcb)
+{
+  struct tcp_pcb *npcb;
+  u32_t optdata;
+
+  /* In the LISTEN state, we check for incoming SYN segments,
+     creates a new PCB, and responds with a SYN|ACK. */
+  if (flags & TCP_ACK) {
+    /* For incoming segments with the ACK flag set, respond with a
+       RST. */
+    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n"));
+    tcp_rst(ackno + 1, seqno + tcplen,
+      &(iphdr->dest), &(iphdr->src),
+      tcphdr->dest, tcphdr->src);
+  } else if (flags & TCP_SYN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("TCP connection request %"U16_F" -> %"U16_F".\n", tcphdr->src, tcphdr->dest));
+    npcb = tcp_alloc(pcb->prio);
+    /* If a new PCB could not be created (probably due to lack of memory),
+       we don't do anything, but rely on the sender will retransmit the
+       SYN at a time when we have more memory available. */
+    if (npcb == NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: could not allocate PCB\n"));
+      TCP_STATS_INC(tcp.memerr);
+      return ERR_MEM;
+    }
+    /* Set up the new PCB. */
+    ip_addr_set(&(npcb->local_ip), &(iphdr->dest));
+    npcb->local_port = pcb->local_port;
+    ip_addr_set(&(npcb->remote_ip), &(iphdr->src));
+    npcb->remote_port = tcphdr->src;
+    npcb->state = SYN_RCVD;
+    npcb->rcv_nxt = seqno + 1;
+    npcb->snd_wnd = tcphdr->wnd;
+    npcb->ssthresh = npcb->snd_wnd;
+    npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */
+    npcb->callback_arg = pcb->callback_arg;
+#if LWIP_CALLBACK_API
+    npcb->accept = pcb->accept;
+#endif /* LWIP_CALLBACK_API */
+    /* inherit socket options */
+    npcb->so_options = pcb->so_options & (SOF_DEBUG|SOF_DONTROUTE|SOF_KEEPALIVE|SOF_OOBINLINE|SOF_LINGER);
+    /* Register the new PCB so that we can begin receiving segments
+       for it. */
+    TCP_REG(&tcp_active_pcbs, npcb);
+
+    /* Parse any options in the SYN. */
+    tcp_parseopt(npcb);
+
+    snmp_inc_tcppassiveopens();
+
+    /* Build an MSS option. */
+    optdata = htonl(((u32_t)2 << 24) |
+        ((u32_t)4 << 16) |
+        (((u32_t)npcb->mss / 256) << 8) |
+        (npcb->mss & 255));
+    /* Send a SYN|ACK together with the MSS option. */
+    tcp_enqueue(npcb, NULL, 0, TCP_SYN | TCP_ACK, 0, (u8_t *)&optdata, 4);
+    return tcp_output(npcb);
+  }
+  return ERR_OK;
+}
+
+/* tcp_timewait_input():
+ *
+ * Called by tcp_input() when a segment arrives for a connection in
+ * TIME_WAIT.
+ */
+
+static err_t
+tcp_timewait_input(struct tcp_pcb *pcb)
+{
+  if (TCP_SEQ_GT(seqno + tcplen, pcb->rcv_nxt)) {
+    pcb->rcv_nxt = seqno + tcplen;
+  }
+  if (tcplen > 0) {
+    tcp_ack_now(pcb);
+  }
+  return tcp_output(pcb);
+}
+
+/* tcp_process
+ *
+ * Implements the TCP state machine. Called by tcp_input. In some
+ * states tcp_receive() is called to receive data. The tcp_seg
+ * argument will be freed by the caller (tcp_input()) unless the
+ * recv_data pointer in the pcb is set.
+ */
+
+static err_t
+tcp_process(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *rseg;
+  u8_t acceptable = 0;
+  err_t err;
+  u8_t accepted_inseq;
+
+  err = ERR_OK;
+
+  /* Process incoming RST segments. */
+  if (flags & TCP_RST) {
+    /* First, determine if the reset is acceptable. */
+    if (pcb->state == SYN_SENT) {
+      if (ackno == pcb->snd_nxt) {
+        acceptable = 1;
+      }
+    } else {
+      /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) &&
+          TCP_SEQ_LEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {
+      */
+      if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt+pcb->rcv_wnd)) {
+        acceptable = 1;
+      }
+    }
+
+    if (acceptable) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n"));
+      LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED);
+      recv_flags = TF_RESET;
+      pcb->flags &= ~TF_ACK_DELAY;
+      return ERR_RST;
+    } else {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
+       seqno, pcb->rcv_nxt));
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
+       seqno, pcb->rcv_nxt));
+      return ERR_OK;
+    }
+  }
+
+  /* Update the PCB (in)activity timer. */
+  pcb->tmr = tcp_ticks;
+  pcb->keep_cnt = 0;
+
+  /* Do different things depending on the TCP state. */
+  switch (pcb->state) {
+  case SYN_SENT:
+    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno,
+     pcb->snd_nxt, ntohl(pcb->unacked->tcphdr->seqno)));
+    /* received SYN ACK with expected sequence number? */
+    if ((flags & TCP_ACK) && (flags & TCP_SYN)
+        && ackno == ntohl(pcb->unacked->tcphdr->seqno) + 1) {
+      pcb->snd_buf++;
+      pcb->rcv_nxt = seqno + 1;
+      pcb->lastack = ackno;
+      pcb->snd_wnd = tcphdr->wnd;
+      pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */
+      pcb->state = ESTABLISHED;
+			pcb->cwnd = ((pcb->cwnd == 1) ? (pcb->mss * 2) : pcb->mss);
+      --pcb->snd_queuelen;
+      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"U16_F"\n", (u16_t)pcb->snd_queuelen));
+      rseg = pcb->unacked;
+      pcb->unacked = rseg->next;
+      tcp_seg_free(rseg);
+
+      /* Parse any options in the SYNACK. */
+      tcp_parseopt(pcb);
+
+      /* Call the user specified function to call when sucessfully
+       * connected. */
+      TCP_EVENT_CONNECTED(pcb, ERR_OK, err);
+      tcp_ack(pcb);
+    }
+    /* received ACK? possibly a half-open connection */
+    else if (flags & TCP_ACK) {
+      /* send a RST to bring the other side in a non-synchronized state. */
+      tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src),
+        tcphdr->dest, tcphdr->src);
+    }
+    break;
+  case SYN_RCVD:
+    if (flags & TCP_ACK &&
+       !(flags & TCP_RST)) {
+      /* expected ACK number? */
+      if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)) {
+				u16_t old_cwnd;
+        pcb->state = ESTABLISHED;
+        LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+#if LWIP_CALLBACK_API
+        LWIP_ASSERT("pcb->accept != NULL", pcb->accept != NULL);
+#endif
+        /* Call the accept function. */
+        TCP_EVENT_ACCEPT(pcb, ERR_OK, err);
+        if (err != ERR_OK) {
+          /* If the accept function returns with an error, we abort
+           * the connection. */
+          tcp_abort(pcb);
+          return ERR_ABRT;
+        }
+				old_cwnd = pcb->cwnd;
+        /* If there was any data contained within this ACK,
+         * we'd better pass it on to the application as well. */
+        tcp_receive(pcb);
+				pcb->cwnd = ((old_cwnd == 1) ? (pcb->mss * 2) : pcb->mss);
+      }
+      /* incorrect ACK number */
+      else {
+        /* send RST */
+        tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src),
+          tcphdr->dest, tcphdr->src);
+      }
+    }
+    break;
+  case CLOSE_WAIT:
+    /* FALLTHROUGH */
+  case ESTABLISHED:
+    accepted_inseq = tcp_receive(pcb);
+    if ((flags & TCP_FIN) && accepted_inseq) { /* passive close */
+      tcp_ack_now(pcb);
+      pcb->state = CLOSE_WAIT;
+    }
+    break;
+  case FIN_WAIT_1:
+    tcp_receive(pcb);
+    if (flags & TCP_FIN) {
+      if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+        LWIP_DEBUGF(TCP_DEBUG,
+          ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+        tcp_ack_now(pcb);
+        tcp_pcb_purge(pcb);
+        TCP_RMV(&tcp_active_pcbs, pcb);
+        pcb->state = TIME_WAIT;
+        TCP_REG(&tcp_tw_pcbs, pcb);
+      } else {
+        tcp_ack_now(pcb);
+        pcb->state = CLOSING;
+      }
+    } else if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+      pcb->state = FIN_WAIT_2;
+    }
+    break;
+  case FIN_WAIT_2:
+    tcp_receive(pcb);
+    if (flags & TCP_FIN) {
+      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+      tcp_ack_now(pcb);
+      tcp_pcb_purge(pcb);
+      TCP_RMV(&tcp_active_pcbs, pcb);
+      pcb->state = TIME_WAIT;
+      TCP_REG(&tcp_tw_pcbs, pcb);
+    }
+    break;
+  case CLOSING:
+    tcp_receive(pcb);
+    if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+      tcp_ack_now(pcb);
+      tcp_pcb_purge(pcb);
+      TCP_RMV(&tcp_active_pcbs, pcb);
+      pcb->state = TIME_WAIT;
+      TCP_REG(&tcp_tw_pcbs, pcb);
+    }
+    break;
+  case LAST_ACK:
+    tcp_receive(pcb);
+    if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+      pcb->state = CLOSED;
+      recv_flags = TF_CLOSED;
+    }
+    break;
+  default:
+    break;
+  }
+  return ERR_OK;
+}
+
+/* tcp_receive:
+ *
+ * Called by tcp_process. Checks if the given segment is an ACK for outstanding
+ * data, and if so frees the memory of the buffered data. Next, is places the
+ * segment on any of the receive queues (pcb->recved or pcb->ooseq). If the segment
+ * is buffered, the pbuf is referenced by pbuf_ref so that it will not be freed until
+ * i it has been removed from the buffer.
+ *
+ * If the incoming segment constitutes an ACK for a segment that was used for RTT
+ * estimation, the RTT is estimated here as well.
+ *
+ * @return 1 if
+ */
+
+static u8_t
+tcp_receive(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *next;
+#if TCP_QUEUE_OOSEQ
+  struct tcp_seg *prev, *cseg;
+#endif
+  struct pbuf *p;
+  s32_t off;
+  s16_t m;
+  u32_t right_wnd_edge;
+  u16_t new_tot_len;
+  u8_t accepted_inseq = 0;
+
+  if (flags & TCP_ACK) {
+    right_wnd_edge = pcb->snd_wnd + pcb->snd_wl1;
+
+    /* Update window. */
+    if (TCP_SEQ_LT(pcb->snd_wl1, seqno) ||
+       (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
+       (pcb->snd_wl2 == ackno && tcphdr->wnd > pcb->snd_wnd)) {
+      pcb->snd_wnd = tcphdr->wnd;
+      pcb->snd_wl1 = seqno;
+      pcb->snd_wl2 = ackno;
+      LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: window update %"U32_F"\n", pcb->snd_wnd));
+#if TCP_WND_DEBUG
+    } else {
+      if (pcb->snd_wnd != tcphdr->wnd) {
+        LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: no window update lastack %"U32_F" snd_max %"U32_F" ackno %"U32_F" wl1 %"U32_F" seqno %"U32_F" wl2 %"U32_F"\n",
+                               pcb->lastack, pcb->snd_max, ackno, pcb->snd_wl1, seqno, pcb->snd_wl2));
+      }
+#endif /* TCP_WND_DEBUG */
+    }
+
+    if (pcb->lastack == ackno) {
+      pcb->acked = 0;
+
+      if (pcb->snd_wl1 + pcb->snd_wnd == right_wnd_edge){
+        ++pcb->dupacks;
+        if (pcb->dupacks >= 3 && pcb->unacked != NULL) {
+          if (!(pcb->flags & TF_INFR)) {
+            /* This is fast retransmit. Retransmit the first unacked segment. */
+            LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupacks %"U16_F" (%"U32_F"), fast retransmit %"U32_F"\n",
+                                       (u16_t)pcb->dupacks, pcb->lastack,
+                                       ntohl(pcb->unacked->tcphdr->seqno)));
+            tcp_rexmit(pcb);
+            /* Set ssthresh to max (FlightSize / 2, 2*SMSS) */
+            /*pcb->ssthresh = LWIP_MAX((pcb->snd_max -
+                                      pcb->lastack) / 2,
+                                      2 * pcb->mss);*/
+            /* Set ssthresh to half of the minimum of the currenct cwnd and the advertised window */
+            if (pcb->cwnd > pcb->snd_wnd)
+              pcb->ssthresh = pcb->snd_wnd / 2;
+            else
+              pcb->ssthresh = pcb->cwnd / 2;
+
+            pcb->cwnd = pcb->ssthresh + 3 * pcb->mss;
+            pcb->flags |= TF_INFR;
+          } else {
+            /* Inflate the congestion window, but not if it means that
+               the value overflows. */
+            if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) {
+              pcb->cwnd += pcb->mss;
+            }
+          }
+        }
+      } else {
+        LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupack averted %"U32_F" %"U32_F"\n",
+                                   pcb->snd_wl1 + pcb->snd_wnd, right_wnd_edge));
+      }
+    } else
+      /*if (TCP_SEQ_LT(pcb->lastack, ackno) &&
+        TCP_SEQ_LEQ(ackno, pcb->snd_max)) { */
+      if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_max)){
+      /* We come here when the ACK acknowledges new data. */
+
+      /* Reset the "IN Fast Retransmit" flag, since we are no longer
+         in fast retransmit. Also reset the congestion window to the
+         slow start threshold. */
+      if (pcb->flags & TF_INFR) {
+        pcb->flags &= ~TF_INFR;
+        pcb->cwnd = pcb->ssthresh;
+      }
+
+      /* Reset the number of retransmissions. */
+      pcb->nrtx = 0;
+
+      /* Reset the retransmission time-out. */
+      pcb->rto = (pcb->sa >> 3) + pcb->sv;
+
+      /* Update the send buffer space. */
+      pcb->acked = ackno - pcb->lastack;
+
+      pcb->snd_buf += pcb->acked;
+
+      /* Reset the fast retransmit variables. */
+      pcb->dupacks = 0;
+      pcb->lastack = ackno;
+
+      /* Update the congestion control variables (cwnd and
+         ssthresh). */
+      if (pcb->state >= ESTABLISHED) {
+        if (pcb->cwnd < pcb->ssthresh) {
+          if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) {
+            pcb->cwnd += pcb->mss;
+          }
+          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"U16_F"\n", pcb->cwnd));
+        } else {
+          u16_t new_cwnd = (pcb->cwnd + pcb->mss * pcb->mss / pcb->cwnd);
+          if (new_cwnd > pcb->cwnd) {
+            pcb->cwnd = new_cwnd;
+          }
+          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: congestion avoidance cwnd %"U16_F"\n", pcb->cwnd));
+        }
+      }
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: ACK for %"U32_F", unacked->seqno %"U32_F":%"U32_F"\n",
+                                    ackno,
+                                    pcb->unacked != NULL?
+                                    ntohl(pcb->unacked->tcphdr->seqno): 0,
+                                    pcb->unacked != NULL?
+                                    ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked): 0));
+
+      /* Remove segment from the unacknowledged list if the incoming
+         ACK acknowlegdes them. */
+      while (pcb->unacked != NULL &&
+             TCP_SEQ_LEQ(ntohl(pcb->unacked->tcphdr->seqno) +
+                         TCP_TCPLEN(pcb->unacked), ackno)) {
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unacked\n",
+                                      ntohl(pcb->unacked->tcphdr->seqno),
+                                      ntohl(pcb->unacked->tcphdr->seqno) +
+                                      TCP_TCPLEN(pcb->unacked)));
+
+        next = pcb->unacked;
+        pcb->unacked = pcb->unacked->next;
+
+        LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen));
+        pcb->snd_queuelen -= pbuf_clen(next->p);
+        tcp_seg_free(next);
+
+        LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unacked)\n", (u16_t)pcb->snd_queuelen));
+        if (pcb->snd_queuelen != 0) {
+          LWIP_ASSERT("tcp_receive: valid queue length", pcb->unacked != NULL ||
+                      pcb->unsent != NULL);
+        }
+      }
+      pcb->polltmr = 0;
+    }
+
+    /* We go through the ->unsent list to see if any of the segments
+       on the list are acknowledged by the ACK. This may seem
+       strange since an "unsent" segment shouldn't be acked. The
+       rationale is that lwIP puts all outstanding segments on the
+       ->unsent list after a retransmission, so these segments may
+       in fact have been sent once. */
+    while (pcb->unsent != NULL &&
+           /*TCP_SEQ_LEQ(ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), ackno) &&
+             TCP_SEQ_LEQ(ackno, pcb->snd_max)*/
+           TCP_SEQ_BETWEEN(ackno, ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), pcb->snd_max)
+           ) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unsent\n",
+                                    ntohl(pcb->unsent->tcphdr->seqno), ntohl(pcb->unsent->tcphdr->seqno) +
+                                    TCP_TCPLEN(pcb->unsent)));
+
+      next = pcb->unsent;
+      pcb->unsent = pcb->unsent->next;
+      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen));
+      pcb->snd_queuelen -= pbuf_clen(next->p);
+      tcp_seg_free(next);
+      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unsent)\n", (u16_t)pcb->snd_queuelen));
+      if (pcb->snd_queuelen != 0) {
+        LWIP_ASSERT("tcp_receive: valid queue length",
+          pcb->unacked != NULL || pcb->unsent != NULL);
+      }
+
+      if (pcb->unsent != NULL) {
+        pcb->snd_nxt = htonl(pcb->unsent->tcphdr->seqno);
+      }
+    }
+    /* End of ACK for new data processing. */
+
+    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: pcb->rttest %"U32_F" rtseq %"U32_F" ackno %"U32_F"\n",
+                                pcb->rttest, pcb->rtseq, ackno));
+
+    /* RTT estimation calculations. This is done by checking if the
+       incoming segment acknowledges the segment we use to take a
+       round-trip time measurement. */
+    if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) {
+      m = tcp_ticks - pcb->rttest;
+
+      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n",
+                                  m, m * TCP_SLOW_INTERVAL));
+
+      /* This is taken directly from VJs original code in his paper */
+      m = m - (pcb->sa >> 3);
+      pcb->sa += m;
+      if (m < 0) {
+        m = -m;
+      }
+      m = m - (pcb->sv >> 2);
+      pcb->sv += m;
+      pcb->rto = (pcb->sa >> 3) + pcb->sv;
+
+      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" miliseconds)\n",
+                                  pcb->rto, pcb->rto * TCP_SLOW_INTERVAL));
+
+      pcb->rttest = 0;
+    }
+  }
+
+  /* If the incoming segment contains data, we must process it
+     further. */
+  if (tcplen > 0) {
+    /* This code basically does three things:
+
+    +) If the incoming segment contains data that is the next
+    in-sequence data, this data is passed to the application. This
+    might involve trimming the first edge of the data. The rcv_nxt
+    variable and the advertised window are adjusted.
+
+    +) If the incoming segment has data that is above the next
+    sequence number expected (->rcv_nxt), the segment is placed on
+    the ->ooseq queue. This is done by finding the appropriate
+    place in the ->ooseq queue (which is ordered by sequence
+    number) and trim the segment in both ends if needed. An
+    immediate ACK is sent to indicate that we received an
+    out-of-sequence segment.
+
+    +) Finally, we check if the first segment on the ->ooseq queue
+    now is in sequence (i.e., if rcv_nxt >= ooseq->seqno). If
+    rcv_nxt > ooseq->seqno, we must trim the first edge of the
+    segment on ->ooseq before we adjust rcv_nxt. The data in the
+    segments that are now on sequence are chained onto the
+    incoming segment so that we only need to call the application
+    once.
+    */
+
+    /* First, we check if we must trim the first edge. We have to do
+       this if the sequence number of the incoming segment is less
+       than rcv_nxt, and the sequence number plus the length of the
+       segment is larger than rcv_nxt. */
+    /*    if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){
+          if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/
+    if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)){
+      /* Trimming the first edge is done by pushing the payload
+         pointer in the pbuf downwards. This is somewhat tricky since
+         we do not want to discard the full contents of the pbuf up to
+         the new starting point of the data since we have to keep the
+         TCP header which is present in the first pbuf in the chain.
+
+         What is done is really quite a nasty hack: the first pbuf in
+         the pbuf chain is pointed to by inseg.p. Since we need to be
+         able to deallocate the whole pbuf, we cannot change this
+         inseg.p pointer to point to any of the later pbufs in the
+         chain. Instead, we point the ->payload pointer in the first
+         pbuf to data in one of the later pbufs. We also set the
+         inseg.data pointer to point to the right place. This way, the
+         ->p pointer will still point to the first pbuf, but the
+         ->p->payload pointer will point to data in another pbuf.
+
+         After we are done with adjusting the pbuf pointers we must
+         adjust the ->data pointer in the seg and the segment
+         length.*/
+
+      off = pcb->rcv_nxt - seqno;
+      p = inseg.p;
+      LWIP_ASSERT("inseg.p != NULL", inseg.p);
+      if (inseg.p->len < off) {
+        new_tot_len = inseg.p->tot_len - off;
+        while (p->len < off) {
+          off -= p->len;
+          /* KJM following line changed (with addition of new_tot_len var)
+             to fix bug #9076
+             inseg.p->tot_len -= p->len; */
+          p->tot_len = new_tot_len;
+          p->len = 0;
+          p = p->next;
+        }
+        pbuf_header(p, -off);
+      } else {
+        pbuf_header(inseg.p, -off);
+      }
+      /* KJM following line changed to use p->payload rather than inseg->p->payload
+         to fix bug #9076 */
+      inseg.dataptr = p->payload;
+      inseg.len -= pcb->rcv_nxt - seqno;
+      inseg.tcphdr->seqno = seqno = pcb->rcv_nxt;
+    }
+    else {
+      if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){
+        /* the whole segment is < rcv_nxt */
+        /* must be a duplicate of a packet that has already been correctly handled */
+
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno));
+        tcp_ack_now(pcb);
+      }
+    }
+
+    /* The sequence number must be within the window (above rcv_nxt
+       and below rcv_nxt + rcv_wnd) in order to be further
+       processed. */
+    /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) &&
+      TCP_SEQ_LT(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
+    if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)){
+      if (pcb->rcv_nxt == seqno) {
+        accepted_inseq = 1;
+        /* The incoming segment is the next in sequence. We check if
+           we have to trim the end of the segment and update rcv_nxt
+           and pass the data to the application. */
+#if TCP_QUEUE_OOSEQ
+        if (pcb->ooseq != NULL &&
+            TCP_SEQ_LEQ(pcb->ooseq->tcphdr->seqno, seqno + inseg.len)) {
+          /* We have to trim the second edge of the incoming
+             segment. */
+          inseg.len = pcb->ooseq->tcphdr->seqno - seqno;
+          pbuf_realloc(inseg.p, inseg.len);
+        }
+#endif /* TCP_QUEUE_OOSEQ */
+
+        tcplen = TCP_TCPLEN(&inseg);
+
+        /* First received FIN will be ACKed +1, on any successive (duplicate)
+         * FINs we are already in CLOSE_WAIT and have already done +1.
+         */
+        if (pcb->state != CLOSE_WAIT) {
+          pcb->rcv_nxt += tcplen;
+        }
+
+        /* Update the receiver's (our) window. */
+        if (pcb->rcv_wnd < tcplen) {
+          pcb->rcv_wnd = 0;
+        } else {
+          pcb->rcv_wnd -= tcplen;
+        }
+
+        /* If there is data in the segment, we make preparations to
+           pass this up to the application. The ->recv_data variable
+           is used for holding the pbuf that goes to the
+           application. The code for reassembling out-of-sequence data
+           chains its data on this pbuf as well.
+
+           If the segment was a FIN, we set the TF_GOT_FIN flag that will
+           be used to indicate to the application that the remote side has
+           closed its end of the connection. */
+        if (inseg.p->tot_len > 0) {
+          recv_data = inseg.p;
+          /* Since this pbuf now is the responsibility of the
+             application, we delete our reference to it so that we won't
+             (mistakingly) deallocate it. */
+          inseg.p = NULL;
+        }
+        if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n"));
+          recv_flags = TF_GOT_FIN;
+        }
+
+#if TCP_QUEUE_OOSEQ
+        /* We now check if we have segments on the ->ooseq queue that
+           is now in sequence. */
+        while (pcb->ooseq != NULL &&
+               pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) {
+
+          cseg = pcb->ooseq;
+          seqno = pcb->ooseq->tcphdr->seqno;
+
+          pcb->rcv_nxt += TCP_TCPLEN(cseg);
+          if (pcb->rcv_wnd < TCP_TCPLEN(cseg)) {
+            pcb->rcv_wnd = 0;
+          } else {
+            pcb->rcv_wnd -= TCP_TCPLEN(cseg);
+          }
+          if (cseg->p->tot_len > 0) {
+            /* Chain this pbuf onto the pbuf that we will pass to
+               the application. */
+            if (recv_data) {
+              pbuf_cat(recv_data, cseg->p);
+            } else {
+              recv_data = cseg->p;
+            }
+            cseg->p = NULL;
+          }
+          if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
+            LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n"));
+            recv_flags = TF_GOT_FIN;
+            if (pcb->state == ESTABLISHED) { /* force passive close or we can move to active close */
+              pcb->state = CLOSE_WAIT;
+            }
+          }
+
+
+          pcb->ooseq = cseg->next;
+          tcp_seg_free(cseg);
+        }
+#endif /* TCP_QUEUE_OOSEQ */
+
+
+        /* Acknowledge the segment(s). */
+        tcp_ack(pcb);
+
+      } else {
+        /* We get here if the incoming segment is out-of-sequence. */
+        tcp_ack_now(pcb);
+#if TCP_QUEUE_OOSEQ
+        /* We queue the segment on the ->ooseq queue. */
+        if (pcb->ooseq == NULL) {
+          pcb->ooseq = tcp_seg_copy(&inseg);
+        } else {
+          /* If the queue is not empty, we walk through the queue and
+             try to find a place where the sequence number of the
+             incoming segment is between the sequence numbers of the
+             previous and the next segment on the ->ooseq queue. That is
+             the place where we put the incoming segment. If needed, we
+             trim the second edges of the previous and the incoming
+             segment so that it will fit into the sequence.
+
+             If the incoming segment has the same sequence number as a
+             segment on the ->ooseq queue, we discard the segment that
+             contains less data. */
+
+          prev = NULL;
+          for(next = pcb->ooseq; next != NULL; next = next->next) {
+            if (seqno == next->tcphdr->seqno) {
+              /* The sequence number of the incoming segment is the
+                 same as the sequence number of the segment on
+                 ->ooseq. We check the lengths to see which one to
+                 discard. */
+              if (inseg.len > next->len) {
+                /* The incoming segment is larger than the old
+                   segment. We replace the old segment with the new
+                   one. */
+                cseg = tcp_seg_copy(&inseg);
+                if (cseg != NULL) {
+                  cseg->next = next->next;
+                  if (prev != NULL) {
+                    prev->next = cseg;
+                  } else {
+                    pcb->ooseq = cseg;
+                  }
+                }
+                break;
+              } else {
+                /* Either the lenghts are the same or the incoming
+                   segment was smaller than the old one; in either
+                   case, we ditch the incoming segment. */
+                break;
+              }
+            } else {
+              if (prev == NULL) {
+                if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {
+                  /* The sequence number of the incoming segment is lower
+                     than the sequence number of the first segment on the
+                     queue. We put the incoming segment first on the
+                     queue. */
+
+                  if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) {
+                    /* We need to trim the incoming segment. */
+                    inseg.len = next->tcphdr->seqno - seqno;
+                    pbuf_realloc(inseg.p, inseg.len);
+                  }
+                  cseg = tcp_seg_copy(&inseg);
+                  if (cseg != NULL) {
+                    cseg->next = next;
+                    pcb->ooseq = cseg;
+                  }
+                  break;
+                }
+              } else
+                /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) &&
+                  TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/
+                if(TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno+1, next->tcphdr->seqno-1)){
+                /* The sequence number of the incoming segment is in
+                   between the sequence numbers of the previous and
+                   the next segment on ->ooseq. We trim and insert the
+                   incoming segment and trim the previous segment, if
+                   needed. */
+                if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) {
+                  /* We need to trim the incoming segment. */
+                  inseg.len = next->tcphdr->seqno - seqno;
+                  pbuf_realloc(inseg.p, inseg.len);
+                }
+
+                cseg = tcp_seg_copy(&inseg);
+                if (cseg != NULL) {
+                  cseg->next = next;
+                  prev->next = cseg;
+                  if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) {
+                    /* We need to trim the prev segment. */
+                    prev->len = seqno - prev->tcphdr->seqno;
+                    pbuf_realloc(prev->p, prev->len);
+                  }
+                }
+                break;
+              }
+              /* If the "next" segment is the last segment on the
+                 ooseq queue, we add the incoming segment to the end
+                 of the list. */
+              if (next->next == NULL &&
+                  TCP_SEQ_GT(seqno, next->tcphdr->seqno)) {
+                next->next = tcp_seg_copy(&inseg);
+                if (next->next != NULL) {
+                  if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) {
+                    /* We need to trim the last segment. */
+                    next->len = seqno - next->tcphdr->seqno;
+                    pbuf_realloc(next->p, next->len);
+                  }
+                }
+                break;
+              }
+            }
+            prev = next;
+          }
+        }
+#endif /* TCP_QUEUE_OOSEQ */
+
+      }
+    } else {
+      /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) ||
+        TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
+      if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){
+        tcp_ack_now(pcb);
+      }
+    }
+  } else {
+    /* Segments with length 0 is taken care of here. Segments that
+       fall out of the window are ACKed. */
+    /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) ||
+      TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
+    if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){
+      tcp_ack_now(pcb);
+    }
+  }
+  return accepted_inseq;
+}
+
+/*
+ * tcp_parseopt:
+ *
+ * Parses the options contained in the incoming segment. (Code taken
+ * from uIP with only small changes.)
+ *
+ */
+
+static void
+tcp_parseopt(struct tcp_pcb *pcb)
+{
+  u8_t c;
+  u8_t *opts, opt;
+  u16_t mss;
+
+  opts = (u8_t *)tcphdr + TCP_HLEN;
+
+  /* Parse the TCP MSS option, if present. */
+  if(TCPH_HDRLEN(tcphdr) > 0x5) {
+    for(c = 0; c < (TCPH_HDRLEN(tcphdr) - 5) << 2 ;) {
+      opt = opts[c];
+      if (opt == 0x00) {
+        /* End of options. */
+  break;
+      } else if (opt == 0x01) {
+        ++c;
+        /* NOP option. */
+      } else if (opt == 0x02 &&
+        opts[c + 1] == 0x04) {
+        /* An MSS option with the right option length. */
+        mss = (opts[c + 2] << 8) | opts[c + 3];
+        pcb->mss = mss > TCP_MSS? TCP_MSS: mss;
+
+        /* And we are done processing options. */
+        break;
+      } else {
+  if (opts[c + 1] == 0) {
+          /* If the length field is zero, the options are malformed
+             and we don't process them further. */
+          break;
+        }
+        /* All other options have a length field, so that we easily
+           can skip past them. */
+        c += opts[c + 1];
+      }
+    }
+  }
+}
+#endif /* LWIP_TCP */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/tcp_out.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/tcp_out.c
new file mode 100644
index 0000000..8802fea
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/tcp_out.c
@@ -0,0 +1,727 @@
+/**
+ * @file
+ *
+ * Transmission Control Protocol, outgoing traffic
+ *
+ * The output functions of TCP.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include 
+
+#include "lwip/def.h"
+#include "lwip/opt.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/sys.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/inet.h"
+#include "lwip/tcp.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+
+#if LWIP_TCP
+
+/* Forward declarations.*/
+static void tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb);
+
+err_t
+tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags)
+{
+  /* no data, no length, flags, copy=1, no optdata, no optdatalen */
+  return tcp_enqueue(pcb, NULL, 0, flags, 1, NULL, 0);
+}
+
+/**
+ * Write data for sending (but does not send it immediately).
+ *
+ * It waits in the expectation of more data being sent soon (as
+ * it can send them more efficiently by combining them together).
+ * To prompt the system to send data now, call tcp_output() after
+ * calling tcp_write().
+ * 
+ * @arg pcb Protocol control block of the TCP connection to enqueue data for. 
+ * 
+ * @see tcp_write()
+ */
+
+err_t
+tcp_write(struct tcp_pcb *pcb, const void *arg, u16_t len, u8_t copy)
+{
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, arg=%p, len=%"U16_F", copy=%"U16_F")\n", (void *)pcb,
+    arg, len, (u16_t)copy));
+  /* connection is in valid state for data transmission? */
+  if (pcb->state == ESTABLISHED ||
+     pcb->state == CLOSE_WAIT ||
+     pcb->state == SYN_SENT ||
+     pcb->state == SYN_RCVD) {
+    if (len > 0) {
+      return tcp_enqueue(pcb, (void *)arg, len, 0, copy, NULL, 0);
+    }
+    return ERR_OK;
+  } else {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_STATE | 3, ("tcp_write() called in invalid state\n"));
+    return ERR_CONN;
+  }
+}
+
+/**
+ * Enqueue either data or TCP options (but not both) for tranmission
+ * 
+ * 
+ * 
+ * @arg pcb Protocol control block for the TCP connection to enqueue data for.
+ * @arg arg Pointer to the data to be enqueued for sending.
+ * @arg len Data length in bytes
+ * @arg flags
+ * @arg copy 1 if data must be copied, 0 if data is non-volatile and can be
+ * referenced.
+ * @arg optdata
+ * @arg optlen
+ */
+err_t
+tcp_enqueue(struct tcp_pcb *pcb, void *arg, u16_t len,
+  u8_t flags, u8_t copy,
+  u8_t *optdata, u8_t optlen)
+{
+  struct pbuf *p;
+  struct tcp_seg *seg, *useg, *queue;
+  u32_t left, seqno;
+  u16_t seglen;
+  void *ptr;
+  u8_t queuelen;
+
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_enqueue(pcb=%p, arg=%p, len=%"U16_F", flags=%"X16_F", copy=%"U16_F")\n",
+    (void *)pcb, arg, len, (u16_t)flags, (u16_t)copy));
+  LWIP_ASSERT("tcp_enqueue: len == 0 || optlen == 0 (programmer violates API)",
+      len == 0 || optlen == 0);
+  LWIP_ASSERT("tcp_enqueue: arg == NULL || optdata == NULL (programmer violates API)",
+      arg == NULL || optdata == NULL);
+  /* fail on too much data */
+  if (len > pcb->snd_buf) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too much data (len=%"U16_F" > snd_buf=%"U16_F")\n", len, pcb->snd_buf));
+    return ERR_MEM;
+  }
+  left = len;
+  ptr = arg;
+
+  /* seqno will be the sequence number of the first segment enqueued
+   * by the call to this function. */
+  seqno = pcb->snd_lbb;
+
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen));
+
+  /* If total number of pbufs on the unsent/unacked queues exceeds the
+   * configured maximum, return an error */
+  queuelen = pcb->snd_queuelen;
+  if (queuelen >= TCP_SND_QUEUELEN) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too long queue %"U16_F" (max %"U16_F")\n", queuelen, TCP_SND_QUEUELEN));
+    TCP_STATS_INC(tcp.memerr);
+    return ERR_MEM;
+  }
+  if (queuelen != 0) {
+    LWIP_ASSERT("tcp_enqueue: pbufs on queue => at least one queue non-empty",
+      pcb->unacked != NULL || pcb->unsent != NULL);
+  } else {
+    LWIP_ASSERT("tcp_enqueue: no pbufs on queue => both queues empty",
+      pcb->unacked == NULL && pcb->unsent == NULL);
+  }
+
+  /* First, break up the data into segments and tuck them together in
+   * the local "queue" variable. */
+  useg = queue = seg = NULL;
+  seglen = 0;
+  while (queue == NULL || left > 0) {
+
+    /* The segment length should be the MSS if the data to be enqueued
+     * is larger than the MSS. */
+    seglen = left > pcb->mss? pcb->mss: left;
+
+    /* Allocate memory for tcp_seg, and fill in fields. */
+    seg = memp_malloc(MEMP_TCP_SEG);
+    if (seg == NULL) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for tcp_seg\n"));
+      goto memerr;
+    }
+    seg->next = NULL;
+    seg->p = NULL;
+
+    /* first segment of to-be-queued data? */
+    if (queue == NULL) {
+      queue = seg;
+    }
+    /* subsequent segments of to-be-queued data */
+    else {
+      /* Attach the segment to the end of the queued segments */
+      LWIP_ASSERT("useg != NULL", useg != NULL);
+      useg->next = seg;
+    }
+    /* remember last segment of to-be-queued data for next iteration */
+    useg = seg;
+
+    /* If copy is set, memory should be allocated
+     * and data copied into pbuf, otherwise data comes from
+     * ROM or other static memory, and need not be copied. If
+     * optdata is != NULL, we have options instead of data. */
+     
+    /* options? */
+    if (optdata != NULL) {
+      if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) {
+        goto memerr;
+      }
+      ++queuelen;
+      seg->dataptr = seg->p->payload;
+    }
+    /* copy from volatile memory? */
+    else if (copy) {
+      if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_RAM)) == NULL) {
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue : could not allocate memory for pbuf copy size %"U16_F"\n", seglen));
+        goto memerr;
+      }
+      ++queuelen;
+      if (arg != NULL) {
+        memcpy(seg->p->payload, ptr, seglen);
+      }
+      seg->dataptr = seg->p->payload;
+    }
+    /* do not copy data */
+    else {
+      /* First, allocate a pbuf for holding the data.
+       * since the referenced data is available at least until it is sent out on the
+       * link (as it has to be ACKed by the remote party) we can safely use PBUF_ROM
+       * instead of PBUF_REF here.
+       */
+      if ((p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_ROM)) == NULL) {
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for zero-copy pbuf\n"));
+        goto memerr;
+      }
+      ++queuelen;
+      /* reference the non-volatile payload data */
+      p->payload = ptr;
+      seg->dataptr = ptr;
+
+      /* Second, allocate a pbuf for the headers. */
+      if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_RAM)) == NULL) {
+        /* If allocation fails, we have to deallocate the data pbuf as
+         * well. */
+        pbuf_free(p);
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for header pbuf\n"));
+        goto memerr;
+      }
+      ++queuelen;
+
+      /* Concatenate the headers and data pbufs together. */
+      pbuf_cat(seg->p/*header*/, p/*data*/);
+      p = NULL;
+    }
+
+    /* Now that there are more segments queued, we check again if the
+    length of the queue exceeds the configured maximum. */
+    if (queuelen > TCP_SND_QUEUELEN) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: queue too long %"U16_F" (%"U16_F")\n", queuelen, TCP_SND_QUEUELEN));
+      goto memerr;
+    }
+
+    seg->len = seglen;
+
+    /* build TCP header */
+    if (pbuf_header(seg->p, TCP_HLEN)) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: no room for TCP header in pbuf.\n"));
+      TCP_STATS_INC(tcp.err);
+      goto memerr;
+    }
+    seg->tcphdr = seg->p->payload;
+    seg->tcphdr->src = htons(pcb->local_port);
+    seg->tcphdr->dest = htons(pcb->remote_port);
+    seg->tcphdr->seqno = htonl(seqno);
+    seg->tcphdr->urgp = 0;
+    TCPH_FLAGS_SET(seg->tcphdr, flags);
+    /* don't fill in tcphdr->ackno and tcphdr->wnd until later */
+
+    /* Copy the options into the header, if they are present. */
+    if (optdata == NULL) {
+      TCPH_HDRLEN_SET(seg->tcphdr, 5);
+    }
+    else {
+      TCPH_HDRLEN_SET(seg->tcphdr, (5 + optlen / 4));
+      /* Copy options into data portion of segment.
+       Options can thus only be sent in non data carrying
+       segments such as SYN|ACK. */
+      memcpy(seg->dataptr, optdata, optlen);
+    }
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE, ("tcp_enqueue: queueing %"U32_F":%"U32_F" (0x%"X16_F")\n",
+      ntohl(seg->tcphdr->seqno),
+      ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg),
+      (u16_t)flags));
+
+    left -= seglen;
+    seqno += seglen;
+    ptr = (void *)((u8_t *)ptr + seglen);
+  }
+
+  /* Now that the data to be enqueued has been broken up into TCP
+  segments in the queue variable, we add them to the end of the
+  pcb->unsent queue. */
+  if (pcb->unsent == NULL) {
+    useg = NULL;
+  }
+  else {
+    for (useg = pcb->unsent; useg->next != NULL; useg = useg->next);
+  }
+  /* { useg is last segment on the unsent queue, NULL if list is empty } */
+
+  /* If there is room in the last pbuf on the unsent queue,
+  chain the first pbuf on the queue together with that. */
+  if (useg != NULL &&
+    TCP_TCPLEN(useg) != 0 &&
+    !(TCPH_FLAGS(useg->tcphdr) & (TCP_SYN | TCP_FIN)) &&
+    !(flags & (TCP_SYN | TCP_FIN)) &&
+    /* fit within max seg size */
+    useg->len + queue->len <= pcb->mss) {
+    /* Remove TCP header from first segment of our to-be-queued list */
+    pbuf_header(queue->p, -TCP_HLEN);
+    pbuf_cat(useg->p, queue->p);
+    useg->len += queue->len;
+    useg->next = queue->next;
+
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE | DBG_STATE, ("tcp_enqueue: chaining segments, new len %"U16_F"\n", useg->len));
+    if (seg == queue) {
+      seg = NULL;
+    }
+    memp_free(MEMP_TCP_SEG, queue);
+  }
+  else {
+    /* empty list */
+    if (useg == NULL) {
+      /* initialize list with this segment */
+      pcb->unsent = queue;
+    }
+    /* enqueue segment */
+    else {
+      useg->next = queue;
+    }
+  }
+  if ((flags & TCP_SYN) || (flags & TCP_FIN)) {
+    ++len;
+  }
+  pcb->snd_lbb += len;
+
+  pcb->snd_buf -= len;
+
+  /* update number of segments on the queues */
+  pcb->snd_queuelen = queuelen;
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: %"S16_F" (after enqueued)\n", pcb->snd_queuelen));
+  if (pcb->snd_queuelen != 0) {
+    LWIP_ASSERT("tcp_enqueue: valid queue length",
+      pcb->unacked != NULL || pcb->unsent != NULL);
+  }
+
+  /* Set the PSH flag in the last segment that we enqueued, but only
+  if the segment has data (indicated by seglen > 0). */
+  if (seg != NULL && seglen > 0 && seg->tcphdr != NULL) {
+    TCPH_SET_FLAG(seg->tcphdr, TCP_PSH);
+  }
+
+  return ERR_OK;
+memerr:
+  TCP_STATS_INC(tcp.memerr);
+
+  if (queue != NULL) {
+    tcp_segs_free(queue);
+  }
+  if (pcb->snd_queuelen != 0) {
+    LWIP_ASSERT("tcp_enqueue: valid queue length", pcb->unacked != NULL ||
+      pcb->unsent != NULL);
+  }
+  LWIP_DEBUGF(TCP_QLEN_DEBUG | DBG_STATE, ("tcp_enqueue: %"S16_F" (with mem err)\n", pcb->snd_queuelen));
+  return ERR_MEM;
+}
+
+/* find out what we can send and send it */
+err_t
+tcp_output(struct tcp_pcb *pcb)
+{
+  struct pbuf *p;
+  struct tcp_hdr *tcphdr;
+  struct tcp_seg *seg, *useg;
+  u32_t wnd;
+#if TCP_CWND_DEBUG
+  s16_t i = 0;
+#endif /* TCP_CWND_DEBUG */
+
+  /* First, check if we are invoked by the TCP input processing
+     code. If so, we do not output anything. Instead, we rely on the
+     input processing code to call us when input processing is done
+     with. */
+  if (tcp_input_pcb == pcb) {
+    return ERR_OK;
+  }
+
+  wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd);
+
+  seg = pcb->unsent;
+
+  /* useg should point to last segment on unacked queue */
+  useg = pcb->unacked;
+  if (useg != NULL) {
+    for (; useg->next != NULL; useg = useg->next);
+  }                                                                             
+   
+  /* If the TF_ACK_NOW flag is set and no data will be sent (either
+   * because the ->unsent queue is empty or because the window does
+   * not allow it), construct an empty ACK segment and send it.
+   *
+   * If data is to be sent, we will just piggyback the ACK (see below).
+   */
+  if (pcb->flags & TF_ACK_NOW &&
+     (seg == NULL ||
+      ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd)) {
+    p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
+    if (p == NULL) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n"));
+      return ERR_BUF;
+    }
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt));
+    /* remove ACK flags from the PCB, as we send an empty ACK now */
+    pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
+
+    tcphdr = p->payload;
+    tcphdr->src = htons(pcb->local_port);
+    tcphdr->dest = htons(pcb->remote_port);
+    tcphdr->seqno = htonl(pcb->snd_nxt);
+    tcphdr->ackno = htonl(pcb->rcv_nxt);
+    TCPH_FLAGS_SET(tcphdr, TCP_ACK);
+    tcphdr->wnd = htons(pcb->rcv_wnd);
+    tcphdr->urgp = 0;
+    TCPH_HDRLEN_SET(tcphdr, 5);
+
+    tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+    tcphdr->chksum = inet_chksum_pseudo(p, &(pcb->local_ip), &(pcb->remote_ip),
+          IP_PROTO_TCP, p->tot_len);
+#endif
+    ip_output(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,
+        IP_PROTO_TCP);
+    pbuf_free(p);
+
+    return ERR_OK;
+  }
+
+#if TCP_OUTPUT_DEBUG
+  if (seg == NULL) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: nothing to send (%p)\n", (void*)pcb->unsent));
+  }
+#endif /* TCP_OUTPUT_DEBUG */
+#if TCP_CWND_DEBUG
+  if (seg == NULL) {
+    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", seg == NULL, ack %"U32_F"\n",
+                            pcb->snd_wnd, pcb->cwnd, wnd,
+                            pcb->lastack));
+  } else {
+    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F"\n",
+                            pcb->snd_wnd, pcb->cwnd, wnd,
+                            ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len,
+                            ntohl(seg->tcphdr->seqno), pcb->lastack));
+  }
+#endif /* TCP_CWND_DEBUG */
+  /* data available and window allows it to be sent? */
+  while (seg != NULL &&
+  ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) {
+#if TCP_CWND_DEBUG
+    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F", i %"S16_F"\n",
+                            pcb->snd_wnd, pcb->cwnd, wnd,
+                            ntohl(seg->tcphdr->seqno) + seg->len -
+                            pcb->lastack,
+                            ntohl(seg->tcphdr->seqno), pcb->lastack, i));
+    ++i;
+#endif /* TCP_CWND_DEBUG */
+
+    pcb->unsent = seg->next;
+
+    if (pcb->state != SYN_SENT) {
+      TCPH_SET_FLAG(seg->tcphdr, TCP_ACK);
+      pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
+    }
+
+    tcp_output_segment(seg, pcb);
+    pcb->snd_nxt = ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);
+    if (TCP_SEQ_LT(pcb->snd_max, pcb->snd_nxt)) {
+      pcb->snd_max = pcb->snd_nxt;
+    }
+    /* put segment on unacknowledged list if length > 0 */
+    if (TCP_TCPLEN(seg) > 0) {
+      seg->next = NULL;
+      /* unacked list is empty? */
+      if (pcb->unacked == NULL) {
+        pcb->unacked = seg;
+        useg = seg;
+      /* unacked list is not empty? */
+      } else {
+        /* In the case of fast retransmit, the packet should not go to the tail
+         * of the unacked queue, but rather at the head. We need to check for
+         * this case. -STJ Jul 27, 2004 */
+        if (TCP_SEQ_LT(ntohl(seg->tcphdr->seqno), ntohl(useg->tcphdr->seqno))){
+          /* add segment to head of unacked list */
+          seg->next = pcb->unacked;
+          pcb->unacked = seg;
+        } else {
+          /* add segment to tail of unacked list */
+          useg->next = seg;
+          useg = useg->next;
+        }
+      }
+    /* do not queue empty segments on the unacked list */
+    } else {
+      tcp_seg_free(seg);
+    }
+    seg = pcb->unsent;
+  }
+  return ERR_OK;
+}
+
+/**
+ * Actually send a TCP segment over IP
+ */
+static void
+tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb)
+{
+  u16_t len;
+  struct netif *netif;
+
+  /** @bug Exclude retransmitted segments from this count. */
+  snmp_inc_tcpoutsegs();
+
+  /* The TCP header has already been constructed, but the ackno and
+   wnd fields remain. */
+  seg->tcphdr->ackno = htonl(pcb->rcv_nxt);
+
+  /* silly window avoidance */
+  if (pcb->rcv_wnd < pcb->mss) {
+    seg->tcphdr->wnd = 0;
+  } else {
+    /* advertise our receive window size in this TCP segment */
+    seg->tcphdr->wnd = htons(pcb->rcv_wnd);
+  }
+
+  /* If we don't have a local IP address, we get one by
+     calling ip_route(). */
+  if (ip_addr_isany(&(pcb->local_ip))) {
+    netif = ip_route(&(pcb->remote_ip));
+    if (netif == NULL) {
+      return;
+    }
+    ip_addr_set(&(pcb->local_ip), &(netif->ip_addr));
+  }
+
+  pcb->rtime = 0;
+
+  if (pcb->rttest == 0) {
+    pcb->rttest = tcp_ticks;
+    pcb->rtseq = ntohl(seg->tcphdr->seqno);
+
+    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_output_segment: rtseq %"U32_F"\n", pcb->rtseq));
+  }
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n",
+          htonl(seg->tcphdr->seqno), htonl(seg->tcphdr->seqno) +
+          seg->len));
+
+  len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload);
+
+  seg->p->len -= len;
+  seg->p->tot_len -= len;
+
+  seg->p->payload = seg->tcphdr;
+
+  seg->tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+  seg->tcphdr->chksum = inet_chksum_pseudo(seg->p,
+             &(pcb->local_ip),
+             &(pcb->remote_ip),
+             IP_PROTO_TCP, seg->p->tot_len);
+#endif
+  TCP_STATS_INC(tcp.xmit);
+
+  ip_output(seg->p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,
+      IP_PROTO_TCP);
+}
+
+void
+tcp_rst(u32_t seqno, u32_t ackno,
+  struct ip_addr *local_ip, struct ip_addr *remote_ip,
+  u16_t local_port, u16_t remote_port)
+{
+  struct pbuf *p;
+  struct tcp_hdr *tcphdr;
+  p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
+  if (p == NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n"));
+      return;
+  }
+
+  tcphdr = p->payload;
+  tcphdr->src = htons(local_port);
+  tcphdr->dest = htons(remote_port);
+  tcphdr->seqno = htonl(seqno);
+  tcphdr->ackno = htonl(ackno);
+  TCPH_FLAGS_SET(tcphdr, TCP_RST | TCP_ACK);
+  tcphdr->wnd = htons(TCP_WND);
+  tcphdr->urgp = 0;
+  TCPH_HDRLEN_SET(tcphdr, 5);
+
+  tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+  tcphdr->chksum = inet_chksum_pseudo(p, local_ip, remote_ip,
+              IP_PROTO_TCP, p->tot_len);
+#endif
+  TCP_STATS_INC(tcp.xmit);
+  snmp_inc_tcpoutrsts();
+   /* Send output with hardcoded TTL since we have no access to the pcb */
+  ip_output(p, local_ip, remote_ip, TCP_TTL, 0, IP_PROTO_TCP);
+  pbuf_free(p);
+  LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno));
+}
+
+/* requeue all unacked segments for retransmission */
+void
+tcp_rexmit_rto(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *seg;
+
+  if (pcb->unacked == NULL) {
+    return;
+  }
+
+  /* Move all unacked segments to the head of the unsent queue */
+  for (seg = pcb->unacked; seg->next != NULL; seg = seg->next);
+  /* concatenate unsent queue after unacked queue */
+  seg->next = pcb->unsent;
+  /* unsent queue is the concatenated queue (of unacked, unsent) */
+  pcb->unsent = pcb->unacked;
+  /* unacked queue is now empty */
+  pcb->unacked = NULL;
+
+  pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno);
+  /* increment number of retransmissions */
+  ++pcb->nrtx;
+
+  /* Don't take any RTT measurements after retransmitting. */
+  pcb->rttest = 0;
+
+  /* Do the actual retransmission */
+  tcp_output(pcb);
+}
+
+void
+tcp_rexmit(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *seg;
+
+  if (pcb->unacked == NULL) {
+    return;
+  }
+
+  /* Move the first unacked segment to the unsent queue */
+  seg = pcb->unacked->next;
+  pcb->unacked->next = pcb->unsent;
+  pcb->unsent = pcb->unacked;
+  pcb->unacked = seg;
+
+  pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno);
+
+  ++pcb->nrtx;
+
+  /* Don't take any rtt measurements after retransmitting. */
+  pcb->rttest = 0;
+
+  /* Do the actual retransmission. */
+  snmp_inc_tcpretranssegs();
+  tcp_output(pcb);
+
+}
+
+
+void
+tcp_keepalive(struct tcp_pcb *pcb)
+{
+   struct pbuf *p;
+   struct tcp_hdr *tcphdr;
+
+   LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: sending KEEPALIVE probe to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+                           ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+                           ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip)));
+
+   LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F"   pcb->tmr %"U32_F"  pcb->keep_cnt %"U16_F"\n", tcp_ticks, pcb->tmr, pcb->keep_cnt));
+   
+   p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
+
+   if(p == NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: could not allocate memory for pbuf\n"));
+      return;
+   }
+
+   tcphdr = p->payload;
+   tcphdr->src = htons(pcb->local_port);
+   tcphdr->dest = htons(pcb->remote_port);
+   tcphdr->seqno = htonl(pcb->snd_nxt - 1);
+   tcphdr->ackno = htonl(pcb->rcv_nxt);
+   tcphdr->wnd = htons(pcb->rcv_wnd);
+   tcphdr->urgp = 0;
+   TCPH_HDRLEN_SET(tcphdr, 5);
+   
+   tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+   tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip, IP_PROTO_TCP, p->tot_len);
+#endif
+  TCP_STATS_INC(tcp.xmit);
+
+   /* Send output to IP */
+  ip_output(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP);
+
+  pbuf_free(p);
+
+  LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F".\n", pcb->snd_nxt - 1, pcb->rcv_nxt));
+}
+
+#endif /* LWIP_TCP */
+
+
+
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/udp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/udp.c
new file mode 100644
index 0000000..3d5980f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/core/udp.c
@@ -0,0 +1,665 @@
+/**
+ * @file
+ * User Datagram Protocol module
+ *
+ */
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+/* udp.c
+ *
+ * The code for the User Datagram Protocol UDP.
+ *
+ */
+
+#include 
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/memp.h"
+#include "lwip/inet.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+#include "lwip/icmp.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+#include "lwip/snmp.h"
+
+/* The list of UDP PCBs */
+#if LWIP_UDP
+/* exported in udp.h (was static) */
+struct udp_pcb *udp_pcbs = NULL;
+
+static struct udp_pcb *pcb_cache = NULL;
+
+void
+udp_init(void)
+{
+  udp_pcbs = pcb_cache = NULL;
+}
+
+/**
+ * Process an incoming UDP datagram.
+ *
+ * Given an incoming UDP datagram (as a chain of pbufs) this function
+ * finds a corresponding UDP PCB and
+ *
+ * @param pbuf pbuf to be demultiplexed to a UDP PCB.
+ * @param netif network interface on which the datagram was received.
+ *
+ */
+void
+udp_input(struct pbuf *p, struct netif *inp)
+{
+  struct udp_hdr *udphdr;
+  struct udp_pcb *pcb;
+  struct udp_pcb *uncon_pcb;
+  struct ip_hdr *iphdr;
+  u16_t src, dest;
+  u8_t local_match;
+
+  PERF_START;
+
+  UDP_STATS_INC(udp.recv);
+
+  iphdr = p->payload;
+
+  if (p->tot_len < (IPH_HL(iphdr) * 4 + UDP_HLEN)) {
+    /* drop short packets */
+//    LWIP_DEBUGF(UDP_DEBUG,
+//                ("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len));
+
+    LWIP_DEBUGF(UDP_DEBUG,
+                ("udp_input: short UDP datagram (%u bytes) discarded\n", p->tot_len));
+
+    UDP_STATS_INC(udp.lenerr);
+    UDP_STATS_INC(udp.drop);
+    snmp_inc_udpinerrors();
+    pbuf_free(p);
+    goto end;
+  }
+
+  pbuf_header(p, -((s16_t)(IPH_HL(iphdr) * 4)));
+
+  udphdr = (struct udp_hdr *)p->payload;
+
+  LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len));
+
+  src = ntohs(udphdr->src);
+  dest = ntohs(udphdr->dest);
+
+  udp_debug_print(udphdr);
+
+  /* print the UDP source and destination */
+  LWIP_DEBUGF(UDP_DEBUG,
+              ("udp (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") <-- "
+               "(%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n",
+               ip4_addr1(&iphdr->dest), ip4_addr2(&iphdr->dest),
+               ip4_addr3(&iphdr->dest), ip4_addr4(&iphdr->dest), ntohs(udphdr->dest),
+               ip4_addr1(&iphdr->src), ip4_addr2(&iphdr->src),
+               ip4_addr3(&iphdr->src), ip4_addr4(&iphdr->src), ntohs(udphdr->src)));
+
+  local_match = 0;
+  uncon_pcb = NULL;
+  /* Iterate through the UDP pcb list for a matching pcb */
+  for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
+    /* print the PCB local and remote address */
+    LWIP_DEBUGF(UDP_DEBUG,
+                ("pcb (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") --- "
+                 "(%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n",
+                 ip4_addr1(&pcb->local_ip), ip4_addr2(&pcb->local_ip),
+                 ip4_addr3(&pcb->local_ip), ip4_addr4(&pcb->local_ip), pcb->local_port,
+                 ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+                 ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip), pcb->remote_port));
+
+    /* compare PCB local addr+port to UDP destination addr+port */
+    if ((pcb->local_port == dest) &&
+        (ip_addr_isany(&pcb->local_ip) ||
+         ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest)) || 
+         ip_addr_isbroadcast(&(iphdr->dest), inp))) {
+      local_match = 1;
+      if ((uncon_pcb == NULL) && 
+          ((pcb->flags & UDP_FLAGS_CONNECTED) == 0)) {
+        /* the first unconnected matching PCB */     
+        uncon_pcb = pcb;
+      }
+    }
+    /* compare PCB remote addr+port to UDP source addr+port */
+    if ((local_match != 0) &&
+        (pcb->remote_port == src) &&
+        (ip_addr_isany(&pcb->remote_ip) ||
+         ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)))) {
+      /* the first fully matching PCB */
+      break;
+    }
+  }
+  /* no fully matching pcb found? then look for an unconnected pcb */
+  if (pcb == NULL) {
+    pcb = uncon_pcb;
+  }
+
+  /* Check checksum if this is a match or if it was directed at us. */
+  if (pcb != NULL || ip_addr_cmp(&inp->ip_addr, &iphdr->dest)) {
+    LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE, ("udp_input: calculating checksum\n"));
+#ifdef IPv6
+    if (iphdr->nexthdr == IP_PROTO_UDPLITE) {
+#else
+    if (IPH_PROTO(iphdr) == IP_PROTO_UDPLITE) {
+#endif /* IPv4 */
+      /* Do the UDP Lite checksum */
+#if CHECKSUM_CHECK_UDP
+      if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
+                             (struct ip_addr *)&(iphdr->dest),
+                             IP_PROTO_UDPLITE, ntohs(udphdr->len)) != 0) {
+        LWIP_DEBUGF(UDP_DEBUG | 2,
+                    ("udp_input: UDP Lite datagram discarded due to failing checksum\n"));
+        UDP_STATS_INC(udp.chkerr);
+        UDP_STATS_INC(udp.drop);
+        snmp_inc_udpinerrors();
+        pbuf_free(p);
+        goto end;
+      }
+#endif
+    } else {
+#if CHECKSUM_CHECK_UDP
+      if (udphdr->chksum != 0) {
+        if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
+                               (struct ip_addr *)&(iphdr->dest),
+                               IP_PROTO_UDP, p->tot_len) != 0) {
+          LWIP_DEBUGF(UDP_DEBUG | 2,
+                      ("udp_input: UDP datagram discarded due to failing checksum\n"));
+          UDP_STATS_INC(udp.chkerr);
+          UDP_STATS_INC(udp.drop);
+          snmp_inc_udpinerrors();
+          pbuf_free(p);
+          goto end;
+        }
+      }
+#endif
+    }
+    pbuf_header(p, -UDP_HLEN);
+    if (pcb != NULL) {
+      snmp_inc_udpindatagrams();
+      /* callback */
+      if (pcb->recv != NULL)
+        pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src), src);
+    } else {
+      LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE, ("udp_input: not for us.\n"));
+
+      /* No match was found, send ICMP destination port unreachable unless
+         destination address was broadcast/multicast. */
+
+      if (!ip_addr_isbroadcast(&iphdr->dest, inp) &&
+          !ip_addr_ismulticast(&iphdr->dest)) {
+
+        /* restore pbuf pointer */
+        p->payload = iphdr;
+        icmp_dest_unreach(p, ICMP_DUR_PORT);
+      }
+      UDP_STATS_INC(udp.proterr);
+      UDP_STATS_INC(udp.drop);
+      snmp_inc_udpnoports();
+      pbuf_free(p);
+    }
+  } else {
+    pbuf_free(p);
+  }
+end:
+  PERF_STOP("udp_input");
+}
+
+/**
+ * Send data to a specified address using UDP.
+ *
+ * @param pcb UDP PCB used to send the data.
+ * @param pbuf chain of pbuf's to be sent.
+ * @param dst_ip Destination IP address.
+ * @param dst_port Destination UDP port.
+ *
+ * If the PCB already has a remote address association, it will
+ * be restored after the data is sent.
+ * 
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_MEM. Out of memory.
+ * - ERR_RTE. Could not find route to destination address.
+ *
+ * @see udp_disconnect() udp_send()
+ */
+err_t
+udp_sendto(struct udp_pcb *pcb, struct pbuf *p,
+  struct ip_addr *dst_ip, u16_t dst_port)
+{
+  err_t err;
+  /* temporary space for current PCB remote address */
+  struct ip_addr pcb_remote_ip;
+  u16_t pcb_remote_port;
+  /* remember current remote peer address of PCB */
+  pcb_remote_ip.addr = pcb->remote_ip.addr;
+  pcb_remote_port = pcb->remote_port;
+  /* copy packet destination address to PCB remote peer address */
+  pcb->remote_ip.addr = dst_ip->addr;
+  pcb->remote_port = dst_port;
+  /* send to the packet destination address */
+  err = udp_send(pcb, p);
+  /* restore PCB remote peer address */
+  pcb->remote_ip.addr = pcb_remote_ip.addr;
+  pcb->remote_port = pcb_remote_port;
+  return err;
+}
+
+/**
+ * Send data using UDP.
+ *
+ * @param pcb UDP PCB used to send the data.
+ * @param pbuf chain of pbuf's to be sent.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_MEM. Out of memory.
+ * - ERR_RTE. Could not find route to destination address.
+ *
+ * @see udp_disconnect() udp_sendto()
+ */
+err_t
+udp_send(struct udp_pcb *pcb, struct pbuf *p)
+{
+  struct udp_hdr *udphdr;
+  struct netif *netif;
+  struct ip_addr *src_ip;
+  err_t err;
+  struct pbuf *q; /* q will be sent down the stack */
+
+  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, ("udp_send\n"));
+
+  /* if the PCB is not yet bound to a port, bind it here */
+  if (pcb->local_port == 0) {
+    LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: not yet bound to a port, binding now\n"));
+    err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
+    if (err != ERR_OK) {
+      LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: forced port bind failed\n"));
+      return err;
+    }
+  }
+  /* find the outgoing network interface for this packet */
+  netif = ip_route(&(pcb->remote_ip));
+  /* no outgoing network interface could be found? */
+  if (netif == NULL) {
+    LWIP_DEBUGF(UDP_DEBUG | 1, ("udp_send: No route to 0x%"X32_F"\n", pcb->remote_ip.addr));
+    UDP_STATS_INC(udp.rterr);
+    return ERR_RTE;
+  }
+
+  /* not enough space to add an UDP header to first pbuf in given p chain? */
+  if (pbuf_header(p, UDP_HLEN)) {
+    /* allocate header in a seperate new pbuf */
+    q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM);
+    /* new header pbuf could not be allocated? */
+    if (q == NULL) {
+      LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: could not allocate header\n"));
+      return ERR_MEM;
+    }
+    /* chain header q in front of given pbuf p */
+    pbuf_chain(q, p);
+    /* first pbuf q points to header pbuf */
+    LWIP_DEBUGF(UDP_DEBUG,
+                ("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
+    /* adding a header within p succeeded */
+  } else {
+    /* first pbuf q equals given pbuf */
+    q = p;
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p));
+  }
+  /* q now represents the packet to be sent */
+  udphdr = q->payload;
+  udphdr->src = htons(pcb->local_port);
+  udphdr->dest = htons(pcb->remote_port);
+  /* in UDP, 0 checksum means 'no checksum' */
+  udphdr->chksum = 0x0000; 
+
+  /* PCB local address is IP_ANY_ADDR? */
+  if (ip_addr_isany(&pcb->local_ip)) {
+    /* use outgoing network interface IP address as source address */
+    src_ip = &(netif->ip_addr);
+  } else {
+    /* use UDP PCB local IP address as source address */
+    src_ip = &(pcb->local_ip);
+  }
+
+  LWIP_DEBUGF(UDP_DEBUG, ("udp_send: sending datagram of length %"U16_F"\n", q->tot_len));
+
+  /* UDP Lite protocol? */
+  if (pcb->flags & UDP_FLAGS_UDPLITE) {
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE packet length %"U16_F"\n", q->tot_len));
+    /* set UDP message length in UDP header */
+    udphdr->len = htons(pcb->chksum_len);
+    /* calculate checksum */
+#if CHECKSUM_GEN_UDP
+    udphdr->chksum = inet_chksum_pseudo(q, src_ip, &(pcb->remote_ip),
+                                        IP_PROTO_UDP, pcb->chksum_len);
+    /* chksum zero must become 0xffff, as zero means 'no checksum' */
+    if (udphdr->chksum == 0x0000)
+      udphdr->chksum = 0xffff;
+#else
+    udphdr->chksum = 0x0000;
+#endif
+    /* output to IP */
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDPLITE,)\n"));
+    err = ip_output_if(q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDPLITE, netif);    
+  } else {      /* UDP */
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %"U16_F"\n", q->tot_len));
+    udphdr->len = htons(q->tot_len);
+    /* calculate checksum */
+#if CHECKSUM_GEN_UDP
+    if ((pcb->flags & UDP_FLAGS_NOCHKSUM) == 0) {
+      udphdr->chksum = inet_chksum_pseudo(q, src_ip, &pcb->remote_ip, IP_PROTO_UDP, q->tot_len);
+      /* chksum zero must become 0xffff, as zero means 'no checksum' */
+      if (udphdr->chksum == 0x0000) udphdr->chksum = 0xffff;
+    }
+#else
+    udphdr->chksum = 0x0000;
+#endif
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04"X16_F"\n", udphdr->chksum));
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDP,)\n"));
+    /* output to IP */
+    err = ip_output_if(q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDP, netif);    
+  }
+  /* TODO: must this be increased even if error occured? */
+  snmp_inc_udpoutdatagrams();
+
+  /* did we chain a seperate header pbuf earlier? */
+  if (q != p) {
+    /* free the header pbuf */
+    pbuf_free(q);
+    q = NULL;
+    /* p is still referenced by the caller, and will live on */
+  }
+
+  UDP_STATS_INC(udp.xmit);
+  return err;
+}
+
+/**
+ * Bind an UDP PCB.
+ *
+ * @param pcb UDP PCB to be bound with a local address ipaddr and port.
+ * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to
+ * bind to all local interfaces.
+ * @param port local UDP port to bind with.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_USE. The specified ipaddr and port are already bound to by
+ * another UDP PCB.
+ *
+ * @see udp_disconnect()
+ */
+err_t
+udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
+{
+  struct udp_pcb *ipcb;
+  u8_t rebind;
+
+  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, ("udp_bind(ipaddr = "));
+  ip_addr_debug_print(UDP_DEBUG, ipaddr);
+  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, (", port = %"U16_F")\n", port));
+
+  rebind = 0;
+  /* Check for double bind and rebind of the same pcb */
+  for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+    /* is this UDP PCB already on active list? */
+    if (pcb == ipcb) {
+      /* pcb may occur at most once in active list */
+      LWIP_ASSERT("rebind == 0", rebind == 0);
+      /* pcb already in list, just rebind */
+      rebind = 1;
+    }
+
+    /* this code does not allow upper layer to share a UDP port for
+       listening to broadcast or multicast traffic (See SO_REUSE_ADDR and
+       SO_REUSE_PORT under *BSD). TODO: See where it fits instead, OR
+       combine with implementation of UDP PCB flags. Leon Woestenberg. */
+#ifdef LWIP_UDP_TODO
+    /* port matches that of PCB in list? */
+    else
+      if ((ipcb->local_port == port) &&
+          /* IP address matches, or one is IP_ADDR_ANY? */
+          (ip_addr_isany(&(ipcb->local_ip)) ||
+           ip_addr_isany(ipaddr) ||
+           ip_addr_cmp(&(ipcb->local_ip), ipaddr))) {
+        /* other PCB already binds to this local IP and port */
+        LWIP_DEBUGF(UDP_DEBUG,
+                    ("udp_bind: local port %"U16_F" already bound by another pcb\n", port));
+        return ERR_USE;
+      }
+#endif
+  }
+
+  ip_addr_set(&pcb->local_ip, ipaddr);
+
+  /* no port specified? */
+  if (port == 0) {
+#ifndef UDP_LOCAL_PORT_RANGE_START
+#define UDP_LOCAL_PORT_RANGE_START 4096
+#define UDP_LOCAL_PORT_RANGE_END   0x7fff
+#endif
+    port = UDP_LOCAL_PORT_RANGE_START;
+    ipcb = udp_pcbs;
+    while ((ipcb != NULL) && (port != UDP_LOCAL_PORT_RANGE_END)) {
+      if (ipcb->local_port == port) {
+        port++;
+        ipcb = udp_pcbs;
+      } else
+        ipcb = ipcb->next;
+    }
+    if (ipcb != NULL) {
+      /* no more ports available in local range */
+      LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n"));
+      return ERR_USE;
+    }
+  }
+  pcb->local_port = port;
+  snmp_insert_udpidx_tree(pcb);
+  /* pcb not active yet? */
+  if (rebind == 0) {
+    /* place the PCB on the active list if not already there */
+    pcb->next = udp_pcbs;
+    udp_pcbs = pcb;
+  }
+  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE,
+              ("udp_bind: bound to %"U16_F".%"U16_F".%"U16_F".%"U16_F", port %"U16_F"\n",
+               (u16_t)(ntohl(pcb->local_ip.addr) >> 24 & 0xff),
+               (u16_t)(ntohl(pcb->local_ip.addr) >> 16 & 0xff),
+               (u16_t)(ntohl(pcb->local_ip.addr) >> 8 & 0xff),
+               (u16_t)(ntohl(pcb->local_ip.addr) & 0xff), pcb->local_port));
+  return ERR_OK;
+}
+/**
+ * Connect an UDP PCB.
+ *
+ * This will associate the UDP PCB with the remote address.
+ *
+ * @param pcb UDP PCB to be connected with remote address ipaddr and port.
+ * @param ipaddr remote IP address to connect with.
+ * @param port remote UDP port to connect with.
+ *
+ * @return lwIP error code
+ *
+ * @see udp_disconnect()
+ */
+err_t
+udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
+{
+  struct udp_pcb *ipcb;
+
+  if (pcb->local_port == 0) {
+    err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
+    if (err != ERR_OK)
+      return err;
+  }
+
+  ip_addr_set(&pcb->remote_ip, ipaddr);
+  pcb->remote_port = port;
+  pcb->flags |= UDP_FLAGS_CONNECTED;
+/** TODO: this functionality belongs in upper layers */
+#ifdef LWIP_UDP_TODO
+  /* Nail down local IP for netconn_addr()/getsockname() */
+  if (ip_addr_isany(&pcb->local_ip) && !ip_addr_isany(&pcb->remote_ip)) {
+    struct netif *netif;
+
+    if ((netif = ip_route(&(pcb->remote_ip))) == NULL) {
+      LWIP_DEBUGF(UDP_DEBUG, ("udp_connect: No route to 0x%lx\n", pcb->remote_ip.addr));
+      UDP_STATS_INC(udp.rterr);
+      return ERR_RTE;
+    }
+    /** TODO: this will bind the udp pcb locally, to the interface which
+        is used to route output packets to the remote address. However, we
+        might want to accept incoming packets on any interface! */
+    pcb->local_ip = netif->ip_addr;
+  } else if (ip_addr_isany(&pcb->remote_ip)) {
+    pcb->local_ip.addr = 0;
+  }
+#endif
+  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE,
+              ("udp_connect: connected to %"U16_F".%"U16_F".%"U16_F".%"U16_F",port %"U16_F"\n",
+               (u16_t)(ntohl(pcb->remote_ip.addr) >> 24 & 0xff),
+               (u16_t)(ntohl(pcb->remote_ip.addr) >> 16 & 0xff),
+               (u16_t)(ntohl(pcb->remote_ip.addr) >> 8 & 0xff),
+               (u16_t)(ntohl(pcb->remote_ip.addr) & 0xff), pcb->remote_port));
+
+  /* Insert UDP PCB into the list of active UDP PCBs. */
+  for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+    if (pcb == ipcb) {
+      /* already on the list, just return */
+      return ERR_OK;
+    }
+  }
+  /* PCB not yet on the list, add PCB now */
+  pcb->next = udp_pcbs;
+  udp_pcbs = pcb;
+  return ERR_OK;
+}
+
+void
+udp_disconnect(struct udp_pcb *pcb)
+{
+  /* reset remote address association */
+  ip_addr_set(&pcb->remote_ip, IP_ADDR_ANY);
+  pcb->remote_port = 0;
+  /* mark PCB as unconnected */
+  pcb->flags &= ~UDP_FLAGS_CONNECTED;
+}
+
+void
+udp_recv(struct udp_pcb *pcb,
+         void (* recv)(void *arg, struct udp_pcb *upcb, struct pbuf *p,
+                       struct ip_addr *addr, u16_t port),
+         void *recv_arg)
+{
+  /* remember recv() callback and user data */
+  pcb->recv = recv;
+  pcb->recv_arg = recv_arg;
+}
+
+/**
+ * Remove an UDP PCB.
+ *
+ * @param pcb UDP PCB to be removed. The PCB is removed from the list of
+ * UDP PCB's and the data structure is freed from memory.
+ *
+ * @see udp_new()
+ */
+void
+udp_remove(struct udp_pcb *pcb)
+{
+  struct udp_pcb *pcb2;
+
+  snmp_delete_udpidx_tree(pcb);
+  /* pcb to be removed is first in list? */
+  if (udp_pcbs == pcb) {
+    /* make list start at 2nd pcb */
+    udp_pcbs = udp_pcbs->next;
+    /* pcb not 1st in list */
+  } else
+    for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
+      /* find pcb in udp_pcbs list */
+      if (pcb2->next != NULL && pcb2->next == pcb) {
+        /* remove pcb from list */
+        pcb2->next = pcb->next;
+      }
+    }
+  memp_free(MEMP_UDP_PCB, pcb);
+}
+
+/**
+ * Create a UDP PCB.
+ *
+ * @return The UDP PCB which was created. NULL if the PCB data structure
+ * could not be allocated.
+ *
+ * @see udp_remove()
+ */
+struct udp_pcb *
+udp_new(void)
+{
+  struct udp_pcb *pcb;
+  pcb = memp_malloc(MEMP_UDP_PCB);
+  /* could allocate UDP PCB? */
+  if (pcb != NULL) {
+    /* initialize PCB to all zeroes */
+    memset(pcb, 0, sizeof(struct udp_pcb));
+    pcb->ttl = UDP_TTL;
+  }
+  return pcb;
+}
+
+#if UDP_DEBUG
+void
+udp_debug_print(struct udp_hdr *udphdr)
+{
+  LWIP_DEBUGF(UDP_DEBUG, ("UDP header:\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("|     %5"U16_F"     |     %5"U16_F"     | (src port, dest port)\n",
+                          ntohs(udphdr->src), ntohs(udphdr->dest)));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("|     %5"U16_F"     |     0x%04"X16_F"    | (len, chksum)\n",
+                          ntohs(udphdr->len), ntohs(udphdr->chksum)));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+}
+#endif /* UDP_DEBUG */
+
+#endif /* LWIP_UDP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/ipv4/lwip/icmp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/ipv4/lwip/icmp.h
new file mode 100644
index 0000000..04307e7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/ipv4/lwip/icmp.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ICMP_H__
+#define __LWIP_ICMP_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+
+#define ICMP_ER 0      /* echo reply */
+#define ICMP_DUR 3     /* destination unreachable */
+#define ICMP_SQ 4      /* source quench */
+#define ICMP_RD 5      /* redirect */
+#define ICMP_ECHO 8    /* echo */
+#define ICMP_TE 11     /* time exceeded */
+#define ICMP_PP 12     /* parameter problem */
+#define ICMP_TS 13     /* timestamp */
+#define ICMP_TSR 14    /* timestamp reply */
+#define ICMP_IRQ 15    /* information request */
+#define ICMP_IR 16     /* information reply */
+
+enum icmp_dur_type {
+  ICMP_DUR_NET = 0,    /* net unreachable */
+  ICMP_DUR_HOST = 1,   /* host unreachable */
+  ICMP_DUR_PROTO = 2,  /* protocol unreachable */
+  ICMP_DUR_PORT = 3,   /* port unreachable */
+  ICMP_DUR_FRAG = 4,   /* fragmentation needed and DF set */
+  ICMP_DUR_SR = 5      /* source route failed */
+};
+
+enum icmp_te_type {
+  ICMP_TE_TTL = 0,     /* time to live exceeded in transit */
+  ICMP_TE_FRAG = 1     /* fragment reassembly time exceeded */
+};
+
+void icmp_input(struct pbuf *p, struct netif *inp);
+
+void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
+void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct icmp_echo_hdr {
+  PACK_STRUCT_FIELD(u16_t _type_code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u16_t id);
+  PACK_STRUCT_FIELD(u16_t seqno);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+
+PACK_STRUCT_BEGIN
+struct icmp_dur_hdr {
+  PACK_STRUCT_FIELD(u16_t _type_code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u32_t unused);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+
+PACK_STRUCT_BEGIN
+struct icmp_te_hdr {
+  PACK_STRUCT_FIELD(u16_t _type_code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u32_t unused);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define ICMPH_TYPE(hdr) (ntohs((hdr)->_type_code) >> 8)
+#define ICMPH_CODE(hdr) (ntohs((hdr)->_type_code) & 0xff)
+
+#define ICMPH_TYPE_SET(hdr, type) ((hdr)->_type_code = htons(ICMPH_CODE(hdr) | ((type) << 8)))
+#define ICMPH_CODE_SET(hdr, code) ((hdr)->_type_code = htons((code) | (ICMPH_TYPE(hdr) << 8)))
+
+#endif /* __LWIP_ICMP_H__ */
+    
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/ipv4/lwip/inet.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/ipv4/lwip/inet.h
new file mode 100644
index 0000000..9e77b74
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/ipv4/lwip/inet.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_INET_H__
+#define __LWIP_INET_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+u16_t inet_chksum(void *dataptr, u16_t len);
+#if 0 /* optimized routine */
+u16_t inet_chksum4(u8_t *dataptr, u16_t len);
+#endif
+u16_t inet_chksum_pbuf(struct pbuf *p);
+u16_t inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u16_t proto_len);
+
+u32_t inet_addr(const char *cp);
+int inet_aton(const char *cp, struct in_addr *addr);
+char *inet_ntoa(struct in_addr addr); /* returns ptr to static buffer; not reentrant! */
+
+#ifdef htons
+#undef htons
+#endif /* htons */
+#ifdef htonl
+#undef htonl
+#endif /* htonl */
+#ifdef ntohs
+#undef ntohs
+#endif /* ntohs */
+#ifdef ntohl
+#undef ntohl
+#endif /* ntohl */
+
+#ifndef LWIP_PLATFORM_BYTESWAP
+#define LWIP_PLATFORM_BYTESWAP 0
+#endif
+
+#if BYTE_ORDER == BIG_ENDIAN
+#define htons(x) (x)
+#define ntohs(x) (x)
+#define htonl(x) (x)
+#define ntohl(x) (x)
+#else /* BYTE_ORDER != BIG_ENDIAN */
+#ifdef LWIP_PREFIX_BYTEORDER_FUNCS
+/* workaround for naming collisions on some platforms */
+#define htons lwip_htons
+#define ntohs lwip_ntohs
+#define htonl lwip_htonl
+#define ntohl lwip_ntohl
+#endif
+#if LWIP_PLATFORM_BYTESWAP
+#define htons(x) LWIP_PLATFORM_HTONS(x)
+#define ntohs(x) LWIP_PLATFORM_HTONS(x)
+#define htonl(x) LWIP_PLATFORM_HTONL(x)
+#define ntohl(x) LWIP_PLATFORM_HTONL(x)
+#else
+u16_t htons(u16_t x);
+u16_t ntohs(u16_t x);
+u32_t htonl(u32_t x);
+u32_t ntohl(u32_t x);
+#endif
+
+#endif
+
+#endif /* __LWIP_INET_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/ipv4/lwip/ip.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/ipv4/lwip/ip.h
new file mode 100644
index 0000000..e5a8da0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/ipv4/lwip/ip.h
@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_H__
+#define __LWIP_IP_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+#include "lwip/err.h"
+
+
+void ip_init(void);
+struct netif *ip_route(struct ip_addr *dest);
+err_t ip_input(struct pbuf *p, struct netif *inp);
+err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+    u8_t ttl, u8_t tos, u8_t proto);
+err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+       u8_t ttl, u8_t tos, u8_t proto,
+       struct netif *netif);
+
+#define IP_HLEN 20
+
+#define IP_PROTO_ICMP 1
+#define IP_PROTO_UDP 17
+#define IP_PROTO_UDPLITE 136
+#define IP_PROTO_TCP 6
+
+/* This is passed as the destination address to ip_output_if (not
+   to ip_output), meaning that an IP header already is constructed
+   in the pbuf. This is used when TCP retransmits. */
+#ifdef IP_HDRINCL
+#undef IP_HDRINCL
+#endif /* IP_HDRINCL */
+#define IP_HDRINCL  NULL
+
+
+/* This is the common part of all PCB types. It needs to be at the
+   beginning of a PCB type definition. It is located here so that
+   changes to this common part are made in one location instead of
+   having to change all PCB structs. */
+#define IP_PCB struct ip_addr local_ip; \
+  struct ip_addr remote_ip; \
+   /* Socket options */  \
+  u16_t so_options;      \
+   /* Type Of Service */ \
+  u8_t tos;              \
+  /* Time To Live */     \
+  u8_t ttl
+
+/*
+ * Option flags per-socket. These are the same like SO_XXX.
+ */
+#define SOF_DEBUG     (u16_t)0x0001U    /* turn on debugging info recording */
+#define SOF_ACCEPTCONN  (u16_t)0x0002U    /* socket has had listen() */
+#define SOF_REUSEADDR (u16_t)0x0004U    /* allow local address reuse */
+#define SOF_KEEPALIVE (u16_t)0x0008U    /* keep connections alive */
+#define SOF_DONTROUTE (u16_t)0x0010U    /* just use interface addresses */
+#define SOF_BROADCAST (u16_t)0x0020U    /* permit sending of broadcast msgs */
+#define SOF_USELOOPBACK (u16_t)0x0040U    /* bypass hardware when possible */
+#define SOF_LINGER      (u16_t)0x0080U    /* linger on close if data present */
+#define SOF_OOBINLINE (u16_t)0x0100U    /* leave received OOB data in line */
+#define SOF_REUSEPORT (u16_t)0x0200U    /* allow local address & port reuse */
+
+
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_hdr {
+  /* version / header length / type of service */
+  PACK_STRUCT_FIELD(u16_t _v_hl_tos);
+  /* total length */
+  PACK_STRUCT_FIELD(u16_t _len);
+  /* identification */
+  PACK_STRUCT_FIELD(u16_t _id);
+  /* fragment offset field */
+  PACK_STRUCT_FIELD(u16_t _offset);
+#define IP_RF 0x8000        /* reserved fragment flag */
+#define IP_DF 0x4000        /* dont fragment flag */
+#define IP_MF 0x2000        /* more fragments flag */
+#define IP_OFFMASK 0x1fff   /* mask for fragmenting bits */
+  /* time to live / protocol*/
+  PACK_STRUCT_FIELD(u16_t _ttl_proto);
+  /* checksum */
+  PACK_STRUCT_FIELD(u16_t _chksum);
+  /* source and destination IP addresses */
+  PACK_STRUCT_FIELD(struct ip_addr src);
+  PACK_STRUCT_FIELD(struct ip_addr dest); 
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define IPH_V(hdr)  (ntohs((hdr)->_v_hl_tos) >> 12)
+#define IPH_HL(hdr) ((ntohs((hdr)->_v_hl_tos) >> 8) & 0x0f)
+#define IPH_TOS(hdr) (ntohs((hdr)->_v_hl_tos) & 0xff)
+#define IPH_LEN(hdr) ((hdr)->_len)
+#define IPH_ID(hdr) ((hdr)->_id)
+#define IPH_OFFSET(hdr) ((hdr)->_offset)
+#define IPH_TTL(hdr) (ntohs((hdr)->_ttl_proto) >> 8)
+#define IPH_PROTO(hdr) (ntohs((hdr)->_ttl_proto) & 0xff)
+#define IPH_CHKSUM(hdr) ((hdr)->_chksum)
+
+#define IPH_VHLTOS_SET(hdr, v, hl, tos) (hdr)->_v_hl_tos = (htons(((v) << 12) | ((hl) << 8) | (tos)))
+#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len)
+#define IPH_ID_SET(hdr, id) (hdr)->_id = (id)
+#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off)
+#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl_proto = (htons(IPH_PROTO(hdr) | ((u16_t)(ttl) << 8)))
+#define IPH_PROTO_SET(hdr, proto) (hdr)->_ttl_proto = (htons((proto) | (IPH_TTL(hdr) << 8)))
+#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum)
+
+#if IP_DEBUG
+void ip_debug_print(struct pbuf *p);
+#else
+#define ip_debug_print(p)
+#endif /* IP_DEBUG */
+
+#endif /* __LWIP_IP_H__ */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/ipv4/lwip/ip_addr.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/ipv4/lwip/ip_addr.h
new file mode 100644
index 0000000..1f0f754
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/ipv4/lwip/ip_addr.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_ADDR_H__
+#define __LWIP_IP_ADDR_H__
+
+#include "lwip/arch.h"
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_addr {
+  PACK_STRUCT_FIELD(u32_t addr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/*
+ * struct ipaddr2 is used in the definition of the ARP packet format in
+ * order to support compilers that don't have structure packing.
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_addr2 {
+  PACK_STRUCT_FIELD(u16_t addrw[2]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/* For compatibility with BSD code */
+struct in_addr {
+  u32_t s_addr;
+};
+
+struct netif;
+
+extern const struct ip_addr ip_addr_any;
+extern const struct ip_addr ip_addr_broadcast;
+
+/** IP_ADDR_ can be used as a fixed IP address
+ *  for the wildcard and the broadcast address
+ */
+#define IP_ADDR_ANY         ((struct ip_addr *)&ip_addr_any)
+#define IP_ADDR_BROADCAST   ((struct ip_addr *)&ip_addr_broadcast)
+
+#define INADDR_NONE         ((u32_t)0xffffffff)  /* 255.255.255.255 */
+#define INADDR_LOOPBACK     ((u32_t)0x7f000001)  /* 127.0.0.1 */
+
+/* Definitions of the bits in an Internet address integer.
+
+   On subnets, host and network parts are found according to
+   the subnet mask, not these masks.  */
+
+#define IN_CLASSA(a)        ((((u32_t)(a)) & 0x80000000) == 0)
+#define IN_CLASSA_NET       0xff000000
+#define IN_CLASSA_NSHIFT    24
+#define IN_CLASSA_HOST      (0xffffffff & ~IN_CLASSA_NET)
+#define IN_CLASSA_MAX       128
+
+#define IN_CLASSB(a)        ((((u32_t)(a)) & 0xc0000000) == 0x80000000)
+#define IN_CLASSB_NET       0xffff0000
+#define IN_CLASSB_NSHIFT    16
+#define IN_CLASSB_HOST      (0xffffffff & ~IN_CLASSB_NET)
+#define IN_CLASSB_MAX       65536
+
+#define IN_CLASSC(a)        ((((u32_t)(a)) & 0xe0000000) == 0xc0000000)
+#define IN_CLASSC_NET       0xffffff00
+#define IN_CLASSC_NSHIFT    8
+#define IN_CLASSC_HOST      (0xffffffff & ~IN_CLASSC_NET)
+
+#define IN_CLASSD(a)        (((u32_t)(a) & 0xf0000000) == 0xe0000000)
+#define IN_CLASSD_NET       0xf0000000          /* These ones aren't really */
+#define IN_CLASSD_NSHIFT    28                  /*   net and host fields, but */
+#define IN_CLASSD_HOST      0x0fffffff          /*   routing needn't know. */
+#define IN_MULTICAST(a)     IN_CLASSD(a)
+
+#define IN_EXPERIMENTAL(a)  (((u32_t)(a) & 0xf0000000) == 0xf0000000)
+#define IN_BADCLASS(a)      (((u32_t)(a) & 0xf0000000) == 0xf0000000)
+
+#define IN_LOOPBACKNET      127                 /* official! */
+
+#define IP4_ADDR(ipaddr, a,b,c,d) \
+        (ipaddr)->addr = htonl(((u32_t)((a) & 0xff) << 24) | \
+                               ((u32_t)((b) & 0xff) << 16) | \
+                               ((u32_t)((c) & 0xff) << 8) | \
+                                (u32_t)((d) & 0xff))
+
+#define ip_addr_set(dest, src) (dest)->addr = \
+                               ((src) == NULL? 0:\
+                               (src)->addr)
+/**
+ * Determine if two address are on the same network.
+ *
+ * @arg addr1 IP address 1
+ * @arg addr2 IP address 2
+ * @arg mask network identifier mask
+ * @return !0 if the network identifiers of both address match
+ */
+#define ip_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \
+                                              (mask)->addr) == \
+                                             ((addr2)->addr & \
+                                              (mask)->addr))
+#define ip_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr)
+
+#define ip_addr_isany(addr1) ((addr1) == NULL || (addr1)->addr == 0)
+
+u8_t ip_addr_isbroadcast(struct ip_addr *, struct netif *);
+
+#define ip_addr_ismulticast(addr1) (((addr1)->addr & ntohl(0xf0000000)) == ntohl(0xe0000000))
+
+#define ip_addr_debug_print(debug, ipaddr) \
+        LWIP_DEBUGF(debug, ("%"U16_F".%"U16_F".%"U16_F".%"U16_F, \
+                ipaddr ? (u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff : 0, \
+                ipaddr ? (u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff : 0, \
+                ipaddr ? (u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff : 0, \
+                ipaddr ? (u16_t)ntohl((ipaddr)->addr) & 0xff : 0))
+
+/* These are cast to u16_t, with the intent that they are often arguments
+ * to printf using the U16_F format from cc.h. */
+#define ip4_addr1(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff)
+#define ip4_addr2(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff)
+#define ip4_addr3(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff)
+#define ip4_addr4(ipaddr) ((u16_t)(ntohl((ipaddr)->addr)) & 0xff)
+
+#endif /* __LWIP_IP_ADDR_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/ipv4/lwip/ip_frag.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/ipv4/lwip/ip_frag.h
new file mode 100644
index 0000000..30be1a8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/ipv4/lwip/ip_frag.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Jani Monoses 
+ *
+ */
+
+#ifndef __LWIP_IP_FRAG_H__
+#define __LWIP_IP_FRAG_H__
+
+#include "lwip/opt.h"
+#include "lwip/err.h"
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/ip_addr.h"
+
+void ip_frag_init(void);
+void ip_reass_tmr(void);
+struct pbuf * ip_reass(struct pbuf *p);
+err_t ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest);
+
+#endif /* __LWIP_IP_FRAG_H__ */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/api.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/api.h
new file mode 100644
index 0000000..1059eca
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/api.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_API_H__
+#define __LWIP_API_H__
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+
+#include "lwip/ip.h"
+
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/err.h"
+
+#define NETCONN_NOCOPY 0x00
+#define NETCONN_COPY   0x01
+
+enum netconn_type {
+  NETCONN_TCP,
+  NETCONN_UDP,
+  NETCONN_UDPLITE,
+  NETCONN_UDPNOCHKSUM,
+  NETCONN_RAW
+};
+
+enum netconn_state {
+  NETCONN_NONE,
+  NETCONN_WRITE,
+  NETCONN_ACCEPT,
+  NETCONN_RECV,
+  NETCONN_CONNECT,
+  NETCONN_CLOSE
+};
+
+enum netconn_evt {
+  NETCONN_EVT_RCVPLUS,
+  NETCONN_EVT_RCVMINUS,
+  NETCONN_EVT_SENDPLUS,
+  NETCONN_EVT_SENDMINUS
+};
+
+struct netbuf {
+  struct pbuf *p, *ptr;
+  struct ip_addr *fromaddr;
+  u16_t fromport;
+  err_t err;
+};
+
+struct netconn {
+  enum netconn_type type;
+  enum netconn_state state;
+  union {
+    struct tcp_pcb *tcp;
+    struct udp_pcb *udp;
+    struct raw_pcb *raw;
+  } pcb;
+  err_t err;
+  sys_mbox_t mbox;
+  sys_mbox_t recvmbox;
+  sys_mbox_t acceptmbox;
+  sys_sem_t sem;
+  int socket;
+  u16_t recv_avail;
+  void (* callback)(struct netconn *, enum netconn_evt, u16_t len);
+};
+
+/* Network buffer functions: */
+struct netbuf *   netbuf_new      (void);
+void              netbuf_delete   (struct netbuf *buf);
+void *            netbuf_alloc    (struct netbuf *buf, u16_t size);
+void              netbuf_free     (struct netbuf *buf);
+void              netbuf_ref      (struct netbuf *buf,
+           void *dataptr, u16_t size);
+void              netbuf_chain    (struct netbuf *head,
+           struct netbuf *tail);
+
+u16_t             netbuf_len      (struct netbuf *buf);
+err_t             netbuf_data     (struct netbuf *buf,
+           void **dataptr, u16_t *len);
+s8_t              netbuf_next     (struct netbuf *buf);
+void              netbuf_first    (struct netbuf *buf);
+
+void              netbuf_copy     (struct netbuf *buf,
+           void *dataptr, u16_t len);
+void              netbuf_copy_partial(struct netbuf *buf, void *dataptr, 
+              u16_t len, u16_t offset);
+struct ip_addr *  netbuf_fromaddr (struct netbuf *buf);
+u16_t             netbuf_fromport (struct netbuf *buf);
+
+/* Network connection functions: */
+struct netconn *  netconn_new     (enum netconn_type type);
+struct
+netconn *netconn_new_with_callback(enum netconn_type t,
+                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len));
+struct
+netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u16_t proto,
+                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len));
+err_t             netconn_delete  (struct netconn *conn);
+enum netconn_type netconn_type    (struct netconn *conn);
+err_t             netconn_peer    (struct netconn *conn,
+           struct ip_addr *addr,
+           u16_t *port);
+err_t             netconn_addr    (struct netconn *conn,
+           struct ip_addr **addr,
+           u16_t *port);
+err_t             netconn_bind    (struct netconn *conn,
+           struct ip_addr *addr,
+           u16_t port);
+err_t             netconn_connect (struct netconn *conn,
+           struct ip_addr *addr,
+           u16_t port);
+err_t             netconn_disconnect (struct netconn *conn);
+err_t             netconn_listen  (struct netconn *conn);
+struct netconn *  netconn_accept  (struct netconn *conn);
+struct netbuf *   netconn_recv    (struct netconn *conn);
+err_t             netconn_send    (struct netconn *conn,
+           struct netbuf *buf);
+err_t             netconn_write   (struct netconn *conn,
+           void *dataptr, u16_t size,
+           u8_t copy);
+err_t             netconn_close   (struct netconn *conn);
+
+err_t             netconn_err     (struct netconn *conn);
+
+#endif /* __LWIP_API_H__ */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/api_msg.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/api_msg.h
new file mode 100644
index 0000000..87f3db5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/api_msg.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_API_MSG_H__
+#define __LWIP_API_MSG_H__
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+
+#include "lwip/ip.h"
+
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/api.h"
+
+enum api_msg_type {
+  API_MSG_NEWCONN,
+  API_MSG_DELCONN,
+  
+  API_MSG_BIND,
+  API_MSG_CONNECT,
+  API_MSG_DISCONNECT,
+
+  API_MSG_LISTEN,
+  API_MSG_ACCEPT,
+
+  API_MSG_SEND,
+  API_MSG_RECV,
+  API_MSG_WRITE,
+
+  API_MSG_CLOSE,
+  
+  API_MSG_MAX
+};
+
+struct api_msg_msg {
+  struct netconn *conn;
+  enum netconn_type conntype;
+  union {
+    struct pbuf *p;   
+    struct  {
+      struct ip_addr *ipaddr;
+      u16_t port;
+    } bc;
+    struct {
+      void *dataptr;
+      u16_t len;
+      u8_t copy;
+    } w;    
+    sys_mbox_t mbox;
+    u16_t len;
+  } msg;
+};
+
+struct api_msg {
+  enum api_msg_type type;
+  struct api_msg_msg msg;
+};
+
+void api_msg_input(struct api_msg *msg);
+void api_msg_post(struct api_msg *msg);
+
+#endif /* __LWIP_API_MSG_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/arch.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/arch.h
new file mode 100644
index 0000000..b43dd64
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/arch.h
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ARCH_H__
+#define __LWIP_ARCH_H__
+
+#ifndef LITTLE_ENDIAN
+#define LITTLE_ENDIAN 1234
+#endif
+
+#ifndef BIG_ENDIAN
+#define BIG_ENDIAN 4321
+#endif
+
+#include "arch/cc.h"
+
+#ifndef PACK_STRUCT_BEGIN
+#define PACK_STRUCT_BEGIN
+#endif /* PACK_STRUCT_BEGIN */
+
+#ifndef PACK_STRUCT_END
+#define PACK_STRUCT_END
+#endif /* PACK_STRUCT_END */
+
+#ifndef PACK_STRUCT_FIELD
+#define PACK_STRUCT_FIELD(x) x
+#endif /* PACK_STRUCT_FIELD */
+
+#ifndef PACK_STRUCT_STRUCT
+#define PACK_STRUCT_STRUCT
+#endif /* PACK_STRUCT_STRUCT */
+
+#ifdef LWIP_PROVIDE_ERRNO
+
+#define  EPERM     1  /* Operation not permitted */
+#define  ENOENT     2  /* No such file or directory */
+#define  ESRCH     3  /* No such process */
+#define  EINTR     4  /* Interrupted system call */
+#define  EIO     5  /* I/O error */
+#define  ENXIO     6  /* No such device or address */
+#define  E2BIG     7  /* Arg list too long */
+#define  ENOEXEC     8  /* Exec format error */
+#define  EBADF     9  /* Bad file number */
+#define  ECHILD    10  /* No child processes */
+#define  EAGAIN    11  /* Try again */
+#define  ENOMEM    12  /* Out of memory */
+#define  EACCES    13  /* Permission denied */
+#define  EFAULT    14  /* Bad address */
+#define  ENOTBLK    15  /* Block device required */
+#define  EBUSY    16  /* Device or resource busy */
+#define  EEXIST    17  /* File exists */
+#define  EXDEV    18  /* Cross-device link */
+#define  ENODEV    19  /* No such device */
+#define  ENOTDIR    20  /* Not a directory */
+#define  EISDIR    21  /* Is a directory */
+#define  EINVAL    22  /* Invalid argument */
+#define  ENFILE    23  /* File table overflow */
+#define  EMFILE    24  /* Too many open files */
+#define  ENOTTY    25  /* Not a typewriter */
+#define  ETXTBSY    26  /* Text file busy */
+#define  EFBIG    27  /* File too large */
+#define  ENOSPC    28  /* No space left on device */
+#define  ESPIPE    29  /* Illegal seek */
+#define  EROFS    30  /* Read-only file system */
+#define  EMLINK    31  /* Too many links */
+#define  EPIPE    32  /* Broken pipe */
+#define  EDOM    33  /* Math argument out of domain of func */
+#define  ERANGE    34  /* Math result not representable */
+#define  EDEADLK    35  /* Resource deadlock would occur */
+#define  ENAMETOOLONG  36  /* File name too long */
+#define  ENOLCK    37  /* No record locks available */
+#define  ENOSYS    38  /* Function not implemented */
+#define  ENOTEMPTY  39  /* Directory not empty */
+#define  ELOOP    40  /* Too many symbolic links encountered */
+#define  EWOULDBLOCK  EAGAIN  /* Operation would block */
+#define  ENOMSG    42  /* No message of desired type */
+#define  EIDRM    43  /* Identifier removed */
+#define  ECHRNG    44  /* Channel number out of range */
+#define  EL2NSYNC  45  /* Level 2 not synchronized */
+#define  EL3HLT    46  /* Level 3 halted */
+#define  EL3RST    47  /* Level 3 reset */
+#define  ELNRNG    48  /* Link number out of range */
+#define  EUNATCH    49  /* Protocol driver not attached */
+#define  ENOCSI    50  /* No CSI structure available */
+#define  EL2HLT    51  /* Level 2 halted */
+#define  EBADE    52  /* Invalid exchange */
+#define  EBADR    53  /* Invalid request descriptor */
+#define  EXFULL    54  /* Exchange full */
+#define  ENOANO    55  /* No anode */
+#define  EBADRQC    56  /* Invalid request code */
+#define  EBADSLT    57  /* Invalid slot */
+
+#define  EDEADLOCK  EDEADLK
+
+#define  EBFONT    59  /* Bad font file format */
+#define  ENOSTR    60  /* Device not a stream */
+#define  ENODATA    61  /* No data available */
+#define  ETIME    62  /* Timer expired */
+#define  ENOSR    63  /* Out of streams resources */
+#define  ENONET    64  /* Machine is not on the network */
+#define  ENOPKG    65  /* Package not installed */
+#define  EREMOTE    66  /* Object is remote */
+#define  ENOLINK    67  /* Link has been severed */
+#define  EADV    68  /* Advertise error */
+#define  ESRMNT    69  /* Srmount error */
+#define  ECOMM    70  /* Communication error on send */
+#define  EPROTO    71  /* Protocol error */
+#define  EMULTIHOP  72  /* Multihop attempted */
+#define  EDOTDOT    73  /* RFS specific error */
+#define  EBADMSG    74  /* Not a data message */
+#define  EOVERFLOW  75  /* Value too large for defined data type */
+#define  ENOTUNIQ  76  /* Name not unique on network */
+#define  EBADFD    77  /* File descriptor in bad state */
+#define  EREMCHG    78  /* Remote address changed */
+#define  ELIBACC    79  /* Can not access a needed shared library */
+#define  ELIBBAD    80  /* Accessing a corrupted shared library */
+#define  ELIBSCN    81  /* .lib section in a.out corrupted */
+#define  ELIBMAX    82  /* Attempting to link in too many shared libraries */
+#define  ELIBEXEC  83  /* Cannot exec a shared library directly */
+#define  EILSEQ    84  /* Illegal byte sequence */
+#define  ERESTART  85  /* Interrupted system call should be restarted */
+#define  ESTRPIPE  86  /* Streams pipe error */
+#define  EUSERS    87  /* Too many users */
+#define  ENOTSOCK  88  /* Socket operation on non-socket */
+#define  EDESTADDRREQ  89  /* Destination address required */
+#define  EMSGSIZE  90  /* Message too long */
+#define  EPROTOTYPE  91  /* Protocol wrong type for socket */
+#define  ENOPROTOOPT  92  /* Protocol not available */
+#define  EPROTONOSUPPORT  93  /* Protocol not supported */
+#define  ESOCKTNOSUPPORT  94  /* Socket type not supported */
+#define  EOPNOTSUPP  95  /* Operation not supported on transport endpoint */
+#define  EPFNOSUPPORT  96  /* Protocol family not supported */
+#define  EAFNOSUPPORT  97  /* Address family not supported by protocol */
+#define  EADDRINUSE  98  /* Address already in use */
+#define  EADDRNOTAVAIL  99  /* Cannot assign requested address */
+#define  ENETDOWN  100  /* Network is down */
+#define  ENETUNREACH  101  /* Network is unreachable */
+#define  ENETRESET  102  /* Network dropped connection because of reset */
+#define  ECONNABORTED  103  /* Software caused connection abort */
+#define  ECONNRESET  104  /* Connection reset by peer */
+#define  ENOBUFS    105  /* No buffer space available */
+#define  EISCONN    106  /* Transport endpoint is already connected */
+#define  ENOTCONN  107  /* Transport endpoint is not connected */
+#define  ESHUTDOWN  108  /* Cannot send after transport endpoint shutdown */
+#define  ETOOMANYREFS  109  /* Too many references: cannot splice */
+#define  ETIMEDOUT  110  /* Connection timed out */
+#define  ECONNREFUSED  111  /* Connection refused */
+#define  EHOSTDOWN  112  /* Host is down */
+#define  EHOSTUNREACH  113  /* No route to host */
+#define  EALREADY  114  /* Operation already in progress */
+#define  EINPROGRESS  115  /* Operation now in progress */
+#define  ESTALE    116  /* Stale NFS file handle */
+#define  EUCLEAN    117  /* Structure needs cleaning */
+#define  ENOTNAM    118  /* Not a XENIX named type file */
+#define  ENAVAIL    119  /* No XENIX semaphores available */
+#define  EISNAM    120  /* Is a named type file */
+#define  EREMOTEIO  121  /* Remote I/O error */
+#define  EDQUOT    122  /* Quota exceeded */
+
+#define  ENOMEDIUM  123  /* No medium found */
+#define  EMEDIUMTYPE  124  /* Wrong medium type */
+
+
+#define ENSROK    0 /* DNS server returned answer with no data */
+#define ENSRNODATA  160 /* DNS server returned answer with no data */
+#define ENSRFORMERR 161 /* DNS server claims query was misformatted */
+#define ENSRSERVFAIL 162  /* DNS server returned general failure */
+#define ENSRNOTFOUND 163  /* Domain name not found */
+#define ENSRNOTIMP  164 /* DNS server does not implement requested operation */
+#define ENSRREFUSED 165 /* DNS server refused query */
+#define ENSRBADQUERY 166  /* Misformatted DNS query */
+#define ENSRBADNAME 167 /* Misformatted domain name */
+#define ENSRBADFAMILY 168 /* Unsupported address family */
+#define ENSRBADRESP 169 /* Misformatted DNS reply */
+#define ENSRCONNREFUSED 170 /* Could not contact DNS servers */
+#define ENSRTIMEOUT 171 /* Timeout while contacting DNS servers */
+#define ENSROF    172 /* End of file */
+#define ENSRFILE  173 /* Error reading file */
+#define ENSRNOMEM 174 /* Out of memory */
+#define ENSRDESTRUCTION 175 /* Application terminated lookup */
+#define ENSRQUERYDOMAINTOOLONG  176 /* Domain name is too long */
+#define ENSRCNAMELOOP 177 /* Domain name is too long */
+
+#ifndef errno
+extern int errno;
+#endif
+
+#endif /* LWIP_PROVIDE_ERRNO */
+
+#endif /* __LWIP_ARCH_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/debug.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/debug.h
new file mode 100644
index 0000000..3649cbd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/debug.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_DEBUG_H__
+#define __LWIP_DEBUG_H__
+
+#include "arch/cc.h"
+
+/** lower two bits indicate debug level
+ * - 0 off
+ * - 1 warning
+ * - 2 serious
+ * - 3 severe
+ */
+
+#define DBG_LEVEL_OFF     0
+#define DBG_LEVEL_WARNING 1  /* bad checksums, dropped packets, ... */
+#define DBG_LEVEL_SERIOUS 2  /* memory allocation failures, ... */
+#define DBG_LEVEL_SEVERE  3  /* */ 
+#define DBG_MASK_LEVEL    3
+
+/** flag for LWIP_DEBUGF to enable that debug message */
+#define DBG_ON  0x80U
+/** flag for LWIP_DEBUGF to disable that debug message */
+#define DBG_OFF 0x00U
+
+/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */
+#define DBG_TRACE   0x40U
+/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */
+#define DBG_STATE   0x20U
+/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */
+#define DBG_FRESH   0x10U
+/** flag for LWIP_DEBUGF to halt after printing this debug message */
+#define DBG_HALT    0x08U
+
+#ifndef LWIP_NOASSERT
+#  define LWIP_ASSERT(x,y) do { if(!(y)) LWIP_PLATFORM_ASSERT(x); } while(0)
+#else
+#  define LWIP_ASSERT(x,y) 
+#endif
+
+#ifdef LWIP_DEBUG
+/** print debug message only if debug message type is enabled...
+ *  AND is of correct type AND is at least DBG_LEVEL
+ */
+#  define LWIP_DEBUGF(debug,x) do { if (((debug) & DBG_ON) && ((debug) & DBG_TYPES_ON) && ((s16_t)((debug) & DBG_MASK_LEVEL) >= DBG_MIN_LEVEL)) { LWIP_PLATFORM_DIAG(x); if ((debug) & DBG_HALT) while(1); } } while(0)
+#  define LWIP_ERROR(x)   do { LWIP_PLATFORM_DIAG(x); } while(0)  
+#else /* LWIP_DEBUG */
+#  define LWIP_DEBUGF(debug,x) 
+#  define LWIP_ERROR(x)  
+#endif /* LWIP_DEBUG */
+
+#endif /* __LWIP_DEBUG_H__ */
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/def.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/def.h
new file mode 100644
index 0000000..f26bdd0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/def.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_DEF_H__
+#define __LWIP_DEF_H__
+
+/* this might define NULL already */
+#include "arch/cc.h"
+
+#define LWIP_MAX(x , y)  (x) > (y) ? (x) : (y)
+#define LWIP_MIN(x , y)  (x) < (y) ? (x) : (y)
+
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+
+
+#endif /* __LWIP_DEF_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/dhcp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/dhcp.h
new file mode 100644
index 0000000..df51bdc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/dhcp.h
@@ -0,0 +1,223 @@
+/** @file
+ */
+
+#ifndef __LWIP_DHCP_H__
+#define __LWIP_DHCP_H__
+
+#include "lwip/opt.h"
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+
+/** period (in seconds) of the application calling dhcp_coarse_tmr() */
+#define DHCP_COARSE_TIMER_SECS 60 
+/** period (in milliseconds) of the application calling dhcp_fine_tmr() */
+#define DHCP_FINE_TIMER_MSECS 500 
+
+struct dhcp
+{
+  /** current DHCP state machine state */
+  u8_t state;
+  /** retries of current request */
+  u8_t tries;
+  /** transaction identifier of last sent request */ 
+  u32_t xid;
+  /** our connection to the DHCP server */ 
+  struct udp_pcb *pcb;
+  /** (first) pbuf of incoming msg */
+  struct pbuf *p;
+  /** incoming msg */
+  struct dhcp_msg *msg_in;
+  /** incoming msg options */
+  struct dhcp_msg *options_in; 
+  /** ingoing msg options length */
+  u16_t options_in_len;
+
+  struct pbuf *p_out; /* pbuf of outcoming msg */
+  struct dhcp_msg *msg_out; /* outgoing msg */
+  u16_t options_out_len; /* outgoing msg options length */
+  u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */
+  u16_t t1_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */
+  u16_t t2_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */
+  struct ip_addr server_ip_addr; /* dhcp server address that offered this lease */
+  struct ip_addr offered_ip_addr;
+  struct ip_addr offered_sn_mask;
+  struct ip_addr offered_gw_addr;
+  struct ip_addr offered_bc_addr;
+#define DHCP_MAX_DNS 2
+  u32_t dns_count; /* actual number of DNS servers obtained */
+  struct ip_addr offered_dns_addr[DHCP_MAX_DNS]; /* DNS server addresses */
+ 
+  u32_t offered_t0_lease; /* lease period (in seconds) */
+  u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */
+  u32_t offered_t2_rebind; /* recommended rebind time (usually 66% of lease period)  */
+/** Patch #1308
+ *  TODO: See dhcp.c "TODO"s
+ */
+#if 0
+  struct ip_addr offered_si_addr;
+  u8_t *boot_file_name;
+#endif
+};
+
+/* MUST be compiled with "pack structs" or equivalent! */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** minimum set of fields of any DHCP message */
+struct dhcp_msg
+{
+  PACK_STRUCT_FIELD(u8_t op);
+  PACK_STRUCT_FIELD(u8_t htype);
+  PACK_STRUCT_FIELD(u8_t hlen);
+  PACK_STRUCT_FIELD(u8_t hops);
+  PACK_STRUCT_FIELD(u32_t xid);
+  PACK_STRUCT_FIELD(u16_t secs);
+  PACK_STRUCT_FIELD(u16_t flags);
+  PACK_STRUCT_FIELD(struct ip_addr ciaddr);
+  PACK_STRUCT_FIELD(struct ip_addr yiaddr);
+  PACK_STRUCT_FIELD(struct ip_addr siaddr);
+  PACK_STRUCT_FIELD(struct ip_addr giaddr);
+#define DHCP_CHADDR_LEN 16U
+  PACK_STRUCT_FIELD(u8_t chaddr[DHCP_CHADDR_LEN]);
+#define DHCP_SNAME_LEN 64U
+  PACK_STRUCT_FIELD(u8_t sname[DHCP_SNAME_LEN]);
+#define DHCP_FILE_LEN 128U
+  PACK_STRUCT_FIELD(u8_t file[DHCP_FILE_LEN]);
+  PACK_STRUCT_FIELD(u32_t cookie);
+#define DHCP_MIN_OPTIONS_LEN 68U
+/** make sure user does not configure this too small */
+#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN))
+#  undef DHCP_OPTIONS_LEN
+#endif
+/** allow this to be configured in lwipopts.h, but not too small */
+#if (!defined(DHCP_OPTIONS_LEN))
+/** set this to be sufficient for your options in outgoing DHCP msgs */
+#  define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN
+#endif
+  PACK_STRUCT_FIELD(u8_t options[DHCP_OPTIONS_LEN]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** start DHCP configuration */
+err_t dhcp_start(struct netif *netif);
+/** enforce early lease renewal (not needed normally)*/
+err_t dhcp_renew(struct netif *netif);
+/** release the DHCP lease, usually called before dhcp_stop()*/
+err_t dhcp_release(struct netif *netif);
+/** stop DHCP configuration */
+void dhcp_stop(struct netif *netif);
+/** inform server of our manual IP address */
+void dhcp_inform(struct netif *netif);
+
+/** if enabled, check whether the offered IP address is not in use, using ARP */
+#if DHCP_DOES_ARP_CHECK
+void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr);
+#endif
+
+/** to be called every minute */
+void dhcp_coarse_tmr(void);
+/** to be called every half second */
+void dhcp_fine_tmr(void);
+ 
+/** DHCP message item offsets and length */
+#define DHCP_MSG_OFS (UDP_DATA_OFS)  
+  #define DHCP_OP_OFS (DHCP_MSG_OFS + 0)
+  #define DHCP_HTYPE_OFS (DHCP_MSG_OFS + 1)
+  #define DHCP_HLEN_OFS (DHCP_MSG_OFS + 2)
+  #define DHCP_HOPS_OFS (DHCP_MSG_OFS + 3)
+  #define DHCP_XID_OFS (DHCP_MSG_OFS + 4)
+  #define DHCP_SECS_OFS (DHCP_MSG_OFS + 8)
+  #define DHCP_FLAGS_OFS (DHCP_MSG_OFS + 10)
+  #define DHCP_CIADDR_OFS (DHCP_MSG_OFS + 12)
+  #define DHCP_YIADDR_OFS (DHCP_MSG_OFS + 16)
+  #define DHCP_SIADDR_OFS (DHCP_MSG_OFS + 20)
+  #define DHCP_GIADDR_OFS (DHCP_MSG_OFS + 24)
+  #define DHCP_CHADDR_OFS (DHCP_MSG_OFS + 28)
+  #define DHCP_SNAME_OFS (DHCP_MSG_OFS + 44)
+  #define DHCP_FILE_OFS (DHCP_MSG_OFS + 108)
+#define DHCP_MSG_LEN 236
+
+#define DHCP_COOKIE_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN)
+#define DHCP_OPTIONS_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN + 4)
+
+#define DHCP_CLIENT_PORT 68  
+#define DHCP_SERVER_PORT 67
+
+/** DHCP client states */
+#define DHCP_REQUESTING 1
+#define DHCP_INIT 2
+#define DHCP_REBOOTING 3
+#define DHCP_REBINDING 4
+#define DHCP_RENEWING 5
+#define DHCP_SELECTING 6
+#define DHCP_INFORMING 7
+#define DHCP_CHECKING 8
+#define DHCP_PERMANENT 9
+#define DHCP_BOUND 10
+/** not yet implemented #define DHCP_RELEASING 11 */
+#define DHCP_BACKING_OFF 12
+#define DHCP_OFF 13
+ 
+#define DHCP_BOOTREQUEST 1
+#define DHCP_BOOTREPLY 2
+
+#define DHCP_DISCOVER 1
+#define DHCP_OFFER 2
+#define DHCP_REQUEST 3
+#define DHCP_DECLINE 4
+#define DHCP_ACK 5
+#define DHCP_NAK 6
+#define DHCP_RELEASE 7
+#define DHCP_INFORM 8
+
+#define DHCP_HTYPE_ETH 1
+
+#define DHCP_HLEN_ETH 6
+
+#define DHCP_BROADCAST_FLAG 15
+#define DHCP_BROADCAST_MASK (1 << DHCP_FLAG_BROADCAST)
+
+/** BootP options */
+#define DHCP_OPTION_PAD 0
+#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */
+#define DHCP_OPTION_ROUTER 3
+#define DHCP_OPTION_DNS_SERVER 6 
+#define DHCP_OPTION_HOSTNAME 12
+#define DHCP_OPTION_IP_TTL 23
+#define DHCP_OPTION_MTU 26
+#define DHCP_OPTION_BROADCAST 28
+#define DHCP_OPTION_TCP_TTL 37
+#define DHCP_OPTION_END 255
+
+/** DHCP options */
+#define DHCP_OPTION_REQUESTED_IP 50 /* RFC 2132 9.1, requested IP address */
+#define DHCP_OPTION_LEASE_TIME 51 /* RFC 2132 9.2, time in seconds, in 4 bytes */
+#define DHCP_OPTION_OVERLOAD 52 /* RFC2132 9.3, use file and/or sname field for options */
+
+#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */
+#define DHCP_OPTION_MESSAGE_TYPE_LEN 1
+
+
+#define DHCP_OPTION_SERVER_ID 54 /* RFC 2132 9.7, server IP address */
+#define DHCP_OPTION_PARAMETER_REQUEST_LIST 55 /* RFC 2132 9.8, requested option types */
+
+#define DHCP_OPTION_MAX_MSG_SIZE 57 /* RFC 2132 9.10, message size accepted >= 576 */
+#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2
+
+#define DHCP_OPTION_T1 58 /* T1 renewal time */
+#define DHCP_OPTION_T2 59 /* T2 rebinding time */
+#define DHCP_OPTION_CLIENT_ID 61
+#define DHCP_OPTION_TFTP_SERVERNAME 66
+#define DHCP_OPTION_BOOTFILE 67
+
+/** possible combinations of overloading the file and sname fields with options */
+#define DHCP_OVERLOAD_NONE 0
+#define DHCP_OVERLOAD_FILE 1
+#define DHCP_OVERLOAD_SNAME  2
+#define DHCP_OVERLOAD_SNAME_FILE 3
+
+#endif /*__LWIP_DHCP_H__*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/err.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/err.h
new file mode 100644
index 0000000..fc90f2e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/err.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ERR_H__
+#define __LWIP_ERR_H__
+
+#include "lwip/opt.h"
+
+#include "arch/cc.h"
+
+typedef s8_t err_t;
+
+/* Definitions for error constants. */
+
+#define ERR_OK    0      /* No error, everything OK. */
+#define ERR_MEM  -1      /* Out of memory error.     */
+#define ERR_BUF  -2      /* Buffer error.            */
+
+
+#define ERR_ABRT -3      /* Connection aborted.      */
+#define ERR_RST  -4      /* Connection reset.        */
+#define ERR_CLSD -5      /* Connection closed.       */
+#define ERR_CONN -6      /* Not connected.           */
+
+#define ERR_VAL  -7      /* Illegal value.           */
+
+#define ERR_ARG  -8      /* Illegal argument.        */
+
+#define ERR_RTE  -9      /* Routing problem.         */
+
+#define ERR_USE  -10     /* Address in use.          */
+
+#define ERR_IF   -11     /* Low-level netif error    */
+#define ERR_ISCONN -12   /* Already connected.       */
+
+
+#ifdef LWIP_DEBUG
+extern char *lwip_strerr(err_t err);
+#else
+#define lwip_strerr(x) ""
+#endif /* LWIP_DEBUG */
+#endif /* __LWIP_ERR_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/mem.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/mem.h
new file mode 100644
index 0000000..3d57389
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/mem.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_MEM_H__
+#define __LWIP_MEM_H__
+
+#include "lwip/opt.h"
+#include "lwip/arch.h"
+
+#if MEM_SIZE > 64000l
+typedef u32_t mem_size_t;
+#define MEM_SIZE_F U32_F
+#else
+typedef u16_t mem_size_t;
+#define MEM_SIZE_F U16_F
+#endif /* MEM_SIZE > 64000 */
+
+#if MEM_LIBC_MALLOC
+/* aliases for C library malloc() */
+#define mem_init()
+#define mem_free(x) free(x)
+#define mem_malloc(x) malloc(x)
+#define mem_realloc(x, size) realloc(x,size)
+#else
+/* lwIP alternative malloc */
+void mem_init(void);
+void *mem_malloc(mem_size_t size);
+void mem_free(void *mem);
+void *mem_realloc(void *mem, mem_size_t size);
+#endif
+
+#ifndef MEM_ALIGN_SIZE
+#define MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1) & ~(MEM_ALIGNMENT-1))
+#endif
+
+#ifndef MEM_ALIGN
+#define MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1)))
+#endif
+
+#endif /* __LWIP_MEM_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/memp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/memp.h
new file mode 100644
index 0000000..6da033f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/memp.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef __LWIP_MEMP_H__
+#define __LWIP_MEMP_H__
+
+#include "lwip/opt.h"
+
+typedef enum {
+  MEMP_PBUF,
+  MEMP_RAW_PCB,
+  MEMP_UDP_PCB,
+  MEMP_TCP_PCB,
+  MEMP_TCP_PCB_LISTEN,
+  MEMP_TCP_SEG,
+
+  MEMP_NETBUF,
+  MEMP_NETCONN,
+  MEMP_API_MSG,
+  MEMP_TCPIP_MSG,
+
+  MEMP_SYS_TIMEOUT,
+  
+  MEMP_MAX
+} memp_t;
+
+void memp_init(void);
+
+void *memp_malloc(memp_t type);
+void *memp_realloc(memp_t fromtype, memp_t totype, void *mem);
+void memp_free(memp_t type, void *mem);
+
+#endif /* __LWIP_MEMP_H__  */
+    
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/netif.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/netif.h
new file mode 100644
index 0000000..efc59fd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/netif.h
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_NETIF_H__
+#define __LWIP_NETIF_H__
+
+#include "lwip/opt.h"
+
+#include "lwip/err.h"
+
+#include "lwip/ip_addr.h"
+
+#include "lwip/inet.h"
+#include "lwip/pbuf.h"
+#if LWIP_DHCP
+#  include "lwip/dhcp.h"
+#endif
+
+/** must be the maximum of all used hardware address lengths
+    across all types of interfaces in use */
+#define NETIF_MAX_HWADDR_LEN 6U
+
+/** TODO: define the use (where, when, whom) of netif flags */
+
+/** whether the network interface is 'up'. this is
+ * a software flag used to control whether this network
+ * interface is enabled and processes traffic.
+ */
+#define NETIF_FLAG_UP 0x1U
+/** if set, the netif has broadcast capability */
+#define NETIF_FLAG_BROADCAST 0x2U
+/** if set, the netif is one end of a point-to-point connection */
+#define NETIF_FLAG_POINTTOPOINT 0x4U
+/** if set, the interface is configured using DHCP */
+#define NETIF_FLAG_DHCP 0x08U
+/** if set, the interface has an active link
+ *  (set by the network interface driver) */
+#define NETIF_FLAG_LINK_UP 0x10U
+
+/** Generic data structure used for all lwIP network interfaces.
+ *  The following fields should be filled in by the initialization
+ *  function for the device driver: hwaddr_len, hwaddr[], mtu, flags */
+
+struct netif {
+  /** pointer to next in linked list */
+  struct netif *next;
+
+  /** IP address configuration in network byte order */
+  struct ip_addr ip_addr;
+  struct ip_addr netmask;
+  struct ip_addr gw;
+
+  /** This function is called by the network device driver
+   *  to pass a packet up the TCP/IP stack. */
+  err_t (* input)(struct pbuf *p, struct netif *inp);
+  /** This function is called by the IP module when it wants
+   *  to send a packet on the interface. This function typically
+   *  first resolves the hardware address, then sends the packet. */
+  err_t (* output)(struct netif *netif, struct pbuf *p,
+       struct ip_addr *ipaddr);
+  /** This function is called by the ARP module when it wants
+   *  to send a packet on the interface. This function outputs
+   *  the pbuf as-is on the link medium. */
+  err_t (* linkoutput)(struct netif *netif, struct pbuf *p);
+  /** This field can be set by the device driver and could point
+   *  to state information for the device. */
+  void *state;
+#if LWIP_DHCP
+  /** the DHCP client state information for this netif */
+  struct dhcp *dhcp;
+#endif
+  /** number of bytes used in hwaddr */
+  u8_t hwaddr_len;
+  /** link level hardware address of this interface */
+  u8_t hwaddr[NETIF_MAX_HWADDR_LEN];
+  /** maximum transfer unit (in bytes) */
+  u16_t mtu;
+  /** flags (see NETIF_FLAG_ above) */
+  u8_t flags;
+  /** descriptive abbreviation */
+  char name[2];
+  /** number of this interface */
+  u8_t num;
+#if LWIP_SNMP
+  /** link type (ifType values per RFC1213) */
+  u8_t link_type;
+  /** (estimate) link speed */
+  u32_t link_speed;
+  /** timestamp at last change made (up/down) */
+  u32_t ts;
+  /** counters */
+  u32_t ifinoctets;
+  u32_t ifinucastpkts;
+  u32_t ifinnucastpkts;
+  u32_t ifindiscards;
+  u32_t ifoutoctets;
+  u32_t ifoutucastpkts;
+  u32_t ifoutnucastpkts;
+  u32_t ifoutdiscards;
+#endif
+};
+
+/** The list of network interfaces. */
+extern struct netif *netif_list;
+/** The default network interface. */
+extern struct netif *netif_default;
+
+/* netif_init() must be called first. */
+void netif_init(void);
+
+struct netif *netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
+      struct ip_addr *gw,
+      void *state,
+      err_t (* init)(struct netif *netif),
+      err_t (* input)(struct pbuf *p, struct netif *netif));
+
+void
+netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask,
+    struct ip_addr *gw);
+void netif_remove(struct netif * netif);
+
+/* Returns a network interface given its name. The name is of the form
+   "et0", where the first two letters are the "name" field in the
+   netif structure, and the digit is in the num field in the same
+   structure. */
+struct netif *netif_find(char *name);
+
+void netif_set_default(struct netif *netif);
+
+void netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr);
+void netif_set_netmask(struct netif *netif, struct ip_addr *netmast);
+void netif_set_gw(struct netif *netif, struct ip_addr *gw);
+void netif_set_up(struct netif *netif);
+void netif_set_down(struct netif *netif);
+u8_t netif_is_up(struct netif *netif);
+
+#endif /* __LWIP_NETIF_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/pbuf.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/pbuf.h
new file mode 100644
index 0000000..0b187e1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/pbuf.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef __LWIP_PBUF_H__
+#define __LWIP_PBUF_H__
+
+#include "arch/cc.h"
+
+
+#define PBUF_TRANSPORT_HLEN 20
+#define PBUF_IP_HLEN        20
+
+typedef enum {
+  PBUF_TRANSPORT,
+  PBUF_IP,
+  PBUF_LINK,
+  PBUF_RAW
+} pbuf_layer;
+
+typedef enum {
+  PBUF_RAM,
+  PBUF_ROM,
+  PBUF_REF,
+  PBUF_POOL
+} pbuf_flag;
+
+/* Definitions for the pbuf flag field. These are NOT the flags that
+ * are passed to pbuf_alloc(). */
+#define PBUF_FLAG_RAM   0x00U    /* Flags that pbuf data is stored in RAM */
+#define PBUF_FLAG_ROM   0x01U    /* Flags that pbuf data is stored in ROM */
+#define PBUF_FLAG_POOL  0x02U    /* Flags that the pbuf comes from the pbuf pool */
+#define PBUF_FLAG_REF   0x04U    /* Flags thet the pbuf payload refers to RAM */
+
+/** indicates this packet was broadcast on the link */
+#define PBUF_FLAG_LINK_BROADCAST 0x80U
+
+struct pbuf {
+  /** next pbuf in singly linked pbuf chain */
+  struct pbuf *next;
+
+  /** pointer to the actual data in the buffer */
+  void *payload;
+  
+  /**
+   * total length of this buffer and all next buffers in chain
+   * belonging to the same packet.
+   *
+   * For non-queue packet chains this is the invariant:
+   * p->tot_len == p->len + (p->next? p->next->tot_len: 0)
+   */
+  u16_t tot_len;
+  
+  /** length of this buffer */
+  u16_t len;  
+
+  /** flags telling the type of pbuf, see PBUF_FLAG_ */
+  u16_t flags;
+  
+  /**
+   * the reference count always equals the number of pointers
+   * that refer to this pbuf. This can be pointers from an application,
+   * the stack itself, or pbuf->next pointers from a chain.
+   */
+  u16_t ref;
+  
+};
+
+void pbuf_init(void);
+
+struct pbuf *pbuf_alloc(pbuf_layer l, u16_t size, pbuf_flag flag);
+void pbuf_realloc(struct pbuf *p, u16_t size); 
+u8_t pbuf_header(struct pbuf *p, s16_t header_size);
+void pbuf_ref(struct pbuf *p);
+void pbuf_ref_chain(struct pbuf *p);
+u8_t pbuf_free(struct pbuf *p);
+u8_t pbuf_clen(struct pbuf *p);  
+void pbuf_cat(struct pbuf *h, struct pbuf *t);
+void pbuf_chain(struct pbuf *h, struct pbuf *t);
+struct pbuf *pbuf_take(struct pbuf *f);
+struct pbuf *pbuf_dechain(struct pbuf *p);
+void pbuf_queue(struct pbuf *p, struct pbuf *n);
+struct pbuf * pbuf_dequeue(struct pbuf *p);
+
+#endif /* __LWIP_PBUF_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/raw.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/raw.h
new file mode 100644
index 0000000..83b32da
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/raw.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_RAW_H__
+#define __LWIP_RAW_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+
+struct raw_pcb {
+/* Common members of all PCB types */
+  IP_PCB;
+
+  struct raw_pcb *next;
+
+  u16_t protocol;
+
+  u8_t (* recv)(void *arg, struct raw_pcb *pcb, struct pbuf *p,
+    struct ip_addr *addr);
+  void *recv_arg;
+};
+
+/* The following functions is the application layer interface to the
+   RAW code. */
+struct raw_pcb * raw_new        (u16_t proto);
+void             raw_remove     (struct raw_pcb *pcb);
+err_t            raw_bind       (struct raw_pcb *pcb, struct ip_addr *ipaddr);
+err_t            raw_connect    (struct raw_pcb *pcb, struct ip_addr *ipaddr);
+
+void             raw_recv       (struct raw_pcb *pcb,
+                                 u8_t (* recv)(void *arg, struct raw_pcb *pcb,
+                                              struct pbuf *p,
+                                              struct ip_addr *addr),
+                                 void *recv_arg);
+err_t            raw_sendto    (struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr);
+err_t            raw_send       (struct raw_pcb *pcb, struct pbuf *p);
+
+/* The following functions are the lower layer interface to RAW. */
+u8_t              raw_input      (struct pbuf *p, struct netif *inp);
+void             raw_init       (void);
+
+
+#endif /* __LWIP_RAW_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/sio.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/sio.h
new file mode 100644
index 0000000..5fc28a4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/sio.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ */
+
+/*
+ * This is the interface to the platform specific serial IO module
+ * It needs to be implemented by those platforms which need SLIP or PPP
+ */
+
+#include "arch/cc.h"
+
+#ifndef __sio_fd_t_defined
+typedef void * sio_fd_t;
+#endif
+
+#ifndef sio_open
+sio_fd_t sio_open(u8_t);
+#endif
+
+#ifndef sio_send
+void sio_send(u8_t, sio_fd_t);
+#endif
+
+#ifndef sio_recv
+u8_t sio_recv(sio_fd_t);
+#endif
+
+#ifndef sio_read
+u32_t sio_read(sio_fd_t, u8_t *, u32_t);
+#endif
+
+#ifndef sio_write
+u32_t sio_write(sio_fd_t, u8_t *, u32_t);
+#endif
+
+#ifndef sio_read_abort
+void sio_read_abort(sio_fd_t);
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/snmp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/snmp.h
new file mode 100644
index 0000000..987ebd9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/snmp.h
@@ -0,0 +1,309 @@
+/*
+ * Copyright (c) 2001, 2002 Leon Woestenberg 
+ * Copyright (c) 2001, 2002 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Leon Woestenberg 
+ *
+ */
+#ifndef __LWIP_SNMP_H__
+#define __LWIP_SNMP_H__
+
+#include "lwip/opt.h"
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+
+/* SNMP support available? */
+#if defined(LWIP_SNMP) && (LWIP_SNMP > 0)
+
+/** fixed maximum length for object identifier type */
+#define LWIP_SNMP_OBJ_ID_LEN 32
+/** internal object identifier representation */
+struct snmp_obj_id
+{
+  u8_t len;
+  s32_t id[LWIP_SNMP_OBJ_ID_LEN];
+};
+
+/* system */
+void snmp_set_sysdesr(u8_t* str, u8_t* strlen);
+void snmp_set_sysobjid(struct snmp_obj_id *oid);
+void snmp_get_sysobjid_ptr(struct snmp_obj_id **oid);
+void snmp_inc_sysuptime(void);
+void snmp_get_sysuptime(u32_t *value);
+void snmp_set_syscontact(u8_t *ocstr, u8_t *ocstrlen);
+void snmp_set_sysname(u8_t *ocstr, u8_t *ocstrlen);
+void snmp_set_syslocation(u8_t *ocstr, u8_t *ocstrlen);
+
+/* network interface */
+void snmp_add_ifinoctets(struct netif *ni, u32_t value); 
+void snmp_inc_ifinucastpkts(struct netif *ni);
+void snmp_inc_ifinnucastpkts(struct netif *ni);
+void snmp_inc_ifindiscards(struct netif *ni);
+void snmp_add_ifoutoctets(struct netif *ni, u32_t value);
+void snmp_inc_ifoutucastpkts(struct netif *ni);
+void snmp_inc_ifoutnucastpkts(struct netif *ni);
+void snmp_inc_ifoutdiscards(struct netif *ni);
+void snmp_inc_iflist(void);
+void snmp_dec_iflist(void);
+
+/* ARP (for atTable and ipNetToMediaTable) */
+void snmp_insert_arpidx_tree(struct netif *ni, struct ip_addr *ip);
+void snmp_delete_arpidx_tree(struct netif *ni, struct ip_addr *ip);
+
+/* IP */
+void snmp_inc_ipinreceives(void);
+void snmp_inc_ipinhdrerrors(void);
+void snmp_inc_ipinaddrerrors(void);
+void snmp_inc_ipforwdatagrams(void);
+void snmp_inc_ipinunknownprotos(void);
+void snmp_inc_ipindiscards(void);
+void snmp_inc_ipindelivers(void);
+void snmp_inc_ipoutrequests(void);
+void snmp_inc_ipoutdiscards(void);
+void snmp_inc_ipoutnoroutes(void);
+void snmp_inc_ipreasmreqds(void);
+void snmp_inc_ipreasmoks(void);
+void snmp_inc_ipreasmfails(void);
+void snmp_inc_ipfragoks(void);
+void snmp_inc_ipfragfails(void);
+void snmp_inc_ipfragcreates(void);
+void snmp_inc_iproutingdiscards(void);
+void snmp_insert_ipaddridx_tree(struct netif *ni);
+void snmp_delete_ipaddridx_tree(struct netif *ni);
+void snmp_insert_iprteidx_tree(u8_t dflt, struct netif *ni);
+void snmp_delete_iprteidx_tree(u8_t dflt, struct netif *ni);
+
+/* ICMP */
+void snmp_inc_icmpinmsgs(void);
+void snmp_inc_icmpinerrors(void);
+void snmp_inc_icmpindestunreachs(void);
+void snmp_inc_icmpintimeexcds(void);
+void snmp_inc_icmpinparmprobs(void);
+void snmp_inc_icmpinsrcquenchs(void);
+void snmp_inc_icmpinredirects(void);
+void snmp_inc_icmpinechos(void);
+void snmp_inc_icmpinechoreps(void);
+void snmp_inc_icmpintimestamps(void);
+void snmp_inc_icmpintimestampreps(void);
+void snmp_inc_icmpinaddrmasks(void);
+void snmp_inc_icmpinaddrmaskreps(void);
+void snmp_inc_icmpoutmsgs(void);
+void snmp_inc_icmpouterrors(void);
+void snmp_inc_icmpoutdestunreachs(void);
+void snmp_inc_icmpouttimeexcds(void);
+void snmp_inc_icmpoutparmprobs(void);
+void snmp_inc_icmpoutsrcquenchs(void);
+void snmp_inc_icmpoutredirects(void); 
+void snmp_inc_icmpoutechos(void);
+void snmp_inc_icmpoutechoreps(void);
+void snmp_inc_icmpouttimestamps(void);
+void snmp_inc_icmpouttimestampreps(void);
+void snmp_inc_icmpoutaddrmasks(void);
+void snmp_inc_icmpoutaddrmaskreps(void);
+
+/* TCP */
+void snmp_inc_tcpactiveopens(void);
+void snmp_inc_tcppassiveopens(void);
+void snmp_inc_tcpattemptfails(void);
+void snmp_inc_tcpestabresets(void);
+void snmp_inc_tcpinsegs(void);
+void snmp_inc_tcpoutsegs(void);
+void snmp_inc_tcpretranssegs(void);
+void snmp_inc_tcpinerrs(void);
+void snmp_inc_tcpoutrsts(void);
+
+/* UDP */
+void snmp_inc_udpindatagrams(void);
+void snmp_inc_udpnoports(void);
+void snmp_inc_udpinerrors(void);
+void snmp_inc_udpoutdatagrams(void);
+void snmp_insert_udpidx_tree(struct udp_pcb *pcb);
+void snmp_delete_udpidx_tree(struct udp_pcb *pcb);
+
+/* SNMP */
+void snmp_inc_snmpinpkts(void);
+void snmp_inc_snmpoutpkts(void);
+void snmp_inc_snmpinbadversions(void);
+void snmp_inc_snmpinbadcommunitynames(void);
+void snmp_inc_snmpinbadcommunityuses(void);
+void snmp_inc_snmpinasnparseerrs(void);
+void snmp_inc_snmpintoobigs(void);
+void snmp_inc_snmpinnosuchnames(void);
+void snmp_inc_snmpinbadvalues(void);
+void snmp_inc_snmpinreadonlys(void);
+void snmp_inc_snmpingenerrs(void);
+void snmp_add_snmpintotalreqvars(u8_t value);
+void snmp_add_snmpintotalsetvars(u8_t value);
+void snmp_inc_snmpingetrequests(void);
+void snmp_inc_snmpingetnexts(void);
+void snmp_inc_snmpinsetrequests(void);
+void snmp_inc_snmpingetresponses(void);
+void snmp_inc_snmpintraps(void);
+void snmp_inc_snmpouttoobigs(void);
+void snmp_inc_snmpoutnosuchnames(void);
+void snmp_inc_snmpoutbadvalues(void);
+void snmp_inc_snmpoutgenerrs(void);
+void snmp_inc_snmpoutgetrequests(void);
+void snmp_inc_snmpoutgetnexts(void);
+void snmp_inc_snmpoutsetrequests(void);
+void snmp_inc_snmpoutgetresponses(void);
+void snmp_inc_snmpouttraps(void);
+void snmp_get_snmpgrpid_ptr(struct snmp_obj_id **oid);
+void snmp_set_snmpenableauthentraps(u8_t *value);
+void snmp_get_snmpenableauthentraps(u8_t *value);
+
+/* LWIP_SNMP support not available */
+/* define everything to be empty */
+#else
+
+/* system */
+#define snmp_set_sysdesr(str, strlen)
+#define snmp_get_sysobjid_ptr(oid)
+#define snmp_inc_sysuptime()
+#define snmp_get_sysuptime(value)
+
+/* network interface */
+#define snmp_add_ifinoctets(ni,value) 
+#define snmp_inc_ifinucastpkts(ni)
+#define snmp_inc_ifinnucastpkts(ni)
+#define snmp_inc_ifindiscards(ni)
+#define snmp_add_ifoutoctets(ni,value)
+#define snmp_inc_ifoutucastpkts(ni)
+#define snmp_inc_ifoutnucastpkts(ni)
+#define snmp_inc_ifoutdiscards(ni)
+#define snmp_inc_iflist()
+#define snmp_dec_iflist()
+
+/* ARP */
+#define snmp_insert_arpidx_tree(ni,ip)
+#define snmp_delete_arpidx_tree(ni,ip)
+
+/* IP */
+#define snmp_inc_ipinreceives()
+#define snmp_inc_ipinhdrerrors()
+#define snmp_inc_ipinaddrerrors()
+#define snmp_inc_ipforwdatagrams()
+#define snmp_inc_ipinunknownprotos()
+#define snmp_inc_ipindiscards()
+#define snmp_inc_ipindelivers()
+#define snmp_inc_ipoutrequests()
+#define snmp_inc_ipoutdiscards()
+#define snmp_inc_ipoutnoroutes()
+#define snmp_inc_ipreasmreqds()
+#define snmp_inc_ipreasmoks()
+#define snmp_inc_ipreasmfails()
+#define snmp_inc_ipfragoks()
+#define snmp_inc_ipfragfails()
+#define snmp_inc_ipfragcreates()
+#define snmp_inc_iproutingdiscards()
+#define snmp_insert_ipaddridx_tree(ni)
+#define snmp_delete_ipaddridx_tree(ni)
+#define snmp_insert_iprteidx_tree(dflt, ni)
+#define snmp_delete_iprteidx_tree(dflt, ni)
+
+/* ICMP */
+#define snmp_inc_icmpinmsgs()
+#define snmp_inc_icmpinerrors() 
+#define snmp_inc_icmpindestunreachs() 
+#define snmp_inc_icmpintimeexcds()
+#define snmp_inc_icmpinparmprobs() 
+#define snmp_inc_icmpinsrcquenchs() 
+#define snmp_inc_icmpinredirects() 
+#define snmp_inc_icmpinechos() 
+#define snmp_inc_icmpinechoreps()
+#define snmp_inc_icmpintimestamps() 
+#define snmp_inc_icmpintimestampreps()
+#define snmp_inc_icmpinaddrmasks()
+#define snmp_inc_icmpinaddrmaskreps()
+#define snmp_inc_icmpoutmsgs()
+#define snmp_inc_icmpouterrors()
+#define snmp_inc_icmpoutdestunreachs() 
+#define snmp_inc_icmpouttimeexcds() 
+#define snmp_inc_icmpoutparmprobs()
+#define snmp_inc_icmpoutsrcquenchs()
+#define snmp_inc_icmpoutredirects() 
+#define snmp_inc_icmpoutechos() 
+#define snmp_inc_icmpoutechoreps()
+#define snmp_inc_icmpouttimestamps()
+#define snmp_inc_icmpouttimestampreps()
+#define snmp_inc_icmpoutaddrmasks()
+#define snmp_inc_icmpoutaddrmaskreps()
+/* TCP */
+#define snmp_inc_tcpactiveopens()
+#define snmp_inc_tcppassiveopens()
+#define snmp_inc_tcpattemptfails()
+#define snmp_inc_tcpestabresets()
+#define snmp_inc_tcpinsegs()
+#define snmp_inc_tcpoutsegs()
+#define snmp_inc_tcpretranssegs()
+#define snmp_inc_tcpinerrs()
+#define snmp_inc_tcpoutrsts()
+
+/* UDP */
+#define snmp_inc_udpindatagrams()
+#define snmp_inc_udpnoports()
+#define snmp_inc_udpinerrors()
+#define snmp_inc_udpoutdatagrams()
+#define snmp_insert_udpidx_tree(pcb)
+#define snmp_delete_udpidx_tree(pcb)
+
+/* SNMP */
+#define snmp_inc_snmpinpkts()
+#define snmp_inc_snmpoutpkts()
+#define snmp_inc_snmpinbadversions()
+#define snmp_inc_snmpinbadcommunitynames()
+#define snmp_inc_snmpinbadcommunityuses()
+#define snmp_inc_snmpinasnparseerrs()
+#define snmp_inc_snmpintoobigs()
+#define snmp_inc_snmpinnosuchnames()
+#define snmp_inc_snmpinbadvalues()
+#define snmp_inc_snmpinreadonlys()
+#define snmp_inc_snmpingenerrs()
+#define snmp_add_snmpintotalreqvars(value)
+#define snmp_add_snmpintotalsetvars(value)
+#define snmp_inc_snmpingetrequests()
+#define snmp_inc_snmpingetnexts()
+#define snmp_inc_snmpinsetrequests()
+#define snmp_inc_snmpingetresponses()
+#define snmp_inc_snmpintraps()
+#define snmp_inc_snmpouttoobigs()
+#define snmp_inc_snmpoutnosuchnames()
+#define snmp_inc_snmpoutbadvalues()
+#define snmp_inc_snmpoutgenerrs()
+#define snmp_inc_snmpoutgetrequests()
+#define snmp_inc_snmpoutgetnexts()
+#define snmp_inc_snmpoutsetrequests()
+#define snmp_inc_snmpoutgetresponses()
+#define snmp_inc_snmpouttraps()
+#define snmp_get_snmpgrpid_ptr(oid)
+#define snmp_set_snmpenableauthentraps(value)
+#define snmp_get_snmpenableauthentraps(value)
+
+#endif
+
+#endif /* __LWIP_SNMP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/snmp_asn1.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/snmp_asn1.h
new file mode 100644
index 0000000..d83d41d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/snmp_asn1.h
@@ -0,0 +1,90 @@
+/**
+ * @file
+ * Abstract Syntax Notation One (ISO 8824, 8825) codec.
+ */
+ 
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#ifndef __LWIP_SNMP_ASN1_H__
+#define __LWIP_SNMP_ASN1_H__
+
+#include "lwip/opt.h"
+#include "arch/cc.h"
+#include "lwip/err.h"
+#include "lwip/pbuf.h"
+#include "lwip/snmp.h"
+
+#define SNMP_ASN1_UNIV   (!0x80 | !0x40)
+#define SNMP_ASN1_APPLIC (!0x80 |  0x40)
+#define SNMP_ASN1_CONTXT ( 0x80 | !0x40)
+
+#define SNMP_ASN1_CONSTR (0x20)
+#define SNMP_ASN1_PRIMIT (!0x20)
+
+/* universal tags */
+#define SNMP_ASN1_INTEG  2
+#define SNMP_ASN1_OC_STR 4
+#define SNMP_ASN1_NUL    5
+#define SNMP_ASN1_OBJ_ID 6
+#define SNMP_ASN1_SEQ    16
+
+/* application specific (SNMP) tags */
+#define SNMP_ASN1_IPADDR 0    /* octet string size(4) */
+#define SNMP_ASN1_COUNTER 1   /* u32_t */
+#define SNMP_ASN1_GAUGE 2     /* u32_t */
+#define SNMP_ASN1_TIMETICKS 3 /* u32_t */
+#define SNMP_ASN1_OPAQUE 4    /* octet string */
+
+/* context specific (SNMP) tags */
+#define SNMP_ASN1_PDU_GET_REQ 0
+#define SNMP_ASN1_PDU_GET_NEXT_REQ 1
+#define SNMP_ASN1_PDU_GET_RESP 2
+#define SNMP_ASN1_PDU_SET_REQ 3
+#define SNMP_ASN1_PDU_TRAP 4
+
+err_t snmp_asn1_dec_type(struct pbuf *p, u16_t ofs, u8_t *type);
+err_t snmp_asn1_dec_length(struct pbuf *p, u16_t ofs, u8_t *octets_used, u16_t *length);
+err_t snmp_asn1_dec_u32t(struct pbuf *p, u16_t ofs, u16_t len, u32_t *value);
+err_t snmp_asn1_dec_s32t(struct pbuf *p, u16_t ofs, u16_t len, s32_t *value);
+err_t snmp_asn1_dec_oid(struct pbuf *p, u16_t ofs, u16_t len, struct snmp_obj_id *oid);
+err_t snmp_asn1_dec_raw(struct pbuf *p, u16_t ofs, u16_t len, u16_t raw_len, u8_t *raw);
+
+void snmp_asn1_enc_length_cnt(u16_t length, u8_t *octets_needed);
+void snmp_asn1_enc_u32t_cnt(u32_t value, u16_t *octets_needed);
+void snmp_asn1_enc_s32t_cnt(s32_t value, u16_t *octets_needed);
+void snmp_asn1_enc_oid_cnt(u8_t ident_len, s32_t *ident, u16_t *octets_needed);
+err_t snmp_asn1_enc_type(struct pbuf *p, u16_t ofs, u8_t type);
+err_t snmp_asn1_enc_length(struct pbuf *p, u16_t ofs, u16_t length);
+err_t snmp_asn1_enc_u32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, u32_t value);
+err_t snmp_asn1_enc_s32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, s32_t value);
+err_t snmp_asn1_enc_oid(struct pbuf *p, u16_t ofs, u8_t ident_len, s32_t *ident);
+err_t snmp_asn1_enc_raw(struct pbuf *p, u16_t ofs, u8_t raw_len, u8_t *raw);
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/snmp_msg.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/snmp_msg.h
new file mode 100644
index 0000000..4d91d30
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/snmp_msg.h
@@ -0,0 +1,292 @@
+/**
+ * @file
+ * SNMP Agent message handling structures.
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#ifndef __LWIP_SNMP_MSG_H__
+#define __LWIP_SNMP_MSG_H__
+
+#include "lwip/opt.h"
+#include "arch/cc.h"
+#include "lwip/snmp.h"
+#include "lwip/snmp_structs.h"
+
+#if SNMP_PRIVATE_MIB
+#include "private_mib.h"
+#endif
+
+#define SNMP_IN_PORT 161
+#define SNMP_TRAP_PORT 162
+
+#define SNMP_ES_NOERROR 0
+#define SNMP_ES_TOOBIG 1
+#define SNMP_ES_NOSUCHNAME 2
+#define SNMP_ES_BADVALUE 3
+#define SNMP_ES_READONLY 4
+#define SNMP_ES_GENERROR 5
+
+#define SNMP_GENTRAP_COLDSTART 0
+#define SNMP_GENTRAP_WARMSTART 1
+#define SNMP_GENTRAP_AUTHFAIL 4
+#define SNMP_GENTRAP_ENTERPRISESPC 6
+
+struct snmp_varbind
+{
+  /* next pointer, NULL for last in list */
+  struct snmp_varbind *next;
+  /* previous pointer, NULL for first in list */
+  struct snmp_varbind *prev;
+
+  /* object identifier length (in s32_t) */
+  u8_t ident_len;
+  /* object identifier array */
+  s32_t *ident;
+
+  /* object value ASN1 type */
+  u8_t value_type;
+  /* object value length (in u8_t) */
+  u8_t value_len;
+  /* object value */
+  void *value;
+
+  /* encoding varbind seq length length */
+  u8_t seqlenlen;
+  /* encoding object identifier length length */
+  u8_t olenlen;
+  /* encoding object value length length */
+  u8_t vlenlen;
+  /* encoding varbind seq length */
+  u16_t seqlen;
+  /* encoding object identifier length */
+  u16_t olen;
+  /* encoding object value length */
+  u16_t vlen;
+};
+
+struct snmp_varbind_root
+{
+  struct snmp_varbind *head;
+  struct snmp_varbind *tail;
+  /* number of variable bindings in list */
+  u8_t count;
+  /* encoding varbind-list seq length length */
+  u8_t seqlenlen;
+  /* encoding varbind-list seq length */
+  u16_t seqlen;
+};
+
+/** output response message header length fields */
+struct snmp_resp_header_lengths
+{
+  /* encoding error-index length length */
+  u8_t erridxlenlen;
+  /* encoding error-status length length */
+  u8_t errstatlenlen;
+  /* encoding request id length length */
+  u8_t ridlenlen;
+  /* encoding pdu length length */
+  u8_t pdulenlen;
+  /* encoding community length length */
+  u8_t comlenlen;
+  /* encoding version length length */
+  u8_t verlenlen;
+  /* encoding sequence length length */
+  u8_t seqlenlen;
+
+  /* encoding error-index length */
+  u16_t erridxlen;
+  /* encoding error-status length */
+  u16_t errstatlen;
+  /* encoding request id length */
+  u16_t ridlen;
+  /* encoding pdu length */
+  u16_t pdulen;
+  /* encoding community length */
+  u16_t comlen;
+  /* encoding version length */
+  u16_t verlen;
+  /* encoding sequence length */
+  u16_t seqlen;
+};
+
+/** output response message header length fields */
+struct snmp_trap_header_lengths
+{
+  /* encoding timestamp length length */
+  u8_t tslenlen;
+  /* encoding specific-trap length length */
+  u8_t strplenlen;
+  /* encoding generic-trap length length */
+  u8_t gtrplenlen;
+  /* encoding agent-addr length length */
+  u8_t aaddrlenlen;
+  /* encoding enterprise-id length length */
+  u8_t eidlenlen;
+  /* encoding pdu length length */
+  u8_t pdulenlen;
+  /* encoding community length length */
+  u8_t comlenlen;
+  /* encoding version length length */
+  u8_t verlenlen;
+  /* encoding sequence length length */
+  u8_t seqlenlen;
+
+  /* encoding timestamp length */
+  u16_t tslen;
+  /* encoding specific-trap length */
+  u16_t strplen;
+  /* encoding generic-trap length */
+  u16_t gtrplen;
+  /* encoding agent-addr length */
+  u16_t aaddrlen;
+  /* encoding enterprise-id length */
+  u16_t eidlen;
+  /* encoding pdu length */
+  u16_t pdulen;
+  /* encoding community length */
+  u16_t comlen;
+  /* encoding version length */
+  u16_t verlen;
+  /* encoding sequence length */
+  u16_t seqlen;
+};
+
+/* Accepting new SNMP messages. */
+#define SNMP_MSG_EMPTY                 0
+/* Search for matching object for variable binding. */
+#define SNMP_MSG_SEARCH_OBJ            1
+/* Perform SNMP operation on in-memory object.
+   Pass-through states, for symmetry only. */
+#define SNMP_MSG_INTERNAL_GET_OBJDEF   2
+#define SNMP_MSG_INTERNAL_GET_VALUE    3
+#define SNMP_MSG_INTERNAL_SET_TEST     4
+#define SNMP_MSG_INTERNAL_GET_OBJDEF_S 5
+#define SNMP_MSG_INTERNAL_SET_VALUE    6
+/* Perform SNMP operation on object located externally.
+   In theory this could be used for building a proxy agent.
+   Practical use is for an enterprise spc. app. gateway. */
+#define SNMP_MSG_EXTERNAL_GET_OBJDEF   7
+#define SNMP_MSG_EXTERNAL_GET_VALUE    8
+#define SNMP_MSG_EXTERNAL_SET_TEST     9
+#define SNMP_MSG_EXTERNAL_GET_OBJDEF_S 10
+#define SNMP_MSG_EXTERNAL_SET_VALUE    11
+
+#define SNMP_COMMUNITY_STR_LEN 64
+struct snmp_msg_pstat
+{
+  /* lwIP local port (161) binding */
+  struct udp_pcb *pcb;
+  /* source IP address */
+  struct ip_addr sip;
+  /* source UDP port */
+  u16_t sp;
+  /* request type */
+  u8_t rt;
+  /* request ID */
+  s32_t rid;
+  /* error status */
+  s32_t error_status;
+  /* error index */
+  s32_t error_index;
+  /* community name (zero terminated) */
+  u8_t community[SNMP_COMMUNITY_STR_LEN + 1];
+  /* community string length (exclusive zero term) */
+  u8_t com_strlen;
+  /* one out of MSG_EMPTY, MSG_DEMUX, MSG_INTERNAL, MSG_EXTERNAL_x */
+  u8_t state;
+  /* saved arguments for MSG_EXTERNAL_x */
+  struct mib_external_node *ext_mib_node;
+  struct snmp_name_ptr ext_name_ptr;
+  struct obj_def ext_object_def;
+  struct snmp_obj_id ext_oid;
+  /* index into input variable binding list */
+  u8_t vb_idx;
+  /* ptr into input variable binding list */
+  struct snmp_varbind *vb_ptr;
+  /* list of variable bindings from input */
+  struct snmp_varbind_root invb;
+  /* list of variable bindings to output */
+  struct snmp_varbind_root outvb;
+  /* output response lengths used in ASN encoding */
+  struct snmp_resp_header_lengths rhl;
+};
+
+struct snmp_msg_trap
+{
+  /* lwIP local port (161) binding */
+  struct udp_pcb *pcb;
+  /* destination IP address in network order */
+  struct ip_addr dip;
+
+  /* source enterprise ID (sysObjectID) */
+  struct snmp_obj_id *enterprise;
+  /* source IP address, raw network order format */
+  u8_t sip_raw[4];
+  /* generic trap code */
+  u32_t gen_trap;
+  /* specific trap code */
+  u32_t spc_trap;
+  /* timestamp */
+  u32_t ts;
+  /* list of variable bindings to output */
+  struct snmp_varbind_root outvb;
+  /* output trap lengths used in ASN encoding */
+  struct snmp_trap_header_lengths thl;
+};
+
+/** Agent Version constant, 0 = v1 oddity */
+extern const s32_t snmp_version;
+/** Agent default "public" community string */
+extern const char snmp_publiccommunity[7];
+
+extern struct snmp_msg_trap trap_msg;
+
+/** Agent setup, start listening to port 161. */
+void snmp_init(void);
+void snmp_trap_dst_enable(u8_t dst_idx, u8_t enable);
+void snmp_trap_dst_ip_set(u8_t dst_idx, struct ip_addr *dst);
+
+/** Varbind-list functions. */
+struct snmp_varbind* snmp_varbind_alloc(struct snmp_obj_id *oid, u8_t type, u8_t len);
+void snmp_varbind_free(struct snmp_varbind *vb);
+void snmp_varbind_list_free(struct snmp_varbind_root *root);
+void snmp_varbind_tail_add(struct snmp_varbind_root *root, struct snmp_varbind *vb);
+struct snmp_varbind* snmp_varbind_tail_remove(struct snmp_varbind_root *root);
+
+/** Handle an internal (recv) or external (private response) event. */
+void snmp_msg_event(u8_t request_id);
+err_t snmp_send_response(struct snmp_msg_pstat *m_stat);
+err_t snmp_send_trap(s8_t generic_trap, struct snmp_obj_id *eoid, s32_t specific_trap);
+void snmp_coldstart_trap(void);
+void snmp_authfail_trap(void);
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/snmp_structs.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/snmp_structs.h
new file mode 100644
index 0000000..f76632e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/snmp_structs.h
@@ -0,0 +1,253 @@
+/**
+ * @file
+ * Generic MIB tree structures.
+ *
+ * @todo namespace prefixes
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#ifndef __LWIP_SNMP_STRUCTS_H__
+#define __LWIP_SNMP_STRUCTS_H__
+
+#include "lwip/opt.h"
+#if LWIP_SNMP
+
+#include "arch/cc.h"
+#include "lwip/snmp.h"
+
+#if SNMP_PRIVATE_MIB
+#include "private_mib.h"
+#endif
+
+/* MIB object instance */
+#define MIB_OBJECT_NONE 0 
+#define MIB_OBJECT_SCALAR 1
+#define MIB_OBJECT_TAB 2
+
+/* MIB object access */
+#define MIB_OBJECT_READ_ONLY 0
+#define MIB_OBJECT_READ_WRITE 1
+#define MIB_OBJECT_WRITE_ONLY 2
+#define MIB_OBJECT_NOT_ACCESSIBLE 3
+
+/** object definition returned by (get_object_def)() */
+struct obj_def
+{
+  /* MIB_OBJECT_NONE (0), MIB_OBJECT_SCALAR (1), MIB_OBJECT_TAB (2) */
+  u8_t instance;
+  /* 0 read-only, 1 read-write, 2 write-only, 3 not-accessible */
+  u8_t access;
+  /* ASN type for this object */
+  u8_t asn_type;
+  /* value length (host length) */
+  u16_t v_len;
+  /* length of instance part of supplied object identifier */
+  u8_t  id_inst_len;
+  /* instance part of supplied object identifier */
+  s32_t *id_inst_ptr;
+};
+
+struct snmp_name_ptr
+{
+  u8_t ident_len;
+  s32_t *ident;
+};
+
+/** MIB const scalar (.0) node */
+#define MIB_NODE_SC 0x01
+/** MIB const array node */
+#define MIB_NODE_AR 0x02
+/** MIB array node (mem_malloced from RAM) */
+#define MIB_NODE_RA 0x03
+/** MIB list root node (mem_malloced from RAM) */
+#define MIB_NODE_LR 0x04
+/** MIB node for external objects */
+#define MIB_NODE_EX 0x05
+
+/** node "base class" layout, the mandatory fields for a node  */
+struct mib_node
+{
+  /** returns struct obj_def for the given object identifier */
+  void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od);
+  /** returns object value for the given object identifier,
+     @note the caller must allocate at least len bytes for the value */
+  void (*get_value)(struct obj_def *od, u16_t len, void *value);
+  /** tests length and/or range BEFORE setting */
+  u8_t (*set_test)(struct obj_def *od, u16_t len, void *value);
+  /** sets object value, only to be called when set_test()  */
+  void (*set_value)(struct obj_def *od, u16_t len, void *value);  
+  /** One out of MIB_NODE_AR, MIB_NODE_LR or MIB_NODE_EX */
+  const u8_t node_type;
+  /* array or max list length */
+  const u16_t maxlength;
+};
+
+/** derived node for scalars .0 index */
+typedef struct mib_node mib_scalar_node;
+
+/** derived node, points to a fixed size const array
+    of sub-identifiers plus a 'child' pointer */
+struct mib_array_node
+{
+  /* inherited "base class" members */
+  void (* const get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od);
+  void (* const get_value)(struct obj_def *od, u16_t len, void *value);
+  u8_t (*set_test)(struct obj_def *od, u16_t len, void *value);
+  void (*set_value)(struct obj_def *od, u16_t len, void *value);
+
+  const u8_t node_type;
+  const u16_t maxlength;
+
+  /* aditional struct members */
+  const s32_t *objid;
+  struct mib_node* const *nptr;
+};
+
+/** derived node, points to a fixed size mem_malloced array
+    of sub-identifiers plus a 'child' pointer */
+struct mib_ram_array_node
+{
+  /* inherited "base class" members */
+  void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od);
+  void (*get_value)(struct obj_def *od, u16_t len, void *value);
+  u8_t (*set_test)(struct obj_def *od, u16_t len, void *value);
+  void (*set_value)(struct obj_def *od, u16_t len, void *value);
+
+  u8_t node_type;
+  u16_t maxlength;
+
+  /* aditional struct members */
+  s32_t *objid;
+  struct mib_node **nptr;
+};
+
+struct mib_list_node
+{
+  struct mib_list_node *prev;  
+  struct mib_list_node *next;
+  s32_t objid;
+  struct mib_node *nptr;
+};
+
+/** derived node, points to a doubly linked list
+    of sub-identifiers plus a 'child' pointer */
+struct mib_list_rootnode
+{
+  /* inherited "base class" members */
+  void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od);
+  void (*get_value)(struct obj_def *od, u16_t len, void *value);
+  u8_t (*set_test)(struct obj_def *od, u16_t len, void *value);
+  void (*set_value)(struct obj_def *od, u16_t len, void *value);
+
+  u8_t node_type;
+  u16_t maxlength;
+
+  /* aditional struct members */
+  struct mib_list_node *head;
+  struct mib_list_node *tail;
+  /* counts list nodes in list  */
+  u16_t count;
+};
+
+/** derived node, has access functions for mib object in external memory or device
+    using 'tree_level' and 'idx', with a range 0 .. (level_length() - 1) */
+struct mib_external_node
+{
+  /* inherited "base class" members */
+  void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od);
+  void (*get_value)(struct obj_def *od, u16_t len, void *value);
+  u8_t (*set_test)(struct obj_def *od, u16_t len, void *value);
+  void (*set_value)(struct obj_def *od, u16_t len, void *value);
+
+  u8_t node_type;
+  u16_t maxlength;
+
+  /* aditional struct members */
+  /** points to an extenal (in memory) record of some sort of addressing
+      information, passed to and interpreted by the funtions below */
+  void* addr_inf;
+  /** tree levels under this node */
+  u8_t tree_levels;
+  /** number of objects at this level */
+  u16_t (*level_length)(void* addr_inf, u8_t level);
+  /** compares object sub identifier with external id
+      return zero when equal, nonzero when unequal */
+  s32_t (*ident_cmp)(void* addr_inf, u8_t level, u16_t idx, s32_t sub_id);
+  void (*get_objid)(void* addr_inf, u8_t level, u16_t idx, s32_t *sub_id);
+
+  /** async Questions */
+  void (*get_object_def_q)(void* addr_inf, u8_t rid, u8_t ident_len, s32_t *ident);
+  void (*get_value_q)(u8_t rid, struct obj_def *od);
+  void (*set_test_q)(u8_t rid, struct obj_def *od);
+  void (*set_value_q)(u8_t rid, struct obj_def *od, u16_t len, void *value);
+  /** async Answers */
+  void (*get_object_def_a)(u8_t rid, u8_t ident_len, s32_t *ident, struct obj_def *od);
+  void (*get_value_a)(u8_t rid, struct obj_def *od, u16_t len, void *value);
+  u8_t (*set_test_a)(u8_t rid, struct obj_def *od, u16_t len, void *value);
+  void (*set_value_a)(u8_t rid, struct obj_def *od, u16_t len, void *value);
+  /** async Panic Close (agent returns error reply, 
+      e.g. used for external transaction cleanup) */
+  void (*get_object_def_pc)(u8_t rid, u8_t ident_len, s32_t *ident);
+  void (*get_value_pc)(u8_t rid, struct obj_def *od);
+  void (*set_test_pc)(u8_t rid, struct obj_def *od);
+  void (*set_value_pc)(u8_t rid, struct obj_def *od);
+};
+
+/** export MIB tree from mib2.c */
+extern const struct mib_array_node internet;
+
+/** dummy function pointers for non-leaf MIB nodes from mib2.c */
+void noleafs_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+void noleafs_get_value(struct obj_def *od, u16_t len, void *value);
+u8_t noleafs_set_test(struct obj_def *od, u16_t len, void *value);
+void noleafs_set_value(struct obj_def *od, u16_t len, void *value);
+
+void snmp_oidtoip(s32_t *ident, struct ip_addr *ip);
+void snmp_iptooid(struct ip_addr *ip, s32_t *ident);
+void snmp_ifindextonetif(s32_t ifindex, struct netif **netif);
+void snmp_netiftoifindex(struct netif *netif, s32_t *ifidx);
+
+struct mib_list_node* snmp_mib_ln_alloc(s32_t id);
+void snmp_mib_ln_free(struct mib_list_node *ln);
+struct mib_list_rootnode* snmp_mib_lrn_alloc(void);
+void snmp_mib_lrn_free(struct mib_list_rootnode *lrn);
+
+s8_t snmp_mib_node_insert(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **insn);
+s8_t snmp_mib_node_find(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **fn);
+struct mib_list_rootnode *snmp_mib_node_delete(struct mib_list_rootnode *rn, struct mib_list_node *n);
+
+struct mib_node* snmp_search_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_name_ptr *np);
+struct mib_node* snmp_expand_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret);
+u8_t snmp_iso_prefix_tst(u8_t ident_len, s32_t *ident);
+u8_t snmp_iso_prefix_expand(u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret);
+
+#endif /* LWIP_SNMP */
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/sockets.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/sockets.h
new file mode 100644
index 0000000..9c25035
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/sockets.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+#ifndef __LWIP_SOCKETS_H__
+#define __LWIP_SOCKETS_H__
+#include "lwip/ip_addr.h"
+
+struct sockaddr_in {
+  u8_t sin_len;
+  u8_t sin_family;
+  u16_t sin_port;
+  struct in_addr sin_addr;
+  char sin_zero[8];
+};
+
+struct sockaddr {
+  u8_t sa_len;
+  u8_t sa_family;
+  char sa_data[14];
+};
+
+#ifndef socklen_t
+#  define socklen_t int
+#endif
+
+
+#define SOCK_STREAM     1
+#define SOCK_DGRAM      2
+#define SOCK_RAW        3
+
+/*
+ * Option flags per-socket.
+ */
+#define  SO_DEBUG  0x0001    /* turn on debugging info recording */
+#define  SO_ACCEPTCONN  0x0002    /* socket has had listen() */
+#define  SO_REUSEADDR  0x0004    /* allow local address reuse */
+#define  SO_KEEPALIVE  0x0008    /* keep connections alive */
+#define  SO_DONTROUTE  0x0010    /* just use interface addresses */
+#define  SO_BROADCAST  0x0020    /* permit sending of broadcast msgs */
+#define  SO_USELOOPBACK  0x0040    /* bypass hardware when possible */
+#define  SO_LINGER  0x0080    /* linger on close if data present */
+#define  SO_OOBINLINE  0x0100    /* leave received OOB data in line */
+#define	 SO_REUSEPORT	0x0200		/* allow local address & port reuse */
+
+#define SO_DONTLINGER   (int)(~SO_LINGER)
+
+/*
+ * Additional options, not kept in so_options.
+ */
+#define SO_SNDBUF  0x1001    /* send buffer size */
+#define SO_RCVBUF  0x1002    /* receive buffer size */
+#define SO_SNDLOWAT  0x1003    /* send low-water mark */
+#define SO_RCVLOWAT  0x1004    /* receive low-water mark */
+#define SO_SNDTIMEO  0x1005    /* send timeout */
+#define SO_RCVTIMEO  0x1006    /* receive timeout */
+#define  SO_ERROR  0x1007    /* get error status and clear */
+#define  SO_TYPE    0x1008    /* get socket type */
+
+
+
+/*
+ * Structure used for manipulating linger option.
+ */
+struct linger {
+       int l_onoff;                /* option on/off */
+       int l_linger;               /* linger time */
+};
+
+/*
+ * Level number for (get/set)sockopt() to apply to socket itself.
+ */
+#define  SOL_SOCKET  0xfff    /* options for socket level */
+
+
+#define AF_UNSPEC       0
+#define AF_INET         2
+#define PF_INET         AF_INET
+#define PF_UNSPEC       AF_UNSPEC
+
+#define IPPROTO_IP      0
+#define IPPROTO_TCP     6
+#define IPPROTO_UDP     17
+
+#define INADDR_ANY      0
+#define INADDR_BROADCAST 0xffffffff
+
+/* Flags we can use with send and recv. */
+#define MSG_DONTWAIT    0x40            /* Nonblocking i/o for this operation only */
+
+
+/*
+ * Options for level IPPROTO_IP
+ */
+#define IP_TOS       1
+#define IP_TTL       2
+
+
+#define IPTOS_TOS_MASK          0x1E
+#define IPTOS_TOS(tos)          ((tos) & IPTOS_TOS_MASK)
+#define IPTOS_LOWDELAY          0x10
+#define IPTOS_THROUGHPUT        0x08
+#define IPTOS_RELIABILITY       0x04
+#define IPTOS_LOWCOST           0x02
+#define IPTOS_MINCOST           IPTOS_LOWCOST
+
+/*
+ * Definitions for IP precedence (also in ip_tos) (hopefully unused)
+ */
+#define IPTOS_PREC_MASK                 0xe0
+#define IPTOS_PREC(tos)                ((tos) & IPTOS_PREC_MASK)
+#define IPTOS_PREC_NETCONTROL           0xe0
+#define IPTOS_PREC_INTERNETCONTROL      0xc0
+#define IPTOS_PREC_CRITIC_ECP           0xa0
+#define IPTOS_PREC_FLASHOVERRIDE        0x80
+#define IPTOS_PREC_FLASH                0x60
+#define IPTOS_PREC_IMMEDIATE            0x40
+#define IPTOS_PREC_PRIORITY             0x20
+#define IPTOS_PREC_ROUTINE              0x00
+
+
+/*
+ * Commands for ioctlsocket(),  taken from the BSD file fcntl.h.
+ *
+ *
+ * Ioctl's have the command encoded in the lower word,
+ * and the size of any in or out parameters in the upper
+ * word.  The high 2 bits of the upper word are used
+ * to encode the in/out status of the parameter; for now
+ * we restrict parameters to at most 128 bytes.
+ */
+#if !defined(FIONREAD) || !defined(FIONBIO)
+#define IOCPARM_MASK    0x7f            /* parameters must be < 128 bytes */
+#define IOC_VOID        0x20000000      /* no parameters */
+#define IOC_OUT         0x40000000      /* copy out parameters */
+#define IOC_IN          0x80000000      /* copy in parameters */
+#define IOC_INOUT       (IOC_IN|IOC_OUT)
+                                        /* 0x20000000 distinguishes new &
+                                           old ioctl's */
+#define _IO(x,y)        (IOC_VOID|((x)<<8)|(y))
+
+#define _IOR(x,y,t)     (IOC_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
+
+#define _IOW(x,y,t)     (IOC_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
+#endif
+
+#ifndef FIONREAD
+#define FIONREAD    _IOR('f', 127, unsigned long) /* get # bytes to read */
+#endif
+#ifndef FIONBIO
+#define FIONBIO     _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */
+#endif
+
+/* Socket I/O Controls */
+#ifndef SIOCSHIWAT
+#define SIOCSHIWAT  _IOW('s',  0, unsigned long)  /* set high watermark */
+#define SIOCGHIWAT  _IOR('s',  1, unsigned long)  /* get high watermark */
+#define SIOCSLOWAT  _IOW('s',  2, unsigned long)  /* set low watermark */
+#define SIOCGLOWAT  _IOR('s',  3, unsigned long)  /* get low watermark */
+#define SIOCATMARK  _IOR('s',  7, unsigned long)  /* at oob mark? */
+#endif
+
+#ifndef O_NONBLOCK
+#define O_NONBLOCK    04000U
+#endif
+
+#ifndef FD_SET
+  #undef  FD_SETSIZE
+  #define FD_SETSIZE    16
+  #define FD_SET(n, p)  ((p)->fd_bits[(n)/8] |=  (1 << ((n) & 7)))
+  #define FD_CLR(n, p)  ((p)->fd_bits[(n)/8] &= ~(1 << ((n) & 7)))
+  #define FD_ISSET(n,p) ((p)->fd_bits[(n)/8] &   (1 << ((n) & 7)))
+  #define FD_ZERO(p)    memset((void*)(p),0,sizeof(*(p)))
+
+  typedef struct fd_set {
+          unsigned char fd_bits [(FD_SETSIZE+7)/8];
+        } fd_set;
+
+/* 
+ * only define this in sockets.c so it does not interfere
+ * with other projects namespaces where timeval is present
+ */ 
+#ifndef LWIP_TIMEVAL_PRIVATE
+#define LWIP_TIMEVAL_PRIVATE 1
+#endif
+
+#if LWIP_TIMEVAL_PRIVATE
+  struct timeval {
+    long    tv_sec;         /* seconds */
+    long    tv_usec;        /* and microseconds */
+  };
+#endif
+
+#endif
+
+int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen);
+int lwip_bind(int s, struct sockaddr *name, socklen_t namelen);
+int lwip_shutdown(int s, int how);
+int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen);
+int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen);
+int lwip_close(int s);
+int lwip_connect(int s, struct sockaddr *name, socklen_t namelen);
+int lwip_listen(int s, int backlog);
+int lwip_recv(int s, void *mem, int len, unsigned int flags);
+int lwip_read(int s, void *mem, int len);
+int lwip_recvfrom(int s, void *mem, int len, unsigned int flags,
+      struct sockaddr *from, socklen_t *fromlen);
+int lwip_send(int s, void *dataptr, int size, unsigned int flags);
+int lwip_sendto(int s, void *dataptr, int size, unsigned int flags,
+    struct sockaddr *to, socklen_t tolen);
+int lwip_socket(int domain, int type, int protocol);
+int lwip_write(int s, void *dataptr, int size);
+int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
+                struct timeval *timeout);
+int lwip_ioctl(int s, long cmd, void *argp);
+
+#if LWIP_COMPAT_SOCKETS
+#define accept(a,b,c)         lwip_accept(a,b,c)
+#define bind(a,b,c)           lwip_bind(a,b,c)
+#define shutdown(a,b)         lwip_shutdown(a,b)
+#define close(s)              lwip_close(s)
+#define connect(a,b,c)        lwip_connect(a,b,c)
+#define getsockname(a,b,c)    lwip_getsockname(a,b,c)
+#define getpeername(a,b,c)    lwip_getpeername(a,b,c)
+#define setsockopt(a,b,c,d,e) lwip_setsockopt(a,b,c,d,e)
+#define getsockopt(a,b,c,d,e) lwip_getsockopt(a,b,c,d,e)
+#define listen(a,b)           lwip_listen(a,b)
+#define recv(a,b,c,d)         lwip_recv(a,b,c,d)
+#define read(a,b,c)           lwip_read(a,b,c)
+#define recvfrom(a,b,c,d,e,f) lwip_recvfrom(a,b,c,d,e,f)
+#define send(a,b,c,d)         lwip_send(a,b,c,d)
+#define sendto(a,b,c,d,e,f)   lwip_sendto(a,b,c,d,e,f)
+#define socket(a,b,c)         lwip_socket(a,b,c)
+#define write(a,b,c)          lwip_write(a,b,c)
+#define select(a,b,c,d,e)     lwip_select(a,b,c,d,e)
+#define ioctlsocket(a,b,c)    lwip_ioctl(a,b,c)
+#endif /* LWIP_COMPAT_SOCKETS */
+
+#endif /* __LWIP_SOCKETS_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/stats.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/stats.h
new file mode 100644
index 0000000..29dfd57
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/stats.h
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_STATS_H__
+#define __LWIP_STATS_H__
+
+#include "lwip/opt.h"
+#include "arch/cc.h"
+
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+
+#if LWIP_STATS
+
+struct stats_proto {
+  u16_t xmit;    /* Transmitted packets. */
+  u16_t rexmit;  /* Retransmitted packets. */
+  u16_t recv;    /* Received packets. */
+  u16_t fw;      /* Forwarded packets. */
+  u16_t drop;    /* Dropped packets. */
+  u16_t chkerr;  /* Checksum error. */
+  u16_t lenerr;  /* Invalid length error. */
+  u16_t memerr;  /* Out of memory error. */
+  u16_t rterr;   /* Routing error. */
+  u16_t proterr; /* Protocol error. */
+  u16_t opterr;  /* Error in options. */
+  u16_t err;     /* Misc error. */
+  u16_t cachehit;
+};
+
+struct stats_mem {
+  mem_size_t avail;
+  mem_size_t used;
+  mem_size_t max;  
+  mem_size_t err;
+};
+
+struct stats_pbuf {
+  u16_t avail;
+  u16_t used;
+  u16_t max;  
+  u16_t err;
+
+  u16_t alloc_locked;
+  u16_t refresh_locked;
+};
+
+struct stats_syselem {
+  u16_t used;
+  u16_t max;
+  u16_t err;
+};
+
+struct stats_sys {
+  struct stats_syselem sem;
+  struct stats_syselem mbox;
+};
+
+struct stats_ {
+  struct stats_proto link;
+  struct stats_proto ip_frag;
+  struct stats_proto ip;
+  struct stats_proto icmp;
+  struct stats_proto udp;
+  struct stats_proto tcp;
+  struct stats_pbuf pbuf;
+  struct stats_mem mem;
+  struct stats_mem memp[MEMP_MAX];
+  struct stats_sys sys;
+};
+
+extern struct stats_ lwip_stats;
+
+
+void stats_init(void);
+
+#define STATS_INC(x) ++lwip_stats.x
+#else
+#define stats_init()
+#define STATS_INC(x)
+#endif /* LWIP_STATS */
+
+#if TCP_STATS
+#define TCP_STATS_INC(x) STATS_INC(x)
+#else
+#define TCP_STATS_INC(x)
+#endif
+
+#if UDP_STATS
+#define UDP_STATS_INC(x) STATS_INC(x)
+#else
+#define UDP_STATS_INC(x)
+#endif
+
+#if ICMP_STATS
+#define ICMP_STATS_INC(x) STATS_INC(x)
+#else
+#define ICMP_STATS_INC(x)
+#endif
+
+#if IP_STATS
+#define IP_STATS_INC(x) STATS_INC(x)
+#else
+#define IP_STATS_INC(x)
+#endif
+
+#if IPFRAG_STATS
+#define IPFRAG_STATS_INC(x) STATS_INC(x)
+#else
+#define IPFRAG_STATS_INC(x)
+#endif
+
+#if LINK_STATS
+#define LINK_STATS_INC(x) STATS_INC(x)
+#else
+#define LINK_STATS_INC(x)
+#endif
+
+/* Display of statistics */
+#if LWIP_STATS_DISPLAY
+void stats_display(void);
+#else
+#define stats_display()
+#endif
+
+#endif /* __LWIP_STATS_H__ */
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/sys.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/sys.h
new file mode 100644
index 0000000..ce8d5ff
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/sys.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_SYS_H__
+#define __LWIP_SYS_H__
+
+#include "arch/cc.h"
+
+#include "lwip/opt.h"
+
+
+#if NO_SYS
+
+/* For a totally minimal and standalone system, we provide null
+   definitions of the sys_ functions. */
+typedef u8_t sys_sem_t;
+typedef u8_t sys_mbox_t;
+struct sys_timeo {u8_t dummy;};
+
+#define sys_init()
+#define sys_timeout(m,h,a)
+#define sys_untimeout(m,a)
+#define sys_sem_new(c) c
+#define sys_sem_signal(s)
+#define sys_sem_wait(s)
+#define sys_sem_free(s)
+#define sys_mbox_new() 0
+#define sys_mbox_fetch(m,d)
+#define sys_mbox_post(m,d)
+#define sys_mbox_free(m)
+
+#define sys_thread_new(t,a,p)
+
+#else /* NO_SYS */
+
+#include "arch/sys_arch.h"
+
+/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */
+#define SYS_ARCH_TIMEOUT 0xffffffff
+
+typedef void (* sys_timeout_handler)(void *arg);
+
+struct sys_timeo {
+  struct sys_timeo *next;
+  u32_t time;
+  sys_timeout_handler h;
+  void *arg;
+};
+
+struct sys_timeouts {
+  struct sys_timeo *next;
+};
+
+/* sys_init() must be called before anthing else. */
+void sys_init(void);
+
+/*
+ * sys_timeout():
+ *
+ * Schedule a timeout a specified amount of milliseconds in the
+ * future. When the timeout occurs, the specified timeout handler will
+ * be called. The handler will be passed the "arg" argument when
+ * called.
+ *
+ */
+void sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg);
+void sys_untimeout(sys_timeout_handler h, void *arg);
+struct sys_timeouts *sys_arch_timeouts(void);
+
+/* Semaphore functions. */
+sys_sem_t sys_sem_new(u8_t count);
+void sys_sem_signal(sys_sem_t sem);
+u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout);
+void sys_sem_free(sys_sem_t sem);
+void sys_sem_wait(sys_sem_t sem);
+int sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout);
+
+/* Time functions. */
+#ifndef sys_msleep
+void sys_msleep(u32_t ms); /* only has a (close to) 1 jiffy resolution. */
+#endif
+#ifndef sys_jiffies
+u32_t sys_jiffies(void); /* since power up. */
+#endif
+
+/* Mailbox functions. */
+sys_mbox_t sys_mbox_new(void);
+void sys_mbox_post(sys_mbox_t mbox, void *msg);
+u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout);
+void sys_mbox_free(sys_mbox_t mbox);
+void sys_mbox_fetch(sys_mbox_t mbox, void **msg);
+
+
+/* Thread functions. */
+sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio);
+
+/* The following functions are used only in Unix code, and
+   can be omitted when porting the stack. */
+/* Returns the current time in microseconds. */
+unsigned long sys_now(void);
+
+#endif /* NO_SYS */
+
+/* Critical Region Protection */
+/* These functions must be implemented in the sys_arch.c file.
+   In some implementations they can provide a more light-weight protection
+   mechanism than using semaphores. Otherwise semaphores can be used for
+   implementation */
+#ifndef SYS_ARCH_PROTECT
+/** SYS_LIGHTWEIGHT_PROT
+ * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
+ * for certain critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#if SYS_LIGHTWEIGHT_PROT
+
+/** SYS_ARCH_DECL_PROTECT
+ * declare a protection variable. This macro will default to defining a variable of
+ * type sys_prot_t. If a particular port needs a different implementation, then
+ * this macro may be defined in sys_arch.h.
+ */
+#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev
+/** SYS_ARCH_PROTECT
+ * Perform a "fast" protect. This could be implemented by
+ * disabling interrupts for an embedded system or by using a semaphore or
+ * mutex. The implementation should allow calling SYS_ARCH_PROTECT when
+ * already protected. The old protection level is returned in the variable
+ * "lev". This macro will default to calling the sys_arch_protect() function
+ * which should be implemented in sys_arch.c. If a particular port needs a
+ * different implementation, then this macro may be defined in sys_arch.h
+ */
+#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect()
+/** SYS_ARCH_UNPROTECT
+ * Perform a "fast" set of the protection level to "lev". This could be
+ * implemented by setting the interrupt level to "lev" within the MACRO or by
+ * using a semaphore or mutex.  This macro will default to calling the
+ * sys_arch_unprotect() function which should be implemented in
+ * sys_arch.c. If a particular port needs a different implementation, then
+ * this macro may be defined in sys_arch.h
+ */
+#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev)
+sys_prot_t sys_arch_protect(void);
+void sys_arch_unprotect(sys_prot_t pval);
+
+#else
+
+#define SYS_ARCH_DECL_PROTECT(lev)
+#define SYS_ARCH_PROTECT(lev)
+#define SYS_ARCH_UNPROTECT(lev)
+
+#endif /* SYS_LIGHTWEIGHT_PROT */
+
+#endif /* SYS_ARCH_PROTECT */
+
+#endif /* __LWIP_SYS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/tcp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/tcp.h
new file mode 100644
index 0000000..b4f78bf
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/tcp.h
@@ -0,0 +1,531 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_TCP_H__
+#define __LWIP_TCP_H__
+
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/opt.h"
+#include "lwip/ip.h"
+#include "lwip/icmp.h"
+
+#include "lwip/err.h"
+
+struct tcp_pcb;
+
+/* Functions for interfacing with TCP: */
+
+/* Lower layer interface to TCP: */
+void             tcp_init    (void);  /* Must be called first to
+           initialize TCP. */
+void             tcp_tmr     (void);  /* Must be called every
+           TCP_TMR_INTERVAL
+           ms. (Typically 250 ms). */
+/* Application program's interface: */
+struct tcp_pcb * tcp_new     (void);
+struct tcp_pcb * tcp_alloc   (u8_t prio);
+
+void             tcp_arg     (struct tcp_pcb *pcb, void *arg);
+void             tcp_accept  (struct tcp_pcb *pcb,
+            err_t (* accept)(void *arg, struct tcp_pcb *newpcb,
+                 err_t err));
+void             tcp_recv    (struct tcp_pcb *pcb,
+            err_t (* recv)(void *arg, struct tcp_pcb *tpcb,
+          struct pbuf *p, err_t err));
+void             tcp_sent    (struct tcp_pcb *pcb,
+            err_t (* sent)(void *arg, struct tcp_pcb *tpcb,
+               u16_t len));
+void             tcp_poll    (struct tcp_pcb *pcb,
+            err_t (* poll)(void *arg, struct tcp_pcb *tpcb),
+            u8_t interval);
+void             tcp_err     (struct tcp_pcb *pcb,
+            void (* err)(void *arg, err_t err));
+
+#define          tcp_mss(pcb)      ((pcb)->mss)
+#define          tcp_sndbuf(pcb)   ((pcb)->snd_buf)
+
+void             tcp_recved  (struct tcp_pcb *pcb, u16_t len);
+err_t            tcp_bind    (struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+            u16_t port);
+err_t            tcp_connect (struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+            u16_t port, err_t (* connected)(void *arg,
+                    struct tcp_pcb *tpcb,
+                    err_t err));
+struct tcp_pcb * tcp_listen  (struct tcp_pcb *pcb);
+void             tcp_abort   (struct tcp_pcb *pcb);
+err_t            tcp_close   (struct tcp_pcb *pcb);
+err_t            tcp_write   (struct tcp_pcb *pcb, const void *dataptr, u16_t len,
+            u8_t copy);
+
+void             tcp_setprio (struct tcp_pcb *pcb, u8_t prio);
+
+#define TCP_PRIO_MIN    1
+#define TCP_PRIO_NORMAL 64
+#define TCP_PRIO_MAX    127
+
+/* It is also possible to call these two functions at the right
+   intervals (instead of calling tcp_tmr()). */
+void             tcp_slowtmr (void);
+void             tcp_fasttmr (void);
+
+
+/* Only used by IP to pass a TCP segment to TCP: */
+void             tcp_input   (struct pbuf *p, struct netif *inp);
+/* Used within the TCP code only: */
+err_t            tcp_output  (struct tcp_pcb *pcb);
+void             tcp_rexmit  (struct tcp_pcb *pcb);
+void             tcp_rexmit_rto  (struct tcp_pcb *pcb);
+
+
+
+#define TCP_SEQ_LT(a,b)     ((s32_t)((a)-(b)) < 0)
+#define TCP_SEQ_LEQ(a,b)    ((s32_t)((a)-(b)) <= 0)
+#define TCP_SEQ_GT(a,b)     ((s32_t)((a)-(b)) > 0)
+#define TCP_SEQ_GEQ(a,b)    ((s32_t)((a)-(b)) >= 0)
+/* is b<=a<=c? */
+#if 0 /* see bug #10548 */
+#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b))
+#endif
+#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c))
+#define TCP_FIN 0x01U
+#define TCP_SYN 0x02U
+#define TCP_RST 0x04U
+#define TCP_PSH 0x08U
+#define TCP_ACK 0x10U
+#define TCP_URG 0x20U
+#define TCP_ECE 0x40U
+#define TCP_CWR 0x80U
+
+#define TCP_FLAGS 0x3fU
+
+/* Length of the TCP header, excluding options. */
+#define TCP_HLEN 20
+
+#ifndef TCP_TMR_INTERVAL
+#define TCP_TMR_INTERVAL       250  /* The TCP timer interval in
+                                       milliseconds. */
+#endif /* TCP_TMR_INTERVAL */
+
+#ifndef TCP_FAST_INTERVAL
+#define TCP_FAST_INTERVAL      TCP_TMR_INTERVAL /* the fine grained timeout in
+                                       milliseconds */
+#endif /* TCP_FAST_INTERVAL */
+
+#ifndef TCP_SLOW_INTERVAL
+#define TCP_SLOW_INTERVAL      (2*TCP_TMR_INTERVAL)  /* the coarse grained timeout in
+                                       milliseconds */
+#endif /* TCP_SLOW_INTERVAL */
+
+#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */
+#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */
+
+#define TCP_OOSEQ_TIMEOUT        6U /* x RTO */
+
+#define TCP_MSL 60000  /* The maximum segment lifetime in microseconds */
+
+/*
+ * User-settable options (used with setsockopt).
+ */
+#define TCP_NODELAY    0x01    /* don't delay send to coalesce packets */
+#define TCP_KEEPALIVE  0x02    /* send KEEPALIVE probes when idle for pcb->keepalive miliseconds */
+
+/* Keepalive values */
+#define  TCP_KEEPDEFAULT   7200000                       /* KEEPALIVE timer in miliseconds */
+#define  TCP_KEEPINTVL     75000                         /* Time between KEEPALIVE probes in miliseconds */
+#define  TCP_KEEPCNT       9                             /* Counter for KEEPALIVE probes */
+#define  TCP_MAXIDLE       TCP_KEEPCNT * TCP_KEEPINTVL   /* Maximum KEEPALIVE probe time */
+
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct tcp_hdr {
+  PACK_STRUCT_FIELD(u16_t src);
+  PACK_STRUCT_FIELD(u16_t dest);
+  PACK_STRUCT_FIELD(u32_t seqno);
+  PACK_STRUCT_FIELD(u32_t ackno);
+  PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags);
+  PACK_STRUCT_FIELD(u16_t wnd);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u16_t urgp);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define TCPH_OFFSET(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 8)
+#define TCPH_HDRLEN(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 12)
+#define TCPH_FLAGS(phdr)  (ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS)
+
+#define TCPH_OFFSET_SET(phdr, offset) (phdr)->_hdrlen_rsvd_flags = htons(((offset) << 8) | TCPH_FLAGS(phdr))
+#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | TCPH_FLAGS(phdr))
+#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons((ntohs((phdr)->_hdrlen_rsvd_flags) & ~TCP_FLAGS) | (flags))
+#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (flags))
+#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (TCPH_FLAGS(phdr) & ~(flags)) )
+
+#define TCP_TCPLEN(seg) ((seg)->len + ((TCPH_FLAGS((seg)->tcphdr) & TCP_FIN || \
+          TCPH_FLAGS((seg)->tcphdr) & TCP_SYN)? 1: 0))
+
+enum tcp_state {
+  CLOSED      = 0,
+  LISTEN      = 1,
+  SYN_SENT    = 2,
+  SYN_RCVD    = 3,
+  ESTABLISHED = 4,
+  FIN_WAIT_1  = 5,
+  FIN_WAIT_2  = 6,
+  CLOSE_WAIT  = 7,
+  CLOSING     = 8,
+  LAST_ACK    = 9,
+  TIME_WAIT   = 10
+};
+
+/* the TCP protocol control block */
+struct tcp_pcb {
+/** common PCB members */
+  IP_PCB;
+/** protocol specific PCB members */
+  struct tcp_pcb *next; /* for the linked list */
+  enum tcp_state state; /* TCP state */
+  u8_t prio;
+  void *callback_arg;
+
+  u16_t local_port;
+  u16_t remote_port;
+  
+  u8_t flags;
+#define TF_ACK_DELAY (u8_t)0x01U   /* Delayed ACK. */
+#define TF_ACK_NOW   (u8_t)0x02U   /* Immediate ACK. */
+#define TF_INFR      (u8_t)0x04U   /* In fast recovery. */
+#define TF_RESET     (u8_t)0x08U   /* Connection was reset. */
+#define TF_CLOSED    (u8_t)0x10U   /* Connection was sucessfully closed. */
+#define TF_GOT_FIN   (u8_t)0x20U   /* Connection was closed by the remote end. */
+#define TF_NODELAY   (u8_t)0x40U   /* Disable Nagle algorithm */
+
+  /* receiver variables */
+  u32_t rcv_nxt;   /* next seqno expected */
+  u16_t rcv_wnd;   /* receiver window */
+  
+  /* Timers */
+  u32_t tmr;
+  u8_t polltmr, pollinterval;
+  
+  /* Retransmission timer. */
+  u16_t rtime;
+  
+  u16_t mss;   /* maximum segment size */
+  
+  /* RTT (round trip time) estimation variables */
+  u32_t rttest; /* RTT estimate in 500ms ticks */
+  u32_t rtseq;  /* sequence number being timed */
+  s16_t sa, sv; /* @todo document this */
+
+  u16_t rto;    /* retransmission time-out */
+  u8_t nrtx;    /* number of retransmissions */
+
+  /* fast retransmit/recovery */
+  u32_t lastack; /* Highest acknowledged seqno. */
+  u8_t dupacks;
+  
+  /* congestion avoidance/control variables */
+  u16_t cwnd;  
+  u16_t ssthresh;
+
+  /* sender variables */
+  u32_t snd_nxt,       /* next seqno to be sent */
+    snd_max,       /* Highest seqno sent. */
+    snd_wnd,       /* sender window */
+    snd_wl1, snd_wl2, /* Sequence and acknowledgement numbers of last
+       window update. */
+    snd_lbb;       /* Sequence number of next byte to be buffered. */
+
+  u16_t acked;
+  
+  u16_t snd_buf;   /* Available buffer space for sending (in bytes). */
+  u8_t snd_queuelen; /* Available buffer space for sending (in tcp_segs). */
+  
+  
+  /* These are ordered by sequence number: */
+  struct tcp_seg *unsent;   /* Unsent (queued) segments. */
+  struct tcp_seg *unacked;  /* Sent but unacknowledged segments. */
+#if TCP_QUEUE_OOSEQ  
+  struct tcp_seg *ooseq;    /* Received out of sequence segments. */
+#endif /* TCP_QUEUE_OOSEQ */
+
+#if LWIP_CALLBACK_API
+  /* Function to be called when more send buffer space is available. */
+  err_t (* sent)(void *arg, struct tcp_pcb *pcb, u16_t space);
+  
+  /* Function to be called when (in-sequence) data has arrived. */
+  err_t (* recv)(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err);
+
+  /* Function to be called when a connection has been set up. */
+  err_t (* connected)(void *arg, struct tcp_pcb *pcb, err_t err);
+
+  /* Function to call when a listener has been connected. */
+  err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err);
+
+  /* Function which is called periodically. */
+  err_t (* poll)(void *arg, struct tcp_pcb *pcb);
+
+  /* Function to be called whenever a fatal error occurs. */
+  void (* errf)(void *arg, err_t err);
+#endif /* LWIP_CALLBACK_API */
+
+  /* idle time before KEEPALIVE is sent */
+  u32_t keepalive;
+  
+  /* KEEPALIVE counter */
+  u8_t keep_cnt;
+};
+
+struct tcp_pcb_listen {  
+/* Common members of all PCB types */
+  IP_PCB;
+
+/* Protocol specific PCB members */
+  struct tcp_pcb_listen *next;   /* for the linked list */
+  
+  /* Even if state is obviously LISTEN this is here for
+   * field compatibility with tpc_pcb to which it is cast sometimes
+   * Until a cleaner solution emerges this is here.FIXME
+   */ 
+  enum tcp_state state;   /* TCP state */
+
+  u8_t prio;
+  void *callback_arg;
+  
+  u16_t local_port; 
+
+#if LWIP_CALLBACK_API
+  /* Function to call when a listener has been connected. */
+  err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err);
+#endif /* LWIP_CALLBACK_API */
+};
+
+#if LWIP_EVENT_API
+
+enum lwip_event {
+  LWIP_EVENT_ACCEPT,
+  LWIP_EVENT_SENT,
+  LWIP_EVENT_RECV,
+  LWIP_EVENT_CONNECTED,
+  LWIP_EVENT_POLL,
+  LWIP_EVENT_ERR
+};
+
+err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb,
+         enum lwip_event,
+         struct pbuf *p,
+         u16_t size,
+         err_t err);
+
+#define TCP_EVENT_ACCEPT(pcb,err,ret)    ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_ACCEPT, NULL, 0, err)
+#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                   LWIP_EVENT_SENT, NULL, space, ERR_OK)
+#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_RECV, (p), 0, (err))
+#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_CONNECTED, NULL, 0, (err))
+#define TCP_EVENT_POLL(pcb,ret)       ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_POLL, NULL, 0, ERR_OK)
+#define TCP_EVENT_ERR(errf,arg,err)  lwip_tcp_event((arg), NULL, \
+                LWIP_EVENT_ERR, NULL, 0, (err))
+#else /* LWIP_EVENT_API */
+#define TCP_EVENT_ACCEPT(pcb,err,ret)     \
+                        if((pcb)->accept != NULL) \
+                        (ret = (pcb)->accept((pcb)->callback_arg,(pcb),(err)))
+#define TCP_EVENT_SENT(pcb,space,ret) \
+                        if((pcb)->sent != NULL) \
+                        (ret = (pcb)->sent((pcb)->callback_arg,(pcb),(space)))
+#define TCP_EVENT_RECV(pcb,p,err,ret) \
+                        if((pcb)->recv != NULL) \
+                        { ret = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err)); } else { \
+                          if (p) pbuf_free(p); }
+#define TCP_EVENT_CONNECTED(pcb,err,ret) \
+                        if((pcb)->connected != NULL) \
+                        (ret = (pcb)->connected((pcb)->callback_arg,(pcb),(err)))
+#define TCP_EVENT_POLL(pcb,ret) \
+                        if((pcb)->poll != NULL) \
+                        (ret = (pcb)->poll((pcb)->callback_arg,(pcb)))
+#define TCP_EVENT_ERR(errf,arg,err) \
+                        if((errf) != NULL) \
+                        (errf)((arg),(err))
+#endif /* LWIP_EVENT_API */
+
+/* This structure represents a TCP segment on the unsent and unacked queues */
+struct tcp_seg {
+  struct tcp_seg *next;    /* used when putting segements on a queue */
+  struct pbuf *p;          /* buffer containing data + TCP header */
+  void *dataptr;           /* pointer to the TCP data in the pbuf */
+  u16_t len;               /* the TCP length of this segment */
+  struct tcp_hdr *tcphdr;  /* the TCP header */
+};
+
+/* Internal functions and global variables: */
+struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb);
+void tcp_pcb_purge(struct tcp_pcb *pcb);
+void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb);
+
+u8_t tcp_segs_free(struct tcp_seg *seg);
+u8_t tcp_seg_free(struct tcp_seg *seg);
+struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg);
+
+#define tcp_ack(pcb)     if((pcb)->flags & TF_ACK_DELAY) { \
+                            (pcb)->flags &= ~TF_ACK_DELAY; \
+                            (pcb)->flags |= TF_ACK_NOW; \
+                            tcp_output(pcb); \
+                         } else { \
+                            (pcb)->flags |= TF_ACK_DELAY; \
+                         }
+
+#define tcp_ack_now(pcb) (pcb)->flags |= TF_ACK_NOW; \
+                         tcp_output(pcb)
+
+err_t tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags);
+err_t tcp_enqueue(struct tcp_pcb *pcb, void *dataptr, u16_t len,
+    u8_t flags, u8_t copy,
+                u8_t *optdata, u8_t optlen);
+
+void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg);
+
+void tcp_rst(u32_t seqno, u32_t ackno,
+       struct ip_addr *local_ip, struct ip_addr *remote_ip,
+       u16_t local_port, u16_t remote_port);
+
+u32_t tcp_next_iss(void);
+
+void tcp_keepalive(struct tcp_pcb *pcb);
+
+extern struct tcp_pcb *tcp_input_pcb;
+extern u32_t tcp_ticks;
+
+#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
+void tcp_debug_print(struct tcp_hdr *tcphdr);
+void tcp_debug_print_flags(u8_t flags);
+void tcp_debug_print_state(enum tcp_state s);
+void tcp_debug_print_pcbs(void);
+s16_t tcp_pcbs_sane(void);
+#else
+#  define tcp_debug_print(tcphdr)
+#  define tcp_debug_print_flags(flags)
+#  define tcp_debug_print_state(s)
+#  define tcp_debug_print_pcbs()
+#  define tcp_pcbs_sane() 1
+#endif /* TCP_DEBUG */
+
+#if NO_SYS
+#define tcp_timer_needed()
+#else
+void tcp_timer_needed(void);
+#endif
+
+/* The TCP PCB lists. */
+union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */
+  struct tcp_pcb_listen *listen_pcbs; 
+  struct tcp_pcb *pcbs;
+};
+extern union tcp_listen_pcbs_t tcp_listen_pcbs;
+extern struct tcp_pcb *tcp_active_pcbs;  /* List of all TCP PCBs that are in a
+              state in which they accept or send
+              data. */
+extern struct tcp_pcb *tcp_tw_pcbs;      /* List of all TCP PCBs in TIME-WAIT. */
+
+extern struct tcp_pcb *tcp_tmp_pcb;      /* Only used for temporary storage. */
+
+/* Axioms about the above lists:   
+   1) Every TCP PCB that is not CLOSED is in one of the lists.
+   2) A PCB is only in one of the lists.
+   3) All PCBs in the tcp_listen_pcbs list is in LISTEN state.
+   4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state.
+*/
+
+/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB
+   with a PCB list or removes a PCB from a list, respectively. */
+#if 0
+#define TCP_REG(pcbs, npcb) do {\
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %d\n", npcb, npcb->local_port)); \
+                            for(tcp_tmp_pcb = *pcbs; \
+          tcp_tmp_pcb != NULL; \
+        tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+                                LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != npcb); \
+                            } \
+                            LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", npcb->state != CLOSED); \
+                            npcb->next = *pcbs; \
+                            LWIP_ASSERT("TCP_REG: npcb->next != npcb", npcb->next != npcb); \
+                            *(pcbs) = npcb; \
+                            LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
+              tcp_timer_needed(); \
+                            } while(0)
+#define TCP_RMV(pcbs, npcb) do { \
+                            LWIP_ASSERT("TCP_RMV: pcbs != NULL", *pcbs != NULL); \
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", npcb, *pcbs)); \
+                            if(*pcbs == npcb) { \
+                               *pcbs = (*pcbs)->next; \
+                            } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+                               if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \
+                                  tcp_tmp_pcb->next = npcb->next; \
+                                  break; \
+                               } \
+                            } \
+                            npcb->next = NULL; \
+                            LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", npcb, *pcbs)); \
+                            } while(0)
+
+#else /* LWIP_DEBUG */
+#define TCP_REG(pcbs, npcb) do { \
+                            npcb->next = *pcbs; \
+                            *(pcbs) = npcb; \
+              tcp_timer_needed(); \
+                            } while(0)
+#define TCP_RMV(pcbs, npcb) do { \
+                            if(*(pcbs) == npcb) { \
+                               (*(pcbs)) = (*pcbs)->next; \
+                            } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+                               if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \
+                                  tcp_tmp_pcb->next = npcb->next; \
+                                  break; \
+                               } \
+                            } \
+                            npcb->next = NULL; \
+                            } while(0)
+#endif /* LWIP_DEBUG */
+#endif /* __LWIP_TCP_H__ */
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/tcpip.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/tcpip.h
new file mode 100644
index 0000000..242664e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/tcpip.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_TCPIP_H__
+#define __LWIP_TCPIP_H__
+
+#include "lwip/api_msg.h"
+#include "lwip/pbuf.h"
+
+void tcpip_init(void (* tcpip_init_done)(void *), void *arg);
+void tcpip_apimsg(struct api_msg *apimsg);
+err_t tcpip_input(struct pbuf *p, struct netif *inp);
+err_t tcpip_callback(void (*f)(void *ctx), void *ctx);
+
+void tcpip_tcp_timer_needed(void);
+
+enum tcpip_msg_type {
+  TCPIP_MSG_API,
+  TCPIP_MSG_INPUT,
+  TCPIP_MSG_CALLBACK
+};
+
+struct tcpip_msg {
+  enum tcpip_msg_type type;
+  sys_sem_t *sem;
+  union {
+    struct api_msg *apimsg;
+    struct {
+      struct pbuf *p;
+      struct netif *netif;
+    } inp;
+    struct {
+      void (*f)(void *ctx);
+      void *ctx;
+    } cb;
+  } msg;
+};
+
+
+#endif /* __LWIP_TCPIP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/udp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/udp.h
new file mode 100644
index 0000000..adefdc9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/lwip/udp.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_UDP_H__
+#define __LWIP_UDP_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+
+#define UDP_HLEN 8
+
+struct udp_hdr {
+  PACK_STRUCT_FIELD(u16_t src);
+  PACK_STRUCT_FIELD(u16_t dest);  /* src/dest UDP ports */
+  PACK_STRUCT_FIELD(u16_t len);
+  PACK_STRUCT_FIELD(u16_t chksum);
+} PACK_STRUCT_STRUCT;
+
+#define UDP_FLAGS_NOCHKSUM 0x01U
+#define UDP_FLAGS_UDPLITE  0x02U
+#define UDP_FLAGS_CONNECTED  0x04U
+
+struct udp_pcb {
+/* Common members of all PCB types */
+  IP_PCB;
+
+/* Protocol specific PCB members */
+
+  struct udp_pcb *next;
+
+  u8_t flags;
+  u16_t local_port, remote_port;
+  
+  u16_t chksum_len;
+  
+  void (* recv)(void *arg, struct udp_pcb *pcb, struct pbuf *p,
+    struct ip_addr *addr, u16_t port);
+  void *recv_arg;  
+};
+/* udp_pcbs export for exernal reference (e.g. SNMP agent) */
+extern struct udp_pcb *udp_pcbs;
+
+/* The following functions is the application layer interface to the
+   UDP code. */
+struct udp_pcb * udp_new        (void);
+void             udp_remove     (struct udp_pcb *pcb);
+err_t            udp_bind       (struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port);
+err_t            udp_connect    (struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port);
+void             udp_disconnect    (struct udp_pcb *pcb);
+void             udp_recv       (struct udp_pcb *pcb,
+         void (* recv)(void *arg, struct udp_pcb *upcb,
+                 struct pbuf *p,
+                 struct ip_addr *addr,
+                 u16_t port),
+         void *recv_arg);
+err_t            udp_sendto     (struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *dst_ip, u16_t dst_port);
+err_t            udp_send       (struct udp_pcb *pcb, struct pbuf *p);
+
+#define          udp_flags(pcb)  ((pcb)->flags)
+#define          udp_setflags(pcb, f)  ((pcb)->flags = (f))
+
+/* The following functions are the lower layer interface to UDP. */
+void             udp_input      (struct pbuf *p, struct netif *inp);
+void             udp_init       (void);
+
+#if UDP_DEBUG
+void udp_debug_print(struct udp_hdr *udphdr);
+#else
+#define udp_debug_print(udphdr)
+#endif
+#endif /* __LWIP_UDP_H__ */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/netif/etharp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/netif/etharp.h
new file mode 100644
index 0000000..cc0a35f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/netif/etharp.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (c) 2003-2004 Leon Woestenberg 
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef __NETIF_ETHARP_H__
+#define __NETIF_ETHARP_H__
+
+#ifndef ETH_PAD_SIZE
+#define ETH_PAD_SIZE 0
+#endif
+
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/ip.h"
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct eth_addr {
+  PACK_STRUCT_FIELD(u8_t addr[6]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct eth_hdr {
+#if ETH_PAD_SIZE
+  PACK_STRUCT_FIELD(u8_t padding[ETH_PAD_SIZE]);
+#endif
+  PACK_STRUCT_FIELD(struct eth_addr dest);
+  PACK_STRUCT_FIELD(struct eth_addr src);
+  PACK_STRUCT_FIELD(u16_t type);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** the ARP message */
+struct etharp_hdr {
+  PACK_STRUCT_FIELD(struct eth_hdr ethhdr);
+  PACK_STRUCT_FIELD(u16_t hwtype);
+  PACK_STRUCT_FIELD(u16_t proto);
+  PACK_STRUCT_FIELD(u16_t _hwlen_protolen);
+  PACK_STRUCT_FIELD(u16_t opcode);
+  PACK_STRUCT_FIELD(struct eth_addr shwaddr);
+  PACK_STRUCT_FIELD(struct ip_addr2 sipaddr);
+  PACK_STRUCT_FIELD(struct eth_addr dhwaddr);
+  PACK_STRUCT_FIELD(struct ip_addr2 dipaddr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ethip_hdr {
+  PACK_STRUCT_FIELD(struct eth_hdr eth);
+  PACK_STRUCT_FIELD(struct ip_hdr ip);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** 5 seconds period */
+#define ARP_TMR_INTERVAL 5000
+
+#define ETHTYPE_ARP 0x0806
+#define ETHTYPE_IP  0x0800
+
+
+void etharp_init(void);
+void etharp_tmr(void);
+s8_t etharp_find_addr(struct netif *netif, struct ip_addr *ipaddr,
+         struct eth_addr **eth_ret, struct ip_addr **ip_ret);
+void etharp_ip_input(struct netif *netif, struct pbuf *p);
+void etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr,
+         struct pbuf *p);
+err_t etharp_output(struct netif *netif, struct ip_addr *ipaddr,
+         struct pbuf *q);
+err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q);
+err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr);
+
+#endif /* __NETIF_ARP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/netif/loopif.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/netif/loopif.h
new file mode 100644
index 0000000..7fd5487
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/netif/loopif.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __NETIF_LOOPIF_H__
+#define __NETIF_LOOPIF_H__
+
+#include "lwip/netif.h"
+
+err_t loopif_init(struct netif *netif);
+
+#endif /* __NETIF_LOOPIF_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/netif/slipif.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/netif/slipif.h
new file mode 100644
index 0000000..d9060fc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/include/netif/slipif.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __NETIF_SLIPIF_H__
+#define __NETIF_SLIPIF_H__
+
+#include "lwip/netif.h"
+
+err_t slipif_init(struct netif * netif);
+ 
+#endif 
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/FILES b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/FILES
new file mode 100644
index 0000000..825d407
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/FILES
@@ -0,0 +1,27 @@
+This directory contains generic network interface device drivers that
+do not contain any hardware or architecture specific code. The files
+are:
+
+etharp.c
+          Implements the ARP (Address Resolution Protocol) over
+          Ethernet. The code in this file should be used together with
+          Ethernet device drivers. Note that this module has been
+          largely made Ethernet independent so you should be able to
+          adapt this for other link layers (such as Firewire).
+
+ethernetif.c
+          An example of how an Ethernet device driver could look. This
+          file can be used as a "skeleton" for developing new Ethernet
+          network device drivers. It uses the etharp.c ARP code.
+
+loopif.c
+          An example network interface that shows how a "loopback"
+          interface would work. This is not really intended for actual
+          use, but as a very basic example of how initialization and
+          output functions work.
+
+slipif.c
+          A generic implementation of the SLIP (Serial Line IP)
+          protocol. It requires a sio (serial I/O) module to work.
+	  
+ppp/      Point-to-Point Protocol stack
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/etharp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/etharp.c
new file mode 100644
index 0000000..22eeb9a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/etharp.c
@@ -0,0 +1,892 @@
+/**
+ * @file
+ * Address Resolution Protocol module for IP over Ethernet
+ *
+ * Functionally, ARP is divided into two parts. The first maps an IP address
+ * to a physical address when sending a packet, and the second part answers
+ * requests from other machines for our physical address.
+ *
+ * This implementation complies with RFC 826 (Ethernet ARP). It supports
+ * Gratuitious ARP from RFC3220 (IP Mobility Support for IPv4) section 4.6
+ * if an interface calls etharp_query(our_netif, its_ip_addr, NULL) upon
+ * address change.
+ */
+
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (c) 2003-2004 Leon Woestenberg 
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+#include 
+#include "lwip/opt.h"
+#include "lwip/inet.h"
+#include "netif/etharp.h"
+#include "lwip/ip.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+
+/* ARP needs to inform DHCP of any ARP replies? */
+#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK)
+#  include "lwip/dhcp.h"
+#endif
+
+/** the time an ARP entry stays valid after its last update,
+ * (240 * 5) seconds = 20 minutes.
+ */
+#define ARP_MAXAGE 240
+/** the time an ARP entry stays pending after first request,
+ * (2 * 5) seconds = 10 seconds.
+ * 
+ * @internal Keep this number at least 2, otherwise it might
+ * run out instantly if the timeout occurs directly after a request.
+ */
+#define ARP_MAXPENDING 2
+
+#define HWTYPE_ETHERNET 1
+
+/** ARP message types */
+#define ARP_REQUEST 1
+#define ARP_REPLY 2
+
+#define ARPH_HWLEN(hdr) (ntohs((hdr)->_hwlen_protolen) >> 8)
+#define ARPH_PROTOLEN(hdr) (ntohs((hdr)->_hwlen_protolen) & 0xff)
+
+#define ARPH_HWLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons(ARPH_PROTOLEN(hdr) | ((len) << 8))
+#define ARPH_PROTOLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons((len) | (ARPH_HWLEN(hdr) << 8))
+
+enum etharp_state {
+  ETHARP_STATE_EMPTY,
+  ETHARP_STATE_PENDING,
+  ETHARP_STATE_STABLE,
+  /** @internal transitional state used in etharp_tmr() for convenience*/
+  ETHARP_STATE_EXPIRED
+};
+
+struct etharp_entry {
+#if ARP_QUEUEING
+  /** 
+   * Pointer to queue of pending outgoing packets on this ARP entry.
+   */
+   struct pbuf *p;
+#endif
+  struct ip_addr ipaddr;
+  struct eth_addr ethaddr;
+  enum etharp_state state;
+  u8_t ctime;
+  struct netif *netif;
+};
+
+static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}};
+static struct etharp_entry arp_table[ARP_TABLE_SIZE];
+
+/**
+ * Try hard to create a new entry - we want the IP address to appear in
+ * the cache (even if this means removing an active entry or so). */
+#define ETHARP_TRY_HARD 1
+
+static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags);
+static err_t update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags);
+/**
+ * Initializes ARP module.
+ */
+void
+etharp_init(void)
+{
+  u8_t i;
+  /* clear ARP entries */
+  for(i = 0; i < ARP_TABLE_SIZE; ++i) {
+    arp_table[i].state = ETHARP_STATE_EMPTY;
+#if ARP_QUEUEING
+    arp_table[i].p = NULL;
+#endif
+    arp_table[i].ctime = 0;
+    arp_table[i].netif = NULL;
+  }
+}
+
+/**
+ * Clears expired entries in the ARP table.
+ *
+ * This function should be called every ETHARP_TMR_INTERVAL microseconds (5 seconds),
+ * in order to expire entries in the ARP table.
+ */
+void
+etharp_tmr(void)
+{
+  u8_t i;
+
+  LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n"));
+  /* remove expired entries from the ARP table */
+  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
+    arp_table[i].ctime++;
+    /* stable entry? */
+    if ((arp_table[i].state == ETHARP_STATE_STABLE) &&
+         /* entry has become old? */
+        (arp_table[i].ctime >= ARP_MAXAGE)) {
+      LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired stable entry %"U16_F".\n", (u16_t)i));
+      arp_table[i].state = ETHARP_STATE_EXPIRED;
+    /* pending entry? */
+    } else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+      /* entry unresolved/pending for too long? */
+      if (arp_table[i].ctime >= ARP_MAXPENDING) {
+        LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired pending entry %"U16_F".\n", (u16_t)i));
+        arp_table[i].state = ETHARP_STATE_EXPIRED;
+#if ARP_QUEUEING
+      } else if (arp_table[i].p != NULL) {
+        /* resend an ARP query here */
+#endif
+      }
+    }
+    /* clean up entries that have just been expired */
+    if (arp_table[i].state == ETHARP_STATE_EXPIRED) {
+      /* remove from SNMP ARP index tree */
+      snmp_delete_arpidx_tree(arp_table[i].netif, &arp_table[i].ipaddr);
+#if ARP_QUEUEING
+      /* and empty packet queue */
+      if (arp_table[i].p != NULL) {
+        /* remove all queued packets */
+        LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].p)));
+        pbuf_free(arp_table[i].p);
+        arp_table[i].p = NULL;
+      }
+#endif
+      /* recycle entry for re-use */      
+      arp_table[i].state = ETHARP_STATE_EMPTY;
+    }
+  }
+}
+
+/**
+ * Search the ARP table for a matching or new entry.
+ * 
+ * If an IP address is given, return a pending or stable ARP entry that matches
+ * the address. If no match is found, create a new entry with this address set,
+ * but in state ETHARP_EMPTY. The caller must check and possibly change the
+ * state of the returned entry.
+ * 
+ * If ipaddr is NULL, return a initialized new entry in state ETHARP_EMPTY.
+ * 
+ * In all cases, attempt to create new entries from an empty entry. If no
+ * empty entries are available and ETHARP_TRY_HARD flag is set, recycle
+ * old entries. Heuristic choose the least important entry for recycling.
+ *
+ * @param ipaddr IP address to find in ARP cache, or to add if not found.
+ * @param flags
+ * - ETHARP_TRY_HARD: Try hard to create a entry by allowing recycling of
+ * active (stable or pending) entries.
+ *  
+ * @return The ARP entry index that matched or is created, ERR_MEM if no
+ * entry is found or could be recycled.
+ */
+static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags)
+{
+  s8_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE;
+  s8_t empty = ARP_TABLE_SIZE;
+  u8_t i = 0, age_pending = 0, age_stable = 0;
+#if ARP_QUEUEING
+  /* oldest entry with packets on queue */
+  s8_t old_queue = ARP_TABLE_SIZE;
+  /* its age */
+  u8_t age_queue = 0;
+#endif
+
+  /**
+   * a) do a search through the cache, remember candidates
+   * b) select candidate entry
+   * c) create new entry
+   */
+
+  /* a) in a single search sweep, do all of this
+   * 1) remember the first empty entry (if any)
+   * 2) remember the oldest stable entry (if any)
+   * 3) remember the oldest pending entry without queued packets (if any)
+   * 4) remember the oldest pending entry with queued packets (if any)
+   * 5) search for a matching IP entry, either pending or stable
+   *    until 5 matches, or all entries are searched for.
+   */
+
+  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
+    /* no empty entry found yet and now we do find one? */
+    if ((empty == ARP_TABLE_SIZE) && (arp_table[i].state == ETHARP_STATE_EMPTY)) {
+      LWIP_DEBUGF(ETHARP_DEBUG, ("find_entry: found empty entry %"U16_F"\n", (u16_t)i));
+      /* remember first empty entry */
+      empty = i;
+    }
+    /* pending entry? */
+    else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+      /* if given, does IP address match IP address in ARP entry? */
+      if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {
+        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching pending entry %"U16_F"\n", (u16_t)i));
+        /* found exact IP address match, simply bail out */
+        return i;
+#if ARP_QUEUEING
+      /* pending with queued packets? */
+      } else if (arp_table[i].p != NULL) {
+        if (arp_table[i].ctime >= age_queue) {
+          old_queue = i;
+          age_queue = arp_table[i].ctime;
+        }
+#endif
+      /* pending without queued packets? */
+      } else {
+        if (arp_table[i].ctime >= age_pending) {
+          old_pending = i;
+          age_pending = arp_table[i].ctime;
+        }
+      }        
+    }
+    /* stable entry? */
+    else if (arp_table[i].state == ETHARP_STATE_STABLE) {
+      /* if given, does IP address match IP address in ARP entry? */
+      if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {
+        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching stable entry %"U16_F"\n", (u16_t)i));
+        /* found exact IP address match, simply bail out */
+        return i;
+      /* remember entry with oldest stable entry in oldest, its age in maxtime */
+      } else if (arp_table[i].ctime >= age_stable) {
+        old_stable = i;
+        age_stable = arp_table[i].ctime;
+      }
+    }
+  }
+  /* { we have no match } => try to create a new entry */
+   
+  /* no empty entry found and not allowed to recycle? */
+  if ((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_TRY_HARD) == 0))
+  {
+    return (s8_t)ERR_MEM;
+  }
+  
+  /* b) choose the least destructive entry to recycle:
+   * 1) empty entry
+   * 2) oldest stable entry
+   * 3) oldest pending entry without queued packets
+   * 4) oldest pending entry without queued packets
+   * 
+   * { ETHARP_TRY_HARD is set at this point }
+   */ 
+
+  /* 1) empty entry available? */
+  if (empty < ARP_TABLE_SIZE) {
+    i = empty;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting empty entry %"U16_F"\n", (u16_t)i));
+  }
+  /* 2) found recyclable stable entry? */
+  else if (old_stable < ARP_TABLE_SIZE) {
+    /* recycle oldest stable*/
+    i = old_stable;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest stable entry %"U16_F"\n", (u16_t)i));
+#if ARP_QUEUEING
+    /* no queued packets should exist on stable entries */
+    LWIP_ASSERT("arp_table[i].p == NULL", arp_table[i].p == NULL);
+#endif
+  /* 3) found recyclable pending entry without queued packets? */
+  } else if (old_pending < ARP_TABLE_SIZE) {
+    /* recycle oldest pending */
+    i = old_pending;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F" (without queue)\n", (u16_t)i));
+#if ARP_QUEUEING
+  /* 4) found recyclable pending entry with queued packets? */
+  } else if (old_queue < ARP_TABLE_SIZE) {
+    /* recycle oldest pending */
+    i = old_queue;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F", freeing packet queue %p\n", (u16_t)i, (void *)(arp_table[i].p)));
+    pbuf_free(arp_table[i].p);
+    arp_table[i].p = NULL;
+#endif
+    /* no empty or recyclable entries found */
+  } else {
+    return (s8_t)ERR_MEM;
+  }
+
+  /* { empty or recyclable entry found } */
+  LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
+
+  if (arp_table[i].state != ETHARP_STATE_EMPTY)
+  {
+    snmp_delete_arpidx_tree(arp_table[i].netif, &arp_table[i].ipaddr);
+  }
+  /* recycle entry (no-op for an already empty entry) */
+  arp_table[i].state = ETHARP_STATE_EMPTY;
+
+  /* IP address given? */
+  if (ipaddr != NULL) {
+    /* set IP address */
+    ip_addr_set(&arp_table[i].ipaddr, ipaddr);
+  }
+  arp_table[i].ctime = 0;
+  return (err_t)i;
+}
+
+/**
+ * Update (or insert) a IP/MAC address pair in the ARP cache.
+ *
+ * If a pending entry is resolved, any queued packets will be sent
+ * at this point.
+ * 
+ * @param ipaddr IP address of the inserted ARP entry.
+ * @param ethaddr Ethernet address of the inserted ARP entry.
+ * @param flags Defines behaviour:
+ * - ETHARP_TRY_HARD Allows ARP to insert this as a new item. If not specified,
+ * only existing ARP entries will be updated.
+ *
+ * @return
+ * - ERR_OK Succesfully updated ARP cache.
+ * - ERR_MEM If we could not add a new ARP entry when ETHARP_TRY_HARD was set.
+ * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
+ *
+ * @see pbuf_free()
+ */
+static err_t
+update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags)
+{
+  s8_t i;
+  u8_t k;
+  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 3, ("update_arp_entry()\n"));
+  LWIP_ASSERT("netif->hwaddr_len != 0", netif->hwaddr_len != 0);
+  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n",
+                                        ip4_addr1(ipaddr), ip4_addr2(ipaddr), ip4_addr3(ipaddr), ip4_addr4(ipaddr), 
+                                        ethaddr->addr[0], ethaddr->addr[1], ethaddr->addr[2],
+                                        ethaddr->addr[3], ethaddr->addr[4], ethaddr->addr[5]));
+  /* non-unicast address? */
+  if (ip_addr_isany(ipaddr) ||
+      ip_addr_isbroadcast(ipaddr, netif) ||
+      ip_addr_ismulticast(ipaddr)) {
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: will not add non-unicast IP address to ARP cache\n"));
+    return ERR_ARG;
+  }
+  /* find or create ARP entry */
+  i = find_entry(ipaddr, flags);
+  /* bail out if no entry could be found */
+  if (i < 0) return (err_t)i;
+  
+  /* mark it stable */
+  arp_table[i].state = ETHARP_STATE_STABLE;
+  /* record network interface */
+  arp_table[i].netif = netif;
+
+  /* insert in SNMP ARP index tree */
+  snmp_insert_arpidx_tree(netif, &arp_table[i].ipaddr);
+
+  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: updating stable entry %"S16_F"\n", (s16_t)i));
+  /* update address */
+  k = netif->hwaddr_len;
+  while (k > 0) {
+    k--;
+    arp_table[i].ethaddr.addr[k] = ethaddr->addr[k];
+  }
+  /* reset time stamp */
+  arp_table[i].ctime = 0;
+/* this is where we will send out queued packets! */
+#if ARP_QUEUEING
+  while (arp_table[i].p != NULL) {
+    /* get the first packet on the queue */
+    struct pbuf *p = arp_table[i].p;
+    /* Ethernet header */
+    struct eth_hdr *ethhdr = p->payload;
+    /* remember (and reference) remainder of queue */
+    /* note: this will also terminate the p pbuf chain */
+    arp_table[i].p = pbuf_dequeue(p);
+    /* fill-in Ethernet header */
+    k = netif->hwaddr_len;
+    while(k > 0) {
+      k--;
+      ethhdr->dest.addr[k] = ethaddr->addr[k];
+      ethhdr->src.addr[k] = netif->hwaddr[k];
+    }
+    ethhdr->type = htons(ETHTYPE_IP);
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: sending queued IP packet %p.\n", (void *)p));
+    /* send the queued IP packet */
+    netif->linkoutput(netif, p);
+    /* free the queued IP packet */
+    pbuf_free(p);
+  }
+#endif
+  return ERR_OK;
+}
+
+/**
+ * Finds (stable) ethernet/IP address pair from ARP table
+ * using interface and IP address index.
+ * @note the addresses in the ARP table are in network order!
+ *
+ * @param netif points to interface index
+ * @param ipaddr points to the (network order) IP address index
+ * @param eth_ret points to return pointer
+ * @param ip_ret points to return pointer
+ * @return table index if found, -1 otherwise
+ */
+s8_t
+etharp_find_addr(struct netif *netif, struct ip_addr *ipaddr,
+         struct eth_addr **eth_ret, struct ip_addr **ip_ret)
+{
+  s8_t i;
+
+  i = 0;
+  while (i < ARP_TABLE_SIZE)
+  {
+    if ((arp_table[i].state == ETHARP_STATE_STABLE) &&
+        (arp_table[i].netif == netif) && 
+        ip_addr_cmp(ipaddr, &arp_table[i].ipaddr) )
+    {
+      *eth_ret = &arp_table[i].ethaddr;
+      *ip_ret = &arp_table[i].ipaddr;
+      return i;
+    }
+    i++;
+  }
+  return -1;
+}
+
+/**
+ * Updates the ARP table using the given IP packet.
+ *
+ * Uses the incoming IP packet's source address to update the
+ * ARP cache for the local network. The function does not alter
+ * or free the packet. This function must be called before the
+ * packet p is passed to the IP layer.
+ *
+ * @param netif The lwIP network interface on which the IP packet pbuf arrived.
+ * @param pbuf The IP packet that arrived on netif.
+ *
+ * @return NULL
+ *
+ * @see pbuf_free()
+ */
+void
+etharp_ip_input(struct netif *netif, struct pbuf *p)
+{
+  struct ethip_hdr *hdr;
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+  /* Only insert an entry if the source IP address of the
+     incoming IP packet comes from a host on the local network. */
+  hdr = p->payload;
+  /* source is not on the local network? */
+  if (!ip_addr_netcmp(&(hdr->ip.src), &(netif->ip_addr), &(netif->netmask))) {
+    /* do nothing */
+    return;
+  }
+
+  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_ip_input: updating ETHARP table.\n"));
+  /* update ARP table */
+  /* @todo We could use ETHARP_TRY_HARD if we think we are going to talk
+   * back soon (for example, if the destination IP address is ours. */
+  update_arp_entry(netif, &(hdr->ip.src), &(hdr->eth.src), 0);
+}
+
+
+/**
+ * Responds to ARP requests to us. Upon ARP replies to us, add entry to cache  
+ * send out queued IP packets. Updates cache with snooped address pairs.
+ *
+ * Should be called for incoming ARP packets. The pbuf in the argument
+ * is freed by this function.
+ *
+ * @param netif The lwIP network interface on which the ARP packet pbuf arrived.
+ * @param pbuf The ARP packet that arrived on netif. Is freed by this function.
+ * @param ethaddr Ethernet address of netif.
+ *
+ * @return NULL
+ *
+ * @see pbuf_free()
+ */
+void
+etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, struct pbuf *p)
+{
+  struct etharp_hdr *hdr;
+  /* these are aligned properly, whereas the ARP header fields might not be */
+  struct ip_addr sipaddr, dipaddr;
+  u8_t i;
+  u8_t for_us;
+
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+  
+  /* drop short ARP packets */
+  if (p->tot_len < sizeof(struct etharp_hdr)) {
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 1, ("etharp_arp_input: packet dropped, too short (%"S16_F"/%"S16_F")\n", p->tot_len, (s16_t)sizeof(struct etharp_hdr)));
+    pbuf_free(p);
+    return;
+  }
+
+  hdr = p->payload;
+ 
+  /* Copy struct ip_addr2 to aligned ip_addr, to support compilers without
+   * structure packing (not using structure copy which breaks strict-aliasing rules). */
+  memcpy(&sipaddr, &hdr->sipaddr, sizeof(sipaddr));
+  memcpy(&dipaddr, &hdr->dipaddr, sizeof(dipaddr));
+
+  /* this interface is not configured? */
+  if (netif->ip_addr.addr == 0) {
+    for_us = 0;
+  } else {
+    /* ARP packet directed to us? */
+    for_us = ip_addr_cmp(&dipaddr, &(netif->ip_addr));
+  }
+
+  /* ARP message directed to us? */
+  if (for_us) {
+    /* add IP address in ARP cache; assume requester wants to talk to us.
+     * can result in directly sending the queued packets for this host. */
+    update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), ETHARP_TRY_HARD);
+  /* ARP message not directed to us? */
+  } else {
+    /* update the source IP address in the cache, if present */
+    update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), 0);
+  }
+
+  /* now act on the message itself */
+  switch (htons(hdr->opcode)) {
+  /* ARP request? */
+  case ARP_REQUEST:
+    /* ARP request. If it asked for our address, we send out a
+     * reply. In any case, we time-stamp any existing ARP entry,
+     * and possiby send out an IP packet that was queued on it. */
+
+    LWIP_DEBUGF (ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: incoming ARP request\n"));
+    /* ARP request for our address? */
+    if (for_us) {
+
+      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: replying to ARP request for our IP address\n"));
+      /* re-use pbuf to send ARP reply */
+      hdr->opcode = htons(ARP_REPLY);
+
+      hdr->dipaddr = hdr->sipaddr;
+      hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr;
+
+      i = netif->hwaddr_len;
+      while(i > 0) {
+        i--;
+        hdr->dhwaddr.addr[i] = hdr->shwaddr.addr[i];
+        hdr->shwaddr.addr[i] = ethaddr->addr[i];
+        hdr->ethhdr.dest.addr[i] = hdr->dhwaddr.addr[i];
+        hdr->ethhdr.src.addr[i] = ethaddr->addr[i];
+      }
+
+      hdr->hwtype = htons(HWTYPE_ETHERNET);
+      ARPH_HWLEN_SET(hdr, netif->hwaddr_len);
+
+      hdr->proto = htons(ETHTYPE_IP);
+      ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr));
+
+      hdr->ethhdr.type = htons(ETHTYPE_ARP);
+      /* return ARP reply */
+      netif->linkoutput(netif, p);
+    /* we are not configured? */
+    } else if (netif->ip_addr.addr == 0) {
+      /* { for_us == 0 and netif->ip_addr.addr == 0 } */
+      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: we are unconfigured, ARP request ignored.\n"));
+    /* request was not directed to us */
+    } else {
+      /* { for_us == 0 and netif->ip_addr.addr != 0 } */
+      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP request was not for us.\n"));
+    }
+    break;
+  case ARP_REPLY:
+    /* ARP reply. We already updated the ARP cache earlier. */
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: incoming ARP reply\n"));
+#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK)
+    /* DHCP wants to know about ARP replies from any host with an
+     * IP address also offered to us by the DHCP server. We do not
+     * want to take a duplicate IP address on a single network.
+     * @todo How should we handle redundant (fail-over) interfaces?
+     * */
+    dhcp_arp_reply(netif, &sipaddr);
+#endif
+    break;
+  default:
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP unknown opcode type %"S16_F"\n", htons(hdr->opcode)));
+    break;
+  }
+  /* free ARP packet */
+  pbuf_free(p);
+}
+
+/**
+ * Resolve and fill-in Ethernet address header for outgoing packet.
+ *
+ * For IP multicast and broadcast, corresponding Ethernet addresses
+ * are selected and the packet is transmitted on the link.
+ *
+ * For unicast addresses, the packet is submitted to etharp_query(). In
+ * case the IP address is outside the local network, the IP address of
+ * the gateway is used.
+ *
+ * @param netif The lwIP network interface which the IP packet will be sent on.
+ * @param ipaddr The IP address of the packet destination.
+ * @param pbuf The pbuf(s) containing the IP packet to be sent.
+ *
+ * @return
+ * - ERR_RTE No route to destination (no gateway to external networks),
+ * or the return type of either etharp_query() or netif->linkoutput().
+ */
+err_t
+etharp_output(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q)
+{
+  struct eth_addr *dest, *srcaddr, mcastaddr;
+  struct eth_hdr *ethhdr;
+  u8_t i;
+
+  /* make room for Ethernet header - should not fail */
+  if (pbuf_header(q, sizeof(struct eth_hdr)) != 0) {
+    /* bail out */
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_output: could not allocate room for header.\n"));
+    LINK_STATS_INC(link.lenerr);
+    return ERR_BUF;
+  }
+
+  /* assume unresolved Ethernet address */
+  dest = NULL;
+  /* Determine on destination hardware address. Broadcasts and multicasts
+   * are special, other IP addresses are looked up in the ARP table. */
+
+  /* broadcast destination IP address? */
+  if (ip_addr_isbroadcast(ipaddr, netif)) {
+    /* broadcast on Ethernet also */
+    dest = (struct eth_addr *)ðbroadcast;
+  /* multicast destination IP address? */
+  } else if (ip_addr_ismulticast(ipaddr)) {
+    /* Hash IP multicast address to MAC address.*/
+    mcastaddr.addr[0] = 0x01;
+    mcastaddr.addr[1] = 0x00;
+    mcastaddr.addr[2] = 0x5e;
+    mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f;
+    mcastaddr.addr[4] = ip4_addr3(ipaddr);
+    mcastaddr.addr[5] = ip4_addr4(ipaddr);
+    /* destination Ethernet address is multicast */
+    dest = &mcastaddr;
+  /* unicast destination IP address? */
+  } else {
+    /* outside local network? */
+    if (!ip_addr_netcmp(ipaddr, &(netif->ip_addr), &(netif->netmask))) {
+      /* interface has default gateway? */
+      if (netif->gw.addr != 0) {
+        /* send to hardware address of default gateway IP address */
+        ipaddr = &(netif->gw);
+      /* no default gateway available */
+      } else {
+        /* no route to destination error (default gateway missing) */
+        return ERR_RTE;
+      }
+    }
+    /* queue on destination Ethernet address belonging to ipaddr */
+    return etharp_query(netif, ipaddr, q);
+  }
+
+  /* continuation for multicast/broadcast destinations */
+  /* obtain source Ethernet address of the given interface */
+  srcaddr = (struct eth_addr *)netif->hwaddr;
+  ethhdr = q->payload;
+  i = netif->hwaddr_len;
+  while(i > 0) {
+    i--;
+    ethhdr->dest.addr[i] = dest->addr[i];
+    ethhdr->src.addr[i] = srcaddr->addr[i];
+  }
+  ethhdr->type = htons(ETHTYPE_IP);
+  /* send packet directly on the link */
+  return netif->linkoutput(netif, q);
+}
+
+/**
+ * Send an ARP request for the given IP address and/or queue a packet.
+ *
+ * If the IP address was not yet in the cache, a pending ARP cache entry
+ * is added and an ARP request is sent for the given address. The packet
+ * is queued on this entry.
+ *
+ * If the IP address was already pending in the cache, a new ARP request
+ * is sent for the given address. The packet is queued on this entry.
+ *
+ * If the IP address was already stable in the cache, and a packet is
+ * given, it is directly sent and no ARP request is sent out. 
+ * 
+ * If the IP address was already stable in the cache, and no packet is
+ * given, an ARP request is sent out.
+ * 
+ * @param netif The lwIP network interface on which ipaddr
+ * must be queried for.
+ * @param ipaddr The IP address to be resolved.
+ * @param q If non-NULL, a pbuf that must be delivered to the IP address.
+ * q is not freed by this function.
+ *
+ * @return
+ * - ERR_BUF Could not make room for Ethernet header.
+ * - ERR_MEM Hardware address unknown, and no more ARP entries available
+ *   to query for address or queue the packet.
+ * - ERR_MEM Could not queue packet due to memory shortage.
+ * - ERR_RTE No route to destination (no gateway to external networks).
+ * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
+ *
+ */
+err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q)
+{
+  struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr;
+  err_t result = ERR_MEM;
+  s8_t i; /* ARP entry index */
+  u8_t k; /* Ethernet address octet index */
+
+  /* non-unicast address? */
+  if (ip_addr_isbroadcast(ipaddr, netif) ||
+      ip_addr_ismulticast(ipaddr) ||
+      ip_addr_isany(ipaddr)) {
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n"));
+    return ERR_ARG;
+  }
+
+  /* find entry in ARP cache, ask to create entry if queueing packet */
+  i = find_entry(ipaddr, ETHARP_TRY_HARD);
+
+  /* could not find or create entry? */
+  if (i < 0)
+  {
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not create ARP entry\n"));
+    if (q) LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: packet dropped\n"));
+    return (err_t)i;
+  }
+
+  /* mark a fresh entry as pending (we just sent a request) */
+  if (arp_table[i].state == ETHARP_STATE_EMPTY) {
+    arp_table[i].state = ETHARP_STATE_PENDING;
+  }
+
+  /* { i is either a STABLE or (new or existing) PENDING entry } */
+  LWIP_ASSERT("arp_table[i].state == PENDING or STABLE",
+  ((arp_table[i].state == ETHARP_STATE_PENDING) ||
+   (arp_table[i].state == ETHARP_STATE_STABLE)));
+
+  /* do we have a pending entry? or an implicit query request? */
+  if ((arp_table[i].state == ETHARP_STATE_PENDING) || (q == NULL)) {
+    /* try to resolve it; send out ARP request */
+    result = etharp_request(netif, ipaddr);
+  }
+  
+  /* packet given? */
+  if (q != NULL) {
+    /* stable entry? */
+    if (arp_table[i].state == ETHARP_STATE_STABLE) {
+      /* we have a valid IP->Ethernet address mapping,
+       * fill in the Ethernet header for the outgoing packet */
+      struct eth_hdr *ethhdr = q->payload;
+      k = netif->hwaddr_len;
+      while(k > 0) {
+        k--;
+        ethhdr->dest.addr[k] = arp_table[i].ethaddr.addr[k];
+        ethhdr->src.addr[k]  = srcaddr->addr[k];
+      }
+      ethhdr->type = htons(ETHTYPE_IP);
+      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: sending packet %p\n", (void *)q));
+      /* send the packet */
+      result = netif->linkoutput(netif, q);
+    /* pending entry? (either just created or already pending */
+    } else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+#if ARP_QUEUEING /* queue the given q packet */
+      struct pbuf *p;
+      /* copy any PBUF_REF referenced payloads into PBUF_RAM */
+      /* (the caller of lwIP assumes the referenced payload can be
+       * freed after it returns from the lwIP call that brought us here) */
+      p = pbuf_take(q);
+      /* packet could be taken over? */
+      if (p != NULL) {
+        /* queue packet ... */
+        if (arp_table[i].p == NULL) {
+          /* ... in the empty queue */
+          pbuf_ref(p);
+          arp_table[i].p = p;
+#if 0 /* multi-packet-queueing disabled, see bug #11400 */
+        } else {
+          /* ... at tail of non-empty queue */
+          pbuf_queue(arp_table[i].p, p);
+#endif
+        }
+        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"S16_F"\n", (void *)q, (s16_t)i));
+        result = ERR_OK;
+      } else {
+        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
+        /* { result == ERR_MEM } through initialization */
+      }
+#else /* ARP_QUEUEING == 0 */
+      /* q && state == PENDING && ARP_QUEUEING == 0 => result = ERR_MEM */
+      /* { result == ERR_MEM } through initialization */
+      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: Ethernet destination address unknown, queueing disabled, packet %p dropped\n", (void *)q));
+#endif
+    }
+  }
+  return result;
+}
+
+err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr)
+{
+  struct pbuf *p;
+  struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr;
+  err_t result = ERR_OK;
+  u8_t k; /* ARP entry index */
+
+  /* allocate a pbuf for the outgoing ARP request packet */
+  p = pbuf_alloc(PBUF_LINK, sizeof(struct etharp_hdr), PBUF_RAM);
+  /* could allocate a pbuf for an ARP request? */
+  if (p != NULL) {
+    struct etharp_hdr *hdr = p->payload;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_request: sending ARP request.\n"));
+    hdr->opcode = htons(ARP_REQUEST);
+    k = netif->hwaddr_len;
+    while(k > 0) {
+      k--;
+      hdr->shwaddr.addr[k] = srcaddr->addr[k];
+      /* the hardware address is what we ask for, in
+       * a request it is a don't-care value, we use zeroes */
+      hdr->dhwaddr.addr[k] = 0x00;
+    }
+    hdr->dipaddr = *(struct ip_addr2 *)ipaddr;
+    hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr;
+
+    hdr->hwtype = htons(HWTYPE_ETHERNET);
+    ARPH_HWLEN_SET(hdr, netif->hwaddr_len);
+
+    hdr->proto = htons(ETHTYPE_IP);
+    ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr));
+    k = netif->hwaddr_len;
+    while(k > 0) {
+      k--;
+      /* broadcast to all network interfaces on the local network */
+      hdr->ethhdr.dest.addr[k] = 0xff;
+      hdr->ethhdr.src.addr[k] = srcaddr->addr[k];
+    }
+    hdr->ethhdr.type = htons(ETHTYPE_ARP);
+    /* send ARP query */
+    result = netif->linkoutput(netif, p);
+    /* free ARP query packet */
+    pbuf_free(p);
+    p = NULL;
+  /* could not allocate pbuf for ARP request */
+  } else {
+    result = ERR_MEM;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_request: could not allocate pbuf for ARP request.\n"));
+  }
+  return result;
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ethernetif.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ethernetif.c
new file mode 100644
index 0000000..300775f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ethernetif.c
@@ -0,0 +1,326 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+/*
+ * This file is a skeleton for developing Ethernet network interface
+ * drivers for lwIP. Add code to the low_level functions and do a
+ * search-and-replace for the word "ethernetif" to replace it with
+ * something that better describes your network interface.
+ */
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include 
+
+#include "netif/etharp.h"
+
+/* Define those to better describe your network interface. */
+#define IFNAME0 'e'
+#define IFNAME1 'n'
+
+struct ethernetif {
+  struct eth_addr *ethaddr;
+  /* Add whatever per-interface state that is needed here. */
+};
+
+static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}};
+
+/* Forward declarations. */
+static void  ethernetif_input(struct netif *netif);
+static err_t ethernetif_output(struct netif *netif, struct pbuf *p,
+             struct ip_addr *ipaddr);
+
+static void
+low_level_init(struct netif *netif)
+{
+  struct ethernetif *ethernetif = netif->state;
+  
+  /* set MAC hardware address length */
+  netif->hwaddr_len = 6;
+
+  /* set MAC hardware address */
+  netif->hwaddr[0] = ;
+  ...
+  netif->hwaddr[5] = ;
+
+  /* maximum transfer unit */
+  netif->mtu = 1500;
+  
+  /* broadcast capability */
+  netif->flags = NETIF_FLAG_BROADCAST;
+ 
+  /* Do whatever else is needed to initialize interface. */  
+}
+
+/*
+ * low_level_output():
+ *
+ * Should do the actual transmission of the packet. The packet is
+ * contained in the pbuf that is passed to the function. This pbuf
+ * might be chained.
+ *
+ */
+
+static err_t
+low_level_output(struct netif *netif, struct pbuf *p)
+{
+  struct ethernetif *ethernetif = netif->state;
+  struct pbuf *q;
+
+  initiate transfer();
+  
+#if ETH_PAD_SIZE
+  pbuf_header(p, -ETH_PAD_SIZE);			/* drop the padding word */
+#endif
+
+  for(q = p; q != NULL; q = q->next) {
+    /* Send the data from the pbuf to the interface, one pbuf at a
+       time. The size of the data in each pbuf is kept in the ->len
+       variable. */
+    send data from(q->payload, q->len);
+  }
+
+  signal that packet should be sent();
+
+#if ETH_PAD_SIZE
+  pbuf_header(p, ETH_PAD_SIZE);			/* reclaim the padding word */
+#endif
+  
+#if LINK_STATS
+  lwip_stats.link.xmit++;
+#endif /* LINK_STATS */      
+
+  return ERR_OK;
+}
+
+/*
+ * low_level_input():
+ *
+ * Should allocate a pbuf and transfer the bytes of the incoming
+ * packet from the interface into the pbuf.
+ *
+ */
+
+static struct pbuf *
+low_level_input(struct netif *netif)
+{
+  struct ethernetif *ethernetif = netif->state;
+  struct pbuf *p, *q;
+  u16_t len;
+
+  /* Obtain the size of the packet and put it into the "len"
+     variable. */
+  len = ;
+
+#if ETH_PAD_SIZE
+  len += ETH_PAD_SIZE;						/* allow room for Ethernet padding */
+#endif
+
+  /* We allocate a pbuf chain of pbufs from the pool. */
+  p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
+  
+  if (p != NULL) {
+
+#if ETH_PAD_SIZE
+    pbuf_header(p, -ETH_PAD_SIZE);			/* drop the padding word */
+#endif
+
+    /* We iterate over the pbuf chain until we have read the entire
+     * packet into the pbuf. */
+    for(q = p; q != NULL; q = q->next) {
+      /* Read enough bytes to fill this pbuf in the chain. The
+       * available data in the pbuf is given by the q->len
+       * variable. */
+      read data into(q->payload, q->len);
+    }
+    acknowledge that packet has been read();
+
+#if ETH_PAD_SIZE
+    pbuf_header(p, ETH_PAD_SIZE);			/* reclaim the padding word */
+#endif
+
+#if LINK_STATS
+    lwip_stats.link.recv++;
+#endif /* LINK_STATS */      
+  } else {
+    drop packet();
+#if LINK_STATS
+    lwip_stats.link.memerr++;
+    lwip_stats.link.drop++;
+#endif /* LINK_STATS */      
+  }
+
+  return p;  
+}
+
+/*
+ * ethernetif_output():
+ *
+ * This function is called by the TCP/IP stack when an IP packet
+ * should be sent. It calls the function called low_level_output() to
+ * do the actual transmission of the packet.
+ *
+ */
+
+static err_t
+ethernetif_output(struct netif *netif, struct pbuf *p,
+      struct ip_addr *ipaddr)
+{
+  
+ /* resolve hardware address, then send (or queue) packet */
+  return etharp_output(netif, ipaddr, p);
+ 
+}
+
+/*
+ * ethernetif_input():
+ *
+ * This function should be called when a packet is ready to be read
+ * from the interface. It uses the function low_level_input() that
+ * should handle the actual reception of bytes from the network
+ * interface.
+ *
+ */
+
+static void
+ethernetif_input(struct netif *netif)
+{
+  struct ethernetif *ethernetif;
+  struct eth_hdr *ethhdr;
+  struct pbuf *p;
+
+  ethernetif = netif->state;
+  
+  /* move received packet into a new pbuf */
+  p = low_level_input(netif);
+  /* no packet could be read, silently ignore this */
+  if (p == NULL) return;
+  /* points to packet payload, which starts with an Ethernet header */
+  ethhdr = p->payload;
+
+#if LINK_STATS
+  lwip_stats.link.recv++;
+#endif /* LINK_STATS */
+
+  ethhdr = p->payload;
+    
+  switch (htons(ethhdr->type)) {
+  /* IP packet? */
+  case ETHTYPE_IP:
+#if 0
+/* CSi disabled ARP table update on ingress IP packets.
+   This seems to work but needs thorough testing. */
+    /* update ARP table */
+    etharp_ip_input(netif, p);
+#endif
+    /* skip Ethernet header */
+    pbuf_header(p, -sizeof(struct eth_hdr));
+    /* pass to network layer */
+    netif->input(p, netif);
+    break;
+      
+    case ETHTYPE_ARP:
+      /* pass p to ARP module  */
+      etharp_arp_input(netif, ethernetif->ethaddr, p);
+      break;
+    default:
+      pbuf_free(p);
+      p = NULL;
+      break;
+  }
+}
+
+static void
+arp_timer(void *arg)
+{
+  etharp_tmr();
+  sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL);
+}
+
+/*
+ * ethernetif_init():
+ *
+ * Should be called at the beginning of the program to set up the
+ * network interface. It calls the function low_level_init() to do the
+ * actual setup of the hardware.
+ *
+ */
+
+err_t
+ethernetif_init(struct netif *netif)
+{
+  struct ethernetif *ethernetif;
+    
+  ethernetif = mem_malloc(sizeof(struct ethernetif));
+  
+  if (ethernetif == NULL)
+  {
+  	LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n"));
+  	return ERR_MEM;
+  }
+
+#if LWIP_SNMP
+  /* ifType ethernetCsmacd(6) @see RFC1213 */
+  netif->link_type = 6;
+  /* your link speed here */
+  netif->link_speed = ;
+  netif->ts = 0;
+  netif->ifinoctets = 0;
+  netif->ifinucastpkts = 0;
+  netif->ifinnucastpkts = 0;
+  netif->ifindiscards = 0;
+  netif->ifoutoctets = 0;
+  netif->ifoutucastpkts = 0;
+  netif->ifoutnucastpkts = 0;
+  netif->ifoutdiscards = 0;
+#endif
+  
+  netif->state = ethernetif;
+  netif->name[0] = IFNAME0;
+  netif->name[1] = IFNAME1;
+  netif->output = ethernetif_output;
+  netif->linkoutput = low_level_output;
+  
+  ethernetif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]);
+  
+  low_level_init(netif);
+
+  etharp_init();
+
+  sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL);
+
+  return ERR_OK;
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/loopif.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/loopif.c
new file mode 100644
index 0000000..cd523fb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/loopif.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#include "lwip/opt.h"
+
+#if LWIP_HAVE_LOOPIF
+
+#include "netif/loopif.h"
+#include "lwip/mem.h"
+
+#if defined(LWIP_DEBUG) && defined(LWIP_TCPDUMP)
+#include "netif/tcpdump.h"
+#endif /* LWIP_DEBUG && LWIP_TCPDUMP */
+
+#include "lwip/tcp.h"
+#include "lwip/ip.h"
+
+static void
+loopif_input( void * arg )
+{
+	struct netif *netif = (struct netif *)( ((void **)arg)[ 0 ] );
+	struct pbuf *r = (struct pbuf *)( ((void **)arg)[ 1 ] );
+
+	mem_free( arg );
+	netif -> input( r, netif );
+}
+
+static err_t
+loopif_output(struct netif *netif, struct pbuf *p,
+       struct ip_addr *ipaddr)
+{
+  struct pbuf *q, *r;
+  u8_t *ptr;
+  void **arg;
+
+#if defined(LWIP_DEBUG) && defined(LWIP_TCPDUMP)
+  tcpdump(p);
+#endif /* LWIP_DEBUG && LWIP_TCPDUMP */
+  
+  r = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
+  if (r != NULL) {
+    ptr = r->payload;
+    
+    for(q = p; q != NULL; q = q->next) {
+      memcpy(ptr, q->payload, q->len);
+      ptr += q->len;
+    }
+
+    arg = mem_malloc( sizeof( void *[2]));
+	if( NULL == arg ) {
+		return ERR_MEM;
+	}
+	
+	arg[0] = netif;
+	arg[1] = r;
+	/**
+	 * workaround (patch #1779) to try to prevent bug #2595:
+	 * When connecting to "localhost" with the loopif interface,
+	 * tcp_output doesn't get the opportunity to finnish sending the
+	 * segment before tcp_process gets it, resulting in tcp_process
+	 * referencing pcb->unacked-> which still is NULL.
+	 * 
+	 * TODO: Is there still a race condition here? Leon
+	 */
+	sys_timeout( 1, loopif_input, arg );
+	
+    return ERR_OK;    
+  }
+  return ERR_MEM;
+}
+
+err_t
+loopif_init(struct netif *netif)
+{
+  netif->name[0] = 'l';
+  netif->name[1] = 'o';
+#if 0 /** TODO: I think this should be enabled, or not? Leon */
+  netif->input = loopif_input;
+#endif
+  netif->output = loopif_output;
+  return ERR_OK;
+}
+
+#endif /* LWIP_HAVE_LOOPIF */
+
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/auth.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/auth.c
new file mode 100644
index 0000000..0786a2e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/auth.c
@@ -0,0 +1,927 @@
+/*****************************************************************************
+* auth.c - Network Authentication and Phase Control program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 by Global Election Systems Inc.  All rights reserved.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-08 Guy Lancaster , Global Election Systems Inc.
+*   Ported from public pppd code.
+*****************************************************************************/
+/*
+ * auth.c - PPP authentication and phase control.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University.  The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "fsm.h"
+#include "lcp.h"
+#include "pap.h"
+#include "chap.h"
+#include "auth.h"
+#include "ipcp.h"
+
+#if CBCP_SUPPORT > 0
+#include "cbcp.h"
+#endif
+
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+/* Bits in auth_pending[] */
+#define PAP_WITHPEER    1
+#define PAP_PEER    2
+#define CHAP_WITHPEER   4
+#define CHAP_PEER   8
+
+
+                                                                    
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+/* Used for storing a sequence of words.  Usually malloced. */
+struct wordlist {
+    struct wordlist *next;
+    char        word[1];
+};
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+extern char *crypt (const char *, const char *);
+
+/* Prototypes for procedures local to this file. */
+
+static void network_phase (int);
+static void check_idle (void *);
+static void connect_time_expired (void *);
+#if 0
+static int  login (char *, char *, char **, int *);
+#endif
+static void logout (void);
+static int  null_login (int);
+static int  get_pap_passwd (int, char *, char *);
+static int  have_pap_secret (void);
+static int  have_chap_secret (char *, char *, u32_t);
+static int  ip_addr_check (u32_t, struct wordlist *);
+#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 */
+static void set_allowed_addrs(int unit, struct wordlist *addrs);
+static void free_wordlist (struct wordlist *);
+#endif
+#if CBCP_SUPPORT > 0
+static void callback_phase (int);
+#endif
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
+/* The name by which the peer authenticated itself to us. */
+static char peer_authname[MAXNAMELEN];
+#endif
+
+/* Records which authentication operations haven't completed yet. */
+static int auth_pending[NUM_PPP];
+
+/* Set if we have successfully called login() */
+static int logged_in;
+
+/* Set if we have run the /etc/ppp/auth-up script. */
+static int did_authup;
+
+/* List of addresses which the peer may use. */
+static struct wordlist *addresses[NUM_PPP];
+
+/* Number of network protocols which we have opened. */
+static int num_np_open;
+
+/* Number of network protocols which have come up. */
+static int num_np_up;
+
+#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
+/* Set if we got the contents of passwd[] from the pap-secrets file. */
+static int passwd_from_file;
+#endif
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * An Open on LCP has requested a change from Dead to Establish phase.
+ * Do what's necessary to bring the physical layer up.
+ */
+void link_required(int unit)
+{
+    AUTHDEBUG((LOG_INFO, "link_required: %d\n", unit));
+}
+
+/*
+ * LCP has terminated the link; go to the Dead phase and take the
+ * physical layer down.
+ */
+void link_terminated(int unit)
+{
+    AUTHDEBUG((LOG_INFO, "link_terminated: %d\n", unit));
+    
+    if (lcp_phase[unit] == PHASE_DEAD)
+        return;
+    if (logged_in)
+        logout();
+    lcp_phase[unit] = PHASE_DEAD;
+    AUTHDEBUG((LOG_NOTICE, "Connection terminated.\n"));
+	pppMainWakeup(unit);
+}
+
+/*
+ * LCP has gone down; it will either die or try to re-establish.
+ */
+void link_down(int unit)
+{
+    int i;
+    struct protent *protp;
+    
+    AUTHDEBUG((LOG_INFO, "link_down: %d\n", unit));
+    if (did_authup) {
+        /* XXX Do link down processing. */
+        did_authup = 0;
+    }
+    for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+        if (!protp->enabled_flag)
+            continue;
+        if (protp->protocol != PPP_LCP && protp->lowerdown != NULL)
+            (*protp->lowerdown)(unit);
+        if (protp->protocol < 0xC000 && protp->close != NULL)
+            (*protp->close)(unit, "LCP down");
+    }
+    num_np_open = 0;
+    num_np_up = 0;
+    if (lcp_phase[unit] != PHASE_DEAD)
+        lcp_phase[unit] = PHASE_TERMINATE;
+	pppMainWakeup(unit);
+}
+
+/*
+ * The link is established.
+ * Proceed to the Dead, Authenticate or Network phase as appropriate.
+ */
+void link_established(int unit)
+{
+    int auth;
+    int i;
+    struct protent *protp;
+    lcp_options *wo = &lcp_wantoptions[unit];
+    lcp_options *go = &lcp_gotoptions[unit];
+#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
+    lcp_options *ho = &lcp_hisoptions[unit];
+#endif
+    
+    AUTHDEBUG((LOG_INFO, "link_established: %d\n", unit));
+    /*
+     * Tell higher-level protocols that LCP is up.
+     */
+    for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i)
+        if (protp->protocol != PPP_LCP && protp->enabled_flag
+                && protp->lowerup != NULL)
+            (*protp->lowerup)(unit);
+    
+    if (ppp_settings.auth_required && !(go->neg_chap || go->neg_upap)) {
+        /*
+         * We wanted the peer to authenticate itself, and it refused:
+         * treat it as though it authenticated with PAP using a username
+         * of "" and a password of "".  If that's not OK, boot it out.
+         */
+        if (!wo->neg_upap || !null_login(unit)) {
+            AUTHDEBUG((LOG_WARNING, "peer refused to authenticate\n"));
+            lcp_close(unit, "peer refused to authenticate");
+            return;
+        }
+    }
+    
+    lcp_phase[unit] = PHASE_AUTHENTICATE;
+    auth = 0;
+#if CHAP_SUPPORT > 0
+    if (go->neg_chap) {
+        ChapAuthPeer(unit, ppp_settings.our_name, go->chap_mdtype);
+        auth |= CHAP_PEER;
+    } 
+#endif
+#if PAP_SUPPORT > 0 && CHAP_SUPPORT > 0
+    else
+#endif
+#if PAP_SUPPORT > 0
+    if (go->neg_upap) {
+        upap_authpeer(unit);
+        auth |= PAP_PEER;
+    }
+#endif
+#if CHAP_SUPPORT > 0
+    if (ho->neg_chap) {
+        ChapAuthWithPeer(unit, ppp_settings.user, ho->chap_mdtype);
+        auth |= CHAP_WITHPEER;
+    }
+#endif
+#if PAP_SUPPORT > 0 && CHAP_SUPPORT > 0
+    else
+#endif
+#if PAP_SUPPORT > 0
+    if (ho->neg_upap) {
+        if (ppp_settings.passwd[0] == 0) {
+            passwd_from_file = 1;
+            if (!get_pap_passwd(unit, ppp_settings.user, ppp_settings.passwd))
+                AUTHDEBUG((LOG_ERR, "No secret found for PAP login\n"));
+        }
+        upap_authwithpeer(unit, ppp_settings.user, ppp_settings.passwd);
+        auth |= PAP_WITHPEER;
+    }
+#endif
+    auth_pending[unit] = auth;
+    
+    if (!auth)
+        network_phase(unit);
+}
+
+
+/*
+ * The peer has failed to authenticate himself using `protocol'.
+ */
+void auth_peer_fail(int unit, u16_t protocol)
+{
+    AUTHDEBUG((LOG_INFO, "auth_peer_fail: %d proto=%X\n", unit, protocol));
+    /*
+     * Authentication failure: take the link down
+     */
+    lcp_close(unit, "Authentication failed");
+}
+
+
+#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
+/*
+ * The peer has been successfully authenticated using `protocol'.
+ */
+void auth_peer_success(int unit, u16_t protocol, char *name, int namelen)
+{
+    int pbit;
+    
+    AUTHDEBUG((LOG_INFO, "auth_peer_success: %d proto=%X\n", unit, protocol));
+    switch (protocol) {
+    case PPP_CHAP:
+        pbit = CHAP_PEER;
+        break;
+    case PPP_PAP:
+        pbit = PAP_PEER;
+        break;
+    default:
+        AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n",
+               protocol));
+        return;
+    }
+    
+    /*
+     * Save the authenticated name of the peer for later.
+     */
+    if (namelen > sizeof(peer_authname) - 1)
+        namelen = sizeof(peer_authname) - 1;
+    BCOPY(name, peer_authname, namelen);
+    peer_authname[namelen] = 0;
+    
+    /*
+     * If there is no more authentication still to be done,
+     * proceed to the network (or callback) phase.
+     */
+    if ((auth_pending[unit] &= ~pbit) == 0)
+        network_phase(unit);
+}
+
+/*
+ * We have failed to authenticate ourselves to the peer using `protocol'.
+ */
+void auth_withpeer_fail(int unit, u16_t protocol)
+{
+    int errCode = PPPERR_AUTHFAIL;
+    
+    AUTHDEBUG((LOG_INFO, "auth_withpeer_fail: %d proto=%X\n", unit, protocol));
+    if (passwd_from_file)
+        BZERO(ppp_settings.passwd, MAXSECRETLEN);
+    /* 
+     * XXX Warning: the unit number indicates the interface which is
+     * not necessarily the PPP connection.  It works here as long
+     * as we are only supporting PPP interfaces.
+     */
+    pppIOCtl(unit, PPPCTLS_ERRCODE, &errCode);
+
+    /*
+     * We've failed to authenticate ourselves to our peer.
+     * He'll probably take the link down, and there's not much
+     * we can do except wait for that.
+     */
+}
+
+/*
+ * We have successfully authenticated ourselves with the peer using `protocol'.
+ */
+void auth_withpeer_success(int unit, u16_t protocol)
+{
+    int pbit;
+    
+    AUTHDEBUG((LOG_INFO, "auth_withpeer_success: %d proto=%X\n", unit, protocol));
+    switch (protocol) {
+    case PPP_CHAP:
+        pbit = CHAP_WITHPEER;
+        break;
+    case PPP_PAP:
+        if (passwd_from_file)
+            BZERO(ppp_settings.passwd, MAXSECRETLEN);
+        pbit = PAP_WITHPEER;
+        break;
+    default:
+        AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n",
+               protocol));
+        pbit = 0;
+    }
+    
+    /*
+     * If there is no more authentication still being done,
+     * proceed to the network (or callback) phase.
+     */
+    if ((auth_pending[unit] &= ~pbit) == 0)
+        network_phase(unit);
+}
+#endif
+
+
+/*
+ * np_up - a network protocol has come up.
+ */
+void np_up(int unit, u16_t proto)
+{
+    AUTHDEBUG((LOG_INFO, "np_up: %d proto=%X\n", unit, proto));
+    if (num_np_up == 0) {
+	AUTHDEBUG((LOG_INFO, "np_up: maxconnect=%d idle_time_limit=%d\n",ppp_settings.maxconnect,ppp_settings.idle_time_limit));
+        /*
+         * At this point we consider that the link has come up successfully.
+         */
+        if (ppp_settings.idle_time_limit > 0)
+            TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit);
+        
+        /*
+         * Set a timeout to close the connection once the maximum
+         * connect time has expired.
+         */
+        if (ppp_settings.maxconnect > 0)
+            TIMEOUT(connect_time_expired, 0, ppp_settings.maxconnect);
+    }
+    ++num_np_up;
+}
+
+/*
+ * np_down - a network protocol has gone down.
+ */
+void np_down(int unit, u16_t proto)
+{
+    AUTHDEBUG((LOG_INFO, "np_down: %d proto=%X\n", unit, proto));
+    if (--num_np_up == 0 && ppp_settings.idle_time_limit > 0) {
+        UNTIMEOUT(check_idle, NULL);
+    }
+}
+
+/*
+ * np_finished - a network protocol has finished using the link.
+ */
+void np_finished(int unit, u16_t proto)
+{
+    AUTHDEBUG((LOG_INFO, "np_finished: %d proto=%X\n", unit, proto));
+    if (--num_np_open <= 0) {
+        /* no further use for the link: shut up shop. */
+        lcp_close(0, "No network protocols running");
+    }
+}
+
+/*
+ * auth_reset - called when LCP is starting negotiations to recheck
+ * authentication options, i.e. whether we have appropriate secrets
+ * to use for authenticating ourselves and/or the peer.
+ */
+void auth_reset(int unit)
+{
+    lcp_options *go = &lcp_gotoptions[unit];
+    lcp_options *ao = &lcp_allowoptions[0];
+    ipcp_options *ipwo = &ipcp_wantoptions[0];
+    u32_t remote;
+    
+    AUTHDEBUG((LOG_INFO, "auth_reset: %d\n", unit));
+    ao->neg_upap = !ppp_settings.refuse_pap && (ppp_settings.passwd[0] != 0 || get_pap_passwd(unit, NULL, NULL));
+    ao->neg_chap = !ppp_settings.refuse_chap && ppp_settings.passwd[0] != 0 /*have_chap_secret(ppp_settings.user, ppp_settings.remote_name, (u32_t)0)*/;
+    
+    if (go->neg_upap && !have_pap_secret())
+        go->neg_upap = 0;
+    if (go->neg_chap) {
+        remote = ipwo->accept_remote? 0: ipwo->hisaddr;
+        if (!have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote))
+            go->neg_chap = 0;
+    }
+}
+
+
+#if PAP_SUPPORT > 0
+/*
+ * check_passwd - Check the user name and passwd against the PAP secrets
+ * file.  If requested, also check against the system password database,
+ * and login the user if OK.
+ *
+ * returns:
+ *  UPAP_AUTHNAK: Authentication failed.
+ *  UPAP_AUTHACK: Authentication succeeded.
+ * In either case, msg points to an appropriate message.
+ */
+int check_passwd(
+	int unit,
+	char *auser,
+	int userlen,
+	char *apasswd,
+	int passwdlen,
+	char **msg,
+	int *msglen
+)
+{
+#if 1
+	*msg = (char *) 0;
+	return UPAP_AUTHACK;     /* XXX Assume all entries OK. */
+#else
+    int ret = 0;
+    struct wordlist *addrs = NULL;
+    char passwd[256], user[256];
+    char secret[MAXWORDLEN];
+    static u_short attempts = 0;
+    
+    /*
+     * Make copies of apasswd and auser, then null-terminate them.
+     */
+    BCOPY(apasswd, passwd, passwdlen);
+    passwd[passwdlen] = '\0';
+    BCOPY(auser, user, userlen);
+    user[userlen] = '\0';
+    *msg = (char *) 0;
+
+    /* XXX Validate user name and password. */
+    ret = UPAP_AUTHACK;     /* XXX Assume all entries OK. */
+        
+    if (ret == UPAP_AUTHNAK) {
+        if (*msg == (char *) 0)
+            *msg = "Login incorrect";
+        *msglen = strlen(*msg);
+        /*
+         * Frustrate passwd stealer programs.
+         * Allow 10 tries, but start backing off after 3 (stolen from login).
+         * On 10'th, drop the connection.
+         */
+        if (attempts++ >= 10) {
+            AUTHDEBUG((LOG_WARNING, "%d LOGIN FAILURES BY %s\n", attempts, user));
+            /*ppp_panic("Excess Bad Logins");*/
+        }
+        if (attempts > 3) {
+            sys_msleep((attempts - 3) * 5);
+        }
+        if (addrs != NULL) {
+            free_wordlist(addrs);
+        }
+    } else {
+        attempts = 0;           /* Reset count */
+        if (*msg == (char *) 0)
+            *msg = "Login ok";
+        *msglen = strlen(*msg);
+        set_allowed_addrs(unit, addrs);
+    }
+    
+    BZERO(passwd, sizeof(passwd));
+    BZERO(secret, sizeof(secret));
+    
+    return ret;
+#endif
+}
+#endif
+
+
+/*
+ * auth_ip_addr - check whether the peer is authorized to use
+ * a given IP address.  Returns 1 if authorized, 0 otherwise.
+ */
+int auth_ip_addr(int unit, u32_t addr)
+{
+    return ip_addr_check(addr, addresses[unit]);
+}
+
+/*
+ * bad_ip_adrs - return 1 if the IP address is one we don't want
+ * to use, such as an address in the loopback net or a multicast address.
+ * addr is in network byte order.
+ */
+int bad_ip_adrs(u32_t addr)
+{
+    addr = ntohl(addr);
+    return (addr >> IN_CLASSA_NSHIFT) == IN_LOOPBACKNET
+        || IN_MULTICAST(addr) || IN_BADCLASS(addr);
+}
+
+
+#if CHAP_SUPPORT > 0
+/*
+ * get_secret - open the CHAP secret file and return the secret
+ * for authenticating the given client on the given server.
+ * (We could be either client or server).
+ */
+int get_secret(
+    int unit,
+    char *client,
+    char *server,
+    char *secret,
+    int *secret_len,
+    int save_addrs
+)
+{
+#if 1
+    int len;
+    struct wordlist *addrs;
+    
+    addrs = NULL;
+
+    if(!client || !client[0] || strcmp(client, ppp_settings.user)) {
+	return 0;
+    }
+
+    len = strlen(ppp_settings.passwd);
+    if (len > MAXSECRETLEN) {
+        AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server));
+        len = MAXSECRETLEN;
+    }
+    BCOPY(ppp_settings.passwd, secret, len);
+    *secret_len = len;
+    
+    return 1;
+#else
+    int ret = 0, len;
+    struct wordlist *addrs;
+    char secbuf[MAXWORDLEN];
+    
+    addrs = NULL;
+    secbuf[0] = 0;
+
+    /* XXX Find secret. */  
+    if (ret < 0)
+        return 0;
+    
+    if (save_addrs)
+        set_allowed_addrs(unit, addrs);
+    
+    len = strlen(secbuf);
+    if (len > MAXSECRETLEN) {
+        AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server));
+        len = MAXSECRETLEN;
+    }
+    BCOPY(secbuf, secret, len);
+    BZERO(secbuf, sizeof(secbuf));
+    *secret_len = len;
+    
+    return 1;
+#endif
+}
+#endif
+
+
+#if 0 /* UNUSED */
+/*
+ * auth_check_options - called to check authentication options.
+ */
+void auth_check_options(void)
+{
+    lcp_options *wo = &lcp_wantoptions[0];
+    int can_auth;
+    ipcp_options *ipwo = &ipcp_wantoptions[0];
+    u32_t remote;
+    
+    /* Default our_name to hostname, and user to our_name */
+    if (ppp_settings.our_name[0] == 0 || ppp_settings.usehostname)
+        strcpy(ppp_settings.our_name, ppp_settings.hostname);
+    if (ppp_settings.user[0] == 0)
+        strcpy(ppp_settings.user, ppp_settings.our_name);
+    
+    /* If authentication is required, ask peer for CHAP or PAP. */
+    if (ppp_settings.auth_required && !wo->neg_chap && !wo->neg_upap) {
+        wo->neg_chap = 1;
+        wo->neg_upap = 1;
+    }
+    
+    /*
+     * Check whether we have appropriate secrets to use
+     * to authenticate the peer.
+     */
+    can_auth = wo->neg_upap && have_pap_secret();
+    if (!can_auth && wo->neg_chap) {
+        remote = ipwo->accept_remote? 0: ipwo->hisaddr;
+        can_auth = have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote);
+    }
+    
+    if (ppp_settings.auth_required && !can_auth) {
+        ppp_panic("No auth secret");
+    }
+}
+#endif
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * Proceed to the network phase.
+ */
+static void network_phase(int unit)
+{
+    int i;
+    struct protent *protp;
+    lcp_options *go = &lcp_gotoptions[unit];
+    
+    /*
+     * If the peer had to authenticate, run the auth-up script now.
+     */
+    if ((go->neg_chap || go->neg_upap) && !did_authup) {
+        /* XXX Do setup for peer authentication. */
+        did_authup = 1;
+    }
+    
+#if CBCP_SUPPORT > 0
+    /*
+     * If we negotiated callback, do it now.
+     */
+    if (go->neg_cbcp) {
+        lcp_phase[unit] = PHASE_CALLBACK;
+        (*cbcp_protent.open)(unit);
+        return;
+    }
+#endif
+    
+    lcp_phase[unit] = PHASE_NETWORK;
+    for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i)
+        if (protp->protocol < 0xC000 && protp->enabled_flag
+                && protp->open != NULL) {
+            (*protp->open)(unit);
+            if (protp->protocol != PPP_CCP)
+                ++num_np_open;
+        }
+    
+    if (num_np_open == 0)
+        /* nothing to do */
+        lcp_close(0, "No network protocols running");
+}
+
+/*
+ * check_idle - check whether the link has been idle for long
+ * enough that we can shut it down.
+ */
+static void check_idle(void *arg)
+{
+    struct ppp_idle idle;
+    u_short itime;
+    
+	(void)arg;
+    if (!get_idle_time(0, &idle))
+        return;
+    itime = LWIP_MIN(idle.xmit_idle, idle.recv_idle);
+    if (itime >= ppp_settings.idle_time_limit) {
+        /* link is idle: shut it down. */
+        AUTHDEBUG((LOG_INFO, "Terminating connection due to lack of activity.\n"));
+        lcp_close(0, "Link inactive");
+    } else {
+        TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit - itime);
+    }
+}
+
+/*
+ * connect_time_expired - log a message and close the connection.
+ */
+static void connect_time_expired(void *arg)
+{
+	(void)arg;
+
+    AUTHDEBUG((LOG_INFO, "Connect time expired\n"));
+    lcp_close(0, "Connect time expired");   /* Close connection */
+}
+
+#if 0
+/*
+ * login - Check the user name and password against the system
+ * password database, and login the user if OK.
+ *
+ * returns:
+ *  UPAP_AUTHNAK: Login failed.
+ *  UPAP_AUTHACK: Login succeeded.
+ * In either case, msg points to an appropriate message.
+ */
+static int login(char *user, char *passwd, char **msg, int *msglen)
+{
+    /* XXX Fail until we decide that we want to support logins. */
+    return (UPAP_AUTHNAK);
+}
+#endif
+
+/*
+ * logout - Logout the user.
+ */
+static void logout(void)
+{
+    logged_in = 0;
+}
+
+
+/*
+ * null_login - Check if a username of "" and a password of "" are
+ * acceptable, and iff so, set the list of acceptable IP addresses
+ * and return 1.
+ */
+static int null_login(int unit)
+{
+	(void)unit;
+    /* XXX Fail until we decide that we want to support logins. */
+    return 0;
+}
+
+
+/*
+ * get_pap_passwd - get a password for authenticating ourselves with
+ * our peer using PAP.  Returns 1 on success, 0 if no suitable password
+ * could be found.
+ */
+static int get_pap_passwd(int unit, char *user, char *passwd)
+{
+/* normally we would reject PAP if no password is provided,
+   but this causes problems with some providers (like CHT in Taiwan)
+   who incorrectly request PAP and expect a bogus/empty password, so
+   always provide a default user/passwd of "none"/"none"
+*/
+    if(user)
+    	strcpy(user,   "none");
+    if(passwd)
+    	strcpy(passwd, "none");
+
+    return 1;
+}
+
+
+/*
+ * have_pap_secret - check whether we have a PAP file with any
+ * secrets that we could possibly use for authenticating the peer.
+ */
+static int have_pap_secret(void)
+{
+    /* XXX Fail until we set up our passwords. */
+    return 0;
+}
+
+
+/*
+ * have_chap_secret - check whether we have a CHAP file with a
+ * secret that we could possibly use for authenticating `client'
+ * on `server'.  Either can be the null string, meaning we don't
+ * know the identity yet.
+ */
+static int have_chap_secret(char *client, char *server, u32_t remote)
+{
+	(void)client;
+	(void)server;
+	(void)remote;
+    /* XXX Fail until we set up our passwords. */
+    return 0;
+}
+
+
+#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 */
+/*
+ * set_allowed_addrs() - set the list of allowed addresses.
+ */
+static void set_allowed_addrs(int unit, struct wordlist *addrs)
+{
+    if (addresses[unit] != NULL)
+        free_wordlist(addresses[unit]);
+    addresses[unit] = addrs;
+
+#if 0
+    /*
+     * If there's only one authorized address we might as well
+     * ask our peer for that one right away
+     */
+    if (addrs != NULL && addrs->next == NULL) {
+        char *p = addrs->word;
+        struct ipcp_options *wo = &ipcp_wantoptions[unit];
+        u32_t a;
+        struct hostent *hp;
+        
+        if (wo->hisaddr == 0 && *p != '!' && *p != '-'
+                && strchr(p, '/') == NULL) {
+            hp = gethostbyname(p);
+            if (hp != NULL && hp->h_addrtype == AF_INET)
+                a = *(u32_t *)hp->h_addr;
+            else
+                a = inet_addr(p);
+            if (a != (u32_t) -1)
+                wo->hisaddr = a;
+        }
+    }
+#endif
+}
+#endif
+
+static int ip_addr_check(u32_t addr, struct wordlist *addrs)
+{
+    
+    /* don't allow loopback or multicast address */
+    if (bad_ip_adrs(addr))
+        return 0;
+    
+    if (addrs == NULL)
+        return !ppp_settings.auth_required;      /* no addresses authorized */
+    
+    /* XXX All other addresses allowed. */
+    return 1;
+}
+
+#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT */
+/*
+ * free_wordlist - release memory allocated for a wordlist.
+ */
+static void free_wordlist(struct wordlist *wp)
+{
+    struct wordlist *next;
+    
+    while (wp != NULL) {
+        next = wp->next;
+        free(wp);
+        wp = next;
+    }
+}
+#endif
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/auth.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/auth.h
new file mode 100644
index 0000000..5817405
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/auth.h
@@ -0,0 +1,94 @@
+/*****************************************************************************
+* auth.h -  PPP Authentication and phase control header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*	Original derived from BSD pppd.h.
+*****************************************************************************/
+/*
+ * pppd.h - PPP daemon global declarations.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ */
+
+#ifndef AUTH_H
+#define AUTH_H
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+void link_required (int);		/* we are starting to use the link */
+void link_terminated (int);	/* we are finished with the link */
+void link_down (int);			/* the LCP layer has left the Opened state */
+void link_established (int);	/* the link is up; authenticate now */
+void np_up (int, u16_t);			/* a network protocol has come up */
+void np_down (int, u16_t);		/* a network protocol has gone down */
+void np_finished (int, u16_t);	/* a network protocol no longer needs link */
+void auth_peer_fail (int, u16_t);/* peer failed to authenticate itself */
+
+/* peer successfully authenticated itself */
+void auth_peer_success (int, u16_t, char *, int);
+
+/* we failed to authenticate ourselves */
+void auth_withpeer_fail (int, u16_t);
+
+/* we successfully authenticated ourselves */
+void auth_withpeer_success (int, u16_t);
+
+/* check authentication options supplied */
+void auth_check_options (void);
+void auth_reset (int);			/* check what secrets we have */
+
+/* Check peer-supplied username/password */
+int  check_passwd (int, char *, int, char *, int, char **, int *);
+
+/* get "secret" for chap */
+int  get_secret (int, char *, char *, char *, int *, int);
+
+/* check if IP address is authorized */
+int  auth_ip_addr (int, u32_t);
+
+/* check if IP address is unreasonable */
+int  bad_ip_adrs (u32_t);
+
+
+#endif /* AUTH_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/chap.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/chap.c
new file mode 100644
index 0000000..30441bd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/chap.c
@@ -0,0 +1,872 @@
+/*** WARNING - THIS HAS NEVER BEEN FINISHED ***/
+/*****************************************************************************
+* chap.c - Network Challenge Handshake Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*	Original based on BSD chap.c.
+*****************************************************************************/
+/*
+ * chap.c - Challenge Handshake Authentication Protocol.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University.  The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1991 Gregory M. Christy.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Gregory M. Christy.  The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "magic.h"
+
+#if CHAP_SUPPORT > 0
+
+#include "randm.h"
+#include "auth.h"
+#include "md5.h"
+#include "chap.h"
+#include "chpms.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Protocol entry points.
+ */
+static void ChapInit (int);
+static void ChapLowerUp (int);
+static void ChapLowerDown (int);
+static void ChapInput (int, u_char *, int);
+static void ChapProtocolReject (int);
+static int  ChapPrintPkt (u_char *, int,
+			      void (*) (void *, char *, ...), void *);
+
+static void ChapChallengeTimeout (void *);
+static void ChapResponseTimeout (void *);
+static void ChapReceiveChallenge (chap_state *, u_char *, int, int);
+static void ChapRechallenge (void *);
+static void ChapReceiveResponse (chap_state *, u_char *, int, int);
+static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len);
+static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len);
+static void ChapSendStatus (chap_state *, int);
+static void ChapSendChallenge (chap_state *);
+static void ChapSendResponse (chap_state *);
+static void ChapGenChallenge (chap_state *);
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+chap_state chap[NUM_PPP];		/* CHAP state; one for each unit */
+
+struct protent chap_protent = {
+    PPP_CHAP,
+    ChapInit,
+    ChapInput,
+    ChapProtocolReject,
+    ChapLowerUp,
+    ChapLowerDown,
+    NULL,
+    NULL,
+#if 0
+    ChapPrintPkt,
+    NULL,
+#endif
+    1,
+    "CHAP",
+#if 0
+    NULL,
+    NULL,
+    NULL
+#endif
+};
+
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static char *ChapCodenames[] = {
+	"Challenge", "Response", "Success", "Failure"
+};
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * ChapAuthWithPeer - Authenticate us with our peer (start client).
+ *
+ */
+void ChapAuthWithPeer(int unit, char *our_name, int digest)
+{
+	chap_state *cstate = &chap[unit];
+	
+	cstate->resp_name = our_name;
+	cstate->resp_type = digest;
+	
+	if (cstate->clientstate == CHAPCS_INITIAL ||
+			cstate->clientstate == CHAPCS_PENDING) {
+		/* lower layer isn't up - wait until later */
+		cstate->clientstate = CHAPCS_PENDING;
+		return;
+	}
+	
+	/*
+	 * We get here as a result of LCP coming up.
+	 * So even if CHAP was open before, we will 
+	 * have to re-authenticate ourselves.
+	 */
+	cstate->clientstate = CHAPCS_LISTEN;
+}
+
+
+/*
+ * ChapAuthPeer - Authenticate our peer (start server).
+ */
+void ChapAuthPeer(int unit, char *our_name, int digest)
+{
+	chap_state *cstate = &chap[unit];
+	
+	cstate->chal_name = our_name;
+	cstate->chal_type = digest;
+	
+	if (cstate->serverstate == CHAPSS_INITIAL ||
+			cstate->serverstate == CHAPSS_PENDING) {
+		/* lower layer isn't up - wait until later */
+		cstate->serverstate = CHAPSS_PENDING;
+		return;
+	}
+	
+	ChapGenChallenge(cstate);
+	ChapSendChallenge(cstate);		/* crank it up dude! */
+	cstate->serverstate = CHAPSS_INITIAL_CHAL;
+}
+
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * ChapInit - Initialize a CHAP unit.
+ */
+static void ChapInit(int unit)
+{
+	chap_state *cstate = &chap[unit];
+	
+	BZERO(cstate, sizeof(*cstate));
+	cstate->unit = unit;
+	cstate->clientstate = CHAPCS_INITIAL;
+	cstate->serverstate = CHAPSS_INITIAL;
+	cstate->timeouttime = CHAP_DEFTIMEOUT;
+	cstate->max_transmits = CHAP_DEFTRANSMITS;
+	/* random number generator is initialized in magic_init */
+}
+
+
+/*
+ * ChapChallengeTimeout - Timeout expired on sending challenge.
+ */
+static void ChapChallengeTimeout(void *arg)
+{
+	chap_state *cstate = (chap_state *) arg;
+	
+	/* if we aren't sending challenges, don't worry.  then again we */
+	/* probably shouldn't be here either */
+	if (cstate->serverstate != CHAPSS_INITIAL_CHAL &&
+			cstate->serverstate != CHAPSS_RECHALLENGE)
+		return;
+	
+	if (cstate->chal_transmits >= cstate->max_transmits) {
+		/* give up on peer */
+		CHAPDEBUG((LOG_ERR, "Peer failed to respond to CHAP challenge\n"));
+		cstate->serverstate = CHAPSS_BADAUTH;
+		auth_peer_fail(cstate->unit, PPP_CHAP);
+		return;
+	}
+	
+	ChapSendChallenge(cstate);		/* Re-send challenge */
+}
+
+
+/*
+ * ChapResponseTimeout - Timeout expired on sending response.
+ */
+static void ChapResponseTimeout(void *arg)
+{
+	chap_state *cstate = (chap_state *) arg;
+	
+	/* if we aren't sending a response, don't worry. */
+	if (cstate->clientstate != CHAPCS_RESPONSE)
+		return;
+	
+	ChapSendResponse(cstate);		/* re-send response */
+}
+
+
+/*
+ * ChapRechallenge - Time to challenge the peer again.
+ */
+static void ChapRechallenge(void *arg)
+{
+	chap_state *cstate = (chap_state *) arg;
+	
+	/* if we aren't sending a response, don't worry. */
+	if (cstate->serverstate != CHAPSS_OPEN)
+		return;
+	
+	ChapGenChallenge(cstate);
+	ChapSendChallenge(cstate);
+	cstate->serverstate = CHAPSS_RECHALLENGE;
+}
+
+
+/*
+ * ChapLowerUp - The lower layer is up.
+ *
+ * Start up if we have pending requests.
+ */
+static void ChapLowerUp(int unit)
+{
+	chap_state *cstate = &chap[unit];
+	
+	if (cstate->clientstate == CHAPCS_INITIAL)
+		cstate->clientstate = CHAPCS_CLOSED;
+	else if (cstate->clientstate == CHAPCS_PENDING)
+		cstate->clientstate = CHAPCS_LISTEN;
+	
+	if (cstate->serverstate == CHAPSS_INITIAL)
+		cstate->serverstate = CHAPSS_CLOSED;
+	else if (cstate->serverstate == CHAPSS_PENDING) {
+		ChapGenChallenge(cstate);
+		ChapSendChallenge(cstate);
+		cstate->serverstate = CHAPSS_INITIAL_CHAL;
+	}
+}
+
+
+/*
+ * ChapLowerDown - The lower layer is down.
+ *
+ * Cancel all timeouts.
+ */
+static void ChapLowerDown(int unit)
+{
+	chap_state *cstate = &chap[unit];
+	
+	/* Timeout(s) pending?  Cancel if so. */
+	if (cstate->serverstate == CHAPSS_INITIAL_CHAL ||
+			cstate->serverstate == CHAPSS_RECHALLENGE)
+		UNTIMEOUT(ChapChallengeTimeout, cstate);
+	else if (cstate->serverstate == CHAPSS_OPEN
+			&& cstate->chal_interval != 0)
+		UNTIMEOUT(ChapRechallenge, cstate);
+	if (cstate->clientstate == CHAPCS_RESPONSE)
+		UNTIMEOUT(ChapResponseTimeout, cstate);
+	
+	cstate->clientstate = CHAPCS_INITIAL;
+	cstate->serverstate = CHAPSS_INITIAL;
+}
+
+
+/*
+ * ChapProtocolReject - Peer doesn't grok CHAP.
+ */
+static void ChapProtocolReject(int unit)
+{
+	chap_state *cstate = &chap[unit];
+	
+	if (cstate->serverstate != CHAPSS_INITIAL &&
+			cstate->serverstate != CHAPSS_CLOSED)
+		auth_peer_fail(unit, PPP_CHAP);
+	if (cstate->clientstate != CHAPCS_INITIAL &&
+			cstate->clientstate != CHAPCS_CLOSED)
+		auth_withpeer_fail(unit, PPP_CHAP);
+	ChapLowerDown(unit);		/* shutdown chap */
+}
+
+
+/*
+ * ChapInput - Input CHAP packet.
+ */
+static void ChapInput(int unit, u_char *inpacket, int packet_len)
+{
+	chap_state *cstate = &chap[unit];
+	u_char *inp;
+	u_char code, id;
+	int len;
+	
+	/*
+	 * Parse header (code, id and length).
+	 * If packet too short, drop it.
+	 */
+	inp = inpacket;
+	if (packet_len < CHAP_HEADERLEN) {
+		CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short header.\n"));
+		return;
+	}
+	GETCHAR(code, inp);
+	GETCHAR(id, inp);
+	GETSHORT(len, inp);
+	if (len < CHAP_HEADERLEN) {
+		CHAPDEBUG((LOG_INFO, "ChapInput: rcvd illegal length.\n"));
+		return;
+	}
+	if (len > packet_len) {
+		CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short packet.\n"));
+		return;
+	}
+	len -= CHAP_HEADERLEN;
+	
+	/*
+	 * Action depends on code (as in fact it usually does :-).
+	 */
+	switch (code) {
+	case CHAP_CHALLENGE:
+		ChapReceiveChallenge(cstate, inp, id, len);
+		break;
+	
+	case CHAP_RESPONSE:
+		ChapReceiveResponse(cstate, inp, id, len);
+		break;
+	
+	case CHAP_FAILURE:
+		ChapReceiveFailure(cstate, inp, id, len);
+		break;
+	
+	case CHAP_SUCCESS:
+		ChapReceiveSuccess(cstate, inp, id, len);
+		break;
+	
+	default:				/* Need code reject? */
+		CHAPDEBUG((LOG_WARNING, "Unknown CHAP code (%d) received.\n", code));
+		break;
+	}
+}
+
+
+/*
+ * ChapReceiveChallenge - Receive Challenge and send Response.
+ */
+static void ChapReceiveChallenge(chap_state *cstate, u_char *inp, int id, int len)
+{
+	int rchallenge_len;
+	u_char *rchallenge;
+	int secret_len;
+	char secret[MAXSECRETLEN];
+	char rhostname[256];
+	MD5_CTX mdContext;
+	u_char hash[MD5_SIGNATURE_SIZE];
+	
+	CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: Rcvd id %d.\n", id));
+	if (cstate->clientstate == CHAPCS_CLOSED ||
+		cstate->clientstate == CHAPCS_PENDING) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: in state %d\n",
+			   cstate->clientstate));
+		return;
+	}
+	
+	if (len < 2) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n"));
+		return;
+	}
+	
+	GETCHAR(rchallenge_len, inp);
+	len -= sizeof (u_char) + rchallenge_len;	/* now name field length */
+	if (len < 0) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n"));
+		return;
+	}
+	rchallenge = inp;
+	INCPTR(rchallenge_len, inp);
+	
+	if (len >= sizeof(rhostname))
+		len = sizeof(rhostname) - 1;
+	BCOPY(inp, rhostname, len);
+	rhostname[len] = '\000';
+	
+	CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: received name field '%s'\n",
+	       rhostname));
+	
+	/* Microsoft doesn't send their name back in the PPP packet */
+	if (ppp_settings.remote_name[0] != 0 && (ppp_settings.explicit_remote || rhostname[0] == 0)) {
+		strncpy(rhostname, ppp_settings.remote_name, sizeof(rhostname));
+		rhostname[sizeof(rhostname) - 1] = 0;
+		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: using '%s' as remote name\n",
+			   rhostname));
+	}
+	
+	/* get secret for authenticating ourselves with the specified host */
+	if (!get_secret(cstate->unit, cstate->resp_name, rhostname,
+			    secret, &secret_len, 0)) {
+		secret_len = 0;		/* assume null secret if can't find one */
+		CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating us to %s\n", rhostname));
+	}
+	
+	/* cancel response send timeout if necessary */
+	if (cstate->clientstate == CHAPCS_RESPONSE)
+		UNTIMEOUT(ChapResponseTimeout, cstate);
+	
+	cstate->resp_id = id;
+	cstate->resp_transmits = 0;
+	
+	/*  generate MD based on negotiated type */
+	switch (cstate->resp_type) { 
+	
+	case CHAP_DIGEST_MD5:
+		MD5Init(&mdContext);
+		MD5Update(&mdContext, &cstate->resp_id, 1);
+		MD5Update(&mdContext, (u_char*)secret, secret_len);
+		MD5Update(&mdContext, rchallenge, rchallenge_len);
+		MD5Final(hash, &mdContext);
+		BCOPY(hash, cstate->response, MD5_SIGNATURE_SIZE);
+		cstate->resp_length = MD5_SIGNATURE_SIZE;
+		break;
+	
+#ifdef CHAPMS
+	case CHAP_MICROSOFT:
+		ChapMS(cstate, rchallenge, rchallenge_len, secret, secret_len);
+		break;
+#endif
+	
+	default:
+		CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->resp_type));
+		return;
+	}
+	
+	BZERO(secret, sizeof(secret));
+	ChapSendResponse(cstate);
+}
+
+
+/*
+ * ChapReceiveResponse - Receive and process response.
+ */
+static void ChapReceiveResponse(chap_state *cstate, u_char *inp, int id, int len)
+{
+	u_char *remmd, remmd_len;
+	int secret_len, old_state;
+	int code;
+	char rhostname[256];
+	MD5_CTX mdContext;
+	char secret[MAXSECRETLEN];
+	u_char hash[MD5_SIGNATURE_SIZE];
+	
+	CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: Rcvd id %d.\n", id));
+	
+	if (cstate->serverstate == CHAPSS_CLOSED ||
+			cstate->serverstate == CHAPSS_PENDING) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: in state %d\n",
+		cstate->serverstate));
+		return;
+	}
+	
+	if (id != cstate->chal_id)
+		return;			/* doesn't match ID of last challenge */
+	
+	/*
+	* If we have received a duplicate or bogus Response,
+	* we have to send the same answer (Success/Failure)
+	* as we did for the first Response we saw.
+	*/
+	if (cstate->serverstate == CHAPSS_OPEN) {
+		ChapSendStatus(cstate, CHAP_SUCCESS);
+		return;
+	}
+	if (cstate->serverstate == CHAPSS_BADAUTH) {
+		ChapSendStatus(cstate, CHAP_FAILURE);
+		return;
+	}
+	
+	if (len < 2) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n"));
+		return;
+	}
+	GETCHAR(remmd_len, inp);		/* get length of MD */
+	remmd = inp;			/* get pointer to MD */
+	INCPTR(remmd_len, inp);
+	
+	len -= sizeof (u_char) + remmd_len;
+	if (len < 0) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n"));
+		return;
+	}
+	
+	UNTIMEOUT(ChapChallengeTimeout, cstate);
+	
+	if (len >= sizeof(rhostname))
+		len = sizeof(rhostname) - 1;
+	BCOPY(inp, rhostname, len);
+	rhostname[len] = '\000';
+	
+	CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: received name field: %s\n",
+				rhostname));
+	
+	/*
+	* Get secret for authenticating them with us,
+	* do the hash ourselves, and compare the result.
+	*/
+	code = CHAP_FAILURE;
+	if (!get_secret(cstate->unit, rhostname, cstate->chal_name,
+	secret, &secret_len, 1)) {
+/*        CHAPDEBUG((LOG_WARNING, TL_CHAP, "No CHAP secret found for authenticating %s\n", rhostname)); */
+		CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating %s\n",
+		rhostname));
+	} else {
+	
+		/*  generate MD based on negotiated type */
+		switch (cstate->chal_type) { 
+		
+		case CHAP_DIGEST_MD5:		/* only MD5 is defined for now */
+			if (remmd_len != MD5_SIGNATURE_SIZE)
+				break;			/* it's not even the right length */
+			MD5Init(&mdContext);
+			MD5Update(&mdContext, &cstate->chal_id, 1);
+			MD5Update(&mdContext, (u_char*)secret, secret_len);
+			MD5Update(&mdContext, cstate->challenge, cstate->chal_len);
+			MD5Final(hash, &mdContext); 
+			
+			/* compare local and remote MDs and send the appropriate status */
+			if (memcmp (hash, remmd, MD5_SIGNATURE_SIZE) == 0)
+				code = CHAP_SUCCESS;	/* they are the same! */
+			break;
+		
+		default:
+			CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->chal_type));
+		}
+	}
+	
+	BZERO(secret, sizeof(secret));
+	ChapSendStatus(cstate, code);
+	
+	if (code == CHAP_SUCCESS) {
+		old_state = cstate->serverstate;
+		cstate->serverstate = CHAPSS_OPEN;
+		if (old_state == CHAPSS_INITIAL_CHAL) {
+			auth_peer_success(cstate->unit, PPP_CHAP, rhostname, len);
+		}
+		if (cstate->chal_interval != 0)
+			TIMEOUT(ChapRechallenge, cstate, cstate->chal_interval);
+	} else {
+		CHAPDEBUG((LOG_ERR, "CHAP peer authentication failed\n"));
+		cstate->serverstate = CHAPSS_BADAUTH;
+		auth_peer_fail(cstate->unit, PPP_CHAP);
+	}
+}
+
+/*
+ * ChapReceiveSuccess - Receive Success
+ */
+static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len)
+{
+
+	CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: Rcvd id %d.\n", id));
+	
+	if (cstate->clientstate == CHAPCS_OPEN)
+		/* presumably an answer to a duplicate response */
+		return;
+	
+	if (cstate->clientstate != CHAPCS_RESPONSE) {
+		/* don't know what this is */
+		CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: in state %d\n",
+			   cstate->clientstate));
+		return;
+	}
+	
+	UNTIMEOUT(ChapResponseTimeout, cstate);
+	
+	/*
+	 * Print message.
+	 */
+	if (len > 0)
+		PRINTMSG(inp, len);
+	
+	cstate->clientstate = CHAPCS_OPEN;
+	
+	auth_withpeer_success(cstate->unit, PPP_CHAP);
+}
+
+
+/*
+ * ChapReceiveFailure - Receive failure.
+ */
+static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len)
+{
+	CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: Rcvd id %d.\n", id));
+	
+	if (cstate->clientstate != CHAPCS_RESPONSE) {
+		/* don't know what this is */
+		CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: in state %d\n",
+			   cstate->clientstate));
+		return;
+	}
+	
+	UNTIMEOUT(ChapResponseTimeout, cstate);
+	
+	/*
+	 * Print message.
+	 */
+	if (len > 0)
+		PRINTMSG(inp, len);
+	
+	CHAPDEBUG((LOG_ERR, "CHAP authentication failed\n"));
+	auth_withpeer_fail(cstate->unit, PPP_CHAP);
+}
+
+
+/*
+ * ChapSendChallenge - Send an Authenticate challenge.
+ */
+static void ChapSendChallenge(chap_state *cstate)
+{
+	u_char *outp;
+	int chal_len, name_len;
+	int outlen;
+	
+	chal_len = cstate->chal_len;
+	name_len = strlen(cstate->chal_name);
+	outlen = CHAP_HEADERLEN + sizeof (u_char) + chal_len + name_len;
+	outp = outpacket_buf[cstate->unit];
+	
+	MAKEHEADER(outp, PPP_CHAP);		/* paste in a CHAP header */
+	
+	PUTCHAR(CHAP_CHALLENGE, outp);
+	PUTCHAR(cstate->chal_id, outp);
+	PUTSHORT(outlen, outp);
+	
+	PUTCHAR(chal_len, outp);		/* put length of challenge */
+	BCOPY(cstate->challenge, outp, chal_len);
+	INCPTR(chal_len, outp);
+	
+	BCOPY(cstate->chal_name, outp, name_len);	/* append hostname */
+	
+	pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+	
+	CHAPDEBUG((LOG_INFO, "ChapSendChallenge: Sent id %d.\n", cstate->chal_id));
+	
+	TIMEOUT(ChapChallengeTimeout, cstate, cstate->timeouttime);
+	++cstate->chal_transmits;
+}
+
+
+/*
+ * ChapSendStatus - Send a status response (ack or nak).
+ */
+static void ChapSendStatus(chap_state *cstate, int code)
+{
+	u_char *outp;
+	int outlen, msglen;
+	char msg[256];
+	
+	if (code == CHAP_SUCCESS)
+		strcpy(msg, "Welcome!");
+	else
+		strcpy(msg, "I don't like you.  Go 'way.");
+	msglen = strlen(msg);
+	
+	outlen = CHAP_HEADERLEN + msglen;
+	outp = outpacket_buf[cstate->unit];
+	
+	MAKEHEADER(outp, PPP_CHAP);		/* paste in a header */
+	
+	PUTCHAR(code, outp);
+	PUTCHAR(cstate->chal_id, outp);
+	PUTSHORT(outlen, outp);
+	BCOPY(msg, outp, msglen);
+	pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+	
+	CHAPDEBUG((LOG_INFO, "ChapSendStatus: Sent code %d, id %d.\n", code,
+	       cstate->chal_id));
+}
+
+/*
+ * ChapGenChallenge is used to generate a pseudo-random challenge string of
+ * a pseudo-random length between min_len and max_len.  The challenge
+ * string and its length are stored in *cstate, and various other fields of
+ * *cstate are initialized.
+ */
+
+static void ChapGenChallenge(chap_state *cstate)
+{
+	int chal_len;
+	u_char *ptr = cstate->challenge;
+	int i;
+	
+	/* pick a random challenge length between MIN_CHALLENGE_LENGTH and 
+	   MAX_CHALLENGE_LENGTH */  
+	chal_len = (unsigned)
+				((((magic() >> 16) *
+			        (MAX_CHALLENGE_LENGTH - MIN_CHALLENGE_LENGTH)) >> 16)
+			     + MIN_CHALLENGE_LENGTH);
+	cstate->chal_len = chal_len;
+	cstate->chal_id = ++cstate->id;
+	cstate->chal_transmits = 0;
+	
+	/* generate a random string */
+	for (i = 0; i < chal_len; i++ )
+		*ptr++ = (char) (magic() & 0xff);
+}
+
+/*
+ * ChapSendResponse - send a response packet with values as specified
+ * in *cstate.
+ */
+/* ARGSUSED */
+static void ChapSendResponse(chap_state *cstate)
+{
+	u_char *outp;
+	int outlen, md_len, name_len;
+	
+	md_len = cstate->resp_length;
+	name_len = strlen(cstate->resp_name);
+	outlen = CHAP_HEADERLEN + sizeof (u_char) + md_len + name_len;
+	outp = outpacket_buf[cstate->unit];
+	
+	MAKEHEADER(outp, PPP_CHAP);
+	
+	PUTCHAR(CHAP_RESPONSE, outp);	/* we are a response */
+	PUTCHAR(cstate->resp_id, outp);	/* copy id from challenge packet */
+	PUTSHORT(outlen, outp);			/* packet length */
+	
+	PUTCHAR(md_len, outp);			/* length of MD */
+	BCOPY(cstate->response, outp, md_len);		/* copy MD to buffer */
+	INCPTR(md_len, outp);
+	
+	BCOPY(cstate->resp_name, outp, name_len);	/* append our name */
+	
+	/* send the packet */
+	pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+	
+	cstate->clientstate = CHAPCS_RESPONSE;
+	TIMEOUT(ChapResponseTimeout, cstate, cstate->timeouttime);
+	++cstate->resp_transmits;
+}
+
+/*
+ * ChapPrintPkt - print the contents of a CHAP packet.
+ */
+static int ChapPrintPkt(
+	u_char *p,
+	int plen,
+	void (*printer) (void *, char *, ...),
+	void *arg
+)
+{
+	int code, id, len;
+	int clen, nlen;
+	u_char x;
+	
+	if (plen < CHAP_HEADERLEN)
+		return 0;
+	GETCHAR(code, p);
+	GETCHAR(id, p);
+	GETSHORT(len, p);
+	if (len < CHAP_HEADERLEN || len > plen)
+		return 0;
+	
+	if (code >= 1 && code <= sizeof(ChapCodenames) / sizeof(char *))
+		printer(arg, " %s", ChapCodenames[code-1]);
+	else
+		printer(arg, " code=0x%x", code);
+	printer(arg, " id=0x%x", id);
+	len -= CHAP_HEADERLEN;
+	switch (code) {
+	case CHAP_CHALLENGE:
+	case CHAP_RESPONSE:
+		if (len < 1)
+			break;
+		clen = p[0];
+		if (len < clen + 1)
+			break;
+		++p;
+		nlen = len - clen - 1;
+		printer(arg, " <");
+		for (; clen > 0; --clen) {
+			GETCHAR(x, p);
+			printer(arg, "%.2x", x);
+		}
+		printer(arg, ">, name = %.*Z", nlen, p);
+		break;
+	case CHAP_FAILURE:
+	case CHAP_SUCCESS:
+		printer(arg, " %.*Z", len, p);
+		break;
+	default:
+		for (clen = len; clen > 0; --clen) {
+			GETCHAR(x, p);
+			printer(arg, " %.2x", x);
+		}
+	}
+	
+	return len + CHAP_HEADERLEN;
+}
+
+#endif
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/chap.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/chap.h
new file mode 100644
index 0000000..1aca134
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/chap.h
@@ -0,0 +1,167 @@
+/*****************************************************************************
+* chap.h - Network Challenge Handshake Authentication Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-03 Guy Lancaster , Global Election Systems Inc.
+*	Original built from BSD network code.
+******************************************************************************/
+/*
+ * chap.h - Challenge Handshake Authentication Protocol definitions.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University.  The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1991 Gregory M. Christy
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the author.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: chap.h,v 1.1 2003/05/27 14:37:56 jani Exp $
+ */
+
+#ifndef CHAP_H
+#define CHAP_H
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+
+/* Code + ID + length */
+#define CHAP_HEADERLEN		4
+
+/*
+ * CHAP codes.
+ */
+
+#define CHAP_DIGEST_MD5		5	/* use MD5 algorithm */
+#define MD5_SIGNATURE_SIZE	16	/* 16 bytes in a MD5 message digest */
+#define CHAP_MICROSOFT		0x80	/* use Microsoft-compatible alg. */
+#define MS_CHAP_RESPONSE_LEN	49	/* Response length for MS-CHAP */
+
+#define CHAP_CHALLENGE		1
+#define CHAP_RESPONSE		2
+#define CHAP_SUCCESS		3
+#define CHAP_FAILURE    	4
+
+/*
+ *  Challenge lengths (for challenges we send) and other limits.
+ */
+#define MIN_CHALLENGE_LENGTH	32
+#define MAX_CHALLENGE_LENGTH	64
+#define MAX_RESPONSE_LENGTH	64	/* sufficient for MD5 or MS-CHAP */
+
+/*
+ * Client (peer) states.
+ */
+#define CHAPCS_INITIAL		0	/* Lower layer down, not opened */
+#define CHAPCS_CLOSED		1	/* Lower layer up, not opened */
+#define CHAPCS_PENDING		2	/* Auth us to peer when lower up */
+#define CHAPCS_LISTEN		3	/* Listening for a challenge */
+#define CHAPCS_RESPONSE		4	/* Sent response, waiting for status */
+#define CHAPCS_OPEN		5	/* We've received Success */
+
+/*
+ * Server (authenticator) states.
+ */
+#define CHAPSS_INITIAL		0	/* Lower layer down, not opened */
+#define CHAPSS_CLOSED		1	/* Lower layer up, not opened */
+#define CHAPSS_PENDING		2	/* Auth peer when lower up */
+#define CHAPSS_INITIAL_CHAL	3	/* We've sent the first challenge */
+#define CHAPSS_OPEN		4	/* We've sent a Success msg */
+#define CHAPSS_RECHALLENGE	5	/* We've sent another challenge */
+#define CHAPSS_BADAUTH		6	/* We've sent a Failure msg */
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * Each interface is described by a chap structure.
+ */
+
+typedef struct chap_state {
+    int unit;			/* Interface unit number */
+    int clientstate;		/* Client state */
+    int serverstate;		/* Server state */
+    u_char challenge[MAX_CHALLENGE_LENGTH]; /* last challenge string sent */
+    u_char chal_len;		/* challenge length */
+    u_char chal_id;		/* ID of last challenge */
+    u_char chal_type;		/* hash algorithm for challenges */
+    u_char id;			/* Current id */
+    char *chal_name;		/* Our name to use with challenge */
+    int chal_interval;		/* Time until we challenge peer again */
+    int timeouttime;		/* Timeout time in seconds */
+    int max_transmits;		/* Maximum # of challenge transmissions */
+    int chal_transmits;		/* Number of transmissions of challenge */
+    int resp_transmits;		/* Number of transmissions of response */
+    u_char response[MAX_RESPONSE_LENGTH];	/* Response to send */
+    u_char resp_length;		/* length of response */
+    u_char resp_id;		/* ID for response messages */
+    u_char resp_type;		/* hash algorithm for responses */
+    char *resp_name;		/* Our name to send with response */
+} chap_state;
+
+
+/******************
+*** PUBLIC DATA ***
+******************/
+extern chap_state chap[];
+
+extern struct protent chap_protent;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+void ChapAuthWithPeer (int, char *, int);
+void ChapAuthPeer (int, char *, int);
+
+#endif /* CHAP_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/chpms.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/chpms.c
new file mode 100644
index 0000000..3064344
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/chpms.c
@@ -0,0 +1,398 @@
+/*** WARNING - THIS CODE HAS NOT BEEN FINISHED! ***/
+/*****************************************************************************
+* chpms.c - Network MicroSoft Challenge Handshake Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 by Global Election Systems Inc.  All rights reserved.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-08 Guy Lancaster , Global Election Systems Inc.
+*	Original based on BSD chap_ms.c.
+*****************************************************************************/
+/*
+ * chap_ms.c - Microsoft MS-CHAP compatible implementation.
+ *
+ * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited.
+ * http://www.strataware.com/
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Eric Rosenquist.  The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+/*
+ * Modifications by Lauri Pesonen / lpesonen@clinet.fi, april 1997
+ *
+ *   Implemented LANManager type password response to MS-CHAP challenges.
+ *   Now pppd provides both NT style and LANMan style blocks, and the
+ *   prefered is set by option "ms-lanman". Default is to use NT.
+ *   The hash text (StdText) was taken from Win95 RASAPI32.DLL.
+ *
+ *   You should also use DOMAIN\\USERNAME as described in README.MSCHAP80
+ */
+
+#define USE_CRYPT
+
+
+#include "ppp.h"
+
+#if MSCHAP_SUPPORT > 0
+
+#include "md4.h"
+#ifndef USE_CRYPT
+#include "des.h"
+#endif
+#include "chap.h"
+#include "chpms.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+typedef struct {
+    u_char LANManResp[24];
+    u_char NTResp[24];
+    u_char UseNT;		/* If 1, ignore the LANMan response field */
+} MS_ChapResponse;
+/* We use MS_CHAP_RESPONSE_LEN, rather than sizeof(MS_ChapResponse),
+   in case this struct gets padded. */
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+
+/* XXX Don't know what to do with these. */
+extern void setkey(const char *);
+extern void encrypt(char *, int);
+
+static void	DesEncrypt (u_char *, u_char *, u_char *);
+static void	MakeKey (u_char *, u_char *);
+
+#ifdef USE_CRYPT
+static void	Expand (u_char *, u_char *);
+static void	Collapse (u_char *, u_char *);
+#endif
+
+static void ChallengeResponse(
+	u_char *challenge,	/* IN   8 octets */
+	u_char *pwHash,		/* IN  16 octets */
+	u_char *response	/* OUT 24 octets */
+);
+static void ChapMS_NT(
+	char *rchallenge,
+	int rchallenge_len,
+	char *secret,
+	int secret_len,
+	MS_ChapResponse *response
+);
+static u_char Get7Bits(
+	u_char *input,
+	int startBit
+);
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+void ChapMS(
+	chap_state *cstate,
+	char *rchallenge,
+	int rchallenge_len,
+	char *secret,
+	int secret_len
+)
+{
+	MS_ChapResponse	response;
+#ifdef MSLANMAN
+	extern int ms_lanman;
+#endif
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "ChapMS: secret is '%.*s'\n", secret_len, secret));
+#endif
+	BZERO(&response, sizeof(response));
+	
+	/* Calculate both always */
+	ChapMS_NT(rchallenge, rchallenge_len, secret, secret_len, &response);
+	
+#ifdef MSLANMAN
+	ChapMS_LANMan(rchallenge, rchallenge_len, secret, secret_len, &response);
+	
+	/* prefered method is set by option  */
+	response.UseNT = !ms_lanman;
+#else
+	response.UseNT = 1;
+#endif
+	
+	BCOPY(&response, cstate->response, MS_CHAP_RESPONSE_LEN);
+	cstate->resp_length = MS_CHAP_RESPONSE_LEN;
+}
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+static void ChallengeResponse(
+	u_char *challenge,	/* IN   8 octets */
+	u_char *pwHash,		/* IN  16 octets */
+	u_char *response	/* OUT 24 octets */
+)
+{
+	char    ZPasswordHash[21];
+	
+	BZERO(ZPasswordHash, sizeof(ZPasswordHash));
+	BCOPY(pwHash, ZPasswordHash, 16);
+	
+#if 0
+	log_packet(ZPasswordHash, sizeof(ZPasswordHash), "ChallengeResponse - ZPasswordHash", LOG_DEBUG);
+#endif
+	
+	DesEncrypt(challenge, ZPasswordHash +  0, response + 0);
+	DesEncrypt(challenge, ZPasswordHash +  7, response + 8);
+	DesEncrypt(challenge, ZPasswordHash + 14, response + 16);
+	
+#if 0
+	log_packet(response, 24, "ChallengeResponse - response", LOG_DEBUG);
+#endif
+}
+
+
+#ifdef USE_CRYPT
+static void DesEncrypt(
+	u_char *clear,	/* IN  8 octets */
+	u_char *key,	/* IN  7 octets */
+	u_char *cipher	/* OUT 8 octets */
+)
+{
+	u_char des_key[8];
+	u_char crypt_key[66];
+	u_char des_input[66];
+	
+	MakeKey(key, des_key);
+	
+	Expand(des_key, crypt_key);
+	setkey(crypt_key);
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n",
+	       clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7]));
+#endif
+	
+	Expand(clear, des_input);
+	encrypt(des_input, 0);
+	Collapse(des_input, cipher);
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+	       cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7]));
+#endif
+}
+
+#else /* USE_CRYPT */
+
+static void DesEncrypt(
+	u_char *clear,	/* IN  8 octets */
+	u_char *key,	/* IN  7 octets */
+	u_char *cipher	/* OUT 8 octets */
+)
+{
+	des_cblock		des_key;
+	des_key_schedule	key_schedule;
+	
+	MakeKey(key, des_key);
+	
+	des_set_key(&des_key, key_schedule);
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n",
+	       clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7]));
+#endif
+	
+	des_ecb_encrypt((des_cblock *)clear, (des_cblock *)cipher, key_schedule, 1);
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+	       cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7]));
+#endif
+}
+
+#endif /* USE_CRYPT */
+
+
+static u_char Get7Bits(
+	u_char *input,
+	int startBit
+)
+{
+	register unsigned int	word;
+	
+	word  = (unsigned)input[startBit / 8] << 8;
+	word |= (unsigned)input[startBit / 8 + 1];
+	
+	word >>= 15 - (startBit % 8 + 7);
+	
+	return word & 0xFE;
+}
+
+#ifdef USE_CRYPT
+
+/* in == 8-byte string (expanded version of the 56-bit key)
+ * out == 64-byte string where each byte is either 1 or 0
+ * Note that the low-order "bit" is always ignored by by setkey()
+ */
+static void Expand(u_char *in, u_char *out)
+{
+	int j, c;
+	int i;
+	
+	for(i = 0; i < 64; in++){
+		c = *in;
+		for(j = 7; j >= 0; j--)
+			*out++ = (c >> j) & 01;
+		i += 8;
+	}
+}
+
+/* The inverse of Expand
+ */
+static void Collapse(u_char *in, u_char *out)
+{
+	int j;
+	int i;
+	unsigned int c;
+	
+	for (i = 0; i < 64; i += 8, out++) {
+		c = 0;
+		for (j = 7; j >= 0; j--, in++)
+			c |= *in << j;
+		*out = c & 0xff;
+	}
+}
+#endif
+
+static void MakeKey(
+	u_char *key,		/* IN  56 bit DES key missing parity bits */
+	u_char *des_key		/* OUT 64 bit DES key with parity bits added */
+)
+{
+	des_key[0] = Get7Bits(key,  0);
+	des_key[1] = Get7Bits(key,  7);
+	des_key[2] = Get7Bits(key, 14);
+	des_key[3] = Get7Bits(key, 21);
+	des_key[4] = Get7Bits(key, 28);
+	des_key[5] = Get7Bits(key, 35);
+	des_key[6] = Get7Bits(key, 42);
+	des_key[7] = Get7Bits(key, 49);
+	
+#ifndef USE_CRYPT
+	des_set_odd_parity((des_cblock *)des_key);
+#endif
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "MakeKey: 56-bit input : %02X%02X%02X%02X%02X%02X%02X\n",
+	       key[0], key[1], key[2], key[3], key[4], key[5], key[6]));
+	CHAPDEBUG((LOG_INFO, "MakeKey: 64-bit output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+	       des_key[0], des_key[1], des_key[2], des_key[3], des_key[4], des_key[5], des_key[6], des_key[7]));
+#endif
+}
+
+static void ChapMS_NT(
+	char *rchallenge,
+	int rchallenge_len,
+	char *secret,
+	int secret_len,
+	MS_ChapResponse *response
+)
+{
+	int			i;
+	MDstruct	md4Context;
+	u_char		unicodePassword[MAX_NT_PASSWORD * 2];
+	static int	low_byte_first = -1;
+	
+	/* Initialize the Unicode version of the secret (== password). */
+	/* This implicitly supports 8-bit ISO8859/1 characters. */
+	BZERO(unicodePassword, sizeof(unicodePassword));
+	for (i = 0; i < secret_len; i++)
+		unicodePassword[i * 2] = (u_char)secret[i];
+	
+	MDbegin(&md4Context);
+	MDupdate(&md4Context, unicodePassword, secret_len * 2 * 8);	/* Unicode is 2 bytes/char, *8 for bit count */
+	
+	if (low_byte_first == -1)
+		low_byte_first = (htons((unsigned short int)1) != 1);
+	if (low_byte_first == 0)
+		MDreverse((u_long *)&md4Context);  /*  sfb 961105 */
+	
+	MDupdate(&md4Context, NULL, 0);	/* Tell MD4 we're done */
+	
+	ChallengeResponse(rchallenge, (char *)md4Context.buffer, response->NTResp);
+}
+
+#ifdef MSLANMAN
+static u_char *StdText = (u_char *)"KGS!@#$%"; /* key from rasapi32.dll */
+
+static ChapMS_LANMan(
+	char *rchallenge,
+	int rchallenge_len,
+	char *secret,
+	int secret_len,
+	MS_ChapResponse	*response
+)
+{
+	int			i;
+	u_char		UcasePassword[MAX_NT_PASSWORD]; /* max is actually 14 */
+	u_char		PasswordHash[16];
+	
+	/* LANMan password is case insensitive */
+	BZERO(UcasePassword, sizeof(UcasePassword));
+	for (i = 0; i < secret_len; i++)
+		UcasePassword[i] = (u_char)toupper(secret[i]);
+	DesEncrypt( StdText, UcasePassword + 0, PasswordHash + 0 );
+	DesEncrypt( StdText, UcasePassword + 7, PasswordHash + 8 );
+	ChallengeResponse(rchallenge, PasswordHash, response->LANManResp);
+}
+#endif
+
+#endif /* MSCHAP_SUPPORT */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/chpms.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/chpms.h
new file mode 100644
index 0000000..0b30c65
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/chpms.h
@@ -0,0 +1,64 @@
+/*****************************************************************************
+* chpms.h - Network Microsoft Challenge Handshake Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-01-30 Guy Lancaster , Global Election Systems Inc.
+*	Original built from BSD network code.
+******************************************************************************/
+/*
+ * chap.h - Challenge Handshake Authentication Protocol definitions.
+ *
+ * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited.
+ * http://www.strataware.com/
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Eric Rosenquist.  The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: chpms.h,v 1.3 2004/02/07 00:30:03 likewise Exp $
+ */
+
+#ifndef CHPMS_H
+#define CHPMS_H
+
+#define MAX_NT_PASSWORD	256	/* Maximum number of (Unicode) chars in an NT password */
+
+void ChapMS (chap_state *, char *, int, char *, int);
+
+#endif /* CHPMS_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/fsm.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/fsm.c
new file mode 100644
index 0000000..6cad715
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/fsm.c
@@ -0,0 +1,838 @@
+/*****************************************************************************
+* fsm.c - Network Control Protocol Finite State Machine program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-01 Guy Lancaster , Global Election Systems Inc.
+*	Original based on BSD fsm.c.
+*****************************************************************************/
+/*
+ * fsm.c - {Link, IP} Control Protocol Finite State Machine.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+/*
+ * TODO:
+ * Randomize fsm id on link/init.
+ * Deal with variable outgoing MTU.
+ */
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "fsm.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+static void fsm_timeout (void *);
+static void fsm_rconfreq (fsm *, u_char, u_char *, int);
+static void fsm_rconfack (fsm *, int, u_char *, int);
+static void fsm_rconfnakrej (fsm *, int, int, u_char *, int);
+static void fsm_rtermreq (fsm *, int, u_char *, int);
+static void fsm_rtermack (fsm *);
+static void fsm_rcoderej (fsm *, u_char *, int);
+static void fsm_sconfreq (fsm *, int);
+
+#define PROTO_NAME(f)	((f)->callbacks->proto_name)
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+int peer_mru[NUM_PPP];
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+
+/*
+ * fsm_init - Initialize fsm.
+ *
+ * Initialize fsm state.
+ */
+void fsm_init(fsm *f)
+{
+	f->state = INITIAL;
+	f->flags = 0;
+	f->id = 0;				/* XXX Start with random id? */
+	f->timeouttime = FSM_DEFTIMEOUT;
+	f->maxconfreqtransmits = FSM_DEFMAXCONFREQS;
+	f->maxtermtransmits = FSM_DEFMAXTERMREQS;
+	f->maxnakloops = FSM_DEFMAXNAKLOOPS;
+	f->term_reason_len = 0;
+}
+
+
+/*
+ * fsm_lowerup - The lower layer is up.
+ */
+void fsm_lowerup(fsm *f)
+{
+	int oldState = f->state;
+
+	switch( f->state ){
+	case INITIAL:
+		f->state = CLOSED;
+		break;
+	
+	case STARTING:
+		if( f->flags & OPT_SILENT )
+			f->state = STOPPED;
+		else {
+			/* Send an initial configure-request */
+			fsm_sconfreq(f, 0);
+			f->state = REQSENT;
+		}
+	break;
+	
+	default:
+		FSMDEBUG((LOG_INFO, "%s: Up event in state %d!\n",
+				PROTO_NAME(f), f->state));
+	}
+	
+	FSMDEBUG((LOG_INFO, "%s: lowerup state %d -> %d\n",
+			PROTO_NAME(f), oldState, f->state));
+}
+
+
+/*
+ * fsm_lowerdown - The lower layer is down.
+ *
+ * Cancel all timeouts and inform upper layers.
+ */
+void fsm_lowerdown(fsm *f)
+{
+	int oldState = f->state;
+	
+	switch( f->state ){
+	case CLOSED:
+		f->state = INITIAL;
+		break;
+	
+	case STOPPED:
+		f->state = STARTING;
+		if( f->callbacks->starting )
+			(*f->callbacks->starting)(f);
+		break;
+	
+	case CLOSING:
+		f->state = INITIAL;
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		break;
+	
+	case STOPPING:
+	case REQSENT:
+	case ACKRCVD:
+	case ACKSENT:
+		f->state = STARTING;
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		break;
+	
+	case OPENED:
+		if( f->callbacks->down )
+			(*f->callbacks->down)(f);
+		f->state = STARTING;
+		break;
+	
+	default:
+		FSMDEBUG((LOG_INFO, "%s: Down event in state %d!\n",
+				PROTO_NAME(f), f->state));
+	}
+	
+	FSMDEBUG((LOG_INFO, "%s: lowerdown state %d -> %d\n",
+			PROTO_NAME(f), oldState, f->state));
+}
+
+
+/*
+ * fsm_open - Link is allowed to come up.
+ */
+void fsm_open(fsm *f)
+{
+	int oldState = f->state;
+	
+	switch( f->state ){
+		case INITIAL:
+			f->state = STARTING;
+			if( f->callbacks->starting )
+				(*f->callbacks->starting)(f);
+			break;
+		
+		case CLOSED:
+		if( f->flags & OPT_SILENT )
+			f->state = STOPPED;
+		else {
+			/* Send an initial configure-request */
+			fsm_sconfreq(f, 0);
+			f->state = REQSENT;
+		}
+		break;
+	
+	case CLOSING:
+		f->state = STOPPING;
+		/* fall through */
+	case STOPPED:
+	case OPENED:
+		if( f->flags & OPT_RESTART ){
+			fsm_lowerdown(f);
+			fsm_lowerup(f);
+		}
+		break;
+	}
+	
+	FSMDEBUG((LOG_INFO, "%s: open state %d -> %d\n",
+			PROTO_NAME(f), oldState, f->state));
+}
+
+
+/*
+ * fsm_close - Start closing connection.
+ *
+ * Cancel timeouts and either initiate close or possibly go directly to
+ * the CLOSED state.
+ */
+void fsm_close(fsm *f, char *reason)
+{
+	int oldState = f->state;
+	
+	f->term_reason = reason;
+	f->term_reason_len = (reason == NULL? 0: strlen(reason));
+	switch( f->state ){
+	case STARTING:
+		f->state = INITIAL;
+		break;
+	case STOPPED:
+		f->state = CLOSED;
+		break;
+	case STOPPING:
+		f->state = CLOSING;
+		break;
+	
+	case REQSENT:
+	case ACKRCVD:
+	case ACKSENT:
+	case OPENED:
+		if( f->state != OPENED )
+			UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		else if( f->callbacks->down )
+			(*f->callbacks->down)(f);	/* Inform upper layers we're down */
+		
+		/* Init restart counter, send Terminate-Request */
+		f->retransmits = f->maxtermtransmits;
+		fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+					(u_char *) f->term_reason, f->term_reason_len);
+		TIMEOUT(fsm_timeout, f, f->timeouttime);
+		--f->retransmits;
+		
+		f->state = CLOSING;
+		break;
+	}
+	
+	FSMDEBUG((LOG_INFO, "%s: close reason=%s state %d -> %d\n",
+			PROTO_NAME(f), reason, oldState, f->state));
+}
+
+
+/*
+ * fsm_sdata - Send some data.
+ *
+ * Used for all packets sent to our peer by this module.
+ */
+void fsm_sdata(
+	fsm *f,
+	u_char code, 
+	u_char id,
+	u_char *data,
+	int datalen
+)
+{
+	u_char *outp;
+	int outlen;
+	
+	/* Adjust length to be smaller than MTU */
+	outp = outpacket_buf[f->unit];
+	if (datalen > peer_mru[f->unit] - (int)HEADERLEN)
+		datalen = peer_mru[f->unit] - HEADERLEN;
+	if (datalen && data != outp + PPP_HDRLEN + HEADERLEN)
+		BCOPY(data, outp + PPP_HDRLEN + HEADERLEN, datalen);
+	outlen = datalen + HEADERLEN;
+	MAKEHEADER(outp, f->protocol);
+	PUTCHAR(code, outp);
+	PUTCHAR(id, outp);
+	PUTSHORT(outlen, outp);
+	pppWrite(f->unit, outpacket_buf[f->unit], outlen + PPP_HDRLEN);
+	FSMDEBUG((LOG_INFO, "fsm_sdata(%s): Sent code %d,%d,%d.\n",
+				PROTO_NAME(f), code, id, outlen));
+}
+
+
+/*
+ * fsm_input - Input packet.
+ */
+void fsm_input(fsm *f, u_char *inpacket, int l)
+{
+	u_char *inp = inpacket;
+	u_char code, id;
+	int len;
+	
+	/*
+	* Parse header (code, id and length).
+	* If packet too short, drop it.
+	*/
+	if (l < HEADERLEN) {
+		FSMDEBUG((LOG_WARNING, "fsm_input(%x): Rcvd short header.\n",
+					f->protocol));
+		return;
+	}
+	GETCHAR(code, inp);
+	GETCHAR(id, inp);
+	GETSHORT(len, inp);
+	if (len < HEADERLEN) {
+		FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd illegal length.\n",
+				f->protocol));
+		return;
+	}
+	if (len > l) {
+		FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd short packet.\n",
+				f->protocol));
+		return;
+	}
+	len -= HEADERLEN;		/* subtract header length */
+	
+	if( f->state == INITIAL || f->state == STARTING ){
+		FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd packet in state %d.\n",
+				f->protocol, f->state));
+		return;
+	}
+	FSMDEBUG((LOG_INFO, "fsm_input(%s):%d,%d,%d\n", PROTO_NAME(f), code, id, l));
+	/*
+	 * Action depends on code.
+	 */
+	switch (code) {
+	case CONFREQ:
+		fsm_rconfreq(f, id, inp, len);
+		break;
+	
+	case CONFACK:
+		fsm_rconfack(f, id, inp, len);
+		break;
+	
+	case CONFNAK:
+	case CONFREJ:
+		fsm_rconfnakrej(f, code, id, inp, len);
+		break;
+	
+	case TERMREQ:
+		fsm_rtermreq(f, id, inp, len);
+		break;
+	
+	case TERMACK:
+		fsm_rtermack(f);
+		break;
+	
+	case CODEREJ:
+		fsm_rcoderej(f, inp, len);
+		break;
+	
+	default:
+		if( !f->callbacks->extcode
+				|| !(*f->callbacks->extcode)(f, code, id, inp, len) )
+			fsm_sdata(f, CODEREJ, ++f->id, inpacket, len + HEADERLEN);
+		break;
+	}
+}
+
+
+/*
+ * fsm_protreject - Peer doesn't speak this protocol.
+ *
+ * Treat this as a catastrophic error (RXJ-).
+ */
+void fsm_protreject(fsm *f)
+{
+	switch( f->state ){
+	case CLOSING:
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		/* fall through */
+	case CLOSED:
+		f->state = CLOSED;
+		if( f->callbacks->finished )
+			(*f->callbacks->finished)(f);
+		break;
+	
+	case STOPPING:
+	case REQSENT:
+	case ACKRCVD:
+	case ACKSENT:
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		/* fall through */
+	case STOPPED:
+		f->state = STOPPED;
+		if( f->callbacks->finished )
+			(*f->callbacks->finished)(f);
+		break;
+	
+	case OPENED:
+		if( f->callbacks->down )
+			(*f->callbacks->down)(f);
+		
+		/* Init restart counter, send Terminate-Request */
+		f->retransmits = f->maxtermtransmits;
+		fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+					(u_char *) f->term_reason, f->term_reason_len);
+		TIMEOUT(fsm_timeout, f, f->timeouttime);
+		--f->retransmits;
+		
+		f->state = STOPPING;
+		break;
+	
+	default:
+		FSMDEBUG((LOG_INFO, "%s: Protocol-reject event in state %d!\n",
+					PROTO_NAME(f), f->state));
+	}
+}
+
+
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+
+/*
+ * fsm_timeout - Timeout expired.
+ */
+static void fsm_timeout(void *arg)
+{
+    fsm *f = (fsm *) arg;
+
+    switch (f->state) {
+    case CLOSING:
+    case STOPPING:
+		if( f->retransmits <= 0 ){
+		    FSMDEBUG((LOG_WARNING, "%s: timeout sending Terminate-Request state=%d\n",
+					   PROTO_NAME(f), f->state));
+		    /*
+		     * We've waited for an ack long enough.  Peer probably heard us.
+		     */
+		    f->state = (f->state == CLOSING)? CLOSED: STOPPED;
+		    if( f->callbacks->finished )
+			(*f->callbacks->finished)(f);
+		} else {
+		    FSMDEBUG((LOG_WARNING, "%s: timeout resending Terminate-Requests state=%d\n",
+					   PROTO_NAME(f), f->state));
+		    /* Send Terminate-Request */
+		    fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+			      (u_char *) f->term_reason, f->term_reason_len);
+		    TIMEOUT(fsm_timeout, f, f->timeouttime);
+		    --f->retransmits;
+		}
+		break;
+
+    case REQSENT:
+    case ACKRCVD:
+    case ACKSENT:
+		if (f->retransmits <= 0) {
+		    FSMDEBUG((LOG_WARNING, "%s: timeout sending Config-Requests state=%d\n",
+			   PROTO_NAME(f), f->state));
+		    f->state = STOPPED;
+		    if( (f->flags & OPT_PASSIVE) == 0 && f->callbacks->finished )
+				(*f->callbacks->finished)(f);
+	
+		} else {
+		    FSMDEBUG((LOG_WARNING, "%s: timeout resending Config-Request state=%d\n",
+			   PROTO_NAME(f), f->state));
+		    /* Retransmit the configure-request */
+		    if (f->callbacks->retransmit)
+				(*f->callbacks->retransmit)(f);
+		    fsm_sconfreq(f, 1);		/* Re-send Configure-Request */
+		    if( f->state == ACKRCVD )
+				f->state = REQSENT;
+		}
+		break;
+
+    default:
+		FSMDEBUG((LOG_INFO, "%s: Timeout event in state %d!\n",
+				  PROTO_NAME(f), f->state));
+	    }
+}
+
+
+/*
+ * fsm_rconfreq - Receive Configure-Request.
+ */
+static void fsm_rconfreq(fsm *f, u_char id, u_char *inp, int len)
+{
+	int code, reject_if_disagree;
+	
+	FSMDEBUG((LOG_INFO, "fsm_rconfreq(%s): Rcvd id %d state=%d\n", 
+				PROTO_NAME(f), id, f->state));
+	switch( f->state ){
+	case CLOSED:
+		/* Go away, we're closed */
+		fsm_sdata(f, TERMACK, id, NULL, 0);
+		return;
+	case CLOSING:
+	case STOPPING:
+		return;
+	
+	case OPENED:
+		/* Go down and restart negotiation */
+		if( f->callbacks->down )
+			(*f->callbacks->down)(f);	/* Inform upper layers */
+		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
+		break;
+	
+	case STOPPED:
+		/* Negotiation started by our peer */
+		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
+		f->state = REQSENT;
+		break;
+	}
+	
+	/*
+	* Pass the requested configuration options
+	* to protocol-specific code for checking.
+	*/
+	if (f->callbacks->reqci){		/* Check CI */
+		reject_if_disagree = (f->nakloops >= f->maxnakloops);
+		code = (*f->callbacks->reqci)(f, inp, &len, reject_if_disagree);
+	} 
+	else if (len)
+		code = CONFREJ;			/* Reject all CI */
+	else
+		code = CONFACK;
+	
+	/* send the Ack, Nak or Rej to the peer */
+	fsm_sdata(f, (u_char)code, id, inp, len);
+	
+	if (code == CONFACK) {
+		if (f->state == ACKRCVD) {
+			UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+			f->state = OPENED;
+			if (f->callbacks->up)
+				(*f->callbacks->up)(f);	/* Inform upper layers */
+		} 
+		else
+			f->state = ACKSENT;
+		f->nakloops = 0;
+	} 
+	else {
+		/* we sent CONFACK or CONFREJ */
+		if (f->state != ACKRCVD)
+			f->state = REQSENT;
+		if( code == CONFNAK )
+			++f->nakloops;
+	}
+}
+
+
+/*
+ * fsm_rconfack - Receive Configure-Ack.
+ */
+static void fsm_rconfack(fsm *f, int id, u_char *inp, int len)
+{
+	FSMDEBUG((LOG_INFO, "fsm_rconfack(%s): Rcvd id %d state=%d\n",
+				PROTO_NAME(f), id, f->state));
+	
+	if (id != f->reqid || f->seen_ack)		/* Expected id? */
+		return;					/* Nope, toss... */
+	if( !(f->callbacks->ackci? (*f->callbacks->ackci)(f, inp, len):
+								(len == 0)) ){
+		/* Ack is bad - ignore it */
+		FSMDEBUG((LOG_INFO, "%s: received bad Ack (length %d)\n",
+					PROTO_NAME(f), len));
+		return;
+	}
+	f->seen_ack = 1;
+	
+	switch (f->state) {
+	case CLOSED:
+	case STOPPED:
+		fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+		break;
+	
+	case REQSENT:
+		f->state = ACKRCVD;
+		f->retransmits = f->maxconfreqtransmits;
+		break;
+	
+	case ACKRCVD:
+		/* Huh? an extra valid Ack? oh well... */
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		fsm_sconfreq(f, 0);
+		f->state = REQSENT;
+		break;
+	
+	case ACKSENT:
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		f->state = OPENED;
+		f->retransmits = f->maxconfreqtransmits;
+		if (f->callbacks->up)
+			(*f->callbacks->up)(f);	/* Inform upper layers */
+		break;
+	
+	case OPENED:
+		/* Go down and restart negotiation */
+		if (f->callbacks->down)
+			(*f->callbacks->down)(f);	/* Inform upper layers */
+		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
+		f->state = REQSENT;
+		break;
+	}
+}
+
+
+/*
+ * fsm_rconfnakrej - Receive Configure-Nak or Configure-Reject.
+ */
+static void fsm_rconfnakrej(fsm *f, int code, int id, u_char *inp, int len)
+{
+	int (*proc) (fsm *, u_char *, int);
+	int ret;
+	
+	FSMDEBUG((LOG_INFO, "fsm_rconfnakrej(%s): Rcvd id %d state=%d\n",
+				PROTO_NAME(f), id, f->state));
+	
+	if (id != f->reqid || f->seen_ack)	/* Expected id? */
+		return;				/* Nope, toss... */
+	proc = (code == CONFNAK)? f->callbacks->nakci: f->callbacks->rejci;
+	if (!proc || !(ret = proc(f, inp, len))) {
+		/* Nak/reject is bad - ignore it */
+		FSMDEBUG((LOG_INFO, "%s: received bad %s (length %d)\n",
+					PROTO_NAME(f), (code==CONFNAK? "Nak": "reject"), len));
+		return;
+	}
+	f->seen_ack = 1;
+	
+	switch (f->state) {
+	case CLOSED:
+	case STOPPED:
+		fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+		break;
+	
+	case REQSENT:
+	case ACKSENT:
+		/* They didn't agree to what we wanted - try another request */
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		if (ret < 0)
+			f->state = STOPPED;		/* kludge for stopping CCP */
+		else
+			fsm_sconfreq(f, 0);		/* Send Configure-Request */
+		break;
+	
+	case ACKRCVD:
+		/* Got a Nak/reject when we had already had an Ack?? oh well... */
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		fsm_sconfreq(f, 0);
+		f->state = REQSENT;
+		break;
+	
+	case OPENED:
+		/* Go down and restart negotiation */
+		if (f->callbacks->down)
+			(*f->callbacks->down)(f);	/* Inform upper layers */
+		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
+		f->state = REQSENT;
+		break;
+	}
+}
+
+
+/*
+ * fsm_rtermreq - Receive Terminate-Req.
+ */
+static void fsm_rtermreq(fsm *f, int id, u_char *p, int len)
+{
+	FSMDEBUG((LOG_INFO, "fsm_rtermreq(%s): Rcvd id %d state=%d\n",
+				PROTO_NAME(f), id, f->state));
+	
+	switch (f->state) {
+	case ACKRCVD:
+	case ACKSENT:
+		f->state = REQSENT;		/* Start over but keep trying */
+		break;
+	
+	case OPENED:
+		if (len > 0) {
+			FSMDEBUG((LOG_INFO, "%s terminated by peer (%x)\n", PROTO_NAME(f), p));
+		} else {
+			FSMDEBUG((LOG_INFO, "%s terminated by peer\n", PROTO_NAME(f)));
+		}
+		if (f->callbacks->down)
+			(*f->callbacks->down)(f);	/* Inform upper layers */
+		f->retransmits = 0;
+		f->state = STOPPING;
+		TIMEOUT(fsm_timeout, f, f->timeouttime);
+		break;
+	}
+	
+	fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+}
+
+
+/*
+ * fsm_rtermack - Receive Terminate-Ack.
+ */
+static void fsm_rtermack(fsm *f)
+{
+	FSMDEBUG((LOG_INFO, "fsm_rtermack(%s): state=%d\n", 
+				PROTO_NAME(f), f->state));
+	
+	switch (f->state) {
+	case CLOSING:
+		UNTIMEOUT(fsm_timeout, f);
+		f->state = CLOSED;
+		if( f->callbacks->finished )
+			(*f->callbacks->finished)(f);
+		break;
+	case STOPPING:
+		UNTIMEOUT(fsm_timeout, f);
+		f->state = STOPPED;
+		if( f->callbacks->finished )
+			(*f->callbacks->finished)(f);
+		break;
+	
+	case ACKRCVD:
+		f->state = REQSENT;
+		break;
+	
+	case OPENED:
+		if (f->callbacks->down)
+			(*f->callbacks->down)(f);	/* Inform upper layers */
+		fsm_sconfreq(f, 0);
+		break;
+	}
+}
+
+
+/*
+ * fsm_rcoderej - Receive an Code-Reject.
+ */
+static void fsm_rcoderej(fsm *f, u_char *inp, int len)
+{
+	u_char code, id;
+	
+	FSMDEBUG((LOG_INFO, "fsm_rcoderej(%s): state=%d\n", 
+				PROTO_NAME(f), f->state));
+	
+	if (len < HEADERLEN) {
+		FSMDEBUG((LOG_INFO, "fsm_rcoderej: Rcvd short Code-Reject packet!\n"));
+		return;
+	}
+	GETCHAR(code, inp);
+	GETCHAR(id, inp);
+	FSMDEBUG((LOG_WARNING, "%s: Rcvd Code-Reject for code %d, id %d\n",
+				PROTO_NAME(f), code, id));
+	
+	if( f->state == ACKRCVD )
+		f->state = REQSENT;
+}
+
+
+/*
+ * fsm_sconfreq - Send a Configure-Request.
+ */
+static void fsm_sconfreq(fsm *f, int retransmit)
+{
+	u_char *outp;
+	int cilen;
+	
+	if( f->state != REQSENT && f->state != ACKRCVD && f->state != ACKSENT ){
+		/* Not currently negotiating - reset options */
+		if( f->callbacks->resetci )
+			(*f->callbacks->resetci)(f);
+		f->nakloops = 0;
+		}
+	
+	if( !retransmit ){
+		/* New request - reset retransmission counter, use new ID */
+		f->retransmits = f->maxconfreqtransmits;
+		f->reqid = ++f->id;
+	}
+	
+	f->seen_ack = 0;
+	
+	/*
+	 * Make up the request packet
+	 */
+	outp = outpacket_buf[f->unit] + PPP_HDRLEN + HEADERLEN;
+	if( f->callbacks->cilen && f->callbacks->addci ){
+		cilen = (*f->callbacks->cilen)(f);
+		if( cilen > peer_mru[f->unit] - (int)HEADERLEN )
+			cilen = peer_mru[f->unit] - HEADERLEN;
+		if (f->callbacks->addci)
+			(*f->callbacks->addci)(f, outp, &cilen);
+	} else
+		cilen = 0;
+	
+	/* send the request to our peer */
+	fsm_sdata(f, CONFREQ, f->reqid, outp, cilen);
+	
+	/* start the retransmit timer */
+	--f->retransmits;
+	TIMEOUT(fsm_timeout, f, f->timeouttime);
+	
+	FSMDEBUG((LOG_INFO, "%s: sending Configure-Request, id %d\n",
+				PROTO_NAME(f), f->reqid));
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/fsm.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/fsm.h
new file mode 100644
index 0000000..4cca402
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/fsm.h
@@ -0,0 +1,187 @@
+/*****************************************************************************
+* fsm.h - Network Control Protocol Finite State Machine header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*	Original based on BSD code.
+*****************************************************************************/
+/*
+ * fsm.h - {Link, IP} Control Protocol Finite State Machine definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: fsm.h,v 1.1 2003/05/27 14:37:56 jani Exp $
+ */
+
+#ifndef FSM_H
+#define FSM_H
+
+
+/*****************************************************************************
+************************* PUBLIC DEFINITIONS *********************************
+*****************************************************************************/
+/*
+ * LCP Packet header = Code, id, length.
+ */
+#define HEADERLEN	(sizeof (u_char) + sizeof (u_char) + sizeof (u_short))
+
+
+/*
+ *  CP (LCP, IPCP, etc.) codes.
+ */
+#define CONFREQ		1		/* Configuration Request */
+#define CONFACK		2		/* Configuration Ack */
+#define CONFNAK		3		/* Configuration Nak */
+#define CONFREJ		4		/* Configuration Reject */
+#define TERMREQ		5		/* Termination Request */
+#define TERMACK		6		/* Termination Ack */
+#define CODEREJ		7		/* Code Reject */
+
+/*
+ * Link states.
+ */
+#define INITIAL		0		/* Down, hasn't been opened */
+#define STARTING	1		/* Down, been opened */
+#define CLOSED		2		/* Up, hasn't been opened */
+#define STOPPED		3		/* Open, waiting for down event */
+#define CLOSING		4		/* Terminating the connection, not open */
+#define STOPPING	5		/* Terminating, but open */
+#define REQSENT		6		/* We've sent a Config Request */
+#define ACKRCVD		7		/* We've received a Config Ack */
+#define ACKSENT		8		/* We've sent a Config Ack */
+#define OPENED		9		/* Connection available */
+
+
+/*
+ * Flags - indicate options controlling FSM operation
+ */
+#define OPT_PASSIVE	1		/* Don't die if we don't get a response */
+#define OPT_RESTART	2		/* Treat 2nd OPEN as DOWN, UP */
+#define OPT_SILENT	4		/* Wait for peer to speak first */
+
+
+/*****************************************************************************
+************************* PUBLIC DATA TYPES **********************************
+*****************************************************************************/
+/*
+ * Each FSM is described by an fsm structure and fsm callbacks.
+ */
+typedef struct fsm {
+    int unit;				/* Interface unit number */
+    u_short protocol;		/* Data Link Layer Protocol field value */
+    int state;				/* State */
+    int flags;				/* Contains option bits */
+    u_char id;				/* Current id */
+    u_char reqid;			/* Current request id */
+    u_char seen_ack;		/* Have received valid Ack/Nak/Rej to Req */
+    int timeouttime;		/* Timeout time in milliseconds */
+    int maxconfreqtransmits;/* Maximum Configure-Request transmissions */
+    int retransmits;		/* Number of retransmissions left */
+    int maxtermtransmits;	/* Maximum Terminate-Request transmissions */
+    int nakloops;			/* Number of nak loops since last ack */
+    int maxnakloops;		/* Maximum number of nak loops tolerated */
+    struct fsm_callbacks* callbacks;/* Callback routines */
+    char* term_reason;		/* Reason for closing protocol */
+    int term_reason_len;	/* Length of term_reason */
+} fsm;
+
+
+typedef struct fsm_callbacks {
+    void (*resetci)			/* Reset our Configuration Information */
+		(fsm*);
+    int  (*cilen)			/* Length of our Configuration Information */
+		(fsm*);
+    void (*addci) 			/* Add our Configuration Information */
+		(fsm*, u_char*, int*);
+    int  (*ackci)			/* ACK our Configuration Information */
+		(fsm*, u_char*, int);
+    int  (*nakci)			/* NAK our Configuration Information */
+		(fsm*, u_char*, int);
+    int  (*rejci)			/* Reject our Configuration Information */
+		(fsm*, u_char*, int);
+    int  (*reqci)			/* Request peer's Configuration Information */
+		(fsm*, u_char*, int*, int);
+    void (*up)				/* Called when fsm reaches OPENED state */
+		(fsm*);
+    void (*down)			/* Called when fsm leaves OPENED state */
+		(fsm*);
+    void (*starting)		/* Called when we want the lower layer */
+		(fsm*);
+    void (*finished)		/* Called when we don't want the lower layer */
+		(fsm*);
+    void (*protreject)		/* Called when Protocol-Reject received */
+		(int);
+    void (*retransmit)		/* Retransmission is necessary */
+		(fsm*);
+    int  (*extcode)			/* Called when unknown code received */
+		(fsm*, int, u_char, u_char*, int);
+    char *proto_name;		/* String name for protocol (for messages) */
+} fsm_callbacks;
+
+
+/*****************************************************************************
+*********************** PUBLIC DATA STRUCTURES *******************************
+*****************************************************************************/
+/*
+ * Variables
+ */
+extern int peer_mru[];		/* currently negotiated peer MRU (per unit) */
+
+
+/*****************************************************************************
+************************** PUBLIC FUNCTIONS **********************************
+*****************************************************************************/
+
+/*
+ * Prototypes
+ */
+void fsm_init (fsm*);
+void fsm_lowerup (fsm*);
+void fsm_lowerdown (fsm*);
+void fsm_open (fsm*);
+void fsm_close (fsm*, char*);
+void fsm_input (fsm*, u_char*, int);
+void fsm_protreject (fsm*);
+void fsm_sdata (fsm*, u_char, u_char, u_char*, int);
+
+
+#endif /* FSM_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/ipcp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/ipcp.c
new file mode 100644
index 0000000..ec3207a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/ipcp.c
@@ -0,0 +1,1377 @@
+/*****************************************************************************
+* ipcp.c - Network PPP IP Control Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-08 Guy Lancaster , Global Election Systems Inc.
+*	Original.
+*****************************************************************************/
+/*
+ * ipcp.c - PPP IP Control Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include 
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "auth.h"
+#include "fsm.h"
+#include "vj.h"
+#include "ipcp.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+/* #define OLD_CI_ADDRS 1 */	/* Support deprecated address negotiation. */
+
+/*
+ * Lengths of configuration options.
+ */
+#define CILEN_VOID	2
+#define CILEN_COMPRESS	4	/* min length for compression protocol opt. */
+#define CILEN_VJ	6	/* length for RFC1332 Van-Jacobson opt. */
+#define CILEN_ADDR	6	/* new-style single address option */
+#define CILEN_ADDRS	10	/* old-style dual address option */
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Callbacks for fsm code.  (CI = Configuration Information)
+ */
+static void ipcp_resetci (fsm *);	/* Reset our CI */
+static int  ipcp_cilen (fsm *);	        /* Return length of our CI */
+static void ipcp_addci (fsm *, u_char *, int *); /* Add our CI */
+static int  ipcp_ackci (fsm *, u_char *, int);	/* Peer ack'd our CI */
+static int  ipcp_nakci (fsm *, u_char *, int);	/* Peer nak'd our CI */
+static int  ipcp_rejci (fsm *, u_char *, int);	/* Peer rej'd our CI */
+static int  ipcp_reqci (fsm *, u_char *, int *, int); /* Rcv CI */
+static void ipcp_up (fsm *);		/* We're UP */
+static void ipcp_down (fsm *);		/* We're DOWN */
+#if 0
+static void ipcp_script (fsm *, char *); /* Run an up/down script */
+#endif
+static void ipcp_finished (fsm *);	/* Don't need lower layer */
+
+/*
+ * Protocol entry points from main code.
+ */
+static void ipcp_init (int);
+static void ipcp_open (int);
+static void ipcp_close (int, char *);
+static void ipcp_lowerup (int);
+static void ipcp_lowerdown (int);
+static void ipcp_input (int, u_char *, int);
+static void ipcp_protrej (int);
+
+static void ipcp_clear_addrs (int);
+
+#define CODENAME(x)	((x) == CONFACK ? "ACK" : \
+			 (x) == CONFNAK ? "NAK" : "REJ")
+
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+/* global vars */
+ipcp_options ipcp_wantoptions[NUM_PPP];	/* Options that we want to request */
+ipcp_options ipcp_gotoptions[NUM_PPP];	/* Options that peer ack'd */
+ipcp_options ipcp_allowoptions[NUM_PPP];	/* Options we allow peer to request */
+ipcp_options ipcp_hisoptions[NUM_PPP];	/* Options that we ack'd */
+
+fsm ipcp_fsm[NUM_PPP];		/* IPCP fsm structure */
+
+struct protent ipcp_protent = {
+    PPP_IPCP,
+    ipcp_init,
+    ipcp_input,
+    ipcp_protrej,
+    ipcp_lowerup,
+    ipcp_lowerdown,
+    ipcp_open,
+    ipcp_close,
+#if 0
+    ipcp_printpkt,
+    NULL,
+#endif
+    1,
+    "IPCP",
+#if 0
+    ip_check_options,
+    NULL,
+    ip_active_pkt
+#endif
+};
+
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+/* local vars */
+static int cis_received[NUM_PPP];		/* # Conf-Reqs received */
+static int default_route_set[NUM_PPP];	/* Have set up a default route */
+
+static fsm_callbacks ipcp_callbacks = { /* IPCP callback routines */
+    ipcp_resetci,		/* Reset our Configuration Information */
+    ipcp_cilen,			/* Length of our Configuration Information */
+    ipcp_addci,			/* Add our Configuration Information */
+    ipcp_ackci,			/* ACK our Configuration Information */
+    ipcp_nakci,			/* NAK our Configuration Information */
+    ipcp_rejci,			/* Reject our Configuration Information */
+    ipcp_reqci,			/* Request peer's Configuration Information */
+    ipcp_up,			/* Called when fsm reaches OPENED state */
+    ipcp_down,			/* Called when fsm leaves OPENED state */
+    NULL,				/* Called when we want the lower layer up */
+    ipcp_finished,		/* Called when we want the lower layer down */
+    NULL,				/* Called when Protocol-Reject received */
+    NULL,				/* Retransmission is necessary */
+    NULL,				/* Called to handle protocol-specific codes */
+    "IPCP"				/* String name of protocol */
+};
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+
+/*
+ * Non-standard inet_ntoa left here for compat with original ppp
+ * sources. Assumes u32_t instead of struct in_addr.
+ */ 
+
+char * _inet_ntoa(u32_t n)
+{
+	struct in_addr ia;
+	ia.s_addr = n;
+	return inet_ntoa(ia);
+}
+
+#define inet_ntoa _inet_ntoa
+
+/*
+ * ipcp_init - Initialize IPCP.
+ */
+static void ipcp_init(int unit)
+{
+	fsm *f = &ipcp_fsm[unit];
+	ipcp_options *wo = &ipcp_wantoptions[unit];
+	ipcp_options *ao = &ipcp_allowoptions[unit];
+	
+	f->unit = unit;
+	f->protocol = PPP_IPCP;
+	f->callbacks = &ipcp_callbacks;
+	fsm_init(&ipcp_fsm[unit]);
+	
+	memset(wo, 0, sizeof(*wo));
+	memset(ao, 0, sizeof(*ao));
+	
+	wo->neg_addr = 1;
+	wo->ouraddr = 0;
+#if VJ_SUPPORT > 0
+	wo->neg_vj = 1;
+#else
+	wo->neg_vj = 0;
+#endif
+	wo->vj_protocol = IPCP_VJ_COMP;
+	wo->maxslotindex = MAX_SLOTS - 1;
+	wo->cflag = 0;
+	
+	wo->default_route = 1;
+	
+	ao->neg_addr = 1;
+#if VJ_SUPPORT > 0
+	ao->neg_vj = 1;
+#else
+	ao->neg_vj = 0;
+#endif
+	ao->maxslotindex = MAX_SLOTS - 1;
+	ao->cflag = 1;
+	
+	ao->default_route = 1;
+}
+
+
+/*
+ * ipcp_open - IPCP is allowed to come up.
+ */
+static void ipcp_open(int unit)
+{
+	fsm_open(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_close - Take IPCP down.
+ */
+static void ipcp_close(int unit, char *reason)
+{
+	fsm_close(&ipcp_fsm[unit], reason);
+}
+
+
+/*
+ * ipcp_lowerup - The lower layer is up.
+ */
+static void ipcp_lowerup(int unit)
+{
+	fsm_lowerup(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_lowerdown - The lower layer is down.
+ */
+static void ipcp_lowerdown(int unit)
+{
+	fsm_lowerdown(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_input - Input IPCP packet.
+ */
+static void ipcp_input(int unit, u_char *p, int len)
+{
+	fsm_input(&ipcp_fsm[unit], p, len);
+}
+
+
+/*
+ * ipcp_protrej - A Protocol-Reject was received for IPCP.
+ *
+ * Pretend the lower layer went down, so we shut up.
+ */
+static void ipcp_protrej(int unit)
+{
+	fsm_lowerdown(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_resetci - Reset our CI.
+ */
+static void ipcp_resetci(fsm *f)
+{
+	ipcp_options *wo = &ipcp_wantoptions[f->unit];
+	
+	wo->req_addr = wo->neg_addr && ipcp_allowoptions[f->unit].neg_addr;
+	if (wo->ouraddr == 0)
+		wo->accept_local = 1;
+	if (wo->hisaddr == 0)
+		wo->accept_remote = 1;
+	/* Request DNS addresses from the peer */
+	wo->req_dns1 = ppp_settings.usepeerdns;
+	wo->req_dns2 = ppp_settings.usepeerdns;
+	ipcp_gotoptions[f->unit] = *wo;
+	cis_received[f->unit] = 0;
+}
+
+
+/*
+ * ipcp_cilen - Return length of our CI.
+ */
+static int ipcp_cilen(fsm *f)
+{
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	ipcp_options *wo = &ipcp_wantoptions[f->unit];
+	ipcp_options *ho = &ipcp_hisoptions[f->unit];
+	
+#define LENCIVJ(neg, old)	(neg ? (old? CILEN_COMPRESS : CILEN_VJ) : 0)
+#define LENCIADDR(neg, old)	(neg ? (old? CILEN_ADDRS : CILEN_ADDR) : 0)
+#define LENCIDNS(neg)		(neg ? (CILEN_ADDR) : 0)
+	
+	/*
+	 * First see if we want to change our options to the old
+	 * forms because we have received old forms from the peer.
+	 */
+	if (wo->neg_addr && !go->neg_addr && !go->old_addrs) {
+		/* use the old style of address negotiation */
+		go->neg_addr = 1;
+		go->old_addrs = 1;
+	}
+	if (wo->neg_vj && !go->neg_vj && !go->old_vj) {
+		/* try an older style of VJ negotiation */
+		if (cis_received[f->unit] == 0) {
+			/* keep trying the new style until we see some CI from the peer */
+			go->neg_vj = 1;
+		} else {
+			/* use the old style only if the peer did */
+			if (ho->neg_vj && ho->old_vj) {
+				go->neg_vj = 1;
+				go->old_vj = 1;
+				go->vj_protocol = ho->vj_protocol;
+			}
+		}
+	}
+	
+	return (LENCIADDR(go->neg_addr, go->old_addrs)
+			+ LENCIVJ(go->neg_vj, go->old_vj) +
+			LENCIDNS(go->req_dns1) +
+			LENCIDNS(go->req_dns2));
+}
+
+
+/*
+ * ipcp_addci - Add our desired CIs to a packet.
+ */
+static void ipcp_addci(fsm *f, u_char *ucp, int *lenp)
+{
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	int len = *lenp;
+	
+#define ADDCIVJ(opt, neg, val, old, maxslotindex, cflag) \
+	if (neg) { \
+		int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \
+		if (len >= vjlen) { \
+			PUTCHAR(opt, ucp); \
+			PUTCHAR(vjlen, ucp); \
+			PUTSHORT(val, ucp); \
+			if (!old) { \
+				PUTCHAR(maxslotindex, ucp); \
+				PUTCHAR(cflag, ucp); \
+			} \
+			len -= vjlen; \
+		} else \
+			neg = 0; \
+	}
+	
+#define ADDCIADDR(opt, neg, old, val1, val2) \
+	if (neg) { \
+		int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \
+		if (len >= addrlen) { \
+			u32_t l; \
+			PUTCHAR(opt, ucp); \
+			PUTCHAR(addrlen, ucp); \
+			l = ntohl(val1); \
+			PUTLONG(l, ucp); \
+			if (old) { \
+				l = ntohl(val2); \
+				PUTLONG(l, ucp); \
+			} \
+			len -= addrlen; \
+		} else \
+			neg = 0; \
+	}
+
+#define ADDCIDNS(opt, neg, addr) \
+	if (neg) { \
+		if (len >= CILEN_ADDR) { \
+			u32_t l; \
+			PUTCHAR(opt, ucp); \
+			PUTCHAR(CILEN_ADDR, ucp); \
+			l = ntohl(addr); \
+			PUTLONG(l, ucp); \
+			len -= CILEN_ADDR; \
+		} else \
+			neg = 0; \
+	}
+	
+	ADDCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr,
+			  go->old_addrs, go->ouraddr, go->hisaddr);
+	
+	ADDCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj,
+			go->maxslotindex, go->cflag);
+	
+	ADDCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]);
+
+	ADDCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]);
+
+	*lenp -= len;
+}
+
+
+/*
+ * ipcp_ackci - Ack our CIs.
+ *
+ * Returns:
+ *	0 - Ack was bad.
+ *	1 - Ack was good.
+ */
+static int ipcp_ackci(fsm *f, u_char *p, int len)
+{
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	u_short cilen, citype, cishort;
+	u32_t cilong;
+	u_char cimaxslotindex, cicflag;
+	
+	/*
+	 * CIs must be in exactly the same order that we sent...
+	 * Check packet length and CI length at each step.
+	 * If we find any deviations, then this packet is bad.
+	 */
+	
+#define ACKCIVJ(opt, neg, val, old, maxslotindex, cflag) \
+	if (neg) { \
+		int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \
+		if ((len -= vjlen) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != vjlen || \
+				citype != opt)  \
+			goto bad; \
+		GETSHORT(cishort, p); \
+		if (cishort != val) \
+			goto bad; \
+		if (!old) { \
+			GETCHAR(cimaxslotindex, p); \
+			if (cimaxslotindex != maxslotindex) \
+				goto bad; \
+			GETCHAR(cicflag, p); \
+			if (cicflag != cflag) \
+				goto bad; \
+		} \
+	}
+	
+#define ACKCIADDR(opt, neg, old, val1, val2) \
+	if (neg) { \
+		int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \
+		u32_t l; \
+		if ((len -= addrlen) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != addrlen || \
+				citype != opt) \
+			goto bad; \
+		GETLONG(l, p); \
+		cilong = htonl(l); \
+		if (val1 != cilong) \
+			goto bad; \
+		if (old) { \
+			GETLONG(l, p); \
+			cilong = htonl(l); \
+			if (val2 != cilong) \
+				goto bad; \
+		} \
+	}
+
+#define ACKCIDNS(opt, neg, addr) \
+	if (neg) { \
+		u32_t l; \
+		if ((len -= CILEN_ADDR) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_ADDR || \
+				citype != opt) \
+			goto bad; \
+		GETLONG(l, p); \
+		cilong = htonl(l); \
+		if (addr != cilong) \
+			goto bad; \
+	}
+	
+	ACKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr,
+			  go->old_addrs, go->ouraddr, go->hisaddr);
+	
+	ACKCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj,
+			go->maxslotindex, go->cflag);
+	
+	ACKCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]);
+
+	ACKCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]);
+
+	/*
+	 * If there are any remaining CIs, then this packet is bad.
+	 */
+	if (len != 0)
+		goto bad;
+	return (1);
+	
+bad:
+	IPCPDEBUG((LOG_INFO, "ipcp_ackci: received bad Ack!\n"));
+	return (0);
+}
+
+/*
+ * ipcp_nakci - Peer has sent a NAK for some of our CIs.
+ * This should not modify any state if the Nak is bad
+ * or if IPCP is in the OPENED state.
+ *
+ * Returns:
+ *	0 - Nak was bad.
+ *	1 - Nak was good.
+ */
+static int ipcp_nakci(fsm *f, u_char *p, int len)
+{
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	u_char cimaxslotindex, cicflag;
+	u_char citype, cilen, *next;
+	u_short cishort;
+	u32_t ciaddr1, ciaddr2, l, cidnsaddr;
+	ipcp_options no;		/* options we've seen Naks for */
+	ipcp_options try;		/* options to request next time */
+	
+	BZERO(&no, sizeof(no));
+	try = *go;
+	
+	/*
+	 * Any Nak'd CIs must be in exactly the same order that we sent.
+	 * Check packet length and CI length at each step.
+	 * If we find any deviations, then this packet is bad.
+	 */
+#define NAKCIADDR(opt, neg, old, code) \
+	if (go->neg && \
+			len >= (cilen = (old? CILEN_ADDRS: CILEN_ADDR)) && \
+			p[1] == cilen && \
+			p[0] == opt) { \
+		len -= cilen; \
+		INCPTR(2, p); \
+		GETLONG(l, p); \
+		ciaddr1 = htonl(l); \
+		if (old) { \
+			GETLONG(l, p); \
+			ciaddr2 = htonl(l); \
+			no.old_addrs = 1; \
+		} else \
+			ciaddr2 = 0; \
+		no.neg = 1; \
+		code \
+	}
+	
+#define NAKCIVJ(opt, neg, code) \
+	if (go->neg && \
+			((cilen = p[1]) == CILEN_COMPRESS || cilen == CILEN_VJ) && \
+			len >= cilen && \
+			p[0] == opt) { \
+		len -= cilen; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		no.neg = 1; \
+		code \
+	}
+	
+#define NAKCIDNS(opt, neg, code) \
+	if (go->neg && \
+			((cilen = p[1]) == CILEN_ADDR) && \
+			len >= cilen && \
+			p[0] == opt) { \
+		len -= cilen; \
+		INCPTR(2, p); \
+		GETLONG(l, p); \
+		cidnsaddr = htonl(l); \
+		no.neg = 1; \
+		code \
+	}
+	
+	/*
+	 * Accept the peer's idea of {our,his} address, if different
+	 * from our idea, only if the accept_{local,remote} flag is set.
+	 */
+	NAKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr, go->old_addrs,
+	  if (go->accept_local && ciaddr1) { /* Do we know our address? */
+		  try.ouraddr = ciaddr1;
+		  IPCPDEBUG((LOG_INFO, "local IP address %s\n",
+			     inet_ntoa(ciaddr1)));
+	  }
+	  if (go->accept_remote && ciaddr2) { /* Does he know his? */
+		  try.hisaddr = ciaddr2;
+		  IPCPDEBUG((LOG_INFO, "remote IP address %s\n",
+			     inet_ntoa(ciaddr2)));
+	  }
+	);
+	
+	/*
+	 * Accept the peer's value of maxslotindex provided that it
+	 * is less than what we asked for.  Turn off slot-ID compression
+	 * if the peer wants.  Send old-style compress-type option if
+	 * the peer wants.
+	 */
+	NAKCIVJ(CI_COMPRESSTYPE, neg_vj,
+		if (cilen == CILEN_VJ) {
+			GETCHAR(cimaxslotindex, p);
+			GETCHAR(cicflag, p);
+			if (cishort == IPCP_VJ_COMP) {
+				try.old_vj = 0;
+				if (cimaxslotindex < go->maxslotindex)
+					try.maxslotindex = cimaxslotindex;
+				if (!cicflag)
+					try.cflag = 0;
+			} else {
+				try.neg_vj = 0;
+			}
+		} else {
+			if (cishort == IPCP_VJ_COMP || cishort == IPCP_VJ_COMP_OLD) {
+				try.old_vj = 1;
+				try.vj_protocol = cishort;
+			} else {
+				try.neg_vj = 0;
+			}
+		}
+	);
+	
+	NAKCIDNS(CI_MS_DNS1, req_dns1,
+			try.dnsaddr[0] = cidnsaddr;
+		  	IPCPDEBUG((LOG_INFO, "primary DNS address %s\n", inet_ntoa(cidnsaddr)));
+			);
+
+	NAKCIDNS(CI_MS_DNS2, req_dns2,
+			try.dnsaddr[1] = cidnsaddr;
+		  	IPCPDEBUG((LOG_INFO, "secondary DNS address %s\n", inet_ntoa(cidnsaddr)));
+			);
+
+	/*
+	* There may be remaining CIs, if the peer is requesting negotiation
+	* on an option that we didn't include in our request packet.
+	* If they want to negotiate about IP addresses, we comply.
+	* If they want us to ask for compression, we refuse.
+	*/
+	while (len > CILEN_VOID) {
+		GETCHAR(citype, p);
+		GETCHAR(cilen, p);
+		if( (len -= cilen) < 0 )
+			goto bad;
+		next = p + cilen - 2;
+		
+		switch (citype) {
+		case CI_COMPRESSTYPE:
+			if (go->neg_vj || no.neg_vj ||
+					(cilen != CILEN_VJ && cilen != CILEN_COMPRESS))
+				goto bad;
+			no.neg_vj = 1;
+			break;
+		case CI_ADDRS:
+			if ((go->neg_addr && go->old_addrs) || no.old_addrs
+					|| cilen != CILEN_ADDRS)
+				goto bad;
+			try.neg_addr = 1;
+			try.old_addrs = 1;
+			GETLONG(l, p);
+			ciaddr1 = htonl(l);
+			if (ciaddr1 && go->accept_local)
+				try.ouraddr = ciaddr1;
+			GETLONG(l, p);
+			ciaddr2 = htonl(l);
+			if (ciaddr2 && go->accept_remote)
+				try.hisaddr = ciaddr2;
+			no.old_addrs = 1;
+			break;
+		case CI_ADDR:
+			if (go->neg_addr || no.neg_addr || cilen != CILEN_ADDR)
+				goto bad;
+			try.old_addrs = 0;
+			GETLONG(l, p);
+			ciaddr1 = htonl(l);
+			if (ciaddr1 && go->accept_local)
+				try.ouraddr = ciaddr1;
+			if (try.ouraddr != 0)
+				try.neg_addr = 1;
+			no.neg_addr = 1;
+			break;
+		}
+		p = next;
+	}
+	
+	/* If there is still anything left, this packet is bad. */
+	if (len != 0)
+		goto bad;
+	
+	/*
+	 * OK, the Nak is good.  Now we can update state.
+	 */
+	if (f->state != OPENED)
+		*go = try;
+	
+	return 1;
+	
+bad:
+	IPCPDEBUG((LOG_INFO, "ipcp_nakci: received bad Nak!\n"));
+	return 0;
+}
+
+
+/*
+ * ipcp_rejci - Reject some of our CIs.
+ */
+static int ipcp_rejci(fsm *f, u_char *p, int len)
+{
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	u_char cimaxslotindex, ciflag, cilen;
+	u_short cishort;
+	u32_t cilong;
+	ipcp_options try;		/* options to request next time */
+	
+	try = *go;
+	/*
+	 * Any Rejected CIs must be in exactly the same order that we sent.
+	 * Check packet length and CI length at each step.
+	 * If we find any deviations, then this packet is bad.
+	 */
+#define REJCIADDR(opt, neg, old, val1, val2) \
+	if (go->neg && \
+			len >= (cilen = old? CILEN_ADDRS: CILEN_ADDR) && \
+			p[1] == cilen && \
+			p[0] == opt) { \
+		u32_t l; \
+		len -= cilen; \
+		INCPTR(2, p); \
+		GETLONG(l, p); \
+		cilong = htonl(l); \
+		/* Check rejected value. */ \
+		if (cilong != val1) \
+			goto bad; \
+		if (old) { \
+			GETLONG(l, p); \
+			cilong = htonl(l); \
+			/* Check rejected value. */ \
+			if (cilong != val2) \
+				goto bad; \
+		} \
+		try.neg = 0; \
+	}
+	
+#define REJCIVJ(opt, neg, val, old, maxslot, cflag) \
+	if (go->neg && \
+			p[1] == (old? CILEN_COMPRESS : CILEN_VJ) && \
+			len >= p[1] && \
+			p[0] == opt) { \
+		len -= p[1]; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		/* Check rejected value. */  \
+		if (cishort != val) \
+			goto bad; \
+		if (!old) { \
+			GETCHAR(cimaxslotindex, p); \
+			if (cimaxslotindex != maxslot) \
+				goto bad; \
+			GETCHAR(ciflag, p); \
+			if (ciflag != cflag) \
+				goto bad; \
+		} \
+		try.neg = 0; \
+	}
+	
+#define REJCIDNS(opt, neg, dnsaddr) \
+	if (go->neg && \
+			((cilen = p[1]) == CILEN_ADDR) && \
+			len >= cilen && \
+			p[0] == opt) { \
+		u32_t l; \
+		len -= cilen; \
+		INCPTR(2, p); \
+		GETLONG(l, p); \
+		cilong = htonl(l); \
+		/* Check rejected value. */ \
+		if (cilong != dnsaddr) \
+			goto bad; \
+		try.neg = 0; \
+	}
+
+	REJCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr,
+			  go->old_addrs, go->ouraddr, go->hisaddr);
+	
+	REJCIVJ(CI_COMPRESSTYPE, neg_vj, go->vj_protocol, go->old_vj,
+			go->maxslotindex, go->cflag);
+	
+	REJCIDNS(CI_MS_DNS1, req_dns1, go->dnsaddr[0]);
+
+	REJCIDNS(CI_MS_DNS2, req_dns2, go->dnsaddr[1]);
+
+	/*
+	 * If there are any remaining CIs, then this packet is bad.
+	 */
+	if (len != 0)
+		goto bad;
+	/*
+	 * Now we can update state.
+	 */
+	if (f->state != OPENED)
+		*go = try;
+	return 1;
+	
+bad:
+	IPCPDEBUG((LOG_INFO, "ipcp_rejci: received bad Reject!\n"));
+	return 0;
+}
+
+
+/*
+ * ipcp_reqci - Check the peer's requested CIs and send appropriate response.
+ *
+ * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified
+ * appropriately.  If reject_if_disagree is non-zero, doesn't return
+ * CONFNAK; returns CONFREJ if it can't return CONFACK.
+ */
+static int ipcp_reqci(
+	fsm *f,
+	u_char *inp,		/* Requested CIs */
+	int *len,			/* Length of requested CIs */
+	int reject_if_disagree
+)
+{
+	ipcp_options *wo = &ipcp_wantoptions[f->unit];
+	ipcp_options *ho = &ipcp_hisoptions[f->unit];
+	ipcp_options *ao = &ipcp_allowoptions[f->unit];
+#ifdef OLD_CI_ADDRS
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+#endif
+	u_char *cip, *next;				/* Pointer to current and next CIs */
+	u_short cilen, citype;			/* Parsed len, type */
+	u_short cishort;				/* Parsed short value */
+	u32_t tl, ciaddr1;			/* Parsed address values */
+#ifdef OLD_CI_ADDRS
+	u32_t ciaddr2;				/* Parsed address values */
+#endif
+	int rc = CONFACK;				/* Final packet return code */
+	int orc;						/* Individual option return code */
+	u_char *p;						/* Pointer to next char to parse */
+	u_char *ucp = inp;				/* Pointer to current output char */
+	int l = *len;					/* Length left */
+	u_char maxslotindex, cflag;
+	int d;
+	
+	cis_received[f->unit] = 1;
+	
+	/*
+	 * Reset all his options.
+	 */
+	BZERO(ho, sizeof(*ho));
+	
+	/*
+	 * Process all his options.
+	 */
+	next = inp;
+	while (l) {
+		orc = CONFACK;				/* Assume success */
+		cip = p = next;				/* Remember begining of CI */
+		if (l < 2 ||				/* Not enough data for CI header or */
+				p[1] < 2 ||			/*  CI length too small or */
+				p[1] > l) {			/*  CI length too big? */
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: bad CI length!\n"));
+			orc = CONFREJ;			/* Reject bad CI */
+			cilen = l;				/* Reject till end of packet */
+			l = 0;					/* Don't loop again */
+			goto endswitch;
+		}
+		GETCHAR(citype, p);			/* Parse CI type */
+		GETCHAR(cilen, p);			/* Parse CI length */
+		l -= cilen;					/* Adjust remaining length */
+		next += cilen;				/* Step to next CI */
+
+		switch (citype) {			/* Check CI type */
+#ifdef OLD_CI_ADDRS /* Need to save space... */
+		case CI_ADDRS:
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: received ADDRS\n"));
+			if (!ao->neg_addr ||
+					cilen != CILEN_ADDRS) {	/* Check CI length */
+				orc = CONFREJ;		/* Reject CI */
+				break;
+			}
+			
+			/*
+			 * If he has no address, or if we both have his address but
+			 * disagree about it, then NAK it with our idea.
+			 * In particular, if we don't know his address, but he does,
+			 * then accept it.
+			 */
+			GETLONG(tl, p);		/* Parse source address (his) */
+			ciaddr1 = htonl(tl);
+			IPCPDEBUG((LOG_INFO, "his addr %s\n", inet_ntoa(ciaddr1)));
+			if (ciaddr1 != wo->hisaddr
+					&& (ciaddr1 == 0 || !wo->accept_remote)) {
+				orc = CONFNAK;
+				if (!reject_if_disagree) {
+					DECPTR(sizeof(u32_t), p);
+					tl = ntohl(wo->hisaddr);
+					PUTLONG(tl, p);
+				}
+			} else if (ciaddr1 == 0 && wo->hisaddr == 0) {
+				/*
+				 * If neither we nor he knows his address, reject the option.
+				 */
+				orc = CONFREJ;
+				wo->req_addr = 0;	/* don't NAK with 0.0.0.0 later */
+				break;
+			}
+			
+			/*
+			 * If he doesn't know our address, or if we both have our address
+			 * but disagree about it, then NAK it with our idea.
+			 */
+			GETLONG(tl, p);		/* Parse desination address (ours) */
+			ciaddr2 = htonl(tl);
+			IPCPDEBUG((LOG_INFO, "our addr %s\n", inet_ntoa(ciaddr2)));
+			if (ciaddr2 != wo->ouraddr) {
+				if (ciaddr2 == 0 || !wo->accept_local) {
+					orc = CONFNAK;
+					if (!reject_if_disagree) {
+						DECPTR(sizeof(u32_t), p);
+						tl = ntohl(wo->ouraddr);
+						PUTLONG(tl, p);
+					}
+				} else {
+					go->ouraddr = ciaddr2;	/* accept peer's idea */
+				}
+			}
+			
+			ho->neg_addr = 1;
+			ho->old_addrs = 1;
+			ho->hisaddr = ciaddr1;
+			ho->ouraddr = ciaddr2;
+			break;
+#endif
+		
+		case CI_ADDR:
+			if (!ao->neg_addr) {
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR not allowed\n"));
+				orc = CONFREJ;				/* Reject CI */
+				break;
+			} else if (cilen != CILEN_ADDR) {	/* Check CI length */
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR bad len\n"));
+				orc = CONFREJ;				/* Reject CI */
+				break;
+			}
+			
+			/*
+			 * If he has no address, or if we both have his address but
+			 * disagree about it, then NAK it with our idea.
+			 * In particular, if we don't know his address, but he does,
+			 * then accept it.
+			 */
+			GETLONG(tl, p);	/* Parse source address (his) */
+			ciaddr1 = htonl(tl);
+			if (ciaddr1 != wo->hisaddr
+					&& (ciaddr1 == 0 || !wo->accept_remote)) {
+				orc = CONFNAK;
+				if (!reject_if_disagree) {
+					DECPTR(sizeof(u32_t), p);
+					tl = ntohl(wo->hisaddr);
+					PUTLONG(tl, p);
+				}
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Nak ADDR %s\n", inet_ntoa(ciaddr1)));
+			} else if (ciaddr1 == 0 && wo->hisaddr == 0) {
+				/*
+				 * Don't ACK an address of 0.0.0.0 - reject it instead.
+				 */
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR %s\n", inet_ntoa(ciaddr1)));
+				orc = CONFREJ;
+				wo->req_addr = 0;	/* don't NAK with 0.0.0.0 later */
+				break;
+			}
+			
+			ho->neg_addr = 1;
+			ho->hisaddr = ciaddr1;
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: ADDR %s\n", inet_ntoa(ciaddr1)));
+			break;
+		
+		case CI_MS_DNS1:
+		case CI_MS_DNS2:
+			/* Microsoft primary or secondary DNS request */
+			d = citype == CI_MS_DNS2;
+			
+			/* If we do not have a DNS address then we cannot send it */
+			if (ao->dnsaddr[d] == 0 ||
+					cilen != CILEN_ADDR) {	/* Check CI length */
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting DNS%d Request\n", d+1));
+				orc = CONFREJ;				/* Reject CI */
+				break;
+			}
+			GETLONG(tl, p);
+			if (htonl(tl) != ao->dnsaddr[d]) {
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking DNS%d Request %d\n",
+							d+1, inet_ntoa(tl)));
+				DECPTR(sizeof(u32_t), p);
+				tl = ntohl(ao->dnsaddr[d]);
+				PUTLONG(tl, p);
+				orc = CONFNAK;
+			}
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: received DNS%d Request\n", d+1));
+			break;
+		
+		case CI_MS_WINS1:
+		case CI_MS_WINS2:
+			/* Microsoft primary or secondary WINS request */
+			d = citype == CI_MS_WINS2;
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: received WINS%d Request\n", d+1));
+			
+			/* If we do not have a DNS address then we cannot send it */
+			if (ao->winsaddr[d] == 0 ||
+				cilen != CILEN_ADDR) {	/* Check CI length */
+				orc = CONFREJ;			/* Reject CI */
+				break;
+			}
+			GETLONG(tl, p);
+			if (htonl(tl) != ao->winsaddr[d]) {
+				DECPTR(sizeof(u32_t), p);
+				tl = ntohl(ao->winsaddr[d]);
+				PUTLONG(tl, p);
+				orc = CONFNAK;
+			}
+			break;
+		
+		case CI_COMPRESSTYPE:
+			if (!ao->neg_vj) {
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE not allowed\n"));
+				orc = CONFREJ;
+				break;
+			} else if (cilen != CILEN_VJ && cilen != CILEN_COMPRESS) {
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE len=%d\n", cilen));
+				orc = CONFREJ;
+				break;
+			}
+			GETSHORT(cishort, p);
+			
+			if (!(cishort == IPCP_VJ_COMP ||
+					(cishort == IPCP_VJ_COMP_OLD && cilen == CILEN_COMPRESS))) {
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE %d\n", cishort));
+				orc = CONFREJ;
+				break;
+			}
+			
+			ho->neg_vj = 1;
+			ho->vj_protocol = cishort;
+			if (cilen == CILEN_VJ) {
+				GETCHAR(maxslotindex, p);
+				if (maxslotindex > ao->maxslotindex) { 
+					IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ max slot %d\n", maxslotindex));
+					orc = CONFNAK;
+					if (!reject_if_disagree){
+						DECPTR(1, p);
+						PUTCHAR(ao->maxslotindex, p);
+					}
+				}
+				GETCHAR(cflag, p);
+				if (cflag && !ao->cflag) {
+					IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ cflag %d\n", cflag));
+					orc = CONFNAK;
+					if (!reject_if_disagree){
+						DECPTR(1, p);
+						PUTCHAR(wo->cflag, p);
+					}
+				}
+				ho->maxslotindex = maxslotindex;
+				ho->cflag = cflag;
+			} else {
+				ho->old_vj = 1;
+				ho->maxslotindex = MAX_SLOTS - 1;
+				ho->cflag = 1;
+			}
+			IPCPDEBUG((LOG_INFO, 
+						"ipcp_reqci: received COMPRESSTYPE p=%d old=%d maxslot=%d cflag=%d\n",
+						ho->vj_protocol, ho->old_vj, ho->maxslotindex, ho->cflag));
+			break;
+			
+		default:
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting unknown CI type %d\n", citype));
+			orc = CONFREJ;
+			break;
+		}
+		
+endswitch:
+		if (orc == CONFACK &&		/* Good CI */
+				rc != CONFACK)		/*  but prior CI wasnt? */
+			continue;				/* Don't send this one */
+		
+		if (orc == CONFNAK) {		/* Nak this CI? */
+			if (reject_if_disagree) {	/* Getting fed up with sending NAKs? */
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting too many naks\n"));
+				orc = CONFREJ;		/* Get tough if so */
+			} else {
+				if (rc == CONFREJ)	/* Rejecting prior CI? */
+					continue;		/* Don't send this one */
+				if (rc == CONFACK) {	/* Ack'd all prior CIs? */
+					rc = CONFNAK;	/* Not anymore... */
+					ucp = inp;		/* Backup */
+				}
+			}
+		}
+		
+		if (orc == CONFREJ &&		/* Reject this CI */
+				rc != CONFREJ) {	/*  but no prior ones? */
+			rc = CONFREJ;
+			ucp = inp;				/* Backup */
+		}
+		
+		/* Need to move CI? */
+		if (ucp != cip)
+			BCOPY(cip, ucp, cilen);	/* Move it */
+		
+		/* Update output pointer */
+		INCPTR(cilen, ucp);
+	}
+	
+	/*
+	 * If we aren't rejecting this packet, and we want to negotiate
+	 * their address, and they didn't send their address, then we
+	 * send a NAK with a CI_ADDR option appended.  We assume the
+	 * input buffer is long enough that we can append the extra
+	 * option safely.
+	 */
+	if (rc != CONFREJ && !ho->neg_addr &&
+			wo->req_addr && !reject_if_disagree) {
+		IPCPDEBUG((LOG_INFO, "ipcp_reqci: Requesting peer address\n"));
+		if (rc == CONFACK) {
+			rc = CONFNAK;
+			ucp = inp;				/* reset pointer */
+			wo->req_addr = 0;		/* don't ask again */
+		}
+		PUTCHAR(CI_ADDR, ucp);
+		PUTCHAR(CILEN_ADDR, ucp);
+		tl = ntohl(wo->hisaddr);
+		PUTLONG(tl, ucp);
+	}
+	
+	*len = (int)(ucp - inp);		/* Compute output length */
+	IPCPDEBUG((LOG_INFO, "ipcp_reqci: returning Configure-%s\n", CODENAME(rc)));
+	return (rc);			/* Return final code */
+}
+
+
+#if 0
+/*
+ * ip_check_options - check that any IP-related options are OK,
+ * and assign appropriate defaults.
+ */
+static void ip_check_options(u_long localAddr)
+{
+	ipcp_options *wo = &ipcp_wantoptions[0];
+
+	/*
+	 * Load our default IP address but allow the remote host to give us
+	 * a new address.
+	 */
+	if (wo->ouraddr == 0 && !ppp_settings.disable_defaultip) {
+		wo->accept_local = 1;	/* don't insist on this default value */
+		wo->ouraddr = htonl(localAddr);
+	}
+}
+#endif
+
+
+/*
+ * ipcp_up - IPCP has come UP.
+ *
+ * Configure the IP network interface appropriately and bring it up.
+ */
+static void ipcp_up(fsm *f)
+{
+	u32_t mask;
+	ipcp_options *ho = &ipcp_hisoptions[f->unit];
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	ipcp_options *wo = &ipcp_wantoptions[f->unit];
+	
+	np_up(f->unit, PPP_IP);
+	IPCPDEBUG((LOG_INFO, "ipcp: up\n"));
+	
+	/*
+	 * We must have a non-zero IP address for both ends of the link.
+	 */
+	if (!ho->neg_addr)
+		ho->hisaddr = wo->hisaddr;
+	
+	if (ho->hisaddr == 0) {
+		IPCPDEBUG((LOG_ERR, "Could not determine remote IP address\n"));
+		ipcp_close(f->unit, "Could not determine remote IP address");
+		return;
+	}
+	if (go->ouraddr == 0) {
+		IPCPDEBUG((LOG_ERR, "Could not determine local IP address\n"));
+		ipcp_close(f->unit, "Could not determine local IP address");
+		return;
+	}
+	
+	if (ppp_settings.usepeerdns && (go->dnsaddr[0] || go->dnsaddr[1])) {
+		/*pppGotDNSAddrs(go->dnsaddr[0], go->dnsaddr[1]);*/
+	}
+
+	/*
+	 * Check that the peer is allowed to use the IP address it wants.
+	 */
+	if (!auth_ip_addr(f->unit, ho->hisaddr)) {
+		IPCPDEBUG((LOG_ERR, "Peer is not authorized to use remote address %s\n",
+				inet_ntoa(ho->hisaddr)));
+		ipcp_close(f->unit, "Unauthorized remote IP address");
+		return;
+	}
+	
+	/* set tcp compression */
+	sifvjcomp(f->unit, ho->neg_vj, ho->cflag, ho->maxslotindex);
+	
+	/*
+	 * Set IP addresses and (if specified) netmask.
+	 */
+	mask = GetMask(go->ouraddr);
+	
+	if (!sifaddr(f->unit, go->ouraddr, ho->hisaddr, mask, go->dnsaddr[0], go->dnsaddr[1])) {
+		IPCPDEBUG((LOG_WARNING, "sifaddr failed\n"));
+		ipcp_close(f->unit, "Interface configuration failed");
+		return;
+	}
+	
+	/* bring the interface up for IP */
+	if (!sifup(f->unit)) {
+		IPCPDEBUG((LOG_WARNING, "sifup failed\n"));
+		ipcp_close(f->unit, "Interface configuration failed");
+		return;
+	}
+	
+	sifnpmode(f->unit, PPP_IP, NPMODE_PASS);
+	
+	/* assign a default route through the interface if required */
+	if (ipcp_wantoptions[f->unit].default_route) 
+		if (sifdefaultroute(f->unit, go->ouraddr, ho->hisaddr))
+			default_route_set[f->unit] = 1;
+	
+	IPCPDEBUG((LOG_NOTICE, "local  IP address %s\n", inet_ntoa(go->ouraddr)));
+	IPCPDEBUG((LOG_NOTICE, "remote IP address %s\n", inet_ntoa(ho->hisaddr)));
+	if (go->dnsaddr[0]) {
+		IPCPDEBUG((LOG_NOTICE, "primary   DNS address %s\n", inet_ntoa(go->dnsaddr[0])));
+	}
+	if (go->dnsaddr[1]) {
+		IPCPDEBUG((LOG_NOTICE, "secondary DNS address %s\n", inet_ntoa(go->dnsaddr[1])));
+	}
+}
+
+
+/*
+ * ipcp_down - IPCP has gone DOWN.
+ *
+ * Take the IP network interface down, clear its addresses
+ * and delete routes through it.
+ */
+static void ipcp_down(fsm *f)
+{
+	IPCPDEBUG((LOG_INFO, "ipcp: down\n"));
+	np_down(f->unit, PPP_IP);
+	sifvjcomp(f->unit, 0, 0, 0);
+	
+	sifdown(f->unit);
+	ipcp_clear_addrs(f->unit);
+}
+
+
+/*
+ * ipcp_clear_addrs() - clear the interface addresses, routes, etc.
+ */
+static void ipcp_clear_addrs(int unit)
+{
+	u32_t ouraddr, hisaddr;
+	
+	ouraddr = ipcp_gotoptions[unit].ouraddr;
+	hisaddr = ipcp_hisoptions[unit].hisaddr;
+	if (default_route_set[unit]) {
+		cifdefaultroute(unit, ouraddr, hisaddr);
+		default_route_set[unit] = 0;
+	}
+	cifaddr(unit, ouraddr, hisaddr);
+}
+
+
+/*
+ * ipcp_finished - possibly shut down the lower layers.
+ */
+static void ipcp_finished(fsm *f)
+{
+	np_finished(f->unit, PPP_IP);
+}
+
+#if 0
+static int ipcp_printpkt(
+	u_char *p,
+	int plen,
+	void (*printer) (void *, char *, ...),
+	void *arg
+)
+{
+	(void)p;
+	(void)plen;
+	(void)printer;
+	(void)arg;
+	return 0;
+}
+
+/*
+ * ip_active_pkt - see if this IP packet is worth bringing the link up for.
+ * We don't bring the link up for IP fragments or for TCP FIN packets
+ * with no data.
+ */
+#define IP_HDRLEN	20	/* bytes */
+#define IP_OFFMASK	0x1fff
+#define IPPROTO_TCP	6
+#define TCP_HDRLEN	20
+#define TH_FIN		0x01
+
+/*
+ * We use these macros because the IP header may be at an odd address,
+ * and some compilers might use word loads to get th_off or ip_hl.
+ */
+
+#define net_short(x)	(((x)[0] << 8) + (x)[1])
+#define get_iphl(x)	(((unsigned char *)(x))[0] & 0xF)
+#define get_ipoff(x)	net_short((unsigned char *)(x) + 6)
+#define get_ipproto(x)	(((unsigned char *)(x))[9])
+#define get_tcpoff(x)	(((unsigned char *)(x))[12] >> 4)
+#define get_tcpflags(x)	(((unsigned char *)(x))[13])
+
+static int ip_active_pkt(u_char *pkt, int len)
+{
+	u_char *tcp;
+	int hlen;
+	
+	len -= PPP_HDRLEN;
+	pkt += PPP_HDRLEN;
+	if (len < IP_HDRLEN)
+		return 0;
+	if ((get_ipoff(pkt) & IP_OFFMASK) != 0)
+		return 0;
+	if (get_ipproto(pkt) != IPPROTO_TCP)
+		return 1;
+	hlen = get_iphl(pkt) * 4;
+	if (len < hlen + TCP_HDRLEN)
+		return 0;
+	tcp = pkt + hlen;
+	if ((get_tcpflags(tcp) & TH_FIN) != 0 && len == hlen + get_tcpoff(tcp) * 4)
+		return 0;
+	return 1;
+}
+#endif
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/ipcp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/ipcp.h
new file mode 100644
index 0000000..28fc36e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/ipcp.h
@@ -0,0 +1,126 @@
+/*****************************************************************************
+* ipcp.h -  PPP IP NCP: Internet Protocol Network Control Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*	Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * ipcp.h - IP Control Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: ipcp.h,v 1.1 2003/05/27 14:37:56 jani Exp $
+ */
+
+#ifndef IPCP_H
+#define IPCP_H
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+/*
+ * Options.
+ */
+#define CI_ADDRS	1			/* IP Addresses */
+#define CI_COMPRESSTYPE	2		/* Compression Type */
+#define	CI_ADDR		3
+
+#define CI_MS_WINS1	128			/* Primary WINS value */
+#define CI_MS_DNS1	129			/* Primary DNS value */
+#define CI_MS_WINS2	130			/* Secondary WINS value */
+#define CI_MS_DNS2	131			/* Secondary DNS value */
+
+#define IPCP_VJMODE_OLD 1		/* "old" mode (option # = 0x0037) */
+#define IPCP_VJMODE_RFC1172 2	/* "old-rfc"mode (option # = 0x002d) */
+#define IPCP_VJMODE_RFC1332 3	/* "new-rfc"mode (option # = 0x002d, */
+                                /*  maxslot and slot number compression) */
+
+#define IPCP_VJ_COMP 0x002d		/* current value for VJ compression option*/
+#define IPCP_VJ_COMP_OLD 0x0037	/* "old" (i.e, broken) value for VJ */
+								/* compression option*/ 
+
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+typedef struct ipcp_options {
+    u_int neg_addr : 1;			/* Negotiate IP Address? */
+    u_int old_addrs : 1;			/* Use old (IP-Addresses) option? */
+    u_int req_addr : 1;			/* Ask peer to send IP address? */
+    u_int default_route : 1;		/* Assign default route through interface? */
+    u_int proxy_arp : 1;			/* Make proxy ARP entry for peer? */
+    u_int neg_vj : 1;				/* Van Jacobson Compression? */
+    u_int old_vj : 1;				/* use old (short) form of VJ option? */
+    u_int accept_local : 1;		/* accept peer's value for ouraddr */
+    u_int accept_remote : 1;		/* accept peer's value for hisaddr */
+    u_int req_dns1 : 1;			/* Ask peer to send primary DNS address? */
+    u_int req_dns2 : 1;			/* Ask peer to send secondary DNS address? */
+    u_short vj_protocol;		/* protocol value to use in VJ option */
+    u_char maxslotindex;		/* VJ slots - 1. */
+    u_char cflag;				/* VJ slot compression flag. */
+    u32_t ouraddr, hisaddr;	/* Addresses in NETWORK BYTE ORDER */
+    u32_t dnsaddr[2];		/* Primary and secondary MS DNS entries */
+    u32_t winsaddr[2];		/* Primary and secondary MS WINS entries */
+} ipcp_options;
+
+
+/*****************************
+*** PUBLIC DATA STRUCTURES ***
+*****************************/
+
+extern fsm ipcp_fsm[];
+extern ipcp_options ipcp_wantoptions[];
+extern ipcp_options ipcp_gotoptions[];
+extern ipcp_options ipcp_allowoptions[];
+extern ipcp_options ipcp_hisoptions[];
+
+extern struct protent ipcp_protent;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+
+#endif /* IPCP_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/lcp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/lcp.c
new file mode 100644
index 0000000..41dbc5d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/lcp.c
@@ -0,0 +1,1991 @@
+/*****************************************************************************
+* lcp.c - Network Link Control Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-01 Guy Lancaster , Global Election Systems Inc.
+*	Original.
+*****************************************************************************/
+
+/*
+ * lcp.c - PPP Link Control Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+ 
+#include 
+ 
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "fsm.h"
+#include "chap.h"
+#include "magic.h"
+#include "auth.h"
+#include "lcp.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+/*
+ * Length of each type of configuration option (in octets)
+ */
+#define CILEN_VOID	2
+#define CILEN_CHAR	3
+#define CILEN_SHORT	4	/* CILEN_VOID + sizeof(short) */
+#define CILEN_CHAP	5	/* CILEN_VOID + sizeof(short) + 1 */
+#define CILEN_LONG	6	/* CILEN_VOID + sizeof(long) */
+#define CILEN_LQR	8	/* CILEN_VOID + sizeof(short) + sizeof(long) */
+#define CILEN_CBCP	3
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Callbacks for fsm code.  (CI = Configuration Information)
+ */
+static void lcp_resetci (fsm*);	        /* Reset our CI */
+static int  lcp_cilen (fsm*);		        /* Return length of our CI */
+static void lcp_addci (fsm*, u_char*, int*);       /* Add our CI to pkt */
+static int  lcp_ackci (fsm*, u_char*, int);/* Peer ack'd our CI */
+static int  lcp_nakci (fsm*, u_char*, int);/* Peer nak'd our CI */
+static int  lcp_rejci (fsm*, u_char*, int);/* Peer rej'd our CI */
+static int  lcp_reqci (fsm*, u_char*, int*, int);  /* Rcv peer CI */
+static void lcp_up (fsm*);		            /* We're UP */
+static void lcp_down (fsm*);	    	    /* We're DOWN */
+static void lcp_starting (fsm*);   	    /* We need lower layer up */
+static void lcp_finished (fsm*);	        /* We need lower layer down */
+static int  lcp_extcode (fsm*, int, u_char, u_char*, int);
+
+static void lcp_rprotrej (fsm*, u_char*, int);
+
+/*
+ * routines to send LCP echos to peer
+ */
+static void lcp_echo_lowerup (int);
+static void lcp_echo_lowerdown (int);
+static void LcpEchoTimeout (void*);
+static void lcp_received_echo_reply (fsm*, int, u_char*, int);
+static void LcpSendEchoRequest (fsm*);
+static void LcpLinkFailure (fsm*);
+static void LcpEchoCheck (fsm*);
+
+/*
+ * Protocol entry points.
+ * Some of these are called directly.
+ */
+static void lcp_input (int, u_char *, int);
+static void lcp_protrej (int);
+
+#define CODENAME(x)	((x) == CONFACK ? "ACK" : \
+			 (x) == CONFNAK ? "NAK" : "REJ")
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+/* global vars */
+LinkPhase lcp_phase[NUM_PPP];			/* Phase of link session (RFC 1661) */
+lcp_options lcp_wantoptions[NUM_PPP];	/* Options that we want to request */
+lcp_options lcp_gotoptions[NUM_PPP];	/* Options that peer ack'd */
+lcp_options lcp_allowoptions[NUM_PPP];	/* Options we allow peer to request */
+lcp_options lcp_hisoptions[NUM_PPP];	/* Options that we ack'd */
+ext_accm xmit_accm[NUM_PPP];			/* extended transmit ACCM */
+
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static fsm lcp_fsm[NUM_PPP];			/* LCP fsm structure (global)*/
+static u_int	 lcp_echo_interval = LCP_ECHOINTERVAL; /* Interval between LCP echo-requests */
+static u_int	 lcp_echo_fails = LCP_MAXECHOFAILS; /* Tolerance to unanswered echo-requests */
+static u32_t lcp_echos_pending = 0;	/* Number of outstanding echo msgs */
+static u32_t lcp_echo_number   = 0;	/* ID number of next echo frame */
+static u32_t lcp_echo_timer_running = 0;  /* TRUE if a timer is running */
+
+static u_char nak_buffer[PPP_MRU];	/* where we construct a nak packet */
+
+static fsm_callbacks lcp_callbacks = {	/* LCP callback routines */
+    lcp_resetci,		/* Reset our Configuration Information */
+    lcp_cilen,			/* Length of our Configuration Information */
+    lcp_addci,			/* Add our Configuration Information */
+    lcp_ackci,			/* ACK our Configuration Information */
+    lcp_nakci,			/* NAK our Configuration Information */
+    lcp_rejci,			/* Reject our Configuration Information */
+    lcp_reqci,			/* Request peer's Configuration Information */
+    lcp_up,				/* Called when fsm reaches OPENED state */
+    lcp_down,			/* Called when fsm leaves OPENED state */
+    lcp_starting,		/* Called when we want the lower layer up */
+    lcp_finished,		/* Called when we want the lower layer down */
+    NULL,				/* Called when Protocol-Reject received */
+    NULL,				/* Retransmission is necessary */
+    lcp_extcode,		/* Called to handle LCP-specific codes */
+    "LCP"				/* String name of protocol */
+};
+
+struct protent lcp_protent = {
+    PPP_LCP,
+    lcp_init,
+    lcp_input,
+    lcp_protrej,
+    lcp_lowerup,
+    lcp_lowerdown,
+    lcp_open,
+    lcp_close,
+#if 0
+    lcp_printpkt,
+    NULL,
+#endif
+    1,
+    "LCP",
+#if 0
+    NULL,
+    NULL,
+    NULL
+#endif
+};
+
+int lcp_loopbackfail = DEFLOOPBACKFAIL;
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * lcp_init - Initialize LCP.
+ */
+void lcp_init(int unit)
+{
+	fsm *f = &lcp_fsm[unit];
+	lcp_options *wo = &lcp_wantoptions[unit];
+	lcp_options *ao = &lcp_allowoptions[unit];
+	
+	f->unit = unit;
+	f->protocol = PPP_LCP;
+	f->callbacks = &lcp_callbacks;
+	
+	fsm_init(f);
+	
+	wo->passive = 0;
+	wo->silent = 0;
+	wo->restart = 0;			/* Set to 1 in kernels or multi-line
+								 * implementations */
+	wo->neg_mru = 1;
+	wo->mru = PPP_DEFMRU;
+	wo->neg_asyncmap = 1;
+	wo->asyncmap = 0x00000000l;	/* Assume don't need to escape any ctl chars. */
+	wo->neg_chap = 0;			/* Set to 1 on server */
+	wo->neg_upap = 0;			/* Set to 1 on server */
+	wo->chap_mdtype = CHAP_DIGEST_MD5;
+	wo->neg_magicnumber = 1;
+	wo->neg_pcompression = 1;
+	wo->neg_accompression = 1;
+	wo->neg_lqr = 0;			/* no LQR implementation yet */
+	wo->neg_cbcp = 0;
+	
+	ao->neg_mru = 1;
+	ao->mru = PPP_MAXMRU;
+	ao->neg_asyncmap = 1;
+	ao->asyncmap = 0x00000000l;	/* Assume don't need to escape any ctl chars. */
+	ao->neg_chap = (CHAP_SUPPORT != 0);
+	ao->chap_mdtype = CHAP_DIGEST_MD5;
+	ao->neg_upap = (PAP_SUPPORT != 0);
+	ao->neg_magicnumber = 1;
+	ao->neg_pcompression = 1;
+	ao->neg_accompression = 1;
+	ao->neg_lqr = 0;			/* no LQR implementation yet */
+	ao->neg_cbcp = (CBCP_SUPPORT != 0);
+
+	/* 
+	 * Set transmit escape for the flag and escape characters plus anything
+	 * set for the allowable options.
+	 */
+	memset(xmit_accm[unit], 0, sizeof(xmit_accm[0]));
+	xmit_accm[unit][15] = 0x60;
+	xmit_accm[unit][0] = (u_char)(ao->asyncmap & 0xFF);
+	xmit_accm[unit][1] = (u_char)((ao->asyncmap >> 8) & 0xFF);
+	xmit_accm[unit][2] = (u_char)((ao->asyncmap >> 16) & 0xFF);
+	xmit_accm[unit][3] = (u_char)((ao->asyncmap >> 24) & 0xFF);
+	LCPDEBUG((LOG_INFO, "lcp_init: xmit_accm=%X %X %X %X\n",
+				xmit_accm[unit][0],
+				xmit_accm[unit][1],
+				xmit_accm[unit][2],
+				xmit_accm[unit][3]));
+	
+	lcp_phase[unit] = PHASE_INITIALIZE;
+}
+
+
+/*
+ * lcp_open - LCP is allowed to come up.
+ */
+void lcp_open(int unit)
+{
+	fsm *f = &lcp_fsm[unit];
+	lcp_options *wo = &lcp_wantoptions[unit];
+	
+	f->flags = 0;
+	if (wo->passive)
+		f->flags |= OPT_PASSIVE;
+	if (wo->silent)
+		f->flags |= OPT_SILENT;
+	fsm_open(f);
+	
+	lcp_phase[unit] = PHASE_ESTABLISH; 
+}
+
+
+/*
+ * lcp_close - Take LCP down.
+ */
+void lcp_close(int unit, char *reason)
+{
+	fsm *f = &lcp_fsm[unit];
+	
+	if (lcp_phase[unit] != PHASE_DEAD)
+		lcp_phase[unit] = PHASE_TERMINATE;
+	if (f->state == STOPPED && f->flags & (OPT_PASSIVE|OPT_SILENT)) {
+		/*
+		 * This action is not strictly according to the FSM in RFC1548,
+		 * but it does mean that the program terminates if you do an
+		 * lcp_close() in passive/silent mode when a connection hasn't
+		 * been established.
+		 */
+		f->state = CLOSED;
+		lcp_finished(f);
+	}
+	else
+		fsm_close(&lcp_fsm[unit], reason);
+}
+
+
+/*
+ * lcp_lowerup - The lower layer is up.
+ */
+void lcp_lowerup(int unit)
+{
+	lcp_options *wo = &lcp_wantoptions[unit];
+	
+	/*
+	* Don't use A/C or protocol compression on transmission,
+	* but accept A/C and protocol compressed packets
+	* if we are going to ask for A/C and protocol compression.
+	*/
+	ppp_set_xaccm(unit, &xmit_accm[unit]);
+	ppp_send_config(unit, PPP_MRU, 0xffffffffl, 0, 0);
+	ppp_recv_config(unit, PPP_MRU, 0x00000000l,
+					wo->neg_pcompression, wo->neg_accompression);
+	peer_mru[unit] = PPP_MRU;
+	lcp_allowoptions[unit].asyncmap 
+		= (u_long)xmit_accm[unit][0]
+			| ((u_long)xmit_accm[unit][1] << 8)
+			| ((u_long)xmit_accm[unit][2] << 16)
+			| ((u_long)xmit_accm[unit][3] << 24);
+	LCPDEBUG((LOG_INFO, "lcp_lowerup: asyncmap=%X %X %X %X\n",
+				xmit_accm[unit][3],
+				xmit_accm[unit][2],
+				xmit_accm[unit][1],
+				xmit_accm[unit][0]));
+	
+	fsm_lowerup(&lcp_fsm[unit]);
+}
+
+
+/*
+ * lcp_lowerdown - The lower layer is down.
+ */
+void lcp_lowerdown(int unit)
+{
+	fsm_lowerdown(&lcp_fsm[unit]);
+}
+
+/*
+ * lcp_sprotrej - Send a Protocol-Reject for some protocol.
+ */
+void lcp_sprotrej(int unit, u_char *p, int len)
+{
+	/*
+	* Send back the protocol and the information field of the
+	* rejected packet.  We only get here if LCP is in the OPENED state.
+	*/
+
+	fsm_sdata(&lcp_fsm[unit], PROTREJ, ++lcp_fsm[unit].id,
+				p, len);
+}
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * lcp_input - Input LCP packet.
+ */
+static void lcp_input(int unit, u_char *p, int len)
+{
+	fsm *f = &lcp_fsm[unit];
+	
+	fsm_input(f, p, len);
+}
+
+
+/*
+ * lcp_extcode - Handle a LCP-specific code.
+ */
+static int lcp_extcode(fsm *f, int code, u_char id, u_char *inp, int len)
+{
+	u_char *magp;
+	
+	switch( code ){
+	case PROTREJ:
+		lcp_rprotrej(f, inp, len);
+		break;
+	
+	case ECHOREQ:
+		if (f->state != OPENED)
+			break;
+		LCPDEBUG((LOG_INFO, "lcp: Echo-Request, Rcvd id %d\n", id));
+		magp = inp;
+		PUTLONG(lcp_gotoptions[f->unit].magicnumber, magp);
+		fsm_sdata(f, ECHOREP, id, inp, len);
+		break;
+	
+	case ECHOREP:
+		lcp_received_echo_reply(f, id, inp, len);
+		break;
+	
+	case DISCREQ:
+		break;
+	
+	default:
+		return 0;
+	}
+	return 1;
+}
+
+    
+/*
+ * lcp_rprotrej - Receive an Protocol-Reject.
+ *
+ * Figure out which protocol is rejected and inform it.
+ */
+static void lcp_rprotrej(fsm *f, u_char *inp, int len)
+{
+	int i;
+	struct protent *protp;
+	u_short prot;
+	
+	if (len < sizeof (u_short)) {
+		LCPDEBUG((LOG_INFO,
+				"lcp_rprotrej: Rcvd short Protocol-Reject packet!\n"));
+		return;
+	}
+	
+	GETSHORT(prot, inp);
+	
+	LCPDEBUG((LOG_INFO,
+			"lcp_rprotrej: Rcvd Protocol-Reject packet for %x!\n",
+			prot));
+	
+	/*
+	* Protocol-Reject packets received in any state other than the LCP
+	* OPENED state SHOULD be silently discarded.
+	*/
+	if( f->state != OPENED ){
+		LCPDEBUG((LOG_INFO, "Protocol-Reject discarded: LCP in state %d\n",
+				f->state));
+		return;
+	}
+	
+	/*
+	* Upcall the proper Protocol-Reject routine.
+	*/
+	for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i)
+		if (protp->protocol == prot && protp->enabled_flag) {
+			(*protp->protrej)(f->unit);
+			return;
+		}
+	
+	LCPDEBUG((LOG_WARNING, "Protocol-Reject for unsupported protocol 0x%x\n",
+			prot));
+}
+
+
+/*
+ * lcp_protrej - A Protocol-Reject was received.
+ */
+static void lcp_protrej(int unit)
+{
+	(void)unit;
+	/*
+	* Can't reject LCP!
+	*/
+	LCPDEBUG((LOG_WARNING,
+			"lcp_protrej: Received Protocol-Reject for LCP!\n"));
+	fsm_protreject(&lcp_fsm[unit]);
+}
+
+
+/*
+ * lcp_resetci - Reset our CI.
+ */
+static void lcp_resetci(fsm *f)
+{
+	lcp_wantoptions[f->unit].magicnumber = magic();
+	lcp_wantoptions[f->unit].numloops = 0;
+	lcp_gotoptions[f->unit] = lcp_wantoptions[f->unit];
+	peer_mru[f->unit] = PPP_MRU;
+	auth_reset(f->unit);
+}
+
+
+/*
+ * lcp_cilen - Return length of our CI.
+ */
+static int lcp_cilen(fsm *f)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+
+#define LENCIVOID(neg)	((neg) ? CILEN_VOID : 0)
+#define LENCICHAP(neg)	((neg) ? CILEN_CHAP : 0)
+#define LENCISHORT(neg)	((neg) ? CILEN_SHORT : 0)
+#define LENCILONG(neg)	((neg) ? CILEN_LONG : 0)
+#define LENCILQR(neg)	((neg) ? CILEN_LQR: 0)
+#define LENCICBCP(neg)	((neg) ? CILEN_CBCP: 0)
+	/*
+	* NB: we only ask for one of CHAP and UPAP, even if we will
+	* accept either.
+	*/
+	return (LENCISHORT(go->neg_mru && go->mru != PPP_DEFMRU) +
+		LENCILONG(go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) +
+		LENCICHAP(go->neg_chap) +
+		LENCISHORT(!go->neg_chap && go->neg_upap) +
+		LENCILQR(go->neg_lqr) +
+		LENCICBCP(go->neg_cbcp) +
+		LENCILONG(go->neg_magicnumber) +
+		LENCIVOID(go->neg_pcompression) +
+		LENCIVOID(go->neg_accompression));
+}
+
+
+/*
+ * lcp_addci - Add our desired CIs to a packet.
+ */
+static void lcp_addci(fsm *f, u_char *ucp, int *lenp)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	u_char *start_ucp = ucp;
+	
+#define ADDCIVOID(opt, neg) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: opt=%d\n", opt)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_VOID, ucp); \
+	}
+#define ADDCISHORT(opt, neg, val) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: INT opt=%d %X\n", opt, val)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_SHORT, ucp); \
+		PUTSHORT(val, ucp); \
+	}
+#define ADDCICHAP(opt, neg, val, digest) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: CHAP opt=%d %X\n", opt, val)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_CHAP, ucp); \
+		PUTSHORT(val, ucp); \
+		PUTCHAR(digest, ucp); \
+	}
+#define ADDCILONG(opt, neg, val) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: L opt=%d %lX\n", opt, val)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_LONG, ucp); \
+		PUTLONG(val, ucp); \
+	}
+#define ADDCILQR(opt, neg, val) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: LQR opt=%d %lX\n", opt, val)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_LQR, ucp); \
+		PUTSHORT(PPP_LQR, ucp); \
+		PUTLONG(val, ucp); \
+	}
+#define ADDCICHAR(opt, neg, val) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: CHAR opt=%d %X '%z'\n", opt, val, val)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_CHAR, ucp); \
+		PUTCHAR(val, ucp); \
+	}
+	
+	ADDCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru);
+	ADDCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl,
+			go->asyncmap);
+	ADDCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype);
+	ADDCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP);
+	ADDCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period);
+	ADDCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT);
+	ADDCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber);
+	ADDCIVOID(CI_PCOMPRESSION, go->neg_pcompression);
+	ADDCIVOID(CI_ACCOMPRESSION, go->neg_accompression);
+	
+	if (ucp - start_ucp != *lenp) {
+		/* this should never happen, because peer_mtu should be 1500 */
+		LCPDEBUG((LOG_ERR, "Bug in lcp_addci: wrong length\n"));
+	}
+}
+
+
+/*
+ * lcp_ackci - Ack our CIs.
+ * This should not modify any state if the Ack is bad.
+ *
+ * Returns:
+ *	0 - Ack was bad.
+ *	1 - Ack was good.
+ */
+static int lcp_ackci(fsm *f, u_char *p, int len)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	u_char cilen, citype, cichar;
+	u_short cishort;
+	u32_t cilong;
+	
+	/*
+	* CIs must be in exactly the same order that we sent.
+	* Check packet length and CI length at each step.
+	* If we find any deviations, then this packet is bad.
+	*/
+#define ACKCIVOID(opt, neg) \
+	if (neg) { \
+		if ((len -= CILEN_VOID) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_VOID || \
+				citype != opt) \
+			goto bad; \
+	}
+#define ACKCISHORT(opt, neg, val) \
+	if (neg) { \
+		if ((len -= CILEN_SHORT) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_SHORT || \
+				citype != opt) \
+			goto bad; \
+		GETSHORT(cishort, p); \
+		if (cishort != val) \
+			goto bad; \
+	}
+#define ACKCICHAR(opt, neg, val) \
+	if (neg) { \
+		if ((len -= CILEN_CHAR) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_CHAR || \
+				citype != opt) \
+			goto bad; \
+		GETCHAR(cichar, p); \
+		if (cichar != val) \
+			goto bad; \
+	}
+#define ACKCICHAP(opt, neg, val, digest) \
+	if (neg) { \
+		if ((len -= CILEN_CHAP) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_CHAP || \
+				citype != opt) \
+			goto bad; \
+		GETSHORT(cishort, p); \
+		if (cishort != val) \
+			goto bad; \
+		GETCHAR(cichar, p); \
+		if (cichar != digest) \
+			goto bad; \
+	}
+#define ACKCILONG(opt, neg, val) \
+	if (neg) { \
+		if ((len -= CILEN_LONG) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_LONG || \
+				citype != opt) \
+			goto bad; \
+		GETLONG(cilong, p); \
+		if (cilong != val) \
+			goto bad; \
+	}
+#define ACKCILQR(opt, neg, val) \
+	if (neg) { \
+		if ((len -= CILEN_LQR) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_LQR || \
+				citype != opt) \
+			goto bad; \
+		GETSHORT(cishort, p); \
+		if (cishort != PPP_LQR) \
+			goto bad; \
+		GETLONG(cilong, p); \
+		if (cilong != val) \
+			goto bad; \
+	}
+	
+	ACKCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru);
+	ACKCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl,
+			go->asyncmap);
+	ACKCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype);
+	ACKCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP);
+	ACKCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period);
+	ACKCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT);
+	ACKCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber);
+	ACKCIVOID(CI_PCOMPRESSION, go->neg_pcompression);
+	ACKCIVOID(CI_ACCOMPRESSION, go->neg_accompression);
+	
+	/*
+	 * If there are any remaining CIs, then this packet is bad.
+	 */
+	if (len != 0)
+		goto bad;
+	LCPDEBUG((LOG_INFO, "lcp_acki: Ack\n"));
+	return (1);
+bad:
+	LCPDEBUG((LOG_WARNING, "lcp_acki: received bad Ack!\n"));
+	return (0);
+}
+
+
+/*
+ * lcp_nakci - Peer has sent a NAK for some of our CIs.
+ * This should not modify any state if the Nak is bad
+ * or if LCP is in the OPENED state.
+ *
+ * Returns:
+ *	0 - Nak was bad.
+ *	1 - Nak was good.
+ */
+static int lcp_nakci(fsm *f, u_char *p, int len)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	lcp_options *wo = &lcp_wantoptions[f->unit];
+	u_char citype, cichar, *next;
+	u_short cishort;
+	u32_t cilong;
+	lcp_options no;		/* options we've seen Naks for */
+	lcp_options try;		/* options to request next time */
+	int looped_back = 0;
+	int cilen;
+	
+	BZERO(&no, sizeof(no));
+	try = *go;
+	
+	/*
+	* Any Nak'd CIs must be in exactly the same order that we sent.
+	* Check packet length and CI length at each step.
+	* If we find any deviations, then this packet is bad.
+	*/
+#define NAKCIVOID(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_VOID && \
+			p[1] == CILEN_VOID && \
+			p[0] == opt) { \
+		len -= CILEN_VOID; \
+		INCPTR(CILEN_VOID, p); \
+		no.neg = 1; \
+		code \
+	}
+#define NAKCICHAP(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_CHAP && \
+			p[1] == CILEN_CHAP && \
+			p[0] == opt) { \
+		len -= CILEN_CHAP; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		GETCHAR(cichar, p); \
+		no.neg = 1; \
+		code \
+	}
+#define NAKCICHAR(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_CHAR && \
+			p[1] == CILEN_CHAR && \
+			p[0] == opt) { \
+		len -= CILEN_CHAR; \
+		INCPTR(2, p); \
+		GETCHAR(cichar, p); \
+		no.neg = 1; \
+		code \
+	}
+#define NAKCISHORT(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_SHORT && \
+			p[1] == CILEN_SHORT && \
+			p[0] == opt) { \
+		len -= CILEN_SHORT; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		no.neg = 1; \
+		code \
+	}
+#define NAKCILONG(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_LONG && \
+			p[1] == CILEN_LONG && \
+			p[0] == opt) { \
+		len -= CILEN_LONG; \
+		INCPTR(2, p); \
+		GETLONG(cilong, p); \
+		no.neg = 1; \
+		code \
+	}
+#define NAKCILQR(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_LQR && \
+			p[1] == CILEN_LQR && \
+			p[0] == opt) { \
+		len -= CILEN_LQR; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		GETLONG(cilong, p); \
+		no.neg = 1; \
+		code \
+	}
+	
+	/*
+	* We don't care if they want to send us smaller packets than
+	* we want.  Therefore, accept any MRU less than what we asked for,
+	* but then ignore the new value when setting the MRU in the kernel.
+	* If they send us a bigger MRU than what we asked, accept it, up to
+	* the limit of the default MRU we'd get if we didn't negotiate.
+	*/
+	if (go->neg_mru && go->mru != PPP_DEFMRU) {
+		NAKCISHORT(CI_MRU, neg_mru,
+			if (cishort <= wo->mru || cishort < PPP_DEFMRU)
+				try.mru = cishort;
+		);
+	}
+	
+	/*
+	* Add any characters they want to our (receive-side) asyncmap.
+	*/
+	if (go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) {
+		NAKCILONG(CI_ASYNCMAP, neg_asyncmap,
+			try.asyncmap = go->asyncmap | cilong;
+		);
+	}
+	
+	/*
+	* If they've nak'd our authentication-protocol, check whether
+	* they are proposing a different protocol, or a different
+	* hash algorithm for CHAP.
+	*/
+	if ((go->neg_chap || go->neg_upap)
+			&& len >= CILEN_SHORT
+			&& p[0] == CI_AUTHTYPE && p[1] >= CILEN_SHORT && p[1] <= len) {
+		cilen = p[1];
+	len -= cilen;
+	no.neg_chap = go->neg_chap;
+	no.neg_upap = go->neg_upap;
+	INCPTR(2, p);
+	GETSHORT(cishort, p);
+	if (cishort == PPP_PAP && cilen == CILEN_SHORT) {
+		/*
+		 * If we were asking for CHAP, they obviously don't want to do it.
+		 * If we weren't asking for CHAP, then we were asking for PAP,
+		 * in which case this Nak is bad.
+		 */
+		if (!go->neg_chap)
+			goto bad;
+		try.neg_chap = 0;
+	
+	} else if (cishort == PPP_CHAP && cilen == CILEN_CHAP) {
+		GETCHAR(cichar, p);
+		if (go->neg_chap) {
+			/*
+			 * We were asking for CHAP/MD5; they must want a different
+			 * algorithm.  If they can't do MD5, we'll have to stop
+			 * asking for CHAP.
+			 */
+			if (cichar != go->chap_mdtype)
+				try.neg_chap = 0;
+		} else {
+			/*
+			 * Stop asking for PAP if we were asking for it.
+			 */
+			try.neg_upap = 0;
+		}
+	
+	} else {
+		/*
+		 * We don't recognize what they're suggesting.
+		 * Stop asking for what we were asking for.
+		 */
+		if (go->neg_chap)
+			try.neg_chap = 0;
+		else
+			try.neg_upap = 0;
+		p += cilen - CILEN_SHORT;
+	}
+	}
+	
+	/*
+	* If they can't cope with our link quality protocol, we'll have
+	* to stop asking for LQR.  We haven't got any other protocol.
+	* If they Nak the reporting period, take their value XXX ?
+	*/
+	NAKCILQR(CI_QUALITY, neg_lqr,
+		if (cishort != PPP_LQR)
+			try.neg_lqr = 0;
+		else
+			try.lqr_period = cilong;
+	);
+	
+	/*
+	* Only implementing CBCP...not the rest of the callback options
+	*/
+	NAKCICHAR(CI_CALLBACK, neg_cbcp,
+		try.neg_cbcp = 0;
+	);
+	
+	/*
+	* Check for a looped-back line.
+	*/
+	NAKCILONG(CI_MAGICNUMBER, neg_magicnumber,
+		try.magicnumber = magic();
+		looped_back = 1;
+	);
+	
+	/*
+	* Peer shouldn't send Nak for protocol compression or
+	* address/control compression requests; they should send
+	* a Reject instead.  If they send a Nak, treat it as a Reject.
+	*/
+	NAKCIVOID(CI_PCOMPRESSION, neg_pcompression,
+		try.neg_pcompression = 0;
+	);
+	NAKCIVOID(CI_ACCOMPRESSION, neg_accompression,
+		try.neg_accompression = 0;
+	);
+	
+	/*
+	* There may be remaining CIs, if the peer is requesting negotiation
+	* on an option that we didn't include in our request packet.
+	* If we see an option that we requested, or one we've already seen
+	* in this packet, then this packet is bad.
+	* If we wanted to respond by starting to negotiate on the requested
+	* option(s), we could, but we don't, because except for the
+	* authentication type and quality protocol, if we are not negotiating
+	* an option, it is because we were told not to.
+	* For the authentication type, the Nak from the peer means
+	* `let me authenticate myself with you' which is a bit pointless.
+	* For the quality protocol, the Nak means `ask me to send you quality
+	* reports', but if we didn't ask for them, we don't want them.
+	* An option we don't recognize represents the peer asking to
+	* negotiate some option we don't support, so ignore it.
+	*/
+	while (len > CILEN_VOID) {
+		GETCHAR(citype, p);
+		GETCHAR(cilen, p);
+		if (cilen < CILEN_VOID || (len -= cilen) < 0)
+			goto bad;
+		next = p + cilen - 2;
+		
+		switch (citype) {
+		case CI_MRU:
+			if ((go->neg_mru && go->mru != PPP_DEFMRU)
+					|| no.neg_mru || cilen != CILEN_SHORT)
+				goto bad;
+			GETSHORT(cishort, p);
+			if (cishort < PPP_DEFMRU)
+				try.mru = cishort;
+			break;
+		case CI_ASYNCMAP:
+			if ((go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl)
+					|| no.neg_asyncmap || cilen != CILEN_LONG)
+				goto bad;
+			break;
+		case CI_AUTHTYPE:
+			if (go->neg_chap || no.neg_chap || go->neg_upap || no.neg_upap)
+				goto bad;
+			break;
+		case CI_MAGICNUMBER:
+			if (go->neg_magicnumber || no.neg_magicnumber ||
+					cilen != CILEN_LONG)
+				goto bad;
+			break;
+		case CI_PCOMPRESSION:
+			if (go->neg_pcompression || no.neg_pcompression
+					|| cilen != CILEN_VOID)
+				goto bad;
+			break;
+		case CI_ACCOMPRESSION:
+			if (go->neg_accompression || no.neg_accompression
+					|| cilen != CILEN_VOID)
+				goto bad;
+			break;
+		case CI_QUALITY:
+			if (go->neg_lqr || no.neg_lqr || cilen != CILEN_LQR)
+				goto bad;
+			break;
+		}
+		p = next;
+	}
+	
+	/* If there is still anything left, this packet is bad. */
+	if (len != 0)
+		goto bad;
+	
+	/*
+	* OK, the Nak is good.  Now we can update state.
+	*/
+	if (f->state != OPENED) {
+		if (looped_back) {
+			if (++try.numloops >= lcp_loopbackfail) {
+				LCPDEBUG((LOG_NOTICE, "Serial line is looped back.\n"));
+				lcp_close(f->unit, "Loopback detected");
+			}
+		} 
+		else
+			try.numloops = 0;
+		*go = try;
+	}
+	
+	return 1;
+	
+bad:
+	LCPDEBUG((LOG_WARNING, "lcp_nakci: received bad Nak!\n"));
+	return 0;
+}
+
+
+/*
+ * lcp_rejci - Peer has Rejected some of our CIs.
+ * This should not modify any state if the Reject is bad
+ * or if LCP is in the OPENED state.
+ *
+ * Returns:
+ *	0 - Reject was bad.
+ *	1 - Reject was good.
+ */
+static int lcp_rejci(fsm *f, u_char *p, int len)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	u_char cichar;
+	u_short cishort;
+	u32_t cilong;
+	lcp_options try;		/* options to request next time */
+	
+	try = *go;
+	
+	/*
+	* Any Rejected CIs must be in exactly the same order that we sent.
+	* Check packet length and CI length at each step.
+	* If we find any deviations, then this packet is bad.
+	*/
+#define REJCIVOID(opt, neg) \
+	if (go->neg && \
+			len >= CILEN_VOID && \
+			p[1] == CILEN_VOID && \
+			p[0] == opt) { \
+		len -= CILEN_VOID; \
+		INCPTR(CILEN_VOID, p); \
+		try.neg = 0; \
+		LCPDEBUG((LOG_INFO, "lcp_rejci: void opt %d rejected\n", opt)); \
+	}
+#define REJCISHORT(opt, neg, val) \
+	if (go->neg && \
+			len >= CILEN_SHORT && \
+			p[1] == CILEN_SHORT && \
+			p[0] == opt) { \
+		len -= CILEN_SHORT; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		/* Check rejected value. */ \
+		if (cishort != val) \
+			goto bad; \
+		try.neg = 0; \
+		LCPDEBUG((LOG_INFO,"lcp_rejci: short opt %d rejected\n", opt)); \
+	}
+#define REJCICHAP(opt, neg, val, digest) \
+	if (go->neg && \
+			len >= CILEN_CHAP && \
+			p[1] == CILEN_CHAP && \
+			p[0] == opt) { \
+		len -= CILEN_CHAP; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		GETCHAR(cichar, p); \
+		/* Check rejected value. */ \
+		if (cishort != val || cichar != digest) \
+			goto bad; \
+		try.neg = 0; \
+		try.neg_upap = 0; \
+		LCPDEBUG((LOG_INFO,"lcp_rejci: chap opt %d rejected\n", opt)); \
+	}
+#define REJCILONG(opt, neg, val) \
+	if (go->neg && \
+			len >= CILEN_LONG && \
+			p[1] == CILEN_LONG && \
+			p[0] == opt) { \
+		len -= CILEN_LONG; \
+		INCPTR(2, p); \
+		GETLONG(cilong, p); \
+		/* Check rejected value. */ \
+		if (cilong != val) \
+			goto bad; \
+		try.neg = 0; \
+		LCPDEBUG((LOG_INFO,"lcp_rejci: long opt %d rejected\n", opt)); \
+	}
+#define REJCILQR(opt, neg, val) \
+	if (go->neg && \
+			len >= CILEN_LQR && \
+			p[1] == CILEN_LQR && \
+			p[0] == opt) { \
+		len -= CILEN_LQR; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		GETLONG(cilong, p); \
+		/* Check rejected value. */ \
+		if (cishort != PPP_LQR || cilong != val) \
+			goto bad; \
+		try.neg = 0; \
+		LCPDEBUG((LOG_INFO,"lcp_rejci: LQR opt %d rejected\n", opt)); \
+	}
+#define REJCICBCP(opt, neg, val) \
+	if (go->neg && \
+			len >= CILEN_CBCP && \
+			p[1] == CILEN_CBCP && \
+			p[0] == opt) { \
+		len -= CILEN_CBCP; \
+		INCPTR(2, p); \
+		GETCHAR(cichar, p); \
+		/* Check rejected value. */ \
+		if (cichar != val) \
+			goto bad; \
+		try.neg = 0; \
+		LCPDEBUG((LOG_INFO,"lcp_rejci: Callback opt %d rejected\n", opt)); \
+	}
+	
+	REJCISHORT(CI_MRU, neg_mru, go->mru);
+	REJCILONG(CI_ASYNCMAP, neg_asyncmap, go->asyncmap);
+	REJCICHAP(CI_AUTHTYPE, neg_chap, PPP_CHAP, go->chap_mdtype);
+	if (!go->neg_chap) {
+		REJCISHORT(CI_AUTHTYPE, neg_upap, PPP_PAP);
+	}
+	REJCILQR(CI_QUALITY, neg_lqr, go->lqr_period);
+	REJCICBCP(CI_CALLBACK, neg_cbcp, CBCP_OPT);
+	REJCILONG(CI_MAGICNUMBER, neg_magicnumber, go->magicnumber);
+	REJCIVOID(CI_PCOMPRESSION, neg_pcompression);
+	REJCIVOID(CI_ACCOMPRESSION, neg_accompression);
+	
+	/*
+	* If there are any remaining CIs, then this packet is bad.
+	*/
+	if (len != 0)
+		goto bad;
+	/*
+	* Now we can update state.
+	*/
+	if (f->state != OPENED)
+		*go = try;
+	return 1;
+	
+bad:
+	LCPDEBUG((LOG_WARNING, "lcp_rejci: received bad Reject!\n"));
+	return 0;
+}
+
+
+/*
+ * lcp_reqci - Check the peer's requested CIs and send appropriate response.
+ *
+ * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified
+ * appropriately.  If reject_if_disagree is non-zero, doesn't return
+ * CONFNAK; returns CONFREJ if it can't return CONFACK.
+ */
+static int lcp_reqci(fsm *f, 
+						u_char *inp,		/* Requested CIs */
+						int *lenp,			/* Length of requested CIs */
+						int reject_if_disagree)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	lcp_options *ho = &lcp_hisoptions[f->unit];
+	lcp_options *ao = &lcp_allowoptions[f->unit];
+	u_char *cip, *next;			/* Pointer to current and next CIs */
+	int cilen, citype, cichar;	/* Parsed len, type, char value */
+	u_short cishort;			/* Parsed short value */
+	u32_t cilong;			/* Parse long value */
+	int rc = CONFACK;			/* Final packet return code */
+	int orc;					/* Individual option return code */
+	u_char *p;					/* Pointer to next char to parse */
+	u_char *rejp;				/* Pointer to next char in reject frame */
+	u_char *nakp;				/* Pointer to next char in Nak frame */
+	int l = *lenp;				/* Length left */
+#if TRACELCP > 0
+	char traceBuf[80];
+	int traceNdx = 0;
+#endif
+	
+	/*
+	 * Reset all his options.
+	 */
+	BZERO(ho, sizeof(*ho));
+	
+	/*
+	 * Process all his options.
+	 */
+	next = inp;
+	nakp = nak_buffer;
+	rejp = inp;
+	while (l) {
+		orc = CONFACK;			/* Assume success */
+		cip = p = next;			/* Remember begining of CI */
+		if (l < 2 ||			/* Not enough data for CI header or */
+				p[1] < 2 ||			/*  CI length too small or */
+				p[1] > l) {			/*  CI length too big? */
+			LCPDEBUG((LOG_WARNING, "lcp_reqci: bad CI length!\n"));
+			orc = CONFREJ;		/* Reject bad CI */
+			cilen = l;			/* Reject till end of packet */
+			l = 0;			/* Don't loop again */
+			citype = 0;
+			goto endswitch;
+		}
+		GETCHAR(citype, p);		/* Parse CI type */
+		GETCHAR(cilen, p);		/* Parse CI length */
+		l -= cilen;			/* Adjust remaining length */
+		next += cilen;			/* Step to next CI */
+		
+		switch (citype) {		/* Check CI type */
+		case CI_MRU:
+			if (!ao->neg_mru) {		/* Allow option? */
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - not allowed\n"));
+				orc = CONFREJ;		/* Reject CI */
+				break;
+			} else if (cilen != CILEN_SHORT) {	/* Check CI length */
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - bad length\n"));
+				orc = CONFREJ;		/* Reject CI */
+				break;
+			}
+			GETSHORT(cishort, p);	/* Parse MRU */
+			
+			/*
+			 * He must be able to receive at least our minimum.
+			 * No need to check a maximum.  If he sends a large number,
+			 * we'll just ignore it.
+			 */
+			if (cishort < PPP_MINMRU) {
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Nak - MRU too small\n"));
+				orc = CONFNAK;		/* Nak CI */
+				PUTCHAR(CI_MRU, nakp);
+				PUTCHAR(CILEN_SHORT, nakp);
+				PUTSHORT(PPP_MINMRU, nakp);	/* Give him a hint */
+				break;
+			}
+			ho->neg_mru = 1;		/* Remember he sent MRU */
+			ho->mru = cishort;		/* And remember value */
+#if TRACELCP > 0
+			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MRU %d", cishort);
+			traceNdx = strlen(traceBuf);
+#endif
+			break;
+		
+		case CI_ASYNCMAP:
+			if (!ao->neg_asyncmap) {
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP not allowed\n"));
+				orc = CONFREJ;
+				break;
+			} else if (cilen != CILEN_LONG) {
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP bad length\n"));
+				orc = CONFREJ;
+				break;
+			}
+			GETLONG(cilong, p);
+			
+			/*
+			 * Asyncmap must have set at least the bits
+			 * which are set in lcp_allowoptions[unit].asyncmap.
+			 */
+			if ((ao->asyncmap & ~cilong) != 0) {
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Nak ASYNCMAP %lX missing %lX\n", 
+							cilong, ao->asyncmap));
+				orc = CONFNAK;
+				PUTCHAR(CI_ASYNCMAP, nakp);
+				PUTCHAR(CILEN_LONG, nakp);
+				PUTLONG(ao->asyncmap | cilong, nakp);
+				break;
+			}
+			ho->neg_asyncmap = 1;
+			ho->asyncmap = cilong;
+#if TRACELCP > 0
+			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ASYNCMAP=%lX", cilong);
+			traceNdx = strlen(traceBuf);
+#endif
+			break;
+		
+		case CI_AUTHTYPE:
+			if (cilen < CILEN_SHORT) {
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE missing arg\n"));
+				orc = CONFREJ;
+				break;
+			} else if (!(ao->neg_upap || ao->neg_chap)) {
+				/*
+				 * Reject the option if we're not willing to authenticate.
+				 */
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE not allowed\n"));
+				orc = CONFREJ;
+				break;
+			}
+			GETSHORT(cishort, p);
+			
+			/*
+			 * Authtype must be UPAP or CHAP.
+			 *
+			 * Note: if both ao->neg_upap and ao->neg_chap are set,
+			 * and the peer sends a Configure-Request with two
+			 * authenticate-protocol requests, one for CHAP and one
+			 * for UPAP, then we will reject the second request.
+			 * Whether we end up doing CHAP or UPAP depends then on
+			 * the ordering of the CIs in the peer's Configure-Request.
+			 */
+			
+			if (cishort == PPP_PAP) {
+				if (ho->neg_chap) {	/* we've already accepted CHAP */
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP already accepted\n"));
+					orc = CONFREJ;
+					break;
+				} else if (cilen != CILEN_SHORT) {
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP bad len\n"));
+					orc = CONFREJ;
+					break;
+				}
+				if (!ao->neg_upap) {	/* we don't want to do PAP */
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE PAP not allowed\n"));
+					orc = CONFNAK;	/* NAK it and suggest CHAP */
+					PUTCHAR(CI_AUTHTYPE, nakp);
+					PUTCHAR(CILEN_CHAP, nakp);
+					PUTSHORT(PPP_CHAP, nakp);
+					PUTCHAR(ao->chap_mdtype, nakp);
+					break;
+				}
+				ho->neg_upap = 1;
+#if TRACELCP > 0
+				snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PAP (%X)", cishort);
+				traceNdx = strlen(traceBuf);
+#endif
+				break;
+			}
+			if (cishort == PPP_CHAP) {
+				if (ho->neg_upap) {	/* we've already accepted PAP */
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP accepted PAP\n"));
+					orc = CONFREJ;
+					break;
+				} else if (cilen != CILEN_CHAP) {
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP bad len\n"));
+					orc = CONFREJ;
+					break;
+				}
+				if (!ao->neg_chap) {	/* we don't want to do CHAP */
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP not allowed\n"));
+					orc = CONFNAK;	/* NAK it and suggest PAP */
+					PUTCHAR(CI_AUTHTYPE, nakp);
+					PUTCHAR(CILEN_SHORT, nakp);
+					PUTSHORT(PPP_PAP, nakp);
+					break;
+				}
+				GETCHAR(cichar, p);	/* get digest type*/
+				if (cichar != CHAP_DIGEST_MD5
+#ifdef CHAPMS
+						&& cichar != CHAP_MICROSOFT
+#endif
+				) {
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP digest=%d\n", cichar));
+					orc = CONFNAK;
+					PUTCHAR(CI_AUTHTYPE, nakp);
+					PUTCHAR(CILEN_CHAP, nakp);
+					PUTSHORT(PPP_CHAP, nakp);
+					PUTCHAR(ao->chap_mdtype, nakp);
+					break;
+				}
+#if TRACELCP > 0
+				snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CHAP %X,%d", cishort, cichar);
+				traceNdx = strlen(traceBuf);
+#endif
+				ho->chap_mdtype = cichar; /* save md type */
+				ho->neg_chap = 1;
+				break;
+			}
+			
+			/*
+			 * We don't recognize the protocol they're asking for.
+			 * Nak it with something we're willing to do.
+			 * (At this point we know ao->neg_upap || ao->neg_chap.)
+			 */
+			orc = CONFNAK;
+			PUTCHAR(CI_AUTHTYPE, nakp);
+			if (ao->neg_chap) {
+				LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req CHAP\n", cishort));
+				PUTCHAR(CILEN_CHAP, nakp);
+				PUTSHORT(PPP_CHAP, nakp);
+				PUTCHAR(ao->chap_mdtype, nakp);
+			} 
+			else {
+				LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req PAP\n", cishort));
+				PUTCHAR(CILEN_SHORT, nakp);
+				PUTSHORT(PPP_PAP, nakp);
+			}
+			break;
+		
+		case CI_QUALITY:
+			GETSHORT(cishort, p);
+			GETLONG(cilong, p);
+#if TRACELCP > 0
+			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " QUALITY (%x %x)", cishort, (unsigned int) cilong);
+			traceNdx = strlen(traceBuf);
+#endif
+
+			if (!ao->neg_lqr ||
+					cilen != CILEN_LQR) {
+				orc = CONFREJ;
+				break;
+			}
+			
+			/*
+			 * Check the protocol and the reporting period.
+			 * XXX When should we Nak this, and what with?
+			 */
+			if (cishort != PPP_LQR) {
+				orc = CONFNAK;
+				PUTCHAR(CI_QUALITY, nakp);
+				PUTCHAR(CILEN_LQR, nakp);
+				PUTSHORT(PPP_LQR, nakp);
+				PUTLONG(ao->lqr_period, nakp);
+				break;
+			}
+			break;
+		
+		case CI_MAGICNUMBER:
+			if (!(ao->neg_magicnumber || go->neg_magicnumber) ||
+					cilen != CILEN_LONG) {
+				orc = CONFREJ;
+				break;
+			}
+			GETLONG(cilong, p);
+#if TRACELCP > 0
+			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MAGICNUMBER (%lX)", cilong);
+			traceNdx = strlen(traceBuf);
+#endif
+
+			/*
+			 * He must have a different magic number.
+			 */
+			if (go->neg_magicnumber &&
+					cilong == go->magicnumber) {
+				cilong = magic();	/* Don't put magic() inside macro! */
+				orc = CONFNAK;
+				PUTCHAR(CI_MAGICNUMBER, nakp);
+				PUTCHAR(CILEN_LONG, nakp);
+				PUTLONG(cilong, nakp);
+				break;
+			}
+			ho->neg_magicnumber = 1;
+			ho->magicnumber = cilong;
+			break;
+		
+		
+		case CI_PCOMPRESSION:
+#if TRACELCP > 0
+			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PCOMPRESSION");
+			traceNdx = strlen(traceBuf);
+#endif
+			if (!ao->neg_pcompression ||
+					cilen != CILEN_VOID) {
+				orc = CONFREJ;
+				break;
+			}
+			ho->neg_pcompression = 1;
+			break;
+		
+		case CI_ACCOMPRESSION:
+#if TRACELCP > 0
+			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ACCOMPRESSION");
+			traceNdx = strlen(traceBuf);
+#endif
+			if (!ao->neg_accompression ||
+					cilen != CILEN_VOID) {
+				orc = CONFREJ;
+				break;
+			}
+			ho->neg_accompression = 1;
+			break;
+		
+		case CI_MRRU:
+#if TRACELCP > 0
+			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_MRRU");
+			traceNdx = strlen(traceBuf);
+#endif
+			orc = CONFREJ;
+			break;
+		
+		case CI_SSNHF:
+#if TRACELCP > 0
+			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_SSNHF");
+			traceNdx = strlen(traceBuf);
+#endif
+			orc = CONFREJ;
+			break;
+		
+		case CI_EPDISC:
+#if TRACELCP > 0
+			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_EPDISC");
+			traceNdx = strlen(traceBuf);
+#endif
+			orc = CONFREJ;
+			break;
+		
+		default:
+#if TRACELCP
+			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " unknown %d", citype);
+			traceNdx = strlen(traceBuf);
+#endif
+			orc = CONFREJ;
+			break;
+		}
+		
+	endswitch:
+#if TRACELCP
+		if (traceNdx >= 80 - 32) {
+			LCPDEBUG((LOG_INFO, "lcp_reqci: rcvd%s\n", traceBuf));
+			traceNdx = 0;
+		}
+#endif
+		if (orc == CONFACK &&		/* Good CI */
+				rc != CONFACK)		/*  but prior CI wasnt? */
+			continue;			/* Don't send this one */
+		
+		if (orc == CONFNAK) {		/* Nak this CI? */
+			if (reject_if_disagree	/* Getting fed up with sending NAKs? */
+					&& citype != CI_MAGICNUMBER) {
+				orc = CONFREJ;		/* Get tough if so */
+			} 
+			else {
+				if (rc == CONFREJ)	/* Rejecting prior CI? */
+					continue;		/* Don't send this one */
+				rc = CONFNAK;
+			}
+		}
+		if (orc == CONFREJ) {		/* Reject this CI */
+			rc = CONFREJ;
+			if (cip != rejp)		/* Need to move rejected CI? */
+				BCOPY(cip, rejp, cilen); /* Move it */
+			INCPTR(cilen, rejp);	/* Update output pointer */
+		}
+	}
+	
+	/*
+	 * If we wanted to send additional NAKs (for unsent CIs), the
+	 * code would go here.  The extra NAKs would go at *nakp.
+	 * At present there are no cases where we want to ask the
+	 * peer to negotiate an option.
+	 */
+	
+	switch (rc) {
+	case CONFACK:
+		*lenp = (int)(next - inp);
+		break;
+	case CONFNAK:
+		/*
+		 * Copy the Nak'd options from the nak_buffer to the caller's buffer.
+		 */
+		*lenp = (int)(nakp - nak_buffer);
+		BCOPY(nak_buffer, inp, *lenp);
+		break;
+	case CONFREJ:
+		*lenp = (int)(rejp - inp);
+		break;
+	}
+	
+#if TRACELCP > 0
+	if (traceNdx > 0) {
+		LCPDEBUG((LOG_INFO, "lcp_reqci: %s\n", traceBuf));
+	}
+#endif
+	LCPDEBUG((LOG_INFO, "lcp_reqci: returning CONF%s.\n", CODENAME(rc)));
+	return (rc);			/* Return final code */
+}
+
+
+/*
+ * lcp_up - LCP has come UP.
+ */
+static void lcp_up(fsm *f)
+{
+	lcp_options *wo = &lcp_wantoptions[f->unit];
+	lcp_options *ho = &lcp_hisoptions[f->unit];
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	lcp_options *ao = &lcp_allowoptions[f->unit];
+	
+	if (!go->neg_magicnumber)
+		go->magicnumber = 0;
+	if (!ho->neg_magicnumber)
+		ho->magicnumber = 0;
+	
+	/*
+	* Set our MTU to the smaller of the MTU we wanted and
+	* the MRU our peer wanted.  If we negotiated an MRU,
+	* set our MRU to the larger of value we wanted and
+	* the value we got in the negotiation.
+	*/
+	ppp_send_config(f->unit, LWIP_MIN(ao->mru, (ho->neg_mru? ho->mru: PPP_MRU)),
+				(ho->neg_asyncmap? ho->asyncmap: 0xffffffffl),
+				ho->neg_pcompression, ho->neg_accompression);
+	/*
+	* If the asyncmap hasn't been negotiated, we really should
+	* set the receive asyncmap to ffffffff, but we set it to 0
+	* for backwards contemptibility.
+	*/
+	ppp_recv_config(f->unit, (go->neg_mru? LWIP_MAX(wo->mru, go->mru): PPP_MRU),
+				(go->neg_asyncmap? go->asyncmap: 0x00000000),
+				go->neg_pcompression, go->neg_accompression);
+	
+	if (ho->neg_mru)
+		peer_mru[f->unit] = ho->mru;
+	
+	lcp_echo_lowerup(f->unit);  /* Enable echo messages */
+	
+	link_established(f->unit);
+}
+
+
+/*
+ * lcp_down - LCP has gone DOWN.
+ *
+ * Alert other protocols.
+ */
+static void lcp_down(fsm *f)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	
+	lcp_echo_lowerdown(f->unit);
+	
+	link_down(f->unit);
+	
+	ppp_send_config(f->unit, PPP_MRU, 0xffffffffl, 0, 0);
+	ppp_recv_config(f->unit, PPP_MRU,
+				(go->neg_asyncmap? go->asyncmap: 0x00000000),
+				go->neg_pcompression, go->neg_accompression);
+	peer_mru[f->unit] = PPP_MRU;
+}
+
+
+/*
+ * lcp_starting - LCP needs the lower layer up.
+ */
+static void lcp_starting(fsm *f)
+{
+	link_required(f->unit);
+}
+
+
+/*
+ * lcp_finished - LCP has finished with the lower layer.
+ */
+static void lcp_finished(fsm *f)
+{
+	link_terminated(f->unit);
+}
+
+
+#if 0
+/*
+ * print_string - print a readable representation of a string using
+ * printer.
+ */
+static void print_string(
+    char *p,
+    int len,
+    void (*printer) (void *, char *, ...),
+    void *arg
+)
+{
+    int c;
+    
+    printer(arg, "\"");
+    for (; len > 0; --len) {
+        c = *p++;
+        if (' ' <= c && c <= '~') {
+            if (c == '\\' || c == '"')
+                printer(arg, "\\");
+            printer(arg, "%c", c);
+        } else {
+            switch (c) {
+            case '\n':
+                printer(arg, "\\n");
+                break;
+            case '\r':
+                printer(arg, "\\r");
+                break;
+            case '\t':
+                printer(arg, "\\t");
+                break;
+            default:
+                printer(arg, "\\%.3o", c);
+            }
+        }
+    }
+    printer(arg, "\"");
+}
+
+
+/*
+ * lcp_printpkt - print the contents of an LCP packet.
+ */
+static char *lcp_codenames[] = {
+	"ConfReq", "ConfAck", "ConfNak", "ConfRej",
+	"TermReq", "TermAck", "CodeRej", "ProtRej",
+	"EchoReq", "EchoRep", "DiscReq"
+};
+
+static int lcp_printpkt(
+	u_char *p,
+	int plen,
+	void (*printer) (void *, char *, ...),
+	void *arg
+)
+{
+	int code, id, len, olen;
+	u_char *pstart, *optend;
+	u_short cishort;
+	u32_t cilong;
+	
+	if (plen < HEADERLEN)
+		return 0;
+	pstart = p;
+	GETCHAR(code, p);
+	GETCHAR(id, p);
+	GETSHORT(len, p);
+	if (len < HEADERLEN || len > plen)
+		return 0;
+	
+	if (code >= 1 && code <= sizeof(lcp_codenames) / sizeof(char *))
+		printer(arg, " %s", lcp_codenames[code-1]);
+	else
+		printer(arg, " code=0x%x", code);
+	printer(arg, " id=0x%x", id);
+	len -= HEADERLEN;
+	switch (code) {
+	case CONFREQ:
+	case CONFACK:
+	case CONFNAK:
+	case CONFREJ:
+		/* print option list */
+		while (len >= 2) {
+			GETCHAR(code, p);
+			GETCHAR(olen, p);
+			p -= 2;
+			if (olen < 2 || olen > len) {
+				break;
+			}
+			printer(arg, " <");
+			len -= olen;
+			optend = p + olen;
+			switch (code) {
+			case CI_MRU:
+				if (olen == CILEN_SHORT) {
+					p += 2;
+					GETSHORT(cishort, p);
+					printer(arg, "mru %d", cishort);
+				}
+				break;
+			case CI_ASYNCMAP:
+				if (olen == CILEN_LONG) {
+					p += 2;
+					GETLONG(cilong, p);
+					printer(arg, "asyncmap 0x%lx", cilong);
+				}
+				break;
+			case CI_AUTHTYPE:
+				if (olen >= CILEN_SHORT) {
+					p += 2;
+					printer(arg, "auth ");
+					GETSHORT(cishort, p);
+					switch (cishort) {
+					case PPP_PAP:
+						printer(arg, "pap");
+						break;
+					case PPP_CHAP:
+						printer(arg, "chap");
+						break;
+					default:
+						printer(arg, "0x%x", cishort);
+					}
+				}
+				break;
+			case CI_QUALITY:
+				if (olen >= CILEN_SHORT) {
+					p += 2;
+					printer(arg, "quality ");
+					GETSHORT(cishort, p);
+					switch (cishort) {
+					case PPP_LQR:
+						printer(arg, "lqr");
+						break;
+					default:
+						printer(arg, "0x%x", cishort);
+					}
+				}
+				break;
+			case CI_CALLBACK:
+				if (olen >= CILEN_CHAR) {
+					p += 2;
+					printer(arg, "callback ");
+					GETSHORT(cishort, p);
+					switch (cishort) {
+					case CBCP_OPT:
+						printer(arg, "CBCP");
+						break;
+					default:
+						printer(arg, "0x%x", cishort);
+					}
+				}
+				break;
+			case CI_MAGICNUMBER:
+				if (olen == CILEN_LONG) {
+					p += 2;
+					GETLONG(cilong, p);
+					printer(arg, "magic 0x%x", cilong);
+				}
+				break;
+			case CI_PCOMPRESSION:
+				if (olen == CILEN_VOID) {
+					p += 2;
+					printer(arg, "pcomp");
+				}
+				break;
+			case CI_ACCOMPRESSION:
+				if (olen == CILEN_VOID) {
+					p += 2;
+					printer(arg, "accomp");
+				}
+				break;
+			}
+			while (p < optend) {
+				GETCHAR(code, p);
+				printer(arg, " %.2x", code);
+			}
+			printer(arg, ">");
+		}
+		break;
+	
+	case TERMACK:
+	case TERMREQ:
+		if (len > 0 && *p >= ' ' && *p < 0x7f) {
+			printer(arg, " ");
+			print_string((char*)p, len, printer, arg);
+			p += len;
+			len = 0;
+		}
+		break;
+	
+	case ECHOREQ:
+	case ECHOREP:
+	case DISCREQ:
+		if (len >= 4) {
+			GETLONG(cilong, p);
+			printer(arg, " magic=0x%x", cilong);
+			p += 4;
+			len -= 4;
+		}
+		break;
+	}
+	
+	/* print the rest of the bytes in the packet */
+	for (; len > 0; --len) {
+		GETCHAR(code, p);
+		printer(arg, " %.2x", code);
+	}
+	
+	return (int)(p - pstart);
+}
+#endif
+
+/*
+ * Time to shut down the link because there is nothing out there.
+ */
+
+static void LcpLinkFailure (fsm *f)
+{
+	if (f->state == OPENED) {
+		LCPDEBUG((LOG_INFO, "No response to %d echo-requests\n", lcp_echos_pending));
+		LCPDEBUG((LOG_NOTICE, "Serial link appears to be disconnected.\n"));
+		lcp_close(f->unit, "Peer not responding");
+	}
+}
+
+/*
+ * Timer expired for the LCP echo requests from this process.
+ */
+
+static void LcpEchoCheck (fsm *f)
+{
+	LcpSendEchoRequest (f);
+	
+	/*
+	 * Start the timer for the next interval.
+	 */
+	LWIP_ASSERT("lcp_echo_timer_running == 0", lcp_echo_timer_running == 0);
+
+	TIMEOUT (LcpEchoTimeout, f, lcp_echo_interval);
+	lcp_echo_timer_running = 1;
+}
+
+/*
+ * LcpEchoTimeout - Timer expired on the LCP echo
+ */
+
+static void LcpEchoTimeout (void *arg)
+{
+	if (lcp_echo_timer_running != 0) {
+		lcp_echo_timer_running = 0;
+		LcpEchoCheck ((fsm *) arg);
+	}
+}
+
+/*
+ * LcpEchoReply - LCP has received a reply to the echo
+ */
+static void lcp_received_echo_reply (fsm *f, int id, u_char *inp, int len)
+{
+	u32_t magic;
+	
+	(void)id;
+
+	/* Check the magic number - don't count replies from ourselves. */
+	if (len < 4) {
+		LCPDEBUG((LOG_WARNING, "lcp: received short Echo-Reply, length %d\n", len));
+		return;
+	}
+	GETLONG(magic, inp);
+	if (lcp_gotoptions[f->unit].neg_magicnumber
+			&& magic == lcp_gotoptions[f->unit].magicnumber) {
+		LCPDEBUG((LOG_WARNING, "appear to have received our own echo-reply!\n"));
+		return;
+	}
+	
+	/* Reset the number of outstanding echo frames */
+	lcp_echos_pending = 0;
+}
+
+/*
+ * LcpSendEchoRequest - Send an echo request frame to the peer
+ */
+
+static void LcpSendEchoRequest (fsm *f)
+{
+	u32_t lcp_magic;
+	u_char pkt[4], *pktp;
+	
+	/*
+	* Detect the failure of the peer at this point.
+	*/
+	if (lcp_echo_fails != 0) {
+		if (lcp_echos_pending++ >= lcp_echo_fails) {
+			LcpLinkFailure(f);
+			lcp_echos_pending = 0;
+		}
+	}
+	
+	/*
+	* Make and send the echo request frame.
+	*/
+	if (f->state == OPENED) {
+		lcp_magic = lcp_gotoptions[f->unit].magicnumber;
+		pktp = pkt;
+		PUTLONG(lcp_magic, pktp);
+		fsm_sdata(f, ECHOREQ, (u_char)(lcp_echo_number++ & 0xFF), pkt, (int)(pktp - pkt));
+	}
+}
+
+/*
+ * lcp_echo_lowerup - Start the timer for the LCP frame
+ */
+
+static void lcp_echo_lowerup (int unit)
+{
+	fsm *f = &lcp_fsm[unit];
+	
+	/* Clear the parameters for generating echo frames */
+	lcp_echos_pending      = 0;
+	lcp_echo_number        = 0;
+	lcp_echo_timer_running = 0;
+	
+	/* If a timeout interval is specified then start the timer */
+	if (lcp_echo_interval != 0)
+		LcpEchoCheck (f);
+}
+
+/*
+ * lcp_echo_lowerdown - Stop the timer for the LCP frame
+ */
+
+static void lcp_echo_lowerdown (int unit)
+{
+	fsm *f = &lcp_fsm[unit];
+	
+	if (lcp_echo_timer_running != 0) {
+		UNTIMEOUT (LcpEchoTimeout, f);
+		lcp_echo_timer_running = 0;
+	}
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/lcp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/lcp.h
new file mode 100644
index 0000000..2c0c340
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/lcp.h
@@ -0,0 +1,169 @@
+/*****************************************************************************
+* lcp.h - Network Link Control Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*	Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * lcp.h - Link Control Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: lcp.h,v 1.1 2003/05/27 14:37:56 jani Exp $
+ */
+
+#ifndef LCP_H
+#define LCP_H
+
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+/*
+ * Options.
+ */
+#define CI_MRU		1	/* Maximum Receive Unit */
+#define CI_ASYNCMAP	2	/* Async Control Character Map */
+#define CI_AUTHTYPE	3	/* Authentication Type */
+#define CI_QUALITY	4	/* Quality Protocol */
+#define CI_MAGICNUMBER	5	/* Magic Number */
+#define CI_PCOMPRESSION	7	/* Protocol Field Compression */
+#define CI_ACCOMPRESSION 8	/* Address/Control Field Compression */
+#define CI_CALLBACK	13	/* callback */
+#define CI_MRRU		17	/* max reconstructed receive unit; multilink */
+#define CI_SSNHF	18	/* short sequence numbers for multilink */
+#define CI_EPDISC	19	/* endpoint discriminator */
+
+/*
+ * LCP-specific packet types.
+ */
+#define PROTREJ		8	/* Protocol Reject */
+#define ECHOREQ		9	/* Echo Request */
+#define ECHOREP		10	/* Echo Reply */
+#define DISCREQ		11	/* Discard Request */
+#define CBCP_OPT	6	/* Use callback control protocol */
+
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * The state of options is described by an lcp_options structure.
+ */
+typedef struct lcp_options {
+    u_int passive : 1;			/* Don't die if we don't get a response */
+    u_int silent : 1;				/* Wait for the other end to start first */
+    u_int restart : 1;			/* Restart vs. exit after close */
+    u_int neg_mru : 1;			/* Negotiate the MRU? */
+    u_int neg_asyncmap : 1;		/* Negotiate the async map? */
+    u_int neg_upap : 1;			/* Ask for UPAP authentication? */
+    u_int neg_chap : 1;			/* Ask for CHAP authentication? */
+    u_int neg_magicnumber : 1;	/* Ask for magic number? */
+    u_int neg_pcompression : 1;	/* HDLC Protocol Field Compression? */
+    u_int neg_accompression : 1;	/* HDLC Address/Control Field Compression? */
+    u_int neg_lqr : 1;			/* Negotiate use of Link Quality Reports */
+    u_int neg_cbcp : 1;			/* Negotiate use of CBCP */
+#ifdef PPP_MULTILINK
+    u_int neg_mrru : 1;			/* Negotiate multilink MRRU */
+    u_int neg_ssnhf : 1;		/* Negotiate short sequence numbers */
+    u_int neg_endpoint : 1;		/* Negotiate endpoint discriminator */
+#endif
+    u_short mru;			/* Value of MRU */
+#ifdef PPP_MULTILINK
+    u_short mrru;			/* Value of MRRU, and multilink enable */
+#endif
+    u_char chap_mdtype;			/* which MD type (hashing algorithm) */
+    u32_t asyncmap;			/* Value of async map */
+    u32_t magicnumber;
+    int numloops;				/* Number of loops during magic number neg. */
+    u32_t lqr_period;		/* Reporting period for LQR 1/100ths second */
+#ifdef PPP_MULTILINK
+    struct epdisc endpoint;	/* endpoint discriminator */
+#endif
+} lcp_options;
+
+/*
+ * Values for phase from BSD pppd.h based on RFC 1661.
+ */
+typedef enum {
+	PHASE_DEAD = 0,
+	PHASE_INITIALIZE,
+	PHASE_ESTABLISH,
+	PHASE_AUTHENTICATE,
+	PHASE_CALLBACK,
+	PHASE_NETWORK,
+	PHASE_TERMINATE
+} LinkPhase;
+
+
+/*****************************
+*** PUBLIC DATA STRUCTURES ***
+*****************************/
+
+extern LinkPhase lcp_phase[NUM_PPP];	/* Phase of link session (RFC 1661) */
+extern lcp_options lcp_wantoptions[];
+extern lcp_options lcp_gotoptions[];
+extern lcp_options lcp_allowoptions[];
+extern lcp_options lcp_hisoptions[];
+extern ext_accm xmit_accm[];
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+void lcp_init (int);
+void lcp_open (int);
+void lcp_close (int, char *);
+void lcp_lowerup (int);
+void lcp_lowerdown (int);
+void lcp_sprotrej (int, u_char *, int);	/* send protocol reject */
+
+extern struct protent lcp_protent;
+
+/* Default number of times we receive our magic number from the peer
+   before deciding the link is looped-back. */
+#define DEFLOOPBACKFAIL	10
+
+#endif /* LCP_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/magic.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/magic.c
new file mode 100644
index 0000000..6e9d475
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/magic.c
@@ -0,0 +1,79 @@
+/*****************************************************************************
+* magic.c - Network Random Number Generator program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*	Original based on BSD magic.c.
+*****************************************************************************/
+/*
+ * magic.c - PPP Magic Number routines.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "ppp.h"
+#include "randm.h"
+#include "magic.h"
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * magicInit - Initialize the magic number generator.
+ *
+ * Since we use another random number generator that has its own
+ * initialization, we do nothing here.
+ */
+void magicInit()
+{
+	return;
+}
+
+/*
+ * magic - Returns the next magic number.
+ */
+u32_t magic()
+{
+    return avRandom();
+}
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/magic.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/magic.h
new file mode 100644
index 0000000..6e9b10b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/magic.h
@@ -0,0 +1,64 @@
+/*****************************************************************************
+* magic.h - Network Random Number Generator header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * magic.h - PPP Magic Number definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: magic.h,v 1.1 2003/05/27 14:37:56 jani Exp $
+ */
+
+#ifndef MAGIC_H
+#define MAGIC_H
+
+/*****************************************************************************
+************************** PUBLIC FUNCTIONS **********************************
+*****************************************************************************/
+
+void magicInit(void);   /* Initialize the magic number generator */
+u32_t magic(void);  /* Returns the next magic number */
+
+#endif /* MAGIC_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/md5.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/md5.c
new file mode 100644
index 0000000..488d64a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/md5.c
@@ -0,0 +1,306 @@
+/*
+ ***********************************************************************
+ ** md5.c -- the source code for MD5 routines                         **
+ ** RSA Data Security, Inc. MD5 Message-Digest Algorithm              **
+ ** Created: 2/17/90 RLR                                              **
+ ** Revised: 1/91 SRD,AJ,BSK,JT Reference C ver., 7/10 constant corr. **
+ ***********************************************************************
+ */
+
+/*
+ ***********************************************************************
+ ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved.  **
+ **                                                                   **
+ ** License to copy and use this software is granted provided that    **
+ ** it is identified as the "RSA Data Security, Inc. MD5 Message-     **
+ ** Digest Algorithm" in all material mentioning or referencing this  **
+ ** software or this function.                                        **
+ **                                                                   **
+ ** License is also granted to make and use derivative works          **
+ ** provided that such works are identified as "derived from the RSA  **
+ ** Data Security, Inc. MD5 Message-Digest Algorithm" in all          **
+ ** material mentioning or referencing the derived work.              **
+ **                                                                   **
+ ** RSA Data Security, Inc. makes no representations concerning       **
+ ** either the merchantability of this software or the suitability    **
+ ** of this software for any particular purpose.  It is provided "as  **
+ ** is" without express or implied warranty of any kind.              **
+ **                                                                   **
+ ** These notices must be retained in any copies of any part of this  **
+ ** documentation and/or software.                                    **
+ ***********************************************************************
+ */
+
+#include "ppp.h"
+#include "md5.h"
+#include "pppdebug.h"
+
+#if CHAP_SUPPORT > 0 || MD5_SUPPORT > 0
+
+/*
+ ***********************************************************************
+ **  Message-digest routines:                                         **
+ **  To form the message digest for a message M                       **
+ **    (1) Initialize a context buffer mdContext using MD5Init        **
+ **    (2) Call MD5Update on mdContext and M                          **
+ **    (3) Call MD5Final on mdContext                                 **
+ **  The message digest is now in mdContext->digest[0...15]           **
+ ***********************************************************************
+ */
+
+/* forward declaration */
+static void Transform (u32_t *buf, u32_t *in);
+
+static unsigned char PADDING[64] = {
+  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+/* F, G, H and I are basic MD5 functions */
+#define F(x, y, z) (((x) & (y)) | ((~x) & (z)))
+#define G(x, y, z) (((x) & (z)) | ((y) & (~z)))
+#define H(x, y, z) ((x) ^ (y) ^ (z))
+#define I(x, y, z) ((y) ^ ((x) | (~z)))
+
+/* ROTATE_LEFT rotates x left n bits */
+#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n))))
+
+/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4 */
+/* Rotation is separate from addition to prevent recomputation */
+#define FF(a, b, c, d, x, s, ac) \
+  {(a) += F ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+#define GG(a, b, c, d, x, s, ac) \
+  {(a) += G ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+#define HH(a, b, c, d, x, s, ac) \
+  {(a) += H ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+#define II(a, b, c, d, x, s, ac) \
+  {(a) += I ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+
+#ifdef __STDC__
+#define UL(x)	x##UL
+#else
+#ifdef WIN32
+#define UL(x)	x##UL
+#else
+#define UL(x)	x
+#endif
+#endif
+
+/* The routine MD5Init initializes the message-digest context
+   mdContext. All fields are set to zero.
+ */
+void MD5Init (MD5_CTX *mdContext)
+{
+  mdContext->i[0] = mdContext->i[1] = (u32_t)0;
+
+  /* Load magic initialization constants.
+   */
+  mdContext->buf[0] = (u32_t)0x67452301UL;
+  mdContext->buf[1] = (u32_t)0xefcdab89UL;
+  mdContext->buf[2] = (u32_t)0x98badcfeUL;
+  mdContext->buf[3] = (u32_t)0x10325476UL;
+}
+
+/* The routine MD5Update updates the message-digest context to
+   account for the presence of each of the characters inBuf[0..inLen-1]
+   in the message whose digest is being computed.
+ */
+void MD5Update(MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen)
+{
+  u32_t in[16];
+  int mdi;
+  unsigned int i, ii;
+
+#if 0
+  ppp_trace(LOG_INFO, "MD5Update: %u:%.*H\n", inLen, MIN(inLen, 20) * 2, inBuf);
+  ppp_trace(LOG_INFO, "MD5Update: %u:%s\n", inLen, inBuf);
+#endif
+  
+  /* compute number of bytes mod 64 */
+  mdi = (int)((mdContext->i[0] >> 3) & 0x3F);
+
+  /* update number of bits */
+  if ((mdContext->i[0] + ((u32_t)inLen << 3)) < mdContext->i[0])
+    mdContext->i[1]++;
+  mdContext->i[0] += ((u32_t)inLen << 3);
+  mdContext->i[1] += ((u32_t)inLen >> 29);
+
+  while (inLen--) {
+    /* add new character to buffer, increment mdi */
+    mdContext->in[mdi++] = *inBuf++;
+
+    /* transform if necessary */
+    if (mdi == 0x40) {
+      for (i = 0, ii = 0; i < 16; i++, ii += 4)
+        in[i] = (((u32_t)mdContext->in[ii+3]) << 24) |
+                (((u32_t)mdContext->in[ii+2]) << 16) |
+				(((u32_t)mdContext->in[ii+1]) << 8) |
+                ((u32_t)mdContext->in[ii]);
+      Transform (mdContext->buf, in);
+      mdi = 0;
+    }
+  }
+}
+
+/* The routine MD5Final terminates the message-digest computation and
+   ends with the desired message digest in mdContext->digest[0...15].
+ */
+void MD5Final (unsigned char hash[], MD5_CTX *mdContext)
+{
+  u32_t in[16];
+  int mdi;
+  unsigned int i, ii;
+  unsigned int padLen;
+
+  /* save number of bits */
+  in[14] = mdContext->i[0];
+  in[15] = mdContext->i[1];
+
+  /* compute number of bytes mod 64 */
+  mdi = (int)((mdContext->i[0] >> 3) & 0x3F);
+
+  /* pad out to 56 mod 64 */
+  padLen = (mdi < 56) ? (56 - mdi) : (120 - mdi);
+  MD5Update (mdContext, PADDING, padLen);
+
+  /* append length in bits and transform */
+  for (i = 0, ii = 0; i < 14; i++, ii += 4)
+    in[i] = (((u32_t)mdContext->in[ii+3]) << 24) |
+            (((u32_t)mdContext->in[ii+2]) << 16) |
+            (((u32_t)mdContext->in[ii+1]) << 8) |
+            ((u32_t)mdContext->in[ii]);
+  Transform (mdContext->buf, in);
+
+  /* store buffer in digest */
+  for (i = 0, ii = 0; i < 4; i++, ii += 4) {
+    mdContext->digest[ii] = (unsigned char)(mdContext->buf[i] & 0xFF);
+	mdContext->digest[ii+1] =
+      (unsigned char)((mdContext->buf[i] >> 8) & 0xFF);
+    mdContext->digest[ii+2] =
+      (unsigned char)((mdContext->buf[i] >> 16) & 0xFF);
+    mdContext->digest[ii+3] =
+      (unsigned char)((mdContext->buf[i] >> 24) & 0xFF);
+  }
+  memcpy(hash, mdContext->digest, 16);
+}
+
+/* Basic MD5 step. Transforms buf based on in.
+ */
+static void Transform (u32_t *buf, u32_t *in)
+{
+  u32_t a = buf[0], b = buf[1], c = buf[2], d = buf[3];
+
+  /* Round 1 */
+#define S11 7
+#define S12 12
+#define S13 17
+#define S14 22
+  FF ( a, b, c, d, in[ 0], S11, UL(3614090360)); /* 1 */
+  FF ( d, a, b, c, in[ 1], S12, UL(3905402710)); /* 2 */
+  FF ( c, d, a, b, in[ 2], S13, UL( 606105819)); /* 3 */
+  FF ( b, c, d, a, in[ 3], S14, UL(3250441966)); /* 4 */
+  FF ( a, b, c, d, in[ 4], S11, UL(4118548399)); /* 5 */
+  FF ( d, a, b, c, in[ 5], S12, UL(1200080426)); /* 6 */
+  FF ( c, d, a, b, in[ 6], S13, UL(2821735955)); /* 7 */
+  FF ( b, c, d, a, in[ 7], S14, UL(4249261313)); /* 8 */
+  FF ( a, b, c, d, in[ 8], S11, UL(1770035416)); /* 9 */
+  FF ( d, a, b, c, in[ 9], S12, UL(2336552879)); /* 10 */
+  FF ( c, d, a, b, in[10], S13, UL(4294925233)); /* 11 */
+  FF ( b, c, d, a, in[11], S14, UL(2304563134)); /* 12 */
+  FF ( a, b, c, d, in[12], S11, UL(1804603682)); /* 13 */
+  FF ( d, a, b, c, in[13], S12, UL(4254626195)); /* 14 */
+  FF ( c, d, a, b, in[14], S13, UL(2792965006)); /* 15 */
+  FF ( b, c, d, a, in[15], S14, UL(1236535329)); /* 16 */
+
+  /* Round 2 */
+#define S21 5
+#define S22 9
+#define S23 14
+#define S24 20
+  GG ( a, b, c, d, in[ 1], S21, UL(4129170786)); /* 17 */
+  GG ( d, a, b, c, in[ 6], S22, UL(3225465664)); /* 18 */
+  GG ( c, d, a, b, in[11], S23, UL( 643717713)); /* 19 */
+  GG ( b, c, d, a, in[ 0], S24, UL(3921069994)); /* 20 */
+  GG ( a, b, c, d, in[ 5], S21, UL(3593408605)); /* 21 */
+  GG ( d, a, b, c, in[10], S22, UL(  38016083)); /* 22 */
+  GG ( c, d, a, b, in[15], S23, UL(3634488961)); /* 23 */
+  GG ( b, c, d, a, in[ 4], S24, UL(3889429448)); /* 24 */
+  GG ( a, b, c, d, in[ 9], S21, UL( 568446438)); /* 25 */
+  GG ( d, a, b, c, in[14], S22, UL(3275163606)); /* 26 */
+  GG ( c, d, a, b, in[ 3], S23, UL(4107603335)); /* 27 */
+  GG ( b, c, d, a, in[ 8], S24, UL(1163531501)); /* 28 */
+  GG ( a, b, c, d, in[13], S21, UL(2850285829)); /* 29 */
+  GG ( d, a, b, c, in[ 2], S22, UL(4243563512)); /* 30 */
+  GG ( c, d, a, b, in[ 7], S23, UL(1735328473)); /* 31 */
+  GG ( b, c, d, a, in[12], S24, UL(2368359562)); /* 32 */
+
+  /* Round 3 */
+#define S31 4
+#define S32 11
+#define S33 16
+#define S34 23
+  HH ( a, b, c, d, in[ 5], S31, UL(4294588738)); /* 33 */
+  HH ( d, a, b, c, in[ 8], S32, UL(2272392833)); /* 34 */
+  HH ( c, d, a, b, in[11], S33, UL(1839030562)); /* 35 */
+  HH ( b, c, d, a, in[14], S34, UL(4259657740)); /* 36 */
+  HH ( a, b, c, d, in[ 1], S31, UL(2763975236)); /* 37 */
+  HH ( d, a, b, c, in[ 4], S32, UL(1272893353)); /* 38 */
+  HH ( c, d, a, b, in[ 7], S33, UL(4139469664)); /* 39 */
+  HH ( b, c, d, a, in[10], S34, UL(3200236656)); /* 40 */
+  HH ( a, b, c, d, in[13], S31, UL( 681279174)); /* 41 */
+  HH ( d, a, b, c, in[ 0], S32, UL(3936430074)); /* 42 */
+  HH ( c, d, a, b, in[ 3], S33, UL(3572445317)); /* 43 */
+  HH ( b, c, d, a, in[ 6], S34, UL(  76029189)); /* 44 */
+  HH ( a, b, c, d, in[ 9], S31, UL(3654602809)); /* 45 */
+  HH ( d, a, b, c, in[12], S32, UL(3873151461)); /* 46 */
+  HH ( c, d, a, b, in[15], S33, UL( 530742520)); /* 47 */
+  HH ( b, c, d, a, in[ 2], S34, UL(3299628645)); /* 48 */
+
+  /* Round 4 */
+#define S41 6
+#define S42 10
+#define S43 15
+#define S44 21
+  II ( a, b, c, d, in[ 0], S41, UL(4096336452)); /* 49 */
+  II ( d, a, b, c, in[ 7], S42, UL(1126891415)); /* 50 */
+  II ( c, d, a, b, in[14], S43, UL(2878612391)); /* 51 */
+  II ( b, c, d, a, in[ 5], S44, UL(4237533241)); /* 52 */
+  II ( a, b, c, d, in[12], S41, UL(1700485571)); /* 53 */
+  II ( d, a, b, c, in[ 3], S42, UL(2399980690)); /* 54 */
+  II ( c, d, a, b, in[10], S43, UL(4293915773)); /* 55 */
+  II ( b, c, d, a, in[ 1], S44, UL(2240044497)); /* 56 */
+  II ( a, b, c, d, in[ 8], S41, UL(1873313359)); /* 57 */
+  II ( d, a, b, c, in[15], S42, UL(4264355552)); /* 58 */
+  II ( c, d, a, b, in[ 6], S43, UL(2734768916)); /* 59 */
+  II ( b, c, d, a, in[13], S44, UL(1309151649)); /* 60 */
+  II ( a, b, c, d, in[ 4], S41, UL(4149444226)); /* 61 */
+  II ( d, a, b, c, in[11], S42, UL(3174756917)); /* 62 */
+  II ( c, d, a, b, in[ 2], S43, UL( 718787259)); /* 63 */
+  II ( b, c, d, a, in[ 9], S44, UL(3951481745)); /* 64 */
+
+  buf[0] += a;
+  buf[1] += b;
+  buf[2] += c;
+  buf[3] += d;
+}
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/md5.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/md5.h
new file mode 100644
index 0000000..83d318c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/md5.h
@@ -0,0 +1,55 @@
+/*
+ ***********************************************************************
+ ** md5.h -- header file for implementation of MD5                    **
+ ** RSA Data Security, Inc. MD5 Message-Digest Algorithm              **
+ ** Created: 2/17/90 RLR                                              **
+ ** Revised: 12/27/90 SRD,AJ,BSK,JT Reference C version               **
+ ** Revised (for MD5): RLR 4/27/91                                    **
+ **   -- G modified to have y&~z instead of y&z                       **
+ **   -- FF, GG, HH modified to add in last register done             **
+ **   -- Access pattern: round 2 works mod 5, round 3 works mod 3     **
+ **   -- distinct additive constant for each step                     **
+ **   -- round 4 added, working mod 7                                 **
+ ***********************************************************************
+ */
+
+/*
+ ***********************************************************************
+ ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved.  **
+ **                                                                   **
+ ** License to copy and use this software is granted provided that    **
+ ** it is identified as the "RSA Data Security, Inc. MD5 Message-     **
+ ** Digest Algorithm" in all material mentioning or referencing this  **
+ ** software or this function.                                        **
+ **                                                                   **
+ ** License is also granted to make and use derivative works          **
+ ** provided that such works are identified as "derived from the RSA  **
+ ** Data Security, Inc. MD5 Message-Digest Algorithm" in all          **
+ ** material mentioning or referencing the derived work.              **
+ **                                                                   **
+ ** RSA Data Security, Inc. makes no representations concerning       **
+ ** either the merchantability of this software or the suitability    **
+ ** of this software for any particular purpose.  It is provided "as  **
+ ** is" without express or implied warranty of any kind.              **
+ **                                                                   **
+ ** These notices must be retained in any copies of any part of this  **
+ ** documentation and/or software.                                    **
+ ***********************************************************************
+ */
+
+#ifndef MD5_H
+#define MD5_H
+
+/* Data structure for MD5 (Message-Digest) computation */
+typedef struct {
+  u32_t i[2];                   /* number of _bits_ handled mod 2^64 */
+  u32_t buf[4];                                    /* scratch buffer */
+  unsigned char in[64];                              /* input buffer */
+  unsigned char digest[16];     /* actual digest after MD5Final call */
+} MD5_CTX;
+
+void MD5Init (MD5_CTX *mdContext);
+void MD5Update (MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen);
+void MD5Final (unsigned char hash[], MD5_CTX *mdContext);
+
+#endif /* MD5_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/pap.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/pap.c
new file mode 100644
index 0000000..4b105ef
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/pap.c
@@ -0,0 +1,608 @@
+/*****************************************************************************
+* pap.c - Network Password Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-12 Guy Lancaster , Global Election Systems Inc.
+*	Original.
+*****************************************************************************/
+/*
+ * upap.c - User/Password Authentication Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "ppp.h"
+#include "auth.h"
+#include "pap.h"
+#include "pppdebug.h"
+
+
+#if PAP_SUPPORT > 0
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Protocol entry points.
+ */
+static void upap_init (int);
+static void upap_lowerup (int);
+static void upap_lowerdown (int);
+static void upap_input (int, u_char *, int);
+static void upap_protrej (int);
+
+static void upap_timeout (void *);
+static void upap_reqtimeout (void *);
+static void upap_rauthreq (upap_state *, u_char *, int, int);
+static void upap_rauthack (upap_state *, u_char *, int, int);
+static void upap_rauthnak (upap_state *, u_char *, int, int);
+static void upap_sauthreq (upap_state *);
+static void upap_sresp (upap_state *, u_char, u_char, char *, int);
+
+
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+struct protent pap_protent = {
+    PPP_PAP,
+    upap_init,
+    upap_input,
+    upap_protrej,
+    upap_lowerup,
+    upap_lowerdown,
+    NULL,
+    NULL,
+#if 0
+    upap_printpkt,
+    NULL,
+#endif
+    1,
+    "PAP",
+#if 0
+    NULL,
+    NULL,
+    NULL
+#endif
+};
+
+upap_state upap[NUM_PPP];		/* UPAP state; one for each unit */
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ *  Set the default login name and password for the pap sessions
+ */
+void upap_setloginpasswd(int unit, const char *luser, const char *lpassword)
+{
+	upap_state *u = &upap[unit];
+	
+	/* Save the username and password we're given */
+	u->us_user = luser;
+	u->us_userlen = strlen(luser);
+	u->us_passwd = lpassword;
+	u->us_passwdlen = strlen(lpassword);
+}
+
+
+/*
+ * upap_authwithpeer - Authenticate us with our peer (start client).
+ *
+ * Set new state and send authenticate's.
+ */
+void upap_authwithpeer(int unit, char *user, char *password)
+{
+	upap_state *u = &upap[unit];
+	
+	UPAPDEBUG((LOG_INFO, "upap_authwithpeer: %d user=%s password=%s s=%d\n",
+				unit, user, password, u->us_clientstate));
+	
+	upap_setloginpasswd(unit, user, password);
+
+	u->us_transmits = 0;
+	
+	/* Lower layer up yet? */
+	if (u->us_clientstate == UPAPCS_INITIAL ||
+			u->us_clientstate == UPAPCS_PENDING) {
+		u->us_clientstate = UPAPCS_PENDING;
+		return;
+	}
+	
+	upap_sauthreq(u);			/* Start protocol */
+}
+
+
+/*
+ * upap_authpeer - Authenticate our peer (start server).
+ *
+ * Set new state.
+ */
+void upap_authpeer(int unit)
+{
+	upap_state *u = &upap[unit];
+	
+	/* Lower layer up yet? */
+	if (u->us_serverstate == UPAPSS_INITIAL ||
+			u->us_serverstate == UPAPSS_PENDING) {
+		u->us_serverstate = UPAPSS_PENDING;
+		return;
+	}
+	
+	u->us_serverstate = UPAPSS_LISTEN;
+	if (u->us_reqtimeout > 0)
+		TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout);
+}
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * upap_init - Initialize a UPAP unit.
+ */
+static void upap_init(int unit)
+{
+	upap_state *u = &upap[unit];
+
+	UPAPDEBUG((LOG_INFO, "upap_init: %d\n", unit));	
+	u->us_unit = unit;
+	u->us_user = NULL;
+	u->us_userlen = 0;
+	u->us_passwd = NULL;
+	u->us_passwdlen = 0;
+	u->us_clientstate = UPAPCS_INITIAL;
+	u->us_serverstate = UPAPSS_INITIAL;
+	u->us_id = 0;
+	u->us_timeouttime = UPAP_DEFTIMEOUT;
+	u->us_maxtransmits = 10;
+	u->us_reqtimeout = UPAP_DEFREQTIME;
+}
+
+/*
+ * upap_timeout - Retransmission timer for sending auth-reqs expired.
+ */
+static void upap_timeout(void *arg)
+{
+	upap_state *u = (upap_state *) arg;
+	
+	UPAPDEBUG((LOG_INFO, "upap_timeout: %d timeout %d expired s=%d\n", 
+				u->us_unit, u->us_timeouttime, u->us_clientstate));
+	
+	if (u->us_clientstate != UPAPCS_AUTHREQ)
+		return;
+	
+	if (u->us_transmits >= u->us_maxtransmits) {
+		/* give up in disgust */
+		UPAPDEBUG((LOG_ERR, "No response to PAP authenticate-requests\n"));
+		u->us_clientstate = UPAPCS_BADAUTH;
+		auth_withpeer_fail(u->us_unit, PPP_PAP);
+		return;
+	}
+	
+	upap_sauthreq(u);		/* Send Authenticate-Request */
+}
+
+
+/*
+ * upap_reqtimeout - Give up waiting for the peer to send an auth-req.
+ */
+static void upap_reqtimeout(void *arg)
+{
+	upap_state *u = (upap_state *) arg;
+	
+	if (u->us_serverstate != UPAPSS_LISTEN)
+		return;			/* huh?? */
+	
+	auth_peer_fail(u->us_unit, PPP_PAP);
+	u->us_serverstate = UPAPSS_BADAUTH;
+}
+
+
+/*
+ * upap_lowerup - The lower layer is up.
+ *
+ * Start authenticating if pending.
+ */
+static void upap_lowerup(int unit)
+{
+	upap_state *u = &upap[unit];
+	
+	UPAPDEBUG((LOG_INFO, "upap_lowerup: %d s=%d\n", unit, u->us_clientstate));
+	
+	if (u->us_clientstate == UPAPCS_INITIAL)
+		u->us_clientstate = UPAPCS_CLOSED;
+	else if (u->us_clientstate == UPAPCS_PENDING) {
+		upap_sauthreq(u);	/* send an auth-request */
+	}
+	
+	if (u->us_serverstate == UPAPSS_INITIAL)
+		u->us_serverstate = UPAPSS_CLOSED;
+	else if (u->us_serverstate == UPAPSS_PENDING) {
+		u->us_serverstate = UPAPSS_LISTEN;
+		if (u->us_reqtimeout > 0)
+			TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout);
+	}
+}
+
+
+/*
+ * upap_lowerdown - The lower layer is down.
+ *
+ * Cancel all timeouts.
+ */
+static void upap_lowerdown(int unit)
+{
+	upap_state *u = &upap[unit];
+	
+	UPAPDEBUG((LOG_INFO, "upap_lowerdown: %d s=%d\n", unit, u->us_clientstate));
+	
+	if (u->us_clientstate == UPAPCS_AUTHREQ)	/* Timeout pending? */
+		UNTIMEOUT(upap_timeout, u);		/* Cancel timeout */
+	if (u->us_serverstate == UPAPSS_LISTEN && u->us_reqtimeout > 0)
+		UNTIMEOUT(upap_reqtimeout, u);
+	
+	u->us_clientstate = UPAPCS_INITIAL;
+	u->us_serverstate = UPAPSS_INITIAL;
+}
+
+
+/*
+ * upap_protrej - Peer doesn't speak this protocol.
+ *
+ * This shouldn't happen.  In any case, pretend lower layer went down.
+ */
+static void upap_protrej(int unit)
+{
+	upap_state *u = &upap[unit];
+	
+	if (u->us_clientstate == UPAPCS_AUTHREQ) {
+		UPAPDEBUG((LOG_ERR, "PAP authentication failed due to protocol-reject\n"));
+		auth_withpeer_fail(unit, PPP_PAP);
+	}
+	if (u->us_serverstate == UPAPSS_LISTEN) {
+		UPAPDEBUG((LOG_ERR, "PAP authentication of peer failed (protocol-reject)\n"));
+		auth_peer_fail(unit, PPP_PAP);
+	}
+	upap_lowerdown(unit);
+}
+
+
+/*
+ * upap_input - Input UPAP packet.
+ */
+static void upap_input(int unit, u_char *inpacket, int l)
+{
+	upap_state *u = &upap[unit];
+	u_char *inp;
+	u_char code, id;
+	int len;
+	
+	/*
+	 * Parse header (code, id and length).
+	 * If packet too short, drop it.
+	 */
+	inp = inpacket;
+	if (l < UPAP_HEADERLEN) {
+		UPAPDEBUG((LOG_INFO, "pap_input: rcvd short header.\n"));
+		return;
+	}
+	GETCHAR(code, inp);
+	GETCHAR(id, inp);
+	GETSHORT(len, inp);
+	if (len < UPAP_HEADERLEN) {
+		UPAPDEBUG((LOG_INFO, "pap_input: rcvd illegal length.\n"));
+		return;
+	}
+	if (len > l) {
+		UPAPDEBUG((LOG_INFO, "pap_input: rcvd short packet.\n"));
+		return;
+	}
+	len -= UPAP_HEADERLEN;
+	
+	/*
+	 * Action depends on code.
+	 */
+	switch (code) {
+	case UPAP_AUTHREQ:
+		upap_rauthreq(u, inp, id, len);
+		break;
+	
+	case UPAP_AUTHACK:
+		upap_rauthack(u, inp, id, len);
+		break;
+	
+	case UPAP_AUTHNAK:
+		upap_rauthnak(u, inp, id, len);
+		break;
+	
+	default:				/* XXX Need code reject */
+		break;
+	}
+}
+
+
+/*
+ * upap_rauth - Receive Authenticate.
+ */
+static void upap_rauthreq(
+	upap_state *u, 
+	u_char *inp, 
+	int id,
+	int len
+)
+{
+	u_char ruserlen, rpasswdlen;
+	char *ruser, *rpasswd;
+	int retcode;
+	char *msg;
+	int msglen;
+	
+	UPAPDEBUG((LOG_INFO, "pap_rauth: Rcvd id %d.\n", id));
+	
+	if (u->us_serverstate < UPAPSS_LISTEN)
+		return;
+	
+	/*
+	 * If we receive a duplicate authenticate-request, we are
+	 * supposed to return the same status as for the first request.
+	 */
+	if (u->us_serverstate == UPAPSS_OPEN) {
+		upap_sresp(u, UPAP_AUTHACK, id, "", 0);	/* return auth-ack */
+		return;
+	}
+	if (u->us_serverstate == UPAPSS_BADAUTH) {
+		upap_sresp(u, UPAP_AUTHNAK, id, "", 0);	/* return auth-nak */
+		return;
+	}
+	
+	/*
+	 * Parse user/passwd.
+	 */
+	if (len < sizeof (u_char)) {
+		UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
+		return;
+	}
+	GETCHAR(ruserlen, inp);
+	len -= sizeof (u_char) + ruserlen + sizeof (u_char);
+	if (len < 0) {
+		UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
+		return;
+	}
+	ruser = (char *) inp;
+	INCPTR(ruserlen, inp);
+	GETCHAR(rpasswdlen, inp);
+	if (len < rpasswdlen) {
+		UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
+		return;
+	}
+	rpasswd = (char *) inp;
+	
+	/*
+	 * Check the username and password given.
+	 */
+	retcode = check_passwd(u->us_unit, ruser, ruserlen, rpasswd,
+			   rpasswdlen, &msg, &msglen);
+	BZERO(rpasswd, rpasswdlen);
+	
+	upap_sresp(u, retcode, id, msg, msglen);
+	
+	if (retcode == UPAP_AUTHACK) {
+		u->us_serverstate = UPAPSS_OPEN;
+		auth_peer_success(u->us_unit, PPP_PAP, ruser, ruserlen);
+	} else {
+		u->us_serverstate = UPAPSS_BADAUTH;
+		auth_peer_fail(u->us_unit, PPP_PAP);
+	}
+	
+	if (u->us_reqtimeout > 0)
+		UNTIMEOUT(upap_reqtimeout, u);
+}
+
+
+/*
+ * upap_rauthack - Receive Authenticate-Ack.
+ */
+static void upap_rauthack(
+	upap_state *u,
+	u_char *inp,
+	int id,
+	int len
+)
+{
+	u_char msglen;
+	char *msg;
+	
+	UPAPDEBUG((LOG_INFO, "pap_rauthack: Rcvd id %d s=%d\n", id, u->us_clientstate));
+	
+	if (u->us_clientstate != UPAPCS_AUTHREQ) /* XXX */
+		return;
+	
+	/*
+	 * Parse message.
+	 */
+	if (len < sizeof (u_char)) {
+		UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n"));
+		return;
+	}
+	GETCHAR(msglen, inp);
+	len -= sizeof (u_char);
+	if (len < msglen) {
+		UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n"));
+		return;
+	}
+	msg = (char *) inp;
+	PRINTMSG(msg, msglen);
+	
+	u->us_clientstate = UPAPCS_OPEN;
+	
+	auth_withpeer_success(u->us_unit, PPP_PAP);
+}
+
+
+/*
+ * upap_rauthnak - Receive Authenticate-Nakk.
+ */
+static void upap_rauthnak(
+	upap_state *u,
+	u_char *inp,
+	int id,
+	int len
+)
+{
+	u_char msglen;
+	char *msg;
+	
+	UPAPDEBUG((LOG_INFO, "pap_rauthnak: Rcvd id %d s=%d\n", id, u->us_clientstate));
+	
+	if (u->us_clientstate != UPAPCS_AUTHREQ) /* XXX */
+		return;
+	
+	/*
+	 * Parse message.
+	 */
+	if (len < sizeof (u_char)) {
+		UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n"));
+		return;
+	}
+	GETCHAR(msglen, inp);
+	len -= sizeof (u_char);
+	if (len < msglen) {
+		UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n"));
+		return;
+	}
+	msg = (char *) inp;
+	PRINTMSG(msg, msglen);
+	
+	u->us_clientstate = UPAPCS_BADAUTH;
+	
+	UPAPDEBUG((LOG_ERR, "PAP authentication failed\n"));
+	auth_withpeer_fail(u->us_unit, PPP_PAP);
+}
+
+
+/*
+ * upap_sauthreq - Send an Authenticate-Request.
+ */
+static void upap_sauthreq(upap_state *u)
+{
+	u_char *outp;
+	int outlen;
+	
+	outlen = UPAP_HEADERLEN + 2 * sizeof (u_char) 
+			+ u->us_userlen + u->us_passwdlen;
+	outp = outpacket_buf[u->us_unit];
+	
+	MAKEHEADER(outp, PPP_PAP);
+	
+	PUTCHAR(UPAP_AUTHREQ, outp);
+	PUTCHAR(++u->us_id, outp);
+	PUTSHORT(outlen, outp);
+	PUTCHAR(u->us_userlen, outp);
+	BCOPY(u->us_user, outp, u->us_userlen);
+	INCPTR(u->us_userlen, outp);
+	PUTCHAR(u->us_passwdlen, outp);
+	BCOPY(u->us_passwd, outp, u->us_passwdlen);
+	
+	pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN);
+	
+	UPAPDEBUG((LOG_INFO, "pap_sauth: Sent id %d\n", u->us_id));
+	
+	TIMEOUT(upap_timeout, u, u->us_timeouttime);
+	++u->us_transmits;
+	u->us_clientstate = UPAPCS_AUTHREQ;
+}
+
+
+/*
+ * upap_sresp - Send a response (ack or nak).
+ */
+static void upap_sresp(
+	upap_state *u,
+	u_char code, 
+	u_char id,
+	char *msg,
+	int msglen
+)
+{
+	u_char *outp;
+	int outlen;
+	
+	outlen = UPAP_HEADERLEN + sizeof (u_char) + msglen;
+	outp = outpacket_buf[u->us_unit];
+	MAKEHEADER(outp, PPP_PAP);
+	
+	PUTCHAR(code, outp);
+	PUTCHAR(id, outp);
+	PUTSHORT(outlen, outp);
+	PUTCHAR(msglen, outp);
+	BCOPY(msg, outp, msglen);
+	pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN);
+	
+	UPAPDEBUG((LOG_INFO, "pap_sresp: Sent code %d, id %d s=%d\n", 
+				code, id, u->us_clientstate));
+}
+
+#if 0
+/*
+ * upap_printpkt - print the contents of a PAP packet.
+ */
+static int upap_printpkt(
+	u_char *p,
+	int plen,
+	void (*printer) (void *, char *, ...),
+	void *arg
+)
+{
+	(void)p;
+	(void)plen;
+	(void)printer;
+	(void)arg;
+	return 0;
+}
+#endif
+
+#endif /* PAP_SUPPORT */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/pap.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/pap.h
new file mode 100644
index 0000000..59eb2c7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/pap.h
@@ -0,0 +1,129 @@
+/*****************************************************************************
+* pap.h -  PPP Password Authentication Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*	Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * upap.h - User/Password Authentication Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+#ifndef PAP_H
+#define PAP_H
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+/*
+ * Packet header = Code, id, length.
+ */
+#define UPAP_HEADERLEN	(sizeof (u_char) + sizeof (u_char) + sizeof (u_short))
+
+
+/*
+ * UPAP codes.
+ */
+#define UPAP_AUTHREQ	1	/* Authenticate-Request */
+#define UPAP_AUTHACK	2	/* Authenticate-Ack */
+#define UPAP_AUTHNAK	3	/* Authenticate-Nak */
+
+/*
+ * Client states.
+ */
+#define UPAPCS_INITIAL	0	/* Connection down */
+#define UPAPCS_CLOSED	1	/* Connection up, haven't requested auth */
+#define UPAPCS_PENDING	2	/* Connection down, have requested auth */
+#define UPAPCS_AUTHREQ	3	/* We've sent an Authenticate-Request */
+#define UPAPCS_OPEN		4	/* We've received an Ack */
+#define UPAPCS_BADAUTH	5	/* We've received a Nak */
+
+/*
+ * Server states.
+ */
+#define UPAPSS_INITIAL	0	/* Connection down */
+#define UPAPSS_CLOSED	1	/* Connection up, haven't requested auth */
+#define UPAPSS_PENDING	2	/* Connection down, have requested auth */
+#define UPAPSS_LISTEN	3	/* Listening for an Authenticate */
+#define UPAPSS_OPEN		4	/* We've sent an Ack */
+#define UPAPSS_BADAUTH	5	/* We've sent a Nak */
+
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * Each interface is described by upap structure.
+ */
+typedef struct upap_state {
+    int us_unit;			/* Interface unit number */
+    const char *us_user;	/* User */
+    int us_userlen;			/* User length */
+    const char *us_passwd;	/* Password */
+    int us_passwdlen;		/* Password length */
+    int us_clientstate;		/* Client state */
+    int us_serverstate;		/* Server state */
+    u_char us_id;			/* Current id */
+    int us_timeouttime;		/* Timeout (seconds) for auth-req retrans. */
+    int us_transmits;		/* Number of auth-reqs sent */
+    int us_maxtransmits;	/* Maximum number of auth-reqs to send */
+    int us_reqtimeout;		/* Time to wait for auth-req from peer */
+} upap_state;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+extern upap_state upap[];
+
+void upap_setloginpasswd(int unit, const char *luser, const char *lpassword);
+void upap_authwithpeer (int, char *, char *);
+void upap_authpeer (int);
+
+extern struct protent pap_protent;
+
+#endif /* PAP_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/ppp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/ppp.c
new file mode 100644
index 0000000..afd4116
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/ppp.c
@@ -0,0 +1,1631 @@
+/*****************************************************************************
+* ppp.c - Network Point to Point Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*   Original.
+*****************************************************************************/
+
+/*
+ * ppp_defs.h - PPP definitions.
+ *
+ * if_pppvar.h - private structures and declarations for PPP.
+ *
+ * Copyright (c) 1994 The Australian National University.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, provided that the above copyright
+ * notice appears in all copies.  This software is provided without any
+ * warranty, express or implied. The Australian National University
+ * makes no representations about the suitability of this software for
+ * any purpose.
+ *
+ * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY
+ * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
+ * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
+ * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS,
+ * OR MODIFICATIONS.
+ */
+
+/*
+ * if_ppp.h - Point-to-Point Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+ 
+#include 
+ 
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "randm.h"
+#include "fsm.h"
+#if PAP_SUPPORT > 0
+#include "pap.h"
+#endif
+#if CHAP_SUPPORT > 0
+#include "chap.h"
+#endif
+#include "ipcp.h"
+#include "lcp.h"
+#include "magic.h"
+#include "auth.h"
+#if VJ_SUPPORT > 0
+#include "vj.h"
+#endif
+
+#include "pppdebug.h"
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+/*
+ * The basic PPP frame.
+ */
+#define PPP_ADDRESS(p)  (((u_char *)(p))[0])
+#define PPP_CONTROL(p)  (((u_char *)(p))[1])
+#define PPP_PROTOCOL(p) ((((u_char *)(p))[2] << 8) + ((u_char *)(p))[3])
+
+/* PPP packet parser states.  Current state indicates operation yet to be
+ * completed. */
+typedef enum {
+    PDIDLE = 0,                 /* Idle state - waiting. */
+    PDSTART,                    /* Process start flag. */
+    PDADDRESS,                  /* Process address field. */
+    PDCONTROL,                  /* Process control field. */
+    PDPROTOCOL1,                /* Process protocol field 1. */
+    PDPROTOCOL2,                /* Process protocol field 2. */
+    PDDATA                      /* Process data byte. */
+} PPPDevStates;
+
+#define ESCAPE_P(accm, c) ((accm)[(c) >> 3] & pppACCMMask[c & 0x07])
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+/*
+ * PPP interface control block.
+ */
+typedef struct PPPControl_s {
+    char openFlag;                      /* True when in use. */
+    char oldFrame;                      /* Old framing character for fd. */
+    sio_fd_t fd;                    /* File device ID of port. */
+    int  kill_link;                     /* Shut the link down. */
+    int  sig_hup;                       /* Carrier lost. */
+    int  if_up;                         /* True when the interface is up. */
+    int  errCode;                       /* Code indicating why interface is down. */
+    struct pbuf *inHead, *inTail;       /* The input packet. */
+    PPPDevStates inState;               /* The input process state. */
+    char inEscaped;                     /* Escape next character. */
+    u16_t inProtocol;                   /* The input protocol code. */
+    u16_t inFCS;                        /* Input Frame Check Sequence value. */
+    int  mtu;                           /* Peer's mru */
+    int  pcomp;                         /* Does peer accept protocol compression? */
+    int  accomp;                        /* Does peer accept addr/ctl compression? */
+    u_long lastXMit;                    /* Time of last transmission. */
+    ext_accm inACCM;                    /* Async-Ctl-Char-Map for input. */
+    ext_accm outACCM;                   /* Async-Ctl-Char-Map for output. */
+#if VJ_SUPPORT > 0
+    int  vjEnabled;                     /* Flag indicating VJ compression enabled. */
+    struct vjcompress vjComp;           /* Van Jabobsen compression header. */
+#endif
+
+    struct netif netif;
+
+    struct ppp_addrs addrs;
+
+    void (*linkStatusCB)(void *ctx, int errCode, void *arg);
+    void *linkStatusCtx;
+
+} PPPControl;
+
+
+/*
+ * Ioctl definitions.
+ */
+
+struct npioctl {
+    int     protocol;           /* PPP procotol, e.g. PPP_IP */
+    enum NPmode mode;
+};
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+static void pppMain(void *pd);
+static void pppDrop(PPPControl *pc);
+static void pppInProc(int pd, u_char *s, int l);
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+u_long subnetMask;
+
+static PPPControl pppControl[NUM_PPP]; /* The PPP interface control blocks. */
+
+/*
+ * PPP Data Link Layer "protocol" table.
+ * One entry per supported protocol.
+ * The last entry must be NULL.
+ */
+struct protent *ppp_protocols[] = {
+    &lcp_protent,
+#if PAP_SUPPORT > 0
+    &pap_protent,
+#endif
+#if CHAP_SUPPORT > 0
+    &chap_protent,
+#endif
+#if CBCP_SUPPORT > 0
+    &cbcp_protent,
+#endif
+    &ipcp_protent,
+#if CCP_SUPPORT > 0
+    &ccp_protent,
+#endif
+    NULL
+};
+
+
+/*
+ * Buffers for outgoing packets.  This must be accessed only from the appropriate
+ * PPP task so that it doesn't need to be protected to avoid collisions.
+ */
+u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN];  
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+
+/*
+ * FCS lookup table as calculated by genfcstab.
+ */
+static const u_short fcstab[256] = {
+    0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
+    0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
+    0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
+    0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
+    0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
+    0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
+    0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
+    0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
+    0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
+    0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
+    0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
+    0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
+    0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
+    0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
+    0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
+    0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
+    0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
+    0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
+    0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
+    0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
+    0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
+    0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
+    0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
+    0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
+    0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
+    0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
+    0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
+    0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
+    0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
+    0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
+    0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
+    0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
+};
+
+/* PPP's Asynchronous-Control-Character-Map.  The mask array is used
+ * to select the specific bit for a character. */
+static u_char pppACCMMask[] = {
+    0x01,
+    0x02,
+    0x04,
+    0x08,
+    0x10,
+    0x20,
+    0x40,
+    0x80
+};
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/* Initialize the PPP subsystem. */
+
+struct ppp_settings ppp_settings;
+
+void pppInit(void)
+{
+    struct protent *protp;
+    int i, j;
+    
+	memset(&ppp_settings, 0, sizeof(ppp_settings));
+	ppp_settings.usepeerdns = 1;
+	pppSetAuth(PPPAUTHTYPE_NONE, NULL, NULL);
+
+	magicInit();
+
+    for (i = 0; i < NUM_PPP; i++) {
+        pppControl[i].openFlag = 0;
+
+		subnetMask = htonl(0xffffff00);
+    
+        /*
+         * Initialize to the standard option set.
+         */
+        for (j = 0; (protp = ppp_protocols[j]) != NULL; ++j)
+            (*protp->init)(i);
+    }
+
+#if LINK_STATS
+    /* Clear the statistics. */
+    memset(&lwip_stats.link, 0, sizeof(lwip_stats.link));
+#endif
+}
+
+void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd)
+{
+    switch(authType) {
+	case PPPAUTHTYPE_NONE:
+	default:
+#ifdef LWIP_PPP_STRICT_PAP_REJECT
+	    ppp_settings.refuse_pap = 1;
+#else
+	    /* some providers request pap and accept an empty login/pw */
+	    ppp_settings.refuse_pap = 0;
+#endif
+	    ppp_settings.refuse_chap = 1;
+	    break;
+	case PPPAUTHTYPE_ANY:
+/* Warning: Using PPPAUTHTYPE_ANY might have security consequences.
+ * RFC 1994 says:
+ *
+ * In practice, within or associated with each PPP server, there is a
+ * database which associates "user" names with authentication
+ * information ("secrets").  It is not anticipated that a particular
+ * named user would be authenticated by multiple methods.  This would
+ * make the user vulnerable to attacks which negotiate the least secure
+ * method from among a set (such as PAP rather than CHAP).  If the same
+ * secret was used, PAP would reveal the secret to be used later with
+ * CHAP.
+ *
+ * Instead, for each user name there should be an indication of exactly
+ * one method used to authenticate that user name.  If a user needs to
+ * make use of different authentication methods under different
+ * circumstances, then distinct user names SHOULD be employed, each of
+ * which identifies exactly one authentication method.
+ *
+ */
+	    ppp_settings.refuse_pap = 0;
+	    ppp_settings.refuse_chap = 0;
+	    break;
+	case PPPAUTHTYPE_PAP:
+	    ppp_settings.refuse_pap = 0;
+	    ppp_settings.refuse_chap = 1;
+	    break;
+	case PPPAUTHTYPE_CHAP:
+	    ppp_settings.refuse_pap = 1;
+	    ppp_settings.refuse_chap = 0;
+	    break;
+    }
+
+    if(user) {
+	strncpy(ppp_settings.user, user, sizeof(ppp_settings.user)-1);
+	ppp_settings.user[sizeof(ppp_settings.user)-1] = '\0';
+    } else
+	ppp_settings.user[0] = '\0';
+
+    if(passwd) {
+	strncpy(ppp_settings.passwd, passwd, sizeof(ppp_settings.passwd)-1);
+	ppp_settings.passwd[sizeof(ppp_settings.passwd)-1] = '\0';
+    } else
+	ppp_settings.passwd[0] = '\0';
+}
+
+/* Open a new PPP connection using the given I/O device.
+ * This initializes the PPP control block but does not
+ * attempt to negotiate the LCP session.  If this port
+ * connects to a modem, the modem connection must be
+ * established before calling this.
+ * Return a new PPP connection descriptor on success or
+ * an error code (negative) on failure. */
+int pppOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx)
+{
+    PPPControl *pc;
+    int pd;
+
+    /* Find a free PPP session descriptor. Critical region? */
+    for (pd = 0; pd < NUM_PPP && pppControl[pd].openFlag != 0; pd++);
+    if (pd >= NUM_PPP)
+        pd = PPPERR_OPEN;
+    else
+        pppControl[pd].openFlag = !0;
+
+    /* Launch a deamon thread. */
+    if (pd >= 0) {
+
+        pppControl[pd].openFlag = 1;
+
+        lcp_init(pd);
+        pc = &pppControl[pd];
+        pc->fd = fd;
+        pc->kill_link = 0;
+        pc->sig_hup = 0;
+        pc->if_up = 0;
+        pc->errCode = 0;
+        pc->inState = PDIDLE;
+        pc->inHead = NULL;
+        pc->inTail = NULL;
+        pc->inEscaped = 0;
+        pc->lastXMit = 0;
+
+#if VJ_SUPPORT > 0
+        pc->vjEnabled = 0;
+        vj_compress_init(&pc->vjComp);
+#endif
+
+        /* 
+         * Default the in and out accm so that escape and flag characters
+         * are always escaped. 
+         */
+        memset(pc->inACCM, 0, sizeof(ext_accm));
+        pc->inACCM[15] = 0x60;
+        memset(pc->outACCM, 0, sizeof(ext_accm));
+        pc->outACCM[15] = 0x60;
+
+	pc->linkStatusCB = linkStatusCB;
+	pc->linkStatusCtx = linkStatusCtx;
+
+	sys_thread_new(pppMain, (void*)pd, PPP_THREAD_PRIO);
+	if(!linkStatusCB) {
+		while(pd >= 0 && !pc->if_up) {
+			sys_msleep(500);
+			if (lcp_phase[pd] == PHASE_DEAD) {
+				pppClose(pd);
+				if (pc->errCode)
+					pd = pc->errCode;
+				else
+					pd = PPPERR_CONNECT;
+			}
+		}
+	}
+    }
+    return pd;
+}
+
+/* Close a PPP connection and release the descriptor. 
+ * Any outstanding packets in the queues are dropped.
+ * Return 0 on success, an error code on failure. */
+int pppClose(int pd)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 0;
+
+    /* Disconnect */
+    pc->kill_link = !0;
+    pppMainWakeup(pd);
+    
+    if(!pc->linkStatusCB) {
+	    while(st >= 0 && lcp_phase[pd] != PHASE_DEAD) {
+		    sys_msleep(500);
+		    break;
+	    }
+    }
+    return st;
+}
+
+/* This function is called when carrier is lost on the PPP channel. */
+void pppSigHUP(int pd)
+{
+    PPPControl *pc = &pppControl[pd];
+
+    pc->sig_hup = 1;
+    pppMainWakeup(pd);
+}
+
+static void nPut(PPPControl *pc, struct pbuf *nb)
+{
+	struct pbuf *b;
+	int c;
+
+	for(b = nb; b != NULL; b = b->next) {
+	    if((c = sio_write(pc->fd, b->payload, b->len)) != b->len) {
+		PPPDEBUG((LOG_WARNING,
+			    "PPP nPut: incomplete sio_write(%d,, %u) = %d\n", pc->fd, b->len, c));
+#if LINK_STATS
+		lwip_stats.link.err++;
+#endif /* LINK_STATS */
+		pc->lastXMit = 0; /* prepend PPP_FLAG to next packet */
+		break;
+	    }
+	}
+	pbuf_free(nb);
+
+#if LINK_STATS
+	lwip_stats.link.xmit++;
+#endif /* LINK_STATS */
+}
+
+/* 
+ * pppAppend - append given character to end of given pbuf.  If outACCM
+ * is not NULL and the character needs to be escaped, do so.
+ * If pbuf is full, append another.
+ * Return the current pbuf.
+ */
+static struct pbuf *pppAppend(u_char c, struct pbuf *nb, ext_accm *outACCM)
+{
+    struct pbuf *tb = nb;
+    
+    /* Make sure there is room for the character and an escape code.
+     * Sure we don't quite fill the buffer if the character doesn't
+     * get escaped but is one character worth complicating this? */
+    /* Note: We assume no packet header. */
+    if (nb && (PBUF_POOL_BUFSIZE - nb->len) < 2) {
+	tb = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+	if (tb) {
+	    nb->next = tb;
+        }
+#if LINK_STATS
+	else {
+	    lwip_stats.link.memerr++;
+	}
+#endif /* LINK_STATS */
+	nb = tb;
+    }
+    if (nb) {
+	if (outACCM && ESCAPE_P(*outACCM, c)) {
+            *((u_char*)nb->payload + nb->len++) = PPP_ESCAPE;
+            *((u_char*)nb->payload + nb->len++) = c ^ PPP_TRANS;
+        }
+        else
+            *((u_char*)nb->payload + nb->len++) = c;
+    }
+        
+    return tb;
+}
+
+/* Send a packet on the given connection. */
+static err_t pppifOutput(struct netif *netif, struct pbuf *pb, struct ip_addr *ipaddr)
+{
+    int pd = (int)netif->state;
+    u_short protocol = PPP_IP;
+    PPPControl *pc = &pppControl[pd];
+    u_int fcsOut = PPP_INITFCS;
+    struct pbuf *headMB = NULL, *tailMB = NULL, *p;
+    u_char c;
+
+    (void)ipaddr;
+
+    /* Validate parameters. */
+    /* We let any protocol value go through - it can't hurt us
+     * and the peer will just drop it if it's not accepting it. */
+	if (pd < 0 || pd >= NUM_PPP || !pc->openFlag || !pb) {
+        PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad parms prot=%d pb=%p\n",
+                    pd, protocol, pb));
+#if LINK_STATS
+		lwip_stats.link.opterr++;
+		lwip_stats.link.drop++;
+#endif
+		return ERR_ARG;
+	}
+
+    /* Check that the link is up. */
+	if (lcp_phase[pd] == PHASE_DEAD) {
+        PPPDEBUG((LOG_ERR, "pppifOutput[%d]: link not up\n", pd));
+#if LINK_STATS
+		lwip_stats.link.rterr++;
+		lwip_stats.link.drop++;
+#endif
+		return ERR_RTE;
+	}
+
+    /* Grab an output buffer. */
+	headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+    if (headMB == NULL) {
+        PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: first alloc fail\n", pd));
+#if LINK_STATS
+		lwip_stats.link.memerr++;
+		lwip_stats.link.drop++;
+#endif /* LINK_STATS */
+        return ERR_MEM;
+    }
+        
+#if VJ_SUPPORT > 0
+    /* 
+     * Attempt Van Jacobson header compression if VJ is configured and
+     * this is an IP packet. 
+     */
+    if (protocol == PPP_IP && pc->vjEnabled) {
+        switch (vj_compress_tcp(&pc->vjComp, pb)) {
+        case TYPE_IP:
+            /* No change...
+            protocol = PPP_IP_PROTOCOL;
+             */
+            break;
+        case TYPE_COMPRESSED_TCP:
+            protocol = PPP_VJC_COMP;
+            break;
+        case TYPE_UNCOMPRESSED_TCP:
+            protocol = PPP_VJC_UNCOMP;
+            break;
+        default:
+            PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad IP packet\n", pd));
+#if LINK_STATS
+			lwip_stats.link.proterr++;
+			lwip_stats.link.drop++;
+#endif
+        	pbuf_free(headMB);
+            return ERR_VAL;
+        }
+    }
+#endif
+        
+    tailMB = headMB;
+        
+    /* Build the PPP header. */
+    if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG)
+        tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+    pc->lastXMit = sys_jiffies();
+    if (!pc->accomp) {
+        fcsOut = PPP_FCS(fcsOut, PPP_ALLSTATIONS);
+        tailMB = pppAppend(PPP_ALLSTATIONS, tailMB, &pc->outACCM);
+        fcsOut = PPP_FCS(fcsOut, PPP_UI);
+        tailMB = pppAppend(PPP_UI, tailMB, &pc->outACCM);
+    }
+    if (!pc->pcomp || protocol > 0xFF) {
+        c = (protocol >> 8) & 0xFF;
+        fcsOut = PPP_FCS(fcsOut, c);
+        tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    }
+    c = protocol & 0xFF;
+    fcsOut = PPP_FCS(fcsOut, c);
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    
+    /* Load packet. */
+	for(p = pb; p; p = p->next) {
+    	int n;
+    	u_char *sPtr;
+
+        sPtr = (u_char*)p->payload;
+        n = p->len;
+        while (n-- > 0) {
+            c = *sPtr++;
+            
+            /* Update FCS before checking for special characters. */
+            fcsOut = PPP_FCS(fcsOut, c);
+            
+            /* Copy to output buffer escaping special characters. */
+            tailMB = pppAppend(c, tailMB, &pc->outACCM);
+        }
+    }
+
+    /* Add FCS and trailing flag. */
+    c = ~fcsOut & 0xFF;
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    c = (~fcsOut >> 8) & 0xFF;
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+        
+    /* If we failed to complete the packet, throw it away. */
+    if (!tailMB) {
+        PPPDEBUG((LOG_WARNING,
+                    "pppifOutput[%d]: Alloc err - dropping proto=%d\n", 
+                    pd, protocol));
+        pbuf_free(headMB);
+#if LINK_STATS
+		lwip_stats.link.memerr++;
+		lwip_stats.link.drop++;
+#endif
+        return ERR_MEM;
+    }
+
+	/* Send it. */
+    PPPDEBUG((LOG_INFO, "pppifOutput[%d]: proto=0x%04X\n", pd, protocol));
+
+    nPut(pc, headMB);
+
+    return ERR_OK;
+}
+
+/* Get and set parameters for the given connection.
+ * Return 0 on success, an error code on failure. */
+int  pppIOCtl(int pd, int cmd, void *arg)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 0;
+
+    if (pd < 0 || pd >= NUM_PPP)
+        st = PPPERR_PARAM;
+    else {
+        switch(cmd) {
+        case PPPCTLG_UPSTATUS:      /* Get the PPP up status. */
+            if (arg) 
+                *(int *)arg = (int)(pc->if_up);
+            else
+                st = PPPERR_PARAM;
+            break;
+        case PPPCTLS_ERRCODE:       /* Set the PPP error code. */
+            if (arg) 
+                pc->errCode = *(int *)arg;
+            else
+                st = PPPERR_PARAM;
+            break;
+        case PPPCTLG_ERRCODE:       /* Get the PPP error code. */
+            if (arg) 
+                *(int *)arg = (int)(pc->errCode);
+            else
+                st = PPPERR_PARAM;
+            break;
+        case PPPCTLG_FD:
+            if (arg) 
+                *(sio_fd_t *)arg = pc->fd;
+            else
+                st = PPPERR_PARAM;
+            break;
+        default:
+            st = PPPERR_PARAM;
+            break;
+        }
+    }
+    
+    return st;
+}
+
+/*
+ * Return the Maximum Transmission Unit for the given PPP connection.
+ */
+u_int pppMTU(int pd)
+{
+    PPPControl *pc = &pppControl[pd];
+    u_int st;
+    
+    /* Validate parameters. */
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag)
+        st = 0;
+    else
+        st = pc->mtu;
+        
+    return st;
+}
+
+/*
+ * Write n characters to a ppp link.
+ *  RETURN: >= 0 Number of characters written
+ *           -1 Failed to write to device
+ */
+int pppWrite(int pd, const u_char *s, int n)
+{
+    PPPControl *pc = &pppControl[pd];
+    u_char c;
+    u_int fcsOut = PPP_INITFCS;
+    struct pbuf *headMB = NULL, *tailMB;
+	headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+    if (headMB == NULL) {
+#if LINK_STATS
+		lwip_stats.link.memerr++;
+		lwip_stats.link.proterr++;
+#endif /* LINK_STATS */
+		return PPPERR_ALLOC;
+    }
+
+    tailMB = headMB;
+        
+    /* If the link has been idle, we'll send a fresh flag character to
+     * flush any noise. */
+    if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG)
+        tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+    pc->lastXMit = sys_jiffies();
+     
+    /* Load output buffer. */
+    while (n-- > 0) {
+        c = *s++;
+        
+        /* Update FCS before checking for special characters. */
+        fcsOut = PPP_FCS(fcsOut, c);
+        
+        /* Copy to output buffer escaping special characters. */
+        tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    }
+    
+    /* Add FCS and trailing flag. */
+    c = ~fcsOut & 0xFF;
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    c = (~fcsOut >> 8) & 0xFF;
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+        
+    /* If we failed to complete the packet, throw it away.
+     * Otherwise send it. */
+    if (!tailMB) {
+		PPPDEBUG((LOG_WARNING,
+                "pppWrite[%d]: Alloc err - dropping pbuf len=%d\n", pd, headMB->len));
+/*                "pppWrite[%d]: Alloc err - dropping %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */
+		pbuf_free(headMB);
+#if LINK_STATS
+		lwip_stats.link.memerr++;
+		lwip_stats.link.proterr++;
+#endif /* LINK_STATS */
+		return PPPERR_ALLOC;
+	}
+
+    PPPDEBUG((LOG_INFO, "pppWrite[%d]: len=%d\n", pd, headMB->len));
+/*     "pppWrite[%d]: %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */
+    nPut(pc, headMB);
+
+    return PPPERR_NONE;
+}
+
+/*
+ * ppp_send_config - configure the transmit characteristics of
+ * the ppp interface.
+ */
+void ppp_send_config(
+    int unit, 
+    int mtu,
+    u32_t asyncmap,
+    int pcomp, 
+    int accomp
+)
+{
+    PPPControl *pc = &pppControl[unit];
+    int i;
+    
+    pc->mtu = mtu;
+    pc->pcomp = pcomp;
+    pc->accomp = accomp;
+    
+    /* Load the ACCM bits for the 32 control codes. */
+    for (i = 0; i < 32/8; i++)
+        pc->outACCM[i] = (u_char)((asyncmap >> (8 * i)) & 0xFF);
+    PPPDEBUG((LOG_INFO, "ppp_send_config[%d]: outACCM=%X %X %X %X\n",
+                unit,
+                pc->outACCM[0], pc->outACCM[1], pc->outACCM[2], pc->outACCM[3]));
+}
+
+
+/*
+ * ppp_set_xaccm - set the extended transmit ACCM for the interface.
+ */
+void ppp_set_xaccm(int unit, ext_accm *accm)
+{
+    memcpy(pppControl[unit].outACCM, accm, sizeof(ext_accm));
+    PPPDEBUG((LOG_INFO, "ppp_set_xaccm[%d]: outACCM=%X %X %X %X\n",
+                unit,
+                pppControl[unit].outACCM[0],
+                pppControl[unit].outACCM[1],
+                pppControl[unit].outACCM[2],
+                pppControl[unit].outACCM[3]));
+}
+
+
+/*
+ * ppp_recv_config - configure the receive-side characteristics of
+ * the ppp interface.
+ */
+void ppp_recv_config(
+    int unit, 
+    int mru,
+    u32_t asyncmap,
+    int pcomp, 
+    int accomp
+)
+{
+    PPPControl *pc = &pppControl[unit];
+    int i;
+    
+	(void)accomp;
+	(void)pcomp;
+	(void)mru;
+
+    /* Load the ACCM bits for the 32 control codes. */
+    for (i = 0; i < 32 / 8; i++)
+        pc->inACCM[i] = (u_char)(asyncmap >> (i * 8));
+    PPPDEBUG((LOG_INFO, "ppp_recv_config[%d]: inACCM=%X %X %X %X\n",
+                unit,
+                pc->inACCM[0], pc->inACCM[1], pc->inACCM[2], pc->inACCM[3]));
+}
+
+#if 0
+/*
+ * ccp_test - ask kernel whether a given compression method
+ * is acceptable for use.  Returns 1 if the method and parameters
+ * are OK, 0 if the method is known but the parameters are not OK
+ * (e.g. code size should be reduced), or -1 if the method is unknown.
+ */
+int ccp_test(
+    int unit, 
+    int opt_len, 
+    int for_transmit,
+    u_char *opt_ptr
+)
+{
+    return 0;   /* XXX Currently no compression. */
+}
+
+/*
+ * ccp_flags_set - inform kernel about the current state of CCP.
+ */
+void ccp_flags_set(int unit, int isopen, int isup)
+{
+    /* XXX */
+}
+
+/*
+ * ccp_fatal_error - returns 1 if decompression was disabled as a
+ * result of an error detected after decompression of a packet,
+ * 0 otherwise.  This is necessary because of patent nonsense.
+ */
+int ccp_fatal_error(int unit)
+{
+    /* XXX */
+    return 0;
+}
+#endif
+
+/*
+ * get_idle_time - return how long the link has been idle.
+ */
+int get_idle_time(int u, struct ppp_idle *ip)
+{   
+    /* XXX */
+	(void)u;
+	(void)ip;
+
+    return 0;
+}
+
+
+/*
+ * Return user specified netmask, modified by any mask we might determine
+ * for address `addr' (in network byte order).
+ * Here we scan through the system's list of interfaces, looking for
+ * any non-point-to-point interfaces which might appear to be on the same
+ * network as `addr'.  If we find any, we OR in their netmask to the
+ * user-specified netmask.
+ */
+u32_t GetMask(u32_t addr)
+{
+    u32_t mask, nmask;
+    
+    htonl(addr);
+    if (IN_CLASSA(addr))    /* determine network mask for address class */
+        nmask = IN_CLASSA_NET;
+    else if (IN_CLASSB(addr))
+        nmask = IN_CLASSB_NET;
+    else
+        nmask = IN_CLASSC_NET;
+    /* class D nets are disallowed by bad_ip_adrs */
+    mask = subnetMask | htonl(nmask);
+    
+    /* XXX
+     * Scan through the system's network interfaces.
+     * Get each netmask and OR them into our mask.
+     */
+    
+    return mask;
+}
+
+/*
+ * sifvjcomp - config tcp header compression
+ */
+int sifvjcomp(
+    int pd, 
+    int vjcomp, 
+    int cidcomp, 
+    int maxcid
+)
+{
+#if VJ_SUPPORT > 0
+    PPPControl *pc = &pppControl[pd];
+    
+    pc->vjEnabled = vjcomp;
+    pc->vjComp.compressSlot = cidcomp;
+    pc->vjComp.maxSlotIndex = maxcid;
+    PPPDEBUG((LOG_INFO, "sifvjcomp: VJ compress enable=%d slot=%d max slot=%d\n",
+                vjcomp, cidcomp, maxcid));
+#endif
+
+    return 0;
+}
+
+/*
+ * pppifNetifInit - netif init callback
+ */
+static err_t pppifNetifInit(struct netif *netif)
+{
+	netif->name[0] = 'p';
+	netif->name[1] = 'p';
+	netif->output = pppifOutput;
+	netif->mtu = pppMTU((int)netif->state);
+	return ERR_OK;
+}
+
+
+/*
+ * sifup - Config the interface up and enable IP packets to pass.
+ */
+int sifup(int pd)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+    } else {
+		netif_remove(&pc->netif);
+		if (netif_add(&pc->netif, &pc->addrs.our_ipaddr, &pc->addrs.netmask, &pc->addrs.his_ipaddr, (void *)pd, pppifNetifInit, ip_input)) {
+        	
+        	netif_set_up(&pc->netif);
+        	pc->if_up = 1;
+        	pc->errCode = PPPERR_NONE;
+
+			PPPDEBUG((LOG_DEBUG, "sifup: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+			if(pc->linkStatusCB)
+				pc->linkStatusCB(pc->linkStatusCtx, pc->errCode, &pc->addrs);
+		} else {
+        	st = 0;
+        	PPPDEBUG((LOG_ERR, "sifup[%d]: netif_add failed\n", pd));
+		}
+    }
+
+    return st;
+}
+
+/*
+ * sifnpmode - Set the mode for handling packets for a given NP.
+ */
+int sifnpmode(int u, int proto, enum NPmode mode)
+{
+	(void)u;
+	(void)proto;
+	(void)mode;
+    return 0;
+}
+
+/*
+ * sifdown - Config the interface down and disable IP.
+ */
+int sifdown(int pd)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifdown[%d]: bad parms\n", pd));
+    } else {
+        pc->if_up = 0;
+	netif_remove(&pc->netif);
+	PPPDEBUG((LOG_DEBUG, "sifdown: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+	if(pc->linkStatusCB)
+		pc->linkStatusCB(pc->linkStatusCtx, PPPERR_CONNECT, NULL);
+	}
+    return st;
+}
+
+/*
+ * sifaddr - Config the interface IP addresses and netmask.
+ */
+int sifaddr(
+    int pd,             /* Interface unit ??? */
+    u32_t o,        /* Our IP address ??? */
+    u32_t h,        /* His IP address ??? */
+    u32_t m,        /* IP subnet mask ??? */
+    u32_t ns1,      /* Primary DNS */
+    u32_t ns2       /* Secondary DNS */
+)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+    } else {
+		memcpy(&pc->addrs.our_ipaddr, &o, sizeof(o));
+		memcpy(&pc->addrs.his_ipaddr, &h, sizeof(h));
+		memcpy(&pc->addrs.netmask, &m, sizeof(m));
+		memcpy(&pc->addrs.dns1, &ns1, sizeof(ns1));
+		memcpy(&pc->addrs.dns2, &ns2, sizeof(ns2));
+    }
+    return st;
+}
+
+/*
+ * cifaddr - Clear the interface IP addresses, and delete routes
+ * through the interface if possible.
+ */
+int cifaddr(
+    int pd,         /* Interface unit ??? */
+    u32_t o,    /* Our IP address ??? */
+    u32_t h     /* IP broadcast address ??? */
+)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+	(void)o;
+	(void)h;
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+    } else {
+		IP4_ADDR(&pc->addrs.our_ipaddr, 0,0,0,0);
+		IP4_ADDR(&pc->addrs.his_ipaddr, 0,0,0,0);
+		IP4_ADDR(&pc->addrs.netmask, 255,255,255,0);
+		IP4_ADDR(&pc->addrs.dns1, 0,0,0,0);
+		IP4_ADDR(&pc->addrs.dns2, 0,0,0,0);
+    }
+    return st;
+}
+
+/*
+ * sifdefaultroute - assign a default route through the address given.
+ */
+int sifdefaultroute(int pd, u32_t l, u32_t g)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+	(void)l;
+	(void)g;
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+    } else {
+		netif_set_default(&pc->netif);
+    }
+
+    /* TODO: check how PPP handled the netMask, previously not set by ipSetDefault */
+
+    return st;
+}
+
+/*
+ * cifdefaultroute - delete a default route through the address given.
+ */
+int cifdefaultroute(int pd, u32_t l, u32_t g)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+	(void)l;
+	(void)g;
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+    } else {
+		netif_set_default(NULL);
+    }
+
+    return st;
+}
+
+void
+pppMainWakeup(int pd)
+{
+	PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d\n", pd));
+	sio_read_abort(pppControl[pd].fd);
+}
+
+/* these callbacks are necessary because lcp_* functions
+   must be called in the same context as pppInput(),
+   namely the tcpip_thread(), essentially because
+   they manipulate timeouts which are thread-private
+*/
+
+static void
+pppStartCB(void *arg)
+{
+    int pd = (int)arg;
+
+	PPPDEBUG((LOG_DEBUG, "pppStartCB: unit %d\n", pd));
+    lcp_lowerup(pd);
+    lcp_open(pd);      /* Start protocol */
+}
+
+static void
+pppStopCB(void *arg)
+{
+    int pd = (int)arg;
+
+	PPPDEBUG((LOG_DEBUG, "pppStopCB: unit %d\n", pd));
+    lcp_close(pd, "User request");
+}
+
+static void
+pppHupCB(void *arg)
+{
+    int pd = (int)arg;
+
+	PPPDEBUG((LOG_DEBUG, "pppHupCB: unit %d\n", pd));
+    lcp_lowerdown(pd);
+    link_terminated(pd);
+}
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/* The main PPP process function.  This implements the state machine according
+ * to section 4 of RFC 1661: The Point-To-Point Protocol. */
+static void pppMain(void *arg)
+{
+    int pd = (int)arg;
+    struct pbuf *p;
+    PPPControl* pc;
+
+    pc = &pppControl[pd];
+
+    p = pbuf_alloc(PBUF_RAW, PPP_MRU+PPP_HDRLEN, PBUF_RAM);
+    if(!p) {
+		LWIP_ASSERT("p != NULL", p);
+		pc->errCode = PPPERR_ALLOC;
+		goto out;
+    }
+
+    /*
+     * Start the connection and handle incoming events (packet or timeout).
+     */
+	PPPDEBUG((LOG_INFO, "pppMain: unit %d: Connecting\n", pd));
+    tcpip_callback(pppStartCB, arg);
+    while (lcp_phase[pd] != PHASE_DEAD) {
+        if (pc->kill_link) {
+	    	PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d kill_link -> pppStopCB\n", pd));
+		pc->errCode = PPPERR_USER;
+		/* This will leave us at PHASE_DEAD. */
+    		tcpip_callback(pppStopCB, arg);
+		pc->kill_link = 0;
+        }
+        else if (pc->sig_hup) {
+	    	PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d sig_hup -> pppHupCB\n", pd));
+		pc->sig_hup = 0;
+    		tcpip_callback(pppHupCB, arg);
+        } else {
+		int c = sio_read(pc->fd, p->payload, p->len);
+		if(c > 0) {
+			pppInProc(pd, p->payload, c);
+		} else {
+		    PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d sio_read len=%d returned %d\n", pd, p->len, c));
+		    sys_msleep(1); /* give other tasks a chance to run */
+		}
+        }
+    }
+	PPPDEBUG((LOG_INFO, "pppMain: unit %d: PHASE_DEAD\n", pd));
+    pbuf_free(p);
+
+out:
+	PPPDEBUG((LOG_DEBUG, "pppMain: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+    if(pc->linkStatusCB)
+	    pc->linkStatusCB(pc->linkStatusCtx, pc->errCode ? pc->errCode : PPPERR_PROTOCOL, NULL);
+
+    pc->openFlag = 0;
+}
+
+static struct pbuf *pppSingleBuf(struct pbuf *p)
+{
+	struct pbuf *q, *b;
+	u_char *pl;
+
+	if(p->tot_len == p->len)
+		return p;
+
+	q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
+	if(!q) {
+		PPPDEBUG((LOG_ERR,
+                        "pppSingleBuf: unable to alloc new buf (%d)\n", p->tot_len));
+		return p; /* live dangerously */
+	}
+
+	for(b = p, pl = q->payload; b != NULL; b = b->next) {
+		memcpy(pl, b->payload, b->len);
+		pl += b->len;
+	}
+
+	pbuf_free(p);
+
+	return q;
+}
+
+struct pppInputHeader {
+	int unit;
+	u16_t proto;
+};
+
+/*
+ * Pass the processed input packet to the appropriate handler.
+ * This function and all handlers run in the context of the tcpip_thread
+ */
+static void pppInput(void *arg)
+{
+	struct pbuf *nb = (struct pbuf *)arg;
+    u16_t protocol;
+    int pd;
+
+	pd = ((struct pppInputHeader *)nb->payload)->unit;
+	protocol = ((struct pppInputHeader *)nb->payload)->proto;
+
+    pbuf_header(nb, -(int)sizeof(struct pppInputHeader));
+
+#if LINK_STATS
+    lwip_stats.link.recv++;
+#endif /* LINK_STATS */
+
+    /*
+     * Toss all non-LCP packets unless LCP is OPEN.
+     * Until we get past the authentication phase, toss all packets
+     * except LCP, LQR and authentication packets.
+     */
+    if((lcp_phase[pd] <= PHASE_AUTHENTICATE) && (protocol != PPP_LCP)) {
+	    if(!((protocol == PPP_LQR) || (protocol == PPP_PAP) || (protocol == PPP_CHAP)) ||
+			(lcp_phase[pd] != PHASE_AUTHENTICATE)) {
+		PPPDEBUG((LOG_INFO, "pppInput: discarding proto 0x%04X in phase %d\n", protocol, lcp_phase[pd]));
+		goto drop;
+	    }
+    }
+
+    switch(protocol) {
+    case PPP_VJC_COMP:      /* VJ compressed TCP */
+#if VJ_SUPPORT > 0
+        PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_comp in pbuf len=%d\n", pd, nb->len));
+        /*
+         * Clip off the VJ header and prepend the rebuilt TCP/IP header and
+         * pass the result to IP.
+         */
+        if (vj_uncompress_tcp(&nb, &pppControl[pd].vjComp) >= 0) {
+            if (pppControl[pd].netif.input != NULL) {
+              pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+            }
+			return;
+        }
+	/* Something's wrong so drop it. */
+	PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ compressed\n", pd));
+#else
+        /* No handler for this protocol so drop the packet. */
+        PPPDEBUG((LOG_INFO, "pppInput[%d]: drop VJ Comp in %d:%s\n", pd, nb->len, nb->payload));
+#endif /* VJ_SUPPORT > 0 */
+	break;
+    case PPP_VJC_UNCOMP:    /* VJ uncompressed TCP */
+#if VJ_SUPPORT > 0
+        PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_un in pbuf len=%d\n", pd, nb->len));
+        /*
+         * Process the TCP/IP header for VJ header compression and then pass
+         * the packet to IP.
+         */
+        if (vj_uncompress_uncomp(nb, &pppControl[pd].vjComp) >= 0) {
+            if (pppControl[pd].netif.input != NULL) {
+              pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+            }
+			return;
+        }
+	/* Something's wrong so drop it. */
+	PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ uncompressed\n", pd));
+#else
+        /* No handler for this protocol so drop the packet. */
+        PPPDEBUG((LOG_INFO,
+                    "pppInput[%d]: drop VJ UnComp in %d:.*H\n", 
+                    pd, nb->len, LWIP_MIN(nb->len * 2, 40), nb->payload));
+#endif /* VJ_SUPPORT > 0 */
+	break;
+    case PPP_IP:            /* Internet Protocol */
+        PPPDEBUG((LOG_INFO, "pppInput[%d]: ip in pbuf len=%d\n", pd, nb->len));
+        if (pppControl[pd].netif.input != NULL) {
+          pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+        }
+		return;
+    default:
+	{
+		struct protent *protp;
+		int i;
+
+		/*
+		 * Upcall the proper protocol input routine.
+		 */
+		for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+			if (protp->protocol == protocol && protp->enabled_flag) {
+				PPPDEBUG((LOG_INFO, "pppInput[%d]: %s len=%d\n", pd, protp->name, nb->len));
+				nb = pppSingleBuf(nb);
+				(*protp->input)(pd, nb->payload, nb->len);
+				goto out;
+			}
+		}
+
+		/* No handler for this protocol so reject the packet. */
+		PPPDEBUG((LOG_INFO, "pppInput[%d]: rejecting unsupported proto 0x%04X len=%d\n", pd, protocol, nb->len));
+		pbuf_header(nb, sizeof(protocol));
+#if BYTE_ORDER == LITTLE_ENDIAN
+		protocol = htons(protocol);
+		memcpy(nb->payload, &protocol, sizeof(protocol));
+#endif
+		lcp_sprotrej(pd, nb->payload, nb->len);
+	}
+	break;
+    }
+
+drop:
+#if LINK_STATS
+    lwip_stats.link.drop++;
+#endif
+
+out:
+    pbuf_free(nb);
+    return;
+}
+
+
+/*
+ * Drop the input packet.
+ */
+static void pppDrop(PPPControl *pc)
+{
+    if (pc->inHead != NULL) {
+#if 0	    
+        PPPDEBUG((LOG_INFO, "pppDrop: %d:%.*H\n", pc->inHead->len, min(60, pc->inHead->len * 2), pc->inHead->payload));
+#endif	
+        PPPDEBUG((LOG_INFO, "pppDrop: pbuf len=%d\n", pc->inHead->len));
+	if (pc->inTail && (pc->inTail != pc->inHead))
+	    pbuf_free(pc->inTail);
+        pbuf_free(pc->inHead);
+        pc->inHead = NULL;
+        pc->inTail = NULL;
+    }
+#if VJ_SUPPORT > 0
+    vj_uncompress_err(&pc->vjComp);
+#endif
+
+#if LINK_STATS
+    lwip_stats.link.drop++;
+#endif /* LINK_STATS */
+}
+
+
+/*
+ * Process a received octet string.
+ */
+static void pppInProc(int pd, u_char *s, int l)
+{
+    PPPControl *pc = &pppControl[pd];
+    struct pbuf *nextNBuf;
+    u_char curChar;
+
+    PPPDEBUG((LOG_DEBUG, "pppInProc[%d]: got %d bytes\n", pd, l));
+    while (l-- > 0) {
+        curChar = *s++;
+        
+        /* Handle special characters. */
+        if (ESCAPE_P(pc->inACCM, curChar)) {
+            /* Check for escape sequences. */
+            /* XXX Note that this does not handle an escaped 0x5d character which
+             * would appear as an escape character.  Since this is an ASCII ']'
+             * and there is no reason that I know of to escape it, I won't complicate
+             * the code to handle this case. GLL */
+            if (curChar == PPP_ESCAPE)
+                pc->inEscaped = 1;
+            /* Check for the flag character. */
+            else if (curChar == PPP_FLAG) {
+                /* If this is just an extra flag character, ignore it. */
+                if (pc->inState <= PDADDRESS)
+                    ;
+                /* If we haven't received the packet header, drop what has come in. */
+                else if (pc->inState < PDDATA) {
+                    PPPDEBUG((LOG_WARNING,
+                                "pppInProc[%d]: Dropping incomplete packet %d\n", 
+                                pd, pc->inState));
+#if LINK_STATS
+					lwip_stats.link.lenerr++;
+#endif
+                    pppDrop(pc);
+                }
+                /* If the fcs is invalid, drop the packet. */
+                else if (pc->inFCS != PPP_GOODFCS) {
+                    PPPDEBUG((LOG_INFO,
+                                "pppInProc[%d]: Dropping bad fcs 0x%04X proto=0x%04X\n", 
+                                pd, pc->inFCS, pc->inProtocol));
+#if LINK_STATS
+					lwip_stats.link.chkerr++;
+#endif
+                    pppDrop(pc);
+                }
+                /* Otherwise it's a good packet so pass it on. */
+                else {
+                    
+                    /* Trim off the checksum. */
+		    if(pc->inTail->len >= 2) {
+			pc->inTail->len -= 2;
+
+			pc->inTail->tot_len = pc->inTail->len;
+			if (pc->inTail != pc->inHead) {
+			    pbuf_cat(pc->inHead, pc->inTail);
+			}
+		    } else {
+			pc->inTail->tot_len = pc->inTail->len;
+			if (pc->inTail != pc->inHead) {
+			    pbuf_cat(pc->inHead, pc->inTail);
+			}
+
+			pbuf_realloc(pc->inHead, pc->inHead->tot_len - 2);
+		    }
+
+                    /* Dispatch the packet thereby consuming it. */
+		    if(tcpip_callback(pppInput, pc->inHead) != ERR_OK) {
+                    	PPPDEBUG((LOG_ERR,
+				    "pppInProc[%d]: tcpip_callback() failed, dropping packet\n", pd));
+			pbuf_free(pc->inHead);
+#if LINK_STATS
+			lwip_stats.link.drop++;
+#endif
+		    }
+                    pc->inHead = NULL;
+                    pc->inTail = NULL;
+                }
+                    
+                /* Prepare for a new packet. */
+                pc->inFCS = PPP_INITFCS;
+                pc->inState = PDADDRESS;
+                pc->inEscaped = 0;
+            }
+            /* Other characters are usually control characters that may have
+             * been inserted by the physical layer so here we just drop them. */
+            else {
+                PPPDEBUG((LOG_WARNING,
+                            "pppInProc[%d]: Dropping ACCM char <%d>\n", pd, curChar));
+            }
+        }
+        /* Process other characters. */
+        else {
+            /* Unencode escaped characters. */
+            if (pc->inEscaped) {
+                pc->inEscaped = 0;
+                curChar ^= PPP_TRANS;
+            }
+            
+            /* Process character relative to current state. */
+            switch(pc->inState) {
+            case PDIDLE:                    /* Idle state - waiting. */
+                /* Drop the character if it's not 0xff
+                 * we would have processed a flag character above. */
+                if (curChar != PPP_ALLSTATIONS) {
+                	break;
+				}
+
+				/* Fall through */
+            case PDSTART:                   /* Process start flag. */
+                /* Prepare for a new packet. */
+                pc->inFCS = PPP_INITFCS;
+
+				/* Fall through */
+            case PDADDRESS:                 /* Process address field. */
+                if (curChar == PPP_ALLSTATIONS) {
+                    pc->inState = PDCONTROL;
+                    break;
+                }
+                /* Else assume compressed address and control fields so
+                 * fall through to get the protocol... */
+            case PDCONTROL:                 /* Process control field. */
+                /* If we don't get a valid control code, restart. */
+                if (curChar == PPP_UI) {
+                    pc->inState = PDPROTOCOL1;
+                	break;
+                }
+#if 0
+                else {
+                    PPPDEBUG((LOG_WARNING,
+                                "pppInProc[%d]: Invalid control <%d>\n", pd, curChar));
+                    pc->inState = PDSTART;
+                }
+#endif
+            case PDPROTOCOL1:               /* Process protocol field 1. */
+                /* If the lower bit is set, this is the end of the protocol
+                 * field. */
+                if (curChar & 1) {
+                    pc->inProtocol = curChar;
+                    pc->inState = PDDATA;
+                }
+                else {
+                    pc->inProtocol = (u_int)curChar << 8;
+                    pc->inState = PDPROTOCOL2;
+                }
+                break;
+            case PDPROTOCOL2:               /* Process protocol field 2. */
+                pc->inProtocol |= curChar;
+                pc->inState = PDDATA;
+                break;
+            case PDDATA:                    /* Process data byte. */
+                /* Make space to receive processed data. */
+                if (pc->inTail == NULL || pc->inTail->len == PBUF_POOL_BUFSIZE) {
+		    if(pc->inTail) {
+			pc->inTail->tot_len = pc->inTail->len;
+			if (pc->inTail != pc->inHead) {
+			    pbuf_cat(pc->inHead, pc->inTail);
+			}
+		    }
+                    /* If we haven't started a packet, we need a packet header. */
+                    nextNBuf = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+                    if (nextNBuf == NULL) {
+                        /* No free buffers.  Drop the input packet and let the
+                         * higher layers deal with it.  Continue processing
+                         * the received pbuf chain in case a new packet starts. */
+                        PPPDEBUG((LOG_ERR, "pppInProc[%d]: NO FREE MBUFS!\n", pd));
+#if LINK_STATS
+						lwip_stats.link.memerr++;
+#endif /* LINK_STATS */
+                        pppDrop(pc);
+                        pc->inState = PDSTART;  /* Wait for flag sequence. */
+			break;
+                    }
+		    if (pc->inHead == NULL) {
+			struct pppInputHeader *pih = nextNBuf->payload;
+
+			pih->unit = pd;
+			pih->proto = pc->inProtocol;
+
+			nextNBuf->len += sizeof(*pih);
+
+			pc->inHead = nextNBuf;
+		    }
+		    pc->inTail = nextNBuf;
+                }
+                /* Load character into buffer. */
+                ((u_char*)pc->inTail->payload)[pc->inTail->len++] = curChar;
+                break;
+            }
+
+            /* update the frame check sequence number. */
+            pc->inFCS = PPP_FCS(pc->inFCS, curChar);
+        }
+    }
+	avRandomize();
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/ppp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/ppp.h
new file mode 100644
index 0000000..0943248
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/ppp.h
@@ -0,0 +1,446 @@
+/*****************************************************************************
+* ppp.h - Network Point to Point Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*	Original derived from BSD codes.
+*****************************************************************************/
+
+#ifndef PPP_H
+#define PPP_H
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT > 0
+#include "lwip/sio.h"
+#include "lwip/api.h"
+#include "lwip/sockets.h"
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+#include "lwip/tcpip.h"
+#include "lwip/netif.h"
+
+/*
+ * pppd.h - PPP daemon global declarations.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ */
+/*
+ * ppp_defs.h - PPP definitions.
+ *
+ * Copyright (c) 1994 The Australian National University.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, provided that the above copyright
+ * notice appears in all copies.  This software is provided without any
+ * warranty, express or implied. The Australian National University
+ * makes no representations about the suitability of this software for
+ * any purpose.
+ *
+ * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY
+ * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
+ * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
+ * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS,
+ * OR MODIFICATIONS.
+ */
+
+#define TIMEOUT(f, a, t)    sys_untimeout((f), (a)), sys_timeout((t)*1000, (f), (a))
+#define UNTIMEOUT(f, a)     sys_untimeout((f), (a))
+
+
+# ifndef __u_char_defined
+
+/* Type definitions for BSD code. */
+typedef unsigned long u_long;
+typedef unsigned int u_int;
+typedef unsigned short u_short;
+typedef unsigned char u_char;
+
+#endif
+
+/*
+ * Constants and structures defined by the internet system,
+ * Per RFC 790, September 1981, and numerous additions.
+ */
+
+/*
+ * The basic PPP frame.
+ */
+#define PPP_HDRLEN  4       /* octets for standard ppp header */
+#define PPP_FCSLEN  2       /* octets for FCS */
+
+
+/*
+ * Significant octet values.
+ */
+#define PPP_ALLSTATIONS 0xff    /* All-Stations broadcast address */
+#define PPP_UI          0x03    /* Unnumbered Information */
+#define PPP_FLAG        0x7e    /* Flag Sequence */
+#define PPP_ESCAPE      0x7d    /* Asynchronous Control Escape */
+#define PPP_TRANS       0x20    /* Asynchronous transparency modifier */
+
+/*
+ * Protocol field values.
+ */
+#define PPP_IP          0x21    /* Internet Protocol */
+#define PPP_AT          0x29    /* AppleTalk Protocol */
+#define PPP_VJC_COMP    0x2d    /* VJ compressed TCP */
+#define PPP_VJC_UNCOMP  0x2f    /* VJ uncompressed TCP */
+#define PPP_COMP        0xfd    /* compressed packet */
+#define PPP_IPCP        0x8021  /* IP Control Protocol */
+#define PPP_ATCP        0x8029  /* AppleTalk Control Protocol */
+#define PPP_CCP         0x80fd  /* Compression Control Protocol */
+#define PPP_LCP         0xc021  /* Link Control Protocol */
+#define PPP_PAP         0xc023  /* Password Authentication Protocol */
+#define PPP_LQR         0xc025  /* Link Quality Report protocol */
+#define PPP_CHAP        0xc223  /* Cryptographic Handshake Auth. Protocol */
+#define PPP_CBCP        0xc029  /* Callback Control Protocol */
+
+/*
+ * Values for FCS calculations.
+ */
+#define PPP_INITFCS 0xffff  /* Initial FCS value */
+#define PPP_GOODFCS 0xf0b8  /* Good final FCS value */
+#define PPP_FCS(fcs, c) (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff])
+
+/*
+ * Extended asyncmap - allows any character to be escaped.
+ */
+typedef u_char  ext_accm[32];
+
+/*
+ * What to do with network protocol (NP) packets.
+ */
+enum NPmode {
+    NPMODE_PASS,        /* pass the packet through */
+    NPMODE_DROP,        /* silently drop the packet */
+    NPMODE_ERROR,       /* return an error */
+    NPMODE_QUEUE        /* save it up for later. */
+};
+
+/*
+ * Inline versions of get/put char/short/long.
+ * Pointer is advanced; we assume that both arguments
+ * are lvalues and will already be in registers.
+ * cp MUST be u_char *.
+ */
+#define GETCHAR(c, cp) { \
+    (c) = *(cp)++; \
+}
+#define PUTCHAR(c, cp) { \
+    *(cp)++ = (u_char) (c); \
+}
+
+
+#define GETSHORT(s, cp) { \
+    (s) = *(cp); (cp)++; (s) << 8; \
+    (s) |= *(cp); (cp)++; \
+}
+#define PUTSHORT(s, cp) { \
+    *(cp)++ = (u_char) ((s) >> 8); \
+    *(cp)++ = (u_char) (s); \
+}
+
+#define GETLONG(l, cp) { \
+    (l) = *(cp); (cp)++; (l) << 8; \
+    (l) |= *(cp); (cp)++; (l) <<= 8; \
+    (l) |= *(cp); (cp)++; (l) <<= 8; \
+    (l) |= *(cp); (cp)++; \
+}
+#define PUTLONG(l, cp) { \
+    *(cp)++ = (u_char) ((l) >> 24); \
+    *(cp)++ = (u_char) ((l) >> 16); \
+    *(cp)++ = (u_char) ((l) >> 8); \
+    *(cp)++ = (u_char) (l); \
+}
+
+
+#define INCPTR(n, cp)   ((cp) += (n))
+#define DECPTR(n, cp)   ((cp) -= (n))
+
+#define BCMP(s0, s1, l)     memcmp((u_char *)(s0), (u_char *)(s1), (l))
+#define BCOPY(s, d, l)      memcpy((d), (s), (l))
+#define BZERO(s, n)         memset(s, 0, n)
+#if PPP_DEBUG
+#define PRINTMSG(m, l)  { m[l] = '\0'; ppp_trace(LOG_INFO, "Remote message: %s\n", m); }
+#else
+#define PRINTMSG(m, l)
+#endif
+
+/*
+ * MAKEHEADER - Add PPP Header fields to a packet.
+ */
+#define MAKEHEADER(p, t) { \
+    PUTCHAR(PPP_ALLSTATIONS, p); \
+    PUTCHAR(PPP_UI, p); \
+    PUTSHORT(t, p); }
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+
+/* Error codes. */
+#define PPPERR_NONE 0				/* No error. */
+#define PPPERR_PARAM -1				/* Invalid parameter. */
+#define PPPERR_OPEN -2				/* Unable to open PPP session. */
+#define PPPERR_DEVICE -3			/* Invalid I/O device for PPP. */
+#define PPPERR_ALLOC -4				/* Unable to allocate resources. */
+#define PPPERR_USER -5				/* User interrupt. */
+#define PPPERR_CONNECT -6			/* Connection lost. */
+#define PPPERR_AUTHFAIL -7			/* Failed authentication challenge. */
+#define PPPERR_PROTOCOL -8			/* Failed to meet protocol. */
+
+/*
+ * PPP IOCTL commands.
+ */
+/*
+ * Get the up status - 0 for down, non-zero for up.  The argument must
+ * point to an int.
+ */
+#define PPPCTLG_UPSTATUS 100	/* Get the up status - 0 down else up */
+#define PPPCTLS_ERRCODE 101		/* Set the error code */
+#define PPPCTLG_ERRCODE 102		/* Get the error code */
+#define	PPPCTLG_FD		103		/* Get the fd associated with the ppp */
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * The following struct gives the addresses of procedures to call
+ * for a particular protocol.
+ */
+struct protent {
+    u_short protocol;       /* PPP protocol number */
+    /* Initialization procedure */
+    void (*init) (int unit);
+    /* Process a received packet */
+    void (*input) (int unit, u_char *pkt, int len);
+    /* Process a received protocol-reject */
+    void (*protrej) (int unit);
+    /* Lower layer has come up */
+    void (*lowerup) (int unit);
+    /* Lower layer has gone down */
+    void (*lowerdown) (int unit);
+    /* Open the protocol */
+    void (*open) (int unit);
+    /* Close the protocol */
+    void (*close) (int unit, char *reason);
+#if 0
+    /* Print a packet in readable form */
+    int  (*printpkt) (u_char *pkt, int len,
+              void (*printer) (void *, char *, ...),
+              void *arg);
+    /* Process a received data packet */
+    void (*datainput) (int unit, u_char *pkt, int len);
+#endif
+    int  enabled_flag;      /* 0 iff protocol is disabled */
+    char *name;         /* Text name of protocol */
+#if 0
+    /* Check requested options, assign defaults */
+    void (*check_options) (u_long);
+    /* Configure interface for demand-dial */
+    int  (*demand_conf) (int unit);
+    /* Say whether to bring up link for this pkt */
+    int  (*active_pkt) (u_char *pkt, int len);
+#endif
+};
+
+/*
+ * The following structure records the time in seconds since
+ * the last NP packet was sent or received.
+ */
+struct ppp_idle {
+    u_short xmit_idle;      /* seconds since last NP packet sent */
+    u_short recv_idle;      /* seconds since last NP packet received */
+};
+
+struct ppp_settings {
+
+	u_int  disable_defaultip : 1;   /* Don't use hostname for default IP addrs */
+	u_int  auth_required : 1;      /* Peer is required to authenticate */
+	u_int  explicit_remote : 1;    /* remote_name specified with remotename opt */
+	u_int  refuse_pap : 1;         /* Don't wanna auth. ourselves with PAP */
+	u_int  refuse_chap : 1;        /* Don't wanna auth. ourselves with CHAP */
+	u_int  usehostname : 1;        /* Use hostname for our_name */
+	u_int  usepeerdns : 1;         /* Ask peer for DNS adds */
+
+	u_short idle_time_limit; /* Shut down link if idle for this long */
+	int  maxconnect;         /* Maximum connect time (seconds) */
+
+	char user[MAXNAMELEN + 1];/* Username for PAP */
+	char passwd[MAXSECRETLEN + 1];           /* Password for PAP, secret for CHAP */
+	char our_name[MAXNAMELEN + 1];         /* Our name for authentication purposes */
+	char remote_name[MAXNAMELEN + 1];      /* Peer's name for authentication */
+};
+
+struct ppp_addrs {
+    struct ip_addr our_ipaddr, his_ipaddr, netmask, dns1, dns2;
+};
+
+/*****************************
+*** PUBLIC DATA STRUCTURES ***
+*****************************/
+/* Buffers for outgoing packets. */
+extern u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN];
+
+extern struct ppp_settings ppp_settings;
+
+extern struct protent *ppp_protocols[];/* Table of pointers to supported protocols */
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+/* Initialize the PPP subsystem. */
+void pppInit(void);
+
+/* Warning: Using PPPAUTHTYPE_ANY might have security consequences.
+ * RFC 1994 says:
+ *
+ * In practice, within or associated with each PPP server, there is a
+ * database which associates "user" names with authentication
+ * information ("secrets").  It is not anticipated that a particular
+ * named user would be authenticated by multiple methods.  This would
+ * make the user vulnerable to attacks which negotiate the least secure
+ * method from among a set (such as PAP rather than CHAP).  If the same
+ * secret was used, PAP would reveal the secret to be used later with
+ * CHAP.
+ *
+ * Instead, for each user name there should be an indication of exactly
+ * one method used to authenticate that user name.  If a user needs to
+ * make use of different authentication methods under different
+ * circumstances, then distinct user names SHOULD be employed, each of
+ * which identifies exactly one authentication method.
+ *
+ */
+enum pppAuthType {
+    PPPAUTHTYPE_NONE,
+    PPPAUTHTYPE_ANY,
+    PPPAUTHTYPE_PAP,
+    PPPAUTHTYPE_CHAP
+};
+
+void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd);
+
+/*
+ * Open a new PPP connection using the given I/O device.
+ * This initializes the PPP control block but does not
+ * attempt to negotiate the LCP session.
+ * Return a new PPP connection descriptor on success or
+ * an error code (negative) on failure. 
+ */
+int pppOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx);
+
+/*
+ * Close a PPP connection and release the descriptor. 
+ * Any outstanding packets in the queues are dropped.
+ * Return 0 on success, an error code on failure. 
+ */
+int pppClose(int pd);
+
+/*
+ * Indicate to the PPP process that the line has disconnected.
+ */
+void pppSigHUP(int pd);
+
+/*
+ * Get and set parameters for the given connection.
+ * Return 0 on success, an error code on failure. 
+ */
+int  pppIOCtl(int pd, int cmd, void *arg);
+
+/*
+ * Return the Maximum Transmission Unit for the given PPP connection.
+ */
+u_int pppMTU(int pd);
+
+/*
+ * Write n characters to a ppp link.
+ *	RETURN: >= 0 Number of characters written
+ *		 	 -1 Failed to write to device
+ */
+int pppWrite(int pd, const u_char *s, int n);
+
+void pppMainWakeup(int pd);
+
+/* Configure i/f transmit parameters */
+void ppp_send_config (int, int, u32_t, int, int);
+/* Set extended transmit ACCM */
+void ppp_set_xaccm (int, ext_accm *);
+/* Configure i/f receive parameters */
+void ppp_recv_config (int, int, u32_t, int, int);
+/* Find out how long link has been idle */
+int  get_idle_time (int, struct ppp_idle *);
+
+/* Configure VJ TCP header compression */
+int  sifvjcomp (int, int, int, int);
+/* Configure i/f down (for IP) */
+int  sifup (int);		
+/* Set mode for handling packets for proto */
+int  sifnpmode (int u, int proto, enum NPmode mode);
+/* Configure i/f down (for IP) */
+int  sifdown (int);	
+/* Configure IP addresses for i/f */
+int  sifaddr (int, u32_t, u32_t, u32_t, u32_t, u32_t);
+/* Reset i/f IP addresses */
+int  cifaddr (int, u32_t, u32_t);
+/* Create default route through i/f */
+int  sifdefaultroute (int, u32_t, u32_t);
+/* Delete default route through i/f */
+int  cifdefaultroute (int, u32_t, u32_t);
+
+/* Get appropriate netmask for address */
+u32_t GetMask (u32_t); 
+
+#endif /* PPP_SUPPORT */
+
+#endif /* PPP_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/pppdebug.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/pppdebug.h
new file mode 100644
index 0000000..e4cf25a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/pppdebug.h
@@ -0,0 +1,89 @@
+/*****************************************************************************
+* pppdebug.h - System debugging utilities.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+* portions Copyright (c) 2001 by Cognizant Pty Ltd.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY (please don't use tabs!)
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-07-29 Guy Lancaster , Global Election Systems Inc.
+*	Original.
+*
+*****************************************************************************
+*/
+#ifndef PPPDEBUG_H
+#define PPPDEBUG_H
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+/* Trace levels. */
+typedef enum {
+	LOG_CRITICAL = 0,
+	LOG_ERR = 1,
+	LOG_NOTICE = 2,
+	LOG_WARNING = 3,
+	LOG_INFO = 5,
+	LOG_DETAIL = 6,
+	LOG_DEBUG = 7
+} LogCodes;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+/*
+ *	ppp_trace - a form of printf to send tracing information to stderr
+ */
+void ppp_trace(int level, const char *format,...);
+
+#if PPP_DEBUG > 0
+
+#define AUTHDEBUG(a) ppp_trace a
+#define IPCPDEBUG(a) ppp_trace a
+#define UPAPDEBUG(a) ppp_trace a
+#define LCPDEBUG(a) ppp_trace a
+#define FSMDEBUG(a) ppp_trace a
+#define CHAPDEBUG(a) ppp_trace a
+#define PPPDEBUG(a) ppp_trace a
+
+#define TRACELCP 1
+
+#else
+
+#define AUTHDEBUG(a)
+#define IPCPDEBUG(a)
+#define UPAPDEBUG(a)
+#define LCPDEBUG(a)
+#define FSMDEBUG(a)
+#define CHAPDEBUG(a)
+
+#define PPPDEBUG(a)
+
+#define TRACELCP 0
+
+#endif
+
+#endif /* PPPDEBUG_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/randm.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/randm.c
new file mode 100644
index 0000000..d4431dd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/randm.c
@@ -0,0 +1,242 @@
+/*****************************************************************************
+* randm.c - Random number generator program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1998 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-06-03 Guy Lancaster , Global Election Systems Inc.
+*   Extracted from avos.
+*****************************************************************************/
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "md5.h"
+#include "randm.h"
+
+#include "pppdebug.h"
+
+
+#if MD5_SUPPORT>0   /* this module depends on MD5 */
+#define RANDPOOLSZ 16   /* Bytes stored in the pool of randomness. */
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static char randPool[RANDPOOLSZ];   /* Pool of randomness. */
+static long randCount = 0;      /* Pseudo-random incrementer */
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * Initialize the random number generator.
+ *
+ * Since this is to be called on power up, we don't have much
+ *  system randomess to work with.  Here all we use is the
+ *  real-time clock.  We'll accumulate more randomness as soon
+ *  as things start happening.
+ */
+void avRandomInit()
+{
+    avChurnRand(NULL, 0);
+}
+
+/*
+ * Churn the randomness pool on a random event.  Call this early and often
+ *  on random and semi-random system events to build randomness in time for
+ *  usage.  For randomly timed events, pass a null pointer and a zero length
+ *  and this will use the system timer and other sources to add randomness.
+ *  If new random data is available, pass a pointer to that and it will be
+ *  included.
+ *
+ * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427
+ */
+void avChurnRand(char *randData, u32_t randLen)
+{
+    MD5_CTX md5;
+
+/*  ppp_trace(LOG_INFO, "churnRand: %u@%P\n", randLen, randData); */
+    MD5Init(&md5);
+    MD5Update(&md5, (u_char *)randPool, sizeof(randPool));
+    if (randData)
+        MD5Update(&md5, (u_char *)randData, randLen);
+    else {
+        struct {
+            /* INCLUDE fields for any system sources of randomness */
+            char foobar;
+        } sysData;
+
+        /* Load sysData fields here. */
+        ;
+        MD5Update(&md5, (u_char *)&sysData, sizeof(sysData));
+    }
+    MD5Final((u_char *)randPool, &md5);
+/*  ppp_trace(LOG_INFO, "churnRand: -> 0\n"); */
+}
+
+/*
+ * Use the random pool to generate random data.  This degrades to pseudo
+ *  random when used faster than randomness is supplied using churnRand().
+ * Note: It's important that there be sufficient randomness in randPool
+ *  before this is called for otherwise the range of the result may be
+ *  narrow enough to make a search feasible.
+ *
+ * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427
+ *
+ * XXX Why does he not just call churnRand() for each block?  Probably
+ *  so that you don't ever publish the seed which could possibly help
+ *  predict future values.
+ * XXX Why don't we preserve md5 between blocks and just update it with
+ *  randCount each time?  Probably there is a weakness but I wish that
+ *  it was documented.
+ */
+void avGenRand(char *buf, u32_t bufLen)
+{
+    MD5_CTX md5;
+    u_char tmp[16];
+    u32_t n;
+
+    while (bufLen > 0) {
+        n = LWIP_MIN(bufLen, RANDPOOLSZ);
+        MD5Init(&md5);
+        MD5Update(&md5, (u_char *)randPool, sizeof(randPool));
+        MD5Update(&md5, (u_char *)&randCount, sizeof(randCount));
+        MD5Final(tmp, &md5);
+        randCount++;
+        memcpy(buf, tmp, n);
+        buf += n;
+        bufLen -= n;
+    }
+}
+
+/*
+ * Return a new random number.
+ */
+u32_t avRandom()
+{
+    u32_t newRand;
+
+    avGenRand((char *)&newRand, sizeof(newRand));
+
+    return newRand;
+}
+
+#else /* MD5_SUPPORT */
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static int  avRandomized = 0;       /* Set when truely randomized. */
+static u32_t avRandomSeed = 0;      /* Seed used for random number generation. */
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * Initialize the random number generator.
+ *
+ * Here we attempt to compute a random number seed but even if
+ * it isn't random, we'll randomize it later.
+ *
+ * The current method uses the fields from the real time clock,
+ * the idle process counter, the millisecond counter, and the
+ * hardware timer tick counter.  When this is invoked
+ * in startup(), then the idle counter and timer values may
+ * repeat after each boot and the real time clock may not be
+ * operational.  Thus we call it again on the first random
+ * event.
+ */
+void avRandomInit()
+{
+#if 0
+    /* Get a pointer into the last 4 bytes of clockBuf. */
+    u32_t *lptr1 = (u32_t *)((char *)&clockBuf[3]);
+
+    /*
+     * Initialize our seed using the real-time clock, the idle
+     * counter, the millisecond timer, and the hardware timer
+     * tick counter.  The real-time clock and the hardware
+     * tick counter are the best sources of randomness but
+     * since the tick counter is only 16 bit (and truncated
+     * at that), the idle counter and millisecond timer
+     * (which may be small values) are added to help
+     * randomize the lower 16 bits of the seed.
+     */
+    readClk();
+    avRandomSeed += *(u32_t *)clockBuf + *lptr1 + OSIdleCtr
+             + ppp_mtime() + ((u32_t)TM1 << 16) + TM1;
+#else
+    avRandomSeed += sys_jiffies(); /* XXX */
+#endif
+        
+    /* Initialize the Borland random number generator. */
+    srand((unsigned)avRandomSeed);
+}
+
+/*
+ * Randomize our random seed value.  Here we use the fact that
+ * this function is called at *truely random* times by the polling
+ * and network functions.  Here we only get 16 bits of new random
+ * value but we use the previous value to randomize the other 16
+ * bits.
+ */
+void avRandomize(void)
+{
+    static u32_t last_jiffies;
+
+    if (!avRandomized) {
+        avRandomized = !0;
+        avRandomInit();
+        /* The initialization function also updates the seed. */
+    } else {
+/*        avRandomSeed += (avRandomSeed << 16) + TM1; */
+    	avRandomSeed += (sys_jiffies() - last_jiffies); /* XXX */
+    }
+    last_jiffies = sys_jiffies();
+}
+
+/*
+ * Return a new random number.
+ * Here we use the Borland rand() function to supply a pseudo random
+ * number which we make truely random by combining it with our own
+ * seed which is randomized by truely random events. 
+ * Thus the numbers will be truely random unless there have been no
+ * operator or network events in which case it will be pseudo random
+ * seeded by the real time clock.
+ */
+u32_t avRandom()
+{
+    return ((((u32_t)rand() << 16) + rand()) + avRandomSeed);
+}
+
+
+
+#endif /* MD5_SUPPORT */
+#endif /* PPP_SUPPORT */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/randm.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/randm.h
new file mode 100644
index 0000000..2563d89
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/randm.h
@@ -0,0 +1,81 @@
+/*****************************************************************************
+* randm.h - Random number generator header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-05-29 Guy Lancaster , Global Election Systems Inc.
+*	Extracted from avos.
+*****************************************************************************/
+
+#ifndef RANDM_H
+#define RANDM_H
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+/*
+ * Initialize the random number generator.
+ */
+void avRandomInit(void);
+
+/*
+ * Churn the randomness pool on a random event.  Call this early and often
+ *	on random and semi-random system events to build randomness in time for
+ *	usage.  For randomly timed events, pass a null pointer and a zero length
+ *	and this will use the system timer and other sources to add randomness.
+ *	If new random data is available, pass a pointer to that and it will be
+ *	included.
+ */
+void avChurnRand(char *randData, u32_t randLen);
+
+/*
+ * Randomize our random seed value.  To be called for truely random events
+ * such as user operations and network traffic.
+ */
+#if MD5_SUPPORT
+#define avRandomize()	avChurnRand(NULL, 0)
+#else
+void avRandomize(void);
+#endif
+
+/*
+ * Use the random pool to generate random data.  This degrades to pseudo
+ *	random when used faster than randomness is supplied using churnRand().
+ *	Thus it's important to make sure that the results of this are not
+ *	published directly because one could predict the next result to at
+ *	least some degree.  Also, it's important to get a good seed before
+ *	the first use.
+ */
+void avGenRand(char *buf, u32_t bufLen);
+
+/*
+ * Return a new random number.
+ */
+u32_t avRandom(void);
+
+
+#endif /* RANDM_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/vj.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/vj.c
new file mode 100644
index 0000000..2c11aff
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/vj.c
@@ -0,0 +1,633 @@
+/*
+ * Routines to compress and uncompess tcp packets (for transmission
+ * over low speed serial lines.
+ *
+ * Copyright (c) 1989 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Berkeley.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *	Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
+ *	- Initial distribution.
+ *
+ * Modified June 1993 by Paul Mackerras, paulus@cs.anu.edu.au,
+ * so that the entire packet being decompressed doesn't have
+ * to be in contiguous memory (just the compressed header).
+ *
+ * Modified March 1998 by Guy Lancaster, glanca@gesn.com,
+ * for a 16 bit processor.
+ */
+
+#include 
+
+#include "ppp.h"
+#include "vj.h"
+#include "pppdebug.h"
+
+#if VJ_SUPPORT > 0
+
+#if LINK_STATS
+#define INCR(counter) ++comp->stats.counter
+#else
+#define INCR(counter)
+#endif
+
+#if defined(NO_CHAR_BITFIELDS)
+#define getip_hl(base)	((base).ip_hl_v&0xf)
+#define getth_off(base)	(((base).th_x2_off&0xf0)>>4)
+#else
+#define getip_hl(base)	((base).ip_hl)
+#define getth_off(base)	((base).th_off)
+#endif
+
+void vj_compress_init(struct vjcompress *comp)
+{
+	register u_int i;
+	register struct cstate *tstate = comp->tstate;
+	
+#if MAX_SLOTS == 0
+	memset((char *)comp, 0, sizeof(*comp));
+#endif
+	comp->maxSlotIndex = MAX_SLOTS - 1;
+	comp->compressSlot = 0;		/* Disable slot ID compression by default. */
+	for (i = MAX_SLOTS - 1; i > 0; --i) {
+		tstate[i].cs_id = i;
+		tstate[i].cs_next = &tstate[i - 1];
+	}
+	tstate[0].cs_next = &tstate[MAX_SLOTS - 1];
+	tstate[0].cs_id = 0;
+	comp->last_cs = &tstate[0];
+	comp->last_recv = 255;
+	comp->last_xmit = 255;
+	comp->flags = VJF_TOSS;
+}
+
+
+/* ENCODE encodes a number that is known to be non-zero.  ENCODEZ
+ * checks for zero (since zero has to be encoded in the long, 3 byte
+ * form).
+ */
+#define ENCODE(n) { \
+	if ((u_short)(n) >= 256) { \
+		*cp++ = 0; \
+		cp[1] = (n); \
+		cp[0] = (n) >> 8; \
+		cp += 2; \
+	} else { \
+		*cp++ = (n); \
+	} \
+}
+#define ENCODEZ(n) { \
+	if ((u_short)(n) >= 256 || (u_short)(n) == 0) { \
+		*cp++ = 0; \
+		cp[1] = (n); \
+		cp[0] = (n) >> 8; \
+		cp += 2; \
+	} else { \
+		*cp++ = (n); \
+	} \
+}
+
+#define DECODEL(f) { \
+	if (*cp == 0) {\
+		u32_t tmp = ntohl(f) + ((cp[1] << 8) | cp[2]); \
+		(f) = htonl(tmp); \
+		cp += 3; \
+	} else { \
+		u32_t tmp = ntohl(f) + (u32_t)*cp++; \
+		(f) = htonl(tmp); \
+	} \
+}
+
+#define DECODES(f) { \
+	if (*cp == 0) {\
+		u_short tmp = ntohs(f) + (((u_short)cp[1] << 8) | cp[2]); \
+		(f) = htons(tmp); \
+		cp += 3; \
+	} else { \
+		u_short tmp = ntohs(f) + (u_short)*cp++; \
+		(f) = htons(tmp); \
+	} \
+}
+
+#define DECODEU(f) { \
+	if (*cp == 0) {\
+		(f) = htons(((u_short)cp[1] << 8) | cp[2]); \
+		cp += 3; \
+	} else { \
+		(f) = htons((u_short)*cp++); \
+	} \
+}
+
+/*
+ * vj_compress_tcp - Attempt to do Van Jacobsen header compression on a
+ * packet.  This assumes that nb and comp are not null and that the first
+ * buffer of the chain contains a valid IP header.
+ * Return the VJ type code indicating whether or not the packet was
+ * compressed.
+ */
+u_int vj_compress_tcp(
+	struct vjcompress *comp,
+	struct pbuf *pb
+)
+{
+	register struct ip *ip = (struct ip *)pb->payload;
+	register struct cstate *cs = comp->last_cs->cs_next;
+	register u_short hlen = getip_hl(*ip);
+	register struct tcphdr *oth;
+	register struct tcphdr *th;
+	register u_short deltaS, deltaA;
+	register u_long deltaL;
+	register u_int changes = 0;
+	u_char new_seq[16];
+	register u_char *cp = new_seq;
+
+	/*	
+	 * Check that the packet is IP proto TCP.
+	 */
+	if (ip->ip_p != IPPROTO_TCP)
+		return (TYPE_IP);
+		
+	/*
+	 * Bail if this is an IP fragment or if the TCP packet isn't
+	 * `compressible' (i.e., ACK isn't set or some other control bit is
+	 * set).  
+	 */
+	if ((ip->ip_off & htons(0x3fff)) || pb->tot_len < 40)
+		return (TYPE_IP);
+	th = (struct tcphdr *)&((long *)ip)[hlen];
+	if ((th->th_flags & (TCP_SYN|TCP_FIN|TCP_RST|TCP_ACK)) != TCP_ACK)
+		return (TYPE_IP);
+		
+	/*
+	 * Packet is compressible -- we're going to send either a
+	 * COMPRESSED_TCP or UNCOMPRESSED_TCP packet.  Either way we need
+	 * to locate (or create) the connection state.  Special case the
+	 * most recently used connection since it's most likely to be used
+	 * again & we don't have to do any reordering if it's used.
+	 */
+	INCR(vjs_packets);
+	if (ip->ip_src.s_addr != cs->cs_ip.ip_src.s_addr 
+			|| ip->ip_dst.s_addr != cs->cs_ip.ip_dst.s_addr 
+			|| *(long *)th != ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)]) {
+		/*
+		 * Wasn't the first -- search for it.
+		 *
+		 * States are kept in a circularly linked list with
+		 * last_cs pointing to the end of the list.  The
+		 * list is kept in lru order by moving a state to the
+		 * head of the list whenever it is referenced.  Since
+		 * the list is short and, empirically, the connection
+		 * we want is almost always near the front, we locate
+		 * states via linear search.  If we don't find a state
+		 * for the datagram, the oldest state is (re-)used.
+		 */
+		register struct cstate *lcs;
+		register struct cstate *lastcs = comp->last_cs;
+		
+		do {
+			lcs = cs; cs = cs->cs_next;
+			INCR(vjs_searches);
+			if (ip->ip_src.s_addr == cs->cs_ip.ip_src.s_addr
+					&& ip->ip_dst.s_addr == cs->cs_ip.ip_dst.s_addr
+					&& *(long *)th == ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)])
+				goto found;
+		} while (cs != lastcs);
+		
+		/*
+		 * Didn't find it -- re-use oldest cstate.  Send an
+		 * uncompressed packet that tells the other side what
+		 * connection number we're using for this conversation.
+		 * Note that since the state list is circular, the oldest
+		 * state points to the newest and we only need to set
+		 * last_cs to update the lru linkage.
+		 */
+		INCR(vjs_misses);
+		comp->last_cs = lcs;
+		hlen += getth_off(*th);
+		hlen <<= 2;
+		/* Check that the IP/TCP headers are contained in the first buffer. */
+		if (hlen > pb->len)
+			return (TYPE_IP);
+		goto uncompressed;
+		
+		found:
+		/*
+		 * Found it -- move to the front on the connection list.
+		 */
+		if (cs == lastcs)
+			comp->last_cs = lcs;
+		else {
+			lcs->cs_next = cs->cs_next;
+			cs->cs_next = lastcs->cs_next;
+			lastcs->cs_next = cs;
+		}
+	}
+	
+	oth = (struct tcphdr *)&((long *)&cs->cs_ip)[hlen];
+	deltaS = hlen;
+	hlen += getth_off(*th);
+	hlen <<= 2;
+	/* Check that the IP/TCP headers are contained in the first buffer. */
+	if (hlen > pb->len) {
+		PPPDEBUG((LOG_INFO, "vj_compress_tcp: header len %d spans buffers\n", 
+					hlen));
+		return (TYPE_IP);
+	}
+	
+	/*
+	 * Make sure that only what we expect to change changed. The first
+	 * line of the `if' checks the IP protocol version, header length &
+	 * type of service.  The 2nd line checks the "Don't fragment" bit.
+	 * The 3rd line checks the time-to-live and protocol (the protocol
+	 * check is unnecessary but costless).  The 4th line checks the TCP
+	 * header length.  The 5th line checks IP options, if any.  The 6th
+	 * line checks TCP options, if any.  If any of these things are
+	 * different between the previous & current datagram, we send the
+	 * current datagram `uncompressed'.
+	 */
+	if (((u_short *)ip)[0] != ((u_short *)&cs->cs_ip)[0] 
+			|| ((u_short *)ip)[3] != ((u_short *)&cs->cs_ip)[3] 
+			|| ((u_short *)ip)[4] != ((u_short *)&cs->cs_ip)[4] 
+			|| getth_off(*th) != getth_off(*oth) 
+			|| (deltaS > 5 && BCMP(ip + 1, &cs->cs_ip + 1, (deltaS - 5) << 2)) 
+			|| (getth_off(*th) > 5 && BCMP(th + 1, oth + 1, (getth_off(*th) - 5) << 2)))
+		goto uncompressed;
+	
+	/*
+	 * Figure out which of the changing fields changed.  The
+	 * receiver expects changes in the order: urgent, window,
+	 * ack, seq (the order minimizes the number of temporaries
+	 * needed in this section of code).
+	 */
+	if (th->th_flags & TCP_URG) {
+		deltaS = ntohs(th->th_urp);
+		ENCODEZ(deltaS);
+		changes |= NEW_U;
+	} else if (th->th_urp != oth->th_urp)
+		/* argh! URG not set but urp changed -- a sensible
+		 * implementation should never do this but RFC793
+		 * doesn't prohibit the change so we have to deal
+		 * with it. */
+		goto uncompressed;
+	
+	if ((deltaS = (u_short)(ntohs(th->th_win) - ntohs(oth->th_win))) != 0) {
+		ENCODE(deltaS);
+		changes |= NEW_W;
+	}
+	
+	if ((deltaL = ntohl(th->th_ack) - ntohl(oth->th_ack)) != 0) {
+		if (deltaL > 0xffff)
+			goto uncompressed;
+		deltaA = (u_short)deltaL;
+		ENCODE(deltaA);
+		changes |= NEW_A;
+	}
+	
+	if ((deltaL = ntohl(th->th_seq) - ntohl(oth->th_seq)) != 0) {
+		if (deltaL > 0xffff)
+			goto uncompressed;
+		deltaS = (u_short)deltaL;
+		ENCODE(deltaS);
+		changes |= NEW_S;
+	}
+	
+	switch(changes) {
+	
+	case 0:
+		/*
+		 * Nothing changed. If this packet contains data and the
+		 * last one didn't, this is probably a data packet following
+		 * an ack (normal on an interactive connection) and we send
+		 * it compressed.  Otherwise it's probably a retransmit,
+		 * retransmitted ack or window probe.  Send it uncompressed
+		 * in case the other side missed the compressed version.
+		 */
+		if (ip->ip_len != cs->cs_ip.ip_len &&
+			ntohs(cs->cs_ip.ip_len) == hlen)
+		break;
+	
+	/* (fall through) */
+	
+	case SPECIAL_I:
+	case SPECIAL_D:
+		/*
+		 * actual changes match one of our special case encodings --
+		 * send packet uncompressed.
+		 */
+		goto uncompressed;
+	
+	case NEW_S|NEW_A:
+		if (deltaS == deltaA && deltaS == ntohs(cs->cs_ip.ip_len) - hlen) {
+			/* special case for echoed terminal traffic */
+			changes = SPECIAL_I;
+			cp = new_seq;
+		}
+		break;
+	
+	case NEW_S:
+		if (deltaS == ntohs(cs->cs_ip.ip_len) - hlen) {
+			/* special case for data xfer */
+			changes = SPECIAL_D;
+			cp = new_seq;
+		}
+		break;
+	}
+	
+	deltaS = (u_short)(ntohs(ip->ip_id) - ntohs(cs->cs_ip.ip_id));
+	if (deltaS != 1) {
+		ENCODEZ(deltaS);
+		changes |= NEW_I;
+	}
+	if (th->th_flags & TCP_PSH)
+	changes |= TCP_PUSH_BIT;
+	/*
+	 * Grab the cksum before we overwrite it below.  Then update our
+	 * state with this packet's header.
+	 */
+	deltaA = ntohs(th->th_sum);
+	BCOPY(ip, &cs->cs_ip, hlen);
+	
+	/*
+	 * We want to use the original packet as our compressed packet.
+	 * (cp - new_seq) is the number of bytes we need for compressed
+	 * sequence numbers.  In addition we need one byte for the change
+	 * mask, one for the connection id and two for the tcp checksum.
+	 * So, (cp - new_seq) + 4 bytes of header are needed.  hlen is how
+	 * many bytes of the original packet to toss so subtract the two to
+	 * get the new packet size.
+	 */
+	deltaS = (u_short)(cp - new_seq);
+	if (!comp->compressSlot || comp->last_xmit != cs->cs_id) {
+		comp->last_xmit = cs->cs_id;
+		hlen -= deltaS + 4;
+		pbuf_header(pb, -hlen);
+		cp = (u_char *)pb->payload;
+		*cp++ = changes | NEW_C;
+		*cp++ = cs->cs_id;
+	} else {
+		hlen -= deltaS + 3;
+		pbuf_header(pb, -hlen);
+		cp = (u_char *)pb->payload;
+		*cp++ = changes;
+	}
+	*cp++ = deltaA >> 8;
+	*cp++ = deltaA;
+	BCOPY(new_seq, cp, deltaS);
+	INCR(vjs_compressed);
+	return (TYPE_COMPRESSED_TCP);
+
+	/*
+	 * Update connection state cs & send uncompressed packet (that is,
+	 * a regular ip/tcp packet but with the 'conversation id' we hope
+	 * to use on future compressed packets in the protocol field).
+	 */
+uncompressed:
+	BCOPY(ip, &cs->cs_ip, hlen);
+	ip->ip_p = cs->cs_id;
+	comp->last_xmit = cs->cs_id;
+	return (TYPE_UNCOMPRESSED_TCP);
+}
+
+/*
+ * Called when we may have missed a packet.
+ */
+void vj_uncompress_err(struct vjcompress *comp)
+{
+    comp->flags |= VJF_TOSS;
+	INCR(vjs_errorin);
+}
+
+/*
+ * "Uncompress" a packet of type TYPE_UNCOMPRESSED_TCP.
+ * Return 0 on success, -1 on failure.
+ */
+int vj_uncompress_uncomp(
+	struct pbuf *nb,
+	struct vjcompress *comp
+)
+{
+	register u_int hlen;
+	register struct cstate *cs;
+	register struct ip *ip;
+	
+	ip = (struct ip *)nb->payload;
+	hlen = getip_hl(*ip) << 2;
+	if (ip->ip_p >= MAX_SLOTS
+			|| hlen + sizeof(struct tcphdr) > nb->len
+			|| (hlen += getth_off(*((struct tcphdr *)&((char *)ip)[hlen])) << 2)
+			    > nb->len
+			|| hlen > MAX_HDR) {
+		PPPDEBUG((LOG_INFO, "vj_uncompress_uncomp: bad cid=%d, hlen=%d buflen=%d\n", 
+					ip->ip_p, hlen, nb->len));
+		comp->flags |= VJF_TOSS;
+		INCR(vjs_errorin);
+		return -1;
+	}
+	cs = &comp->rstate[comp->last_recv = ip->ip_p];
+	comp->flags &=~ VJF_TOSS;
+	ip->ip_p = IPPROTO_TCP;
+	BCOPY(ip, &cs->cs_ip, hlen);
+	cs->cs_hlen = hlen;
+	INCR(vjs_uncompressedin);
+	return 0;
+}
+
+/*
+ * Uncompress a packet of type TYPE_COMPRESSED_TCP.
+ * The packet is composed of a buffer chain and the first buffer
+ * must contain an accurate chain length.
+ * The first buffer must include the entire compressed TCP/IP header. 
+ * This procedure replaces the compressed header with the uncompressed
+ * header and returns the length of the VJ header.
+ */
+int vj_uncompress_tcp(
+	struct pbuf **nb,
+	struct vjcompress *comp
+)
+{
+	u_char *cp;
+	struct tcphdr *th;
+	struct cstate *cs;
+	u_short *bp;
+	struct pbuf *n0 = *nb;
+	u32_t tmp;
+	u_int vjlen, hlen, changes;
+	
+	INCR(vjs_compressedin);
+	cp = (u_char *)n0->payload;
+	changes = *cp++;
+	if (changes & NEW_C) {
+		/* 
+		 * Make sure the state index is in range, then grab the state.
+		 * If we have a good state index, clear the 'discard' flag. 
+		 */
+		if (*cp >= MAX_SLOTS) {
+			PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: bad cid=%d\n", *cp));
+			goto bad;
+		}
+		
+		comp->flags &=~ VJF_TOSS;
+		comp->last_recv = *cp++;
+	} else {
+		/* 
+		 * this packet has an implicit state index.  If we've
+		 * had a line error since the last time we got an
+		 * explicit state index, we have to toss the packet. 
+		 */
+		if (comp->flags & VJF_TOSS) {
+			PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: tossing\n"));
+			INCR(vjs_tossed);
+			return (-1);
+		}
+	}
+	cs = &comp->rstate[comp->last_recv];
+	hlen = getip_hl(cs->cs_ip) << 2;
+	th = (struct tcphdr *)&((u_char *)&cs->cs_ip)[hlen];
+	th->th_sum = htons((*cp << 8) | cp[1]);
+	cp += 2;
+	if (changes & TCP_PUSH_BIT)
+		th->th_flags |= TCP_PSH;
+	else
+		th->th_flags &=~ TCP_PSH;
+	
+	switch (changes & SPECIALS_MASK) {
+	case SPECIAL_I:
+		{
+			register u32_t i = ntohs(cs->cs_ip.ip_len) - cs->cs_hlen;
+			/* some compilers can't nest inline assembler.. */
+			tmp = ntohl(th->th_ack) + i;
+			th->th_ack = htonl(tmp);
+			tmp = ntohl(th->th_seq) + i;
+			th->th_seq = htonl(tmp);
+		}
+		break;
+	
+	case SPECIAL_D:
+		/* some compilers can't nest inline assembler.. */
+		tmp = ntohl(th->th_seq) + ntohs(cs->cs_ip.ip_len) - cs->cs_hlen;
+		th->th_seq = htonl(tmp);
+		break;
+	
+	default:
+		if (changes & NEW_U) {
+			th->th_flags |= TCP_URG;
+			DECODEU(th->th_urp);
+		} else
+			th->th_flags &=~ TCP_URG;
+		if (changes & NEW_W)
+			DECODES(th->th_win);
+		if (changes & NEW_A)
+			DECODEL(th->th_ack);
+		if (changes & NEW_S)
+			DECODEL(th->th_seq);
+		break;
+	}
+	if (changes & NEW_I) {
+		DECODES(cs->cs_ip.ip_id);
+	} else {
+		cs->cs_ip.ip_id = ntohs(cs->cs_ip.ip_id) + 1;
+		cs->cs_ip.ip_id = htons(cs->cs_ip.ip_id);
+	}
+	
+	/*
+	 * At this point, cp points to the first byte of data in the
+	 * packet.  Fill in the IP total length and update the IP
+	 * header checksum.
+	 */
+	vjlen = (u_short)(cp - (u_char*)n0->payload);
+	if (n0->len < vjlen) {
+		/* 
+		 * We must have dropped some characters (crc should detect
+		 * this but the old slip framing won't) 
+		 */
+		PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: head buffer %d too short %d\n", 
+				  n0->len, vjlen));
+		goto bad;
+	}
+	
+#if BYTE_ORDER == LITTLE_ENDIAN
+	tmp = n0->tot_len - vjlen + cs->cs_hlen;
+	cs->cs_ip.ip_len = htons(tmp);
+#else
+	cs->cs_ip.ip_len = htons(n0->tot_len - vjlen + cs->cs_hlen);
+#endif
+	
+	/* recompute the ip header checksum */
+	bp = (u_short *) &cs->cs_ip;
+	cs->cs_ip.ip_sum = 0;
+	for (tmp = 0; hlen > 0; hlen -= 2)
+		tmp += *bp++;
+	tmp = (tmp & 0xffff) + (tmp >> 16);
+	tmp = (tmp & 0xffff) + (tmp >> 16);
+	cs->cs_ip.ip_sum = (u_short)(~tmp);
+	
+	/* Remove the compressed header and prepend the uncompressed header. */
+	pbuf_header(n0, -vjlen);
+
+	if(MEM_ALIGN(n0->payload) != n0->payload) {
+		struct pbuf *np, *q;
+		u8_t *bufptr;
+
+		np = pbuf_alloc(PBUF_RAW, n0->len + cs->cs_hlen, PBUF_POOL);
+		if(!np) {
+			PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: realign failed\n"));
+			*nb = NULL;
+			goto bad;
+		}
+
+		pbuf_header(np, -cs->cs_hlen);
+
+		bufptr = n0->payload;
+		for(q = np; q != NULL; q = q->next) {
+			memcpy(q->payload, bufptr, q->len);
+			bufptr += q->len;
+		}
+
+		if(n0->next) {
+			pbuf_chain(np, n0->next);
+			pbuf_dechain(n0);
+		}
+		pbuf_free(n0);
+		n0 = np;
+	}
+
+	if(pbuf_header(n0, cs->cs_hlen)) {
+		struct pbuf *np;
+
+		LWIP_ASSERT("vj_uncompress_tcp: cs->cs_hlen <= PBUF_POOL_BUFSIZE", cs->cs_hlen <= PBUF_POOL_BUFSIZE);
+		np = pbuf_alloc(PBUF_RAW, cs->cs_hlen, PBUF_POOL);
+		if(!np) {
+			PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: prepend failed\n"));
+			*nb = NULL;
+			goto bad;
+		}
+		pbuf_cat(np, n0);
+		n0 = np;
+	}
+	LWIP_ASSERT("n0->len >= cs->cs_hlen", n0->len >= cs->cs_hlen);
+	memcpy(n0->payload, &cs->cs_ip, cs->cs_hlen);
+
+	*nb = n0;
+
+	return vjlen;
+	
+bad:
+	comp->flags |= VJF_TOSS;
+	INCR(vjs_errorin);
+	return (-1);
+}
+
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/vj.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/vj.h
new file mode 100644
index 0000000..9da2714
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/vj.h
@@ -0,0 +1,155 @@
+/*
+ * Definitions for tcp compression routines.
+ *
+ * $Id: vj.h,v 1.4 2004/02/07 00:30:03 likewise Exp $
+ *
+ * Copyright (c) 1989 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Berkeley.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *	Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
+ *	- Initial distribution.
+ */
+
+#ifndef VJ_H
+#define VJ_H
+
+#include "vjbsdhdr.h"
+
+#define MAX_SLOTS	16			/* must be > 2 and < 256 */
+#define MAX_HDR		128
+
+/*
+ * Compressed packet format:
+ *
+ * The first octet contains the packet type (top 3 bits), TCP
+ * 'push' bit, and flags that indicate which of the 4 TCP sequence
+ * numbers have changed (bottom 5 bits).  The next octet is a
+ * conversation number that associates a saved IP/TCP header with
+ * the compressed packet.  The next two octets are the TCP checksum
+ * from the original datagram.  The next 0 to 15 octets are
+ * sequence number changes, one change per bit set in the header
+ * (there may be no changes and there are two special cases where
+ * the receiver implicitly knows what changed -- see below).
+ * 
+ * There are 5 numbers which can change (they are always inserted
+ * in the following order): TCP urgent pointer, window,
+ * acknowlegement, sequence number and IP ID.  (The urgent pointer
+ * is different from the others in that its value is sent, not the
+ * change in value.)  Since typical use of SLIP links is biased
+ * toward small packets (see comments on MTU/MSS below), changes
+ * use a variable length coding with one octet for numbers in the
+ * range 1 - 255 and 3 octets (0, MSB, LSB) for numbers in the
+ * range 256 - 65535 or 0.  (If the change in sequence number or
+ * ack is more than 65535, an uncompressed packet is sent.)
+ */
+
+/*
+ * Packet types (must not conflict with IP protocol version)
+ *
+ * The top nibble of the first octet is the packet type.  There are
+ * three possible types: IP (not proto TCP or tcp with one of the
+ * control flags set); uncompressed TCP (a normal IP/TCP packet but
+ * with the 8-bit protocol field replaced by an 8-bit connection id --
+ * this type of packet syncs the sender & receiver); and compressed
+ * TCP (described above).
+ *
+ * LSB of 4-bit field is TCP "PUSH" bit (a worthless anachronism) and
+ * is logically part of the 4-bit "changes" field that follows.  Top
+ * three bits are actual packet type.  For backward compatibility
+ * and in the interest of conserving bits, numbers are chosen so the
+ * IP protocol version number (4) which normally appears in this nibble
+ * means "IP packet".
+ */
+
+/* packet types */
+#define TYPE_IP 0x40
+#define TYPE_UNCOMPRESSED_TCP 0x70
+#define TYPE_COMPRESSED_TCP 0x80
+#define TYPE_ERROR 0x00
+
+/* Bits in first octet of compressed packet */
+#define NEW_C	0x40	/* flag bits for what changed in a packet */
+#define NEW_I	0x20
+#define NEW_S	0x08
+#define NEW_A	0x04
+#define NEW_W	0x02
+#define NEW_U	0x01
+
+/* reserved, special-case values of above */
+#define SPECIAL_I (NEW_S|NEW_W|NEW_U)		/* echoed interactive traffic */
+#define SPECIAL_D (NEW_S|NEW_A|NEW_W|NEW_U)	/* unidirectional data */
+#define SPECIALS_MASK (NEW_S|NEW_A|NEW_W|NEW_U)
+
+#define TCP_PUSH_BIT 0x10
+
+
+/*
+ * "state" data for each active tcp conversation on the wire.  This is
+ * basically a copy of the entire IP/TCP header from the last packet
+ * we saw from the conversation together with a small identifier
+ * the transmit & receive ends of the line use to locate saved header.
+ */
+struct cstate {
+    struct cstate *cs_next;	/* next most recently used state (xmit only) */
+    u_short cs_hlen;		/* size of hdr (receive only) */
+    u_char cs_id;			/* connection # associated with this state */
+    u_char cs_filler;
+    union {
+		char csu_hdr[MAX_HDR];
+		struct ip csu_ip;	/* ip/tcp hdr from most recent packet */
+    } vjcs_u;
+};
+#define cs_ip vjcs_u.csu_ip
+#define cs_hdr vjcs_u.csu_hdr
+
+
+struct vjstat {
+    unsigned long vjs_packets;			/* outbound packets */
+    unsigned long vjs_compressed;		/* outbound compressed packets */
+    unsigned long vjs_searches;			/* searches for connection state */
+    unsigned long vjs_misses;			/* times couldn't find conn. state */
+    unsigned long vjs_uncompressedin;	/* inbound uncompressed packets */
+    unsigned long vjs_compressedin;		/* inbound compressed packets */
+    unsigned long vjs_errorin;			/* inbound unknown type packets */
+    unsigned long vjs_tossed;			/* inbound packets tossed because of error */
+};
+
+/*
+ * all the state data for one serial line (we need one of these per line).
+ */
+struct vjcompress {
+    struct cstate *last_cs;	/* most recently used tstate */
+    u_char last_recv;		/* last rcvd conn. id */
+    u_char last_xmit;		/* last sent conn. id */
+    u_short flags;
+    u_char maxSlotIndex;
+    u_char compressSlot;	/* Flag indicating OK to compress slot ID. */
+#if LINK_STATS
+    struct vjstat stats;
+#endif
+    struct cstate tstate[MAX_SLOTS];	/* xmit connection states */
+    struct cstate rstate[MAX_SLOTS];	/* receive connection states */
+};
+
+/* flag values */
+#define VJF_TOSS 1U		/* tossing rcvd frames because of input err */
+
+extern void  vj_compress_init (struct vjcompress *comp);
+extern u_int vj_compress_tcp (struct vjcompress *comp, struct pbuf *pb);
+extern void  vj_uncompress_err (struct vjcompress *comp);
+extern int vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp);
+extern int vj_uncompress_tcp(struct pbuf **nb, struct vjcompress *comp);
+
+#endif /* VJ_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/vjbsdhdr.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/vjbsdhdr.h
new file mode 100644
index 0000000..a7d180c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/ppp/vjbsdhdr.h
@@ -0,0 +1,76 @@
+#ifndef VJBSDHDR_H
+#define VJBSDHDR_H
+
+#include "lwip/tcp.h"
+
+
+/*
+ * Structure of an internet header, naked of options.
+ *
+ * We declare ip_len and ip_off to be short, rather than u_short
+ * pragmatically since otherwise unsigned comparisons can result
+ * against negative integers quite easily, and fail in subtle ways.
+ */
+PACK_STRUCT_BEGIN
+struct ip
+{
+#if defined(NO_CHAR_BITFIELDS)
+	u_char ip_hl_v;	/* bug in GCC for mips means the bitfield stuff will sometimes break - so we use a char for both and get round it with macro's instead... */
+#else
+#if BYTE_ORDER == LITTLE_ENDIAN
+	unsigned ip_hl:4,				/* header length */
+		ip_v:4;						/* version */
+#elif BYTE_ORDER == BIG_ENDIAN 
+	unsigned ip_v:4,					/* version */
+		ip_hl:4;					/* header length */
+#else
+	COMPLAIN - NO BYTE ORDER SELECTED!
+#endif
+#endif
+	u_char	ip_tos;					/* type of service */
+	u_short	ip_len;					/* total length */
+	u_short	ip_id;					/* identification */
+	u_short	ip_off;					/* fragment offset field */
+#define	IP_DF 0x4000				/* dont fragment flag */
+#define	IP_MF 0x2000				/* more fragments flag */
+#define	IP_OFFMASK 0x1fff			/* mask for fragmenting bits */
+	u_char	ip_ttl;					/* time to live */
+	u_char	ip_p;					/* protocol */
+	u_short	ip_sum;					/* checksum */
+	struct	in_addr ip_src,ip_dst;	/* source and dest address */
+};
+PACK_STRUCT_END
+
+typedef u32_t tcp_seq;
+
+/*
+ * TCP header.
+ * Per RFC 793, September, 1981.
+ */
+PACK_STRUCT_BEGIN
+struct tcphdr  
+{
+	u_short	th_sport;		/* source port */
+	u_short	th_dport;		/* destination port */
+	tcp_seq	th_seq;			/* sequence number */
+	tcp_seq	th_ack;			/* acknowledgement number */
+#if defined(NO_CHAR_BITFIELDS)
+	u_char th_x2_off;
+#else
+#if BYTE_ORDER == LITTLE_ENDIAN
+	unsigned	th_x2:4,		/* (unused) */
+			th_off:4;		/* data offset */
+#endif
+#if BYTE_ORDER == BIG_ENDIAN 
+	unsigned	th_off:4,		/* data offset */
+			th_x2:4;		/* (unused) */
+#endif
+#endif
+	u_char	th_flags;
+	u_short	th_win;			/* window */
+	u_short	th_sum;			/* checksum */
+	u_short	th_urp;			/* urgent pointer */
+};
+PACK_STRUCT_END
+
+#endif /* VJBSDHDR_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/slipif.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/slipif.c
new file mode 100644
index 0000000..ba8510b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP/netif/slipif.c
@@ -0,0 +1,213 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is built upon the file: src/arch/rtxc/netif/sioslip.c
+ *
+ * Author: Magnus Ivarsson  
+ */
+
+/* 
+ * This is an arch independent SLIP netif. The specific serial hooks must be
+ * provided by another file. They are sio_open, sio_recv and sio_send
+ */
+
+#include "netif/slipif.h"
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+#include "lwip/sio.h"
+
+#define SLIP_END     0300
+#define SLIP_ESC     0333
+#define SLIP_ESC_END 0334
+#define SLIP_ESC_ESC 0335
+
+#define MAX_SIZE     1500
+
+/**
+ * Send a pbuf doing the necessary SLIP encapsulation
+ *
+ * Uses the serial layer's sio_send() 
+ */
+err_t
+slipif_output(struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr)
+{
+  struct pbuf *q;
+  u16_t i;
+  u8_t c;
+
+  /* Send pbuf out on the serial I/O device. */
+  sio_send(SLIP_END, netif->state);
+
+  for (q = p; q != NULL; q = q->next) {
+    for (i = 0; i < q->len; i++) {
+      c = ((u8_t *)q->payload)[i];
+      switch (c) {
+      case SLIP_END:
+        sio_send(SLIP_ESC, netif->state);
+        sio_send(SLIP_ESC_END, netif->state);
+        break;
+      case SLIP_ESC:
+        sio_send(SLIP_ESC, netif->state);
+        sio_send(SLIP_ESC_ESC, netif->state);
+        break;
+      default:
+        sio_send(c, netif->state);
+        break;
+      }
+    }
+  }
+  sio_send(SLIP_END, netif->state);
+  return 0;
+}
+
+/**
+ * Handle the incoming SLIP stream character by character
+ *
+ * Poll the serial layer by calling sio_recv()
+ * 
+ * @return The IP packet when SLIP_END is received 
+ */
+static struct pbuf *
+slipif_input(struct netif *netif)
+{
+  u8_t c;
+  struct pbuf *p, *q;
+  u16_t recved;
+  u16_t i;
+
+  q = p = NULL;
+  recved = i = 0;
+  c = 0;
+
+  while (1) {
+    c = sio_recv(netif->state);
+    switch (c) {
+    case SLIP_END:
+      if (recved > 0) {
+        /* Received whole packet. */
+        pbuf_realloc(q, recved);
+        
+        LINK_STATS_INC(link.recv);
+        
+        LWIP_DEBUGF(SLIP_DEBUG, ("slipif: Got packet\n"));
+        return q;
+      }
+      break;
+
+    case SLIP_ESC:
+      c = sio_recv(netif->state);
+      switch (c) {
+      case SLIP_ESC_END:
+        c = SLIP_END;
+        break;
+      case SLIP_ESC_ESC:
+        c = SLIP_ESC;
+        break;
+      }
+      /* FALLTHROUGH */
+
+    default:
+      if (p == NULL) {
+        LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: alloc\n"));
+        p = pbuf_alloc(PBUF_LINK, PBUF_POOL_BUFSIZE, PBUF_POOL);
+
+        if (p == NULL) {
+          LINK_STATS_INC(link.drop);
+          LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: no new pbuf! (DROP)\n"));
+        }
+
+        if (q != NULL) {
+          pbuf_cat(q, p);
+        } else {
+          q = p;
+        }
+      }
+      if (p != NULL && recved < MAX_SIZE) {
+        ((u8_t *)p->payload)[i] = c;
+        recved++;
+        i++;
+        if (i >= p->len) {
+          i = 0;
+          if (p->next != NULL && p->next->len > 0)
+            p = p->next;
+          else
+            p = NULL;
+        }
+      }
+      break;
+    }
+
+  }
+  return NULL;
+}
+
+/**
+ * The SLIP input thread.
+ *
+ * Feed the IP layer with incoming packets
+ */
+static void
+slipif_loop(void *nf)
+{
+  struct pbuf *p;
+  struct netif *netif = (struct netif *)nf;
+
+  while (1) {
+    p = slipif_input(netif);
+    netif->input(p, netif);
+  }
+}
+
+/**
+ * SLIP netif initialization
+ *
+ * Call the arch specific sio_open and remember
+ * the opened device in the state field of the netif.
+ */
+err_t
+slipif_init(struct netif *netif)
+{
+
+  LWIP_DEBUGF(SLIP_DEBUG, ("slipif_init: netif->num=%"U16_F"\n", (u16_t)netif->num));
+
+  netif->name[0] = 's';
+  netif->name[1] = 'l';
+  netif->output = slipif_output;
+  netif->mtu = 1500;
+  netif->flags = NETIF_FLAG_POINTTOPOINT;
+
+  netif->state = sio_open(netif->num);
+  if (!netif->state)
+    return ERR_IF;
+
+  sys_thread_new(slipif_loop, netif, SLIPIF_THREAD_PRIO);
+  return ERR_OK;
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/CHANGELOG b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/CHANGELOG
new file mode 100644
index 0000000..bc0ca0e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/CHANGELOG
@@ -0,0 +1,1881 @@
+FUTURE
+
+  * TODO: The lwIP source code makes some invalid assumptions on processor
+    word-length, storage sizes and alignment. See the mailing lists for
+    problems with exoteric (/DSP) architectures showing these problems.
+    We still have to fix some of these issues neatly.
+
+  * TODO: the PPP code is broken in a few ways. There are namespace
+    collisions on BSD systems and many assumptions on word-length
+    (sizeof(int)). In ppp.c an assumption is made on the availability of
+    a thread subsystem. Either PPP needs to be moved to contrib/ports/???
+    or rearranged to be more generic.
+
+HISTORY
+
+(CVS HEAD)
+
+  * [Enter new changes just after this line - do not remove this line]
+
+  ++ New features:
+
+
+  ++ Bugfixes:
+
+
+(STABLE-1.3.0)
+
+  ++ New features:
+
+  2008-03-10 Jonathan Larmour
+  * inet_chksum.c: Allow choice of one of the sample algorithms to be
+    made from lwipopts.h. Fix comment on how to override LWIP_CHKSUM.
+
+  2008-01-22 Frédéric Bernon
+  * tcp.c, tcp_in.c, tcp.h, opt.h: Rename LWIP_CALCULATE_EFF_SEND_MSS in 
+    TCP_CALCULATE_EFF_SEND_MSS to have coherent TCP options names.
+
+  2008-01-14 Frédéric Bernon
+  * rawapi.txt, api_msg.c, tcp.c, tcp_in.c, tcp.h: changes for task #7675 "Enable
+    to refuse data on a TCP_EVENT_RECV call". Important, behavior changes for the
+    tcp_recv callback (see rawapi.txt).
+
+  2008-01-14 Frédéric Bernon, Marc Chaland
+  * ip.c: Integrate patch #6369" ip_input : checking before realloc".
+  
+  2008-01-12 Frédéric Bernon
+  * tcpip.h, tcpip.c, api.h, api_lib.c, api_msg.c, sockets.c: replace the field
+    netconn::sem per netconn::op_completed like suggested for the task #7490
+    "Add return value to sys_mbox_post".
+
+  2008-01-12 Frédéric Bernon
+  * api_msg.c, opt.h: replace DEFAULT_RECVMBOX_SIZE per DEFAULT_TCP_RECVMBOX_SIZE,
+    DEFAULT_UDP_RECVMBOX_SIZE and DEFAULT_RAW_RECVMBOX_SIZE (to optimize queues
+    sizes), like suggested for the task #7490 "Add return value to sys_mbox_post".
+
+  2008-01-10 Frédéric Bernon
+  * tcpip.h, tcpip.c: add tcpip_callback_with_block function for the task #7490
+    "Add return value to sys_mbox_post". tcpip_callback is always defined as
+    "blocking" ("block" parameter = 1).
+
+  2008-01-10 Frédéric Bernon
+  * tcpip.h, tcpip.c, api.h, api_lib.c, api_msg.c, sockets.c: replace the field
+    netconn::mbox (sys_mbox_t) per netconn::sem (sys_sem_t) for the task #7490
+    "Add return value to sys_mbox_post".
+
+  2008-01-05 Frédéric Bernon
+  * sys_arch.txt, api.h, api_lib.c, api_msg.h, api_msg.c, tcpip.c, sys.h, opt.h:
+    Introduce changes for task #7490 "Add return value to sys_mbox_post" with some
+    modifications in the sys_mbox api: sys_mbox_new take a "size" parameters which
+    indicate the number of pointers query by the mailbox. There is three defines
+    in opt.h to indicate sizes for tcpip::mbox, netconn::recvmbox, and for the 
+    netconn::acceptmbox. Port maintainers, you can decide to just add this new 
+    parameter in your implementation, but to ignore it to keep the previous behavior.
+    The new sys_mbox_trypost function return a value to know if the mailbox is
+    full or if the message is posted. Take a look to sys_arch.txt for more details.
+    This new function is used in tcpip_input (so, can be called in an interrupt
+    context since the function is not blocking), and in recv_udp and recv_raw.
+
+  2008-01-04 Frédéric Bernon, Simon Goldschmidt, Jonathan Larmour
+  * rawapi.txt, api.h, api_lib.c, api_msg.h, api_msg.c, sockets.c, tcp.h, tcp.c,
+    tcp_in.c, init.c, opt.h: rename backlog options with TCP_ prefix, limit the
+    "backlog" parameter in an u8_t, 0 is interpreted as "smallest queue", add
+    documentation in the rawapi.txt file.
+
+  2007-12-31 Kieran Mansley (based on patch from Per-Henrik Lundbolm)
+  * tcp.c, tcp_in.c, tcp_out.c, tcp.h: Add TCP persist timer
+
+  2007-12-31 Frédéric Bernon, Luca Ceresoli
+  * autoip.c, etharp.c: ip_addr.h: Integrate patch #6348: "Broadcast ARP packets
+    in autoip". The change in etharp_raw could be removed, since all calls to
+    etharp_raw use ethbroadcast for the "ethdst_addr" parameter. But it could be
+    wrong in the future.
+
+  2007-12-30 Frédéric Bernon, Tom Evans
+  * ip.c: Fix bug #21846 "LwIP doesn't appear to perform any IP Source Address
+    Filtering" reported by Tom Evans.
+
+  2007-12-21 Frédéric Bernon, Simon Goldschmidt, Jonathan Larmour
+  * tcp.h, opt.h, api.h, api_msg.h, tcp.c, tcp_in.c, api_lib.c, api_msg.c,
+    sockets.c, init.c: task #7252: Implement TCP listen backlog: Warning: raw API
+    applications have to call 'tcp_accepted(pcb)' in their accept callback to
+    keep accepting new connections.
+
+  2007-12-13 Frédéric Bernon
+  * api_msg.c, err.h, err.c, sockets.c, dns.c, dns.h: replace "enum dns_result"
+    by err_t type. Add a new err_t code "ERR_INPROGRESS".
+
+  2007-12-12 Frédéric Bernon
+  * dns.h, dns.c, opt.h: move DNS options to the "right" place. Most visibles
+    are the one which have ram usage.
+
+  2007-12-05 Frédéric Bernon
+  * netdb.c: add a LWIP_DNS_API_HOSTENT_STORAGE option to decide to use a static
+    set of variables (=0) or a local one (=1). In this last case, your port should
+    provide a function "struct hostent* sys_thread_hostent( struct hostent* h)"
+    which have to do a copy of "h" and return a pointer ont the "per-thread" copy.
+
+  2007-12-03 Simon Goldschmidt
+  * ip.c: ip_input: check if a packet is for inp first before checking all other
+    netifs on netif_list (speeds up packet receiving in most cases)
+
+  2007-11-30 Simon Goldschmidt
+  * udp.c, raw.c: task #7497: Sort lists (pcb, netif, ...) for faster access
+    UDP: move a (connected) pcb selected for input to the front of the list of
+    pcbs so that it is found faster next time. Same for RAW pcbs that have eaten
+    a packet.
+
+  2007-11-28 Simon Goldschmidt
+  * etharp.c, stats.c, stats.h, opt.h: Introduced ETHARP_STATS
+
+  2007-11-25 Simon Goldschmidt
+  * dhcp.c: dhcp_unfold_reply() uses pbuf_copy_partial instead of its own copy
+    algorithm.
+
+  2007-11-24 Simon Goldschmidt
+  * netdb.h, netdb.c, sockets.h/.c: Moved lwip_gethostbyname from sockets.c
+    to the new file netdb.c; included lwip_getaddrinfo.
+
+  2007-11-21 Simon Goldschmidt
+  * tcp.h, opt.h, tcp.c, tcp_in.c: implemented calculating the effective send-mss
+    based on the MTU of the netif used to send. Enabled by default. Disable by
+    setting LWIP_CALCULATE_EFF_SEND_MSS to 0. This fixes bug #21492.
+
+  2007-11-19 Frédéric Bernon
+  * api_msg.c, dns.h, dns.c: Implement DNS_DOES_NAME_CHECK option (check if name
+    received match the name query), implement DNS_USES_STATIC_BUF (the place where
+    copy dns payload to parse the response), return an error if there is no place
+    for a new query, and fix some minor problems.
+
+  2007-11-16 Simon Goldschmidt
+  * new files: ipv4/inet.c, ipv4/inet_chksum.c, ipv6/inet6.c
+    removed files: core/inet.c, core/inet6.c
+    Moved inet files into ipv4/ipv6 directory; splitted inet.c/inet.h into
+    inet and chksum part; changed includes in all lwIP files as appropriate
+
+  2007-11-16 Simon Goldschmidt
+  * api.h, api_msg.h, api_lib.c, api_msg.c, socket.h, socket.c: Added sequential
+    dns resolver function for netconn api (netconn_gethostbyname) and socket api
+    (gethostbyname/gethostbyname_r).
+
+  2007-11-15 Jim Pettinato, Frédéric Bernon
+  * opt.h, init.c, tcpip.c, dhcp.c, dns.h, dns.c: add DNS client for simple name
+    requests with RAW api interface. Initialization is done in lwip_init() with
+    build time options. DNS timer is added in tcpip_thread context. DHCP can set
+    DNS server ip addresses when options are received. You need to set LWIP_DNS=1
+    in your lwipopts.h file (LWIP_DNS=0 in opt.h). DNS_DEBUG can be set to get
+    some traces with LWIP_DEBUGF. Sanity check have been added. There is a "todo"
+    list with points to improve.
+
+  2007-11-06 Simon Goldschmidt
+  * opt.h, mib2.c: Patch #6215: added ifAdminStatus write support (if explicitly
+    enabled by defining SNMP_SAFE_REQUESTS to 0); added code to check link status
+    for ifOperStatus if LWIP_NETIF_LINK_CALLBACK is defined.
+
+  2007-11-06 Simon Goldschmidt
+  * api.h, api_msg.h and dependent files: Task #7410: Removed the need to include
+    core header files in api.h (ip/tcp/udp/raw.h) to hide the internal
+    implementation from netconn api applications.
+
+  2007-11-03 Frédéric Bernon
+  * api.h, api_lib.c, api_msg.c, sockets.c, opt.h: add SO_RCVBUF option for UDP &
+    RAW netconn. You need to set LWIP_SO_RCVBUF=1 in your lwipopts.h (it's disabled
+    by default). Netconn API users can use the netconn_recv_bufsize macro to access
+    it. This is a first release which have to be improve for TCP. Note it used the
+    netconn::recv_avail which need to be more "thread-safe" (note there is already
+    the problem for FIONREAD with lwip_ioctl/ioctlsocket).
+
+  2007-11-01 Frédéric Bernon, Marc Chaland
+  * sockets.h, sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c, tcp.h, tcp_out.c:
+    Integrate "patch #6250 : MSG_MORE flag for send". MSG_MORE is used at socket api
+    layer, NETCONN_MORE at netconn api layer, and TCP_WRITE_FLAG_MORE at raw api
+    layer. This option enable to delayed TCP PUSH flag on multiple "write" calls.
+    Note that previous "copy" parameter for "write" APIs is now called "apiflags".
+
+  2007-10-24 Frédéric Bernon
+  * api.h, api_lib.c, api_msg.c: Add macro API_EVENT in the same spirit than 
+    TCP_EVENT_xxx macros to get a code more readable. It could also help to remove
+    some code (like we have talk in "patch #5919 : Create compile switch to remove
+    select code"), but it could be done later.
+
+  2007-10-08 Simon Goldschmidt
+  * many files: Changed initialization: many init functions are not needed any
+    more since we now rely on the compiler initializing global and static
+    variables to zero!
+
+  2007-10-06 Simon Goldschmidt
+  * ip_frag.c, memp.c, mib2.c, ip_frag.h, memp_std.h, opt.h: Changed IP_REASSEMBLY
+    to enqueue the received pbufs so that multiple packets can be reassembled
+    simultaneously and no static reassembly buffer is needed.
+
+  2007-10-05 Simon Goldschmidt
+  * tcpip.c, etharp.h, etharp.c: moved ethernet_input from tcpip.c to etharp.c so
+    all netifs (or ports) can use it.
+
+  2007-10-05 Frédéric Bernon
+  * netifapi.h, netifapi.c: add function netifapi_netif_set_default. Change the 
+    common function to reduce a little bit the footprint (for all functions using
+    only the "netif" parameter).
+
+  2007-10-03 Frédéric Bernon
+  * netifapi.h, netifapi.c: add functions netifapi_netif_set_up, netifapi_netif_set_down,
+    netifapi_autoip_start and netifapi_autoip_stop. Use a common function to reduce
+    a little bit the footprint (for all functions using only the "netif" parameter).
+
+  2007-09-15 Frédéric Bernon
+  * udp.h, udp.c, sockets.c: Changes for "#20503 IGMP Improvement". Add IP_MULTICAST_IF
+    option in socket API, and a new field "multicast_ip" in "struct udp_pcb" (for
+    netconn and raw API users), only if LWIP_IGMP=1. Add getsockopt processing for
+    IP_MULTICAST_TTL and IP_MULTICAST_IF.
+
+  2007-09-10 Frédéric Bernon
+  * snmp.h, mib2.c: enable to remove SNMP timer (which consumne several cycles
+    even when it's not necessary). snmp_agent.txt tell to call snmp_inc_sysuptime()
+    each 10ms (but, it's intrusive if you use sys_timeout feature). Now, you can
+    decide to call snmp_add_sysuptime(100) each 1000ms (which is bigger "step", but
+    call to a lower frequency). Or, you can decide to not call snmp_inc_sysuptime()
+    or snmp_add_sysuptime(), and to define the SNMP_GET_SYSUPTIME(sysuptime) macro.
+    This one is undefined by default in mib2.c. SNMP_GET_SYSUPTIME is called inside
+    snmp_get_sysuptime(u32_t *value), and enable to change "sysuptime" value only
+    when it's queried (any direct call to "sysuptime" is changed by a call to 
+    snmp_get_sysuptime).
+
+  2007-09-09 Frédéric Bernon, Bill Florac
+  * igmp.h, igmp.c, netif.h, netif.c, ip.c: To enable to have interfaces with IGMP,
+    and others without it, there is a new NETIF_FLAG_IGMP flag to set in netif->flags
+    if you want IGMP on an interface. igmp_stop() is now called inside netif_remove().
+    igmp_report_groups() is now called inside netif_set_link_up() (need to have
+    LWIP_NETIF_LINK_CALLBACK=1) to resend reports once the link is up (avoid to wait
+    the next query message to receive the matching multicast streams).
+
+  2007-09-08 Frédéric Bernon
+  * sockets.c, ip.h, api.h, tcp.h: declare a "struct ip_pcb" which only contains
+    IP_PCB. Add in the netconn's "pcb" union a "struct ip_pcb *ip;" (no size change).
+    Use this new field to access to common pcb fields (ttl, tos, so_options, etc...).
+    Enable to access to these fields with LWIP_TCP=0.
+
+  2007-09-05 Frédéric Bernon
+  * udp.c, ipv4/icmp.c, ipv4/ip.c, ipv6/icmp.c, ipv6/ip6.c, ipv4/icmp.h,
+    ipv6/icmp.h, opt.h: Integrate "task #7272 : LWIP_ICMP option". The new option
+    LWIP_ICMP enable/disable ICMP module inside the IP stack (enable per default).
+    Be careful, disabling ICMP make your product non-compliant to RFC1122, but
+    help to reduce footprint, and to reduce "visibility" on the Internet.
+
+  2007-09-05 Frédéric Bernon, Bill Florac
+  * opt.h, sys.h, tcpip.c, slipif.c, ppp.c, sys_arch.txt: Change parameters list
+    for sys_thread_new (see "task #7252 : Create sys_thread_new_ex()"). Two new
+    parameters have to be provided: a task name, and a task stack size. For this
+    one, since it's platform dependant, you could define the best one for you in
+    your lwipopts.h. For port maintainers, you can just add these new parameters
+    in your sys_arch.c file, and but it's not mandatory, use them in your OS
+    specific functions.
+
+  2007-09-05 Frédéric Bernon
+  * inet.c, autoip.c, msg_in.c, msg_out.c, init.c: Move some build time checkings
+    inside init.c for task #7142 "Sanity check user-configurable values".
+
+  2007-09-04 Frédéric Bernon, Bill Florac
+  * igmp.h, igmp.c, memp_std.h, memp.c, init.c, opt.h: Replace mem_malloc call by
+    memp_malloc, and use a new MEMP_NUM_IGMP_GROUP option (see opt.h to define the
+    value). It will avoid potential fragmentation problems, use a counter to know
+    how many times a group is used on an netif, and free it when all applications
+    leave it. MEMP_NUM_IGMP_GROUP got 8 as default value (and init.c got a sanity
+    check if LWIP_IGMP!=0).
+
+  2007-09-03 Frédéric Bernon
+  * igmp.h, igmp.c, sockets.c, api_msg.c: Changes for "#20503 IGMP Improvement".
+    Initialize igmp_mac_filter to NULL in netif_add (this field should be set in
+    the netif's "init" function). Use the "imr_interface" field (for socket layer)
+    and/or the "interface" field (for netconn layer), for join/leave operations.
+    The igmp_join/leavegroup first parameter change from a netif to an ipaddr.
+    This field could be a netif's ipaddr, or "any" (same meaning than ip_addr_isany).
+
+  2007-08-30 Frédéric Bernon
+  * Add netbuf.h, netbuf.c, Change api.h, api_lib.c: #7249 "Split netbuf functions
+    from api/api_lib". Now netbuf API is independant of netconn, and can be used
+    with other API (application based on raw API, or future "socket2" API). Ports
+    maintainers just have to add src/api/netbuf.c in their makefile/projects.
+
+  2007-08-30 Frédéric Bernon, Jonathan Larmour
+  * init.c: Add first version of lwip_sanity_check for task #7142 "Sanity check
+    user-configurable values".
+
+  2007-08-29 Frédéric Bernon
+  * igmp.h, igmp.c, tcpip.c, init.c, netif.c: change igmp_init and add igmp_start.
+    igmp_start is call inside netif_add. Now, igmp initialization is in the same
+    spirit than the others modules. Modify some IGMP debug traces.
+
+  2007-08-29 Frédéric Bernon
+  * Add init.h, init.c, Change opt.h, tcpip.c: Task  #7213 "Add a lwip_init function"
+    Add lwip_init function to regroup all modules initializations, and to provide
+    a place to add code for task #7142 "Sanity check user-configurable values".
+    Ports maintainers should remove direct initializations calls from their code,
+    and add init.c in their makefiles. Note that lwip_init() function is called
+    inside tcpip_init, but can also be used by raw api users since all calls are
+    disabled when matching options are disabled. Also note that their is new options
+    in opt.h, you should configure in your lwipopts.h (they are enabled per default).
+
+  2007-08-26 Marc Boucher
+  * api_msg.c: do_close_internal(): Reset the callbacks and arg (conn) to NULL
+    since they can under certain circumstances be called with an invalid conn
+    pointer after the connection has been closed (and conn has been freed). 
+
+  2007-08-25 Frédéric Bernon (Artem Migaev's Patch)
+  * netif.h, netif.c: Integrate "patch #6163 : Function to check if link layer is up".
+    Add a netif_is_link_up() function if LWIP_NETIF_LINK_CALLBACK option is set.
+
+  2007-08-22 Frédéric Bernon
+  * netif.h, netif.c, opt.h: Rename LWIP_NETIF_CALLBACK in LWIP_NETIF_STATUS_CALLBACK
+    to be coherent with new LWIP_NETIF_LINK_CALLBACK option before next release.
+
+  2007-08-22 Frédéric Bernon
+  * tcpip.h, tcpip.c, ethernetif.c, opt.h: remove options ETHARP_TCPIP_INPUT &
+    ETHARP_TCPIP_ETHINPUT, now, only "ethinput" code is supported, even if the 
+    name is tcpip_input (we keep the name of 1.2.0 function).
+
+  2007-08-17 Jared Grubb
+  * memp_std.h, memp.h, memp.c, mem.c, stats.c: (Task #7136) Centralize mempool 
+    settings into new memp_std.h and optional user file lwippools.h. This adds
+    more dynamic mempools, and allows the user to create an arbitrary number of
+    mempools for mem_malloc.
+
+  2007-08-16 Marc Boucher
+  * api_msg.c: Initialize newconn->state to NETCONN_NONE in accept_function;
+    otherwise it was left to NETCONN_CLOSE and sent_tcp() could prematurely
+    close the connection.
+
+  2007-08-16 Marc Boucher
+  * sockets.c: lwip_accept(): check netconn_peer() error return.
+
+  2007-08-16 Marc Boucher
+  * mem.c, mem.h: Added mem_calloc().
+
+  2007-08-16 Marc Boucher
+  * tcpip.c, tcpip.h memp.c, memp.h: Added distinct memp (MEMP_TCPIP_MSG_INPKT)
+    for input packets to prevent floods from consuming all of MEMP_TCPIP_MSG
+    and starving other message types.
+    Renamed MEMP_TCPIP_MSG to MEMP_TCPIP_MSG_API
+
+  2007-08-16 Marc Boucher
+  * pbuf.c, pbuf.h, etharp.c, tcp_in.c, sockets.c: Split pbuf flags in pbuf
+    type and flgs (later renamed to flags).
+    Use enum pbuf_flag as pbuf_type.  Renumber PBUF_FLAG_*.
+    Improved lwip_recvfrom().  TCP push now propagated.
+
+  2007-08-16 Marc Boucher
+  * ethernetif.c, contrib/ports/various: ethbroadcast now a shared global
+    provided by etharp.
+
+  2007-08-16 Marc Boucher
+  * ppp_oe.c ppp_oe.h, auth.c chap.c fsm.c lcp.c ppp.c ppp.h,
+    etharp.c ethernetif.c, etharp.h, opt.h tcpip.h, tcpip.c:
+    Added PPPoE support and various PPP improvements.
+
+  2007-07-25 Simon Goldschmidt
+  * api_lib.c, ip_frag.c, pbuf.c, api.h, pbuf.h: Introduced pbuf_copy_partial,
+    making netbuf_copy_partial use this function.
+
+  2007-07-25 Simon Goldschmidt
+  * tcp_in.c: Fix bug #20506: Slow start / initial congestion window starts with
+    2 * mss (instead of 1 * mss previously) to comply with some newer RFCs and
+    other stacks.
+
+  2007-07-13 Jared Grubb (integrated by Frédéric Bernon)
+  * opt.h, netif.h, netif.c, ethernetif.c: Add new configuration option to add
+    a link callback in the netif struct, and functions to handle it. Be carefull
+    for port maintainers to add the NETIF_FLAG_LINK_UP flag (like in ethernetif.c)
+    if you want to be sure to be compatible with future changes...
+
+  2007-06-30 Frédéric Bernon
+  * sockets.h, sockets.c: Implement MSG_PEEK flag for recv/recvfrom functions.
+
+  2007-06-21 Simon Goldschmidt
+  * etharp.h, etharp.c: Combined etharp_request with etharp_raw for both
+    LWIP_AUTOIP =0 and =1 to remove redundant code.
+
+  2007-06-21 Simon Goldschmidt
+  * mem.c, memp.c, mem.h, memp.h, opt.h: task #6863: Introduced the option
+    MEM_USE_POOLS to use 4 pools with different sized elements instead of a
+    heap. This both prevents memory fragmentation and gives a higher speed
+    at the cost of more memory consumption. Turned off by default.
+
+  2007-06-21 Simon Goldschmidt
+  * api_lib.c, api_msg.c, api.h, api_msg.h: Converted the length argument of
+    netconn_write (and therefore also api_msg_msg.msg.w.len) from u16_t into
+    int to be able to send a bigger buffer than 64K with one time (mainly
+    used from lwip_send).
+
+  2007-06-21 Simon Goldschmidt
+  * tcp.h, api_msg.c: Moved the nagle algorithm from netconn_write/do_write
+    into a define (tcp_output_nagle) in tcp.h to provide it to raw api users, too.
+
+  2007-06-21 Simon Goldschmidt
+  * api.h, api_lib.c, api_msg.c: Fixed bug #20021: Moved sendbuf-processing in
+    netconn_write from api_lib.c to api_msg.c to also prevent multiple context-
+    changes on low memory or empty send-buffer.
+
+  2007-06-18 Simon Goldschmidt
+  * etharp.c, etharp.h: Changed etharp to use a defined hardware address length
+    of 6 to avoid loading netif->hwaddr_len every time (since this file is only
+    used for ethernet and struct eth_addr already had a defined length of 6).
+
+  2007-06-17 Simon Goldschmidt
+  * sockets.c, sockets.h: Implemented socket options SO_NO_CHECK for UDP sockets
+    to disable UDP checksum generation on transmit.
+
+  2007-06-13 Frédéric Bernon, Simon Goldschmidt
+  * debug.h, api_msg.c: change LWIP_ERROR to use it to check errors like invalid
+    pointers or parameters, and let the possibility to redefined it in cc.h. Use
+    this macro to check "conn" parameter in api_msg.c functions.
+
+  2007-06-11 Simon Goldschmidt
+  * sockets.c, sockets.h: Added UDP lite support for sockets
+
+  2007-06-10 Simon Goldschmidt
+  * udp.h, opt.h, api_msg.c, ip.c, udp.c: Included switch LWIP_UDPLITE (enabled
+    by default) to switch off UDP-Lite support if not needed (reduces udp.c code
+    size)
+
+  2007-06-09 Dominik Spies (integrated by Frédéric Bernon)
+  * autoip.h, autoip.c, dhcp.h, dhcp.c, netif.h, netif.c, etharp.h, etharp.c, opt.h:
+    AutoIP implementation available for IPv4, with new options LWIP_AUTOIP and
+    LWIP_DHCP_AUTOIP_COOP if you want to cooperate with DHCP. Some tips to adapt
+    (see TODO mark in the source code).
+
+  2007-06-09 Simon Goldschmidt
+  * etharp.h, etharp.c, ethernetif.c: Modified order of parameters for
+    etharp_output() to match netif->output so etharp_output() can be used
+    directly as netif->output to save one function call.
+
+  2007-06-08 Simon Goldschmidt
+  * netif.h, ethernetif.c, slipif.c, loopif.c: Added define
+    NETIF_INIT_SNMP(netif, type, speed) to initialize per-netif snmp variables,
+    added initialization of those to ethernetif, slipif and loopif.
+
+  2007-05-18 Simon Goldschmidt
+  * opt.h, ip_frag.c, ip_frag.h, ip.c: Added option IP_FRAG_USES_STATIC_BUF
+    (defaulting to off for now) that can be set to 0 to send fragmented
+    packets by passing PBUF_REFs down the stack.
+
+  2007-05-23 Frédéric Bernon
+  * api_lib.c: Implement SO_RCVTIMEO for accept and recv on TCP
+    connections, such present in patch #5959.
+
+  2007-05-23 Frédéric Bernon
+  * api.h, api_lib.c, api_msg.c, sockets.c: group the different NETCONN_UDPxxx
+    code in only one part...
+
+  2007-05-18 Simon Goldschmidt
+  * opt.h, memp.h, memp.c: Added option MEMP_OVERFLOW_CHECK to check for memp
+    elements to overflow. This is achieved by adding some bytes before and after
+    each pool element (increasing their size, of course), filling them with a
+    prominent value and checking them on freeing the element.
+    Set it to 2 to also check every element in every pool each time memp_malloc()
+    or memp_free() is called (slower but more helpful).
+
+  2007-05-10 Simon Goldschmidt
+  * opt.h, memp.h, memp.c, pbuf.c (see task #6831): use a new memp pool for
+    PBUF_POOL pbufs instead of the old pool implementation in pbuf.c to reduce
+    code size.
+
+  2007-05-11 Frédéric Bernon
+  * sockets.c, api_lib.c, api_msg.h, api_msg.c, netifapi.h, netifapi.c, tcpip.c:
+    Include a function pointer instead of a table index in the message to reduce
+    footprint. Disable some part of lwip_send and lwip_sendto if some options are
+    not set (LWIP_TCP, LWIP_UDP, LWIP_RAW).
+
+  2007-05-10 Simon Goldschmidt
+  * *.h (except netif/ppp/*.h): Included patch #5448: include '#ifdef __cplusplus
+    \ extern "C" {' in all header files. Now you can write your application using
+    the lwIP stack in C++ and simply #include the core files. Note I have left
+    out the netif/ppp/*h header files for now, since I don't know which files are
+    included by applications and which are for internal use only.
+
+  2007-05-09 Simon Goldschmidt
+  * opt.h, *.c/*.h: Included patch #5920: Create define to override C-library
+    memcpy. 2 Defines are created: MEMCPY() for normal memcpy, SMEMCPY() for
+    situations where some compilers might inline the copy and save a function
+    call. Also replaced all calls to memcpy() with calls to (S)MEMCPY().
+
+  2007-05-08 Simon Goldschmidt
+  * mem.h: If MEM_LIBC_MALLOC==1, allow the defines (e.g. mem_malloc() -> malloc())
+    to be overriden in case the C-library malloc implementation is not protected
+    against concurrent access.
+
+  2007-05-04 Simon Goldschmidt (Atte Kojo)
+  * etharp.c: Introduced fast one-entry-cache to speed up ARP lookup when sending
+    multiple packets to the same host.
+
+  2007-05-04 Frédéric Bernon, Jonathan Larmour
+  * sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c: Fix bug #19162 "lwip_sento: a possible
+    to corrupt remote addr/port connection state". Reduce problems "not enought memory" with
+    netbuf (if we receive lot of datagrams). Improve lwip_sendto (only one exchange between
+    sockets api and api_msg which run in tcpip_thread context). Add netconn_sento function.
+    Warning, if you directly access to "fromaddr" & "fromport" field from netbuf struct,
+    these fields are now renamed "addr" & "port".
+
+  2007-04-11 Jonathan Larmour
+  * sys.h, api_lib.c: Provide new sys_mbox_tryfetch function. Require ports to provide new
+    sys_arch_mbox_tryfetch function to get a message if one is there, otherwise return
+    with SYS_MBOX_EMPTY. sys_arch_mbox_tryfetch can be implemented as a function-like macro
+    by the port in sys_arch.h if desired.
+
+  2007-04-06 Frédéric Bernon, Simon Goldschmidt
+  * opt.h, tcpip.h, tcpip.c, netifapi.h, netifapi.c: New configuration option LWIP_NETIF_API
+    allow to use thread-safe functions to add/remove netif in list, and to start/stop dhcp
+    clients, using new functions from netifapi.h. Disable as default (no port change to do).
+
+  2007-04-05 Frédéric Bernon
+  * sockets.c: remplace ENOBUFS errors on alloc_socket by ENFILE to be more BSD compliant.
+
+  2007-04-04 Simon Goldschmidt
+  * arch.h, api_msg.c, dhcp.c, msg_in.c, sockets.c: Introduced #define LWIP_UNUSED_ARG(x)
+    use this for and architecture-independent form to tell the compiler you intentionally
+    are not using this variable. Can be overriden in cc.h.
+
+  2007-03-28 Frédéric Bernon
+  * opt.h, netif.h, dhcp.h, dhcp.c: New configuration option LWIP_NETIF_HOSTNAME allow to
+    define a hostname in netif struct (this is just a pointer, so, you can use a hardcoded
+    string, point on one of your's ethernetif field, or alloc a string you will free yourself).
+    It will be used by DHCP to register a client hostname, but can also be use when you call
+    snmp_set_sysname.
+
+  2007-03-28 Frédéric Bernon
+  * netif.h, netif.c: A new NETIF_FLAG_ETHARP flag is defined in netif.h, to allow to 
+    initialize a network interface's flag with. It tell this interface is an ethernet
+    device, and we can use ARP with it to do a "gratuitous ARP" (RFC 3220 "IP Mobility
+    Support for IPv4" section 4.6) when interface is "up" with netif_set_up().
+
+  2007-03-26 Frédéric Bernon, Jonathan Larmour
+  * opt.h, tcpip.c: New configuration option LWIP_ARP allow to disable ARP init at build
+    time if you only use PPP or SLIP. The default is enable. Note we don't have to call 
+    etharp_init in your port's initilization sequence if you use tcpip.c, because this call
+    is done in tcpip_init function.
+
+  2007-03-22 Frédéric Bernon
+  * stats.h, stats.c, msg_in.c: Stats counters can be change to u32_t if necessary with the
+    new option LWIP_STATS_LARGE. If you need this option, define LWIP_STATS_LARGE to 1 in
+    your lwipopts.h. More, unused counters are not defined in the stats structs, and not 
+    display by stats_display(). Note that some options (SYS_STATS and RAW_STATS) are defined
+    but never used. Fix msg_in.c with the correct #if test for a stat display.
+
+  2007-03-21 Kieran Mansley
+  * netif.c, netif.h: Apply patch#4197 with some changes (originator: rireland@hmgsl.com). 
+    Provides callback on netif up/down state change.
+
+  2007-03-11 Frédéric Bernon, Mace Gael, Steve Reynolds
+  * sockets.h, sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c, igmp.h, igmp.c,
+    ip.c, netif.h, tcpip.c, opt.h:
+    New configuration option LWIP_IGMP to enable IGMP processing. Based on only one 
+    filter per all network interfaces. Declare a new function in netif to enable to
+    control the MAC filter (to reduce lwIP traffic processing).
+
+  2007-03-11 Frédéric Bernon
+  * tcp.h, tcp.c, sockets.c, tcp_out.c, tcp_in.c, opt.h: Keepalive values can
+    be configured at run time with LWIP_TCP_KEEPALIVE, but don't change this
+    unless you know what you're doing (default are RFC1122 compliant). Note
+    that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set in seconds.
+
+  2007-03-08 Frédéric Bernon
+  * tcp.h: Keepalive values can be configured at compile time, but don't change
+    this unless you know what you're doing (default are RFC1122 compliant).
+
+  2007-03-08 Frédéric Bernon
+  * sockets.c, api.h, api_lib.c, tcpip.c, sys.h, sys.c, err.c, opt.h:
+    Implement LWIP_SO_RCVTIMEO configuration option to enable/disable SO_RCVTIMEO
+    on UDP sockets/netconn.
+
+  2007-03-08 Simon Goldschmidt
+  * snmp_msg.h, msg_in.c: SNMP UDP ports can be configured at compile time.
+
+  2007-03-06 Frédéric Bernon
+  * api.h, api_lib.c, sockets.h, sockets.c, tcpip.c, sys.h, sys.c, err.h: 
+    Implement SO_RCVTIMEO on UDP sockets/netconn.
+
+  2007-02-28 Kieran Mansley (based on patch from Simon Goldschmidt)
+  * api_lib.c, tcpip.c, memp.c, memp.h: make API msg structs allocated
+    on the stack and remove the API msg type from memp
+
+  2007-02-26 Jonathan Larmour (based on patch from Simon Goldschmidt)
+  * sockets.h, sockets.c: Move socket initialization to new
+    lwip_socket_init() function.
+    NOTE: this changes the API with ports. Ports will have to be
+    updated to call lwip_socket_init() now.
+
+  2007-02-26 Jonathan Larmour (based on patch from Simon Goldschmidt)
+  * api_lib.c: Use memcpy in netbuf_copy_partial.
+
+
+  ++ Bug fixes:
+
+  2008-03-17 Frédéric Bernon, Ed Kerekes
+  * igmp.h, igmp.c: Fix bug #22613 "IGMP iphdr problem" (could have
+    some problems to fill the IP header on some targets, use now the
+    ip.h macros to do it).
+
+  2008-03-13 Frédéric Bernon
+  * sockets.c: Fix bug #22435 "lwip_recvfrom with TCP break;". Using
+    (lwip_)recvfrom with valid "from" and "fromlen" parameters, on a
+    TCP connection caused a crash. Note that using (lwip_)recvfrom
+    like this is a bit slow and that using (lwip)getpeername is the
+    good lwip way to do it (so, using recv is faster on tcp sockets).
+
+  2008-03-12 Frédéric Bernon, Jonathan Larmour
+  * api_msg.c, contrib/apps/ping.c: Fix bug #22530 "api_msg.c's
+    recv_raw() does not consume data", and the ping sample (with
+    LWIP_SOCKET=1, the code did the wrong supposition that lwip_recvfrom
+    returned the IP payload, without the IP header).
+
+  2008-03-04 Jonathan Larmour
+  * mem.c, stats.c, mem.h: apply patch #6414 to avoid compiler errors
+  and/or warnings on some systems where mem_size_t and size_t differ.
+  * pbuf.c, ppp.c: Fix warnings on some systems with mem_malloc.
+
+  2008-03-04 Kieran Mansley (contributions by others) 
+  * Numerous small compiler error/warning fixes from contributions to
+    mailing list after 1.3.0 release candidate made.
+
+  2008-01-25 Cui hengbin (integrated by Frédéric Bernon)
+  * dns.c: Fix bug #22108 "DNS problem" caused by unaligned structures.
+
+  2008-01-15 Kieran Mansley
+  * tcp_out.c: BUG20511.  Modify persist timer to start when we are
+    prevented from sending by a small send window, not just a zero
+    send window.
+
+  2008-01-09 Jonathan Larmour
+  * opt.h, ip.c: Rename IP_OPTIONS define to IP_OPTIONS_ALLOWED to avoid
+    conflict with Linux system headers.
+
+  2008-01-06 Jonathan Larmour
+  * dhcp.c: fix bug #19927: "DHCP NACK problem" by clearing any existing set IP
+    address entirely on receiving a DHCPNAK, and restarting discovery.
+
+  2007-12-21 Simon Goldschmidt
+  * sys.h, api_lib.c, api_msg.c, sockets.c: fix bug #21698: "netconn->recv_avail
+    is not protected" by using new macros for interlocked access to modify/test
+    netconn->recv_avail.
+
+  2007-12-20 Kieran Mansley (based on patch from Oleg Tyshev)
+  * tcp_in.c: fix bug# 21535 (nrtx not reset correctly in SYN_SENT state)
+
+  2007-12-20 Kieran Mansley (based on patch from Per-Henrik Lundbolm)
+  * tcp.c, tcp_in.c, tcp_out.c, tcp.h: fix bug #20199 (better handling
+    of silly window avoidance and prevent lwIP from shrinking the window)
+
+  2007-12-04 Simon Goldschmidt
+  * tcp.c, tcp_in.c: fix bug #21699 (segment leak in ooseq processing when last
+    data packet was lost): add assert that all segment lists are empty in
+    tcp_pcb_remove before setting pcb to CLOSED state; don't directly set CLOSED
+    state from LAST_ACK in tcp_process
+
+  2007-12-02 Simon Goldschmidt
+  * sockets.h: fix bug #21654: exclude definition of struct timeval from #ifndef FD_SET
+    If including  for system-struct timeval, LWIP_TIMEVAL_PRIVATE now
+    has to be set to 0 in lwipopts.h
+
+  2007-12-02 Simon Goldschmidt
+  * api_msg.c, api_lib.c: fix bug #21656 (recvmbox problem in netconn API): always
+    allocate a recvmbox in netconn_new_with_proto_and_callback. For a tcp-listen
+    netconn, this recvmbox is later freed and a new mbox is allocated for acceptmbox.
+    This is a fix for thread-safety and allocates all items needed for a netconn
+    when the netconn is created.
+
+  2007-11-30 Simon Goldschmidt
+  * udp.c: first attempt to fix bug #21655 (DHCP doesn't work reliably with multiple
+    netifs): if LWIP_DHCP is enabled, UDP packets to DHCP_CLIENT_PORT are passed
+    to netif->dhcp->pcb only (if that exists) and not to any other pcb for the same
+    port (only solution to let UDP pcbs 'bind' to a netif instead of an IP address)
+
+  2007-11-27 Simon Goldschmidt
+  * ip.c: fixed bug #21643 (udp_send/raw_send don't fail if netif is down) by
+    letting ip_route only use netifs that are up.
+
+  2007-11-27 Simon Goldschmidt
+  * err.h, api_lib.c, api_msg.c, sockets.c: Changed error handling: ERR_MEM, ERR_BUF
+    and ERR_RTE are seen as non-fatal, all other errors are fatal. netconns and
+    sockets block most operations once they have seen a fatal error.
+
+  2007-11-27 Simon Goldschmidt
+  * udp.h, udp.c, dhcp.c: Implemented new function udp_sendto_if which takes the
+    netif to send as an argument (to be able to send on netifs that are down).
+
+  2007-11-26 Simon Goldschmidt
+  * tcp_in.c: Fixed bug #21582: pcb->acked accounting can be wrong when ACKs
+    arrive out-of-order
+
+  2007-11-21 Simon Goldschmidt
+  * tcp.h, tcp_out.c, api_msg.c: Fixed bug #20287: tcp_output_nagle sends too early
+    Fixed the nagle algorithm; nagle now also works for all raw API applications
+    and has to be explicitly disabled with 'tcp_pcb->flags |= TF_NODELAY'
+
+  2007-11-12 Frédéric Bernon
+  * sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c: Fixed bug #20900. Now, most
+    of the netconn_peer and netconn_addr processing is done inside tcpip_thread
+    context in do_getaddr.
+
+  2007-11-10 Simon Goldschmidt
+  * etharp.c: Fixed bug: assert fired when MEMP_ARP_QUEUE was empty (which can
+    happen any time). Now the packet simply isn't enqueued when out of memory.
+
+  2007-11-01 Simon Goldschmidt
+  * tcp.c, tcp_in.c: Fixed bug #21494: The send mss (pcb->mss) is set to 536 (or
+    TCP_MSS if that is smaller) as long as no MSS option is received from the
+    remote host.
+
+  2007-11-01 Simon Goldschmidt
+  * tcp.h, tcp.c, tcp_in.c: Fixed bug #21491: The MSS option sent (with SYN)
+    is now based on TCP_MSS instead of pcb->mss (on passive open now effectively
+    sending our configured TCP_MSS instead of the one received).
+
+  2007-11-01 Simon Goldschmidt
+  * tcp_in.c: Fixed bug #21181: On active open, the initial congestion window was
+    calculated based on the configured TCP_MSS, not on the MSS option received
+    with SYN+ACK.
+
+  2007-10-09 Simon Goldschmidt
+  * udp.c, inet.c, inet.h: Fixed UDPLite: send: Checksum was always generated too
+    short and also was generated wrong if checksum coverage != tot_len;
+    receive: checksum was calculated wrong if checksum coverage != tot_len
+
+  2007-10-08 Simon Goldschmidt
+  * mem.c: lfree was not updated in mem_realloc!
+
+  2007-10-07 Frédéric Bernon
+  * sockets.c, api.h, api_lib.c: First step to fix "bug #20900 : Potential
+    crash error problem with netconn_peer & netconn_addr". VERY IMPORTANT:
+    this change cause an API breakage for netconn_addr, since a parameter
+    type change. Any compiler should cause an error without any changes in
+    yours netconn_peer calls (so, it can't be a "silent change"). It also
+    reduce a little bit the footprint for socket layer (lwip_getpeername &
+    lwip_getsockname use now a common lwip_getaddrname function since 
+    netconn_peer & netconn_addr have the same parameters).
+
+  2007-09-20 Simon Goldschmidt
+  * tcp.c: Fixed bug #21080 (tcp_bind without check pcbs in TIME_WAIT state)
+    by checking  tcp_tw_pcbs also
+
+  2007-09-19 Simon Goldschmidt
+  * icmp.c: Fixed bug #21107 (didn't reset IP TTL in ICMP echo replies)
+
+  2007-09-15 Mike Kleshov
+  * mem.c: Fixed bug #21077 (inaccuracy in calculation of lwip_stat.mem.used)
+
+  2007-09-06 Frédéric Bernon
+  * several-files: replace some #include "arch/cc.h" by "lwip/arch.h", or simply remove
+    it as long as "lwip/opt.h" is included before (this one include "lwip/debug.h" which
+    already include "lwip/arch.h"). Like that, default defines are provided by "lwip/arch.h"
+    if they are not defined in cc.h, in the same spirit than "lwip/opt.h" for lwipopts.h.
+
+  2007-08-30 Frédéric Bernon
+  * igmp.h, igmp.c: Some changes to remove some redundant code, add some traces, 
+    and fix some coding style.
+
+  2007-08-28 Frédéric Bernon
+  * tcpip.c: Fix TCPIP_MSG_INPKT processing: now, tcpip_input can be used for any
+    kind of packets. These packets are considered like Ethernet packets (payload 
+    pointing to ethhdr) if the netif got the NETIF_FLAG_ETHARP flag. Else, packets 
+    are considered like IP packets (payload pointing to iphdr).
+
+  2007-08-27 Frédéric Bernon
+  * api.h, api_lib.c, api_msg.c: First fix for "bug #20900 : Potential crash error
+    problem with netconn_peer & netconn_addr". Introduce NETCONN_LISTEN netconn_state
+    and remove obsolete ones (NETCONN_RECV & NETCONN_ACCEPT).
+
+  2007-08-24 Kieran Mansley
+  * inet.c Modify (acc >> 16) test to ((acc >> 16) != 0) to help buggy
+    compiler (Paradigm C++)
+
+  2007-08-09 Frédéric Bernon, Bill Florac
+  * stats.h, stats.c, igmp.h, igmp.c, opt.h: Fix for bug #20503 : IGMP Improvement.
+    Introduce IGMP_STATS to centralize statistics management.
+
+  2007-08-09 Frédéric Bernon, Bill Florac
+  * udp.c: Fix for bug #20503 : IGMP Improvement. Enable to receive a multicast
+    packet on a udp pcb binded on an netif's IP address, and not on "any".
+
+  2007-08-09 Frédéric Bernon, Bill Florac
+  * igmp.h, igmp.c, ip.c: Fix minor changes from bug #20503 : IGMP Improvement.
+    This is mainly on using lookup/lookfor, and some coding styles...
+
+  2007-07-26 Frédéric Bernon (and "thedoctor")
+  * igmp.c: Fix bug #20595 to accept IGMPv3 "Query" messages.
+
+  2007-07-25 Simon Goldschmidt
+  * api_msg.c, tcp.c: Another fix for bug #20021: by not returning an error if
+    tcp_output fails in tcp_close, the code in do_close_internal gets simpler
+    (tcp_output is called again later from tcp timers).
+
+  2007-07-25 Simon Goldschmidt
+  * ip_frag.c: Fixed bug #20429: use the new pbuf_copy_partial instead of the old
+    copy_from_pbuf, which illegally modified the given pbuf.
+
+  2007-07-25 Simon Goldschmidt
+  * tcp_out.c: tcp_enqueue: pcb->snd_queuelen didn't work for chaine PBUF_RAMs:
+    changed snd_queuelen++ to snd_queuelen += pbuf_clen(p).
+
+  2007-07-24 Simon Goldschmidt
+  * api_msg.c, tcp.c: Fix bug #20480: Check the pcb passed to tcp_listen() for the
+    correct state (must be CLOSED).
+
+  2007-07-13 Thomas Taranowski (commited by Jared Grubb)
+  * memp.c: Fix bug #20478: memp_malloc returned NULL+MEMP_SIZE on failed
+    allocation. It now returns NULL.
+
+  2007-07-13 Frédéric Bernon
+  * api_msg.c: Fix bug #20318: api_msg "recv" callbacks don't call pbuf_free in
+    all error cases.
+
+  2007-07-13 Frédéric Bernon
+  * api_msg.c: Fix bug #20315: possible memory leak problem if tcp_listen failed,
+    because current code doesn't follow rawapi.txt documentation.
+
+  2007-07-13 Kieran Mansley
+  * src/core/tcp_in.c Apply patch#5741 from Oleg Tyshev to fix bug in
+    out of sequence processing of received packets
+
+  2007-07-03 Simon Goldschmidt
+  * nearly-all-files: Added assertions where PBUF_RAM pbufs are used and an
+    assumption is made that this pbuf is in one piece (i.e. not chained). These
+    assumptions clash with the possibility of converting to fully pool-based
+    pbuf implementations, where PBUF_RAM pbufs might be chained.
+
+  2007-07-03 Simon Goldschmidt
+  * api.h, api_lib.c, api_msg.c: Final fix for bug #20021 and some other problems
+    when closing tcp netconns: removed conn->sem, less context switches when
+    closing, both netconn_close and netconn_delete should safely close tcp
+    connections.
+
+  2007-07-02 Simon Goldschmidt
+  * ipv4/ip.h, ipv6/ip.h, opt.h, netif.h, etharp.h, ipv4/ip.c, netif.c, raw.c,
+    tcp_out.c, udp.c, etharp.c: Added option LWIP_NETIF_HWADDRHINT (default=off)
+    to cache ARP table indices with each pcb instead of single-entry cache for
+    the complete stack.
+
+  2007-07-02 Simon Goldschmidt
+  * tcp.h, tcp.c, tcp_in.c, tcp_out.c: Added some ASSERTS and casts to prevent
+    warnings when assigning to smaller types.
+
+  2007-06-28 Simon Goldschmidt
+  * tcp_out.c: Added check to prevent tcp_pcb->snd_queuelen from overflowing.
+
+  2007-06-28 Simon Goldschmidt
+  * tcp.h: Fixed bug #20287: Fixed nagle algorithm (sending was done too early if
+    a segment contained chained pbufs)
+
+  2007-06-28 Frédéric Bernon
+  * autoip.c: replace most of rand() calls by a macro LWIP_AUTOIP_RAND which compute
+    a "pseudo-random" value based on netif's MAC and some autoip fields. It's always
+    possible to define this macro in your own lwipopts.h to always use C library's
+    rand(). Note that autoip_create_rand_addr doesn't use this macro.
+
+  2007-06-28 Frédéric Bernon
+  * netifapi.h, netifapi.c, tcpip.h, tcpip.c: Update code to handle the option
+    LWIP_TCPIP_CORE_LOCKING, and do some changes to be coherent with last modifications
+    in api_lib/api_msg (use pointers and not type with table, etc...) 
+
+  2007-06-26 Simon Goldschmidt
+  * udp.h: Fixed bug #20259: struct udp_hdr was lacking the packin defines.
+
+  2007-06-25 Simon Goldschmidt
+  * udp.c: Fixed bug #20253: icmp_dest_unreach was called with a wrong p->payload
+    for udp packets with no matching pcb.
+
+  2007-06-25 Simon Goldschmidt
+  * udp.c: Fixed bug #20220: UDP PCB search in udp_input(): a non-local match
+    could get udp input packets if the remote side matched.
+
+  2007-06-13 Simon Goldschmidt
+  * netif.c: Fixed bug #20180 (TCP pcbs listening on IP_ADDR_ANY could get
+    changed in netif_set_ipaddr if previous netif->ip_addr.addr was 0.
+
+  2007-06-13 Simon Goldschmidt
+  * api_msg.c: pcb_new sets conn->err if protocol is not implemented
+    -> netconn_new_..() does not allocate a new connection for unsupported
+    protocols.
+
+  2007-06-13 Frédéric Bernon, Simon Goldschmidt
+  * api_lib.c: change return expression in netconn_addr and netconn_peer, because
+    conn->err was reset to ERR_OK without any reasons (and error was lost)...
+
+  2007-06-13 Frédéric Bernon, Matthias Weisser
+  * opt.h, mem.h, mem.c, memp.c, pbuf.c, ip_frag.c, vj.c: Fix bug #20162. Rename
+    MEM_ALIGN in LWIP_MEM_ALIGN and MEM_ALIGN_SIZE in LWIP_MEM_ALIGN_SIZE to avoid
+    some macro names collision with some OS macros.
+
+  2007-06-11 Simon Goldschmidt
+  * udp.c: UDP Lite: corrected the use of chksum_len (based on RFC3828: if it's 0,
+    create checksum over the complete packet. On RX, if it's < 8 (and not 0),
+    discard the packet. Also removed the duplicate 'udphdr->chksum = 0' for both
+    UDP & UDP Lite.
+
+  2007-06-11 Srinivas Gollakota & Oleg Tyshev
+  * tcp_out.c: Fix for bug #20075 : "A problem with keep-alive timer and TCP flags"
+    where TCP flags wasn't initialized in tcp_keepalive.
+
+  2007-06-03 Simon Goldschmidt
+  * udp.c: udp_input(): Input pbuf was not freed if pcb had no recv function
+    registered, p->payload was modified without modifying p->len if sending
+    icmp_dest_unreach() (had no negative effect but was definitively wrong).
+
+  2007-06-03 Simon Goldschmidt
+  * icmp.c: Corrected bug #19937: For responding to an icmp echo request, icmp
+    re-used the input pbuf even if that didn't have enough space to include the
+    link headers. Now the space is tested and a new pbuf is allocated for the
+    echo response packet if the echo request pbuf isn't big enough.
+
+  2007-06-01 Simon Goldschmidt
+  * sockets.c: Checked in patch #5914: Moved sockopt processing into tcpip_thread.
+
+  2007-05-23 Frédéric Bernon
+  * api_lib.c, sockets.c: Fixed bug #5958 for netconn_listen (acceptmbox only
+    allocated by do_listen if success) and netconn_accept errors handling. In
+    most of api_lib functions, we replace some errors checkings like "if (conn==NULL)"
+    by ASSERT, except for netconn_delete.
+
+  2007-05-23 Frédéric Bernon
+  * api_lib.c: Fixed bug #5957 "Safe-thread problem inside netconn_recv" to return
+    an error code if it's impossible to fetch a pbuf on a TCP connection (and not
+    directly close the recvmbox).
+
+  2007-05-22 Simon Goldschmidt
+  * tcp.c: Fixed bug #1895 (tcp_bind not correct) by introducing a list of
+    bound but unconnected (and non-listening) tcp_pcbs.
+
+  2007-05-22 Frédéric Bernon
+  * sys.h, sys.c, api_lib.c, tcpip.c: remove sys_mbox_fetch_timeout() (was only
+    used for LWIP_SO_RCVTIMEO option) and use sys_arch_mbox_fetch() instead of
+    sys_mbox_fetch() in api files. Now, users SHOULD NOT use internal lwIP features
+    like "sys_timeout" in their application threads.
+
+  2007-05-22 Frédéric Bernon
+  * api.h, api_lib.c, api_msg.h, api_msg.c: change the struct api_msg_msg to see
+    which parameters are used by which do_xxx function, and to avoid "misusing"
+    parameters (patch #5938).
+
+  2007-05-22 Simon Goldschmidt
+  * api_lib.c, api_msg.c, raw.c, api.h, api_msg.h, raw.h: Included patch #5938:
+    changed raw_pcb.protocol from u16_t to u8_t since for IPv4 and IPv6, proto
+    is only 8 bits wide. This affects the api, as there, the protocol was
+    u16_t, too.
+
+  2007-05-18 Simon Goldschmidt
+  * memp.c: addition to patch #5913: smaller pointer was returned but
+    memp_memory was the same size -> did not save memory.
+
+  2007-05-16 Simon Goldschmidt
+  * loopif.c, slipif.c: Fix bug #19729: free pbuf if netif->input() returns
+    != ERR_OK.
+
+  2007-05-16 Simon Goldschmidt
+  * api_msg.c, udp.c: If a udp_pcb has a local_ip set, check if it is the same
+    as the one of the netif used for sending to prevent sending from old
+    addresses after a netif address gets changed (partly fixes bug #3168).
+
+  2007-05-16 Frédéric Bernon
+  * tcpip.c, igmp.h, igmp.c: Fixed bug "#19800 : IGMP: igmp_tick() will not work
+    with NO_SYS=1". Note that igmp_init is always in tcpip_thread (and not in 
+    tcpip_init) because we have to be sure that network interfaces are already
+    added (mac filter is updated only in igmp_init for the moment).
+
+  2007-05-16 Simon Goldschmidt
+  * mem.c, memp.c: Removed semaphores from memp, changed sys_sem_wait calls
+    into sys_arch_sem_wait calls to prevent timers from running while waiting
+    for the heap. This fixes bug #19167.
+
+  2007-05-13 Simon Goldschmidt
+  * tcp.h, sockets.h, sockets.c: Fixed bug from patch #5865 by moving the defines
+    for socket options (lwip_set/-getsockopt) used with level IPPROTO_TCP from
+    tcp.h to sockets.h.
+
+  2007-05-07 Simon Goldschmidt
+  * mem.c: Another attempt to fix bug #17922.
+
+  2007-05-04 Simon Goldschmidt
+  * pbuf.c, pbuf.h, etharp.c: Further update to ARP queueing: Changed pbuf_copy()
+    implementation so that it can be reused (don't allocate the target
+    pbuf inside pbuf_copy()).
+
+  2007-05-04 Simon Goldschmidt
+  * memp.c: checked in patch #5913: in memp_malloc() we can return memp as mem
+    to save a little RAM (next pointer of memp is not used while not in pool).
+
+  2007-05-03 "maq"
+  * sockets.c: Fix ioctl FIONREAD when some data remains from last recv.
+    (patch #3574).
+
+  2007-04-23 Simon Goldschmidt
+  * loopif.c, loopif.h, opt.h, src/netif/FILES: fix bug #2595: "loopif results
+    in NULL reference for incoming TCP packets". Loopif has to be configured
+    (using LWIP_LOOPIF_MULTITHREADING) to directly call netif->input()
+    (multithreading environments, e.g. netif->input() = tcpip_input()) or
+    putting packets on a list that is fed to the stack by calling loopif_poll()
+    (single-thread / NO_SYS / polling environment where e.g.
+    netif->input() = ip_input).
+
+  2007-04-17 Jonathan Larmour
+  * pbuf.c: Use s32_t in pbuf_realloc(), as an s16_t can't reliably hold
+    the difference between two u16_t's.
+  * sockets.h: FD_SETSIZE needs to match number of sockets, which is
+    MEMP_NUM_NETCONN in sockets.c right now.
+
+  2007-04-12 Jonathan Larmour
+  * icmp.c: Reset IP header TTL in ICMP ECHO responses (bug #19580).
+
+  2007-04-12 Kieran Mansley
+  * tcp.c, tcp_in.c, tcp_out.c, tcp.h: Modify way the retransmission
+    timer is reset to fix bug#19434, with help from Oleg Tyshev.
+
+  2007-04-11 Simon Goldschmidt
+  * etharp.c, pbuf.c, pbuf.h: 3rd fix for bug #11400 (arp-queuing): More pbufs than
+    previously thought need to be copied (everything but PBUF_ROM!). Cleaned up
+    pbuf.c: removed functions no needed any more (by etharp).
+
+  2007-04-11 Kieran Mansley
+  * inet.c, ip_addr.h, sockets.h, sys.h, tcp.h: Apply patch #5745: Fix
+    "Constant is long" warnings with 16bit compilers.  Contributed by
+    avatar@mmlab.cse.yzu.edu.tw
+
+  2007-04-05 Frédéric Bernon, Jonathan Larmour
+  * api_msg.c: Fix bug #16830: "err_tcp() posts to connection mailbox when no pend on
+    the mailbox is active". Now, the post is only done during a connect, and do_send,
+    do_write and do_join_leave_group don't do anything if a previous error was signaled.
+
+  2007-04-03 Frédéric Bernon
+  * ip.c: Don't set the IP_DF ("Don't fragment") flag in the IP header in IP output
+    packets. See patch #5834.
+
+  2007-03-30 Frédéric Bernon
+  * api_msg.c: add a "pcb_new" helper function to avoid redundant code, and to add
+    missing  pcb allocations checking (in do_bind, and for each raw_new). Fix style.
+
+  2007-03-30 Frédéric Bernon
+  * most of files: prefix all debug.h define with "LWIP_" to avoid any conflict with
+    others environment defines (these were too "generic").
+
+  2007-03-28 Frédéric Bernon
+  * api.h, api_lib.c, sockets.c: netbuf_ref doesn't check its internal pbuf_alloc call
+    result and can cause a crash. lwip_send now check netbuf_ref result.
+
+  2007-03-28 Simon Goldschmidt
+  * sockets.c Remove "#include " from sockets.c to avoid multiple
+    definition of macros (in errno.h and lwip/arch.h) if LWIP_PROVIDE_ERRNO is
+    defined. This is the way it should have been already (looking at
+    doc/sys_arch.txt)
+
+  2007-03-28 Kieran Mansley
+  * opt.h Change default PBUF_POOL_BUFSIZE (again) to accomodate default MSS +
+    IP and TCP headers *and* physical link headers
+
+  2007-03-26 Frédéric Bernon (based on patch from Dmitry Potapov)
+  * api_lib.c: patch for netconn_write(), fixes a possible race condition which cause
+    to send some garbage. It is not a definitive solution, but the patch does solve
+    the problem for most cases.
+
+  2007-03-22 Frédéric Bernon
+  * api_msg.h, api_msg.c: Remove obsolete API_MSG_ACCEPT and do_accept (never used).
+
+  2007-03-22 Frédéric Bernon
+  * api_lib.c: somes resources couldn't be freed if there was errors during
+    netconn_new_with_proto_and_callback.
+
+  2007-03-22 Frédéric Bernon
+  * ethernetif.c: update netif->input calls to check return value. In older ports,
+    it's a good idea to upgrade them, even if before, there could be another problem
+    (access to an uninitialized mailbox).
+
+  2007-03-21 Simon Goldschmidt
+  * sockets.c: fixed bug #5067 (essentialy a signed/unsigned warning fixed
+    by casting to unsigned).
+
+  2007-03-21 Frédéric Bernon
+  * api_lib.c, api_msg.c, tcpip.c: integrate sys_mbox_fetch(conn->mbox, NULL) calls from
+    api_lib.c to tcpip.c's tcpip_apimsg(). Now, use a local variable and not a
+    dynamic one from memp to send tcpip_msg to tcpip_thread in a synchrone call.
+    Free tcpip_msg from tcpip_apimsg is not done in tcpip_thread. This give a
+    faster and more reliable communication between api_lib and tcpip.
+
+  2007-03-21 Frédéric Bernon
+  * opt.h: Add LWIP_NETIF_CALLBACK (to avoid compiler warning) and set it to 0.
+
+  2007-03-21 Frédéric Bernon
+  * api_msg.c, igmp.c, igmp.h: Fix C++ style comments
+
+  2007-03-21 Kieran Mansley
+  * opt.h Change default PBUF_POOL_BUFSIZE to accomodate default MSS +
+    IP and TCP headers
+
+  2007-03-21 Kieran Mansley
+  * Fix all uses of pbuf_header to check the return value.  In some
+    cases just assert if it fails as I'm not sure how to fix them, but
+    this is no worse than before when they would carry on regardless
+    of the failure.
+
+  2007-03-21 Kieran Mansley
+  * sockets.c, igmp.c, igmp.h, memp.h: Fix C++ style comments and
+    comment out missing header include in icmp.c
+
+  2007-03-20 Frédéric Bernon
+  * memp.h, stats.c: Fix stats_display function where memp_names table wasn't
+    synchronized with memp.h.
+
+  2007-03-20 Frédéric Bernon
+  * tcpip.c: Initialize tcpip's mbox, and verify if initialized in tcpip_input,
+    tcpip_ethinput, tcpip_callback, tcpip_apimsg, to fix a init problem with 
+    network interfaces. Also fix a compiler warning.
+
+  2007-03-20 Kieran Mansley
+  * udp.c: Only try and use pbuf_header() to make space for headers if
+    not a ROM or REF pbuf.
+
+  2007-03-19 Frédéric Bernon
+  * api_msg.h, api_msg.c, tcpip.h, tcpip.c: Add return types to tcpip_apimsg()
+    and api_msg_post().
+
+  2007-03-19 Frédéric Bernon
+  * Remove unimplemented "memp_realloc" function from memp.h.
+
+  2007-03-11 Simon Goldschmidt
+  * pbuf.c: checked in patch #5796: pbuf_alloc: len field claculation caused
+    memory corruption.
+
+  2007-03-11 Simon Goldschmidt (based on patch from Dmitry Potapov)
+  * api_lib.c, sockets.c, api.h, api_msg.h, sockets.h: Fixed bug #19251
+    (missing `const' qualifier in socket functions), to get more compatible to
+    standard POSIX sockets.
+
+  2007-03-11 Frédéric Bernon (based on patch from Dmitry Potapov)
+  * sockets.c: Add asserts inside bind, connect and sendto to check input
+    parameters. Remove excessive set_errno() calls after get_socket(), because
+    errno is set inside of get_socket(). Move last sock_set_errno() inside
+    lwip_close.
+
+  2007-03-09 Simon Goldschmidt
+  * memp.c: Fixed bug #11400: New etharp queueing introduced bug: memp_memory
+    was allocated too small.
+
+  2007-03-06 Simon Goldschmidt
+  * tcpip.c: Initialize dhcp timers in tcpip_thread (if LWIP_DHCP) to protect
+    the stack from concurrent access.
+
+  2007-03-06 Frédéric Bernon, Dmitry Potapov
+  * tcpip.c, ip_frag.c, ethernetif.c: Fix some build problems, and a redundancy
+    call to "lwip_stats.link.recv++;" in low_level_input() & ethernetif_input().
+
+  2007-03-06 Simon Goldschmidt
+  * ip_frag.c, ip_frag.h: Reduce code size: don't include code in those files
+    if IP_FRAG == 0 and IP_REASSEMBLY == 0
+
+  2007-03-06 Frédéric Bernon, Simon Goldschmidt
+  * opt.h, ip_frag.h, tcpip.h, tcpip.c, ethernetif.c: add new configuration
+    option named ETHARP_TCPIP_ETHINPUT, which enable the new tcpip_ethinput.
+    Allow to do ARP processing for incoming packets inside tcpip_thread
+    (protecting ARP layer against concurrent access). You can also disable
+    old code using tcp_input with new define ETHARP_TCPIP_INPUT set to 0.
+    Older ports have to use tcpip_ethinput.
+
+  2007-03-06 Simon Goldschmidt (based on patch from Dmitry Potapov)
+  * err.h, err.c: fixed compiler warning "initialization dircards qualifiers
+    from pointer target type"
+
+  2007-03-05 Frédéric Bernon
+  * opt.h, sockets.h: add new configuration options (LWIP_POSIX_SOCKETS_IO_NAMES,
+    ETHARP_TRUST_IP_MAC, review SO_REUSE)
+
+  2007-03-04 Frédéric Bernon
+  * api_msg.c: Remove some compiler warnings : parameter "pcb" was never
+    referenced.
+
+  2007-03-04 Frédéric Bernon
+  * api_lib.c: Fix "[patch #5764] api_lib.c cleanup: after patch #5687" (from
+    Dmitry Potapov).
+    The api_msg struct stay on the stack (not moved to netconn struct).
+
+  2007-03-04 Simon Goldschmidt (based on patch from Dmitry Potapov)
+  * pbuf.c: Fix BUG#19168 - pbuf_free can cause deadlock (if
+    SYS_LIGHTWEIGHT_PROT=1 & freeing PBUF_RAM when mem_sem is not available)
+    Also fixed cast warning in pbuf_alloc()
+
+  2007-03-04 Simon Goldschmidt
+  * etharp.c, etharp.h, memp.c, memp.h, opt.h: Fix BUG#11400 - don't corrupt
+    existing pbuf chain when enqueuing multiple pbufs to a pending ARP request
+
+  2007-03-03 Frédéric Bernon
+  * udp.c: remove obsolete line "static struct udp_pcb *pcb_cache = NULL;"
+    It is static, and never used in udp.c except udp_init().
+
+  2007-03-02 Simon Goldschmidt
+  * tcpip.c: Moved call to ip_init(), udp_init() and tcp_init() from
+    tcpip_thread() to tcpip_init(). This way, raw API connections can be
+    initialized before tcpip_thread is running (e.g. before OS is started)
+
+  2007-03-02 Frédéric Bernon
+  * rawapi.txt: Fix documentation mismatch with etharp.h about etharp_tmr's call
+    interval.
+
+  2007-02-28 Kieran Mansley 
+  * pbuf.c: Fix BUG#17645 - ensure pbuf payload pointer is not moved
+    outside the region of the pbuf by pbuf_header()
+
+  2007-02-28 Kieran Mansley 
+  * sockets.c: Fix BUG#19161 - ensure milliseconds timeout is non-zero
+    when supplied timeout is also non-zero 
+
+(STABLE-1.2.0)
+
+  2006-12-05 Leon Woestenberg
+  * CHANGELOG: Mention STABLE-1.2.0 release.
+
+  ++ New features:
+
+  2006-12-01 Christiaan Simons
+  * mem.h, opt.h: Added MEM_LIBC_MALLOC option.
+    Note this is a workaround. Currently I have no other options left.
+
+  2006-10-26 Christiaan Simons (accepted patch by Jonathan Larmour)
+  * ipv4/ip_frag.c: rename MAX_MTU to IP_FRAG_MAX_MTU and move define
+    to include/lwip/opt.h.
+  * ipv4/lwip/ip_frag.h: Remove unused IP_REASS_INTERVAL.
+    Move IP_REASS_MAXAGE and IP_REASS_BUFSIZE to include/lwip/opt.h.
+  * opt.h: Add above new options.
+
+  2006-08-18 Christiaan Simons
+  * tcp_{in,out}.c: added SNMP counters.
+  * ipv4/ip.c: added SNMP counters.
+  * ipv4/ip_frag.c: added SNMP counters.
+
+  2006-08-08 Christiaan Simons
+  * etharp.{c,h}: added etharp_find_addr() to read
+    (stable) ethernet/IP address pair from ARP table
+
+  2006-07-14 Christiaan Simons
+  * mib_structs.c: added
+  * include/lwip/snmp_structs.h: added
+  * netif.{c,h}, netif/ethernetif.c: added SNMP statistics to netif struct
+
+  2006-07-06 Christiaan Simons
+  * snmp/asn1_{enc,dec}.c added
+  * snmp/mib2.c added
+  * snmp/msg_{in,out}.c added
+  * include/lwip/snmp_asn1.h added
+  * include/lwip/snmp_msg.h added
+  * doc/snmp_agent.txt added
+
+  2006-03-29 Christiaan Simons
+  * inet.c, inet.h: Added platform byteswap support.
+    Added LWIP_PLATFORM_BYTESWAP define (defaults to 0) and
+    optional LWIP_PLATFORM_HTONS(), LWIP_PLATFORM_HTONL() macros.
+
+  ++ Bug fixes:
+
+  2006-11-30 Christiaan Simons
+  * dhcp.c: Fixed false triggers of request_timeout.
+
+  2006-11-28 Christiaan Simons
+  * netif.c: In netif_add() fixed missing clear of ip_addr, netmask, gw and flags.
+
+  2006-10-11 Christiaan Simons
+  * api_lib.c etharp.c, ip.c, memp.c, stats.c, sys.{c,h} tcp.h:
+    Partially accepted patch #5449 for ANSI C compatibility / build fixes.
+  * ipv4/lwip/ip.h ipv6/lwip/ip.h: Corrected UDP-Lite protocol
+    identifier from 170 to 136 (bug #17574).
+
+  2006-10-10 Christiaan Simons
+  * api_msg.c: Fixed Nagle algorithm as reported by Bob Grice.
+
+  2006-08-17 Christiaan Simons
+  * udp.c: Fixed bug #17200, added check for broadcast
+    destinations for PCBs bound to a unicast address.
+
+  2006-08-07 Christiaan Simons
+  * api_msg.c: Flushing TCP output in do_close() (bug #15926).
+
+  2006-06-27 Christiaan Simons
+  * api_msg.c: Applied patch for cold case (bug #11135).
+    In accept_function() ensure newconn->callback is always initialized.
+
+  2006-06-15 Christiaan Simons
+  * mem.h: added MEM_SIZE_F alias to fix an ancient cold case (bug #1748),
+    facilitate printing of mem_size_t and u16_t statistics.
+
+  2006-06-14 Christiaan Simons
+  * api_msg.c: Applied patch #5146 to handle allocation failures
+    in accept() by Kevin Lawson.
+
+  2006-05-26 Christiaan Simons
+  * api_lib.c: Removed conn->sem creation and destruction 
+    from netconn_write() and added sys_sem_new to netconn_new_*.
+
+(STABLE-1_1_1)
+
+  2006-03-03  Christiaan Simons
+  * ipv4/ip_frag.c: Added bound-checking assertions on ip_reassbitmap
+    access and added pbuf_alloc() return value checks.
+
+  2006-01-01  Leon Woestenberg 
+  * tcp_{in,out}.c, tcp_out.c: Removed 'even sndbuf' fix in TCP, which is
+    now handled by the checksum routine properly.
+
+  2006-02-27  Leon Woestenberg 
+   * pbuf.c: Fix alignment; pbuf_init() would not work unless
+     pbuf_pool_memory[] was properly aligned. (Patch by Curt McDowell.)
+
+  2005-12-20  Leon Woestenberg 
+  * tcp.c: Remove PCBs which stay in LAST_ACK state too long. Patch
+    submitted by Mitrani Hiroshi.
+
+  2005-12-15  Christiaan Simons
+  * inet.c: Disabled the added summing routine to preserve code space.
+
+  2005-12-14  Leon Woestenberg 
+  * tcp_in.c: Duplicate FIN ACK race condition fix by Kelvin Lawson.
+    Added Curt McDowell's optimized checksumming routine for future
+    inclusion. Need to create test case for unaliged, aligned, odd,
+    even length combination of cases on various endianess machines.
+
+  2005-12-09  Christiaan Simons
+  * inet.c: Rewrote standard checksum routine in proper portable C.
+
+  2005-11-25  Christiaan Simons
+  * udp.c tcp.c: Removed SO_REUSE hack. Should reside in socket code only.
+  * *.c: introduced cc.h LWIP_DEBUG formatters matching the u16_t, s16_t,
+    u32_t, s32_t typedefs. This solves most debug word-length assumes.
+
+  2005-07-17 Leon Woestenberg 
+  * inet.c: Fixed unaligned 16-bit access in the standard checksum
+    routine by Peter Jolasson.
+  * slipif.c: Fixed implementation assumption of single-pbuf datagrams.
+
+  2005-02-04 Leon Woestenberg 
+  * tcp_out.c: Fixed uninitialized 'queue' referenced in memerr branch.
+  * tcp_{out|in}.c: Applied patch fixing unaligned access.
+
+  2005-01-04 Leon Woestenberg 
+  * pbuf.c: Fixed missing semicolon after LWIP_DEBUG statement.
+
+  2005-01-03 Leon Woestenberg 
+  * udp.c: UDP pcb->recv() was called even when it was NULL.
+
+(STABLE-1_1_0)
+
+  2004-12-28 Leon Woestenberg 
+  * etharp.*: Disabled multiple packets on the ARP queue.
+    This clashes with TCP queueing.
+
+  2004-11-28 Leon Woestenberg 
+  * etharp.*: Fixed race condition from ARP request to ARP timeout.
+    Halved the ARP period, doubled the period counts.
+    ETHARP_MAX_PENDING now should be at least 2. This prevents
+    the counter from reaching 0 right away (which would allow
+    too little time for ARP responses to be received).
+
+  2004-11-25 Leon Woestenberg 
+  * dhcp.c: Decline messages were not multicast but unicast.
+  * etharp.c: ETHARP_CREATE is renamed to ETHARP_TRY_HARD.
+    Do not try hard to insert arbitrary packet's source address,
+    etharp_ip_input() now calls etharp_update() without ETHARP_TRY_HARD. 
+    etharp_query() now always DOES call ETHARP_TRY_HARD so that users
+    querying an address will see it appear in the cache (DHCP could
+    suffer from this when a server invalidly gave an in-use address.)
+  * ipv4/ip_addr.h: Renamed ip_addr_maskcmp() to _netcmp() as we are
+    comparing network addresses (identifiers), not the network masks
+    themselves.
+  * ipv4/ip_addr.c: ip_addr_isbroadcast() now checks that the given
+    IP address actually belongs to the network of the given interface.
+
+  2004-11-24 Kieran Mansley 
+  * tcp.c: Increment pcb->snd_buf when ACK is received in SYN_SENT state.
+
+(STABLE-1_1_0-RC1)
+
+  2004-10-16 Kieran Mansley 
+  * tcp.c: Add code to tcp_recved() to send an ACK (window update) immediately,
+    even if one is already pending, if the rcv_wnd is above a threshold
+    (currently TCP_WND/2). This avoids waiting for a timer to expire to send a
+    delayed ACK in order to open the window if the stack is only receiving data.
+
+  2004-09-12 Kieran Mansley 
+  * tcp*.*: Retransmit time-out handling improvement by Sam Jansen.
+
+  2004-08-20 Tony Mountifield 
+  * etharp.c: Make sure the first pbuf queued on an ARP entry
+    is properly ref counted.
+
+  2004-07-27 Tony Mountifield 
+  * debug.h: Added (int) cast in LWIP_DEBUGF() to avoid compiler
+    warnings about comparison.
+  * pbuf.c: Stopped compiler complaining of empty if statement
+    when LWIP_DEBUGF() empty.  Closed an unclosed comment.
+  * tcp.c: Stopped compiler complaining of empty if statement
+    when LWIP_DEBUGF() empty.
+  * ip.h Corrected IPH_TOS() macro: returns a byte, so doesn't need htons().
+  * inet.c: Added a couple of casts to quiet the compiler.
+    No need to test isascii(c) before isdigit(c) or isxdigit(c).
+
+  2004-07-22 Tony Mountifield 
+  * inet.c: Made data types consistent in inet_ntoa().
+    Added casts for return values of checksum routines, to pacify compiler.
+  * ip_frag.c, tcp_out.c, sockets.c, pbuf.c
+    Small corrections to some debugging statements, to pacify compiler.
+
+  2004-07-21 Tony Mountifield 
+  * etharp.c: Removed spurious semicolon and added missing end-of-comment.
+  * ethernetif.c Updated low_level_output() to match prototype for
+    netif->linkoutput and changed low_level_input() similarly for consistency.
+  * api_msg.c: Changed recv_raw() from int to u8_t, to match prototype
+    of raw_recv() in raw.h and so avoid compiler error.
+  * sockets.c: Added trivial (int) cast to keep compiler happier.
+  * ip.c, netif.c Changed debug statements to use the tidier ip4_addrN() macros.
+
+(STABLE-1_0_0)
+
+  ++ Changes:
+
+  2004-07-05 Leon Woestenberg 
+  * sockets.*: Restructured LWIP_PRIVATE_TIMEVAL. Make sure
+    your cc.h file defines this either 1 or 0. If non-defined,
+    defaults to 1.
+  * .c: Added  and  includes where used.
+  * etharp.c: Made some array indices unsigned.
+
+  2004-06-27 Leon Woestenberg 
+  * netif.*: Added netif_set_up()/down().
+  * dhcp.c: Changes to restart program flow.
+
+  2004-05-07 Leon Woestenberg 
+  * etharp.c: In find_entry(), instead of a list traversal per candidate, do a
+    single-pass lookup for different candidates. Should exploit locality.
+
+  2004-04-29 Leon Woestenberg 
+  * tcp*.c: Cleaned up source comment documentation for Doxygen processing.
+  * opt.h: ETHARP_ALWAYS_INSERT option removed to comply with ARP RFC.
+  * etharp.c: update_arp_entry() only adds new ARP entries when adviced to by
+    the caller. This deprecates the ETHARP_ALWAYS_INSERT overrule option.
+
+  ++ Bug fixes:
+
+  2004-04-27 Leon Woestenberg 
+  * etharp.c: Applied patch of bug #8708 by Toni Mountifield with a solution
+    suggested by Timmy Brolin. Fix for 32-bit processors that cannot access
+    non-aligned 32-bit words, such as soms 32-bit TCP/IP header fields. Fix
+    is to prefix the 14-bit Ethernet headers with two padding bytes.
+
+  2004-04-23 Leon Woestenberg 
+  * ip_addr.c: Fix in the ip_addr_isbroadcast() check.
+  * etharp.c: Fixed the case where the packet that initiates the ARP request
+    is not queued, and gets lost. Fixed the case where the packets destination
+    address is already known; we now always queue the packet and perform an ARP
+    request.
+
+(STABLE-0_7_0)
+
+  ++ Bug fixes:
+
+  * Fixed TCP bug for SYN_SENT to ESTABLISHED state transition.
+  * Fixed TCP bug in dequeueing of FIN from out of order segment queue.
+  * Fixed two possible NULL references in rare cases.
+
+(STABLE-0_6_6)
+
+  ++ Bug fixes:
+
+  * Fixed DHCP which did not include the IP address in DECLINE messages.
+
+  ++ Changes:
+
+  * etharp.c has been hauled over a bit.
+
+(STABLE-0_6_5)
+
+  ++ Bug fixes:
+
+  * Fixed TCP bug induced by bad window resizing with unidirectional TCP traffic.
+  * Packets sent from ARP queue had invalid source hardware address.
+
+  ++ Changes:
+
+  * Pass-by ARP requests do now update the cache.
+
+  ++ New features:
+
+  * No longer dependent on ctype.h.
+  * New socket options.
+  * Raw IP pcb support.
+
+(STABLE-0_6_4)
+
+  ++ Bug fixes:
+
+  * Some debug formatters and casts fixed.
+  * Numereous fixes in PPP.
+
+  ++ Changes:
+
+  * DEBUGF now is LWIP_DEBUGF
+  * pbuf_dechain() has been re-enabled.
+  * Mentioned the changed use of CVS branches in README.
+
+(STABLE-0_6_3)
+
+  ++ Bug fixes:
+
+  * Fixed pool pbuf memory leak in pbuf_alloc().
+    Occured if not enough PBUF_POOL pbufs for a packet pbuf chain.
+    Reported by Savin Zlobec.
+
+  * PBUF_POOL chains had their tot_len field not set for non-first
+    pbufs. Fixed in pbuf_alloc().
+
+  ++ New features:
+
+  * Added PPP stack contributed by Marc Boucher
+
+  ++ Changes:
+
+  * Now drops short packets for ICMP/UDP/TCP protocols. More robust.
+
+  * ARP queueuing now queues the latest packet instead of the first.
+    This is the RFC recommended behaviour, but can be overridden in
+    lwipopts.h.
+
+(0.6.2)
+
+  ++ Bugfixes:
+
+  * TCP has been fixed to deal with the new use of the pbuf->ref
+    counter.
+
+  * DHCP dhcp_inform() crash bug fixed.
+
+  ++ Changes:
+
+  * Removed pbuf_pool_free_cache and pbuf_pool_alloc_cache. Also removed
+    pbuf_refresh(). This has sped up pbuf pool operations considerably.
+    Implemented by David Haas.
+
+(0.6.1)
+
+  ++ New features:
+
+  * The packet buffer implementation has been enhanced to support
+    zero-copy and copy-on-demand for packet buffers which have their
+    payloads in application-managed memory.
+    Implemented by David Haas.
+
+    Use PBUF_REF to make a pbuf refer to RAM. lwIP will use zero-copy
+    if an outgoing packet can be directly sent on the link, or perform
+    a copy-on-demand when necessary.
+
+    The application can safely assume the packet is sent, and the RAM
+    is available to the application directly after calling udp_send()
+    or similar function.
+
+  ++ Bugfixes:
+
+  * ARP_QUEUEING should now correctly work for all cases, including
+    PBUF_REF.
+    Implemented by Leon Woestenberg.
+
+  ++ Changes:
+
+  * IP_ADDR_ANY is no longer a NULL pointer. Instead, it is a pointer
+    to a '0.0.0.0' IP address.
+
+  * The packet buffer implementation is changed. The pbuf->ref counter
+    meaning has changed, and several pbuf functions have been
+    adapted accordingly.
+
+  * netif drivers have to be changed to set the hardware address length field
+    that must be initialized correctly by the driver (hint: 6 for Ethernet MAC).
+    See the contrib/ports/c16x cs8900 driver as a driver example.
+
+  * netif's have a dhcp field that must be initialized to NULL by the driver.
+    See the contrib/ports/c16x cs8900 driver as a driver example.
+
+(0.5.x) This file has been unmaintained up to 0.6.1. All changes are
+  logged in CVS but have not been explained here.
+
+(0.5.3) Changes since version 0.5.2
+
+  ++ Bugfixes:
+
+  * memp_malloc(MEMP_API_MSG) could fail with multiple application
+    threads because it wasn't protected by semaphores.
+
+  ++ Other changes:
+
+  * struct ip_addr now packed.
+
+  * The name of the time variable in arp.c has been changed to ctime
+    to avoid conflicts with the time() function.
+
+(0.5.2) Changes since version 0.5.1
+
+  ++ New features:
+
+  * A new TCP function, tcp_tmr(), now handles both TCP timers.
+
+  ++ Bugfixes:
+
+  * A bug in tcp_parseopt() could cause the stack to hang because of a
+    malformed TCP option.
+
+  * The address of new connections in the accept() function in the BSD
+    socket library was not handled correctly.
+
+  * pbuf_dechain() did not update the ->tot_len field of the tail.
+
+  * Aborted TCP connections were not handled correctly in all
+    situations.
+
+  ++ Other changes:
+
+  * All protocol header structs are now packed.
+
+  * The ->len field in the tcp_seg structure now counts the actual
+    amount of data, and does not add one for SYN and FIN segments.
+
+(0.5.1) Changes since version 0.5.0
+
+  ++ New features:
+
+  * Possible to run as a user process under Linux.
+
+  * Preliminary support for cross platform packed structs.
+
+  * ARP timer now implemented.
+
+  ++ Bugfixes:
+
+  * TCP output queue length was badly initialized when opening
+    connections.
+
+  * TCP delayed ACKs were not sent correctly.
+
+  * Explicit initialization of BSS segment variables.
+
+  * read() in BSD socket library could drop data.
+
+  * Problems with memory alignment.
+
+  * Situations when all TCP buffers were used could lead to
+    starvation.
+
+  * TCP MSS option wasn't parsed correctly.
+
+  * Problems with UDP checksum calculation.
+
+  * IP multicast address tests had endianess problems.
+
+  * ARP requests had wrong destination hardware address.
+
+  ++ Other changes:
+
+  * struct eth_addr changed from u16_t[3] array to u8_t[6].
+
+  * A ->linkoutput() member was added to struct netif.
+
+  * TCP and UDP ->dest_* struct members where changed to ->remote_*.
+
+  * ntoh* macros are now null definitions for big endian CPUs.
+
+(0.5.0) Changes since version 0.4.2
+
+  ++ New features:
+
+  * Redesigned operating system emulation layer to make porting easier.
+
+  * Better control over TCP output buffers.
+
+  * Documenation added.
+
+  ++ Bugfixes:
+
+  * Locking issues in buffer management.
+
+  * Bugfixes in the sequential API.
+
+  * IP forwarding could cause memory leakage. This has been fixed.
+
+  ++ Other changes:
+
+  * Directory structure somewhat changed; the core/ tree has been
+    collapsed.
+
+(0.4.2) Changes since version 0.4.1
+
+  ++ New features:
+
+  * Experimental ARP implementation added.
+
+  * Skeleton Ethernet driver added.
+
+  * Experimental BSD socket API library added.
+
+  ++ Bugfixes:
+
+  * In very intense situations, memory leakage could occur. This has
+    been fixed.
+
+  ++ Other changes:
+
+  * Variables named "data" and "code" have been renamed in order to
+    avoid name conflicts in certain compilers.
+
+  * Variable++ have in appliciable cases been translated to ++variable
+    since some compilers generate better code in the latter case.
+
+(0.4.1) Changes since version 0.4
+
+  ++ New features:
+
+  * TCP: Connection attempts time out earlier than data
+    transmissions. Nagle algorithm implemented. Push flag set on the
+    last segment in a burst.
+
+  * UDP: experimental support for UDP-Lite extensions.
+
+  ++ Bugfixes:
+
+  * TCP: out of order segments were in some cases handled incorrectly,
+    and this has now been fixed. Delayed acknowledgements was broken
+    in 0.4, has now been fixed. Binding to an address that is in use
+    now results in an error. Reset connections sometimes hung an
+    application; this has been fixed.
+
+  * Checksum calculation sometimes failed for chained pbufs with odd
+    lengths. This has been fixed.
+
+  * API: a lot of bug fixes in the API. The UDP API has been improved
+    and tested. Error reporting and handling has been
+    improved. Logical flaws and race conditions for incoming TCP
+    connections has been found and removed.
+
+  * Memory manager: alignment issues. Reallocating memory sometimes
+    failed, this has been fixed.
+
+  * Generic library: bcopy was flawed and has been fixed.
+
+  ++ Other changes:
+
+  * API: all datatypes has been changed from generic ones such as
+    ints, to specified ones such as u16_t. Functions that return
+    errors now have the correct type (err_t).
+
+  * General: A lot of code cleaned up and debugging code removed. Many
+    portability issues have been fixed.
+
+  * The license was changed; the advertising clause was removed.
+
+  * C64 port added.
+
+  * Thanks: Huge thanks go to Dagan Galarneau, Horst Garnetzke, Petri
+    Kosunen, Mikael Caleres, and Frits Wilmink for reporting and
+    fixing bugs!
+
+(0.4) Changes since version 0.3.1
+
+  * Memory management has been radically changed; instead of
+    allocating memory from a shared heap, memory for objects that are
+    rapidly allocated and deallocated is now kept in pools. Allocation
+    and deallocation from those memory pools is very fast. The shared
+    heap is still present but is used less frequently.
+
+  * The memory, memory pool, and packet buffer subsystems now support
+    4-, 2-, or 1-byte alignment.
+
+  * "Out of memory" situations are handled in a more robust way.
+
+  * Stack usage has been reduced.
+
+  * Easier configuration of lwIP parameters such as memory usage,
+    TTLs, statistics gathering, etc. All configuration parameters are
+    now kept in a single header file "lwipopts.h".
+
+  * The directory structure has been changed slightly so that all
+    architecture specific files are kept under the src/arch
+    hierarchy.
+
+  * Error propagation has been improved, both in the protocol modules
+    and in the API.
+
+  * The code for the RTXC architecture has been implemented, tested
+    and put to use.
+
+  * Bugs have been found and corrected in the TCP, UDP, IP, API, and
+    the Internet checksum modules.
+
+  * Bugs related to porting between a 32-bit and a 16-bit architecture
+    have been found and corrected.
+
+  * The license has been changed slightly to conform more with the
+    original BSD license, including the advertisement clause.
+
+(0.3.1) Changes since version 0.3
+
+  * Fix of a fatal bug in the buffer management. Pbufs with allocated
+    RAM never returned the RAM when the pbuf was deallocated.
+
+  * TCP congestion control, window updates and retransmissions did not
+    work correctly. This has now been fixed.
+
+  * Bugfixes in the API.
+
+(0.3) Changes since version 0.2
+
+  * New and improved directory structure. All include files are now
+    kept in a dedicated include/ directory.
+
+  * The API now has proper error handling. A new function,
+    netconn_err(), now returns an error code for the connection in
+    case of errors.
+
+  * Improvements in the memory management subsystem. The system now
+    keeps a pointer to the lowest free memory block. A new function,
+    mem_malloc2() tries to allocate memory once, and if it fails tries
+    to free some memory and retry the allocation.
+
+  * Much testing has been done with limited memory
+    configurations. lwIP now does a better job when overloaded.
+
+  * Some bugfixes and improvements to the buffer (pbuf) subsystem.
+
+  * Many bugfixes in the TCP code:
+
+    - Fixed a bug in tcp_close().
+
+    - The TCP receive window was incorrectly closed when out of
+      sequence segments was received. This has been fixed.
+
+    - Connections are now timed-out of the FIN-WAIT-2 state.
+
+    - The initial congestion window could in some cases be too
+      large. This has been fixed.
+
+    - The retransmission queue could in some cases be screwed up. This
+      has been fixed.
+
+    - TCP RST flag now handled correctly.
+
+    - Out of sequence data was in some cases never delivered to the
+      application. This has been fixed.
+
+    - Retransmitted segments now contain the correct acknowledgment
+      number and advertised window.
+
+    - TCP retransmission timeout backoffs are not correctly computed
+      (ala BSD). After a number of retransmissions, TCP now gives up
+      the connection.
+
+  * TCP connections now are kept on three lists, one for active
+    connections, one for listening connections, and one for
+    connections that are in TIME-WAIT. This greatly speeds up the fast
+    timeout processing for sending delayed ACKs.
+
+  * TCP now provides proper feedback to the application when a
+    connection has been successfully set up.
+
+  * More comments have been added to the code. The code has also been
+    somewhat cleaned up.
+
+(0.2) Initial public release.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/COPYING b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/COPYING
new file mode 100644
index 0000000..0d77a67
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/COPYING
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2001, 2002 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/FILES b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/FILES
new file mode 100644
index 0000000..30d6e32
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/FILES
@@ -0,0 +1,4 @@
+src/      - The source code for the lwIP TCP/IP stack.
+doc/      - The documentation for lwIP.
+
+See also the FILES file in each subdirectory.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/README b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/README
new file mode 100644
index 0000000..a6c9c73
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/README
@@ -0,0 +1,89 @@
+INTRODUCTION
+
+lwIP is a small independent implementation of the TCP/IP protocol
+suite that has been developed by Adam Dunkels at the Computer and
+Networks Architectures (CNA) lab at the Swedish Institute of Computer
+Science (SICS).
+
+The focus of the lwIP TCP/IP implementation is to reduce the RAM usage
+while still having a full scale TCP. This making lwIP suitable for use
+in embedded systems with tens of kilobytes of free RAM and room for
+around 40 kilobytes of code ROM.
+
+FEATURES
+
+  * IP (Internet Protocol) including packet forwarding over multiple network
+    interfaces
+  * ICMP (Internet Control Message Protocol) for network maintenance and debugging
+  * IGMP (Internet Group Management Protocol) for multicast traffic management
+  * UDP (User Datagram Protocol) including experimental UDP-lite extensions
+  * TCP (Transmission Control Protocol) with congestion control, RTT estimation
+    and fast recovery/fast retransmit
+  * Specialized raw/native API for enhanced performance
+  * Optional Berkeley-like socket API
+  * DNS (Domain names resolver)
+  * SNMP (Simple Network Management Protocol)
+  * DHCP (Dynamic Host Configuration Protocol)
+  * AUTOIP (for IPv4, conform with RFC 3927)
+  * PPP (Point-to-Point Protocol)
+  * ARP (Address Resolution Protocol) for Ethernet
+
+LICENSE
+
+lwIP is freely available under a BSD license.
+
+DEVELOPMENT
+
+lwIP has grown into an excellent TCP/IP stack for embedded devices,
+and developers using the stack often submit bug fixes, improvements,
+and additions to the stack to further increase its usefulness.
+
+Development of lwIP is hosted on Savannah, a central point for
+software development, maintenance and distribution. Everyone can
+help improve lwIP by use of Savannah's interface, CVS and the
+mailing list. A core team of developers will commit changes to the
+CVS source tree.
+
+The lwIP TCP/IP stack is maintained in the 'lwip' CVS module and
+contributions (such as platform ports) are in the 'contrib' module.
+
+See doc/savannah.txt for details on CVS server access for users and
+developers.
+
+Last night's CVS tar ball can be downloaded from:
+  http://savannah.gnu.org/cvs.backups/lwip.tar.gz [CHANGED - NEEDS FIXING]
+
+The current CVS trees are web-browsable:
+  http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/lwip/
+  http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/contrib/
+
+Submit patches and bugs via the lwIP project page:
+  http://savannah.nongnu.org/projects/lwip/
+
+
+DOCUMENTATION
+
+The original out-dated homepage of lwIP and Adam Dunkels' papers on
+lwIP are at the official lwIP home page:
+  http://www.sics.se/~adam/lwip/
+
+Self documentation of the source code is regularly extracted from the
+current CVS sources and is available from this web page:
+  http://www.nongnu.org/lwip/
+
+There is now a constantly growin wiki about lwIP at
+  http://lwip.scribblewiki.com/
+
+Also, there are mailing lists you can subscribe at
+  http://savannah.nongnu.org/mail/?group=lwip
+plus searchable archives:
+  http://lists.nongnu.org/archive/html/lwip-users/
+  http://lists.nongnu.org/archive/html/lwip-devel/
+
+Reading Adam's papers, the files in docs/, browsing the source code
+documentation and browsing the mailing list archives is a good way to
+become familiar with the design of lwIP.
+
+Adam Dunkels 
+Leon Woestenberg 
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/MCF5225x_ethernetif.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/MCF5225x_ethernetif.c
new file mode 100644
index 0000000..3e885f3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/MCF5225x_ethernetif.c
@@ -0,0 +1,888 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* Standard library includes. */
+#include 
+#include 
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+TaskHandle_t xEthIntTask;
+
+/* lwIP includes. */
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+#include "netif/etharp.h"
+
+/* Hardware includes. */
+#include "fec.h"
+
+/* Delay to wait for a DMA buffer to become available if one is not already
+available. */
+#define netifBUFFER_WAIT_ATTEMPTS					10
+#define netifBUFFER_WAIT_DELAY						(10 / portTICK_PERIOD_MS)
+
+/* Delay between polling the PHY to see if a link has been established. */
+#define netifLINK_DELAY								( 500 / portTICK_PERIOD_MS )
+
+/* Delay between looking for incoming packets.  In ideal world this would be
+infinite. */
+#define netifBLOCK_TIME_WAITING_FOR_INPUT			netifLINK_DELAY
+
+/* Name for the netif. */
+#define IFNAME0 'e'
+#define IFNAME1 'n'
+
+/* Hardware specific. */
+#define netifFIRST_FEC_VECTOR						23
+
+/*-----------------------------------------------------------*/
+
+/* The DMA descriptors.  This is a char array to allow us to align it correctly. */
+static unsigned char xFECTxDescriptors_unaligned[ ( configNUM_FEC_TX_BUFFERS * sizeof( FECBD ) ) + 16 ];
+static unsigned char xFECRxDescriptors_unaligned[ ( configNUM_FEC_RX_BUFFERS * sizeof( FECBD ) ) + 16 ];
+static FECBD *xFECTxDescriptors;
+static FECBD *xFECRxDescriptors;
+
+/* The DMA buffers.  These are char arrays to allow them to be alligned correctly. */
+static unsigned char ucFECTxBuffers[ ( configNUM_FEC_TX_BUFFERS * configFEC_BUFFER_SIZE ) + 16 ];
+static unsigned char ucFECRxBuffers[ ( configNUM_FEC_RX_BUFFERS * configFEC_BUFFER_SIZE ) + 16 ];
+static unsigned portBASE_TYPE uxNextRxBuffer = 0, uxNextTxBuffer = 0;
+
+/* Semaphore used by the FEC interrupt handler to wake the handler task. */
+static SemaphoreHandle_t xFecSemaphore;
+
+#pragma options align= packed
+struct ethernetif
+{
+  struct eth_addr *ethaddr;
+  /* Add whatever per-interface state that is needed here. */
+};
+
+/*-----------------------------------------------------------*/
+
+/* Standard lwIP netif handlers. */
+static void prvInitialiseFECBuffers( void );
+static void low_level_init( struct netif *netif );
+static err_t low_level_output(struct netif *netif, struct pbuf *p);
+static struct pbuf *low_level_input(struct netif *netif);
+static void ethernetif_input( void *pParams );
+
+/* Functions adapted from Freescale provided code. */
+static int fec_mii_write( int phy_addr, int reg_addr, int data );
+static int fec_mii_read( int phy_addr, int reg_addr, uint16* data );
+static uint8 fec_hash_address( const uint8* addr );
+static void fec_set_address( const uint8 *pa );
+static void fec_irq_enable( void );
+
+/*-----------------------------------------------------------*/
+
+/********************************************************************/
+/*
+ * Write a value to a PHY's MII register.
+ *
+ * Parameters:
+ *  ch          FEC channel
+ *  phy_addr    Address of the PHY.
+ *  reg_addr    Address of the register in the PHY.
+ *  data        Data to be written to the PHY register.
+ *
+ * Return Values:
+ *  0 on failure
+ *  1 on success.
+ *
+ * Please refer to your PHY manual for registers and their meanings.
+ * mii_write() polls for the FEC's MII interrupt event and clears it. 
+ * If after a suitable amount of time the event isn't triggered, a 
+ * value of 0 is returned.
+ */
+static int fec_mii_write( int phy_addr, int reg_addr, int data )
+{
+int timeout;
+uint32 eimr;
+
+	/* Clear the MII interrupt bit */
+	MCF_FEC_EIR = MCF_FEC_EIR_MII;
+
+	/* Mask the MII interrupt */
+	eimr = MCF_FEC_EIMR;
+	MCF_FEC_EIMR &= ~MCF_FEC_EIMR_MII;
+
+	/* Write to the MII Management Frame Register to kick-off the MII write */
+	MCF_FEC_MMFR = MCF_FEC_MMFR_ST_01 | MCF_FEC_MMFR_OP_WRITE | MCF_FEC_MMFR_PA(phy_addr) | MCF_FEC_MMFR_RA(reg_addr) | MCF_FEC_MMFR_TA_10 | MCF_FEC_MMFR_DATA( data );
+
+	/* Poll for the MII interrupt (interrupt should be masked) */
+	for (timeout = 0; timeout < MII_TIMEOUT; timeout++)
+	{
+		if (MCF_FEC_EIR & MCF_FEC_EIR_MII)
+		{
+			break;
+		}
+	}
+
+	if( timeout == MII_TIMEOUT )
+	{
+		return 0;
+	}
+
+	/* Clear the MII interrupt bit */
+	MCF_FEC_EIR = MCF_FEC_EIR_MII;
+
+	/* Restore the EIMR */
+	MCF_FEC_EIMR = eimr;
+
+	return 1;
+}
+
+/********************************************************************/
+/*
+ * Read a value from a PHY's MII register.
+ *
+ * Parameters:
+ *  ch          FEC channel
+ *  phy_addr    Address of the PHY.
+ *  reg_addr    Address of the register in the PHY.
+ *  data        Pointer to storage for the Data to be read
+ *              from the PHY register (passed by reference)
+ *
+ * Return Values:
+ *  0 on failure
+ *  1 on success.
+ *
+ * Please refer to your PHY manual for registers and their meanings.
+ * mii_read() polls for the FEC's MII interrupt event and clears it. 
+ * If after a suitable amount of time the event isn't triggered, a 
+ * value of 0 is returned.
+ */
+static int fec_mii_read( int phy_addr, int reg_addr, uint16* data )
+{
+int timeout;
+uint32 eimr;
+
+	/* Clear the MII interrupt bit */
+	MCF_FEC_EIR = MCF_FEC_EIR_MII;
+
+	/* Mask the MII interrupt */
+	eimr = MCF_FEC_EIMR;
+	MCF_FEC_EIMR &= ~MCF_FEC_EIMR_MII;
+
+	/* Write to the MII Management Frame Register to kick-off the MII read */
+	MCF_FEC_MMFR = MCF_FEC_MMFR_ST_01 | MCF_FEC_MMFR_OP_READ | MCF_FEC_MMFR_PA(phy_addr) | MCF_FEC_MMFR_RA(reg_addr) | MCF_FEC_MMFR_TA_10;
+
+	/* Poll for the MII interrupt (interrupt should be masked) */
+	for (timeout = 0; timeout < MII_TIMEOUT; timeout++)
+	{
+		if (MCF_FEC_EIR & MCF_FEC_EIR_MII)
+		{
+			break;
+		}
+	}
+
+	if(timeout == MII_TIMEOUT)
+	{
+		return 0;
+	}
+
+	/* Clear the MII interrupt bit */
+	MCF_FEC_EIR = MCF_FEC_EIR_MII;
+
+	/* Restore the EIMR */
+	MCF_FEC_EIMR = eimr;
+
+	*data = (uint16)(MCF_FEC_MMFR & 0x0000FFFF);
+
+	return 1;
+}
+
+
+/********************************************************************/
+/*
+ * Generate the hash table settings for the given address
+ *
+ * Parameters:
+ *  addr    48-bit (6 byte) Address to generate the hash for
+ *
+ * Return Value:
+ *  The 6 most significant bits of the 32-bit CRC result
+ */
+static uint8 fec_hash_address( const uint8* addr )
+{
+uint32 crc;
+uint8 byte;
+int i, j;
+
+	crc = 0xFFFFFFFF;
+	for(i=0; i<6; ++i)
+	{
+		byte = addr[i];
+		for(j=0; j<8; ++j)
+		{
+			if((byte & 0x01)^(crc & 0x01))
+			{
+				crc >>= 1;
+				crc = crc ^ 0xEDB88320;
+			}
+			else
+			{
+				crc >>= 1;
+			}
+
+			byte >>= 1;
+		}
+	}
+
+	return (uint8)(crc >> 26);
+}
+
+/********************************************************************/
+/*
+ * Set the Physical (Hardware) Address and the Individual Address
+ * Hash in the selected FEC
+ *
+ * Parameters:
+ *  ch  FEC channel
+ *  pa  Physical (Hardware) Address for the selected FEC
+ */
+static void fec_set_address( const uint8 *pa )
+{
+	uint8 crc;
+
+	/*
+	* Set the Physical Address
+	*/
+	MCF_FEC_PALR = (uint32)((pa[0]<<24) | (pa[1]<<16) | (pa[2]<<8) | pa[3]);
+	MCF_FEC_PAUR = (uint32)((pa[4]<<24) | (pa[5]<<16));
+
+	/*
+	* Calculate and set the hash for given Physical Address
+	* in the  Individual Address Hash registers
+	*/
+	crc = fec_hash_address(pa);
+	if(crc >= 32)
+	{
+		MCF_FEC_IAUR |= (uint32)(1 << (crc - 32));
+	}
+	else
+	{
+		MCF_FEC_IALR |= (uint32)(1 << crc);
+	}
+}
+
+
+/********************************************************************/
+/*
+ * Enable interrupts on the selected FEC
+ *
+ */
+static void fec_irq_enable( void )
+{
+int fec_vbase;
+
+#if INTC_LVL_FEC > configMAX_SYSCALL_INTERRUPT_PRIORITY
+	#error INTC_LVL_FEC must be less than or equal to configMAX_SYSCALL_INTERRUPT_PRIORITY
+#endif
+
+	fec_vbase = 64 + netifFIRST_FEC_VECTOR;
+    
+	/* Enable FEC interrupts to the ColdFire core 
+	 * Setup each ICR with a unique interrupt level combination */
+	fec_vbase -= 64;
+
+	/* FEC Rx Frame */
+	MCF_INTC0_ICR(fec_vbase+4)  = MCF_INTC_ICR_IL(INTC_LVL_FEC);
+
+	/* FEC Rx Buffer */                              
+	MCF_INTC0_ICR(fec_vbase+5)  = MCF_INTC_ICR_IL(INTC_LVL_FEC);
+
+	/* FEC FIFO Underrun */                              
+	MCF_INTC0_ICR(fec_vbase+2)  = MCF_INTC_ICR_IL(INTC_LVL_FEC+1);
+
+	/* FEC Collision Retry Limit */                              
+	MCF_INTC0_ICR(fec_vbase+3)  = MCF_INTC_ICR_IL(INTC_LVL_FEC+1);
+
+	/* FEC Late Collision */                                 
+	MCF_INTC0_ICR(fec_vbase+7)  = MCF_INTC_ICR_IL(INTC_LVL_FEC+1);
+
+	/* FEC Heartbeat Error */                                
+	MCF_INTC0_ICR(fec_vbase+8)  = MCF_INTC_ICR_IL(INTC_LVL_FEC+1);
+
+	/* FEC Bus Error */                              
+	MCF_INTC0_ICR(fec_vbase+10) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1);
+
+	/* FEC Babbling Transmit */                              
+	MCF_INTC0_ICR(fec_vbase+11) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1);
+
+	/* FEC Babbling Receive */                               
+	MCF_INTC0_ICR(fec_vbase+12) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1);
+                                 
+	/* Enable the FEC interrupts in the mask register */    
+	MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK33 | MCF_INTC_IMRH_INT_MASK34 | MCF_INTC_IMRH_INT_MASK35 );
+	MCF_INTC0_IMRL &= ~( MCF_INTC_IMRL_INT_MASK25 | MCF_INTC_IMRL_INT_MASK26 | MCF_INTC_IMRL_INT_MASK27 | MCF_INTC_IMRL_INT_MASK28 | MCF_INTC_IMRL_INT_MASK29 | MCF_INTC_IMRL_INT_MASK30 | MCF_INTC_IMRL_INT_MASK31 | MCF_INTC_IMRL_MASKALL );
+
+    /* Clear any pending FEC interrupt events */
+    MCF_FEC_EIR = MCF_FEC_EIR_CLEAR_ALL;
+
+    /* Unmask all FEC interrupts */
+    MCF_FEC_EIMR = MCF_FEC_EIMR_UNMASK_ALL;
+}
+
+/**
+ * In this function, the hardware should be initialized.
+ * Called from ethernetif_init().
+ *
+ * @param netif the already initialized lwip network interface structure
+ *        for this ethernetif
+ */
+static void low_level_init( struct netif *netif )
+{
+unsigned short usData;
+const unsigned char ucMACAddress[6] = 
+{
+	configMAC_0, configMAC_1,configMAC_2,configMAC_3,configMAC_4,configMAC_5
+};
+
+	prvInitialiseFECBuffers();
+	vSemaphoreCreateBinary( xFecSemaphore );
+	
+	for( usData = 0; usData < 6; usData++ )
+	{
+		netif->hwaddr[ usData ] = ucMACAddress[ usData ];
+	}
+
+	/* Set the Reset bit and clear the Enable bit */
+	MCF_FEC_ECR = MCF_FEC_ECR_RESET;
+
+	/* Wait at least 8 clock cycles */
+	for( usData = 0; usData < 10; usData++ )
+	{
+		asm( "NOP" );
+	}
+
+	/* Set MII speed to 2.5MHz. */
+	MCF_FEC_MSCR = MCF_FEC_MSCR_MII_SPEED( ( ( configCPU_CLOCK_HZ / 1000000 ) / 5 ) + 1 );
+
+	/*
+	 * Make sure the external interface signals are enabled
+	 */
+	MCF_GPIO_PNQPAR = MCF_GPIO_PNQPAR_IRQ3_FEC_MDIO	| MCF_GPIO_PNQPAR_IRQ5_FEC_MDC;
+
+
+    MCF_GPIO_PTIPAR = MCF_GPIO_PTIPAR_FEC_COL_FEC_COL			
+					| MCF_GPIO_PTIPAR_FEC_CRS_FEC_CRS			
+					| MCF_GPIO_PTIPAR_FEC_RXCLK_FEC_RXCLK		
+					| MCF_GPIO_PTIPAR_FEC_RXD0_FEC_RXD0			
+					| MCF_GPIO_PTIPAR_FEC_RXD1_FEC_RXD1			
+					| MCF_GPIO_PTIPAR_FEC_RXD2_FEC_RXD2			
+					| MCF_GPIO_PTIPAR_FEC_RXD3_FEC_RXD3			
+					| MCF_GPIO_PTIPAR_FEC_RXDV_FEC_RXDV;		
+
+	MCF_GPIO_PTJPAR = MCF_GPIO_PTJPAR_FEC_RXER_FEC_RXER			
+					| MCF_GPIO_PTJPAR_FEC_TXCLK_FEC_TXCLK		
+					| MCF_GPIO_PTJPAR_FEC_TXD0_FEC_TXD0			
+					| MCF_GPIO_PTJPAR_FEC_TXD1_FEC_TXD1			
+					| MCF_GPIO_PTJPAR_FEC_TXD2_FEC_TXD2			
+					| MCF_GPIO_PTJPAR_FEC_TXD3_FEC_TXD3			
+					| MCF_GPIO_PTJPAR_FEC_TXEN_FEC_TXEN			
+					| MCF_GPIO_PTJPAR_FEC_TXER_FEC_TXER;		
+
+
+	/* Can we talk to the PHY? */
+	do
+	{
+		vTaskDelay( netifLINK_DELAY );
+		usData = 0;
+		fec_mii_read( configPHY_ADDRESS, PHY_PHYIDR1, &usData );
+
+	} while( ( usData == 0xffff ) || ( usData == 0 ) );
+
+	/* Start auto negotiate. */
+	fec_mii_write( configPHY_ADDRESS, PHY_BMCR, ( PHY_BMCR_AN_RESTART | PHY_BMCR_AN_ENABLE ) );
+
+	/* Wait for auto negotiate to complete. */
+	do
+	{
+		vTaskDelay( netifLINK_DELAY );
+		fec_mii_read( configPHY_ADDRESS, PHY_BMSR, &usData );
+
+	} while( !( usData & PHY_BMSR_AN_COMPLETE ) );
+
+	/* When we get here we have a link - find out what has been negotiated. */
+	fec_mii_read( configPHY_ADDRESS, PHY_ANLPAR, &usData );
+	
+	if( ( usData & PHY_ANLPAR_100BTX_FDX ) || ( usData & PHY_ANLPAR_100BTX ) )
+	{
+		/* Speed is 100. */
+	}
+	else
+	{
+		/* Speed is 10. */
+	}
+
+	if( ( usData & PHY_ANLPAR_100BTX_FDX ) || ( usData & PHY_ANLPAR_10BTX_FDX ) )
+	{
+		/* Full duplex. */
+		MCF_FEC_RCR &= (uint32)~MCF_FEC_RCR_DRT;
+		MCF_FEC_TCR |= MCF_FEC_TCR_FDEN;
+	}
+	else
+	{
+		MCF_FEC_RCR |= MCF_FEC_RCR_DRT;
+		MCF_FEC_TCR &= (uint32)~MCF_FEC_TCR_FDEN;
+	}
+	
+	/* Clear the Individual and Group Address Hash registers */
+	MCF_FEC_IALR = 0;
+	MCF_FEC_IAUR = 0;
+	MCF_FEC_GALR = 0;
+	MCF_FEC_GAUR = 0;
+
+	/* Set the Physical Address for the selected FEC */
+	fec_set_address( ucMACAddress );
+
+	/* Set Rx Buffer Size */
+	MCF_FEC_EMRBR = (uint16)configFEC_BUFFER_SIZE;
+
+	/* Point to the start of the circular Rx buffer descriptor queue */
+	MCF_FEC_ERDSR = ( volatile unsigned long ) &( xFECRxDescriptors[ 0 ] );
+
+	/* Point to the start of the circular Tx buffer descriptor queue */
+	MCF_FEC_ETSDR = ( volatile unsigned long ) &( xFECTxDescriptors[ 0 ] );
+
+	/* Mask all FEC interrupts */
+	MCF_FEC_EIMR = MCF_FEC_EIMR_MASK_ALL;
+
+	/* Clear all FEC interrupt events */
+	MCF_FEC_EIR = MCF_FEC_EIR_CLEAR_ALL;
+
+	/* Initialize the Receive Control Register */
+	MCF_FEC_RCR = MCF_FEC_RCR_MAX_FL(ETH_MAX_FRM) | MCF_FEC_RCR_FCE;
+
+	MCF_FEC_RCR |= MCF_FEC_RCR_MII_MODE;
+
+	#if( configUSE_PROMISCUOUS_MODE == 1 )
+	{
+		MCF_FEC_RCR |= MCF_FEC_RCR_PROM;
+	}
+	#endif
+
+	/* Create the task that handles the EMAC. */
+	xTaskCreate( ethernetif_input, "ETH_INT", configETHERNET_INPUT_TASK_STACK_SIZE, (void *)netif, configETHERNET_INPUT_TASK_PRIORITY, &xEthIntTask );
+	
+	fec_irq_enable();
+	MCF_FEC_ECR = MCF_FEC_ECR_ETHER_EN;
+	MCF_FEC_RDAR = MCF_FEC_RDAR_R_DES_ACTIVE;	
+}
+
+/**
+ * This function should do the actual transmission of the packet. The packet is
+ * contained in the pbuf that is passed to the function. This pbuf
+ * might be chained.
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)
+ * @return ERR_OK if the packet could be sent
+ *         an err_t value if the packet couldn't be sent
+ *
+ * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to
+ *       strange results. You might consider waiting for space in the DMA queue
+ *       to become availale since the stack doesn't retry to send a packet
+ *       dropped because of memory failure (except for the TCP timers).
+ */
+static err_t low_level_output(struct netif *netif, struct pbuf *p)
+{
+struct pbuf *q;
+u32_t l = 0;
+unsigned char *pcTxData = NULL;
+portBASE_TYPE i;
+
+	( void ) netif;
+
+	#if ETH_PAD_SIZE
+	  pbuf_header(p, -ETH_PAD_SIZE);			/* drop the padding word */
+	#endif
+
+	/* Get a DMA buffer into which we can write the data to send. */
+	for( i = 0; i < netifBUFFER_WAIT_ATTEMPTS; i++ )
+	{
+		if( xFECTxDescriptors[ uxNextTxBuffer ].status & TX_BD_R )
+		{
+			/* Wait for the buffer to become available. */
+			vTaskDelay( netifBUFFER_WAIT_DELAY );
+		}
+		else
+		{
+			pcTxData = xFECTxDescriptors[ uxNextTxBuffer ].data;
+			break;
+		}
+	}
+
+	if( pcTxData == NULL ) 
+	{
+		/* For break point only. */
+		portNOP();
+
+		return ERR_BUF;
+	}
+	else 
+	{
+		for( q = p; q != NULL; q = q->next ) 
+		{
+			/* Send the data from the pbuf to the interface, one pbuf at a
+			time. The size of the data in each pbuf is kept in the ->len
+			variable. */
+			memcpy( &pcTxData[l], (u8_t*)q->payload, q->len );
+			l += q->len;
+		}
+	}
+
+	/* Setup the buffer descriptor for transmission */
+	xFECTxDescriptors[ uxNextTxBuffer ].length = l;//nbuf->length + ETH_HDR_LEN;
+	xFECTxDescriptors[ uxNextTxBuffer ].status |= (TX_BD_R | TX_BD_L);
+
+	/* Continue the Tx DMA task (in case it was waiting for a new TxBD) */
+	MCF_FEC_TDAR = MCF_FEC_TDAR_X_DES_ACTIVE;
+
+	uxNextTxBuffer++;
+	if( uxNextTxBuffer >= configNUM_FEC_TX_BUFFERS )
+	{
+		uxNextTxBuffer = 0;
+	}
+
+	#if ETH_PAD_SIZE
+		pbuf_header(p, ETH_PAD_SIZE);			/* reclaim the padding word */
+	#endif
+
+	LINK_STATS_INC(link.xmit);
+
+	return ERR_OK;
+}
+
+/**
+ * Should allocate a pbuf and transfer the bytes of the incoming
+ * packet from the interface into the pbuf.
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ * @return a pbuf filled with the received packet (including MAC header)
+ *         NULL on memory error
+ */
+static struct pbuf *low_level_input(struct netif *netif)
+{
+struct pbuf *p, *q;
+u16_t len, l;
+
+	( void ) netif;
+
+	l = 0;
+	p = NULL;
+
+	/* Obtain the size of the packet and put it into the "len" variable. */
+	len = xFECRxDescriptors[ uxNextRxBuffer ].length;
+
+	if( ( len != 0 ) && ( ( xFECRxDescriptors[ uxNextRxBuffer ].status & RX_BD_E ) == 0 ) )
+	{
+		#if ETH_PAD_SIZE
+			len += ETH_PAD_SIZE;						/* allow room for Ethernet padding */
+		#endif
+
+		/* We allocate a pbuf chain of pbufs from the pool. */
+		p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
+
+		if (p != NULL) 
+		{
+
+			#if ETH_PAD_SIZE
+					pbuf_header(p, -ETH_PAD_SIZE);			/* drop the padding word */
+			#endif
+
+			/* We iterate over the pbuf chain until we have read the entire
+			 * packet into the pbuf. */
+			for(q = p; q != NULL; q = q->next) 
+			{
+				/* Read enough bytes to fill this pbuf in the chain. The
+				 * available data in the pbuf is given by the q->len
+				 * variable. */
+				memcpy((u8_t*)q->payload, &(xFECRxDescriptors[ uxNextRxBuffer ].data[l]), q->len);
+				l = l + q->len;
+			}
+
+
+			#if ETH_PAD_SIZE
+				pbuf_header(p, ETH_PAD_SIZE);			/* reclaim the padding word */
+			#endif
+
+			LINK_STATS_INC(link.recv);
+
+		} 
+		else 
+		{
+
+			LINK_STATS_INC(link.memerr);
+			LINK_STATS_INC(link.drop);
+
+		} /* End else */
+		
+		
+		/* Free the descriptor. */
+		xFECRxDescriptors[ uxNextRxBuffer ].status |= RX_BD_E;
+		MCF_FEC_RDAR = MCF_FEC_RDAR_R_DES_ACTIVE;
+		
+		uxNextRxBuffer++;
+		if( uxNextRxBuffer >= configNUM_FEC_RX_BUFFERS )
+		{
+			uxNextRxBuffer = 0;
+		}		
+		
+	} /* End if */
+
+	return p;
+}
+
+/**
+ * This function should be called when a packet is ready to be read
+ * from the interface. It uses the function low_level_input() that
+ * should handle the actual reception of bytes from the network
+ * interface.Then the type of the received packet is determined and
+ * the appropriate input function is called.
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ */
+
+static void ethernetif_input( void *pParams )
+{
+struct netif *netif;
+struct ethernetif *ethernetif;
+struct eth_hdr *ethhdr;
+struct pbuf *p;
+
+	netif = (struct netif*) pParams;
+	ethernetif = netif->state;
+
+	for( ;; )
+	{
+		do
+		{
+
+			/* move received packet into a new pbuf */
+			p = low_level_input( netif );
+
+			if( p == NULL )
+			{
+				/* No packet could be read.  Wait a for an interrupt to tell us
+				there is more data available. */
+				xSemaphoreTake( xFecSemaphore, netifBLOCK_TIME_WAITING_FOR_INPUT );
+			}
+
+		} while( p == NULL );
+
+		/* points to packet payload, which starts with an Ethernet header */
+		ethhdr = p->payload;
+
+		switch (htons(ethhdr->type)) {
+			/* IP or ARP packet? */
+
+		case ETHTYPE_IP:
+
+			pbuf_header( p, (s16_t)-sizeof(struct eth_hdr) );
+
+			/* full packet send to tcpip_thread to process */
+			if (netif->input(p, netif) != ERR_OK)
+			{
+				LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n"));
+				pbuf_free(p);
+				p = NULL;
+			}
+			break;
+
+		case ETHTYPE_ARP:
+
+			#if ETHARP_TRUST_IP_MAC
+				etharp_ip_input(netif, p);
+			#endif
+
+			etharp_arp_input(netif, ethernetif->ethaddr, p);
+			break;
+
+		default:
+			pbuf_free(p);
+			p = NULL;
+			break;
+		}
+	}
+}
+
+/**
+ * Should be called at the beginning of the program to set up the
+ * network interface. It calls the function low_level_init() to do the
+ * actual setup of the hardware.
+ *
+ * This function should be passed as a parameter to netif_add().
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ * @return ERR_OK if the loopif is initialized
+ *         ERR_MEM if private data couldn't be allocated
+ *         any other err_t on error
+ */
+err_t ethernetif_init(struct netif *netif)
+{
+	struct ethernetif *ethernetif;
+
+	LWIP_ASSERT("netif != NULL", (netif != NULL));
+
+	ethernetif = mem_malloc(sizeof(struct ethernetif));
+
+	if (ethernetif == NULL)
+	{
+		LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n"));
+		return ERR_MEM;
+	}
+
+	#if LWIP_NETIF_HOSTNAME
+	/* Initialize interface hostname */
+	netif->hostname = "lwip";
+	#endif /* LWIP_NETIF_HOSTNAME */
+
+	/*
+	* Initialize the snmp variables and counters inside the struct netif.
+	* The last argument should be replaced with your link speed, in units
+	* of bits per second.
+	*/
+	NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 100);
+
+	netif->state = ethernetif;
+	netif->name[0] = IFNAME0;
+	netif->name[1] = IFNAME1;
+
+	/* We directly use etharp_output() here to save a function call.
+	* You can instead declare your own function an call etharp_output()
+	* from it if you have to do some checks before sending (e.g. if link
+	* is available...)
+	*/
+	netif->output = etharp_output;
+	netif->linkoutput = low_level_output;
+
+	ethernetif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]);
+
+	low_level_init(netif);
+
+	return ERR_OK;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseFECBuffers( void )
+{
+unsigned portBASE_TYPE ux;
+unsigned char *pcBufPointer;
+
+	pcBufPointer = &( xFECTxDescriptors_unaligned[ 0 ] );
+	while( ( ( unsigned long ) pcBufPointer & 0x0fUL ) != 0 )
+	{
+		pcBufPointer++;
+	}
+	
+	xFECTxDescriptors = ( FECBD * ) pcBufPointer;
+	
+	pcBufPointer = &( xFECRxDescriptors_unaligned[ 0 ] );
+	while( ( ( unsigned long ) pcBufPointer & 0x0fUL ) != 0 )
+	{
+		pcBufPointer++;
+	}
+	
+	xFECRxDescriptors = ( FECBD * ) pcBufPointer;
+
+
+	/* Setup the buffers and descriptors. */
+	pcBufPointer = &( ucFECTxBuffers[ 0 ] );
+	while( ( ( unsigned long ) pcBufPointer & 0x0fUL ) != 0 )
+	{
+		pcBufPointer++;
+	}
+
+	for( ux = 0; ux < configNUM_FEC_TX_BUFFERS; ux++ )
+	{
+		xFECTxDescriptors[ ux ].status = TX_BD_TC;
+		xFECTxDescriptors[ ux ].data = pcBufPointer;
+		pcBufPointer += configFEC_BUFFER_SIZE;
+		xFECTxDescriptors[ ux ].length = 0;
+	}
+
+	pcBufPointer = &( ucFECRxBuffers[ 0 ] );
+	while( ( ( unsigned long ) pcBufPointer & 0x0fUL ) != 0 )
+	{
+		pcBufPointer++;
+	}
+	
+	for( ux = 0; ux < configNUM_FEC_RX_BUFFERS; ux++ )
+	{
+	    xFECRxDescriptors[ ux ].status = RX_BD_E;
+	    xFECRxDescriptors[ ux ].length = configFEC_BUFFER_SIZE;
+	    xFECRxDescriptors[ ux ].data = pcBufPointer;
+	    pcBufPointer += configFEC_BUFFER_SIZE;
+	}
+
+	/* Set the wrap bit in the last descriptors to form a ring. */
+	xFECTxDescriptors[ configNUM_FEC_TX_BUFFERS - 1 ].status |= TX_BD_W;
+	xFECRxDescriptors[ configNUM_FEC_RX_BUFFERS - 1 ].status |= RX_BD_W;
+
+	uxNextRxBuffer = 0;
+	uxNextTxBuffer = 0;
+}
+/*-----------------------------------------------------------*/
+
+__declspec(interrupt:0) void vFECISRHandler( void )
+{
+unsigned long ulEvent;
+portBASE_TYPE xHighPriorityTaskWoken = pdFALSE;
+   
+	ulEvent = MCF_FEC_EIR & MCF_FEC_EIMR;
+	MCF_FEC_EIR = ulEvent;
+
+	if( ( ulEvent & MCF_FEC_EIR_RXB ) || ( ulEvent & MCF_FEC_EIR_RXF ) )
+	{
+		/* A packet has been received.  Wake the handler task. */
+		xSemaphoreGiveFromISR( xFecSemaphore, &xHighPriorityTaskWoken );
+	}
+
+	if (ulEvent & ( MCF_FEC_EIR_UN | MCF_FEC_EIR_RL | MCF_FEC_EIR_LC | MCF_FEC_EIR_EBERR | MCF_FEC_EIR_BABT | MCF_FEC_EIR_BABR | MCF_FEC_EIR_HBERR ) )
+	{
+		/* Sledge hammer error handling. */
+		prvInitialiseFECBuffers();
+		MCF_FEC_RDAR = MCF_FEC_RDAR_R_DES_ACTIVE;
+	}
+
+	portEND_SWITCHING_ISR( xHighPriorityTaskWoken );
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/__sys_arch.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/__sys_arch.c
new file mode 100644
index 0000000..18e3955
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/__sys_arch.c
@@ -0,0 +1,571 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Modifications Copyright (c) 2006 Christian Walter 
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ * Modifcations: Christian Walter 
+ *
+ * $Id: sys_arch.c,v 1.1 2008/08/05 00:10:49 b06862 Exp $
+ */
+
+/* ------------------------ System includes ------------------------------- */
+
+#include "stdlib.h"
+
+/* ------------------------ FreeRTOS includes ----------------------------- */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+
+/* ------------------------ lwIP includes --------------------------------- */
+#include "lwip/debug.h"
+#include "lwip/def.h"
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+#include "lwip/sio.h"
+#include "lwip/stats.h"
+
+/* ------------------------ Project includes ------------------------------ */
+
+/* ------------------------ Defines --------------------------------------- */
+/* This is the number of threads that can be started with sys_thead_new() */
+#define SYS_MBOX_SIZE               ( 16 )
+#define MS_TO_TICKS( ms )           \
+    ( TickType_t )( ( TickType_t ) ( ms ) / portTICK_PERIOD_MS )
+#define TICKS_TO_MS( ticks )        \
+    ( unsigned long )( ( TickType_t ) ( ticks ) * portTICK_PERIOD_MS )
+#define THREAD_STACK_SIZE           ( 256 /*FSL:1024*/ )
+#define THREAD_NAME                 "lwIP"
+
+#define THREAD_INIT( tcb ) \
+    do { \
+        tcb->next = NULL; \
+        tcb->pid = ( TaskHandle_t )0; \
+        tcb->timeouts.next = NULL; \
+    } while( 0 )
+
+/* ------------------------ Type definitions ------------------------------ */
+typedef struct sys_tcb
+{
+    struct sys_tcb *next;
+    struct sys_timeouts timeouts;
+    TaskHandle_t     pid;
+} sys_tcb_t;
+
+/* ------------------------ Prototypes ------------------------------------ */
+
+/* ------------------------ Static functions ------------------------------ */
+sys_tcb_t      *sys_thread_current( void );
+
+/* ------------------------ Static variables ------------------------------ */
+static sys_tcb_t *tasks = NULL;
+
+/* ------------------------ Start implementation -------------------------- */
+void
+sys_init( void )
+{
+    LWIP_ASSERT( "sys_init: not called first", tasks == NULL );
+    tasks = NULL;
+}
+
+/*
+ * This optional function does a "fast" critical region protection and returns
+ * the previous protection level. This function is only called during very short
+ * critical regions. An embedded system which supports ISR-based drivers might
+ * want to implement this function by disabling interrupts. Task-based systems
+ * might want to implement this by using a mutex or disabling tasking. This
+ * function should support recursive calls from the same task or interrupt. In
+ * other words, sys_arch_protect() could be called while already protected. In
+ * that case the return value indicates that it is already protected.
+ *
+ * sys_arch_protect() is only required if your port is supporting an operating
+ * system.
+ */
+sys_prot_t
+sys_arch_protect( void )
+{
+    vPortEnterCritical(  );
+    return 1;
+}
+
+/*
+ * This optional function does a "fast" set of critical region protection to the
+ * value specified by pval. See the documentation for sys_arch_protect() for
+ * more information. This function is only required if your port is supporting
+ * an operating system.
+ */
+void
+sys_arch_unprotect( sys_prot_t pval )
+{
+    ( void )pval;
+    vPortExitCritical(  );
+}
+
+/*
+ * Prints an assertion messages and aborts execution.
+ */
+void
+sys_assert( const char *msg )
+{
+	/*FSL:only needed for debugging
+	printf(msg);
+	printf("\n\r");
+	*/
+    vPortEnterCritical(  );
+    for(;;)
+    ;
+}
+
+void
+sys_debug( const char *const fmt, ... )
+{
+	/*FSL: same implementation as printf*/
+
+    /*FSL: removed due to lack of space*/
+    //printf(fmt);
+}
+
+/* ------------------------ Start implementation ( Threads ) -------------- */
+
+/*
+ * Starts a new thread with priority "prio" that will begin its execution in the
+ * function "thread()". The "arg" argument will be passed as an argument to the
+ * thread() function. The argument "ssize" is the requested stack size for the
+ * new thread. The id of the new thread is returned. Both the id and the
+ * priority are system dependent.
+ */
+sys_thread_t
+sys_thread_new(char *name, void ( *thread ) ( void *arg ), void *arg, int /*size_t*/ stacksize, int prio )
+{
+    sys_thread_t    thread_hdl = SYS_THREAD_NULL;
+    int             i;
+    sys_tcb_t      *p;
+
+    /* We disable the FreeRTOS scheduler because it might be the case that the new
+     * tasks gets scheduled inside the xTaskCreate function. To prevent this we
+     * disable the scheduling. Note that this can happen although we have interrupts
+     * disabled because xTaskCreate contains a call to taskYIELD( ).
+     */
+    vPortEnterCritical(  );
+
+    p = tasks;
+    i = 0;
+    /* We are called the first time. Initialize it. */
+    if( p == NULL )
+    {
+        p = (sys_tcb_t *)pvPortMalloc( sizeof( sys_tcb_t ) );
+        if( p != NULL )
+        {
+            tasks = p;
+        }
+    }
+    else
+    {
+        /* First task already counter. */
+        i++;
+        /* Cycle to the end of the list. */
+        while( p->next != NULL )
+        {
+            i++;
+            p = p->next;
+        }
+        p->next = (sys_tcb_t *)pvPortMalloc( sizeof( sys_tcb_t ) );
+        p = p->next;
+    }
+
+    if( p != NULL )
+    {
+        /* Memory allocated. Initialize the data structure. */
+        THREAD_INIT( p );
+
+        /* Now q points to a free element in the list. */
+        if( xTaskCreate( thread, name, stacksize, arg, prio, &p->pid ) == pdPASS )
+        {
+            thread_hdl = p;
+        }
+        else
+        {
+            vPortFree( p );
+        }
+    }
+
+    vPortExitCritical(  );
+    return thread_hdl;
+}
+
+void
+sys_arch_thread_remove( sys_thread_t hdl )
+{
+    sys_tcb_t      *current = tasks, *prev;
+    sys_tcb_t      *toremove = hdl;
+    TaskHandle_t     pid = ( TaskHandle_t ) 0;
+
+    LWIP_ASSERT( "sys_arch_thread_remove: assertion hdl != NULL failed!", hdl != NULL );
+
+    /* If we have to remove the first task we must update the global "tasks"
+     * variable. */
+    vPortEnterCritical(  );
+    if( hdl != NULL )
+    {
+        prev = NULL;
+        while( ( current != NULL ) && ( current != toremove ) )
+        {
+            prev = current;
+            current = current->next;
+        }
+        /* Found it. */
+        if( current == toremove )
+        {
+            /* Not the first entry in the list. */
+            if( prev != NULL )
+            {
+                prev->next = toremove->next;
+            }
+            else
+            {
+                tasks = toremove->next;
+            }
+            LWIP_ASSERT( "sys_arch_thread_remove: can't remove thread with timeouts!",
+                         toremove->timeouts.next == NULL );
+            pid = toremove->pid;
+            THREAD_INIT( toremove );
+            vPortFree( toremove );
+        }
+    }
+    /* We are done with accessing the shared datastructure. Release the
+     * resources.
+     */
+    vPortExitCritical(  );
+    if( pid != ( TaskHandle_t ) 0 )
+    {
+        vTaskDelete( pid );
+        /* not reached. */
+    }
+}
+
+/*
+ * Returns the thread control block for the currently active task. In case
+ * of an error the functions returns NULL.
+ */
+sys_thread_t
+sys_arch_thread_current( void )
+{
+    sys_tcb_t      *p = tasks;
+    TaskHandle_t     pid = xTaskGetCurrentTaskHandle(  );
+
+    vPortEnterCritical(  );
+    while( ( p != NULL ) && ( p->pid != pid ) )
+    {
+        p = p->next;
+    }
+    vPortExitCritical(  );
+    return p;
+}
+
+/*
+ * Returns a pointer to the per-thread sys_timeouts structure. In lwIP,
+ * each thread has a list of timeouts which is represented as a linked
+ * list of sys_timeout structures. The sys_timeouts structure holds a
+ * pointer to a linked list of timeouts. This function is called by
+ * the lwIP timeout scheduler and must not return a NULL value.
+ *
+ * In a single threaded sys_arch implementation, this function will
+ * simply return a pointer to a global sys_timeouts variable stored in
+ * the sys_arch module.
+ */
+struct sys_timeouts *
+sys_arch_timeouts( void )
+{
+    sys_tcb_t      *ptask;
+
+    ptask = sys_arch_thread_current(  );
+    LWIP_ASSERT( "sys_arch_timeouts: ptask != NULL", ptask != NULL );
+    return ptask != NULL ? &( ptask->timeouts ) : NULL;
+}
+
+/* ------------------------ Start implementation ( Semaphores ) ----------- */
+
+/* Creates and returns a new semaphore. The "count" argument specifies
+ * the initial state of the semaphore.
+ */
+sys_sem_t
+sys_sem_new( u8_t count )
+{
+    SemaphoreHandle_t xSemaphore;
+
+    vSemaphoreCreateBinary( xSemaphore );
+    if( xSemaphore != SYS_SEM_NULL )
+    {
+        if( count == 0 )
+        {
+            xSemaphoreTake( xSemaphore, 1 );
+        }
+#if SYS_STATS == 1
+        vPortEnterCritical(  );
+        lwip_stats.sys.sem.used++;
+        if( lwip_stats.sys.sem.used > lwip_stats.sys.sem.max )
+        {
+            lwip_stats.sys.sem.max = lwip_stats.sys.sem.used;
+        }
+        vPortExitCritical(  );
+#endif
+    }
+    else
+    {
+        LWIP_ASSERT( "sys_sem_new: xSemaphore == SYS_SEM_NULL", xSemaphore != SYS_SEM_NULL );
+    }
+
+    return xSemaphore;
+}
+
+/* Deallocates a semaphore */
+void
+sys_sem_free( sys_sem_t sem )
+{
+    LWIP_ASSERT( "sys_sem_free: sem != SYS_SEM_NULL", sem != SYS_SEM_NULL );
+    if( sem != SYS_SEM_NULL )
+    {
+#if SYS_STATS == 1
+        vPortEnterCritical(  );
+        lwip_stats.sys.sem.used--;
+        vPortExitCritical(  );
+#endif
+        vQueueDelete( sem );
+    }
+}
+
+/* Signals a semaphore */
+void
+sys_sem_signal( sys_sem_t sem )
+{
+    LWIP_ASSERT( "sys_sem_signal: sem != SYS_SEM_NULL", sem != SYS_SEM_NULL );
+    xSemaphoreGive( sem );
+}
+
+/*
+ * Blocks the thread while waiting for the semaphore to be
+ * signaled. If the "timeout" argument is non-zero, the thread should
+ * only be blocked for the specified time (measured in
+ * milliseconds).
+ *
+ * If the timeout argument is non-zero, the return value is the number of
+ * milliseconds spent waiting for the semaphore to be signaled. If the
+ * semaphore wasn't signaled within the specified time, the return value is
+ * SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
+ * (i.e., it was already signaled), the function may return zero.
+ *
+ * Notice that lwIP implements a function with a similar name,
+ * sys_sem_wait(), that uses the sys_arch_sem_wait() function.
+ */
+u32_t
+sys_arch_sem_wait( sys_sem_t sem, u32_t timeout )
+{
+    portBASE_TYPE   xStatus;
+    TickType_t    xTicksStart, xTicksEnd, xTicksElapsed;
+    u32_t           timespent;
+
+    LWIP_ASSERT( "sys_arch_sem_wait: sem != SYS_SEM_NULL", sem != SYS_SEM_NULL );
+    xTicksStart = xTaskGetTickCount(  );
+    if( timeout == 0 )
+    {
+        do
+        {
+            xStatus = xSemaphoreTake( sem, MS_TO_TICKS( 100 ) );
+        }
+        while( xStatus != pdTRUE );
+    }
+    else
+    {
+        xStatus = xSemaphoreTake( sem, MS_TO_TICKS( timeout ) );
+    }
+
+    /* Semaphore was signaled. */
+    if( xStatus == pdTRUE )
+    {
+        xTicksEnd = xTaskGetTickCount(  );
+        xTicksElapsed = xTicksEnd - xTicksStart;
+        timespent = TICKS_TO_MS( xTicksElapsed );
+    }
+    else
+    {
+        timespent = SYS_ARCH_TIMEOUT;
+    }
+    return timespent;
+}
+
+
+/* ------------------------ Start implementation ( Mailboxes ) ------------ */
+
+/* Creates an empty mailbox. */
+sys_mbox_t
+sys_mbox_new( /*paolo:void*/int size )
+{
+    QueueHandle_t    mbox;
+
+    mbox = xQueueCreate( SYS_MBOX_SIZE/*size*/, sizeof( void * ) );
+    if( mbox != SYS_MBOX_NULL )
+    {
+#if SYS_STATS == 1
+        vPortEnterCritical(  );
+        lwip_stats.sys.mbox.used++;
+        if( lwip_stats.sys.mbox.used > lwip_stats.sys.mbox.max )
+        {
+            lwip_stats.sys.mbox.max = lwip_stats.sys.mbox.used;
+        }
+        vPortExitCritical(  );
+#endif
+    }
+    return mbox;
+}
+
+/*
+  Deallocates a mailbox. If there are messages still present in the
+  mailbox when the mailbox is deallocated, it is an indication of a
+  programming error in lwIP and the developer should be notified.
+*/
+void
+sys_mbox_free( sys_mbox_t mbox )
+{
+    void           *msg;
+
+    LWIP_ASSERT( "sys_mbox_free: mbox != SYS_MBOX_NULL", mbox != SYS_MBOX_NULL );
+    if( mbox != SYS_MBOX_NULL )
+    {
+        while( uxQueueMessagesWaiting( mbox ) != 0 )
+        {
+            if( sys_arch_mbox_fetch( mbox, &msg, 1 ) != SYS_ARCH_TIMEOUT )
+            {
+                LWIP_ASSERT( "sys_mbox_free: memory leak (msg != NULL)", msg == NULL );
+            }
+        }
+        vQueueDelete( mbox );
+#if SYS_STATS == 1
+        vPortEnterCritical(  );
+        lwip_stats.sys.mbox.used--;
+        vPortExitCritical(  );
+#endif
+    }
+}
+
+/*
+ * This function sends a message to a mailbox. It is unusual in that no error
+ * return is made. This is because the caller is responsible for ensuring that
+ * the mailbox queue will not fail. The caller does this by limiting the number
+ * of msg structures which exist for a given mailbox.
+ */
+void
+sys_mbox_post( sys_mbox_t mbox, void *data )
+{
+    portBASE_TYPE   xQueueSent;
+
+    /* Queue must not be full - Otherwise it is an error. */
+    xQueueSent = xQueueSend( mbox, &data, 0 );
+    LWIP_ASSERT( "sys_mbox_post: xQueueSent == pdPASS", xQueueSent == pdPASS );
+}
+
+/*FSL*/
+/*
+ *Try to post the "msg" to the mailbox. Returns ERR_MEM if this one
+ *is full, else, ERR_OK if the "msg" is posted.
+ */
+err_t
+sys_mbox_trypost( sys_mbox_t mbox, void *data )
+{
+    /* Queue must not be full - Otherwise it is an error. */
+    if(xQueueSend( mbox, &data, 0 ) == pdPASS)
+    {
+    	return ERR_OK;
+    }
+    else
+    {
+    	return ERR_MEM;
+    }
+}
+
+/*
+ * Blocks the thread until a message arrives in the mailbox, but does
+ * not block the thread longer than "timeout" milliseconds (similar to
+ * the sys_arch_sem_wait() function). The "msg" argument is a result
+ * parameter that is set by the function (i.e., by doing "*msg =
+ * ptr"). The "msg" parameter maybe NULL to indicate that the message
+ * should be dropped.
+ *
+ * Note that a function with a similar name, sys_mbox_fetch(), is
+ * implemented by lwIP.
+ */
+u32_t
+sys_arch_mbox_fetch( sys_mbox_t mbox, void **msg, u32_t timeout )
+{
+    void           *ret_msg;
+    portBASE_TYPE   xStatus;
+    TickType_t    xTicksStart, xTicksEnd, xTicksElapsed;
+    u32_t           timespent;
+
+    LWIP_ASSERT( "sys_arch_mbox_fetch: mbox != SYS_MBOX_NULL", mbox != SYS_MBOX_NULL );
+    xTicksStart = xTaskGetTickCount(  );
+    if( timeout == 0 )
+    {
+        do
+        {
+            xStatus = xQueueReceive( mbox, &ret_msg, MS_TO_TICKS( 100 ) );
+        }
+        while( xStatus != pdTRUE );
+    }
+    else
+    {
+        xStatus = xQueueReceive( mbox, &ret_msg, MS_TO_TICKS( timeout ) );
+    }
+
+    if( xStatus == pdTRUE )
+    {
+        if( msg )
+        {
+            *msg = ret_msg;
+        }
+        xTicksEnd = xTaskGetTickCount(  );
+        xTicksElapsed = xTicksEnd - xTicksStart;
+        timespent = TICKS_TO_MS( xTicksElapsed );
+    }
+    else
+    {
+        if( msg )
+        {
+            *msg = NULL;
+        }
+        timespent = SYS_ARCH_TIMEOUT;
+    }
+    return timespent;
+}
+
+u32_t
+sys_jiffies( void )
+{
+    TickType_t    xTicks = xTaskGetTickCount(  );
+
+    return ( u32_t )TICKS_TO_MS( xTicks );
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/arch/cc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/arch/cc.h
new file mode 100644
index 0000000..1317768
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/arch/cc.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ * Modifcations: Christian Walter 
+ */
+#ifndef __CC_H__
+#define __CC_H__
+
+/* ------------------------ System includes ------------------------------- */
+
+/* ------------------------ Project includes ------------------------------ */
+#include "cpu.h"
+#include "sys_arch.h"
+
+/* ------------------------ Defines --------------------------------------- */
+
+//#pragma options align= packed
+#define PACK_STRUCT_BEGIN		
+#define PACK_STRUCT_STRUCT      //non CW compatible: __attribute__ ((__packed__))
+#define PACK_STRUCT_END
+
+#define PACK_STRUCT_FIELD( x )  x
+
+/*FSL: non used on code:
+#define ALIGN_STRUCT_8_BEGIN
+#define ALIGN_STRUCT_8          //non CW compatible: __attribute__ ((aligned (8)))
+#define ALIGN_STRUCT_8_END
+*/
+
+#define LWIP_PLATFORM_ASSERT( x ) sys_assert( x )
+#define LWIP_PLATFORM_DIAG( x, ... ) do{ sys_debug x; } while( 0 );
+
+/* Define (sn)printf formatters for these lwIP types */
+#define U16_F                   "hu"
+#define S16_F                   "hd"
+#define X16_F                   "hx"
+#define U32_F                   "lu"
+#define S32_F                   "ld"
+#define X32_F                   "lx"
+
+/* ------------------------ Type definitions (lwIP) ----------------------- */
+typedef unsigned char u8_t;
+typedef signed char s8_t;
+typedef unsigned short u16_t;
+typedef signed short s16_t;
+typedef unsigned long u32_t;
+typedef signed long s32_t;
+typedef u32_t   mem_ptr_t;
+typedef int     sys_prot_t;
+
+/* ------------------------ Prototypes ------------------------------------ */
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/arch/cpu.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/arch/cpu.h
new file mode 100644
index 0000000..fcdb1bc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/arch/cpu.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __CPU_H__
+#define __CPU_H__
+
+/* ------------------------ Defines --------------------------------------- */
+#define BYTE_ORDER BIG_ENDIAN
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/arch/perf.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/arch/perf.h
new file mode 100644
index 0000000..5c58a65
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/arch/perf.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __PERF_H__
+#define __PERF_H__
+
+/* ------------------------ Defines --------------------------------------- */
+#define PERF_START              /* null definition */
+#define PERF_STOP(x)            /* null definition */
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/arch/sys_arch.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/arch/sys_arch.h
new file mode 100644
index 0000000..20b2e9d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/arch/sys_arch.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __SYS_RTXC_H__
+#define __SYS_RTXC_H__
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+
+#define SYS_MBOX_NULL (QueueHandle_t)0
+#define SYS_SEM_NULL  (SemaphoreHandle_t)0
+
+typedef SemaphoreHandle_t sys_sem_t;
+typedef QueueHandle_t sys_mbox_t;
+typedef TaskHandle_t sys_thread_t;
+
+/* Message queue constants. */
+#define archMESG_QUEUE_LENGTH	( 6 )
+#define archPOST_BLOCK_TIME_MS	( ( unsigned long ) 10000 )
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/eth.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/eth.h
new file mode 100644
index 0000000..6b0b664
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/eth.h
@@ -0,0 +1,55 @@
+/*! 
+ * \file    eth.h
+ * \brief   Definitinos for Ethernet Frames
+ * \version $Revision: 1.2 $
+ * \author  Michael Norman
+ */
+
+#ifndef _ETH_H
+#define _ETH_H
+
+/*******************************************************************/
+
+/* Ethernet standard lengths in bytes*/
+#define ETH_ADDR_LEN    (6)
+#define ETH_TYPE_LEN    (2)
+#define ETH_CRC_LEN     (4)
+#define ETH_MAX_DATA    (1500)
+#define ETH_MIN_DATA    (46)
+#define ETH_HDR_LEN     (ETH_ADDR_LEN * 2 + ETH_TYPE_LEN)
+
+/* Defined Ethernet Frame Types */
+#define ETH_FRM_IP      (0x0800)
+#define ETH_FRM_ARP     (0x0806)
+#define ETH_FRM_RARP    (0x8035)
+#define ETH_FRM_TEST    (0xA5A5)
+
+/* Maximum and Minimum Ethernet Frame Sizes */
+#define ETH_MAX_FRM     (ETH_HDR_LEN + ETH_MAX_DATA + ETH_CRC_LEN)
+#define ETH_MIN_FRM     (ETH_HDR_LEN + ETH_MIN_DATA + ETH_CRC_LEN)
+#define ETH_MTU         (ETH_HDR_LEN + ETH_MAX_DATA)
+
+/* Ethernet Addresses */
+typedef uint8 ETH_ADDR[ETH_ADDR_LEN];
+
+/* 16-bit Ethernet Frame Type, ie. Protocol */
+typedef uint16 ETH_FRM_TYPE;
+
+/* Ethernet Frame Header definition */
+typedef struct
+{
+    ETH_ADDR     dest;
+    ETH_ADDR     src;
+    ETH_FRM_TYPE type;
+} ETH_HDR;
+
+/* Ethernet Frame definition */
+typedef struct
+{
+    ETH_HDR head;
+    uint8*  data;
+} ETH_FRAME;
+
+/*******************************************************************/
+
+#endif  /* _ETH_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/eth_phy.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/eth_phy.h
new file mode 100644
index 0000000..9242e10
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/eth_phy.h
@@ -0,0 +1,87 @@
+/*!
+ * \file    eth.h
+ * \brief   Definitions for Ethernet Physical Layer Interface
+ * \version $Revision: 1.3 $
+ * \author  Michael Norman
+ */
+
+#ifndef _ETH_PHY_H
+#define _ETH_PHY_H
+
+/*******************************************************************/
+
+int
+eth_phy_autoneg(int phy_addr, MII_SPEED speed, MII_DUPLEX duplex);
+
+int 
+eth_phy_manual(int phy_addr, MII_SPEED speed, MII_DUPLEX duplex, int loop);
+
+int 
+eth_phy_get_speed(int, int*);
+
+int 
+eth_phy_get_duplex(int, int*);
+
+int 
+eth_phy_reg_dump(int);
+
+/*******************************************************************/
+
+/* MII Register Addresses */
+#define PHY_BMCR				    (0x00)
+#define PHY_BMSR                    (0x01)
+#define PHY_PHYIDR1				    (0x02)
+#define PHY_PHYIDR2				    (0x03)
+#define PHY_ANAR				    (0x04)
+#define PHY_ANLPAR		            (0x05)
+
+/* Bit definitions and macros for PHY_CTRL */
+#define PHY_BMCR_RESET		        (0x8000)
+#define PHY_BMCR_LOOP   		    (0x4000)
+#define PHY_BMCR_SPEED		        (0x2000)
+#define PHY_BMCR_AN_ENABLE		    (0x1000)
+#define PHY_BMCR_POWERDOWN  	    (0x0800)
+#define PHY_BMCR_ISOLATE	        (0x0400)
+#define PHY_BMCR_AN_RESTART	        (0x0200)
+#define PHY_BMCR_FDX			    (0x0100)
+#define PHY_BMCR_COL_TEST	        (0x0080)
+
+/* Bit definitions and macros for PHY_STAT */
+#define PHY_BMSR_100BT4             (0x8000)
+#define PHY_BMSR_100BTX_FDX         (0x4000)
+#define PHY_BMSR_100BTX             (0x2000)
+#define PHY_BMSR_10BT_FDX           (0x1000)
+#define PHY_BMSR_10BT               (0x0800)
+#define PHY_BMSR_NO_PREAMBLE        (0x0040)
+#define PHY_BMSR_AN_COMPLETE        (0x0020)
+#define PHY_BMSR_REMOTE_FAULT       (0x0010)
+#define PHY_BMSR_AN_ABILITY         (0x0008)
+#define PHY_BMSR_LINK               (0x0004)
+#define PHY_BMSR_JABBER             (0x0002)
+#define PHY_BMSR_EXTENDED           (0x0001)
+
+/* Bit definitions and macros for PHY_AN_ADV */
+#define PHY_ANAR_NEXT_PAGE          (0x8001)
+#define PHY_ANAR_REM_FAULT	        (0x2001)
+#define PHY_ANAR_PAUSE		        (0x0401)
+#define PHY_ANAR_100BT4		        (0x0201)
+#define PHY_ANAR_100BTX_FDX	        (0x0101)
+#define PHY_ANAR_100BTX		        (0x0081)
+#define PHY_ANAR_10BT_FDX		    (0x0041)
+#define PHY_ANAR_10BT		        (0x0021)
+#define PHY_ANAR_802_3		        (0x0001)
+
+/* Bit definitions and macros for PHY_AN_LINK_PAR */
+#define PHY_ANLPAR_NEXT_PAGE        (0x8000)
+#define PHY_ANLPAR_ACK              (0x4000)
+#define PHY_ANLPAR_REM_FAULT	    (0x2000)
+#define PHY_ANLPAR_PAUSE		    (0x0400)
+#define PHY_ANLPAR_100BT4		    (0x0200)
+#define PHY_ANLPAR_100BTX_FDX	    (0x0100)
+#define PHY_ANLPAR_100BTX		    (0x0080)
+#define PHY_ANLPAR_10BTX_FDX        (0x0040)
+#define PHY_ANLPAR_10BT		        (0x0020)
+
+/*******************************************************************/
+
+#endif  /* _ETH_PHY_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/fec.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/fec.h
new file mode 100644
index 0000000..ebca2bb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/fec.h
@@ -0,0 +1,166 @@
+/*
+ * File:    fec.h
+ * Purpose: Driver for the Fast Ethernet Controller (FEC)
+ *
+ * Notes:       
+ */
+
+#ifndef _FEC_H_
+#define _FEC_H_
+
+#include "eth.h"
+#include "fecbd.h"
+#include "mii.h"
+#include "eth_phy.h"
+
+/********************************************************************/
+
+/* External Interface Modes */
+#define FEC_MODE_7WIRE          0   /* Old 7-wire (AMD) mode */
+#define FEC_MODE_MII            1   /* Media Independent Interface */
+#define FEC_MODE_RMII           2   /* Reduced MII */
+#define FEC_MODE_LOOPBACK       3   /* Internal Loopback */
+
+#define INTC_LVL_FEC			3
+/*
+ * FEC Configuration Parameters
+ */
+typedef struct 
+{
+    uint8      ch;       /* FEC channel              */
+    uint8      mode;     /* Transceiver mode         */
+    MII_SPEED  speed;    /* Ethernet Speed           */
+    MII_DUPLEX duplex;   /* Ethernet Duplex          */
+    uint8      prom;     /* Promiscuous Mode?        */
+    uint8      mac[6];   /* Ethernet Address         */
+    uint8      phyaddr;  /* PHY address              */
+    uint8      initphy;  /* Init PHY?                */
+    int        nrxbd;    /* Number of RxBDs          */
+    int        ntxbd;    /* Number of TxBDs          */
+} FEC_CONFIG;
+#define YES 1
+#define NO 0
+/*
+ * FEC Event Log
+ */
+typedef struct {
+    int errors;     /* total count of errors   */
+    int hberr;      /* heartbeat error         */
+    int babr;       /* babbling receiver       */
+    int babt;       /* babbling transmitter    */
+    int gra;        /* graceful stop complete  */
+    int txf;        /* transmit frame          */
+    int txb;        /* transmit buffer         */
+    int rxf;        /* receive frame           */
+    int rxb;        /* received buffer         */
+    int mii;        /* MII                     */
+    int eberr;      /* FEC/DMA fatal bus error */
+    int lc;         /* late collision          */
+    int rl;         /* collision retry limit   */
+    int un;         /* Tx FIFO underflow       */
+    int rfsw_inv;   /* Invalid bit in RFSW     */
+    int rfsw_l;     /* RFSW Last in Frame      */
+    int rfsw_m;     /* RFSW Miss               */
+    int rfsw_bc;    /* RFSW Broadcast          */
+    int rfsw_mc;    /* RFSW Multicast          */
+    int rfsw_lg;    /* RFSW Length Violation   */
+    int rfsw_no;    /* RFSW Non-octet          */
+    int rfsw_cr;    /* RFSW Bad CRC            */
+    int rfsw_ov;    /* RFSW Overflow           */
+    int rfsw_tr;    /* RFSW Truncated          */
+} FEC_EVENT_LOG;
+
+#if 0
+
+int 
+fec_mii_write( int, int, int);
+
+int 
+fec_mii_read(int, int, uint16*);
+
+void
+fec_mii_init(int, int);
+
+void
+fec_mib_init(void);
+
+void
+fec_mib_dump(void);
+
+void
+fec_log_init(int);
+
+void
+fec_log_dump(int);
+
+void
+fec_reg_dump(int);
+
+void
+fec_duplex (int, MII_DUPLEX);
+
+void
+fec_rmii_speed (int, MII_SPEED);
+
+uint8
+fec_hash_address(const uint8*);
+
+void
+fec_set_address (const uint8*);
+
+void
+fec_reset ( void );
+
+void
+fec_init (int, const uint8*);
+
+void
+fec_rx_start(int, uint8*, int);
+
+void
+fec_rx_continue( void );
+
+void
+fec_rx_handler(void);
+
+void
+fec0_rx_handler(void);
+
+void
+fec1_rx_handler(void);
+
+void
+fec_tx_continue( void );
+
+void
+fec_tx_stop (int);
+
+void
+fec_tx_handler(NIF*, int);
+
+int
+fec_send (uint8*, uint8*, uint16 , NBUF*);
+
+int
+fec0_send(uint8*, uint8*, uint16 , NBUF*);
+
+int
+fec1_send(uint8*, uint8*, uint16 , NBUF*);
+
+void
+fec_irq_enable( void );
+
+void
+fec_irq_disable(int);
+
+int
+fec_eth_start(FEC_CONFIG*, int);
+
+void
+fec_eth_stop(int);
+
+#endif
+
+/********************************************************************/
+
+#endif /* _FEC_H_ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/fecbd.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/fecbd.h
new file mode 100644
index 0000000..546b2ce
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/fecbd.h
@@ -0,0 +1,101 @@
+/*
+ * File:    fecbd.h
+ * Purpose:     
+ *
+ * Purpose: Provide a simple buffer management driver
+ */
+
+#ifndef _FECBD_H_
+#define _FECBD_H_
+
+/********************************************************************/
+
+#define Rx  1
+#define Tx  0
+
+/*
+ * Buffer sizes in bytes 
+ */
+#ifndef RX_BUF_SZ
+#define RX_BUF_SZ  1520 //2048 
+#endif
+#ifndef TX_BUF_SZ
+#define TX_BUF_SZ  1520
+#endif
+
+/* 
+ * Buffer Descriptor Format 
+ */
+#pragma options align= packed
+typedef struct
+{
+    uint16 status;  /* control and status */
+    uint16 length;  /* transfer length */
+    uint8  *data;   /* buffer address */
+} FECBD;
+
+/*
+ * Bit level definitions for status field of buffer descriptors
+ */
+#define TX_BD_R         0x8000
+#define TX_BD_TO1       0x4000
+#define TX_BD_W         0x2000
+#define TX_BD_TO2       0x1000
+#define TX_BD_INTERRUPT 0x1000  /* MCF547x/8x Only */
+#define TX_BD_L         0x0800
+#define TX_BD_TC        0x0400
+#define TX_BD_DEF       0x0200  /* MCF5272 Only */
+#define TX_BD_ABC       0x0200
+#define TX_BD_HB        0x0100  /* MCF5272 Only */
+#define TX_BD_LC        0x0080  /* MCF5272 Only */
+#define TX_BD_RL        0x0040  /* MCF5272 Only */
+#define TX_BD_UN        0x0002  /* MCF5272 Only */
+#define TX_BD_CSL       0x0001  /* MCF5272 Only */
+
+#define RX_BD_E         0x8000
+#define RX_BD_R01       0x4000
+#define RX_BD_W         0x2000
+#define RX_BD_R02       0x1000
+#define RX_BD_INTERRUPT 0x1000  /* MCF547x/8x Only */
+#define RX_BD_L         0x0800
+#define RX_BD_M         0x0100
+#define RX_BD_BC        0x0080
+#define RX_BD_MC        0x0040
+#define RX_BD_LG        0x0020
+#define RX_BD_NO        0x0010
+#define RX_BD_CR        0x0004
+#define RX_BD_OV        0x0002
+#define RX_BD_TR        0x0001
+#define RX_BD_ERROR     (RX_BD_NO | RX_BD_CR | RX_BD_OV | RX_BD_TR)
+
+/*
+ * The following defines are provided by the MCF547x/8x 
+ * DMA API.  These are shown here to show their correlation
+ * to the other FEC buffer descriptor status bits
+ * 
+ * #define MCD_FEC_BUF_READY   0x8000
+ * #define MCD_FEC_WRAP        0x2000
+ * #define MCD_FEC_INTERRUPT   0x1000
+ * #define MCD_FEC_END_FRAME   0x0800
+ */
+
+/* 
+ * Functions provided in fec_bd.c 
+ */
+int     fecbd_init(int, int, int);
+void    fecbd_flush(int);
+void    fecbd_dump( void );
+uint32  fecbd_get_start(int, int);
+FECBD*  fecbd_rx_alloc(int);
+FECBD*  fecbd_tx_alloc(int);
+FECBD*  fecbd_tx_free(int);
+
+/*
+ * Error codes
+ */
+#define ERR_MALLOC      (-1)
+#define ERR_NBUFALLOC   (-2)
+
+/*******************************************************************/
+
+#endif /* _FECBD_H_ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/mii.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/mii.h
new file mode 100644
index 0000000..26b2793
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/mii.h
@@ -0,0 +1,43 @@
+/*!
+ * \file    mii.h
+ * \brief   Media Independent Interface (MII) driver
+ * \version $Revision: 1.3 $
+ * \author  Michael Norman
+ * 
+ * \warning This driver assumes that FEC0 is used for all MII management
+ *          communications.  For dual PHYs, etc., insure that FEC0_MDC and
+ *          FEC0_MDIO are connected to the PHY's MDC and MDIO.
+ */
+
+#ifndef _MII_H_
+#define _MII_H_
+
+/*******************************************************************/
+
+int
+mii_write(int, int, uint16);
+
+int
+mii_read(int, int, uint16*);
+
+void
+mii_init(int);
+
+/* MII Speed Settings */
+typedef enum {
+	MII_10BASE_T,	/*!< 10Base-T  operation */
+	MII_100BASE_TX	/*!< 100Base-TX operation */
+} MII_SPEED;
+
+/* MII Duplex Settings */
+typedef enum {
+	MII_HDX,		/*!< half-duplex */
+	MII_FDX			/*!< full-duplex */
+} MII_DUPLEX;
+
+#define MII_TIMEOUT		    0x10000
+#define MII_LINK_TIMEOUT	0x10000
+
+/*******************************************************************/
+
+#endif /* _MII_H_ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/STR91x/arch/cc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/STR91x/arch/cc.h
new file mode 100644
index 0000000..37b18f5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/STR91x/arch/cc.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __CC_H__
+#define __CC_H__
+
+#include 
+#include 
+
+#include "cpu.h"
+
+typedef unsigned   char    u8_t;
+typedef signed     char    s8_t;
+typedef unsigned   short   u16_t;
+typedef signed     short   s16_t;
+typedef unsigned   long    u32_t;
+typedef signed     long    s32_t;
+typedef u32_t mem_ptr_t;
+typedef int sys_prot_t;
+
+#define PACK_STRUCT_BEGIN
+#define PACK_STRUCT_STRUCT
+#define PACK_STRUCT_END
+#define PACK_STRUCT_FIELD(x) x
+
+#define LWIP_PLATFORM_DIAG(x)
+#define LWIP_PLATFORM_ASSERT(x)
+
+#endif /* __CC_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/STR91x/arch/cpu.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/STR91x/arch/cpu.h
new file mode 100644
index 0000000..2af31a8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/STR91x/arch/cpu.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __CPU_H__
+#define __CPU_H__
+
+#define BYTE_ORDER LITTLE_ENDIAN
+
+#endif /* __CPU_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/STR91x/arch/init.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/STR91x/arch/init.h
new file mode 100644
index 0000000..14b9515
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/STR91x/arch/init.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __ARCH_INIT_H__
+#define __ARCH_INIT_H__
+
+#define TCPIP_INIT_DONE(arg)  tcpip_init_done(arg)
+
+void tcpip_init_done(void *);
+int wait_for_tcpip_init(void);
+
+#endif /* __ARCH_INIT_H__ */
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/STR91x/arch/lib.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/STR91x/arch/lib.h
new file mode 100644
index 0000000..9726dee
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/STR91x/arch/lib.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LIB_H__
+#define __LIB_H__
+
+#include 
+
+
+#endif /* __LIB_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/STR91x/arch/perf.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/STR91x/arch/perf.h
new file mode 100644
index 0000000..68afdb5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/STR91x/arch/perf.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __PERF_H__
+#define __PERF_H__
+
+#define PERF_START    /* null definition */
+#define PERF_STOP(x)  /* null definition */
+
+#endif /* __PERF_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/STR91x/arch/sys_arch.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/STR91x/arch/sys_arch.h
new file mode 100644
index 0000000..2f50a9b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/STR91x/arch/sys_arch.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __SYS_RTXC_H__
+#define __SYS_RTXC_H__
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+
+#define SYS_MBOX_NULL (QueueHandle_t)0
+#define SYS_SEM_NULL  (SemaphoreHandle_t)0
+
+typedef SemaphoreHandle_t sys_sem_t;
+typedef QueueHandle_t sys_mbox_t;
+typedef TaskHandle_t sys_thread_t;
+
+/* Message queue constants. */
+#define archMESG_QUEUE_LENGTH	( 6 )
+#define archPOST_BLOCK_TIME_MS	( ( unsigned long ) 10000 )
+
+#endif /* __SYS_RTXC_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/sys_arch.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/sys_arch.c
new file mode 100644
index 0000000..4f781c1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/sys_arch.c
@@ -0,0 +1,440 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* lwIP includes. */
+#include "lwip/debug.h"
+#include "lwip/def.h"
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+#include "lwip/stats.h"
+
+struct timeoutlist
+{
+	struct sys_timeouts timeouts;
+	TaskHandle_t pid;
+};
+
+/* This is the number of threads that can be started with sys_thread_new() */
+#define SYS_THREAD_MAX 4
+
+static struct timeoutlist s_timeoutlist[SYS_THREAD_MAX];
+static u16_t s_nextthread = 0;
+
+
+/*-----------------------------------------------------------------------------------*/
+//  Creates an empty mailbox.
+sys_mbox_t sys_mbox_new(int size)
+{
+	QueueHandle_t mbox;
+
+	( void ) size;
+
+	mbox = xQueueCreate( archMESG_QUEUE_LENGTH, sizeof( void * ) );
+
+#if SYS_STATS
+      ++lwip_stats.sys.mbox.used;
+      if (lwip_stats.sys.mbox.max < lwip_stats.sys.mbox.used) {
+         lwip_stats.sys.mbox.max = lwip_stats.sys.mbox.used;
+	  }
+#endif /* SYS_STATS */
+
+	return mbox;
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Deallocates a mailbox. If there are messages still present in the
+  mailbox when the mailbox is deallocated, it is an indication of a
+  programming error in lwIP and the developer should be notified.
+*/
+void sys_mbox_free(sys_mbox_t mbox)
+{
+	if( uxQueueMessagesWaiting( mbox ) )
+	{
+		/* Line for breakpoint.  Should never break here! */
+		portNOP();
+#if SYS_STATS
+	    lwip_stats.sys.mbox.err++;
+#endif /* SYS_STATS */
+
+		// TODO notify the user of failure.
+	}
+
+	vQueueDelete( mbox );
+
+#if SYS_STATS
+     --lwip_stats.sys.mbox.used;
+#endif /* SYS_STATS */
+}
+
+/*-----------------------------------------------------------------------------------*/
+//   Posts the "msg" to the mailbox.
+void sys_mbox_post(sys_mbox_t mbox, void *data)
+{
+	while ( xQueueSendToBack(mbox, &data, portMAX_DELAY ) != pdTRUE ){}
+}
+
+
+/*-----------------------------------------------------------------------------------*/
+//   Try to post the "msg" to the mailbox.
+err_t sys_mbox_trypost(sys_mbox_t mbox, void *msg)
+{
+err_t result;
+
+   if ( xQueueSend( mbox, &msg, 0 ) == pdPASS )
+   {
+      result = ERR_OK;
+   }
+   else {
+      // could not post, queue must be full
+      result = ERR_MEM;
+
+#if SYS_STATS
+      lwip_stats.sys.mbox.err++;
+#endif /* SYS_STATS */
+
+   }
+
+   return result;
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Blocks the thread until a message arrives in the mailbox, but does
+  not block the thread longer than "timeout" milliseconds (similar to
+  the sys_arch_sem_wait() function). The "msg" argument is a result
+  parameter that is set by the function (i.e., by doing "*msg =
+  ptr"). The "msg" parameter maybe NULL to indicate that the message
+  should be dropped.
+
+  The return values are the same as for the sys_arch_sem_wait() function:
+  Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a
+  timeout.
+
+  Note that a function with a similar name, sys_mbox_fetch(), is
+  implemented by lwIP.
+*/
+u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout)
+{
+void *dummyptr;
+TickType_t StartTime, EndTime, Elapsed;
+
+	StartTime = xTaskGetTickCount();
+
+	if ( msg == NULL )
+	{
+		msg = &dummyptr;
+	}
+
+	if ( timeout != 0 )
+	{
+		if ( pdTRUE == xQueueReceive( mbox, &(*msg), timeout / portTICK_PERIOD_MS ) )
+		{
+			EndTime = xTaskGetTickCount();
+			Elapsed = (EndTime - StartTime) * portTICK_PERIOD_MS;
+
+			return ( Elapsed );
+		}
+		else // timed out blocking for message
+		{
+			*msg = NULL;
+
+			return SYS_ARCH_TIMEOUT;
+		}
+	}
+	else // block forever for a message.
+	{
+		while( pdTRUE != xQueueReceive( mbox, &(*msg), portMAX_DELAY ) ){} // time is arbitrary
+		EndTime = xTaskGetTickCount();
+		Elapsed = (EndTime - StartTime) * portTICK_PERIOD_MS;
+
+		return ( Elapsed ); // return time blocked TODO test
+	}
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Similar to sys_arch_mbox_fetch, but if message is not ready immediately, we'll
+  return with SYS_MBOX_EMPTY.  On success, 0 is returned.
+*/
+u32_t sys_arch_mbox_tryfetch(sys_mbox_t mbox, void **msg)
+{
+void *dummyptr;
+
+	if ( msg == NULL )
+	{
+		msg = &dummyptr;
+	}
+
+   if ( pdTRUE == xQueueReceive( mbox, &(*msg), 0 ) )
+   {
+      return ERR_OK;
+   }
+   else
+   {
+      return SYS_MBOX_EMPTY;
+   }
+}
+
+/*-----------------------------------------------------------------------------------*/
+//  Creates and returns a new semaphore. The "count" argument specifies
+//  the initial state of the semaphore.
+sys_sem_t sys_sem_new(u8_t count)
+{
+	SemaphoreHandle_t  xSemaphore;
+
+	vSemaphoreCreateBinary( xSemaphore );
+
+	if( xSemaphore == NULL )
+	{
+
+#if SYS_STATS
+      ++lwip_stats.sys.sem.err;
+#endif /* SYS_STATS */
+
+		return SYS_SEM_NULL;	// TODO need assert
+	}
+
+	if(count == 0)	// Means it can't be taken
+	{
+		xSemaphoreTake(xSemaphore,1);
+	}
+
+#if SYS_STATS
+	++lwip_stats.sys.sem.used;
+ 	if (lwip_stats.sys.sem.max < lwip_stats.sys.sem.used) {
+		lwip_stats.sys.sem.max = lwip_stats.sys.sem.used;
+	}
+#endif /* SYS_STATS */
+
+	return xSemaphore;
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Blocks the thread while waiting for the semaphore to be
+  signaled. If the "timeout" argument is non-zero, the thread should
+  only be blocked for the specified time (measured in
+  milliseconds).
+
+  If the timeout argument is non-zero, the return value is the number of
+  milliseconds spent waiting for the semaphore to be signaled. If the
+  semaphore wasn't signaled within the specified time, the return value is
+  SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
+  (i.e., it was already signaled), the function may return zero.
+
+  Notice that lwIP implements a function with a similar name,
+  sys_sem_wait(), that uses the sys_arch_sem_wait() function.
+*/
+u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout)
+{
+TickType_t StartTime, EndTime, Elapsed;
+
+	StartTime = xTaskGetTickCount();
+
+	if(	timeout != 0)
+	{
+		if( xSemaphoreTake( sem, timeout / portTICK_PERIOD_MS ) == pdTRUE )
+		{
+			EndTime = xTaskGetTickCount();
+			Elapsed = (EndTime - StartTime) * portTICK_PERIOD_MS;
+
+			return (Elapsed); // return time blocked TODO test
+		}
+		else
+		{
+			return SYS_ARCH_TIMEOUT;
+		}
+	}
+	else // must block without a timeout
+	{
+		while( xSemaphoreTake( sem, portMAX_DELAY ) != pdTRUE ){}
+		EndTime = xTaskGetTickCount();
+		Elapsed = (EndTime - StartTime) * portTICK_PERIOD_MS;
+
+		return ( Elapsed ); // return time blocked
+
+	}
+}
+
+/*-----------------------------------------------------------------------------------*/
+// Signals a semaphore
+void sys_sem_signal(sys_sem_t sem)
+{
+	xSemaphoreGive( sem );
+}
+
+/*-----------------------------------------------------------------------------------*/
+// Deallocates a semaphore
+void sys_sem_free(sys_sem_t sem)
+{
+#if SYS_STATS
+      --lwip_stats.sys.sem.used;
+#endif /* SYS_STATS */
+
+	vQueueDelete( sem );
+}
+
+/*-----------------------------------------------------------------------------------*/
+// Initialize sys arch
+void sys_init(void)
+{
+	int i;
+
+	// Initialize the the per-thread sys_timeouts structures
+	// make sure there are no valid pids in the list
+	for(i = 0; i < SYS_THREAD_MAX; i++)
+	{
+		s_timeoutlist[i].pid = 0;
+		s_timeoutlist[i].timeouts.next = NULL;
+	}
+
+	// keep track of how many threads have been created
+	s_nextthread = 0;
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Returns a pointer to the per-thread sys_timeouts structure. In lwIP,
+  each thread has a list of timeouts which is represented as a linked
+  list of sys_timeout structures. The sys_timeouts structure holds a
+  pointer to a linked list of timeouts. This function is called by
+  the lwIP timeout scheduler and must not return a NULL value.
+
+  In a single threaded sys_arch implementation, this function will
+  simply return a pointer to a global sys_timeouts variable stored in
+  the sys_arch module.
+*/
+struct sys_timeouts *sys_arch_timeouts(void)
+{
+int i;
+TaskHandle_t pid;
+struct timeoutlist *tl;
+
+	pid = xTaskGetCurrentTaskHandle( );
+
+	for(i = 0; i < s_nextthread; i++)
+	{
+		tl = &(s_timeoutlist[i]);
+		if(tl->pid == pid)
+		{
+			return &(tl->timeouts);
+		}
+	}
+
+	// Error
+	return NULL;
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*-----------------------------------------------------------------------------------*/
+// TODO
+/*-----------------------------------------------------------------------------------*/
+/*
+  Starts a new thread with priority "prio" that will begin its execution in the
+  function "thread()". The "arg" argument will be passed as an argument to the
+  thread() function. The id of the new thread is returned. Both the id and
+  the priority are system dependent.
+*/
+sys_thread_t sys_thread_new(char *name, void (* thread)(void *arg), void *arg, int stacksize, int prio)
+{
+TaskHandle_t CreatedTask;
+int result;
+
+   if ( s_nextthread < SYS_THREAD_MAX )
+   {
+      result = xTaskCreate( thread, name, stacksize, arg, prio, &CreatedTask );
+
+	   // For each task created, store the task handle (pid) in the timers array.
+	   // This scheme doesn't allow for threads to be deleted
+	   s_timeoutlist[s_nextthread++].pid = CreatedTask;
+
+	   if(result == pdPASS)
+	   {
+		   return CreatedTask;
+	   }
+	   else
+	   {
+		   return NULL;
+	   }
+   }
+   else
+   {
+      return NULL;
+   }
+}
+
+/*
+  This optional function does a "fast" critical region protection and returns
+  the previous protection level. This function is only called during very short
+  critical regions. An embedded system which supports ISR-based drivers might
+  want to implement this function by disabling interrupts. Task-based systems
+  might want to implement this by using a mutex or disabling tasking. This
+  function should support recursive calls from the same task or interrupt. In
+  other words, sys_arch_protect() could be called while already protected. In
+  that case the return value indicates that it is already protected.
+
+  sys_arch_protect() is only required if your port is supporting an operating
+  system.
+*/
+sys_prot_t sys_arch_protect(void)
+{
+	vPortEnterCritical();
+	return 1;
+}
+
+/*
+  This optional function does a "fast" set of critical region protection to the
+  value specified by pval. See the documentation for sys_arch_protect() for
+  more information. This function is only required if your port is supporting
+  an operating system.
+*/
+void sys_arch_unprotect(sys_prot_t pval)
+{
+	( void ) pval;
+	vPortExitCritical();
+}
+
+/*
+ * Prints an assertion messages and aborts execution.
+ */
+void sys_assert( const char *msg )
+{
+	( void ) msg;
+	/*FSL:only needed for debugging
+	printf(msg);
+	printf("\n\r");
+	*/
+    vPortEnterCritical(  );
+    for(;;)
+    ;
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/doc/FILES b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/doc/FILES
new file mode 100644
index 0000000..7455d4b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/doc/FILES
@@ -0,0 +1,5 @@
+savannah.txt   - How to obtain the current development source code.
+contrib.txt    - How to contribute to lwIP as a developer.
+rawapi.txt     - The documentation for the core API of lwIP.
+snmp_agent.txt - The documentation for the lwIP SNMP agent.
+sys_arch.txt   - The documentation for a system abstraction layer of lwIP.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/doc/contrib.txt b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/doc/contrib.txt
new file mode 100644
index 0000000..3057beb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/doc/contrib.txt
@@ -0,0 +1,63 @@
+1 Introduction
+
+This document describes some guidelines for people participating
+in lwIP development.
+
+2 How to contribute to lwIP
+
+Here is a short list of suggestions to anybody working with lwIP and 
+trying to contribute bug reports, fixes, enhancements, platform ports etc.
+First of all as you may already know lwIP is a volunteer project so feedback
+to fixes or questions might often come late. Hopefully the bug and patch tracking 
+features of Savannah help us not lose users' input.
+
+2.1 Source code style:
+
+1. do not use tabs.
+2. indentation is two spaces per level (i.e. per tab).
+3. end debug messages with a trailing newline (\n).
+4. one space between keyword and opening bracket.
+5. no space between function and opening bracket.
+6. one space and no newline before opening curly braces of a block.
+7. closing curly brace on a single line.
+8. spaces surrounding assignment and comparisons.
+9. don't initialize static and/or global variables to zero, the compiler takes care of that.
+10. use current source code style as further reference.
+
+2.2 Source code documentation style:
+
+1. JavaDoc compliant and Doxygen compatible.
+2. Function documentation above functions in .c files, not .h files.
+   (This forces you to synchronize documentation and implementation.)
+3. Use current documentation style as further reference.
+ 
+2.3 Bug reports and patches:
+
+1. Make sure you are reporting bugs or send patches against the latest
+   sources. (From the latest release and/or the current CVS sources.)
+2. If you think you found a bug make sure it's not already filed in the
+   bugtracker at Savannah.
+3. If you have a fix put the patch on Savannah. If it is a patch that affects
+   both core and arch specific stuff please separate them so that the core can
+   be applied separately while leaving the other patch 'open'. The prefered way
+   is to NOT touch archs you can't test and let maintainers take care of them.
+   This is a good way to see if they are used at all - the same goes for unix
+   netifs except tapif.
+4. Do not file a bug and post a fix to it to the patch area. Either a bug report
+   or a patch will be enough.
+   If you correct an existing bug then attach the patch to the bug rather than creating a new entry in the patch area.
+5. Trivial patches (compiler warning, indentation and spelling fixes or anything obvious which takes a line or two)
+   can go to the lwip-users list. This is still the fastest way of interaction and the list is not so crowded
+   as to allow for loss of fixes. Putting bugs on Savannah and subsequently closing them is too much an overhead
+   for reporting a compiler warning fix.
+6. Patches should be specific to a single change or to related changes.Do not mix bugfixes with spelling and other
+   trivial fixes unless the bugfix is trivial too.Do not reorganize code and rename identifiers in the same patch you
+   change behaviour if not necessary.A patch is easier to read and understand if it's to the point and short than
+   if it's not to the point and long :) so the chances for it to be applied are greater. 
+
+2.4 Platform porters:
+
+1. If you have ported lwIP to a platform (an OS, a uC/processor or a combination of these) and
+   you think it could benefit others[1] you might want discuss this on the mailing list. You
+   can also ask for CVS access to submit and maintain your port in the contrib CVS module.
+   
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/doc/rawapi.txt b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/doc/rawapi.txt
new file mode 100644
index 0000000..d511280
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/doc/rawapi.txt
@@ -0,0 +1,437 @@
+Raw TCP/IP interface for lwIP
+
+Authors: Adam Dunkels, Leon Woestenberg, Christiaan Simons
+
+lwIP provides two Application Program's Interfaces (APIs) for programs
+to use for communication with the TCP/IP code:
+* low-level "core" / "callback" or "raw" API.
+* higher-level "sequential" API.
+
+The sequential API provides a way for ordinary, sequential, programs
+to use the lwIP stack. It is quite similar to the BSD socket API. The
+model of execution is based on the blocking open-read-write-close
+paradigm. Since the TCP/IP stack is event based by nature, the TCP/IP
+code and the application program must reside in different execution
+contexts (threads).
+
+** The remainder of this document discusses the "raw" API. **
+
+The raw TCP/IP interface allows the application program to integrate
+better with the TCP/IP code. Program execution is event based by
+having callback functions being called from within the TCP/IP
+code. The TCP/IP code and the application program both run in the same
+thread. The sequential API has a much higher overhead and is not very
+well suited for small systems since it forces a multithreaded paradigm
+on the application.
+
+The raw TCP/IP interface is not only faster in terms of code execution
+time but is also less memory intensive. The drawback is that program
+development is somewhat harder and application programs written for
+the raw TCP/IP interface are more difficult to understand. Still, this
+is the preferred way of writing applications that should be small in
+code size and memory usage.
+
+Both APIs can be used simultaneously by different application
+programs. In fact, the sequential API is implemented as an application
+program using the raw TCP/IP interface.
+
+--- Callbacks
+
+Program execution is driven by callbacks. Each callback is an ordinary
+C function that is called from within the TCP/IP code. Every callback
+function is passed the current TCP or UDP connection state as an
+argument. Also, in order to be able to keep program specific state,
+the callback functions are called with a program specified argument
+that is independent of the TCP/IP state.
+
+The function for setting the application connection state is:
+
+- void tcp_arg(struct tcp_pcb *pcb, void *arg)
+
+  Specifies the program specific state that should be passed to all
+  other callback functions. The "pcb" argument is the current TCP
+  connection control block, and the "arg" argument is the argument
+  that will be passed to the callbacks.
+
+  
+--- TCP connection setup
+
+The functions used for setting up connections is similar to that of
+the sequential API and of the BSD socket API. A new TCP connection
+identifier (i.e., a protocol control block - PCB) is created with the
+tcp_new() function. This PCB can then be either set to listen for new
+incoming connections or be explicitly connected to another host.
+
+- struct tcp_pcb *tcp_new(void)
+
+  Creates a new connection identifier (PCB). If memory is not
+  available for creating the new pcb, NULL is returned.
+
+- err_t tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port)
+
+  Binds the pcb to a local IP address and port number. The IP address
+  can be specified as IP_ADDR_ANY in order to bind the connection to
+  all local IP addresses.
+
+  If another connection is bound to the same port, the function will
+  return ERR_USE, otherwise ERR_OK is returned.
+
+- struct tcp_pcb *tcp_listen(struct tcp_pcb *pcb)
+
+  Commands a pcb to start listening for incoming connections. When an
+  incoming connection is accepted, the function specified with the
+  tcp_accept() function will be called. The pcb will have to be bound
+  to a local port with the tcp_bind() function.
+
+  The tcp_listen() function returns a new connection identifier, and
+  the one passed as an argument to the function will be
+  deallocated. The reason for this behavior is that less memory is
+  needed for a connection that is listening, so tcp_listen() will
+  reclaim the memory needed for the original connection and allocate a
+  new smaller memory block for the listening connection.
+
+  tcp_listen() may return NULL if no memory was available for the
+  listening connection. If so, the memory associated with the pcb
+  passed as an argument to tcp_listen() will not be deallocated.
+
+- struct tcp_pcb *tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog)
+
+  Same as tcp_listen, but limits the number of outstanding connections
+  in the listen queue to the value specified by the backlog argument.
+  To use it, your need to set TCP_LISTEN_BACKLOG=1 in your lwipopts.h.
+
+- void tcp_accepted(struct tcp_pcb *pcb)
+
+  Inform lwIP that an incoming connection has been accepted. This would
+  usually be called from the accept callback. This allows lwIP to perform
+  housekeeping tasks, such as allowing further incoming connections to be
+  queued in the listen backlog.
+
+- void tcp_accept(struct tcp_pcb *pcb,
+                  err_t (* accept)(void *arg, struct tcp_pcb *newpcb,
+                                   err_t err))
+
+  Specified the callback function that should be called when a new
+  connection arrives on a listening connection.
+      
+- err_t tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+                    u16_t port, err_t (* connected)(void *arg,
+                                                    struct tcp_pcb *tpcb,
+                                                    err_t err));
+
+  Sets up the pcb to connect to the remote host and sends the
+  initial SYN segment which opens the connection. 
+
+  The tcp_connect() function returns immediately; it does not wait for
+  the connection to be properly setup. Instead, it will call the
+  function specified as the fourth argument (the "connected" argument)
+  when the connection is established. If the connection could not be
+  properly established, either because the other host refused the
+  connection or because the other host didn't answer, the "connected"
+  function will be called with an the "err" argument set accordingly.
+
+  The tcp_connect() function can return ERR_MEM if no memory is
+  available for enqueueing the SYN segment. If the SYN indeed was
+  enqueued successfully, the tcp_connect() function returns ERR_OK.
+
+  
+--- Sending TCP data
+
+TCP data is sent by enqueueing the data with a call to
+tcp_write(). When the data is successfully transmitted to the remote
+host, the application will be notified with a call to a specified
+callback function.
+
+- err_t tcp_write(struct tcp_pcb *pcb, void *dataptr, u16_t len,
+                  u8_t copy)
+
+  Enqueues the data pointed to by the argument dataptr. The length of
+  the data is passed as the len parameter. The copy argument is either
+  0 or 1 and indicates whether the new memory should be allocated for
+  the data to be copied into. If the argument is 0, no new memory
+  should be allocated and the data should only be referenced by
+  pointer.
+
+  The tcp_write() function will fail and return ERR_MEM if the length
+  of the data exceeds the current send buffer size or if the length of
+  the queue of outgoing segment is larger than the upper limit defined
+  in lwipopts.h. The number of bytes available in the output queue can
+  be retrieved with the tcp_sndbuf() function.
+
+  The proper way to use this function is to call the function with at
+  most tcp_sndbuf() bytes of data. If the function returns ERR_MEM,
+  the application should wait until some of the currently enqueued
+  data has been successfully received by the other host and try again.
+
+- void tcp_sent(struct tcp_pcb *pcb,
+                err_t (* sent)(void *arg, struct tcp_pcb *tpcb,
+                u16_t len))
+
+  Specifies the callback function that should be called when data has
+  successfully been received (i.e., acknowledged) by the remote
+  host. The len argument passed to the callback function gives the
+  amount bytes that was acknowledged by the last acknowledgment.
+
+  
+--- Receiving TCP data
+
+TCP data reception is callback based - an application specified
+callback function is called when new data arrives. When the
+application has taken the data, it has to call the tcp_recved()
+function to indicate that TCP can advertise increase the receive
+window.
+
+- void tcp_recv(struct tcp_pcb *pcb,
+                err_t (* recv)(void *arg, struct tcp_pcb *tpcb,
+                               struct pbuf *p, err_t err))
+
+  Sets the callback function that will be called when new data
+  arrives. The callback function will be passed a NULL pbuf to
+  indicate that the remote host has closed the connection. If
+  there are no errors and the callback function is to return
+  ERR_OK, then it must free the pbuf. Otherwise, it must not
+  free the pbuf so that lwIP core code can store it.
+
+- void tcp_recved(struct tcp_pcb *pcb, u16_t len)
+
+  Must be called when the application has received the data. The len
+  argument indicates the length of the received data.
+    
+
+--- Application polling
+
+When a connection is idle (i.e., no data is either transmitted or
+received), lwIP will repeatedly poll the application by calling a
+specified callback function. This can be used either as a watchdog
+timer for killing connections that have stayed idle for too long, or
+as a method of waiting for memory to become available. For instance,
+if a call to tcp_write() has failed because memory wasn't available,
+the application may use the polling functionality to call tcp_write()
+again when the connection has been idle for a while.
+
+- void tcp_poll(struct tcp_pcb *pcb, u8_t interval,
+                err_t (* poll)(void *arg, struct tcp_pcb *tpcb))
+
+  Specifies the polling interval and the callback function that should
+  be called to poll the application. The interval is specified in
+  number of TCP coarse grained timer shots, which typically occurs
+  twice a second. An interval of 10 means that the application would
+  be polled every 5 seconds.
+
+
+--- Closing and aborting connections
+
+- err_t tcp_close(struct tcp_pcb *pcb)
+
+  Closes the connection. The function may return ERR_MEM if no memory
+  was available for closing the connection. If so, the application
+  should wait and try again either by using the acknowledgment
+  callback or the polling functionality. If the close succeeds, the
+  function returns ERR_OK.
+
+  The pcb is deallocated by the TCP code after a call to tcp_close(). 
+
+- void tcp_abort(struct tcp_pcb *pcb)
+
+  Aborts the connection by sending a RST (reset) segment to the remote
+  host. The pcb is deallocated. This function never fails.
+
+If a connection is aborted because of an error, the application is
+alerted of this event by the err callback. Errors that might abort a
+connection are when there is a shortage of memory. The callback
+function to be called is set using the tcp_err() function.
+
+- void tcp_err(struct tcp_pcb *pcb, void (* err)(void *arg,
+       err_t err))
+
+  The error callback function does not get the pcb passed to it as a
+  parameter since the pcb may already have been deallocated.
+
+
+--- Lower layer TCP interface
+
+TCP provides a simple interface to the lower layers of the
+system. During system initialization, the function tcp_init() has
+to be called before any other TCP function is called. When the system
+is running, the two timer functions tcp_fasttmr() and tcp_slowtmr()
+must be called with regular intervals. The tcp_fasttmr() should be
+called every TCP_FAST_INTERVAL milliseconds (defined in tcp.h) and
+tcp_slowtmr() should be called every TCP_SLOW_INTERVAL milliseconds. 
+
+
+--- UDP interface
+
+The UDP interface is similar to that of TCP, but due to the lower
+level of complexity of UDP, the interface is significantly simpler.
+
+- struct udp_pcb *udp_new(void)
+
+  Creates a new UDP pcb which can be used for UDP communication. The
+  pcb is not active until it has either been bound to a local address
+  or connected to a remote address.
+
+- void udp_remove(struct udp_pcb *pcb)
+
+  Removes and deallocates the pcb.  
+  
+- err_t udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port)
+
+  Binds the pcb to a local address. The IP-address argument "ipaddr"
+  can be IP_ADDR_ANY to indicate that it should listen to any local IP
+  address. The function currently always return ERR_OK.
+
+- err_t udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                    u16_t port)
+
+  Sets the remote end of the pcb. This function does not generate any
+  network traffic, but only set the remote address of the pcb.
+
+- err_t udp_disconnect(struct udp_pcb *pcb)
+
+  Remove the remote end of the pcb. This function does not generate
+  any network traffic, but only removes the remote address of the pcb.
+
+- err_t udp_send(struct udp_pcb *pcb, struct pbuf *p)
+
+  Sends the pbuf p. The pbuf is not deallocated.
+
+- void udp_recv(struct udp_pcb *pcb,
+                void (* recv)(void *arg, struct udp_pcb *upcb,
+                                         struct pbuf *p,
+                                         struct ip_addr *addr,
+                                         u16_t port),
+                              void *recv_arg)
+
+  Specifies a callback function that should be called when a UDP
+  datagram is received.
+  
+
+--- System initalization
+
+A truly complete and generic sequence for initializing the lwip stack
+cannot be given because it depends on the build configuration (lwipopts.h)
+and additional initializations for your runtime environment (e.g. timers).
+
+We can give you some idea on how to proceed when using the raw API.
+We assume a configuration using a single Ethernet netif and the
+UDP and TCP transport layers, IPv4 and the DHCP client.
+
+Call these functions in the order of appearance:
+
+- stats_init()
+
+  Clears the structure where runtime statistics are gathered.
+
+- sys_init()
+  
+  Not of much use since we set the NO_SYS 1 option in lwipopts.h,
+  to be called for easy configuration changes.
+
+- mem_init()
+
+  Initializes the dynamic memory heap defined by MEM_SIZE.
+
+- memp_init()
+
+  Initializes the memory pools defined by MEMP_NUM_x.
+
+- pbuf_init()
+
+  Initializes the pbuf memory pool defined by PBUF_POOL_SIZE.
+  
+- etharp_init()
+
+  Initializes the ARP table and queue.
+  Note: you must call etharp_tmr at a ARP_TMR_INTERVAL (5 seconds) regular interval
+  after this initialization.
+
+- ip_init()
+
+  Doesn't do much, it should be called to handle future changes.
+
+- udp_init()
+
+  Clears the UDP PCB list.
+
+- tcp_init()
+
+  Clears the TCP PCB list and clears some internal TCP timers.
+  Note: you must call tcp_fasttmr() and tcp_slowtmr() at the
+  predefined regular intervals after this initialization. 
+  
+- netif_add(struct netif *netif, struct ip_addr *ipaddr,
+            struct ip_addr *netmask, struct ip_addr *gw,
+            void *state, err_t (* init)(struct netif *netif),
+            err_t (* input)(struct pbuf *p, struct netif *netif))
+
+  Adds your network interface to the netif_list. Allocate a struct
+  netif and pass a pointer to this structure as the first argument.
+  Give pointers to cleared ip_addr structures when using DHCP,
+  or fill them with sane numbers otherwise. The state pointer may be NULL.
+
+  The init function pointer must point to a initialization function for
+  your ethernet netif interface. The following code illustrates it's use.
+  
+  err_t netif_if_init(struct netif *netif)
+  {
+    u8_t i;
+    
+    for(i = 0; i < ETHARP_HWADDR_LEN; i++) netif->hwaddr[i] = some_eth_addr[i];
+    init_my_eth_device();
+    return ERR_OK;
+  }
+  
+  For ethernet drivers, the input function pointer must point to the lwip
+  function ethernet_input() declared in "netif/etharp.h". Other drivers
+  must use ip_input() declared in "lwip/ip.h".
+  
+- netif_set_default(struct netif *netif)
+
+  Registers the default network interface.
+
+- netif_set_up(struct netif *netif)
+
+  When the netif is fully configured this function must be called.
+
+- dhcp_start(struct netif *netif)
+
+  Creates a new DHCP client for this interface on the first call.
+  Note: you must call dhcp_fine_tmr() and dhcp_coarse_tmr() at
+  the predefined regular intervals after starting the client.
+  
+  You can peek in the netif->dhcp struct for the actual DHCP status.
+
+
+--- Optimalization hints
+
+The first thing you want to optimize is the lwip_standard_checksum()
+routine from src/core/inet.c. You can override this standard
+function with the #define LWIP_CHKSUM .
+
+There are C examples given in inet.c or you might want to
+craft an assembly function for this. RFC1071 is a good
+introduction to this subject.
+
+Other significant improvements can be made by supplying
+assembly or inline replacements for htons() and htonl()
+if you're using a little-endian architecture.
+#define LWIP_PLATFORM_BYTESWAP 1
+#define LWIP_PLATFORM_HTONS(x) 
+#define LWIP_PLATFORM_HTONL(x) 
+
+Check your network interface driver if it reads at
+a higher speed than the maximum wire-speed. If the
+hardware isn't serviced frequently and fast enough
+buffer overflows are likely to occur.
+
+E.g. when using the cs8900 driver, call cs8900if_service(ethif)
+as frequently as possible. When using an RTOS let the cs8900 interrupt
+wake a high priority task that services your driver using a binary
+semaphore or event flag. Some drivers might allow additional tuning
+to match your application and network.
+
+For a production release it is recommended to set LWIP_STATS to 0.
+Note that speed performance isn't influenced much by simply setting
+high values to the memory options.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/doc/savannah.txt b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/doc/savannah.txt
new file mode 100644
index 0000000..b4c6acb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/doc/savannah.txt
@@ -0,0 +1,135 @@
+Daily Use Guide for using Savannah for lwIP
+
+Table of Contents:
+
+1 - Obtaining lwIP from the CVS repository
+2 - Committers/developers CVS access using SSH (to be written)
+3 - Merging from DEVEL branch to main trunk (stable branch)
+4 - How to release lwIP
+
+
+
+1 Obtaining lwIP from the CVS repository
+----------------------------------------
+
+To perform an anonymous CVS checkout of the main trunk (this is where
+bug fixes and incremental enhancements occur), do this:
+
+cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout lwip
+ 
+Or, obtain a stable branch (updated with bug fixes only) as follows:
+cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \
+  -r STABLE-0_7 -d lwip-0.7 lwip
+
+Or, obtain a specific (fixed) release as follows:
+cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \
+  -r STABLE-0_7_0 -d lwip-0.7.0 lwip
+
+3 Committers/developers CVS access using SSH
+--------------------------------------------
+
+The Savannah server uses SSH (Secure Shell) protocol 2 authentication and encryption.
+As such, CVS commits to the server occur through a SSH tunnel for project members.
+To create a SSH2 key pair in UNIX-like environments, do this:
+
+ssh-keygen -t dsa
+
+Under Windows, a recommended SSH client is "PuTTY", freely available with good
+documentation and a graphic user interface. Use its key generator.
+
+Now paste the id_dsa.pub contents into your Savannah account public key list. Wait
+a while so that Savannah can update its configuration (This can take minutes).
+
+Try to login using SSH:
+
+ssh -v your_login@cvs.sv.gnu.org
+
+If it tells you:
+
+Authenticating with public key "your_key_name"...
+Server refused to allocate pty
+
+then you could login; Savannah refuses to give you a shell - which is OK, as we
+are allowed to use SSH for CVS only. Now, you should be able to do this:
+
+export CVS_RSH=ssh
+cvs -z3 -d:ext:your_login@cvs.sv.gnu.org:/sources/lwip co lwip
+ 
+after which you can edit your local files with bug fixes or new features and
+commit them. Make sure you know what you are doing when using CVS to make
+changes on the repository. If in doubt, ask on the lwip-members mailing list.
+
+(If SSH asks about authenticity of the host, you can check the key
+ fingerprint against http://savannah.nongnu.org/cvs/?group=lwip)
+
+
+3 Merging from DEVEL branch to main trunk (stable)
+--------------------------------------------------
+
+Merging is a delicate process in CVS and requires the
+following disciplined steps in order to prevent conflicts
+in the future. Conflicts can be hard to solve!
+
+Merging from branch A to branch B requires that the A branch
+has a tag indicating the previous merger. This tag is called
+'merged_from_A_to_B'. After merging, the tag is moved in the
+A branch to remember this merger for future merge actions.
+
+IMPORTANT: AFTER COMMITTING A SUCCESFUL MERGE IN THE
+REPOSITORY, THE TAG MUST BE SET ON THE SOURCE BRANCH OF THE
+MERGE ACTION (REPLACING EXISTING TAGS WITH THE SAME NAME).
+
+Merge all changes in DEVEL since our last merge to main:
+
+In the working copy of the main trunk:
+cvs update -P -jmerged_from_DEVEL_to_main -jDEVEL 
+
+(This will apply the changes between 'merged_from_DEVEL_to_main'
+and 'DEVEL' to your work set of files)
+
+We can now commit the merge result.
+cvs commit -R -m "Merged from DEVEL to main." 
+
+If this worked out OK, we now move the tag in the DEVEL branch
+to this merge point, so we can use this point for future merges:
+
+cvs rtag -F -r DEVEL merged_from_DEVEL_to_main lwip 
+
+4 How to release lwIP
+---------------------
+
+First, checkout a clean copy of the branch to be released. Tag this set with
+tag name "STABLE-0_6_3". (I use release number 0.6.3 throughout this example).
+
+Login CVS using pserver authentication, then export a clean copy of the
+tagged tree. Export is similar to a checkout, except that the CVS metadata
+is not created locally. 
+
+export CVS_RSH=ssh
+cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \
+  -r STABLE-0_6_3 -d lwip-0.6.3 lwip
+
+Archive this directory using tar, gzip'd, bzip2'd and zip'd.
+
+tar czvf lwip-0.6.3.tar.gz lwip-0.6.3
+tar cjvf lwip-0.6.3.tar.bz2 lwip-0.6.3
+zip -r lwip-0.6.3.zip lwip-0.6.3
+
+Now, sign the archives with a detached GPG binary signature as follows:
+
+gpg -b lwip-0.6.3.tar.gz
+gpg -b lwip-0.6.3.tar.bz2
+gpg -b lwip-0.6.3.zip
+
+Upload these files using anonymous FTP:
+ncftp ftp://savannah.gnu.org/incoming/savannah/lwip
+
+ncftp>mput *0.6.3.*
+
+Additionally, you may post a news item on Savannah, like this:
+
+A new 0.6.3 release is now available here:
+http://savannah.nongnu.org/files/?group=lwip&highlight=0.6.3
+
+You will have to submit this via the user News interface, then approve
+this via the Administrator News interface.
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/doc/snmp_agent.txt b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/doc/snmp_agent.txt
new file mode 100644
index 0000000..54c278a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/doc/snmp_agent.txt
@@ -0,0 +1,181 @@
+SNMPv1 agent for lwIP
+
+Author: Christiaan Simons
+
+This is a brief introduction how to use and configure the SNMP agent.
+Note the agent uses the raw-API UDP interface so you may also want to
+read rawapi.txt to gain a better understanding of the SNMP message handling.
+
+0 Agent Capabilities
+====================
+
+SNMPv1 per RFC1157
+  This is an old(er) standard but is still widely supported.
+  For SNMPv2c and v3 have a greater complexity and need many
+  more lines of code. IMHO this breaks the idea of "lightweight IP".
+
+  Note the S in SNMP stands for "Simple". Note that "Simple" is
+  relative. SNMP is simple compared to the complex ISO network
+  management protocols CMIP (Common Management Information Protocol)
+  and CMOT (CMip Over Tcp).
+
+MIB II per RFC1213
+  The standard lwIP stack management information base.
+  This is a required MIB, so this is always enabled.
+  When builing lwIP without TCP, the mib-2.tcp group is omitted.
+  The groups EGP, CMOT and transmission are disabled by default.
+  
+  Most mib-2 objects are not writable except:
+  sysName, sysLocation, sysContact, snmpEnableAuthenTraps.
+  Writing to or changing the ARP and IP address and route
+  tables is not possible.
+ 
+  Note lwIP has a very limited notion of IP routing. It currently
+  doen't have a route table and doesn't have a notion of the U,G,H flags.
+  Instead lwIP uses the interface list with only one default interface
+  acting as a single gateway interface (G) for the default route.
+
+  The agent returns a "virtual table" with the default route 0.0.0.0
+  for the default interface and network routes (no H) for each
+  network interface in the netif_list.
+  All routes are considered to be up (U).
+
+Loading additional MIBs
+  MIBs can only be added in compile-time, not in run-time.
+  There is no MIB compiler thus additional MIBs must be hand coded.
+
+Large SNMP message support
+  The packet decoding and encoding routines are designed
+  to use pbuf-chains. Larger payloads then the minimum
+  SNMP requirement of 484 octets are supported if the 
+  PBUF_POOL_SIZE and IP_REASS_BUFSIZE are set to match your
+  local requirement.
+
+1 Building the Agent
+====================
+
+First of all you'll need to add the following define
+to your local lwipopts.h:
+
+#define LWIP_SNMP               1
+
+and add the source files in lwip/src/core/snmp
+and some snmp headers in lwip/src/include/lwip to your makefile.
+
+Note you'll might need to adapt you network driver to update
+the mib2 variables for your interface.
+
+2 Running the Agent
+===================
+
+The following function calls must be made in your program to
+actually get the SNMP agent running.
+
+Before starting the agent you should supply pointers
+to non-volatile memory for sysContact, sysLocation,
+and snmpEnableAuthenTraps. You can do this by calling
+
+snmp_set_syscontact()
+snmp_set_syslocation()
+snmp_set_snmpenableauthentraps()
+
+Additionally you may want to set
+
+snmp_set_sysdescr()
+snmp_set_sysobjid() (if you have a private MIB)
+snmp_set_sysname()
+
+Also before starting the agent you need to setup
+one or more trap destinations using these calls:
+
+snmp_trap_dst_enable();
+snmp_trap_dst_ip_set();
+
+In the lwIP initialisation sequence call snmp_init() just after
+the call to udp_init().
+
+Exactly every 10 msec the SNMP uptime timestamp must be updated with
+snmp_inc_sysuptime(). You should call this from a timer interrupt
+or a timer signal handler depending on your runtime environment.
+
+An alternative way to update the SNMP uptime timestamp is to do a call like
+snmp_add_sysuptime(100) each 1000ms (which is bigger "step", but call to
+a lower frequency). Another one is to not call snmp_inc_sysuptime() or
+snmp_add_sysuptime(), and to define the SNMP_GET_SYSUPTIME(sysuptime) macro.
+This one is undefined by default in mib2.c. SNMP_GET_SYSUPTIME is called inside
+snmp_get_sysuptime(u32_t *value), and enable to change "sysuptime" value only
+when it's queried (any function which need "sysuptime" have to call
+snmp_get_sysuptime).
+
+
+3 Private MIBs
+==============
+
+If want to extend the agent with your own private MIB you'll need to
+add the following define to your local lwipopts.h:
+
+#define SNMP_PRIVATE_MIB        1
+
+You must provide the private_mib.h and associated files yourself.
+Note we don't have a "MIB compiler" that generates C source from a MIB,
+so you're required to do some serious coding if you enable this!
+
+Note the lwIP enterprise ID (26381) is assigned to the lwIP project,
+ALL OBJECT IDENTIFIERS LIVING UNDER THIS ID ARE ASSIGNED BY THE lwIP
+MAINTAINERS!
+
+If you need to create your own private MIB you'll need
+to apply for your own enterprise ID with IANA: http://www.iana.org/numbers.html 
+
+You can set it by passing a struct snmp_obj_id to the agent
+using snmp_set_sysobjid(&my_object_id), just before snmp_init().
+
+Note the object identifiers for thes MIB-2 and your private MIB
+tree must be kept in sorted ascending (lexicographical) order.
+This to ensure correct getnext operation.
+
+An example for a private MIB is part of the "minimal Unix" project:
+contrib/ports/unix/proj/minimal/lwip_prvmib.c
+
+The next chapter gives a more detailed description of the
+MIB-2 tree and the optional private MIB.
+
+4 The Gory Details
+==================
+
+4.0 Object identifiers and the MIB tree.
+
+We have three distinct parts for all object identifiers:
+
+The prefix
+  .iso.org.dod.internet
+
+the middle part 
+  .mgmt.mib-2.ip.ipNetToMediaTable.ipNetToMediaEntry.ipNetToMediaPhysAddress
+
+and the index part
+  .1.192.168.0.1
+
+Objects located above the .internet hierarchy aren't supported.
+Currently only the .mgmt sub-tree is available and
+when the SNMP_PRIVATE_MIB is enabled the .private tree
+becomes available too.
+
+Object identifiers from incoming requests are checked
+for a matching prefix, middle part and index part
+or are expanded(*) for GetNext requests with short
+or inexisting names in the request.
+(* we call this "expansion" but this also
+resembles the "auto-completion" operation)
+
+The middle part is usually located in ROM (const)
+to preserve precious RAM on small microcontrollers.
+However RAM location is possible for an dynamically
+changing private tree.
+
+The index part is handled by functions which in
+turn use dynamically allocated index trees from RAM.
+These trees are updated by e.g. the etharp code
+when new entries are made or removed form the ARP cache.
+
+/** @todo more gory details */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/doc/sys_arch.txt b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/doc/sys_arch.txt
new file mode 100644
index 0000000..bc68096
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/doc/sys_arch.txt
@@ -0,0 +1,226 @@
+sys_arch interface for lwIP 0.6++
+
+Author: Adam Dunkels
+
+The operating system emulation layer provides a common interface
+between the lwIP code and the underlying operating system kernel. The
+general idea is that porting lwIP to new architectures requires only
+small changes to a few header files and a new sys_arch
+implementation. It is also possible to do a sys_arch implementation
+that does not rely on any underlying operating system.
+
+The sys_arch provides semaphores and mailboxes to lwIP. For the full
+lwIP functionality, multiple threads support can be implemented in the
+sys_arch, but this is not required for the basic lwIP
+functionality. Previous versions of lwIP required the sys_arch to
+implement timer scheduling as well but as of lwIP 0.5 this is
+implemented in a higher layer.
+
+In addition to the source file providing the functionality of sys_arch,
+the OS emulation layer must provide several header files defining
+macros used throughout lwip.  The files required and the macros they
+must define are listed below the sys_arch description.
+
+Semaphores can be either counting or binary - lwIP works with both
+kinds. Mailboxes are used for message passing and can be implemented
+either as a queue which allows multiple messages to be posted to a
+mailbox, or as a rendez-vous point where only one message can be
+posted at a time. lwIP works with both kinds, but the former type will
+be more efficient. A message in a mailbox is just a pointer, nothing
+more. 
+
+Semaphores are represented by the type "sys_sem_t" which is typedef'd
+in the sys_arch.h file. Mailboxes are equivalently represented by the
+type "sys_mbox_t". lwIP does not place any restrictions on how
+sys_sem_t or sys_mbox_t are represented internally.
+
+The following functions must be implemented by the sys_arch:
+
+- void sys_init(void)
+
+  Is called to initialize the sys_arch layer.
+
+- sys_sem_t sys_sem_new(u8_t count)
+
+  Creates and returns a new semaphore. The "count" argument specifies
+  the initial state of the semaphore.
+
+- void sys_sem_free(sys_sem_t sem)
+
+  Deallocates a semaphore.
+
+- void sys_sem_signal(sys_sem_t sem)
+
+  Signals a semaphore.
+
+- u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout)
+
+  Blocks the thread while waiting for the semaphore to be
+  signaled. If the "timeout" argument is non-zero, the thread should
+  only be blocked for the specified time (measured in
+  milliseconds). If the "timeout" argument is zero, the thread should be
+  blocked until the semaphore is signalled.
+
+  If the timeout argument is non-zero, the return value is the number of
+  milliseconds spent waiting for the semaphore to be signaled. If the
+  semaphore wasn't signaled within the specified time, the return value is
+  SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
+  (i.e., it was already signaled), the function may return zero.
+
+  Notice that lwIP implements a function with a similar name,
+  sys_sem_wait(), that uses the sys_arch_sem_wait() function.
+
+- sys_mbox_t sys_mbox_new(int size)
+
+  Creates an empty mailbox for maximum "size" elements. Elements stored
+  in mailboxes are pointers. You have to define macros "_MBOX_SIZE"
+  in your lwipopts.h, or ignore this parameter in your implementation
+  and use a default size.
+
+- void sys_mbox_free(sys_mbox_t mbox)
+
+  Deallocates a mailbox. If there are messages still present in the
+  mailbox when the mailbox is deallocated, it is an indication of a
+  programming error in lwIP and the developer should be notified.
+
+- void sys_mbox_post(sys_mbox_t mbox, void *msg)
+
+  Posts the "msg" to the mailbox. This function have to block until
+  the "msg" is really posted.
+
+- err_t sys_mbox_trypost(sys_mbox_t mbox, void *msg)
+
+  Try to post the "msg" to the mailbox. Returns ERR_MEM if this one
+  is full, else, ERR_OK if the "msg" is posted.
+
+- u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout)
+
+  Blocks the thread until a message arrives in the mailbox, but does
+  not block the thread longer than "timeout" milliseconds (similar to
+  the sys_arch_sem_wait() function). If "timeout" is 0, the thread should
+  be blocked until a message arrives. The "msg" argument is a result
+  parameter that is set by the function (i.e., by doing "*msg =
+  ptr"). The "msg" parameter maybe NULL to indicate that the message
+  should be dropped.
+
+  The return values are the same as for the sys_arch_sem_wait() function:
+  Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a
+  timeout.
+
+  Note that a function with a similar name, sys_mbox_fetch(), is
+  implemented by lwIP. 
+
+- u32_t sys_arch_mbox_tryfetch(sys_mbox_t mbox, void **msg)
+
+  This is similar to sys_arch_mbox_fetch, however if a message is not
+  present in the mailbox, it immediately returns with the code
+  SYS_MBOX_EMPTY. On success 0 is returned.
+
+  To allow for efficient implementations, this can be defined as a
+  function-like macro in sys_arch.h instead of a normal function. For
+  example, a naive implementation could be:
+    #define sys_arch_mbox_tryfetch(mbox,msg) \
+      sys_arch_mbox_fetch(mbox,msg,1)
+  although this would introduce unnecessary delays.
+  
+- struct sys_timeouts *sys_arch_timeouts(void)
+
+  Returns a pointer to the per-thread sys_timeouts structure. In lwIP,
+  each thread has a list of timeouts which is repressented as a linked
+  list of sys_timeout structures. The sys_timeouts structure holds a
+  pointer to a linked list of timeouts. This function is called by
+  the lwIP timeout scheduler and must not return a NULL value. 
+
+  In a single thread sys_arch implementation, this function will
+  simply return a pointer to a global sys_timeouts variable stored in
+  the sys_arch module.
+  
+If threads are supported by the underlying operating system and if
+such functionality is needed in lwIP, the following function will have
+to be implemented as well:
+
+- sys_thread_t sys_thread_new(char *name, void (* thread)(void *arg), void *arg, int stacksize, int prio)
+
+  Starts a new thread named "name" with priority "prio" that will begin its
+  execution in the function "thread()". The "arg" argument will be passed as an
+  argument to the thread() function. The stack size to used for this thread is
+  the "stacksize" parameter. The id of the new thread is returned. Both the id
+  and the priority are system dependent.
+
+- sys_prot_t sys_arch_protect(void)
+
+  This optional function does a "fast" critical region protection and returns
+  the previous protection level. This function is only called during very short
+  critical regions. An embedded system which supports ISR-based drivers might
+  want to implement this function by disabling interrupts. Task-based systems
+  might want to implement this by using a mutex or disabling tasking. This
+  function should support recursive calls from the same task or interrupt. In
+  other words, sys_arch_protect() could be called while already protected. In
+  that case the return value indicates that it is already protected.
+
+  sys_arch_protect() is only required if your port is supporting an operating
+  system.
+
+- void sys_arch_unprotect(sys_prot_t pval)
+
+  This optional function does a "fast" set of critical region protection to the
+  value specified by pval. See the documentation for sys_arch_protect() for
+  more information. This function is only required if your port is supporting
+  an operating system.
+
+Note:
+
+Be carefull with using mem_malloc() in sys_arch. When malloc() refers to
+mem_malloc() you can run into a circular function call problem. In mem.c
+mem_init() tries to allcate a semaphore using mem_malloc, which of course
+can't be performed when sys_arch uses mem_malloc.
+
+-------------------------------------------------------------------------------
+Additional files required for the "OS support" emulation layer:
+-------------------------------------------------------------------------------
+
+cc.h       - Architecture environment, some compiler specific, some
+             environment specific (probably should move env stuff 
+             to sys_arch.h.)
+
+  Typedefs for the types used by lwip -
+    u8_t, s8_t, u16_t, s16_t, u32_t, s32_t, mem_ptr_t
+
+  Compiler hints for packing lwip's structures -
+    PACK_STRUCT_FIELD(x)
+    PACK_STRUCT_STRUCT
+    PACK_STRUCT_BEGIN
+    PACK_STRUCT_END
+
+  Platform specific diagnostic output -
+    LWIP_PLATFORM_DIAG(x)    - non-fatal, print a message.
+    LWIP_PLATFORM_ASSERT(x)  - fatal, print message and abandon execution.
+
+  "lightweight" synchronization mechanisms -
+    SYS_ARCH_DECL_PROTECT(x) - declare a protection state variable.
+    SYS_ARCH_PROTECT(x)      - enter protection mode.
+    SYS_ARCH_UNPROTECT(x)    - leave protection mode.
+
+  If the compiler does not provide memset() this file must include a
+  definition of it, or include a file which defines it.
+
+  This file must either include a system-local  which defines
+  the standard *nix error codes, or it should #define LWIP_PROVIDE_ERRNO
+  to make lwip/arch.h define the codes which are used throughout.
+
+
+perf.h     - Architecture specific performance measurement.
+  Measurement calls made throughout lwip, these can be defined to nothing.
+    PERF_START               - start measuring something.
+    PERF_STOP(x)             - stop measuring something, and record the result.
+
+sys_arch.h - Tied to sys_arch.c
+
+  Arch dependent types for the following objects:
+    sys_sem_t, sys_mbox_t, sys_thread_t,
+  And, optionally:
+    sys_prot_t
+
+  Defines to set vars of sys_mbox_t and sys_sem_t to NULL.
+    SYS_MBOX_NULL NULL
+    SYS_SEM_NULL NULL
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/FILES b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/FILES
new file mode 100644
index 0000000..10115a7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/FILES
@@ -0,0 +1,13 @@
+api/      - The code for the high-level wrapper API. Not needed if
+            you use the lowel-level call-back/raw API.
+
+core/     - The core of the TPC/IP stack; protocol implementations,
+            memory and buffer management, and the low-level raw API.
+
+include/  - lwIP include files.
+
+netif/    - Generic network interface device drivers are kept here,
+            as well as the ARP module.
+
+For more information on the various subdirectories, check the FILES
+file in each directory.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/api_lib.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/api_lib.c
new file mode 100644
index 0000000..36d52f9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/api_lib.c
@@ -0,0 +1,570 @@
+/**
+ * @file
+ * Sequential API External module
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* This is the part of the API that is linked with
+   the application */
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/api.h"
+#include "lwip/tcpip.h"
+#include "lwip/memp.h"
+
+#include "lwip/ip.h"
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include 
+
+/**
+ * Create a new netconn (of a specific type) that has a callback function.
+ * The corresponding pcb is also created.
+ *
+ * @param t the type of 'connection' to create (@see enum netconn_type)
+ * @param proto the IP protocol for RAW IP pcbs
+ * @param callback a function to call on status changes (RX available, TX'ed)
+ * @return a newly allocated struct netconn or
+ *         NULL on memory error
+ */
+struct netconn*
+netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto, netconn_callback callback)
+{
+  struct netconn *conn;
+  struct api_msg msg;
+
+  conn = netconn_alloc(t, callback);
+  if (conn != NULL ) {
+    msg.function = do_newconn;
+    msg.msg.msg.n.proto = proto;
+    msg.msg.conn = conn;
+    TCPIP_APIMSG(&msg);
+
+    if (conn->err != ERR_OK) {
+      LWIP_ASSERT("freeing conn without freeing pcb", conn->pcb.tcp == NULL);
+      LWIP_ASSERT("conn has no op_completed", conn->op_completed != SYS_SEM_NULL);
+      LWIP_ASSERT("conn has no recvmbox", conn->recvmbox != SYS_MBOX_NULL);
+      LWIP_ASSERT("conn->acceptmbox shouldn't exist", conn->acceptmbox == SYS_MBOX_NULL);
+      sys_sem_free(conn->op_completed);
+      sys_mbox_free(conn->recvmbox);
+      memp_free(MEMP_NETCONN, conn);
+      return NULL;
+    }
+  }
+  return conn;
+}
+
+/**
+ * Close a netconn 'connection' and free its resources.
+ * UDP and RAW connection are completely closed, TCP pcbs might still be in a waitstate
+ * after this returns.
+ *
+ * @param conn the netconn to delete
+ * @return ERR_OK if the connection was deleted
+ */
+err_t
+netconn_delete(struct netconn *conn)
+{
+  struct api_msg msg;
+
+  /* No ASSERT here because possible to get a (conn == NULL) if we got an accept error */
+  if (conn == NULL) {
+    return ERR_OK;
+  }
+
+  msg.function = do_delconn;
+  msg.msg.conn = conn;
+  tcpip_apimsg(&msg);
+
+  conn->pcb.tcp = NULL;
+  netconn_free(conn);
+
+  return ERR_OK;
+}
+
+/**
+ * Get the type of a netconn (as enum netconn_type).
+ *
+ * @param conn the netconn of which to get the type
+ * @return the netconn_type of conn
+ */
+enum netconn_type
+netconn_type(struct netconn *conn)
+{
+  LWIP_ERROR("netconn_type: invalid conn", (conn != NULL), return NETCONN_INVALID;);
+  return conn->type;
+}
+
+/**
+ * Get the local or remote IP address and port of a netconn.
+ * For RAW netconns, this returns the protocol instead of a port!
+ *
+ * @param conn the netconn to query
+ * @param addr a pointer to which to save the IP address
+ * @param port a pointer to which to save the port (or protocol for RAW)
+ * @param local 1 to get the local IP address, 0 to get the remote one
+ * @return ERR_CONN for invalid connections
+ *         ERR_OK if the information was retrieved
+ */
+err_t
+netconn_getaddr(struct netconn *conn, struct ip_addr *addr, u16_t *port, u8_t local)
+{
+  struct api_msg msg;
+
+  LWIP_ERROR("netconn_getaddr: invalid conn", (conn != NULL), return ERR_ARG;);
+  LWIP_ERROR("netconn_getaddr: invalid addr", (addr != NULL), return ERR_ARG;);
+  LWIP_ERROR("netconn_getaddr: invalid port", (port != NULL), return ERR_ARG;);
+
+  msg.function = do_getaddr;
+  msg.msg.conn = conn;
+  msg.msg.msg.ad.ipaddr = addr;
+  msg.msg.msg.ad.port = port;
+  msg.msg.msg.ad.local = local;
+  TCPIP_APIMSG(&msg);
+
+  return conn->err;
+}
+
+/**
+ * Bind a netconn to a specific local IP address and port.
+ * Binding one netconn twice might not always be checked correctly!
+ *
+ * @param conn the netconn to bind
+ * @param addr the local IP address to bind the netconn to (use IP_ADDR_ANY
+ *             to bind to all addresses)
+ * @param port the local port to bind the netconn to (not used for RAW)
+ * @return ERR_OK if bound, any other err_t on failure
+ */
+err_t
+netconn_bind(struct netconn *conn, struct ip_addr *addr, u16_t port)
+{
+  struct api_msg msg;
+
+  LWIP_ERROR("netconn_bind: invalid conn", (conn != NULL), return ERR_ARG;);
+
+  msg.function = do_bind;
+  msg.msg.conn = conn;
+  msg.msg.msg.bc.ipaddr = addr;
+  msg.msg.msg.bc.port = port;
+  TCPIP_APIMSG(&msg);
+  return conn->err;
+}
+
+/**
+ * Connect a netconn to a specific remote IP address and port.
+ *
+ * @param conn the netconn to connect
+ * @param addr the remote IP address to connect to
+ * @param port the remote port to connect to (no used for RAW)
+ * @return ERR_OK if connected, return value of tcp_/udp_/raw_connect otherwise
+ */
+err_t
+netconn_connect(struct netconn *conn, struct ip_addr *addr, u16_t port)
+{
+  struct api_msg msg;
+
+  LWIP_ERROR("netconn_connect: invalid conn", (conn != NULL), return ERR_ARG;);
+
+  msg.function = do_connect;
+  msg.msg.conn = conn;
+  msg.msg.msg.bc.ipaddr = addr;
+  msg.msg.msg.bc.port = port;
+  /* This is the only function which need to not block tcpip_thread */
+  tcpip_apimsg(&msg);
+  return conn->err;
+}
+
+/**
+ * Disconnect a netconn from its current peer (only valid for UDP netconns).
+ *
+ * @param conn the netconn to disconnect
+ * @return TODO: return value is not set here...
+ */
+err_t
+netconn_disconnect(struct netconn *conn)
+{
+  struct api_msg msg;
+
+  LWIP_ERROR("netconn_disconnect: invalid conn", (conn != NULL), return ERR_ARG;);
+
+  msg.function = do_disconnect;
+  msg.msg.conn = conn;
+  TCPIP_APIMSG(&msg);
+  return conn->err;
+}
+
+/**
+ * Set a TCP netconn into listen mode
+ *
+ * @param conn the tcp netconn to set to listen mode
+ * @param backlog the listen backlog, only used if TCP_LISTEN_BACKLOG==1
+ * @return ERR_OK if the netconn was set to listen (UDP and RAW netconns
+ *         don't return any error (yet?))
+ */
+err_t
+netconn_listen_with_backlog(struct netconn *conn, u8_t backlog)
+{
+  struct api_msg msg;
+
+  /* This does no harm. If TCP_LISTEN_BACKLOG is off, backlog is unused. */
+  LWIP_UNUSED_ARG(backlog);
+
+  LWIP_ERROR("netconn_listen: invalid conn", (conn != NULL), return ERR_ARG;);
+
+  msg.function = do_listen;
+  msg.msg.conn = conn;
+#if TCP_LISTEN_BACKLOG
+  msg.msg.msg.lb.backlog = backlog;
+#endif /* TCP_LISTEN_BACKLOG */
+  TCPIP_APIMSG(&msg);
+  return conn->err;
+}
+
+/**
+ * Accept a new connection on a TCP listening netconn.
+ *
+ * @param conn the TCP listen netconn
+ * @return the newly accepted netconn or NULL on timeout
+ */
+struct netconn *
+netconn_accept(struct netconn *conn)
+{
+  struct netconn *newconn;
+
+  LWIP_ERROR("netconn_accept: invalid conn",       (conn != NULL),                      return NULL;);
+  LWIP_ERROR("netconn_accept: invalid acceptmbox", (conn->acceptmbox != SYS_MBOX_NULL), return NULL;);
+
+#if LWIP_SO_RCVTIMEO
+  if (sys_arch_mbox_fetch(conn->acceptmbox, (void *)&newconn, conn->recv_timeout) == SYS_ARCH_TIMEOUT) {
+    newconn = NULL;
+  } else
+#else
+  sys_arch_mbox_fetch(conn->acceptmbox, (void *)&newconn, 0);
+#endif /* LWIP_SO_RCVTIMEO*/
+  {
+    /* Register event with callback */
+    API_EVENT(conn, NETCONN_EVT_RCVMINUS, 0);
+
+#if TCP_LISTEN_BACKLOG
+    if (newconn != NULL) {
+      /* Let the stack know that we have accepted the connection. */
+      struct api_msg msg;
+      msg.function = do_recv;
+      msg.msg.conn = conn;
+      TCPIP_APIMSG(&msg);
+    }
+#endif /* TCP_LISTEN_BACKLOG */
+  }
+
+  return newconn;
+}
+
+/**
+ * Receive data (in form of a netbuf containing a packet buffer) from a netconn
+ *
+ * @param conn the netconn from which to receive data
+ * @return a new netbuf containing received data or NULL on memory error or timeout
+ */
+struct netbuf *
+netconn_recv(struct netconn *conn)
+{
+  struct api_msg msg;
+  struct netbuf *buf = NULL;
+  struct pbuf *p;
+  u16_t len;
+
+  LWIP_ERROR("netconn_recv: invalid conn",  (conn != NULL), return NULL;);
+
+  if (conn->recvmbox == SYS_MBOX_NULL) {
+    /* @todo: should calling netconn_recv on a TCP listen conn be fatal (ERR_CONN)?? */
+    /* TCP listen conns don't have a recvmbox! */
+    conn->err = ERR_CONN;
+    return NULL;
+  }
+
+  if (ERR_IS_FATAL(conn->err)) {
+    return NULL;
+  }
+
+  if (conn->type == NETCONN_TCP) {
+#if LWIP_TCP
+    if (conn->state == NETCONN_LISTEN) {
+      /* @todo: should calling netconn_recv on a TCP listen conn be fatal?? */
+      conn->err = ERR_CONN;
+      return NULL;
+    }
+
+    buf = memp_malloc(MEMP_NETBUF);
+
+    if (buf == NULL) {
+      conn->err = ERR_MEM;
+      return NULL;
+    }
+
+#if LWIP_SO_RCVTIMEO
+    if (sys_arch_mbox_fetch(conn->recvmbox, (void *)&p, conn->recv_timeout)==SYS_ARCH_TIMEOUT) {
+      conn->err = ERR_TIMEOUT;
+      p = NULL;
+    }
+#else
+    sys_arch_mbox_fetch(conn->recvmbox, (void *)&p, 0);
+#endif /* LWIP_SO_RCVTIMEO*/
+
+    if (p != NULL) {
+      len = p->tot_len;
+      SYS_ARCH_DEC(conn->recv_avail, len);
+    } else {
+      len = 0;
+    }
+
+    /* Register event with callback */
+    API_EVENT(conn, NETCONN_EVT_RCVMINUS, len);
+
+    /* If we are closed, we indicate that we no longer wish to use the socket */
+    if (p == NULL) {
+      memp_free(MEMP_NETBUF, buf);
+      /* Avoid to lose any previous error code */
+      if (conn->err == ERR_OK) {
+        conn->err = ERR_CLSD;
+      }
+      return NULL;
+    }
+
+    buf->p = p;
+    buf->ptr = p;
+    buf->port = 0;
+    buf->addr = NULL;
+
+    /* Let the stack know that we have taken the data. */
+    msg.function = do_recv;
+    msg.msg.conn = conn;
+    if (buf != NULL) {
+      msg.msg.msg.r.len = buf->p->tot_len;
+    } else {
+      msg.msg.msg.r.len = 1;
+    }
+    TCPIP_APIMSG(&msg);
+#endif /* LWIP_TCP */
+  } else {
+#if (LWIP_UDP || LWIP_RAW)
+#if LWIP_SO_RCVTIMEO
+    if (sys_arch_mbox_fetch(conn->recvmbox, (void *)&buf, conn->recv_timeout)==SYS_ARCH_TIMEOUT) {
+      buf = NULL;
+    }
+#else
+    sys_arch_mbox_fetch(conn->recvmbox, (void *)&buf, 0);
+#endif /* LWIP_SO_RCVTIMEO*/
+    if (buf!=NULL) {
+      SYS_ARCH_DEC(conn->recv_avail, buf->p->tot_len);
+      /* Register event with callback */
+      API_EVENT(conn, NETCONN_EVT_RCVMINUS, buf->p->tot_len);
+    }
+#endif /* (LWIP_UDP || LWIP_RAW) */
+  }
+
+  LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_recv: received %p (err %d)\n", (void *)buf, conn->err));
+
+  return buf;
+}
+
+/**
+ * Send data (in form of a netbuf) to a specific remote IP address and port.
+ * Only to be used for UDP and RAW netconns (not TCP).
+ *
+ * @param conn the netconn over which to send data
+ * @param buf a netbuf containing the data to send
+ * @param addr the remote IP address to which to send the data
+ * @param port the remote port to which to send the data
+ * @return ERR_OK if data was sent, any other err_t on error
+ */
+err_t
+netconn_sendto(struct netconn *conn, struct netbuf *buf, struct ip_addr *addr, u16_t port)
+{
+  if (buf != NULL) {
+    buf->addr = addr;
+    buf->port = port;
+    return netconn_send(conn, buf);
+  }
+  return ERR_VAL;
+}
+
+/**
+ * Send data over a UDP or RAW netconn (that is already connected).
+ *
+ * @param conn the UDP or RAW netconn over which to send data
+ * @param buf a netbuf containing the data to send
+ * @return ERR_OK if data was sent, any other err_t on error
+ */
+err_t
+netconn_send(struct netconn *conn, struct netbuf *buf)
+{
+  struct api_msg msg;
+
+  LWIP_ERROR("netconn_send: invalid conn",  (conn != NULL), return ERR_ARG;);
+
+  LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_send: sending %d bytes\n", buf->p->tot_len));
+  msg.function = do_send;
+  msg.msg.conn = conn;
+  msg.msg.msg.b = buf;
+  TCPIP_APIMSG(&msg);
+  return conn->err;
+}
+
+/**
+ * Send data over a TCP netconn.
+ *
+ * @param conn the TCP netconn over which to send data
+ * @param dataptr pointer to the application buffer that contains the data to send
+ * @param size size of the application data to send
+ * @param apiflags combination of following flags :
+ * - NETCONN_COPY (0x01) data will be copied into memory belonging to the stack
+ * - NETCONN_MORE (0x02) for TCP connection, PSH flag will be set on last segment sent
+ * @return ERR_OK if data was sent, any other err_t on error
+ */
+err_t
+netconn_write(struct netconn *conn, const void *dataptr, int size, u8_t apiflags)
+{
+  struct api_msg msg;
+
+  LWIP_ERROR("netconn_write: invalid conn",  (conn != NULL), return ERR_ARG;);
+  LWIP_ERROR("netconn_write: invalid conn->type",  (conn->type == NETCONN_TCP), return ERR_VAL;);
+
+  msg.function = do_write;
+  msg.msg.conn = conn;
+  msg.msg.msg.w.dataptr = dataptr;
+  msg.msg.msg.w.apiflags = apiflags;
+  msg.msg.msg.w.len = size;
+  /* For locking the core: this _can_ be delayed on low memory/low send buffer,
+     but if it is, this is done inside api_msg.c:do_write(), so we can use the
+     non-blocking version here. */
+  TCPIP_APIMSG(&msg);
+  return conn->err;
+}
+
+/**
+ * Close a TCP netconn (doesn't delete it).
+ *
+ * @param conn the TCP netconn to close
+ * @return ERR_OK if the netconn was closed, any other err_t on error
+ */
+err_t
+netconn_close(struct netconn *conn)
+{
+  struct api_msg msg;
+
+  LWIP_ERROR("netconn_close: invalid conn",  (conn != NULL), return ERR_ARG;);
+
+  msg.function = do_close;
+  msg.msg.conn = conn;
+  tcpip_apimsg(&msg);
+  return conn->err;
+}
+
+#if LWIP_IGMP
+/**
+ * Join multicast groups for UDP netconns.
+ *
+ * @param conn the UDP netconn for which to change multicast addresses
+ * @param multiaddr IP address of the multicast group to join or leave
+ * @param interface the IP address of the network interface on which to send
+ *                  the igmp message
+ * @param join_or_leave flag whether to send a join- or leave-message
+ * @return ERR_OK if the action was taken, any err_t on error
+ */
+err_t
+netconn_join_leave_group(struct netconn *conn,
+                         struct ip_addr *multiaddr,
+                         struct ip_addr *interface,
+                         enum netconn_igmp join_or_leave)
+{
+  struct api_msg msg;
+
+  LWIP_ERROR("netconn_join_leave_group: invalid conn",  (conn != NULL), return ERR_ARG;);
+
+  msg.function = do_join_leave_group;
+  msg.msg.conn = conn;
+  msg.msg.msg.jl.multiaddr = multiaddr;
+  msg.msg.msg.jl.interface = interface;
+  msg.msg.msg.jl.join_or_leave = join_or_leave;
+  TCPIP_APIMSG(&msg);
+  return conn->err;
+}
+#endif /* LWIP_IGMP */
+
+#if LWIP_DNS
+/**
+ * Execute a DNS query, only one IP address is returned
+ *
+ * @param name a string representation of the DNS host name to query
+ * @param addr a preallocated struct ip_addr where to store the resolved IP address
+ * @return ERR_OK: resolving succeeded
+ *         ERR_MEM: memory error, try again later
+ *         ERR_ARG: dns client not initialized or invalid hostname
+ *         ERR_VAL: dns server response was invalid
+ */
+err_t
+netconn_gethostbyname(const char *name, struct ip_addr *addr)
+{
+  struct dns_api_msg msg;
+  err_t err;
+  sys_sem_t sem;
+
+  LWIP_ERROR("netconn_gethostbyname: invalid name", (name != NULL), return ERR_ARG;);
+  LWIP_ERROR("netconn_gethostbyname: invalid addr", (addr != NULL), return ERR_ARG;);
+
+  sem = sys_sem_new(0);
+  if (sem == SYS_SEM_NULL) {
+    return ERR_MEM;
+  }
+
+  msg.name = name;
+  msg.addr = addr;
+  msg.err = &err;
+  msg.sem = sem;
+
+  tcpip_callback(do_gethostbyname, &msg);
+  sys_sem_wait(sem);
+  sys_sem_free(sem);
+
+  return err;
+}
+#endif /* LWIP_DNS*/
+
+#endif /* LWIP_NETCONN */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/api_msg.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/api_msg.c
new file mode 100644
index 0000000..f08177c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/api_msg.c
@@ -0,0 +1,1202 @@
+/**
+ * @file
+ * Sequential API Internal module
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/api_msg.h"
+
+#include "lwip/ip.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+#include "lwip/raw.h"
+
+#include "lwip/memp.h"
+#include "lwip/tcpip.h"
+#include "lwip/igmp.h"
+#include "lwip/dns.h"
+
+/* forward declarations */
+#if LWIP_TCP
+static err_t do_writemore(struct netconn *conn);
+static void do_close_internal(struct netconn *conn);
+#endif
+
+#if LWIP_RAW
+/**
+ * Receive callback function for RAW netconns.
+ * Doesn't 'eat' the packet, only references it and sends it to
+ * conn->recvmbox
+ *
+ * @see raw.h (struct raw_pcb.recv) for parameters and return value
+ */
+static u8_t
+recv_raw(void *arg, struct raw_pcb *pcb, struct pbuf *p,
+    struct ip_addr *addr)
+{
+  struct pbuf *q;
+  struct netbuf *buf;
+  struct netconn *conn;
+#if LWIP_SO_RCVBUF
+  int recv_avail;
+#endif /* LWIP_SO_RCVBUF */
+
+  LWIP_UNUSED_ARG(addr);
+  conn = arg;
+
+#if LWIP_SO_RCVBUF
+  SYS_ARCH_GET(conn->recv_avail, recv_avail);
+  if ((conn != NULL) && (conn->recvmbox != SYS_MBOX_NULL) &&
+      ((recv_avail + (int)(p->tot_len)) <= conn->recv_bufsize)) {
+#else  /* LWIP_SO_RCVBUF */
+  if ((conn != NULL) && (conn->recvmbox != SYS_MBOX_NULL)) {
+#endif /* LWIP_SO_RCVBUF */
+    /* copy the whole packet into new pbufs */
+    q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
+    if(q != NULL) {
+      if (pbuf_copy(q, p) != ERR_OK) {
+        pbuf_free(q);
+        q = NULL;
+      }
+    }
+
+    if(q != NULL) {
+      buf = memp_malloc(MEMP_NETBUF);
+      if (buf == NULL) {
+        pbuf_free(q);
+        return 0;
+      }
+
+      buf->p = q;
+      buf->ptr = q;
+      buf->addr = &(((struct ip_hdr*)(q->payload))->src);
+      buf->port = pcb->protocol;
+
+      SYS_ARCH_INC(conn->recv_avail, q->tot_len);
+      /* Register event with callback */
+      API_EVENT(conn, NETCONN_EVT_RCVPLUS, q->tot_len);
+      if (sys_mbox_trypost(conn->recvmbox, buf) != ERR_OK) {
+        netbuf_delete(buf);
+      }
+    }
+  }
+
+  return 0; /* do not eat the packet */
+}
+#endif /* LWIP_RAW*/
+
+#if LWIP_UDP
+/**
+ * Receive callback function for UDP netconns.
+ * Posts the packet to conn->recvmbox or deletes it on memory error.
+ *
+ * @see udp.h (struct udp_pcb.recv) for parameters
+ */
+static void
+recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p,
+   struct ip_addr *addr, u16_t port)
+{
+  struct netbuf *buf;
+  struct netconn *conn;
+#if LWIP_SO_RCVBUF
+  int recv_avail;
+#endif /* LWIP_SO_RCVBUF */
+
+  LWIP_UNUSED_ARG(pcb); /* only used for asserts... */
+  LWIP_ASSERT("recv_udp must have a pcb argument", pcb != NULL);
+  LWIP_ASSERT("recv_udp must have an argument", arg != NULL);
+  conn = arg;
+  LWIP_ASSERT("recv_udp: recv for wrong pcb!", conn->pcb.udp == pcb);
+
+#if LWIP_SO_RCVBUF
+  SYS_ARCH_GET(conn->recv_avail, recv_avail);
+  if ((conn == NULL) || (conn->recvmbox == SYS_MBOX_NULL) ||
+      ((recv_avail + (int)(p->tot_len)) > conn->recv_bufsize)) {
+#else  /* LWIP_SO_RCVBUF */
+  if ((conn == NULL) || (conn->recvmbox == SYS_MBOX_NULL)) {
+#endif /* LWIP_SO_RCVBUF */
+    pbuf_free(p);
+    return;
+  }
+
+  buf = memp_malloc(MEMP_NETBUF);
+  if (buf == NULL) {
+    pbuf_free(p);
+    return;
+  } else {
+    buf->p = p;
+    buf->ptr = p;
+    buf->addr = addr;
+    buf->port = port;
+  }
+
+  SYS_ARCH_INC(conn->recv_avail, p->tot_len);
+  /* Register event with callback */
+  API_EVENT(conn, NETCONN_EVT_RCVPLUS, p->tot_len);
+  if (sys_mbox_trypost(conn->recvmbox, buf) != ERR_OK) {
+    netbuf_delete(buf);
+    return;
+  }
+}
+#endif /* LWIP_UDP */
+
+#if LWIP_TCP
+/**
+ * Receive callback function for TCP netconns.
+ * Posts the packet to conn->recvmbox, but doesn't delete it on errors.
+ *
+ * @see tcp.h (struct tcp_pcb.recv) for parameters and return value
+ */
+static err_t
+recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
+{
+  struct netconn *conn;
+  u16_t len;
+
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_ASSERT("recv_tcp must have a pcb argument", pcb != NULL);
+  LWIP_ASSERT("recv_tcp must have an argument", arg != NULL);
+  conn = arg;
+  LWIP_ASSERT("recv_tcp: recv for wrong pcb!", conn->pcb.tcp == pcb);
+
+  if ((conn == NULL) || (conn->recvmbox == SYS_MBOX_NULL)) {
+    return ERR_VAL;
+  }
+
+  conn->err = err;
+  if (p != NULL) {
+    len = p->tot_len;
+    SYS_ARCH_INC(conn->recv_avail, len);
+  } else {
+    len = 0;
+  }
+  /* Register event with callback */
+  API_EVENT(conn, NETCONN_EVT_RCVPLUS, len);
+  if (sys_mbox_trypost(conn->recvmbox, p) != ERR_OK) {
+    return ERR_MEM;
+  }
+
+  return ERR_OK;
+}
+
+/**
+ * Poll callback function for TCP netconns.
+ * Wakes up an application thread that waits for a connection to close
+ * or data to be sent. The application thread then takes the
+ * appropriate action to go on.
+ *
+ * Signals the conn->sem.
+ * netconn_close waits for conn->sem if closing failed.
+ *
+ * @see tcp.h (struct tcp_pcb.poll) for parameters and return value
+ */
+static err_t
+poll_tcp(void *arg, struct tcp_pcb *pcb)
+{
+  struct netconn *conn = arg;
+
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_ASSERT("conn != NULL", (conn != NULL));
+
+  if (conn->state == NETCONN_WRITE) {
+    do_writemore(conn);
+  } else if (conn->state == NETCONN_CLOSE) {
+    do_close_internal(conn);
+  }
+
+  return ERR_OK;
+}
+
+/**
+ * Sent callback function for TCP netconns.
+ * Signals the conn->sem and calls API_EVENT.
+ * netconn_write waits for conn->sem if send buffer is low.
+ *
+ * @see tcp.h (struct tcp_pcb.sent) for parameters and return value
+ */
+static err_t
+sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len)
+{
+  struct netconn *conn = arg;
+
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_ASSERT("conn != NULL", (conn != NULL));
+
+  if (conn->state == NETCONN_WRITE) {
+    LWIP_ASSERT("conn->pcb.tcp != NULL", conn->pcb.tcp != NULL);
+    do_writemore(conn);
+  } else if (conn->state == NETCONN_CLOSE) {
+    do_close_internal(conn);
+  }
+
+  if (conn) {
+    if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT)) {
+      API_EVENT(conn, NETCONN_EVT_SENDPLUS, len);
+    }
+  }
+
+  return ERR_OK;
+}
+
+/**
+ * Error callback function for TCP netconns.
+ * Signals conn->sem, posts to all conn mboxes and calls API_EVENT.
+ * The application thread has then to decide what to do.
+ *
+ * @see tcp.h (struct tcp_pcb.err) for parameters
+ */
+static void
+err_tcp(void *arg, err_t err)
+{
+  struct netconn *conn;
+
+  conn = arg;
+  LWIP_ASSERT("conn != NULL", (conn != NULL));
+
+  conn->pcb.tcp = NULL;
+
+  conn->err = err;
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+    /* Register event with callback */
+    API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0);
+    sys_mbox_post(conn->recvmbox, NULL);
+  }
+  if (conn->op_completed != SYS_SEM_NULL && conn->state == NETCONN_CONNECT) {
+    conn->state = NETCONN_NONE;
+    sys_sem_signal(conn->op_completed);
+  }
+  if (conn->acceptmbox != SYS_MBOX_NULL) {
+    /* Register event with callback */
+    API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0);
+    sys_mbox_post(conn->acceptmbox, NULL);
+  }
+  if ((conn->state == NETCONN_WRITE) || (conn->state == NETCONN_CLOSE)) {
+    /* calling do_writemore/do_close_internal is not necessary
+       since the pcb has already been deleted! */
+    conn->state = NETCONN_NONE;
+    /* wake up the waiting task */
+    sys_sem_signal(conn->op_completed);
+  }
+}
+
+/**
+ * Setup a tcp_pcb with the correct callback function pointers
+ * and their arguments.
+ *
+ * @param conn the TCP netconn to setup
+ */
+static void
+setup_tcp(struct netconn *conn)
+{
+  struct tcp_pcb *pcb;
+
+  pcb = conn->pcb.tcp;
+  tcp_arg(pcb, conn);
+  tcp_recv(pcb, recv_tcp);
+  tcp_sent(pcb, sent_tcp);
+  tcp_poll(pcb, poll_tcp, 4);
+  tcp_err(pcb, err_tcp);
+}
+
+/**
+ * Accept callback function for TCP netconns.
+ * Allocates a new netconn and posts that to conn->acceptmbox.
+ *
+ * @see tcp.h (struct tcp_pcb_listen.accept) for parameters and return value
+ */
+static err_t
+accept_function(void *arg, struct tcp_pcb *newpcb, err_t err)
+{
+  struct netconn *newconn;
+  struct netconn *conn;
+
+#if API_MSG_DEBUG
+#if TCP_DEBUG
+  tcp_debug_print_state(newpcb->state);
+#endif /* TCP_DEBUG */
+#endif /* API_MSG_DEBUG */
+  conn = (struct netconn *)arg;
+
+  LWIP_ERROR("accept_function: invalid conn->acceptmbox",
+             conn->acceptmbox != SYS_MBOX_NULL, return ERR_VAL;);
+
+  /* We have to set the callback here even though
+   * the new socket is unknown. conn->socket is marked as -1. */
+  newconn = netconn_alloc(conn->type, conn->callback);
+  if (newconn == NULL) {
+    return ERR_MEM;
+  }
+  newconn->pcb.tcp = newpcb;
+  setup_tcp(newconn);
+  newconn->err = err;
+  /* Register event with callback */
+  API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0);
+
+  if (sys_mbox_trypost(conn->acceptmbox, newconn) != ERR_OK) {
+    /* When returning != ERR_OK, the connection is aborted in tcp_process(),
+       so do nothing here! */
+    newconn->pcb.tcp = NULL;
+    netconn_free(newconn);
+    return ERR_MEM;
+  }
+  return ERR_OK;
+}
+#endif /* LWIP_TCP */
+
+/**
+ * Create a new pcb of a specific type.
+ * Called from do_newconn().
+ *
+ * @param msg the api_msg_msg describing the connection type
+ * @return msg->conn->err, but the return value is currently ignored
+ */
+static err_t
+pcb_new(struct api_msg_msg *msg)
+{
+   msg->conn->err = ERR_OK;
+
+   LWIP_ASSERT("pcb_new: pcb already allocated", msg->conn->pcb.tcp == NULL);
+
+   /* Allocate a PCB for this connection */
+   switch(NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+   case NETCONN_RAW:
+     msg->conn->pcb.raw = raw_new(msg->msg.n.proto);
+     if(msg->conn->pcb.raw == NULL) {
+       msg->conn->err = ERR_MEM;
+       break;
+     }
+     raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
+     break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+   case NETCONN_UDP:
+     msg->conn->pcb.udp = udp_new();
+     if(msg->conn->pcb.udp == NULL) {
+       msg->conn->err = ERR_MEM;
+       break;
+     }
+#if LWIP_UDPLITE
+     if (msg->conn->type==NETCONN_UDPLITE) {
+       udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
+     }
+#endif /* LWIP_UDPLITE */
+     if (msg->conn->type==NETCONN_UDPNOCHKSUM) {
+       udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
+     }
+     udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+     break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+   case NETCONN_TCP:
+     msg->conn->pcb.tcp = tcp_new();
+     if(msg->conn->pcb.tcp == NULL) {
+       msg->conn->err = ERR_MEM;
+       break;
+     }
+     setup_tcp(msg->conn);
+     break;
+#endif /* LWIP_TCP */
+   default:
+     /* Unsupported netconn type, e.g. protocol disabled */
+     msg->conn->err = ERR_VAL;
+     break;
+   }
+
+  return msg->conn->err;
+}
+
+/**
+ * Create a new pcb of a specific type inside a netconn.
+ * Called from netconn_new_with_proto_and_callback.
+ *
+ * @param msg the api_msg_msg describing the connection type
+ */
+void
+do_newconn(struct api_msg_msg *msg)
+{
+   if(msg->conn->pcb.tcp == NULL) {
+     pcb_new(msg);
+   }
+   /* Else? This "new" connection already has a PCB allocated. */
+   /* Is this an error condition? Should it be deleted? */
+   /* We currently just are happy and return. */
+
+   TCPIP_APIMSG_ACK(msg);
+}
+
+/**
+ * Create a new netconn (of a specific type) that has a callback function.
+ * The corresponding pcb is NOT created!
+ *
+ * @param t the type of 'connection' to create (@see enum netconn_type)
+ * @param proto the IP protocol for RAW IP pcbs
+ * @param callback a function to call on status changes (RX available, TX'ed)
+ * @return a newly allocated struct netconn or
+ *         NULL on memory error
+ */
+struct netconn*
+netconn_alloc(enum netconn_type t, netconn_callback callback)
+{
+  struct netconn *conn;
+  int size;
+
+  conn = memp_malloc(MEMP_NETCONN);
+  if (conn == NULL) {
+    return NULL;
+  }
+
+  conn->err = ERR_OK;
+  conn->type = t;
+  conn->pcb.tcp = NULL;
+
+#if (DEFAULT_RAW_RECVMBOX_SIZE == DEFAULT_UDP_RECVMBOX_SIZE) && \
+    (DEFAULT_RAW_RECVMBOX_SIZE == DEFAULT_TCP_RECVMBOX_SIZE)
+  size = DEFAULT_RAW_RECVMBOX_SIZE;
+#else
+  switch(NETCONNTYPE_GROUP(t)) {
+#if LWIP_RAW
+  case NETCONN_RAW:
+    size = DEFAULT_RAW_RECVMBOX_SIZE;
+    break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+  case NETCONN_UDP:
+    size = DEFAULT_UDP_RECVMBOX_SIZE;
+    break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+  case NETCONN_TCP:
+    size = DEFAULT_TCP_RECVMBOX_SIZE;
+    break;
+#endif /* LWIP_TCP */
+  default:
+    LWIP_ASSERT("netconn_alloc: undefined netconn_type", 0);
+    break;
+  }
+#endif
+
+  if ((conn->op_completed = sys_sem_new(0)) == SYS_SEM_NULL) {
+    memp_free(MEMP_NETCONN, conn);
+    return NULL;
+  }
+  if ((conn->recvmbox = sys_mbox_new(size)) == SYS_MBOX_NULL) {
+    sys_sem_free(conn->op_completed);
+    memp_free(MEMP_NETCONN, conn);
+    return NULL;
+  }
+
+  conn->acceptmbox   = SYS_MBOX_NULL;
+  conn->state        = NETCONN_NONE;
+  /* initialize socket to -1 since 0 is a valid socket */
+  conn->socket       = -1;
+  conn->callback     = callback;
+  conn->recv_avail   = 0;
+#if LWIP_SO_RCVTIMEO
+  conn->recv_timeout = 0;
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+  conn->recv_bufsize = INT_MAX;
+#endif /* LWIP_SO_RCVBUF */
+  return conn;
+}
+
+/**
+ * Delete a netconn and all its resources.
+ * The pcb is NOT freed (since we might not be in the right thread context do this).
+ *
+ * @param conn the netconn to free
+ */
+void
+netconn_free(struct netconn *conn)
+{
+  void *mem;
+  LWIP_ASSERT("PCB must be deallocated outside this function", conn->pcb.tcp == NULL);
+
+  /* Drain the recvmbox. */
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+    while (sys_mbox_tryfetch(conn->recvmbox, &mem) != SYS_MBOX_EMPTY) {
+      if (conn->type == NETCONN_TCP) {
+        if(mem != NULL) {
+          pbuf_free((struct pbuf *)mem);
+        }
+      } else {
+        netbuf_delete((struct netbuf *)mem);
+      }
+    }
+    sys_mbox_free(conn->recvmbox);
+    conn->recvmbox = SYS_MBOX_NULL;
+  }
+
+  /* Drain the acceptmbox. */
+  if (conn->acceptmbox != SYS_MBOX_NULL) {
+    while (sys_mbox_tryfetch(conn->acceptmbox, &mem) != SYS_MBOX_EMPTY) {
+      netconn_delete((struct netconn *)mem);
+    }
+    sys_mbox_free(conn->acceptmbox);
+    conn->acceptmbox = SYS_MBOX_NULL;
+  }
+
+  sys_sem_free(conn->op_completed);
+  conn->op_completed = SYS_SEM_NULL;
+
+  memp_free(MEMP_NETCONN, conn);
+}
+
+#if LWIP_TCP
+/**
+ * Internal helper function to close a TCP netconn: since this sometimes
+ * doesn't work at the first attempt, this function is called from multiple
+ * places.
+ *
+ * @param conn the TCP netconn to close
+ */
+static void
+do_close_internal(struct netconn *conn)
+{
+  err_t err;
+
+  LWIP_ASSERT("invalid conn", (conn != NULL));
+  LWIP_ASSERT("this is for tcp netconns only", (conn->type == NETCONN_TCP));
+  LWIP_ASSERT("conn must be in state NETCONN_CLOSE", (conn->state == NETCONN_CLOSE));
+  LWIP_ASSERT("pcb already closed", (conn->pcb.tcp != NULL));
+
+  /* Set back some callback pointers */
+  if (conn->pcb.tcp->state == LISTEN) {
+    tcp_arg(conn->pcb.tcp, NULL);
+    tcp_accept(conn->pcb.tcp, NULL);
+  } else {
+    tcp_recv(conn->pcb.tcp, NULL);
+  }
+  /* Try to close the connection */
+  err = tcp_close(conn->pcb.tcp);
+  if (err == ERR_OK) {
+    /* Closing succeeded */
+    conn->state = NETCONN_NONE;
+    /* Set back some callback pointers as conn is going away */
+    tcp_err(conn->pcb.tcp, NULL);
+    tcp_poll(conn->pcb.tcp, NULL, 4);
+    tcp_sent(conn->pcb.tcp, NULL);
+    tcp_recv(conn->pcb.tcp, NULL);
+    tcp_arg(conn->pcb.tcp, NULL);
+    conn->pcb.tcp = NULL;
+    conn->err = ERR_OK;
+    /* Trigger select() in socket layer. This send should something else so the
+       errorfd is set, not the read and write fd! */
+    API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0);
+    API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0);
+    /* wake up the application task */
+    sys_sem_signal(conn->op_completed);
+  }
+  /* If closing didn't succeed, we get called again either
+     from poll_tcp or from sent_tcp */
+}
+#endif /* LWIP_TCP */
+
+/**
+ * Delete the pcb inside a netconn.
+ * Called from netconn_delete.
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_delconn(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      raw_remove(msg->conn->pcb.raw);
+      break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+    case NETCONN_UDP:
+      msg->conn->pcb.udp->recv_arg = NULL;
+      udp_remove(msg->conn->pcb.udp);
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+    case NETCONN_TCP:
+      msg->conn->state = NETCONN_CLOSE;
+      do_close_internal(msg->conn);
+      /* API_EVENT is called inside do_close_internal, before releasing
+         the application thread, so we can return at this point! */
+      return;
+#endif /* LWIP_TCP */
+    default:
+      break;
+    }
+  }
+  /* tcp netconns don't come here! */
+
+  /* Trigger select() in socket layer. This send should something else so the
+     errorfd is set, not the read and write fd! */
+  API_EVENT(msg->conn, NETCONN_EVT_RCVPLUS, 0);
+  API_EVENT(msg->conn, NETCONN_EVT_SENDPLUS, 0);
+
+  if (msg->conn->op_completed != SYS_SEM_NULL) {
+    sys_sem_signal(msg->conn->op_completed);
+  }
+}
+
+/**
+ * Bind a pcb contained in a netconn
+ * Called from netconn_bind.
+ *
+ * @param msg the api_msg_msg pointing to the connection and containing
+ *            the IP address and port to bind to
+ */
+void
+do_bind(struct api_msg_msg *msg)
+{
+  if (!ERR_IS_FATAL(msg->conn->err)) {
+    if (msg->conn->pcb.tcp != NULL) {
+      switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+      case NETCONN_RAW:
+        msg->conn->err = raw_bind(msg->conn->pcb.raw, msg->msg.bc.ipaddr);
+        break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+      case NETCONN_UDP:
+        msg->conn->err = udp_bind(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port);
+        break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+      case NETCONN_TCP:
+        msg->conn->err = tcp_bind(msg->conn->pcb.tcp, msg->msg.bc.ipaddr, msg->msg.bc.port);
+        break;
+#endif /* LWIP_TCP */
+      default:
+        break;
+      }
+    } else {
+      /* msg->conn->pcb is NULL */
+      msg->conn->err = ERR_VAL;
+    }
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+
+#if LWIP_TCP
+/**
+ * TCP callback function if a connection (opened by tcp_connect/do_connect) has
+ * been established (or reset by the remote host).
+ *
+ * @see tcp.h (struct tcp_pcb.connected) for parameters and return values
+ */
+static err_t
+do_connected(void *arg, struct tcp_pcb *pcb, err_t err)
+{
+  struct netconn *conn;
+
+  LWIP_UNUSED_ARG(pcb);
+
+  conn = arg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  conn->err = err;
+  if ((conn->type == NETCONN_TCP) && (err == ERR_OK)) {
+    setup_tcp(conn);
+  }
+  conn->state = NETCONN_NONE;
+  sys_sem_signal(conn->op_completed);
+  return ERR_OK;
+}
+#endif /* LWIP_TCP */
+
+/**
+ * Connect a pcb contained inside a netconn
+ * Called from netconn_connect.
+ *
+ * @param msg the api_msg_msg pointing to the connection and containing
+ *            the IP address and port to connect to
+ */
+void
+do_connect(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp == NULL) {
+    sys_sem_signal(msg->conn->op_completed);
+    return;
+  }
+
+  switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+  case NETCONN_RAW:
+    msg->conn->err = raw_connect(msg->conn->pcb.raw, msg->msg.bc.ipaddr);
+    sys_sem_signal(msg->conn->op_completed);
+    break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+  case NETCONN_UDP:
+    msg->conn->err = udp_connect(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port);
+    sys_sem_signal(msg->conn->op_completed);
+    break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+  case NETCONN_TCP:
+    msg->conn->state = NETCONN_CONNECT;
+    setup_tcp(msg->conn);
+    msg->conn->err = tcp_connect(msg->conn->pcb.tcp, msg->msg.bc.ipaddr, msg->msg.bc.port,
+                                 do_connected);
+    /* sys_sem_signal() is called from do_connected (or err_tcp()),
+     * when the connection is established! */
+    break;
+#endif /* LWIP_TCP */
+  default:
+    break;
+  }
+}
+
+/**
+ * Connect a pcb contained inside a netconn
+ * Only used for UDP netconns.
+ * Called from netconn_disconnect.
+ *
+ * @param msg the api_msg_msg pointing to the connection to disconnect
+ */
+void
+do_disconnect(struct api_msg_msg *msg)
+{
+#if LWIP_UDP
+  if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_UDP) {
+    udp_disconnect(msg->conn->pcb.udp);
+  }
+#endif /* LWIP_UDP */
+  TCPIP_APIMSG_ACK(msg);
+}
+
+/**
+ * Set a TCP pcb contained in a netconn into listen mode
+ * Called from netconn_listen.
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_listen(struct api_msg_msg *msg)
+{
+#if LWIP_TCP
+  if (!ERR_IS_FATAL(msg->conn->err)) {
+    if (msg->conn->pcb.tcp != NULL) {
+      if (msg->conn->type == NETCONN_TCP) {
+        if (msg->conn->pcb.tcp->state == CLOSED) {
+#if TCP_LISTEN_BACKLOG
+          struct tcp_pcb* lpcb = tcp_listen_with_backlog(msg->conn->pcb.tcp, msg->msg.lb.backlog);
+#else  /* TCP_LISTEN_BACKLOG */
+          struct tcp_pcb* lpcb = tcp_listen(msg->conn->pcb.tcp);
+#endif /* TCP_LISTEN_BACKLOG */
+          if (lpcb == NULL) {
+            msg->conn->err = ERR_MEM;
+          } else {
+            /* delete the recvmbox and allocate the acceptmbox */
+            if (msg->conn->recvmbox != SYS_MBOX_NULL) {
+              /** @todo: should we drain the recvmbox here? */
+              sys_mbox_free(msg->conn->recvmbox);
+              msg->conn->recvmbox = SYS_MBOX_NULL;
+            }
+            if (msg->conn->acceptmbox == SYS_MBOX_NULL) {
+              if ((msg->conn->acceptmbox = sys_mbox_new(DEFAULT_ACCEPTMBOX_SIZE)) == SYS_MBOX_NULL) {
+                msg->conn->err = ERR_MEM;
+              }
+            }
+            if (msg->conn->err == ERR_OK) {
+              msg->conn->state = NETCONN_LISTEN;
+              msg->conn->pcb.tcp = lpcb;
+              tcp_arg(msg->conn->pcb.tcp, msg->conn);
+              tcp_accept(msg->conn->pcb.tcp, accept_function);
+            }
+          }
+        } else {
+          msg->conn->err = ERR_CONN;
+        }
+      }
+    }
+  }
+#endif /* LWIP_TCP */
+  TCPIP_APIMSG_ACK(msg);
+}
+
+/**
+ * Send some data on a RAW or UDP pcb contained in a netconn
+ * Called from netconn_send
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_send(struct api_msg_msg *msg)
+{
+  if (!ERR_IS_FATAL(msg->conn->err)) {
+    if (msg->conn->pcb.tcp != NULL) {
+      switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+      case NETCONN_RAW:
+        if (msg->msg.b->addr == NULL) {
+          msg->conn->err = raw_send(msg->conn->pcb.raw, msg->msg.b->p);
+        } else {
+          msg->conn->err = raw_sendto(msg->conn->pcb.raw, msg->msg.b->p, msg->msg.b->addr);
+        }
+        break;
+#endif
+#if LWIP_UDP
+      case NETCONN_UDP:
+        if (msg->msg.b->addr == NULL) {
+          msg->conn->err = udp_send(msg->conn->pcb.udp, msg->msg.b->p);
+        } else {
+          msg->conn->err = udp_sendto(msg->conn->pcb.udp, msg->msg.b->p, msg->msg.b->addr, msg->msg.b->port);
+        }
+        break;
+#endif /* LWIP_UDP */
+      default:
+        break;
+      }
+    }
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+
+/**
+ * Recv some data from a RAW or UDP pcb contained in a netconn
+ * Called from netconn_recv
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_recv(struct api_msg_msg *msg)
+{
+#if LWIP_TCP
+  if (!ERR_IS_FATAL(msg->conn->err)) {
+    if (msg->conn->pcb.tcp != NULL) {
+      if (msg->conn->type == NETCONN_TCP) {
+#if TCP_LISTEN_BACKLOG
+        if (msg->conn->pcb.tcp->state == LISTEN) {
+          tcp_accepted(msg->conn->pcb.tcp);
+        } else
+#endif /* TCP_LISTEN_BACKLOG */
+        {
+          tcp_recved(msg->conn->pcb.tcp, msg->msg.r.len);
+        }
+      }
+    }
+  }
+#endif /* LWIP_TCP */
+  TCPIP_APIMSG_ACK(msg);
+}
+
+#if LWIP_TCP
+/**
+ * See if more data needs to be written from a previous call to netconn_write.
+ * Called initially from do_write. If the first call can't send all data
+ * (because of low memory or empty send-buffer), this function is called again
+ * from sent_tcp() or poll_tcp() to send more data. If all data is sent, the
+ * blocking application thread (waiting in netconn_write) is released.
+ *
+ * @param conn netconn (that is currently in state NETCONN_WRITE) to process
+ * @return ERR_OK
+ *         ERR_MEM if LWIP_TCPIP_CORE_LOCKING=1 and sending hasn't yet finished
+ */
+static err_t
+do_writemore(struct netconn *conn)
+{
+  err_t err;
+  void *dataptr;
+  u16_t len, available;
+  u8_t write_finished = 0;
+
+  LWIP_ASSERT("conn->state == NETCONN_WRITE", (conn->state == NETCONN_WRITE));
+
+  dataptr = (u8_t*)conn->write_msg->msg.w.dataptr + conn->write_offset;
+  if ((conn->write_msg->msg.w.len - conn->write_offset > 0xffff)) { /* max_u16_t */
+    len = 0xffff;
+#if LWIP_TCPIP_CORE_LOCKING
+    conn->write_delayed = 1;
+#endif
+  } else {
+    len = conn->write_msg->msg.w.len - conn->write_offset;
+  }
+  available = tcp_sndbuf(conn->pcb.tcp);
+  if (available < len) {
+    /* don't try to write more than sendbuf */
+    len = available;
+#if LWIP_TCPIP_CORE_LOCKING
+    conn->write_delayed = 1;
+#endif
+  }
+
+  err = tcp_write(conn->pcb.tcp, dataptr, len, conn->write_msg->msg.w.apiflags);
+  LWIP_ASSERT("do_writemore: invalid length!", ((conn->write_offset + len) <= conn->write_msg->msg.w.len));
+  if (err == ERR_OK) {
+    conn->write_offset += len;
+    if (conn->write_offset == conn->write_msg->msg.w.len) {
+      /* everything was written */
+      write_finished = 1;
+      conn->write_msg = NULL;
+      conn->write_offset = 0;
+    }
+    err = tcp_output_nagle(conn->pcb.tcp);
+    conn->err = err;
+    if ((err == ERR_OK) && (tcp_sndbuf(conn->pcb.tcp) <= TCP_SNDLOWAT)) {
+      API_EVENT(conn, NETCONN_EVT_SENDMINUS, len);
+    }
+  } else if (err == ERR_MEM) {
+    /* If ERR_MEM, we wait for sent_tcp or poll_tcp to be called
+       we do NOT return to the application thread, since ERR_MEM is
+       only a temporary error! */
+
+    /* tcp_enqueue returned ERR_MEM, try tcp_output anyway */
+    err = tcp_output(conn->pcb.tcp);
+
+#if LWIP_TCPIP_CORE_LOCKING
+    conn->write_delayed = 1;
+#endif
+  } else {
+    /* On errors != ERR_MEM, we don't try writing any more but return
+       the error to the application thread. */
+    conn->err = err;
+    write_finished = 1;
+  }
+
+  if (write_finished) {
+    /* everything was written: set back connection state
+       and back to application task */
+    conn->state = NETCONN_NONE;
+#if LWIP_TCPIP_CORE_LOCKING
+    if (conn->write_delayed != 0)
+#endif
+    {
+      sys_sem_signal(conn->op_completed);
+    }
+  }
+#if LWIP_TCPIP_CORE_LOCKING
+  else
+    return ERR_MEM;
+#endif
+  return ERR_OK;
+}
+#endif /* LWIP_TCP */
+
+/**
+ * Send some data on a TCP pcb contained in a netconn
+ * Called from netconn_write
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_write(struct api_msg_msg *msg)
+{
+  if (!ERR_IS_FATAL(msg->conn->err)) {
+    if ((msg->conn->pcb.tcp != NULL) && (msg->conn->type == NETCONN_TCP)) {
+#if LWIP_TCP
+      msg->conn->state = NETCONN_WRITE;
+      /* set all the variables used by do_writemore */
+      msg->conn->write_msg = msg;
+      msg->conn->write_offset = 0;
+#if LWIP_TCPIP_CORE_LOCKING
+      msg->conn->write_delayed = 0;
+      if (do_writemore(msg->conn) != ERR_OK) {
+        LWIP_ASSERT("state!", msg->conn->state == NETCONN_WRITE);
+        UNLOCK_TCPIP_CORE();
+        sys_arch_sem_wait(msg->conn->op_completed, 0);
+        LOCK_TCPIP_CORE();
+        LWIP_ASSERT("state!", msg->conn->state == NETCONN_NONE);
+      }
+#else
+      do_writemore(msg->conn);
+#endif
+      /* for both cases: if do_writemore was called, don't ACK the APIMSG! */
+      return;
+#endif /* LWIP_TCP */
+#if (LWIP_UDP || LWIP_RAW)
+    } else {
+      msg->conn->err = ERR_VAL;
+#endif /* (LWIP_UDP || LWIP_RAW) */
+    }
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+
+/**
+ * Return a connection's local or remote address
+ * Called from netconn_getaddr
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_getaddr(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.ip != NULL) {
+    *(msg->msg.ad.ipaddr) = (msg->msg.ad.local?msg->conn->pcb.ip->local_ip:msg->conn->pcb.ip->remote_ip);
+
+    switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      if (msg->msg.ad.local) {
+        *(msg->msg.ad.port) = msg->conn->pcb.raw->protocol;
+      } else {
+        /* return an error as connecting is only a helper for upper layers */
+        msg->conn->err = ERR_CONN;
+      }
+      break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+    case NETCONN_UDP:
+      if (msg->msg.ad.local) {
+        *(msg->msg.ad.port) = msg->conn->pcb.udp->local_port;
+      } else {
+        if ((msg->conn->pcb.udp->flags & UDP_FLAGS_CONNECTED) == 0) {
+          msg->conn->err = ERR_CONN;
+        } else {
+          *(msg->msg.ad.port) = msg->conn->pcb.udp->remote_port;
+        }
+      }
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+    case NETCONN_TCP:
+      *(msg->msg.ad.port) = (msg->msg.ad.local?msg->conn->pcb.tcp->local_port:msg->conn->pcb.tcp->remote_port);
+      break;
+#endif /* LWIP_TCP */
+    }
+  } else {
+    msg->conn->err = ERR_CONN;
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+
+/**
+ * Close a TCP pcb contained in a netconn
+ * Called from netconn_close
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_close(struct api_msg_msg *msg)
+{
+#if LWIP_TCP
+  if ((msg->conn->pcb.tcp != NULL) && (msg->conn->type == NETCONN_TCP)) {
+      msg->conn->state = NETCONN_CLOSE;
+      do_close_internal(msg->conn);
+      /* for tcp netconns, do_close_internal ACKs the message */
+  } else
+#endif /* LWIP_TCP */
+  {
+    msg->conn->err = ERR_VAL;
+    TCPIP_APIMSG_ACK(msg);
+  }
+}
+
+#if LWIP_IGMP
+/**
+ * Join multicast groups for UDP netconns.
+ * Called from netconn_join_leave_group
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_join_leave_group(struct api_msg_msg *msg)
+{
+  if (!ERR_IS_FATAL(msg->conn->err)) {
+    if (msg->conn->pcb.tcp != NULL) {
+      if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_UDP) {
+#if LWIP_UDP
+        if (msg->msg.jl.join_or_leave == NETCONN_JOIN) {
+          msg->conn->err = igmp_joingroup(msg->msg.jl.interface, msg->msg.jl.multiaddr);
+        } else {
+          msg->conn->err = igmp_leavegroup(msg->msg.jl.interface, msg->msg.jl.multiaddr);
+        }
+#endif /* LWIP_UDP */
+#if (LWIP_TCP || LWIP_RAW)
+      } else {
+        msg->conn->err = ERR_VAL;
+#endif /* (LWIP_TCP || LWIP_RAW) */
+      }
+    }
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+#endif /* LWIP_IGMP */
+
+#if LWIP_DNS
+/**
+ * Callback function that is called when DNS name is resolved
+ * (or on timeout). A waiting application thread is waked up by
+ * signaling the semaphore.
+ */
+static void
+do_dns_found(const char *name, struct ip_addr *ipaddr, void *arg)
+{
+  struct dns_api_msg *msg = (struct dns_api_msg*)arg;
+
+  LWIP_ASSERT("DNS response for wrong host name", strcmp(msg->name, name) == 0);
+
+  if (ipaddr == NULL) {
+    /* timeout or memory error */
+    *msg->err = ERR_VAL;
+  } else {
+    /* address was resolved */
+    *msg->err = ERR_OK;
+    *msg->addr = *ipaddr;
+  }
+  /* wake up the application task waiting in netconn_gethostbyname */
+  sys_sem_signal(msg->sem);
+}
+
+/**
+ * Execute a DNS query
+ * Called from netconn_gethostbyname
+ *
+ * @param arg the dns_api_msg pointing to the query
+ */
+void
+do_gethostbyname(void *arg)
+{
+  struct dns_api_msg *msg = (struct dns_api_msg*)arg;
+
+  *msg->err = dns_gethostbyname(msg->name, msg->addr, do_dns_found, msg);
+  if (*msg->err != ERR_INPROGRESS) {
+    /* on error or immediate success, wake up the application
+     * task waiting in netconn_gethostbyname */
+    sys_sem_signal(msg->sem);
+  }
+}
+#endif /* LWIP_DNS */
+
+#endif /* LWIP_NETCONN */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/err.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/err.c
new file mode 100644
index 0000000..19ad3e7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/err.c
@@ -0,0 +1,74 @@
+/**
+ * @file
+ * Error Management module
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/err.h"
+
+#ifdef LWIP_DEBUG
+
+static const char *err_strerr[] = {
+           "Ok.",                    /* ERR_OK          0  */
+           "Out of memory error.",   /* ERR_MEM        -1  */
+           "Buffer error.",          /* ERR_BUF        -2  */
+           "Routing problem.",       /* ERR_RTE        -3  */
+           "Connection aborted.",    /* ERR_ABRT       -4  */
+           "Connection reset.",      /* ERR_RST        -5  */
+           "Connection closed.",     /* ERR_CLSD       -6  */
+           "Not connected.",         /* ERR_CONN       -7  */
+           "Illegal value.",         /* ERR_VAL        -8  */
+           "Illegal argument.",      /* ERR_ARG        -9  */
+           "Address in use.",        /* ERR_USE        -10 */
+           "Low-level netif error.", /* ERR_IF         -11 */
+           "Already connected.",     /* ERR_ISCONN     -12 */
+           "Timeout.",               /* ERR_TIMEOUT    -13 */
+           "Operation in progress."  /* ERR_INPROGRESS -14 */
+};
+
+/**
+ * Convert an lwip internal error to a string representation.
+ *
+ * @param err an lwip internal err_t
+ * @return a string representation for err
+ */
+const char *
+lwip_strerr(err_t err)
+{
+  return err_strerr[-err];
+
+}
+
+#endif /* LWIP_DEBUG */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/netbuf.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/netbuf.c
new file mode 100644
index 0000000..12f4881
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/netbuf.c
@@ -0,0 +1,235 @@
+/**
+ * @file
+ * Network buffer management
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netbuf.h"
+#include "lwip/memp.h"
+
+#include 
+
+/**
+ * Create (allocate) and initialize a new netbuf.
+ * The netbuf doesn't yet contain a packet buffer!
+ *
+ * @return a pointer to a new netbuf
+ *         NULL on lack of memory
+ */
+struct
+netbuf *netbuf_new(void)
+{
+  struct netbuf *buf;
+
+  buf = memp_malloc(MEMP_NETBUF);
+  if (buf != NULL) {
+    buf->p = NULL;
+    buf->ptr = NULL;
+    buf->addr = NULL;
+    return buf;
+  } else {
+    return NULL;
+  }
+}
+
+/**
+ * Deallocate a netbuf allocated by netbuf_new().
+ *
+ * @param buf pointer to a netbuf allocated by netbuf_new()
+ */
+void
+netbuf_delete(struct netbuf *buf)
+{
+  if (buf != NULL) {
+    if (buf->p != NULL) {
+      pbuf_free(buf->p);
+      buf->p = buf->ptr = NULL;
+    }
+    memp_free(MEMP_NETBUF, buf);
+  }
+}
+
+/**
+ * Allocate memory for a packet buffer for a given netbuf.
+ *
+ * @param buf the netbuf for which to allocate a packet buffer
+ * @param size the size of the packet buffer to allocate
+ * @return pointer to the allocated memory
+ *         NULL if no memory could be allocated
+ */
+void *
+netbuf_alloc(struct netbuf *buf, u16_t size)
+{
+  LWIP_ERROR("netbuf_alloc: invalid buf", (buf != NULL), return NULL;);
+
+  /* Deallocate any previously allocated memory. */
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = pbuf_alloc(PBUF_TRANSPORT, size, PBUF_RAM);
+  if (buf->p == NULL) {
+     return NULL;
+  }
+  LWIP_ASSERT("check that first pbuf can hold size",
+             (buf->p->len >= size));
+  buf->ptr = buf->p;
+  return buf->p->payload;
+}
+
+/**
+ * Free the packet buffer included in a netbuf
+ *
+ * @param buf pointer to the netbuf which contains the packet buffer to free
+ */
+void
+netbuf_free(struct netbuf *buf)
+{
+  LWIP_ERROR("netbuf_free: invalid buf", (buf != NULL), return;);
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = buf->ptr = NULL;
+}
+
+/**
+ * Let a netbuf reference existing (non-volatile) data.
+ *
+ * @param buf netbuf which should reference the data
+ * @param dataptr pointer to the data to reference
+ * @param size size of the data
+ * @return ERR_OK if data is referenced
+ *         ERR_MEM if data couldn't be referenced due to lack of memory
+ */
+err_t
+netbuf_ref(struct netbuf *buf, const void *dataptr, u16_t size)
+{
+  LWIP_ERROR("netbuf_ref: invalid buf", (buf != NULL), return ERR_ARG;);
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF);
+  if (buf->p == NULL) {
+    buf->ptr = NULL;
+    return ERR_MEM;
+  }
+  buf->p->payload = (void*)dataptr;
+  buf->p->len = buf->p->tot_len = size;
+  buf->ptr = buf->p;
+  return ERR_OK;
+}
+
+/**
+ * Chain one netbuf to another (@see pbuf_chain)
+ *
+ * @param head the first netbuf
+ * @param tail netbuf to chain after head
+ */
+void
+netbuf_chain(struct netbuf *head, struct netbuf *tail)
+{
+  LWIP_ERROR("netbuf_ref: invalid head", (head != NULL), return;);
+  LWIP_ERROR("netbuf_chain: invalid tail", (tail != NULL), return;);
+  pbuf_chain(head->p, tail->p);
+  head->ptr = head->p;
+  memp_free(MEMP_NETBUF, tail);
+}
+
+/**
+ * Get the data pointer and length of the data inside a netbuf.
+ *
+ * @param buf netbuf to get the data from
+ * @param dataptr pointer to a void pointer where to store the data pointer
+ * @param len pointer to an u16_t where the length of the data is stored
+ * @return ERR_OK if the information was retreived,
+ *         ERR_BUF on error.
+ */
+err_t
+netbuf_data(struct netbuf *buf, void **dataptr, u16_t *len)
+{
+  LWIP_ERROR("netbuf_data: invalid buf", (buf != NULL), return ERR_ARG;);
+  LWIP_ERROR("netbuf_data: invalid dataptr", (dataptr != NULL), return ERR_ARG;);
+  LWIP_ERROR("netbuf_data: invalid len", (len != NULL), return ERR_ARG;);
+
+  if (buf->ptr == NULL) {
+    return ERR_BUF;
+  }
+  *dataptr = buf->ptr->payload;
+  *len = buf->ptr->len;
+  return ERR_OK;
+}
+
+/**
+ * Move the current data pointer of a packet buffer contained in a netbuf
+ * to the next part.
+ * The packet buffer itself is not modified.
+ *
+ * @param buf the netbuf to modify
+ * @return -1 if there is no next part
+ *         1  if moved to the next part but now there is no next part
+ *         0  if moved to the next part and there are still more parts
+ */
+s8_t
+netbuf_next(struct netbuf *buf)
+{
+  LWIP_ERROR("netbuf_free: invalid buf", (buf != NULL), return -1;);
+  if (buf->ptr->next == NULL) {
+    return -1;
+  }
+  buf->ptr = buf->ptr->next;
+  if (buf->ptr->next == NULL) {
+    return 1;
+  }
+  return 0;
+}
+
+/**
+ * Move the current data pointer of a packet buffer contained in a netbuf
+ * to the beginning of the packet.
+ * The packet buffer itself is not modified.
+ *
+ * @param buf the netbuf to modify
+ */
+void
+netbuf_first(struct netbuf *buf)
+{
+  LWIP_ERROR("netbuf_free: invalid buf", (buf != NULL), return;);
+  buf->ptr = buf->p;
+}
+
+#endif /* LWIP_NETCONN */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/netdb.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/netdb.c
new file mode 100644
index 0000000..d45f83f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/netdb.c
@@ -0,0 +1,352 @@
+/**
+ * @file
+ * API functions for name resolving
+ *
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Simon Goldschmidt
+ *
+ */
+
+#include "lwip/netdb.h"
+
+#if LWIP_DNS && LWIP_SOCKET
+
+#include "lwip/err.h"
+#include "lwip/mem.h"
+#include "lwip/ip_addr.h"
+#include "lwip/api.h"
+
+/** helper struct for gethostbyname_r to access the char* buffer */
+struct gethostbyname_r_helper {
+  struct ip_addr *addrs;
+  struct ip_addr addr;
+  char *aliases;
+};
+
+/** h_errno is exported in netdb.h for access by applications. */
+#if LWIP_DNS_API_DECLARE_H_ERRNO
+int h_errno;
+#endif /* LWIP_DNS_API_DECLARE_H_ERRNO */
+
+/** define "hostent" variables storage: 0 if we use a static (but unprotected)
+ * set of variables for lwip_gethostbyname, 1 if we use a local storage */
+#ifndef LWIP_DNS_API_HOSTENT_STORAGE
+#define LWIP_DNS_API_HOSTENT_STORAGE 0
+#endif
+
+/** define "hostent" variables storage */
+#if LWIP_DNS_API_HOSTENT_STORAGE
+#define HOSTENT_STORAGE
+#else
+#define HOSTENT_STORAGE static
+#endif /* LWIP_DNS_API_STATIC_HOSTENT */
+
+/**
+ * Returns an entry containing addresses of address family AF_INET
+ * for the host with name name.
+ * Due to dns_gethostbyname limitations, only one address is returned.
+ *
+ * @param name the hostname to resolve
+ * @return an entry containing addresses of address family AF_INET
+ *         for the host with name name
+ */
+struct hostent*
+lwip_gethostbyname(const char *name)
+{
+  err_t err;
+  struct ip_addr addr;
+
+  /* buffer variables for lwip_gethostbyname() */
+  HOSTENT_STORAGE struct hostent s_hostent;
+  HOSTENT_STORAGE char *s_aliases;
+  HOSTENT_STORAGE struct ip_addr s_hostent_addr;
+  HOSTENT_STORAGE struct ip_addr *s_phostent_addr;
+
+  /* query host IP address */
+  err = netconn_gethostbyname(name, &addr);
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(DNS_DEBUG, ("lwip_gethostbyname(%s) failed, err=%d\n", name, err));
+    h_errno = HOST_NOT_FOUND;
+    return NULL;
+  }
+
+  /* fill hostent */
+  s_hostent_addr = addr;
+  s_phostent_addr = &s_hostent_addr;
+  s_hostent.h_name = (char*)name;
+  s_hostent.h_aliases = &s_aliases;
+  s_hostent.h_addrtype = AF_INET;
+  s_hostent.h_length = sizeof(struct ip_addr);
+  s_hostent.h_addr_list = (char**)&s_phostent_addr;
+
+#if DNS_DEBUG
+  /* dump hostent */
+  LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_name           == %s\n",      s_hostent.h_name));
+  LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_aliases        == 0x%08lX\n",(u32_t)(s_hostent.h_aliases)));
+  if (s_hostent.h_aliases != NULL) {
+    u8_t idx;
+    for ( idx=0; s_hostent.h_aliases[idx]; idx++) {
+      LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_aliases[%i]->   == 0x%08lX\n", idx, s_hostent.h_aliases[idx]));
+      LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_aliases[%i]->   == %s\n",      idx, s_hostent.h_aliases[idx]));
+    }
+  }
+  LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addrtype       == %lu\n",    (u32_t)(s_hostent.h_addrtype)));
+  LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_length         == %lu\n",    (u32_t)(s_hostent.h_length)));
+  LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addr_list      == 0x%08lX\n", s_hostent.h_addr_list));
+  if (s_hostent.h_addr_list != NULL) {
+    u8_t idx;
+    for ( idx=0; s_hostent.h_addr_list[idx]; idx++) {
+      LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addr_list[%i]   == 0x%08lX\n", idx, s_hostent.h_addr_list[idx]));
+      LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addr_list[%i]-> == %s\n",      idx, inet_ntoa(*((struct in_addr*)(s_hostent.h_addr_list[idx])))));
+    }
+  }
+#endif /* DNS_DEBUG */
+
+#if LWIP_DNS_API_HOSTENT_STORAGE
+  /* this function should return the "per-thread" hostent after copy from s_hostent */
+  return sys_thread_hostent(&s_hostent);
+#else
+  return &s_hostent;
+#endif /* LWIP_DNS_API_HOSTENT_STORAGE */
+}
+
+/**
+ * Thread-safe variant of lwip_gethostbyname: instead of using a static
+ * buffer, this function takes buffer and errno pointers as arguments
+ * and uses these for the result.
+ *
+ * @param name the hostname to resolve
+ * @param ret pre-allocated struct where to store the result
+ * @param buf pre-allocated buffer where to store additional data
+ * @param buflen the size of buf
+ * @param result pointer to a hostent pointer that is set to ret on success
+ *               and set to zero on error
+ * @param h_errnop pointer to an int where to store errors (instead of modifying
+ *                 the global h_errno)
+ * @return 0 on success, non-zero on error, additional error information
+ *         is stored in *h_errnop instead of h_errno to be thread-safe
+ */
+int
+lwip_gethostbyname_r(const char *name, struct hostent *ret, char *buf,
+                size_t buflen, struct hostent **result, int *h_errnop)
+{
+  err_t err;
+  struct gethostbyname_r_helper *h;
+  char *hostname;
+  size_t namelen;
+  int lh_errno;
+
+  if (h_errnop == NULL) {
+    /* ensure h_errnop is never NULL */
+    h_errnop = &lh_errno;
+  }
+
+  if (result == NULL) {
+    /* not all arguments given */
+    *h_errnop = EINVAL;
+    return -1;
+  }
+  /* first thing to do: set *result to nothing */
+  *result = NULL;
+  if ((name == NULL) || (ret == NULL) || (buf == 0)) {
+    /* not all arguments given */
+    *h_errnop = EINVAL;
+    return -1;
+  }
+
+  namelen = strlen(name);
+  if (buflen < (sizeof(struct gethostbyname_r_helper) + namelen + 1 + (MEM_ALIGNMENT - 1))) {
+    /* buf can't hold the data needed + a copy of name */
+    *h_errnop = ERANGE;
+    return -1;
+  }
+
+  h = (struct gethostbyname_r_helper*)LWIP_MEM_ALIGN(buf);
+  hostname = ((char*)h) + sizeof(struct gethostbyname_r_helper);
+
+  /* query host IP address */
+  err = netconn_gethostbyname(name, &(h->addr));
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(DNS_DEBUG, ("lwip_gethostbyname(%s) failed, err=%d\n", name, err));
+    *h_errnop = ENSRNOTFOUND;
+    return -1;
+  }
+
+  /* copy the hostname into buf */
+  MEMCPY(hostname, name, namelen);
+  hostname[namelen] = 0;
+
+  /* fill hostent */
+  h->addrs = &(h->addr);
+  h->aliases = NULL;
+  ret->h_name = (char*)hostname;
+  ret->h_aliases = &(h->aliases);
+  ret->h_addrtype = AF_INET;
+  ret->h_length = sizeof(struct ip_addr);
+  ret->h_addr_list = (char**)&(h->addrs);
+
+  /* set result != NULL */
+  *result = ret;
+
+  /* return success */
+  return 0;
+}
+
+/**
+ * Frees one or more addrinfo structures returned by getaddrinfo(), along with
+ * any additional storage associated with those structures. If the ai_next field
+ * of the structure is not null, the entire list of structures is freed.
+ *
+ * @param ai struct addrinfo to free
+ */
+void
+lwip_freeaddrinfo(struct addrinfo *ai)
+{
+  struct addrinfo *next;
+
+  while (ai != NULL) {
+    if (ai->ai_addr != NULL) {
+      mem_free(ai->ai_addr);
+    }
+    if (ai->ai_canonname != NULL) {
+      mem_free(ai->ai_canonname);
+    }
+    next = ai->ai_next;
+    mem_free(ai);
+    ai = next;
+  }
+}
+
+/**
+ * Translates the name of a service location (for example, a host name) and/or
+ * a service name and returns a set of socket addresses and associated
+ * information to be used in creating a socket with which to address the
+ * specified service.
+ * Memory for the result is allocated internally and must be freed by calling
+ * lwip_freeaddrinfo()!
+ *
+ * Due to a limitation in dns_gethostbyname, only the first address of a
+ * host is returned.
+ * Also, service names are not supported (only port numbers)!
+ *
+ * @param nodename descriptive name or address string of the host
+ *                 (may be NULL -> local address)
+ * @param servname port number as string of NULL 
+ * @param hints structure containing input values that set socktype and protocol
+ * @param res pointer to a pointer where to store the result (set to NULL on failure)
+ * @return 0 on success, non-zero on failure
+ */
+int
+lwip_getaddrinfo(const char *nodename, const char *servname,
+       const struct addrinfo *hints, struct addrinfo **res)
+{
+  err_t err;
+  struct ip_addr addr;
+  struct addrinfo *ai;
+  struct sockaddr_in *sa = NULL;
+  int port_nr = 0;
+
+  if (res == NULL) {
+    return EAI_FAIL;
+  }
+  *res = NULL;
+  if ((nodename == NULL) && (servname == NULL)) {
+    return EAI_NONAME;
+  }
+
+  if (servname != NULL) {
+    /* service name specified: convert to port number
+     * @todo?: currently, only ASCII integers (port numbers) are supported! */
+    port_nr = atoi(servname);
+    if ((port_nr <= 0) || (port_nr > 0xffff)) {
+      return EAI_SERVICE;
+    }
+  }
+
+  if (nodename != NULL) {
+    /* service location specified, try to resolve */
+    err = netconn_gethostbyname(nodename, &addr);
+    if (err != ERR_OK) {
+      return EAI_FAIL;
+    }
+  } else {
+    /* service location specified, use loopback address */
+    addr.addr = INADDR_LOOPBACK;
+  }
+
+  ai = mem_malloc(sizeof(struct addrinfo));
+  if (ai == NULL) {
+    goto memerr;
+  }
+  memset(ai, 0, sizeof(struct addrinfo));
+  sa = mem_malloc(sizeof(struct sockaddr_in));
+  if (sa == NULL) {
+    goto memerr;
+  }
+  memset(sa, 0, sizeof(struct sockaddr_in));
+  /* set up sockaddr */
+  sa->sin_addr.s_addr = addr.addr;
+  sa->sin_family = AF_INET;
+  sa->sin_len = sizeof(struct sockaddr_in);
+  sa->sin_port = htons(port_nr);
+
+  /* set up addrinfo */
+  ai->ai_family = AF_INET;
+  if (hints != NULL) {
+    /* copy socktype & protocol from hints if specified */
+    ai->ai_socktype = hints->ai_socktype;
+    ai->ai_protocol = hints->ai_protocol;
+  }
+  if (nodename != NULL) {
+    /* copy nodename to canonname if specified */
+    size_t namelen = strlen(nodename);
+    ai->ai_canonname = mem_malloc(namelen + 1);
+    if (ai->ai_canonname == NULL) {
+      goto memerr;
+    }
+    MEMCPY(ai->ai_canonname, nodename, namelen);
+    ai->ai_canonname[namelen] = 0;
+  }
+  ai->ai_addrlen = sizeof(struct sockaddr_in);
+  ai->ai_addr = (struct sockaddr*)sa;
+
+  *res = ai;
+
+  return 0;
+memerr:
+  if (ai != NULL) {
+    mem_free(ai);
+  }
+  if (sa != NULL) {
+    mem_free(sa);
+  }
+  return EAI_MEMORY;
+}
+
+#endif /* LWIP_DNS && LWIP_SOCKET */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/netifapi.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/netifapi.c
new file mode 100644
index 0000000..49b6ef0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/netifapi.c
@@ -0,0 +1,126 @@
+/**
+ * @file
+ * Network Interface Sequential API module
+ *
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netifapi.h"
+#include "lwip/tcpip.h"
+
+/**
+ * Call netif_add() inside the tcpip_thread context.
+ */
+void
+do_netifapi_netif_add( struct netifapi_msg_msg *msg)
+{
+  if (!netif_add( msg->netif,
+                  msg->msg.add.ipaddr,
+                  msg->msg.add.netmask,
+                  msg->msg.add.gw,
+                  msg->msg.add.state,
+                  msg->msg.add.init,
+                  msg->msg.add.input)) {
+    msg->err = ERR_IF;
+  } else {
+    msg->err = ERR_OK;
+  }
+  TCPIP_NETIFAPI_ACK(msg);
+}
+
+/**
+ * Call the "errtfunc" (or the "voidfunc" if "errtfunc" is NULL) inside the
+ * tcpip_thread context.
+ */
+void
+do_netifapi_netif_common( struct netifapi_msg_msg *msg)
+{
+  if (msg->msg.common.errtfunc!=NULL) {
+    msg->err =
+    msg->msg.common.errtfunc(msg->netif);
+  } else {
+    msg->err = ERR_OK;
+    msg->msg.common.voidfunc(msg->netif);
+  }
+  TCPIP_NETIFAPI_ACK(msg);
+}
+
+/**
+ * Call netif_add() in a thread-safe way by running that function inside the
+ * tcpip_thread context.
+ *
+ * @note for params @see netif_add()
+ */
+err_t
+netifapi_netif_add(struct netif *netif,
+                   struct ip_addr *ipaddr,
+                   struct ip_addr *netmask,
+                   struct ip_addr *gw,
+                   void *state,
+                   err_t (* init)(struct netif *netif),
+                   err_t (* input)(struct pbuf *p, struct netif *netif))
+{
+  struct netifapi_msg msg;
+  msg.function = do_netifapi_netif_add;
+  msg.msg.netif = netif;
+  msg.msg.msg.add.ipaddr  = ipaddr;
+  msg.msg.msg.add.netmask = netmask;
+  msg.msg.msg.add.gw      = gw;
+  msg.msg.msg.add.state   = state;
+  msg.msg.msg.add.init    = init;
+  msg.msg.msg.add.input   = input;
+  TCPIP_NETIFAPI(&msg);
+  return msg.msg.err;
+}
+
+/**
+ * call the "errtfunc" (or the "voidfunc" if "errtfunc" is NULL) in a thread-safe
+ * way by running that function inside the tcpip_thread context.
+ *
+ * @note use only for functions where there is only "netif" parameter.
+ */
+err_t
+netifapi_netif_common( struct netif *netif,
+                       void  (* voidfunc)(struct netif *netif),
+                       err_t (* errtfunc)(struct netif *netif) )
+{
+  struct netifapi_msg msg;
+  msg.function = do_netifapi_netif_common;
+  msg.msg.netif = netif;
+  msg.msg.msg.common.voidfunc = voidfunc;
+  msg.msg.msg.common.errtfunc = errtfunc;
+  TCPIP_NETIFAPI(&msg);
+  return msg.msg.err;
+}
+
+#endif /* LWIP_NETIF_API */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/sockets.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/sockets.c
new file mode 100644
index 0000000..18663c9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/sockets.c
@@ -0,0 +1,1924 @@
+/**
+ * @file
+ * Sockets BSD-Like API module
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ * Improved by Marc Boucher  and David Haas 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/sockets.h"
+#include "lwip/api.h"
+#include "lwip/sys.h"
+#include "lwip/igmp.h"
+#include "lwip/inet.h"
+#include "lwip/tcp.h"
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/tcpip.h"
+
+#include 
+
+#define NUM_SOCKETS MEMP_NUM_NETCONN
+
+/** Contains all internal pointers and states used for a socket */
+struct lwip_socket {
+  /** sockets currently are built on netconns, each socket has one netconn */
+  struct netconn *conn;
+  /** data that was left from the previous read */
+  struct netbuf *lastdata;
+  /** offset in the data that was left from the previous read */
+  u16_t lastoffset;
+  /** number of times data was received, set by event_callback(),
+      tested by the receive and select functions */
+  u16_t rcvevent;
+  /** number of times data was received, set by event_callback(),
+      tested by select */
+  u16_t sendevent;
+  /** socket flags (currently, only used for O_NONBLOCK) */
+  u16_t flags;
+  /** last error that occurred on this socket */
+  int err;
+};
+
+/** Description for a task waiting in select */
+struct lwip_select_cb {
+  /** Pointer to the next waiting task */
+  struct lwip_select_cb *next;
+  /** readset passed to select */
+  fd_set *readset;
+  /** writeset passed to select */
+  fd_set *writeset;
+  /** unimplemented: exceptset passed to select */
+  fd_set *exceptset;
+  /** don't signal the same semaphore twice: set to 1 when signalled */
+  int sem_signalled;
+  /** semaphore to wake up a task waiting for select */
+  sys_sem_t sem;
+};
+
+/** This struct is used to pass data to the set/getsockopt_internal
+ * functions running in tcpip_thread context (only a void* is allowed) */
+struct lwip_setgetsockopt_data {
+  /** socket struct for which to change options */
+  struct lwip_socket *sock;
+  /** socket index for which to change options */
+  int s;
+  /** level of the option to process */
+  int level;
+  /** name of the option to process */
+  int optname;
+  /** set: value to set the option to
+    * get: value of the option is stored here */
+  void *optval;
+  /** size of *optval */
+  socklen_t *optlen;
+  /** if an error occures, it is temporarily stored here */
+  err_t err;
+};
+
+/** The global array of available sockets */
+static struct lwip_socket sockets[NUM_SOCKETS];
+/** The global list of tasks waiting for select */
+static struct lwip_select_cb *select_cb_list;
+
+/** Semaphore protecting the sockets array */
+static sys_sem_t socksem;
+/** Semaphore protecting select_cb_list */
+static sys_sem_t selectsem;
+
+/** Table to quickly map an lwIP error (err_t) to a socket error
+  * by using -err as an index */
+static const int err_to_errno_table[] = {
+  0,             /* ERR_OK          0      No error, everything OK. */
+  ENOMEM,        /* ERR_MEM        -1      Out of memory error.     */
+  ENOBUFS,       /* ERR_BUF        -2      Buffer error.            */
+  EHOSTUNREACH,  /* ERR_RTE        -3      Routing problem.         */
+  ECONNABORTED,  /* ERR_ABRT       -4      Connection aborted.      */
+  ECONNRESET,    /* ERR_RST        -5      Connection reset.        */
+  ESHUTDOWN,     /* ERR_CLSD       -6      Connection closed.       */
+  ENOTCONN,      /* ERR_CONN       -7      Not connected.           */
+  EINVAL,        /* ERR_VAL        -8      Illegal value.           */
+  EIO,           /* ERR_ARG        -9      Illegal argument.        */
+  EADDRINUSE,    /* ERR_USE        -10     Address in use.          */
+  -1,            /* ERR_IF         -11     Low-level netif error    */
+  -1,            /* ERR_ISCONN     -12     Already connected.       */
+  ETIMEDOUT,     /* ERR_TIMEOUT    -13     Timeout                  */
+  EINPROGRESS    /* ERR_INPROGRESS -14     Operation in progress    */
+};
+
+#define ERR_TO_ERRNO_TABLE_SIZE \
+  (sizeof(err_to_errno_table)/sizeof(err_to_errno_table[0]))
+
+#define err_to_errno(err) \
+  ((unsigned)(-(err)) < ERR_TO_ERRNO_TABLE_SIZE ? \
+    err_to_errno_table[-(err)] : EIO)
+
+#ifdef ERRNO
+#define set_errno(err) errno = (err)
+#else
+#define set_errno(err)
+#endif
+
+#define sock_set_errno(sk, e) do { \
+  sk->err = (e); \
+  set_errno(sk->err); \
+} while (0)
+
+/* Forward delcaration of some functions */
+static void event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len);
+static void lwip_getsockopt_internal(void *arg);
+static void lwip_setsockopt_internal(void *arg);
+
+/**
+ * Initialize this module. This function has to be called before any other
+ * functions in this module!
+ */
+void
+lwip_socket_init(void)
+{
+  socksem   = sys_sem_new(1);
+  selectsem = sys_sem_new(1);
+}
+
+/**
+ * Map a externally used socket index to the internal socket representation.
+ *
+ * @param s externally used socket index
+ * @return struct lwip_socket for the socket or NULL if not found
+ */
+static struct lwip_socket *
+get_socket(int s)
+{
+  struct lwip_socket *sock;
+
+  if ((s < 0) || (s >= NUM_SOCKETS)) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): invalid\n", s));
+    set_errno(EBADF);
+    return NULL;
+  }
+
+  sock = &sockets[s];
+
+  if (!sock->conn) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): not active\n", s));
+    set_errno(EBADF);
+    return NULL;
+  }
+
+  return sock;
+}
+
+/**
+ * Allocate a new socket for a given netconn.
+ *
+ * @param newconn the netconn for which to allocate a socket
+ * @return the index of the new socket; -1 on error
+ */
+static int
+alloc_socket(struct netconn *newconn)
+{
+  int i;
+
+  /* Protect socket array */
+  sys_sem_wait(socksem);
+
+  /* allocate a new socket identifier */
+  for (i = 0; i < NUM_SOCKETS; ++i) {
+    if (!sockets[i].conn) {
+      sockets[i].conn       = newconn;
+      sockets[i].lastdata   = NULL;
+      sockets[i].lastoffset = 0;
+      sockets[i].rcvevent   = 0;
+      sockets[i].sendevent  = 1; /* TCP send buf is empty */
+      sockets[i].flags      = 0;
+      sockets[i].err        = 0;
+      sys_sem_signal(socksem);
+      return i;
+    }
+  }
+  sys_sem_signal(socksem);
+  return -1;
+}
+
+/* Below this, the well-known socket functions are implemented.
+ * Use google.com or opengroup.org to get a good description :-)
+ *
+ * Exceptions are documented!
+ */
+
+int
+lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen)
+{
+  struct lwip_socket *sock, *nsock;
+  struct netconn *newconn;
+  struct ip_addr naddr;
+  u16_t port;
+  int newsock;
+  struct sockaddr_in sin;
+  err_t err;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d)...\n", s));
+  sock = get_socket(s);
+  if (!sock)
+    return -1;
+
+  newconn = netconn_accept(sock->conn);
+  if (!newconn) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) failed, err=%d\n", s, sock->conn->err));
+    sock_set_errno(sock, err_to_errno(sock->conn->err));
+    return -1;
+  }
+
+  /* get the IP address and port of the remote host */
+  err = netconn_peer(newconn, &naddr, &port);
+  if (err != ERR_OK) {
+    netconn_delete(newconn);
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  memset(&sin, 0, sizeof(sin));
+  sin.sin_len = sizeof(sin);
+  sin.sin_family = AF_INET;
+  sin.sin_port = htons(port);
+  sin.sin_addr.s_addr = naddr.addr;
+
+  if (*addrlen > sizeof(sin))
+    *addrlen = sizeof(sin);
+
+  SMEMCPY(addr, &sin, *addrlen);
+
+  newsock = alloc_socket(newconn);
+  if (newsock == -1) {
+    netconn_delete(newconn);
+    sock_set_errno(sock, ENFILE);
+    return -1;
+  }
+  LWIP_ASSERT("invalid socket index", (newsock >= 0) && (newsock < NUM_SOCKETS));
+  newconn->callback = event_callback;
+  nsock = &sockets[newsock];
+  LWIP_ASSERT("invalid socket pointer", nsock != NULL);
+
+  sys_sem_wait(socksem);
+  /* See event_callback: If data comes in right away after an accept, even
+   * though the server task might not have created a new socket yet.
+   * In that case, newconn->socket is counted down (newconn->socket--),
+   * so nsock->rcvevent is >= 1 here!
+   */
+  nsock->rcvevent += -1 - newconn->socket;
+  newconn->socket = newsock;
+  sys_sem_signal(socksem);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d addr=", s, newsock));
+  ip_addr_debug_print(SOCKETS_DEBUG, &naddr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", port));
+
+  sock_set_errno(sock, 0);
+  return newsock;
+}
+
+int
+lwip_bind(int s, struct sockaddr *name, socklen_t namelen)
+{
+  struct lwip_socket *sock;
+  struct ip_addr local_addr;
+  u16_t local_port;
+  err_t err;
+
+  sock = get_socket(s);
+  if (!sock)
+    return -1;
+
+  LWIP_ERROR("lwip_bind: invalid address", ((namelen == sizeof(struct sockaddr_in)) &&
+             ((((struct sockaddr_in *)name)->sin_family) == AF_INET)),
+             sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;);
+
+  local_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr;
+  local_port = ((struct sockaddr_in *)name)->sin_port;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d, addr=", s));
+  ip_addr_debug_print(SOCKETS_DEBUG, &local_addr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(local_port)));
+
+  err = netconn_bind(sock->conn, &local_addr, ntohs(local_port));
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) succeeded\n", s));
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_close(int s)
+{
+  struct lwip_socket *sock;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_close(%d)\n", s));
+
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+
+  netconn_delete(sock->conn);
+
+  sys_sem_wait(socksem);
+  if (sock->lastdata) {
+    netbuf_delete(sock->lastdata);
+  }
+  sock->lastdata   = NULL;
+  sock->lastoffset = 0;
+  sock->conn       = NULL;
+  sock_set_errno(sock, 0);
+  sys_sem_signal(socksem);
+  return 0;
+}
+
+int
+lwip_connect(int s, const struct sockaddr *name, socklen_t namelen)
+{
+  struct lwip_socket *sock;
+  err_t err;
+
+  sock = get_socket(s);
+  if (!sock)
+    return -1;
+
+  LWIP_ERROR("lwip_connect: invalid address", ((namelen == sizeof(struct sockaddr_in)) &&
+             ((((struct sockaddr_in *)name)->sin_family) == AF_INET)),
+             sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;);
+
+  if (((struct sockaddr_in *)name)->sin_family == AF_UNSPEC) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, AF_UNSPEC)\n", s));
+    err = netconn_disconnect(sock->conn);
+  } else {
+    struct ip_addr remote_addr;
+    u16_t remote_port;
+
+    remote_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr;
+    remote_port = ((struct sockaddr_in *)name)->sin_port;
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, addr=", s));
+    ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr);
+    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(remote_port)));
+
+    err = netconn_connect(sock->conn, &remote_addr, ntohs(remote_port));
+  }
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) succeeded\n", s));
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+/**
+ * Set a socket into listen mode.
+ * The socket may not have been used for another connection previously.
+ *
+ * @param s the socket to set to listening mode
+ * @param backlog (ATTENTION: need TCP_LISTEN_BACKLOG=1)
+ * @return 0 on success, non-zero on failure
+ */
+int
+lwip_listen(int s, int backlog)
+{
+  struct lwip_socket *sock;
+  err_t err;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d, backlog=%d)\n", s, backlog));
+
+  sock = get_socket(s);
+  if (!sock)
+    return -1;
+
+  /* limit the "backlog" parameter to fit in an u8_t */
+  if (backlog < 0) {
+    backlog = 0;
+  }
+  if (backlog > 0xff) {
+    backlog = 0xff;
+  }
+
+  err = netconn_listen_with_backlog(sock->conn, backlog);
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d) failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_recvfrom(int s, void *mem, int len, unsigned int flags,
+        struct sockaddr *from, socklen_t *fromlen)
+{
+  struct lwip_socket *sock;
+  struct netbuf      *buf;
+  u16_t               buflen, copylen, off = 0;
+  struct ip_addr     *addr;
+  u16_t               port;
+  u8_t                done = 0;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d, %p, %d, 0x%x, ..)\n", s, mem, len, flags));
+  sock = get_socket(s);
+  if (!sock)
+    return -1;
+
+  do {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: top while sock->lastdata=%p\n", (void*)sock->lastdata));
+    /* Check if there is data left from the last recv operation. */
+    if (sock->lastdata) {
+      buf = sock->lastdata;
+    } else {
+      /* If this is non-blocking call, then check first */
+      if (((flags & MSG_DONTWAIT) || (sock->flags & O_NONBLOCK)) && !sock->rcvevent) {
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): returning EWOULDBLOCK\n", s));
+        sock_set_errno(sock, EWOULDBLOCK);
+        return -1;
+      }
+
+      /* No data was left from the previous operation, so we try to get
+      some from the network. */
+      sock->lastdata = buf = netconn_recv(sock->conn);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: netconn_recv netbuf=%p\n", (void*)buf));
+
+      if (!buf) {
+        /* We should really do some error checking here. */
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): buf == NULL!\n", s));
+        sock_set_errno(sock, (((sock->conn->pcb.ip!=NULL) && (sock->conn->err==ERR_OK))?ETIMEDOUT:err_to_errno(sock->conn->err)));
+        return 0;
+      }
+    }
+
+    buflen = netbuf_len(buf);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: buflen=%d len=%d off=%d sock->lastoffset=%d\n", buflen, len, off, sock->lastoffset));
+
+    buflen -= sock->lastoffset;
+
+    if (len > buflen) {
+      copylen = buflen;
+    } else {
+      copylen = len;
+    }
+
+    /* copy the contents of the received buffer into
+    the supplied memory pointer mem */
+    netbuf_copy_partial(buf, (u8_t*)mem + off, copylen, sock->lastoffset);
+
+    off += copylen;
+
+    if (netconn_type(sock->conn) == NETCONN_TCP) {
+      len -= copylen;
+      if ( (len <= 0) || (buf->p->flags & PBUF_FLAG_PUSH) || !sock->rcvevent) {
+        done = 1;
+      }
+    } else {
+      done = 1;
+    }
+
+    /* If we don't peek the incoming message... */
+    if ((flags & MSG_PEEK)==0) {
+      /* If this is a TCP socket, check if there is data left in the
+         buffer. If so, it should be saved in the sock structure for next
+         time around. */
+      if ((sock->conn->type == NETCONN_TCP) && (buflen - copylen > 0)) {
+        sock->lastdata = buf;
+        sock->lastoffset += copylen;
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: lastdata now netbuf=%p\n", (void*)buf));
+      } else {
+        sock->lastdata = NULL;
+        sock->lastoffset = 0;
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: deleting netbuf=%p\n", (void*)buf));
+        netbuf_delete(buf);
+      }
+    } else {
+      done = 1;
+    }
+  } while (!done);
+
+  /* Check to see from where the data was.*/
+  if (from && fromlen) {
+    struct sockaddr_in sin;
+
+    if (netconn_type(sock->conn) == NETCONN_TCP) {
+      addr = (struct ip_addr*)&(sin.sin_addr.s_addr);
+      netconn_getaddr(sock->conn, addr, &port, 0);
+    } else {
+      addr = netbuf_fromaddr(buf);
+      port = netbuf_fromport(buf);
+    }
+
+    memset(&sin, 0, sizeof(sin));
+    sin.sin_len = sizeof(sin);
+    sin.sin_family = AF_INET;
+    sin.sin_port = htons(port);
+    sin.sin_addr.s_addr = addr->addr;
+
+    if (*fromlen > sizeof(sin))
+      *fromlen = sizeof(sin);
+
+    SMEMCPY(from, &sin, *fromlen);
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s));
+    ip_addr_debug_print(SOCKETS_DEBUG, addr);
+    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, off));
+  } else {
+#if SOCKETS_DEBUG
+    struct sockaddr_in sin;
+
+    if (netconn_type(sock->conn) == NETCONN_TCP) {
+      addr = (struct ip_addr*)&(sin.sin_addr.s_addr);
+      netconn_getaddr(sock->conn, addr, &port, 0);
+    } else {
+      addr = netbuf_fromaddr(buf);
+      port = netbuf_fromport(buf);
+    }
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s));
+    ip_addr_debug_print(SOCKETS_DEBUG, addr);
+    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, off));
+#endif /*  SOCKETS_DEBUG */
+  }
+
+  sock_set_errno(sock, 0);
+  return off;
+}
+
+int
+lwip_read(int s, void *mem, int len)
+{
+  return lwip_recvfrom(s, mem, len, 0, NULL, NULL);
+}
+
+int
+lwip_recv(int s, void *mem, int len, unsigned int flags)
+{
+  return lwip_recvfrom(s, mem, len, flags, NULL, NULL);
+}
+
+int
+lwip_send(int s, const void *data, int size, unsigned int flags)
+{
+  struct lwip_socket *sock;
+  err_t err;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d, data=%p, size=%d, flags=0x%x)\n",
+                              s, data, size, flags));
+
+  sock = get_socket(s);
+  if (!sock)
+    return -1;
+
+  if (sock->conn->type!=NETCONN_TCP) {
+#if (LWIP_UDP || LWIP_RAW)
+    return lwip_sendto(s, data, size, flags, NULL, 0);
+#else
+    sock_set_errno(sock, err_to_errno(ERR_ARG));
+    return -1;
+#endif /* (LWIP_UDP || LWIP_RAW) */
+  }
+
+  err = netconn_write(sock->conn, data, size, NETCONN_COPY | ((flags & MSG_MORE)?NETCONN_MORE:0));
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) err=%d size=%d\n", s, err, size));
+  sock_set_errno(sock, err_to_errno(err));
+  return (err==ERR_OK?size:-1);
+}
+
+int
+lwip_sendto(int s, const void *data, int size, unsigned int flags,
+       struct sockaddr *to, socklen_t tolen)
+{
+  struct lwip_socket *sock;
+  struct ip_addr remote_addr;
+  int err;
+#if !LWIP_TCPIP_CORE_LOCKING
+  struct netbuf buf;
+  u16_t remote_port;
+#endif
+
+  sock = get_socket(s);
+  if (!sock)
+    return -1;
+
+  if (sock->conn->type==NETCONN_TCP) {
+#if LWIP_TCP
+    return lwip_send(s, data, size, flags);
+#else
+    sock_set_errno(sock, err_to_errno(ERR_ARG));
+    return -1;
+#endif /* LWIP_TCP */
+  }
+
+  LWIP_ASSERT("lwip_sendto: size must fit in u16_t",
+              ((size >= 0) && (size <= 0xffff)));
+  LWIP_ERROR("lwip_sendto: invalid address", (((to == NULL) && (tolen == 0)) ||
+             ((tolen == sizeof(struct sockaddr_in)) &&
+             ((((struct sockaddr_in *)to)->sin_family) == AF_INET))),
+             sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;);
+
+#if LWIP_TCPIP_CORE_LOCKING
+  /* Should only be consider like a sample or a simple way to experiment this option (no check of "to" field...) */
+  { struct pbuf* p;
+
+    p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF);
+    if (p == NULL) {
+      err = ERR_MEM;
+    } else {
+      p->payload = (void*)data;
+      p->len = p->tot_len = size;
+
+      remote_addr.addr = ((struct sockaddr_in *)to)->sin_addr.s_addr;
+
+      LOCK_TCPIP_CORE();
+      if (sock->conn->type==NETCONN_RAW) {
+        err = sock->conn->err = raw_sendto(sock->conn->pcb.raw, p, &remote_addr);
+      } else {
+        err = sock->conn->err = udp_sendto(sock->conn->pcb.udp, p, &remote_addr, ntohs(((struct sockaddr_in *)to)->sin_port));
+      }
+      UNLOCK_TCPIP_CORE();
+
+      pbuf_free(p);
+    }
+  }
+#else
+  /* initialize a buffer */
+  buf.p = buf.ptr = NULL;
+  if (to) {
+    remote_addr.addr = ((struct sockaddr_in *)to)->sin_addr.s_addr;
+    remote_port      = ntohs(((struct sockaddr_in *)to)->sin_port);
+    buf.addr         = &remote_addr;
+    buf.port         = remote_port;
+  } else {
+    remote_addr.addr = 0;
+    remote_port      = 0;
+    buf.addr         = NULL;
+    buf.port         = 0;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_sendto(%d, data=%p, size=%d, flags=0x%x to=",
+              s, data, size, flags));
+  ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", remote_port));
+
+  /* make the buffer point to the data that should be sent */
+  if ((err = netbuf_ref(&buf, data, size)) == ERR_OK) {
+    /* send the data */
+    err = netconn_send(sock->conn, &buf);
+  }
+
+  /* deallocated the buffer */
+  if (buf.p != NULL) {
+    pbuf_free(buf.p);
+  }
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+  sock_set_errno(sock, err_to_errno(err));
+  return (err==ERR_OK?size:-1);
+}
+
+int
+lwip_socket(int domain, int type, int protocol)
+{
+  struct netconn *conn;
+  int i;
+
+  LWIP_UNUSED_ARG(domain);
+
+  /* create a netconn */
+  switch (type) {
+  case SOCK_RAW:
+    conn = netconn_new_with_proto_and_callback(NETCONN_RAW, (u8_t)protocol, event_callback);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_RAW, %d) = ",
+                                 domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+    break;
+  case SOCK_DGRAM:
+    conn = netconn_new_with_callback( (protocol == IPPROTO_UDPLITE) ?
+                 NETCONN_UDPLITE : NETCONN_UDP, event_callback);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_DGRAM, %d) = ",
+                                 domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+    break;
+  case SOCK_STREAM:
+    conn = netconn_new_with_callback(NETCONN_TCP, event_callback);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_STREAM, %d) = ",
+                                 domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+    break;
+  default:
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%d, %d/UNKNOWN, %d) = -1\n",
+                                 domain, type, protocol));
+    set_errno(EINVAL);
+    return -1;
+  }
+
+  if (!conn) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("-1 / ENOBUFS (could not create netconn)\n"));
+    set_errno(ENOBUFS);
+    return -1;
+  }
+
+  i = alloc_socket(conn);
+
+  if (i == -1) {
+    netconn_delete(conn);
+    set_errno(ENFILE);
+    return -1;
+  }
+  conn->socket = i;
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("%d\n", i));
+  set_errno(0);
+  return i;
+}
+
+int
+lwip_write(int s, const void *data, int size)
+{
+  return lwip_send(s, data, size, 0);
+}
+
+/**
+ * Go through the readset and writeset lists and see which socket of the sockets
+ * set in the sets has events. On return, readset, writeset and exceptset have
+ * the sockets enabled that had events.
+ *
+ * exceptset is not used for now!!!
+ *
+ * @param maxfdp1 the highest socket index in the sets
+ * @param readset in: set of sockets to check for read events;
+ *                out: set of sockets that had read events
+ * @param writeset in: set of sockets to check for write events;
+ *                 out: set of sockets that had write events
+ * @param exceptset not yet implemented
+ * @return number of sockets that had events (read+write)
+ */
+static int
+lwip_selscan(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset)
+{
+  int i, nready = 0;
+  fd_set lreadset, lwriteset, lexceptset;
+  struct lwip_socket *p_sock;
+
+  FD_ZERO(&lreadset);
+  FD_ZERO(&lwriteset);
+  FD_ZERO(&lexceptset);
+
+  /* Go through each socket in each list to count number of sockets which
+  currently match */
+  for(i = 0; i < maxfdp1; i++) {
+    if (FD_ISSET(i, readset)) {
+      /* See if netconn of this socket is ready for read */
+      p_sock = get_socket(i);
+      if (p_sock && (p_sock->lastdata || p_sock->rcvevent)) {
+        FD_SET(i, &lreadset);
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for reading\n", i));
+        nready++;
+      }
+    }
+    if (FD_ISSET(i, writeset)) {
+      /* See if netconn of this socket is ready for write */
+      p_sock = get_socket(i);
+      if (p_sock && p_sock->sendevent) {
+        FD_SET(i, &lwriteset);
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for writing\n", i));
+        nready++;
+      }
+    }
+  }
+  *readset = lreadset;
+  *writeset = lwriteset;
+  FD_ZERO(exceptset);
+
+  return nready;
+}
+
+
+/**
+ * Processing exceptset is not yet implemented.
+ */
+int
+lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
+               struct timeval *timeout)
+{
+  int i;
+  int nready;
+  fd_set lreadset, lwriteset, lexceptset;
+  u32_t msectimeout;
+  struct lwip_select_cb select_cb;
+  struct lwip_select_cb *p_selcb;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select(%d, %p, %p, %p, tvsec=%ld tvusec=%ld)\n",
+                  maxfdp1, (void *)readset, (void *) writeset, (void *) exceptset,
+                  timeout ? timeout->tv_sec : -1L, timeout ? timeout->tv_usec : -1L));
+
+  select_cb.next = 0;
+  select_cb.readset = readset;
+  select_cb.writeset = writeset;
+  select_cb.exceptset = exceptset;
+  select_cb.sem_signalled = 0;
+
+  /* Protect ourselves searching through the list */
+  sys_sem_wait(selectsem);
+
+  if (readset)
+    lreadset = *readset;
+  else
+    FD_ZERO(&lreadset);
+  if (writeset)
+    lwriteset = *writeset;
+  else
+    FD_ZERO(&lwriteset);
+  if (exceptset)
+    lexceptset = *exceptset;
+  else
+    FD_ZERO(&lexceptset);
+
+  /* Go through each socket in each list to count number of sockets which
+     currently match */
+  nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset);
+
+  /* If we don't have any current events, then suspend if we are supposed to */
+  if (!nready) {
+    if (timeout && timeout->tv_sec == 0 && timeout->tv_usec == 0) {
+      sys_sem_signal(selectsem);
+      if (readset)
+        FD_ZERO(readset);
+      if (writeset)
+        FD_ZERO(writeset);
+      if (exceptset)
+        FD_ZERO(exceptset);
+
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: no timeout, returning 0\n"));
+      set_errno(0);
+
+      return 0;
+    }
+
+    /* add our semaphore to list */
+    /* We don't actually need any dynamic memory. Our entry on the
+     * list is only valid while we are in this function, so it's ok
+     * to use local variables */
+
+    select_cb.sem = sys_sem_new(0);
+    /* Note that we are still protected */
+    /* Put this select_cb on top of list */
+    select_cb.next = select_cb_list;
+    select_cb_list = &select_cb;
+
+    /* Now we can safely unprotect */
+    sys_sem_signal(selectsem);
+
+    /* Now just wait to be woken */
+    if (timeout == 0)
+      /* Wait forever */
+      msectimeout = 0;
+    else {
+      msectimeout =  ((timeout->tv_sec * 1000) + ((timeout->tv_usec + 500)/1000));
+      if(msectimeout == 0)
+        msectimeout = 1;
+    }
+
+    i = sys_sem_wait_timeout(select_cb.sem, msectimeout);
+
+    /* Take us off the list */
+    sys_sem_wait(selectsem);
+    if (select_cb_list == &select_cb)
+      select_cb_list = select_cb.next;
+    else
+      for (p_selcb = select_cb_list; p_selcb; p_selcb = p_selcb->next) {
+        if (p_selcb->next == &select_cb) {
+          p_selcb->next = select_cb.next;
+          break;
+        }
+      }
+
+    sys_sem_signal(selectsem);
+
+    sys_sem_free(select_cb.sem);
+    if (i == 0)  {
+      /* Timeout */
+      if (readset)
+        FD_ZERO(readset);
+      if (writeset)
+        FD_ZERO(writeset);
+      if (exceptset)
+        FD_ZERO(exceptset);
+
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: timeout expired\n"));
+      set_errno(0);
+
+      return 0;
+    }
+
+    if (readset)
+      lreadset = *readset;
+    else
+      FD_ZERO(&lreadset);
+    if (writeset)
+      lwriteset = *writeset;
+    else
+      FD_ZERO(&lwriteset);
+    if (exceptset)
+      lexceptset = *exceptset;
+    else
+      FD_ZERO(&lexceptset);
+
+    /* See what's set */
+    nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset);
+  } else
+    sys_sem_signal(selectsem);
+
+  if (readset)
+    *readset = lreadset;
+  if (writeset)
+    *writeset = lwriteset;
+  if (exceptset)
+    *exceptset = lexceptset;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: nready=%d\n", nready));
+  set_errno(0);
+
+  return nready;
+}
+
+/**
+ * Callback registered in the netconn layer for each socket-netconn.
+ * Processes recvevent (data available) and wakes up tasks waiting for select.
+ */
+static void
+event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len)
+{
+  int s;
+  struct lwip_socket *sock;
+  struct lwip_select_cb *scb;
+
+  LWIP_UNUSED_ARG(len);
+
+  /* Get socket */
+  if (conn) {
+    s = conn->socket;
+    if (s < 0) {
+      /* Data comes in right away after an accept, even though
+       * the server task might not have created a new socket yet.
+       * Just count down (or up) if that's the case and we
+       * will use the data later. Note that only receive events
+       * can happen before the new socket is set up. */
+      sys_sem_wait(socksem);
+      if (conn->socket < 0) {
+        if (evt == NETCONN_EVT_RCVPLUS) {
+          conn->socket--;
+        }
+        sys_sem_signal(socksem);
+        return;
+      }
+      sys_sem_signal(socksem);
+    }
+
+    sock = get_socket(s);
+    if (!sock) {
+      return;
+    }
+  } else {
+    return;
+  }
+
+  sys_sem_wait(selectsem);
+  /* Set event as required */
+  switch (evt) {
+    case NETCONN_EVT_RCVPLUS:
+      sock->rcvevent++;
+      break;
+    case NETCONN_EVT_RCVMINUS:
+      sock->rcvevent--;
+      break;
+    case NETCONN_EVT_SENDPLUS:
+      sock->sendevent = 1;
+      break;
+    case NETCONN_EVT_SENDMINUS:
+      sock->sendevent = 0;
+      break;
+    default:
+      LWIP_ASSERT("unknown event", 0);
+      break;
+  }
+  sys_sem_signal(selectsem);
+
+  /* Now decide if anyone is waiting for this socket */
+  /* NOTE: This code is written this way to protect the select link list
+     but to avoid a deadlock situation by releasing socksem before
+     signalling for the select. This means we need to go through the list
+     multiple times ONLY IF a select was actually waiting. We go through
+     the list the number of waiting select calls + 1. This list is
+     expected to be small. */
+  while (1) {
+    sys_sem_wait(selectsem);
+    for (scb = select_cb_list; scb; scb = scb->next) {
+      if (scb->sem_signalled == 0) {
+        /* Test this select call for our socket */
+        if (scb->readset && FD_ISSET(s, scb->readset))
+          if (sock->rcvevent)
+            break;
+        if (scb->writeset && FD_ISSET(s, scb->writeset))
+          if (sock->sendevent)
+            break;
+      }
+    }
+    if (scb) {
+      scb->sem_signalled = 1;
+      sys_sem_signal(selectsem);
+      sys_sem_signal(scb->sem);
+    } else {
+      sys_sem_signal(selectsem);
+      break;
+    }
+  }
+}
+
+/**
+ * Unimplemented: Close one end of a full-duplex connection.
+ * Currently, the full connection is closed.
+ */
+int
+lwip_shutdown(int s, int how)
+{
+  LWIP_UNUSED_ARG(how);
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_shutdown(%d, how=%d)\n", s, how));
+  return lwip_close(s); /* XXX temporary hack until proper implementation */
+}
+
+static int
+lwip_getaddrname(int s, struct sockaddr *name, socklen_t *namelen, u8_t local)
+{
+  struct lwip_socket *sock;
+  struct sockaddr_in sin;
+  struct ip_addr naddr;
+
+  sock = get_socket(s);
+  if (!sock)
+    return -1;
+
+  memset(&sin, 0, sizeof(sin));
+  sin.sin_len = sizeof(sin);
+  sin.sin_family = AF_INET;
+
+  /* get the IP address and port */
+  netconn_getaddr(sock->conn, &naddr, &sin.sin_port, local);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getaddrname(%d, addr=", s));
+  ip_addr_debug_print(SOCKETS_DEBUG, &naddr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%d)\n", sin.sin_port));
+
+  sin.sin_port = htons(sin.sin_port);
+  sin.sin_addr.s_addr = naddr.addr;
+
+  if (*namelen > sizeof(sin))
+    *namelen = sizeof(sin);
+
+  SMEMCPY(name, &sin, *namelen);
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_getpeername(int s, struct sockaddr *name, socklen_t *namelen)
+{
+  return lwip_getaddrname(s, name, namelen, 0);
+}
+
+int
+lwip_getsockname(int s, struct sockaddr *name, socklen_t *namelen)
+{
+  return lwip_getaddrname(s, name, namelen, 1);
+}
+
+int
+lwip_getsockopt(int s, int level, int optname, void *optval, socklen_t *optlen)
+{
+  err_t err = ERR_OK;
+  struct lwip_socket *sock = get_socket(s);
+  struct lwip_setgetsockopt_data data;
+
+  if (!sock)
+    return -1;
+
+  if ((NULL == optval) || (NULL == optlen)) {
+    sock_set_errno(sock, EFAULT);
+    return -1;
+  }
+
+  /* Do length and type checks for the various options first, to keep it readable. */
+  switch (level) {
+
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch (optname) {
+
+    case SO_ACCEPTCONN:
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_ERROR:
+    case SO_KEEPALIVE:
+    /* UNIMPL case SO_CONTIMEO: */
+    /* UNIMPL case SO_SNDTIMEO: */
+#if LWIP_SO_RCVTIMEO
+    case SO_RCVTIMEO:
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+    case SO_RCVBUF:
+#endif /* LWIP_SO_RCVBUF */
+    /* UNIMPL case SO_OOBINLINE: */
+    /* UNIMPL case SO_SNDBUF: */
+    /* UNIMPL case SO_RCVLOWAT: */
+    /* UNIMPL case SO_SNDLOWAT: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    case SO_TYPE:
+    /* UNIMPL case SO_USELOOPBACK: */
+      if (*optlen < sizeof(int)) {
+        err = EINVAL;
+      }
+      break;
+
+    case SO_NO_CHECK:
+      if (*optlen < sizeof(int)) {
+        err = EINVAL;
+      }
+#if LWIP_UDP
+      if ((sock->conn->type != NETCONN_UDP) ||
+          ((udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_UDPLITE) != 0)) {
+        /* this flag is only available for UDP, not for UDP lite */
+        err = EAFNOSUPPORT;
+      }
+#endif /* LWIP_UDP */
+      break;
+
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n",
+                                  s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch (optname) {
+    /* UNIMPL case IP_HDRINCL: */
+    /* UNIMPL case IP_RCVDSTADDR: */
+    /* UNIMPL case IP_RCVIF: */
+    case IP_TTL:
+    case IP_TOS:
+      if (*optlen < sizeof(int)) {
+        err = EINVAL;
+      }
+      break;
+#if LWIP_IGMP
+    case IP_MULTICAST_TTL:
+      if (*optlen < sizeof(u8_t)) {
+        err = EINVAL;
+      }
+      break;
+    case IP_MULTICAST_IF:
+      if (*optlen < sizeof(struct in_addr)) {
+        err = EINVAL;
+      }
+      break;
+#endif /* LWIP_IGMP */
+
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n",
+                                  s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+
+#if LWIP_TCP
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    if (*optlen < sizeof(int)) {
+      err = EINVAL;
+      break;
+    }
+
+    /* If this is no TCP socket, ignore any options. */
+    if (sock->conn->type != NETCONN_TCP)
+      return 0;
+
+    switch (optname) {
+    case TCP_NODELAY:
+    case TCP_KEEPALIVE:
+#if LWIP_TCP_KEEPALIVE
+    case TCP_KEEPIDLE:
+    case TCP_KEEPINTVL:
+    case TCP_KEEPCNT:
+#endif /* LWIP_TCP_KEEPALIVE */
+      break;
+
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n",
+                                  s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_TCP */
+#if LWIP_UDP && LWIP_UDPLITE
+/* Level: IPPROTO_UDPLITE */
+  case IPPROTO_UDPLITE:
+    if (*optlen < sizeof(int)) {
+      err = EINVAL;
+      break;
+    }
+
+    /* If this is no UDP lite socket, ignore any options. */
+    if (sock->conn->type != NETCONN_UDPLITE)
+      return 0;
+
+    switch (optname) {
+    case UDPLITE_SEND_CSCOV:
+    case UDPLITE_RECV_CSCOV:
+      break;
+
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UNIMPL: optname=0x%x, ..)\n",
+                                  s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_UDP && LWIP_UDPLITE*/
+/* UNDEFINED LEVEL */
+  default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n",
+                                  s, level, optname));
+      err = ENOPROTOOPT;
+  }  /* switch */
+
+
+  if (err != ERR_OK) {
+    sock_set_errno(sock, err);
+    return -1;
+  }
+
+  /* Now do the actual option processing */
+  data.sock = sock;
+  data.level = level;
+  data.optname = optname;
+  data.optval = optval;
+  data.optlen = optlen;
+  data.err = err;
+  tcpip_callback(lwip_getsockopt_internal, &data);
+  sys_arch_sem_wait(sock->conn->op_completed, 0);
+  /* maybe lwip_getsockopt_internal has changed err */
+  err = data.err;
+
+  sock_set_errno(sock, err);
+  return err ? -1 : 0;
+}
+
+static void
+lwip_getsockopt_internal(void *arg)
+{
+  struct lwip_socket *sock;
+#ifdef LWIP_DEBUG
+  int s;
+#endif /* LWIP_DEBUG */
+  int level, optname;
+  void *optval;
+  struct lwip_setgetsockopt_data *data;
+
+  LWIP_ASSERT("arg != NULL", arg != NULL);
+
+  data = (struct lwip_setgetsockopt_data*)arg;
+  sock = data->sock;
+#ifdef LWIP_DEBUG
+  s = data->s;
+#endif /* LWIP_DEBUG */
+  level = data->level;
+  optname = data->optname;
+  optval = data->optval;
+
+  switch (level) {
+
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch (optname) {
+
+    /* The option flags */
+    case SO_ACCEPTCONN:
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_KEEPALIVE:
+    /* UNIMPL case SO_OOBINCLUDE: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    /*case SO_USELOOPBACK: UNIMPL */
+      *(int*)optval = sock->conn->pcb.ip->so_options & optname;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, optname=0x%x, ..) = %s\n",
+                                  s, optname, (*(int*)optval?"on":"off")));
+      break;
+
+    case SO_TYPE:
+      switch (NETCONNTYPE_GROUP(sock->conn->type)) {
+      case NETCONN_RAW:
+        *(int*)optval = SOCK_RAW;
+        break;
+      case NETCONN_TCP:
+        *(int*)optval = SOCK_STREAM;
+        break;
+      case NETCONN_UDP:
+        *(int*)optval = SOCK_DGRAM;
+        break;
+      default: /* unrecognized socket type */
+        *(int*)optval = sock->conn->type;
+        LWIP_DEBUGF(SOCKETS_DEBUG,
+                    ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE): unrecognized socket type %d\n",
+                    s, *(int *)optval));
+      }  /* switch (sock->conn->type) */
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE) = %d\n",
+                  s, *(int *)optval));
+      break;
+
+    case SO_ERROR:
+      if (sock->err == 0) {
+        sock_set_errno(sock, err_to_errno(sock->conn->err));
+      }
+      *(int *)optval = sock->err;
+      sock->err = 0;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_ERROR) = %d\n",
+                  s, *(int *)optval));
+      break;
+
+#if LWIP_SO_RCVTIMEO
+    case SO_RCVTIMEO:
+      *(int *)optval = sock->conn->recv_timeout;
+      break;
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+    case SO_RCVBUF:
+      *(int *)optval = sock->conn->recv_bufsize;
+      break;
+#endif /* LWIP_SO_RCVBUF */
+#if LWIP_UDP
+    case SO_NO_CHECK:
+      *(int*)optval = (udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_NOCHKSUM) ? 1 : 0;
+      break;
+#endif /* LWIP_UDP*/
+    }  /* switch (optname) */
+    break;
+
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch (optname) {
+    case IP_TTL:
+      *(int*)optval = sock->conn->pcb.ip->ttl;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TTL) = %d\n",
+                  s, *(int *)optval));
+      break;
+    case IP_TOS:
+      *(int*)optval = sock->conn->pcb.ip->tos;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TOS) = %d\n",
+                  s, *(int *)optval));
+      break;
+#if LWIP_IGMP
+    case IP_MULTICAST_TTL:
+      *(u8_t*)optval = sock->conn->pcb.ip->ttl;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_TTL) = %d\n",
+                  s, *(int *)optval));
+      break;
+    case IP_MULTICAST_IF:
+      ((struct in_addr*) optval)->s_addr = sock->conn->pcb.udp->multicast_ip.addr;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_IF) = 0x%x\n",
+                  s, *(u32_t *)optval));
+      break;
+#endif /* LWIP_IGMP */
+    }  /* switch (optname) */
+    break;
+
+#if LWIP_TCP
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    switch (optname) {
+    case TCP_NODELAY:
+      *(int*)optval = (sock->conn->pcb.tcp->flags & TF_NODELAY);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_NODELAY) = %s\n",
+                  s, (*(int*)optval)?"on":"off") );
+      break;
+    case TCP_KEEPALIVE:
+      *(int*)optval = (int)sock->conn->pcb.tcp->keep_idle;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPALIVE) = %d\n",
+                  s, *(int *)optval));
+      break;
+
+#if LWIP_TCP_KEEPALIVE
+    case TCP_KEEPIDLE:
+      *(int*)optval = (int)(sock->conn->pcb.tcp->keep_idle/1000);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPIDLE) = %d\n",
+                  s, *(int *)optval));
+      break;
+    case TCP_KEEPINTVL:
+      *(int*)optval = (int)(sock->conn->pcb.tcp->keep_intvl/1000);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPINTVL) = %d\n",
+                  s, *(int *)optval));
+      break;
+    case TCP_KEEPCNT:
+      *(int*)optval = (int)sock->conn->pcb.tcp->keep_cnt;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPCNT) = %d\n",
+                  s, *(int *)optval));
+      break;
+#endif /* LWIP_TCP_KEEPALIVE */
+
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_TCP */
+#if LWIP_UDP && LWIP_UDPLITE
+  /* Level: IPPROTO_UDPLITE */
+  case IPPROTO_UDPLITE:
+    switch (optname) {
+    case UDPLITE_SEND_CSCOV:
+      *(int*)optval = sock->conn->pcb.udp->chksum_len_tx;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UDPLITE_SEND_CSCOV) = %d\n",
+                  s, (*(int*)optval)) );
+      break;
+    case UDPLITE_RECV_CSCOV:
+      *(int*)optval = sock->conn->pcb.udp->chksum_len_rx;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UDPLITE_RECV_CSCOV) = %d\n",
+                  s, (*(int*)optval)) );
+      break;
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_UDP */
+  } /* switch (level) */
+  sys_sem_signal(sock->conn->op_completed);
+}
+
+int
+lwip_setsockopt(int s, int level, int optname, const void *optval, socklen_t optlen)
+{
+  struct lwip_socket *sock = get_socket(s);
+  int err = ERR_OK;
+  struct lwip_setgetsockopt_data data;
+
+  if (!sock)
+    return -1;
+
+  if (NULL == optval) {
+    sock_set_errno(sock, EFAULT);
+    return -1;
+  }
+
+  /* Do length and type checks for the various options first, to keep it readable. */
+  switch (level) {
+
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch (optname) {
+
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_KEEPALIVE:
+    /* UNIMPL case case SO_CONTIMEO: */
+    /* UNIMPL case case SO_SNDTIMEO: */
+#if LWIP_SO_RCVTIMEO
+    case SO_RCVTIMEO:
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+    case SO_RCVBUF:
+#endif /* LWIP_SO_RCVBUF */
+    /* UNIMPL case SO_OOBINLINE: */
+    /* UNIMPL case SO_SNDBUF: */
+    /* UNIMPL case SO_RCVLOWAT: */
+    /* UNIMPL case SO_SNDLOWAT: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    /* UNIMPL case SO_USELOOPBACK: */
+      if (optlen < sizeof(int)) {
+        err = EINVAL;
+      }
+      break;
+    case SO_NO_CHECK:
+      if (optlen < sizeof(int)) {
+        err = EINVAL;
+      }
+#if LWIP_UDP
+      if ((sock->conn->type != NETCONN_UDP) ||
+          ((udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_UDPLITE) != 0)) {
+        /* this flag is only available for UDP, not for UDP lite */
+        err = EAFNOSUPPORT;
+      }
+#endif /* LWIP_UDP */
+      break;
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n",
+                  s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch (optname) {
+    /* UNIMPL case IP_HDRINCL: */
+    /* UNIMPL case IP_RCVDSTADDR: */
+    /* UNIMPL case IP_RCVIF: */
+    case IP_TTL:
+    case IP_TOS:
+      if (optlen < sizeof(int)) {
+        err = EINVAL;
+      }
+      break;
+#if LWIP_IGMP
+    case IP_MULTICAST_TTL:
+      if (optlen < sizeof(u8_t)) {
+        err = EINVAL;
+      }
+      if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_UDP) {
+        err = EAFNOSUPPORT;
+      }
+      break;
+    case IP_MULTICAST_IF:
+      if (optlen < sizeof(struct in_addr)) {
+        err = EINVAL;
+      }
+      if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_UDP) {
+        err = EAFNOSUPPORT;
+      }
+      break;
+    case IP_ADD_MEMBERSHIP:
+    case IP_DROP_MEMBERSHIP:
+      if (optlen < sizeof(struct ip_mreq)) {
+        err = EINVAL;
+      }
+      if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_UDP) {
+        err = EAFNOSUPPORT;
+      }
+      break;
+#endif /* LWIP_IGMP */
+      default:
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n",
+                    s, optname));
+        err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+
+#if LWIP_TCP
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    if (optlen < sizeof(int)) {
+      err = EINVAL;
+      break;
+    }
+
+    /* If this is no TCP socket, ignore any options. */
+    if (sock->conn->type != NETCONN_TCP)
+      return 0;
+
+    switch (optname) {
+    case TCP_NODELAY:
+    case TCP_KEEPALIVE:
+#if LWIP_TCP_KEEPALIVE
+    case TCP_KEEPIDLE:
+    case TCP_KEEPINTVL:
+    case TCP_KEEPCNT:
+#endif /* LWIP_TCP_KEEPALIVE */
+      break;
+
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n",
+                  s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_TCP */
+#if LWIP_UDP && LWIP_UDPLITE
+/* Level: IPPROTO_UDPLITE */
+  case IPPROTO_UDPLITE:
+    if (optlen < sizeof(int)) {
+      err = EINVAL;
+      break;
+    }
+
+    /* If this is no UDP lite socket, ignore any options. */
+    if (sock->conn->type != NETCONN_UDPLITE)
+      return 0;
+
+    switch (optname) {
+    case UDPLITE_SEND_CSCOV:
+    case UDPLITE_RECV_CSCOV:
+      break;
+
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UNIMPL: optname=0x%x, ..)\n",
+                  s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_UDP && LWIP_UDPLITE */
+/* UNDEFINED LEVEL */
+  default:
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n",
+                s, level, optname));
+    err = ENOPROTOOPT;
+  }  /* switch (level) */
+
+
+  if (err != ERR_OK) {
+    sock_set_errno(sock, err);
+    return -1;
+  }
+
+
+  /* Now do the actual option processing */
+  data.sock = sock;
+  data.level = level;
+  data.optname = optname;
+  data.optval = (void*)optval;
+  data.optlen = &optlen;
+  data.err = err;
+  tcpip_callback(lwip_setsockopt_internal, &data);
+  sys_arch_sem_wait(sock->conn->op_completed, 0);
+  /* maybe lwip_setsockopt_internal has changed err */
+  err = data.err;
+
+  sock_set_errno(sock, err);
+  return err ? -1 : 0;
+}
+
+static void
+lwip_setsockopt_internal(void *arg)
+{
+  struct lwip_socket *sock;
+#ifdef LWIP_DEBUG
+  int s;
+#endif /* LWIP_DEBUG */
+  int level, optname;
+  const void *optval;
+  struct lwip_setgetsockopt_data *data;
+
+  LWIP_ASSERT("arg != NULL", arg != NULL);
+
+  data = (struct lwip_setgetsockopt_data*)arg;
+  sock = data->sock;
+#ifdef LWIP_DEBUG
+  s = data->s;
+#endif /* LWIP_DEBUG */
+  level = data->level;
+  optname = data->optname;
+  optval = data->optval;
+
+  switch (level) {
+
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch (optname) {
+
+    /* The option flags */
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_KEEPALIVE:
+    /* UNIMPL case SO_OOBINCLUDE: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    /* UNIMPL case SO_USELOOPBACK: */
+      if (*(int*)optval) {
+        sock->conn->pcb.ip->so_options |= optname;
+      } else {
+        sock->conn->pcb.ip->so_options &= ~optname;
+      }
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, optname=0x%x, ..) -> %s\n",
+                  s, optname, (*(int*)optval?"on":"off")));
+      break;
+#if LWIP_SO_RCVTIMEO
+    case SO_RCVTIMEO:
+      sock->conn->recv_timeout = ( *(int*)optval );
+      break;
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+    case SO_RCVBUF:
+      sock->conn->recv_bufsize = ( *(int*)optval );
+      break;
+#endif /* LWIP_SO_RCVBUF */
+#if LWIP_UDP
+    case SO_NO_CHECK:
+      if (*(int*)optval) {
+        udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) | UDP_FLAGS_NOCHKSUM);
+      } else {
+        udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) & ~UDP_FLAGS_NOCHKSUM);
+      }
+      break;
+#endif /* LWIP_UDP */
+    }  /* switch (optname) */
+    break;
+
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch (optname) {
+    case IP_TTL:
+      sock->conn->pcb.ip->ttl = (u8_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TTL, ..) -> %u\n",
+                  s, sock->conn->pcb.ip->ttl));
+      break;
+    case IP_TOS:
+      sock->conn->pcb.ip->tos = (u8_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TOS, ..)-> %u\n",
+                  s, sock->conn->pcb.ip->tos));
+      break;
+#if LWIP_IGMP
+    case IP_MULTICAST_TTL:
+      sock->conn->pcb.udp->ttl = (u8_t)(*(u8_t*)optval);
+      break;
+    case IP_MULTICAST_IF:
+      sock->conn->pcb.udp->multicast_ip.addr = ((struct in_addr*) optval)->s_addr;
+      break;
+    case IP_ADD_MEMBERSHIP:
+    case IP_DROP_MEMBERSHIP:
+      {
+        /* If this is a TCP or a RAW socket, ignore these options. */
+        struct ip_mreq *imr = (struct ip_mreq *)optval;
+        if(optname == IP_ADD_MEMBERSHIP){
+          data->err = igmp_joingroup((struct ip_addr*)&(imr->imr_interface.s_addr), (struct ip_addr*)&(imr->imr_multiaddr.s_addr));
+        } else {
+          data->err = igmp_leavegroup((struct ip_addr*)&(imr->imr_interface.s_addr), (struct ip_addr*)&(imr->imr_multiaddr.s_addr));
+        }
+        if(data->err != ERR_OK) {
+          data->err = EADDRNOTAVAIL;
+        }
+      }
+      break;
+#endif /* LWIP_IGMP */
+    }  /* switch (optname) */
+    break;
+
+#if LWIP_TCP
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    switch (optname) {
+    case TCP_NODELAY:
+      if (*(int*)optval) {
+        sock->conn->pcb.tcp->flags |= TF_NODELAY;
+      } else {
+        sock->conn->pcb.tcp->flags &= ~TF_NODELAY;
+      }
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_NODELAY) -> %s\n",
+                  s, (*(int *)optval)?"on":"off") );
+      break;
+    case TCP_KEEPALIVE:
+      sock->conn->pcb.tcp->keep_idle = (u32_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) -> %lu\n",
+                  s, sock->conn->pcb.tcp->keep_idle));
+      break;
+
+#if LWIP_TCP_KEEPALIVE
+    case TCP_KEEPIDLE:
+      sock->conn->pcb.tcp->keep_idle = 1000*(u32_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPIDLE) -> %lu\n",
+                  s, sock->conn->pcb.tcp->keep_idle));
+      break;
+    case TCP_KEEPINTVL:
+      sock->conn->pcb.tcp->keep_intvl = 1000*(u32_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPINTVL) -> %lu\n",
+                  s, sock->conn->pcb.tcp->keep_intvl));
+      break;
+    case TCP_KEEPCNT:
+      sock->conn->pcb.tcp->keep_cnt = (u32_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPCNT) -> %lu\n",
+                  s, sock->conn->pcb.tcp->keep_cnt));
+      break;
+#endif /* LWIP_TCP_KEEPALIVE */
+
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_TCP*/
+#if LWIP_UDP && LWIP_UDPLITE
+  /* Level: IPPROTO_UDPLITE */
+  case IPPROTO_UDPLITE:
+    switch (optname) {
+    case UDPLITE_SEND_CSCOV:
+      if ((*(int*)optval != 0) && (*(int*)optval < 8)) {
+        /* don't allow illegal values! */
+        sock->conn->pcb.udp->chksum_len_tx = 8;
+      } else {
+        sock->conn->pcb.udp->chksum_len_tx = *(int*)optval;
+      }
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UDPLITE_SEND_CSCOV) -> %d\n",
+                  s, (*(int*)optval)) );
+      break;
+    case UDPLITE_RECV_CSCOV:
+      if ((*(int*)optval != 0) && (*(int*)optval < 8)) {
+        /* don't allow illegal values! */
+        sock->conn->pcb.udp->chksum_len_rx = 8;
+      } else {
+        sock->conn->pcb.udp->chksum_len_rx = *(int*)optval;
+      }
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UDPLITE_RECV_CSCOV) -> %d\n",
+                  s, (*(int*)optval)) );
+      break;
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_UDP */
+  }  /* switch (level) */
+  sys_sem_signal(sock->conn->op_completed);
+}
+
+int
+lwip_ioctl(int s, long cmd, void *argp)
+{
+  struct lwip_socket *sock = get_socket(s);
+  u16_t buflen = 0;
+
+  if (!sock)
+    return -1;
+
+  switch (cmd) {
+  case FIONREAD:
+    if (!argp) {
+      sock_set_errno(sock, EINVAL);
+      return -1;
+    }
+
+    SYS_ARCH_GET(sock->conn->recv_avail, *((u16_t*)argp));
+
+    /* Check if there is data left from the last recv operation. /maq 041215 */
+    if (sock->lastdata) {
+      buflen = netbuf_len(sock->lastdata);
+      buflen -= sock->lastoffset;
+
+      *((u16_t*)argp) += buflen;
+    }
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONREAD, %p) = %u\n", s, argp, *((u16_t*)argp)));
+    sock_set_errno(sock, 0);
+    return 0;
+
+  case FIONBIO:
+    if (argp && *(u32_t*)argp)
+      sock->flags |= O_NONBLOCK;
+    else
+      sock->flags &= ~O_NONBLOCK;
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONBIO, %d)\n", s, !!(sock->flags & O_NONBLOCK)));
+    sock_set_errno(sock, 0);
+    return 0;
+
+  default:
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, UNIMPL: 0x%lx, %p)\n", s, cmd, argp));
+    sock_set_errno(sock, ENOSYS); /* not yet implemented */
+    return -1;
+  } /* switch (cmd) */
+}
+
+#endif /* LWIP_SOCKET */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/tcpip.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/tcpip.c
new file mode 100644
index 0000000..b22894e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/api/tcpip.c
@@ -0,0 +1,521 @@
+/**
+ * @file
+ * Sequential API Main thread module
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if !NO_SYS /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/sys.h"
+#include "lwip/memp.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_frag.h"
+#include "lwip/tcp.h"
+#include "lwip/autoip.h"
+#include "lwip/dhcp.h"
+#include "lwip/igmp.h"
+#include "lwip/dns.h"
+#include "lwip/tcpip.h"
+#include "lwip/init.h"
+#include "netif/etharp.h"
+#include "netif/ppp_oe.h"
+
+/* global variables */
+static void (* tcpip_init_done)(void *arg);
+static void *tcpip_init_done_arg;
+static sys_mbox_t mbox = SYS_MBOX_NULL;
+
+#if LWIP_TCPIP_CORE_LOCKING
+/** The global semaphore to lock the stack. */
+sys_sem_t lock_tcpip_core;
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+
+#if LWIP_TCP
+/* global variable that shows if the tcp timer is currently scheduled or not */
+static int tcpip_tcp_timer_active;
+
+/**
+ * Timer callback function that calls tcp_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+tcpip_tcp_timer(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+
+  /* call TCP timer handler */
+  tcp_tmr();
+  /* timer still needed? */
+  if (tcp_active_pcbs || tcp_tw_pcbs) {
+    /* restart timer */
+    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
+  } else {
+    /* disable timer */
+    tcpip_tcp_timer_active = 0;
+  }
+}
+
+#if !NO_SYS
+/**
+ * Called from TCP_REG when registering a new PCB:
+ * the reason is to have the TCP timer only running when
+ * there are active (or time-wait) PCBs.
+ */
+void
+tcp_timer_needed(void)
+{
+  /* timer is off but needed again? */
+  if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) {
+    /* enable and start timer */
+    tcpip_tcp_timer_active = 1;
+    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
+  }
+}
+#endif /* !NO_SYS */
+#endif /* LWIP_TCP */
+
+#if IP_REASSEMBLY
+/**
+ * Timer callback function that calls ip_reass_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+ip_reass_timer(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: ip_reass_tmr()\n"));
+  ip_reass_tmr();
+  sys_timeout(IP_TMR_INTERVAL, ip_reass_timer, NULL);
+}
+#endif /* IP_REASSEMBLY */
+
+#if LWIP_ARP
+/**
+ * Timer callback function that calls etharp_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+arp_timer(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: etharp_tmr()\n"));
+  etharp_tmr();
+  sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL);
+}
+#endif /* LWIP_ARP */
+
+#if LWIP_DHCP
+/**
+ * Timer callback function that calls dhcp_coarse_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+dhcp_timer_coarse(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: dhcp_coarse_tmr()\n"));
+  dhcp_coarse_tmr();
+  sys_timeout(DHCP_COARSE_TIMER_MSECS, dhcp_timer_coarse, NULL);
+}
+
+/**
+ * Timer callback function that calls dhcp_fine_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+dhcp_timer_fine(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: dhcp_fine_tmr()\n"));
+  dhcp_fine_tmr();
+  sys_timeout(DHCP_FINE_TIMER_MSECS, dhcp_timer_fine, NULL);
+}
+#endif /* LWIP_DHCP */
+
+#if LWIP_AUTOIP
+/**
+ * Timer callback function that calls autoip_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+autoip_timer(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: autoip_tmr()\n"));
+  autoip_tmr();
+  sys_timeout(AUTOIP_TMR_INTERVAL, autoip_timer, NULL);
+}
+#endif /* LWIP_AUTOIP */
+
+#if LWIP_IGMP
+/**
+ * Timer callback function that calls igmp_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+igmp_timer(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: igmp_tmr()\n"));
+  igmp_tmr();
+  sys_timeout(IGMP_TMR_INTERVAL, igmp_timer, NULL);
+}
+#endif /* LWIP_IGMP */
+
+#if LWIP_DNS
+/**
+ * Timer callback function that calls dns_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+dns_timer(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: dns_tmr()\n"));
+  dns_tmr();
+  sys_timeout(DNS_TMR_INTERVAL, dns_timer, NULL);
+}
+#endif /* LWIP_DNS */
+
+/**
+ * The main lwIP thread. This thread has exclusive access to lwIP core functions
+ * (unless access to them is not locked). Other threads communicate with this
+ * thread using message boxes.
+ *
+ * It also starts all the timers to make sure they are running in the right
+ * thread context.
+ *
+ * @param arg unused argument
+ */
+static void
+tcpip_thread(void *arg)
+{
+  struct tcpip_msg *msg;
+  LWIP_UNUSED_ARG(arg);
+
+#if IP_REASSEMBLY
+  sys_timeout(IP_TMR_INTERVAL, ip_reass_timer, NULL);
+#endif /* IP_REASSEMBLY */
+#if LWIP_ARP
+  sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL);
+#endif /* LWIP_ARP */
+#if LWIP_DHCP
+  sys_timeout(DHCP_COARSE_TIMER_MSECS, dhcp_timer_coarse, NULL);
+  sys_timeout(DHCP_FINE_TIMER_MSECS, dhcp_timer_fine, NULL);
+#endif /* LWIP_DHCP */
+#if LWIP_AUTOIP
+  sys_timeout(AUTOIP_TMR_INTERVAL, autoip_timer, NULL);
+#endif /* LWIP_AUTOIP */
+#if LWIP_IGMP
+  sys_timeout(IGMP_TMR_INTERVAL, igmp_timer, NULL);
+#endif /* LWIP_IGMP */
+#if LWIP_DNS
+  sys_timeout(DNS_TMR_INTERVAL, dns_timer, NULL);
+#endif /* LWIP_DNS */
+
+  if (tcpip_init_done != NULL) {
+    tcpip_init_done(tcpip_init_done_arg);
+  }
+
+  LOCK_TCPIP_CORE();
+  while (1) {                          /* MAIN Loop */
+    sys_mbox_fetch(mbox, (void *)&msg);
+    switch (msg->type) {
+#if LWIP_NETCONN
+    case TCPIP_MSG_API:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: API message %p\n", (void *)msg));
+      msg->msg.apimsg->function(&(msg->msg.apimsg->msg));
+      break;
+#endif /* LWIP_NETCONN */
+
+    case TCPIP_MSG_INPKT:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: PACKET %p\n", (void *)msg));
+#if LWIP_ARP
+      if (msg->msg.inp.netif->flags & NETIF_FLAG_ETHARP) {
+        ethernet_input(msg->msg.inp.p, msg->msg.inp.netif);
+      } else
+#endif /* LWIP_ARP */
+      { ip_input(msg->msg.inp.p, msg->msg.inp.netif);
+      }
+      memp_free(MEMP_TCPIP_MSG_INPKT, msg);
+      break;
+
+#if LWIP_NETIF_API
+    case TCPIP_MSG_NETIFAPI:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: Netif API message %p\n", (void *)msg));
+      msg->msg.netifapimsg->function(&(msg->msg.netifapimsg->msg));
+      break;
+#endif /* LWIP_NETIF_API */
+
+    case TCPIP_MSG_CALLBACK:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg));
+      msg->msg.cb.f(msg->msg.cb.ctx);
+      memp_free(MEMP_TCPIP_MSG_API, msg);
+      break;
+
+    case TCPIP_MSG_TIMEOUT:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: TIMEOUT %p\n", (void *)msg));
+
+      if(msg->msg.tmo.msecs != 0xffffffff)
+        sys_timeout (msg->msg.tmo.msecs, msg->msg.tmo.h, msg->msg.tmo.arg);
+      else
+        sys_untimeout (msg->msg.tmo.h, msg->msg.tmo.arg);
+      memp_free(MEMP_TCPIP_MSG_API, msg);
+      break;
+
+    default:
+      break;
+    }
+  }
+}
+
+/**
+ * Pass a received packet to tcpip_thread for input processing
+ *
+ * @param p the received packet, p->payload pointing to the Ethernet header or
+ *          to an IP header (if netif doesn't got NETIF_FLAG_ETHARP flag)
+ * @param inp the network interface on which the packet was received
+ */
+err_t
+tcpip_input(struct pbuf *p, struct netif *inp)
+{
+  struct tcpip_msg *msg;
+
+  if (mbox != SYS_MBOX_NULL) {
+    msg = memp_malloc(MEMP_TCPIP_MSG_INPKT);
+    if (msg == NULL) {
+      return ERR_MEM;
+    }
+
+    msg->type = TCPIP_MSG_INPKT;
+    msg->msg.inp.p = p;
+    msg->msg.inp.netif = inp;
+    if (sys_mbox_trypost(mbox, msg) != ERR_OK) {
+      memp_free(MEMP_TCPIP_MSG_INPKT, msg);
+      return ERR_MEM;
+    }
+    return ERR_OK;
+  }
+  return ERR_VAL;
+}
+
+/**
+ * Call a specific function in the thread context of
+ * tcpip_thread for easy access synchronization.
+ * A function called in that way may access lwIP core code
+ * without fearing concurrent access.
+ *
+ * @param f the function to call
+ * @param ctx parameter passed to f
+ * @param block 1 to block until the request is posted, 0 to non-blocking mode
+ * @return ERR_OK if the function was called, another err_t if not
+ */
+err_t
+tcpip_callback_with_block(void (*f)(void *ctx), void *ctx, u8_t block)
+{
+  struct tcpip_msg *msg;
+
+  if (mbox != SYS_MBOX_NULL) {
+    msg = memp_malloc(MEMP_TCPIP_MSG_API);
+    if (msg == NULL) {
+      return ERR_MEM;
+    }
+
+    msg->type = TCPIP_MSG_CALLBACK;
+    msg->msg.cb.f = f;
+    msg->msg.cb.ctx = ctx;
+    if (block) {
+      sys_mbox_post(mbox, msg);
+    } else {
+      if (sys_mbox_trypost(mbox, msg) != ERR_OK) {
+        memp_free(MEMP_TCPIP_MSG_API, msg);
+        return ERR_MEM;
+      }
+    }
+    return ERR_OK;
+  }
+  return ERR_VAL;
+}
+
+err_t
+tcpip_timeout(u32_t msecs, sys_timeout_handler h, void *arg)
+{
+  struct tcpip_msg *msg;
+
+  if (mbox != SYS_MBOX_NULL) {
+    msg = memp_malloc(MEMP_TCPIP_MSG_API);
+    if (msg == NULL) {
+      return ERR_MEM;
+    }
+
+    msg->type = TCPIP_MSG_TIMEOUT;
+    msg->msg.tmo.msecs = msecs;
+    msg->msg.tmo.h = h;
+    msg->msg.tmo.arg = arg;
+    sys_mbox_post(mbox, msg);
+    return ERR_OK;
+  }
+  return ERR_VAL;
+}
+
+#if LWIP_NETCONN
+/**
+ * Call the lower part of a netconn_* function
+ * This function is then running in the thread context
+ * of tcpip_thread and has exclusive access to lwIP core code.
+ *
+ * @param apimsg a struct containing the function to call and its parameters
+ * @return ERR_OK if the function was called, another err_t if not
+ */
+err_t
+tcpip_apimsg(struct api_msg *apimsg)
+{
+  struct tcpip_msg msg;
+
+  if (mbox != SYS_MBOX_NULL) {
+    msg.type = TCPIP_MSG_API;
+    msg.msg.apimsg = apimsg;
+    sys_mbox_post(mbox, &msg);
+    sys_arch_sem_wait(apimsg->msg.conn->op_completed, 0);
+    return ERR_OK;
+  }
+  return ERR_VAL;
+}
+
+#if LWIP_TCPIP_CORE_LOCKING
+/**
+ * Call the lower part of a netconn_* function
+ * This function has exclusive access to lwIP core code by locking it
+ * before the function is called.
+ *
+ * @param apimsg a struct containing the function to call and its parameters
+ * @return ERR_OK (only for compatibility fo tcpip_apimsg())
+ */
+err_t
+tcpip_apimsg_lock(struct api_msg *apimsg)
+{
+  LOCK_TCPIP_CORE();
+  apimsg->function(&(apimsg->msg));
+  UNLOCK_TCPIP_CORE();
+  return ERR_OK;
+
+}
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+#endif /* LWIP_NETCONN */
+
+#if LWIP_NETIF_API
+#if !LWIP_TCPIP_CORE_LOCKING
+/**
+ * Much like tcpip_apimsg, but calls the lower part of a netifapi_*
+ * function.
+ *
+ * @param netifapimsg a struct containing the function to call and its parameters
+ * @return error code given back by the function that was called
+ */
+err_t
+tcpip_netifapi(struct netifapi_msg* netifapimsg)
+{
+  struct tcpip_msg msg;
+
+  if (mbox != SYS_MBOX_NULL) {
+    netifapimsg->msg.sem = sys_sem_new(0);
+    if (netifapimsg->msg.sem == SYS_SEM_NULL) {
+      netifapimsg->msg.err = ERR_MEM;
+      return netifapimsg->msg.err;
+    }
+
+    msg.type = TCPIP_MSG_NETIFAPI;
+    msg.msg.netifapimsg = netifapimsg;
+    sys_mbox_post(mbox, &msg);
+    sys_sem_wait(netifapimsg->msg.sem);
+    sys_sem_free(netifapimsg->msg.sem);
+    return netifapimsg->msg.err;
+  }
+  return ERR_VAL;
+}
+#else /* !LWIP_TCPIP_CORE_LOCKING */
+/**
+ * Call the lower part of a netifapi_* function
+ * This function has exclusive access to lwIP core code by locking it
+ * before the function is called.
+ *
+ * @param netifapimsg a struct containing the function to call and its parameters
+ * @return ERR_OK (only for compatibility fo tcpip_netifapi())
+ */
+err_t
+tcpip_netifapi_lock(struct netifapi_msg* netifapimsg)
+{
+  LOCK_TCPIP_CORE();
+  netifapimsg->function(&(netifapimsg->msg));
+  UNLOCK_TCPIP_CORE();
+  return netifapimsg->msg.err;
+}
+#endif /* !LWIP_TCPIP_CORE_LOCKING */
+#endif /* LWIP_NETIF_API */
+
+/**
+ * Initialize this module:
+ * - initialize all sub modules
+ * - start the tcpip_thread
+ *
+ * @param initfunc a function to call when tcpip_thread is running and finished initializing
+ * @param arg argument to pass to initfunc
+ */
+void
+tcpip_init(void (* initfunc)(void *), void *arg)
+{
+  lwip_init();
+
+  tcpip_init_done = initfunc;
+  tcpip_init_done_arg = arg;
+  mbox = sys_mbox_new(TCPIP_MBOX_SIZE);
+#if LWIP_TCPIP_CORE_LOCKING
+  lock_tcpip_core = sys_sem_new(1);
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+
+  sys_thread_new(TCPIP_THREAD_NAME, tcpip_thread, NULL, TCPIP_THREAD_STACKSIZE, TCPIP_THREAD_PRIO);
+}
+
+#endif /* !NO_SYS */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/dhcp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/dhcp.c
new file mode 100644
index 0000000..f0c41c6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/dhcp.c
@@ -0,0 +1,1548 @@
+/**
+ * @file
+ * Dynamic Host Configuration Protocol client
+ *
+ */
+
+/*
+ *
+ * Copyright (c) 2001-2004 Leon Woestenberg 
+ * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is a contribution to the lwIP TCP/IP stack.
+ * The Swedish Institute of Computer Science and Adam Dunkels
+ * are specifically granted permission to redistribute this
+ * source code.
+ *
+ * Author: Leon Woestenberg 
+ *
+ * This is a DHCP client for the lwIP TCP/IP stack. It aims to conform
+ * with RFC 2131 and RFC 2132.
+ *
+ * TODO:
+ * - Proper parsing of DHCP messages exploiting file/sname field overloading.
+ * - Add JavaDoc style documentation (API, internals).
+ * - Support for interfaces other than Ethernet (SLIP, PPP, ...)
+ *
+ * Please coordinate changes and requests with Leon Woestenberg
+ * 
+ *
+ * Integration with your code:
+ *
+ * In lwip/dhcp.h
+ * #define DHCP_COARSE_TIMER_SECS (recommended 60 which is a minute)
+ * #define DHCP_FINE_TIMER_MSECS (recommended 500 which equals TCP coarse timer)
+ *
+ * Then have your application call dhcp_coarse_tmr() and
+ * dhcp_fine_tmr() on the defined intervals.
+ *
+ * dhcp_start(struct netif *netif);
+ * starts a DHCP client instance which configures the interface by
+ * obtaining an IP address lease and maintaining it.
+ *
+ * Use dhcp_release(netif) to end the lease and use dhcp_stop(netif)
+ * to remove the DHCP client.
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_DHCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+#include "lwip/udp.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/inet.h"
+#include "lwip/sys.h"
+#include "lwip/dhcp.h"
+#include "lwip/autoip.h"
+#include "lwip/dns.h"
+#include "netif/etharp.h"
+
+#include 
+
+/** global transaction identifier, must be
+ *  unique for each DHCP request. We simply increment, starting
+ *  with this value (easy to match with a packet analyzer) */
+static u32_t xid = 0xABCD0000;
+
+/* DHCP client state machine functions */
+static void dhcp_handle_ack(struct netif *netif);
+static void dhcp_handle_nak(struct netif *netif);
+static void dhcp_handle_offer(struct netif *netif);
+
+static err_t dhcp_discover(struct netif *netif);
+static err_t dhcp_select(struct netif *netif);
+static void dhcp_check(struct netif *netif);
+static void dhcp_bind(struct netif *netif);
+#if DHCP_DOES_ARP_CHECK
+static err_t dhcp_decline(struct netif *netif);
+#endif /* DHCP_DOES_ARP_CHECK */
+static err_t dhcp_rebind(struct netif *netif);
+static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state);
+
+/* receive, unfold, parse and free incoming messages */
+static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port);
+static err_t dhcp_unfold_reply(struct dhcp *dhcp);
+static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type);
+static u8_t dhcp_get_option_byte(u8_t *ptr);
+#if 0
+static u16_t dhcp_get_option_short(u8_t *ptr);
+#endif
+static u32_t dhcp_get_option_long(u8_t *ptr);
+static void dhcp_free_reply(struct dhcp *dhcp);
+
+/* set the DHCP timers */
+static void dhcp_timeout(struct netif *netif);
+static void dhcp_t1_timeout(struct netif *netif);
+static void dhcp_t2_timeout(struct netif *netif);
+
+/* build outgoing messages */
+/* create a DHCP request, fill in common headers */
+static err_t dhcp_create_request(struct netif *netif);
+/* free a DHCP request */
+static void dhcp_delete_request(struct netif *netif);
+/* add a DHCP option (type, then length in bytes) */
+static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len);
+/* add option values */
+static void dhcp_option_byte(struct dhcp *dhcp, u8_t value);
+static void dhcp_option_short(struct dhcp *dhcp, u16_t value);
+static void dhcp_option_long(struct dhcp *dhcp, u32_t value);
+/* always add the DHCP options trailer to end and pad */
+static void dhcp_option_trailer(struct dhcp *dhcp);
+
+/**
+ * Back-off the DHCP client (because of a received NAK response).
+ *
+ * Back-off the DHCP client because of a received NAK. Receiving a
+ * NAK means the client asked for something non-sensible, for
+ * example when it tries to renew a lease obtained on another network.
+ *
+ * We clear any existing set IP address and restart DHCP negotiation
+ * afresh (as per RFC2131 3.2.3).
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_handle_nak(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 3, ("dhcp_handle_nak(netif=%p) %c%c%"U16_F"\n",
+    (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+  /* Set the interface down since the address must no longer be used, as per RFC2131 */
+  netif_set_down(netif);
+  /* remove IP address from interface */
+  netif_set_ipaddr(netif, IP_ADDR_ANY);
+  netif_set_gw(netif, IP_ADDR_ANY);
+  netif_set_netmask(netif, IP_ADDR_ANY);
+  /* Change to a defined state */
+  dhcp_set_state(dhcp, DHCP_BACKING_OFF);
+  /* We can immediately restart discovery */
+  dhcp_discover(netif);
+}
+
+/**
+ * Checks if the offered IP address is already in use.
+ *
+ * It does so by sending an ARP request for the offered address and
+ * entering CHECKING state. If no ARP reply is received within a small
+ * interval, the address is assumed to be free for use by us.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_check(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 3, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (s16_t)netif->name[0],
+    (s16_t)netif->name[1]));
+  /* create an ARP query for the offered IP address, expecting that no host
+     responds, as the IP address should not be in use. */
+  result = etharp_query(netif, &dhcp->offered_ip_addr, NULL);
+  if (result != ERR_OK) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 2, ("dhcp_check: could not perform ARP query\n"));
+  }
+  dhcp->tries++;
+  msecs = 500;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_check(): set request timeout %"U16_F" msecs\n", msecs));
+  dhcp_set_state(dhcp, DHCP_CHECKING);
+}
+
+/**
+ * Remember the configuration offered by a DHCP server.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_handle_offer(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  /* obtain the server address */
+  u8_t *option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SERVER_ID);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 3, ("dhcp_handle_offer(netif=%p) %c%c%"U16_F"\n",
+    (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+  if (option_ptr != NULL) {
+    dhcp->server_ip_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): server 0x%08"X32_F"\n", dhcp->server_ip_addr.addr));
+    /* remember offered address */
+    ip_addr_set(&dhcp->offered_ip_addr, (struct ip_addr *)&dhcp->msg_in->yiaddr);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08"X32_F"\n", dhcp->offered_ip_addr.addr));
+
+    dhcp_select(netif);
+  }
+}
+
+/**
+ * Select a DHCP server offer out of all offers.
+ *
+ * Simply select the first offer received.
+ *
+ * @param netif the netif under DHCP control
+ * @return lwIP specific error (see error.h)
+ */
+static err_t
+dhcp_select(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+#if LWIP_NETIF_HOSTNAME
+  const char *p;
+#endif /* LWIP_NETIF_HOSTNAME */
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 3, ("dhcp_select(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_REQUEST);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, 576);
+
+    /* MUST request the offered IP address */
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+
+    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
+
+    dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/);
+    dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK);
+    dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER);
+    dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST);
+    dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER);
+
+#if LWIP_NETIF_HOSTNAME
+    p = (const char*)netif->hostname;
+    if (p!=NULL) {
+      dhcp_option(dhcp, DHCP_OPTION_HOSTNAME, strlen(p));
+      while (*p) {
+        dhcp_option_byte(dhcp, *p++);
+      }
+    }
+#endif /* LWIP_NETIF_HOSTNAME */
+
+    dhcp_option_trailer(dhcp);
+    /* shrink the pbuf to the actual content length */
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    /* TODO: we really should bind to a specific local interface here
+       but we cannot specify an unconfigured netif as it is addressless */
+    /* send broadcast to any DHCP server */
+    udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif);
+    /* reconnect to any (or to server here?!) */
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_select: REQUESTING\n"));
+    dhcp_set_state(dhcp, DHCP_REQUESTING);
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 2, ("dhcp_select: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 4 ? dhcp->tries * 1000 : 4 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_select(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+/**
+ * The DHCP timer that checks for lease renewal/rebind timeouts.
+ *
+ */
+void
+dhcp_coarse_tmr()
+{
+  struct netif *netif = netif_list;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_coarse_tmr()\n"));
+  /* iterate through all network interfaces */
+  while (netif != NULL) {
+    /* only act on DHCP configured interfaces */
+    if (netif->dhcp != NULL) {
+      /* timer is active (non zero), and triggers (zeroes) now? */
+      if (netif->dhcp->t2_timeout-- == 1) {
+        LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n"));
+        /* this clients' rebind timeout triggered */
+        dhcp_t2_timeout(netif);
+      /* timer is active (non zero), and triggers (zeroes) now */
+      } else if (netif->dhcp->t1_timeout-- == 1) {
+        LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n"));
+        /* this clients' renewal timeout triggered */
+        dhcp_t1_timeout(netif);
+      }
+    }
+    /* proceed to next netif */
+    netif = netif->next;
+  }
+}
+
+/**
+ * DHCP transaction timeout handling
+ *
+ * A DHCP server is expected to respond within a short period of time.
+ * This timer checks whether an outstanding DHCP request is timed out.
+ *
+ */
+void
+dhcp_fine_tmr()
+{
+  struct netif *netif = netif_list;
+  /* loop through netif's */
+  while (netif != NULL) {
+    /* only act on DHCP configured interfaces */
+    if (netif->dhcp != NULL) {
+      /* timer is active (non zero), and is about to trigger now */
+      if (netif->dhcp->request_timeout > 1) {
+        netif->dhcp->request_timeout--;
+      }
+      else if (netif->dhcp->request_timeout == 1) {
+        netif->dhcp->request_timeout--;
+        /* { netif->dhcp->request_timeout == 0 } */
+        LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_fine_tmr(): request timeout\n"));
+        /* this clients' request timeout triggered */
+        dhcp_timeout(netif);
+      }
+    }
+    /* proceed to next network interface */
+    netif = netif->next;
+  }
+}
+
+/**
+ * A DHCP negotiation transaction, or ARP request, has timed out.
+ *
+ * The timer that was started with the DHCP or ARP request has
+ * timed out, indicating no response was received in time.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 3, ("dhcp_timeout()\n"));
+  /* back-off period has passed, or server selection timed out */
+  if ((dhcp->state == DHCP_BACKING_OFF) || (dhcp->state == DHCP_SELECTING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout(): restarting discovery\n"));
+    dhcp_discover(netif);
+  /* receiving the requested lease timed out */
+  } else if (dhcp->state == DHCP_REQUESTING) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): REQUESTING, DHCP request timed out\n"));
+    if (dhcp->tries <= 5) {
+      dhcp_select(netif);
+    } else {
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): REQUESTING, releasing, restarting\n"));
+      dhcp_release(netif);
+      dhcp_discover(netif);
+    }
+  /* received no ARP reply for the offered address (which is good) */
+  } else if (dhcp->state == DHCP_CHECKING) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): CHECKING, ARP request timed out\n"));
+    if (dhcp->tries <= 1) {
+      dhcp_check(netif);
+    /* no ARP replies on the offered address,
+       looks like the IP address is indeed free */
+    } else {
+      /* bind the interface to the offered address */
+      dhcp_bind(netif);
+    }
+  }
+  /* did not get response to renew request? */
+  else if (dhcp->state == DHCP_RENEWING) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): RENEWING, DHCP request timed out\n"));
+    /* just retry renewal */
+    /* note that the rebind timer will eventually time-out if renew does not work */
+    dhcp_renew(netif);
+  /* did not get response to rebind request? */
+  } else if (dhcp->state == DHCP_REBINDING) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): REBINDING, DHCP request timed out\n"));
+    if (dhcp->tries <= 8) {
+      dhcp_rebind(netif);
+    } else {
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): RELEASING, DISCOVERING\n"));
+      dhcp_release(netif);
+      dhcp_discover(netif);
+    }
+  }
+}
+
+/**
+ * The renewal period has timed out.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_t1_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_t1_timeout()\n"));
+  if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) {
+    /* just retry to renew - note that the rebind timer (t2) will
+     * eventually time-out if renew tries fail. */
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_t1_timeout(): must renew\n"));
+    dhcp_renew(netif);
+  }
+}
+
+/**
+ * The rebind period has timed out.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_t2_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_t2_timeout()\n"));
+  if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) {
+    /* just retry to rebind */
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_t2_timeout(): must rebind\n"));
+    dhcp_rebind(netif);
+  }
+}
+
+/**
+ * Handle a DHCP ACK packet
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_handle_ack(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  u8_t *option_ptr;
+  /* clear options we might not get from the ACK */
+  dhcp->offered_sn_mask.addr = 0;
+  dhcp->offered_gw_addr.addr = 0;
+  dhcp->offered_bc_addr.addr = 0;
+
+  /* lease time given? */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_LEASE_TIME);
+  if (option_ptr != NULL) {
+    /* remember offered lease time */
+    dhcp->offered_t0_lease = dhcp_get_option_long(option_ptr + 2);
+  }
+  /* renewal period given? */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T1);
+  if (option_ptr != NULL) {
+    /* remember given renewal period */
+    dhcp->offered_t1_renew = dhcp_get_option_long(option_ptr + 2);
+  } else {
+    /* calculate safe periods for renewal */
+    dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2;
+  }
+
+  /* renewal period given? */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T2);
+  if (option_ptr != NULL) {
+    /* remember given rebind period */
+    dhcp->offered_t2_rebind = dhcp_get_option_long(option_ptr + 2);
+  } else {
+    /* calculate safe periods for rebinding */
+    dhcp->offered_t2_rebind = dhcp->offered_t0_lease;
+  }
+
+  /* (y)our internet address */
+  ip_addr_set(&dhcp->offered_ip_addr, &dhcp->msg_in->yiaddr);
+
+/**
+ * Patch #1308
+ * TODO: we must check if the file field is not overloaded by DHCP options!
+ */
+#if 0
+  /* boot server address */
+  ip_addr_set(&dhcp->offered_si_addr, &dhcp->msg_in->siaddr);
+  /* boot file name */
+  if (dhcp->msg_in->file[0]) {
+    dhcp->boot_file_name = mem_malloc(strlen(dhcp->msg_in->file) + 1);
+    strcpy(dhcp->boot_file_name, dhcp->msg_in->file);
+  }
+#endif
+
+  /* subnet mask */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SUBNET_MASK);
+  /* subnet mask given? */
+  if (option_ptr != NULL) {
+    dhcp->offered_sn_mask.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+  }
+
+  /* gateway router */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_ROUTER);
+  if (option_ptr != NULL) {
+    dhcp->offered_gw_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+  }
+
+  /* broadcast address */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_BROADCAST);
+  if (option_ptr != NULL) {
+    dhcp->offered_bc_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+  }
+
+  /* DNS servers */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_DNS_SERVER);
+  if (option_ptr != NULL) {
+    u8_t n;
+    dhcp->dns_count = dhcp_get_option_byte(&option_ptr[1]) / (u32_t)sizeof(struct ip_addr);
+    /* limit to at most DHCP_MAX_DNS DNS servers */
+    if (dhcp->dns_count > DHCP_MAX_DNS)
+      dhcp->dns_count = DHCP_MAX_DNS;
+    for (n = 0; n < dhcp->dns_count; n++) {
+      dhcp->offered_dns_addr[n].addr = htonl(dhcp_get_option_long(&option_ptr[2 + n * 4]));
+#if LWIP_DNS
+      dns_setserver( n, (struct ip_addr *)(&(dhcp->offered_dns_addr[n].addr)));
+#endif /* LWIP_DNS */
+    }
+#if LWIP_DNS
+    dns_setserver( n, (struct ip_addr *)(&ip_addr_any));
+#endif /* LWIP_DNS */
+  }
+}
+
+/**
+ * Start DHCP negotiation for a network interface.
+ *
+ * If no DHCP client instance was attached to this interface,
+ * a new client is created first. If a DHCP client instance
+ * was already present, it restarts negotiation.
+ *
+ * @param netif The lwIP network interface
+ * @return lwIP error code
+ * - ERR_OK - No error
+ * - ERR_MEM - Out of memory
+ */
+err_t
+dhcp_start(struct netif *netif)
+{
+  struct dhcp *dhcp;
+  err_t result = ERR_OK;
+
+  LWIP_ERROR("netif != NULL", (netif != NULL), return ERR_ARG;);
+  dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+  netif->flags &= ~NETIF_FLAG_DHCP;
+
+  /* no DHCP client attached yet? */
+  if (dhcp == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): starting new DHCP client\n"));
+    dhcp = mem_malloc(sizeof(struct dhcp));
+    if (dhcp == NULL) {
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n"));
+      return ERR_MEM;
+    }
+    /* store this dhcp client in the netif */
+    netif->dhcp = dhcp;
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): allocated dhcp"));
+  /* already has DHCP client attached */
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | 3, ("dhcp_start(): restarting DHCP configuration\n"));
+  }
+
+  /* clear data structure */
+  memset(dhcp, 0, sizeof(struct dhcp));
+  /* allocate UDP PCB */
+  dhcp->pcb = udp_new();
+  if (dhcp->pcb == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG  | LWIP_DBG_TRACE, ("dhcp_start(): could not obtain pcb\n"));
+    mem_free((void *)dhcp);
+    netif->dhcp = dhcp = NULL;
+    return ERR_MEM;
+  }
+  /* set up local and remote port for the pcb */
+  udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+  udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+  /* set up the recv callback and argument */
+  udp_recv(dhcp->pcb, dhcp_recv, netif);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n"));
+  /* (re)start the DHCP negotiation */
+  result = dhcp_discover(netif);
+  if (result != ERR_OK) {
+    /* free resources allocated above */
+    dhcp_stop(netif);
+    return ERR_MEM;
+  }
+  netif->flags |= NETIF_FLAG_DHCP;
+  return result;
+}
+
+/**
+ * Inform a DHCP server of our manual configuration.
+ *
+ * This informs DHCP servers of our fixed IP address configuration
+ * by sending an INFORM message. It does not involve DHCP address
+ * configuration, it is just here to be nice to the network.
+ *
+ * @param netif The lwIP network interface
+ */
+void
+dhcp_inform(struct netif *netif)
+{
+  struct dhcp *dhcp, *old_dhcp = netif->dhcp;
+  err_t result = ERR_OK;
+  dhcp = mem_malloc(sizeof(struct dhcp));
+  if (dhcp == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 2, ("dhcp_inform(): could not allocate dhcp\n"));
+    return;
+  }
+  netif->dhcp = dhcp;
+  memset(dhcp, 0, sizeof(struct dhcp));
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_inform(): allocated dhcp\n"));
+  dhcp->pcb = udp_new();
+  if (dhcp->pcb == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 2, ("dhcp_inform(): could not obtain pcb"));
+    mem_free((void *)dhcp);
+    return;
+  }
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_inform(): created new udp pcb\n"));
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_INFORM);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    /* TODO: use netif->mtu ?! */
+    dhcp_option_short(dhcp, 576);
+
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    udp_connect(dhcp->pcb, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_inform: INFORMING\n"));
+    udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif);
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    dhcp_delete_request(netif);
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 2, ("dhcp_inform: could not allocate DHCP request\n"));
+  }
+
+  if (dhcp != NULL) {
+    if (dhcp->pcb != NULL) {
+      udp_remove(dhcp->pcb);
+    }
+    dhcp->pcb = NULL;
+    mem_free((void *)dhcp);
+    netif->dhcp = old_dhcp;
+  }
+}
+
+#if DHCP_DOES_ARP_CHECK
+/**
+ * Match an ARP reply with the offered IP address.
+ *
+ * @param netif the network interface on which the reply was received
+ * @param addr The IP address we received a reply from
+ */
+void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr)
+{
+  LWIP_ERROR("netif != NULL", (netif != NULL), return;);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 3, ("dhcp_arp_reply()\n"));
+  /* is a DHCP client doing an ARP check? */
+  if ((netif->dhcp != NULL) && (netif->dhcp->state == DHCP_CHECKING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08"X32_F"\n", addr->addr));
+    /* did a host respond with the address we
+       were offered by the DHCP server? */
+    if (ip_addr_cmp(addr, &netif->dhcp->offered_ip_addr)) {
+      /* we will not accept the offered address */
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | 1, ("dhcp_arp_reply(): arp reply matched with offered address, declining\n"));
+      dhcp_decline(netif);
+    }
+  }
+}
+
+/**
+ * Decline an offered lease.
+ *
+ * Tell the DHCP server we do not accept the offered address.
+ * One reason to decline the lease is when we find out the address
+ * is already in use by another host (through ARP).
+ *
+ * @param netif the netif under DHCP control
+ */
+static err_t
+dhcp_decline(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result = ERR_OK;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 3, ("dhcp_decline()\n"));
+  dhcp_set_state(dhcp, DHCP_BACKING_OFF);
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_DECLINE);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, 576);
+
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+
+    dhcp_option_trailer(dhcp);
+    /* resize pbuf to reflect true size of options */
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    /* @todo: should we really connect here? we are performing sendto() */
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    /* per section 4.4.4, broadcast DECLINE messages */
+    udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_decline: BACKING OFF\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 2, ("dhcp_decline: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = 10*1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+#endif
+
+
+/**
+ * Start the DHCP process, discover a DHCP server.
+ *
+ * @param netif the netif under DHCP control
+ */
+static err_t
+dhcp_discover(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result = ERR_OK;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 3, ("dhcp_discover()\n"));
+  ip_addr_set(&dhcp->offered_ip_addr, IP_ADDR_ANY);
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: making request\n"));
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_DISCOVER);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, 576);
+
+    dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/);
+    dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK);
+    dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER);
+    dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST);
+    dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER);
+
+    dhcp_option_trailer(dhcp);
+
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: realloc()ing\n"));
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, DHCP_SERVER_PORT)\n"));
+    udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: deleting()ing\n"));
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover: SELECTING\n"));
+    dhcp_set_state(dhcp, DHCP_SELECTING);
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 2, ("dhcp_discover: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+#if LWIP_DHCP_AUTOIP_COOP
+  /* that means we waited 57 seconds */
+  if(dhcp->tries >= 9 && dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_OFF) {
+    dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_ON;
+    autoip_start(netif);
+  }
+#endif /* LWIP_DHCP_AUTOIP_COOP */
+  msecs = dhcp->tries < 4 ? (dhcp->tries + 1) * 1000 : 10 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+
+/**
+ * Bind the interface to the offered IP address.
+ *
+ * @param netif network interface to bind to the offered address
+ */
+static void
+dhcp_bind(struct netif *netif)
+{
+  u32_t timeout;
+  struct dhcp *dhcp;
+  struct ip_addr sn_mask, gw_addr;
+  LWIP_ERROR("dhcp_bind: netif != NULL", (netif != NULL), return;);
+  dhcp = netif->dhcp;
+  LWIP_ERROR("dhcp_bind: dhcp != NULL", (dhcp != NULL), return;);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 3, ("dhcp_bind(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+
+  /* temporary DHCP lease? */
+  if (dhcp->offered_t1_renew != 0xffffffffUL) {
+    /* set renewal period timer */
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t1 renewal timer %"U32_F" secs\n", dhcp->offered_t1_renew));
+    timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
+    if(timeout > 0xffff) {
+      timeout = 0xffff;
+    }
+    dhcp->t1_timeout = (u16_t)timeout;
+    if (dhcp->t1_timeout == 0) {
+      dhcp->t1_timeout = 1;
+    }
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t1_renew*1000));
+  }
+  /* set renewal period timer */
+  if (dhcp->offered_t2_rebind != 0xffffffffUL) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t2 rebind timer %"U32_F" secs\n", dhcp->offered_t2_rebind));
+    timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
+    if(timeout > 0xffff) {
+      timeout = 0xffff;
+    }
+    dhcp->t2_timeout = (u16_t)timeout;
+    if (dhcp->t2_timeout == 0) {
+      dhcp->t2_timeout = 1;
+    }
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t2_rebind*1000));
+  }
+  /* copy offered network mask */
+  ip_addr_set(&sn_mask, &dhcp->offered_sn_mask);
+
+  /* subnet mask not given? */
+  /* TODO: this is not a valid check. what if the network mask is 0? */
+  if (sn_mask.addr == 0) {
+    /* choose a safe subnet mask given the network class */
+    u8_t first_octet = ip4_addr1(&sn_mask);
+    if (first_octet <= 127) {
+      sn_mask.addr = htonl(0xff000000);
+    } else if (first_octet >= 192) {
+      sn_mask.addr = htonl(0xffffff00);
+    } else {
+      sn_mask.addr = htonl(0xffff0000);
+    }
+  }
+
+  ip_addr_set(&gw_addr, &dhcp->offered_gw_addr);
+  /* gateway address not given? */
+  if (gw_addr.addr == 0) {
+    /* copy network address */
+    gw_addr.addr = (dhcp->offered_ip_addr.addr & sn_mask.addr);
+    /* use first host address on network as gateway */
+    gw_addr.addr |= htonl(0x00000001);
+  }
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): IP: 0x%08"X32_F"\n", dhcp->offered_ip_addr.addr));
+  netif_set_ipaddr(netif, &dhcp->offered_ip_addr);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): SN: 0x%08"X32_F"\n", sn_mask.addr));
+  netif_set_netmask(netif, &sn_mask);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): GW: 0x%08"X32_F"\n", gw_addr.addr));
+  netif_set_gw(netif, &gw_addr);
+  /* bring the interface up */
+  netif_set_up(netif);
+  /* netif is now bound to DHCP leased address */
+  dhcp_set_state(dhcp, DHCP_BOUND);
+}
+
+/**
+ * Renew an existing DHCP lease at the involved DHCP server.
+ *
+ * @param netif network interface which must renew its lease
+ */
+err_t
+dhcp_renew(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 3, ("dhcp_renew()\n"));
+  dhcp_set_state(dhcp, DHCP_RENEWING);
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_REQUEST);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    /* TODO: use netif->mtu in some way */
+    dhcp_option_short(dhcp, 576);
+
+#if 0
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+#endif
+
+#if 0
+    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
+#endif
+    /* append DHCP message trailer */
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT);
+    udp_sendto_if(dhcp->pcb, dhcp->p_out, &dhcp->server_ip_addr, DHCP_SERVER_PORT, netif);
+    dhcp_delete_request(netif);
+
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew: RENEWING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 2, ("dhcp_renew: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  /* back-off on retries, but to a maximum of 20 seconds */
+  msecs = dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+/**
+ * Rebind with a DHCP server for an existing DHCP lease.
+ *
+ * @param netif network interface which must rebind with a DHCP server
+ */
+static err_t
+dhcp_rebind(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind()\n"));
+  dhcp_set_state(dhcp, DHCP_REBINDING);
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_REQUEST);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, 576);
+
+#if 0
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+
+    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
+#endif
+
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    /* broadcast to server */
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind: REBINDING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 2, ("dhcp_rebind: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+/**
+ * Release a DHCP lease.
+ *
+ * @param netif network interface which must release its lease
+ */
+err_t
+dhcp_release(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 3, ("dhcp_release()\n"));
+
+  /* idle DHCP client */
+  dhcp_set_state(dhcp, DHCP_OFF);
+  /* clean old DHCP offer */
+  dhcp->server_ip_addr.addr = 0;
+  dhcp->offered_ip_addr.addr = dhcp->offered_sn_mask.addr = 0;
+  dhcp->offered_gw_addr.addr = dhcp->offered_bc_addr.addr = 0;
+  dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0;
+  dhcp->dns_count = 0;
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_RELEASE);
+
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT);
+    udp_sendto_if(dhcp->pcb, dhcp->p_out, &dhcp->server_ip_addr, DHCP_SERVER_PORT, netif);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_release: RELEASED, DHCP_OFF\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 2, ("dhcp_release: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_release(): set request timeout %"U16_F" msecs\n", msecs));
+  /* bring the interface down */
+  netif_set_down(netif);
+  /* remove IP address from interface */
+  netif_set_ipaddr(netif, IP_ADDR_ANY);
+  netif_set_gw(netif, IP_ADDR_ANY);
+  netif_set_netmask(netif, IP_ADDR_ANY);
+
+  /* TODO: netif_down(netif); */
+  return result;
+}
+
+/**
+ * Remove the DHCP client from the interface.
+ *
+ * @param netif The network interface to stop DHCP on
+ */
+void
+dhcp_stop(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_ERROR("dhcp_stop: netif != NULL", (netif != NULL), return;);
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 3, ("dhcp_stop()\n"));
+  /* netif is DHCP configured? */
+  if (dhcp != NULL) {
+    if (dhcp->pcb != NULL) {
+      udp_remove(dhcp->pcb);
+      dhcp->pcb = NULL;
+    }
+    if (dhcp->p != NULL) {
+      pbuf_free(dhcp->p);
+      dhcp->p = NULL;
+    }
+    /* free unfolded reply */
+    dhcp_free_reply(dhcp);
+    mem_free((void *)dhcp);
+    netif->dhcp = NULL;
+  }
+}
+
+/*
+ * Set the DHCP state of a DHCP client.
+ *
+ * If the state changed, reset the number of tries.
+ *
+ * TODO: we might also want to reset the timeout here?
+ */
+static void
+dhcp_set_state(struct dhcp *dhcp, u8_t new_state)
+{
+  if (new_state != dhcp->state) {
+    dhcp->state = new_state;
+    dhcp->tries = 0;
+  }
+}
+
+/*
+ * Concatenate an option type and length field to the outgoing
+ * DHCP message.
+ *
+ */
+static void
+dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len)
+{
+  LWIP_ASSERT("dhcp_option: dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2U + option_len <= DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = option_type;
+  dhcp->msg_out->options[dhcp->options_out_len++] = option_len;
+}
+/*
+ * Concatenate a single byte to the outgoing DHCP message.
+ *
+ */
+static void
+dhcp_option_byte(struct dhcp *dhcp, u8_t value)
+{
+  LWIP_ASSERT("dhcp_option_byte: dhcp->options_out_len < DHCP_OPTIONS_LEN", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = value;
+}
+
+static void
+dhcp_option_short(struct dhcp *dhcp, u16_t value)
+{
+  LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2U <= DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0xff00U) >> 8);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t) (value & 0x00ffU);
+}
+
+static void
+dhcp_option_long(struct dhcp *dhcp, u32_t value)
+{
+  LWIP_ASSERT("dhcp_option_long: dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 4U <= DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0xff000000UL) >> 24);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0x00ff0000UL) >> 16);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0x0000ff00UL) >> 8);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0x000000ffUL));
+}
+
+/**
+ * Extract the DHCP message and the DHCP options.
+ *
+ * Extract the DHCP message and the DHCP options, each into a contiguous
+ * piece of memory. As a DHCP message is variable sized by its options,
+ * and also allows overriding some fields for options, the easy approach
+ * is to first unfold the options into a conitguous piece of memory, and
+ * use that further on.
+ *
+ */
+static err_t
+dhcp_unfold_reply(struct dhcp *dhcp)
+{
+  u16_t ret;
+  LWIP_ERROR("dhcp != NULL", (dhcp != NULL), return ERR_ARG;);
+  LWIP_ERROR("dhcp->p != NULL", (dhcp->p != NULL), return ERR_VAL;);
+  /* free any left-overs from previous unfolds */
+  dhcp_free_reply(dhcp);
+  /* options present? */
+  if (dhcp->p->tot_len > (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN)) {
+    dhcp->options_in_len = dhcp->p->tot_len - (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN);
+    dhcp->options_in = mem_malloc(dhcp->options_in_len);
+    if (dhcp->options_in == NULL) {
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->options\n"));
+      return ERR_MEM;
+    }
+  }
+  dhcp->msg_in = mem_malloc(sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN);
+  if (dhcp->msg_in == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->msg_in\n"));
+    mem_free((void *)dhcp->options_in);
+    dhcp->options_in = NULL;
+    return ERR_MEM;
+  }
+
+  /** copy the DHCP message without options */
+  ret = pbuf_copy_partial(dhcp->p, dhcp->msg_in, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN, 0);
+  LWIP_ASSERT("ret == sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN", ret == sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_unfold_reply(): copied %"U16_F" bytes into dhcp->msg_in[]\n",
+     sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN));
+
+  if (dhcp->options_in != NULL) {
+    /** copy the DHCP options */
+    ret = pbuf_copy_partial(dhcp->p, dhcp->options_in, dhcp->options_in_len, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN);
+    LWIP_ASSERT("ret == dhcp->options_in_len", ret == dhcp->options_in_len);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_unfold_reply(): copied %"U16_F" bytes to dhcp->options_in[]\n",
+      dhcp->options_in_len));
+  }
+  LWIP_UNUSED_ARG(ret);
+  return ERR_OK;
+}
+
+/**
+ * Free the incoming DHCP message including contiguous copy of
+ * its DHCP options.
+ *
+ */
+static void dhcp_free_reply(struct dhcp *dhcp)
+{
+  if (dhcp->msg_in != NULL) {
+    mem_free((void *)dhcp->msg_in);
+    dhcp->msg_in = NULL;
+  }
+  if (dhcp->options_in) {
+    mem_free((void *)dhcp->options_in);
+    dhcp->options_in = NULL;
+    dhcp->options_in_len = 0;
+  }
+  LWIP_DEBUGF(DHCP_DEBUG, ("dhcp_free_reply(): free'd\n"));
+}
+
+
+/**
+ * If an incoming DHCP message is in response to us, then trigger the state machine
+ */
+static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port)
+{
+  struct netif *netif = (struct netif *)arg;
+  struct dhcp *dhcp = netif->dhcp;
+  struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload;
+  u8_t *options_ptr;
+  u8_t msg_type;
+  u8_t i;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 3, ("dhcp_recv(pbuf = %p) from DHCP server %"U16_F".%"U16_F".%"U16_F".%"U16_F" port %"U16_F"\n", (void*)p,
+    (u16_t)(ntohl(addr->addr) >> 24 & 0xff), (u16_t)(ntohl(addr->addr) >> 16 & 0xff),
+    (u16_t)(ntohl(addr->addr) >>  8 & 0xff), (u16_t)(ntohl(addr->addr) & 0xff), port));
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("pbuf->len = %"U16_F"\n", p->len));
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("pbuf->tot_len = %"U16_F"\n", p->tot_len));
+  /* prevent warnings about unused arguments */
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_UNUSED_ARG(addr);
+  LWIP_UNUSED_ARG(port);
+  dhcp->p = p;
+  /* TODO: check packet length before reading them */
+  if (reply_msg->op != DHCP_BOOTREPLY) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 1, ("not a DHCP reply message, but type %"U16_F"\n", (u16_t)reply_msg->op));
+    goto free_pbuf_and_return;
+  }
+  /* iterate through hardware address and match against DHCP message */
+  for (i = 0; i < netif->hwaddr_len; i++) {
+    if (netif->hwaddr[i] != reply_msg->chaddr[i]) {
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 2, ("netif->hwaddr[%"U16_F"]==%02"X16_F" != reply_msg->chaddr[%"U16_F"]==%02"X16_F"\n",
+        (u16_t)i, (u16_t)netif->hwaddr[i], (u16_t)i, (u16_t)reply_msg->chaddr[i]));
+      goto free_pbuf_and_return;
+    }
+  }
+  /* match transaction ID against what we expected */
+  if (ntohl(reply_msg->xid) != dhcp->xid) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 2, ("transaction id mismatch reply_msg->xid(%"X32_F")!=dhcp->xid(%"X32_F")\n",ntohl(reply_msg->xid),dhcp->xid));
+    goto free_pbuf_and_return;
+  }
+  /* option fields could be unfold? */
+  if (dhcp_unfold_reply(dhcp) != ERR_OK) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 2, ("problem unfolding DHCP message - too short on memory?\n"));
+    goto free_pbuf_and_return;
+  }
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n"));
+  /* obtain pointer to DHCP message type */
+  options_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_MESSAGE_TYPE);
+  if (options_ptr == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 1, ("DHCP_OPTION_MESSAGE_TYPE option not found\n"));
+    goto free_pbuf_and_return;
+  }
+
+  /* read DHCP message type */
+  msg_type = dhcp_get_option_byte(options_ptr + 2);
+  /* message type is DHCP ACK? */
+  if (msg_type == DHCP_ACK) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 1, ("DHCP_ACK received\n"));
+    /* in requesting state? */
+    if (dhcp->state == DHCP_REQUESTING) {
+      dhcp_handle_ack(netif);
+      dhcp->request_timeout = 0;
+#if DHCP_DOES_ARP_CHECK
+      /* check if the acknowledged lease address is already in use */
+      dhcp_check(netif);
+#else
+      /* bind interface to the acknowledged lease address */
+      dhcp_bind(netif);
+#endif
+    }
+    /* already bound to the given lease address? */
+    else if ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING)) {
+      dhcp->request_timeout = 0;
+      dhcp_bind(netif);
+    }
+  }
+  /* received a DHCP_NAK in appropriate state? */
+  else if ((msg_type == DHCP_NAK) &&
+    ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REQUESTING) ||
+     (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING  ))) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 1, ("DHCP_NAK received\n"));
+    dhcp->request_timeout = 0;
+    dhcp_handle_nak(netif);
+  }
+  /* received a DHCP_OFFER in DHCP_SELECTING state? */
+  else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_SELECTING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 1, ("DHCP_OFFER received in DHCP_SELECTING state\n"));
+    dhcp->request_timeout = 0;
+    /* remember offered lease */
+    dhcp_handle_offer(netif);
+  }
+free_pbuf_and_return:
+  pbuf_free(p);
+  dhcp->p = NULL;
+}
+
+/**
+ * Create a DHCP request, fill in common headers
+ *
+ * @param netif the netif under DHCP control
+ */
+static err_t
+dhcp_create_request(struct netif *netif)
+{
+  struct dhcp *dhcp;
+  u16_t i;
+  LWIP_ERROR("dhcp_create_request: netif != NULL", (netif != NULL), return ERR_ARG;);
+  dhcp = netif->dhcp;
+  LWIP_ERROR("dhcp_create_request: dhcp != NULL", (dhcp != NULL), return ERR_VAL;);
+  LWIP_ASSERT("dhcp_create_request: dhcp->p_out == NULL", dhcp->p_out == NULL);
+  LWIP_ASSERT("dhcp_create_request: dhcp->msg_out == NULL", dhcp->msg_out == NULL);
+  dhcp->p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM);
+  if (dhcp->p_out == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 2, ("dhcp_create_request(): could not allocate pbuf\n"));
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("dhcp_create_request: check that first pbuf can hold struct dhcp_msg",
+           (dhcp->p_out->len >= sizeof(struct dhcp_msg)));
+
+  /* give unique transaction identifier to this request */
+  dhcp->xid = xid++;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 2, ("transaction id xid++(%"X32_F") dhcp->xid(%"U32_F")\n",xid,dhcp->xid));
+
+  dhcp->msg_out = (struct dhcp_msg *)dhcp->p_out->payload;
+
+  dhcp->msg_out->op = DHCP_BOOTREQUEST;
+  /* TODO: make link layer independent */
+  dhcp->msg_out->htype = DHCP_HTYPE_ETH;
+  /* TODO: make link layer independent */
+  dhcp->msg_out->hlen = DHCP_HLEN_ETH;
+  dhcp->msg_out->hops = 0;
+  dhcp->msg_out->xid = htonl(dhcp->xid);
+  dhcp->msg_out->secs = 0;
+  dhcp->msg_out->flags = 0;
+  dhcp->msg_out->ciaddr.addr = netif->ip_addr.addr;
+  dhcp->msg_out->yiaddr.addr = 0;
+  dhcp->msg_out->siaddr.addr = 0;
+  dhcp->msg_out->giaddr.addr = 0;
+  for (i = 0; i < DHCP_CHADDR_LEN; i++) {
+    /* copy netif hardware address, pad with zeroes */
+    dhcp->msg_out->chaddr[i] = (i < netif->hwaddr_len) ? netif->hwaddr[i] : 0/* pad byte*/;
+  }
+  for (i = 0; i < DHCP_SNAME_LEN; i++) {
+    dhcp->msg_out->sname[i] = 0;
+  }
+  for (i = 0; i < DHCP_FILE_LEN; i++) {
+    dhcp->msg_out->file[i] = 0;
+  }
+  dhcp->msg_out->cookie = htonl(0x63825363UL);
+  dhcp->options_out_len = 0;
+  /* fill options field with an incrementing array (for debugging purposes) */
+  for (i = 0; i < DHCP_OPTIONS_LEN; i++) {
+    dhcp->msg_out->options[i] = (u8_t)i; /* for debugging only, no matter if truncated */
+  }
+  return ERR_OK;
+}
+
+/**
+ * Free previously allocated memory used to send a DHCP request.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_delete_request(struct netif *netif)
+{
+  struct dhcp *dhcp;
+  LWIP_ERROR("dhcp_delete_request: netif != NULL", (netif != NULL), return;);
+  dhcp = netif->dhcp;
+  LWIP_ERROR("dhcp_delete_request: dhcp != NULL", (dhcp != NULL), return;);
+  LWIP_ASSERT("dhcp_delete_request: dhcp->p_out != NULL", dhcp->p_out != NULL);
+  LWIP_ASSERT("dhcp_delete_request: dhcp->msg_out != NULL", dhcp->msg_out != NULL);
+  if (dhcp->p_out != NULL) {
+    pbuf_free(dhcp->p_out);
+  }
+  dhcp->p_out = NULL;
+  dhcp->msg_out = NULL;
+}
+
+/**
+ * Add a DHCP message trailer
+ *
+ * Adds the END option to the DHCP message, and if
+ * necessary, up to three padding bytes.
+ *
+ * @param dhcp DHCP state structure
+ */
+static void
+dhcp_option_trailer(struct dhcp *dhcp)
+{
+  LWIP_ERROR("dhcp_option_trailer: dhcp != NULL", (dhcp != NULL), return;);
+  LWIP_ASSERT("dhcp_option_trailer: dhcp->msg_out != NULL\n", dhcp->msg_out != NULL);
+  LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = DHCP_OPTION_END;
+  /* packet is too small, or not 4 byte aligned? */
+  while ((dhcp->options_out_len < DHCP_MIN_OPTIONS_LEN) || (dhcp->options_out_len & 3)) {
+    /* LWIP_DEBUGF(DHCP_DEBUG,("dhcp_option_trailer:dhcp->options_out_len=%"U16_F", DHCP_OPTIONS_LEN=%"U16_F, dhcp->options_out_len, DHCP_OPTIONS_LEN)); */
+    LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+    /* add a fill/padding byte */
+    dhcp->msg_out->options[dhcp->options_out_len++] = 0;
+  }
+}
+
+/**
+ * Find the offset of a DHCP option inside the DHCP message.
+ *
+ * @param dhcp DHCP client
+ * @param option_type
+ *
+ * @return a byte offset into the UDP message where the option was found, or
+ * zero if the given option was not found.
+ */
+static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type)
+{
+  u8_t overload = DHCP_OVERLOAD_NONE;
+
+  /* options available? */
+  if ((dhcp->options_in != NULL) && (dhcp->options_in_len > 0)) {
+    /* start with options field */
+    u8_t *options = (u8_t *)dhcp->options_in;
+    u16_t offset = 0;
+    /* at least 1 byte to read and no end marker, then at least 3 bytes to read? */
+    while ((offset < dhcp->options_in_len) && (options[offset] != DHCP_OPTION_END)) {
+      /* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%"U16_F", q->len=%"U16_F, msg_offset, q->len)); */
+      /* are the sname and/or file field overloaded with options? */
+      if (options[offset] == DHCP_OPTION_OVERLOAD) {
+        LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 2, ("overloaded message detected\n"));
+        /* skip option type and length */
+        offset += 2;
+        overload = options[offset++];
+      }
+      /* requested option found */
+      else if (options[offset] == option_type) {
+        LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("option found at offset %"U16_F" in options\n", offset));
+        return &options[offset];
+      /* skip option */
+      } else {
+         LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %"U16_F" in options\n", options[offset]));
+        /* skip option type */
+        offset++;
+        /* skip option length, and then length bytes */
+        offset += 1 + options[offset];
+      }
+    }
+    /* is this an overloaded message? */
+    if (overload != DHCP_OVERLOAD_NONE) {
+      u16_t field_len;
+      if (overload == DHCP_OVERLOAD_FILE) {
+        LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 1, ("overloaded file field\n"));
+        options = (u8_t *)&dhcp->msg_in->file;
+        field_len = DHCP_FILE_LEN;
+      } else if (overload == DHCP_OVERLOAD_SNAME) {
+        LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 1, ("overloaded sname field\n"));
+        options = (u8_t *)&dhcp->msg_in->sname;
+        field_len = DHCP_SNAME_LEN;
+      /* TODO: check if else if () is necessary */
+      } else {
+        LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | 1, ("overloaded sname and file field\n"));
+        options = (u8_t *)&dhcp->msg_in->sname;
+        field_len = DHCP_FILE_LEN + DHCP_SNAME_LEN;
+      }
+      offset = 0;
+
+      /* at least 1 byte to read and no end marker */
+      while ((offset < field_len) && (options[offset] != DHCP_OPTION_END)) {
+        if (options[offset] == option_type) {
+           LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("option found at offset=%"U16_F"\n", offset));
+          return &options[offset];
+        /* skip option */
+        } else {
+          LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("skipping option %"U16_F"\n", options[offset]));
+          /* skip option type */
+          offset++;
+          offset += 1 + options[offset];
+        }
+      }
+    }
+  }
+  return NULL;
+}
+
+/**
+ * Return the byte of DHCP option data.
+ *
+ * @param client DHCP client.
+ * @param ptr pointer obtained by dhcp_get_option_ptr().
+ *
+ * @return byte value at the given address.
+ */
+static u8_t
+dhcp_get_option_byte(u8_t *ptr)
+{
+  LWIP_DEBUGF(DHCP_DEBUG, ("option byte value=%"U16_F"\n", (u16_t)(*ptr)));
+  return *ptr;
+}
+
+#if 0 /* currently unused */
+/**
+ * Return the 16-bit value of DHCP option data.
+ *
+ * @param client DHCP client.
+ * @param ptr pointer obtained by dhcp_get_option_ptr().
+ *
+ * @return byte value at the given address.
+ */
+static u16_t
+dhcp_get_option_short(u8_t *ptr)
+{
+  u16_t value;
+  value = *ptr++ << 8;
+  value |= *ptr;
+  LWIP_DEBUGF(DHCP_DEBUG, ("option short value=%"U16_F"\n", value));
+  return value;
+}
+#endif
+
+/**
+ * Return the 32-bit value of DHCP option data.
+ *
+ * @param client DHCP client.
+ * @param ptr pointer obtained by dhcp_get_option_ptr().
+ *
+ * @return byte value at the given address.
+ */
+static u32_t dhcp_get_option_long(u8_t *ptr)
+{
+  u32_t value;
+  value = (u32_t)(*ptr++) << 24;
+  value |= (u32_t)(*ptr++) << 16;
+  value |= (u32_t)(*ptr++) << 8;
+  value |= (u32_t)(*ptr++);
+  LWIP_DEBUGF(DHCP_DEBUG, ("option long value=%"U32_F"\n", value));
+  return value;
+}
+
+#endif /* LWIP_DHCP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/dns.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/dns.c
new file mode 100644
index 0000000..defd7e4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/dns.c
@@ -0,0 +1,823 @@
+/**
+ * @file
+ * DNS - host name to IP address resolver.
+ *
+ */
+
+/**
+
+ * This file implements a DNS host name to IP address resolver.
+
+ * Port to lwIP from uIP
+ * by Jim Pettinato April 2007
+
+ * uIP version Copyright (c) 2002-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * DNS.C
+ *
+ * The lwIP DNS resolver functions are used to lookup a host name and
+ * map it to a numerical IP address. It maintains a list of resolved
+ * hostnames that can be queried with the dns_lookup() function.
+ * New hostnames can be resolved using the dns_query() function.
+ *
+ * The lwIP version of the resolver also adds a non-blocking version of
+ * gethostbyname() that will work with a raw API application. This function
+ * checks for an IP address string first and converts it if it is valid.
+ * gethostbyname() then does a dns_lookup() to see if the name is 
+ * already in the table. If so, the IP is returned. If not, a query is 
+ * issued and the function returns with a ERR_INPROGRESS status. The app
+ * using the dns client must then go into a waiting state.
+ *
+ * Once a hostname has been resolved (or found to be non-existent),
+ * the resolver code calls a specified callback function (which 
+ * must be implemented by the module that uses the resolver).
+ */
+
+/*-----------------------------------------------------------------------------
+ * RFC 1035 - Domain names - implementation and specification
+ * RFC 2181 - Clarifications to the DNS Specification
+ *----------------------------------------------------------------------------*/
+
+/** @todo: define good default values (rfc compliance) */
+/** @todo: improve answer parsing, more checkings... */
+/** @todo: check RFC1035 - 7.3. Processing responses */
+
+/*-----------------------------------------------------------------------------
+ * Includes
+ *----------------------------------------------------------------------------*/
+
+#include "lwip/opt.h"
+
+#if LWIP_DNS /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/udp.h"
+#include "lwip/mem.h"
+#include "lwip/dns.h"
+
+#include 
+
+/** DNS server IP address */
+#ifndef DNS_SERVER_ADDRESS
+#define DNS_SERVER_ADDRESS        inet_addr("208.67.222.222") /* resolver1.opendns.com */
+#endif
+
+/** DNS server port address */
+#ifndef DNS_SERVER_PORT
+#define DNS_SERVER_PORT           53
+#endif
+
+/** DNS maximum number of retries when asking for a name, before "timeout". */
+#ifndef DNS_MAX_RETRIES
+#define DNS_MAX_RETRIES           4
+#endif
+
+/** DNS resource record max. TTL (one week as default) */
+#ifndef DNS_MAX_TTL
+#define DNS_MAX_TTL               604800
+#endif
+
+/* DNS protocol flags */
+#define DNS_FLAG1_RESPONSE        0x80
+#define DNS_FLAG1_OPCODE_STATUS   0x10
+#define DNS_FLAG1_OPCODE_INVERSE  0x08
+#define DNS_FLAG1_OPCODE_STANDARD 0x00
+#define DNS_FLAG1_AUTHORATIVE     0x04
+#define DNS_FLAG1_TRUNC           0x02
+#define DNS_FLAG1_RD              0x01
+#define DNS_FLAG2_RA              0x80
+#define DNS_FLAG2_ERR_MASK        0x0f
+#define DNS_FLAG2_ERR_NONE        0x00
+#define DNS_FLAG2_ERR_NAME        0x03
+
+/* DNS protocol states */
+#define DNS_STATE_UNUSED          0
+#define DNS_STATE_NEW             1
+#define DNS_STATE_ASKING          2
+#define DNS_STATE_DONE            3
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+#if (defined(__MWERKS__)  || defined(__CWCC__))
+	#pragma options align= packed
+#endif
+/** DNS message header */
+struct dns_hdr {
+  u16_t id;
+  u8_t flags1;
+  u8_t flags2;
+  u16_t numquestions;
+  u16_t numanswers;
+  u16_t numauthrr;
+  u16_t numextrarr;
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+#if (defined(__MWERKS__)  || defined(__CWCC__))
+	#pragma options align= packed
+#endif
+/** DNS query message structure */
+struct dns_query {
+  /* DNS query record starts with either a domain name or a pointer
+     to a name already present somewhere in the packet. */
+  u16_t type;
+  u16_t class;
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+#if (defined(__MWERKS__)  || defined(__CWCC__))
+	#pragma options align= packed
+#endif
+/** DNS answer message structure */
+struct dns_answer {
+  /* DNS answer record starts with either a domain name or a pointer
+     to a name already present somewhere in the packet. */
+  u16_t type;
+  u16_t class;
+  u32_t ttl;
+  u16_t len;
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** DNS table entry */
+struct dns_table_entry {
+  u8_t  state;
+  u8_t  numdns;
+  u8_t  tmr;
+  u8_t  retries;
+  u8_t  seqno;
+  u8_t  err;
+  u32_t ttl;
+  char name[DNS_MAX_NAME_LENGTH];
+  struct ip_addr ipaddr;
+  /* pointer to callback on DNS query done */
+  dns_found_callback found;
+  void *arg;
+};
+
+
+/* forward declarations */
+static void dns_recv(void *s, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port);
+static void dns_check_entries(void);
+
+/*-----------------------------------------------------------------------------
+ * Globales
+ *----------------------------------------------------------------------------*/
+
+/* DNS variables */
+static struct udp_pcb        *dns_pcb;
+static u8_t                   dns_seqno;
+static struct dns_table_entry dns_table[DNS_TABLE_SIZE];
+static struct ip_addr         dns_servers[DNS_MAX_SERVERS];
+
+#if (DNS_USES_STATIC_BUF == 1)
+static u8_t                   dns_payload[DNS_MSG_SIZE];
+#endif /* (DNS_USES_STATIC_BUF == 1) */
+
+/**
+ * Initialize the resolver: set up the UDP pcb and configure the default server
+ * (DNS_SERVER_ADDRESS).
+ */
+void
+dns_init()
+{
+  struct ip_addr dnsserver;
+  
+  /* initialize default DNS server address */
+  dnsserver.addr = DNS_SERVER_ADDRESS;
+
+  LWIP_DEBUGF(DNS_DEBUG, ("dns_init: initializing\n"));
+
+  /* if dns client not yet initialized... */
+  if (dns_pcb == NULL) {
+    dns_pcb = udp_new();
+
+    if (dns_pcb != NULL) {
+      /* initialize DNS table not needed (initialized to zero since it is a
+       * global variable) */
+      LWIP_ASSERT("For implicit initialization to work, DNS_STATE_UNUSED needs to be 0",
+        DNS_STATE_UNUSED == 0);
+
+      /* initialize DNS client */
+      udp_bind(dns_pcb, IP_ADDR_ANY, 0);
+      udp_recv(dns_pcb, dns_recv, NULL);
+
+      /* initialize default DNS primary server */
+      dns_setserver(0, &dnsserver);
+    }
+  }
+}
+
+/**
+ * Initialize one of the DNS servers.
+ *
+ * @param numdns the index of the DNS server to set must be < DNS_MAX_SERVERS
+ * @param dnsserver IP address of the DNS server to set
+ */
+void
+dns_setserver(u8_t numdns, struct ip_addr *dnsserver)
+{
+  if ((numdns < DNS_MAX_SERVERS) && (dns_pcb != NULL) &&
+      (dnsserver != NULL) && (dnsserver->addr !=0 )) {
+    dns_servers[numdns] = (*dnsserver);
+  }
+}
+
+/**
+ * Obtain one of the currently configured DNS server.
+ *
+ * @param numdns the index of the DNS server
+ * @return IP address of the indexed DNS server or "ip_addr_any" if the DNS
+ *         server has not been configured.
+ */
+struct ip_addr
+dns_getserver(u8_t numdns)
+{
+  if (numdns < DNS_MAX_SERVERS) {
+    return dns_servers[numdns];
+  } else {
+    return *IP_ADDR_ANY;
+  }
+}
+
+/**
+ * The DNS resolver client timer - handle retries and timeouts and should
+ * be called every DNS_TMR_INTERVAL milliseconds (every second by default).
+ */
+void
+dns_tmr(void)
+{
+  if (dns_pcb != NULL) {
+    LWIP_DEBUGF(DNS_DEBUG, ("dns_tmr: dns_check_entries\n"));
+    dns_check_entries();
+  }
+}
+
+/**
+ * Look up a hostname in the array of known hostnames.
+ *
+ * @note This function only looks in the internal array of known
+ * hostnames, it does not send out a query for the hostname if none
+ * was found. The function dns_enqueue() can be used to send a query
+ * for a hostname.
+ *
+ * @param name the hostname to look up
+ * @return the hostname's IP address, as u32_t (instead of struct ip_addr to
+ *         better check for failure: != 0) or 0 if the hostname was not found
+ *         in the cached dns_table.
+ */
+static u32_t
+dns_lookup(const char *name)
+{
+  u8_t i;
+
+  /* Walk through name list, return entry if found. If not, return NULL. */
+  for (i = 0; i < DNS_TABLE_SIZE; ++i) {
+    if ((dns_table[i].state == DNS_STATE_DONE) &&
+        (strcmp(name, dns_table[i].name) == 0)) {
+      LWIP_DEBUGF(DNS_DEBUG, ("dns_lookup: \"%s\": found = ", name));
+      ip_addr_debug_print(DNS_DEBUG, &(dns_table[i].ipaddr));
+      LWIP_DEBUGF(DNS_DEBUG, ("\n"));
+      return dns_table[i].ipaddr.addr;
+    }
+  }
+
+  return 0;
+}
+
+#if DNS_DOES_NAME_CHECK
+/**
+ * Compare the "dotted" name "query" with the encoded name "response"
+ * to make sure an answer from the DNS server matches the current dns_table
+ * entry (otherwise, answers might arrive late for hostname not on the list
+ * any more).
+ *
+ * @param query hostname (not encoded) from the dns_table
+ * @param response encoded hostname in the DNS response
+ * @return 0: names equal; 1: names differ
+ */
+static u8_t
+dns_compare_name(unsigned char *query, unsigned char *response)
+{
+  unsigned char n;
+
+  do {
+    n = *response++;
+    /** @see RFC 1035 - 4.1.4. Message compression */
+    if ((n & 0xc0) == 0xc0) {
+      /* Compressed name */
+      break;
+    } else {
+      /* Not compressed name */
+      while (n > 0) {
+        if ((*query) != (*response)) {
+          return 1;
+        }
+        ++response;
+        ++query;
+        --n;
+      };
+      ++query;
+    }
+  } while (*response != 0);
+
+  return 0;
+}
+#endif /* DNS_DOES_NAME_CHECK */
+
+/**
+ * Walk through a compact encoded DNS name and return the end of the name.
+ *
+ * @param query encoded DNS name in the DNS server response
+ * @return end of the name
+ */
+static unsigned char *
+dns_parse_name(unsigned char *query)
+{
+  unsigned char n;
+
+  do {
+    n = *query++;
+    /** @see RFC 1035 - 4.1.4. Message compression */
+    if ((n & 0xc0) == 0xc0) {
+      /* Compressed name */
+      break;
+    } else {
+      /* Not compressed name */
+      while (n > 0) {
+        ++query;
+        --n;
+      };
+    }
+  } while (*query != 0);
+
+  return query + 1;
+}
+
+/**
+ * Send a DNS query packet.
+ *
+ * @param numdns index of the DNS server in the dns_servers table
+ * @param name hostname to query
+ * @param id index of the hostname in dns_table, used as transaction ID in the
+ *        DNS query packet
+ * @return ERR_OK if packet is sent; an err_t indicating the problem otherwise
+ */
+static err_t
+dns_send(u8_t numdns, const char* name, u8_t id)
+{
+  err_t err;
+  struct dns_hdr *hdr;
+  struct dns_query qry;
+  struct pbuf *p;
+  char *query, *nptr;
+  const char *pHostname;
+  u8_t n;
+
+  LWIP_DEBUGF(DNS_DEBUG, ("dns_send: dns_servers[%"U16_F"] \"%s\": request\n",
+              (u16_t)(numdns), name));
+  LWIP_ASSERT("dns server out of array", numdns < DNS_MAX_SERVERS);
+  LWIP_ASSERT("dns server has no IP address set", dns_servers[numdns].addr != 0);
+
+  /* if here, we have either a new query or a retry on a previous query to process */
+  p = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dns_hdr) + DNS_MAX_NAME_LENGTH +
+                 sizeof(struct dns_query), PBUF_RAM);
+  if (p != NULL) {
+    LWIP_ASSERT("pbuf must be in one piece", p->next == NULL);
+    /* fill dns header */
+    hdr = (struct dns_hdr*)p->payload;
+    memset(hdr, 0, sizeof(struct dns_hdr));
+    hdr->id = htons(id);
+    hdr->flags1 = DNS_FLAG1_RD;
+    hdr->numquestions = htons(1);
+    query = (char*)hdr + sizeof(struct dns_hdr);
+    pHostname = name;
+    --pHostname;
+
+    /* convert hostname into suitable query format. */
+    do {
+      ++pHostname;
+      nptr = query;
+      ++query;
+      for(n = 0; *pHostname != '.' && *pHostname != 0; ++pHostname) {
+        *query = *pHostname;
+        ++query;
+        ++n;
+      }
+      *nptr = n;
+    } while(*pHostname != 0);
+    *query++='\0';
+
+    /* fill dns query */
+    qry.type  = htons(DNS_RRTYPE_A);
+    qry.class = htons(DNS_RRCLASS_IN);
+    MEMCPY( query, &qry, sizeof(struct dns_query));
+
+    /* resize pbuf to the exact dns query */
+    pbuf_realloc(p, (query + sizeof(struct dns_query)) - ((char*)(p->payload)));
+
+    /* connect to the server for faster receiving */
+    udp_connect(dns_pcb, &dns_servers[numdns], DNS_SERVER_PORT);
+    /* send dns packet */
+    err = udp_sendto(dns_pcb, p, &dns_servers[numdns], DNS_SERVER_PORT);
+
+    /* free pbuf */
+    pbuf_free(p);
+  } else {
+    err = ERR_MEM;
+  }
+
+  return err;
+}
+
+/**
+ * dns_check_entry() - see if pEntry has not yet been queried and, if so, sends out a query.
+ * Check an entry in the dns_table:
+ * - send out query for new entries
+ * - retry old pending entries on timeout (also with different servers)
+ * - remove completed entries from the table if their TTL has expired
+ *
+ * @param i index of the dns_table entry to check
+ */
+static void
+dns_check_entry(u8_t i)
+{
+  struct dns_table_entry *pEntry = &dns_table[i];
+
+  LWIP_ASSERT("array index out of bounds", i < DNS_TABLE_SIZE);
+
+  switch(pEntry->state) {
+
+    case DNS_STATE_NEW: {
+      /* initialize new entry */
+      pEntry->state   = DNS_STATE_ASKING;
+      pEntry->numdns  = 0;
+      pEntry->tmr     = 1;
+      pEntry->retries = 0;
+      
+      /* send DNS packet for this entry */
+      dns_send(pEntry->numdns, pEntry->name, i);
+      break;
+    }
+
+    case DNS_STATE_ASKING: {
+      if (--pEntry->tmr == 0) {
+        if (++pEntry->retries == DNS_MAX_RETRIES) {
+          if ((pEntry->numdns+1numdns+1].addr!=0)) {
+            /* change of server */
+            pEntry->numdns++;
+            pEntry->tmr     = 1;
+            pEntry->retries = 0;
+            break;
+          } else {
+            LWIP_DEBUGF(DNS_DEBUG, ("dns_check_entry: \"%s\": timeout\n", pEntry->name));
+            /* call specified callback function if provided */
+            if (pEntry->found)
+              (*pEntry->found)(pEntry->name, NULL, pEntry->arg);
+            /* flush this entry */
+            pEntry->state   = DNS_STATE_UNUSED;
+            pEntry->found   = NULL;
+            break;
+          }
+        }
+
+        /* wait longer for the next retry */
+        pEntry->tmr = pEntry->retries;
+
+        /* send DNS packet for this entry */
+        dns_send(pEntry->numdns, pEntry->name, i);
+      }
+      break;
+    }
+
+    case DNS_STATE_DONE: {
+      /* if the time to live is nul */
+      if (--pEntry->ttl == 0) {
+        LWIP_DEBUGF(DNS_DEBUG, ("dns_check_entry: \"%s\": flush\n", pEntry->name));
+        /* flush this entry */
+        pEntry->state = DNS_STATE_UNUSED;
+        pEntry->found = NULL;
+      }
+      break;
+    }
+    case DNS_STATE_UNUSED:
+      /* nothing to do */
+      break;
+    default:
+      LWIP_ASSERT("unknown dns_table entry state:", 0);
+      break;
+  }
+}
+
+/**
+ * Call dns_check_entry for each entry in dns_table - check all entries.
+ */
+static void
+dns_check_entries(void)
+{
+  u8_t i;
+
+  for (i = 0; i < DNS_TABLE_SIZE; ++i) {
+    dns_check_entry(i);
+  }
+}
+
+/**
+ * Receive input function for DNS response packets arriving for the dns UDP pcb.
+ *
+ * @params see udp.h
+ */
+static void
+dns_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port)
+{
+  u8_t i;
+  char *pHostname;
+  struct dns_hdr *hdr;
+  struct dns_answer ans;
+  struct dns_table_entry *pEntry;
+  u8_t nquestions, nanswers;
+#if (DNS_USES_STATIC_BUF == 0)
+  u8_t dns_payload[DNS_MSG_SIZE];
+#endif /* (DNS_USES_STATIC_BUF == 0) */
+#if (DNS_USES_STATIC_BUF == 2)
+  u8_t* dns_payload;
+#endif /* (DNS_USES_STATIC_BUF == 2) */
+
+  LWIP_UNUSED_ARG(arg);
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_UNUSED_ARG(addr);
+  LWIP_UNUSED_ARG(port);
+
+  /* is the dns message too big ? */
+  if (p->tot_len > DNS_MSG_SIZE) {
+    LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: pbuf too big\n"));
+    /* free pbuf and return */
+    goto memerr1;
+  }
+
+  /* is the dns message big enough ? */
+  if (p->tot_len < (sizeof(struct dns_hdr) + sizeof(struct dns_query) + sizeof(struct dns_answer))) {
+    LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: pbuf too small\n"));
+    /* free pbuf and return */
+    goto memerr1;
+  }
+
+#if (DNS_USES_STATIC_BUF == 2)
+  dns_payload = mem_malloc(p->tot_len);
+  if (dns_payload == NULL) {
+    LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: mem_malloc error\n"));
+    /* free pbuf and return */
+    goto memerr1;
+  }
+#endif /* (DNS_USES_STATIC_BUF == 2) */
+
+  /* copy dns payload inside static buffer for processing */ 
+  if (pbuf_copy_partial(p, dns_payload, p->tot_len, 0) == p->tot_len) {
+    /* The ID in the DNS header should be our entry into the name table. */
+    hdr = (struct dns_hdr*)dns_payload;
+    i = htons(hdr->id);
+    if (i < DNS_TABLE_SIZE) {
+      pEntry = &dns_table[i];
+      if(pEntry->state == DNS_STATE_ASKING) {
+        /* This entry is now completed. */
+        pEntry->state = DNS_STATE_DONE;
+        pEntry->err   = hdr->flags2 & DNS_FLAG2_ERR_MASK;
+
+        /* We only care about the question(s) and the answers. The authrr
+           and the extrarr are simply discarded. */
+        nquestions = htons(hdr->numquestions);
+        nanswers   = htons(hdr->numanswers);
+
+        /* Check for error. If so, call callback to inform. */
+        if (((hdr->flags1 & DNS_FLAG1_RESPONSE) == 0) || (pEntry->err != 0) || (nquestions != 1)) {
+          LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": error in flags\n", pEntry->name));
+          /* call callback to indicate error, clean up memory and return */
+          goto responseerr;
+        }
+
+#if DNS_DOES_NAME_CHECK
+        /* Check if the name in the "question" part match with the name in the entry. */
+        if (dns_compare_name((unsigned char *)(pEntry->name), (unsigned char *)dns_payload + sizeof(struct dns_hdr)) != 0) {
+          LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response not match to query\n", pEntry->name));
+          /* call callback to indicate error, clean up memory and return */
+          goto responseerr;
+        }
+#endif /* DNS_DOES_NAME_CHECK */
+
+        /* Skip the name in the "question" part */
+        pHostname = (char *) dns_parse_name((unsigned char *)dns_payload + sizeof(struct dns_hdr)) + sizeof(struct dns_query);
+
+        while(nanswers > 0) {
+          /* skip answer resource record's host name */
+          pHostname = (char *) dns_parse_name((unsigned char *)pHostname);
+
+          /* Check for IP address type and Internet class. Others are discarded. */
+          MEMCPY(&ans, pHostname, sizeof(struct dns_answer));
+          if((ntohs(ans.type) == DNS_RRTYPE_A) && (ntohs(ans.class) == DNS_RRCLASS_IN) && (ntohs(ans.len) == sizeof(struct ip_addr)) ) {
+            /* read the answer resource record's TTL, and maximize it if needed */
+            pEntry->ttl = ntohl(ans.ttl);
+            if (pEntry->ttl > DNS_MAX_TTL) {
+              pEntry->ttl = DNS_MAX_TTL;
+            }
+            /* read the IP address after answer resource record's header */
+            MEMCPY( &(pEntry->ipaddr), (pHostname+sizeof(struct dns_answer)), sizeof(struct ip_addr));
+            LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response = ", pEntry->name));
+            ip_addr_debug_print(DNS_DEBUG, (&(pEntry->ipaddr)));
+            LWIP_DEBUGF(DNS_DEBUG, ("\n"));
+            /* call specified callback function if provided */
+            if (pEntry->found) {
+              (*pEntry->found)(pEntry->name, &pEntry->ipaddr, pEntry->arg);
+            }
+            /* deallocate memory and return */
+            goto memerr2;
+          } else {
+            pHostname = pHostname + sizeof(struct dns_answer) + htons(ans.len);
+          }
+          --nanswers;
+        }
+        LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": error in response\n", pEntry->name));
+        /* call callback to indicate error, clean up memory and return */
+        goto responseerr;
+      }
+    }
+  }
+
+  /* deallocate memory and return */
+  goto memerr2;
+
+responseerr:
+  /* ERROR: call specified callback function with NULL as name to indicate an error */
+  if (pEntry->found) {
+    (*pEntry->found)(pEntry->name, NULL, pEntry->arg);
+  }
+  /* flush this entry */
+  pEntry->state = DNS_STATE_UNUSED;
+  pEntry->found = NULL;
+
+memerr2:
+#if (DNS_USES_STATIC_BUF == 2)
+  /* free dns buffer */
+  mem_free(dns_payload);
+#endif /* (DNS_USES_STATIC_BUF == 2) */
+
+memerr1:
+  /* free pbuf */
+  pbuf_free(p);
+  return;
+}
+
+/**
+ * Queues a new hostname to resolve and sends out a DNS query for that hostname
+ *
+ * @param name the hostname that is to be queried
+ * @param found a callback founction to be called on success, failure or timeout
+ * @param callback_arg argument to pass to the callback function
+ * @return @return a err_t return code.
+ */
+static err_t
+dns_enqueue(const char *name, dns_found_callback found, void *callback_arg)
+{
+  u8_t i;
+  u8_t lseq, lseqi;
+  struct dns_table_entry *pEntry = NULL;
+
+  /* search an unused entry, or the oldest one */
+  lseq = lseqi = 0;
+  for (i = 0; i < DNS_TABLE_SIZE; ++i) {
+    pEntry = &dns_table[i];
+    /* is it an unused entry ? */
+    if (pEntry->state == DNS_STATE_UNUSED)
+      break;
+
+    /* check if this is the oldest completed entry */
+    if (pEntry->state == DNS_STATE_DONE) {
+      if ((dns_seqno - pEntry->seqno) > lseq) {
+        lseq = dns_seqno - pEntry->seqno;
+        lseqi = i;
+      }
+    }
+  }
+
+  /* if we don't have found an unused entry, use the oldest completed one */
+  if (i == DNS_TABLE_SIZE) {
+    if ((lseqi >= DNS_TABLE_SIZE) || (dns_table[lseqi].state != DNS_STATE_DONE)) {
+      /* no entry can't be used now, table is full */
+      LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": DNS entries table is full\n", name));
+      return ERR_MEM;
+    } else {
+      /* use the oldest completed one */
+      i = lseqi;
+      pEntry = &dns_table[i];
+    }
+  }
+
+  /* use this entry */
+  LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": use DNS entry %"U16_F"\n", name, (u16_t)(i)));
+
+  /* fill the entry */
+  pEntry->state = DNS_STATE_NEW;
+  pEntry->seqno = dns_seqno++;
+  pEntry->found = found;
+  pEntry->arg   = callback_arg;
+  strcpy(pEntry->name, name);
+
+  /* force to send query without waiting timer */
+  dns_check_entry(i);
+
+  /* dns query is enqueued */
+  return ERR_INPROGRESS;
+}
+
+/**
+ * Resolve a hostname (string) into an IP address.
+ * NON-BLOCKING callback version for use with raw API!!!
+ *
+ * Returns immediately with one of err_t return codes:
+ * - ERR_OK if hostname is a valid IP address string or the host
+ *   name is already in the local names table.
+ * - ERR_INPROGRESS enqueue a request to be sent to the DNS server
+ *   for resolution if no errors are present.
+ *
+ * @param hostname the hostname that is to be queried
+ * @param addr pointer to a struct ip_addr where to store the address if it is already
+ *             cached in the dns_table (only valid if ERR_OK is returned!)
+ * @param found a callback function to be called on success, failure or timeout (only if
+ *              ERR_INPROGRESS is returned!)
+ * @param callback_arg argument to pass to the callback function
+ * @return a err_t return code.
+ */
+err_t
+dns_gethostbyname(const char *hostname, struct ip_addr *addr, dns_found_callback found,
+                  void *callback_arg)
+{
+  /* not initialized or no valid server yet, or invalid addr pointer
+   * or invalid hostname or invalid hostname length */
+  if ((dns_pcb == NULL) || (addr == NULL) ||
+      (!hostname) || (!hostname[0]) ||
+      (strlen(hostname) >= DNS_MAX_NAME_LENGTH)) {
+    return ERR_VAL;
+  }
+
+#if LWIP_HAVE_LOOPIF
+  if (strcmp(hostname,"localhost")==0) {
+    addr->addr = INADDR_LOOPBACK;
+    return ERR_OK;
+  }
+#endif /* LWIP_HAVE_LOOPIF */
+
+  /* host name already in octet notation? set ip addr and return ERR_OK
+   * already have this address cached? */
+  if (((addr->addr = inet_addr(hostname)) != INADDR_NONE) ||
+      ((addr->addr = dns_lookup(hostname)) != 0)) {
+    return ERR_OK;
+  }
+
+  /* queue query with specified callback */
+  return dns_enqueue(hostname, found, callback_arg);
+}
+
+#endif /* LWIP_DNS */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/init.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/init.c
new file mode 100644
index 0000000..1faacb8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/init.c
@@ -0,0 +1,253 @@
+/**
+ * @file
+ * Modules initialization
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/init.h"
+#include "lwip/stats.h"
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/sockets.h"
+#include "lwip/ip.h"
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+#include "lwip/autoip.h"
+#include "lwip/igmp.h"
+#include "lwip/dns.h"
+#include "netif/etharp.h"
+
+/* Compile-time sanity checks for configuration errors.
+ * These can be done independently of LWIP_DEBUG, without penalty.
+ */
+#ifndef BYTE_ORDER
+  #error "BYTE_ORDER is not defined, you have to define it in your cc.h"
+#endif
+#if (!LWIP_ARP && ARP_QUEUEING)
+  #error "If you want to use ARP Queueing, you have to define LWIP_ARP=1 in your lwipopts.h"
+#endif
+#if (!LWIP_UDP && LWIP_UDPLITE)
+  #error "If you want to use UDP Lite, you have to define LWIP_UDP=1 in your lwipopts.h"
+#endif
+#if (!LWIP_UDP && LWIP_SNMP)
+  #error "If you want to use SNMP, you have to define LWIP_UDP=1 in your lwipopts.h"
+#endif
+#if (!LWIP_UDP && LWIP_DHCP)
+  #error "If you want to use DHCP, you have to define LWIP_UDP=1 in your lwipopts.h"
+#endif
+#if (!LWIP_UDP && LWIP_IGMP)
+  #error "If you want to use IGMP, you have to define LWIP_UDP=1 in your lwipopts.h"
+#endif
+#if (!LWIP_UDP && LWIP_DNS)
+  #error "If you want to use DNS, you have to define LWIP_UDP=1 in your lwipopts.h"
+#endif
+#if (LWIP_ARP && (ARP_TABLE_SIZE > 0x7f))
+  #error "If you want to use ARP, ARP_TABLE_SIZE must fit in an s8_t, so, you have to reduce it in your lwipopts.h"
+#endif
+#if (LWIP_ARP && ARP_QUEUEING && (MEMP_NUM_ARP_QUEUE<=0))
+  #error "If you want to use ARP Queueing, you have to define MEMP_NUM_ARP_QUEUE>=1 in your lwipopts.h"
+#endif
+#if (LWIP_RAW && (MEMP_NUM_RAW_PCB<=0))
+  #error "If you want to use RAW, you have to define MEMP_NUM_RAW_PCB>=1 in your lwipopts.h"
+#endif
+#if (LWIP_UDP && (MEMP_NUM_UDP_PCB<=0))
+  #error "If you want to use UDP, you have to define MEMP_NUM_UDP_PCB>=1 in your lwipopts.h"
+#endif
+#if (LWIP_TCP && (MEMP_NUM_TCP_PCB<=0))
+  #error "If you want to use TCP, you have to define MEMP_NUM_TCP_PCB>=1 in your lwipopts.h"
+#endif
+#if (LWIP_TCP && (TCP_WND > 0xffff))
+  #error "If you want to use TCP, TCP_WND must fit in an u16_t, so, you have to reduce it in your lwipopts.h"
+#endif
+#if (LWIP_TCP && (TCP_SND_QUEUELEN > 0xffff))
+  #error "If you want to use TCP, TCP_SND_QUEUELEN must fit in an u16_t, so, you have to reduce it in your lwipopts.h"
+#endif
+#if (LWIP_TCP && ((TCP_MAXRTX > 12) || (TCP_SYNMAXRTX > 12)))
+  #error "If you want to use TCP, TCP_MAXRTX and TCP_SYNMAXRTX must less or equal to 12 (due to tcp_backoff table), so, you have to reduce them in your lwipopts.h"
+#endif
+#if (LWIP_TCP && TCP_LISTEN_BACKLOG && (TCP_DEFAULT_LISTEN_BACKLOG < 0) || (TCP_DEFAULT_LISTEN_BACKLOG > 0xff))
+  #error "If you want to use TCP backlog, TCP_DEFAULT_LISTEN_BACKLOG must fit into an u8_t"
+#endif
+#if (LWIP_IGMP && (MEMP_NUM_IGMP_GROUP<=1))
+  #error "If you want to use IGMP, you have to define MEMP_NUM_IGMP_GROUP>1 in your lwipopts.h"
+#endif
+#if (PPP_SUPPORT && (NO_SYS==1))
+  #error "If you want to use PPP, you have to define NO_SYS=0 in your lwipopts.h"
+#endif
+#if (LWIP_NETIF_API && (NO_SYS==1))
+  #error "If you want to use NETIF API, you have to define NO_SYS=0 in your lwipopts.h"
+#endif
+#if ((LWIP_SOCKET || LWIP_NETCONN) && (NO_SYS==1))
+  #error "If you want to use Sequential API, you have to define NO_SYS=0 in your lwipopts.h"
+#endif
+#if ((LWIP_NETCONN || LWIP_SOCKET) && (MEMP_NUM_TCPIP_MSG_API<=0))
+  #error "If you want to use Sequential API, you have to define MEMP_NUM_TCPIP_MSG_API>=1 in your lwipopts.h"
+#endif
+#if (!LWIP_NETCONN && LWIP_SOCKET)
+  #error "If you want to use Socket API, you have to define LWIP_NETCONN=1 in your lwipopts.h"
+#endif
+#if (((!LWIP_DHCP) || (!LWIP_AUTOIP)) && LWIP_DHCP_AUTOIP_COOP)
+  #error "If you want to use DHCP/AUTOIP cooperation mode, you have to define LWIP_DHCP=1 and LWIP_AUTOIP=1 in your lwipopts.h"
+#endif
+#if (((!LWIP_DHCP) || (!LWIP_ARP)) && DHCP_DOES_ARP_CHECK)
+  #error "If you want to use DHCP ARP checking, you have to define LWIP_DHCP=1 and LWIP_ARP=1 in your lwipopts.h"
+#endif
+#if (!LWIP_ARP && LWIP_AUTOIP)
+  #error "If you want to use AUTOIP, you have to define LWIP_ARP=1 in your lwipopts.h"
+#endif
+#if (LWIP_SNMP && (SNMP_CONCURRENT_REQUESTS<=0))
+  #error "If you want to use SNMP, you have to define SNMP_CONCURRENT_REQUESTS>=1 in your lwipopts.h"
+#endif
+#if (LWIP_SNMP && (SNMP_TRAP_DESTINATIONS<=0))
+  #error "If you want to use SNMP, you have to define SNMP_TRAP_DESTINATIONS>=1 in your lwipopts.h"
+#endif
+#if (LWIP_TCP && ((LWIP_EVENT_API && LWIP_CALLBACK_API) || (!LWIP_EVENT_API && !LWIP_CALLBACK_API)))
+  #error "One and exactly one of LWIP_EVENT_API and LWIP_CALLBACK_API has to be enabled in your lwipopts.h"
+#endif
+/* There must be sufficient timeouts, taking into account requirements of the subsystems. */
+#if ((NO_SYS==0) && (MEMP_NUM_SYS_TIMEOUT < (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + PPP_SUPPORT)))
+  #error "MEMP_NUM_SYS_TIMEOUT is too low to accomodate all required timeouts"
+#endif
+#if (IP_REASSEMBLY && (MEMP_NUM_REASSDATA > IP_REASS_MAX_PBUFS))
+  #error "MEMP_NUM_REASSDATA > IP_REASS_MAX_PBUFS doesn't make sense since each struct ip_reassdata must hold 2 pbufs at least!"
+#endif
+#if (MEM_LIBC_MALLOC && MEM_USE_POOLS)
+  #error "MEM_LIBC_MALLOC and MEM_USE_POOLS may not both be simultaneously enabled in your lwipopts.h"
+#endif
+#if (MEM_USE_POOLS && !MEMP_USE_CUSTOM_POOLS)
+  #error "MEM_USE_POOLS requires custom pools (MEMP_USE_CUSTOM_POOLS) to be enabled in your lwipopts.h"
+#endif
+
+
+/* Compile-time checks for deprecated options.
+ */
+#ifdef MEMP_NUM_TCPIP_MSG
+  #error "MEMP_NUM_TCPIP_MSG option is deprecated. Remove it from your lwipopts.h."
+#endif
+#ifdef MEMP_NUM_API_MSG
+  #error "MEMP_NUM_API_MSG option is deprecated. Remove it from your lwipopts.h."
+#endif
+#ifdef TCP_REXMIT_DEBUG
+  #error "TCP_REXMIT_DEBUG option is deprecated. Remove it from your lwipopts.h."
+#endif
+#ifdef RAW_STATS
+  #error "RAW_STATS option is deprecated. Remove it from your lwipopts.h."
+#endif
+#ifdef ETHARP_QUEUE_FIRST
+  #error "ETHARP_QUEUE_FIRST option is deprecated. Remove it from your lwipopts.h."
+#endif
+#ifdef ETHARP_ALWAYS_INSERT
+  #error "ETHARP_ALWAYS_INSERT option is deprecated. Remove it from your lwipopts.h."
+#endif
+#if SO_REUSE
+/* I removed the lot since this was an ugly hack. It broke the raw-API.
+   It also came with many ugly goto's, Christiaan Simons. */
+  #error "SO_REUSE currently unavailable, this was a hack"
+#endif
+
+#ifdef LWIP_DEBUG
+static void
+lwip_sanity_check(void)
+{
+  /* Warnings */
+#if LWIP_NETCONN
+  if (MEMP_NUM_NETCONN > (MEMP_NUM_TCP_PCB+MEMP_NUM_TCP_PCB_LISTEN+MEMP_NUM_UDP_PCB+MEMP_NUM_RAW_PCB))
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: MEMP_NUM_NETCONN should be less than the sum of MEMP_NUM_{TCP,RAW,UDP}_PCB+MEMP_NUM_TCP_PCB_LISTEN\n"));
+#endif /* LWIP_NETCONN */
+#if LWIP_TCP
+  if (MEMP_NUM_TCP_SEG < TCP_SND_QUEUELEN)
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: MEMP_NUM_TCP_SEG should be at least as big as TCP_SND_QUEUELEN\n"));
+  if (TCP_SND_QUEUELEN < (2 * (TCP_SND_BUF/TCP_MSS)))
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_SND_QUEUELEN must be at least as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work\n"));
+  if (TCP_SNDLOWAT > TCP_SND_BUF)
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_SNDLOWAT must be less than or equal to TCP_SND_BUF.\n"));
+  if (TCP_WND > (PBUF_POOL_SIZE*PBUF_POOL_BUFSIZE))
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_WND is larger than space provided by PBUF_POOL_SIZE*PBUF_POOL_BUFSIZE\n"));
+  if (TCP_WND < TCP_MSS)
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_WND is smaller than MSS\n"));
+#endif /* LWIP_TCP */
+}
+#else  /* LWIP_DEBUG */
+#define lwip_sanity_check()
+#endif /* LWIP_DEBUG */
+
+/**
+ * Perform Sanity check of user-configurable values, and initialize all modules.
+ */
+void
+lwip_init(void)
+{
+  /* Sanity check user-configurable values */
+  lwip_sanity_check();
+
+  /* Modules initialization */
+  stats_init();
+  sys_init();
+  mem_init();
+  memp_init();
+  pbuf_init();
+  netif_init();
+#if LWIP_SOCKET
+  lwip_socket_init();
+#endif /* LWIP_SOCKET */
+  ip_init();
+#if LWIP_ARP
+  etharp_init();
+#endif /* LWIP_ARP */
+#if LWIP_RAW
+  raw_init();
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+  udp_init();
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+  tcp_init();
+#endif /* LWIP_TCP */
+#if LWIP_AUTOIP
+  autoip_init();
+#endif /* LWIP_AUTOIP */
+#if LWIP_IGMP
+  igmp_init();
+#endif /* LWIP_IGMP */
+#if LWIP_DNS
+  dns_init();
+#endif /* LWIP_DNS */
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/autoip.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/autoip.c
new file mode 100644
index 0000000..e7fd48e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/autoip.c
@@ -0,0 +1,432 @@
+/**
+ * @file
+ * AutoIP Automatic LinkLocal IP Configuration
+ *
+ */
+
+/*
+ *
+ * Copyright (c) 2007 Dominik Spies 
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Dominik Spies 
+ *
+ * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform
+ * with RFC 3927.
+ *
+ *
+ * Please coordinate changes and requests with Dominik Spies
+ * 
+ */
+
+/*******************************************************************************
+ * USAGE:
+ * 
+ * define LWIP_AUTOIP 1  in your lwipopts.h
+ * 
+ * If you don't use tcpip.c (so, don't call, you don't call tcpip_init):
+ * - First, call autoip_init().
+ * - call autoip_tmr() all AUTOIP_TMR_INTERVAL msces,
+ *   that should be defined in autoip.h.
+ *   I recommend a value of 100. The value must divide 1000 with a remainder almost 0.
+ *   Possible values are 1000, 500, 333, 250, 200, 166, 142, 125, 111, 100 ....
+ *
+ * Without DHCP:
+ * - Call autoip_start() after netif_add().
+ * 
+ * With DHCP:
+ * - define LWIP_DHCP_AUTOIP_COOP 1 in your lwipopts.h.
+ * - Configure your DHCP Client.
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_AUTOIP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/mem.h"
+#include "lwip/udp.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/autoip.h"
+#include "netif/etharp.h"
+
+#include 
+#include 
+
+/* Pseudo random macro based on netif informations.
+ * You could use "rand()" from the C Library if you define LWIP_AUTOIP_RAND in lwipopts.h */
+#ifndef LWIP_AUTOIP_RAND
+#define LWIP_AUTOIP_RAND(netif) ( (((u32_t)((netif->hwaddr[5]) & 0xff) << 24) | \
+                                   ((u32_t)((netif->hwaddr[3]) & 0xff) << 16) | \
+                                   ((u32_t)((netif->hwaddr[2]) & 0xff) << 8) | \
+                                   ((u32_t)((netif->hwaddr[4]) & 0xff))) + \
+                                   (netif->autoip?netif->autoip->tried_llipaddr:0))
+#endif /* LWIP_AUTOIP_RAND */
+
+/* static functions */
+static void autoip_handle_arp_conflict(struct netif *netif);
+
+/* creates random LL IP-Address for a network interface */
+static void autoip_create_rand_addr(struct netif *netif, struct ip_addr *RandomIPAddr);
+
+/* sends an ARP announce */
+static err_t autoip_arp_announce(struct netif *netif);
+
+/* configure interface for use with current LL IP-Address */
+static err_t autoip_bind(struct netif *netif);
+
+/**
+ * Initialize this module
+ */
+void
+autoip_init(void)
+{
+  LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | 3, ("autoip_init()\n"));
+}
+
+/**
+ * Handle a IP address conflict after an ARP conflict detection
+ */
+static void
+autoip_handle_arp_conflict(struct netif *netif)
+{
+  /* Somehow detect if we are defending or retreating */
+  unsigned char defend = 1; /* tbd */
+
+  if(defend) {
+    if(netif->autoip->lastconflict > 0) {
+      /* retreat, there was a conflicting ARP in the last
+       * DEFEND_INTERVAL seconds
+       */
+      LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | 1,
+        ("autoip_handle_arp_conflict(): we are defending, but in DEFEND_INTERVAL, retreating\n"));
+
+      /* TODO: close all TCP sessions */
+      autoip_start(netif);
+    } else {
+      LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | 1,
+        ("autoip_handle_arp_conflict(): we are defend, send ARP Announce\n"));
+      autoip_arp_announce(netif);
+      netif->autoip->lastconflict = DEFEND_INTERVAL * AUTOIP_TICKS_PER_SECOND;
+    }
+  } else {
+    LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | 1,
+      ("autoip_handle_arp_conflict(): we do not defend, retreating\n"));
+    /* TODO: close all TCP sessions */
+    autoip_start(netif);
+  }
+}
+
+/**
+ * Create an IP-Address out of range 169.254.1.0 to 169.254.254.255
+ *
+ * @param netif network interface on which create the IP-Address
+ * @param RandomIPAddr ip address to initialize
+ */
+static void
+autoip_create_rand_addr(struct netif *netif, struct ip_addr *RandomIPAddr)
+{
+  /* Here we create an IP-Address out of range 169.254.1.0 to 169.254.254.255
+   * compliant to RFC 3927 Section 2.1
+   * We have 254 * 256 possibilities
+   */
+  
+  RandomIPAddr->addr = (0xA9FE0100 + ((u32_t)(((u8_t)(netif->hwaddr[4])) |
+    ((u32_t)((u8_t)(netif->hwaddr[5]))) << 8)) + netif->autoip->tried_llipaddr);
+
+  if (RandomIPAddr->addr>0xA9FEFEFF) {
+    RandomIPAddr->addr = (0xA9FE0100 + (RandomIPAddr->addr-0xA9FEFEFF));
+  }
+  if (RandomIPAddr->addr<0xA9FE0100) {
+    RandomIPAddr->addr = (0xA9FEFEFF - (0xA9FE0100-RandomIPAddr->addr));
+  }
+  RandomIPAddr->addr = htonl(RandomIPAddr->addr);
+  
+  LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | 1,
+    ("autoip_create_rand_addr(): tried_llipaddr=%"U16_F", 0x%08"X32_F"\n",
+    (u16_t)(netif->autoip->tried_llipaddr), (u32_t)(RandomIPAddr->addr)));
+}
+
+/**
+ * Sends an ARP announce from a network interface
+ *
+ * @param netif network interface used to send the announce
+ */
+static err_t
+autoip_arp_announce(struct netif *netif)
+{
+  return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, ðbroadcast,
+    (struct eth_addr *)netif->hwaddr, &netif->autoip->llipaddr, ðzero,
+    &netif->autoip->llipaddr, ARP_REQUEST);
+}
+
+/**
+ * Configure interface for use with current LL IP-Address
+ *
+ * @param netif network interface to configure with current LL IP-Address
+ */
+static err_t
+autoip_bind(struct netif *netif)
+{
+  struct autoip *autoip = netif->autoip;
+  struct ip_addr sn_mask, gw_addr;
+
+  LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | 3,
+    ("autoip_bind(netif=%p) %c%c%"U16_F" 0x%08"X32_F"\n",
+    (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num, autoip->llipaddr.addr));
+
+  IP4_ADDR(&sn_mask, 255, 255, 0, 0);
+  IP4_ADDR(&gw_addr, 0, 0, 0, 0);
+
+  netif_set_ipaddr(netif, &autoip->llipaddr);
+  netif_set_netmask(netif, &sn_mask);
+  netif_set_gw(netif, &gw_addr);  
+
+  /* bring the interface up */
+  netif_set_up(netif);
+
+  return ERR_OK;
+}
+
+/**
+ * Start AutoIP client
+ *
+ * @param netif network interface on which start the AutoIP client
+ */
+err_t
+autoip_start(struct netif *netif)
+{
+  struct autoip *autoip = netif->autoip;
+  err_t result = ERR_OK;
+
+  if(netif_is_up(netif)) {
+    netif_set_down(netif);
+  }
+
+  /* Set IP-Address, Netmask and Gateway to 0 to make sure that
+   * ARP Packets are formed correctly
+   */
+  netif->ip_addr.addr = 0;
+  netif->netmask.addr = 0;
+  netif->gw.addr      = 0;
+
+  LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+    ("autoip_start(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0],
+    netif->name[1], (u16_t)netif->num));
+  if(autoip == NULL) {
+    /* no AutoIP client attached yet? */
+    LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE,
+      ("autoip_start(): starting new AUTOIP client\n"));
+    autoip = mem_malloc(sizeof(struct autoip));
+    if(autoip == NULL) {
+      LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE,
+        ("autoip_start(): could not allocate autoip\n"));
+      return ERR_MEM;
+    }
+    memset( autoip, 0, sizeof(struct autoip));
+    /* store this AutoIP client in the netif */
+    netif->autoip = autoip;
+    LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, ("autoip_start(): allocated autoip"));
+  } else {
+    autoip->state = AUTOIP_STATE_OFF;
+    autoip->ttw = 0;
+    autoip->sent_num = 0;
+    memset(&autoip->llipaddr, 0, sizeof(struct ip_addr));
+    autoip->lastconflict = 0;
+  }
+
+  autoip_create_rand_addr(netif, &(autoip->llipaddr));
+  autoip->tried_llipaddr++;
+  autoip->state = AUTOIP_STATE_PROBING;
+  autoip->sent_num = 0;
+
+  /* time to wait to first probe, this is randomly
+   * choosen out of 0 to PROBE_WAIT seconds.
+   * compliant to RFC 3927 Section 2.2.1
+   */
+  autoip->ttw = (u16_t)(LWIP_AUTOIP_RAND(netif) % (PROBE_WAIT * AUTOIP_TICKS_PER_SECOND));
+
+  /*
+   * if we tried more then MAX_CONFLICTS we must limit our rate for
+   * accquiring and probing address
+   * compliant to RFC 3927 Section 2.2.1
+   */
+
+  if(autoip->tried_llipaddr > MAX_CONFLICTS) {
+    autoip->ttw = RATE_LIMIT_INTERVAL * AUTOIP_TICKS_PER_SECOND;
+  }
+
+  return result;
+}
+
+/**
+ * Stop AutoIP client
+ *
+ * @param netif network interface on which stop the AutoIP client
+ */
+err_t
+autoip_stop(struct netif *netif)
+{
+  netif->autoip->state = AUTOIP_STATE_OFF;
+  netif_set_down(netif);
+  return ERR_OK;
+}
+
+/**
+ * Has to be called in loop every AUTOIP_TMR_INTERVAL milliseconds
+ */
+void
+autoip_tmr()
+{
+  struct netif *netif = netif_list;
+  /* loop through netif's */
+  while (netif != NULL) {
+    /* only act on AutoIP configured interfaces */
+    if (netif->autoip != NULL) {
+      if(netif->autoip->lastconflict > 0) {
+        netif->autoip->lastconflict--;
+      }
+
+      LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE,
+        ("autoip_tmr() AutoIP-State: %"U16_F", ttw=%"U16_F"\n",
+        (u16_t)(netif->autoip->state), netif->autoip->ttw));
+
+      switch(netif->autoip->state) {
+        case AUTOIP_STATE_PROBING:
+          if(netif->autoip->ttw > 0) {
+            netif->autoip->ttw--;
+          } else {
+            if(netif->autoip->sent_num == PROBE_NUM) {
+              netif->autoip->state = AUTOIP_STATE_ANNOUNCING;
+              netif->autoip->sent_num = 0;
+              netif->autoip->ttw = ANNOUNCE_WAIT * AUTOIP_TICKS_PER_SECOND;
+            } else {
+              etharp_request(netif, &(netif->autoip->llipaddr));
+              LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | 3,
+                ("autoip_tmr() PROBING Sent Probe\n"));
+              netif->autoip->sent_num++;
+              /* calculate time to wait to next probe */
+              netif->autoip->ttw = (u16_t)((LWIP_AUTOIP_RAND(netif) %
+                ((PROBE_MAX - PROBE_MIN) * AUTOIP_TICKS_PER_SECOND) ) +
+                PROBE_MIN * AUTOIP_TICKS_PER_SECOND);
+            }
+          }
+          break;
+
+        case AUTOIP_STATE_ANNOUNCING:
+          if(netif->autoip->ttw > 0) {
+            netif->autoip->ttw--;
+          } else {
+            if(netif->autoip->sent_num == 0) {
+             /* We are here the first time, so we waited ANNOUNCE_WAIT seconds
+              * Now we can bind to an IP address and use it
+              */
+              autoip_bind(netif);
+            }
+
+            if(netif->autoip->sent_num == ANNOUNCE_NUM) {
+              netif->autoip->state = AUTOIP_STATE_BOUND;
+              netif->autoip->sent_num = 0;
+              netif->autoip->ttw = 0;
+            } else {
+              autoip_arp_announce(netif);
+              LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | 3,
+                ("autoip_tmr() ANNOUNCING Sent Announce\n"));
+              netif->autoip->sent_num++;
+              netif->autoip->ttw = ANNOUNCE_INTERVAL * AUTOIP_TICKS_PER_SECOND;
+            }
+          }
+          break;
+      }
+    }
+    /* proceed to next network interface */
+    netif = netif->next;
+  }
+}
+
+/**
+ * Handles every incoming ARP Packet, called by etharp_arp_input.
+ *
+ * @param netif network interface to use for autoip processing
+ * @param hdr Incoming ARP packet
+ */
+void
+autoip_arp_reply(struct netif *netif, struct etharp_hdr *hdr)
+{
+  LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | 3, ("autoip_arp_reply()\n"));
+  if ((netif->autoip != NULL) && (netif->autoip->state != AUTOIP_STATE_OFF)) {
+   /* when ip.src == llipaddr && hw.src != netif->hwaddr
+    *
+    * when probing  ip.dst == llipaddr && hw.src != netif->hwaddr
+    * we have a conflict and must solve it
+    */
+    struct ip_addr sipaddr, dipaddr;
+    struct eth_addr netifaddr;
+    netifaddr.addr[0] = netif->hwaddr[0];
+    netifaddr.addr[1] = netif->hwaddr[1];
+    netifaddr.addr[2] = netif->hwaddr[2];
+    netifaddr.addr[3] = netif->hwaddr[3];
+    netifaddr.addr[4] = netif->hwaddr[4];
+    netifaddr.addr[5] = netif->hwaddr[5];
+
+    /* Copy struct ip_addr2 to aligned ip_addr, to support compilers without
+     * structure packing (not using structure copy which breaks strict-aliasing rules).
+     */
+    MEMCPY(&sipaddr, &hdr->sipaddr, sizeof(sipaddr));
+    MEMCPY(&dipaddr, &hdr->dipaddr, sizeof(dipaddr));
+      
+    if ((netif->autoip->state == AUTOIP_STATE_PROBING) ||
+        ((netif->autoip->state == AUTOIP_STATE_ANNOUNCING) &&
+         (netif->autoip->sent_num == 0))) {
+     /* RFC 3927 Section 2.2.1:
+      * from beginning to after ANNOUNCE_WAIT
+      * seconds we have a conflict if
+      * ip.src == llipaddr OR
+      * ip.dst == llipaddr && hw.src != own hwaddr
+      */
+      if ((ip_addr_cmp(&sipaddr, &netif->autoip->llipaddr)) ||
+          (ip_addr_cmp(&dipaddr, &netif->autoip->llipaddr) &&
+           !eth_addr_cmp(&netifaddr, &hdr->shwaddr))) {
+        LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | 1,
+          ("autoip_arp_reply(): Probe Conflict detected\n"));
+        autoip_start(netif);
+      }
+    } else {
+     /* RFC 3927 Section 2.5:
+      * in any state we have a conflict if
+      * ip.src == llipaddr && hw.src != own hwaddr
+      */
+      if (ip_addr_cmp(&sipaddr, &netif->autoip->llipaddr) &&
+          !eth_addr_cmp(&netifaddr, &hdr->shwaddr)) {
+        LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | 1,
+          ("autoip_arp_reply(): Conflicting ARP-Packet detected\n"));
+        autoip_handle_arp_conflict(netif);
+      }
+    }
+  }
+}
+
+#endif /* LWIP_AUTOIP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/icmp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/icmp.c
new file mode 100644
index 0000000..aca1e5e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/icmp.c
@@ -0,0 +1,317 @@
+/**
+ * @file
+ * ICMP - Internet Control Message Protocol
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* Some ICMP messages should be passed to the transport protocols. This
+   is not implemented. */
+
+#include "lwip/opt.h"
+
+#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/icmp.h"
+#include "lwip/inet.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/ip.h"
+#include "lwip/def.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+
+#include 
+
+/* The amount of data from the original packet to return in a dest-unreachable */
+#define ICMP_DEST_UNREACH_DATASIZE 8
+
+/**
+ * Processes ICMP input packets, called from ip_input().
+ *
+ * Currently only processes icmp echo requests and sends
+ * out the echo response.
+ *
+ * @param p the icmp echo request packet, p->payload pointing to the ip header
+ * @param inp the netif on which this packet was received
+ */
+void
+icmp_input(struct pbuf *p, struct netif *inp)
+{
+  u8_t type;
+#ifdef LWIP_DEBUG
+  u8_t code;
+#endif /* LWIP_DEBUG */
+  struct icmp_echo_hdr *iecho;
+  struct ip_hdr *iphdr;
+  struct ip_addr tmpaddr;
+  s16_t hlen;
+
+  ICMP_STATS_INC(icmp.recv);
+  snmp_inc_icmpinmsgs();
+
+
+  iphdr = p->payload;
+  hlen = IPH_HL(iphdr) * 4;
+  if (pbuf_header(p, -hlen) || (p->tot_len < sizeof(u16_t)*2)) {
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len));
+    goto lenerr;
+  }
+
+  type = *((u8_t *)p->payload);
+#ifdef LWIP_DEBUG
+  code = *(((u8_t *)p->payload)+1);
+#endif /* LWIP_DEBUG */
+  switch (type) {
+  case ICMP_ECHO:
+    /* broadcast or multicast destination address? */
+    if (ip_addr_isbroadcast(&iphdr->dest, inp) || ip_addr_ismulticast(&iphdr->dest)) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast or broadcast pings\n"));
+      ICMP_STATS_INC(icmp.err);
+      pbuf_free(p);
+      return;
+    }
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
+    if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n"));
+      goto lenerr;
+    }
+    if (inet_chksum_pbuf(p) != 0) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n"));
+      pbuf_free(p);
+      ICMP_STATS_INC(icmp.chkerr);
+      snmp_inc_icmpinerrors();
+      return;
+    }
+    if (pbuf_header(p, (PBUF_IP_HLEN + PBUF_LINK_HLEN))) {
+      /* p is not big enough to contain link headers
+       * allocate a new one and copy p into it
+       */
+      struct pbuf *r;
+      /* switch p->payload to ip header */
+      if (pbuf_header(p, hlen)) {
+        LWIP_ASSERT("icmp_input: moving p->payload to ip header failed\n", 0);
+        goto memerr;
+      }
+      /* allocate new packet buffer with space for link headers */
+      r = pbuf_alloc(PBUF_LINK, p->tot_len, PBUF_RAM);
+      if (r == NULL) {
+        LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed\n"));
+        goto memerr;
+      }
+      LWIP_ASSERT("check that first pbuf can hold struct the ICMP header",
+                  (r->len >= hlen + sizeof(struct icmp_echo_hdr)));
+      /* copy the whole packet including ip header */
+      if (pbuf_copy(r, p) != ERR_OK) {
+        LWIP_ASSERT("icmp_input: copying to new pbuf failed\n", 0);
+        goto memerr;
+      }
+      iphdr = r->payload;
+      /* switch r->payload back to icmp header */
+      if (pbuf_header(r, -hlen)) {
+        LWIP_ASSERT("icmp_input: restoring original p->payload failed\n", 0);
+        goto memerr;
+      }
+      /* free the original p */
+      pbuf_free(p);
+      /* we now have an identical copy of p that has room for link headers */
+      p = r;
+    } else {
+      /* restore p->payload to point to icmp header */
+      if (pbuf_header(p, -(s16_t)(PBUF_IP_HLEN + PBUF_LINK_HLEN))) {
+        LWIP_ASSERT("icmp_input: restoring original p->payload failed\n", 0);
+        goto memerr;
+      }
+    }
+    /* At this point, all checks are OK. */
+    /* We generate an answer by switching the dest and src ip addresses,
+     * setting the icmp type to ECHO_RESPONSE and updating the checksum. */
+    iecho = p->payload;
+    tmpaddr.addr = iphdr->src.addr;
+    iphdr->src.addr = iphdr->dest.addr;
+    iphdr->dest.addr = tmpaddr.addr;
+    ICMPH_TYPE_SET(iecho, ICMP_ER);
+    /* adjust the checksum */
+    if (iecho->chksum >= htons(0xffff - (ICMP_ECHO << 8))) {
+      iecho->chksum += htons(ICMP_ECHO << 8) + 1;
+    } else {
+      iecho->chksum += htons(ICMP_ECHO << 8);
+    }
+
+    /* Set the correct TTL and recalculate the header checksum. */
+    IPH_TTL_SET(iphdr, ICMP_TTL);
+    IPH_CHKSUM_SET(iphdr, 0);
+#if CHECKSUM_GEN_IP
+    IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
+#endif /* CHECKSUM_GEN_IP */
+
+    ICMP_STATS_INC(icmp.xmit);
+    /* increase number of messages attempted to send */
+    snmp_inc_icmpoutmsgs();
+    /* increase number of echo replies attempted to send */
+    snmp_inc_icmpoutechoreps();
+
+    if(pbuf_header(p, hlen)) {
+      LWIP_ASSERT("Can't move over header in packet", 0);
+    } else {
+      err_t ret;
+      ret = ip_output_if(p, &(iphdr->src), IP_HDRINCL,
+                   ICMP_TTL, 0, IP_PROTO_ICMP, inp);
+      if (ret != ERR_OK) {
+        LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ip_output_if returned an error: %c.\n", ret));
+      }
+    }
+    break;
+  default:
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n",
+                (s16_t)type, (s16_t)code));
+    ICMP_STATS_INC(icmp.proterr);
+    ICMP_STATS_INC(icmp.drop);
+  }
+  pbuf_free(p);
+  return;
+lenerr:
+  pbuf_free(p);
+  ICMP_STATS_INC(icmp.lenerr);
+  snmp_inc_icmpinerrors();
+  return;
+memerr:
+  pbuf_free(p);
+  ICMP_STATS_INC(icmp.err);
+  snmp_inc_icmpinerrors();
+  return;
+}
+
+/**
+ * Send an icmp 'destination unreachable' packet, called from ip_input() if
+ * the transport layer protocol is unknown and from udp_input() if the local
+ * port is not bound.
+ *
+ * @param p the input packet for which the 'unreachable' should be sent,
+ *          p->payload pointing to the IP header
+ * @param t type of the 'unreachable' packet
+ */
+void
+icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  struct icmp_dur_hdr *idur;
+
+  /* ICMP header + IP header + 8 bytes of data */
+  q = pbuf_alloc(PBUF_IP, sizeof(struct icmp_dur_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE,
+                 PBUF_RAM);
+  if (q == NULL) {
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_dest_unreach: failed to allocate pbuf for ICMP packet.\n"));
+    return;
+  }
+  LWIP_ASSERT("check that first pbuf can hold icmp message",
+             (q->len >= (sizeof(struct icmp_dur_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE)));
+
+  iphdr = p->payload;
+
+  idur = q->payload;
+  ICMPH_TYPE_SET(idur, ICMP_DUR);
+  ICMPH_CODE_SET(idur, t);
+
+  SMEMCPY((u8_t *)q->payload + sizeof(struct icmp_dur_hdr), p->payload,
+          IP_HLEN + ICMP_DEST_UNREACH_DATASIZE);
+
+  /* calculate checksum */
+  idur->chksum = 0;
+  idur->chksum = inet_chksum(idur, q->len);
+  ICMP_STATS_INC(icmp.xmit);
+  /* increase number of messages attempted to send */
+  snmp_inc_icmpoutmsgs();
+  /* increase number of destination unreachable messages attempted to send */
+  snmp_inc_icmpoutdestunreachs();
+
+  ip_output(q, NULL, &(iphdr->src), ICMP_TTL, 0, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+#if IP_FORWARD || IP_REASSEMBLY
+/**
+ * Send a 'time exceeded' packet, called from ip_forward() if TTL is 0.
+ *
+ * @param p the input packet for which the 'time exceeded' should be sent,
+ *          p->payload pointing to the IP header
+ * @param t type of the 'time exceeded' packet
+ */
+void
+icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  struct icmp_te_hdr *tehdr;
+
+  /* ICMP header + IP header + 8 bytes of data */
+  q = pbuf_alloc(PBUF_IP, sizeof(struct icmp_dur_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE,
+                 PBUF_RAM);
+  if (q == NULL) {
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded: failed to allocate pbuf for ICMP packet.\n"));
+    return;
+  }
+  LWIP_ASSERT("check that first pbuf can hold icmp message",
+             (q->len >= (sizeof(struct icmp_dur_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE)));
+
+  iphdr = p->payload;
+  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded from "));
+  ip_addr_debug_print(ICMP_DEBUG, &(iphdr->src));
+  LWIP_DEBUGF(ICMP_DEBUG, (" to "));
+  ip_addr_debug_print(ICMP_DEBUG, &(iphdr->dest));
+  LWIP_DEBUGF(ICMP_DEBUG, ("\n"));
+
+  tehdr = q->payload;
+  ICMPH_TYPE_SET(tehdr, ICMP_TE);
+  ICMPH_CODE_SET(tehdr, t);
+
+  /* copy fields from original packet */
+  SMEMCPY((u8_t *)q->payload + sizeof(struct icmp_dur_hdr), (u8_t *)p->payload,
+          IP_HLEN + ICMP_DEST_UNREACH_DATASIZE);
+
+  /* calculate checksum */
+  tehdr->chksum = 0;
+  tehdr->chksum = inet_chksum(tehdr, q->len);
+  ICMP_STATS_INC(icmp.xmit);
+  /* increase number of messages attempted to send */
+  snmp_inc_icmpoutmsgs();
+  /* increase number of destination unreachable messages attempted to send */
+  snmp_inc_icmpouttimeexcds();
+  ip_output(q, NULL, &(iphdr->src), ICMP_TTL, 0, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+#endif /* IP_FORWARD */
+
+#endif /* LWIP_ICMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/igmp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/igmp.c
new file mode 100644
index 0000000..13144b6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/igmp.c
@@ -0,0 +1,808 @@
+/**
+ * @file
+ * IGMP - Internet Group Management Protocol
+ *
+ */
+
+/*
+ * Copyright (c) 2002 CITEL Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS''
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is a contribution to the lwIP TCP/IP stack.
+ * The Swedish Institute of Computer Science and Adam Dunkels
+ * are specifically granted permission to redistribute this
+ * source code.
+*/
+
+/*-------------------------------------------------------------
+Note 1)
+Although the rfc requires V1 AND V2 capability
+we will only support v2 since now V1 is very old (August 1989)
+V1 can be added if required
+
+a debug print and statistic have been implemented to
+show this up.
+-------------------------------------------------------------
+-------------------------------------------------------------
+Note 2)
+A query for a specific group address (as opposed to ALLHOSTS)
+has now been implemented as I am unsure if it is required
+
+a debug print and statistic have been implemented to
+show this up.
+-------------------------------------------------------------
+-------------------------------------------------------------
+Note 3)
+The router alert rfc 2113 is implemented in outgoing packets
+but not checked rigorously incoming
+-------------------------------------------------------------
+Steve Reynolds
+------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------------
+ * RFC 988  - Host extensions for IP multicasting                         - V0
+ * RFC 1054 - Host extensions for IP multicasting                         -
+ * RFC 1112 - Host extensions for IP multicasting                         - V1
+ * RFC 2236 - Internet Group Management Protocol, Version 2               - V2  <- this code is based on this RFC (it's the "de facto" standard)
+ * RFC 3376 - Internet Group Management Protocol, Version 3               - V3
+ * RFC 4604 - Using Internet Group Management Protocol Version 3...       - V3+
+ * RFC 2113 - IP Router Alert Option                                      - 
+ *----------------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------------
+ * Includes
+ *----------------------------------------------------------------------------*/
+
+#include "lwip/opt.h"
+
+#if LWIP_IGMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/igmp.h"
+#include "lwip/debug.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/ip.h"
+#include "lwip/inet.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/netif.h"
+#include "lwip/icmp.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+#include "lwip/stats.h"
+
+#include "string.h"
+
+/*-----------------------------------------------------------------------------
+ * Globales
+ *----------------------------------------------------------------------------*/
+
+static struct igmp_group* igmp_group_list;
+static struct ip_addr     allsystems;
+static struct ip_addr     allrouters;
+
+/**
+ * Initialize the IGMP module
+ */
+void
+igmp_init(void)
+{
+  LWIP_DEBUGF(IGMP_DEBUG, ("igmp_init: initializing\n"));
+
+  IP4_ADDR(&allsystems, 224, 0, 0, 1);
+  IP4_ADDR(&allrouters, 224, 0, 0, 2);
+}
+
+#ifdef LWIP_DEBUG
+/**
+ * Dump global IGMP groups list
+ */
+void
+igmp_dump_group_list()
+{ 
+  struct igmp_group *group = igmp_group_list;
+
+  while (group != NULL) {
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_dump_group_list: [%"U32_F"] ", (u32_t)(group->group_state)));
+    ip_addr_debug_print(IGMP_DEBUG, &group->group_address);
+    LWIP_DEBUGF(IGMP_DEBUG, (" on if %x\n", (int) group->interface));
+    group = group->next;
+  }
+  LWIP_DEBUGF(IGMP_DEBUG, ("\n"));
+}
+#else
+#define igmp_dump_group_list()
+#endif /* LWIP_DEBUG */
+
+/**
+ * Start IGMP processing on interface
+ *
+ * @param netif network interface on which start IGMP processing
+ */
+err_t
+igmp_start(struct netif *netif)
+{
+  struct igmp_group* group;
+
+  LWIP_DEBUGF(IGMP_DEBUG, ("igmp_start: starting IGMP processing on if %x\n", (int) netif));
+
+  group = igmp_lookup_group(netif, &allsystems);
+
+  if (group != NULL) {
+    group->group_state = IGMP_GROUP_IDLE_MEMBER;
+    group->use++;
+
+    /* Allow the igmp messages at the MAC level */
+    if (netif->igmp_mac_filter != NULL) {
+      LWIP_DEBUGF(IGMP_DEBUG, ("igmp_start: igmp_mac_filter(ADD "));
+      ip_addr_debug_print(IGMP_DEBUG, &allsystems);
+      LWIP_DEBUGF(IGMP_DEBUG, (") on if %x\n", (int) netif));
+      netif->igmp_mac_filter( netif, &allsystems, IGMP_ADD_MAC_FILTER);
+    }
+
+    return ERR_OK;
+  }
+
+  return ERR_MEM;
+}
+
+/**
+ * Stop IGMP processing on interface
+ *
+ * @param netif network interface on which stop IGMP processing
+ */
+err_t
+igmp_stop(struct netif *netif)
+{
+  struct igmp_group *group = igmp_group_list;
+  struct igmp_group *prev  = NULL;
+  struct igmp_group *next;
+
+  /* look for groups joined on this interface further down the list */
+  while (group != NULL) {
+    next = group->next;
+    /* is it a group joined on this interface? */
+    if (group->interface == netif) {
+      /* is it the first group of the list? */
+      if (group == igmp_group_list) {
+        igmp_group_list = next;
+      }
+      /* is there a "previous" group defined? */
+      if (prev != NULL) {
+        prev->next = next;
+      }
+      /* disable the group at the MAC level */
+      if (netif->igmp_mac_filter != NULL) {
+        LWIP_DEBUGF(IGMP_DEBUG, ("igmp_stop: igmp_mac_filter(DEL "));
+        ip_addr_debug_print(IGMP_DEBUG, &group->group_address);
+        LWIP_DEBUGF(IGMP_DEBUG, (") on if %x\n", (int) netif));
+        netif->igmp_mac_filter(netif, &(group->group_address), IGMP_DEL_MAC_FILTER);
+      }
+      /* free group */
+      memp_free(MEMP_IGMP_GROUP, group);
+    } else {
+      /* change the "previous" */
+      prev = group;
+    }
+    /* move to "next" */
+    group = next;
+  }
+  return ERR_OK;
+}
+
+/**
+ * Report IGMP memberships for this interface
+ *
+ * @param netif network interface on which report IGMP memberships
+ */
+void
+igmp_report_groups( struct netif *netif)
+{
+  struct igmp_group *group = igmp_group_list;
+
+  LWIP_DEBUGF(IGMP_DEBUG, ("igmp_report_groups: sending IGMP reports on if %x\n", (int) netif));
+
+  while (group != NULL) {
+    if (group->interface == netif) {
+      igmp_delaying_member( group, IGMP_JOIN_DELAYING_MEMBER_TMR);
+    }
+    group = group->next;
+  }
+}
+
+/**
+ * Search for a group in the global igmp_group_list
+ *
+ * @param ifp the network interface for which to look
+ * @param addr the group ip address to search for
+ * @return a struct igmp_group* if the group has been found,
+ *         NULL if the group wasn't found.
+ */
+struct igmp_group *
+igmp_lookfor_group(struct netif *ifp, struct ip_addr *addr)
+{
+  struct igmp_group *group = igmp_group_list;
+
+  while (group != NULL) {
+    if ((group->interface == ifp) && (ip_addr_cmp(&(group->group_address), addr))) {
+      return group;
+    }
+    group = group->next;
+  }
+
+  /* to be clearer, we return NULL here instead of
+   * 'group' (which is also NULL at this point).
+   */
+  return NULL;
+}
+
+/**
+ * Search for a specific igmp group and create a new one if not found-
+ *
+ * @param ifp the network interface for which to look
+ * @param addr the group ip address to search
+ * @return a struct igmp_group*,
+ *         NULL on memory error.
+ */
+struct igmp_group *
+igmp_lookup_group(struct netif *ifp, struct ip_addr *addr)
+{
+  struct igmp_group *group = igmp_group_list;
+  
+  /* Search if the group already exists */
+  group = igmp_lookfor_group(ifp, addr);
+  if (group != NULL) {
+    /* Group already exists. */
+    return group;
+  }
+
+  /* Group doesn't exist yet, create a new one */
+  group = memp_malloc(MEMP_IGMP_GROUP);
+  if (group != NULL) {
+    group->interface          = ifp;
+    ip_addr_set(&(group->group_address), addr);
+    group->timer              = 0; /* Not running */
+    group->group_state        = IGMP_GROUP_NON_MEMBER;
+    group->last_reporter_flag = 0;
+    group->use                = 0;
+    group->next               = igmp_group_list;
+    
+    igmp_group_list = group;
+  }
+
+  LWIP_DEBUGF(IGMP_DEBUG, ("igmp_lookup_group: %sallocated a new group with address ", (group?"":"impossible to ")));
+  ip_addr_debug_print(IGMP_DEBUG, addr);
+  LWIP_DEBUGF(IGMP_DEBUG, (" on if %x\n", (int) ifp));
+
+  return group;
+}
+
+/**
+ * Remove a group in the global igmp_group_list
+ *
+ * @param group the group to remove from the global igmp_group_list
+ * @return ERR_OK if group was removed from the list, an err_t otherwise
+ */
+err_t
+igmp_remove_group(struct igmp_group *group)
+{
+  err_t err = ERR_OK;
+
+  /* Is it the first group? */
+  if (igmp_group_list == group) {
+    igmp_group_list = group->next;
+  } else {
+    /* look for group further down the list */
+    struct igmp_group *tmpGroup;
+    for (tmpGroup = igmp_group_list; tmpGroup != NULL; tmpGroup = tmpGroup->next) {
+      if (tmpGroup->next == group) {
+        tmpGroup->next = group->next;
+        break;
+      }
+    }
+    /* Group not found in the global igmp_group_list */
+    if (tmpGroup == NULL)
+      err = ERR_ARG;
+  }
+  /* free group */
+  memp_free(MEMP_IGMP_GROUP, group);
+
+  return err;
+}
+
+/**
+ * Called from ip_input() if a new IGMP packet is received.
+ *
+ * @param p received igmp packet, p->payload pointing to the ip header
+ * @param inp network interface on which the packet was received
+ * @param dest destination ip address of the igmp packet
+ */
+void
+igmp_input(struct pbuf *p, struct netif *inp, struct ip_addr *dest)
+{
+  struct ip_hdr *    iphdr;
+  struct igmp_msg*   igmp;
+  struct igmp_group* group;
+  struct igmp_group* groupref;
+
+  /* Note that the length CAN be greater than 8 but only 8 are used - All are included in the checksum */    
+  iphdr = p->payload;
+  if (pbuf_header(p, -(s16_t)(IPH_HL(iphdr) * 4)) || (p->len < IGMP_MINLEN)) {
+    pbuf_free(p);
+    IGMP_STATS_INC(igmp.lenerr);
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: length error\n"));
+    return;
+  }
+
+  LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: message from "));
+  ip_addr_debug_print(IGMP_DEBUG, &(iphdr->src));
+  LWIP_DEBUGF(IGMP_DEBUG, (" to address "));
+  ip_addr_debug_print(IGMP_DEBUG, &(iphdr->dest));
+  LWIP_DEBUGF(IGMP_DEBUG, (" on if %x\n", (int) inp));
+
+  /* Now calculate and check the checksum */
+  igmp = (struct igmp_msg *)p->payload;
+  if (inet_chksum(igmp, p->len)) {
+    pbuf_free(p);
+    IGMP_STATS_INC(igmp.chkerr);
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: checksum error\n"));
+    return;
+  }
+
+  /* Packet is ok so find an existing group */
+  group = igmp_lookfor_group(inp, dest); /* use the incoming IP address! */
+  
+  /* If group can be found or create... */
+  if (!group) {
+    pbuf_free(p);
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP frame not for us\n"));
+    return;
+  }
+
+  /* NOW ACT ON THE INCOMING MESSAGE TYPE... */
+  switch (igmp->igmp_msgtype) {
+   case IGMP_MEMB_QUERY: {
+     /* IGMP_MEMB_QUERY to the "all systems" address ? */
+     if ((ip_addr_cmp(dest, &allsystems)) && (igmp->igmp_group_address.addr == 0)) {
+       /* THIS IS THE GENERAL QUERY */
+       LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: General IGMP_MEMB_QUERY on \"ALL SYSTEMS\" address (224.0.0.1) [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp)));
+
+       if (igmp->igmp_maxresp == 0) {
+         IGMP_STATS_INC(igmp.v1_rxed);
+         LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: got an all hosts query with time== 0 - this is V1 and not implemented - treat as v2\n"));
+         igmp->igmp_maxresp = IGMP_V1_DELAYING_MEMBER_TMR;
+       }
+
+       IGMP_STATS_INC(igmp.group_query_rxed);
+       groupref = igmp_group_list;
+       while (groupref) {
+         /* Do not send messages on the all systems group address! */
+         if ((groupref->interface == inp) && (!(ip_addr_cmp(&(groupref->group_address), &allsystems)))) {
+           igmp_delaying_member( groupref, igmp->igmp_maxresp);
+         }
+         groupref = groupref->next;
+       }
+     } else {
+       /* IGMP_MEMB_QUERY to a specific group ? */
+       if (group->group_address.addr != 0) {
+         LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP_MEMB_QUERY to a specific group "));
+         ip_addr_debug_print(IGMP_DEBUG, &group->group_address);
+         if (ip_addr_cmp (dest, &allsystems)) {
+           LWIP_DEBUGF(IGMP_DEBUG, (" using \"ALL SYSTEMS\" address (224.0.0.1) [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp)));
+           /* we first need to re-lookfor the group since we used dest last time */
+           group = igmp_lookfor_group(inp, &igmp->igmp_group_address);
+         } else {
+           LWIP_DEBUGF(IGMP_DEBUG, (" with the group address as destination [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp)));
+         }
+
+         if (group != NULL) {
+           IGMP_STATS_INC(igmp.unicast_query);
+           igmp_delaying_member( group, igmp->igmp_maxresp);
+         }
+       }
+     }
+     break;
+   }
+   case IGMP_V2_MEMB_REPORT: {
+     LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP_V2_MEMB_REPORT\n"));
+
+     IGMP_STATS_INC(igmp.report_rxed);
+     if (group->group_state == IGMP_GROUP_DELAYING_MEMBER) {
+       /* This is on a specific group we have already looked up */
+       group->timer = 0; /* stopped */
+       group->group_state = IGMP_GROUP_IDLE_MEMBER;
+       group->last_reporter_flag = 0;
+     }
+     break;
+   }
+   default: {
+     LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: unexpected msg %x in state %x on group %x on if %x\n", (int) igmp->igmp_msgtype, (int) group->group_state, (int) &group, (int) group->interface));
+     break;
+   }
+  }
+
+  pbuf_free(p);
+  return;
+}
+
+/**
+ * Join a group on one network interface.
+ *
+ * @param ifaddr ip address of the network interface which should join a new group
+ * @param groupaddr the ip address of the group which to join
+ * @return ERR_OK if group was joined on the netif(s), an err_t otherwise
+ */
+err_t
+igmp_joingroup(struct ip_addr *ifaddr, struct ip_addr *groupaddr)
+{
+  err_t              err = ERR_VAL; /* no matching interface */
+  struct igmp_group *group;
+  struct netif      *netif;
+
+  /* make sure it is multicast address */
+  LWIP_ERROR("igmp_joingroup: attempt to join non-multicast address", ip_addr_ismulticast(groupaddr), return ERR_VAL;);
+  LWIP_ERROR("igmp_joingroup: attempt to join allsystems address", (!ip_addr_cmp(groupaddr, &allsystems)), return ERR_VAL;);
+
+  /* loop through netif's */
+  netif = netif_list;
+  while (netif != NULL) {
+    /* Should we join this interface ? */
+    if ((netif->flags & NETIF_FLAG_IGMP) && ((ip_addr_isany(ifaddr) || ip_addr_cmp(&(netif->ip_addr), ifaddr)))) {
+      /* find group or create a new one if not found */
+      group = igmp_lookup_group(netif, groupaddr);
+
+      if (group != NULL) {
+        /* This should create a new group, check the state to make sure */
+        if (group->group_state != IGMP_GROUP_NON_MEMBER) {
+          LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup: join to group not in state IGMP_GROUP_NON_MEMBER\n"));
+        } else {
+          /* OK - it was new group */
+          LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup: join to new group: "));
+          ip_addr_debug_print(IGMP_DEBUG, groupaddr);
+          LWIP_DEBUGF(IGMP_DEBUG, ("\n"));
+
+          /* If first use of the group, allow the group at the MAC level */
+          if ((group->use==0) && (netif->igmp_mac_filter != NULL)) {
+            LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup: igmp_mac_filter(ADD "));
+            ip_addr_debug_print(IGMP_DEBUG, groupaddr);
+            LWIP_DEBUGF(IGMP_DEBUG, (") on if %x\n", (int) netif));
+            netif->igmp_mac_filter(netif, groupaddr, IGMP_ADD_MAC_FILTER);
+          }
+
+          IGMP_STATS_INC(igmp.join_sent);
+          igmp_send(group, IGMP_V2_MEMB_REPORT);
+
+          igmp_start_timer(group, IGMP_JOIN_DELAYING_MEMBER_TMR);
+
+          /* Need to work out where this timer comes from */
+          group->group_state = IGMP_GROUP_DELAYING_MEMBER;
+        }
+        /* Increment group use */
+        group->use++;
+        /* Join on this interface */
+        err = ERR_OK;
+      } else {
+        /* Return an error even if some network interfaces are joined */
+        /** @todo undo any other netif already joined */
+        LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup: Not enought memory to join to group\n"));
+        return ERR_MEM;
+      }
+    }
+    /* proceed to next network interface */
+    netif = netif->next;
+  }
+
+  return err;
+}
+
+/**
+ * Leave a group on one network interface.
+ *
+ * @param ifaddr ip address of the network interface which should leave a group
+ * @param groupaddr the ip address of the group which to leave
+ * @return ERR_OK if group was left on the netif(s), an err_t otherwise
+ */
+err_t
+igmp_leavegroup(struct ip_addr *ifaddr, struct ip_addr *groupaddr)
+{
+  err_t              err = ERR_VAL; /* no matching interface */
+  struct igmp_group *group;
+  struct netif      *netif;
+
+  /* make sure it is multicast address */
+  LWIP_ERROR("igmp_leavegroup: attempt to leave non-multicast address", ip_addr_ismulticast(groupaddr), return ERR_VAL;);
+  LWIP_ERROR("igmp_leavegroup: attempt to leave allsystems address", (!ip_addr_cmp(groupaddr, &allsystems)), return ERR_VAL;);
+
+  /* loop through netif's */
+  netif = netif_list;
+  while (netif != NULL) {
+    /* Should we leave this interface ? */
+    if ((netif->flags & NETIF_FLAG_IGMP) && ((ip_addr_isany(ifaddr) || ip_addr_cmp(&(netif->ip_addr), ifaddr)))) {
+      /* find group */
+      group = igmp_lookfor_group(netif, groupaddr);
+
+      if (group != NULL) {
+        /* Only send a leave if the flag is set according to the state diagram */
+        LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: Leaving group: "));
+        ip_addr_debug_print(IGMP_DEBUG, groupaddr);
+        LWIP_DEBUGF(IGMP_DEBUG, ("\n"));
+
+        /* If there is no other use of the group */
+        if (group->use <= 1) {
+          /* If we are the last reporter for this group */
+          if (group->last_reporter_flag) {
+            LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: sending leaving group\n"));
+            IGMP_STATS_INC(igmp.leave_sent);
+            igmp_send(group, IGMP_LEAVE_GROUP);
+          }
+          
+          /* Disable the group at the MAC level */
+          if (netif->igmp_mac_filter != NULL) {
+            LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: igmp_mac_filter(DEL "));
+            ip_addr_debug_print(IGMP_DEBUG, groupaddr);
+            LWIP_DEBUGF(IGMP_DEBUG, (") on if %x\n", (int) netif));
+            netif->igmp_mac_filter(netif, groupaddr, IGMP_DEL_MAC_FILTER);
+          }
+          
+          LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: remove group: "));
+          ip_addr_debug_print(IGMP_DEBUG, groupaddr);
+          LWIP_DEBUGF(IGMP_DEBUG, ("\n"));          
+          
+          /* Free the group */
+          igmp_remove_group(group);
+        } else {
+          /* Decrement group use */
+          group->use--;
+        }
+        /* Leave on this interface */
+        err = ERR_OK;
+      } else {
+        /* It's not a fatal error on "leavegroup" */
+        LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: not member of group\n"));
+      }
+    }
+    /* proceed to next network interface */
+    netif = netif->next;
+  }
+
+  return err;
+}
+
+/**
+ * The igmp timer function (both for NO_SYS=1 and =0)
+ * Should be called every IGMP_TMR_INTERVAL milliseconds (100 ms is default).
+ */
+void
+igmp_tmr(void)
+{
+  struct igmp_group *group = igmp_group_list;
+
+  while (group != NULL) {
+    if (group->timer != 0) {
+      group->timer -= 1;
+      if (group->timer == 0) {
+        igmp_timeout(group);
+      }
+    }
+    group = group->next;
+  }
+}
+
+/**
+ * Called if a timeout for one group is reached.
+ * Sends a report for this group.
+ *
+ * @param group an igmp_group for which a timeout is reached
+ */
+void
+igmp_timeout(struct igmp_group *group)
+{
+  /* If the state is IGMP_GROUP_DELAYING_MEMBER then we send a report for this group */
+  if (group->group_state == IGMP_GROUP_DELAYING_MEMBER) {
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_timeout: report membership for group with address "));
+    ip_addr_debug_print(IGMP_DEBUG, &(group->group_address));
+    LWIP_DEBUGF(IGMP_DEBUG, (" on if %x\n", (int) group->interface));
+
+    igmp_send(group, IGMP_V2_MEMB_REPORT);
+  }
+}
+
+/**
+ * Start a timer for an igmp group
+ *
+ * @param group the igmp_group for which to start a timer
+ * @param max_time the time in multiples of IGMP_TMR_INTERVAL (decrease with
+ *        every call to igmp_tmr())
+ */
+void
+igmp_start_timer(struct igmp_group *group, u8_t max_time)
+{
+  /**
+   * @todo Important !! this should be random 0 -> max_time. Find out how to do this
+   */
+  group->timer = max_time;
+}
+
+/**
+ * Stop a timer for an igmp_group
+ *
+ * @param group the igmp_group for which to stop the timer
+ */
+void
+igmp_stop_timer(struct igmp_group *group)
+{
+  group->timer = 0;
+}
+
+/**
+ * Delaying membership report for a group if necessary
+ *
+ * @param group the igmp_group for which "delaying" membership report
+ * @param maxresp query delay
+ */
+void
+igmp_delaying_member( struct igmp_group *group, u8_t maxresp)
+{
+  if ((group->group_state == IGMP_GROUP_IDLE_MEMBER) || ((group->group_state == IGMP_GROUP_DELAYING_MEMBER) && (maxresp > group->timer))) {
+    igmp_start_timer(group, (maxresp)/2);
+    group->group_state = IGMP_GROUP_DELAYING_MEMBER;
+  }
+}
+
+
+/**
+ * Sends an IP packet on a network interface. This function constructs the IP header
+ * and calculates the IP header checksum. If the source IP address is NULL,
+ * the IP address of the outgoing network interface is filled in as source address.
+ *
+ * @param p the packet to send (p->payload points to the data, e.g. next
+            protocol header; if dest == IP_HDRINCL, p already includes an IP
+            header and p->payload points to that IP header)
+ * @param src the source IP address to send from (if src == IP_ADDR_ANY, the
+ *         IP  address of the netif used to send is used as source address)
+ * @param dest the destination IP address to send the packet to
+ * @param ttl the TTL value to be set in the IP header
+ * @param proto the PROTOCOL to be set in the IP header
+ * @param netif the netif on which to send this packet
+ * @return ERR_OK if the packet was sent OK
+ *         ERR_BUF if p doesn't have enough space for IP/LINK headers
+ *         returns errors returned by netif->output
+ */
+err_t
+igmp_ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+                  u8_t ttl, u8_t proto, struct netif *netif)
+{
+  static u16_t    ip_id = 0;
+  struct ip_hdr * iphdr = NULL;
+  u16_t *         ra    = NULL;
+
+  /* First write in the "router alert" */
+  if (pbuf_header(p, ROUTER_ALERTLEN)) {
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_ip_output_if: not enough room for IP header in pbuf\n"));
+    return ERR_BUF;
+  }
+
+  /* This is the "router alert" option */
+  ra    = p->payload;
+  ra[0] = htons (ROUTER_ALERT);
+  ra[1] = 0x0000; /* Router shall examine packet */
+
+  /* now the normal ip header */
+  if (pbuf_header(p, IP_HLEN)) {
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_ip_output_if: not enough room for IP header in pbuf\n"));
+    return ERR_BUF;
+  }
+
+  iphdr = p->payload;
+
+  /* Should the IP header be generated or is it already included in p? */
+  if (dest != IP_HDRINCL) {
+    /** @todo should be shared with ip.c - ip_output_if */
+    IPH_TTL_SET(iphdr, ttl);
+    IPH_PROTO_SET(iphdr, proto);
+
+    ip_addr_set(&(iphdr->dest), dest);
+
+    IPH_VHLTOS_SET(iphdr, 4, ((IP_HLEN + ROUTER_ALERTLEN) / 4), 0/*tos*/);
+    IPH_LEN_SET(iphdr, htons(p->tot_len));
+    IPH_OFFSET_SET(iphdr, 0);
+    IPH_ID_SET(iphdr, htons(ip_id));
+    ++ip_id;
+
+    if (ip_addr_isany(src)) {
+      ip_addr_set(&(iphdr->src), &(netif->ip_addr));
+    } else {
+      ip_addr_set(&(iphdr->src), src);
+    }
+
+    IPH_CHKSUM_SET(iphdr, 0);
+#if CHECKSUM_GEN_IP
+    IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, (IP_HLEN + ROUTER_ALERTLEN)));
+#endif
+  } else {
+    dest = &(iphdr->dest);
+  }
+
+#if IP_DEBUG
+  ip_debug_print(p);
+#endif
+
+  LWIP_DEBUGF(IGMP_DEBUG, ("igmp_ip_output_if: sending to if %x\n", (int) netif));
+
+  return netif->output(netif, p, dest);
+}
+
+/**
+ * Send an igmp packet to a specific group.
+ *
+ * @param group the group to which to send the packet
+ * @param type the type of igmp packet to send
+ */
+void
+igmp_send(struct igmp_group *group, u8_t type)
+{
+  struct pbuf*     p    = NULL;
+  struct igmp_msg* igmp = NULL;
+  struct ip_addr   src  = {0};
+  struct ip_addr*  dest = NULL;
+
+  /* IP header + "router alert" option + IGMP header */
+  p = pbuf_alloc(PBUF_TRANSPORT, IGMP_MINLEN, PBUF_RAM);
+  
+  if (p) {
+    igmp = p->payload;
+    LWIP_ASSERT("igmp_send: check that first pbuf can hold struct igmp_msg",
+               (p->len >= sizeof(struct igmp_msg)));
+    ip_addr_set(&src, &((group->interface)->ip_addr));
+     
+    if (type == IGMP_V2_MEMB_REPORT) {
+      dest = &(group->group_address);
+      IGMP_STATS_INC(igmp.report_sent);
+      ip_addr_set(&(igmp->igmp_group_address), &(group->group_address));
+      group->last_reporter_flag = 1; /* Remember we were the last to report */
+    } else {
+      if (type == IGMP_LEAVE_GROUP) {
+        dest = &allrouters;
+        ip_addr_set(&(igmp->igmp_group_address), &(group->group_address));
+      }
+    }
+
+    if ((type == IGMP_V2_MEMB_REPORT) || (type == IGMP_LEAVE_GROUP)) {
+      igmp->igmp_msgtype  = type;
+      igmp->igmp_maxresp  = 0;
+      igmp->igmp_checksum = 0;
+      igmp->igmp_checksum = inet_chksum( igmp, IGMP_MINLEN);
+
+      igmp_ip_output_if( p, &src, dest, IGMP_TTL, IP_PROTO_IGMP, group->interface);
+    }
+
+    pbuf_free (p);
+  } else {
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_send: not enough memory for igmp_send\n"));
+  }
+}
+
+#endif /* LWIP_IGMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/inet.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/inet.c
new file mode 100644
index 0000000..cded5ef
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/inet.c
@@ -0,0 +1,278 @@
+/**
+ * @file
+ * Functions common to all TCP/IPv4 modules, such as the byte order functions.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/inet.h"
+
+/* Here for now until needed in other places in lwIP */
+#ifndef isprint
+#define in_range(c, lo, up)  ((u8_t)c >= lo && (u8_t)c <= up)
+#define isprint(c)           in_range(c, 0x20, 0x7f)
+#define isdigit(c)           in_range(c, '0', '9')
+#define isxdigit(c)          (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F'))
+#define islower(c)           in_range(c, 'a', 'z')
+#define isspace(c)           (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v')
+#endif
+
+/**
+ * Ascii internet address interpretation routine.
+ * The value returned is in network order.
+ *
+ * @param cp IP address in ascii represenation (e.g. "127.0.0.1")
+ * @return ip address in network order
+ */
+u32_t
+inet_addr(const char *cp)
+{
+  struct in_addr val;
+
+  if (inet_aton(cp, &val)) {
+    return (val.s_addr);
+  }
+  return (INADDR_NONE);
+}
+
+/**
+ * Check whether "cp" is a valid ascii representation
+ * of an Internet address and convert to a binary address.
+ * Returns 1 if the address is valid, 0 if not.
+ * This replaces inet_addr, the return value from which
+ * cannot distinguish between failure and a local broadcast address.
+ *
+ * @param cp IP address in ascii represenation (e.g. "127.0.0.1")
+ * @param addr pointer to which to save the ip address in network order
+ * @return 1 if cp could be converted to addr, 0 on failure
+ */
+int
+inet_aton(const char *cp, struct in_addr *addr)
+{
+  u32_t val;
+  int base, n, c;
+  u32_t parts[4];
+  u32_t *pp = parts;
+
+  c = *cp;
+  for (;;) {
+    /*
+     * Collect number up to ``.''.
+     * Values are specified as for C:
+     * 0x=hex, 0=octal, 1-9=decimal.
+     */
+    if (!isdigit(c))
+      return (0);
+    val = 0;
+    base = 10;
+    if (c == '0') {
+      c = *++cp;
+      if (c == 'x' || c == 'X') {
+        base = 16;
+        c = *++cp;
+      } else
+        base = 8;
+    }
+    for (;;) {
+      if (isdigit(c)) {
+        val = (val * base) + (int)(c - '0');
+        c = *++cp;
+      } else if (base == 16 && isxdigit(c)) {
+        val = (val << 4) | (int)(c + 10 - (islower(c) ? 'a' : 'A'));
+        c = *++cp;
+      } else
+        break;
+    }
+    if (c == '.') {
+      /*
+       * Internet format:
+       *  a.b.c.d
+       *  a.b.c   (with c treated as 16 bits)
+       *  a.b (with b treated as 24 bits)
+       */
+      if (pp >= parts + 3)
+        return (0);
+      *pp++ = val;
+      c = *++cp;
+    } else
+      break;
+  }
+  /*
+   * Check for trailing characters.
+   */
+  if (c != '\0' && (!isprint(c) || !isspace(c)))
+    return (0);
+  /*
+   * Concoct the address according to
+   * the number of parts specified.
+   */
+  n = pp - parts + 1;
+  switch (n) {
+
+  case 0:
+    return (0);       /* initial nondigit */
+
+  case 1:             /* a -- 32 bits */
+    break;
+
+  case 2:             /* a.b -- 8.24 bits */
+    if (val > 0xffffffUL)
+      return (0);
+    val |= parts[0] << 24;
+    break;
+
+  case 3:             /* a.b.c -- 8.8.16 bits */
+    if (val > 0xffff)
+      return (0);
+    val |= (parts[0] << 24) | (parts[1] << 16);
+    break;
+
+  case 4:             /* a.b.c.d -- 8.8.8.8 bits */
+    if (val > 0xff)
+      return (0);
+    val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8);
+    break;
+  }
+  if (addr)
+    addr->s_addr = htonl(val);
+  return (1);
+}
+
+/**
+ * Convert numeric IP address into decimal dotted ASCII representation.
+ * returns ptr to static buffer; not reentrant!
+ *
+ * @param addr ip address in network order to convert
+ * @return pointer to a global static (!) buffer that holds the ASCII
+ *         represenation of addr
+ */
+char *
+inet_ntoa(struct in_addr addr)
+{
+  static char str[16];
+  u32_t s_addr = addr.s_addr;
+  char inv[3];
+  char *rp;
+  u8_t *ap;
+  u8_t rem;
+  u8_t n;
+  u8_t i;
+
+  rp = str;
+  ap = (u8_t *)&s_addr;
+  for(n = 0; n < 4; n++) {
+    i = 0;
+    do {
+      rem = *ap % (u8_t)10;
+      *ap /= (u8_t)10;
+      inv[i++] = '0' + rem;
+    } while(*ap);
+    while(i--)
+      *rp++ = inv[i];
+    *rp++ = '.';
+    ap++;
+  }
+  *--rp = 0;
+  return str;
+}
+
+/**
+ * These are reference implementations of the byte swapping functions.
+ * Again with the aim of being simple, correct and fully portable.
+ * Byte swapping is the second thing you would want to optimize. You will
+ * need to port it to your architecture and in your cc.h:
+ *
+ * #define LWIP_PLATFORM_BYTESWAP 1
+ * #define LWIP_PLATFORM_HTONS(x) 
+ * #define LWIP_PLATFORM_HTONL(x) 
+ *
+ * Note ntohs() and ntohl() are merely references to the htonx counterparts.
+ */
+
+#if (LWIP_PLATFORM_BYTESWAP == 0) && (BYTE_ORDER == LITTLE_ENDIAN)
+
+/**
+ * Convert an u16_t from host- to network byte order.
+ *
+ * @param n u16_t in host byte order
+ * @return n in network byte order
+ */
+u16_t
+htons(u16_t n)
+{
+  return ((n & 0xff) << 8) | ((n & 0xff00) >> 8);
+}
+
+/**
+ * Convert an u16_t from network- to host byte order.
+ *
+ * @param n u16_t in network byte order
+ * @return n in host byte order
+ */
+u16_t
+ntohs(u16_t n)
+{
+  return htons(n);
+}
+
+/**
+ * Convert an u32_t from host- to network byte order.
+ *
+ * @param n u32_t in host byte order
+ * @return n in network byte order
+ */
+u32_t
+htonl(u32_t n)
+{
+  return ((n & 0xff) << 24) |
+    ((n & 0xff00) << 8) |
+    ((n & 0xff0000UL) >> 8) |
+    ((n & 0xff000000UL) >> 24);
+}
+
+/**
+ * Convert an u32_t from network- to host byte order.
+ *
+ * @param n u32_t in network byte order
+ * @return n in host byte order
+ */
+u32_t
+ntohl(u32_t n)
+{
+  return htonl(n);
+}
+
+#endif /* (LWIP_PLATFORM_BYTESWAP == 0) && (BYTE_ORDER == LITTLE_ENDIAN) */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/inet_chksum.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/inet_chksum.c
new file mode 100644
index 0000000..095bef6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/inet_chksum.c
@@ -0,0 +1,423 @@
+/**
+ * @file
+ * Incluse internet checksum functions.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/inet_chksum.h"
+#include "lwip/inet.h"
+
+#include 
+
+/* These are some reference implementations of the checksum algorithm, with the
+ * aim of being simple, correct and fully portable. Checksumming is the
+ * first thing you would want to optimize for your platform. If you create
+ * your own version, link it in and in your cc.h put:
+ *
+ * #define LWIP_CHKSUM 
+ *
+ * Or you can select from the implementations below by defining
+ * LWIP_CHKSUM_ALGORITHM to 1, 2 or 3.
+ */
+
+#ifndef LWIP_CHKSUM
+# define LWIP_CHKSUM lwip_standard_chksum
+# ifndef LWIP_CHKSUM_ALGORITHM
+#  define LWIP_CHKSUM_ALGORITHM 1
+# endif
+#endif
+/* If none set: */
+#ifndef LWIP_CHKSUM_ALGORITHM
+# define LWIP_CHKSUM_ALGORITHM 0
+#endif
+
+#if (LWIP_CHKSUM_ALGORITHM == 1) /* Version #1 */
+/**
+ * lwip checksum
+ *
+ * @param dataptr points to start of data to be summed at any boundary
+ * @param len length of data to be summed
+ * @return host order (!) lwip checksum (non-inverted Internet sum)
+ *
+ * @note accumulator size limits summable length to 64k
+ * @note host endianess is irrelevant (p3 RFC1071)
+ */
+static u16_t
+lwip_standard_chksum(void *dataptr, u16_t len)
+{
+  u32_t acc;
+  u16_t src;
+  u8_t *octetptr;
+
+  acc = 0;
+  /* dataptr may be at odd or even addresses */
+  octetptr = (u8_t*)dataptr;
+  while (len > 1)
+  {
+    /* declare first octet as most significant
+       thus assume network order, ignoring host order */
+    src = (*octetptr) << 8;
+    octetptr++;
+    /* declare second octet as least significant */
+    src |= (*octetptr);
+    octetptr++;
+    acc += src;
+    len -= 2;
+  }
+  if (len > 0)
+  {
+    /* accumulate remaining octet */
+    src = (*octetptr) << 8;
+    acc += src;
+  }
+  /* add deferred carry bits */
+  acc = (acc >> 16) + (acc & 0x0000ffffUL);
+  if ((acc & 0xffff0000) != 0) {
+    acc = (acc >> 16) + (acc & 0x0000ffffUL);
+  }
+  /* This maybe a little confusing: reorder sum using htons()
+     instead of ntohs() since it has a little less call overhead.
+     The caller must invert bits for Internet sum ! */
+  return htons((u16_t)acc);
+}
+#endif
+
+#if (LWIP_CHKSUM_ALGORITHM == 2) /* Alternative version #2 */
+/*
+ * Curt McDowell
+ * Broadcom Corp.
+ * csm@broadcom.com
+ *
+ * IP checksum two bytes at a time with support for
+ * unaligned buffer.
+ * Works for len up to and including 0x20000.
+ * by Curt McDowell, Broadcom Corp. 12/08/2005
+ *
+ * @param dataptr points to start of data to be summed at any boundary
+ * @param len length of data to be summed
+ * @return host order (!) lwip checksum (non-inverted Internet sum)
+ */
+
+static u16_t
+lwip_standard_chksum(void *dataptr, int len)
+{
+  u8_t *pb = dataptr;
+  u16_t *ps, t = 0;
+  u32_t sum = 0;
+  int odd = ((u32_t)pb & 1);
+
+  /* Get aligned to u16_t */
+  if (odd && len > 0) {
+    ((u8_t *)&t)[1] = *pb++;
+    len--;
+  }
+
+  /* Add the bulk of the data */
+  ps = (u16_t *)pb;
+  while (len > 1) {
+    sum += *ps++;
+    len -= 2;
+  }
+
+  /* Consume left-over byte, if any */
+  if (len > 0)
+    ((u8_t *)&t)[0] = *(u8_t *)ps;;
+
+  /* Add end bytes */
+  sum += t;
+
+  /*  Fold 32-bit sum to 16 bits */
+  while ((sum >> 16) != 0)
+    sum = (sum & 0xffff) + (sum >> 16);
+
+  /* Swap if alignment was odd */
+  if (odd)
+    sum = ((sum & 0xff) << 8) | ((sum & 0xff00) >> 8);
+
+  return sum;
+}
+#endif
+
+#if (LWIP_CHKSUM_ALGORITHM == 3) /* Alternative version #3 */
+/**
+ * An optimized checksum routine. Basically, it uses loop-unrolling on
+ * the checksum loop, treating the head and tail bytes specially, whereas
+ * the inner loop acts on 8 bytes at a time.
+ *
+ * @arg start of buffer to be checksummed. May be an odd byte address.
+ * @len number of bytes in the buffer to be checksummed.
+ * @return host order (!) lwip checksum (non-inverted Internet sum)
+ *
+ * by Curt McDowell, Broadcom Corp. December 8th, 2005
+ */
+
+static u16_t
+lwip_standard_chksum(void *dataptr, int len)
+{
+  u8_t *pb = dataptr;
+  u16_t *ps, t = 0;
+  u32_t *pl;
+  u32_t sum = 0, tmp;
+  /* starts at odd byte address? */
+  int odd = ((u32_t)pb & 1);
+
+  if (odd && len > 0) {
+    ((u8_t *)&t)[1] = *pb++;
+    len--;
+  }
+
+  ps = (u16_t *)pb;
+
+  if (((u32_t)ps & 3) && len > 1) {
+    sum += *ps++;
+    len -= 2;
+  }
+
+  pl = (u32_t *)ps;
+
+  while (len > 7)  {
+    tmp = sum + *pl++;          /* ping */
+    if (tmp < sum)
+      tmp++;                    /* add back carry */
+
+    sum = tmp + *pl++;          /* pong */
+    if (sum < tmp)
+      sum++;                    /* add back carry */
+
+    len -= 8;
+  }
+
+  /* make room in upper bits */
+  sum = (sum >> 16) + (sum & 0xffff);
+
+  ps = (u16_t *)pl;
+
+  /* 16-bit aligned word remaining? */
+  while (len > 1) {
+    sum += *ps++;
+    len -= 2;
+  }
+
+  /* dangling tail byte remaining? */
+  if (len > 0)                  /* include odd byte */
+    ((u8_t *)&t)[0] = *(u8_t *)ps;
+
+  sum += t;                     /* add end bytes */
+
+  while ((sum >> 16) != 0)      /* combine halves */
+    sum = (sum >> 16) + (sum & 0xffff);
+
+  if (odd)
+    sum = ((sum & 0xff) << 8) | ((sum & 0xff00) >> 8);
+
+  return sum;
+}
+#endif
+
+/* inet_chksum_pseudo:
+ *
+ * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
+ * IP addresses are expected to be in network byte order.
+ *
+ * @param p chain of pbufs over that a checksum should be calculated (ip data part)
+ * @param src source ip address (used for checksum of pseudo header)
+ * @param dst destination ip address (used for checksum of pseudo header)
+ * @param proto ip protocol (used for checksum of pseudo header)
+ * @param proto_len length of the ip data part (used for checksum of pseudo header)
+ * @return checksum (as u16_t) to be saved directly in the protocol header
+ */
+u16_t
+inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u16_t proto_len)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped;
+
+  acc = 0;
+  swapped = 0;
+  /* iterate through all pbuf in chain */
+  for(q = p; q != NULL; q = q->next) {
+    LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n",
+      (void *)q, (void *)q->next));
+    acc += LWIP_CHKSUM(q->payload, q->len);
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/
+    while ((acc >> 16) != 0) {
+      acc = (acc & 0xffffUL) + (acc >> 16);
+    }
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8);
+    }
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/
+  }
+
+  if (swapped) {
+    acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8);
+  }
+  acc += (src->addr & 0xffffUL);
+  acc += ((src->addr >> 16) & 0xffffUL);
+  acc += (dest->addr & 0xffffUL);
+  acc += ((dest->addr >> 16) & 0xffffUL);
+  acc += (u32_t)htons((u16_t)proto);
+  acc += (u32_t)htons(proto_len);
+
+  while ((acc >> 16) != 0) {
+    acc = (acc & 0xffffUL) + (acc >> 16);
+  }
+  LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc));
+  return (u16_t)~(acc & 0xffffUL);
+}
+
+/* inet_chksum_pseudo:
+ *
+ * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
+ * IP addresses are expected to be in network byte order.
+ *
+ * @param p chain of pbufs over that a checksum should be calculated (ip data part)
+ * @param src source ip address (used for checksum of pseudo header)
+ * @param dst destination ip address (used for checksum of pseudo header)
+ * @param proto ip protocol (used for checksum of pseudo header)
+ * @param proto_len length of the ip data part (used for checksum of pseudo header)
+ * @return checksum (as u16_t) to be saved directly in the protocol header
+ */
+u16_t
+inet_chksum_pseudo_partial(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u16_t proto_len, u16_t chksum_len)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped;
+  u16_t chklen;
+
+  acc = 0;
+  swapped = 0;
+  /* iterate through all pbuf in chain */
+  for(q = p; (q != NULL) && (chksum_len > 0); q = q->next) {
+    LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n",
+      (void *)q, (void *)q->next));
+    chklen = q->len;
+    if (chklen > chksum_len) {
+      chklen = chksum_len;
+    }
+    acc += LWIP_CHKSUM(q->payload, chklen);
+    chksum_len -= chklen;
+    LWIP_ASSERT("delete me", chksum_len < 0x7fff);
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/
+    while ((acc >> 16) != 0) {
+      acc = (acc & 0xffffUL) + (acc >> 16);
+    }
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8);
+    }
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/
+  }
+
+  if (swapped) {
+    acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8);
+  }
+  acc += (src->addr & 0xffffUL);
+  acc += ((src->addr >> 16) & 0xffffUL);
+  acc += (dest->addr & 0xffffUL);
+  acc += ((dest->addr >> 16) & 0xffffUL);
+  acc += (u32_t)htons((u16_t)proto);
+  acc += (u32_t)htons(proto_len);
+
+  while ((acc >> 16) != 0) {
+    acc = (acc & 0xffffUL) + (acc >> 16);
+  }
+  LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc));
+  return (u16_t)~(acc & 0xffffUL);
+}
+
+/* inet_chksum:
+ *
+ * Calculates the Internet checksum over a portion of memory. Used primarily for IP
+ * and ICMP.
+ *
+ * @param dataptr start of the buffer to calculate the checksum (no alignment needed)
+ * @param len length of the buffer to calculate the checksum
+ * @return checksum (as u16_t) to be saved directly in the protocol header
+ */
+
+u16_t
+inet_chksum(void *dataptr, u16_t len)
+{
+  u32_t acc;
+
+  acc = LWIP_CHKSUM(dataptr, len);
+  while ((acc >> 16) != 0) {
+    acc = (acc & 0xffff) + (acc >> 16);
+  }
+  return (u16_t)~(acc & 0xffff);
+}
+
+/**
+ * Calculate a checksum over a chain of pbufs (without pseudo-header, much like
+ * inet_chksum only pbufs are used).
+ *
+ * @param p pbuf chain over that the checksum should be calculated
+ * @return checksum (as u16_t) to be saved directly in the protocol header
+ */
+u16_t
+inet_chksum_pbuf(struct pbuf *p)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped;
+
+  acc = 0;
+  swapped = 0;
+  for(q = p; q != NULL; q = q->next) {
+    acc += LWIP_CHKSUM(q->payload, q->len);
+    while ((acc >> 16) != 0) {
+      acc = (acc & 0xffffUL) + (acc >> 16);
+    }
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = (acc & 0x00ffUL << 8) | (acc & 0xff00UL >> 8);
+    }
+  }
+
+  if (swapped) {
+    acc = ((acc & 0x00ffUL) << 8) | ((acc & 0xff00UL) >> 8);
+  }
+  return (u16_t)~(acc & 0xffffUL);
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/ip.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/ip.c
new file mode 100644
index 0000000..11da757
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/ip.c
@@ -0,0 +1,614 @@
+/**
+ * @file
+ * This is the IPv4 layer implementation for incoming and outgoing IP traffic.
+ *
+ * @see ip_frag.c
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+#include "lwip/ip.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/ip_frag.h"
+#include "lwip/inet.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/netif.h"
+#include "lwip/icmp.h"
+#include "lwip/igmp.h"
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+#include "lwip/snmp.h"
+#include "lwip/dhcp.h"
+#include "lwip/stats.h"
+#include "arch/perf.h"
+
+/**
+ * Finds the appropriate network interface for a given IP address. It
+ * searches the list of network interfaces linearly. A match is found
+ * if the masked IP address of the network interface equals the masked
+ * IP address given to the function.
+ *
+ * @param dest the destination IP address for which to find the route
+ * @return the netif on which to send to reach dest
+ */
+struct netif *
+ip_route(struct ip_addr *dest)
+{
+  struct netif *netif;
+
+  /* iterate through netifs */
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+    /* network mask matches? */
+    if (netif_is_up(netif)) {
+      if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) {
+        /* return netif on which to forward IP packet */
+        return netif;
+      }
+    }
+  }
+  if ((netif_default == NULL) || (!netif_is_up(netif_default))) {
+    LWIP_DEBUGF(IP_DEBUG | 2, ("ip_route: No route to 0x%"X32_F"\n", dest->addr));
+    IP_STATS_INC(ip.rterr);
+    snmp_inc_ipoutnoroutes();
+    return NULL;
+  }
+  /* no matching netif found, use default netif */
+  return netif_default;
+}
+
+#if IP_FORWARD
+/**
+ * Forwards an IP packet. It finds an appropriate route for the
+ * packet, decrements the TTL value of the packet, adjusts the
+ * checksum and outputs the packet on the appropriate interface.
+ *
+ * @param p the packet to forward (p->payload points to IP header)
+ * @param iphdr the IP header of the input packet
+ * @param inp the netif on which this packet was received
+ * @return the netif on which the packet was sent (NULL if it wasn't sent)
+ */
+static struct netif *
+ip_forward(struct pbuf *p, struct ip_hdr *iphdr, struct netif *inp)
+{
+  struct netif *netif;
+
+  PERF_START;
+  /* Find network interface where to forward this IP packet to. */
+  netif = ip_route((struct ip_addr *)&(iphdr->dest));
+  if (netif == NULL) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_forward: no forwarding route for 0x%"X32_F" found\n",
+                      iphdr->dest.addr));
+    snmp_inc_ipoutnoroutes();
+    return (struct netif *)NULL;
+  }
+  /* Do not forward packets onto the same network interface on which
+   * they arrived. */
+  if (netif == inp) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_forward: not bouncing packets back on incoming interface.\n"));
+    snmp_inc_ipoutnoroutes();
+    return (struct netif *)NULL;
+  }
+
+  /* decrement TTL */
+  IPH_TTL_SET(iphdr, IPH_TTL(iphdr) - 1);
+  /* send ICMP if TTL == 0 */
+  if (IPH_TTL(iphdr) == 0) {
+    snmp_inc_ipinhdrerrors();
+#if LWIP_ICMP
+    /* Don't send ICMP messages in response to ICMP messages */
+    if (IPH_PROTO(iphdr) != IP_PROTO_ICMP) {
+      icmp_time_exceeded(p, ICMP_TE_TTL);
+    }
+#endif /* LWIP_ICMP */
+    return (struct netif *)NULL;
+  }
+
+  /* Incrementally update the IP checksum. */
+  if (IPH_CHKSUM(iphdr) >= htons(0xffff - 0x100)) {
+    IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100) + 1);
+  } else {
+    IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100));
+  }
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to 0x%"X32_F"\n",
+                    iphdr->dest.addr));
+
+  IP_STATS_INC(ip.fw);
+  IP_STATS_INC(ip.xmit);
+  snmp_inc_ipforwdatagrams();
+
+  PERF_STOP("ip_forward");
+  /* transmit pbuf on chosen interface */
+  netif->output(netif, p, (struct ip_addr *)&(iphdr->dest));
+  return netif;
+}
+#endif /* IP_FORWARD */
+
+/**
+ * This function is called by the network interface device driver when
+ * an IP packet is received. The function does the basic checks of the
+ * IP header such as packet size being at least larger than the header
+ * size etc. If the packet was not destined for us, the packet is
+ * forwarded (using ip_forward). The IP checksum is always checked.
+ *
+ * Finally, the packet is sent to the upper layer protocol input function.
+ *
+ * @param p the received IP packet (p->payload points to IP header)
+ * @param inp the netif on which this packet was received
+ * @return ERR_OK if the packet was processed (could return ERR_* if it wasn't
+ *         processed, but currently always returns ERR_OK)
+ */
+err_t
+ip_input(struct pbuf *p, struct netif *inp)
+{
+  struct ip_hdr *iphdr;
+  struct netif *netif;
+  u16_t iphdr_hlen;
+  u16_t iphdr_len;
+#if LWIP_DHCP
+  int check_ip_src=1;
+#endif /* LWIP_DHCP */
+
+  IP_STATS_INC(ip.recv);
+  snmp_inc_ipinreceives();
+
+  /* identify the IP header */
+  iphdr = p->payload;
+  if (IPH_V(iphdr) != 4) {
+    LWIP_DEBUGF(IP_DEBUG | 1, ("IP packet dropped due to bad version number %"U16_F"\n", IPH_V(iphdr)));
+    ip_debug_print(p);
+    pbuf_free(p);
+    IP_STATS_INC(ip.err);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipinhdrerrors();
+    return ERR_OK;
+  }
+
+  /* obtain IP header length in number of 32-bit words */
+  iphdr_hlen = IPH_HL(iphdr);
+  /* calculate IP header length in bytes */
+  iphdr_hlen *= 4;
+  /* obtain ip length in bytes */
+  iphdr_len = ntohs(IPH_LEN(iphdr));
+
+  /* header length exceeds first pbuf length, or ip length exceeds total pbuf length? */
+  if ((iphdr_hlen > p->len) || (iphdr_len > p->tot_len)) {
+    if (iphdr_hlen > p->len)
+    LWIP_DEBUGF(IP_DEBUG | 2, ("IP header (len %"U16_F") does not fit in first pbuf (len %"U16_F"), IP packet dropped.\n",
+                               iphdr_hlen, p->len));
+    if (iphdr_len > p->tot_len)
+    LWIP_DEBUGF(IP_DEBUG | 2, ("IP (len %"U16_F") is longer than pbuf (len %"U16_F"), "
+                               "IP packet dropped.\n",
+                               iphdr_len, p->tot_len));
+    /* free (drop) packet pbufs */
+    pbuf_free(p);
+    IP_STATS_INC(ip.lenerr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipindiscards();
+    return ERR_OK;
+  }
+
+  /* verify checksum */
+#if CHECKSUM_CHECK_IP
+  if (inet_chksum(iphdr, iphdr_hlen) != 0) {
+
+    LWIP_DEBUGF(IP_DEBUG | 2, ("Checksum (0x%"X16_F") failed, IP packet dropped.\n", inet_chksum(iphdr, iphdr_hlen)));
+    ip_debug_print(p);
+    pbuf_free(p);
+    IP_STATS_INC(ip.chkerr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipinhdrerrors();
+    return ERR_OK;
+  }
+#endif
+
+  /* Trim pbuf. This should have been done at the netif layer,
+   * but we'll do it anyway just to be sure that its done. */
+  pbuf_realloc(p, iphdr_len);
+
+  /* match packet against an interface, i.e. is this packet for us? */
+#if LWIP_IGMP
+  if (ip_addr_ismulticast(&(iphdr->dest))) {
+    if ((inp->flags & NETIF_FLAG_IGMP) && (igmp_lookfor_group(inp, &(iphdr->dest)))) {
+      netif = inp;
+    } else {
+      netif = NULL;
+    }
+  } else
+#endif /* LWIP_IGMP */
+  {
+    /* start trying with inp. if that's not acceptable, start walking the
+       list of configured netifs.
+       'first' is used as a boolean to mark whether we started walking the list */
+    int first = 1;
+    netif = inp;
+    do {
+      LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest 0x%"X32_F" netif->ip_addr 0x%"X32_F" (0x%"X32_F", 0x%"X32_F", 0x%"X32_F")\n",
+          iphdr->dest.addr, netif->ip_addr.addr,
+          iphdr->dest.addr & netif->netmask.addr,
+          netif->ip_addr.addr & netif->netmask.addr,
+          iphdr->dest.addr & ~(netif->netmask.addr)));
+
+      /* interface is up and configured? */
+      if ((netif_is_up(netif)) && (!ip_addr_isany(&(netif->ip_addr)))) {
+        /* unicast to this interface address? */
+        if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr)) ||
+            /* or broadcast on this interface network address? */
+            ip_addr_isbroadcast(&(iphdr->dest), netif)) {
+          LWIP_DEBUGF(IP_DEBUG, ("ip_input: packet accepted on interface %c%c\n",
+              netif->name[0], netif->name[1]));
+          /* break out of for loop */
+          break;
+        }
+      }
+      if (first) {
+        first = 0;
+        netif = netif_list;
+      } else {
+        netif = netif->next;
+      }
+      if (netif == inp) {
+        netif = netif->next;
+      }
+    } while(netif != NULL);
+  }
+
+#if LWIP_DHCP
+  /* Pass DHCP messages regardless of destination address. DHCP traffic is addressed
+   * using link layer addressing (such as Ethernet MAC) so we must not filter on IP.
+   * According to RFC 1542 section 3.1.1, referred by RFC 2131).
+   */
+  if (netif == NULL) {
+    /* remote port is DHCP server? */
+    if (IPH_PROTO(iphdr) == IP_PROTO_UDP) {
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE | 1, ("ip_input: UDP packet to DHCP client port %"U16_F"\n",
+        ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdr_hlen))->dest)));
+      if (ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdr_hlen))->dest) == DHCP_CLIENT_PORT) {
+        LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE | 1, ("ip_input: DHCP packet accepted.\n"));
+        netif = inp;
+        check_ip_src = 0;
+      }
+    }
+  }
+#endif /* LWIP_DHCP */
+
+  /* broadcast or multicast packet source address? Compliant with RFC 1122: 3.2.1.3 */
+#if LWIP_DHCP
+  if (check_ip_src)
+#endif /* LWIP_DHCP */
+  {  if ((ip_addr_isbroadcast(&(iphdr->src), inp)) ||
+         (ip_addr_ismulticast(&(iphdr->src)))) {
+      /* packet source is not valid */
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE | 1, ("ip_input: packet source is not valid.\n"));
+      /* free (drop) packet pbufs */
+      pbuf_free(p);
+      IP_STATS_INC(ip.drop);
+      snmp_inc_ipinaddrerrors();
+      snmp_inc_ipindiscards();
+      return ERR_OK;
+    }
+  }
+
+  /* packet not for us? */
+  if (netif == NULL) {
+    /* packet not for us, route or discard */
+    LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE | 1, ("ip_input: packet not for us.\n"));
+#if IP_FORWARD
+    /* non-broadcast packet? */
+    if (!ip_addr_isbroadcast(&(iphdr->dest), inp)) {
+      /* try to forward IP packet on (other) interfaces */
+      ip_forward(p, iphdr, inp);
+    } else
+#endif /* IP_FORWARD */
+    {
+      snmp_inc_ipinaddrerrors();
+      snmp_inc_ipindiscards();
+    }
+    pbuf_free(p);
+    return ERR_OK;
+  }
+  /* packet consists of multiple fragments? */
+  if ((IPH_OFFSET(iphdr) & htons(IP_OFFMASK | IP_MF)) != 0) {
+#if IP_REASSEMBLY /* packet fragment reassembly code present? */
+    LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip_reass()\n",
+      ntohs(IPH_ID(iphdr)), p->tot_len, ntohs(IPH_LEN(iphdr)), !!(IPH_OFFSET(iphdr) & htons(IP_MF)), (ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)*8));
+    /* reassemble the packet*/
+    p = ip_reass(p);
+    /* packet not fully reassembled yet? */
+    if (p == NULL) {
+      return ERR_OK;
+    }
+    iphdr = p->payload;
+#else /* IP_REASSEMBLY == 0, no packet fragment reassembly code present */
+    pbuf_free(p);
+    LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since it was fragmented (0x%"X16_F") (while IP_REASSEMBLY == 0).\n",
+      ntohs(IPH_OFFSET(iphdr))));
+    IP_STATS_INC(ip.opterr);
+    IP_STATS_INC(ip.drop);
+    /* unsupported protocol feature */
+    snmp_inc_ipinunknownprotos();
+    return ERR_OK;
+#endif /* IP_REASSEMBLY */
+  }
+
+#if IP_OPTIONS_ALLOWED == 0 /* no support for IP options in the IP header? */
+
+#if LWIP_IGMP
+  /* there is an extra "router alert" option in IGMP messages which we allow for but do not police */
+  if((iphdr_hlen > IP_HLEN &&  (IPH_PROTO(iphdr) != IP_PROTO_IGMP)) {
+#else
+  if (iphdr_hlen > IP_HLEN) {
+#endif /* LWIP_IGMP */
+    LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since there were IP options (while IP_OPTIONS_ALLOWED == 0).\n"));
+    pbuf_free(p);
+    IP_STATS_INC(ip.opterr);
+    IP_STATS_INC(ip.drop);
+    /* unsupported protocol feature */
+    snmp_inc_ipinunknownprotos();
+    return ERR_OK;
+  }
+#endif /* IP_OPTIONS_ALLOWED == 0 */
+
+  /* send to upper layers */
+  LWIP_DEBUGF(IP_DEBUG, ("ip_input: \n"));
+  ip_debug_print(p);
+  LWIP_DEBUGF(IP_DEBUG, ("ip_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len));
+
+#if LWIP_RAW
+  /* raw input did not eat the packet? */
+  if (raw_input(p, inp) == 0)
+#endif /* LWIP_RAW */
+  {
+
+    switch (IPH_PROTO(iphdr)) {
+#if LWIP_UDP
+    case IP_PROTO_UDP:
+#if LWIP_UDPLITE
+    case IP_PROTO_UDPLITE:
+#endif /* LWIP_UDPLITE */
+      snmp_inc_ipindelivers();
+      udp_input(p, inp);
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+    case IP_PROTO_TCP:
+      snmp_inc_ipindelivers();
+      tcp_input(p, inp);
+      break;
+#endif /* LWIP_TCP */
+#if LWIP_ICMP
+    case IP_PROTO_ICMP:
+      snmp_inc_ipindelivers();
+      icmp_input(p, inp);
+      break;
+#endif /* LWIP_ICMP */
+#if LWIP_IGMP
+    case IP_PROTO_IGMP:
+      igmp_input(p,inp,&(iphdr->dest));
+      break;
+#endif /* LWIP_IGMP */
+    default:
+#if LWIP_ICMP
+      /* send ICMP destination protocol unreachable unless is was a broadcast */
+      if (!ip_addr_isbroadcast(&(iphdr->dest), inp) &&
+          !ip_addr_ismulticast(&(iphdr->dest))) {
+        p->payload = iphdr;
+        icmp_dest_unreach(p, ICMP_DUR_PROTO);
+      }
+#endif /* LWIP_ICMP */
+      pbuf_free(p);
+
+      LWIP_DEBUGF(IP_DEBUG | 2, ("Unsupported transport protocol %"U16_F"\n", IPH_PROTO(iphdr)));
+
+      IP_STATS_INC(ip.proterr);
+      IP_STATS_INC(ip.drop);
+      snmp_inc_ipinunknownprotos();
+    }
+  }
+
+  return ERR_OK;
+}
+
+/**
+ * Sends an IP packet on a network interface. This function constructs
+ * the IP header and calculates the IP header checksum. If the source
+ * IP address is NULL, the IP address of the outgoing network
+ * interface is filled in as source address.
+ * If the destination IP address is IP_HDRINCL, p is assumed to already
+ * include an IP header and p->payload points to it instead of the data.
+ *
+ * @param p the packet to send (p->payload points to the data, e.g. next
+            protocol header; if dest == IP_HDRINCL, p already includes an IP
+            header and p->payload points to that IP header)
+ * @param src the source IP address to send from (if src == IP_ADDR_ANY, the
+ *         IP  address of the netif used to send is used as source address)
+ * @param dest the destination IP address to send the packet to
+ * @param ttl the TTL value to be set in the IP header
+ * @param tos the TOS value to be set in the IP header
+ * @param proto the PROTOCOL to be set in the IP header
+ * @param netif the netif on which to send this packet
+ * @return ERR_OK if the packet was sent OK
+ *         ERR_BUF if p doesn't have enough space for IP/LINK headers
+ *         returns errors returned by netif->output
+ *
+ * @note ip_id: RFC791 "some host may be able to simply use
+ *  unique identifiers independent of destination"
+ */
+err_t
+ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+             u8_t ttl, u8_t tos,
+             u8_t proto, struct netif *netif)
+{
+  struct ip_hdr *iphdr;
+  static u16_t ip_id = 0;
+
+  snmp_inc_ipoutrequests();
+
+  /* Should the IP header be generated or is it already included in p? */
+  if (dest != IP_HDRINCL) {
+    /* generate IP header */
+    if (pbuf_header(p, IP_HLEN)) {
+      LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: not enough room for IP header in pbuf\n"));
+
+      IP_STATS_INC(ip.err);
+      snmp_inc_ipoutdiscards();
+      return ERR_BUF;
+    }
+
+    iphdr = p->payload;
+    LWIP_ASSERT("check that first pbuf can hold struct ip_hdr",
+               (p->len >= sizeof(struct ip_hdr)));
+
+    IPH_TTL_SET(iphdr, ttl);
+    IPH_PROTO_SET(iphdr, proto);
+
+    ip_addr_set(&(iphdr->dest), dest);
+
+    IPH_VHLTOS_SET(iphdr, 4, IP_HLEN / 4, tos);
+    IPH_LEN_SET(iphdr, htons(p->tot_len));
+    IPH_OFFSET_SET(iphdr, 0);
+    IPH_ID_SET(iphdr, htons(ip_id));
+    ++ip_id;
+
+    if (ip_addr_isany(src)) {
+      ip_addr_set(&(iphdr->src), &(netif->ip_addr));
+    } else {
+      ip_addr_set(&(iphdr->src), src);
+    }
+
+    IPH_CHKSUM_SET(iphdr, 0);
+#if CHECKSUM_GEN_IP
+    IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
+#endif
+  } else {
+    /* IP header already included in p */
+    iphdr = p->payload;
+    dest = &(iphdr->dest);
+  }
+
+#if IP_FRAG
+  /* don't fragment if interface has mtu set to 0 [loopif] */
+  if (netif->mtu && (p->tot_len > netif->mtu))
+    return ip_frag(p,netif,dest);
+#endif
+
+  IP_STATS_INC(ip.xmit);
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c%"U16_F"\n", netif->name[0], netif->name[1], netif->num));
+  ip_debug_print(p);
+
+  LWIP_DEBUGF(IP_DEBUG, ("netif->output()"));
+
+  return netif->output(netif, p, dest);
+}
+
+/**
+ * Simple interface to ip_output_if. It finds the outgoing network
+ * interface and calls upon ip_output_if to do the actual work.
+ *
+ * @param p the packet to send (p->payload points to the data, e.g. next
+            protocol header; if dest == IP_HDRINCL, p already includes an IP
+            header and p->payload points to that IP header)
+ * @param src the source IP address to send from (if src == IP_ADDR_ANY, the
+ *         IP  address of the netif used to send is used as source address)
+ * @param dest the destination IP address to send the packet to
+ * @param ttl the TTL value to be set in the IP header
+ * @param tos the TOS value to be set in the IP header
+ * @param proto the PROTOCOL to be set in the IP header
+ *
+ * @return ERR_RTE if no route is found
+ *         see ip_output_if() for more return values
+ */
+err_t
+ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+          u8_t ttl, u8_t tos, u8_t proto)
+{
+  struct netif *netif;
+
+  if ((netif = ip_route(dest)) == NULL) {
+    return ERR_RTE;
+  }
+
+  return ip_output_if(p, src, dest, ttl, tos, proto, netif);
+}
+
+#if IP_DEBUG
+/* Print an IP header by using LWIP_DEBUGF
+ * @param p an IP packet, p->payload pointing to the IP header
+ */
+void
+ip_debug_print(struct pbuf *p)
+{
+  struct ip_hdr *iphdr = p->payload;
+  u8_t *payload;
+
+  payload = (u8_t *)iphdr + IP_HLEN;
+
+  LWIP_DEBUGF(IP_DEBUG, ("IP header:\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" |%2"S16_F" |  0x%02"X16_F" |     %5"U16_F"     | (v, hl, tos, len)\n",
+                    IPH_V(iphdr),
+                    IPH_HL(iphdr),
+                    IPH_TOS(iphdr),
+                    ntohs(IPH_LEN(iphdr))));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|    %5"U16_F"      |%"U16_F"%"U16_F"%"U16_F"|    %4"U16_F"   | (id, flags, offset)\n",
+                    ntohs(IPH_ID(iphdr)),
+                    ntohs(IPH_OFFSET(iphdr)) >> 15 & 1,
+                    ntohs(IPH_OFFSET(iphdr)) >> 14 & 1,
+                    ntohs(IPH_OFFSET(iphdr)) >> 13 & 1,
+                    ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3"U16_F"  |  %3"U16_F"  |    0x%04"X16_F"     | (ttl, proto, chksum)\n",
+                    IPH_TTL(iphdr),
+                    IPH_PROTO(iphdr),
+                    ntohs(IPH_CHKSUM(iphdr))));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  | (src)\n",
+                    ip4_addr1(&iphdr->src),
+                    ip4_addr2(&iphdr->src),
+                    ip4_addr3(&iphdr->src),
+                    ip4_addr4(&iphdr->src)));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  | (dest)\n",
+                    ip4_addr1(&iphdr->dest),
+                    ip4_addr2(&iphdr->dest),
+                    ip4_addr3(&iphdr->dest),
+                    ip4_addr4(&iphdr->dest)));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+}
+#endif /* IP_DEBUG */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/ip_addr.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/ip_addr.c
new file mode 100644
index 0000000..7a96c2f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/ip_addr.c
@@ -0,0 +1,84 @@
+/**
+ * @file
+ * This is the IPv4 address tools implementation.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+#include "lwip/ip_addr.h"
+#include "lwip/inet.h"
+#include "lwip/netif.h"
+
+#define IP_ADDR_ANY_VALUE 0x00000000UL
+#define IP_ADDR_BROADCAST_VALUE 0xffffffffUL
+
+/* used by IP_ADDR_ANY and IP_ADDR_BROADCAST in ip_addr.h */
+const struct ip_addr ip_addr_any = { IP_ADDR_ANY_VALUE };
+const struct ip_addr ip_addr_broadcast = { IP_ADDR_BROADCAST_VALUE };
+
+/**
+ * Determine if an address is a broadcast address on a network interface
+ *
+ * @param addr address to be checked
+ * @param netif the network interface against which the address is checked
+ * @return returns non-zero if the address is a broadcast address
+ */
+u8_t ip_addr_isbroadcast(struct ip_addr *addr, struct netif *netif)
+{
+  u32_t addr2test;
+
+  addr2test = addr->addr;
+  /* all ones (broadcast) or all zeroes (old skool broadcast) */
+  if ((~addr2test == IP_ADDR_ANY_VALUE) ||
+      (addr2test == IP_ADDR_ANY_VALUE))
+    return 1;
+  /* no broadcast support on this network interface? */
+  else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0)
+    /* the given address cannot be a broadcast address
+     * nor can we check against any broadcast addresses */
+    return 0;
+  /* address matches network interface address exactly? => no broadcast */
+  else if (addr2test == netif->ip_addr.addr)
+    return 0;
+  /*  on the same (sub) network... */
+  else if (ip_addr_netcmp(addr, &(netif->ip_addr), &(netif->netmask))
+         /* ...and host identifier bits are all ones? =>... */
+          && ((addr2test & ~netif->netmask.addr) ==
+           (IP_ADDR_BROADCAST_VALUE & ~netif->netmask.addr)))
+    /* => network broadcast address */
+    return 1;
+  else
+    return 0;
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/ip_frag.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/ip_frag.c
new file mode 100644
index 0000000..5cca281
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv4/ip_frag.c
@@ -0,0 +1,783 @@
+/**
+ * @file
+ * This is the IPv4 packet segmentation and reassembly implementation.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Jani Monoses 
+ *         Simon Goldschmidt
+ * original reassembly code by Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+#include "lwip/ip_frag.h"
+#include "lwip/ip.h"
+#include "lwip/inet.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/netif.h"
+#include "lwip/snmp.h"
+#include "lwip/stats.h"
+#include "lwip/icmp.h"
+
+#include 
+
+#if IP_REASSEMBLY
+/**
+ * The IP reassembly code currently has the following limitations:
+ * - IP header options are not supported
+ * - fragments must not overlap (e.g. due to different routes),
+ *   currently, overlapping or duplicate fragments are thrown away
+ *   if IP_REASS_CHECK_OVERLAP=1 (the default)!
+ *
+ * @todo: work with IP header options
+ */
+
+/** Setting this to 0, you can turn off checking the fragments for overlapping
+ * regions. The code gets a little smaller. Only use this if you know that
+ * overlapping won't occur on your network! */
+#ifndef IP_REASS_CHECK_OVERLAP
+#define IP_REASS_CHECK_OVERLAP 1
+#endif /* IP_REASS_CHECK_OVERLAP */
+
+/** Set to 0 to prevent freeing the oldest datagram when the reassembly buffer is
+ * full (IP_REASS_MAX_PBUFS pbufs are enqueued). The code gets a little smaller.
+ * Datagrams will be freed by timeout only. Especially useful when MEMP_NUM_REASSDATA
+ * is set to 1, so one datagram can be reassembled at a time, only. */
+#ifndef IP_REASS_FREE_OLDEST
+#define IP_REASS_FREE_OLDEST 1
+#endif /* IP_REASS_FREE_OLDEST */
+
+#define IP_REASS_FLAG_LASTFRAG 0x01
+
+/** This is a helper struct which holds the starting
+ * offset and the ending offset of this fragment to
+ * easily chain the fragments.
+ */
+struct ip_reass_helper {
+  struct pbuf *next_pbuf;
+  u16_t start;
+  u16_t end;
+};
+
+#define IP_ADDRESSES_AND_ID_MATCH(iphdrA, iphdrB)  \
+  (ip_addr_cmp(&(iphdrA)->src, &(iphdrB)->src) && \
+   ip_addr_cmp(&(iphdrA)->dest, &(iphdrB)->dest) && \
+   IPH_ID(iphdrA) == IPH_ID(iphdrB)) ? 1 : 0
+
+/* global variables */
+static struct ip_reassdata *reassdatagrams;
+static u16_t ip_reass_pbufcount;
+
+/* function prototypes */
+static void ip_reass_dequeue_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev);
+static int ip_reass_free_complete_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev);
+
+/**
+ * Reassembly timer base function
+ * for both NO_SYS == 0 and 1 (!).
+ *
+ * Should be called every 1000 msec (defined by IP_TMR_INTERVAL).
+ */
+void
+ip_reass_tmr(void)
+{
+  struct ip_reassdata *r, *prev = NULL;
+
+  r = reassdatagrams;
+  while (r != NULL) {
+    /* Decrement the timer. Once it reaches 0,
+     * clean up the incomplete fragment assembly */
+    if (r->timer > 0) {
+      r->timer--;
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer dec %"U16_F"\n",(u16_t)r->timer));
+      prev = r;
+      r = r->next;
+    } else {
+      /* reassembly timed out */
+      struct ip_reassdata *tmp;
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer timed out\n"));
+      tmp = r;
+      /* get the next pointer before freeing */
+      r = r->next;
+      /* free the helper struct and all enqueued pbufs */
+      ip_reass_free_complete_datagram(tmp, prev);
+     }
+   }
+}
+
+/**
+ * Free a datagram (struct ip_reassdata) and all its pbufs.
+ * Updates the total count of enqueued pbufs (ip_reass_pbufcount),
+ * SNMP counters and sends an ICMP time exceeded packet.
+ *
+ * @param ipr datagram to free
+ * @param prev the previous datagram in the linked list
+ * @return the number of pbufs freed
+ */
+static int
+ip_reass_free_complete_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev)
+{
+  int pbufs_freed = 0;
+  struct pbuf *p;
+  struct ip_reass_helper *iprh;
+
+  LWIP_ASSERT("prev != ipr", prev != ipr);
+  if (prev != NULL) {
+    LWIP_ASSERT("prev->next == ipr", prev->next == ipr);
+  }
+
+  snmp_inc_ipreasmfails();
+#if LWIP_ICMP
+  iprh = (struct ip_reass_helper *)ipr->p->payload;
+  if (iprh->start == 0) {
+    /* The first fragment was received, send ICMP time exceeded. */
+    /* First, de-queue the first pbuf from r->p. */
+    p = ipr->p;
+    ipr->p = iprh->next_pbuf;
+    /* Then, copy the original header into it. */
+    SMEMCPY(p->payload, &ipr->iphdr, IP_HLEN);
+    icmp_time_exceeded(p, ICMP_TE_FRAG);
+    pbufs_freed += pbuf_clen(p);
+    pbuf_free(p);
+  }
+#endif /* LWIP_ICMP */
+
+  /* First, free all received pbufs.  The individual pbufs need to be released
+     separately as they have not yet been chained */
+  p = ipr->p;
+  while (p != NULL) {
+    struct pbuf *pcur;
+    iprh = (struct ip_reass_helper *)p->payload;
+    pcur = p;
+    /* get the next pointer before freeing */
+    p = iprh->next_pbuf;
+    pbufs_freed += pbuf_clen(pcur);
+    pbuf_free(pcur);
+  }
+  /* Then, unchain the struct ip_reassdata from the list and free it. */
+  ip_reass_dequeue_datagram(ipr, prev);
+  LWIP_ASSERT("ip_reass_pbufcount >= clen", ip_reass_pbufcount >= pbufs_freed);
+  ip_reass_pbufcount -= pbufs_freed;
+
+  return pbufs_freed;
+}
+
+#if IP_REASS_FREE_OLDEST
+/**
+ * Free the oldest datagram to make room for enqueueing new fragments.
+ * The datagram 'fraghdr' belongs to is not freed!
+ *
+ * @param fraghdr IP header of the current fragment
+ * @param pbufs_needed number of pbufs needed to enqueue
+ *        (used for freeing other datagrams if not enough space)
+ * @return the number of pbufs freed
+ */
+static int
+ip_reass_remove_oldest_datagram(struct ip_hdr *fraghdr, int pbufs_needed)
+{
+  /* @todo Can't we simply remove the last datagram in the
+   *       linked list behind reassdatagrams?
+   */
+  struct ip_reassdata *r, *oldest, *prev;
+  int pbufs_freed = 0, pbufs_freed_current;
+  int other_datagrams;
+
+  /* Free datagrams until being allowed to enqueue 'pbufs_needed' pbufs,
+   * but don't free the datagram that 'fraghdr' belongs to! */
+  do {
+    oldest = NULL;
+    prev = NULL;
+    other_datagrams = 0;
+    r = reassdatagrams;
+    while (r != NULL) {
+      if (!IP_ADDRESSES_AND_ID_MATCH(&r->iphdr, fraghdr)) {
+        /* Not the same datagram as fraghdr */
+        other_datagrams++;
+        if (oldest == NULL) {
+          oldest = r;
+        } else if (r->timer <= oldest->timer) {
+          /* older than the previous oldest */
+          oldest = r;
+        }
+      }
+      if (r->next != NULL) {
+        prev = r;
+      }
+      r = r->next;
+    }
+    if (oldest != NULL) {
+      pbufs_freed_current = ip_reass_free_complete_datagram(oldest, prev);
+      pbufs_freed += pbufs_freed_current;
+    }
+  } while ((pbufs_freed < pbufs_needed) && (other_datagrams > 1));
+  return pbufs_freed;
+}
+#endif /* IP_REASS_FREE_OLDEST */
+
+/**
+ * Enqueues a new fragment into the fragment queue
+ * @param fraghdr points to the new fragments IP hdr
+ * @param clen number of pbufs needed to enqueue (used for freeing other datagrams if not enough space)
+ * @return A pointer to the queue location into which the fragment was enqueued
+ */
+static struct ip_reassdata*
+ip_reass_enqueue_new_datagram(struct ip_hdr *fraghdr, int clen)
+{
+  struct ip_reassdata* ipr;
+  /* No matching previous fragment found, allocate a new reassdata struct */
+  ipr = memp_malloc(MEMP_REASSDATA);
+  if (ipr == NULL) {
+#if IP_REASS_FREE_OLDEST
+    if (ip_reass_remove_oldest_datagram(fraghdr, clen) >= clen) {
+      ipr = memp_malloc(MEMP_REASSDATA);
+    }
+    if (ipr == NULL)
+#endif /* IP_REASS_FREE_OLDEST */
+    {
+      IPFRAG_STATS_INC(ip_frag.memerr);
+      LWIP_DEBUGF(IP_REASS_DEBUG,("Failed to alloc reassdata struct\n"));
+      return NULL;
+    }
+  }
+  memset(ipr, 0, sizeof(struct ip_reassdata));
+  ipr->timer = IP_REASS_MAXAGE;
+
+  /* enqueue the new structure to the front of the list */
+  ipr->next = reassdatagrams;
+  reassdatagrams = ipr;
+  /* copy the ip header for later tests and input */
+  /* @todo: no ip options supported? */
+  SMEMCPY(&(ipr->iphdr), fraghdr, IP_HLEN);
+  return ipr;
+}
+
+/**
+ * Dequeues a datagram from the datagram queue. Doesn't deallocate the pbufs.
+ * @param ipr points to the queue entry to dequeue
+ */
+static void
+ip_reass_dequeue_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev)
+{
+
+  /* dequeue the reass struct  */
+  if (reassdatagrams == ipr) {
+    /* it was the first in the list */
+    reassdatagrams = ipr->next;
+  } else {
+    /* it wasn't the first, so it must have a valid 'prev' */
+    LWIP_ASSERT("sanity check linked list", prev != NULL);
+    prev->next = ipr->next;
+  }
+
+  /* now we can free the ip_reass struct */
+  memp_free(MEMP_REASSDATA, ipr);
+}
+
+/**
+ * Chain a new pbuf into the pbuf list that composes the datagram.  The pbuf list
+ * will grow over time as  new pbufs are rx.
+ * Also checks that the datagram passes basic continuity checks (if the last
+ * fragment was received at least once).
+ * @param root_p points to the 'root' pbuf for the current datagram being assembled.
+ * @param new_p points to the pbuf for the current fragment
+ * @return 0 if invalid, >0 otherwise
+ */
+static int
+ip_reass_chain_frag_into_datagram_and_validate(struct ip_reassdata *ipr, struct pbuf *new_p)
+{
+  struct ip_reass_helper *iprh, *iprh_tmp, *iprh_prev=NULL;
+  struct pbuf *q;
+  u16_t offset,len;
+  struct ip_hdr *fraghdr;
+  int valid = 1;
+
+  /* Extract length and fragment offset from current fragment */
+  fraghdr = (struct ip_hdr*)new_p->payload;
+  len = ntohs(IPH_LEN(fraghdr)) - IPH_HL(fraghdr) * 4;
+  offset = (ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) * 8;
+
+  /* overwrite the fragment's ip header from the pbuf with our helper struct,
+   * and setup the embedded helper structure. */
+  /* make sure the struct ip_reass_helper fits into the IP header */
+  LWIP_ASSERT("sizeof(struct ip_reass_helper) <= IP_HLEN",
+              sizeof(struct ip_reass_helper) <= IP_HLEN);
+  iprh = (struct ip_reass_helper*)new_p->payload;
+  iprh->next_pbuf = NULL;
+  iprh->start = offset;
+  iprh->end = offset + len;
+
+  /* Iterate through until we either get to the end of the list (append),
+   * or we find on with a larger offset (insert). */
+  for (q = ipr->p; q != NULL;) {
+    iprh_tmp = (struct ip_reass_helper*)q->payload;
+    if (iprh->start < iprh_tmp->start) {
+      /* the new pbuf should be inserted before this */
+      iprh->next_pbuf = q;
+      if (iprh_prev != NULL) {
+        /* not the fragment with the lowest offset */
+#if IP_REASS_CHECK_OVERLAP
+        if ((iprh->start < iprh_prev->end) || (iprh->end > iprh_tmp->start)) {
+          /* fragment overlaps with previous or following, throw away */
+          goto freepbuf;
+        }
+#endif /* IP_REASS_CHECK_OVERLAP */
+        iprh_prev->next_pbuf = new_p;
+      } else {
+        /* fragment with the lowest offset */
+        ipr->p = new_p;
+      }
+      break;
+    } else if(iprh->start == iprh_tmp->start) {
+      /* received the same datagram twice: no need to keep the datagram */
+      goto freepbuf;
+#if IP_REASS_CHECK_OVERLAP
+    } else if(iprh->start < iprh_tmp->end) {
+      /* overlap: no need to keep the new datagram */
+      goto freepbuf;
+#endif /* IP_REASS_CHECK_OVERLAP */
+    } else {
+      /* Check if the fragments received so far have no wholes. */
+      if (iprh_prev != NULL) {
+        if (iprh_prev->end != iprh_tmp->start) {
+          /* There is a fragment missing between the current
+           * and the previous fragment */
+          valid = 0;
+        }
+      }
+    }
+    q = iprh_tmp->next_pbuf;
+    iprh_prev = iprh_tmp;
+  }
+
+  /* If q is NULL, then we made it to the end of the list. Determine what to do now */
+  if (q == NULL) {
+    if (iprh_prev != NULL) {
+      /* this is (for now), the fragment with the highest offset:
+       * chain it to the last fragment */
+#if IP_REASS_CHECK_OVERLAP
+      LWIP_ASSERT("check fragments don't overlap", iprh_prev->end <= iprh->start);
+#endif /* IP_REASS_CHECK_OVERLAP */
+      iprh_prev->next_pbuf = new_p;
+      if (iprh_prev->end != iprh->start) {
+        valid = 0;
+      }
+    } else {
+#if IP_REASS_CHECK_OVERLAP
+      LWIP_ASSERT("no previous fragment, this must be the first fragment!",
+        ipr->p == NULL);
+#endif /* IP_REASS_CHECK_OVERLAP */
+      /* this is the first fragment we ever received for this ip datagram */
+      ipr->p = new_p;
+    }
+  }
+
+  /* At this point, the validation part begins: */
+  /* If we already received the last fragment */
+  if ((ipr->flags & IP_REASS_FLAG_LASTFRAG) != 0) {
+    /* and had no wholes so far */
+    if (valid) {
+      /* then check if the rest of the fragments is here */
+      /* Check if the queue starts with the first datagram */
+      if (((struct ip_reass_helper*)ipr->p->payload)->start != 0) {
+        valid = 0;
+      } else {
+        /* and check that there are no wholes after this datagram */
+        iprh_prev = iprh;
+        q = iprh->next_pbuf;
+        while (q != NULL) {
+          iprh = (struct ip_reass_helper*)q->payload;
+          if (iprh_prev->end != iprh->start) {
+            valid = 0;
+            break;
+          }
+          iprh_prev = iprh;
+          q = iprh->next_pbuf;
+        }
+        /* if still valid, all fragments are received
+         * (because to the MF==0 already arrived */
+        if (valid) {
+          LWIP_ASSERT("sanity check", ipr->p != NULL);
+          LWIP_ASSERT("sanity check",
+            ((struct ip_reass_helper*)ipr->p->payload) != iprh);
+          LWIP_ASSERT("validate_datagram:next_pbuf!=NULL",
+            iprh->next_pbuf == NULL);
+          LWIP_ASSERT("validate_datagram:datagram end!=datagram len",
+            iprh->end == ipr->datagram_len);
+        }
+      }
+    }
+    /* If valid is 0 here, there are some fragments missing in the middle
+     * (since MF == 0 has already arrived). Such datagrams simply time out if
+     * no more fragments are received... */
+    return valid;
+  }
+  /* If we come here, not all fragments were received, yet! */
+  return 0; /* not yet valid! */
+#if IP_REASS_CHECK_OVERLAP
+freepbuf:
+  ip_reass_pbufcount -= pbuf_clen(new_p);
+  pbuf_free(new_p);
+  return 0;
+#endif /* IP_REASS_CHECK_OVERLAP */
+}
+
+/**
+ * Reassembles incoming IP fragments into an IP datagram.
+ *
+ * @param p points to a pbuf chain of the fragment
+ * @return NULL if reassembly is incomplete, ? otherwise
+ */
+struct pbuf *
+ip_reass(struct pbuf *p)
+{
+  struct pbuf *r;
+  struct ip_hdr *fraghdr;
+  struct ip_reassdata *ipr;
+  struct ip_reass_helper *iprh;
+  u16_t offset, len;
+  u8_t clen;
+  struct ip_reassdata *ipr_prev = NULL;
+
+  IPFRAG_STATS_INC(ip_frag.recv);
+  snmp_inc_ipreasmreqds();
+
+  fraghdr = (struct ip_hdr*)p->payload;
+
+  if ((IPH_HL(fraghdr) * 4) != IP_HLEN) {
+    LWIP_DEBUGF(IP_REASS_DEBUG,("ip_reass: IP options currently not supported!\n"));
+    IPFRAG_STATS_INC(ip_frag.err);
+    goto nullreturn;
+  }
+
+  offset = (ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) * 8;
+  len = ntohs(IPH_LEN(fraghdr)) - IPH_HL(fraghdr) * 4;
+
+  /* Check if we are allowed to enqueue more datagrams. */
+  clen = pbuf_clen(p);
+  if ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS) {
+#if IP_REASS_FREE_OLDEST
+    if (!ip_reass_remove_oldest_datagram(fraghdr, clen) ||
+        ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS))
+#endif /* IP_REASS_FREE_OLDEST */
+    {
+      /* No datagram could be freed and still too many pbufs enqueued */
+      LWIP_DEBUGF(IP_REASS_DEBUG,("ip_reass: Overflow condition: pbufct=%d, clen=%d, MAX=%d\n",
+        ip_reass_pbufcount, clen, IP_REASS_MAX_PBUFS));
+      IPFRAG_STATS_INC(ip_frag.memerr);
+      /* @todo: send ICMP time exceeded here? */
+      /* drop this pbuf */
+      goto nullreturn;
+    }
+  }
+
+  /* Look for the datagram the fragment belongs to in the current datagram queue,
+   * remembering the previous in the queue for later dequeueing. */
+  for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) {
+    /* Check if the incoming fragment matches the one currently present
+       in the reassembly buffer. If so, we proceed with copying the
+       fragment into the buffer. */
+    if (IP_ADDRESSES_AND_ID_MATCH(&ipr->iphdr, fraghdr)) {
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: matching previous fragment ID=%"X16_F"\n",
+        ntohs(IPH_ID(fraghdr))));
+      IPFRAG_STATS_INC(ip_frag.cachehit);
+      break;
+    }
+    ipr_prev = ipr;
+  }
+
+  if (ipr == NULL) {
+  /* Enqueue a new datagram into the datagram queue */
+    ipr = ip_reass_enqueue_new_datagram(fraghdr, clen);
+    /* Bail if unable to enqueue */
+    if(ipr == NULL) {
+      goto nullreturn;
+    }
+  } else {
+    if (((ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) &&
+      ((ntohs(IPH_OFFSET(&ipr->iphdr)) & IP_OFFMASK) != 0)) {
+      /* ipr->iphdr is not the header from the first fragment, but fraghdr is
+       * -> copy fraghdr into ipr->iphdr since we want to have the header
+       * of the first fragment (for ICMP time exceeded and later, for copying
+       * all options, if supported)*/
+      SMEMCPY(&ipr->iphdr, fraghdr, IP_HLEN);
+    }
+  }
+  /* Track the current number of pbufs current 'in-flight', in order to limit
+  the number of fragments that may be enqueued at any one time */
+  ip_reass_pbufcount += clen;
+
+  /* At this point, we have either created a new entry or pointing
+   * to an existing one */
+
+  /* check for 'no more fragments', and update queue entry*/
+  if ((ntohs(IPH_OFFSET(fraghdr)) & IP_MF) == 0) {
+    ipr->flags |= IP_REASS_FLAG_LASTFRAG;
+    ipr->datagram_len = offset + len;
+    LWIP_DEBUGF(IP_REASS_DEBUG,
+     ("ip_reass: last fragment seen, total len %"S16_F"\n",
+      ipr->datagram_len));
+  }
+  /* find the right place to insert this pbuf */
+  /* @todo: trim pbufs if fragments are overlapping */
+  if (ip_reass_chain_frag_into_datagram_and_validate(ipr, p)) {
+    /* the totally last fragment (flag more fragments = 0) was received at least
+     * once AND all fragments are received */
+    ipr->datagram_len += IP_HLEN;
+
+    /* save the second pbuf before copying the header over the pointer */
+    r = ((struct ip_reass_helper*)ipr->p->payload)->next_pbuf;
+
+    /* copy the original ip header back to the first pbuf */
+    fraghdr = (struct ip_hdr*)(ipr->p->payload);
+    SMEMCPY(fraghdr, &ipr->iphdr, IP_HLEN);
+    IPH_LEN_SET(fraghdr, htons(ipr->datagram_len));
+    IPH_OFFSET_SET(fraghdr, 0);
+    IPH_CHKSUM_SET(fraghdr, 0);
+    /* @todo: do we need to set calculate the correct checksum? */
+    IPH_CHKSUM_SET(fraghdr, inet_chksum(fraghdr, IP_HLEN));
+
+    p = ipr->p;
+
+    /* chain together the pbufs contained within the reass_data list. */
+    while(r != NULL) {
+      iprh = (struct ip_reass_helper*)r->payload;
+
+      /* hide the ip header for every succeding fragment */
+      pbuf_header(r, -IP_HLEN);
+      pbuf_cat(p, r);
+      r = iprh->next_pbuf;
+    }
+    /* release the sources allocate for the fragment queue entry */
+    ip_reass_dequeue_datagram(ipr, ipr_prev);
+
+    /* and adjust the number of pbufs currently queued for reassembly. */
+    ip_reass_pbufcount -= pbuf_clen(p);
+
+    /* Return the pbuf chain */
+    return p;
+  }
+  /* the datagram is not (yet?) reassembled completely */
+  LWIP_DEBUGF(IP_REASS_DEBUG,("ip_reass_pbufcount: %d out\n", ip_reass_pbufcount));
+  return NULL;
+
+nullreturn:
+  LWIP_DEBUGF(IP_REASS_DEBUG,("ip_reass: nullreturn\n"));
+  IPFRAG_STATS_INC(ip_frag.drop);
+  pbuf_free(p);
+  return NULL;
+}
+#endif /* IP_REASSEMBLY */
+
+#if IP_FRAG
+#if IP_FRAG_USES_STATIC_BUF
+static u8_t buf[LWIP_MEM_ALIGN_SIZE(IP_FRAG_MAX_MTU)];
+#endif /* IP_FRAG_USES_STATIC_BUF */
+
+/**
+ * Fragment an IP datagram if too large for the netif.
+ *
+ * Chop the datagram in MTU sized chunks and send them in order
+ * by using a fixed size static memory buffer (PBUF_REF) or
+ * point PBUF_REFs into p (depending on IP_FRAG_USES_STATIC_BUF).
+ *
+ * @param p ip packet to send
+ * @param netif the netif on which to send
+ * @param dest destination ip address to which to send
+ *
+ * @return ERR_OK if sent successfully, err_t otherwise
+ */
+err_t
+ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest)
+{
+  struct pbuf *rambuf;
+#if IP_FRAG_USES_STATIC_BUF
+  struct pbuf *header;
+#else
+  struct pbuf *newpbuf;
+  struct ip_hdr *original_iphdr;
+#endif
+  struct ip_hdr *iphdr;
+  u16_t nfb;
+  u16_t left, cop;
+  u16_t mtu = netif->mtu;
+  u16_t ofo, omf;
+  u16_t last;
+  u16_t poff = IP_HLEN;
+  u16_t tmp;
+#if !IP_FRAG_USES_STATIC_BUF
+  u16_t newpbuflen = 0;
+  u16_t left_to_copy;
+#endif
+
+  /* Get a RAM based MTU sized pbuf */
+#if IP_FRAG_USES_STATIC_BUF
+  /* When using a static buffer, we use a PBUF_REF, which we will
+   * use to reference the packet (without link header).
+   * Layer and length is irrelevant.
+   */
+  rambuf = pbuf_alloc(PBUF_LINK, 0, PBUF_REF);
+  if (rambuf == NULL) {
+    LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_frag: pbuf_alloc(PBUF_LINK, 0, PBUF_REF) failed\n"));
+    return ERR_MEM;
+  }
+  rambuf->tot_len = rambuf->len = mtu;
+  rambuf->payload = LWIP_MEM_ALIGN((void *)buf);
+
+  /* Copy the IP header in it */
+  iphdr = rambuf->payload;
+  SMEMCPY(iphdr, p->payload, IP_HLEN);
+#else /* IP_FRAG_USES_STATIC_BUF */
+  original_iphdr = p->payload;
+  iphdr = original_iphdr;
+#endif /* IP_FRAG_USES_STATIC_BUF */
+
+  /* Save original offset */
+  tmp = ntohs(IPH_OFFSET(iphdr));
+  ofo = tmp & IP_OFFMASK;
+  omf = tmp & IP_MF;
+
+  left = p->tot_len - IP_HLEN;
+
+  nfb = (mtu - IP_HLEN) / 8;
+
+  while (left) {
+    last = (left <= mtu - IP_HLEN);
+
+    /* Set new offset and MF flag */
+    tmp = omf | (IP_OFFMASK & (ofo));
+    if (!last)
+      tmp = tmp | IP_MF;
+
+    /* Fill this fragment */
+    cop = last ? left : nfb * 8;
+
+#if IP_FRAG_USES_STATIC_BUF
+    poff += pbuf_copy_partial(p, (u8_t*)iphdr + IP_HLEN, cop, poff);
+#else /* IP_FRAG_USES_STATIC_BUF */
+    /* When not using a static buffer, create a chain of pbufs.
+     * The first will be a PBUF_RAM holding the link and IP header.
+     * The rest will be PBUF_REFs mirroring the pbuf chain to be fragged,
+     * but limited to the size of an mtu.
+     */
+    rambuf = pbuf_alloc(PBUF_LINK, IP_HLEN, PBUF_RAM);
+    if (rambuf == NULL) {
+      return ERR_MEM;
+    }
+    LWIP_ASSERT("this needs a pbuf in one piece!",
+                (p->len >= (IP_HLEN)));
+    SMEMCPY(rambuf->payload, original_iphdr, IP_HLEN);
+    iphdr = rambuf->payload;
+
+    /* Can just adjust p directly for needed offset. */
+    p->payload = (u8_t *)p->payload + poff;
+    p->len -= poff;
+
+    left_to_copy = cop;
+    while (left_to_copy) {
+      newpbuflen = (left_to_copy < p->len) ? left_to_copy : p->len;
+      /* Is this pbuf already empty? */
+      if (!newpbuflen) {
+        p = p->next;
+        continue;
+      }
+      newpbuf = pbuf_alloc(PBUF_RAW, 0, PBUF_REF);
+      if (newpbuf == NULL) {
+        pbuf_free(rambuf);
+        return ERR_MEM;
+      }
+      /* Mirror this pbuf, although we might not need all of it. */
+      newpbuf->payload = p->payload;
+      newpbuf->len = newpbuf->tot_len = newpbuflen;
+      /* Add it to end of rambuf's chain, but using pbuf_cat, not pbuf_chain
+       * so that it is removed when pbuf_dechain is later called on rambuf.
+       */
+      pbuf_cat(rambuf, newpbuf);
+      left_to_copy -= newpbuflen;
+      if (left_to_copy)
+        p = p->next;
+    }
+    poff = newpbuflen;
+#endif /* IP_FRAG_USES_STATIC_BUF */
+
+    /* Correct header */
+    IPH_OFFSET_SET(iphdr, htons(tmp));
+    IPH_LEN_SET(iphdr, htons(cop + IP_HLEN));
+    IPH_CHKSUM_SET(iphdr, 0);
+    IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
+
+#if IP_FRAG_USES_STATIC_BUF
+    if (last)
+      pbuf_realloc(rambuf, left + IP_HLEN);
+
+    /* This part is ugly: we alloc a RAM based pbuf for
+     * the link level header for each chunk and then
+     * free it.A PBUF_ROM style pbuf for which pbuf_header
+     * worked would make things simpler.
+     */
+    header = pbuf_alloc(PBUF_LINK, 0, PBUF_RAM);
+    if (header != NULL) {
+      pbuf_chain(header, rambuf);
+      netif->output(netif, header, dest);
+      IPFRAG_STATS_INC(ip_frag.xmit);
+      snmp_inc_ipfragcreates();
+      pbuf_free(header);
+    } else {
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_frag: pbuf_alloc() for header failed\n"));
+      pbuf_free(rambuf);
+      return ERR_MEM;
+    }
+#else /* IP_FRAG_USES_STATIC_BUF */
+    /* No need for separate header pbuf - we allowed room for it in rambuf
+     * when allocated.
+     */
+    netif->output(netif, rambuf, dest);
+    IPFRAG_STATS_INC(ip_frag.xmit);
+
+    /* Unfortunately we can't reuse rambuf - the hardware may still be
+     * using the buffer. Instead we free it (and the ensuing chain) and
+     * recreate it next time round the loop. If we're lucky the hardware
+     * will have already sent the packet, the free will really free, and
+     * there will be zero memory penalty.
+     */
+
+    pbuf_free(rambuf);
+#endif /* IP_FRAG_USES_STATIC_BUF */
+    left -= cop;
+    ofo += nfb;
+  }
+#if IP_FRAG_USES_STATIC_BUF
+  pbuf_free(rambuf);
+#endif /* IP_FRAG_USES_STATIC_BUF */
+  snmp_inc_ipfragoks();
+  return ERR_OK;
+}
+#endif /* IP_FRAG */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv6/README b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv6/README
new file mode 100644
index 0000000..a59caef
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv6/README
@@ -0,0 +1 @@
+IPv6 support in lwIP is very experimental.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv6/icmp6.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv6/icmp6.c
new file mode 100644
index 0000000..1661ace
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv6/icmp6.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* Some ICMP messages should be passed to the transport protocols. This
+   is not implemented. */
+
+#include "lwip/opt.h"
+
+#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/icmp.h"
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+#include "lwip/def.h"
+#include "lwip/stats.h"
+
+void
+icmp_input(struct pbuf *p, struct netif *inp)
+{
+  u8_t type;
+  struct icmp_echo_hdr *iecho;
+  struct ip_hdr *iphdr;
+  struct ip_addr tmpaddr;
+
+  ICMP_STATS_INC(icmp.recv);
+
+  /* TODO: check length before accessing payload! */
+
+  type = ((u8_t *)p->payload)[0];
+
+  switch (type) {
+  case ICMP6_ECHO:
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
+
+    if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n"));
+
+      pbuf_free(p);
+      ICMP_STATS_INC(icmp.lenerr);
+      return;
+    }
+    iecho = p->payload;
+    iphdr = (struct ip_hdr *)((u8_t *)p->payload - IP_HLEN);
+    if (inet_chksum_pbuf(p) != 0) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%"X16_F")\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len)));
+      ICMP_STATS_INC(icmp.chkerr);
+    /*      return;*/
+    }
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp: p->len %"S16_F" p->tot_len %"S16_F"\n", p->len, p->tot_len));
+    ip_addr_set(&tmpaddr, &(iphdr->src));
+    ip_addr_set(&(iphdr->src), &(iphdr->dest));
+    ip_addr_set(&(iphdr->dest), &tmpaddr);
+    iecho->type = ICMP6_ER;
+    /* adjust the checksum */
+    if (iecho->chksum >= htons(0xffff - (ICMP6_ECHO << 8))) {
+      iecho->chksum += htons(ICMP6_ECHO << 8) + 1;
+    } else {
+      iecho->chksum += htons(ICMP6_ECHO << 8);
+    }
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%"X16_F")\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len)));
+    ICMP_STATS_INC(icmp.xmit);
+
+    /*    LWIP_DEBUGF("icmp: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len);*/
+    ip_output_if (p, &(iphdr->src), IP_HDRINCL,
+     iphdr->hoplim, IP_PROTO_ICMP, inp);
+    break;
+  default:
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" not supported.\n", (s16_t)type));
+    ICMP_STATS_INC(icmp.proterr);
+    ICMP_STATS_INC(icmp.drop);
+  }
+
+  pbuf_free(p);
+}
+
+void
+icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  struct icmp_dur_hdr *idur;
+
+  /* @todo: can this be PBUF_LINK instead of PBUF_IP? */
+  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
+  /* ICMP header + IP header + 8 bytes of data */
+  if (q == NULL) {
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_dest_unreach: failed to allocate pbuf for ICMP packet.\n"));
+    pbuf_free(p);
+    return;
+  }
+  LWIP_ASSERT("check that first pbuf can hold icmp message",
+             (q->len >= (8 + IP_HLEN + 8)));
+
+  iphdr = p->payload;
+
+  idur = q->payload;
+  idur->type = (u8_t)ICMP6_DUR;
+  idur->icode = (u8_t)t;
+
+  SMEMCPY((u8_t *)q->payload + 8, p->payload, IP_HLEN + 8);
+
+  /* calculate checksum */
+  idur->chksum = 0;
+  idur->chksum = inet_chksum(idur, q->len);
+  ICMP_STATS_INC(icmp.xmit);
+
+  ip_output(q, NULL,
+      (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+void
+icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  struct icmp_te_hdr *tehdr;
+
+  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded\n"));
+
+  /* @todo: can this be PBUF_LINK instead of PBUF_IP? */
+  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
+  /* ICMP header + IP header + 8 bytes of data */
+  if (q == NULL) {
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_dest_unreach: failed to allocate pbuf for ICMP packet.\n"));
+    pbuf_free(p);
+    return;
+  }
+  LWIP_ASSERT("check that first pbuf can hold icmp message",
+             (q->len >= (8 + IP_HLEN + 8)));
+
+  iphdr = p->payload;
+
+  tehdr = q->payload;
+  tehdr->type = (u8_t)ICMP6_TE;
+  tehdr->icode = (u8_t)t;
+
+  /* copy fields from original packet */
+  SMEMCPY((u8_t *)q->payload + 8, (u8_t *)p->payload, IP_HLEN + 8);
+
+  /* calculate checksum */
+  tehdr->chksum = 0;
+  tehdr->chksum = inet_chksum(tehdr, q->len);
+  ICMP_STATS_INC(icmp.xmit);
+  ip_output(q, NULL,
+      (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+#endif /* LWIP_ICMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv6/inet6.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv6/inet6.c
new file mode 100644
index 0000000..8214f05
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv6/inet6.c
@@ -0,0 +1,163 @@
+/**
+ * @file
+ * Functions common to all TCP/IPv6 modules, such as the Internet checksum and the
+ * byte order functions.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/inet.h"
+
+/* chksum:
+ *
+ * Sums up all 16 bit words in a memory portion. Also includes any odd byte.
+ * This function is used by the other checksum functions.
+ *
+ * For now, this is not optimized. Must be optimized for the particular processor
+ * arcitecture on which it is to run. Preferebly coded in assembler.
+ */
+
+static u32_t
+chksum(void *dataptr, u16_t len)
+{
+  u16_t *sdataptr = dataptr;
+  u32_t acc;
+  
+  
+  for(acc = 0; len > 1; len -= 2) {
+    acc += *sdataptr++;
+  }
+
+  /* add up any odd byte */
+  if (len == 1) {
+    acc += htons((u16_t)(*(u8_t *)dataptr) << 8);
+  }
+
+  return acc;
+
+}
+
+/* inet_chksum_pseudo:
+ *
+ * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
+ */
+
+u16_t
+inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u32_t proto_len)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped, i;
+
+  acc = 0;
+  swapped = 0;
+  for(q = p; q != NULL; q = q->next) {    
+    acc += chksum(q->payload, q->len);
+    while (acc >> 16) {
+      acc = (acc & 0xffff) + (acc >> 16);
+    }
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+    }
+  }
+
+  if (swapped) {
+    acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+  }
+  
+  for(i = 0; i < 8; i++) {
+    acc += ((u16_t *)src->addr)[i] & 0xffff;
+    acc += ((u16_t *)dest->addr)[i] & 0xffff;
+    while (acc >> 16) {
+      acc = (acc & 0xffff) + (acc >> 16);
+    }
+  }
+  acc += (u16_t)htons((u16_t)proto);
+  acc += ((u16_t *)&proto_len)[0] & 0xffff;
+  acc += ((u16_t *)&proto_len)[1] & 0xffff;
+
+  while (acc >> 16) {
+    acc = (acc & 0xffff) + (acc >> 16);
+  }
+  return ~(acc & 0xffff);
+}
+
+/* inet_chksum:
+ *
+ * Calculates the Internet checksum over a portion of memory. Used primarely for IP
+ * and ICMP.
+ */
+
+u16_t
+inet_chksum(void *dataptr, u16_t len)
+{
+  u32_t acc, sum;
+
+  acc = chksum(dataptr, len);
+  sum = (acc & 0xffff) + (acc >> 16);
+  sum += (sum >> 16);
+  return ~(sum & 0xffff);
+}
+
+u16_t
+inet_chksum_pbuf(struct pbuf *p)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped;
+  
+  acc = 0;
+  swapped = 0;
+  for(q = p; q != NULL; q = q->next) {
+    acc += chksum(q->payload, q->len);
+    while (acc >> 16) {
+      acc = (acc & 0xffff) + (acc >> 16);
+    }    
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = (acc & 0xff << 8) | (acc & 0xff00 >> 8);
+    }
+  }
+ 
+  if (swapped) {
+    acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+  }
+  return ~(acc & 0xffff);
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv6/ip6.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv6/ip6.c
new file mode 100644
index 0000000..46bc3ad
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv6/ip6.c
@@ -0,0 +1,375 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+
+/* ip.c
+ *
+ * This is the code for the IP layer for IPv6.
+ *
+ */
+
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/ip.h"
+#include "lwip/inet.h"
+#include "lwip/netif.h"
+#include "lwip/icmp.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+
+/* ip_init:
+ *
+ * Initializes the IP layer.
+ */
+
+void
+ip_init(void)
+{
+}
+
+/* ip_route:
+ *
+ * Finds the appropriate network interface for a given IP address. It searches the
+ * list of network interfaces linearly. A match is found if the masked IP address of
+ * the network interface equals the masked IP address given to the function.
+ */
+
+struct netif *
+ip_route(struct ip_addr *dest)
+{
+  struct netif *netif;
+
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+    if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) {
+      return netif;
+    }
+  }
+
+  return netif_default;
+}
+
+/* ip_forward:
+ *
+ * Forwards an IP packet. It finds an appropriate route for the packet, decrements
+ * the TTL value of the packet, adjusts the checksum and outputs the packet on the
+ * appropriate interface.
+ */
+
+static void
+ip_forward(struct pbuf *p, struct ip_hdr *iphdr)
+{
+  struct netif *netif;
+
+  PERF_START;
+
+  if ((netif = ip_route((struct ip_addr *)&(iphdr->dest))) == NULL) {
+
+    LWIP_DEBUGF(IP_DEBUG, ("ip_input: no forwarding route found for "));
+#if IP_DEBUG
+    ip_addr_debug_print(IP_DEBUG, ((struct ip_addr *)&(iphdr->dest)));
+#endif /* IP_DEBUG */
+    LWIP_DEBUGF(IP_DEBUG, ("\n"));
+    pbuf_free(p);
+    return;
+  }
+  /* Decrement TTL and send ICMP if ttl == 0. */
+  if (--iphdr->hoplim == 0) {
+#if LWIP_ICMP
+    /* Don't send ICMP messages in response to ICMP messages */
+    if (iphdr->nexthdr != IP_PROTO_ICMP) {
+      icmp_time_exceeded(p, ICMP_TE_TTL);
+    }
+#endif /* LWIP_ICMP */
+    pbuf_free(p);
+    return;
+  }
+
+  /* Incremental update of the IP checksum. */
+  /*  if (iphdr->chksum >= htons(0xffff - 0x100)) {
+    iphdr->chksum += htons(0x100) + 1;
+  } else {
+    iphdr->chksum += htons(0x100);
+    }*/
+
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to "));
+#if IP_DEBUG
+  ip_addr_debug_print(IP_DEBUG, ((struct ip_addr *)&(iphdr->dest)));
+#endif /* IP_DEBUG */
+  LWIP_DEBUGF(IP_DEBUG, ("\n"));
+
+  IP_STATS_INC(ip.fw);
+  IP_STATS_INC(ip.xmit);
+
+  PERF_STOP("ip_forward");
+
+  netif->output(netif, p, (struct ip_addr *)&(iphdr->dest));
+}
+
+/* ip_input:
+ *
+ * This function is called by the network interface device driver when an IP packet is
+ * received. The function does the basic checks of the IP header such as packet size
+ * being at least larger than the header size etc. If the packet was not destined for
+ * us, the packet is forwarded (using ip_forward). The IP checksum is always checked.
+ *
+ * Finally, the packet is sent to the upper layer protocol input function.
+ */
+
+void
+ip_input(struct pbuf *p, struct netif *inp) {
+  struct ip_hdr *iphdr;
+  struct netif *netif;
+
+
+  PERF_START;
+
+#if IP_DEBUG
+  ip_debug_print(p);
+#endif /* IP_DEBUG */
+
+
+  IP_STATS_INC(ip.recv);
+
+  /* identify the IP header */
+  iphdr = p->payload;
+
+
+  if (iphdr->v != 6) {
+    LWIP_DEBUGF(IP_DEBUG, ("IP packet dropped due to bad version number\n"));
+#if IP_DEBUG
+    ip_debug_print(p);
+#endif /* IP_DEBUG */
+    pbuf_free(p);
+    IP_STATS_INC(ip.err);
+    IP_STATS_INC(ip.drop);
+    return;
+  }
+
+  /* is this packet for us? */
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+#if IP_DEBUG
+    LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest "));
+    ip_addr_debug_print(IP_DEBUG, ((struct ip_addr *)&(iphdr->dest)));
+    LWIP_DEBUGF(IP_DEBUG, ("netif->ip_addr "));
+    ip_addr_debug_print(IP_DEBUG, ((struct ip_addr *)&(iphdr->dest)));
+    LWIP_DEBUGF(IP_DEBUG, ("\n"));
+#endif /* IP_DEBUG */
+    if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr))) {
+      break;
+    }
+  }
+
+
+  if (netif == NULL) {
+    /* packet not for us, route or discard */
+#if IP_FORWARD
+    ip_forward(p, iphdr);
+#endif
+    pbuf_free(p);
+    return;
+  }
+
+  pbuf_realloc(p, IP_HLEN + ntohs(iphdr->len));
+
+  /* send to upper layers */
+#if IP_DEBUG
+  /*  LWIP_DEBUGF("ip_input: \n");
+  ip_debug_print(p);
+  LWIP_DEBUGF("ip_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len);*/
+#endif /* IP_DEBUG */
+
+  if(pbuf_header(p, -IP_HLEN)) {
+    LWIP_ASSERT("Can't move over header in packet", 0);
+    return;
+  }
+
+  switch (iphdr->nexthdr) {
+  case IP_PROTO_UDP:
+    udp_input(p, inp);
+    break;
+  case IP_PROTO_TCP:
+    tcp_input(p, inp);
+    break;
+#if LWIP_ICMP
+  case IP_PROTO_ICMP:
+    icmp_input(p, inp);
+    break;
+#endif /* LWIP_ICMP */
+  default:
+#if LWIP_ICMP
+    /* send ICMP destination protocol unreachable */
+    icmp_dest_unreach(p, ICMP_DUR_PROTO);
+#endif /* LWIP_ICMP */
+    pbuf_free(p);
+    LWIP_DEBUGF(IP_DEBUG, ("Unsupported transport protocol %"U16_F"\n",
+          iphdr->nexthdr));
+
+    IP_STATS_INC(ip.proterr);
+    IP_STATS_INC(ip.drop);
+  }
+  PERF_STOP("ip_input");
+}
+
+
+/* ip_output_if:
+ *
+ * Sends an IP packet on a network interface. This function constructs the IP header
+ * and calculates the IP header checksum. If the source IP address is NULL,
+ * the IP address of the outgoing network interface is filled in as source address.
+ */
+
+err_t
+ip_output_if (struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+       u8_t ttl,
+       u8_t proto, struct netif *netif)
+{
+  struct ip_hdr *iphdr;
+
+  PERF_START;
+
+  LWIP_DEBUGF(IP_DEBUG, ("len %"U16_F" tot_len %"U16_F"\n", p->len, p->tot_len));
+  if (pbuf_header(p, IP_HLEN)) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_output: not enough room for IP header in pbuf\n"));
+    IP_STATS_INC(ip.err);
+
+    return ERR_BUF;
+  }
+  LWIP_DEBUGF(IP_DEBUG, ("len %"U16_F" tot_len %"U16_F"\n", p->len, p->tot_len));
+
+  iphdr = p->payload;
+
+
+  if (dest != IP_HDRINCL) {
+    LWIP_DEBUGF(IP_DEBUG, ("!IP_HDRLINCL\n"));
+    iphdr->hoplim = ttl;
+    iphdr->nexthdr = proto;
+    iphdr->len = htons(p->tot_len - IP_HLEN);
+    ip_addr_set(&(iphdr->dest), dest);
+
+    iphdr->v = 6;
+
+    if (ip_addr_isany(src)) {
+      ip_addr_set(&(iphdr->src), &(netif->ip_addr));
+    } else {
+      ip_addr_set(&(iphdr->src), src);
+    }
+
+  } else {
+    dest = &(iphdr->dest);
+  }
+
+  IP_STATS_INC(ip.xmit);
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c (len %"U16_F")\n", netif->name[0], netif->name[1], p->tot_len));
+#if IP_DEBUG
+  ip_debug_print(p);
+#endif /* IP_DEBUG */
+
+  PERF_STOP("ip_output_if");
+  return netif->output(netif, p, dest);
+}
+
+/* ip_output:
+ *
+ * Simple interface to ip_output_if. It finds the outgoing network interface and
+ * calls upon ip_output_if to do the actual work.
+ */
+
+err_t
+ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+    u8_t ttl, u8_t proto)
+{
+  struct netif *netif;
+  if ((netif = ip_route(dest)) == NULL) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to 0x%"X32_F"\n", dest->addr));
+    IP_STATS_INC(ip.rterr);
+    return ERR_RTE;
+  }
+
+  return ip_output_if (p, src, dest, ttl, proto, netif);
+}
+
+#if IP_DEBUG
+void
+ip_debug_print(struct pbuf *p)
+{
+  struct ip_hdr *iphdr = p->payload;
+
+  LWIP_DEBUGF(IP_DEBUG, ("IP header:\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" |  %"X16_F"%"X16_F"  |      %"X16_F"%"X16_F"           | (v, traffic class, flow label)\n",
+        iphdr->v,
+        iphdr->tclass1, iphdr->tclass2,
+        iphdr->flow1, iphdr->flow2));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|    %5"U16_F"      | %2"U16_F"  |  %2"U16_F"   | (len, nexthdr, hoplim)\n",
+        ntohs(iphdr->len),
+        iphdr->nexthdr,
+        iphdr->hoplim));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (src)\n",
+        (ntohl(iphdr->src.addr[0]) >> 16) & 0xffff,
+        ntohl(iphdr->src.addr[0]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (src)\n",
+        (ntohl(iphdr->src.addr[1]) >> 16) & 0xffff,
+        ntohl(iphdr->src.addr[1]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (src)\n",
+        (ntohl(iphdr->src.addr[2]) >> 16) & 0xffff,
+        ntohl(iphdr->src.addr[2]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (src)\n",
+        (ntohl(iphdr->src.addr[3]) >> 16) & 0xffff,
+        ntohl(iphdr->src.addr[3]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (dest)\n",
+        (ntohl(iphdr->dest.addr[0]) >> 16) & 0xffff,
+        ntohl(iphdr->dest.addr[0]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (dest)\n",
+        (ntohl(iphdr->dest.addr[1]) >> 16) & 0xffff,
+        ntohl(iphdr->dest.addr[1]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (dest)\n",
+        (ntohl(iphdr->dest.addr[2]) >> 16) & 0xffff,
+        ntohl(iphdr->dest.addr[2]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (dest)\n",
+        (ntohl(iphdr->dest.addr[3]) >> 16) & 0xffff,
+        ntohl(iphdr->dest.addr[3]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+}
+#endif /* IP_DEBUG */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv6/ip6_addr.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv6/ip6_addr.c
new file mode 100644
index 0000000..d898526
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/ipv6/ip6_addr.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+#include "lwip/ip_addr.h"
+#include "lwip/inet.h"
+
+u8_t
+ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2,
+                struct ip_addr *mask)
+{
+  return((addr1->addr[0] & mask->addr[0]) == (addr2->addr[0] & mask->addr[0]) &&
+         (addr1->addr[1] & mask->addr[1]) == (addr2->addr[1] & mask->addr[1]) &&
+         (addr1->addr[2] & mask->addr[2]) == (addr2->addr[2] & mask->addr[2]) &&
+         (addr1->addr[3] & mask->addr[3]) == (addr2->addr[3] & mask->addr[3]));
+        
+}
+
+u8_t
+ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2)
+{
+  return(addr1->addr[0] == addr2->addr[0] &&
+         addr1->addr[1] == addr2->addr[1] &&
+         addr1->addr[2] == addr2->addr[2] &&
+         addr1->addr[3] == addr2->addr[3]);
+}
+
+void
+ip_addr_set(struct ip_addr *dest, struct ip_addr *src)
+{
+  SMEMCPY(dest, src, sizeof(struct ip_addr));
+  /*  dest->addr[0] = src->addr[0];
+  dest->addr[1] = src->addr[1];
+  dest->addr[2] = src->addr[2];
+  dest->addr[3] = src->addr[3];*/
+}
+
+u8_t
+ip_addr_isany(struct ip_addr *addr)
+{
+  if (addr == NULL) return 1;
+  return((addr->addr[0] | addr->addr[1] | addr->addr[2] | addr->addr[3]) == 0);
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/mem.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/mem.c
new file mode 100644
index 0000000..fbe3fa2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/mem.c
@@ -0,0 +1,577 @@
+/**
+ * @file
+ * Dynamic memory manager
+ *
+ * This is a lightweight replacement for the standard C library malloc().
+ *
+ * If you want to use the standard C library malloc() instead, define
+ * MEM_LIBC_MALLOC to 1 in your lwipopts.h
+ *
+ * To let mem_malloc() use pools (prevents fragmentation and is much faster than
+ * a heap but might waste some memory), define MEM_USE_POOLS to 1, define
+ * MEM_USE_CUSTOM_POOLS to 1 and create a file "lwippools.h" that includes a list
+ * of pools like this (more pools can be added between _START and _END):
+ *
+ * Define three pools with sizes 256, 512, and 1512 bytes
+ * LWIP_MALLOC_MEMPOOL_START
+ * LWIP_MALLOC_MEMPOOL(20, 256)
+ * LWIP_MALLOC_MEMPOOL(10, 512)
+ * LWIP_MALLOC_MEMPOOL(5, 1512)
+ * LWIP_MALLOC_MEMPOOL_END
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *         Simon Goldschmidt
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if !MEM_LIBC_MALLOC /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+
+#include 
+
+#if MEM_USE_POOLS
+/* lwIP head implemented with different sized pools */
+
+/**
+ * This structure is used to save the pool one element came from.
+ */
+struct mem_helper
+{
+   memp_t poolnr;
+};
+
+/**
+ * Allocate memory: determine the smallest pool that is big enough
+ * to contain an element of 'size' and get an element from that pool.
+ *
+ * @param size the size in bytes of the memory needed
+ * @return a pointer to the allocated memory or NULL if the pool is empty
+ */
+void *
+mem_malloc(mem_size_t size)
+{
+  struct mem_helper *element;
+  memp_t poolnr;
+
+  for (poolnr = MEMP_POOL_FIRST; poolnr <= MEMP_POOL_LAST; poolnr++) {
+    /* is this pool big enough to hold an element of the required size
+       plus a struct mem_helper that saves the pool this element came from? */
+    if ((size + sizeof(struct mem_helper)) <= memp_sizes[poolnr]) {
+      break;
+    }
+  }
+  if (poolnr > MEMP_POOL_LAST) {
+    LWIP_ASSERT("mem_malloc(): no pool is that big!", 0);
+    return NULL;
+  }
+  element = (struct mem_helper*)memp_malloc(poolnr);
+  if (element == NULL) {
+    /* No need to DEBUGF or ASSERT: This error is already
+       taken care of in memp.c */
+    /** @todo: we could try a bigger pool if this one is empty! */
+    return NULL;
+  }
+
+  /* save the pool number this element came from */
+  element->poolnr = poolnr;
+  /* and return a pointer to the memory directly after the struct mem_helper */
+  element++;
+
+  return element;
+}
+
+/**
+ * Free memory previously allocated by mem_malloc. Loads the pool number
+ * and calls memp_free with that pool number to put the element back into
+ * its pool
+ *
+ * @param rmem the memory element to free
+ */
+void
+mem_free(void *rmem)
+{
+  struct mem_helper *hmem = (struct mem_helper*)rmem;
+
+  LWIP_ASSERT("rmem != NULL", (rmem != NULL));
+  LWIP_ASSERT("rmem == MEM_ALIGN(rmem)", (rmem == LWIP_MEM_ALIGN(rmem)));
+
+  /* get the original struct mem_helper */
+  hmem--;
+
+  LWIP_ASSERT("hmem != NULL", (hmem != NULL));
+  LWIP_ASSERT("hmem == MEM_ALIGN(hmem)", (hmem == LWIP_MEM_ALIGN(hmem)));
+  LWIP_ASSERT("hmem->poolnr < MEMP_MAX", (hmem->poolnr < MEMP_MAX));
+
+  /* and put it in the pool we saved earlier */
+  memp_free(hmem->poolnr, hmem);
+}
+
+#else /* MEM_USE_POOLS */
+/* lwIP replacement for your libc malloc() */
+
+/**
+ * The heap is made up as a list of structs of this type.
+ * This does not have to be aligned since for getting its size,
+ * we only use the macro SIZEOF_STRUCT_MEM, which automatically alignes.
+ */
+struct mem {
+  /** index (-> ram[next]) of the next struct */
+  mem_size_t next;
+  /** index (-> ram[next]) of the next struct */
+  mem_size_t prev;
+  /** 1: this area is used; 0: this area is unused */
+  u8_t used;
+};
+
+/** All allocated blocks will be MIN_SIZE bytes big, at least!
+ * MIN_SIZE can be overridden to suit your needs. Smaller values save space,
+ * larger values could prevent too small blocks to fragment the RAM too much. */
+#ifndef MIN_SIZE
+#define MIN_SIZE             12
+#endif /* MIN_SIZE */
+/* some alignment macros: we define them here for better source code layout */
+#define MIN_SIZE_ALIGNED     LWIP_MEM_ALIGN_SIZE(MIN_SIZE)
+#define SIZEOF_STRUCT_MEM    LWIP_MEM_ALIGN_SIZE(sizeof(struct mem))
+#define MEM_SIZE_ALIGNED     LWIP_MEM_ALIGN_SIZE(MEM_SIZE)
+
+/** the heap. we need one struct mem at the end and some room for alignment */
+static u8_t ram_heap[MEM_SIZE_ALIGNED + (2*SIZEOF_STRUCT_MEM) + MEM_ALIGNMENT];
+/** pointer to the heap (ram_heap): for alignment, ram is now a pointer instead of an array */
+static u8_t *ram;
+/** the last entry, always unused! */
+static struct mem *ram_end;
+/** pointer to the lowest free block, this is used for faster search */
+static struct mem *lfree;
+/** concurrent access protection */
+static sys_sem_t mem_sem;
+
+/**
+ * "Plug holes" by combining adjacent empty struct mems.
+ * After this function is through, there should not exist
+ * one empty struct mem pointing to another empty struct mem.
+ *
+ * @param mem this points to a struct mem which just has been freed
+ * @internal this function is only called by mem_free() and mem_realloc()
+ *
+ * This assumes access to the heap is protected by the calling function
+ * already.
+ */
+static void
+plug_holes(struct mem *mem)
+{
+  struct mem *nmem;
+  struct mem *pmem;
+
+  LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram);
+  LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end);
+  LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0);
+
+  /* plug hole forward */
+  LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE_ALIGNED", mem->next <= MEM_SIZE_ALIGNED);
+
+  nmem = (struct mem *)&ram[mem->next];
+  if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) {
+    /* if mem->next is unused and not end of ram, combine mem and mem->next */
+    if (lfree == nmem) {
+      lfree = mem;
+    }
+    mem->next = nmem->next;
+    ((struct mem *)&ram[nmem->next])->prev = (u8_t *)mem - ram;
+  }
+
+  /* plug hole backward */
+  pmem = (struct mem *)&ram[mem->prev];
+  if (pmem != mem && pmem->used == 0) {
+    /* if mem->prev is unused, combine mem and mem->prev */
+    if (lfree == mem) {
+      lfree = pmem;
+    }
+    pmem->next = mem->next;
+    ((struct mem *)&ram[mem->next])->prev = (u8_t *)pmem - ram;
+  }
+}
+
+/**
+ * Zero the heap and initialize start, end and lowest-free
+ */
+void
+mem_init(void)
+{
+  struct mem *mem;
+
+  LWIP_ASSERT("Sanity check alignment",
+    (SIZEOF_STRUCT_MEM & (MEM_ALIGNMENT-1)) == 0);
+
+  /* align the heap */
+  ram = LWIP_MEM_ALIGN(ram_heap);
+  /* initialize the start of the heap */
+  mem = (struct mem *)ram;
+  mem->next = MEM_SIZE_ALIGNED;
+  mem->prev = 0;
+  mem->used = 0;
+  /* initialize the end of the heap */
+  ram_end = (struct mem *)&ram[MEM_SIZE_ALIGNED];
+  ram_end->used = 1;
+  ram_end->next = MEM_SIZE_ALIGNED;
+  ram_end->prev = MEM_SIZE_ALIGNED;
+
+  mem_sem = sys_sem_new(1);
+
+  /* initialize the lowest-free pointer to the start of the heap */
+  lfree = (struct mem *)ram;
+
+#if MEM_STATS
+  lwip_stats.mem.avail = MEM_SIZE_ALIGNED;
+#endif /* MEM_STATS */
+}
+
+/**
+ * Put a struct mem back on the heap
+ *
+ * @param rmem is the data portion of a struct mem as returned by a previous
+ *             call to mem_malloc()
+ */
+void
+mem_free(void *rmem)
+{
+  struct mem *mem;
+
+  if (rmem == NULL) {
+    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_TRACE | 2, ("mem_free(p == NULL) was called.\n"));
+    return;
+  }
+  LWIP_ASSERT("mem_free: sanity check alignment", (((mem_ptr_t)rmem) & (MEM_ALIGNMENT-1)) == 0);
+
+  /* protect the heap from concurrent access */
+  sys_arch_sem_wait(mem_sem, 0);
+
+  LWIP_ASSERT("mem_free: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
+    (u8_t *)rmem < (u8_t *)ram_end);
+
+  if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
+    LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_free: illegal memory\n"));
+#if MEM_STATS
+    ++lwip_stats.mem.err;
+#endif /* MEM_STATS */
+    sys_sem_signal(mem_sem);
+    return;
+  }
+  /* Get the corresponding struct mem ... */
+  mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM);
+  /* ... which has to be in a used state ... */
+  LWIP_ASSERT("mem_free: mem->used", mem->used);
+  /* ... and is now unused. */
+  mem->used = 0;
+
+  if (mem < lfree) {
+    /* the newly freed struct is now the lowest */
+    lfree = mem;
+  }
+
+#if MEM_STATS
+  lwip_stats.mem.used -= mem->next - ((u8_t *)mem - ram);
+#endif /* MEM_STATS */
+
+  /* finally, see if prev or next are free also */
+  plug_holes(mem);
+  sys_sem_signal(mem_sem);
+}
+
+/**
+ * In contrast to its name, mem_realloc can only shrink memory, not expand it.
+ * Since the only use (for now) is in pbuf_realloc (which also can only shrink),
+ * this shouldn't be a problem!
+ *
+ * @param rmem pointer to memory allocated by mem_malloc the is to be shrinked
+ * @param newsize required size after shrinking (needs to be smaller than or
+ *                equal to the previous size)
+ * @return for compatibility reasons: is always == rmem, at the moment
+ */
+void *
+mem_realloc(void *rmem, mem_size_t newsize)
+{
+  mem_size_t size;
+  mem_size_t ptr, ptr2;
+  struct mem *mem, *mem2;
+
+  /* Expand the size of the allocated memory region so that we can
+     adjust for alignment. */
+  newsize = LWIP_MEM_ALIGN_SIZE(newsize);
+
+  if(newsize < MIN_SIZE_ALIGNED) {
+    /* every data block must be at least MIN_SIZE_ALIGNED long */
+    newsize = MIN_SIZE_ALIGNED;
+  }
+
+  if (newsize > MEM_SIZE_ALIGNED) {
+    return NULL;
+  }
+
+  LWIP_ASSERT("mem_realloc: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
+   (u8_t *)rmem < (u8_t *)ram_end);
+
+  if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
+    LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_realloc: illegal memory\n"));
+    return rmem;
+  }
+  /* Get the corresponding struct mem ... */
+  mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM);
+  /* ... and its offset pointer */
+  ptr = (u8_t *)mem - ram;
+
+  size = mem->next - ptr - SIZEOF_STRUCT_MEM;
+  LWIP_ASSERT("mem_realloc can only shrink memory", newsize <= size);
+  if (newsize > size) {
+    /* not supported */
+    return NULL;
+  }
+  if (newsize == size) {
+    /* No change in size, simply return */
+    return rmem;
+  }
+
+  /* protect the heap from concurrent access */
+  sys_arch_sem_wait(mem_sem, 0);
+
+#if MEM_STATS
+  lwip_stats.mem.used -= (size - newsize);
+#endif /* MEM_STATS */
+
+  mem2 = (struct mem *)&ram[mem->next];
+  if(mem2->used == 0) {
+    /* The next struct is unused, we can simply move it at little */
+    mem_size_t next;
+    /* remember the old next pointer */
+    next = mem2->next;
+    /* create new struct mem which is moved directly after the shrinked mem */
+    ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize;
+    if (lfree == mem2) {
+      lfree = (struct mem *)&ram[ptr2];
+    }
+    mem2 = (struct mem *)&ram[ptr2];
+    mem2->used = 0;
+    /* restore the next pointer */
+    mem2->next = next;
+    /* link it back to mem */
+    mem2->prev = ptr;
+    /* link mem to it */
+    mem->next = ptr2;
+    /* last thing to restore linked list: as we have moved mem2,
+     * let 'mem2->next->prev' point to mem2 again. but only if mem2->next is not
+     * the end of the heap */
+    if (mem2->next != MEM_SIZE_ALIGNED) {
+      ((struct mem *)&ram[mem2->next])->prev = ptr2;
+    }
+    /* no need to plug holes, we've already done that */
+  } else if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED <= size) {
+    /* Next struct is used but there's room for another struct mem with
+     * at least MIN_SIZE_ALIGNED of data.
+     * Old size ('size') must be big enough to contain at least 'newsize' plus a struct mem
+     * ('SIZEOF_STRUCT_MEM') with some data ('MIN_SIZE_ALIGNED').
+     * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty
+     *       region that couldn't hold data, but when mem->next gets freed,
+     *       the 2 regions would be combined, resulting in more free memory */
+    ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize;
+    mem2 = (struct mem *)&ram[ptr2];
+    if (mem2 < lfree) {
+      lfree = mem2;
+    }
+    mem2->used = 0;
+    mem2->next = mem->next;
+    mem2->prev = ptr;
+    mem->next = ptr2;
+    if (mem2->next != MEM_SIZE_ALIGNED) {
+      ((struct mem *)&ram[mem2->next])->prev = ptr2;
+    }
+    /* the original mem->next is used, so no need to plug holes! */
+  }
+  /* else {
+    next struct mem is used but size between mem and mem2 is not big enough
+    to create another struct mem
+    -> don't do anyhting.
+    -> the remaining space stays unused since it is too small
+  } */
+  sys_sem_signal(mem_sem);
+  return rmem;
+}
+
+/**
+ * Adam's mem_malloc() plus solution for bug #17922
+ * Allocate a block of memory with a minimum of 'size' bytes.
+ *
+ * @param size is the minimum size of the requested block in bytes.
+ * @return pointer to allocated memory or NULL if no free memory was found.
+ *
+ * Note that the returned value will always be aligned (as defined by MEM_ALIGNMENT).
+ */
+void *
+mem_malloc(mem_size_t size)
+{
+  mem_size_t ptr, ptr2;
+  struct mem *mem, *mem2;
+
+  if (size == 0) {
+    return NULL;
+  }
+
+  /* Expand the size of the allocated memory region so that we can
+     adjust for alignment. */
+  size = LWIP_MEM_ALIGN_SIZE(size);
+
+  if(size < MIN_SIZE_ALIGNED) {
+    /* every data block must be at least MIN_SIZE_ALIGNED long */
+    size = MIN_SIZE_ALIGNED;
+  }
+
+  if (size > MEM_SIZE_ALIGNED) {
+    return NULL;
+  }
+
+  /* protect the heap from concurrent access */
+  sys_arch_sem_wait(mem_sem, 0);
+
+  /* Scan through the heap searching for a free block that is big enough,
+   * beginning with the lowest free block.
+   */
+  for (ptr = (u8_t *)lfree - ram; ptr < MEM_SIZE_ALIGNED - size;
+       ptr = ((struct mem *)&ram[ptr])->next) {
+    mem = (struct mem *)&ram[ptr];
+
+    if ((!mem->used) &&
+        (mem->next - (ptr + SIZEOF_STRUCT_MEM)) >= size) {
+      /* mem is not used and at least perfect fit is possible:
+       * mem->next - (ptr + SIZEOF_STRUCT_MEM) gives us the 'user data size' of mem */
+
+      if (mem->next - (ptr + SIZEOF_STRUCT_MEM) >= (size + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED)) {
+        /* (in addition to the above, we test if another struct mem (SIZEOF_STRUCT_MEM) containing
+         * at least MIN_SIZE_ALIGNED of data also fits in the 'user data space' of 'mem')
+         * -> split large block, create empty remainder,
+         * remainder must be large enough to contain MIN_SIZE_ALIGNED data: if
+         * mem->next - (ptr + (2*SIZEOF_STRUCT_MEM)) == size,
+         * struct mem would fit in but no data between mem2 and mem2->next
+         * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty
+         *       region that couldn't hold data, but when mem->next gets freed,
+         *       the 2 regions would be combined, resulting in more free memory
+         */
+        ptr2 = ptr + SIZEOF_STRUCT_MEM + size;
+        /* create mem2 struct */
+        mem2 = (struct mem *)&ram[ptr2];
+        mem2->used = 0;
+        mem2->next = mem->next;
+        mem2->prev = ptr;
+        /* and insert it between mem and mem->next */
+        mem->next = ptr2;
+        mem->used = 1;
+
+        if (mem2->next != MEM_SIZE_ALIGNED) {
+          ((struct mem *)&ram[mem2->next])->prev = ptr2;
+        }
+#if MEM_STATS
+        lwip_stats.mem.used += (size + SIZEOF_STRUCT_MEM);
+        if (lwip_stats.mem.max < lwip_stats.mem.used) {
+          lwip_stats.mem.max = lwip_stats.mem.used;
+        }
+#endif /* MEM_STATS */
+      } else {
+        /* (a mem2 struct does no fit into the user data space of mem and mem->next will always
+         * be used at this point: if not we have 2 unused structs in a row, plug_holes should have
+         * take care of this).
+         * -> near fit or excact fit: do not split, no mem2 creation
+         * also can't move mem->next directly behind mem, since mem->next
+         * will always be used at this point!
+         */
+        mem->used = 1;
+#if MEM_STATS
+        lwip_stats.mem.used += mem->next - ((u8_t *)mem - ram);
+        if (lwip_stats.mem.max < lwip_stats.mem.used) {
+          lwip_stats.mem.max = lwip_stats.mem.used;
+        }
+#endif /* MEM_STATS */
+      }
+
+      if (mem == lfree) {
+        /* Find next free block after mem and update lowest free pointer */
+        while (lfree->used && lfree != ram_end) {
+          lfree = (struct mem *)&ram[lfree->next];
+        }
+        LWIP_ASSERT("mem_malloc: !lfree->used", ((lfree == ram_end) || (!lfree->used)));
+      }
+      sys_sem_signal(mem_sem);
+      LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.",
+       (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end);
+      LWIP_ASSERT("mem_malloc: allocated memory properly aligned.",
+       (unsigned long)((u8_t *)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0);
+      LWIP_ASSERT("mem_malloc: sanity check alignment",
+        (((mem_ptr_t)mem) & (MEM_ALIGNMENT-1)) == 0);
+
+      return (u8_t *)mem + SIZEOF_STRUCT_MEM;
+    }
+  }
+  LWIP_DEBUGF(MEM_DEBUG | 2, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size));
+#if MEM_STATS
+  ++lwip_stats.mem.err;
+#endif /* MEM_STATS */
+  sys_sem_signal(mem_sem);
+  return NULL;
+}
+
+#endif /* MEM_USE_POOLS */
+/**
+ * Contiguously allocates enough space for count objects that are size bytes
+ * of memory each and returns a pointer to the allocated memory.
+ *
+ * The allocated memory is filled with bytes of value zero.
+ *
+ * @param count number of objects to allocate
+ * @param size size of the objects to allocate
+ * @return pointer to allocated memory / NULL pointer if there is an error
+ */
+void *mem_calloc(mem_size_t count, mem_size_t size)
+{
+  void *p;
+
+  /* allocate 'count' objects of size 'size' */
+  p = mem_malloc(count * size);
+  if (p) {
+    /* zero the memory */
+    memset(p, 0, count * size);
+  }
+  return p;
+}
+
+#endif /* !MEM_LIBC_MALLOC */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/memp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/memp.c
new file mode 100644
index 0000000..d43e479
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/memp.c
@@ -0,0 +1,380 @@
+/**
+ * @file
+ * Dynamic pool memory manager
+ *
+ * lwIP has dedicated pools for many structures (netconn, protocol control blocks,
+ * packet buffers, ...). All these pools are managed here.
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/memp.h"
+#include "lwip/pbuf.h"
+#include "lwip/udp.h"
+#include "lwip/raw.h"
+#include "lwip/tcp.h"
+#include "lwip/igmp.h"
+#include "lwip/api.h"
+#include "lwip/api_msg.h"
+#include "lwip/tcpip.h"
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+#include "netif/etharp.h"
+#include "lwip/ip_frag.h"
+
+#include 
+
+struct memp {
+  struct memp *next;
+#if MEMP_OVERFLOW_CHECK
+  const char *file;
+  int line;
+#endif /* MEMP_OVERFLOW_CHECK */
+};
+
+#if MEMP_OVERFLOW_CHECK
+/* if MEMP_OVERFLOW_CHECK is turned on, we reserve some bytes at the beginning
+ * and at the end of each element, initialize them as 0xcd and check
+ * them later. */
+/* If MEMP_OVERFLOW_CHECK is >= 2, on every call to memp_malloc or memp_free,
+ * every single element in each pool is checked!
+ * This is VERY SLOW but also very helpful. */
+/* MEMP_SANITY_REGION_BEFORE and MEMP_SANITY_REGION_AFTER can be overridden in
+ * lwipopts.h to change the amount reserved for checking. */
+#ifndef MEMP_SANITY_REGION_BEFORE
+#define MEMP_SANITY_REGION_BEFORE  16
+#endif /* MEMP_SANITY_REGION_BEFORE*/
+#if MEMP_SANITY_REGION_BEFORE > 0
+#define MEMP_SANITY_REGION_BEFORE_ALIGNED    LWIP_MEM_ALIGN_SIZE(MEMP_SANITY_REGION_BEFORE)
+#else
+#define MEMP_SANITY_REGION_BEFORE_ALIGNED    0
+#endif /* MEMP_SANITY_REGION_BEFORE*/
+#ifndef MEMP_SANITY_REGION_AFTER
+#define MEMP_SANITY_REGION_AFTER   16
+#endif /* MEMP_SANITY_REGION_AFTER*/
+#if MEMP_SANITY_REGION_AFTER > 0
+#define MEMP_SANITY_REGION_AFTER_ALIGNED     LWIP_MEM_ALIGN_SIZE(MEMP_SANITY_REGION_AFTER)
+#else
+#define MEMP_SANITY_REGION_AFTER_ALIGNED     0
+#endif /* MEMP_SANITY_REGION_AFTER*/
+
+/* MEMP_SIZE: save space for struct memp and for sanity check */
+#define MEMP_SIZE          (LWIP_MEM_ALIGN_SIZE(sizeof(struct memp)) + MEMP_SANITY_REGION_BEFORE_ALIGNED)
+#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x) + MEMP_SANITY_REGION_AFTER_ALIGNED)
+
+#else /* MEMP_OVERFLOW_CHECK */
+
+/* No sanity checks
+ * We don't need to preserve the struct memp while not allocated, so we
+ * can save a little space and set MEMP_SIZE to 0.
+ */
+#define MEMP_SIZE           0
+#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x))
+
+#endif /* MEMP_OVERFLOW_CHECK */
+
+/** This array holds the first free element of each pool.
+ *  Elements form a linked list. */
+static struct memp *memp_tab[MEMP_MAX];
+
+/** This array holds the element sizes of each pool. */
+#if !MEM_USE_POOLS
+static
+#endif
+const u16_t memp_sizes[MEMP_MAX] = {
+#define LWIP_MEMPOOL(name,num,size,desc)  MEMP_ALIGN_SIZE(size),
+#include "lwip/memp_std.h"
+};
+
+/** This array holds the number of elements in each pool. */
+static const u16_t memp_num[MEMP_MAX] = {
+#define LWIP_MEMPOOL(name,num,size,desc)  (num),
+#include "lwip/memp_std.h"
+};
+
+/** This array holds a textual description of each pool. */
+#ifdef LWIP_DEBUG
+static const char *memp_desc[MEMP_MAX] = {
+#define LWIP_MEMPOOL(name,num,size,desc)  (desc),
+#include "lwip/memp_std.h"
+};
+#endif /* LWIP_DEBUG */
+
+/** This is the actual memory used by the pools. */
+static u8_t memp_memory[MEM_ALIGNMENT - 1
+#define LWIP_MEMPOOL(name,num,size,desc) + ( (num) * (MEMP_SIZE + MEMP_ALIGN_SIZE(size) ) )
+#include "lwip/memp_std.h"
+];
+
+#if MEMP_SANITY_CHECK
+/**
+ * Check that memp-lists don't form a circle
+ */
+static int
+memp_sanity(void)
+{
+  s16_t i, c;
+  struct memp *m, *n;
+
+  for (i = 0; i < MEMP_MAX; i++) {
+    for (m = memp_tab[i]; m != NULL; m = m->next) {
+      c = 1;
+      for (n = memp_tab[i]; n != NULL; n = n->next) {
+        if (n == m && --c < 0) {
+          return 0;
+        }
+      }
+    }
+  }
+  return 1;
+}
+#endif /* MEMP_SANITY_CHECK*/
+#if MEMP_OVERFLOW_CHECK
+/**
+ * Check if a memp element was victim of an overflow
+ * (e.g. the restricted area after it has been altered)
+ *
+ * @param p the memp element to check
+ * @param memp_size the element size of the pool p comes from
+ */
+static void
+memp_overflow_check_element(struct memp *p, u16_t memp_size)
+{
+  u16_t k;
+  u8_t *m;
+#if MEMP_SANITY_REGION_BEFORE_ALIGNED > 0
+  m = (u8_t*)p + MEMP_SIZE - MEMP_SANITY_REGION_BEFORE_ALIGNED;
+  for (k = 0; k < MEMP_SANITY_REGION_BEFORE_ALIGNED; k++) {
+    if (m[k] != 0xcd) {
+      LWIP_ASSERT("detected memp underflow!", 0);
+    }
+  }
+#endif
+#if MEMP_SANITY_REGION_AFTER_ALIGNED > 0
+  m = (u8_t*)p + MEMP_SIZE + memp_size - MEMP_SANITY_REGION_AFTER_ALIGNED;
+  for (k = 0; k < MEMP_SANITY_REGION_AFTER_ALIGNED; k++) {
+    if (m[k] != 0xcd) {
+      LWIP_ASSERT("detected memp overflow!", 0);
+    }
+  }
+#endif
+}
+
+/**
+ * Do an overflow check for all elements in every pool.
+ *
+ * @see memp_overflow_check_element for a description of the check
+ */
+static void
+memp_overflow_check_all(void)
+{
+  u16_t i, j;
+  struct memp *p;
+
+  p = LWIP_MEM_ALIGN(memp_memory);
+  for (i = 0; i < MEMP_MAX; ++i) {
+    p = p;
+    for (j = 0; j < memp_num[i]; ++j) {
+      memp_overflow_check_element(p, memp_sizes[i]);
+      p = (struct memp*)((u8_t*)p + MEMP_SIZE + memp_sizes[i]);
+    }
+  }
+}
+
+/**
+ * Initialize the restricted areas of all memp elements in every pool.
+ */
+static void
+memp_overflow_init(void)
+{
+  u16_t i, j;
+  struct memp *p;
+  u8_t *m;
+
+  p = LWIP_MEM_ALIGN(memp_memory);
+  for (i = 0; i < MEMP_MAX; ++i) {
+    p = p;
+    for (j = 0; j < memp_num[i]; ++j) {
+#if MEMP_SANITY_REGION_BEFORE_ALIGNED > 0
+      m = (u8_t*)p + MEMP_SIZE - MEMP_SANITY_REGION_BEFORE_ALIGNED;
+      memset(m, 0xcd, MEMP_SANITY_REGION_BEFORE_ALIGNED);
+#endif
+#if MEMP_SANITY_REGION_AFTER_ALIGNED > 0
+      m = (u8_t*)p + MEMP_SIZE + memp_sizes[i] - MEMP_SANITY_REGION_AFTER_ALIGNED;
+      memset(m, 0xcd, MEMP_SANITY_REGION_AFTER_ALIGNED);
+#endif
+      p = (struct memp*)((u8_t*)p + MEMP_SIZE + memp_sizes[i]);
+    }
+  }
+}
+#endif /* MEMP_OVERFLOW_CHECK */
+
+/**
+ * Initialize this module.
+ *
+ * Carves out memp_memory into linked lists for each pool-type.
+ */
+void
+memp_init(void)
+{
+  struct memp *memp;
+  u16_t i, j;
+
+#if MEMP_STATS
+  for (i = 0; i < MEMP_MAX; ++i) {
+    lwip_stats.memp[i].used = lwip_stats.memp[i].max =
+      lwip_stats.memp[i].err = 0;
+    lwip_stats.memp[i].avail = memp_num[i];
+  }
+#endif /* MEMP_STATS */
+
+  memp = LWIP_MEM_ALIGN(memp_memory);
+  /* for every pool: */
+  for (i = 0; i < MEMP_MAX; ++i) {
+    memp_tab[i] = NULL;
+    /* create a linked list of memp elements */
+    for (j = 0; j < memp_num[i]; ++j) {
+      memp->next = memp_tab[i];
+      memp_tab[i] = memp;
+      memp = (struct memp *)((u8_t *)memp + MEMP_SIZE + memp_sizes[i]);
+    }
+  }
+#if MEMP_OVERFLOW_CHECK
+  memp_overflow_init();
+  /* check everything a first time to see if it worked */
+  memp_overflow_check_all();
+#endif /* MEMP_OVERFLOW_CHECK */
+}
+
+/**
+ * Get an element from a specific pool.
+ *
+ * @param type the pool to get an element from
+ *
+ * the debug version has two more parameters:
+ * @param file file name calling this function
+ * @param line number of line where this function is called
+ *
+ * @return a pointer to the allocated memory or a NULL pointer on error
+ */
+void *
+#if !MEMP_OVERFLOW_CHECK
+memp_malloc(memp_t type)
+#else
+memp_malloc_fn(memp_t type, const char* file, const int line)
+#endif
+{
+  struct memp *memp;
+  SYS_ARCH_DECL_PROTECT(old_level);
+
+  LWIP_ERROR("memp_malloc: type < MEMP_MAX", (type < MEMP_MAX), return NULL;);
+
+  SYS_ARCH_PROTECT(old_level);
+#if MEMP_OVERFLOW_CHECK >= 2
+  memp_overflow_check_all();
+#endif /* MEMP_OVERFLOW_CHECK >= 2 */
+
+  memp = memp_tab[type];
+
+  if (memp != NULL) {
+    memp_tab[type] = memp->next;
+#if MEMP_OVERFLOW_CHECK
+    memp->next = NULL;
+    memp->file = file;
+    memp->line = line;
+#endif /* MEMP_OVERFLOW_CHECK */
+#if MEMP_STATS
+    ++lwip_stats.memp[type].used;
+    if (lwip_stats.memp[type].used > lwip_stats.memp[type].max) {
+      lwip_stats.memp[type].max = lwip_stats.memp[type].used;
+    }
+#endif /* MEMP_STATS */
+    LWIP_ASSERT("memp_malloc: memp properly aligned",
+                ((mem_ptr_t)memp % MEM_ALIGNMENT) == 0);
+    memp = (struct memp*)((u8_t*)memp + MEMP_SIZE);
+  } else {
+    LWIP_DEBUGF(MEMP_DEBUG | 2, ("memp_malloc: out of memory in pool %s\n", memp_desc[type]));
+#if MEMP_STATS
+    ++lwip_stats.memp[type].err;
+#endif /* MEMP_STATS */
+  }
+
+  SYS_ARCH_UNPROTECT(old_level);
+
+  return memp;
+}
+
+/**
+ * Put an element back into its pool.
+ *
+ * @param type the pool where to put mem
+ * @param mem the memp element to free
+ */
+void
+memp_free(memp_t type, void *mem)
+{
+  struct memp *memp;
+  SYS_ARCH_DECL_PROTECT(old_level);
+
+  if (mem == NULL) {
+    return;
+  }
+  LWIP_ASSERT("memp_free: mem properly aligned",
+                ((mem_ptr_t)mem % MEM_ALIGNMENT) == 0);
+
+  memp = (struct memp *)((u8_t*)mem - MEMP_SIZE);
+
+  SYS_ARCH_PROTECT(old_level);
+#if MEMP_OVERFLOW_CHECK
+#if MEMP_OVERFLOW_CHECK >= 2
+  memp_overflow_check_all();
+#else
+  memp_overflow_check_element(memp, memp_sizes[type]);
+#endif /* MEMP_OVERFLOW_CHECK >= 2 */
+#endif /* MEMP_OVERFLOW_CHECK */
+
+#if MEMP_STATS
+  lwip_stats.memp[type].used--;
+#endif /* MEMP_STATS */
+
+  memp->next = memp_tab[type];
+  memp_tab[type] = memp;
+
+#if MEMP_SANITY_CHECK
+  LWIP_ASSERT("memp sanity", memp_sanity());
+#endif /* MEMP_SANITY_CHECK */
+
+  SYS_ARCH_UNPROTECT(old_level);
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/netif.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/netif.c
new file mode 100644
index 0000000..362c6ae
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/netif.c
@@ -0,0 +1,499 @@
+/**
+ * @file
+ * lwIP network interface abstraction
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/tcp.h"
+#include "lwip/snmp.h"
+#include "lwip/igmp.h"
+#include "netif/etharp.h"
+
+#if LWIP_NETIF_STATUS_CALLBACK
+#define NETIF_STATUS_CALLBACK(n) { if (n->status_callback) (n->status_callback)(n); }
+#else
+#define NETIF_STATUS_CALLBACK(n) { /* NOP */ }
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+
+#if LWIP_NETIF_LINK_CALLBACK
+#define NETIF_LINK_CALLBACK(n) { if (n->link_callback) (n->link_callback)(n); }
+#else
+#define NETIF_LINK_CALLBACK(n) { /* NOP */ }
+#endif /* LWIP_NETIF_LINK_CALLBACK */
+
+struct netif *netif_list;
+struct netif *netif_default;
+
+/**
+ * Add a network interface to the list of lwIP netifs.
+ *
+ * @param netif a pre-allocated netif structure
+ * @param ipaddr IP address for the new netif
+ * @param netmask network mask for the new netif
+ * @param gw default gateway IP address for the new netif
+ * @param state opaque data passed to the new netif
+ * @param init callback function that initializes the interface
+ * @param input callback function that is called to pass
+ * ingress packets up in the protocol layer stack.
+ *
+ * @return netif, or NULL if failed.
+ */
+struct netif *
+netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
+  struct ip_addr *gw,
+  void *state,
+  err_t (* init)(struct netif *netif),
+  err_t (* input)(struct pbuf *p, struct netif *netif))
+{
+  static u8_t netifnum = 0;
+
+  /* reset new interface configuration state */
+  netif->ip_addr.addr = 0;
+  netif->netmask.addr = 0;
+  netif->gw.addr = 0;
+  netif->flags = 0;
+#if LWIP_DHCP
+  /* netif not under DHCP control by default */
+  netif->dhcp = NULL;
+#endif /* LWIP_DHCP */
+#if LWIP_AUTOIP
+  /* netif not under AutoIP control by default */
+  netif->autoip = NULL;
+#endif /* LWIP_AUTOIP */
+#if LWIP_NETIF_STATUS_CALLBACK
+  netif->status_callback = NULL;
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+#if LWIP_NETIF_LINK_CALLBACK
+  netif->link_callback = NULL;
+#endif /* LWIP_NETIF_LINK_CALLBACK */
+#if LWIP_IGMP
+  netif->igmp_mac_filter = NULL;
+#endif /* LWIP_IGMP */
+
+  /* remember netif specific state information data */
+  netif->state = state;
+  netif->num = netifnum++;
+  netif->input = input;
+#if LWIP_NETIF_HWADDRHINT
+  netif->addr_hint = NULL;
+#endif /* LWIP_NETIF_HWADDRHINT*/
+
+  netif_set_addr(netif, ipaddr, netmask, gw);
+
+  /* call user specified initialization function for netif */
+  if (init(netif) != ERR_OK) {
+    return NULL;
+  }
+
+  /* add this netif to the list */
+  netif->next = netif_list;
+  netif_list = netif;
+  snmp_inc_iflist();
+
+#if LWIP_IGMP
+  /* start IGMP processing */
+  if (netif->flags & NETIF_FLAG_IGMP) {
+    igmp_start( netif);
+  }
+#endif /* LWIP_IGMP */
+
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP addr ",
+    netif->name[0], netif->name[1]));
+  ip_addr_debug_print(NETIF_DEBUG, ipaddr);
+  LWIP_DEBUGF(NETIF_DEBUG, (" netmask "));
+  ip_addr_debug_print(NETIF_DEBUG, netmask);
+  LWIP_DEBUGF(NETIF_DEBUG, (" gw "));
+  ip_addr_debug_print(NETIF_DEBUG, gw);
+  LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
+  return netif;
+}
+
+/**
+ * Change IP address configuration for a network interface (including netmask
+ * and default gateway).
+ *
+ * @param netif the network interface to change
+ * @param ipaddr the new IP address
+ * @param netmask the new netmask
+ * @param gw the new default gateway
+ */
+void
+netif_set_addr(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
+    struct ip_addr *gw)
+{
+  netif_set_ipaddr(netif, ipaddr);
+  netif_set_netmask(netif, netmask);
+  netif_set_gw(netif, gw);
+}
+
+/**
+ * Remove a network interface from the list of lwIP netifs.
+ *
+ * @param netif the network interface to remove
+ */
+void netif_remove(struct netif * netif)
+{
+  if ( netif == NULL ) return;
+
+#if LWIP_IGMP
+  /* stop IGMP processing */
+  if (netif->flags & NETIF_FLAG_IGMP) {
+    igmp_stop( netif);
+  }
+#endif /* LWIP_IGMP */
+
+  snmp_delete_ipaddridx_tree(netif);
+
+  /*  is it the first netif? */
+  if (netif_list == netif) {
+    netif_list = netif->next;
+    snmp_dec_iflist();
+  }
+  else {
+    /*  look for netif further down the list */
+    struct netif * tmpNetif;
+    for (tmpNetif = netif_list; tmpNetif != NULL; tmpNetif = tmpNetif->next) {
+      if (tmpNetif->next == netif) {
+        tmpNetif->next = netif->next;
+        snmp_dec_iflist();
+        break;
+      }
+    }
+    if (tmpNetif == NULL)
+      return; /*  we didn't find any netif today */
+  }
+  /* this netif is default? */
+  if (netif_default == netif)
+    /* reset default netif */
+    netif_set_default(NULL);
+  LWIP_DEBUGF( NETIF_DEBUG, ("netif_remove: removed netif\n") );
+}
+
+/**
+ * Find a network interface by searching for its name
+ *
+ * @param name the name of the netif (like netif->name) plus concatenated number
+ * in ascii representation (e.g. 'en0')
+ */
+struct netif *
+netif_find(char *name)
+{
+  struct netif *netif;
+  u8_t num;
+
+  if (name == NULL) {
+    return NULL;
+  }
+
+  num = name[2] - '0';
+
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+    if (num == netif->num &&
+       name[0] == netif->name[0] &&
+       name[1] == netif->name[1]) {
+      LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: found %c%c\n", name[0], name[1]));
+      return netif;
+    }
+  }
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: didn't find %c%c\n", name[0], name[1]));
+  return NULL;
+}
+
+/**
+ * Change the IP address of a network interface
+ *
+ * @param netif the network interface to change
+ * @param ipaddr the new IP address
+ *
+ * @note call netif_set_addr() if you also want to change netmask and
+ * default gateway
+ */
+void
+netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr)
+{
+  /* TODO: Handling of obsolete pcbs */
+  /* See:  http://mail.gnu.org/archive/html/lwip-users/2003-03/msg00118.html */
+#if LWIP_TCP
+  struct tcp_pcb *pcb;
+  struct tcp_pcb_listen *lpcb;
+
+  /* address is actually being changed? */
+  if ((ip_addr_cmp(ipaddr, &(netif->ip_addr))) == 0)
+  {
+    /* extern struct tcp_pcb *tcp_active_pcbs; defined by tcp.h */
+    LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: netif address being changed\n"));
+    pcb = tcp_active_pcbs;
+    while (pcb != NULL) {
+      /* PCB bound to current local interface address? */
+      if (ip_addr_cmp(&(pcb->local_ip), &(netif->ip_addr))) {
+        /* this connection must be aborted */
+        struct tcp_pcb *next = pcb->next;
+        LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb));
+        tcp_abort(pcb);
+        pcb = next;
+      } else {
+        pcb = pcb->next;
+      }
+    }
+    for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+      /* PCB bound to current local interface address? */
+      if ((!(ip_addr_isany(&(lpcb->local_ip)))) &&
+          (ip_addr_cmp(&(lpcb->local_ip), &(netif->ip_addr)))) {
+        /* The PCB is listening to the old ipaddr and
+         * is set to listen to the new one instead */
+        ip_addr_set(&(lpcb->local_ip), ipaddr);
+      }
+    }
+  }
+#endif
+  snmp_delete_ipaddridx_tree(netif);
+  snmp_delete_iprteidx_tree(0,netif);
+  /* set new IP address to netif */
+  ip_addr_set(&(netif->ip_addr), ipaddr);
+  snmp_insert_ipaddridx_tree(netif);
+  snmp_insert_iprteidx_tree(0,netif);
+
+  LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | 3, ("netif: IP address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+    netif->name[0], netif->name[1],
+    ip4_addr1(&netif->ip_addr),
+    ip4_addr2(&netif->ip_addr),
+    ip4_addr3(&netif->ip_addr),
+    ip4_addr4(&netif->ip_addr)));
+}
+
+/**
+ * Change the default gateway for a network interface
+ *
+ * @param netif the network interface to change
+ * @param gw the new default gateway
+ *
+ * @note call netif_set_addr() if you also want to change ip address and netmask
+ */
+void
+netif_set_gw(struct netif *netif, struct ip_addr *gw)
+{
+  ip_addr_set(&(netif->gw), gw);
+  LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | 3, ("netif: GW address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+    netif->name[0], netif->name[1],
+    ip4_addr1(&netif->gw),
+    ip4_addr2(&netif->gw),
+    ip4_addr3(&netif->gw),
+    ip4_addr4(&netif->gw)));
+}
+
+/**
+ * Change the netmask of a network interface
+ *
+ * @param netif the network interface to change
+ * @param netmask the new netmask
+ *
+ * @note call netif_set_addr() if you also want to change ip address and
+ * default gateway
+ */
+void
+netif_set_netmask(struct netif *netif, struct ip_addr *netmask)
+{
+  snmp_delete_iprteidx_tree(0, netif);
+  /* set new netmask to netif */
+  ip_addr_set(&(netif->netmask), netmask);
+  snmp_insert_iprteidx_tree(0, netif);
+  LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | 3, ("netif: netmask of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+    netif->name[0], netif->name[1],
+    ip4_addr1(&netif->netmask),
+    ip4_addr2(&netif->netmask),
+    ip4_addr3(&netif->netmask),
+    ip4_addr4(&netif->netmask)));
+}
+
+/**
+ * Set a network interface as the default network interface
+ * (used to output all packets for which no specific route is found)
+ *
+ * @param netif the default network interface
+ */
+void
+netif_set_default(struct netif *netif)
+{
+  if (netif == NULL)
+  {
+    /* remove default route */
+    snmp_delete_iprteidx_tree(1, netif);
+  }
+  else
+  {
+    /* install default route */
+    snmp_insert_iprteidx_tree(1, netif);
+  }
+  netif_default = netif;
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n",
+           netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\''));
+}
+
+/**
+ * Bring an interface up, available for processing
+ * traffic.
+ *
+ * @note: Enabling DHCP on a down interface will make it come
+ * up once configured.
+ *
+ * @see dhcp_start()
+ */
+void netif_set_up(struct netif *netif)
+{
+  if ( !(netif->flags & NETIF_FLAG_UP )) {
+    netif->flags |= NETIF_FLAG_UP;
+
+#if LWIP_SNMP
+    snmp_get_sysuptime(&netif->ts);
+#endif /* LWIP_SNMP */
+
+    NETIF_LINK_CALLBACK(netif);
+    NETIF_STATUS_CALLBACK(netif);
+
+#if LWIP_ARP
+    /** For Ethernet network interfaces, we would like to send a
+     *  "gratuitous ARP"; this is an ARP packet sent by a node in order
+     *  to spontaneously cause other nodes to update an entry in their
+     *  ARP cache. From RFC 3220 "IP Mobility Support for IPv4" section 4.6.
+     */
+    if (netif->flags & NETIF_FLAG_ETHARP) {
+      etharp_query(netif, &(netif->ip_addr), NULL);
+    }
+#endif /* LWIP_ARP */
+
+  }
+}
+
+/**
+ * Bring an interface down, disabling any traffic processing.
+ *
+ * @note: Enabling DHCP on a down interface will make it come
+ * up once configured.
+ *
+ * @see dhcp_start()
+ */
+void netif_set_down(struct netif *netif)
+{
+  if ( netif->flags & NETIF_FLAG_UP )
+    {
+      netif->flags &= ~NETIF_FLAG_UP;
+#if LWIP_SNMP
+      snmp_get_sysuptime(&netif->ts);
+#endif
+
+      NETIF_LINK_CALLBACK(netif);
+      NETIF_STATUS_CALLBACK(netif);
+    }
+}
+
+/**
+ * Ask if an interface is up
+ */
+u8_t netif_is_up(struct netif *netif)
+{
+  return (netif->flags & NETIF_FLAG_UP)?1:0;
+}
+
+#if LWIP_NETIF_STATUS_CALLBACK
+/**
+ * Set callback to be called when interface is brought up/down
+ */
+void netif_set_status_callback(struct netif *netif, void (* status_callback)(struct netif *netif ))
+{
+    if ( netif )
+        netif->status_callback = status_callback;
+}
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+
+#if LWIP_NETIF_LINK_CALLBACK
+/**
+ * Called by a driver when its link goes up
+ */
+void netif_set_link_up(struct netif *netif )
+{
+  netif->flags |= NETIF_FLAG_LINK_UP;
+
+#if LWIP_ARP
+  /** For Ethernet network interfaces, we would like to send a
+   *  "gratuitous ARP"; this is an ARP packet sent by a node in order
+   *  to spontaneously cause other nodes to update an entry in their
+   *  ARP cache. From RFC 3220 "IP Mobility Support for IPv4" section 4.6.
+   */
+  if (netif->flags & NETIF_FLAG_ETHARP) {
+    etharp_query(netif, &(netif->ip_addr), NULL);
+  }
+#endif /* LWIP_ARP */
+
+#if LWIP_IGMP
+  /* resend IGMP memberships */
+  if (netif->flags & NETIF_FLAG_IGMP) {
+    igmp_report_groups( netif);
+  }
+#endif /* LWIP_IGMP */
+
+  NETIF_LINK_CALLBACK(netif);
+}
+
+/**
+ * Called by a driver when its link goes down
+ */
+void netif_set_link_down(struct netif *netif )
+{
+  netif->flags &= ~NETIF_FLAG_LINK_UP;
+  NETIF_LINK_CALLBACK(netif);
+}
+
+/**
+ * Ask if a link is up
+ */
+u8_t netif_is_link_up(struct netif *netif)
+{
+  return (netif->flags & NETIF_FLAG_LINK_UP) ? 1 : 0;
+}
+
+/**
+ * Set callback to be called when link is brought up/down
+ */
+void netif_set_link_callback(struct netif *netif, void (* link_callback)(struct netif *netif ))
+{
+    if ( netif )
+        netif->link_callback = link_callback;
+}
+#endif /* LWIP_NETIF_LINK_CALLBACK */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/pbuf.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/pbuf.c
new file mode 100644
index 0000000..ecd5e16
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/pbuf.c
@@ -0,0 +1,777 @@
+/**
+ * @file
+ * Packet buffer management
+ *
+ * Packets are built from the pbuf data structure. It supports dynamic
+ * memory allocation for packet contents or can reference externally
+ * managed packet contents both in RAM and ROM. Quick allocation for
+ * incoming packets is provided through pools with fixed sized pbufs.
+ *
+ * A packet may span over multiple pbufs, chained as a singly linked
+ * list. This is called a "pbuf chain".
+ *
+ * Multiple packets may be queued, also using this singly linked list.
+ * This is called a "packet queue".
+ *
+ * So, a packet queue consists of one or more pbuf chains, each of
+ * which consist of one or more pbufs. CURRENTLY, PACKET QUEUES ARE
+ * NOT SUPPORTED!!! Use helper structs to queue multiple packets.
+ *
+ * The differences between a pbuf chain and a packet queue are very
+ * precise but subtle.
+ *
+ * The last pbuf of a packet has a ->tot_len field that equals the
+ * ->len field. It can be found by traversing the list. If the last
+ * pbuf of a packet has a ->next field other than NULL, more packets
+ * are on the queue.
+ *
+ * Therefore, looping through a pbuf of a single packet, has an
+ * loop end condition (tot_len == p->len), NOT (next == NULL).
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/stats.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include "arch/perf.h"
+
+#include 
+
+#define SIZEOF_STRUCT_PBUF        LWIP_MEM_ALIGN_SIZE(sizeof(struct pbuf))
+/* Since the pool is created in memp, PBUF_POOL_BUFSIZE will be automatically
+   aligned there. Therefore, PBUF_POOL_BUFSIZE_ALIGNED can be used here. */
+#define PBUF_POOL_BUFSIZE_ALIGNED LWIP_MEM_ALIGN_SIZE(PBUF_POOL_BUFSIZE)
+
+/**
+ * Allocates a pbuf of the given type (possibly a chain for PBUF_POOL type).
+ *
+ * The actual memory allocated for the pbuf is determined by the
+ * layer at which the pbuf is allocated and the requested size
+ * (from the size parameter).
+ *
+ * @param layer flag to define header size
+ * @param length size of the pbuf's payload
+ * @param type this parameter decides how and where the pbuf
+ * should be allocated as follows:
+ *
+ * - PBUF_RAM: buffer memory for pbuf is allocated as one large
+ *             chunk. This includes protocol headers as well.
+ * - PBUF_ROM: no buffer memory is allocated for the pbuf, even for
+ *             protocol headers. Additional headers must be prepended
+ *             by allocating another pbuf and chain in to the front of
+ *             the ROM pbuf. It is assumed that the memory used is really
+ *             similar to ROM in that it is immutable and will not be
+ *             changed. Memory which is dynamic should generally not
+ *             be attached to PBUF_ROM pbufs. Use PBUF_REF instead.
+ * - PBUF_REF: no buffer memory is allocated for the pbuf, even for
+ *             protocol headers. It is assumed that the pbuf is only
+ *             being used in a single thread. If the pbuf gets queued,
+ *             then pbuf_take should be called to copy the buffer.
+ * - PBUF_POOL: the pbuf is allocated as a pbuf chain, with pbufs from
+ *              the pbuf pool that is allocated during pbuf_init().
+ *
+ * @return the allocated pbuf. If multiple pbufs where allocated, this
+ * is the first pbuf of a pbuf chain.
+ */
+struct pbuf *
+pbuf_alloc(pbuf_layer layer, u16_t length, pbuf_type type)
+{
+  struct pbuf *p, *q, *r;
+  u16_t offset;
+  s32_t rem_len; /* remaining length */
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE | 3, ("pbuf_alloc(length=%"U16_F")\n", length));
+
+  /* determine header offset */
+  offset = 0;
+  switch (layer) {
+  case PBUF_TRANSPORT:
+    /* add room for transport (often TCP) layer header */
+    offset += PBUF_TRANSPORT_HLEN;
+    /* FALLTHROUGH */
+  case PBUF_IP:
+    /* add room for IP layer header */
+    offset += PBUF_IP_HLEN;
+    /* FALLTHROUGH */
+  case PBUF_LINK:
+    /* add room for link layer header */
+    offset += PBUF_LINK_HLEN;
+    break;
+  case PBUF_RAW:
+    break;
+  default:
+    LWIP_ASSERT("pbuf_alloc: bad pbuf layer", 0);
+    return NULL;
+  }
+
+  switch (type) {
+  case PBUF_POOL:
+    /* allocate head of pbuf chain into p */
+      p = memp_malloc(MEMP_PBUF_POOL);
+    LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE | 3, ("pbuf_alloc: allocated pbuf %p\n", (void *)p));
+    if (p == NULL) {
+      return NULL;
+    }
+    p->type = type;
+    p->next = NULL;
+
+    /* make the payload pointer point 'offset' bytes into pbuf data memory */
+    p->payload = LWIP_MEM_ALIGN((void *)((u8_t *)p + (SIZEOF_STRUCT_PBUF + offset)));
+    LWIP_ASSERT("pbuf_alloc: pbuf p->payload properly aligned",
+            ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
+    /* the total length of the pbuf chain is the requested size */
+    p->tot_len = length;
+    /* set the length of the first pbuf in the chain */
+    p->len = LWIP_MIN(length, PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset));
+    LWIP_ASSERT("check p->payload + p->len does not overflow pbuf",
+                ((u8_t*)p->payload + p->len <=
+                 (u8_t*)p + SIZEOF_STRUCT_PBUF + PBUF_POOL_BUFSIZE_ALIGNED));
+    /* set reference count (needed here in case we fail) */
+    p->ref = 1;
+
+    /* now allocate the tail of the pbuf chain */
+
+    /* remember first pbuf for linkage in next iteration */
+    r = p;
+    /* remaining length to be allocated */
+    rem_len = length - p->len;
+    /* any remaining pbufs to be allocated? */
+    while (rem_len > 0) {
+      q = memp_malloc(MEMP_PBUF_POOL);
+      if (q == NULL) {
+        /* free chain so far allocated */
+        pbuf_free(p);
+        /* bail out unsuccesfully */
+        return NULL;
+      }
+      q->type = type;
+      q->flags = 0;
+      q->next = NULL;
+      /* make previous pbuf point to this pbuf */
+      r->next = q;
+      /* set total length of this pbuf and next in chain */
+      LWIP_ASSERT("rem_len < max_u16_t", rem_len < 0xffff);
+      q->tot_len = (u16_t)rem_len;
+      /* this pbuf length is pool size, unless smaller sized tail */
+      q->len = LWIP_MIN((u16_t)rem_len, PBUF_POOL_BUFSIZE_ALIGNED);
+      q->payload = (void *)((u8_t *)q + SIZEOF_STRUCT_PBUF);
+      LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned",
+              ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0);
+      LWIP_ASSERT("check p->payload + p->len does not overflow pbuf",
+                  ((u8_t*)p->payload + p->len <=
+                   (u8_t*)p + SIZEOF_STRUCT_PBUF + PBUF_POOL_BUFSIZE_ALIGNED));
+      q->ref = 1;
+      /* calculate remaining length to be allocated */
+      rem_len -= q->len;
+      /* remember this pbuf for linkage in next iteration */
+      r = q;
+    }
+    /* end of chain */
+    /*r->next = NULL;*/
+
+    break;
+  case PBUF_RAM:
+    /* If pbuf is to be allocated in RAM, allocate memory for it. */
+    p = (struct pbuf*)mem_malloc(LWIP_MEM_ALIGN_SIZE(SIZEOF_STRUCT_PBUF + offset) + LWIP_MEM_ALIGN_SIZE(length));
+    if (p == NULL) {
+      return NULL;
+    }
+    /* Set up internal structure of the pbuf. */
+    p->payload = LWIP_MEM_ALIGN((void *)((u8_t *)p + SIZEOF_STRUCT_PBUF + offset));
+    p->len = p->tot_len = length;
+    p->next = NULL;
+    p->type = type;
+
+    LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned",
+           ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
+    break;
+  /* pbuf references existing (non-volatile static constant) ROM payload? */
+  case PBUF_ROM:
+  /* pbuf references existing (externally allocated) RAM payload? */
+  case PBUF_REF:
+    /* only allocate memory for the pbuf structure */
+    p = memp_malloc(MEMP_PBUF);
+    if (p == NULL) {
+      LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE | 2, ("pbuf_alloc: Could not allocate MEMP_PBUF for PBUF_%s.\n",
+                  (type == PBUF_ROM) ? "ROM" : "REF"));
+      return NULL;
+    }
+    /* caller must set this field properly, afterwards */
+    p->payload = NULL;
+    p->len = p->tot_len = length;
+    p->next = NULL;
+    p->type = type;
+    break;
+  default:
+    LWIP_ASSERT("pbuf_alloc: erroneous type", 0);
+    return NULL;
+  }
+  /* set reference count */
+  p->ref = 1;
+  /* set flags */
+  p->flags = 0;
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE | 3, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p));
+  return p;
+}
+
+
+/**
+ * Shrink a pbuf chain to a desired length.
+ *
+ * @param p pbuf to shrink.
+ * @param new_len desired new length of pbuf chain
+ *
+ * Depending on the desired length, the first few pbufs in a chain might
+ * be skipped and left unchanged. The new last pbuf in the chain will be
+ * resized, and any remaining pbufs will be freed.
+ *
+ * @note If the pbuf is ROM/REF, only the ->tot_len and ->len fields are adjusted.
+ * @note May not be called on a packet queue.
+ *
+ * @note Despite its name, pbuf_realloc cannot grow the size of a pbuf (chain).
+ */
+void
+pbuf_realloc(struct pbuf *p, u16_t new_len)
+{
+  struct pbuf *q;
+  u16_t rem_len; /* remaining length */
+  s32_t grow;
+
+  LWIP_ASSERT("pbuf_realloc: sane p->type", p->type == PBUF_POOL ||
+              p->type == PBUF_ROM ||
+              p->type == PBUF_RAM ||
+              p->type == PBUF_REF);
+
+  /* desired length larger than current length? */
+  if (new_len >= p->tot_len) {
+    /* enlarging not yet supported */
+    return;
+  }
+
+  /* the pbuf chain grows by (new_len - p->tot_len) bytes
+   * (which may be negative in case of shrinking) */
+  grow = new_len - p->tot_len;
+
+  /* first, step over any pbufs that should remain in the chain */
+  rem_len = new_len;
+  q = p;
+  /* should this pbuf be kept? */
+  while (rem_len > q->len) {
+    /* decrease remaining length by pbuf length */
+    rem_len -= q->len;
+    /* decrease total length indicator */
+    LWIP_ASSERT("grow < max_u16_t", grow < 0xffff);
+    q->tot_len += (u16_t)grow;
+    /* proceed to next pbuf in chain */
+    q = q->next;
+  }
+  /* we have now reached the new last pbuf (in q) */
+  /* rem_len == desired length for pbuf q */
+
+  /* shrink allocated memory for PBUF_RAM */
+  /* (other types merely adjust their length fields */
+  if ((q->type == PBUF_RAM) && (rem_len != q->len)) {
+    /* reallocate and adjust the length of the pbuf that will be split */
+    q = mem_realloc(q, (u8_t *)q->payload - (u8_t *)q + rem_len);
+    LWIP_ASSERT("mem_realloc give q == NULL", q != NULL);
+  }
+  /* adjust length fields for new last pbuf */
+  q->len = rem_len;
+  q->tot_len = q->len;
+
+  /* any remaining pbufs in chain? */
+  if (q->next != NULL) {
+    /* free remaining pbufs in chain */
+    pbuf_free(q->next);
+  }
+  /* q is last packet in chain */
+  q->next = NULL;
+
+}
+
+/**
+ * Adjusts the payload pointer to hide or reveal headers in the payload.
+ *
+ * Adjusts the ->payload pointer so that space for a header
+ * (dis)appears in the pbuf payload.
+ *
+ * The ->payload, ->tot_len and ->len fields are adjusted.
+ *
+ * @param p pbuf to change the header size.
+ * @param header_size_increment Number of bytes to increment header size which
+ * increases the size of the pbuf. New space is on the front.
+ * (Using a negative value decreases the header size.)
+ * If hdr_size_inc is 0, this function does nothing and returns succesful.
+ *
+ * PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so
+ * the call will fail. A check is made that the increase in header size does
+ * not move the payload pointer in front of the start of the buffer.
+ * @return non-zero on failure, zero on success.
+ *
+ */
+u8_t
+pbuf_header(struct pbuf *p, s16_t header_size_increment)
+{
+  u16_t type;
+  void *payload;
+  u16_t increment_magnitude;
+
+  LWIP_ASSERT("p != NULL", p != NULL);
+  if ((header_size_increment == 0) || (p == NULL))
+    return 0;
+
+  if (header_size_increment < 0){
+    increment_magnitude = -header_size_increment;
+    /* Check that we aren't going to move off the end of the pbuf */
+    LWIP_ERROR("increment_magnitude <= p->len", (increment_magnitude <= p->len), return 1;);
+  } else {
+    increment_magnitude = header_size_increment;
+#if 0
+    /* Can't assert these as some callers speculatively call
+         pbuf_header() to see if it's OK.  Will return 1 below instead. */
+    /* Check that we've got the correct type of pbuf to work with */
+    LWIP_ASSERT("p->type == PBUF_RAM || p->type == PBUF_POOL",
+                p->type == PBUF_RAM || p->type == PBUF_POOL);
+    /* Check that we aren't going to move off the beginning of the pbuf */
+    LWIP_ASSERT("p->payload - increment_magnitude >= p + SIZEOF_STRUCT_PBUF",
+                (u8_t *)p->payload - increment_magnitude >= (u8_t *)p + SIZEOF_STRUCT_PBUF);
+#endif
+  }
+
+  type = p->type;
+  /* remember current payload pointer */
+  payload = p->payload;
+
+  /* pbuf types containing payloads? */
+  if (type == PBUF_RAM || type == PBUF_POOL) {
+    /* set new payload pointer */
+    p->payload = (u8_t *)p->payload - header_size_increment;
+    /* boundary check fails? */
+    if ((u8_t *)p->payload < (u8_t *)p + SIZEOF_STRUCT_PBUF) {
+      LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_header: failed as %p < %p (not enough space for new header size)\n",
+        (void *)p->payload,
+        (void *)(p + 1)));\
+      /* restore old payload pointer */
+      p->payload = payload;
+      /* bail out unsuccesfully */
+      return 1;
+    }
+  /* pbuf types refering to external payloads? */
+  } else if (type == PBUF_REF || type == PBUF_ROM) {
+    /* hide a header in the payload? */
+    if ((header_size_increment < 0) && (increment_magnitude <= p->len)) {
+      /* increase payload pointer */
+      p->payload = (u8_t *)p->payload - header_size_increment;
+    } else {
+      /* cannot expand payload to front (yet!)
+       * bail out unsuccesfully */
+      return 1;
+    }
+  }
+  else {
+    /* Unknown type */
+    LWIP_ASSERT("bad pbuf type", 0);
+    return 1;
+  }
+  /* modify pbuf length fields */
+  p->len += header_size_increment;
+  p->tot_len += header_size_increment;
+
+  LWIP_DEBUGF(PBUF_DEBUG, ("pbuf_header: old %p new %p (%"S16_F")\n",
+    (void *)payload, (void *)p->payload, header_size_increment));
+
+  return 0;
+}
+
+/**
+ * Dereference a pbuf chain or queue and deallocate any no-longer-used
+ * pbufs at the head of this chain or queue.
+ *
+ * Decrements the pbuf reference count. If it reaches zero, the pbuf is
+ * deallocated.
+ *
+ * For a pbuf chain, this is repeated for each pbuf in the chain,
+ * up to the first pbuf which has a non-zero reference count after
+ * decrementing. So, when all reference counts are one, the whole
+ * chain is free'd.
+ *
+ * @param p The pbuf (chain) to be dereferenced.
+ *
+ * @return the number of pbufs that were de-allocated
+ * from the head of the chain.
+ *
+ * @note MUST NOT be called on a packet queue (Not verified to work yet).
+ * @note the reference counter of a pbuf equals the number of pointers
+ * that refer to the pbuf (or into the pbuf).
+ *
+ * @internal examples:
+ *
+ * Assuming existing chains a->b->c with the following reference
+ * counts, calling pbuf_free(a) results in:
+ *
+ * 1->2->3 becomes ...1->3
+ * 3->3->3 becomes 2->3->3
+ * 1->1->2 becomes ......1
+ * 2->1->1 becomes 1->1->1
+ * 1->1->1 becomes .......
+ *
+ */
+u8_t
+pbuf_free(struct pbuf *p)
+{
+  u16_t type;
+  struct pbuf *q;
+  u8_t count;
+
+  if (p == NULL) {
+    LWIP_ASSERT("p != NULL", p != NULL);
+    /* if assertions are disabled, proceed with debug output */
+    LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE | 2, ("pbuf_free(p == NULL) was called.\n"));
+    return 0;
+  }
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE | 3, ("pbuf_free(%p)\n", (void *)p));
+
+  PERF_START;
+
+  LWIP_ASSERT("pbuf_free: sane type",
+    p->type == PBUF_RAM || p->type == PBUF_ROM ||
+    p->type == PBUF_REF || p->type == PBUF_POOL);
+
+  count = 0;
+  /* de-allocate all consecutive pbufs from the head of the chain that
+   * obtain a zero reference count after decrementing*/
+  while (p != NULL) {
+    u16_t ref;
+    SYS_ARCH_DECL_PROTECT(old_level);
+    /* Since decrementing ref cannot be guaranteed to be a single machine operation
+     * we must protect it. We put the new ref into a local variable to prevent
+     * further protection. */
+    SYS_ARCH_PROTECT(old_level);
+    /* all pbufs in a chain are referenced at least once */
+    LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0);
+    /* decrease reference count (number of pointers to pbuf) */
+    ref = --(p->ref);
+    SYS_ARCH_UNPROTECT(old_level);
+    /* this pbuf is no longer referenced to? */
+    if (ref == 0) {
+      /* remember next pbuf in chain for next iteration */
+      q = p->next;
+      LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: deallocating %p\n", (void *)p));
+      type = p->type;
+      /* is this a pbuf from the pool? */
+      if (type == PBUF_POOL) {
+        memp_free(MEMP_PBUF_POOL, p);
+      /* is this a ROM or RAM referencing pbuf? */
+      } else if (type == PBUF_ROM || type == PBUF_REF) {
+        memp_free(MEMP_PBUF, p);
+      /* type == PBUF_RAM */
+      } else {
+        mem_free(p);
+      }
+      count++;
+      /* proceed to next pbuf */
+      p = q;
+    /* p->ref > 0, this pbuf is still referenced to */
+    /* (and so the remaining pbufs in chain as well) */
+    } else {
+      LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, ref));
+      /* stop walking through the chain */
+      p = NULL;
+    }
+  }
+  PERF_STOP("pbuf_free");
+  /* return number of de-allocated pbufs */
+  return count;
+}
+
+/**
+ * Count number of pbufs in a chain
+ *
+ * @param p first pbuf of chain
+ * @return the number of pbufs in a chain
+ */
+
+u8_t
+pbuf_clen(struct pbuf *p)
+{
+  u8_t len;
+
+  len = 0;
+  while (p != NULL) {
+    ++len;
+    p = p->next;
+  }
+  return len;
+}
+
+/**
+ * Increment the reference count of the pbuf.
+ *
+ * @param p pbuf to increase reference counter of
+ *
+ */
+void
+pbuf_ref(struct pbuf *p)
+{
+  SYS_ARCH_DECL_PROTECT(old_level);
+  /* pbuf given? */
+  if (p != NULL) {
+    SYS_ARCH_PROTECT(old_level);
+    ++(p->ref);
+    SYS_ARCH_UNPROTECT(old_level);
+  }
+}
+
+/**
+ * Concatenate two pbufs (each may be a pbuf chain) and take over
+ * the caller's reference of the tail pbuf.
+ *
+ * @note The caller MAY NOT reference the tail pbuf afterwards.
+ * Use pbuf_chain() for that purpose.
+ *
+ * @see pbuf_chain()
+ */
+
+void
+pbuf_cat(struct pbuf *h, struct pbuf *t)
+{
+  struct pbuf *p;
+
+  LWIP_ERROR("(h != NULL) && (t != NULL) (programmer violates API)",
+             ((h != NULL) && (t != NULL)), return;);
+
+  /* proceed to last pbuf of chain */
+  for (p = h; p->next != NULL; p = p->next) {
+    /* add total length of second chain to all totals of first chain */
+    p->tot_len += t->tot_len;
+  }
+  /* { p is last pbuf of first h chain, p->next == NULL } */
+  LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len);
+  LWIP_ASSERT("p->next == NULL", p->next == NULL);
+  /* add total length of second chain to last pbuf total of first chain */
+  p->tot_len += t->tot_len;
+  /* chain last pbuf of head (p) with first of tail (t) */
+  p->next = t;
+  /* p->next now references t, but the caller will drop its reference to t,
+   * so netto there is no change to the reference count of t.
+   */
+}
+
+/**
+ * Chain two pbufs (or pbuf chains) together.
+ *
+ * The caller MUST call pbuf_free(t) once it has stopped
+ * using it. Use pbuf_cat() instead if you no longer use t.
+ *
+ * @param h head pbuf (chain)
+ * @param t tail pbuf (chain)
+ * @note The pbufs MUST belong to the same packet.
+ * @note MAY NOT be called on a packet queue.
+ *
+ * The ->tot_len fields of all pbufs of the head chain are adjusted.
+ * The ->next field of the last pbuf of the head chain is adjusted.
+ * The ->ref field of the first pbuf of the tail chain is adjusted.
+ *
+ */
+void
+pbuf_chain(struct pbuf *h, struct pbuf *t)
+{
+  pbuf_cat(h, t);
+  /* t is now referenced by h */
+  pbuf_ref(t);
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_FRESH | 2, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t));
+}
+
+/**
+ * Dechains the first pbuf from its succeeding pbufs in the chain.
+ *
+ * Makes p->tot_len field equal to p->len.
+ * @param p pbuf to dechain
+ * @return remainder of the pbuf chain, or NULL if it was de-allocated.
+ * @note May not be called on a packet queue.
+ */
+struct pbuf *
+pbuf_dechain(struct pbuf *p)
+{
+  struct pbuf *q;
+  u8_t tail_gone = 1;
+  /* tail */
+  q = p->next;
+  /* pbuf has successor in chain? */
+  if (q != NULL) {
+    /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */
+    LWIP_ASSERT("p->tot_len == p->len + q->tot_len", q->tot_len == p->tot_len - p->len);
+    /* enforce invariant if assertion is disabled */
+    q->tot_len = p->tot_len - p->len;
+    /* decouple pbuf from remainder */
+    p->next = NULL;
+    /* total length of pbuf p is its own length only */
+    p->tot_len = p->len;
+    /* q is no longer referenced by p, free it */
+    LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_STATE, ("pbuf_dechain: unreferencing %p\n", (void *)q));
+    tail_gone = pbuf_free(q);
+    if (tail_gone > 0) {
+      LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_STATE,
+                  ("pbuf_dechain: deallocated %p (as it is no longer referenced)\n", (void *)q));
+    }
+    /* return remaining tail or NULL if deallocated */
+  }
+  /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */
+  LWIP_ASSERT("p->tot_len == p->len", p->tot_len == p->len);
+  return ((tail_gone > 0) ? NULL : q);
+}
+
+/**
+ *
+ * Create PBUF_RAM copies of pbufs.
+ *
+ * Used to queue packets on behalf of the lwIP stack, such as
+ * ARP based queueing.
+ *
+ * @note You MUST explicitly use p = pbuf_take(p);
+ *
+ * @note Only one packet is copied, no packet queue!
+ *
+ * @param p_to pbuf source of the copy
+ * @param p_from pbuf destination of the copy
+ *
+ * @return ERR_OK if pbuf was copied
+ *         ERR_ARG if one of the pbufs is NULL or p_to is not big
+ *                 enough to hold p_from
+ */
+err_t
+pbuf_copy(struct pbuf *p_to, struct pbuf *p_from)
+{
+  u16_t offset_to=0, offset_from=0, len;
+
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE | 3, ("pbuf_copy(%p, %p)\n",
+    (void*)p_to, (void*)p_from));
+
+  /* is the target big enough to hold the source? */
+  LWIP_ERROR("pbuf_copy: target not big enough to hold source", ((p_to != NULL) &&
+             (p_from != NULL) && (p_to->tot_len >= p_from->tot_len)), return ERR_ARG;);
+
+  /* iterate through pbuf chain */
+  do
+  {
+    LWIP_ASSERT("p_to != NULL", p_to != NULL);
+    /* copy one part of the original chain */
+    if ((p_to->len - offset_to) >= (p_from->len - offset_from)) {
+      /* complete current p_from fits into current p_to */
+      len = p_from->len - offset_from;
+    } else {
+      /* current p_from does not fit into current p_to */
+      len = p_to->len - offset_to;
+    }
+    MEMCPY((u8_t*)p_to->payload + offset_to, (u8_t*)p_from->payload + offset_from, len);
+    offset_to += len;
+    offset_from += len;
+    LWIP_ASSERT("offset_to <= p_to->len", offset_to <= p_to->len);
+    if (offset_to == p_to->len) {
+      /* on to next p_to (if any) */
+      offset_to = 0;
+      p_to = p_to->next;
+    }
+    LWIP_ASSERT("offset_from <= p_from->len", offset_from <= p_from->len);
+    if (offset_from >= p_from->len) {
+      /* on to next p_from (if any) */
+      offset_from = 0;
+      p_from = p_from->next;
+    }
+
+    if((p_from != NULL) && (p_from->len == p_from->tot_len)) {
+      /* don't copy more than one packet! */
+      LWIP_ERROR("pbuf_copy() does not allow packet queues!\n",
+                 (p_from->next == NULL), return ERR_VAL;);
+    }
+    if((p_to != NULL) && (p_to->len == p_to->tot_len)) {
+      /* don't copy more than one packet! */
+      LWIP_ERROR("pbuf_copy() does not allow packet queues!\n",
+                  (p_to->next == NULL), return ERR_VAL;);
+    }
+  } while (p_from);
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE | 1, ("pbuf_copy: end of chain reached.\n"));
+  return ERR_OK;
+}
+
+/**
+ * Copy (part of) the contents of a packet buffer
+ * to an application supplied buffer.
+ *
+ * @param buf the pbuf from which to copy data
+ * @param dataptr the application supplied buffer
+ * @param len length of data to copy (dataptr must be big enough)
+ * @param offset offset into the packet buffer from where to begin copying len bytes
+ */
+u16_t
+pbuf_copy_partial(struct pbuf *buf, void *dataptr, u16_t len, u16_t offset)
+{
+  struct pbuf *p;
+  u16_t left;
+  u16_t buf_copy_len;
+  u16_t copied_total = 0;
+
+  LWIP_ERROR("netbuf_copy_partial: invalid buf", (buf != NULL), return 0;);
+  LWIP_ERROR("netbuf_copy_partial: invalid dataptr", (dataptr != NULL), return 0;);
+
+  left = 0;
+
+  if((buf == NULL) || (dataptr == NULL)) {
+    return 0;
+  }
+
+  /* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */
+  for(p = buf; len != 0 && p != NULL; p = p->next) {
+    if ((offset != 0) && (offset >= p->len)) {
+      /* don't copy from this buffer -> on to the next */
+      offset -= p->len;
+    } else {
+      /* copy from this buffer. maybe only partially. */
+      buf_copy_len = p->len - offset;
+      if (buf_copy_len > len)
+          buf_copy_len = len;
+      /* copy the necessary parts of the buffer */
+      MEMCPY(&((char*)dataptr)[left], &((char*)p->payload)[offset], buf_copy_len);
+      copied_total += buf_copy_len;
+      left += buf_copy_len;
+      len -= buf_copy_len;
+      offset = 0;
+    }
+  }
+  return copied_total;
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/raw.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/raw.c
new file mode 100644
index 0000000..2ba693b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/raw.c
@@ -0,0 +1,336 @@
+/**
+ * @file
+ * Implementation of raw protocol PCBs for low-level handling of
+ * different types of protocols besides (or overriding) those
+ * already available in lwIP.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/def.h"
+#include "lwip/memp.h"
+#include "lwip/inet.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/raw.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+#include "arch/perf.h"
+
+#include 
+
+/** The list of RAW PCBs */
+static struct raw_pcb *raw_pcbs;
+
+/**
+ * Determine if in incoming IP packet is covered by a RAW PCB
+ * and if so, pass it to a user-provided receive callback function.
+ *
+ * Given an incoming IP datagram (as a chain of pbufs) this function
+ * finds a corresponding RAW PCB and calls the corresponding receive
+ * callback function.
+ *
+ * @param p pbuf to be demultiplexed to a RAW PCB.
+ * @param inp network interface on which the datagram was received.
+ * @return - 1 if the packet has been eaten by a RAW PCB receive
+ *           callback function. The caller MAY NOT not reference the
+ *           packet any longer, and MAY NOT call pbuf_free().
+ * @return - 0 if packet is not eaten (pbuf is still referenced by the
+ *           caller).
+ *
+ */
+u8_t
+raw_input(struct pbuf *p, struct netif *inp)
+{
+  struct raw_pcb *pcb, *prev;
+  struct ip_hdr *iphdr;
+  s16_t proto;
+  u8_t eaten = 0;
+
+  LWIP_UNUSED_ARG(inp);
+
+  iphdr = p->payload;
+  proto = IPH_PROTO(iphdr);
+
+  prev = NULL;
+  pcb = raw_pcbs;
+  /* loop through all raw pcbs until the packet is eaten by one */
+  /* this allows multiple pcbs to match against the packet by design */
+  while ((eaten == 0) && (pcb != NULL)) {
+    if (pcb->protocol == proto) {
+      /* receive callback function available? */
+      if (pcb->recv != NULL) {
+        /* the receive callback function did not eat the packet? */
+        if (pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src)) != 0)
+        {
+          /* receive function ate the packet */
+          p = NULL;
+          eaten = 1;
+          if (prev != NULL) {
+          /* move the pcb to the front of raw_pcbs so that is
+             found faster next time */
+            prev->next = pcb->next;
+            pcb->next = raw_pcbs;
+            raw_pcbs = pcb;
+          }
+        }
+      }
+      /* no receive callback function was set for this raw PCB */
+      /* drop the packet */
+    }
+    prev = pcb;
+    pcb = pcb->next;
+  }
+  return eaten;
+}
+
+/**
+ * Bind a RAW PCB.
+ *
+ * @param pcb RAW PCB to be bound with a local address ipaddr.
+ * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to
+ * bind to all local interfaces.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_USE. The specified IP address is already bound to by
+ * another RAW PCB.
+ *
+ * @see raw_disconnect()
+ */
+err_t
+raw_bind(struct raw_pcb *pcb, struct ip_addr *ipaddr)
+{
+  ip_addr_set(&pcb->local_ip, ipaddr);
+  return ERR_OK;
+}
+
+/**
+ * Connect an RAW PCB. This function is required by upper layers
+ * of lwip. Using the raw api you could use raw_sendto() instead
+ *
+ * This will associate the RAW PCB with the remote address.
+ *
+ * @param pcb RAW PCB to be connected with remote address ipaddr and port.
+ * @param ipaddr remote IP address to connect with.
+ *
+ * @return lwIP error code
+ *
+ * @see raw_disconnect() and raw_sendto()
+ */
+err_t
+raw_connect(struct raw_pcb *pcb, struct ip_addr *ipaddr)
+{
+  ip_addr_set(&pcb->remote_ip, ipaddr);
+  return ERR_OK;
+}
+
+
+/**
+ * Set the callback function for received packets that match the
+ * raw PCB's protocol and binding.
+ *
+ * The callback function MUST either
+ * - eat the packet by calling pbuf_free() and returning non-zero. The
+ *   packet will not be passed to other raw PCBs or other protocol layers.
+ * - not free the packet, and return zero. The packet will be matched
+ *   against further PCBs and/or forwarded to another protocol layers.
+ *
+ * @return non-zero if the packet was free()d, zero if the packet remains
+ * available for others.
+ */
+void
+raw_recv(struct raw_pcb *pcb,
+         u8_t (* recv)(void *arg, struct raw_pcb *upcb, struct pbuf *p,
+                      struct ip_addr *addr),
+         void *recv_arg)
+{
+  /* remember recv() callback and user data */
+  pcb->recv = recv;
+  pcb->recv_arg = recv_arg;
+}
+
+/**
+ * Send the raw IP packet to the given address. Note that actually you cannot
+ * modify the IP headers (this is inconsistent with the receive callback where
+ * you actually get the IP headers), you can only specify the IP payload here.
+ * It requires some more changes in lwIP. (there will be a raw_send() function
+ * then.)
+ *
+ * @param pcb the raw pcb which to send
+ * @param p the IP payload to send
+ * @param ipaddr the destination address of the IP packet
+ *
+ */
+err_t
+raw_sendto(struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr)
+{
+  err_t err;
+  struct netif *netif;
+  struct ip_addr *src_ip;
+  struct pbuf *q; /* q will be sent down the stack */
+
+  LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE | 3, ("raw_sendto\n"));
+
+  /* not enough space to add an IP header to first pbuf in given p chain? */
+  if (pbuf_header(p, IP_HLEN)) {
+    /* allocate header in new pbuf */
+    q = pbuf_alloc(PBUF_IP, 0, PBUF_RAM);
+    /* new header pbuf could not be allocated? */
+    if (q == NULL) {
+      LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE | 2, ("raw_sendto: could not allocate header\n"));
+      return ERR_MEM;
+    }
+    /* chain header q in front of given pbuf p */
+    pbuf_chain(q, p);
+    /* { first pbuf q points to header pbuf } */
+    LWIP_DEBUGF(RAW_DEBUG, ("raw_sendto: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
+  }  else {
+    /* first pbuf q equals given pbuf */
+    q = p;
+    if(pbuf_header(q, -IP_HLEN)) {
+      LWIP_ASSERT("Can't restore header we just removed!", 0);
+      return ERR_MEM;
+    }
+  }
+
+  if ((netif = ip_route(ipaddr)) == NULL) {
+    LWIP_DEBUGF(RAW_DEBUG | 1, ("raw_sendto: No route to 0x%"X32_F"\n", ipaddr->addr));
+    /* free any temporary header pbuf allocated by pbuf_header() */
+    if (q != p) {
+      pbuf_free(q);
+    }
+    return ERR_RTE;
+  }
+
+  if (ip_addr_isany(&pcb->local_ip)) {
+    /* use outgoing network interface IP address as source address */
+    src_ip = &(netif->ip_addr);
+  } else {
+    /* use RAW PCB local IP address as source address */
+    src_ip = &(pcb->local_ip);
+  }
+
+#if LWIP_NETIF_HWADDRHINT
+  netif->addr_hint = &(pcb->addr_hint);
+#endif /* LWIP_NETIF_HWADDRHINT*/
+  err = ip_output_if (q, src_ip, ipaddr, pcb->ttl, pcb->tos, pcb->protocol, netif);
+#if LWIP_NETIF_HWADDRHINT
+  netif->addr_hint = NULL;
+#endif /* LWIP_NETIF_HWADDRHINT*/
+
+  /* did we chain a header earlier? */
+  if (q != p) {
+    /* free the header */
+    pbuf_free(q);
+  }
+  return err;
+}
+
+/**
+ * Send the raw IP packet to the address given by raw_connect()
+ *
+ * @param pcb the raw pcb which to send
+ * @param p the IP payload to send
+ *
+ */
+err_t
+raw_send(struct raw_pcb *pcb, struct pbuf *p)
+{
+  return raw_sendto(pcb, p, &pcb->remote_ip);
+}
+
+/**
+ * Remove an RAW PCB.
+ *
+ * @param pcb RAW PCB to be removed. The PCB is removed from the list of
+ * RAW PCB's and the data structure is freed from memory.
+ *
+ * @see raw_new()
+ */
+void
+raw_remove(struct raw_pcb *pcb)
+{
+  struct raw_pcb *pcb2;
+  /* pcb to be removed is first in list? */
+  if (raw_pcbs == pcb) {
+    /* make list start at 2nd pcb */
+    raw_pcbs = raw_pcbs->next;
+    /* pcb not 1st in list */
+  } else {
+    for(pcb2 = raw_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
+      /* find pcb in raw_pcbs list */
+      if (pcb2->next != NULL && pcb2->next == pcb) {
+        /* remove pcb from list */
+        pcb2->next = pcb->next;
+      }
+    }
+  }
+  memp_free(MEMP_RAW_PCB, pcb);
+}
+
+/**
+ * Create a RAW PCB.
+ *
+ * @return The RAW PCB which was created. NULL if the PCB data structure
+ * could not be allocated.
+ *
+ * @param proto the protocol number of the IPs payload (e.g. IP_PROTO_ICMP)
+ *
+ * @see raw_remove()
+ */
+struct raw_pcb *
+raw_new(u8_t proto) {
+  struct raw_pcb *pcb;
+
+  LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE | 3, ("raw_new\n"));
+
+  pcb = memp_malloc(MEMP_RAW_PCB);
+  /* could allocate RAW PCB? */
+  if (pcb != NULL) {
+    /* initialize PCB to all zeroes */
+    memset(pcb, 0, sizeof(struct raw_pcb));
+    pcb->protocol = proto;
+    pcb->ttl = RAW_TTL;
+    pcb->next = raw_pcbs;
+    raw_pcbs = pcb;
+  }
+  return pcb;
+}
+
+#endif /* LWIP_RAW */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/snmp/asn1_dec.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/snmp/asn1_dec.c
new file mode 100644
index 0000000..87288ac
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/snmp/asn1_dec.c
@@ -0,0 +1,657 @@
+/**
+ * @file
+ * Abstract Syntax Notation One (ISO 8824, 8825) decoding
+ *
+ * @todo not optimised (yet), favor correctness over speed, favor speed over size
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/snmp_asn1.h"
+
+/**
+ * Retrieves type field from incoming pbuf chain.
+ *
+ * @param p points to a pbuf holding an ASN1 coded type field
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded type field
+ * @param type return ASN1 type
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ */
+err_t
+snmp_asn1_dec_type(struct pbuf *p, u16_t ofs, u8_t *type)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+      *type = *msg_ptr;
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Decodes length field from incoming pbuf chain into host length.
+ *
+ * @param p points to a pbuf holding an ASN1 coded length
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded length
+ * @param octets_used returns number of octets used by the length code
+ * @param length return host order length, upto 64k
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ */
+err_t
+snmp_asn1_dec_length(struct pbuf *p, u16_t ofs, u8_t *octets_used, u16_t *length)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+
+      if (*msg_ptr < 0x80)
+      {
+        /* primitive definite length format */
+        *octets_used = 1;
+        *length = *msg_ptr;
+        return ERR_OK;
+      }
+      else if (*msg_ptr == 0x80)
+      {
+        /* constructed indefinite length format, termination with two zero octets */
+        u8_t zeros;
+        u8_t i;
+
+        *length = 0;
+        zeros = 0;
+        while (zeros != 2)
+        {
+          i = 2;
+          while (i > 0)
+          {
+            i--;
+            (*length) += 1;
+            ofs += 1;
+            if (ofs >= plen)
+            {
+              /* next octet in next pbuf */
+              p = p->next;
+              if (p == NULL) { return ERR_ARG; }
+              msg_ptr = p->payload;
+              plen += p->len;
+            }
+            else
+            {
+              /* next octet in same pbuf */
+              msg_ptr++;
+            }
+            if (*msg_ptr == 0)
+            {
+              zeros++;
+              if (zeros == 2)
+              {
+                /* stop while (i > 0) */
+                i = 0;
+              }
+            }
+            else
+            {
+              zeros = 0;
+            }
+          }
+        }
+        *octets_used = 1;
+        return ERR_OK;
+      }
+      else if (*msg_ptr == 0x81)
+      {
+        /* constructed definite length format, one octet */
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+        *length = *msg_ptr;
+        *octets_used = 2;
+        return ERR_OK;
+      }
+      else if (*msg_ptr == 0x82)
+      {
+        u8_t i;
+
+        /* constructed definite length format, two octets */
+        i = 2;
+        while (i > 0)
+        {
+          i--;
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+          if (i == 0)
+          {
+            /* least significant length octet */
+            *length |= *msg_ptr;
+          }
+          else
+          {
+            /* most significant length octet */
+            *length = (*msg_ptr) << 8;
+          }
+        }
+        *octets_used = 3;
+        return ERR_OK;
+      }
+      else
+      {
+        /* constructed definite length format 3..127 octets, this is too big (>64k) */
+        /**  @todo: do we need to accept inefficient codings with many leading zero's? */
+        *octets_used = 1 + ((*msg_ptr) & 0x7f);
+        return ERR_ARG;
+      }
+    }
+    p = p->next;
+  }
+
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Decodes positive integer (counter, gauge, timeticks) into u32_t.
+ *
+ * @param p points to a pbuf holding an ASN1 coded integer
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded integer
+ * @param len length of the coded integer field
+ * @param value return host order integer
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ *
+ * @note ASN coded integers are _always_ signed. E.g. +0xFFFF is coded
+ * as 0x00,0xFF,0xFF. Note the leading sign octet. A positive value
+ * of 0xFFFFFFFF is preceded with 0x00 and the length is 5 octets!!
+ */
+err_t
+snmp_asn1_dec_u32t(struct pbuf *p, u16_t ofs, u16_t len, u32_t *value)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+      if ((len > 0) && (len < 6))
+      {
+        /* start from zero */
+        *value = 0;
+        if (*msg_ptr & 0x80)
+        {
+          /* negative, expecting zero sign bit! */
+          return ERR_ARG;
+        }
+        else
+        {
+          /* positive */
+          if ((len > 1) && (*msg_ptr == 0))
+          {
+            /* skip leading "sign byte" octet 0x00 */
+            len--;
+            ofs += 1;
+            if (ofs >= plen)
+            {
+              /* next octet in next pbuf */
+              p = p->next;
+              if (p == NULL) { return ERR_ARG; }
+              msg_ptr = p->payload;
+              plen += p->len;
+            }
+            else
+            {
+              /* next octet in same pbuf */
+              msg_ptr++;
+            }
+          }
+        }
+        /* OR octets with value */
+        while (len > 1)
+        {
+          len--;
+          *value |= *msg_ptr;
+          *value <<= 8;
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+        }
+        *value |= *msg_ptr;
+        return ERR_OK;
+      }
+      else
+      {
+        return ERR_ARG;
+      }
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Decodes integer into s32_t.
+ *
+ * @param p points to a pbuf holding an ASN1 coded integer
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded integer
+ * @param len length of the coded integer field
+ * @param value return host order integer
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ *
+ * @note ASN coded integers are _always_ signed!
+ */
+err_t
+snmp_asn1_dec_s32t(struct pbuf *p, u16_t ofs, u16_t len, s32_t *value)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+#if BYTE_ORDER == LITTLE_ENDIAN
+  u8_t *lsb_ptr = (u8_t*)value;
+#endif
+#if BYTE_ORDER == BIG_ENDIAN
+  u8_t *lsb_ptr = (u8_t*)value + sizeof(s32_t) - 1;
+#endif
+  u8_t sign;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+      if ((len > 0) && (len < 5))
+      {
+        if (*msg_ptr & 0x80)
+        {
+          /* negative, start from -1 */
+          *value = -1;
+          sign = 1;
+        }
+        else
+        {
+          /* positive, start from 0 */
+          *value = 0;
+          sign = 0;
+        }
+        /* OR/AND octets with value */
+        while (len > 1)
+        {
+          len--;
+          if (sign)
+          {
+            *lsb_ptr &= *msg_ptr;
+            *value <<= 8;
+            *lsb_ptr |= 255;
+          }
+          else
+          {
+            *lsb_ptr |= *msg_ptr;
+            *value <<= 8;
+          }
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+        }
+        if (sign)
+        {
+          *lsb_ptr &= *msg_ptr;
+        }
+        else
+        {
+          *lsb_ptr |= *msg_ptr;
+        }
+        return ERR_OK;
+      }
+      else
+      {
+        return ERR_ARG;
+      }
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Decodes object identifier from incoming message into array of s32_t.
+ *
+ * @param p points to a pbuf holding an ASN1 coded object identifier
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded object identifier
+ * @param len length of the coded object identifier
+ * @param oid return object identifier struct
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ */
+err_t
+snmp_asn1_dec_oid(struct pbuf *p, u16_t ofs, u16_t len, struct snmp_obj_id *oid)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+  s32_t *oid_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+
+      oid->len = 0;
+      oid_ptr = &oid->id[0];
+      if (len > 0)
+      {
+        /* first compressed octet */
+        if (*msg_ptr == 0x2B)
+        {
+          /* (most) common case 1.3 (iso.org) */
+          *oid_ptr = 1;
+          oid_ptr++;
+          *oid_ptr = 3;
+          oid_ptr++;
+        }
+        else if (*msg_ptr < 40)
+        {
+          *oid_ptr = 0;
+          oid_ptr++;
+          *oid_ptr = *msg_ptr;
+          oid_ptr++;
+        }
+        else if (*msg_ptr < 80)
+        {
+          *oid_ptr = 1;
+          oid_ptr++;
+          *oid_ptr = (*msg_ptr) - 40;
+          oid_ptr++;
+        }
+        else
+        {
+          *oid_ptr = 2;
+          oid_ptr++;
+          *oid_ptr = (*msg_ptr) - 80;
+          oid_ptr++;
+        }
+        oid->len = 2;
+      }
+      else
+      {
+        /* accepting zero length identifiers e.g. for
+           getnext operation. uncommon but valid */
+        return ERR_OK;
+      }
+      len--;
+      if (len > 0)
+      {
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+      }
+      while ((len > 0) && (oid->len < LWIP_SNMP_OBJ_ID_LEN))
+      {
+        /* sub-identifier uses multiple octets */
+        if (*msg_ptr & 0x80)
+        {
+          s32_t sub_id = 0;
+
+          while ((*msg_ptr & 0x80) && (len > 1))
+          {
+            len--;
+            sub_id = (sub_id << 7) + (*msg_ptr & ~0x80);
+            ofs += 1;
+            if (ofs >= plen)
+            {
+              /* next octet in next pbuf */
+              p = p->next;
+              if (p == NULL) { return ERR_ARG; }
+              msg_ptr = p->payload;
+              plen += p->len;
+            }
+            else
+            {
+              /* next octet in same pbuf */
+              msg_ptr++;
+            }
+          }
+          if (!(*msg_ptr & 0x80) && (len > 0))
+          {
+            /* last octet sub-identifier */
+            len--;
+            sub_id = (sub_id << 7) + *msg_ptr;
+            *oid_ptr = sub_id;
+          }
+        }
+        else
+        {
+          /* !(*msg_ptr & 0x80) sub-identifier uses single octet */
+          len--;
+          *oid_ptr = *msg_ptr;
+        }
+        if (len > 0)
+        {
+          /* remaining oid bytes available ... */
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+        }
+        oid_ptr++;
+        oid->len++;
+      }
+      if (len == 0)
+      {
+        /* len == 0, end of oid */
+        return ERR_OK;
+      }
+      else
+      {
+        /* len > 0, oid->len == LWIP_SNMP_OBJ_ID_LEN or malformed encoding */
+        return ERR_ARG;
+      }
+
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Decodes (copies) raw data (ip-addresses, octet strings, opaque encoding)
+ * from incoming message into array.
+ *
+ * @param p points to a pbuf holding an ASN1 coded raw data
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded raw data
+ * @param len length of the coded raw data (zero is valid, e.g. empty string!)
+ * @param raw_len length of the raw return value
+ * @param raw return raw bytes
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ */
+err_t
+snmp_asn1_dec_raw(struct pbuf *p, u16_t ofs, u16_t len, u16_t raw_len, u8_t *raw)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  if (len > 0)
+  {
+    plen = 0;
+    while (p != NULL)
+    {
+      base = plen;
+      plen += p->len;
+      if (ofs < plen)
+      {
+        msg_ptr = p->payload;
+        msg_ptr += ofs - base;
+        if (raw_len >= len)
+        {
+          while (len > 1)
+          {
+            /* copy len - 1 octets */
+            len--;
+            *raw = *msg_ptr;
+            raw++;
+            ofs += 1;
+            if (ofs >= plen)
+            {
+              /* next octet in next pbuf */
+              p = p->next;
+              if (p == NULL) { return ERR_ARG; }
+              msg_ptr = p->payload;
+              plen += p->len;
+            }
+            else
+            {
+              /* next octet in same pbuf */
+              msg_ptr++;
+            }
+          }
+          /* copy last octet */
+          *raw = *msg_ptr;
+          return ERR_OK;
+        }
+        else
+        {
+          /* raw_len < len, not enough dst space */
+          return ERR_ARG;
+        }
+      }
+      p = p->next;
+    }
+    /* p == NULL, ofs >= plen */
+    return ERR_ARG;
+  }
+  else
+  {
+    /* len == 0, empty string */
+    return ERR_OK;
+  }
+}
+
+#endif /* LWIP_SNMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/snmp/asn1_enc.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/snmp/asn1_enc.c
new file mode 100644
index 0000000..ac29636
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/snmp/asn1_enc.c
@@ -0,0 +1,611 @@
+/**
+ * @file
+ * Abstract Syntax Notation One (ISO 8824, 8825) encoding
+ *
+ * @todo not optimised (yet), favor correctness over speed, favor speed over size
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/snmp_asn1.h"
+
+/**
+ * Returns octet count for length.
+ *
+ * @param length
+ * @param octets_needed points to the return value
+ */
+void
+snmp_asn1_enc_length_cnt(u16_t length, u8_t *octets_needed)
+{
+  if (length < 0x80U)
+  {
+    *octets_needed = 1;
+  }
+  else if (length < 0x100U)
+  {
+    *octets_needed = 2;
+  }
+  else
+  {
+    *octets_needed = 3;
+  }
+}
+
+/**
+ * Returns octet count for an u32_t.
+ *
+ * @param value
+ * @param octets_needed points to the return value
+ *
+ * @note ASN coded integers are _always_ signed. E.g. +0xFFFF is coded
+ * as 0x00,0xFF,0xFF. Note the leading sign octet. A positive value
+ * of 0xFFFFFFFF is preceded with 0x00 and the length is 5 octets!!
+ */
+void
+snmp_asn1_enc_u32t_cnt(u32_t value, u16_t *octets_needed)
+{
+  if (value < 0x80UL)
+  {
+    *octets_needed = 1;
+  }
+  else if (value < 0x8000UL)
+  {
+    *octets_needed = 2;
+  }
+  else if (value < 0x800000UL)
+  {
+    *octets_needed = 3;
+  }
+  else if (value < 0x80000000UL)
+  {
+    *octets_needed = 4;
+  }
+  else
+  {
+    *octets_needed = 5;
+  }
+}
+
+/**
+ * Returns octet count for an s32_t.
+ *
+ * @param value
+ * @param octets_needed points to the return value
+ *
+ * @note ASN coded integers are _always_ signed.
+ */
+void
+snmp_asn1_enc_s32t_cnt(s32_t value, u16_t *octets_needed)
+{
+  if (value < 0)
+  {
+    value = ~value;
+  }
+  if (value < 0x80L)
+  {
+    *octets_needed = 1;
+  }
+  else if (value < 0x8000L)
+  {
+    *octets_needed = 2;
+  }
+  else if (value < 0x800000L)
+  {
+    *octets_needed = 3;
+  }
+  else
+  {
+    *octets_needed = 4;
+  }
+}
+
+/**
+ * Returns octet count for an object identifier.
+ *
+ * @param ident_len object identifier array length
+ * @param ident points to object identifier array
+ * @param octets_needed points to the return value
+ */
+void
+snmp_asn1_enc_oid_cnt(u8_t ident_len, s32_t *ident, u16_t *octets_needed)
+{
+  s32_t sub_id;
+  u8_t cnt;
+
+  cnt = 0;
+  if (ident_len > 1)
+  {
+    /* compressed prefix in one octet */
+    cnt++;
+    ident_len -= 2;
+    ident += 2;
+  }
+  while(ident_len > 0)
+  {
+    ident_len--;
+    sub_id = *ident;
+
+    sub_id >>= 7;
+    cnt++;
+    while(sub_id > 0)
+    {
+      sub_id >>= 7;
+      cnt++;
+    }
+    ident++;
+  }
+  *octets_needed = cnt;
+}
+
+/**
+ * Encodes ASN type field into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode value into
+ * @param ofs points to the offset within the pbuf chain
+ * @param type input ASN1 type
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ */
+err_t
+snmp_asn1_enc_type(struct pbuf *p, u16_t ofs, u8_t type)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+      *msg_ptr = type;
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Encodes host order length field into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode length into
+ * @param ofs points to the offset within the pbuf chain
+ * @param length is the host order length to be encoded
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ */
+err_t
+snmp_asn1_enc_length(struct pbuf *p, u16_t ofs, u16_t length)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+
+      if (length < 0x80)
+      {
+        *msg_ptr = length;
+        return ERR_OK;
+      }
+      else if (length < 0x100)
+      {
+        *msg_ptr = 0x81;
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+        *msg_ptr = length;
+        return ERR_OK;
+      }
+      else
+      {
+        u8_t i;
+
+        /* length >= 0x100 && length <= 0xFFFF */
+        *msg_ptr = 0x82;
+        i = 2;
+        while (i > 0)
+        {
+          i--;
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+          if (i == 0)
+          {
+            /* least significant length octet */
+            *msg_ptr = length;
+          }
+          else
+          {
+            /* most significant length octet */
+            *msg_ptr = length >> 8;
+          }
+        }
+        return ERR_OK;
+      }
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Encodes u32_t (counter, gauge, timeticks) into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode value into
+ * @param ofs points to the offset within the pbuf chain
+ * @param octets_needed encoding length (from snmp_asn1_enc_u32t_cnt())
+ * @param value is the host order u32_t value to be encoded
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ *
+ * @see snmp_asn1_enc_u32t_cnt()
+ */
+err_t
+snmp_asn1_enc_u32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, u32_t value)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+
+      if (octets_needed == 5)
+      {
+        /* not enough bits in 'value' add leading 0x00 */
+        octets_needed--;
+        *msg_ptr = 0x00;
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+      }
+      while (octets_needed > 1)
+      {
+        octets_needed--;
+        *msg_ptr = value >> (octets_needed << 3);
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+      }
+      /* (only) one least significant octet */
+      *msg_ptr = value;
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Encodes s32_t integer into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode value into
+ * @param ofs points to the offset within the pbuf chain
+ * @param octets_needed encoding length (from snmp_asn1_enc_s32t_cnt())
+ * @param value is the host order s32_t value to be encoded
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ *
+ * @see snmp_asn1_enc_s32t_cnt()
+ */
+err_t
+snmp_asn1_enc_s32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, s32_t value)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+
+      while (octets_needed > 1)
+      {
+        octets_needed--;
+        *msg_ptr = value >> (octets_needed << 3);
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+      }
+      /* (only) one least significant octet */
+      *msg_ptr = value;
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Encodes object identifier into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode oid into
+ * @param ofs points to the offset within the pbuf chain
+ * @param ident_len object identifier array length
+ * @param ident points to object identifier array
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ */
+err_t
+snmp_asn1_enc_oid(struct pbuf *p, u16_t ofs, u8_t ident_len, s32_t *ident)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+
+      if (ident_len > 1)
+      {
+        if ((ident[0] == 1) && (ident[1] == 3))
+        {
+          /* compressed (most common) prefix .iso.org */
+          *msg_ptr = 0x2b;
+        }
+        else
+        {
+          /* calculate prefix */
+          *msg_ptr = (ident[0] * 40) + ident[1];
+        }
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+        ident_len -= 2;
+        ident += 2;
+      }
+      else
+      {
+/* @bug:  allow empty varbinds for symmetry (we must decode them for getnext), allow partial compression??  */
+        /* ident_len <= 1, at least we need zeroDotZero (0.0) (ident_len == 2) */
+        return ERR_ARG;
+      }
+      while (ident_len > 0)
+      {
+        s32_t sub_id;
+        u8_t shift, tail;
+
+        ident_len--;
+        sub_id = *ident;
+        tail = 0;
+        shift = 28;
+        while(shift > 0)
+        {
+          u8_t code;
+
+          code = sub_id >> shift;
+          if ((code != 0) || (tail != 0))
+          {
+            tail = 1;
+            *msg_ptr = code | 0x80;
+            ofs += 1;
+            if (ofs >= plen)
+            {
+              /* next octet in next pbuf */
+              p = p->next;
+              if (p == NULL) { return ERR_ARG; }
+              msg_ptr = p->payload;
+              plen += p->len;
+            }
+            else
+            {
+              /* next octet in same pbuf */
+              msg_ptr++;
+            }
+          }
+          shift -= 7;
+        }
+        *msg_ptr = (u8_t)sub_id & 0x7F;
+        if (ident_len > 0)
+        {
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+        }
+        /* proceed to next sub-identifier */
+        ident++;
+      }
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Encodes raw data (octet string, opaque) into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode raw data into
+ * @param ofs points to the offset within the pbuf chain
+ * @param raw_len raw data length
+ * @param raw points raw data
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ */
+err_t
+snmp_asn1_enc_raw(struct pbuf *p, u16_t ofs, u8_t raw_len, u8_t *raw)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+
+      while (raw_len > 1)
+      {
+        /* copy raw_len - 1 octets */
+        raw_len--;
+        *msg_ptr = *raw;
+        raw++;
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+      }
+      if (raw_len > 0)
+      {
+        /* copy last or single octet */
+        *msg_ptr = *raw;
+      }
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+#endif /* LWIP_SNMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/snmp/mib2.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/snmp/mib2.c
new file mode 100644
index 0000000..0e582c1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/snmp/mib2.c
@@ -0,0 +1,4126 @@
+/**
+ * @file
+ * Management Information Base II (RFC1213) objects and functions.
+ *
+ * @note the object identifiers for this MIB-2 and private MIB tree
+ * must be kept in sorted ascending order. This to ensure correct getnext operation.
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/snmp.h"
+#include "lwip/netif.h"
+#include "lwip/ip.h"
+#include "lwip/ip_frag.h"
+#include "lwip/tcp.h"
+#include "lwip/udp.h"
+#include "lwip/snmp_asn1.h"
+#include "lwip/snmp_structs.h"
+#include "netif/etharp.h"
+
+/**
+ * IANA assigned enterprise ID for lwIP is 26381
+ * @see http://www.iana.org/assignments/enterprise-numbers
+ *
+ * @note this enterprise ID is assigned to the lwIP project,
+ * all object identifiers living under this ID are assigned
+ * by the lwIP maintainers (contact Christiaan Simons)!
+ * @note don't change this define, use snmp_set_sysobjid()
+ *
+ * If you need to create your own private MIB you'll need
+ * to apply for your own enterprise ID with IANA:
+ * http://www.iana.org/numbers.html
+ */
+#define SNMP_ENTERPRISE_ID 26381
+#define SNMP_SYSOBJID_LEN 7
+#define SNMP_SYSOBJID {1, 3, 6, 1, 4, 1, SNMP_ENTERPRISE_ID}
+
+#ifndef SNMP_SYSSERVICES
+#define SNMP_SYSSERVICES ((1 << 6) | (1 << 3) | ((IP_FORWARD) << 2))
+#endif
+
+#ifndef SNMP_GET_SYSUPTIME
+#define SNMP_GET_SYSUPTIME(sysuptime)
+#endif
+
+static void system_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void system_get_value(struct obj_def *od, u16_t len, void *value);
+static u8_t system_set_test(struct obj_def *od, u16_t len, void *value);
+static void system_set_value(struct obj_def *od, u16_t len, void *value);
+static void interfaces_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void interfaces_get_value(struct obj_def *od, u16_t len, void *value);
+static void ifentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void ifentry_get_value(struct obj_def *od, u16_t len, void *value);
+#if !SNMP_SAFE_REQUESTS
+static u8_t ifentry_set_test (struct obj_def *od, u16_t len, void *value);
+static void ifentry_set_value (struct obj_def *od, u16_t len, void *value);
+#endif /* SNMP_SAFE_REQUESTS */
+static void atentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void atentry_get_value(struct obj_def *od, u16_t len, void *value);
+static void ip_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void ip_get_value(struct obj_def *od, u16_t len, void *value);
+static u8_t ip_set_test(struct obj_def *od, u16_t len, void *value);
+static void ip_addrentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void ip_addrentry_get_value(struct obj_def *od, u16_t len, void *value);
+static void ip_rteentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void ip_rteentry_get_value(struct obj_def *od, u16_t len, void *value);
+static void ip_ntomentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void ip_ntomentry_get_value(struct obj_def *od, u16_t len, void *value);
+static void icmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void icmp_get_value(struct obj_def *od, u16_t len, void *value);
+#if LWIP_TCP
+static void tcp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void tcp_get_value(struct obj_def *od, u16_t len, void *value);
+#ifdef THIS_SEEMS_UNUSED
+static void tcpconnentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void tcpconnentry_get_value(struct obj_def *od, u16_t len, void *value);
+#endif
+#endif
+static void udp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void udp_get_value(struct obj_def *od, u16_t len, void *value);
+static void udpentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void udpentry_get_value(struct obj_def *od, u16_t len, void *value);
+static void snmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void snmp_get_value(struct obj_def *od, u16_t len, void *value);
+static u8_t snmp_set_test(struct obj_def *od, u16_t len, void *value);
+static void snmp_set_value(struct obj_def *od, u16_t len, void *value);
+
+
+/* snmp .1.3.6.1.2.1.11 */
+const mib_scalar_node snmp_scalar = {
+  &snmp_get_object_def,
+  &snmp_get_value,
+  &snmp_set_test,
+  &snmp_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t snmp_ids[28] = {
+  1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+  17, 18, 19, 20, 21, 22, 24, 25, 26, 27, 28, 29, 30
+};
+struct mib_node* const snmp_nodes[28] = {
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar
+};
+const struct mib_array_node snmp = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  28,
+  snmp_ids,
+  snmp_nodes
+};
+
+/* dot3 and EtherLike MIB not planned. (transmission .1.3.6.1.2.1.10) */
+/* historical (some say hysterical). (cmot .1.3.6.1.2.1.9) */
+/* lwIP has no EGP, thus may not implement it. (egp .1.3.6.1.2.1.8) */
+
+/* udp .1.3.6.1.2.1.7 */
+/** index root node for udpTable */
+struct mib_list_rootnode udp_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t udpentry_ids[2] = { 1, 2 };
+struct mib_node* const udpentry_nodes[2] = {
+  (struct mib_node* const)&udp_root, (struct mib_node* const)&udp_root,
+};
+const struct mib_array_node udpentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  2,
+  udpentry_ids,
+  udpentry_nodes
+};
+
+s32_t udptable_id = 1;
+struct mib_node* udptable_node = (struct mib_node* const)&udpentry;
+struct mib_ram_array_node udptable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &udptable_id,
+  &udptable_node
+};
+
+const mib_scalar_node udp_scalar = {
+  &udp_get_object_def,
+  &udp_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t udp_ids[5] = { 1, 2, 3, 4, 5 };
+struct mib_node* const udp_nodes[5] = {
+  (struct mib_node* const)&udp_scalar, (struct mib_node* const)&udp_scalar,
+  (struct mib_node* const)&udp_scalar, (struct mib_node* const)&udp_scalar,
+  (struct mib_node* const)&udptable
+};
+const struct mib_array_node udp = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  5,
+  udp_ids,
+  udp_nodes
+};
+
+/* tcp .1.3.6.1.2.1.6 */
+#if LWIP_TCP
+/* only if the TCP protocol is available may implement this group */
+/** index root node for tcpConnTable */
+struct mib_list_rootnode tcpconntree_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t tcpconnentry_ids[5] = { 1, 2, 3, 4, 5 };
+struct mib_node* const tcpconnentry_nodes[5] = {
+  (struct mib_node* const)&tcpconntree_root, (struct mib_node* const)&tcpconntree_root,
+  (struct mib_node* const)&tcpconntree_root, (struct mib_node* const)&tcpconntree_root,
+  (struct mib_node* const)&tcpconntree_root
+};
+const struct mib_array_node tcpconnentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  5,
+  tcpconnentry_ids,
+  tcpconnentry_nodes
+};
+
+s32_t tcpconntable_id = 1;
+struct mib_node* tcpconntable_node = (struct mib_node* const)&tcpconnentry;
+struct mib_ram_array_node tcpconntable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+/** @todo update maxlength when inserting / deleting from table
+   0 when table is empty, 1 when more than one entry */
+  0,
+  &tcpconntable_id,
+  &tcpconntable_node
+};
+
+const mib_scalar_node tcp_scalar = {
+  &tcp_get_object_def,
+  &tcp_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t tcp_ids[15] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
+struct mib_node* const tcp_nodes[15] = {
+  (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar,
+  (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar,
+  (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar,
+  (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar,
+  (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar,
+  (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar,
+  (struct mib_node* const)&tcpconntable, (struct mib_node* const)&tcp_scalar,
+  (struct mib_node* const)&tcp_scalar
+};
+const struct mib_array_node tcp = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  15,
+  tcp_ids,
+  tcp_nodes
+};
+#endif
+
+/* icmp .1.3.6.1.2.1.5 */
+const mib_scalar_node icmp_scalar = {
+  &icmp_get_object_def,
+  &icmp_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t icmp_ids[26] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 };
+struct mib_node* const icmp_nodes[26] = {
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar
+};
+const struct mib_array_node icmp = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  26,
+  icmp_ids,
+  icmp_nodes
+};
+
+/** index root node for ipNetToMediaTable */
+struct mib_list_rootnode ipntomtree_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t ipntomentry_ids[4] = { 1, 2, 3, 4 };
+struct mib_node* const ipntomentry_nodes[4] = {
+  (struct mib_node* const)&ipntomtree_root, (struct mib_node* const)&ipntomtree_root,
+  (struct mib_node* const)&ipntomtree_root, (struct mib_node* const)&ipntomtree_root
+};
+const struct mib_array_node ipntomentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  4,
+  ipntomentry_ids,
+  ipntomentry_nodes
+};
+
+s32_t ipntomtable_id = 1;
+struct mib_node* ipntomtable_node = (struct mib_node* const)&ipntomentry;
+struct mib_ram_array_node ipntomtable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &ipntomtable_id,
+  &ipntomtable_node
+};
+
+/** index root node for ipRouteTable */
+struct mib_list_rootnode iprtetree_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t iprteentry_ids[13] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 };
+struct mib_node* const iprteentry_nodes[13] = {
+  (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root,
+  (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root,
+  (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root,
+  (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root,
+  (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root,
+  (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root,
+  (struct mib_node* const)&iprtetree_root
+};
+const struct mib_array_node iprteentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  13,
+  iprteentry_ids,
+  iprteentry_nodes
+};
+
+s32_t iprtetable_id = 1;
+struct mib_node* iprtetable_node = (struct mib_node* const)&iprteentry;
+struct mib_ram_array_node iprtetable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &iprtetable_id,
+  &iprtetable_node
+};
+
+/** index root node for ipAddrTable */
+struct mib_list_rootnode ipaddrtree_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t ipaddrentry_ids[5] = { 1, 2, 3, 4, 5 };
+struct mib_node* const ipaddrentry_nodes[5] = {
+  (struct mib_node* const)&ipaddrtree_root,
+  (struct mib_node* const)&ipaddrtree_root,
+  (struct mib_node* const)&ipaddrtree_root,
+  (struct mib_node* const)&ipaddrtree_root,
+  (struct mib_node* const)&ipaddrtree_root
+};
+const struct mib_array_node ipaddrentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  5,
+  ipaddrentry_ids,
+  ipaddrentry_nodes
+};
+
+s32_t ipaddrtable_id = 1;
+struct mib_node* ipaddrtable_node = (struct mib_node* const)&ipaddrentry;
+struct mib_ram_array_node ipaddrtable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &ipaddrtable_id,
+  &ipaddrtable_node
+};
+
+/* ip .1.3.6.1.2.1.4 */
+const mib_scalar_node ip_scalar = {
+  &ip_get_object_def,
+  &ip_get_value,
+  &ip_set_test,
+  &noleafs_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t ip_ids[23] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 };
+struct mib_node* const ip_nodes[23] = {
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ipaddrtable,
+  (struct mib_node* const)&iprtetable, (struct mib_node* const)&ipntomtable,
+  (struct mib_node* const)&ip_scalar
+};
+const struct mib_array_node mib2_ip = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  23,
+  ip_ids,
+  ip_nodes
+};
+
+/** index root node for atTable */
+struct mib_list_rootnode arptree_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t atentry_ids[3] = { 1, 2, 3 };
+struct mib_node* const atentry_nodes[3] = {
+  (struct mib_node* const)&arptree_root,
+  (struct mib_node* const)&arptree_root,
+  (struct mib_node* const)&arptree_root
+};
+const struct mib_array_node atentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  3,
+  atentry_ids,
+  atentry_nodes
+};
+
+const s32_t attable_id = 1;
+struct mib_node* const attable_node = (struct mib_node* const)&atentry;
+const struct mib_array_node attable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  1,
+  &attable_id,
+  &attable_node
+};
+
+/* at .1.3.6.1.2.1.3 */
+s32_t at_id = 1;
+struct mib_node* mib2_at_node = (struct mib_node* const)&attable;
+struct mib_ram_array_node at = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &at_id,
+  &mib2_at_node
+};
+
+/** index root node for ifTable */
+struct mib_list_rootnode iflist_root = {
+  &ifentry_get_object_def,
+  &ifentry_get_value,
+#if SNMP_SAFE_REQUESTS
+  &noleafs_set_test,
+  &noleafs_set_value,
+#else /* SNMP_SAFE_REQUESTS */
+  &ifentry_set_test,
+  &ifentry_set_value,
+#endif /* SNMP_SAFE_REQUESTS */
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t ifentry_ids[22] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 };
+struct mib_node* const ifentry_nodes[22] = {
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root
+};
+const struct mib_array_node ifentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  22,
+  ifentry_ids,
+  ifentry_nodes
+};
+
+s32_t iftable_id = 1;
+struct mib_node* iftable_node = (struct mib_node* const)&ifentry;
+struct mib_ram_array_node iftable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &iftable_id,
+  &iftable_node
+};
+
+/* interfaces .1.3.6.1.2.1.2 */
+const mib_scalar_node interfaces_scalar = {
+  &interfaces_get_object_def,
+  &interfaces_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t interfaces_ids[2] = { 1, 2 };
+struct mib_node* const interfaces_nodes[2] = {
+  (struct mib_node* const)&interfaces_scalar, (struct mib_node* const)&iftable
+};
+const struct mib_array_node interfaces = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  2,
+  interfaces_ids,
+  interfaces_nodes
+};
+
+
+/*             0 1 2 3 4 5 6 */
+/* system .1.3.6.1.2.1.1 */
+const mib_scalar_node sys_tem_scalar = {
+  &system_get_object_def,
+  &system_get_value,
+  &system_set_test,
+  &system_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t sys_tem_ids[7] = { 1, 2, 3, 4, 5, 6, 7 };
+struct mib_node* const sys_tem_nodes[7] = {
+  (struct mib_node* const)&sys_tem_scalar, (struct mib_node* const)&sys_tem_scalar,
+  (struct mib_node* const)&sys_tem_scalar, (struct mib_node* const)&sys_tem_scalar,
+  (struct mib_node* const)&sys_tem_scalar, (struct mib_node* const)&sys_tem_scalar,
+  (struct mib_node* const)&sys_tem_scalar
+};
+/* work around name issue with 'sys_tem', some compiler(s?) seem to reserve 'system' */
+const struct mib_array_node sys_tem = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  7,
+  sys_tem_ids,
+  sys_tem_nodes
+};
+
+/* mib-2 .1.3.6.1.2.1 */
+#if LWIP_TCP
+#define MIB2_GROUPS 8
+#else
+#define MIB2_GROUPS 7
+#endif
+const s32_t mib2_ids[MIB2_GROUPS] =
+{
+  1,
+  2,
+  3,
+  4,
+  5,
+#if LWIP_TCP
+  6,
+#endif
+  7,
+  11
+};
+struct mib_node* const mib2_nodes[MIB2_GROUPS] = {
+  (struct mib_node* const)&sys_tem,
+  (struct mib_node* const)&interfaces,
+  (struct mib_node* const)&at,
+  (struct mib_node* const)&mib2_ip,
+  (struct mib_node* const)&icmp,
+#if LWIP_TCP
+  (struct mib_node* const)&tcp,
+#endif
+  (struct mib_node* const)&udp,
+  (struct mib_node* const)&snmp
+};
+
+const struct mib_array_node mib2 = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  MIB2_GROUPS,
+  mib2_ids,
+  mib2_nodes
+};
+
+/* mgmt .1.3.6.1.2 */
+const s32_t mgmt_ids[1] = { 1 };
+struct mib_node* const mgmt_nodes[1] = { (struct mib_node* const)&mib2 };
+const struct mib_array_node mgmt = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  1,
+  mgmt_ids,
+  mgmt_nodes
+};
+
+/* internet .1.3.6.1 */
+#if SNMP_PRIVATE_MIB
+s32_t internet_ids[2] = { 2, 4 };
+struct mib_node* const internet_nodes[2] = { (struct mib_node* const)&mgmt, (struct mib_node* const)&private };
+const struct mib_array_node internet = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  2,
+  internet_ids,
+  internet_nodes
+};
+#else
+const s32_t internet_ids[1] = { 2 };
+struct mib_node* const internet_nodes[1] = { (struct mib_node* const)&mgmt };
+const struct mib_array_node internet = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  1,
+  internet_ids,
+  internet_nodes
+};
+#endif
+
+/** mib-2.system.sysObjectID  */
+static struct snmp_obj_id sysobjid = {SNMP_SYSOBJID_LEN, SNMP_SYSOBJID};
+/** enterprise ID for generic TRAPs, .iso.org.dod.internet.mgmt.mib-2.snmp */
+static struct snmp_obj_id snmpgrp_id = {7,{1,3,6,1,2,1,11}};
+/** mib-2.system.sysServices */
+static const s32_t sysservices = SNMP_SYSSERVICES;
+
+/** mib-2.system.sysDescr */
+static const u8_t sysdescr_len_default = 4;
+static const u8_t sysdescr_default[] = "lwIP";
+static u8_t* sysdescr_len_ptr = (u8_t*)&sysdescr_len_default;
+static u8_t* sysdescr_ptr = (u8_t*)&sysdescr_default[0];
+/** mib-2.system.sysContact */
+static const u8_t syscontact_len_default = 0;
+static const u8_t syscontact_default[] = "";
+static u8_t* syscontact_len_ptr = (u8_t*)&syscontact_len_default;
+static u8_t* syscontact_ptr = (u8_t*)&syscontact_default[0];
+/** mib-2.system.sysName */
+static const u8_t sysname_len_default = 8;
+static const u8_t sysname_default[] = "FQDN-unk";
+static u8_t* sysname_len_ptr = (u8_t*)&sysname_len_default;
+static u8_t* sysname_ptr = (u8_t*)&sysname_default[0];
+/** mib-2.system.sysLocation */
+static const u8_t syslocation_len_default = 0;
+static const u8_t syslocation_default[] = "";
+static u8_t* syslocation_len_ptr = (u8_t*)&syslocation_len_default;
+static u8_t* syslocation_ptr = (u8_t*)&syslocation_default[0];
+/** mib-2.snmp.snmpEnableAuthenTraps */
+static const u8_t snmpenableauthentraps_default = 2; /* disabled */
+static u8_t* snmpenableauthentraps_ptr = (u8_t*)&snmpenableauthentraps_default;
+
+/** mib-2.interfaces.ifTable.ifEntry.ifSpecific (zeroDotZero) */
+static const struct snmp_obj_id ifspecific = {2, {0, 0}};
+/** mib-2.ip.ipRouteTable.ipRouteEntry.ipRouteInfo (zeroDotZero) */
+static const struct snmp_obj_id iprouteinfo = {2, {0, 0}};
+
+
+
+/* mib-2.system counter(s) */
+static u32_t sysuptime = 0;
+
+/* mib-2.ip counter(s) */
+static u32_t ipinreceives = 0,
+             ipinhdrerrors = 0,
+             ipinaddrerrors = 0,
+             ipforwdatagrams = 0,
+             ipinunknownprotos = 0,
+             ipindiscards = 0,
+             ipindelivers = 0,
+             ipoutrequests = 0,
+             ipoutdiscards = 0,
+             ipoutnoroutes = 0,
+             ipreasmreqds = 0,
+             ipreasmoks = 0,
+             ipreasmfails = 0,
+             ipfragoks = 0,
+             ipfragfails = 0,
+             ipfragcreates = 0,
+             iproutingdiscards = 0;
+/* mib-2.icmp counter(s) */
+static u32_t icmpinmsgs = 0,
+             icmpinerrors = 0,
+             icmpindestunreachs = 0,
+             icmpintimeexcds = 0,
+             icmpinparmprobs = 0,
+             icmpinsrcquenchs = 0,
+             icmpinredirects = 0,
+             icmpinechos = 0,
+             icmpinechoreps = 0,
+             icmpintimestamps = 0,
+             icmpintimestampreps = 0,
+             icmpinaddrmasks = 0,
+             icmpinaddrmaskreps = 0,
+             icmpoutmsgs = 0,
+             icmpouterrors = 0,
+             icmpoutdestunreachs = 0,
+             icmpouttimeexcds = 0,
+             icmpoutparmprobs = 0,
+             icmpoutsrcquenchs = 0,
+             icmpoutredirects = 0,
+             icmpoutechos = 0,
+             icmpoutechoreps = 0,
+             icmpouttimestamps = 0,
+             icmpouttimestampreps = 0,
+             icmpoutaddrmasks = 0,
+             icmpoutaddrmaskreps = 0;
+/* mib-2.tcp counter(s) */
+static u32_t tcpactiveopens = 0,
+             tcppassiveopens = 0,
+             tcpattemptfails = 0,
+             tcpestabresets = 0,
+             tcpinsegs = 0,
+             tcpoutsegs = 0,
+             tcpretranssegs = 0,
+             tcpinerrs = 0,
+             tcpoutrsts = 0;
+/* mib-2.udp counter(s) */
+static u32_t udpindatagrams = 0,
+             udpnoports = 0,
+             udpinerrors = 0,
+             udpoutdatagrams = 0;
+/* mib-2.snmp counter(s) */
+static u32_t snmpinpkts = 0,
+             snmpoutpkts = 0,
+             snmpinbadversions = 0,
+             snmpinbadcommunitynames = 0,
+             snmpinbadcommunityuses = 0,
+             snmpinasnparseerrs = 0,
+             snmpintoobigs = 0,
+             snmpinnosuchnames = 0,
+             snmpinbadvalues = 0,
+             snmpinreadonlys = 0,
+             snmpingenerrs = 0,
+             snmpintotalreqvars = 0,
+             snmpintotalsetvars = 0,
+             snmpingetrequests = 0,
+             snmpingetnexts = 0,
+             snmpinsetrequests = 0,
+             snmpingetresponses = 0,
+             snmpintraps = 0,
+             snmpouttoobigs = 0,
+             snmpoutnosuchnames = 0,
+             snmpoutbadvalues = 0,
+             snmpoutgenerrs = 0,
+             snmpoutgetrequests = 0,
+             snmpoutgetnexts = 0,
+             snmpoutsetrequests = 0,
+             snmpoutgetresponses = 0,
+             snmpouttraps = 0;
+
+
+
+/* prototypes of the following functions are in lwip/src/include/lwip/snmp.h */
+/**
+ * Copy octet string.
+ *
+ * @param dst points to destination
+ * @param src points to source
+ * @param n number of octets to copy.
+ */
+void ocstrncpy(u8_t *dst, u8_t *src, u8_t n)
+{
+  while (n > 0)
+  {
+    n--;
+    *dst++ = *src++;
+  }
+}
+
+/**
+ * Copy object identifier (s32_t) array.
+ *
+ * @param dst points to destination
+ * @param src points to source
+ * @param n number of sub identifiers to copy.
+ */
+void objectidncpy(s32_t *dst, s32_t *src, u8_t n)
+{
+  while(n > 0)
+  {
+    n--;
+    *dst++ = *src++;
+  }
+}
+
+/**
+ * Initializes sysDescr pointers.
+ *
+ * @param str if non-NULL then copy str pointer
+ * @param len points to string length, excluding zero terminator
+ */
+void snmp_set_sysdesr(u8_t *str, u8_t *len)
+{
+  if (str != NULL)
+  {
+    sysdescr_ptr = str;
+    sysdescr_len_ptr = len;
+  }
+}
+
+void snmp_get_sysobjid_ptr(struct snmp_obj_id **oid)
+{
+  *oid = &sysobjid;
+}
+
+/**
+ * Initializes sysObjectID value.
+ *
+ * @param oid points to stuct snmp_obj_id to copy
+ */
+void snmp_set_sysobjid(struct snmp_obj_id *oid)
+{
+  sysobjid = *oid;
+}
+
+/**
+ * Must be called at regular 10 msec interval from a timer interrupt
+ * or signal handler depending on your runtime environment.
+ */
+void snmp_inc_sysuptime(void)
+{
+  sysuptime++;
+}
+
+void snmp_add_sysuptime(u32_t value)
+{
+  sysuptime+=value;
+}
+
+void snmp_get_sysuptime(u32_t *value)
+{
+  SNMP_GET_SYSUPTIME(sysuptime);
+  *value = sysuptime;
+}
+
+/**
+ * Initializes sysContact pointers,
+ * e.g. ptrs to non-volatile memory external to lwIP.
+ *
+ * @param ocstr if non-NULL then copy str pointer
+ * @param ocstrlen points to string length, excluding zero terminator
+ */
+void snmp_set_syscontact(u8_t *ocstr, u8_t *ocstrlen)
+{
+  if (ocstr != NULL)
+  {
+    syscontact_ptr = ocstr;
+    syscontact_len_ptr = ocstrlen;
+  }
+}
+
+/**
+ * Initializes sysName pointers,
+ * e.g. ptrs to non-volatile memory external to lwIP.
+ *
+ * @param ocstr if non-NULL then copy str pointer
+ * @param ocstrlen points to string length, excluding zero terminator
+ */
+void snmp_set_sysname(u8_t *ocstr, u8_t *ocstrlen)
+{
+  if (ocstr != NULL)
+  {
+    sysname_ptr = ocstr;
+    sysname_len_ptr = ocstrlen;
+  }
+}
+
+/**
+ * Initializes sysLocation pointers,
+ * e.g. ptrs to non-volatile memory external to lwIP.
+ *
+ * @param ocstr if non-NULL then copy str pointer
+ * @param ocstrlen points to string length, excluding zero terminator
+ */
+void snmp_set_syslocation(u8_t *ocstr, u8_t *ocstrlen)
+{
+  if (ocstr != NULL)
+  {
+    syslocation_ptr = ocstr;
+    syslocation_len_ptr = ocstrlen;
+  }
+}
+
+
+void snmp_add_ifinoctets(struct netif *ni, u32_t value)
+{
+  ni->ifinoctets += value;
+}
+
+void snmp_inc_ifinucastpkts(struct netif *ni)
+{
+  (ni->ifinucastpkts)++;
+}
+
+void snmp_inc_ifinnucastpkts(struct netif *ni)
+{
+  (ni->ifinnucastpkts)++;
+}
+
+void snmp_inc_ifindiscards(struct netif *ni)
+{
+  (ni->ifindiscards)++;
+}
+
+void snmp_add_ifoutoctets(struct netif *ni, u32_t value)
+{
+  ni->ifoutoctets += value;
+}
+
+void snmp_inc_ifoutucastpkts(struct netif *ni)
+{
+  (ni->ifoutucastpkts)++;
+}
+
+void snmp_inc_ifoutnucastpkts(struct netif *ni)
+{
+  (ni->ifoutnucastpkts)++;
+}
+
+void snmp_inc_ifoutdiscards(struct netif *ni)
+{
+  (ni->ifoutdiscards)++;
+}
+
+void snmp_inc_iflist(void)
+{
+  struct mib_list_node *if_node = NULL;
+
+  snmp_mib_node_insert(&iflist_root, iflist_root.count + 1, &if_node);
+  /* enable getnext traversal on filled table */
+  iftable.maxlength = 1;
+}
+
+void snmp_dec_iflist(void)
+{
+  snmp_mib_node_delete(&iflist_root, iflist_root.tail);
+  /* disable getnext traversal on empty table */
+  if(iflist_root.count == 0) iftable.maxlength = 0;
+}
+
+/**
+ * Inserts ARP table indexes (.xIfIndex.xNetAddress)
+ * into arp table index trees (both atTable and ipNetToMediaTable).
+ */
+void snmp_insert_arpidx_tree(struct netif *ni, struct ip_addr *ip)
+{
+  struct mib_list_rootnode *at_rn;
+  struct mib_list_node *at_node;
+  struct ip_addr hip;
+  s32_t arpidx[5];
+  u8_t level, tree;
+
+  LWIP_ASSERT("ni != NULL", ni != NULL);
+  snmp_netiftoifindex(ni, &arpidx[0]);
+  hip.addr = ntohl(ip->addr);
+  snmp_iptooid(&hip, &arpidx[1]);
+
+  for (tree = 0; tree < 2; tree++)
+  {
+    if (tree == 0)
+    {
+      at_rn = &arptree_root;
+    }
+    else
+    {
+      at_rn = &ipntomtree_root;
+    }
+    for (level = 0; level < 5; level++)
+    {
+      at_node = NULL;
+      snmp_mib_node_insert(at_rn, arpidx[level], &at_node);
+      if ((level != 4) && (at_node != NULL))
+      {
+        if (at_node->nptr == NULL)
+        {
+          at_rn = snmp_mib_lrn_alloc();
+          at_node->nptr = (struct mib_node*)at_rn;
+          if (at_rn != NULL)
+          {
+            if (level == 3)
+            {
+              if (tree == 0)
+              {
+                at_rn->get_object_def = atentry_get_object_def;
+                at_rn->get_value = atentry_get_value;
+              }
+              else
+              {
+                at_rn->get_object_def = ip_ntomentry_get_object_def;
+                at_rn->get_value = ip_ntomentry_get_value;
+              }
+              at_rn->set_test = noleafs_set_test;
+              at_rn->set_value = noleafs_set_value;
+            }
+          }
+          else
+          {
+            /* at_rn == NULL, malloc failure */
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_arpidx_tree() insert failed, mem full"));
+            break;
+          }
+        }
+        else
+        {
+          at_rn = (struct mib_list_rootnode*)at_node->nptr;
+        }
+      }
+    }
+  }
+  /* enable getnext traversal on filled tables */
+  at.maxlength = 1;
+  ipntomtable.maxlength = 1;
+}
+
+/**
+ * Removes ARP table indexes (.xIfIndex.xNetAddress)
+ * from arp table index trees.
+ */
+void snmp_delete_arpidx_tree(struct netif *ni, struct ip_addr *ip)
+{
+  struct mib_list_rootnode *at_rn, *next, *del_rn[5];
+  struct mib_list_node *at_n, *del_n[5];
+  struct ip_addr hip;
+  s32_t arpidx[5];
+  u8_t fc, tree, level, del_cnt;
+
+  snmp_netiftoifindex(ni, &arpidx[0]);
+  hip.addr = ntohl(ip->addr);
+  snmp_iptooid(&hip, &arpidx[1]);
+
+  for (tree = 0; tree < 2; tree++)
+  {
+    /* mark nodes for deletion */
+    if (tree == 0)
+    {
+      at_rn = &arptree_root;
+    }
+    else
+    {
+      at_rn = &ipntomtree_root;
+    }
+    level = 0;
+    del_cnt = 0;
+    while ((level < 5) && (at_rn != NULL))
+    {
+      fc = snmp_mib_node_find(at_rn, arpidx[level], &at_n);
+      if (fc == 0)
+      {
+        /* arpidx[level] does not exist */
+        del_cnt = 0;
+        at_rn = NULL;
+      }
+      else if (fc == 1)
+      {
+        del_rn[del_cnt] = at_rn;
+        del_n[del_cnt] = at_n;
+        del_cnt++;
+        at_rn = (struct mib_list_rootnode*)(at_n->nptr);
+      }
+      else if (fc == 2)
+      {
+        /* reset delete (2 or more childs) */
+        del_cnt = 0;
+        at_rn = (struct mib_list_rootnode*)(at_n->nptr);
+      }
+      level++;
+    }
+    /* delete marked index nodes */
+    while (del_cnt > 0)
+    {
+      del_cnt--;
+
+      at_rn = del_rn[del_cnt];
+      at_n = del_n[del_cnt];
+
+      next = snmp_mib_node_delete(at_rn, at_n);
+      if (next != NULL)
+      {
+        LWIP_ASSERT("next_count == 0",next->count == 0);
+        snmp_mib_lrn_free(next);
+      }
+    }
+  }
+  /* disable getnext traversal on empty tables */
+  if(arptree_root.count == 0) at.maxlength = 0;
+  if(ipntomtree_root.count == 0) ipntomtable.maxlength = 0;
+}
+
+void snmp_inc_ipinreceives(void)
+{
+  ipinreceives++;
+}
+
+void snmp_inc_ipinhdrerrors(void)
+{
+  ipinhdrerrors++;
+}
+
+void snmp_inc_ipinaddrerrors(void)
+{
+  ipinaddrerrors++;
+}
+
+void snmp_inc_ipforwdatagrams(void)
+{
+  ipforwdatagrams++;
+}
+
+void snmp_inc_ipinunknownprotos(void)
+{
+  ipinunknownprotos++;
+}
+
+void snmp_inc_ipindiscards(void)
+{
+  ipindiscards++;
+}
+
+void snmp_inc_ipindelivers(void)
+{
+  ipindelivers++;
+}
+
+void snmp_inc_ipoutrequests(void)
+{
+  ipoutrequests++;
+}
+
+void snmp_inc_ipoutdiscards(void)
+{
+  ipoutdiscards++;
+}
+
+void snmp_inc_ipoutnoroutes(void)
+{
+  ipoutnoroutes++;
+}
+
+void snmp_inc_ipreasmreqds(void)
+{
+  ipreasmreqds++;
+}
+
+void snmp_inc_ipreasmoks(void)
+{
+  ipreasmoks++;
+}
+
+void snmp_inc_ipreasmfails(void)
+{
+  ipreasmfails++;
+}
+
+void snmp_inc_ipfragoks(void)
+{
+  ipfragoks++;
+}
+
+void snmp_inc_ipfragfails(void)
+{
+  ipfragfails++;
+}
+
+void snmp_inc_ipfragcreates(void)
+{
+  ipfragcreates++;
+}
+
+void snmp_inc_iproutingdiscards(void)
+{
+  iproutingdiscards++;
+}
+
+/**
+ * Inserts ipAddrTable indexes (.ipAdEntAddr)
+ * into index tree.
+ */
+void snmp_insert_ipaddridx_tree(struct netif *ni)
+{
+  struct mib_list_rootnode *ipa_rn;
+  struct mib_list_node *ipa_node;
+  struct ip_addr ip;
+  s32_t ipaddridx[4];
+  u8_t level;
+
+  LWIP_ASSERT("ni != NULL", ni != NULL);
+  ip.addr = ntohl(ni->ip_addr.addr);
+  snmp_iptooid(&ip, &ipaddridx[0]);
+
+  level = 0;
+  ipa_rn = &ipaddrtree_root;
+  while (level < 4)
+  {
+    ipa_node = NULL;
+    snmp_mib_node_insert(ipa_rn, ipaddridx[level], &ipa_node);
+    if ((level != 3) && (ipa_node != NULL))
+    {
+      if (ipa_node->nptr == NULL)
+      {
+        ipa_rn = snmp_mib_lrn_alloc();
+        ipa_node->nptr = (struct mib_node*)ipa_rn;
+        if (ipa_rn != NULL)
+        {
+          if (level == 2)
+          {
+            ipa_rn->get_object_def = ip_addrentry_get_object_def;
+            ipa_rn->get_value = ip_addrentry_get_value;
+            ipa_rn->set_test = noleafs_set_test;
+            ipa_rn->set_value = noleafs_set_value;
+          }
+        }
+        else
+        {
+          /* ipa_rn == NULL, malloc failure */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_ipaddridx_tree() insert failed, mem full"));
+          break;
+        }
+      }
+      else
+      {
+        ipa_rn = (struct mib_list_rootnode*)ipa_node->nptr;
+      }
+    }
+    level++;
+  }
+  /* enable getnext traversal on filled table */
+  ipaddrtable.maxlength = 1;
+}
+
+/**
+ * Removes ipAddrTable indexes (.ipAdEntAddr)
+ * from index tree.
+ */
+void snmp_delete_ipaddridx_tree(struct netif *ni)
+{
+  struct mib_list_rootnode *ipa_rn, *next, *del_rn[4];
+  struct mib_list_node *ipa_n, *del_n[4];
+  struct ip_addr ip;
+  s32_t ipaddridx[4];
+  u8_t fc, level, del_cnt;
+
+  LWIP_ASSERT("ni != NULL", ni != NULL);
+  ip.addr = ntohl(ni->ip_addr.addr);
+  snmp_iptooid(&ip, &ipaddridx[0]);
+
+  /* mark nodes for deletion */
+  level = 0;
+  del_cnt = 0;
+  ipa_rn = &ipaddrtree_root;
+  while ((level < 4) && (ipa_rn != NULL))
+  {
+    fc = snmp_mib_node_find(ipa_rn, ipaddridx[level], &ipa_n);
+    if (fc == 0)
+    {
+      /* ipaddridx[level] does not exist */
+      del_cnt = 0;
+      ipa_rn = NULL;
+    }
+    else if (fc == 1)
+    {
+      del_rn[del_cnt] = ipa_rn;
+      del_n[del_cnt] = ipa_n;
+      del_cnt++;
+      ipa_rn = (struct mib_list_rootnode*)(ipa_n->nptr);
+    }
+    else if (fc == 2)
+    {
+      /* reset delete (2 or more childs) */
+      del_cnt = 0;
+      ipa_rn = (struct mib_list_rootnode*)(ipa_n->nptr);
+    }
+    level++;
+  }
+  /* delete marked index nodes */
+  while (del_cnt > 0)
+  {
+    del_cnt--;
+
+    ipa_rn = del_rn[del_cnt];
+    ipa_n = del_n[del_cnt];
+
+    next = snmp_mib_node_delete(ipa_rn, ipa_n);
+    if (next != NULL)
+    {
+      LWIP_ASSERT("next_count == 0",next->count == 0);
+      snmp_mib_lrn_free(next);
+    }
+  }
+  /* disable getnext traversal on empty table */
+  if (ipaddrtree_root.count == 0) ipaddrtable.maxlength = 0;
+}
+
+/**
+ * Inserts ipRouteTable indexes (.ipRouteDest)
+ * into index tree.
+ *
+ * @param dflt non-zero for the default rte, zero for network rte
+ * @param ni points to network interface for this rte
+ *
+ * @todo record sysuptime for _this_ route when it is installed
+ *   (needed for ipRouteAge) in the netif.
+ */
+void snmp_insert_iprteidx_tree(u8_t dflt, struct netif *ni)
+{
+  u8_t insert = 0;
+  struct ip_addr dst;
+
+  if (dflt != 0)
+  {
+    /* the default route 0.0.0.0 */
+    dst.addr = 0;
+    insert = 1;
+  }
+  else
+  {
+    /* route to the network address */
+    dst.addr = ntohl(ni->ip_addr.addr & ni->netmask.addr);
+    /* exclude 0.0.0.0 network (reserved for default rte) */
+    if (dst.addr != 0) insert = 1;
+  }
+  if (insert)
+  {
+    struct mib_list_rootnode *iprte_rn;
+    struct mib_list_node *iprte_node;
+    s32_t iprteidx[4];
+    u8_t level;
+
+    snmp_iptooid(&dst, &iprteidx[0]);
+    level = 0;
+    iprte_rn = &iprtetree_root;
+    while (level < 4)
+    {
+      iprte_node = NULL;
+      snmp_mib_node_insert(iprte_rn, iprteidx[level], &iprte_node);
+      if ((level != 3) && (iprte_node != NULL))
+      {
+        if (iprte_node->nptr == NULL)
+        {
+          iprte_rn = snmp_mib_lrn_alloc();
+          iprte_node->nptr = (struct mib_node*)iprte_rn;
+          if (iprte_rn != NULL)
+          {
+            if (level == 2)
+            {
+              iprte_rn->get_object_def = ip_rteentry_get_object_def;
+              iprte_rn->get_value = ip_rteentry_get_value;
+              iprte_rn->set_test = noleafs_set_test;
+              iprte_rn->set_value = noleafs_set_value;
+            }
+          }
+          else
+          {
+            /* iprte_rn == NULL, malloc failure */
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_iprteidx_tree() insert failed, mem full"));
+            break;
+          }
+        }
+        else
+        {
+          iprte_rn = (struct mib_list_rootnode*)iprte_node->nptr;
+        }
+      }
+      level++;
+    }
+  }
+  /* enable getnext traversal on filled table */
+  iprtetable.maxlength = 1;
+}
+
+/**
+ * Removes ipRouteTable indexes (.ipRouteDest)
+ * from index tree.
+ *
+ * @param dflt non-zero for the default rte, zero for network rte
+ * @param ni points to network interface for this rte or NULL
+ *   for default route to be removed.
+ */
+void snmp_delete_iprteidx_tree(u8_t dflt, struct netif *ni)
+{
+  u8_t delete = 0;
+  struct ip_addr dst;
+
+  if (dflt != 0)
+  {
+    /* the default route 0.0.0.0 */
+    dst.addr = 0;
+    delete = 1;
+  }
+  else
+  {
+    /* route to the network address */
+    dst.addr = ntohl(ni->ip_addr.addr & ni->netmask.addr);
+    /* exclude 0.0.0.0 network (reserved for default rte) */
+    if (dst.addr != 0) delete = 1;
+  }
+  if (delete)
+  {
+    struct mib_list_rootnode *iprte_rn, *next, *del_rn[4];
+    struct mib_list_node *iprte_n, *del_n[4];
+    s32_t iprteidx[4];
+    u8_t fc, level, del_cnt;
+
+    snmp_iptooid(&dst, &iprteidx[0]);
+    /* mark nodes for deletion */
+    level = 0;
+    del_cnt = 0;
+    iprte_rn = &iprtetree_root;
+    while ((level < 4) && (iprte_rn != NULL))
+    {
+      fc = snmp_mib_node_find(iprte_rn, iprteidx[level], &iprte_n);
+      if (fc == 0)
+      {
+        /* iprteidx[level] does not exist */
+        del_cnt = 0;
+        iprte_rn = NULL;
+      }
+      else if (fc == 1)
+      {
+        del_rn[del_cnt] = iprte_rn;
+        del_n[del_cnt] = iprte_n;
+        del_cnt++;
+        iprte_rn = (struct mib_list_rootnode*)(iprte_n->nptr);
+      }
+      else if (fc == 2)
+      {
+        /* reset delete (2 or more childs) */
+        del_cnt = 0;
+        iprte_rn = (struct mib_list_rootnode*)(iprte_n->nptr);
+      }
+      level++;
+    }
+    /* delete marked index nodes */
+    while (del_cnt > 0)
+    {
+      del_cnt--;
+
+      iprte_rn = del_rn[del_cnt];
+      iprte_n = del_n[del_cnt];
+
+      next = snmp_mib_node_delete(iprte_rn, iprte_n);
+      if (next != NULL)
+      {
+        LWIP_ASSERT("next_count == 0",next->count == 0);
+        snmp_mib_lrn_free(next);
+      }
+    }
+  }
+  /* disable getnext traversal on empty table */
+  if (iprtetree_root.count == 0) iprtetable.maxlength = 0;
+}
+
+
+void snmp_inc_icmpinmsgs(void)
+{
+  icmpinmsgs++;
+}
+
+void snmp_inc_icmpinerrors(void)
+{
+  icmpinerrors++;
+}
+
+void snmp_inc_icmpindestunreachs(void)
+{
+  icmpindestunreachs++;
+}
+
+void snmp_inc_icmpintimeexcds(void)
+{
+  icmpintimeexcds++;
+}
+
+void snmp_inc_icmpinparmprobs(void)
+{
+  icmpinparmprobs++;
+}
+
+void snmp_inc_icmpinsrcquenchs(void)
+{
+  icmpinsrcquenchs++;
+}
+
+void snmp_inc_icmpinredirects(void)
+{
+  icmpinredirects++;
+}
+
+void snmp_inc_icmpinechos(void)
+{
+  icmpinechos++;
+}
+
+void snmp_inc_icmpinechoreps(void)
+{
+  icmpinechoreps++;
+}
+
+void snmp_inc_icmpintimestamps(void)
+{
+  icmpintimestamps++;
+}
+
+void snmp_inc_icmpintimestampreps(void)
+{
+  icmpintimestampreps++;
+}
+
+void snmp_inc_icmpinaddrmasks(void)
+{
+  icmpinaddrmasks++;
+}
+
+void snmp_inc_icmpinaddrmaskreps(void)
+{
+  icmpinaddrmaskreps++;
+}
+
+void snmp_inc_icmpoutmsgs(void)
+{
+  icmpoutmsgs++;
+}
+
+void snmp_inc_icmpouterrors(void)
+{
+  icmpouterrors++;
+}
+
+void snmp_inc_icmpoutdestunreachs(void)
+{
+  icmpoutdestunreachs++;
+}
+
+void snmp_inc_icmpouttimeexcds(void)
+{
+  icmpouttimeexcds++;
+}
+
+void snmp_inc_icmpoutparmprobs(void)
+{
+  icmpoutparmprobs++;
+}
+
+void snmp_inc_icmpoutsrcquenchs(void)
+{
+  icmpoutsrcquenchs++;
+}
+
+void snmp_inc_icmpoutredirects(void)
+{
+  icmpoutredirects++;
+}
+
+void snmp_inc_icmpoutechos(void)
+{
+  icmpoutechos++;
+}
+
+void snmp_inc_icmpoutechoreps(void)
+{
+  icmpoutechoreps++;
+}
+
+void snmp_inc_icmpouttimestamps(void)
+{
+  icmpouttimestamps++;
+}
+
+void snmp_inc_icmpouttimestampreps(void)
+{
+  icmpouttimestampreps++;
+}
+
+void snmp_inc_icmpoutaddrmasks(void)
+{
+  icmpoutaddrmasks++;
+}
+
+void snmp_inc_icmpoutaddrmaskreps(void)
+{
+  icmpoutaddrmaskreps++;
+}
+
+void snmp_inc_tcpactiveopens(void)
+{
+  tcpactiveopens++;
+}
+
+void snmp_inc_tcppassiveopens(void)
+{
+  tcppassiveopens++;
+}
+
+void snmp_inc_tcpattemptfails(void)
+{
+  tcpattemptfails++;
+}
+
+void snmp_inc_tcpestabresets(void)
+{
+  tcpestabresets++;
+}
+
+void snmp_inc_tcpinsegs(void)
+{
+  tcpinsegs++;
+}
+
+void snmp_inc_tcpoutsegs(void)
+{
+  tcpoutsegs++;
+}
+
+void snmp_inc_tcpretranssegs(void)
+{
+  tcpretranssegs++;
+}
+
+void snmp_inc_tcpinerrs(void)
+{
+  tcpinerrs++;
+}
+
+void snmp_inc_tcpoutrsts(void)
+{
+  tcpoutrsts++;
+}
+
+void snmp_inc_udpindatagrams(void)
+{
+  udpindatagrams++;
+}
+
+void snmp_inc_udpnoports(void)
+{
+  udpnoports++;
+}
+
+void snmp_inc_udpinerrors(void)
+{
+  udpinerrors++;
+}
+
+void snmp_inc_udpoutdatagrams(void)
+{
+  udpoutdatagrams++;
+}
+
+/**
+ * Inserts udpTable indexes (.udpLocalAddress.udpLocalPort)
+ * into index tree.
+ */
+void snmp_insert_udpidx_tree(struct udp_pcb *pcb)
+{
+  struct mib_list_rootnode *udp_rn;
+  struct mib_list_node *udp_node;
+  struct ip_addr ip;
+  s32_t udpidx[5];
+  u8_t level;
+
+  LWIP_ASSERT("pcb != NULL", pcb != NULL);
+  ip.addr = ntohl(pcb->local_ip.addr);
+  snmp_iptooid(&ip, &udpidx[0]);
+  udpidx[4] = pcb->local_port;
+
+  udp_rn = &udp_root;
+  for (level = 0; level < 5; level++)
+  {
+    udp_node = NULL;
+    snmp_mib_node_insert(udp_rn, udpidx[level], &udp_node);
+    if ((level != 4) && (udp_node != NULL))
+    {
+      if (udp_node->nptr == NULL)
+      {
+        udp_rn = snmp_mib_lrn_alloc();
+        udp_node->nptr = (struct mib_node*)udp_rn;
+        if (udp_rn != NULL)
+        {
+          if (level == 3)
+          {
+            udp_rn->get_object_def = udpentry_get_object_def;
+            udp_rn->get_value = udpentry_get_value;
+            udp_rn->set_test = noleafs_set_test;
+            udp_rn->set_value = noleafs_set_value;
+          }
+        }
+        else
+        {
+          /* udp_rn == NULL, malloc failure */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_udpidx_tree() insert failed, mem full"));
+          break;
+        }
+      }
+      else
+      {
+        udp_rn = (struct mib_list_rootnode*)udp_node->nptr;
+      }
+    }
+  }
+  udptable.maxlength = 1;
+}
+
+/**
+ * Removes udpTable indexes (.udpLocalAddress.udpLocalPort)
+ * from index tree.
+ */
+void snmp_delete_udpidx_tree(struct udp_pcb *pcb)
+{
+  struct mib_list_rootnode *udp_rn, *next, *del_rn[5];
+  struct mib_list_node *udp_n, *del_n[5];
+  struct ip_addr ip;
+  s32_t udpidx[5];
+  u8_t bindings, fc, level, del_cnt;
+
+  LWIP_ASSERT("pcb != NULL", pcb != NULL);
+  ip.addr = ntohl(pcb->local_ip.addr);
+  snmp_iptooid(&ip, &udpidx[0]);
+  udpidx[4] = pcb->local_port;
+
+  /* count PCBs for a given binding
+     (e.g. when reusing ports or for temp output PCBs) */
+  bindings = 0;
+  pcb = udp_pcbs;
+  while ((pcb != NULL))
+  {
+    if ((pcb->local_ip.addr == ip.addr) &&
+        (pcb->local_port == udpidx[4]))
+    {
+      bindings++;
+    }
+    pcb = pcb->next;
+  }
+  if (bindings == 1)
+  {
+    /* selectively remove */
+    /* mark nodes for deletion */
+    level = 0;
+    del_cnt = 0;
+    udp_rn = &udp_root;
+    while ((level < 5) && (udp_rn != NULL))
+    {
+      fc = snmp_mib_node_find(udp_rn, udpidx[level], &udp_n);
+      if (fc == 0)
+      {
+        /* udpidx[level] does not exist */
+        del_cnt = 0;
+        udp_rn = NULL;
+      }
+      else if (fc == 1)
+      {
+        del_rn[del_cnt] = udp_rn;
+        del_n[del_cnt] = udp_n;
+        del_cnt++;
+        udp_rn = (struct mib_list_rootnode*)(udp_n->nptr);
+      }
+      else if (fc == 2)
+      {
+        /* reset delete (2 or more childs) */
+        del_cnt = 0;
+        udp_rn = (struct mib_list_rootnode*)(udp_n->nptr);
+      }
+      level++;
+    }
+    /* delete marked index nodes */
+    while (del_cnt > 0)
+    {
+      del_cnt--;
+
+      udp_rn = del_rn[del_cnt];
+      udp_n = del_n[del_cnt];
+
+      next = snmp_mib_node_delete(udp_rn, udp_n);
+      if (next != NULL)
+      {
+        LWIP_ASSERT("next_count == 0",next->count == 0);
+        snmp_mib_lrn_free(next);
+      }
+    }
+  }
+  /* disable getnext traversal on empty table */
+  if (udp_root.count == 0) udptable.maxlength = 0;
+}
+
+
+void snmp_inc_snmpinpkts(void)
+{
+  snmpinpkts++;
+}
+
+void snmp_inc_snmpoutpkts(void)
+{
+  snmpoutpkts++;
+}
+
+void snmp_inc_snmpinbadversions(void)
+{
+  snmpinbadversions++;
+}
+
+void snmp_inc_snmpinbadcommunitynames(void)
+{
+  snmpinbadcommunitynames++;
+}
+
+void snmp_inc_snmpinbadcommunityuses(void)
+{
+  snmpinbadcommunityuses++;
+}
+
+void snmp_inc_snmpinasnparseerrs(void)
+{
+  snmpinasnparseerrs++;
+}
+
+void snmp_inc_snmpintoobigs(void)
+{
+  snmpintoobigs++;
+}
+
+void snmp_inc_snmpinnosuchnames(void)
+{
+  snmpinnosuchnames++;
+}
+
+void snmp_inc_snmpinbadvalues(void)
+{
+  snmpinbadvalues++;
+}
+
+void snmp_inc_snmpinreadonlys(void)
+{
+  snmpinreadonlys++;
+}
+
+void snmp_inc_snmpingenerrs(void)
+{
+  snmpingenerrs++;
+}
+
+void snmp_add_snmpintotalreqvars(u8_t value)
+{
+  snmpintotalreqvars += value;
+}
+
+void snmp_add_snmpintotalsetvars(u8_t value)
+{
+  snmpintotalsetvars += value;
+}
+
+void snmp_inc_snmpingetrequests(void)
+{
+  snmpingetrequests++;
+}
+
+void snmp_inc_snmpingetnexts(void)
+{
+  snmpingetnexts++;
+}
+
+void snmp_inc_snmpinsetrequests(void)
+{
+  snmpinsetrequests++;
+}
+
+void snmp_inc_snmpingetresponses(void)
+{
+  snmpingetresponses++;
+}
+
+void snmp_inc_snmpintraps(void)
+{
+  snmpintraps++;
+}
+
+void snmp_inc_snmpouttoobigs(void)
+{
+  snmpouttoobigs++;
+}
+
+void snmp_inc_snmpoutnosuchnames(void)
+{
+  snmpoutnosuchnames++;
+}
+
+void snmp_inc_snmpoutbadvalues(void)
+{
+  snmpoutbadvalues++;
+}
+
+void snmp_inc_snmpoutgenerrs(void)
+{
+  snmpoutgenerrs++;
+}
+
+void snmp_inc_snmpoutgetrequests(void)
+{
+  snmpoutgetrequests++;
+}
+
+void snmp_inc_snmpoutgetnexts(void)
+{
+  snmpoutgetnexts++;
+}
+
+void snmp_inc_snmpoutsetrequests(void)
+{
+  snmpoutsetrequests++;
+}
+
+void snmp_inc_snmpoutgetresponses(void)
+{
+  snmpoutgetresponses++;
+}
+
+void snmp_inc_snmpouttraps(void)
+{
+  snmpouttraps++;
+}
+
+void snmp_get_snmpgrpid_ptr(struct snmp_obj_id **oid)
+{
+  *oid = &snmpgrp_id;
+}
+
+void snmp_set_snmpenableauthentraps(u8_t *value)
+{
+  if (value != NULL)
+  {
+    snmpenableauthentraps_ptr = value;
+  }
+}
+
+void snmp_get_snmpenableauthentraps(u8_t *value)
+{
+  *value = *snmpenableauthentraps_ptr;
+}
+
+void
+noleafs_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  if (ident_len){}
+  if (ident){}
+  od->instance = MIB_OBJECT_NONE;
+}
+
+void
+noleafs_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  if (od){}
+  if (len){}
+  if (value){}
+}
+
+u8_t
+noleafs_set_test(struct obj_def *od, u16_t len, void *value)
+{
+  if (od){}
+  if (len){}
+  if (value){}
+  /* can't set */
+  return 0;
+}
+
+void
+noleafs_set_value(struct obj_def *od, u16_t len, void *value)
+{
+  if (od){}
+  if (len){}
+  if (value){}
+}
+
+
+/**
+ * Returns systems object definitions.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.0 (object id trailer)
+ * @param od points to object definition.
+ */
+static void
+system_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  u8_t id;
+
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def system.%"U16_F".0\n",(u16_t)id));
+    switch (id)
+    {
+      case 1: /* sysDescr */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = *sysdescr_len_ptr;
+        break;
+      case 2: /* sysObjectID */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID);
+        od->v_len = sysobjid.len * sizeof(s32_t);
+        break;
+      case 3: /* sysUpTime */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 4: /* sysContact */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = *syscontact_len_ptr;
+        break;
+      case 5: /* sysName */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = *sysname_len_ptr;
+        break;
+      case 6: /* sysLocation */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = *syslocation_len_ptr;
+        break;
+      case 7: /* sysServices */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("system_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("system_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+/**
+ * Returns system object value.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.0 (object id trailer)
+ * @param len return value space (in bytes)
+ * @param value points to (varbind) space to copy value into.
+ */
+static void
+system_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* sysDescr */
+      ocstrncpy(value,sysdescr_ptr,len);
+      break;
+    case 2: /* sysObjectID */
+      objectidncpy((s32_t*)value,(s32_t*)sysobjid.id,len / sizeof(s32_t));
+      break;
+    case 3: /* sysUpTime */
+      {
+        snmp_get_sysuptime(value);
+      }
+      break;
+    case 4: /* sysContact */
+      ocstrncpy(value,syscontact_ptr,len);
+      break;
+    case 5: /* sysName */
+      ocstrncpy(value,sysname_ptr,len);
+      break;
+    case 6: /* sysLocation */
+      ocstrncpy(value,syslocation_ptr,len);
+      break;
+    case 7: /* sysServices */
+      {
+        s32_t *sint_ptr = value;
+        *sint_ptr = sysservices;
+      }
+      break;
+  };
+}
+
+static u8_t
+system_set_test(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id, set_ok;
+
+  if (value) {}
+  set_ok = 0;
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 4: /* sysContact */
+      if ((syscontact_ptr != syscontact_default) &&
+          (len <= 255))
+      {
+        set_ok = 1;
+      }
+      break;
+    case 5: /* sysName */
+      if ((sysname_ptr != sysname_default) &&
+          (len <= 255))
+      {
+        set_ok = 1;
+      }
+      break;
+    case 6: /* sysLocation */
+      if ((syslocation_ptr != syslocation_default) &&
+          (len <= 255))
+      {
+        set_ok = 1;
+      }
+      break;
+  };
+  return set_ok;
+}
+
+static void
+system_set_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 4: /* sysContact */
+      ocstrncpy(syscontact_ptr,value,len);
+      *syscontact_len_ptr = len;
+      break;
+    case 5: /* sysName */
+      ocstrncpy(sysname_ptr,value,len);
+      *sysname_len_ptr = len;
+      break;
+    case 6: /* sysLocation */
+      ocstrncpy(syslocation_ptr,value,len);
+      *syslocation_len_ptr = len;
+      break;
+  };
+}
+
+/**
+ * Returns interfaces.ifnumber object definition.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.index
+ * @param od points to object definition.
+ */
+static void
+interfaces_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    od->instance = MIB_OBJECT_SCALAR;
+    od->access = MIB_OBJECT_READ_ONLY;
+    od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+    od->v_len = sizeof(s32_t);
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("interfaces_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+/**
+ * Returns interfaces.ifnumber object value.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.0 (object id trailer)
+ * @param len return value space (in bytes)
+ * @param value points to (varbind) space to copy value into.
+ */
+static void
+interfaces_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  if (len){}
+  if (od->id_inst_ptr[0] == 1)
+  {
+    s32_t *sint_ptr = value;
+    *sint_ptr = iflist_root.count;
+  }
+}
+
+/**
+ * Returns ifentry object definitions.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.index
+ * @param od points to object definition.
+ */
+static void
+ifentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  u8_t id;
+
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def ifentry.%"U16_F"\n",(u16_t)id));
+    switch (id)
+    {
+      case 1: /* ifIndex */
+      case 3: /* ifType */
+      case 4: /* ifMtu */
+      case 8: /* ifOperStatus */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 2: /* ifDescr */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        /** @todo this should be some sort of sizeof(struct netif.name) */
+        od->v_len = 2;
+        break;
+      case 5: /* ifSpeed */
+      case 21: /* ifOutQLen */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 6: /* ifPhysAddress */
+        {
+          struct netif *netif;
+
+          snmp_ifindextonetif(ident[1], &netif);
+          od->instance = MIB_OBJECT_TAB;
+          od->access = MIB_OBJECT_READ_ONLY;
+          od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+          od->v_len = netif->hwaddr_len;
+        }
+        break;
+      case 7: /* ifAdminStatus */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 9: /* ifLastChange */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 10: /* ifInOctets */
+      case 11: /* ifInUcastPkts */
+      case 12: /* ifInNUcastPkts */
+      case 13: /* ifInDiscarts */
+      case 14: /* ifInErrors */
+      case 15: /* ifInUnkownProtos */
+      case 16: /* ifOutOctets */
+      case 17: /* ifOutUcastPkts */
+      case 18: /* ifOutNUcastPkts */
+      case 19: /* ifOutDiscarts */
+      case 20: /* ifOutErrors */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 22: /* ifSpecific */
+        /** @note returning zeroDotZero (0.0) no media specific MIB support */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID);
+        od->v_len = ifspecific.len * sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ifentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("ifentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+/**
+ * Returns ifentry object value.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.0 (object id trailer)
+ * @param len return value space (in bytes)
+ * @param value points to (varbind) space to copy value into.
+ */
+static void
+ifentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  struct netif *netif;
+  u8_t id;
+
+  snmp_ifindextonetif(od->id_inst_ptr[1], &netif);
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* ifIndex */
+      {
+        s32_t *sint_ptr = value;
+        *sint_ptr = od->id_inst_ptr[1];
+      }
+      break;
+    case 2: /* ifDescr */
+      ocstrncpy(value,(u8_t*)netif->name,len);
+      break;
+    case 3: /* ifType */
+      {
+        s32_t *sint_ptr = value;
+        *sint_ptr = netif->link_type;
+      }
+      break;
+    case 4: /* ifMtu */
+      {
+        s32_t *sint_ptr = value;
+        *sint_ptr = netif->mtu;
+      }
+      break;
+    case 5: /* ifSpeed */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->link_speed;
+      }
+      break;
+    case 6: /* ifPhysAddress */
+      ocstrncpy(value,netif->hwaddr,len);
+      break;
+    case 7: /* ifAdminStatus */
+#if LWIP_NETIF_LINK_CALLBACK
+      {
+        s32_t *sint_ptr = value;
+        if (netif_is_up(netif))
+        {
+          if (netif_is_link_up(netif))
+          {
+            *sint_ptr = 1; /* up */
+          }
+          else
+          {
+            *sint_ptr = 7; /* lowerLayerDown */
+          }
+        }
+        else
+        {
+          *sint_ptr = 2; /* down */
+        }
+      }
+      break;
+#endif
+    case 8: /* ifOperStatus */
+      {
+        s32_t *sint_ptr = value;
+        if (netif_is_up(netif))
+        {
+          *sint_ptr = 1;
+        }
+        else
+        {
+          *sint_ptr = 2;
+        }
+      }
+      break;
+    case 9: /* ifLastChange */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ts;
+      }
+      break;
+    case 10: /* ifInOctets */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifinoctets;
+      }
+      break;
+    case 11: /* ifInUcastPkts */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifinucastpkts;
+      }
+      break;
+    case 12: /* ifInNUcastPkts */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifinnucastpkts;
+      }
+      break;
+    case 13: /* ifInDiscarts */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifindiscards;
+      }
+      break;
+    case 14: /* ifInErrors */
+    case 15: /* ifInUnkownProtos */
+      /** @todo add these counters! */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = 0;
+      }
+      break;
+    case 16: /* ifOutOctets */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifoutoctets;
+      }
+      break;
+    case 17: /* ifOutUcastPkts */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifoutucastpkts;
+      }
+      break;
+    case 18: /* ifOutNUcastPkts */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifoutnucastpkts;
+      }
+      break;
+    case 19: /* ifOutDiscarts */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifoutdiscards;
+      }
+      break;
+    case 20: /* ifOutErrors */
+       /** @todo add this counter! */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = 0;
+      }
+      break;
+    case 21: /* ifOutQLen */
+      /** @todo figure out if this must be 0 (no queue) or 1? */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = 0;
+      }
+      break;
+    case 22: /* ifSpecific */
+      objectidncpy((s32_t*)value,(s32_t*)ifspecific.id,len / sizeof(s32_t));
+      break;
+  };
+}
+
+#if !SNMP_SAFE_REQUESTS
+static u8_t
+ifentry_set_test (struct obj_def *od, u16_t len, void *value)
+{
+  struct netif *netif;
+  u8_t id, set_ok;
+
+  set_ok = 0;
+  snmp_ifindextonetif(od->id_inst_ptr[1], &netif);
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 7: /* ifAdminStatus */
+      {
+        s32_t *sint_ptr = value;
+        if (*sint_ptr == 1 || *sint_ptr == 2)
+          set_ok = 1;
+      }
+      break;
+  }
+  return set_ok;
+}
+
+static void
+ifentry_set_value (struct obj_def *od, u16_t len, void *value)
+{
+  struct netif *netif;
+  u8_t id;
+
+  snmp_ifindextonetif(od->id_inst_ptr[1], &netif);
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 7: /* ifAdminStatus */
+      {
+        s32_t *sint_ptr = value;
+        if (*sint_ptr == 1)
+        {
+          netif_set_up(netif);
+        }
+        else if (*sint_ptr == 2)
+        {
+          netif_set_down(netif);
+         }
+      }
+      break;
+  }
+}
+#endif /* SNMP_SAFE_REQUESTS */
+
+/**
+ * Returns atentry object definitions.
+ *
+ * @param ident_len the address length (6)
+ * @param ident points to objectname.atifindex.atnetaddress
+ * @param od points to object definition.
+ */
+static void
+atentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (5) */
+  ident_len += 5;
+  ident -= 5;
+
+  if (ident_len == 6)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    switch (ident[0])
+    {
+      case 1: /* atIfIndex */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 2: /* atPhysAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = 6; /** @todo try to use netif::hwaddr_len */
+        break;
+      case 3: /* atNetAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("atentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    }
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("atentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+atentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+#if LWIP_ARP
+  u8_t id;
+  struct eth_addr* ethaddr_ret;
+  struct ip_addr* ipaddr_ret;
+#endif /* LWIP_ARP */
+  struct ip_addr ip;
+  struct netif *netif;
+
+  if (len) {}
+
+  snmp_ifindextonetif(od->id_inst_ptr[1], &netif);
+  snmp_oidtoip(&od->id_inst_ptr[2], &ip);
+  ip.addr = htonl(ip.addr);
+
+#if LWIP_ARP /** @todo implement a netif_find_addr */
+  if (etharp_find_addr(netif, &ip, ðaddr_ret, &ipaddr_ret) > -1)
+  {
+    id = od->id_inst_ptr[0];
+    switch (id)
+    {
+      case 1: /* atIfIndex */
+        {
+          s32_t *sint_ptr = value;
+          *sint_ptr = od->id_inst_ptr[1];
+        }
+        break;
+      case 2: /* atPhysAddress */
+        {
+          struct eth_addr *dst = value;
+
+          *dst = *ethaddr_ret;
+        }
+        break;
+      case 3: /* atNetAddress */
+        {
+          struct ip_addr *dst = value;
+
+          *dst = *ipaddr_ret;
+        }
+        break;
+    }
+  }
+#endif /* LWIP_ARP */
+}
+
+static void
+ip_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  u8_t id;
+
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def ip.%"U16_F".0\n",(u16_t)id));
+    switch (id)
+    {
+      case 1: /* ipForwarding */
+      case 2: /* ipDefaultTTL */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 3: /* ipInReceives */
+      case 4: /* ipInHdrErrors */
+      case 5: /* ipInAddrErrors */
+      case 6: /* ipForwDatagrams */
+      case 7: /* ipInUnknownProtos */
+      case 8: /* ipInDiscards */
+      case 9: /* ipInDelivers */
+      case 10: /* ipOutRequests */
+      case 11: /* ipOutDiscards */
+      case 12: /* ipOutNoRoutes */
+      case 14: /* ipReasmReqds */
+      case 15: /* ipReasmOKs */
+      case 16: /* ipReasmFails */
+      case 17: /* ipFragOKs */
+      case 18: /* ipFragFails */
+      case 19: /* ipFragCreates */
+      case 23: /* ipRoutingDiscards */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 13: /* ipReasmTimeout */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+ip_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+
+  if (len) {}
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* ipForwarding */
+      {
+        s32_t *sint_ptr = value;
+#if IP_FORWARD
+        /* forwarding */
+        *sint_ptr = 1;
+#else
+        /* not-forwarding */
+        *sint_ptr = 2;
+#endif
+      }
+      break;
+    case 2: /* ipDefaultTTL */
+      {
+        s32_t *sint_ptr = value;
+        *sint_ptr = IP_DEFAULT_TTL;
+      }
+      break;
+    case 3: /* ipInReceives */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipinreceives;
+      }
+      break;
+    case 4: /* ipInHdrErrors */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipinhdrerrors;
+      }
+      break;
+    case 5: /* ipInAddrErrors */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipinaddrerrors;
+      }
+      break;
+    case 6: /* ipForwDatagrams */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipforwdatagrams;
+      }
+      break;
+    case 7: /* ipInUnknownProtos */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipinunknownprotos;
+      }
+      break;
+    case 8: /* ipInDiscards */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipindiscards;
+      }
+      break;
+    case 9: /* ipInDelivers */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipindelivers;
+      }
+      break;
+    case 10: /* ipOutRequests */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipoutrequests;
+      }
+      break;
+    case 11: /* ipOutDiscards */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipoutdiscards;
+      }
+      break;
+    case 12: /* ipOutNoRoutes */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipoutnoroutes;
+      }
+      break;
+    case 13: /* ipReasmTimeout */
+      {
+        s32_t *sint_ptr = value;
+#if IP_REASSEMBLY
+        *sint_ptr = IP_REASS_MAXAGE;
+#else
+        *sint_ptr = 0;
+#endif
+      }
+      break;
+    case 14: /* ipReasmReqds */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipreasmreqds;
+      }
+      break;
+    case 15: /* ipReasmOKs */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipreasmoks;
+      }
+      break;
+    case 16: /* ipReasmFails */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipreasmfails;
+      }
+      break;
+    case 17: /* ipFragOKs */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipfragoks;
+      }
+      break;
+    case 18: /* ipFragFails */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipfragfails;
+      }
+      break;
+    case 19: /* ipFragCreates */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipfragcreates;
+      }
+      break;
+    case 23: /* ipRoutingDiscards */
+      /** @todo can lwIP discard routes at all?? hardwire this to 0?? */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = iproutingdiscards;
+      }
+      break;
+  };
+}
+
+/**
+ * Test ip object value before setting.
+ *
+ * @param od is the object definition
+ * @param len return value space (in bytes)
+ * @param value points to (varbind) space to copy value from.
+ *
+ * @note we allow set if the value matches the hardwired value,
+ *   otherwise return badvalue.
+ */
+static u8_t
+ip_set_test(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id, set_ok;
+  s32_t *sint_ptr = value;
+
+  if (len) {}
+  set_ok = 0;
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* ipForwarding */
+#if IP_FORWARD
+      /* forwarding */
+      if (*sint_ptr == 1)
+#else
+      /* not-forwarding */
+      if (*sint_ptr == 2)
+#endif
+      {
+        set_ok = 1;
+      }
+      break;
+    case 2: /* ipDefaultTTL */
+      if (*sint_ptr == IP_DEFAULT_TTL)
+      {
+        set_ok = 1;
+      }
+      break;
+  };
+  return set_ok;
+}
+
+static void
+ip_addrentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (4) */
+  ident_len += 4;
+  ident -= 4;
+
+  if (ident_len == 5)
+  {
+    u8_t id;
+
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    switch (id)
+    {
+      case 1: /* ipAdEntAddr */
+      case 3: /* ipAdEntNetMask */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      case 2: /* ipAdEntIfIndex */
+      case 4: /* ipAdEntBcastAddr */
+      case 5: /* ipAdEntReasmMaxSize */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_addrentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    }
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_addrentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+ip_addrentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+  u16_t ifidx;
+  struct ip_addr ip;
+  struct netif *netif = netif_list;
+
+  if (len) {}
+  snmp_oidtoip(&od->id_inst_ptr[1], &ip);
+  ip.addr = htonl(ip.addr);
+  ifidx = 0;
+  while ((netif != NULL) && !ip_addr_cmp(&ip, &netif->ip_addr))
+  {
+    netif = netif->next;
+    ifidx++;
+  }
+
+  if (netif != NULL)
+  {
+    id = od->id_inst_ptr[0];
+    switch (id)
+    {
+      case 1: /* ipAdEntAddr */
+        {
+          struct ip_addr *dst = value;
+          *dst = netif->ip_addr;
+        }
+        break;
+      case 2: /* ipAdEntIfIndex */
+        {
+          s32_t *sint_ptr = value;
+          *sint_ptr = ifidx + 1;
+        }
+        break;
+      case 3: /* ipAdEntNetMask */
+        {
+          struct ip_addr *dst = value;
+          *dst = netif->netmask;
+        }
+        break;
+      case 4: /* ipAdEntBcastAddr */
+        {
+          s32_t *sint_ptr = value;
+
+          /* lwIP oddity, there's no broadcast
+            address in the netif we can rely on */
+          *sint_ptr = ip_addr_broadcast.addr & 1;
+        }
+        break;
+      case 5: /* ipAdEntReasmMaxSize */
+        {
+          s32_t *sint_ptr = value;
+#if IP_REASSEMBLY
+          /* @todo The theoretical maximum is IP_REASS_MAX_PBUFS * size of the pbufs,
+           * but only if receiving one fragmented packet at a time.
+           * The current solution is to calculate for 2 simultaneous packets...
+           */
+          *sint_ptr = (IP_HLEN + ((IP_REASS_MAX_PBUFS/2) *
+            (PBUF_POOL_BUFSIZE - PBUF_LINK_HLEN - IP_HLEN)));
+#else
+          /** @todo returning MTU would be a bad thing and
+             returning a wild guess like '576' isn't good either */
+          *sint_ptr = 0;
+#endif
+        }
+        break;
+    }
+  }
+}
+
+/**
+ * @note
+ * lwIP IP routing is currently using the network addresses in netif_list.
+ * if no suitable network IP is found in netif_list, the default_netif is used.
+ */
+static void
+ip_rteentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  u8_t id;
+
+  /* return to object name, adding index depth (4) */
+  ident_len += 4;
+  ident -= 4;
+
+  if (ident_len == 5)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    switch (id)
+    {
+      case 1: /* ipRouteDest */
+      case 7: /* ipRouteNextHop */
+      case 11: /* ipRouteMask */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      case 2: /* ipRouteIfIndex */
+      case 3: /* ipRouteMetric1 */
+      case 4: /* ipRouteMetric2 */
+      case 5: /* ipRouteMetric3 */
+      case 6: /* ipRouteMetric4 */
+      case 8: /* ipRouteType */
+      case 10: /* ipRouteAge */
+      case 12: /* ipRouteMetric5 */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 9: /* ipRouteProto */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 13: /* ipRouteInfo */
+        /** @note returning zeroDotZero (0.0) no routing protocol specific MIB */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID);
+        od->v_len = iprouteinfo.len * sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_rteentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    }
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_rteentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+ip_rteentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  struct netif *netif;
+  struct ip_addr dest;
+  s32_t *ident;
+  u8_t id;
+
+  ident = od->id_inst_ptr;
+  snmp_oidtoip(&ident[1], &dest);
+  dest.addr = htonl(dest.addr);
+
+  if (dest.addr == 0)
+  {
+    /* ip_route() uses default netif for default route */
+    netif = netif_default;
+  }
+  else
+  {
+    /* not using ip_route(), need exact match! */
+    netif = netif_list;
+    while ((netif != NULL) &&
+            !ip_addr_netcmp(&dest, &(netif->ip_addr), &(netif->netmask)) )
+    {
+      netif = netif->next;
+    }
+  }
+  if (netif != NULL)
+  {
+    id = ident[0];
+    switch (id)
+    {
+      case 1: /* ipRouteDest */
+        {
+          struct ip_addr *dst = value;
+
+          if (dest.addr == 0)
+          {
+            /* default rte has 0.0.0.0 dest */
+            dst->addr = 0;
+          }
+          else
+          {
+            /* netifs have netaddress dest */
+            dst->addr = netif->ip_addr.addr & netif->netmask.addr;
+          }
+        }
+        break;
+      case 2: /* ipRouteIfIndex */
+        {
+          s32_t *sint_ptr = value;
+
+          snmp_netiftoifindex(netif, sint_ptr);
+        }
+        break;
+      case 3: /* ipRouteMetric1 */
+        {
+          s32_t *sint_ptr = value;
+
+          if (dest.addr == 0)
+          {
+            /* default rte has metric 1 */
+            *sint_ptr = 1;
+          }
+          else
+          {
+            /* other rtes have metric 0 */
+            *sint_ptr = 0;
+          }
+        }
+        break;
+      case 4: /* ipRouteMetric2 */
+      case 5: /* ipRouteMetric3 */
+      case 6: /* ipRouteMetric4 */
+      case 12: /* ipRouteMetric5 */
+        {
+          s32_t *sint_ptr = value;
+          /* not used */
+          *sint_ptr = -1;
+        }
+        break;
+      case 7: /* ipRouteNextHop */
+        {
+          struct ip_addr *dst = value;
+
+          if (dest.addr == 0)
+          {
+            /* default rte: gateway */
+            *dst = netif->gw;
+          }
+          else
+          {
+            /* other rtes: netif ip_addr  */
+            *dst = netif->ip_addr;
+          }
+        }
+        break;
+      case 8: /* ipRouteType */
+        {
+          s32_t *sint_ptr = value;
+
+          if (dest.addr == 0)
+          {
+            /* default rte is indirect */
+            *sint_ptr = 4;
+          }
+          else
+          {
+            /* other rtes are direct */
+            *sint_ptr = 3;
+          }
+        }
+        break;
+      case 9: /* ipRouteProto */
+        {
+          s32_t *sint_ptr = value;
+          /* locally defined routes */
+          *sint_ptr = 2;
+        }
+        break;
+      case 10: /* ipRouteAge */
+        {
+          s32_t *sint_ptr = value;
+          /** @todo (sysuptime - timestamp last change) / 100
+              @see snmp_insert_iprteidx_tree() */
+          *sint_ptr = 0;
+        }
+        break;
+      case 11: /* ipRouteMask */
+        {
+          struct ip_addr *dst = value;
+
+          if (dest.addr == 0)
+          {
+            /* default rte use 0.0.0.0 mask */
+            dst->addr = 0;
+          }
+          else
+          {
+            /* other rtes use netmask */
+            *dst = netif->netmask;
+          }
+        }
+        break;
+      case 13: /* ipRouteInfo */
+        objectidncpy((s32_t*)value,(s32_t*)iprouteinfo.id,len / sizeof(s32_t));
+        break;
+    }
+  }
+}
+
+static void
+ip_ntomentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (5) */
+  ident_len += 5;
+  ident -= 5;
+
+  if (ident_len == 6)
+  {
+    u8_t id;
+
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    switch (id)
+    {
+      case 1: /* ipNetToMediaIfIndex */
+      case 4: /* ipNetToMediaType */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 2: /* ipNetToMediaPhysAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = 6; /** @todo try to use netif::hwaddr_len */
+        break;
+      case 3: /* ipNetToMediaNetAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_ntomentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    }
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_ntomentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+ip_ntomentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+#if LWIP_ARP
+  u8_t id;
+  struct eth_addr* ethaddr_ret;
+  struct ip_addr* ipaddr_ret;
+#endif /* LWIP_ARP */
+  struct ip_addr ip;
+  struct netif *netif;
+
+  if (len) {}
+
+  snmp_ifindextonetif(od->id_inst_ptr[1], &netif);
+  snmp_oidtoip(&od->id_inst_ptr[2], &ip);
+  ip.addr = htonl(ip.addr);
+
+#if LWIP_ARP /** @todo implement a netif_find_addr */
+  if (etharp_find_addr(netif, &ip, ðaddr_ret, &ipaddr_ret) > -1)
+  {
+    id = od->id_inst_ptr[0];
+    switch (id)
+    {
+      case 1: /* ipNetToMediaIfIndex */
+        {
+          s32_t *sint_ptr = value;
+          *sint_ptr = od->id_inst_ptr[1];
+        }
+        break;
+      case 2: /* ipNetToMediaPhysAddress */
+        {
+          struct eth_addr *dst = value;
+
+          *dst = *ethaddr_ret;
+        }
+        break;
+      case 3: /* ipNetToMediaNetAddress */
+        {
+          struct ip_addr *dst = value;
+
+          *dst = *ipaddr_ret;
+        }
+        break;
+      case 4: /* ipNetToMediaType */
+        {
+          s32_t *sint_ptr = value;
+          /* dynamic (?) */
+          *sint_ptr = 3;
+        }
+        break;
+    }
+  }
+#endif /* LWIP_ARP */
+}
+
+static void
+icmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if ((ident_len == 2) &&
+      (ident[0] > 0) && (ident[0] < 27))
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    od->instance = MIB_OBJECT_SCALAR;
+    od->access = MIB_OBJECT_READ_ONLY;
+    od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+    od->v_len = sizeof(u32_t);
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("icmp_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+icmp_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u32_t *uint_ptr = value;
+  u8_t id;
+
+  if (len){}
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* icmpInMsgs */
+      *uint_ptr = icmpinmsgs;
+      break;
+    case 2: /* icmpInErrors */
+      *uint_ptr = icmpinerrors;
+      break;
+    case 3: /* icmpInDestUnreachs */
+      *uint_ptr = icmpindestunreachs;
+      break;
+    case 4: /* icmpInTimeExcds */
+      *uint_ptr = icmpintimeexcds;
+      break;
+    case 5: /* icmpInParmProbs */
+      *uint_ptr = icmpinparmprobs;
+      break;
+    case 6: /* icmpInSrcQuenchs */
+      *uint_ptr = icmpinsrcquenchs;
+      break;
+    case 7: /* icmpInRedirects */
+      *uint_ptr = icmpinredirects;
+      break;
+    case 8: /* icmpInEchos */
+      *uint_ptr = icmpinechos;
+      break;
+    case 9: /* icmpInEchoReps */
+      *uint_ptr = icmpinechoreps;
+      break;
+    case 10: /* icmpInTimestamps */
+      *uint_ptr = icmpintimestamps;
+      break;
+    case 11: /* icmpInTimestampReps */
+      *uint_ptr = icmpintimestampreps;
+      break;
+    case 12: /* icmpInAddrMasks */
+      *uint_ptr = icmpinaddrmasks;
+      break;
+    case 13: /* icmpInAddrMaskReps */
+      *uint_ptr = icmpinaddrmaskreps;
+      break;
+    case 14: /* icmpOutMsgs */
+      *uint_ptr = icmpoutmsgs;
+      break;
+    case 15: /* icmpOutErrors */
+      *uint_ptr = icmpouterrors;
+      break;
+    case 16: /* icmpOutDestUnreachs */
+      *uint_ptr = icmpoutdestunreachs;
+      break;
+    case 17: /* icmpOutTimeExcds */
+      *uint_ptr = icmpouttimeexcds;
+      break;
+    case 18: /* icmpOutParmProbs */
+      *uint_ptr = icmpoutparmprobs;
+      break;
+    case 19: /* icmpOutSrcQuenchs */
+      *uint_ptr = icmpoutsrcquenchs;
+      break;
+    case 20: /* icmpOutRedirects */
+      *uint_ptr = icmpoutredirects;
+      break;
+    case 21: /* icmpOutEchos */
+      *uint_ptr = icmpoutechos;
+      break;
+    case 22: /* icmpOutEchoReps */
+      *uint_ptr = icmpoutechoreps;
+      break;
+    case 23: /* icmpOutTimestamps */
+      *uint_ptr = icmpouttimestamps;
+      break;
+    case 24: /* icmpOutTimestampReps */
+      *uint_ptr = icmpouttimestampreps;
+      break;
+    case 25: /* icmpOutAddrMasks */
+      *uint_ptr = icmpoutaddrmasks;
+      break;
+    case 26: /* icmpOutAddrMaskReps */
+      *uint_ptr = icmpoutaddrmaskreps;
+      break;
+  }
+}
+
+#if LWIP_TCP
+/** @todo tcp grp */
+static void
+tcp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  u8_t id;
+
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def tcp.%"U16_F".0\n",(u16_t)id));
+
+    switch (id)
+    {
+      case 1: /* tcpRtoAlgorithm */
+      case 2: /* tcpRtoMin */
+      case 3: /* tcpRtoMax */
+      case 4: /* tcpMaxConn */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 5: /* tcpActiveOpens */
+      case 6: /* tcpPassiveOpens */
+      case 7: /* tcpAttemptFails */
+      case 8: /* tcpEstabResets */
+      case 10: /* tcpInSegs */
+      case 11: /* tcpOutSegs */
+      case 12: /* tcpRetransSegs */
+      case 14: /* tcpInErrs */
+      case 15: /* tcpOutRsts */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 9: /* tcpCurrEstab */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE);
+        od->v_len = sizeof(u32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcp_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcp_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+tcp_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u32_t *uint_ptr = value;
+  s32_t *sint_ptr = value;
+  u8_t id;
+
+  if (len){}
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* tcpRtoAlgorithm, vanj(4) */
+      *sint_ptr = 4;
+      break;
+    case 2: /* tcpRtoMin */
+      /* @todo not the actual value, a guess,
+          needs to be calculated */
+      *sint_ptr = 1000;
+      break;
+    case 3: /* tcpRtoMax */
+      /* @todo not the actual value, a guess,
+         needs to be calculated */
+      *sint_ptr = 60000;
+      break;
+    case 4: /* tcpMaxConn */
+      *sint_ptr = MEMP_NUM_TCP_PCB;
+      break;
+    case 5: /* tcpActiveOpens */
+      *uint_ptr = tcpactiveopens;
+      break;
+    case 6: /* tcpPassiveOpens */
+      *uint_ptr = tcppassiveopens;
+      break;
+    case 7: /* tcpAttemptFails */
+      *uint_ptr = tcpattemptfails;
+      break;
+    case 8: /* tcpEstabResets */
+      *uint_ptr = tcpestabresets;
+      break;
+    case 9: /* tcpCurrEstab */
+      {
+        u16_t tcpcurrestab = 0;
+        struct tcp_pcb *pcb = tcp_active_pcbs;
+        while (pcb != NULL)
+        {
+          if ((pcb->state == ESTABLISHED) ||
+              (pcb->state == CLOSE_WAIT))
+          {
+            tcpcurrestab++;
+          }
+          pcb = pcb->next;
+        }
+        *uint_ptr = tcpcurrestab;
+      }
+      break;
+    case 10: /* tcpInSegs */
+      *uint_ptr = tcpinsegs;
+      break;
+    case 11: /* tcpOutSegs */
+      *uint_ptr = tcpoutsegs;
+      break;
+    case 12: /* tcpRetransSegs */
+      *uint_ptr = tcpretranssegs;
+      break;
+    case 14: /* tcpInErrs */
+      *uint_ptr = tcpinerrs;
+      break;
+    case 15: /* tcpOutRsts */
+      *uint_ptr = tcpoutrsts;
+      break;
+  }
+}
+#ifdef THIS_SEEMS_UNUSED
+static void
+tcpconnentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (10) */
+  ident_len += 10;
+  ident -= 10;
+
+  if (ident_len == 11)
+  {
+    u8_t id;
+
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def tcp.%"U16_F".0\n",(u16_t)id));
+
+    switch (id)
+    {
+      case 1: /* tcpConnState */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 2: /* tcpConnLocalAddress */
+      case 4: /* tcpConnRemAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      case 3: /* tcpConnLocalPort */
+      case 5: /* tcpConnRemPort */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcpconnentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcpconnentry_get_object_def: no such object\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+tcpconnentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  struct ip_addr lip, rip;
+  u16_t lport, rport;
+  s32_t *ident;
+
+  ident = od->id_inst_ptr;
+  snmp_oidtoip(&ident[1], &lip);
+  lip.addr = htonl(lip.addr);
+  lport = ident[5];
+  snmp_oidtoip(&ident[6], &rip);
+  rip.addr = htonl(rip.addr);
+  rport = ident[10];
+
+  /** @todo find matching PCB */
+}
+#endif /* if 0 */
+#endif
+
+static void
+udp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if ((ident_len == 2) &&
+      (ident[0] > 0) && (ident[0] < 6))
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    od->instance = MIB_OBJECT_SCALAR;
+    od->access = MIB_OBJECT_READ_ONLY;
+    od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+    od->v_len = sizeof(u32_t);
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("udp_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+udp_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u32_t *uint_ptr = value;
+  u8_t id;
+
+  if (len){}
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* udpInDatagrams */
+      *uint_ptr = udpindatagrams;
+      break;
+    case 2: /* udpNoPorts */
+      *uint_ptr = udpnoports;
+      break;
+    case 3: /* udpInErrors */
+      *uint_ptr = udpinerrors;
+      break;
+    case 4: /* udpOutDatagrams */
+      *uint_ptr = udpoutdatagrams;
+      break;
+  }
+}
+
+static void
+udpentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (5) */
+  ident_len += 5;
+  ident -= 5;
+
+  if (ident_len == 6)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    switch (ident[0])
+    {
+      case 1: /* udpLocalAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      case 2: /* udpLocalPort */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("udpentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    }
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("udpentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+udpentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+  struct udp_pcb *pcb;
+  struct ip_addr ip;
+  u16_t port;
+
+  if (len){}
+  snmp_oidtoip(&od->id_inst_ptr[1], &ip);
+  ip.addr = htonl(ip.addr);
+  port = od->id_inst_ptr[5];
+
+  pcb = udp_pcbs;
+  while ((pcb != NULL) &&
+         !((pcb->local_ip.addr == ip.addr) &&
+           (pcb->local_port == port)))
+  {
+    pcb = pcb->next;
+  }
+
+  if (pcb != NULL)
+  {
+    id = od->id_inst_ptr[0];
+    switch (id)
+    {
+      case 1: /* udpLocalAddress */
+        {
+          struct ip_addr *dst = value;
+          *dst = pcb->local_ip;
+        }
+        break;
+      case 2: /* udpLocalPort */
+        {
+          s32_t *sint_ptr = value;
+          *sint_ptr = pcb->local_port;
+        }
+        break;
+    }
+  }
+}
+
+static void
+snmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    u8_t id;
+
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    switch (id)
+    {
+      case 1: /* snmpInPkts */
+      case 2: /* snmpOutPkts */
+      case 3: /* snmpInBadVersions */
+      case 4: /* snmpInBadCommunityNames */
+      case 5: /* snmpInBadCommunityUses */
+      case 6: /* snmpInASNParseErrs */
+      case 8: /* snmpInTooBigs */
+      case 9: /* snmpInNoSuchNames */
+      case 10: /* snmpInBadValues */
+      case 11: /* snmpInReadOnlys */
+      case 12: /* snmpInGenErrs */
+      case 13: /* snmpInTotalReqVars */
+      case 14: /* snmpInTotalSetVars */
+      case 15: /* snmpInGetRequests */
+      case 16: /* snmpInGetNexts */
+      case 17: /* snmpInSetRequests */
+      case 18: /* snmpInGetResponses */
+      case 19: /* snmpInTraps */
+      case 20: /* snmpOutTooBigs */
+      case 21: /* snmpOutNoSuchNames */
+      case 22: /* snmpOutBadValues */
+      case 24: /* snmpOutGenErrs */
+      case 25: /* snmpOutGetRequests */
+      case 26: /* snmpOutGetNexts */
+      case 27: /* snmpOutSetRequests */
+      case 28: /* snmpOutGetResponses */
+      case 29: /* snmpOutTraps */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 30: /* snmpEnableAuthenTraps */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+snmp_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u32_t *uint_ptr = value;
+  u8_t id;
+
+  if (len){}
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+      case 1: /* snmpInPkts */
+        *uint_ptr = snmpinpkts;
+        break;
+      case 2: /* snmpOutPkts */
+        *uint_ptr = snmpoutpkts;
+        break;
+      case 3: /* snmpInBadVersions */
+        *uint_ptr = snmpinbadversions;
+        break;
+      case 4: /* snmpInBadCommunityNames */
+        *uint_ptr = snmpinbadcommunitynames;
+        break;
+      case 5: /* snmpInBadCommunityUses */
+        *uint_ptr = snmpinbadcommunityuses;
+        break;
+      case 6: /* snmpInASNParseErrs */
+        *uint_ptr = snmpinasnparseerrs;
+        break;
+      case 8: /* snmpInTooBigs */
+        *uint_ptr = snmpintoobigs;
+        break;
+      case 9: /* snmpInNoSuchNames */
+        *uint_ptr = snmpinnosuchnames;
+        break;
+      case 10: /* snmpInBadValues */
+        *uint_ptr = snmpinbadvalues;
+        break;
+      case 11: /* snmpInReadOnlys */
+        *uint_ptr = snmpinreadonlys;
+        break;
+      case 12: /* snmpInGenErrs */
+        *uint_ptr = snmpingenerrs;
+        break;
+      case 13: /* snmpInTotalReqVars */
+        *uint_ptr = snmpintotalreqvars;
+        break;
+      case 14: /* snmpInTotalSetVars */
+        *uint_ptr = snmpintotalsetvars;
+        break;
+      case 15: /* snmpInGetRequests */
+        *uint_ptr = snmpingetrequests;
+        break;
+      case 16: /* snmpInGetNexts */
+        *uint_ptr = snmpingetnexts;
+        break;
+      case 17: /* snmpInSetRequests */
+        *uint_ptr = snmpinsetrequests;
+        break;
+      case 18: /* snmpInGetResponses */
+        *uint_ptr = snmpingetresponses;
+        break;
+      case 19: /* snmpInTraps */
+        *uint_ptr = snmpintraps;
+        break;
+      case 20: /* snmpOutTooBigs */
+        *uint_ptr = snmpouttoobigs;
+        break;
+      case 21: /* snmpOutNoSuchNames */
+        *uint_ptr = snmpoutnosuchnames;
+        break;
+      case 22: /* snmpOutBadValues */
+        *uint_ptr = snmpoutbadvalues;
+        break;
+      case 24: /* snmpOutGenErrs */
+        *uint_ptr = snmpoutgenerrs;
+        break;
+      case 25: /* snmpOutGetRequests */
+        *uint_ptr = snmpoutgetrequests;
+        break;
+      case 26: /* snmpOutGetNexts */
+        *uint_ptr = snmpoutgetnexts;
+        break;
+      case 27: /* snmpOutSetRequests */
+        *uint_ptr = snmpoutsetrequests;
+        break;
+      case 28: /* snmpOutGetResponses */
+        *uint_ptr = snmpoutgetresponses;
+        break;
+      case 29: /* snmpOutTraps */
+        *uint_ptr = snmpouttraps;
+        break;
+      case 30: /* snmpEnableAuthenTraps */
+        *uint_ptr = *snmpenableauthentraps_ptr;
+        break;
+  };
+}
+
+/**
+ * Test snmp object value before setting.
+ *
+ * @param od is the object definition
+ * @param len return value space (in bytes)
+ * @param value points to (varbind) space to copy value from.
+ */
+static u8_t
+snmp_set_test(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id, set_ok;
+
+  if (len) {}
+  set_ok = 0;
+  id = od->id_inst_ptr[0];
+  if (id == 30)
+  {
+    /* snmpEnableAuthenTraps */
+    s32_t *sint_ptr = value;
+
+    if (snmpenableauthentraps_ptr != &snmpenableauthentraps_default)
+    {
+      /* we should have writable non-volatile mem here */
+      if ((*sint_ptr == 1) || (*sint_ptr == 2))
+      {
+        set_ok = 1;
+      }
+    }
+    else
+    {
+      /* const or hardwired value */
+      if (*sint_ptr == snmpenableauthentraps_default)
+      {
+        set_ok = 1;
+      }
+    }
+  }
+  return set_ok;
+}
+
+static void
+snmp_set_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+
+  if (len) {}
+  id = od->id_inst_ptr[0];
+  if (id == 30)
+  {
+    /* snmpEnableAuthenTraps */
+    s32_t *sint_ptr = value;
+    *snmpenableauthentraps_ptr = *sint_ptr;
+  }
+}
+
+#endif /* LWIP_SNMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/snmp/mib_structs.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/snmp/mib_structs.c
new file mode 100644
index 0000000..cff50b5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/snmp/mib_structs.c
@@ -0,0 +1,1183 @@
+/**
+ * @file
+ * MIB tree access/construction functions.
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/snmp_structs.h"
+#include "lwip/mem.h"
+
+/** .iso.org.dod.internet address prefix, @see snmp_iso_*() */
+const s32_t prefix[4] = {1, 3, 6, 1};
+
+#define NODE_STACK_SIZE (LWIP_SNMP_OBJ_ID_LEN)
+/** node stack entry (old news?) */
+struct nse
+{
+  /** right child */
+  struct mib_node* r_ptr;
+  /** right child identifier */
+  s32_t r_id;
+  /** right child next level */
+  u8_t r_nl;
+};
+static u8_t node_stack_cnt;
+static struct nse node_stack[NODE_STACK_SIZE];
+
+/**
+ * Pushes nse struct onto stack.
+ */
+static void
+push_node(struct nse* node)
+{
+  LWIP_ASSERT("node_stack_cnt < NODE_STACK_SIZE",node_stack_cnt < NODE_STACK_SIZE);
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("push_node() node=%p id=%"S32_F"\n",(void*)(node->r_ptr),node->r_id));
+  if (node_stack_cnt < NODE_STACK_SIZE)
+  {
+    node_stack[node_stack_cnt] = *node;
+    node_stack_cnt++;
+  }
+}
+
+/**
+ * Pops nse struct from stack.
+ */
+static void
+pop_node(struct nse* node)
+{
+  if (node_stack_cnt > 0)
+  {
+    node_stack_cnt--;
+    *node = node_stack[node_stack_cnt];
+  }
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("pop_node() node=%p id=%"S32_F"\n",(void *)(node->r_ptr),node->r_id));
+}
+
+/**
+ * Conversion from ifIndex to lwIP netif
+ * @param ifindex is a s32_t object sub-identifier
+ * @param netif points to returned netif struct pointer
+ */
+void
+snmp_ifindextonetif(s32_t ifindex, struct netif **netif)
+{
+  struct netif *nif = netif_list;
+  u16_t i, ifidx;
+
+  ifidx = ifindex - 1;
+  i = 0;
+  while ((nif != NULL) && (i < ifidx))
+  {
+    nif = nif->next;
+    i++;
+  }
+  *netif = nif;
+}
+
+/**
+ * Conversion from lwIP netif to ifIndex
+ * @param netif points to a netif struct
+ * @param ifidx points to s32_t object sub-identifier
+ */
+void
+snmp_netiftoifindex(struct netif *netif, s32_t *ifidx)
+{
+  struct netif *nif = netif_list;
+  u16_t i;
+
+  i = 0;
+  while (nif != netif)
+  {
+    nif = nif->next;
+    i++;
+  }
+  *ifidx = i+1;
+}
+
+/**
+ * Conversion from oid to lwIP ip_addr
+ * @param ident points to s32_t ident[4] input
+ * @param ip points to output struct
+ */
+void
+snmp_oidtoip(s32_t *ident, struct ip_addr *ip)
+{
+  u32_t ipa;
+
+  ipa = ident[0];
+  ipa <<= 8;
+  ipa |= ident[1];
+  ipa <<= 8;
+  ipa |= ident[2];
+  ipa <<= 8;
+  ipa |= ident[3];
+  ip->addr = ipa;
+}
+
+/**
+ * Conversion from lwIP ip_addr to oid
+ * @param ip points to input struct
+ * @param ident points to s32_t ident[4] output
+ */
+void
+snmp_iptooid(struct ip_addr *ip, s32_t *ident)
+{
+  u32_t ipa;
+
+  ipa = ip->addr;
+  ident[0] = (ipa >> 24) & 0xff;
+  ident[1] = (ipa >> 16) & 0xff;
+  ident[2] = (ipa >> 8) & 0xff;
+  ident[3] = ipa & 0xff;
+}
+
+struct mib_list_node *
+snmp_mib_ln_alloc(s32_t id)
+{
+  struct mib_list_node *ln;
+
+  ln = (struct mib_list_node *)mem_malloc(sizeof(struct mib_list_node));
+  if (ln != NULL)
+  {
+    ln->prev = NULL;
+    ln->next = NULL;
+    ln->objid = id;
+    ln->nptr = NULL;
+  }
+  return ln;
+}
+
+void
+snmp_mib_ln_free(struct mib_list_node *ln)
+{
+  mem_free(ln);
+}
+
+struct mib_list_rootnode *
+snmp_mib_lrn_alloc(void)
+{
+  struct mib_list_rootnode *lrn;
+
+  lrn = (struct mib_list_rootnode*)mem_malloc(sizeof(struct mib_list_rootnode));
+  if (lrn != NULL)
+  {
+    lrn->get_object_def = noleafs_get_object_def;
+    lrn->get_value = noleafs_get_value;
+    lrn->set_test = noleafs_set_test;
+    lrn->set_value = noleafs_set_value;
+    lrn->node_type = MIB_NODE_LR;
+    lrn->maxlength = 0;
+    lrn->head = NULL;
+    lrn->tail = NULL;
+    lrn->count = 0;
+  }
+  return lrn;
+}
+
+void
+snmp_mib_lrn_free(struct mib_list_rootnode *lrn)
+{
+  mem_free(lrn);
+}
+
+/**
+ * Inserts node in idx list in a sorted
+ * (ascending order) fashion and
+ * allocates the node if needed.
+ *
+ * @param rn points to the root node
+ * @param objid is the object sub identifier
+ * @param insn points to a pointer to the inserted node
+ *   used for constructing the tree.
+ * @return -1 if failed, 1 if inserted, 2 if present.
+ */
+s8_t
+snmp_mib_node_insert(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **insn)
+{
+  struct mib_list_node *nn;
+  s8_t insert;
+
+  LWIP_ASSERT("rn != NULL",rn != NULL);
+
+  /* -1 = malloc failure, 0 = not inserted, 1 = inserted, 2 = was present */
+  insert = 0;
+  if (rn->head == NULL)
+  {
+    /* empty list, add first node */
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc empty list objid==%"S32_F"\n",objid));
+    nn = snmp_mib_ln_alloc(objid);
+    if (nn != NULL)
+    {
+      rn->head = nn;
+      rn->tail = nn;
+      *insn = nn;
+      insert = 1;
+    }
+    else
+    {
+      insert = -1;
+    }
+  }
+  else
+  {
+    struct mib_list_node *n;
+    /* at least one node is present */
+    n = rn->head;
+    while ((n != NULL) && (insert == 0))
+    {
+      if (n->objid == objid)
+      {
+        /* node is already there */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("node already there objid==%"S32_F"\n",objid));
+        *insn = n;
+        insert = 2;
+      }
+      else if (n->objid < objid)
+      {
+        if (n->next == NULL)
+        {
+          /* alloc and insert at the tail */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc ins tail objid==%"S32_F"\n",objid));
+          nn = snmp_mib_ln_alloc(objid);
+          if (nn != NULL)
+          {
+            nn->next = NULL;
+            nn->prev = n;
+            n->next = nn;
+            rn->tail = nn;
+            *insn = nn;
+            insert = 1;
+          }
+          else
+          {
+            /* insertion failure */
+            insert = -1;
+          }
+        }
+        else
+        {
+          /* there's more to explore: traverse list */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("traverse list\n"));
+          n = n->next;
+        }
+      }
+      else
+      {
+        /* n->objid > objid */
+        /* alloc and insert between n->prev and n */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc ins n->prev, objid==%"S32_F", n\n",objid));
+        nn = snmp_mib_ln_alloc(objid);
+        if (nn != NULL)
+        {
+          if (n->prev == NULL)
+          {
+            /* insert at the head */
+            nn->next = n;
+            nn->prev = NULL;
+            rn->head = nn;
+            n->prev = nn;
+          }
+          else
+          {
+            /* insert in the middle */
+            nn->next = n;
+            nn->prev = n->prev;
+            n->prev->next = nn;
+            n->prev = nn;
+          }
+          *insn = nn;
+          insert = 1;
+        }
+        else
+        {
+          /* insertion failure */
+          insert = -1;
+        }
+      }
+    }
+  }
+  if (insert == 1)
+  {
+    rn->count += 1;
+  }
+  LWIP_ASSERT("insert != 0",insert != 0);
+  return insert;
+}
+
+/**
+ * Finds node in idx list and returns deletion mark.
+ *
+ * @param rn points to the root node
+ * @param objid  is the object sub identifier
+ * @param fn returns pointer to found node
+ * @return 0 if not found, 1 if deletable,
+ *   2 can't delete (2 or more children), 3 not a list_node
+ */
+s8_t
+snmp_mib_node_find(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **fn)
+{
+  s8_t fc;
+  struct mib_list_node *n;
+
+  LWIP_ASSERT("rn != NULL",rn != NULL);
+  n = rn->head;
+  while ((n != NULL) && (n->objid != objid))
+  {
+    n = n->next;
+  }
+  if (n == NULL)
+  {
+    fc = 0;
+  }
+  else if (n->nptr == NULL)
+  {
+    /* leaf, can delete node */
+    fc = 1;
+  }
+  else
+  {
+    struct mib_list_rootnode *r;
+
+    if (n->nptr->node_type == MIB_NODE_LR)
+    {
+      r = (struct mib_list_rootnode *)n->nptr;
+      if (r->count > 1)
+      {
+        /* can't delete node */
+        fc = 2;
+      }
+      else
+      {
+        /* count <= 1, can delete node */
+        fc = 1;
+      }
+    }
+    else
+    {
+      /* other node type */
+      fc = 3;
+    }
+  }
+  *fn = n;
+  return fc;
+}
+
+/**
+ * Removes node from idx list
+ * if it has a single child left.
+ *
+ * @param rn points to the root node
+ * @param n points to the node to delete
+ * @return the nptr to be freed by caller
+ */
+struct mib_list_rootnode *
+snmp_mib_node_delete(struct mib_list_rootnode *rn, struct mib_list_node *n)
+{
+  struct mib_list_rootnode *next;
+
+  LWIP_ASSERT("rn != NULL",rn != NULL);
+  LWIP_ASSERT("n != NULL",n != NULL);
+
+  /* caller must remove this sub-tree */
+  next = (struct mib_list_rootnode*)(n->nptr);
+  rn->count -= 1;
+
+  if (n == rn->head)
+  {
+    rn->head = n->next;
+    if (n->next != NULL)
+    {
+      /* not last node, new list begin */
+      n->next->prev = NULL;
+    }
+  }
+  else if (n == rn->tail)
+  {
+    rn->tail = n->prev;
+    if (n->prev != NULL)
+    {
+      /* not last node, new list end */
+      n->prev->next = NULL;
+    }
+  }
+  else
+  {
+    /* node must be in the middle */
+    n->prev->next = n->next;
+    n->next->prev = n->prev;
+  }
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("free list objid==%"S32_F"\n",n->objid));
+  snmp_mib_ln_free(n);
+  if (rn->count == 0)
+  {
+    rn->head = NULL;
+    rn->tail = NULL;
+  }
+  return next;
+}
+
+
+
+/**
+ * Searches tree for the supplied (scalar?) object identifier.
+ *
+ * @param node points to the root of the tree ('.internet')
+ * @param ident_len the length of the supplied object identifier
+ * @param ident points to the array of sub identifiers
+ * @param np points to the found object instance (rerurn)
+ * @return pointer to the requested parent (!) node if success, NULL otherwise
+ */
+struct mib_node *
+snmp_search_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_name_ptr *np)
+{
+  u8_t node_type, ext_level;
+
+  ext_level = 0;
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("node==%p *ident==%"S32_F"\n",(void*)node,*ident));
+  while (node != NULL)
+  {
+    node_type = node->node_type;
+    if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA))
+    {
+      struct mib_array_node *an;
+      u16_t i;
+
+      if (ident_len > 0)
+      {
+        /* array node (internal ROM or RAM, fixed length) */
+        an = (struct mib_array_node *)node;
+        i = 0;
+        while ((i < an->maxlength) && (an->objid[i] != *ident))
+        {
+          i++;
+        }
+        if (i < an->maxlength)
+        {
+          /* found it, if available proceed to child, otherwise inspect leaf */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("an->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,an->objid[i],*ident));
+          if (an->nptr[i] == NULL)
+          {
+            /* a scalar leaf OR table,
+               inspect remaining instance number / table index */
+            np->ident_len = ident_len;
+            np->ident = ident;
+            return (struct mib_node*)an;
+          }
+          else
+          {
+            /* follow next child pointer */
+            ident++;
+            ident_len--;
+            node = an->nptr[i];
+          }
+        }
+        else
+        {
+          /* search failed, identifier mismatch (nosuchname) */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("an search failed *ident==%"S32_F"\n",*ident));
+          return NULL;
+        }
+      }
+      else
+      {
+        /* search failed, short object identifier (nosuchname) */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("an search failed, short object identifier\n"));
+        return NULL;
+      }
+    }
+    else if(node_type == MIB_NODE_LR)
+    {
+      struct mib_list_rootnode *lrn;
+      struct mib_list_node *ln;
+
+      if (ident_len > 0)
+      {
+        /* list root node (internal 'RAM', variable length) */
+        lrn = (struct mib_list_rootnode *)node;
+        ln = lrn->head;
+        /* iterate over list, head to tail */
+        while ((ln != NULL) && (ln->objid != *ident))
+        {
+          ln = ln->next;
+        }
+        if (ln != NULL)
+        {
+          /* found it, proceed to child */;
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln->objid==%"S32_F" *ident==%"S32_F"\n",ln->objid,*ident));
+          if (ln->nptr == NULL)
+          {
+            np->ident_len = ident_len;
+            np->ident = ident;
+            return (struct mib_node*)lrn;
+          }
+          else
+          {
+            /* follow next child pointer */
+            ident_len--;
+            ident++;
+            node = ln->nptr;
+          }
+        }
+        else
+        {
+          /* search failed */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln search failed *ident==%"S32_F"\n",*ident));
+          return NULL;
+        }
+      }
+      else
+      {
+        /* search failed, short object identifier (nosuchname) */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln search failed, short object identifier\n"));
+        return NULL;
+      }
+    }
+    else if(node_type == MIB_NODE_EX)
+    {
+      struct mib_external_node *en;
+      u16_t i, len;
+
+      if (ident_len > 0)
+      {
+        /* external node (addressing and access via functions) */
+        en = (struct mib_external_node *)node;
+
+        i = 0;
+        len = en->level_length(en->addr_inf,ext_level);
+        while ((i < len) && (en->ident_cmp(en->addr_inf,ext_level,i,*ident) != 0))
+        {
+          i++;
+        }
+        if (i < len)
+        {
+          s32_t debug_id;
+
+          en->get_objid(en->addr_inf,ext_level,i,&debug_id);
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("en->objid==%"S32_F" *ident==%"S32_F"\n",debug_id,*ident));
+          if ((ext_level + 1) == en->tree_levels)
+          {
+            np->ident_len = ident_len;
+            np->ident = ident;
+            return (struct mib_node*)en;
+          }
+          else
+          {
+            /* found it, proceed to child */
+            ident_len--;
+            ident++;
+            ext_level++;
+          }
+        }
+        else
+        {
+          /* search failed */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("en search failed *ident==%"S32_F"\n",*ident));
+          return NULL;
+        }
+      }
+      else
+      {
+        /* search failed, short object identifier (nosuchname) */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("en search failed, short object identifier\n"));
+        return NULL;
+      }
+    }
+    else if (node_type == MIB_NODE_SC)
+    {
+      mib_scalar_node *sn;
+
+      sn = (mib_scalar_node *)node;
+      if ((ident_len == 1) && (*ident == 0))
+      {
+        np->ident_len = ident_len;
+        np->ident = ident;
+        return (struct mib_node*)sn;
+      }
+      else
+      {
+        /* search failed, short object identifier (nosuchname) */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed, invalid object identifier length\n"));
+        return NULL;
+      }
+    }
+    else
+    {
+      /* unknown node_type */
+      LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed node_type %"U16_F" unkown\n",(u16_t)node_type));
+      return NULL;
+    }
+  }
+  /* done, found nothing */
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed node==%p\n",(void*)node));
+  return NULL;
+}
+
+/**
+ * Test table for presence of at least one table entry.
+ */
+static u8_t
+empty_table(struct mib_node *node)
+{
+  u8_t node_type;
+  u8_t empty = 0;
+
+  if (node != NULL)
+  {
+    node_type = node->node_type;
+    if (node_type == MIB_NODE_LR)
+    {
+      struct mib_list_rootnode *lrn;
+      lrn = (struct mib_list_rootnode *)node;
+      if ((lrn->count == 0) || (lrn->head == NULL))
+      {
+        empty = 1;
+      }
+    }
+    else if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA))
+    {
+      struct mib_array_node *an;
+      an = (struct mib_array_node *)node;
+      if ((an->maxlength == 0) || (an->nptr == NULL))
+      {
+        empty = 1;
+      }
+    }
+    else if (node_type == MIB_NODE_EX)
+    {
+      struct mib_external_node *en;
+      en = (struct mib_external_node *)node;
+      if (en->tree_levels == 0)
+      {
+        empty = 1;
+      }
+    }
+  }
+  return empty;
+}
+
+/**
+ * Tree expansion.
+ */
+struct mib_node *
+snmp_expand_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret)
+{
+  u8_t node_type, ext_level, climb_tree;
+
+  ext_level = 0;
+  /* reset node stack */
+  node_stack_cnt = 0;
+  while (node != NULL)
+  {
+    climb_tree = 0;
+    node_type = node->node_type;
+    if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA))
+    {
+      struct mib_array_node *an;
+      u16_t i;
+
+      /* array node (internal ROM or RAM, fixed length) */
+      an = (struct mib_array_node *)node;
+      if (ident_len > 0)
+      {
+        i = 0;
+        while ((i < an->maxlength) && (an->objid[i] < *ident))
+        {
+          i++;
+        }
+        if (i < an->maxlength)
+        {
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("an->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,an->objid[i],*ident));
+          /* add identifier to oidret */
+          oidret->id[oidret->len] = an->objid[i];
+          (oidret->len)++;
+
+          if (an->nptr[i] == NULL)
+          {
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("leaf node\n"));
+            /* leaf node (e.g. in a fixed size table) */
+            if (an->objid[i] > *ident)
+            {
+              return (struct mib_node*)an;
+            }
+            else if ((i + 1) < an->maxlength)
+            {
+              /* an->objid[i] == *ident */
+              (oidret->len)--;
+              oidret->id[oidret->len] = an->objid[i + 1];
+              (oidret->len)++;
+              return (struct mib_node*)an;
+            }
+            else
+            {
+              /* (i + 1) == an->maxlength */
+              (oidret->len)--;
+              climb_tree = 1;
+            }
+          }
+          else
+          {
+            u8_t j;
+            struct nse cur_node;
+
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("non-leaf node\n"));
+            /* non-leaf, store right child ptr and id */
+            j = i + 1;
+            while ((j < an->maxlength) && (empty_table(an->nptr[j])))
+            {
+              j++;
+            }
+            if (j < an->maxlength)
+            {
+              cur_node.r_ptr = an->nptr[j];
+              cur_node.r_id = an->objid[j];
+              cur_node.r_nl = 0;
+            }
+            else
+            {
+              cur_node.r_ptr = NULL;
+            }
+            push_node(&cur_node);
+            if (an->objid[i] == *ident)
+            {
+              ident_len--;
+              ident++;
+            }
+            else
+            {
+              /* an->objid[i] < *ident */
+              ident_len = 0;
+            }
+            /* follow next child pointer */
+            node = an->nptr[i];
+          }
+        }
+        else
+        {
+          /* i == an->maxlength */
+          climb_tree = 1;
+        }
+      }
+      else
+      {
+        u8_t j;
+        /* ident_len == 0, complete with leftmost '.thing' */
+        j = 0;
+        while ((j < an->maxlength) && empty_table(an->nptr[j]))
+        {
+          j++;
+        }
+        if (j < an->maxlength)
+        {
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("left an->objid[j]==%"S32_F"\n",an->objid[j]));
+          oidret->id[oidret->len] = an->objid[j];
+          (oidret->len)++;
+          if (an->nptr[j] == NULL)
+          {
+            /* leaf node */
+            return (struct mib_node*)an;
+          }
+          else
+          {
+            /* no leaf, continue */
+            node = an->nptr[j];
+          }
+        }
+        else
+        {
+          /* j == an->maxlength */
+          climb_tree = 1;
+        }
+      }
+    }
+    else if(node_type == MIB_NODE_LR)
+    {
+      struct mib_list_rootnode *lrn;
+      struct mib_list_node *ln;
+
+      /* list root node (internal 'RAM', variable length) */
+      lrn = (struct mib_list_rootnode *)node;
+      if (ident_len > 0)
+      {
+        ln = lrn->head;
+        /* iterate over list, head to tail */
+        while ((ln != NULL) && (ln->objid < *ident))
+        {
+          ln = ln->next;
+        }
+        if (ln != NULL)
+        {
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln->objid==%"S32_F" *ident==%"S32_F"\n",ln->objid,*ident));
+          oidret->id[oidret->len] = ln->objid;
+          (oidret->len)++;
+          if (ln->nptr == NULL)
+          {
+            /* leaf node */
+            if (ln->objid > *ident)
+            {
+              return (struct mib_node*)lrn;
+            }
+            else if (ln->next != NULL)
+            {
+              /* ln->objid == *ident */
+              (oidret->len)--;
+              oidret->id[oidret->len] = ln->next->objid;
+              (oidret->len)++;
+              return (struct mib_node*)lrn;
+            }
+            else
+            {
+              /* ln->next == NULL */
+              (oidret->len)--;
+              climb_tree = 1;
+            }
+          }
+          else
+          {
+            struct mib_list_node *jn;
+            struct nse cur_node;
+
+            /* non-leaf, store right child ptr and id */
+            jn = ln->next;
+            while ((jn != NULL) && empty_table(jn->nptr))
+            {
+              jn = jn->next;
+            }
+            if (jn != NULL)
+            {
+              cur_node.r_ptr = jn->nptr;
+              cur_node.r_id = jn->objid;
+              cur_node.r_nl = 0;
+            }
+            else
+            {
+              cur_node.r_ptr = NULL;
+            }
+            push_node(&cur_node);
+            if (ln->objid == *ident)
+            {
+              ident_len--;
+              ident++;
+            }
+            else
+            {
+              /* ln->objid < *ident */
+              ident_len = 0;
+            }
+            /* follow next child pointer */
+            node = ln->nptr;
+          }
+
+        }
+        else
+        {
+          /* ln == NULL */
+          climb_tree = 1;
+        }
+      }
+      else
+      {
+        struct mib_list_node *jn;
+        /* ident_len == 0, complete with leftmost '.thing' */
+        jn = lrn->head;
+        while ((jn != NULL) && empty_table(jn->nptr))
+        {
+          jn = jn->next;
+        }
+        if (jn != NULL)
+        {
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("left jn->objid==%"S32_F"\n",jn->objid));
+          oidret->id[oidret->len] = jn->objid;
+          (oidret->len)++;
+          if (jn->nptr == NULL)
+          {
+            /* leaf node */
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("jn->nptr == NULL\n"));
+            return (struct mib_node*)lrn;
+          }
+          else
+          {
+            /* no leaf, continue */
+            node = jn->nptr;
+          }
+        }
+        else
+        {
+          /* jn == NULL */
+          climb_tree = 1;
+        }
+      }
+    }
+    else if(node_type == MIB_NODE_EX)
+    {
+      struct mib_external_node *en;
+      s32_t ex_id;
+
+      /* external node (addressing and access via functions) */
+      en = (struct mib_external_node *)node;
+      if (ident_len > 0)
+      {
+        u16_t i, len;
+
+        i = 0;
+        len = en->level_length(en->addr_inf,ext_level);
+        while ((i < len) && (en->ident_cmp(en->addr_inf,ext_level,i,*ident) < 0))
+        {
+          i++;
+        }
+        if (i < len)
+        {
+          /* add identifier to oidret */
+          en->get_objid(en->addr_inf,ext_level,i,&ex_id);
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("en->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,ex_id,*ident));
+          oidret->id[oidret->len] = ex_id;
+          (oidret->len)++;
+
+          if ((ext_level + 1) == en->tree_levels)
+          {
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("leaf node\n"));
+            /* leaf node */
+            if (ex_id > *ident)
+            {
+              return (struct mib_node*)en;
+            }
+            else if ((i + 1) < len)
+            {
+              /* ex_id == *ident */
+              en->get_objid(en->addr_inf,ext_level,i + 1,&ex_id);
+              (oidret->len)--;
+              oidret->id[oidret->len] = ex_id;
+              (oidret->len)++;
+              return (struct mib_node*)en;
+            }
+            else
+            {
+              /* (i + 1) == len */
+              (oidret->len)--;
+              climb_tree = 1;
+            }
+          }
+          else
+          {
+            u8_t j;
+            struct nse cur_node;
+
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("non-leaf node\n"));
+            /* non-leaf, store right child ptr and id */
+            j = i + 1;
+            if (j < len)
+            {
+              /* right node is the current external node */
+              cur_node.r_ptr = node;
+              en->get_objid(en->addr_inf,ext_level,j,&cur_node.r_id);
+              cur_node.r_nl = ext_level + 1;
+            }
+            else
+            {
+              cur_node.r_ptr = NULL;
+            }
+            push_node(&cur_node);
+            if (en->ident_cmp(en->addr_inf,ext_level,i,*ident) == 0)
+            {
+              ident_len--;
+              ident++;
+            }
+            else
+            {
+              /* external id < *ident */
+              ident_len = 0;
+            }
+            /* proceed to child */
+            ext_level++;
+          }
+        }
+        else
+        {
+          /* i == len (en->level_len()) */
+          climb_tree = 1;
+        }
+      }
+      else
+      {
+        /* ident_len == 0, complete with leftmost '.thing' */
+        en->get_objid(en->addr_inf,ext_level,0,&ex_id);
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("left en->objid==%"S32_F"\n",ex_id));
+        oidret->id[oidret->len] = ex_id;
+        (oidret->len)++;
+        if ((ext_level + 1) == en->tree_levels)
+        {
+          /* leaf node */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("(ext_level + 1) == en->tree_levels\n"));
+          return (struct mib_node*)en;
+        }
+        else
+        {
+          /* no leaf, proceed to child */
+          ext_level++;
+        }
+      }
+    }
+    else if(node_type == MIB_NODE_SC)
+    {
+      mib_scalar_node *sn;
+
+      /* scalar node  */
+      sn = (mib_scalar_node *)node;
+      if (ident_len > 0)
+      {
+        /* at .0 */
+        climb_tree = 1;
+      }
+      else
+      {
+        /* ident_len == 0, complete object identifier */
+        oidret->id[oidret->len] = 0;
+        (oidret->len)++;
+        /* leaf node */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("completed scalar leaf\n"));
+        return (struct mib_node*)sn;
+      }
+    }
+    else
+    {
+      /* unknown/unhandled node_type */
+      LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed node_type %"U16_F" unkown\n",(u16_t)node_type));
+      return NULL;
+    }
+
+    if (climb_tree)
+    {
+      struct nse child;
+
+      /* find right child ptr */
+      child.r_ptr = NULL;
+      child.r_id = 0;
+      child.r_nl = 0;
+      while ((node_stack_cnt > 0) && (child.r_ptr == NULL))
+      {
+        pop_node(&child);
+        /* trim returned oid */
+        (oidret->len)--;
+      }
+      if (child.r_ptr != NULL)
+      {
+        /* incoming ident is useless beyond this point */
+        ident_len = 0;
+        oidret->id[oidret->len] = child.r_id;
+        oidret->len++;
+        node = child.r_ptr;
+        ext_level = child.r_nl;
+      }
+      else
+      {
+        /* tree ends here ... */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed, tree ends here\n"));
+        return NULL;
+      }
+    }
+  }
+  /* done, found nothing */
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed node==%p\n",(void*)node));
+  return NULL;
+}
+
+/**
+ * Test object identifier for the iso.org.dod.internet prefix.
+ *
+ * @param ident_len the length of the supplied object identifier
+ * @param ident points to the array of sub identifiers
+ * @return 1 if it matches, 0 otherwise
+ */
+u8_t
+snmp_iso_prefix_tst(u8_t ident_len, s32_t *ident)
+{
+  if ((ident_len > 3) &&
+      (ident[0] == 1) && (ident[1] == 3) &&
+      (ident[2] == 6) && (ident[3] == 1))
+  {
+    return 1;
+  }
+  else
+  {
+    return 0;
+  }
+}
+
+/**
+ * Expands object identifier to the iso.org.dod.internet
+ * prefix for use in getnext operation.
+ *
+ * @param ident_len the length of the supplied object identifier
+ * @param ident points to the array of sub identifiers
+ * @param oidret points to returned expanded object identifier
+ * @return 1 if it matches, 0 otherwise
+ *
+ * @note ident_len 0 is allowed, expanding to the first known object id!!
+ */
+u8_t
+snmp_iso_prefix_expand(u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret)
+{
+  const s32_t *prefix_ptr;
+  s32_t *ret_ptr;
+  u8_t i;
+
+  i = 0;
+  prefix_ptr = &prefix[0];
+  ret_ptr = &oidret->id[0];
+  ident_len = ((ident_len < 4)?ident_len:4);
+  while ((i < ident_len) && ((*ident) <= (*prefix_ptr)))
+  {
+    *ret_ptr++ = *prefix_ptr++;
+    ident++;
+    i++;
+  }
+  if (i == ident_len)
+  {
+    /* match, complete missing bits */
+    while (i < 4)
+    {
+      *ret_ptr++ = *prefix_ptr++;
+      i++;
+    }
+    oidret->len = i;
+    return 1;
+  }
+  else
+  {
+    /* i != ident_len */
+    return 0;
+  }
+}
+
+#endif /* LWIP_SNMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/snmp/msg_in.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/snmp/msg_in.c
new file mode 100644
index 0000000..4f62bc9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/snmp/msg_in.c
@@ -0,0 +1,1453 @@
+/**
+ * @file
+ * SNMP input message processing (RFC1157).
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/ip_addr.h"
+#include "lwip/mem.h"
+#include "lwip/udp.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+#include "lwip/snmp_asn1.h"
+#include "lwip/snmp_msg.h"
+#include "lwip/snmp_structs.h"
+
+#include 
+
+/* public (non-static) constants */
+/** SNMP v1 == 0 */
+const s32_t snmp_version = 0;
+/** default SNMP community string */
+const char snmp_publiccommunity[7] = "public";
+
+/* statically allocated buffers for SNMP_CONCURRENT_REQUESTS */
+struct snmp_msg_pstat msg_input_list[SNMP_CONCURRENT_REQUESTS];
+/* UDP Protocol Control Block */
+struct udp_pcb *snmp1_pcb;
+
+static void snmp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port);
+static err_t snmp_pdu_header_check(struct pbuf *p, u16_t ofs, u16_t pdu_len, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat);
+static err_t snmp_pdu_dec_varbindlist(struct pbuf *p, u16_t ofs, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat);
+
+
+/**
+ * Starts SNMP Agent.
+ * Allocates UDP pcb and binds it to IP_ADDR_ANY port 161.
+ */
+void
+snmp_init(void)
+{
+  struct snmp_msg_pstat *msg_ps;
+  u8_t i;
+
+  snmp1_pcb = udp_new();
+  if (snmp1_pcb != NULL)
+  {
+    udp_recv(snmp1_pcb, snmp_recv, (void *)SNMP_IN_PORT);
+    udp_bind(snmp1_pcb, IP_ADDR_ANY, SNMP_IN_PORT);
+  }
+  msg_ps = &msg_input_list[0];
+  for (i=0; istate = SNMP_MSG_EMPTY;
+    msg_ps->error_index = 0;
+    msg_ps->error_status = SNMP_ES_NOERROR;
+    msg_ps++;
+  }
+  trap_msg.pcb = snmp1_pcb;
+  /* The coldstart trap will only be output
+     if our outgoing interface is up & configured  */
+  snmp_coldstart_trap();
+}
+
+static void
+snmp_error_response(struct snmp_msg_pstat *msg_ps, u8_t error)
+{
+  snmp_varbind_list_free(&msg_ps->outvb);
+  msg_ps->outvb = msg_ps->invb;
+  msg_ps->invb.head = NULL;
+  msg_ps->invb.tail = NULL;
+  msg_ps->invb.count = 0;
+  msg_ps->error_status = error;
+  msg_ps->error_index = 1 + msg_ps->vb_idx;
+  snmp_send_response(msg_ps);
+  snmp_varbind_list_free(&msg_ps->outvb);
+  msg_ps->state = SNMP_MSG_EMPTY;
+}
+
+static void
+snmp_ok_response(struct snmp_msg_pstat *msg_ps)
+{
+  err_t err_ret;
+
+  err_ret = snmp_send_response(msg_ps);
+  if (err_ret == ERR_MEM)
+  {
+    /* serious memory problem, can't return tooBig */
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event = %"S32_F"\n",msg_ps->error_status));
+  }
+  /* free varbinds (if available) */
+  snmp_varbind_list_free(&msg_ps->invb);
+  snmp_varbind_list_free(&msg_ps->outvb);
+  msg_ps->state = SNMP_MSG_EMPTY;
+}
+
+/**
+ * Service an internal or external event for SNMP GET.
+ *
+ * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1)
+ * @param msg_ps points to the assosicated message process state
+ */
+static void
+snmp_msg_get_event(u8_t request_id, struct snmp_msg_pstat *msg_ps)
+{
+  LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_get_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state));
+
+  if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF)
+  {
+    struct mib_external_node *en;
+    struct snmp_name_ptr np;
+
+    /* get_object_def() answer*/
+    en = msg_ps->ext_mib_node;
+    np = msg_ps->ext_name_ptr;
+
+    /* translate answer into a known lifeform */
+    en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def);
+    if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE)
+    {
+      msg_ps->state = SNMP_MSG_EXTERNAL_GET_VALUE;
+      en->get_value_q(request_id, &msg_ps->ext_object_def);
+    }
+    else
+    {
+      en->get_object_def_pc(request_id, np.ident_len, np.ident);
+      /* search failed, object id points to unknown object (nosuchname) */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_VALUE)
+  {
+    struct mib_external_node *en;
+    struct snmp_varbind *vb;
+
+    /* get_value() answer */
+    en = msg_ps->ext_mib_node;
+
+    /* allocate output varbind */
+    vb = (struct snmp_varbind *)mem_malloc(sizeof(struct snmp_varbind));
+    LWIP_ASSERT("vb != NULL",vb != NULL);
+    if (vb != NULL)
+    {
+      vb->next = NULL;
+      vb->prev = NULL;
+
+      /* move name from invb to outvb */
+      vb->ident = msg_ps->vb_ptr->ident;
+      vb->ident_len = msg_ps->vb_ptr->ident_len;
+      /* ensure this memory is refereced once only */
+      msg_ps->vb_ptr->ident = NULL;
+      msg_ps->vb_ptr->ident_len = 0;
+
+      vb->value_type = msg_ps->ext_object_def.asn_type;
+      vb->value_len =  msg_ps->ext_object_def.v_len;
+      if (vb->value_len > 0)
+      {
+        vb->value = mem_malloc(vb->value_len);
+        LWIP_ASSERT("vb->value != NULL",vb->value != NULL);
+        if (vb->value != NULL)
+        {
+          en->get_value_a(request_id, &msg_ps->ext_object_def, vb->value_len, vb->value);
+          snmp_varbind_tail_add(&msg_ps->outvb, vb);
+          /* search again (if vb_idx < msg_ps->invb.count) */
+          msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+          msg_ps->vb_idx += 1;
+        }
+        else
+        {
+          en->get_value_pc(request_id, &msg_ps->ext_object_def);
+          LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: no variable space\n"));
+          msg_ps->vb_ptr->ident = vb->ident;
+          msg_ps->vb_ptr->ident_len = vb->ident_len;
+          mem_free(vb);
+          snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+        }
+      }
+      else
+      {
+        /* vb->value_len == 0, empty value (e.g. empty string) */
+        en->get_value_a(request_id, &msg_ps->ext_object_def, 0, NULL);
+        vb->value = NULL;
+        snmp_varbind_tail_add(&msg_ps->outvb, vb);
+        /* search again (if vb_idx < msg_ps->invb.count) */
+        msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+        msg_ps->vb_idx += 1;
+      }
+    }
+    else
+    {
+      en->get_value_pc(request_id, &msg_ps->ext_object_def);
+      LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: no outvb space\n"));
+      snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+    }
+  }
+
+  while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+         (msg_ps->vb_idx < msg_ps->invb.count))
+  {
+    struct mib_node *mn;
+    struct snmp_name_ptr np;
+
+    if (msg_ps->vb_idx == 0)
+    {
+      msg_ps->vb_ptr = msg_ps->invb.head;
+    }
+    else
+    {
+      msg_ps->vb_ptr = msg_ps->vb_ptr->next;
+    }
+    /** test object identifier for .iso.org.dod.internet prefix */
+    if (snmp_iso_prefix_tst(msg_ps->vb_ptr->ident_len,  msg_ps->vb_ptr->ident))
+    {
+      mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4,
+                             msg_ps->vb_ptr->ident + 4, &np);
+      if (mn != NULL)
+      {
+        if (mn->node_type == MIB_NODE_EX)
+        {
+          /* external object */
+          struct mib_external_node *en = (struct mib_external_node*)mn;
+
+          msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF;
+          /* save en && args in msg_ps!! */
+          msg_ps->ext_mib_node = en;
+          msg_ps->ext_name_ptr = np;
+
+          en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident);
+        }
+        else
+        {
+          /* internal object */
+          struct obj_def object_def;
+
+          msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF;
+          mn->get_object_def(np.ident_len, np.ident, &object_def);
+          if (object_def.instance != MIB_OBJECT_NONE)
+          {
+            mn = mn;
+          }
+          else
+          {
+            /* search failed, object id points to unknown object (nosuchname) */
+            mn =  NULL;
+          }
+          if (mn != NULL)
+          {
+            struct snmp_varbind *vb;
+
+            msg_ps->state = SNMP_MSG_INTERNAL_GET_VALUE;
+            /* allocate output varbind */
+            vb = (struct snmp_varbind *)mem_malloc(sizeof(struct snmp_varbind));
+            LWIP_ASSERT("vb != NULL",vb != NULL);
+            if (vb != NULL)
+            {
+              vb->next = NULL;
+              vb->prev = NULL;
+
+              /* move name from invb to outvb */
+              vb->ident = msg_ps->vb_ptr->ident;
+              vb->ident_len = msg_ps->vb_ptr->ident_len;
+              /* ensure this memory is refereced once only */
+              msg_ps->vb_ptr->ident = NULL;
+              msg_ps->vb_ptr->ident_len = 0;
+
+              vb->value_type = object_def.asn_type;
+              vb->value_len = object_def.v_len;
+              if (vb->value_len > 0)
+              {
+                vb->value = mem_malloc(vb->value_len);
+                LWIP_ASSERT("vb->value != NULL",vb->value != NULL);
+                if (vb->value != NULL)
+                {
+                  mn->get_value(&object_def, vb->value_len, vb->value);
+                  snmp_varbind_tail_add(&msg_ps->outvb, vb);
+                  msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+                  msg_ps->vb_idx += 1;
+                }
+                else
+                {
+                  LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: couldn't allocate variable space\n"));
+                  msg_ps->vb_ptr->ident = vb->ident;
+                  msg_ps->vb_ptr->ident_len = vb->ident_len;
+                  mem_free(vb);
+                  snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+                }
+              }
+              else
+              {
+                /* vb->value_len == 0, empty value (e.g. empty string) */
+                vb->value = NULL;
+                snmp_varbind_tail_add(&msg_ps->outvb, vb);
+                msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+                msg_ps->vb_idx += 1;
+              }
+            }
+            else
+            {
+              LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: couldn't allocate outvb space\n"));
+              snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+            }
+          }
+        }
+      }
+    }
+    else
+    {
+      mn = NULL;
+    }
+    if (mn == NULL)
+    {
+      /* mn == NULL, noSuchName */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+      (msg_ps->vb_idx == msg_ps->invb.count))
+  {
+    snmp_ok_response(msg_ps);
+  }
+}
+
+/**
+ * Service an internal or external event for SNMP GETNEXT.
+ *
+ * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1)
+ * @param msg_ps points to the assosicated message process state
+ */
+static void
+snmp_msg_getnext_event(u8_t request_id, struct snmp_msg_pstat *msg_ps)
+{
+  LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_getnext_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state));
+
+  if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF)
+  {
+    struct mib_external_node *en;
+
+    /* get_object_def() answer*/
+    en = msg_ps->ext_mib_node;
+
+    /* translate answer into a known lifeform */
+    en->get_object_def_a(request_id, 1, &msg_ps->ext_oid.id[msg_ps->ext_oid.len - 1], &msg_ps->ext_object_def);
+    if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE)
+    {
+      msg_ps->state = SNMP_MSG_EXTERNAL_GET_VALUE;
+      en->get_value_q(request_id, &msg_ps->ext_object_def);
+    }
+    else
+    {
+      en->get_object_def_pc(request_id, 1, &msg_ps->ext_oid.id[msg_ps->ext_oid.len - 1]);
+      /* search failed, object id points to unknown object (nosuchname) */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_VALUE)
+  {
+    struct mib_external_node *en;
+    struct snmp_varbind *vb;
+
+    /* get_value() answer */
+    en = msg_ps->ext_mib_node;
+
+    vb = snmp_varbind_alloc(&msg_ps->ext_oid,
+                            msg_ps->ext_object_def.asn_type,
+                            msg_ps->ext_object_def.v_len);
+    if (vb != NULL)
+    {
+      en->get_value_a(request_id, &msg_ps->ext_object_def, vb->value_len, vb->value);
+      snmp_varbind_tail_add(&msg_ps->outvb, vb);
+      msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+      msg_ps->vb_idx += 1;
+    }
+    else
+    {
+      en->get_value_pc(request_id, &msg_ps->ext_object_def);
+      LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_getnext_event: couldn't allocate outvb space\n"));
+      snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+    }
+  }
+
+  while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+         (msg_ps->vb_idx < msg_ps->invb.count))
+  {
+    struct mib_node *mn;
+    struct snmp_obj_id oid;
+
+    if (msg_ps->vb_idx == 0)
+    {
+      msg_ps->vb_ptr = msg_ps->invb.head;
+    }
+    else
+    {
+      msg_ps->vb_ptr = msg_ps->vb_ptr->next;
+    }
+    if (snmp_iso_prefix_expand(msg_ps->vb_ptr->ident_len, msg_ps->vb_ptr->ident, &oid))
+    {
+      if (msg_ps->vb_ptr->ident_len > 3)
+      {
+        /* can offset ident_len and ident */
+        mn = snmp_expand_tree((struct mib_node*)&internet,
+                              msg_ps->vb_ptr->ident_len - 4,
+                              msg_ps->vb_ptr->ident + 4, &oid);
+      }
+      else
+      {
+        /* can't offset ident_len -4, ident + 4 */
+        mn = snmp_expand_tree((struct mib_node*)&internet, 0, NULL, &oid);
+      }
+    }
+    else
+    {
+      mn = NULL;
+    }
+    if (mn != NULL)
+    {
+      if (mn->node_type == MIB_NODE_EX)
+      {
+        /* external object */
+        struct mib_external_node *en = (struct mib_external_node*)mn;
+
+        msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF;
+        /* save en && args in msg_ps!! */
+        msg_ps->ext_mib_node = en;
+        msg_ps->ext_oid = oid;
+
+        en->get_object_def_q(en->addr_inf, request_id, 1, &oid.id[oid.len - 1]);
+      }
+      else
+      {
+        /* internal object */
+        struct obj_def object_def;
+        struct snmp_varbind *vb;
+
+        msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF;
+        mn->get_object_def(1, &oid.id[oid.len - 1], &object_def);
+
+        vb = snmp_varbind_alloc(&oid, object_def.asn_type, object_def.v_len);
+        if (vb != NULL)
+        {
+          msg_ps->state = SNMP_MSG_INTERNAL_GET_VALUE;
+          mn->get_value(&object_def, object_def.v_len, vb->value);
+          snmp_varbind_tail_add(&msg_ps->outvb, vb);
+          msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+          msg_ps->vb_idx += 1;
+        }
+        else
+        {
+          LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv couldn't allocate outvb space\n"));
+          snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+        }
+      }
+    }
+    if (mn == NULL)
+    {
+      /* mn == NULL, noSuchName */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+      (msg_ps->vb_idx == msg_ps->invb.count))
+  {
+    snmp_ok_response(msg_ps);
+  }
+}
+
+/**
+ * Service an internal or external event for SNMP SET.
+ *
+ * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1)
+ * @param msg_ps points to the assosicated message process state
+ */
+static void
+snmp_msg_set_event(u8_t request_id, struct snmp_msg_pstat *msg_ps)
+{
+  LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_set_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state));
+
+  if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF)
+  {
+    struct mib_external_node *en;
+    struct snmp_name_ptr np;
+
+    /* get_object_def() answer*/
+    en = msg_ps->ext_mib_node;
+    np = msg_ps->ext_name_ptr;
+
+    /* translate answer into a known lifeform */
+    en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def);
+    if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE)
+    {
+      msg_ps->state = SNMP_MSG_EXTERNAL_SET_TEST;
+      en->set_test_q(request_id, &msg_ps->ext_object_def);
+    }
+    else
+    {
+      en->get_object_def_pc(request_id, np.ident_len, np.ident);
+      /* search failed, object id points to unknown object (nosuchname) */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  else if (msg_ps->state == SNMP_MSG_EXTERNAL_SET_TEST)
+  {
+    struct mib_external_node *en;
+
+    /* set_test() answer*/
+    en = msg_ps->ext_mib_node;
+
+    if (msg_ps->ext_object_def.access == MIB_OBJECT_READ_WRITE)
+    {
+       if ((msg_ps->ext_object_def.asn_type == msg_ps->vb_ptr->value_type) &&
+           (en->set_test_a(request_id,&msg_ps->ext_object_def,
+                           msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value) != 0))
+      {
+        msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+        msg_ps->vb_idx += 1;
+      }
+      else
+      {
+        en->set_test_pc(request_id,&msg_ps->ext_object_def);
+        /* bad value */
+        snmp_error_response(msg_ps,SNMP_ES_BADVALUE);
+      }
+    }
+    else
+    {
+      en->set_test_pc(request_id,&msg_ps->ext_object_def);
+      /* object not available for set */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF_S)
+  {
+    struct mib_external_node *en;
+    struct snmp_name_ptr np;
+
+    /* get_object_def() answer*/
+    en = msg_ps->ext_mib_node;
+    np = msg_ps->ext_name_ptr;
+
+    /* translate answer into a known lifeform */
+    en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def);
+    if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE)
+    {
+      msg_ps->state = SNMP_MSG_EXTERNAL_SET_VALUE;
+      en->set_value_q(request_id, &msg_ps->ext_object_def,
+                      msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value);
+    }
+    else
+    {
+      en->get_object_def_pc(request_id, np.ident_len, np.ident);
+      /* set_value failed, object has disappeared for some odd reason?? */
+      snmp_error_response(msg_ps,SNMP_ES_GENERROR);
+    }
+  }
+  else if (msg_ps->state == SNMP_MSG_EXTERNAL_SET_VALUE)
+  {
+    struct mib_external_node *en;
+
+    /** set_value_a() @todo: use reply value?? */
+    en = msg_ps->ext_mib_node;
+    en->set_value_a(request_id, &msg_ps->ext_object_def, 0, NULL);
+
+    /** @todo use set_value_pc() if toobig */
+    msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE;
+    msg_ps->vb_idx += 1;
+  }
+
+  /* test all values before setting */
+  while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+         (msg_ps->vb_idx < msg_ps->invb.count))
+  {
+    struct mib_node *mn;
+    struct snmp_name_ptr np;
+
+    if (msg_ps->vb_idx == 0)
+    {
+      msg_ps->vb_ptr = msg_ps->invb.head;
+    }
+    else
+    {
+      msg_ps->vb_ptr = msg_ps->vb_ptr->next;
+    }
+    /** test object identifier for .iso.org.dod.internet prefix */
+    if (snmp_iso_prefix_tst(msg_ps->vb_ptr->ident_len,  msg_ps->vb_ptr->ident))
+    {
+      mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4,
+                             msg_ps->vb_ptr->ident + 4, &np);
+      if (mn != NULL)
+      {
+        if (mn->node_type == MIB_NODE_EX)
+        {
+          /* external object */
+          struct mib_external_node *en = (struct mib_external_node*)mn;
+
+          msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF;
+          /* save en && args in msg_ps!! */
+          msg_ps->ext_mib_node = en;
+          msg_ps->ext_name_ptr = np;
+
+          en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident);
+        }
+        else
+        {
+          /* internal object */
+          struct obj_def object_def;
+
+          msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF;
+          mn->get_object_def(np.ident_len, np.ident, &object_def);
+          if (object_def.instance != MIB_OBJECT_NONE)
+          {
+            mn = mn;
+          }
+          else
+          {
+            /* search failed, object id points to unknown object (nosuchname) */
+            mn = NULL;
+          }
+          if (mn != NULL)
+          {
+            msg_ps->state = SNMP_MSG_INTERNAL_SET_TEST;
+
+            if (object_def.access == MIB_OBJECT_READ_WRITE)
+            {
+              if ((object_def.asn_type == msg_ps->vb_ptr->value_type) &&
+                  (mn->set_test(&object_def,msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value) != 0))
+              {
+                msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+                msg_ps->vb_idx += 1;
+              }
+              else
+              {
+                /* bad value */
+                snmp_error_response(msg_ps,SNMP_ES_BADVALUE);
+              }
+            }
+            else
+            {
+              /* object not available for set */
+              snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+            }
+          }
+        }
+      }
+    }
+    else
+    {
+      mn = NULL;
+    }
+    if (mn == NULL)
+    {
+      /* mn == NULL, noSuchName */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+
+  if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+      (msg_ps->vb_idx == msg_ps->invb.count))
+  {
+    msg_ps->vb_idx = 0;
+    msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE;
+  }
+
+  /* set all values "atomically" (be as "atomic" as possible) */
+  while ((msg_ps->state == SNMP_MSG_INTERNAL_SET_VALUE) &&
+         (msg_ps->vb_idx < msg_ps->invb.count))
+  {
+    struct mib_node *mn;
+    struct snmp_name_ptr np;
+
+    if (msg_ps->vb_idx == 0)
+    {
+      msg_ps->vb_ptr = msg_ps->invb.head;
+    }
+    else
+    {
+      msg_ps->vb_ptr = msg_ps->vb_ptr->next;
+    }
+    /* skip iso prefix test, was done previously while settesting() */
+    mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4,
+                           msg_ps->vb_ptr->ident + 4, &np);
+    /* check if object is still available
+       (e.g. external hot-plug thingy present?) */
+    if (mn != NULL)
+    {
+      if (mn->node_type == MIB_NODE_EX)
+      {
+        /* external object */
+        struct mib_external_node *en = (struct mib_external_node*)mn;
+
+        msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF_S;
+        /* save en && args in msg_ps!! */
+        msg_ps->ext_mib_node = en;
+        msg_ps->ext_name_ptr = np;
+
+        en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident);
+      }
+      else
+      {
+        /* internal object */
+        struct obj_def object_def;
+
+        msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF_S;
+        mn->get_object_def(np.ident_len, np.ident, &object_def);
+        msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE;
+        mn->set_value(&object_def,msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value);
+        msg_ps->vb_idx += 1;
+      }
+    }
+  }
+  if ((msg_ps->state == SNMP_MSG_INTERNAL_SET_VALUE) &&
+      (msg_ps->vb_idx == msg_ps->invb.count))
+  {
+    /* simply echo the input if we can set it
+       @todo do we need to return the actual value?
+       e.g. if value is silently modified or behaves sticky? */
+    msg_ps->outvb = msg_ps->invb;
+    msg_ps->invb.head = NULL;
+    msg_ps->invb.tail = NULL;
+    msg_ps->invb.count = 0;
+    snmp_ok_response(msg_ps);
+  }
+}
+
+
+/**
+ * Handle one internal or external event.
+ * Called for one async event. (recv external/private answer)
+ *
+ * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1)
+ */
+void
+snmp_msg_event(u8_t request_id)
+{
+  struct snmp_msg_pstat *msg_ps;
+
+  if (request_id < SNMP_CONCURRENT_REQUESTS)
+  {
+    msg_ps = &msg_input_list[request_id];
+    if (msg_ps->rt == SNMP_ASN1_PDU_GET_NEXT_REQ)
+    {
+      snmp_msg_getnext_event(request_id, msg_ps);
+    }
+    else if (msg_ps->rt == SNMP_ASN1_PDU_GET_REQ)
+    {
+      snmp_msg_get_event(request_id, msg_ps);
+    }
+    else if(msg_ps->rt == SNMP_ASN1_PDU_SET_REQ)
+    {
+      snmp_msg_set_event(request_id, msg_ps);
+    }
+  }
+}
+
+
+/* lwIP UDP receive callback function */
+static void
+snmp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port)
+{
+  struct udp_hdr *udphdr;
+
+  /* suppress unused argument warning */
+  LWIP_UNUSED_ARG(arg);
+  /* peek in the UDP header (goto IP payload) */
+  if(pbuf_header(p, UDP_HLEN)){
+    LWIP_ASSERT("Can't move to UDP header", 0);
+    pbuf_free(p);
+    return;
+  }
+  udphdr = p->payload;
+
+  /* check if datagram is really directed at us (including broadcast requests) */
+  if ((pcb == snmp1_pcb) && (ntohs(udphdr->dest) == SNMP_IN_PORT))
+  {
+    struct snmp_msg_pstat *msg_ps;
+    u8_t req_idx;
+
+    /* traverse input message process list, look for SNMP_MSG_EMPTY */
+    msg_ps = &msg_input_list[0];
+    req_idx = 0;
+    while ((req_idxstate != SNMP_MSG_EMPTY))
+    {
+      req_idx++;
+      msg_ps++;
+    }
+    if (req_idx != SNMP_CONCURRENT_REQUESTS)
+    {
+      err_t err_ret;
+      u16_t payload_len;
+      u16_t payload_ofs;
+      u16_t varbind_ofs = 0;
+
+      /* accepting request */
+      snmp_inc_snmpinpkts();
+      /* record used 'protocol control block' */
+      msg_ps->pcb = pcb;
+      /* source address (network order) */
+      msg_ps->sip = *addr;
+      /* source port (host order (lwIP oddity)) */
+      msg_ps->sp = port;
+      /* read UDP payload length from UDP header */
+      payload_len = ntohs(udphdr->len) - UDP_HLEN;
+
+      /* adjust to UDP payload */
+      payload_ofs = UDP_HLEN;
+
+      /* check total length, version, community, pdu type */
+      err_ret = snmp_pdu_header_check(p, payload_ofs, payload_len, &varbind_ofs, msg_ps);
+      if (((msg_ps->rt == SNMP_ASN1_PDU_GET_REQ) ||
+           (msg_ps->rt == SNMP_ASN1_PDU_GET_NEXT_REQ) ||
+           (msg_ps->rt == SNMP_ASN1_PDU_SET_REQ)) &&
+          ((msg_ps->error_status == SNMP_ES_NOERROR) &&
+           (msg_ps->error_index == 0)) )
+      {
+        /* Only accept requests and requests without error (be robust) */
+        err_ret = err_ret;
+      }
+      else
+      {
+        /* Reject response and trap headers or error requests as input! */
+        err_ret = ERR_ARG;
+      }
+      if (err_ret == ERR_OK)
+      {
+        LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv ok, community %s\n", msg_ps->community));
+
+        /* Builds a list of variable bindings. Copy the varbinds from the pbuf
+          chain to glue them when these are divided over two or more pbuf's. */
+        err_ret = snmp_pdu_dec_varbindlist(p, varbind_ofs, &varbind_ofs, msg_ps);
+        if ((err_ret == ERR_OK) && (msg_ps->invb.count > 0))
+        {
+          /* we've decoded the incoming message, release input msg now */
+          pbuf_free(p);
+
+          msg_ps->error_status = SNMP_ES_NOERROR;
+          msg_ps->error_index = 0;
+          /* find object for each variable binding */
+          msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+          /* first variable binding from list to inspect */
+          msg_ps->vb_idx = 0;
+
+          LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv varbind cnt=%"U16_F"\n",(u16_t)msg_ps->invb.count));
+
+          /* handle input event and as much objects as possible in one go */
+          snmp_msg_event(req_idx);
+        }
+        else
+        {
+          /* varbind-list decode failed, or varbind list empty.
+             drop request silently, do not return error!
+             (errors are only returned for a specific varbind failure) */
+          pbuf_free(p);
+          LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_pdu_dec_varbindlist() failed\n"));
+        }
+      }
+      else
+      {
+        /* header check failed
+           drop request silently, do not return error! */
+        pbuf_free(p);
+        LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_pdu_header_check() failed\n"));
+      }
+    }
+    else
+    {
+      /* exceeding number of concurrent requests */
+      pbuf_free(p);
+    }
+  }
+  else
+  {
+    /* datagram not for us */
+    pbuf_free(p);
+  }
+}
+
+/**
+ * Checks and decodes incoming SNMP message header, logs header errors.
+ *
+ * @param p points to pbuf chain of SNMP message (UDP payload)
+ * @param ofs points to first octet of SNMP message
+ * @param pdu_len the length of the UDP payload
+ * @param ofs_ret returns the ofset of the variable bindings
+ * @param m_stat points to the current message request state return
+ * @return
+ * - ERR_OK SNMP header is sane and accepted
+ * - ERR_ARG SNMP header is either malformed or rejected
+ */
+static err_t
+snmp_pdu_header_check(struct pbuf *p, u16_t ofs, u16_t pdu_len, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat)
+{
+  err_t derr;
+  u16_t len, ofs_base;
+  u8_t  len_octets;
+  u8_t  type;
+  s32_t version;
+
+  ofs_base = ofs;
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) ||
+      (pdu_len != (1 + len_octets + len)) ||
+      (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)))
+  {
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets);
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)))
+  {
+    /* can't decode or no integer (version) */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &version);
+  if (derr != ERR_OK)
+  {
+    /* can't decode */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  if (version != 0)
+  {
+    /* not version 1 */
+    snmp_inc_snmpinbadversions();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets + len);
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR)))
+  {
+    /* can't decode or no octet string (community) */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, SNMP_COMMUNITY_STR_LEN, m_stat->community);
+  if (derr != ERR_OK)
+  {
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  /* add zero terminator */
+  len = ((len < (SNMP_COMMUNITY_STR_LEN))?(len):(SNMP_COMMUNITY_STR_LEN));
+  m_stat->community[len] = 0;
+  m_stat->com_strlen = len;
+  if (strncmp(snmp_publiccommunity, (const char*)m_stat->community, SNMP_COMMUNITY_STR_LEN) != 0)
+  {
+    /** @todo: move this if we need to check more names */
+    snmp_inc_snmpinbadcommunitynames();
+    snmp_authfail_trap();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets + len);
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if (derr != ERR_OK)
+  {
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  switch(type)
+  {
+    case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_REQ):
+      /* GetRequest PDU */
+      snmp_inc_snmpingetrequests();
+      derr = ERR_OK;
+      break;
+    case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_NEXT_REQ):
+      /* GetNextRequest PDU */
+      snmp_inc_snmpingetnexts();
+      derr = ERR_OK;
+      break;
+    case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_RESP):
+      /* GetResponse PDU */
+      snmp_inc_snmpingetresponses();
+      derr = ERR_ARG;
+      break;
+    case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_SET_REQ):
+      /* SetRequest PDU */
+      snmp_inc_snmpinsetrequests();
+      derr = ERR_OK;
+      break;
+    case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_TRAP):
+      /* Trap PDU */
+      snmp_inc_snmpintraps();
+      derr = ERR_ARG;
+      break;
+    default:
+      snmp_inc_snmpinasnparseerrs();
+      derr = ERR_ARG;
+      break;
+  }
+  if (derr != ERR_OK)
+  {
+    /* unsupported input PDU for this agent (no parse error) */
+    return ERR_ARG;
+  }
+  m_stat->rt = type & 0x1F;
+  ofs += (1 + len_octets);
+  if (len != (pdu_len - (ofs - ofs_base)))
+  {
+    /* decoded PDU length does not equal actual payload length */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)))
+  {
+    /* can't decode or no integer (request ID) */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->rid);
+  if (derr != ERR_OK)
+  {
+    /* can't decode */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets + len);
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)))
+  {
+    /* can't decode or no integer (error-status) */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  /* must be noError (0) for incoming requests.
+     log errors for mib-2 completeness and for debug purposes */
+  derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->error_status);
+  if (derr != ERR_OK)
+  {
+    /* can't decode */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  switch (m_stat->error_status)
+  {
+    case SNMP_ES_TOOBIG:
+      snmp_inc_snmpintoobigs();
+      break;
+    case SNMP_ES_NOSUCHNAME:
+      snmp_inc_snmpinnosuchnames();
+      break;
+    case SNMP_ES_BADVALUE:
+      snmp_inc_snmpinbadvalues();
+      break;
+    case SNMP_ES_READONLY:
+      snmp_inc_snmpinreadonlys();
+      break;
+    case SNMP_ES_GENERROR:
+      snmp_inc_snmpingenerrs();
+      break;
+  }
+  ofs += (1 + len_octets + len);
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)))
+  {
+    /* can't decode or no integer (error-index) */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  /* must be 0 for incoming requests.
+     decode anyway to catch bad integers (and dirty tricks) */
+  derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->error_index);
+  if (derr != ERR_OK)
+  {
+    /* can't decode */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets + len);
+  *ofs_ret = ofs;
+  return ERR_OK;
+}
+
+static err_t
+snmp_pdu_dec_varbindlist(struct pbuf *p, u16_t ofs, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat)
+{
+  err_t derr;
+  u16_t len, vb_len;
+  u8_t  len_octets;
+  u8_t type;
+
+  /* variable binding list */
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &vb_len);
+  if ((derr != ERR_OK) ||
+      (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)))
+  {
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets);
+
+  /* start with empty list */
+  m_stat->invb.count = 0;
+  m_stat->invb.head = NULL;
+  m_stat->invb.tail = NULL;
+
+  while (vb_len > 0)
+  {
+    struct snmp_obj_id oid, oid_value;
+    struct snmp_varbind *vb;
+
+    snmp_asn1_dec_type(p, ofs, &type);
+    derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+    if ((derr != ERR_OK) ||
+        (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)) ||
+        (len <= 0) || (len > vb_len))
+    {
+      snmp_inc_snmpinasnparseerrs();
+      /* free varbinds (if available) */
+      snmp_varbind_list_free(&m_stat->invb);
+      return ERR_ARG;
+    }
+    ofs += (1 + len_octets);
+    vb_len -= (1 + len_octets);
+
+    snmp_asn1_dec_type(p, ofs, &type);
+    derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+    if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID)))
+    {
+      /* can't decode object name length */
+      snmp_inc_snmpinasnparseerrs();
+      /* free varbinds (if available) */
+      snmp_varbind_list_free(&m_stat->invb);
+      return ERR_ARG;
+    }
+    derr = snmp_asn1_dec_oid(p, ofs + 1 + len_octets, len, &oid);
+    if (derr != ERR_OK)
+    {
+      /* can't decode object name */
+      snmp_inc_snmpinasnparseerrs();
+      /* free varbinds (if available) */
+      snmp_varbind_list_free(&m_stat->invb);
+      return ERR_ARG;
+    }
+    ofs += (1 + len_octets + len);
+    vb_len -= (1 + len_octets + len);
+
+    snmp_asn1_dec_type(p, ofs, &type);
+    derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+    if (derr != ERR_OK)
+    {
+      /* can't decode object value length */
+      snmp_inc_snmpinasnparseerrs();
+      /* free varbinds (if available) */
+      snmp_varbind_list_free(&m_stat->invb);
+      return ERR_ARG;
+    }
+
+    switch (type)
+    {
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG):
+        vb = snmp_varbind_alloc(&oid, type, sizeof(s32_t));
+        if (vb != NULL)
+        {
+          s32_t *vptr = vb->value;
+
+          derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, vptr);
+          snmp_varbind_tail_add(&m_stat->invb, vb);
+        }
+        else
+        {
+          derr = ERR_ARG;
+        }
+        break;
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS):
+        vb = snmp_varbind_alloc(&oid, type, sizeof(u32_t));
+        if (vb != NULL)
+        {
+          u32_t *vptr = vb->value;
+
+          derr = snmp_asn1_dec_u32t(p, ofs + 1 + len_octets, len, vptr);
+          snmp_varbind_tail_add(&m_stat->invb, vb);
+        }
+        else
+        {
+          derr = ERR_ARG;
+        }
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE):
+        vb = snmp_varbind_alloc(&oid, type, len);
+        if (vb != NULL)
+        {
+          derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, vb->value_len, vb->value);
+          snmp_varbind_tail_add(&m_stat->invb, vb);
+        }
+        else
+        {
+          derr = ERR_ARG;
+        }
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL):
+        vb = snmp_varbind_alloc(&oid, type, 0);
+        if (vb != NULL)
+        {
+          snmp_varbind_tail_add(&m_stat->invb, vb);
+          derr = ERR_OK;
+        }
+        else
+        {
+          derr = ERR_ARG;
+        }
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID):
+        derr = snmp_asn1_dec_oid(p, ofs + 1 + len_octets, len, &oid_value);
+        if (derr == ERR_OK)
+        {
+          vb = snmp_varbind_alloc(&oid, type, oid_value.len * sizeof(s32_t));
+          if (vb != NULL)
+          {
+            u8_t i = oid_value.len;
+            s32_t *vptr = vb->value;
+
+            while(i > 0)
+            {
+              i--;
+              vptr[i] = oid_value.id[i];
+            }
+            snmp_varbind_tail_add(&m_stat->invb, vb);
+            derr = ERR_OK;
+          }
+          else
+          {
+            derr = ERR_ARG;
+          }
+        }
+        break;
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR):
+        if (len == 4)
+        {
+          /* must be exactly 4 octets! */
+          vb = snmp_varbind_alloc(&oid, type, 4);
+          if (vb != NULL)
+          {
+            derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, vb->value_len, vb->value);
+            snmp_varbind_tail_add(&m_stat->invb, vb);
+          }
+          else
+          {
+            derr = ERR_ARG;
+          }
+        }
+        else
+        {
+          derr = ERR_ARG;
+        }
+        break;
+      default:
+        derr = ERR_ARG;
+        break;
+    }
+    if (derr != ERR_OK)
+    {
+      snmp_inc_snmpinasnparseerrs();
+      /* free varbinds (if available) */
+      snmp_varbind_list_free(&m_stat->invb);
+      return ERR_ARG;
+    }
+    ofs += (1 + len_octets + len);
+    vb_len -= (1 + len_octets + len);
+  }
+
+  if (m_stat->rt == SNMP_ASN1_PDU_SET_REQ)
+  {
+    snmp_add_snmpintotalsetvars(m_stat->invb.count);
+  }
+  else
+  {
+    snmp_add_snmpintotalreqvars(m_stat->invb.count);
+  }
+
+  *ofs_ret = ofs;
+  return ERR_OK;
+}
+
+struct snmp_varbind*
+snmp_varbind_alloc(struct snmp_obj_id *oid, u8_t type, u8_t len)
+{
+  struct snmp_varbind *vb;
+
+  vb = (struct snmp_varbind *)mem_malloc(sizeof(struct snmp_varbind));
+  LWIP_ASSERT("vb != NULL",vb != NULL);
+  if (vb != NULL)
+  {
+    u8_t i;
+
+    vb->next = NULL;
+    vb->prev = NULL;
+    i = oid->len;
+    vb->ident_len = i;
+    if (i > 0)
+    {
+      /* allocate array of s32_t for our object identifier */
+      vb->ident = (s32_t*)mem_malloc(sizeof(s32_t) * i);
+      LWIP_ASSERT("vb->ident != NULL",vb->ident != NULL);
+      if (vb->ident == NULL)
+      {
+        mem_free(vb);
+        return NULL;
+      }
+      while(i > 0)
+      {
+        i--;
+        vb->ident[i] = oid->id[i];
+      }
+    }
+    else
+    {
+      /* i == 0, pass zero length object identifier */
+      vb->ident = NULL;
+    }
+    vb->value_type = type;
+    vb->value_len = len;
+    if (len > 0)
+    {
+      /* allocate raw bytes for our object value */
+      vb->value = mem_malloc(len);
+      LWIP_ASSERT("vb->value != NULL",vb->value != NULL);
+      if (vb->value == NULL)
+      {
+        if (vb->ident != NULL)
+        {
+          mem_free(vb->ident);
+        }
+        mem_free(vb);
+        return NULL;
+      }
+    }
+    else
+    {
+      /* ASN1_NUL type, or zero length ASN1_OC_STR */
+      vb->value = NULL;
+    }
+  }
+  return vb;
+}
+
+void
+snmp_varbind_free(struct snmp_varbind *vb)
+{
+  if (vb->value != NULL )
+  {
+    mem_free(vb->value);
+  }
+  if (vb->ident != NULL )
+  {
+    mem_free(vb->ident);
+  }
+  mem_free(vb);
+}
+
+void
+snmp_varbind_list_free(struct snmp_varbind_root *root)
+{
+  struct snmp_varbind *vb, *prev;
+
+  vb = root->tail;
+  while ( vb != NULL )
+  {
+    prev = vb->prev;
+    snmp_varbind_free(vb);
+    vb = prev;
+  }
+  root->count = 0;
+  root->head = NULL;
+  root->tail = NULL;
+}
+
+void
+snmp_varbind_tail_add(struct snmp_varbind_root *root, struct snmp_varbind *vb)
+{
+  if (root->count == 0)
+  {
+    /* add first varbind to list */
+    root->head = vb;
+    root->tail = vb;
+  }
+  else
+  {
+    /* add nth varbind to list tail */
+    root->tail->next = vb;
+    vb->prev = root->tail;
+    root->tail = vb;
+  }
+  root->count += 1;
+}
+
+struct snmp_varbind*
+snmp_varbind_tail_remove(struct snmp_varbind_root *root)
+{
+  struct snmp_varbind* vb;
+
+  if (root->count > 0)
+  {
+    /* remove tail varbind */
+    vb = root->tail;
+    root->tail = vb->prev;
+    vb->prev->next = NULL;
+    root->count -= 1;
+  }
+  else
+  {
+    /* nothing to remove */
+    vb = NULL;
+  }
+  return vb;
+}
+
+#endif /* LWIP_SNMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/snmp/msg_out.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/snmp/msg_out.c
new file mode 100644
index 0000000..242d309
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/snmp/msg_out.c
@@ -0,0 +1,683 @@
+/**
+ * @file
+ * SNMP output message processing (RFC1157).
+ *
+ * Output responses and traps are build in two passes:
+ *
+ * Pass 0: iterate over the output message backwards to determine encoding lengths
+ * Pass 1: the actual forward encoding of internal form into ASN1
+ *
+ * The single-pass encoding method described by Comer & Stevens
+ * requires extra buffer space and copying for reversal of the packet.
+ * The buffer requirement can be prohibitively large for big payloads
+ * (>= 484) therefore we use the two encoding passes.
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/udp.h"
+#include "lwip/netif.h"
+#include "lwip/snmp.h"
+#include "lwip/snmp_asn1.h"
+#include "lwip/snmp_msg.h"
+
+struct snmp_trap_dst
+{
+  /* destination IP address in network order */
+  struct ip_addr dip;
+  /* set to 0 when disabled, >0 when enabled */
+  u8_t enable;
+};
+struct snmp_trap_dst trap_dst[SNMP_TRAP_DESTINATIONS];
+
+/** TRAP message structure */
+struct snmp_msg_trap trap_msg;
+
+static u16_t snmp_resp_header_sum(struct snmp_msg_pstat *m_stat, u16_t vb_len);
+static u16_t snmp_trap_header_sum(struct snmp_msg_trap *m_trap, u16_t vb_len);
+static u16_t snmp_varbind_list_sum(struct snmp_varbind_root *root);
+
+static u16_t snmp_resp_header_enc(struct snmp_msg_pstat *m_stat, struct pbuf *p);
+static u16_t snmp_trap_header_enc(struct snmp_msg_trap *m_trap, struct pbuf *p);
+static u16_t snmp_varbind_list_enc(struct snmp_varbind_root *root, struct pbuf *p, u16_t ofs);
+
+/**
+ * Sets enable switch for this trap destination.
+ * @param dst_idx index in 0 .. SNMP_TRAP_DESTINATIONS-1
+ * @param enable switch if 0 destination is disabled >0 enabled.
+ */
+void
+snmp_trap_dst_enable(u8_t dst_idx, u8_t enable)
+{
+  if (dst_idx < SNMP_TRAP_DESTINATIONS)
+  {
+    trap_dst[dst_idx].enable = enable;
+  }
+}
+
+/**
+ * Sets IPv4 address for this trap destination.
+ * @param dst_idx index in 0 .. SNMP_TRAP_DESTINATIONS-1
+ * @param dst IPv4 address in host order.
+ */
+void
+snmp_trap_dst_ip_set(u8_t dst_idx, struct ip_addr *dst)
+{
+  if (dst_idx < SNMP_TRAP_DESTINATIONS)
+  {
+    trap_dst[dst_idx].dip.addr = htonl(dst->addr);
+  }
+}
+
+/**
+ * Sends a 'getresponse' message to the request originator.
+ *
+ * @param m_stat points to the current message request state source
+ * @return ERR_OK when success, ERR_MEM if we're out of memory
+ *
+ * @note the caller is responsible for filling in outvb in the m_stat
+ * and provide error-status and index (except for tooBig errors) ...
+ */
+err_t
+snmp_send_response(struct snmp_msg_pstat *m_stat)
+{
+  struct snmp_varbind_root emptyvb = {NULL, NULL, 0, 0, 0};
+  struct pbuf *p;
+  u16_t tot_len;
+  err_t err;
+
+  /* pass 0, calculate length fields */
+  tot_len = snmp_varbind_list_sum(&m_stat->outvb);
+  tot_len = snmp_resp_header_sum(m_stat, tot_len);
+
+  /* try allocating pbuf(s) for complete response */
+  p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL);
+  if (p == NULL)
+  {
+    LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() tooBig\n"));
+
+    /* can't construct reply, return error-status tooBig */
+    m_stat->error_status = SNMP_ES_TOOBIG;
+    m_stat->error_index = 0;
+    /* pass 0, recalculate lengths, for empty varbind-list */
+    tot_len = snmp_varbind_list_sum(&emptyvb);
+    tot_len = snmp_resp_header_sum(m_stat, tot_len);
+    /* retry allocation once for header and empty varbind-list */
+    p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL);
+  }
+  if (p != NULL)
+  {
+    /* first pbuf alloc try or retry alloc success */
+    u16_t ofs;
+
+    LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() p != NULL\n"));
+
+    /* pass 1, size error, encode packet ino the pbuf(s) */
+    ofs = snmp_resp_header_enc(m_stat, p);
+    if (m_stat->error_status == SNMP_ES_TOOBIG)
+    {
+      snmp_varbind_list_enc(&emptyvb, p, ofs);
+    }
+    else
+    {
+      snmp_varbind_list_enc(&m_stat->outvb, p, ofs);
+    }
+
+    switch (m_stat->error_status)
+    {
+      case SNMP_ES_TOOBIG:
+        snmp_inc_snmpouttoobigs();
+        break;
+      case SNMP_ES_NOSUCHNAME:
+        snmp_inc_snmpoutnosuchnames();
+        break;
+      case SNMP_ES_BADVALUE:
+        snmp_inc_snmpoutbadvalues();
+        break;
+      case SNMP_ES_GENERROR:
+        snmp_inc_snmpoutgenerrs();
+        break;
+    }
+    snmp_inc_snmpoutgetresponses();
+    snmp_inc_snmpoutpkts();
+
+    /** @todo do we need separate rx and tx pcbs for threaded case? */
+    /** connect to the originating source */
+    udp_connect(m_stat->pcb, &m_stat->sip, m_stat->sp);
+    err = udp_send(m_stat->pcb, p);
+    if (err == ERR_MEM)
+    {
+      /** @todo release some memory, retry and return tooBig? tooMuchHassle? */
+      err = ERR_MEM;
+    }
+    else
+    {
+      err = ERR_OK;
+    }
+    /** disassociate remote address and port with this pcb */
+    udp_disconnect(m_stat->pcb);
+
+    pbuf_free(p);
+    LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() done\n"));
+    return err;
+  }
+  else
+  {
+    /* first pbuf alloc try or retry alloc failed
+       very low on memory, couldn't return tooBig */
+    return ERR_MEM;
+  }
+}
+
+
+/**
+ * Sends an generic or enterprise specific trap message.
+ *
+ * @param generic_trap is the trap code
+ * @param eoid points to enterprise object identifier
+ * @param specific_trap used for enterprise traps when generic_trap == 6
+ * @return ERR_OK when success, ERR_MEM if we're out of memory
+ *
+ * @note the caller is responsible for filling in outvb in the trap_msg
+ * @note the use of the enterpise identifier field
+ * is per RFC1215.
+ * Use .iso.org.dod.internet.mgmt.mib-2.snmp for generic traps
+ * and .iso.org.dod.internet.private.enterprises.yourenterprise
+ * (sysObjectID) for specific traps.
+ */
+err_t
+snmp_send_trap(s8_t generic_trap, struct snmp_obj_id *eoid, s32_t specific_trap)
+{
+  struct snmp_trap_dst *td;
+  struct netif *dst_if;
+  struct ip_addr dst_ip;
+  struct pbuf *p;
+  u16_t i,tot_len;
+
+  for (i=0, td = &trap_dst[0]; ienable != 0) && (td->dip.addr != 0))
+    {
+      /* network order trap destination */
+      trap_msg.dip.addr = td->dip.addr;
+      /* lookup current source address for this dst */
+      dst_if = ip_route(&td->dip);
+      dst_ip.addr = ntohl(dst_if->ip_addr.addr);
+      trap_msg.sip_raw[0] = dst_ip.addr >> 24;
+      trap_msg.sip_raw[1] = dst_ip.addr >> 16;
+      trap_msg.sip_raw[2] = dst_ip.addr >> 8;
+      trap_msg.sip_raw[3] = dst_ip.addr;
+      trap_msg.gen_trap = generic_trap;
+      trap_msg.spc_trap = specific_trap;
+      if (generic_trap == SNMP_GENTRAP_ENTERPRISESPC)
+      {
+        /* enterprise-Specific trap */
+        trap_msg.enterprise = eoid;
+      }
+      else
+      {
+        /* generic (MIB-II) trap */
+        snmp_get_snmpgrpid_ptr(&trap_msg.enterprise);
+      }
+      snmp_get_sysuptime(&trap_msg.ts);
+
+      /* pass 0, calculate length fields */
+      tot_len = snmp_varbind_list_sum(&trap_msg.outvb);
+      tot_len = snmp_trap_header_sum(&trap_msg, tot_len);
+
+      /* allocate pbuf(s) */
+      p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL);
+      if (p != NULL)
+      {
+        u16_t ofs;
+
+        /* pass 1, encode packet ino the pbuf(s) */
+        ofs = snmp_trap_header_enc(&trap_msg, p);
+        snmp_varbind_list_enc(&trap_msg.outvb, p, ofs);
+
+        snmp_inc_snmpouttraps();
+        snmp_inc_snmpoutpkts();
+
+        /** connect to the TRAP destination */
+        udp_connect(trap_msg.pcb, &trap_msg.dip, SNMP_TRAP_PORT);
+        udp_send(trap_msg.pcb, p);
+        /** disassociate remote address and port with this pcb */
+        udp_disconnect(trap_msg.pcb);
+
+        pbuf_free(p);
+      }
+      else
+      {
+        return ERR_MEM;
+      }
+    }
+  }
+  return ERR_OK;
+}
+
+void
+snmp_coldstart_trap(void)
+{
+  trap_msg.outvb.head = NULL;
+  trap_msg.outvb.tail = NULL;
+  trap_msg.outvb.count = 0;
+  snmp_send_trap(SNMP_GENTRAP_COLDSTART, NULL, 0);
+}
+
+void
+snmp_authfail_trap(void)
+{
+  u8_t enable;
+  snmp_get_snmpenableauthentraps(&enable);
+  if (enable == 1)
+  {
+    trap_msg.outvb.head = NULL;
+    trap_msg.outvb.tail = NULL;
+    trap_msg.outvb.count = 0;
+    snmp_send_trap(SNMP_GENTRAP_AUTHFAIL, NULL, 0);
+  }
+}
+
+/**
+ * Sums response header field lengths from tail to head and
+ * returns resp_header_lengths for second encoding pass.
+ *
+ * @param vb_len varbind-list length
+ * @param rhl points to returned header lengths
+ * @return the required lenght for encoding the response header
+ */
+static u16_t
+snmp_resp_header_sum(struct snmp_msg_pstat *m_stat, u16_t vb_len)
+{
+  u16_t tot_len;
+  struct snmp_resp_header_lengths *rhl;
+
+  rhl = &m_stat->rhl;
+  tot_len = vb_len;
+  snmp_asn1_enc_s32t_cnt(m_stat->error_index, &rhl->erridxlen);
+  snmp_asn1_enc_length_cnt(rhl->erridxlen, &rhl->erridxlenlen);
+  tot_len += 1 + rhl->erridxlenlen + rhl->erridxlen;
+
+  snmp_asn1_enc_s32t_cnt(m_stat->error_status, &rhl->errstatlen);
+  snmp_asn1_enc_length_cnt(rhl->errstatlen, &rhl->errstatlenlen);
+  tot_len += 1 + rhl->errstatlenlen + rhl->errstatlen;
+
+  snmp_asn1_enc_s32t_cnt(m_stat->rid, &rhl->ridlen);
+  snmp_asn1_enc_length_cnt(rhl->ridlen, &rhl->ridlenlen);
+  tot_len += 1 + rhl->ridlenlen + rhl->ridlen;
+
+  rhl->pdulen = tot_len;
+  snmp_asn1_enc_length_cnt(rhl->pdulen, &rhl->pdulenlen);
+  tot_len += 1 + rhl->pdulenlen;
+
+  rhl->comlen = m_stat->com_strlen;
+  snmp_asn1_enc_length_cnt(rhl->comlen, &rhl->comlenlen);
+  tot_len += 1 + rhl->comlenlen + rhl->comlen;
+
+  snmp_asn1_enc_s32t_cnt(snmp_version, &rhl->verlen);
+  snmp_asn1_enc_length_cnt(rhl->verlen, &rhl->verlenlen);
+  tot_len += 1 + rhl->verlen + rhl->verlenlen;
+
+  rhl->seqlen = tot_len;
+  snmp_asn1_enc_length_cnt(rhl->seqlen, &rhl->seqlenlen);
+  tot_len += 1 + rhl->seqlenlen;
+
+  return tot_len;
+}
+
+/**
+ * Sums trap header field lengths from tail to head and
+ * returns trap_header_lengths for second encoding pass.
+ *
+ * @param vb_len varbind-list length
+ * @param thl points to returned header lengths
+ * @return the required lenght for encoding the trap header
+ */
+static u16_t
+snmp_trap_header_sum(struct snmp_msg_trap *m_trap, u16_t vb_len)
+{
+  u16_t tot_len;
+  struct snmp_trap_header_lengths *thl;
+
+  thl = &m_trap->thl;
+  tot_len = vb_len;
+
+  snmp_asn1_enc_u32t_cnt(m_trap->ts, &thl->tslen);
+  snmp_asn1_enc_length_cnt(thl->tslen, &thl->tslenlen);
+  tot_len += 1 + thl->tslen + thl->tslenlen;
+
+  snmp_asn1_enc_s32t_cnt(m_trap->spc_trap, &thl->strplen);
+  snmp_asn1_enc_length_cnt(thl->strplen, &thl->strplenlen);
+  tot_len += 1 + thl->strplen + thl->strplenlen;
+
+  snmp_asn1_enc_s32t_cnt(m_trap->gen_trap, &thl->gtrplen);
+  snmp_asn1_enc_length_cnt(thl->gtrplen, &thl->gtrplenlen);
+  tot_len += 1 + thl->gtrplen + thl->gtrplenlen;
+
+  thl->aaddrlen = 4;
+  snmp_asn1_enc_length_cnt(thl->aaddrlen, &thl->aaddrlenlen);
+  tot_len += 1 + thl->aaddrlen + thl->aaddrlenlen;
+
+  snmp_asn1_enc_oid_cnt(m_trap->enterprise->len, &m_trap->enterprise->id[0], &thl->eidlen);
+  snmp_asn1_enc_length_cnt(thl->eidlen, &thl->eidlenlen);
+  tot_len += 1 + thl->eidlen + thl->eidlenlen;
+
+  thl->pdulen = tot_len;
+  snmp_asn1_enc_length_cnt(thl->pdulen, &thl->pdulenlen);
+  tot_len += 1 + thl->pdulenlen;
+
+  thl->comlen = sizeof(snmp_publiccommunity) - 1;
+  snmp_asn1_enc_length_cnt(thl->comlen, &thl->comlenlen);
+  tot_len += 1 + thl->comlenlen + thl->comlen;
+
+  snmp_asn1_enc_s32t_cnt(snmp_version, &thl->verlen);
+  snmp_asn1_enc_length_cnt(thl->verlen, &thl->verlenlen);
+  tot_len += 1 + thl->verlen + thl->verlenlen;
+
+  thl->seqlen = tot_len;
+  snmp_asn1_enc_length_cnt(thl->seqlen, &thl->seqlenlen);
+  tot_len += 1 + thl->seqlenlen;
+
+  return tot_len;
+}
+
+/**
+ * Sums varbind lengths from tail to head and
+ * annotates lengths in varbind for second encoding pass.
+ *
+ * @param root points to the root of the variable binding list
+ * @return the required lenght for encoding the variable bindings
+ */
+static u16_t
+snmp_varbind_list_sum(struct snmp_varbind_root *root)
+{
+  struct snmp_varbind *vb;
+  u32_t *uint_ptr;
+  s32_t *sint_ptr;
+  u16_t tot_len;
+
+  tot_len = 0;
+  vb = root->tail;
+  while ( vb != NULL )
+  {
+    /* encoded value lenght depends on type */
+    switch (vb->value_type)
+    {
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG):
+        sint_ptr = vb->value;
+        snmp_asn1_enc_s32t_cnt(*sint_ptr, &vb->vlen);
+        break;
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS):
+        uint_ptr = vb->value;
+        snmp_asn1_enc_u32t_cnt(*uint_ptr, &vb->vlen);
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR):
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE):
+        vb->vlen = vb->value_len;
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID):
+        sint_ptr = vb->value;
+        snmp_asn1_enc_oid_cnt(vb->value_len / sizeof(s32_t), sint_ptr, &vb->vlen);
+        break;
+      default:
+        /* unsupported type */
+        vb->vlen = 0;
+        break;
+    };
+    /* encoding length of value length field */
+    snmp_asn1_enc_length_cnt(vb->vlen, &vb->vlenlen);
+    snmp_asn1_enc_oid_cnt(vb->ident_len, vb->ident, &vb->olen);
+    snmp_asn1_enc_length_cnt(vb->olen, &vb->olenlen);
+
+    vb->seqlen = 1 + vb->vlenlen + vb->vlen;
+    vb->seqlen += 1 + vb->olenlen + vb->olen;
+    snmp_asn1_enc_length_cnt(vb->seqlen, &vb->seqlenlen);
+
+    /* varbind seq */
+    tot_len += 1 + vb->seqlenlen + vb->seqlen;
+
+    vb = vb->prev;
+  }
+
+  /* varbind-list seq */
+  root->seqlen = tot_len;
+  snmp_asn1_enc_length_cnt(root->seqlen, &root->seqlenlen);
+  tot_len += 1 + root->seqlenlen;
+
+  return tot_len;
+}
+
+/**
+ * Encodes response header from head to tail.
+ */
+static u16_t
+snmp_resp_header_enc(struct snmp_msg_pstat *m_stat, struct pbuf *p)
+{
+  u16_t ofs;
+
+  ofs = 0;
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.seqlen);
+  ofs += m_stat->rhl.seqlenlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.verlen);
+  ofs += m_stat->rhl.verlenlen;
+  snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.verlen, snmp_version);
+  ofs += m_stat->rhl.verlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.comlen);
+  ofs += m_stat->rhl.comlenlen;
+  snmp_asn1_enc_raw(p, ofs, m_stat->rhl.comlen, m_stat->community);
+  ofs += m_stat->rhl.comlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_RESP));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.pdulen);
+  ofs += m_stat->rhl.pdulenlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.ridlen);
+  ofs += m_stat->rhl.ridlenlen;
+  snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.ridlen, m_stat->rid);
+  ofs += m_stat->rhl.ridlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.errstatlen);
+  ofs += m_stat->rhl.errstatlenlen;
+  snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.errstatlen, m_stat->error_status);
+  ofs += m_stat->rhl.errstatlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.erridxlen);
+  ofs += m_stat->rhl.erridxlenlen;
+  snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.erridxlen, m_stat->error_index);
+  ofs += m_stat->rhl.erridxlen;
+
+  return ofs;
+}
+
+/**
+ * Encodes trap header from head to tail.
+ */
+static u16_t
+snmp_trap_header_enc(struct snmp_msg_trap *m_trap, struct pbuf *p)
+{
+  u16_t ofs;
+
+  ofs = 0;
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.seqlen);
+  ofs += m_trap->thl.seqlenlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.verlen);
+  ofs += m_trap->thl.verlenlen;
+  snmp_asn1_enc_s32t(p, ofs, m_trap->thl.verlen, snmp_version);
+  ofs += m_trap->thl.verlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.comlen);
+  ofs += m_trap->thl.comlenlen;
+  snmp_asn1_enc_raw(p, ofs, m_trap->thl.comlen, (u8_t *)&snmp_publiccommunity[0]);
+  ofs += m_trap->thl.comlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_TRAP));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.pdulen);
+  ofs += m_trap->thl.pdulenlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.eidlen);
+  ofs += m_trap->thl.eidlenlen;
+  snmp_asn1_enc_oid(p, ofs, m_trap->enterprise->len, &m_trap->enterprise->id[0]);
+  ofs += m_trap->thl.eidlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.aaddrlen);
+  ofs += m_trap->thl.aaddrlenlen;
+  snmp_asn1_enc_raw(p, ofs, m_trap->thl.aaddrlen, &m_trap->sip_raw[0]);
+  ofs += m_trap->thl.aaddrlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.gtrplen);
+  ofs += m_trap->thl.gtrplenlen;
+  snmp_asn1_enc_u32t(p, ofs, m_trap->thl.gtrplen, m_trap->gen_trap);
+  ofs += m_trap->thl.gtrplen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.strplen);
+  ofs += m_trap->thl.strplenlen;
+  snmp_asn1_enc_u32t(p, ofs, m_trap->thl.strplen, m_trap->spc_trap);
+  ofs += m_trap->thl.strplen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.tslen);
+  ofs += m_trap->thl.tslenlen;
+  snmp_asn1_enc_u32t(p, ofs, m_trap->thl.tslen, m_trap->ts);
+  ofs += m_trap->thl.tslen;
+
+  return ofs;
+}
+
+/**
+ * Encodes varbind list from head to tail.
+ */
+static u16_t
+snmp_varbind_list_enc(struct snmp_varbind_root *root, struct pbuf *p, u16_t ofs)
+{
+  struct snmp_varbind *vb;
+  s32_t *sint_ptr;
+  u32_t *uint_ptr;
+  u8_t *raw_ptr;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, root->seqlen);
+  ofs += root->seqlenlen;
+
+  vb = root->head;
+  while ( vb != NULL )
+  {
+    snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ));
+    ofs += 1;
+    snmp_asn1_enc_length(p, ofs, vb->seqlen);
+    ofs += vb->seqlenlen;
+
+    snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID));
+    ofs += 1;
+    snmp_asn1_enc_length(p, ofs, vb->olen);
+    ofs += vb->olenlen;
+    snmp_asn1_enc_oid(p, ofs, vb->ident_len, &vb->ident[0]);
+    ofs += vb->olen;
+
+    snmp_asn1_enc_type(p, ofs, vb->value_type);
+    ofs += 1;
+    snmp_asn1_enc_length(p, ofs, vb->vlen);
+    ofs += vb->vlenlen;
+
+    switch (vb->value_type)
+    {
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG):
+        sint_ptr = vb->value;
+        snmp_asn1_enc_s32t(p, ofs, vb->vlen, *sint_ptr);
+        break;
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS):
+        uint_ptr = vb->value;
+        snmp_asn1_enc_u32t(p, ofs, vb->vlen, *uint_ptr);
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE):
+        raw_ptr = vb->value;
+        snmp_asn1_enc_raw(p, ofs, vb->vlen, raw_ptr);
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL):
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID):
+        sint_ptr = vb->value;
+        snmp_asn1_enc_oid(p, ofs, vb->value_len / sizeof(s32_t), sint_ptr);
+        break;
+      default:
+        /* unsupported type */
+        break;
+    };
+    ofs += vb->vlen;
+    vb = vb->next;
+  }
+  return ofs;
+}
+
+#endif /* LWIP_SNMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/stats.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/stats.c
new file mode 100644
index 0000000..76c979f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/stats.c
@@ -0,0 +1,142 @@
+/**
+ * @file
+ * Statistics module
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_STATS /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/def.h"
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+
+#include 
+
+struct stats_ lwip_stats;
+
+#if LWIP_STATS_DISPLAY
+void
+stats_display_proto(struct stats_proto *proto, char *name)
+{
+  LWIP_PLATFORM_DIAG(("\n%s\n\t", name));
+  LWIP_PLATFORM_DIAG(("xmit: %"STAT_COUNTER_F"\n\t", proto->xmit));
+  LWIP_PLATFORM_DIAG(("rexmit: %"STAT_COUNTER_F"\n\t", proto->rexmit));
+  LWIP_PLATFORM_DIAG(("recv: %"STAT_COUNTER_F"\n\t", proto->recv));
+  LWIP_PLATFORM_DIAG(("fw: %"STAT_COUNTER_F"\n\t", proto->fw));
+  LWIP_PLATFORM_DIAG(("drop: %"STAT_COUNTER_F"\n\t", proto->drop));
+  LWIP_PLATFORM_DIAG(("chkerr: %"STAT_COUNTER_F"\n\t", proto->chkerr));
+  LWIP_PLATFORM_DIAG(("lenerr: %"STAT_COUNTER_F"\n\t", proto->lenerr));
+  LWIP_PLATFORM_DIAG(("memerr: %"STAT_COUNTER_F"\n\t", proto->memerr));
+  LWIP_PLATFORM_DIAG(("rterr: %"STAT_COUNTER_F"\n\t", proto->rterr));
+  LWIP_PLATFORM_DIAG(("proterr: %"STAT_COUNTER_F"\n\t", proto->proterr));
+  LWIP_PLATFORM_DIAG(("opterr: %"STAT_COUNTER_F"\n\t", proto->opterr));
+  LWIP_PLATFORM_DIAG(("err: %"STAT_COUNTER_F"\n\t", proto->err));
+  LWIP_PLATFORM_DIAG(("cachehit: %"STAT_COUNTER_F"\n", proto->cachehit));
+}
+
+void
+stats_display_igmp(struct stats_igmp *igmp)
+{
+  LWIP_PLATFORM_DIAG(("\nIGMP\n\t"));
+  LWIP_PLATFORM_DIAG(("lenerr: %"STAT_COUNTER_F"\n\t", igmp->lenerr));
+  LWIP_PLATFORM_DIAG(("chkerr: %"STAT_COUNTER_F"\n\t", igmp->chkerr));
+  LWIP_PLATFORM_DIAG(("v1_rxed: %"STAT_COUNTER_F"\n\t", igmp->v1_rxed));
+  LWIP_PLATFORM_DIAG(("join_sent: %"STAT_COUNTER_F"\n\t", igmp->join_sent));
+  LWIP_PLATFORM_DIAG(("leave_sent: %"STAT_COUNTER_F"\n\t", igmp->leave_sent));
+  LWIP_PLATFORM_DIAG(("unicast_query: %"STAT_COUNTER_F"\n\t", igmp->unicast_query));
+  LWIP_PLATFORM_DIAG(("report_sent: %"STAT_COUNTER_F"\n\t", igmp->report_sent));
+  LWIP_PLATFORM_DIAG(("report_rxed: %"STAT_COUNTER_F"\n\t", igmp->report_rxed));
+  LWIP_PLATFORM_DIAG(("group_query_rxed: %"STAT_COUNTER_F"\n", igmp->group_query_rxed));
+}
+
+void
+stats_display_mem(struct stats_mem *mem, char *name)
+{
+  LWIP_PLATFORM_DIAG(("\nMEM %s\n\t", name));
+  LWIP_PLATFORM_DIAG(("avail: %"U32_F"\n\t", (u32_t)mem->avail));
+  LWIP_PLATFORM_DIAG(("used: %"U32_F"\n\t", (u32_t)mem->used));
+  LWIP_PLATFORM_DIAG(("max: %"U32_F"\n\t", (u32_t)mem->max));
+  LWIP_PLATFORM_DIAG(("err: %"U32_F"\n", (u32_t)mem->err));
+}
+
+void
+stats_display(void)
+{
+#if MEMP_STATS
+  s16_t i;
+  char * memp_names[] = {
+#define LWIP_MEMPOOL(name,num,size,desc) desc,
+#include "lwip/memp_std.h"
+  };
+#endif
+#if LINK_STATS
+  stats_display_proto(&lwip_stats.link, "LINK");
+#endif
+#if ETHARP_STATS
+  stats_display_proto(&lwip_stats.etharp, "ETHARP");
+#endif
+#if IPFRAG_STATS
+  stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG");
+#endif
+#if IP_STATS
+  stats_display_proto(&lwip_stats.ip, "IP");
+#endif
+#if ICMP_STATS
+  stats_display_proto(&lwip_stats.icmp, "ICMP");
+#endif
+#if IGMP_STATS
+  stats_display_igmp(&lwip_stats.igmp);
+#endif
+#if UDP_STATS
+  stats_display_proto(&lwip_stats.udp, "UDP");
+#endif
+#if TCP_STATS
+  stats_display_proto(&lwip_stats.tcp, "TCP");
+#endif
+#if MEM_STATS
+  stats_display_mem(&lwip_stats.mem, "HEAP");
+#endif
+#if MEMP_STATS
+  for (i = 0; i < MEMP_MAX; i++) {
+    stats_display_mem(&lwip_stats.memp[i], memp_names[i]);
+  }
+#endif
+}
+#endif /* LWIP_STATS_DISPLAY */
+
+#endif /* LWIP_STATS */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/sys.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/sys.c
new file mode 100644
index 0000000..7f81e50
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/sys.c
@@ -0,0 +1,344 @@
+/**
+ * @file
+ * lwIP Operating System abstraction
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if (NO_SYS == 0) /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/sys.h"
+#include "lwip/def.h"
+#include "lwip/memp.h"
+#include "lwip/tcpip.h"
+
+/**
+ * Struct used for sys_sem_wait_timeout() to tell wether the time
+ * has run out or the semaphore has really become available.
+ */
+struct sswt_cb
+{
+  s16_t timeflag;
+  sys_sem_t *psem;
+};
+
+/**
+ * Wait (forever) for a message to arrive in an mbox.
+ * While waiting, timeouts (for this thread) are processed.
+ *
+ * @param mbox the mbox to fetch the message from
+ * @param msg the place to store the message
+ */
+void
+sys_mbox_fetch(sys_mbox_t mbox, void **msg)
+{
+  u32_t time;
+  struct sys_timeouts *timeouts;
+  struct sys_timeo *tmptimeout;
+  sys_timeout_handler h;
+  void *arg;
+
+ again:
+  timeouts = sys_arch_timeouts();
+
+  if (!timeouts || !timeouts->next) {
+    UNLOCK_TCPIP_CORE();
+    time = sys_arch_mbox_fetch(mbox, msg, 0);
+    LOCK_TCPIP_CORE();
+  } else {
+    if (timeouts->next->time > 0) {
+      UNLOCK_TCPIP_CORE();
+      time = sys_arch_mbox_fetch(mbox, msg, timeouts->next->time);
+      LOCK_TCPIP_CORE();
+    } else {
+      time = SYS_ARCH_TIMEOUT;
+    }
+
+    if (time == SYS_ARCH_TIMEOUT) {
+      /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message
+         could be fetched. We should now call the timeout handler and
+         deallocate the memory allocated for the timeout. */
+      tmptimeout = timeouts->next;
+      timeouts->next = tmptimeout->next;
+      h   = tmptimeout->h;
+      arg = tmptimeout->arg;
+      memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
+      if (h != NULL) {
+        LWIP_DEBUGF(SYS_DEBUG, ("smf calling h=%p(%p)\n", (void*)&h, arg));
+        h(arg);
+      }
+
+      /* We try again to fetch a message from the mbox. */
+      goto again;
+    } else {
+      /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout
+         occured. The time variable is set to the number of
+         milliseconds we waited for the message. */
+      if (time < timeouts->next->time) {
+        timeouts->next->time -= time;
+      } else {
+        timeouts->next->time = 0;
+      }
+    }
+  }
+}
+
+/**
+ * Wait (forever) for a semaphore to become available.
+ * While waiting, timeouts (for this thread) are processed.
+ *
+ * @param sem semaphore to wait for
+ */
+void
+sys_sem_wait(sys_sem_t sem)
+{
+  u32_t time;
+  struct sys_timeouts *timeouts;
+  struct sys_timeo *tmptimeout;
+  sys_timeout_handler h;
+  void *arg;
+
+ again:
+
+  timeouts = sys_arch_timeouts();
+
+  if (!timeouts || !timeouts->next) {
+    sys_arch_sem_wait(sem, 0);
+  } else {
+    if (timeouts->next->time > 0) {
+      time = sys_arch_sem_wait(sem, timeouts->next->time);
+    } else {
+      time = SYS_ARCH_TIMEOUT;
+    }
+
+    if (time == SYS_ARCH_TIMEOUT) {
+      /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message
+        could be fetched. We should now call the timeout handler and
+        deallocate the memory allocated for the timeout. */
+      tmptimeout = timeouts->next;
+      timeouts->next = tmptimeout->next;
+      h = tmptimeout->h;
+      arg = tmptimeout->arg;
+      memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
+      if (h != NULL) {
+        LWIP_DEBUGF(SYS_DEBUG, ("ssw h=%p(%p)\n", (void*)&h, (void *)arg));
+        h(arg);
+      }
+
+      /* We try again to fetch a message from the mbox. */
+      goto again;
+    } else {
+      /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout
+         occured. The time variable is set to the number of
+         milliseconds we waited for the message. */
+      if (time < timeouts->next->time) {
+        timeouts->next->time -= time;
+      } else {
+        timeouts->next->time = 0;
+      }
+    }
+  }
+}
+
+/**
+ * Create a one-shot timer (aka timeout). Timeouts are processed in the
+ * following cases:
+ * - while waiting for a message using sys_mbox_fetch()
+ * - while waiting for a semaphore using sys_sem_wait() or sys_sem_wait_timeout()
+ * - while sleeping using the inbuilt sys_msleep()
+ *
+ * @param msecs time in milliseconds after that the timer should expire
+ * @param h callback function to call when msecs have elapsed
+ * @param arg argument to pass to the callback function
+ */
+void
+sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg)
+{
+  struct sys_timeouts *timeouts;
+  struct sys_timeo *timeout, *t;
+
+  timeout = memp_malloc(MEMP_SYS_TIMEOUT);
+  if (timeout == NULL) {
+    LWIP_ASSERT("sys_timeout: timeout != NULL", timeout != NULL);
+    return;
+  }
+  timeout->next = NULL;
+  timeout->h = h;
+  timeout->arg = arg;
+  timeout->time = msecs;
+
+  timeouts = sys_arch_timeouts();
+
+  LWIP_DEBUGF(SYS_DEBUG, ("sys_timeout: %p msecs=%"U32_F" h=%p arg=%p\n",
+    (void *)timeout, msecs, (void*)&h, (void *)arg));
+
+  if (timeouts == NULL) {
+    LWIP_ASSERT("sys_timeout: timeouts != NULL", timeouts != NULL);
+    return;
+  }
+
+  if (timeouts->next == NULL) {
+    timeouts->next = timeout;
+    return;
+  }
+
+  if (timeouts->next->time > msecs) {
+    timeouts->next->time -= msecs;
+    timeout->next = timeouts->next;
+    timeouts->next = timeout;
+  } else {
+    for(t = timeouts->next; t != NULL; t = t->next) {
+      timeout->time -= t->time;
+      if (t->next == NULL || t->next->time > timeout->time) {
+        if (t->next != NULL) {
+          t->next->time -= timeout->time;
+        }
+        timeout->next = t->next;
+        t->next = timeout;
+        break;
+      }
+    }
+  }
+}
+
+/**
+ * Go through timeout list (for this task only) and remove the first matching
+ * entry, even though the timeout has not triggered yet.
+ *
+ * @note This function only works as expected if there is only one timeout
+ * calling 'h' in the list of timeouts.
+ *
+ * @param h callback function that would be called by the timeout
+ * @param arg callback argument that would be passed to h
+*/
+void
+sys_untimeout(sys_timeout_handler h, void *arg)
+{
+  struct sys_timeouts *timeouts;
+  struct sys_timeo *prev_t, *t;
+
+  timeouts = sys_arch_timeouts();
+
+  if (timeouts == NULL) {
+    LWIP_ASSERT("sys_untimeout: timeouts != NULL", timeouts != NULL);
+    return;
+  }
+  if (timeouts->next == NULL) {
+    return;
+  }
+
+  for (t = timeouts->next, prev_t = NULL; t != NULL; prev_t = t, t = t->next) {
+    if ((t->h == h) && (t->arg == arg)) {
+      /* We have a match */
+      /* Unlink from previous in list */
+      if (prev_t == NULL)
+        timeouts->next = t->next;
+      else
+        prev_t->next = t->next;
+      /* If not the last one, add time of this one back to next */
+      if (t->next != NULL)
+        t->next->time += t->time;
+      memp_free(MEMP_SYS_TIMEOUT, t);
+      return;
+    }
+  }
+  return;
+}
+
+/**
+ * Timeout handler function for sys_sem_wait_timeout()
+ *
+ * @param arg struct sswt_cb* used to signal a semaphore and end waiting.
+ */
+static void
+sswt_handler(void *arg)
+{
+  struct sswt_cb *sswt_cb = (struct sswt_cb *) arg;
+
+  /* Timeout. Set flag to TRUE and signal semaphore */
+  sswt_cb->timeflag = 1;
+  sys_sem_signal(*(sswt_cb->psem));
+}
+
+/**
+ * Wait for a semaphore with timeout (specified in ms)
+ *
+ * @param sem semaphore to wait
+ * @param timeout timeout in ms (0: wait forever)
+ * @return 0 on timeout, 1 otherwise
+ */
+int
+sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout)
+{
+  struct sswt_cb sswt_cb;
+
+  sswt_cb.psem = &sem;
+  sswt_cb.timeflag = 0;
+
+  /* If timeout is zero, then just wait forever */
+  if (timeout > 0) {
+    /* Create a timer and pass it the address of our flag */
+    sys_timeout(timeout, sswt_handler, &sswt_cb);
+  }
+  sys_sem_wait(sem);
+  /* Was it a timeout? */
+  if (sswt_cb.timeflag) {
+    /* timeout */
+    return 0;
+  } else {
+    /* Not a timeout. Remove timeout entry */
+    sys_untimeout(sswt_handler, &sswt_cb);
+    return 1;
+  }
+}
+
+/**
+ * Sleep for some ms. Timeouts are processed while sleeping.
+ *
+ * @param ms number of milliseconds to sleep
+ */
+void
+sys_msleep(u32_t ms)
+{
+  sys_sem_t delaysem = sys_sem_new(0);
+
+  sys_sem_wait_timeout(delaysem, ms);
+
+  sys_sem_free(delaysem);
+}
+
+
+#endif /* NO_SYS */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/tcp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/tcp.c
new file mode 100644
index 0000000..aa2f3c8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/tcp.c
@@ -0,0 +1,1418 @@
+/**
+ * @file
+ * Transmission Control Protocol for IP
+ *
+ * This file contains common functions for the TCP implementation, such as functinos
+ * for manipulating the data structures and the TCP timer functions. TCP functions
+ * related to input and output is found in tcp_in.c and tcp_out.c respectively.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/snmp.h"
+#include "lwip/tcp.h"
+
+#include 
+
+/* Incremented every coarse grained timer shot (typically every 500 ms). */
+u32_t tcp_ticks;
+const u8_t tcp_backoff[13] =
+    { 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7};
+ /* Times per slowtmr hits */
+const u8_t tcp_persist_backoff[7] = { 3, 6, 12, 24, 48, 96, 120 };
+
+/* The TCP PCB lists. */
+
+/** List of all TCP PCBs bound but not yet (connected || listening) */
+struct tcp_pcb *tcp_bound_pcbs;
+/** List of all TCP PCBs in LISTEN state */
+union tcp_listen_pcbs_t tcp_listen_pcbs;
+/** List of all TCP PCBs that are in a state in which
+ * they accept or send data. */
+struct tcp_pcb *tcp_active_pcbs;
+/** List of all TCP PCBs in TIME-WAIT state */
+struct tcp_pcb *tcp_tw_pcbs;
+
+struct tcp_pcb *tcp_tmp_pcb;
+
+static u8_t tcp_timer;
+static u16_t tcp_new_port(void);
+
+/**
+ * Called periodically to dispatch TCP timers.
+ *
+ */
+void
+tcp_tmr(void)
+{
+  /* Call tcp_fasttmr() every 250 ms */
+  tcp_fasttmr();
+
+  if (++tcp_timer & 1) {
+    /* Call tcp_tmr() every 500 ms, i.e., every other timer
+       tcp_tmr() is called. */
+    tcp_slowtmr();
+  }
+}
+
+/**
+ * Closes the connection held by the PCB.
+ *
+ * Listening pcbs are freed and may not be referenced any more.
+ * Connection pcbs are freed if not yet connected and may not be referenced
+ * any more. If a connection is established (at least SYN received or in
+ * a closing state), the connection is closed, and put in a closing state.
+ * The pcb is then automatically freed in tcp_slowtmr(). It is therefore
+ * unsafe to reference it.
+ *
+ * @param pcb the tcp_pcb to close
+ * @return ERR_OK if connection has been closed
+ *         another err_t if closing failed and pcb is not freed
+ */
+err_t
+tcp_close(struct tcp_pcb *pcb)
+{
+  err_t err;
+
+#if TCP_DEBUG
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in "));
+  tcp_debug_print_state(pcb->state);
+#endif /* TCP_DEBUG */
+
+  switch (pcb->state) {
+  case CLOSED:
+    /* Closing a pcb in the CLOSED state might seem erroneous,
+     * however, it is in this state once allocated and as yet unused
+     * and the user needs some way to free it should the need arise.
+     * Calling tcp_close() with a pcb that has already been closed, (i.e. twice)
+     * or for a pcb that has been used and then entered the CLOSED state
+     * is erroneous, but this should never happen as the pcb has in those cases
+     * been freed, and so any remaining handles are bogus. */
+    err = ERR_OK;
+    TCP_RMV(&tcp_bound_pcbs, pcb);
+    memp_free(MEMP_TCP_PCB, pcb);
+    pcb = NULL;
+    break;
+  case LISTEN:
+    err = ERR_OK;
+    tcp_pcb_remove((struct tcp_pcb **)&tcp_listen_pcbs.pcbs, pcb);
+    memp_free(MEMP_TCP_PCB_LISTEN, pcb);
+    pcb = NULL;
+    break;
+  case SYN_SENT:
+    err = ERR_OK;
+    tcp_pcb_remove(&tcp_active_pcbs, pcb);
+    memp_free(MEMP_TCP_PCB, pcb);
+    pcb = NULL;
+    snmp_inc_tcpattemptfails();
+    break;
+  case SYN_RCVD:
+    err = tcp_send_ctrl(pcb, TCP_FIN);
+    if (err == ERR_OK) {
+      snmp_inc_tcpattemptfails();
+      pcb->state = FIN_WAIT_1;
+    }
+    break;
+  case ESTABLISHED:
+    err = tcp_send_ctrl(pcb, TCP_FIN);
+    if (err == ERR_OK) {
+      snmp_inc_tcpestabresets();
+      pcb->state = FIN_WAIT_1;
+    }
+    break;
+  case CLOSE_WAIT:
+    err = tcp_send_ctrl(pcb, TCP_FIN);
+    if (err == ERR_OK) {
+      snmp_inc_tcpestabresets();
+      pcb->state = LAST_ACK;
+    }
+    break;
+  default:
+    /* Has already been closed, do nothing. */
+    err = ERR_OK;
+    pcb = NULL;
+    break;
+  }
+
+  if (pcb != NULL && err == ERR_OK) {
+    /* To ensure all data has been sent when tcp_close returns, we have
+       to make sure tcp_output doesn't fail.
+       Since we don't really have to ensure all data has been sent when tcp_close
+       returns (unsent data is sent from tcp timer functions, also), we don't care
+       for the return value of tcp_output for now. */
+    /* @todo: When implementing SO_LINGER, this must be changed somehow:
+       If SOF_LINGER is set, the data should be sent when tcp_close returns. */
+    tcp_output(pcb);
+  }
+  return err;
+}
+
+/**
+ * Aborts a connection by sending a RST to the remote host and deletes
+ * the local protocol control block. This is done when a connection is
+ * killed because of shortage of memory.
+ *
+ * @param pcb the tcp_pcb to abort
+ */
+void
+tcp_abort(struct tcp_pcb *pcb)
+{
+  u32_t seqno, ackno;
+  u16_t remote_port, local_port;
+  struct ip_addr remote_ip, local_ip;
+#if LWIP_CALLBACK_API
+  void (* errf)(void *arg, err_t err);
+#endif /* LWIP_CALLBACK_API */
+  void *errf_arg;
+
+
+  /* Figure out on which TCP PCB list we are, and remove us. If we
+     are in an active state, call the receive function associated with
+     the PCB with a NULL argument, and send an RST to the remote end. */
+  if (pcb->state == TIME_WAIT) {
+    tcp_pcb_remove(&tcp_tw_pcbs, pcb);
+    memp_free(MEMP_TCP_PCB, pcb);
+  } else {
+    seqno = pcb->snd_nxt;
+    ackno = pcb->rcv_nxt;
+    ip_addr_set(&local_ip, &(pcb->local_ip));
+    ip_addr_set(&remote_ip, &(pcb->remote_ip));
+    local_port = pcb->local_port;
+    remote_port = pcb->remote_port;
+#if LWIP_CALLBACK_API
+    errf = pcb->errf;
+#endif /* LWIP_CALLBACK_API */
+    errf_arg = pcb->callback_arg;
+    tcp_pcb_remove(&tcp_active_pcbs, pcb);
+    if (pcb->unacked != NULL) {
+      tcp_segs_free(pcb->unacked);
+    }
+    if (pcb->unsent != NULL) {
+      tcp_segs_free(pcb->unsent);
+    }
+#if TCP_QUEUE_OOSEQ
+    if (pcb->ooseq != NULL) {
+      tcp_segs_free(pcb->ooseq);
+    }
+#endif /* TCP_QUEUE_OOSEQ */
+    memp_free(MEMP_TCP_PCB, pcb);
+    TCP_EVENT_ERR(errf, errf_arg, ERR_ABRT);
+    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abort: sending RST\n"));
+    tcp_rst(seqno, ackno, &local_ip, &remote_ip, local_port, remote_port);
+  }
+}
+
+/**
+ * Binds the connection to a local portnumber and IP address. If the
+ * IP address is not given (i.e., ipaddr == NULL), the IP address of
+ * the outgoing network interface is used instead.
+ *
+ * @param pcb the tcp_pcb to bind (no check is done whether this pcb is
+ *        already bound!)
+ * @param ipaddr the local ip address to bind to (use IP_ADDR_ANY to bind
+ *        to any local address
+ * @param port the local port to bind to
+ * @return ERR_USE if the port is already in use
+ *         ERR_OK if bound
+ */
+err_t
+tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
+{
+  struct tcp_pcb *cpcb;
+
+  LWIP_ERROR("tcp_connect: can only bind in state CLOSED", pcb->state == CLOSED, return ERR_ISCONN);
+
+  if (port == 0) {
+    port = tcp_new_port();
+  }
+  /* Check if the address already is in use. */
+  /* Check the listen pcbs. */
+  for(cpcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs;
+      cpcb != NULL; cpcb = cpcb->next) {
+    if (cpcb->local_port == port) {
+      if (ip_addr_isany(&(cpcb->local_ip)) ||
+          ip_addr_isany(ipaddr) ||
+          ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
+        return ERR_USE;
+      }
+    }
+  }
+  /* Check the connected pcbs. */
+  for(cpcb = tcp_active_pcbs;
+      cpcb != NULL; cpcb = cpcb->next) {
+    if (cpcb->local_port == port) {
+      if (ip_addr_isany(&(cpcb->local_ip)) ||
+          ip_addr_isany(ipaddr) ||
+          ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
+        return ERR_USE;
+      }
+    }
+  }
+  /* Check the bound, not yet connected pcbs. */
+  for(cpcb = tcp_bound_pcbs; cpcb != NULL; cpcb = cpcb->next) {
+    if (cpcb->local_port == port) {
+      if (ip_addr_isany(&(cpcb->local_ip)) ||
+          ip_addr_isany(ipaddr) ||
+          ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
+        return ERR_USE;
+      }
+    }
+  }
+  /* @todo: until SO_REUSEADDR is implemented (see task #6995 on savannah),
+   * we have to check the pcbs in TIME-WAIT state, also: */
+  for(cpcb = tcp_tw_pcbs; cpcb != NULL; cpcb = cpcb->next) {
+    if (cpcb->local_port == port) {
+      if (ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
+        return ERR_USE;
+      }
+    }
+  }
+
+  if (!ip_addr_isany(ipaddr)) {
+    pcb->local_ip = *ipaddr;
+  }
+  pcb->local_port = port;
+  TCP_REG(&tcp_bound_pcbs, pcb);
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %"U16_F"\n", port));
+  return ERR_OK;
+}
+#if LWIP_CALLBACK_API
+/**
+ * Default accept callback if no accept callback is specified by the user.
+ */
+static err_t
+tcp_accept_null(void *arg, struct tcp_pcb *pcb, err_t err)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_UNUSED_ARG(err);
+
+  return ERR_ABRT;
+}
+#endif /* LWIP_CALLBACK_API */
+
+/**
+ * Set the state of the connection to be LISTEN, which means that it
+ * is able to accept incoming connections. The protocol control block
+ * is reallocated in order to consume less memory. Setting the
+ * connection to LISTEN is an irreversible process.
+ *
+ * @param pcb the original tcp_pcb
+ * @param backlog the incoming connections queue limit
+ * @return tcp_pcb used for listening, consumes less memory.
+ *
+ * @note The original tcp_pcb is freed. This function therefore has to be
+ *       called like this:
+ *             tpcb = tcp_listen(tpcb);
+ */
+struct tcp_pcb *
+tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog)
+{
+  struct tcp_pcb_listen *lpcb;
+
+  LWIP_UNUSED_ARG(backlog);
+  LWIP_ERROR("tcp_listen: pcb already connected", pcb->state == CLOSED, return NULL);
+
+  /* already listening? */
+  if (pcb->state == LISTEN) {
+    return pcb;
+  }
+  lpcb = memp_malloc(MEMP_TCP_PCB_LISTEN);
+  if (lpcb == NULL) {
+    return NULL;
+  }
+  lpcb->callback_arg = pcb->callback_arg;
+  lpcb->local_port = pcb->local_port;
+  lpcb->state = LISTEN;
+  lpcb->so_options = pcb->so_options;
+  lpcb->so_options |= SOF_ACCEPTCONN;
+  lpcb->ttl = pcb->ttl;
+  lpcb->tos = pcb->tos;
+  ip_addr_set(&lpcb->local_ip, &pcb->local_ip);
+  TCP_RMV(&tcp_bound_pcbs, pcb);
+  memp_free(MEMP_TCP_PCB, pcb);
+#if LWIP_CALLBACK_API
+  lpcb->accept = tcp_accept_null;
+#endif /* LWIP_CALLBACK_API */
+#if TCP_LISTEN_BACKLOG
+  lpcb->accepts_pending = 0;
+  lpcb->backlog = (backlog ? backlog : 1);
+#endif /* TCP_LISTEN_BACKLOG */
+  TCP_REG(&tcp_listen_pcbs.listen_pcbs, lpcb);
+  return (struct tcp_pcb *)lpcb;
+}
+
+/**
+ * This function should be called by the application when it has
+ * processed the data. The purpose is to advertise a larger window
+ * when the data has been processed.
+ *
+ * @param pcb the tcp_pcb for which data is read
+ * @param len the amount of bytes that have been read by the application
+ */
+void
+tcp_recved(struct tcp_pcb *pcb, u16_t len)
+{
+  if ((u32_t)pcb->rcv_wnd + len > TCP_WND) {
+    pcb->rcv_wnd = TCP_WND;
+    pcb->rcv_ann_wnd = TCP_WND;
+  } else {
+    pcb->rcv_wnd += len;
+    if (pcb->rcv_wnd >= pcb->mss) {
+      pcb->rcv_ann_wnd = pcb->rcv_wnd;
+    }
+  }
+
+  if (!(pcb->flags & TF_ACK_DELAY) &&
+     !(pcb->flags & TF_ACK_NOW)) {
+    /*
+     * We send an ACK here (if one is not already pending, hence
+     * the above tests) as tcp_recved() implies that the application
+     * has processed some data, and so we can open the receiver's
+     * window to allow more to be transmitted.  This could result in
+     * two ACKs being sent for each received packet in some limited cases
+     * (where the application is only receiving data, and is slow to
+     * process it) but it is necessary to guarantee that the sender can
+     * continue to transmit.
+     */
+    tcp_ack(pcb);
+  }
+  else if (pcb->flags & TF_ACK_DELAY && pcb->rcv_wnd >= TCP_WND/2) {
+    /* If we can send a window update such that there is a full
+     * segment available in the window, do so now.  This is sort of
+     * nagle-like in its goals, and tries to hit a compromise between
+     * sending acks each time the window is updated, and only sending
+     * window updates when a timer expires.  The "threshold" used
+     * above (currently TCP_WND/2) can be tuned to be more or less
+     * aggressive  */
+    tcp_ack_now(pcb);
+  }
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: recveived %"U16_F" bytes, wnd %"U16_F" (%"U16_F").\n",
+         len, pcb->rcv_wnd, TCP_WND - pcb->rcv_wnd));
+}
+
+/**
+ * A nastly hack featuring 'goto' statements that allocates a
+ * new TCP local port.
+ *
+ * @return a new (free) local TCP port number
+ */
+static u16_t
+tcp_new_port(void)
+{
+  struct tcp_pcb *pcb;
+#ifndef TCP_LOCAL_PORT_RANGE_START
+#define TCP_LOCAL_PORT_RANGE_START 4096
+#define TCP_LOCAL_PORT_RANGE_END   0x7fff
+#endif
+  static u16_t port = TCP_LOCAL_PORT_RANGE_START;
+
+ again:
+  if (++port > TCP_LOCAL_PORT_RANGE_END) {
+    port = TCP_LOCAL_PORT_RANGE_START;
+  }
+
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->local_port == port) {
+      goto again;
+    }
+  }
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->local_port == port) {
+      goto again;
+    }
+  }
+  for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->local_port == port) {
+      goto again;
+    }
+  }
+  return port;
+}
+
+/**
+ * Connects to another host. The function given as the "connected"
+ * argument will be called when the connection has been established.
+ *
+ * @param pcb the tcp_pcb used to establish the connection
+ * @param ipaddr the remote ip address to connect to
+ * @param port the remote tcp port to connect to
+ * @param connected callback function to call when connected (or on error)
+ * @return ERR_VAL if invalid arguments are given
+ *         ERR_OK if connect request has been sent
+ *         other err_t values if connect request couldn't be sent
+ */
+err_t
+tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port,
+      err_t (* connected)(void *arg, struct tcp_pcb *tpcb, err_t err))
+{
+  u32_t optdata;
+  err_t ret;
+  u32_t iss;
+
+  LWIP_ERROR("tcp_connect: can only connected from state CLOSED", pcb->state == CLOSED, return ERR_ISCONN);
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %"U16_F"\n", port));
+  if (ipaddr != NULL) {
+    pcb->remote_ip = *ipaddr;
+  } else {
+    return ERR_VAL;
+  }
+  pcb->remote_port = port;
+  if (pcb->local_port == 0) {
+    pcb->local_port = tcp_new_port();
+  }
+  iss = tcp_next_iss();
+  pcb->rcv_nxt = 0;
+  pcb->snd_nxt = iss;
+  pcb->lastack = iss - 1;
+  pcb->snd_lbb = iss - 1;
+  pcb->rcv_wnd = TCP_WND;
+  pcb->rcv_ann_wnd = TCP_WND;
+  pcb->snd_wnd = TCP_WND;
+  /* The send MSS is updated when an MSS option is received. */
+  pcb->mss = (TCP_MSS > 536) ? 536 : TCP_MSS;
+#if TCP_CALCULATE_EFF_SEND_MSS
+  pcb->mss = tcp_eff_send_mss(pcb->mss, ipaddr);
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+  pcb->cwnd = 1;
+  pcb->ssthresh = pcb->mss * 10;
+  pcb->state = SYN_SENT;
+#if LWIP_CALLBACK_API
+  pcb->connected = connected;
+#endif /* LWIP_CALLBACK_API */
+  TCP_RMV(&tcp_bound_pcbs, pcb);
+  TCP_REG(&tcp_active_pcbs, pcb);
+
+  snmp_inc_tcpactiveopens();
+
+  /* Build an MSS option */
+  optdata = TCP_BUILD_MSS_OPTION();
+
+  ret = tcp_enqueue(pcb, NULL, 0, TCP_SYN, 0, (u8_t *)&optdata, 4);
+  if (ret == ERR_OK) {
+    tcp_output(pcb);
+  }
+  return ret;
+}
+
+/**
+ * Called every 500 ms and implements the retransmission timer and the timer that
+ * removes PCBs that have been in TIME-WAIT for enough time. It also increments
+ * various timers such as the inactivity timer in each PCB.
+ *
+ * Automatically called from tcp_tmr().
+ */
+void
+tcp_slowtmr(void)
+{
+  struct tcp_pcb *pcb, *pcb2, *prev;
+  u16_t eff_wnd;
+  u8_t pcb_remove;      /* flag if a PCB should be removed */
+  err_t err;
+
+  err = ERR_OK;
+
+  ++tcp_ticks;
+
+  /* Steps through all of the active PCBs. */
+  prev = NULL;
+  pcb = tcp_active_pcbs;
+  if (pcb == NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n"));
+  }
+  while (pcb != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n"));
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN);
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT);
+
+    pcb_remove = 0;
+
+    if (pcb->state == SYN_SENT && pcb->nrtx == TCP_SYNMAXRTX) {
+      ++pcb_remove;
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n"));
+    }
+    else if (pcb->nrtx == TCP_MAXRTX) {
+      ++pcb_remove;
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n"));
+    } else {
+      if (pcb->persist_backoff > 0) {
+        /* If snd_wnd is zero, use persist timer to send 1 byte probes
+         * instead of using the standard retransmission mechanism. */
+        pcb->persist_cnt++;
+        if (pcb->persist_cnt >= tcp_persist_backoff[pcb->persist_backoff-1]) {
+          pcb->persist_cnt = 0;
+          if (pcb->persist_backoff < sizeof(tcp_persist_backoff)) {
+            pcb->persist_backoff++;
+          }
+          tcp_zero_window_probe(pcb);
+        }
+      } else {
+        /* Increase the retransmission timer if it is running */
+        if(pcb->rtime >= 0)
+          ++pcb->rtime;
+
+        if (pcb->unacked != NULL && pcb->rtime >= pcb->rto) {
+          /* Time for a retransmission. */
+          LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_slowtmr: rtime %"S16_F
+                                      " pcb->rto %"S16_F"\n",
+                                      pcb->rtime, pcb->rto));
+
+          /* Double retransmission time-out unless we are trying to
+           * connect to somebody (i.e., we are in SYN_SENT). */
+          if (pcb->state != SYN_SENT) {
+            pcb->rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[pcb->nrtx];
+          }
+
+          /* Reset the retransmission timer. */
+          pcb->rtime = 0;
+
+          /* Reduce congestion window and ssthresh. */
+          eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd);
+          pcb->ssthresh = eff_wnd >> 1;
+          if (pcb->ssthresh < pcb->mss) {
+            pcb->ssthresh = pcb->mss * 2;
+          }
+          pcb->cwnd = pcb->mss;
+          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"U16_F
+                                       " ssthresh %"U16_F"\n",
+                                       pcb->cwnd, pcb->ssthresh));
+
+          /* The following needs to be called AFTER cwnd is set to one
+             mss - STJ */
+          tcp_rexmit_rto(pcb);
+        }
+      }
+    }
+    /* Check if this PCB has stayed too long in FIN-WAIT-2 */
+    if (pcb->state == FIN_WAIT_2) {
+      if ((u32_t)(tcp_ticks - pcb->tmr) >
+          TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) {
+        ++pcb_remove;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in FIN-WAIT-2\n"));
+      }
+    }
+
+    /* Check if KEEPALIVE should be sent */
+    if((pcb->so_options & SOF_KEEPALIVE) &&
+       ((pcb->state == ESTABLISHED) ||
+        (pcb->state == CLOSE_WAIT))) {
+#if LWIP_TCP_KEEPALIVE
+      if((u32_t)(tcp_ticks - pcb->tmr) >
+         (pcb->keep_idle + (pcb->keep_cnt*pcb->keep_intvl))
+         / TCP_SLOW_INTERVAL)
+#else
+      if((u32_t)(tcp_ticks - pcb->tmr) >
+         (pcb->keep_idle + TCP_MAXIDLE) / TCP_SLOW_INTERVAL)
+#endif /* LWIP_TCP_KEEPALIVE */
+      {
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to %"U16_F".%"U16_F".%"U16_F".%"U16_F".\n",
+                                ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+                                ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip)));
+
+        tcp_abort(pcb);
+      }
+#if LWIP_TCP_KEEPALIVE
+      else if((u32_t)(tcp_ticks - pcb->tmr) >
+              (pcb->keep_idle + pcb->keep_cnt_sent * pcb->keep_intvl)
+              / TCP_SLOW_INTERVAL)
+#else
+      else if((u32_t)(tcp_ticks - pcb->tmr) >
+              (pcb->keep_idle + pcb->keep_cnt_sent * TCP_KEEPINTVL_DEFAULT)
+              / TCP_SLOW_INTERVAL)
+#endif /* LWIP_TCP_KEEPALIVE */
+      {
+        tcp_keepalive(pcb);
+        pcb->keep_cnt_sent++;
+      }
+    }
+
+    /* If this PCB has queued out of sequence data, but has been
+       inactive for too long, will drop the data (it will eventually
+       be retransmitted). */
+#if TCP_QUEUE_OOSEQ
+    if (pcb->ooseq != NULL &&
+        (u32_t)tcp_ticks - pcb->tmr >= pcb->rto * TCP_OOSEQ_TIMEOUT) {
+      tcp_segs_free(pcb->ooseq);
+      pcb->ooseq = NULL;
+      LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n"));
+    }
+#endif /* TCP_QUEUE_OOSEQ */
+
+    /* Check if this PCB has stayed too long in SYN-RCVD */
+    if (pcb->state == SYN_RCVD) {
+      if ((u32_t)(tcp_ticks - pcb->tmr) >
+          TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) {
+        ++pcb_remove;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n"));
+      }
+    }
+
+    /* Check if this PCB has stayed too long in LAST-ACK */
+    if (pcb->state == LAST_ACK) {
+      if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
+        ++pcb_remove;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n"));
+      }
+    }
+
+    /* If the PCB should be removed, do it. */
+    if (pcb_remove) {
+      tcp_pcb_purge(pcb);
+      /* Remove PCB from tcp_active_pcbs list. */
+      if (prev != NULL) {
+        LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs);
+        prev->next = pcb->next;
+      } else {
+        /* This PCB was the first. */
+        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb);
+        tcp_active_pcbs = pcb->next;
+      }
+
+      TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_ABRT);
+
+      pcb2 = pcb->next;
+      memp_free(MEMP_TCP_PCB, pcb);
+      pcb = pcb2;
+    } else {
+
+      /* We check if we should poll the connection. */
+      ++pcb->polltmr;
+      if (pcb->polltmr >= pcb->pollinterval) {
+        pcb->polltmr = 0;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n"));
+        TCP_EVENT_POLL(pcb, err);
+        if (err == ERR_OK) {
+          tcp_output(pcb);
+        }
+      }
+
+      prev = pcb;
+      pcb = pcb->next;
+    }
+  }
+
+
+  /* Steps through all of the TIME-WAIT PCBs. */
+  prev = NULL;
+  pcb = tcp_tw_pcbs;
+  while (pcb != NULL) {
+    LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+    pcb_remove = 0;
+
+    /* Check if this PCB has stayed long enough in TIME-WAIT */
+    if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
+      ++pcb_remove;
+    }
+
+
+
+    /* If the PCB should be removed, do it. */
+    if (pcb_remove) {
+      tcp_pcb_purge(pcb);
+      /* Remove PCB from tcp_tw_pcbs list. */
+      if (prev != NULL) {
+        LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs);
+        prev->next = pcb->next;
+      } else {
+        /* This PCB was the first. */
+        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb);
+        tcp_tw_pcbs = pcb->next;
+      }
+      pcb2 = pcb->next;
+      memp_free(MEMP_TCP_PCB, pcb);
+      pcb = pcb2;
+    } else {
+      prev = pcb;
+      pcb = pcb->next;
+    }
+  }
+}
+
+/**
+ * Is called every TCP_FAST_INTERVAL (250 ms) and process data previously
+ * "refused" by upper layer (application) and sends delayed ACKs.
+ *
+ * Automatically called from tcp_tmr().
+ */
+void
+tcp_fasttmr(void)
+{
+  struct tcp_pcb *pcb;
+
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    /* If there is data which was previously "refused" by upper layer */
+    if (pcb->refused_data != NULL) {
+      /* Notify again application with data previously received. */
+      err_t err;
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_fasttmr: notify kept packet\n"));
+      TCP_EVENT_RECV(pcb, pcb->refused_data, ERR_OK, err);
+      if (err == ERR_OK) {
+        pcb->refused_data = NULL;
+      }
+    }
+
+    /* send delayed ACKs */
+    if (pcb->flags & TF_ACK_DELAY) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n"));
+      tcp_ack_now(pcb);
+      pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
+    }
+  }
+}
+
+/**
+ * Deallocates a list of TCP segments (tcp_seg structures).
+ *
+ * @param seg tcp_seg list of TCP segments to free
+ * @return the number of pbufs that were deallocated
+ */
+u8_t
+tcp_segs_free(struct tcp_seg *seg)
+{
+  u8_t count = 0;
+  struct tcp_seg *next;
+  while (seg != NULL) {
+    next = seg->next;
+    count += tcp_seg_free(seg);
+    seg = next;
+  }
+  return count;
+}
+
+/**
+ * Frees a TCP segment (tcp_seg structure).
+ *
+ * @param seg single tcp_seg to free
+ * @return the number of pbufs that were deallocated
+ */
+u8_t
+tcp_seg_free(struct tcp_seg *seg)
+{
+  u8_t count = 0;
+
+  if (seg != NULL) {
+    if (seg->p != NULL) {
+      count = pbuf_free(seg->p);
+#if TCP_DEBUG
+      seg->p = NULL;
+#endif /* TCP_DEBUG */
+    }
+    memp_free(MEMP_TCP_SEG, seg);
+  }
+  return count;
+}
+
+/**
+ * Sets the priority of a connection.
+ *
+ * @param pcb the tcp_pcb to manipulate
+ * @param prio new priority
+ */
+void
+tcp_setprio(struct tcp_pcb *pcb, u8_t prio)
+{
+  pcb->prio = prio;
+}
+#if TCP_QUEUE_OOSEQ
+
+/**
+ * Returns a copy of the given TCP segment.
+ * The pbuf and data are not copied, only the pointers
+ *
+ * @param seg the old tcp_seg
+ * @return a copy of seg
+ */
+struct tcp_seg *
+tcp_seg_copy(struct tcp_seg *seg)
+{
+  struct tcp_seg *cseg;
+
+  cseg = memp_malloc(MEMP_TCP_SEG);
+  if (cseg == NULL) {
+    return NULL;
+  }
+  SMEMCPY((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg));
+  pbuf_ref(cseg->p);
+  return cseg;
+}
+#endif
+
+#if LWIP_CALLBACK_API
+/**
+ * Default receive callback that is called if the user didn't register
+ * a recv callback for the pcb.
+ */
+static err_t
+tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
+{
+  arg = arg;
+  if (p != NULL) {
+    pbuf_free(p);
+  } else if (err == ERR_OK) {
+    return tcp_close(pcb);
+  }
+  return ERR_OK;
+}
+#endif /* LWIP_CALLBACK_API */
+
+/**
+ * Kills the oldest active connection that has lower priority than prio.
+ *
+ * @param prio minimum priority
+ */
+static void
+tcp_kill_prio(u8_t prio)
+{
+  struct tcp_pcb *pcb, *inactive;
+  u32_t inactivity;
+  u8_t mprio;
+
+
+  mprio = TCP_PRIO_MAX;
+
+  /* We kill the oldest active connection that has lower priority than prio. */
+  inactivity = 0;
+  inactive = NULL;
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->prio <= prio &&
+       pcb->prio <= mprio &&
+       (u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
+      inactivity = tcp_ticks - pcb->tmr;
+      inactive = pcb;
+      mprio = pcb->prio;
+    }
+  }
+  if (inactive != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n",
+           (void *)inactive, inactivity));
+    tcp_abort(inactive);
+  }
+}
+
+/**
+ * Kills the oldest connection that is in TIME_WAIT state.
+ * Called from tcp_alloc() if no more connections are available.
+ */
+static void
+tcp_kill_timewait(void)
+{
+  struct tcp_pcb *pcb, *inactive;
+  u32_t inactivity;
+
+  inactivity = 0;
+  inactive = NULL;
+  /* Go through the list of TIME_WAIT pcbs and get the oldest pcb. */
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
+      inactivity = tcp_ticks - pcb->tmr;
+      inactive = pcb;
+    }
+  }
+  if (inactive != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n",
+           (void *)inactive, inactivity));
+    tcp_abort(inactive);
+  }
+}
+
+/**
+ * Allocate a new tcp_pcb structure.
+ *
+ * @param prio priority for the new pcb
+ * @return a new tcp_pcb that initially is in state CLOSED
+ */
+struct tcp_pcb *
+tcp_alloc(u8_t prio)
+{
+  struct tcp_pcb *pcb;
+  u32_t iss;
+
+  pcb = memp_malloc(MEMP_TCP_PCB);
+  if (pcb == NULL) {
+    /* Try killing oldest connection in TIME-WAIT. */
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n"));
+    tcp_kill_timewait();
+    /* Try to allocate a tcp_pcb again. */
+    pcb = memp_malloc(MEMP_TCP_PCB);
+    if (pcb == NULL) {
+      /* Try killing active connections with lower priority than the new one. */
+      tcp_kill_prio(prio);
+      /* Try to allocate a tcp_pcb again. */
+      pcb = memp_malloc(MEMP_TCP_PCB);
+    }
+  }
+  if (pcb != NULL) {
+    memset(pcb, 0, sizeof(struct tcp_pcb));
+    pcb->prio = TCP_PRIO_NORMAL;
+    pcb->snd_buf = TCP_SND_BUF;
+    pcb->snd_queuelen = 0;
+    pcb->rcv_wnd = TCP_WND;
+    pcb->rcv_ann_wnd = TCP_WND;
+    pcb->tos = 0;
+    pcb->ttl = TCP_TTL;
+    /* The send MSS is updated when an MSS option is received. */
+    pcb->mss = (TCP_MSS > 536) ? 536 : TCP_MSS;
+    pcb->rto = 3000 / TCP_SLOW_INTERVAL;
+    pcb->sa = 0;
+    pcb->sv = 3000 / TCP_SLOW_INTERVAL;
+    pcb->rtime = -1;
+    pcb->cwnd = 1;
+    iss = tcp_next_iss();
+    pcb->snd_wl2 = iss;
+    pcb->snd_nxt = iss;
+    pcb->snd_max = iss;
+    pcb->lastack = iss;
+    pcb->snd_lbb = iss;
+    pcb->tmr = tcp_ticks;
+
+    pcb->polltmr = 0;
+
+#if LWIP_CALLBACK_API
+    pcb->recv = tcp_recv_null;
+#endif /* LWIP_CALLBACK_API */
+
+    /* Init KEEPALIVE timer */
+    pcb->keep_idle  = TCP_KEEPIDLE_DEFAULT;
+
+#if LWIP_TCP_KEEPALIVE
+    pcb->keep_intvl = TCP_KEEPINTVL_DEFAULT;
+    pcb->keep_cnt   = TCP_KEEPCNT_DEFAULT;
+#endif /* LWIP_TCP_KEEPALIVE */
+
+    pcb->keep_cnt_sent = 0;
+  }
+  return pcb;
+}
+
+/**
+ * Creates a new TCP protocol control block but doesn't place it on
+ * any of the TCP PCB lists.
+ * The pcb is not put on any list until binding using tcp_bind().
+ *
+ * @internal: Maybe there should be a idle TCP PCB list where these
+ * PCBs are put on. Port reservation using tcp_bind() is implemented but
+ * allocated pcbs that are not bound can't be killed automatically if wanting
+ * to allocate a pcb with higher prio (@see tcp_kill_prio())
+ *
+ * @return a new tcp_pcb that initially is in state CLOSED
+ */
+struct tcp_pcb *
+tcp_new(void)
+{
+  return tcp_alloc(TCP_PRIO_NORMAL);
+}
+
+/**
+ * Used to specify the argument that should be passed callback
+ * functions.
+ *
+ * @param pcb tcp_pcb to set the callback argument
+ * @param arg void pointer argument to pass to callback functions
+ */
+void
+tcp_arg(struct tcp_pcb *pcb, void *arg)
+{
+  pcb->callback_arg = arg;
+}
+#if LWIP_CALLBACK_API
+
+/**
+ * Used to specify the function that should be called when a TCP
+ * connection receives data.
+ *
+ * @param pcb tcp_pcb to set the recv callback
+ * @param recv callback function to call for this pcb when data is received
+ */
+void
+tcp_recv(struct tcp_pcb *pcb,
+   err_t (* recv)(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err))
+{
+  pcb->recv = recv;
+}
+
+/**
+ * Used to specify the function that should be called when TCP data
+ * has been successfully delivered to the remote host.
+ *
+ * @param pcb tcp_pcb to set the sent callback
+ * @param sent callback function to call for this pcb when data is successfully sent
+ */
+void
+tcp_sent(struct tcp_pcb *pcb,
+   err_t (* sent)(void *arg, struct tcp_pcb *tpcb, u16_t len))
+{
+  pcb->sent = sent;
+}
+
+/**
+ * Used to specify the function that should be called when a fatal error
+ * has occured on the connection.
+ *
+ * @param pcb tcp_pcb to set the err callback
+ * @param errf callback function to call for this pcb when a fatal error
+ *        has occured on the connection
+ */
+void
+tcp_err(struct tcp_pcb *pcb,
+   void (* errf)(void *arg, err_t err))
+{
+  pcb->errf = errf;
+}
+
+/**
+ * Used for specifying the function that should be called when a
+ * LISTENing connection has been connected to another host.
+ *
+ * @param pcb tcp_pcb to set the accept callback
+ * @param accept callback function to call for this pcb when LISTENing
+ *        connection has been connected to another host
+ */
+void
+tcp_accept(struct tcp_pcb *pcb,
+     err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err))
+{
+  ((struct tcp_pcb_listen *)pcb)->accept = accept;
+}
+#endif /* LWIP_CALLBACK_API */
+
+
+/**
+ * Used to specify the function that should be called periodically
+ * from TCP. The interval is specified in terms of the TCP coarse
+ * timer interval, which is called twice a second.
+ *
+ */
+void
+tcp_poll(struct tcp_pcb *pcb,
+   err_t (* poll)(void *arg, struct tcp_pcb *tpcb), u8_t interval)
+{
+#if LWIP_CALLBACK_API
+  pcb->poll = poll;
+#endif /* LWIP_CALLBACK_API */
+  pcb->pollinterval = interval;
+}
+
+/**
+ * Purges a TCP PCB. Removes any buffered data and frees the buffer memory
+ * (pcb->ooseq, pcb->unsent and pcb->unacked are freed).
+ *
+ * @param pcb tcp_pcb to purge. The pcb itself is not deallocated!
+ */
+void
+tcp_pcb_purge(struct tcp_pcb *pcb)
+{
+  if (pcb->state != CLOSED &&
+     pcb->state != TIME_WAIT &&
+     pcb->state != LISTEN) {
+
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n"));
+
+    if (pcb->refused_data != NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->refused_data\n"));
+      pbuf_free(pcb->refused_data);
+      pcb->refused_data = NULL;
+    }
+    if (pcb->unsent != NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: not all data sent\n"));
+    }
+    if (pcb->unacked != NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n"));
+    }
+#if TCP_QUEUE_OOSEQ /* LW */
+    if (pcb->ooseq != NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n"));
+    }
+
+    /* Stop the retransmission timer as it will expect data on unacked
+       queue if it fires */
+    pcb->rtime = -1;
+
+    tcp_segs_free(pcb->ooseq);
+    pcb->ooseq = NULL;
+#endif /* TCP_QUEUE_OOSEQ */
+    tcp_segs_free(pcb->unsent);
+    tcp_segs_free(pcb->unacked);
+    pcb->unacked = pcb->unsent = NULL;
+  }
+}
+
+/**
+ * Purges the PCB and removes it from a PCB list. Any delayed ACKs are sent first.
+ *
+ * @param pcblist PCB list to purge.
+ * @param pcb tcp_pcb to purge. The pcb itself is also deallocated!
+ */
+void
+tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb)
+{
+  TCP_RMV(pcblist, pcb);
+
+  tcp_pcb_purge(pcb);
+
+  /* if there is an outstanding delayed ACKs, send it */
+  if (pcb->state != TIME_WAIT &&
+     pcb->state != LISTEN &&
+     pcb->flags & TF_ACK_DELAY) {
+    pcb->flags |= TF_ACK_NOW;
+    tcp_output(pcb);
+  }
+
+  if (pcb->state != LISTEN) {
+    LWIP_ASSERT("unsent segments leaking", pcb->unsent == NULL);
+    LWIP_ASSERT("unacked segments leaking", pcb->unacked == NULL);
+#if TCP_QUEUE_OOSEQ
+    LWIP_ASSERT("ooseq segments leaking", pcb->ooseq == NULL);
+#endif /* TCP_QUEUE_OOSEQ */
+  }
+
+  pcb->state = CLOSED;
+
+  LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane());
+}
+
+/**
+ * Calculates a new initial sequence number for new connections.
+ *
+ * @return u32_t pseudo random sequence number
+ */
+u32_t
+tcp_next_iss(void)
+{
+  static u32_t iss = 6510;
+
+  iss += tcp_ticks;       /* XXX */
+  return iss;
+}
+
+#if TCP_CALCULATE_EFF_SEND_MSS
+/**
+ * Calcluates the effective send mss that can be used for a specific IP address
+ * by using ip_route to determin the netif used to send to the address and
+ * calculating the minimum of TCP_MSS and that netif's mtu (if set).
+ */
+u16_t
+tcp_eff_send_mss(u16_t sendmss, struct ip_addr *addr)
+{
+  u16_t mss_s;
+  struct netif *outif;
+
+  outif = ip_route(addr);
+  if ((outif != NULL) && (outif->mtu != 0)) {
+    mss_s = outif->mtu - IP_HLEN - TCP_HLEN;
+    /* RFC 1122, chap 4.2.2.6:
+     * Eff.snd.MSS = min(SendMSS+20, MMS_S) - TCPhdrsize - IPoptionsize
+     * but we only send options with SYN and that is never filled with data! */
+    sendmss = LWIP_MIN(sendmss, mss_s);
+  }
+  return sendmss;
+}
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+
+#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
+/**
+ * Print a tcp header for debugging purposes.
+ *
+ * @param tcphdr pointer to a struct tcp_hdr
+ */
+void
+tcp_debug_print(struct tcp_hdr *tcphdr)
+{
+  LWIP_DEBUGF(TCP_DEBUG, ("TCP header:\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|    %5"U16_F"      |    %5"U16_F"      | (src port, dest port)\n",
+         ntohs(tcphdr->src), ntohs(tcphdr->dest)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|           %010"U32_F"          | (seq no)\n",
+          ntohl(tcphdr->seqno)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|           %010"U32_F"          | (ack no)\n",
+         ntohl(tcphdr->ackno)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("| %2"U16_F" |   |%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"|     %5"U16_F"     | (hdrlen, flags (",
+       TCPH_HDRLEN(tcphdr),
+         TCPH_FLAGS(tcphdr) >> 5 & 1,
+         TCPH_FLAGS(tcphdr) >> 4 & 1,
+         TCPH_FLAGS(tcphdr) >> 3 & 1,
+         TCPH_FLAGS(tcphdr) >> 2 & 1,
+         TCPH_FLAGS(tcphdr) >> 1 & 1,
+         TCPH_FLAGS(tcphdr) & 1,
+         ntohs(tcphdr->wnd)));
+  tcp_debug_print_flags(TCPH_FLAGS(tcphdr));
+  LWIP_DEBUGF(TCP_DEBUG, ("), win)\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|    0x%04"X16_F"     |     %5"U16_F"     | (chksum, urgp)\n",
+         ntohs(tcphdr->chksum), ntohs(tcphdr->urgp)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+}
+
+/**
+ * Print a tcp state for debugging purposes.
+ *
+ * @param s enum tcp_state to print
+ */
+void
+tcp_debug_print_state(enum tcp_state s)
+{
+  LWIP_DEBUGF(TCP_DEBUG, ("State: "));
+  switch (s) {
+  case CLOSED:
+    LWIP_DEBUGF(TCP_DEBUG, ("CLOSED\n"));
+    break;
+ case LISTEN:
+   LWIP_DEBUGF(TCP_DEBUG, ("LISTEN\n"));
+   break;
+  case SYN_SENT:
+    LWIP_DEBUGF(TCP_DEBUG, ("SYN_SENT\n"));
+    break;
+  case SYN_RCVD:
+    LWIP_DEBUGF(TCP_DEBUG, ("SYN_RCVD\n"));
+    break;
+  case ESTABLISHED:
+    LWIP_DEBUGF(TCP_DEBUG, ("ESTABLISHED\n"));
+    break;
+  case FIN_WAIT_1:
+    LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_1\n"));
+    break;
+  case FIN_WAIT_2:
+    LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_2\n"));
+    break;
+  case CLOSE_WAIT:
+    LWIP_DEBUGF(TCP_DEBUG, ("CLOSE_WAIT\n"));
+    break;
+  case CLOSING:
+    LWIP_DEBUGF(TCP_DEBUG, ("CLOSING\n"));
+    break;
+  case LAST_ACK:
+    LWIP_DEBUGF(TCP_DEBUG, ("LAST_ACK\n"));
+    break;
+  case TIME_WAIT:
+    LWIP_DEBUGF(TCP_DEBUG, ("TIME_WAIT\n"));
+   break;
+  }
+}
+
+/**
+ * Print tcp flags for debugging purposes.
+ *
+ * @param flags tcp flags, all active flags are printed
+ */
+void
+tcp_debug_print_flags(u8_t flags)
+{
+  if (flags & TCP_FIN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("FIN "));
+  }
+  if (flags & TCP_SYN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("SYN "));
+  }
+  if (flags & TCP_RST) {
+    LWIP_DEBUGF(TCP_DEBUG, ("RST "));
+  }
+  if (flags & TCP_PSH) {
+    LWIP_DEBUGF(TCP_DEBUG, ("PSH "));
+  }
+  if (flags & TCP_ACK) {
+    LWIP_DEBUGF(TCP_DEBUG, ("ACK "));
+  }
+  if (flags & TCP_URG) {
+    LWIP_DEBUGF(TCP_DEBUG, ("URG "));
+  }
+  if (flags & TCP_ECE) {
+    LWIP_DEBUGF(TCP_DEBUG, ("ECE "));
+  }
+  if (flags & TCP_CWR) {
+    LWIP_DEBUGF(TCP_DEBUG, ("CWR "));
+  }
+}
+
+/**
+ * Print all tcp_pcbs in every list for debugging purposes.
+ */
+void
+tcp_debug_print_pcbs(void)
+{
+  struct tcp_pcb *pcb;
+  LWIP_DEBUGF(TCP_DEBUG, ("Active PCB states:\n"));
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ",
+                       pcb->local_port, pcb->remote_port,
+                       pcb->snd_nxt, pcb->rcv_nxt));
+    tcp_debug_print_state(pcb->state);
+  }
+  LWIP_DEBUGF(TCP_DEBUG, ("Listen PCB states:\n"));
+  for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ",
+                       pcb->local_port, pcb->remote_port,
+                       pcb->snd_nxt, pcb->rcv_nxt));
+    tcp_debug_print_state(pcb->state);
+  }
+  LWIP_DEBUGF(TCP_DEBUG, ("TIME-WAIT PCB states:\n"));
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ",
+                       pcb->local_port, pcb->remote_port,
+                       pcb->snd_nxt, pcb->rcv_nxt));
+    tcp_debug_print_state(pcb->state);
+  }
+}
+
+/**
+ * Check state consistency of the tcp_pcb lists.
+ */
+s16_t
+tcp_pcbs_sane(void)
+{
+  struct tcp_pcb *pcb;
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != CLOSED", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != LISTEN", pcb->state != LISTEN);
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
+  }
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_ASSERT("tcp_pcbs_sane: tw pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+  }
+  return 1;
+}
+#endif /* TCP_DEBUG */
+
+#endif /* LWIP_TCP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/tcp_in.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/tcp_in.c
new file mode 100644
index 0000000..0f79b54
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/tcp_in.c
@@ -0,0 +1,1352 @@
+/**
+ * @file
+ * Transmission Control Protocol, incoming traffic
+ *
+ * The input processing functions of the TCP layer.
+ *
+ * These functions are generally called in the order (ip_input() ->)
+ * tcp_input() -> * tcp_process() -> tcp_receive() (-> application).
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/tcp.h"
+#include "lwip/def.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/inet.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+#include "arch/perf.h"
+
+/* These variables are global to all functions involved in the input
+   processing of TCP segments. They are set by the tcp_input()
+   function. */
+static struct tcp_seg inseg;
+static struct tcp_hdr *tcphdr;
+static struct ip_hdr *iphdr;
+static u32_t seqno, ackno;
+static u8_t flags;
+static u16_t tcplen;
+
+static u8_t recv_flags;
+static struct pbuf *recv_data;
+
+struct tcp_pcb *tcp_input_pcb;
+
+/* Forward declarations. */
+static err_t tcp_process(struct tcp_pcb *pcb);
+static u8_t tcp_receive(struct tcp_pcb *pcb);
+static void tcp_parseopt(struct tcp_pcb *pcb);
+
+static err_t tcp_listen_input(struct tcp_pcb_listen *pcb);
+static err_t tcp_timewait_input(struct tcp_pcb *pcb);
+
+/**
+ * The initial input processing of TCP. It verifies the TCP header, demultiplexes
+ * the segment between the PCBs and passes it on to tcp_process(), which implements
+ * the TCP finite state machine. This function is called by the IP layer (in
+ * ip_input()).
+ *
+ * @param p received TCP segment to process (p->payload pointing to the IP header)
+ * @param inp network interface on which this segment was received
+ */
+void
+tcp_input(struct pbuf *p, struct netif *inp)
+{
+  struct tcp_pcb *pcb, *prev;
+  struct tcp_pcb_listen *lpcb;
+  u8_t hdrlen;
+  err_t err;
+
+  PERF_START;
+
+  TCP_STATS_INC(tcp.recv);
+  snmp_inc_tcpinsegs();
+
+  iphdr = p->payload;
+  tcphdr = (struct tcp_hdr *)((u8_t *)p->payload + IPH_HL(iphdr) * 4);
+
+#if TCP_INPUT_DEBUG
+  tcp_debug_print(tcphdr);
+#endif
+
+  /* remove header from payload */
+  if (pbuf_header(p, -((s16_t)(IPH_HL(iphdr) * 4))) || (p->tot_len < sizeof(struct tcp_hdr))) {
+    /* drop short packets */
+    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet (%"U16_F" bytes) discarded\n", p->tot_len));
+    TCP_STATS_INC(tcp.lenerr);
+    TCP_STATS_INC(tcp.drop);
+    snmp_inc_tcpinerrs();
+    pbuf_free(p);
+    return;
+  }
+
+  /* Don't even process incoming broadcasts/multicasts. */
+  if (ip_addr_isbroadcast(&(iphdr->dest), inp) ||
+      ip_addr_ismulticast(&(iphdr->dest))) {
+    TCP_STATS_INC(tcp.proterr);
+    TCP_STATS_INC(tcp.drop);
+    snmp_inc_tcpinerrs();
+    pbuf_free(p);
+    return;
+  }
+
+#if CHECKSUM_CHECK_TCP
+  /* Verify TCP checksum. */
+  if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
+      (struct ip_addr *)&(iphdr->dest),
+      IP_PROTO_TCP, p->tot_len) != 0) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packet discarded due to failing checksum 0x%04"X16_F"\n",
+        inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), (struct ip_addr *)&(iphdr->dest),
+      IP_PROTO_TCP, p->tot_len)));
+#if TCP_DEBUG
+    tcp_debug_print(tcphdr);
+#endif /* TCP_DEBUG */
+    TCP_STATS_INC(tcp.chkerr);
+    TCP_STATS_INC(tcp.drop);
+    snmp_inc_tcpinerrs();
+    pbuf_free(p);
+    return;
+  }
+#endif
+
+  /* Move the payload pointer in the pbuf so that it points to the
+     TCP data instead of the TCP header. */
+  hdrlen = TCPH_HDRLEN(tcphdr);
+  if(pbuf_header(p, -(hdrlen * 4))){
+    /* drop short packets */
+    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet\n"));
+    TCP_STATS_INC(tcp.lenerr);
+    TCP_STATS_INC(tcp.drop);
+    snmp_inc_tcpinerrs();
+    pbuf_free(p);
+    return;
+  }
+
+  /* Convert fields in TCP header to host byte order. */
+  tcphdr->src = ntohs(tcphdr->src);
+  tcphdr->dest = ntohs(tcphdr->dest);
+  seqno = tcphdr->seqno = ntohl(tcphdr->seqno);
+  ackno = tcphdr->ackno = ntohl(tcphdr->ackno);
+  tcphdr->wnd = ntohs(tcphdr->wnd);
+
+  flags = TCPH_FLAGS(tcphdr) & TCP_FLAGS;
+  tcplen = p->tot_len + ((flags & TCP_FIN || flags & TCP_SYN)? 1: 0);
+
+  /* Demultiplex an incoming segment. First, we check if it is destined
+     for an active connection. */
+  prev = NULL;
+
+
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
+    LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN);
+    if (pcb->remote_port == tcphdr->src &&
+       pcb->local_port == tcphdr->dest &&
+       ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) &&
+       ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) {
+
+      /* Move this PCB to the front of the list so that subsequent
+         lookups will be faster (we exploit locality in TCP segment
+         arrivals). */
+      LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb);
+      if (prev != NULL) {
+        prev->next = pcb->next;
+        pcb->next = tcp_active_pcbs;
+        tcp_active_pcbs = pcb;
+      }
+      LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb);
+      break;
+    }
+    prev = pcb;
+  }
+
+  if (pcb == NULL) {
+    /* If it did not go to an active connection, we check the connections
+       in the TIME-WAIT state. */
+    for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+      LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+      if (pcb->remote_port == tcphdr->src &&
+         pcb->local_port == tcphdr->dest &&
+         ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) &&
+         ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) {
+        /* We don't really care enough to move this PCB to the front
+           of the list since we are not very likely to receive that
+           many segments for connections in TIME-WAIT. */
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for TIME_WAITing connection.\n"));
+        tcp_timewait_input(pcb);
+        pbuf_free(p);
+        return;
+      }
+    }
+
+  /* Finally, if we still did not get a match, we check all PCBs that
+     are LISTENing for incoming connections. */
+    prev = NULL;
+    for(lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+      if ((ip_addr_isany(&(lpcb->local_ip)) ||
+        ip_addr_cmp(&(lpcb->local_ip), &(iphdr->dest))) &&
+        lpcb->local_port == tcphdr->dest) {
+        /* Move this PCB to the front of the list so that subsequent
+           lookups will be faster (we exploit locality in TCP segment
+           arrivals). */
+        if (prev != NULL) {
+          ((struct tcp_pcb_listen *)prev)->next = lpcb->next;
+                /* our successor is the remainder of the listening list */
+          lpcb->next = tcp_listen_pcbs.listen_pcbs;
+                /* put this listening pcb at the head of the listening list */
+          tcp_listen_pcbs.listen_pcbs = lpcb;
+        }
+
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for LISTENing connection.\n"));
+        tcp_listen_input(lpcb);
+        pbuf_free(p);
+        return;
+      }
+      prev = (struct tcp_pcb *)lpcb;
+    }
+  }
+
+#if TCP_INPUT_DEBUG
+  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("+-+-+-+-+-+-+-+-+-+-+-+-+-+- tcp_input: flags "));
+  tcp_debug_print_flags(TCPH_FLAGS(tcphdr));
+  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n"));
+#endif /* TCP_INPUT_DEBUG */
+
+
+  if (pcb != NULL) {
+    /* The incoming segment belongs to a connection. */
+#if TCP_INPUT_DEBUG
+#if TCP_DEBUG
+    tcp_debug_print_state(pcb->state);
+#endif /* TCP_DEBUG */
+#endif /* TCP_INPUT_DEBUG */
+
+    /* Set up a tcp_seg structure. */
+    inseg.next = NULL;
+    inseg.len = p->tot_len;
+    inseg.dataptr = p->payload;
+    inseg.p = p;
+    inseg.tcphdr = tcphdr;
+
+    recv_data = NULL;
+    recv_flags = 0;
+
+    /* If there is data which was previously "refused" by upper layer */
+    if (pcb->refused_data != NULL) {
+      /* Notify again application with data previously received. */
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: notify kept packet\n"));
+      TCP_EVENT_RECV(pcb, pcb->refused_data, ERR_OK, err);
+      if (err == ERR_OK) {
+        pcb->refused_data = NULL;
+      } else {
+        /* drop incoming packets, because pcb is "full" */
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: drop incoming packets, because pcb is \"full\"\n"));
+        TCP_STATS_INC(tcp.drop);
+        snmp_inc_tcpinerrs();
+        pbuf_free(p);
+        return;
+      }
+    }
+
+    tcp_input_pcb = pcb;
+    err = tcp_process(pcb);
+    tcp_input_pcb = NULL;
+    /* A return value of ERR_ABRT means that tcp_abort() was called
+       and that the pcb has been freed. If so, we don't do anything. */
+    if (err != ERR_ABRT) {
+      if (recv_flags & TF_RESET) {
+        /* TF_RESET means that the connection was reset by the other
+           end. We then call the error callback to inform the
+           application that the connection is dead before we
+           deallocate the PCB. */
+        TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_RST);
+        tcp_pcb_remove(&tcp_active_pcbs, pcb);
+        memp_free(MEMP_TCP_PCB, pcb);
+      } else if (recv_flags & TF_CLOSED) {
+        /* The connection has been closed and we will deallocate the
+           PCB. */
+        tcp_pcb_remove(&tcp_active_pcbs, pcb);
+        memp_free(MEMP_TCP_PCB, pcb);
+      } else {
+        err = ERR_OK;
+        /* If the application has registered a "sent" function to be
+           called when new send buffer space is available, we call it
+           now. */
+        if (pcb->acked > 0) {
+          TCP_EVENT_SENT(pcb, pcb->acked, err);
+        }
+
+        if (recv_data != NULL) {
+          if(flags & TCP_PSH) {
+            recv_data->flags |= PBUF_FLAG_PUSH;
+          }
+
+          /* Notify application that data has been received. */
+          TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err);
+
+          /* If the upper layer can't receive this data, store it */
+          if (err != ERR_OK) {
+            pcb->refused_data = recv_data;
+            LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: keep incoming packet, because pcb is \"full\"\n"));
+          }
+        }
+
+        /* If a FIN segment was received, we call the callback
+           function with a NULL buffer to indicate EOF. */
+        if (recv_flags & TF_GOT_FIN) {
+          TCP_EVENT_RECV(pcb, NULL, ERR_OK, err);
+        }
+
+        /* If there were no errors, we try to send something out. */
+        if (err == ERR_OK) {
+          tcp_output(pcb);
+        }
+      }
+    }
+
+
+    /* give up our reference to inseg.p */
+    if (inseg.p != NULL)
+    {
+      pbuf_free(inseg.p);
+      inseg.p = NULL;
+    }
+#if TCP_INPUT_DEBUG
+#if TCP_DEBUG
+    tcp_debug_print_state(pcb->state);
+#endif /* TCP_DEBUG */
+#endif /* TCP_INPUT_DEBUG */
+
+  } else {
+
+    /* If no matching PCB was found, send a TCP RST (reset) to the
+       sender. */
+    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_input: no PCB match found, resetting.\n"));
+    if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) {
+      TCP_STATS_INC(tcp.proterr);
+      TCP_STATS_INC(tcp.drop);
+      tcp_rst(ackno, seqno + tcplen,
+        &(iphdr->dest), &(iphdr->src),
+        tcphdr->dest, tcphdr->src);
+    }
+    pbuf_free(p);
+  }
+
+  LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane());
+  PERF_STOP("tcp_input");
+}
+
+/**
+ * Called by tcp_input() when a segment arrives for a listening
+ * connection (from tcp_input()).
+ *
+ * @param pcb the tcp_pcb_listen for which a segment arrived
+ * @return ERR_OK if the segment was processed
+ *         another err_t on error
+ *
+ * @note the return value is not (yet?) used in tcp_input()
+ * @note the segment which arrived is saved in global variables, therefore only the pcb
+ *       involved is passed as a parameter to this function
+ */
+static err_t
+tcp_listen_input(struct tcp_pcb_listen *pcb)
+{
+  struct tcp_pcb *npcb;
+  u32_t optdata;
+
+  /* In the LISTEN state, we check for incoming SYN segments,
+     creates a new PCB, and responds with a SYN|ACK. */
+  if (flags & TCP_ACK) {
+    /* For incoming segments with the ACK flag set, respond with a
+       RST. */
+    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n"));
+    tcp_rst(ackno + 1, seqno + tcplen,
+      &(iphdr->dest), &(iphdr->src),
+      tcphdr->dest, tcphdr->src);
+  } else if (flags & TCP_SYN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("TCP connection request %"U16_F" -> %"U16_F".\n", tcphdr->src, tcphdr->dest));
+#if TCP_LISTEN_BACKLOG
+    if (pcb->accepts_pending >= pcb->backlog) {
+      return ERR_ABRT;
+    }
+#endif /* TCP_LISTEN_BACKLOG */
+    npcb = tcp_alloc(pcb->prio);
+    /* If a new PCB could not be created (probably due to lack of memory),
+       we don't do anything, but rely on the sender will retransmit the
+       SYN at a time when we have more memory available. */
+    if (npcb == NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: could not allocate PCB\n"));
+      TCP_STATS_INC(tcp.memerr);
+      return ERR_MEM;
+    }
+#if TCP_LISTEN_BACKLOG
+    pcb->accepts_pending++;
+#endif /* TCP_LISTEN_BACKLOG */
+    /* Set up the new PCB. */
+    ip_addr_set(&(npcb->local_ip), &(iphdr->dest));
+    npcb->local_port = pcb->local_port;
+    ip_addr_set(&(npcb->remote_ip), &(iphdr->src));
+    npcb->remote_port = tcphdr->src;
+    npcb->state = SYN_RCVD;
+    npcb->rcv_nxt = seqno + 1;
+    npcb->snd_wnd = tcphdr->wnd;
+    npcb->ssthresh = npcb->snd_wnd;
+    npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */
+    npcb->callback_arg = pcb->callback_arg;
+#if LWIP_CALLBACK_API
+    npcb->accept = pcb->accept;
+#endif /* LWIP_CALLBACK_API */
+    /* inherit socket options */
+    npcb->so_options = pcb->so_options & (SOF_DEBUG|SOF_DONTROUTE|SOF_KEEPALIVE|SOF_OOBINLINE|SOF_LINGER);
+    /* Register the new PCB so that we can begin receiving segments
+       for it. */
+    TCP_REG(&tcp_active_pcbs, npcb);
+
+    /* Parse any options in the SYN. */
+    tcp_parseopt(npcb);
+#if TCP_CALCULATE_EFF_SEND_MSS
+    npcb->mss = tcp_eff_send_mss(npcb->mss, &(npcb->remote_ip));
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+
+    snmp_inc_tcppassiveopens();
+
+    /* Build an MSS option. */
+    optdata = TCP_BUILD_MSS_OPTION();
+    /* Send a SYN|ACK together with the MSS option. */
+    tcp_enqueue(npcb, NULL, 0, TCP_SYN | TCP_ACK, 0, (u8_t *)&optdata, 4);
+    return tcp_output(npcb);
+  }
+  return ERR_OK;
+}
+
+/**
+ * Called by tcp_input() when a segment arrives for a connection in
+ * TIME_WAIT.
+ *
+ * @param pcb the tcp_pcb for which a segment arrived
+ *
+ * @note the segment which arrived is saved in global variables, therefore only the pcb
+ *       involved is passed as a parameter to this function
+ */
+static err_t
+tcp_timewait_input(struct tcp_pcb *pcb)
+{
+  if (TCP_SEQ_GT(seqno + tcplen, pcb->rcv_nxt)) {
+    pcb->rcv_nxt = seqno + tcplen;
+  }
+  if (tcplen > 0) {
+    tcp_ack_now(pcb);
+  }
+  return tcp_output(pcb);
+}
+
+/**
+ * Implements the TCP state machine. Called by tcp_input. In some
+ * states tcp_receive() is called to receive data. The tcp_seg
+ * argument will be freed by the caller (tcp_input()) unless the
+ * recv_data pointer in the pcb is set.
+ *
+ * @param pcb the tcp_pcb for which a segment arrived
+ *
+ * @note the segment which arrived is saved in global variables, therefore only the pcb
+ *       involved is passed as a parameter to this function
+ */
+static err_t
+tcp_process(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *rseg;
+  u8_t acceptable = 0;
+  err_t err;
+  u8_t accepted_inseq;
+
+  err = ERR_OK;
+
+  /* Process incoming RST segments. */
+  if (flags & TCP_RST) {
+    /* First, determine if the reset is acceptable. */
+    if (pcb->state == SYN_SENT) {
+      if (ackno == pcb->snd_nxt) {
+        acceptable = 1;
+      }
+    } else {
+      if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt,
+                          pcb->rcv_nxt+pcb->rcv_ann_wnd)) {
+        acceptable = 1;
+      }
+    }
+
+    if (acceptable) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n"));
+      LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED);
+      recv_flags = TF_RESET;
+      pcb->flags &= ~TF_ACK_DELAY;
+      return ERR_RST;
+    } else {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
+       seqno, pcb->rcv_nxt));
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
+       seqno, pcb->rcv_nxt));
+      return ERR_OK;
+    }
+  }
+
+  /* Update the PCB (in)activity timer. */
+  pcb->tmr = tcp_ticks;
+  pcb->keep_cnt_sent = 0;
+
+  /* Do different things depending on the TCP state. */
+  switch (pcb->state) {
+  case SYN_SENT:
+    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno,
+     pcb->snd_nxt, ntohl(pcb->unacked->tcphdr->seqno)));
+    /* received SYN ACK with expected sequence number? */
+    if ((flags & TCP_ACK) && (flags & TCP_SYN)
+        && ackno == ntohl(pcb->unacked->tcphdr->seqno) + 1) {
+      pcb->snd_buf++;
+      pcb->rcv_nxt = seqno + 1;
+      pcb->lastack = ackno;
+      pcb->snd_wnd = tcphdr->wnd;
+      pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */
+      pcb->state = ESTABLISHED;
+
+      /* Parse any options in the SYNACK before using pcb->mss since that
+       * can be changed by the received options! */
+      tcp_parseopt(pcb);
+#if TCP_CALCULATE_EFF_SEND_MSS
+      pcb->mss = tcp_eff_send_mss(pcb->mss, &(pcb->remote_ip));
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+
+      /* Set ssthresh again after changing pcb->mss (already set in tcp_connect
+       * but for the default value of pcb->mss) */
+      pcb->ssthresh = pcb->mss * 10;
+
+      pcb->cwnd = ((pcb->cwnd == 1) ? (pcb->mss * 2) : pcb->mss);
+      LWIP_ASSERT("pcb->snd_queuelen > 0", (pcb->snd_queuelen > 0));
+      --pcb->snd_queuelen;
+      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"U16_F"\n", (u16_t)pcb->snd_queuelen));
+      rseg = pcb->unacked;
+      pcb->unacked = rseg->next;
+
+      /* If there's nothing left to acknowledge, stop the retransmit
+         timer, otherwise reset it to start again */
+      if(pcb->unacked == NULL)
+        pcb->rtime = -1;
+      else {
+        pcb->rtime = 0;
+        pcb->nrtx = 0;
+      }
+
+      tcp_seg_free(rseg);
+
+      /* Call the user specified function to call when sucessfully
+       * connected. */
+      TCP_EVENT_CONNECTED(pcb, ERR_OK, err);
+      tcp_ack_now(pcb);
+    }
+    /* received ACK? possibly a half-open connection */
+    else if (flags & TCP_ACK) {
+      /* send a RST to bring the other side in a non-synchronized state. */
+      tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src),
+        tcphdr->dest, tcphdr->src);
+    }
+    break;
+  case SYN_RCVD:
+    if (flags & TCP_ACK &&
+       !(flags & TCP_RST)) {
+      /* expected ACK number? */
+      if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)) {
+        u16_t old_cwnd;
+        pcb->state = ESTABLISHED;
+        LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+#if LWIP_CALLBACK_API
+        LWIP_ASSERT("pcb->accept != NULL", pcb->accept != NULL);
+#endif
+        /* Call the accept function. */
+        TCP_EVENT_ACCEPT(pcb, ERR_OK, err);
+        if (err != ERR_OK) {
+          /* If the accept function returns with an error, we abort
+           * the connection. */
+          tcp_abort(pcb);
+          return ERR_ABRT;
+        }
+        old_cwnd = pcb->cwnd;
+        /* If there was any data contained within this ACK,
+         * we'd better pass it on to the application as well. */
+        accepted_inseq = tcp_receive(pcb);
+
+        pcb->cwnd = ((old_cwnd == 1) ? (pcb->mss * 2) : pcb->mss);
+
+        if ((flags & TCP_FIN) && accepted_inseq) {
+          tcp_ack_now(pcb);
+          pcb->state = CLOSE_WAIT;
+        }
+      }
+      /* incorrect ACK number */
+      else {
+        /* send RST */
+        tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src),
+                tcphdr->dest, tcphdr->src);
+      }
+    }
+    break;
+  case CLOSE_WAIT:
+    /* FALLTHROUGH */
+  case ESTABLISHED:
+    accepted_inseq = tcp_receive(pcb);
+    if ((flags & TCP_FIN) && accepted_inseq) { /* passive close */
+      tcp_ack_now(pcb);
+      pcb->state = CLOSE_WAIT;
+    }
+    break;
+  case FIN_WAIT_1:
+    tcp_receive(pcb);
+    if (flags & TCP_FIN) {
+      if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+        LWIP_DEBUGF(TCP_DEBUG,
+          ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+        tcp_ack_now(pcb);
+        tcp_pcb_purge(pcb);
+        TCP_RMV(&tcp_active_pcbs, pcb);
+        pcb->state = TIME_WAIT;
+        TCP_REG(&tcp_tw_pcbs, pcb);
+      } else {
+        tcp_ack_now(pcb);
+        pcb->state = CLOSING;
+      }
+    } else if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+      pcb->state = FIN_WAIT_2;
+    }
+    break;
+  case FIN_WAIT_2:
+    tcp_receive(pcb);
+    if (flags & TCP_FIN) {
+      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+      tcp_ack_now(pcb);
+      tcp_pcb_purge(pcb);
+      TCP_RMV(&tcp_active_pcbs, pcb);
+      pcb->state = TIME_WAIT;
+      TCP_REG(&tcp_tw_pcbs, pcb);
+    }
+    break;
+  case CLOSING:
+    tcp_receive(pcb);
+    if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+      tcp_ack_now(pcb);
+      tcp_pcb_purge(pcb);
+      TCP_RMV(&tcp_active_pcbs, pcb);
+      pcb->state = TIME_WAIT;
+      TCP_REG(&tcp_tw_pcbs, pcb);
+    }
+    break;
+  case LAST_ACK:
+    tcp_receive(pcb);
+    if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+      /* bugfix #21699: don't set pcb->state to CLOSED here or we risk leaking segments */
+      recv_flags = TF_CLOSED;
+    }
+    break;
+  default:
+    break;
+  }
+  return ERR_OK;
+}
+
+/**
+ * Called by tcp_process. Checks if the given segment is an ACK for outstanding
+ * data, and if so frees the memory of the buffered data. Next, is places the
+ * segment on any of the receive queues (pcb->recved or pcb->ooseq). If the segment
+ * is buffered, the pbuf is referenced by pbuf_ref so that it will not be freed until
+ * i it has been removed from the buffer.
+ *
+ * If the incoming segment constitutes an ACK for a segment that was used for RTT
+ * estimation, the RTT is estimated here as well.
+ *
+ * Called from tcp_process().
+ *
+ * @return 1 if the incoming segment is the next in sequence, 0 if not
+ */
+static u8_t
+tcp_receive(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *next;
+#if TCP_QUEUE_OOSEQ
+  struct tcp_seg *prev, *cseg;
+#endif
+  struct pbuf *p;
+  s32_t off;
+  s16_t m;
+  u32_t right_wnd_edge;
+  u16_t new_tot_len;
+  u8_t accepted_inseq = 0;
+
+  if (flags & TCP_ACK) {
+    right_wnd_edge = pcb->snd_wnd + pcb->snd_wl1;
+
+    /* Update window. */
+    if (TCP_SEQ_LT(pcb->snd_wl1, seqno) ||
+       (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
+       (pcb->snd_wl2 == ackno && tcphdr->wnd > pcb->snd_wnd)) {
+      pcb->snd_wnd = tcphdr->wnd;
+      pcb->snd_wl1 = seqno;
+      pcb->snd_wl2 = ackno;
+      if (pcb->snd_wnd > 0 && pcb->persist_backoff > 0) {
+          pcb->persist_backoff = 0;
+      }
+      LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: window update %"U16_F"\n", pcb->snd_wnd));
+#if TCP_WND_DEBUG
+    } else {
+      if (pcb->snd_wnd != tcphdr->wnd) {
+        LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: no window update lastack %"U32_F" snd_max %"U32_F" ackno %"U32_F" wl1 %"U32_F" seqno %"U32_F" wl2 %"U32_F"\n",
+                               pcb->lastack, pcb->snd_max, ackno, pcb->snd_wl1, seqno, pcb->snd_wl2));
+      }
+#endif /* TCP_WND_DEBUG */
+    }
+
+    if (pcb->lastack == ackno) {
+      pcb->acked = 0;
+
+      if (pcb->snd_wl1 + pcb->snd_wnd == right_wnd_edge){
+        ++pcb->dupacks;
+        if (pcb->dupacks >= 3 && pcb->unacked != NULL) {
+          if (!(pcb->flags & TF_INFR)) {
+            /* This is fast retransmit. Retransmit the first unacked segment. */
+            LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupacks %"U16_F" (%"U32_F"), fast retransmit %"U32_F"\n",
+                                       (u16_t)pcb->dupacks, pcb->lastack,
+                                       ntohl(pcb->unacked->tcphdr->seqno)));
+            tcp_rexmit(pcb);
+            /* Set ssthresh to max (FlightSize / 2, 2*SMSS) */
+            /*pcb->ssthresh = LWIP_MAX((pcb->snd_max -
+                                      pcb->lastack) / 2,
+                                      2 * pcb->mss);*/
+            /* Set ssthresh to half of the minimum of the current cwnd and the advertised window */
+            if (pcb->cwnd > pcb->snd_wnd)
+              pcb->ssthresh = pcb->snd_wnd / 2;
+            else
+              pcb->ssthresh = pcb->cwnd / 2;
+
+            /* The minimum value for ssthresh should be 2 MSS */
+            if (pcb->ssthresh < 2*pcb->mss) {
+              LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: The minimum value for ssthresh %"U16_F" should be min 2 mss %"U16_F"...\n", pcb->ssthresh, 2*pcb->mss));
+              pcb->ssthresh = 2*pcb->mss;
+            }
+
+            pcb->cwnd = pcb->ssthresh + 3 * pcb->mss;
+            pcb->flags |= TF_INFR;
+          } else {
+            /* Inflate the congestion window, but not if it means that
+               the value overflows. */
+            if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) {
+              pcb->cwnd += pcb->mss;
+            }
+          }
+        }
+      } else {
+        LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupack averted %"U32_F" %"U32_F"\n",
+                                   pcb->snd_wl1 + pcb->snd_wnd, right_wnd_edge));
+      }
+    } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_max)){
+      /* We come here when the ACK acknowledges new data. */
+
+      /* Reset the "IN Fast Retransmit" flag, since we are no longer
+         in fast retransmit. Also reset the congestion window to the
+         slow start threshold. */
+      if (pcb->flags & TF_INFR) {
+        pcb->flags &= ~TF_INFR;
+        pcb->cwnd = pcb->ssthresh;
+      }
+
+      /* Reset the number of retransmissions. */
+      pcb->nrtx = 0;
+
+      /* Reset the retransmission time-out. */
+      pcb->rto = (pcb->sa >> 3) + pcb->sv;
+
+      /* Update the send buffer space. Diff between the two can never exceed 64K? */
+      pcb->acked = (u16_t)(ackno - pcb->lastack);
+
+      pcb->snd_buf += pcb->acked;
+
+      /* Reset the fast retransmit variables. */
+      pcb->dupacks = 0;
+      pcb->lastack = ackno;
+
+      /* Update the congestion control variables (cwnd and
+         ssthresh). */
+      if (pcb->state >= ESTABLISHED) {
+        if (pcb->cwnd < pcb->ssthresh) {
+          if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) {
+            pcb->cwnd += pcb->mss;
+          }
+          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"U16_F"\n", pcb->cwnd));
+        } else {
+          u16_t new_cwnd = (pcb->cwnd + pcb->mss * pcb->mss / pcb->cwnd);
+          if (new_cwnd > pcb->cwnd) {
+            pcb->cwnd = new_cwnd;
+          }
+          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: congestion avoidance cwnd %"U16_F"\n", pcb->cwnd));
+        }
+      }
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: ACK for %"U32_F", unacked->seqno %"U32_F":%"U32_F"\n",
+                                    ackno,
+                                    pcb->unacked != NULL?
+                                    ntohl(pcb->unacked->tcphdr->seqno): 0,
+                                    pcb->unacked != NULL?
+                                    ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked): 0));
+
+      /* Remove segment from the unacknowledged list if the incoming
+         ACK acknowlegdes them. */
+      while (pcb->unacked != NULL &&
+             TCP_SEQ_LEQ(ntohl(pcb->unacked->tcphdr->seqno) +
+                         TCP_TCPLEN(pcb->unacked), ackno)) {
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unacked\n",
+                                      ntohl(pcb->unacked->tcphdr->seqno),
+                                      ntohl(pcb->unacked->tcphdr->seqno) +
+                                      TCP_TCPLEN(pcb->unacked)));
+
+        next = pcb->unacked;
+        pcb->unacked = pcb->unacked->next;
+
+        LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen));
+        LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= pbuf_clen(next->p)));
+        pcb->snd_queuelen -= pbuf_clen(next->p);
+        tcp_seg_free(next);
+
+        LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unacked)\n", (u16_t)pcb->snd_queuelen));
+        if (pcb->snd_queuelen != 0) {
+          LWIP_ASSERT("tcp_receive: valid queue length", pcb->unacked != NULL ||
+                      pcb->unsent != NULL);
+        }
+      }
+
+      /* If there's nothing left to acknowledge, stop the retransmit
+         timer, otherwise reset it to start again */
+      if(pcb->unacked == NULL)
+        pcb->rtime = -1;
+      else
+        pcb->rtime = 0;
+
+      pcb->polltmr = 0;
+    } else {
+      /* Fix bug bug #21582: out of sequence ACK, didn't really ack anything */
+      pcb->acked = 0;
+    }
+
+    /* We go through the ->unsent list to see if any of the segments
+       on the list are acknowledged by the ACK. This may seem
+       strange since an "unsent" segment shouldn't be acked. The
+       rationale is that lwIP puts all outstanding segments on the
+       ->unsent list after a retransmission, so these segments may
+       in fact have been sent once. */
+    while (pcb->unsent != NULL &&
+           /*TCP_SEQ_LEQ(ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), ackno) &&
+             TCP_SEQ_LEQ(ackno, pcb->snd_max)*/
+           TCP_SEQ_BETWEEN(ackno, ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), pcb->snd_max)
+           ) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unsent\n",
+                                    ntohl(pcb->unsent->tcphdr->seqno), ntohl(pcb->unsent->tcphdr->seqno) +
+                                    TCP_TCPLEN(pcb->unsent)));
+
+      next = pcb->unsent;
+      pcb->unsent = pcb->unsent->next;
+      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen));
+      LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= pbuf_clen(next->p)));
+      pcb->snd_queuelen -= pbuf_clen(next->p);
+      tcp_seg_free(next);
+      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unsent)\n", (u16_t)pcb->snd_queuelen));
+      if (pcb->snd_queuelen != 0) {
+        LWIP_ASSERT("tcp_receive: valid queue length",
+          pcb->unacked != NULL || pcb->unsent != NULL);
+      }
+
+      if (pcb->unsent != NULL) {
+        pcb->snd_nxt = htonl(pcb->unsent->tcphdr->seqno);
+      }
+    }
+    /* End of ACK for new data processing. */
+
+    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: pcb->rttest %"U32_F" rtseq %"U32_F" ackno %"U32_F"\n",
+                                pcb->rttest, pcb->rtseq, ackno));
+
+    /* RTT estimation calculations. This is done by checking if the
+       incoming segment acknowledges the segment we use to take a
+       round-trip time measurement. */
+    if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) {
+      /* diff between this shouldn't exceed 32K since this are tcp timer ticks
+         and a round-trip shouldn't be that long... */
+      m = (s16_t)(tcp_ticks - pcb->rttest);
+
+      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n",
+                                  m, m * TCP_SLOW_INTERVAL));
+
+      /* This is taken directly from VJs original code in his paper */
+      m = m - (pcb->sa >> 3);
+      pcb->sa += m;
+      if (m < 0) {
+        m = -m;
+      }
+      m = m - (pcb->sv >> 2);
+      pcb->sv += m;
+      pcb->rto = (pcb->sa >> 3) + pcb->sv;
+
+      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" milliseconds)\n",
+                                  pcb->rto, pcb->rto * TCP_SLOW_INTERVAL));
+
+      pcb->rttest = 0;
+    }
+  }
+
+  /* If the incoming segment contains data, we must process it
+     further. */
+  if (tcplen > 0) {
+    /* This code basically does three things:
+
+    +) If the incoming segment contains data that is the next
+    in-sequence data, this data is passed to the application. This
+    might involve trimming the first edge of the data. The rcv_nxt
+    variable and the advertised window are adjusted.
+
+    +) If the incoming segment has data that is above the next
+    sequence number expected (->rcv_nxt), the segment is placed on
+    the ->ooseq queue. This is done by finding the appropriate
+    place in the ->ooseq queue (which is ordered by sequence
+    number) and trim the segment in both ends if needed. An
+    immediate ACK is sent to indicate that we received an
+    out-of-sequence segment.
+
+    +) Finally, we check if the first segment on the ->ooseq queue
+    now is in sequence (i.e., if rcv_nxt >= ooseq->seqno). If
+    rcv_nxt > ooseq->seqno, we must trim the first edge of the
+    segment on ->ooseq before we adjust rcv_nxt. The data in the
+    segments that are now on sequence are chained onto the
+    incoming segment so that we only need to call the application
+    once.
+    */
+
+    /* First, we check if we must trim the first edge. We have to do
+       this if the sequence number of the incoming segment is less
+       than rcv_nxt, and the sequence number plus the length of the
+       segment is larger than rcv_nxt. */
+    /*    if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){
+          if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/
+    if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)){
+      /* Trimming the first edge is done by pushing the payload
+         pointer in the pbuf downwards. This is somewhat tricky since
+         we do not want to discard the full contents of the pbuf up to
+         the new starting point of the data since we have to keep the
+         TCP header which is present in the first pbuf in the chain.
+
+         What is done is really quite a nasty hack: the first pbuf in
+         the pbuf chain is pointed to by inseg.p. Since we need to be
+         able to deallocate the whole pbuf, we cannot change this
+         inseg.p pointer to point to any of the later pbufs in the
+         chain. Instead, we point the ->payload pointer in the first
+         pbuf to data in one of the later pbufs. We also set the
+         inseg.data pointer to point to the right place. This way, the
+         ->p pointer will still point to the first pbuf, but the
+         ->p->payload pointer will point to data in another pbuf.
+
+         After we are done with adjusting the pbuf pointers we must
+         adjust the ->data pointer in the seg and the segment
+         length.*/
+
+      off = pcb->rcv_nxt - seqno;
+      p = inseg.p;
+      LWIP_ASSERT("inseg.p != NULL", inseg.p);
+      LWIP_ASSERT("insane offset!", (off < 0x7fff));
+      if (inseg.p->len < off) {
+        LWIP_ASSERT("pbuf too short!", (((s32_t)inseg.p->tot_len) >= off));
+        new_tot_len = (u16_t)(inseg.p->tot_len - off);
+        while (p->len < off) {
+          off -= p->len;
+          /* KJM following line changed (with addition of new_tot_len var)
+             to fix bug #9076
+             inseg.p->tot_len -= p->len; */
+          p->tot_len = new_tot_len;
+          p->len = 0;
+          p = p->next;
+        }
+        if(pbuf_header(p, (s16_t)-off)) {
+          /* Do we need to cope with this failing?  Assert for now */
+          LWIP_ASSERT("pbuf_header failed", 0);
+        }
+      } else {
+        if(pbuf_header(inseg.p, (s16_t)-off)) {
+          /* Do we need to cope with this failing?  Assert for now */
+          LWIP_ASSERT("pbuf_header failed", 0);
+        }
+      }
+      /* KJM following line changed to use p->payload rather than inseg->p->payload
+         to fix bug #9076 */
+      inseg.dataptr = p->payload;
+      inseg.len -= (u16_t)(pcb->rcv_nxt - seqno);
+      inseg.tcphdr->seqno = seqno = pcb->rcv_nxt;
+    }
+    else {
+      if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){
+        /* the whole segment is < rcv_nxt */
+        /* must be a duplicate of a packet that has already been correctly handled */
+
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno));
+        tcp_ack_now(pcb);
+      }
+    }
+
+    /* The sequence number must be within the window (above rcv_nxt
+       and below rcv_nxt + rcv_wnd) in order to be further
+       processed. */
+    if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt,
+                        pcb->rcv_nxt + pcb->rcv_ann_wnd - 1)){
+      if (pcb->rcv_nxt == seqno) {
+        accepted_inseq = 1;
+        /* The incoming segment is the next in sequence. We check if
+           we have to trim the end of the segment and update rcv_nxt
+           and pass the data to the application. */
+#if TCP_QUEUE_OOSEQ
+        if (pcb->ooseq != NULL &&
+                TCP_SEQ_LEQ(pcb->ooseq->tcphdr->seqno, seqno + inseg.len)) {
+          if (pcb->ooseq->len > 0) {
+            /* We have to trim the second edge of the incoming
+               segment. */
+            inseg.len = (u16_t)(pcb->ooseq->tcphdr->seqno - seqno);
+            pbuf_realloc(inseg.p, inseg.len);
+          } else {
+            /* does the ooseq segment contain only flags that are in inseg also? */
+            if ((TCPH_FLAGS(inseg.tcphdr) & (TCP_FIN|TCP_SYN)) ==
+                (TCPH_FLAGS(pcb->ooseq->tcphdr) & (TCP_FIN|TCP_SYN))) {
+              struct tcp_seg *old_ooseq = pcb->ooseq;
+              pcb->ooseq = pcb->ooseq->next;
+              memp_free(MEMP_TCP_SEG, old_ooseq);
+            }
+          }
+        }
+#endif /* TCP_QUEUE_OOSEQ */
+
+        tcplen = TCP_TCPLEN(&inseg);
+
+        /* First received FIN will be ACKed +1, on any successive (duplicate)
+         * FINs we are already in CLOSE_WAIT and have already done +1.
+         */
+        if (pcb->state != CLOSE_WAIT) {
+          pcb->rcv_nxt += tcplen;
+        }
+
+        /* Update the receiver's (our) window. */
+        if (pcb->rcv_wnd < tcplen) {
+          pcb->rcv_wnd = 0;
+        } else {
+          pcb->rcv_wnd -= tcplen;
+        }
+
+        if (pcb->rcv_ann_wnd < tcplen) {
+          pcb->rcv_ann_wnd = 0;
+        } else {
+          pcb->rcv_ann_wnd -= tcplen;
+        }
+
+        /* If there is data in the segment, we make preparations to
+           pass this up to the application. The ->recv_data variable
+           is used for holding the pbuf that goes to the
+           application. The code for reassembling out-of-sequence data
+           chains its data on this pbuf as well.
+
+           If the segment was a FIN, we set the TF_GOT_FIN flag that will
+           be used to indicate to the application that the remote side has
+           closed its end of the connection. */
+        if (inseg.p->tot_len > 0) {
+          recv_data = inseg.p;
+          /* Since this pbuf now is the responsibility of the
+             application, we delete our reference to it so that we won't
+             (mistakingly) deallocate it. */
+          inseg.p = NULL;
+        }
+        if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n"));
+          recv_flags = TF_GOT_FIN;
+        }
+
+#if TCP_QUEUE_OOSEQ
+        /* We now check if we have segments on the ->ooseq queue that
+           is now in sequence. */
+        while (pcb->ooseq != NULL &&
+               pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) {
+
+          cseg = pcb->ooseq;
+          seqno = pcb->ooseq->tcphdr->seqno;
+
+          pcb->rcv_nxt += TCP_TCPLEN(cseg);
+          if (pcb->rcv_wnd < TCP_TCPLEN(cseg)) {
+            pcb->rcv_wnd = 0;
+          } else {
+            pcb->rcv_wnd -= TCP_TCPLEN(cseg);
+          }
+          if (pcb->rcv_ann_wnd < TCP_TCPLEN(cseg)) {
+            pcb->rcv_ann_wnd = 0;
+          } else {
+            pcb->rcv_ann_wnd -= TCP_TCPLEN(cseg);
+          }
+
+          if (cseg->p->tot_len > 0) {
+            /* Chain this pbuf onto the pbuf that we will pass to
+               the application. */
+            if (recv_data) {
+              pbuf_cat(recv_data, cseg->p);
+            } else {
+              recv_data = cseg->p;
+            }
+            cseg->p = NULL;
+          }
+          if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
+            LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n"));
+            recv_flags = TF_GOT_FIN;
+            if (pcb->state == ESTABLISHED) { /* force passive close or we can move to active close */
+              pcb->state = CLOSE_WAIT;
+            }
+          }
+
+
+          pcb->ooseq = cseg->next;
+          tcp_seg_free(cseg);
+        }
+#endif /* TCP_QUEUE_OOSEQ */
+
+
+        /* Acknowledge the segment(s). */
+        tcp_ack(pcb);
+
+      } else {
+        /* We get here if the incoming segment is out-of-sequence. */
+        tcp_ack_now(pcb);
+#if TCP_QUEUE_OOSEQ
+        /* We queue the segment on the ->ooseq queue. */
+        if (pcb->ooseq == NULL) {
+          pcb->ooseq = tcp_seg_copy(&inseg);
+        } else {
+          /* If the queue is not empty, we walk through the queue and
+             try to find a place where the sequence number of the
+             incoming segment is between the sequence numbers of the
+             previous and the next segment on the ->ooseq queue. That is
+             the place where we put the incoming segment. If needed, we
+             trim the second edges of the previous and the incoming
+             segment so that it will fit into the sequence.
+
+             If the incoming segment has the same sequence number as a
+             segment on the ->ooseq queue, we discard the segment that
+             contains less data. */
+
+          prev = NULL;
+          for(next = pcb->ooseq; next != NULL; next = next->next) {
+            if (seqno == next->tcphdr->seqno) {
+              /* The sequence number of the incoming segment is the
+                 same as the sequence number of the segment on
+                 ->ooseq. We check the lengths to see which one to
+                 discard. */
+              if (inseg.len > next->len) {
+                /* The incoming segment is larger than the old
+                   segment. We replace the old segment with the new
+                   one. */
+                cseg = tcp_seg_copy(&inseg);
+                if (cseg != NULL) {
+                  cseg->next = next->next;
+                  if (prev != NULL) {
+                    prev->next = cseg;
+                  } else {
+                    pcb->ooseq = cseg;
+                  }
+                }
+                tcp_seg_free(next);
+                if (cseg->next != NULL) {
+                  next = cseg->next;
+                  if (TCP_SEQ_GT(seqno + cseg->len, next->tcphdr->seqno)) {
+                    /* We need to trim the incoming segment. */
+                    cseg->len = (u16_t)(next->tcphdr->seqno - seqno);
+                    pbuf_realloc(cseg->p, cseg->len);
+                  }
+                }
+                break;
+              } else {
+                /* Either the lenghts are the same or the incoming
+                   segment was smaller than the old one; in either
+                   case, we ditch the incoming segment. */
+                break;
+              }
+            } else {
+              if (prev == NULL) {
+                if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {
+                  /* The sequence number of the incoming segment is lower
+                     than the sequence number of the first segment on the
+                     queue. We put the incoming segment first on the
+                     queue. */
+
+                  if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) {
+                    /* We need to trim the incoming segment. */
+                    inseg.len = (u16_t)(next->tcphdr->seqno - seqno);
+                    pbuf_realloc(inseg.p, inseg.len);
+                  }
+                  cseg = tcp_seg_copy(&inseg);
+                  if (cseg != NULL) {
+                    cseg->next = next;
+                    pcb->ooseq = cseg;
+                  }
+                  break;
+                }
+              } else
+                /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) &&
+                  TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/
+                if(TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno+1, next->tcphdr->seqno-1)){
+                /* The sequence number of the incoming segment is in
+                   between the sequence numbers of the previous and
+                   the next segment on ->ooseq. We trim and insert the
+                   incoming segment and trim the previous segment, if
+                   needed. */
+                if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) {
+                  /* We need to trim the incoming segment. */
+                  inseg.len = (u16_t)(next->tcphdr->seqno - seqno);
+                  pbuf_realloc(inseg.p, inseg.len);
+                }
+
+                cseg = tcp_seg_copy(&inseg);
+                if (cseg != NULL) {
+                  cseg->next = next;
+                  prev->next = cseg;
+                  if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) {
+                    /* We need to trim the prev segment. */
+                    prev->len = (u16_t)(seqno - prev->tcphdr->seqno);
+                    pbuf_realloc(prev->p, prev->len);
+                  }
+                }
+                break;
+              }
+              /* If the "next" segment is the last segment on the
+                 ooseq queue, we add the incoming segment to the end
+                 of the list. */
+              if (next->next == NULL &&
+                  TCP_SEQ_GT(seqno, next->tcphdr->seqno)) {
+                next->next = tcp_seg_copy(&inseg);
+                if (next->next != NULL) {
+                  if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) {
+                    /* We need to trim the last segment. */
+                    next->len = (u16_t)(seqno - next->tcphdr->seqno);
+                    pbuf_realloc(next->p, next->len);
+                  }
+                }
+                break;
+              }
+            }
+            prev = next;
+          }
+        }
+#endif /* TCP_QUEUE_OOSEQ */
+
+      }
+    } else {
+      if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt,
+                          pcb->rcv_nxt + pcb->rcv_ann_wnd-1)){
+        tcp_ack_now(pcb);
+      }
+    }
+  } else {
+    /* Segments with length 0 is taken care of here. Segments that
+       fall out of the window are ACKed. */
+    /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) ||
+      TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
+    if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){
+      tcp_ack_now(pcb);
+    }
+  }
+  return accepted_inseq;
+}
+
+/**
+ * Parses the options contained in the incoming segment. (Code taken
+ * from uIP with only small changes.)
+ *
+ * Called from tcp_listen_input() and tcp_process().
+ * Currently, only the MSS option is supported!
+ *
+ * @param pcb the tcp_pcb for which a segment arrived
+ */
+static void
+tcp_parseopt(struct tcp_pcb *pcb)
+{
+  u8_t c;
+  u8_t *opts, opt;
+  u16_t mss;
+
+  opts = (u8_t *)tcphdr + TCP_HLEN;
+
+  /* Parse the TCP MSS option, if present. */
+  if(TCPH_HDRLEN(tcphdr) > 0x5) {
+    for(c = 0; c < (TCPH_HDRLEN(tcphdr) - 5) << 2 ;) {
+      opt = opts[c];
+      if (opt == 0x00) {
+        /* End of options. */
+        break;
+      } else if (opt == 0x01) {
+        ++c;
+        /* NOP option. */
+      } else if (opt == 0x02 &&
+        opts[c + 1] == 0x04) {
+        /* An MSS option with the right option length. */
+        mss = (opts[c + 2] << 8) | opts[c + 3];
+        pcb->mss = mss > TCP_MSS? TCP_MSS: mss;
+
+        /* And we are done processing options. */
+        break;
+      } else {
+        if (opts[c + 1] == 0) {
+          /* If the length field is zero, the options are malformed
+             and we don't process them further. */
+          break;
+        }
+        /* All other options have a length field, so that we easily
+           can skip past them. */
+        c += opts[c + 1];
+      }
+    }
+  }
+}
+
+#endif /* LWIP_TCP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/tcp_out.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/tcp_out.c
new file mode 100644
index 0000000..a116d3c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/tcp_out.c
@@ -0,0 +1,953 @@
+/**
+ * @file
+ * Transmission Control Protocol, outgoing traffic
+ *
+ * The output functions of TCP.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/tcp.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/sys.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/inet.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+
+#include 
+
+/* Forward declarations.*/
+static void tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb);
+
+/**
+ * Called by tcp_close() to send a segment including flags but not data.
+ *
+ * @param pcb the tcp_pcb over which to send a segment
+ * @param flags the flags to set in the segment header
+ * @return ERR_OK if sent, another err_t otherwise
+ */
+err_t
+tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags)
+{
+  /* no data, no length, flags, copy=1, no optdata, no optdatalen */
+  return tcp_enqueue(pcb, NULL, 0, flags, TCP_WRITE_FLAG_COPY, NULL, 0);
+}
+
+/**
+ * Write data for sending (but does not send it immediately).
+ *
+ * It waits in the expectation of more data being sent soon (as
+ * it can send them more efficiently by combining them together).
+ * To prompt the system to send data now, call tcp_output() after
+ * calling tcp_write().
+ *
+ * @param pcb Protocol control block of the TCP connection to enqueue data for.
+ * @param data pointer to the data to send
+ * @param len length (in bytes) of the data to send
+ * @param apiflags combination of following flags :
+ * - TCP_WRITE_FLAG_COPY (0x01) data will be copied into memory belonging to the stack
+ * - TCP_WRITE_FLAG_MORE (0x02) for TCP connection, PSH flag will be set on last segment sent,
+ * @return ERR_OK if enqueued, another err_t on error
+ *
+ * @see tcp_write()
+ */
+err_t
+tcp_write(struct tcp_pcb *pcb, const void *data, u16_t len, u8_t apiflags)
+{
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, data=%p, len=%"U16_F", apiflags=%"U16_F")\n", (void *)pcb,
+    data, len, (u16_t)apiflags));
+  /* connection is in valid state for data transmission? */
+  if (pcb->state == ESTABLISHED ||
+     pcb->state == CLOSE_WAIT ||
+     pcb->state == SYN_SENT ||
+     pcb->state == SYN_RCVD) {
+    if (len > 0) {
+      return tcp_enqueue(pcb, (void *)data, len, 0, apiflags, NULL, 0);
+    }
+    return ERR_OK;
+  } else {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_STATE | 3, ("tcp_write() called in invalid state\n"));
+    return ERR_CONN;
+  }
+}
+
+/**
+ * Enqueue either data or TCP options (but not both) for tranmission
+ *
+ * Called by tcp_connect(), tcp_listen_input(), tcp_send_ctrl() and tcp_write().
+ *
+ * @param pcb Protocol control block for the TCP connection to enqueue data for.
+ * @param arg Pointer to the data to be enqueued for sending.
+ * @param len Data length in bytes
+ * @param flags tcp header flags to set in the outgoing segment
+ * @param apiflags combination of following flags :
+ * - TCP_WRITE_FLAG_COPY (0x01) data will be copied into memory belonging to the stack
+ * - TCP_WRITE_FLAG_MORE (0x02) for TCP connection, PSH flag will be set on last segment sent,
+ * @param optdata
+ * @param optlen
+ */
+err_t
+tcp_enqueue(struct tcp_pcb *pcb, void *arg, u16_t len,
+  u8_t flags, u8_t apiflags,
+  u8_t *optdata, u8_t optlen)
+{
+  struct pbuf *p;
+  struct tcp_seg *seg, *useg, *queue;
+  u32_t seqno;
+  u16_t left, seglen;
+  void *ptr;
+  u16_t queuelen;
+
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_enqueue(pcb=%p, arg=%p, len=%"U16_F", flags=%"X16_F", apiflags=%"U16_F")\n",
+    (void *)pcb, arg, len, (u16_t)flags, (u16_t)apiflags));
+  LWIP_ERROR("tcp_enqueue: len == 0 || optlen == 0 (programmer violates API)",
+      ((len == 0) || (optlen == 0)), return ERR_ARG;);
+  LWIP_ERROR("tcp_enqueue: arg == NULL || optdata == NULL (programmer violates API)",
+      ((arg == NULL) || (optdata == NULL)), return ERR_ARG;);
+  /* fail on too much data */
+  if (len > pcb->snd_buf) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too much data (len=%"U16_F" > snd_buf=%"U16_F")\n", len, pcb->snd_buf));
+    pcb->flags |= TF_NAGLEMEMERR;
+    return ERR_MEM;
+  }
+  left = len;
+  ptr = arg;
+
+  /* seqno will be the sequence number of the first segment enqueued
+   * by the call to this function. */
+  seqno = pcb->snd_lbb;
+
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen));
+
+  /* If total number of pbufs on the unsent/unacked queues exceeds the
+   * configured maximum, return an error */
+  queuelen = pcb->snd_queuelen;
+  /* check for configured max queuelen and possible overflow */
+  if ((queuelen >= TCP_SND_QUEUELEN) || (queuelen > TCP_SNDQUEUELEN_OVERFLOW)) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too long queue %"U16_F" (max %"U16_F")\n", queuelen, TCP_SND_QUEUELEN));
+    TCP_STATS_INC(tcp.memerr);
+    pcb->flags |= TF_NAGLEMEMERR;
+    return ERR_MEM;
+  }
+  if (queuelen != 0) {
+    LWIP_ASSERT("tcp_enqueue: pbufs on queue => at least one queue non-empty",
+      pcb->unacked != NULL || pcb->unsent != NULL);
+  } else {
+    LWIP_ASSERT("tcp_enqueue: no pbufs on queue => both queues empty",
+      pcb->unacked == NULL && pcb->unsent == NULL);
+  }
+
+  /* First, break up the data into segments and tuck them together in
+   * the local "queue" variable. */
+  useg = queue = seg = NULL;
+  seglen = 0;
+  while (queue == NULL || left > 0) {
+
+    /* The segment length should be the MSS if the data to be enqueued
+     * is larger than the MSS. */
+    seglen = left > pcb->mss? pcb->mss: left;
+
+    /* Allocate memory for tcp_seg, and fill in fields. */
+    seg = memp_malloc(MEMP_TCP_SEG);
+    if (seg == NULL) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for tcp_seg\n"));
+      goto memerr;
+    }
+    seg->next = NULL;
+    seg->p = NULL;
+
+    /* first segment of to-be-queued data? */
+    if (queue == NULL) {
+      queue = seg;
+    }
+    /* subsequent segments of to-be-queued data */
+    else {
+      /* Attach the segment to the end of the queued segments */
+      LWIP_ASSERT("useg != NULL", useg != NULL);
+      useg->next = seg;
+    }
+    /* remember last segment of to-be-queued data for next iteration */
+    useg = seg;
+
+    /* If copy is set, memory should be allocated
+     * and data copied into pbuf, otherwise data comes from
+     * ROM or other static memory, and need not be copied. If
+     * optdata is != NULL, we have options instead of data. */
+
+    /* options? */
+    if (optdata != NULL) {
+      if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) {
+        goto memerr;
+      }
+      LWIP_ASSERT("check that first pbuf can hold optlen",
+                  (seg->p->len >= optlen));
+      queuelen += pbuf_clen(seg->p);
+      seg->dataptr = seg->p->payload;
+    }
+    /* copy from volatile memory? */
+    else if (apiflags & TCP_WRITE_FLAG_COPY) {
+      if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_RAM)) == NULL) {
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue : could not allocate memory for pbuf copy size %"U16_F"\n", seglen));
+        goto memerr;
+      }
+      LWIP_ASSERT("check that first pbuf can hold the complete seglen",
+                  (seg->p->len >= seglen));
+      queuelen += pbuf_clen(seg->p);
+      if (arg != NULL) {
+        MEMCPY(seg->p->payload, ptr, seglen);
+      }
+      seg->dataptr = seg->p->payload;
+    }
+    /* do not copy data */
+    else {
+      /* First, allocate a pbuf for holding the data.
+       * since the referenced data is available at least until it is sent out on the
+       * link (as it has to be ACKed by the remote party) we can safely use PBUF_ROM
+       * instead of PBUF_REF here.
+       */
+      if ((p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_ROM)) == NULL) {
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for zero-copy pbuf\n"));
+        goto memerr;
+      }
+      ++queuelen;
+      /* reference the non-volatile payload data */
+      p->payload = ptr;
+      seg->dataptr = ptr;
+
+      /* Second, allocate a pbuf for the headers. */
+      if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_RAM)) == NULL) {
+        /* If allocation fails, we have to deallocate the data pbuf as
+         * well. */
+        pbuf_free(p);
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for header pbuf\n"));
+        goto memerr;
+      }
+      queuelen += pbuf_clen(seg->p);
+
+      /* Concatenate the headers and data pbufs together. */
+      pbuf_cat(seg->p/*header*/, p/*data*/);
+      p = NULL;
+    }
+
+    /* Now that there are more segments queued, we check again if the
+    length of the queue exceeds the configured maximum or overflows. */
+    if ((queuelen > TCP_SND_QUEUELEN) || (queuelen > TCP_SNDQUEUELEN_OVERFLOW)) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: queue too long %"U16_F" (%"U16_F")\n", queuelen, TCP_SND_QUEUELEN));
+      goto memerr;
+    }
+
+    seg->len = seglen;
+
+    /* build TCP header */
+    if (pbuf_header(seg->p, TCP_HLEN)) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: no room for TCP header in pbuf.\n"));
+      TCP_STATS_INC(tcp.err);
+      goto memerr;
+    }
+    seg->tcphdr = seg->p->payload;
+    seg->tcphdr->src = htons(pcb->local_port);
+    seg->tcphdr->dest = htons(pcb->remote_port);
+    seg->tcphdr->seqno = htonl(seqno);
+    seg->tcphdr->urgp = 0;
+    TCPH_FLAGS_SET(seg->tcphdr, flags);
+    /* don't fill in tcphdr->ackno and tcphdr->wnd until later */
+
+    /* Copy the options into the header, if they are present. */
+    if (optdata == NULL) {
+      TCPH_HDRLEN_SET(seg->tcphdr, 5);
+    }
+    else {
+      TCPH_HDRLEN_SET(seg->tcphdr, (5 + optlen / 4));
+      /* Copy options into data portion of segment.
+       Options can thus only be sent in non data carrying
+       segments such as SYN|ACK. */
+      SMEMCPY(seg->dataptr, optdata, optlen);
+    }
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_TRACE, ("tcp_enqueue: queueing %"U32_F":%"U32_F" (0x%"X16_F")\n",
+      ntohl(seg->tcphdr->seqno),
+      ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg),
+      (u16_t)flags));
+
+    left -= seglen;
+    seqno += seglen;
+    ptr = (void *)((u8_t *)ptr + seglen);
+  }
+
+  /* Now that the data to be enqueued has been broken up into TCP
+  segments in the queue variable, we add them to the end of the
+  pcb->unsent queue. */
+  if (pcb->unsent == NULL) {
+    useg = NULL;
+  }
+  else {
+    for (useg = pcb->unsent; useg->next != NULL; useg = useg->next){}
+  }
+  /* { useg is last segment on the unsent queue, NULL if list is empty } */
+
+  /* If there is room in the last pbuf on the unsent queue,
+  chain the first pbuf on the queue together with that. */
+  if (useg != NULL &&
+    TCP_TCPLEN(useg) != 0 &&
+    !(TCPH_FLAGS(useg->tcphdr) & (TCP_SYN | TCP_FIN)) &&
+    !(flags & (TCP_SYN | TCP_FIN)) &&
+    /* fit within max seg size */
+    useg->len + queue->len <= pcb->mss) {
+    /* Remove TCP header from first segment of our to-be-queued list */
+    if(pbuf_header(queue->p, -TCP_HLEN)) {
+      /* Can we cope with this failing?  Just assert for now */
+      LWIP_ASSERT("pbuf_header failed\n", 0);
+      TCP_STATS_INC(tcp.err);
+      goto memerr;
+    }
+    pbuf_cat(useg->p, queue->p);
+    useg->len += queue->len;
+    useg->next = queue->next;
+
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("tcp_enqueue: chaining segments, new len %"U16_F"\n", useg->len));
+    if (seg == queue) {
+      seg = NULL;
+    }
+    memp_free(MEMP_TCP_SEG, queue);
+  }
+  else {
+    /* empty list */
+    if (useg == NULL) {
+      /* initialize list with this segment */
+      pcb->unsent = queue;
+    }
+    /* enqueue segment */
+    else {
+      useg->next = queue;
+    }
+  }
+  if ((flags & TCP_SYN) || (flags & TCP_FIN)) {
+    ++len;
+  }
+  if (flags & TCP_FIN) {
+    pcb->flags |= TF_FIN;
+  }
+  pcb->snd_lbb += len;
+
+  pcb->snd_buf -= len;
+
+  /* update number of segments on the queues */
+  pcb->snd_queuelen = queuelen;
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: %"S16_F" (after enqueued)\n", pcb->snd_queuelen));
+  if (pcb->snd_queuelen != 0) {
+    LWIP_ASSERT("tcp_enqueue: valid queue length",
+      pcb->unacked != NULL || pcb->unsent != NULL);
+  }
+
+  /* Set the PSH flag in the last segment that we enqueued, but only
+  if the segment has data (indicated by seglen > 0). */
+  if (seg != NULL && seglen > 0 && seg->tcphdr != NULL && ((apiflags & TCP_WRITE_FLAG_MORE)==0)) {
+    TCPH_SET_FLAG(seg->tcphdr, TCP_PSH);
+  }
+
+  return ERR_OK;
+memerr:
+  pcb->flags |= TF_NAGLEMEMERR;
+  TCP_STATS_INC(tcp.memerr);
+
+  if (queue != NULL) {
+    tcp_segs_free(queue);
+  }
+  if (pcb->snd_queuelen != 0) {
+    LWIP_ASSERT("tcp_enqueue: valid queue length", pcb->unacked != NULL ||
+      pcb->unsent != NULL);
+  }
+  LWIP_DEBUGF(TCP_QLEN_DEBUG | LWIP_DBG_STATE, ("tcp_enqueue: %"S16_F" (with mem err)\n", pcb->snd_queuelen));
+  return ERR_MEM;
+}
+
+/**
+ * Find out what we can send and send it
+ *
+ * @param pcb Protocol control block for the TCP connection to send data
+ * @return ERR_OK if data has been sent or nothing to send
+ *         another err_t on error
+ */
+err_t
+tcp_output(struct tcp_pcb *pcb)
+{
+  struct pbuf *p;
+  struct tcp_hdr *tcphdr;
+  struct tcp_seg *seg, *useg;
+  u32_t wnd;
+#if TCP_CWND_DEBUG
+  s16_t i = 0;
+#endif /* TCP_CWND_DEBUG */
+
+  /* First, check if we are invoked by the TCP input processing
+     code. If so, we do not output anything. Instead, we rely on the
+     input processing code to call us when input processing is done
+     with. */
+  if (tcp_input_pcb == pcb) {
+    return ERR_OK;
+  }
+
+  wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd);
+
+  seg = pcb->unsent;
+
+  /* useg should point to last segment on unacked queue */
+  useg = pcb->unacked;
+  if (useg != NULL) {
+    for (; useg->next != NULL; useg = useg->next){}
+  }
+
+  /* If the TF_ACK_NOW flag is set and no data will be sent (either
+   * because the ->unsent queue is empty or because the window does
+   * not allow it), construct an empty ACK segment and send it.
+   *
+   * If data is to be sent, we will just piggyback the ACK (see below).
+   */
+  if (pcb->flags & TF_ACK_NOW &&
+     (seg == NULL ||
+      ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd)) {
+    p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
+    if (p == NULL) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n"));
+      return ERR_BUF;
+    }
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt));
+    /* remove ACK flags from the PCB, as we send an empty ACK now */
+    pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
+
+    tcphdr = p->payload;
+    tcphdr->src = htons(pcb->local_port);
+    tcphdr->dest = htons(pcb->remote_port);
+    tcphdr->seqno = htonl(pcb->snd_nxt);
+    tcphdr->ackno = htonl(pcb->rcv_nxt);
+    TCPH_FLAGS_SET(tcphdr, TCP_ACK);
+    tcphdr->wnd = htons(pcb->rcv_ann_wnd);
+    tcphdr->urgp = 0;
+    TCPH_HDRLEN_SET(tcphdr, 5);
+
+    tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+    tcphdr->chksum = inet_chksum_pseudo(p, &(pcb->local_ip), &(pcb->remote_ip),
+          IP_PROTO_TCP, p->tot_len);
+#endif
+#if LWIP_NETIF_HWADDRHINT
+    {
+      struct netif *netif;
+      netif = ip_route(&pcb->remote_ip);
+      if(netif != NULL){
+        netif->addr_hint = &(pcb->addr_hint);
+        ip_output_if(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl,
+                     pcb->tos, IP_PROTO_TCP, netif);
+        netif->addr_hint = NULL;
+      }
+    }
+#else /* LWIP_NETIF_HWADDRHINT*/
+    ip_output(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,
+        IP_PROTO_TCP);
+#endif /* LWIP_NETIF_HWADDRHINT*/
+    pbuf_free(p);
+
+    return ERR_OK;
+  }
+
+#if TCP_OUTPUT_DEBUG
+  if (seg == NULL) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: nothing to send (%p)\n",
+                                   (void*)pcb->unsent));
+  }
+#endif /* TCP_OUTPUT_DEBUG */
+#if TCP_CWND_DEBUG
+  if (seg == NULL) {
+    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U16_F
+                                 ", cwnd %"U16_F", wnd %"U32_F
+                                 ", seg == NULL, ack %"U32_F"\n",
+                                 pcb->snd_wnd, pcb->cwnd, wnd, pcb->lastack));
+  } else {
+    LWIP_DEBUGF(TCP_CWND_DEBUG,
+                ("tcp_output: snd_wnd %"U16_F", cwnd %"U16_F", wnd %"U32_F
+                 ", effwnd %"U32_F", seq %"U32_F", ack %"U32_F"\n",
+                 pcb->snd_wnd, pcb->cwnd, wnd,
+                 ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len,
+                 ntohl(seg->tcphdr->seqno), pcb->lastack));
+  }
+#endif /* TCP_CWND_DEBUG */
+  /* data available and window allows it to be sent? */
+  while (seg != NULL &&
+         ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) {
+    LWIP_ASSERT("RST not expected here!",
+                (TCPH_FLAGS(seg->tcphdr) & TCP_RST) == 0);
+    /* Stop sending if the nagle algorithm would prevent it
+     * Don't stop:
+     * - if tcp_enqueue had a memory error before (prevent delayed ACK timeout) or
+     * - if FIN was already enqueued for this PCB (SYN is always alone in a segment -
+     *   either seg->next != NULL or pcb->unacked == NULL;
+     *   RST is no sent using tcp_enqueue/tcp_output.
+     */
+    if((tcp_do_output_nagle(pcb) == 0) &&
+      ((pcb->flags & (TF_NAGLEMEMERR | TF_FIN)) == 0)){
+      break;
+    }
+#if TCP_CWND_DEBUG
+    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U16_F", cwnd %"U16_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F", i %"S16_F"\n",
+                            pcb->snd_wnd, pcb->cwnd, wnd,
+                            ntohl(seg->tcphdr->seqno) + seg->len -
+                            pcb->lastack,
+                            ntohl(seg->tcphdr->seqno), pcb->lastack, i));
+    ++i;
+#endif /* TCP_CWND_DEBUG */
+
+    pcb->unsent = seg->next;
+
+    if (pcb->state != SYN_SENT) {
+      TCPH_SET_FLAG(seg->tcphdr, TCP_ACK);
+      pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
+    }
+
+    tcp_output_segment(seg, pcb);
+    pcb->snd_nxt = ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);
+    if (TCP_SEQ_LT(pcb->snd_max, pcb->snd_nxt)) {
+      pcb->snd_max = pcb->snd_nxt;
+    }
+    /* put segment on unacknowledged list if length > 0 */
+    if (TCP_TCPLEN(seg) > 0) {
+      seg->next = NULL;
+      /* unacked list is empty? */
+      if (pcb->unacked == NULL) {
+        pcb->unacked = seg;
+        useg = seg;
+      /* unacked list is not empty? */
+      } else {
+        /* In the case of fast retransmit, the packet should not go to the tail
+         * of the unacked queue, but rather at the head. We need to check for
+         * this case. -STJ Jul 27, 2004 */
+        if (TCP_SEQ_LT(ntohl(seg->tcphdr->seqno), ntohl(useg->tcphdr->seqno))){
+          /* add segment to head of unacked list */
+          seg->next = pcb->unacked;
+          pcb->unacked = seg;
+        } else {
+          /* add segment to tail of unacked list */
+          useg->next = seg;
+          useg = useg->next;
+        }
+      }
+    /* do not queue empty segments on the unacked list */
+    } else {
+      tcp_seg_free(seg);
+    }
+    seg = pcb->unsent;
+  }
+
+  if (seg != NULL && pcb->persist_backoff == 0 &&
+      ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > pcb->snd_wnd) {
+    /* prepare for persist timer */
+    pcb->persist_cnt = 0;
+    pcb->persist_backoff = 1;
+  }
+
+  pcb->flags &= ~TF_NAGLEMEMERR;
+  return ERR_OK;
+}
+
+/**
+ * Called by tcp_output() to actually send a TCP segment over IP.
+ *
+ * @param seg the tcp_seg to send
+ * @param pcb the tcp_pcb for the TCP connection used to send the segment
+ */
+static void
+tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb)
+{
+  u16_t len;
+  struct netif *netif;
+
+  /** @bug Exclude retransmitted segments from this count. */
+  snmp_inc_tcpoutsegs();
+
+  /* The TCP header has already been constructed, but the ackno and
+   wnd fields remain. */
+  seg->tcphdr->ackno = htonl(pcb->rcv_nxt);
+
+  /* advertise our receive window size in this TCP segment */
+  seg->tcphdr->wnd = htons(pcb->rcv_ann_wnd);
+
+  /* If we don't have a local IP address, we get one by
+     calling ip_route(). */
+  if (ip_addr_isany(&(pcb->local_ip))) {
+    netif = ip_route(&(pcb->remote_ip));
+    if (netif == NULL) {
+      return;
+    }
+    ip_addr_set(&(pcb->local_ip), &(netif->ip_addr));
+  }
+
+  /* Set retransmission timer running if it is not currently enabled */
+  if(pcb->rtime == -1)
+    pcb->rtime = 0;
+
+  if (pcb->rttest == 0) {
+    pcb->rttest = tcp_ticks;
+    pcb->rtseq = ntohl(seg->tcphdr->seqno);
+
+    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_output_segment: rtseq %"U32_F"\n", pcb->rtseq));
+  }
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n",
+          htonl(seg->tcphdr->seqno), htonl(seg->tcphdr->seqno) +
+          seg->len));
+
+  len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload);
+
+  seg->p->len -= len;
+  seg->p->tot_len -= len;
+
+  seg->p->payload = seg->tcphdr;
+
+  seg->tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+  seg->tcphdr->chksum = inet_chksum_pseudo(seg->p,
+             &(pcb->local_ip),
+             &(pcb->remote_ip),
+             IP_PROTO_TCP, seg->p->tot_len);
+#endif
+  TCP_STATS_INC(tcp.xmit);
+
+#if LWIP_NETIF_HWADDRHINT
+  {
+    struct netif *netif;
+    netif = ip_route(&pcb->remote_ip);
+    if(netif != NULL){
+      netif->addr_hint = &(pcb->addr_hint);
+      ip_output_if(seg->p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl,
+                   pcb->tos, IP_PROTO_TCP, netif);
+      netif->addr_hint = NULL;
+    }
+  }
+#else /* LWIP_NETIF_HWADDRHINT*/
+  ip_output(seg->p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,
+      IP_PROTO_TCP);
+#endif /* LWIP_NETIF_HWADDRHINT*/
+}
+
+/**
+ * Send a TCP RESET packet (empty segment with RST flag set) either to
+ * abort a connection or to show that there is no matching local connection
+ * for a received segment.
+ *
+ * Called by tcp_abort() (to abort a local connection), tcp_input() (if no
+ * matching local pcb was found), tcp_listen_input() (if incoming segment
+ * has ACK flag set) and tcp_process() (received segment in the wrong state)
+ *
+ * Since a RST segment is in most cases not sent for an active connection,
+ * tcp_rst() has a number of arguments that are taken from a tcp_pcb for
+ * most other segment output functions.
+ *
+ * @param seqno the sequence number to use for the outgoing segment
+ * @param ackno the acknowledge number to use for the outgoing segment
+ * @param local_ip the local IP address to send the segment from
+ * @param remote_ip the remote IP address to send the segment to
+ * @param local_port the local TCP port to send the segment from
+ * @param remote_port the remote TCP port to send the segment to
+ */
+void
+tcp_rst(u32_t seqno, u32_t ackno,
+  struct ip_addr *local_ip, struct ip_addr *remote_ip,
+  u16_t local_port, u16_t remote_port)
+{
+  struct pbuf *p;
+  struct tcp_hdr *tcphdr;
+  p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
+  if (p == NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n"));
+      return;
+  }
+  LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr",
+              (p->len >= sizeof(struct tcp_hdr)));
+
+  tcphdr = p->payload;
+  tcphdr->src = htons(local_port);
+  tcphdr->dest = htons(remote_port);
+  tcphdr->seqno = htonl(seqno);
+  tcphdr->ackno = htonl(ackno);
+  TCPH_FLAGS_SET(tcphdr, TCP_RST | TCP_ACK);
+  tcphdr->wnd = htons(TCP_WND);
+  tcphdr->urgp = 0;
+  TCPH_HDRLEN_SET(tcphdr, 5);
+
+  tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+  tcphdr->chksum = inet_chksum_pseudo(p, local_ip, remote_ip,
+              IP_PROTO_TCP, p->tot_len);
+#endif
+  TCP_STATS_INC(tcp.xmit);
+  snmp_inc_tcpoutrsts();
+   /* Send output with hardcoded TTL since we have no access to the pcb */
+  ip_output(p, local_ip, remote_ip, TCP_TTL, 0, IP_PROTO_TCP);
+  pbuf_free(p);
+  LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno));
+}
+
+/**
+ * Requeue all unacked segments for retransmission
+ *
+ * Called by tcp_slowtmr() for slow retransmission.
+ *
+ * @param pcb the tcp_pcb for which to re-enqueue all unacked segments
+ */
+void
+tcp_rexmit_rto(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *seg;
+
+  if (pcb->unacked == NULL) {
+    return;
+  }
+
+  /* Move all unacked segments to the head of the unsent queue */
+  for (seg = pcb->unacked; seg->next != NULL; seg = seg->next){}
+  /* concatenate unsent queue after unacked queue */
+  seg->next = pcb->unsent;
+  /* unsent queue is the concatenated queue (of unacked, unsent) */
+  pcb->unsent = pcb->unacked;
+  /* unacked queue is now empty */
+  pcb->unacked = NULL;
+
+  pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno);
+  /* increment number of retransmissions */
+  ++pcb->nrtx;
+
+  /* Don't take any RTT measurements after retransmitting. */
+  pcb->rttest = 0;
+
+  /* Do the actual retransmission */
+  tcp_output(pcb);
+}
+
+/**
+ * Requeue the first unacked segment for retransmission
+ *
+ * Called by tcp_receive() for fast retramsmit.
+ *
+ * @param pcb the tcp_pcb for which to retransmit the first unacked segment
+ */
+void
+tcp_rexmit(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *seg;
+
+  if (pcb->unacked == NULL) {
+    return;
+  }
+
+  /* Move the first unacked segment to the unsent queue */
+  seg = pcb->unacked->next;
+  pcb->unacked->next = pcb->unsent;
+  pcb->unsent = pcb->unacked;
+  pcb->unacked = seg;
+
+  pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno);
+
+  ++pcb->nrtx;
+
+  /* Don't take any rtt measurements after retransmitting. */
+  pcb->rttest = 0;
+
+  /* Do the actual retransmission. */
+  snmp_inc_tcpretranssegs();
+  tcp_output(pcb);
+}
+
+/**
+ * Send keepalive packets to keep a connection active although
+ * no data is sent over it.
+ *
+ * Called by tcp_slowtmr()
+ *
+ * @param pcb the tcp_pcb for which to send a keepalive packet
+ */
+void
+tcp_keepalive(struct tcp_pcb *pcb)
+{
+  struct pbuf *p;
+  struct tcp_hdr *tcphdr;
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: sending KEEPALIVE probe to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+                          ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+                          ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip)));
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F"   pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n",
+                          tcp_ticks, pcb->tmr, pcb->keep_cnt_sent));
+
+  p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
+
+  if(p == NULL) {
+    LWIP_DEBUGF(TCP_DEBUG,
+                ("tcp_keepalive: could not allocate memory for pbuf\n"));
+    return;
+  }
+  LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr",
+              (p->len >= sizeof(struct tcp_hdr)));
+
+  tcphdr = p->payload;
+  tcphdr->src = htons(pcb->local_port);
+  tcphdr->dest = htons(pcb->remote_port);
+  tcphdr->seqno = htonl(pcb->snd_nxt - 1);
+  tcphdr->ackno = htonl(pcb->rcv_nxt);
+  TCPH_FLAGS_SET(tcphdr, 0);
+  tcphdr->wnd = htons(pcb->rcv_ann_wnd);
+  tcphdr->urgp = 0;
+  TCPH_HDRLEN_SET(tcphdr, 5);
+
+  tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+  tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip,
+                                      IP_PROTO_TCP, p->tot_len);
+#endif
+  TCP_STATS_INC(tcp.xmit);
+
+  /* Send output to IP */
+#if LWIP_NETIF_HWADDRHINT
+  {
+    struct netif *netif;
+    netif = ip_route(&pcb->remote_ip);
+    if(netif != NULL){
+      netif->addr_hint = &(pcb->addr_hint);
+      ip_output_if(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl,
+                   0, IP_PROTO_TCP, netif);
+      netif->addr_hint = NULL;
+    }
+  }
+#else /* LWIP_NETIF_HWADDRHINT*/
+  ip_output(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP);
+#endif /* LWIP_NETIF_HWADDRHINT*/
+
+  pbuf_free(p);
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F".\n",
+                          pcb->snd_nxt - 1, pcb->rcv_nxt));
+}
+
+
+/**
+ * Send persist timer zero-window probes to keep a connection active
+ * when a window update is lost.
+ *
+ * Called by tcp_slowtmr()
+ *
+ * @param pcb the tcp_pcb for which to send a zero-window probe packet
+ */
+void
+tcp_zero_window_probe(struct tcp_pcb *pcb)
+{
+  struct pbuf *p;
+  struct tcp_hdr *tcphdr;
+  struct tcp_seg *seg;
+
+  LWIP_DEBUGF(TCP_DEBUG,
+              ("tcp_zero_window_probe: sending ZERO WINDOW probe to %"
+               U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+               ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+               ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip)));
+
+  LWIP_DEBUGF(TCP_DEBUG,
+              ("tcp_zero_window_probe: tcp_ticks %"U32_F
+               "   pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n",
+               tcp_ticks, pcb->tmr, pcb->keep_cnt_sent));
+
+  seg = pcb->unacked;
+
+  if(seg == NULL)
+    seg = pcb->unsent;
+
+  if(seg == NULL)
+    return;
+
+  p = pbuf_alloc(PBUF_IP, TCP_HLEN + 1, PBUF_RAM);
+
+  if(p == NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: no memory for pbuf\n"));
+    return;
+  }
+  LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr",
+              (p->len >= sizeof(struct tcp_hdr)));
+
+  tcphdr = p->payload;
+  tcphdr->src = htons(pcb->local_port);
+  tcphdr->dest = htons(pcb->remote_port);
+  tcphdr->seqno = seg->tcphdr->seqno;
+  tcphdr->ackno = htonl(pcb->rcv_nxt);
+  TCPH_FLAGS_SET(tcphdr, 0);
+  tcphdr->wnd = htons(pcb->rcv_ann_wnd);
+  tcphdr->urgp = 0;
+  TCPH_HDRLEN_SET(tcphdr, 5);
+
+  /* Copy in one byte from the head of the unacked queue */
+  *((char *)p->payload + sizeof(struct tcp_hdr)) = *(char *)seg->dataptr;
+
+  tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+  tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip,
+                                      IP_PROTO_TCP, p->tot_len);
+#endif
+  TCP_STATS_INC(tcp.xmit);
+
+  /* Send output to IP */
+#if LWIP_NETIF_HWADDRHINT
+  {
+    struct netif *netif;
+    netif = ip_route(&pcb->remote_ip);
+    if(netif != NULL){
+      netif->addr_hint = &(pcb->addr_hint);
+      ip_output_if(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl,
+                   0, IP_PROTO_TCP, netif);
+      netif->addr_hint = NULL;
+    }
+  }
+#else /* LWIP_NETIF_HWADDRHINT*/
+  ip_output(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP);
+#endif /* LWIP_NETIF_HWADDRHINT*/
+
+  pbuf_free(p);
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: seqno %"U32_F
+                          " ackno %"U32_F".\n",
+                          pcb->snd_nxt - 1, pcb->rcv_nxt));
+}
+#endif /* LWIP_TCP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/udp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/udp.c
new file mode 100644
index 0000000..a87656b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/core/udp.c
@@ -0,0 +1,824 @@
+/**
+ * @file
+ * User Datagram Protocol module
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+/* udp.c
+ *
+ * The code for the User Datagram Protocol UDP & UDPLite (RFC 3828).
+ *
+ */
+
+/* @todo Check the use of '(struct udp_pcb).chksum_len_rx'!
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_UDP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/udp.h"
+#include "lwip/def.h"
+#include "lwip/memp.h"
+#include "lwip/inet.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/icmp.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+#include "arch/perf.h"
+#include "lwip/dhcp.h"
+
+#include 
+
+/* The list of UDP PCBs */
+/* exported in udp.h (was static) */
+struct udp_pcb *udp_pcbs;
+
+/**
+ * Process an incoming UDP datagram.
+ *
+ * Given an incoming UDP datagram (as a chain of pbufs) this function
+ * finds a corresponding UDP PCB and hands over the pbuf to the pcbs
+ * recv function. If no pcb is found or the datagram is incorrect, the
+ * pbuf is freed.
+ *
+ * @param p pbuf to be demultiplexed to a UDP PCB.
+ * @param inp network interface on which the datagram was received.
+ *
+ */
+void
+udp_input(struct pbuf *p, struct netif *inp)
+{
+  struct udp_hdr *udphdr;
+  struct udp_pcb *pcb, *prev;
+  struct udp_pcb *uncon_pcb;
+  struct ip_hdr *iphdr;
+  u16_t src, dest;
+  u8_t local_match;
+
+  PERF_START;
+
+  UDP_STATS_INC(udp.recv);
+
+  iphdr = p->payload;
+
+  /* Check minimum length (IP header + UDP header)
+   * and move payload pointer to UDP header */
+  if (p->tot_len < (IPH_HL(iphdr) * 4 + UDP_HLEN) || pbuf_header(p, -(s16_t)(IPH_HL(iphdr) * 4))) {
+    /* drop short packets */
+    LWIP_DEBUGF(UDP_DEBUG,
+                ("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len));
+    UDP_STATS_INC(udp.lenerr);
+    UDP_STATS_INC(udp.drop);
+    snmp_inc_udpinerrors();
+    pbuf_free(p);
+    goto end;
+  }
+
+  udphdr = (struct udp_hdr *)p->payload;
+
+  LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len));
+
+  /* convert src and dest ports to host byte order */
+  src = ntohs(udphdr->src);
+  dest = ntohs(udphdr->dest);
+
+  udp_debug_print(udphdr);
+
+  /* print the UDP source and destination */
+  LWIP_DEBUGF(UDP_DEBUG,
+              ("udp (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") <-- "
+               "(%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n",
+               ip4_addr1(&iphdr->dest), ip4_addr2(&iphdr->dest),
+               ip4_addr3(&iphdr->dest), ip4_addr4(&iphdr->dest), ntohs(udphdr->dest),
+               ip4_addr1(&iphdr->src), ip4_addr2(&iphdr->src),
+               ip4_addr3(&iphdr->src), ip4_addr4(&iphdr->src), ntohs(udphdr->src)));
+
+#if LWIP_DHCP
+  pcb = NULL;
+  /* when LWIP_DHCP is active, packets to DHCP_CLIENT_PORT may only be processed by
+     the dhcp module, no other UDP pcb may use the local UDP port DHCP_CLIENT_PORT */
+  if (dest == DHCP_CLIENT_PORT) {
+    /* all packets for DHCP_CLIENT_PORT not coming from DHCP_SERVER_PORT are dropped! */
+    if (src == DHCP_SERVER_PORT) {
+      if ((inp->dhcp != NULL) && (inp->dhcp->pcb != NULL)) {
+        /* accept the packe if
+           (- broadcast or directed to us) -> DHCP is link-layer-addressed, local ip is always ANY!
+           - inp->dhcp->pcb->remote == ANY or iphdr->src */
+        if ((ip_addr_isany(&inp->dhcp->pcb->remote_ip) ||
+           ip_addr_cmp(&(inp->dhcp->pcb->remote_ip), &(iphdr->src)))) {
+          pcb = inp->dhcp->pcb;
+        }
+      }
+    }
+  } else
+#endif /* LWIP_DHCP */
+  {
+    prev = NULL;
+    local_match = 0;
+    uncon_pcb = NULL;
+    /* Iterate through the UDP pcb list for a matching pcb.
+     * 'Perfect match' pcbs (connected to the remote port & ip address) are
+     * preferred. If no perfect match is found, the first unconnected pcb that
+     * matches the local port and ip address gets the datagram. */
+    for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
+      local_match = 0;
+      /* print the PCB local and remote address */
+      LWIP_DEBUGF(UDP_DEBUG,
+                  ("pcb (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") --- "
+                   "(%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n",
+                   ip4_addr1(&pcb->local_ip), ip4_addr2(&pcb->local_ip),
+                   ip4_addr3(&pcb->local_ip), ip4_addr4(&pcb->local_ip), pcb->local_port,
+                   ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+                   ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip), pcb->remote_port));
+
+      /* compare PCB local addr+port to UDP destination addr+port */
+      if ((pcb->local_port == dest) &&
+          (ip_addr_isany(&pcb->local_ip) ||
+           ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest)) ||
+#if LWIP_IGMP
+           ip_addr_ismulticast(&(iphdr->dest)) ||
+#endif /* LWIP_IGMP */
+           ip_addr_isbroadcast(&(iphdr->dest), inp))) {
+        local_match = 1;
+        if ((uncon_pcb == NULL) &&
+            ((pcb->flags & UDP_FLAGS_CONNECTED) == 0)) {
+          /* the first unconnected matching PCB */
+          uncon_pcb = pcb;
+        }
+      }
+      /* compare PCB remote addr+port to UDP source addr+port */
+      if ((local_match != 0) &&
+          (pcb->remote_port == src) &&
+          (ip_addr_isany(&pcb->remote_ip) ||
+           ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)))) {
+        /* the first fully matching PCB */
+        if (prev != NULL) {
+          /* move the pcb to the front of udp_pcbs so that is
+             found faster next time */
+          prev->next = pcb->next;
+          pcb->next = udp_pcbs;
+          udp_pcbs = pcb;
+        } else {
+          UDP_STATS_INC(udp.cachehit);
+        }
+        break;
+      }
+      prev = pcb;
+    }
+    /* no fully matching pcb found? then look for an unconnected pcb */
+    if (pcb == NULL) {
+      pcb = uncon_pcb;
+    }
+  }
+
+  /* Check checksum if this is a match or if it was directed at us. */
+  if (pcb != NULL || ip_addr_cmp(&inp->ip_addr, &iphdr->dest)) {
+    LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_input: calculating checksum\n"));
+#if LWIP_UDPLITE
+    if (IPH_PROTO(iphdr) == IP_PROTO_UDPLITE) {
+      /* Do the UDP Lite checksum */
+#if CHECKSUM_CHECK_UDP
+      u16_t chklen = ntohs(udphdr->len);
+      if (chklen < sizeof(struct udp_hdr)) {
+        if (chklen == 0) {
+          /* For UDP-Lite, checksum length of 0 means checksum
+             over the complete packet (See RFC 3828 chap. 3.1) */
+          chklen = p->tot_len;
+        } else {
+          /* At least the UDP-Lite header must be covered by the
+             checksum! (Again, see RFC 3828 chap. 3.1) */
+          UDP_STATS_INC(udp.chkerr);
+          UDP_STATS_INC(udp.drop);
+          snmp_inc_udpinerrors();
+          pbuf_free(p);
+          goto end;
+        }
+      }
+      if (inet_chksum_pseudo_partial(p, (struct ip_addr *)&(iphdr->src),
+                             (struct ip_addr *)&(iphdr->dest),
+                             IP_PROTO_UDPLITE, p->tot_len, chklen) != 0) {
+        LWIP_DEBUGF(UDP_DEBUG | 2,
+                    ("udp_input: UDP Lite datagram discarded due to failing checksum\n"));
+        UDP_STATS_INC(udp.chkerr);
+        UDP_STATS_INC(udp.drop);
+        snmp_inc_udpinerrors();
+        pbuf_free(p);
+        goto end;
+      }
+#endif /* CHECKSUM_CHECK_UDP */
+    } else
+#endif /* LWIP_UDPLITE */
+    {
+#if CHECKSUM_CHECK_UDP
+      if (udphdr->chksum != 0) {
+        if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
+                               (struct ip_addr *)&(iphdr->dest),
+                               IP_PROTO_UDP, p->tot_len) != 0) {
+          LWIP_DEBUGF(UDP_DEBUG | 2,
+                      ("udp_input: UDP datagram discarded due to failing checksum\n"));
+          UDP_STATS_INC(udp.chkerr);
+          UDP_STATS_INC(udp.drop);
+          snmp_inc_udpinerrors();
+          pbuf_free(p);
+          goto end;
+        }
+      }
+#endif /* CHECKSUM_CHECK_UDP */
+    }
+    if(pbuf_header(p, -UDP_HLEN)) {
+      /* Can we cope with this failing? Just assert for now */
+      LWIP_ASSERT("pbuf_header failed\n", 0);
+      UDP_STATS_INC(udp.drop);
+      snmp_inc_udpinerrors();
+      pbuf_free(p);
+      goto end;
+    }
+    if (pcb != NULL) {
+      snmp_inc_udpindatagrams();
+      /* callback */
+      if (pcb->recv != NULL) {
+        /* now the recv function is responsible for freeing p */
+        pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src), src);
+      } else {
+        /* no recv function registered? then we have to free the pbuf! */
+        pbuf_free(p);
+        goto end;
+      }
+    } else {
+      LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_input: not for us.\n"));
+
+#if LWIP_ICMP
+      /* No match was found, send ICMP destination port unreachable unless
+         destination address was broadcast/multicast. */
+      if (!ip_addr_isbroadcast(&iphdr->dest, inp) &&
+          !ip_addr_ismulticast(&iphdr->dest)) {
+        /* move payload pointer back to ip header */
+        pbuf_header(p, (IPH_HL(iphdr) * 4) + UDP_HLEN);
+        LWIP_ASSERT("p->payload == iphdr", (p->payload == iphdr));
+        icmp_dest_unreach(p, ICMP_DUR_PORT);
+      }
+#endif /* LWIP_ICMP */
+      UDP_STATS_INC(udp.proterr);
+      UDP_STATS_INC(udp.drop);
+      snmp_inc_udpnoports();
+      pbuf_free(p);
+    }
+  } else {
+    pbuf_free(p);
+  }
+end:
+  PERF_STOP("udp_input");
+}
+
+/**
+ * Send data using UDP.
+ *
+ * @param pcb UDP PCB used to send the data.
+ * @param p chain of pbuf's to be sent.
+ *
+ * The datagram will be sent to the current remote_ip & remote_port
+ * stored in pcb. If the pcb is not bound to a port, it will
+ * automatically be bound to a random port.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_MEM. Out of memory.
+ * - ERR_RTE. Could not find route to destination address.
+ * - More errors could be returned by lower protocol layers.
+ *
+ * @see udp_disconnect() udp_sendto()
+ */
+err_t
+udp_send(struct udp_pcb *pcb, struct pbuf *p)
+{
+  /* send to the packet using remote ip and port stored in the pcb */
+  return udp_sendto(pcb, p, &pcb->remote_ip, pcb->remote_port);
+}
+
+/**
+ * Send data to a specified address using UDP.
+ *
+ * @param pcb UDP PCB used to send the data.
+ * @param p chain of pbuf's to be sent.
+ * @param dst_ip Destination IP address.
+ * @param dst_port Destination UDP port.
+ *
+ * dst_ip & dst_port are expected to be in the same byte order as in the pcb.
+ *
+ * If the PCB already has a remote address association, it will
+ * be restored after the data is sent.
+ *
+ * @return lwIP error code (@see udp_send for possible error codes)
+ *
+ * @see udp_disconnect() udp_send()
+ */
+err_t
+udp_sendto(struct udp_pcb *pcb, struct pbuf *p,
+  struct ip_addr *dst_ip, u16_t dst_port)
+{
+  struct netif *netif;
+
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | 3, ("udp_send\n"));
+
+  /* find the outgoing network interface for this packet */
+#if LWIP_IGMP
+  netif = ip_route((ip_addr_ismulticast(dst_ip))?(&(pcb->multicast_ip)):(dst_ip));
+#else
+  netif = ip_route(dst_ip);
+#endif /* LWIP_IGMP */
+
+  /* no outgoing network interface could be found? */
+  if (netif == NULL) {
+    LWIP_DEBUGF(UDP_DEBUG | 1, ("udp_send: No route to 0x%"X32_F"\n", dst_ip->addr));
+    UDP_STATS_INC(udp.rterr);
+    return ERR_RTE;
+  }
+  return udp_sendto_if(pcb, p, dst_ip, dst_port, netif);
+}
+
+/**
+ * Send data to a specified address using UDP.
+ * The netif used for sending can be specified.
+ *
+ * This function exists mainly for DHCP, to be able to send UDP packets
+ * on a netif that is still down.
+ *
+ * @param pcb UDP PCB used to send the data.
+ * @param p chain of pbuf's to be sent.
+ * @param dst_ip Destination IP address.
+ * @param dst_port Destination UDP port.
+ * @param netif the netif used for sending.
+ *
+ * dst_ip & dst_port are expected to be in the same byte order as in the pcb.
+ *
+ * @return lwIP error code (@see udp_send for possible error codes)
+ *
+ * @see udp_disconnect() udp_send()
+ */
+err_t
+udp_sendto_if(struct udp_pcb *pcb, struct pbuf *p,
+  struct ip_addr *dst_ip, u16_t dst_port, struct netif *netif)
+{
+  struct udp_hdr *udphdr;
+  struct ip_addr *src_ip;
+  err_t err;
+  struct pbuf *q; /* q will be sent down the stack */
+
+  /* if the PCB is not yet bound to a port, bind it here */
+  if (pcb->local_port == 0) {
+    LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | 2, ("udp_send: not yet bound to a port, binding now\n"));
+    err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
+    if (err != ERR_OK) {
+      LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | 2, ("udp_send: forced port bind failed\n"));
+      return err;
+    }
+  }
+
+  /* not enough space to add an UDP header to first pbuf in given p chain? */
+  if (pbuf_header(p, UDP_HLEN)) {
+    /* allocate header in a separate new pbuf */
+    q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM);
+    /* new header pbuf could not be allocated? */
+    if (q == NULL) {
+      LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | 2, ("udp_send: could not allocate header\n"));
+      return ERR_MEM;
+    }
+    /* chain header q in front of given pbuf p */
+    pbuf_chain(q, p);
+    /* first pbuf q points to header pbuf */
+    LWIP_DEBUGF(UDP_DEBUG,
+                ("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
+  } else {
+    /* adding space for header within p succeeded */
+    /* first pbuf q equals given pbuf */
+    q = p;
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p));
+  }
+  LWIP_ASSERT("check that first pbuf can hold struct udp_hdr",
+              (q->len >= sizeof(struct udp_hdr)));
+  /* q now represents the packet to be sent */
+  udphdr = q->payload;
+  udphdr->src = htons(pcb->local_port);
+  udphdr->dest = htons(dst_port);
+  /* in UDP, 0 checksum means 'no checksum' */
+  udphdr->chksum = 0x0000;
+
+  /* PCB local address is IP_ANY_ADDR? */
+  if (ip_addr_isany(&pcb->local_ip)) {
+    /* use outgoing network interface IP address as source address */
+    src_ip = &(netif->ip_addr);
+  } else {
+    /* check if UDP PCB local IP address is correct
+     * this could be an old address if netif->ip_addr has changed */
+    if (!ip_addr_cmp(&(pcb->local_ip), &(netif->ip_addr))) {
+      /* local_ip doesn't match, drop the packet */
+      if (q != p) {
+        /* free the header pbuf */
+        pbuf_free(q);
+        q = NULL;
+        /* p is still referenced by the caller, and will live on */
+      }
+      return ERR_VAL;
+    }
+    /* use UDP PCB local IP address as source address */
+    src_ip = &(pcb->local_ip);
+  }
+
+  LWIP_DEBUGF(UDP_DEBUG, ("udp_send: sending datagram of length %"U16_F"\n", q->tot_len));
+
+#if LWIP_UDPLITE
+  /* UDP Lite protocol? */
+  if (pcb->flags & UDP_FLAGS_UDPLITE) {
+    u16_t chklen, chklen_hdr;
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE packet length %"U16_F"\n", q->tot_len));
+    /* set UDP message length in UDP header */
+    chklen_hdr = chklen = pcb->chksum_len_tx;
+    if ((chklen < sizeof(struct udp_hdr)) || (chklen > q->tot_len)) {
+      if (chklen != 0) {
+        LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE pcb->chksum_len is illegal: %"U16_F"\n", chklen));
+      }
+      /* For UDP-Lite, checksum length of 0 means checksum
+         over the complete packet. (See RFC 3828 chap. 3.1)
+         At least the UDP-Lite header must be covered by the
+         checksum, therefore, if chksum_len has an illegal
+         value, we generate the checksum over the complete
+         packet to be safe. */
+      chklen_hdr = 0;
+      chklen = q->tot_len;
+    }
+    udphdr->len = htons(chklen_hdr);
+    /* calculate checksum */
+#if CHECKSUM_GEN_UDP
+    udphdr->chksum = inet_chksum_pseudo_partial(q, src_ip, dst_ip,
+                                        IP_PROTO_UDPLITE, q->tot_len, chklen);
+    /* chksum zero must become 0xffff, as zero means 'no checksum' */
+    if (udphdr->chksum == 0x0000)
+      udphdr->chksum = 0xffff;
+#endif /* CHECKSUM_CHECK_UDP */
+    /* output to IP */
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDPLITE,)\n"));
+#if LWIP_NETIF_HWADDRHINT
+    netif->addr_hint = &(pcb->addr_hint);
+#endif /* LWIP_NETIF_HWADDRHINT*/
+    err = ip_output_if(q, src_ip, dst_ip, pcb->ttl, pcb->tos, IP_PROTO_UDPLITE, netif);
+#if LWIP_NETIF_HWADDRHINT
+    netif->addr_hint = NULL;
+#endif /* LWIP_NETIF_HWADDRHINT*/
+  } else
+#endif /* LWIP_UDPLITE */
+  {      /* UDP */
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %"U16_F"\n", q->tot_len));
+    udphdr->len = htons(q->tot_len);
+    /* calculate checksum */
+#if CHECKSUM_GEN_UDP
+    if ((pcb->flags & UDP_FLAGS_NOCHKSUM) == 0) {
+      udphdr->chksum = inet_chksum_pseudo(q, src_ip, dst_ip, IP_PROTO_UDP, q->tot_len);
+      /* chksum zero must become 0xffff, as zero means 'no checksum' */
+      if (udphdr->chksum == 0x0000) udphdr->chksum = 0xffff;
+    }
+#endif /* CHECKSUM_CHECK_UDP */
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04"X16_F"\n", udphdr->chksum));
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDP,)\n"));
+    /* output to IP */
+#if LWIP_NETIF_HWADDRHINT
+    netif->addr_hint = &(pcb->addr_hint);
+#endif /* LWIP_NETIF_HWADDRHINT*/
+    err = ip_output_if(q, src_ip, dst_ip, pcb->ttl, pcb->tos, IP_PROTO_UDP, netif);
+#if LWIP_NETIF_HWADDRHINT
+    netif->addr_hint = NULL;
+#endif /* LWIP_NETIF_HWADDRHINT*/
+  }
+  /* TODO: must this be increased even if error occured? */
+  snmp_inc_udpoutdatagrams();
+
+  /* did we chain a separate header pbuf earlier? */
+  if (q != p) {
+    /* free the header pbuf */
+    pbuf_free(q);
+    q = NULL;
+    /* p is still referenced by the caller, and will live on */
+  }
+
+  UDP_STATS_INC(udp.xmit);
+  return err;
+}
+
+/**
+ * Bind an UDP PCB.
+ *
+ * @param pcb UDP PCB to be bound with a local address ipaddr and port.
+ * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to
+ * bind to all local interfaces.
+ * @param port local UDP port to bind with. Use 0 to automatically bind
+ * to a random port between UDP_LOCAL_PORT_RANGE_START and
+ * UDP_LOCAL_PORT_RANGE_END.
+ *
+ * ipaddr & port are expected to be in the same byte order as in the pcb.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_USE. The specified ipaddr and port are already bound to by
+ * another UDP PCB.
+ *
+ * @see udp_disconnect()
+ */
+err_t
+udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
+{
+  struct udp_pcb *ipcb;
+  u8_t rebind;
+
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | 3, ("udp_bind(ipaddr = "));
+  ip_addr_debug_print(UDP_DEBUG, ipaddr);
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | 3, (", port = %"U16_F")\n", port));
+
+  rebind = 0;
+  /* Check for double bind and rebind of the same pcb */
+  for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+    /* is this UDP PCB already on active list? */
+    if (pcb == ipcb) {
+      /* pcb may occur at most once in active list */
+      LWIP_ASSERT("rebind == 0", rebind == 0);
+      /* pcb already in list, just rebind */
+      rebind = 1;
+    }
+
+    /* this code does not allow upper layer to share a UDP port for
+       listening to broadcast or multicast traffic (See SO_REUSE_ADDR and
+       SO_REUSE_PORT under *BSD). TODO: See where it fits instead, OR
+       combine with implementation of UDP PCB flags. Leon Woestenberg. */
+#ifdef LWIP_UDP_TODO
+    /* port matches that of PCB in list? */
+    else
+      if ((ipcb->local_port == port) &&
+          /* IP address matches, or one is IP_ADDR_ANY? */
+          (ip_addr_isany(&(ipcb->local_ip)) ||
+           ip_addr_isany(ipaddr) ||
+           ip_addr_cmp(&(ipcb->local_ip), ipaddr))) {
+        /* other PCB already binds to this local IP and port */
+        LWIP_DEBUGF(UDP_DEBUG,
+                    ("udp_bind: local port %"U16_F" already bound by another pcb\n", port));
+        return ERR_USE;
+      }
+#endif
+  }
+
+  ip_addr_set(&pcb->local_ip, ipaddr);
+
+  /* no port specified? */
+  if (port == 0) {
+#ifndef UDP_LOCAL_PORT_RANGE_START
+#define UDP_LOCAL_PORT_RANGE_START 4096
+#define UDP_LOCAL_PORT_RANGE_END   0x7fff
+#endif
+    port = UDP_LOCAL_PORT_RANGE_START;
+    ipcb = udp_pcbs;
+    while ((ipcb != NULL) && (port != UDP_LOCAL_PORT_RANGE_END)) {
+      if (ipcb->local_port == port) {
+        /* port is already used by another udp_pcb */
+        port++;
+        /* restart scanning all udp pcbs */
+        ipcb = udp_pcbs;
+      } else
+        /* go on with next udp pcb */
+        ipcb = ipcb->next;
+    }
+    if (ipcb != NULL) {
+      /* no more ports available in local range */
+      LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n"));
+      return ERR_USE;
+    }
+  }
+  pcb->local_port = port;
+  snmp_insert_udpidx_tree(pcb);
+  /* pcb not active yet? */
+  if (rebind == 0) {
+    /* place the PCB on the active list if not already there */
+    pcb->next = udp_pcbs;
+    udp_pcbs = pcb;
+  }
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+              ("udp_bind: bound to %"U16_F".%"U16_F".%"U16_F".%"U16_F", port %"U16_F"\n",
+               (u16_t)(ntohl(pcb->local_ip.addr) >> 24 & 0xff),
+               (u16_t)(ntohl(pcb->local_ip.addr) >> 16 & 0xff),
+               (u16_t)(ntohl(pcb->local_ip.addr) >> 8 & 0xff),
+               (u16_t)(ntohl(pcb->local_ip.addr) & 0xff), pcb->local_port));
+  return ERR_OK;
+}
+/**
+ * Connect an UDP PCB.
+ *
+ * This will associate the UDP PCB with the remote address.
+ *
+ * @param pcb UDP PCB to be connected with remote address ipaddr and port.
+ * @param ipaddr remote IP address to connect with.
+ * @param port remote UDP port to connect with.
+ *
+ * @return lwIP error code
+ *
+ * ipaddr & port are expected to be in the same byte order as in the pcb.
+ *
+ * The udp pcb is bound to a random local port if not already bound.
+ *
+ * @see udp_disconnect()
+ */
+err_t
+udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
+{
+  struct udp_pcb *ipcb;
+
+  if (pcb->local_port == 0) {
+    err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
+    if (err != ERR_OK)
+      return err;
+  }
+
+  ip_addr_set(&pcb->remote_ip, ipaddr);
+  pcb->remote_port = port;
+  pcb->flags |= UDP_FLAGS_CONNECTED;
+/** TODO: this functionality belongs in upper layers */
+#ifdef LWIP_UDP_TODO
+  /* Nail down local IP for netconn_addr()/getsockname() */
+  if (ip_addr_isany(&pcb->local_ip) && !ip_addr_isany(&pcb->remote_ip)) {
+    struct netif *netif;
+
+    if ((netif = ip_route(&(pcb->remote_ip))) == NULL) {
+      LWIP_DEBUGF(UDP_DEBUG, ("udp_connect: No route to 0x%lx\n", pcb->remote_ip.addr));
+      UDP_STATS_INC(udp.rterr);
+      return ERR_RTE;
+    }
+    /** TODO: this will bind the udp pcb locally, to the interface which
+        is used to route output packets to the remote address. However, we
+        might want to accept incoming packets on any interface! */
+    pcb->local_ip = netif->ip_addr;
+  } else if (ip_addr_isany(&pcb->remote_ip)) {
+    pcb->local_ip.addr = 0;
+  }
+#endif
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+              ("udp_connect: connected to %"U16_F".%"U16_F".%"U16_F".%"U16_F",port %"U16_F"\n",
+               (u16_t)(ntohl(pcb->remote_ip.addr) >> 24 & 0xff),
+               (u16_t)(ntohl(pcb->remote_ip.addr) >> 16 & 0xff),
+               (u16_t)(ntohl(pcb->remote_ip.addr) >> 8 & 0xff),
+               (u16_t)(ntohl(pcb->remote_ip.addr) & 0xff), pcb->remote_port));
+
+  /* Insert UDP PCB into the list of active UDP PCBs. */
+  for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+    if (pcb == ipcb) {
+      /* already on the list, just return */
+      return ERR_OK;
+    }
+  }
+  /* PCB not yet on the list, add PCB now */
+  pcb->next = udp_pcbs;
+  udp_pcbs = pcb;
+  return ERR_OK;
+}
+
+/**
+ * Disconnect a UDP PCB
+ *
+ * @param pcb the udp pcb to disconnect.
+ */
+void
+udp_disconnect(struct udp_pcb *pcb)
+{
+  /* reset remote address association */
+  ip_addr_set(&pcb->remote_ip, IP_ADDR_ANY);
+  pcb->remote_port = 0;
+  /* mark PCB as unconnected */
+  pcb->flags &= ~UDP_FLAGS_CONNECTED;
+}
+
+/**
+ * Set a receive callback for a UDP PCB
+ *
+ * This callback will be called when receiving a datagram for the pcb.
+ *
+ * @param pcb the pcb for wich to set the recv callback
+ * @param recv function pointer of the callback function
+ * @param recv_arg additional argument to pass to the callback function
+ */
+void
+udp_recv(struct udp_pcb *pcb,
+         void (* recv)(void *arg, struct udp_pcb *upcb, struct pbuf *p,
+                       struct ip_addr *addr, u16_t port),
+         void *recv_arg)
+{
+  /* remember recv() callback and user data */
+  pcb->recv = recv;
+  pcb->recv_arg = recv_arg;
+}
+
+/**
+ * Remove an UDP PCB.
+ *
+ * @param pcb UDP PCB to be removed. The PCB is removed from the list of
+ * UDP PCB's and the data structure is freed from memory.
+ *
+ * @see udp_new()
+ */
+void
+udp_remove(struct udp_pcb *pcb)
+{
+  struct udp_pcb *pcb2;
+
+  snmp_delete_udpidx_tree(pcb);
+  /* pcb to be removed is first in list? */
+  if (udp_pcbs == pcb) {
+    /* make list start at 2nd pcb */
+    udp_pcbs = udp_pcbs->next;
+    /* pcb not 1st in list */
+  } else
+    for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
+      /* find pcb in udp_pcbs list */
+      if (pcb2->next != NULL && pcb2->next == pcb) {
+        /* remove pcb from list */
+        pcb2->next = pcb->next;
+      }
+    }
+  memp_free(MEMP_UDP_PCB, pcb);
+}
+
+/**
+ * Create a UDP PCB.
+ *
+ * @return The UDP PCB which was created. NULL if the PCB data structure
+ * could not be allocated.
+ *
+ * @see udp_remove()
+ */
+struct udp_pcb *
+udp_new(void)
+{
+  struct udp_pcb *pcb;
+  pcb = memp_malloc(MEMP_UDP_PCB);
+  /* could allocate UDP PCB? */
+  if (pcb != NULL) {
+    /* UDP Lite: by initializing to all zeroes, chksum_len is set to 0
+     * which means checksum is generated over the whole datagram per default
+     * (recommended as default by RFC 3828). */
+    /* initialize PCB to all zeroes */
+    memset(pcb, 0, sizeof(struct udp_pcb));
+    pcb->ttl = UDP_TTL;
+  }
+  return pcb;
+}
+
+#if UDP_DEBUG
+/**
+ * Print UDP header information for debug purposes.
+ *
+ * @param udphdr pointer to the udp header in memory.
+ */
+void
+udp_debug_print(struct udp_hdr *udphdr)
+{
+  LWIP_DEBUGF(UDP_DEBUG, ("UDP header:\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("|     %5"U16_F"     |     %5"U16_F"     | (src port, dest port)\n",
+                          ntohs(udphdr->src), ntohs(udphdr->dest)));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("|     %5"U16_F"     |     0x%04"X16_F"    | (len, chksum)\n",
+                          ntohs(udphdr->len), ntohs(udphdr->chksum)));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+}
+#endif /* UDP_DEBUG */
+
+#endif /* LWIP_UDP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/autoip.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/autoip.h
new file mode 100644
index 0000000..78e8475
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/autoip.h
@@ -0,0 +1,105 @@
+/**
+ * @file
+ *
+ * AutoIP Automatic LinkLocal IP Configuration
+ */
+
+/*
+ *
+ * Copyright (c) 2007 Dominik Spies 
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Dominik Spies 
+ *
+ * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform
+ * with RFC 3927.
+ *
+ *
+ * Please coordinate changes and requests with Dominik Spies
+ * 
+ */
+
+#ifndef __LWIP_AUTOIP_H__
+#define __LWIP_AUTOIP_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_AUTOIP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+#include "netif/etharp.h"
+
+/* AutoIP Timing */
+#define AUTOIP_TMR_INTERVAL      100
+#define AUTOIP_TICKS_PER_SECOND (1000 / AUTOIP_TMR_INTERVAL)
+
+/* RFC 3927 Constants */
+#define PROBE_WAIT               1   /* second   (initial random delay)                 */
+#define PROBE_MIN                1   /* second   (minimum delay till repeated probe)    */
+#define PROBE_MAX                2   /* seconds  (maximum delay till repeated probe)    */
+#define PROBE_NUM                3   /*          (number of probe packets)              */
+#define ANNOUNCE_NUM             2   /*          (number of announcement packets)       */
+#define ANNOUNCE_INTERVAL        2   /* seconds  (time between announcement packets)    */
+#define ANNOUNCE_WAIT            2   /* seconds  (delay before announcing)              */
+#define MAX_CONFLICTS            10  /*          (max conflicts before rate limiting)   */
+#define RATE_LIMIT_INTERVAL      60  /* seconds  (delay between successive attempts)    */
+#define DEFEND_INTERVAL          10  /* seconds  (min. wait between defensive ARPs)     */
+
+/* AutoIP client states */
+#define AUTOIP_STATE_OFF         0
+#define AUTOIP_STATE_PROBING     1
+#define AUTOIP_STATE_ANNOUNCING  2
+#define AUTOIP_STATE_BOUND       3
+
+struct autoip
+{
+  struct ip_addr llipaddr;  /* the currently selected, probed, announced or used LL IP-Address */
+  u8_t state;               /* current AutoIP state machine state */
+  u8_t sent_num;            /* sent number of probes or announces, dependent on state */
+  u16_t ttw;                /* ticks to wait, tick is AUTOIP_TMR_INTERVAL long */
+  u8_t lastconflict;        /* ticks until a conflict can be solved by defending */
+  u8_t tried_llipaddr;      /* total number of probed/used Link Local IP-Addresses */
+};
+
+
+/** Init srand, has to be called before entering mainloop */
+void autoip_init(void);
+
+/** Start AutoIP client */
+err_t autoip_start(struct netif *netif);
+
+/** Stop AutoIP client */
+err_t autoip_stop(struct netif *netif);
+
+/** Handles every incoming ARP Packet, called by etharp_arp_input */
+void autoip_arp_reply(struct netif *netif, struct etharp_hdr *hdr);
+
+/** Has to be called in loop every AUTOIP_TMR_INTERVAL milliseconds */
+void autoip_tmr(void);
+
+#endif /* LWIP_AUTOIP */
+
+#endif /* __LWIP_AUTOIP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/icmp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/icmp.h
new file mode 100644
index 0000000..39835cb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/icmp.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ICMP_H__
+#define __LWIP_ICMP_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ICMP_ER 0      /* echo reply */
+#define ICMP_DUR 3     /* destination unreachable */
+#define ICMP_SQ 4      /* source quench */
+#define ICMP_RD 5      /* redirect */
+#define ICMP_ECHO 8    /* echo */
+#define ICMP_TE 11     /* time exceeded */
+#define ICMP_PP 12     /* parameter problem */
+#define ICMP_TS 13     /* timestamp */
+#define ICMP_TSR 14    /* timestamp reply */
+#define ICMP_IRQ 15    /* information request */
+#define ICMP_IR 16     /* information reply */
+
+enum icmp_dur_type {
+  ICMP_DUR_NET = 0,    /* net unreachable */
+  ICMP_DUR_HOST = 1,   /* host unreachable */
+  ICMP_DUR_PROTO = 2,  /* protocol unreachable */
+  ICMP_DUR_PORT = 3,   /* port unreachable */
+  ICMP_DUR_FRAG = 4,   /* fragmentation needed and DF set */
+  ICMP_DUR_SR = 5      /* source route failed */
+};
+
+enum icmp_te_type {
+  ICMP_TE_TTL = 0,     /* time to live exceeded in transit */
+  ICMP_TE_FRAG = 1     /* fragment reassembly time exceeded */
+};
+
+void icmp_input(struct pbuf *p, struct netif *inp);
+
+void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
+void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+#if (defined(__MWERKS__)  || defined(__CWCC__))
+	#pragma options align= packed
+#endif
+struct icmp_echo_hdr {
+  PACK_STRUCT_FIELD(u16_t _type_code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u16_t id);
+  PACK_STRUCT_FIELD(u16_t seqno);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+
+PACK_STRUCT_BEGIN
+#if (defined(__MWERKS__)  || defined(__CWCC__))
+	#pragma options align= packed
+#endif
+struct icmp_dur_hdr {
+  PACK_STRUCT_FIELD(u16_t _type_code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u32_t unused);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+
+PACK_STRUCT_BEGIN
+#if (defined(__MWERKS__)  || defined(__CWCC__))
+	#pragma options align= packed
+#endif
+struct icmp_te_hdr {
+  PACK_STRUCT_FIELD(u16_t _type_code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u32_t unused);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define ICMPH_TYPE(hdr) (ntohs((hdr)->_type_code) >> 8)
+#define ICMPH_CODE(hdr) (ntohs((hdr)->_type_code) & 0xff)
+
+#define ICMPH_TYPE_SET(hdr, type) ((hdr)->_type_code = htons(ICMPH_CODE(hdr) | ((type) << 8)))
+#define ICMPH_CODE_SET(hdr, code) ((hdr)->_type_code = htons((code) | (ICMPH_TYPE(hdr) << 8)))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_ICMP */
+
+#endif /* __LWIP_ICMP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/igmp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/igmp.h
new file mode 100644
index 0000000..f942209
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/igmp.h
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2002 CITEL Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS''
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is a contribution to the lwIP TCP/IP stack.
+ * The Swedish Institute of Computer Science and Adam Dunkels
+ * are specifically granted permission to redistribute this
+ * source code.
+*/
+
+#ifndef __LWIP_IGMP_H__
+#define __LWIP_IGMP_H__
+
+#include "lwip/opt.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/pbuf.h"
+
+#if LWIP_IGMP /* don't build if not configured for use in lwipopts.h */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * IGMP constants
+ */
+#define IP_PROTO_IGMP                  2
+#define IGMP_TTL                       1
+#define IGMP_MINLEN                    8
+#define ROUTER_ALERT                   0x9404
+#define ROUTER_ALERTLEN                4
+
+/*
+ * IGMP message types, including version number.
+ */
+#define IGMP_MEMB_QUERY                0x11 /* Membership query         */
+#define IGMP_V1_MEMB_REPORT            0x12 /* Ver. 1 membership report */
+#define IGMP_V2_MEMB_REPORT            0x16 /* Ver. 2 membership report */
+#define IGMP_LEAVE_GROUP               0x17 /* Leave-group message      */
+
+/* IGMP timer */
+#define IGMP_TMR_INTERVAL              100 /* Milliseconds */
+#define IGMP_V1_DELAYING_MEMBER_TMR   (1000/IGMP_TMR_INTERVAL)
+#define IGMP_JOIN_DELAYING_MEMBER_TMR (500 /IGMP_TMR_INTERVAL)
+
+/* MAC Filter Actions */
+#define IGMP_DEL_MAC_FILTER            0
+#define IGMP_ADD_MAC_FILTER            1
+
+/* Group  membership states */
+#define IGMP_GROUP_NON_MEMBER          0
+#define IGMP_GROUP_DELAYING_MEMBER     1
+#define IGMP_GROUP_IDLE_MEMBER         2
+
+/*
+ * IGMP packet format.
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+#if (defined(__MWERKS__)  || defined(__CWCC__))
+	#pragma options align= packed
+#endif
+struct igmp_msg {
+ PACK_STRUCT_FIELD(u8_t           igmp_msgtype);
+ PACK_STRUCT_FIELD(u8_t           igmp_maxresp);
+ PACK_STRUCT_FIELD(u16_t          igmp_checksum);
+ PACK_STRUCT_FIELD(struct ip_addr igmp_group_address);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/*
+ * now a group structure - there is
+ * a list of groups for each interface
+ * these should really be linked from the interface, but
+ * if we keep them separate we will not affect the lwip original code
+ * too much
+ *
+ * There will be a group for the all systems group address but this
+ * will not run the state machine as it is used to kick off reports
+ * from all the other groups
+ */
+
+struct igmp_group {
+  struct igmp_group *next;
+  struct netif      *interface;
+  struct ip_addr     group_address;
+  u8_t               last_reporter_flag; /* signifies we were the last person to report */
+  u8_t               group_state;
+  u16_t              timer;
+  u8_t               use; /* counter of simultaneous uses */
+};
+
+
+/*  Prototypes */
+void   igmp_init(void);
+
+err_t  igmp_start( struct netif *netif);
+
+err_t  igmp_stop( struct netif *netif);
+
+void   igmp_report_groups( struct netif *netif);
+
+struct igmp_group *igmp_lookfor_group( struct netif *ifp, struct ip_addr *addr);
+
+struct igmp_group *igmp_lookup_group( struct netif *ifp, struct ip_addr *addr);
+
+err_t  igmp_remove_group( struct igmp_group *group);
+
+void   igmp_input( struct pbuf *p, struct netif *inp, struct ip_addr *dest);
+
+err_t  igmp_joingroup( struct ip_addr *ifaddr, struct ip_addr *groupaddr);
+
+err_t  igmp_leavegroup( struct ip_addr *ifaddr, struct ip_addr *groupaddr);
+
+void   igmp_tmr(void);
+
+void   igmp_timeout( struct igmp_group *group);
+
+void   igmp_start_timer( struct igmp_group *group, u8_t max_time);
+
+void   igmp_stop_timer( struct igmp_group *group);
+
+void   igmp_delaying_member( struct igmp_group *group, u8_t maxresp);
+
+err_t  igmp_ip_output_if( struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, u8_t ttl, u8_t proto, struct netif *netif);
+
+void   igmp_send( struct igmp_group *group, u8_t type);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IGMP */
+
+#endif /* __LWIP_IGMP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/inet.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/inet.h
new file mode 100644
index 0000000..2779a00
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/inet.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_INET_H__
+#define __LWIP_INET_H__
+
+#include "lwip/opt.h"
+
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+u32_t inet_addr(const char *cp);
+int inet_aton(const char *cp, struct in_addr *addr);
+char *inet_ntoa(struct in_addr addr); /* returns ptr to static buffer; not reentrant! */
+
+#ifdef htons
+#undef htons
+#endif /* htons */
+#ifdef htonl
+#undef htonl
+#endif /* htonl */
+#ifdef ntohs
+#undef ntohs
+#endif /* ntohs */
+#ifdef ntohl
+#undef ntohl
+#endif /* ntohl */
+
+#ifndef LWIP_PLATFORM_BYTESWAP
+#define LWIP_PLATFORM_BYTESWAP 0
+#endif
+
+#if BYTE_ORDER == BIG_ENDIAN
+#define htons(x) (x)
+#define ntohs(x) (x)
+#define htonl(x) (x)
+#define ntohl(x) (x)
+#else /* BYTE_ORDER != BIG_ENDIAN */
+#ifdef LWIP_PREFIX_BYTEORDER_FUNCS
+/* workaround for naming collisions on some platforms */
+#define htons lwip_htons
+#define ntohs lwip_ntohs
+#define htonl lwip_htonl
+#define ntohl lwip_ntohl
+#endif /* LWIP_PREFIX_BYTEORDER_FUNCS */
+#if LWIP_PLATFORM_BYTESWAP
+#define htons(x) LWIP_PLATFORM_HTONS(x)
+#define ntohs(x) LWIP_PLATFORM_HTONS(x)
+#define htonl(x) LWIP_PLATFORM_HTONL(x)
+#define ntohl(x) LWIP_PLATFORM_HTONL(x)
+#else /* LWIP_PLATFORM_BYTESWAP */
+u16_t htons(u16_t x);
+u16_t ntohs(u16_t x);
+u32_t htonl(u32_t x);
+u32_t ntohl(u32_t x);
+#endif /* LWIP_PLATFORM_BYTESWAP */
+
+#endif /* BYTE_ORDER == BIG_ENDIAN */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_INET_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/inet_chksum.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/inet_chksum.h
new file mode 100644
index 0000000..7a381a0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/inet_chksum.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_INET_CHKSUM_H__
+#define __LWIP_INET_CHKSUM_H__
+
+#include "lwip/opt.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+u16_t inet_chksum(void *dataptr, u16_t len);
+u16_t inet_chksum_pbuf(struct pbuf *p);
+u16_t inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u16_t proto_len);
+u16_t inet_chksum_pseudo_partial(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u16_t proto_len, u16_t chksum_len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_INET_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/ip.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/ip.h
new file mode 100644
index 0000000..946837d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/ip.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_H__
+#define __LWIP_IP_H__
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ip_init() /* Compatibility define, not init needed. */
+struct netif *ip_route(struct ip_addr *dest);
+err_t ip_input(struct pbuf *p, struct netif *inp);
+err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+    u8_t ttl, u8_t tos, u8_t proto);
+err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+       u8_t ttl, u8_t tos, u8_t proto,
+       struct netif *netif);
+
+#define IP_HLEN 20
+
+#define IP_PROTO_ICMP    1
+#define IP_PROTO_UDP     17
+#define IP_PROTO_UDPLITE 136
+#define IP_PROTO_TCP     6
+
+/* This is passed as the destination address to ip_output_if (not
+   to ip_output), meaning that an IP header already is constructed
+   in the pbuf. This is used when TCP retransmits. */
+#ifdef IP_HDRINCL
+#undef IP_HDRINCL
+#endif /* IP_HDRINCL */
+#define IP_HDRINCL  NULL
+
+#if LWIP_NETIF_HWADDRHINT
+#define IP_PCB_ADDRHINT ;u8_t addr_hint
+#else
+#define IP_PCB_ADDRHINT
+#endif /* LWIP_NETIF_HWADDRHINT */
+
+/* This is the common part of all PCB types. It needs to be at the
+   beginning of a PCB type definition. It is located here so that
+   changes to this common part are made in one location instead of
+   having to change all PCB structs. */
+#define IP_PCB \
+  /* ip addresses in network byte order */ \
+  struct ip_addr local_ip; \
+  struct ip_addr remote_ip; \
+   /* Socket options */  \
+  u16_t so_options;      \
+   /* Type Of Service */ \
+  u8_t tos;              \
+  /* Time To Live */     \
+  u8_t ttl               \
+  /* link layer address resolution hint */ \
+  IP_PCB_ADDRHINT
+
+struct ip_pcb {
+/* Common members of all PCB types */
+  IP_PCB;
+};
+
+/*
+ * Option flags per-socket. These are the same like SO_XXX.
+ */
+#define SOF_DEBUG       (u16_t)0x0001U    /* turn on debugging info recording */
+#define SOF_ACCEPTCONN  (u16_t)0x0002U    /* socket has had listen() */
+#define SOF_REUSEADDR   (u16_t)0x0004U    /* allow local address reuse */
+#define SOF_KEEPALIVE   (u16_t)0x0008U    /* keep connections alive */
+#define SOF_DONTROUTE   (u16_t)0x0010U    /* just use interface addresses */
+#define SOF_BROADCAST   (u16_t)0x0020U    /* permit sending of broadcast msgs */
+#define SOF_USELOOPBACK (u16_t)0x0040U    /* bypass hardware when possible */
+#define SOF_LINGER      (u16_t)0x0080U    /* linger on close if data present */
+#define SOF_OOBINLINE   (u16_t)0x0100U    /* leave received OOB data in line */
+#define SOF_REUSEPORT   (u16_t)0x0200U    /* allow local address & port reuse */
+
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+#if (defined(__MWERKS__)  || defined(__CWCC__))
+	#pragma options align= packed
+#endif
+struct ip_hdr {
+  /* version / header length / type of service */
+  PACK_STRUCT_FIELD(u16_t _v_hl_tos);
+  /* total length */
+  PACK_STRUCT_FIELD(u16_t _len);
+  /* identification */
+  PACK_STRUCT_FIELD(u16_t _id);
+  /* fragment offset field */
+  PACK_STRUCT_FIELD(u16_t _offset);
+#define IP_RF 0x8000        /* reserved fragment flag */
+#define IP_DF 0x4000        /* dont fragment flag */
+#define IP_MF 0x2000        /* more fragments flag */
+#define IP_OFFMASK 0x1fff   /* mask for fragmenting bits */
+  /* time to live / protocol*/
+  PACK_STRUCT_FIELD(u16_t _ttl_proto);
+  /* checksum */
+  PACK_STRUCT_FIELD(u16_t _chksum);
+  /* source and destination IP addresses */
+  PACK_STRUCT_FIELD(struct ip_addr src);
+  PACK_STRUCT_FIELD(struct ip_addr dest);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define IPH_V(hdr)  (ntohs((hdr)->_v_hl_tos) >> 12)
+#define IPH_HL(hdr) ((ntohs((hdr)->_v_hl_tos) >> 8) & 0x0f)
+#define IPH_TOS(hdr) (ntohs((hdr)->_v_hl_tos) & 0xff)
+#define IPH_LEN(hdr) ((hdr)->_len)
+#define IPH_ID(hdr) ((hdr)->_id)
+#define IPH_OFFSET(hdr) ((hdr)->_offset)
+#define IPH_TTL(hdr) (ntohs((hdr)->_ttl_proto) >> 8)
+#define IPH_PROTO(hdr) (ntohs((hdr)->_ttl_proto) & 0xff)
+#define IPH_CHKSUM(hdr) ((hdr)->_chksum)
+
+#define IPH_VHLTOS_SET(hdr, v, hl, tos) (hdr)->_v_hl_tos = (htons(((v) << 12) | ((hl) << 8) | (tos)))
+#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len)
+#define IPH_ID_SET(hdr, id) (hdr)->_id = (id)
+#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off)
+#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl_proto = (htons(IPH_PROTO(hdr) | ((u16_t)(ttl) << 8)))
+#define IPH_PROTO_SET(hdr, proto) (hdr)->_ttl_proto = (htons((proto) | (IPH_TTL(hdr) << 8)))
+#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum)
+
+#if IP_DEBUG
+void ip_debug_print(struct pbuf *p);
+#else
+#define ip_debug_print(p)
+#endif /* IP_DEBUG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_IP_H__ */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/ip_addr.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/ip_addr.h
new file mode 100644
index 0000000..acc51e3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/ip_addr.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_ADDR_H__
+#define __LWIP_IP_ADDR_H__
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+#if (defined(__MWERKS__)  || defined(__CWCC__))
+	#pragma options align= packed
+#endif
+struct ip_addr {
+  PACK_STRUCT_FIELD(u32_t addr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/*
+ * struct ipaddr2 is used in the definition of the ARP packet format in
+ * order to support compilers that don't have structure packing.
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+#if (defined(__MWERKS__)  || defined(__CWCC__))
+	#pragma options align= packed
+#endif
+struct ip_addr2 {
+  PACK_STRUCT_FIELD(u16_t addrw[2]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/* For compatibility with BSD code */
+struct in_addr {
+  u32_t s_addr;
+};
+
+struct netif;
+
+extern const struct ip_addr ip_addr_any;
+extern const struct ip_addr ip_addr_broadcast;
+
+/** IP_ADDR_ can be used as a fixed IP address
+ *  for the wildcard and the broadcast address
+ */
+#define IP_ADDR_ANY         ((struct ip_addr *)&ip_addr_any)
+#define IP_ADDR_BROADCAST   ((struct ip_addr *)&ip_addr_broadcast)
+
+#define INADDR_NONE         ((u32_t)0xffffffffUL)  /* 255.255.255.255 */
+#define INADDR_LOOPBACK     ((u32_t)0x7f000001UL)  /* 127.0.0.1 */
+
+/* Definitions of the bits in an Internet address integer.
+
+   On subnets, host and network parts are found according to
+   the subnet mask, not these masks.  */
+
+#define IN_CLASSA(a)        ((((u32_t)(a)) & 0x80000000UL) == 0)
+#define IN_CLASSA_NET       0xff000000
+#define IN_CLASSA_NSHIFT    24
+#define IN_CLASSA_HOST      (0xffffffff & ~IN_CLASSA_NET)
+#define IN_CLASSA_MAX       128
+
+#define IN_CLASSB(a)        ((((u32_t)(a)) & 0xc0000000UL) == 0x80000000UL)
+#define IN_CLASSB_NET       0xffff0000
+#define IN_CLASSB_NSHIFT    16
+#define IN_CLASSB_HOST      (0xffffffff & ~IN_CLASSB_NET)
+#define IN_CLASSB_MAX       65536
+
+#define IN_CLASSC(a)        ((((u32_t)(a)) & 0xe0000000UL) == 0xc0000000UL)
+#define IN_CLASSC_NET       0xffffff00
+#define IN_CLASSC_NSHIFT    8
+#define IN_CLASSC_HOST      (0xffffffff & ~IN_CLASSC_NET)
+
+#define IN_CLASSD(a)        (((u32_t)(a) & 0xf0000000UL) == 0xe0000000UL)
+#define IN_CLASSD_NET       0xf0000000          /* These ones aren't really */
+#define IN_CLASSD_NSHIFT    28                  /*   net and host fields, but */
+#define IN_CLASSD_HOST      0x0fffffff          /*   routing needn't know. */
+#define IN_MULTICAST(a)     IN_CLASSD(a)
+
+#define IN_EXPERIMENTAL(a)  (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL)
+#define IN_BADCLASS(a)      (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL)
+
+#define IN_LOOPBACKNET      127                 /* official! */
+
+#define IP4_ADDR(ipaddr, a,b,c,d) \
+        (ipaddr)->addr = htonl(((u32_t)((a) & 0xff) << 24) | \
+                               ((u32_t)((b) & 0xff) << 16) | \
+                               ((u32_t)((c) & 0xff) << 8) | \
+                                (u32_t)((d) & 0xff))
+
+#define ip_addr_set(dest, src) (dest)->addr = \
+                               ((src) == NULL? 0:\
+                               (src)->addr)
+/**
+ * Determine if two address are on the same network.
+ *
+ * @arg addr1 IP address 1
+ * @arg addr2 IP address 2
+ * @arg mask network identifier mask
+ * @return !0 if the network identifiers of both address match
+ */
+#define ip_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \
+                                              (mask)->addr) == \
+                                             ((addr2)->addr & \
+                                              (mask)->addr))
+#define ip_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr)
+
+#define ip_addr_isany(addr1) ((addr1) == NULL || (addr1)->addr == 0)
+
+u8_t ip_addr_isbroadcast(struct ip_addr *, struct netif *);
+
+#define ip_addr_ismulticast(addr1) (((addr1)->addr & ntohl(0xf0000000UL)) == ntohl(0xe0000000UL))
+
+#define ip_addr_islinklocal(addr1) (((addr1)->addr & ntohl(0xffff0000UL)) == ntohl(0xa9fe0000UL))
+
+#define ip_addr_debug_print(debug, ipaddr) \
+        LWIP_DEBUGF(debug, ("%"U16_F".%"U16_F".%"U16_F".%"U16_F, \
+                ipaddr ? (u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff : 0, \
+                ipaddr ? (u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff : 0, \
+                ipaddr ? (u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff : 0, \
+                ipaddr ? (u16_t)ntohl((ipaddr)->addr) & 0xff : 0))
+
+/* These are cast to u16_t, with the intent that they are often arguments
+ * to printf using the U16_F format from cc.h. */
+#define ip4_addr1(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff)
+#define ip4_addr2(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff)
+#define ip4_addr3(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff)
+#define ip4_addr4(ipaddr) ((u16_t)(ntohl((ipaddr)->addr)) & 0xff)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_IP_ADDR_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/ip_frag.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/ip_frag.h
new file mode 100644
index 0000000..a025ca1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv4/lwip/ip_frag.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Jani Monoses 
+ *
+ */
+
+#ifndef __LWIP_IP_FRAG_H__
+#define __LWIP_IP_FRAG_H__
+
+#include "lwip/opt.h"
+#include "lwip/err.h"
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/ip_addr.h"
+#include "lwip/ip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if IP_REASSEMBLY
+/* The IP reassembly timer interval in milliseconds. */
+#define IP_TMR_INTERVAL 1000
+
+/* IP reassembly helper struct.
+ * This is exported because memp needs to know the size.
+ */
+struct ip_reassdata {
+  struct ip_reassdata *next;
+  struct pbuf *p;
+  struct ip_hdr iphdr;
+  u16_t datagram_len;
+  u8_t flags;
+  u8_t timer;
+};
+
+void ip_reass_init(void);
+void ip_reass_tmr(void);
+struct pbuf * ip_reass(struct pbuf *p);
+#endif /* IP_REASSEMBLY */
+
+#if IP_FRAG
+err_t ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest);
+#endif /* IP_FRAG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_IP_FRAG_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv6/lwip/icmp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv6/lwip/icmp.h
new file mode 100644
index 0000000..cbdf07a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv6/lwip/icmp.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ICMP_H__
+#define __LWIP_ICMP_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ICMP6_DUR  1
+#define ICMP6_TE   3
+#define ICMP6_ECHO 128    /* echo */
+#define ICMP6_ER   129      /* echo reply */
+
+
+enum icmp_dur_type {
+  ICMP_DUR_NET = 0,    /* net unreachable */
+  ICMP_DUR_HOST = 1,   /* host unreachable */
+  ICMP_DUR_PROTO = 2,  /* protocol unreachable */
+  ICMP_DUR_PORT = 3,   /* port unreachable */
+  ICMP_DUR_FRAG = 4,   /* fragmentation needed and DF set */
+  ICMP_DUR_SR = 5      /* source route failed */
+};
+
+enum icmp_te_type {
+  ICMP_TE_TTL = 0,     /* time to live exceeded in transit */
+  ICMP_TE_FRAG = 1     /* fragment reassembly time exceeded */
+};
+
+void icmp_input(struct pbuf *p, struct netif *inp);
+
+void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
+void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
+
+struct icmp_echo_hdr {
+  u8_t type;
+  u8_t icode;
+  u16_t chksum;
+  u16_t id;
+  u16_t seqno;
+};
+
+struct icmp_dur_hdr {
+  u8_t type;
+  u8_t icode;
+  u16_t chksum;
+  u32_t unused;
+};
+
+struct icmp_te_hdr {
+  u8_t type;
+  u8_t icode;
+  u16_t chksum;
+  u32_t unused;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_ICMP */
+
+#endif /* __LWIP_ICMP_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv6/lwip/inet.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv6/lwip/inet.h
new file mode 100644
index 0000000..216ebd7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv6/lwip/inet.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_INET_H__
+#define __LWIP_INET_H__
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+u16_t inet_chksum(void *data, u16_t len);
+u16_t inet_chksum_pbuf(struct pbuf *p);
+u16_t inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u32_t proto_len);
+
+u32_t inet_addr(const char *cp);
+s8_t inet_aton(const char *cp, struct in_addr *addr);
+
+#ifndef _MACHINE_ENDIAN_H_
+#ifndef _NETINET_IN_H
+#ifndef _LINUX_BYTEORDER_GENERIC_H
+u16_t htons(u16_t n);
+u16_t ntohs(u16_t n);
+u32_t htonl(u32_t n);
+u32_t ntohl(u32_t n);
+#endif /* _LINUX_BYTEORDER_GENERIC_H */
+#endif /* _NETINET_IN_H */
+#endif /* _MACHINE_ENDIAN_H_ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_INET_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv6/lwip/ip.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv6/lwip/ip.h
new file mode 100644
index 0000000..e73bf4b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv6/lwip/ip.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_H__
+#define __LWIP_IP_H__
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IP_HLEN 40
+
+#define IP_PROTO_ICMP    58
+#define IP_PROTO_UDP     17
+#define IP_PROTO_UDPLITE 136
+#define IP_PROTO_TCP     6
+
+/* This is passed as the destination address to ip_output_if (not
+   to ip_output), meaning that an IP header already is constructed
+   in the pbuf. This is used when TCP retransmits. */
+#ifdef IP_HDRINCL
+#undef IP_HDRINCL
+#endif /* IP_HDRINCL */
+#define IP_HDRINCL  NULL
+
+#if LWIP_NETIF_HWADDRHINT
+#define IP_PCB_ADDRHINT ;u8_t addr_hint
+#else
+#define IP_PCB_ADDRHINT
+#endif /* LWIP_NETIF_HWADDRHINT */
+
+/* This is the common part of all PCB types. It needs to be at the
+   beginning of a PCB type definition. It is located here so that
+   changes to this common part are made in one location instead of
+   having to change all PCB structs. */
+#define IP_PCB struct ip_addr local_ip; \
+  struct ip_addr remote_ip; \
+   /* Socket options */  \
+  u16_t so_options;      \
+   /* Type Of Service */ \
+  u8_t tos;              \
+  /* Time To Live */     \
+  u8_t ttl;              \
+  /* link layer address resolution hint */ \
+  IP_PCB_ADDRHINT
+
+
+/* The IPv6 header. */
+struct ip_hdr {
+#if BYTE_ORDER == LITTLE_ENDIAN
+  u8_t tclass1:4, v:4;
+  u8_t flow1:4, tclass2:4;  
+#else
+  u8_t v:4, tclass1:4;
+  u8_t tclass2:8, flow1:4;
+#endif
+  u16_t flow2;
+  u16_t len;                /* payload length */
+  u8_t nexthdr;             /* next header */
+  u8_t hoplim;              /* hop limit (TTL) */
+  struct ip_addr src, dest;          /* source and destination IP addresses */
+};
+
+#define IPH_PROTO(hdr) (iphdr->nexthdr)
+
+void ip_init(void);
+
+#include "lwip/netif.h"
+
+struct netif *ip_route(struct ip_addr *dest);
+
+void ip_input(struct pbuf *p, struct netif *inp);
+
+/* source and destination addresses in network byte order, please */
+err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+         u8_t ttl, u8_t proto);
+
+err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+      u8_t ttl, u8_t proto,
+      struct netif *netif);
+
+#if IP_DEBUG
+void ip_debug_print(struct pbuf *p);
+#endif /* IP_DEBUG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_IP_H__ */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv6/lwip/ip_addr.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv6/lwip/ip_addr.h
new file mode 100644
index 0000000..6aeba20
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/ipv6/lwip/ip_addr.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_ADDR_H__
+#define __LWIP_IP_ADDR_H__
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IP_ADDR_ANY 0
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+#if (defined(__MWERKS__)  || defined(__CWCC__))
+	#pragma options align= packed
+#endif
+ struct ip_addr {
+  PACK_STRUCT_FIELD(u32_t addr[4]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/*
+ * struct ipaddr2 is used in the definition of the ARP packet format in
+ * order to support compilers that don't have structure packing.
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+#if (defined(__MWERKS__)  || defined(__CWCC__))
+	#pragma options align= packed
+#endif
+struct ip_addr2 {
+  PACK_STRUCT_FIELD(u16_t addrw[2]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define IP6_ADDR(ipaddr, a,b,c,d,e,f,g,h) do { (ipaddr)->addr[0] = htonl((u32_t)((a & 0xffff) << 16) | (b & 0xffff)); \
+                                               (ipaddr)->addr[1] = htonl(((c & 0xffff) << 16) | (d & 0xffff)); \
+                                               (ipaddr)->addr[2] = htonl(((e & 0xffff) << 16) | (f & 0xffff)); \
+                                               (ipaddr)->addr[3] = htonl(((g & 0xffff) << 16) | (h & 0xffff)); } while(0)
+
+u8_t ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2,
+        struct ip_addr *mask);
+u8_t ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2);
+void ip_addr_set(struct ip_addr *dest, struct ip_addr *src);
+u8_t ip_addr_isany(struct ip_addr *addr);
+
+#define ip_addr_debug_print(debug, ipaddr) \
+        LWIP_DEBUGF(debug, ("%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F"\n", \
+         (ntohl(ipaddr->addr[0]) >> 16) & 0xffff, \
+         ntohl(ipaddr->addr[0]) & 0xffff, \
+         (ntohl(ipaddr->addr[1]) >> 16) & 0xffff, \
+         ntohl(ipaddr->addr[1]) & 0xffff, \
+         (ntohl(ipaddr->addr[2]) >> 16) & 0xffff, \
+         ntohl(ipaddr->addr[2]) & 0xffff, \
+         (ntohl(ipaddr->addr[3]) >> 16) & 0xffff, \
+         ntohl(ipaddr->addr[3]) & 0xffff));
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_IP_ADDR_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/api.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/api.h
new file mode 100644
index 0000000..c26dada
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/api.h
@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_API_H__
+#define __LWIP_API_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netbuf.h"
+#include "lwip/sys.h"
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Throughout this file, IP addresses and port numbers are expected to be in
+ * the same byte order as in the corresponding pcb.
+ */
+
+/* Flags for netconn_write */
+#define NETCONN_NOFLAG 0x00
+#define NETCONN_NOCOPY 0x00 /* Only for source code compatibility */
+#define NETCONN_COPY   0x01
+#define NETCONN_MORE   0x02
+
+/* Helpers to process several netconn_types by the same code */
+#define NETCONNTYPE_GROUP(t)    (t&0xF0)
+#define NETCONNTYPE_DATAGRAM(t) (t&0xE0)
+
+enum netconn_type {
+  NETCONN_INVALID    = 0,
+  /* NETCONN_TCP Group */
+  NETCONN_TCP        = 0x10,
+  /* NETCONN_UDP Group */
+  NETCONN_UDP        = 0x20,
+  NETCONN_UDPLITE    = 0x21,
+  NETCONN_UDPNOCHKSUM= 0x22,
+  /* NETCONN_RAW Group */
+  NETCONN_RAW        = 0x40
+};
+
+enum netconn_state {
+  NETCONN_NONE,
+  NETCONN_WRITE,
+  NETCONN_LISTEN,
+  NETCONN_CONNECT,
+  NETCONN_CLOSE
+};
+
+enum netconn_evt {
+  NETCONN_EVT_RCVPLUS,
+  NETCONN_EVT_RCVMINUS,
+  NETCONN_EVT_SENDPLUS,
+  NETCONN_EVT_SENDMINUS
+};
+
+#if LWIP_IGMP
+enum netconn_igmp {
+  NETCONN_JOIN,
+  NETCONN_LEAVE
+};
+#endif /* LWIP_IGMP */
+
+/* forward-declare some structs to avoid to include their headers */
+struct ip_pcb;
+struct tcp_pcb;
+struct udp_pcb;
+struct raw_pcb;
+struct netconn;
+
+/** A callback prototype to inform about events for a netconn */
+typedef void (* netconn_callback)(struct netconn *, enum netconn_evt, u16_t len);
+
+/** A netconn descriptor */
+struct netconn {
+  /** type of the netconn (TCP, UDP or RAW) */
+  enum netconn_type type;
+  /** current state of the netconn */
+  enum netconn_state state;
+  /** the lwIP internal protocol control block */
+  union {
+    struct ip_pcb  *ip;
+    struct tcp_pcb *tcp;
+    struct udp_pcb *udp;
+    struct raw_pcb *raw;
+  } pcb;
+  /** the last error this netconn had */
+  err_t err;
+  /** sem that is used to synchroneously execute functions in the core context */
+  sys_sem_t op_completed;
+  /** mbox where received packets are stored until they are fetched
+      by the netconn application thread (can grow quite big) */
+  sys_mbox_t recvmbox;
+  /** mbox where new connections are stored until processed
+      by the application thread */
+  sys_mbox_t acceptmbox;
+  /** only used for socket layer */
+  int socket;
+#if LWIP_SO_RCVTIMEO
+  /** timeout to wait for new data to be received
+      (or connections to arrive for listening netconns) */
+  int recv_timeout;
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+  /** maximum amount of bytes queued in recvmbox */
+  int recv_bufsize;
+#endif /* LWIP_SO_RCVBUF */
+  u16_t recv_avail;
+  /** TCP: when data passed to netconn_write doesn't fit into the send buffer,
+      this temporarily stores the message. */
+  struct api_msg_msg *write_msg;
+  /** TCP: when data passed to netconn_write doesn't fit into the send buffer,
+      this temporarily stores how much is already sent. */
+  int write_offset;
+#if LWIP_TCPIP_CORE_LOCKING
+  /** TCP: when data passed to netconn_write doesn't fit into the send buffer,
+      this temporarily stores whether to wake up the original application task
+      if data couldn't be sent in the first try. */
+  u8_t write_delayed;
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+  /** A callback function that is informed about events for this netconn */
+  netconn_callback callback;
+};
+
+/* Register an Network connection event */
+#define API_EVENT(c,e,l) if (c->callback) {         \
+                           (*c->callback)(c, e, l); \
+                         }
+
+/* Network connection functions: */
+#define netconn_new(t)                  netconn_new_with_proto_and_callback(t, 0, NULL)
+#define netconn_new_with_callback(t, c) netconn_new_with_proto_and_callback(t, 0, c)
+struct
+netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto,
+                                   netconn_callback callback);
+err_t             netconn_delete  (struct netconn *conn);
+enum netconn_type netconn_type    (struct netconn *conn);
+
+err_t             netconn_getaddr (struct netconn *conn,
+                                   struct ip_addr *addr,
+                                   u16_t *port,
+                                   u8_t local);
+#define netconn_peer(c,i,p) netconn_getaddr(c,i,p,0)
+#define netconn_addr(c,i,p) netconn_getaddr(c,i,p,1)
+
+err_t             netconn_bind    (struct netconn *conn,
+                                   struct ip_addr *addr,
+                                   u16_t port);
+err_t             netconn_connect (struct netconn *conn,
+                                   struct ip_addr *addr,
+                                   u16_t port);
+err_t             netconn_disconnect (struct netconn *conn);
+err_t             netconn_listen_with_backlog(struct netconn *conn, u8_t backlog);
+#define netconn_listen(conn) netconn_listen_with_backlog(conn, TCP_DEFAULT_LISTEN_BACKLOG)
+struct netconn *  netconn_accept  (struct netconn *conn);
+struct netbuf *   netconn_recv    (struct netconn *conn);
+err_t             netconn_sendto  (struct netconn *conn,
+                                   struct netbuf *buf, struct ip_addr *addr, u16_t port);
+err_t             netconn_send    (struct netconn *conn,
+                                   struct netbuf *buf);
+err_t             netconn_write   (struct netconn *conn,
+                                   const void *dataptr, int size,
+                                   u8_t apiflags);
+err_t             netconn_close   (struct netconn *conn);
+
+#if LWIP_IGMP
+err_t             netconn_join_leave_group (struct netconn *conn,
+                                            struct ip_addr *multiaddr,
+                                            struct ip_addr *interface,
+                                            enum netconn_igmp join_or_leave);
+#endif /* LWIP_IGMP */
+#if LWIP_DNS
+err_t             netconn_gethostbyname(const char *name, struct ip_addr *addr);
+#endif /* LWIP_DNS */
+
+#define netconn_err(conn)          ((conn)->err)
+#define netconn_recv_bufsize(conn) ((conn)->recv_bufsize)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_NETCONN */
+
+#endif /* __LWIP_API_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/api_msg.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/api_msg.h
new file mode 100644
index 0000000..7635f9d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/api_msg.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_API_MSG_H__
+#define __LWIP_API_MSG_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+#include "lwip/sys.h"
+#include "lwip/igmp.h"
+#include "lwip/api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* IP addresses and port numbers are expected to be in
+ * the same byte order as in the corresponding pcb.
+ */
+/** This struct includes everything that is necessary to execute a function
+    for a netconn in another thread context (mainly used to process netconns
+    in the tcpip_thread context to be thread safe). */
+struct api_msg_msg {
+  /** The netconn which to process - always needed: it includes the semaphore
+      which is used to block the application thread until the function finished. */
+  struct netconn *conn;
+  /** Depending on the executed function, one of these union members is used */
+  union {
+    /** used for do_send */
+    struct netbuf *b;
+    /** used for do_newconn */
+    struct {
+      u8_t proto;
+    } n;
+    /** used for do_bind and do_connect */
+    struct {
+      struct ip_addr *ipaddr;
+      u16_t port;
+    } bc;
+    /** used for do_getaddr */
+    struct {
+      struct ip_addr *ipaddr;
+      u16_t *port;
+      u8_t local;
+    } ad;
+    /** used for do_write */
+    struct {
+      const void *dataptr;
+      int len;
+      u8_t apiflags;
+    } w;
+    /** used ofr do_recv */
+    struct {
+      u16_t len;
+    } r;
+#if LWIP_IGMP
+    /** used for do_join_leave_group */
+    struct {
+      struct ip_addr *multiaddr;
+      struct ip_addr *interface;
+      enum netconn_igmp join_or_leave;
+    } jl;
+#endif /* LWIP_IGMP */
+#if TCP_LISTEN_BACKLOG
+    struct {
+      u8_t backlog;
+    } lb;
+#endif /* TCP_LISTEN_BACKLOG */
+  } msg;
+};
+
+/** This struct contains a function to execute in another thread context and
+    a struct api_msg_msg that serves as an argument for this function.
+    This is passed to tcpip_apimsg to execute functions in tcpip_thread context. */
+struct api_msg {
+  /** function to execute in tcpip_thread context */
+  void (* function)(struct api_msg_msg *msg);
+  /** arguments for this function */
+  struct api_msg_msg msg;
+};
+
+#if LWIP_DNS
+/** As do_gethostbyname requires more arguments but doesn't require a netconn,
+    it has its own struct (to avoid struct api_msg getting bigger than necessary).
+    do_gethostbyname must be called using tcpip_callback instead of tcpip_apimsg
+    (see netconn_gethostbyname). */
+struct dns_api_msg {
+  /** Hostname to query or dotted IP address string */
+  const char *name;
+  /** Rhe resolved address is stored here */
+  struct ip_addr *addr;
+  /** This semaphore is posted when the name is resolved, the application thread
+      should wait on it. */
+  sys_sem_t sem;
+  /** Errors are given back here */
+  err_t *err;
+};
+#endif /* LWIP_DNS */
+
+void do_newconn         ( struct api_msg_msg *msg);
+void do_delconn         ( struct api_msg_msg *msg);
+void do_bind            ( struct api_msg_msg *msg);
+void do_connect         ( struct api_msg_msg *msg);
+void do_disconnect      ( struct api_msg_msg *msg);
+void do_listen          ( struct api_msg_msg *msg);
+void do_send            ( struct api_msg_msg *msg);
+void do_recv            ( struct api_msg_msg *msg);
+void do_write           ( struct api_msg_msg *msg);
+void do_getaddr         ( struct api_msg_msg *msg);
+void do_close           ( struct api_msg_msg *msg);
+#if LWIP_IGMP
+void do_join_leave_group( struct api_msg_msg *msg);
+#endif /* LWIP_IGMP */
+
+#if LWIP_DNS
+void do_gethostbyname(void *arg);
+#endif /* LWIP_DNS */
+
+struct netconn* netconn_alloc(enum netconn_type t, netconn_callback callback);
+void netconn_free(struct netconn *conn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_NETCONN */
+
+#endif /* __LWIP_API_MSG_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/arch.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/arch.h
new file mode 100644
index 0000000..7ecca8b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/arch.h
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ARCH_H__
+#define __LWIP_ARCH_H__
+
+#ifndef LITTLE_ENDIAN
+#define LITTLE_ENDIAN 1234
+#endif
+
+#ifndef BIG_ENDIAN
+#define BIG_ENDIAN 4321
+#endif
+
+#include "arch/cc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef PACK_STRUCT_BEGIN
+#define PACK_STRUCT_BEGIN
+#endif /* PACK_STRUCT_BEGIN */
+
+#ifndef PACK_STRUCT_END
+#define PACK_STRUCT_END
+#endif /* PACK_STRUCT_END */
+
+#ifndef PACK_STRUCT_FIELD
+#define PACK_STRUCT_FIELD(x) x
+#endif /* PACK_STRUCT_FIELD */
+
+
+#ifndef LWIP_UNUSED_ARG
+#define LWIP_UNUSED_ARG(x) (void)x
+#endif /* LWIP_UNUSED_ARG */
+
+
+#ifdef LWIP_PROVIDE_ERRNO
+
+#define  EPERM     1  /* Operation not permitted */
+#define  ENOENT     2  /* No such file or directory */
+#define  ESRCH     3  /* No such process */
+#define  EINTR     4  /* Interrupted system call */
+#define  EIO     5  /* I/O error */
+#define  ENXIO     6  /* No such device or address */
+#define  E2BIG     7  /* Arg list too long */
+#define  ENOEXEC     8  /* Exec format error */
+#define  EBADF     9  /* Bad file number */
+#define  ECHILD    10  /* No child processes */
+#define  EAGAIN    11  /* Try again */
+#define  ENOMEM    12  /* Out of memory */
+#define  EACCES    13  /* Permission denied */
+#define  EFAULT    14  /* Bad address */
+#define  ENOTBLK    15  /* Block device required */
+#define  EBUSY    16  /* Device or resource busy */
+#define  EEXIST    17  /* File exists */
+#define  EXDEV    18  /* Cross-device link */
+#define  ENODEV    19  /* No such device */
+#define  ENOTDIR    20  /* Not a directory */
+#define  EISDIR    21  /* Is a directory */
+#define  EINVAL    22  /* Invalid argument */
+#define  ENFILE    23  /* File table overflow */
+#define  EMFILE    24  /* Too many open files */
+#define  ENOTTY    25  /* Not a typewriter */
+#define  ETXTBSY    26  /* Text file busy */
+#define  EFBIG    27  /* File too large */
+#define  ENOSPC    28  /* No space left on device */
+#define  ESPIPE    29  /* Illegal seek */
+#define  EROFS    30  /* Read-only file system */
+#define  EMLINK    31  /* Too many links */
+#define  EPIPE    32  /* Broken pipe */
+#define  EDOM    33  /* Math argument out of domain of func */
+#define  ERANGE    34  /* Math result not representable */
+#define  EDEADLK    35  /* Resource deadlock would occur */
+#define  ENAMETOOLONG  36  /* File name too long */
+#define  ENOLCK    37  /* No record locks available */
+#define  ENOSYS    38  /* Function not implemented */
+#define  ENOTEMPTY  39  /* Directory not empty */
+#define  ELOOP    40  /* Too many symbolic links encountered */
+#define  EWOULDBLOCK  EAGAIN  /* Operation would block */
+#define  ENOMSG    42  /* No message of desired type */
+#define  EIDRM    43  /* Identifier removed */
+#define  ECHRNG    44  /* Channel number out of range */
+#define  EL2NSYNC  45  /* Level 2 not synchronized */
+#define  EL3HLT    46  /* Level 3 halted */
+#define  EL3RST    47  /* Level 3 reset */
+#define  ELNRNG    48  /* Link number out of range */
+#define  EUNATCH    49  /* Protocol driver not attached */
+#define  ENOCSI    50  /* No CSI structure available */
+#define  EL2HLT    51  /* Level 2 halted */
+#define  EBADE    52  /* Invalid exchange */
+#define  EBADR    53  /* Invalid request descriptor */
+#define  EXFULL    54  /* Exchange full */
+#define  ENOANO    55  /* No anode */
+#define  EBADRQC    56  /* Invalid request code */
+#define  EBADSLT    57  /* Invalid slot */
+
+#define  EDEADLOCK  EDEADLK
+
+#define  EBFONT    59  /* Bad font file format */
+#define  ENOSTR    60  /* Device not a stream */
+#define  ENODATA    61  /* No data available */
+#define  ETIME    62  /* Timer expired */
+#define  ENOSR    63  /* Out of streams resources */
+#define  ENONET    64  /* Machine is not on the network */
+#define  ENOPKG    65  /* Package not installed */
+#define  EREMOTE    66  /* Object is remote */
+#define  ENOLINK    67  /* Link has been severed */
+#define  EADV    68  /* Advertise error */
+#define  ESRMNT    69  /* Srmount error */
+#define  ECOMM    70  /* Communication error on send */
+#define  EPROTO    71  /* Protocol error */
+#define  EMULTIHOP  72  /* Multihop attempted */
+#define  EDOTDOT    73  /* RFS specific error */
+#define  EBADMSG    74  /* Not a data message */
+#define  EOVERFLOW  75  /* Value too large for defined data type */
+#define  ENOTUNIQ  76  /* Name not unique on network */
+#define  EBADFD    77  /* File descriptor in bad state */
+#define  EREMCHG    78  /* Remote address changed */
+#define  ELIBACC    79  /* Can not access a needed shared library */
+#define  ELIBBAD    80  /* Accessing a corrupted shared library */
+#define  ELIBSCN    81  /* .lib section in a.out corrupted */
+#define  ELIBMAX    82  /* Attempting to link in too many shared libraries */
+#define  ELIBEXEC  83  /* Cannot exec a shared library directly */
+#define  EILSEQ    84  /* Illegal byte sequence */
+#define  ERESTART  85  /* Interrupted system call should be restarted */
+#define  ESTRPIPE  86  /* Streams pipe error */
+#define  EUSERS    87  /* Too many users */
+#define  ENOTSOCK  88  /* Socket operation on non-socket */
+#define  EDESTADDRREQ  89  /* Destination address required */
+#define  EMSGSIZE  90  /* Message too long */
+#define  EPROTOTYPE  91  /* Protocol wrong type for socket */
+#define  ENOPROTOOPT  92  /* Protocol not available */
+#define  EPROTONOSUPPORT  93  /* Protocol not supported */
+#define  ESOCKTNOSUPPORT  94  /* Socket type not supported */
+#define  EOPNOTSUPP  95  /* Operation not supported on transport endpoint */
+#define  EPFNOSUPPORT  96  /* Protocol family not supported */
+#define  EAFNOSUPPORT  97  /* Address family not supported by protocol */
+#define  EADDRINUSE  98  /* Address already in use */
+#define  EADDRNOTAVAIL  99  /* Cannot assign requested address */
+#define  ENETDOWN  100  /* Network is down */
+#define  ENETUNREACH  101  /* Network is unreachable */
+#define  ENETRESET  102  /* Network dropped connection because of reset */
+#define  ECONNABORTED  103  /* Software caused connection abort */
+#define  ECONNRESET  104  /* Connection reset by peer */
+#define  ENOBUFS    105  /* No buffer space available */
+#define  EISCONN    106  /* Transport endpoint is already connected */
+#define  ENOTCONN  107  /* Transport endpoint is not connected */
+#define  ESHUTDOWN  108  /* Cannot send after transport endpoint shutdown */
+#define  ETOOMANYREFS  109  /* Too many references: cannot splice */
+#define  ETIMEDOUT  110  /* Connection timed out */
+#define  ECONNREFUSED  111  /* Connection refused */
+#define  EHOSTDOWN  112  /* Host is down */
+#define  EHOSTUNREACH  113  /* No route to host */
+#define  EALREADY  114  /* Operation already in progress */
+#define  EINPROGRESS  115  /* Operation now in progress */
+#define  ESTALE    116  /* Stale NFS file handle */
+#define  EUCLEAN    117  /* Structure needs cleaning */
+#define  ENOTNAM    118  /* Not a XENIX named type file */
+#define  ENAVAIL    119  /* No XENIX semaphores available */
+#define  EISNAM    120  /* Is a named type file */
+#define  EREMOTEIO  121  /* Remote I/O error */
+#define  EDQUOT    122  /* Quota exceeded */
+
+#define  ENOMEDIUM  123  /* No medium found */
+#define  EMEDIUMTYPE  124  /* Wrong medium type */
+
+
+#define ENSROK    0 /* DNS server returned answer with no data */
+#define ENSRNODATA  160 /* DNS server returned answer with no data */
+#define ENSRFORMERR 161 /* DNS server claims query was misformatted */
+#define ENSRSERVFAIL 162  /* DNS server returned general failure */
+#define ENSRNOTFOUND 163  /* Domain name not found */
+#define ENSRNOTIMP  164 /* DNS server does not implement requested operation */
+#define ENSRREFUSED 165 /* DNS server refused query */
+#define ENSRBADQUERY 166  /* Misformatted DNS query */
+#define ENSRBADNAME 167 /* Misformatted domain name */
+#define ENSRBADFAMILY 168 /* Unsupported address family */
+#define ENSRBADRESP 169 /* Misformatted DNS reply */
+#define ENSRCONNREFUSED 170 /* Could not contact DNS servers */
+#define ENSRTIMEOUT 171 /* Timeout while contacting DNS servers */
+#define ENSROF    172 /* End of file */
+#define ENSRFILE  173 /* Error reading file */
+#define ENSRNOMEM 174 /* Out of memory */
+#define ENSRDESTRUCTION 175 /* Application terminated lookup */
+#define ENSRQUERYDOMAINTOOLONG  176 /* Domain name is too long */
+#define ENSRCNAMELOOP 177 /* Domain name is too long */
+
+#ifndef errno
+extern int errno;
+#endif
+
+#endif /* LWIP_PROVIDE_ERRNO */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_ARCH_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/debug.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/debug.h
new file mode 100644
index 0000000..1e468f6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/debug.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_DEBUG_H__
+#define __LWIP_DEBUG_H__
+
+#include "lwip/arch.h"
+
+/** lower two bits indicate debug level
+ * - 0 off
+ * - 1 warning
+ * - 2 serious
+ * - 3 severe
+ */
+#define LWIP_DBG_LEVEL_OFF     0x00
+#define LWIP_DBG_LEVEL_WARNING 0x01 /* bad checksums, dropped packets, ... */
+#define LWIP_DBG_LEVEL_SERIOUS 0x02 /* memory allocation failures, ... */
+#define LWIP_DBG_LEVEL_SEVERE  0x03
+#define LWIP_DBG_MASK_LEVEL    0x03
+
+/** flag for LWIP_DEBUGF to enable that debug message */
+#define LWIP_DBG_ON            0x80U
+/** flag for LWIP_DEBUGF to disable that debug message */
+#define LWIP_DBG_OFF           0x00U
+
+/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */
+#define LWIP_DBG_TRACE         0x40U
+/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */
+#define LWIP_DBG_STATE         0x20U
+/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */
+#define LWIP_DBG_FRESH         0x10U
+/** flag for LWIP_DEBUGF to halt after printing this debug message */
+#define LWIP_DBG_HALT          0x08U
+
+#ifndef LWIP_NOASSERT
+#define LWIP_ASSERT(x,y) do { if(!(y)) LWIP_PLATFORM_ASSERT(x); } while(0)
+#else  /* LWIP_NOASSERT */
+#define LWIP_ASSERT(x,y)
+#endif /* LWIP_NOASSERT */
+
+/** print "m" message only if "e" is true, and execute "h" expression */
+#ifndef LWIP_ERROR
+#define LWIP_ERROR(m,e,h) do { if (!(e)) { LWIP_PLATFORM_ASSERT(m); h;}} while(0)
+#endif /* LWIP_ERROR */
+
+#ifdef LWIP_DEBUG
+/** print debug message only if debug message type is enabled...
+ *  AND is of correct type AND is at least LWIP_DBG_LEVEL
+ */
+#define LWIP_DEBUGF(debug,x) do { \
+                               if ( \
+                                   ((debug) & LWIP_DBG_ON) && \
+                                   ((debug) & LWIP_DBG_TYPES_ON) && \
+                                   ((s16_t)((debug) & LWIP_DBG_MASK_LEVEL) >= LWIP_DBG_MIN_LEVEL)) { \
+                                 LWIP_PLATFORM_DIAG(x); \
+                                 if ((debug) & LWIP_DBG_HALT) { \
+                                   while(1); \
+                                 } \
+                               } \
+                             } while(0)
+
+#else  /* LWIP_DEBUG */
+#define LWIP_DEBUGF(debug,x)
+#endif /* LWIP_DEBUG */
+
+#endif /* __LWIP_DEBUG_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/def.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/def.h
new file mode 100644
index 0000000..f64c120
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/def.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_DEF_H__
+#define __LWIP_DEF_H__
+
+/* this might define NULL already */
+#include "lwip/arch.h"
+
+#define LWIP_MAX(x , y)  (((x) > (y)) ? (x) : (y))
+#define LWIP_MIN(x , y)  (((x) < (y)) ? (x) : (y))
+
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+
+
+#endif /* __LWIP_DEF_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/dhcp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/dhcp.h
new file mode 100644
index 0000000..1644690
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/dhcp.h
@@ -0,0 +1,249 @@
+/** @file
+ */
+
+#ifndef __LWIP_DHCP_H__
+#define __LWIP_DHCP_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_DHCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** period (in seconds) of the application calling dhcp_coarse_tmr() */
+#define DHCP_COARSE_TIMER_SECS 60
+/** period (in milliseconds) of the application calling dhcp_coarse_tmr() */
+#define DHCP_COARSE_TIMER_MSECS (DHCP_COARSE_TIMER_SECS*1000)
+/** period (in milliseconds) of the application calling dhcp_fine_tmr() */
+#define DHCP_FINE_TIMER_MSECS 500
+
+struct dhcp
+{
+  /** current DHCP state machine state */
+  u8_t state;
+  /** retries of current request */
+  u8_t tries;
+  /** transaction identifier of last sent request */
+  u32_t xid;
+  /** our connection to the DHCP server */
+  struct udp_pcb *pcb;
+  /** (first) pbuf of incoming msg */
+  struct pbuf *p;
+  /** incoming msg */
+  struct dhcp_msg *msg_in;
+  /** incoming msg options */
+  struct dhcp_msg *options_in;
+  /** ingoing msg options length */
+  u16_t options_in_len;
+
+  struct pbuf *p_out; /* pbuf of outcoming msg */
+  struct dhcp_msg *msg_out; /* outgoing msg */
+  u16_t options_out_len; /* outgoing msg options length */
+  u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */
+  u16_t t1_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */
+  u16_t t2_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */
+  struct ip_addr server_ip_addr; /* dhcp server address that offered this lease */
+  struct ip_addr offered_ip_addr;
+  struct ip_addr offered_sn_mask;
+  struct ip_addr offered_gw_addr;
+  struct ip_addr offered_bc_addr;
+#define DHCP_MAX_DNS 2
+  u32_t dns_count; /* actual number of DNS servers obtained */
+  struct ip_addr offered_dns_addr[DHCP_MAX_DNS]; /* DNS server addresses */
+
+  u32_t offered_t0_lease; /* lease period (in seconds) */
+  u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */
+  u32_t offered_t2_rebind; /* recommended rebind time (usually 66% of lease period)  */
+#if LWIP_DHCP_AUTOIP_COOP
+  u8_t autoip_coop_state;
+#endif
+/** Patch #1308
+ *  TODO: See dhcp.c "TODO"s
+ */
+#if 0
+  struct ip_addr offered_si_addr;
+  u8_t *boot_file_name;
+#endif
+};
+
+/* MUST be compiled with "pack structs" or equivalent! */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+#if (defined(__MWERKS__)  || defined(__CWCC__))
+	#pragma options align= packed
+#endif
+/** minimum set of fields of any DHCP message */
+struct dhcp_msg
+{
+  PACK_STRUCT_FIELD(u8_t op);
+  PACK_STRUCT_FIELD(u8_t htype);
+  PACK_STRUCT_FIELD(u8_t hlen);
+  PACK_STRUCT_FIELD(u8_t hops);
+  PACK_STRUCT_FIELD(u32_t xid);
+  PACK_STRUCT_FIELD(u16_t secs);
+  PACK_STRUCT_FIELD(u16_t flags);
+  PACK_STRUCT_FIELD(struct ip_addr ciaddr);
+  PACK_STRUCT_FIELD(struct ip_addr yiaddr);
+  PACK_STRUCT_FIELD(struct ip_addr siaddr);
+  PACK_STRUCT_FIELD(struct ip_addr giaddr);
+#define DHCP_CHADDR_LEN 16U
+  PACK_STRUCT_FIELD(u8_t chaddr[DHCP_CHADDR_LEN]);
+#define DHCP_SNAME_LEN 64U
+  PACK_STRUCT_FIELD(u8_t sname[DHCP_SNAME_LEN]);
+#define DHCP_FILE_LEN 128U
+  PACK_STRUCT_FIELD(u8_t file[DHCP_FILE_LEN]);
+  PACK_STRUCT_FIELD(u32_t cookie);
+#define DHCP_MIN_OPTIONS_LEN 68U
+/** make sure user does not configure this too small */
+#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN))
+#  undef DHCP_OPTIONS_LEN
+#endif
+/** allow this to be configured in lwipopts.h, but not too small */
+#if (!defined(DHCP_OPTIONS_LEN))
+/** set this to be sufficient for your options in outgoing DHCP msgs */
+#  define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN
+#endif
+  PACK_STRUCT_FIELD(u8_t options[DHCP_OPTIONS_LEN]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** start DHCP configuration */
+err_t dhcp_start(struct netif *netif);
+/** enforce early lease renewal (not needed normally)*/
+err_t dhcp_renew(struct netif *netif);
+/** release the DHCP lease, usually called before dhcp_stop()*/
+err_t dhcp_release(struct netif *netif);
+/** stop DHCP configuration */
+void dhcp_stop(struct netif *netif);
+/** inform server of our manual IP address */
+void dhcp_inform(struct netif *netif);
+
+/** if enabled, check whether the offered IP address is not in use, using ARP */
+#if DHCP_DOES_ARP_CHECK
+void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr);
+#endif
+
+/** to be called every minute */
+void dhcp_coarse_tmr(void);
+/** to be called every half second */
+void dhcp_fine_tmr(void);
+
+/** DHCP message item offsets and length */
+#define DHCP_MSG_OFS (UDP_DATA_OFS)
+  #define DHCP_OP_OFS (DHCP_MSG_OFS + 0)
+  #define DHCP_HTYPE_OFS (DHCP_MSG_OFS + 1)
+  #define DHCP_HLEN_OFS (DHCP_MSG_OFS + 2)
+  #define DHCP_HOPS_OFS (DHCP_MSG_OFS + 3)
+  #define DHCP_XID_OFS (DHCP_MSG_OFS + 4)
+  #define DHCP_SECS_OFS (DHCP_MSG_OFS + 8)
+  #define DHCP_FLAGS_OFS (DHCP_MSG_OFS + 10)
+  #define DHCP_CIADDR_OFS (DHCP_MSG_OFS + 12)
+  #define DHCP_YIADDR_OFS (DHCP_MSG_OFS + 16)
+  #define DHCP_SIADDR_OFS (DHCP_MSG_OFS + 20)
+  #define DHCP_GIADDR_OFS (DHCP_MSG_OFS + 24)
+  #define DHCP_CHADDR_OFS (DHCP_MSG_OFS + 28)
+  #define DHCP_SNAME_OFS (DHCP_MSG_OFS + 44)
+  #define DHCP_FILE_OFS (DHCP_MSG_OFS + 108)
+#define DHCP_MSG_LEN 236
+
+#define DHCP_COOKIE_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN)
+#define DHCP_OPTIONS_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN + 4)
+
+#define DHCP_CLIENT_PORT 68
+#define DHCP_SERVER_PORT 67
+
+/** DHCP client states */
+#define DHCP_REQUESTING 1
+#define DHCP_INIT 2
+#define DHCP_REBOOTING 3
+#define DHCP_REBINDING 4
+#define DHCP_RENEWING 5
+#define DHCP_SELECTING 6
+#define DHCP_INFORMING 7
+#define DHCP_CHECKING 8
+#define DHCP_PERMANENT 9
+#define DHCP_BOUND 10
+/** not yet implemented #define DHCP_RELEASING 11 */
+#define DHCP_BACKING_OFF 12
+#define DHCP_OFF 13
+
+/** AUTOIP cooperatation flags */
+#define DHCP_AUTOIP_COOP_STATE_OFF 0
+#define DHCP_AUTOIP_COOP_STATE_ON 1
+
+#define DHCP_BOOTREQUEST 1
+#define DHCP_BOOTREPLY 2
+
+#define DHCP_DISCOVER 1
+#define DHCP_OFFER 2
+#define DHCP_REQUEST 3
+#define DHCP_DECLINE 4
+#define DHCP_ACK 5
+#define DHCP_NAK 6
+#define DHCP_RELEASE 7
+#define DHCP_INFORM 8
+
+#define DHCP_HTYPE_ETH 1
+
+#define DHCP_HLEN_ETH 6
+
+#define DHCP_BROADCAST_FLAG 15
+#define DHCP_BROADCAST_MASK (1 << DHCP_FLAG_BROADCAST)
+
+/** BootP options */
+#define DHCP_OPTION_PAD 0
+#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */
+#define DHCP_OPTION_ROUTER 3
+#define DHCP_OPTION_DNS_SERVER 6
+#define DHCP_OPTION_HOSTNAME 12
+#define DHCP_OPTION_IP_TTL 23
+#define DHCP_OPTION_MTU 26
+#define DHCP_OPTION_BROADCAST 28
+#define DHCP_OPTION_TCP_TTL 37
+#define DHCP_OPTION_END 255
+
+/** DHCP options */
+#define DHCP_OPTION_REQUESTED_IP 50 /* RFC 2132 9.1, requested IP address */
+#define DHCP_OPTION_LEASE_TIME 51 /* RFC 2132 9.2, time in seconds, in 4 bytes */
+#define DHCP_OPTION_OVERLOAD 52 /* RFC2132 9.3, use file and/or sname field for options */
+
+#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */
+#define DHCP_OPTION_MESSAGE_TYPE_LEN 1
+
+
+#define DHCP_OPTION_SERVER_ID 54 /* RFC 2132 9.7, server IP address */
+#define DHCP_OPTION_PARAMETER_REQUEST_LIST 55 /* RFC 2132 9.8, requested option types */
+
+#define DHCP_OPTION_MAX_MSG_SIZE 57 /* RFC 2132 9.10, message size accepted >= 576 */
+#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2
+
+#define DHCP_OPTION_T1 58 /* T1 renewal time */
+#define DHCP_OPTION_T2 59 /* T2 rebinding time */
+#define DHCP_OPTION_US 60
+#define DHCP_OPTION_CLIENT_ID 61
+#define DHCP_OPTION_TFTP_SERVERNAME 66
+#define DHCP_OPTION_BOOTFILE 67
+
+/** possible combinations of overloading the file and sname fields with options */
+#define DHCP_OVERLOAD_NONE 0
+#define DHCP_OVERLOAD_FILE 1
+#define DHCP_OVERLOAD_SNAME  2
+#define DHCP_OVERLOAD_SNAME_FILE 3
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_DHCP */
+
+#endif /*__LWIP_DHCP_H__*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/dns.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/dns.h
new file mode 100644
index 0000000..851fe58
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/dns.h
@@ -0,0 +1,92 @@
+/**
+ * lwip DNS resolver header file.
+
+ * Author: Jim Pettinato
+ *   April 2007
+
+ * ported from uIP resolv.c Copyright (c) 2002-2003, Adam Dunkels.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __LWIP_DNS_H__
+#define __LWIP_DNS_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_DNS /* don't build if not configured for use in lwipopts.h */
+
+/** DNS timer period */
+#define DNS_TMR_INTERVAL          1000
+
+/** DNS field TYPE used for "Resource Records" */
+#define DNS_RRTYPE_A              1     /* a host address */
+#define DNS_RRTYPE_NS             2     /* an authoritative name server */
+#define DNS_RRTYPE_MD             3     /* a mail destination (Obsolete - use MX) */
+#define DNS_RRTYPE_MF             4     /* a mail forwarder (Obsolete - use MX) */
+#define DNS_RRTYPE_CNAME          5     /* the canonical name for an alias */
+#define DNS_RRTYPE_SOA            6     /* marks the start of a zone of authority */
+#define DNS_RRTYPE_MB             7     /* a mailbox domain name (EXPERIMENTAL) */
+#define DNS_RRTYPE_MG             8     /* a mail group member (EXPERIMENTAL) */
+#define DNS_RRTYPE_MR             9     /* a mail rename domain name (EXPERIMENTAL) */
+#define DNS_RRTYPE_NULL           10    /* a null RR (EXPERIMENTAL) */
+#define DNS_RRTYPE_WKS            11    /* a well known service description */
+#define DNS_RRTYPE_PTR            12    /* a domain name pointer */
+#define DNS_RRTYPE_HINFO          13    /* host information */
+#define DNS_RRTYPE_MINFO          14    /* mailbox or mail list information */
+#define DNS_RRTYPE_MX             15    /* mail exchange */
+#define DNS_RRTYPE_TXT            16    /* text strings */
+
+/** DNS field CLASS used for "Resource Records" */
+#define DNS_RRCLASS_IN            1     /* the Internet */
+#define DNS_RRCLASS_CS            2     /* the CSNET class (Obsolete - used only for examples in some obsolete RFCs) */
+#define DNS_RRCLASS_CH            3     /* the CHAOS class */
+#define DNS_RRCLASS_HS            4     /* Hesiod [Dyer 87] */
+#define DNS_RRCLASS_FLUSH         0x800 /* Flush bit */
+
+/** Callback which is invoked when a hostname is found.
+ * A function of this type must be implemented by the application using the DNS resolver.
+ * @param name pointer to the name that was looked up.
+ * @param ipaddr pointer to a struct ip_addr containing the IP address of the hostname,
+ *        or NULL if the name could not be found (or on any other error).
+ * @param callback_arg a user-specified callback argument passed to dns_gethostbyname
+*/
+typedef void (*dns_found_callback)(const char *name, struct ip_addr *ipaddr, void *callback_arg);
+
+
+void           dns_init(void);
+
+void           dns_tmr(void);
+
+void           dns_setserver(u8_t numdns, struct ip_addr *dnsserver);
+
+struct ip_addr dns_getserver(u8_t numdns);
+
+err_t          dns_gethostbyname(const char *hostname, struct ip_addr *addr,
+                                 dns_found_callback found, void *callback_arg);
+
+#endif /* LWIP_DNS */
+
+#endif /* __LWIP_DNS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/err.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/err.h
new file mode 100644
index 0000000..1685fa9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/err.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ERR_H__
+#define __LWIP_ERR_H__
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef s8_t err_t;
+
+/* Definitions for error constants. */
+
+#define ERR_OK          0    /* No error, everything OK. */
+#define ERR_MEM        -1    /* Out of memory error.     */
+#define ERR_BUF        -2    /* Buffer error.            */
+#define ERR_RTE        -3    /* Routing problem.         */
+
+#define ERR_IS_FATAL(e) ((e) < ERR_RTE)
+
+#define ERR_ABRT       -4    /* Connection aborted.      */
+#define ERR_RST        -5    /* Connection reset.        */
+#define ERR_CLSD       -6    /* Connection closed.       */
+#define ERR_CONN       -7    /* Not connected.           */
+
+#define ERR_VAL        -8    /* Illegal value.           */
+
+#define ERR_ARG        -9    /* Illegal argument.        */
+
+#define ERR_USE        -10   /* Address in use.          */
+
+#define ERR_IF         -11   /* Low-level netif error    */
+#define ERR_ISCONN     -12   /* Already connected.       */
+
+#define ERR_TIMEOUT    -13   /* Timeout.                 */
+
+#define ERR_INPROGRESS -14   /* Operation in progress    */
+
+
+#ifdef LWIP_DEBUG
+extern const char *lwip_strerr(err_t err);
+#else
+#define lwip_strerr(x) ""
+#endif /* LWIP_DEBUG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_ERR_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/init.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/init.h
new file mode 100644
index 0000000..7fe5799
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/init.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_INIT_H__
+#define __LWIP_INIT_H__
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Modules initialization */
+void lwip_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_INIT_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/mem.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/mem.h
new file mode 100644
index 0000000..21c48f8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/mem.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_MEM_H__
+#define __LWIP_MEM_H__
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if MEM_LIBC_MALLOC
+
+#include  /* for size_t */
+
+typedef size_t mem_size_t;
+
+/* aliases for C library malloc() */
+#define mem_init()
+/* in case C library malloc() needs extra protection,
+ * allow these defines to be overridden.
+ */
+#ifndef mem_free
+#define mem_free(x) free(x)
+#endif
+#ifndef mem_malloc
+#define mem_malloc(x) malloc(x)
+#endif
+#ifndef mem_calloc
+#define mem_calloc(x, y) calloc(x, y)
+#endif
+#ifndef mem_realloc
+#define mem_realloc(x, size) (x)
+#endif
+#else /* MEM_LIBC_MALLOC */
+
+/* MEM_SIZE would have to be aligned, but using 64000 here instead of
+ * 65535 leaves some room for alignment...
+ */
+#if MEM_SIZE > 64000l
+typedef u32_t mem_size_t;
+#else
+typedef u16_t mem_size_t;
+#endif /* MEM_SIZE > 64000 */
+
+#if MEM_USE_POOLS
+/** mem_init is not used when using pools instead of a heap */
+#define mem_init()
+/** mem_realloc is not used when using pools instead of a heap:
+    we can't free part of a pool element and don't want to copy the rest */
+#define mem_realloc(mem, size) (mem)
+#else /* MEM_USE_POOLS */
+/* lwIP alternative malloc */
+void  mem_init(void);
+void *mem_realloc(void *mem, mem_size_t size);
+#endif /* MEM_USE_POOLS */
+void *mem_malloc(mem_size_t size);
+void *mem_calloc(mem_size_t count, mem_size_t size);
+void  mem_free(void *mem);
+#endif /* MEM_LIBC_MALLOC */
+
+#ifndef LWIP_MEM_ALIGN_SIZE
+#define LWIP_MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1) & ~(MEM_ALIGNMENT-1))
+#endif
+
+#ifndef LWIP_MEM_ALIGN
+#define LWIP_MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1)))
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_MEM_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/memp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/memp.h
new file mode 100644
index 0000000..18f8831
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/memp.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef __LWIP_MEMP_H__
+#define __LWIP_MEMP_H__
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Create the list of all memory pools managed by memp. MEMP_MAX represents a NULL pool at the end */
+typedef enum {
+#define LWIP_MEMPOOL(name,num,size,desc)  MEMP_##name,
+#include "lwip/memp_std.h"
+  MEMP_MAX
+} memp_t;
+
+#if MEM_USE_POOLS
+/* Use a helper type to get the start and end of the user "memory pools" for mem_malloc */
+typedef enum {
+    /* Get the first (via:
+       MEMP_POOL_HELPER_START = ((u8_t) 1*MEMP_POOL_A + 0*MEMP_POOL_B + 0*MEMP_POOL_C + 0)*/
+    MEMP_POOL_HELPER_FIRST = ((u8_t)
+#define LWIP_MEMPOOL(name,num,size,desc)
+#define LWIP_MALLOC_MEMPOOL_START 1
+#define LWIP_MALLOC_MEMPOOL(num, size) * MEMP_POOL_##size + 0
+#define LWIP_MALLOC_MEMPOOL_END
+#include "lwip/memp_std.h"
+    ) ,
+    /* Get the last (via:
+       MEMP_POOL_HELPER_END = ((u8_t) 0 + MEMP_POOL_A*0 + MEMP_POOL_B*0 + MEMP_POOL_C*1) */
+    MEMP_POOL_HELPER_LAST = ((u8_t)
+#define LWIP_MEMPOOL(name,num,size,desc)
+#define LWIP_MALLOC_MEMPOOL_START
+#define LWIP_MALLOC_MEMPOOL(num, size) 0 + MEMP_POOL_##size *
+#define LWIP_MALLOC_MEMPOOL_END 1
+#include "lwip/memp_std.h"
+    )
+} memp_pool_helper_t;
+
+/* The actual start and stop values are here (cast them over)
+   We use this helper type and these defines so we can avoid using const memp_t values */
+#define MEMP_POOL_FIRST ((memp_t) MEMP_POOL_HELPER_FIRST)
+#define MEMP_POOL_LAST   ((memp_t) MEMP_POOL_HELPER_LAST)
+
+extern const u16_t memp_sizes[MEMP_MAX];
+#endif /* MEM_USE_POOLS */
+
+void  memp_init(void);
+
+#if MEMP_OVERFLOW_CHECK
+void *memp_malloc_fn(memp_t type, const char* file, const int line);
+#define memp_malloc(t) memp_malloc_fn((t), __FILE__, __LINE__)
+#else
+void *memp_malloc(memp_t type);
+#endif
+void  memp_free(memp_t type, void *mem);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_MEMP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/memp_std.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/memp_std.h
new file mode 100644
index 0000000..ac51813
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/memp_std.h
@@ -0,0 +1,101 @@
+/*
+ * SETUP: Make sure we define everything we will need.
+ *
+ * We have create three types of pools:
+ *   1) MEMPOOL - standard pools
+ *   2) MALLOC_MEMPOOL - to be used by mem_malloc in mem.c
+ *   3) PBUF_MEMPOOL - a mempool of pbuf's, so include space for the pbuf struct
+ *
+ * If the include'r doesn't require any special treatment of each of the types
+ * above, then will declare #2 & #3 to be just standard mempools.
+ */
+#ifndef LWIP_MALLOC_MEMPOOL
+/* This treats "malloc pools" just like any other pool */
+#define LWIP_MALLOC_MEMPOOL(num, size) LWIP_MEMPOOL(POOL_##size, num, size, "MALLOC_"#size)
+#define LWIP_MALLOC_MEMPOOL_START
+#define LWIP_MALLOC_MEMPOOL_END
+#endif /* LWIP_MALLOC_MEMPOOL */
+
+#ifndef LWIP_PBUF_MEMPOOL
+/* This treats "pbuf pools" just like any other pool.
+ * Allocates buffers for a pbuf struct AND a payload size */
+#define LWIP_PBUF_MEMPOOL(name, num, payload, desc) LWIP_MEMPOOL(name, num, (MEMP_ALIGN_SIZE(sizeof(struct pbuf)) + MEMP_ALIGN_SIZE(payload)), desc)
+#endif /* LWIP_PBUF_MEMPOOL */
+
+
+/*
+ * A list of internal pools used by LWIP.
+ *
+ * LWIP_MEMPOOL(pool_name, number_elements, element_size, pool_description)
+ *     creates a pool name MEMP_pool_name. description is used in stats.c
+ */
+#if LWIP_RAW
+LWIP_MEMPOOL(RAW_PCB,        MEMP_NUM_RAW_PCB,         sizeof(struct raw_pcb),        "RAW_PCB")
+#endif /* LWIP_RAW */
+
+#if LWIP_UDP
+LWIP_MEMPOOL(UDP_PCB,        MEMP_NUM_UDP_PCB,         sizeof(struct udp_pcb),        "UDP_PCB")
+#endif /* LWIP_UDP */
+
+#if LWIP_TCP
+LWIP_MEMPOOL(TCP_PCB,        MEMP_NUM_TCP_PCB,         sizeof(struct tcp_pcb),        "TCP_PCB")
+LWIP_MEMPOOL(TCP_PCB_LISTEN, MEMP_NUM_TCP_PCB_LISTEN,  sizeof(struct tcp_pcb_listen), "TCP_PCB_LISTEN")
+LWIP_MEMPOOL(TCP_SEG,        MEMP_NUM_TCP_SEG,         sizeof(struct tcp_seg),        "TCP_SEG")
+#endif /* LWIP_TCP */
+
+#if IP_REASSEMBLY
+LWIP_MEMPOOL(REASSDATA,      MEMP_NUM_REASSDATA,       sizeof(struct ip_reassdata),   "REASSDATA")
+#endif /* IP_REASSEMBLY */
+
+#if LWIP_NETCONN
+LWIP_MEMPOOL(NETBUF,         MEMP_NUM_NETBUF,          sizeof(struct netbuf),         "NETBUF")
+LWIP_MEMPOOL(NETCONN,        MEMP_NUM_NETCONN,         sizeof(struct netconn),        "NETCONN")
+#endif /* LWIP_NETCONN */
+
+#if NO_SYS==0
+LWIP_MEMPOOL(TCPIP_MSG_API,  MEMP_NUM_TCPIP_MSG_API,   sizeof(struct tcpip_msg),      "TCPIP_MSG_API")
+LWIP_MEMPOOL(TCPIP_MSG_INPKT,MEMP_NUM_TCPIP_MSG_INPKT, sizeof(struct tcpip_msg),      "TCPIP_MSG_INPKT")
+#endif /* NO_SYS==0 */
+
+#if ARP_QUEUEING
+LWIP_MEMPOOL(ARP_QUEUE,      MEMP_NUM_ARP_QUEUE,       sizeof(struct etharp_q_entry), "ARP_QUEUE")
+#endif /* ARP_QUEUEING */
+
+#if LWIP_IGMP
+LWIP_MEMPOOL(IGMP_GROUP,     MEMP_NUM_IGMP_GROUP,      sizeof(struct igmp_group),     "IGMP_GROUP")
+#endif /* LWIP_IGMP */
+
+#if NO_SYS==0
+LWIP_MEMPOOL(SYS_TIMEOUT,    MEMP_NUM_SYS_TIMEOUT,     sizeof(struct sys_timeo),      "SYS_TIMEOUT")
+#endif /* NO_SYS==0 */
+
+
+/*
+ * A list of pools of pbuf's used by LWIP.
+ *
+ * LWIP_PBUF_MEMPOOL(pool_name, number_elements, pbuf_payload_size, pool_description)
+ *     creates a pool name MEMP_pool_name. description is used in stats.c
+ *     This allocates enough space for the pbuf struct and a payload.
+ *     (Example: pbuf_payload_size=0 allocates only size for the struct)
+ */
+LWIP_PBUF_MEMPOOL(PBUF,      MEMP_NUM_PBUF,            0,                             "PBUF_REF/ROM")
+LWIP_PBUF_MEMPOOL(PBUF_POOL, PBUF_POOL_SIZE,           PBUF_POOL_BUFSIZE,             "PBUF_POOL")
+
+
+/*
+ * Allow for user-defined pools; this must be explicitly set in lwipopts.h
+ * since the default is to NOT look for lwippools.h
+ */
+#if MEMP_USE_CUSTOM_POOLS
+#include "lwippools.h"
+#endif /* MEMP_USE_CUSTOM_POOLS */
+
+/*
+ * REQUIRED CLEANUP: Clear up so we don't get "multiply defined" error later
+ * (#undef is ignored for something that is not defined)
+ */
+#undef LWIP_MEMPOOL
+#undef LWIP_MALLOC_MEMPOOL
+#undef LWIP_MALLOC_MEMPOOL_START
+#undef LWIP_MALLOC_MEMPOOL_END
+#undef LWIP_PBUF_MEMPOOL
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/netbuf.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/netbuf.h
new file mode 100644
index 0000000..131f8a3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/netbuf.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_NETBUF_H__
+#define __LWIP_NETBUF_H__
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct netbuf {
+  struct pbuf *p, *ptr;
+  struct ip_addr *addr;
+  u16_t port;
+};
+
+/* Network buffer functions: */
+struct netbuf *   netbuf_new      (void);
+void              netbuf_delete   (struct netbuf *buf);
+void *            netbuf_alloc    (struct netbuf *buf, u16_t size);
+void              netbuf_free     (struct netbuf *buf);
+err_t             netbuf_ref      (struct netbuf *buf,
+           const void *dataptr, u16_t size);
+void              netbuf_chain    (struct netbuf *head,
+           struct netbuf *tail);
+
+u16_t             netbuf_len      (struct netbuf *buf);
+err_t             netbuf_data     (struct netbuf *buf,
+           void **dataptr, u16_t *len);
+s8_t              netbuf_next     (struct netbuf *buf);
+void              netbuf_first    (struct netbuf *buf);
+
+
+#define netbuf_copy_partial(buf, dataptr, len, offset) \
+  pbuf_copy_partial((buf)->p, (dataptr), (len), (offset))
+#define netbuf_copy(buf,dataptr,len) netbuf_copy_partial(buf, dataptr, len, 0)
+#define netbuf_len(buf)              ((buf)->p->tot_len)
+#define netbuf_fromaddr(buf)         ((buf)->addr)
+#define netbuf_fromport(buf)         ((buf)->port)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_NETBUF_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/netdb.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/netdb.h
new file mode 100644
index 0000000..f344b31
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/netdb.h
@@ -0,0 +1,109 @@
+/*
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Simon Goldschmidt
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_DNS && LWIP_SOCKET
+
+#include "lwip/sockets.h"
+
+/* some rarely used options */
+#ifndef LWIP_DNS_API_DECLARE_H_ERRNO
+#define LWIP_DNS_API_DECLARE_H_ERRNO 1
+#endif
+
+#ifndef LWIP_DNS_API_DEFINE_ERRORS
+#define LWIP_DNS_API_DEFINE_ERRORS 1
+#endif
+
+#ifndef LWIP_DNS_API_DECLARE_STRUCTS
+#define LWIP_DNS_API_DECLARE_STRUCTS 1
+#endif
+
+#if LWIP_DNS_API_DEFINE_ERRORS
+/** Errors used by the DNS API functions, h_errno can be one of them */
+#define EAI_NONAME      200
+#define EAI_SERVICE     201
+#define EAI_FAIL        202
+#define EAI_MEMORY      203
+
+#define HOST_NOT_FOUND  210
+#define NO_DATA         211
+#define NO_RECOVERY     212
+#define TRY_AGAIN       213
+#endif /* LWIP_DNS_API_DEFINE_ERRORS */
+
+#if LWIP_DNS_API_DECLARE_STRUCTS
+struct hostent {
+    char  *h_name;      /* Official name of the host. */
+    char **h_aliases;   /* A pointer to an array of pointers to alternative host names,
+                           terminated by a null pointer. */
+    int    h_addrtype;  /* Address type. */
+    int    h_length;    /* The length, in bytes, of the address. */
+    char **h_addr_list; /* A pointer to an array of pointers to network addresses (in
+                           network byte order) for the host, terminated by a null pointer. */
+#define h_addr h_addr_list[0] /* for backward compatibility */
+};
+
+struct addrinfo {
+    int               ai_flags;      /* Input flags. */
+    int               ai_family;     /* Address family of socket. */
+    int               ai_socktype;   /* Socket type. */
+    int               ai_protocol;   /* Protocol of socket. */
+    socklen_t         ai_addrlen;    /* Length of socket address. */
+    struct sockaddr  *ai_addr;       /* Socket address of socket. */
+    char             *ai_canonname;  /* Canonical name of service location. */
+    struct addrinfo  *ai_next;       /* Pointer to next in list. */
+};
+#endif /* LWIP_DNS_API_DECLARE_STRUCTS */
+
+#if LWIP_DNS_API_DECLARE_H_ERRNO
+/* application accessable error code set by the DNS API functions */
+extern int h_errno;
+#endif /* LWIP_DNS_API_DECLARE_H_ERRNO*/
+
+struct hostent *lwip_gethostbyname(const char *name);
+int lwip_gethostbyname_r(const char *name, struct hostent *ret, char *buf,
+                size_t buflen, struct hostent **result, int *h_errnop);
+void lwip_freeaddrinfo(struct addrinfo *ai);
+int lwip_getaddrinfo(const char *nodename,
+       const char *servname,
+       const struct addrinfo *hints,
+       struct addrinfo **res);
+
+#if LWIP_COMPAT_SOCKETS
+#define gethostbyname(name) lwip_gethostbyname(name)
+#define gethostbyname_r(name, ret, buf, buflen, result, h_errnop) \
+       lwip_gethostbyname_r(name, ret, buf, buflen, result, h_errnop)
+#define freeaddrinfo(addrinfo) lwip_freeaddrinfo(a)
+#define getaddrinfo(nodname, servname, hints, res) \
+       lwip_getaddrinfo(nodname, servname, hints, res)
+#endif /* LWIP_COMPAT_SOCKETS */
+
+#endif /* LWIP_DNS && LWIP_SOCKET */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/netif.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/netif.h
new file mode 100644
index 0000000..d8a59ae
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/netif.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_NETIF_H__
+#define __LWIP_NETIF_H__
+
+#include "lwip/opt.h"
+
+#include "lwip/err.h"
+
+#include "lwip/ip_addr.h"
+
+#include "lwip/inet.h"
+#include "lwip/pbuf.h"
+#if LWIP_DHCP
+struct dhcp;
+#endif
+#if LWIP_AUTOIP
+struct autoip;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Throughout this file, IP addresses are expected to be in
+ * the same byte order as in IP_PCB. */
+
+/** must be the maximum of all used hardware address lengths
+    across all types of interfaces in use */
+#define NETIF_MAX_HWADDR_LEN 6U
+
+/** TODO: define the use (where, when, whom) of netif flags */
+
+/** whether the network interface is 'up'. this is
+ * a software flag used to control whether this network
+ * interface is enabled and processes traffic.
+ */
+#define NETIF_FLAG_UP           0x01U
+/** if set, the netif has broadcast capability */
+#define NETIF_FLAG_BROADCAST    0x02U
+/** if set, the netif is one end of a point-to-point connection */
+#define NETIF_FLAG_POINTTOPOINT 0x04U
+/** if set, the interface is configured using DHCP */
+#define NETIF_FLAG_DHCP         0x08U
+/** if set, the interface has an active link
+ *  (set by the network interface driver) */
+#define NETIF_FLAG_LINK_UP      0x10U
+/** if set, the netif is an device using ARP */
+#define NETIF_FLAG_ETHARP       0x20U
+/** if set, the netif has IGMP capability */
+#define NETIF_FLAG_IGMP         0x40U
+
+/** Generic data structure used for all lwIP network interfaces.
+ *  The following fields should be filled in by the initialization
+ *  function for the device driver: hwaddr_len, hwaddr[], mtu, flags */
+
+struct netif {
+  /** pointer to next in linked list */
+  struct netif *next;
+
+  /** IP address configuration in network byte order */
+  struct ip_addr ip_addr;
+  struct ip_addr netmask;
+  struct ip_addr gw;
+
+  /** This function is called by the network device driver
+   *  to pass a packet up the TCP/IP stack. */
+  err_t (* input)(struct pbuf *p, struct netif *inp);
+  /** This function is called by the IP module when it wants
+   *  to send a packet on the interface. This function typically
+   *  first resolves the hardware address, then sends the packet. */
+  err_t (* output)(struct netif *netif, struct pbuf *p,
+       struct ip_addr *ipaddr);
+  /** This function is called by the ARP module when it wants
+   *  to send a packet on the interface. This function outputs
+   *  the pbuf as-is on the link medium. */
+  err_t (* linkoutput)(struct netif *netif, struct pbuf *p);
+#if LWIP_NETIF_STATUS_CALLBACK
+  /** This function is called when the netif state is set to up or down
+   */
+  void (* status_callback)(struct netif *netif);
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+#if LWIP_NETIF_LINK_CALLBACK
+  /** This function is called when the netif link is set to up or down
+   */
+  void (* link_callback)(struct netif *netif);
+#endif /* LWIP_NETIF_LINK_CALLBACK */
+  /** This field can be set by the device driver and could point
+   *  to state information for the device. */
+  void *state;
+#if LWIP_DHCP
+  /** the DHCP client state information for this netif */
+  struct dhcp *dhcp;
+#endif /* LWIP_DHCP */
+#if LWIP_AUTOIP
+  /** the AutoIP client state information for this netif */
+  struct autoip *autoip;
+#endif
+#if LWIP_NETIF_HOSTNAME
+  /* the hostname for this netif, NULL is a valid value */
+  char*  hostname;
+#endif /* LWIP_NETIF_HOSTNAME */
+  /** number of bytes used in hwaddr */
+  u8_t hwaddr_len;
+  /** link level hardware address of this interface */
+  u8_t hwaddr[NETIF_MAX_HWADDR_LEN];
+  /** maximum transfer unit (in bytes) */
+  u16_t mtu;
+  /** flags (see NETIF_FLAG_ above) */
+  u8_t flags;
+  /** descriptive abbreviation */
+  char name[2];
+  /** number of this interface */
+  u8_t num;
+#if LWIP_SNMP
+  /** link type (from "snmp_ifType" enum from snmp.h) */
+  u8_t link_type;
+  /** (estimate) link speed */
+  u32_t link_speed;
+  /** timestamp at last change made (up/down) */
+  u32_t ts;
+  /** counters */
+  u32_t ifinoctets;
+  u32_t ifinucastpkts;
+  u32_t ifinnucastpkts;
+  u32_t ifindiscards;
+  u32_t ifoutoctets;
+  u32_t ifoutucastpkts;
+  u32_t ifoutnucastpkts;
+  u32_t ifoutdiscards;
+#endif /* LWIP_SNMP */
+#if LWIP_IGMP
+  /* This function could be called to add or delete a entry in the multicast filter table of the ethernet MAC.*/
+  err_t (*igmp_mac_filter)( struct netif *netif, struct ip_addr *group, u8_t action);
+#endif /* LWIP_IGMP */
+#if LWIP_NETIF_HWADDRHINT
+  u8_t *addr_hint;
+#endif /* LWIP_NETIF_HWADDRHINT */
+};
+
+#if LWIP_SNMP
+#define NETIF_INIT_SNMP(netif, type, speed) \
+  /* use "snmp_ifType" enum from snmp.h for "type", snmp_ifType_ethernet_csmacd by example */ \
+  netif->link_type = type;    \
+  /* your link speed here (units: bits per second) */  \
+  netif->link_speed = speed;  \
+  netif->ts = 0;              \
+  netif->ifinoctets = 0;      \
+  netif->ifinucastpkts = 0;   \
+  netif->ifinnucastpkts = 0;  \
+  netif->ifindiscards = 0;    \
+  netif->ifoutoctets = 0;     \
+  netif->ifoutucastpkts = 0;  \
+  netif->ifoutnucastpkts = 0; \
+  netif->ifoutdiscards = 0
+#else /* LWIP_SNMP */
+#define NETIF_INIT_SNMP(netif, type, speed)
+#endif /* LWIP_SNMP */
+
+
+/** The list of network interfaces. */
+extern struct netif *netif_list;
+/** The default network interface. */
+extern struct netif *netif_default;
+
+#define netif_init() /* Compatibility define, not init needed. */
+
+struct netif *netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
+      struct ip_addr *gw,
+      void *state,
+      err_t (* init)(struct netif *netif),
+      err_t (* input)(struct pbuf *p, struct netif *netif));
+
+void
+netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask,
+    struct ip_addr *gw);
+void netif_remove(struct netif * netif);
+
+/* Returns a network interface given its name. The name is of the form
+   "et0", where the first two letters are the "name" field in the
+   netif structure, and the digit is in the num field in the same
+   structure. */
+struct netif *netif_find(char *name);
+
+void netif_set_default(struct netif *netif);
+
+void netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr);
+void netif_set_netmask(struct netif *netif, struct ip_addr *netmask);
+void netif_set_gw(struct netif *netif, struct ip_addr *gw);
+
+void netif_set_up(struct netif *netif);
+void netif_set_down(struct netif *netif);
+u8_t netif_is_up(struct netif *netif);
+
+#if LWIP_NETIF_STATUS_CALLBACK
+/*
+ * Set callback to be called when interface is brought up/down
+ */
+void netif_set_status_callback(struct netif *netif, void (* status_callback)(struct netif *netif));
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+
+#if LWIP_NETIF_LINK_CALLBACK
+void netif_set_link_up(struct netif *netif);
+void netif_set_link_down(struct netif *netif);
+u8_t netif_is_link_up(struct netif *netif);
+/*
+ * Set callback to be called when link is brought up/down
+ */
+void netif_set_link_callback(struct netif *netif, void (* link_callback)(struct netif *netif));
+#endif /* LWIP_NETIF_LINK_CALLBACK */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_NETIF_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/netifapi.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/netifapi.h
new file mode 100644
index 0000000..88f8d31
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/netifapi.h
@@ -0,0 +1,100 @@
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef __LWIP_NETIFAPI_H__
+#define __LWIP_NETIFAPI_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/sys.h"
+#include "lwip/netif.h"
+#include "lwip/dhcp.h"
+#include "lwip/autoip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct netifapi_msg_msg {
+#if !LWIP_TCPIP_CORE_LOCKING
+  sys_sem_t sem;
+#endif /* !LWIP_TCPIP_CORE_LOCKING */
+  err_t err;
+  struct netif *netif;
+  union {
+    struct {
+      struct ip_addr *ipaddr;
+      struct ip_addr *netmask;
+      struct ip_addr *gw;
+      void *state;
+      err_t (* init) (struct netif *netif);
+      err_t (* input)(struct pbuf *p, struct netif *netif);
+    } add;
+    struct {
+      void  (* voidfunc)(struct netif *netif);
+      err_t (* errtfunc)(struct netif *netif);
+    } common;
+  } msg;
+};
+
+struct netifapi_msg {
+  void (* function)(struct netifapi_msg_msg *msg);
+  struct netifapi_msg_msg msg;
+};
+
+
+/* API for application */
+err_t netifapi_netif_add       ( struct netif *netif,
+                                 struct ip_addr *ipaddr,
+                                 struct ip_addr *netmask,
+                                 struct ip_addr *gw,
+                                 void *state,
+                                 err_t (* init)(struct netif *netif),
+                                 err_t (* input)(struct pbuf *p, struct netif *netif) );
+
+err_t netifapi_netif_common    ( struct netif *netif,
+                                 void  (* voidfunc)(struct netif *netif),
+                                 err_t (* errtfunc)(struct netif *netif) );
+
+#define netifapi_netif_remove(n)      netifapi_netif_common(n, netif_remove, NULL)
+#define netifapi_netif_set_up(n)      netifapi_netif_common(n, netif_set_up, NULL)
+#define netifapi_netif_set_down(n)    netifapi_netif_common(n, netif_set_down, NULL)
+#define netifapi_netif_set_default(n) netifapi_netif_common(n, netif_set_default, NULL)
+#define netifapi_dhcp_start(n)        netifapi_netif_common(n, NULL, dhcp_start)
+#define netifapi_dhcp_stop(n)         netifapi_netif_common(n, dhcp_stop, NULL)
+#define netifapi_autoip_start(n)      netifapi_netif_common(n, NULL, autoip_start)
+#define netifapi_autoip_stop(n)       netifapi_netif_common(n, NULL, autoip_stop)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_NETIF_API */
+
+#endif /* __LWIP_NETIFAPI_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/opt.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/opt.h
new file mode 100644
index 0000000..98058b4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/opt.h
@@ -0,0 +1,1654 @@
+/**
+ * @file
+ *
+ * lwIP Options Configuration
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_OPT_H__
+#define __LWIP_OPT_H__
+
+/*
+ * Include user defined options first. Anything not defined in these files
+ * will be set to standard values. Override anything you dont like!
+ */
+#include "lwipopts.h"
+#include "lwip/debug.h"
+
+/*
+   -----------------------------------------------
+   ---------- Platform specific locking ----------
+   -----------------------------------------------
+*/
+
+/**
+ * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
+ * critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#ifndef SYS_LIGHTWEIGHT_PROT
+#define SYS_LIGHTWEIGHT_PROT            0
+#endif
+
+/**
+ * NO_SYS==1: Provides VERY minimal functionality. Otherwise,
+ * use lwIP facilities.
+ */
+#ifndef NO_SYS
+#define NO_SYS                          0
+#endif
+
+/**
+ * MEMCPY: override this if you have a faster implementation at hand than the
+ * one included in your C library
+ */
+#ifndef MEMCPY
+#define MEMCPY(dst,src,len)             memcpy(dst,src,len)
+#endif
+
+/**
+ * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a
+ * call to memcpy() if the length is known at compile time and is small.
+ */
+#ifndef SMEMCPY
+#define SMEMCPY(dst,src,len)            memcpy(dst,src,len)
+#endif
+
+/*
+   ------------------------------------
+   ---------- Memory options ----------
+   ------------------------------------
+*/
+/**
+ * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library
+ * instead of the lwip internal allocator. Can save code size if you
+ * already use it.
+ */
+#ifndef MEM_LIBC_MALLOC
+#define MEM_LIBC_MALLOC                 0
+#endif
+
+/**
+ * MEM_ALIGNMENT: should be set to the alignment of the CPU
+ *    4 byte alignment -> #define MEM_ALIGNMENT 4
+ *    2 byte alignment -> #define MEM_ALIGNMENT 2
+ */
+#ifndef MEM_ALIGNMENT
+#define MEM_ALIGNMENT                   1
+#endif
+
+/**
+ * MEM_SIZE: the size of the heap memory. If the application will send
+ * a lot of data that needs to be copied, this should be set high.
+ */
+#ifndef MEM_SIZE
+#define MEM_SIZE                        1600
+#endif
+
+/**
+ * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable
+ * amount of bytes before and after each memp element in every pool and fills
+ * it with a prominent default value.
+ *    MEMP_OVERFLOW_CHECK == 0 no checking
+ *    MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed
+ *    MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time
+ *      memp_malloc() or memp_free() is called (useful but slow!)
+ */
+#ifndef MEMP_OVERFLOW_CHECK
+#define MEMP_OVERFLOW_CHECK             0
+#endif
+
+/**
+ * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make
+ * sure that there are no cycles in the linked lists.
+ */
+#ifndef MEMP_SANITY_CHECK
+#define MEMP_SANITY_CHECK               0
+#endif
+
+/**
+ * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set
+ * of memory pools of various sizes. When mem_malloc is called, an element of
+ * the smallest pool that can provide the lenght needed is returned.
+ */
+#ifndef MEM_USE_POOLS
+#define MEM_USE_POOLS                   0
+#endif
+
+/**
+ * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h
+ * that defines additional pools beyond the "standard" ones required
+ * by lwIP. If you set this to 1, you must have lwippools.h in your
+ * inlude path somewhere.
+ */
+#ifndef MEMP_USE_CUSTOM_POOLS
+#define MEMP_USE_CUSTOM_POOLS           0
+#endif
+
+
+/*
+   ------------------------------------------------
+   ---------- Internal Memory Pool Sizes ----------
+   ------------------------------------------------
+*/
+/**
+ * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF).
+ * If the application sends a lot of data out of ROM (or other static memory),
+ * this should be set high.
+ */
+#ifndef MEMP_NUM_PBUF
+#define MEMP_NUM_PBUF                   16
+#endif
+
+/**
+ * MEMP_NUM_RAW_PCB: Number of raw connection PCBs
+ * (requires the LWIP_RAW option)
+ */
+#ifndef MEMP_NUM_RAW_PCB
+#define MEMP_NUM_RAW_PCB                4
+#endif
+
+/**
+ * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+ * per active UDP "connection".
+ * (requires the LWIP_UDP option)
+ */
+#ifndef MEMP_NUM_UDP_PCB
+#define MEMP_NUM_UDP_PCB                4
+#endif
+
+/**
+ * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections.
+ * (requires the LWIP_TCP option)
+ */
+#ifndef MEMP_NUM_TCP_PCB
+#define MEMP_NUM_TCP_PCB                5
+#endif
+
+/**
+ * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections.
+ * (requires the LWIP_TCP option)
+ */
+#ifndef MEMP_NUM_TCP_PCB_LISTEN
+#define MEMP_NUM_TCP_PCB_LISTEN         8
+#endif
+
+/**
+ * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments.
+ * (requires the LWIP_TCP option)
+ */
+#ifndef MEMP_NUM_TCP_SEG
+#define MEMP_NUM_TCP_SEG                16
+#endif
+
+/**
+ * MEMP_NUM_REASSDATA: the number of simultaneously IP packets queued for
+ * reassembly (whole packets, not fragments!)
+ */
+#ifndef MEMP_NUM_REASSDATA
+#define MEMP_NUM_REASSDATA              5
+#endif
+
+/**
+ * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing
+ * packets (pbufs) that are waiting for an ARP request (to resolve
+ * their destination address) to finish.
+ * (requires the ARP_QUEUEING option)
+ */
+#ifndef MEMP_NUM_ARP_QUEUE
+#define MEMP_NUM_ARP_QUEUE              30
+#endif
+
+/**
+ * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces
+ * can be members et the same time (one per netif - allsystems group -, plus one
+ * per netif membership).
+ * (requires the LWIP_IGMP option)
+ */
+#ifndef MEMP_NUM_IGMP_GROUP
+#define MEMP_NUM_IGMP_GROUP             8
+#endif
+
+/**
+ * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts.
+ * (requires NO_SYS==0)
+ */
+#ifndef MEMP_NUM_SYS_TIMEOUT
+#define MEMP_NUM_SYS_TIMEOUT            3
+#endif
+
+/**
+ * MEMP_NUM_NETBUF: the number of struct netbufs.
+ * (only needed if you use the sequential API, like api_lib.c)
+ */
+#ifndef MEMP_NUM_NETBUF
+#define MEMP_NUM_NETBUF                 2
+#endif
+
+/**
+ * MEMP_NUM_NETCONN: the number of struct netconns.
+ * (only needed if you use the sequential API, like api_lib.c)
+ */
+#ifndef MEMP_NUM_NETCONN
+#define MEMP_NUM_NETCONN                4
+#endif
+
+/**
+ * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used
+ * for callback/timeout API communication.
+ * (only needed if you use tcpip.c)
+ */
+#ifndef MEMP_NUM_TCPIP_MSG_API
+#define MEMP_NUM_TCPIP_MSG_API          8
+#endif
+
+/**
+ * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used
+ * for incoming packets.
+ * (only needed if you use tcpip.c)
+ */
+#ifndef MEMP_NUM_TCPIP_MSG_INPKT
+#define MEMP_NUM_TCPIP_MSG_INPKT        8
+#endif
+
+/**
+ * PBUF_POOL_SIZE: the number of buffers in the pbuf pool.
+ */
+#ifndef PBUF_POOL_SIZE
+#define PBUF_POOL_SIZE                  16
+#endif
+
+/*
+   ---------------------------------
+   ---------- ARP options ----------
+   ---------------------------------
+*/
+/**
+ * LWIP_ARP==1: Enable ARP functionality.
+ */
+#ifndef LWIP_ARP
+#define LWIP_ARP                        1
+#endif
+
+/**
+ * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached.
+ */
+#ifndef ARP_TABLE_SIZE
+#define ARP_TABLE_SIZE                  10
+#endif
+
+/**
+ * ARP_QUEUEING==1: Outgoing packets are queued during hardware address
+ * resolution.
+ */
+#ifndef ARP_QUEUEING
+#define ARP_QUEUEING                    1
+#endif
+
+/**
+ * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be
+ * updated with the source MAC and IP addresses supplied in the packet.
+ * You may want to disable this if you do not trust LAN peers to have the
+ * correct addresses, or as a limited approach to attempt to handle
+ * spoofing. If disabled, lwIP will need to make a new ARP request if
+ * the peer is not already in the ARP table, adding a little latency.
+ */
+#ifndef ETHARP_TRUST_IP_MAC
+#define ETHARP_TRUST_IP_MAC             1
+#endif
+
+/*
+   --------------------------------
+   ---------- IP options ----------
+   --------------------------------
+*/
+/**
+ * IP_FORWARD==1: Enables the ability to forward IP packets across network
+ * interfaces. If you are going to run lwIP on a device with only one network
+ * interface, define this to 0.
+ */
+#ifndef IP_FORWARD
+#define IP_FORWARD                      0
+#endif
+
+/**
+ * IP_OPTIONS_ALLOWED: Defines the behavior for IP options.
+ *      IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped.
+ *      IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed).
+ */
+#ifndef IP_OPTIONS_ALLOWED
+#define IP_OPTIONS_ALLOWED              1
+#endif
+
+/**
+ * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that
+ * this option does not affect outgoing packet sizes, which can be controlled
+ * via IP_FRAG.
+ */
+#ifndef IP_REASSEMBLY
+#define IP_REASSEMBLY                   1
+#endif
+
+/**
+ * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note
+ * that this option does not affect incoming packet sizes, which can be
+ * controlled via IP_REASSEMBLY.
+ */
+#ifndef IP_FRAG
+#define IP_FRAG                         1
+#endif
+
+/**
+ * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally)
+ * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived
+ * in this time, the whole packet is discarded.
+ */
+#ifndef IP_REASS_MAXAGE
+#define IP_REASS_MAXAGE                 3
+#endif
+
+/**
+ * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled.
+ * Since the received pbufs are enqueued, be sure to configure
+ * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive
+ * packets even if the maximum amount of fragments is enqueued for reassembly!
+ */
+#ifndef IP_REASS_MAX_PBUFS
+#define IP_REASS_MAX_PBUFS              10
+#endif
+
+/**
+ * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP
+ * fragmentation. Otherwise pbufs are allocated and reference the original
+ * packet data to be fragmented.
+ */
+#ifndef IP_FRAG_USES_STATIC_BUF
+#define IP_FRAG_USES_STATIC_BUF         1
+#endif
+
+/**
+ * IP_FRAG_MAX_MTU: Assumed max MTU on any interface for IP frag buffer
+ * (requires IP_FRAG_USES_STATIC_BUF==1)
+ */
+#if IP_FRAG_USES_STATIC_BUF && !defined(IP_FRAG_MAX_MTU)
+#define IP_FRAG_MAX_MTU                 1500
+#endif
+
+/**
+ * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers.
+ */
+#ifndef IP_DEFAULT_TTL
+#define IP_DEFAULT_TTL                  255
+#endif
+
+/*
+   ----------------------------------
+   ---------- ICMP options ----------
+   ----------------------------------
+*/
+/**
+ * LWIP_ICMP==1: Enable ICMP module inside the IP stack.
+ * Be careful, disable that make your product non-compliant to RFC1122
+ */
+#ifndef LWIP_ICMP
+#define LWIP_ICMP                       1
+#endif
+
+/**
+ * ICMP_TTL: Default value for Time-To-Live used by ICMP packets.
+ */
+#ifndef ICMP_TTL
+#define ICMP_TTL                       (IP_DEFAULT_TTL)
+#endif
+
+/*
+   ---------------------------------
+   ---------- RAW options ----------
+   ---------------------------------
+*/
+/**
+ * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
+ */
+#ifndef LWIP_RAW
+#define LWIP_RAW                        1
+#endif
+
+/**
+ * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
+ */
+#ifndef RAW_TTL
+#define RAW_TTL                        (IP_DEFAULT_TTL)
+#endif
+
+/*
+   ----------------------------------
+   ---------- DHCP options ----------
+   ----------------------------------
+*/
+/**
+ * LWIP_DHCP==1: Enable DHCP module.
+ */
+#ifndef LWIP_DHCP
+#define LWIP_DHCP                       0
+#endif
+
+/**
+ * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address.
+ */
+#ifndef DHCP_DOES_ARP_CHECK
+#define DHCP_DOES_ARP_CHECK             ((LWIP_DHCP) && (LWIP_ARP))
+#endif
+
+/*
+   ------------------------------------
+   ---------- AUTOIP options ----------
+   ------------------------------------
+*/
+/**
+ * LWIP_AUTOIP==1: Enable AUTOIP module.
+ */
+#ifndef LWIP_AUTOIP
+#define LWIP_AUTOIP                     0
+#endif
+
+/**
+ * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on
+ * the same interface at the same time.
+ */
+#ifndef LWIP_DHCP_AUTOIP_COOP
+#define LWIP_DHCP_AUTOIP_COOP           0
+#endif
+
+/*
+   ----------------------------------
+   ---------- SNMP options ----------
+   ----------------------------------
+*/
+/**
+ * LWIP_SNMP==1: Turn on SNMP module. UDP must be available for SNMP
+ * transport.
+ */
+#ifndef LWIP_SNMP
+#define LWIP_SNMP                       0
+#endif
+
+/**
+ * SNMP_CONCURRENT_REQUESTS: Number of concurrent requests the module will
+ * allow. At least one request buffer is required.
+ */
+#ifndef SNMP_CONCURRENT_REQUESTS
+#define SNMP_CONCURRENT_REQUESTS        1
+#endif
+
+/**
+ * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap
+ * destination is required
+ */
+#ifndef SNMP_TRAP_DESTINATIONS
+#define SNMP_TRAP_DESTINATIONS          1
+#endif
+
+/**
+ * SNMP_PRIVATE_MIB:
+ */
+#ifndef SNMP_PRIVATE_MIB
+#define SNMP_PRIVATE_MIB                0
+#endif
+
+/**
+ * Only allow SNMP write actions that are 'safe' (e.g. disabeling netifs is not
+ * a safe action and disabled when SNMP_SAFE_REQUESTS = 1).
+ * Unsafe requests are disabled by default!
+ */
+#ifndef SNMP_SAFE_REQUESTS
+#define SNMP_SAFE_REQUESTS              1
+#endif
+
+/*
+   ----------------------------------
+   ---------- IGMP options ----------
+   ----------------------------------
+*/
+/**
+ * LWIP_IGMP==1: Turn on IGMP module.
+ */
+#ifndef LWIP_IGMP
+#define LWIP_IGMP                       0
+#endif
+
+/*
+   ----------------------------------
+   ---------- DNS options -----------
+   ----------------------------------
+*/
+/**
+ * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS
+ * transport.
+ */
+#ifndef LWIP_DNS
+#define LWIP_DNS                        0
+#endif
+
+/** DNS maximum number of entries to maintain locally. */
+#ifndef DNS_TABLE_SIZE
+#define DNS_TABLE_SIZE                  4
+#endif
+
+/** DNS maximum host name length supported in the name table. */
+#ifndef DNS_MAX_NAME_LENGTH
+#define DNS_MAX_NAME_LENGTH             256
+#endif
+
+/** The maximum of DNS servers */
+#ifndef DNS_MAX_SERVERS
+#define DNS_MAX_SERVERS                 2
+#endif
+
+/** DNS do a name checking between the query and the response. */
+#ifndef DNS_DOES_NAME_CHECK
+#define DNS_DOES_NAME_CHECK             1
+#endif
+
+/** DNS use a local buffer if DNS_USES_STATIC_BUF=0, a static one if
+    DNS_USES_STATIC_BUF=1, or a dynamic one if DNS_USES_STATIC_BUF=2.
+    The buffer will be of size DNS_MSG_SIZE */
+#ifndef DNS_USES_STATIC_BUF
+#define DNS_USES_STATIC_BUF             1
+#endif
+
+/** DNS message max. size. Default value is RFC compliant. */
+#ifndef DNS_MSG_SIZE
+#define DNS_MSG_SIZE                    512
+#endif
+
+/*
+   ---------------------------------
+   ---------- UDP options ----------
+   ---------------------------------
+*/
+/**
+ * LWIP_UDP==1: Turn on UDP.
+ */
+#ifndef LWIP_UDP
+#define LWIP_UDP                        1
+#endif
+
+/**
+ * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP)
+ */
+#ifndef LWIP_UDPLITE
+#define LWIP_UDPLITE                    0
+#endif
+
+/**
+ * UDP_TTL: Default Time-To-Live value.
+ */
+#ifndef UDP_TTL
+#define UDP_TTL                         (IP_DEFAULT_TTL)
+#endif
+
+/*
+   ---------------------------------
+   ---------- TCP options ----------
+   ---------------------------------
+*/
+/**
+ * LWIP_TCP==1: Turn on TCP.
+ */
+#ifndef LWIP_TCP
+#define LWIP_TCP                        1
+#endif
+
+/**
+ * TCP_TTL: Default Time-To-Live value.
+ */
+#ifndef TCP_TTL
+#define TCP_TTL                         (IP_DEFAULT_TTL)
+#endif
+
+/**
+ * TCP_WND: The size of a TCP window.
+ */
+#ifndef TCP_WND
+#define TCP_WND                         2048
+#endif
+
+/**
+ * TCP_MAXRTX: Maximum number of retransmissions of data segments.
+ */
+#ifndef TCP_MAXRTX
+#define TCP_MAXRTX                      12
+#endif
+
+/**
+ * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments.
+ */
+#ifndef TCP_SYNMAXRTX
+#define TCP_SYNMAXRTX                   6
+#endif
+
+/**
+ * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order.
+ * Define to 0 if your device is low on memory.
+ */
+#ifndef TCP_QUEUE_OOSEQ
+#define TCP_QUEUE_OOSEQ                 1
+#endif
+
+/**
+ * TCP_MSS: TCP Maximum segment size. (default is 128, a *very*
+ * conservative default.)
+ * For the receive side, this MSS is advertised to the remote side
+ * when opening a connection. For the transmit size, this MSS sets
+ * an upper limit on the MSS advertised by the remote host.
+ */
+#ifndef TCP_MSS
+#define TCP_MSS                         128
+#endif
+
+/**
+ * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really
+ * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which
+ * reflects the available reassembly buffer size at the remote host) and the
+ * largest size permitted by the IP layer" (RFC 1122)
+ * Setting this to 1 enables code that checks TCP_MSS against the MTU of the
+ * netif used for a connection and limits the MSS if it would be too big otherwise.
+ */
+#ifndef TCP_CALCULATE_EFF_SEND_MSS
+#define TCP_CALCULATE_EFF_SEND_MSS      1
+#endif
+
+
+/**
+ * TCP_SND_BUF: TCP sender buffer space (bytes).
+ */
+#ifndef TCP_SND_BUF
+#define TCP_SND_BUF                     256
+#endif
+
+/**
+ * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least
+ * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work.
+ */
+#ifndef TCP_SND_QUEUELEN
+#define TCP_SND_QUEUELEN                (4 * (TCP_SND_BUF/TCP_MSS))
+#endif
+
+/**
+ * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than or equal
+ * to TCP_SND_BUF. It is the amount of space which must be available in the
+ * TCP snd_buf for select to return writable.
+ */
+#ifndef TCP_SNDLOWAT
+#define TCP_SNDLOWAT                    (TCP_SND_BUF/2)
+#endif
+
+/**
+ * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb.
+ */
+#ifndef TCP_LISTEN_BACKLOG
+#define TCP_LISTEN_BACKLOG              0
+#endif
+
+/**
+ * The maximum allowed backlog for TCP listen netconns.
+ * This backlog is used unless another is explicitly specified.
+ * 0xff is the maximum (u8_t).
+ */
+#ifndef TCP_DEFAULT_LISTEN_BACKLOG
+#define TCP_DEFAULT_LISTEN_BACKLOG      0xff
+#endif
+
+/**
+ * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1.
+ *     LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all
+ *         events (accept, sent, etc) that happen in the system.
+ *     LWIP_CALLBACK_API==1: The PCB callback function is called directly
+ *         for the event.
+ */
+#ifndef LWIP_EVENT_API
+#define LWIP_EVENT_API                  0
+#define LWIP_CALLBACK_API               1
+#else
+#define LWIP_EVENT_API                  1
+#define LWIP_CALLBACK_API               0
+#endif
+
+
+/*
+   ----------------------------------
+   ---------- Pbuf options ----------
+   ----------------------------------
+*/
+/**
+ * PBUF_LINK_HLEN: the number of bytes that should be allocated for a
+ * link level header. The default is 14, the standard value for
+ * Ethernet.
+ */
+#ifndef PBUF_LINK_HLEN
+#define PBUF_LINK_HLEN                  14
+#endif
+
+/**
+ * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is
+ * designed to accomodate single full size TCP frame in one pbuf, including
+ * TCP_MSS, IP header, and link header.
+ */
+#ifndef PBUF_POOL_BUFSIZE
+#define PBUF_POOL_BUFSIZE               LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN)
+#endif
+
+/*
+   ------------------------------------------------
+   ---------- Network Interfaces options ----------
+   ------------------------------------------------
+*/
+/**
+ * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname
+ * field.
+ */
+#ifndef LWIP_NETIF_HOSTNAME
+#define LWIP_NETIF_HOSTNAME             0
+#endif
+
+/**
+ * LWIP_NETIF_API==1: Support netif api (in netifapi.c)
+ */
+#ifndef LWIP_NETIF_API
+#define LWIP_NETIF_API                  0
+#endif
+
+/**
+ * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface
+ * changes its up/down status (i.e., due to DHCP IP acquistion)
+ */
+#ifndef LWIP_NETIF_STATUS_CALLBACK
+#define LWIP_NETIF_STATUS_CALLBACK      0
+#endif
+
+/**
+ * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface
+ * whenever the link changes (i.e., link down)
+ */
+#ifndef LWIP_NETIF_LINK_CALLBACK
+#define LWIP_NETIF_LINK_CALLBACK        0
+#endif
+
+/**
+ * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table
+ * indices) in struct netif. TCP and UDP can make use of this to prevent
+ * scanning the ARP table for every sent packet. While this is faster for big
+ * ARP tables or many concurrent connections, it might be counterproductive
+ * if you have a tiny ARP table or if there never are concurrent connections.
+ */
+#ifndef LWIP_NETIF_HWADDRHINT
+#define LWIP_NETIF_HWADDRHINT           0
+#endif
+
+/*
+   ------------------------------------
+   ---------- LOOPIF options ----------
+   ------------------------------------
+*/
+/**
+ * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c
+ */
+#ifndef LWIP_HAVE_LOOPIF
+#define LWIP_HAVE_LOOPIF                0
+#endif
+
+/**
+ * LWIP_LOOPIF_MULTITHREADING: Indicates whether threading is enabled in
+ * the system, as LOOPIF must change how it behaves depending on this setting.
+ * Setting this is needed to avoid reentering non-reentrant functions like
+ * tcp_input().
+ *    LWIP_LOOPIF_MULTITHREADING==1: Indicates that the user is using a
+ *       multithreaded environment like tcpip.c. In this case, netif->input()
+ *       is called directly.
+ *    LWIP_LOOPIF_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup.
+ *       The packets are put on a list and loopif_poll() must be called in
+ *       the main application loop.
+ */
+#ifndef LWIP_LOOPIF_MULTITHREADING
+#define LWIP_LOOPIF_MULTITHREADING      1
+#endif
+
+/*
+   ------------------------------------
+   ---------- Thread options ----------
+   ------------------------------------
+*/
+/**
+ * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread.
+ */
+#ifndef TCPIP_THREAD_NAME
+#define TCPIP_THREAD_NAME              "tcpip_thread"
+#endif
+
+/**
+ * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef TCPIP_THREAD_STACKSIZE
+#define TCPIP_THREAD_STACKSIZE          0
+#endif
+
+/**
+ * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef TCPIP_THREAD_PRIO
+#define TCPIP_THREAD_PRIO               1
+#endif
+
+/**
+ * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages
+ * The queue size value itself is platform-dependent, but is passed to
+ * sys_mbox_new() when tcpip_init is called.
+ */
+#ifndef TCPIP_MBOX_SIZE
+#define TCPIP_MBOX_SIZE                 0
+#endif
+
+/**
+ * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread.
+ */
+#ifndef SLIPIF_THREAD_NAME
+#define SLIPIF_THREAD_NAME             "slipif_loop"
+#endif
+
+/**
+ * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef SLIPIF_THREAD_STACKSIZE
+#define SLIPIF_THREAD_STACKSIZE         0
+#endif
+
+/**
+ * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef SLIPIF_THREAD_PRIO
+#define SLIPIF_THREAD_PRIO              1
+#endif
+
+/**
+ * PPP_THREAD_NAME: The name assigned to the pppMain thread.
+ */
+#ifndef PPP_THREAD_NAME
+#define PPP_THREAD_NAME                "pppMain"
+#endif
+
+/**
+ * PPP_THREAD_STACKSIZE: The stack size used by the pppMain thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef PPP_THREAD_STACKSIZE
+#define PPP_THREAD_STACKSIZE            0
+#endif
+
+/**
+ * PPP_THREAD_PRIO: The priority assigned to the pppMain thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef PPP_THREAD_PRIO
+#define PPP_THREAD_PRIO                 1
+#endif
+
+/**
+ * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread.
+ */
+#ifndef DEFAULT_THREAD_NAME
+#define DEFAULT_THREAD_NAME            "lwIP"
+#endif
+
+/**
+ * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef DEFAULT_THREAD_STACKSIZE
+#define DEFAULT_THREAD_STACKSIZE        0
+#endif
+
+/**
+ * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef DEFAULT_THREAD_PRIO
+#define DEFAULT_THREAD_PRIO             1
+#endif
+
+/**
+ * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#ifndef DEFAULT_RAW_RECVMBOX_SIZE
+#define DEFAULT_RAW_RECVMBOX_SIZE       0
+#endif
+
+/**
+ * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#ifndef DEFAULT_UDP_RECVMBOX_SIZE
+#define DEFAULT_UDP_RECVMBOX_SIZE       0
+#endif
+
+/**
+ * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#ifndef DEFAULT_TCP_RECVMBOX_SIZE
+#define DEFAULT_TCP_RECVMBOX_SIZE       0
+#endif
+
+/**
+ * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections.
+ * The queue size value itself is platform-dependent, but is passed to
+ * sys_mbox_new() when the acceptmbox is created.
+ */
+#ifndef DEFAULT_ACCEPTMBOX_SIZE
+#define DEFAULT_ACCEPTMBOX_SIZE         0
+#endif
+
+/*
+   ----------------------------------------------
+   ---------- Sequential layer options ----------
+   ----------------------------------------------
+*/
+/**
+ * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!)
+ * Don't use it if you're not an active lwIP project member
+ */
+#ifndef LWIP_TCPIP_CORE_LOCKING
+#define LWIP_TCPIP_CORE_LOCKING         0
+#endif
+
+/**
+ * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c)
+ */
+#ifndef LWIP_NETCONN
+#define LWIP_NETCONN                    1
+#endif
+
+/*
+   ------------------------------------
+   ---------- Socket options ----------
+   ------------------------------------
+*/
+/**
+ * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)
+ */
+#ifndef LWIP_SOCKET
+#define LWIP_SOCKET                     1
+#endif
+
+/**
+ * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names.
+ * (only used if you use sockets.c)
+ */
+#ifndef LWIP_COMPAT_SOCKETS
+#define LWIP_COMPAT_SOCKETS             1
+#endif
+
+/**
+ * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names.
+ * Disable this option if you use a POSIX operating system that uses the same
+ * names (read, write & close). (only used if you use sockets.c)
+ */
+#ifndef LWIP_POSIX_SOCKETS_IO_NAMES
+#define LWIP_POSIX_SOCKETS_IO_NAMES     1
+#endif
+
+/**
+ * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT
+ * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set
+ * in seconds. (does not require sockets.c, and will affect tcp.c)
+ */
+#ifndef LWIP_TCP_KEEPALIVE
+#define LWIP_TCP_KEEPALIVE              0
+#endif
+
+/**
+ * LWIP_SO_RCVTIMEO==1: Enable SO_RCVTIMEO processing.
+ */
+#ifndef LWIP_SO_RCVTIMEO
+#define LWIP_SO_RCVTIMEO                0
+#endif
+
+/**
+ * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing.
+ */
+#ifndef LWIP_SO_RCVBUF
+#define LWIP_SO_RCVBUF                  0
+#endif
+
+/**
+ * SO_REUSE==1: Enable SO_REUSEADDR and SO_REUSEPORT options. DO NOT USE!
+ */
+#ifndef SO_REUSE
+#define SO_REUSE                        0
+#endif
+
+/*
+   ----------------------------------------
+   ---------- Statistics options ----------
+   ----------------------------------------
+*/
+/**
+ * LWIP_STATS==1: Enable statistics collection in lwip_stats.
+ */
+#ifndef LWIP_STATS
+#define LWIP_STATS                      1
+#endif
+
+#if LWIP_STATS
+
+/**
+ * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions.
+ */
+#ifndef LWIP_STATS_DISPLAY
+#define LWIP_STATS_DISPLAY              0
+#endif
+
+/**
+ * LINK_STATS==1: Enable link stats.
+ */
+#ifndef LINK_STATS
+#define LINK_STATS                      1
+#endif
+
+/**
+ * ETHARP_STATS==1: Enable etharp stats.
+ */
+#ifndef ETHARP_STATS
+#define ETHARP_STATS                    (LWIP_ARP)
+#endif
+
+/**
+ * IP_STATS==1: Enable IP stats.
+ */
+#ifndef IP_STATS
+#define IP_STATS                        1
+#endif
+
+/**
+ * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is
+ * on if using either frag or reass.
+ */
+#ifndef IPFRAG_STATS
+#define IPFRAG_STATS                    (IP_REASSEMBLY || IP_FRAG)
+#endif
+
+/**
+ * ICMP_STATS==1: Enable ICMP stats.
+ */
+#ifndef ICMP_STATS
+#define ICMP_STATS                      1
+#endif
+
+/**
+ * IGMP_STATS==1: Enable IGMP stats.
+ */
+#ifndef IGMP_STATS
+#define IGMP_STATS                      (LWIP_IGMP)
+#endif
+
+/**
+ * UDP_STATS==1: Enable UDP stats. Default is on if
+ * UDP enabled, otherwise off.
+ */
+#ifndef UDP_STATS
+#define UDP_STATS                       (LWIP_UDP)
+#endif
+
+/**
+ * TCP_STATS==1: Enable TCP stats. Default is on if TCP
+ * enabled, otherwise off.
+ */
+#ifndef TCP_STATS
+#define TCP_STATS                       (LWIP_TCP)
+#endif
+
+/**
+ * MEM_STATS==1: Enable mem.c stats.
+ */
+#ifndef MEM_STATS
+#define MEM_STATS                       1
+#endif
+
+/**
+ * MEMP_STATS==1: Enable memp.c pool stats.
+ */
+#ifndef MEMP_STATS
+#define MEMP_STATS                      1
+#endif
+
+/**
+ * SYS_STATS==1: Enable system stats (sem and mbox counts, etc).
+ */
+#ifndef SYS_STATS
+#define SYS_STATS                       1
+#endif
+
+#else
+
+#define LINK_STATS                      0
+#define IP_STATS                        0
+#define IPFRAG_STATS                    0
+#define ICMP_STATS                      0
+#define IGMP_STATS                      0
+#define UDP_STATS                       0
+#define TCP_STATS                       0
+#define MEM_STATS                       0
+#define MEMP_STATS                      0
+#define SYS_STATS                       0
+#define LWIP_STATS_DISPLAY              0
+
+#endif /* LWIP_STATS */
+
+/*
+   ---------------------------------
+   ---------- PPP options ----------
+   ---------------------------------
+*/
+/**
+ * PPP_SUPPORT==1: Enable PPP.
+ */
+#ifndef PPP_SUPPORT
+#define PPP_SUPPORT                     0
+#endif
+
+/**
+ * PPPOE_SUPPORT==1: Enable PPP Over Ethernet
+ */
+#ifndef PPPOE_SUPPORT
+#define PPPOE_SUPPORT                   0
+#endif
+
+/**
+ * PPPOS_SUPPORT==1: Enable PPP Over Serial
+ */
+#ifndef PPPOS_SUPPORT
+#define PPPOS_SUPPORT                   PPP_SUPPORT
+#endif
+
+#if PPP_SUPPORT
+
+/**
+ * NUM_PPP: Max PPP sessions.
+ */
+#ifndef NUM_PPP
+#define NUM_PPP                         1
+#endif
+
+/**
+ * PAP_SUPPORT==1: Support PAP.
+ */
+#ifndef PAP_SUPPORT
+#define PAP_SUPPORT                     0
+#endif
+
+/**
+ * CHAP_SUPPORT==1: Support CHAP.
+ */
+#ifndef CHAP_SUPPORT
+#define CHAP_SUPPORT                    0
+#endif
+
+/**
+ * MSCHAP_SUPPORT==1: Support MSCHAP. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef MSCHAP_SUPPORT
+#define MSCHAP_SUPPORT                  0
+#endif
+
+/**
+ * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef CBCP_SUPPORT
+#define CBCP_SUPPORT                    0
+#endif
+
+/**
+ * CCP_SUPPORT==1: Support CCP. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef CCP_SUPPORT
+#define CCP_SUPPORT                     0
+#endif
+
+/**
+ * VJ_SUPPORT==1: Support VJ header compression.
+ */
+#ifndef VJ_SUPPORT
+#define VJ_SUPPORT                      0
+#endif
+
+/**
+ * MD5_SUPPORT==1: Support MD5 (see also CHAP).
+ */
+#ifndef MD5_SUPPORT
+#define MD5_SUPPORT                     0
+#endif
+
+/*
+ * Timeouts
+ */
+#ifndef FSM_DEFTIMEOUT
+#define FSM_DEFTIMEOUT                  6       /* Timeout time in seconds */
+#endif
+
+#ifndef FSM_DEFMAXTERMREQS
+#define FSM_DEFMAXTERMREQS              2       /* Maximum Terminate-Request transmissions */
+#endif
+
+#ifndef FSM_DEFMAXCONFREQS
+#define FSM_DEFMAXCONFREQS              10      /* Maximum Configure-Request transmissions */
+#endif
+
+#ifndef FSM_DEFMAXNAKLOOPS
+#define FSM_DEFMAXNAKLOOPS              5       /* Maximum number of nak loops */
+#endif
+
+#ifndef UPAP_DEFTIMEOUT
+#define UPAP_DEFTIMEOUT                 6       /* Timeout (seconds) for retransmitting req */
+#endif
+
+#ifndef UPAP_DEFREQTIME
+#define UPAP_DEFREQTIME                 30      /* Time to wait for auth-req from peer */
+#endif
+
+#ifndef CHAP_DEFTIMEOUT
+#define CHAP_DEFTIMEOUT                 6       /* Timeout time in seconds */
+#endif
+
+#ifndef CHAP_DEFTRANSMITS
+#define CHAP_DEFTRANSMITS               10      /* max # times to send challenge */
+#endif
+
+/* Interval in seconds between keepalive echo requests, 0 to disable. */
+#ifndef LCP_ECHOINTERVAL
+#define LCP_ECHOINTERVAL                0
+#endif
+
+/* Number of unanswered echo requests before failure. */
+#ifndef LCP_MAXECHOFAILS
+#define LCP_MAXECHOFAILS                3
+#endif
+
+/* Max Xmit idle time (in jiffies) before resend flag char. */
+#ifndef PPP_MAXIDLEFLAG
+#define PPP_MAXIDLEFLAG                 100
+#endif
+
+/*
+ * Packet sizes
+ *
+ * Note - lcp shouldn't be allowed to negotiate stuff outside these
+ *    limits.  See lcp.h in the pppd directory.
+ * (XXX - these constants should simply be shared by lcp.c instead
+ *    of living in lcp.h)
+ */
+#define PPP_MTU                         1500     /* Default MTU (size of Info field) */
+#ifndef PPP_MAXMTU
+/* #define PPP_MAXMTU  65535 - (PPP_HDRLEN + PPP_FCSLEN) */
+#define PPP_MAXMTU                      1500 /* Largest MTU we allow */
+#endif
+#define PPP_MINMTU                      64
+#define PPP_MRU                         1500     /* default MRU = max length of info field */
+#define PPP_MAXMRU                      1500     /* Largest MRU we allow */
+#ifndef PPP_DEFMRU
+#define PPP_DEFMRU                      296             /* Try for this */
+#endif
+#define PPP_MINMRU                      128             /* No MRUs below this */
+
+
+#define MAXNAMELEN                      256     /* max length of hostname or name for auth */
+#define MAXSECRETLEN                    256     /* max length of password or secret */
+
+#endif /* PPP_SUPPORT */
+
+/*
+   --------------------------------------
+   ---------- Checksum options ----------
+   --------------------------------------
+*/
+/**
+ * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.
+ */
+#ifndef CHECKSUM_GEN_IP
+#define CHECKSUM_GEN_IP                 1
+#endif
+
+/**
+ * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.
+ */
+#ifndef CHECKSUM_GEN_UDP
+#define CHECKSUM_GEN_UDP                1
+#endif
+
+/**
+ * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.
+ */
+#ifndef CHECKSUM_GEN_TCP
+#define CHECKSUM_GEN_TCP                1
+#endif
+
+/**
+ * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.
+ */
+#ifndef CHECKSUM_CHECK_IP
+#define CHECKSUM_CHECK_IP               1
+#endif
+
+/**
+ * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.
+ */
+#ifndef CHECKSUM_CHECK_UDP
+#define CHECKSUM_CHECK_UDP              1
+#endif
+
+/**
+ * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.
+ */
+#ifndef CHECKSUM_CHECK_TCP
+#define CHECKSUM_CHECK_TCP              1
+#endif
+
+/*
+   ---------------------------------------
+   ---------- Debugging options ----------
+   ---------------------------------------
+*/
+/**
+ * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is
+ * compared against this value. If it is smaller, then debugging
+ * messages are written.
+ */
+#ifndef LWIP_DBG_MIN_LEVEL
+#define LWIP_DBG_MIN_LEVEL              LWIP_DBG_LEVEL_OFF
+#endif
+
+/**
+ * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable
+ * debug messages of certain types.
+ */
+#ifndef LWIP_DBG_TYPES_ON
+#define LWIP_DBG_TYPES_ON               LWIP_DBG_ON
+#endif
+
+/**
+ * ETHARP_DEBUG: Enable debugging in etharp.c.
+ */
+#ifndef ETHARP_DEBUG
+#define ETHARP_DEBUG                    LWIP_DBG_OFF
+#endif
+
+/**
+ * NETIF_DEBUG: Enable debugging in netif.c.
+ */
+#ifndef NETIF_DEBUG
+#define NETIF_DEBUG                     LWIP_DBG_OFF
+#endif
+
+/**
+ * PBUF_DEBUG: Enable debugging in pbuf.c.
+ */
+#ifndef PBUF_DEBUG
+#define PBUF_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * API_LIB_DEBUG: Enable debugging in api_lib.c.
+ */
+#ifndef API_LIB_DEBUG
+#define API_LIB_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * API_MSG_DEBUG: Enable debugging in api_msg.c.
+ */
+#ifndef API_MSG_DEBUG
+#define API_MSG_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * SOCKETS_DEBUG: Enable debugging in sockets.c.
+ */
+#ifndef SOCKETS_DEBUG
+#define SOCKETS_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * ICMP_DEBUG: Enable debugging in icmp.c.
+ */
+#ifndef ICMP_DEBUG
+#define ICMP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * IGMP_DEBUG: Enable debugging in igmp.c.
+ */
+#ifndef IGMP_DEBUG
+#define IGMP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * INET_DEBUG: Enable debugging in inet.c.
+ */
+#ifndef INET_DEBUG
+#define INET_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * IP_DEBUG: Enable debugging for IP.
+ */
+#ifndef IP_DEBUG
+#define IP_DEBUG                        LWIP_DBG_OFF
+#endif
+
+/**
+ * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass.
+ */
+#ifndef IP_REASS_DEBUG
+#define IP_REASS_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * RAW_DEBUG: Enable debugging in raw.c.
+ */
+#ifndef RAW_DEBUG
+#define RAW_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * MEM_DEBUG: Enable debugging in mem.c.
+ */
+#ifndef MEM_DEBUG
+#define MEM_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * MEMP_DEBUG: Enable debugging in memp.c.
+ */
+#ifndef MEMP_DEBUG
+#define MEMP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * SYS_DEBUG: Enable debugging in sys.c.
+ */
+#ifndef SYS_DEBUG
+#define SYS_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_DEBUG: Enable debugging for TCP.
+ */
+#ifndef TCP_DEBUG
+#define TCP_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug.
+ */
+#ifndef TCP_INPUT_DEBUG
+#define TCP_INPUT_DEBUG                 LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit.
+ */
+#ifndef TCP_FR_DEBUG
+#define TCP_FR_DEBUG                    LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit
+ * timeout.
+ */
+#ifndef TCP_RTO_DEBUG
+#define TCP_RTO_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_CWND_DEBUG: Enable debugging for TCP congestion window.
+ */
+#ifndef TCP_CWND_DEBUG
+#define TCP_CWND_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating.
+ */
+#ifndef TCP_WND_DEBUG
+#define TCP_WND_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions.
+ */
+#ifndef TCP_OUTPUT_DEBUG
+#define TCP_OUTPUT_DEBUG                LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_RST_DEBUG: Enable debugging for TCP with the RST message.
+ */
+#ifndef TCP_RST_DEBUG
+#define TCP_RST_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths.
+ */
+#ifndef TCP_QLEN_DEBUG
+#define TCP_QLEN_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * UDP_DEBUG: Enable debugging in UDP.
+ */
+#ifndef UDP_DEBUG
+#define UDP_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * TCPIP_DEBUG: Enable debugging in tcpip.c.
+ */
+#ifndef TCPIP_DEBUG
+#define TCPIP_DEBUG                     LWIP_DBG_OFF
+#endif
+
+/**
+ * PPP_DEBUG: Enable debugging for PPP.
+ */
+#ifndef PPP_DEBUG
+#define PPP_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * SLIP_DEBUG: Enable debugging in slipif.c.
+ */
+#ifndef SLIP_DEBUG
+#define SLIP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * DHCP_DEBUG: Enable debugging in dhcp.c.
+ */
+#ifndef DHCP_DEBUG
+#define DHCP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * AUTOIP_DEBUG: Enable debugging in autoip.c.
+ */
+#ifndef AUTOIP_DEBUG
+#define AUTOIP_DEBUG                    LWIP_DBG_OFF
+#endif
+
+/**
+ * SNMP_MSG_DEBUG: Enable debugging for SNMP messages.
+ */
+#ifndef SNMP_MSG_DEBUG
+#define SNMP_MSG_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs.
+ */
+#ifndef SNMP_MIB_DEBUG
+#define SNMP_MIB_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * DNS_DEBUG: Enable debugging for DNS.
+ */
+#ifndef DNS_DEBUG
+#define DNS_DEBUG                       LWIP_DBG_OFF
+#endif
+
+#endif /* __LWIP_OPT_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/pbuf.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/pbuf.h
new file mode 100644
index 0000000..d02ab45
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/pbuf.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef __LWIP_PBUF_H__
+#define __LWIP_PBUF_H__
+
+#include "lwip/opt.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PBUF_TRANSPORT_HLEN 20
+#define PBUF_IP_HLEN        20
+
+typedef enum {
+  PBUF_TRANSPORT,
+  PBUF_IP,
+  PBUF_LINK,
+  PBUF_RAW
+} pbuf_layer;
+
+typedef enum {
+  PBUF_RAM, /* pbuf data is stored in RAM */
+  PBUF_ROM, /* pbuf data is stored in ROM */
+  PBUF_REF, /* pbuf comes from the pbuf pool */
+  PBUF_POOL /* pbuf payload refers to RAM */
+} pbuf_type;
+
+
+/** indicates this packet's data should be immediately passed to the application */
+#define PBUF_FLAG_PUSH 0x01U
+
+struct pbuf {
+  /** next pbuf in singly linked pbuf chain */
+  struct pbuf *next;
+
+  /** pointer to the actual data in the buffer */
+  void *payload;
+
+  /**
+   * total length of this buffer and all next buffers in chain
+   * belonging to the same packet.
+   *
+   * For non-queue packet chains this is the invariant:
+   * p->tot_len == p->len + (p->next? p->next->tot_len: 0)
+   */
+  u16_t tot_len;
+
+  /** length of this buffer */
+  u16_t len;
+
+  /** pbuf_type as u8_t instead of enum to save space */
+  u8_t /*pbuf_type*/ type;
+
+  /** misc flags */
+  u8_t flags;
+
+  /**
+   * the reference count always equals the number of pointers
+   * that refer to this pbuf. This can be pointers from an application,
+   * the stack itself, or pbuf->next pointers from a chain.
+   */
+  u16_t ref;
+
+};
+
+/* Initializes the pbuf module. This call is empty for now, but may not be in future. */
+#define pbuf_init()
+
+struct pbuf *pbuf_alloc(pbuf_layer l, u16_t size, pbuf_type type);
+void pbuf_realloc(struct pbuf *p, u16_t size);
+u8_t pbuf_header(struct pbuf *p, s16_t header_size);
+void pbuf_ref(struct pbuf *p);
+void pbuf_ref_chain(struct pbuf *p);
+u8_t pbuf_free(struct pbuf *p);
+u8_t pbuf_clen(struct pbuf *p);
+void pbuf_cat(struct pbuf *head, struct pbuf *tail);
+void pbuf_chain(struct pbuf *head, struct pbuf *tail);
+struct pbuf *pbuf_dechain(struct pbuf *p);
+err_t pbuf_copy(struct pbuf *p_to, struct pbuf *p_from);
+u16_t pbuf_copy_partial(struct pbuf *p, void *dataptr, u16_t len, u16_t offset);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_PBUF_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/raw.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/raw.h
new file mode 100644
index 0000000..8681ce2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/raw.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_RAW_H__
+#define __LWIP_RAW_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct raw_pcb {
+/* Common members of all PCB types */
+  IP_PCB;
+
+  struct raw_pcb *next;
+
+  u8_t protocol;
+
+  /* receive callback function
+   * @param arg user supplied argument (raw_pcb.recv_arg)
+   * @param pcb the raw_pcb which received data
+   * @param p the packet buffer that was received
+   * @param addr the remote IP address from which the packet was received
+   * @return 1 if the packet was 'eaten' (aka. deleted),
+   *         0 if the packet lives on
+   * If returning 1, the callback is responsible for freeing the pbuf
+   * if it's not used any more.
+   */
+  u8_t (* recv)(void *arg, struct raw_pcb *pcb, struct pbuf *p,
+    struct ip_addr *addr);
+  /* user-supplied argument for the recv callback */
+  void *recv_arg;
+};
+
+/* The following functions is the application layer interface to the
+   RAW code. */
+struct raw_pcb * raw_new        (u8_t proto);
+void             raw_remove     (struct raw_pcb *pcb);
+err_t            raw_bind       (struct raw_pcb *pcb, struct ip_addr *ipaddr);
+err_t            raw_connect    (struct raw_pcb *pcb, struct ip_addr *ipaddr);
+
+void             raw_recv       (struct raw_pcb *pcb,
+                                 u8_t (* recv)(void *arg, struct raw_pcb *pcb,
+                                              struct pbuf *p,
+                                              struct ip_addr *addr),
+                                 void *recv_arg);
+err_t            raw_sendto     (struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr);
+err_t            raw_send       (struct raw_pcb *pcb, struct pbuf *p);
+
+/* The following functions are the lower layer interface to RAW. */
+u8_t             raw_input      (struct pbuf *p, struct netif *inp);
+#define raw_init() /* Compatibility define, not init needed. */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_RAW */
+
+#endif /* __LWIP_RAW_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/sio.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/sio.h
new file mode 100644
index 0000000..79cf292
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/sio.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ */
+
+/*
+ * This is the interface to the platform specific serial IO module
+ * It needs to be implemented by those platforms which need SLIP or PPP
+ */
+
+#include "lwip/arch.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef __sio_fd_t_defined
+typedef void * sio_fd_t;
+#endif
+
+#ifndef sio_open
+sio_fd_t sio_open(u8_t);
+#endif
+
+#ifndef sio_send
+void sio_send(u8_t, sio_fd_t);
+#endif
+
+#ifndef sio_recv
+u8_t sio_recv(sio_fd_t);
+#endif
+
+#ifndef sio_read
+u32_t sio_read(sio_fd_t, u8_t *, u32_t);
+#endif
+
+#ifndef sio_write
+u32_t sio_write(sio_fd_t, u8_t *, u32_t);
+#endif
+
+#ifndef sio_read_abort
+void sio_read_abort(sio_fd_t);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/snmp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/snmp.h
new file mode 100644
index 0000000..d775d3e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/snmp.h
@@ -0,0 +1,364 @@
+/*
+ * Copyright (c) 2001, 2002 Leon Woestenberg 
+ * Copyright (c) 2001, 2002 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Leon Woestenberg 
+ *
+ */
+#ifndef __LWIP_SNMP_H__
+#define __LWIP_SNMP_H__
+
+#include "lwip/opt.h"
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @see RFC1213, "MIB-II, 6. Definitions"
+ */
+enum snmp_ifType {
+  snmp_ifType_other=1,                /* none of the following */
+  snmp_ifType_regular1822,
+  snmp_ifType_hdh1822,
+  snmp_ifType_ddn_x25,
+  snmp_ifType_rfc877_x25,
+  snmp_ifType_ethernet_csmacd,
+  snmp_ifType_iso88023_csmacd,
+  snmp_ifType_iso88024_tokenBus,
+  snmp_ifType_iso88025_tokenRing,
+  snmp_ifType_iso88026_man,
+  snmp_ifType_starLan,
+  snmp_ifType_proteon_10Mbit,
+  snmp_ifType_proteon_80Mbit,
+  snmp_ifType_hyperchannel,
+  snmp_ifType_fddi,
+  snmp_ifType_lapb,
+  snmp_ifType_sdlc,
+  snmp_ifType_ds1,                    /* T-1 */
+  snmp_ifType_e1,                     /* european equiv. of T-1 */
+  snmp_ifType_basicISDN,
+  snmp_ifType_primaryISDN,            /* proprietary serial */
+  snmp_ifType_propPointToPointSerial,
+  snmp_ifType_ppp,
+  snmp_ifType_softwareLoopback,
+  snmp_ifType_eon,                    /* CLNP over IP [11] */
+  snmp_ifType_ethernet_3Mbit,
+  snmp_ifType_nsip,                   /* XNS over IP */
+  snmp_ifType_slip,                   /* generic SLIP */
+  snmp_ifType_ultra,                  /* ULTRA technologies */
+  snmp_ifType_ds3,                    /* T-3 */
+  snmp_ifType_sip,                    /* SMDS */
+  snmp_ifType_frame_relay
+};
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+/** SNMP "sysuptime" Interval */
+#define SNMP_SYSUPTIME_INTERVAL 10
+
+/** fixed maximum length for object identifier type */
+#define LWIP_SNMP_OBJ_ID_LEN 32
+
+/** internal object identifier representation */
+struct snmp_obj_id
+{
+  u8_t len;
+  s32_t id[LWIP_SNMP_OBJ_ID_LEN];
+};
+
+/* system */
+void snmp_set_sysdesr(u8_t* str, u8_t* len);
+void snmp_set_sysobjid(struct snmp_obj_id *oid);
+void snmp_get_sysobjid_ptr(struct snmp_obj_id **oid);
+void snmp_inc_sysuptime(void);
+void snmp_add_sysuptime(u32_t value);
+void snmp_get_sysuptime(u32_t *value);
+void snmp_set_syscontact(u8_t *ocstr, u8_t *ocstrlen);
+void snmp_set_sysname(u8_t *ocstr, u8_t *ocstrlen);
+void snmp_set_syslocation(u8_t *ocstr, u8_t *ocstrlen);
+
+/* network interface */
+void snmp_add_ifinoctets(struct netif *ni, u32_t value);
+void snmp_inc_ifinucastpkts(struct netif *ni);
+void snmp_inc_ifinnucastpkts(struct netif *ni);
+void snmp_inc_ifindiscards(struct netif *ni);
+void snmp_add_ifoutoctets(struct netif *ni, u32_t value);
+void snmp_inc_ifoutucastpkts(struct netif *ni);
+void snmp_inc_ifoutnucastpkts(struct netif *ni);
+void snmp_inc_ifoutdiscards(struct netif *ni);
+void snmp_inc_iflist(void);
+void snmp_dec_iflist(void);
+
+/* ARP (for atTable and ipNetToMediaTable) */
+void snmp_insert_arpidx_tree(struct netif *ni, struct ip_addr *ip);
+void snmp_delete_arpidx_tree(struct netif *ni, struct ip_addr *ip);
+
+/* IP */
+void snmp_inc_ipinreceives(void);
+void snmp_inc_ipinhdrerrors(void);
+void snmp_inc_ipinaddrerrors(void);
+void snmp_inc_ipforwdatagrams(void);
+void snmp_inc_ipinunknownprotos(void);
+void snmp_inc_ipindiscards(void);
+void snmp_inc_ipindelivers(void);
+void snmp_inc_ipoutrequests(void);
+void snmp_inc_ipoutdiscards(void);
+void snmp_inc_ipoutnoroutes(void);
+void snmp_inc_ipreasmreqds(void);
+void snmp_inc_ipreasmoks(void);
+void snmp_inc_ipreasmfails(void);
+void snmp_inc_ipfragoks(void);
+void snmp_inc_ipfragfails(void);
+void snmp_inc_ipfragcreates(void);
+void snmp_inc_iproutingdiscards(void);
+void snmp_insert_ipaddridx_tree(struct netif *ni);
+void snmp_delete_ipaddridx_tree(struct netif *ni);
+void snmp_insert_iprteidx_tree(u8_t dflt, struct netif *ni);
+void snmp_delete_iprteidx_tree(u8_t dflt, struct netif *ni);
+
+/* ICMP */
+void snmp_inc_icmpinmsgs(void);
+void snmp_inc_icmpinerrors(void);
+void snmp_inc_icmpindestunreachs(void);
+void snmp_inc_icmpintimeexcds(void);
+void snmp_inc_icmpinparmprobs(void);
+void snmp_inc_icmpinsrcquenchs(void);
+void snmp_inc_icmpinredirects(void);
+void snmp_inc_icmpinechos(void);
+void snmp_inc_icmpinechoreps(void);
+void snmp_inc_icmpintimestamps(void);
+void snmp_inc_icmpintimestampreps(void);
+void snmp_inc_icmpinaddrmasks(void);
+void snmp_inc_icmpinaddrmaskreps(void);
+void snmp_inc_icmpoutmsgs(void);
+void snmp_inc_icmpouterrors(void);
+void snmp_inc_icmpoutdestunreachs(void);
+void snmp_inc_icmpouttimeexcds(void);
+void snmp_inc_icmpoutparmprobs(void);
+void snmp_inc_icmpoutsrcquenchs(void);
+void snmp_inc_icmpoutredirects(void);
+void snmp_inc_icmpoutechos(void);
+void snmp_inc_icmpoutechoreps(void);
+void snmp_inc_icmpouttimestamps(void);
+void snmp_inc_icmpouttimestampreps(void);
+void snmp_inc_icmpoutaddrmasks(void);
+void snmp_inc_icmpoutaddrmaskreps(void);
+
+/* TCP */
+void snmp_inc_tcpactiveopens(void);
+void snmp_inc_tcppassiveopens(void);
+void snmp_inc_tcpattemptfails(void);
+void snmp_inc_tcpestabresets(void);
+void snmp_inc_tcpinsegs(void);
+void snmp_inc_tcpoutsegs(void);
+void snmp_inc_tcpretranssegs(void);
+void snmp_inc_tcpinerrs(void);
+void snmp_inc_tcpoutrsts(void);
+
+/* UDP */
+void snmp_inc_udpindatagrams(void);
+void snmp_inc_udpnoports(void);
+void snmp_inc_udpinerrors(void);
+void snmp_inc_udpoutdatagrams(void);
+void snmp_insert_udpidx_tree(struct udp_pcb *pcb);
+void snmp_delete_udpidx_tree(struct udp_pcb *pcb);
+
+/* SNMP */
+void snmp_inc_snmpinpkts(void);
+void snmp_inc_snmpoutpkts(void);
+void snmp_inc_snmpinbadversions(void);
+void snmp_inc_snmpinbadcommunitynames(void);
+void snmp_inc_snmpinbadcommunityuses(void);
+void snmp_inc_snmpinasnparseerrs(void);
+void snmp_inc_snmpintoobigs(void);
+void snmp_inc_snmpinnosuchnames(void);
+void snmp_inc_snmpinbadvalues(void);
+void snmp_inc_snmpinreadonlys(void);
+void snmp_inc_snmpingenerrs(void);
+void snmp_add_snmpintotalreqvars(u8_t value);
+void snmp_add_snmpintotalsetvars(u8_t value);
+void snmp_inc_snmpingetrequests(void);
+void snmp_inc_snmpingetnexts(void);
+void snmp_inc_snmpinsetrequests(void);
+void snmp_inc_snmpingetresponses(void);
+void snmp_inc_snmpintraps(void);
+void snmp_inc_snmpouttoobigs(void);
+void snmp_inc_snmpoutnosuchnames(void);
+void snmp_inc_snmpoutbadvalues(void);
+void snmp_inc_snmpoutgenerrs(void);
+void snmp_inc_snmpoutgetrequests(void);
+void snmp_inc_snmpoutgetnexts(void);
+void snmp_inc_snmpoutsetrequests(void);
+void snmp_inc_snmpoutgetresponses(void);
+void snmp_inc_snmpouttraps(void);
+void snmp_get_snmpgrpid_ptr(struct snmp_obj_id **oid);
+void snmp_set_snmpenableauthentraps(u8_t *value);
+void snmp_get_snmpenableauthentraps(u8_t *value);
+
+/* LWIP_SNMP support not available */
+/* define everything to be empty */
+#else
+
+/* system */
+#define snmp_set_sysdesr(str, len)
+#define snmp_set_sysobjid(oid);
+#define snmp_get_sysobjid_ptr(oid)
+#define snmp_inc_sysuptime()
+#define snmp_add_sysuptime(value)
+#define snmp_get_sysuptime(value)
+#define snmp_set_syscontact(ocstr, ocstrlen);
+#define snmp_set_sysname(ocstr, ocstrlen);
+#define snmp_set_syslocation(ocstr, ocstrlen);
+
+/* network interface */
+#define snmp_add_ifinoctets(ni,value)
+#define snmp_inc_ifinucastpkts(ni)
+#define snmp_inc_ifinnucastpkts(ni)
+#define snmp_inc_ifindiscards(ni)
+#define snmp_add_ifoutoctets(ni,value)
+#define snmp_inc_ifoutucastpkts(ni)
+#define snmp_inc_ifoutnucastpkts(ni)
+#define snmp_inc_ifoutdiscards(ni)
+#define snmp_inc_iflist()
+#define snmp_dec_iflist()
+
+/* ARP */
+#define snmp_insert_arpidx_tree(ni,ip)
+#define snmp_delete_arpidx_tree(ni,ip)
+
+/* IP */
+#define snmp_inc_ipinreceives()
+#define snmp_inc_ipinhdrerrors()
+#define snmp_inc_ipinaddrerrors()
+#define snmp_inc_ipforwdatagrams()
+#define snmp_inc_ipinunknownprotos()
+#define snmp_inc_ipindiscards()
+#define snmp_inc_ipindelivers()
+#define snmp_inc_ipoutrequests()
+#define snmp_inc_ipoutdiscards()
+#define snmp_inc_ipoutnoroutes()
+#define snmp_inc_ipreasmreqds()
+#define snmp_inc_ipreasmoks()
+#define snmp_inc_ipreasmfails()
+#define snmp_inc_ipfragoks()
+#define snmp_inc_ipfragfails()
+#define snmp_inc_ipfragcreates()
+#define snmp_inc_iproutingdiscards()
+#define snmp_insert_ipaddridx_tree(ni)
+#define snmp_delete_ipaddridx_tree(ni)
+#define snmp_insert_iprteidx_tree(dflt, ni)
+#define snmp_delete_iprteidx_tree(dflt, ni)
+
+/* ICMP */
+#define snmp_inc_icmpinmsgs()
+#define snmp_inc_icmpinerrors()
+#define snmp_inc_icmpindestunreachs()
+#define snmp_inc_icmpintimeexcds()
+#define snmp_inc_icmpinparmprobs()
+#define snmp_inc_icmpinsrcquenchs()
+#define snmp_inc_icmpinredirects()
+#define snmp_inc_icmpinechos()
+#define snmp_inc_icmpinechoreps()
+#define snmp_inc_icmpintimestamps()
+#define snmp_inc_icmpintimestampreps()
+#define snmp_inc_icmpinaddrmasks()
+#define snmp_inc_icmpinaddrmaskreps()
+#define snmp_inc_icmpoutmsgs()
+#define snmp_inc_icmpouterrors()
+#define snmp_inc_icmpoutdestunreachs()
+#define snmp_inc_icmpouttimeexcds()
+#define snmp_inc_icmpoutparmprobs()
+#define snmp_inc_icmpoutsrcquenchs()
+#define snmp_inc_icmpoutredirects()
+#define snmp_inc_icmpoutechos()
+#define snmp_inc_icmpoutechoreps()
+#define snmp_inc_icmpouttimestamps()
+#define snmp_inc_icmpouttimestampreps()
+#define snmp_inc_icmpoutaddrmasks()
+#define snmp_inc_icmpoutaddrmaskreps()
+/* TCP */
+#define snmp_inc_tcpactiveopens()
+#define snmp_inc_tcppassiveopens()
+#define snmp_inc_tcpattemptfails()
+#define snmp_inc_tcpestabresets()
+#define snmp_inc_tcpinsegs()
+#define snmp_inc_tcpoutsegs()
+#define snmp_inc_tcpretranssegs()
+#define snmp_inc_tcpinerrs()
+#define snmp_inc_tcpoutrsts()
+
+/* UDP */
+#define snmp_inc_udpindatagrams()
+#define snmp_inc_udpnoports()
+#define snmp_inc_udpinerrors()
+#define snmp_inc_udpoutdatagrams()
+#define snmp_insert_udpidx_tree(pcb)
+#define snmp_delete_udpidx_tree(pcb)
+
+/* SNMP */
+#define snmp_inc_snmpinpkts()
+#define snmp_inc_snmpoutpkts()
+#define snmp_inc_snmpinbadversions()
+#define snmp_inc_snmpinbadcommunitynames()
+#define snmp_inc_snmpinbadcommunityuses()
+#define snmp_inc_snmpinasnparseerrs()
+#define snmp_inc_snmpintoobigs()
+#define snmp_inc_snmpinnosuchnames()
+#define snmp_inc_snmpinbadvalues()
+#define snmp_inc_snmpinreadonlys()
+#define snmp_inc_snmpingenerrs()
+#define snmp_add_snmpintotalreqvars(value)
+#define snmp_add_snmpintotalsetvars(value)
+#define snmp_inc_snmpingetrequests()
+#define snmp_inc_snmpingetnexts()
+#define snmp_inc_snmpinsetrequests()
+#define snmp_inc_snmpingetresponses()
+#define snmp_inc_snmpintraps()
+#define snmp_inc_snmpouttoobigs()
+#define snmp_inc_snmpoutnosuchnames()
+#define snmp_inc_snmpoutbadvalues()
+#define snmp_inc_snmpoutgenerrs()
+#define snmp_inc_snmpoutgetrequests()
+#define snmp_inc_snmpoutgetnexts()
+#define snmp_inc_snmpoutsetrequests()
+#define snmp_inc_snmpoutgetresponses()
+#define snmp_inc_snmpouttraps()
+#define snmp_get_snmpgrpid_ptr(oid)
+#define snmp_set_snmpenableauthentraps(value)
+#define snmp_get_snmpenableauthentraps(value)
+
+#endif /* LWIP_SNMP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_SNMP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/snmp_asn1.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/snmp_asn1.h
new file mode 100644
index 0000000..fd1c4ec
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/snmp_asn1.h
@@ -0,0 +1,97 @@
+/**
+ * @file
+ * Abstract Syntax Notation One (ISO 8824, 8825) codec.
+ */
+ 
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#ifndef __LWIP_SNMP_ASN1_H__
+#define __LWIP_SNMP_ASN1_H__
+
+#include "lwip/opt.h"
+#include "lwip/err.h"
+#include "lwip/pbuf.h"
+#include "lwip/snmp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SNMP_ASN1_UNIV   (!0x80 | !0x40)
+#define SNMP_ASN1_APPLIC (!0x80 |  0x40)
+#define SNMP_ASN1_CONTXT ( 0x80 | !0x40)
+
+#define SNMP_ASN1_CONSTR (0x20)
+#define SNMP_ASN1_PRIMIT (!0x20)
+
+/* universal tags */
+#define SNMP_ASN1_INTEG  2
+#define SNMP_ASN1_OC_STR 4
+#define SNMP_ASN1_NUL    5
+#define SNMP_ASN1_OBJ_ID 6
+#define SNMP_ASN1_SEQ    16
+
+/* application specific (SNMP) tags */
+#define SNMP_ASN1_IPADDR 0    /* octet string size(4) */
+#define SNMP_ASN1_COUNTER 1   /* u32_t */
+#define SNMP_ASN1_GAUGE 2     /* u32_t */
+#define SNMP_ASN1_TIMETICKS 3 /* u32_t */
+#define SNMP_ASN1_OPAQUE 4    /* octet string */
+
+/* context specific (SNMP) tags */
+#define SNMP_ASN1_PDU_GET_REQ 0
+#define SNMP_ASN1_PDU_GET_NEXT_REQ 1
+#define SNMP_ASN1_PDU_GET_RESP 2
+#define SNMP_ASN1_PDU_SET_REQ 3
+#define SNMP_ASN1_PDU_TRAP 4
+
+err_t snmp_asn1_dec_type(struct pbuf *p, u16_t ofs, u8_t *type);
+err_t snmp_asn1_dec_length(struct pbuf *p, u16_t ofs, u8_t *octets_used, u16_t *length);
+err_t snmp_asn1_dec_u32t(struct pbuf *p, u16_t ofs, u16_t len, u32_t *value);
+err_t snmp_asn1_dec_s32t(struct pbuf *p, u16_t ofs, u16_t len, s32_t *value);
+err_t snmp_asn1_dec_oid(struct pbuf *p, u16_t ofs, u16_t len, struct snmp_obj_id *oid);
+err_t snmp_asn1_dec_raw(struct pbuf *p, u16_t ofs, u16_t len, u16_t raw_len, u8_t *raw);
+
+void snmp_asn1_enc_length_cnt(u16_t length, u8_t *octets_needed);
+void snmp_asn1_enc_u32t_cnt(u32_t value, u16_t *octets_needed);
+void snmp_asn1_enc_s32t_cnt(s32_t value, u16_t *octets_needed);
+void snmp_asn1_enc_oid_cnt(u8_t ident_len, s32_t *ident, u16_t *octets_needed);
+err_t snmp_asn1_enc_type(struct pbuf *p, u16_t ofs, u8_t type);
+err_t snmp_asn1_enc_length(struct pbuf *p, u16_t ofs, u16_t length);
+err_t snmp_asn1_enc_u32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, u32_t value);
+err_t snmp_asn1_enc_s32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, s32_t value);
+err_t snmp_asn1_enc_oid(struct pbuf *p, u16_t ofs, u8_t ident_len, s32_t *ident);
+err_t snmp_asn1_enc_raw(struct pbuf *p, u16_t ofs, u8_t raw_len, u8_t *raw);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_SNMP_ASN1_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/snmp_msg.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/snmp_msg.h
new file mode 100644
index 0000000..017be6a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/snmp_msg.h
@@ -0,0 +1,307 @@
+/**
+ * @file
+ * SNMP Agent message handling structures.
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#ifndef __LWIP_SNMP_MSG_H__
+#define __LWIP_SNMP_MSG_H__
+
+#include "lwip/opt.h"
+#include "lwip/snmp.h"
+#include "lwip/snmp_structs.h"
+
+#if SNMP_PRIVATE_MIB
+#include "private_mib.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* The listen port of the SNMP agent. Clients have to make their requests to
+   this port. Most standard clients won't work if you change this! */
+#ifndef SNMP_IN_PORT
+#define SNMP_IN_PORT 161
+#endif
+/* The remote port the SNMP agent sends traps to. Most standard trap sinks won't
+   work if you change this! */
+#ifndef SNMP_TRAP_PORT
+#define SNMP_TRAP_PORT 162
+#endif
+
+#define SNMP_ES_NOERROR 0
+#define SNMP_ES_TOOBIG 1
+#define SNMP_ES_NOSUCHNAME 2
+#define SNMP_ES_BADVALUE 3
+#define SNMP_ES_READONLY 4
+#define SNMP_ES_GENERROR 5
+
+#define SNMP_GENTRAP_COLDSTART 0
+#define SNMP_GENTRAP_WARMSTART 1
+#define SNMP_GENTRAP_AUTHFAIL 4
+#define SNMP_GENTRAP_ENTERPRISESPC 6
+
+struct snmp_varbind
+{
+  /* next pointer, NULL for last in list */
+  struct snmp_varbind *next;
+  /* previous pointer, NULL for first in list */
+  struct snmp_varbind *prev;
+
+  /* object identifier length (in s32_t) */
+  u8_t ident_len;
+  /* object identifier array */
+  s32_t *ident;
+
+  /* object value ASN1 type */
+  u8_t value_type;
+  /* object value length (in u8_t) */
+  u8_t value_len;
+  /* object value */
+  void *value;
+
+  /* encoding varbind seq length length */
+  u8_t seqlenlen;
+  /* encoding object identifier length length */
+  u8_t olenlen;
+  /* encoding object value length length */
+  u8_t vlenlen;
+  /* encoding varbind seq length */
+  u16_t seqlen;
+  /* encoding object identifier length */
+  u16_t olen;
+  /* encoding object value length */
+  u16_t vlen;
+};
+
+struct snmp_varbind_root
+{
+  struct snmp_varbind *head;
+  struct snmp_varbind *tail;
+  /* number of variable bindings in list */
+  u8_t count;
+  /* encoding varbind-list seq length length */
+  u8_t seqlenlen;
+  /* encoding varbind-list seq length */
+  u16_t seqlen;
+};
+
+/** output response message header length fields */
+struct snmp_resp_header_lengths
+{
+  /* encoding error-index length length */
+  u8_t erridxlenlen;
+  /* encoding error-status length length */
+  u8_t errstatlenlen;
+  /* encoding request id length length */
+  u8_t ridlenlen;
+  /* encoding pdu length length */
+  u8_t pdulenlen;
+  /* encoding community length length */
+  u8_t comlenlen;
+  /* encoding version length length */
+  u8_t verlenlen;
+  /* encoding sequence length length */
+  u8_t seqlenlen;
+
+  /* encoding error-index length */
+  u16_t erridxlen;
+  /* encoding error-status length */
+  u16_t errstatlen;
+  /* encoding request id length */
+  u16_t ridlen;
+  /* encoding pdu length */
+  u16_t pdulen;
+  /* encoding community length */
+  u16_t comlen;
+  /* encoding version length */
+  u16_t verlen;
+  /* encoding sequence length */
+  u16_t seqlen;
+};
+
+/** output response message header length fields */
+struct snmp_trap_header_lengths
+{
+  /* encoding timestamp length length */
+  u8_t tslenlen;
+  /* encoding specific-trap length length */
+  u8_t strplenlen;
+  /* encoding generic-trap length length */
+  u8_t gtrplenlen;
+  /* encoding agent-addr length length */
+  u8_t aaddrlenlen;
+  /* encoding enterprise-id length length */
+  u8_t eidlenlen;
+  /* encoding pdu length length */
+  u8_t pdulenlen;
+  /* encoding community length length */
+  u8_t comlenlen;
+  /* encoding version length length */
+  u8_t verlenlen;
+  /* encoding sequence length length */
+  u8_t seqlenlen;
+
+  /* encoding timestamp length */
+  u16_t tslen;
+  /* encoding specific-trap length */
+  u16_t strplen;
+  /* encoding generic-trap length */
+  u16_t gtrplen;
+  /* encoding agent-addr length */
+  u16_t aaddrlen;
+  /* encoding enterprise-id length */
+  u16_t eidlen;
+  /* encoding pdu length */
+  u16_t pdulen;
+  /* encoding community length */
+  u16_t comlen;
+  /* encoding version length */
+  u16_t verlen;
+  /* encoding sequence length */
+  u16_t seqlen;
+};
+
+/* Accepting new SNMP messages. */
+#define SNMP_MSG_EMPTY                 0
+/* Search for matching object for variable binding. */
+#define SNMP_MSG_SEARCH_OBJ            1
+/* Perform SNMP operation on in-memory object.
+   Pass-through states, for symmetry only. */
+#define SNMP_MSG_INTERNAL_GET_OBJDEF   2
+#define SNMP_MSG_INTERNAL_GET_VALUE    3
+#define SNMP_MSG_INTERNAL_SET_TEST     4
+#define SNMP_MSG_INTERNAL_GET_OBJDEF_S 5
+#define SNMP_MSG_INTERNAL_SET_VALUE    6
+/* Perform SNMP operation on object located externally.
+   In theory this could be used for building a proxy agent.
+   Practical use is for an enterprise spc. app. gateway. */
+#define SNMP_MSG_EXTERNAL_GET_OBJDEF   7
+#define SNMP_MSG_EXTERNAL_GET_VALUE    8
+#define SNMP_MSG_EXTERNAL_SET_TEST     9
+#define SNMP_MSG_EXTERNAL_GET_OBJDEF_S 10
+#define SNMP_MSG_EXTERNAL_SET_VALUE    11
+
+#define SNMP_COMMUNITY_STR_LEN 64
+struct snmp_msg_pstat
+{
+  /* lwIP local port (161) binding */
+  struct udp_pcb *pcb;
+  /* source IP address */
+  struct ip_addr sip;
+  /* source UDP port */
+  u16_t sp;
+  /* request type */
+  u8_t rt;
+  /* request ID */
+  s32_t rid;
+  /* error status */
+  s32_t error_status;
+  /* error index */
+  s32_t error_index;
+  /* community name (zero terminated) */
+  u8_t community[SNMP_COMMUNITY_STR_LEN + 1];
+  /* community string length (exclusive zero term) */
+  u8_t com_strlen;
+  /* one out of MSG_EMPTY, MSG_DEMUX, MSG_INTERNAL, MSG_EXTERNAL_x */
+  u8_t state;
+  /* saved arguments for MSG_EXTERNAL_x */
+  struct mib_external_node *ext_mib_node;
+  struct snmp_name_ptr ext_name_ptr;
+  struct obj_def ext_object_def;
+  struct snmp_obj_id ext_oid;
+  /* index into input variable binding list */
+  u8_t vb_idx;
+  /* ptr into input variable binding list */
+  struct snmp_varbind *vb_ptr;
+  /* list of variable bindings from input */
+  struct snmp_varbind_root invb;
+  /* list of variable bindings to output */
+  struct snmp_varbind_root outvb;
+  /* output response lengths used in ASN encoding */
+  struct snmp_resp_header_lengths rhl;
+};
+
+struct snmp_msg_trap
+{
+  /* lwIP local port (161) binding */
+  struct udp_pcb *pcb;
+  /* destination IP address in network order */
+  struct ip_addr dip;
+
+  /* source enterprise ID (sysObjectID) */
+  struct snmp_obj_id *enterprise;
+  /* source IP address, raw network order format */
+  u8_t sip_raw[4];
+  /* generic trap code */
+  u32_t gen_trap;
+  /* specific trap code */
+  u32_t spc_trap;
+  /* timestamp */
+  u32_t ts;
+  /* list of variable bindings to output */
+  struct snmp_varbind_root outvb;
+  /* output trap lengths used in ASN encoding */
+  struct snmp_trap_header_lengths thl;
+};
+
+/** Agent Version constant, 0 = v1 oddity */
+extern const s32_t snmp_version;
+/** Agent default "public" community string */
+extern const char snmp_publiccommunity[7];
+
+extern struct snmp_msg_trap trap_msg;
+
+/** Agent setup, start listening to port 161. */
+void snmp_init(void);
+void snmp_trap_dst_enable(u8_t dst_idx, u8_t enable);
+void snmp_trap_dst_ip_set(u8_t dst_idx, struct ip_addr *dst);
+
+/** Varbind-list functions. */
+struct snmp_varbind* snmp_varbind_alloc(struct snmp_obj_id *oid, u8_t type, u8_t len);
+void snmp_varbind_free(struct snmp_varbind *vb);
+void snmp_varbind_list_free(struct snmp_varbind_root *root);
+void snmp_varbind_tail_add(struct snmp_varbind_root *root, struct snmp_varbind *vb);
+struct snmp_varbind* snmp_varbind_tail_remove(struct snmp_varbind_root *root);
+
+/** Handle an internal (recv) or external (private response) event. */
+void snmp_msg_event(u8_t request_id);
+err_t snmp_send_response(struct snmp_msg_pstat *m_stat);
+err_t snmp_send_trap(s8_t generic_trap, struct snmp_obj_id *eoid, s32_t specific_trap);
+void snmp_coldstart_trap(void);
+void snmp_authfail_trap(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_SNMP_MSG_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/snmp_structs.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/snmp_structs.h
new file mode 100644
index 0000000..2c86a98
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/snmp_structs.h
@@ -0,0 +1,262 @@
+/**
+ * @file
+ * Generic MIB tree structures.
+ *
+ * @todo namespace prefixes
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#ifndef __LWIP_SNMP_STRUCTS_H__
+#define __LWIP_SNMP_STRUCTS_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/snmp.h"
+
+#if SNMP_PRIVATE_MIB
+#include "private_mib.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* MIB object instance */
+#define MIB_OBJECT_NONE 0 
+#define MIB_OBJECT_SCALAR 1
+#define MIB_OBJECT_TAB 2
+
+/* MIB object access */
+#define MIB_OBJECT_READ_ONLY 0
+#define MIB_OBJECT_READ_WRITE 1
+#define MIB_OBJECT_WRITE_ONLY 2
+#define MIB_OBJECT_NOT_ACCESSIBLE 3
+
+/** object definition returned by (get_object_def)() */
+struct obj_def
+{
+  /* MIB_OBJECT_NONE (0), MIB_OBJECT_SCALAR (1), MIB_OBJECT_TAB (2) */
+  u8_t instance;
+  /* 0 read-only, 1 read-write, 2 write-only, 3 not-accessible */
+  u8_t access;
+  /* ASN type for this object */
+  u8_t asn_type;
+  /* value length (host length) */
+  u16_t v_len;
+  /* length of instance part of supplied object identifier */
+  u8_t  id_inst_len;
+  /* instance part of supplied object identifier */
+  s32_t *id_inst_ptr;
+};
+
+struct snmp_name_ptr
+{
+  u8_t ident_len;
+  s32_t *ident;
+};
+
+/** MIB const scalar (.0) node */
+#define MIB_NODE_SC 0x01
+/** MIB const array node */
+#define MIB_NODE_AR 0x02
+/** MIB array node (mem_malloced from RAM) */
+#define MIB_NODE_RA 0x03
+/** MIB list root node (mem_malloced from RAM) */
+#define MIB_NODE_LR 0x04
+/** MIB node for external objects */
+#define MIB_NODE_EX 0x05
+
+/** node "base class" layout, the mandatory fields for a node  */
+struct mib_node
+{
+  /** returns struct obj_def for the given object identifier */
+  void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od);
+  /** returns object value for the given object identifier,
+     @note the caller must allocate at least len bytes for the value */
+  void (*get_value)(struct obj_def *od, u16_t len, void *value);
+  /** tests length and/or range BEFORE setting */
+  u8_t (*set_test)(struct obj_def *od, u16_t len, void *value);
+  /** sets object value, only to be called when set_test()  */
+  void (*set_value)(struct obj_def *od, u16_t len, void *value);  
+  /** One out of MIB_NODE_AR, MIB_NODE_LR or MIB_NODE_EX */
+  const u8_t node_type;
+  /* array or max list length */
+  const u16_t maxlength;
+};
+
+/** derived node for scalars .0 index */
+typedef struct mib_node mib_scalar_node;
+
+/** derived node, points to a fixed size const array
+    of sub-identifiers plus a 'child' pointer */
+struct mib_array_node
+{
+  /* inherited "base class" members */
+  void (* const get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od);
+  void (* const get_value)(struct obj_def *od, u16_t len, void *value);
+  u8_t (*set_test)(struct obj_def *od, u16_t len, void *value);
+  void (*set_value)(struct obj_def *od, u16_t len, void *value);
+
+  const u8_t node_type;
+  const u16_t maxlength;
+
+  /* aditional struct members */
+  const s32_t *objid;
+  struct mib_node* const *nptr;
+};
+
+/** derived node, points to a fixed size mem_malloced array
+    of sub-identifiers plus a 'child' pointer */
+struct mib_ram_array_node
+{
+  /* inherited "base class" members */
+  void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od);
+  void (*get_value)(struct obj_def *od, u16_t len, void *value);
+  u8_t (*set_test)(struct obj_def *od, u16_t len, void *value);
+  void (*set_value)(struct obj_def *od, u16_t len, void *value);
+
+  u8_t node_type;
+  u16_t maxlength;
+
+  /* aditional struct members */
+  s32_t *objid;
+  struct mib_node **nptr;
+};
+
+struct mib_list_node
+{
+  struct mib_list_node *prev;  
+  struct mib_list_node *next;
+  s32_t objid;
+  struct mib_node *nptr;
+};
+
+/** derived node, points to a doubly linked list
+    of sub-identifiers plus a 'child' pointer */
+struct mib_list_rootnode
+{
+  /* inherited "base class" members */
+  void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od);
+  void (*get_value)(struct obj_def *od, u16_t len, void *value);
+  u8_t (*set_test)(struct obj_def *od, u16_t len, void *value);
+  void (*set_value)(struct obj_def *od, u16_t len, void *value);
+
+  u8_t node_type;
+  u16_t maxlength;
+
+  /* aditional struct members */
+  struct mib_list_node *head;
+  struct mib_list_node *tail;
+  /* counts list nodes in list  */
+  u16_t count;
+};
+
+/** derived node, has access functions for mib object in external memory or device
+    using 'tree_level' and 'idx', with a range 0 .. (level_length() - 1) */
+struct mib_external_node
+{
+  /* inherited "base class" members */
+  void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od);
+  void (*get_value)(struct obj_def *od, u16_t len, void *value);
+  u8_t (*set_test)(struct obj_def *od, u16_t len, void *value);
+  void (*set_value)(struct obj_def *od, u16_t len, void *value);
+
+  u8_t node_type;
+  u16_t maxlength;
+
+  /* aditional struct members */
+  /** points to an extenal (in memory) record of some sort of addressing
+      information, passed to and interpreted by the funtions below */
+  void* addr_inf;
+  /** tree levels under this node */
+  u8_t tree_levels;
+  /** number of objects at this level */
+  u16_t (*level_length)(void* addr_inf, u8_t level);
+  /** compares object sub identifier with external id
+      return zero when equal, nonzero when unequal */
+  s32_t (*ident_cmp)(void* addr_inf, u8_t level, u16_t idx, s32_t sub_id);
+  void (*get_objid)(void* addr_inf, u8_t level, u16_t idx, s32_t *sub_id);
+
+  /** async Questions */
+  void (*get_object_def_q)(void* addr_inf, u8_t rid, u8_t ident_len, s32_t *ident);
+  void (*get_value_q)(u8_t rid, struct obj_def *od);
+  void (*set_test_q)(u8_t rid, struct obj_def *od);
+  void (*set_value_q)(u8_t rid, struct obj_def *od, u16_t len, void *value);
+  /** async Answers */
+  void (*get_object_def_a)(u8_t rid, u8_t ident_len, s32_t *ident, struct obj_def *od);
+  void (*get_value_a)(u8_t rid, struct obj_def *od, u16_t len, void *value);
+  u8_t (*set_test_a)(u8_t rid, struct obj_def *od, u16_t len, void *value);
+  void (*set_value_a)(u8_t rid, struct obj_def *od, u16_t len, void *value);
+  /** async Panic Close (agent returns error reply, 
+      e.g. used for external transaction cleanup) */
+  void (*get_object_def_pc)(u8_t rid, u8_t ident_len, s32_t *ident);
+  void (*get_value_pc)(u8_t rid, struct obj_def *od);
+  void (*set_test_pc)(u8_t rid, struct obj_def *od);
+  void (*set_value_pc)(u8_t rid, struct obj_def *od);
+};
+
+/** export MIB tree from mib2.c */
+extern const struct mib_array_node internet;
+
+/** dummy function pointers for non-leaf MIB nodes from mib2.c */
+void noleafs_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+void noleafs_get_value(struct obj_def *od, u16_t len, void *value);
+u8_t noleafs_set_test(struct obj_def *od, u16_t len, void *value);
+void noleafs_set_value(struct obj_def *od, u16_t len, void *value);
+
+void snmp_oidtoip(s32_t *ident, struct ip_addr *ip);
+void snmp_iptooid(struct ip_addr *ip, s32_t *ident);
+void snmp_ifindextonetif(s32_t ifindex, struct netif **netif);
+void snmp_netiftoifindex(struct netif *netif, s32_t *ifidx);
+
+struct mib_list_node* snmp_mib_ln_alloc(s32_t id);
+void snmp_mib_ln_free(struct mib_list_node *ln);
+struct mib_list_rootnode* snmp_mib_lrn_alloc(void);
+void snmp_mib_lrn_free(struct mib_list_rootnode *lrn);
+
+s8_t snmp_mib_node_insert(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **insn);
+s8_t snmp_mib_node_find(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **fn);
+struct mib_list_rootnode *snmp_mib_node_delete(struct mib_list_rootnode *rn, struct mib_list_node *n);
+
+struct mib_node* snmp_search_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_name_ptr *np);
+struct mib_node* snmp_expand_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret);
+u8_t snmp_iso_prefix_tst(u8_t ident_len, s32_t *ident);
+u8_t snmp_iso_prefix_expand(u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_SNMP */
+
+#endif /* __LWIP_SNMP_STRUCTS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/sockets.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/sockets.h
new file mode 100644
index 0000000..aa3e65c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/sockets.h
@@ -0,0 +1,337 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+#ifndef __LWIP_SOCKETS_H__
+#define __LWIP_SOCKETS_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/ip_addr.h"
+#include "lwip/inet.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* members are in network byte order */
+struct sockaddr_in {
+  u8_t sin_len;
+  u8_t sin_family;
+  u16_t sin_port;
+  struct in_addr sin_addr;
+  char sin_zero[8];
+};
+
+struct sockaddr {
+  u8_t sa_len;
+  u8_t sa_family;
+  char sa_data[14];
+};
+
+#ifndef socklen_t
+#  define socklen_t u32_t
+#endif
+
+/* Socket protocol types (TCP/UDP/RAW) */
+#define SOCK_STREAM     1
+#define SOCK_DGRAM      2
+#define SOCK_RAW        3
+
+/*
+ * Option flags per-socket. These must match the SOF_ flags in ip.h!
+ */
+#define  SO_DEBUG       0x0001 /* Unimplemented: turn on debugging info recording */
+#define  SO_ACCEPTCONN  0x0002 /* socket has had listen() */
+#define  SO_REUSEADDR   0x0004 /* Unimplemented: allow local address reuse */
+#define  SO_KEEPALIVE   0x0008 /* keep connections alive */
+#define  SO_DONTROUTE   0x0010 /* Unimplemented: just use interface addresses */
+#define  SO_BROADCAST   0x0020 /* Unimplemented: permit sending of broadcast msgs */
+#define  SO_USELOOPBACK 0x0040 /* Unimplemented: bypass hardware when possible */
+#define  SO_LINGER      0x0080 /* linger on close if data present */
+#define  SO_OOBINLINE   0x0100 /* Unimplemented: leave received OOB data in line */
+#define  SO_REUSEPORT   0x0200 /* Unimplemented: allow local address & port reuse */
+
+#define SO_DONTLINGER   ((int)(~SO_LINGER))
+
+/*
+ * Additional options, not kept in so_options.
+ */
+#define SO_SNDBUF    0x1001    /* Unimplemented: send buffer size */
+#define SO_RCVBUF    0x1002    /* receive buffer size */
+#define SO_SNDLOWAT  0x1003    /* Unimplemented: send low-water mark */
+#define SO_RCVLOWAT  0x1004    /* Unimplemented: receive low-water mark */
+#define SO_SNDTIMEO  0x1005    /* Unimplemented: send timeout */
+#define SO_RCVTIMEO  0x1006    /* receive timeout */
+#define SO_ERROR     0x1007    /* get error status and clear */
+#define SO_TYPE      0x1008    /* get socket type */
+#define SO_CONTIMEO  0x1009    /* Unimplemented: connect timeout */
+#define SO_NO_CHECK  0x100a    /* don't create UDP checksum */
+
+
+/*
+ * Structure used for manipulating linger option.
+ */
+struct linger {
+       int l_onoff;                /* option on/off */
+       int l_linger;               /* linger time */
+};
+
+/*
+ * Level number for (get/set)sockopt() to apply to socket itself.
+ */
+#define  SOL_SOCKET  0xfff    /* options for socket level */
+
+
+#define AF_UNSPEC       0
+#define AF_INET         2
+#define PF_INET         AF_INET
+#define PF_UNSPEC       AF_UNSPEC
+
+#define IPPROTO_IP      0
+#define IPPROTO_TCP     6
+#define IPPROTO_UDP     17
+#define IPPROTO_UDPLITE 136
+
+#define INADDR_ANY       0
+#define INADDR_BROADCAST 0xffffffff
+
+/* Flags we can use with send and recv. */
+#define MSG_PEEK       0x01    /* Peeks at an incoming message */
+#define MSG_WAITALL    0x02    /* Unimplemented: Requests that the function block until the full amount of data requested can be returned */
+#define MSG_OOB        0x04    /* Unimplemented: Requests out-of-band data. The significance and semantics of out-of-band data are protocol-specific */
+#define MSG_DONTWAIT   0x08    /* Nonblocking i/o for this operation only */
+#define MSG_MORE       0x10    /* Sender will send more */
+
+
+/*
+ * Options for level IPPROTO_IP
+ */
+#define IP_TOS             1
+#define IP_TTL             2
+
+#if LWIP_TCP
+/*
+ * Options for level IPPROTO_TCP
+ */
+#define TCP_NODELAY    0x01    /* don't delay send to coalesce packets */
+#define TCP_KEEPALIVE  0x02    /* send KEEPALIVE probes when idle for pcb->keep_idle milliseconds */
+#define TCP_KEEPIDLE   0x03    /* set pcb->keep_idle  - Same as TCP_KEEPALIVE, but use seconds for get/setsockopt */
+#define TCP_KEEPINTVL  0x04    /* set pcb->keep_intvl - Use seconds for get/setsockopt */
+#define TCP_KEEPCNT    0x05    /* set pcb->keep_cnt   - Use number of probes sent for get/setsockopt */
+#endif /* LWIP_TCP */
+
+#if LWIP_UDP && LWIP_UDPLITE
+/*
+ * Options for level IPPROTO_UDPLITE
+ */
+#define UDPLITE_SEND_CSCOV 0x01 /* sender checksum coverage */
+#define UDPLITE_RECV_CSCOV 0x02 /* minimal receiver checksum coverage */
+#endif /* LWIP_UDP && LWIP_UDPLITE*/
+
+
+#if LWIP_IGMP
+/*
+ * Options and types for UDP multicast traffic handling
+ */
+#define IP_ADD_MEMBERSHIP  3
+#define IP_DROP_MEMBERSHIP 4
+#define IP_MULTICAST_TTL   5
+#define IP_MULTICAST_IF    6
+#define IP_MULTICAST_LOOP  7
+
+typedef struct ip_mreq {
+    struct in_addr imr_multiaddr; /* IP multicast address of group */
+    struct in_addr imr_interface; /* local IP address of interface */
+} ip_mreq;
+#endif /* LWIP_IGMP */
+
+/* Unimplemented for now... */
+#define IPTOS_TOS_MASK          0x1E
+#define IPTOS_TOS(tos)          ((tos) & IPTOS_TOS_MASK)
+#define IPTOS_LOWDELAY          0x10
+#define IPTOS_THROUGHPUT        0x08
+#define IPTOS_RELIABILITY       0x04
+#define IPTOS_LOWCOST           0x02
+#define IPTOS_MINCOST           IPTOS_LOWCOST
+
+/*
+ * Definitions for IP precedence (also in ip_tos) (Unimplemented)
+ */
+#define IPTOS_PREC_MASK                 0xe0
+#define IPTOS_PREC(tos)                ((tos) & IPTOS_PREC_MASK)
+#define IPTOS_PREC_NETCONTROL           0xe0
+#define IPTOS_PREC_INTERNETCONTROL      0xc0
+#define IPTOS_PREC_CRITIC_ECP           0xa0
+#define IPTOS_PREC_FLASHOVERRIDE        0x80
+#define IPTOS_PREC_FLASH                0x60
+#define IPTOS_PREC_IMMEDIATE            0x40
+#define IPTOS_PREC_PRIORITY             0x20
+#define IPTOS_PREC_ROUTINE              0x00
+
+
+/*
+ * Commands for ioctlsocket(),  taken from the BSD file fcntl.h.
+ * lwip_ioctl only supports FIONREAD and FIONBIO, for now
+ *
+ * Ioctl's have the command encoded in the lower word,
+ * and the size of any in or out parameters in the upper
+ * word.  The high 2 bits of the upper word are used
+ * to encode the in/out status of the parameter; for now
+ * we restrict parameters to at most 128 bytes.
+ */
+#if !defined(FIONREAD) || !defined(FIONBIO)
+#define IOCPARM_MASK    0x7fU           /* parameters must be < 128 bytes */
+#define IOC_VOID        0x20000000UL    /* no parameters */
+#define IOC_OUT         0x40000000UL    /* copy out parameters */
+#define IOC_IN          0x80000000UL    /* copy in parameters */
+#define IOC_INOUT       (IOC_IN|IOC_OUT)
+                                        /* 0x20000000 distinguishes new &
+                                           old ioctl's */
+#define _IO(x,y)        (IOC_VOID|((x)<<8)|(y))
+
+#define _IOR(x,y,t)     (IOC_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
+
+#define _IOW(x,y,t)     (IOC_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
+#endif /* !defined(FIONREAD) || !defined(FIONBIO) */
+
+#ifndef FIONREAD
+#define FIONREAD    _IOR('f', 127, unsigned long) /* get # bytes to read */
+#endif
+#ifndef FIONBIO
+#define FIONBIO     _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */
+#endif
+
+/* Socket I/O Controls: unimplemented */
+#ifndef SIOCSHIWAT
+#define SIOCSHIWAT  _IOW('s',  0, unsigned long)  /* set high watermark */
+#define SIOCGHIWAT  _IOR('s',  1, unsigned long)  /* get high watermark */
+#define SIOCSLOWAT  _IOW('s',  2, unsigned long)  /* set low watermark */
+#define SIOCGLOWAT  _IOR('s',  3, unsigned long)  /* get low watermark */
+#define SIOCATMARK  _IOR('s',  7, unsigned long)  /* at oob mark? */
+#endif
+
+/* Socket flags: */
+#ifndef O_NONBLOCK
+#define O_NONBLOCK    04000U
+#endif
+
+/* FD_SET used for lwip_select */
+#ifndef FD_SET
+  #undef  FD_SETSIZE
+  /* Make FD_SETSIZE match NUM_SOCKETS in socket.c */
+  #define FD_SETSIZE    MEMP_NUM_NETCONN
+  #define FD_SET(n, p)  ((p)->fd_bits[(n)/8] |=  (1 << ((n) & 7)))
+  #define FD_CLR(n, p)  ((p)->fd_bits[(n)/8] &= ~(1 << ((n) & 7)))
+  #define FD_ISSET(n,p) ((p)->fd_bits[(n)/8] &   (1 << ((n) & 7)))
+  #define FD_ZERO(p)    memset((void*)(p),0,sizeof(*(p)))
+
+  typedef struct fd_set {
+          unsigned char fd_bits [(FD_SETSIZE+7)/8];
+        } fd_set;
+
+#endif /* FD_SET */
+
+/** LWIP_TIMEVAL_PRIVATE: if you want to use the struct timeval provided
+ * by your system, set this to 0 and include  in cc.h */
+#ifndef LWIP_TIMEVAL_PRIVATE
+#define LWIP_TIMEVAL_PRIVATE 1
+#endif
+
+#if LWIP_TIMEVAL_PRIVATE
+struct timeval {
+  long    tv_sec;         /* seconds */
+  long    tv_usec;        /* and microseconds */
+};
+#endif /* LWIP_TIMEVAL_PRIVATE */
+
+void lwip_socket_init(void);
+
+int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen);
+int lwip_bind(int s, struct sockaddr *name, socklen_t namelen);
+int lwip_shutdown(int s, int how);
+int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen);
+int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen);
+int lwip_close(int s);
+int lwip_connect(int s, const struct sockaddr *name, socklen_t namelen);
+int lwip_listen(int s, int backlog);
+int lwip_recv(int s, void *mem, int len, unsigned int flags);
+int lwip_read(int s, void *mem, int len);
+int lwip_recvfrom(int s, void *mem, int len, unsigned int flags,
+      struct sockaddr *from, socklen_t *fromlen);
+int lwip_send(int s, const void *dataptr, int size, unsigned int flags);
+int lwip_sendto(int s, const void *dataptr, int size, unsigned int flags,
+    struct sockaddr *to, socklen_t tolen);
+int lwip_socket(int domain, int type, int protocol);
+int lwip_write(int s, const void *dataptr, int size);
+int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
+                struct timeval *timeout);
+int lwip_ioctl(int s, long cmd, void *argp);
+
+#if LWIP_COMPAT_SOCKETS
+#define accept(a,b,c)         lwip_accept(a,b,c)
+#define bind(a,b,c)           lwip_bind(a,b,c)
+#define shutdown(a,b)         lwip_shutdown(a,b)
+#define closesocket(s)        lwip_close(s)
+#define connect(a,b,c)        lwip_connect(a,b,c)
+#define getsockname(a,b,c)    lwip_getsockname(a,b,c)
+#define getpeername(a,b,c)    lwip_getpeername(a,b,c)
+#define setsockopt(a,b,c,d,e) lwip_setsockopt(a,b,c,d,e)
+#define getsockopt(a,b,c,d,e) lwip_getsockopt(a,b,c,d,e)
+#define listen(a,b)           lwip_listen(a,b)
+#define recv(a,b,c,d)         lwip_recv(a,b,c,d)
+#define recvfrom(a,b,c,d,e,f) lwip_recvfrom(a,b,c,d,e,f)
+#define send(a,b,c,d)         lwip_send(a,b,c,d)
+#define sendto(a,b,c,d,e,f)   lwip_sendto(a,b,c,d,e,f)
+#define socket(a,b,c)         lwip_socket(a,b,c)
+#define select(a,b,c,d,e)     lwip_select(a,b,c,d,e)
+#define ioctlsocket(a,b,c)    lwip_ioctl(a,b,c)
+
+#if LWIP_POSIX_SOCKETS_IO_NAMES
+#define read(a,b,c)           lwip_read(a,b,c)
+#define write(a,b,c)          lwip_write(a,b,c)
+#define close(s)              lwip_close(s)
+#endif /* LWIP_POSIX_SOCKETS_IO_NAMES */
+
+#endif /* LWIP_COMPAT_SOCKETS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_SOCKET */
+
+#endif /* __LWIP_SOCKETS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/stats.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/stats.h
new file mode 100644
index 0000000..aebf490
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/stats.h
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_STATS_H__
+#define __LWIP_STATS_H__
+
+#include "lwip/opt.h"
+
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_STATS
+
+#ifndef LWIP_STATS_LARGE
+#define LWIP_STATS_LARGE 0
+#endif
+
+#if LWIP_STATS_LARGE
+#define STAT_COUNTER     u32_t
+#define STAT_COUNTER_F   U32_F
+#else
+#define STAT_COUNTER     u16_t
+#define STAT_COUNTER_F   U16_F
+#endif
+
+struct stats_proto {
+  STAT_COUNTER xmit;             /* Transmitted packets. */
+  STAT_COUNTER rexmit;           /* Retransmitted packets. */
+  STAT_COUNTER recv;             /* Received packets. */
+  STAT_COUNTER fw;               /* Forwarded packets. */
+  STAT_COUNTER drop;             /* Dropped packets. */
+  STAT_COUNTER chkerr;           /* Checksum error. */
+  STAT_COUNTER lenerr;           /* Invalid length error. */
+  STAT_COUNTER memerr;           /* Out of memory error. */
+  STAT_COUNTER rterr;            /* Routing error. */
+  STAT_COUNTER proterr;          /* Protocol error. */
+  STAT_COUNTER opterr;           /* Error in options. */
+  STAT_COUNTER err;              /* Misc error. */
+  STAT_COUNTER cachehit;
+};
+
+struct stats_igmp {
+  STAT_COUNTER lenerr;           /* Invalid length error. */
+  STAT_COUNTER chkerr;           /* Checksum error. */
+  STAT_COUNTER v1_rxed;          /* */
+  STAT_COUNTER join_sent;        /* */
+  STAT_COUNTER leave_sent;       /* */
+  STAT_COUNTER unicast_query;    /* */
+  STAT_COUNTER report_sent;      /* */
+  STAT_COUNTER report_rxed;      /* */
+  STAT_COUNTER group_query_rxed; /* */
+};
+
+struct stats_mem {
+  mem_size_t avail;
+  mem_size_t used;
+  mem_size_t max;
+  mem_size_t err;
+};
+
+struct stats_syselem {
+  STAT_COUNTER used;
+  STAT_COUNTER max;
+  STAT_COUNTER err;
+};
+
+struct stats_sys {
+  struct stats_syselem sem;
+  struct stats_syselem mbox;
+};
+
+struct stats_ {
+#if LINK_STATS
+  struct stats_proto link;
+#endif
+#if ETHARP_STATS
+  struct stats_proto etharp;
+#endif
+#if IPFRAG_STATS
+  struct stats_proto ip_frag;
+#endif
+#if IP_STATS
+  struct stats_proto ip;
+#endif
+#if ICMP_STATS
+  struct stats_proto icmp;
+#endif
+#if IGMP_STATS
+  struct stats_igmp igmp;
+#endif
+#if UDP_STATS
+  struct stats_proto udp;
+#endif
+#if TCP_STATS
+  struct stats_proto tcp;
+#endif
+#if MEM_STATS
+  struct stats_mem mem;
+#endif
+#if MEMP_STATS
+  struct stats_mem memp[MEMP_MAX];
+#endif
+#if SYS_STATS
+  struct stats_sys sys;
+#endif
+};
+
+extern struct stats_ lwip_stats;
+
+#define stats_init() /* Compatibility define, not init needed. */
+
+#define STATS_INC(x) ++lwip_stats.x
+#else
+#define stats_init()
+#define STATS_INC(x)
+#endif /* LWIP_STATS */
+
+#if TCP_STATS
+#define TCP_STATS_INC(x) STATS_INC(x)
+#else
+#define TCP_STATS_INC(x)
+#endif
+
+#if UDP_STATS
+#define UDP_STATS_INC(x) STATS_INC(x)
+#else
+#define UDP_STATS_INC(x)
+#endif
+
+#if ICMP_STATS
+#define ICMP_STATS_INC(x) STATS_INC(x)
+#else
+#define ICMP_STATS_INC(x)
+#endif
+
+#if IGMP_STATS
+#define IGMP_STATS_INC(x) STATS_INC(x)
+#else
+#define IGMP_STATS_INC(x)
+#endif
+
+#if IP_STATS
+#define IP_STATS_INC(x) STATS_INC(x)
+#else
+#define IP_STATS_INC(x)
+#endif
+
+#if IPFRAG_STATS
+#define IPFRAG_STATS_INC(x) STATS_INC(x)
+#else
+#define IPFRAG_STATS_INC(x)
+#endif
+
+#if ETHARP_STATS
+#define ETHARP_STATS_INC(x) STATS_INC(x)
+#else
+#define ETHARP_STATS_INC(x)
+#endif
+
+#if LINK_STATS
+#define LINK_STATS_INC(x) STATS_INC(x)
+#else
+#define LINK_STATS_INC(x)
+#endif
+
+/* Display of statistics */
+#if LWIP_STATS_DISPLAY
+void stats_display(void);
+#else
+#define stats_display()
+#endif /* LWIP_STATS_DISPLAY */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_STATS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/sys.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/sys.h
new file mode 100644
index 0000000..f713f1e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/sys.h
@@ -0,0 +1,246 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_SYS_H__
+#define __LWIP_SYS_H__
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if NO_SYS
+
+/* For a totally minimal and standalone system, we provide null
+   definitions of the sys_ functions. */
+typedef u8_t sys_sem_t;
+typedef u8_t sys_mbox_t;
+typedef u8_t sys_prot_t;
+struct sys_timeo {u8_t dummy;};
+
+#define sys_init()
+#define sys_timeout(m,h,a)
+#define sys_untimeout(m,a)
+#define sys_sem_new(c) c
+#define sys_sem_signal(s)
+#define sys_sem_wait(s)
+#define sys_sem_wait_timeout(s,t)
+#define sys_arch_sem_wait(s,t)
+#define sys_sem_free(s)
+#define sys_mbox_new(s) 0
+#define sys_mbox_fetch(m,d)
+#define sys_mbox_tryfetch(m,d)
+#define sys_mbox_post(m,d)
+#define sys_mbox_trypost(m,d)
+#define sys_mbox_free(m)
+
+#define sys_thread_new(n,t,a,s,p)
+
+#else /* NO_SYS */
+
+/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */
+#define SYS_ARCH_TIMEOUT 0xffffffffUL
+
+/* sys_mbox_tryfetch returns SYS_MBOX_EMPTY if appropriate.
+ * For now we use the same magic value, but we allow this to change in future.
+ */
+#define SYS_MBOX_EMPTY SYS_ARCH_TIMEOUT
+
+#include "lwip/err.h"
+#include "arch/sys_arch.h"
+
+typedef void (* sys_timeout_handler)(void *arg);
+
+struct sys_timeo {
+  struct sys_timeo *next;
+  u32_t time;
+  sys_timeout_handler h;
+  void *arg;
+};
+
+struct sys_timeouts {
+  struct sys_timeo *next;
+};
+
+/* sys_init() must be called before anthing else. */
+void sys_init(void);
+
+/*
+ * sys_timeout():
+ *
+ * Schedule a timeout a specified amount of milliseconds in the
+ * future. When the timeout occurs, the specified timeout handler will
+ * be called. The handler will be passed the "arg" argument when
+ * called.
+ *
+ */
+void sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg);
+void sys_untimeout(sys_timeout_handler h, void *arg);
+struct sys_timeouts *sys_arch_timeouts(void);
+
+/* Semaphore functions. */
+sys_sem_t sys_sem_new(u8_t count);
+void sys_sem_signal(sys_sem_t sem);
+u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout);
+void sys_sem_free(sys_sem_t sem);
+void sys_sem_wait(sys_sem_t sem);
+int sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout);
+
+/* Time functions. */
+#ifndef sys_msleep
+void sys_msleep(u32_t ms); /* only has a (close to) 1 jiffy resolution. */
+#endif
+#ifndef sys_jiffies
+u32_t sys_jiffies(void); /* since power up. */
+#endif
+
+/* Mailbox functions. */
+sys_mbox_t sys_mbox_new(int size);
+void sys_mbox_post(sys_mbox_t mbox, void *msg);
+err_t sys_mbox_trypost(sys_mbox_t mbox, void *msg);
+u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout);
+#ifndef sys_arch_mbox_tryfetch /* Allow port to override with a macro */
+u32_t sys_arch_mbox_tryfetch(sys_mbox_t mbox, void **msg);
+#endif
+/* For now, we map straight to sys_arch implementation. */
+#define sys_mbox_tryfetch(mbox, msg) sys_arch_mbox_tryfetch(mbox, msg)
+void sys_mbox_free(sys_mbox_t mbox);
+void sys_mbox_fetch(sys_mbox_t mbox, void **msg);
+
+/* Thread functions. */
+sys_thread_t sys_thread_new(char *name, void (* thread)(void *arg), void *arg, int stacksize, int prio);
+
+/* The following functions are used only in Unix code, and
+   can be omitted when porting the stack. */
+/* Returns the current time in microseconds. */
+unsigned long sys_now(void);
+
+#endif /* NO_SYS */
+
+/* Critical Region Protection */
+/* These functions must be implemented in the sys_arch.c file.
+   In some implementations they can provide a more light-weight protection
+   mechanism than using semaphores. Otherwise semaphores can be used for
+   implementation */
+#ifndef SYS_ARCH_PROTECT
+/** SYS_LIGHTWEIGHT_PROT
+ * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
+ * for certain critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#if SYS_LIGHTWEIGHT_PROT
+
+/** SYS_ARCH_DECL_PROTECT
+ * declare a protection variable. This macro will default to defining a variable of
+ * type sys_prot_t. If a particular port needs a different implementation, then
+ * this macro may be defined in sys_arch.h.
+ */
+#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev
+/** SYS_ARCH_PROTECT
+ * Perform a "fast" protect. This could be implemented by
+ * disabling interrupts for an embedded system or by using a semaphore or
+ * mutex. The implementation should allow calling SYS_ARCH_PROTECT when
+ * already protected. The old protection level is returned in the variable
+ * "lev". This macro will default to calling the sys_arch_protect() function
+ * which should be implemented in sys_arch.c. If a particular port needs a
+ * different implementation, then this macro may be defined in sys_arch.h
+ */
+#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect()
+/** SYS_ARCH_UNPROTECT
+ * Perform a "fast" set of the protection level to "lev". This could be
+ * implemented by setting the interrupt level to "lev" within the MACRO or by
+ * using a semaphore or mutex.  This macro will default to calling the
+ * sys_arch_unprotect() function which should be implemented in
+ * sys_arch.c. If a particular port needs a different implementation, then
+ * this macro may be defined in sys_arch.h
+ */
+#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev)
+sys_prot_t sys_arch_protect(void);
+void sys_arch_unprotect(sys_prot_t pval);
+
+#else
+
+#define SYS_ARCH_DECL_PROTECT(lev)
+#define SYS_ARCH_PROTECT(lev)
+#define SYS_ARCH_UNPROTECT(lev)
+
+#endif /* SYS_LIGHTWEIGHT_PROT */
+
+#endif /* SYS_ARCH_PROTECT */
+
+/*
+ * Macros to set/get and increase/decrease variables in a thread-safe way.
+ * Use these for accessing variable that are used from more than one thread.
+ */
+
+#ifndef SYS_ARCH_INC
+#define SYS_ARCH_INC(var, val) do { \
+                                SYS_ARCH_DECL_PROTECT(old_level); \
+                                SYS_ARCH_PROTECT(old_level); \
+                                var += val; \
+                                SYS_ARCH_UNPROTECT(old_level); \
+                              } while(0)
+#endif /* SYS_ARCH_INC */
+
+#ifndef SYS_ARCH_DEC
+#define SYS_ARCH_DEC(var, val) do { \
+                                SYS_ARCH_DECL_PROTECT(old_level); \
+                                SYS_ARCH_PROTECT(old_level); \
+                                var -= val; \
+                                SYS_ARCH_UNPROTECT(old_level); \
+                              } while(0)
+#endif /* SYS_ARCH_DEC */
+
+#ifndef SYS_ARCH_GET
+#define SYS_ARCH_GET(var, ret) do { \
+                                SYS_ARCH_DECL_PROTECT(old_level); \
+                                SYS_ARCH_PROTECT(old_level); \
+                                ret = var; \
+                                SYS_ARCH_UNPROTECT(old_level); \
+                              } while(0)
+#endif /* SYS_ARCH_GET */
+
+#ifndef SYS_ARCH_SET
+#define SYS_ARCH_SET(var, val) do { \
+                                SYS_ARCH_DECL_PROTECT(old_level); \
+                                SYS_ARCH_PROTECT(old_level); \
+                                var = val; \
+                                SYS_ARCH_UNPROTECT(old_level); \
+                              } while(0)
+#endif /* SYS_ARCH_SET */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_SYS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/tcp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/tcp.h
new file mode 100644
index 0000000..9912be0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/tcp.h
@@ -0,0 +1,644 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_TCP_H__
+#define __LWIP_TCP_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip.h"
+#include "lwip/icmp.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct tcp_pcb;
+
+/* Functions for interfacing with TCP: */
+
+/* Lower layer interface to TCP: */
+#define tcp_init() /* Compatibility define, not init needed. */
+void             tcp_tmr     (void);  /* Must be called every
+                                         TCP_TMR_INTERVAL
+                                         ms. (Typically 250 ms). */
+/* Application program's interface: */
+struct tcp_pcb * tcp_new     (void);
+struct tcp_pcb * tcp_alloc   (u8_t prio);
+
+void             tcp_arg     (struct tcp_pcb *pcb, void *arg);
+void             tcp_accept  (struct tcp_pcb *pcb,
+                              err_t (* accept)(void *arg, struct tcp_pcb *newpcb,
+                 err_t err));
+void             tcp_recv    (struct tcp_pcb *pcb,
+                              err_t (* recv)(void *arg, struct tcp_pcb *tpcb,
+                              struct pbuf *p, err_t err));
+void             tcp_sent    (struct tcp_pcb *pcb,
+                              err_t (* sent)(void *arg, struct tcp_pcb *tpcb,
+                              u16_t len));
+void             tcp_poll    (struct tcp_pcb *pcb,
+                              err_t (* poll)(void *arg, struct tcp_pcb *tpcb),
+                              u8_t interval);
+void             tcp_err     (struct tcp_pcb *pcb,
+                              void (* err)(void *arg, err_t err));
+
+#define          tcp_mss(pcb)      ((pcb)->mss)
+#define          tcp_sndbuf(pcb)   ((pcb)->snd_buf)
+
+#if TCP_LISTEN_BACKLOG
+#define          tcp_accepted(pcb) (((struct tcp_pcb_listen *)(pcb))->accepts_pending--)
+#else  /* TCP_LISTEN_BACKLOG */
+#define          tcp_accepted(pcb)
+#endif /* TCP_LISTEN_BACKLOG */
+
+void             tcp_recved  (struct tcp_pcb *pcb, u16_t len);
+err_t            tcp_bind    (struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+                              u16_t port);
+err_t            tcp_connect (struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+                              u16_t port, err_t (* connected)(void *arg,
+                              struct tcp_pcb *tpcb,
+                              err_t err));
+
+struct tcp_pcb * tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog);
+#define          tcp_listen(pcb) tcp_listen_with_backlog(pcb, TCP_DEFAULT_LISTEN_BACKLOG)
+
+void             tcp_abort   (struct tcp_pcb *pcb);
+err_t            tcp_close   (struct tcp_pcb *pcb);
+
+/* Flags for "apiflags" parameter in tcp_write and tcp_enqueue */
+#define TCP_WRITE_FLAG_COPY 0x01
+#define TCP_WRITE_FLAG_MORE 0x02
+
+err_t            tcp_write   (struct tcp_pcb *pcb, const void *dataptr, u16_t len,
+                              u8_t apiflags);
+
+void             tcp_setprio (struct tcp_pcb *pcb, u8_t prio);
+
+#define TCP_PRIO_MIN    1
+#define TCP_PRIO_NORMAL 64
+#define TCP_PRIO_MAX    127
+
+/* It is also possible to call these two functions at the right
+   intervals (instead of calling tcp_tmr()). */
+void             tcp_slowtmr (void);
+void             tcp_fasttmr (void);
+
+
+/* Only used by IP to pass a TCP segment to TCP: */
+void             tcp_input   (struct pbuf *p, struct netif *inp);
+/* Used within the TCP code only: */
+err_t            tcp_output  (struct tcp_pcb *pcb);
+void             tcp_rexmit  (struct tcp_pcb *pcb);
+void             tcp_rexmit_rto  (struct tcp_pcb *pcb);
+
+/**
+ * This is the Nagle algorithm: inhibit the sending of new TCP
+ * segments when new outgoing data arrives from the user if any
+ * previously transmitted data on the connection remains
+ * unacknowledged.
+ */
+#define tcp_do_output_nagle(tpcb) ((((tpcb)->unacked == NULL) || \
+                            ((tpcb)->flags & TF_NODELAY) || \
+                            (((tpcb)->unsent != NULL) && ((tpcb)->unsent->next != NULL))) ? \
+                                1 : 0)
+#define tcp_output_nagle(tpcb) (tcp_do_output_nagle(tpcb) ? tcp_output(tpcb) : ERR_OK)
+
+
+/** This returns a TCP header option for MSS in an u32_t */
+#define TCP_BUILD_MSS_OPTION()  htonl(((u32_t)2 << 24) | \
+                                ((u32_t)4 << 16) | \
+                                (((u32_t)TCP_MSS / 256) << 8) | \
+                                (TCP_MSS & 255))
+
+#define TCP_SEQ_LT(a,b)     ((s32_t)((a)-(b)) < 0)
+#define TCP_SEQ_LEQ(a,b)    ((s32_t)((a)-(b)) <= 0)
+#define TCP_SEQ_GT(a,b)     ((s32_t)((a)-(b)) > 0)
+#define TCP_SEQ_GEQ(a,b)    ((s32_t)((a)-(b)) >= 0)
+/* is b<=a<=c? */
+#if 0 /* see bug #10548 */
+#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b))
+#endif
+#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c))
+#define TCP_FIN 0x01U
+#define TCP_SYN 0x02U
+#define TCP_RST 0x04U
+#define TCP_PSH 0x08U
+#define TCP_ACK 0x10U
+#define TCP_URG 0x20U
+#define TCP_ECE 0x40U
+#define TCP_CWR 0x80U
+
+#define TCP_FLAGS 0x3fU
+
+/* Length of the TCP header, excluding options. */
+#define TCP_HLEN 20
+
+#ifndef TCP_TMR_INTERVAL
+#define TCP_TMR_INTERVAL       250  /* The TCP timer interval in milliseconds. */
+#endif /* TCP_TMR_INTERVAL */
+
+#ifndef TCP_FAST_INTERVAL
+#define TCP_FAST_INTERVAL      TCP_TMR_INTERVAL /* the fine grained timeout in milliseconds */
+#endif /* TCP_FAST_INTERVAL */
+
+#ifndef TCP_SLOW_INTERVAL
+#define TCP_SLOW_INTERVAL      (2*TCP_TMR_INTERVAL)  /* the coarse grained timeout in milliseconds */
+#endif /* TCP_SLOW_INTERVAL */
+
+#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */
+#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */
+
+#define TCP_OOSEQ_TIMEOUT        6U /* x RTO */
+
+#ifndef TCP_MSL
+#define TCP_MSL 60000U /* The maximum segment lifetime in milliseconds */
+#endif
+
+/* Keepalive values, compliant with RFC 1122. Don't change this unless you know what you're doing */
+#ifndef  TCP_KEEPIDLE_DEFAULT
+#define  TCP_KEEPIDLE_DEFAULT     7200000UL /* Default KEEPALIVE timer in milliseconds */
+#endif
+
+#ifndef  TCP_KEEPINTVL_DEFAULT
+#define  TCP_KEEPINTVL_DEFAULT    75000UL   /* Default Time between KEEPALIVE probes in milliseconds */
+#endif
+
+#ifndef  TCP_KEEPCNT_DEFAULT
+#define  TCP_KEEPCNT_DEFAULT      9U        /* Default Counter for KEEPALIVE probes */
+#endif
+
+#define  TCP_MAXIDLE              TCP_KEEPCNT_DEFAULT * TCP_KEEPINTVL_DEFAULT  /* Maximum KEEPALIVE probe time */
+
+/* Fields are (of course) in network byte order.
+ * Some fields are converted to host byte order in tcp_input().
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+#if (defined(__MWERKS__)  || defined(__CWCC__))
+	#pragma options align= packed
+#endif
+struct tcp_hdr {
+  PACK_STRUCT_FIELD(u16_t src);
+  PACK_STRUCT_FIELD(u16_t dest);
+  PACK_STRUCT_FIELD(u32_t seqno);
+  PACK_STRUCT_FIELD(u32_t ackno);
+  PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags);
+  PACK_STRUCT_FIELD(u16_t wnd);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u16_t urgp);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define TCPH_OFFSET(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 8)
+#define TCPH_HDRLEN(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 12)
+#define TCPH_FLAGS(phdr)  (ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS)
+
+#define TCPH_OFFSET_SET(phdr, offset) (phdr)->_hdrlen_rsvd_flags = htons(((offset) << 8) | TCPH_FLAGS(phdr))
+#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | TCPH_FLAGS(phdr))
+#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons((ntohs((phdr)->_hdrlen_rsvd_flags) & ~TCP_FLAGS) | (flags))
+#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (flags))
+#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (TCPH_FLAGS(phdr) & ~(flags)) )
+
+#define TCP_TCPLEN(seg) ((seg)->len + ((TCPH_FLAGS((seg)->tcphdr) & TCP_FIN || \
+          TCPH_FLAGS((seg)->tcphdr) & TCP_SYN)? 1: 0))
+
+enum tcp_state {
+  CLOSED      = 0,
+  LISTEN      = 1,
+  SYN_SENT    = 2,
+  SYN_RCVD    = 3,
+  ESTABLISHED = 4,
+  FIN_WAIT_1  = 5,
+  FIN_WAIT_2  = 6,
+  CLOSE_WAIT  = 7,
+  CLOSING     = 8,
+  LAST_ACK    = 9,
+  TIME_WAIT   = 10
+};
+
+/** Flags used on input processing, not on pcb->flags
+*/
+#define TF_RESET     (u8_t)0x08U   /* Connection was reset. */
+#define TF_CLOSED    (u8_t)0x10U   /* Connection was sucessfully closed. */
+#define TF_GOT_FIN   (u8_t)0x20U   /* Connection was closed by the remote end. */
+
+/**
+ * members common to struct tcp_pcb and struct tcp_listen_pcb
+ */
+#define TCP_PCB_COMMON(type) \
+  type *next; /* for the linked list */ \
+  enum tcp_state state; /* TCP state */ \
+  u8_t prio; \
+  void *callback_arg; \
+  /* ports are in host byte order */ \
+  u16_t local_port
+
+/* the TCP protocol control block */
+struct tcp_pcb {
+/** common PCB members */
+  IP_PCB;
+/** protocol specific PCB members */
+  TCP_PCB_COMMON(struct tcp_pcb);
+
+  /* ports are in host byte order */
+  u16_t remote_port;
+
+  u8_t flags;
+#define TF_ACK_DELAY   (u8_t)0x01U   /* Delayed ACK. */
+#define TF_ACK_NOW     (u8_t)0x02U   /* Immediate ACK. */
+#define TF_INFR        (u8_t)0x04U   /* In fast recovery. */
+#define TF_FIN         (u8_t)0x20U   /* Connection was closed locally (FIN segment enqueued). */
+#define TF_NODELAY     (u8_t)0x40U   /* Disable Nagle algorithm */
+#define TF_NAGLEMEMERR (u8_t)0x80U /* nagle enabled, memerr, try to output to prevent delayed ACK to happen */
+
+  /* the rest of the fields are in host byte order
+     as we have to do some math with them */
+  /* receiver variables */
+  u32_t rcv_nxt;   /* next seqno expected */
+  u16_t rcv_wnd;   /* receiver window */
+  u16_t rcv_ann_wnd; /* announced receive window */
+
+  /* Timers */
+  u32_t tmr;
+  u8_t polltmr, pollinterval;
+
+  /* Retransmission timer. */
+  s16_t rtime;
+
+  u16_t mss;   /* maximum segment size */
+
+  /* RTT (round trip time) estimation variables */
+  u32_t rttest; /* RTT estimate in 500ms ticks */
+  u32_t rtseq;  /* sequence number being timed */
+  s16_t sa, sv; /* @todo document this */
+
+  s16_t rto;    /* retransmission time-out */
+  u8_t nrtx;    /* number of retransmissions */
+
+  /* fast retransmit/recovery */
+  u32_t lastack; /* Highest acknowledged seqno. */
+  u8_t dupacks;
+
+  /* congestion avoidance/control variables */
+  u16_t cwnd;
+  u16_t ssthresh;
+
+  /* sender variables */
+  u32_t snd_nxt,   /* next seqno to be sent */
+    snd_max;       /* Highest seqno sent. */
+  u16_t snd_wnd;   /* sender window */
+  u32_t snd_wl1, snd_wl2, /* Sequence and acknowledgement numbers of last
+                             window update. */
+    snd_lbb;       /* Sequence number of next byte to be buffered. */
+
+  u16_t acked;
+
+  u16_t snd_buf;   /* Available buffer space for sending (in bytes). */
+#define TCP_SNDQUEUELEN_OVERFLOW (0xffff-3)
+  u16_t snd_queuelen; /* Available buffer space for sending (in tcp_segs). */
+
+
+  /* These are ordered by sequence number: */
+  struct tcp_seg *unsent;   /* Unsent (queued) segments. */
+  struct tcp_seg *unacked;  /* Sent but unacknowledged segments. */
+#if TCP_QUEUE_OOSEQ
+  struct tcp_seg *ooseq;    /* Received out of sequence segments. */
+#endif /* TCP_QUEUE_OOSEQ */
+
+  struct pbuf *refused_data; /* Data previously received but not yet taken by upper layer */
+
+#if LWIP_CALLBACK_API
+  /* Function to be called when more send buffer space is available.
+   * @param arg user-supplied argument (tcp_pcb.callback_arg)
+   * @param pcb the tcp_pcb which has send buffer space available
+   * @param space the amount of bytes available
+   * @return ERR_OK: try to send some data by calling tcp_output
+   */
+  err_t (* sent)(void *arg, struct tcp_pcb *pcb, u16_t space);
+
+  /* Function to be called when (in-sequence) data has arrived.
+   * @param arg user-supplied argument (tcp_pcb.callback_arg)
+   * @param pcb the tcp_pcb for which data has arrived
+   * @param p the packet buffer which arrived
+   * @param err an error argument (TODO: that is current always ERR_OK?)
+   * @return ERR_OK: try to send some data by calling tcp_output
+   */
+  err_t (* recv)(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err);
+
+  /* Function to be called when a connection has been set up.
+   * @param arg user-supplied argument (tcp_pcb.callback_arg)
+   * @param pcb the tcp_pcb that now is connected
+   * @param err an error argument (TODO: that is current always ERR_OK?)
+   * @return value is currently ignored
+   */
+  err_t (* connected)(void *arg, struct tcp_pcb *pcb, err_t err);
+
+  /* Function to call when a listener has been connected.
+   * @param arg user-supplied argument (tcp_pcb.callback_arg)
+   * @param pcb a new tcp_pcb that now is connected
+   * @param err an error argument (TODO: that is current always ERR_OK?)
+   * @return ERR_OK: accept the new connection,
+   *                 any other err_t abortsthe new connection
+   */
+  err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err);
+
+  /* Function which is called periodically.
+   * The period can be adjusted in multiples of the TCP slow timer interval
+   * by changing tcp_pcb.polltmr.
+   * @param arg user-supplied argument (tcp_pcb.callback_arg)
+   * @param pcb the tcp_pcb to poll for
+   * @return ERR_OK: try to send some data by calling tcp_output
+   */
+  err_t (* poll)(void *arg, struct tcp_pcb *pcb);
+
+  /* Function to be called whenever a fatal error occurs.
+   * There is no pcb parameter since most of the times, the pcb is
+   * already deallocated (or there is no pcb) when this function is called.
+   * @param arg user-supplied argument (tcp_pcb.callback_arg)
+   * @param err an indication why the error callback is called:
+   *            ERR_ABRT: aborted through tcp_abort or by a TCP timer
+   *            ERR_RST: the connection was reset by the remote host
+   */
+  void (* errf)(void *arg, err_t err);
+#endif /* LWIP_CALLBACK_API */
+
+  /* idle time before KEEPALIVE is sent */
+  u32_t keep_idle;
+#if LWIP_TCP_KEEPALIVE
+  u32_t keep_intvl;
+  u32_t keep_cnt;
+#endif /* LWIP_TCP_KEEPALIVE */
+
+  /* Persist timer counter */
+  u32_t persist_cnt;
+  /* Persist timer back-off */
+  u8_t persist_backoff;
+
+  /* KEEPALIVE counter */
+  u8_t keep_cnt_sent;
+};
+
+struct tcp_pcb_listen {
+/* Common members of all PCB types */
+  IP_PCB;
+/* Protocol specific PCB members */
+  TCP_PCB_COMMON(struct tcp_pcb_listen);
+
+#if LWIP_CALLBACK_API
+  /* Function to call when a listener has been connected.
+   * @param arg user-supplied argument (tcp_pcb.callback_arg)
+   * @param pcb a new tcp_pcb that now is connected
+   * @param err an error argument (TODO: that is current always ERR_OK?)
+   * @return ERR_OK: accept the new connection,
+   *                 any other err_t abortsthe new connection
+   */
+  err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err);
+#endif /* LWIP_CALLBACK_API */
+#if TCP_LISTEN_BACKLOG
+  u8_t backlog;
+  u8_t accepts_pending;
+#endif /* TCP_LISTEN_BACKLOG */
+};
+
+#if LWIP_EVENT_API
+
+enum lwip_event {
+  LWIP_EVENT_ACCEPT,
+  LWIP_EVENT_SENT,
+  LWIP_EVENT_RECV,
+  LWIP_EVENT_CONNECTED,
+  LWIP_EVENT_POLL,
+  LWIP_EVENT_ERR
+};
+
+err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb,
+         enum lwip_event,
+         struct pbuf *p,
+         u16_t size,
+         err_t err);
+
+#define TCP_EVENT_ACCEPT(pcb,err,ret)    ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_ACCEPT, NULL, 0, err)
+#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                   LWIP_EVENT_SENT, NULL, space, ERR_OK)
+#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_RECV, (p), 0, (err))
+#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_CONNECTED, NULL, 0, (err))
+#define TCP_EVENT_POLL(pcb,ret)       ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_POLL, NULL, 0, ERR_OK)
+#define TCP_EVENT_ERR(errf,arg,err)  lwip_tcp_event((arg), NULL, \
+                LWIP_EVENT_ERR, NULL, 0, (err))
+#else /* LWIP_EVENT_API */
+#define TCP_EVENT_ACCEPT(pcb,err,ret)     \
+                        if((pcb)->accept != NULL) \
+                        (ret = (pcb)->accept((pcb)->callback_arg,(pcb),(err)))
+#define TCP_EVENT_SENT(pcb,space,ret) \
+                        if((pcb)->sent != NULL) \
+                        (ret = (pcb)->sent((pcb)->callback_arg,(pcb),(space)))
+#define TCP_EVENT_RECV(pcb,p,err,ret) \
+                        if((pcb)->recv != NULL) \
+                        { ret = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err)); } else { \
+                          ret = ERR_OK; \
+                          if (p) pbuf_free(p); }
+#define TCP_EVENT_CONNECTED(pcb,err,ret) \
+                        if((pcb)->connected != NULL) \
+                        (ret = (pcb)->connected((pcb)->callback_arg,(pcb),(err)))
+#define TCP_EVENT_POLL(pcb,ret) \
+                        if((pcb)->poll != NULL) \
+                        (ret = (pcb)->poll((pcb)->callback_arg,(pcb)))
+#define TCP_EVENT_ERR(errf,arg,err) \
+                        if((errf) != NULL) \
+                        (errf)((arg),(err))
+#endif /* LWIP_EVENT_API */
+
+/* This structure represents a TCP segment on the unsent and unacked queues */
+struct tcp_seg {
+  struct tcp_seg *next;    /* used when putting segements on a queue */
+  struct pbuf *p;          /* buffer containing data + TCP header */
+  void *dataptr;           /* pointer to the TCP data in the pbuf */
+  u16_t len;               /* the TCP length of this segment */
+  struct tcp_hdr *tcphdr;  /* the TCP header */
+};
+
+/* Internal functions and global variables: */
+struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb);
+void tcp_pcb_purge(struct tcp_pcb *pcb);
+void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb);
+
+u8_t tcp_segs_free(struct tcp_seg *seg);
+u8_t tcp_seg_free(struct tcp_seg *seg);
+struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg);
+
+#define tcp_ack(pcb)     if((pcb)->flags & TF_ACK_DELAY) { \
+                            (pcb)->flags &= ~TF_ACK_DELAY; \
+                            (pcb)->flags |= TF_ACK_NOW; \
+                            tcp_output(pcb); \
+                         } else { \
+                            (pcb)->flags |= TF_ACK_DELAY; \
+                         }
+
+#define tcp_ack_now(pcb) (pcb)->flags |= TF_ACK_NOW; \
+                         tcp_output(pcb)
+
+err_t tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags);
+err_t tcp_enqueue(struct tcp_pcb *pcb, void *dataptr, u16_t len,
+    u8_t flags, u8_t apiflags,
+                u8_t *optdata, u8_t optlen);
+
+void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg);
+
+void tcp_rst(u32_t seqno, u32_t ackno,
+       struct ip_addr *local_ip, struct ip_addr *remote_ip,
+       u16_t local_port, u16_t remote_port);
+
+u32_t tcp_next_iss(void);
+
+void tcp_keepalive(struct tcp_pcb *pcb);
+void tcp_zero_window_probe(struct tcp_pcb *pcb);
+
+#if TCP_CALCULATE_EFF_SEND_MSS
+u16_t tcp_eff_send_mss(u16_t sendmss, struct ip_addr *addr);
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+
+extern struct tcp_pcb *tcp_input_pcb;
+extern u32_t tcp_ticks;
+
+#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
+void tcp_debug_print(struct tcp_hdr *tcphdr);
+void tcp_debug_print_flags(u8_t flags);
+void tcp_debug_print_state(enum tcp_state s);
+void tcp_debug_print_pcbs(void);
+s16_t tcp_pcbs_sane(void);
+#else
+#  define tcp_debug_print(tcphdr)
+#  define tcp_debug_print_flags(flags)
+#  define tcp_debug_print_state(s)
+#  define tcp_debug_print_pcbs()
+#  define tcp_pcbs_sane() 1
+#endif /* TCP_DEBUG */
+
+#if NO_SYS
+#define tcp_timer_needed()
+#else
+void tcp_timer_needed(void);
+#endif
+
+/* The TCP PCB lists. */
+union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */
+  struct tcp_pcb_listen *listen_pcbs;
+  struct tcp_pcb *pcbs;
+};
+extern union tcp_listen_pcbs_t tcp_listen_pcbs;
+extern struct tcp_pcb *tcp_active_pcbs;  /* List of all TCP PCBs that are in a
+              state in which they accept or send
+              data. */
+extern struct tcp_pcb *tcp_tw_pcbs;      /* List of all TCP PCBs in TIME-WAIT. */
+
+extern struct tcp_pcb *tcp_tmp_pcb;      /* Only used for temporary storage. */
+
+/* Axioms about the above lists:
+   1) Every TCP PCB that is not CLOSED is in one of the lists.
+   2) A PCB is only in one of the lists.
+   3) All PCBs in the tcp_listen_pcbs list is in LISTEN state.
+   4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state.
+*/
+
+/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB
+   with a PCB list or removes a PCB from a list, respectively. */
+#if 0
+#define TCP_REG(pcbs, npcb) do {\
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %d\n", npcb, npcb->local_port)); \
+                            for(tcp_tmp_pcb = *pcbs; \
+          tcp_tmp_pcb != NULL; \
+        tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+                                LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != npcb); \
+                            } \
+                            LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", npcb->state != CLOSED); \
+                            npcb->next = *pcbs; \
+                            LWIP_ASSERT("TCP_REG: npcb->next != npcb", npcb->next != npcb); \
+                            *(pcbs) = npcb; \
+                            LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
+              tcp_timer_needed(); \
+                            } while(0)
+#define TCP_RMV(pcbs, npcb) do { \
+                            LWIP_ASSERT("TCP_RMV: pcbs != NULL", *pcbs != NULL); \
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", npcb, *pcbs)); \
+                            if(*pcbs == npcb) { \
+                               *pcbs = (*pcbs)->next; \
+                            } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+                               if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \
+                                  tcp_tmp_pcb->next = npcb->next; \
+                                  break; \
+                               } \
+                            } \
+                            npcb->next = NULL; \
+                            LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", npcb, *pcbs)); \
+                            } while(0)
+
+#else /* LWIP_DEBUG */
+#define TCP_REG(pcbs, npcb) do { \
+                            npcb->next = *pcbs; \
+                            *(pcbs) = npcb; \
+              tcp_timer_needed(); \
+                            } while(0)
+#define TCP_RMV(pcbs, npcb) do { \
+                            if(*(pcbs) == npcb) { \
+                               (*(pcbs)) = (*pcbs)->next; \
+                            } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+                               if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \
+                                  tcp_tmp_pcb->next = npcb->next; \
+                                  break; \
+                               } \
+                            } \
+                            npcb->next = NULL; \
+                            } while(0)
+#endif /* LWIP_DEBUG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_TCP */
+
+#endif /* __LWIP_TCP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/tcpip.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/tcpip.h
new file mode 100644
index 0000000..7822437
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/tcpip.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_TCPIP_H__
+#define __LWIP_TCPIP_H__
+
+#include "lwip/opt.h"
+
+#if !NO_SYS /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/api_msg.h"
+#include "lwip/netifapi.h"
+#include "lwip/pbuf.h"
+#include "lwip/api.h"
+#include "lwip/sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_TCPIP_CORE_LOCKING
+/** The global semaphore to lock the stack. */
+extern sys_sem_t lock_tcpip_core;
+#define LOCK_TCPIP_CORE()     sys_sem_wait(lock_tcpip_core)
+#define UNLOCK_TCPIP_CORE()   sys_sem_signal(lock_tcpip_core)
+#define TCPIP_APIMSG(m)       tcpip_apimsg_lock(m)
+#define TCPIP_APIMSG_ACK(m)
+#define TCPIP_NETIFAPI(m)     tcpip_netifapi_lock(m)
+#define TCPIP_NETIFAPI_ACK(m)
+#else
+#define LOCK_TCPIP_CORE()
+#define UNLOCK_TCPIP_CORE()
+#define TCPIP_APIMSG(m)       tcpip_apimsg(m)
+#define TCPIP_APIMSG_ACK(m)   sys_sem_signal(m->conn->op_completed)
+#define TCPIP_NETIFAPI(m)     tcpip_netifapi(m)
+#define TCPIP_NETIFAPI_ACK(m) sys_sem_signal(m->sem)
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+
+void tcpip_init(void (* tcpip_init_done)(void *), void *arg);
+
+#if LWIP_NETCONN
+err_t tcpip_apimsg(struct api_msg *apimsg);
+#if LWIP_TCPIP_CORE_LOCKING
+err_t tcpip_apimsg_lock(struct api_msg *apimsg);
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+#endif /* LWIP_NETCONN */
+
+err_t tcpip_input(struct pbuf *p, struct netif *inp);
+
+#if LWIP_NETIF_API
+err_t tcpip_netifapi(struct netifapi_msg *netifapimsg);
+#if LWIP_TCPIP_CORE_LOCKING
+err_t tcpip_netifapi_lock(struct netifapi_msg *netifapimsg);
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+#endif /* LWIP_NETIF_API */
+
+err_t tcpip_callback_with_block(void (*f)(void *ctx), void *ctx, u8_t block);
+#define tcpip_callback(f,ctx) tcpip_callback_with_block(f,ctx,1)
+
+err_t tcpip_timeout(u32_t msecs, sys_timeout_handler h, void *arg);
+#define tcpip_untimeout(h, arg) tcpip_timeout(0xffffffff, h, arg)
+
+enum tcpip_msg_type {
+#if LWIP_NETCONN
+  TCPIP_MSG_API,
+#endif /* LWIP_NETCONN */
+  TCPIP_MSG_INPKT,
+#if LWIP_NETIF_API
+  TCPIP_MSG_NETIFAPI,
+#endif /* LWIP_NETIF_API */
+  TCPIP_MSG_CALLBACK,
+  TCPIP_MSG_TIMEOUT
+};
+
+struct tcpip_msg {
+  enum tcpip_msg_type type;
+  sys_sem_t *sem;
+  union {
+#if LWIP_NETCONN
+    struct api_msg *apimsg;
+#endif /* LWIP_NETCONN */
+#if LWIP_NETIF_API
+    struct netifapi_msg *netifapimsg;
+#endif /* LWIP_NETIF_API */
+    struct {
+      struct pbuf *p;
+      struct netif *netif;
+    } inp;
+    struct {
+      void (*f)(void *ctx);
+      void *ctx;
+    } cb;
+    struct {
+      u32_t msecs;
+      sys_timeout_handler h;
+      void *arg;
+    } tmo;
+  } msg;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !NO_SYS */
+
+#endif /* __LWIP_TCPIP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/udp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/udp.h
new file mode 100644
index 0000000..7cdcdfe
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/lwip/udp.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_UDP_H__
+#define __LWIP_UDP_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_UDP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/ip_addr.h"
+#include "lwip/ip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define UDP_HLEN 8
+
+/* Fields are (of course) in network byte order. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+#if (defined(__MWERKS__)  || defined(__CWCC__))
+	#pragma options align= packed
+#endif
+struct udp_hdr {
+  PACK_STRUCT_FIELD(u16_t src);
+  PACK_STRUCT_FIELD(u16_t dest);  /* src/dest UDP ports */
+  PACK_STRUCT_FIELD(u16_t len);
+  PACK_STRUCT_FIELD(u16_t chksum);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define UDP_FLAGS_NOCHKSUM 0x01U
+#define UDP_FLAGS_UDPLITE  0x02U
+#define UDP_FLAGS_CONNECTED  0x04U
+
+struct udp_pcb {
+/* Common members of all PCB types */
+  IP_PCB;
+
+/* Protocol specific PCB members */
+
+  struct udp_pcb *next;
+
+  u8_t flags;
+  /* ports are in host byte order */
+  u16_t local_port, remote_port;
+
+#if LWIP_IGMP
+  /* outgoing network interface for multicast packets */
+  struct ip_addr multicast_ip;
+#endif /* LWIP_IGMP */
+
+#if LWIP_UDPLITE
+  /* used for UDP_LITE only */
+  u16_t chksum_len_rx, chksum_len_tx;
+#endif /* LWIP_UDPLITE */
+
+  /* receive callback function
+   * addr and port are in same byte order as in the pcb
+   * The callback is responsible for freeing the pbuf
+   * if it's not used any more.
+   *
+   * @param arg user supplied argument (udp_pcb.recv_arg)
+   * @param pcb the udp_pcb which received data
+   * @param p the packet buffer that was received
+   * @param addr the remote IP address from which the packet was received
+   * @param port the remote port from which the packet was received
+   */
+  void (* recv)(void *arg, struct udp_pcb *pcb, struct pbuf *p,
+    struct ip_addr *addr, u16_t port);
+  /* user-supplied argument for the recv callback */
+  void *recv_arg;
+};
+/* udp_pcbs export for exernal reference (e.g. SNMP agent) */
+extern struct udp_pcb *udp_pcbs;
+
+/* The following functions is the application layer interface to the
+   UDP code. */
+struct udp_pcb * udp_new        (void);
+void             udp_remove     (struct udp_pcb *pcb);
+err_t            udp_bind       (struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port);
+err_t            udp_connect    (struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port);
+void             udp_disconnect    (struct udp_pcb *pcb);
+void             udp_recv       (struct udp_pcb *pcb,
+         void (* recv)(void *arg, struct udp_pcb *upcb,
+                 struct pbuf *p,
+                 struct ip_addr *addr,
+                 u16_t port),
+         void *recv_arg);
+err_t            udp_sendto_if  (struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *dst_ip, u16_t dst_port, struct netif *netif);
+err_t            udp_sendto     (struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *dst_ip, u16_t dst_port);
+err_t            udp_send       (struct udp_pcb *pcb, struct pbuf *p);
+
+#define          udp_flags(pcb)  ((pcb)->flags)
+#define          udp_setflags(pcb, f)  ((pcb)->flags = (f))
+
+/* The following functions are the lower layer interface to UDP. */
+void             udp_input      (struct pbuf *p, struct netif *inp);
+
+#define udp_init() /* Compatibility define, not init needed. */
+
+#if UDP_DEBUG
+void udp_debug_print(struct udp_hdr *udphdr);
+#else
+#define udp_debug_print(udphdr)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_UDP */
+
+#endif /* __LWIP_UDP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/netif/etharp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/netif/etharp.h
new file mode 100644
index 0000000..3cea6ca
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/netif/etharp.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (c) 2003-2004 Leon Woestenberg 
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef __NETIF_ETHARP_H__
+#define __NETIF_ETHARP_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_ARP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/ip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef ETH_PAD_SIZE
+#define ETH_PAD_SIZE          0
+#endif
+
+#ifndef ETHARP_HWADDR_LEN
+#define ETHARP_HWADDR_LEN     6
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+#if (defined(__MWERKS__)  || defined(__CWCC__))
+	#pragma options align= packed
+#endif
+struct eth_addr {
+  PACK_STRUCT_FIELD(u8_t addr[ETHARP_HWADDR_LEN]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+#if (defined(__MWERKS__)  || defined(__CWCC__))
+	#pragma options align= packed
+#endif
+struct eth_hdr {
+#if ETH_PAD_SIZE
+  PACK_STRUCT_FIELD(u8_t padding[ETH_PAD_SIZE]);
+#endif
+  PACK_STRUCT_FIELD(struct eth_addr dest);
+  PACK_STRUCT_FIELD(struct eth_addr src);
+  PACK_STRUCT_FIELD(u16_t type);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+#if (defined(__MWERKS__)  || defined(__CWCC__))
+	#pragma options align= packed
+#endif
+/** the ARP message */
+struct etharp_hdr {
+  PACK_STRUCT_FIELD(struct eth_hdr ethhdr);
+  PACK_STRUCT_FIELD(u16_t hwtype);
+  PACK_STRUCT_FIELD(u16_t proto);
+  PACK_STRUCT_FIELD(u16_t _hwlen_protolen);
+  PACK_STRUCT_FIELD(u16_t opcode);
+  PACK_STRUCT_FIELD(struct eth_addr shwaddr);
+  PACK_STRUCT_FIELD(struct ip_addr2 sipaddr);
+  PACK_STRUCT_FIELD(struct eth_addr dhwaddr);
+  PACK_STRUCT_FIELD(struct ip_addr2 dipaddr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+#if (defined(__MWERKS__)  || defined(__CWCC__))
+	#pragma options align= packed
+#endif
+struct ethip_hdr {
+  PACK_STRUCT_FIELD(struct eth_hdr eth);
+  PACK_STRUCT_FIELD(struct ip_hdr ip);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** 5 seconds period */
+#define ARP_TMR_INTERVAL 5000
+
+#define ETHTYPE_ARP       0x0806
+#define ETHTYPE_IP        0x0800
+#define ETHTYPE_PPPOEDISC 0x8863  /* PPP Over Ethernet Discovery Stage */
+#define ETHTYPE_PPPOE     0x8864  /* PPP Over Ethernet Session Stage */
+
+/** ARP message types (opcodes) */
+#define ARP_REQUEST 1
+#define ARP_REPLY   2
+
+#if ARP_QUEUEING
+/** struct for queueing outgoing packets for unknown address
+  * defined here to be accessed by memp.h
+  */
+struct etharp_q_entry {
+  struct etharp_q_entry *next;
+  struct pbuf *p;
+};
+#endif /* ARP_QUEUEING */
+
+#define etharp_init() /* Compatibility define, not init needed. */
+void etharp_tmr(void);
+s8_t etharp_find_addr(struct netif *netif, struct ip_addr *ipaddr,
+         struct eth_addr **eth_ret, struct ip_addr **ip_ret);
+void etharp_ip_input(struct netif *netif, struct pbuf *p);
+void etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr,
+         struct pbuf *p);
+err_t etharp_output(struct netif *netif, struct pbuf *q, struct ip_addr *ipaddr);
+err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q);
+err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr);
+
+err_t ethernet_input(struct pbuf *p, struct netif *netif);
+
+#if LWIP_AUTOIP
+err_t etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr,
+                 const struct eth_addr *ethdst_addr,
+                 const struct eth_addr *hwsrc_addr, const struct ip_addr *ipsrc_addr,
+                 const struct eth_addr *hwdst_addr, const struct ip_addr *ipdst_addr,
+                 const u16_t opcode);
+#endif /* LWIP_AUTOIP */
+
+#define eth_addr_cmp(addr1, addr2) (memcmp((addr1)->addr, (addr2)->addr, ETHARP_HWADDR_LEN) == 0)
+
+extern const struct eth_addr ethbroadcast, ethzero;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_ARP */
+
+#endif /* __NETIF_ARP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/netif/loopif.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/netif/loopif.h
new file mode 100644
index 0000000..979ac7a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/netif/loopif.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __NETIF_LOOPIF_H__
+#define __NETIF_LOOPIF_H__
+
+#include "lwip/netif.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !LWIP_LOOPIF_MULTITHREADING
+void loopif_poll(struct netif *netif);
+#endif
+
+err_t loopif_init(struct netif *netif);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NETIF_LOOPIF_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/netif/ppp_oe.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/netif/ppp_oe.h
new file mode 100644
index 0000000..aa95382
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/netif/ppp_oe.h
@@ -0,0 +1,167 @@
+/*****************************************************************************
+* ppp_oe.h - PPP Over Ethernet implementation for lwIP.
+*
+* Copyright (c) 2006 by Marc Boucher, Services Informatiques (MBSI) inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 06-01-01 Marc Boucher 
+*   Ported to lwIP.
+*****************************************************************************/
+
+
+
+/* based on NetBSD: if_pppoe.c,v 1.64 2006/01/31 23:50:15 martin Exp */
+
+/*-
+ * Copyright (c) 2002 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Martin Husemann .
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef PPP_OE_H
+#define PPP_OE_H
+
+#include "lwip/opt.h"
+
+#if PPPOE_SUPPORT > 0
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+#if (defined(__MWERKS__)  || defined(__CWCC__))
+	#pragma options align= packed
+#endif
+struct pppoehdr {
+	PACK_STRUCT_FIELD(u8_t vertype);
+	PACK_STRUCT_FIELD(u8_t code);
+	PACK_STRUCT_FIELD(u16_t session);
+	PACK_STRUCT_FIELD(u16_t plen);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+#if (defined(__MWERKS__)  || defined(__CWCC__))
+	#pragma options align= packed
+#endif
+struct pppoetag {
+	PACK_STRUCT_FIELD(u16_t tag);
+	PACK_STRUCT_FIELD(u16_t len);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+
+#define PPPOE_STATE_INITIAL	0
+#define PPPOE_STATE_PADI_SENT	1
+#define	PPPOE_STATE_PADR_SENT	2
+#define	PPPOE_STATE_SESSION	3
+#define	PPPOE_STATE_CLOSING	4
+/* passive */
+#define	PPPOE_STATE_PADO_SENT	1
+
+#define PPPOE_HEADERLEN	sizeof(struct pppoehdr)
+#define	PPPOE_VERTYPE	0x11	/* VER=1, TYPE = 1 */
+
+#define	PPPOE_TAG_EOL		0x0000		/* end of list */
+#define	PPPOE_TAG_SNAME		0x0101		/* service name */
+#define	PPPOE_TAG_ACNAME	0x0102		/* access concentrator name */
+#define	PPPOE_TAG_HUNIQUE	0x0103		/* host unique */
+#define	PPPOE_TAG_ACCOOKIE	0x0104		/* AC cookie */
+#define	PPPOE_TAG_VENDOR	0x0105		/* vendor specific */
+#define	PPPOE_TAG_RELAYSID	0x0110		/* relay session id */
+#define	PPPOE_TAG_SNAME_ERR	0x0201		/* service name error */
+#define	PPPOE_TAG_ACSYS_ERR	0x0202		/* AC system error */
+#define	PPPOE_TAG_GENERIC_ERR	0x0203		/* gerneric error */
+
+#define PPPOE_CODE_PADI		0x09		/* Active Discovery Initiation */
+#define	PPPOE_CODE_PADO		0x07		/* Active Discovery Offer */
+#define	PPPOE_CODE_PADR		0x19		/* Active Discovery Request */
+#define	PPPOE_CODE_PADS		0x65		/* Active Discovery Session confirmation */
+#define	PPPOE_CODE_PADT		0xA7		/* Active Discovery Terminate */
+
+#ifndef ETHERMTU
+#define ETHERMTU 1500
+#endif
+
+/* two byte PPP protocol discriminator, then IP data */
+#define	PPPOE_MAXMTU	(ETHERMTU-PPPOE_HEADERLEN-2)
+
+struct pppoe_softc;
+
+
+void pppoe_init(void);
+
+err_t pppoe_create(struct netif *ethif, int pd, void (*linkStatusCB)(int pd, int up), struct pppoe_softc **scptr);
+err_t pppoe_destroy(struct netif *ifp);
+
+int pppoe_connect(struct pppoe_softc *sc);
+void pppoe_disconnect(struct pppoe_softc *sc);
+
+void pppoe_disc_input(struct netif *netif, struct pbuf *p);
+void pppoe_data_input(struct netif *netif, struct pbuf *p);
+
+err_t pppoe_xmit(struct pppoe_softc *sc, struct pbuf *pb);
+
+extern int pppoe_hdrlen;
+
+#endif /* PPPOE_SUPPORT */
+
+#endif /* PPP_OE_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/netif/slipif.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/netif/slipif.h
new file mode 100644
index 0000000..ef11e97
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/include/netif/slipif.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __NETIF_SLIPIF_H__
+#define __NETIF_SLIPIF_H__
+
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+err_t slipif_init(struct netif * netif);
+
+#ifdef __cplusplus
+}
+#endif
+ 
+#endif 
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/FILES b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/FILES
new file mode 100644
index 0000000..a0dca19
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/FILES
@@ -0,0 +1,25 @@
+This directory contains generic network interface device drivers that
+do not contain any hardware or architecture specific code. The files
+are:
+
+etharp.c
+          Implements the ARP (Address Resolution Protocol) over
+          Ethernet. The code in this file should be used together with
+          Ethernet device drivers. Note that this module has been
+          largely made Ethernet independent so you should be able to
+          adapt this for other link layers (such as Firewire).
+
+ethernetif.c
+          An example of how an Ethernet device driver could look. This
+          file can be used as a "skeleton" for developing new Ethernet
+          network device drivers. It uses the etharp.c ARP code.
+
+loopif.c
+          A "loopback" network interface driver. It requires configuration
+          through the define LWIP_LOOPIF_MULTITHREADING (see opt.h).
+
+slipif.c
+          A generic implementation of the SLIP (Serial Line IP)
+          protocol. It requires a sio (serial I/O) module to work.
+
+ppp/      Point-to-Point Protocol stack
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/etharp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/etharp.c
new file mode 100644
index 0000000..27ae689
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/etharp.c
@@ -0,0 +1,1177 @@
+/**
+ * @file
+ * Address Resolution Protocol module for IP over Ethernet
+ *
+ * Functionally, ARP is divided into two parts. The first maps an IP address
+ * to a physical address when sending a packet, and the second part answers
+ * requests from other machines for our physical address.
+ *
+ * This implementation complies with RFC 826 (Ethernet ARP). It supports
+ * Gratuitious ARP from RFC3220 (IP Mobility Support for IPv4) section 4.6
+ * if an interface calls etharp_query(our_netif, its_ip_addr, NULL) upon
+ * address change.
+ */
+
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (c) 2003-2004 Leon Woestenberg 
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_ARP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+#include "lwip/dhcp.h"
+#include "lwip/autoip.h"
+#include "netif/etharp.h"
+
+#if PPPOE_SUPPORT
+#include "netif/ppp_oe.h"
+#endif /* PPPOE_SUPPORT */
+
+#include 
+
+/** the time an ARP entry stays valid after its last update,
+ *  for ARP_TMR_INTERVAL = 5000, this is
+ *  (240 * 5) seconds = 20 minutes.
+ */
+#define ARP_MAXAGE 240
+/** the time an ARP entry stays pending after first request,
+ *  for ARP_TMR_INTERVAL = 5000, this is
+ *  (2 * 5) seconds = 10 seconds.
+ *
+ *  @internal Keep this number at least 2, otherwise it might
+ *  run out instantly if the timeout occurs directly after a request.
+ */
+#define ARP_MAXPENDING 2
+
+#define HWTYPE_ETHERNET 1
+
+#define ARPH_HWLEN(hdr) (ntohs((hdr)->_hwlen_protolen) >> 8)
+#define ARPH_PROTOLEN(hdr) (ntohs((hdr)->_hwlen_protolen) & 0xff)
+
+#define ARPH_HWLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons(ARPH_PROTOLEN(hdr) | ((len) << 8))
+#define ARPH_PROTOLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons((len) | (ARPH_HWLEN(hdr) << 8))
+
+enum etharp_state {
+  ETHARP_STATE_EMPTY = 0,
+  ETHARP_STATE_PENDING,
+  ETHARP_STATE_STABLE
+};
+
+struct etharp_entry {
+#if ARP_QUEUEING
+  /**
+   * Pointer to queue of pending outgoing packets on this ARP entry.
+   */
+  struct etharp_q_entry *q;
+#endif
+  struct ip_addr ipaddr;
+  struct eth_addr ethaddr;
+  enum etharp_state state;
+  u8_t ctime;
+  struct netif *netif;
+};
+
+const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}};
+const struct eth_addr ethzero = {{0,0,0,0,0,0}};
+static struct etharp_entry arp_table[ARP_TABLE_SIZE];
+#if !LWIP_NETIF_HWADDRHINT
+static u8_t etharp_cached_entry;
+#endif
+
+/**
+ * Try hard to create a new entry - we want the IP address to appear in
+ * the cache (even if this means removing an active entry or so). */
+#define ETHARP_TRY_HARD 1
+#define ETHARP_FIND_ONLY  2
+
+#if LWIP_NETIF_HWADDRHINT
+#define NETIF_SET_HINT(netif, hint)  if (((netif) != NULL) && ((netif)->addr_hint != NULL))  \
+                                      *((netif)->addr_hint) = (hint);
+static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags, struct netif *netif);
+#else /* LWIP_NETIF_HWADDRHINT */
+static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags);
+#endif /* LWIP_NETIF_HWADDRHINT */
+
+static err_t update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags);
+
+
+/* Some checks, instead of etharp_init(): */
+#if (LWIP_ARP && (ARP_TABLE_SIZE > 0x7f))
+  #error "If you want to use ARP, ARP_TABLE_SIZE must fit in an s8_t, so, you have to reduce it in your lwipopts.h"
+#endif
+
+
+#if ARP_QUEUEING
+/**
+ * Free a complete queue of etharp entries
+ *
+ * @param q a qeueue of etharp_q_entry's to free
+ */
+static void
+free_etharp_q(struct etharp_q_entry *q)
+{
+  struct etharp_q_entry *r;
+  LWIP_ASSERT("q != NULL", q != NULL);
+  LWIP_ASSERT("q->p != NULL", q->p != NULL);
+  while (q) {
+    r = q;
+    q = q->next;
+    LWIP_ASSERT("r->p != NULL", (r->p != NULL));
+    pbuf_free(r->p);
+    memp_free(MEMP_ARP_QUEUE, r);
+  }
+}
+#endif
+
+/**
+ * Clears expired entries in the ARP table.
+ *
+ * This function should be called every ETHARP_TMR_INTERVAL microseconds (5 seconds),
+ * in order to expire entries in the ARP table.
+ */
+void
+etharp_tmr(void)
+{
+  u8_t i;
+
+  LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n"));
+  /* remove expired entries from the ARP table */
+  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
+    arp_table[i].ctime++;
+    if (((arp_table[i].state == ETHARP_STATE_STABLE) &&
+         (arp_table[i].ctime >= ARP_MAXAGE)) ||
+        ((arp_table[i].state == ETHARP_STATE_PENDING)  &&
+         (arp_table[i].ctime >= ARP_MAXPENDING))) {
+         /* pending or stable entry has become old! */
+      LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired %s entry %"U16_F".\n",
+           arp_table[i].state == ETHARP_STATE_STABLE ? "stable" : "pending", (u16_t)i));
+      /* clean up entries that have just been expired */
+      /* remove from SNMP ARP index tree */
+      snmp_delete_arpidx_tree(arp_table[i].netif, &arp_table[i].ipaddr);
+#if ARP_QUEUEING
+      /* and empty packet queue */
+      if (arp_table[i].q != NULL) {
+        /* remove all queued packets */
+        LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].q)));
+        free_etharp_q(arp_table[i].q);
+        arp_table[i].q = NULL;
+      }
+#endif
+      /* recycle entry for re-use */
+      arp_table[i].state = ETHARP_STATE_EMPTY;
+    }
+#if ARP_QUEUEING
+    /* still pending entry? (not expired) */
+    if (arp_table[i].state == ETHARP_STATE_PENDING) {
+        /* resend an ARP query here? */
+    }
+#endif
+  }
+}
+
+/**
+ * Search the ARP table for a matching or new entry.
+ *
+ * If an IP address is given, return a pending or stable ARP entry that matches
+ * the address. If no match is found, create a new entry with this address set,
+ * but in state ETHARP_EMPTY. The caller must check and possibly change the
+ * state of the returned entry.
+ *
+ * If ipaddr is NULL, return a initialized new entry in state ETHARP_EMPTY.
+ *
+ * In all cases, attempt to create new entries from an empty entry. If no
+ * empty entries are available and ETHARP_TRY_HARD flag is set, recycle
+ * old entries. Heuristic choose the least important entry for recycling.
+ *
+ * @param ipaddr IP address to find in ARP cache, or to add if not found.
+ * @param flags
+ * - ETHARP_TRY_HARD: Try hard to create a entry by allowing recycling of
+ * active (stable or pending) entries.
+ *
+ * @return The ARP entry index that matched or is created, ERR_MEM if no
+ * entry is found or could be recycled.
+ */
+static s8_t
+#if LWIP_NETIF_HWADDRHINT
+find_entry(struct ip_addr *ipaddr, u8_t flags, struct netif *netif)
+#else /* LWIP_NETIF_HWADDRHINT */
+find_entry(struct ip_addr *ipaddr, u8_t flags)
+#endif /* LWIP_NETIF_HWADDRHINT */
+{
+  s8_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE;
+  s8_t empty = ARP_TABLE_SIZE;
+  u8_t i = 0, age_pending = 0, age_stable = 0;
+#if ARP_QUEUEING
+  /* oldest entry with packets on queue */
+  s8_t old_queue = ARP_TABLE_SIZE;
+  /* its age */
+  u8_t age_queue = 0;
+#endif
+
+  /* First, test if the last call to this function asked for the
+   * same address. If so, we're really fast! */
+  if (ipaddr) {
+    /* ipaddr to search for was given */
+#if LWIP_NETIF_HWADDRHINT
+    if ((netif != NULL) && (netif->addr_hint != NULL)) {
+      /* per-pcb cached entry was given */
+      u8_t per_pcb_cache = *(netif->addr_hint);
+      if ((per_pcb_cache < ARP_TABLE_SIZE) && arp_table[per_pcb_cache].state == ETHARP_STATE_STABLE) {
+        /* the per-pcb-cached entry is stable */
+        if (ip_addr_cmp(ipaddr, &arp_table[per_pcb_cache].ipaddr)) {
+          /* per-pcb cached entry was the right one! */
+          ETHARP_STATS_INC(etharp.cachehit);
+          return per_pcb_cache;
+        }
+      }
+    }
+#else /* #if LWIP_NETIF_HWADDRHINT */
+    if (arp_table[etharp_cached_entry].state == ETHARP_STATE_STABLE) {
+      /* the cached entry is stable */
+      if (ip_addr_cmp(ipaddr, &arp_table[etharp_cached_entry].ipaddr)) {
+        /* cached entry was the right one! */
+        ETHARP_STATS_INC(etharp.cachehit);
+        return etharp_cached_entry;
+      }
+    }
+#endif /* #if LWIP_NETIF_HWADDRHINT */
+  }
+
+  /**
+   * a) do a search through the cache, remember candidates
+   * b) select candidate entry
+   * c) create new entry
+   */
+
+  /* a) in a single search sweep, do all of this
+   * 1) remember the first empty entry (if any)
+   * 2) remember the oldest stable entry (if any)
+   * 3) remember the oldest pending entry without queued packets (if any)
+   * 4) remember the oldest pending entry with queued packets (if any)
+   * 5) search for a matching IP entry, either pending or stable
+   *    until 5 matches, or all entries are searched for.
+   */
+
+  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
+    /* no empty entry found yet and now we do find one? */
+    if ((empty == ARP_TABLE_SIZE) && (arp_table[i].state == ETHARP_STATE_EMPTY)) {
+      LWIP_DEBUGF(ETHARP_DEBUG, ("find_entry: found empty entry %"U16_F"\n", (u16_t)i));
+      /* remember first empty entry */
+      empty = i;
+    }
+    /* pending entry? */
+    else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+      /* if given, does IP address match IP address in ARP entry? */
+      if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: found matching pending entry %"U16_F"\n", (u16_t)i));
+        /* found exact IP address match, simply bail out */
+#if LWIP_NETIF_HWADDRHINT
+        NETIF_SET_HINT(netif, i);
+#else /* #if LWIP_NETIF_HWADDRHINT */
+        etharp_cached_entry = i;
+#endif /* #if LWIP_NETIF_HWADDRHINT */
+        return i;
+#if ARP_QUEUEING
+      /* pending with queued packets? */
+      } else if (arp_table[i].q != NULL) {
+        if (arp_table[i].ctime >= age_queue) {
+          old_queue = i;
+          age_queue = arp_table[i].ctime;
+        }
+#endif
+      /* pending without queued packets? */
+      } else {
+        if (arp_table[i].ctime >= age_pending) {
+          old_pending = i;
+          age_pending = arp_table[i].ctime;
+        }
+      }
+    }
+    /* stable entry? */
+    else if (arp_table[i].state == ETHARP_STATE_STABLE) {
+      /* if given, does IP address match IP address in ARP entry? */
+      if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: found matching stable entry %"U16_F"\n", (u16_t)i));
+        /* found exact IP address match, simply bail out */
+#if LWIP_NETIF_HWADDRHINT
+        NETIF_SET_HINT(netif, i);
+#else /* #if LWIP_NETIF_HWADDRHINT */
+        etharp_cached_entry = i;
+#endif /* #if LWIP_NETIF_HWADDRHINT */
+        return i;
+      /* remember entry with oldest stable entry in oldest, its age in maxtime */
+      } else if (arp_table[i].ctime >= age_stable) {
+        old_stable = i;
+        age_stable = arp_table[i].ctime;
+      }
+    }
+  }
+  /* { we have no match } => try to create a new entry */
+
+  /* no empty entry found and not allowed to recycle? */
+  if (((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_TRY_HARD) == 0))
+      /* or don't create new entry, only search? */
+      || ((flags & ETHARP_FIND_ONLY) != 0)) {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: no empty entry found and not allowed to recycle\n"));
+    return (s8_t)ERR_MEM;
+  }
+
+  /* b) choose the least destructive entry to recycle:
+   * 1) empty entry
+   * 2) oldest stable entry
+   * 3) oldest pending entry without queued packets
+   * 4) oldest pending entry without queued packets
+   *
+   * { ETHARP_TRY_HARD is set at this point }
+   */
+
+  /* 1) empty entry available? */
+  if (empty < ARP_TABLE_SIZE) {
+    i = empty;
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting empty entry %"U16_F"\n", (u16_t)i));
+  }
+  /* 2) found recyclable stable entry? */
+  else if (old_stable < ARP_TABLE_SIZE) {
+    /* recycle oldest stable*/
+    i = old_stable;
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting oldest stable entry %"U16_F"\n", (u16_t)i));
+#if ARP_QUEUEING
+    /* no queued packets should exist on stable entries */
+    LWIP_ASSERT("arp_table[i].q == NULL", arp_table[i].q == NULL);
+#endif
+  /* 3) found recyclable pending entry without queued packets? */
+  } else if (old_pending < ARP_TABLE_SIZE) {
+    /* recycle oldest pending */
+    i = old_pending;
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F" (without queue)\n", (u16_t)i));
+#if ARP_QUEUEING
+  /* 4) found recyclable pending entry with queued packets? */
+  } else if (old_queue < ARP_TABLE_SIZE) {
+    /* recycle oldest pending */
+    i = old_queue;
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F", freeing packet queue %p\n", (u16_t)i, (void *)(arp_table[i].q)));
+    free_etharp_q(arp_table[i].q);
+    arp_table[i].q = NULL;
+#endif
+    /* no empty or recyclable entries found */
+  } else {
+    return (s8_t)ERR_MEM;
+  }
+
+  /* { empty or recyclable entry found } */
+  LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
+
+  if (arp_table[i].state != ETHARP_STATE_EMPTY)
+  {
+    snmp_delete_arpidx_tree(arp_table[i].netif, &arp_table[i].ipaddr);
+  }
+  /* recycle entry (no-op for an already empty entry) */
+  arp_table[i].state = ETHARP_STATE_EMPTY;
+
+  /* IP address given? */
+  if (ipaddr != NULL) {
+    /* set IP address */
+    ip_addr_set(&arp_table[i].ipaddr, ipaddr);
+  }
+  arp_table[i].ctime = 0;
+#if LWIP_NETIF_HWADDRHINT
+  NETIF_SET_HINT(netif, i);
+#else /* #if LWIP_NETIF_HWADDRHINT */
+  etharp_cached_entry = i;
+#endif /* #if LWIP_NETIF_HWADDRHINT */
+  return (err_t)i;
+}
+
+/**
+ * Send an IP packet on the network using netif->linkoutput
+ * The ethernet header is filled in before sending.
+ *
+ * @params netif the lwIP network interface on which to send the packet
+ * @params p the packet to send, p->payload pointing to the (uninitialized) ethernet header
+ * @params src the source MAC address to be copied into the ethernet header
+ * @params dst the destination MAC address to be copied into the ethernet header
+ * @return ERR_OK if the packet was sent, any other err_t on failure
+ */
+static err_t
+etharp_send_ip(struct netif *netif, struct pbuf *p, struct eth_addr *src, struct eth_addr *dst)
+{
+  struct eth_hdr *ethhdr = p->payload;
+  u8_t k;
+
+  LWIP_ASSERT("netif->hwaddr_len must be the same as ETHARP_HWADDR_LEN for etharp!",
+              (netif->hwaddr_len == ETHARP_HWADDR_LEN));
+  k = ETHARP_HWADDR_LEN;
+  while(k > 0) {
+    k--;
+    ethhdr->dest.addr[k] = dst->addr[k];
+    ethhdr->src.addr[k]  = src->addr[k];
+  }
+  ethhdr->type = htons(ETHTYPE_IP);
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_send_ip: sending packet %p\n", (void *)p));
+  /* send the packet */
+  return netif->linkoutput(netif, p);
+}
+
+/**
+ * Update (or insert) a IP/MAC address pair in the ARP cache.
+ *
+ * If a pending entry is resolved, any queued packets will be sent
+ * at this point.
+ *
+ * @param ipaddr IP address of the inserted ARP entry.
+ * @param ethaddr Ethernet address of the inserted ARP entry.
+ * @param flags Defines behaviour:
+ * - ETHARP_TRY_HARD Allows ARP to insert this as a new item. If not specified,
+ * only existing ARP entries will be updated.
+ *
+ * @return
+ * - ERR_OK Succesfully updated ARP cache.
+ * - ERR_MEM If we could not add a new ARP entry when ETHARP_TRY_HARD was set.
+ * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
+ *
+ * @see pbuf_free()
+ */
+static err_t
+update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags)
+{
+  s8_t i;
+  u8_t k;
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | 3, ("update_arp_entry()\n"));
+  LWIP_ASSERT("netif->hwaddr_len == ETHARP_HWADDR_LEN", netif->hwaddr_len == ETHARP_HWADDR_LEN);
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n",
+                                        ip4_addr1(ipaddr), ip4_addr2(ipaddr), ip4_addr3(ipaddr), ip4_addr4(ipaddr),
+                                        ethaddr->addr[0], ethaddr->addr[1], ethaddr->addr[2],
+                                        ethaddr->addr[3], ethaddr->addr[4], ethaddr->addr[5]));
+  /* non-unicast address? */
+  if (ip_addr_isany(ipaddr) ||
+      ip_addr_isbroadcast(ipaddr, netif) ||
+      ip_addr_ismulticast(ipaddr)) {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("update_arp_entry: will not add non-unicast IP address to ARP cache\n"));
+    return ERR_ARG;
+  }
+  /* find or create ARP entry */
+#if LWIP_NETIF_HWADDRHINT
+  i = find_entry(ipaddr, flags, netif);
+#else /* LWIP_NETIF_HWADDRHINT */
+  i = find_entry(ipaddr, flags);
+#endif /* LWIP_NETIF_HWADDRHINT */
+  /* bail out if no entry could be found */
+  if (i < 0)
+    return (err_t)i;
+
+  /* mark it stable */
+  arp_table[i].state = ETHARP_STATE_STABLE;
+  /* record network interface */
+  arp_table[i].netif = netif;
+
+  /* insert in SNMP ARP index tree */
+  snmp_insert_arpidx_tree(netif, &arp_table[i].ipaddr);
+
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("update_arp_entry: updating stable entry %"S16_F"\n", (s16_t)i));
+  /* update address */
+  k = ETHARP_HWADDR_LEN;
+  while (k > 0) {
+    k--;
+    arp_table[i].ethaddr.addr[k] = ethaddr->addr[k];
+  }
+  /* reset time stamp */
+  arp_table[i].ctime = 0;
+#if ARP_QUEUEING
+  /* this is where we will send out queued packets! */
+  while (arp_table[i].q != NULL) {
+    struct pbuf *p;
+    /* remember remainder of queue */
+    struct etharp_q_entry *q = arp_table[i].q;
+    /* pop first item off the queue */
+    arp_table[i].q = q->next;
+    /* get the packet pointer */
+    p = q->p;
+    /* now queue entry can be freed */
+    memp_free(MEMP_ARP_QUEUE, q);
+    /* send the queued IP packet */
+    etharp_send_ip(netif, p, (struct eth_addr*)(netif->hwaddr), ethaddr);
+    /* free the queued IP packet */
+    pbuf_free(p);
+  }
+#endif
+  return ERR_OK;
+}
+
+/**
+ * Finds (stable) ethernet/IP address pair from ARP table
+ * using interface and IP address index.
+ * @note the addresses in the ARP table are in network order!
+ *
+ * @param netif points to interface index
+ * @param ipaddr points to the (network order) IP address index
+ * @param eth_ret points to return pointer
+ * @param ip_ret points to return pointer
+ * @return table index if found, -1 otherwise
+ */
+s8_t
+etharp_find_addr(struct netif *netif, struct ip_addr *ipaddr,
+         struct eth_addr **eth_ret, struct ip_addr **ip_ret)
+{
+  s8_t i;
+
+  LWIP_UNUSED_ARG(netif);
+
+#if LWIP_NETIF_HWADDRHINT
+  i = find_entry(ipaddr, ETHARP_FIND_ONLY, NULL);
+#else /* LWIP_NETIF_HWADDRHINT */
+  i = find_entry(ipaddr, ETHARP_FIND_ONLY);
+#endif /* LWIP_NETIF_HWADDRHINT */
+  if((i >= 0) && arp_table[i].state == ETHARP_STATE_STABLE) {
+      *eth_ret = &arp_table[i].ethaddr;
+      *ip_ret = &arp_table[i].ipaddr;
+      return i;
+  }
+  return -1;
+}
+
+/**
+ * Updates the ARP table using the given IP packet.
+ *
+ * Uses the incoming IP packet's source address to update the
+ * ARP cache for the local network. The function does not alter
+ * or free the packet. This function must be called before the
+ * packet p is passed to the IP layer.
+ *
+ * @param netif The lwIP network interface on which the IP packet pbuf arrived.
+ * @param p The IP packet that arrived on netif.
+ *
+ * @return NULL
+ *
+ * @see pbuf_free()
+ */
+void
+etharp_ip_input(struct netif *netif, struct pbuf *p)
+{
+  struct ethip_hdr *hdr;
+  LWIP_ERROR("netif != NULL", (netif != NULL), return;);
+  /* Only insert an entry if the source IP address of the
+     incoming IP packet comes from a host on the local network. */
+  hdr = p->payload;
+  /* source is not on the local network? */
+  if (!ip_addr_netcmp(&(hdr->ip.src), &(netif->ip_addr), &(netif->netmask))) {
+    /* do nothing */
+    return;
+  }
+
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_ip_input: updating ETHARP table.\n"));
+  /* update ARP table */
+  /* @todo We could use ETHARP_TRY_HARD if we think we are going to talk
+   * back soon (for example, if the destination IP address is ours. */
+  update_arp_entry(netif, &(hdr->ip.src), &(hdr->eth.src), 0);
+}
+
+
+/**
+ * Responds to ARP requests to us. Upon ARP replies to us, add entry to cache
+ * send out queued IP packets. Updates cache with snooped address pairs.
+ *
+ * Should be called for incoming ARP packets. The pbuf in the argument
+ * is freed by this function.
+ *
+ * @param netif The lwIP network interface on which the ARP packet pbuf arrived.
+ * @param ethaddr Ethernet address of netif.
+ * @param p The ARP packet that arrived on netif. Is freed by this function.
+ *
+ * @return NULL
+ *
+ * @see pbuf_free()
+ */
+void
+etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, struct pbuf *p)
+{
+  struct etharp_hdr *hdr;
+  /* these are aligned properly, whereas the ARP header fields might not be */
+  struct ip_addr sipaddr, dipaddr;
+  u8_t i;
+  u8_t for_us;
+#if LWIP_AUTOIP
+  const u8_t * ethdst_hwaddr;
+#endif /* LWIP_AUTOIP */
+
+  LWIP_ERROR("netif != NULL", (netif != NULL), return;);
+
+  /* drop short ARP packets: we have to check for p->len instead of p->tot_len here
+     since a struct etharp_hdr is pointed to p->payload, so it musn't be chained! */
+  if (p->len < sizeof(struct etharp_hdr)) {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | 1, ("etharp_arp_input: packet dropped, too short (%"S16_F"/%"S16_F")\n", p->tot_len, (s16_t)sizeof(struct etharp_hdr)));
+    ETHARP_STATS_INC(etharp.lenerr);
+    ETHARP_STATS_INC(etharp.drop);
+    pbuf_free(p);
+    return;
+  }
+
+  hdr = p->payload;
+
+  /* RFC 826 "Packet Reception": */
+  if ((hdr->hwtype != htons(HWTYPE_ETHERNET)) ||
+      (hdr->_hwlen_protolen != htons((ETHARP_HWADDR_LEN << 8) | sizeof(struct ip_addr))) ||
+      (hdr->proto != htons(ETHTYPE_IP)) ||
+      (hdr->ethhdr.type != htons(ETHTYPE_ARP)))  {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | 1,
+      ("etharp_arp_input: packet dropped, wrong hw type, hwlen, proto, protolen or ethernet type (%"U16_F"/%"U16_F"/%"U16_F"/%"U16_F"/%"U16_F")\n",
+      hdr->hwtype, ARPH_HWLEN(hdr), hdr->proto, ARPH_PROTOLEN(hdr), hdr->ethhdr.type));
+    ETHARP_STATS_INC(etharp.proterr);
+    ETHARP_STATS_INC(etharp.drop);
+    pbuf_free(p);
+    return;
+  }
+  ETHARP_STATS_INC(etharp.recv);
+
+#if LWIP_AUTOIP
+  /* We have to check if a host already has configured our random
+   * created link local address and continously check if there is
+   * a host with this IP-address so we can detect collisions */
+  autoip_arp_reply(netif, hdr);
+#endif /* LWIP_AUTOIP */
+
+  /* Copy struct ip_addr2 to aligned ip_addr, to support compilers without
+   * structure packing (not using structure copy which breaks strict-aliasing rules). */
+  SMEMCPY(&sipaddr, &hdr->sipaddr, sizeof(sipaddr));
+  SMEMCPY(&dipaddr, &hdr->dipaddr, sizeof(dipaddr));
+
+  /* this interface is not configured? */
+  if (netif->ip_addr.addr == 0) {
+    for_us = 0;
+  } else {
+    /* ARP packet directed to us? */
+    for_us = ip_addr_cmp(&dipaddr, &(netif->ip_addr));
+  }
+
+  /* ARP message directed to us? */
+  if (for_us) {
+    /* add IP address in ARP cache; assume requester wants to talk to us.
+     * can result in directly sending the queued packets for this host. */
+    update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), ETHARP_TRY_HARD);
+  /* ARP message not directed to us? */
+  } else {
+    /* update the source IP address in the cache, if present */
+    update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), 0);
+  }
+
+  /* now act on the message itself */
+  switch (htons(hdr->opcode)) {
+  /* ARP request? */
+  case ARP_REQUEST:
+    /* ARP request. If it asked for our address, we send out a
+     * reply. In any case, we time-stamp any existing ARP entry,
+     * and possiby send out an IP packet that was queued on it. */
+
+    LWIP_DEBUGF (ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: incoming ARP request\n"));
+    /* ARP request for our address? */
+    if (for_us) {
+
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: replying to ARP request for our IP address\n"));
+      /* Re-use pbuf to send ARP reply.
+         Since we are re-using an existing pbuf, we can't call etharp_raw since
+         that would allocate a new pbuf. */
+      hdr->opcode = htons(ARP_REPLY);
+
+      hdr->dipaddr = hdr->sipaddr;
+      hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr;
+
+      LWIP_ASSERT("netif->hwaddr_len must be the same as ETHARP_HWADDR_LEN for etharp!",
+                  (netif->hwaddr_len == ETHARP_HWADDR_LEN));
+      i = ETHARP_HWADDR_LEN;
+#if LWIP_AUTOIP
+      /* If we are using Link-Local, ARP packets must be broadcast on the
+       * link layer. (See RFC3927 Section 2.5) */
+      ethdst_hwaddr = ((netif->autoip != NULL) && (netif->autoip->state != AUTOIP_STATE_OFF)) ? (u8_t*)(ethbroadcast.addr) : hdr->shwaddr.addr;
+#endif /* LWIP_AUTOIP */
+
+      while(i > 0) {
+        i--;
+        hdr->dhwaddr.addr[i] = hdr->shwaddr.addr[i];
+#if LWIP_AUTOIP
+        hdr->ethhdr.dest.addr[i] = ethdst_hwaddr[i];
+#else  /* LWIP_AUTOIP */
+        hdr->ethhdr.dest.addr[i] = hdr->shwaddr.addr[i];
+#endif /* LWIP_AUTOIP */
+        hdr->shwaddr.addr[i] = ethaddr->addr[i];
+        hdr->ethhdr.src.addr[i] = ethaddr->addr[i];
+      }
+
+      /* hwtype, hwaddr_len, proto, protolen and the type in the ethernet header
+         are already correct, we tested that before */
+
+      /* return ARP reply */
+      netif->linkoutput(netif, p);
+    /* we are not configured? */
+    } else if (netif->ip_addr.addr == 0) {
+      /* { for_us == 0 and netif->ip_addr.addr == 0 } */
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: we are unconfigured, ARP request ignored.\n"));
+    /* request was not directed to us */
+    } else {
+      /* { for_us == 0 and netif->ip_addr.addr != 0 } */
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: ARP request was not for us.\n"));
+    }
+    break;
+  case ARP_REPLY:
+    /* ARP reply. We already updated the ARP cache earlier. */
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: incoming ARP reply\n"));
+#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK)
+    /* DHCP wants to know about ARP replies from any host with an
+     * IP address also offered to us by the DHCP server. We do not
+     * want to take a duplicate IP address on a single network.
+     * @todo How should we handle redundant (fail-over) interfaces? */
+    dhcp_arp_reply(netif, &sipaddr);
+#endif
+    break;
+  default:
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: ARP unknown opcode type %"S16_F"\n", htons(hdr->opcode)));
+    ETHARP_STATS_INC(etharp.err);
+    break;
+  }
+  /* free ARP packet */
+  pbuf_free(p);
+}
+
+/**
+ * Resolve and fill-in Ethernet address header for outgoing IP packet.
+ *
+ * For IP multicast and broadcast, corresponding Ethernet addresses
+ * are selected and the packet is transmitted on the link.
+ *
+ * For unicast addresses, the packet is submitted to etharp_query(). In
+ * case the IP address is outside the local network, the IP address of
+ * the gateway is used.
+ *
+ * @param netif The lwIP network interface which the IP packet will be sent on.
+ * @param q The pbuf(s) containing the IP packet to be sent.
+ * @param ipaddr The IP address of the packet destination.
+ *
+ * @return
+ * - ERR_RTE No route to destination (no gateway to external networks),
+ * or the return type of either etharp_query() or etharp_send_ip().
+ */
+err_t
+etharp_output(struct netif *netif, struct pbuf *q, struct ip_addr *ipaddr)
+{
+  struct eth_addr *dest, mcastaddr;
+
+  /* make room for Ethernet header - should not fail */
+  if (pbuf_header(q, sizeof(struct eth_hdr)) != 0) {
+    /* bail out */
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | 2, ("etharp_output: could not allocate room for header.\n"));
+    LINK_STATS_INC(link.lenerr);
+    return ERR_BUF;
+  }
+
+  /* assume unresolved Ethernet address */
+  dest = NULL;
+  /* Determine on destination hardware address. Broadcasts and multicasts
+   * are special, other IP addresses are looked up in the ARP table. */
+
+  /* broadcast destination IP address? */
+  if (ip_addr_isbroadcast(ipaddr, netif)) {
+    /* broadcast on Ethernet also */
+    dest = (struct eth_addr *)ðbroadcast;
+  /* multicast destination IP address? */
+  } else if (ip_addr_ismulticast(ipaddr)) {
+    /* Hash IP multicast address to MAC address.*/
+    mcastaddr.addr[0] = 0x01;
+    mcastaddr.addr[1] = 0x00;
+    mcastaddr.addr[2] = 0x5e;
+    mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f;
+    mcastaddr.addr[4] = ip4_addr3(ipaddr);
+    mcastaddr.addr[5] = ip4_addr4(ipaddr);
+    /* destination Ethernet address is multicast */
+    dest = &mcastaddr;
+  /* unicast destination IP address? */
+  } else {
+    /* outside local network? */
+    if (!ip_addr_netcmp(ipaddr, &(netif->ip_addr), &(netif->netmask))) {
+      /* interface has default gateway? */
+      if (netif->gw.addr != 0) {
+        /* send to hardware address of default gateway IP address */
+        ipaddr = &(netif->gw);
+      /* no default gateway available */
+      } else {
+        /* no route to destination error (default gateway missing) */
+        return ERR_RTE;
+      }
+    }
+    /* queue on destination Ethernet address belonging to ipaddr */
+    return etharp_query(netif, ipaddr, q);
+  }
+
+  /* continuation for multicast/broadcast destinations */
+  /* obtain source Ethernet address of the given interface */
+  /* send packet directly on the link */
+  return etharp_send_ip(netif, q, (struct eth_addr*)(netif->hwaddr), dest);
+}
+
+/**
+ * Send an ARP request for the given IP address and/or queue a packet.
+ *
+ * If the IP address was not yet in the cache, a pending ARP cache entry
+ * is added and an ARP request is sent for the given address. The packet
+ * is queued on this entry.
+ *
+ * If the IP address was already pending in the cache, a new ARP request
+ * is sent for the given address. The packet is queued on this entry.
+ *
+ * If the IP address was already stable in the cache, and a packet is
+ * given, it is directly sent and no ARP request is sent out.
+ *
+ * If the IP address was already stable in the cache, and no packet is
+ * given, an ARP request is sent out.
+ *
+ * @param netif The lwIP network interface on which ipaddr
+ * must be queried for.
+ * @param ipaddr The IP address to be resolved.
+ * @param q If non-NULL, a pbuf that must be delivered to the IP address.
+ * q is not freed by this function.
+ *
+ * @note q must only be ONE packet, not a packet queue!
+ *
+ * @return
+ * - ERR_BUF Could not make room for Ethernet header.
+ * - ERR_MEM Hardware address unknown, and no more ARP entries available
+ *   to query for address or queue the packet.
+ * - ERR_MEM Could not queue packet due to memory shortage.
+ * - ERR_RTE No route to destination (no gateway to external networks).
+ * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
+ *
+ */
+err_t
+etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q)
+{
+  struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr;
+  err_t result = ERR_MEM;
+  s8_t i; /* ARP entry index */
+
+  /* non-unicast address? */
+  if (ip_addr_isbroadcast(ipaddr, netif) ||
+      ip_addr_ismulticast(ipaddr) ||
+      ip_addr_isany(ipaddr)) {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n"));
+    return ERR_ARG;
+  }
+
+  /* find entry in ARP cache, ask to create entry if queueing packet */
+#if LWIP_NETIF_HWADDRHINT
+  i = find_entry(ipaddr, ETHARP_TRY_HARD, netif);
+#else /* LWIP_NETIF_HWADDRHINT */
+  i = find_entry(ipaddr, ETHARP_TRY_HARD);
+#endif /* LWIP_NETIF_HWADDRHINT */
+
+  /* could not find or create entry? */
+  if (i < 0) {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not create ARP entry\n"));
+    if (q) {
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: packet dropped\n"));
+      ETHARP_STATS_INC(etharp.memerr);
+    }
+    return (err_t)i;
+  }
+
+  /* mark a fresh entry as pending (we just sent a request) */
+  if (arp_table[i].state == ETHARP_STATE_EMPTY) {
+    arp_table[i].state = ETHARP_STATE_PENDING;
+  }
+
+  /* { i is either a STABLE or (new or existing) PENDING entry } */
+  LWIP_ASSERT("arp_table[i].state == PENDING or STABLE",
+  ((arp_table[i].state == ETHARP_STATE_PENDING) ||
+   (arp_table[i].state == ETHARP_STATE_STABLE)));
+
+  /* do we have a pending entry? or an implicit query request? */
+  if ((arp_table[i].state == ETHARP_STATE_PENDING) || (q == NULL)) {
+    /* try to resolve it; send out ARP request */
+    result = etharp_request(netif, ipaddr);
+    if (result != ERR_OK) {
+      /* ARP request couldn't be sent */
+      /* We don't re-send arp request in etharp_tmr, but we still queue packets,
+         since this failure could be temporary, and the next packet calling
+         etharp_query again could lead to sending the queued packets. */
+    }
+  }
+
+  /* packet given? */
+  if (q != NULL) {
+    /* stable entry? */
+    if (arp_table[i].state == ETHARP_STATE_STABLE) {
+      /* we have a valid IP->Ethernet address mapping */
+      /* send the packet */
+      result = etharp_send_ip(netif, q, srcaddr, &(arp_table[i].ethaddr));
+    /* pending entry? (either just created or already pending */
+    } else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+#if ARP_QUEUEING /* queue the given q packet */
+      struct pbuf *p;
+      int copy_needed = 0;
+      /* IF q includes a PBUF_REF, PBUF_POOL or PBUF_RAM, we have no choice but
+       * to copy the whole queue into a new PBUF_RAM (see bug #11400)
+       * PBUF_ROMs can be left as they are, since ROM must not get changed. */
+      p = q;
+      while (p) {
+        LWIP_ASSERT("no packet queues allowed!", (p->len != p->tot_len) || (p->next == 0));
+        if(p->type != PBUF_ROM) {
+          copy_needed = 1;
+          break;
+        }
+        p = p->next;
+      }
+      if(copy_needed) {
+        /* copy the whole packet into new pbufs */
+        p = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
+        if(p != NULL) {
+          if (pbuf_copy(p, q) != ERR_OK) {
+            pbuf_free(p);
+            p = NULL;
+          }
+        }
+      } else {
+        /* referencing the old pbuf is enough */
+        p = q;
+        pbuf_ref(p);
+      }
+      /* packet could be taken over? */
+      if (p != NULL) {
+        /* queue packet ... */
+        struct etharp_q_entry *new_entry;
+        /* allocate a new arp queue entry */
+        new_entry = memp_malloc(MEMP_ARP_QUEUE);
+        if (new_entry != NULL) {
+          new_entry->next = 0;
+          new_entry->p = p;
+          if(arp_table[i].q != NULL) {
+            /* queue was already existent, append the new entry to the end */
+            struct etharp_q_entry *r;
+            r = arp_table[i].q;
+            while (r->next != NULL) {
+              r = r->next;
+            }
+            r->next = new_entry;
+          } else {
+            /* queue did not exist, first item in queue */
+            arp_table[i].q = new_entry;
+          }
+          LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"S16_F"\n", (void *)q, (s16_t)i));
+          result = ERR_OK;
+        } else {
+          /* the pool MEMP_ARP_QUEUE is empty */
+          pbuf_free(p);
+          LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
+          /* { result == ERR_MEM } through initialization */
+        }
+      } else {
+        ETHARP_STATS_INC(etharp.memerr);
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
+        /* { result == ERR_MEM } through initialization */
+      }
+#else /* ARP_QUEUEING == 0 */
+      /* q && state == PENDING && ARP_QUEUEING == 0 => result = ERR_MEM */
+      /* { result == ERR_MEM } through initialization */
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: Ethernet destination address unknown, queueing disabled, packet %p dropped\n", (void *)q));
+#endif
+    }
+  }
+  return result;
+}
+
+/**
+ * Send a raw ARP packet (opcode and all addresses can be modified)
+ *
+ * @param netif the lwip network interface on which to send the ARP packet
+ * @param ethsrc_addr the source MAC address for the ethernet header
+ * @param ethdst_addr the destination MAC address for the ethernet header
+ * @param hwsrc_addr the source MAC address for the ARP protocol header
+ * @param ipsrc_addr the source IP address for the ARP protocol header
+ * @param hwdst_addr the destination MAC address for the ARP protocol header
+ * @param ipdst_addr the destination IP address for the ARP protocol header
+ * @param opcode the type of the ARP packet
+ * @return ERR_OK if the ARP packet has been sent
+ *         ERR_MEM if the ARP packet couldn't be allocated
+ *         any other err_t on failure
+ */
+#if !LWIP_AUTOIP
+static
+#endif /* LWIP_AUTOIP */
+err_t
+etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr,
+           const struct eth_addr *ethdst_addr,
+           const struct eth_addr *hwsrc_addr, const struct ip_addr *ipsrc_addr,
+           const struct eth_addr *hwdst_addr, const struct ip_addr *ipdst_addr,
+           const u16_t opcode)
+{
+  struct pbuf *p;
+  err_t result = ERR_OK;
+  u8_t k; /* ARP entry index */
+  struct etharp_hdr *hdr;
+#if LWIP_AUTOIP
+  const u8_t * ethdst_hwaddr;
+#endif /* LWIP_AUTOIP */
+
+  /* allocate a pbuf for the outgoing ARP request packet */
+  p = pbuf_alloc(PBUF_LINK, sizeof(struct etharp_hdr), PBUF_RAM);
+  /* could allocate a pbuf for an ARP request? */
+  if (p == NULL) {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | 2, ("etharp_raw: could not allocate pbuf for ARP request.\n"));
+    ETHARP_STATS_INC(etharp.memerr);
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("check that first pbuf can hold struct etharp_hdr",
+              (p->len >= sizeof(struct etharp_hdr)));
+
+  hdr = p->payload;
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_raw: sending raw ARP packet.\n"));
+  hdr->opcode = htons(opcode);
+
+  LWIP_ASSERT("netif->hwaddr_len must be the same as ETHARP_HWADDR_LEN for etharp!",
+              (netif->hwaddr_len == ETHARP_HWADDR_LEN));
+  k = ETHARP_HWADDR_LEN;
+#if LWIP_AUTOIP
+  /* If we are using Link-Local, ARP packets must be broadcast on the
+   * link layer. (See RFC3927 Section 2.5) */
+  ethdst_hwaddr = ((netif->autoip != NULL) && (netif->autoip->state != AUTOIP_STATE_OFF)) ? (u8_t*)(ethbroadcast.addr) : ethdst_addr->addr;
+#endif /* LWIP_AUTOIP */
+  /* Write MAC-Addresses (combined loop for both headers) */
+  while(k > 0) {
+    k--;
+    /* Write the ARP MAC-Addresses */
+    hdr->shwaddr.addr[k] = hwsrc_addr->addr[k];
+    hdr->dhwaddr.addr[k] = hwdst_addr->addr[k];
+    /* Write the Ethernet MAC-Addresses */
+#if LWIP_AUTOIP
+    hdr->ethhdr.dest.addr[k] = ethdst_hwaddr[k];
+#else  /* LWIP_AUTOIP */
+    hdr->ethhdr.dest.addr[k] = ethdst_addr->addr[k];
+#endif /* LWIP_AUTOIP */
+    hdr->ethhdr.src.addr[k]  = ethsrc_addr->addr[k];
+  }
+  hdr->sipaddr = *(struct ip_addr2 *)ipsrc_addr;
+  hdr->dipaddr = *(struct ip_addr2 *)ipdst_addr;
+
+  hdr->hwtype = htons(HWTYPE_ETHERNET);
+  hdr->proto = htons(ETHTYPE_IP);
+  /* set hwlen and protolen together */
+  hdr->_hwlen_protolen = htons((ETHARP_HWADDR_LEN << 8) | sizeof(struct ip_addr));
+
+  hdr->ethhdr.type = htons(ETHTYPE_ARP);
+  /* send ARP query */
+  result = netif->linkoutput(netif, p);
+  ETHARP_STATS_INC(etharp.xmit);
+  /* free ARP query packet */
+  pbuf_free(p);
+  p = NULL;
+  /* could not allocate pbuf for ARP request */
+
+  return result;
+}
+
+/**
+ * Send an ARP request packet asking for ipaddr.
+ *
+ * @param netif the lwip network interface on which to send the request
+ * @param ipaddr the IP address for which to ask
+ * @return ERR_OK if the request has been sent
+ *         ERR_MEM if the ARP packet couldn't be allocated
+ *         any other err_t on failure
+ */
+err_t
+etharp_request(struct netif *netif, struct ip_addr *ipaddr)
+{
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_request: sending ARP request.\n"));
+  return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, ðbroadcast,
+                    (struct eth_addr *)netif->hwaddr, &netif->ip_addr, ðzero,
+                    ipaddr, ARP_REQUEST);
+}
+
+/**
+ * Process received ethernet frames. Using this function instead of directly
+ * calling ip_input and passing ARP frames through etharp in ethernetif_input,
+ * the ARP cache is protected from concurrent access.
+ *
+ * @param p the recevied packet, p->payload pointing to the ethernet header
+ * @param netif the network interface on which the packet was received
+ */
+err_t
+ethernet_input(struct pbuf *p, struct netif *netif)
+{
+  struct eth_hdr* ethhdr;
+
+  /* points to packet payload, which starts with an Ethernet header */
+  ethhdr = p->payload;
+
+  switch (htons(ethhdr->type)) {
+    /* IP packet? */
+    case ETHTYPE_IP:
+#if ETHARP_TRUST_IP_MAC
+      /* update ARP table */
+      etharp_ip_input(netif, p);
+#endif /* ETHARP_TRUST_IP_MAC */
+      /* skip Ethernet header */
+      if(pbuf_header(p, -(s16_t)sizeof(struct eth_hdr))) {
+        LWIP_ASSERT("Can't move over header in packet", 0);
+        pbuf_free(p);
+        p = NULL;
+      } else {
+        /* pass to IP layer */
+        ip_input(p, netif);
+      }
+      break;
+
+    case ETHTYPE_ARP:
+      /* pass p to ARP module */
+      etharp_arp_input(netif, (struct eth_addr*)(netif->hwaddr), p);
+      break;
+
+#if PPPOE_SUPPORT
+    case ETHTYPE_PPPOEDISC: /* PPP Over Ethernet Discovery Stage */
+      pppoe_disc_input(netif, p);
+      break;
+
+    case ETHTYPE_PPPOE: /* PPP Over Ethernet Session Stage */
+      pppoe_data_input(netif, p);
+      break;
+#endif /* PPPOE_SUPPORT */
+
+    default:
+      pbuf_free(p);
+      p = NULL;
+      break;
+  }
+
+  /* This means the pbuf is freed or consumed,
+     so the caller doesn't have to free it again */
+  return ERR_OK;
+}
+#endif /* LWIP_ARP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ethernetif.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ethernetif.c
new file mode 100644
index 0000000..58b879d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ethernetif.c
@@ -0,0 +1,313 @@
+/**
+ * @file
+ * Ethernet Interface Skeleton
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+/*
+ * This file is a skeleton for developing Ethernet network interface
+ * drivers for lwIP. Add code to the low_level functions and do a
+ * search-and-replace for the word "ethernetif" to replace it with
+ * something that better describes your network interface.
+ */
+
+#include "lwip/opt.h"
+
+#if 0 /* don't build, this is only a skeleton, see previous comment */
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include 
+#include 
+#include "netif/etharp.h"
+#include "netif/ppp_oe.h"
+
+/* Define those to better describe your network interface. */
+#define IFNAME0 'e'
+#define IFNAME1 'n'
+
+/**
+ * Helper struct to hold private data used to operate your ethernet interface.
+ * Keeping the ethernet address of the MAC in this struct is not necessary
+ * as it is already kept in the struct netif.
+ * But this is only an example, anyway...
+ */
+struct ethernetif {
+  struct eth_addr *ethaddr;
+  /* Add whatever per-interface state that is needed here. */
+};
+
+/* Forward declarations. */
+static void  ethernetif_input(struct netif *netif);
+
+/**
+ * In this function, the hardware should be initialized.
+ * Called from ethernetif_init().
+ *
+ * @param netif the already initialized lwip network interface structure
+ *        for this ethernetif
+ */
+static void
+low_level_init(struct netif *netif)
+{
+  struct ethernetif *ethernetif = netif->state;
+  
+  /* set MAC hardware address length */
+  netif->hwaddr_len = ETHARP_HWADDR_LEN;
+
+  /* set MAC hardware address */
+  netif->hwaddr[0] = ;
+  ...
+  netif->hwaddr[5] = ;
+
+  /* maximum transfer unit */
+  netif->mtu = 1500;
+  
+  /* device capabilities */
+  /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
+  netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
+ 
+  /* Do whatever else is needed to initialize interface. */  
+}
+
+/**
+ * This function should do the actual transmission of the packet. The packet is
+ * contained in the pbuf that is passed to the function. This pbuf
+ * might be chained.
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)
+ * @return ERR_OK if the packet could be sent
+ *         an err_t value if the packet couldn't be sent
+ *
+ * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to
+ *       strange results. You might consider waiting for space in the DMA queue
+ *       to become availale since the stack doesn't retry to send a packet
+ *       dropped because of memory failure (except for the TCP timers).
+ */
+
+static err_t
+low_level_output(struct netif *netif, struct pbuf *p)
+{
+  struct ethernetif *ethernetif = netif->state;
+  struct pbuf *q;
+
+  initiate transfer();
+  
+#if ETH_PAD_SIZE
+  pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
+#endif
+
+  for(q = p; q != NULL; q = q->next) {
+    /* Send the data from the pbuf to the interface, one pbuf at a
+       time. The size of the data in each pbuf is kept in the ->len
+       variable. */
+    send data from(q->payload, q->len);
+  }
+
+  signal that packet should be sent();
+
+#if ETH_PAD_SIZE
+  pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
+#endif
+  
+  LINK_STATS_INC(link.xmit);
+
+  return ERR_OK;
+}
+
+/**
+ * Should allocate a pbuf and transfer the bytes of the incoming
+ * packet from the interface into the pbuf.
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ * @return a pbuf filled with the received packet (including MAC header)
+ *         NULL on memory error
+ */
+static struct pbuf *
+low_level_input(struct netif *netif)
+{
+  struct ethernetif *ethernetif = netif->state;
+  struct pbuf *p, *q;
+  u16_t len;
+
+  /* Obtain the size of the packet and put it into the "len"
+     variable. */
+  len = ;
+
+#if ETH_PAD_SIZE
+  len += ETH_PAD_SIZE; /* allow room for Ethernet padding */
+#endif
+
+  /* We allocate a pbuf chain of pbufs from the pool. */
+  p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
+  
+  if (p != NULL) {
+
+#if ETH_PAD_SIZE
+    pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
+#endif
+
+    /* We iterate over the pbuf chain until we have read the entire
+     * packet into the pbuf. */
+    for(q = p; q != NULL; q = q->next) {
+      /* Read enough bytes to fill this pbuf in the chain. The
+       * available data in the pbuf is given by the q->len
+       * variable. */
+      read data into(q->payload, q->len);
+    }
+    acknowledge that packet has been read();
+
+#if ETH_PAD_SIZE
+    pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
+#endif
+
+    LINK_STATS_INC(link.recv);
+  } else {
+    drop packet();
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.drop);
+  }
+
+  return p;  
+}
+
+/**
+ * This function should be called when a packet is ready to be read
+ * from the interface. It uses the function low_level_input() that
+ * should handle the actual reception of bytes from the network
+ * interface. Then the type of the received packet is determined and
+ * the appropriate input function is called.
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ */
+static void
+ethernetif_input(struct netif *netif)
+{
+  struct ethernetif *ethernetif;
+  struct eth_hdr *ethhdr;
+  struct pbuf *p;
+
+  ethernetif = netif->state;
+
+  /* move received packet into a new pbuf */
+  p = low_level_input(netif);
+  /* no packet could be read, silently ignore this */
+  if (p == NULL) return;
+  /* points to packet payload, which starts with an Ethernet header */
+  ethhdr = p->payload;
+
+  switch (htons(ethhdr->type)) {
+  /* IP or ARP packet? */
+  case ETHTYPE_IP:
+  case ETHTYPE_ARP:
+#if PPPOE_SUPPORT
+  /* PPPoE packet? */
+  case ETHTYPE_PPPOEDISC:
+  case ETHTYPE_PPPOE:
+#endif /* PPPOE_SUPPORT */
+    /* full packet send to tcpip_thread to process */
+    if (netif->input(p, netif)!=ERR_OK)
+     { LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n"));
+       pbuf_free(p);
+       p = NULL;
+     }
+    break;
+
+  default:
+    pbuf_free(p);
+    p = NULL;
+    break;
+  }
+}
+
+/**
+ * Should be called at the beginning of the program to set up the
+ * network interface. It calls the function low_level_init() to do the
+ * actual setup of the hardware.
+ *
+ * This function should be passed as a parameter to netif_add().
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ * @return ERR_OK if the loopif is initialized
+ *         ERR_MEM if private data couldn't be allocated
+ *         any other err_t on error
+ */
+err_t
+ethernetif_init(struct netif *netif)
+{
+  struct ethernetif *ethernetif;
+
+  LWIP_ASSERT("netif != NULL", (netif != NULL));
+    
+  ethernetif = mem_malloc(sizeof(struct ethernetif));
+  if (ethernetif == NULL) {
+    LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n"));
+    return ERR_MEM;
+  }
+
+#if LWIP_NETIF_HOSTNAME
+  /* Initialize interface hostname */
+  netif->hostname = "lwip";
+#endif /* LWIP_NETIF_HOSTNAME */
+
+  /*
+   * Initialize the snmp variables and counters inside the struct netif.
+   * The last argument should be replaced with your link speed, in units
+   * of bits per second.
+   */
+  NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, ???);
+
+  netif->state = ethernetif;
+  netif->name[0] = IFNAME0;
+  netif->name[1] = IFNAME1;
+  /* We directly use etharp_output() here to save a function call.
+   * You can instead declare your own function an call etharp_output()
+   * from it if you have to do some checks before sending (e.g. if link
+   * is available...) */
+  netif->output = etharp_output;
+  netif->linkoutput = low_level_output;
+  
+  ethernetif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]);
+  
+  /* initialize the hardware */
+  low_level_init(netif);
+
+  return ERR_OK;
+}
+
+#endif /* 0 */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/loopif.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/loopif.c
new file mode 100644
index 0000000..a84c842
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/loopif.c
@@ -0,0 +1,217 @@
+/**
+ * @file
+ * Loop Interface
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#include "lwip/opt.h"
+
+#if LWIP_HAVE_LOOPIF
+
+#include "netif/loopif.h"
+#include "lwip/pbuf.h"
+#include "lwip/snmp.h"
+
+#include 
+
+#if !LWIP_LOOPIF_MULTITHREADING
+
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+
+/* helper struct for the linked list of pbufs */
+struct loopif_private {
+  struct pbuf *first;
+  struct pbuf *last;
+};
+
+/**
+ * Call loopif_poll() in the main loop of your application. This is to prevent
+ * reentering non-reentrant functions like tcp_input(). Packets passed to
+ * loopif_output() are put on a list that is passed to netif->input() by
+ * loopif_poll().
+ *
+ * @param netif the lwip network interface structure for this loopif
+ */
+void
+loopif_poll(struct netif *netif)
+{
+  SYS_ARCH_DECL_PROTECT(lev);
+  struct pbuf *in, *in_end;
+  struct loopif_private *priv = (struct loopif_private*)netif->state;
+
+  LWIP_ERROR("priv != NULL", (priv != NULL), return;);
+
+  do {
+    /* Get a packet from the list. With SYS_LIGHTWEIGHT_PROT=1, this is protected */
+    SYS_ARCH_PROTECT(lev);
+    in = priv->first;
+    if(in) {
+      in_end = in;
+      while(in_end->len != in_end->tot_len) {
+        LWIP_ASSERT("bogus pbuf: len != tot_len but next == NULL!", in_end->next != NULL);
+        in_end = in_end->next;
+      }
+      /* 'in_end' now points to the last pbuf from 'in' */
+      if(in_end == priv->last) {
+        /* this was the last pbuf in the list */
+        priv->first = priv->last = NULL;
+      } else {
+        /* pop the pbuf off the list */
+        priv->first = in_end->next;
+        LWIP_ASSERT("should not be null since first != last!", priv->first != NULL);
+      }
+    }
+    SYS_ARCH_UNPROTECT(lev);
+  
+    if(in != NULL) {
+      if(in_end->next != NULL) {
+        /* De-queue the pbuf from its successors on the 'priv' list. */
+        in_end->next = NULL;
+      }
+      if(netif->input(in, netif) != ERR_OK) {
+        pbuf_free(in);
+      }
+      /* Don't reference the packet any more! */
+      in = NULL;
+      in_end = NULL;
+    }
+  /* go on while there is a packet on the list */
+  } while(priv->first != NULL);
+}
+#endif /* LWIP_LOOPIF_MULTITHREADING */
+
+/**
+ * Send an IP packet over the loopback interface.
+ * The pbuf is simply copied and handed back to netif->input.
+ * In multithreaded mode, this is done directly since netif->input must put
+ * the packet on a queue.
+ * In callback mode, the packet is put on an internal queue and is fed to
+ * netif->input by loopif_poll().
+ *
+ * @param netif the lwip network interface structure for this loopif
+ * @param p the (IP) packet to 'send'
+ * @param ipaddr the ip address to send the packet to (not used for loopif)
+ * @return ERR_OK if the packet has been sent
+ *         ERR_MEM if the pbuf used to copy the packet couldn't be allocated
+ */
+static err_t
+loopif_output(struct netif *netif, struct pbuf *p,
+       struct ip_addr *ipaddr)
+{
+#if !LWIP_LOOPIF_MULTITHREADING
+  SYS_ARCH_DECL_PROTECT(lev);
+  struct loopif_private *priv;
+  struct pbuf *last;
+#endif /* LWIP_LOOPIF_MULTITHREADING */
+  struct pbuf *r;
+  err_t err;
+
+  LWIP_UNUSED_ARG(ipaddr);
+
+  /* Allocate a new pbuf */
+  r = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
+  if (r == NULL) {
+    return ERR_MEM;
+  }
+
+  /* Copy the whole pbuf queue p into the single pbuf r */
+  if ((err = pbuf_copy(r, p)) != ERR_OK) {
+    pbuf_free(r);
+    r = NULL;
+    return err;
+  }
+
+#if LWIP_LOOPIF_MULTITHREADING
+  /* Multithreading environment, netif->input() is supposed to put the packet
+     into a mailbox, so we can safely call it here without risking to re-enter
+     functions that are not reentrant (TCP!!!) */
+  if(netif->input(r, netif) != ERR_OK) {
+    pbuf_free(r);
+    r = NULL;
+  }
+#else /* LWIP_LOOPIF_MULTITHREADING */
+  /* Raw API without threads: put the packet on a linked list which gets emptied
+     through calling loopif_poll(). */
+  priv = (struct loopif_private*)netif->state;
+
+  /* let last point to the last pbuf in chain r */
+  for (last = r; last->next != NULL; last = last->next);
+  SYS_ARCH_PROTECT(lev);
+  if(priv->first != NULL) {
+    LWIP_ASSERT("if first != NULL, last must also be != NULL", priv->last != NULL);
+    priv->last->next = r;
+    priv->last = last;
+  } else {
+    priv->first = r;
+    priv->last = last;
+  }
+  SYS_ARCH_UNPROTECT(lev);
+#endif /* LWIP_LOOPIF_MULTITHREADING */
+
+  return ERR_OK;    
+}
+
+/**
+ * Initialize a lwip network interface structure for a loopback interface
+ *
+ * @param netif the lwip network interface structure for this loopif
+ * @return ERR_OK if the loopif is initialized
+ *         ERR_MEM if private data couldn't be allocated
+ */
+err_t
+loopif_init(struct netif *netif)
+{
+#if !LWIP_LOOPIF_MULTITHREADING
+  struct loopif_private *priv;
+
+  priv = (struct loopif_private*)mem_malloc(sizeof(struct loopif_private));
+  if(priv == NULL) 
+    return ERR_MEM;
+  priv->first = priv->last = NULL;
+  netif->state = priv;
+#endif /* LWIP_LOOPIF_MULTITHREADING */
+
+  /* initialize the snmp variables and counters inside the struct netif
+   * ifSpeed: no assumption can be made!
+   */
+  NETIF_INIT_SNMP(netif, snmp_ifType_softwareLoopback, 0);
+
+  netif->name[0] = 'l';
+  netif->name[1] = 'o';
+  netif->output = loopif_output;
+  return ERR_OK;
+}
+
+#endif /* LWIP_HAVE_LOOPIF */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/auth.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/auth.c
new file mode 100644
index 0000000..c637c2d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/auth.c
@@ -0,0 +1,988 @@
+/*****************************************************************************
+* auth.c - Network Authentication and Phase Control program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 by Global Election Systems Inc.  All rights reserved.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-08 Guy Lancaster , Global Election Systems Inc.
+*   Ported from public pppd code.
+*****************************************************************************/
+/*
+ * auth.c - PPP authentication and phase control.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University.  The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "fsm.h"
+#include "lcp.h"
+#include "pap.h"
+#include "chap.h"
+#include "auth.h"
+#include "ipcp.h"
+
+#if CBCP_SUPPORT
+#include "cbcp.h"
+#endif /* CBCP_SUPPORT */
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+/* Bits in auth_pending[] */
+#define PAP_WITHPEER    1
+#define PAP_PEER        2
+#define CHAP_WITHPEER   4
+#define CHAP_PEER       8
+
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+/* Used for storing a sequence of words.  Usually malloced. */
+struct wordlist {
+  struct wordlist *next;
+  char        word[1];
+};
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+extern char *crypt (const char *, const char *);
+
+/* Prototypes for procedures local to this file. */
+
+static void network_phase (int);
+static void check_idle (void *);
+static void connect_time_expired (void *);
+#if 0
+static int  login (char *, char *, char **, int *);
+#endif
+static void logout (void);
+static int  null_login (int);
+static int  get_pap_passwd (int, char *, char *);
+static int  have_pap_secret (void);
+static int  have_chap_secret (char *, char *, u32_t);
+static int  ip_addr_check (u32_t, struct wordlist *);
+#if 0 /* PAP_SUPPORT || CHAP_SUPPORT */
+static void set_allowed_addrs(int unit, struct wordlist *addrs);
+static void free_wordlist (struct wordlist *);
+#endif /* 0 */ /* PAP_SUPPORT || CHAP_SUPPORT */
+#if CBCP_SUPPORT
+static void callback_phase (int);
+#endif /* CBCP_SUPPORT */
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+#if PAP_SUPPORT || CHAP_SUPPORT
+/* The name by which the peer authenticated itself to us. */
+static char peer_authname[MAXNAMELEN];
+#endif /* PAP_SUPPORT || CHAP_SUPPORT */
+
+/* Records which authentication operations haven't completed yet. */
+static int auth_pending[NUM_PPP];
+
+/* Set if we have successfully called login() */
+static int logged_in;
+
+/* Set if we have run the /etc/ppp/auth-up script. */
+static int did_authup;
+
+/* List of addresses which the peer may use. */
+static struct wordlist *addresses[NUM_PPP];
+
+/* Number of network protocols which we have opened. */
+static int num_np_open;
+
+/* Number of network protocols which have come up. */
+static int num_np_up;
+
+#if PAP_SUPPORT || CHAP_SUPPORT
+/* Set if we got the contents of passwd[] from the pap-secrets file. */
+static int passwd_from_file;
+#endif /* PAP_SUPPORT || CHAP_SUPPORT */
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * An Open on LCP has requested a change from Dead to Establish phase.
+ * Do what's necessary to bring the physical layer up.
+ */
+void
+link_required(int unit)
+{
+  LWIP_UNUSED_ARG(unit);
+
+  AUTHDEBUG((LOG_INFO, "link_required: %d\n", unit));
+}
+
+/*
+ * LCP has terminated the link; go to the Dead phase and take the
+ * physical layer down.
+ */
+void
+link_terminated(int unit)
+{
+  AUTHDEBUG((LOG_INFO, "link_terminated: %d\n", unit));
+  if (lcp_phase[unit] == PHASE_DEAD) {
+    return;
+  }
+  if (logged_in) {
+    logout();
+  }
+  lcp_phase[unit] = PHASE_DEAD;
+  AUTHDEBUG((LOG_NOTICE, "Connection terminated.\n"));
+  pppLinkTerminated(unit);
+}
+
+/*
+ * LCP has gone down; it will either die or try to re-establish.
+ */
+void
+link_down(int unit)
+{
+  int i;
+  struct protent *protp;
+  
+  AUTHDEBUG((LOG_INFO, "link_down: %d\n", unit));
+  if (did_authup) {
+    /* XXX Do link down processing. */
+    did_authup = 0;
+  }
+  for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+    if (!protp->enabled_flag) {
+      continue;
+    }
+    if (protp->protocol != PPP_LCP && protp->lowerdown != NULL) {
+      (*protp->lowerdown)(unit);
+    }
+    if (protp->protocol < 0xC000 && protp->close != NULL) {
+      (*protp->close)(unit, "LCP down");
+    }
+  }
+  num_np_open = 0;
+  num_np_up = 0;
+  if (lcp_phase[unit] != PHASE_DEAD) {
+    lcp_phase[unit] = PHASE_TERMINATE;
+  }
+  pppLinkDown(unit);
+}
+
+/*
+ * The link is established.
+ * Proceed to the Dead, Authenticate or Network phase as appropriate.
+ */
+void
+link_established(int unit)
+{
+  int auth;
+  int i;
+  struct protent *protp;
+  lcp_options *wo = &lcp_wantoptions[unit];
+  lcp_options *go = &lcp_gotoptions[unit];
+#if PAP_SUPPORT || CHAP_SUPPORT
+  lcp_options *ho = &lcp_hisoptions[unit];
+#endif /* PAP_SUPPORT || CHAP_SUPPORT */
+
+  AUTHDEBUG((LOG_INFO, "link_established: %d\n", unit));
+  /*
+   * Tell higher-level protocols that LCP is up.
+   */
+  for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+    if (protp->protocol != PPP_LCP && protp->enabled_flag && protp->lowerup != NULL) {
+      (*protp->lowerup)(unit);
+    }
+  }
+  if (ppp_settings.auth_required && !(go->neg_chap || go->neg_upap)) {
+    /*
+     * We wanted the peer to authenticate itself, and it refused:
+     * treat it as though it authenticated with PAP using a username
+     * of "" and a password of "".  If that's not OK, boot it out.
+     */
+    if (!wo->neg_upap || !null_login(unit)) {
+      AUTHDEBUG((LOG_WARNING, "peer refused to authenticate\n"));
+      lcp_close(unit, "peer refused to authenticate");
+      return;
+    }
+  }
+    
+  lcp_phase[unit] = PHASE_AUTHENTICATE;
+  auth = 0;
+#if CHAP_SUPPORT
+  if (go->neg_chap) {
+    ChapAuthPeer(unit, ppp_settings.our_name, go->chap_mdtype);
+    auth |= CHAP_PEER;
+  } 
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT && CHAP_SUPPORT
+  else
+#endif /* PAP_SUPPORT && CHAP_SUPPORT */
+#if PAP_SUPPORT
+  if (go->neg_upap) {
+    upap_authpeer(unit);
+    auth |= PAP_PEER;
+  }
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+  if (ho->neg_chap) {
+    ChapAuthWithPeer(unit, ppp_settings.user, ho->chap_mdtype);
+    auth |= CHAP_WITHPEER;
+  }
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT && CHAP_SUPPORT
+  else
+#endif /* PAP_SUPPORT && CHAP_SUPPORT */
+#if PAP_SUPPORT
+  if (ho->neg_upap) {
+    if (ppp_settings.passwd[0] == 0) {
+      passwd_from_file = 1;
+      if (!get_pap_passwd(unit, ppp_settings.user, ppp_settings.passwd)) {
+        AUTHDEBUG((LOG_ERR, "No secret found for PAP login\n"));
+      }
+    }
+    upap_authwithpeer(unit, ppp_settings.user, ppp_settings.passwd);
+    auth |= PAP_WITHPEER;
+  }
+#endif /* PAP_SUPPORT */
+  auth_pending[unit] = auth;
+
+  if (!auth) {
+    network_phase(unit);
+  }
+}
+
+/*
+ * The peer has failed to authenticate himself using `protocol'.
+ */
+void
+auth_peer_fail(int unit, u16_t protocol)
+{
+  LWIP_UNUSED_ARG(protocol);
+
+  AUTHDEBUG((LOG_INFO, "auth_peer_fail: %d proto=%X\n", unit, protocol));
+  /*
+   * Authentication failure: take the link down
+   */
+  lcp_close(unit, "Authentication failed");
+}
+
+
+#if PAP_SUPPORT || CHAP_SUPPORT
+/*
+ * The peer has been successfully authenticated using `protocol'.
+ */
+void
+auth_peer_success(int unit, u16_t protocol, char *name, int namelen)
+{
+  int pbit;
+  
+  AUTHDEBUG((LOG_INFO, "auth_peer_success: %d proto=%X\n", unit, protocol));
+  switch (protocol) {
+    case PPP_CHAP:
+      pbit = CHAP_PEER;
+      break;
+    case PPP_PAP:
+      pbit = PAP_PEER;
+      break;
+    default:
+      AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n", protocol));
+      return;
+  }
+  
+  /*
+   * Save the authenticated name of the peer for later.
+   */
+  if (namelen > sizeof(peer_authname) - 1) {
+    namelen = sizeof(peer_authname) - 1;
+  }
+  BCOPY(name, peer_authname, namelen);
+  peer_authname[namelen] = 0;
+  
+  /*
+   * If there is no more authentication still to be done,
+   * proceed to the network (or callback) phase.
+   */
+  if ((auth_pending[unit] &= ~pbit) == 0) {
+    network_phase(unit);
+  }
+}
+
+/*
+ * We have failed to authenticate ourselves to the peer using `protocol'.
+ */
+void
+auth_withpeer_fail(int unit, u16_t protocol)
+{
+  int errCode = PPPERR_AUTHFAIL;
+  
+  LWIP_UNUSED_ARG(protocol);
+
+  AUTHDEBUG((LOG_INFO, "auth_withpeer_fail: %d proto=%X\n", unit, protocol));
+  if (passwd_from_file) {
+    BZERO(ppp_settings.passwd, MAXSECRETLEN);
+  }
+  /* 
+   * XXX Warning: the unit number indicates the interface which is
+   * not necessarily the PPP connection.  It works here as long
+   * as we are only supporting PPP interfaces.
+   */
+  pppIOCtl(unit, PPPCTLS_ERRCODE, &errCode);
+
+  /*
+   * We've failed to authenticate ourselves to our peer.
+   * He'll probably take the link down, and there's not much
+   * we can do except wait for that.
+   */
+}
+
+/*
+ * We have successfully authenticated ourselves with the peer using `protocol'.
+ */
+void
+auth_withpeer_success(int unit, u16_t protocol)
+{
+  int pbit;
+  
+  AUTHDEBUG((LOG_INFO, "auth_withpeer_success: %d proto=%X\n", unit, protocol));
+  switch (protocol) {
+    case PPP_CHAP:
+      pbit = CHAP_WITHPEER;
+      break;
+    case PPP_PAP:
+      if (passwd_from_file) {
+        BZERO(ppp_settings.passwd, MAXSECRETLEN);
+      }
+      pbit = PAP_WITHPEER;
+      break;
+    default:
+      AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n", protocol));
+      pbit = 0;
+  }
+  
+  /*
+   * If there is no more authentication still being done,
+   * proceed to the network (or callback) phase.
+   */
+  if ((auth_pending[unit] &= ~pbit) == 0) {
+    network_phase(unit);
+  }
+}
+#endif /* PAP_SUPPORT || CHAP_SUPPORT */
+
+
+/*
+ * np_up - a network protocol has come up.
+ */
+void
+np_up(int unit, u16_t proto)
+{
+  LWIP_UNUSED_ARG(unit);
+  LWIP_UNUSED_ARG(proto);
+
+  AUTHDEBUG((LOG_INFO, "np_up: %d proto=%X\n", unit, proto));
+  if (num_np_up == 0) {
+    AUTHDEBUG((LOG_INFO, "np_up: maxconnect=%d idle_time_limit=%d\n",ppp_settings.maxconnect,ppp_settings.idle_time_limit));
+    /*
+     * At this point we consider that the link has come up successfully.
+     */
+    if (ppp_settings.idle_time_limit > 0) {
+      TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit);
+    }
+    
+    /*
+     * Set a timeout to close the connection once the maximum
+     * connect time has expired.
+     */
+    if (ppp_settings.maxconnect > 0) {
+      TIMEOUT(connect_time_expired, 0, ppp_settings.maxconnect);
+    }
+  }
+  ++num_np_up;
+}
+
+/*
+ * np_down - a network protocol has gone down.
+ */
+void
+np_down(int unit, u16_t proto)
+{
+  LWIP_UNUSED_ARG(unit);
+  LWIP_UNUSED_ARG(proto);
+
+  AUTHDEBUG((LOG_INFO, "np_down: %d proto=%X\n", unit, proto));
+  if (--num_np_up == 0 && ppp_settings.idle_time_limit > 0) {
+    UNTIMEOUT(check_idle, NULL);
+  }
+}
+
+/*
+ * np_finished - a network protocol has finished using the link.
+ */
+void
+np_finished(int unit, u16_t proto)
+{
+  LWIP_UNUSED_ARG(unit);
+  LWIP_UNUSED_ARG(proto);
+
+  AUTHDEBUG((LOG_INFO, "np_finished: %d proto=%X\n", unit, proto));
+  if (--num_np_open <= 0) {
+    /* no further use for the link: shut up shop. */
+    lcp_close(0, "No network protocols running");
+  }
+}
+
+/*
+ * auth_reset - called when LCP is starting negotiations to recheck
+ * authentication options, i.e. whether we have appropriate secrets
+ * to use for authenticating ourselves and/or the peer.
+ */
+void
+auth_reset(int unit)
+{
+  lcp_options *go = &lcp_gotoptions[unit];
+  lcp_options *ao = &lcp_allowoptions[0];
+  ipcp_options *ipwo = &ipcp_wantoptions[0];
+  u32_t remote;
+
+  AUTHDEBUG((LOG_INFO, "auth_reset: %d\n", unit));
+  ao->neg_upap = !ppp_settings.refuse_pap && (ppp_settings.passwd[0] != 0 || get_pap_passwd(unit, NULL, NULL));
+  ao->neg_chap = !ppp_settings.refuse_chap && ppp_settings.passwd[0] != 0 /*have_chap_secret(ppp_settings.user, ppp_settings.remote_name, (u32_t)0)*/;
+
+  if (go->neg_upap && !have_pap_secret()) {
+    go->neg_upap = 0;
+  }
+  if (go->neg_chap) {
+    remote = ipwo->accept_remote? 0: ipwo->hisaddr;
+    if (!have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote)) {
+      go->neg_chap = 0;
+    }
+  }
+}
+
+#if PAP_SUPPORT
+/*
+ * check_passwd - Check the user name and passwd against the PAP secrets
+ * file.  If requested, also check against the system password database,
+ * and login the user if OK.
+ *
+ * returns:
+ *  UPAP_AUTHNAK: Authentication failed.
+ *  UPAP_AUTHACK: Authentication succeeded.
+ * In either case, msg points to an appropriate message.
+ */
+int
+check_passwd( int unit, char *auser, int userlen, char *apasswd, int passwdlen, char **msg, int *msglen)
+{
+#if 1
+  LWIP_UNUSED_ARG(unit);
+  LWIP_UNUSED_ARG(auser);
+  LWIP_UNUSED_ARG(userlen);
+  LWIP_UNUSED_ARG(apasswd);
+  LWIP_UNUSED_ARG(passwdlen);
+  LWIP_UNUSED_ARG(msglen);
+  *msg = (char *) 0;
+  return UPAP_AUTHACK;     /* XXX Assume all entries OK. */
+#else
+  int ret = 0;
+  struct wordlist *addrs = NULL;
+  char passwd[256], user[256];
+  char secret[MAXWORDLEN];
+  static u_short attempts = 0;
+  
+  /*
+   * Make copies of apasswd and auser, then null-terminate them.
+   */
+  BCOPY(apasswd, passwd, passwdlen);
+  passwd[passwdlen] = '\0';
+  BCOPY(auser, user, userlen);
+  user[userlen] = '\0';
+  *msg = (char *) 0;
+
+  /* XXX Validate user name and password. */
+  ret = UPAP_AUTHACK;     /* XXX Assume all entries OK. */
+      
+  if (ret == UPAP_AUTHNAK) {
+    if (*msg == (char *) 0) {
+      *msg = "Login incorrect";
+    }
+    *msglen = strlen(*msg);
+    /*
+     * Frustrate passwd stealer programs.
+     * Allow 10 tries, but start backing off after 3 (stolen from login).
+     * On 10'th, drop the connection.
+     */
+    if (attempts++ >= 10) {
+      AUTHDEBUG((LOG_WARNING, "%d LOGIN FAILURES BY %s\n", attempts, user));
+      /*ppp_panic("Excess Bad Logins");*/
+    }
+    if (attempts > 3) {
+      sys_msleep((attempts - 3) * 5);
+    }
+    if (addrs != NULL) {
+      free_wordlist(addrs);
+    }
+  } else {
+    attempts = 0; /* Reset count */
+    if (*msg == (char *) 0) {
+      *msg = "Login ok";
+    }
+    *msglen = strlen(*msg);
+    set_allowed_addrs(unit, addrs);
+  }
+
+  BZERO(passwd, sizeof(passwd));
+  BZERO(secret, sizeof(secret));
+
+  return ret;
+#endif
+}
+#endif /* PAP_SUPPORT */
+
+
+/*
+ * auth_ip_addr - check whether the peer is authorized to use
+ * a given IP address.  Returns 1 if authorized, 0 otherwise.
+ */
+int
+auth_ip_addr(int unit, u32_t addr)
+{
+  return ip_addr_check(addr, addresses[unit]);
+}
+
+/*
+ * bad_ip_adrs - return 1 if the IP address is one we don't want
+ * to use, such as an address in the loopback net or a multicast address.
+ * addr is in network byte order.
+ */
+int
+bad_ip_adrs(u32_t addr)
+{
+  addr = ntohl(addr);
+  return (addr >> IN_CLASSA_NSHIFT) == IN_LOOPBACKNET
+      || IN_MULTICAST(addr) || IN_BADCLASS(addr);
+}
+
+
+#if CHAP_SUPPORT
+/*
+ * get_secret - open the CHAP secret file and return the secret
+ * for authenticating the given client on the given server.
+ * (We could be either client or server).
+ */
+int get_secret( int unit, char *client, char *server, char *secret, int *secret_len, int save_addrs)
+{
+#if 1
+  int len;
+  struct wordlist *addrs;
+
+  LWIP_UNUSED_ARG(unit);
+  LWIP_UNUSED_ARG(server);
+  LWIP_UNUSED_ARG(save_addrs);
+
+  addrs = NULL;
+
+  if(!client || !client[0] || strcmp(client, ppp_settings.user)) {
+    return 0;
+  }
+
+  len = strlen(ppp_settings.passwd);
+  if (len > MAXSECRETLEN) {
+    AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server));
+    len = MAXSECRETLEN;
+  }
+
+  BCOPY(ppp_settings.passwd, secret, len);
+  *secret_len = len;
+
+  return 1;
+#else
+  int ret = 0, len;
+  struct wordlist *addrs;
+  char secbuf[MAXWORDLEN];
+  
+  addrs = NULL;
+  secbuf[0] = 0;
+
+  /* XXX Find secret. */
+  if (ret < 0) {
+    return 0;
+  }
+
+  if (save_addrs) {
+    set_allowed_addrs(unit, addrs);
+  }
+
+  len = strlen(secbuf);
+  if (len > MAXSECRETLEN) {
+    AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server));
+    len = MAXSECRETLEN;
+  }
+
+  BCOPY(secbuf, secret, len);
+  BZERO(secbuf, sizeof(secbuf));
+  *secret_len = len;
+
+  return 1;
+#endif
+}
+#endif /* CHAP_SUPPORT */
+
+
+#if 0 /* UNUSED */
+/*
+ * auth_check_options - called to check authentication options.
+ */
+void
+auth_check_options(void)
+{
+  lcp_options *wo = &lcp_wantoptions[0];
+  int can_auth;
+  ipcp_options *ipwo = &ipcp_wantoptions[0];
+  u32_t remote;
+
+  /* Default our_name to hostname, and user to our_name */
+  if (ppp_settings.our_name[0] == 0 || ppp_settings.usehostname) {
+      strcpy(ppp_settings.our_name, ppp_settings.hostname);
+  }
+
+  if (ppp_settings.user[0] == 0) {
+    strcpy(ppp_settings.user, ppp_settings.our_name);
+  }
+
+  /* If authentication is required, ask peer for CHAP or PAP. */
+  if (ppp_settings.auth_required && !wo->neg_chap && !wo->neg_upap) {
+    wo->neg_chap = 1;
+    wo->neg_upap = 1;
+  }
+  
+  /*
+   * Check whether we have appropriate secrets to use
+   * to authenticate the peer.
+   */
+  can_auth = wo->neg_upap && have_pap_secret();
+  if (!can_auth && wo->neg_chap) {
+    remote = ipwo->accept_remote? 0: ipwo->hisaddr;
+    can_auth = have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote);
+  }
+
+  if (ppp_settings.auth_required && !can_auth) {
+    ppp_panic("No auth secret");
+  }
+}
+#endif
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * Proceed to the network phase.
+ */
+static void
+network_phase(int unit)
+{
+  int i;
+  struct protent *protp;
+  lcp_options *go = &lcp_gotoptions[unit];
+  
+  /*
+   * If the peer had to authenticate, run the auth-up script now.
+   */
+  if ((go->neg_chap || go->neg_upap) && !did_authup) {
+    /* XXX Do setup for peer authentication. */
+    did_authup = 1;
+  }
+
+#if CBCP_SUPPORT
+  /*
+   * If we negotiated callback, do it now.
+   */
+  if (go->neg_cbcp) {
+    lcp_phase[unit] = PHASE_CALLBACK;
+    (*cbcp_protent.open)(unit);
+    return;
+  }
+#endif /* CBCP_SUPPORT */
+
+  lcp_phase[unit] = PHASE_NETWORK;
+  for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+    if (protp->protocol < 0xC000 && protp->enabled_flag && protp->open != NULL) {
+      (*protp->open)(unit);
+      if (protp->protocol != PPP_CCP) {
+        ++num_np_open;
+      }
+    }
+  }
+
+  if (num_np_open == 0) {
+    /* nothing to do */
+    lcp_close(0, "No network protocols running");
+  }
+}
+
+/*
+ * check_idle - check whether the link has been idle for long
+ * enough that we can shut it down.
+ */
+static void
+check_idle(void *arg)
+{
+  struct ppp_idle idle;
+  u_short itime;
+  
+  LWIP_UNUSED_ARG(arg);
+  if (!get_idle_time(0, &idle)) {
+    return;
+  }
+  itime = LWIP_MIN(idle.xmit_idle, idle.recv_idle);
+  if (itime >= ppp_settings.idle_time_limit) {
+    /* link is idle: shut it down. */
+    AUTHDEBUG((LOG_INFO, "Terminating connection due to lack of activity.\n"));
+    lcp_close(0, "Link inactive");
+  } else {
+    TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit - itime);
+  }
+}
+
+/*
+ * connect_time_expired - log a message and close the connection.
+ */
+static void
+connect_time_expired(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+
+  AUTHDEBUG((LOG_INFO, "Connect time expired\n"));
+  lcp_close(0, "Connect time expired");   /* Close connection */
+}
+
+#if 0
+/*
+ * login - Check the user name and password against the system
+ * password database, and login the user if OK.
+ *
+ * returns:
+ *  UPAP_AUTHNAK: Login failed.
+ *  UPAP_AUTHACK: Login succeeded.
+ * In either case, msg points to an appropriate message.
+ */
+static int
+login(char *user, char *passwd, char **msg, int *msglen)
+{
+  /* XXX Fail until we decide that we want to support logins. */
+  return (UPAP_AUTHNAK);
+}
+#endif
+
+/*
+ * logout - Logout the user.
+ */
+static void
+logout(void)
+{
+  logged_in = 0;
+}
+
+/*
+ * null_login - Check if a username of "" and a password of "" are
+ * acceptable, and iff so, set the list of acceptable IP addresses
+ * and return 1.
+ */
+static int
+null_login(int unit)
+{
+  LWIP_UNUSED_ARG(unit);
+  /* XXX Fail until we decide that we want to support logins. */
+  return 0;
+}
+
+/*
+ * get_pap_passwd - get a password for authenticating ourselves with
+ * our peer using PAP.  Returns 1 on success, 0 if no suitable password
+ * could be found.
+ */
+static int
+get_pap_passwd(int unit, char *user, char *passwd)
+{
+  LWIP_UNUSED_ARG(unit);
+/* normally we would reject PAP if no password is provided,
+   but this causes problems with some providers (like CHT in Taiwan)
+   who incorrectly request PAP and expect a bogus/empty password, so
+   always provide a default user/passwd of "none"/"none"
+*/
+  if(user) {
+    strcpy(user, "none");
+  }
+  if(passwd) {
+    strcpy(passwd, "none");
+  }
+  return 1;
+}
+
+/*
+ * have_pap_secret - check whether we have a PAP file with any
+ * secrets that we could possibly use for authenticating the peer.
+ */
+static int
+have_pap_secret(void)
+{
+  /* XXX Fail until we set up our passwords. */
+  return 0;
+}
+
+/*
+ * have_chap_secret - check whether we have a CHAP file with a
+ * secret that we could possibly use for authenticating `client'
+ * on `server'.  Either can be the null string, meaning we don't
+ * know the identity yet.
+ */
+static int
+have_chap_secret(char *client, char *server, u32_t remote)
+{
+  LWIP_UNUSED_ARG(client);
+  LWIP_UNUSED_ARG(server);
+  LWIP_UNUSED_ARG(remote);
+  /* XXX Fail until we set up our passwords. */
+  return 0;
+}
+
+#if 0 /* PAP_SUPPORT || CHAP_SUPPORT */
+/*
+ * set_allowed_addrs() - set the list of allowed addresses.
+ */
+static void
+set_allowed_addrs(int unit, struct wordlist *addrs)
+{
+  if (addresses[unit] != NULL) {
+    free_wordlist(addresses[unit]);
+  }
+  addresses[unit] = addrs;
+
+#if 0
+  /*
+   * If there's only one authorized address we might as well
+   * ask our peer for that one right away
+   */
+  if (addrs != NULL && addrs->next == NULL) {
+    char *p = addrs->word;
+    struct ipcp_options *wo = &ipcp_wantoptions[unit];
+    u32_t a;
+    struct hostent *hp;
+    
+    if (wo->hisaddr == 0 && *p != '!' && *p != '-' && strchr(p, '/') == NULL) {
+      hp = gethostbyname(p);
+      if (hp != NULL && hp->h_addrtype == AF_INET) {
+        a = *(u32_t *)hp->h_addr;
+      } else {
+        a = inet_addr(p);
+      }
+      if (a != (u32_t) -1) {
+        wo->hisaddr = a;
+      }
+    }
+  }
+#endif
+}
+#endif /* 0 */ /* PAP_SUPPORT || CHAP_SUPPORT */
+
+static int
+ip_addr_check(u32_t addr, struct wordlist *addrs)
+{
+  /* don't allow loopback or multicast address */
+  if (bad_ip_adrs(addr)) {
+    return 0;
+  }
+
+  if (addrs == NULL) {
+    return !ppp_settings.auth_required; /* no addresses authorized */
+  }
+
+  /* XXX All other addresses allowed. */
+  return 1;
+}
+
+#if 0 /* PAP_SUPPORT || CHAP_SUPPORT */
+/*
+ * free_wordlist - release memory allocated for a wordlist.
+ */
+static void
+free_wordlist(struct wordlist *wp)
+{
+  struct wordlist *next;
+  
+  while (wp != NULL) {
+    next = wp->next;
+    free(wp);
+    wp = next;
+  }
+}
+#endif  /* 0 */ /* PAP_SUPPORT || CHAP_SUPPORT */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/auth.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/auth.h
new file mode 100644
index 0000000..6e9e000
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/auth.h
@@ -0,0 +1,111 @@
+/*****************************************************************************
+* auth.h -  PPP Authentication and phase control header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD pppd.h.
+*****************************************************************************/
+/*
+ * pppd.h - PPP daemon global declarations.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ */
+
+#ifndef AUTH_H
+#define AUTH_H
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+/* we are starting to use the link */
+void link_required (int);
+
+/* we are finished with the link */
+void link_terminated (int);
+
+/* the LCP layer has left the Opened state */
+void link_down (int);
+
+/* the link is up; authenticate now */
+void link_established (int);
+
+/* a network protocol has come up */
+void np_up (int, u16_t);
+
+/* a network protocol has gone down */
+void np_down (int, u16_t);
+
+/* a network protocol no longer needs link */
+void np_finished (int, u16_t);
+
+/* peer failed to authenticate itself */
+void auth_peer_fail (int, u16_t);
+
+/* peer successfully authenticated itself */
+void auth_peer_success (int, u16_t, char *, int);
+
+/* we failed to authenticate ourselves */
+void auth_withpeer_fail (int, u16_t);
+
+/* we successfully authenticated ourselves */
+void auth_withpeer_success (int, u16_t);
+
+/* check authentication options supplied */
+void auth_check_options (void);
+
+/* check what secrets we have */
+void auth_reset (int);
+
+/* Check peer-supplied username/password */
+int  check_passwd (int, char *, int, char *, int, char **, int *);
+
+/* get "secret" for chap */
+int  get_secret (int, char *, char *, char *, int *, int);
+
+/* check if IP address is authorized */
+int  auth_ip_addr (int, u32_t);
+
+/* check if IP address is unreasonable */
+int  bad_ip_adrs (u32_t);
+
+#endif /* AUTH_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/chap.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/chap.c
new file mode 100644
index 0000000..938994a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/chap.c
@@ -0,0 +1,902 @@
+/*** WARNING - THIS HAS NEVER BEEN FINISHED ***/
+/*****************************************************************************
+* chap.c - Network Challenge Handshake Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*   Original based on BSD chap.c.
+*****************************************************************************/
+/*
+ * chap.c - Challenge Handshake Authentication Protocol.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University.  The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1991 Gregory M. Christy.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Gregory M. Christy.  The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#if CHAP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "magic.h"
+#include "randm.h"
+#include "auth.h"
+#include "md5.h"
+#include "chap.h"
+#include "chpms.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Protocol entry points.
+ */
+static void ChapInit (int);
+static void ChapLowerUp (int);
+static void ChapLowerDown (int);
+static void ChapInput (int, u_char *, int);
+static void ChapProtocolReject (int);
+#if 0
+static int  ChapPrintPkt (u_char *, int, void (*) (void *, char *, ...), void *);
+#endif
+
+static void ChapChallengeTimeout (void *);
+static void ChapResponseTimeout (void *);
+static void ChapReceiveChallenge (chap_state *, u_char *, int, int);
+static void ChapRechallenge (void *);
+static void ChapReceiveResponse (chap_state *, u_char *, int, int);
+static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len);
+static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len);
+static void ChapSendStatus (chap_state *, int);
+static void ChapSendChallenge (chap_state *);
+static void ChapSendResponse (chap_state *);
+static void ChapGenChallenge (chap_state *);
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+chap_state chap[NUM_PPP]; /* CHAP state; one for each unit */
+
+struct protent chap_protent = {
+  PPP_CHAP,
+  ChapInit,
+  ChapInput,
+  ChapProtocolReject,
+  ChapLowerUp,
+  ChapLowerDown,
+  NULL,
+  NULL,
+#if 0
+  ChapPrintPkt,
+  NULL,
+#endif
+  1,
+  "CHAP",
+#if 0
+  NULL,
+  NULL,
+  NULL
+#endif
+};
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * ChapAuthWithPeer - Authenticate us with our peer (start client).
+ *
+ */
+void
+ChapAuthWithPeer(int unit, char *our_name, int digest)
+{
+  chap_state *cstate = &chap[unit];
+
+  cstate->resp_name = our_name;
+  cstate->resp_type = digest;
+
+  if (cstate->clientstate == CHAPCS_INITIAL ||
+      cstate->clientstate == CHAPCS_PENDING) {
+    /* lower layer isn't up - wait until later */
+    cstate->clientstate = CHAPCS_PENDING;
+    return;
+  }
+
+  /*
+   * We get here as a result of LCP coming up.
+   * So even if CHAP was open before, we will 
+   * have to re-authenticate ourselves.
+   */
+  cstate->clientstate = CHAPCS_LISTEN;
+}
+
+
+/*
+ * ChapAuthPeer - Authenticate our peer (start server).
+ */
+void
+ChapAuthPeer(int unit, char *our_name, int digest)
+{
+  chap_state *cstate = &chap[unit];
+
+  cstate->chal_name = our_name;
+  cstate->chal_type = digest;
+  
+  if (cstate->serverstate == CHAPSS_INITIAL ||
+      cstate->serverstate == CHAPSS_PENDING) {
+    /* lower layer isn't up - wait until later */
+    cstate->serverstate = CHAPSS_PENDING;
+    return;
+  }
+
+  ChapGenChallenge(cstate);
+  ChapSendChallenge(cstate);    /* crank it up dude! */
+  cstate->serverstate = CHAPSS_INITIAL_CHAL;
+}
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * ChapInit - Initialize a CHAP unit.
+ */
+static void
+ChapInit(int unit)
+{
+  chap_state *cstate = &chap[unit];
+
+  BZERO(cstate, sizeof(*cstate));
+  cstate->unit = unit;
+  cstate->clientstate = CHAPCS_INITIAL;
+  cstate->serverstate = CHAPSS_INITIAL;
+  cstate->timeouttime = CHAP_DEFTIMEOUT;
+  cstate->max_transmits = CHAP_DEFTRANSMITS;
+  /* random number generator is initialized in magic_init */
+}
+
+
+/*
+ * ChapChallengeTimeout - Timeout expired on sending challenge.
+ */
+static void
+ChapChallengeTimeout(void *arg)
+{
+  chap_state *cstate = (chap_state *) arg;
+
+  /* if we aren't sending challenges, don't worry.  then again we */
+  /* probably shouldn't be here either */
+  if (cstate->serverstate != CHAPSS_INITIAL_CHAL &&
+      cstate->serverstate != CHAPSS_RECHALLENGE) {
+    return;
+  }
+
+  if (cstate->chal_transmits >= cstate->max_transmits) {
+    /* give up on peer */
+    CHAPDEBUG((LOG_ERR, "Peer failed to respond to CHAP challenge\n"));
+    cstate->serverstate = CHAPSS_BADAUTH;
+    auth_peer_fail(cstate->unit, PPP_CHAP);
+    return;
+  }
+
+  ChapSendChallenge(cstate); /* Re-send challenge */
+}
+
+
+/*
+ * ChapResponseTimeout - Timeout expired on sending response.
+ */
+static void
+ChapResponseTimeout(void *arg)
+{
+  chap_state *cstate = (chap_state *) arg;
+
+  /* if we aren't sending a response, don't worry. */
+  if (cstate->clientstate != CHAPCS_RESPONSE) {
+    return;
+  }
+
+  ChapSendResponse(cstate);    /* re-send response */
+}
+
+
+/*
+ * ChapRechallenge - Time to challenge the peer again.
+ */
+static void
+ChapRechallenge(void *arg)
+{
+  chap_state *cstate = (chap_state *) arg;
+  
+  /* if we aren't sending a response, don't worry. */
+  if (cstate->serverstate != CHAPSS_OPEN) {
+    return;
+  }
+
+  ChapGenChallenge(cstate);
+  ChapSendChallenge(cstate);
+  cstate->serverstate = CHAPSS_RECHALLENGE;
+}
+
+
+/*
+ * ChapLowerUp - The lower layer is up.
+ *
+ * Start up if we have pending requests.
+ */
+static void
+ChapLowerUp(int unit)
+{
+  chap_state *cstate = &chap[unit];
+
+  if (cstate->clientstate == CHAPCS_INITIAL) {
+    cstate->clientstate = CHAPCS_CLOSED;
+  } else if (cstate->clientstate == CHAPCS_PENDING) {
+    cstate->clientstate = CHAPCS_LISTEN;
+  }
+
+  if (cstate->serverstate == CHAPSS_INITIAL) {
+    cstate->serverstate = CHAPSS_CLOSED;
+  } else if (cstate->serverstate == CHAPSS_PENDING) {
+    ChapGenChallenge(cstate);
+    ChapSendChallenge(cstate);
+    cstate->serverstate = CHAPSS_INITIAL_CHAL;
+  }
+}
+
+
+/*
+ * ChapLowerDown - The lower layer is down.
+ *
+ * Cancel all timeouts.
+ */
+static void
+ChapLowerDown(int unit)
+{
+  chap_state *cstate = &chap[unit];
+
+  /* Timeout(s) pending?  Cancel if so. */
+  if (cstate->serverstate == CHAPSS_INITIAL_CHAL ||
+      cstate->serverstate == CHAPSS_RECHALLENGE) {
+    UNTIMEOUT(ChapChallengeTimeout, cstate);
+  } else if (cstate->serverstate == CHAPSS_OPEN
+      && cstate->chal_interval != 0) {
+    UNTIMEOUT(ChapRechallenge, cstate);
+  }
+  if (cstate->clientstate == CHAPCS_RESPONSE) {
+    UNTIMEOUT(ChapResponseTimeout, cstate);
+  }
+  cstate->clientstate = CHAPCS_INITIAL;
+  cstate->serverstate = CHAPSS_INITIAL;
+}
+
+
+/*
+ * ChapProtocolReject - Peer doesn't grok CHAP.
+ */
+static void
+ChapProtocolReject(int unit)
+{
+  chap_state *cstate = &chap[unit];
+  
+  if (cstate->serverstate != CHAPSS_INITIAL &&
+      cstate->serverstate != CHAPSS_CLOSED) {
+    auth_peer_fail(unit, PPP_CHAP);
+  }
+  if (cstate->clientstate != CHAPCS_INITIAL &&
+      cstate->clientstate != CHAPCS_CLOSED) {
+    auth_withpeer_fail(unit, PPP_CHAP);
+  }
+  ChapLowerDown(unit); /* shutdown chap */
+}
+
+
+/*
+ * ChapInput - Input CHAP packet.
+ */
+static void
+ChapInput(int unit, u_char *inpacket, int packet_len)
+{
+  chap_state *cstate = &chap[unit];
+  u_char *inp;
+  u_char code, id;
+  int len;
+  
+  /*
+   * Parse header (code, id and length).
+   * If packet too short, drop it.
+   */
+  inp = inpacket;
+  if (packet_len < CHAP_HEADERLEN) {
+    CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short header.\n"));
+    return;
+  }
+  GETCHAR(code, inp);
+  GETCHAR(id, inp);
+  GETSHORT(len, inp);
+  if (len < CHAP_HEADERLEN) {
+    CHAPDEBUG((LOG_INFO, "ChapInput: rcvd illegal length.\n"));
+    return;
+  }
+  if (len > packet_len) {
+    CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short packet.\n"));
+    return;
+  }
+  len -= CHAP_HEADERLEN;
+  
+  /*
+   * Action depends on code (as in fact it usually does :-).
+   */
+  switch (code) {
+    case CHAP_CHALLENGE:
+      ChapReceiveChallenge(cstate, inp, id, len);
+      break;
+    
+    case CHAP_RESPONSE:
+      ChapReceiveResponse(cstate, inp, id, len);
+      break;
+    
+    case CHAP_FAILURE:
+      ChapReceiveFailure(cstate, inp, id, len);
+      break;
+    
+    case CHAP_SUCCESS:
+      ChapReceiveSuccess(cstate, inp, id, len);
+      break;
+    
+    default:        /* Need code reject? */
+      CHAPDEBUG((LOG_WARNING, "Unknown CHAP code (%d) received.\n", code));
+      break;
+  }
+}
+
+
+/*
+ * ChapReceiveChallenge - Receive Challenge and send Response.
+ */
+static void
+ChapReceiveChallenge(chap_state *cstate, u_char *inp, int id, int len)
+{
+  int rchallenge_len;
+  u_char *rchallenge;
+  int secret_len;
+  char secret[MAXSECRETLEN];
+  char rhostname[256];
+  MD5_CTX mdContext;
+  u_char hash[MD5_SIGNATURE_SIZE];
+  
+  CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: Rcvd id %d.\n", id));
+  if (cstate->clientstate == CHAPCS_CLOSED ||
+    cstate->clientstate == CHAPCS_PENDING) {
+    CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: in state %d\n",
+         cstate->clientstate));
+    return;
+  }
+
+  if (len < 2) {
+    CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n"));
+    return;
+  }
+
+  GETCHAR(rchallenge_len, inp);
+  len -= sizeof (u_char) + rchallenge_len;  /* now name field length */
+  if (len < 0) {
+    CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n"));
+    return;
+  }
+  rchallenge = inp;
+  INCPTR(rchallenge_len, inp);
+
+  if (len >= sizeof(rhostname)) {
+    len = sizeof(rhostname) - 1;
+  }
+  BCOPY(inp, rhostname, len);
+  rhostname[len] = '\000';
+
+  CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: received name field '%s'\n", rhostname));
+
+  /* Microsoft doesn't send their name back in the PPP packet */
+  if (ppp_settings.remote_name[0] != 0 && (ppp_settings.explicit_remote || rhostname[0] == 0)) {
+    strncpy(rhostname, ppp_settings.remote_name, sizeof(rhostname));
+    rhostname[sizeof(rhostname) - 1] = 0;
+    CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: using '%s' as remote name\n", rhostname));
+  }
+
+  /* get secret for authenticating ourselves with the specified host */
+  if (!get_secret(cstate->unit, cstate->resp_name, rhostname, secret, &secret_len, 0)) {
+    secret_len = 0;    /* assume null secret if can't find one */
+    CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating us to %s\n", rhostname));
+  }
+
+  /* cancel response send timeout if necessary */
+  if (cstate->clientstate == CHAPCS_RESPONSE) {
+    UNTIMEOUT(ChapResponseTimeout, cstate);
+  }
+
+  cstate->resp_id = id;
+  cstate->resp_transmits = 0;
+
+  /*  generate MD based on negotiated type */
+  switch (cstate->resp_type) { 
+
+  case CHAP_DIGEST_MD5:
+    MD5Init(&mdContext);
+    MD5Update(&mdContext, &cstate->resp_id, 1);
+    MD5Update(&mdContext, (u_char*)secret, secret_len);
+    MD5Update(&mdContext, rchallenge, rchallenge_len);
+    MD5Final(hash, &mdContext);
+    BCOPY(hash, cstate->response, MD5_SIGNATURE_SIZE);
+    cstate->resp_length = MD5_SIGNATURE_SIZE;
+    break;
+  
+#ifdef CHAPMS
+  case CHAP_MICROSOFT:
+    ChapMS(cstate, rchallenge, rchallenge_len, secret, secret_len);
+    break;
+#endif
+
+  default:
+    CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->resp_type));
+    return;
+  }
+
+  BZERO(secret, sizeof(secret));
+  ChapSendResponse(cstate);
+}
+
+
+/*
+ * ChapReceiveResponse - Receive and process response.
+ */
+static void
+ChapReceiveResponse(chap_state *cstate, u_char *inp, int id, int len)
+{
+  u_char *remmd, remmd_len;
+  int secret_len, old_state;
+  int code;
+  char rhostname[256];
+  MD5_CTX mdContext;
+  char secret[MAXSECRETLEN];
+  u_char hash[MD5_SIGNATURE_SIZE];
+  
+  CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: Rcvd id %d.\n", id));
+  
+  if (cstate->serverstate == CHAPSS_CLOSED ||
+      cstate->serverstate == CHAPSS_PENDING) {
+    CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: in state %d\n",
+    cstate->serverstate));
+    return;
+  }
+
+  if (id != cstate->chal_id) {
+    return;      /* doesn't match ID of last challenge */
+  }
+
+  /*
+  * If we have received a duplicate or bogus Response,
+  * we have to send the same answer (Success/Failure)
+  * as we did for the first Response we saw.
+  */
+  if (cstate->serverstate == CHAPSS_OPEN) {
+    ChapSendStatus(cstate, CHAP_SUCCESS);
+    return;
+  }
+  if (cstate->serverstate == CHAPSS_BADAUTH) {
+    ChapSendStatus(cstate, CHAP_FAILURE);
+    return;
+  }
+  
+  if (len < 2) {
+    CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n"));
+    return;
+  }
+  GETCHAR(remmd_len, inp); /* get length of MD */
+  remmd = inp;             /* get pointer to MD */
+  INCPTR(remmd_len, inp);
+  
+  len -= sizeof (u_char) + remmd_len;
+  if (len < 0) {
+    CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n"));
+    return;
+  }
+
+  UNTIMEOUT(ChapChallengeTimeout, cstate);
+  
+  if (len >= sizeof(rhostname)) {
+    len = sizeof(rhostname) - 1;
+  }
+  BCOPY(inp, rhostname, len);
+  rhostname[len] = '\000';
+
+  CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: received name field: %s\n", rhostname));
+
+  /*
+  * Get secret for authenticating them with us,
+  * do the hash ourselves, and compare the result.
+  */
+  code = CHAP_FAILURE;
+  if (!get_secret(cstate->unit, rhostname, cstate->chal_name, secret, &secret_len, 1)) {
+    /* CHAPDEBUG((LOG_WARNING, TL_CHAP, "No CHAP secret found for authenticating %s\n", rhostname)); */
+    CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating %s\n",
+    rhostname));
+  } else {
+    /*  generate MD based on negotiated type */
+    switch (cstate->chal_type) {
+
+      case CHAP_DIGEST_MD5:    /* only MD5 is defined for now */
+        if (remmd_len != MD5_SIGNATURE_SIZE) {
+          break;      /* it's not even the right length */
+        }
+        MD5Init(&mdContext);
+        MD5Update(&mdContext, &cstate->chal_id, 1);
+        MD5Update(&mdContext, (u_char*)secret, secret_len);
+        MD5Update(&mdContext, cstate->challenge, cstate->chal_len);
+        MD5Final(hash, &mdContext); 
+        
+        /* compare local and remote MDs and send the appropriate status */
+        if (memcmp (hash, remmd, MD5_SIGNATURE_SIZE) == 0) {
+          code = CHAP_SUCCESS;  /* they are the same! */
+        }
+        break;
+      
+      default:
+        CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->chal_type));
+    }
+  }
+  
+  BZERO(secret, sizeof(secret));
+  ChapSendStatus(cstate, code);
+
+  if (code == CHAP_SUCCESS) {
+    old_state = cstate->serverstate;
+    cstate->serverstate = CHAPSS_OPEN;
+    if (old_state == CHAPSS_INITIAL_CHAL) {
+      auth_peer_success(cstate->unit, PPP_CHAP, rhostname, len);
+    }
+    if (cstate->chal_interval != 0) {
+      TIMEOUT(ChapRechallenge, cstate, cstate->chal_interval);
+    }
+  } else {
+    CHAPDEBUG((LOG_ERR, "CHAP peer authentication failed\n"));
+    cstate->serverstate = CHAPSS_BADAUTH;
+    auth_peer_fail(cstate->unit, PPP_CHAP);
+  }
+}
+
+/*
+ * ChapReceiveSuccess - Receive Success
+ */
+static void
+ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len)
+{
+  LWIP_UNUSED_ARG(id);
+  LWIP_UNUSED_ARG(inp);
+
+  CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: Rcvd id %d.\n", id));
+
+  if (cstate->clientstate == CHAPCS_OPEN) {
+    /* presumably an answer to a duplicate response */
+    return;
+  }
+
+  if (cstate->clientstate != CHAPCS_RESPONSE) {
+    /* don't know what this is */
+    CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: in state %d\n", cstate->clientstate));
+    return;
+  }
+  
+  UNTIMEOUT(ChapResponseTimeout, cstate);
+  
+  /*
+   * Print message.
+   */
+  if (len > 0) {
+    PRINTMSG(inp, len);
+  }
+
+  cstate->clientstate = CHAPCS_OPEN;
+
+  auth_withpeer_success(cstate->unit, PPP_CHAP);
+}
+
+
+/*
+ * ChapReceiveFailure - Receive failure.
+ */
+static void
+ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len)
+{
+  LWIP_UNUSED_ARG(id);
+  LWIP_UNUSED_ARG(inp);
+
+  CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: Rcvd id %d.\n", id));
+
+  if (cstate->clientstate != CHAPCS_RESPONSE) {
+    /* don't know what this is */
+    CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: in state %d\n", cstate->clientstate));
+    return;
+  }
+
+  UNTIMEOUT(ChapResponseTimeout, cstate);
+
+  /*
+   * Print message.
+   */
+  if (len > 0) {
+    PRINTMSG(inp, len);
+  }
+
+  CHAPDEBUG((LOG_ERR, "CHAP authentication failed\n"));
+  auth_withpeer_fail(cstate->unit, PPP_CHAP);
+}
+
+
+/*
+ * ChapSendChallenge - Send an Authenticate challenge.
+ */
+static void
+ChapSendChallenge(chap_state *cstate)
+{
+  u_char *outp;
+  int chal_len, name_len;
+  int outlen;
+  
+  chal_len = cstate->chal_len;
+  name_len = strlen(cstate->chal_name);
+  outlen = CHAP_HEADERLEN + sizeof (u_char) + chal_len + name_len;
+  outp = outpacket_buf[cstate->unit];
+  
+  MAKEHEADER(outp, PPP_CHAP);    /* paste in a CHAP header */
+  
+  PUTCHAR(CHAP_CHALLENGE, outp);
+  PUTCHAR(cstate->chal_id, outp);
+  PUTSHORT(outlen, outp);
+  
+  PUTCHAR(chal_len, outp);    /* put length of challenge */
+  BCOPY(cstate->challenge, outp, chal_len);
+  INCPTR(chal_len, outp);
+  
+  BCOPY(cstate->chal_name, outp, name_len);  /* append hostname */
+  
+  pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+  
+  CHAPDEBUG((LOG_INFO, "ChapSendChallenge: Sent id %d.\n", cstate->chal_id));
+  
+  TIMEOUT(ChapChallengeTimeout, cstate, cstate->timeouttime);
+  ++cstate->chal_transmits;
+}
+
+
+/*
+ * ChapSendStatus - Send a status response (ack or nak).
+ */
+static void
+ChapSendStatus(chap_state *cstate, int code)
+{
+  u_char *outp;
+  int outlen, msglen;
+  char msg[256];
+  
+  if (code == CHAP_SUCCESS) {
+    strcpy(msg, "Welcome!");
+  } else {
+    strcpy(msg, "I don't like you.  Go 'way.");
+  }
+  msglen = strlen(msg);
+  
+  outlen = CHAP_HEADERLEN + msglen;
+  outp = outpacket_buf[cstate->unit];
+  
+  MAKEHEADER(outp, PPP_CHAP);    /* paste in a header */
+  
+  PUTCHAR(code, outp);
+  PUTCHAR(cstate->chal_id, outp);
+  PUTSHORT(outlen, outp);
+  BCOPY(msg, outp, msglen);
+  pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+  
+  CHAPDEBUG((LOG_INFO, "ChapSendStatus: Sent code %d, id %d.\n", code, cstate->chal_id));
+}
+
+/*
+ * ChapGenChallenge is used to generate a pseudo-random challenge string of
+ * a pseudo-random length between min_len and max_len.  The challenge
+ * string and its length are stored in *cstate, and various other fields of
+ * *cstate are initialized.
+ */
+
+static void
+ChapGenChallenge(chap_state *cstate)
+{
+  int chal_len;
+  u_char *ptr = cstate->challenge;
+  int i;
+  
+  /* pick a random challenge length between MIN_CHALLENGE_LENGTH and 
+     MAX_CHALLENGE_LENGTH */  
+  chal_len = (unsigned)
+        ((((magic() >> 16) *
+              (MAX_CHALLENGE_LENGTH - MIN_CHALLENGE_LENGTH)) >> 16)
+           + MIN_CHALLENGE_LENGTH);
+  cstate->chal_len = chal_len;
+  cstate->chal_id = ++cstate->id;
+  cstate->chal_transmits = 0;
+  
+  /* generate a random string */
+  for (i = 0; i < chal_len; i++ ) {
+    *ptr++ = (char) (magic() & 0xff);
+  }
+}
+
+/*
+ * ChapSendResponse - send a response packet with values as specified
+ * in *cstate.
+ */
+/* ARGSUSED */
+static void
+ChapSendResponse(chap_state *cstate)
+{
+  u_char *outp;
+  int outlen, md_len, name_len;
+  
+  md_len = cstate->resp_length;
+  name_len = strlen(cstate->resp_name);
+  outlen = CHAP_HEADERLEN + sizeof (u_char) + md_len + name_len;
+  outp = outpacket_buf[cstate->unit];
+  
+  MAKEHEADER(outp, PPP_CHAP);
+  
+  PUTCHAR(CHAP_RESPONSE, outp);  /* we are a response */
+  PUTCHAR(cstate->resp_id, outp);  /* copy id from challenge packet */
+  PUTSHORT(outlen, outp);      /* packet length */
+  
+  PUTCHAR(md_len, outp);      /* length of MD */
+  BCOPY(cstate->response, outp, md_len);    /* copy MD to buffer */
+  INCPTR(md_len, outp);
+  
+  BCOPY(cstate->resp_name, outp, name_len);  /* append our name */
+  
+  /* send the packet */
+  pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+  
+  cstate->clientstate = CHAPCS_RESPONSE;
+  TIMEOUT(ChapResponseTimeout, cstate, cstate->timeouttime);
+  ++cstate->resp_transmits;
+}
+
+#if 0
+static char *ChapCodenames[] = {
+  "Challenge", "Response", "Success", "Failure"
+};
+/*
+ * ChapPrintPkt - print the contents of a CHAP packet.
+ */
+static int
+ChapPrintPkt( u_char *p, int plen, void (*printer) (void *, char *, ...), void *arg)
+{
+  int code, id, len;
+  int clen, nlen;
+  u_char x;
+  
+  if (plen < CHAP_HEADERLEN) {
+    return 0;
+  }
+  GETCHAR(code, p);
+  GETCHAR(id, p);
+  GETSHORT(len, p);
+  if (len < CHAP_HEADERLEN || len > plen) {
+    return 0;
+  }
+  if (code >= 1 && code <= sizeof(ChapCodenames) / sizeof(char *)) {
+    printer(arg, " %s", ChapCodenames[code-1]);
+  } else {
+    printer(arg, " code=0x%x", code);
+  }
+  printer(arg, " id=0x%x", id);
+  len -= CHAP_HEADERLEN;
+  switch (code) {
+    case CHAP_CHALLENGE:
+    case CHAP_RESPONSE:
+      if (len < 1) {
+        break;
+      }
+      clen = p[0];
+      if (len < clen + 1) {
+        break;
+      }
+      ++p;
+      nlen = len - clen - 1;
+      printer(arg, " <");
+      for (; clen > 0; --clen) {
+        GETCHAR(x, p);
+        printer(arg, "%.2x", x);
+      }
+      printer(arg, ">, name = %.*Z", nlen, p);
+      break;
+    case CHAP_FAILURE:
+    case CHAP_SUCCESS:
+      printer(arg, " %.*Z", len, p);
+      break;
+    default:
+      for (clen = len; clen > 0; --clen) {
+        GETCHAR(x, p);
+        printer(arg, " %.2x", x);
+      }
+  }
+
+  return len + CHAP_HEADERLEN;
+}
+#endif
+
+#endif /* CHAP_SUPPORT */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/chap.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/chap.h
new file mode 100644
index 0000000..b48eecb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/chap.h
@@ -0,0 +1,166 @@
+/*****************************************************************************
+* chap.h - Network Challenge Handshake Authentication Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-03 Guy Lancaster , Global Election Systems Inc.
+*   Original built from BSD network code.
+******************************************************************************/
+/*
+ * chap.h - Challenge Handshake Authentication Protocol definitions.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University.  The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1991 Gregory M. Christy
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the author.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: chap.h,v 1.4 2007/12/19 20:47:22 fbernon Exp $
+ */
+
+#ifndef CHAP_H
+#define CHAP_H
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+
+/* Code + ID + length */
+#define CHAP_HEADERLEN 4
+
+/*
+ * CHAP codes.
+ */
+
+#define CHAP_DIGEST_MD5      5    /* use MD5 algorithm */
+#define MD5_SIGNATURE_SIZE   16   /* 16 bytes in a MD5 message digest */
+#define CHAP_MICROSOFT       0x80 /* use Microsoft-compatible alg. */
+#define MS_CHAP_RESPONSE_LEN 49   /* Response length for MS-CHAP */
+
+#define CHAP_CHALLENGE       1
+#define CHAP_RESPONSE        2
+#define CHAP_SUCCESS         3
+#define CHAP_FAILURE         4
+
+/*
+ *  Challenge lengths (for challenges we send) and other limits.
+ */
+#define MIN_CHALLENGE_LENGTH 32
+#define MAX_CHALLENGE_LENGTH 64
+#define MAX_RESPONSE_LENGTH  64 /* sufficient for MD5 or MS-CHAP */
+
+/*
+ * Client (peer) states.
+ */
+#define CHAPCS_INITIAL       0 /* Lower layer down, not opened */
+#define CHAPCS_CLOSED        1 /* Lower layer up, not opened */
+#define CHAPCS_PENDING       2 /* Auth us to peer when lower up */
+#define CHAPCS_LISTEN        3 /* Listening for a challenge */
+#define CHAPCS_RESPONSE      4 /* Sent response, waiting for status */
+#define CHAPCS_OPEN          5 /* We've received Success */
+
+/*
+ * Server (authenticator) states.
+ */
+#define CHAPSS_INITIAL       0 /* Lower layer down, not opened */
+#define CHAPSS_CLOSED        1 /* Lower layer up, not opened */
+#define CHAPSS_PENDING       2 /* Auth peer when lower up */
+#define CHAPSS_INITIAL_CHAL  3 /* We've sent the first challenge */
+#define CHAPSS_OPEN          4 /* We've sent a Success msg */
+#define CHAPSS_RECHALLENGE   5 /* We've sent another challenge */
+#define CHAPSS_BADAUTH       6 /* We've sent a Failure msg */
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * Each interface is described by a chap structure.
+ */
+
+typedef struct chap_state {
+  int unit;                               /* Interface unit number */
+  int clientstate;                        /* Client state */
+  int serverstate;                        /* Server state */
+  u_char challenge[MAX_CHALLENGE_LENGTH]; /* last challenge string sent */
+  u_char chal_len;                        /* challenge length */
+  u_char chal_id;                         /* ID of last challenge */
+  u_char chal_type;                       /* hash algorithm for challenges */
+  u_char id;                              /* Current id */
+  char *chal_name;                        /* Our name to use with challenge */
+  int chal_interval;                      /* Time until we challenge peer again */
+  int timeouttime;                        /* Timeout time in seconds */
+  int max_transmits;                      /* Maximum # of challenge transmissions */
+  int chal_transmits;                     /* Number of transmissions of challenge */
+  int resp_transmits;                     /* Number of transmissions of response */
+  u_char response[MAX_RESPONSE_LENGTH];   /* Response to send */
+  u_char resp_length;                     /* length of response */
+  u_char resp_id;                         /* ID for response messages */
+  u_char resp_type;                       /* hash algorithm for responses */
+  char *resp_name;                        /* Our name to send with response */
+} chap_state;
+
+
+/******************
+*** PUBLIC DATA ***
+******************/
+extern chap_state chap[];
+
+extern struct protent chap_protent;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+void ChapAuthWithPeer (int, char *, int);
+void ChapAuthPeer (int, char *, int);
+
+#endif /* CHAP_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/chpms.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/chpms.c
new file mode 100644
index 0000000..900db42
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/chpms.c
@@ -0,0 +1,396 @@
+/*** WARNING - THIS CODE HAS NOT BEEN FINISHED! ***/
+/*****************************************************************************
+* chpms.c - Network MicroSoft Challenge Handshake Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 by Global Election Systems Inc.  All rights reserved.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-08 Guy Lancaster , Global Election Systems Inc.
+*   Original based on BSD chap_ms.c.
+*****************************************************************************/
+/*
+ * chap_ms.c - Microsoft MS-CHAP compatible implementation.
+ *
+ * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited.
+ * http://www.strataware.com/
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Eric Rosenquist.  The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+/*
+ * Modifications by Lauri Pesonen / lpesonen@clinet.fi, april 1997
+ *
+ *   Implemented LANManager type password response to MS-CHAP challenges.
+ *   Now pppd provides both NT style and LANMan style blocks, and the
+ *   prefered is set by option "ms-lanman". Default is to use NT.
+ *   The hash text (StdText) was taken from Win95 RASAPI32.DLL.
+ *
+ *   You should also use DOMAIN\\USERNAME as described in README.MSCHAP80
+ */
+
+#define USE_CRYPT
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#if MSCHAP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "md4.h"
+#ifndef USE_CRYPT
+#include "des.h"
+#endif
+#include "chap.h"
+#include "chpms.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+typedef struct {
+    u_char LANManResp[24];
+    u_char NTResp[24];
+    u_char UseNT; /* If 1, ignore the LANMan response field */
+} MS_ChapResponse;
+/* We use MS_CHAP_RESPONSE_LEN, rather than sizeof(MS_ChapResponse),
+   in case this struct gets padded. */
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+
+/* XXX Don't know what to do with these. */
+extern void setkey(const char *);
+extern void encrypt(char *, int);
+
+static void DesEncrypt (u_char *, u_char *, u_char *);
+static void MakeKey (u_char *, u_char *);
+
+#ifdef USE_CRYPT
+static void Expand (u_char *, u_char *);
+static void Collapse (u_char *, u_char *);
+#endif
+
+static void ChallengeResponse(
+  u_char *challenge, /* IN   8 octets */
+  u_char *pwHash,    /* IN  16 octets */
+  u_char *response   /* OUT 24 octets */
+);
+static void ChapMS_NT(
+  char *rchallenge,
+  int rchallenge_len,
+  char *secret,
+  int secret_len,
+  MS_ChapResponse *response
+);
+static u_char Get7Bits(
+  u_char *input,
+  int startBit
+);
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+void
+ChapMS( chap_state *cstate, char *rchallenge, int rchallenge_len, char *secret, int secret_len)
+{
+  MS_ChapResponse response;
+#ifdef MSLANMAN
+  extern int ms_lanman;
+#endif
+
+#if 0
+  CHAPDEBUG((LOG_INFO, "ChapMS: secret is '%.*s'\n", secret_len, secret));
+#endif
+  BZERO(&response, sizeof(response));
+
+  /* Calculate both always */
+  ChapMS_NT(rchallenge, rchallenge_len, secret, secret_len, &response);
+
+#ifdef MSLANMAN
+  ChapMS_LANMan(rchallenge, rchallenge_len, secret, secret_len, &response);
+
+  /* prefered method is set by option  */
+  response.UseNT = !ms_lanman;
+#else
+  response.UseNT = 1;
+#endif
+
+  BCOPY(&response, cstate->response, MS_CHAP_RESPONSE_LEN);
+  cstate->resp_length = MS_CHAP_RESPONSE_LEN;
+}
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+static void
+ChallengeResponse( u_char *challenge, /* IN   8 octets */
+                   u_char *pwHash,    /* IN  16 octets */
+                   u_char *response   /* OUT 24 octets */)
+{
+  char    ZPasswordHash[21];
+
+  BZERO(ZPasswordHash, sizeof(ZPasswordHash));
+  BCOPY(pwHash, ZPasswordHash, 16);
+
+#if 0
+  log_packet(ZPasswordHash, sizeof(ZPasswordHash), "ChallengeResponse - ZPasswordHash", LOG_DEBUG);
+#endif
+
+  DesEncrypt(challenge, ZPasswordHash +  0, response + 0);
+  DesEncrypt(challenge, ZPasswordHash +  7, response + 8);
+  DesEncrypt(challenge, ZPasswordHash + 14, response + 16);
+
+#if 0
+  log_packet(response, 24, "ChallengeResponse - response", LOG_DEBUG);
+#endif
+}
+
+
+#ifdef USE_CRYPT
+static void
+DesEncrypt( u_char *clear, /* IN  8 octets */
+            u_char *key,   /* IN  7 octets */
+            u_char *cipher /* OUT 8 octets */)
+{
+  u_char des_key[8];
+  u_char crypt_key[66];
+  u_char des_input[66];
+
+  MakeKey(key, des_key);
+
+  Expand(des_key, crypt_key);
+  setkey(crypt_key);
+
+#if 0
+  CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n",
+             clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7]));
+#endif
+
+  Expand(clear, des_input);
+  encrypt(des_input, 0);
+  Collapse(des_input, cipher);
+
+#if 0
+  CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+             cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7]));
+#endif
+}
+
+#else /* USE_CRYPT */
+
+static void
+DesEncrypt( u_char *clear, /* IN  8 octets */
+            u_char *key,   /* IN  7 octets */
+            u_char *cipher /* OUT 8 octets */)
+{
+  des_cblock    des_key;
+  des_key_schedule  key_schedule;
+
+  MakeKey(key, des_key);
+
+  des_set_key(&des_key, key_schedule);
+
+#if 0
+  CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n",
+             clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7]));
+#endif
+
+  des_ecb_encrypt((des_cblock *)clear, (des_cblock *)cipher, key_schedule, 1);
+
+#if 0
+  CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+             cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7]));
+#endif
+}
+
+#endif /* USE_CRYPT */
+
+
+static u_char
+Get7Bits( u_char *input, int startBit)
+{
+  register unsigned int  word;
+
+  word  = (unsigned)input[startBit / 8] << 8;
+  word |= (unsigned)input[startBit / 8 + 1];
+
+  word >>= 15 - (startBit % 8 + 7);
+
+  return word & 0xFE;
+}
+
+#ifdef USE_CRYPT
+
+/* in == 8-byte string (expanded version of the 56-bit key)
+ * out == 64-byte string where each byte is either 1 or 0
+ * Note that the low-order "bit" is always ignored by by setkey()
+ */
+static void
+Expand(u_char *in, u_char *out)
+{
+  int j, c;
+  int i;
+
+  for(i = 0; i < 64; in++){
+    c = *in;
+    for(j = 7; j >= 0; j--) {
+      *out++ = (c >> j) & 01;
+    }
+    i += 8;
+  }
+}
+
+/* The inverse of Expand
+ */
+static void
+Collapse(u_char *in, u_char *out)
+{
+  int j;
+  int i;
+  unsigned int c;
+
+  for (i = 0; i < 64; i += 8, out++) {
+    c = 0;
+    for (j = 7; j >= 0; j--, in++) {
+      c |= *in << j;
+    }
+    *out = c & 0xff;
+  }
+}
+#endif
+
+static void
+MakeKey( u_char *key,    /* IN  56 bit DES key missing parity bits */
+         u_char *des_key /* OUT 64 bit DES key with parity bits added */)
+{
+  des_key[0] = Get7Bits(key,  0);
+  des_key[1] = Get7Bits(key,  7);
+  des_key[2] = Get7Bits(key, 14);
+  des_key[3] = Get7Bits(key, 21);
+  des_key[4] = Get7Bits(key, 28);
+  des_key[5] = Get7Bits(key, 35);
+  des_key[6] = Get7Bits(key, 42);
+  des_key[7] = Get7Bits(key, 49);
+  
+#ifndef USE_CRYPT
+  des_set_odd_parity((des_cblock *)des_key);
+#endif
+  
+#if 0
+  CHAPDEBUG((LOG_INFO, "MakeKey: 56-bit input : %02X%02X%02X%02X%02X%02X%02X\n",
+             key[0], key[1], key[2], key[3], key[4], key[5], key[6]));
+  CHAPDEBUG((LOG_INFO, "MakeKey: 64-bit output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+             des_key[0], des_key[1], des_key[2], des_key[3], des_key[4], des_key[5], des_key[6], des_key[7]));
+#endif
+}
+
+static void
+ChapMS_NT( char *rchallenge,
+           int rchallenge_len,
+           char *secret,
+           int secret_len,
+           MS_ChapResponse *response)
+{
+  int      i;
+  MDstruct  md4Context;
+  u_char    unicodePassword[MAX_NT_PASSWORD * 2];
+  static int  low_byte_first = -1;
+
+  /* Initialize the Unicode version of the secret (== password). */
+  /* This implicitly supports 8-bit ISO8859/1 characters. */
+  BZERO(unicodePassword, sizeof(unicodePassword));
+  for (i = 0; i < secret_len; i++) {
+    unicodePassword[i * 2] = (u_char)secret[i];
+  }
+  MDbegin(&md4Context);
+  MDupdate(&md4Context, unicodePassword, secret_len * 2 * 8);  /* Unicode is 2 bytes/char, *8 for bit count */
+
+  if (low_byte_first == -1) {
+    low_byte_first = (htons((unsigned short int)1) != 1);
+  }
+  if (low_byte_first == 0) {
+    MDreverse((u_long *)&md4Context);  /*  sfb 961105 */
+  }
+
+  MDupdate(&md4Context, NULL, 0);  /* Tell MD4 we're done */
+
+  ChallengeResponse(rchallenge, (char *)md4Context.buffer, response->NTResp);
+}
+
+#ifdef MSLANMAN
+static u_char *StdText = (u_char *)"KGS!@#$%"; /* key from rasapi32.dll */
+
+static void
+ChapMS_LANMan( char *rchallenge,
+               int rchallenge_len,
+               char *secret,
+               int secret_len,
+               MS_ChapResponse  *response)
+{
+  int      i;
+  u_char    UcasePassword[MAX_NT_PASSWORD]; /* max is actually 14 */
+  u_char    PasswordHash[16];
+  
+  /* LANMan password is case insensitive */
+  BZERO(UcasePassword, sizeof(UcasePassword));
+  for (i = 0; i < secret_len; i++) {
+    UcasePassword[i] = (u_char)toupper(secret[i]);
+  }
+  DesEncrypt( StdText, UcasePassword + 0, PasswordHash + 0 );
+  DesEncrypt( StdText, UcasePassword + 7, PasswordHash + 8 );
+  ChallengeResponse(rchallenge, PasswordHash, response->LANManResp);
+}
+#endif
+
+#endif /* MSCHAP_SUPPORT */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/chpms.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/chpms.h
new file mode 100644
index 0000000..f023cce
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/chpms.h
@@ -0,0 +1,64 @@
+/*****************************************************************************
+* chpms.h - Network Microsoft Challenge Handshake Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-01-30 Guy Lancaster , Global Election Systems Inc.
+*   Original built from BSD network code.
+******************************************************************************/
+/*
+ * chap.h - Challenge Handshake Authentication Protocol definitions.
+ *
+ * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited.
+ * http://www.strataware.com/
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Eric Rosenquist.  The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: chpms.h,v 1.5 2007/12/19 20:47:23 fbernon Exp $
+ */
+
+#ifndef CHPMS_H
+#define CHPMS_H
+
+#define MAX_NT_PASSWORD 256 /* Maximum number of (Unicode) chars in an NT password */
+
+void ChapMS (chap_state *, char *, int, char *, int);
+
+#endif /* CHPMS_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/fsm.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/fsm.c
new file mode 100644
index 0000000..8c2fab4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/fsm.c
@@ -0,0 +1,906 @@
+/*****************************************************************************
+* fsm.c - Network Control Protocol Finite State Machine program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-01 Guy Lancaster , Global Election Systems Inc.
+*   Original based on BSD fsm.c.
+*****************************************************************************/
+/*
+ * fsm.c - {Link, IP} Control Protocol Finite State Machine.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+/*
+ * TODO:
+ * Randomize fsm id on link/init.
+ * Deal with variable outgoing MTU.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "fsm.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+#if PPP_DEBUG
+
+static const char *ppperr_strerr[] = {
+           "LS_INITIAL",  /* LS_INITIAL  0 */
+           "LS_STARTING", /* LS_STARTING 1 */
+           "LS_CLOSED",   /* LS_CLOSED   2 */
+           "LS_STOPPED",  /* LS_STOPPED  3 */
+           "LS_CLOSING",  /* LS_CLOSING  4 */
+           "LS_STOPPING", /* LS_STOPPING 5 */
+           "LS_REQSENT",  /* LS_REQSENT  6 */
+           "LS_ACKRCVD",  /* LS_ACKRCVD  7 */
+           "LS_ACKSENT",  /* LS_ACKSENT  8 */
+           "LS_OPENED"    /* LS_OPENED   9 */
+};
+
+#endif /* PPP_DEBUG */
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+static void fsm_timeout (void *);
+static void fsm_rconfreq (fsm *, u_char, u_char *, int);
+static void fsm_rconfack (fsm *, int, u_char *, int);
+static void fsm_rconfnakrej (fsm *, int, int, u_char *, int);
+static void fsm_rtermreq (fsm *, int, u_char *, int);
+static void fsm_rtermack (fsm *);
+static void fsm_rcoderej (fsm *, u_char *, int);
+static void fsm_sconfreq (fsm *, int);
+
+#define PROTO_NAME(f) ((f)->callbacks->proto_name)
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+int peer_mru[NUM_PPP];
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+
+/*
+ * fsm_init - Initialize fsm.
+ *
+ * Initialize fsm state.
+ */
+void
+fsm_init(fsm *f)
+{
+  f->state = LS_INITIAL;
+  f->flags = 0;
+  f->id = 0;        /* XXX Start with random id? */
+  f->timeouttime = FSM_DEFTIMEOUT;
+  f->maxconfreqtransmits = FSM_DEFMAXCONFREQS;
+  f->maxtermtransmits = FSM_DEFMAXTERMREQS;
+  f->maxnakloops = FSM_DEFMAXNAKLOOPS;
+  f->term_reason_len = 0;
+}
+
+
+/*
+ * fsm_lowerup - The lower layer is up.
+ */
+void
+fsm_lowerup(fsm *f)
+{
+  int oldState = f->state;
+
+  LWIP_UNUSED_ARG(oldState);
+
+  switch( f->state ) {
+    case LS_INITIAL:
+      f->state = LS_CLOSED;
+      break;
+
+    case LS_STARTING:
+      if( f->flags & OPT_SILENT ) {
+        f->state = LS_STOPPED;
+      } else {
+        /* Send an initial configure-request */
+        fsm_sconfreq(f, 0);
+        f->state = LS_REQSENT;
+      }
+    break;
+
+    default:
+      FSMDEBUG((LOG_INFO, "%s: Up event in state %d (%s)!\n",
+          PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+  }
+  
+  FSMDEBUG((LOG_INFO, "%s: lowerup state %d (%s) -> %d (%s)\n",
+      PROTO_NAME(f), oldState, ppperr_strerr[oldState], f->state, ppperr_strerr[f->state]));
+}
+
+
+/*
+ * fsm_lowerdown - The lower layer is down.
+ *
+ * Cancel all timeouts and inform upper layers.
+ */
+void
+fsm_lowerdown(fsm *f)
+{
+  int oldState = f->state;
+
+  LWIP_UNUSED_ARG(oldState);
+
+  switch( f->state ) {
+    case LS_CLOSED:
+      f->state = LS_INITIAL;
+      break;
+
+    case LS_STOPPED:
+      f->state = LS_STARTING;
+      if( f->callbacks->starting ) {
+        (*f->callbacks->starting)(f);
+      }
+      break;
+
+    case LS_CLOSING:
+      f->state = LS_INITIAL;
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      break;
+
+    case LS_STOPPING:
+    case LS_REQSENT:
+    case LS_ACKRCVD:
+    case LS_ACKSENT:
+      f->state = LS_STARTING;
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      break;
+
+    case LS_OPENED:
+      if( f->callbacks->down ) {
+        (*f->callbacks->down)(f);
+      }
+      f->state = LS_STARTING;
+      break;
+
+    default:
+      FSMDEBUG((LOG_INFO, "%s: Down event in state %d (%s)!\n",
+          PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+  }
+
+  FSMDEBUG((LOG_INFO, "%s: lowerdown state %d (%s) -> %d (%s)\n",
+      PROTO_NAME(f), oldState, ppperr_strerr[oldState], f->state, ppperr_strerr[f->state]));
+}
+
+
+/*
+ * fsm_open - Link is allowed to come up.
+ */
+void
+fsm_open(fsm *f)
+{
+  int oldState = f->state;
+
+  LWIP_UNUSED_ARG(oldState);
+
+  switch( f->state ) {
+    case LS_INITIAL:
+      f->state = LS_STARTING;
+      if( f->callbacks->starting ) {
+        (*f->callbacks->starting)(f);
+      }
+      break;
+
+    case LS_CLOSED:
+      if( f->flags & OPT_SILENT ) {
+        f->state = LS_STOPPED;
+      } else {
+        /* Send an initial configure-request */
+        fsm_sconfreq(f, 0);
+        f->state = LS_REQSENT;
+      }
+      break;
+  
+    case LS_CLOSING:
+      f->state = LS_STOPPING;
+      /* fall through */
+    case LS_STOPPED:
+    case LS_OPENED:
+      if( f->flags & OPT_RESTART ) {
+        fsm_lowerdown(f);
+        fsm_lowerup(f);
+      }
+      break;
+  }
+
+  FSMDEBUG((LOG_INFO, "%s: open state %d (%s) -> %d (%s)\n",
+      PROTO_NAME(f), oldState, ppperr_strerr[oldState], f->state, ppperr_strerr[f->state]));
+}
+
+
+/*
+ * fsm_close - Start closing connection.
+ *
+ * Cancel timeouts and either initiate close or possibly go directly to
+ * the LS_CLOSED state.
+ */
+void
+fsm_close(fsm *f, char *reason)
+{
+  int oldState = f->state;
+
+  LWIP_UNUSED_ARG(oldState);
+
+  f->term_reason = reason;
+  f->term_reason_len = (reason == NULL? 0: strlen(reason));
+  switch( f->state ) {
+    case LS_STARTING:
+      f->state = LS_INITIAL;
+      break;
+    case LS_STOPPED:
+      f->state = LS_CLOSED;
+      break;
+    case LS_STOPPING:
+      f->state = LS_CLOSING;
+      break;
+
+    case LS_REQSENT:
+    case LS_ACKRCVD:
+    case LS_ACKSENT:
+    case LS_OPENED:
+      if( f->state != LS_OPENED ) {
+        UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      } else if( f->callbacks->down ) {
+        (*f->callbacks->down)(f);  /* Inform upper layers we're down */
+      }
+      /* Init restart counter, send Terminate-Request */
+      f->retransmits = f->maxtermtransmits;
+      fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+            (u_char *) f->term_reason, f->term_reason_len);
+      TIMEOUT(fsm_timeout, f, f->timeouttime);
+      --f->retransmits;
+
+      f->state = LS_CLOSING;
+      break;
+  }
+
+  FSMDEBUG((LOG_INFO, "%s: close reason=%s state %d (%s) -> %d (%s)\n",
+      PROTO_NAME(f), reason, oldState, ppperr_strerr[oldState], f->state, ppperr_strerr[f->state]));
+}
+
+
+/*
+ * fsm_sdata - Send some data.
+ *
+ * Used for all packets sent to our peer by this module.
+ */
+void
+fsm_sdata( fsm *f, u_char code, u_char id, u_char *data, int datalen)
+{
+  u_char *outp;
+  int outlen;
+
+  /* Adjust length to be smaller than MTU */
+  outp = outpacket_buf[f->unit];
+  if (datalen > peer_mru[f->unit] - (int)HEADERLEN) {
+    datalen = peer_mru[f->unit] - HEADERLEN;
+  }
+  if (datalen && data != outp + PPP_HDRLEN + HEADERLEN) {
+    BCOPY(data, outp + PPP_HDRLEN + HEADERLEN, datalen);
+  }
+  outlen = datalen + HEADERLEN;
+  MAKEHEADER(outp, f->protocol);
+  PUTCHAR(code, outp);
+  PUTCHAR(id, outp);
+  PUTSHORT(outlen, outp);
+  pppWrite(f->unit, outpacket_buf[f->unit], outlen + PPP_HDRLEN);
+  FSMDEBUG((LOG_INFO, "fsm_sdata(%s): Sent code %d,%d,%d.\n",
+        PROTO_NAME(f), code, id, outlen));
+}
+
+
+/*
+ * fsm_input - Input packet.
+ */
+void
+fsm_input(fsm *f, u_char *inpacket, int l)
+{
+  u_char *inp = inpacket;
+  u_char code, id;
+  int len;
+
+  /*
+  * Parse header (code, id and length).
+  * If packet too short, drop it.
+  */
+  if (l < HEADERLEN) {
+    FSMDEBUG((LOG_WARNING, "fsm_input(%x): Rcvd short header.\n",
+          f->protocol));
+    return;
+  }
+  GETCHAR(code, inp);
+  GETCHAR(id, inp);
+  GETSHORT(len, inp);
+  if (len < HEADERLEN) {
+    FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd illegal length.\n",
+        f->protocol));
+    return;
+  }
+  if (len > l) {
+    FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd short packet.\n",
+        f->protocol));
+    return;
+  }
+  len -= HEADERLEN;    /* subtract header length */
+
+  if( f->state == LS_INITIAL || f->state == LS_STARTING ) {
+    FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd packet in state %d (%s).\n",
+        f->protocol, f->state, ppperr_strerr[f->state]));
+    return;
+  }
+  FSMDEBUG((LOG_INFO, "fsm_input(%s):%d,%d,%d\n", PROTO_NAME(f), code, id, l));
+  /*
+   * Action depends on code.
+   */
+  switch (code) {
+    case CONFREQ:
+      fsm_rconfreq(f, id, inp, len);
+      break;
+    
+    case CONFACK:
+      fsm_rconfack(f, id, inp, len);
+      break;
+    
+    case CONFNAK:
+    case CONFREJ:
+      fsm_rconfnakrej(f, code, id, inp, len);
+      break;
+    
+    case TERMREQ:
+      fsm_rtermreq(f, id, inp, len);
+      break;
+    
+    case TERMACK:
+      fsm_rtermack(f);
+      break;
+    
+    case CODEREJ:
+      fsm_rcoderej(f, inp, len);
+      break;
+    
+    default:
+      if( !f->callbacks->extcode ||
+          !(*f->callbacks->extcode)(f, code, id, inp, len) ) {
+        fsm_sdata(f, CODEREJ, ++f->id, inpacket, len + HEADERLEN);
+      }
+      break;
+  }
+}
+
+
+/*
+ * fsm_protreject - Peer doesn't speak this protocol.
+ *
+ * Treat this as a catastrophic error (RXJ-).
+ */
+void
+fsm_protreject(fsm *f)
+{
+  switch( f->state ) {
+    case LS_CLOSING:
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      /* fall through */
+    case LS_CLOSED:
+      f->state = LS_CLOSED;
+      if( f->callbacks->finished ) {
+        (*f->callbacks->finished)(f);
+      }
+      break;
+
+    case LS_STOPPING:
+    case LS_REQSENT:
+    case LS_ACKRCVD:
+    case LS_ACKSENT:
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      /* fall through */
+    case LS_STOPPED:
+      f->state = LS_STOPPED;
+      if( f->callbacks->finished ) {
+        (*f->callbacks->finished)(f);
+      }
+      break;
+    
+    case LS_OPENED:
+      if( f->callbacks->down ) {
+        (*f->callbacks->down)(f);
+      }
+      /* Init restart counter, send Terminate-Request */
+      f->retransmits = f->maxtermtransmits;
+      fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+            (u_char *) f->term_reason, f->term_reason_len);
+      TIMEOUT(fsm_timeout, f, f->timeouttime);
+      --f->retransmits;
+      
+      f->state = LS_STOPPING;
+      break;
+    
+    default:
+      FSMDEBUG((LOG_INFO, "%s: Protocol-reject event in state %d (%s)!\n",
+            PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+    }
+}
+
+
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+
+/*
+ * fsm_timeout - Timeout expired.
+ */
+static void
+fsm_timeout(void *arg)
+{
+  fsm *f = (fsm *) arg;
+
+  switch (f->state) {
+    case LS_CLOSING:
+    case LS_STOPPING:
+      if( f->retransmits <= 0 ) {
+        FSMDEBUG((LOG_WARNING, "%s: timeout sending Terminate-Request state=%d (%s)\n",
+             PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+        /*
+         * We've waited for an ack long enough.  Peer probably heard us.
+         */
+        f->state = (f->state == LS_CLOSING)? LS_CLOSED: LS_STOPPED;
+        if( f->callbacks->finished ) {
+          (*f->callbacks->finished)(f);
+        }
+      } else {
+        FSMDEBUG((LOG_WARNING, "%s: timeout resending Terminate-Requests state=%d (%s)\n",
+             PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+        /* Send Terminate-Request */
+        fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+            (u_char *) f->term_reason, f->term_reason_len);
+        TIMEOUT(fsm_timeout, f, f->timeouttime);
+        --f->retransmits;
+      }
+      break;
+
+    case LS_REQSENT:
+    case LS_ACKRCVD:
+    case LS_ACKSENT:
+      if (f->retransmits <= 0) {
+        FSMDEBUG((LOG_WARNING, "%s: timeout sending Config-Requests state=%d (%s)\n",
+         PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+        f->state = LS_STOPPED;
+        if( (f->flags & OPT_PASSIVE) == 0 && f->callbacks->finished ) {
+          (*f->callbacks->finished)(f);
+        }
+      } else {
+        FSMDEBUG((LOG_WARNING, "%s: timeout resending Config-Request state=%d (%s)\n",
+         PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+        /* Retransmit the configure-request */
+        if (f->callbacks->retransmit) {
+          (*f->callbacks->retransmit)(f);
+        }
+        fsm_sconfreq(f, 1);    /* Re-send Configure-Request */
+        if( f->state == LS_ACKRCVD ) {
+          f->state = LS_REQSENT;
+        }
+      }
+      break;
+
+    default:
+      FSMDEBUG((LOG_INFO, "%s: Timeout event in state %d (%s)!\n",
+          PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+  }
+}
+
+
+/*
+ * fsm_rconfreq - Receive Configure-Request.
+ */
+static void
+fsm_rconfreq(fsm *f, u_char id, u_char *inp, int len)
+{
+  int code, reject_if_disagree;
+
+  FSMDEBUG((LOG_INFO, "fsm_rconfreq(%s): Rcvd id %d state=%d (%s)\n", 
+        PROTO_NAME(f), id, f->state, ppperr_strerr[f->state]));
+  switch( f->state ) {
+    case LS_CLOSED:
+      /* Go away, we're closed */
+      fsm_sdata(f, TERMACK, id, NULL, 0);
+      return;
+    case LS_CLOSING:
+    case LS_STOPPING:
+      return;
+
+    case LS_OPENED:
+      /* Go down and restart negotiation */
+      if( f->callbacks->down ) {
+        (*f->callbacks->down)(f);  /* Inform upper layers */
+      }
+      fsm_sconfreq(f, 0);    /* Send initial Configure-Request */
+      break;
+
+    case LS_STOPPED:
+      /* Negotiation started by our peer */
+      fsm_sconfreq(f, 0);    /* Send initial Configure-Request */
+      f->state = LS_REQSENT;
+      break;
+  }
+  
+  /*
+  * Pass the requested configuration options
+  * to protocol-specific code for checking.
+  */
+  if (f->callbacks->reqci) {    /* Check CI */
+    reject_if_disagree = (f->nakloops >= f->maxnakloops);
+    code = (*f->callbacks->reqci)(f, inp, &len, reject_if_disagree);
+  } else if (len) {
+    code = CONFREJ;      /* Reject all CI */
+  } else {
+    code = CONFACK;
+  }
+  
+  /* send the Ack, Nak or Rej to the peer */
+  fsm_sdata(f, (u_char)code, id, inp, len);
+  
+  if (code == CONFACK) {
+    if (f->state == LS_ACKRCVD) {
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      f->state = LS_OPENED;
+      if (f->callbacks->up) {
+        (*f->callbacks->up)(f);  /* Inform upper layers */
+      }
+    } else {
+      f->state = LS_ACKSENT;
+    }
+    f->nakloops = 0;
+  } else {
+    /* we sent CONFACK or CONFREJ */
+    if (f->state != LS_ACKRCVD) {
+      f->state = LS_REQSENT;
+    }
+    if( code == CONFNAK ) {
+      ++f->nakloops;
+    }
+  }
+}
+
+
+/*
+ * fsm_rconfack - Receive Configure-Ack.
+ */
+static void
+fsm_rconfack(fsm *f, int id, u_char *inp, int len)
+{
+  FSMDEBUG((LOG_INFO, "fsm_rconfack(%s): Rcvd id %d state=%d (%s)\n",
+        PROTO_NAME(f), id, f->state, ppperr_strerr[f->state]));
+  
+  if (id != f->reqid || f->seen_ack) {   /* Expected id? */
+    return; /* Nope, toss... */
+  }
+  if( !(f->callbacks->ackci? (*f->callbacks->ackci)(f, inp, len): (len == 0)) ) {
+    /* Ack is bad - ignore it */
+    FSMDEBUG((LOG_INFO, "%s: received bad Ack (length %d)\n",
+          PROTO_NAME(f), len));
+    return;
+  }
+  f->seen_ack = 1;
+  
+  switch (f->state) {
+    case LS_CLOSED:
+    case LS_STOPPED:
+      fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+      break;
+    
+    case LS_REQSENT:
+      f->state = LS_ACKRCVD;
+      f->retransmits = f->maxconfreqtransmits;
+      break;
+    
+    case LS_ACKRCVD:
+      /* Huh? an extra valid Ack? oh well... */
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      fsm_sconfreq(f, 0);
+      f->state = LS_REQSENT;
+      break;
+    
+    case LS_ACKSENT:
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      f->state = LS_OPENED;
+      f->retransmits = f->maxconfreqtransmits;
+      if (f->callbacks->up) {
+        (*f->callbacks->up)(f);  /* Inform upper layers */
+      }
+      break;
+    
+    case LS_OPENED:
+      /* Go down and restart negotiation */
+      if (f->callbacks->down) {
+        (*f->callbacks->down)(f);  /* Inform upper layers */
+      }
+      fsm_sconfreq(f, 0);    /* Send initial Configure-Request */
+      f->state = LS_REQSENT;
+      break;
+  }
+}
+
+
+/*
+ * fsm_rconfnakrej - Receive Configure-Nak or Configure-Reject.
+ */
+static void
+fsm_rconfnakrej(fsm *f, int code, int id, u_char *inp, int len)
+{
+  int (*proc) (fsm *, u_char *, int);
+  int ret;
+
+  FSMDEBUG((LOG_INFO, "fsm_rconfnakrej(%s): Rcvd id %d state=%d (%s)\n",
+        PROTO_NAME(f), id, f->state, ppperr_strerr[f->state]));
+
+  if (id != f->reqid || f->seen_ack) { /* Expected id? */
+    return;        /* Nope, toss... */
+  }
+  proc = (code == CONFNAK)? f->callbacks->nakci: f->callbacks->rejci;
+  if (!proc || !((ret = proc(f, inp, len)))) {
+    /* Nak/reject is bad - ignore it */
+    FSMDEBUG((LOG_INFO, "%s: received bad %s (length %d)\n",
+          PROTO_NAME(f), (code==CONFNAK? "Nak": "reject"), len));
+    return;
+  }
+  f->seen_ack = 1;
+
+  switch (f->state) {
+    case LS_CLOSED:
+    case LS_STOPPED:
+      fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+      break;
+    
+    case LS_REQSENT:
+    case LS_ACKSENT:
+      /* They didn't agree to what we wanted - try another request */
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      if (ret < 0) {
+        f->state = LS_STOPPED;    /* kludge for stopping CCP */
+      } else {
+        fsm_sconfreq(f, 0);    /* Send Configure-Request */
+      }
+      break;
+    
+    case LS_ACKRCVD:
+      /* Got a Nak/reject when we had already had an Ack?? oh well... */
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      fsm_sconfreq(f, 0);
+      f->state = LS_REQSENT;
+      break;
+    
+    case LS_OPENED:
+      /* Go down and restart negotiation */
+      if (f->callbacks->down) {
+        (*f->callbacks->down)(f);  /* Inform upper layers */
+      }
+      fsm_sconfreq(f, 0);    /* Send initial Configure-Request */
+      f->state = LS_REQSENT;
+      break;
+  }
+}
+
+
+/*
+ * fsm_rtermreq - Receive Terminate-Req.
+ */
+static void
+fsm_rtermreq(fsm *f, int id, u_char *p, int len)
+{
+  LWIP_UNUSED_ARG(p);
+
+  FSMDEBUG((LOG_INFO, "fsm_rtermreq(%s): Rcvd id %d state=%d (%s)\n",
+        PROTO_NAME(f), id, f->state, ppperr_strerr[f->state]));
+
+  switch (f->state) {
+    case LS_ACKRCVD:
+    case LS_ACKSENT:
+      f->state = LS_REQSENT;    /* Start over but keep trying */
+      break;
+
+    case LS_OPENED:
+      if (len > 0) {
+        FSMDEBUG((LOG_INFO, "%s terminated by peer (%x)\n", PROTO_NAME(f), p));
+      } else {
+        FSMDEBUG((LOG_INFO, "%s terminated by peer\n", PROTO_NAME(f)));
+      }
+      if (f->callbacks->down) {
+        (*f->callbacks->down)(f);  /* Inform upper layers */
+      }
+      f->retransmits = 0;
+      f->state = LS_STOPPING;
+      TIMEOUT(fsm_timeout, f, f->timeouttime);
+      break;
+  }
+
+  fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+}
+
+
+/*
+ * fsm_rtermack - Receive Terminate-Ack.
+ */
+static void
+fsm_rtermack(fsm *f)
+{
+  FSMDEBUG((LOG_INFO, "fsm_rtermack(%s): state=%d (%s)\n", 
+        PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+  
+  switch (f->state) {
+    case LS_CLOSING:
+      UNTIMEOUT(fsm_timeout, f);
+      f->state = LS_CLOSED;
+      if( f->callbacks->finished ) {
+        (*f->callbacks->finished)(f);
+      }
+      break;
+
+    case LS_STOPPING:
+      UNTIMEOUT(fsm_timeout, f);
+      f->state = LS_STOPPED;
+      if( f->callbacks->finished ) {
+        (*f->callbacks->finished)(f);
+      }
+      break;
+    
+    case LS_ACKRCVD:
+      f->state = LS_REQSENT;
+      break;
+    
+    case LS_OPENED:
+      if (f->callbacks->down) {
+        (*f->callbacks->down)(f);  /* Inform upper layers */
+      }
+      fsm_sconfreq(f, 0);
+      break;
+  }
+}
+
+
+/*
+ * fsm_rcoderej - Receive an Code-Reject.
+ */
+static void
+fsm_rcoderej(fsm *f, u_char *inp, int len)
+{
+  u_char code, id;
+  
+  FSMDEBUG((LOG_INFO, "fsm_rcoderej(%s): state=%d (%s)\n", 
+        PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+  
+  if (len < HEADERLEN) {
+    FSMDEBUG((LOG_INFO, "fsm_rcoderej: Rcvd short Code-Reject packet!\n"));
+    return;
+  }
+  GETCHAR(code, inp);
+  GETCHAR(id, inp);
+  FSMDEBUG((LOG_WARNING, "%s: Rcvd Code-Reject for code %d, id %d\n",
+        PROTO_NAME(f), code, id));
+  
+  if( f->state == LS_ACKRCVD ) {
+    f->state = LS_REQSENT;
+  }
+}
+
+
+/*
+ * fsm_sconfreq - Send a Configure-Request.
+ */
+static void
+fsm_sconfreq(fsm *f, int retransmit)
+{
+  u_char *outp;
+  int cilen;
+  
+  if( f->state != LS_REQSENT && f->state != LS_ACKRCVD && f->state != LS_ACKSENT ) {
+    /* Not currently negotiating - reset options */
+    if( f->callbacks->resetci ) {
+      (*f->callbacks->resetci)(f);
+    }
+    f->nakloops = 0;
+  }
+  
+  if( !retransmit ) {
+    /* New request - reset retransmission counter, use new ID */
+    f->retransmits = f->maxconfreqtransmits;
+    f->reqid = ++f->id;
+  }
+  
+  f->seen_ack = 0;
+  
+  /*
+   * Make up the request packet
+   */
+  outp = outpacket_buf[f->unit] + PPP_HDRLEN + HEADERLEN;
+  if( f->callbacks->cilen && f->callbacks->addci ) {
+    cilen = (*f->callbacks->cilen)(f);
+    if( cilen > peer_mru[f->unit] - (int)HEADERLEN ) {
+      cilen = peer_mru[f->unit] - HEADERLEN;
+    }
+    if (f->callbacks->addci) {
+      (*f->callbacks->addci)(f, outp, &cilen);
+    }
+  } else {
+    cilen = 0;
+  }
+
+  /* send the request to our peer */
+  fsm_sdata(f, CONFREQ, f->reqid, outp, cilen);
+  
+  /* start the retransmit timer */
+  --f->retransmits;
+  TIMEOUT(fsm_timeout, f, f->timeouttime);
+  
+  FSMDEBUG((LOG_INFO, "%s: sending Configure-Request, id %d\n",
+        PROTO_NAME(f), f->reqid));
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/fsm.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/fsm.h
new file mode 100644
index 0000000..02af4ee
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/fsm.h
@@ -0,0 +1,169 @@
+/*****************************************************************************
+* fsm.h - Network Control Protocol Finite State Machine header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*   Original based on BSD code.
+*****************************************************************************/
+/*
+ * fsm.h - {Link, IP} Control Protocol Finite State Machine definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: fsm.h,v 1.4 2007/12/19 20:47:23 fbernon Exp $
+ */
+
+#ifndef FSM_H
+#define FSM_H
+
+/*****************************************************************************
+************************* PUBLIC DEFINITIONS *********************************
+*****************************************************************************/
+/*
+ * LCP Packet header = Code, id, length.
+ */
+#define HEADERLEN (sizeof (u_char) + sizeof (u_char) + sizeof (u_short))
+
+
+/*
+ *  CP (LCP, IPCP, etc.) codes.
+ */
+#define CONFREQ     1 /* Configuration Request */
+#define CONFACK     2 /* Configuration Ack */
+#define CONFNAK     3 /* Configuration Nak */
+#define CONFREJ     4 /* Configuration Reject */
+#define TERMREQ     5 /* Termination Request */
+#define TERMACK     6 /* Termination Ack */
+#define CODEREJ     7 /* Code Reject */
+
+/*
+ * Link states.
+ */
+#define LS_INITIAL  0 /* Down, hasn't been opened */
+#define LS_STARTING 1 /* Down, been opened */
+#define LS_CLOSED   2 /* Up, hasn't been opened */
+#define LS_STOPPED  3 /* Open, waiting for down event */
+#define LS_CLOSING  4 /* Terminating the connection, not open */
+#define LS_STOPPING 5 /* Terminating, but open */
+#define LS_REQSENT  6 /* We've sent a Config Request */
+#define LS_ACKRCVD  7 /* We've received a Config Ack */
+#define LS_ACKSENT  8 /* We've sent a Config Ack */
+#define LS_OPENED   9 /* Connection available */
+
+/*
+ * Flags - indicate options controlling FSM operation
+ */
+#define OPT_PASSIVE 1 /* Don't die if we don't get a response */
+#define OPT_RESTART 2 /* Treat 2nd OPEN as DOWN, UP */
+#define OPT_SILENT  4 /* Wait for peer to speak first */
+
+
+/*****************************************************************************
+************************* PUBLIC DATA TYPES **********************************
+*****************************************************************************/
+/*
+ * Each FSM is described by an fsm structure and fsm callbacks.
+ */
+typedef struct fsm {
+  int unit;                        /* Interface unit number */
+  u_short protocol;                /* Data Link Layer Protocol field value */
+  int state;                       /* State */
+  int flags;                       /* Contains option bits */
+  u_char id;                       /* Current id */
+  u_char reqid;                    /* Current request id */
+  u_char seen_ack;                 /* Have received valid Ack/Nak/Rej to Req */
+  int timeouttime;                 /* Timeout time in milliseconds */
+  int maxconfreqtransmits;         /* Maximum Configure-Request transmissions */
+  int retransmits;                 /* Number of retransmissions left */
+  int maxtermtransmits;            /* Maximum Terminate-Request transmissions */
+  int nakloops;                    /* Number of nak loops since last ack */
+  int maxnakloops;                 /* Maximum number of nak loops tolerated */
+  struct fsm_callbacks* callbacks; /* Callback routines */
+  char* term_reason;               /* Reason for closing protocol */
+  int term_reason_len;             /* Length of term_reason */
+} fsm;
+
+
+typedef struct fsm_callbacks {
+  void (*resetci)(fsm*);                            /* Reset our Configuration Information */
+  int  (*cilen)(fsm*);                              /* Length of our Configuration Information */
+  void (*addci)(fsm*, u_char*, int*);               /* Add our Configuration Information */
+  int  (*ackci)(fsm*, u_char*, int);                /* ACK our Configuration Information */
+  int  (*nakci)(fsm*, u_char*, int);                /* NAK our Configuration Information */
+  int  (*rejci)(fsm*, u_char*, int);                /* Reject our Configuration Information */
+  int  (*reqci)(fsm*, u_char*, int*, int);          /* Request peer's Configuration Information */
+  void (*up)(fsm*);                                 /* Called when fsm reaches LS_OPENED state */
+  void (*down)(fsm*);                               /* Called when fsm leaves LS_OPENED state */
+  void (*starting)(fsm*);                           /* Called when we want the lower layer */
+  void (*finished)(fsm*);                           /* Called when we don't want the lower layer */
+  void (*protreject)(int);                          /* Called when Protocol-Reject received */
+  void (*retransmit)(fsm*);                         /* Retransmission is necessary */
+  int  (*extcode)(fsm*, int, u_char, u_char*, int); /* Called when unknown code received */
+  char *proto_name;                                 /* String name for protocol (for messages) */
+} fsm_callbacks;
+
+
+/*****************************************************************************
+*********************** PUBLIC DATA STRUCTURES *******************************
+*****************************************************************************/
+/*
+ * Variables
+ */
+extern int peer_mru[]; /* currently negotiated peer MRU (per unit) */
+
+
+/*****************************************************************************
+************************** PUBLIC FUNCTIONS **********************************
+*****************************************************************************/
+
+/*
+ * Prototypes
+ */
+void fsm_init (fsm*);
+void fsm_lowerup (fsm*);
+void fsm_lowerdown (fsm*);
+void fsm_open (fsm*);
+void fsm_close (fsm*, char*);
+void fsm_input (fsm*, u_char*, int);
+void fsm_protreject (fsm*);
+void fsm_sdata (fsm*, u_char, u_char, u_char*, int);
+
+#endif /* FSM_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/ipcp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/ipcp.c
new file mode 100644
index 0000000..7567091
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/ipcp.c
@@ -0,0 +1,1440 @@
+/*****************************************************************************
+* ipcp.c - Network PPP IP Control Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-08 Guy Lancaster , Global Election Systems Inc.
+*   Original.
+*****************************************************************************/
+/*
+ * ipcp.c - PPP IP Control Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "auth.h"
+#include "fsm.h"
+#include "vj.h"
+#include "ipcp.h"
+
+#include 
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+/* #define OLD_CI_ADDRS 1 */ /* Support deprecated address negotiation. */
+
+/*
+ * Lengths of configuration options.
+ */
+#define CILEN_VOID     2
+#define CILEN_COMPRESS 4  /* min length for compression protocol opt. */
+#define CILEN_VJ       6  /* length for RFC1332 Van-Jacobson opt. */
+#define CILEN_ADDR     6  /* new-style single address option */
+#define CILEN_ADDRS    10 /* old-style dual address option */
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Callbacks for fsm code.  (CI = Configuration Information)
+ */
+static void ipcp_resetci (fsm *);                     /* Reset our CI */
+static int  ipcp_cilen (fsm *);                       /* Return length of our CI */
+static void ipcp_addci (fsm *, u_char *, int *);      /* Add our CI */
+static int  ipcp_ackci (fsm *, u_char *, int);        /* Peer ack'd our CI */
+static int  ipcp_nakci (fsm *, u_char *, int);        /* Peer nak'd our CI */
+static int  ipcp_rejci (fsm *, u_char *, int);        /* Peer rej'd our CI */
+static int  ipcp_reqci (fsm *, u_char *, int *, int); /* Rcv CI */
+static void ipcp_up (fsm *);                          /* We're UP */
+static void ipcp_down (fsm *);                        /* We're DOWN */
+#if 0
+static void ipcp_script (fsm *, char *); /* Run an up/down script */
+#endif
+static void ipcp_finished (fsm *);                    /* Don't need lower layer */
+
+/*
+ * Protocol entry points from main code.
+ */
+static void ipcp_init (int);
+static void ipcp_open (int);
+static void ipcp_close (int, char *);
+static void ipcp_lowerup (int);
+static void ipcp_lowerdown (int);
+static void ipcp_input (int, u_char *, int);
+static void ipcp_protrej (int);
+
+static void ipcp_clear_addrs (int);
+
+#define CODENAME(x) ((x) == CONFACK ? "ACK" : \
+                     (x) == CONFNAK ? "NAK" : "REJ")
+
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+/* global vars */
+ipcp_options ipcp_wantoptions[NUM_PPP];  /* Options that we want to request */
+ipcp_options ipcp_gotoptions[NUM_PPP];   /* Options that peer ack'd */
+ipcp_options ipcp_allowoptions[NUM_PPP]; /* Options we allow peer to request */
+ipcp_options ipcp_hisoptions[NUM_PPP];   /* Options that we ack'd */
+
+fsm ipcp_fsm[NUM_PPP]; /* IPCP fsm structure */
+
+struct protent ipcp_protent = {
+  PPP_IPCP,
+  ipcp_init,
+  ipcp_input,
+  ipcp_protrej,
+  ipcp_lowerup,
+  ipcp_lowerdown,
+  ipcp_open,
+  ipcp_close,
+#if 0
+  ipcp_printpkt,
+  NULL,
+#endif
+  1,
+  "IPCP",
+#if 0
+  ip_check_options,
+  NULL,
+  ip_active_pkt
+#endif
+};
+
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+/* local vars */
+static int cis_received[NUM_PPP];      /* # Conf-Reqs received */
+static int default_route_set[NUM_PPP]; /* Have set up a default route */
+
+static fsm_callbacks ipcp_callbacks = { /* IPCP callback routines */
+  ipcp_resetci,  /* Reset our Configuration Information */
+  ipcp_cilen,    /* Length of our Configuration Information */
+  ipcp_addci,    /* Add our Configuration Information */
+  ipcp_ackci,    /* ACK our Configuration Information */
+  ipcp_nakci,    /* NAK our Configuration Information */
+  ipcp_rejci,    /* Reject our Configuration Information */
+  ipcp_reqci,    /* Request peer's Configuration Information */
+  ipcp_up,       /* Called when fsm reaches LS_OPENED state */
+  ipcp_down,     /* Called when fsm leaves LS_OPENED state */
+  NULL,          /* Called when we want the lower layer up */
+  ipcp_finished, /* Called when we want the lower layer down */
+  NULL,          /* Called when Protocol-Reject received */
+  NULL,          /* Retransmission is necessary */
+  NULL,          /* Called to handle protocol-specific codes */
+  "IPCP"         /* String name of protocol */
+};
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+
+/*
+ * Non-standard inet_ntoa left here for compat with original ppp
+ * sources. Assumes u32_t instead of struct in_addr.
+ */ 
+
+char *
+_inet_ntoa(u32_t n)
+{
+  struct in_addr ia;
+  ia.s_addr = n;
+  return inet_ntoa(ia);
+}
+
+#define inet_ntoa _inet_ntoa
+
+/*
+ * ipcp_init - Initialize IPCP.
+ */
+static void
+ipcp_init(int unit)
+{
+  fsm           *f = &ipcp_fsm[unit];
+  ipcp_options *wo = &ipcp_wantoptions[unit];
+  ipcp_options *ao = &ipcp_allowoptions[unit];
+
+  f->unit      = unit;
+  f->protocol  = PPP_IPCP;
+  f->callbacks = &ipcp_callbacks;
+  fsm_init(&ipcp_fsm[unit]);
+
+  memset(wo, 0, sizeof(*wo));
+  memset(ao, 0, sizeof(*ao));
+
+  wo->neg_addr      = 1;
+  wo->ouraddr       = 0;
+#if VJ_SUPPORT
+  wo->neg_vj        = 1;
+#else  /* VJ_SUPPORT */
+  wo->neg_vj        = 0;
+#endif /* VJ_SUPPORT */
+  wo->vj_protocol   = IPCP_VJ_COMP;
+  wo->maxslotindex  = MAX_SLOTS - 1;
+  wo->cflag         = 0;
+  wo->default_route = 1;
+
+  ao->neg_addr      = 1;
+#if VJ_SUPPORT
+  ao->neg_vj        = 1;
+#else  /* VJ_SUPPORT */
+  ao->neg_vj        = 0;
+#endif /* VJ_SUPPORT */
+  ao->maxslotindex  = MAX_SLOTS - 1;
+  ao->cflag         = 1;
+  ao->default_route = 1;
+}
+
+
+/*
+ * ipcp_open - IPCP is allowed to come up.
+ */
+static void
+ipcp_open(int unit)
+{
+  fsm_open(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_close - Take IPCP down.
+ */
+static void
+ipcp_close(int unit, char *reason)
+{
+  fsm_close(&ipcp_fsm[unit], reason);
+}
+
+
+/*
+ * ipcp_lowerup - The lower layer is up.
+ */
+static void
+ipcp_lowerup(int unit)
+{
+  fsm_lowerup(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_lowerdown - The lower layer is down.
+ */
+static void
+ipcp_lowerdown(int unit)
+{
+  fsm_lowerdown(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_input - Input IPCP packet.
+ */
+static void
+ipcp_input(int unit, u_char *p, int len)
+{
+  fsm_input(&ipcp_fsm[unit], p, len);
+}
+
+
+/*
+ * ipcp_protrej - A Protocol-Reject was received for IPCP.
+ *
+ * Pretend the lower layer went down, so we shut up.
+ */
+static void
+ipcp_protrej(int unit)
+{
+  fsm_lowerdown(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_resetci - Reset our CI.
+ */
+static void
+ipcp_resetci(fsm *f)
+{
+  ipcp_options *wo = &ipcp_wantoptions[f->unit];
+  
+  wo->req_addr = wo->neg_addr && ipcp_allowoptions[f->unit].neg_addr;
+  if (wo->ouraddr == 0) {
+    wo->accept_local = 1;
+  }
+  if (wo->hisaddr == 0) {
+    wo->accept_remote = 1;
+  }
+  /* Request DNS addresses from the peer */
+  wo->req_dns1 = ppp_settings.usepeerdns;
+  wo->req_dns2 = ppp_settings.usepeerdns;
+  ipcp_gotoptions[f->unit] = *wo;
+  cis_received[f->unit] = 0;
+}
+
+
+/*
+ * ipcp_cilen - Return length of our CI.
+ */
+static int
+ipcp_cilen(fsm *f)
+{
+  ipcp_options *go = &ipcp_gotoptions[f->unit];
+  ipcp_options *wo = &ipcp_wantoptions[f->unit];
+  ipcp_options *ho = &ipcp_hisoptions[f->unit];
+
+#define LENCIVJ(neg, old)   (neg ? (old? CILEN_COMPRESS : CILEN_VJ) : 0)
+#define LENCIADDR(neg, old) (neg ? (old? CILEN_ADDRS : CILEN_ADDR) : 0)
+#define LENCIDNS(neg)       (neg ? (CILEN_ADDR) : 0)
+
+  /*
+   * First see if we want to change our options to the old
+   * forms because we have received old forms from the peer.
+   */
+  if (wo->neg_addr && !go->neg_addr && !go->old_addrs) {
+    /* use the old style of address negotiation */
+    go->neg_addr = 1;
+    go->old_addrs = 1;
+  }
+  if (wo->neg_vj && !go->neg_vj && !go->old_vj) {
+    /* try an older style of VJ negotiation */
+    if (cis_received[f->unit] == 0) {
+      /* keep trying the new style until we see some CI from the peer */
+      go->neg_vj = 1;
+    } else {
+      /* use the old style only if the peer did */
+      if (ho->neg_vj && ho->old_vj) {
+        go->neg_vj = 1;
+        go->old_vj = 1;
+        go->vj_protocol = ho->vj_protocol;
+      }
+    }
+  }
+
+  return (LENCIADDR(go->neg_addr, go->old_addrs) +
+          LENCIVJ(go->neg_vj, go->old_vj) +
+          LENCIDNS(go->req_dns1) +
+          LENCIDNS(go->req_dns2));
+}
+
+
+/*
+ * ipcp_addci - Add our desired CIs to a packet.
+ */
+static void
+ipcp_addci(fsm *f, u_char *ucp, int *lenp)
+{
+  ipcp_options *go = &ipcp_gotoptions[f->unit];
+  int len = *lenp;
+
+#define ADDCIVJ(opt, neg, val, old, maxslotindex, cflag) \
+  if (neg) { \
+    int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \
+    if (len >= vjlen) { \
+      PUTCHAR(opt, ucp); \
+      PUTCHAR(vjlen, ucp); \
+      PUTSHORT(val, ucp); \
+      if (!old) { \
+        PUTCHAR(maxslotindex, ucp); \
+        PUTCHAR(cflag, ucp); \
+      } \
+      len -= vjlen; \
+    } else { \
+      neg = 0; \
+    } \
+  }
+
+#define ADDCIADDR(opt, neg, old, val1, val2) \
+  if (neg) { \
+    int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \
+    if (len >= addrlen) { \
+      u32_t l; \
+      PUTCHAR(opt, ucp); \
+      PUTCHAR(addrlen, ucp); \
+      l = ntohl(val1); \
+      PUTLONG(l, ucp); \
+      if (old) { \
+        l = ntohl(val2); \
+        PUTLONG(l, ucp); \
+      } \
+      len -= addrlen; \
+    } else { \
+      neg = 0; \
+    } \
+  }
+
+#define ADDCIDNS(opt, neg, addr) \
+  if (neg) { \
+    if (len >= CILEN_ADDR) { \
+      u32_t l; \
+      PUTCHAR(opt, ucp); \
+      PUTCHAR(CILEN_ADDR, ucp); \
+      l = ntohl(addr); \
+      PUTLONG(l, ucp); \
+      len -= CILEN_ADDR; \
+    } else { \
+      neg = 0; \
+    } \
+  }
+
+  ADDCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr,
+      go->old_addrs, go->ouraddr, go->hisaddr);
+
+  ADDCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj,
+      go->maxslotindex, go->cflag);
+
+  ADDCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]);
+
+  ADDCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]);
+
+  *lenp -= len;
+}
+
+
+/*
+ * ipcp_ackci - Ack our CIs.
+ *
+ * Returns:
+ *  0 - Ack was bad.
+ *  1 - Ack was good.
+ */
+static int
+ipcp_ackci(fsm *f, u_char *p, int len)
+{
+  ipcp_options *go = &ipcp_gotoptions[f->unit];
+  u_short cilen, citype, cishort;
+  u32_t cilong;
+  u_char cimaxslotindex, cicflag;
+
+  /*
+   * CIs must be in exactly the same order that we sent...
+   * Check packet length and CI length at each step.
+   * If we find any deviations, then this packet is bad.
+   */
+
+#define ACKCIVJ(opt, neg, val, old, maxslotindex, cflag) \
+  if (neg) { \
+    int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \
+    if ((len -= vjlen) < 0) { \
+      goto bad; \
+    } \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != vjlen || \
+        citype != opt) { \
+      goto bad; \
+    } \
+    GETSHORT(cishort, p); \
+    if (cishort != val) { \
+      goto bad; \
+    } \
+    if (!old) { \
+      GETCHAR(cimaxslotindex, p); \
+      if (cimaxslotindex != maxslotindex) { \
+        goto bad; \
+      } \
+      GETCHAR(cicflag, p); \
+      if (cicflag != cflag) { \
+        goto bad; \
+      } \
+    } \
+  }
+  
+#define ACKCIADDR(opt, neg, old, val1, val2) \
+  if (neg) { \
+    int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \
+    u32_t l; \
+    if ((len -= addrlen) < 0) { \
+      goto bad; \
+    } \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != addrlen || \
+        citype != opt) { \
+      goto bad; \
+    } \
+    GETLONG(l, p); \
+    cilong = htonl(l); \
+    if (val1 != cilong) { \
+      goto bad; \
+    } \
+    if (old) { \
+      GETLONG(l, p); \
+      cilong = htonl(l); \
+      if (val2 != cilong) { \
+        goto bad; \
+      } \
+    } \
+  }
+
+#define ACKCIDNS(opt, neg, addr) \
+  if (neg) { \
+    u32_t l; \
+    if ((len -= CILEN_ADDR) < 0) { \
+      goto bad; \
+    } \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != CILEN_ADDR || \
+        citype != opt) { \
+      goto bad; \
+    } \
+    GETLONG(l, p); \
+    cilong = htonl(l); \
+    if (addr != cilong) { \
+      goto bad; \
+    } \
+  }
+
+  ACKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr,
+        go->old_addrs, go->ouraddr, go->hisaddr);
+
+  ACKCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj,
+      go->maxslotindex, go->cflag);
+
+  ACKCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]);
+
+  ACKCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]);
+
+  /*
+   * If there are any remaining CIs, then this packet is bad.
+   */
+  if (len != 0) {
+    goto bad;
+  }
+  return (1);
+  
+bad:
+  IPCPDEBUG((LOG_INFO, "ipcp_ackci: received bad Ack!\n"));
+  return (0);
+}
+
+/*
+ * ipcp_nakci - Peer has sent a NAK for some of our CIs.
+ * This should not modify any state if the Nak is bad
+ * or if IPCP is in the LS_OPENED state.
+ *
+ * Returns:
+ *  0 - Nak was bad.
+ *  1 - Nak was good.
+ */
+static int
+ipcp_nakci(fsm *f, u_char *p, int len)
+{
+  ipcp_options *go = &ipcp_gotoptions[f->unit];
+  u_char cimaxslotindex, cicflag;
+  u_char citype, cilen, *next;
+  u_short cishort;
+  u32_t ciaddr1, ciaddr2, l, cidnsaddr;
+  ipcp_options no;    /* options we've seen Naks for */
+  ipcp_options try;    /* options to request next time */
+
+  BZERO(&no, sizeof(no));
+  try = *go;
+
+  /*
+   * Any Nak'd CIs must be in exactly the same order that we sent.
+   * Check packet length and CI length at each step.
+   * If we find any deviations, then this packet is bad.
+   */
+#define NAKCIADDR(opt, neg, old, code) \
+  if (go->neg && \
+      len >= (cilen = (old? CILEN_ADDRS: CILEN_ADDR)) && \
+      p[1] == cilen && \
+      p[0] == opt) { \
+    len -= cilen; \
+    INCPTR(2, p); \
+    GETLONG(l, p); \
+    ciaddr1 = htonl(l); \
+    if (old) { \
+      GETLONG(l, p); \
+      ciaddr2 = htonl(l); \
+      no.old_addrs = 1; \
+    } else { \
+      ciaddr2 = 0; \
+    } \
+    no.neg = 1; \
+    code \
+  }
+
+#define NAKCIVJ(opt, neg, code) \
+  if (go->neg && \
+      ((cilen = p[1]) == CILEN_COMPRESS || cilen == CILEN_VJ) && \
+      len >= cilen && \
+      p[0] == opt) { \
+    len -= cilen; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    no.neg = 1; \
+    code \
+  }
+  
+#define NAKCIDNS(opt, neg, code) \
+  if (go->neg && \
+      ((cilen = p[1]) == CILEN_ADDR) && \
+      len >= cilen && \
+      p[0] == opt) { \
+    len -= cilen; \
+    INCPTR(2, p); \
+    GETLONG(l, p); \
+    cidnsaddr = htonl(l); \
+    no.neg = 1; \
+    code \
+  }
+
+  /*
+   * Accept the peer's idea of {our,his} address, if different
+   * from our idea, only if the accept_{local,remote} flag is set.
+   */
+  NAKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr, go->old_addrs,
+    if (go->accept_local && ciaddr1) { /* Do we know our address? */
+      try.ouraddr = ciaddr1;
+      IPCPDEBUG((LOG_INFO, "local IP address %s\n",
+           inet_ntoa(ciaddr1)));
+    }
+    if (go->accept_remote && ciaddr2) { /* Does he know his? */
+      try.hisaddr = ciaddr2;
+      IPCPDEBUG((LOG_INFO, "remote IP address %s\n",
+           inet_ntoa(ciaddr2)));
+    }
+  );
+
+  /*
+   * Accept the peer's value of maxslotindex provided that it
+   * is less than what we asked for.  Turn off slot-ID compression
+   * if the peer wants.  Send old-style compress-type option if
+   * the peer wants.
+   */
+  NAKCIVJ(CI_COMPRESSTYPE, neg_vj,
+    if (cilen == CILEN_VJ) {
+      GETCHAR(cimaxslotindex, p);
+      GETCHAR(cicflag, p);
+      if (cishort == IPCP_VJ_COMP) {
+        try.old_vj = 0;
+        if (cimaxslotindex < go->maxslotindex) {
+          try.maxslotindex = cimaxslotindex;
+        }
+        if (!cicflag) {
+          try.cflag = 0;
+        }
+      } else {
+        try.neg_vj = 0;
+      }
+    } else {
+      if (cishort == IPCP_VJ_COMP || cishort == IPCP_VJ_COMP_OLD) {
+        try.old_vj = 1;
+        try.vj_protocol = cishort;
+      } else {
+        try.neg_vj = 0;
+      }
+    }
+  );
+
+  NAKCIDNS(CI_MS_DNS1, req_dns1,
+      try.dnsaddr[0] = cidnsaddr;
+        IPCPDEBUG((LOG_INFO, "primary DNS address %s\n", inet_ntoa(cidnsaddr)));
+      );
+
+  NAKCIDNS(CI_MS_DNS2, req_dns2,
+      try.dnsaddr[1] = cidnsaddr;
+        IPCPDEBUG((LOG_INFO, "secondary DNS address %s\n", inet_ntoa(cidnsaddr)));
+      );
+
+  /*
+  * There may be remaining CIs, if the peer is requesting negotiation
+  * on an option that we didn't include in our request packet.
+  * If they want to negotiate about IP addresses, we comply.
+  * If they want us to ask for compression, we refuse.
+  */
+  while (len > CILEN_VOID) {
+    GETCHAR(citype, p);
+    GETCHAR(cilen, p);
+    if( (len -= cilen) < 0 ) {
+      goto bad;
+    }
+    next = p + cilen - 2;
+
+    switch (citype) {
+      case CI_COMPRESSTYPE:
+        if (go->neg_vj || no.neg_vj ||
+            (cilen != CILEN_VJ && cilen != CILEN_COMPRESS)) {
+          goto bad;
+        }
+        no.neg_vj = 1;
+        break;
+      case CI_ADDRS:
+        if ((go->neg_addr && go->old_addrs) || no.old_addrs
+            || cilen != CILEN_ADDRS) {
+          goto bad;
+        }
+        try.neg_addr = 1;
+        try.old_addrs = 1;
+        GETLONG(l, p);
+        ciaddr1 = htonl(l);
+        if (ciaddr1 && go->accept_local) {
+          try.ouraddr = ciaddr1;
+        }
+        GETLONG(l, p);
+        ciaddr2 = htonl(l);
+        if (ciaddr2 && go->accept_remote) {
+          try.hisaddr = ciaddr2;
+        }
+        no.old_addrs = 1;
+        break;
+      case CI_ADDR:
+        if (go->neg_addr || no.neg_addr || cilen != CILEN_ADDR) {
+          goto bad;
+        }
+        try.old_addrs = 0;
+        GETLONG(l, p);
+        ciaddr1 = htonl(l);
+        if (ciaddr1 && go->accept_local) {
+          try.ouraddr = ciaddr1;
+        }
+        if (try.ouraddr != 0) {
+          try.neg_addr = 1;
+        }
+        no.neg_addr = 1;
+        break;
+    }
+    p = next;
+  }
+
+  /* If there is still anything left, this packet is bad. */
+  if (len != 0) {
+    goto bad;
+  }
+
+  /*
+   * OK, the Nak is good.  Now we can update state.
+   */
+  if (f->state != LS_OPENED) {
+    *go = try;
+  }
+
+  return 1;
+
+bad:
+  IPCPDEBUG((LOG_INFO, "ipcp_nakci: received bad Nak!\n"));
+  return 0;
+}
+
+
+/*
+ * ipcp_rejci - Reject some of our CIs.
+ */
+static int
+ipcp_rejci(fsm *f, u_char *p, int len)
+{
+  ipcp_options *go = &ipcp_gotoptions[f->unit];
+  u_char cimaxslotindex, ciflag, cilen;
+  u_short cishort;
+  u32_t cilong;
+  ipcp_options try;    /* options to request next time */
+
+  try = *go;
+  /*
+   * Any Rejected CIs must be in exactly the same order that we sent.
+   * Check packet length and CI length at each step.
+   * If we find any deviations, then this packet is bad.
+   */
+#define REJCIADDR(opt, neg, old, val1, val2) \
+  if (go->neg && \
+      len >= (cilen = old? CILEN_ADDRS: CILEN_ADDR) && \
+      p[1] == cilen && \
+      p[0] == opt) { \
+    u32_t l; \
+    len -= cilen; \
+    INCPTR(2, p); \
+    GETLONG(l, p); \
+    cilong = htonl(l); \
+    /* Check rejected value. */ \
+    if (cilong != val1) { \
+      goto bad; \
+    } \
+    if (old) { \
+      GETLONG(l, p); \
+      cilong = htonl(l); \
+      /* Check rejected value. */ \
+      if (cilong != val2) { \
+        goto bad; \
+      } \
+    } \
+    try.neg = 0; \
+  }
+
+#define REJCIVJ(opt, neg, val, old, maxslot, cflag) \
+  if (go->neg && \
+      p[1] == (old? CILEN_COMPRESS : CILEN_VJ) && \
+      len >= p[1] && \
+      p[0] == opt) { \
+    len -= p[1]; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    /* Check rejected value. */  \
+    if (cishort != val) { \
+      goto bad; \
+    } \
+    if (!old) { \
+      GETCHAR(cimaxslotindex, p); \
+      if (cimaxslotindex != maxslot) { \
+        goto bad; \
+      } \
+      GETCHAR(ciflag, p); \
+      if (ciflag != cflag) { \
+        goto bad; \
+      } \
+    } \
+    try.neg = 0; \
+  }
+
+#define REJCIDNS(opt, neg, dnsaddr) \
+  if (go->neg && \
+      ((cilen = p[1]) == CILEN_ADDR) && \
+      len >= cilen && \
+      p[0] == opt) { \
+    u32_t l; \
+    len -= cilen; \
+    INCPTR(2, p); \
+    GETLONG(l, p); \
+    cilong = htonl(l); \
+    /* Check rejected value. */ \
+    if (cilong != dnsaddr) { \
+      goto bad; \
+    } \
+    try.neg = 0; \
+  }
+
+  REJCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr,
+        go->old_addrs, go->ouraddr, go->hisaddr);
+
+  REJCIVJ(CI_COMPRESSTYPE, neg_vj, go->vj_protocol, go->old_vj,
+      go->maxslotindex, go->cflag);
+
+  REJCIDNS(CI_MS_DNS1, req_dns1, go->dnsaddr[0]);
+
+  REJCIDNS(CI_MS_DNS2, req_dns2, go->dnsaddr[1]);
+
+  /*
+   * If there are any remaining CIs, then this packet is bad.
+   */
+  if (len != 0) {
+    goto bad;
+  }
+  /*
+   * Now we can update state.
+   */
+  if (f->state != LS_OPENED) {
+    *go = try;
+  }
+  return 1;
+
+bad:
+  IPCPDEBUG((LOG_INFO, "ipcp_rejci: received bad Reject!\n"));
+  return 0;
+}
+
+
+/*
+ * ipcp_reqci - Check the peer's requested CIs and send appropriate response.
+ *
+ * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified
+ * appropriately.  If reject_if_disagree is non-zero, doesn't return
+ * CONFNAK; returns CONFREJ if it can't return CONFACK.
+ */
+static int
+ipcp_reqci(fsm *f, u_char *inp/* Requested CIs */,int *len/* Length of requested CIs */,int reject_if_disagree)
+{
+  ipcp_options *wo = &ipcp_wantoptions[f->unit];
+  ipcp_options *ho = &ipcp_hisoptions[f->unit];
+  ipcp_options *ao = &ipcp_allowoptions[f->unit];
+#ifdef OLD_CI_ADDRS
+  ipcp_options *go = &ipcp_gotoptions[f->unit];
+#endif
+  u_char *cip, *next;     /* Pointer to current and next CIs */
+  u_short cilen, citype;  /* Parsed len, type */
+  u_short cishort;        /* Parsed short value */
+  u32_t tl, ciaddr1;      /* Parsed address values */
+#ifdef OLD_CI_ADDRS
+  u32_t ciaddr2;          /* Parsed address values */
+#endif
+  int rc = CONFACK;       /* Final packet return code */
+  int orc;                /* Individual option return code */
+  u_char *p;              /* Pointer to next char to parse */
+  u_char *ucp = inp;      /* Pointer to current output char */
+  int l = *len;           /* Length left */
+  u_char maxslotindex, cflag;
+  int d;
+
+  cis_received[f->unit] = 1;
+
+  /*
+   * Reset all his options.
+   */
+  BZERO(ho, sizeof(*ho));
+
+  /*
+   * Process all his options.
+   */
+  next = inp;
+  while (l) {
+    orc = CONFACK;       /* Assume success */
+    cip = p = next;      /* Remember begining of CI */
+    if (l < 2 ||         /* Not enough data for CI header or */
+        p[1] < 2 ||      /*  CI length too small or */
+        p[1] > l) {      /*  CI length too big? */
+      IPCPDEBUG((LOG_INFO, "ipcp_reqci: bad CI length!\n"));
+      orc = CONFREJ;     /* Reject bad CI */
+      cilen = l;         /* Reject till end of packet */
+      l = 0;             /* Don't loop again */
+      goto endswitch;
+    }
+    GETCHAR(citype, p);  /* Parse CI type */
+    GETCHAR(cilen, p);   /* Parse CI length */
+    l -= cilen;          /* Adjust remaining length */
+    next += cilen;       /* Step to next CI */
+
+    switch (citype) {      /* Check CI type */
+#ifdef OLD_CI_ADDRS /* Need to save space... */
+      case CI_ADDRS:
+        IPCPDEBUG((LOG_INFO, "ipcp_reqci: received ADDRS\n"));
+        if (!ao->neg_addr ||
+            cilen != CILEN_ADDRS) {  /* Check CI length */
+          orc = CONFREJ;    /* Reject CI */
+          break;
+        }
+
+        /*
+         * If he has no address, or if we both have his address but
+         * disagree about it, then NAK it with our idea.
+         * In particular, if we don't know his address, but he does,
+         * then accept it.
+         */
+        GETLONG(tl, p);    /* Parse source address (his) */
+        ciaddr1 = htonl(tl);
+        IPCPDEBUG((LOG_INFO, "his addr %s\n", inet_ntoa(ciaddr1)));
+        if (ciaddr1 != wo->hisaddr
+            && (ciaddr1 == 0 || !wo->accept_remote)) {
+          orc = CONFNAK;
+          if (!reject_if_disagree) {
+            DECPTR(sizeof(u32_t), p);
+            tl = ntohl(wo->hisaddr);
+            PUTLONG(tl, p);
+          }
+        } else if (ciaddr1 == 0 && wo->hisaddr == 0) {
+          /*
+           * If neither we nor he knows his address, reject the option.
+           */
+          orc = CONFREJ;
+          wo->req_addr = 0;  /* don't NAK with 0.0.0.0 later */
+          break;
+        }
+
+        /*
+         * If he doesn't know our address, or if we both have our address
+         * but disagree about it, then NAK it with our idea.
+         */
+        GETLONG(tl, p);    /* Parse desination address (ours) */
+        ciaddr2 = htonl(tl);
+        IPCPDEBUG((LOG_INFO, "our addr %s\n", inet_ntoa(ciaddr2)));
+        if (ciaddr2 != wo->ouraddr) {
+          if (ciaddr2 == 0 || !wo->accept_local) {
+            orc = CONFNAK;
+            if (!reject_if_disagree) {
+              DECPTR(sizeof(u32_t), p);
+              tl = ntohl(wo->ouraddr);
+              PUTLONG(tl, p);
+            }
+          } else {
+            go->ouraddr = ciaddr2;  /* accept peer's idea */
+          }
+        }
+
+        ho->neg_addr = 1;
+        ho->old_addrs = 1;
+        ho->hisaddr = ciaddr1;
+        ho->ouraddr = ciaddr2;
+        break;
+#endif
+
+      case CI_ADDR:
+        if (!ao->neg_addr) {
+          IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR not allowed\n"));
+          orc = CONFREJ;        /* Reject CI */
+          break;
+        } else if (cilen != CILEN_ADDR) {  /* Check CI length */
+          IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR bad len\n"));
+          orc = CONFREJ;        /* Reject CI */
+          break;
+        }
+
+        /*
+         * If he has no address, or if we both have his address but
+         * disagree about it, then NAK it with our idea.
+         * In particular, if we don't know his address, but he does,
+         * then accept it.
+         */
+        GETLONG(tl, p);  /* Parse source address (his) */
+        ciaddr1 = htonl(tl);
+        if (ciaddr1 != wo->hisaddr
+            && (ciaddr1 == 0 || !wo->accept_remote)) {
+          orc = CONFNAK;
+          if (!reject_if_disagree) {
+            DECPTR(sizeof(u32_t), p);
+            tl = ntohl(wo->hisaddr);
+            PUTLONG(tl, p);
+          }
+          IPCPDEBUG((LOG_INFO, "ipcp_reqci: Nak ADDR %s\n", inet_ntoa(ciaddr1)));
+        } else if (ciaddr1 == 0 && wo->hisaddr == 0) {
+          /*
+           * Don't ACK an address of 0.0.0.0 - reject it instead.
+           */
+          IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR %s\n", inet_ntoa(ciaddr1)));
+          orc = CONFREJ;
+          wo->req_addr = 0;  /* don't NAK with 0.0.0.0 later */
+          break;
+        }
+
+        ho->neg_addr = 1;
+        ho->hisaddr = ciaddr1;
+        IPCPDEBUG((LOG_INFO, "ipcp_reqci: ADDR %s\n", inet_ntoa(ciaddr1)));
+        break;
+
+      case CI_MS_DNS1:
+      case CI_MS_DNS2:
+        /* Microsoft primary or secondary DNS request */
+        d = citype == CI_MS_DNS2;
+
+        /* If we do not have a DNS address then we cannot send it */
+        if (ao->dnsaddr[d] == 0 ||
+            cilen != CILEN_ADDR) {  /* Check CI length */
+          IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting DNS%d Request\n", d+1));
+          orc = CONFREJ;        /* Reject CI */
+          break;
+        }
+        GETLONG(tl, p);
+        if (htonl(tl) != ao->dnsaddr[d]) {
+          IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking DNS%d Request %d\n",
+                d+1, inet_ntoa(tl)));
+          DECPTR(sizeof(u32_t), p);
+          tl = ntohl(ao->dnsaddr[d]);
+          PUTLONG(tl, p);
+          orc = CONFNAK;
+        }
+        IPCPDEBUG((LOG_INFO, "ipcp_reqci: received DNS%d Request\n", d+1));
+        break;
+
+      case CI_MS_WINS1:
+      case CI_MS_WINS2:
+        /* Microsoft primary or secondary WINS request */
+        d = citype == CI_MS_WINS2;
+        IPCPDEBUG((LOG_INFO, "ipcp_reqci: received WINS%d Request\n", d+1));
+
+        /* If we do not have a DNS address then we cannot send it */
+        if (ao->winsaddr[d] == 0 ||
+          cilen != CILEN_ADDR) {  /* Check CI length */
+          orc = CONFREJ;      /* Reject CI */
+          break;
+        }
+        GETLONG(tl, p);
+        if (htonl(tl) != ao->winsaddr[d]) {
+          DECPTR(sizeof(u32_t), p);
+          tl = ntohl(ao->winsaddr[d]);
+          PUTLONG(tl, p);
+          orc = CONFNAK;
+        }
+        break;
+
+      case CI_COMPRESSTYPE:
+        if (!ao->neg_vj) {
+          IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE not allowed\n"));
+          orc = CONFREJ;
+          break;
+        } else if (cilen != CILEN_VJ && cilen != CILEN_COMPRESS) {
+          IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE len=%d\n", cilen));
+          orc = CONFREJ;
+          break;
+        }
+        GETSHORT(cishort, p);
+
+        if (!(cishort == IPCP_VJ_COMP ||
+            (cishort == IPCP_VJ_COMP_OLD && cilen == CILEN_COMPRESS))) {
+          IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE %d\n", cishort));
+          orc = CONFREJ;
+          break;
+        }
+
+        ho->neg_vj = 1;
+        ho->vj_protocol = cishort;
+        if (cilen == CILEN_VJ) {
+          GETCHAR(maxslotindex, p);
+          if (maxslotindex > ao->maxslotindex) { 
+            IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ max slot %d\n", maxslotindex));
+            orc = CONFNAK;
+            if (!reject_if_disagree) {
+              DECPTR(1, p);
+              PUTCHAR(ao->maxslotindex, p);
+            }
+          }
+          GETCHAR(cflag, p);
+          if (cflag && !ao->cflag) {
+            IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ cflag %d\n", cflag));
+            orc = CONFNAK;
+            if (!reject_if_disagree) {
+              DECPTR(1, p);
+              PUTCHAR(wo->cflag, p);
+            }
+          }
+          ho->maxslotindex = maxslotindex;
+          ho->cflag = cflag;
+        } else {
+          ho->old_vj = 1;
+          ho->maxslotindex = MAX_SLOTS - 1;
+          ho->cflag = 1;
+        }
+        IPCPDEBUG((LOG_INFO, 
+              "ipcp_reqci: received COMPRESSTYPE p=%d old=%d maxslot=%d cflag=%d\n",
+              ho->vj_protocol, ho->old_vj, ho->maxslotindex, ho->cflag));
+        break;
+
+      default:
+        IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting unknown CI type %d\n", citype));
+        orc = CONFREJ;
+        break;
+    }
+
+endswitch:
+    if (orc == CONFACK &&    /* Good CI */
+        rc != CONFACK) {     /*  but prior CI wasnt? */
+      continue;              /* Don't send this one */
+    }
+
+    if (orc == CONFNAK) {    /* Nak this CI? */
+      if (reject_if_disagree) {  /* Getting fed up with sending NAKs? */
+        IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting too many naks\n"));
+        orc = CONFREJ;       /* Get tough if so */
+      } else {
+        if (rc == CONFREJ) { /* Rejecting prior CI? */
+          continue;          /* Don't send this one */
+        }
+        if (rc == CONFACK) { /* Ack'd all prior CIs? */
+          rc = CONFNAK;      /* Not anymore... */
+          ucp = inp;         /* Backup */
+        }
+      }
+    }
+
+    if (orc == CONFREJ &&    /* Reject this CI */
+        rc != CONFREJ) {  /*  but no prior ones? */
+      rc = CONFREJ;
+      ucp = inp;        /* Backup */
+    }
+    
+    /* Need to move CI? */
+    if (ucp != cip) {
+      BCOPY(cip, ucp, cilen);  /* Move it */
+    }
+
+    /* Update output pointer */
+    INCPTR(cilen, ucp);
+  }
+
+  /*
+   * If we aren't rejecting this packet, and we want to negotiate
+   * their address, and they didn't send their address, then we
+   * send a NAK with a CI_ADDR option appended.  We assume the
+   * input buffer is long enough that we can append the extra
+   * option safely.
+   */
+  if (rc != CONFREJ && !ho->neg_addr &&
+      wo->req_addr && !reject_if_disagree) {
+    IPCPDEBUG((LOG_INFO, "ipcp_reqci: Requesting peer address\n"));
+    if (rc == CONFACK) {
+      rc = CONFNAK;
+      ucp = inp;        /* reset pointer */
+      wo->req_addr = 0;    /* don't ask again */
+    }
+    PUTCHAR(CI_ADDR, ucp);
+    PUTCHAR(CILEN_ADDR, ucp);
+    tl = ntohl(wo->hisaddr);
+    PUTLONG(tl, ucp);
+  }
+
+  *len = (int)(ucp - inp);    /* Compute output length */
+  IPCPDEBUG((LOG_INFO, "ipcp_reqci: returning Configure-%s\n", CODENAME(rc)));
+  return (rc);      /* Return final code */
+}
+
+
+#if 0
+/*
+ * ip_check_options - check that any IP-related options are OK,
+ * and assign appropriate defaults.
+ */
+static void
+ip_check_options(u_long localAddr)
+{
+  ipcp_options *wo = &ipcp_wantoptions[0];
+
+  /*
+   * Load our default IP address but allow the remote host to give us
+   * a new address.
+   */
+  if (wo->ouraddr == 0 && !ppp_settings.disable_defaultip) {
+    wo->accept_local = 1;  /* don't insist on this default value */
+    wo->ouraddr = htonl(localAddr);
+  }
+}
+#endif
+
+
+/*
+ * ipcp_up - IPCP has come UP.
+ *
+ * Configure the IP network interface appropriately and bring it up.
+ */
+static void
+ipcp_up(fsm *f)
+{
+  u32_t mask;
+  ipcp_options *ho = &ipcp_hisoptions[f->unit];
+  ipcp_options *go = &ipcp_gotoptions[f->unit];
+  ipcp_options *wo = &ipcp_wantoptions[f->unit];
+
+  np_up(f->unit, PPP_IP);
+  IPCPDEBUG((LOG_INFO, "ipcp: up\n"));
+
+  /*
+   * We must have a non-zero IP address for both ends of the link.
+   */
+  if (!ho->neg_addr) {
+    ho->hisaddr = wo->hisaddr;
+  }
+
+  if (ho->hisaddr == 0) {
+    IPCPDEBUG((LOG_ERR, "Could not determine remote IP address\n"));
+    ipcp_close(f->unit, "Could not determine remote IP address");
+    return;
+  }
+  if (go->ouraddr == 0) {
+    IPCPDEBUG((LOG_ERR, "Could not determine local IP address\n"));
+    ipcp_close(f->unit, "Could not determine local IP address");
+    return;
+  }
+
+  if (ppp_settings.usepeerdns && (go->dnsaddr[0] || go->dnsaddr[1])) {
+    /*pppGotDNSAddrs(go->dnsaddr[0], go->dnsaddr[1]);*/
+  }
+
+  /*
+   * Check that the peer is allowed to use the IP address it wants.
+   */
+  if (!auth_ip_addr(f->unit, ho->hisaddr)) {
+    IPCPDEBUG((LOG_ERR, "Peer is not authorized to use remote address %s\n",
+        inet_ntoa(ho->hisaddr)));
+    ipcp_close(f->unit, "Unauthorized remote IP address");
+    return;
+  }
+
+  /* set tcp compression */
+  sifvjcomp(f->unit, ho->neg_vj, ho->cflag, ho->maxslotindex);
+
+  /*
+   * Set IP addresses and (if specified) netmask.
+   */
+  mask = GetMask(go->ouraddr);
+
+  if (!sifaddr(f->unit, go->ouraddr, ho->hisaddr, mask, go->dnsaddr[0], go->dnsaddr[1])) {
+    IPCPDEBUG((LOG_WARNING, "sifaddr failed\n"));
+    ipcp_close(f->unit, "Interface configuration failed");
+    return;
+  }
+
+  /* bring the interface up for IP */
+  if (!sifup(f->unit)) {
+    IPCPDEBUG((LOG_WARNING, "sifup failed\n"));
+    ipcp_close(f->unit, "Interface configuration failed");
+    return;
+  }
+
+  sifnpmode(f->unit, PPP_IP, NPMODE_PASS);
+
+  /* assign a default route through the interface if required */
+  if (ipcp_wantoptions[f->unit].default_route) {
+    if (sifdefaultroute(f->unit, go->ouraddr, ho->hisaddr)) {
+      default_route_set[f->unit] = 1;
+    }
+  }
+
+  IPCPDEBUG((LOG_NOTICE, "local  IP address %s\n", inet_ntoa(go->ouraddr)));
+  IPCPDEBUG((LOG_NOTICE, "remote IP address %s\n", inet_ntoa(ho->hisaddr)));
+  if (go->dnsaddr[0]) {
+    IPCPDEBUG((LOG_NOTICE, "primary   DNS address %s\n", inet_ntoa(go->dnsaddr[0])));
+  }
+  if (go->dnsaddr[1]) {
+    IPCPDEBUG((LOG_NOTICE, "secondary DNS address %s\n", inet_ntoa(go->dnsaddr[1])));
+  }
+}
+
+
+/*
+ * ipcp_down - IPCP has gone DOWN.
+ *
+ * Take the IP network interface down, clear its addresses
+ * and delete routes through it.
+ */
+static void
+ipcp_down(fsm *f)
+{
+  IPCPDEBUG((LOG_INFO, "ipcp: down\n"));
+  np_down(f->unit, PPP_IP);
+  sifvjcomp(f->unit, 0, 0, 0);
+
+  sifdown(f->unit);
+  ipcp_clear_addrs(f->unit);
+}
+
+
+/*
+ * ipcp_clear_addrs() - clear the interface addresses, routes, etc.
+ */
+static void
+ipcp_clear_addrs(int unit)
+{
+  u32_t ouraddr, hisaddr;
+
+  ouraddr = ipcp_gotoptions[unit].ouraddr;
+  hisaddr = ipcp_hisoptions[unit].hisaddr;
+  if (default_route_set[unit]) {
+    cifdefaultroute(unit, ouraddr, hisaddr);
+    default_route_set[unit] = 0;
+  }
+  cifaddr(unit, ouraddr, hisaddr);
+}
+
+
+/*
+ * ipcp_finished - possibly shut down the lower layers.
+ */
+static void
+ipcp_finished(fsm *f)
+{
+  np_finished(f->unit, PPP_IP);
+}
+
+#if 0
+static int
+ipcp_printpkt(u_char *p, int plen, void (*printer) (void *, char *, ...), void *arg)
+{
+  LWIP_UNUSED_ARG(p);
+  LWIP_UNUSED_ARG(plen);
+  LWIP_UNUSED_ARG(printer);
+  LWIP_UNUSED_ARG(arg);
+  return 0;
+}
+
+/*
+ * ip_active_pkt - see if this IP packet is worth bringing the link up for.
+ * We don't bring the link up for IP fragments or for TCP FIN packets
+ * with no data.
+ */
+#define IP_HDRLEN   20  /* bytes */
+#define IP_OFFMASK  0x1fff
+#define IPPROTO_TCP 6
+#define TCP_HDRLEN  20
+#define TH_FIN      0x01
+
+/*
+ * We use these macros because the IP header may be at an odd address,
+ * and some compilers might use word loads to get th_off or ip_hl.
+ */
+
+#define net_short(x)    (((x)[0] << 8) + (x)[1])
+#define get_iphl(x)     (((unsigned char *)(x))[0] & 0xF)
+#define get_ipoff(x)    net_short((unsigned char *)(x) + 6)
+#define get_ipproto(x)  (((unsigned char *)(x))[9])
+#define get_tcpoff(x)   (((unsigned char *)(x))[12] >> 4)
+#define get_tcpflags(x) (((unsigned char *)(x))[13])
+
+static int
+ip_active_pkt(u_char *pkt, int len)
+{
+  u_char *tcp;
+  int hlen;
+
+  len -= PPP_HDRLEN;
+  pkt += PPP_HDRLEN;
+  if (len < IP_HDRLEN) {
+    return 0;
+  }
+  if ((get_ipoff(pkt) & IP_OFFMASK) != 0) {
+    return 0;
+  }
+  if (get_ipproto(pkt) != IPPROTO_TCP) {
+    return 1;
+  }
+  hlen = get_iphl(pkt) * 4;
+  if (len < hlen + TCP_HDRLEN) {
+    return 0;
+  }
+  tcp = pkt + hlen;
+  if ((get_tcpflags(tcp) & TH_FIN) != 0 && len == hlen + get_tcpoff(tcp) * 4) {
+    return 0;
+  }
+  return 1;
+}
+#endif
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/ipcp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/ipcp.h
new file mode 100644
index 0000000..80e0190
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/ipcp.h
@@ -0,0 +1,124 @@
+/*****************************************************************************
+* ipcp.h -  PPP IP NCP: Internet Protocol Network Control Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * ipcp.h - IP Control Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: ipcp.h,v 1.3 2007/12/19 20:47:23 fbernon Exp $
+ */
+
+#ifndef IPCP_H
+#define IPCP_H
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+/*
+ * Options.
+ */
+#define CI_ADDRS            1      /* IP Addresses */
+#define CI_COMPRESSTYPE     2      /* Compression Type */
+#define CI_ADDR             3
+
+#define CI_MS_WINS1         128    /* Primary WINS value */
+#define CI_MS_DNS1          129    /* Primary DNS value */
+#define CI_MS_WINS2         130    /* Secondary WINS value */
+#define CI_MS_DNS2          131    /* Secondary DNS value */
+
+#define IPCP_VJMODE_OLD     1      /* "old" mode (option # = 0x0037) */
+#define IPCP_VJMODE_RFC1172 2      /* "old-rfc"mode (option # = 0x002d) */
+#define IPCP_VJMODE_RFC1332 3      /* "new-rfc"mode (option # = 0x002d, */
+                                   /*  maxslot and slot number compression) */
+
+#define IPCP_VJ_COMP        0x002d /* current value for VJ compression option */
+#define IPCP_VJ_COMP_OLD    0x0037 /* "old" (i.e, broken) value for VJ */
+                                   /* compression option */ 
+
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+typedef struct ipcp_options {
+  u_int   neg_addr      : 1; /* Negotiate IP Address? */
+  u_int   old_addrs     : 1; /* Use old (IP-Addresses) option? */
+  u_int   req_addr      : 1; /* Ask peer to send IP address? */
+  u_int   default_route : 1; /* Assign default route through interface? */
+  u_int   proxy_arp     : 1; /* Make proxy ARP entry for peer? */
+  u_int   neg_vj        : 1; /* Van Jacobson Compression? */
+  u_int   old_vj        : 1; /* use old (short) form of VJ option? */
+  u_int   accept_local  : 1; /* accept peer's value for ouraddr */
+  u_int   accept_remote : 1; /* accept peer's value for hisaddr */
+  u_int   req_dns1      : 1; /* Ask peer to send primary DNS address? */
+  u_int   req_dns2      : 1; /* Ask peer to send secondary DNS address? */
+  u_short vj_protocol;       /* protocol value to use in VJ option */
+  u_char  maxslotindex;      /* VJ slots - 1. */
+  u_char  cflag;             /* VJ slot compression flag. */
+  u32_t   ouraddr, hisaddr;  /* Addresses in NETWORK BYTE ORDER */
+  u32_t   dnsaddr[2];        /* Primary and secondary MS DNS entries */
+  u32_t   winsaddr[2];       /* Primary and secondary MS WINS entries */
+} ipcp_options;
+
+
+/*****************************
+*** PUBLIC DATA STRUCTURES ***
+*****************************/
+
+extern fsm ipcp_fsm[];
+extern ipcp_options ipcp_wantoptions[];
+extern ipcp_options ipcp_gotoptions[];
+extern ipcp_options ipcp_allowoptions[];
+extern ipcp_options ipcp_hisoptions[];
+
+extern struct protent ipcp_protent;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+#endif /* IPCP_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/lcp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/lcp.c
new file mode 100644
index 0000000..f8af228
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/lcp.c
@@ -0,0 +1,2035 @@
+/*****************************************************************************
+* lcp.c - Network Link Control Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-01 Guy Lancaster , Global Election Systems Inc.
+*   Original.
+*****************************************************************************/
+
+/*
+ * lcp.c - PPP Link Control Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+ 
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "fsm.h"
+#include "chap.h"
+#include "magic.h"
+#include "auth.h"
+#include "lcp.h"
+
+#include 
+
+#if PPPOE_SUPPORT
+#include "netif/ppp_oe.h"
+#else
+#define PPPOE_MAXMTU PPP_MAXMRU
+#endif
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+/*
+ * Length of each type of configuration option (in octets)
+ */
+#define CILEN_VOID  2
+#define CILEN_CHAR  3
+#define CILEN_SHORT 4 /* CILEN_VOID + sizeof(short) */
+#define CILEN_CHAP  5 /* CILEN_VOID + sizeof(short) + 1 */
+#define CILEN_LONG  6 /* CILEN_VOID + sizeof(long) */
+#define CILEN_LQR   8 /* CILEN_VOID + sizeof(short) + sizeof(long) */
+#define CILEN_CBCP  3
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Callbacks for fsm code.  (CI = Configuration Information)
+ */
+static void lcp_resetci (fsm*);                   /* Reset our CI */
+static int  lcp_cilen (fsm*);                     /* Return length of our CI */
+static void lcp_addci (fsm*, u_char*, int*);      /* Add our CI to pkt */
+static int  lcp_ackci (fsm*, u_char*, int);       /* Peer ack'd our CI */
+static int  lcp_nakci (fsm*, u_char*, int);       /* Peer nak'd our CI */
+static int  lcp_rejci (fsm*, u_char*, int);       /* Peer rej'd our CI */
+static int  lcp_reqci (fsm*, u_char*, int*, int); /* Rcv peer CI */
+static void lcp_up (fsm*);                        /* We're UP */
+static void lcp_down (fsm*);                      /* We're DOWN */
+static void lcp_starting (fsm*);                  /* We need lower layer up */
+static void lcp_finished (fsm*);                  /* We need lower layer down */
+static int  lcp_extcode (fsm*, int, u_char, u_char*, int);
+
+static void lcp_rprotrej (fsm*, u_char*, int);
+
+/*
+ * routines to send LCP echos to peer
+ */
+static void lcp_echo_lowerup (int);
+static void lcp_echo_lowerdown (int);
+static void LcpEchoTimeout (void*);
+static void lcp_received_echo_reply (fsm*, int, u_char*, int);
+static void LcpSendEchoRequest (fsm*);
+static void LcpLinkFailure (fsm*);
+static void LcpEchoCheck (fsm*);
+
+/*
+ * Protocol entry points.
+ * Some of these are called directly.
+ */
+static void lcp_input (int, u_char *, int);
+static void lcp_protrej (int);
+
+#define CODENAME(x) ((x) == CONFACK ? "ACK" : (x) == CONFNAK ? "NAK" : "REJ")
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+/* global vars */
+LinkPhase lcp_phase[NUM_PPP];          /* Phase of link session (RFC 1661) */
+lcp_options lcp_wantoptions[NUM_PPP];  /* Options that we want to request */
+lcp_options lcp_gotoptions[NUM_PPP];   /* Options that peer ack'd */
+lcp_options lcp_allowoptions[NUM_PPP]; /* Options we allow peer to request */
+lcp_options lcp_hisoptions[NUM_PPP];   /* Options that we ack'd */
+ext_accm xmit_accm[NUM_PPP];           /* extended transmit ACCM */
+
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static fsm lcp_fsm[NUM_PPP];                            /* LCP fsm structure (global)*/
+static u_int lcp_echo_interval      = LCP_ECHOINTERVAL; /* Interval between LCP echo-requests */
+static u_int lcp_echo_fails         = LCP_MAXECHOFAILS; /* Tolerance to unanswered echo-requests */
+static u32_t lcp_echos_pending      = 0;                /* Number of outstanding echo msgs */
+static u32_t lcp_echo_number        = 0;                /* ID number of next echo frame */
+static u32_t lcp_echo_timer_running = 0;                /* TRUE if a timer is running */
+
+static u_char nak_buffer[PPP_MRU]; /* where we construct a nak packet */
+
+static fsm_callbacks lcp_callbacks = { /* LCP callback routines */
+  lcp_resetci,  /* Reset our Configuration Information */
+  lcp_cilen,    /* Length of our Configuration Information */
+  lcp_addci,    /* Add our Configuration Information */
+  lcp_ackci,    /* ACK our Configuration Information */
+  lcp_nakci,    /* NAK our Configuration Information */
+  lcp_rejci,    /* Reject our Configuration Information */
+  lcp_reqci,    /* Request peer's Configuration Information */
+  lcp_up,       /* Called when fsm reaches LS_OPENED state */
+  lcp_down,     /* Called when fsm leaves LS_OPENED state */
+  lcp_starting, /* Called when we want the lower layer up */
+  lcp_finished, /* Called when we want the lower layer down */
+  NULL,         /* Called when Protocol-Reject received */
+  NULL,         /* Retransmission is necessary */
+  lcp_extcode,  /* Called to handle LCP-specific codes */
+  "LCP"         /* String name of protocol */
+};
+
+struct protent lcp_protent = {
+    PPP_LCP,
+    lcp_init,
+    lcp_input,
+    lcp_protrej,
+    lcp_lowerup,
+    lcp_lowerdown,
+    lcp_open,
+    lcp_close,
+#if 0
+    lcp_printpkt,
+    NULL,
+#endif
+    1,
+    "LCP",
+#if 0
+    NULL,
+    NULL,
+    NULL
+#endif
+};
+
+int lcp_loopbackfail = DEFLOOPBACKFAIL;
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * lcp_init - Initialize LCP.
+ */
+void
+lcp_init(int unit)
+{
+  fsm         *f  = &lcp_fsm[unit];
+  lcp_options *wo = &lcp_wantoptions[unit];
+  lcp_options *ao = &lcp_allowoptions[unit];
+  
+  f->unit      = unit;
+  f->protocol  = PPP_LCP;
+  f->callbacks = &lcp_callbacks;
+  
+  fsm_init(f);
+  
+  wo->passive           = 0;
+  wo->silent            = 0;
+  wo->restart           = 0;               /* Set to 1 in kernels or multi-line implementations */
+  wo->neg_mru           = 1;
+  wo->mru               = PPP_DEFMRU;
+  wo->neg_asyncmap      = 1;
+  wo->asyncmap          = 0x00000000l;     /* Assume don't need to escape any ctl chars. */
+  wo->neg_chap          = 0;               /* Set to 1 on server */
+  wo->neg_upap          = 0;               /* Set to 1 on server */
+  wo->chap_mdtype       = CHAP_DIGEST_MD5;
+  wo->neg_magicnumber   = 1;
+  wo->neg_pcompression  = 1;
+  wo->neg_accompression = 1;
+  wo->neg_lqr           = 0;               /* no LQR implementation yet */
+  wo->neg_cbcp          = 0;
+  
+  ao->neg_mru           = 1;
+  ao->mru               = PPP_MAXMRU;
+  ao->neg_asyncmap      = 1;
+  ao->asyncmap          = 0x00000000l;     /* Assume don't need to escape any ctl chars. */
+  ao->neg_chap          = (CHAP_SUPPORT != 0);
+  ao->chap_mdtype       = CHAP_DIGEST_MD5;
+  ao->neg_upap          = (PAP_SUPPORT != 0);
+  ao->neg_magicnumber   = 1;
+  ao->neg_pcompression  = 1;
+  ao->neg_accompression = 1;
+  ao->neg_lqr           = 0;               /* no LQR implementation yet */
+  ao->neg_cbcp          = (CBCP_SUPPORT != 0);
+
+  /* 
+   * Set transmit escape for the flag and escape characters plus anything
+   * set for the allowable options.
+   */
+  memset(xmit_accm[unit], 0, sizeof(xmit_accm[0]));
+  xmit_accm[unit][15] = 0x60;
+  xmit_accm[unit][0]  = (u_char)((ao->asyncmap        & 0xFF));
+  xmit_accm[unit][1]  = (u_char)((ao->asyncmap >> 8)  & 0xFF);
+  xmit_accm[unit][2]  = (u_char)((ao->asyncmap >> 16) & 0xFF);
+  xmit_accm[unit][3]  = (u_char)((ao->asyncmap >> 24) & 0xFF);
+  LCPDEBUG((LOG_INFO, "lcp_init: xmit_accm=%X %X %X %X\n",
+        xmit_accm[unit][0],
+        xmit_accm[unit][1],
+        xmit_accm[unit][2],
+        xmit_accm[unit][3]));
+  
+  lcp_phase[unit] = PHASE_INITIALIZE;
+}
+
+
+/*
+ * lcp_open - LCP is allowed to come up.
+ */
+void
+lcp_open(int unit)
+{
+  fsm         *f  = &lcp_fsm[unit];
+  lcp_options *wo = &lcp_wantoptions[unit];
+
+  f->flags = 0;
+  if (wo->passive) {
+    f->flags |= OPT_PASSIVE;
+  }
+  if (wo->silent) {
+    f->flags |= OPT_SILENT;
+  }
+  fsm_open(f);
+
+  lcp_phase[unit] = PHASE_ESTABLISH;
+}
+
+
+/*
+ * lcp_close - Take LCP down.
+ */
+void
+lcp_close(int unit, char *reason)
+{
+  fsm *f = &lcp_fsm[unit];
+
+  if (lcp_phase[unit] != PHASE_DEAD) {
+    lcp_phase[unit] = PHASE_TERMINATE;
+  }
+  if (f->state == LS_STOPPED && f->flags & (OPT_PASSIVE|OPT_SILENT)) {
+    /*
+     * This action is not strictly according to the FSM in RFC1548,
+     * but it does mean that the program terminates if you do an
+     * lcp_close() in passive/silent mode when a connection hasn't
+     * been established.
+     */
+    f->state = LS_CLOSED;
+    lcp_finished(f);
+  } else {
+    fsm_close(&lcp_fsm[unit], reason);
+  }
+}
+
+
+/*
+ * lcp_lowerup - The lower layer is up.
+ */
+void
+lcp_lowerup(int unit)
+{
+  lcp_options *wo = &lcp_wantoptions[unit];
+
+  /*
+   * Don't use A/C or protocol compression on transmission,
+   * but accept A/C and protocol compressed packets
+   * if we are going to ask for A/C and protocol compression.
+   */
+  ppp_set_xaccm(unit, &xmit_accm[unit]);
+  ppp_send_config(unit, PPP_MRU, 0xffffffffl, 0, 0);
+  ppp_recv_config(unit, PPP_MRU, 0x00000000l,
+  wo->neg_pcompression, wo->neg_accompression);
+  peer_mru[unit] = PPP_MRU;
+  lcp_allowoptions[unit].asyncmap = (u_long)xmit_accm[unit][0]
+                                 | ((u_long)xmit_accm[unit][1] << 8)
+                                 | ((u_long)xmit_accm[unit][2] << 16)
+                                 | ((u_long)xmit_accm[unit][3] << 24);
+  LCPDEBUG((LOG_INFO, "lcp_lowerup: asyncmap=%X %X %X %X\n",
+            xmit_accm[unit][3],
+            xmit_accm[unit][2],
+            xmit_accm[unit][1],
+            xmit_accm[unit][0]));
+
+  fsm_lowerup(&lcp_fsm[unit]);
+}
+
+
+/*
+ * lcp_lowerdown - The lower layer is down.
+ */
+void
+lcp_lowerdown(int unit)
+{
+  fsm_lowerdown(&lcp_fsm[unit]);
+}
+
+/*
+ * lcp_sprotrej - Send a Protocol-Reject for some protocol.
+ */
+void
+lcp_sprotrej(int unit, u_char *p, int len)
+{
+  /*
+   * Send back the protocol and the information field of the
+   * rejected packet.  We only get here if LCP is in the LS_OPENED state.
+   */
+
+  fsm_sdata(&lcp_fsm[unit], PROTREJ, ++lcp_fsm[unit].id, p, len);
+}
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * lcp_input - Input LCP packet.
+ */
+static void
+lcp_input(int unit, u_char *p, int len)
+{
+  fsm *f = &lcp_fsm[unit];
+
+  fsm_input(f, p, len);
+}
+
+
+/*
+ * lcp_extcode - Handle a LCP-specific code.
+ */
+static int
+lcp_extcode(fsm *f, int code, u_char id, u_char *inp, int len)
+{
+  u_char *magp;
+
+  switch( code ){
+    case PROTREJ:
+      lcp_rprotrej(f, inp, len);
+      break;
+  
+    case ECHOREQ:
+      if (f->state != LS_OPENED) {
+        break;
+      }
+      LCPDEBUG((LOG_INFO, "lcp: Echo-Request, Rcvd id %d\n", id));
+      magp = inp;
+      PUTLONG(lcp_gotoptions[f->unit].magicnumber, magp);
+      fsm_sdata(f, ECHOREP, id, inp, len);
+      break;
+
+    case ECHOREP:
+      lcp_received_echo_reply(f, id, inp, len);
+      break;
+    
+    case DISCREQ:
+      break;
+    
+    default:
+      return 0;
+  }
+  return 1;
+}
+
+
+/*
+ * lcp_rprotrej - Receive an Protocol-Reject.
+ *
+ * Figure out which protocol is rejected and inform it.
+ */
+static void
+lcp_rprotrej(fsm *f, u_char *inp, int len)
+{
+  int i;
+  struct protent *protp;
+  u_short prot;
+
+  if (len < sizeof (u_short)) {
+    LCPDEBUG((LOG_INFO, "lcp_rprotrej: Rcvd short Protocol-Reject packet!\n"));
+    return;
+  }
+
+  GETSHORT(prot, inp);
+
+  LCPDEBUG((LOG_INFO, "lcp_rprotrej: Rcvd Protocol-Reject packet for %x!\n", prot));
+
+  /*
+   * Protocol-Reject packets received in any state other than the LCP
+   * LS_OPENED state SHOULD be silently discarded.
+   */
+  if( f->state != LS_OPENED ) {
+    LCPDEBUG((LOG_INFO, "Protocol-Reject discarded: LCP in state %d\n", f->state));
+    return;
+  }
+
+  /*
+   * Upcall the proper Protocol-Reject routine.
+   */
+  for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+    if (protp->protocol == prot && protp->enabled_flag) {
+      (*protp->protrej)(f->unit);
+      return;
+    }
+  }
+
+  LCPDEBUG((LOG_WARNING, "Protocol-Reject for unsupported protocol 0x%x\n", prot));
+}
+
+
+/*
+ * lcp_protrej - A Protocol-Reject was received.
+ */
+static void
+lcp_protrej(int unit)
+{
+  LWIP_UNUSED_ARG(unit);
+  /*
+   * Can't reject LCP!
+   */
+  LCPDEBUG((LOG_WARNING, "lcp_protrej: Received Protocol-Reject for LCP!\n"));
+  fsm_protreject(&lcp_fsm[unit]);
+}
+
+
+/*
+ * lcp_resetci - Reset our CI.
+ */
+static void
+lcp_resetci(fsm *f)
+{
+  lcp_wantoptions[f->unit].magicnumber = magic();
+  lcp_wantoptions[f->unit].numloops = 0;
+  lcp_gotoptions[f->unit] = lcp_wantoptions[f->unit];
+  peer_mru[f->unit] = PPP_MRU;
+  auth_reset(f->unit);
+}
+
+
+/*
+ * lcp_cilen - Return length of our CI.
+ */
+static int lcp_cilen(fsm *f)
+{
+  lcp_options *go = &lcp_gotoptions[f->unit];
+
+#define LENCIVOID(neg)  ((neg) ? CILEN_VOID : 0)
+#define LENCICHAP(neg)  ((neg) ? CILEN_CHAP : 0)
+#define LENCISHORT(neg) ((neg) ? CILEN_SHORT : 0)
+#define LENCILONG(neg)  ((neg) ? CILEN_LONG : 0)
+#define LENCILQR(neg)   ((neg) ? CILEN_LQR: 0)
+#define LENCICBCP(neg)  ((neg) ? CILEN_CBCP: 0)
+  /*
+   * NB: we only ask for one of CHAP and UPAP, even if we will
+   * accept either.
+   */
+  return (LENCISHORT(go->neg_mru && go->mru != PPP_DEFMRU) +
+          LENCILONG(go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) +
+          LENCICHAP(go->neg_chap) +
+          LENCISHORT(!go->neg_chap && go->neg_upap) +
+          LENCILQR(go->neg_lqr) +
+          LENCICBCP(go->neg_cbcp) +
+          LENCILONG(go->neg_magicnumber) +
+          LENCIVOID(go->neg_pcompression) +
+          LENCIVOID(go->neg_accompression));
+}
+
+
+/*
+ * lcp_addci - Add our desired CIs to a packet.
+ */
+static void
+lcp_addci(fsm *f, u_char *ucp, int *lenp)
+{
+  lcp_options *go = &lcp_gotoptions[f->unit];
+  u_char *start_ucp = ucp;
+
+#define ADDCIVOID(opt, neg) \
+  if (neg) { \
+    LCPDEBUG((LOG_INFO, "lcp_addci: opt=%d\n", opt)); \
+    PUTCHAR(opt, ucp); \
+    PUTCHAR(CILEN_VOID, ucp); \
+  }
+#define ADDCISHORT(opt, neg, val) \
+  if (neg) { \
+    LCPDEBUG((LOG_INFO, "lcp_addci: INT opt=%d %X\n", opt, val)); \
+    PUTCHAR(opt, ucp); \
+    PUTCHAR(CILEN_SHORT, ucp); \
+    PUTSHORT(val, ucp); \
+  }
+#define ADDCICHAP(opt, neg, val, digest) \
+  if (neg) { \
+    LCPDEBUG((LOG_INFO, "lcp_addci: CHAP opt=%d %X\n", opt, val)); \
+    PUTCHAR(opt, ucp); \
+    PUTCHAR(CILEN_CHAP, ucp); \
+    PUTSHORT(val, ucp); \
+    PUTCHAR(digest, ucp); \
+  }
+#define ADDCILONG(opt, neg, val) \
+  if (neg) { \
+    LCPDEBUG((LOG_INFO, "lcp_addci: L opt=%d %lX\n", opt, val)); \
+    PUTCHAR(opt, ucp); \
+    PUTCHAR(CILEN_LONG, ucp); \
+    PUTLONG(val, ucp); \
+  }
+#define ADDCILQR(opt, neg, val) \
+  if (neg) { \
+    LCPDEBUG((LOG_INFO, "lcp_addci: LQR opt=%d %lX\n", opt, val)); \
+    PUTCHAR(opt, ucp); \
+    PUTCHAR(CILEN_LQR, ucp); \
+    PUTSHORT(PPP_LQR, ucp); \
+    PUTLONG(val, ucp); \
+  }
+#define ADDCICHAR(opt, neg, val) \
+  if (neg) { \
+    LCPDEBUG((LOG_INFO, "lcp_addci: CHAR opt=%d %X '%z'\n", opt, val, val)); \
+    PUTCHAR(opt, ucp); \
+    PUTCHAR(CILEN_CHAR, ucp); \
+    PUTCHAR(val, ucp); \
+  }
+
+  ADDCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru);
+  ADDCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl, go->asyncmap);
+  ADDCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype);
+  ADDCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP);
+  ADDCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period);
+  ADDCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT);
+  ADDCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber);
+  ADDCIVOID(CI_PCOMPRESSION, go->neg_pcompression);
+  ADDCIVOID(CI_ACCOMPRESSION, go->neg_accompression);
+
+  if (ucp - start_ucp != *lenp) {
+    /* this should never happen, because peer_mtu should be 1500 */
+    LCPDEBUG((LOG_ERR, "Bug in lcp_addci: wrong length\n"));
+  }
+}
+
+
+/*
+ * lcp_ackci - Ack our CIs.
+ * This should not modify any state if the Ack is bad.
+ *
+ * Returns:
+ *  0 - Ack was bad.
+ *  1 - Ack was good.
+ */
+static int
+lcp_ackci(fsm *f, u_char *p, int len)
+{
+  lcp_options *go = &lcp_gotoptions[f->unit];
+  u_char cilen, citype, cichar;
+  u_short cishort;
+  u32_t cilong;
+
+  /*
+   * CIs must be in exactly the same order that we sent.
+   * Check packet length and CI length at each step.
+   * If we find any deviations, then this packet is bad.
+   */
+#define ACKCIVOID(opt, neg) \
+  if (neg) { \
+    if ((len -= CILEN_VOID) < 0) \
+      goto bad; \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != CILEN_VOID || citype != opt) \
+      goto bad; \
+  }
+#define ACKCISHORT(opt, neg, val) \
+  if (neg) { \
+    if ((len -= CILEN_SHORT) < 0) \
+      goto bad; \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != CILEN_SHORT || citype != opt) \
+      goto bad; \
+    GETSHORT(cishort, p); \
+    if (cishort != val) \
+      goto bad; \
+  }
+#define ACKCICHAR(opt, neg, val) \
+  if (neg) { \
+    if ((len -= CILEN_CHAR) < 0) \
+      goto bad; \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != CILEN_CHAR || citype != opt) \
+      goto bad; \
+    GETCHAR(cichar, p); \
+    if (cichar != val) \
+      goto bad; \
+  }
+#define ACKCICHAP(opt, neg, val, digest) \
+  if (neg) { \
+    if ((len -= CILEN_CHAP) < 0) \
+      goto bad; \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != CILEN_CHAP || citype != opt) \
+      goto bad; \
+    GETSHORT(cishort, p); \
+    if (cishort != val) \
+      goto bad; \
+    GETCHAR(cichar, p); \
+    if (cichar != digest) \
+      goto bad; \
+  }
+#define ACKCILONG(opt, neg, val) \
+  if (neg) { \
+    if ((len -= CILEN_LONG) < 0) \
+      goto bad; \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != CILEN_LONG ||  citype != opt) \
+      goto bad; \
+    GETLONG(cilong, p); \
+    if (cilong != val) \
+      goto bad; \
+  }
+#define ACKCILQR(opt, neg, val) \
+  if (neg) { \
+    if ((len -= CILEN_LQR) < 0) \
+      goto bad; \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != CILEN_LQR || citype != opt) \
+      goto bad; \
+    GETSHORT(cishort, p); \
+    if (cishort != PPP_LQR) \
+      goto bad; \
+    GETLONG(cilong, p); \
+    if (cilong != val) \
+      goto bad; \
+  }
+
+  ACKCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru);
+  ACKCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl, go->asyncmap);
+  ACKCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype);
+  ACKCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP);
+  ACKCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period);
+  ACKCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT);
+  ACKCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber);
+  ACKCIVOID(CI_PCOMPRESSION, go->neg_pcompression);
+  ACKCIVOID(CI_ACCOMPRESSION, go->neg_accompression);
+
+  /*
+   * If there are any remaining CIs, then this packet is bad.
+   */
+  if (len != 0) {
+    goto bad;
+  }
+  LCPDEBUG((LOG_INFO, "lcp_acki: Ack\n"));
+  return (1);
+bad:
+  LCPDEBUG((LOG_WARNING, "lcp_acki: received bad Ack!\n"));
+  return (0);
+}
+
+
+/*
+ * lcp_nakci - Peer has sent a NAK for some of our CIs.
+ * This should not modify any state if the Nak is bad
+ * or if LCP is in the LS_OPENED state.
+ *
+ * Returns:
+ *  0 - Nak was bad.
+ *  1 - Nak was good.
+ */
+static int
+lcp_nakci(fsm *f, u_char *p, int len)
+{
+  lcp_options *go = &lcp_gotoptions[f->unit];
+  lcp_options *wo = &lcp_wantoptions[f->unit];
+  u_char citype, cichar, *next;
+  u_short cishort;
+  u32_t cilong;
+  lcp_options no;     /* options we've seen Naks for */
+  lcp_options try;    /* options to request next time */
+  int looped_back = 0;
+  int cilen;
+
+  BZERO(&no, sizeof(no));
+  try = *go;
+
+  /*
+   * Any Nak'd CIs must be in exactly the same order that we sent.
+   * Check packet length and CI length at each step.
+   * If we find any deviations, then this packet is bad.
+   */
+#define NAKCIVOID(opt, neg, code) \
+  if (go->neg && \
+      len >= CILEN_VOID && \
+      p[1] == CILEN_VOID && \
+      p[0] == opt) { \
+    len -= CILEN_VOID; \
+    INCPTR(CILEN_VOID, p); \
+    no.neg = 1; \
+    code \
+  }
+#define NAKCICHAP(opt, neg, code) \
+  if (go->neg && \
+      len >= CILEN_CHAP && \
+      p[1] == CILEN_CHAP && \
+      p[0] == opt) { \
+    len -= CILEN_CHAP; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    GETCHAR(cichar, p); \
+    no.neg = 1; \
+    code \
+  }
+#define NAKCICHAR(opt, neg, code) \
+  if (go->neg && \
+      len >= CILEN_CHAR && \
+      p[1] == CILEN_CHAR && \
+      p[0] == opt) { \
+    len -= CILEN_CHAR; \
+    INCPTR(2, p); \
+    GETCHAR(cichar, p); \
+    no.neg = 1; \
+    code \
+  }
+#define NAKCISHORT(opt, neg, code) \
+  if (go->neg && \
+      len >= CILEN_SHORT && \
+      p[1] == CILEN_SHORT && \
+      p[0] == opt) { \
+    len -= CILEN_SHORT; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    no.neg = 1; \
+    code \
+  }
+#define NAKCILONG(opt, neg, code) \
+  if (go->neg && \
+      len >= CILEN_LONG && \
+      p[1] == CILEN_LONG && \
+      p[0] == opt) { \
+    len -= CILEN_LONG; \
+    INCPTR(2, p); \
+    GETLONG(cilong, p); \
+    no.neg = 1; \
+    code \
+  }
+#define NAKCILQR(opt, neg, code) \
+  if (go->neg && \
+      len >= CILEN_LQR && \
+      p[1] == CILEN_LQR && \
+      p[0] == opt) { \
+    len -= CILEN_LQR; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    GETLONG(cilong, p); \
+    no.neg = 1; \
+    code \
+  }
+
+  /*
+   * We don't care if they want to send us smaller packets than
+   * we want.  Therefore, accept any MRU less than what we asked for,
+   * but then ignore the new value when setting the MRU in the kernel.
+   * If they send us a bigger MRU than what we asked, accept it, up to
+   * the limit of the default MRU we'd get if we didn't negotiate.
+   */
+  if (go->neg_mru && go->mru != PPP_DEFMRU) {
+    NAKCISHORT(CI_MRU, neg_mru,
+      if (cishort <= wo->mru || cishort < PPP_DEFMRU) {
+        try.mru = cishort;
+      }
+    );
+  }
+
+  /*
+   * Add any characters they want to our (receive-side) asyncmap.
+   */
+  if (go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) {
+    NAKCILONG(CI_ASYNCMAP, neg_asyncmap,
+      try.asyncmap = go->asyncmap | cilong;
+    );
+  }
+
+  /*
+   * If they've nak'd our authentication-protocol, check whether
+   * they are proposing a different protocol, or a different
+   * hash algorithm for CHAP.
+   */
+  if ((go->neg_chap || go->neg_upap)
+      && len >= CILEN_SHORT
+      && p[0] == CI_AUTHTYPE && p[1] >= CILEN_SHORT && p[1] <= len) {
+    cilen = p[1];
+    len -= cilen;
+    no.neg_chap = go->neg_chap;
+    no.neg_upap = go->neg_upap;
+    INCPTR(2, p);
+    GETSHORT(cishort, p);
+    if (cishort == PPP_PAP && cilen == CILEN_SHORT) {
+      /*
+       * If we were asking for CHAP, they obviously don't want to do it.
+       * If we weren't asking for CHAP, then we were asking for PAP,
+       * in which case this Nak is bad.
+       */
+      if (!go->neg_chap) {
+        goto bad;
+      }
+      try.neg_chap = 0;
+    
+    } else if (cishort == PPP_CHAP && cilen == CILEN_CHAP) {
+      GETCHAR(cichar, p);
+      if (go->neg_chap) {
+        /*
+         * We were asking for CHAP/MD5; they must want a different
+         * algorithm.  If they can't do MD5, we'll have to stop
+         * asking for CHAP.
+         */
+        if (cichar != go->chap_mdtype) {
+          try.neg_chap = 0;
+        }
+      } else {
+        /*
+         * Stop asking for PAP if we were asking for it.
+         */
+        try.neg_upap = 0;
+      }
+    
+    } else {
+      /*
+       * We don't recognize what they're suggesting.
+       * Stop asking for what we were asking for.
+       */
+      if (go->neg_chap) {
+        try.neg_chap = 0;
+      } else {
+        try.neg_upap = 0;
+      }
+      p += cilen - CILEN_SHORT;
+    }
+  }
+
+  /*
+   * If they can't cope with our link quality protocol, we'll have
+   * to stop asking for LQR.  We haven't got any other protocol.
+   * If they Nak the reporting period, take their value XXX ?
+   */
+  NAKCILQR(CI_QUALITY, neg_lqr,
+    if (cishort != PPP_LQR) {
+      try.neg_lqr = 0;
+    } else {
+      try.lqr_period = cilong;
+    }
+  );
+
+  /*
+   * Only implementing CBCP...not the rest of the callback options
+   */
+  NAKCICHAR(CI_CALLBACK, neg_cbcp,
+    try.neg_cbcp = 0;
+  );
+
+  /*
+   * Check for a looped-back line.
+   */
+  NAKCILONG(CI_MAGICNUMBER, neg_magicnumber,
+    try.magicnumber = magic();
+    looped_back = 1;
+  );
+
+  /*
+   * Peer shouldn't send Nak for protocol compression or
+   * address/control compression requests; they should send
+   * a Reject instead.  If they send a Nak, treat it as a Reject.
+   */
+  NAKCIVOID(CI_PCOMPRESSION, neg_pcompression,
+    try.neg_pcompression = 0;
+  );
+  NAKCIVOID(CI_ACCOMPRESSION, neg_accompression,
+    try.neg_accompression = 0;
+  );
+
+  /*
+   * There may be remaining CIs, if the peer is requesting negotiation
+   * on an option that we didn't include in our request packet.
+   * If we see an option that we requested, or one we've already seen
+   * in this packet, then this packet is bad.
+   * If we wanted to respond by starting to negotiate on the requested
+   * option(s), we could, but we don't, because except for the
+   * authentication type and quality protocol, if we are not negotiating
+   * an option, it is because we were told not to.
+   * For the authentication type, the Nak from the peer means
+   * `let me authenticate myself with you' which is a bit pointless.
+   * For the quality protocol, the Nak means `ask me to send you quality
+   * reports', but if we didn't ask for them, we don't want them.
+   * An option we don't recognize represents the peer asking to
+   * negotiate some option we don't support, so ignore it.
+   */
+  while (len > CILEN_VOID) {
+    GETCHAR(citype, p);
+    GETCHAR(cilen, p);
+    if (cilen < CILEN_VOID || (len -= cilen) < 0) {
+      goto bad;
+    }
+    next = p + cilen - 2;
+
+    switch (citype) {
+      case CI_MRU:
+        if ((go->neg_mru && go->mru != PPP_DEFMRU)
+            || no.neg_mru || cilen != CILEN_SHORT) {
+          goto bad;
+        }
+        GETSHORT(cishort, p);
+        if (cishort < PPP_DEFMRU) {
+          try.mru = cishort;
+        }
+        break;
+      case CI_ASYNCMAP:
+        if ((go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl)
+            || no.neg_asyncmap || cilen != CILEN_LONG) {
+          goto bad;
+        }
+        break;
+      case CI_AUTHTYPE:
+        if (go->neg_chap || no.neg_chap || go->neg_upap || no.neg_upap) {
+          goto bad;
+        }
+        break;
+      case CI_MAGICNUMBER:
+        if (go->neg_magicnumber || no.neg_magicnumber ||
+            cilen != CILEN_LONG) {
+          goto bad;
+        }
+        break;
+      case CI_PCOMPRESSION:
+        if (go->neg_pcompression || no.neg_pcompression
+            || cilen != CILEN_VOID) {
+          goto bad;
+        }
+        break;
+      case CI_ACCOMPRESSION:
+        if (go->neg_accompression || no.neg_accompression
+            || cilen != CILEN_VOID) {
+          goto bad;
+        }
+        break;
+      case CI_QUALITY:
+        if (go->neg_lqr || no.neg_lqr || cilen != CILEN_LQR) {
+          goto bad;
+        }
+        break;
+    }
+    p = next;
+  }
+
+  /* If there is still anything left, this packet is bad. */
+  if (len != 0) {
+    goto bad;
+  }
+
+  /*
+  * OK, the Nak is good.  Now we can update state.
+  */
+  if (f->state != LS_OPENED) {
+    if (looped_back) {
+      if (++try.numloops >= lcp_loopbackfail) {
+        LCPDEBUG((LOG_NOTICE, "Serial line is looped back.\n"));
+        lcp_close(f->unit, "Loopback detected");
+      }
+    } else {
+      try.numloops = 0;
+    }
+    *go = try;
+  }
+
+  return 1;
+
+bad:
+  LCPDEBUG((LOG_WARNING, "lcp_nakci: received bad Nak!\n"));
+  return 0;
+}
+
+
+/*
+ * lcp_rejci - Peer has Rejected some of our CIs.
+ * This should not modify any state if the Reject is bad
+ * or if LCP is in the LS_OPENED state.
+ *
+ * Returns:
+ *  0 - Reject was bad.
+ *  1 - Reject was good.
+ */
+static int
+lcp_rejci(fsm *f, u_char *p, int len)
+{
+  lcp_options *go = &lcp_gotoptions[f->unit];
+  u_char cichar;
+  u_short cishort;
+  u32_t cilong;
+  lcp_options try; /* options to request next time */
+
+  try = *go;
+
+  /*
+   * Any Rejected CIs must be in exactly the same order that we sent.
+   * Check packet length and CI length at each step.
+   * If we find any deviations, then this packet is bad.
+   */
+#define REJCIVOID(opt, neg) \
+  if (go->neg && \
+      len >= CILEN_VOID && \
+      p[1] == CILEN_VOID && \
+      p[0] == opt) { \
+    len -= CILEN_VOID; \
+    INCPTR(CILEN_VOID, p); \
+    try.neg = 0; \
+    LCPDEBUG((LOG_INFO, "lcp_rejci: void opt %d rejected\n", opt)); \
+  }
+#define REJCISHORT(opt, neg, val) \
+  if (go->neg && \
+      len >= CILEN_SHORT && \
+      p[1] == CILEN_SHORT && \
+      p[0] == opt) { \
+    len -= CILEN_SHORT; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    /* Check rejected value. */ \
+    if (cishort != val) { \
+      goto bad; \
+    } \
+    try.neg = 0; \
+    LCPDEBUG((LOG_INFO,"lcp_rejci: short opt %d rejected\n", opt)); \
+  }
+#define REJCICHAP(opt, neg, val, digest) \
+  if (go->neg && \
+      len >= CILEN_CHAP && \
+      p[1] == CILEN_CHAP && \
+      p[0] == opt) { \
+    len -= CILEN_CHAP; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    GETCHAR(cichar, p); \
+    /* Check rejected value. */ \
+    if (cishort != val || cichar != digest) { \
+      goto bad; \
+    } \
+    try.neg = 0; \
+    try.neg_upap = 0; \
+    LCPDEBUG((LOG_INFO,"lcp_rejci: chap opt %d rejected\n", opt)); \
+  }
+#define REJCILONG(opt, neg, val) \
+  if (go->neg && \
+      len >= CILEN_LONG && \
+      p[1] == CILEN_LONG && \
+      p[0] == opt) { \
+    len -= CILEN_LONG; \
+    INCPTR(2, p); \
+    GETLONG(cilong, p); \
+    /* Check rejected value. */ \
+    if (cilong != val) { \
+      goto bad; \
+    } \
+    try.neg = 0; \
+    LCPDEBUG((LOG_INFO,"lcp_rejci: long opt %d rejected\n", opt)); \
+  }
+#define REJCILQR(opt, neg, val) \
+  if (go->neg && \
+      len >= CILEN_LQR && \
+      p[1] == CILEN_LQR && \
+      p[0] == opt) { \
+    len -= CILEN_LQR; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    GETLONG(cilong, p); \
+    /* Check rejected value. */ \
+    if (cishort != PPP_LQR || cilong != val) { \
+      goto bad; \
+    } \
+    try.neg = 0; \
+    LCPDEBUG((LOG_INFO,"lcp_rejci: LQR opt %d rejected\n", opt)); \
+  }
+#define REJCICBCP(opt, neg, val) \
+  if (go->neg && \
+      len >= CILEN_CBCP && \
+      p[1] == CILEN_CBCP && \
+      p[0] == opt) { \
+    len -= CILEN_CBCP; \
+    INCPTR(2, p); \
+    GETCHAR(cichar, p); \
+    /* Check rejected value. */ \
+    if (cichar != val) { \
+      goto bad; \
+    } \
+    try.neg = 0; \
+    LCPDEBUG((LOG_INFO,"lcp_rejci: Callback opt %d rejected\n", opt)); \
+  }
+  
+  REJCISHORT(CI_MRU, neg_mru, go->mru);
+  REJCILONG(CI_ASYNCMAP, neg_asyncmap, go->asyncmap);
+  REJCICHAP(CI_AUTHTYPE, neg_chap, PPP_CHAP, go->chap_mdtype);
+  if (!go->neg_chap) {
+    REJCISHORT(CI_AUTHTYPE, neg_upap, PPP_PAP);
+  }
+  REJCILQR(CI_QUALITY, neg_lqr, go->lqr_period);
+  REJCICBCP(CI_CALLBACK, neg_cbcp, CBCP_OPT);
+  REJCILONG(CI_MAGICNUMBER, neg_magicnumber, go->magicnumber);
+  REJCIVOID(CI_PCOMPRESSION, neg_pcompression);
+  REJCIVOID(CI_ACCOMPRESSION, neg_accompression);
+  
+  /*
+   * If there are any remaining CIs, then this packet is bad.
+   */
+  if (len != 0) {
+    goto bad;
+  }
+  /*
+   * Now we can update state.
+   */
+  if (f->state != LS_OPENED) {
+    *go = try;
+  }
+  return 1;
+  
+bad:
+  LCPDEBUG((LOG_WARNING, "lcp_rejci: received bad Reject!\n"));
+  return 0;
+}
+
+
+/*
+ * lcp_reqci - Check the peer's requested CIs and send appropriate response.
+ *
+ * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified
+ * appropriately.  If reject_if_disagree is non-zero, doesn't return
+ * CONFNAK; returns CONFREJ if it can't return CONFACK.
+ */
+static int
+lcp_reqci(fsm *f, 
+          u_char *inp,    /* Requested CIs */
+          int *lenp,      /* Length of requested CIs */
+          int reject_if_disagree)
+{
+  lcp_options *go = &lcp_gotoptions[f->unit];
+  lcp_options *ho = &lcp_hisoptions[f->unit];
+  lcp_options *ao = &lcp_allowoptions[f->unit];
+  u_char *cip, *next;         /* Pointer to current and next CIs */
+  int cilen, citype, cichar;  /* Parsed len, type, char value */
+  u_short cishort;            /* Parsed short value */
+  u32_t cilong;               /* Parse long value */
+  int rc = CONFACK;           /* Final packet return code */
+  int orc;                    /* Individual option return code */
+  u_char *p;                  /* Pointer to next char to parse */
+  u_char *rejp;               /* Pointer to next char in reject frame */
+  u_char *nakp;               /* Pointer to next char in Nak frame */
+  int l = *lenp;              /* Length left */
+#if TRACELCP > 0
+  char traceBuf[80];
+  int traceNdx = 0;
+#endif
+
+  /*
+   * Reset all his options.
+   */
+  BZERO(ho, sizeof(*ho));
+
+  /*
+   * Process all his options.
+   */
+  next = inp;
+  nakp = nak_buffer;
+  rejp = inp;
+  while (l) {
+    orc = CONFACK;      /* Assume success */
+    cip = p = next;     /* Remember begining of CI */
+    if (l < 2 ||        /* Not enough data for CI header or */
+        p[1] < 2 ||     /*  CI length too small or */
+        p[1] > l) {     /*  CI length too big? */
+      LCPDEBUG((LOG_WARNING, "lcp_reqci: bad CI length!\n"));
+      orc = CONFREJ;    /* Reject bad CI */
+      cilen = l;        /* Reject till end of packet */
+      l = 0;            /* Don't loop again */
+      citype = 0;
+      goto endswitch;
+    }
+    GETCHAR(citype, p); /* Parse CI type */
+    GETCHAR(cilen, p);  /* Parse CI length */
+    l -= cilen;         /* Adjust remaining length */
+    next += cilen;      /* Step to next CI */
+
+    switch (citype) {   /* Check CI type */
+      case CI_MRU:
+        if (!ao->neg_mru) {    /* Allow option? */
+          LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - not allowed\n"));
+          orc = CONFREJ;    /* Reject CI */
+          break;
+        } else if (cilen != CILEN_SHORT) {  /* Check CI length */
+          LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - bad length\n"));
+          orc = CONFREJ;    /* Reject CI */
+          break;
+        }
+        GETSHORT(cishort, p);  /* Parse MRU */
+
+        /*
+         * He must be able to receive at least our minimum.
+         * No need to check a maximum.  If he sends a large number,
+         * we'll just ignore it.
+         */
+        if (cishort < PPP_MINMRU) {
+          LCPDEBUG((LOG_INFO, "lcp_reqci: Nak - MRU too small\n"));
+          orc = CONFNAK;    /* Nak CI */
+          PUTCHAR(CI_MRU, nakp);
+          PUTCHAR(CILEN_SHORT, nakp);
+          PUTSHORT(PPP_MINMRU, nakp);  /* Give him a hint */
+          break;
+        }
+        ho->neg_mru = 1;    /* Remember he sent MRU */
+        ho->mru = cishort;    /* And remember value */
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MRU %d", cishort);
+        traceNdx = strlen(traceBuf);
+#endif
+        break;
+
+      case CI_ASYNCMAP:
+        if (!ao->neg_asyncmap) {
+          LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP not allowed\n"));
+          orc = CONFREJ;
+          break;
+        } else if (cilen != CILEN_LONG) {
+          LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP bad length\n"));
+          orc = CONFREJ;
+          break;
+        }
+        GETLONG(cilong, p);
+        
+        /*
+         * Asyncmap must have set at least the bits
+         * which are set in lcp_allowoptions[unit].asyncmap.
+         */
+        if ((ao->asyncmap & ~cilong) != 0) {
+          LCPDEBUG((LOG_INFO, "lcp_reqci: Nak ASYNCMAP %lX missing %lX\n", 
+                    cilong, ao->asyncmap));
+          orc = CONFNAK;
+          PUTCHAR(CI_ASYNCMAP, nakp);
+          PUTCHAR(CILEN_LONG, nakp);
+          PUTLONG(ao->asyncmap | cilong, nakp);
+          break;
+        }
+        ho->neg_asyncmap = 1;
+        ho->asyncmap = cilong;
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ASYNCMAP=%lX", cilong);
+        traceNdx = strlen(traceBuf);
+#endif
+        break;
+
+      case CI_AUTHTYPE:
+        if (cilen < CILEN_SHORT) {
+          LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE missing arg\n"));
+          orc = CONFREJ;
+          break;
+        } else if (!(ao->neg_upap || ao->neg_chap)) {
+          /*
+           * Reject the option if we're not willing to authenticate.
+           */
+          LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE not allowed\n"));
+          orc = CONFREJ;
+          break;
+        }
+        GETSHORT(cishort, p);
+        
+        /*
+         * Authtype must be UPAP or CHAP.
+         *
+         * Note: if both ao->neg_upap and ao->neg_chap are set,
+         * and the peer sends a Configure-Request with two
+         * authenticate-protocol requests, one for CHAP and one
+         * for UPAP, then we will reject the second request.
+         * Whether we end up doing CHAP or UPAP depends then on
+         * the ordering of the CIs in the peer's Configure-Request.
+         */
+        
+        if (cishort == PPP_PAP) {
+          if (ho->neg_chap) {  /* we've already accepted CHAP */
+            LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP already accepted\n"));
+            orc = CONFREJ;
+            break;
+          } else if (cilen != CILEN_SHORT) {
+            LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP bad len\n"));
+            orc = CONFREJ;
+            break;
+          }
+          if (!ao->neg_upap) {  /* we don't want to do PAP */
+            LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE PAP not allowed\n"));
+            orc = CONFNAK;  /* NAK it and suggest CHAP */
+            PUTCHAR(CI_AUTHTYPE, nakp);
+            PUTCHAR(CILEN_CHAP, nakp);
+            PUTSHORT(PPP_CHAP, nakp);
+            PUTCHAR(ao->chap_mdtype, nakp);
+            break;
+          }
+          ho->neg_upap = 1;
+#if TRACELCP > 0
+          snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PAP (%X)", cishort);
+          traceNdx = strlen(traceBuf);
+#endif
+          break;
+        }
+        if (cishort == PPP_CHAP) {
+          if (ho->neg_upap) {  /* we've already accepted PAP */
+            LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP accepted PAP\n"));
+            orc = CONFREJ;
+            break;
+          } else if (cilen != CILEN_CHAP) {
+            LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP bad len\n"));
+            orc = CONFREJ;
+            break;
+          }
+          if (!ao->neg_chap) {  /* we don't want to do CHAP */
+            LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP not allowed\n"));
+            orc = CONFNAK;  /* NAK it and suggest PAP */
+            PUTCHAR(CI_AUTHTYPE, nakp);
+            PUTCHAR(CILEN_SHORT, nakp);
+            PUTSHORT(PPP_PAP, nakp);
+            break;
+          }
+          GETCHAR(cichar, p);  /* get digest type*/
+          if (cichar != CHAP_DIGEST_MD5
+#ifdef CHAPMS
+              && cichar != CHAP_MICROSOFT
+#endif
+          ) {
+            LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP digest=%d\n", cichar));
+            orc = CONFNAK;
+            PUTCHAR(CI_AUTHTYPE, nakp);
+            PUTCHAR(CILEN_CHAP, nakp);
+            PUTSHORT(PPP_CHAP, nakp);
+            PUTCHAR(ao->chap_mdtype, nakp);
+            break;
+          }
+#if TRACELCP > 0
+          snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CHAP %X,%d", cishort, cichar);
+          traceNdx = strlen(traceBuf);
+#endif
+          ho->chap_mdtype = cichar; /* save md type */
+          ho->neg_chap = 1;
+          break;
+        }
+        
+        /*
+         * We don't recognize the protocol they're asking for.
+         * Nak it with something we're willing to do.
+         * (At this point we know ao->neg_upap || ao->neg_chap.)
+         */
+        orc = CONFNAK;
+        PUTCHAR(CI_AUTHTYPE, nakp);
+        if (ao->neg_chap) {
+          LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req CHAP\n", cishort));
+          PUTCHAR(CILEN_CHAP, nakp);
+          PUTSHORT(PPP_CHAP, nakp);
+          PUTCHAR(ao->chap_mdtype, nakp);
+        } else {
+          LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req PAP\n", cishort));
+          PUTCHAR(CILEN_SHORT, nakp);
+          PUTSHORT(PPP_PAP, nakp);
+        }
+        break;
+      
+      case CI_QUALITY:
+        GETSHORT(cishort, p);
+        GETLONG(cilong, p);
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " QUALITY (%x %x)", cishort, (unsigned int) cilong);
+        traceNdx = strlen(traceBuf);
+#endif
+
+        if (!ao->neg_lqr ||
+            cilen != CILEN_LQR) {
+          orc = CONFREJ;
+          break;
+        }
+        
+        /*
+         * Check the protocol and the reporting period.
+         * XXX When should we Nak this, and what with?
+         */
+        if (cishort != PPP_LQR) {
+          orc = CONFNAK;
+          PUTCHAR(CI_QUALITY, nakp);
+          PUTCHAR(CILEN_LQR, nakp);
+          PUTSHORT(PPP_LQR, nakp);
+          PUTLONG(ao->lqr_period, nakp);
+          break;
+        }
+        break;
+      
+      case CI_MAGICNUMBER:
+        if (!(ao->neg_magicnumber || go->neg_magicnumber) ||
+            cilen != CILEN_LONG) {
+          orc = CONFREJ;
+          break;
+        }
+        GETLONG(cilong, p);
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MAGICNUMBER (%lX)", cilong);
+        traceNdx = strlen(traceBuf);
+#endif
+
+        /*
+         * He must have a different magic number.
+         */
+        if (go->neg_magicnumber &&
+            cilong == go->magicnumber) {
+          cilong = magic();  /* Don't put magic() inside macro! */
+          orc = CONFNAK;
+          PUTCHAR(CI_MAGICNUMBER, nakp);
+          PUTCHAR(CILEN_LONG, nakp);
+          PUTLONG(cilong, nakp);
+          break;
+        }
+        ho->neg_magicnumber = 1;
+        ho->magicnumber = cilong;
+        break;
+      
+      
+      case CI_PCOMPRESSION:
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PCOMPRESSION");
+        traceNdx = strlen(traceBuf);
+#endif
+        if (!ao->neg_pcompression ||
+            cilen != CILEN_VOID) {
+          orc = CONFREJ;
+          break;
+        }
+        ho->neg_pcompression = 1;
+        break;
+      
+      case CI_ACCOMPRESSION:
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ACCOMPRESSION");
+        traceNdx = strlen(traceBuf);
+#endif
+        if (!ao->neg_accompression ||
+            cilen != CILEN_VOID) {
+          orc = CONFREJ;
+          break;
+        }
+        ho->neg_accompression = 1;
+        break;
+      
+      case CI_MRRU:
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_MRRU");
+        traceNdx = strlen(traceBuf);
+#endif
+        orc = CONFREJ;
+        break;
+      
+      case CI_SSNHF:
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_SSNHF");
+        traceNdx = strlen(traceBuf);
+#endif
+        orc = CONFREJ;
+        break;
+      
+      case CI_EPDISC:
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_EPDISC");
+        traceNdx = strlen(traceBuf);
+#endif
+        orc = CONFREJ;
+        break;
+      
+      default:
+#if TRACELCP
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " unknown %d", citype);
+        traceNdx = strlen(traceBuf);
+#endif
+        orc = CONFREJ;
+        break;
+    }
+
+  endswitch:
+#if TRACELCP
+    if (traceNdx >= 80 - 32) {
+      LCPDEBUG((LOG_INFO, "lcp_reqci: rcvd%s\n", traceBuf));
+      traceNdx = 0;
+    }
+#endif
+    if (orc == CONFACK && /* Good CI */
+        rc != CONFACK) {  /*  but prior CI wasnt? */
+      continue;           /* Don't send this one */
+    }
+
+    if (orc == CONFNAK) {     /* Nak this CI? */
+      if (reject_if_disagree  /* Getting fed up with sending NAKs? */
+          && citype != CI_MAGICNUMBER) {
+        orc = CONFREJ;        /* Get tough if so */
+      } else {
+        if (rc == CONFREJ) {  /* Rejecting prior CI? */
+          continue;           /* Don't send this one */
+        }
+        rc = CONFNAK;
+      }
+    }
+    if (orc == CONFREJ) {        /* Reject this CI */
+      rc = CONFREJ;
+      if (cip != rejp) {         /* Need to move rejected CI? */
+        BCOPY(cip, rejp, cilen); /* Move it */
+      }
+      INCPTR(cilen, rejp);       /* Update output pointer */
+    }
+  }
+
+  /*
+   * If we wanted to send additional NAKs (for unsent CIs), the
+   * code would go here.  The extra NAKs would go at *nakp.
+   * At present there are no cases where we want to ask the
+   * peer to negotiate an option.
+   */
+
+  switch (rc) {
+    case CONFACK:
+      *lenp = (int)(next - inp);
+      break;
+    case CONFNAK:
+      /*
+       * Copy the Nak'd options from the nak_buffer to the caller's buffer.
+       */
+      *lenp = (int)(nakp - nak_buffer);
+      BCOPY(nak_buffer, inp, *lenp);
+      break;
+    case CONFREJ:
+      *lenp = (int)(rejp - inp);
+      break;
+  }
+
+#if TRACELCP > 0
+  if (traceNdx > 0) {
+    LCPDEBUG((LOG_INFO, "lcp_reqci: %s\n", traceBuf));
+  }
+#endif
+  LCPDEBUG((LOG_INFO, "lcp_reqci: returning CONF%s.\n", CODENAME(rc)));
+  return (rc);      /* Return final code */
+}
+
+
+/*
+ * lcp_up - LCP has come UP.
+ */
+static void
+lcp_up(fsm *f)
+{
+  lcp_options *wo = &lcp_wantoptions[f->unit];
+  lcp_options *ho = &lcp_hisoptions[f->unit];
+  lcp_options *go = &lcp_gotoptions[f->unit];
+  lcp_options *ao = &lcp_allowoptions[f->unit];
+
+  if (!go->neg_magicnumber) {
+    go->magicnumber = 0;
+  }
+  if (!ho->neg_magicnumber) {
+    ho->magicnumber = 0;
+  }
+
+  /*
+   * Set our MTU to the smaller of the MTU we wanted and
+   * the MRU our peer wanted.  If we negotiated an MRU,
+   * set our MRU to the larger of value we wanted and
+   * the value we got in the negotiation.
+   */
+  ppp_send_config(f->unit, LWIP_MIN(ao->mru, (ho->neg_mru? ho->mru: PPP_MRU)),
+                 (ho->neg_asyncmap? ho->asyncmap: 0xffffffffl),
+                  ho->neg_pcompression, ho->neg_accompression);
+  /*
+   * If the asyncmap hasn't been negotiated, we really should
+   * set the receive asyncmap to ffffffff, but we set it to 0
+   * for backwards contemptibility.
+   */
+  ppp_recv_config(f->unit, (go->neg_mru? LWIP_MAX(wo->mru, go->mru): PPP_MRU),
+                 (go->neg_asyncmap? go->asyncmap: 0x00000000),
+                  go->neg_pcompression, go->neg_accompression);
+
+  if (ho->neg_mru) {
+    peer_mru[f->unit] = ho->mru;
+  }
+
+  lcp_echo_lowerup(f->unit); /* Enable echo messages */
+
+  link_established(f->unit);
+}
+
+
+/*
+ * lcp_down - LCP has gone DOWN.
+ *
+ * Alert other protocols.
+ */
+static void
+lcp_down(fsm *f)
+{
+  lcp_options *go = &lcp_gotoptions[f->unit];
+
+  lcp_echo_lowerdown(f->unit);
+
+  link_down(f->unit);
+
+  ppp_send_config(f->unit, PPP_MRU, 0xffffffffl, 0, 0);
+  ppp_recv_config(f->unit, PPP_MRU,
+                  (go->neg_asyncmap? go->asyncmap: 0x00000000),
+                   go->neg_pcompression, go->neg_accompression);
+  peer_mru[f->unit] = PPP_MRU;
+}
+
+
+/*
+ * lcp_starting - LCP needs the lower layer up.
+ */
+static void
+lcp_starting(fsm *f)
+{
+  link_required(f->unit);
+}
+
+
+/*
+ * lcp_finished - LCP has finished with the lower layer.
+ */
+static void
+lcp_finished(fsm *f)
+{
+  link_terminated(f->unit);
+}
+
+
+#if 0
+/*
+ * print_string - print a readable representation of a string using
+ * printer.
+ */
+static void
+print_string( char *p, int len, void (*printer) (void *, char *, ...), void *arg)
+{
+  int c;
+  
+  printer(arg, "\"");
+  for (; len > 0; --len) {
+    c = *p++;
+    if (' ' <= c && c <= '~') {
+        if (c == '\\' || c == '"') {
+          printer(arg, "\\");
+        }
+        printer(arg, "%c", c);
+    } else {
+      switch (c) {
+        case '\n':
+          printer(arg, "\\n");
+          break;
+        case '\r':
+          printer(arg, "\\r");
+          break;
+        case '\t':
+          printer(arg, "\\t");
+          break;
+        default:
+          printer(arg, "\\%.3o", c);
+        }
+    }
+  }
+  printer(arg, "\"");
+}
+
+
+/*
+ * lcp_printpkt - print the contents of an LCP packet.
+ */
+static char *lcp_codenames[] = {
+  "ConfReq", "ConfAck", "ConfNak", "ConfRej",
+  "TermReq", "TermAck", "CodeRej", "ProtRej",
+  "EchoReq", "EchoRep", "DiscReq"
+};
+
+static int
+lcp_printpkt( u_char *p, int plen, void (*printer) (void *, char *, ...), void *arg)
+{
+  int code, id, len, olen;
+  u_char *pstart, *optend;
+  u_short cishort;
+  u32_t cilong;
+
+  if (plen < HEADERLEN) {
+    return 0;
+  }
+  pstart = p;
+  GETCHAR(code, p);
+  GETCHAR(id, p);
+  GETSHORT(len, p);
+  if (len < HEADERLEN || len > plen) {
+    return 0;
+  }
+
+  if (code >= 1 && code <= sizeof(lcp_codenames) / sizeof(char *)) {
+    printer(arg, " %s", lcp_codenames[code-1]);
+  } else {
+    printer(arg, " code=0x%x", code);
+  }
+  printer(arg, " id=0x%x", id);
+  len -= HEADERLEN;
+  switch (code) {
+    case CONFREQ:
+    case CONFACK:
+    case CONFNAK:
+    case CONFREJ:
+      /* print option list */
+      while (len >= 2) {
+        GETCHAR(code, p);
+        GETCHAR(olen, p);
+        p -= 2;
+        if (olen < 2 || olen > len) {
+          break;
+        }
+        printer(arg, " <");
+        len -= olen;
+        optend = p + olen;
+        switch (code) {
+          case CI_MRU:
+            if (olen == CILEN_SHORT) {
+              p += 2;
+              GETSHORT(cishort, p);
+              printer(arg, "mru %d", cishort);
+            }
+            break;
+          case CI_ASYNCMAP:
+            if (olen == CILEN_LONG) {
+              p += 2;
+              GETLONG(cilong, p);
+              printer(arg, "asyncmap 0x%lx", cilong);
+            }
+            break;
+          case CI_AUTHTYPE:
+            if (olen >= CILEN_SHORT) {
+              p += 2;
+              printer(arg, "auth ");
+              GETSHORT(cishort, p);
+              switch (cishort) {
+                case PPP_PAP:
+                  printer(arg, "pap");
+                  break;
+                case PPP_CHAP:
+                  printer(arg, "chap");
+                  break;
+                default:
+                  printer(arg, "0x%x", cishort);
+              }
+            }
+            break;
+          case CI_QUALITY:
+            if (olen >= CILEN_SHORT) {
+              p += 2;
+              printer(arg, "quality ");
+              GETSHORT(cishort, p);
+              switch (cishort) {
+                case PPP_LQR:
+                  printer(arg, "lqr");
+                  break;
+                default:
+                  printer(arg, "0x%x", cishort);
+              }
+            }
+            break;
+          case CI_CALLBACK:
+            if (olen >= CILEN_CHAR) {
+              p += 2;
+              printer(arg, "callback ");
+              GETSHORT(cishort, p);
+              switch (cishort) {
+                case CBCP_OPT:
+                  printer(arg, "CBCP");
+                  break;
+                default:
+                  printer(arg, "0x%x", cishort);
+              }
+            }
+            break;
+          case CI_MAGICNUMBER:
+            if (olen == CILEN_LONG) {
+              p += 2;
+              GETLONG(cilong, p);
+              printer(arg, "magic 0x%x", cilong);
+            }
+            break;
+          case CI_PCOMPRESSION:
+            if (olen == CILEN_VOID) {
+              p += 2;
+              printer(arg, "pcomp");
+            }
+            break;
+          case CI_ACCOMPRESSION:
+            if (olen == CILEN_VOID) {
+              p += 2;
+              printer(arg, "accomp");
+            }
+            break;
+        }
+        while (p < optend) {
+          GETCHAR(code, p);
+          printer(arg, " %.2x", code);
+        }
+        printer(arg, ">");
+      }
+      break;
+    
+    case TERMACK:
+    case TERMREQ:
+      if (len > 0 && *p >= ' ' && *p < 0x7f) {
+        printer(arg, " ");
+        print_string((char*)p, len, printer, arg);
+        p += len;
+        len = 0;
+      }
+      break;
+    
+    case ECHOREQ:
+    case ECHOREP:
+    case DISCREQ:
+      if (len >= 4) {
+        GETLONG(cilong, p);
+        printer(arg, " magic=0x%x", cilong);
+        p += 4;
+        len -= 4;
+      }
+      break;
+  }
+
+  /* print the rest of the bytes in the packet */
+  for (; len > 0; --len) {
+    GETCHAR(code, p);
+    printer(arg, " %.2x", code);
+  }
+
+  return (int)(p - pstart);
+}
+#endif
+
+/*
+ * Time to shut down the link because there is nothing out there.
+ */
+static void
+LcpLinkFailure (fsm *f)
+{
+  if (f->state == LS_OPENED) {
+    LCPDEBUG((LOG_INFO, "No response to %d echo-requests\n", lcp_echos_pending));
+    LCPDEBUG((LOG_NOTICE, "Serial link appears to be disconnected.\n"));
+    lcp_close(f->unit, "Peer not responding");
+  }
+}
+
+/*
+ * Timer expired for the LCP echo requests from this process.
+ */
+static void
+LcpEchoCheck (fsm *f)
+{
+  LcpSendEchoRequest (f);
+
+  /*
+   * Start the timer for the next interval.
+   */
+  LWIP_ASSERT("lcp_echo_timer_running == 0", lcp_echo_timer_running == 0);
+
+  TIMEOUT (LcpEchoTimeout, f, lcp_echo_interval);
+  lcp_echo_timer_running = 1;
+}
+
+/*
+ * LcpEchoTimeout - Timer expired on the LCP echo
+ */
+static void
+LcpEchoTimeout (void *arg)
+{
+  if (lcp_echo_timer_running != 0) {
+    lcp_echo_timer_running = 0;
+    LcpEchoCheck ((fsm *) arg);
+  }
+}
+
+/*
+ * LcpEchoReply - LCP has received a reply to the echo
+ */
+static void
+lcp_received_echo_reply (fsm *f, int id, u_char *inp, int len)
+{
+  u32_t magic;
+
+  LWIP_UNUSED_ARG(id);
+
+  /* Check the magic number - don't count replies from ourselves. */
+  if (len < 4) {
+    LCPDEBUG((LOG_WARNING, "lcp: received short Echo-Reply, length %d\n", len));
+    return;
+  }
+  GETLONG(magic, inp);
+  if (lcp_gotoptions[f->unit].neg_magicnumber && magic == lcp_gotoptions[f->unit].magicnumber) {
+    LCPDEBUG((LOG_WARNING, "appear to have received our own echo-reply!\n"));
+    return;
+  }
+  
+  /* Reset the number of outstanding echo frames */
+  lcp_echos_pending = 0;
+}
+
+/*
+ * LcpSendEchoRequest - Send an echo request frame to the peer
+ */
+static void
+LcpSendEchoRequest (fsm *f)
+{
+  u32_t lcp_magic;
+  u_char pkt[4], *pktp;
+
+  /*
+   * Detect the failure of the peer at this point.
+   */
+  if (lcp_echo_fails != 0) {
+    if (lcp_echos_pending++ >= lcp_echo_fails) {
+      LcpLinkFailure(f);
+      lcp_echos_pending = 0;
+    }
+  }
+
+  /*
+   * Make and send the echo request frame.
+   */
+  if (f->state == LS_OPENED) {
+    lcp_magic = lcp_gotoptions[f->unit].magicnumber;
+    pktp = pkt;
+    PUTLONG(lcp_magic, pktp);
+    fsm_sdata(f, ECHOREQ, (u_char)(lcp_echo_number++ & 0xFF), pkt, (int)(pktp - pkt));
+  }
+}
+
+/*
+ * lcp_echo_lowerup - Start the timer for the LCP frame
+ */
+
+static void
+lcp_echo_lowerup (int unit)
+{
+  fsm *f = &lcp_fsm[unit];
+
+  /* Clear the parameters for generating echo frames */
+  lcp_echos_pending      = 0;
+  lcp_echo_number        = 0;
+  lcp_echo_timer_running = 0;
+
+  /* If a timeout interval is specified then start the timer */
+  if (lcp_echo_interval != 0) {
+    LcpEchoCheck (f);
+  }
+}
+
+/*
+ * lcp_echo_lowerdown - Stop the timer for the LCP frame
+ */
+
+static void
+lcp_echo_lowerdown (int unit)
+{
+  fsm *f = &lcp_fsm[unit];
+
+  if (lcp_echo_timer_running != 0) {
+    UNTIMEOUT (LcpEchoTimeout, f);
+    lcp_echo_timer_running = 0;
+  }
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/lcp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/lcp.h
new file mode 100644
index 0000000..5e3f757
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/lcp.h
@@ -0,0 +1,167 @@
+/*****************************************************************************
+* lcp.h - Network Link Control Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * lcp.h - Link Control Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: lcp.h,v 1.3 2007/12/19 20:47:23 fbernon Exp $
+ */
+
+#ifndef LCP_H
+#define LCP_H
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+/*
+ * Options.
+ */
+#define CI_MRU           1  /* Maximum Receive Unit */
+#define CI_ASYNCMAP      2  /* Async Control Character Map */
+#define CI_AUTHTYPE      3  /* Authentication Type */
+#define CI_QUALITY       4  /* Quality Protocol */
+#define CI_MAGICNUMBER   5  /* Magic Number */
+#define CI_PCOMPRESSION  7  /* Protocol Field Compression */
+#define CI_ACCOMPRESSION 8  /* Address/Control Field Compression */
+#define CI_CALLBACK      13 /* callback */
+#define CI_MRRU          17 /* max reconstructed receive unit; multilink */
+#define CI_SSNHF         18 /* short sequence numbers for multilink */
+#define CI_EPDISC        19 /* endpoint discriminator */
+
+/*
+ * LCP-specific packet types.
+ */
+#define PROTREJ          8  /* Protocol Reject */
+#define ECHOREQ          9  /* Echo Request */
+#define ECHOREP          10 /* Echo Reply */
+#define DISCREQ          11 /* Discard Request */
+#define CBCP_OPT         6  /* Use callback control protocol */
+
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * The state of options is described by an lcp_options structure.
+ */
+typedef struct lcp_options {
+    u_int passive           : 1; /* Don't die if we don't get a response */
+    u_int silent            : 1; /* Wait for the other end to start first */
+    u_int restart           : 1; /* Restart vs. exit after close */
+    u_int neg_mru           : 1; /* Negotiate the MRU? */
+    u_int neg_asyncmap      : 1; /* Negotiate the async map? */
+    u_int neg_upap          : 1; /* Ask for UPAP authentication? */
+    u_int neg_chap          : 1; /* Ask for CHAP authentication? */
+    u_int neg_magicnumber   : 1; /* Ask for magic number? */
+    u_int neg_pcompression  : 1; /* HDLC Protocol Field Compression? */
+    u_int neg_accompression : 1; /* HDLC Address/Control Field Compression? */
+    u_int neg_lqr           : 1; /* Negotiate use of Link Quality Reports */
+    u_int neg_cbcp          : 1; /* Negotiate use of CBCP */
+#ifdef PPP_MULTILINK
+    u_int neg_mrru          : 1; /* Negotiate multilink MRRU */
+    u_int neg_ssnhf         : 1; /* Negotiate short sequence numbers */
+    u_int neg_endpoint      : 1; /* Negotiate endpoint discriminator */
+#endif
+    u_short mru;                 /* Value of MRU */
+#ifdef PPP_MULTILINK
+    u_short mrru;                /* Value of MRRU, and multilink enable */
+#endif
+    u_char chap_mdtype;          /* which MD type (hashing algorithm) */
+    u32_t asyncmap;              /* Value of async map */
+    u32_t magicnumber;
+    int numloops;                /* Number of loops during magic number neg. */
+    u32_t lqr_period;            /* Reporting period for LQR 1/100ths second */
+#ifdef PPP_MULTILINK
+    struct epdisc endpoint;      /* endpoint discriminator */
+#endif
+} lcp_options;
+
+/*
+ * Values for phase from BSD pppd.h based on RFC 1661.
+ */
+typedef enum {
+  PHASE_DEAD = 0,
+  PHASE_INITIALIZE,
+  PHASE_ESTABLISH,
+  PHASE_AUTHENTICATE,
+  PHASE_CALLBACK,
+  PHASE_NETWORK,
+  PHASE_TERMINATE
+} LinkPhase;
+
+
+/*****************************
+*** PUBLIC DATA STRUCTURES ***
+*****************************/
+
+extern LinkPhase lcp_phase[NUM_PPP]; /* Phase of link session (RFC 1661) */
+extern lcp_options lcp_wantoptions[];
+extern lcp_options lcp_gotoptions[];
+extern lcp_options lcp_allowoptions[];
+extern lcp_options lcp_hisoptions[];
+extern ext_accm xmit_accm[];
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+void lcp_init     (int);
+void lcp_open     (int);
+void lcp_close    (int, char *);
+void lcp_lowerup  (int);
+void lcp_lowerdown(int);
+void lcp_sprotrej (int, u_char *, int); /* send protocol reject */
+
+extern struct protent lcp_protent;
+
+/* Default number of times we receive our magic number from the peer
+   before deciding the link is looped-back. */
+#define DEFLOOPBACKFAIL 10
+
+#endif /* LCP_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/magic.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/magic.c
new file mode 100644
index 0000000..e4ff2e6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/magic.c
@@ -0,0 +1,82 @@
+/*****************************************************************************
+* magic.c - Network Random Number Generator program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*   Original based on BSD magic.c.
+*****************************************************************************/
+/*
+ * magic.c - PPP Magic Number routines.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT
+
+#include "ppp.h"
+#include "randm.h"
+#include "magic.h"
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * magicInit - Initialize the magic number generator.
+ *
+ * Since we use another random number generator that has its own
+ * initialization, we do nothing here.
+ */
+void magicInit()
+{
+  return;
+}
+
+/*
+ * magic - Returns the next magic number.
+ */
+u32_t magic()
+{
+  return avRandom();
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/magic.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/magic.h
new file mode 100644
index 0000000..2082349
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/magic.h
@@ -0,0 +1,67 @@
+/*****************************************************************************
+* magic.h - Network Random Number Generator header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * magic.h - PPP Magic Number definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: magic.h,v 1.2 2007/12/02 22:35:55 fbernon Exp $
+ */
+
+#ifndef MAGIC_H
+#define MAGIC_H
+
+/*****************************************************************************
+************************** PUBLIC FUNCTIONS **********************************
+*****************************************************************************/
+
+/* Initialize the magic number generator */
+void  magicInit(void);
+
+/* Returns the next magic number */
+u32_t magic(void);
+
+#endif /* MAGIC_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/md5.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/md5.c
new file mode 100644
index 0000000..87c219c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/md5.c
@@ -0,0 +1,318 @@
+/*
+ ***********************************************************************
+ ** md5.c -- the source code for MD5 routines                         **
+ ** RSA Data Security, Inc. MD5 Message-Digest Algorithm              **
+ ** Created: 2/17/90 RLR                                              **
+ ** Revised: 1/91 SRD,AJ,BSK,JT Reference C ver., 7/10 constant corr. **
+ ***********************************************************************
+ */
+
+/*
+ ***********************************************************************
+ ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved.  **
+ **                                                                   **
+ ** License to copy and use this software is granted provided that    **
+ ** it is identified as the "RSA Data Security, Inc. MD5 Message-     **
+ ** Digest Algorithm" in all material mentioning or referencing this  **
+ ** software or this function.                                        **
+ **                                                                   **
+ ** License is also granted to make and use derivative works          **
+ ** provided that such works are identified as "derived from the RSA  **
+ ** Data Security, Inc. MD5 Message-Digest Algorithm" in all          **
+ ** material mentioning or referencing the derived work.              **
+ **                                                                   **
+ ** RSA Data Security, Inc. makes no representations concerning       **
+ ** either the merchantability of this software or the suitability    **
+ ** of this software for any particular purpose.  It is provided "as  **
+ ** is" without express or implied warranty of any kind.              **
+ **                                                                   **
+ ** These notices must be retained in any copies of any part of this  **
+ ** documentation and/or software.                                    **
+ ***********************************************************************
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#if CHAP_SUPPORT || MD5_SUPPORT
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "md5.h"
+
+/*
+ ***********************************************************************
+ **  Message-digest routines:                                         **
+ **  To form the message digest for a message M                       **
+ **    (1) Initialize a context buffer mdContext using MD5Init        **
+ **    (2) Call MD5Update on mdContext and M                          **
+ **    (3) Call MD5Final on mdContext                                 **
+ **  The message digest is now in mdContext->digest[0...15]           **
+ ***********************************************************************
+ */
+
+/* forward declaration */
+static void Transform (u32_t *buf, u32_t *in);
+
+static unsigned char PADDING[64] = {
+  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+/* F, G, H and I are basic MD5 functions */
+#define F(x, y, z) (((x) & (y)) | ((~x) & (z)))
+#define G(x, y, z) (((x) & (z)) | ((y) & (~z)))
+#define H(x, y, z) ((x) ^ (y) ^ (z))
+#define I(x, y, z) ((y) ^ ((x) | (~z)))
+
+/* ROTATE_LEFT rotates x left n bits */
+#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n))))
+
+/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4 */
+/* Rotation is separate from addition to prevent recomputation */
+#define FF(a, b, c, d, x, s, ac) \
+  {(a) += F ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+#define GG(a, b, c, d, x, s, ac) \
+  {(a) += G ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+#define HH(a, b, c, d, x, s, ac) \
+  {(a) += H ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+#define II(a, b, c, d, x, s, ac) \
+  {(a) += I ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+
+#ifdef __STDC__
+#define UL(x) x##UL
+#else
+#ifdef WIN32
+#define UL(x) x##UL
+#else
+#define UL(x) x
+#endif
+#endif
+
+/* The routine MD5Init initializes the message-digest context
+   mdContext. All fields are set to zero.
+ */
+void
+MD5Init (MD5_CTX *mdContext)
+{
+  mdContext->i[0] = mdContext->i[1] = (u32_t)0;
+
+  /* Load magic initialization constants. */
+  mdContext->buf[0] = (u32_t)0x67452301UL;
+  mdContext->buf[1] = (u32_t)0xefcdab89UL;
+  mdContext->buf[2] = (u32_t)0x98badcfeUL;
+  mdContext->buf[3] = (u32_t)0x10325476UL;
+}
+
+/* The routine MD5Update updates the message-digest context to
+   account for the presence of each of the characters inBuf[0..inLen-1]
+   in the message whose digest is being computed.
+ */
+void
+MD5Update(MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen)
+{
+  u32_t in[16];
+  int mdi;
+  unsigned int i, ii;
+
+#if 0
+  ppp_trace(LOG_INFO, "MD5Update: %u:%.*H\n", inLen, MIN(inLen, 20) * 2, inBuf);
+  ppp_trace(LOG_INFO, "MD5Update: %u:%s\n", inLen, inBuf);
+#endif
+  
+  /* compute number of bytes mod 64 */
+  mdi = (int)((mdContext->i[0] >> 3) & 0x3F);
+
+  /* update number of bits */
+  if ((mdContext->i[0] + ((u32_t)inLen << 3)) < mdContext->i[0]) {
+    mdContext->i[1]++;
+  }
+  mdContext->i[0] += ((u32_t)inLen << 3);
+  mdContext->i[1] += ((u32_t)inLen >> 29);
+
+  while (inLen--) {
+    /* add new character to buffer, increment mdi */
+    mdContext->in[mdi++] = *inBuf++;
+
+    /* transform if necessary */
+    if (mdi == 0x40) {
+      for (i = 0, ii = 0; i < 16; i++, ii += 4) {
+        in[i] = (((u32_t)mdContext->in[ii+3]) << 24) |
+                (((u32_t)mdContext->in[ii+2]) << 16) |
+                (((u32_t)mdContext->in[ii+1]) << 8)  |
+                ((u32_t)mdContext->in[ii]);
+      }
+      Transform (mdContext->buf, in);
+      mdi = 0;
+    }
+  }
+}
+
+/* The routine MD5Final terminates the message-digest computation and
+   ends with the desired message digest in mdContext->digest[0...15].
+ */
+void
+MD5Final (unsigned char hash[], MD5_CTX *mdContext)
+{
+  u32_t in[16];
+  int mdi;
+  unsigned int i, ii;
+  unsigned int padLen;
+
+  /* save number of bits */
+  in[14] = mdContext->i[0];
+  in[15] = mdContext->i[1];
+
+  /* compute number of bytes mod 64 */
+  mdi = (int)((mdContext->i[0] >> 3) & 0x3F);
+
+  /* pad out to 56 mod 64 */
+  padLen = (mdi < 56) ? (56 - mdi) : (120 - mdi);
+  MD5Update (mdContext, PADDING, padLen);
+
+  /* append length in bits and transform */
+  for (i = 0, ii = 0; i < 14; i++, ii += 4) {
+    in[i] = (((u32_t)mdContext->in[ii+3]) << 24) |
+            (((u32_t)mdContext->in[ii+2]) << 16) |
+            (((u32_t)mdContext->in[ii+1]) << 8)  |
+            ((u32_t)mdContext->in[ii]);
+  }
+  Transform (mdContext->buf, in);
+
+  /* store buffer in digest */
+  for (i = 0, ii = 0; i < 4; i++, ii += 4) {
+    mdContext->digest[ii]   = (unsigned char)(mdContext->buf[i] & 0xFF);
+    mdContext->digest[ii+1] =
+      (unsigned char)((mdContext->buf[i] >> 8)  & 0xFF);
+    mdContext->digest[ii+2] =
+      (unsigned char)((mdContext->buf[i] >> 16) & 0xFF);
+    mdContext->digest[ii+3] =
+      (unsigned char)((mdContext->buf[i] >> 24) & 0xFF);
+  }
+  SMEMCPY(hash, mdContext->digest, 16);
+}
+
+/* Basic MD5 step. Transforms buf based on in.
+ */
+static void
+Transform (u32_t *buf, u32_t *in)
+{
+  u32_t a = buf[0], b = buf[1], c = buf[2], d = buf[3];
+
+  /* Round 1 */
+#define S11 7
+#define S12 12
+#define S13 17
+#define S14 22
+  FF ( a, b, c, d, in[ 0], S11, UL(3614090360)); /* 1 */
+  FF ( d, a, b, c, in[ 1], S12, UL(3905402710)); /* 2 */
+  FF ( c, d, a, b, in[ 2], S13, UL( 606105819)); /* 3 */
+  FF ( b, c, d, a, in[ 3], S14, UL(3250441966)); /* 4 */
+  FF ( a, b, c, d, in[ 4], S11, UL(4118548399)); /* 5 */
+  FF ( d, a, b, c, in[ 5], S12, UL(1200080426)); /* 6 */
+  FF ( c, d, a, b, in[ 6], S13, UL(2821735955)); /* 7 */
+  FF ( b, c, d, a, in[ 7], S14, UL(4249261313)); /* 8 */
+  FF ( a, b, c, d, in[ 8], S11, UL(1770035416)); /* 9 */
+  FF ( d, a, b, c, in[ 9], S12, UL(2336552879)); /* 10 */
+  FF ( c, d, a, b, in[10], S13, UL(4294925233)); /* 11 */
+  FF ( b, c, d, a, in[11], S14, UL(2304563134)); /* 12 */
+  FF ( a, b, c, d, in[12], S11, UL(1804603682)); /* 13 */
+  FF ( d, a, b, c, in[13], S12, UL(4254626195)); /* 14 */
+  FF ( c, d, a, b, in[14], S13, UL(2792965006)); /* 15 */
+  FF ( b, c, d, a, in[15], S14, UL(1236535329)); /* 16 */
+
+  /* Round 2 */
+#define S21 5
+#define S22 9
+#define S23 14
+#define S24 20
+  GG ( a, b, c, d, in[ 1], S21, UL(4129170786)); /* 17 */
+  GG ( d, a, b, c, in[ 6], S22, UL(3225465664)); /* 18 */
+  GG ( c, d, a, b, in[11], S23, UL( 643717713)); /* 19 */
+  GG ( b, c, d, a, in[ 0], S24, UL(3921069994)); /* 20 */
+  GG ( a, b, c, d, in[ 5], S21, UL(3593408605)); /* 21 */
+  GG ( d, a, b, c, in[10], S22, UL(  38016083)); /* 22 */
+  GG ( c, d, a, b, in[15], S23, UL(3634488961)); /* 23 */
+  GG ( b, c, d, a, in[ 4], S24, UL(3889429448)); /* 24 */
+  GG ( a, b, c, d, in[ 9], S21, UL( 568446438)); /* 25 */
+  GG ( d, a, b, c, in[14], S22, UL(3275163606)); /* 26 */
+  GG ( c, d, a, b, in[ 3], S23, UL(4107603335)); /* 27 */
+  GG ( b, c, d, a, in[ 8], S24, UL(1163531501)); /* 28 */
+  GG ( a, b, c, d, in[13], S21, UL(2850285829)); /* 29 */
+  GG ( d, a, b, c, in[ 2], S22, UL(4243563512)); /* 30 */
+  GG ( c, d, a, b, in[ 7], S23, UL(1735328473)); /* 31 */
+  GG ( b, c, d, a, in[12], S24, UL(2368359562)); /* 32 */
+
+  /* Round 3 */
+#define S31 4
+#define S32 11
+#define S33 16
+#define S34 23
+  HH ( a, b, c, d, in[ 5], S31, UL(4294588738)); /* 33 */
+  HH ( d, a, b, c, in[ 8], S32, UL(2272392833)); /* 34 */
+  HH ( c, d, a, b, in[11], S33, UL(1839030562)); /* 35 */
+  HH ( b, c, d, a, in[14], S34, UL(4259657740)); /* 36 */
+  HH ( a, b, c, d, in[ 1], S31, UL(2763975236)); /* 37 */
+  HH ( d, a, b, c, in[ 4], S32, UL(1272893353)); /* 38 */
+  HH ( c, d, a, b, in[ 7], S33, UL(4139469664)); /* 39 */
+  HH ( b, c, d, a, in[10], S34, UL(3200236656)); /* 40 */
+  HH ( a, b, c, d, in[13], S31, UL( 681279174)); /* 41 */
+  HH ( d, a, b, c, in[ 0], S32, UL(3936430074)); /* 42 */
+  HH ( c, d, a, b, in[ 3], S33, UL(3572445317)); /* 43 */
+  HH ( b, c, d, a, in[ 6], S34, UL(  76029189)); /* 44 */
+  HH ( a, b, c, d, in[ 9], S31, UL(3654602809)); /* 45 */
+  HH ( d, a, b, c, in[12], S32, UL(3873151461)); /* 46 */
+  HH ( c, d, a, b, in[15], S33, UL( 530742520)); /* 47 */
+  HH ( b, c, d, a, in[ 2], S34, UL(3299628645)); /* 48 */
+
+  /* Round 4 */
+#define S41 6
+#define S42 10
+#define S43 15
+#define S44 21
+  II ( a, b, c, d, in[ 0], S41, UL(4096336452)); /* 49 */
+  II ( d, a, b, c, in[ 7], S42, UL(1126891415)); /* 50 */
+  II ( c, d, a, b, in[14], S43, UL(2878612391)); /* 51 */
+  II ( b, c, d, a, in[ 5], S44, UL(4237533241)); /* 52 */
+  II ( a, b, c, d, in[12], S41, UL(1700485571)); /* 53 */
+  II ( d, a, b, c, in[ 3], S42, UL(2399980690)); /* 54 */
+  II ( c, d, a, b, in[10], S43, UL(4293915773)); /* 55 */
+  II ( b, c, d, a, in[ 1], S44, UL(2240044497)); /* 56 */
+  II ( a, b, c, d, in[ 8], S41, UL(1873313359)); /* 57 */
+  II ( d, a, b, c, in[15], S42, UL(4264355552)); /* 58 */
+  II ( c, d, a, b, in[ 6], S43, UL(2734768916)); /* 59 */
+  II ( b, c, d, a, in[13], S44, UL(1309151649)); /* 60 */
+  II ( a, b, c, d, in[ 4], S41, UL(4149444226)); /* 61 */
+  II ( d, a, b, c, in[11], S42, UL(3174756917)); /* 62 */
+  II ( c, d, a, b, in[ 2], S43, UL( 718787259)); /* 63 */
+  II ( b, c, d, a, in[ 9], S44, UL(3951481745)); /* 64 */
+
+  buf[0] += a;
+  buf[1] += b;
+  buf[2] += c;
+  buf[3] += d;
+}
+
+#endif /* CHAP_SUPPORT || MD5_SUPPORT */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/md5.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/md5.h
new file mode 100644
index 0000000..0bcb23c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/md5.h
@@ -0,0 +1,55 @@
+/*
+ ***********************************************************************
+ ** md5.h -- header file for implementation of MD5                    **
+ ** RSA Data Security, Inc. MD5 Message-Digest Algorithm              **
+ ** Created: 2/17/90 RLR                                              **
+ ** Revised: 12/27/90 SRD,AJ,BSK,JT Reference C version               **
+ ** Revised (for MD5): RLR 4/27/91                                    **
+ **   -- G modified to have y&~z instead of y&z                       **
+ **   -- FF, GG, HH modified to add in last register done             **
+ **   -- Access pattern: round 2 works mod 5, round 3 works mod 3     **
+ **   -- distinct additive constant for each step                     **
+ **   -- round 4 added, working mod 7                                 **
+ ***********************************************************************
+ */
+
+/*
+ ***********************************************************************
+ ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved.  **
+ **                                                                   **
+ ** License to copy and use this software is granted provided that    **
+ ** it is identified as the "RSA Data Security, Inc. MD5 Message-     **
+ ** Digest Algorithm" in all material mentioning or referencing this  **
+ ** software or this function.                                        **
+ **                                                                   **
+ ** License is also granted to make and use derivative works          **
+ ** provided that such works are identified as "derived from the RSA  **
+ ** Data Security, Inc. MD5 Message-Digest Algorithm" in all          **
+ ** material mentioning or referencing the derived work.              **
+ **                                                                   **
+ ** RSA Data Security, Inc. makes no representations concerning       **
+ ** either the merchantability of this software or the suitability    **
+ ** of this software for any particular purpose.  It is provided "as  **
+ ** is" without express or implied warranty of any kind.              **
+ **                                                                   **
+ ** These notices must be retained in any copies of any part of this  **
+ ** documentation and/or software.                                    **
+ ***********************************************************************
+ */
+
+#ifndef MD5_H
+#define MD5_H
+
+/* Data structure for MD5 (Message-Digest) computation */
+typedef struct {
+  u32_t i[2];               /* number of _bits_ handled mod 2^64 */
+  u32_t buf[4];             /* scratch buffer */
+  unsigned char in[64];     /* input buffer */
+  unsigned char digest[16]; /* actual digest after MD5Final call */
+} MD5_CTX;
+
+void MD5Init  ( MD5_CTX *mdContext);
+void MD5Update( MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen);
+void MD5Final ( unsigned char hash[], MD5_CTX *mdContext);
+
+#endif /* MD5_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/pap.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/pap.c
new file mode 100644
index 0000000..fea7bbd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/pap.c
@@ -0,0 +1,617 @@
+/*****************************************************************************
+* pap.c - Network Password Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-12 Guy Lancaster , Global Election Systems Inc.
+*   Original.
+*****************************************************************************/
+/*
+ * upap.c - User/Password Authentication Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#if PAP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "auth.h"
+#include "pap.h"
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Protocol entry points.
+ */
+static void upap_init      (int);
+static void upap_lowerup   (int);
+static void upap_lowerdown (int);
+static void upap_input     (int, u_char *, int);
+static void upap_protrej   (int);
+
+static void upap_timeout   (void *);
+static void upap_reqtimeout(void *);
+static void upap_rauthreq  (upap_state *, u_char *, int, int);
+static void upap_rauthack  (upap_state *, u_char *, int, int);
+static void upap_rauthnak  (upap_state *, u_char *, int, int);
+static void upap_sauthreq  (upap_state *);
+static void upap_sresp     (upap_state *, u_char, u_char, char *, int);
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+struct protent pap_protent = {
+  PPP_PAP,
+  upap_init,
+  upap_input,
+  upap_protrej,
+  upap_lowerup,
+  upap_lowerdown,
+  NULL,
+  NULL,
+#if 0
+  upap_printpkt,
+  NULL,
+#endif
+  1,
+  "PAP",
+#if 0
+  NULL,
+  NULL,
+  NULL
+#endif
+};
+
+upap_state upap[NUM_PPP]; /* UPAP state; one for each unit */
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ *  Set the default login name and password for the pap sessions
+ */
+void
+upap_setloginpasswd(int unit, const char *luser, const char *lpassword)
+{
+  upap_state *u = &upap[unit];
+  
+  /* Save the username and password we're given */
+  u->us_user = luser;
+  u->us_userlen = strlen(luser);
+  u->us_passwd = lpassword;
+  u->us_passwdlen = strlen(lpassword);
+}
+
+
+/*
+ * upap_authwithpeer - Authenticate us with our peer (start client).
+ *
+ * Set new state and send authenticate's.
+ */
+void
+upap_authwithpeer(int unit, char *user, char *password)
+{
+  upap_state *u = &upap[unit];
+
+  UPAPDEBUG((LOG_INFO, "upap_authwithpeer: %d user=%s password=%s s=%d\n",
+             unit, user, password, u->us_clientstate));
+
+  upap_setloginpasswd(unit, user, password);
+
+  u->us_transmits = 0;
+
+  /* Lower layer up yet? */
+  if (u->us_clientstate == UPAPCS_INITIAL ||
+      u->us_clientstate == UPAPCS_PENDING) {
+    u->us_clientstate = UPAPCS_PENDING;
+    return;
+  }
+
+  upap_sauthreq(u);      /* Start protocol */
+}
+
+
+/*
+ * upap_authpeer - Authenticate our peer (start server).
+ *
+ * Set new state.
+ */
+void
+upap_authpeer(int unit)
+{
+  upap_state *u = &upap[unit];
+
+  /* Lower layer up yet? */
+  if (u->us_serverstate == UPAPSS_INITIAL ||
+      u->us_serverstate == UPAPSS_PENDING) {
+    u->us_serverstate = UPAPSS_PENDING;
+    return;
+  }
+
+  u->us_serverstate = UPAPSS_LISTEN;
+  if (u->us_reqtimeout > 0) {
+    TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout);
+  }
+}
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * upap_init - Initialize a UPAP unit.
+ */
+static void
+upap_init(int unit)
+{
+  upap_state *u = &upap[unit];
+
+  UPAPDEBUG((LOG_INFO, "upap_init: %d\n", unit));
+  u->us_unit         = unit;
+  u->us_user         = NULL;
+  u->us_userlen      = 0;
+  u->us_passwd       = NULL;
+  u->us_passwdlen    = 0;
+  u->us_clientstate  = UPAPCS_INITIAL;
+  u->us_serverstate  = UPAPSS_INITIAL;
+  u->us_id           = 0;
+  u->us_timeouttime  = UPAP_DEFTIMEOUT;
+  u->us_maxtransmits = 10;
+  u->us_reqtimeout   = UPAP_DEFREQTIME;
+}
+
+/*
+ * upap_timeout - Retransmission timer for sending auth-reqs expired.
+ */
+static void
+upap_timeout(void *arg)
+{
+  upap_state *u = (upap_state *) arg;
+
+  UPAPDEBUG((LOG_INFO, "upap_timeout: %d timeout %d expired s=%d\n", 
+        u->us_unit, u->us_timeouttime, u->us_clientstate));
+
+  if (u->us_clientstate != UPAPCS_AUTHREQ) {
+    return;
+  }
+
+  if (u->us_transmits >= u->us_maxtransmits) {
+    /* give up in disgust */
+    UPAPDEBUG((LOG_ERR, "No response to PAP authenticate-requests\n"));
+    u->us_clientstate = UPAPCS_BADAUTH;
+    auth_withpeer_fail(u->us_unit, PPP_PAP);
+    return;
+  }
+
+  upap_sauthreq(u);    /* Send Authenticate-Request */
+}
+
+
+/*
+ * upap_reqtimeout - Give up waiting for the peer to send an auth-req.
+ */
+static void
+upap_reqtimeout(void *arg)
+{
+  upap_state *u = (upap_state *) arg;
+
+  if (u->us_serverstate != UPAPSS_LISTEN) {
+    return; /* huh?? */
+  }
+
+  auth_peer_fail(u->us_unit, PPP_PAP);
+  u->us_serverstate = UPAPSS_BADAUTH;
+}
+
+
+/*
+ * upap_lowerup - The lower layer is up.
+ *
+ * Start authenticating if pending.
+ */
+static void
+upap_lowerup(int unit)
+{
+  upap_state *u = &upap[unit];
+
+  UPAPDEBUG((LOG_INFO, "upap_lowerup: %d s=%d\n", unit, u->us_clientstate));
+
+  if (u->us_clientstate == UPAPCS_INITIAL) {
+    u->us_clientstate = UPAPCS_CLOSED;
+  } else if (u->us_clientstate == UPAPCS_PENDING) {
+    upap_sauthreq(u);  /* send an auth-request */
+  }
+
+  if (u->us_serverstate == UPAPSS_INITIAL) {
+    u->us_serverstate = UPAPSS_CLOSED;
+  } else if (u->us_serverstate == UPAPSS_PENDING) {
+    u->us_serverstate = UPAPSS_LISTEN;
+    if (u->us_reqtimeout > 0) {
+      TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout);
+    }
+  }
+}
+
+
+/*
+ * upap_lowerdown - The lower layer is down.
+ *
+ * Cancel all timeouts.
+ */
+static void
+upap_lowerdown(int unit)
+{
+  upap_state *u = &upap[unit];
+
+  UPAPDEBUG((LOG_INFO, "upap_lowerdown: %d s=%d\n", unit, u->us_clientstate));
+
+  if (u->us_clientstate == UPAPCS_AUTHREQ) { /* Timeout pending? */
+    UNTIMEOUT(upap_timeout, u);    /* Cancel timeout */
+  }
+  if (u->us_serverstate == UPAPSS_LISTEN && u->us_reqtimeout > 0) {
+    UNTIMEOUT(upap_reqtimeout, u);
+  }
+
+  u->us_clientstate = UPAPCS_INITIAL;
+  u->us_serverstate = UPAPSS_INITIAL;
+}
+
+
+/*
+ * upap_protrej - Peer doesn't speak this protocol.
+ *
+ * This shouldn't happen.  In any case, pretend lower layer went down.
+ */
+static void
+upap_protrej(int unit)
+{
+  upap_state *u = &upap[unit];
+
+  if (u->us_clientstate == UPAPCS_AUTHREQ) {
+    UPAPDEBUG((LOG_ERR, "PAP authentication failed due to protocol-reject\n"));
+    auth_withpeer_fail(unit, PPP_PAP);
+  }
+  if (u->us_serverstate == UPAPSS_LISTEN) {
+    UPAPDEBUG((LOG_ERR, "PAP authentication of peer failed (protocol-reject)\n"));
+    auth_peer_fail(unit, PPP_PAP);
+  }
+  upap_lowerdown(unit);
+}
+
+
+/*
+ * upap_input - Input UPAP packet.
+ */
+static void
+upap_input(int unit, u_char *inpacket, int l)
+{
+  upap_state *u = &upap[unit];
+  u_char *inp;
+  u_char code, id;
+  int len;
+
+  /*
+   * Parse header (code, id and length).
+   * If packet too short, drop it.
+   */
+  inp = inpacket;
+  if (l < UPAP_HEADERLEN) {
+    UPAPDEBUG((LOG_INFO, "pap_input: rcvd short header.\n"));
+    return;
+  }
+  GETCHAR(code, inp);
+  GETCHAR(id, inp);
+  GETSHORT(len, inp);
+  if (len < UPAP_HEADERLEN) {
+    UPAPDEBUG((LOG_INFO, "pap_input: rcvd illegal length.\n"));
+    return;
+  }
+  if (len > l) {
+    UPAPDEBUG((LOG_INFO, "pap_input: rcvd short packet.\n"));
+    return;
+  }
+  len -= UPAP_HEADERLEN;
+
+  /*
+   * Action depends on code.
+   */
+  switch (code) {
+    case UPAP_AUTHREQ:
+      upap_rauthreq(u, inp, id, len);
+      break;
+
+    case UPAP_AUTHACK:
+      upap_rauthack(u, inp, id, len);
+      break;
+
+    case UPAP_AUTHNAK:
+      upap_rauthnak(u, inp, id, len);
+      break;
+
+    default:        /* XXX Need code reject */
+      break;
+  }
+}
+
+
+/*
+ * upap_rauth - Receive Authenticate.
+ */
+static void
+upap_rauthreq(upap_state *u, u_char *inp, int id, int len)
+{
+  u_char ruserlen, rpasswdlen;
+  char *ruser, *rpasswd;
+  int retcode;
+  char *msg;
+  int msglen;
+
+  UPAPDEBUG((LOG_INFO, "pap_rauth: Rcvd id %d.\n", id));
+
+  if (u->us_serverstate < UPAPSS_LISTEN) {
+    return;
+  }
+
+  /*
+   * If we receive a duplicate authenticate-request, we are
+   * supposed to return the same status as for the first request.
+   */
+  if (u->us_serverstate == UPAPSS_OPEN) {
+    upap_sresp(u, UPAP_AUTHACK, id, "", 0);  /* return auth-ack */
+    return;
+  }
+  if (u->us_serverstate == UPAPSS_BADAUTH) {
+    upap_sresp(u, UPAP_AUTHNAK, id, "", 0);  /* return auth-nak */
+    return;
+  }
+
+  /*
+   * Parse user/passwd.
+   */
+  if (len < sizeof (u_char)) {
+    UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
+    return;
+  }
+  GETCHAR(ruserlen, inp);
+  len -= sizeof (u_char) + ruserlen + sizeof (u_char);
+  if (len < 0) {
+    UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
+    return;
+  }
+  ruser = (char *) inp;
+  INCPTR(ruserlen, inp);
+  GETCHAR(rpasswdlen, inp);
+  if (len < rpasswdlen) {
+    UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
+    return;
+  }
+  rpasswd = (char *) inp;
+
+  /*
+   * Check the username and password given.
+   */
+  retcode = check_passwd(u->us_unit, ruser, ruserlen, rpasswd, rpasswdlen, &msg, &msglen);
+  BZERO(rpasswd, rpasswdlen);
+
+  upap_sresp(u, retcode, id, msg, msglen);
+
+  if (retcode == UPAP_AUTHACK) {
+    u->us_serverstate = UPAPSS_OPEN;
+    auth_peer_success(u->us_unit, PPP_PAP, ruser, ruserlen);
+  } else {
+    u->us_serverstate = UPAPSS_BADAUTH;
+    auth_peer_fail(u->us_unit, PPP_PAP);
+  }
+
+  if (u->us_reqtimeout > 0) {
+    UNTIMEOUT(upap_reqtimeout, u);
+  }
+}
+
+
+/*
+ * upap_rauthack - Receive Authenticate-Ack.
+ */
+static void
+upap_rauthack(upap_state *u, u_char *inp, int id, int len)
+{
+  u_char msglen;
+  char *msg;
+
+  LWIP_UNUSED_ARG(id);
+
+  UPAPDEBUG((LOG_INFO, "pap_rauthack: Rcvd id %d s=%d\n", id, u->us_clientstate));
+
+  if (u->us_clientstate != UPAPCS_AUTHREQ) { /* XXX */
+    return;
+  }
+
+  /*
+   * Parse message.
+   */
+  if (len < sizeof (u_char)) {
+    UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n"));
+    return;
+  }
+  GETCHAR(msglen, inp);
+  len -= sizeof (u_char);
+  if (len < msglen) {
+    UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n"));
+    return;
+  }
+  msg = (char *) inp;
+  PRINTMSG(msg, msglen);
+
+  u->us_clientstate = UPAPCS_OPEN;
+
+  auth_withpeer_success(u->us_unit, PPP_PAP);
+}
+
+
+/*
+ * upap_rauthnak - Receive Authenticate-Nakk.
+ */
+static void
+upap_rauthnak(upap_state *u, u_char *inp, int id, int len)
+{
+  u_char msglen;
+  char *msg;
+
+  LWIP_UNUSED_ARG(id);
+
+  UPAPDEBUG((LOG_INFO, "pap_rauthnak: Rcvd id %d s=%d\n", id, u->us_clientstate));
+
+  if (u->us_clientstate != UPAPCS_AUTHREQ) { /* XXX */
+    return;
+  }
+
+  /*
+   * Parse message.
+   */
+  if (len < sizeof (u_char)) {
+    UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n"));
+    return;
+  }
+  GETCHAR(msglen, inp);
+  len -= sizeof (u_char);
+  if (len < msglen) {
+    UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n"));
+    return;
+  }
+  msg = (char *) inp;
+  PRINTMSG(msg, msglen);
+
+  u->us_clientstate = UPAPCS_BADAUTH;
+
+  UPAPDEBUG((LOG_ERR, "PAP authentication failed\n"));
+  auth_withpeer_fail(u->us_unit, PPP_PAP);
+}
+
+
+/*
+ * upap_sauthreq - Send an Authenticate-Request.
+ */
+static void
+upap_sauthreq(upap_state *u)
+{
+  u_char *outp;
+  int outlen;
+
+  outlen = UPAP_HEADERLEN + 2 * sizeof (u_char) 
+         + u->us_userlen + u->us_passwdlen;
+  outp = outpacket_buf[u->us_unit];
+
+  MAKEHEADER(outp, PPP_PAP);
+
+  PUTCHAR(UPAP_AUTHREQ, outp);
+  PUTCHAR(++u->us_id, outp);
+  PUTSHORT(outlen, outp);
+  PUTCHAR(u->us_userlen, outp);
+  BCOPY(u->us_user, outp, u->us_userlen);
+  INCPTR(u->us_userlen, outp);
+  PUTCHAR(u->us_passwdlen, outp);
+  BCOPY(u->us_passwd, outp, u->us_passwdlen);
+
+  pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN);
+
+  UPAPDEBUG((LOG_INFO, "pap_sauth: Sent id %d\n", u->us_id));
+
+  TIMEOUT(upap_timeout, u, u->us_timeouttime);
+  ++u->us_transmits;
+  u->us_clientstate = UPAPCS_AUTHREQ;
+}
+
+
+/*
+ * upap_sresp - Send a response (ack or nak).
+ */
+static void
+upap_sresp(upap_state *u, u_char code, u_char id, char *msg, int msglen)
+{
+  u_char *outp;
+  int outlen;
+
+  outlen = UPAP_HEADERLEN + sizeof (u_char) + msglen;
+  outp = outpacket_buf[u->us_unit];
+  MAKEHEADER(outp, PPP_PAP);
+
+  PUTCHAR(code, outp);
+  PUTCHAR(id, outp);
+  PUTSHORT(outlen, outp);
+  PUTCHAR(msglen, outp);
+  BCOPY(msg, outp, msglen);
+  pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN);
+
+  UPAPDEBUG((LOG_INFO, "pap_sresp: Sent code %d, id %d s=%d\n", code, id, u->us_clientstate));
+}
+
+#if 0
+/*
+ * upap_printpkt - print the contents of a PAP packet.
+ */
+static int upap_printpkt(
+  u_char *p,
+  int plen,
+  void (*printer) (void *, char *, ...),
+  void *arg
+)
+{
+  LWIP_UNUSED_ARG(p);
+  LWIP_UNUSED_ARG(plen);
+  LWIP_UNUSED_ARG(printer);
+  LWIP_UNUSED_ARG(arg);
+  return 0;
+}
+#endif /* 0 */
+
+#endif /* PAP_SUPPORT */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/pap.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/pap.h
new file mode 100644
index 0000000..fdff86e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/pap.h
@@ -0,0 +1,131 @@
+/*****************************************************************************
+* pap.h -  PPP Password Authentication Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * upap.h - User/Password Authentication Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef PAP_H
+#define PAP_H
+
+#if PAP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+/*
+ * Packet header = Code, id, length.
+ */
+#define UPAP_HEADERLEN (sizeof (u_char) + sizeof (u_char) + sizeof (u_short))
+
+
+/*
+ * UPAP codes.
+ */
+#define UPAP_AUTHREQ 1 /* Authenticate-Request */
+#define UPAP_AUTHACK 2 /* Authenticate-Ack */
+#define UPAP_AUTHNAK 3 /* Authenticate-Nak */
+
+/*
+ * Client states.
+ */
+#define UPAPCS_INITIAL 0 /* Connection down */
+#define UPAPCS_CLOSED  1 /* Connection up, haven't requested auth */
+#define UPAPCS_PENDING 2 /* Connection down, have requested auth */
+#define UPAPCS_AUTHREQ 3 /* We've sent an Authenticate-Request */
+#define UPAPCS_OPEN    4 /* We've received an Ack */
+#define UPAPCS_BADAUTH 5 /* We've received a Nak */
+
+/*
+ * Server states.
+ */
+#define UPAPSS_INITIAL 0 /* Connection down */
+#define UPAPSS_CLOSED  1 /* Connection up, haven't requested auth */
+#define UPAPSS_PENDING 2 /* Connection down, have requested auth */
+#define UPAPSS_LISTEN  3 /* Listening for an Authenticate */
+#define UPAPSS_OPEN    4 /* We've sent an Ack */
+#define UPAPSS_BADAUTH 5 /* We've sent a Nak */
+
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * Each interface is described by upap structure.
+ */
+typedef struct upap_state {
+  int us_unit;           /* Interface unit number */
+  const char *us_user;   /* User */
+  int us_userlen;        /* User length */
+  const char *us_passwd; /* Password */
+  int us_passwdlen;      /* Password length */
+  int us_clientstate;    /* Client state */
+  int us_serverstate;    /* Server state */
+  u_char us_id;          /* Current id */
+  int us_timeouttime;    /* Timeout (seconds) for auth-req retrans. */
+  int us_transmits;      /* Number of auth-reqs sent */
+  int us_maxtransmits;   /* Maximum number of auth-reqs to send */
+  int us_reqtimeout;     /* Time to wait for auth-req from peer */
+} upap_state;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+extern upap_state upap[];
+
+void upap_setloginpasswd(int unit, const char *luser, const char *lpassword);
+void upap_authwithpeer  (int, char *, char *);
+void upap_authpeer      (int);
+
+extern struct protent pap_protent;
+
+#endif /* PAP_SUPPORT */
+
+#endif /* PAP_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/ppp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/ppp.c
new file mode 100644
index 0000000..9267dd2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/ppp.c
@@ -0,0 +1,2003 @@
+/*****************************************************************************
+* ppp.c - Network Point to Point Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*   Original.
+*****************************************************************************/
+
+/*
+ * ppp_defs.h - PPP definitions.
+ *
+ * if_pppvar.h - private structures and declarations for PPP.
+ *
+ * Copyright (c) 1994 The Australian National University.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, provided that the above copyright
+ * notice appears in all copies.  This software is provided without any
+ * warranty, express or implied. The Australian National University
+ * makes no representations about the suitability of this software for
+ * any purpose.
+ *
+ * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY
+ * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
+ * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
+ * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS,
+ * OR MODIFICATIONS.
+ */
+
+/*
+ * if_ppp.h - Point-to-Point Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/ip.h" /* for ip_input() */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "randm.h"
+#include "fsm.h"
+#if PAP_SUPPORT
+#include "pap.h"
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+#include "chap.h"
+#endif /* CHAP_SUPPORT */
+#include "ipcp.h"
+#include "lcp.h"
+#include "magic.h"
+#include "auth.h"
+#if VJ_SUPPORT
+#include "vj.h"
+#endif /* VJ_SUPPORT */
+#if PPPOE_SUPPORT
+#include "netif/ppp_oe.h"
+#endif /* PPPOE_SUPPORT */
+
+#include 
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+/*
+ * The basic PPP frame.
+ */
+#define PPP_ADDRESS(p)  (((u_char *)(p))[0])
+#define PPP_CONTROL(p)  (((u_char *)(p))[1])
+#define PPP_PROTOCOL(p) ((((u_char *)(p))[2] << 8) + ((u_char *)(p))[3])
+
+/* PPP packet parser states.  Current state indicates operation yet to be
+ * completed. */
+typedef enum {
+  PDIDLE = 0,  /* Idle state - waiting. */
+  PDSTART,     /* Process start flag. */
+  PDADDRESS,   /* Process address field. */
+  PDCONTROL,   /* Process control field. */
+  PDPROTOCOL1, /* Process protocol field 1. */
+  PDPROTOCOL2, /* Process protocol field 2. */
+  PDDATA       /* Process data byte. */
+} PPPDevStates;
+
+#define ESCAPE_P(accm, c) ((accm)[(c) >> 3] & pppACCMMask[c & 0x07])
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+/*
+ * PPP interface control block.
+ */
+typedef struct PPPControl_s {
+  char openFlag;                /* True when in use. */
+#if PPPOE_SUPPORT
+  struct netif *ethif;
+  struct pppoe_softc *pppoe_sc;
+#endif /* PPPOE_SUPPORT */
+  int  if_up;                   /* True when the interface is up. */
+  int  errCode;                 /* Code indicating why interface is down. */
+#if PPPOS_SUPPORT
+  sio_fd_t fd;                  /* File device ID of port. */
+  int  kill_link;               /* Shut the link down. */
+  int  sig_hup;                 /* Carrier lost. */
+  struct pbuf *inHead, *inTail; /* The input packet. */
+  PPPDevStates inState;         /* The input process state. */
+  char inEscaped;               /* Escape next character. */
+  u16_t inProtocol;             /* The input protocol code. */
+  u16_t inFCS;                  /* Input Frame Check Sequence value. */
+#endif /* PPPOS_SUPPORT */
+  int  mtu;                     /* Peer's mru */
+  int  pcomp;                   /* Does peer accept protocol compression? */
+  int  accomp;                  /* Does peer accept addr/ctl compression? */
+  u_long lastXMit;              /* Time of last transmission. */
+  ext_accm inACCM;              /* Async-Ctl-Char-Map for input. */
+  ext_accm outACCM;             /* Async-Ctl-Char-Map for output. */
+#if PPPOS_SUPPORT && VJ_SUPPORT
+  int  vjEnabled;               /* Flag indicating VJ compression enabled. */
+  struct vjcompress vjComp;     /* Van Jabobsen compression header. */
+#endif /* PPPOS_SUPPORT && VJ_SUPPORT */
+
+  struct netif netif;
+
+  struct ppp_addrs addrs;
+
+  void (*linkStatusCB)(void *ctx, int errCode, void *arg);
+  void *linkStatusCtx;
+
+} PPPControl;
+
+
+/*
+ * Ioctl definitions.
+ */
+
+struct npioctl {
+  int         protocol; /* PPP procotol, e.g. PPP_IP */
+  enum NPmode mode;
+};
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+#if PPPOS_SUPPORT
+static void pppMain(void *pd);
+static void pppDrop(PPPControl *pc);
+static void pppInProc(int pd, u_char *s, int l);
+#endif /* PPPOS_SUPPORT */
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+u_long subnetMask;
+
+static PPPControl pppControl[NUM_PPP]; /* The PPP interface control blocks. */
+
+/*
+ * PPP Data Link Layer "protocol" table.
+ * One entry per supported protocol.
+ * The last entry must be NULL.
+ */
+struct protent *ppp_protocols[] = {
+  &lcp_protent,
+#if PAP_SUPPORT
+  &pap_protent,
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+  &chap_protent,
+#endif /* CHAP_SUPPORT */
+#if CBCP_SUPPORT
+  &cbcp_protent,
+#endif /* CBCP_SUPPORT */
+  &ipcp_protent,
+#if CCP_SUPPORT
+  &ccp_protent,
+#endif /* CCP_SUPPORT */
+  NULL
+};
+
+
+/*
+ * Buffers for outgoing packets.  This must be accessed only from the appropriate
+ * PPP task so that it doesn't need to be protected to avoid collisions.
+ */
+u_char *outpacket_buf[NUM_PPP];  
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+
+#if PPPOS_SUPPORT
+/*
+ * FCS lookup table as calculated by genfcstab.
+ */
+static const u_short fcstab[256] = {
+  0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
+  0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
+  0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
+  0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
+  0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
+  0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
+  0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
+  0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
+  0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
+  0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
+  0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
+  0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
+  0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
+  0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
+  0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
+  0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
+  0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
+  0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
+  0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
+  0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
+  0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
+  0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
+  0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
+  0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
+  0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
+  0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
+  0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
+  0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
+  0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
+  0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
+  0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
+  0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
+};
+
+/* PPP's Asynchronous-Control-Character-Map.  The mask array is used
+ * to select the specific bit for a character. */
+static u_char pppACCMMask[] = {
+  0x01,
+  0x02,
+  0x04,
+  0x08,
+  0x10,
+  0x20,
+  0x40,
+  0x80
+};
+
+
+void
+pppMainWakeup(int pd)
+{
+  PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d\n", pd));
+  sio_read_abort(pppControl[pd].fd);
+}
+#endif /* PPPOS_SUPPORT */
+
+void
+pppLinkTerminated(int pd)
+{
+  PPPControl *pc = &pppControl[pd];
+
+  PPPDEBUG((LOG_DEBUG, "pppLinkTerminated: unit %d\n", pd));
+
+#if PPPOE_SUPPORT
+  if(pc->ethif) {
+    pppoe_disconnect(pc->pppoe_sc);
+  } else
+#endif /* PPPOE_SUPPORT */
+  {
+#if PPPOS_SUPPORT
+    pppMainWakeup(pd);
+#endif /* PPPOS_SUPPORT */
+  }
+}
+
+void
+pppLinkDown(int pd)
+{
+  PPPControl *pc = &pppControl[pd];
+
+  PPPDEBUG((LOG_DEBUG, "pppLinkDown: unit %d\n", pd));
+
+#if PPPOE_SUPPORT
+  if(pc->ethif) {
+    pppoe_disconnect(pc->pppoe_sc);
+  } else
+#endif /* PPPOE_SUPPORT */
+  {
+#if PPPOS_SUPPORT
+    pppMainWakeup(pd);
+#endif /* PPPOS_SUPPORT */
+  }
+}
+
+/* these callbacks are necessary because lcp_* functions
+   must be called in the same context as pppInput(),
+   namely the tcpip_thread(), essentially because
+   they manipulate timeouts which are thread-private
+*/
+
+static void
+pppStartCB(void *arg)
+{
+  int pd = (int)arg;
+
+  PPPDEBUG((LOG_DEBUG, "pppStartCB: unit %d\n", pd));
+  lcp_lowerup(pd);
+  lcp_open(pd); /* Start protocol */
+}
+
+static void
+pppStopCB(void *arg)
+{
+  int pd = (int)arg;
+
+  PPPDEBUG((LOG_DEBUG, "pppStopCB: unit %d\n", pd));
+  lcp_close(pd, "User request");
+}
+
+static void
+pppHupCB(void *arg)
+{
+  int pd = (int)arg;
+
+  PPPDEBUG((LOG_DEBUG, "pppHupCB: unit %d\n", pd));
+  lcp_lowerdown(pd);
+  link_terminated(pd);
+}
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/* Initialize the PPP subsystem. */
+
+struct ppp_settings ppp_settings;
+
+err_t
+pppInit(void)
+{
+  struct protent *protp;
+  int i, j;
+
+  memset(&ppp_settings, 0, sizeof(ppp_settings));
+  ppp_settings.usepeerdns = 1;
+  pppSetAuth(PPPAUTHTYPE_NONE, NULL, NULL);
+
+  magicInit();
+
+  for (i = 0; i < NUM_PPP; i++) {
+    pppControl[i].openFlag = 0;
+
+    subnetMask = htonl(0xffffff00);
+
+    outpacket_buf[i] = (u_char *)mem_malloc(PPP_MRU+PPP_HDRLEN);
+    if(!outpacket_buf[i]) {
+      return ERR_MEM;
+    }
+
+    /*
+     * Initialize to the standard option set.
+     */
+    for (j = 0; (protp = ppp_protocols[j]) != NULL; ++j) {
+      (*protp->init)(i);
+    }
+  }
+
+#if LINK_STATS
+  /** @todo already done in stats_init (in fact, zeroed at boot). So, remove it? */
+  /* Clear the statistics. */
+  memset(&lwip_stats.link, 0, sizeof(lwip_stats.link));
+#endif /* LINK_STATS */
+
+#if PPPOE_SUPPORT
+  pppoe_init();
+#endif /* PPPOE_SUPPORT */
+
+  return ERR_OK;
+}
+
+void
+pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd)
+{
+  switch(authType) {
+    case PPPAUTHTYPE_NONE:
+    default:
+#ifdef LWIP_PPP_STRICT_PAP_REJECT
+      ppp_settings.refuse_pap = 1;
+#else  /* LWIP_PPP_STRICT_PAP_REJECT */
+      /* some providers request pap and accept an empty login/pw */
+      ppp_settings.refuse_pap = 0;
+#endif /* LWIP_PPP_STRICT_PAP_REJECT */
+      ppp_settings.refuse_chap = 1;
+      break;
+
+    case PPPAUTHTYPE_ANY:
+      /* Warning: Using PPPAUTHTYPE_ANY might have security consequences.
+       * RFC 1994 says:
+       *
+       * In practice, within or associated with each PPP server, there is a
+       * database which associates "user" names with authentication
+       * information ("secrets").  It is not anticipated that a particular
+       * named user would be authenticated by multiple methods.  This would
+       * make the user vulnerable to attacks which negotiate the least secure
+       * method from among a set (such as PAP rather than CHAP).  If the same
+       * secret was used, PAP would reveal the secret to be used later with
+       * CHAP.
+       *
+       * Instead, for each user name there should be an indication of exactly
+       * one method used to authenticate that user name.  If a user needs to
+       * make use of different authentication methods under different
+       * circumstances, then distinct user names SHOULD be employed, each of
+       * which identifies exactly one authentication method.
+       *
+       */
+      ppp_settings.refuse_pap = 0;
+      ppp_settings.refuse_chap = 0;
+      break;
+
+    case PPPAUTHTYPE_PAP:
+      ppp_settings.refuse_pap = 0;
+      ppp_settings.refuse_chap = 1;
+      break;
+
+    case PPPAUTHTYPE_CHAP:
+      ppp_settings.refuse_pap = 1;
+      ppp_settings.refuse_chap = 0;
+      break;
+  }
+
+  if(user) {
+    strncpy(ppp_settings.user, user, sizeof(ppp_settings.user)-1);
+    ppp_settings.user[sizeof(ppp_settings.user)-1] = '\0';
+  } else {
+    ppp_settings.user[0] = '\0';
+  }
+
+  if(passwd) {
+    strncpy(ppp_settings.passwd, passwd, sizeof(ppp_settings.passwd)-1);
+    ppp_settings.passwd[sizeof(ppp_settings.passwd)-1] = '\0';
+  } else {
+    ppp_settings.passwd[0] = '\0';
+  }
+}
+
+#if PPPOS_SUPPORT
+/* Open a new PPP connection using the given I/O device.
+ * This initializes the PPP control block but does not
+ * attempt to negotiate the LCP session.  If this port
+ * connects to a modem, the modem connection must be
+ * established before calling this.
+ * Return a new PPP connection descriptor on success or
+ * an error code (negative) on failure. */
+int
+pppOverSerialOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx)
+{
+  PPPControl *pc;
+  int pd;
+
+  /* Find a free PPP session descriptor. Critical region? */
+  for (pd = 0; pd < NUM_PPP && pppControl[pd].openFlag != 0; pd++);
+
+  if (pd >= NUM_PPP) {
+    pd = PPPERR_OPEN;
+  } else {
+    pppControl[pd].openFlag = !0;
+  }
+
+  /* Launch a deamon thread. */
+  if (pd >= 0) {
+    pppControl[pd].openFlag = 1;
+
+    lcp_init(pd);
+    pc = &pppControl[pd];
+    pc->fd = fd;
+#if PPPOE_SUPPORT
+    pc->ethif= NULL;
+#endif /* PPPOE_SUPPORT */
+    pc->kill_link = 0;
+    pc->sig_hup = 0;
+    pc->if_up = 0;
+    pc->errCode = 0;
+    pc->inState = PDIDLE;
+    pc->inHead = NULL;
+    pc->inTail = NULL;
+    pc->inEscaped = 0;
+    pc->lastXMit = 0;
+
+#if VJ_SUPPORT
+    pc->vjEnabled = 0;
+    vj_compress_init(&pc->vjComp);
+#endif /* VJ_SUPPORT */
+
+    /* 
+     * Default the in and out accm so that escape and flag characters
+     * are always escaped. 
+     */
+    memset(pc->inACCM, 0, sizeof(ext_accm));
+    pc->inACCM[15] = 0x60;
+    memset(pc->outACCM, 0, sizeof(ext_accm));
+    pc->outACCM[15] = 0x60;
+
+    pc->linkStatusCB = linkStatusCB;
+    pc->linkStatusCtx = linkStatusCtx;
+
+    sys_thread_new(PPP_THREAD_NAME, pppMain, (void*)pd, PPP_THREAD_STACKSIZE, PPP_THREAD_PRIO);
+    if(!linkStatusCB) {
+      while(pd >= 0 && !pc->if_up) {
+        sys_msleep(500);
+        if (lcp_phase[pd] == PHASE_DEAD) {
+          pppClose(pd);
+          if (pc->errCode) {
+            pd = pc->errCode;
+          } else {
+            pd = PPPERR_CONNECT;
+          }
+        }
+      }
+    }
+  }
+
+  return pd;
+}
+#endif /* PPPOS_SUPPORT */
+
+#if PPPOE_SUPPORT
+static void pppOverEthernetLinkStatusCB(int pd, int up);
+
+void
+pppOverEthernetClose(int pd)
+{
+  PPPControl* pc = &pppControl[pd];
+
+  /* *TJL* There's no lcp_deinit */
+  lcp_close(pd, NULL);
+
+  pppoe_destroy(&pc->netif);
+}
+
+int pppOverEthernetOpen(struct netif *ethif, const char *service_name, const char *concentrator_name, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx)
+{
+  PPPControl *pc;
+  int pd;
+
+  LWIP_UNUSED_ARG(service_name);
+  LWIP_UNUSED_ARG(concentrator_name);
+
+  /* Find a free PPP session descriptor. Critical region? */
+  for (pd = 0; pd < NUM_PPP && pppControl[pd].openFlag != 0; pd++);
+  if (pd >= NUM_PPP) {
+    pd = PPPERR_OPEN;
+  } else {
+    pppControl[pd].openFlag = !0;
+  }
+
+  /* Launch a deamon thread. */
+  if (pd >= 0) {
+
+    pppControl[pd].openFlag = 1;
+
+    lcp_init(pd);
+
+    lcp_wantoptions[pd].mru = PPPOE_MAXMTU;
+    lcp_wantoptions[pd].neg_asyncmap = 0;
+    lcp_wantoptions[pd].neg_pcompression = 0;
+    lcp_wantoptions[pd].neg_accompression = 0;
+
+    lcp_allowoptions[pd].mru = PPPOE_MAXMTU;
+    lcp_allowoptions[pd].neg_asyncmap = 0;
+    lcp_allowoptions[pd].neg_pcompression = 0;
+    lcp_allowoptions[pd].neg_accompression = 0;
+
+    pc = &pppControl[pd];
+    pc->if_up = 0;
+    pc->errCode = 0;
+    pc->lastXMit = 0;
+#if PPPOS_SUPPORT
+    pc->kill_link = 0;
+    pc->sig_hup = 0;
+    pc->inState = PDIDLE;
+    pc->inHead = NULL;
+    pc->inTail = NULL;
+    pc->inEscaped = 0;
+#if VJ_SUPPORT
+    pc->vjEnabled = 0;
+#endif /* VJ_SUPPORT */
+#endif /* PPPOS_SUPPORT */
+    pc->ethif= ethif;
+
+    memset(pc->inACCM,  0, sizeof(ext_accm));
+    memset(pc->outACCM, 0, sizeof(ext_accm));
+
+    pc->linkStatusCB  = linkStatusCB;
+    pc->linkStatusCtx = linkStatusCtx;
+
+    if(pppoe_create(ethif, pd, pppOverEthernetLinkStatusCB, &pc->pppoe_sc) != ERR_OK) {
+      pc->openFlag = 0;
+      return PPPERR_OPEN;
+    }
+
+    pppoe_connect(pc->pppoe_sc);
+
+    if(!linkStatusCB) {
+      while(pd >= 0 && !pc->if_up) {
+        sys_msleep(500);
+        if (lcp_phase[pd] == PHASE_DEAD) {
+          pppClose(pd);
+          if (pc->errCode) {
+            pd = pc->errCode;
+          } else {
+            pd = PPPERR_CONNECT;
+          }
+        }
+      }
+    }
+  }
+
+  return pd;
+}
+#endif /* PPPOE_SUPPORT */
+
+
+/* Close a PPP connection and release the descriptor. 
+ * Any outstanding packets in the queues are dropped.
+ * Return 0 on success, an error code on failure. */
+int
+pppClose(int pd)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 0;
+
+  /* Disconnect */
+#if PPPOE_SUPPORT
+  if(pc->ethif) {
+    PPPDEBUG((LOG_DEBUG, "pppClose: unit %d kill_link -> pppStopCB\n", pd));
+    pc->errCode = PPPERR_USER;
+    /* This will leave us at PHASE_DEAD. */
+    tcpip_callback(pppStopCB, (void*)pd);
+  } else
+#endif /* PPPOE_SUPPORT */
+  {
+#if PPPOS_SUPPORT
+    pc->kill_link = !0;
+    pppMainWakeup(pd);
+#endif /* PPPOS_SUPPORT */
+  }
+
+  if(!pc->linkStatusCB) {
+    while(st >= 0 && lcp_phase[pd] != PHASE_DEAD) {
+      sys_msleep(500);
+      break;
+    }
+  }
+
+  return st;
+}
+
+/* This function is called when carrier is lost on the PPP channel. */
+void
+pppSigHUP(int pd)
+{
+  PPPControl *pc = &pppControl[pd];
+
+#if PPPOE_SUPPORT
+  if(pc->ethif) {
+    PPPDEBUG((LOG_DEBUG, "pppSigHUP: unit %d sig_hup -> pppHupCB\n", pd));
+    tcpip_callback(pppHupCB, (void*)pd);
+  } else
+#endif /* PPPOE_SUPPORT */
+  {
+#if PPPOS_SUPPORT
+    pc->sig_hup = 1;
+    pppMainWakeup(pd);
+#endif /* PPPOS_SUPPORT */
+  }
+}
+
+#if PPPOS_SUPPORT
+static void
+nPut(PPPControl *pc, struct pbuf *nb)
+{
+  struct pbuf *b;
+  int c;
+
+  for(b = nb; b != NULL; b = b->next) {
+    if((c = sio_write(pc->fd, b->payload, b->len)) != b->len) {
+      PPPDEBUG((LOG_WARNING,
+               "PPP nPut: incomplete sio_write(%d,, %u) = %d\n", pc->fd, b->len, c));
+      LINK_STATS_INC(link.err);
+      pc->lastXMit = 0; /* prepend PPP_FLAG to next packet */
+      break;
+    }
+  }
+
+  pbuf_free(nb);
+  LINK_STATS_INC(link.xmit);
+}
+
+/* 
+ * pppAppend - append given character to end of given pbuf.  If outACCM
+ * is not NULL and the character needs to be escaped, do so.
+ * If pbuf is full, append another.
+ * Return the current pbuf.
+ */
+static struct pbuf *
+pppAppend(u_char c, struct pbuf *nb, ext_accm *outACCM)
+{
+  struct pbuf *tb = nb;
+  
+  /* Make sure there is room for the character and an escape code.
+   * Sure we don't quite fill the buffer if the character doesn't
+   * get escaped but is one character worth complicating this? */
+  /* Note: We assume no packet header. */
+  if (nb && (PBUF_POOL_BUFSIZE - nb->len) < 2) {
+    tb = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+    if (tb) {
+      nb->next = tb;
+    } else {
+      LINK_STATS_INC(link.memerr);
+    }
+    nb = tb;
+  }
+
+  if (nb) {
+    if (outACCM && ESCAPE_P(*outACCM, c)) {
+      *((u_char*)nb->payload + nb->len++) = PPP_ESCAPE;
+      *((u_char*)nb->payload + nb->len++) = c ^ PPP_TRANS;
+    } else {
+      *((u_char*)nb->payload + nb->len++) = c;
+    }
+  }
+
+  return tb;
+}
+#endif /* PPPOS_SUPPORT */
+
+#if PPPOE_SUPPORT
+static err_t
+pppifOutputOverEthernet(int pd, struct pbuf *p)
+{
+  PPPControl *pc = &pppControl[pd];
+  struct pbuf *pb;
+  u_short protocol = PPP_IP;
+  int i=0;
+
+  pb = pbuf_alloc(PBUF_LINK, pppoe_hdrlen + sizeof(protocol), PBUF_RAM);
+  if(!pb) {
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.proterr);
+    return ERR_MEM;
+  }
+
+  pbuf_header(pb, -pppoe_hdrlen);
+
+  pc->lastXMit = sys_jiffies();
+
+  if (!pc->pcomp || protocol > 0xFF) {
+    *((u_char*)pb->payload + i++) = (protocol >> 8) & 0xFF;
+  }
+  *((u_char*)pb->payload + i) = protocol & 0xFF;
+
+  pbuf_chain(pb, p);
+
+  if(pppoe_xmit(pc->pppoe_sc, pb) != ERR_OK) {
+    LINK_STATS_INC(link.err);
+    return PPPERR_DEVICE;
+  }
+
+  LINK_STATS_INC(link.xmit);
+  return ERR_OK;
+}
+#endif /* PPPOE_SUPPORT */
+
+/* Send a packet on the given connection. */
+static err_t
+pppifOutput(struct netif *netif, struct pbuf *pb, struct ip_addr *ipaddr)
+{
+  int pd = (int)netif->state;
+  u_short protocol = PPP_IP;
+  PPPControl *pc = &pppControl[pd];
+#if PPPOS_SUPPORT
+  u_int fcsOut = PPP_INITFCS;
+  struct pbuf *headMB = NULL, *tailMB = NULL, *p;
+  u_char c;
+#endif /* PPPOS_SUPPORT */
+
+  LWIP_UNUSED_ARG(ipaddr);
+
+  /* Validate parameters. */
+  /* We let any protocol value go through - it can't hurt us
+   * and the peer will just drop it if it's not accepting it. */
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag || !pb) {
+    PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad parms prot=%d pb=%p\n",
+              pd, protocol, pb));
+    LINK_STATS_INC(link.opterr);
+    LINK_STATS_INC(link.drop);
+    return ERR_ARG;
+  }
+
+  /* Check that the link is up. */
+  if (lcp_phase[pd] == PHASE_DEAD) {
+    PPPDEBUG((LOG_ERR, "pppifOutput[%d]: link not up\n", pd));
+    LINK_STATS_INC(link.rterr);
+    LINK_STATS_INC(link.drop);
+    return ERR_RTE;
+  }
+
+#if PPPOE_SUPPORT
+  if(pc->ethif) {
+    return pppifOutputOverEthernet(pd, pb);
+  }
+#endif /* PPPOE_SUPPORT */
+
+#if PPPOS_SUPPORT
+  /* Grab an output buffer. */
+  headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+  if (headMB == NULL) {
+    PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: first alloc fail\n", pd));
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.drop);
+    return ERR_MEM;
+  }
+
+#if VJ_SUPPORT
+  /* 
+   * Attempt Van Jacobson header compression if VJ is configured and
+   * this is an IP packet. 
+   */
+  if (protocol == PPP_IP && pc->vjEnabled) {
+    switch (vj_compress_tcp(&pc->vjComp, pb)) {
+      case TYPE_IP:
+        /* No change...
+           protocol = PPP_IP_PROTOCOL; */
+        break;
+      case TYPE_COMPRESSED_TCP:
+        protocol = PPP_VJC_COMP;
+        break;
+      case TYPE_UNCOMPRESSED_TCP:
+        protocol = PPP_VJC_UNCOMP;
+        break;
+      default:
+        PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad IP packet\n", pd));
+        LINK_STATS_INC(link.proterr);
+        LINK_STATS_INC(link.drop);
+        pbuf_free(headMB);
+        return ERR_VAL;
+    }
+  }
+#endif /* VJ_SUPPORT */
+
+  tailMB = headMB;
+
+  /* Build the PPP header. */
+  if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG) {
+    tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+  }
+
+  pc->lastXMit = sys_jiffies();
+  if (!pc->accomp) {
+    fcsOut = PPP_FCS(fcsOut, PPP_ALLSTATIONS);
+    tailMB = pppAppend(PPP_ALLSTATIONS, tailMB, &pc->outACCM);
+    fcsOut = PPP_FCS(fcsOut, PPP_UI);
+    tailMB = pppAppend(PPP_UI, tailMB, &pc->outACCM);
+  }
+  if (!pc->pcomp || protocol > 0xFF) {
+    c = (protocol >> 8) & 0xFF;
+    fcsOut = PPP_FCS(fcsOut, c);
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+  }
+  c = protocol & 0xFF;
+  fcsOut = PPP_FCS(fcsOut, c);
+  tailMB = pppAppend(c, tailMB, &pc->outACCM);
+
+  /* Load packet. */
+  for(p = pb; p; p = p->next) {
+    int n;
+    u_char *sPtr;
+
+    sPtr = (u_char*)p->payload;
+    n = p->len;
+    while (n-- > 0) {
+      c = *sPtr++;
+
+      /* Update FCS before checking for special characters. */
+      fcsOut = PPP_FCS(fcsOut, c);
+      
+      /* Copy to output buffer escaping special characters. */
+      tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    }
+  }
+
+  /* Add FCS and trailing flag. */
+  c = ~fcsOut & 0xFF;
+  tailMB = pppAppend(c, tailMB, &pc->outACCM);
+  c = (~fcsOut >> 8) & 0xFF;
+  tailMB = pppAppend(c, tailMB, &pc->outACCM);
+  tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+
+  /* If we failed to complete the packet, throw it away. */
+  if (!tailMB) {
+    PPPDEBUG((LOG_WARNING,
+             "pppifOutput[%d]: Alloc err - dropping proto=%d\n", 
+              pd, protocol));
+    pbuf_free(headMB);
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.drop);
+    return ERR_MEM;
+  }
+
+  /* Send it. */
+  PPPDEBUG((LOG_INFO, "pppifOutput[%d]: proto=0x%04X\n", pd, protocol));
+
+  nPut(pc, headMB);
+#endif /* PPPOS_SUPPORT */
+
+  return ERR_OK;
+}
+
+/* Get and set parameters for the given connection.
+ * Return 0 on success, an error code on failure. */
+int
+pppIOCtl(int pd, int cmd, void *arg)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 0;
+
+  if (pd < 0 || pd >= NUM_PPP) {
+    st = PPPERR_PARAM;
+  } else {
+    switch(cmd) {
+    case PPPCTLG_UPSTATUS:      /* Get the PPP up status. */
+      if (arg) {
+        *(int *)arg = (int)(pc->if_up);
+      } else {
+        st = PPPERR_PARAM;
+      }
+      break;
+    case PPPCTLS_ERRCODE:       /* Set the PPP error code. */
+      if (arg) {
+        pc->errCode = *(int *)arg;
+      } else {
+        st = PPPERR_PARAM;
+      }
+      break;
+    case PPPCTLG_ERRCODE:       /* Get the PPP error code. */
+      if (arg) {
+        *(int *)arg = (int)(pc->errCode);
+      } else {
+        st = PPPERR_PARAM;
+      }
+      break;
+#if PPPOS_SUPPORT
+    case PPPCTLG_FD:
+      if (arg) {
+        *(sio_fd_t *)arg = pc->fd;
+      } else {
+        st = PPPERR_PARAM;
+      }
+      break;
+#endif /* PPPOS_SUPPORT */
+    default:
+      st = PPPERR_PARAM;
+      break;
+    }
+  }
+
+  return st;
+}
+
+/*
+ * Return the Maximum Transmission Unit for the given PPP connection.
+ */
+u_int
+pppMTU(int pd)
+{
+  PPPControl *pc = &pppControl[pd];
+  u_int st;
+
+  /* Validate parameters. */
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+    st = 0;
+  } else {
+    st = pc->mtu;
+  }
+
+  return st;
+}
+
+#if PPPOE_SUPPORT
+int
+pppWriteOverEthernet(int pd, const u_char *s, int n)
+{
+  PPPControl *pc = &pppControl[pd];
+  struct pbuf *pb;
+
+  /* skip address & flags */
+  s += 2;
+  n -= 2;
+
+  pb = pbuf_alloc(PBUF_LINK, pppoe_hdrlen + n, PBUF_RAM);
+  if(!pb) {
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.proterr);
+    return PPPERR_ALLOC;
+  }
+
+  pbuf_header(pb, -pppoe_hdrlen);
+
+  pc->lastXMit = sys_jiffies();
+
+  SMEMCPY(pb->payload, s, n);
+
+  if(pppoe_xmit(pc->pppoe_sc, pb) != ERR_OK) {
+    LINK_STATS_INC(link.err);
+    return PPPERR_DEVICE;
+  }
+
+  LINK_STATS_INC(link.xmit);
+  return PPPERR_NONE;
+}
+#endif /* PPPOE_SUPPORT */
+
+/*
+ * Write n characters to a ppp link.
+ *  RETURN: >= 0 Number of characters written
+ *           -1 Failed to write to device
+ */
+int
+pppWrite(int pd, const u_char *s, int n)
+{
+  PPPControl *pc = &pppControl[pd];
+#if PPPOS_SUPPORT
+  u_char c;
+  u_int fcsOut;
+  struct pbuf *headMB, *tailMB;
+#endif /* PPPOS_SUPPORT */
+
+#if PPPOE_SUPPORT
+  if(pc->ethif) {
+    return pppWriteOverEthernet(pd, s, n);
+  }
+#endif /* PPPOE_SUPPORT */
+
+#if PPPOS_SUPPORT
+  headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+  if (headMB == NULL) {
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.proterr);
+    return PPPERR_ALLOC;
+  }
+
+  tailMB = headMB;
+
+  /* If the link has been idle, we'll send a fresh flag character to
+   * flush any noise. */
+  if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG) {
+    tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+  }
+  pc->lastXMit = sys_jiffies();
+
+  fcsOut = PPP_INITFCS;
+  /* Load output buffer. */
+  while (n-- > 0) {
+    c = *s++;
+
+    /* Update FCS before checking for special characters. */
+    fcsOut = PPP_FCS(fcsOut, c);
+
+    /* Copy to output buffer escaping special characters. */
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+  }
+    
+  /* Add FCS and trailing flag. */
+  c = ~fcsOut & 0xFF;
+  tailMB = pppAppend(c, tailMB, &pc->outACCM);
+  c = (~fcsOut >> 8) & 0xFF;
+  tailMB = pppAppend(c, tailMB, &pc->outACCM);
+  tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+
+  /* If we failed to complete the packet, throw it away.
+   * Otherwise send it. */
+  if (!tailMB) {
+    PPPDEBUG((LOG_WARNING,
+             "pppWrite[%d]: Alloc err - dropping pbuf len=%d\n", pd, headMB->len));
+           /*"pppWrite[%d]: Alloc err - dropping %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */
+    pbuf_free(headMB);
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.proterr);
+    return PPPERR_ALLOC;
+  }
+
+  PPPDEBUG((LOG_INFO, "pppWrite[%d]: len=%d\n", pd, headMB->len));
+                   /* "pppWrite[%d]: %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */
+  nPut(pc, headMB);
+#endif /* PPPOS_SUPPORT */
+
+  return PPPERR_NONE;
+}
+
+/*
+ * ppp_send_config - configure the transmit characteristics of
+ * the ppp interface.
+ */
+void
+ppp_send_config( int unit, int mtu, u32_t asyncmap, int pcomp, int accomp)
+{
+  PPPControl *pc = &pppControl[unit];
+  int i;
+  
+  pc->mtu = mtu;
+  pc->pcomp = pcomp;
+  pc->accomp = accomp;
+  
+  /* Load the ACCM bits for the 32 control codes. */
+  for (i = 0; i < 32/8; i++) {
+    pc->outACCM[i] = (u_char)((asyncmap >> (8 * i)) & 0xFF);
+  }
+  PPPDEBUG((LOG_INFO, "ppp_send_config[%d]: outACCM=%X %X %X %X\n",
+            unit,
+            pc->outACCM[0], pc->outACCM[1], pc->outACCM[2], pc->outACCM[3]));
+}
+
+
+/*
+ * ppp_set_xaccm - set the extended transmit ACCM for the interface.
+ */
+void
+ppp_set_xaccm(int unit, ext_accm *accm)
+{
+  SMEMCPY(pppControl[unit].outACCM, accm, sizeof(ext_accm));
+  PPPDEBUG((LOG_INFO, "ppp_set_xaccm[%d]: outACCM=%X %X %X %X\n",
+            unit,
+            pppControl[unit].outACCM[0],
+            pppControl[unit].outACCM[1],
+            pppControl[unit].outACCM[2],
+            pppControl[unit].outACCM[3]));
+}
+
+
+/*
+ * ppp_recv_config - configure the receive-side characteristics of
+ * the ppp interface.
+ */
+void
+ppp_recv_config( int unit, int mru, u32_t asyncmap, int pcomp, int accomp)
+{
+  PPPControl *pc = &pppControl[unit];
+  int i;
+
+  LWIP_UNUSED_ARG(accomp);
+  LWIP_UNUSED_ARG(pcomp);
+  LWIP_UNUSED_ARG(mru);
+
+  /* Load the ACCM bits for the 32 control codes. */
+  for (i = 0; i < 32 / 8; i++) {
+    pc->inACCM[i] = (u_char)(asyncmap >> (i * 8));
+  }
+  PPPDEBUG((LOG_INFO, "ppp_recv_config[%d]: inACCM=%X %X %X %X\n",
+            unit,
+            pc->inACCM[0], pc->inACCM[1], pc->inACCM[2], pc->inACCM[3]));
+}
+
+#if 0
+/*
+ * ccp_test - ask kernel whether a given compression method
+ * is acceptable for use.  Returns 1 if the method and parameters
+ * are OK, 0 if the method is known but the parameters are not OK
+ * (e.g. code size should be reduced), or -1 if the method is unknown.
+ */
+int
+ccp_test( int unit, int opt_len,  int for_transmit, u_char *opt_ptr)
+{
+  return 0; /* XXX Currently no compression. */
+}
+
+/*
+ * ccp_flags_set - inform kernel about the current state of CCP.
+ */
+void
+ccp_flags_set(int unit, int isopen, int isup)
+{
+  /* XXX */
+}
+
+/*
+ * ccp_fatal_error - returns 1 if decompression was disabled as a
+ * result of an error detected after decompression of a packet,
+ * 0 otherwise.  This is necessary because of patent nonsense.
+ */
+int
+ccp_fatal_error(int unit)
+{
+  /* XXX */
+  return 0;
+}
+#endif
+
+/*
+ * get_idle_time - return how long the link has been idle.
+ */
+int
+get_idle_time(int u, struct ppp_idle *ip)
+{
+  /* XXX */
+  LWIP_UNUSED_ARG(u);
+  LWIP_UNUSED_ARG(ip);
+
+  return 0;
+}
+
+
+/*
+ * Return user specified netmask, modified by any mask we might determine
+ * for address `addr' (in network byte order).
+ * Here we scan through the system's list of interfaces, looking for
+ * any non-point-to-point interfaces which might appear to be on the same
+ * network as `addr'.  If we find any, we OR in their netmask to the
+ * user-specified netmask.
+ */
+u32_t
+GetMask(u32_t addr)
+{
+  u32_t mask, nmask;
+
+  htonl(addr);
+  if (IN_CLASSA(addr)) { /* determine network mask for address class */
+    nmask = IN_CLASSA_NET;
+  } else if (IN_CLASSB(addr)) {
+    nmask = IN_CLASSB_NET;
+  } else { 
+    nmask = IN_CLASSC_NET;
+  }
+
+  /* class D nets are disallowed by bad_ip_adrs */
+  mask = subnetMask | htonl(nmask);
+  
+  /* XXX
+   * Scan through the system's network interfaces.
+   * Get each netmask and OR them into our mask.
+   */
+
+  return mask;
+}
+
+/*
+ * sifvjcomp - config tcp header compression
+ */
+int
+sifvjcomp( int pd, int vjcomp, int cidcomp, int maxcid)
+{
+#if PPPOS_SUPPORT && VJ_SUPPORT
+  PPPControl *pc = &pppControl[pd];
+  
+  pc->vjEnabled = vjcomp;
+  pc->vjComp.compressSlot = cidcomp;
+  pc->vjComp.maxSlotIndex = maxcid;
+  PPPDEBUG((LOG_INFO, "sifvjcomp: VJ compress enable=%d slot=%d max slot=%d\n",
+            vjcomp, cidcomp, maxcid));
+#endif /* PPPOS_SUPPORT && VJ_SUPPORT */
+
+  return 0;
+}
+
+/*
+ * pppifNetifInit - netif init callback
+ */
+static err_t
+pppifNetifInit(struct netif *netif)
+{
+  netif->name[0] = 'p';
+  netif->name[1] = 'p';
+  netif->output = pppifOutput;
+  netif->mtu = pppMTU((int)netif->state);
+  return ERR_OK;
+}
+
+
+/*
+ * sifup - Config the interface up and enable IP packets to pass.
+ */
+int
+sifup(int pd)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 1;
+  
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+    st = 0;
+    PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+  } else {
+    netif_remove(&pc->netif);
+    if (netif_add(&pc->netif, &pc->addrs.our_ipaddr, &pc->addrs.netmask, &pc->addrs.his_ipaddr, (void *)pd, pppifNetifInit, ip_input)) {
+      netif_set_up(&pc->netif);
+#if LWIP_DHCP
+      /* ugly workaround for storing a reference to the ppp related info*/
+      pc->netif.dhcp = (struct dhcp *) &pc->addrs;
+#endif /* LWIP_DHCP */
+      pc->if_up = 1;
+      pc->errCode = PPPERR_NONE;
+
+      PPPDEBUG((LOG_DEBUG, "sifup: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+      if(pc->linkStatusCB) {
+        pc->linkStatusCB(pc->linkStatusCtx, pc->errCode, &pc->addrs);
+      }
+    } else {
+      st = 0;
+      PPPDEBUG((LOG_ERR, "sifup[%d]: netif_add failed\n", pd));
+    }
+  }
+
+  return st;
+}
+
+/*
+ * sifnpmode - Set the mode for handling packets for a given NP.
+ */
+int
+sifnpmode(int u, int proto, enum NPmode mode)
+{
+  LWIP_UNUSED_ARG(u);
+  LWIP_UNUSED_ARG(proto);
+  LWIP_UNUSED_ARG(mode);
+  return 0;
+}
+
+/*
+ * sifdown - Config the interface down and disable IP.
+ */
+int
+sifdown(int pd)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 1;
+  
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+    st = 0;
+    PPPDEBUG((LOG_WARNING, "sifdown[%d]: bad parms\n", pd));
+  } else {
+    pc->if_up = 0;
+    netif_remove(&pc->netif);
+    PPPDEBUG((LOG_DEBUG, "sifdown: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+    if(pc->linkStatusCB) {
+      pc->linkStatusCB(pc->linkStatusCtx, PPPERR_CONNECT, NULL);
+    }
+  }
+  return st;
+}
+
+/**
+ * sifaddr - Config the interface IP addresses and netmask.
+ * @param pd Interface unit ???
+ * @param o Our IP address ???
+ * @param h His IP address ???
+ * @param m IP subnet mask ???
+ * @param ns1 Primary DNS
+ * @param ns2 Secondary DNS
+ */
+int
+sifaddr( int pd, u32_t o, u32_t h, u32_t m, u32_t ns1, u32_t ns2)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 1;
+  
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+    st = 0;
+    PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+  } else {
+    SMEMCPY(&pc->addrs.our_ipaddr, &o, sizeof(o));
+    SMEMCPY(&pc->addrs.his_ipaddr, &h, sizeof(h));
+    SMEMCPY(&pc->addrs.netmask, &m, sizeof(m));
+    SMEMCPY(&pc->addrs.dns1, &ns1, sizeof(ns1));
+    SMEMCPY(&pc->addrs.dns2, &ns2, sizeof(ns2));
+  }
+  return st;
+}
+
+/**
+ * cifaddr - Clear the interface IP addresses, and delete routes
+ * through the interface if possible.
+ * @param pd Interface unit ???
+ * @param o Our IP address ???
+ * @param h IP broadcast address ???
+ */
+int
+cifaddr( int pd, u32_t o, u32_t h)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 1;
+  
+  LWIP_UNUSED_ARG(o);
+  LWIP_UNUSED_ARG(h);
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+    st = 0;
+    PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+  } else {
+    IP4_ADDR(&pc->addrs.our_ipaddr, 0,0,0,0);
+    IP4_ADDR(&pc->addrs.his_ipaddr, 0,0,0,0);
+    IP4_ADDR(&pc->addrs.netmask, 255,255,255,0);
+    IP4_ADDR(&pc->addrs.dns1, 0,0,0,0);
+    IP4_ADDR(&pc->addrs.dns2, 0,0,0,0);
+  }
+  return st;
+}
+
+/*
+ * sifdefaultroute - assign a default route through the address given.
+ */
+int
+sifdefaultroute(int pd, u32_t l, u32_t g)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 1;
+
+  LWIP_UNUSED_ARG(l);
+  LWIP_UNUSED_ARG(g);
+
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+    st = 0;
+    PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+  } else {
+    netif_set_default(&pc->netif);
+  }
+
+  /* TODO: check how PPP handled the netMask, previously not set by ipSetDefault */
+
+  return st;
+}
+
+/*
+ * cifdefaultroute - delete a default route through the address given.
+ */
+int
+cifdefaultroute(int pd, u32_t l, u32_t g)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 1;
+
+  LWIP_UNUSED_ARG(l);
+  LWIP_UNUSED_ARG(g);
+
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+    st = 0;
+    PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+  } else {
+    netif_set_default(NULL);
+  }
+
+  return st;
+}
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+
+#if PPPOS_SUPPORT
+/* The main PPP process function.  This implements the state machine according
+ * to section 4 of RFC 1661: The Point-To-Point Protocol. */
+static void
+pppMain(void *arg)
+{
+  int pd = (int)arg;
+  struct pbuf *p;
+  PPPControl* pc;
+  int c;
+
+  pc = &pppControl[pd];
+
+  p = pbuf_alloc(PBUF_RAW, PPP_MRU+PPP_HDRLEN, PBUF_RAM);
+  if (!p) {
+    LWIP_ASSERT("p != NULL", p);
+    pc->errCode = PPPERR_ALLOC;
+    goto out;
+  }
+
+  /*
+   * Start the connection and handle incoming events (packet or timeout).
+   */
+  PPPDEBUG((LOG_INFO, "pppMain: unit %d: Connecting\n", pd));
+  tcpip_callback(pppStartCB, arg);
+  while (lcp_phase[pd] != PHASE_DEAD) {
+    if (pc->kill_link) {
+      PPPDEBUG((LOG_DEBUG, "pppMain: unit %d kill_link -> pppStopCB\n", pd));
+      pc->errCode = PPPERR_USER;
+      /* This will leave us at PHASE_DEAD. */
+      tcpip_callback(pppStopCB, arg);
+      pc->kill_link = 0;
+    } else if (pc->sig_hup) {
+      PPPDEBUG((LOG_DEBUG, "pppMain: unit %d sig_hup -> pppHupCB\n", pd));
+      pc->sig_hup = 0;
+      tcpip_callback(pppHupCB, arg);
+    } else {
+      c = sio_read(pc->fd, p->payload, p->len);
+      if(c > 0) {
+        pppInProc(pd, p->payload, c);
+      } else {
+        PPPDEBUG((LOG_DEBUG, "pppMain: unit %d sio_read len=%d returned %d\n", pd, p->len, c));
+        sys_msleep(1); /* give other tasks a chance to run */
+      }
+    }
+  }
+  PPPDEBUG((LOG_INFO, "pppMain: unit %d: PHASE_DEAD\n", pd));
+  pppDrop(pc); /* bug fix #17726 */
+  pbuf_free(p);
+
+out:
+  PPPDEBUG((LOG_DEBUG, "pppMain: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+  if(pc->linkStatusCB) {
+    pc->linkStatusCB(pc->linkStatusCtx, pc->errCode ? pc->errCode : PPPERR_PROTOCOL, NULL);
+  }
+
+  pc->openFlag = 0;
+}
+#endif /* PPPOS_SUPPORT */
+
+#if PPPOE_SUPPORT
+
+void
+pppOverEthernetInitFailed(void* arg)
+{
+  PPPControl* pc;
+  int pd = (int)arg;
+
+  pppHupCB(arg);
+  pppStopCB(arg);
+
+  pc = &pppControl[pd];
+  pppoe_destroy(&pc->netif);
+  pc->openFlag = 0;
+
+  if(pc->linkStatusCB) {
+    pc->linkStatusCB(pc->linkStatusCtx, pc->errCode ? pc->errCode : PPPERR_PROTOCOL, NULL);
+  }
+}
+
+static void
+pppOverEthernetLinkStatusCB(int pd, int up)
+{
+  if(up) {
+    PPPDEBUG((LOG_INFO, "pppMain: unit %d: Connecting\n", pd));
+    tcpip_callback(pppStartCB, (void*)pd);
+  } else {
+    PPPControl* pc;
+    pc = &pppControl[pd];
+    tcpip_callback(pppOverEthernetInitFailed, (void*)pd);
+  }
+}
+#endif /* PPPOE_SUPPORT */
+
+struct pbuf *
+pppSingleBuf(struct pbuf *p)
+{
+  struct pbuf *q, *b;
+  u_char *pl;
+
+  if(p->tot_len == p->len) {
+    return p;
+  }
+
+  q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
+  if(!q) {
+    PPPDEBUG((LOG_ERR,
+             "pppSingleBuf: unable to alloc new buf (%d)\n", p->tot_len));
+    return p; /* live dangerously */
+  }
+
+  for(b = p, pl = q->payload; b != NULL; b = b->next) {
+    MEMCPY(pl, b->payload, b->len);
+    pl += b->len;
+  }
+
+  pbuf_free(p);
+
+  return q;
+}
+
+struct pppInputHeader {
+  int unit;
+  u16_t proto;
+};
+
+/*
+ * Pass the processed input packet to the appropriate handler.
+ * This function and all handlers run in the context of the tcpip_thread
+ */
+static void
+pppInput(void *arg)
+{
+  struct pbuf *nb = (struct pbuf *)arg;
+  u16_t protocol;
+  int pd;
+
+  pd = ((struct pppInputHeader *)nb->payload)->unit;
+  protocol = ((struct pppInputHeader *)nb->payload)->proto;
+    
+  if(pbuf_header(nb, -(int)sizeof(struct pppInputHeader))) {
+    LWIP_ASSERT("pbuf_header failed\n", 0);
+    goto drop;
+  }
+
+  LINK_STATS_INC(link.recv);
+
+  /*
+   * Toss all non-LCP packets unless LCP is OPEN.
+   * Until we get past the authentication phase, toss all packets
+   * except LCP, LQR and authentication packets.
+   */
+  if((lcp_phase[pd] <= PHASE_AUTHENTICATE) && (protocol != PPP_LCP)) {
+    if(!((protocol == PPP_LQR) || (protocol == PPP_PAP) || (protocol == PPP_CHAP)) ||
+        (lcp_phase[pd] != PHASE_AUTHENTICATE)) {
+      PPPDEBUG((LOG_INFO, "pppInput: discarding proto 0x%04X in phase %d\n", protocol, lcp_phase[pd]));
+      goto drop;
+    }
+  }
+
+  switch(protocol) {
+    case PPP_VJC_COMP:      /* VJ compressed TCP */
+#if VJ_SUPPORT
+      PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_comp in pbuf len=%d\n", pd, nb->len));
+      /*
+       * Clip off the VJ header and prepend the rebuilt TCP/IP header and
+       * pass the result to IP.
+       */
+      if ((vj_uncompress_tcp(&nb, &pppControl[pd].vjComp) >= 0) && (pppControl[pd].netif.input)) {
+        pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+        return;
+      }
+      /* Something's wrong so drop it. */
+      PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ compressed\n", pd));
+#else  /* VJ_SUPPORT */
+      /* No handler for this protocol so drop the packet. */
+      PPPDEBUG((LOG_INFO, "pppInput[%d]: drop VJ Comp in %d:%s\n", pd, nb->len, nb->payload));
+#endif /* VJ_SUPPORT */
+      break;
+
+    case PPP_VJC_UNCOMP:    /* VJ uncompressed TCP */
+#if VJ_SUPPORT
+      PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_un in pbuf len=%d\n", pd, nb->len));
+      /*
+       * Process the TCP/IP header for VJ header compression and then pass
+       * the packet to IP.
+       */
+      if ((vj_uncompress_uncomp(nb, &pppControl[pd].vjComp) >= 0) && pppControl[pd].netif.input) {
+        pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+        return;
+      }
+      /* Something's wrong so drop it. */
+      PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ uncompressed\n", pd));
+#else  /* VJ_SUPPORT */
+      /* No handler for this protocol so drop the packet. */
+      PPPDEBUG((LOG_INFO,
+               "pppInput[%d]: drop VJ UnComp in %d:.*H\n", 
+                pd, nb->len, LWIP_MIN(nb->len * 2, 40), nb->payload));
+#endif /* VJ_SUPPORT */
+      break;
+
+    case PPP_IP:            /* Internet Protocol */
+      PPPDEBUG((LOG_INFO, "pppInput[%d]: ip in pbuf len=%d\n", pd, nb->len));
+      if (pppControl[pd].netif.input) {
+        pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+        return;
+      }
+      break;
+
+    default: {
+      struct protent *protp;
+      int i;
+
+      /*
+       * Upcall the proper protocol input routine.
+       */
+      for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+        if (protp->protocol == protocol && protp->enabled_flag) {
+          PPPDEBUG((LOG_INFO, "pppInput[%d]: %s len=%d\n", pd, protp->name, nb->len));
+          nb = pppSingleBuf(nb);
+          (*protp->input)(pd, nb->payload, nb->len);
+          goto out;
+        }
+      }
+
+      /* No handler for this protocol so reject the packet. */
+      PPPDEBUG((LOG_INFO, "pppInput[%d]: rejecting unsupported proto 0x%04X len=%d\n", pd, protocol, nb->len));
+      if (pbuf_header(nb, sizeof(protocol))) {
+        LWIP_ASSERT("pbuf_header failed\n", 0);
+        goto drop;
+      }
+#if BYTE_ORDER == LITTLE_ENDIAN
+      protocol = htons(protocol);
+      SMEMCPY(nb->payload, &protocol, sizeof(protocol));
+#endif /* BYTE_ORDER == LITTLE_ENDIAN */
+      lcp_sprotrej(pd, nb->payload, nb->len);
+    }
+    break;
+  }
+
+drop:
+  LINK_STATS_INC(link.drop);
+
+out:
+  pbuf_free(nb);
+  return;
+}
+
+#if PPPOS_SUPPORT
+/*
+ * Drop the input packet.
+ */
+static void
+pppDrop(PPPControl *pc)
+{
+  if (pc->inHead != NULL) {
+#if 0
+    PPPDEBUG((LOG_INFO, "pppDrop: %d:%.*H\n", pc->inHead->len, min(60, pc->inHead->len * 2), pc->inHead->payload));
+#endif
+    PPPDEBUG((LOG_INFO, "pppDrop: pbuf len=%d\n", pc->inHead->len));
+    if (pc->inTail && (pc->inTail != pc->inHead)) {
+      pbuf_free(pc->inTail);
+    }
+    pbuf_free(pc->inHead);
+    pc->inHead = NULL;
+    pc->inTail = NULL;
+  }
+#if VJ_SUPPORT
+  vj_uncompress_err(&pc->vjComp);
+#endif /* VJ_SUPPORT */
+
+  LINK_STATS_INC(link.drop);
+}
+
+/**
+ * Process a received octet string.
+ */
+static void
+pppInProc(int pd, u_char *s, int l)
+{
+  PPPControl *pc = &pppControl[pd];
+  struct pbuf *nextNBuf;
+  u_char curChar;
+
+  PPPDEBUG((LOG_DEBUG, "pppInProc[%d]: got %d bytes\n", pd, l));
+  while (l-- > 0) {
+    curChar = *s++;
+    
+    /* Handle special characters. */
+    if (ESCAPE_P(pc->inACCM, curChar)) {
+      /* Check for escape sequences. */
+      /* XXX Note that this does not handle an escaped 0x5d character which
+       * would appear as an escape character.  Since this is an ASCII ']'
+       * and there is no reason that I know of to escape it, I won't complicate
+       * the code to handle this case. GLL */
+      if (curChar == PPP_ESCAPE) {
+        pc->inEscaped = 1;
+      /* Check for the flag character. */
+      } else if (curChar == PPP_FLAG) {
+         /* If this is just an extra flag character, ignore it. */
+         if (pc->inState <= PDADDRESS) {
+           /* ignore it */;
+         /* If we haven't received the packet header, drop what has come in. */
+         } else if (pc->inState < PDDATA) {
+           PPPDEBUG((LOG_WARNING,
+                    "pppInProc[%d]: Dropping incomplete packet %d\n", 
+                     pd, pc->inState));
+           LINK_STATS_INC(link.lenerr);
+           pppDrop(pc);
+         /* If the fcs is invalid, drop the packet. */
+         } else if (pc->inFCS != PPP_GOODFCS) {
+           PPPDEBUG((LOG_INFO,
+                    "pppInProc[%d]: Dropping bad fcs 0x%04X proto=0x%04X\n", 
+                     pd, pc->inFCS, pc->inProtocol));
+           LINK_STATS_INC(link.chkerr);
+           pppDrop(pc);
+         /* Otherwise it's a good packet so pass it on. */
+         } else {
+           /* Trim off the checksum. */
+           if(pc->inTail->len >= 2) {
+             pc->inTail->len -= 2;
+
+             pc->inTail->tot_len = pc->inTail->len;
+             if (pc->inTail != pc->inHead) {
+               pbuf_cat(pc->inHead, pc->inTail);
+             }
+           } else {
+             pc->inTail->tot_len = pc->inTail->len;
+             if (pc->inTail != pc->inHead) {
+               pbuf_cat(pc->inHead, pc->inTail);
+             }
+
+             pbuf_realloc(pc->inHead, pc->inHead->tot_len - 2);
+           }
+
+           /* Dispatch the packet thereby consuming it. */
+           if(tcpip_callback(pppInput, pc->inHead) != ERR_OK) {
+             PPPDEBUG((LOG_ERR, "pppInProc[%d]: tcpip_callback() failed, dropping packet\n", pd));
+             pbuf_free(pc->inHead);
+             LINK_STATS_INC(link.drop);
+           }
+           pc->inHead = NULL;
+           pc->inTail = NULL;
+         }
+
+         /* Prepare for a new packet. */
+         pc->inFCS = PPP_INITFCS;
+         pc->inState = PDADDRESS;
+         pc->inEscaped = 0;
+      /* Other characters are usually control characters that may have
+       * been inserted by the physical layer so here we just drop them. */
+      } else {
+        PPPDEBUG((LOG_WARNING,
+                 "pppInProc[%d]: Dropping ACCM char <%d>\n", pd, curChar));
+      }
+    /* Process other characters. */
+    } else {
+      /* Unencode escaped characters. */
+      if (pc->inEscaped) {
+        pc->inEscaped = 0;
+        curChar ^= PPP_TRANS;
+      }
+
+      /* Process character relative to current state. */
+      switch(pc->inState) {
+        case PDIDLE:                    /* Idle state - waiting. */
+          /* Drop the character if it's not 0xff
+           * we would have processed a flag character above. */
+          if (curChar != PPP_ALLSTATIONS) {
+            break;
+          }
+
+        /* Fall through */
+        case PDSTART:                   /* Process start flag. */
+          /* Prepare for a new packet. */
+          pc->inFCS = PPP_INITFCS;
+
+        /* Fall through */
+        case PDADDRESS:                 /* Process address field. */
+          if (curChar == PPP_ALLSTATIONS) {
+            pc->inState = PDCONTROL;
+            break;
+          }
+          /* Else assume compressed address and control fields so
+           * fall through to get the protocol... */
+        case PDCONTROL:                 /* Process control field. */
+          /* If we don't get a valid control code, restart. */
+          if (curChar == PPP_UI) {
+            pc->inState = PDPROTOCOL1;
+            break;
+          }
+#if 0
+          else {
+            PPPDEBUG((LOG_WARNING,
+                     "pppInProc[%d]: Invalid control <%d>\n", pd, curChar));
+                      pc->inState = PDSTART;
+          }
+#endif
+        case PDPROTOCOL1:               /* Process protocol field 1. */
+          /* If the lower bit is set, this is the end of the protocol
+           * field. */
+          if (curChar & 1) {
+            pc->inProtocol = curChar;
+            pc->inState = PDDATA;
+          } else {
+            pc->inProtocol = (u_int)curChar << 8;
+            pc->inState = PDPROTOCOL2;
+          }
+          break;
+        case PDPROTOCOL2:               /* Process protocol field 2. */
+          pc->inProtocol |= curChar;
+          pc->inState = PDDATA;
+          break;
+        case PDDATA:                    /* Process data byte. */
+          /* Make space to receive processed data. */
+          if (pc->inTail == NULL || pc->inTail->len == PBUF_POOL_BUFSIZE) {
+            if(pc->inTail) {
+              pc->inTail->tot_len = pc->inTail->len;
+              if (pc->inTail != pc->inHead) {
+                pbuf_cat(pc->inHead, pc->inTail);
+              }
+            }
+            /* If we haven't started a packet, we need a packet header. */
+            nextNBuf = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+            if (nextNBuf == NULL) {
+              /* No free buffers.  Drop the input packet and let the
+               * higher layers deal with it.  Continue processing
+               * the received pbuf chain in case a new packet starts. */
+              PPPDEBUG((LOG_ERR, "pppInProc[%d]: NO FREE MBUFS!\n", pd));
+              LINK_STATS_INC(link.memerr);
+              pppDrop(pc);
+              pc->inState = PDSTART;  /* Wait for flag sequence. */
+              break;
+            }
+            if (pc->inHead == NULL) {
+              struct pppInputHeader *pih = nextNBuf->payload;
+
+              pih->unit = pd;
+              pih->proto = pc->inProtocol;
+
+              nextNBuf->len += sizeof(*pih);
+
+              pc->inHead = nextNBuf;
+            }
+            pc->inTail = nextNBuf;
+          }
+          /* Load character into buffer. */
+          ((u_char*)pc->inTail->payload)[pc->inTail->len++] = curChar;
+          break;
+      }
+
+      /* update the frame check sequence number. */
+      pc->inFCS = PPP_FCS(pc->inFCS, curChar);
+    }
+  }
+
+  avRandomize();
+}
+#endif /* PPPOS_SUPPORT */
+
+#if PPPOE_SUPPORT
+void
+pppInProcOverEthernet(int pd, struct pbuf *pb)
+{
+  struct pppInputHeader *pih;
+  u16_t inProtocol;
+
+  if(pb->len < sizeof(inProtocol)) {
+    PPPDEBUG((LOG_ERR, "pppInProcOverEthernet: too small for protocol field\n"));
+    goto drop;
+  }
+
+  inProtocol = (((u8_t *)pb->payload)[0] << 8) | ((u8_t*)pb->payload)[1];
+
+  /* make room for pppInputHeader - should not fail */
+  if (pbuf_header(pb, sizeof(*pih) - sizeof(inProtocol)) != 0) {
+    PPPDEBUG((LOG_ERR, "pppInProcOverEthernet: could not allocate room for header\n"));
+    goto drop;
+  }
+
+  pih = pb->payload;
+
+  pih->unit = pd;
+  pih->proto = inProtocol;
+
+  /* Dispatch the packet thereby consuming it. */
+  if(tcpip_callback(pppInput, pb) != ERR_OK) {
+    PPPDEBUG((LOG_ERR, "pppInProcOverEthernet[%d]: tcpip_callback() failed, dropping packet\n", pd));
+    goto drop;
+  }
+
+  return;
+
+drop:
+  LINK_STATS_INC(link.drop);
+  pbuf_free(pb);
+  return;
+}
+#endif /* PPPOE_SUPPORT */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/ppp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/ppp.h
new file mode 100644
index 0000000..d610e4b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/ppp.h
@@ -0,0 +1,465 @@
+/*****************************************************************************
+* ppp.h - Network Point to Point Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD codes.
+*****************************************************************************/
+
+#ifndef PPP_H
+#define PPP_H
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/def.h"
+#include "lwip/sio.h"
+#include "lwip/api.h"
+#include "lwip/sockets.h"
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+#include "lwip/tcpip.h"
+#include "lwip/netif.h"
+
+/*
+ * pppd.h - PPP daemon global declarations.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ */
+/*
+ * ppp_defs.h - PPP definitions.
+ *
+ * Copyright (c) 1994 The Australian National University.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, provided that the above copyright
+ * notice appears in all copies.  This software is provided without any
+ * warranty, express or implied. The Australian National University
+ * makes no representations about the suitability of this software for
+ * any purpose.
+ *
+ * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY
+ * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
+ * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
+ * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS,
+ * OR MODIFICATIONS.
+ */
+
+#define TIMEOUT(f, a, t)    sys_untimeout((f), (a)), sys_timeout((t)*1000, (f), (a))
+#define UNTIMEOUT(f, a)     sys_untimeout((f), (a))
+
+
+#ifndef __u_char_defined
+
+/* Type definitions for BSD code. */
+typedef unsigned long  u_long;
+typedef unsigned int   u_int;
+typedef unsigned short u_short;
+typedef unsigned char  u_char;
+
+#endif
+
+/*
+ * Constants and structures defined by the internet system,
+ * Per RFC 790, September 1981, and numerous additions.
+ */
+
+/*
+ * The basic PPP frame.
+ */
+#define PPP_HDRLEN      4       /* octets for standard ppp header */
+#define PPP_FCSLEN      2       /* octets for FCS */
+
+
+/*
+ * Significant octet values.
+ */
+#define PPP_ALLSTATIONS 0xff    /* All-Stations broadcast address */
+#define PPP_UI          0x03    /* Unnumbered Information */
+#define PPP_FLAG        0x7e    /* Flag Sequence */
+#define PPP_ESCAPE      0x7d    /* Asynchronous Control Escape */
+#define PPP_TRANS       0x20    /* Asynchronous transparency modifier */
+
+/*
+ * Protocol field values.
+ */
+#define PPP_IP          0x21    /* Internet Protocol */
+#define PPP_AT          0x29    /* AppleTalk Protocol */
+#define PPP_VJC_COMP    0x2d    /* VJ compressed TCP */
+#define PPP_VJC_UNCOMP  0x2f    /* VJ uncompressed TCP */
+#define PPP_COMP        0xfd    /* compressed packet */
+#define PPP_IPCP        0x8021  /* IP Control Protocol */
+#define PPP_ATCP        0x8029  /* AppleTalk Control Protocol */
+#define PPP_CCP         0x80fd  /* Compression Control Protocol */
+#define PPP_LCP         0xc021  /* Link Control Protocol */
+#define PPP_PAP         0xc023  /* Password Authentication Protocol */
+#define PPP_LQR         0xc025  /* Link Quality Report protocol */
+#define PPP_CHAP        0xc223  /* Cryptographic Handshake Auth. Protocol */
+#define PPP_CBCP        0xc029  /* Callback Control Protocol */
+
+/*
+ * Values for FCS calculations.
+ */
+#define PPP_INITFCS     0xffff  /* Initial FCS value */
+#define PPP_GOODFCS     0xf0b8  /* Good final FCS value */
+#define PPP_FCS(fcs, c) (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff])
+
+/*
+ * Extended asyncmap - allows any character to be escaped.
+ */
+typedef u_char  ext_accm[32];
+
+/*
+ * What to do with network protocol (NP) packets.
+ */
+enum NPmode {
+  NPMODE_PASS,        /* pass the packet through */
+  NPMODE_DROP,        /* silently drop the packet */
+  NPMODE_ERROR,       /* return an error */
+  NPMODE_QUEUE        /* save it up for later. */
+};
+
+/*
+ * Inline versions of get/put char/short/long.
+ * Pointer is advanced; we assume that both arguments
+ * are lvalues and will already be in registers.
+ * cp MUST be u_char *.
+ */
+#define GETCHAR(c, cp) { \
+    (c) = *(cp)++; \
+}
+#define PUTCHAR(c, cp) { \
+    *(cp)++ = (u_char) (c); \
+}
+
+
+#define GETSHORT(s, cp) { \
+    (s) = *(cp); (cp)++; (s) <<= 8; \
+    (s) |= *(cp); (cp)++; \
+}
+#define PUTSHORT(s, cp) { \
+    *(cp)++ = (u_char) ((s) >> 8); \
+    *(cp)++ = (u_char) (s & 0xff); \
+}
+
+#define GETLONG(l, cp) { \
+    (l) = *(cp); (cp)++; (l) <<= 8; \
+    (l) |= *(cp); (cp)++; (l) <<= 8; \
+    (l) |= *(cp); (cp)++; (l) <<= 8; \
+    (l) |= *(cp); (cp)++; \
+}
+#define PUTLONG(l, cp) { \
+    *(cp)++ = (u_char) ((l) >> 24); \
+    *(cp)++ = (u_char) ((l) >> 16); \
+    *(cp)++ = (u_char) ((l) >> 8); \
+    *(cp)++ = (u_char) (l); \
+}
+
+
+#define INCPTR(n, cp)   ((cp) += (n))
+#define DECPTR(n, cp)   ((cp) -= (n))
+
+#define BCMP(s0, s1, l)     memcmp((u_char *)(s0), (u_char *)(s1), (l))
+#define BCOPY(s, d, l)      MEMCPY((d), (s), (l))
+#define BZERO(s, n)         memset(s, 0, n)
+
+#if PPP_DEBUG
+#define PRINTMSG(m, l)  { m[l] = '\0'; ppp_trace(LOG_INFO, "Remote message: %s\n", m); }
+#else  /* PPP_DEBUG */
+#define PRINTMSG(m, l)
+#endif /* PPP_DEBUG */
+
+/*
+ * MAKEHEADER - Add PPP Header fields to a packet.
+ */
+#define MAKEHEADER(p, t) { \
+    PUTCHAR(PPP_ALLSTATIONS, p); \
+    PUTCHAR(PPP_UI, p); \
+    PUTSHORT(t, p); }
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+
+/* Error codes. */
+#define PPPERR_NONE      0 /* No error. */
+#define PPPERR_PARAM    -1 /* Invalid parameter. */
+#define PPPERR_OPEN     -2 /* Unable to open PPP session. */
+#define PPPERR_DEVICE   -3 /* Invalid I/O device for PPP. */
+#define PPPERR_ALLOC    -4 /* Unable to allocate resources. */
+#define PPPERR_USER     -5 /* User interrupt. */
+#define PPPERR_CONNECT  -6 /* Connection lost. */
+#define PPPERR_AUTHFAIL -7 /* Failed authentication challenge. */
+#define PPPERR_PROTOCOL -8 /* Failed to meet protocol. */
+
+/*
+ * PPP IOCTL commands.
+ */
+/*
+ * Get the up status - 0 for down, non-zero for up.  The argument must
+ * point to an int.
+ */
+#define PPPCTLG_UPSTATUS 100 /* Get the up status - 0 down else up */
+#define PPPCTLS_ERRCODE  101 /* Set the error code */
+#define PPPCTLG_ERRCODE  102 /* Get the error code */
+#define PPPCTLG_FD       103 /* Get the fd associated with the ppp */
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * The following struct gives the addresses of procedures to call
+ * for a particular protocol.
+ */
+struct protent {
+    u_short protocol;       /* PPP protocol number */
+    /* Initialization procedure */
+    void (*init) (int unit);
+    /* Process a received packet */
+    void (*input) (int unit, u_char *pkt, int len);
+    /* Process a received protocol-reject */
+    void (*protrej) (int unit);
+    /* Lower layer has come up */
+    void (*lowerup) (int unit);
+    /* Lower layer has gone down */
+    void (*lowerdown) (int unit);
+    /* Open the protocol */
+    void (*open) (int unit);
+    /* Close the protocol */
+    void (*close) (int unit, char *reason);
+#if 0
+    /* Print a packet in readable form */
+    int  (*printpkt) (u_char *pkt, int len,
+              void (*printer) (void *, char *, ...),
+              void *arg);
+    /* Process a received data packet */
+    void (*datainput) (int unit, u_char *pkt, int len);
+#endif
+    int  enabled_flag;      /* 0 iff protocol is disabled */
+    char *name;         /* Text name of protocol */
+#if 0
+    /* Check requested options, assign defaults */
+    void (*check_options) (u_long);
+    /* Configure interface for demand-dial */
+    int  (*demand_conf) (int unit);
+    /* Say whether to bring up link for this pkt */
+    int  (*active_pkt) (u_char *pkt, int len);
+#endif
+};
+
+/*
+ * The following structure records the time in seconds since
+ * the last NP packet was sent or received.
+ */
+struct ppp_idle {
+  u_short xmit_idle;      /* seconds since last NP packet sent */
+  u_short recv_idle;      /* seconds since last NP packet received */
+};
+
+struct ppp_settings {
+
+  u_int  disable_defaultip : 1;       /* Don't use hostname for default IP addrs */
+  u_int  auth_required     : 1;       /* Peer is required to authenticate */
+  u_int  explicit_remote   : 1;       /* remote_name specified with remotename opt */
+  u_int  refuse_pap        : 1;       /* Don't wanna auth. ourselves with PAP */
+  u_int  refuse_chap       : 1;       /* Don't wanna auth. ourselves with CHAP */
+  u_int  usehostname       : 1;       /* Use hostname for our_name */
+  u_int  usepeerdns        : 1;       /* Ask peer for DNS adds */
+
+  u_short idle_time_limit;            /* Shut down link if idle for this long */
+  int  maxconnect;                    /* Maximum connect time (seconds) */
+
+  char user       [MAXNAMELEN   + 1]; /* Username for PAP */
+  char passwd     [MAXSECRETLEN + 1]; /* Password for PAP, secret for CHAP */
+  char our_name   [MAXNAMELEN   + 1]; /* Our name for authentication purposes */
+  char remote_name[MAXNAMELEN   + 1]; /* Peer's name for authentication */
+};
+
+struct ppp_addrs {
+  struct ip_addr our_ipaddr, his_ipaddr, netmask, dns1, dns2;
+};
+
+/*****************************
+*** PUBLIC DATA STRUCTURES ***
+*****************************/
+
+/* Buffers for outgoing packets. */
+extern u_char *outpacket_buf[NUM_PPP];
+
+extern struct ppp_settings ppp_settings;
+
+extern struct protent *ppp_protocols[]; /* Table of pointers to supported protocols */
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+/* Initialize the PPP subsystem. */
+err_t pppInit(void);
+
+/* Warning: Using PPPAUTHTYPE_ANY might have security consequences.
+ * RFC 1994 says:
+ *
+ * In practice, within or associated with each PPP server, there is a
+ * database which associates "user" names with authentication
+ * information ("secrets").  It is not anticipated that a particular
+ * named user would be authenticated by multiple methods.  This would
+ * make the user vulnerable to attacks which negotiate the least secure
+ * method from among a set (such as PAP rather than CHAP).  If the same
+ * secret was used, PAP would reveal the secret to be used later with
+ * CHAP.
+ *
+ * Instead, for each user name there should be an indication of exactly
+ * one method used to authenticate that user name.  If a user needs to
+ * make use of different authentication methods under different
+ * circumstances, then distinct user names SHOULD be employed, each of
+ * which identifies exactly one authentication method.
+ *
+ */
+enum pppAuthType {
+    PPPAUTHTYPE_NONE,
+    PPPAUTHTYPE_ANY,
+    PPPAUTHTYPE_PAP,
+    PPPAUTHTYPE_CHAP
+};
+
+void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd);
+
+/*
+ * Open a new PPP connection using the given serial I/O device.
+ * This initializes the PPP control block but does not
+ * attempt to negotiate the LCP session.
+ * Return a new PPP connection descriptor on success or
+ * an error code (negative) on failure. 
+ */
+int pppOverSerialOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx);
+
+/*
+ * Open a new PPP Over Ethernet (PPPOE) connection.
+ */
+int pppOverEthernetOpen(struct netif *ethif, const char *service_name, const char *concentrator_name, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx);
+
+/* for source code compatibility */
+#define pppOpen(fd,cb,ls) pppOverSerialOpen(fd,cb,ls)
+
+/*
+ * Close a PPP connection and release the descriptor. 
+ * Any outstanding packets in the queues are dropped.
+ * Return 0 on success, an error code on failure. 
+ */
+int pppClose(int pd);
+
+/*
+ * Indicate to the PPP process that the line has disconnected.
+ */
+void pppSigHUP(int pd);
+
+/*
+ * Get and set parameters for the given connection.
+ * Return 0 on success, an error code on failure. 
+ */
+int  pppIOCtl(int pd, int cmd, void *arg);
+
+/*
+ * Return the Maximum Transmission Unit for the given PPP connection.
+ */
+u_int pppMTU(int pd);
+
+/*
+ * Write n characters to a ppp link.
+ * RETURN: >= 0 Number of characters written, -1 Failed to write to device.
+ */
+int pppWrite(int pd, const u_char *s, int n);
+
+void pppInProcOverEthernet(int pd, struct pbuf *pb);
+
+struct pbuf *pppSingleBuf(struct pbuf *p);
+
+void pppLinkTerminated(int pd);
+
+void pppLinkDown(int pd);
+
+void pppMainWakeup(int pd);
+
+/* Configure i/f transmit parameters */
+void ppp_send_config (int, int, u32_t, int, int);
+/* Set extended transmit ACCM */
+void ppp_set_xaccm (int, ext_accm *);
+/* Configure i/f receive parameters */
+void ppp_recv_config (int, int, u32_t, int, int);
+/* Find out how long link has been idle */
+int  get_idle_time (int, struct ppp_idle *);
+
+/* Configure VJ TCP header compression */
+int  sifvjcomp (int, int, int, int);
+/* Configure i/f down (for IP) */
+int  sifup (int);
+/* Set mode for handling packets for proto */
+int  sifnpmode (int u, int proto, enum NPmode mode);
+/* Configure i/f down (for IP) */
+int  sifdown (int);
+/* Configure IP addresses for i/f */
+int  sifaddr (int, u32_t, u32_t, u32_t, u32_t, u32_t);
+/* Reset i/f IP addresses */
+int  cifaddr (int, u32_t, u32_t);
+/* Create default route through i/f */
+int  sifdefaultroute (int, u32_t, u32_t);
+/* Delete default route through i/f */
+int  cifdefaultroute (int, u32_t, u32_t);
+
+/* Get appropriate netmask for address */
+u32_t GetMask (u32_t); 
+
+#endif /* PPP_SUPPORT */
+
+#endif /* PPP_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/ppp_oe.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/ppp_oe.c
new file mode 100644
index 0000000..2fcffdd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/ppp_oe.c
@@ -0,0 +1,1227 @@
+/*****************************************************************************
+* ppp_oe.c - PPP Over Ethernet implementation for lwIP.
+*
+* Copyright (c) 2006 by Marc Boucher, Services Informatiques (MBSI) inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 06-01-01 Marc Boucher 
+*   Ported to lwIP.
+*****************************************************************************/
+
+
+
+/* based on NetBSD: if_pppoe.c,v 1.64 2006/01/31 23:50:15 martin Exp */
+
+/*-
+ * Copyright (c) 2002 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Martin Husemann .
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "lwip/opt.h"
+
+#if PPPOE_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "lwip/sys.h"
+
+#include "netif/ppp_oe.h"
+#include "netif/etharp.h"
+
+#include 
+#include 
+
+/** @todo Replace this part with a simple list like other lwIP lists */
+#ifndef _SYS_QUEUE_H_
+#define _SYS_QUEUE_H_
+
+/*
+ * A list is headed by a single forward pointer (or an array of forward
+ * pointers for a hash table header). The elements are doubly linked
+ * so that an arbitrary element can be removed without a need to
+ * traverse the list. New elements can be added to the list before
+ * or after an existing element or at the head of the list. A list
+ * may only be traversed in the forward direction.
+ *
+ * For details on the use of these macros, see the queue(3) manual page.
+ */
+
+/*
+ * List declarations.
+ */
+#define  LIST_HEAD(name, type)                                                 \
+struct name {                                                                  \
+  struct type *lh_first;  /* first element */                                  \
+}
+
+#define  LIST_HEAD_INITIALIZER(head)                                           \
+  { NULL }
+
+#define  LIST_ENTRY(type)                                                      \
+struct {                                                                       \
+  struct type *le_next;  /* next element */                                    \
+  struct type **le_prev; /* address of previous next element */                \
+}
+
+/*
+ * List functions.
+ */
+
+#define  LIST_EMPTY(head)  ((head)->lh_first == NULL)
+
+#define  LIST_FIRST(head)  ((head)->lh_first)
+
+#define  LIST_FOREACH(var, head, field)                                        \
+  for ((var) = LIST_FIRST((head));                                             \
+      (var);                                                                   \
+      (var) = LIST_NEXT((var), field))
+
+#define  LIST_INIT(head) do {                                                  \
+  LIST_FIRST((head)) = NULL;                                                   \
+} while (0)
+
+#define  LIST_INSERT_AFTER(listelm, elm, field) do {                           \
+  if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)         \
+    LIST_NEXT((listelm), field)->field.le_prev =                               \
+        &LIST_NEXT((elm), field);                                              \
+  LIST_NEXT((listelm), field) = (elm);                                         \
+  (elm)->field.le_prev = &LIST_NEXT((listelm), field);                         \
+} while (0)
+
+#define  LIST_INSERT_BEFORE(listelm, elm, field) do {                          \
+  (elm)->field.le_prev = (listelm)->field.le_prev;                             \
+  LIST_NEXT((elm), field) = (listelm);                                         \
+  *(listelm)->field.le_prev = (elm);                                           \
+  (listelm)->field.le_prev = &LIST_NEXT((elm), field);                         \
+} while (0)
+
+#define  LIST_INSERT_HEAD(head, elm, field) do {                               \
+  if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL)                  \
+    LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);              \
+  LIST_FIRST((head)) = (elm);                                                  \
+  (elm)->field.le_prev = &LIST_FIRST((head));                                  \
+} while (0)
+
+#define  LIST_NEXT(elm, field)  ((elm)->field.le_next)
+
+#define  LIST_REMOVE(elm, field) do {                                          \
+  if (LIST_NEXT((elm), field) != NULL)                                         \
+    LIST_NEXT((elm), field)->field.le_prev =                                   \
+        (elm)->field.le_prev;                                                  \
+  *(elm)->field.le_prev = LIST_NEXT((elm), field);                             \
+} while (0)
+
+#endif /* !_SYS_QUEUE_H_ */
+
+
+/* Add a 16 bit unsigned value to a buffer pointed to by PTR */
+#define PPPOE_ADD_16(PTR, VAL) \
+    *(PTR)++ = (VAL) / 256;    \
+    *(PTR)++ = (VAL) % 256
+
+/* Add a complete PPPoE header to the buffer pointed to by PTR */
+#define PPPOE_ADD_HEADER(PTR, CODE, SESS, LEN)  \
+    *(PTR)++ = PPPOE_VERTYPE;  \
+    *(PTR)++ = (CODE);         \
+    PPPOE_ADD_16(PTR, SESS);   \
+    PPPOE_ADD_16(PTR, LEN)
+
+#define PPPOE_DISC_TIMEOUT (5*1000)  /* base for quick timeout calculation */
+#define PPPOE_SLOW_RETRY   (60*1000) /* persistent retry interval */
+#define PPPOE_DISC_MAXPADI  4        /* retry PADI four times (quickly) */
+#define PPPOE_DISC_MAXPADR  2        /* retry PADR twice */
+
+#ifdef PPPOE_SERVER
+/* from if_spppsubr.c */
+#define IFF_PASSIVE IFF_LINK0 /* wait passively for connection */
+#endif
+
+struct pppoe_softc {
+  LIST_ENTRY(pppoe_softc) sc_list;
+  struct netif *sc_ethif;      /* ethernet interface we are using */
+  int sc_pd;                   /* ppp unit number */
+  void (*sc_linkStatusCB)(int pd, int up);
+
+  int sc_state;                /* discovery phase or session connected */
+  struct eth_addr sc_dest;     /* hardware address of concentrator */
+  u16_t sc_session;            /* PPPoE session id */
+
+  char *sc_service_name;       /* if != NULL: requested name of service */
+  char *sc_concentrator_name;  /* if != NULL: requested concentrator id */
+  u8_t *sc_ac_cookie;          /* content of AC cookie we must echo back */
+  size_t sc_ac_cookie_len;     /* length of cookie data */
+#ifdef PPPOE_SERVER
+  u8_t *sc_hunique;            /* content of host unique we must echo back */
+  size_t sc_hunique_len;       /* length of host unique */
+#endif
+  int sc_padi_retried;         /* number of PADI retries already done */
+  int sc_padr_retried;         /* number of PADR retries already done */
+};
+
+/* input routines */
+static void pppoe_dispatch_disc_pkt(struct netif *, struct pbuf *);
+
+/* management routines */
+static int pppoe_do_disconnect(struct pppoe_softc *);
+static void pppoe_abort_connect(struct pppoe_softc *);
+static void pppoe_clear_softc(struct pppoe_softc *, const char *);
+
+/* internal timeout handling */
+static void pppoe_timeout(void *);
+
+/* sending actual protocol controll packets */
+static err_t pppoe_send_padi(struct pppoe_softc *);
+static err_t pppoe_send_padr(struct pppoe_softc *);
+#ifdef PPPOE_SERVER
+static err_t pppoe_send_pado(struct pppoe_softc *);
+static err_t pppoe_send_pads(struct pppoe_softc *);
+#endif
+static err_t pppoe_send_padt(struct netif *, u_int, const u8_t *);
+
+/* internal helper functions */
+static struct pppoe_softc * pppoe_find_softc_by_session(u_int, struct netif *);
+static struct pppoe_softc * pppoe_find_softc_by_hunique(u8_t *, size_t, struct netif *);
+
+static LIST_HEAD(pppoe_softc_head, pppoe_softc) pppoe_softc_list;
+
+int pppoe_hdrlen;
+
+void
+pppoe_init(void)
+{
+  pppoe_hdrlen = sizeof(struct eth_hdr) + PPPOE_HEADERLEN;
+  LIST_INIT(&pppoe_softc_list);
+}
+
+err_t
+pppoe_create(struct netif *ethif, int pd, void (*linkStatusCB)(int pd, int up), struct pppoe_softc **scptr)
+{
+  struct pppoe_softc *sc;
+
+  sc = mem_malloc(sizeof(struct pppoe_softc));
+  if(!sc) {
+    *scptr = NULL;
+    return ERR_MEM;
+  }
+  memset(sc, 0, sizeof(struct pppoe_softc));
+
+  /* changed to real address later */
+  MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest));
+
+  sc->sc_pd = pd;
+  sc->sc_linkStatusCB = linkStatusCB;
+  sc->sc_ethif = ethif;
+
+  LIST_INSERT_HEAD(&pppoe_softc_list, sc, sc_list);
+
+  *scptr = sc;
+
+  return ERR_OK;
+}
+
+err_t
+pppoe_destroy(struct netif *ifp)
+{
+  struct pppoe_softc * sc;
+
+  LIST_FOREACH(sc, &pppoe_softc_list, sc_list) {
+    if (sc->sc_ethif == ifp) {
+      break;
+    }
+  }
+
+  if(!(sc && (sc->sc_ethif == ifp))) {
+    return ERR_IF;
+  }
+
+  tcpip_untimeout(pppoe_timeout, sc);
+  LIST_REMOVE(sc, sc_list);
+
+  if (sc->sc_concentrator_name) {
+    mem_free(sc->sc_concentrator_name);
+  }
+  if (sc->sc_service_name) {
+    mem_free(sc->sc_service_name);
+  }
+  if (sc->sc_ac_cookie) {
+    mem_free(sc->sc_ac_cookie);
+  }
+  mem_free(sc);
+
+  return ERR_OK;
+}
+
+/*
+ * Find the interface handling the specified session.
+ * Note: O(number of sessions open), this is a client-side only, mean
+ * and lean implementation, so number of open sessions typically should
+ * be 1.
+ */
+static struct pppoe_softc *
+pppoe_find_softc_by_session(u_int session, struct netif *rcvif)
+{
+  struct pppoe_softc *sc;
+
+  if (session == 0) {
+    return NULL;
+  }
+
+  LIST_FOREACH(sc, &pppoe_softc_list, sc_list) {
+    if (sc->sc_state == PPPOE_STATE_SESSION
+        && sc->sc_session == session) {
+      if (sc->sc_ethif == rcvif) {
+        return sc;
+      } else {
+        return NULL;
+      }
+    }
+  }
+  return NULL;
+}
+
+/* Check host unique token passed and return appropriate softc pointer,
+ * or NULL if token is bogus. */
+static struct pppoe_softc *
+pppoe_find_softc_by_hunique(u8_t *token, size_t len, struct netif *rcvif)
+{
+  struct pppoe_softc *sc, *t;
+
+  if (LIST_EMPTY(&pppoe_softc_list)) {
+    return NULL;
+  }
+
+  if (len != sizeof sc) {
+    return NULL;
+  }
+  MEMCPY(&t, token, len);
+
+  LIST_FOREACH(sc, &pppoe_softc_list, sc_list) {
+    if (sc == t) {
+      break;
+    }
+  }
+
+  if (sc == NULL) {
+    PPPDEBUG((LOG_DEBUG, "pppoe: alien host unique tag, no session found\n"));
+    return NULL;
+  }
+
+  /* should be safe to access *sc now */
+  if (sc->sc_state < PPPOE_STATE_PADI_SENT || sc->sc_state >= PPPOE_STATE_SESSION) {
+    printf("%c%c%"U16_F": host unique tag found, but it belongs to a connection in state %d\n",
+      sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, sc->sc_state);
+    return NULL;
+  }
+  if (sc->sc_ethif != rcvif) {
+    printf("%c%c%"U16_F": wrong interface, not accepting host unique\n",
+      sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num);
+    return NULL;
+  }
+  return sc;
+}
+
+static void
+pppoe_linkstatus_up(void *arg)
+{
+  struct pppoe_softc *sc = (struct pppoe_softc*)arg;
+
+  sc->sc_linkStatusCB(sc->sc_pd, 1);
+}
+
+/* analyze and handle a single received packet while not in session state */
+static void
+pppoe_dispatch_disc_pkt(struct netif *netif, struct pbuf *pb)
+{
+  u16_t tag, len;
+  u16_t session, plen;
+  struct pppoe_softc *sc;
+  const char *err_msg;
+  char devname[6];
+  char *error;
+  u8_t *ac_cookie;
+  size_t ac_cookie_len;
+#ifdef PPPOE_SERVER
+  u8_t *hunique;
+  size_t hunique_len;
+#endif
+  struct pppoehdr *ph;
+  struct pppoetag pt;
+  int off = 0, err, errortag;
+  struct eth_hdr *ethhdr;
+
+  pb = pppSingleBuf(pb);
+
+  strcpy(devname, "pppoe");  /* as long as we don't know which instance */
+  err_msg = NULL;
+  errortag = 0;
+  if (pb->len < sizeof(*ethhdr)) {
+    goto done;
+  }
+  ethhdr = (struct eth_hdr *)pb->payload;
+  off += sizeof(*ethhdr);
+
+  ac_cookie = NULL;
+  ac_cookie_len = 0;
+#ifdef PPPOE_SERVER
+  hunique = NULL;
+  hunique_len = 0;
+#endif
+  session = 0;
+  if (pb->len - off <= PPPOE_HEADERLEN) {
+    printf("pppoe: packet too short: %d\n", pb->len);
+    goto done;
+  }
+
+  ph = (struct pppoehdr *) (ethhdr + 1);
+  if (ph->vertype != PPPOE_VERTYPE) {
+    printf("pppoe: unknown version/type packet: 0x%x\n", ph->vertype);
+    goto done;
+  }
+  session = ntohs(ph->session);
+  plen = ntohs(ph->plen);
+  off += sizeof(*ph);
+
+  if (plen + off > pb->len) {
+    printf("pppoe: packet content does not fit: data available = %d, packet size = %u\n",
+        pb->len - off, plen);
+    goto done;
+  }
+  if(pb->tot_len == pb->len) {
+    pb->tot_len = pb->len = off + plen; /* ignore trailing garbage */
+  }
+  tag = 0;
+  len = 0;
+  sc = NULL;
+  while (off + sizeof(pt) <= pb->len) {
+    MEMCPY(&pt, (u8_t*)pb->payload + off, sizeof(pt));
+    tag = ntohs(pt.tag);
+    len = ntohs(pt.len);
+    if (off + sizeof(pt) + len > pb->len) {
+      printf("pppoe: tag 0x%x len 0x%x is too long\n", tag, len);
+      goto done;
+    }
+    switch (tag) {
+      case PPPOE_TAG_EOL:
+        goto breakbreak;
+      case PPPOE_TAG_SNAME:
+        break;  /* ignored */
+      case PPPOE_TAG_ACNAME:
+        break;  /* ignored */
+      case PPPOE_TAG_HUNIQUE:
+        if (sc != NULL) {
+          break;
+        }
+#ifdef PPPOE_SERVER
+        hunique = (u8_t*)pb->payload + off + sizeof(pt);
+        hunique_len = len;
+#endif
+        sc = pppoe_find_softc_by_hunique((u8_t*)pb->payload + off + sizeof(pt), len, netif);
+        if (sc != NULL) {
+          snprintf(devname, sizeof(devname), "%c%c%"U16_F, sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num);
+        }
+        break;
+      case PPPOE_TAG_ACCOOKIE:
+        if (ac_cookie == NULL) {
+          ac_cookie = (u8_t*)pb->payload + off + sizeof(pt);
+          ac_cookie_len = len;
+        }
+        break;
+      case PPPOE_TAG_SNAME_ERR:
+        err_msg = "SERVICE NAME ERROR";
+        errortag = 1;
+        break;
+      case PPPOE_TAG_ACSYS_ERR:
+        err_msg = "AC SYSTEM ERROR";
+        errortag = 1;
+        break;
+      case PPPOE_TAG_GENERIC_ERR:
+        err_msg = "GENERIC ERROR";
+        errortag = 1;
+        break;
+    }
+    if (err_msg) {
+      error = NULL;
+      if (errortag && len) {
+        error = mem_malloc(len+1);
+        if (error) {
+          strncpy(error, (char*)pb->payload + off + sizeof(pt), len);
+          error[len-1] = '\0';
+        }
+      }
+      if (error) {
+        printf("%s: %s: %s\n", devname, err_msg, error);
+        mem_free(error);
+      } else {
+        printf("%s: %s\n", devname, err_msg);
+      }
+      if (errortag) {
+        goto done;
+      }
+    }
+    off += sizeof(pt) + len;
+  }
+
+breakbreak:;
+  switch (ph->code) {
+    case PPPOE_CODE_PADI:
+#ifdef PPPOE_SERVER
+      /*
+       * got service name, concentrator name, and/or host unique.
+       * ignore if we have no interfaces with IFF_PASSIVE|IFF_UP.
+       */
+      if (LIST_EMPTY(&pppoe_softc_list)) {
+        goto done;
+      }
+      LIST_FOREACH(sc, &pppoe_softc_list, sc_list) {
+        if (!(sc->sc_sppp.pp_if.if_flags & IFF_UP)) {
+          continue;
+        }
+        if (!(sc->sc_sppp.pp_if.if_flags & IFF_PASSIVE)) {
+          continue;
+        }
+        if (sc->sc_state == PPPOE_STATE_INITIAL) {
+          break;
+        }
+      }
+      if (sc == NULL) {
+        /* printf("pppoe: free passive interface is not found\n"); */
+        goto done;
+      }
+      if (hunique) {
+        if (sc->sc_hunique) {
+          mem_free(sc->sc_hunique);
+        }
+        sc->sc_hunique = mem_malloc(hunique_len);
+        if (sc->sc_hunique == NULL) {
+          goto done;
+        }
+        sc->sc_hunique_len = hunique_len;
+        MEMCPY(sc->sc_hunique, hunique, hunique_len);
+      }
+      MEMCPY(&sc->sc_dest, eh->ether_shost, sizeof sc->sc_dest);
+      sc->sc_state = PPPOE_STATE_PADO_SENT;
+      pppoe_send_pado(sc);
+      break;
+  #endif /* PPPOE_SERVER */
+    case PPPOE_CODE_PADR:
+  #ifdef PPPOE_SERVER
+      /*
+       * get sc from ac_cookie if IFF_PASSIVE
+       */
+      if (ac_cookie == NULL) {
+        /* be quiet if there is not a single pppoe instance */
+        printf("pppoe: received PADR but not includes ac_cookie\n");
+        goto done;
+      }
+      sc = pppoe_find_softc_by_hunique(ac_cookie, ac_cookie_len, netif);
+      if (sc == NULL) {
+        /* be quiet if there is not a single pppoe instance */
+        if (!LIST_EMPTY(&pppoe_softc_list)) {
+          printf("pppoe: received PADR but could not find request for it\n");
+        }
+        goto done;
+      }
+      if (sc->sc_state != PPPOE_STATE_PADO_SENT) {
+        printf("%c%c%"U16_F": received unexpected PADR\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num);
+        goto done;
+      }
+      if (hunique) {
+        if (sc->sc_hunique) {
+          mem_free(sc->sc_hunique);
+        }
+        sc->sc_hunique = mem_malloc(hunique_len);
+        if (sc->sc_hunique == NULL) {
+          goto done;
+        }
+        sc->sc_hunique_len = hunique_len;
+        MEMCPY(sc->sc_hunique, hunique, hunique_len);
+      }
+      pppoe_send_pads(sc);
+      sc->sc_state = PPPOE_STATE_SESSION;
+      tcpip_timeout (100, pppoe_linkstatus_up, sc); /* notify upper layers */
+      break;
+  #else
+      /* ignore, we are no access concentrator */
+      goto done;
+  #endif /* PPPOE_SERVER */
+    case PPPOE_CODE_PADO:
+      if (sc == NULL) {
+        /* be quiet if there is not a single pppoe instance */
+        if (!LIST_EMPTY(&pppoe_softc_list)) {
+          printf("pppoe: received PADO but could not find request for it\n");
+        }
+        goto done;
+      }
+      if (sc->sc_state != PPPOE_STATE_PADI_SENT) {
+        printf("%c%c%"U16_F": received unexpected PADO\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num);
+        goto done;
+      }
+      if (ac_cookie) {
+        if (sc->sc_ac_cookie) {
+          mem_free(sc->sc_ac_cookie);
+        }
+        sc->sc_ac_cookie = mem_malloc(ac_cookie_len);
+        if (sc->sc_ac_cookie == NULL) {
+          goto done;
+        }
+        sc->sc_ac_cookie_len = ac_cookie_len;
+        MEMCPY(sc->sc_ac_cookie, ac_cookie, ac_cookie_len);
+      }
+      MEMCPY(&sc->sc_dest, ethhdr->src.addr, sizeof(sc->sc_dest.addr));
+      tcpip_untimeout(pppoe_timeout, sc);
+      sc->sc_padr_retried = 0;
+      sc->sc_state = PPPOE_STATE_PADR_SENT;
+      if ((err = pppoe_send_padr(sc)) != 0) {
+        PPPDEBUG((LOG_DEBUG, "pppoe: %c%c%"U16_F": failed to send PADR, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err));
+      }
+      tcpip_timeout(PPPOE_DISC_TIMEOUT * (1 + sc->sc_padr_retried), pppoe_timeout, sc);
+      break;
+    case PPPOE_CODE_PADS:
+      if (sc == NULL) {
+        goto done;
+      }
+      sc->sc_session = session;
+      tcpip_untimeout(pppoe_timeout, sc);
+      PPPDEBUG((LOG_DEBUG, "pppoe: %c%c%"U16_F": session 0x%x connected\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, session));
+      sc->sc_state = PPPOE_STATE_SESSION;
+      tcpip_timeout (100, pppoe_linkstatus_up, sc); /* notify upper layers */
+      break;
+    case PPPOE_CODE_PADT:
+      if (sc == NULL) {
+        goto done;
+      }
+      pppoe_clear_softc(sc, "received PADT");
+      break;
+    default:
+      if(sc) {
+        printf("%c%c%"U16_F": unknown code (0x%04x) session = 0x%04x\n",
+            sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num,
+            ph->code, session);
+      } else {
+        printf("pppoe: unknown code (0x%04x) session = 0x%04x\n", ph->code, session);
+      }
+      break;
+  }
+
+done:
+  pbuf_free(pb);
+  return;
+}
+
+void
+pppoe_disc_input(struct netif *netif, struct pbuf *p)
+{
+  /* avoid error messages if there is not a single pppoe instance */
+  if (!LIST_EMPTY(&pppoe_softc_list)) {
+    pppoe_dispatch_disc_pkt(netif, p);
+  } else {
+    pbuf_free(p);
+  }
+}
+
+void
+pppoe_data_input(struct netif *netif, struct pbuf *pb)
+{
+  u16_t session, plen;
+  struct pppoe_softc *sc;
+  struct pppoehdr *ph;
+#ifdef PPPOE_TERM_UNKNOWN_SESSIONS
+  u8_t shost[ETHER_ADDR_LEN];
+#endif
+
+#ifdef PPPOE_TERM_UNKNOWN_SESSIONS
+  MEMCPY(shost, ((struct eth_hdr *)pb->payload)->src.addr, sizeof(shost));
+#endif
+  if (pbuf_header(pb, -(int)sizeof(struct eth_hdr)) != 0) {
+    /* bail out */
+    PPPDEBUG((LOG_ERR, "pppoe_data_input: pbuf_header failed\n"));
+    LINK_STATS_INC(link.lenerr);
+    goto drop;
+  } 
+
+  pb = pppSingleBuf (pb);
+
+  if (pb->len <= PPPOE_HEADERLEN) {
+    printf("pppoe (data): dropping too short packet: %d bytes\n", pb->len);
+    goto drop;
+  }
+
+  if (pb->len < sizeof(*ph)) {
+    printf("pppoe_data_input: could not get PPPoE header\n");
+    goto drop;
+  }
+  ph = (struct pppoehdr *)pb->payload;
+
+  if (ph->vertype != PPPOE_VERTYPE) {
+    printf("pppoe (data): unknown version/type packet: 0x%x\n", ph->vertype);
+    goto drop;
+  }
+  if (ph->code != 0) {
+    goto drop;
+  }
+
+  session = ntohs(ph->session);
+  sc = pppoe_find_softc_by_session(session, netif);
+  if (sc == NULL) {
+#ifdef PPPOE_TERM_UNKNOWN_SESSIONS
+    printf("pppoe: input for unknown session 0x%x, sending PADT\n", session);
+    pppoe_send_padt(netif, session, shost);
+#endif
+    goto drop;
+  }
+
+  plen = ntohs(ph->plen);
+
+  if (pbuf_header(pb, -(int)(PPPOE_HEADERLEN)) != 0) {
+    /* bail out */
+    PPPDEBUG((LOG_ERR, "pppoe_data_input: pbuf_header PPPOE_HEADERLEN failed\n"));
+    LINK_STATS_INC(link.lenerr);
+    goto drop;
+  } 
+
+  PPPDEBUG((LOG_DEBUG, "pppoe_data_input: %c%c%"U16_F": pkthdr.len=%d, pppoe.len=%d\n",
+        sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num,
+        pb->len, plen));
+
+  if (pb->len < plen) {
+    goto drop;
+  }
+
+  pppInProcOverEthernet(sc->sc_pd, pb);
+
+  return;
+
+drop:
+  pbuf_free(pb);
+}
+
+static err_t
+pppoe_output(struct pppoe_softc *sc, struct pbuf *pb)
+{
+  struct eth_hdr *ethhdr;
+  u16_t etype;
+  err_t res;
+
+  if (!sc->sc_ethif) {
+    pbuf_free(pb);
+    return ERR_IF;
+  }
+
+  ethhdr = (struct eth_hdr *)pb->payload;
+  etype = sc->sc_state == PPPOE_STATE_SESSION ? ETHTYPE_PPPOE : ETHTYPE_PPPOEDISC;
+  ethhdr->type = htons(etype);
+  MEMCPY(ethhdr->dest.addr, sc->sc_dest.addr, sizeof(ethhdr->dest.addr));
+  MEMCPY(ethhdr->src.addr, ((struct eth_addr *)sc->sc_ethif->hwaddr)->addr, sizeof(ethhdr->src.addr));
+
+  PPPDEBUG((LOG_DEBUG, "pppoe: %c%c%"U16_F" (%x) state=%d, session=0x%x output -> %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F", len=%d\n",
+      sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, etype,
+      sc->sc_state, sc->sc_session,
+      sc->sc_dest.addr[0], sc->sc_dest.addr[1], sc->sc_dest.addr[2], sc->sc_dest.addr[3], sc->sc_dest.addr[4], sc->sc_dest.addr[5],
+      pb->tot_len));
+
+  res = sc->sc_ethif->linkoutput(sc->sc_ethif, pb);
+
+  pbuf_free(pb);
+
+  return res;
+}
+
+static err_t
+pppoe_send_padi(struct pppoe_softc *sc)
+{
+  struct pbuf *pb;
+  u8_t *p;
+  int len, l1 = 0, l2 = 0; /* XXX: gcc */
+
+  if (sc->sc_state >PPPOE_STATE_PADI_SENT) {
+    PPPDEBUG((LOG_ERR, "ERROR: pppoe_send_padi in state %d", sc->sc_state));
+  }
+
+  /* calculate length of frame (excluding ethernet header + pppoe header) */
+  len = 2 + 2 + 2 + 2 + sizeof sc;  /* service name tag is required, host unique is send too */
+  if (sc->sc_service_name != NULL) {
+    l1 = strlen(sc->sc_service_name);
+    len += l1;
+  }
+  if (sc->sc_concentrator_name != NULL) {
+    l2 = strlen(sc->sc_concentrator_name);
+    len += 2 + 2 + l2;
+  }
+
+  /* allocate a buffer */
+  pb = pbuf_alloc(PBUF_LINK, sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len, PBUF_RAM);
+  if (!pb) {
+    return ERR_MEM;
+  }
+
+  p = (u8_t*)pb->payload + sizeof (struct eth_hdr);
+  /* fill in pkt */
+  PPPOE_ADD_HEADER(p, PPPOE_CODE_PADI, 0, len);
+  PPPOE_ADD_16(p, PPPOE_TAG_SNAME);
+  if (sc->sc_service_name != NULL) {
+    PPPOE_ADD_16(p, l1);
+    MEMCPY(p, sc->sc_service_name, l1);
+    p += l1;
+  } else {
+    PPPOE_ADD_16(p, 0);
+  }
+  if (sc->sc_concentrator_name != NULL) {
+    PPPOE_ADD_16(p, PPPOE_TAG_ACNAME);
+    PPPOE_ADD_16(p, l2);
+    MEMCPY(p, sc->sc_concentrator_name, l2);
+    p += l2;
+  }
+  PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE);
+  PPPOE_ADD_16(p, sizeof(sc));
+  MEMCPY(p, &sc, sizeof sc);
+
+  /* send pkt */
+  return pppoe_output(sc, pb);
+}
+
+static void
+pppoe_timeout(void *arg)
+{
+  int retry_wait, err;
+  struct pppoe_softc *sc = (struct pppoe_softc*)arg;
+
+  PPPDEBUG((LOG_DEBUG, "pppoe: %c%c%"U16_F": timeout\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num));
+
+  switch (sc->sc_state) {
+    case PPPOE_STATE_PADI_SENT:
+      /*
+       * We have two basic ways of retrying:
+       *  - Quick retry mode: try a few times in short sequence
+       *  - Slow retry mode: we already had a connection successfully
+       *    established and will try infinitely (without user
+       *    intervention)
+       * We only enter slow retry mode if IFF_LINK1 (aka autodial)
+       * is not set.
+       */
+
+      /* initialize for quick retry mode */
+      retry_wait = PPPOE_DISC_TIMEOUT * (1 + sc->sc_padi_retried);
+
+      sc->sc_padi_retried++;
+      if (sc->sc_padi_retried >= PPPOE_DISC_MAXPADI) {
+#if 0
+        if ((sc->sc_sppp.pp_if.if_flags & IFF_LINK1) == 0) {
+          /* slow retry mode */
+          retry_wait = PPPOE_SLOW_RETRY;
+        } else
+#endif
+        {
+          pppoe_abort_connect(sc);
+          return;
+        }
+      }
+      if ((err = pppoe_send_padi(sc)) != 0) {
+        sc->sc_padi_retried--;
+        PPPDEBUG((LOG_DEBUG, "pppoe: %c%c%"U16_F": failed to transmit PADI, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err));
+      }
+      tcpip_timeout(retry_wait, pppoe_timeout, sc);
+      break;
+
+    case PPPOE_STATE_PADR_SENT:
+      sc->sc_padr_retried++;
+      if (sc->sc_padr_retried >= PPPOE_DISC_MAXPADR) {
+        MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest));
+        sc->sc_state = PPPOE_STATE_PADI_SENT;
+        sc->sc_padr_retried = 0;
+        if ((err = pppoe_send_padi(sc)) != 0) {
+          PPPDEBUG((LOG_DEBUG, "pppoe: %c%c%"U16_F": failed to send PADI, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err));
+        }
+        tcpip_timeout(PPPOE_DISC_TIMEOUT * (1 + sc->sc_padi_retried), pppoe_timeout, sc);
+        return;
+      }
+      if ((err = pppoe_send_padr(sc)) != 0) {
+        sc->sc_padr_retried--;
+        PPPDEBUG((LOG_DEBUG, "pppoe: %c%c%"U16_F": failed to send PADR, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err));
+      }
+      tcpip_timeout(PPPOE_DISC_TIMEOUT * (1 + sc->sc_padr_retried), pppoe_timeout, sc);
+      break;
+    case PPPOE_STATE_CLOSING:
+      pppoe_do_disconnect(sc);
+      break;
+    default:
+      return;  /* all done, work in peace */
+  }
+}
+
+/* Start a connection (i.e. initiate discovery phase) */
+int
+pppoe_connect(struct pppoe_softc *sc)
+{
+  int err;
+
+  if (sc->sc_state != PPPOE_STATE_INITIAL) {
+    return EBUSY;
+  }
+
+#ifdef PPPOE_SERVER
+  /* wait PADI if IFF_PASSIVE */
+  if ((sc->sc_sppp.pp_if.if_flags & IFF_PASSIVE)) {
+    return 0;
+  }
+#endif
+  /* save state, in case we fail to send PADI */
+  sc->sc_state = PPPOE_STATE_PADI_SENT;
+  sc->sc_padr_retried = 0;
+  err = pppoe_send_padi(sc);
+  PPPDEBUG((LOG_DEBUG, "pppoe: %c%c%"U16_F": failed to send PADI, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err));
+  tcpip_timeout(PPPOE_DISC_TIMEOUT, pppoe_timeout, sc);
+  return err;
+}
+
+/* disconnect */
+void
+pppoe_disconnect(struct pppoe_softc *sc)
+{
+  if (sc->sc_state < PPPOE_STATE_SESSION) {
+    return;
+  }
+  /*
+   * Do not call pppoe_disconnect here, the upper layer state
+   * machine gets confused by this. We must return from this
+   * function and defer disconnecting to the timeout handler.
+   */
+  sc->sc_state = PPPOE_STATE_CLOSING;
+  tcpip_timeout(20, pppoe_timeout, sc);
+}
+
+static int
+pppoe_do_disconnect(struct pppoe_softc *sc)
+{
+  int err;
+
+  if (sc->sc_state < PPPOE_STATE_SESSION) {
+    err = EBUSY;
+  } else {
+    PPPDEBUG((LOG_DEBUG, "pppoe: %c%c%"U16_F": disconnecting\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num));
+    err = pppoe_send_padt(sc->sc_ethif, sc->sc_session, (const u8_t *)&sc->sc_dest);
+  }
+
+  /* cleanup softc */
+  sc->sc_state = PPPOE_STATE_INITIAL;
+  MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest));
+  if (sc->sc_ac_cookie) {
+    mem_free(sc->sc_ac_cookie);
+    sc->sc_ac_cookie = NULL;
+  }
+  sc->sc_ac_cookie_len = 0;
+#ifdef PPPOE_SERVER
+  if (sc->sc_hunique) {
+    mem_free(sc->sc_hunique);
+    sc->sc_hunique = NULL;
+  }
+  sc->sc_hunique_len = 0;
+#endif
+  sc->sc_session = 0;
+
+  sc->sc_linkStatusCB(sc->sc_pd, 0); /* notify upper layers */
+
+  return err;
+}
+
+/* Connection attempt aborted */
+static void
+pppoe_abort_connect(struct pppoe_softc *sc)
+{
+  printf("%c%c%"U16_F": could not establish connection\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num);
+  sc->sc_state = PPPOE_STATE_CLOSING;
+
+  sc->sc_linkStatusCB(sc->sc_pd, 0); /* notify upper layers */
+
+  /* clear connection state */
+  MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest));
+  sc->sc_state = PPPOE_STATE_INITIAL;
+}
+
+/* Send a PADR packet */
+static err_t
+pppoe_send_padr(struct pppoe_softc *sc)
+{
+  struct pbuf *pb;
+  u8_t *p;
+  size_t len, l1 = 0; /* XXX: gcc */
+
+  if (sc->sc_state != PPPOE_STATE_PADR_SENT) {
+    return ERR_CONN;
+  }
+
+  len = 2 + 2 + 2 + 2 + sizeof(sc);    /* service name, host unique */
+  if (sc->sc_service_name != NULL) {    /* service name tag maybe empty */
+    l1 = strlen(sc->sc_service_name);
+    len += l1;
+  }
+  if (sc->sc_ac_cookie_len > 0) {
+    len += 2 + 2 + sc->sc_ac_cookie_len;  /* AC cookie */
+  }
+  pb = pbuf_alloc(PBUF_LINK, sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len, PBUF_RAM);
+  if (!pb) {
+    return ERR_MEM;
+  }
+  p = (u8_t*)pb->payload + sizeof (struct eth_hdr);
+  PPPOE_ADD_HEADER(p, PPPOE_CODE_PADR, 0, len);
+  PPPOE_ADD_16(p, PPPOE_TAG_SNAME);
+  if (sc->sc_service_name != NULL) {
+    PPPOE_ADD_16(p, l1);
+    MEMCPY(p, sc->sc_service_name, l1);
+    p += l1;
+  } else {
+    PPPOE_ADD_16(p, 0);
+  }
+  if (sc->sc_ac_cookie_len > 0) {
+    PPPOE_ADD_16(p, PPPOE_TAG_ACCOOKIE);
+    PPPOE_ADD_16(p, sc->sc_ac_cookie_len);
+    MEMCPY(p, sc->sc_ac_cookie, sc->sc_ac_cookie_len);
+    p += sc->sc_ac_cookie_len;
+  }
+  PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE);
+  PPPOE_ADD_16(p, sizeof(sc));
+  MEMCPY(p, &sc, sizeof sc);
+
+  return pppoe_output(sc, pb);
+}
+
+/* send a PADT packet */
+static err_t
+pppoe_send_padt(struct netif *outgoing_if, u_int session, const u8_t *dest)
+{
+  struct pbuf *pb;
+  struct eth_hdr *ethhdr;
+  err_t res;
+  u8_t *p;
+
+  pb = pbuf_alloc(PBUF_LINK, sizeof(struct eth_hdr) + PPPOE_HEADERLEN, PBUF_RAM);
+  if (!pb) {
+    return ERR_MEM;
+  }
+
+  ethhdr = (struct eth_hdr *)pb->payload;
+  ethhdr->type = htons(ETHTYPE_PPPOEDISC);
+  MEMCPY(ethhdr->dest.addr, dest, sizeof(ethhdr->dest.addr));
+  MEMCPY(ethhdr->src.addr, ((struct eth_addr *)outgoing_if->hwaddr)->addr, sizeof(ethhdr->src.addr));
+
+  p = (u8_t*)(ethhdr + 1);
+  PPPOE_ADD_HEADER(p, PPPOE_CODE_PADT, session, 0);
+
+  res = outgoing_if->linkoutput(outgoing_if, pb);
+
+  pbuf_free(pb);
+
+  return res;
+}
+
+#ifdef PPPOE_SERVER
+static err_t
+pppoe_send_pado(struct pppoe_softc *sc)
+{
+  struct pbuf *pb;
+  u8_t *p;
+  size_t len;
+
+  if (sc->sc_state != PPPOE_STATE_PADO_SENT) {
+    return ERR_CONN;
+  }
+
+  /* calc length */
+  len = 0;
+  /* include ac_cookie */
+  len += 2 + 2 + sizeof(sc);
+  /* include hunique */
+  len += 2 + 2 + sc->sc_hunique_len;
+  pb = pbuf_alloc(PBUF_LINK, sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len, PBUF_RAM);
+  if (!pb) {
+    return ERR_MEM;
+  }
+  p = (u8_t*)pb->payload + sizeof (struct eth_hdr);
+  PPPOE_ADD_HEADER(p, PPPOE_CODE_PADO, 0, len);
+  PPPOE_ADD_16(p, PPPOE_TAG_ACCOOKIE);
+  PPPOE_ADD_16(p, sizeof(sc));
+  MEMCPY(p, &sc, sizeof(sc));
+  p += sizeof(sc);
+  PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE);
+  PPPOE_ADD_16(p, sc->sc_hunique_len);
+  MEMCPY(p, sc->sc_hunique, sc->sc_hunique_len);
+  return pppoe_output(sc, pb);
+}
+
+static err_t
+pppoe_send_pads(struct pppoe_softc *sc)
+{
+  struct pbuf *pb;
+  u8_t *p;
+  size_t len, l1 = 0;  /* XXX: gcc */
+
+  if (sc->sc_state != PPPOE_STATE_PADO_SENT) {
+    return ERR_CONN;
+  }
+
+  sc->sc_session = mono_time.tv_sec % 0xff + 1;
+  /* calc length */
+  len = 0;
+  /* include hunique */
+  len += 2 + 2 + 2 + 2 + sc->sc_hunique_len;  /* service name, host unique*/
+  if (sc->sc_service_name != NULL) {    /* service name tag maybe empty */
+    l1 = strlen(sc->sc_service_name);
+    len += l1;
+  }
+  pb = pbuf_alloc(PBUF_LINK, sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len, PBUF_RAM);
+  if (!pb) {
+    return ERR_MEM;
+  }
+  p = (u8_t*)pb->payload + sizeof (struct eth_hdr);
+  PPPOE_ADD_HEADER(p, PPPOE_CODE_PADS, sc->sc_session, len);
+  PPPOE_ADD_16(p, PPPOE_TAG_SNAME);
+  if (sc->sc_service_name != NULL) {
+    PPPOE_ADD_16(p, l1);
+    MEMCPY(p, sc->sc_service_name, l1);
+    p += l1;
+  } else {
+    PPPOE_ADD_16(p, 0);
+  }
+  PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE);
+  PPPOE_ADD_16(p, sc->sc_hunique_len);
+  MEMCPY(p, sc->sc_hunique, sc->sc_hunique_len);
+  return pppoe_output(sc, pb);
+}
+#endif
+
+err_t
+pppoe_xmit(struct pppoe_softc *sc, struct pbuf *pb)
+{
+  u8_t *p;
+  size_t len;
+
+  /* are we ready to process data yet? */
+  if (sc->sc_state < PPPOE_STATE_SESSION) {
+    /*sppp_flush(&sc->sc_sppp.pp_if);*/
+    pbuf_free(pb);
+    return ERR_CONN;
+  }
+
+  len = pb->tot_len;
+
+  /* make room for Ethernet header - should not fail */
+  if (pbuf_header(pb, sizeof(struct eth_hdr) + PPPOE_HEADERLEN) != 0) {
+    /* bail out */
+    PPPDEBUG((LOG_ERR, "pppoe: %c%c%"U16_F": pppoe_xmit: could not allocate room for header\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num));
+    LINK_STATS_INC(link.lenerr);
+    pbuf_free(pb);
+    return ERR_BUF;
+  } 
+
+  p = (u8_t*)pb->payload + sizeof(struct eth_hdr);
+  PPPOE_ADD_HEADER(p, 0, sc->sc_session, len);
+
+  return pppoe_output(sc, pb);
+}
+
+#if 0 /*def PFIL_HOOKS*/
+static int
+pppoe_ifattach_hook(void *arg, struct pbuf **mp, struct netif *ifp, int dir)
+{
+  struct pppoe_softc *sc;
+  int s;
+
+  if (mp != (struct pbuf **)PFIL_IFNET_DETACH) {
+    return 0;
+  }
+
+  LIST_FOREACH(sc, &pppoe_softc_list, sc_list) {
+    if (sc->sc_ethif != ifp) {
+      continue;
+    }
+    if (sc->sc_sppp.pp_if.if_flags & IFF_UP) {
+      sc->sc_sppp.pp_if.if_flags &= ~(IFF_UP|IFF_RUNNING);
+      printf("%c%c%"U16_F": ethernet interface detached, going down\n",
+          sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num);
+    }
+    sc->sc_ethif = NULL;
+    pppoe_clear_softc(sc, "ethernet interface detached");
+  }
+
+  return 0;
+}
+#endif
+
+static void
+pppoe_clear_softc(struct pppoe_softc *sc, const char *message)
+{
+  LWIP_UNUSED_ARG(message);
+
+  /* stop timer */
+  tcpip_untimeout(pppoe_timeout, sc);
+  PPPDEBUG((LOG_DEBUG, "pppoe: %c%c%"U16_F": session 0x%x terminated, %s\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, sc->sc_session, message));
+
+  /* fix our state */
+  sc->sc_state = PPPOE_STATE_INITIAL;
+
+  /* notify upper layers */
+  sc->sc_linkStatusCB(sc->sc_pd, 0);
+
+  /* clean up softc */
+  MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest));
+  if (sc->sc_ac_cookie) {
+    mem_free(sc->sc_ac_cookie);
+    sc->sc_ac_cookie = NULL;
+  }
+  sc->sc_ac_cookie_len = 0;
+  sc->sc_session = 0;
+}
+
+#endif /* PPPOE_SUPPORT */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/pppdebug.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/pppdebug.h
new file mode 100644
index 0000000..77b8d1f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/pppdebug.h
@@ -0,0 +1,86 @@
+/*****************************************************************************
+* pppdebug.h - System debugging utilities.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+* portions Copyright (c) 2001 by Cognizant Pty Ltd.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY (please don't use tabs!)
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-07-29 Guy Lancaster , Global Election Systems Inc.
+*   Original.
+*
+*****************************************************************************
+*/
+#ifndef PPPDEBUG_H
+#define PPPDEBUG_H
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+/* Trace levels. */
+typedef enum {
+LOG_CRITICAL = 0,
+LOG_ERR      = 1,
+LOG_NOTICE   = 2,
+LOG_WARNING  = 3,
+LOG_INFO     = 5,
+LOG_DETAIL   = 6,
+LOG_DEBUG    = 7
+} LogCodes;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+/*
+ * ppp_trace - a form of printf to send tracing information to stderr
+ */
+void ppp_trace(int level, const char *format,...);
+
+#define TRACELCP PPP_DEBUG
+
+#if PPP_DEBUG
+
+#define AUTHDEBUG(a) ppp_trace a
+#define IPCPDEBUG(a) ppp_trace a
+#define UPAPDEBUG(a) ppp_trace a
+#define LCPDEBUG(a)  ppp_trace a
+#define FSMDEBUG(a)  ppp_trace a
+#define CHAPDEBUG(a) ppp_trace a
+#define PPPDEBUG(a)  ppp_trace a
+
+#else /* PPP_DEBUG */
+
+#define AUTHDEBUG(a)
+#define IPCPDEBUG(a)
+#define UPAPDEBUG(a)
+#define LCPDEBUG(a)
+#define FSMDEBUG(a)
+#define CHAPDEBUG(a)
+#define PPPDEBUG(a)
+
+#endif /* PPP_DEBUG */
+
+#endif /* PPPDEBUG_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/randm.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/randm.c
new file mode 100644
index 0000000..b6c974c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/randm.c
@@ -0,0 +1,248 @@
+/*****************************************************************************
+* randm.c - Random number generator program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1998 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-06-03 Guy Lancaster , Global Election Systems Inc.
+*   Extracted from avos.
+*****************************************************************************/
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "md5.h"
+#include "randm.h"
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+
+#if MD5_SUPPORT /* this module depends on MD5 */
+#define RANDPOOLSZ 16   /* Bytes stored in the pool of randomness. */
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static char randPool[RANDPOOLSZ];   /* Pool of randomness. */
+static long randCount = 0;      /* Pseudo-random incrementer */
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * Initialize the random number generator.
+ *
+ * Since this is to be called on power up, we don't have much
+ *  system randomess to work with.  Here all we use is the
+ *  real-time clock.  We'll accumulate more randomness as soon
+ *  as things start happening.
+ */
+void
+avRandomInit()
+{
+  avChurnRand(NULL, 0);
+}
+
+/*
+ * Churn the randomness pool on a random event.  Call this early and often
+ *  on random and semi-random system events to build randomness in time for
+ *  usage.  For randomly timed events, pass a null pointer and a zero length
+ *  and this will use the system timer and other sources to add randomness.
+ *  If new random data is available, pass a pointer to that and it will be
+ *  included.
+ *
+ * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427
+ */
+void
+avChurnRand(char *randData, u32_t randLen)
+{
+  MD5_CTX md5;
+
+  /* ppp_trace(LOG_INFO, "churnRand: %u@%P\n", randLen, randData); */
+  MD5Init(&md5);
+  MD5Update(&md5, (u_char *)randPool, sizeof(randPool));
+  if (randData) {
+    MD5Update(&md5, (u_char *)randData, randLen);
+  } else {
+    struct {
+      /* INCLUDE fields for any system sources of randomness */
+      char foobar;
+    } sysData;
+
+    /* Load sysData fields here. */
+    MD5Update(&md5, (u_char *)&sysData, sizeof(sysData));
+  }
+  MD5Final((u_char *)randPool, &md5);
+/*  ppp_trace(LOG_INFO, "churnRand: -> 0\n"); */
+}
+
+/*
+ * Use the random pool to generate random data.  This degrades to pseudo
+ *  random when used faster than randomness is supplied using churnRand().
+ * Note: It's important that there be sufficient randomness in randPool
+ *  before this is called for otherwise the range of the result may be
+ *  narrow enough to make a search feasible.
+ *
+ * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427
+ *
+ * XXX Why does he not just call churnRand() for each block?  Probably
+ *  so that you don't ever publish the seed which could possibly help
+ *  predict future values.
+ * XXX Why don't we preserve md5 between blocks and just update it with
+ *  randCount each time?  Probably there is a weakness but I wish that
+ *  it was documented.
+ */
+void
+avGenRand(char *buf, u32_t bufLen)
+{
+  MD5_CTX md5;
+  u_char tmp[16];
+  u32_t n;
+
+  while (bufLen > 0) {
+    n = LWIP_MIN(bufLen, RANDPOOLSZ);
+    MD5Init(&md5);
+    MD5Update(&md5, (u_char *)randPool, sizeof(randPool));
+    MD5Update(&md5, (u_char *)&randCount, sizeof(randCount));
+    MD5Final(tmp, &md5);
+    randCount++;
+    MEMCPY(buf, tmp, n);
+    buf += n;
+    bufLen -= n;
+  }
+}
+
+/*
+ * Return a new random number.
+ */
+u32_t
+avRandom()
+{
+  u32_t newRand;
+
+  avGenRand((char *)&newRand, sizeof(newRand));
+
+  return newRand;
+}
+
+#else /* MD5_SUPPORT */
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static int  avRandomized = 0;       /* Set when truely randomized. */
+static u32_t avRandomSeed = 0;      /* Seed used for random number generation. */
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * Initialize the random number generator.
+ *
+ * Here we attempt to compute a random number seed but even if
+ * it isn't random, we'll randomize it later.
+ *
+ * The current method uses the fields from the real time clock,
+ * the idle process counter, the millisecond counter, and the
+ * hardware timer tick counter.  When this is invoked
+ * in startup(), then the idle counter and timer values may
+ * repeat after each boot and the real time clock may not be
+ * operational.  Thus we call it again on the first random
+ * event.
+ */
+void
+avRandomInit()
+{
+#if 0
+  /* Get a pointer into the last 4 bytes of clockBuf. */
+  u32_t *lptr1 = (u32_t *)((char *)&clockBuf[3]);
+
+  /*
+   * Initialize our seed using the real-time clock, the idle
+   * counter, the millisecond timer, and the hardware timer
+   * tick counter.  The real-time clock and the hardware
+   * tick counter are the best sources of randomness but
+   * since the tick counter is only 16 bit (and truncated
+   * at that), the idle counter and millisecond timer
+   * (which may be small values) are added to help
+   * randomize the lower 16 bits of the seed.
+   */
+  readClk();
+  avRandomSeed += *(u32_t *)clockBuf + *lptr1 + OSIdleCtr
+           + ppp_mtime() + ((u32_t)TM1 << 16) + TM1;
+#else
+  avRandomSeed += sys_jiffies(); /* XXX */
+#endif
+
+  /* Initialize the Borland random number generator. */
+  srand((unsigned)avRandomSeed);
+}
+
+/*
+ * Randomize our random seed value.  Here we use the fact that
+ * this function is called at *truely random* times by the polling
+ * and network functions.  Here we only get 16 bits of new random
+ * value but we use the previous value to randomize the other 16
+ * bits.
+ */
+void
+avRandomize(void)
+{
+  static u32_t last_jiffies;
+
+  if (!avRandomized) {
+    avRandomized = !0;
+    avRandomInit();
+    /* The initialization function also updates the seed. */
+  } else {
+    /* avRandomSeed += (avRandomSeed << 16) + TM1; */
+    avRandomSeed += (sys_jiffies() - last_jiffies); /* XXX */
+  }
+  last_jiffies = sys_jiffies();
+}
+
+/*
+ * Return a new random number.
+ * Here we use the Borland rand() function to supply a pseudo random
+ * number which we make truely random by combining it with our own
+ * seed which is randomized by truely random events. 
+ * Thus the numbers will be truely random unless there have been no
+ * operator or network events in which case it will be pseudo random
+ * seeded by the real time clock.
+ */
+u32_t
+avRandom()
+{
+  return ((((u32_t)rand() << 16) + rand()) + avRandomSeed);
+}
+
+#endif /* MD5_SUPPORT */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/randm.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/randm.h
new file mode 100644
index 0000000..5fb99ef
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/randm.h
@@ -0,0 +1,81 @@
+/*****************************************************************************
+* randm.h - Random number generator header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-05-29 Guy Lancaster , Global Election Systems Inc.
+*   Extracted from avos.
+*****************************************************************************/
+
+#ifndef RANDM_H
+#define RANDM_H
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+/*
+ * Initialize the random number generator.
+ */
+void avRandomInit(void);
+
+/*
+ * Churn the randomness pool on a random event.  Call this early and often
+ * on random and semi-random system events to build randomness in time for
+ * usage.  For randomly timed events, pass a null pointer and a zero length
+ * and this will use the system timer and other sources to add randomness.
+ * If new random data is available, pass a pointer to that and it will be
+ * included.
+ */
+void avChurnRand(char *randData, u32_t randLen);
+
+/*
+ * Randomize our random seed value.  To be called for truely random events
+ * such as user operations and network traffic.
+ */
+#if MD5_SUPPORT
+#define avRandomize() avChurnRand(NULL, 0)
+#else  /* MD5_SUPPORT */
+void avRandomize(void);
+#endif /* MD5_SUPPORT */
+
+/*
+ * Use the random pool to generate random data.  This degrades to pseudo
+ * random when used faster than randomness is supplied using churnRand().
+ * Thus it's important to make sure that the results of this are not
+ * published directly because one could predict the next result to at
+ * least some degree.  Also, it's important to get a good seed before
+ * the first use.
+ */
+void avGenRand(char *buf, u32_t bufLen);
+
+/*
+ * Return a new random number.
+ */
+u32_t avRandom(void);
+
+
+#endif /* RANDM_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/vj.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/vj.c
new file mode 100644
index 0000000..eba7da9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/vj.c
@@ -0,0 +1,660 @@
+/*
+ * Routines to compress and uncompess tcp packets (for transmission
+ * over low speed serial lines.
+ *
+ * Copyright (c) 1989 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Berkeley.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
+ *   Initial distribution.
+ *
+ * Modified June 1993 by Paul Mackerras, paulus@cs.anu.edu.au,
+ * so that the entire packet being decompressed doesn't have
+ * to be in contiguous memory (just the compressed header).
+ *
+ * Modified March 1998 by Guy Lancaster, glanca@gesn.com,
+ * for a 16 bit processor.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "vj.h"
+
+#include 
+
+#if VJ_SUPPORT
+
+#if LINK_STATS
+#define INCR(counter) ++comp->stats.counter
+#else
+#define INCR(counter)
+#endif
+
+#if defined(NO_CHAR_BITFIELDS)
+#define getip_hl(base)  ((base).ip_hl_v&0xf)
+#define getth_off(base) (((base).th_x2_off&0xf0)>>4)
+#else
+#define getip_hl(base)  ((base).ip_hl)
+#define getth_off(base) ((base).th_off)
+#endif
+
+void
+vj_compress_init(struct vjcompress *comp)
+{
+  register u_int i;
+  register struct cstate *tstate = comp->tstate;
+  
+#if MAX_SLOTS == 0
+  memset((char *)comp, 0, sizeof(*comp));
+#endif
+  comp->maxSlotIndex = MAX_SLOTS - 1;
+  comp->compressSlot = 0;    /* Disable slot ID compression by default. */
+  for (i = MAX_SLOTS - 1; i > 0; --i) {
+    tstate[i].cs_id = i;
+    tstate[i].cs_next = &tstate[i - 1];
+  }
+  tstate[0].cs_next = &tstate[MAX_SLOTS - 1];
+  tstate[0].cs_id = 0;
+  comp->last_cs = &tstate[0];
+  comp->last_recv = 255;
+  comp->last_xmit = 255;
+  comp->flags = VJF_TOSS;
+}
+
+
+/* ENCODE encodes a number that is known to be non-zero.  ENCODEZ
+ * checks for zero (since zero has to be encoded in the long, 3 byte
+ * form).
+ */
+#define ENCODE(n) { \
+  if ((u_short)(n) >= 256) { \
+    *cp++ = 0; \
+    cp[1] = (n); \
+    cp[0] = (n) >> 8; \
+    cp += 2; \
+  } else { \
+    *cp++ = (n); \
+  } \
+}
+#define ENCODEZ(n) { \
+  if ((u_short)(n) >= 256 || (u_short)(n) == 0) { \
+    *cp++ = 0; \
+    cp[1] = (n); \
+    cp[0] = (n) >> 8; \
+    cp += 2; \
+  } else { \
+    *cp++ = (n); \
+  } \
+}
+
+#define DECODEL(f) { \
+  if (*cp == 0) {\
+    u32_t tmp = ntohl(f) + ((cp[1] << 8) | cp[2]); \
+    (f) = htonl(tmp); \
+    cp += 3; \
+  } else { \
+    u32_t tmp = ntohl(f) + (u32_t)*cp++; \
+    (f) = htonl(tmp); \
+  } \
+}
+
+#define DECODES(f) { \
+  if (*cp == 0) {\
+    u_short tmp = ntohs(f) + (((u_short)cp[1] << 8) | cp[2]); \
+    (f) = htons(tmp); \
+    cp += 3; \
+  } else { \
+    u_short tmp = ntohs(f) + (u_short)*cp++; \
+    (f) = htons(tmp); \
+  } \
+}
+
+#define DECODEU(f) { \
+  if (*cp == 0) {\
+    (f) = htons(((u_short)cp[1] << 8) | cp[2]); \
+    cp += 3; \
+  } else { \
+    (f) = htons((u_short)*cp++); \
+  } \
+}
+
+/*
+ * vj_compress_tcp - Attempt to do Van Jacobsen header compression on a
+ * packet.  This assumes that nb and comp are not null and that the first
+ * buffer of the chain contains a valid IP header.
+ * Return the VJ type code indicating whether or not the packet was
+ * compressed.
+ */
+u_int
+vj_compress_tcp(struct vjcompress *comp, struct pbuf *pb)
+{
+  register struct ip *ip = (struct ip *)pb->payload;
+  register struct cstate *cs = comp->last_cs->cs_next;
+  register u_short hlen = getip_hl(*ip);
+  register struct tcphdr *oth;
+  register struct tcphdr *th;
+  register u_short deltaS, deltaA;
+  register u_long deltaL;
+  register u_int changes = 0;
+  u_char new_seq[16];
+  register u_char *cp = new_seq;
+
+  /*  
+   * Check that the packet is IP proto TCP.
+   */
+  if (ip->ip_p != IPPROTO_TCP) {
+    return (TYPE_IP);
+  }
+
+  /*
+   * Bail if this is an IP fragment or if the TCP packet isn't
+   * `compressible' (i.e., ACK isn't set or some other control bit is
+   * set).  
+   */
+  if ((ip->ip_off & htons(0x3fff)) || pb->tot_len < 40) {
+    return (TYPE_IP);
+  }
+  th = (struct tcphdr *)&((long *)ip)[hlen];
+  if ((th->th_flags & (TCP_SYN|TCP_FIN|TCP_RST|TCP_ACK)) != TCP_ACK) {
+    return (TYPE_IP);
+  }
+  /*
+   * Packet is compressible -- we're going to send either a
+   * COMPRESSED_TCP or UNCOMPRESSED_TCP packet.  Either way we need
+   * to locate (or create) the connection state.  Special case the
+   * most recently used connection since it's most likely to be used
+   * again & we don't have to do any reordering if it's used.
+   */
+  INCR(vjs_packets);
+  if (ip->ip_src.s_addr != cs->cs_ip.ip_src.s_addr 
+      || ip->ip_dst.s_addr != cs->cs_ip.ip_dst.s_addr 
+      || *(long *)th != ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)]) {
+    /*
+     * Wasn't the first -- search for it.
+     *
+     * States are kept in a circularly linked list with
+     * last_cs pointing to the end of the list.  The
+     * list is kept in lru order by moving a state to the
+     * head of the list whenever it is referenced.  Since
+     * the list is short and, empirically, the connection
+     * we want is almost always near the front, we locate
+     * states via linear search.  If we don't find a state
+     * for the datagram, the oldest state is (re-)used.
+     */
+    register struct cstate *lcs;
+    register struct cstate *lastcs = comp->last_cs;
+    
+    do {
+      lcs = cs; cs = cs->cs_next;
+      INCR(vjs_searches);
+      if (ip->ip_src.s_addr == cs->cs_ip.ip_src.s_addr
+          && ip->ip_dst.s_addr == cs->cs_ip.ip_dst.s_addr
+          && *(long *)th == ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)]) {
+        goto found;
+      }
+    } while (cs != lastcs);
+
+    /*
+     * Didn't find it -- re-use oldest cstate.  Send an
+     * uncompressed packet that tells the other side what
+     * connection number we're using for this conversation.
+     * Note that since the state list is circular, the oldest
+     * state points to the newest and we only need to set
+     * last_cs to update the lru linkage.
+     */
+    INCR(vjs_misses);
+    comp->last_cs = lcs;
+    hlen += getth_off(*th);
+    hlen <<= 2;
+    /* Check that the IP/TCP headers are contained in the first buffer. */
+    if (hlen > pb->len) {
+      return (TYPE_IP);
+    }
+    goto uncompressed;
+
+    found:
+    /*
+     * Found it -- move to the front on the connection list.
+     */
+    if (cs == lastcs) {
+      comp->last_cs = lcs;
+    } else {
+      lcs->cs_next = cs->cs_next;
+      cs->cs_next = lastcs->cs_next;
+      lastcs->cs_next = cs;
+    }
+  }
+
+  oth = (struct tcphdr *)&((long *)&cs->cs_ip)[hlen];
+  deltaS = hlen;
+  hlen += getth_off(*th);
+  hlen <<= 2;
+  /* Check that the IP/TCP headers are contained in the first buffer. */
+  if (hlen > pb->len) {
+    PPPDEBUG((LOG_INFO, "vj_compress_tcp: header len %d spans buffers\n", hlen));
+    return (TYPE_IP);
+  }
+
+  /*
+   * Make sure that only what we expect to change changed. The first
+   * line of the `if' checks the IP protocol version, header length &
+   * type of service.  The 2nd line checks the "Don't fragment" bit.
+   * The 3rd line checks the time-to-live and protocol (the protocol
+   * check is unnecessary but costless).  The 4th line checks the TCP
+   * header length.  The 5th line checks IP options, if any.  The 6th
+   * line checks TCP options, if any.  If any of these things are
+   * different between the previous & current datagram, we send the
+   * current datagram `uncompressed'.
+   */
+  if (((u_short *)ip)[0] != ((u_short *)&cs->cs_ip)[0] 
+      || ((u_short *)ip)[3] != ((u_short *)&cs->cs_ip)[3] 
+      || ((u_short *)ip)[4] != ((u_short *)&cs->cs_ip)[4] 
+      || getth_off(*th) != getth_off(*oth) 
+      || (deltaS > 5 && BCMP(ip + 1, &cs->cs_ip + 1, (deltaS - 5) << 2)) 
+      || (getth_off(*th) > 5 && BCMP(th + 1, oth + 1, (getth_off(*th) - 5) << 2))) {
+    goto uncompressed;
+  }
+
+  /*
+   * Figure out which of the changing fields changed.  The
+   * receiver expects changes in the order: urgent, window,
+   * ack, seq (the order minimizes the number of temporaries
+   * needed in this section of code).
+   */
+  if (th->th_flags & TCP_URG) {
+    deltaS = ntohs(th->th_urp);
+    ENCODEZ(deltaS);
+    changes |= NEW_U;
+  } else if (th->th_urp != oth->th_urp) {
+    /* argh! URG not set but urp changed -- a sensible
+     * implementation should never do this but RFC793
+     * doesn't prohibit the change so we have to deal
+     * with it. */
+    goto uncompressed;
+  }
+
+  if ((deltaS = (u_short)(ntohs(th->th_win) - ntohs(oth->th_win))) != 0) {
+    ENCODE(deltaS);
+    changes |= NEW_W;
+  }
+
+  if ((deltaL = ntohl(th->th_ack) - ntohl(oth->th_ack)) != 0) {
+    if (deltaL > 0xffff) {
+      goto uncompressed;
+    }
+    deltaA = (u_short)deltaL;
+    ENCODE(deltaA);
+    changes |= NEW_A;
+  }
+
+  if ((deltaL = ntohl(th->th_seq) - ntohl(oth->th_seq)) != 0) {
+    if (deltaL > 0xffff) {
+      goto uncompressed;
+    }
+    deltaS = (u_short)deltaL;
+    ENCODE(deltaS);
+    changes |= NEW_S;
+  }
+
+  switch(changes) {
+  case 0:
+    /*
+     * Nothing changed. If this packet contains data and the
+     * last one didn't, this is probably a data packet following
+     * an ack (normal on an interactive connection) and we send
+     * it compressed.  Otherwise it's probably a retransmit,
+     * retransmitted ack or window probe.  Send it uncompressed
+     * in case the other side missed the compressed version.
+     */
+    if (ip->ip_len != cs->cs_ip.ip_len &&
+      ntohs(cs->cs_ip.ip_len) == hlen) {
+      break;
+    }
+
+  /* (fall through) */
+
+  case SPECIAL_I:
+  case SPECIAL_D:
+    /*
+     * actual changes match one of our special case encodings --
+     * send packet uncompressed.
+     */
+    goto uncompressed;
+
+  case NEW_S|NEW_A:
+    if (deltaS == deltaA && deltaS == ntohs(cs->cs_ip.ip_len) - hlen) {
+      /* special case for echoed terminal traffic */
+      changes = SPECIAL_I;
+      cp = new_seq;
+    }
+    break;
+
+  case NEW_S:
+    if (deltaS == ntohs(cs->cs_ip.ip_len) - hlen) {
+      /* special case for data xfer */
+      changes = SPECIAL_D;
+      cp = new_seq;
+    }
+    break;
+  }
+
+  deltaS = (u_short)(ntohs(ip->ip_id) - ntohs(cs->cs_ip.ip_id));
+  if (deltaS != 1) {
+    ENCODEZ(deltaS);
+    changes |= NEW_I;
+  }
+  if (th->th_flags & TCP_PSH) {
+    changes |= TCP_PUSH_BIT;
+  }
+  /*
+   * Grab the cksum before we overwrite it below.  Then update our
+   * state with this packet's header.
+   */
+  deltaA = ntohs(th->th_sum);
+  BCOPY(ip, &cs->cs_ip, hlen);
+
+  /*
+   * We want to use the original packet as our compressed packet.
+   * (cp - new_seq) is the number of bytes we need for compressed
+   * sequence numbers.  In addition we need one byte for the change
+   * mask, one for the connection id and two for the tcp checksum.
+   * So, (cp - new_seq) + 4 bytes of header are needed.  hlen is how
+   * many bytes of the original packet to toss so subtract the two to
+   * get the new packet size.
+   */
+  deltaS = (u_short)(cp - new_seq);
+  if (!comp->compressSlot || comp->last_xmit != cs->cs_id) {
+    comp->last_xmit = cs->cs_id;
+    hlen -= deltaS + 4;
+    if(pbuf_header(pb, -hlen)){
+      /* Can we cope with this failing?  Just assert for now */
+      LWIP_ASSERT("pbuf_header failed\n", 0);
+    }
+    cp = (u_char *)pb->payload;
+    *cp++ = changes | NEW_C;
+    *cp++ = cs->cs_id;
+  } else {
+    hlen -= deltaS + 3;
+    if(pbuf_header(pb, -hlen)) {
+      /* Can we cope with this failing?  Just assert for now */
+      LWIP_ASSERT("pbuf_header failed\n", 0);
+    }
+    cp = (u_char *)pb->payload;
+    *cp++ = changes;
+  }
+  *cp++ = deltaA >> 8;
+  *cp++ = deltaA;
+  BCOPY(new_seq, cp, deltaS);
+  INCR(vjs_compressed);
+  return (TYPE_COMPRESSED_TCP);
+
+  /*
+   * Update connection state cs & send uncompressed packet (that is,
+   * a regular ip/tcp packet but with the 'conversation id' we hope
+   * to use on future compressed packets in the protocol field).
+   */
+uncompressed:
+  BCOPY(ip, &cs->cs_ip, hlen);
+  ip->ip_p = cs->cs_id;
+  comp->last_xmit = cs->cs_id;
+  return (TYPE_UNCOMPRESSED_TCP);
+}
+
+/*
+ * Called when we may have missed a packet.
+ */
+void
+vj_uncompress_err(struct vjcompress *comp)
+{
+  comp->flags |= VJF_TOSS;
+  INCR(vjs_errorin);
+}
+
+/*
+ * "Uncompress" a packet of type TYPE_UNCOMPRESSED_TCP.
+ * Return 0 on success, -1 on failure.
+ */
+int
+vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp)
+{
+  register u_int hlen;
+  register struct cstate *cs;
+  register struct ip *ip;
+  
+  ip = (struct ip *)nb->payload;
+  hlen = getip_hl(*ip) << 2;
+  if (ip->ip_p >= MAX_SLOTS
+      || hlen + sizeof(struct tcphdr) > nb->len
+      || (hlen += getth_off(*((struct tcphdr *)&((char *)ip)[hlen])) << 2)
+          > nb->len
+      || hlen > MAX_HDR) {
+    PPPDEBUG((LOG_INFO, "vj_uncompress_uncomp: bad cid=%d, hlen=%d buflen=%d\n", 
+          ip->ip_p, hlen, nb->len));
+    comp->flags |= VJF_TOSS;
+    INCR(vjs_errorin);
+    return -1;
+  }
+  cs = &comp->rstate[comp->last_recv = ip->ip_p];
+  comp->flags &=~ VJF_TOSS;
+  ip->ip_p = IPPROTO_TCP;
+  BCOPY(ip, &cs->cs_ip, hlen);
+  cs->cs_hlen = hlen;
+  INCR(vjs_uncompressedin);
+  return 0;
+}
+
+/*
+ * Uncompress a packet of type TYPE_COMPRESSED_TCP.
+ * The packet is composed of a buffer chain and the first buffer
+ * must contain an accurate chain length.
+ * The first buffer must include the entire compressed TCP/IP header. 
+ * This procedure replaces the compressed header with the uncompressed
+ * header and returns the length of the VJ header.
+ */
+int
+vj_uncompress_tcp(struct pbuf **nb, struct vjcompress *comp)
+{
+  u_char *cp;
+  struct tcphdr *th;
+  struct cstate *cs;
+  u_short *bp;
+  struct pbuf *n0 = *nb;
+  u32_t tmp;
+  u_int vjlen, hlen, changes;
+
+  INCR(vjs_compressedin);
+  cp = (u_char *)n0->payload;
+  changes = *cp++;
+  if (changes & NEW_C) {
+    /* 
+     * Make sure the state index is in range, then grab the state.
+     * If we have a good state index, clear the 'discard' flag. 
+     */
+    if (*cp >= MAX_SLOTS) {
+      PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: bad cid=%d\n", *cp));
+      goto bad;
+    }
+
+    comp->flags &=~ VJF_TOSS;
+    comp->last_recv = *cp++;
+  } else {
+    /* 
+     * this packet has an implicit state index.  If we've
+     * had a line error since the last time we got an
+     * explicit state index, we have to toss the packet. 
+     */
+    if (comp->flags & VJF_TOSS) {
+      PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: tossing\n"));
+      INCR(vjs_tossed);
+      return (-1);
+    }
+  }
+  cs = &comp->rstate[comp->last_recv];
+  hlen = getip_hl(cs->cs_ip) << 2;
+  th = (struct tcphdr *)&((u_char *)&cs->cs_ip)[hlen];
+  th->th_sum = htons((*cp << 8) | cp[1]);
+  cp += 2;
+  if (changes & TCP_PUSH_BIT) {
+    th->th_flags |= TCP_PSH;
+  } else {
+    th->th_flags &=~ TCP_PSH;
+  }
+
+  switch (changes & SPECIALS_MASK) {
+  case SPECIAL_I:
+    {
+      register u32_t i = ntohs(cs->cs_ip.ip_len) - cs->cs_hlen;
+      /* some compilers can't nest inline assembler.. */
+      tmp = ntohl(th->th_ack) + i;
+      th->th_ack = htonl(tmp);
+      tmp = ntohl(th->th_seq) + i;
+      th->th_seq = htonl(tmp);
+    }
+    break;
+
+  case SPECIAL_D:
+    /* some compilers can't nest inline assembler.. */
+    tmp = ntohl(th->th_seq) + ntohs(cs->cs_ip.ip_len) - cs->cs_hlen;
+    th->th_seq = htonl(tmp);
+    break;
+
+  default:
+    if (changes & NEW_U) {
+      th->th_flags |= TCP_URG;
+      DECODEU(th->th_urp);
+    } else {
+      th->th_flags &=~ TCP_URG;
+    }
+    if (changes & NEW_W) {
+      DECODES(th->th_win);
+    }
+    if (changes & NEW_A) {
+      DECODEL(th->th_ack);
+    }
+    if (changes & NEW_S) {
+      DECODEL(th->th_seq);
+    }
+    break;
+  }
+  if (changes & NEW_I) {
+    DECODES(cs->cs_ip.ip_id);
+  } else {
+    cs->cs_ip.ip_id = ntohs(cs->cs_ip.ip_id) + 1;
+    cs->cs_ip.ip_id = htons(cs->cs_ip.ip_id);
+  }
+
+  /*
+   * At this point, cp points to the first byte of data in the
+   * packet.  Fill in the IP total length and update the IP
+   * header checksum.
+   */
+  vjlen = (u_short)(cp - (u_char*)n0->payload);
+  if (n0->len < vjlen) {
+    /* 
+     * We must have dropped some characters (crc should detect
+     * this but the old slip framing won't) 
+     */
+    PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: head buffer %d too short %d\n", 
+          n0->len, vjlen));
+    goto bad;
+  }
+
+#if BYTE_ORDER == LITTLE_ENDIAN
+  tmp = n0->tot_len - vjlen + cs->cs_hlen;
+  cs->cs_ip.ip_len = htons(tmp);
+#else
+  cs->cs_ip.ip_len = htons(n0->tot_len - vjlen + cs->cs_hlen);
+#endif
+
+  /* recompute the ip header checksum */
+  bp = (u_short *) &cs->cs_ip;
+  cs->cs_ip.ip_sum = 0;
+  for (tmp = 0; hlen > 0; hlen -= 2) {
+    tmp += *bp++;
+  }
+  tmp = (tmp & 0xffff) + (tmp >> 16);
+  tmp = (tmp & 0xffff) + (tmp >> 16);
+  cs->cs_ip.ip_sum = (u_short)(~tmp);
+  
+  /* Remove the compressed header and prepend the uncompressed header. */
+  if(pbuf_header(n0, -((s16_t)(vjlen)))) {
+    /* Can we cope with this failing?  Just assert for now */
+    LWIP_ASSERT("pbuf_header failed\n", 0);
+    goto bad;
+  }
+
+  if(LWIP_MEM_ALIGN(n0->payload) != n0->payload) {
+    struct pbuf *np, *q;
+    u8_t *bufptr;
+
+    np = pbuf_alloc(PBUF_RAW, n0->len + cs->cs_hlen, PBUF_POOL);
+    if(!np) {
+      PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: realign failed\n"));
+      goto bad;
+    }
+
+    if(pbuf_header(np, -cs->cs_hlen)) {
+      /* Can we cope with this failing?  Just assert for now */
+      LWIP_ASSERT("pbuf_header failed\n", 0);
+      goto bad;
+    }
+
+    bufptr = n0->payload;
+    for(q = np; q != NULL; q = q->next) {
+      MEMCPY(q->payload, bufptr, q->len);
+      bufptr += q->len;
+    }
+
+    if(n0->next) {
+      pbuf_chain(np, n0->next);
+      pbuf_dechain(n0);
+    }
+    pbuf_free(n0);
+    n0 = np;
+  }
+
+  if(pbuf_header(n0, cs->cs_hlen)) {
+    struct pbuf *np;
+
+    LWIP_ASSERT("vj_uncompress_tcp: cs->cs_hlen <= PBUF_POOL_BUFSIZE", cs->cs_hlen <= PBUF_POOL_BUFSIZE);
+    np = pbuf_alloc(PBUF_RAW, cs->cs_hlen, PBUF_POOL);
+    if(!np) {
+      PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: prepend failed\n"));
+      goto bad;
+    }
+    pbuf_cat(np, n0);
+    n0 = np;
+  }
+  LWIP_ASSERT("n0->len >= cs->cs_hlen", n0->len >= cs->cs_hlen);
+  MEMCPY(n0->payload, &cs->cs_ip, cs->cs_hlen);
+
+  *nb = n0;
+
+  return vjlen;
+
+bad:
+  comp->flags |= VJF_TOSS;
+  INCR(vjs_errorin);
+  return (-1);
+}
+
+#endif /* VJ_SUPPORT */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/vj.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/vj.h
new file mode 100644
index 0000000..bc02442
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/vj.h
@@ -0,0 +1,155 @@
+/*
+ * Definitions for tcp compression routines.
+ *
+ * $Id: vj.h,v 1.5 2007/12/19 20:47:23 fbernon Exp $
+ *
+ * Copyright (c) 1989 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Berkeley.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
+ * - Initial distribution.
+ */
+
+#ifndef VJ_H
+#define VJ_H
+
+#include "vjbsdhdr.h"
+
+#define MAX_SLOTS 16 /* must be > 2 and < 256 */
+#define MAX_HDR   128
+
+/*
+ * Compressed packet format:
+ *
+ * The first octet contains the packet type (top 3 bits), TCP
+ * 'push' bit, and flags that indicate which of the 4 TCP sequence
+ * numbers have changed (bottom 5 bits).  The next octet is a
+ * conversation number that associates a saved IP/TCP header with
+ * the compressed packet.  The next two octets are the TCP checksum
+ * from the original datagram.  The next 0 to 15 octets are
+ * sequence number changes, one change per bit set in the header
+ * (there may be no changes and there are two special cases where
+ * the receiver implicitly knows what changed -- see below).
+ * 
+ * There are 5 numbers which can change (they are always inserted
+ * in the following order): TCP urgent pointer, window,
+ * acknowlegement, sequence number and IP ID.  (The urgent pointer
+ * is different from the others in that its value is sent, not the
+ * change in value.)  Since typical use of SLIP links is biased
+ * toward small packets (see comments on MTU/MSS below), changes
+ * use a variable length coding with one octet for numbers in the
+ * range 1 - 255 and 3 octets (0, MSB, LSB) for numbers in the
+ * range 256 - 65535 or 0.  (If the change in sequence number or
+ * ack is more than 65535, an uncompressed packet is sent.)
+ */
+
+/*
+ * Packet types (must not conflict with IP protocol version)
+ *
+ * The top nibble of the first octet is the packet type.  There are
+ * three possible types: IP (not proto TCP or tcp with one of the
+ * control flags set); uncompressed TCP (a normal IP/TCP packet but
+ * with the 8-bit protocol field replaced by an 8-bit connection id --
+ * this type of packet syncs the sender & receiver); and compressed
+ * TCP (described above).
+ *
+ * LSB of 4-bit field is TCP "PUSH" bit (a worthless anachronism) and
+ * is logically part of the 4-bit "changes" field that follows.  Top
+ * three bits are actual packet type.  For backward compatibility
+ * and in the interest of conserving bits, numbers are chosen so the
+ * IP protocol version number (4) which normally appears in this nibble
+ * means "IP packet".
+ */
+
+/* packet types */
+#define TYPE_IP               0x40
+#define TYPE_UNCOMPRESSED_TCP 0x70
+#define TYPE_COMPRESSED_TCP   0x80
+#define TYPE_ERROR            0x00
+
+/* Bits in first octet of compressed packet */
+#define NEW_C 0x40 /* flag bits for what changed in a packet */
+#define NEW_I 0x20
+#define NEW_S 0x08
+#define NEW_A 0x04
+#define NEW_W 0x02
+#define NEW_U 0x01
+
+/* reserved, special-case values of above */
+#define SPECIAL_I (NEW_S|NEW_W|NEW_U) /* echoed interactive traffic */
+#define SPECIAL_D (NEW_S|NEW_A|NEW_W|NEW_U) /* unidirectional data */
+#define SPECIALS_MASK (NEW_S|NEW_A|NEW_W|NEW_U)
+
+#define TCP_PUSH_BIT 0x10
+
+
+/*
+ * "state" data for each active tcp conversation on the wire.  This is
+ * basically a copy of the entire IP/TCP header from the last packet
+ * we saw from the conversation together with a small identifier
+ * the transmit & receive ends of the line use to locate saved header.
+ */
+struct cstate {
+  struct cstate *cs_next; /* next most recently used state (xmit only) */
+  u_short cs_hlen;        /* size of hdr (receive only) */
+  u_char cs_id;           /* connection # associated with this state */
+  u_char cs_filler;
+  union {
+    char csu_hdr[MAX_HDR];
+    struct ip csu_ip;     /* ip/tcp hdr from most recent packet */
+  } vjcs_u;
+};
+#define cs_ip vjcs_u.csu_ip
+#define cs_hdr vjcs_u.csu_hdr
+
+
+struct vjstat {
+  unsigned long vjs_packets;        /* outbound packets */
+  unsigned long vjs_compressed;     /* outbound compressed packets */
+  unsigned long vjs_searches;       /* searches for connection state */
+  unsigned long vjs_misses;         /* times couldn't find conn. state */
+  unsigned long vjs_uncompressedin; /* inbound uncompressed packets */
+  unsigned long vjs_compressedin;   /* inbound compressed packets */
+  unsigned long vjs_errorin;        /* inbound unknown type packets */
+  unsigned long vjs_tossed;         /* inbound packets tossed because of error */
+};
+
+/*
+ * all the state data for one serial line (we need one of these per line).
+ */
+struct vjcompress {
+  struct cstate *last_cs;          /* most recently used tstate */
+  u_char last_recv;                /* last rcvd conn. id */
+  u_char last_xmit;                /* last sent conn. id */
+  u_short flags;
+  u_char maxSlotIndex;
+  u_char compressSlot;             /* Flag indicating OK to compress slot ID. */
+#if LINK_STATS
+  struct vjstat stats;
+#endif
+  struct cstate tstate[MAX_SLOTS]; /* xmit connection states */
+  struct cstate rstate[MAX_SLOTS]; /* receive connection states */
+};
+
+/* flag values */
+#define VJF_TOSS 1U /* tossing rcvd frames because of input err */
+
+extern void  vj_compress_init    (struct vjcompress *comp);
+extern u_int vj_compress_tcp     (struct vjcompress *comp, struct pbuf *pb);
+extern void  vj_uncompress_err   (struct vjcompress *comp);
+extern int   vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp);
+extern int   vj_uncompress_tcp   (struct pbuf **nb, struct vjcompress *comp);
+
+#endif /* VJ_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/vjbsdhdr.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/vjbsdhdr.h
new file mode 100644
index 0000000..6c247c6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/ppp/vjbsdhdr.h
@@ -0,0 +1,81 @@
+#ifndef VJBSDHDR_H
+#define VJBSDHDR_H
+
+#include "lwip/tcp.h"
+
+/*
+ * Structure of an internet header, naked of options.
+ *
+ * We declare ip_len and ip_off to be short, rather than u_short
+ * pragmatically since otherwise unsigned comparisons can result
+ * against negative integers quite easily, and fail in subtle ways.
+ */
+PACK_STRUCT_BEGIN
+#if (defined(__MWERKS__)  || defined(__CWCC__))
+	#pragma options align= packed
+#endif
+struct ip
+{
+#if defined(NO_CHAR_BITFIELDS)
+  u_char   ip_hl_v;  /* bug in GCC for mips means the bitfield stuff will sometimes break - so we use a char for both and get round it with macro's instead... */
+#else
+#if BYTE_ORDER == LITTLE_ENDIAN
+  unsigned ip_hl:4,              /* header length */
+           ip_v :4;              /* version */
+#elif BYTE_ORDER == BIG_ENDIAN 
+  unsigned ip_v :4,              /* version */
+           ip_hl:4;              /* header length */
+#else
+  COMPLAIN - NO BYTE ORDER SELECTED!
+#endif
+#endif
+  u_char  ip_tos;                /* type of service */
+  u_short ip_len;                /* total length */
+  u_short ip_id;                 /* identification */
+  u_short ip_off;                /* fragment offset field */
+#define  IP_DF 0x4000            /* dont fragment flag */
+#define  IP_MF 0x2000            /* more fragments flag */
+#define  IP_OFFMASK 0x1fff       /* mask for fragmenting bits */
+  u_char  ip_ttl;                /* time to live */
+  u_char  ip_p;                  /* protocol */
+  u_short ip_sum;                /* checksum */
+  struct  in_addr ip_src,ip_dst; /* source and dest address */
+};
+PACK_STRUCT_END
+
+typedef u32_t tcp_seq;
+
+/*
+ * TCP header.
+ * Per RFC 793, September, 1981.
+ */
+PACK_STRUCT_BEGIN
+#if (defined(__MWERKS__)  || defined(__CWCC__))
+	#pragma options align= packed
+#endif
+struct tcphdr  
+{
+  u_short  th_sport;    /* source port */
+  u_short  th_dport;    /* destination port */
+  tcp_seq  th_seq;      /* sequence number */
+  tcp_seq  th_ack;      /* acknowledgement number */
+#if defined(NO_CHAR_BITFIELDS)
+  u_char   th_x2_off;
+#else
+#if BYTE_ORDER == LITTLE_ENDIAN
+  unsigned th_x2 :4,    /* (unused) */
+           th_off:4;    /* data offset */
+#endif
+#if BYTE_ORDER == BIG_ENDIAN 
+  unsigned th_off:4,    /* data offset */
+           th_x2 :4;    /* (unused) */
+#endif
+#endif
+  u_char   th_flags;
+  u_short  th_win;      /* window */
+  u_short  th_sum;      /* checksum */
+  u_short  th_urp;      /* urgent pointer */
+};
+PACK_STRUCT_END
+
+#endif /* VJBSDHDR_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/slipif.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/slipif.c
new file mode 100644
index 0000000..7839da4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/slipif.c
@@ -0,0 +1,275 @@
+/**
+ * @file
+ * SLIP Interface
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is built upon the file: src/arch/rtxc/netif/sioslip.c
+ *
+ * Author: Magnus Ivarsson  
+ */
+
+/* 
+ * This is an arch independent SLIP netif. The specific serial hooks must be
+ * provided by another file. They are sio_open, sio_recv and sio_send
+ */
+
+#include "netif/slipif.h"
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+#include "lwip/sio.h"
+
+#define SLIP_END     0300 /* 0xC0 */
+#define SLIP_ESC     0333 /* 0xDB */
+#define SLIP_ESC_END 0334 /* 0xDC */
+#define SLIP_ESC_ESC 0335 /* 0xDD */
+
+#define MAX_SIZE     1500
+
+/**
+ * Send a pbuf doing the necessary SLIP encapsulation
+ *
+ * Uses the serial layer's sio_send()
+ *
+ * @param netif the lwip network interface structure for this slipif
+ * @param p the pbuf chaing packet to send
+ * @param ipaddr the ip address to send the packet to (not used for slipif)
+ * @return always returns ERR_OK since the serial layer does not provide return values
+ */
+err_t
+slipif_output(struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr)
+{
+  struct pbuf *q;
+  u16_t i;
+  u8_t c;
+
+  LWIP_ASSERT("netif != NULL", (netif != NULL));
+  LWIP_ASSERT("netif->state != NULL", (netif->state != NULL));
+  LWIP_ASSERT("p != NULL", (p != NULL));
+
+  LWIP_UNUSED_ARG(ipaddr);
+
+  /* Send pbuf out on the serial I/O device. */
+  sio_send(SLIP_END, netif->state);
+
+  for (q = p; q != NULL; q = q->next) {
+    for (i = 0; i < q->len; i++) {
+      c = ((u8_t *)q->payload)[i];
+      switch (c) {
+      case SLIP_END:
+        sio_send(SLIP_ESC, netif->state);
+        sio_send(SLIP_ESC_END, netif->state);
+        break;
+      case SLIP_ESC:
+        sio_send(SLIP_ESC, netif->state);
+        sio_send(SLIP_ESC_ESC, netif->state);
+        break;
+      default:
+        sio_send(c, netif->state);
+        break;
+      }
+    }
+  }
+  sio_send(SLIP_END, netif->state);
+  return ERR_OK;
+}
+
+/**
+ * Handle the incoming SLIP stream character by character
+ *
+ * Poll the serial layer by calling sio_recv()
+ *
+ * @param netif the lwip network interface structure for this slipif
+ * @return The IP packet when SLIP_END is received 
+ */
+static struct pbuf *
+slipif_input(struct netif *netif)
+{
+  u8_t c;
+  /* q is the whole pbuf chain for a packet, p is the current pbuf in the chain */
+  struct pbuf *p, *q;
+  u16_t recved;
+  u16_t i;
+
+  LWIP_ASSERT("netif != NULL", (netif != NULL));
+  LWIP_ASSERT("netif->state != NULL", (netif->state != NULL));
+
+  q = p = NULL;
+  recved = i = 0;
+  c = 0;
+
+  while (1) {
+    c = sio_recv(netif->state);
+    switch (c) {
+    case SLIP_END:
+      if (recved > 0) {
+        /* Received whole packet. */
+        /* Trim the pbuf to the size of the received packet. */
+        pbuf_realloc(q, recved);
+        
+        LINK_STATS_INC(link.recv);
+        
+        LWIP_DEBUGF(SLIP_DEBUG, ("slipif: Got packet\n"));
+        return q;
+      }
+      break;
+
+    case SLIP_ESC:
+      c = sio_recv(netif->state);
+      switch (c) {
+      case SLIP_ESC_END:
+        c = SLIP_END;
+        break;
+      case SLIP_ESC_ESC:
+        c = SLIP_ESC;
+        break;
+      }
+      /* FALLTHROUGH */
+
+    default:
+      /* byte received, packet not yet completely received */
+      if (p == NULL) {
+        /* allocate a new pbuf */
+        LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: alloc\n"));
+        p = pbuf_alloc(PBUF_LINK, PBUF_POOL_BUFSIZE, PBUF_POOL);
+
+        if (p == NULL) {
+          LINK_STATS_INC(link.drop);
+          LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: no new pbuf! (DROP)\n"));
+          /* don't process any further since we got no pbuf to receive to */
+          break;
+        }
+
+        if (q != NULL) {
+          /* 'chain' the pbuf to the existing chain */
+          pbuf_cat(q, p);
+        } else {
+          /* p is the first pbuf in the chain */
+          q = p;
+        }
+      }
+
+      /* this automatically drops bytes if > MAX_SIZE */
+      if ((p != NULL) && (recved <= MAX_SIZE)) {
+        ((u8_t *)p->payload)[i] = c;
+        recved++;
+        i++;
+        if (i >= p->len) {
+          /* on to the next pbuf */
+          i = 0;
+          if (p->next != NULL && p->next->len > 0) {
+            /* p is a chain, on to the next in the chain */
+            p = p->next;
+          } else {
+            /* p is a single pbuf, set it to NULL so next time a new
+             * pbuf is allocated */
+            p = NULL;
+          }
+        }
+      }
+      break;
+    }
+  }
+  return NULL;
+}
+
+#if !NO_SYS
+/**
+ * The SLIP input thread.
+ *
+ * Feed the IP layer with incoming packets
+ *
+ * @param nf the lwip network interface structure for this slipif
+ */
+static void
+slipif_loop(void *nf)
+{
+  struct pbuf *p;
+  struct netif *netif = (struct netif *)nf;
+
+  while (1) {
+    p = slipif_input(netif);
+    if (p != NULL) {
+      if (netif->input(p, netif) != ERR_OK) {
+        pbuf_free(p);
+        p = NULL;
+      }
+    }
+  }
+}
+#endif /* !NO_SYS */
+
+/**
+ * SLIP netif initialization
+ *
+ * Call the arch specific sio_open and remember
+ * the opened device in the state field of the netif.
+ *
+ * @param netif the lwip network interface structure for this slipif
+ * @return ERR_OK if serial line could be opened,
+ *         ERR_IF is serial line couldn't be opened
+ *
+ * @note netif->num must contain the number of the serial port to open
+ *       (0 by default)
+ */
+err_t
+slipif_init(struct netif *netif)
+{
+
+  LWIP_DEBUGF(SLIP_DEBUG, ("slipif_init: netif->num=%"U16_F"\n", (u16_t)netif->num));
+
+  netif->name[0] = 's';
+  netif->name[1] = 'l';
+  netif->output = slipif_output;
+  netif->mtu = MAX_SIZE;
+  netif->flags = NETIF_FLAG_POINTTOPOINT;
+
+  /* Try to open the serial port (netif->num contains the port number). */
+  netif->state = sio_open(netif->num);
+  if (!netif->state) {
+    /* Opening the serial port failed. */
+    return ERR_IF;
+  }
+
+  /* initialize the snmp variables and counters inside the struct netif
+   * ifSpeed: no assumption can be made without knowing more about the
+   * serial line!
+   */
+  NETIF_INIT_SNMP(netif, snmp_ifType_slip, 0);
+
+  /* Create a thread to poll the serial line. */
+  sys_thread_new(SLIPIF_THREAD_NAME, slipif_loop, netif, SLIPIF_THREAD_STACKSIZE, SLIPIF_THREAD_PRIO);
+  return ERR_OK;
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/stf91x_ethernetif.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/stf91x_ethernetif.c
new file mode 100644
index 0000000..87042f8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/src/netif/stf91x_ethernetif.c
@@ -0,0 +1,416 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+/*
+ * This file is a skeleton for developing Ethernet network interface
+ * drivers for lwIP. Add code to the low_level functions and do a
+ * search-and-replace for the word "ethernetif" to replace it with
+ * something that better describes your network interface.
+ */
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include 
+#include 
+#include "netif/etharp.h"
+#include "91x_enet.h"
+
+// Standard library include
+#include 
+#include 
+
+#define netifMTU													( 1500 )
+#define netifINTERFACE_TASK_STACK_SIZE		( 350 )
+#define netifINTERFACE_TASK_PRIORITY			( configMAX_PRIORITIES - 1 )
+#define netifBUFFER_WAIT_ATTEMPTS					10
+#define netifBUFFER_WAIT_DELAY						(10 / portTICK_PERIOD_MS)
+#define IFNAME0 'e'
+#define IFNAME1 'n'
+
+/* The time to block waiting for input. */
+#define emacBLOCK_TIME_WAITING_FOR_INPUT	( ( TickType_t ) 100 )
+
+/* Interrupt status bit definition. */
+#define DMI_RX_CURRENT_DONE 0x8000
+
+static u8_t s_rxBuff[1520];
+
+/* The semaphore used by the ISR to wake the lwIP task. */
+static SemaphoreHandle_t s_xSemaphore = NULL;
+
+struct ethernetif {
+  struct eth_addr *ethaddr;
+  /* Add whatever per-interface state that is needed here. */
+};
+
+/* Forward declarations. */
+static void ethernetif_input( void *pParams );
+u8 *pcGetNextBuffer( void );
+
+/**
+ * In this function, the hardware should be initialized.
+ * Called from ethernetif_init().
+ *
+ * @param netif the already initialized lwip network interface structure
+ *        for this ethernetif
+ */
+static void low_level_init(struct netif *netif)
+{
+  /* set MAC hardware address length */
+  netif->hwaddr_len = ETHARP_HWADDR_LEN;
+
+  /* set MAC hardware address */
+  netif->hwaddr[0] = MAC_ADDR0;
+  netif->hwaddr[1] = MAC_ADDR1;
+  netif->hwaddr[2] = MAC_ADDR2;
+  netif->hwaddr[3] = MAC_ADDR3;
+  netif->hwaddr[4] = MAC_ADDR4;
+  netif->hwaddr[5] = MAC_ADDR5;
+
+  /* maximum transfer unit */
+  netif->mtu = netifMTU;
+
+  // device capabilities.
+	// don't set NETIF_FLAG_ETHARP if this device is not an ethernet one
+  netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP;
+
+  /* Do whatever else is needed to initialize interface. */
+	
+  if( s_xSemaphore == NULL )
+  {
+      vSemaphoreCreateBinary( s_xSemaphore );
+      xSemaphoreTake( s_xSemaphore,  0);
+  }
+
+  /* Initialise the MAC. */
+  ENET_InitClocksGPIO();
+  ENET_Init(PHY_AUTO_NEGOTIATION);
+  ENET_Start();
+	
+  portENTER_CRITICAL();
+  {
+      /*set MAC physical*/
+      ENET_MAC->MAH = (MAC_ADDR5<<8) + MAC_ADDR4;
+      ENET_MAC->MAL = (MAC_ADDR3<<24) + (MAC_ADDR2<<16) + (MAC_ADDR1<<8) + MAC_ADDR0;
+	
+      VIC_Config( ENET_ITLine, VIC_IRQ, 1 );
+      VIC_ITCmd( ENET_ITLine, ENABLE );	
+      ENET_DMA->ISR = DMI_RX_CURRENT_DONE;
+      ENET_DMA->IER = DMI_RX_CURRENT_DONE;
+  }
+  portEXIT_CRITICAL();
+	
+  netif->flags |= NETIF_FLAG_LINK_UP;
+
+  /* Create the task that handles the EMAC. */
+  xTaskCreate( ethernetif_input, "ETH_INT", netifINTERFACE_TASK_STACK_SIZE, (void *)netif, netifINTERFACE_TASK_PRIORITY, NULL );
+}	
+
+
+/**
+ * This function should do the actual transmission of the packet. The packet is
+ * contained in the pbuf that is passed to the function. This pbuf
+ * might be chained.
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)
+ * @return ERR_OK if the packet could be sent
+ *         an err_t value if the packet couldn't be sent
+ *
+ * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to
+ *       strange results. You might consider waiting for space in the DMA queue
+ *       to become availale since the stack doesn't retry to send a packet
+ *       dropped because of memory failure (except for the TCP timers).
+ */
+static err_t low_level_output(struct netif *netif, struct pbuf *p)
+{
+  struct pbuf *q;
+  u32_t l = 0;
+	unsigned char *pcTxData;
+
+#if ETH_PAD_SIZE
+  pbuf_header(p, -ETH_PAD_SIZE);			/* drop the padding word */
+#endif
+	
+	/* Get a DMA buffer into which we can write the data to send. */
+	for( int i = 0; i < netifBUFFER_WAIT_ATTEMPTS; i++ )
+	{
+		pcTxData = pcGetNextBuffer();
+
+		if( pcTxData ){
+			break;
+		} else {
+			vTaskDelay( netifBUFFER_WAIT_DELAY );
+		}
+	}
+	
+	if (pcTxData == NULL) {
+		portNOP();		
+		
+		return ERR_BUF;
+	}
+	else {
+
+		for(q = p; q != NULL; q = q->next) {
+			/* Send the data from the pbuf to the interface, one pbuf at a
+				 time. The size of the data in each pbuf is kept in the ->len
+				 variable. */
+			
+			vTaskSuspendAll();
+			memcpy(&pcTxData[l], (u8_t*)q->payload, q->len);
+			xTaskResumeAll();
+			l += q->len;
+		}
+	}
+
+	ENET_TxPkt( &pcTxData, l );
+			
+	#if ETH_PAD_SIZE
+		pbuf_header(p, ETH_PAD_SIZE);			/* reclaim the padding word */
+	#endif
+
+		LINK_STATS_INC(link.xmit);
+
+  return ERR_OK;
+}
+
+/**
+ * Should allocate a pbuf and transfer the bytes of the incoming
+ * packet from the interface into the pbuf.
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ * @return a pbuf filled with the received packet (including MAC header)
+ *         NULL on memory error
+ */
+static struct pbuf *low_level_input(struct netif *netif)
+{
+  struct pbuf *p, *q;
+  u16_t len, l;
+
+  l = 0;
+  p = NULL;
+	
+
+	/* Obtain the size of the packet and put it into the "len"
+		 variable. */
+	len = ENET_HandleRxPkt(s_rxBuff);
+
+	if(len)
+	{
+	#if ETH_PAD_SIZE
+		len += ETH_PAD_SIZE;						/* allow room for Ethernet padding */
+	#endif
+
+		/* We allocate a pbuf chain of pbufs from the pool. */
+		p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
+
+		if (p != NULL) {
+
+	#if ETH_PAD_SIZE
+			pbuf_header(p, -ETH_PAD_SIZE);			/* drop the padding word */
+	#endif
+
+			/* We iterate over the pbuf chain until we have read the entire
+			 * packet into the pbuf. */
+			for(q = p; q != NULL; q = q->next) {
+				/* Read enough bytes to fill this pbuf in the chain. The
+				 * available data in the pbuf is given by the q->len
+				 * variable. */
+				vTaskSuspendAll();
+				memcpy((u8_t*)q->payload, &s_rxBuff[l], q->len);
+				xTaskResumeAll();
+				l = l + q->len;
+			}
+
+
+	#if ETH_PAD_SIZE
+			pbuf_header(p, ETH_PAD_SIZE);			/* reclaim the padding word */
+	#endif
+
+			LINK_STATS_INC(link.recv);
+
+		} else {
+
+			LINK_STATS_INC(link.memerr);
+			LINK_STATS_INC(link.drop);
+
+		} /* End else */
+	} /* End if */
+			
+  return p;
+}
+
+/**
+ * This function should be called when a packet is ready to be read
+ * from the interface. It uses the function low_level_input() that
+ * should handle the actual reception of bytes from the network
+ * interface.Then the type of the received packet is determined and
+ * the appropriate input function is called.
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ */
+
+static void ethernetif_input( void *pParams )
+{
+	struct netif *netif;
+  struct ethernetif *ethernetif;
+  struct eth_hdr *ethhdr;
+  struct pbuf *p;
+
+	netif = (struct netif*) pParams;
+	ethernetif = netif->state;
+	
+	for( ;; )
+	{
+		do
+		{
+			
+			/* move received packet into a new pbuf */
+			p = low_level_input( netif );
+			
+			if( p == NULL )
+			{
+				/* No packet could be read.  Wait a for an interrupt to tell us
+				there is more data available. */
+				xSemaphoreTake( s_xSemaphore, emacBLOCK_TIME_WAITING_FOR_INPUT );
+			}
+		
+		} while( p == NULL );
+
+		/* points to packet payload, which starts with an Ethernet header */
+		ethhdr = p->payload;
+
+		switch (htons(ethhdr->type)) {
+			/* IP or ARP packet? */
+	
+		case ETHTYPE_IP:
+	
+			/* full packet send to tcpip_thread to process */
+			if (netif->input(p, netif) != ERR_OK)
+			{
+				LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n"));
+				pbuf_free(p);
+				p = NULL;
+			}
+			break;
+				
+		case ETHTYPE_ARP:
+				
+#if ETHARP_TRUST_IP_MAC
+			etharp_ip_input(netif, p);
+#endif
+				
+			etharp_arp_input(netif, ethernetif->ethaddr, p);
+			break;
+		
+		default:
+			pbuf_free(p);
+			p = NULL;
+			break;
+		}
+	}
+}
+
+/**
+ * Should be called at the beginning of the program to set up the
+ * network interface. It calls the function low_level_init() to do the
+ * actual setup of the hardware.
+ *
+ * This function should be passed as a parameter to netif_add().
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ * @return ERR_OK if the loopif is initialized
+ *         ERR_MEM if private data couldn't be allocated
+ *         any other err_t on error
+ */
+err_t
+ethernetif_init(struct netif *netif)
+{
+  struct ethernetif *ethernetif;
+	
+	LWIP_ASSERT("netif != NULL", (netif != NULL));
+
+  ethernetif = mem_malloc(sizeof(struct ethernetif));
+
+  if (ethernetif == NULL)
+  {
+  	LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n"));
+  	return ERR_MEM;
+  }
+
+#if LWIP_NETIF_HOSTNAME
+  /* Initialize interface hostname */
+  netif->hostname = "lwip";
+#endif /* LWIP_NETIF_HOSTNAME */
+	
+  /*
+	 * Initialize the snmp variables and counters inside the struct netif.
+	 * The last argument should be replaced with your link speed, in units
+	 * of bits per second.
+	 */
+	NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 100);	
+
+  netif->state = ethernetif;
+  netif->name[0] = IFNAME0;
+  netif->name[1] = IFNAME1;
+  /* We directly use etharp_output() here to save a function call.
+	 * You can instead declare your own function an call etharp_output()
+	 * from it if you have to do some checks before sending (e.g. if link
+	 * is available...)
+	 */	
+  netif->output = etharp_output;
+  netif->linkoutput = low_level_output;
+
+  ethernetif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]);
+
+  low_level_init(netif);
+
+  return ERR_OK;
+}
+/*-----------------------------------------------------------*/
+
+void ENET_IRQHandler(void)
+{
+portBASE_TYPE xSwitchRequired;
+
+	/* Give the semaphore in case the lwIP task needs waking. */
+	xSwitchRequired = xSemaphoreGiveFromISR( s_xSemaphore, &xSwitchRequired );
+	
+	/* Clear the interrupt. */
+	ENET_DMA->ISR = DMI_RX_CURRENT_DONE;
+	
+	/* Switch tasks if necessary. */	
+	portEND_SWITCHING_ISR( xSwitchRequired );
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/sys b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_130/sys
new file mode 100644
index 0000000..e69de29
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/CHANGELOG b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/CHANGELOG
new file mode 100644
index 0000000..860d1c4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/CHANGELOG
@@ -0,0 +1,2419 @@
+FUTURE
+
+  * TODO: The lwIP source code makes some invalid assumptions on processor
+    word-length, storage sizes and alignment. See the mailing lists for
+    problems with exoteric (/DSP) architectures showing these problems.
+    We still have to fix some of these issues neatly.
+
+  * TODO: the PPP code is broken in a few ways. There are namespace
+    collisions on BSD systems and many assumptions on word-length
+    (sizeof(int)). In ppp.c an assumption is made on the availability of
+    a thread subsystem. Either PPP needs to be moved to contrib/ports/???
+    or rearranged to be more generic.
+
+HISTORY
+
+(CVS HEAD)
+
+  * [Enter new changes just after this line - do not remove this line]
+
+  ++ New features:
+
+
+  ++ Bugfixes:
+
+
+(STABLE-1.3.2)
+
+  ++ New features:
+
+  2009-10-27 Simon Goldschmidt/Stephan Lesage
+  * netifapi.c/.h: Added netifapi_netif_set_addr()
+
+  2009-10-07 Simon Goldschmidt/Fabian Koch
+  * api_msg.c, netbuf.c/.h, opt.h: patch #6888: Patch for UDP Netbufs to
+    support dest-addr and dest-port (optional: LWIP_NETBUF_RECVINFO)
+
+  2009-08-26 Simon Goldschmidt/Simon Kallweit
+  * slipif.c/.h: bug #26397: SLIP polling support
+
+  2009-08-25 Simon Goldschmidt
+  * opt.h, etharp.h/.c: task #9033: Support IEEE 802.1q tagged frame (VLAN),
+    New configuration options ETHARP_SUPPORT_VLAN and ETHARP_VLAN_CHECK.
+
+  2009-08-25 Simon Goldschmidt
+  * ip_addr.h, netdb.c: patch #6900: added define ip_ntoa(struct ip_addr*)
+
+  2009-08-24 Jakob Stoklund Olesen
+  * autoip.c, dhcp.c, netif.c: patch #6725: Teach AutoIP and DHCP to respond
+    to netif_set_link_up().
+
+  2009-08-23 Simon Goldschmidt
+  * tcp.h/.c: Added function tcp_debug_state_str() to convert a tcp state
+    to a human-readable string.
+
+  ++ Bugfixes:
+
+  2009-12-24: Kieran Mansley
+  * tcp_in.c Apply patches from Oleg Tyshev to improve OOS processing
+    (BUG#28241)
+
+  2009-12-06: Simon Goldschmidt
+  * ppp.h/.c: Fixed bug #27079 (Yet another leak in PPP): outpacket_buf can
+    be statically allocated (like in ucip)
+
+  2009-12-04: Simon Goldschmidt (patch by Ioardan Neshev)
+  * pap.c: patch #6969: PPP: missing PAP authentication UNTIMEOUT
+
+  2009-12-03: Simon Goldschmidt
+  * tcp.h, tcp_in.c, tcp_out.c: Fixed bug #28106: dup ack for fast retransmit
+    could have non-zero length
+
+  2009-12-02: Simon Goldschmidt
+  * tcp_in.c: Fixed bug #27904: TCP sends too many ACKs: delay resetting
+    tcp_input_pcb until after calling the pcb's callbacks
+
+  2009-11-29: Simon Goldschmidt
+  * tcp_in.c: Fixed bug #28054: Two segments with FIN flag on the out-of-
+    sequence queue, also fixed PBUF_POOL leak in the out-of-sequence code
+
+  2009-11-29: Simon Goldschmidt
+  * pbuf.c: Fixed bug #28064: pbuf_alloc(PBUF_POOL) is not thread-safe by
+    queueing a call into tcpip_thread to free ooseq-bufs if the pool is empty
+
+  2009-11-26: Simon Goldschmidt
+  * tcp.h: Fixed bug #28098: Nagle can prevent fast retransmit from sending
+    segment
+
+  2009-11-26: Simon Goldschmidt
+  * tcp.h, sockets.c: Fixed bug #28099: API required to disable Nagle
+    algorithm at PCB level
+
+  2009-11-22: Simon Goldschmidt
+  * tcp_out.c: Fixed bug #27905: FIN isn't combined with data on unsent
+
+  2009-11-22: Simon Goldschmidt (suggested by Bill Auerbach)
+  * tcp.c: tcp_alloc: prevent increasing stats.err for MEMP_TCP_PCB when
+    reusing time-wait pcb
+
+  2009-11-20: Simon Goldschmidt (patch by Albert Bartel)
+  * sockets.c: Fixed bug #28062: Data received directly after accepting
+    does not wake up select
+
+  2009-11-11: Simon Goldschmidt
+  * netdb.h: Fixed bug #27994: incorrect define for freeaddrinfo(addrinfo)
+
+  2009-10-30: Simon Goldschmidt
+  * opt.h: Increased default value for TCP_MSS to 536, updated default
+    value for TCP_WND to 4*TCP_MSS to keep delayed ACK working.
+
+  2009-10-28: Kieran Mansley
+  * tcp_in.c, tcp_out.c, tcp.h: re-work the fast retransmission code
+    to follow algorithm from TCP/IP Illustrated
+
+  2009-10-27: Kieran Mansley
+  * tcp_in.c: fix BUG#27445: grow cwnd with every duplicate ACK
+
+  2009-10-25: Simon Goldschmidt
+  * tcp.h: bug-fix in the TCP_EVENT_RECV macro (has to call tcp_recved if
+    pcb->recv is NULL to keep rcv_wnd correct)
+
+  2009-10-25: Simon Goldschmidt
+  * tcp_in.c: Fixed bug #26251: RST process in TIME_WAIT TCP state
+
+  2009-10-23: Simon Goldschmidt (David Empson)
+  * tcp.c: Fixed bug #27783: Silly window avoidance for small window sizes
+
+  2009-10-21: Simon Goldschmidt
+  * tcp_in.c: Fixed bug #27215: TCP sent() callback gives leading and
+    trailing 1 byte len (SYN/FIN)
+
+  2009-10-21: Simon Goldschmidt
+  * tcp_out.c: Fixed bug #27315: zero window probe and FIN
+
+  2009-10-19: Simon Goldschmidt
+  * dhcp.c/.h: Minor code simplification (don't store received pbuf, change
+    conditional code to assert where applicable), check pbuf length before
+    testing for valid reply
+
+  2009-10-19: Simon Goldschmidt
+  * dhcp.c: Removed most calls to udp_connect since they aren't necessary
+    when using udp_sendto_if() - always stay connected to IP_ADDR_ANY.
+
+  2009-10-16: Simon Goldschmidt
+  * ip.c: Fixed bug #27390: Source IP check in ip_input() causes it to drop
+    valid DHCP packets -> allow 0.0.0.0 as source address when LWIP_DHCP is
+    enabled
+
+  2009-10-15: Simon Goldschmidt (Oleg Tyshev)
+  * tcp_in.c: Fixed bug #27329: dupacks by unidirectional data transmit
+
+  2009-10-15: Simon Goldschmidt
+  * api_lib.c: Fixed bug #27709: conn->err race condition on netconn_recv()
+    timeout
+
+  2009-10-15: Simon Goldschmidt
+  * autoip.c: Fixed bug #27704: autoip starts with wrong address
+    LWIP_AUTOIP_CREATE_SEED_ADDR() returned address in host byte order instead
+    of network byte order
+
+  2009-10-11 Simon Goldschmidt (Jörg Kesten)
+  * tcp_out.c: Fixed bug #27504: tcp_enqueue wrongly concatenates segments
+    which are not consecutive when retransmitting unacked segments
+
+  2009-10-09 Simon Goldschmidt
+  * opt.h: Fixed default values of some stats to only be enabled if used
+    Fixes bug #27338: sys_stats is defined when NO_SYS = 1
+
+  2009-08-30 Simon Goldschmidt
+  * ip.c: Fixed bug bug #27345: "ip_frag() does not use the LWIP_NETIF_LOOPBACK
+    function" by checking for loopback before calling ip_frag
+
+  2009-08-25 Simon Goldschmidt
+  * dhcp.c: fixed invalid dependency to etharp_query if DHCP_DOES_ARP_CHECK==0
+
+  2009-08-23 Simon Goldschmidt
+  * ppp.c: bug #27078: Possible memory leak in pppInit()
+
+  2009-08-23 Simon Goldschmidt
+  * netdb.c, dns.c: bug #26657: DNS, if host name is "localhost", result
+    is error.
+
+  2009-08-23 Simon Goldschmidt
+  * opt.h, init.c: bug #26649: TCP fails when TCP_MSS > TCP_SND_BUF
+    Fixed wrong parenthesis, added check in init.c
+
+  2009-08-23 Simon Goldschmidt
+  * ppp.c: bug #27266: wait-state debug message in pppMain occurs every ms
+
+  2009-08-23 Simon Goldschmidt
+  * many ppp files: bug #27267: Added include to string.h where needed
+
+  2009-08-23 Simon Goldschmidt
+  * tcp.h: patch #6843: tcp.h macro optimization patch (for little endian)
+
+
+(STABLE-1.3.1)
+
+  ++ New features:
+
+  2009-05-10 Simon Goldschmidt
+  * opt.h, sockets.c, pbuf.c, netbuf.h, pbuf.h: task #7013: Added option
+    LWIP_NETIF_TX_SINGLE_PBUF to try to create transmit packets from only
+    one pbuf to help MACs that don't support scatter-gather DMA.
+
+  2009-05-09 Simon Goldschmidt
+  * icmp.h, icmp.c: Shrinked ICMP code, added option to NOT check icoming
+    ECHO pbuf for size (just use it): LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN
+
+  2009-05-05 Simon Goldschmidt, Jakob Stoklund Olesen
+  * ip.h, ip.c: Added ip_current_netif() & ip_current_header() to receive
+    extended info about the currently received packet.
+
+  2009-04-27 Simon Goldschmidt
+  * sys.h: Made SYS_LIGHTWEIGHT_PROT and sys_now() work with NO_SYS=1
+
+  2009-04-25 Simon Goldschmidt
+  * mem.c, opt.h: Added option MEM_USE_POOLS_TRY_BIGGER_POOL to try the next
+    bigger malloc pool if one is empty (only usable with MEM_USE_POOLS).
+
+  2009-04-21 Simon Goldschmidt
+  * dns.c, init.c, dns.h, opt.h: task #7507, patch #6786: DNS supports static
+    hosts table. New configuration options DNS_LOCAL_HOSTLIST and
+    DNS_LOCAL_HOSTLIST_IS_DYNAMIC. Also, DNS_LOOKUP_LOCAL_EXTERN() can be defined
+    as an external function for lookup.
+
+  2009-04-15 Simon Goldschmidt
+  * dhcp.c: patch #6763: Global DHCP XID can be redefined to something more unique
+
+  2009-03-31 Kieran Mansley
+  * tcp.c, tcp_out.c, tcp_in.c, sys.h, tcp.h, opts.h: add support for
+    TCP timestamp options, off by default.  Rework tcp_enqueue() to
+    take option flags rather than specified option data
+
+  2009-02-18 Simon Goldschmidt
+  * cc.h: Added printf formatter for size_t: SZT_F
+
+  2009-02-16 Simon Goldschmidt (patch by Rishi Khan)
+  * icmp.c, opt.h: patch #6539: (configurable) response to broadcast- and multicast
+    pings
+
+  2009-02-12 Simon Goldschmidt
+  * init.h: Added LWIP_VERSION to get the current version of the stack
+
+  2009-02-11 Simon Goldschmidt (suggested by Gottfried Spitaler)
+  * opt.h, memp.h/.c: added MEMP_MEM_MALLOC to use mem_malloc/mem_free instead
+    of the pool allocator (can save code size with MEM_LIBC_MALLOC if libc-malloc
+    is otherwise used)
+
+  2009-01-28 Jonathan Larmour (suggested by Bill Bauerbach)
+  * ipv4/inet_chksum.c, ipv4/lwip/inet_chksum.h: inet_chksum_pseudo_partial()
+  is only used by UDPLITE at present, so conditionalise it.
+
+  2008-12-03 Simon Goldschmidt (base on patch from Luca Ceresoli)
+  * autoip.c: checked in (slightly modified) patch #6683: Customizable AUTOIP
+    "seed" address. This should reduce AUTOIP conflicts if
+    LWIP_AUTOIP_CREATE_SEED_ADDR is overridden.
+
+  2008-10-02 Jonathan Larmour and Rishi Khan
+  * sockets.c (lwip_accept): Return EWOULDBLOCK if would block on non-blocking
+    socket.
+
+  2008-06-30 Simon Goldschmidt
+  * mem.c, opt.h, stats.h: fixed bug #21433: Calling mem_free/pbuf_free from
+    interrupt context isn't safe: LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT allows
+    mem_free to run between mem_malloc iterations. Added illegal counter for
+    mem stats.
+
+  2008-06-27 Simon Goldschmidt
+  * stats.h/.c, some other files: patch #6483: stats module improvement:
+    Added defines to display each module's statistic individually, added stats
+    defines for MEM, MEMP and SYS modules, removed (unused) rexmit counter.
+
+  2008-06-17 Simon Goldschmidt
+  * err.h: patch #6459: Made err_t overridable to use a more efficient type
+    (define LWIP_ERR_T in cc.h)
+
+  2008-06-17 Simon Goldschmidt
+  * slipif.c: patch #6480: Added a configuration option for slipif for symmetry
+    to loopif
+
+  2008-06-17 Simon Goldschmidt (patch by Luca Ceresoli)
+  * netif.c, loopif.c, ip.c, netif.h, loopif.h, opt.h: Checked in slightly
+    modified version of patch # 6370: Moved loopif code to netif.c so that
+    loopback traffic is supported on all netifs (all local IPs).
+    Added option to limit loopback packets for each netifs.
+
+
+  ++ Bugfixes:
+  2009-08-12 Kieran Mansley
+  * tcp_in.c, tcp.c: Fix bug #27209: handle trimming of segments when
+    out of window or out of order properly
+
+  2009-08-12 Kieran Mansley
+  * tcp_in.c: Fix bug #27199: use snd_wl2 instead of snd_wl1
+
+  2009-07-28 Simon Goldschmidt
+  * mem.h: Fixed bug #27105: "realloc() cannot replace mem_realloc()"s
+
+  2009-07-27 Kieran Mansley
+  * api.h api_msg.h netdb.h sockets.h: add missing #include directives
+
+  2009-07-09 Kieran Mansley
+  * api_msg.c, sockets.c, api.h: BUG23240 use signed counters for
+    recv_avail and don't increment counters until message successfully
+    sent to mbox
+
+  2009-06-25 Kieran Mansley
+  * api_msg.c api.h: BUG26722: initialise netconn write variables 
+    in netconn_alloc
+
+  2009-06-25 Kieran Mansley
+  * tcp.h: BUG26879: set ret value in TCP_EVENT macros when function is not set
+
+  2009-06-25 Kieran Mansley
+  * tcp.c, tcp_in.c, tcp_out.c, tcp.h: BUG26301 and BUG26267: correct
+    simultaneous close behaviour, and make snd_nxt have the same meaning 
+    as in the RFCs.
+
+  2009-05-12 Simon Goldschmidt
+  * etharp.h, etharp.c, netif.c: fixed bug #26507: "Gratuitous ARP depends on
+    arp_table / uses etharp_query" by adding etharp_gratuitous()
+
+  2009-05-12 Simon Goldschmidt
+  * ip.h, ip.c, igmp.c: bug #26487: Added ip_output_if_opt that can add IP options
+    to the IP header (used by igmp_ip_output_if)
+
+  2009-05-06 Simon Goldschmidt
+  * inet_chksum.c: On little endian architectures, use LWIP_PLATFORM_HTONS (if
+    defined) for SWAP_BYTES_IN_WORD to speed up checksumming.
+
+  2009-05-05 Simon Goldschmidt
+  * sockets.c: bug #26405: Prematurely released semaphore causes lwip_select()
+    to crash
+
+  2009-05-04 Simon Goldschmidt
+  * init.c: snmp was not initialized in lwip_init()
+
+  2009-05-04 Frédéric Bernon
+  * dhcp.c, netbios.c: Changes if IP_SOF_BROADCAST is enabled.
+
+  2009-05-03 Simon Goldschmidt
+  * tcp.h: bug #26349: Nagle algorithm doesn't send although segment is full
+    (and unsent->next == NULL)
+
+  2009-05-02 Simon Goldschmidt
+  * tcpip.h, tcpip.c: fixed tcpip_untimeout (does not need the time, broken after
+    1.3.0 in CVS only) - fixes compilation of ppp_oe.c
+
+  2009-05-02 Simon Goldschmidt
+  * msg_in.c: fixed bug #25636: SNMPSET value is ignored for integer fields
+
+  2009-05-01 Simon Goldschmidt
+  * pap.c: bug #21680: PPP upap_rauthnak() drops legal NAK packets
+
+  2009-05-01 Simon Goldschmidt
+  * ppp.c: bug #24228: Memory corruption with PPP and DHCP
+
+  2009-04-29 Frédéric Bernon
+  * raw.c, udp.c, init.c, opt.h, ip.h, sockets.h: bug #26309: Implement the
+    SO(F)_BROADCAST filter for all API layers. Avoid the unindented reception
+    of broadcast packets even when this option wasn't set. Port maintainers
+    which want to enable this filter have to set IP_SOF_BROADCAST=1 in opt.h.
+    If you want this option also filter broadcast on recv operations, you also
+    have to set IP_SOF_BROADCAST_RECV=1 in opt.h.
+
+  2009-04-28 Simon Goldschmidt, Jakob Stoklund Olesen
+  * dhcp.c: patch #6721, bugs #25575, #25576: Some small fixes to DHCP and
+    DHCP/AUTOIP cooperation
+
+  2009-04-25 Simon Goldschmidt, Oleg Tyshev
+  * tcp_out.c: bug #24212: Deadlocked tcp_retransmit due to exceeded pcb->cwnd
+    Fixed by sorting the unsent and unacked queues (segments are inserted at the
+    right place in tcp_output and tcp_rexmit).
+
+  2009-04-25 Simon Goldschmidt
+  * memp.c, mem.c, memp.h, mem_std.h: bug #26213 "Problem with memory allocation
+    when debugging": memp_sizes contained the wrong sizes (including sanity
+    regions); memp pools for MEM_USE_POOLS were too small
+
+  2009-04-24 Simon Goldschmidt, Frédéric Bernon
+  * inet.c: patch #6765: Fix a small problem with the last changes (incorrect
+    behavior, with with ip address string not ended by a '\0', a space or a
+    end of line)
+
+  2009-04-19 Simon Goldschmidt
+  * rawapi.txt: Fixed bug #26069: Corrected documentation: if tcp_connect fails,
+    pcb->err is called, not pcb->connected (with an error code).
+
+  2009-04-19 Simon Goldschmidt
+  * tcp_out.c: Fixed bug #26236: "TCP options (timestamp) don't work with
+    no-copy-tcpwrite": deallocate option data, only concat segments with same flags
+
+  2009-04-19 Simon Goldschmidt
+  * tcp_out.c: Fixed bug #25094: "Zero-length pbuf" (options are now allocated
+    in the header pbuf, not the data pbuf)
+
+  2009-04-18 Simon Goldschmidt
+  * api_msg.c: fixed bug #25695: Segmentation fault in do_writemore()
+
+  2009-04-15 Simon Goldschmidt
+  * sockets.c: tried to fix bug #23559: lwip_recvfrom problem with tcp
+
+  2009-04-15 Simon Goldschmidt
+  * dhcp.c: task #9192: mem_free of dhcp->options_in and dhcp->msg_in
+
+  2009-04-15 Simon Goldschmidt
+  * ip.c, ip6.c, tcp_out.c, ip.h: patch #6808: Add a utility function
+    ip_hinted_output() (for smaller code mainly)
+
+  2009-04-15 Simon Goldschmidt
+  * inet.c: patch #6765: Supporting new line characters in inet_aton()
+
+  2009-04-15 Simon Goldschmidt
+  * dhcp.c: patch #6764: DHCP rebind and renew did not send hostnam option;
+    Converted constant OPTION_MAX_MSG_SIZE to netif->mtu, check if netif->mtu
+    is big enough in dhcp_start
+
+  2009-04-15 Simon Goldschmidt
+  * netbuf.c: bug #26027: netbuf_chain resulted in pbuf memory leak
+
+  2009-04-15 Simon Goldschmidt
+  * sockets.c, ppp.c: bug #25763: corrected 4 occurrences of SMEMCPY to MEMCPY
+
+  2009-04-15 Simon Goldschmidt
+  * sockets.c: bug #26121: set_errno can be overridden
+
+  2009-04-09 Kieran Mansley (patch from Luca Ceresoli )
+  * init.c, opt.h: Patch#6774 TCP_QUEUE_OOSEQ breaks compilation when
+    LWIP_TCP==0
+
+  2009-04-09 Kieran Mansley (patch from Roy Lee )
+  * tcp.h: Patch#6802 Add do-while-clauses to those function like
+    macros in tcp.h
+
+  2009-03-31 Kieran Mansley
+  * tcp.c, tcp_in.c, tcp_out.c, tcp.h, opt.h: Rework the way window
+    updates are calculated and sent (BUG20515)
+
+  * tcp_in.c: cope with SYN packets received during established states,
+    and retransmission of initial SYN.
+
+  * tcp_out.c: set push bit correctly when tcp segments are merged
+
+  2009-03-27 Kieran Mansley
+  * tcp_out.c set window correctly on probes (correcting change made
+    yesterday)
+
+  2009-03-26 Kieran Mansley
+  * tcp.c, tcp_in.c, tcp.h: add tcp_abandon() to cope with dropping
+    connections where no reset required (bug #25622)
+
+  * tcp_out.c: set TCP_ACK flag on keepalive and zero window probes 
+    (bug #20779)
+
+  2009-02-18 Simon Goldschmidt (Jonathan Larmour and Bill Auerbach)
+  * ip_frag.c: patch #6528: the buffer used for IP_FRAG_USES_STATIC_BUF could be
+    too small depending on MEM_ALIGNMENT
+
+  2009-02-16 Simon Goldschmidt
+  * sockets.h/.c, api_*.h/.c: fixed arguments of socket functions to match the standard;
+    converted size argument of netconn_write to 'size_t'
+
+  2009-02-16 Simon Goldschmidt
+  * tcp.h, tcp.c: fixed bug #24440: TCP connection close problem on 64-bit host
+    by moving accept callback function pointer to TCP_PCB_COMMON
+
+  2009-02-12 Simon Goldschmidt
+  * dhcp.c: fixed bug #25345 (DHCPDECLINE is sent with "Maximum message size"
+    option)
+
+  2009-02-11 Simon Goldschmidt
+  * dhcp.c: fixed bug #24480 (releasing old udp_pdb and pbuf in dhcp_start)
+
+  2009-02-11 Simon Goldschmidt
+  * opt.h, api_msg.c: added configurable default valud for netconn->recv_bufsize:
+    RECV_BUFSIZE_DEFAULT (fixes bug #23726: pbuf pool exhaustion on slow recv())
+
+  2009-02-10 Simon Goldschmidt
+  * tcp.c: fixed bug #25467: Listen backlog is not reset on timeout in SYN_RCVD:
+    Accepts_pending is decrease on a corresponding listen pcb when a connection
+    in state SYN_RCVD is close.
+
+  2009-01-28 Jonathan Larmour
+  * pbuf.c: reclaim pbufs from TCP out-of-sequence segments if we run
+    out of pool pbufs.
+
+  2008-12-19 Simon Goldschmidt
+  * many files: patch #6699: fixed some warnings on platform where sizeof(int) == 2 
+
+  2008-12-10 Tamas Somogyi, Frédéric Bernon
+  * sockets.c: fixed bug #25051: lwip_recvfrom problem with udp: fromaddr and
+    port uses deleted netbuf.
+
+  2008-10-18 Simon Goldschmidt
+  * tcp_in.c: fixed bug ##24596: Vulnerability on faulty TCP options length
+    in tcp_parseopt
+
+  2008-10-15 Simon Goldschmidt
+  * ip_frag.c: fixed bug #24517: IP reassembly crashes on unaligned IP headers
+    by packing the struct ip_reass_helper.
+
+  2008-10-03 David Woodhouse, Jonathan Larmour
+  * etharp.c (etharp_arp_input): Fix type aliasing problem copying ip address.
+
+  2008-10-02 Jonathan Larmour
+  * dns.c: Hard-code structure sizes, to avoid issues on some compilers where
+    padding is included.
+
+  2008-09-30 Jonathan Larmour
+  * sockets.c (lwip_accept): check addr isn't NULL. If it's valid, do an
+    assertion check that addrlen isn't NULL.
+
+  2008-09-30 Jonathan Larmour
+  * tcp.c: Fix bug #24227, wrong error message in tcp_bind.
+
+  2008-08-26 Simon Goldschmidt
+  * inet.h, ip_addr.h: fixed bug #24132: Cross-dependency between ip_addr.h and
+    inet.h -> moved declaration of struct in_addr from ip_addr.h to inet.h
+
+  2008-08-14 Simon Goldschmidt
+  * api_msg.c: fixed bug #23847: do_close_internal references freed memory (when
+    tcp_close returns != ERR_OK)
+
+  2008-07-08 Frédéric Bernon
+  * stats.h: Fix some build bugs introduced with patch #6483 (missing some parameters
+    in macros, mainly if MEM_STATS=0 and MEMP_STATS=0).
+
+  2008-06-24 Jonathan Larmour
+  * tcp_in.c: Fix for bug #23693 as suggested by Art R. Ensure cseg is unused
+    if tcp_seg_copy fails.
+
+  2008-06-17 Simon Goldschmidt
+  * inet_chksum.c: Checked in some ideas of patch #6460 (loop optimizations)
+    and created defines for swapping bytes and folding u32 to u16.
+
+  2008-05-30 Kieran Mansley
+  * tcp_in.c Remove redundant "if" statement, and use real rcv_wnd
+    rather than rcv_ann_wnd when deciding if packets are in-window.
+    Contributed by 
+
+  2008-05-30 Kieran Mansley
+  * mem.h: Fix BUG#23254.  Change macro definition of mem_* to allow
+    passing as function pointers when MEM_LIBC_MALLOC is defined.
+
+  2008-05-09 Jonathan Larmour
+  * err.h, err.c, sockets.c: Fix bug #23119: Reorder timeout error code to
+    stop it being treated as a fatal error.
+
+  2008-04-15 Simon Goldschmidt
+  * dhcp.c: fixed bug #22804: dhcp_stop doesn't clear NETIF_FLAG_DHCP
+    (flag now cleared)
+
+  2008-03-27 Simon Goldschmidt
+  * mem.c, tcpip.c, tcpip.h, opt.h: fixed bug #21433 (Calling mem_free/pbuf_free
+    from interrupt context isn't safe): set LWIP_USE_HEAP_FROM_INTERRUPT to 1
+    in lwipopts.h or use pbuf_free_callback(p)/mem_free_callback(m) to free pbufs
+    or heap memory from interrupt context
+
+  2008-03-26 Simon Goldschmidt
+  * tcp_in.c, tcp.c: fixed bug #22249: division by zero could occur if a remote
+    host sent a zero mss as TCP option.
+
+
+(STABLE-1.3.0)
+
+  ++ New features:
+
+  2008-03-10 Jonathan Larmour
+  * inet_chksum.c: Allow choice of one of the sample algorithms to be
+    made from lwipopts.h. Fix comment on how to override LWIP_CHKSUM.
+
+  2008-01-22 Frédéric Bernon
+  * tcp.c, tcp_in.c, tcp.h, opt.h: Rename LWIP_CALCULATE_EFF_SEND_MSS in 
+    TCP_CALCULATE_EFF_SEND_MSS to have coherent TCP options names.
+
+  2008-01-14 Frédéric Bernon
+  * rawapi.txt, api_msg.c, tcp.c, tcp_in.c, tcp.h: changes for task #7675 "Enable
+    to refuse data on a TCP_EVENT_RECV call". Important, behavior changes for the
+    tcp_recv callback (see rawapi.txt).
+
+  2008-01-14 Frédéric Bernon, Marc Chaland
+  * ip.c: Integrate patch #6369" ip_input : checking before realloc".
+  
+  2008-01-12 Frédéric Bernon
+  * tcpip.h, tcpip.c, api.h, api_lib.c, api_msg.c, sockets.c: replace the field
+    netconn::sem per netconn::op_completed like suggested for the task #7490
+    "Add return value to sys_mbox_post".
+
+  2008-01-12 Frédéric Bernon
+  * api_msg.c, opt.h: replace DEFAULT_RECVMBOX_SIZE per DEFAULT_TCP_RECVMBOX_SIZE,
+    DEFAULT_UDP_RECVMBOX_SIZE and DEFAULT_RAW_RECVMBOX_SIZE (to optimize queues
+    sizes), like suggested for the task #7490 "Add return value to sys_mbox_post".
+
+  2008-01-10 Frédéric Bernon
+  * tcpip.h, tcpip.c: add tcpip_callback_with_block function for the task #7490
+    "Add return value to sys_mbox_post". tcpip_callback is always defined as
+    "blocking" ("block" parameter = 1).
+
+  2008-01-10 Frédéric Bernon
+  * tcpip.h, tcpip.c, api.h, api_lib.c, api_msg.c, sockets.c: replace the field
+    netconn::mbox (sys_mbox_t) per netconn::sem (sys_sem_t) for the task #7490
+    "Add return value to sys_mbox_post".
+
+  2008-01-05 Frédéric Bernon
+  * sys_arch.txt, api.h, api_lib.c, api_msg.h, api_msg.c, tcpip.c, sys.h, opt.h:
+    Introduce changes for task #7490 "Add return value to sys_mbox_post" with some
+    modifications in the sys_mbox api: sys_mbox_new take a "size" parameters which
+    indicate the number of pointers query by the mailbox. There is three defines
+    in opt.h to indicate sizes for tcpip::mbox, netconn::recvmbox, and for the 
+    netconn::acceptmbox. Port maintainers, you can decide to just add this new 
+    parameter in your implementation, but to ignore it to keep the previous behavior.
+    The new sys_mbox_trypost function return a value to know if the mailbox is
+    full or if the message is posted. Take a look to sys_arch.txt for more details.
+    This new function is used in tcpip_input (so, can be called in an interrupt
+    context since the function is not blocking), and in recv_udp and recv_raw.
+
+  2008-01-04 Frédéric Bernon, Simon Goldschmidt, Jonathan Larmour
+  * rawapi.txt, api.h, api_lib.c, api_msg.h, api_msg.c, sockets.c, tcp.h, tcp.c,
+    tcp_in.c, init.c, opt.h: rename backlog options with TCP_ prefix, limit the
+    "backlog" parameter in an u8_t, 0 is interpreted as "smallest queue", add
+    documentation in the rawapi.txt file.
+
+  2007-12-31 Kieran Mansley (based on patch from Per-Henrik Lundbolm)
+  * tcp.c, tcp_in.c, tcp_out.c, tcp.h: Add TCP persist timer
+
+  2007-12-31 Frédéric Bernon, Luca Ceresoli
+  * autoip.c, etharp.c: ip_addr.h: Integrate patch #6348: "Broadcast ARP packets
+    in autoip". The change in etharp_raw could be removed, since all calls to
+    etharp_raw use ethbroadcast for the "ethdst_addr" parameter. But it could be
+    wrong in the future.
+
+  2007-12-30 Frédéric Bernon, Tom Evans
+  * ip.c: Fix bug #21846 "LwIP doesn't appear to perform any IP Source Address
+    Filtering" reported by Tom Evans.
+
+  2007-12-21 Frédéric Bernon, Simon Goldschmidt, Jonathan Larmour
+  * tcp.h, opt.h, api.h, api_msg.h, tcp.c, tcp_in.c, api_lib.c, api_msg.c,
+    sockets.c, init.c: task #7252: Implement TCP listen backlog: Warning: raw API
+    applications have to call 'tcp_accepted(pcb)' in their accept callback to
+    keep accepting new connections.
+
+  2007-12-13 Frédéric Bernon
+  * api_msg.c, err.h, err.c, sockets.c, dns.c, dns.h: replace "enum dns_result"
+    by err_t type. Add a new err_t code "ERR_INPROGRESS".
+
+  2007-12-12 Frédéric Bernon
+  * dns.h, dns.c, opt.h: move DNS options to the "right" place. Most visibles
+    are the one which have ram usage.
+
+  2007-12-05 Frédéric Bernon
+  * netdb.c: add a LWIP_DNS_API_HOSTENT_STORAGE option to decide to use a static
+    set of variables (=0) or a local one (=1). In this last case, your port should
+    provide a function "struct hostent* sys_thread_hostent( struct hostent* h)"
+    which have to do a copy of "h" and return a pointer ont the "per-thread" copy.
+
+  2007-12-03 Simon Goldschmidt
+  * ip.c: ip_input: check if a packet is for inp first before checking all other
+    netifs on netif_list (speeds up packet receiving in most cases)
+
+  2007-11-30 Simon Goldschmidt
+  * udp.c, raw.c: task #7497: Sort lists (pcb, netif, ...) for faster access
+    UDP: move a (connected) pcb selected for input to the front of the list of
+    pcbs so that it is found faster next time. Same for RAW pcbs that have eaten
+    a packet.
+
+  2007-11-28 Simon Goldschmidt
+  * etharp.c, stats.c, stats.h, opt.h: Introduced ETHARP_STATS
+
+  2007-11-25 Simon Goldschmidt
+  * dhcp.c: dhcp_unfold_reply() uses pbuf_copy_partial instead of its own copy
+    algorithm.
+
+  2007-11-24 Simon Goldschmidt
+  * netdb.h, netdb.c, sockets.h/.c: Moved lwip_gethostbyname from sockets.c
+    to the new file netdb.c; included lwip_getaddrinfo.
+
+  2007-11-21 Simon Goldschmidt
+  * tcp.h, opt.h, tcp.c, tcp_in.c: implemented calculating the effective send-mss
+    based on the MTU of the netif used to send. Enabled by default. Disable by
+    setting LWIP_CALCULATE_EFF_SEND_MSS to 0. This fixes bug #21492.
+
+  2007-11-19 Frédéric Bernon
+  * api_msg.c, dns.h, dns.c: Implement DNS_DOES_NAME_CHECK option (check if name
+    received match the name query), implement DNS_USES_STATIC_BUF (the place where
+    copy dns payload to parse the response), return an error if there is no place
+    for a new query, and fix some minor problems.
+
+  2007-11-16 Simon Goldschmidt
+  * new files: ipv4/inet.c, ipv4/inet_chksum.c, ipv6/inet6.c
+    removed files: core/inet.c, core/inet6.c
+    Moved inet files into ipv4/ipv6 directory; splitted inet.c/inet.h into
+    inet and chksum part; changed includes in all lwIP files as appropriate
+
+  2007-11-16 Simon Goldschmidt
+  * api.h, api_msg.h, api_lib.c, api_msg.c, socket.h, socket.c: Added sequential
+    dns resolver function for netconn api (netconn_gethostbyname) and socket api
+    (gethostbyname/gethostbyname_r).
+
+  2007-11-15 Jim Pettinato, Frédéric Bernon
+  * opt.h, init.c, tcpip.c, dhcp.c, dns.h, dns.c: add DNS client for simple name
+    requests with RAW api interface. Initialization is done in lwip_init() with
+    build time options. DNS timer is added in tcpip_thread context. DHCP can set
+    DNS server ip addresses when options are received. You need to set LWIP_DNS=1
+    in your lwipopts.h file (LWIP_DNS=0 in opt.h). DNS_DEBUG can be set to get
+    some traces with LWIP_DEBUGF. Sanity check have been added. There is a "todo"
+    list with points to improve.
+
+  2007-11-06 Simon Goldschmidt
+  * opt.h, mib2.c: Patch #6215: added ifAdminStatus write support (if explicitly
+    enabled by defining SNMP_SAFE_REQUESTS to 0); added code to check link status
+    for ifOperStatus if LWIP_NETIF_LINK_CALLBACK is defined.
+
+  2007-11-06 Simon Goldschmidt
+  * api.h, api_msg.h and dependent files: Task #7410: Removed the need to include
+    core header files in api.h (ip/tcp/udp/raw.h) to hide the internal
+    implementation from netconn api applications.
+
+  2007-11-03 Frédéric Bernon
+  * api.h, api_lib.c, api_msg.c, sockets.c, opt.h: add SO_RCVBUF option for UDP &
+    RAW netconn. You need to set LWIP_SO_RCVBUF=1 in your lwipopts.h (it's disabled
+    by default). Netconn API users can use the netconn_recv_bufsize macro to access
+    it. This is a first release which have to be improve for TCP. Note it used the
+    netconn::recv_avail which need to be more "thread-safe" (note there is already
+    the problem for FIONREAD with lwip_ioctl/ioctlsocket).
+
+  2007-11-01 Frédéric Bernon, Marc Chaland
+  * sockets.h, sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c, tcp.h, tcp_out.c:
+    Integrate "patch #6250 : MSG_MORE flag for send". MSG_MORE is used at socket api
+    layer, NETCONN_MORE at netconn api layer, and TCP_WRITE_FLAG_MORE at raw api
+    layer. This option enable to delayed TCP PUSH flag on multiple "write" calls.
+    Note that previous "copy" parameter for "write" APIs is now called "apiflags".
+
+  2007-10-24 Frédéric Bernon
+  * api.h, api_lib.c, api_msg.c: Add macro API_EVENT in the same spirit than 
+    TCP_EVENT_xxx macros to get a code more readable. It could also help to remove
+    some code (like we have talk in "patch #5919 : Create compile switch to remove
+    select code"), but it could be done later.
+
+  2007-10-08 Simon Goldschmidt
+  * many files: Changed initialization: many init functions are not needed any
+    more since we now rely on the compiler initializing global and static
+    variables to zero!
+
+  2007-10-06 Simon Goldschmidt
+  * ip_frag.c, memp.c, mib2.c, ip_frag.h, memp_std.h, opt.h: Changed IP_REASSEMBLY
+    to enqueue the received pbufs so that multiple packets can be reassembled
+    simultaneously and no static reassembly buffer is needed.
+
+  2007-10-05 Simon Goldschmidt
+  * tcpip.c, etharp.h, etharp.c: moved ethernet_input from tcpip.c to etharp.c so
+    all netifs (or ports) can use it.
+
+  2007-10-05 Frédéric Bernon
+  * netifapi.h, netifapi.c: add function netifapi_netif_set_default. Change the 
+    common function to reduce a little bit the footprint (for all functions using
+    only the "netif" parameter).
+
+  2007-10-03 Frédéric Bernon
+  * netifapi.h, netifapi.c: add functions netifapi_netif_set_up, netifapi_netif_set_down,
+    netifapi_autoip_start and netifapi_autoip_stop. Use a common function to reduce
+    a little bit the footprint (for all functions using only the "netif" parameter).
+
+  2007-09-15 Frédéric Bernon
+  * udp.h, udp.c, sockets.c: Changes for "#20503 IGMP Improvement". Add IP_MULTICAST_IF
+    option in socket API, and a new field "multicast_ip" in "struct udp_pcb" (for
+    netconn and raw API users), only if LWIP_IGMP=1. Add getsockopt processing for
+    IP_MULTICAST_TTL and IP_MULTICAST_IF.
+
+  2007-09-10 Frédéric Bernon
+  * snmp.h, mib2.c: enable to remove SNMP timer (which consumne several cycles
+    even when it's not necessary). snmp_agent.txt tell to call snmp_inc_sysuptime()
+    each 10ms (but, it's intrusive if you use sys_timeout feature). Now, you can
+    decide to call snmp_add_sysuptime(100) each 1000ms (which is bigger "step", but
+    call to a lower frequency). Or, you can decide to not call snmp_inc_sysuptime()
+    or snmp_add_sysuptime(), and to define the SNMP_GET_SYSUPTIME(sysuptime) macro.
+    This one is undefined by default in mib2.c. SNMP_GET_SYSUPTIME is called inside
+    snmp_get_sysuptime(u32_t *value), and enable to change "sysuptime" value only
+    when it's queried (any direct call to "sysuptime" is changed by a call to 
+    snmp_get_sysuptime).
+
+  2007-09-09 Frédéric Bernon, Bill Florac
+  * igmp.h, igmp.c, netif.h, netif.c, ip.c: To enable to have interfaces with IGMP,
+    and others without it, there is a new NETIF_FLAG_IGMP flag to set in netif->flags
+    if you want IGMP on an interface. igmp_stop() is now called inside netif_remove().
+    igmp_report_groups() is now called inside netif_set_link_up() (need to have
+    LWIP_NETIF_LINK_CALLBACK=1) to resend reports once the link is up (avoid to wait
+    the next query message to receive the matching multicast streams).
+
+  2007-09-08 Frédéric Bernon
+  * sockets.c, ip.h, api.h, tcp.h: declare a "struct ip_pcb" which only contains
+    IP_PCB. Add in the netconn's "pcb" union a "struct ip_pcb *ip;" (no size change).
+    Use this new field to access to common pcb fields (ttl, tos, so_options, etc...).
+    Enable to access to these fields with LWIP_TCP=0.
+
+  2007-09-05 Frédéric Bernon
+  * udp.c, ipv4/icmp.c, ipv4/ip.c, ipv6/icmp.c, ipv6/ip6.c, ipv4/icmp.h,
+    ipv6/icmp.h, opt.h: Integrate "task #7272 : LWIP_ICMP option". The new option
+    LWIP_ICMP enable/disable ICMP module inside the IP stack (enable per default).
+    Be careful, disabling ICMP make your product non-compliant to RFC1122, but
+    help to reduce footprint, and to reduce "visibility" on the Internet.
+
+  2007-09-05 Frédéric Bernon, Bill Florac
+  * opt.h, sys.h, tcpip.c, slipif.c, ppp.c, sys_arch.txt: Change parameters list
+    for sys_thread_new (see "task #7252 : Create sys_thread_new_ex()"). Two new
+    parameters have to be provided: a task name, and a task stack size. For this
+    one, since it's platform dependant, you could define the best one for you in
+    your lwipopts.h. For port maintainers, you can just add these new parameters
+    in your sys_arch.c file, and but it's not mandatory, use them in your OS
+    specific functions.
+
+  2007-09-05 Frédéric Bernon
+  * inet.c, autoip.c, msg_in.c, msg_out.c, init.c: Move some build time checkings
+    inside init.c for task #7142 "Sanity check user-configurable values".
+
+  2007-09-04 Frédéric Bernon, Bill Florac
+  * igmp.h, igmp.c, memp_std.h, memp.c, init.c, opt.h: Replace mem_malloc call by
+    memp_malloc, and use a new MEMP_NUM_IGMP_GROUP option (see opt.h to define the
+    value). It will avoid potential fragmentation problems, use a counter to know
+    how many times a group is used on an netif, and free it when all applications
+    leave it. MEMP_NUM_IGMP_GROUP got 8 as default value (and init.c got a sanity
+    check if LWIP_IGMP!=0).
+
+  2007-09-03 Frédéric Bernon
+  * igmp.h, igmp.c, sockets.c, api_msg.c: Changes for "#20503 IGMP Improvement".
+    Initialize igmp_mac_filter to NULL in netif_add (this field should be set in
+    the netif's "init" function). Use the "imr_interface" field (for socket layer)
+    and/or the "interface" field (for netconn layer), for join/leave operations.
+    The igmp_join/leavegroup first parameter change from a netif to an ipaddr.
+    This field could be a netif's ipaddr, or "any" (same meaning than ip_addr_isany).
+
+  2007-08-30 Frédéric Bernon
+  * Add netbuf.h, netbuf.c, Change api.h, api_lib.c: #7249 "Split netbuf functions
+    from api/api_lib". Now netbuf API is independant of netconn, and can be used
+    with other API (application based on raw API, or future "socket2" API). Ports
+    maintainers just have to add src/api/netbuf.c in their makefile/projects.
+
+  2007-08-30 Frédéric Bernon, Jonathan Larmour
+  * init.c: Add first version of lwip_sanity_check for task #7142 "Sanity check
+    user-configurable values".
+
+  2007-08-29 Frédéric Bernon
+  * igmp.h, igmp.c, tcpip.c, init.c, netif.c: change igmp_init and add igmp_start.
+    igmp_start is call inside netif_add. Now, igmp initialization is in the same
+    spirit than the others modules. Modify some IGMP debug traces.
+
+  2007-08-29 Frédéric Bernon
+  * Add init.h, init.c, Change opt.h, tcpip.c: Task  #7213 "Add a lwip_init function"
+    Add lwip_init function to regroup all modules initializations, and to provide
+    a place to add code for task #7142 "Sanity check user-configurable values".
+    Ports maintainers should remove direct initializations calls from their code,
+    and add init.c in their makefiles. Note that lwip_init() function is called
+    inside tcpip_init, but can also be used by raw api users since all calls are
+    disabled when matching options are disabled. Also note that their is new options
+    in opt.h, you should configure in your lwipopts.h (they are enabled per default).
+
+  2007-08-26 Marc Boucher
+  * api_msg.c: do_close_internal(): Reset the callbacks and arg (conn) to NULL
+    since they can under certain circumstances be called with an invalid conn
+    pointer after the connection has been closed (and conn has been freed). 
+
+  2007-08-25 Frédéric Bernon (Artem Migaev's Patch)
+  * netif.h, netif.c: Integrate "patch #6163 : Function to check if link layer is up".
+    Add a netif_is_link_up() function if LWIP_NETIF_LINK_CALLBACK option is set.
+
+  2007-08-22 Frédéric Bernon
+  * netif.h, netif.c, opt.h: Rename LWIP_NETIF_CALLBACK in LWIP_NETIF_STATUS_CALLBACK
+    to be coherent with new LWIP_NETIF_LINK_CALLBACK option before next release.
+
+  2007-08-22 Frédéric Bernon
+  * tcpip.h, tcpip.c, ethernetif.c, opt.h: remove options ETHARP_TCPIP_INPUT &
+    ETHARP_TCPIP_ETHINPUT, now, only "ethinput" code is supported, even if the 
+    name is tcpip_input (we keep the name of 1.2.0 function).
+
+  2007-08-17 Jared Grubb
+  * memp_std.h, memp.h, memp.c, mem.c, stats.c: (Task #7136) Centralize mempool 
+    settings into new memp_std.h and optional user file lwippools.h. This adds
+    more dynamic mempools, and allows the user to create an arbitrary number of
+    mempools for mem_malloc.
+
+  2007-08-16 Marc Boucher
+  * api_msg.c: Initialize newconn->state to NETCONN_NONE in accept_function;
+    otherwise it was left to NETCONN_CLOSE and sent_tcp() could prematurely
+    close the connection.
+
+  2007-08-16 Marc Boucher
+  * sockets.c: lwip_accept(): check netconn_peer() error return.
+
+  2007-08-16 Marc Boucher
+  * mem.c, mem.h: Added mem_calloc().
+
+  2007-08-16 Marc Boucher
+  * tcpip.c, tcpip.h memp.c, memp.h: Added distinct memp (MEMP_TCPIP_MSG_INPKT)
+    for input packets to prevent floods from consuming all of MEMP_TCPIP_MSG
+    and starving other message types.
+    Renamed MEMP_TCPIP_MSG to MEMP_TCPIP_MSG_API
+
+  2007-08-16 Marc Boucher
+  * pbuf.c, pbuf.h, etharp.c, tcp_in.c, sockets.c: Split pbuf flags in pbuf
+    type and flgs (later renamed to flags).
+    Use enum pbuf_flag as pbuf_type.  Renumber PBUF_FLAG_*.
+    Improved lwip_recvfrom().  TCP push now propagated.
+
+  2007-08-16 Marc Boucher
+  * ethernetif.c, contrib/ports/various: ethbroadcast now a shared global
+    provided by etharp.
+
+  2007-08-16 Marc Boucher
+  * ppp_oe.c ppp_oe.h, auth.c chap.c fsm.c lcp.c ppp.c ppp.h,
+    etharp.c ethernetif.c, etharp.h, opt.h tcpip.h, tcpip.c:
+    Added PPPoE support and various PPP improvements.
+
+  2007-07-25 Simon Goldschmidt
+  * api_lib.c, ip_frag.c, pbuf.c, api.h, pbuf.h: Introduced pbuf_copy_partial,
+    making netbuf_copy_partial use this function.
+
+  2007-07-25 Simon Goldschmidt
+  * tcp_in.c: Fix bug #20506: Slow start / initial congestion window starts with
+    2 * mss (instead of 1 * mss previously) to comply with some newer RFCs and
+    other stacks.
+
+  2007-07-13 Jared Grubb (integrated by Frédéric Bernon)
+  * opt.h, netif.h, netif.c, ethernetif.c: Add new configuration option to add
+    a link callback in the netif struct, and functions to handle it. Be carefull
+    for port maintainers to add the NETIF_FLAG_LINK_UP flag (like in ethernetif.c)
+    if you want to be sure to be compatible with future changes...
+
+  2007-06-30 Frédéric Bernon
+  * sockets.h, sockets.c: Implement MSG_PEEK flag for recv/recvfrom functions.
+
+  2007-06-21 Simon Goldschmidt
+  * etharp.h, etharp.c: Combined etharp_request with etharp_raw for both
+    LWIP_AUTOIP =0 and =1 to remove redundant code.
+
+  2007-06-21 Simon Goldschmidt
+  * mem.c, memp.c, mem.h, memp.h, opt.h: task #6863: Introduced the option
+    MEM_USE_POOLS to use 4 pools with different sized elements instead of a
+    heap. This both prevents memory fragmentation and gives a higher speed
+    at the cost of more memory consumption. Turned off by default.
+
+  2007-06-21 Simon Goldschmidt
+  * api_lib.c, api_msg.c, api.h, api_msg.h: Converted the length argument of
+    netconn_write (and therefore also api_msg_msg.msg.w.len) from u16_t into
+    int to be able to send a bigger buffer than 64K with one time (mainly
+    used from lwip_send).
+
+  2007-06-21 Simon Goldschmidt
+  * tcp.h, api_msg.c: Moved the nagle algorithm from netconn_write/do_write
+    into a define (tcp_output_nagle) in tcp.h to provide it to raw api users, too.
+
+  2007-06-21 Simon Goldschmidt
+  * api.h, api_lib.c, api_msg.c: Fixed bug #20021: Moved sendbuf-processing in
+    netconn_write from api_lib.c to api_msg.c to also prevent multiple context-
+    changes on low memory or empty send-buffer.
+
+  2007-06-18 Simon Goldschmidt
+  * etharp.c, etharp.h: Changed etharp to use a defined hardware address length
+    of 6 to avoid loading netif->hwaddr_len every time (since this file is only
+    used for ethernet and struct eth_addr already had a defined length of 6).
+
+  2007-06-17 Simon Goldschmidt
+  * sockets.c, sockets.h: Implemented socket options SO_NO_CHECK for UDP sockets
+    to disable UDP checksum generation on transmit.
+
+  2007-06-13 Frédéric Bernon, Simon Goldschmidt
+  * debug.h, api_msg.c: change LWIP_ERROR to use it to check errors like invalid
+    pointers or parameters, and let the possibility to redefined it in cc.h. Use
+    this macro to check "conn" parameter in api_msg.c functions.
+
+  2007-06-11 Simon Goldschmidt
+  * sockets.c, sockets.h: Added UDP lite support for sockets
+
+  2007-06-10 Simon Goldschmidt
+  * udp.h, opt.h, api_msg.c, ip.c, udp.c: Included switch LWIP_UDPLITE (enabled
+    by default) to switch off UDP-Lite support if not needed (reduces udp.c code
+    size)
+
+  2007-06-09 Dominik Spies (integrated by Frédéric Bernon)
+  * autoip.h, autoip.c, dhcp.h, dhcp.c, netif.h, netif.c, etharp.h, etharp.c, opt.h:
+    AutoIP implementation available for IPv4, with new options LWIP_AUTOIP and
+    LWIP_DHCP_AUTOIP_COOP if you want to cooperate with DHCP. Some tips to adapt
+    (see TODO mark in the source code).
+
+  2007-06-09 Simon Goldschmidt
+  * etharp.h, etharp.c, ethernetif.c: Modified order of parameters for
+    etharp_output() to match netif->output so etharp_output() can be used
+    directly as netif->output to save one function call.
+
+  2007-06-08 Simon Goldschmidt
+  * netif.h, ethernetif.c, slipif.c, loopif.c: Added define
+    NETIF_INIT_SNMP(netif, type, speed) to initialize per-netif snmp variables,
+    added initialization of those to ethernetif, slipif and loopif.
+
+  2007-05-18 Simon Goldschmidt
+  * opt.h, ip_frag.c, ip_frag.h, ip.c: Added option IP_FRAG_USES_STATIC_BUF
+    (defaulting to off for now) that can be set to 0 to send fragmented
+    packets by passing PBUF_REFs down the stack.
+
+  2007-05-23 Frédéric Bernon
+  * api_lib.c: Implement SO_RCVTIMEO for accept and recv on TCP
+    connections, such present in patch #5959.
+
+  2007-05-23 Frédéric Bernon
+  * api.h, api_lib.c, api_msg.c, sockets.c: group the different NETCONN_UDPxxx
+    code in only one part...
+
+  2007-05-18 Simon Goldschmidt
+  * opt.h, memp.h, memp.c: Added option MEMP_OVERFLOW_CHECK to check for memp
+    elements to overflow. This is achieved by adding some bytes before and after
+    each pool element (increasing their size, of course), filling them with a
+    prominent value and checking them on freeing the element.
+    Set it to 2 to also check every element in every pool each time memp_malloc()
+    or memp_free() is called (slower but more helpful).
+
+  2007-05-10 Simon Goldschmidt
+  * opt.h, memp.h, memp.c, pbuf.c (see task #6831): use a new memp pool for
+    PBUF_POOL pbufs instead of the old pool implementation in pbuf.c to reduce
+    code size.
+
+  2007-05-11 Frédéric Bernon
+  * sockets.c, api_lib.c, api_msg.h, api_msg.c, netifapi.h, netifapi.c, tcpip.c:
+    Include a function pointer instead of a table index in the message to reduce
+    footprint. Disable some part of lwip_send and lwip_sendto if some options are
+    not set (LWIP_TCP, LWIP_UDP, LWIP_RAW).
+
+  2007-05-10 Simon Goldschmidt
+  * *.h (except netif/ppp/*.h): Included patch #5448: include '#ifdef __cplusplus
+    \ extern "C" {' in all header files. Now you can write your application using
+    the lwIP stack in C++ and simply #include the core files. Note I have left
+    out the netif/ppp/*h header files for now, since I don't know which files are
+    included by applications and which are for internal use only.
+
+  2007-05-09 Simon Goldschmidt
+  * opt.h, *.c/*.h: Included patch #5920: Create define to override C-library
+    memcpy. 2 Defines are created: MEMCPY() for normal memcpy, SMEMCPY() for
+    situations where some compilers might inline the copy and save a function
+    call. Also replaced all calls to memcpy() with calls to (S)MEMCPY().
+
+  2007-05-08 Simon Goldschmidt
+  * mem.h: If MEM_LIBC_MALLOC==1, allow the defines (e.g. mem_malloc() -> malloc())
+    to be overriden in case the C-library malloc implementation is not protected
+    against concurrent access.
+
+  2007-05-04 Simon Goldschmidt (Atte Kojo)
+  * etharp.c: Introduced fast one-entry-cache to speed up ARP lookup when sending
+    multiple packets to the same host.
+
+  2007-05-04 Frédéric Bernon, Jonathan Larmour
+  * sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c: Fix bug #19162 "lwip_sento: a possible
+    to corrupt remote addr/port connection state". Reduce problems "not enought memory" with
+    netbuf (if we receive lot of datagrams). Improve lwip_sendto (only one exchange between
+    sockets api and api_msg which run in tcpip_thread context). Add netconn_sento function.
+    Warning, if you directly access to "fromaddr" & "fromport" field from netbuf struct,
+    these fields are now renamed "addr" & "port".
+
+  2007-04-11 Jonathan Larmour
+  * sys.h, api_lib.c: Provide new sys_mbox_tryfetch function. Require ports to provide new
+    sys_arch_mbox_tryfetch function to get a message if one is there, otherwise return
+    with SYS_MBOX_EMPTY. sys_arch_mbox_tryfetch can be implemented as a function-like macro
+    by the port in sys_arch.h if desired.
+
+  2007-04-06 Frédéric Bernon, Simon Goldschmidt
+  * opt.h, tcpip.h, tcpip.c, netifapi.h, netifapi.c: New configuration option LWIP_NETIF_API
+    allow to use thread-safe functions to add/remove netif in list, and to start/stop dhcp
+    clients, using new functions from netifapi.h. Disable as default (no port change to do).
+
+  2007-04-05 Frédéric Bernon
+  * sockets.c: remplace ENOBUFS errors on alloc_socket by ENFILE to be more BSD compliant.
+
+  2007-04-04 Simon Goldschmidt
+  * arch.h, api_msg.c, dhcp.c, msg_in.c, sockets.c: Introduced #define LWIP_UNUSED_ARG(x)
+    use this for and architecture-independent form to tell the compiler you intentionally
+    are not using this variable. Can be overriden in cc.h.
+
+  2007-03-28 Frédéric Bernon
+  * opt.h, netif.h, dhcp.h, dhcp.c: New configuration option LWIP_NETIF_HOSTNAME allow to
+    define a hostname in netif struct (this is just a pointer, so, you can use a hardcoded
+    string, point on one of your's ethernetif field, or alloc a string you will free yourself).
+    It will be used by DHCP to register a client hostname, but can also be use when you call
+    snmp_set_sysname.
+
+  2007-03-28 Frédéric Bernon
+  * netif.h, netif.c: A new NETIF_FLAG_ETHARP flag is defined in netif.h, to allow to 
+    initialize a network interface's flag with. It tell this interface is an ethernet
+    device, and we can use ARP with it to do a "gratuitous ARP" (RFC 3220 "IP Mobility
+    Support for IPv4" section 4.6) when interface is "up" with netif_set_up().
+
+  2007-03-26 Frédéric Bernon, Jonathan Larmour
+  * opt.h, tcpip.c: New configuration option LWIP_ARP allow to disable ARP init at build
+    time if you only use PPP or SLIP. The default is enable. Note we don't have to call 
+    etharp_init in your port's initilization sequence if you use tcpip.c, because this call
+    is done in tcpip_init function.
+
+  2007-03-22 Frédéric Bernon
+  * stats.h, stats.c, msg_in.c: Stats counters can be change to u32_t if necessary with the
+    new option LWIP_STATS_LARGE. If you need this option, define LWIP_STATS_LARGE to 1 in
+    your lwipopts.h. More, unused counters are not defined in the stats structs, and not 
+    display by stats_display(). Note that some options (SYS_STATS and RAW_STATS) are defined
+    but never used. Fix msg_in.c with the correct #if test for a stat display.
+
+  2007-03-21 Kieran Mansley
+  * netif.c, netif.h: Apply patch#4197 with some changes (originator: rireland@hmgsl.com). 
+    Provides callback on netif up/down state change.
+
+  2007-03-11 Frédéric Bernon, Mace Gael, Steve Reynolds
+  * sockets.h, sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c, igmp.h, igmp.c,
+    ip.c, netif.h, tcpip.c, opt.h:
+    New configuration option LWIP_IGMP to enable IGMP processing. Based on only one 
+    filter per all network interfaces. Declare a new function in netif to enable to
+    control the MAC filter (to reduce lwIP traffic processing).
+
+  2007-03-11 Frédéric Bernon
+  * tcp.h, tcp.c, sockets.c, tcp_out.c, tcp_in.c, opt.h: Keepalive values can
+    be configured at run time with LWIP_TCP_KEEPALIVE, but don't change this
+    unless you know what you're doing (default are RFC1122 compliant). Note
+    that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set in seconds.
+
+  2007-03-08 Frédéric Bernon
+  * tcp.h: Keepalive values can be configured at compile time, but don't change
+    this unless you know what you're doing (default are RFC1122 compliant).
+
+  2007-03-08 Frédéric Bernon
+  * sockets.c, api.h, api_lib.c, tcpip.c, sys.h, sys.c, err.c, opt.h:
+    Implement LWIP_SO_RCVTIMEO configuration option to enable/disable SO_RCVTIMEO
+    on UDP sockets/netconn.
+
+  2007-03-08 Simon Goldschmidt
+  * snmp_msg.h, msg_in.c: SNMP UDP ports can be configured at compile time.
+
+  2007-03-06 Frédéric Bernon
+  * api.h, api_lib.c, sockets.h, sockets.c, tcpip.c, sys.h, sys.c, err.h: 
+    Implement SO_RCVTIMEO on UDP sockets/netconn.
+
+  2007-02-28 Kieran Mansley (based on patch from Simon Goldschmidt)
+  * api_lib.c, tcpip.c, memp.c, memp.h: make API msg structs allocated
+    on the stack and remove the API msg type from memp
+
+  2007-02-26 Jonathan Larmour (based on patch from Simon Goldschmidt)
+  * sockets.h, sockets.c: Move socket initialization to new
+    lwip_socket_init() function.
+    NOTE: this changes the API with ports. Ports will have to be
+    updated to call lwip_socket_init() now.
+
+  2007-02-26 Jonathan Larmour (based on patch from Simon Goldschmidt)
+  * api_lib.c: Use memcpy in netbuf_copy_partial.
+
+
+  ++ Bug fixes:
+
+  2008-03-17 Frédéric Bernon, Ed Kerekes
+  * igmp.h, igmp.c: Fix bug #22613 "IGMP iphdr problem" (could have
+    some problems to fill the IP header on some targets, use now the
+    ip.h macros to do it).
+
+  2008-03-13 Frédéric Bernon
+  * sockets.c: Fix bug #22435 "lwip_recvfrom with TCP break;". Using
+    (lwip_)recvfrom with valid "from" and "fromlen" parameters, on a
+    TCP connection caused a crash. Note that using (lwip_)recvfrom
+    like this is a bit slow and that using (lwip)getpeername is the
+    good lwip way to do it (so, using recv is faster on tcp sockets).
+
+  2008-03-12 Frédéric Bernon, Jonathan Larmour
+  * api_msg.c, contrib/apps/ping.c: Fix bug #22530 "api_msg.c's
+    recv_raw() does not consume data", and the ping sample (with
+    LWIP_SOCKET=1, the code did the wrong supposition that lwip_recvfrom
+    returned the IP payload, without the IP header).
+
+  2008-03-04 Jonathan Larmour
+  * mem.c, stats.c, mem.h: apply patch #6414 to avoid compiler errors
+  and/or warnings on some systems where mem_size_t and size_t differ.
+  * pbuf.c, ppp.c: Fix warnings on some systems with mem_malloc.
+
+  2008-03-04 Kieran Mansley (contributions by others) 
+  * Numerous small compiler error/warning fixes from contributions to
+    mailing list after 1.3.0 release candidate made.
+
+  2008-01-25 Cui hengbin (integrated by Frédéric Bernon)
+  * dns.c: Fix bug #22108 "DNS problem" caused by unaligned structures.
+
+  2008-01-15 Kieran Mansley
+  * tcp_out.c: BUG20511.  Modify persist timer to start when we are
+    prevented from sending by a small send window, not just a zero
+    send window.
+
+  2008-01-09 Jonathan Larmour
+  * opt.h, ip.c: Rename IP_OPTIONS define to IP_OPTIONS_ALLOWED to avoid
+    conflict with Linux system headers.
+
+  2008-01-06 Jonathan Larmour
+  * dhcp.c: fix bug #19927: "DHCP NACK problem" by clearing any existing set IP
+    address entirely on receiving a DHCPNAK, and restarting discovery.
+
+  2007-12-21 Simon Goldschmidt
+  * sys.h, api_lib.c, api_msg.c, sockets.c: fix bug #21698: "netconn->recv_avail
+    is not protected" by using new macros for interlocked access to modify/test
+    netconn->recv_avail.
+
+  2007-12-20 Kieran Mansley (based on patch from Oleg Tyshev)
+  * tcp_in.c: fix bug# 21535 (nrtx not reset correctly in SYN_SENT state)
+
+  2007-12-20 Kieran Mansley (based on patch from Per-Henrik Lundbolm)
+  * tcp.c, tcp_in.c, tcp_out.c, tcp.h: fix bug #20199 (better handling
+    of silly window avoidance and prevent lwIP from shrinking the window)
+
+  2007-12-04 Simon Goldschmidt
+  * tcp.c, tcp_in.c: fix bug #21699 (segment leak in ooseq processing when last
+    data packet was lost): add assert that all segment lists are empty in
+    tcp_pcb_remove before setting pcb to CLOSED state; don't directly set CLOSED
+    state from LAST_ACK in tcp_process
+
+  2007-12-02 Simon Goldschmidt
+  * sockets.h: fix bug #21654: exclude definition of struct timeval from #ifndef FD_SET
+    If including  for system-struct timeval, LWIP_TIMEVAL_PRIVATE now
+    has to be set to 0 in lwipopts.h
+
+  2007-12-02 Simon Goldschmidt
+  * api_msg.c, api_lib.c: fix bug #21656 (recvmbox problem in netconn API): always
+    allocate a recvmbox in netconn_new_with_proto_and_callback. For a tcp-listen
+    netconn, this recvmbox is later freed and a new mbox is allocated for acceptmbox.
+    This is a fix for thread-safety and allocates all items needed for a netconn
+    when the netconn is created.
+
+  2007-11-30 Simon Goldschmidt
+  * udp.c: first attempt to fix bug #21655 (DHCP doesn't work reliably with multiple
+    netifs): if LWIP_DHCP is enabled, UDP packets to DHCP_CLIENT_PORT are passed
+    to netif->dhcp->pcb only (if that exists) and not to any other pcb for the same
+    port (only solution to let UDP pcbs 'bind' to a netif instead of an IP address)
+
+  2007-11-27 Simon Goldschmidt
+  * ip.c: fixed bug #21643 (udp_send/raw_send don't fail if netif is down) by
+    letting ip_route only use netifs that are up.
+
+  2007-11-27 Simon Goldschmidt
+  * err.h, api_lib.c, api_msg.c, sockets.c: Changed error handling: ERR_MEM, ERR_BUF
+    and ERR_RTE are seen as non-fatal, all other errors are fatal. netconns and
+    sockets block most operations once they have seen a fatal error.
+
+  2007-11-27 Simon Goldschmidt
+  * udp.h, udp.c, dhcp.c: Implemented new function udp_sendto_if which takes the
+    netif to send as an argument (to be able to send on netifs that are down).
+
+  2007-11-26 Simon Goldschmidt
+  * tcp_in.c: Fixed bug #21582: pcb->acked accounting can be wrong when ACKs
+    arrive out-of-order
+
+  2007-11-21 Simon Goldschmidt
+  * tcp.h, tcp_out.c, api_msg.c: Fixed bug #20287: tcp_output_nagle sends too early
+    Fixed the nagle algorithm; nagle now also works for all raw API applications
+    and has to be explicitly disabled with 'tcp_pcb->flags |= TF_NODELAY'
+
+  2007-11-12 Frédéric Bernon
+  * sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c: Fixed bug #20900. Now, most
+    of the netconn_peer and netconn_addr processing is done inside tcpip_thread
+    context in do_getaddr.
+
+  2007-11-10 Simon Goldschmidt
+  * etharp.c: Fixed bug: assert fired when MEMP_ARP_QUEUE was empty (which can
+    happen any time). Now the packet simply isn't enqueued when out of memory.
+
+  2007-11-01 Simon Goldschmidt
+  * tcp.c, tcp_in.c: Fixed bug #21494: The send mss (pcb->mss) is set to 536 (or
+    TCP_MSS if that is smaller) as long as no MSS option is received from the
+    remote host.
+
+  2007-11-01 Simon Goldschmidt
+  * tcp.h, tcp.c, tcp_in.c: Fixed bug #21491: The MSS option sent (with SYN)
+    is now based on TCP_MSS instead of pcb->mss (on passive open now effectively
+    sending our configured TCP_MSS instead of the one received).
+
+  2007-11-01 Simon Goldschmidt
+  * tcp_in.c: Fixed bug #21181: On active open, the initial congestion window was
+    calculated based on the configured TCP_MSS, not on the MSS option received
+    with SYN+ACK.
+
+  2007-10-09 Simon Goldschmidt
+  * udp.c, inet.c, inet.h: Fixed UDPLite: send: Checksum was always generated too
+    short and also was generated wrong if checksum coverage != tot_len;
+    receive: checksum was calculated wrong if checksum coverage != tot_len
+
+  2007-10-08 Simon Goldschmidt
+  * mem.c: lfree was not updated in mem_realloc!
+
+  2007-10-07 Frédéric Bernon
+  * sockets.c, api.h, api_lib.c: First step to fix "bug #20900 : Potential
+    crash error problem with netconn_peer & netconn_addr". VERY IMPORTANT:
+    this change cause an API breakage for netconn_addr, since a parameter
+    type change. Any compiler should cause an error without any changes in
+    yours netconn_peer calls (so, it can't be a "silent change"). It also
+    reduce a little bit the footprint for socket layer (lwip_getpeername &
+    lwip_getsockname use now a common lwip_getaddrname function since 
+    netconn_peer & netconn_addr have the same parameters).
+
+  2007-09-20 Simon Goldschmidt
+  * tcp.c: Fixed bug #21080 (tcp_bind without check pcbs in TIME_WAIT state)
+    by checking  tcp_tw_pcbs also
+
+  2007-09-19 Simon Goldschmidt
+  * icmp.c: Fixed bug #21107 (didn't reset IP TTL in ICMP echo replies)
+
+  2007-09-15 Mike Kleshov
+  * mem.c: Fixed bug #21077 (inaccuracy in calculation of lwip_stat.mem.used)
+
+  2007-09-06 Frédéric Bernon
+  * several-files: replace some #include "arch/cc.h" by "lwip/arch.h", or simply remove
+    it as long as "lwip/opt.h" is included before (this one include "lwip/debug.h" which
+    already include "lwip/arch.h"). Like that, default defines are provided by "lwip/arch.h"
+    if they are not defined in cc.h, in the same spirit than "lwip/opt.h" for lwipopts.h.
+
+  2007-08-30 Frédéric Bernon
+  * igmp.h, igmp.c: Some changes to remove some redundant code, add some traces, 
+    and fix some coding style.
+
+  2007-08-28 Frédéric Bernon
+  * tcpip.c: Fix TCPIP_MSG_INPKT processing: now, tcpip_input can be used for any
+    kind of packets. These packets are considered like Ethernet packets (payload 
+    pointing to ethhdr) if the netif got the NETIF_FLAG_ETHARP flag. Else, packets 
+    are considered like IP packets (payload pointing to iphdr).
+
+  2007-08-27 Frédéric Bernon
+  * api.h, api_lib.c, api_msg.c: First fix for "bug #20900 : Potential crash error
+    problem with netconn_peer & netconn_addr". Introduce NETCONN_LISTEN netconn_state
+    and remove obsolete ones (NETCONN_RECV & NETCONN_ACCEPT).
+
+  2007-08-24 Kieran Mansley
+  * inet.c Modify (acc >> 16) test to ((acc >> 16) != 0) to help buggy
+    compiler (Paradigm C++)
+
+  2007-08-09 Frédéric Bernon, Bill Florac
+  * stats.h, stats.c, igmp.h, igmp.c, opt.h: Fix for bug #20503 : IGMP Improvement.
+    Introduce IGMP_STATS to centralize statistics management.
+
+  2007-08-09 Frédéric Bernon, Bill Florac
+  * udp.c: Fix for bug #20503 : IGMP Improvement. Enable to receive a multicast
+    packet on a udp pcb binded on an netif's IP address, and not on "any".
+
+  2007-08-09 Frédéric Bernon, Bill Florac
+  * igmp.h, igmp.c, ip.c: Fix minor changes from bug #20503 : IGMP Improvement.
+    This is mainly on using lookup/lookfor, and some coding styles...
+
+  2007-07-26 Frédéric Bernon (and "thedoctor")
+  * igmp.c: Fix bug #20595 to accept IGMPv3 "Query" messages.
+
+  2007-07-25 Simon Goldschmidt
+  * api_msg.c, tcp.c: Another fix for bug #20021: by not returning an error if
+    tcp_output fails in tcp_close, the code in do_close_internal gets simpler
+    (tcp_output is called again later from tcp timers).
+
+  2007-07-25 Simon Goldschmidt
+  * ip_frag.c: Fixed bug #20429: use the new pbuf_copy_partial instead of the old
+    copy_from_pbuf, which illegally modified the given pbuf.
+
+  2007-07-25 Simon Goldschmidt
+  * tcp_out.c: tcp_enqueue: pcb->snd_queuelen didn't work for chaine PBUF_RAMs:
+    changed snd_queuelen++ to snd_queuelen += pbuf_clen(p).
+
+  2007-07-24 Simon Goldschmidt
+  * api_msg.c, tcp.c: Fix bug #20480: Check the pcb passed to tcp_listen() for the
+    correct state (must be CLOSED).
+
+  2007-07-13 Thomas Taranowski (commited by Jared Grubb)
+  * memp.c: Fix bug #20478: memp_malloc returned NULL+MEMP_SIZE on failed
+    allocation. It now returns NULL.
+
+  2007-07-13 Frédéric Bernon
+  * api_msg.c: Fix bug #20318: api_msg "recv" callbacks don't call pbuf_free in
+    all error cases.
+
+  2007-07-13 Frédéric Bernon
+  * api_msg.c: Fix bug #20315: possible memory leak problem if tcp_listen failed,
+    because current code doesn't follow rawapi.txt documentation.
+
+  2007-07-13 Kieran Mansley
+  * src/core/tcp_in.c Apply patch#5741 from Oleg Tyshev to fix bug in
+    out of sequence processing of received packets
+
+  2007-07-03 Simon Goldschmidt
+  * nearly-all-files: Added assertions where PBUF_RAM pbufs are used and an
+    assumption is made that this pbuf is in one piece (i.e. not chained). These
+    assumptions clash with the possibility of converting to fully pool-based
+    pbuf implementations, where PBUF_RAM pbufs might be chained.
+
+  2007-07-03 Simon Goldschmidt
+  * api.h, api_lib.c, api_msg.c: Final fix for bug #20021 and some other problems
+    when closing tcp netconns: removed conn->sem, less context switches when
+    closing, both netconn_close and netconn_delete should safely close tcp
+    connections.
+
+  2007-07-02 Simon Goldschmidt
+  * ipv4/ip.h, ipv6/ip.h, opt.h, netif.h, etharp.h, ipv4/ip.c, netif.c, raw.c,
+    tcp_out.c, udp.c, etharp.c: Added option LWIP_NETIF_HWADDRHINT (default=off)
+    to cache ARP table indices with each pcb instead of single-entry cache for
+    the complete stack.
+
+  2007-07-02 Simon Goldschmidt
+  * tcp.h, tcp.c, tcp_in.c, tcp_out.c: Added some ASSERTS and casts to prevent
+    warnings when assigning to smaller types.
+
+  2007-06-28 Simon Goldschmidt
+  * tcp_out.c: Added check to prevent tcp_pcb->snd_queuelen from overflowing.
+
+  2007-06-28 Simon Goldschmidt
+  * tcp.h: Fixed bug #20287: Fixed nagle algorithm (sending was done too early if
+    a segment contained chained pbufs)
+
+  2007-06-28 Frédéric Bernon
+  * autoip.c: replace most of rand() calls by a macro LWIP_AUTOIP_RAND which compute
+    a "pseudo-random" value based on netif's MAC and some autoip fields. It's always
+    possible to define this macro in your own lwipopts.h to always use C library's
+    rand(). Note that autoip_create_rand_addr doesn't use this macro.
+
+  2007-06-28 Frédéric Bernon
+  * netifapi.h, netifapi.c, tcpip.h, tcpip.c: Update code to handle the option
+    LWIP_TCPIP_CORE_LOCKING, and do some changes to be coherent with last modifications
+    in api_lib/api_msg (use pointers and not type with table, etc...) 
+
+  2007-06-26 Simon Goldschmidt
+  * udp.h: Fixed bug #20259: struct udp_hdr was lacking the packin defines.
+
+  2007-06-25 Simon Goldschmidt
+  * udp.c: Fixed bug #20253: icmp_dest_unreach was called with a wrong p->payload
+    for udp packets with no matching pcb.
+
+  2007-06-25 Simon Goldschmidt
+  * udp.c: Fixed bug #20220: UDP PCB search in udp_input(): a non-local match
+    could get udp input packets if the remote side matched.
+
+  2007-06-13 Simon Goldschmidt
+  * netif.c: Fixed bug #20180 (TCP pcbs listening on IP_ADDR_ANY could get
+    changed in netif_set_ipaddr if previous netif->ip_addr.addr was 0.
+
+  2007-06-13 Simon Goldschmidt
+  * api_msg.c: pcb_new sets conn->err if protocol is not implemented
+    -> netconn_new_..() does not allocate a new connection for unsupported
+    protocols.
+
+  2007-06-13 Frédéric Bernon, Simon Goldschmidt
+  * api_lib.c: change return expression in netconn_addr and netconn_peer, because
+    conn->err was reset to ERR_OK without any reasons (and error was lost)...
+
+  2007-06-13 Frédéric Bernon, Matthias Weisser
+  * opt.h, mem.h, mem.c, memp.c, pbuf.c, ip_frag.c, vj.c: Fix bug #20162. Rename
+    MEM_ALIGN in LWIP_MEM_ALIGN and MEM_ALIGN_SIZE in LWIP_MEM_ALIGN_SIZE to avoid
+    some macro names collision with some OS macros.
+
+  2007-06-11 Simon Goldschmidt
+  * udp.c: UDP Lite: corrected the use of chksum_len (based on RFC3828: if it's 0,
+    create checksum over the complete packet. On RX, if it's < 8 (and not 0),
+    discard the packet. Also removed the duplicate 'udphdr->chksum = 0' for both
+    UDP & UDP Lite.
+
+  2007-06-11 Srinivas Gollakota & Oleg Tyshev
+  * tcp_out.c: Fix for bug #20075 : "A problem with keep-alive timer and TCP flags"
+    where TCP flags wasn't initialized in tcp_keepalive.
+
+  2007-06-03 Simon Goldschmidt
+  * udp.c: udp_input(): Input pbuf was not freed if pcb had no recv function
+    registered, p->payload was modified without modifying p->len if sending
+    icmp_dest_unreach() (had no negative effect but was definitively wrong).
+
+  2007-06-03 Simon Goldschmidt
+  * icmp.c: Corrected bug #19937: For responding to an icmp echo request, icmp
+    re-used the input pbuf even if that didn't have enough space to include the
+    link headers. Now the space is tested and a new pbuf is allocated for the
+    echo response packet if the echo request pbuf isn't big enough.
+
+  2007-06-01 Simon Goldschmidt
+  * sockets.c: Checked in patch #5914: Moved sockopt processing into tcpip_thread.
+
+  2007-05-23 Frédéric Bernon
+  * api_lib.c, sockets.c: Fixed bug #5958 for netconn_listen (acceptmbox only
+    allocated by do_listen if success) and netconn_accept errors handling. In
+    most of api_lib functions, we replace some errors checkings like "if (conn==NULL)"
+    by ASSERT, except for netconn_delete.
+
+  2007-05-23 Frédéric Bernon
+  * api_lib.c: Fixed bug #5957 "Safe-thread problem inside netconn_recv" to return
+    an error code if it's impossible to fetch a pbuf on a TCP connection (and not
+    directly close the recvmbox).
+
+  2007-05-22 Simon Goldschmidt
+  * tcp.c: Fixed bug #1895 (tcp_bind not correct) by introducing a list of
+    bound but unconnected (and non-listening) tcp_pcbs.
+
+  2007-05-22 Frédéric Bernon
+  * sys.h, sys.c, api_lib.c, tcpip.c: remove sys_mbox_fetch_timeout() (was only
+    used for LWIP_SO_RCVTIMEO option) and use sys_arch_mbox_fetch() instead of
+    sys_mbox_fetch() in api files. Now, users SHOULD NOT use internal lwIP features
+    like "sys_timeout" in their application threads.
+
+  2007-05-22 Frédéric Bernon
+  * api.h, api_lib.c, api_msg.h, api_msg.c: change the struct api_msg_msg to see
+    which parameters are used by which do_xxx function, and to avoid "misusing"
+    parameters (patch #5938).
+
+  2007-05-22 Simon Goldschmidt
+  * api_lib.c, api_msg.c, raw.c, api.h, api_msg.h, raw.h: Included patch #5938:
+    changed raw_pcb.protocol from u16_t to u8_t since for IPv4 and IPv6, proto
+    is only 8 bits wide. This affects the api, as there, the protocol was
+    u16_t, too.
+
+  2007-05-18 Simon Goldschmidt
+  * memp.c: addition to patch #5913: smaller pointer was returned but
+    memp_memory was the same size -> did not save memory.
+
+  2007-05-16 Simon Goldschmidt
+  * loopif.c, slipif.c: Fix bug #19729: free pbuf if netif->input() returns
+    != ERR_OK.
+
+  2007-05-16 Simon Goldschmidt
+  * api_msg.c, udp.c: If a udp_pcb has a local_ip set, check if it is the same
+    as the one of the netif used for sending to prevent sending from old
+    addresses after a netif address gets changed (partly fixes bug #3168).
+
+  2007-05-16 Frédéric Bernon
+  * tcpip.c, igmp.h, igmp.c: Fixed bug "#19800 : IGMP: igmp_tick() will not work
+    with NO_SYS=1". Note that igmp_init is always in tcpip_thread (and not in 
+    tcpip_init) because we have to be sure that network interfaces are already
+    added (mac filter is updated only in igmp_init for the moment).
+
+  2007-05-16 Simon Goldschmidt
+  * mem.c, memp.c: Removed semaphores from memp, changed sys_sem_wait calls
+    into sys_arch_sem_wait calls to prevent timers from running while waiting
+    for the heap. This fixes bug #19167.
+
+  2007-05-13 Simon Goldschmidt
+  * tcp.h, sockets.h, sockets.c: Fixed bug from patch #5865 by moving the defines
+    for socket options (lwip_set/-getsockopt) used with level IPPROTO_TCP from
+    tcp.h to sockets.h.
+
+  2007-05-07 Simon Goldschmidt
+  * mem.c: Another attempt to fix bug #17922.
+
+  2007-05-04 Simon Goldschmidt
+  * pbuf.c, pbuf.h, etharp.c: Further update to ARP queueing: Changed pbuf_copy()
+    implementation so that it can be reused (don't allocate the target
+    pbuf inside pbuf_copy()).
+
+  2007-05-04 Simon Goldschmidt
+  * memp.c: checked in patch #5913: in memp_malloc() we can return memp as mem
+    to save a little RAM (next pointer of memp is not used while not in pool).
+
+  2007-05-03 "maq"
+  * sockets.c: Fix ioctl FIONREAD when some data remains from last recv.
+    (patch #3574).
+
+  2007-04-23 Simon Goldschmidt
+  * loopif.c, loopif.h, opt.h, src/netif/FILES: fix bug #2595: "loopif results
+    in NULL reference for incoming TCP packets". Loopif has to be configured
+    (using LWIP_LOOPIF_MULTITHREADING) to directly call netif->input()
+    (multithreading environments, e.g. netif->input() = tcpip_input()) or
+    putting packets on a list that is fed to the stack by calling loopif_poll()
+    (single-thread / NO_SYS / polling environment where e.g.
+    netif->input() = ip_input).
+
+  2007-04-17 Jonathan Larmour
+  * pbuf.c: Use s32_t in pbuf_realloc(), as an s16_t can't reliably hold
+    the difference between two u16_t's.
+  * sockets.h: FD_SETSIZE needs to match number of sockets, which is
+    MEMP_NUM_NETCONN in sockets.c right now.
+
+  2007-04-12 Jonathan Larmour
+  * icmp.c: Reset IP header TTL in ICMP ECHO responses (bug #19580).
+
+  2007-04-12 Kieran Mansley
+  * tcp.c, tcp_in.c, tcp_out.c, tcp.h: Modify way the retransmission
+    timer is reset to fix bug#19434, with help from Oleg Tyshev.
+
+  2007-04-11 Simon Goldschmidt
+  * etharp.c, pbuf.c, pbuf.h: 3rd fix for bug #11400 (arp-queuing): More pbufs than
+    previously thought need to be copied (everything but PBUF_ROM!). Cleaned up
+    pbuf.c: removed functions no needed any more (by etharp).
+
+  2007-04-11 Kieran Mansley
+  * inet.c, ip_addr.h, sockets.h, sys.h, tcp.h: Apply patch #5745: Fix
+    "Constant is long" warnings with 16bit compilers.  Contributed by
+    avatar@mmlab.cse.yzu.edu.tw
+
+  2007-04-05 Frédéric Bernon, Jonathan Larmour
+  * api_msg.c: Fix bug #16830: "err_tcp() posts to connection mailbox when no pend on
+    the mailbox is active". Now, the post is only done during a connect, and do_send,
+    do_write and do_join_leave_group don't do anything if a previous error was signaled.
+
+  2007-04-03 Frédéric Bernon
+  * ip.c: Don't set the IP_DF ("Don't fragment") flag in the IP header in IP output
+    packets. See patch #5834.
+
+  2007-03-30 Frédéric Bernon
+  * api_msg.c: add a "pcb_new" helper function to avoid redundant code, and to add
+    missing  pcb allocations checking (in do_bind, and for each raw_new). Fix style.
+
+  2007-03-30 Frédéric Bernon
+  * most of files: prefix all debug.h define with "LWIP_" to avoid any conflict with
+    others environment defines (these were too "generic").
+
+  2007-03-28 Frédéric Bernon
+  * api.h, api_lib.c, sockets.c: netbuf_ref doesn't check its internal pbuf_alloc call
+    result and can cause a crash. lwip_send now check netbuf_ref result.
+
+  2007-03-28 Simon Goldschmidt
+  * sockets.c Remove "#include " from sockets.c to avoid multiple
+    definition of macros (in errno.h and lwip/arch.h) if LWIP_PROVIDE_ERRNO is
+    defined. This is the way it should have been already (looking at
+    doc/sys_arch.txt)
+
+  2007-03-28 Kieran Mansley
+  * opt.h Change default PBUF_POOL_BUFSIZE (again) to accomodate default MSS +
+    IP and TCP headers *and* physical link headers
+
+  2007-03-26 Frédéric Bernon (based on patch from Dmitry Potapov)
+  * api_lib.c: patch for netconn_write(), fixes a possible race condition which cause
+    to send some garbage. It is not a definitive solution, but the patch does solve
+    the problem for most cases.
+
+  2007-03-22 Frédéric Bernon
+  * api_msg.h, api_msg.c: Remove obsolete API_MSG_ACCEPT and do_accept (never used).
+
+  2007-03-22 Frédéric Bernon
+  * api_lib.c: somes resources couldn't be freed if there was errors during
+    netconn_new_with_proto_and_callback.
+
+  2007-03-22 Frédéric Bernon
+  * ethernetif.c: update netif->input calls to check return value. In older ports,
+    it's a good idea to upgrade them, even if before, there could be another problem
+    (access to an uninitialized mailbox).
+
+  2007-03-21 Simon Goldschmidt
+  * sockets.c: fixed bug #5067 (essentialy a signed/unsigned warning fixed
+    by casting to unsigned).
+
+  2007-03-21 Frédéric Bernon
+  * api_lib.c, api_msg.c, tcpip.c: integrate sys_mbox_fetch(conn->mbox, NULL) calls from
+    api_lib.c to tcpip.c's tcpip_apimsg(). Now, use a local variable and not a
+    dynamic one from memp to send tcpip_msg to tcpip_thread in a synchrone call.
+    Free tcpip_msg from tcpip_apimsg is not done in tcpip_thread. This give a
+    faster and more reliable communication between api_lib and tcpip.
+
+  2007-03-21 Frédéric Bernon
+  * opt.h: Add LWIP_NETIF_CALLBACK (to avoid compiler warning) and set it to 0.
+
+  2007-03-21 Frédéric Bernon
+  * api_msg.c, igmp.c, igmp.h: Fix C++ style comments
+
+  2007-03-21 Kieran Mansley
+  * opt.h Change default PBUF_POOL_BUFSIZE to accomodate default MSS +
+    IP and TCP headers
+
+  2007-03-21 Kieran Mansley
+  * Fix all uses of pbuf_header to check the return value.  In some
+    cases just assert if it fails as I'm not sure how to fix them, but
+    this is no worse than before when they would carry on regardless
+    of the failure.
+
+  2007-03-21 Kieran Mansley
+  * sockets.c, igmp.c, igmp.h, memp.h: Fix C++ style comments and
+    comment out missing header include in icmp.c
+
+  2007-03-20 Frédéric Bernon
+  * memp.h, stats.c: Fix stats_display function where memp_names table wasn't
+    synchronized with memp.h.
+
+  2007-03-20 Frédéric Bernon
+  * tcpip.c: Initialize tcpip's mbox, and verify if initialized in tcpip_input,
+    tcpip_ethinput, tcpip_callback, tcpip_apimsg, to fix a init problem with 
+    network interfaces. Also fix a compiler warning.
+
+  2007-03-20 Kieran Mansley
+  * udp.c: Only try and use pbuf_header() to make space for headers if
+    not a ROM or REF pbuf.
+
+  2007-03-19 Frédéric Bernon
+  * api_msg.h, api_msg.c, tcpip.h, tcpip.c: Add return types to tcpip_apimsg()
+    and api_msg_post().
+
+  2007-03-19 Frédéric Bernon
+  * Remove unimplemented "memp_realloc" function from memp.h.
+
+  2007-03-11 Simon Goldschmidt
+  * pbuf.c: checked in patch #5796: pbuf_alloc: len field claculation caused
+    memory corruption.
+
+  2007-03-11 Simon Goldschmidt (based on patch from Dmitry Potapov)
+  * api_lib.c, sockets.c, api.h, api_msg.h, sockets.h: Fixed bug #19251
+    (missing `const' qualifier in socket functions), to get more compatible to
+    standard POSIX sockets.
+
+  2007-03-11 Frédéric Bernon (based on patch from Dmitry Potapov)
+  * sockets.c: Add asserts inside bind, connect and sendto to check input
+    parameters. Remove excessive set_errno() calls after get_socket(), because
+    errno is set inside of get_socket(). Move last sock_set_errno() inside
+    lwip_close.
+
+  2007-03-09 Simon Goldschmidt
+  * memp.c: Fixed bug #11400: New etharp queueing introduced bug: memp_memory
+    was allocated too small.
+
+  2007-03-06 Simon Goldschmidt
+  * tcpip.c: Initialize dhcp timers in tcpip_thread (if LWIP_DHCP) to protect
+    the stack from concurrent access.
+
+  2007-03-06 Frédéric Bernon, Dmitry Potapov
+  * tcpip.c, ip_frag.c, ethernetif.c: Fix some build problems, and a redundancy
+    call to "lwip_stats.link.recv++;" in low_level_input() & ethernetif_input().
+
+  2007-03-06 Simon Goldschmidt
+  * ip_frag.c, ip_frag.h: Reduce code size: don't include code in those files
+    if IP_FRAG == 0 and IP_REASSEMBLY == 0
+
+  2007-03-06 Frédéric Bernon, Simon Goldschmidt
+  * opt.h, ip_frag.h, tcpip.h, tcpip.c, ethernetif.c: add new configuration
+    option named ETHARP_TCPIP_ETHINPUT, which enable the new tcpip_ethinput.
+    Allow to do ARP processing for incoming packets inside tcpip_thread
+    (protecting ARP layer against concurrent access). You can also disable
+    old code using tcp_input with new define ETHARP_TCPIP_INPUT set to 0.
+    Older ports have to use tcpip_ethinput.
+
+  2007-03-06 Simon Goldschmidt (based on patch from Dmitry Potapov)
+  * err.h, err.c: fixed compiler warning "initialization dircards qualifiers
+    from pointer target type"
+
+  2007-03-05 Frédéric Bernon
+  * opt.h, sockets.h: add new configuration options (LWIP_POSIX_SOCKETS_IO_NAMES,
+    ETHARP_TRUST_IP_MAC, review SO_REUSE)
+
+  2007-03-04 Frédéric Bernon
+  * api_msg.c: Remove some compiler warnings : parameter "pcb" was never
+    referenced.
+
+  2007-03-04 Frédéric Bernon
+  * api_lib.c: Fix "[patch #5764] api_lib.c cleanup: after patch #5687" (from
+    Dmitry Potapov).
+    The api_msg struct stay on the stack (not moved to netconn struct).
+
+  2007-03-04 Simon Goldschmidt (based on patch from Dmitry Potapov)
+  * pbuf.c: Fix BUG#19168 - pbuf_free can cause deadlock (if
+    SYS_LIGHTWEIGHT_PROT=1 & freeing PBUF_RAM when mem_sem is not available)
+    Also fixed cast warning in pbuf_alloc()
+
+  2007-03-04 Simon Goldschmidt
+  * etharp.c, etharp.h, memp.c, memp.h, opt.h: Fix BUG#11400 - don't corrupt
+    existing pbuf chain when enqueuing multiple pbufs to a pending ARP request
+
+  2007-03-03 Frédéric Bernon
+  * udp.c: remove obsolete line "static struct udp_pcb *pcb_cache = NULL;"
+    It is static, and never used in udp.c except udp_init().
+
+  2007-03-02 Simon Goldschmidt
+  * tcpip.c: Moved call to ip_init(), udp_init() and tcp_init() from
+    tcpip_thread() to tcpip_init(). This way, raw API connections can be
+    initialized before tcpip_thread is running (e.g. before OS is started)
+
+  2007-03-02 Frédéric Bernon
+  * rawapi.txt: Fix documentation mismatch with etharp.h about etharp_tmr's call
+    interval.
+
+  2007-02-28 Kieran Mansley 
+  * pbuf.c: Fix BUG#17645 - ensure pbuf payload pointer is not moved
+    outside the region of the pbuf by pbuf_header()
+
+  2007-02-28 Kieran Mansley 
+  * sockets.c: Fix BUG#19161 - ensure milliseconds timeout is non-zero
+    when supplied timeout is also non-zero 
+
+(STABLE-1.2.0)
+
+  2006-12-05 Leon Woestenberg
+  * CHANGELOG: Mention STABLE-1.2.0 release.
+
+  ++ New features:
+
+  2006-12-01 Christiaan Simons
+  * mem.h, opt.h: Added MEM_LIBC_MALLOC option.
+    Note this is a workaround. Currently I have no other options left.
+
+  2006-10-26 Christiaan Simons (accepted patch by Jonathan Larmour)
+  * ipv4/ip_frag.c: rename MAX_MTU to IP_FRAG_MAX_MTU and move define
+    to include/lwip/opt.h.
+  * ipv4/lwip/ip_frag.h: Remove unused IP_REASS_INTERVAL.
+    Move IP_REASS_MAXAGE and IP_REASS_BUFSIZE to include/lwip/opt.h.
+  * opt.h: Add above new options.
+
+  2006-08-18 Christiaan Simons
+  * tcp_{in,out}.c: added SNMP counters.
+  * ipv4/ip.c: added SNMP counters.
+  * ipv4/ip_frag.c: added SNMP counters.
+
+  2006-08-08 Christiaan Simons
+  * etharp.{c,h}: added etharp_find_addr() to read
+    (stable) ethernet/IP address pair from ARP table
+
+  2006-07-14 Christiaan Simons
+  * mib_structs.c: added
+  * include/lwip/snmp_structs.h: added
+  * netif.{c,h}, netif/ethernetif.c: added SNMP statistics to netif struct
+
+  2006-07-06 Christiaan Simons
+  * snmp/asn1_{enc,dec}.c added
+  * snmp/mib2.c added
+  * snmp/msg_{in,out}.c added
+  * include/lwip/snmp_asn1.h added
+  * include/lwip/snmp_msg.h added
+  * doc/snmp_agent.txt added
+
+  2006-03-29 Christiaan Simons
+  * inet.c, inet.h: Added platform byteswap support.
+    Added LWIP_PLATFORM_BYTESWAP define (defaults to 0) and
+    optional LWIP_PLATFORM_HTONS(), LWIP_PLATFORM_HTONL() macros.
+
+  ++ Bug fixes:
+
+  2006-11-30 Christiaan Simons
+  * dhcp.c: Fixed false triggers of request_timeout.
+
+  2006-11-28 Christiaan Simons
+  * netif.c: In netif_add() fixed missing clear of ip_addr, netmask, gw and flags.
+
+  2006-10-11 Christiaan Simons
+  * api_lib.c etharp.c, ip.c, memp.c, stats.c, sys.{c,h} tcp.h:
+    Partially accepted patch #5449 for ANSI C compatibility / build fixes.
+  * ipv4/lwip/ip.h ipv6/lwip/ip.h: Corrected UDP-Lite protocol
+    identifier from 170 to 136 (bug #17574).
+
+  2006-10-10 Christiaan Simons
+  * api_msg.c: Fixed Nagle algorithm as reported by Bob Grice.
+
+  2006-08-17 Christiaan Simons
+  * udp.c: Fixed bug #17200, added check for broadcast
+    destinations for PCBs bound to a unicast address.
+
+  2006-08-07 Christiaan Simons
+  * api_msg.c: Flushing TCP output in do_close() (bug #15926).
+
+  2006-06-27 Christiaan Simons
+  * api_msg.c: Applied patch for cold case (bug #11135).
+    In accept_function() ensure newconn->callback is always initialized.
+
+  2006-06-15 Christiaan Simons
+  * mem.h: added MEM_SIZE_F alias to fix an ancient cold case (bug #1748),
+    facilitate printing of mem_size_t and u16_t statistics.
+
+  2006-06-14 Christiaan Simons
+  * api_msg.c: Applied patch #5146 to handle allocation failures
+    in accept() by Kevin Lawson.
+
+  2006-05-26 Christiaan Simons
+  * api_lib.c: Removed conn->sem creation and destruction 
+    from netconn_write() and added sys_sem_new to netconn_new_*.
+
+(STABLE-1_1_1)
+
+  2006-03-03  Christiaan Simons
+  * ipv4/ip_frag.c: Added bound-checking assertions on ip_reassbitmap
+    access and added pbuf_alloc() return value checks.
+
+  2006-01-01  Leon Woestenberg 
+  * tcp_{in,out}.c, tcp_out.c: Removed 'even sndbuf' fix in TCP, which is
+    now handled by the checksum routine properly.
+
+  2006-02-27  Leon Woestenberg 
+   * pbuf.c: Fix alignment; pbuf_init() would not work unless
+     pbuf_pool_memory[] was properly aligned. (Patch by Curt McDowell.)
+
+  2005-12-20  Leon Woestenberg 
+  * tcp.c: Remove PCBs which stay in LAST_ACK state too long. Patch
+    submitted by Mitrani Hiroshi.
+
+  2005-12-15  Christiaan Simons
+  * inet.c: Disabled the added summing routine to preserve code space.
+
+  2005-12-14  Leon Woestenberg 
+  * tcp_in.c: Duplicate FIN ACK race condition fix by Kelvin Lawson.
+    Added Curt McDowell's optimized checksumming routine for future
+    inclusion. Need to create test case for unaliged, aligned, odd,
+    even length combination of cases on various endianess machines.
+
+  2005-12-09  Christiaan Simons
+  * inet.c: Rewrote standard checksum routine in proper portable C.
+
+  2005-11-25  Christiaan Simons
+  * udp.c tcp.c: Removed SO_REUSE hack. Should reside in socket code only.
+  * *.c: introduced cc.h LWIP_DEBUG formatters matching the u16_t, s16_t,
+    u32_t, s32_t typedefs. This solves most debug word-length assumes.
+
+  2005-07-17 Leon Woestenberg 
+  * inet.c: Fixed unaligned 16-bit access in the standard checksum
+    routine by Peter Jolasson.
+  * slipif.c: Fixed implementation assumption of single-pbuf datagrams.
+
+  2005-02-04 Leon Woestenberg 
+  * tcp_out.c: Fixed uninitialized 'queue' referenced in memerr branch.
+  * tcp_{out|in}.c: Applied patch fixing unaligned access.
+
+  2005-01-04 Leon Woestenberg 
+  * pbuf.c: Fixed missing semicolon after LWIP_DEBUG statement.
+
+  2005-01-03 Leon Woestenberg 
+  * udp.c: UDP pcb->recv() was called even when it was NULL.
+
+(STABLE-1_1_0)
+
+  2004-12-28 Leon Woestenberg 
+  * etharp.*: Disabled multiple packets on the ARP queue.
+    This clashes with TCP queueing.
+
+  2004-11-28 Leon Woestenberg 
+  * etharp.*: Fixed race condition from ARP request to ARP timeout.
+    Halved the ARP period, doubled the period counts.
+    ETHARP_MAX_PENDING now should be at least 2. This prevents
+    the counter from reaching 0 right away (which would allow
+    too little time for ARP responses to be received).
+
+  2004-11-25 Leon Woestenberg 
+  * dhcp.c: Decline messages were not multicast but unicast.
+  * etharp.c: ETHARP_CREATE is renamed to ETHARP_TRY_HARD.
+    Do not try hard to insert arbitrary packet's source address,
+    etharp_ip_input() now calls etharp_update() without ETHARP_TRY_HARD. 
+    etharp_query() now always DOES call ETHARP_TRY_HARD so that users
+    querying an address will see it appear in the cache (DHCP could
+    suffer from this when a server invalidly gave an in-use address.)
+  * ipv4/ip_addr.h: Renamed ip_addr_maskcmp() to _netcmp() as we are
+    comparing network addresses (identifiers), not the network masks
+    themselves.
+  * ipv4/ip_addr.c: ip_addr_isbroadcast() now checks that the given
+    IP address actually belongs to the network of the given interface.
+
+  2004-11-24 Kieran Mansley 
+  * tcp.c: Increment pcb->snd_buf when ACK is received in SYN_SENT state.
+
+(STABLE-1_1_0-RC1)
+
+  2004-10-16 Kieran Mansley 
+  * tcp.c: Add code to tcp_recved() to send an ACK (window update) immediately,
+    even if one is already pending, if the rcv_wnd is above a threshold
+    (currently TCP_WND/2). This avoids waiting for a timer to expire to send a
+    delayed ACK in order to open the window if the stack is only receiving data.
+
+  2004-09-12 Kieran Mansley 
+  * tcp*.*: Retransmit time-out handling improvement by Sam Jansen.
+
+  2004-08-20 Tony Mountifield 
+  * etharp.c: Make sure the first pbuf queued on an ARP entry
+    is properly ref counted.
+
+  2004-07-27 Tony Mountifield 
+  * debug.h: Added (int) cast in LWIP_DEBUGF() to avoid compiler
+    warnings about comparison.
+  * pbuf.c: Stopped compiler complaining of empty if statement
+    when LWIP_DEBUGF() empty.  Closed an unclosed comment.
+  * tcp.c: Stopped compiler complaining of empty if statement
+    when LWIP_DEBUGF() empty.
+  * ip.h Corrected IPH_TOS() macro: returns a byte, so doesn't need htons().
+  * inet.c: Added a couple of casts to quiet the compiler.
+    No need to test isascii(c) before isdigit(c) or isxdigit(c).
+
+  2004-07-22 Tony Mountifield 
+  * inet.c: Made data types consistent in inet_ntoa().
+    Added casts for return values of checksum routines, to pacify compiler.
+  * ip_frag.c, tcp_out.c, sockets.c, pbuf.c
+    Small corrections to some debugging statements, to pacify compiler.
+
+  2004-07-21 Tony Mountifield 
+  * etharp.c: Removed spurious semicolon and added missing end-of-comment.
+  * ethernetif.c Updated low_level_output() to match prototype for
+    netif->linkoutput and changed low_level_input() similarly for consistency.
+  * api_msg.c: Changed recv_raw() from int to u8_t, to match prototype
+    of raw_recv() in raw.h and so avoid compiler error.
+  * sockets.c: Added trivial (int) cast to keep compiler happier.
+  * ip.c, netif.c Changed debug statements to use the tidier ip4_addrN() macros.
+
+(STABLE-1_0_0)
+
+  ++ Changes:
+
+  2004-07-05 Leon Woestenberg 
+  * sockets.*: Restructured LWIP_PRIVATE_TIMEVAL. Make sure
+    your cc.h file defines this either 1 or 0. If non-defined,
+    defaults to 1.
+  * .c: Added  and  includes where used.
+  * etharp.c: Made some array indices unsigned.
+
+  2004-06-27 Leon Woestenberg 
+  * netif.*: Added netif_set_up()/down().
+  * dhcp.c: Changes to restart program flow.
+
+  2004-05-07 Leon Woestenberg 
+  * etharp.c: In find_entry(), instead of a list traversal per candidate, do a
+    single-pass lookup for different candidates. Should exploit locality.
+
+  2004-04-29 Leon Woestenberg 
+  * tcp*.c: Cleaned up source comment documentation for Doxygen processing.
+  * opt.h: ETHARP_ALWAYS_INSERT option removed to comply with ARP RFC.
+  * etharp.c: update_arp_entry() only adds new ARP entries when adviced to by
+    the caller. This deprecates the ETHARP_ALWAYS_INSERT overrule option.
+
+  ++ Bug fixes:
+
+  2004-04-27 Leon Woestenberg 
+  * etharp.c: Applied patch of bug #8708 by Toni Mountifield with a solution
+    suggested by Timmy Brolin. Fix for 32-bit processors that cannot access
+    non-aligned 32-bit words, such as soms 32-bit TCP/IP header fields. Fix
+    is to prefix the 14-bit Ethernet headers with two padding bytes.
+
+  2004-04-23 Leon Woestenberg 
+  * ip_addr.c: Fix in the ip_addr_isbroadcast() check.
+  * etharp.c: Fixed the case where the packet that initiates the ARP request
+    is not queued, and gets lost. Fixed the case where the packets destination
+    address is already known; we now always queue the packet and perform an ARP
+    request.
+
+(STABLE-0_7_0)
+
+  ++ Bug fixes:
+
+  * Fixed TCP bug for SYN_SENT to ESTABLISHED state transition.
+  * Fixed TCP bug in dequeueing of FIN from out of order segment queue.
+  * Fixed two possible NULL references in rare cases.
+
+(STABLE-0_6_6)
+
+  ++ Bug fixes:
+
+  * Fixed DHCP which did not include the IP address in DECLINE messages.
+
+  ++ Changes:
+
+  * etharp.c has been hauled over a bit.
+
+(STABLE-0_6_5)
+
+  ++ Bug fixes:
+
+  * Fixed TCP bug induced by bad window resizing with unidirectional TCP traffic.
+  * Packets sent from ARP queue had invalid source hardware address.
+
+  ++ Changes:
+
+  * Pass-by ARP requests do now update the cache.
+
+  ++ New features:
+
+  * No longer dependent on ctype.h.
+  * New socket options.
+  * Raw IP pcb support.
+
+(STABLE-0_6_4)
+
+  ++ Bug fixes:
+
+  * Some debug formatters and casts fixed.
+  * Numereous fixes in PPP.
+
+  ++ Changes:
+
+  * DEBUGF now is LWIP_DEBUGF
+  * pbuf_dechain() has been re-enabled.
+  * Mentioned the changed use of CVS branches in README.
+
+(STABLE-0_6_3)
+
+  ++ Bug fixes:
+
+  * Fixed pool pbuf memory leak in pbuf_alloc().
+    Occured if not enough PBUF_POOL pbufs for a packet pbuf chain.
+    Reported by Savin Zlobec.
+
+  * PBUF_POOL chains had their tot_len field not set for non-first
+    pbufs. Fixed in pbuf_alloc().
+
+  ++ New features:
+
+  * Added PPP stack contributed by Marc Boucher
+
+  ++ Changes:
+
+  * Now drops short packets for ICMP/UDP/TCP protocols. More robust.
+
+  * ARP queueuing now queues the latest packet instead of the first.
+    This is the RFC recommended behaviour, but can be overridden in
+    lwipopts.h.
+
+(0.6.2)
+
+  ++ Bugfixes:
+
+  * TCP has been fixed to deal with the new use of the pbuf->ref
+    counter.
+
+  * DHCP dhcp_inform() crash bug fixed.
+
+  ++ Changes:
+
+  * Removed pbuf_pool_free_cache and pbuf_pool_alloc_cache. Also removed
+    pbuf_refresh(). This has sped up pbuf pool operations considerably.
+    Implemented by David Haas.
+
+(0.6.1)
+
+  ++ New features:
+
+  * The packet buffer implementation has been enhanced to support
+    zero-copy and copy-on-demand for packet buffers which have their
+    payloads in application-managed memory.
+    Implemented by David Haas.
+
+    Use PBUF_REF to make a pbuf refer to RAM. lwIP will use zero-copy
+    if an outgoing packet can be directly sent on the link, or perform
+    a copy-on-demand when necessary.
+
+    The application can safely assume the packet is sent, and the RAM
+    is available to the application directly after calling udp_send()
+    or similar function.
+
+  ++ Bugfixes:
+
+  * ARP_QUEUEING should now correctly work for all cases, including
+    PBUF_REF.
+    Implemented by Leon Woestenberg.
+
+  ++ Changes:
+
+  * IP_ADDR_ANY is no longer a NULL pointer. Instead, it is a pointer
+    to a '0.0.0.0' IP address.
+
+  * The packet buffer implementation is changed. The pbuf->ref counter
+    meaning has changed, and several pbuf functions have been
+    adapted accordingly.
+
+  * netif drivers have to be changed to set the hardware address length field
+    that must be initialized correctly by the driver (hint: 6 for Ethernet MAC).
+    See the contrib/ports/c16x cs8900 driver as a driver example.
+
+  * netif's have a dhcp field that must be initialized to NULL by the driver.
+    See the contrib/ports/c16x cs8900 driver as a driver example.
+
+(0.5.x) This file has been unmaintained up to 0.6.1. All changes are
+  logged in CVS but have not been explained here.
+
+(0.5.3) Changes since version 0.5.2
+
+  ++ Bugfixes:
+
+  * memp_malloc(MEMP_API_MSG) could fail with multiple application
+    threads because it wasn't protected by semaphores.
+
+  ++ Other changes:
+
+  * struct ip_addr now packed.
+
+  * The name of the time variable in arp.c has been changed to ctime
+    to avoid conflicts with the time() function.
+
+(0.5.2) Changes since version 0.5.1
+
+  ++ New features:
+
+  * A new TCP function, tcp_tmr(), now handles both TCP timers.
+
+  ++ Bugfixes:
+
+  * A bug in tcp_parseopt() could cause the stack to hang because of a
+    malformed TCP option.
+
+  * The address of new connections in the accept() function in the BSD
+    socket library was not handled correctly.
+
+  * pbuf_dechain() did not update the ->tot_len field of the tail.
+
+  * Aborted TCP connections were not handled correctly in all
+    situations.
+
+  ++ Other changes:
+
+  * All protocol header structs are now packed.
+
+  * The ->len field in the tcp_seg structure now counts the actual
+    amount of data, and does not add one for SYN and FIN segments.
+
+(0.5.1) Changes since version 0.5.0
+
+  ++ New features:
+
+  * Possible to run as a user process under Linux.
+
+  * Preliminary support for cross platform packed structs.
+
+  * ARP timer now implemented.
+
+  ++ Bugfixes:
+
+  * TCP output queue length was badly initialized when opening
+    connections.
+
+  * TCP delayed ACKs were not sent correctly.
+
+  * Explicit initialization of BSS segment variables.
+
+  * read() in BSD socket library could drop data.
+
+  * Problems with memory alignment.
+
+  * Situations when all TCP buffers were used could lead to
+    starvation.
+
+  * TCP MSS option wasn't parsed correctly.
+
+  * Problems with UDP checksum calculation.
+
+  * IP multicast address tests had endianess problems.
+
+  * ARP requests had wrong destination hardware address.
+
+  ++ Other changes:
+
+  * struct eth_addr changed from u16_t[3] array to u8_t[6].
+
+  * A ->linkoutput() member was added to struct netif.
+
+  * TCP and UDP ->dest_* struct members where changed to ->remote_*.
+
+  * ntoh* macros are now null definitions for big endian CPUs.
+
+(0.5.0) Changes since version 0.4.2
+
+  ++ New features:
+
+  * Redesigned operating system emulation layer to make porting easier.
+
+  * Better control over TCP output buffers.
+
+  * Documenation added.
+
+  ++ Bugfixes:
+
+  * Locking issues in buffer management.
+
+  * Bugfixes in the sequential API.
+
+  * IP forwarding could cause memory leakage. This has been fixed.
+
+  ++ Other changes:
+
+  * Directory structure somewhat changed; the core/ tree has been
+    collapsed.
+
+(0.4.2) Changes since version 0.4.1
+
+  ++ New features:
+
+  * Experimental ARP implementation added.
+
+  * Skeleton Ethernet driver added.
+
+  * Experimental BSD socket API library added.
+
+  ++ Bugfixes:
+
+  * In very intense situations, memory leakage could occur. This has
+    been fixed.
+
+  ++ Other changes:
+
+  * Variables named "data" and "code" have been renamed in order to
+    avoid name conflicts in certain compilers.
+
+  * Variable++ have in appliciable cases been translated to ++variable
+    since some compilers generate better code in the latter case.
+
+(0.4.1) Changes since version 0.4
+
+  ++ New features:
+
+  * TCP: Connection attempts time out earlier than data
+    transmissions. Nagle algorithm implemented. Push flag set on the
+    last segment in a burst.
+
+  * UDP: experimental support for UDP-Lite extensions.
+
+  ++ Bugfixes:
+
+  * TCP: out of order segments were in some cases handled incorrectly,
+    and this has now been fixed. Delayed acknowledgements was broken
+    in 0.4, has now been fixed. Binding to an address that is in use
+    now results in an error. Reset connections sometimes hung an
+    application; this has been fixed.
+
+  * Checksum calculation sometimes failed for chained pbufs with odd
+    lengths. This has been fixed.
+
+  * API: a lot of bug fixes in the API. The UDP API has been improved
+    and tested. Error reporting and handling has been
+    improved. Logical flaws and race conditions for incoming TCP
+    connections has been found and removed.
+
+  * Memory manager: alignment issues. Reallocating memory sometimes
+    failed, this has been fixed.
+
+  * Generic library: bcopy was flawed and has been fixed.
+
+  ++ Other changes:
+
+  * API: all datatypes has been changed from generic ones such as
+    ints, to specified ones such as u16_t. Functions that return
+    errors now have the correct type (err_t).
+
+  * General: A lot of code cleaned up and debugging code removed. Many
+    portability issues have been fixed.
+
+  * The license was changed; the advertising clause was removed.
+
+  * C64 port added.
+
+  * Thanks: Huge thanks go to Dagan Galarneau, Horst Garnetzke, Petri
+    Kosunen, Mikael Caleres, and Frits Wilmink for reporting and
+    fixing bugs!
+
+(0.4) Changes since version 0.3.1
+
+  * Memory management has been radically changed; instead of
+    allocating memory from a shared heap, memory for objects that are
+    rapidly allocated and deallocated is now kept in pools. Allocation
+    and deallocation from those memory pools is very fast. The shared
+    heap is still present but is used less frequently.
+
+  * The memory, memory pool, and packet buffer subsystems now support
+    4-, 2-, or 1-byte alignment.
+
+  * "Out of memory" situations are handled in a more robust way.
+
+  * Stack usage has been reduced.
+
+  * Easier configuration of lwIP parameters such as memory usage,
+    TTLs, statistics gathering, etc. All configuration parameters are
+    now kept in a single header file "lwipopts.h".
+
+  * The directory structure has been changed slightly so that all
+    architecture specific files are kept under the src/arch
+    hierarchy.
+
+  * Error propagation has been improved, both in the protocol modules
+    and in the API.
+
+  * The code for the RTXC architecture has been implemented, tested
+    and put to use.
+
+  * Bugs have been found and corrected in the TCP, UDP, IP, API, and
+    the Internet checksum modules.
+
+  * Bugs related to porting between a 32-bit and a 16-bit architecture
+    have been found and corrected.
+
+  * The license has been changed slightly to conform more with the
+    original BSD license, including the advertisement clause.
+
+(0.3.1) Changes since version 0.3
+
+  * Fix of a fatal bug in the buffer management. Pbufs with allocated
+    RAM never returned the RAM when the pbuf was deallocated.
+
+  * TCP congestion control, window updates and retransmissions did not
+    work correctly. This has now been fixed.
+
+  * Bugfixes in the API.
+
+(0.3) Changes since version 0.2
+
+  * New and improved directory structure. All include files are now
+    kept in a dedicated include/ directory.
+
+  * The API now has proper error handling. A new function,
+    netconn_err(), now returns an error code for the connection in
+    case of errors.
+
+  * Improvements in the memory management subsystem. The system now
+    keeps a pointer to the lowest free memory block. A new function,
+    mem_malloc2() tries to allocate memory once, and if it fails tries
+    to free some memory and retry the allocation.
+
+  * Much testing has been done with limited memory
+    configurations. lwIP now does a better job when overloaded.
+
+  * Some bugfixes and improvements to the buffer (pbuf) subsystem.
+
+  * Many bugfixes in the TCP code:
+
+    - Fixed a bug in tcp_close().
+
+    - The TCP receive window was incorrectly closed when out of
+      sequence segments was received. This has been fixed.
+
+    - Connections are now timed-out of the FIN-WAIT-2 state.
+
+    - The initial congestion window could in some cases be too
+      large. This has been fixed.
+
+    - The retransmission queue could in some cases be screwed up. This
+      has been fixed.
+
+    - TCP RST flag now handled correctly.
+
+    - Out of sequence data was in some cases never delivered to the
+      application. This has been fixed.
+
+    - Retransmitted segments now contain the correct acknowledgment
+      number and advertised window.
+
+    - TCP retransmission timeout backoffs are not correctly computed
+      (ala BSD). After a number of retransmissions, TCP now gives up
+      the connection.
+
+  * TCP connections now are kept on three lists, one for active
+    connections, one for listening connections, and one for
+    connections that are in TIME-WAIT. This greatly speeds up the fast
+    timeout processing for sending delayed ACKs.
+
+  * TCP now provides proper feedback to the application when a
+    connection has been successfully set up.
+
+  * More comments have been added to the code. The code has also been
+    somewhat cleaned up.
+
+(0.2) Initial public release.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/COPYING b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/COPYING
new file mode 100644
index 0000000..e23898b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/COPYING
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2001, 2002 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/FILES b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/FILES
new file mode 100644
index 0000000..6625319
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/FILES
@@ -0,0 +1,4 @@
+src/      - The source code for the lwIP TCP/IP stack.
+doc/      - The documentation for lwIP.
+
+See also the FILES file in each subdirectory.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/README b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/README
new file mode 100644
index 0000000..a62cc4f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/README
@@ -0,0 +1,89 @@
+INTRODUCTION
+
+lwIP is a small independent implementation of the TCP/IP protocol
+suite that has been developed by Adam Dunkels at the Computer and
+Networks Architectures (CNA) lab at the Swedish Institute of Computer
+Science (SICS).
+
+The focus of the lwIP TCP/IP implementation is to reduce the RAM usage
+while still having a full scale TCP. This making lwIP suitable for use
+in embedded systems with tens of kilobytes of free RAM and room for
+around 40 kilobytes of code ROM.
+
+FEATURES
+
+  * IP (Internet Protocol) including packet forwarding over multiple network
+    interfaces
+  * ICMP (Internet Control Message Protocol) for network maintenance and debugging
+  * IGMP (Internet Group Management Protocol) for multicast traffic management
+  * UDP (User Datagram Protocol) including experimental UDP-lite extensions
+  * TCP (Transmission Control Protocol) with congestion control, RTT estimation
+    and fast recovery/fast retransmit
+  * Specialized raw/native API for enhanced performance
+  * Optional Berkeley-like socket API
+  * DNS (Domain names resolver)
+  * SNMP (Simple Network Management Protocol)
+  * DHCP (Dynamic Host Configuration Protocol)
+  * AUTOIP (for IPv4, conform with RFC 3927)
+  * PPP (Point-to-Point Protocol)
+  * ARP (Address Resolution Protocol) for Ethernet
+
+LICENSE
+
+lwIP is freely available under a BSD license.
+
+DEVELOPMENT
+
+lwIP has grown into an excellent TCP/IP stack for embedded devices,
+and developers using the stack often submit bug fixes, improvements,
+and additions to the stack to further increase its usefulness.
+
+Development of lwIP is hosted on Savannah, a central point for
+software development, maintenance and distribution. Everyone can
+help improve lwIP by use of Savannah's interface, CVS and the
+mailing list. A core team of developers will commit changes to the
+CVS source tree.
+
+The lwIP TCP/IP stack is maintained in the 'lwip' CVS module and
+contributions (such as platform ports) are in the 'contrib' module.
+
+See doc/savannah.txt for details on CVS server access for users and
+developers.
+
+Last night's CVS tar ball can be downloaded from:
+  http://savannah.gnu.org/cvs.backups/lwip.tar.gz [CHANGED - NEEDS FIXING]
+
+The current CVS trees are web-browsable:
+  http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/lwip/
+  http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/contrib/
+
+Submit patches and bugs via the lwIP project page:
+  http://savannah.nongnu.org/projects/lwip/
+
+
+DOCUMENTATION
+
+The original out-dated homepage of lwIP and Adam Dunkels' papers on
+lwIP are at the official lwIP home page:
+  http://www.sics.se/~adam/lwip/
+
+Self documentation of the source code is regularly extracted from the
+current CVS sources and is available from this web page:
+  http://www.nongnu.org/lwip/
+
+There is now a constantly growin wiki about lwIP at
+  http://lwip.wikia.com/wiki/LwIP_Wiki
+
+Also, there are mailing lists you can subscribe at
+  http://savannah.nongnu.org/mail/?group=lwip
+plus searchable archives:
+  http://lists.nongnu.org/archive/html/lwip-users/
+  http://lists.nongnu.org/archive/html/lwip-devel/
+
+Reading Adam's papers, the files in docs/, browsing the source code
+documentation and browsing the mailing list archives is a good way to
+become familiar with the design of lwIP.
+
+Adam Dunkels 
+Leon Woestenberg 
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/doc/FILES b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/doc/FILES
new file mode 100644
index 0000000..05d356f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/doc/FILES
@@ -0,0 +1,6 @@
+savannah.txt   - How to obtain the current development source code.
+contrib.txt    - How to contribute to lwIP as a developer.
+rawapi.txt     - The documentation for the core API of lwIP.
+                 Also provides an overview about the other APIs and multithreading.
+snmp_agent.txt - The documentation for the lwIP SNMP agent.
+sys_arch.txt   - The documentation for a system abstraction layer of lwIP.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/doc/contrib.txt b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/doc/contrib.txt
new file mode 100644
index 0000000..39596fc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/doc/contrib.txt
@@ -0,0 +1,63 @@
+1 Introduction
+
+This document describes some guidelines for people participating
+in lwIP development.
+
+2 How to contribute to lwIP
+
+Here is a short list of suggestions to anybody working with lwIP and 
+trying to contribute bug reports, fixes, enhancements, platform ports etc.
+First of all as you may already know lwIP is a volunteer project so feedback
+to fixes or questions might often come late. Hopefully the bug and patch tracking 
+features of Savannah help us not lose users' input.
+
+2.1 Source code style:
+
+1. do not use tabs.
+2. indentation is two spaces per level (i.e. per tab).
+3. end debug messages with a trailing newline (\n).
+4. one space between keyword and opening bracket.
+5. no space between function and opening bracket.
+6. one space and no newline before opening curly braces of a block.
+7. closing curly brace on a single line.
+8. spaces surrounding assignment and comparisons.
+9. don't initialize static and/or global variables to zero, the compiler takes care of that.
+10. use current source code style as further reference.
+
+2.2 Source code documentation style:
+
+1. JavaDoc compliant and Doxygen compatible.
+2. Function documentation above functions in .c files, not .h files.
+   (This forces you to synchronize documentation and implementation.)
+3. Use current documentation style as further reference.
+ 
+2.3 Bug reports and patches:
+
+1. Make sure you are reporting bugs or send patches against the latest
+   sources. (From the latest release and/or the current CVS sources.)
+2. If you think you found a bug make sure it's not already filed in the
+   bugtracker at Savannah.
+3. If you have a fix put the patch on Savannah. If it is a patch that affects
+   both core and arch specific stuff please separate them so that the core can
+   be applied separately while leaving the other patch 'open'. The prefered way
+   is to NOT touch archs you can't test and let maintainers take care of them.
+   This is a good way to see if they are used at all - the same goes for unix
+   netifs except tapif.
+4. Do not file a bug and post a fix to it to the patch area. Either a bug report
+   or a patch will be enough.
+   If you correct an existing bug then attach the patch to the bug rather than creating a new entry in the patch area.
+5. Trivial patches (compiler warning, indentation and spelling fixes or anything obvious which takes a line or two)
+   can go to the lwip-users list. This is still the fastest way of interaction and the list is not so crowded
+   as to allow for loss of fixes. Putting bugs on Savannah and subsequently closing them is too much an overhead
+   for reporting a compiler warning fix.
+6. Patches should be specific to a single change or to related changes.Do not mix bugfixes with spelling and other
+   trivial fixes unless the bugfix is trivial too.Do not reorganize code and rename identifiers in the same patch you
+   change behaviour if not necessary.A patch is easier to read and understand if it's to the point and short than
+   if it's not to the point and long :) so the chances for it to be applied are greater. 
+
+2.4 Platform porters:
+
+1. If you have ported lwIP to a platform (an OS, a uC/processor or a combination of these) and
+   you think it could benefit others[1] you might want discuss this on the mailing list. You
+   can also ask for CVS access to submit and maintain your port in the contrib CVS module.
+   
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/doc/rawapi.txt b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/doc/rawapi.txt
new file mode 100644
index 0000000..8eec6e7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/doc/rawapi.txt
@@ -0,0 +1,478 @@
+Raw TCP/IP interface for lwIP
+
+Authors: Adam Dunkels, Leon Woestenberg, Christiaan Simons
+
+lwIP provides three Application Program's Interfaces (APIs) for programs
+to use for communication with the TCP/IP code:
+* low-level "core" / "callback" or "raw" API.
+* higher-level "sequential" API.
+* BSD-style socket API.
+
+The sequential API provides a way for ordinary, sequential, programs
+to use the lwIP stack. It is quite similar to the BSD socket API. The
+model of execution is based on the blocking open-read-write-close
+paradigm. Since the TCP/IP stack is event based by nature, the TCP/IP
+code and the application program must reside in different execution
+contexts (threads).
+
+The socket API is a compatibility API for existing applications,
+currently it is built on top of the sequential API. It is meant to
+provide all functions needed to run socket API applications running
+on other platforms (e.g. unix / windows etc.). However, due to limitations
+in the specification of this API, there might be incompatibilities
+that require small modifications of existing programs.
+
+** Threading
+
+lwIP started targeting single-threaded environments. When adding multi-
+threading support, instead of making the core thread-safe, another
+approach was chosen: there is one main thread running the lwIP core
+(also known as the "tcpip_thread"). The raw API may only be used from
+this thread! Application threads using the sequential- or socket API
+communicate with this main thread through message passing.
+
+      As such, the list of functions that may be called from
+      other threads or an ISR is very limited! Only functions
+      from these API header files are thread-safe:
+      - api.h
+      - netbuf.h
+      - netdb.h
+      - netifapi.h
+      - sockets.h
+      - sys.h
+
+      Additionaly, memory (de-)allocation functions may be
+      called from multiple threads (not ISR!) with NO_SYS=0
+      since they are protected by SYS_LIGHTWEIGHT_PROT and/or
+      semaphores.
+
+      Only since 1.3.0, if SYS_LIGHTWEIGHT_PROT is set to 1
+      and LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT is set to 1,
+      pbuf_free() may also be called from another thread or
+      an ISR (since only then, mem_free - for PBUF_RAM - may
+      be called from an ISR: otherwise, the HEAP is only
+      protected by semaphores).
+      
+
+** The remainder of this document discusses the "raw" API. **
+
+The raw TCP/IP interface allows the application program to integrate
+better with the TCP/IP code. Program execution is event based by
+having callback functions being called from within the TCP/IP
+code. The TCP/IP code and the application program both run in the same
+thread. The sequential API has a much higher overhead and is not very
+well suited for small systems since it forces a multithreaded paradigm
+on the application.
+
+The raw TCP/IP interface is not only faster in terms of code execution
+time but is also less memory intensive. The drawback is that program
+development is somewhat harder and application programs written for
+the raw TCP/IP interface are more difficult to understand. Still, this
+is the preferred way of writing applications that should be small in
+code size and memory usage.
+
+Both APIs can be used simultaneously by different application
+programs. In fact, the sequential API is implemented as an application
+program using the raw TCP/IP interface.
+
+--- Callbacks
+
+Program execution is driven by callbacks. Each callback is an ordinary
+C function that is called from within the TCP/IP code. Every callback
+function is passed the current TCP or UDP connection state as an
+argument. Also, in order to be able to keep program specific state,
+the callback functions are called with a program specified argument
+that is independent of the TCP/IP state.
+
+The function for setting the application connection state is:
+
+- void tcp_arg(struct tcp_pcb *pcb, void *arg)
+
+  Specifies the program specific state that should be passed to all
+  other callback functions. The "pcb" argument is the current TCP
+  connection control block, and the "arg" argument is the argument
+  that will be passed to the callbacks.
+
+  
+--- TCP connection setup
+
+The functions used for setting up connections is similar to that of
+the sequential API and of the BSD socket API. A new TCP connection
+identifier (i.e., a protocol control block - PCB) is created with the
+tcp_new() function. This PCB can then be either set to listen for new
+incoming connections or be explicitly connected to another host.
+
+- struct tcp_pcb *tcp_new(void)
+
+  Creates a new connection identifier (PCB). If memory is not
+  available for creating the new pcb, NULL is returned.
+
+- err_t tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port)
+
+  Binds the pcb to a local IP address and port number. The IP address
+  can be specified as IP_ADDR_ANY in order to bind the connection to
+  all local IP addresses.
+
+  If another connection is bound to the same port, the function will
+  return ERR_USE, otherwise ERR_OK is returned.
+
+- struct tcp_pcb *tcp_listen(struct tcp_pcb *pcb)
+
+  Commands a pcb to start listening for incoming connections. When an
+  incoming connection is accepted, the function specified with the
+  tcp_accept() function will be called. The pcb will have to be bound
+  to a local port with the tcp_bind() function.
+
+  The tcp_listen() function returns a new connection identifier, and
+  the one passed as an argument to the function will be
+  deallocated. The reason for this behavior is that less memory is
+  needed for a connection that is listening, so tcp_listen() will
+  reclaim the memory needed for the original connection and allocate a
+  new smaller memory block for the listening connection.
+
+  tcp_listen() may return NULL if no memory was available for the
+  listening connection. If so, the memory associated with the pcb
+  passed as an argument to tcp_listen() will not be deallocated.
+
+- struct tcp_pcb *tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog)
+
+  Same as tcp_listen, but limits the number of outstanding connections
+  in the listen queue to the value specified by the backlog argument.
+  To use it, your need to set TCP_LISTEN_BACKLOG=1 in your lwipopts.h.
+
+- void tcp_accepted(struct tcp_pcb *pcb)
+
+  Inform lwIP that an incoming connection has been accepted. This would
+  usually be called from the accept callback. This allows lwIP to perform
+  housekeeping tasks, such as allowing further incoming connections to be
+  queued in the listen backlog.
+
+- void tcp_accept(struct tcp_pcb *pcb,
+                  err_t (* accept)(void *arg, struct tcp_pcb *newpcb,
+                                   err_t err))
+
+  Specified the callback function that should be called when a new
+  connection arrives on a listening connection.
+      
+- err_t tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+                    u16_t port, err_t (* connected)(void *arg,
+                                                    struct tcp_pcb *tpcb,
+                                                    err_t err));
+
+  Sets up the pcb to connect to the remote host and sends the
+  initial SYN segment which opens the connection. 
+
+  The tcp_connect() function returns immediately; it does not wait for
+  the connection to be properly setup. Instead, it will call the
+  function specified as the fourth argument (the "connected" argument)
+  when the connection is established. If the connection could not be
+  properly established, either because the other host refused the
+  connection or because the other host didn't answer, the "err"
+  callback function of this pcb (registered with tcp_err, see below)
+  will be called.
+
+  The tcp_connect() function can return ERR_MEM if no memory is
+  available for enqueueing the SYN segment. If the SYN indeed was
+  enqueued successfully, the tcp_connect() function returns ERR_OK.
+
+  
+--- Sending TCP data
+
+TCP data is sent by enqueueing the data with a call to
+tcp_write(). When the data is successfully transmitted to the remote
+host, the application will be notified with a call to a specified
+callback function.
+
+- err_t tcp_write(struct tcp_pcb *pcb, void *dataptr, u16_t len,
+                  u8_t copy)
+
+  Enqueues the data pointed to by the argument dataptr. The length of
+  the data is passed as the len parameter. The copy argument is either
+  0 or 1 and indicates whether the new memory should be allocated for
+  the data to be copied into. If the argument is 0, no new memory
+  should be allocated and the data should only be referenced by
+  pointer.
+
+  The tcp_write() function will fail and return ERR_MEM if the length
+  of the data exceeds the current send buffer size or if the length of
+  the queue of outgoing segment is larger than the upper limit defined
+  in lwipopts.h. The number of bytes available in the output queue can
+  be retrieved with the tcp_sndbuf() function.
+
+  The proper way to use this function is to call the function with at
+  most tcp_sndbuf() bytes of data. If the function returns ERR_MEM,
+  the application should wait until some of the currently enqueued
+  data has been successfully received by the other host and try again.
+
+- void tcp_sent(struct tcp_pcb *pcb,
+                err_t (* sent)(void *arg, struct tcp_pcb *tpcb,
+                u16_t len))
+
+  Specifies the callback function that should be called when data has
+  successfully been received (i.e., acknowledged) by the remote
+  host. The len argument passed to the callback function gives the
+  amount bytes that was acknowledged by the last acknowledgment.
+
+  
+--- Receiving TCP data
+
+TCP data reception is callback based - an application specified
+callback function is called when new data arrives. When the
+application has taken the data, it has to call the tcp_recved()
+function to indicate that TCP can advertise increase the receive
+window.
+
+- void tcp_recv(struct tcp_pcb *pcb,
+                err_t (* recv)(void *arg, struct tcp_pcb *tpcb,
+                               struct pbuf *p, err_t err))
+
+  Sets the callback function that will be called when new data
+  arrives. The callback function will be passed a NULL pbuf to
+  indicate that the remote host has closed the connection. If
+  there are no errors and the callback function is to return
+  ERR_OK, then it must free the pbuf. Otherwise, it must not
+  free the pbuf so that lwIP core code can store it.
+
+- void tcp_recved(struct tcp_pcb *pcb, u16_t len)
+
+  Must be called when the application has received the data. The len
+  argument indicates the length of the received data.
+    
+
+--- Application polling
+
+When a connection is idle (i.e., no data is either transmitted or
+received), lwIP will repeatedly poll the application by calling a
+specified callback function. This can be used either as a watchdog
+timer for killing connections that have stayed idle for too long, or
+as a method of waiting for memory to become available. For instance,
+if a call to tcp_write() has failed because memory wasn't available,
+the application may use the polling functionality to call tcp_write()
+again when the connection has been idle for a while.
+
+- void tcp_poll(struct tcp_pcb *pcb, u8_t interval,
+                err_t (* poll)(void *arg, struct tcp_pcb *tpcb))
+
+  Specifies the polling interval and the callback function that should
+  be called to poll the application. The interval is specified in
+  number of TCP coarse grained timer shots, which typically occurs
+  twice a second. An interval of 10 means that the application would
+  be polled every 5 seconds.
+
+
+--- Closing and aborting connections
+
+- err_t tcp_close(struct tcp_pcb *pcb)
+
+  Closes the connection. The function may return ERR_MEM if no memory
+  was available for closing the connection. If so, the application
+  should wait and try again either by using the acknowledgment
+  callback or the polling functionality. If the close succeeds, the
+  function returns ERR_OK.
+
+  The pcb is deallocated by the TCP code after a call to tcp_close(). 
+
+- void tcp_abort(struct tcp_pcb *pcb)
+
+  Aborts the connection by sending a RST (reset) segment to the remote
+  host. The pcb is deallocated. This function never fails.
+
+If a connection is aborted because of an error, the application is
+alerted of this event by the err callback. Errors that might abort a
+connection are when there is a shortage of memory. The callback
+function to be called is set using the tcp_err() function.
+
+- void tcp_err(struct tcp_pcb *pcb, void (* err)(void *arg,
+       err_t err))
+
+  The error callback function does not get the pcb passed to it as a
+  parameter since the pcb may already have been deallocated.
+
+
+--- Lower layer TCP interface
+
+TCP provides a simple interface to the lower layers of the
+system. During system initialization, the function tcp_init() has
+to be called before any other TCP function is called. When the system
+is running, the two timer functions tcp_fasttmr() and tcp_slowtmr()
+must be called with regular intervals. The tcp_fasttmr() should be
+called every TCP_FAST_INTERVAL milliseconds (defined in tcp.h) and
+tcp_slowtmr() should be called every TCP_SLOW_INTERVAL milliseconds. 
+
+
+--- UDP interface
+
+The UDP interface is similar to that of TCP, but due to the lower
+level of complexity of UDP, the interface is significantly simpler.
+
+- struct udp_pcb *udp_new(void)
+
+  Creates a new UDP pcb which can be used for UDP communication. The
+  pcb is not active until it has either been bound to a local address
+  or connected to a remote address.
+
+- void udp_remove(struct udp_pcb *pcb)
+
+  Removes and deallocates the pcb.  
+  
+- err_t udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port)
+
+  Binds the pcb to a local address. The IP-address argument "ipaddr"
+  can be IP_ADDR_ANY to indicate that it should listen to any local IP
+  address. The function currently always return ERR_OK.
+
+- err_t udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                    u16_t port)
+
+  Sets the remote end of the pcb. This function does not generate any
+  network traffic, but only set the remote address of the pcb.
+
+- err_t udp_disconnect(struct udp_pcb *pcb)
+
+  Remove the remote end of the pcb. This function does not generate
+  any network traffic, but only removes the remote address of the pcb.
+
+- err_t udp_send(struct udp_pcb *pcb, struct pbuf *p)
+
+  Sends the pbuf p. The pbuf is not deallocated.
+
+- void udp_recv(struct udp_pcb *pcb,
+                void (* recv)(void *arg, struct udp_pcb *upcb,
+                                         struct pbuf *p,
+                                         struct ip_addr *addr,
+                                         u16_t port),
+                              void *recv_arg)
+
+  Specifies a callback function that should be called when a UDP
+  datagram is received.
+  
+
+--- System initalization
+
+A truly complete and generic sequence for initializing the lwip stack
+cannot be given because it depends on the build configuration (lwipopts.h)
+and additional initializations for your runtime environment (e.g. timers).
+
+We can give you some idea on how to proceed when using the raw API.
+We assume a configuration using a single Ethernet netif and the
+UDP and TCP transport layers, IPv4 and the DHCP client.
+
+Call these functions in the order of appearance:
+
+- stats_init()
+
+  Clears the structure where runtime statistics are gathered.
+
+- sys_init()
+  
+  Not of much use since we set the NO_SYS 1 option in lwipopts.h,
+  to be called for easy configuration changes.
+
+- mem_init()
+
+  Initializes the dynamic memory heap defined by MEM_SIZE.
+
+- memp_init()
+
+  Initializes the memory pools defined by MEMP_NUM_x.
+
+- pbuf_init()
+
+  Initializes the pbuf memory pool defined by PBUF_POOL_SIZE.
+  
+- etharp_init()
+
+  Initializes the ARP table and queue.
+  Note: you must call etharp_tmr at a ARP_TMR_INTERVAL (5 seconds) regular interval
+  after this initialization.
+
+- ip_init()
+
+  Doesn't do much, it should be called to handle future changes.
+
+- udp_init()
+
+  Clears the UDP PCB list.
+
+- tcp_init()
+
+  Clears the TCP PCB list and clears some internal TCP timers.
+  Note: you must call tcp_fasttmr() and tcp_slowtmr() at the
+  predefined regular intervals after this initialization. 
+  
+- netif_add(struct netif *netif, struct ip_addr *ipaddr,
+            struct ip_addr *netmask, struct ip_addr *gw,
+            void *state, err_t (* init)(struct netif *netif),
+            err_t (* input)(struct pbuf *p, struct netif *netif))
+
+  Adds your network interface to the netif_list. Allocate a struct
+  netif and pass a pointer to this structure as the first argument.
+  Give pointers to cleared ip_addr structures when using DHCP,
+  or fill them with sane numbers otherwise. The state pointer may be NULL.
+
+  The init function pointer must point to a initialization function for
+  your ethernet netif interface. The following code illustrates it's use.
+  
+  err_t netif_if_init(struct netif *netif)
+  {
+    u8_t i;
+    
+    for(i = 0; i < ETHARP_HWADDR_LEN; i++) netif->hwaddr[i] = some_eth_addr[i];
+    init_my_eth_device();
+    return ERR_OK;
+  }
+  
+  For ethernet drivers, the input function pointer must point to the lwip
+  function ethernet_input() declared in "netif/etharp.h". Other drivers
+  must use ip_input() declared in "lwip/ip.h".
+  
+- netif_set_default(struct netif *netif)
+
+  Registers the default network interface.
+
+- netif_set_up(struct netif *netif)
+
+  When the netif is fully configured this function must be called.
+
+- dhcp_start(struct netif *netif)
+
+  Creates a new DHCP client for this interface on the first call.
+  Note: you must call dhcp_fine_tmr() and dhcp_coarse_tmr() at
+  the predefined regular intervals after starting the client.
+  
+  You can peek in the netif->dhcp struct for the actual DHCP status.
+
+
+--- Optimalization hints
+
+The first thing you want to optimize is the lwip_standard_checksum()
+routine from src/core/inet.c. You can override this standard
+function with the #define LWIP_CHKSUM .
+
+There are C examples given in inet.c or you might want to
+craft an assembly function for this. RFC1071 is a good
+introduction to this subject.
+
+Other significant improvements can be made by supplying
+assembly or inline replacements for htons() and htonl()
+if you're using a little-endian architecture.
+#define LWIP_PLATFORM_BYTESWAP 1
+#define LWIP_PLATFORM_HTONS(x) 
+#define LWIP_PLATFORM_HTONL(x) 
+
+Check your network interface driver if it reads at
+a higher speed than the maximum wire-speed. If the
+hardware isn't serviced frequently and fast enough
+buffer overflows are likely to occur.
+
+E.g. when using the cs8900 driver, call cs8900if_service(ethif)
+as frequently as possible. When using an RTOS let the cs8900 interrupt
+wake a high priority task that services your driver using a binary
+semaphore or event flag. Some drivers might allow additional tuning
+to match your application and network.
+
+For a production release it is recommended to set LWIP_STATS to 0.
+Note that speed performance isn't influenced much by simply setting
+high values to the memory options.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/doc/savannah.txt b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/doc/savannah.txt
new file mode 100644
index 0000000..409905b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/doc/savannah.txt
@@ -0,0 +1,135 @@
+Daily Use Guide for using Savannah for lwIP
+
+Table of Contents:
+
+1 - Obtaining lwIP from the CVS repository
+2 - Committers/developers CVS access using SSH (to be written)
+3 - Merging from DEVEL branch to main trunk (stable branch)
+4 - How to release lwIP
+
+
+
+1 Obtaining lwIP from the CVS repository
+----------------------------------------
+
+To perform an anonymous CVS checkout of the main trunk (this is where
+bug fixes and incremental enhancements occur), do this:
+
+cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout lwip
+ 
+Or, obtain a stable branch (updated with bug fixes only) as follows:
+cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \
+  -r STABLE-0_7 -d lwip-0.7 lwip
+
+Or, obtain a specific (fixed) release as follows:
+cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \
+  -r STABLE-0_7_0 -d lwip-0.7.0 lwip
+
+3 Committers/developers CVS access using SSH
+--------------------------------------------
+
+The Savannah server uses SSH (Secure Shell) protocol 2 authentication and encryption.
+As such, CVS commits to the server occur through a SSH tunnel for project members.
+To create a SSH2 key pair in UNIX-like environments, do this:
+
+ssh-keygen -t dsa
+
+Under Windows, a recommended SSH client is "PuTTY", freely available with good
+documentation and a graphic user interface. Use its key generator.
+
+Now paste the id_dsa.pub contents into your Savannah account public key list. Wait
+a while so that Savannah can update its configuration (This can take minutes).
+
+Try to login using SSH:
+
+ssh -v your_login@cvs.sv.gnu.org
+
+If it tells you:
+
+Authenticating with public key "your_key_name"...
+Server refused to allocate pty
+
+then you could login; Savannah refuses to give you a shell - which is OK, as we
+are allowed to use SSH for CVS only. Now, you should be able to do this:
+
+export CVS_RSH=ssh
+cvs -z3 -d:ext:your_login@cvs.sv.gnu.org:/sources/lwip co lwip
+ 
+after which you can edit your local files with bug fixes or new features and
+commit them. Make sure you know what you are doing when using CVS to make
+changes on the repository. If in doubt, ask on the lwip-members mailing list.
+
+(If SSH asks about authenticity of the host, you can check the key
+ fingerprint against http://savannah.nongnu.org/cvs/?group=lwip)
+
+
+3 Merging from DEVEL branch to main trunk (stable)
+--------------------------------------------------
+
+Merging is a delicate process in CVS and requires the
+following disciplined steps in order to prevent conflicts
+in the future. Conflicts can be hard to solve!
+
+Merging from branch A to branch B requires that the A branch
+has a tag indicating the previous merger. This tag is called
+'merged_from_A_to_B'. After merging, the tag is moved in the
+A branch to remember this merger for future merge actions.
+
+IMPORTANT: AFTER COMMITTING A SUCCESFUL MERGE IN THE
+REPOSITORY, THE TAG MUST BE SET ON THE SOURCE BRANCH OF THE
+MERGE ACTION (REPLACING EXISTING TAGS WITH THE SAME NAME).
+
+Merge all changes in DEVEL since our last merge to main:
+
+In the working copy of the main trunk:
+cvs update -P -jmerged_from_DEVEL_to_main -jDEVEL 
+
+(This will apply the changes between 'merged_from_DEVEL_to_main'
+and 'DEVEL' to your work set of files)
+
+We can now commit the merge result.
+cvs commit -R -m "Merged from DEVEL to main." 
+
+If this worked out OK, we now move the tag in the DEVEL branch
+to this merge point, so we can use this point for future merges:
+
+cvs rtag -F -r DEVEL merged_from_DEVEL_to_main lwip 
+
+4 How to release lwIP
+---------------------
+
+First, checkout a clean copy of the branch to be released. Tag this set with
+tag name "STABLE-0_6_3". (I use release number 0.6.3 throughout this example).
+
+Login CVS using pserver authentication, then export a clean copy of the
+tagged tree. Export is similar to a checkout, except that the CVS metadata
+is not created locally. 
+
+export CVS_RSH=ssh
+cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \
+  -r STABLE-0_6_3 -d lwip-0.6.3 lwip
+
+Archive this directory using tar, gzip'd, bzip2'd and zip'd.
+
+tar czvf lwip-0.6.3.tar.gz lwip-0.6.3
+tar cjvf lwip-0.6.3.tar.bz2 lwip-0.6.3
+zip -r lwip-0.6.3.zip lwip-0.6.3
+
+Now, sign the archives with a detached GPG binary signature as follows:
+
+gpg -b lwip-0.6.3.tar.gz
+gpg -b lwip-0.6.3.tar.bz2
+gpg -b lwip-0.6.3.zip
+
+Upload these files using anonymous FTP:
+ncftp ftp://savannah.gnu.org/incoming/savannah/lwip
+
+ncftp>mput *0.6.3.*
+
+Additionally, you may post a news item on Savannah, like this:
+
+A new 0.6.3 release is now available here:
+http://savannah.nongnu.org/files/?group=lwip&highlight=0.6.3
+
+You will have to submit this via the user News interface, then approve
+this via the Administrator News interface.
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/doc/snmp_agent.txt b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/doc/snmp_agent.txt
new file mode 100644
index 0000000..9b58616
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/doc/snmp_agent.txt
@@ -0,0 +1,181 @@
+SNMPv1 agent for lwIP
+
+Author: Christiaan Simons
+
+This is a brief introduction how to use and configure the SNMP agent.
+Note the agent uses the raw-API UDP interface so you may also want to
+read rawapi.txt to gain a better understanding of the SNMP message handling.
+
+0 Agent Capabilities
+====================
+
+SNMPv1 per RFC1157
+  This is an old(er) standard but is still widely supported.
+  For SNMPv2c and v3 have a greater complexity and need many
+  more lines of code. IMHO this breaks the idea of "lightweight IP".
+
+  Note the S in SNMP stands for "Simple". Note that "Simple" is
+  relative. SNMP is simple compared to the complex ISO network
+  management protocols CMIP (Common Management Information Protocol)
+  and CMOT (CMip Over Tcp).
+
+MIB II per RFC1213
+  The standard lwIP stack management information base.
+  This is a required MIB, so this is always enabled.
+  When builing lwIP without TCP, the mib-2.tcp group is omitted.
+  The groups EGP, CMOT and transmission are disabled by default.
+  
+  Most mib-2 objects are not writable except:
+  sysName, sysLocation, sysContact, snmpEnableAuthenTraps.
+  Writing to or changing the ARP and IP address and route
+  tables is not possible.
+ 
+  Note lwIP has a very limited notion of IP routing. It currently
+  doen't have a route table and doesn't have a notion of the U,G,H flags.
+  Instead lwIP uses the interface list with only one default interface
+  acting as a single gateway interface (G) for the default route.
+
+  The agent returns a "virtual table" with the default route 0.0.0.0
+  for the default interface and network routes (no H) for each
+  network interface in the netif_list.
+  All routes are considered to be up (U).
+
+Loading additional MIBs
+  MIBs can only be added in compile-time, not in run-time.
+  There is no MIB compiler thus additional MIBs must be hand coded.
+
+Large SNMP message support
+  The packet decoding and encoding routines are designed
+  to use pbuf-chains. Larger payloads then the minimum
+  SNMP requirement of 484 octets are supported if the 
+  PBUF_POOL_SIZE and IP_REASS_BUFSIZE are set to match your
+  local requirement.
+
+1 Building the Agent
+====================
+
+First of all you'll need to add the following define
+to your local lwipopts.h:
+
+#define LWIP_SNMP               1
+
+and add the source files in lwip/src/core/snmp
+and some snmp headers in lwip/src/include/lwip to your makefile.
+
+Note you'll might need to adapt you network driver to update
+the mib2 variables for your interface.
+
+2 Running the Agent
+===================
+
+The following function calls must be made in your program to
+actually get the SNMP agent running.
+
+Before starting the agent you should supply pointers
+to non-volatile memory for sysContact, sysLocation,
+and snmpEnableAuthenTraps. You can do this by calling
+
+snmp_set_syscontact()
+snmp_set_syslocation()
+snmp_set_snmpenableauthentraps()
+
+Additionally you may want to set
+
+snmp_set_sysdescr()
+snmp_set_sysobjid() (if you have a private MIB)
+snmp_set_sysname()
+
+Also before starting the agent you need to setup
+one or more trap destinations using these calls:
+
+snmp_trap_dst_enable();
+snmp_trap_dst_ip_set();
+
+In the lwIP initialisation sequence call snmp_init() just after
+the call to udp_init().
+
+Exactly every 10 msec the SNMP uptime timestamp must be updated with
+snmp_inc_sysuptime(). You should call this from a timer interrupt
+or a timer signal handler depending on your runtime environment.
+
+An alternative way to update the SNMP uptime timestamp is to do a call like
+snmp_add_sysuptime(100) each 1000ms (which is bigger "step", but call to
+a lower frequency). Another one is to not call snmp_inc_sysuptime() or
+snmp_add_sysuptime(), and to define the SNMP_GET_SYSUPTIME(sysuptime) macro.
+This one is undefined by default in mib2.c. SNMP_GET_SYSUPTIME is called inside
+snmp_get_sysuptime(u32_t *value), and enable to change "sysuptime" value only
+when it's queried (any function which need "sysuptime" have to call
+snmp_get_sysuptime).
+
+
+3 Private MIBs
+==============
+
+If want to extend the agent with your own private MIB you'll need to
+add the following define to your local lwipopts.h:
+
+#define SNMP_PRIVATE_MIB        1
+
+You must provide the private_mib.h and associated files yourself.
+Note we don't have a "MIB compiler" that generates C source from a MIB,
+so you're required to do some serious coding if you enable this!
+
+Note the lwIP enterprise ID (26381) is assigned to the lwIP project,
+ALL OBJECT IDENTIFIERS LIVING UNDER THIS ID ARE ASSIGNED BY THE lwIP
+MAINTAINERS!
+
+If you need to create your own private MIB you'll need
+to apply for your own enterprise ID with IANA: http://www.iana.org/numbers.html 
+
+You can set it by passing a struct snmp_obj_id to the agent
+using snmp_set_sysobjid(&my_object_id), just before snmp_init().
+
+Note the object identifiers for thes MIB-2 and your private MIB
+tree must be kept in sorted ascending (lexicographical) order.
+This to ensure correct getnext operation.
+
+An example for a private MIB is part of the "minimal Unix" project:
+contrib/ports/unix/proj/minimal/lwip_prvmib.c
+
+The next chapter gives a more detailed description of the
+MIB-2 tree and the optional private MIB.
+
+4 The Gory Details
+==================
+
+4.0 Object identifiers and the MIB tree.
+
+We have three distinct parts for all object identifiers:
+
+The prefix
+  .iso.org.dod.internet
+
+the middle part 
+  .mgmt.mib-2.ip.ipNetToMediaTable.ipNetToMediaEntry.ipNetToMediaPhysAddress
+
+and the index part
+  .1.192.168.0.1
+
+Objects located above the .internet hierarchy aren't supported.
+Currently only the .mgmt sub-tree is available and
+when the SNMP_PRIVATE_MIB is enabled the .private tree
+becomes available too.
+
+Object identifiers from incoming requests are checked
+for a matching prefix, middle part and index part
+or are expanded(*) for GetNext requests with short
+or inexisting names in the request.
+(* we call this "expansion" but this also
+resembles the "auto-completion" operation)
+
+The middle part is usually located in ROM (const)
+to preserve precious RAM on small microcontrollers.
+However RAM location is possible for an dynamically
+changing private tree.
+
+The index part is handled by functions which in
+turn use dynamically allocated index trees from RAM.
+These trees are updated by e.g. the etharp code
+when new entries are made or removed form the ARP cache.
+
+/** @todo more gory details */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/doc/sys_arch.txt b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/doc/sys_arch.txt
new file mode 100644
index 0000000..66310a9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/doc/sys_arch.txt
@@ -0,0 +1,228 @@
+sys_arch interface for lwIP 0.6++
+
+Author: Adam Dunkels
+
+The operating system emulation layer provides a common interface
+between the lwIP code and the underlying operating system kernel. The
+general idea is that porting lwIP to new architectures requires only
+small changes to a few header files and a new sys_arch
+implementation. It is also possible to do a sys_arch implementation
+that does not rely on any underlying operating system.
+
+The sys_arch provides semaphores and mailboxes to lwIP. For the full
+lwIP functionality, multiple threads support can be implemented in the
+sys_arch, but this is not required for the basic lwIP
+functionality. Previous versions of lwIP required the sys_arch to
+implement timer scheduling as well but as of lwIP 0.5 this is
+implemented in a higher layer.
+
+In addition to the source file providing the functionality of sys_arch,
+the OS emulation layer must provide several header files defining
+macros used throughout lwip.  The files required and the macros they
+must define are listed below the sys_arch description.
+
+Semaphores can be either counting or binary - lwIP works with both
+kinds. Mailboxes are used for message passing and can be implemented
+either as a queue which allows multiple messages to be posted to a
+mailbox, or as a rendez-vous point where only one message can be
+posted at a time. lwIP works with both kinds, but the former type will
+be more efficient. A message in a mailbox is just a pointer, nothing
+more. 
+
+Semaphores are represented by the type "sys_sem_t" which is typedef'd
+in the sys_arch.h file. Mailboxes are equivalently represented by the
+type "sys_mbox_t". lwIP does not place any restrictions on how
+sys_sem_t or sys_mbox_t are represented internally.
+
+The following functions must be implemented by the sys_arch:
+
+- void sys_init(void)
+
+  Is called to initialize the sys_arch layer.
+
+- sys_sem_t sys_sem_new(u8_t count)
+
+  Creates and returns a new semaphore. The "count" argument specifies
+  the initial state of the semaphore.
+
+- void sys_sem_free(sys_sem_t sem)
+
+  Deallocates a semaphore.
+
+- void sys_sem_signal(sys_sem_t sem)
+
+  Signals a semaphore.
+
+- u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout)
+
+  Blocks the thread while waiting for the semaphore to be
+  signaled. If the "timeout" argument is non-zero, the thread should
+  only be blocked for the specified time (measured in
+  milliseconds). If the "timeout" argument is zero, the thread should be
+  blocked until the semaphore is signalled.
+
+  If the timeout argument is non-zero, the return value is the number of
+  milliseconds spent waiting for the semaphore to be signaled. If the
+  semaphore wasn't signaled within the specified time, the return value is
+  SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
+  (i.e., it was already signaled), the function may return zero.
+
+  Notice that lwIP implements a function with a similar name,
+  sys_sem_wait(), that uses the sys_arch_sem_wait() function.
+
+- sys_mbox_t sys_mbox_new(int size)
+
+  Creates an empty mailbox for maximum "size" elements. Elements stored
+  in mailboxes are pointers. You have to define macros "_MBOX_SIZE"
+  in your lwipopts.h, or ignore this parameter in your implementation
+  and use a default size.
+
+- void sys_mbox_free(sys_mbox_t mbox)
+
+  Deallocates a mailbox. If there are messages still present in the
+  mailbox when the mailbox is deallocated, it is an indication of a
+  programming error in lwIP and the developer should be notified.
+
+- void sys_mbox_post(sys_mbox_t mbox, void *msg)
+
+  Posts the "msg" to the mailbox. This function have to block until
+  the "msg" is really posted.
+
+- err_t sys_mbox_trypost(sys_mbox_t mbox, void *msg)
+
+  Try to post the "msg" to the mailbox. Returns ERR_MEM if this one
+  is full, else, ERR_OK if the "msg" is posted.
+
+- u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout)
+
+  Blocks the thread until a message arrives in the mailbox, but does
+  not block the thread longer than "timeout" milliseconds (similar to
+  the sys_arch_sem_wait() function). If "timeout" is 0, the thread should
+  be blocked until a message arrives. The "msg" argument is a result
+  parameter that is set by the function (i.e., by doing "*msg =
+  ptr"). The "msg" parameter maybe NULL to indicate that the message
+  should be dropped.
+
+  The return values are the same as for the sys_arch_sem_wait() function:
+  Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a
+  timeout.
+
+  Note that a function with a similar name, sys_mbox_fetch(), is
+  implemented by lwIP. 
+
+- u32_t sys_arch_mbox_tryfetch(sys_mbox_t mbox, void **msg)
+
+  This is similar to sys_arch_mbox_fetch, however if a message is not
+  present in the mailbox, it immediately returns with the code
+  SYS_MBOX_EMPTY. On success 0 is returned.
+
+  To allow for efficient implementations, this can be defined as a
+  function-like macro in sys_arch.h instead of a normal function. For
+  example, a naive implementation could be:
+    #define sys_arch_mbox_tryfetch(mbox,msg) \
+      sys_arch_mbox_fetch(mbox,msg,1)
+  although this would introduce unnecessary delays.
+  
+- struct sys_timeouts *sys_arch_timeouts(void)
+
+  Returns a pointer to the per-thread sys_timeouts structure. In lwIP,
+  each thread has a list of timeouts which is repressented as a linked
+  list of sys_timeout structures. The sys_timeouts structure holds a
+  pointer to a linked list of timeouts. This function is called by
+  the lwIP timeout scheduler and must not return a NULL value. 
+
+  In a single thread sys_arch implementation, this function will
+  simply return a pointer to a global sys_timeouts variable stored in
+  the sys_arch module.
+  
+If threads are supported by the underlying operating system and if
+such functionality is needed in lwIP, the following function will have
+to be implemented as well:
+
+- sys_thread_t sys_thread_new(char *name, void (* thread)(void *arg), void *arg, int stacksize, int prio)
+
+  Starts a new thread named "name" with priority "prio" that will begin its
+  execution in the function "thread()". The "arg" argument will be passed as an
+  argument to the thread() function. The stack size to used for this thread is
+  the "stacksize" parameter. The id of the new thread is returned. Both the id
+  and the priority are system dependent.
+
+- sys_prot_t sys_arch_protect(void)
+
+  This optional function does a "fast" critical region protection and returns
+  the previous protection level. This function is only called during very short
+  critical regions. An embedded system which supports ISR-based drivers might
+  want to implement this function by disabling interrupts. Task-based systems
+  might want to implement this by using a mutex or disabling tasking. This
+  function should support recursive calls from the same task or interrupt. In
+  other words, sys_arch_protect() could be called while already protected. In
+  that case the return value indicates that it is already protected.
+
+  sys_arch_protect() is only required if your port is supporting an operating
+  system.
+
+- void sys_arch_unprotect(sys_prot_t pval)
+
+  This optional function does a "fast" set of critical region protection to the
+  value specified by pval. See the documentation for sys_arch_protect() for
+  more information. This function is only required if your port is supporting
+  an operating system.
+
+Note:
+
+Be carefull with using mem_malloc() in sys_arch. When malloc() refers to
+mem_malloc() you can run into a circular function call problem. In mem.c
+mem_init() tries to allcate a semaphore using mem_malloc, which of course
+can't be performed when sys_arch uses mem_malloc.
+
+-------------------------------------------------------------------------------
+Additional files required for the "OS support" emulation layer:
+-------------------------------------------------------------------------------
+
+cc.h       - Architecture environment, some compiler specific, some
+             environment specific (probably should move env stuff 
+             to sys_arch.h.)
+
+  Typedefs for the types used by lwip -
+    u8_t, s8_t, u16_t, s16_t, u32_t, s32_t, mem_ptr_t
+
+  Compiler hints for packing lwip's structures -
+    PACK_STRUCT_FIELD(x)
+    PACK_STRUCT_STRUCT
+    PACK_STRUCT_BEGIN
+    PACK_STRUCT_END
+
+  Platform specific diagnostic output -
+    LWIP_PLATFORM_DIAG(x)    - non-fatal, print a message.
+    LWIP_PLATFORM_ASSERT(x)  - fatal, print message and abandon execution.
+    Portability defines for printf formatters:
+    U16_F, S16_F, X16_F, U32_F, S32_F, X32_F, SZT_F
+
+  "lightweight" synchronization mechanisms -
+    SYS_ARCH_DECL_PROTECT(x) - declare a protection state variable.
+    SYS_ARCH_PROTECT(x)      - enter protection mode.
+    SYS_ARCH_UNPROTECT(x)    - leave protection mode.
+
+  If the compiler does not provide memset() this file must include a
+  definition of it, or include a file which defines it.
+
+  This file must either include a system-local  which defines
+  the standard *nix error codes, or it should #define LWIP_PROVIDE_ERRNO
+  to make lwip/arch.h define the codes which are used throughout.
+
+
+perf.h     - Architecture specific performance measurement.
+  Measurement calls made throughout lwip, these can be defined to nothing.
+    PERF_START               - start measuring something.
+    PERF_STOP(x)             - stop measuring something, and record the result.
+
+sys_arch.h - Tied to sys_arch.c
+
+  Arch dependent types for the following objects:
+    sys_sem_t, sys_mbox_t, sys_thread_t,
+  And, optionally:
+    sys_prot_t
+
+  Defines to set vars of sys_mbox_t and sys_sem_t to NULL.
+    SYS_MBOX_NULL NULL
+    SYS_SEM_NULL NULL
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/FILES b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/FILES
new file mode 100644
index 0000000..952aeab
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/FILES
@@ -0,0 +1,13 @@
+api/      - The code for the high-level wrapper API. Not needed if
+            you use the lowel-level call-back/raw API.
+
+core/     - The core of the TPC/IP stack; protocol implementations,
+            memory and buffer management, and the low-level raw API.
+
+include/  - lwIP include files.
+
+netif/    - Generic network interface device drivers are kept here,
+            as well as the ARP module.
+
+For more information on the various subdirectories, check the FILES
+file in each directory.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/api_lib.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/api_lib.c
new file mode 100644
index 0000000..195a9a5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/api_lib.c
@@ -0,0 +1,558 @@
+/**
+ * @file
+ * Sequential API External module
+ *
+ */
+ 
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* This is the part of the API that is linked with
+   the application */
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/api.h"
+#include "lwip/tcpip.h"
+#include "lwip/memp.h"
+
+#include "lwip/ip.h"
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include 
+
+/**
+ * Create a new netconn (of a specific type) that has a callback function.
+ * The corresponding pcb is also created.
+ *
+ * @param t the type of 'connection' to create (@see enum netconn_type)
+ * @param proto the IP protocol for RAW IP pcbs
+ * @param callback a function to call on status changes (RX available, TX'ed)
+ * @return a newly allocated struct netconn or
+ *         NULL on memory error
+ */
+struct netconn*
+netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto, netconn_callback callback)
+{
+  struct netconn *conn;
+  struct api_msg msg;
+
+  conn = netconn_alloc(t, callback);
+  if (conn != NULL ) {
+    msg.function = do_newconn;
+    msg.msg.msg.n.proto = proto;
+    msg.msg.conn = conn;
+    TCPIP_APIMSG(&msg);
+
+    if (conn->err != ERR_OK) {
+      LWIP_ASSERT("freeing conn without freeing pcb", conn->pcb.tcp == NULL);
+      LWIP_ASSERT("conn has no op_completed", conn->op_completed != SYS_SEM_NULL);
+      LWIP_ASSERT("conn has no recvmbox", conn->recvmbox != SYS_MBOX_NULL);
+      LWIP_ASSERT("conn->acceptmbox shouldn't exist", conn->acceptmbox == SYS_MBOX_NULL);
+      sys_sem_free(conn->op_completed);
+      sys_mbox_free(conn->recvmbox);
+      memp_free(MEMP_NETCONN, conn);
+      return NULL;
+    }
+  }
+  return conn;
+}
+
+/**
+ * Close a netconn 'connection' and free its resources.
+ * UDP and RAW connection are completely closed, TCP pcbs might still be in a waitstate
+ * after this returns.
+ *
+ * @param conn the netconn to delete
+ * @return ERR_OK if the connection was deleted
+ */
+err_t
+netconn_delete(struct netconn *conn)
+{
+  struct api_msg msg;
+
+  /* No ASSERT here because possible to get a (conn == NULL) if we got an accept error */
+  if (conn == NULL) {
+    return ERR_OK;
+  }
+
+  msg.function = do_delconn;
+  msg.msg.conn = conn;
+  tcpip_apimsg(&msg);
+
+  conn->pcb.tcp = NULL;
+  netconn_free(conn);
+
+  return ERR_OK;
+}
+
+/**
+ * Get the local or remote IP address and port of a netconn.
+ * For RAW netconns, this returns the protocol instead of a port!
+ *
+ * @param conn the netconn to query
+ * @param addr a pointer to which to save the IP address
+ * @param port a pointer to which to save the port (or protocol for RAW)
+ * @param local 1 to get the local IP address, 0 to get the remote one
+ * @return ERR_CONN for invalid connections
+ *         ERR_OK if the information was retrieved
+ */
+err_t
+netconn_getaddr(struct netconn *conn, struct ip_addr *addr, u16_t *port, u8_t local)
+{
+  struct api_msg msg;
+
+  LWIP_ERROR("netconn_getaddr: invalid conn", (conn != NULL), return ERR_ARG;);
+  LWIP_ERROR("netconn_getaddr: invalid addr", (addr != NULL), return ERR_ARG;);
+  LWIP_ERROR("netconn_getaddr: invalid port", (port != NULL), return ERR_ARG;);
+
+  msg.function = do_getaddr;
+  msg.msg.conn = conn;
+  msg.msg.msg.ad.ipaddr = addr;
+  msg.msg.msg.ad.port = port;
+  msg.msg.msg.ad.local = local;
+  TCPIP_APIMSG(&msg);
+
+  return conn->err;
+}
+
+/**
+ * Bind a netconn to a specific local IP address and port.
+ * Binding one netconn twice might not always be checked correctly!
+ *
+ * @param conn the netconn to bind
+ * @param addr the local IP address to bind the netconn to (use IP_ADDR_ANY
+ *             to bind to all addresses)
+ * @param port the local port to bind the netconn to (not used for RAW)
+ * @return ERR_OK if bound, any other err_t on failure
+ */
+err_t
+netconn_bind(struct netconn *conn, struct ip_addr *addr, u16_t port)
+{
+  struct api_msg msg;
+
+  LWIP_ERROR("netconn_bind: invalid conn", (conn != NULL), return ERR_ARG;);
+
+  msg.function = do_bind;
+  msg.msg.conn = conn;
+  msg.msg.msg.bc.ipaddr = addr;
+  msg.msg.msg.bc.port = port;
+  TCPIP_APIMSG(&msg);
+  return conn->err;
+}
+
+/**
+ * Connect a netconn to a specific remote IP address and port.
+ *
+ * @param conn the netconn to connect
+ * @param addr the remote IP address to connect to
+ * @param port the remote port to connect to (no used for RAW)
+ * @return ERR_OK if connected, return value of tcp_/udp_/raw_connect otherwise
+ */
+err_t
+netconn_connect(struct netconn *conn, struct ip_addr *addr, u16_t port)
+{
+  struct api_msg msg;
+
+  LWIP_ERROR("netconn_connect: invalid conn", (conn != NULL), return ERR_ARG;);
+
+  msg.function = do_connect;
+  msg.msg.conn = conn;
+  msg.msg.msg.bc.ipaddr = addr;
+  msg.msg.msg.bc.port = port;
+  /* This is the only function which need to not block tcpip_thread */
+  tcpip_apimsg(&msg);
+  return conn->err;
+}
+
+/**
+ * Disconnect a netconn from its current peer (only valid for UDP netconns).
+ *
+ * @param conn the netconn to disconnect
+ * @return TODO: return value is not set here...
+ */
+err_t
+netconn_disconnect(struct netconn *conn)
+{
+  struct api_msg msg;
+
+  LWIP_ERROR("netconn_disconnect: invalid conn", (conn != NULL), return ERR_ARG;);
+
+  msg.function = do_disconnect;
+  msg.msg.conn = conn;
+  TCPIP_APIMSG(&msg);
+  return conn->err;
+}
+
+/**
+ * Set a TCP netconn into listen mode
+ *
+ * @param conn the tcp netconn to set to listen mode
+ * @param backlog the listen backlog, only used if TCP_LISTEN_BACKLOG==1
+ * @return ERR_OK if the netconn was set to listen (UDP and RAW netconns
+ *         don't return any error (yet?))
+ */
+err_t
+netconn_listen_with_backlog(struct netconn *conn, u8_t backlog)
+{
+  struct api_msg msg;
+
+  /* This does no harm. If TCP_LISTEN_BACKLOG is off, backlog is unused. */
+  LWIP_UNUSED_ARG(backlog);
+
+  LWIP_ERROR("netconn_listen: invalid conn", (conn != NULL), return ERR_ARG;);
+
+  msg.function = do_listen;
+  msg.msg.conn = conn;
+#if TCP_LISTEN_BACKLOG
+  msg.msg.msg.lb.backlog = backlog;
+#endif /* TCP_LISTEN_BACKLOG */
+  TCPIP_APIMSG(&msg);
+  return conn->err;
+}
+
+/**
+ * Accept a new connection on a TCP listening netconn.
+ *
+ * @param conn the TCP listen netconn
+ * @return the newly accepted netconn or NULL on timeout
+ */
+struct netconn *
+netconn_accept(struct netconn *conn)
+{
+  struct netconn *newconn;
+
+  LWIP_ERROR("netconn_accept: invalid conn",       (conn != NULL),                      return NULL;);
+  LWIP_ERROR("netconn_accept: invalid acceptmbox", (conn->acceptmbox != SYS_MBOX_NULL), return NULL;);
+
+#if LWIP_SO_RCVTIMEO
+  if (sys_arch_mbox_fetch(conn->acceptmbox, (void *)&newconn, conn->recv_timeout) == SYS_ARCH_TIMEOUT) {
+    newconn = NULL;
+  } else
+#else
+  sys_arch_mbox_fetch(conn->acceptmbox, (void *)&newconn, 0);
+#endif /* LWIP_SO_RCVTIMEO*/
+  {
+    /* Register event with callback */
+    API_EVENT(conn, NETCONN_EVT_RCVMINUS, 0);
+
+#if TCP_LISTEN_BACKLOG
+    if (newconn != NULL) {
+      /* Let the stack know that we have accepted the connection. */
+      struct api_msg msg;
+      msg.function = do_recv;
+      msg.msg.conn = conn;
+      TCPIP_APIMSG(&msg);
+    }
+#endif /* TCP_LISTEN_BACKLOG */
+  }
+
+  return newconn;
+}
+
+/**
+ * Receive data (in form of a netbuf containing a packet buffer) from a netconn
+ *
+ * @param conn the netconn from which to receive data
+ * @return a new netbuf containing received data or NULL on memory error or timeout
+ */
+struct netbuf *
+netconn_recv(struct netconn *conn)
+{
+  struct api_msg msg;
+  struct netbuf *buf = NULL;
+  struct pbuf *p;
+  u16_t len;
+
+  LWIP_ERROR("netconn_recv: invalid conn",  (conn != NULL), return NULL;);
+
+  if (conn->recvmbox == SYS_MBOX_NULL) {
+    /* @todo: should calling netconn_recv on a TCP listen conn be fatal (ERR_CONN)?? */
+    /* TCP listen conns don't have a recvmbox! */
+    conn->err = ERR_CONN;
+    return NULL;
+  }
+
+  if (ERR_IS_FATAL(conn->err)) {
+    return NULL;
+  }
+
+  if (conn->type == NETCONN_TCP) {
+#if LWIP_TCP
+    if (conn->state == NETCONN_LISTEN) {
+      /* @todo: should calling netconn_recv on a TCP listen conn be fatal?? */
+      conn->err = ERR_CONN;
+      return NULL;
+    }
+
+    buf = memp_malloc(MEMP_NETBUF);
+
+    if (buf == NULL) {
+      conn->err = ERR_MEM;
+      return NULL;
+    }
+
+#if LWIP_SO_RCVTIMEO
+    if (sys_arch_mbox_fetch(conn->recvmbox, (void *)&p, conn->recv_timeout)==SYS_ARCH_TIMEOUT) {
+      memp_free(MEMP_NETBUF, buf);
+      conn->err = ERR_TIMEOUT;
+      return NULL;
+    }
+#else
+    sys_arch_mbox_fetch(conn->recvmbox, (void *)&p, 0);
+#endif /* LWIP_SO_RCVTIMEO*/
+
+    if (p != NULL) {
+      len = p->tot_len;
+      SYS_ARCH_DEC(conn->recv_avail, len);
+    } else {
+      len = 0;
+    }
+
+    /* Register event with callback */
+    API_EVENT(conn, NETCONN_EVT_RCVMINUS, len);
+
+    /* If we are closed, we indicate that we no longer wish to use the socket */
+    if (p == NULL) {
+      memp_free(MEMP_NETBUF, buf);
+      /* Avoid to lose any previous error code */
+      if (conn->err == ERR_OK) {
+        conn->err = ERR_CLSD;
+      }
+      return NULL;
+    }
+
+    buf->p = p;
+    buf->ptr = p;
+    buf->port = 0;
+    buf->addr = NULL;
+
+    /* Let the stack know that we have taken the data. */
+    msg.function = do_recv;
+    msg.msg.conn = conn;
+    if (buf != NULL) {
+      msg.msg.msg.r.len = buf->p->tot_len;
+    } else {
+      msg.msg.msg.r.len = 1;
+    }
+    TCPIP_APIMSG(&msg);
+#endif /* LWIP_TCP */
+  } else {
+#if (LWIP_UDP || LWIP_RAW)
+#if LWIP_SO_RCVTIMEO
+    if (sys_arch_mbox_fetch(conn->recvmbox, (void *)&buf, conn->recv_timeout)==SYS_ARCH_TIMEOUT) {
+      buf = NULL;
+    }
+#else
+    sys_arch_mbox_fetch(conn->recvmbox, (void *)&buf, 0);
+#endif /* LWIP_SO_RCVTIMEO*/
+    if (buf!=NULL) {
+      SYS_ARCH_DEC(conn->recv_avail, buf->p->tot_len);
+      /* Register event with callback */
+      API_EVENT(conn, NETCONN_EVT_RCVMINUS, buf->p->tot_len);
+    }
+#endif /* (LWIP_UDP || LWIP_RAW) */
+  }
+
+  LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_recv: received %p (err %d)\n", (void *)buf, conn->err));
+
+  return buf;
+}
+
+/**
+ * Send data (in form of a netbuf) to a specific remote IP address and port.
+ * Only to be used for UDP and RAW netconns (not TCP).
+ *
+ * @param conn the netconn over which to send data
+ * @param buf a netbuf containing the data to send
+ * @param addr the remote IP address to which to send the data
+ * @param port the remote port to which to send the data
+ * @return ERR_OK if data was sent, any other err_t on error
+ */
+err_t
+netconn_sendto(struct netconn *conn, struct netbuf *buf, struct ip_addr *addr, u16_t port)
+{
+  if (buf != NULL) {
+    buf->addr = addr;
+    buf->port = port;
+    return netconn_send(conn, buf);
+  }
+  return ERR_VAL;
+}
+
+/**
+ * Send data over a UDP or RAW netconn (that is already connected).
+ *
+ * @param conn the UDP or RAW netconn over which to send data
+ * @param buf a netbuf containing the data to send
+ * @return ERR_OK if data was sent, any other err_t on error
+ */
+err_t
+netconn_send(struct netconn *conn, struct netbuf *buf)
+{
+  struct api_msg msg;
+
+  LWIP_ERROR("netconn_send: invalid conn",  (conn != NULL), return ERR_ARG;);
+
+  LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_send: sending %"U16_F" bytes\n", buf->p->tot_len));
+  msg.function = do_send;
+  msg.msg.conn = conn;
+  msg.msg.msg.b = buf;
+  TCPIP_APIMSG(&msg);
+  return conn->err;
+}
+
+/**
+ * Send data over a TCP netconn.
+ *
+ * @param conn the TCP netconn over which to send data
+ * @param dataptr pointer to the application buffer that contains the data to send
+ * @param size size of the application data to send
+ * @param apiflags combination of following flags :
+ * - NETCONN_COPY (0x01) data will be copied into memory belonging to the stack
+ * - NETCONN_MORE (0x02) for TCP connection, PSH flag will be set on last segment sent
+ * @return ERR_OK if data was sent, any other err_t on error
+ */
+err_t
+netconn_write(struct netconn *conn, const void *dataptr, size_t size, u8_t apiflags)
+{
+  struct api_msg msg;
+
+  LWIP_ERROR("netconn_write: invalid conn",  (conn != NULL), return ERR_ARG;);
+  LWIP_ERROR("netconn_write: invalid conn->type",  (conn->type == NETCONN_TCP), return ERR_VAL;);
+
+  msg.function = do_write;
+  msg.msg.conn = conn;
+  msg.msg.msg.w.dataptr = dataptr;
+  msg.msg.msg.w.apiflags = apiflags;
+  msg.msg.msg.w.len = size;
+  /* For locking the core: this _can_ be delayed on low memory/low send buffer,
+     but if it is, this is done inside api_msg.c:do_write(), so we can use the
+     non-blocking version here. */
+  TCPIP_APIMSG(&msg);
+  return conn->err;
+}
+
+/**
+ * Close a TCP netconn (doesn't delete it).
+ *
+ * @param conn the TCP netconn to close
+ * @return ERR_OK if the netconn was closed, any other err_t on error
+ */
+err_t
+netconn_close(struct netconn *conn)
+{
+  struct api_msg msg;
+
+  LWIP_ERROR("netconn_close: invalid conn",  (conn != NULL), return ERR_ARG;);
+
+  msg.function = do_close;
+  msg.msg.conn = conn;
+  tcpip_apimsg(&msg);
+  return conn->err;
+}
+
+#if LWIP_IGMP
+/**
+ * Join multicast groups for UDP netconns.
+ *
+ * @param conn the UDP netconn for which to change multicast addresses
+ * @param multiaddr IP address of the multicast group to join or leave
+ * @param interface the IP address of the network interface on which to send
+ *                  the igmp message
+ * @param join_or_leave flag whether to send a join- or leave-message
+ * @return ERR_OK if the action was taken, any err_t on error
+ */
+err_t
+netconn_join_leave_group(struct netconn *conn,
+                         struct ip_addr *multiaddr,
+                         struct ip_addr *interface,
+                         enum netconn_igmp join_or_leave)
+{
+  struct api_msg msg;
+
+  LWIP_ERROR("netconn_join_leave_group: invalid conn",  (conn != NULL), return ERR_ARG;);
+
+  msg.function = do_join_leave_group;
+  msg.msg.conn = conn;
+  msg.msg.msg.jl.multiaddr = multiaddr;
+  msg.msg.msg.jl.interface = interface;
+  msg.msg.msg.jl.join_or_leave = join_or_leave;
+  TCPIP_APIMSG(&msg);
+  return conn->err;
+}
+#endif /* LWIP_IGMP */
+
+#if LWIP_DNS
+/**
+ * Execute a DNS query, only one IP address is returned
+ *
+ * @param name a string representation of the DNS host name to query
+ * @param addr a preallocated struct ip_addr where to store the resolved IP address
+ * @return ERR_OK: resolving succeeded
+ *         ERR_MEM: memory error, try again later
+ *         ERR_ARG: dns client not initialized or invalid hostname
+ *         ERR_VAL: dns server response was invalid
+ */
+err_t
+netconn_gethostbyname(const char *name, struct ip_addr *addr)
+{
+  struct dns_api_msg msg;
+  err_t err;
+  sys_sem_t sem;
+
+  LWIP_ERROR("netconn_gethostbyname: invalid name", (name != NULL), return ERR_ARG;);
+  LWIP_ERROR("netconn_gethostbyname: invalid addr", (addr != NULL), return ERR_ARG;);
+
+  sem = sys_sem_new(0);
+  if (sem == SYS_SEM_NULL) {
+    return ERR_MEM;
+  }
+
+  msg.name = name;
+  msg.addr = addr;
+  msg.err = &err;
+  msg.sem = sem;
+
+  tcpip_callback(do_gethostbyname, &msg);
+  sys_sem_wait(sem);
+  sys_sem_free(sem);
+
+  return err;
+}
+#endif /* LWIP_DNS*/
+
+#endif /* LWIP_NETCONN */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/api_msg.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/api_msg.c
new file mode 100644
index 0000000..46c9abf
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/api_msg.c
@@ -0,0 +1,1243 @@
+/**
+ * @file
+ * Sequential API Internal module
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/api_msg.h"
+
+#include "lwip/ip.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+#include "lwip/raw.h"
+
+#include "lwip/memp.h"
+#include "lwip/tcpip.h"
+#include "lwip/igmp.h"
+#include "lwip/dns.h"
+
+#include 
+
+/* forward declarations */
+#if LWIP_TCP
+static err_t do_writemore(struct netconn *conn);
+static void do_close_internal(struct netconn *conn);
+#endif
+
+#if LWIP_RAW
+/**
+ * Receive callback function for RAW netconns.
+ * Doesn't 'eat' the packet, only references it and sends it to
+ * conn->recvmbox
+ *
+ * @see raw.h (struct raw_pcb.recv) for parameters and return value
+ */
+static u8_t
+recv_raw(void *arg, struct raw_pcb *pcb, struct pbuf *p,
+    struct ip_addr *addr)
+{
+  struct pbuf *q;
+  struct netbuf *buf;
+  struct netconn *conn;
+#if LWIP_SO_RCVBUF
+  int recv_avail;
+#endif /* LWIP_SO_RCVBUF */
+
+  LWIP_UNUSED_ARG(addr);
+  conn = arg;
+
+#if LWIP_SO_RCVBUF
+  SYS_ARCH_GET(conn->recv_avail, recv_avail);
+  if ((conn != NULL) && (conn->recvmbox != SYS_MBOX_NULL) &&
+      ((recv_avail + (int)(p->tot_len)) <= conn->recv_bufsize)) {
+#else  /* LWIP_SO_RCVBUF */
+  if ((conn != NULL) && (conn->recvmbox != SYS_MBOX_NULL)) {
+#endif /* LWIP_SO_RCVBUF */
+    /* copy the whole packet into new pbufs */
+    q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
+    if(q != NULL) {
+      if (pbuf_copy(q, p) != ERR_OK) {
+        pbuf_free(q);
+        q = NULL;
+      }
+    }
+
+    if(q != NULL) {
+      buf = memp_malloc(MEMP_NETBUF);
+      if (buf == NULL) {
+        pbuf_free(q);
+        return 0;
+      }
+
+      buf->p = q;
+      buf->ptr = q;
+      buf->addr = &(((struct ip_hdr*)(q->payload))->src);
+      buf->port = pcb->protocol;
+
+      if (sys_mbox_trypost(conn->recvmbox, buf) != ERR_OK) {
+        netbuf_delete(buf);
+        return 0;
+      } else {
+        SYS_ARCH_INC(conn->recv_avail, q->tot_len);
+        /* Register event with callback */
+        API_EVENT(conn, NETCONN_EVT_RCVPLUS, q->tot_len);
+      }
+    }
+  }
+
+  return 0; /* do not eat the packet */
+}
+#endif /* LWIP_RAW*/
+
+#if LWIP_UDP
+/**
+ * Receive callback function for UDP netconns.
+ * Posts the packet to conn->recvmbox or deletes it on memory error.
+ *
+ * @see udp.h (struct udp_pcb.recv) for parameters
+ */
+static void
+recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p,
+   struct ip_addr *addr, u16_t port)
+{
+  struct netbuf *buf;
+  struct netconn *conn;
+#if LWIP_SO_RCVBUF
+  int recv_avail;
+#endif /* LWIP_SO_RCVBUF */
+
+  LWIP_UNUSED_ARG(pcb); /* only used for asserts... */
+  LWIP_ASSERT("recv_udp must have a pcb argument", pcb != NULL);
+  LWIP_ASSERT("recv_udp must have an argument", arg != NULL);
+  conn = arg;
+  LWIP_ASSERT("recv_udp: recv for wrong pcb!", conn->pcb.udp == pcb);
+
+#if LWIP_SO_RCVBUF
+  SYS_ARCH_GET(conn->recv_avail, recv_avail);
+  if ((conn == NULL) || (conn->recvmbox == SYS_MBOX_NULL) ||
+      ((recv_avail + (int)(p->tot_len)) > conn->recv_bufsize)) {
+#else  /* LWIP_SO_RCVBUF */
+  if ((conn == NULL) || (conn->recvmbox == SYS_MBOX_NULL)) {
+#endif /* LWIP_SO_RCVBUF */
+    pbuf_free(p);
+    return;
+  }
+
+  buf = memp_malloc(MEMP_NETBUF);
+  if (buf == NULL) {
+    pbuf_free(p);
+    return;
+  } else {
+    buf->p = p;
+    buf->ptr = p;
+    buf->addr = addr;
+    buf->port = port;
+#if LWIP_NETBUF_RECVINFO
+    {
+      const struct ip_hdr* iphdr = ip_current_header();
+      /* get the UDP header - always in the first pbuf, ensured by udp_input */
+      const struct udp_hdr* udphdr = (void*)(((char*)iphdr) + IPH_LEN(iphdr));
+      buf->toaddr = (struct ip_addr*)&iphdr->dest;
+      buf->toport = udphdr->dest;
+    }
+#endif /* LWIP_NETBUF_RECVINFO */
+  }
+
+  if (sys_mbox_trypost(conn->recvmbox, buf) != ERR_OK) {
+    netbuf_delete(buf);
+    return;
+  } else {
+    SYS_ARCH_INC(conn->recv_avail, p->tot_len);
+    /* Register event with callback */
+    API_EVENT(conn, NETCONN_EVT_RCVPLUS, p->tot_len);
+  }
+}
+#endif /* LWIP_UDP */
+
+#if LWIP_TCP
+/**
+ * Receive callback function for TCP netconns.
+ * Posts the packet to conn->recvmbox, but doesn't delete it on errors.
+ *
+ * @see tcp.h (struct tcp_pcb.recv) for parameters and return value
+ */
+static err_t
+recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
+{
+  struct netconn *conn;
+  u16_t len;
+
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_ASSERT("recv_tcp must have a pcb argument", pcb != NULL);
+  LWIP_ASSERT("recv_tcp must have an argument", arg != NULL);
+  conn = arg;
+  LWIP_ASSERT("recv_tcp: recv for wrong pcb!", conn->pcb.tcp == pcb);
+
+  if ((conn == NULL) || (conn->recvmbox == SYS_MBOX_NULL)) {
+    return ERR_VAL;
+  }
+
+  conn->err = err;
+  if (p != NULL) {
+    len = p->tot_len;
+    SYS_ARCH_INC(conn->recv_avail, len);
+  } else {
+    len = 0;
+  }
+
+  if (sys_mbox_trypost(conn->recvmbox, p) != ERR_OK) {
+    return ERR_MEM;
+  } else {
+    /* Register event with callback */
+    API_EVENT(conn, NETCONN_EVT_RCVPLUS, len);
+  }
+
+  return ERR_OK;
+}
+
+/**
+ * Poll callback function for TCP netconns.
+ * Wakes up an application thread that waits for a connection to close
+ * or data to be sent. The application thread then takes the
+ * appropriate action to go on.
+ *
+ * Signals the conn->sem.
+ * netconn_close waits for conn->sem if closing failed.
+ *
+ * @see tcp.h (struct tcp_pcb.poll) for parameters and return value
+ */
+static err_t
+poll_tcp(void *arg, struct tcp_pcb *pcb)
+{
+  struct netconn *conn = arg;
+
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_ASSERT("conn != NULL", (conn != NULL));
+
+  if (conn->state == NETCONN_WRITE) {
+    do_writemore(conn);
+  } else if (conn->state == NETCONN_CLOSE) {
+    do_close_internal(conn);
+  }
+
+  return ERR_OK;
+}
+
+/**
+ * Sent callback function for TCP netconns.
+ * Signals the conn->sem and calls API_EVENT.
+ * netconn_write waits for conn->sem if send buffer is low.
+ *
+ * @see tcp.h (struct tcp_pcb.sent) for parameters and return value
+ */
+static err_t
+sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len)
+{
+  struct netconn *conn = arg;
+
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_ASSERT("conn != NULL", (conn != NULL));
+
+  if (conn->state == NETCONN_WRITE) {
+    LWIP_ASSERT("conn->pcb.tcp != NULL", conn->pcb.tcp != NULL);
+    do_writemore(conn);
+  } else if (conn->state == NETCONN_CLOSE) {
+    do_close_internal(conn);
+  }
+
+  if (conn) {
+    if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT)) {
+      API_EVENT(conn, NETCONN_EVT_SENDPLUS, len);
+    }
+  }
+  
+  return ERR_OK;
+}
+
+/**
+ * Error callback function for TCP netconns.
+ * Signals conn->sem, posts to all conn mboxes and calls API_EVENT.
+ * The application thread has then to decide what to do.
+ *
+ * @see tcp.h (struct tcp_pcb.err) for parameters
+ */
+static void
+err_tcp(void *arg, err_t err)
+{
+  struct netconn *conn;
+
+  conn = arg;
+  LWIP_ASSERT("conn != NULL", (conn != NULL));
+
+  conn->pcb.tcp = NULL;
+
+  conn->err = err;
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+    /* Register event with callback */
+    API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0);
+    sys_mbox_post(conn->recvmbox, NULL);
+  }
+  if (conn->op_completed != SYS_SEM_NULL && conn->state == NETCONN_CONNECT) {
+    conn->state = NETCONN_NONE;
+    sys_sem_signal(conn->op_completed);
+  }
+  if (conn->acceptmbox != SYS_MBOX_NULL) {
+    /* Register event with callback */
+    API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0);
+    sys_mbox_post(conn->acceptmbox, NULL);
+  }
+  if ((conn->state == NETCONN_WRITE) || (conn->state == NETCONN_CLOSE)) {
+    /* calling do_writemore/do_close_internal is not necessary
+       since the pcb has already been deleted! */
+    conn->state = NETCONN_NONE;
+    /* wake up the waiting task */
+    sys_sem_signal(conn->op_completed);
+  }
+}
+
+/**
+ * Setup a tcp_pcb with the correct callback function pointers
+ * and their arguments.
+ *
+ * @param conn the TCP netconn to setup
+ */
+static void
+setup_tcp(struct netconn *conn)
+{
+  struct tcp_pcb *pcb;
+
+  pcb = conn->pcb.tcp;
+  tcp_arg(pcb, conn);
+  tcp_recv(pcb, recv_tcp);
+  tcp_sent(pcb, sent_tcp);
+  tcp_poll(pcb, poll_tcp, 4);
+  tcp_err(pcb, err_tcp);
+}
+
+/**
+ * Accept callback function for TCP netconns.
+ * Allocates a new netconn and posts that to conn->acceptmbox.
+ *
+ * @see tcp.h (struct tcp_pcb_listen.accept) for parameters and return value
+ */
+static err_t
+accept_function(void *arg, struct tcp_pcb *newpcb, err_t err)
+{
+  struct netconn *newconn;
+  struct netconn *conn;
+
+#if API_MSG_DEBUG
+#if TCP_DEBUG
+  tcp_debug_print_state(newpcb->state);
+#endif /* TCP_DEBUG */
+#endif /* API_MSG_DEBUG */
+  conn = (struct netconn *)arg;
+
+  LWIP_ERROR("accept_function: invalid conn->acceptmbox",
+             conn->acceptmbox != SYS_MBOX_NULL, return ERR_VAL;);
+
+  /* We have to set the callback here even though
+   * the new socket is unknown. conn->socket is marked as -1. */
+  newconn = netconn_alloc(conn->type, conn->callback);
+  if (newconn == NULL) {
+    return ERR_MEM;
+  }
+  newconn->pcb.tcp = newpcb;
+  setup_tcp(newconn);
+  newconn->err = err;
+
+  if (sys_mbox_trypost(conn->acceptmbox, newconn) != ERR_OK) {
+    /* When returning != ERR_OK, the connection is aborted in tcp_process(),
+       so do nothing here! */
+    newconn->pcb.tcp = NULL;
+    netconn_free(newconn);
+    return ERR_MEM;
+  } else {
+    /* Register event with callback */
+    API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0);
+  }
+
+  return ERR_OK;
+}
+#endif /* LWIP_TCP */
+
+/**
+ * Create a new pcb of a specific type.
+ * Called from do_newconn().
+ *
+ * @param msg the api_msg_msg describing the connection type
+ * @return msg->conn->err, but the return value is currently ignored
+ */
+static err_t
+pcb_new(struct api_msg_msg *msg)
+{
+   msg->conn->err = ERR_OK;
+
+   LWIP_ASSERT("pcb_new: pcb already allocated", msg->conn->pcb.tcp == NULL);
+
+   /* Allocate a PCB for this connection */
+   switch(NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+   case NETCONN_RAW:
+     msg->conn->pcb.raw = raw_new(msg->msg.n.proto);
+     if(msg->conn->pcb.raw == NULL) {
+       msg->conn->err = ERR_MEM;
+       break;
+     }
+     raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
+     break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+   case NETCONN_UDP:
+     msg->conn->pcb.udp = udp_new();
+     if(msg->conn->pcb.udp == NULL) {
+       msg->conn->err = ERR_MEM;
+       break;
+     }
+#if LWIP_UDPLITE
+     if (msg->conn->type==NETCONN_UDPLITE) {
+       udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
+     }
+#endif /* LWIP_UDPLITE */
+     if (msg->conn->type==NETCONN_UDPNOCHKSUM) {
+       udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
+     }
+     udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+     break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+   case NETCONN_TCP:
+     msg->conn->pcb.tcp = tcp_new();
+     if(msg->conn->pcb.tcp == NULL) {
+       msg->conn->err = ERR_MEM;
+       break;
+     }
+     setup_tcp(msg->conn);
+     break;
+#endif /* LWIP_TCP */
+   default:
+     /* Unsupported netconn type, e.g. protocol disabled */
+     msg->conn->err = ERR_VAL;
+     break;
+   }
+
+  return msg->conn->err;
+}
+
+/**
+ * Create a new pcb of a specific type inside a netconn.
+ * Called from netconn_new_with_proto_and_callback.
+ *
+ * @param msg the api_msg_msg describing the connection type
+ */
+void
+do_newconn(struct api_msg_msg *msg)
+{
+   if(msg->conn->pcb.tcp == NULL) {
+     pcb_new(msg);
+   }
+   /* Else? This "new" connection already has a PCB allocated. */
+   /* Is this an error condition? Should it be deleted? */
+   /* We currently just are happy and return. */
+
+   TCPIP_APIMSG_ACK(msg);
+}
+
+/**
+ * Create a new netconn (of a specific type) that has a callback function.
+ * The corresponding pcb is NOT created!
+ *
+ * @param t the type of 'connection' to create (@see enum netconn_type)
+ * @param proto the IP protocol for RAW IP pcbs
+ * @param callback a function to call on status changes (RX available, TX'ed)
+ * @return a newly allocated struct netconn or
+ *         NULL on memory error
+ */
+struct netconn*
+netconn_alloc(enum netconn_type t, netconn_callback callback)
+{
+  struct netconn *conn;
+  int size;
+
+  conn = memp_malloc(MEMP_NETCONN);
+  if (conn == NULL) {
+    return NULL;
+  }
+
+  conn->err = ERR_OK;
+  conn->type = t;
+  conn->pcb.tcp = NULL;
+
+#if (DEFAULT_RAW_RECVMBOX_SIZE == DEFAULT_UDP_RECVMBOX_SIZE) && \
+    (DEFAULT_RAW_RECVMBOX_SIZE == DEFAULT_TCP_RECVMBOX_SIZE)
+  size = DEFAULT_RAW_RECVMBOX_SIZE;
+#else
+  switch(NETCONNTYPE_GROUP(t)) {
+#if LWIP_RAW
+  case NETCONN_RAW:
+    size = DEFAULT_RAW_RECVMBOX_SIZE;
+    break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+  case NETCONN_UDP:
+    size = DEFAULT_UDP_RECVMBOX_SIZE;
+    break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+  case NETCONN_TCP:
+    size = DEFAULT_TCP_RECVMBOX_SIZE;
+    break;
+#endif /* LWIP_TCP */
+  default:
+    LWIP_ASSERT("netconn_alloc: undefined netconn_type", 0);
+    break;
+  }
+#endif
+
+  if ((conn->op_completed = sys_sem_new(0)) == SYS_SEM_NULL) {
+    memp_free(MEMP_NETCONN, conn);
+    return NULL;
+  }
+  if ((conn->recvmbox = sys_mbox_new(size)) == SYS_MBOX_NULL) {
+    sys_sem_free(conn->op_completed);
+    memp_free(MEMP_NETCONN, conn);
+    return NULL;
+  }
+
+  conn->acceptmbox   = SYS_MBOX_NULL;
+  conn->state        = NETCONN_NONE;
+  /* initialize socket to -1 since 0 is a valid socket */
+  conn->socket       = -1;
+  conn->callback     = callback;
+  conn->recv_avail   = 0;
+#if LWIP_TCP
+  conn->write_msg    = NULL;
+  conn->write_offset = 0;
+#if LWIP_TCPIP_CORE_LOCKING
+  conn->write_delayed = 0;
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+#endif /* LWIP_TCP */
+#if LWIP_SO_RCVTIMEO
+  conn->recv_timeout = 0;
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+  conn->recv_bufsize = RECV_BUFSIZE_DEFAULT;
+#endif /* LWIP_SO_RCVBUF */
+  return conn;
+}
+
+/**
+ * Delete a netconn and all its resources.
+ * The pcb is NOT freed (since we might not be in the right thread context do this).
+ *
+ * @param conn the netconn to free
+ */
+void
+netconn_free(struct netconn *conn)
+{
+  void *mem;
+  LWIP_ASSERT("PCB must be deallocated outside this function", conn->pcb.tcp == NULL);
+
+  /* Drain the recvmbox. */
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+    while (sys_mbox_tryfetch(conn->recvmbox, &mem) != SYS_MBOX_EMPTY) {
+      if (conn->type == NETCONN_TCP) {
+        if(mem != NULL) {
+          pbuf_free((struct pbuf *)mem);
+        }
+      } else {
+        netbuf_delete((struct netbuf *)mem);
+      }
+    }
+    sys_mbox_free(conn->recvmbox);
+    conn->recvmbox = SYS_MBOX_NULL;
+  }
+
+  /* Drain the acceptmbox. */
+  if (conn->acceptmbox != SYS_MBOX_NULL) {
+    while (sys_mbox_tryfetch(conn->acceptmbox, &mem) != SYS_MBOX_EMPTY) {
+      netconn_delete((struct netconn *)mem);
+    }
+    sys_mbox_free(conn->acceptmbox);
+    conn->acceptmbox = SYS_MBOX_NULL;
+  }
+
+  sys_sem_free(conn->op_completed);
+  conn->op_completed = SYS_SEM_NULL;
+
+  memp_free(MEMP_NETCONN, conn);
+}
+
+#if LWIP_TCP
+/**
+ * Internal helper function to close a TCP netconn: since this sometimes
+ * doesn't work at the first attempt, this function is called from multiple
+ * places.
+ *
+ * @param conn the TCP netconn to close
+ */
+static void
+do_close_internal(struct netconn *conn)
+{
+  err_t err;
+
+  LWIP_ASSERT("invalid conn", (conn != NULL));
+  LWIP_ASSERT("this is for tcp netconns only", (conn->type == NETCONN_TCP));
+  LWIP_ASSERT("conn must be in state NETCONN_CLOSE", (conn->state == NETCONN_CLOSE));
+  LWIP_ASSERT("pcb already closed", (conn->pcb.tcp != NULL));
+
+  /* Set back some callback pointers */
+  tcp_arg(conn->pcb.tcp, NULL);
+  if (conn->pcb.tcp->state == LISTEN) {
+    tcp_accept(conn->pcb.tcp, NULL);
+  } else {
+    tcp_recv(conn->pcb.tcp, NULL);
+    tcp_accept(conn->pcb.tcp, NULL);
+    /* some callbacks have to be reset if tcp_close is not successful */
+    tcp_sent(conn->pcb.tcp, NULL);
+    tcp_poll(conn->pcb.tcp, NULL, 4);
+    tcp_err(conn->pcb.tcp, NULL);
+  }
+  /* Try to close the connection */
+  err = tcp_close(conn->pcb.tcp);
+  if (err == ERR_OK) {
+    /* Closing succeeded */
+    conn->state = NETCONN_NONE;
+    /* Set back some callback pointers as conn is going away */
+    conn->pcb.tcp = NULL;
+    conn->err = ERR_OK;
+    /* Trigger select() in socket layer. This send should something else so the
+       errorfd is set, not the read and write fd! */
+    API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0);
+    API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0);
+    /* wake up the application task */
+    sys_sem_signal(conn->op_completed);
+  } else {
+    /* Closing failed, restore some of the callbacks */
+    /* Closing of listen pcb will never fail! */
+    LWIP_ASSERT("Closing a listen pcb may not fail!", (conn->pcb.tcp->state != LISTEN));
+    tcp_sent(conn->pcb.tcp, sent_tcp);
+    tcp_poll(conn->pcb.tcp, poll_tcp, 4);
+    tcp_err(conn->pcb.tcp, err_tcp);
+    tcp_arg(conn->pcb.tcp, conn);
+  }
+  /* If closing didn't succeed, we get called again either
+     from poll_tcp or from sent_tcp */
+}
+#endif /* LWIP_TCP */
+
+/**
+ * Delete the pcb inside a netconn.
+ * Called from netconn_delete.
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_delconn(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      raw_remove(msg->conn->pcb.raw);
+      break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+    case NETCONN_UDP:
+      msg->conn->pcb.udp->recv_arg = NULL;
+      udp_remove(msg->conn->pcb.udp);
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+    case NETCONN_TCP:
+      msg->conn->state = NETCONN_CLOSE;
+      do_close_internal(msg->conn);
+      /* API_EVENT is called inside do_close_internal, before releasing
+         the application thread, so we can return at this point! */
+      return;
+#endif /* LWIP_TCP */
+    default:
+      break;
+    }
+  }
+  /* tcp netconns don't come here! */
+
+  /* Trigger select() in socket layer. This send should something else so the
+     errorfd is set, not the read and write fd! */
+  API_EVENT(msg->conn, NETCONN_EVT_RCVPLUS, 0);
+  API_EVENT(msg->conn, NETCONN_EVT_SENDPLUS, 0);
+
+  if (msg->conn->op_completed != SYS_SEM_NULL) {
+    sys_sem_signal(msg->conn->op_completed);
+  }
+}
+
+/**
+ * Bind a pcb contained in a netconn
+ * Called from netconn_bind.
+ *
+ * @param msg the api_msg_msg pointing to the connection and containing
+ *            the IP address and port to bind to
+ */
+void
+do_bind(struct api_msg_msg *msg)
+{
+  if (!ERR_IS_FATAL(msg->conn->err)) {
+    if (msg->conn->pcb.tcp != NULL) {
+      switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+      case NETCONN_RAW:
+        msg->conn->err = raw_bind(msg->conn->pcb.raw, msg->msg.bc.ipaddr);
+        break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+      case NETCONN_UDP:
+        msg->conn->err = udp_bind(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port);
+        break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+      case NETCONN_TCP:
+        msg->conn->err = tcp_bind(msg->conn->pcb.tcp, msg->msg.bc.ipaddr, msg->msg.bc.port);
+        break;
+#endif /* LWIP_TCP */
+      default:
+        break;
+      }
+    } else {
+      /* msg->conn->pcb is NULL */
+      msg->conn->err = ERR_VAL;
+    }
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+
+#if LWIP_TCP
+/**
+ * TCP callback function if a connection (opened by tcp_connect/do_connect) has
+ * been established (or reset by the remote host).
+ *
+ * @see tcp.h (struct tcp_pcb.connected) for parameters and return values
+ */
+static err_t
+do_connected(void *arg, struct tcp_pcb *pcb, err_t err)
+{
+  struct netconn *conn;
+
+  LWIP_UNUSED_ARG(pcb);
+
+  conn = arg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  conn->err = err;
+  if ((conn->type == NETCONN_TCP) && (err == ERR_OK)) {
+    setup_tcp(conn);
+  }
+  conn->state = NETCONN_NONE;
+  sys_sem_signal(conn->op_completed);
+  return ERR_OK;
+}
+#endif /* LWIP_TCP */
+
+/**
+ * Connect a pcb contained inside a netconn
+ * Called from netconn_connect.
+ *
+ * @param msg the api_msg_msg pointing to the connection and containing
+ *            the IP address and port to connect to
+ */
+void
+do_connect(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp == NULL) {
+    sys_sem_signal(msg->conn->op_completed);
+    return;
+  }
+
+  switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+  case NETCONN_RAW:
+    msg->conn->err = raw_connect(msg->conn->pcb.raw, msg->msg.bc.ipaddr);
+    sys_sem_signal(msg->conn->op_completed);
+    break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+  case NETCONN_UDP:
+    msg->conn->err = udp_connect(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port);
+    sys_sem_signal(msg->conn->op_completed);
+    break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+  case NETCONN_TCP:
+    msg->conn->state = NETCONN_CONNECT;
+    setup_tcp(msg->conn);
+    msg->conn->err = tcp_connect(msg->conn->pcb.tcp, msg->msg.bc.ipaddr, msg->msg.bc.port,
+                                 do_connected);
+    /* sys_sem_signal() is called from do_connected (or err_tcp()),
+     * when the connection is established! */
+    break;
+#endif /* LWIP_TCP */
+  default:
+    LWIP_ERROR("Invalid netconn type", 0, do{ msg->conn->err = ERR_VAL;
+      sys_sem_signal(msg->conn->op_completed); }while(0));
+    break;
+  }
+}
+
+/**
+ * Connect a pcb contained inside a netconn
+ * Only used for UDP netconns.
+ * Called from netconn_disconnect.
+ *
+ * @param msg the api_msg_msg pointing to the connection to disconnect
+ */
+void
+do_disconnect(struct api_msg_msg *msg)
+{
+#if LWIP_UDP
+  if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_UDP) {
+    udp_disconnect(msg->conn->pcb.udp);
+  }
+#endif /* LWIP_UDP */
+  TCPIP_APIMSG_ACK(msg);
+}
+
+/**
+ * Set a TCP pcb contained in a netconn into listen mode
+ * Called from netconn_listen.
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_listen(struct api_msg_msg *msg)
+{
+#if LWIP_TCP
+  if (!ERR_IS_FATAL(msg->conn->err)) {
+    if (msg->conn->pcb.tcp != NULL) {
+      if (msg->conn->type == NETCONN_TCP) {
+        if (msg->conn->pcb.tcp->state == CLOSED) {
+#if TCP_LISTEN_BACKLOG
+          struct tcp_pcb* lpcb = tcp_listen_with_backlog(msg->conn->pcb.tcp, msg->msg.lb.backlog);
+#else  /* TCP_LISTEN_BACKLOG */
+          struct tcp_pcb* lpcb = tcp_listen(msg->conn->pcb.tcp);
+#endif /* TCP_LISTEN_BACKLOG */
+          if (lpcb == NULL) {
+            msg->conn->err = ERR_MEM;
+          } else {
+            /* delete the recvmbox and allocate the acceptmbox */
+            if (msg->conn->recvmbox != SYS_MBOX_NULL) {
+              /** @todo: should we drain the recvmbox here? */
+              sys_mbox_free(msg->conn->recvmbox);
+              msg->conn->recvmbox = SYS_MBOX_NULL;
+            }
+            if (msg->conn->acceptmbox == SYS_MBOX_NULL) {
+              if ((msg->conn->acceptmbox = sys_mbox_new(DEFAULT_ACCEPTMBOX_SIZE)) == SYS_MBOX_NULL) {
+                msg->conn->err = ERR_MEM;
+              }
+            }
+            if (msg->conn->err == ERR_OK) {
+              msg->conn->state = NETCONN_LISTEN;
+              msg->conn->pcb.tcp = lpcb;
+              tcp_arg(msg->conn->pcb.tcp, msg->conn);
+              tcp_accept(msg->conn->pcb.tcp, accept_function);
+            }
+          }
+        } else {
+          msg->conn->err = ERR_CONN;
+        }
+      }
+    }
+  }
+#endif /* LWIP_TCP */
+  TCPIP_APIMSG_ACK(msg);
+}
+
+/**
+ * Send some data on a RAW or UDP pcb contained in a netconn
+ * Called from netconn_send
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_send(struct api_msg_msg *msg)
+{
+  if (!ERR_IS_FATAL(msg->conn->err)) {
+    if (msg->conn->pcb.tcp != NULL) {
+      switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+      case NETCONN_RAW:
+        if (msg->msg.b->addr == NULL) {
+          msg->conn->err = raw_send(msg->conn->pcb.raw, msg->msg.b->p);
+        } else {
+          msg->conn->err = raw_sendto(msg->conn->pcb.raw, msg->msg.b->p, msg->msg.b->addr);
+        }
+        break;
+#endif
+#if LWIP_UDP
+      case NETCONN_UDP:
+        if (msg->msg.b->addr == NULL) {
+          msg->conn->err = udp_send(msg->conn->pcb.udp, msg->msg.b->p);
+        } else {
+          msg->conn->err = udp_sendto(msg->conn->pcb.udp, msg->msg.b->p, msg->msg.b->addr, msg->msg.b->port);
+        }
+        break;
+#endif /* LWIP_UDP */
+      default:
+        break;
+      }
+    }
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+
+/**
+ * Indicate data has been received from a TCP pcb contained in a netconn
+ * Called from netconn_recv
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_recv(struct api_msg_msg *msg)
+{
+#if LWIP_TCP
+  if (!ERR_IS_FATAL(msg->conn->err)) {
+    if (msg->conn->pcb.tcp != NULL) {
+      if (msg->conn->type == NETCONN_TCP) {
+#if TCP_LISTEN_BACKLOG
+        if (msg->conn->pcb.tcp->state == LISTEN) {
+          tcp_accepted(msg->conn->pcb.tcp);
+        } else
+#endif /* TCP_LISTEN_BACKLOG */
+        {
+          tcp_recved(msg->conn->pcb.tcp, msg->msg.r.len);
+        }
+      }
+    }
+  }
+#endif /* LWIP_TCP */
+  TCPIP_APIMSG_ACK(msg);
+}
+
+#if LWIP_TCP
+/**
+ * See if more data needs to be written from a previous call to netconn_write.
+ * Called initially from do_write. If the first call can't send all data
+ * (because of low memory or empty send-buffer), this function is called again
+ * from sent_tcp() or poll_tcp() to send more data. If all data is sent, the
+ * blocking application thread (waiting in netconn_write) is released.
+ *
+ * @param conn netconn (that is currently in state NETCONN_WRITE) to process
+ * @return ERR_OK
+ *         ERR_MEM if LWIP_TCPIP_CORE_LOCKING=1 and sending hasn't yet finished
+ */
+static err_t
+do_writemore(struct netconn *conn)
+{
+  err_t err;
+  void *dataptr;
+  u16_t len, available;
+  u8_t write_finished = 0;
+  size_t diff;
+
+  LWIP_ASSERT("conn->state == NETCONN_WRITE", (conn->state == NETCONN_WRITE));
+
+  dataptr = (u8_t*)conn->write_msg->msg.w.dataptr + conn->write_offset;
+  diff = conn->write_msg->msg.w.len - conn->write_offset;
+  if (diff > 0xffffUL) { /* max_u16_t */
+    len = 0xffff;
+#if LWIP_TCPIP_CORE_LOCKING
+    conn->write_delayed = 1;
+#endif
+  } else {
+    len = (u16_t)diff;
+  }
+  available = tcp_sndbuf(conn->pcb.tcp);
+  if (available < len) {
+    /* don't try to write more than sendbuf */
+    len = available;
+#if LWIP_TCPIP_CORE_LOCKING
+    conn->write_delayed = 1;
+#endif
+  }
+
+  err = tcp_write(conn->pcb.tcp, dataptr, len, conn->write_msg->msg.w.apiflags);
+  LWIP_ASSERT("do_writemore: invalid length!", ((conn->write_offset + len) <= conn->write_msg->msg.w.len));
+  if (err == ERR_OK) {
+    conn->write_offset += len;
+    if (conn->write_offset == conn->write_msg->msg.w.len) {
+      /* everything was written */
+      write_finished = 1;
+      conn->write_msg = NULL;
+      conn->write_offset = 0;
+      /* API_EVENT might call tcp_tmr, so reset conn->state now */
+      conn->state = NETCONN_NONE;
+    }
+    err = tcp_output_nagle(conn->pcb.tcp);
+    conn->err = err;
+    if ((err == ERR_OK) && (tcp_sndbuf(conn->pcb.tcp) <= TCP_SNDLOWAT)) {
+      API_EVENT(conn, NETCONN_EVT_SENDMINUS, len);
+    }
+  } else if (err == ERR_MEM) {
+    /* If ERR_MEM, we wait for sent_tcp or poll_tcp to be called
+       we do NOT return to the application thread, since ERR_MEM is
+       only a temporary error! */
+
+    /* tcp_enqueue returned ERR_MEM, try tcp_output anyway */
+    err = tcp_output(conn->pcb.tcp);
+
+#if LWIP_TCPIP_CORE_LOCKING
+    conn->write_delayed = 1;
+#endif
+  } else {
+    /* On errors != ERR_MEM, we don't try writing any more but return
+       the error to the application thread. */
+    conn->err = err;
+    write_finished = 1;
+  }
+
+  if (write_finished) {
+    /* everything was written: set back connection state
+       and back to application task */
+    conn->state = NETCONN_NONE;
+#if LWIP_TCPIP_CORE_LOCKING
+    if (conn->write_delayed != 0)
+#endif
+    {
+      sys_sem_signal(conn->op_completed);
+    }
+  }
+#if LWIP_TCPIP_CORE_LOCKING
+  else
+    return ERR_MEM;
+#endif
+  return ERR_OK;
+}
+#endif /* LWIP_TCP */
+
+/**
+ * Send some data on a TCP pcb contained in a netconn
+ * Called from netconn_write
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_write(struct api_msg_msg *msg)
+{
+  if (!ERR_IS_FATAL(msg->conn->err)) {
+    if ((msg->conn->pcb.tcp != NULL) && (msg->conn->type == NETCONN_TCP)) {
+#if LWIP_TCP
+      msg->conn->state = NETCONN_WRITE;
+      /* set all the variables used by do_writemore */
+      LWIP_ASSERT("already writing", msg->conn->write_msg == NULL &&
+        msg->conn->write_offset == 0);
+      msg->conn->write_msg = msg;
+      msg->conn->write_offset = 0;
+#if LWIP_TCPIP_CORE_LOCKING
+      msg->conn->write_delayed = 0;
+      if (do_writemore(msg->conn) != ERR_OK) {
+        LWIP_ASSERT("state!", msg->conn->state == NETCONN_WRITE);
+        UNLOCK_TCPIP_CORE();
+        sys_arch_sem_wait(msg->conn->op_completed, 0);
+        LOCK_TCPIP_CORE();
+        LWIP_ASSERT("state!", msg->conn->state == NETCONN_NONE);
+      }
+#else
+      do_writemore(msg->conn);
+#endif
+      /* for both cases: if do_writemore was called, don't ACK the APIMSG! */
+      return;
+#endif /* LWIP_TCP */
+#if (LWIP_UDP || LWIP_RAW)
+    } else {
+      msg->conn->err = ERR_VAL;
+#endif /* (LWIP_UDP || LWIP_RAW) */
+    }
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+
+/**
+ * Return a connection's local or remote address
+ * Called from netconn_getaddr
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_getaddr(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.ip != NULL) {
+    *(msg->msg.ad.ipaddr) = (msg->msg.ad.local?msg->conn->pcb.ip->local_ip:msg->conn->pcb.ip->remote_ip);
+    
+    switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      if (msg->msg.ad.local) {
+        *(msg->msg.ad.port) = msg->conn->pcb.raw->protocol;
+      } else {
+        /* return an error as connecting is only a helper for upper layers */
+        msg->conn->err = ERR_CONN;
+      }
+      break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+    case NETCONN_UDP:
+      if (msg->msg.ad.local) {
+        *(msg->msg.ad.port) = msg->conn->pcb.udp->local_port;
+      } else {
+        if ((msg->conn->pcb.udp->flags & UDP_FLAGS_CONNECTED) == 0) {
+          msg->conn->err = ERR_CONN;
+        } else {
+          *(msg->msg.ad.port) = msg->conn->pcb.udp->remote_port;
+        }
+      }
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+    case NETCONN_TCP:
+      *(msg->msg.ad.port) = (msg->msg.ad.local?msg->conn->pcb.tcp->local_port:msg->conn->pcb.tcp->remote_port);
+      break;
+#endif /* LWIP_TCP */
+    }
+  } else {
+    msg->conn->err = ERR_CONN;
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+
+/**
+ * Close a TCP pcb contained in a netconn
+ * Called from netconn_close
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_close(struct api_msg_msg *msg)
+{
+#if LWIP_TCP
+  if ((msg->conn->pcb.tcp != NULL) && (msg->conn->type == NETCONN_TCP)) {
+      msg->conn->state = NETCONN_CLOSE;
+      do_close_internal(msg->conn);
+      /* for tcp netconns, do_close_internal ACKs the message */
+  } else
+#endif /* LWIP_TCP */
+  {
+    msg->conn->err = ERR_VAL;
+    sys_sem_signal(msg->conn->op_completed);
+  }
+}
+
+#if LWIP_IGMP
+/**
+ * Join multicast groups for UDP netconns.
+ * Called from netconn_join_leave_group
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_join_leave_group(struct api_msg_msg *msg)
+{ 
+  if (!ERR_IS_FATAL(msg->conn->err)) {
+    if (msg->conn->pcb.tcp != NULL) {
+      if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_UDP) {
+#if LWIP_UDP
+        if (msg->msg.jl.join_or_leave == NETCONN_JOIN) {
+          msg->conn->err = igmp_joingroup(msg->msg.jl.interface, msg->msg.jl.multiaddr);
+        } else {
+          msg->conn->err = igmp_leavegroup(msg->msg.jl.interface, msg->msg.jl.multiaddr);
+        }
+#endif /* LWIP_UDP */
+#if (LWIP_TCP || LWIP_RAW)
+      } else {
+        msg->conn->err = ERR_VAL;
+#endif /* (LWIP_TCP || LWIP_RAW) */
+      }
+    }
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+#endif /* LWIP_IGMP */
+
+#if LWIP_DNS
+/**
+ * Callback function that is called when DNS name is resolved
+ * (or on timeout). A waiting application thread is waked up by
+ * signaling the semaphore.
+ */
+static void
+do_dns_found(const char *name, struct ip_addr *ipaddr, void *arg)
+{
+  struct dns_api_msg *msg = (struct dns_api_msg*)arg;
+
+  LWIP_ASSERT("DNS response for wrong host name", strcmp(msg->name, name) == 0);
+
+  if (ipaddr == NULL) {
+    /* timeout or memory error */
+    *msg->err = ERR_VAL;
+  } else {
+    /* address was resolved */
+    *msg->err = ERR_OK;
+    *msg->addr = *ipaddr;
+  }
+  /* wake up the application task waiting in netconn_gethostbyname */
+  sys_sem_signal(msg->sem);
+}
+
+/**
+ * Execute a DNS query
+ * Called from netconn_gethostbyname
+ *
+ * @param arg the dns_api_msg pointing to the query
+ */
+void
+do_gethostbyname(void *arg)
+{
+  struct dns_api_msg *msg = (struct dns_api_msg*)arg;
+
+  *msg->err = dns_gethostbyname(msg->name, msg->addr, do_dns_found, msg);
+  if (*msg->err != ERR_INPROGRESS) {
+    /* on error or immediate success, wake up the application
+     * task waiting in netconn_gethostbyname */
+    sys_sem_signal(msg->sem);
+  }
+}
+#endif /* LWIP_DNS */
+
+#endif /* LWIP_NETCONN */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/err.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/err.c
new file mode 100644
index 0000000..a90cb98
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/err.c
@@ -0,0 +1,74 @@
+/**
+ * @file
+ * Error Management module
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/err.h"
+
+#ifdef LWIP_DEBUG
+
+static const char *err_strerr[] = {
+           "Ok.",                    /* ERR_OK          0  */
+           "Out of memory error.",   /* ERR_MEM        -1  */
+           "Buffer error.",          /* ERR_BUF        -2  */
+           "Timeout.",               /* ERR_TIMEOUT    -3 */
+           "Routing problem.",       /* ERR_RTE        -4  */
+           "Connection aborted.",    /* ERR_ABRT       -5  */
+           "Connection reset.",      /* ERR_RST        -6  */
+           "Connection closed.",     /* ERR_CLSD       -7  */
+           "Not connected.",         /* ERR_CONN       -8  */
+           "Illegal value.",         /* ERR_VAL        -9  */
+           "Illegal argument.",      /* ERR_ARG        -10 */
+           "Address in use.",        /* ERR_USE        -11 */
+           "Low-level netif error.", /* ERR_IF         -12 */
+           "Already connected.",     /* ERR_ISCONN     -13 */
+           "Operation in progress."  /* ERR_INPROGRESS -14 */
+};
+
+/**
+ * Convert an lwip internal error to a string representation.
+ *
+ * @param err an lwip internal err_t
+ * @return a string representation for err
+ */
+const char *
+lwip_strerr(err_t err)
+{
+  return err_strerr[-err];
+
+}
+
+#endif /* LWIP_DEBUG */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/netbuf.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/netbuf.c
new file mode 100644
index 0000000..57efc4f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/netbuf.c
@@ -0,0 +1,240 @@
+/**
+ * @file
+ * Network buffer management
+ *
+ */
+ 
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netbuf.h"
+#include "lwip/memp.h"
+
+#include 
+
+/**
+ * Create (allocate) and initialize a new netbuf.
+ * The netbuf doesn't yet contain a packet buffer!
+ *
+ * @return a pointer to a new netbuf
+ *         NULL on lack of memory
+ */
+struct
+netbuf *netbuf_new(void)
+{
+  struct netbuf *buf;
+
+  buf = memp_malloc(MEMP_NETBUF);
+  if (buf != NULL) {
+    buf->p = NULL;
+    buf->ptr = NULL;
+    buf->addr = NULL;
+    buf->port = 0;
+#if LWIP_NETBUF_RECVINFO
+    buf->toaddr = NULL;
+    buf->toport = 0;
+#endif /* LWIP_NETBUF_RECVINFO */
+    return buf;
+  } else {
+    return NULL;
+  }
+}
+
+/**
+ * Deallocate a netbuf allocated by netbuf_new().
+ *
+ * @param buf pointer to a netbuf allocated by netbuf_new()
+ */
+void
+netbuf_delete(struct netbuf *buf)
+{
+  if (buf != NULL) {
+    if (buf->p != NULL) {
+      pbuf_free(buf->p);
+      buf->p = buf->ptr = NULL;
+    }
+    memp_free(MEMP_NETBUF, buf);
+  }
+}
+
+/**
+ * Allocate memory for a packet buffer for a given netbuf.
+ *
+ * @param buf the netbuf for which to allocate a packet buffer
+ * @param size the size of the packet buffer to allocate
+ * @return pointer to the allocated memory
+ *         NULL if no memory could be allocated
+ */
+void *
+netbuf_alloc(struct netbuf *buf, u16_t size)
+{
+  LWIP_ERROR("netbuf_alloc: invalid buf", (buf != NULL), return NULL;);
+
+  /* Deallocate any previously allocated memory. */
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = pbuf_alloc(PBUF_TRANSPORT, size, PBUF_RAM);
+  if (buf->p == NULL) {
+     return NULL;
+  }
+  LWIP_ASSERT("check that first pbuf can hold size",
+             (buf->p->len >= size));
+  buf->ptr = buf->p;
+  return buf->p->payload;
+}
+
+/**
+ * Free the packet buffer included in a netbuf
+ *
+ * @param buf pointer to the netbuf which contains the packet buffer to free
+ */
+void
+netbuf_free(struct netbuf *buf)
+{
+  LWIP_ERROR("netbuf_free: invalid buf", (buf != NULL), return;);
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = buf->ptr = NULL;
+}
+
+/**
+ * Let a netbuf reference existing (non-volatile) data.
+ *
+ * @param buf netbuf which should reference the data
+ * @param dataptr pointer to the data to reference
+ * @param size size of the data
+ * @return ERR_OK if data is referenced
+ *         ERR_MEM if data couldn't be referenced due to lack of memory
+ */
+err_t
+netbuf_ref(struct netbuf *buf, const void *dataptr, u16_t size)
+{
+  LWIP_ERROR("netbuf_ref: invalid buf", (buf != NULL), return ERR_ARG;);
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF);
+  if (buf->p == NULL) {
+    buf->ptr = NULL;
+    return ERR_MEM;
+  }
+  buf->p->payload = (void*)dataptr;
+  buf->p->len = buf->p->tot_len = size;
+  buf->ptr = buf->p;
+  return ERR_OK;
+}
+
+/**
+ * Chain one netbuf to another (@see pbuf_chain)
+ *
+ * @param head the first netbuf
+ * @param tail netbuf to chain after head, freed by this function, may not be reference after returning
+ */
+void
+netbuf_chain(struct netbuf *head, struct netbuf *tail)
+{
+  LWIP_ERROR("netbuf_ref: invalid head", (head != NULL), return;);
+  LWIP_ERROR("netbuf_chain: invalid tail", (tail != NULL), return;);
+  pbuf_cat(head->p, tail->p);
+  head->ptr = head->p;
+  memp_free(MEMP_NETBUF, tail);
+}
+
+/**
+ * Get the data pointer and length of the data inside a netbuf.
+ *
+ * @param buf netbuf to get the data from
+ * @param dataptr pointer to a void pointer where to store the data pointer
+ * @param len pointer to an u16_t where the length of the data is stored
+ * @return ERR_OK if the information was retreived,
+ *         ERR_BUF on error.
+ */
+err_t
+netbuf_data(struct netbuf *buf, void **dataptr, u16_t *len)
+{
+  LWIP_ERROR("netbuf_data: invalid buf", (buf != NULL), return ERR_ARG;);
+  LWIP_ERROR("netbuf_data: invalid dataptr", (dataptr != NULL), return ERR_ARG;);
+  LWIP_ERROR("netbuf_data: invalid len", (len != NULL), return ERR_ARG;);
+
+  if (buf->ptr == NULL) {
+    return ERR_BUF;
+  }
+  *dataptr = buf->ptr->payload;
+  *len = buf->ptr->len;
+  return ERR_OK;
+}
+
+/**
+ * Move the current data pointer of a packet buffer contained in a netbuf
+ * to the next part.
+ * The packet buffer itself is not modified.
+ *
+ * @param buf the netbuf to modify
+ * @return -1 if there is no next part
+ *         1  if moved to the next part but now there is no next part
+ *         0  if moved to the next part and there are still more parts
+ */
+s8_t
+netbuf_next(struct netbuf *buf)
+{
+  LWIP_ERROR("netbuf_free: invalid buf", (buf != NULL), return -1;);
+  if (buf->ptr->next == NULL) {
+    return -1;
+  }
+  buf->ptr = buf->ptr->next;
+  if (buf->ptr->next == NULL) {
+    return 1;
+  }
+  return 0;
+}
+
+/**
+ * Move the current data pointer of a packet buffer contained in a netbuf
+ * to the beginning of the packet.
+ * The packet buffer itself is not modified.
+ *
+ * @param buf the netbuf to modify
+ */
+void
+netbuf_first(struct netbuf *buf)
+{
+  LWIP_ERROR("netbuf_free: invalid buf", (buf != NULL), return;);
+  buf->ptr = buf->p;
+}
+
+#endif /* LWIP_NETCONN */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/netdb.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/netdb.c
new file mode 100644
index 0000000..69a331b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/netdb.c
@@ -0,0 +1,346 @@
+/**
+ * @file
+ * API functions for name resolving
+ *
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Simon Goldschmidt
+ *
+ */
+
+#include "lwip/netdb.h"
+
+#if LWIP_DNS && LWIP_SOCKET
+
+#include "lwip/err.h"
+#include "lwip/mem.h"
+#include "lwip/ip_addr.h"
+#include "lwip/api.h"
+
+#include 
+#include 
+
+/** helper struct for gethostbyname_r to access the char* buffer */
+struct gethostbyname_r_helper {
+  struct ip_addr *addrs;
+  struct ip_addr addr;
+  char *aliases;
+};
+
+/** h_errno is exported in netdb.h for access by applications. */
+#if LWIP_DNS_API_DECLARE_H_ERRNO
+int h_errno;
+#endif /* LWIP_DNS_API_DECLARE_H_ERRNO */
+
+/** define "hostent" variables storage: 0 if we use a static (but unprotected)
+ * set of variables for lwip_gethostbyname, 1 if we use a local storage */
+#ifndef LWIP_DNS_API_HOSTENT_STORAGE
+#define LWIP_DNS_API_HOSTENT_STORAGE 0
+#endif
+
+/** define "hostent" variables storage */
+#if LWIP_DNS_API_HOSTENT_STORAGE
+#define HOSTENT_STORAGE
+#else
+#define HOSTENT_STORAGE static
+#endif /* LWIP_DNS_API_STATIC_HOSTENT */
+
+/**
+ * Returns an entry containing addresses of address family AF_INET
+ * for the host with name name.
+ * Due to dns_gethostbyname limitations, only one address is returned.
+ *
+ * @param name the hostname to resolve
+ * @return an entry containing addresses of address family AF_INET
+ *         for the host with name name
+ */
+struct hostent*
+lwip_gethostbyname(const char *name)
+{
+  err_t err;
+  struct ip_addr addr;
+
+  /* buffer variables for lwip_gethostbyname() */
+  HOSTENT_STORAGE struct hostent s_hostent;
+  HOSTENT_STORAGE char *s_aliases;
+  HOSTENT_STORAGE struct ip_addr s_hostent_addr;
+  HOSTENT_STORAGE struct ip_addr *s_phostent_addr;
+
+  /* query host IP address */
+  err = netconn_gethostbyname(name, &addr);
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(DNS_DEBUG, ("lwip_gethostbyname(%s) failed, err=%d\n", name, err));
+    h_errno = HOST_NOT_FOUND;
+    return NULL;
+  }
+
+  /* fill hostent */
+  s_hostent_addr = addr;
+  s_phostent_addr = &s_hostent_addr;
+  s_hostent.h_name = (char*)name;
+  s_hostent.h_aliases = &s_aliases;
+  s_hostent.h_addrtype = AF_INET;
+  s_hostent.h_length = sizeof(struct ip_addr);
+  s_hostent.h_addr_list = (char**)&s_phostent_addr;
+
+#if DNS_DEBUG
+  /* dump hostent */
+  LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_name           == %s\n", s_hostent.h_name));
+  LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_aliases        == %p\n", s_hostent.h_aliases));
+  if (s_hostent.h_aliases != NULL) {
+    u8_t idx;
+    for ( idx=0; s_hostent.h_aliases[idx]; idx++) {
+      LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_aliases[%i]->   == %p\n", idx, s_hostent.h_aliases[idx]));
+      LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_aliases[%i]->   == %s\n", idx, s_hostent.h_aliases[idx]));
+    }
+  }
+  LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addrtype       == %d\n", s_hostent.h_addrtype));
+  LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_length         == %d\n", s_hostent.h_length));
+  LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addr_list      == %p\n", s_hostent.h_addr_list));
+  if (s_hostent.h_addr_list != NULL) {
+    u8_t idx;
+    for ( idx=0; s_hostent.h_addr_list[idx]; idx++) {
+      LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addr_list[%i]   == %p\n", idx, s_hostent.h_addr_list[idx]));
+      LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addr_list[%i]-> == %s\n", idx, ip_ntoa(s_hostent.h_addr_list[idx])));
+    }
+  }
+#endif /* DNS_DEBUG */
+
+#if LWIP_DNS_API_HOSTENT_STORAGE
+  /* this function should return the "per-thread" hostent after copy from s_hostent */
+  return sys_thread_hostent(&s_hostent);
+#else
+  return &s_hostent;
+#endif /* LWIP_DNS_API_HOSTENT_STORAGE */
+}
+
+/**
+ * Thread-safe variant of lwip_gethostbyname: instead of using a static
+ * buffer, this function takes buffer and errno pointers as arguments
+ * and uses these for the result.
+ *
+ * @param name the hostname to resolve
+ * @param ret pre-allocated struct where to store the result
+ * @param buf pre-allocated buffer where to store additional data
+ * @param buflen the size of buf
+ * @param result pointer to a hostent pointer that is set to ret on success
+ *               and set to zero on error
+ * @param h_errnop pointer to an int where to store errors (instead of modifying
+ *                 the global h_errno)
+ * @return 0 on success, non-zero on error, additional error information
+ *         is stored in *h_errnop instead of h_errno to be thread-safe
+ */
+int
+lwip_gethostbyname_r(const char *name, struct hostent *ret, char *buf,
+                size_t buflen, struct hostent **result, int *h_errnop)
+{
+  err_t err;
+  struct gethostbyname_r_helper *h;
+  char *hostname;
+  size_t namelen;
+  int lh_errno;
+
+  if (h_errnop == NULL) {
+    /* ensure h_errnop is never NULL */
+    h_errnop = &lh_errno;
+  }
+
+  if (result == NULL) {
+    /* not all arguments given */
+    *h_errnop = EINVAL;
+    return -1;
+  }
+  /* first thing to do: set *result to nothing */
+  *result = NULL;
+  if ((name == NULL) || (ret == NULL) || (buf == 0)) {
+    /* not all arguments given */
+    *h_errnop = EINVAL;
+    return -1;
+  }
+
+  namelen = strlen(name);
+  if (buflen < (sizeof(struct gethostbyname_r_helper) + namelen + 1 + (MEM_ALIGNMENT - 1))) {
+    /* buf can't hold the data needed + a copy of name */
+    *h_errnop = ERANGE;
+    return -1;
+  }
+
+  h = (struct gethostbyname_r_helper*)LWIP_MEM_ALIGN(buf);
+  hostname = ((char*)h) + sizeof(struct gethostbyname_r_helper);
+
+  /* query host IP address */
+  err = netconn_gethostbyname(name, &(h->addr));
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(DNS_DEBUG, ("lwip_gethostbyname(%s) failed, err=%d\n", name, err));
+    *h_errnop = ENSRNOTFOUND;
+    return -1;
+  }
+
+  /* copy the hostname into buf */
+  MEMCPY(hostname, name, namelen);
+  hostname[namelen] = 0;
+
+  /* fill hostent */
+  h->addrs = &(h->addr);
+  h->aliases = NULL;
+  ret->h_name = (char*)hostname;
+  ret->h_aliases = &(h->aliases);
+  ret->h_addrtype = AF_INET;
+  ret->h_length = sizeof(struct ip_addr);
+  ret->h_addr_list = (char**)&(h->addrs);
+
+  /* set result != NULL */
+  *result = ret;
+
+  /* return success */
+  return 0;
+}
+
+/**
+ * Frees one or more addrinfo structures returned by getaddrinfo(), along with
+ * any additional storage associated with those structures. If the ai_next field
+ * of the structure is not null, the entire list of structures is freed.
+ *
+ * @param ai struct addrinfo to free
+ */
+void
+lwip_freeaddrinfo(struct addrinfo *ai)
+{
+  struct addrinfo *next;
+
+  while (ai != NULL) {
+    next = ai->ai_next;
+    mem_free(ai);
+    ai = next;
+  }
+}
+
+/**
+ * Translates the name of a service location (for example, a host name) and/or
+ * a service name and returns a set of socket addresses and associated
+ * information to be used in creating a socket with which to address the
+ * specified service.
+ * Memory for the result is allocated internally and must be freed by calling
+ * lwip_freeaddrinfo()!
+ *
+ * Due to a limitation in dns_gethostbyname, only the first address of a
+ * host is returned.
+ * Also, service names are not supported (only port numbers)!
+ *
+ * @param nodename descriptive name or address string of the host
+ *                 (may be NULL -> local address)
+ * @param servname port number as string of NULL 
+ * @param hints structure containing input values that set socktype and protocol
+ * @param res pointer to a pointer where to store the result (set to NULL on failure)
+ * @return 0 on success, non-zero on failure
+ */
+int
+lwip_getaddrinfo(const char *nodename, const char *servname,
+       const struct addrinfo *hints, struct addrinfo **res)
+{
+  err_t err;
+  struct ip_addr addr;
+  struct addrinfo *ai;
+  struct sockaddr_in *sa = NULL;
+  int port_nr = 0;
+  size_t total_size;
+  size_t namelen = 0;
+
+  if (res == NULL) {
+    return EAI_FAIL;
+  }
+  *res = NULL;
+  if ((nodename == NULL) && (servname == NULL)) {
+    return EAI_NONAME;
+  }
+
+  if (servname != NULL) {
+    /* service name specified: convert to port number
+     * @todo?: currently, only ASCII integers (port numbers) are supported! */
+    port_nr = atoi(servname);
+    if ((port_nr <= 0) || (port_nr > 0xffff)) {
+      return EAI_SERVICE;
+    }
+  }
+
+  if (nodename != NULL) {
+    /* service location specified, try to resolve */
+    err = netconn_gethostbyname(nodename, &addr);
+    if (err != ERR_OK) {
+      return EAI_FAIL;
+    }
+  } else {
+    /* service location specified, use loopback address */
+    addr.addr = htonl(INADDR_LOOPBACK);
+  }
+
+  total_size = sizeof(struct addrinfo) + sizeof(struct sockaddr_in);
+  if (nodename != NULL) {
+    namelen = strlen(nodename);
+    LWIP_ASSERT("namelen is too long", (namelen + 1) <= (mem_size_t)-1);
+    total_size += namelen + 1;
+  }
+  ai = mem_malloc(total_size);
+  if (ai == NULL) {
+    goto memerr;
+  }
+  memset(ai, 0, total_size);
+  sa = (struct sockaddr_in*)((u8_t*)ai + sizeof(struct addrinfo));
+  /* set up sockaddr */
+  sa->sin_addr.s_addr = addr.addr;
+  sa->sin_family = AF_INET;
+  sa->sin_len = sizeof(struct sockaddr_in);
+  sa->sin_port = htons(port_nr);
+
+  /* set up addrinfo */
+  ai->ai_family = AF_INET;
+  if (hints != NULL) {
+    /* copy socktype & protocol from hints if specified */
+    ai->ai_socktype = hints->ai_socktype;
+    ai->ai_protocol = hints->ai_protocol;
+  }
+  if (nodename != NULL) {
+    /* copy nodename to canonname if specified */
+    ai->ai_canonname = ((char*)ai + sizeof(struct addrinfo) + sizeof(struct sockaddr_in));
+    MEMCPY(ai->ai_canonname, nodename, namelen);
+    ai->ai_canonname[namelen] = 0;
+  }
+  ai->ai_addrlen = sizeof(struct sockaddr_in);
+  ai->ai_addr = (struct sockaddr*)sa;
+
+  *res = ai;
+
+  return 0;
+memerr:
+  if (ai != NULL) {
+    mem_free(ai);
+  }
+  return EAI_MEMORY;
+}
+
+#endif /* LWIP_DNS && LWIP_SOCKET */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/netifapi.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/netifapi.c
new file mode 100644
index 0000000..5708986
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/netifapi.c
@@ -0,0 +1,162 @@
+/**
+ * @file
+ * Network Interface Sequential API module
+ *
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netifapi.h"
+#include "lwip/tcpip.h"
+
+/**
+ * Call netif_add() inside the tcpip_thread context.
+ */
+void
+do_netifapi_netif_add( struct netifapi_msg_msg *msg)
+{
+  if (!netif_add( msg->netif,
+                  msg->msg.add.ipaddr,
+                  msg->msg.add.netmask,
+                  msg->msg.add.gw,
+                  msg->msg.add.state,
+                  msg->msg.add.init,
+                  msg->msg.add.input)) {
+    msg->err = ERR_IF;
+  } else {
+    msg->err = ERR_OK;
+  }
+  TCPIP_NETIFAPI_ACK(msg);
+}
+
+/**
+ * Call netif_set_addr() inside the tcpip_thread context.
+ */
+void
+do_netifapi_netif_set_addr( struct netifapi_msg_msg *msg)
+{
+  netif_set_addr( msg->netif,
+                  msg->msg.add.ipaddr,
+                  msg->msg.add.netmask,
+                  msg->msg.add.gw);
+  msg->err = ERR_OK;
+  TCPIP_NETIFAPI_ACK(msg);
+}
+
+/**
+ * Call the "errtfunc" (or the "voidfunc" if "errtfunc" is NULL) inside the
+ * tcpip_thread context.
+ */
+void
+do_netifapi_netif_common( struct netifapi_msg_msg *msg)
+{
+  if (msg->msg.common.errtfunc!=NULL) {
+    msg->err =
+    msg->msg.common.errtfunc(msg->netif);
+  } else {
+    msg->err = ERR_OK;
+    msg->msg.common.voidfunc(msg->netif);
+  }
+  TCPIP_NETIFAPI_ACK(msg);
+}
+
+/**
+ * Call netif_add() in a thread-safe way by running that function inside the
+ * tcpip_thread context.
+ *
+ * @note for params @see netif_add()
+ */
+err_t
+netifapi_netif_add(struct netif *netif,
+                   struct ip_addr *ipaddr,
+                   struct ip_addr *netmask,
+                   struct ip_addr *gw,
+                   void *state,
+                   err_t (* init)(struct netif *netif),
+                   err_t (* input)(struct pbuf *p, struct netif *netif))
+{
+  struct netifapi_msg msg;
+  msg.function = do_netifapi_netif_add;
+  msg.msg.netif = netif;
+  msg.msg.msg.add.ipaddr  = ipaddr;
+  msg.msg.msg.add.netmask = netmask;
+  msg.msg.msg.add.gw      = gw;
+  msg.msg.msg.add.state   = state;
+  msg.msg.msg.add.init    = init;
+  msg.msg.msg.add.input   = input;
+  TCPIP_NETIFAPI(&msg);
+  return msg.msg.err;
+}
+
+/**
+ * Call netif_set_addr() in a thread-safe way by running that function inside the
+ * tcpip_thread context.
+ *
+ * @note for params @see netif_set_addr()
+ */
+err_t
+netifapi_netif_set_addr(struct netif *netif,
+                        struct ip_addr *ipaddr,
+                        struct ip_addr *netmask,
+                        struct ip_addr *gw)
+{
+  struct netifapi_msg msg;
+  msg.function = do_netifapi_netif_set_addr;
+  msg.msg.netif = netif;
+  msg.msg.msg.add.ipaddr  = ipaddr;
+  msg.msg.msg.add.netmask = netmask;
+  msg.msg.msg.add.gw      = gw;
+  TCPIP_NETIFAPI(&msg);
+  return msg.msg.err;
+}
+
+/**
+ * call the "errtfunc" (or the "voidfunc" if "errtfunc" is NULL) in a thread-safe
+ * way by running that function inside the tcpip_thread context.
+ *
+ * @note use only for functions where there is only "netif" parameter.
+ */
+err_t
+netifapi_netif_common( struct netif *netif,
+                       void  (* voidfunc)(struct netif *netif),
+                       err_t (* errtfunc)(struct netif *netif) )
+{
+  struct netifapi_msg msg;
+  msg.function = do_netifapi_netif_common;
+  msg.msg.netif = netif;
+  msg.msg.msg.common.voidfunc = voidfunc;
+  msg.msg.msg.common.errtfunc = errtfunc;
+  TCPIP_NETIFAPI(&msg);
+  return msg.msg.err;
+}
+
+#endif /* LWIP_NETIF_API */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/sockets.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/sockets.c
new file mode 100644
index 0000000..340c6dc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/sockets.c
@@ -0,0 +1,1971 @@
+/**
+ * @file
+ * Sockets BSD-Like API module
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ * Improved by Marc Boucher  and David Haas 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/sockets.h"
+#include "lwip/api.h"
+#include "lwip/sys.h"
+#include "lwip/igmp.h"
+#include "lwip/inet.h"
+#include "lwip/tcp.h"
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/tcpip.h"
+
+#include 
+
+#define NUM_SOCKETS MEMP_NUM_NETCONN
+
+/** Contains all internal pointers and states used for a socket */
+struct lwip_socket {
+  /** sockets currently are built on netconns, each socket has one netconn */
+  struct netconn *conn;
+  /** data that was left from the previous read */
+  struct netbuf *lastdata;
+  /** offset in the data that was left from the previous read */
+  u16_t lastoffset;
+  /** number of times data was received, set by event_callback(),
+      tested by the receive and select functions */
+  s16_t rcvevent;
+  /** number of times data was received, set by event_callback(),
+      tested by select */
+  u16_t sendevent;
+  /** socket flags (currently, only used for O_NONBLOCK) */
+  u16_t flags;
+  /** last error that occurred on this socket */
+  int err;
+};
+
+/** Description for a task waiting in select */
+struct lwip_select_cb {
+  /** Pointer to the next waiting task */
+  struct lwip_select_cb *next;
+  /** readset passed to select */
+  fd_set *readset;
+  /** writeset passed to select */
+  fd_set *writeset;
+  /** unimplemented: exceptset passed to select */
+  fd_set *exceptset;
+  /** don't signal the same semaphore twice: set to 1 when signalled */
+  int sem_signalled;
+  /** semaphore to wake up a task waiting for select */
+  sys_sem_t sem;
+};
+
+/** This struct is used to pass data to the set/getsockopt_internal
+ * functions running in tcpip_thread context (only a void* is allowed) */
+struct lwip_setgetsockopt_data {
+  /** socket struct for which to change options */
+  struct lwip_socket *sock;
+  /** socket index for which to change options */
+  int s;
+  /** level of the option to process */
+  int level;
+  /** name of the option to process */
+  int optname;
+  /** set: value to set the option to
+    * get: value of the option is stored here */
+  void *optval;
+  /** size of *optval */
+  socklen_t *optlen;
+  /** if an error occures, it is temporarily stored here */
+  err_t err;
+};
+
+/** The global array of available sockets */
+static struct lwip_socket sockets[NUM_SOCKETS];
+/** The global list of tasks waiting for select */
+static struct lwip_select_cb *select_cb_list;
+
+/** Semaphore protecting the sockets array */
+static sys_sem_t socksem;
+/** Semaphore protecting select_cb_list */
+static sys_sem_t selectsem;
+
+/** Table to quickly map an lwIP error (err_t) to a socket error
+  * by using -err as an index */
+static const int err_to_errno_table[] = {
+  0,             /* ERR_OK          0      No error, everything OK. */
+  ENOMEM,        /* ERR_MEM        -1      Out of memory error.     */
+  ENOBUFS,       /* ERR_BUF        -2      Buffer error.            */
+  ETIMEDOUT,     /* ERR_TIMEOUT    -3      Timeout                  */
+  EHOSTUNREACH,  /* ERR_RTE        -4      Routing problem.         */
+  ECONNABORTED,  /* ERR_ABRT       -5      Connection aborted.      */
+  ECONNRESET,    /* ERR_RST        -6      Connection reset.        */
+  ESHUTDOWN,     /* ERR_CLSD       -7      Connection closed.       */
+  ENOTCONN,      /* ERR_CONN       -8      Not connected.           */
+  EINVAL,        /* ERR_VAL        -9      Illegal value.           */
+  EIO,           /* ERR_ARG        -10     Illegal argument.        */
+  EADDRINUSE,    /* ERR_USE        -11     Address in use.          */
+  -1,            /* ERR_IF         -12     Low-level netif error    */
+  -1,            /* ERR_ISCONN     -13     Already connected.       */
+  EINPROGRESS    /* ERR_INPROGRESS -14     Operation in progress    */
+};
+
+#define ERR_TO_ERRNO_TABLE_SIZE \
+  (sizeof(err_to_errno_table)/sizeof(err_to_errno_table[0]))
+
+#define err_to_errno(err) \
+  ((unsigned)(-(err)) < ERR_TO_ERRNO_TABLE_SIZE ? \
+    err_to_errno_table[-(err)] : EIO)
+
+#ifdef ERRNO
+#ifndef set_errno
+#define set_errno(err) errno = (err)
+#endif
+#else
+#define set_errno(err)
+#endif
+
+#define sock_set_errno(sk, e) do { \
+  sk->err = (e); \
+  set_errno(sk->err); \
+} while (0)
+
+/* Forward delcaration of some functions */
+static void event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len);
+static void lwip_getsockopt_internal(void *arg);
+static void lwip_setsockopt_internal(void *arg);
+
+/**
+ * Initialize this module. This function has to be called before any other
+ * functions in this module!
+ */
+void
+lwip_socket_init(void)
+{
+  socksem   = sys_sem_new(1);
+  selectsem = sys_sem_new(1);
+}
+
+/**
+ * Map a externally used socket index to the internal socket representation.
+ *
+ * @param s externally used socket index
+ * @return struct lwip_socket for the socket or NULL if not found
+ */
+static struct lwip_socket *
+get_socket(int s)
+{
+  struct lwip_socket *sock;
+
+  if ((s < 0) || (s >= NUM_SOCKETS)) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): invalid\n", s));
+    set_errno(EBADF);
+    return NULL;
+  }
+
+  sock = &sockets[s];
+
+  if (!sock->conn) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): not active\n", s));
+    set_errno(EBADF);
+    return NULL;
+  }
+
+  return sock;
+}
+
+/**
+ * Allocate a new socket for a given netconn.
+ *
+ * @param newconn the netconn for which to allocate a socket
+ * @return the index of the new socket; -1 on error
+ */
+static int
+alloc_socket(struct netconn *newconn)
+{
+  int i;
+
+  /* Protect socket array */
+  sys_sem_wait(socksem);
+
+  /* allocate a new socket identifier */
+  for (i = 0; i < NUM_SOCKETS; ++i) {
+    if (!sockets[i].conn) {
+      sockets[i].conn       = newconn;
+      sockets[i].lastdata   = NULL;
+      sockets[i].lastoffset = 0;
+      sockets[i].rcvevent   = 0;
+      sockets[i].sendevent  = 1; /* TCP send buf is empty */
+      sockets[i].flags      = 0;
+      sockets[i].err        = 0;
+      sys_sem_signal(socksem);
+      return i;
+    }
+  }
+  sys_sem_signal(socksem);
+  return -1;
+}
+
+/* Below this, the well-known socket functions are implemented.
+ * Use google.com or opengroup.org to get a good description :-)
+ *
+ * Exceptions are documented!
+ */
+
+int
+lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen)
+{
+  struct lwip_socket *sock, *nsock;
+  struct netconn *newconn;
+  struct ip_addr naddr;
+  u16_t port;
+  int newsock;
+  struct sockaddr_in sin;
+  err_t err;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d)...\n", s));
+  sock = get_socket(s);
+  if (!sock)
+    return -1;
+
+  if ((sock->flags & O_NONBLOCK) && (sock->rcvevent <= 0)) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d): returning EWOULDBLOCK\n", s));
+    sock_set_errno(sock, EWOULDBLOCK);
+    return -1;
+  }
+
+  newconn = netconn_accept(sock->conn);
+  if (!newconn) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) failed, err=%d\n", s, sock->conn->err));
+    sock_set_errno(sock, err_to_errno(sock->conn->err));
+    return -1;
+  }
+
+  /* get the IP address and port of the remote host */
+  err = netconn_peer(newconn, &naddr, &port);
+  if (err != ERR_OK) {
+    netconn_delete(newconn);
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  /* Note that POSIX only requires us to check addr is non-NULL. addrlen must
+   * not be NULL if addr is valid.
+   */
+  if (NULL != addr) {
+    LWIP_ASSERT("addr valid but addrlen NULL", addrlen != NULL);
+    memset(&sin, 0, sizeof(sin));
+    sin.sin_len = sizeof(sin);
+    sin.sin_family = AF_INET;
+    sin.sin_port = htons(port);
+    sin.sin_addr.s_addr = naddr.addr;
+
+    if (*addrlen > sizeof(sin))
+      *addrlen = sizeof(sin);
+
+    MEMCPY(addr, &sin, *addrlen);
+  }
+
+  newsock = alloc_socket(newconn);
+  if (newsock == -1) {
+    netconn_delete(newconn);
+    sock_set_errno(sock, ENFILE);
+    return -1;
+  }
+  LWIP_ASSERT("invalid socket index", (newsock >= 0) && (newsock < NUM_SOCKETS));
+  newconn->callback = event_callback;
+  nsock = &sockets[newsock];
+  LWIP_ASSERT("invalid socket pointer", nsock != NULL);
+
+  sys_sem_wait(socksem);
+  /* See event_callback: If data comes in right away after an accept, even
+   * though the server task might not have created a new socket yet.
+   * In that case, newconn->socket is counted down (newconn->socket--),
+   * so nsock->rcvevent is >= 1 here!
+   */
+  nsock->rcvevent += -1 - newconn->socket;
+  newconn->socket = newsock;
+  sys_sem_signal(socksem);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d addr=", s, newsock));
+  ip_addr_debug_print(SOCKETS_DEBUG, &naddr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F"\n", port));
+
+  sock_set_errno(sock, 0);
+  return newsock;
+}
+
+int
+lwip_bind(int s, const struct sockaddr *name, socklen_t namelen)
+{
+  struct lwip_socket *sock;
+  struct ip_addr local_addr;
+  u16_t local_port;
+  err_t err;
+
+  sock = get_socket(s);
+  if (!sock)
+    return -1;
+
+  LWIP_ERROR("lwip_bind: invalid address", ((namelen == sizeof(struct sockaddr_in)) &&
+             ((((const struct sockaddr_in *)name)->sin_family) == AF_INET)),
+             sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;);
+
+  local_addr.addr = ((const struct sockaddr_in *)name)->sin_addr.s_addr;
+  local_port = ((const struct sockaddr_in *)name)->sin_port;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d, addr=", s));
+  ip_addr_debug_print(SOCKETS_DEBUG, &local_addr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", ntohs(local_port)));
+
+  err = netconn_bind(sock->conn, &local_addr, ntohs(local_port));
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) succeeded\n", s));
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_close(int s)
+{
+  struct lwip_socket *sock;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_close(%d)\n", s));
+
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+
+  netconn_delete(sock->conn);
+
+  sys_sem_wait(socksem);
+  if (sock->lastdata) {
+    netbuf_delete(sock->lastdata);
+  }
+  sock->lastdata   = NULL;
+  sock->lastoffset = 0;
+  sock->conn       = NULL;
+  sock_set_errno(sock, 0);
+  sys_sem_signal(socksem);
+  return 0;
+}
+
+int
+lwip_connect(int s, const struct sockaddr *name, socklen_t namelen)
+{
+  struct lwip_socket *sock;
+  err_t err;
+
+  sock = get_socket(s);
+  if (!sock)
+    return -1;
+
+  LWIP_ERROR("lwip_connect: invalid address", ((namelen == sizeof(struct sockaddr_in)) &&
+             ((((const struct sockaddr_in *)name)->sin_family) == AF_INET)),
+             sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;);
+
+  if (((const struct sockaddr_in *)name)->sin_family == AF_UNSPEC) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, AF_UNSPEC)\n", s));
+    err = netconn_disconnect(sock->conn);
+  } else {
+    struct ip_addr remote_addr;
+    u16_t remote_port;
+
+    remote_addr.addr = ((const struct sockaddr_in *)name)->sin_addr.s_addr;
+    remote_port = ((const struct sockaddr_in *)name)->sin_port;
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, addr=", s));
+    ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr);
+    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", ntohs(remote_port)));
+
+    err = netconn_connect(sock->conn, &remote_addr, ntohs(remote_port));
+  }
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) succeeded\n", s));
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+/**
+ * Set a socket into listen mode.
+ * The socket may not have been used for another connection previously.
+ *
+ * @param s the socket to set to listening mode
+ * @param backlog (ATTENTION: need TCP_LISTEN_BACKLOG=1)
+ * @return 0 on success, non-zero on failure
+ */
+int
+lwip_listen(int s, int backlog)
+{
+  struct lwip_socket *sock;
+  err_t err;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d, backlog=%d)\n", s, backlog));
+
+  sock = get_socket(s);
+  if (!sock)
+    return -1;
+
+  /* limit the "backlog" parameter to fit in an u8_t */
+  if (backlog < 0) {
+    backlog = 0;
+  }
+  if (backlog > 0xff) {
+    backlog = 0xff;
+  }
+
+  err = netconn_listen_with_backlog(sock->conn, backlog);
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d) failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_recvfrom(int s, void *mem, size_t len, int flags,
+        struct sockaddr *from, socklen_t *fromlen)
+{
+  struct lwip_socket *sock;
+  struct netbuf      *buf;
+  u16_t               buflen, copylen, off = 0;
+  struct ip_addr     *addr;
+  u16_t               port;
+  u8_t                done = 0;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d, %p, %"SZT_F", 0x%x, ..)\n", s, mem, len, flags));
+  sock = get_socket(s);
+  if (!sock)
+    return -1;
+
+  do {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: top while sock->lastdata=%p\n", (void*)sock->lastdata));
+    /* Check if there is data left from the last recv operation. */
+    if (sock->lastdata) {
+      buf = sock->lastdata;
+    } else {
+      /* If this is non-blocking call, then check first */
+      if (((flags & MSG_DONTWAIT) || (sock->flags & O_NONBLOCK)) && 
+          (sock->rcvevent <= 0)) {
+        if (off > 0) {
+          /* already received data, return that */
+          sock_set_errno(sock, 0);
+          return off;
+        }
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): returning EWOULDBLOCK\n", s));
+        sock_set_errno(sock, EWOULDBLOCK);
+        return -1;
+      }
+
+      /* No data was left from the previous operation, so we try to get
+      some from the network. */
+      sock->lastdata = buf = netconn_recv(sock->conn);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: netconn_recv netbuf=%p\n", (void*)buf));
+
+      if (!buf) {
+        if (off > 0) {
+          /* already received data, return that */
+          sock_set_errno(sock, 0);
+          return off;
+        }
+        /* We should really do some error checking here. */
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): buf == NULL!\n", s));
+        sock_set_errno(sock, (((sock->conn->pcb.ip != NULL) && (sock->conn->err == ERR_OK))
+          ? ETIMEDOUT : err_to_errno(sock->conn->err)));
+        return 0;
+      }
+    }
+
+    buflen = netbuf_len(buf);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: buflen=%"U16_F" len=%"SZT_F" off=%"U16_F" sock->lastoffset=%"U16_F"\n",
+      buflen, len, off, sock->lastoffset));
+
+    buflen -= sock->lastoffset;
+
+    if (len > buflen) {
+      copylen = buflen;
+    } else {
+      copylen = (u16_t)len;
+    }
+
+    /* copy the contents of the received buffer into
+    the supplied memory pointer mem */
+    netbuf_copy_partial(buf, (u8_t*)mem + off, copylen, sock->lastoffset);
+
+    off += copylen;
+
+    if (netconn_type(sock->conn) == NETCONN_TCP) {
+      LWIP_ASSERT("invalid copylen, len would underflow", len >= copylen);
+      len -= copylen;
+      if ( (len <= 0) || 
+           (buf->p->flags & PBUF_FLAG_PUSH) || 
+           (sock->rcvevent <= 0) || 
+           ((flags & MSG_PEEK)!=0)) {
+        done = 1;
+      }
+    } else {
+      done = 1;
+    }
+
+    /* Check to see from where the data was.*/
+    if (done) {
+      if (from && fromlen) {
+        struct sockaddr_in sin;
+
+        if (netconn_type(sock->conn) == NETCONN_TCP) {
+          addr = (struct ip_addr*)&(sin.sin_addr.s_addr);
+          netconn_getaddr(sock->conn, addr, &port, 0);
+        } else {
+          addr = netbuf_fromaddr(buf);
+          port = netbuf_fromport(buf);
+        }
+
+        memset(&sin, 0, sizeof(sin));
+        sin.sin_len = sizeof(sin);
+        sin.sin_family = AF_INET;
+        sin.sin_port = htons(port);
+        sin.sin_addr.s_addr = addr->addr;
+
+        if (*fromlen > sizeof(sin)) {
+          *fromlen = sizeof(sin);
+        }
+
+        MEMCPY(from, &sin, *fromlen);
+
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s));
+        ip_addr_debug_print(SOCKETS_DEBUG, addr);
+        LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F" len=%"U16_F"\n", port, off));
+      } else {
+  #if SOCKETS_DEBUG
+        struct sockaddr_in sin;
+
+        if (netconn_type(sock->conn) == NETCONN_TCP) {
+          addr = (struct ip_addr*)&(sin.sin_addr.s_addr);
+          netconn_getaddr(sock->conn, addr, &port, 0);
+        } else {
+          addr = netbuf_fromaddr(buf);
+          port = netbuf_fromport(buf);
+        }
+
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s));
+        ip_addr_debug_print(SOCKETS_DEBUG, addr);
+        LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F" len=%"U16_F"\n", port, off));
+  #endif /*  SOCKETS_DEBUG */
+      }
+    }
+
+    /* If we don't peek the incoming message... */
+    if ((flags & MSG_PEEK)==0) {
+      /* If this is a TCP socket, check if there is data left in the
+         buffer. If so, it should be saved in the sock structure for next
+         time around. */
+      if ((netconn_type(sock->conn) == NETCONN_TCP) && (buflen - copylen > 0)) {
+        sock->lastdata = buf;
+        sock->lastoffset += copylen;
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: lastdata now netbuf=%p\n", (void*)buf));
+      } else {
+        sock->lastdata = NULL;
+        sock->lastoffset = 0;
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: deleting netbuf=%p\n", (void*)buf));
+        netbuf_delete(buf);
+      }
+    }
+  } while (!done);
+
+  sock_set_errno(sock, 0);
+  return off;
+}
+
+int
+lwip_read(int s, void *mem, size_t len)
+{
+  return lwip_recvfrom(s, mem, len, 0, NULL, NULL);
+}
+
+int
+lwip_recv(int s, void *mem, size_t len, int flags)
+{
+  return lwip_recvfrom(s, mem, len, flags, NULL, NULL);
+}
+
+int
+lwip_send(int s, const void *data, size_t size, int flags)
+{
+  struct lwip_socket *sock;
+  err_t err;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d, data=%p, size=%"SZT_F", flags=0x%x)\n",
+                              s, data, size, flags));
+
+  sock = get_socket(s);
+  if (!sock)
+    return -1;
+
+  if (sock->conn->type != NETCONN_TCP) {
+#if (LWIP_UDP || LWIP_RAW)
+    return lwip_sendto(s, data, size, flags, NULL, 0);
+#else
+    sock_set_errno(sock, err_to_errno(ERR_ARG));
+    return -1;
+#endif /* (LWIP_UDP || LWIP_RAW) */
+  }
+
+  err = netconn_write(sock->conn, data, size, NETCONN_COPY | ((flags & MSG_MORE)?NETCONN_MORE:0));
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) err=%d size=%"SZT_F"\n", s, err, size));
+  sock_set_errno(sock, err_to_errno(err));
+  return (err == ERR_OK ? (int)size : -1);
+}
+
+int
+lwip_sendto(int s, const void *data, size_t size, int flags,
+       const struct sockaddr *to, socklen_t tolen)
+{
+  struct lwip_socket *sock;
+  struct ip_addr remote_addr;
+  err_t err;
+  u16_t short_size;
+#if !LWIP_TCPIP_CORE_LOCKING
+  struct netbuf buf;
+  u16_t remote_port;
+#endif
+
+  sock = get_socket(s);
+  if (!sock)
+    return -1;
+
+  if (sock->conn->type == NETCONN_TCP) {
+#if LWIP_TCP
+    return lwip_send(s, data, size, flags);
+#else
+    sock_set_errno(sock, err_to_errno(ERR_ARG));
+    return -1;
+#endif /* LWIP_TCP */
+  }
+
+  LWIP_ASSERT("lwip_sendto: size must fit in u16_t", size <= 0xffff);
+  short_size = (u16_t)size;
+  LWIP_ERROR("lwip_sendto: invalid address", (((to == NULL) && (tolen == 0)) ||
+             ((tolen == sizeof(struct sockaddr_in)) &&
+             ((((const struct sockaddr_in *)to)->sin_family) == AF_INET))),
+             sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;);
+
+#if LWIP_TCPIP_CORE_LOCKING
+  /* Should only be consider like a sample or a simple way to experiment this option (no check of "to" field...) */
+  { struct pbuf* p;
+  
+    p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF);
+    if (p == NULL) {
+      err = ERR_MEM;
+    } else {
+      p->payload = (void*)data;
+      p->len = p->tot_len = short_size;
+      
+      remote_addr.addr = ((const struct sockaddr_in *)to)->sin_addr.s_addr;
+      
+      LOCK_TCPIP_CORE();
+      if (sock->conn->type==NETCONN_RAW) {
+        err = sock->conn->err = raw_sendto(sock->conn->pcb.raw, p, &remote_addr);
+      } else {
+        err = sock->conn->err = udp_sendto(sock->conn->pcb.udp, p, &remote_addr, ntohs(((const struct sockaddr_in *)to)->sin_port));
+      }
+      UNLOCK_TCPIP_CORE();
+      
+      pbuf_free(p);
+    }
+  }
+#else
+  /* initialize a buffer */
+  buf.p = buf.ptr = NULL;
+  if (to) {
+    remote_addr.addr = ((const struct sockaddr_in *)to)->sin_addr.s_addr;
+    remote_port      = ntohs(((const struct sockaddr_in *)to)->sin_port);
+    buf.addr         = &remote_addr;
+    buf.port         = remote_port;
+  } else {
+    remote_addr.addr = 0;
+    remote_port      = 0;
+    buf.addr         = NULL;
+    buf.port         = 0;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_sendto(%d, data=%p, short_size=%d"U16_F", flags=0x%x to=",
+              s, data, short_size, flags));
+  ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F"\n", remote_port));
+
+  /* make the buffer point to the data that should be sent */
+#if LWIP_NETIF_TX_SINGLE_PBUF
+  /* Allocate a new netbuf and copy the data into it. */
+  if (netbuf_alloc(&buf, short_size) == NULL) {
+    err = ERR_MEM;
+  } else {
+    err = netbuf_take(&buf, data, short_size);
+  }
+#else /* LWIP_NETIF_TX_SINGLE_PBUF */
+  err = netbuf_ref(&buf, data, short_size);
+#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
+  if (err == ERR_OK) {
+    /* send the data */
+    err = netconn_send(sock->conn, &buf);
+  }
+
+  /* deallocated the buffer */
+  netbuf_free(&buf);
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+  sock_set_errno(sock, err_to_errno(err));
+  return (err == ERR_OK ? short_size : -1);
+}
+
+int
+lwip_socket(int domain, int type, int protocol)
+{
+  struct netconn *conn;
+  int i;
+
+  LWIP_UNUSED_ARG(domain);
+
+  /* create a netconn */
+  switch (type) {
+  case SOCK_RAW:
+    conn = netconn_new_with_proto_and_callback(NETCONN_RAW, (u8_t)protocol, event_callback);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_RAW, %d) = ",
+                                 domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+    break;
+  case SOCK_DGRAM:
+    conn = netconn_new_with_callback( (protocol == IPPROTO_UDPLITE) ?
+                 NETCONN_UDPLITE : NETCONN_UDP, event_callback);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_DGRAM, %d) = ",
+                                 domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+    break;
+  case SOCK_STREAM:
+    conn = netconn_new_with_callback(NETCONN_TCP, event_callback);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_STREAM, %d) = ",
+                                 domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+    break;
+  default:
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%d, %d/UNKNOWN, %d) = -1\n",
+                                 domain, type, protocol));
+    set_errno(EINVAL);
+    return -1;
+  }
+
+  if (!conn) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("-1 / ENOBUFS (could not create netconn)\n"));
+    set_errno(ENOBUFS);
+    return -1;
+  }
+
+  i = alloc_socket(conn);
+
+  if (i == -1) {
+    netconn_delete(conn);
+    set_errno(ENFILE);
+    return -1;
+  }
+  conn->socket = i;
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("%d\n", i));
+  set_errno(0);
+  return i;
+}
+
+int
+lwip_write(int s, const void *data, size_t size)
+{
+  return lwip_send(s, data, size, 0);
+}
+
+/**
+ * Go through the readset and writeset lists and see which socket of the sockets
+ * set in the sets has events. On return, readset, writeset and exceptset have
+ * the sockets enabled that had events.
+ *
+ * exceptset is not used for now!!!
+ *
+ * @param maxfdp1 the highest socket index in the sets
+ * @param readset in: set of sockets to check for read events;
+ *                out: set of sockets that had read events
+ * @param writeset in: set of sockets to check for write events;
+ *                 out: set of sockets that had write events
+ * @param exceptset not yet implemented
+ * @return number of sockets that had events (read+write)
+ */
+static int
+lwip_selscan(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset)
+{
+  int i, nready = 0;
+  fd_set lreadset, lwriteset, lexceptset;
+  struct lwip_socket *p_sock;
+  
+  FD_ZERO(&lreadset);
+  FD_ZERO(&lwriteset);
+  FD_ZERO(&lexceptset);
+  
+  /* Go through each socket in each list to count number of sockets which
+  currently match */
+  for(i = 0; i < maxfdp1; i++) {
+    if (FD_ISSET(i, readset)) {
+      /* See if netconn of this socket is ready for read */
+      p_sock = get_socket(i);
+      if (p_sock && (p_sock->lastdata || (p_sock->rcvevent > 0))) {
+        FD_SET(i, &lreadset);
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for reading\n", i));
+        nready++;
+      }
+    }
+    if (FD_ISSET(i, writeset)) {
+      /* See if netconn of this socket is ready for write */
+      p_sock = get_socket(i);
+      if (p_sock && p_sock->sendevent) {
+        FD_SET(i, &lwriteset);
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for writing\n", i));
+        nready++;
+      }
+    }
+  }
+  *readset = lreadset;
+  *writeset = lwriteset;
+  FD_ZERO(exceptset);
+  
+  return nready;
+}
+
+
+/**
+ * Processing exceptset is not yet implemented.
+ */
+int
+lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
+               struct timeval *timeout)
+{
+  int i;
+  int nready;
+  fd_set lreadset, lwriteset, lexceptset;
+  u32_t msectimeout;
+  struct lwip_select_cb select_cb;
+  struct lwip_select_cb *p_selcb;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select(%d, %p, %p, %p, tvsec=%ld tvusec=%ld)\n",
+                  maxfdp1, (void *)readset, (void *) writeset, (void *) exceptset,
+                  timeout ? (long)timeout->tv_sec : (long)-1,
+                  timeout ? (long)timeout->tv_usec : (long)-1));
+
+  select_cb.next = 0;
+  select_cb.readset = readset;
+  select_cb.writeset = writeset;
+  select_cb.exceptset = exceptset;
+  select_cb.sem_signalled = 0;
+
+  /* Protect ourselves searching through the list */
+  sys_sem_wait(selectsem);
+
+  if (readset)
+    lreadset = *readset;
+  else
+    FD_ZERO(&lreadset);
+  if (writeset)
+    lwriteset = *writeset;
+  else
+    FD_ZERO(&lwriteset);
+  if (exceptset)
+    lexceptset = *exceptset;
+  else
+    FD_ZERO(&lexceptset);
+
+  /* Go through each socket in each list to count number of sockets which
+     currently match */
+  nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset);
+
+  /* If we don't have any current events, then suspend if we are supposed to */
+  if (!nready) {
+    if (timeout && timeout->tv_sec == 0 && timeout->tv_usec == 0) {
+      sys_sem_signal(selectsem);
+      if (readset)
+        FD_ZERO(readset);
+      if (writeset)
+        FD_ZERO(writeset);
+      if (exceptset)
+        FD_ZERO(exceptset);
+  
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: no timeout, returning 0\n"));
+      set_errno(0);
+  
+      return 0;
+    }
+    
+    /* add our semaphore to list */
+    /* We don't actually need any dynamic memory. Our entry on the
+     * list is only valid while we are in this function, so it's ok
+     * to use local variables */
+    
+    select_cb.sem = sys_sem_new(0);
+    /* Note that we are still protected */
+    /* Put this select_cb on top of list */
+    select_cb.next = select_cb_list;
+    select_cb_list = &select_cb;
+    
+    /* Now we can safely unprotect */
+    sys_sem_signal(selectsem);
+    
+    /* Now just wait to be woken */
+    if (timeout == 0)
+      /* Wait forever */
+      msectimeout = 0;
+    else {
+      msectimeout =  ((timeout->tv_sec * 1000) + ((timeout->tv_usec + 500)/1000));
+      if(msectimeout == 0)
+        msectimeout = 1;
+    }
+    
+    i = sys_sem_wait_timeout(select_cb.sem, msectimeout);
+    
+    /* Take us off the list */
+    sys_sem_wait(selectsem);
+    if (select_cb_list == &select_cb)
+      select_cb_list = select_cb.next;
+    else
+      for (p_selcb = select_cb_list; p_selcb; p_selcb = p_selcb->next) {
+        if (p_selcb->next == &select_cb) {
+          p_selcb->next = select_cb.next;
+          break;
+        }
+      }
+    
+    sys_sem_signal(selectsem);
+    
+    sys_sem_free(select_cb.sem);
+    if (i == 0)  {
+      /* Timeout */
+      if (readset)
+        FD_ZERO(readset);
+      if (writeset)
+        FD_ZERO(writeset);
+      if (exceptset)
+        FD_ZERO(exceptset);
+  
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: timeout expired\n"));
+      set_errno(0);
+  
+      return 0;
+    }
+    
+    if (readset)
+      lreadset = *readset;
+    else
+      FD_ZERO(&lreadset);
+    if (writeset)
+      lwriteset = *writeset;
+    else
+      FD_ZERO(&lwriteset);
+    if (exceptset)
+      lexceptset = *exceptset;
+    else
+      FD_ZERO(&lexceptset);
+    
+    /* See what's set */
+    nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset);
+  } else
+    sys_sem_signal(selectsem);
+  
+  if (readset)
+    *readset = lreadset;
+  if (writeset)
+    *writeset = lwriteset;
+  if (exceptset)
+    *exceptset = lexceptset;
+  
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: nready=%d\n", nready));
+  set_errno(0);
+  
+  return nready;
+}
+
+/**
+ * Callback registered in the netconn layer for each socket-netconn.
+ * Processes recvevent (data available) and wakes up tasks waiting for select.
+ */
+static void
+event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len)
+{
+  int s;
+  struct lwip_socket *sock;
+  struct lwip_select_cb *scb;
+
+  LWIP_UNUSED_ARG(len);
+
+  /* Get socket */
+  if (conn) {
+    s = conn->socket;
+    if (s < 0) {
+      /* Data comes in right away after an accept, even though
+       * the server task might not have created a new socket yet.
+       * Just count down (or up) if that's the case and we
+       * will use the data later. Note that only receive events
+       * can happen before the new socket is set up. */
+      sys_sem_wait(socksem);
+      if (conn->socket < 0) {
+        if (evt == NETCONN_EVT_RCVPLUS) {
+          conn->socket--;
+        }
+        sys_sem_signal(socksem);
+        return;
+      }
+      s = conn->socket;
+      sys_sem_signal(socksem);
+    }
+
+    sock = get_socket(s);
+    if (!sock) {
+      return;
+    }
+  } else {
+    return;
+  }
+
+  sys_sem_wait(selectsem);
+  /* Set event as required */
+  switch (evt) {
+    case NETCONN_EVT_RCVPLUS:
+      sock->rcvevent++;
+      break;
+    case NETCONN_EVT_RCVMINUS:
+      sock->rcvevent--;
+      break;
+    case NETCONN_EVT_SENDPLUS:
+      sock->sendevent = 1;
+      break;
+    case NETCONN_EVT_SENDMINUS:
+      sock->sendevent = 0;
+      break;
+    default:
+      LWIP_ASSERT("unknown event", 0);
+      break;
+  }
+  sys_sem_signal(selectsem);
+
+  /* Now decide if anyone is waiting for this socket */
+  /* NOTE: This code is written this way to protect the select link list
+     but to avoid a deadlock situation by releasing socksem before
+     signalling for the select. This means we need to go through the list
+     multiple times ONLY IF a select was actually waiting. We go through
+     the list the number of waiting select calls + 1. This list is
+     expected to be small. */
+  while (1) {
+    sys_sem_wait(selectsem);
+    for (scb = select_cb_list; scb; scb = scb->next) {
+      if (scb->sem_signalled == 0) {
+        /* Test this select call for our socket */
+        if (scb->readset && FD_ISSET(s, scb->readset))
+          if (sock->rcvevent > 0)
+            break;
+        if (scb->writeset && FD_ISSET(s, scb->writeset))
+          if (sock->sendevent)
+            break;
+      }
+    }
+    if (scb) {
+      scb->sem_signalled = 1;
+      sys_sem_signal(scb->sem);
+      sys_sem_signal(selectsem);
+    } else {
+      sys_sem_signal(selectsem);
+      break;
+    }
+  }
+}
+
+/**
+ * Unimplemented: Close one end of a full-duplex connection.
+ * Currently, the full connection is closed.
+ */
+int
+lwip_shutdown(int s, int how)
+{
+  LWIP_UNUSED_ARG(how);
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_shutdown(%d, how=%d)\n", s, how));
+  return lwip_close(s); /* XXX temporary hack until proper implementation */
+}
+
+static int
+lwip_getaddrname(int s, struct sockaddr *name, socklen_t *namelen, u8_t local)
+{
+  struct lwip_socket *sock;
+  struct sockaddr_in sin;
+  struct ip_addr naddr;
+
+  sock = get_socket(s);
+  if (!sock)
+    return -1;
+
+  memset(&sin, 0, sizeof(sin));
+  sin.sin_len = sizeof(sin);
+  sin.sin_family = AF_INET;
+
+  /* get the IP address and port */
+  netconn_getaddr(sock->conn, &naddr, &sin.sin_port, local);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getaddrname(%d, addr=", s));
+  ip_addr_debug_print(SOCKETS_DEBUG, &naddr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", sin.sin_port));
+
+  sin.sin_port = htons(sin.sin_port);
+  sin.sin_addr.s_addr = naddr.addr;
+
+  if (*namelen > sizeof(sin))
+    *namelen = sizeof(sin);
+
+  MEMCPY(name, &sin, *namelen);
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_getpeername(int s, struct sockaddr *name, socklen_t *namelen)
+{
+  return lwip_getaddrname(s, name, namelen, 0);
+}
+
+int
+lwip_getsockname(int s, struct sockaddr *name, socklen_t *namelen)
+{
+  return lwip_getaddrname(s, name, namelen, 1);
+}
+
+int
+lwip_getsockopt(int s, int level, int optname, void *optval, socklen_t *optlen)
+{
+  err_t err = ERR_OK;
+  struct lwip_socket *sock = get_socket(s);
+  struct lwip_setgetsockopt_data data;
+
+  if (!sock)
+    return -1;
+
+  if ((NULL == optval) || (NULL == optlen)) {
+    sock_set_errno(sock, EFAULT);
+    return -1;
+  }
+
+  /* Do length and type checks for the various options first, to keep it readable. */
+  switch (level) {
+   
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch (optname) {
+       
+    case SO_ACCEPTCONN:
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_ERROR:
+    case SO_KEEPALIVE:
+    /* UNIMPL case SO_CONTIMEO: */
+    /* UNIMPL case SO_SNDTIMEO: */
+#if LWIP_SO_RCVTIMEO
+    case SO_RCVTIMEO:
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+    case SO_RCVBUF:
+#endif /* LWIP_SO_RCVBUF */
+    /* UNIMPL case SO_OOBINLINE: */
+    /* UNIMPL case SO_SNDBUF: */
+    /* UNIMPL case SO_RCVLOWAT: */
+    /* UNIMPL case SO_SNDLOWAT: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    case SO_TYPE:
+    /* UNIMPL case SO_USELOOPBACK: */
+      if (*optlen < sizeof(int)) {
+        err = EINVAL;
+      }
+      break;
+
+    case SO_NO_CHECK:
+      if (*optlen < sizeof(int)) {
+        err = EINVAL;
+      }
+#if LWIP_UDP
+      if ((sock->conn->type != NETCONN_UDP) ||
+          ((udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_UDPLITE) != 0)) {
+        /* this flag is only available for UDP, not for UDP lite */
+        err = EAFNOSUPPORT;
+      }
+#endif /* LWIP_UDP */
+      break;
+
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n",
+                                  s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+                     
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch (optname) {
+    /* UNIMPL case IP_HDRINCL: */
+    /* UNIMPL case IP_RCVDSTADDR: */
+    /* UNIMPL case IP_RCVIF: */
+    case IP_TTL:
+    case IP_TOS:
+      if (*optlen < sizeof(int)) {
+        err = EINVAL;
+      }
+      break;
+#if LWIP_IGMP
+    case IP_MULTICAST_TTL:
+      if (*optlen < sizeof(u8_t)) {
+        err = EINVAL;
+      }
+      break;
+    case IP_MULTICAST_IF:
+      if (*optlen < sizeof(struct in_addr)) {
+        err = EINVAL;
+      }
+      break;
+#endif /* LWIP_IGMP */
+
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n",
+                                  s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+         
+#if LWIP_TCP
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    if (*optlen < sizeof(int)) {
+      err = EINVAL;
+      break;
+    }
+    
+    /* If this is no TCP socket, ignore any options. */
+    if (sock->conn->type != NETCONN_TCP)
+      return 0;
+
+    switch (optname) {
+    case TCP_NODELAY:
+    case TCP_KEEPALIVE:
+#if LWIP_TCP_KEEPALIVE
+    case TCP_KEEPIDLE:
+    case TCP_KEEPINTVL:
+    case TCP_KEEPCNT:
+#endif /* LWIP_TCP_KEEPALIVE */
+      break;
+       
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n",
+                                  s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_TCP */
+#if LWIP_UDP && LWIP_UDPLITE
+/* Level: IPPROTO_UDPLITE */
+  case IPPROTO_UDPLITE:
+    if (*optlen < sizeof(int)) {
+      err = EINVAL;
+      break;
+    }
+    
+    /* If this is no UDP lite socket, ignore any options. */
+    if (sock->conn->type != NETCONN_UDPLITE)
+      return 0;
+
+    switch (optname) {
+    case UDPLITE_SEND_CSCOV:
+    case UDPLITE_RECV_CSCOV:
+      break;
+       
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UNIMPL: optname=0x%x, ..)\n",
+                                  s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_UDP && LWIP_UDPLITE*/
+/* UNDEFINED LEVEL */
+  default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n",
+                                  s, level, optname));
+      err = ENOPROTOOPT;
+  }  /* switch */
+
+   
+  if (err != ERR_OK) {
+    sock_set_errno(sock, err);
+    return -1;
+  }
+
+  /* Now do the actual option processing */
+  data.sock = sock;
+  data.level = level;
+  data.optname = optname;
+  data.optval = optval;
+  data.optlen = optlen;
+  data.err = err;
+  tcpip_callback(lwip_getsockopt_internal, &data);
+  sys_arch_sem_wait(sock->conn->op_completed, 0);
+  /* maybe lwip_getsockopt_internal has changed err */
+  err = data.err;
+
+  sock_set_errno(sock, err);
+  return err ? -1 : 0;
+}
+
+static void
+lwip_getsockopt_internal(void *arg)
+{
+  struct lwip_socket *sock;
+#ifdef LWIP_DEBUG
+  int s;
+#endif /* LWIP_DEBUG */
+  int level, optname;
+  void *optval;
+  struct lwip_setgetsockopt_data *data;
+
+  LWIP_ASSERT("arg != NULL", arg != NULL);
+
+  data = (struct lwip_setgetsockopt_data*)arg;
+  sock = data->sock;
+#ifdef LWIP_DEBUG
+  s = data->s;
+#endif /* LWIP_DEBUG */
+  level = data->level;
+  optname = data->optname;
+  optval = data->optval;
+
+  switch (level) {
+   
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch (optname) {
+
+    /* The option flags */
+    case SO_ACCEPTCONN:
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_KEEPALIVE:
+    /* UNIMPL case SO_OOBINCLUDE: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    /*case SO_USELOOPBACK: UNIMPL */
+      *(int*)optval = sock->conn->pcb.ip->so_options & optname;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, optname=0x%x, ..) = %s\n",
+                                  s, optname, (*(int*)optval?"on":"off")));
+      break;
+
+    case SO_TYPE:
+      switch (NETCONNTYPE_GROUP(sock->conn->type)) {
+      case NETCONN_RAW:
+        *(int*)optval = SOCK_RAW;
+        break;
+      case NETCONN_TCP:
+        *(int*)optval = SOCK_STREAM;
+        break;
+      case NETCONN_UDP:
+        *(int*)optval = SOCK_DGRAM;
+        break;
+      default: /* unrecognized socket type */
+        *(int*)optval = sock->conn->type;
+        LWIP_DEBUGF(SOCKETS_DEBUG,
+                    ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE): unrecognized socket type %d\n",
+                    s, *(int *)optval));
+      }  /* switch (sock->conn->type) */
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE) = %d\n",
+                  s, *(int *)optval));
+      break;
+
+    case SO_ERROR:
+      if (sock->err == 0) {
+        sock_set_errno(sock, err_to_errno(sock->conn->err));
+      } 
+      *(int *)optval = sock->err;
+      sock->err = 0;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_ERROR) = %d\n",
+                  s, *(int *)optval));
+      break;
+
+#if LWIP_SO_RCVTIMEO
+    case SO_RCVTIMEO:
+      *(int *)optval = sock->conn->recv_timeout;
+      break;
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+    case SO_RCVBUF:
+      *(int *)optval = sock->conn->recv_bufsize;
+      break;
+#endif /* LWIP_SO_RCVBUF */
+#if LWIP_UDP
+    case SO_NO_CHECK:
+      *(int*)optval = (udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_NOCHKSUM) ? 1 : 0;
+      break;
+#endif /* LWIP_UDP*/
+    }  /* switch (optname) */
+    break;
+
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch (optname) {
+    case IP_TTL:
+      *(int*)optval = sock->conn->pcb.ip->ttl;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TTL) = %d\n",
+                  s, *(int *)optval));
+      break;
+    case IP_TOS:
+      *(int*)optval = sock->conn->pcb.ip->tos;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TOS) = %d\n",
+                  s, *(int *)optval));
+      break;
+#if LWIP_IGMP
+    case IP_MULTICAST_TTL:
+      *(u8_t*)optval = sock->conn->pcb.ip->ttl;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_TTL) = %d\n",
+                  s, *(int *)optval));
+      break;
+    case IP_MULTICAST_IF:
+      ((struct in_addr*) optval)->s_addr = sock->conn->pcb.udp->multicast_ip.addr;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_IF) = 0x%"X32_F"\n",
+                  s, *(u32_t *)optval));
+      break;
+#endif /* LWIP_IGMP */
+    }  /* switch (optname) */
+    break;
+
+#if LWIP_TCP
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    switch (optname) {
+    case TCP_NODELAY:
+      *(int*)optval = tcp_nagle_disabled(sock->conn->pcb.tcp);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_NODELAY) = %s\n",
+                  s, (*(int*)optval)?"on":"off") );
+      break;
+    case TCP_KEEPALIVE:
+      *(int*)optval = (int)sock->conn->pcb.tcp->keep_idle;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPALIVE) = %d\n",
+                  s, *(int *)optval));
+      break;
+
+#if LWIP_TCP_KEEPALIVE
+    case TCP_KEEPIDLE:
+      *(int*)optval = (int)(sock->conn->pcb.tcp->keep_idle/1000);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPIDLE) = %d\n",
+                  s, *(int *)optval));
+      break;
+    case TCP_KEEPINTVL:
+      *(int*)optval = (int)(sock->conn->pcb.tcp->keep_intvl/1000);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPINTVL) = %d\n",
+                  s, *(int *)optval));
+      break;
+    case TCP_KEEPCNT:
+      *(int*)optval = (int)sock->conn->pcb.tcp->keep_cnt;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPCNT) = %d\n",
+                  s, *(int *)optval));
+      break;
+#endif /* LWIP_TCP_KEEPALIVE */
+
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_TCP */
+#if LWIP_UDP && LWIP_UDPLITE
+  /* Level: IPPROTO_UDPLITE */
+  case IPPROTO_UDPLITE:
+    switch (optname) {
+    case UDPLITE_SEND_CSCOV:
+      *(int*)optval = sock->conn->pcb.udp->chksum_len_tx;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UDPLITE_SEND_CSCOV) = %d\n",
+                  s, (*(int*)optval)) );
+      break;
+    case UDPLITE_RECV_CSCOV:
+      *(int*)optval = sock->conn->pcb.udp->chksum_len_rx;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UDPLITE_RECV_CSCOV) = %d\n",
+                  s, (*(int*)optval)) );
+      break;
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_UDP */
+  } /* switch (level) */
+  sys_sem_signal(sock->conn->op_completed);
+}
+
+int
+lwip_setsockopt(int s, int level, int optname, const void *optval, socklen_t optlen)
+{
+  struct lwip_socket *sock = get_socket(s);
+  int err = ERR_OK;
+  struct lwip_setgetsockopt_data data;
+
+  if (!sock)
+    return -1;
+
+  if (NULL == optval) {
+    sock_set_errno(sock, EFAULT);
+    return -1;
+  }
+
+  /* Do length and type checks for the various options first, to keep it readable. */
+  switch (level) {
+
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch (optname) {
+
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_KEEPALIVE:
+    /* UNIMPL case case SO_CONTIMEO: */
+    /* UNIMPL case case SO_SNDTIMEO: */
+#if LWIP_SO_RCVTIMEO
+    case SO_RCVTIMEO:
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+    case SO_RCVBUF:
+#endif /* LWIP_SO_RCVBUF */
+    /* UNIMPL case SO_OOBINLINE: */
+    /* UNIMPL case SO_SNDBUF: */
+    /* UNIMPL case SO_RCVLOWAT: */
+    /* UNIMPL case SO_SNDLOWAT: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    /* UNIMPL case SO_USELOOPBACK: */
+      if (optlen < sizeof(int)) {
+        err = EINVAL;
+      }
+      break;
+    case SO_NO_CHECK:
+      if (optlen < sizeof(int)) {
+        err = EINVAL;
+      }
+#if LWIP_UDP
+      if ((sock->conn->type != NETCONN_UDP) ||
+          ((udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_UDPLITE) != 0)) {
+        /* this flag is only available for UDP, not for UDP lite */
+        err = EAFNOSUPPORT;
+      }
+#endif /* LWIP_UDP */
+      break;
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n",
+                  s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch (optname) {
+    /* UNIMPL case IP_HDRINCL: */
+    /* UNIMPL case IP_RCVDSTADDR: */
+    /* UNIMPL case IP_RCVIF: */
+    case IP_TTL:
+    case IP_TOS:
+      if (optlen < sizeof(int)) {
+        err = EINVAL;
+      }
+      break;
+#if LWIP_IGMP
+    case IP_MULTICAST_TTL:
+      if (optlen < sizeof(u8_t)) {
+        err = EINVAL;
+      }
+      if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_UDP) {
+        err = EAFNOSUPPORT;
+      }
+      break;
+    case IP_MULTICAST_IF:
+      if (optlen < sizeof(struct in_addr)) {
+        err = EINVAL;
+      }
+      if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_UDP) {
+        err = EAFNOSUPPORT;
+      }
+      break;
+    case IP_ADD_MEMBERSHIP:
+    case IP_DROP_MEMBERSHIP:
+      if (optlen < sizeof(struct ip_mreq)) {
+        err = EINVAL;
+      }
+      if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_UDP) {
+        err = EAFNOSUPPORT;
+      }
+      break;
+#endif /* LWIP_IGMP */
+      default:
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n",
+                    s, optname));
+        err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+
+#if LWIP_TCP
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    if (optlen < sizeof(int)) {
+      err = EINVAL;
+      break;
+    }
+
+    /* If this is no TCP socket, ignore any options. */
+    if (sock->conn->type != NETCONN_TCP)
+      return 0;
+
+    switch (optname) {
+    case TCP_NODELAY:
+    case TCP_KEEPALIVE:
+#if LWIP_TCP_KEEPALIVE
+    case TCP_KEEPIDLE:
+    case TCP_KEEPINTVL:
+    case TCP_KEEPCNT:
+#endif /* LWIP_TCP_KEEPALIVE */
+      break;
+
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n",
+                  s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_TCP */
+#if LWIP_UDP && LWIP_UDPLITE
+/* Level: IPPROTO_UDPLITE */
+  case IPPROTO_UDPLITE:
+    if (optlen < sizeof(int)) {
+      err = EINVAL;
+      break;
+    }
+
+    /* If this is no UDP lite socket, ignore any options. */
+    if (sock->conn->type != NETCONN_UDPLITE)
+      return 0;
+
+    switch (optname) {
+    case UDPLITE_SEND_CSCOV:
+    case UDPLITE_RECV_CSCOV:
+      break;
+
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UNIMPL: optname=0x%x, ..)\n",
+                  s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_UDP && LWIP_UDPLITE */
+/* UNDEFINED LEVEL */
+  default:
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n",
+                s, level, optname));
+    err = ENOPROTOOPT;
+  }  /* switch (level) */
+
+
+  if (err != ERR_OK) {
+    sock_set_errno(sock, err);
+    return -1;
+  }
+
+
+  /* Now do the actual option processing */
+  data.sock = sock;
+  data.level = level;
+  data.optname = optname;
+  data.optval = (void*)optval;
+  data.optlen = &optlen;
+  data.err = err;
+  tcpip_callback(lwip_setsockopt_internal, &data);
+  sys_arch_sem_wait(sock->conn->op_completed, 0);
+  /* maybe lwip_setsockopt_internal has changed err */
+  err = data.err;
+
+  sock_set_errno(sock, err);
+  return err ? -1 : 0;
+}
+
+static void
+lwip_setsockopt_internal(void *arg)
+{
+  struct lwip_socket *sock;
+#ifdef LWIP_DEBUG
+  int s;
+#endif /* LWIP_DEBUG */
+  int level, optname;
+  const void *optval;
+  struct lwip_setgetsockopt_data *data;
+
+  LWIP_ASSERT("arg != NULL", arg != NULL);
+
+  data = (struct lwip_setgetsockopt_data*)arg;
+  sock = data->sock;
+#ifdef LWIP_DEBUG
+  s = data->s;
+#endif /* LWIP_DEBUG */
+  level = data->level;
+  optname = data->optname;
+  optval = data->optval;
+
+  switch (level) {
+
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch (optname) {
+
+    /* The option flags */
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_KEEPALIVE:
+    /* UNIMPL case SO_OOBINCLUDE: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    /* UNIMPL case SO_USELOOPBACK: */
+      if (*(int*)optval) {
+        sock->conn->pcb.ip->so_options |= optname;
+      } else {
+        sock->conn->pcb.ip->so_options &= ~optname;
+      }
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, optname=0x%x, ..) -> %s\n",
+                  s, optname, (*(int*)optval?"on":"off")));
+      break;
+#if LWIP_SO_RCVTIMEO
+    case SO_RCVTIMEO:
+      sock->conn->recv_timeout = ( *(int*)optval );
+      break;
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+    case SO_RCVBUF:
+      sock->conn->recv_bufsize = ( *(int*)optval );
+      break;
+#endif /* LWIP_SO_RCVBUF */
+#if LWIP_UDP
+    case SO_NO_CHECK:
+      if (*(int*)optval) {
+        udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) | UDP_FLAGS_NOCHKSUM);
+      } else {
+        udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) & ~UDP_FLAGS_NOCHKSUM);
+      }
+      break;
+#endif /* LWIP_UDP */
+    }  /* switch (optname) */
+    break;
+
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch (optname) {
+    case IP_TTL:
+      sock->conn->pcb.ip->ttl = (u8_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TTL, ..) -> %d\n",
+                  s, sock->conn->pcb.ip->ttl));
+      break;
+    case IP_TOS:
+      sock->conn->pcb.ip->tos = (u8_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TOS, ..)-> %d\n",
+                  s, sock->conn->pcb.ip->tos));
+      break;
+#if LWIP_IGMP
+    case IP_MULTICAST_TTL:
+      sock->conn->pcb.udp->ttl = (u8_t)(*(u8_t*)optval);
+      break;
+    case IP_MULTICAST_IF:
+      sock->conn->pcb.udp->multicast_ip.addr = ((struct in_addr*) optval)->s_addr;
+      break;
+    case IP_ADD_MEMBERSHIP:
+    case IP_DROP_MEMBERSHIP:
+      {
+        /* If this is a TCP or a RAW socket, ignore these options. */
+        struct ip_mreq *imr = (struct ip_mreq *)optval;
+        if(optname == IP_ADD_MEMBERSHIP){
+          data->err = igmp_joingroup((struct ip_addr*)&(imr->imr_interface.s_addr), (struct ip_addr*)&(imr->imr_multiaddr.s_addr));
+        } else {
+          data->err = igmp_leavegroup((struct ip_addr*)&(imr->imr_interface.s_addr), (struct ip_addr*)&(imr->imr_multiaddr.s_addr));
+        }
+        if(data->err != ERR_OK) {
+          data->err = EADDRNOTAVAIL;
+        }
+      }
+      break;
+#endif /* LWIP_IGMP */
+    }  /* switch (optname) */
+    break;
+
+#if LWIP_TCP
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    switch (optname) {
+    case TCP_NODELAY:
+      if (*(int*)optval) {
+        tcp_nagle_disable(sock->conn->pcb.tcp);
+      } else {
+        tcp_nagle_enable(sock->conn->pcb.tcp);
+      }
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_NODELAY) -> %s\n",
+                  s, (*(int *)optval)?"on":"off") );
+      break;
+    case TCP_KEEPALIVE:
+      sock->conn->pcb.tcp->keep_idle = (u32_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) -> %"U32_F"\n",
+                  s, sock->conn->pcb.tcp->keep_idle));
+      break;
+
+#if LWIP_TCP_KEEPALIVE
+    case TCP_KEEPIDLE:
+      sock->conn->pcb.tcp->keep_idle = 1000*(u32_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPIDLE) -> %"U32_F"\n",
+                  s, sock->conn->pcb.tcp->keep_idle));
+      break;
+    case TCP_KEEPINTVL:
+      sock->conn->pcb.tcp->keep_intvl = 1000*(u32_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPINTVL) -> %"U32_F"\n",
+                  s, sock->conn->pcb.tcp->keep_intvl));
+      break;
+    case TCP_KEEPCNT:
+      sock->conn->pcb.tcp->keep_cnt = (u32_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPCNT) -> %"U32_F"\n",
+                  s, sock->conn->pcb.tcp->keep_cnt));
+      break;
+#endif /* LWIP_TCP_KEEPALIVE */
+
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_TCP*/
+#if LWIP_UDP && LWIP_UDPLITE
+  /* Level: IPPROTO_UDPLITE */
+  case IPPROTO_UDPLITE:
+    switch (optname) {
+    case UDPLITE_SEND_CSCOV:
+      if ((*(int*)optval != 0) && (*(int*)optval < 8)) {
+        /* don't allow illegal values! */
+        sock->conn->pcb.udp->chksum_len_tx = 8;
+      } else {
+        sock->conn->pcb.udp->chksum_len_tx = *(int*)optval;
+      }
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UDPLITE_SEND_CSCOV) -> %d\n",
+                  s, (*(int*)optval)) );
+      break;
+    case UDPLITE_RECV_CSCOV:
+      if ((*(int*)optval != 0) && (*(int*)optval < 8)) {
+        /* don't allow illegal values! */
+        sock->conn->pcb.udp->chksum_len_rx = 8;
+      } else {
+        sock->conn->pcb.udp->chksum_len_rx = *(int*)optval;
+      }
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UDPLITE_RECV_CSCOV) -> %d\n",
+                  s, (*(int*)optval)) );
+      break;
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_UDP */
+  }  /* switch (level) */
+  sys_sem_signal(sock->conn->op_completed);
+}
+
+int
+lwip_ioctl(int s, long cmd, void *argp)
+{
+  struct lwip_socket *sock = get_socket(s);
+  u16_t buflen = 0;
+  s16_t recv_avail;
+
+  if (!sock)
+    return -1;
+
+  switch (cmd) {
+  case FIONREAD:
+    if (!argp) {
+      sock_set_errno(sock, EINVAL);
+      return -1;
+    }
+
+    SYS_ARCH_GET(sock->conn->recv_avail, recv_avail);
+    if (recv_avail < 0)
+      recv_avail = 0;
+    *((u16_t*)argp) = (u16_t)recv_avail;
+
+    /* Check if there is data left from the last recv operation. /maq 041215 */
+    if (sock->lastdata) {
+      buflen = netbuf_len(sock->lastdata);
+      buflen -= sock->lastoffset;
+
+      *((u16_t*)argp) += buflen;
+    }
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONREAD, %p) = %"U16_F"\n", s, argp, *((u16_t*)argp)));
+    sock_set_errno(sock, 0);
+    return 0;
+
+  case FIONBIO:
+    if (argp && *(u32_t*)argp)
+      sock->flags |= O_NONBLOCK;
+    else
+      sock->flags &= ~O_NONBLOCK;
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONBIO, %d)\n", s, !!(sock->flags & O_NONBLOCK)));
+    sock_set_errno(sock, 0);
+    return 0;
+
+  default:
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, UNIMPL: 0x%lx, %p)\n", s, cmd, argp));
+    sock_set_errno(sock, ENOSYS); /* not yet implemented */
+    return -1;
+  } /* switch (cmd) */
+}
+
+#endif /* LWIP_SOCKET */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/tcpip.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/tcpip.c
new file mode 100644
index 0000000..002df90
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/api/tcpip.c
@@ -0,0 +1,596 @@
+/**
+ * @file
+ * Sequential API Main thread module
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if !NO_SYS /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/sys.h"
+#include "lwip/memp.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_frag.h"
+#include "lwip/tcp.h"
+#include "lwip/autoip.h"
+#include "lwip/dhcp.h"
+#include "lwip/igmp.h"
+#include "lwip/dns.h"
+#include "lwip/tcpip.h"
+#include "lwip/init.h"
+#include "netif/etharp.h"
+#include "netif/ppp_oe.h"
+
+/* global variables */
+static void (* tcpip_init_done)(void *arg);
+static void *tcpip_init_done_arg;
+static sys_mbox_t mbox = SYS_MBOX_NULL;
+
+#if LWIP_TCPIP_CORE_LOCKING
+/** The global semaphore to lock the stack. */
+sys_sem_t lock_tcpip_core;
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+
+#if LWIP_TCP
+/* global variable that shows if the tcp timer is currently scheduled or not */
+static int tcpip_tcp_timer_active;
+
+/**
+ * Timer callback function that calls tcp_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+tcpip_tcp_timer(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+
+  /* call TCP timer handler */
+  tcp_tmr();
+  /* timer still needed? */
+  if (tcp_active_pcbs || tcp_tw_pcbs) {
+    /* restart timer */
+    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
+  } else {
+    /* disable timer */
+    tcpip_tcp_timer_active = 0;
+  }
+}
+
+#if !NO_SYS
+/**
+ * Called from TCP_REG when registering a new PCB:
+ * the reason is to have the TCP timer only running when
+ * there are active (or time-wait) PCBs.
+ */
+void
+tcp_timer_needed(void)
+{
+  /* timer is off but needed again? */
+  if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) {
+    /* enable and start timer */
+    tcpip_tcp_timer_active = 1;
+    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
+  }
+}
+#endif /* !NO_SYS */
+#endif /* LWIP_TCP */
+
+#if IP_REASSEMBLY
+/**
+ * Timer callback function that calls ip_reass_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+ip_reass_timer(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: ip_reass_tmr()\n"));
+  ip_reass_tmr();
+  sys_timeout(IP_TMR_INTERVAL, ip_reass_timer, NULL);
+}
+#endif /* IP_REASSEMBLY */
+
+#if LWIP_ARP
+/**
+ * Timer callback function that calls etharp_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+arp_timer(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: etharp_tmr()\n"));
+  etharp_tmr();
+  sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL);
+}
+#endif /* LWIP_ARP */
+
+#if LWIP_DHCP
+/**
+ * Timer callback function that calls dhcp_coarse_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+dhcp_timer_coarse(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: dhcp_coarse_tmr()\n"));
+  dhcp_coarse_tmr();
+  sys_timeout(DHCP_COARSE_TIMER_MSECS, dhcp_timer_coarse, NULL);
+}
+
+/**
+ * Timer callback function that calls dhcp_fine_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+dhcp_timer_fine(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: dhcp_fine_tmr()\n"));
+  dhcp_fine_tmr();
+  sys_timeout(DHCP_FINE_TIMER_MSECS, dhcp_timer_fine, NULL);
+}
+#endif /* LWIP_DHCP */
+
+#if LWIP_AUTOIP
+/**
+ * Timer callback function that calls autoip_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+autoip_timer(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: autoip_tmr()\n"));
+  autoip_tmr();
+  sys_timeout(AUTOIP_TMR_INTERVAL, autoip_timer, NULL);
+}
+#endif /* LWIP_AUTOIP */
+
+#if LWIP_IGMP
+/**
+ * Timer callback function that calls igmp_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+igmp_timer(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: igmp_tmr()\n"));
+  igmp_tmr();
+  sys_timeout(IGMP_TMR_INTERVAL, igmp_timer, NULL);
+}
+#endif /* LWIP_IGMP */
+
+#if LWIP_DNS
+/**
+ * Timer callback function that calls dns_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+dns_timer(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: dns_tmr()\n"));
+  dns_tmr();
+  sys_timeout(DNS_TMR_INTERVAL, dns_timer, NULL);
+}
+#endif /* LWIP_DNS */
+
+/**
+ * The main lwIP thread. This thread has exclusive access to lwIP core functions
+ * (unless access to them is not locked). Other threads communicate with this
+ * thread using message boxes.
+ *
+ * It also starts all the timers to make sure they are running in the right
+ * thread context.
+ *
+ * @param arg unused argument
+ */
+static void
+tcpip_thread(void *arg)
+{
+  struct tcpip_msg *msg;
+  LWIP_UNUSED_ARG(arg);
+
+#if IP_REASSEMBLY
+  sys_timeout(IP_TMR_INTERVAL, ip_reass_timer, NULL);
+#endif /* IP_REASSEMBLY */
+#if LWIP_ARP
+  sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL);
+#endif /* LWIP_ARP */
+#if LWIP_DHCP
+  sys_timeout(DHCP_COARSE_TIMER_MSECS, dhcp_timer_coarse, NULL);
+  sys_timeout(DHCP_FINE_TIMER_MSECS, dhcp_timer_fine, NULL);
+#endif /* LWIP_DHCP */
+#if LWIP_AUTOIP
+  sys_timeout(AUTOIP_TMR_INTERVAL, autoip_timer, NULL);
+#endif /* LWIP_AUTOIP */
+#if LWIP_IGMP
+  sys_timeout(IGMP_TMR_INTERVAL, igmp_timer, NULL);
+#endif /* LWIP_IGMP */
+#if LWIP_DNS
+  sys_timeout(DNS_TMR_INTERVAL, dns_timer, NULL);
+#endif /* LWIP_DNS */
+
+  if (tcpip_init_done != NULL) {
+    tcpip_init_done(tcpip_init_done_arg);
+  }
+
+  LOCK_TCPIP_CORE();
+  while (1) {                          /* MAIN Loop */
+    sys_mbox_fetch(mbox, (void *)&msg);
+    switch (msg->type) {
+#if LWIP_NETCONN
+    case TCPIP_MSG_API:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: API message %p\n", (void *)msg));
+      msg->msg.apimsg->function(&(msg->msg.apimsg->msg));
+      break;
+#endif /* LWIP_NETCONN */
+
+    case TCPIP_MSG_INPKT:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: PACKET %p\n", (void *)msg));
+#if LWIP_ARP
+      if (msg->msg.inp.netif->flags & NETIF_FLAG_ETHARP) {
+        ethernet_input(msg->msg.inp.p, msg->msg.inp.netif);
+      } else
+#endif /* LWIP_ARP */
+      { ip_input(msg->msg.inp.p, msg->msg.inp.netif);
+      }
+      memp_free(MEMP_TCPIP_MSG_INPKT, msg);
+      break;
+
+#if LWIP_NETIF_API
+    case TCPIP_MSG_NETIFAPI:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: Netif API message %p\n", (void *)msg));
+      msg->msg.netifapimsg->function(&(msg->msg.netifapimsg->msg));
+      break;
+#endif /* LWIP_NETIF_API */
+
+    case TCPIP_MSG_CALLBACK:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg));
+      msg->msg.cb.f(msg->msg.cb.ctx);
+      memp_free(MEMP_TCPIP_MSG_API, msg);
+      break;
+
+    case TCPIP_MSG_TIMEOUT:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: TIMEOUT %p\n", (void *)msg));
+      sys_timeout(msg->msg.tmo.msecs, msg->msg.tmo.h, msg->msg.tmo.arg);
+      memp_free(MEMP_TCPIP_MSG_API, msg);
+      break;
+    case TCPIP_MSG_UNTIMEOUT:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: UNTIMEOUT %p\n", (void *)msg));
+      sys_untimeout(msg->msg.tmo.h, msg->msg.tmo.arg);
+      memp_free(MEMP_TCPIP_MSG_API, msg);
+      break;
+
+    default:
+      break;
+    }
+  }
+}
+
+/**
+ * Pass a received packet to tcpip_thread for input processing
+ *
+ * @param p the received packet, p->payload pointing to the Ethernet header or
+ *          to an IP header (if netif doesn't got NETIF_FLAG_ETHARP flag)
+ * @param inp the network interface on which the packet was received
+ */
+err_t
+tcpip_input(struct pbuf *p, struct netif *inp)
+{
+  struct tcpip_msg *msg;
+
+  if (mbox != SYS_MBOX_NULL) {
+    msg = memp_malloc(MEMP_TCPIP_MSG_INPKT);
+    if (msg == NULL) {
+      return ERR_MEM;
+    }
+
+    msg->type = TCPIP_MSG_INPKT;
+    msg->msg.inp.p = p;
+    msg->msg.inp.netif = inp;
+    if (sys_mbox_trypost(mbox, msg) != ERR_OK) {
+      memp_free(MEMP_TCPIP_MSG_INPKT, msg);
+      return ERR_MEM;
+    }
+    return ERR_OK;
+  }
+  return ERR_VAL;
+}
+
+/**
+ * Call a specific function in the thread context of
+ * tcpip_thread for easy access synchronization.
+ * A function called in that way may access lwIP core code
+ * without fearing concurrent access.
+ *
+ * @param f the function to call
+ * @param ctx parameter passed to f
+ * @param block 1 to block until the request is posted, 0 to non-blocking mode
+ * @return ERR_OK if the function was called, another err_t if not
+ */
+err_t
+tcpip_callback_with_block(void (*f)(void *ctx), void *ctx, u8_t block)
+{
+  struct tcpip_msg *msg;
+
+  if (mbox != SYS_MBOX_NULL) {
+    msg = memp_malloc(MEMP_TCPIP_MSG_API);
+    if (msg == NULL) {
+      return ERR_MEM;
+    }
+
+    msg->type = TCPIP_MSG_CALLBACK;
+    msg->msg.cb.f = f;
+    msg->msg.cb.ctx = ctx;
+    if (block) {
+      sys_mbox_post(mbox, msg);
+    } else {
+      if (sys_mbox_trypost(mbox, msg) != ERR_OK) {
+        memp_free(MEMP_TCPIP_MSG_API, msg);
+        return ERR_MEM;
+      }
+    }
+    return ERR_OK;
+  }
+  return ERR_VAL;
+}
+
+/**
+ * call sys_timeout in tcpip_thread
+ *
+ * @param msec time in miliseconds for timeout
+ * @param h function to be called on timeout
+ * @param arg argument to pass to timeout function h
+ * @return ERR_MEM on memory error, ERR_OK otherwise
+ */
+err_t
+tcpip_timeout(u32_t msecs, sys_timeout_handler h, void *arg)
+{
+  struct tcpip_msg *msg;
+
+  if (mbox != SYS_MBOX_NULL) {
+    msg = memp_malloc(MEMP_TCPIP_MSG_API);
+    if (msg == NULL) {
+      return ERR_MEM;
+    }
+
+    msg->type = TCPIP_MSG_TIMEOUT;
+    msg->msg.tmo.msecs = msecs;
+    msg->msg.tmo.h = h;
+    msg->msg.tmo.arg = arg;
+    sys_mbox_post(mbox, msg);
+    return ERR_OK;
+  }
+  return ERR_VAL;
+}
+
+/**
+ * call sys_untimeout in tcpip_thread
+ *
+ * @param msec time in miliseconds for timeout
+ * @param h function to be called on timeout
+ * @param arg argument to pass to timeout function h
+ * @return ERR_MEM on memory error, ERR_OK otherwise
+ */
+err_t
+tcpip_untimeout(sys_timeout_handler h, void *arg)
+{
+  struct tcpip_msg *msg;
+
+  if (mbox != SYS_MBOX_NULL) {
+    msg = memp_malloc(MEMP_TCPIP_MSG_API);
+    if (msg == NULL) {
+      return ERR_MEM;
+    }
+
+    msg->type = TCPIP_MSG_UNTIMEOUT;
+    msg->msg.tmo.h = h;
+    msg->msg.tmo.arg = arg;
+    sys_mbox_post(mbox, msg);
+    return ERR_OK;
+  }
+  return ERR_VAL;
+}
+
+#if LWIP_NETCONN
+/**
+ * Call the lower part of a netconn_* function
+ * This function is then running in the thread context
+ * of tcpip_thread and has exclusive access to lwIP core code.
+ *
+ * @param apimsg a struct containing the function to call and its parameters
+ * @return ERR_OK if the function was called, another err_t if not
+ */
+err_t
+tcpip_apimsg(struct api_msg *apimsg)
+{
+  struct tcpip_msg msg;
+  
+  if (mbox != SYS_MBOX_NULL) {
+    msg.type = TCPIP_MSG_API;
+    msg.msg.apimsg = apimsg;
+    sys_mbox_post(mbox, &msg);
+    sys_arch_sem_wait(apimsg->msg.conn->op_completed, 0);
+    return ERR_OK;
+  }
+  return ERR_VAL;
+}
+
+#if LWIP_TCPIP_CORE_LOCKING
+/**
+ * Call the lower part of a netconn_* function
+ * This function has exclusive access to lwIP core code by locking it
+ * before the function is called.
+ *
+ * @param apimsg a struct containing the function to call and its parameters
+ * @return ERR_OK (only for compatibility fo tcpip_apimsg())
+ */
+err_t
+tcpip_apimsg_lock(struct api_msg *apimsg)
+{
+  LOCK_TCPIP_CORE();
+  apimsg->function(&(apimsg->msg));
+  UNLOCK_TCPIP_CORE();
+  return ERR_OK;
+
+}
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+#endif /* LWIP_NETCONN */
+
+#if LWIP_NETIF_API
+#if !LWIP_TCPIP_CORE_LOCKING
+/**
+ * Much like tcpip_apimsg, but calls the lower part of a netifapi_*
+ * function.
+ *
+ * @param netifapimsg a struct containing the function to call and its parameters
+ * @return error code given back by the function that was called
+ */
+err_t
+tcpip_netifapi(struct netifapi_msg* netifapimsg)
+{
+  struct tcpip_msg msg;
+  
+  if (mbox != SYS_MBOX_NULL) {
+    netifapimsg->msg.sem = sys_sem_new(0);
+    if (netifapimsg->msg.sem == SYS_SEM_NULL) {
+      netifapimsg->msg.err = ERR_MEM;
+      return netifapimsg->msg.err;
+    }
+    
+    msg.type = TCPIP_MSG_NETIFAPI;
+    msg.msg.netifapimsg = netifapimsg;
+    sys_mbox_post(mbox, &msg);
+    sys_sem_wait(netifapimsg->msg.sem);
+    sys_sem_free(netifapimsg->msg.sem);
+    return netifapimsg->msg.err;
+  }
+  return ERR_VAL;
+}
+#else /* !LWIP_TCPIP_CORE_LOCKING */
+/**
+ * Call the lower part of a netifapi_* function
+ * This function has exclusive access to lwIP core code by locking it
+ * before the function is called.
+ *
+ * @param netifapimsg a struct containing the function to call and its parameters
+ * @return ERR_OK (only for compatibility fo tcpip_netifapi())
+ */
+err_t
+tcpip_netifapi_lock(struct netifapi_msg* netifapimsg)
+{
+  LOCK_TCPIP_CORE();  
+  netifapimsg->function(&(netifapimsg->msg));
+  UNLOCK_TCPIP_CORE();
+  return netifapimsg->msg.err;
+}
+#endif /* !LWIP_TCPIP_CORE_LOCKING */
+#endif /* LWIP_NETIF_API */
+
+/**
+ * Initialize this module:
+ * - initialize all sub modules
+ * - start the tcpip_thread
+ *
+ * @param initfunc a function to call when tcpip_thread is running and finished initializing
+ * @param arg argument to pass to initfunc
+ */
+void
+tcpip_init(void (* initfunc)(void *), void *arg)
+{
+  lwip_init();
+
+  tcpip_init_done = initfunc;
+  tcpip_init_done_arg = arg;
+  mbox = sys_mbox_new(TCPIP_MBOX_SIZE);
+#if LWIP_TCPIP_CORE_LOCKING
+  lock_tcpip_core = sys_sem_new(1);
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+
+  sys_thread_new(TCPIP_THREAD_NAME, tcpip_thread, NULL, TCPIP_THREAD_STACKSIZE, TCPIP_THREAD_PRIO);
+}
+
+/**
+ * Simple callback function used with tcpip_callback to free a pbuf
+ * (pbuf_free has a wrong signature for tcpip_callback)
+ *
+ * @param p The pbuf (chain) to be dereferenced.
+ */
+static void
+pbuf_free_int(void *p)
+{
+  struct pbuf *q = p;
+  pbuf_free(q);
+}
+
+/**
+ * A simple wrapper function that allows you to free a pbuf from interrupt context.
+ *
+ * @param p The pbuf (chain) to be dereferenced.
+ * @return ERR_OK if callback could be enqueued, an err_t if not
+ */
+err_t
+pbuf_free_callback(struct pbuf *p)
+{
+  return tcpip_callback_with_block(pbuf_free_int, p, 0);
+}
+
+/**
+ * A simple wrapper function that allows you to free heap memory from
+ * interrupt context.
+ *
+ * @param m the heap memory to free
+ * @return ERR_OK if callback could be enqueued, an err_t if not
+ */
+err_t
+mem_free_callback(void *m)
+{
+  return tcpip_callback_with_block(mem_free, m, 0);
+}
+
+#endif /* !NO_SYS */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/dhcp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/dhcp.c
new file mode 100644
index 0000000..82068bf
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/dhcp.c
@@ -0,0 +1,1722 @@
+/**
+ * @file
+ * Dynamic Host Configuration Protocol client
+ *
+ */
+
+/*
+ *
+ * Copyright (c) 2001-2004 Leon Woestenberg 
+ * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is a contribution to the lwIP TCP/IP stack.
+ * The Swedish Institute of Computer Science and Adam Dunkels
+ * are specifically granted permission to redistribute this
+ * source code.
+ *
+ * Author: Leon Woestenberg 
+ *
+ * This is a DHCP client for the lwIP TCP/IP stack. It aims to conform
+ * with RFC 2131 and RFC 2132.
+ *
+ * TODO:
+ * - Proper parsing of DHCP messages exploiting file/sname field overloading.
+ * - Add JavaDoc style documentation (API, internals).
+ * - Support for interfaces other than Ethernet (SLIP, PPP, ...)
+ *
+ * Please coordinate changes and requests with Leon Woestenberg
+ * 
+ *
+ * Integration with your code:
+ *
+ * In lwip/dhcp.h
+ * #define DHCP_COARSE_TIMER_SECS (recommended 60 which is a minute)
+ * #define DHCP_FINE_TIMER_MSECS (recommended 500 which equals TCP coarse timer)
+ *
+ * Then have your application call dhcp_coarse_tmr() and
+ * dhcp_fine_tmr() on the defined intervals.
+ *
+ * dhcp_start(struct netif *netif);
+ * starts a DHCP client instance which configures the interface by
+ * obtaining an IP address lease and maintaining it.
+ *
+ * Use dhcp_release(netif) to end the lease and use dhcp_stop(netif)
+ * to remove the DHCP client.
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_DHCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+#include "lwip/udp.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/inet.h"
+#include "lwip/sys.h"
+#include "lwip/dhcp.h"
+#include "lwip/autoip.h"
+#include "lwip/dns.h"
+#include "netif/etharp.h"
+
+#include 
+
+/** Default for DHCP_GLOBAL_XID is 0xABCD0000
+ * This can be changed by defining DHCP_GLOBAL_XID and DHCP_GLOBAL_XID_HEADER, e.g.
+ *  #define DHCP_GLOBAL_XID_HEADER "stdlib.h"
+ *  #define DHCP_GLOBAL_XID rand()
+ */
+#ifdef DHCP_GLOBAL_XID_HEADER
+#include DHCP_GLOBAL_XID_HEADER /* include optional starting XID generation prototypes */
+#endif
+
+/** DHCP_OPTION_MAX_MSG_SIZE is set to the MTU
+ * MTU is checked to be big enough in dhcp_start */
+#define DHCP_MAX_MSG_LEN(netif)        (netif->mtu)
+#define DHCP_MAX_MSG_LEN_MIN_REQUIRED  576
+/** Minimum length for reply before packet is parsed */
+#define DHCP_MIN_REPLY_LEN             44
+
+#define REBOOT_TRIES 2
+
+/* DHCP client state machine functions */
+static void dhcp_handle_ack(struct netif *netif);
+static void dhcp_handle_nak(struct netif *netif);
+static void dhcp_handle_offer(struct netif *netif);
+
+static err_t dhcp_discover(struct netif *netif);
+static err_t dhcp_select(struct netif *netif);
+static void dhcp_bind(struct netif *netif);
+#if DHCP_DOES_ARP_CHECK
+static void dhcp_check(struct netif *netif);
+static err_t dhcp_decline(struct netif *netif);
+#endif /* DHCP_DOES_ARP_CHECK */
+static err_t dhcp_rebind(struct netif *netif);
+static err_t dhcp_reboot(struct netif *netif);
+static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state);
+
+/* receive, unfold, parse and free incoming messages */
+static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port);
+static err_t dhcp_unfold_reply(struct dhcp *dhcp, struct pbuf *p);
+static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type);
+static u8_t dhcp_get_option_byte(u8_t *ptr);
+#if 0
+static u16_t dhcp_get_option_short(u8_t *ptr);
+#endif
+static u32_t dhcp_get_option_long(u8_t *ptr);
+static void dhcp_free_reply(struct dhcp *dhcp);
+
+/* set the DHCP timers */
+static void dhcp_timeout(struct netif *netif);
+static void dhcp_t1_timeout(struct netif *netif);
+static void dhcp_t2_timeout(struct netif *netif);
+
+/* build outgoing messages */
+/* create a DHCP request, fill in common headers */
+static err_t dhcp_create_request(struct netif *netif);
+/* free a DHCP request */
+static void dhcp_delete_request(struct netif *netif);
+/* add a DHCP option (type, then length in bytes) */
+static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len);
+/* add option values */
+static void dhcp_option_byte(struct dhcp *dhcp, u8_t value);
+static void dhcp_option_short(struct dhcp *dhcp, u16_t value);
+static void dhcp_option_long(struct dhcp *dhcp, u32_t value);
+/* always add the DHCP options trailer to end and pad */
+static void dhcp_option_trailer(struct dhcp *dhcp);
+
+/**
+ * Back-off the DHCP client (because of a received NAK response).
+ *
+ * Back-off the DHCP client because of a received NAK. Receiving a
+ * NAK means the client asked for something non-sensible, for
+ * example when it tries to renew a lease obtained on another network.
+ *
+ * We clear any existing set IP address and restart DHCP negotiation
+ * afresh (as per RFC2131 3.2.3).
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_handle_nak(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_nak(netif=%p) %c%c%"U16_F"\n", 
+    (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+  /* Set the interface down since the address must no longer be used, as per RFC2131 */
+  netif_set_down(netif);
+  /* remove IP address from interface */
+  netif_set_ipaddr(netif, IP_ADDR_ANY);
+  netif_set_gw(netif, IP_ADDR_ANY);
+  netif_set_netmask(netif, IP_ADDR_ANY); 
+  /* Change to a defined state */
+  dhcp_set_state(dhcp, DHCP_BACKING_OFF);
+  /* We can immediately restart discovery */
+  dhcp_discover(netif);
+}
+
+#if DHCP_DOES_ARP_CHECK
+/**
+ * Checks if the offered IP address is already in use.
+ *
+ * It does so by sending an ARP request for the offered address and
+ * entering CHECKING state. If no ARP reply is received within a small
+ * interval, the address is assumed to be free for use by us.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_check(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (s16_t)netif->name[0],
+    (s16_t)netif->name[1]));
+  dhcp_set_state(dhcp, DHCP_CHECKING);
+  /* create an ARP query for the offered IP address, expecting that no host
+     responds, as the IP address should not be in use. */
+  result = etharp_query(netif, &dhcp->offered_ip_addr, NULL);
+  if (result != ERR_OK) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_check: could not perform ARP query\n"));
+  }
+  dhcp->tries++;
+  msecs = 500;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_check(): set request timeout %"U16_F" msecs\n", msecs));
+}
+#endif /* DHCP_DOES_ARP_CHECK */
+
+/**
+ * Remember the configuration offered by a DHCP server.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_handle_offer(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  /* obtain the server address */
+  u8_t *option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SERVER_ID);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_offer(netif=%p) %c%c%"U16_F"\n",
+    (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+  if (option_ptr != NULL) {
+    dhcp->server_ip_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): server 0x%08"X32_F"\n", dhcp->server_ip_addr.addr));
+    /* remember offered address */
+    ip_addr_set(&dhcp->offered_ip_addr, (struct ip_addr *)&dhcp->msg_in->yiaddr);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08"X32_F"\n", dhcp->offered_ip_addr.addr));
+
+    dhcp_select(netif);
+  }
+}
+
+/**
+ * Select a DHCP server offer out of all offers.
+ *
+ * Simply select the first offer received.
+ *
+ * @param netif the netif under DHCP control
+ * @return lwIP specific error (see error.h)
+ */
+static err_t
+dhcp_select(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+#if LWIP_NETIF_HOSTNAME
+  const char *p;
+#endif /* LWIP_NETIF_HOSTNAME */
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_select(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+  dhcp_set_state(dhcp, DHCP_REQUESTING);
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_REQUEST);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif));
+
+    /* MUST request the offered IP address */
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+
+    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
+
+    dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/);
+    dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK);
+    dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER);
+    dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST);
+    dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER);
+
+#if LWIP_NETIF_HOSTNAME
+    p = (const char*)netif->hostname;
+    if (p != NULL) {
+      dhcp_option(dhcp, DHCP_OPTION_HOSTNAME, strlen(p));
+      while (*p) {
+        dhcp_option_byte(dhcp, *p++);
+      }
+    }
+#endif /* LWIP_NETIF_HOSTNAME */
+
+    dhcp_option_trailer(dhcp);
+    /* shrink the pbuf to the actual content length */
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    /* send broadcast to any DHCP server */
+    udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_select: REQUESTING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_select: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = (dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_select(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+/**
+ * The DHCP timer that checks for lease renewal/rebind timeouts.
+ *
+ */
+void
+dhcp_coarse_tmr()
+{
+  struct netif *netif = netif_list;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_coarse_tmr()\n"));
+  /* iterate through all network interfaces */
+  while (netif != NULL) {
+    /* only act on DHCP configured interfaces */
+    if (netif->dhcp != NULL) {
+      /* timer is active (non zero), and triggers (zeroes) now? */
+      if (netif->dhcp->t2_timeout-- == 1) {
+        LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n"));
+        /* this clients' rebind timeout triggered */
+        dhcp_t2_timeout(netif);
+      /* timer is active (non zero), and triggers (zeroes) now */
+      } else if (netif->dhcp->t1_timeout-- == 1) {
+        LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n"));
+        /* this clients' renewal timeout triggered */
+        dhcp_t1_timeout(netif);
+      }
+    }
+    /* proceed to next netif */
+    netif = netif->next;
+  }
+}
+
+/**
+ * DHCP transaction timeout handling
+ *
+ * A DHCP server is expected to respond within a short period of time.
+ * This timer checks whether an outstanding DHCP request is timed out.
+ * 
+ */
+void
+dhcp_fine_tmr()
+{
+  struct netif *netif = netif_list;
+  /* loop through netif's */
+  while (netif != NULL) {
+    /* only act on DHCP configured interfaces */
+    if (netif->dhcp != NULL) {
+      /* timer is active (non zero), and is about to trigger now */      
+      if (netif->dhcp->request_timeout > 1) {
+        netif->dhcp->request_timeout--;
+      }
+      else if (netif->dhcp->request_timeout == 1) {
+        netif->dhcp->request_timeout--;
+        /* { netif->dhcp->request_timeout == 0 } */
+        LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_fine_tmr(): request timeout\n"));
+        /* this clients' request timeout triggered */
+        dhcp_timeout(netif);
+      }
+    }
+    /* proceed to next network interface */
+    netif = netif->next;
+  }
+}
+
+/**
+ * A DHCP negotiation transaction, or ARP request, has timed out.
+ *
+ * The timer that was started with the DHCP or ARP request has
+ * timed out, indicating no response was received in time.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout()\n"));
+  /* back-off period has passed, or server selection timed out */
+  if ((dhcp->state == DHCP_BACKING_OFF) || (dhcp->state == DHCP_SELECTING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout(): restarting discovery\n"));
+    dhcp_discover(netif);
+  /* receiving the requested lease timed out */
+  } else if (dhcp->state == DHCP_REQUESTING) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): REQUESTING, DHCP request timed out\n"));
+    if (dhcp->tries <= 5) {
+      dhcp_select(netif);
+    } else {
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): REQUESTING, releasing, restarting\n"));
+      dhcp_release(netif);
+      dhcp_discover(netif);
+    }
+#if DHCP_DOES_ARP_CHECK
+  /* received no ARP reply for the offered address (which is good) */
+  } else if (dhcp->state == DHCP_CHECKING) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): CHECKING, ARP request timed out\n"));
+    if (dhcp->tries <= 1) {
+      dhcp_check(netif);
+    /* no ARP replies on the offered address,
+       looks like the IP address is indeed free */
+    } else {
+      /* bind the interface to the offered address */
+      dhcp_bind(netif);
+    }
+#endif /* DHCP_DOES_ARP_CHECK */
+  }
+  /* did not get response to renew request? */
+  else if (dhcp->state == DHCP_RENEWING) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): RENEWING, DHCP request timed out\n"));
+    /* just retry renewal */
+    /* note that the rebind timer will eventually time-out if renew does not work */
+    dhcp_renew(netif);
+  /* did not get response to rebind request? */
+  } else if (dhcp->state == DHCP_REBINDING) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): REBINDING, DHCP request timed out\n"));
+    if (dhcp->tries <= 8) {
+      dhcp_rebind(netif);
+    } else {
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): RELEASING, DISCOVERING\n"));
+      dhcp_release(netif);
+      dhcp_discover(netif);
+    }
+  } else if (dhcp->state == DHCP_REBOOTING) {
+    if (dhcp->tries < REBOOT_TRIES) {
+      dhcp_reboot(netif);
+    } else {
+      dhcp_discover(netif);
+    }
+  }
+}
+
+/**
+ * The renewal period has timed out.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_t1_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_t1_timeout()\n"));
+  if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) {
+    /* just retry to renew - note that the rebind timer (t2) will
+     * eventually time-out if renew tries fail. */
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_t1_timeout(): must renew\n"));
+    dhcp_renew(netif);
+  }
+}
+
+/**
+ * The rebind period has timed out.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_t2_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_t2_timeout()\n"));
+  if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) {
+    /* just retry to rebind */
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_t2_timeout(): must rebind\n"));
+    dhcp_rebind(netif);
+  }
+}
+
+/**
+ * Handle a DHCP ACK packet
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_handle_ack(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  u8_t *option_ptr;
+  /* clear options we might not get from the ACK */
+  dhcp->offered_sn_mask.addr = 0;
+  dhcp->offered_gw_addr.addr = 0;
+  dhcp->offered_bc_addr.addr = 0;
+
+  /* lease time given? */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_LEASE_TIME);
+  if (option_ptr != NULL) {
+    /* remember offered lease time */
+    dhcp->offered_t0_lease = dhcp_get_option_long(option_ptr + 2);
+  }
+  /* renewal period given? */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T1);
+  if (option_ptr != NULL) {
+    /* remember given renewal period */
+    dhcp->offered_t1_renew = dhcp_get_option_long(option_ptr + 2);
+  } else {
+    /* calculate safe periods for renewal */
+    dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2;
+  }
+
+  /* renewal period given? */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T2);
+  if (option_ptr != NULL) {
+    /* remember given rebind period */
+    dhcp->offered_t2_rebind = dhcp_get_option_long(option_ptr + 2);
+  } else {
+    /* calculate safe periods for rebinding */
+    dhcp->offered_t2_rebind = dhcp->offered_t0_lease;
+  }
+
+  /* (y)our internet address */
+  ip_addr_set(&dhcp->offered_ip_addr, &dhcp->msg_in->yiaddr);
+
+/**
+ * Patch #1308
+ * TODO: we must check if the file field is not overloaded by DHCP options!
+ */
+#if 0
+  /* boot server address */
+  ip_addr_set(&dhcp->offered_si_addr, &dhcp->msg_in->siaddr);
+  /* boot file name */
+  if (dhcp->msg_in->file[0]) {
+    dhcp->boot_file_name = mem_malloc(strlen(dhcp->msg_in->file) + 1);
+    strcpy(dhcp->boot_file_name, dhcp->msg_in->file);
+  }
+#endif
+
+  /* subnet mask */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SUBNET_MASK);
+  /* subnet mask given? */
+  if (option_ptr != NULL) {
+    dhcp->offered_sn_mask.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+  }
+
+  /* gateway router */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_ROUTER);
+  if (option_ptr != NULL) {
+    dhcp->offered_gw_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+  }
+
+  /* broadcast address */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_BROADCAST);
+  if (option_ptr != NULL) {
+    dhcp->offered_bc_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+  }
+  
+  /* DNS servers */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_DNS_SERVER);
+  if (option_ptr != NULL) {
+    u8_t n;
+    dhcp->dns_count = dhcp_get_option_byte(&option_ptr[1]) / (u32_t)sizeof(struct ip_addr);
+    /* limit to at most DHCP_MAX_DNS DNS servers */
+    if (dhcp->dns_count > DHCP_MAX_DNS)
+      dhcp->dns_count = DHCP_MAX_DNS;
+    for (n = 0; n < dhcp->dns_count; n++) {
+      dhcp->offered_dns_addr[n].addr = htonl(dhcp_get_option_long(&option_ptr[2 + n * 4]));
+#if LWIP_DNS
+      dns_setserver( n, (struct ip_addr *)(&(dhcp->offered_dns_addr[n].addr)));
+#endif /* LWIP_DNS */
+    }
+#if LWIP_DNS
+    dns_setserver( n, (struct ip_addr *)(&ip_addr_any));
+#endif /* LWIP_DNS */
+  }
+}
+
+/**
+ * Start DHCP negotiation for a network interface.
+ *
+ * If no DHCP client instance was attached to this interface,
+ * a new client is created first. If a DHCP client instance
+ * was already present, it restarts negotiation.
+ *
+ * @param netif The lwIP network interface
+ * @return lwIP error code
+ * - ERR_OK - No error
+ * - ERR_MEM - Out of memory
+ */
+err_t
+dhcp_start(struct netif *netif)
+{
+  struct dhcp *dhcp;
+  err_t result = ERR_OK;
+
+  LWIP_ERROR("netif != NULL", (netif != NULL), return ERR_ARG;);
+  dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+  /* Remove the flag that says this netif is handled by DHCP,
+     it is set when we succeeded starting. */
+  netif->flags &= ~NETIF_FLAG_DHCP;
+
+  /* check MTU of the netif */
+  if (netif->mtu < DHCP_MAX_MSG_LEN_MIN_REQUIRED) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): Cannot use this netif with DHCP: MTU is too small\n"));
+    return ERR_MEM;
+  }
+
+  /* no DHCP client attached yet? */
+  if (dhcp == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): starting new DHCP client\n"));
+    dhcp = mem_malloc(sizeof(struct dhcp));
+    if (dhcp == NULL) {
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n"));
+      return ERR_MEM;
+    }
+    /* store this dhcp client in the netif */
+    netif->dhcp = dhcp;
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): allocated dhcp"));
+  /* already has DHCP client attached */
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(): restarting DHCP configuration\n"));
+    if (dhcp->pcb != NULL) {
+      udp_remove(dhcp->pcb);
+    }
+    LWIP_ASSERT("pbuf p_out wasn't freed", dhcp->p_out == NULL);
+    LWIP_ASSERT("reply wasn't freed", dhcp->msg_in == NULL &&
+      dhcp->options_in == NULL && dhcp->options_in_len == 0);
+  }
+    
+  /* clear data structure */
+  memset(dhcp, 0, sizeof(struct dhcp));
+  /* allocate UDP PCB */
+  dhcp->pcb = udp_new();
+  if (dhcp->pcb == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG  | LWIP_DBG_TRACE, ("dhcp_start(): could not obtain pcb\n"));
+    mem_free((void *)dhcp);
+    netif->dhcp = dhcp = NULL;
+    return ERR_MEM;
+  }
+#if IP_SOF_BROADCAST
+  dhcp->pcb->so_options|=SOF_BROADCAST;
+#endif /* IP_SOF_BROADCAST */
+  /* set up local and remote port for the pcb */
+  udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+  udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+  /* set up the recv callback and argument */
+  udp_recv(dhcp->pcb, dhcp_recv, netif);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n"));
+  /* (re)start the DHCP negotiation */
+  result = dhcp_discover(netif);
+  if (result != ERR_OK) {
+    /* free resources allocated above */
+    dhcp_stop(netif);
+    return ERR_MEM;
+  }
+  /* Set the flag that says this netif is handled by DHCP. */
+  netif->flags |= NETIF_FLAG_DHCP;
+  return result;
+}
+
+/**
+ * Inform a DHCP server of our manual configuration.
+ *
+ * This informs DHCP servers of our fixed IP address configuration
+ * by sending an INFORM message. It does not involve DHCP address
+ * configuration, it is just here to be nice to the network.
+ *
+ * @param netif The lwIP network interface
+ */
+void
+dhcp_inform(struct netif *netif)
+{
+  struct dhcp *dhcp, *old_dhcp;
+  err_t result = ERR_OK;
+  dhcp = mem_malloc(sizeof(struct dhcp));
+  if (dhcp == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_inform(): could not allocate dhcp\n"));
+    return;
+  }
+  memset(dhcp, 0, sizeof(struct dhcp));
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_inform(): allocated dhcp\n"));
+  dhcp->pcb = udp_new();
+  if (dhcp->pcb == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_inform(): could not obtain pcb"));
+    goto free_dhcp_and_return;
+  }
+  old_dhcp = netif->dhcp;
+  netif->dhcp = dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_inform(): created new udp pcb\n"));
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_INFORM);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif));
+
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+#if IP_SOF_BROADCAST
+    dhcp->pcb->so_options|=SOF_BROADCAST;
+#endif /* IP_SOF_BROADCAST */
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_inform: INFORMING\n"));
+    udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif);
+    dhcp_delete_request(netif);
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_inform: could not allocate DHCP request\n"));
+  }
+
+  udp_remove(dhcp->pcb);
+  dhcp->pcb = NULL;
+  netif->dhcp = old_dhcp;
+free_dhcp_and_return:
+  mem_free((void *)dhcp);
+}
+
+/** Handle a possible change in the network configuration.
+ *
+ * This enters the REBOOTING state to verify that the currently bound
+ * address is still valid.
+ */
+void
+dhcp_network_changed(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  if (!dhcp)
+    return;
+  switch (dhcp->state) {
+  case DHCP_REBINDING:
+  case DHCP_RENEWING:
+  case DHCP_BOUND:
+  case DHCP_REBOOTING:
+    netif_set_down(netif);
+    dhcp->tries = 0;
+    dhcp_reboot(netif);
+    break;
+  case DHCP_OFF:
+    /* stay off */
+    break;
+  default:
+    dhcp->tries = 0;
+    dhcp_discover(netif);
+    break;
+  }
+}
+
+#if DHCP_DOES_ARP_CHECK
+/**
+ * Match an ARP reply with the offered IP address.
+ *
+ * @param netif the network interface on which the reply was received
+ * @param addr The IP address we received a reply from
+ */
+void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr)
+{
+  LWIP_ERROR("netif != NULL", (netif != NULL), return;);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_arp_reply()\n"));
+  /* is a DHCP client doing an ARP check? */
+  if ((netif->dhcp != NULL) && (netif->dhcp->state == DHCP_CHECKING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08"X32_F"\n", addr->addr));
+    /* did a host respond with the address we
+       were offered by the DHCP server? */
+    if (ip_addr_cmp(addr, &netif->dhcp->offered_ip_addr)) {
+      /* we will not accept the offered address */
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING,
+        ("dhcp_arp_reply(): arp reply matched with offered address, declining\n"));
+      dhcp_decline(netif);
+    }
+  }
+}
+
+/**
+ * Decline an offered lease.
+ *
+ * Tell the DHCP server we do not accept the offered address.
+ * One reason to decline the lease is when we find out the address
+ * is already in use by another host (through ARP).
+ *
+ * @param netif the netif under DHCP control
+ */
+static err_t
+dhcp_decline(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result = ERR_OK;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline()\n"));
+  dhcp_set_state(dhcp, DHCP_BACKING_OFF);
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_DECLINE);
+
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+
+    dhcp_option_trailer(dhcp);
+    /* resize pbuf to reflect true size of options */
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    /* per section 4.4.4, broadcast DECLINE messages */
+    udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_decline: BACKING OFF\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
+      ("dhcp_decline: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = 10*1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+#endif
+
+
+/**
+ * Start the DHCP process, discover a DHCP server.
+ *
+ * @param netif the netif under DHCP control
+ */
+static err_t
+dhcp_discover(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result = ERR_OK;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover()\n"));
+  ip_addr_set(&dhcp->offered_ip_addr, IP_ADDR_ANY);
+  dhcp_set_state(dhcp, DHCP_SELECTING);
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: making request\n"));
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_DISCOVER);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif));
+
+    dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/);
+    dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK);
+    dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER);
+    dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST);
+    dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER);
+
+    dhcp_option_trailer(dhcp);
+
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: realloc()ing\n"));
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, DHCP_SERVER_PORT)\n"));
+    udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: deleting()ing\n"));
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover: SELECTING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_discover: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+#if LWIP_DHCP_AUTOIP_COOP
+  if(dhcp->tries >= LWIP_DHCP_AUTOIP_COOP_TRIES && dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_OFF) {
+    dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_ON;
+    autoip_start(netif);
+  }
+#endif /* LWIP_DHCP_AUTOIP_COOP */
+  msecs = (dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+
+/**
+ * Bind the interface to the offered IP address.
+ *
+ * @param netif network interface to bind to the offered address
+ */
+static void
+dhcp_bind(struct netif *netif)
+{
+  u32_t timeout;
+  struct dhcp *dhcp;
+  struct ip_addr sn_mask, gw_addr;
+  LWIP_ERROR("dhcp_bind: netif != NULL", (netif != NULL), return;);
+  dhcp = netif->dhcp;
+  LWIP_ERROR("dhcp_bind: dhcp != NULL", (dhcp != NULL), return;);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+
+  /* temporary DHCP lease? */
+  if (dhcp->offered_t1_renew != 0xffffffffUL) {
+    /* set renewal period timer */
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t1 renewal timer %"U32_F" secs\n", dhcp->offered_t1_renew));
+    timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
+    if(timeout > 0xffff) {
+      timeout = 0xffff;
+    }
+    dhcp->t1_timeout = (u16_t)timeout;
+    if (dhcp->t1_timeout == 0) {
+      dhcp->t1_timeout = 1;
+    }
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t1_renew*1000));
+  }
+  /* set renewal period timer */
+  if (dhcp->offered_t2_rebind != 0xffffffffUL) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t2 rebind timer %"U32_F" secs\n", dhcp->offered_t2_rebind));
+    timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
+    if(timeout > 0xffff) {
+      timeout = 0xffff;
+    }
+    dhcp->t2_timeout = (u16_t)timeout;
+    if (dhcp->t2_timeout == 0) {
+      dhcp->t2_timeout = 1;
+    }
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t2_rebind*1000));
+  }
+  /* copy offered network mask */
+  ip_addr_set(&sn_mask, &dhcp->offered_sn_mask);
+
+  /* subnet mask not given? */
+  /* TODO: this is not a valid check. what if the network mask is 0? */
+  if (sn_mask.addr == 0) {
+    /* choose a safe subnet mask given the network class */
+    u8_t first_octet = ip4_addr1(&sn_mask);
+    if (first_octet <= 127) {
+      sn_mask.addr = htonl(0xff000000);
+    } else if (first_octet >= 192) {
+      sn_mask.addr = htonl(0xffffff00);
+    } else {
+      sn_mask.addr = htonl(0xffff0000);
+    }
+  }
+
+  ip_addr_set(&gw_addr, &dhcp->offered_gw_addr);
+  /* gateway address not given? */
+  if (gw_addr.addr == 0) {
+    /* copy network address */
+    gw_addr.addr = (dhcp->offered_ip_addr.addr & sn_mask.addr);
+    /* use first host address on network as gateway */
+    gw_addr.addr |= htonl(0x00000001);
+  }
+
+#if LWIP_DHCP_AUTOIP_COOP
+  if(dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_ON) {
+    autoip_stop(netif);
+    dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF;
+  }
+#endif /* LWIP_DHCP_AUTOIP_COOP */
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): IP: 0x%08"X32_F"\n", dhcp->offered_ip_addr.addr));
+  netif_set_ipaddr(netif, &dhcp->offered_ip_addr);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): SN: 0x%08"X32_F"\n", sn_mask.addr));
+  netif_set_netmask(netif, &sn_mask);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): GW: 0x%08"X32_F"\n", gw_addr.addr));
+  netif_set_gw(netif, &gw_addr);
+  /* bring the interface up */
+  netif_set_up(netif);
+  /* netif is now bound to DHCP leased address */
+  dhcp_set_state(dhcp, DHCP_BOUND);
+}
+
+/**
+ * Renew an existing DHCP lease at the involved DHCP server.
+ *
+ * @param netif network interface which must renew its lease
+ */
+err_t
+dhcp_renew(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+#if LWIP_NETIF_HOSTNAME
+  const char *p;
+#endif /* LWIP_NETIF_HOSTNAME */
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_renew()\n"));
+  dhcp_set_state(dhcp, DHCP_RENEWING);
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_REQUEST);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif));
+
+#if LWIP_NETIF_HOSTNAME
+    p = (const char*)netif->hostname;
+    if (p != NULL) {
+      dhcp_option(dhcp, DHCP_OPTION_HOSTNAME, strlen(p));
+      while (*p) {
+        dhcp_option_byte(dhcp, *p++);
+      }
+    }
+#endif /* LWIP_NETIF_HOSTNAME */
+
+#if 0
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+#endif
+
+#if 0
+    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
+#endif
+    /* append DHCP message trailer */
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_sendto_if(dhcp->pcb, dhcp->p_out, &dhcp->server_ip_addr, DHCP_SERVER_PORT, netif);
+    dhcp_delete_request(netif);
+
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew: RENEWING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_renew: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  /* back-off on retries, but to a maximum of 20 seconds */
+  msecs = dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+/**
+ * Rebind with a DHCP server for an existing DHCP lease.
+ *
+ * @param netif network interface which must rebind with a DHCP server
+ */
+static err_t
+dhcp_rebind(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+#if LWIP_NETIF_HOSTNAME
+  const char *p;
+#endif /* LWIP_NETIF_HOSTNAME */
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind()\n"));
+  dhcp_set_state(dhcp, DHCP_REBINDING);
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_REQUEST);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif));
+
+#if LWIP_NETIF_HOSTNAME
+    p = (const char*)netif->hostname;
+    if (p != NULL) {
+      dhcp_option(dhcp, DHCP_OPTION_HOSTNAME, strlen(p));
+      while (*p) {
+        dhcp_option_byte(dhcp, *p++);
+      }
+    }
+#endif /* LWIP_NETIF_HOSTNAME */
+
+#if 0
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+
+    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
+#endif
+
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    /* broadcast to server */
+    udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind: REBINDING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_rebind: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+/**
+ * Enter REBOOTING state to verify an existing lease
+ *
+ * @param netif network interface which must reboot
+ */
+static err_t
+dhcp_reboot(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot()\n"));
+  dhcp_set_state(dhcp, DHCP_REBOOTING);
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_REQUEST);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, 576);
+
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    /* broadcast to server */
+    udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot: REBOOTING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_reboot: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+
+/**
+ * Release a DHCP lease.
+ *
+ * @param netif network interface which must release its lease
+ */
+err_t
+dhcp_release(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_release()\n"));
+
+  /* idle DHCP client */
+  dhcp_set_state(dhcp, DHCP_OFF);
+  /* clean old DHCP offer */
+  dhcp->server_ip_addr.addr = 0;
+  dhcp->offered_ip_addr.addr = dhcp->offered_sn_mask.addr = 0;
+  dhcp->offered_gw_addr.addr = dhcp->offered_bc_addr.addr = 0;
+  dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0;
+  dhcp->dns_count = 0;
+  
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_RELEASE);
+
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_sendto_if(dhcp->pcb, dhcp->p_out, &dhcp->server_ip_addr, DHCP_SERVER_PORT, netif);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_release: RELEASED, DHCP_OFF\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_release: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_release(): set request timeout %"U16_F" msecs\n", msecs));
+  /* bring the interface down */
+  netif_set_down(netif);
+  /* remove IP address from interface */
+  netif_set_ipaddr(netif, IP_ADDR_ANY);
+  netif_set_gw(netif, IP_ADDR_ANY);
+  netif_set_netmask(netif, IP_ADDR_ANY);
+  
+  /* TODO: netif_down(netif); */
+  return result;
+}
+
+/**
+ * Remove the DHCP client from the interface.
+ *
+ * @param netif The network interface to stop DHCP on
+ */
+void
+dhcp_stop(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_ERROR("dhcp_stop: netif != NULL", (netif != NULL), return;);
+  /* Remove the flag that says this netif is handled by DHCP. */
+  netif->flags &= ~NETIF_FLAG_DHCP;
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_stop()\n"));
+  /* netif is DHCP configured? */
+  if (dhcp != NULL) {
+#if LWIP_DHCP_AUTOIP_COOP
+  if(dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_ON) {
+    autoip_stop(netif);
+    dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF;
+  }
+#endif /* LWIP_DHCP_AUTOIP_COOP */
+
+    if (dhcp->pcb != NULL) {
+      udp_remove(dhcp->pcb);
+      dhcp->pcb = NULL;
+    }
+    LWIP_ASSERT("reply wasn't freed", dhcp->msg_in == NULL &&
+      dhcp->options_in == NULL && dhcp->options_in_len == 0);
+    mem_free((void *)dhcp);
+    netif->dhcp = NULL;
+  }
+}
+
+/*
+ * Set the DHCP state of a DHCP client.
+ *
+ * If the state changed, reset the number of tries.
+ *
+ * TODO: we might also want to reset the timeout here?
+ */
+static void
+dhcp_set_state(struct dhcp *dhcp, u8_t new_state)
+{
+  if (new_state != dhcp->state) {
+    dhcp->state = new_state;
+    dhcp->tries = 0;
+  }
+}
+
+/*
+ * Concatenate an option type and length field to the outgoing
+ * DHCP message.
+ *
+ */
+static void
+dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len)
+{
+  LWIP_ASSERT("dhcp_option: dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2U + option_len <= DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = option_type;
+  dhcp->msg_out->options[dhcp->options_out_len++] = option_len;
+}
+/*
+ * Concatenate a single byte to the outgoing DHCP message.
+ *
+ */
+static void
+dhcp_option_byte(struct dhcp *dhcp, u8_t value)
+{
+  LWIP_ASSERT("dhcp_option_byte: dhcp->options_out_len < DHCP_OPTIONS_LEN", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = value;
+}
+
+static void
+dhcp_option_short(struct dhcp *dhcp, u16_t value)
+{
+  LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2U <= DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0xff00U) >> 8);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t) (value & 0x00ffU);
+}
+
+static void
+dhcp_option_long(struct dhcp *dhcp, u32_t value)
+{
+  LWIP_ASSERT("dhcp_option_long: dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 4U <= DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0xff000000UL) >> 24);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0x00ff0000UL) >> 16);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0x0000ff00UL) >> 8);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0x000000ffUL));
+}
+
+/**
+ * Extract the DHCP message and the DHCP options.
+ *
+ * Extract the DHCP message and the DHCP options, each into a contiguous
+ * piece of memory. As a DHCP message is variable sized by its options,
+ * and also allows overriding some fields for options, the easy approach
+ * is to first unfold the options into a conitguous piece of memory, and
+ * use that further on.
+ *
+ */
+static err_t
+dhcp_unfold_reply(struct dhcp *dhcp, struct pbuf *p)
+{
+  u16_t ret;
+  LWIP_ERROR("dhcp != NULL", (dhcp != NULL), return ERR_ARG;);
+  /* free any left-overs from previous unfolds */
+  dhcp_free_reply(dhcp);
+  /* options present? */
+  if (p->tot_len > (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN)) {
+    dhcp->options_in_len = p->tot_len - (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN);
+    dhcp->options_in = mem_malloc(dhcp->options_in_len);
+    if (dhcp->options_in == NULL) {
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
+        ("dhcp_unfold_reply(): could not allocate dhcp->options\n"));
+      dhcp->options_in_len = 0;
+      return ERR_MEM;
+    }
+  }
+  dhcp->msg_in = mem_malloc(sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN);
+  if (dhcp->msg_in == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
+      ("dhcp_unfold_reply(): could not allocate dhcp->msg_in\n"));
+    if (dhcp->options_in != NULL) {
+      mem_free(dhcp->options_in);
+      dhcp->options_in = NULL;
+      dhcp->options_in_len = 0;
+    }
+    return ERR_MEM;
+  }
+
+  /** copy the DHCP message without options */
+  ret = pbuf_copy_partial(p, dhcp->msg_in, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN, 0);
+  LWIP_ASSERT("ret == sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN", ret == sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_unfold_reply(): copied %"U16_F" bytes into dhcp->msg_in[]\n",
+     sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN));
+
+  if (dhcp->options_in != NULL) {
+    /** copy the DHCP options */
+    ret = pbuf_copy_partial(p, dhcp->options_in, dhcp->options_in_len, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN);
+    LWIP_ASSERT("ret == dhcp->options_in_len", ret == dhcp->options_in_len);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_unfold_reply(): copied %"U16_F" bytes to dhcp->options_in[]\n",
+      dhcp->options_in_len));
+  }
+  LWIP_UNUSED_ARG(ret);
+  return ERR_OK;
+}
+
+/**
+ * Free the incoming DHCP message including contiguous copy of
+ * its DHCP options.
+ */
+static void dhcp_free_reply(struct dhcp *dhcp)
+{
+  if (dhcp->msg_in != NULL) {
+    mem_free((void *)dhcp->msg_in);
+    dhcp->msg_in = NULL;
+  }
+  if (dhcp->options_in) {
+    mem_free(dhcp->options_in);
+    dhcp->options_in = NULL;
+    dhcp->options_in_len = 0;
+  }
+  LWIP_DEBUGF(DHCP_DEBUG, ("dhcp_free_reply(): free'd\n"));
+}
+
+/**
+ * If an incoming DHCP message is in response to us, then trigger the state machine
+ */
+static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port)
+{
+  struct netif *netif = (struct netif *)arg;
+  struct dhcp *dhcp = netif->dhcp;
+  struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload;
+  u8_t *options_ptr;
+  u8_t msg_type;
+  u8_t i;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_recv(pbuf = %p) from DHCP server %"U16_F".%"U16_F".%"U16_F".%"U16_F" port %"U16_F"\n", (void*)p,
+    (u16_t)(ntohl(addr->addr) >> 24 & 0xff), (u16_t)(ntohl(addr->addr) >> 16 & 0xff),
+    (u16_t)(ntohl(addr->addr) >>  8 & 0xff), (u16_t)(ntohl(addr->addr) & 0xff), port));
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("pbuf->len = %"U16_F"\n", p->len));
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("pbuf->tot_len = %"U16_F"\n", p->tot_len));
+  /* prevent warnings about unused arguments */
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_UNUSED_ARG(addr);
+  LWIP_UNUSED_ARG(port);
+
+  LWIP_ASSERT("reply wasn't freed", dhcp->msg_in == NULL &&
+    dhcp->options_in == NULL && dhcp->options_in_len == 0);
+
+  if (p->len < DHCP_MIN_REPLY_LEN) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP reply message too short\n"));
+    goto free_pbuf_and_return;
+  }
+
+  if (reply_msg->op != DHCP_BOOTREPLY) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("not a DHCP reply message, but type %"U16_F"\n", (u16_t)reply_msg->op));
+    goto free_pbuf_and_return;
+  }
+  /* iterate through hardware address and match against DHCP message */
+  for (i = 0; i < netif->hwaddr_len; i++) {
+    if (netif->hwaddr[i] != reply_msg->chaddr[i]) {
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
+        ("netif->hwaddr[%"U16_F"]==%02"X16_F" != reply_msg->chaddr[%"U16_F"]==%02"X16_F"\n",
+        (u16_t)i, (u16_t)netif->hwaddr[i], (u16_t)i, (u16_t)reply_msg->chaddr[i]));
+      goto free_pbuf_and_return;
+    }
+  }
+  /* match transaction ID against what we expected */
+  if (ntohl(reply_msg->xid) != dhcp->xid) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
+      ("transaction id mismatch reply_msg->xid(%"X32_F")!=dhcp->xid(%"X32_F")\n",ntohl(reply_msg->xid),dhcp->xid));
+    goto free_pbuf_and_return;
+  }
+  /* option fields could be unfold? */
+  if (dhcp_unfold_reply(dhcp, p) != ERR_OK) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
+      ("problem unfolding DHCP message - too short on memory?\n"));
+    goto free_pbuf_and_return;
+  }
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n"));
+  /* obtain pointer to DHCP message type */
+  options_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_MESSAGE_TYPE);
+  if (options_ptr == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP_OPTION_MESSAGE_TYPE option not found\n"));
+    goto free_pbuf_and_return;
+  }
+
+  /* read DHCP message type */
+  msg_type = dhcp_get_option_byte(options_ptr + 2);
+  /* message type is DHCP ACK? */
+  if (msg_type == DHCP_ACK) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_ACK received\n"));
+    /* in requesting state? */
+    if (dhcp->state == DHCP_REQUESTING) {
+      dhcp_handle_ack(netif);
+      dhcp->request_timeout = 0;
+#if DHCP_DOES_ARP_CHECK
+      /* check if the acknowledged lease address is already in use */
+      dhcp_check(netif);
+#else
+      /* bind interface to the acknowledged lease address */
+      dhcp_bind(netif);
+#endif
+    }
+    /* already bound to the given lease address? */
+    else if ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING)) {
+      dhcp->request_timeout = 0;
+      dhcp_bind(netif);
+    }
+  }
+  /* received a DHCP_NAK in appropriate state? */
+  else if ((msg_type == DHCP_NAK) &&
+    ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REQUESTING) ||
+     (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING  ))) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_NAK received\n"));
+    dhcp->request_timeout = 0;
+    dhcp_handle_nak(netif);
+  }
+  /* received a DHCP_OFFER in DHCP_SELECTING state? */
+  else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_SELECTING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_OFFER received in DHCP_SELECTING state\n"));
+    dhcp->request_timeout = 0;
+    /* remember offered lease */
+    dhcp_handle_offer(netif);
+  }
+free_pbuf_and_return:
+  dhcp_free_reply(dhcp);
+  pbuf_free(p);
+}
+
+/**
+ * Create a DHCP request, fill in common headers
+ *
+ * @param netif the netif under DHCP control
+ */
+static err_t
+dhcp_create_request(struct netif *netif)
+{
+  struct dhcp *dhcp;
+  u16_t i;
+#ifndef DHCP_GLOBAL_XID
+  /** default global transaction identifier starting value (easy to match
+   *  with a packet analyser). We simply increment for each new request.
+   *  Predefine DHCP_GLOBAL_XID to a better value or a function call to generate one
+   *  at runtime, any supporting function prototypes can be defined in DHCP_GLOBAL_XID_HEADER */
+  static u32_t xid = 0xABCD0000;
+#else
+  static u32_t xid;
+  static u8_t xid_initialised = 0;
+  if (!xid_initialised) {
+    xid = DHCP_GLOBAL_XID;
+    xid_initialised = !xid_initialised;
+  }
+#endif
+  LWIP_ERROR("dhcp_create_request: netif != NULL", (netif != NULL), return ERR_ARG;);
+  dhcp = netif->dhcp;
+  LWIP_ERROR("dhcp_create_request: dhcp != NULL", (dhcp != NULL), return ERR_VAL;);
+  LWIP_ASSERT("dhcp_create_request: dhcp->p_out == NULL", dhcp->p_out == NULL);
+  LWIP_ASSERT("dhcp_create_request: dhcp->msg_out == NULL", dhcp->msg_out == NULL);
+  dhcp->p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM);
+  if (dhcp->p_out == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
+      ("dhcp_create_request(): could not allocate pbuf\n"));
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("dhcp_create_request: check that first pbuf can hold struct dhcp_msg",
+           (dhcp->p_out->len >= sizeof(struct dhcp_msg)));
+
+  /* reuse transaction identifier in retransmissions */
+  if (dhcp->tries==0)
+      xid++;
+  dhcp->xid = xid;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE,
+              ("transaction id xid(%"X32_F")\n", xid));
+
+  dhcp->msg_out = (struct dhcp_msg *)dhcp->p_out->payload;
+
+  dhcp->msg_out->op = DHCP_BOOTREQUEST;
+  /* TODO: make link layer independent */
+  dhcp->msg_out->htype = DHCP_HTYPE_ETH;
+  /* TODO: make link layer independent */
+  dhcp->msg_out->hlen = DHCP_HLEN_ETH;
+  dhcp->msg_out->hops = 0;
+  dhcp->msg_out->xid = htonl(dhcp->xid);
+  dhcp->msg_out->secs = 0;
+  dhcp->msg_out->flags = 0;
+  dhcp->msg_out->ciaddr.addr = 0;
+  if (dhcp->state==DHCP_BOUND || dhcp->state==DHCP_RENEWING || dhcp->state==DHCP_REBINDING) {
+    dhcp->msg_out->ciaddr.addr = netif->ip_addr.addr;
+  }
+  dhcp->msg_out->yiaddr.addr = 0;
+  dhcp->msg_out->siaddr.addr = 0;
+  dhcp->msg_out->giaddr.addr = 0;
+  for (i = 0; i < DHCP_CHADDR_LEN; i++) {
+    /* copy netif hardware address, pad with zeroes */
+    dhcp->msg_out->chaddr[i] = (i < netif->hwaddr_len) ? netif->hwaddr[i] : 0/* pad byte*/;
+  }
+  for (i = 0; i < DHCP_SNAME_LEN; i++) {
+    dhcp->msg_out->sname[i] = 0;
+  }
+  for (i = 0; i < DHCP_FILE_LEN; i++) {
+    dhcp->msg_out->file[i] = 0;
+  }
+  dhcp->msg_out->cookie = htonl(0x63825363UL);
+  dhcp->options_out_len = 0;
+  /* fill options field with an incrementing array (for debugging purposes) */
+  for (i = 0; i < DHCP_OPTIONS_LEN; i++) {
+    dhcp->msg_out->options[i] = (u8_t)i; /* for debugging only, no matter if truncated */
+  }
+  return ERR_OK;
+}
+
+/**
+ * Free previously allocated memory used to send a DHCP request.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_delete_request(struct netif *netif)
+{
+  struct dhcp *dhcp;
+  LWIP_ERROR("dhcp_delete_request: netif != NULL", (netif != NULL), return;);
+  dhcp = netif->dhcp;
+  LWIP_ERROR("dhcp_delete_request: dhcp != NULL", (dhcp != NULL), return;);
+  LWIP_ASSERT("dhcp_delete_request: dhcp->p_out != NULL", dhcp->p_out != NULL);
+  LWIP_ASSERT("dhcp_delete_request: dhcp->msg_out != NULL", dhcp->msg_out != NULL);
+  if (dhcp->p_out != NULL) {
+    pbuf_free(dhcp->p_out);
+  }
+  dhcp->p_out = NULL;
+  dhcp->msg_out = NULL;
+}
+
+/**
+ * Add a DHCP message trailer
+ *
+ * Adds the END option to the DHCP message, and if
+ * necessary, up to three padding bytes.
+ *
+ * @param dhcp DHCP state structure
+ */
+static void
+dhcp_option_trailer(struct dhcp *dhcp)
+{
+  LWIP_ERROR("dhcp_option_trailer: dhcp != NULL", (dhcp != NULL), return;);
+  LWIP_ASSERT("dhcp_option_trailer: dhcp->msg_out != NULL\n", dhcp->msg_out != NULL);
+  LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = DHCP_OPTION_END;
+  /* packet is too small, or not 4 byte aligned? */
+  while ((dhcp->options_out_len < DHCP_MIN_OPTIONS_LEN) || (dhcp->options_out_len & 3)) {
+    /* LWIP_DEBUGF(DHCP_DEBUG,("dhcp_option_trailer:dhcp->options_out_len=%"U16_F", DHCP_OPTIONS_LEN=%"U16_F, dhcp->options_out_len, DHCP_OPTIONS_LEN)); */
+    LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+    /* add a fill/padding byte */
+    dhcp->msg_out->options[dhcp->options_out_len++] = 0;
+  }
+}
+
+/**
+ * Find the offset of a DHCP option inside the DHCP message.
+ *
+ * @param dhcp DHCP client
+ * @param option_type
+ *
+ * @return a byte offset into the UDP message where the option was found, or
+ * zero if the given option was not found.
+ */
+static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type)
+{
+  u8_t overload = DHCP_OVERLOAD_NONE;
+
+  /* options available? */
+  if ((dhcp->options_in != NULL) && (dhcp->options_in_len > 0)) {
+    /* start with options field */
+    u8_t *options = (u8_t *)dhcp->options_in;
+    u16_t offset = 0;
+    /* at least 1 byte to read and no end marker, then at least 3 bytes to read? */
+    while ((offset < dhcp->options_in_len) && (options[offset] != DHCP_OPTION_END)) {
+      /* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%"U16_F", q->len=%"U16_F, msg_offset, q->len)); */
+      /* are the sname and/or file field overloaded with options? */
+      if (options[offset] == DHCP_OPTION_OVERLOAD) {
+        LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded message detected\n"));
+        /* skip option type and length */
+        offset += 2;
+        overload = options[offset++];
+      }
+      /* requested option found */
+      else if (options[offset] == option_type) {
+        LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("option found at offset %"U16_F" in options\n", offset));
+        return &options[offset];
+      /* skip option */
+      } else {
+         LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %"U16_F" in options\n", options[offset]));
+        /* skip option type */
+        offset++;
+        /* skip option length, and then length bytes */
+        offset += 1 + options[offset];
+      }
+    }
+    /* is this an overloaded message? */
+    if (overload != DHCP_OVERLOAD_NONE) {
+      u16_t field_len;
+      if (overload == DHCP_OVERLOAD_FILE) {
+        LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded file field\n"));
+        options = (u8_t *)&dhcp->msg_in->file;
+        field_len = DHCP_FILE_LEN;
+      } else if (overload == DHCP_OVERLOAD_SNAME) {
+        LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname field\n"));
+        options = (u8_t *)&dhcp->msg_in->sname;
+        field_len = DHCP_SNAME_LEN;
+      /* TODO: check if else if () is necessary */
+      } else {
+        LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname and file field\n"));
+        options = (u8_t *)&dhcp->msg_in->sname;
+        field_len = DHCP_FILE_LEN + DHCP_SNAME_LEN;
+      }
+      offset = 0;
+
+      /* at least 1 byte to read and no end marker */
+      while ((offset < field_len) && (options[offset] != DHCP_OPTION_END)) {
+        if (options[offset] == option_type) {
+           LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("option found at offset=%"U16_F"\n", offset));
+          return &options[offset];
+        /* skip option */
+        } else {
+          LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("skipping option %"U16_F"\n", options[offset]));
+          /* skip option type */
+          offset++;
+          offset += 1 + options[offset];
+        }
+      }
+    }
+  }
+  return NULL;
+}
+
+/**
+ * Return the byte of DHCP option data.
+ *
+ * @param client DHCP client.
+ * @param ptr pointer obtained by dhcp_get_option_ptr().
+ *
+ * @return byte value at the given address.
+ */
+static u8_t
+dhcp_get_option_byte(u8_t *ptr)
+{
+  LWIP_DEBUGF(DHCP_DEBUG, ("option byte value=%"U16_F"\n", (u16_t)(*ptr)));
+  return *ptr;
+}
+
+#if 0 /* currently unused */
+/**
+ * Return the 16-bit value of DHCP option data.
+ *
+ * @param client DHCP client.
+ * @param ptr pointer obtained by dhcp_get_option_ptr().
+ *
+ * @return byte value at the given address.
+ */
+static u16_t
+dhcp_get_option_short(u8_t *ptr)
+{
+  u16_t value;
+  value = *ptr++ << 8;
+  value |= *ptr;
+  LWIP_DEBUGF(DHCP_DEBUG, ("option short value=%"U16_F"\n", value));
+  return value;
+}
+#endif
+
+/**
+ * Return the 32-bit value of DHCP option data.
+ *
+ * @param client DHCP client.
+ * @param ptr pointer obtained by dhcp_get_option_ptr().
+ *
+ * @return byte value at the given address.
+ */
+static u32_t dhcp_get_option_long(u8_t *ptr)
+{
+  u32_t value;
+  value = (u32_t)(*ptr++) << 24;
+  value |= (u32_t)(*ptr++) << 16;
+  value |= (u32_t)(*ptr++) << 8;
+  value |= (u32_t)(*ptr++);
+  LWIP_DEBUGF(DHCP_DEBUG, ("option long value=%"U32_F"\n", value));
+  return value;
+}
+
+#endif /* LWIP_DHCP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/dns.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/dns.c
new file mode 100644
index 0000000..b955538
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/dns.c
@@ -0,0 +1,980 @@
+/**
+ * @file
+ * DNS - host name to IP address resolver.
+ *
+ */
+
+/**
+
+ * This file implements a DNS host name to IP address resolver.
+
+ * Port to lwIP from uIP
+ * by Jim Pettinato April 2007
+
+ * uIP version Copyright (c) 2002-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * DNS.C
+ *
+ * The lwIP DNS resolver functions are used to lookup a host name and
+ * map it to a numerical IP address. It maintains a list of resolved
+ * hostnames that can be queried with the dns_lookup() function.
+ * New hostnames can be resolved using the dns_query() function.
+ *
+ * The lwIP version of the resolver also adds a non-blocking version of
+ * gethostbyname() that will work with a raw API application. This function
+ * checks for an IP address string first and converts it if it is valid.
+ * gethostbyname() then does a dns_lookup() to see if the name is 
+ * already in the table. If so, the IP is returned. If not, a query is 
+ * issued and the function returns with a ERR_INPROGRESS status. The app
+ * using the dns client must then go into a waiting state.
+ *
+ * Once a hostname has been resolved (or found to be non-existent),
+ * the resolver code calls a specified callback function (which 
+ * must be implemented by the module that uses the resolver).
+ */
+
+/*-----------------------------------------------------------------------------
+ * RFC 1035 - Domain names - implementation and specification
+ * RFC 2181 - Clarifications to the DNS Specification
+ *----------------------------------------------------------------------------*/
+
+/** @todo: define good default values (rfc compliance) */
+/** @todo: improve answer parsing, more checkings... */
+/** @todo: check RFC1035 - 7.3. Processing responses */
+
+/*-----------------------------------------------------------------------------
+ * Includes
+ *----------------------------------------------------------------------------*/
+
+#include "lwip/opt.h"
+
+#if LWIP_DNS /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/udp.h"
+#include "lwip/mem.h"
+#include "lwip/dns.h"
+
+#include 
+
+/** DNS server IP address */
+#ifndef DNS_SERVER_ADDRESS
+#define DNS_SERVER_ADDRESS        inet_addr("208.67.222.222") /* resolver1.opendns.com */
+#endif
+
+/** DNS server port address */
+#ifndef DNS_SERVER_PORT
+#define DNS_SERVER_PORT           53
+#endif
+
+/** DNS maximum number of retries when asking for a name, before "timeout". */
+#ifndef DNS_MAX_RETRIES
+#define DNS_MAX_RETRIES           4
+#endif
+
+/** DNS resource record max. TTL (one week as default) */
+#ifndef DNS_MAX_TTL
+#define DNS_MAX_TTL               604800
+#endif
+
+/* DNS protocol flags */
+#define DNS_FLAG1_RESPONSE        0x80
+#define DNS_FLAG1_OPCODE_STATUS   0x10
+#define DNS_FLAG1_OPCODE_INVERSE  0x08
+#define DNS_FLAG1_OPCODE_STANDARD 0x00
+#define DNS_FLAG1_AUTHORATIVE     0x04
+#define DNS_FLAG1_TRUNC           0x02
+#define DNS_FLAG1_RD              0x01
+#define DNS_FLAG2_RA              0x80
+#define DNS_FLAG2_ERR_MASK        0x0f
+#define DNS_FLAG2_ERR_NONE        0x00
+#define DNS_FLAG2_ERR_NAME        0x03
+
+/* DNS protocol states */
+#define DNS_STATE_UNUSED          0
+#define DNS_STATE_NEW             1
+#define DNS_STATE_ASKING          2
+#define DNS_STATE_DONE            3
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** DNS message header */
+struct dns_hdr {
+  PACK_STRUCT_FIELD(u16_t id);
+  PACK_STRUCT_FIELD(u8_t flags1);
+  PACK_STRUCT_FIELD(u8_t flags2);
+  PACK_STRUCT_FIELD(u16_t numquestions);
+  PACK_STRUCT_FIELD(u16_t numanswers);
+  PACK_STRUCT_FIELD(u16_t numauthrr);
+  PACK_STRUCT_FIELD(u16_t numextrarr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+#define SIZEOF_DNS_HDR 12
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** DNS query message structure */
+struct dns_query {
+  /* DNS query record starts with either a domain name or a pointer
+     to a name already present somewhere in the packet. */
+  PACK_STRUCT_FIELD(u16_t type);
+  PACK_STRUCT_FIELD(u16_t class);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+#define SIZEOF_DNS_QUERY 4
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** DNS answer message structure */
+struct dns_answer {
+  /* DNS answer record starts with either a domain name or a pointer
+     to a name already present somewhere in the packet. */
+  PACK_STRUCT_FIELD(u16_t type);
+  PACK_STRUCT_FIELD(u16_t class);
+  PACK_STRUCT_FIELD(u32_t ttl);
+  PACK_STRUCT_FIELD(u16_t len);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+#define SIZEOF_DNS_ANSWER 10
+
+/** DNS table entry */
+struct dns_table_entry {
+  u8_t  state;
+  u8_t  numdns;
+  u8_t  tmr;
+  u8_t  retries;
+  u8_t  seqno;
+  u8_t  err;
+  u32_t ttl;
+  char name[DNS_MAX_NAME_LENGTH];
+  struct ip_addr ipaddr;
+  /* pointer to callback on DNS query done */
+  dns_found_callback found;
+  void *arg;
+};
+
+#if DNS_LOCAL_HOSTLIST
+/** struct used for local host-list */
+struct local_hostlist_entry {
+  /** static hostname */
+  const char *name;
+  /** static host address in network byteorder */
+  u32_t addr;
+  struct local_hostlist_entry *next;
+};
+
+#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+/** Local host-list. For hostnames in this list, no
+ *  external name resolution is performed */
+static struct local_hostlist_entry *local_hostlist_dynamic;
+#else /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+
+/** Defining this allows the local_hostlist_static to be placed in a different
+ * linker section (e.g. FLASH) */
+#ifndef DNS_LOCAL_HOSTLIST_STORAGE_PRE
+#define DNS_LOCAL_HOSTLIST_STORAGE_PRE static
+#endif /* DNS_LOCAL_HOSTLIST_STORAGE_PRE */
+/** Defining this allows the local_hostlist_static to be placed in a different
+ * linker section (e.g. FLASH) */
+#ifndef DNS_LOCAL_HOSTLIST_STORAGE_POST
+#define DNS_LOCAL_HOSTLIST_STORAGE_POST
+#endif /* DNS_LOCAL_HOSTLIST_STORAGE_POST */
+DNS_LOCAL_HOSTLIST_STORAGE_PRE struct local_hostlist_entry local_hostlist_static[]
+  DNS_LOCAL_HOSTLIST_STORAGE_POST = DNS_LOCAL_HOSTLIST_INIT;
+
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+
+static void dns_init_local();
+#endif /* DNS_LOCAL_HOSTLIST */
+
+
+/* forward declarations */
+static void dns_recv(void *s, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port);
+static void dns_check_entries(void);
+
+/*-----------------------------------------------------------------------------
+ * Globales
+ *----------------------------------------------------------------------------*/
+
+/* DNS variables */
+static struct udp_pcb        *dns_pcb;
+static u8_t                   dns_seqno;
+static struct dns_table_entry dns_table[DNS_TABLE_SIZE];
+static struct ip_addr         dns_servers[DNS_MAX_SERVERS];
+
+#if (DNS_USES_STATIC_BUF == 1)
+static u8_t                   dns_payload[DNS_MSG_SIZE];
+#endif /* (DNS_USES_STATIC_BUF == 1) */
+
+/**
+ * Initialize the resolver: set up the UDP pcb and configure the default server
+ * (DNS_SERVER_ADDRESS).
+ */
+void
+dns_init()
+{
+  struct ip_addr dnsserver;
+  
+  /* initialize default DNS server address */
+  dnsserver.addr = DNS_SERVER_ADDRESS;
+
+  LWIP_DEBUGF(DNS_DEBUG, ("dns_init: initializing\n"));
+
+  /* if dns client not yet initialized... */
+  if (dns_pcb == NULL) {
+    dns_pcb = udp_new();
+
+    if (dns_pcb != NULL) {
+      /* initialize DNS table not needed (initialized to zero since it is a
+       * global variable) */
+      LWIP_ASSERT("For implicit initialization to work, DNS_STATE_UNUSED needs to be 0",
+        DNS_STATE_UNUSED == 0);
+
+      /* initialize DNS client */
+      udp_bind(dns_pcb, IP_ADDR_ANY, 0);
+      udp_recv(dns_pcb, dns_recv, NULL);
+
+      /* initialize default DNS primary server */
+      dns_setserver(0, &dnsserver);
+    }
+  }
+#if DNS_LOCAL_HOSTLIST
+  dns_init_local();
+#endif
+}
+
+/**
+ * Initialize one of the DNS servers.
+ *
+ * @param numdns the index of the DNS server to set must be < DNS_MAX_SERVERS
+ * @param dnsserver IP address of the DNS server to set
+ */
+void
+dns_setserver(u8_t numdns, struct ip_addr *dnsserver)
+{
+  if ((numdns < DNS_MAX_SERVERS) && (dns_pcb != NULL) &&
+      (dnsserver != NULL) && (dnsserver->addr !=0 )) {
+    dns_servers[numdns] = (*dnsserver);
+  }
+}
+
+/**
+ * Obtain one of the currently configured DNS server.
+ *
+ * @param numdns the index of the DNS server
+ * @return IP address of the indexed DNS server or "ip_addr_any" if the DNS
+ *         server has not been configured.
+ */
+struct ip_addr
+dns_getserver(u8_t numdns)
+{
+  if (numdns < DNS_MAX_SERVERS) {
+    return dns_servers[numdns];
+  } else {
+    return *IP_ADDR_ANY;
+  }
+}
+
+/**
+ * The DNS resolver client timer - handle retries and timeouts and should
+ * be called every DNS_TMR_INTERVAL milliseconds (every second by default).
+ */
+void
+dns_tmr(void)
+{
+  if (dns_pcb != NULL) {
+    LWIP_DEBUGF(DNS_DEBUG, ("dns_tmr: dns_check_entries\n"));
+    dns_check_entries();
+  }
+}
+
+#if DNS_LOCAL_HOSTLIST
+static void
+dns_init_local()
+{
+#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC && defined(DNS_LOCAL_HOSTLIST_INIT)
+  int i;
+  struct local_hostlist_entry *entry;
+  /* Dynamic: copy entries from DNS_LOCAL_HOSTLIST_INIT to list */
+  struct local_hostlist_entry local_hostlist_init[] = DNS_LOCAL_HOSTLIST_INIT;
+  for (i = 0; i < sizeof(local_hostlist_init) / sizeof(struct local_hostlist_entry); i++) {
+    entry = mem_malloc(sizeof(struct local_hostlist_entry));
+    LWIP_ASSERT("mem-error in dns_init_local", entry != NULL);
+    if (entry != NULL) {
+      struct local_hostlist_entry *init_entry = &local_hostlist_init[i];
+      entry->name = init_entry->name;
+      entry->addr = init_entry->addr;
+      entry->next = local_hostlist_dynamic;
+      local_hostlist_dynamic = entry;
+    }
+  }
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC && defined(DNS_LOCAL_HOSTLIST_INIT) */
+}
+
+/**
+ * Scans the local host-list for a hostname.
+ *
+ * @param hostname Hostname to look for in the local host-list
+ * @return The first IP address for the hostname in the local host-list or
+ *         INADDR_NONE if not found.
+ */
+static u32_t
+dns_lookup_local(const char *hostname)
+{
+#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+  struct local_hostlist_entry *entry = local_hostlist_dynamic;
+  while(entry != NULL) {
+    if(strcmp(entry->name, hostname) == 0) {
+      return entry->addr;
+    }
+    entry = entry->next;
+  }
+#else /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+  int i;
+  for (i = 0; i < sizeof(local_hostlist_static) / sizeof(struct local_hostlist_entry); i++) {
+    if(strcmp(local_hostlist_static[i].name, hostname) == 0) {
+      return local_hostlist_static[i].addr;
+    }
+  }
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+  return INADDR_NONE;
+}
+
+#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+/** Remove all entries from the local host-list for a specific hostname
+ * and/or IP addess
+ *
+ * @param hostname hostname for which entries shall be removed from the local
+ *                 host-list
+ * @param addr address for which entries shall be removed from the local host-list
+ * @return the number of removed entries
+ */
+int
+dns_local_removehost(const char *hostname, const struct ip_addr *addr)
+{
+  int removed = 0;
+  struct local_hostlist_entry *entry = local_hostlist_dynamic;
+  struct local_hostlist_entry *last_entry = NULL;
+  while (entry != NULL) {
+    if (((hostname == NULL) || !strcmp(entry->name, hostname)) &&
+        ((addr == NULL) || (entry->addr == addr->addr))) {
+      struct local_hostlist_entry *free_entry;
+      if (last_entry != NULL) {
+        last_entry->next = entry->next;
+      } else {
+        local_hostlist_dynamic = entry->next;
+      }
+      free_entry = entry;
+      entry = entry->next;
+      mem_free(free_entry);
+      removed++;
+    } else {
+      last_entry = entry;
+      entry = entry->next;
+    }
+  }
+  return removed;
+}
+
+/**
+ * Add a hostname/IP address pair to the local host-list.
+ * Duplicates are not checked.
+ *
+ * @param hostname hostname of the new entry
+ * @param addr IP address of the new entry
+ * @return ERR_OK if succeeded or ERR_MEM on memory error
+ */
+err_t
+dns_local_addhost(const char *hostname, const struct ip_addr *addr)
+{
+  struct local_hostlist_entry *entry;
+  entry = mem_malloc(sizeof(struct local_hostlist_entry));
+  if (entry == NULL) {
+    return ERR_MEM;
+  }
+  entry->name = hostname;
+  entry->addr = addr->addr;
+  entry->next = local_hostlist_dynamic;
+  local_hostlist_dynamic = entry;
+  return ERR_OK;
+}
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC*/
+#endif /* DNS_LOCAL_HOSTLIST */
+
+/**
+ * Look up a hostname in the array of known hostnames.
+ *
+ * @note This function only looks in the internal array of known
+ * hostnames, it does not send out a query for the hostname if none
+ * was found. The function dns_enqueue() can be used to send a query
+ * for a hostname.
+ *
+ * @param name the hostname to look up
+ * @return the hostname's IP address, as u32_t (instead of struct ip_addr to
+ *         better check for failure: != INADDR_NONE) or INADDR_NONE if the hostname
+ *         was not found in the cached dns_table.
+ */
+static u32_t
+dns_lookup(const char *name)
+{
+  u8_t i;
+#if DNS_LOCAL_HOSTLIST || defined(DNS_LOOKUP_LOCAL_EXTERN)
+  u32_t addr;
+#endif /* DNS_LOCAL_HOSTLIST || defined(DNS_LOOKUP_LOCAL_EXTERN) */
+#if DNS_LOCAL_HOSTLIST
+  if ((addr = dns_lookup_local(name)) != INADDR_NONE) {
+    return addr;
+  }
+#endif /* DNS_LOCAL_HOSTLIST */
+#ifdef DNS_LOOKUP_LOCAL_EXTERN
+  if((addr = DNS_LOOKUP_LOCAL_EXTERN(name)) != INADDR_NONE) {
+    return addr;
+  }
+#endif /* DNS_LOOKUP_LOCAL_EXTERN */
+
+  /* Walk through name list, return entry if found. If not, return NULL. */
+  for (i = 0; i < DNS_TABLE_SIZE; ++i) {
+    if ((dns_table[i].state == DNS_STATE_DONE) &&
+        (strcmp(name, dns_table[i].name) == 0)) {
+      LWIP_DEBUGF(DNS_DEBUG, ("dns_lookup: \"%s\": found = ", name));
+      ip_addr_debug_print(DNS_DEBUG, &(dns_table[i].ipaddr));
+      LWIP_DEBUGF(DNS_DEBUG, ("\n"));
+      return dns_table[i].ipaddr.addr;
+    }
+  }
+
+  return INADDR_NONE;
+}
+
+#if DNS_DOES_NAME_CHECK
+/**
+ * Compare the "dotted" name "query" with the encoded name "response"
+ * to make sure an answer from the DNS server matches the current dns_table
+ * entry (otherwise, answers might arrive late for hostname not on the list
+ * any more).
+ *
+ * @param query hostname (not encoded) from the dns_table
+ * @param response encoded hostname in the DNS response
+ * @return 0: names equal; 1: names differ
+ */
+static u8_t
+dns_compare_name(unsigned char *query, unsigned char *response)
+{
+  unsigned char n;
+
+  do {
+    n = *response++;
+    /** @see RFC 1035 - 4.1.4. Message compression */
+    if ((n & 0xc0) == 0xc0) {
+      /* Compressed name */
+      break;
+    } else {
+      /* Not compressed name */
+      while (n > 0) {
+        if ((*query) != (*response)) {
+          return 1;
+        }
+        ++response;
+        ++query;
+        --n;
+      };
+      ++query;
+    }
+  } while (*response != 0);
+
+  return 0;
+}
+#endif /* DNS_DOES_NAME_CHECK */
+
+/**
+ * Walk through a compact encoded DNS name and return the end of the name.
+ *
+ * @param query encoded DNS name in the DNS server response
+ * @return end of the name
+ */
+static unsigned char *
+dns_parse_name(unsigned char *query)
+{
+  unsigned char n;
+
+  do {
+    n = *query++;
+    /** @see RFC 1035 - 4.1.4. Message compression */
+    if ((n & 0xc0) == 0xc0) {
+      /* Compressed name */
+      break;
+    } else {
+      /* Not compressed name */
+      while (n > 0) {
+        ++query;
+        --n;
+      };
+    }
+  } while (*query != 0);
+
+  return query + 1;
+}
+
+/**
+ * Send a DNS query packet.
+ *
+ * @param numdns index of the DNS server in the dns_servers table
+ * @param name hostname to query
+ * @param id index of the hostname in dns_table, used as transaction ID in the
+ *        DNS query packet
+ * @return ERR_OK if packet is sent; an err_t indicating the problem otherwise
+ */
+static err_t
+dns_send(u8_t numdns, const char* name, u8_t id)
+{
+  err_t err;
+  struct dns_hdr *hdr;
+  struct dns_query qry;
+  struct pbuf *p;
+  char *query, *nptr;
+  const char *pHostname;
+  u8_t n;
+
+  LWIP_DEBUGF(DNS_DEBUG, ("dns_send: dns_servers[%"U16_F"] \"%s\": request\n",
+              (u16_t)(numdns), name));
+  LWIP_ASSERT("dns server out of array", numdns < DNS_MAX_SERVERS);
+  LWIP_ASSERT("dns server has no IP address set", dns_servers[numdns].addr != 0);
+
+  /* if here, we have either a new query or a retry on a previous query to process */
+  p = pbuf_alloc(PBUF_TRANSPORT, SIZEOF_DNS_HDR + DNS_MAX_NAME_LENGTH +
+                 SIZEOF_DNS_QUERY, PBUF_RAM);
+  if (p != NULL) {
+    LWIP_ASSERT("pbuf must be in one piece", p->next == NULL);
+    /* fill dns header */
+    hdr = (struct dns_hdr*)p->payload;
+    memset(hdr, 0, SIZEOF_DNS_HDR);
+    hdr->id = htons(id);
+    hdr->flags1 = DNS_FLAG1_RD;
+    hdr->numquestions = htons(1);
+    query = (char*)hdr + SIZEOF_DNS_HDR;
+    pHostname = name;
+    --pHostname;
+
+    /* convert hostname into suitable query format. */
+    do {
+      ++pHostname;
+      nptr = query;
+      ++query;
+      for(n = 0; *pHostname != '.' && *pHostname != 0; ++pHostname) {
+        *query = *pHostname;
+        ++query;
+        ++n;
+      }
+      *nptr = n;
+    } while(*pHostname != 0);
+    *query++='\0';
+
+    /* fill dns query */
+    qry.type  = htons(DNS_RRTYPE_A);
+    qry.class = htons(DNS_RRCLASS_IN);
+    MEMCPY( query, &qry, SIZEOF_DNS_QUERY);
+
+    /* resize pbuf to the exact dns query */
+    pbuf_realloc(p, (query + SIZEOF_DNS_QUERY) - ((char*)(p->payload)));
+
+    /* connect to the server for faster receiving */
+    udp_connect(dns_pcb, &dns_servers[numdns], DNS_SERVER_PORT);
+    /* send dns packet */
+    err = udp_sendto(dns_pcb, p, &dns_servers[numdns], DNS_SERVER_PORT);
+
+    /* free pbuf */
+    pbuf_free(p);
+  } else {
+    err = ERR_MEM;
+  }
+
+  return err;
+}
+
+/**
+ * dns_check_entry() - see if pEntry has not yet been queried and, if so, sends out a query.
+ * Check an entry in the dns_table:
+ * - send out query for new entries
+ * - retry old pending entries on timeout (also with different servers)
+ * - remove completed entries from the table if their TTL has expired
+ *
+ * @param i index of the dns_table entry to check
+ */
+static void
+dns_check_entry(u8_t i)
+{
+  struct dns_table_entry *pEntry = &dns_table[i];
+
+  LWIP_ASSERT("array index out of bounds", i < DNS_TABLE_SIZE);
+
+  switch(pEntry->state) {
+
+    case DNS_STATE_NEW: {
+      /* initialize new entry */
+      pEntry->state   = DNS_STATE_ASKING;
+      pEntry->numdns  = 0;
+      pEntry->tmr     = 1;
+      pEntry->retries = 0;
+      
+      /* send DNS packet for this entry */
+      dns_send(pEntry->numdns, pEntry->name, i);
+      break;
+    }
+
+    case DNS_STATE_ASKING: {
+      if (--pEntry->tmr == 0) {
+        if (++pEntry->retries == DNS_MAX_RETRIES) {
+          if ((pEntry->numdns+1numdns+1].addr!=0)) {
+            /* change of server */
+            pEntry->numdns++;
+            pEntry->tmr     = 1;
+            pEntry->retries = 0;
+            break;
+          } else {
+            LWIP_DEBUGF(DNS_DEBUG, ("dns_check_entry: \"%s\": timeout\n", pEntry->name));
+            /* call specified callback function if provided */
+            if (pEntry->found)
+              (*pEntry->found)(pEntry->name, NULL, pEntry->arg);
+            /* flush this entry */
+            pEntry->state   = DNS_STATE_UNUSED;
+            pEntry->found   = NULL;
+            break;
+          }
+        }
+
+        /* wait longer for the next retry */
+        pEntry->tmr = pEntry->retries;
+
+        /* send DNS packet for this entry */
+        dns_send(pEntry->numdns, pEntry->name, i);
+      }
+      break;
+    }
+
+    case DNS_STATE_DONE: {
+      /* if the time to live is nul */
+      if (--pEntry->ttl == 0) {
+        LWIP_DEBUGF(DNS_DEBUG, ("dns_check_entry: \"%s\": flush\n", pEntry->name));
+        /* flush this entry */
+        pEntry->state = DNS_STATE_UNUSED;
+        pEntry->found = NULL;
+      }
+      break;
+    }
+    case DNS_STATE_UNUSED:
+      /* nothing to do */
+      break;
+    default:
+      LWIP_ASSERT("unknown dns_table entry state:", 0);
+      break;
+  }
+}
+
+/**
+ * Call dns_check_entry for each entry in dns_table - check all entries.
+ */
+static void
+dns_check_entries(void)
+{
+  u8_t i;
+
+  for (i = 0; i < DNS_TABLE_SIZE; ++i) {
+    dns_check_entry(i);
+  }
+}
+
+/**
+ * Receive input function for DNS response packets arriving for the dns UDP pcb.
+ *
+ * @params see udp.h
+ */
+static void
+dns_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port)
+{
+  u8_t i;
+  char *pHostname;
+  struct dns_hdr *hdr;
+  struct dns_answer ans;
+  struct dns_table_entry *pEntry;
+  u8_t nquestions, nanswers;
+#if (DNS_USES_STATIC_BUF == 0)
+  u8_t dns_payload[DNS_MSG_SIZE];
+#endif /* (DNS_USES_STATIC_BUF == 0) */
+#if (DNS_USES_STATIC_BUF == 2)
+  u8_t* dns_payload;
+#endif /* (DNS_USES_STATIC_BUF == 2) */
+
+  LWIP_UNUSED_ARG(arg);
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_UNUSED_ARG(addr);
+  LWIP_UNUSED_ARG(port);
+
+  /* is the dns message too big ? */
+  if (p->tot_len > DNS_MSG_SIZE) {
+    LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: pbuf too big\n"));
+    /* free pbuf and return */
+    goto memerr1;
+  }
+
+  /* is the dns message big enough ? */
+  if (p->tot_len < (SIZEOF_DNS_HDR + SIZEOF_DNS_QUERY + SIZEOF_DNS_ANSWER)) {
+    LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: pbuf too small\n"));
+    /* free pbuf and return */
+    goto memerr1;
+  }
+
+#if (DNS_USES_STATIC_BUF == 2)
+  dns_payload = mem_malloc(p->tot_len);
+  if (dns_payload == NULL) {
+    LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: mem_malloc error\n"));
+    /* free pbuf and return */
+    goto memerr1;
+  }
+#endif /* (DNS_USES_STATIC_BUF == 2) */
+
+  /* copy dns payload inside static buffer for processing */ 
+  if (pbuf_copy_partial(p, dns_payload, p->tot_len, 0) == p->tot_len) {
+    /* The ID in the DNS header should be our entry into the name table. */
+    hdr = (struct dns_hdr*)dns_payload;
+    i = htons(hdr->id);
+    if (i < DNS_TABLE_SIZE) {
+      pEntry = &dns_table[i];
+      if(pEntry->state == DNS_STATE_ASKING) {
+        /* This entry is now completed. */
+        pEntry->state = DNS_STATE_DONE;
+        pEntry->err   = hdr->flags2 & DNS_FLAG2_ERR_MASK;
+
+        /* We only care about the question(s) and the answers. The authrr
+           and the extrarr are simply discarded. */
+        nquestions = htons(hdr->numquestions);
+        nanswers   = htons(hdr->numanswers);
+
+        /* Check for error. If so, call callback to inform. */
+        if (((hdr->flags1 & DNS_FLAG1_RESPONSE) == 0) || (pEntry->err != 0) || (nquestions != 1)) {
+          LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": error in flags\n", pEntry->name));
+          /* call callback to indicate error, clean up memory and return */
+          goto responseerr;
+        }
+
+#if DNS_DOES_NAME_CHECK
+        /* Check if the name in the "question" part match with the name in the entry. */
+        if (dns_compare_name((unsigned char *)(pEntry->name), (unsigned char *)dns_payload + SIZEOF_DNS_HDR) != 0) {
+          LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response not match to query\n", pEntry->name));
+          /* call callback to indicate error, clean up memory and return */
+          goto responseerr;
+        }
+#endif /* DNS_DOES_NAME_CHECK */
+
+        /* Skip the name in the "question" part */
+        pHostname = (char *) dns_parse_name((unsigned char *)dns_payload + SIZEOF_DNS_HDR) + SIZEOF_DNS_QUERY;
+
+        while(nanswers > 0) {
+          /* skip answer resource record's host name */
+          pHostname = (char *) dns_parse_name((unsigned char *)pHostname);
+
+          /* Check for IP address type and Internet class. Others are discarded. */
+          MEMCPY(&ans, pHostname, SIZEOF_DNS_ANSWER);
+          if((ntohs(ans.type) == DNS_RRTYPE_A) && (ntohs(ans.class) == DNS_RRCLASS_IN) && (ntohs(ans.len) == sizeof(struct ip_addr)) ) {
+            /* read the answer resource record's TTL, and maximize it if needed */
+            pEntry->ttl = ntohl(ans.ttl);
+            if (pEntry->ttl > DNS_MAX_TTL) {
+              pEntry->ttl = DNS_MAX_TTL;
+            }
+            /* read the IP address after answer resource record's header */
+            MEMCPY( &(pEntry->ipaddr), (pHostname+SIZEOF_DNS_ANSWER), sizeof(struct ip_addr));
+            LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response = ", pEntry->name));
+            ip_addr_debug_print(DNS_DEBUG, (&(pEntry->ipaddr)));
+            LWIP_DEBUGF(DNS_DEBUG, ("\n"));
+            /* call specified callback function if provided */
+            if (pEntry->found) {
+              (*pEntry->found)(pEntry->name, &pEntry->ipaddr, pEntry->arg);
+            }
+            /* deallocate memory and return */
+            goto memerr2;
+          } else {
+            pHostname = pHostname + SIZEOF_DNS_ANSWER + htons(ans.len);
+          }
+          --nanswers;
+        }
+        LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": error in response\n", pEntry->name));
+        /* call callback to indicate error, clean up memory and return */
+        goto responseerr;
+      }
+    }
+  }
+
+  /* deallocate memory and return */
+  goto memerr2;
+
+responseerr:
+  /* ERROR: call specified callback function with NULL as name to indicate an error */
+  if (pEntry->found) {
+    (*pEntry->found)(pEntry->name, NULL, pEntry->arg);
+  }
+  /* flush this entry */
+  pEntry->state = DNS_STATE_UNUSED;
+  pEntry->found = NULL;
+
+memerr2:
+#if (DNS_USES_STATIC_BUF == 2)
+  /* free dns buffer */
+  mem_free(dns_payload);
+#endif /* (DNS_USES_STATIC_BUF == 2) */
+
+memerr1:
+  /* free pbuf */
+  pbuf_free(p);
+  return;
+}
+
+/**
+ * Queues a new hostname to resolve and sends out a DNS query for that hostname
+ *
+ * @param name the hostname that is to be queried
+ * @param found a callback founction to be called on success, failure or timeout
+ * @param callback_arg argument to pass to the callback function
+ * @return @return a err_t return code.
+ */
+static err_t
+dns_enqueue(const char *name, dns_found_callback found, void *callback_arg)
+{
+  u8_t i;
+  u8_t lseq, lseqi;
+  struct dns_table_entry *pEntry = NULL;
+
+  /* search an unused entry, or the oldest one */
+  lseq = lseqi = 0;
+  for (i = 0; i < DNS_TABLE_SIZE; ++i) {
+    pEntry = &dns_table[i];
+    /* is it an unused entry ? */
+    if (pEntry->state == DNS_STATE_UNUSED)
+      break;
+
+    /* check if this is the oldest completed entry */
+    if (pEntry->state == DNS_STATE_DONE) {
+      if ((dns_seqno - pEntry->seqno) > lseq) {
+        lseq = dns_seqno - pEntry->seqno;
+        lseqi = i;
+      }
+    }
+  }
+
+  /* if we don't have found an unused entry, use the oldest completed one */
+  if (i == DNS_TABLE_SIZE) {
+    if ((lseqi >= DNS_TABLE_SIZE) || (dns_table[lseqi].state != DNS_STATE_DONE)) {
+      /* no entry can't be used now, table is full */
+      LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": DNS entries table is full\n", name));
+      return ERR_MEM;
+    } else {
+      /* use the oldest completed one */
+      i = lseqi;
+      pEntry = &dns_table[i];
+    }
+  }
+
+  /* use this entry */
+  LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": use DNS entry %"U16_F"\n", name, (u16_t)(i)));
+
+  /* fill the entry */
+  pEntry->state = DNS_STATE_NEW;
+  pEntry->seqno = dns_seqno++;
+  pEntry->found = found;
+  pEntry->arg   = callback_arg;
+  strcpy(pEntry->name, name);
+
+  /* force to send query without waiting timer */
+  dns_check_entry(i);
+
+  /* dns query is enqueued */
+  return ERR_INPROGRESS;
+}
+
+/**
+ * Resolve a hostname (string) into an IP address.
+ * NON-BLOCKING callback version for use with raw API!!!
+ *
+ * Returns immediately with one of err_t return codes:
+ * - ERR_OK if hostname is a valid IP address string or the host
+ *   name is already in the local names table.
+ * - ERR_INPROGRESS enqueue a request to be sent to the DNS server
+ *   for resolution if no errors are present.
+ *
+ * @param hostname the hostname that is to be queried
+ * @param addr pointer to a struct ip_addr where to store the address if it is already
+ *             cached in the dns_table (only valid if ERR_OK is returned!)
+ * @param found a callback function to be called on success, failure or timeout (only if
+ *              ERR_INPROGRESS is returned!)
+ * @param callback_arg argument to pass to the callback function
+ * @return a err_t return code.
+ */
+err_t
+dns_gethostbyname(const char *hostname, struct ip_addr *addr, dns_found_callback found,
+                  void *callback_arg)
+{
+  /* not initialized or no valid server yet, or invalid addr pointer
+   * or invalid hostname or invalid hostname length */
+  if ((dns_pcb == NULL) || (addr == NULL) ||
+      (!hostname) || (!hostname[0]) ||
+      (strlen(hostname) >= DNS_MAX_NAME_LENGTH)) {
+    return ERR_VAL;
+  }
+
+#if LWIP_HAVE_LOOPIF
+  if (strcmp(hostname,"localhost")==0) {
+    addr->addr = htonl(INADDR_LOOPBACK);
+    return ERR_OK;
+  }
+#endif /* LWIP_HAVE_LOOPIF */
+
+  /* host name already in octet notation? set ip addr and return ERR_OK
+   * already have this address cached? */
+  if (((addr->addr = inet_addr(hostname)) != INADDR_NONE) ||
+      ((addr->addr = dns_lookup(hostname)) != INADDR_NONE)) {
+    return ERR_OK;
+  }
+
+  /* queue query with specified callback */
+  return dns_enqueue(hostname, found, callback_arg);
+}
+
+#endif /* LWIP_DNS */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/init.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/init.c
new file mode 100644
index 0000000..be0e358
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/init.c
@@ -0,0 +1,274 @@
+/**
+ * @file
+ * Modules initialization
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/init.h"
+#include "lwip/stats.h"
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/sockets.h"
+#include "lwip/ip.h"
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+#include "lwip/snmp_msg.h"
+#include "lwip/autoip.h"
+#include "lwip/igmp.h"
+#include "lwip/dns.h"
+#include "netif/etharp.h"
+
+/* Compile-time sanity checks for configuration errors.
+ * These can be done independently of LWIP_DEBUG, without penalty.
+ */
+#ifndef BYTE_ORDER
+  #error "BYTE_ORDER is not defined, you have to define it in your cc.h"
+#endif
+#if (!IP_SOF_BROADCAST && IP_SOF_BROADCAST_RECV)
+  #error "If you want to use broadcast filter per pcb on recv operations, you have to define IP_SOF_BROADCAST=1 in your lwipopts.h"
+#endif
+#if (!LWIP_ARP && ARP_QUEUEING)
+  #error "If you want to use ARP Queueing, you have to define LWIP_ARP=1 in your lwipopts.h"
+#endif
+#if (!LWIP_UDP && LWIP_UDPLITE)
+  #error "If you want to use UDP Lite, you have to define LWIP_UDP=1 in your lwipopts.h"
+#endif
+#if (!LWIP_UDP && LWIP_SNMP)
+  #error "If you want to use SNMP, you have to define LWIP_UDP=1 in your lwipopts.h"
+#endif
+#if (!LWIP_UDP && LWIP_DHCP)
+  #error "If you want to use DHCP, you have to define LWIP_UDP=1 in your lwipopts.h"
+#endif
+#if (!LWIP_UDP && LWIP_IGMP)
+  #error "If you want to use IGMP, you have to define LWIP_UDP=1 in your lwipopts.h"
+#endif
+#if (!LWIP_UDP && LWIP_DNS)
+  #error "If you want to use DNS, you have to define LWIP_UDP=1 in your lwipopts.h"
+#endif
+#if (LWIP_ARP && (ARP_TABLE_SIZE > 0x7f))
+  #error "If you want to use ARP, ARP_TABLE_SIZE must fit in an s8_t, so, you have to reduce it in your lwipopts.h"
+#endif
+#if (LWIP_ARP && ARP_QUEUEING && (MEMP_NUM_ARP_QUEUE<=0))
+  #error "If you want to use ARP Queueing, you have to define MEMP_NUM_ARP_QUEUE>=1 in your lwipopts.h"
+#endif
+#if (LWIP_RAW && (MEMP_NUM_RAW_PCB<=0))
+  #error "If you want to use RAW, you have to define MEMP_NUM_RAW_PCB>=1 in your lwipopts.h"
+#endif
+#if (LWIP_UDP && (MEMP_NUM_UDP_PCB<=0))
+  #error "If you want to use UDP, you have to define MEMP_NUM_UDP_PCB>=1 in your lwipopts.h"
+#endif
+#if (LWIP_TCP && (MEMP_NUM_TCP_PCB<=0))
+  #error "If you want to use TCP, you have to define MEMP_NUM_TCP_PCB>=1 in your lwipopts.h"
+#endif
+#if (LWIP_TCP && (TCP_WND > 0xffff))
+  #error "If you want to use TCP, TCP_WND must fit in an u16_t, so, you have to reduce it in your lwipopts.h"
+#endif
+#if (LWIP_TCP && (TCP_SND_QUEUELEN > 0xffff))
+  #error "If you want to use TCP, TCP_SND_QUEUELEN must fit in an u16_t, so, you have to reduce it in your lwipopts.h"
+#endif
+#if (LWIP_TCP && ((TCP_MAXRTX > 12) || (TCP_SYNMAXRTX > 12)))
+  #error "If you want to use TCP, TCP_MAXRTX and TCP_SYNMAXRTX must less or equal to 12 (due to tcp_backoff table), so, you have to reduce them in your lwipopts.h"
+#endif
+#if (LWIP_TCP && TCP_LISTEN_BACKLOG && (TCP_DEFAULT_LISTEN_BACKLOG < 0) || (TCP_DEFAULT_LISTEN_BACKLOG > 0xff))
+  #error "If you want to use TCP backlog, TCP_DEFAULT_LISTEN_BACKLOG must fit into an u8_t"
+#endif
+#if (LWIP_IGMP && (MEMP_NUM_IGMP_GROUP<=1))
+  #error "If you want to use IGMP, you have to define MEMP_NUM_IGMP_GROUP>1 in your lwipopts.h"
+#endif
+#if (PPP_SUPPORT && (NO_SYS==1))
+  #error "If you want to use PPP, you have to define NO_SYS=0 in your lwipopts.h"
+#endif 
+#if (LWIP_NETIF_API && (NO_SYS==1))
+  #error "If you want to use NETIF API, you have to define NO_SYS=0 in your lwipopts.h"
+#endif
+#if ((LWIP_SOCKET || LWIP_NETCONN) && (NO_SYS==1))
+  #error "If you want to use Sequential API, you have to define NO_SYS=0 in your lwipopts.h"
+#endif
+#if ((LWIP_NETCONN || LWIP_SOCKET) && (MEMP_NUM_TCPIP_MSG_API<=0))
+  #error "If you want to use Sequential API, you have to define MEMP_NUM_TCPIP_MSG_API>=1 in your lwipopts.h"
+#endif
+#if (!LWIP_NETCONN && LWIP_SOCKET)
+  #error "If you want to use Socket API, you have to define LWIP_NETCONN=1 in your lwipopts.h"
+#endif
+#if (((!LWIP_DHCP) || (!LWIP_AUTOIP)) && LWIP_DHCP_AUTOIP_COOP)
+  #error "If you want to use DHCP/AUTOIP cooperation mode, you have to define LWIP_DHCP=1 and LWIP_AUTOIP=1 in your lwipopts.h"
+#endif
+#if (((!LWIP_DHCP) || (!LWIP_ARP)) && DHCP_DOES_ARP_CHECK)
+  #error "If you want to use DHCP ARP checking, you have to define LWIP_DHCP=1 and LWIP_ARP=1 in your lwipopts.h"
+#endif
+#if (!LWIP_ARP && LWIP_AUTOIP)
+  #error "If you want to use AUTOIP, you have to define LWIP_ARP=1 in your lwipopts.h"
+#endif
+#if (LWIP_SNMP && (SNMP_CONCURRENT_REQUESTS<=0))
+  #error "If you want to use SNMP, you have to define SNMP_CONCURRENT_REQUESTS>=1 in your lwipopts.h"
+#endif
+#if (LWIP_SNMP && (SNMP_TRAP_DESTINATIONS<=0))
+  #error "If you want to use SNMP, you have to define SNMP_TRAP_DESTINATIONS>=1 in your lwipopts.h"
+#endif
+#if (LWIP_TCP && ((LWIP_EVENT_API && LWIP_CALLBACK_API) || (!LWIP_EVENT_API && !LWIP_CALLBACK_API)))
+  #error "One and exactly one of LWIP_EVENT_API and LWIP_CALLBACK_API has to be enabled in your lwipopts.h"
+#endif
+/* There must be sufficient timeouts, taking into account requirements of the subsystems. */
+#if ((NO_SYS==0) && (MEMP_NUM_SYS_TIMEOUT < (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + PPP_SUPPORT)))
+  #error "MEMP_NUM_SYS_TIMEOUT is too low to accomodate all required timeouts"
+#endif
+#if (IP_REASSEMBLY && (MEMP_NUM_REASSDATA > IP_REASS_MAX_PBUFS))
+  #error "MEMP_NUM_REASSDATA > IP_REASS_MAX_PBUFS doesn't make sense since each struct ip_reassdata must hold 2 pbufs at least!"
+#endif
+#if (MEM_LIBC_MALLOC && MEM_USE_POOLS)
+  #error "MEM_LIBC_MALLOC and MEM_USE_POOLS may not both be simultaneously enabled in your lwipopts.h"
+#endif
+#if (MEM_USE_POOLS && !MEMP_USE_CUSTOM_POOLS)
+  #error "MEM_USE_POOLS requires custom pools (MEMP_USE_CUSTOM_POOLS) to be enabled in your lwipopts.h"
+#endif
+#if (PBUF_POOL_BUFSIZE <= MEM_ALIGNMENT)
+  #error "PBUF_POOL_BUFSIZE must be greater than MEM_ALIGNMENT or the offset may take the full first pbuf"
+#endif
+#if (TCP_QUEUE_OOSEQ && !LWIP_TCP)
+  #error "TCP_QUEUE_OOSEQ requires LWIP_TCP"
+#endif
+#if (DNS_LOCAL_HOSTLIST && !DNS_LOCAL_HOSTLIST_IS_DYNAMIC && !(defined(DNS_LOCAL_HOSTLIST_INIT)))
+  #error "you have to define define DNS_LOCAL_HOSTLIST_INIT {{'host1', 0x123}, {'host2', 0x234}} to initialize DNS_LOCAL_HOSTLIST"
+#endif
+#if PPP_SUPPORT && !PPPOS_SUPPORT & !PPPOE_SUPPORT
+  #error "PPP_SUPPORT needs either PPPOS_SUPPORT or PPPOE_SUPPORT turned on"
+#endif
+
+
+/* Compile-time checks for deprecated options.
+ */
+#ifdef MEMP_NUM_TCPIP_MSG
+  #error "MEMP_NUM_TCPIP_MSG option is deprecated. Remove it from your lwipopts.h."
+#endif
+#ifdef MEMP_NUM_API_MSG
+  #error "MEMP_NUM_API_MSG option is deprecated. Remove it from your lwipopts.h."
+#endif
+#ifdef TCP_REXMIT_DEBUG
+  #error "TCP_REXMIT_DEBUG option is deprecated. Remove it from your lwipopts.h."
+#endif
+#ifdef RAW_STATS
+  #error "RAW_STATS option is deprecated. Remove it from your lwipopts.h."
+#endif
+#ifdef ETHARP_QUEUE_FIRST
+  #error "ETHARP_QUEUE_FIRST option is deprecated. Remove it from your lwipopts.h."
+#endif
+#ifdef ETHARP_ALWAYS_INSERT
+  #error "ETHARP_ALWAYS_INSERT option is deprecated. Remove it from your lwipopts.h."
+#endif
+#if SO_REUSE
+/* I removed the lot since this was an ugly hack. It broke the raw-API.
+   It also came with many ugly goto's, Christiaan Simons. */
+  #error "SO_REUSE currently unavailable, this was a hack"
+#endif
+
+#ifdef LWIP_DEBUG
+static void
+lwip_sanity_check(void)
+{
+  /* Warnings */
+#if LWIP_NETCONN
+  if (MEMP_NUM_NETCONN > (MEMP_NUM_TCP_PCB+MEMP_NUM_TCP_PCB_LISTEN+MEMP_NUM_UDP_PCB+MEMP_NUM_RAW_PCB))
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: MEMP_NUM_NETCONN should be less than the sum of MEMP_NUM_{TCP,RAW,UDP}_PCB+MEMP_NUM_TCP_PCB_LISTEN\n"));
+#endif /* LWIP_NETCONN */
+#if LWIP_TCP
+  if (MEMP_NUM_TCP_SEG < TCP_SND_QUEUELEN)
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: MEMP_NUM_TCP_SEG should be at least as big as TCP_SND_QUEUELEN\n"));
+  if (TCP_SND_BUF < 2 * TCP_MSS)
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_SND_BUF must be at least as much as (2 * TCP_MSS) for things to work smoothly\n"));
+  if (TCP_SND_QUEUELEN < (2 * (TCP_SND_BUF/TCP_MSS)))
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_SND_QUEUELEN must be at least as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work\n"));
+  if (TCP_SNDLOWAT > TCP_SND_BUF)
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_SNDLOWAT must be less than or equal to TCP_SND_BUF.\n"));
+  if (TCP_WND > (PBUF_POOL_SIZE*PBUF_POOL_BUFSIZE))
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_WND is larger than space provided by PBUF_POOL_SIZE*PBUF_POOL_BUFSIZE\n"));
+  if (TCP_WND < TCP_MSS)
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_WND is smaller than MSS\n"));
+#endif /* LWIP_TCP */
+}
+#else  /* LWIP_DEBUG */
+#define lwip_sanity_check()
+#endif /* LWIP_DEBUG */
+
+/**
+ * Perform Sanity check of user-configurable values, and initialize all modules.
+ */
+void
+lwip_init(void)
+{
+  /* Sanity check user-configurable values */
+  lwip_sanity_check();
+
+  /* Modules initialization */
+  stats_init();
+  sys_init();
+  mem_init();
+  memp_init();
+  pbuf_init();
+  netif_init();
+#if LWIP_SOCKET
+  lwip_socket_init();
+#endif /* LWIP_SOCKET */
+  ip_init();
+#if LWIP_ARP
+  etharp_init();
+#endif /* LWIP_ARP */
+#if LWIP_RAW
+  raw_init();
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+  udp_init();
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+  tcp_init();
+#endif /* LWIP_TCP */
+#if LWIP_SNMP
+  snmp_init();
+#endif /* LWIP_SNMP */
+#if LWIP_AUTOIP
+  autoip_init();
+#endif /* LWIP_AUTOIP */
+#if LWIP_IGMP
+  igmp_init();
+#endif /* LWIP_IGMP */
+#if LWIP_DNS
+  dns_init();
+#endif /* LWIP_DNS */
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/autoip.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/autoip.c
new file mode 100644
index 0000000..7aa7cea
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/autoip.c
@@ -0,0 +1,497 @@
+/**
+ * @file
+ * AutoIP Automatic LinkLocal IP Configuration
+ *
+ */
+
+/*
+ *
+ * Copyright (c) 2007 Dominik Spies 
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Dominik Spies 
+ *
+ * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform
+ * with RFC 3927.
+ *
+ *
+ * Please coordinate changes and requests with Dominik Spies
+ * 
+ */
+
+/*******************************************************************************
+ * USAGE:
+ * 
+ * define LWIP_AUTOIP 1  in your lwipopts.h
+ * 
+ * If you don't use tcpip.c (so, don't call, you don't call tcpip_init):
+ * - First, call autoip_init().
+ * - call autoip_tmr() all AUTOIP_TMR_INTERVAL msces,
+ *   that should be defined in autoip.h.
+ *   I recommend a value of 100. The value must divide 1000 with a remainder almost 0.
+ *   Possible values are 1000, 500, 333, 250, 200, 166, 142, 125, 111, 100 ....
+ *
+ * Without DHCP:
+ * - Call autoip_start() after netif_add().
+ * 
+ * With DHCP:
+ * - define LWIP_DHCP_AUTOIP_COOP 1 in your lwipopts.h.
+ * - Configure your DHCP Client.
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_AUTOIP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/mem.h"
+#include "lwip/udp.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/autoip.h"
+#include "netif/etharp.h"
+
+#include 
+#include 
+
+/* 169.254.0.0 */
+#define AUTOIP_NET         0xA9FE0000
+/* 169.254.1.0 */
+#define AUTOIP_RANGE_START (AUTOIP_NET | 0x0100)
+/* 169.254.254.255 */
+#define AUTOIP_RANGE_END   (AUTOIP_NET | 0xFEFF)
+
+
+/** Pseudo random macro based on netif informations.
+ * You could use "rand()" from the C Library if you define LWIP_AUTOIP_RAND in lwipopts.h */
+#ifndef LWIP_AUTOIP_RAND
+#define LWIP_AUTOIP_RAND(netif) ( (((u32_t)((netif->hwaddr[5]) & 0xff) << 24) | \
+                                   ((u32_t)((netif->hwaddr[3]) & 0xff) << 16) | \
+                                   ((u32_t)((netif->hwaddr[2]) & 0xff) << 8) | \
+                                   ((u32_t)((netif->hwaddr[4]) & 0xff))) + \
+                                   (netif->autoip?netif->autoip->tried_llipaddr:0))
+#endif /* LWIP_AUTOIP_RAND */
+
+/**
+ * Macro that generates the initial IP address to be tried by AUTOIP.
+ * If you want to override this, define it to something else in lwipopts.h.
+ */
+#ifndef LWIP_AUTOIP_CREATE_SEED_ADDR
+#define LWIP_AUTOIP_CREATE_SEED_ADDR(netif) \
+  htonl(AUTOIP_RANGE_START + ((u32_t)(((u8_t)(netif->hwaddr[4])) | \
+                 ((u32_t)((u8_t)(netif->hwaddr[5]))) << 8)))
+#endif /* LWIP_AUTOIP_CREATE_SEED_ADDR */
+
+/* static functions */
+static void autoip_handle_arp_conflict(struct netif *netif);
+
+/* creates a pseudo random LL IP-Address for a network interface */
+static void autoip_create_addr(struct netif *netif, struct ip_addr *ipaddr);
+
+/* sends an ARP probe */
+static err_t autoip_arp_probe(struct netif *netif);
+
+/* sends an ARP announce */
+static err_t autoip_arp_announce(struct netif *netif);
+
+/* configure interface for use with current LL IP-Address */
+static err_t autoip_bind(struct netif *netif);
+
+/* start sending probes for llipaddr */
+static void autoip_start_probing(struct netif *netif);
+
+/**
+ * Initialize this module
+ */
+void
+autoip_init(void)
+{
+  LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, ("autoip_init()\n"));
+}
+
+/**
+ * Handle a IP address conflict after an ARP conflict detection
+ */
+static void
+autoip_handle_arp_conflict(struct netif *netif)
+{
+  /* Somehow detect if we are defending or retreating */
+  unsigned char defend = 1; /* tbd */
+
+  if(defend) {
+    if(netif->autoip->lastconflict > 0) {
+      /* retreat, there was a conflicting ARP in the last
+       * DEFEND_INTERVAL seconds
+       */
+      LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+        ("autoip_handle_arp_conflict(): we are defending, but in DEFEND_INTERVAL, retreating\n"));
+
+      /* TODO: close all TCP sessions */
+      autoip_start(netif);
+    } else {
+      LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+        ("autoip_handle_arp_conflict(): we are defend, send ARP Announce\n"));
+      autoip_arp_announce(netif);
+      netif->autoip->lastconflict = DEFEND_INTERVAL * AUTOIP_TICKS_PER_SECOND;
+    }
+  } else {
+    LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+      ("autoip_handle_arp_conflict(): we do not defend, retreating\n"));
+    /* TODO: close all TCP sessions */
+    autoip_start(netif);
+  }
+}
+
+/**
+ * Create an IP-Address out of range 169.254.1.0 to 169.254.254.255
+ *
+ * @param netif network interface on which create the IP-Address
+ * @param ipaddr ip address to initialize
+ */
+static void
+autoip_create_addr(struct netif *netif, struct ip_addr *ipaddr)
+{
+  /* Here we create an IP-Address out of range 169.254.1.0 to 169.254.254.255
+   * compliant to RFC 3927 Section 2.1
+   * We have 254 * 256 possibilities */
+
+  u32_t addr = ntohl(LWIP_AUTOIP_CREATE_SEED_ADDR(netif));
+  addr += netif->autoip->tried_llipaddr;
+  addr = AUTOIP_NET | (addr & 0xffff);
+  /* Now, 169.254.0.0 <= addr <= 169.254.255.255 */ 
+
+  if (addr < AUTOIP_RANGE_START) {
+    addr += AUTOIP_RANGE_END - AUTOIP_RANGE_START + 1;
+  }
+  if (addr > AUTOIP_RANGE_END) {
+    addr -= AUTOIP_RANGE_END - AUTOIP_RANGE_START + 1;
+  }
+  LWIP_ASSERT("AUTOIP address not in range", (addr >= AUTOIP_RANGE_START) &&
+    (addr <= AUTOIP_RANGE_END));
+  ipaddr->addr = htonl(addr);
+  
+  LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+    ("autoip_create_addr(): tried_llipaddr=%"U16_F", 0x%08"X32_F"\n",
+    (u16_t)(netif->autoip->tried_llipaddr), (u32_t)(ipaddr->addr)));
+}
+
+/**
+ * Sends an ARP probe from a network interface
+ *
+ * @param netif network interface used to send the probe
+ */
+static err_t
+autoip_arp_probe(struct netif *netif)
+{
+  return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, ðbroadcast,
+    (struct eth_addr *)netif->hwaddr, IP_ADDR_ANY, ðzero,
+    &netif->autoip->llipaddr, ARP_REQUEST);
+}
+
+/**
+ * Sends an ARP announce from a network interface
+ *
+ * @param netif network interface used to send the announce
+ */
+static err_t
+autoip_arp_announce(struct netif *netif)
+{
+  return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, ðbroadcast,
+    (struct eth_addr *)netif->hwaddr, &netif->autoip->llipaddr, ðzero,
+    &netif->autoip->llipaddr, ARP_REQUEST);
+}
+
+/**
+ * Configure interface for use with current LL IP-Address
+ *
+ * @param netif network interface to configure with current LL IP-Address
+ */
+static err_t
+autoip_bind(struct netif *netif)
+{
+  struct autoip *autoip = netif->autoip;
+  struct ip_addr sn_mask, gw_addr;
+
+  LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE,
+    ("autoip_bind(netif=%p) %c%c%"U16_F" 0x%08"X32_F"\n",
+    (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num, autoip->llipaddr.addr));
+
+  IP4_ADDR(&sn_mask, 255, 255, 0, 0);
+  IP4_ADDR(&gw_addr, 0, 0, 0, 0);
+
+  netif_set_ipaddr(netif, &autoip->llipaddr);
+  netif_set_netmask(netif, &sn_mask);
+  netif_set_gw(netif, &gw_addr);  
+
+  /* bring the interface up */
+  netif_set_up(netif);
+
+  return ERR_OK;
+}
+
+/**
+ * Start AutoIP client
+ *
+ * @param netif network interface on which start the AutoIP client
+ */
+err_t
+autoip_start(struct netif *netif)
+{
+  struct autoip *autoip = netif->autoip;
+  err_t result = ERR_OK;
+
+  if(netif_is_up(netif)) {
+    netif_set_down(netif);
+  }
+
+  /* Set IP-Address, Netmask and Gateway to 0 to make sure that
+   * ARP Packets are formed correctly
+   */
+  netif->ip_addr.addr = 0;
+  netif->netmask.addr = 0;
+  netif->gw.addr      = 0;
+
+  LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+    ("autoip_start(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0],
+    netif->name[1], (u16_t)netif->num));
+  if(autoip == NULL) {
+    /* no AutoIP client attached yet? */
+    LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE,
+      ("autoip_start(): starting new AUTOIP client\n"));
+    autoip = mem_malloc(sizeof(struct autoip));
+    if(autoip == NULL) {
+      LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE,
+        ("autoip_start(): could not allocate autoip\n"));
+      return ERR_MEM;
+    }
+    memset( autoip, 0, sizeof(struct autoip));
+    /* store this AutoIP client in the netif */
+    netif->autoip = autoip;
+    LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, ("autoip_start(): allocated autoip"));
+  } else {
+    autoip->state = AUTOIP_STATE_OFF;
+    autoip->ttw = 0;
+    autoip->sent_num = 0;
+    memset(&autoip->llipaddr, 0, sizeof(struct ip_addr));
+    autoip->lastconflict = 0;
+  }
+
+  autoip_create_addr(netif, &(autoip->llipaddr));
+  autoip->tried_llipaddr++;
+  autoip_start_probing(netif);
+
+  return result;
+}
+
+static void
+autoip_start_probing(struct netif *netif)
+{
+  struct autoip *autoip = netif->autoip;
+
+  autoip->state = AUTOIP_STATE_PROBING;
+  autoip->sent_num = 0;
+
+  /* time to wait to first probe, this is randomly
+   * choosen out of 0 to PROBE_WAIT seconds.
+   * compliant to RFC 3927 Section 2.2.1
+   */
+  autoip->ttw = (u16_t)(LWIP_AUTOIP_RAND(netif) % (PROBE_WAIT * AUTOIP_TICKS_PER_SECOND));
+
+  /*
+   * if we tried more then MAX_CONFLICTS we must limit our rate for
+   * accquiring and probing address
+   * compliant to RFC 3927 Section 2.2.1
+   */
+  if(autoip->tried_llipaddr > MAX_CONFLICTS) {
+    autoip->ttw = RATE_LIMIT_INTERVAL * AUTOIP_TICKS_PER_SECOND;
+  }
+}
+
+/**
+ * Handle a possible change in the network configuration.
+ *
+ * If there is an AutoIP address configured, take the interface down
+ * and begin probing with the same address.
+ */
+void
+autoip_network_changed(struct netif *netif)
+{
+  if (netif->autoip && netif->autoip->state != AUTOIP_STATE_OFF) {
+    netif_set_down(netif);
+    autoip_start_probing(netif);
+  }
+}
+
+/**
+ * Stop AutoIP client
+ *
+ * @param netif network interface on which stop the AutoIP client
+ */
+err_t
+autoip_stop(struct netif *netif)
+{
+  netif->autoip->state = AUTOIP_STATE_OFF;
+  netif_set_down(netif);
+  return ERR_OK;
+}
+
+/**
+ * Has to be called in loop every AUTOIP_TMR_INTERVAL milliseconds
+ */
+void
+autoip_tmr()
+{
+  struct netif *netif = netif_list;
+  /* loop through netif's */
+  while (netif != NULL) {
+    /* only act on AutoIP configured interfaces */
+    if (netif->autoip != NULL) {
+      if(netif->autoip->lastconflict > 0) {
+        netif->autoip->lastconflict--;
+      }
+
+      LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE,
+        ("autoip_tmr() AutoIP-State: %"U16_F", ttw=%"U16_F"\n",
+        (u16_t)(netif->autoip->state), netif->autoip->ttw));
+
+      switch(netif->autoip->state) {
+        case AUTOIP_STATE_PROBING:
+          if(netif->autoip->ttw > 0) {
+            netif->autoip->ttw--;
+          } else {
+            if(netif->autoip->sent_num >= PROBE_NUM) {
+              netif->autoip->state = AUTOIP_STATE_ANNOUNCING;
+              netif->autoip->sent_num = 0;
+              netif->autoip->ttw = ANNOUNCE_WAIT * AUTOIP_TICKS_PER_SECOND;
+            } else {
+              autoip_arp_probe(netif);
+              LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE,
+                ("autoip_tmr() PROBING Sent Probe\n"));
+              netif->autoip->sent_num++;
+              /* calculate time to wait to next probe */
+              netif->autoip->ttw = (u16_t)((LWIP_AUTOIP_RAND(netif) %
+                ((PROBE_MAX - PROBE_MIN) * AUTOIP_TICKS_PER_SECOND) ) +
+                PROBE_MIN * AUTOIP_TICKS_PER_SECOND);
+            }
+          }
+          break;
+
+        case AUTOIP_STATE_ANNOUNCING:
+          if(netif->autoip->ttw > 0) {
+            netif->autoip->ttw--;
+          } else {
+            if(netif->autoip->sent_num == 0) {
+             /* We are here the first time, so we waited ANNOUNCE_WAIT seconds
+              * Now we can bind to an IP address and use it.
+              *
+              * autoip_bind calls netif_set_up. This triggers a gratuitous ARP
+              * which counts as an announcement.
+              */
+              autoip_bind(netif);
+            } else {
+              autoip_arp_announce(netif);
+              LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE,
+                ("autoip_tmr() ANNOUNCING Sent Announce\n"));
+            }
+            netif->autoip->ttw = ANNOUNCE_INTERVAL * AUTOIP_TICKS_PER_SECOND;
+            netif->autoip->sent_num++;
+
+            if(netif->autoip->sent_num >= ANNOUNCE_NUM) {
+                netif->autoip->state = AUTOIP_STATE_BOUND;
+                netif->autoip->sent_num = 0;
+                netif->autoip->ttw = 0;
+            }
+          }
+          break;
+      }
+    }
+    /* proceed to next network interface */
+    netif = netif->next;
+  }
+}
+
+/**
+ * Handles every incoming ARP Packet, called by etharp_arp_input.
+ *
+ * @param netif network interface to use for autoip processing
+ * @param hdr Incoming ARP packet
+ */
+void
+autoip_arp_reply(struct netif *netif, struct etharp_hdr *hdr)
+{
+  LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, ("autoip_arp_reply()\n"));
+  if ((netif->autoip != NULL) && (netif->autoip->state != AUTOIP_STATE_OFF)) {
+   /* when ip.src == llipaddr && hw.src != netif->hwaddr
+    *
+    * when probing  ip.dst == llipaddr && hw.src != netif->hwaddr
+    * we have a conflict and must solve it
+    */
+    struct ip_addr sipaddr, dipaddr;
+    struct eth_addr netifaddr;
+    netifaddr.addr[0] = netif->hwaddr[0];
+    netifaddr.addr[1] = netif->hwaddr[1];
+    netifaddr.addr[2] = netif->hwaddr[2];
+    netifaddr.addr[3] = netif->hwaddr[3];
+    netifaddr.addr[4] = netif->hwaddr[4];
+    netifaddr.addr[5] = netif->hwaddr[5];
+
+    /* Copy struct ip_addr2 to aligned ip_addr, to support compilers without
+     * structure packing (not using structure copy which breaks strict-aliasing rules).
+     */
+    SMEMCPY(&sipaddr, &hdr->sipaddr, sizeof(sipaddr));
+    SMEMCPY(&dipaddr, &hdr->dipaddr, sizeof(dipaddr));
+      
+    if ((netif->autoip->state == AUTOIP_STATE_PROBING) ||
+        ((netif->autoip->state == AUTOIP_STATE_ANNOUNCING) &&
+         (netif->autoip->sent_num == 0))) {
+     /* RFC 3927 Section 2.2.1:
+      * from beginning to after ANNOUNCE_WAIT
+      * seconds we have a conflict if
+      * ip.src == llipaddr OR
+      * ip.dst == llipaddr && hw.src != own hwaddr
+      */
+      if ((ip_addr_cmp(&sipaddr, &netif->autoip->llipaddr)) ||
+          (ip_addr_cmp(&dipaddr, &netif->autoip->llipaddr) &&
+           !eth_addr_cmp(&netifaddr, &hdr->shwaddr))) {
+        LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING,
+          ("autoip_arp_reply(): Probe Conflict detected\n"));
+        autoip_start(netif);
+      }
+    } else {
+     /* RFC 3927 Section 2.5:
+      * in any state we have a conflict if
+      * ip.src == llipaddr && hw.src != own hwaddr
+      */
+      if (ip_addr_cmp(&sipaddr, &netif->autoip->llipaddr) &&
+          !eth_addr_cmp(&netifaddr, &hdr->shwaddr)) {
+        LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING,
+          ("autoip_arp_reply(): Conflicting ARP-Packet detected\n"));
+        autoip_handle_arp_conflict(netif);
+      }
+    }
+  }
+}
+
+#endif /* LWIP_AUTOIP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/icmp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/icmp.c
new file mode 100644
index 0000000..b97a587
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/icmp.c
@@ -0,0 +1,331 @@
+/**
+ * @file
+ * ICMP - Internet Control Message Protocol
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* Some ICMP messages should be passed to the transport protocols. This
+   is not implemented. */
+
+#include "lwip/opt.h"
+
+#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/icmp.h"
+#include "lwip/inet.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/ip.h"
+#include "lwip/def.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+
+#include 
+
+/** Small optimization: set to 0 if incoming PBUF_POOL pbuf always can be
+ * used to modify and send a response packet (and to 1 if this is not the case,
+ * e.g. when link header is stripped of when receiving) */
+#ifndef LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN
+#define LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN 1
+#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */
+
+/* The amount of data from the original packet to return in a dest-unreachable */
+#define ICMP_DEST_UNREACH_DATASIZE 8
+
+static void icmp_send_response(struct pbuf *p, u8_t type, u8_t code);
+
+/**
+ * Processes ICMP input packets, called from ip_input().
+ *
+ * Currently only processes icmp echo requests and sends
+ * out the echo response.
+ *
+ * @param p the icmp echo request packet, p->payload pointing to the ip header
+ * @param inp the netif on which this packet was received
+ */
+void
+icmp_input(struct pbuf *p, struct netif *inp)
+{
+  u8_t type;
+#ifdef LWIP_DEBUG
+  u8_t code;
+#endif /* LWIP_DEBUG */
+  struct icmp_echo_hdr *iecho;
+  struct ip_hdr *iphdr;
+  struct ip_addr tmpaddr;
+  s16_t hlen;
+
+  ICMP_STATS_INC(icmp.recv);
+  snmp_inc_icmpinmsgs();
+
+
+  iphdr = p->payload;
+  hlen = IPH_HL(iphdr) * 4;
+  if (pbuf_header(p, -hlen) || (p->tot_len < sizeof(u16_t)*2)) {
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len));
+    goto lenerr;
+  }
+
+  type = *((u8_t *)p->payload);
+#ifdef LWIP_DEBUG
+  code = *(((u8_t *)p->payload)+1);
+#endif /* LWIP_DEBUG */
+  switch (type) {
+  case ICMP_ECHO:
+#if !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING
+    {
+      int accepted = 1;
+#if !LWIP_MULTICAST_PING
+      /* multicast destination address? */
+      if (ip_addr_ismulticast(&iphdr->dest)) {
+        accepted = 0;
+      }
+#endif /* LWIP_MULTICAST_PING */
+#if !LWIP_BROADCAST_PING
+      /* broadcast destination address? */
+      if (ip_addr_isbroadcast(&iphdr->dest, inp)) {
+        accepted = 0;
+      }
+#endif /* LWIP_BROADCAST_PING */
+      /* broadcast or multicast destination address not acceptd? */
+      if (!accepted) {
+        LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast or broadcast pings\n"));
+        ICMP_STATS_INC(icmp.err);
+        pbuf_free(p);
+        return;
+      }
+    }
+#endif /* !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING */
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
+    if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n"));
+      goto lenerr;
+    }
+    if (inet_chksum_pbuf(p) != 0) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n"));
+      pbuf_free(p);
+      ICMP_STATS_INC(icmp.chkerr);
+      snmp_inc_icmpinerrors();
+      return;
+    }
+#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN
+    if (pbuf_header(p, (PBUF_IP_HLEN + PBUF_LINK_HLEN))) {
+      /* p is not big enough to contain link headers
+       * allocate a new one and copy p into it
+       */
+      struct pbuf *r;
+      /* switch p->payload to ip header */
+      if (pbuf_header(p, hlen)) {
+        LWIP_ASSERT("icmp_input: moving p->payload to ip header failed\n", 0);
+        goto memerr;
+      }
+      /* allocate new packet buffer with space for link headers */
+      r = pbuf_alloc(PBUF_LINK, p->tot_len, PBUF_RAM);
+      if (r == NULL) {
+        LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed\n"));
+        goto memerr;
+      }
+      LWIP_ASSERT("check that first pbuf can hold struct the ICMP header",
+                  (r->len >= hlen + sizeof(struct icmp_echo_hdr)));
+      /* copy the whole packet including ip header */
+      if (pbuf_copy(r, p) != ERR_OK) {
+        LWIP_ASSERT("icmp_input: copying to new pbuf failed\n", 0);
+        goto memerr;
+      }
+      iphdr = r->payload;
+      /* switch r->payload back to icmp header */
+      if (pbuf_header(r, -hlen)) {
+        LWIP_ASSERT("icmp_input: restoring original p->payload failed\n", 0);
+        goto memerr;
+      }
+      /* free the original p */
+      pbuf_free(p);
+      /* we now have an identical copy of p that has room for link headers */
+      p = r;
+    } else {
+      /* restore p->payload to point to icmp header */
+      if (pbuf_header(p, -(s16_t)(PBUF_IP_HLEN + PBUF_LINK_HLEN))) {
+        LWIP_ASSERT("icmp_input: restoring original p->payload failed\n", 0);
+        goto memerr;
+      }
+    }
+#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */
+    /* At this point, all checks are OK. */
+    /* We generate an answer by switching the dest and src ip addresses,
+     * setting the icmp type to ECHO_RESPONSE and updating the checksum. */
+    iecho = p->payload;
+    tmpaddr.addr = iphdr->src.addr;
+    iphdr->src.addr = iphdr->dest.addr;
+    iphdr->dest.addr = tmpaddr.addr;
+    ICMPH_TYPE_SET(iecho, ICMP_ER);
+    /* adjust the checksum */
+    if (iecho->chksum >= htons(0xffff - (ICMP_ECHO << 8))) {
+      iecho->chksum += htons(ICMP_ECHO << 8) + 1;
+    } else {
+      iecho->chksum += htons(ICMP_ECHO << 8);
+    }
+
+    /* Set the correct TTL and recalculate the header checksum. */
+    IPH_TTL_SET(iphdr, ICMP_TTL);
+    IPH_CHKSUM_SET(iphdr, 0);
+#if CHECKSUM_GEN_IP
+    IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
+#endif /* CHECKSUM_GEN_IP */
+
+    ICMP_STATS_INC(icmp.xmit);
+    /* increase number of messages attempted to send */
+    snmp_inc_icmpoutmsgs();
+    /* increase number of echo replies attempted to send */
+    snmp_inc_icmpoutechoreps();
+
+    if(pbuf_header(p, hlen)) {
+      LWIP_ASSERT("Can't move over header in packet", 0);
+    } else {
+      err_t ret;
+      ret = ip_output_if(p, &(iphdr->src), IP_HDRINCL,
+                   ICMP_TTL, 0, IP_PROTO_ICMP, inp);
+      if (ret != ERR_OK) {
+        LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ip_output_if returned an error: %c.\n", ret));
+      }
+    }
+    break;
+  default:
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n", 
+                (s16_t)type, (s16_t)code));
+    ICMP_STATS_INC(icmp.proterr);
+    ICMP_STATS_INC(icmp.drop);
+  }
+  pbuf_free(p);
+  return;
+lenerr:
+  pbuf_free(p);
+  ICMP_STATS_INC(icmp.lenerr);
+  snmp_inc_icmpinerrors();
+  return;
+#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN
+memerr:
+  pbuf_free(p);
+  ICMP_STATS_INC(icmp.err);
+  snmp_inc_icmpinerrors();
+  return;
+#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */
+}
+
+/**
+ * Send an icmp 'destination unreachable' packet, called from ip_input() if
+ * the transport layer protocol is unknown and from udp_input() if the local
+ * port is not bound.
+ *
+ * @param p the input packet for which the 'unreachable' should be sent,
+ *          p->payload pointing to the IP header
+ * @param t type of the 'unreachable' packet
+ */
+void
+icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
+{
+  icmp_send_response(p, ICMP_DUR, t);
+}
+
+#if IP_FORWARD || IP_REASSEMBLY
+/**
+ * Send a 'time exceeded' packet, called from ip_forward() if TTL is 0.
+ *
+ * @param p the input packet for which the 'time exceeded' should be sent,
+ *          p->payload pointing to the IP header
+ * @param t type of the 'time exceeded' packet
+ */
+void
+icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
+{
+  icmp_send_response(p, ICMP_TE, t);
+}
+
+#endif /* IP_FORWARD || IP_REASSEMBLY */
+
+/**
+ * Send an icmp packet in response to an incoming packet.
+ *
+ * @param p the input packet for which the 'unreachable' should be sent,
+ *          p->payload pointing to the IP header
+ * @param type Type of the ICMP header
+ * @param code Code of the ICMP header
+ */
+static void
+icmp_send_response(struct pbuf *p, u8_t type, u8_t code)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  /* we can use the echo header here */
+  struct icmp_echo_hdr *icmphdr;
+
+  /* ICMP header + IP header + 8 bytes of data */
+  q = pbuf_alloc(PBUF_IP, sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE,
+                 PBUF_RAM);
+  if (q == NULL) {
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded: failed to allocate pbuf for ICMP packet.\n"));
+    return;
+  }
+  LWIP_ASSERT("check that first pbuf can hold icmp message",
+             (q->len >= (sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE)));
+
+  iphdr = p->payload;
+  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded from "));
+  ip_addr_debug_print(ICMP_DEBUG, &(iphdr->src));
+  LWIP_DEBUGF(ICMP_DEBUG, (" to "));
+  ip_addr_debug_print(ICMP_DEBUG, &(iphdr->dest));
+  LWIP_DEBUGF(ICMP_DEBUG, ("\n"));
+
+  icmphdr = q->payload;
+  icmphdr->type = type;
+  icmphdr->code = code;
+  icmphdr->id = 0;
+  icmphdr->seqno = 0;
+
+  /* copy fields from original packet */
+  SMEMCPY((u8_t *)q->payload + sizeof(struct icmp_echo_hdr), (u8_t *)p->payload,
+          IP_HLEN + ICMP_DEST_UNREACH_DATASIZE);
+
+  /* calculate checksum */
+  icmphdr->chksum = 0;
+  icmphdr->chksum = inet_chksum(icmphdr, q->len);
+  ICMP_STATS_INC(icmp.xmit);
+  /* increase number of messages attempted to send */
+  snmp_inc_icmpoutmsgs();
+  /* increase number of destination unreachable messages attempted to send */
+  snmp_inc_icmpouttimeexcds();
+  ip_output(q, NULL, &(iphdr->src), ICMP_TTL, 0, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+#endif /* LWIP_ICMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/igmp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/igmp.c
new file mode 100644
index 0000000..7c07bc4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/igmp.c
@@ -0,0 +1,757 @@
+/**
+ * @file
+ * IGMP - Internet Group Management Protocol
+ *
+ */
+
+/*
+ * Copyright (c) 2002 CITEL Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS''
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is a contribution to the lwIP TCP/IP stack.
+ * The Swedish Institute of Computer Science and Adam Dunkels
+ * are specifically granted permission to redistribute this
+ * source code.
+*/
+
+/*-------------------------------------------------------------
+Note 1)
+Although the rfc requires V1 AND V2 capability
+we will only support v2 since now V1 is very old (August 1989)
+V1 can be added if required
+
+a debug print and statistic have been implemented to
+show this up.
+-------------------------------------------------------------
+-------------------------------------------------------------
+Note 2)
+A query for a specific group address (as opposed to ALLHOSTS)
+has now been implemented as I am unsure if it is required
+
+a debug print and statistic have been implemented to
+show this up.
+-------------------------------------------------------------
+-------------------------------------------------------------
+Note 3)
+The router alert rfc 2113 is implemented in outgoing packets
+but not checked rigorously incoming
+-------------------------------------------------------------
+Steve Reynolds
+------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------------
+ * RFC 988  - Host extensions for IP multicasting                         - V0
+ * RFC 1054 - Host extensions for IP multicasting                         -
+ * RFC 1112 - Host extensions for IP multicasting                         - V1
+ * RFC 2236 - Internet Group Management Protocol, Version 2               - V2  <- this code is based on this RFC (it's the "de facto" standard)
+ * RFC 3376 - Internet Group Management Protocol, Version 3               - V3
+ * RFC 4604 - Using Internet Group Management Protocol Version 3...       - V3+
+ * RFC 2113 - IP Router Alert Option                                      - 
+ *----------------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------------
+ * Includes
+ *----------------------------------------------------------------------------*/
+
+#include "lwip/opt.h"
+
+#if LWIP_IGMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/igmp.h"
+#include "lwip/debug.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/ip.h"
+#include "lwip/inet.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/netif.h"
+#include "lwip/icmp.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+#include "lwip/stats.h"
+
+#include "string.h"
+
+/*-----------------------------------------------------------------------------
+ * Globales
+ *----------------------------------------------------------------------------*/
+
+static struct igmp_group* igmp_group_list;
+static struct ip_addr     allsystems;
+static struct ip_addr     allrouters;
+
+/**
+ * Initialize the IGMP module
+ */
+void
+igmp_init(void)
+{
+  LWIP_DEBUGF(IGMP_DEBUG, ("igmp_init: initializing\n"));
+
+  IP4_ADDR(&allsystems, 224, 0, 0, 1);
+  IP4_ADDR(&allrouters, 224, 0, 0, 2);
+}
+
+#ifdef LWIP_DEBUG
+/**
+ * Dump global IGMP groups list
+ */
+void
+igmp_dump_group_list()
+{ 
+  struct igmp_group *group = igmp_group_list;
+
+  while (group != NULL) {
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_dump_group_list: [%"U32_F"] ", (u32_t)(group->group_state)));
+    ip_addr_debug_print(IGMP_DEBUG, &group->group_address);
+    LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", group->interface));
+    group = group->next;
+  }
+  LWIP_DEBUGF(IGMP_DEBUG, ("\n"));
+}
+#else
+#define igmp_dump_group_list()
+#endif /* LWIP_DEBUG */
+
+/**
+ * Start IGMP processing on interface
+ *
+ * @param netif network interface on which start IGMP processing
+ */
+err_t
+igmp_start(struct netif *netif)
+{
+  struct igmp_group* group;
+
+  LWIP_DEBUGF(IGMP_DEBUG, ("igmp_start: starting IGMP processing on if %p\n", netif));
+
+  group = igmp_lookup_group(netif, &allsystems);
+
+  if (group != NULL) {
+    group->group_state = IGMP_GROUP_IDLE_MEMBER;
+    group->use++;
+
+    /* Allow the igmp messages at the MAC level */
+    if (netif->igmp_mac_filter != NULL) {
+      LWIP_DEBUGF(IGMP_DEBUG, ("igmp_start: igmp_mac_filter(ADD "));
+      ip_addr_debug_print(IGMP_DEBUG, &allsystems);
+      LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", netif));
+      netif->igmp_mac_filter( netif, &allsystems, IGMP_ADD_MAC_FILTER);
+    }
+
+    return ERR_OK;
+  }
+
+  return ERR_MEM;
+}
+
+/**
+ * Stop IGMP processing on interface
+ *
+ * @param netif network interface on which stop IGMP processing
+ */
+err_t
+igmp_stop(struct netif *netif)
+{
+  struct igmp_group *group = igmp_group_list;
+  struct igmp_group *prev  = NULL;
+  struct igmp_group *next;
+
+  /* look for groups joined on this interface further down the list */
+  while (group != NULL) {
+    next = group->next;
+    /* is it a group joined on this interface? */
+    if (group->interface == netif) {
+      /* is it the first group of the list? */
+      if (group == igmp_group_list) {
+        igmp_group_list = next;
+      }
+      /* is there a "previous" group defined? */
+      if (prev != NULL) {
+        prev->next = next;
+      }
+      /* disable the group at the MAC level */
+      if (netif->igmp_mac_filter != NULL) {
+        LWIP_DEBUGF(IGMP_DEBUG, ("igmp_stop: igmp_mac_filter(DEL "));
+        ip_addr_debug_print(IGMP_DEBUG, &group->group_address);
+        LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", netif));
+        netif->igmp_mac_filter(netif, &(group->group_address), IGMP_DEL_MAC_FILTER);
+      }
+      /* free group */
+      memp_free(MEMP_IGMP_GROUP, group);
+    } else {
+      /* change the "previous" */
+      prev = group;
+    }
+    /* move to "next" */
+    group = next;
+  }
+  return ERR_OK;
+}
+
+/**
+ * Report IGMP memberships for this interface
+ *
+ * @param netif network interface on which report IGMP memberships
+ */
+void
+igmp_report_groups( struct netif *netif)
+{
+  struct igmp_group *group = igmp_group_list;
+
+  LWIP_DEBUGF(IGMP_DEBUG, ("igmp_report_groups: sending IGMP reports on if %p\n", netif));
+
+  while (group != NULL) {
+    if (group->interface == netif) {
+      igmp_delaying_member( group, IGMP_JOIN_DELAYING_MEMBER_TMR);
+    }
+    group = group->next;
+  }
+}
+
+/**
+ * Search for a group in the global igmp_group_list
+ *
+ * @param ifp the network interface for which to look
+ * @param addr the group ip address to search for
+ * @return a struct igmp_group* if the group has been found,
+ *         NULL if the group wasn't found.
+ */
+struct igmp_group *
+igmp_lookfor_group(struct netif *ifp, struct ip_addr *addr)
+{
+  struct igmp_group *group = igmp_group_list;
+
+  while (group != NULL) {
+    if ((group->interface == ifp) && (ip_addr_cmp(&(group->group_address), addr))) {
+      return group;
+    }
+    group = group->next;
+  }
+
+  /* to be clearer, we return NULL here instead of
+   * 'group' (which is also NULL at this point).
+   */
+  return NULL;
+}
+
+/**
+ * Search for a specific igmp group and create a new one if not found-
+ *
+ * @param ifp the network interface for which to look
+ * @param addr the group ip address to search
+ * @return a struct igmp_group*,
+ *         NULL on memory error.
+ */
+struct igmp_group *
+igmp_lookup_group(struct netif *ifp, struct ip_addr *addr)
+{
+  struct igmp_group *group = igmp_group_list;
+  
+  /* Search if the group already exists */
+  group = igmp_lookfor_group(ifp, addr);
+  if (group != NULL) {
+    /* Group already exists. */
+    return group;
+  }
+
+  /* Group doesn't exist yet, create a new one */
+  group = memp_malloc(MEMP_IGMP_GROUP);
+  if (group != NULL) {
+    group->interface          = ifp;
+    ip_addr_set(&(group->group_address), addr);
+    group->timer              = 0; /* Not running */
+    group->group_state        = IGMP_GROUP_NON_MEMBER;
+    group->last_reporter_flag = 0;
+    group->use                = 0;
+    group->next               = igmp_group_list;
+    
+    igmp_group_list = group;
+  }
+
+  LWIP_DEBUGF(IGMP_DEBUG, ("igmp_lookup_group: %sallocated a new group with address ", (group?"":"impossible to ")));
+  ip_addr_debug_print(IGMP_DEBUG, addr);
+  LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", ifp));
+
+  return group;
+}
+
+/**
+ * Remove a group in the global igmp_group_list
+ *
+ * @param group the group to remove from the global igmp_group_list
+ * @return ERR_OK if group was removed from the list, an err_t otherwise
+ */
+err_t
+igmp_remove_group(struct igmp_group *group)
+{
+  err_t err = ERR_OK;
+
+  /* Is it the first group? */
+  if (igmp_group_list == group) {
+    igmp_group_list = group->next;
+  } else {
+    /* look for group further down the list */
+    struct igmp_group *tmpGroup;
+    for (tmpGroup = igmp_group_list; tmpGroup != NULL; tmpGroup = tmpGroup->next) {
+      if (tmpGroup->next == group) {
+        tmpGroup->next = group->next;
+        break;
+      }
+    }
+    /* Group not found in the global igmp_group_list */
+    if (tmpGroup == NULL)
+      err = ERR_ARG;
+  }
+  /* free group */
+  memp_free(MEMP_IGMP_GROUP, group);
+
+  return err;
+}
+
+/**
+ * Called from ip_input() if a new IGMP packet is received.
+ *
+ * @param p received igmp packet, p->payload pointing to the ip header
+ * @param inp network interface on which the packet was received
+ * @param dest destination ip address of the igmp packet
+ */
+void
+igmp_input(struct pbuf *p, struct netif *inp, struct ip_addr *dest)
+{
+  struct ip_hdr *    iphdr;
+  struct igmp_msg*   igmp;
+  struct igmp_group* group;
+  struct igmp_group* groupref;
+
+  /* Note that the length CAN be greater than 8 but only 8 are used - All are included in the checksum */    
+  iphdr = p->payload;
+  if (pbuf_header(p, -(s16_t)(IPH_HL(iphdr) * 4)) || (p->len < IGMP_MINLEN)) {
+    pbuf_free(p);
+    IGMP_STATS_INC(igmp.lenerr);
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: length error\n"));
+    return;
+  }
+
+  LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: message from "));
+  ip_addr_debug_print(IGMP_DEBUG, &(iphdr->src));
+  LWIP_DEBUGF(IGMP_DEBUG, (" to address "));
+  ip_addr_debug_print(IGMP_DEBUG, &(iphdr->dest));
+  LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", inp));
+
+  /* Now calculate and check the checksum */
+  igmp = (struct igmp_msg *)p->payload;
+  if (inet_chksum(igmp, p->len)) {
+    pbuf_free(p);
+    IGMP_STATS_INC(igmp.chkerr);
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: checksum error\n"));
+    return;
+  }
+
+  /* Packet is ok so find an existing group */
+  group = igmp_lookfor_group(inp, dest); /* use the incoming IP address! */
+  
+  /* If group can be found or create... */
+  if (!group) {
+    pbuf_free(p);
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP frame not for us\n"));
+    return;
+  }
+
+  /* NOW ACT ON THE INCOMING MESSAGE TYPE... */
+  switch (igmp->igmp_msgtype) {
+   case IGMP_MEMB_QUERY: {
+     /* IGMP_MEMB_QUERY to the "all systems" address ? */
+     if ((ip_addr_cmp(dest, &allsystems)) && (igmp->igmp_group_address.addr == 0)) {
+       /* THIS IS THE GENERAL QUERY */
+       LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: General IGMP_MEMB_QUERY on \"ALL SYSTEMS\" address (224.0.0.1) [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp)));
+
+       if (igmp->igmp_maxresp == 0) {
+         IGMP_STATS_INC(igmp.v1_rxed);
+         LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: got an all hosts query with time== 0 - this is V1 and not implemented - treat as v2\n"));
+         igmp->igmp_maxresp = IGMP_V1_DELAYING_MEMBER_TMR;
+       }
+
+       IGMP_STATS_INC(igmp.group_query_rxed);
+       groupref = igmp_group_list;
+       while (groupref) {
+         /* Do not send messages on the all systems group address! */
+         if ((groupref->interface == inp) && (!(ip_addr_cmp(&(groupref->group_address), &allsystems)))) {
+           igmp_delaying_member( groupref, igmp->igmp_maxresp);
+         }
+         groupref = groupref->next;
+       }
+     } else {
+       /* IGMP_MEMB_QUERY to a specific group ? */
+       if (group->group_address.addr != 0) {
+         LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP_MEMB_QUERY to a specific group "));
+         ip_addr_debug_print(IGMP_DEBUG, &group->group_address);
+         if (ip_addr_cmp (dest, &allsystems)) {
+           LWIP_DEBUGF(IGMP_DEBUG, (" using \"ALL SYSTEMS\" address (224.0.0.1) [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp)));
+           /* we first need to re-lookfor the group since we used dest last time */
+           group = igmp_lookfor_group(inp, &igmp->igmp_group_address);
+         } else {
+           LWIP_DEBUGF(IGMP_DEBUG, (" with the group address as destination [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp)));
+         }
+
+         if (group != NULL) {
+           IGMP_STATS_INC(igmp.unicast_query);
+           igmp_delaying_member( group, igmp->igmp_maxresp);
+         }
+       }
+     }
+     break;
+   }
+   case IGMP_V2_MEMB_REPORT: {
+     LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP_V2_MEMB_REPORT\n"));
+
+     IGMP_STATS_INC(igmp.report_rxed);
+     if (group->group_state == IGMP_GROUP_DELAYING_MEMBER) {
+       /* This is on a specific group we have already looked up */
+       group->timer = 0; /* stopped */
+       group->group_state = IGMP_GROUP_IDLE_MEMBER;
+       group->last_reporter_flag = 0;
+     }
+     break;
+   }
+   default: {
+     LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: unexpected msg %d in state %d on group %p on if %p\n",
+       igmp->igmp_msgtype, group->group_state, &group, group->interface));
+     break;
+   }
+  }
+
+  pbuf_free(p);
+  return;
+}
+
+/**
+ * Join a group on one network interface.
+ *
+ * @param ifaddr ip address of the network interface which should join a new group
+ * @param groupaddr the ip address of the group which to join
+ * @return ERR_OK if group was joined on the netif(s), an err_t otherwise
+ */
+err_t
+igmp_joingroup(struct ip_addr *ifaddr, struct ip_addr *groupaddr)
+{
+  err_t              err = ERR_VAL; /* no matching interface */
+  struct igmp_group *group;
+  struct netif      *netif;
+
+  /* make sure it is multicast address */
+  LWIP_ERROR("igmp_joingroup: attempt to join non-multicast address", ip_addr_ismulticast(groupaddr), return ERR_VAL;);
+  LWIP_ERROR("igmp_joingroup: attempt to join allsystems address", (!ip_addr_cmp(groupaddr, &allsystems)), return ERR_VAL;);
+
+  /* loop through netif's */
+  netif = netif_list;
+  while (netif != NULL) {
+    /* Should we join this interface ? */
+    if ((netif->flags & NETIF_FLAG_IGMP) && ((ip_addr_isany(ifaddr) || ip_addr_cmp(&(netif->ip_addr), ifaddr)))) {
+      /* find group or create a new one if not found */
+      group = igmp_lookup_group(netif, groupaddr);
+
+      if (group != NULL) {
+        /* This should create a new group, check the state to make sure */
+        if (group->group_state != IGMP_GROUP_NON_MEMBER) {
+          LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup: join to group not in state IGMP_GROUP_NON_MEMBER\n"));
+        } else {
+          /* OK - it was new group */
+          LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup: join to new group: "));
+          ip_addr_debug_print(IGMP_DEBUG, groupaddr);
+          LWIP_DEBUGF(IGMP_DEBUG, ("\n"));
+
+          /* If first use of the group, allow the group at the MAC level */
+          if ((group->use==0) && (netif->igmp_mac_filter != NULL)) {
+            LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup: igmp_mac_filter(ADD "));
+            ip_addr_debug_print(IGMP_DEBUG, groupaddr);
+            LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", netif));
+            netif->igmp_mac_filter(netif, groupaddr, IGMP_ADD_MAC_FILTER);
+          }
+
+          IGMP_STATS_INC(igmp.join_sent);
+          igmp_send(group, IGMP_V2_MEMB_REPORT);
+
+          igmp_start_timer(group, IGMP_JOIN_DELAYING_MEMBER_TMR);
+
+          /* Need to work out where this timer comes from */
+          group->group_state = IGMP_GROUP_DELAYING_MEMBER;
+        }
+        /* Increment group use */
+        group->use++;
+        /* Join on this interface */
+        err = ERR_OK;
+      } else {
+        /* Return an error even if some network interfaces are joined */
+        /** @todo undo any other netif already joined */
+        LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup: Not enought memory to join to group\n"));
+        return ERR_MEM;
+      }
+    }
+    /* proceed to next network interface */
+    netif = netif->next;
+  }
+
+  return err;
+}
+
+/**
+ * Leave a group on one network interface.
+ *
+ * @param ifaddr ip address of the network interface which should leave a group
+ * @param groupaddr the ip address of the group which to leave
+ * @return ERR_OK if group was left on the netif(s), an err_t otherwise
+ */
+err_t
+igmp_leavegroup(struct ip_addr *ifaddr, struct ip_addr *groupaddr)
+{
+  err_t              err = ERR_VAL; /* no matching interface */
+  struct igmp_group *group;
+  struct netif      *netif;
+
+  /* make sure it is multicast address */
+  LWIP_ERROR("igmp_leavegroup: attempt to leave non-multicast address", ip_addr_ismulticast(groupaddr), return ERR_VAL;);
+  LWIP_ERROR("igmp_leavegroup: attempt to leave allsystems address", (!ip_addr_cmp(groupaddr, &allsystems)), return ERR_VAL;);
+
+  /* loop through netif's */
+  netif = netif_list;
+  while (netif != NULL) {
+    /* Should we leave this interface ? */
+    if ((netif->flags & NETIF_FLAG_IGMP) && ((ip_addr_isany(ifaddr) || ip_addr_cmp(&(netif->ip_addr), ifaddr)))) {
+      /* find group */
+      group = igmp_lookfor_group(netif, groupaddr);
+
+      if (group != NULL) {
+        /* Only send a leave if the flag is set according to the state diagram */
+        LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: Leaving group: "));
+        ip_addr_debug_print(IGMP_DEBUG, groupaddr);
+        LWIP_DEBUGF(IGMP_DEBUG, ("\n"));
+
+        /* If there is no other use of the group */
+        if (group->use <= 1) {
+          /* If we are the last reporter for this group */
+          if (group->last_reporter_flag) {
+            LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: sending leaving group\n"));
+            IGMP_STATS_INC(igmp.leave_sent);
+            igmp_send(group, IGMP_LEAVE_GROUP);
+          }
+          
+          /* Disable the group at the MAC level */
+          if (netif->igmp_mac_filter != NULL) {
+            LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: igmp_mac_filter(DEL "));
+            ip_addr_debug_print(IGMP_DEBUG, groupaddr);
+            LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", netif));
+            netif->igmp_mac_filter(netif, groupaddr, IGMP_DEL_MAC_FILTER);
+          }
+          
+          LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: remove group: "));
+          ip_addr_debug_print(IGMP_DEBUG, groupaddr);
+          LWIP_DEBUGF(IGMP_DEBUG, ("\n"));          
+          
+          /* Free the group */
+          igmp_remove_group(group);
+        } else {
+          /* Decrement group use */
+          group->use--;
+        }
+        /* Leave on this interface */
+        err = ERR_OK;
+      } else {
+        /* It's not a fatal error on "leavegroup" */
+        LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: not member of group\n"));
+      }
+    }
+    /* proceed to next network interface */
+    netif = netif->next;
+  }
+
+  return err;
+}
+
+/**
+ * The igmp timer function (both for NO_SYS=1 and =0)
+ * Should be called every IGMP_TMR_INTERVAL milliseconds (100 ms is default).
+ */
+void
+igmp_tmr(void)
+{
+  struct igmp_group *group = igmp_group_list;
+
+  while (group != NULL) {
+    if (group->timer != 0) {
+      group->timer -= 1;
+      if (group->timer == 0) {
+        igmp_timeout(group);
+      }
+    }
+    group = group->next;
+  }
+}
+
+/**
+ * Called if a timeout for one group is reached.
+ * Sends a report for this group.
+ *
+ * @param group an igmp_group for which a timeout is reached
+ */
+void
+igmp_timeout(struct igmp_group *group)
+{
+  /* If the state is IGMP_GROUP_DELAYING_MEMBER then we send a report for this group */
+  if (group->group_state == IGMP_GROUP_DELAYING_MEMBER) {
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_timeout: report membership for group with address "));
+    ip_addr_debug_print(IGMP_DEBUG, &(group->group_address));
+    LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", group->interface));
+
+    igmp_send(group, IGMP_V2_MEMB_REPORT);
+  }
+}
+
+/**
+ * Start a timer for an igmp group
+ *
+ * @param group the igmp_group for which to start a timer
+ * @param max_time the time in multiples of IGMP_TMR_INTERVAL (decrease with
+ *        every call to igmp_tmr())
+ */
+void
+igmp_start_timer(struct igmp_group *group, u8_t max_time)
+{
+  /**
+   * @todo Important !! this should be random 0 -> max_time. Find out how to do this
+   */
+  group->timer = max_time;
+}
+
+/**
+ * Stop a timer for an igmp_group
+ *
+ * @param group the igmp_group for which to stop the timer
+ */
+void
+igmp_stop_timer(struct igmp_group *group)
+{
+  group->timer = 0;
+}
+
+/**
+ * Delaying membership report for a group if necessary
+ *
+ * @param group the igmp_group for which "delaying" membership report
+ * @param maxresp query delay
+ */
+void
+igmp_delaying_member( struct igmp_group *group, u8_t maxresp)
+{
+  if ((group->group_state == IGMP_GROUP_IDLE_MEMBER) ||
+     ((group->group_state == IGMP_GROUP_DELAYING_MEMBER) && (maxresp > group->timer))) {
+    igmp_start_timer(group, (maxresp)/2);
+    group->group_state = IGMP_GROUP_DELAYING_MEMBER;
+  }
+}
+
+
+/**
+ * Sends an IP packet on a network interface. This function constructs the IP header
+ * and calculates the IP header checksum. If the source IP address is NULL,
+ * the IP address of the outgoing network interface is filled in as source address.
+ *
+ * @param p the packet to send (p->payload points to the data, e.g. next
+            protocol header; if dest == IP_HDRINCL, p already includes an IP
+            header and p->payload points to that IP header)
+ * @param src the source IP address to send from (if src == IP_ADDR_ANY, the
+ *         IP  address of the netif used to send is used as source address)
+ * @param dest the destination IP address to send the packet to
+ * @param ttl the TTL value to be set in the IP header
+ * @param proto the PROTOCOL to be set in the IP header
+ * @param netif the netif on which to send this packet
+ * @return ERR_OK if the packet was sent OK
+ *         ERR_BUF if p doesn't have enough space for IP/LINK headers
+ *         returns errors returned by netif->output
+ */
+err_t
+igmp_ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+                  u8_t ttl, u8_t proto, struct netif *netif)
+{
+  /* This is the "router alert" option */
+  u16_t ra[2];
+  ra[0] = htons (ROUTER_ALERT);
+  ra[1] = 0x0000; /* Router shall examine packet */
+  return ip_output_if_opt(p, src, dest, ttl, 0, proto, netif, ra, ROUTER_ALERTLEN);
+}
+
+/**
+ * Send an igmp packet to a specific group.
+ *
+ * @param group the group to which to send the packet
+ * @param type the type of igmp packet to send
+ */
+void
+igmp_send(struct igmp_group *group, u8_t type)
+{
+  struct pbuf*     p    = NULL;
+  struct igmp_msg* igmp = NULL;
+  struct ip_addr   src  = {0};
+  struct ip_addr*  dest = NULL;
+
+  /* IP header + "router alert" option + IGMP header */
+  p = pbuf_alloc(PBUF_TRANSPORT, IGMP_MINLEN, PBUF_RAM);
+  
+  if (p) {
+    igmp = p->payload;
+    LWIP_ASSERT("igmp_send: check that first pbuf can hold struct igmp_msg",
+               (p->len >= sizeof(struct igmp_msg)));
+    ip_addr_set(&src, &((group->interface)->ip_addr));
+     
+    if (type == IGMP_V2_MEMB_REPORT) {
+      dest = &(group->group_address);
+      IGMP_STATS_INC(igmp.report_sent);
+      ip_addr_set(&(igmp->igmp_group_address), &(group->group_address));
+      group->last_reporter_flag = 1; /* Remember we were the last to report */
+    } else {
+      if (type == IGMP_LEAVE_GROUP) {
+        dest = &allrouters;
+        ip_addr_set(&(igmp->igmp_group_address), &(group->group_address));
+      }
+    }
+
+    if ((type == IGMP_V2_MEMB_REPORT) || (type == IGMP_LEAVE_GROUP)) {
+      igmp->igmp_msgtype  = type;
+      igmp->igmp_maxresp  = 0;
+      igmp->igmp_checksum = 0;
+      igmp->igmp_checksum = inet_chksum( igmp, IGMP_MINLEN);
+
+      igmp_ip_output_if(p, &src, dest, IGMP_TTL, IP_PROTO_IGMP, group->interface);
+    }
+
+    pbuf_free(p);
+  } else {
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_send: not enough memory for igmp_send\n"));
+  }
+}
+
+#endif /* LWIP_IGMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/inet.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/inet.c
new file mode 100644
index 0000000..69baf1d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/inet.c
@@ -0,0 +1,278 @@
+/**
+ * @file
+ * Functions common to all TCP/IPv4 modules, such as the byte order functions.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/inet.h"
+
+/* Here for now until needed in other places in lwIP */
+#ifndef isprint
+#define in_range(c, lo, up)  ((u8_t)c >= lo && (u8_t)c <= up)
+#define isprint(c)           in_range(c, 0x20, 0x7f)
+#define isdigit(c)           in_range(c, '0', '9')
+#define isxdigit(c)          (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F'))
+#define islower(c)           in_range(c, 'a', 'z')
+#define isspace(c)           (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v')
+#endif    
+    
+/**
+ * Ascii internet address interpretation routine.
+ * The value returned is in network order.
+ *
+ * @param cp IP address in ascii represenation (e.g. "127.0.0.1")
+ * @return ip address in network order
+ */
+u32_t
+inet_addr(const char *cp)
+{
+  struct in_addr val;
+
+  if (inet_aton(cp, &val)) {
+    return (val.s_addr);
+  }
+  return (INADDR_NONE);
+}
+
+/**
+ * Check whether "cp" is a valid ascii representation
+ * of an Internet address and convert to a binary address.
+ * Returns 1 if the address is valid, 0 if not.
+ * This replaces inet_addr, the return value from which
+ * cannot distinguish between failure and a local broadcast address.
+ *
+ * @param cp IP address in ascii represenation (e.g. "127.0.0.1")
+ * @param addr pointer to which to save the ip address in network order
+ * @return 1 if cp could be converted to addr, 0 on failure
+ */
+int
+inet_aton(const char *cp, struct in_addr *addr)
+{
+  u32_t val;
+  u8_t base;
+  char c;
+  u32_t parts[4];
+  u32_t *pp = parts;
+
+  c = *cp;
+  for (;;) {
+    /*
+     * Collect number up to ``.''.
+     * Values are specified as for C:
+     * 0x=hex, 0=octal, 1-9=decimal.
+     */
+    if (!isdigit(c))
+      return (0);
+    val = 0;
+    base = 10;
+    if (c == '0') {
+      c = *++cp;
+      if (c == 'x' || c == 'X') {
+        base = 16;
+        c = *++cp;
+      } else
+        base = 8;
+    }
+    for (;;) {
+      if (isdigit(c)) {
+        val = (val * base) + (int)(c - '0');
+        c = *++cp;
+      } else if (base == 16 && isxdigit(c)) {
+        val = (val << 4) | (int)(c + 10 - (islower(c) ? 'a' : 'A'));
+        c = *++cp;
+      } else
+        break;
+    }
+    if (c == '.') {
+      /*
+       * Internet format:
+       *  a.b.c.d
+       *  a.b.c   (with c treated as 16 bits)
+       *  a.b (with b treated as 24 bits)
+       */
+      if (pp >= parts + 3)
+        return (0);
+      *pp++ = val;
+      c = *++cp;
+    } else
+      break;
+  }
+  /*
+   * Check for trailing characters.
+   */
+  if (c != '\0' && !isspace(c))
+    return (0);
+  /*
+   * Concoct the address according to
+   * the number of parts specified.
+   */
+  switch (pp - parts + 1) {
+
+  case 0:
+    return (0);       /* initial nondigit */
+
+  case 1:             /* a -- 32 bits */
+    break;
+
+  case 2:             /* a.b -- 8.24 bits */
+    if (val > 0xffffffUL)
+      return (0);
+    val |= parts[0] << 24;
+    break;
+
+  case 3:             /* a.b.c -- 8.8.16 bits */
+    if (val > 0xffff)
+      return (0);
+    val |= (parts[0] << 24) | (parts[1] << 16);
+    break;
+
+  case 4:             /* a.b.c.d -- 8.8.8.8 bits */
+    if (val > 0xff)
+      return (0);
+    val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8);
+    break;
+  }
+  if (addr)
+    addr->s_addr = htonl(val);
+  return (1);
+}
+
+/**
+ * Convert numeric IP address into decimal dotted ASCII representation.
+ * returns ptr to static buffer; not reentrant!
+ *
+ * @param addr ip address in network order to convert
+ * @return pointer to a global static (!) buffer that holds the ASCII
+ *         represenation of addr
+ */
+char *
+inet_ntoa(struct in_addr addr)
+{
+  static char str[16];
+  u32_t s_addr = addr.s_addr;
+  char inv[3];
+  char *rp;
+  u8_t *ap;
+  u8_t rem;
+  u8_t n;
+  u8_t i;
+
+  rp = str;
+  ap = (u8_t *)&s_addr;
+  for(n = 0; n < 4; n++) {
+    i = 0;
+    do {
+      rem = *ap % (u8_t)10;
+      *ap /= (u8_t)10;
+      inv[i++] = '0' + rem;
+    } while(*ap);
+    while(i--)
+      *rp++ = inv[i];
+    *rp++ = '.';
+    ap++;
+  }
+  *--rp = 0;
+  return str;
+}
+
+/**
+ * These are reference implementations of the byte swapping functions.
+ * Again with the aim of being simple, correct and fully portable.
+ * Byte swapping is the second thing you would want to optimize. You will
+ * need to port it to your architecture and in your cc.h:
+ * 
+ * #define LWIP_PLATFORM_BYTESWAP 1
+ * #define LWIP_PLATFORM_HTONS(x) 
+ * #define LWIP_PLATFORM_HTONL(x) 
+ *
+ * Note ntohs() and ntohl() are merely references to the htonx counterparts.
+ */
+
+#if (LWIP_PLATFORM_BYTESWAP == 0) && (BYTE_ORDER == LITTLE_ENDIAN)
+
+/**
+ * Convert an u16_t from host- to network byte order.
+ *
+ * @param n u16_t in host byte order
+ * @return n in network byte order
+ */
+u16_t
+htons(u16_t n)
+{
+  return ((n & 0xff) << 8) | ((n & 0xff00) >> 8);
+}
+
+/**
+ * Convert an u16_t from network- to host byte order.
+ *
+ * @param n u16_t in network byte order
+ * @return n in host byte order
+ */
+u16_t
+ntohs(u16_t n)
+{
+  return htons(n);
+}
+
+/**
+ * Convert an u32_t from host- to network byte order.
+ *
+ * @param n u32_t in host byte order
+ * @return n in network byte order
+ */
+u32_t
+htonl(u32_t n)
+{
+  return ((n & 0xff) << 24) |
+    ((n & 0xff00) << 8) |
+    ((n & 0xff0000UL) >> 8) |
+    ((n & 0xff000000UL) >> 24);
+}
+
+/**
+ * Convert an u32_t from network- to host byte order.
+ *
+ * @param n u32_t in network byte order
+ * @return n in host byte order
+ */
+u32_t
+ntohl(u32_t n)
+{
+  return htonl(n);
+}
+
+#endif /* (LWIP_PLATFORM_BYTESWAP == 0) && (BYTE_ORDER == LITTLE_ENDIAN) */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/inet_chksum.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/inet_chksum.c
new file mode 100644
index 0000000..185881e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/inet_chksum.c
@@ -0,0 +1,438 @@
+/**
+ * @file
+ * Incluse internet checksum functions.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/inet_chksum.h"
+#include "lwip/inet.h"
+
+#include 
+
+/* These are some reference implementations of the checksum algorithm, with the
+ * aim of being simple, correct and fully portable. Checksumming is the
+ * first thing you would want to optimize for your platform. If you create
+ * your own version, link it in and in your cc.h put:
+ * 
+ * #define LWIP_CHKSUM  
+ *
+ * Or you can select from the implementations below by defining
+ * LWIP_CHKSUM_ALGORITHM to 1, 2 or 3.
+ */
+
+#ifndef LWIP_CHKSUM
+# define LWIP_CHKSUM lwip_standard_chksum
+# ifndef LWIP_CHKSUM_ALGORITHM
+#  define LWIP_CHKSUM_ALGORITHM 1
+# endif
+#endif
+/* If none set: */
+#ifndef LWIP_CHKSUM_ALGORITHM
+# define LWIP_CHKSUM_ALGORITHM 0
+#endif
+
+/** Like the name says... */
+#if LWIP_PLATFORM_BYTESWAP && (BYTE_ORDER == LITTLE_ENDIAN)
+/* little endian and PLATFORM_BYTESWAP defined */
+#define SWAP_BYTES_IN_WORD(w) LWIP_PLATFORM_HTONS(w)
+#else
+/* can't use htons on big endian (or PLATFORM_BYTESWAP not defined)... */
+#define SWAP_BYTES_IN_WORD(w) ((w & 0xff) << 8) | ((w & 0xff00) >> 8)
+#endif
+
+/** Split an u32_t in two u16_ts and add them up */
+#define FOLD_U32T(u)          ((u >> 16) + (u & 0x0000ffffUL))
+
+#if (LWIP_CHKSUM_ALGORITHM == 1) /* Version #1 */
+/**
+ * lwip checksum
+ *
+ * @param dataptr points to start of data to be summed at any boundary
+ * @param len length of data to be summed
+ * @return host order (!) lwip checksum (non-inverted Internet sum) 
+ *
+ * @note accumulator size limits summable length to 64k
+ * @note host endianess is irrelevant (p3 RFC1071)
+ */
+static u16_t
+lwip_standard_chksum(void *dataptr, u16_t len)
+{
+  u32_t acc;
+  u16_t src;
+  u8_t *octetptr;
+
+  acc = 0;
+  /* dataptr may be at odd or even addresses */
+  octetptr = (u8_t*)dataptr;
+  while (len > 1) {
+    /* declare first octet as most significant
+       thus assume network order, ignoring host order */
+    src = (*octetptr) << 8;
+    octetptr++;
+    /* declare second octet as least significant */
+    src |= (*octetptr);
+    octetptr++;
+    acc += src;
+    len -= 2;
+  }
+  if (len > 0) {
+    /* accumulate remaining octet */
+    src = (*octetptr) << 8;
+    acc += src;
+  }
+  /* add deferred carry bits */
+  acc = (acc >> 16) + (acc & 0x0000ffffUL);
+  if ((acc & 0xffff0000UL) != 0) {
+    acc = (acc >> 16) + (acc & 0x0000ffffUL);
+  }
+  /* This maybe a little confusing: reorder sum using htons()
+     instead of ntohs() since it has a little less call overhead.
+     The caller must invert bits for Internet sum ! */
+  return htons((u16_t)acc);
+}
+#endif
+
+#if (LWIP_CHKSUM_ALGORITHM == 2) /* Alternative version #2 */
+/*
+ * Curt McDowell
+ * Broadcom Corp.
+ * csm@broadcom.com
+ *
+ * IP checksum two bytes at a time with support for
+ * unaligned buffer.
+ * Works for len up to and including 0x20000.
+ * by Curt McDowell, Broadcom Corp. 12/08/2005
+ *
+ * @param dataptr points to start of data to be summed at any boundary
+ * @param len length of data to be summed
+ * @return host order (!) lwip checksum (non-inverted Internet sum) 
+ */
+
+static u16_t
+lwip_standard_chksum(void *dataptr, int len)
+{
+  u8_t *pb = dataptr;
+  u16_t *ps, t = 0;
+  u32_t sum = 0;
+  int odd = ((u32_t)pb & 1);
+
+  /* Get aligned to u16_t */
+  if (odd && len > 0) {
+    ((u8_t *)&t)[1] = *pb++;
+    len--;
+  }
+
+  /* Add the bulk of the data */
+  ps = (u16_t *)pb;
+  while (len > 1) {
+    sum += *ps++;
+    len -= 2;
+  }
+
+  /* Consume left-over byte, if any */
+  if (len > 0) {
+    ((u8_t *)&t)[0] = *(u8_t *)ps;;
+  }
+
+  /* Add end bytes */
+  sum += t;
+
+  /* Fold 32-bit sum to 16 bits
+     calling this twice is propably faster than if statements... */
+  sum = FOLD_U32T(sum);
+  sum = FOLD_U32T(sum);
+
+  /* Swap if alignment was odd */
+  if (odd) {
+    sum = SWAP_BYTES_IN_WORD(sum);
+  }
+
+  return sum;
+}
+#endif
+
+#if (LWIP_CHKSUM_ALGORITHM == 3) /* Alternative version #3 */
+/**
+ * An optimized checksum routine. Basically, it uses loop-unrolling on
+ * the checksum loop, treating the head and tail bytes specially, whereas
+ * the inner loop acts on 8 bytes at a time. 
+ *
+ * @arg start of buffer to be checksummed. May be an odd byte address.
+ * @len number of bytes in the buffer to be checksummed.
+ * @return host order (!) lwip checksum (non-inverted Internet sum) 
+ * 
+ * by Curt McDowell, Broadcom Corp. December 8th, 2005
+ */
+
+static u16_t
+lwip_standard_chksum(void *dataptr, int len)
+{
+  u8_t *pb = dataptr;
+  u16_t *ps, t = 0;
+  u32_t *pl;
+  u32_t sum = 0, tmp;
+  /* starts at odd byte address? */
+  int odd = ((u32_t)pb & 1);
+
+  if (odd && len > 0) {
+    ((u8_t *)&t)[1] = *pb++;
+    len--;
+  }
+
+  ps = (u16_t *)pb;
+
+  if (((u32_t)ps & 3) && len > 1) {
+    sum += *ps++;
+    len -= 2;
+  }
+
+  pl = (u32_t *)ps;
+
+  while (len > 7)  {
+    tmp = sum + *pl++;          /* ping */
+    if (tmp < sum) {
+      tmp++;                    /* add back carry */
+    }
+
+    sum = tmp + *pl++;          /* pong */
+    if (sum < tmp) {
+      sum++;                    /* add back carry */
+    }
+
+    len -= 8;
+  }
+
+  /* make room in upper bits */
+  sum = FOLD_U32T(sum);
+
+  ps = (u16_t *)pl;
+
+  /* 16-bit aligned word remaining? */
+  while (len > 1) {
+    sum += *ps++;
+    len -= 2;
+  }
+
+  /* dangling tail byte remaining? */
+  if (len > 0) {                /* include odd byte */
+    ((u8_t *)&t)[0] = *(u8_t *)ps;
+  }
+
+  sum += t;                     /* add end bytes */
+
+  /* Fold 32-bit sum to 16 bits
+     calling this twice is propably faster than if statements... */
+  sum = FOLD_U32T(sum);
+  sum = FOLD_U32T(sum);
+
+  if (odd) {
+    sum = SWAP_BYTES_IN_WORD(sum);
+  }
+
+  return sum;
+}
+#endif
+
+/* inet_chksum_pseudo:
+ *
+ * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
+ * IP addresses are expected to be in network byte order.
+ *
+ * @param p chain of pbufs over that a checksum should be calculated (ip data part)
+ * @param src source ip address (used for checksum of pseudo header)
+ * @param dst destination ip address (used for checksum of pseudo header)
+ * @param proto ip protocol (used for checksum of pseudo header)
+ * @param proto_len length of the ip data part (used for checksum of pseudo header)
+ * @return checksum (as u16_t) to be saved directly in the protocol header
+ */
+u16_t
+inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u16_t proto_len)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped;
+
+  acc = 0;
+  swapped = 0;
+  /* iterate through all pbuf in chain */
+  for(q = p; q != NULL; q = q->next) {
+    LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n",
+      (void *)q, (void *)q->next));
+    acc += LWIP_CHKSUM(q->payload, q->len);
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/
+    /* just executing this next line is probably faster that the if statement needed
+       to check whether we really need to execute it, and does no harm */
+    acc = FOLD_U32T(acc);
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = SWAP_BYTES_IN_WORD(acc);
+    }
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/
+  }
+
+  if (swapped) {
+    acc = SWAP_BYTES_IN_WORD(acc);
+  }
+  acc += (src->addr & 0xffffUL);
+  acc += ((src->addr >> 16) & 0xffffUL);
+  acc += (dest->addr & 0xffffUL);
+  acc += ((dest->addr >> 16) & 0xffffUL);
+  acc += (u32_t)htons((u16_t)proto);
+  acc += (u32_t)htons(proto_len);
+
+  /* Fold 32-bit sum to 16 bits
+     calling this twice is propably faster than if statements... */
+  acc = FOLD_U32T(acc);
+  acc = FOLD_U32T(acc);
+  LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc));
+  return (u16_t)~(acc & 0xffffUL);
+}
+
+/* inet_chksum_pseudo:
+ *
+ * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
+ * IP addresses are expected to be in network byte order.
+ *
+ * @param p chain of pbufs over that a checksum should be calculated (ip data part)
+ * @param src source ip address (used for checksum of pseudo header)
+ * @param dst destination ip address (used for checksum of pseudo header)
+ * @param proto ip protocol (used for checksum of pseudo header)
+ * @param proto_len length of the ip data part (used for checksum of pseudo header)
+ * @return checksum (as u16_t) to be saved directly in the protocol header
+ */
+/* Currently only used by UDPLITE, although this could change in the future. */
+#if LWIP_UDPLITE
+u16_t
+inet_chksum_pseudo_partial(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u16_t proto_len, u16_t chksum_len)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped;
+  u16_t chklen;
+
+  acc = 0;
+  swapped = 0;
+  /* iterate through all pbuf in chain */
+  for(q = p; (q != NULL) && (chksum_len > 0); q = q->next) {
+    LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n",
+      (void *)q, (void *)q->next));
+    chklen = q->len;
+    if (chklen > chksum_len) {
+      chklen = chksum_len;
+    }
+    acc += LWIP_CHKSUM(q->payload, chklen);
+    chksum_len -= chklen;
+    LWIP_ASSERT("delete me", chksum_len < 0x7fff);
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/
+    /* fold the upper bit down */
+    acc = FOLD_U32T(acc);
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = SWAP_BYTES_IN_WORD(acc);
+    }
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/
+  }
+
+  if (swapped) {
+    acc = SWAP_BYTES_IN_WORD(acc);
+  }
+  acc += (src->addr & 0xffffUL);
+  acc += ((src->addr >> 16) & 0xffffUL);
+  acc += (dest->addr & 0xffffUL);
+  acc += ((dest->addr >> 16) & 0xffffUL);
+  acc += (u32_t)htons((u16_t)proto);
+  acc += (u32_t)htons(proto_len);
+
+  /* Fold 32-bit sum to 16 bits
+     calling this twice is propably faster than if statements... */
+  acc = FOLD_U32T(acc);
+  acc = FOLD_U32T(acc);
+  LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc));
+  return (u16_t)~(acc & 0xffffUL);
+}
+#endif /* LWIP_UDPLITE */
+
+/* inet_chksum:
+ *
+ * Calculates the Internet checksum over a portion of memory. Used primarily for IP
+ * and ICMP.
+ *
+ * @param dataptr start of the buffer to calculate the checksum (no alignment needed)
+ * @param len length of the buffer to calculate the checksum
+ * @return checksum (as u16_t) to be saved directly in the protocol header
+ */
+
+u16_t
+inet_chksum(void *dataptr, u16_t len)
+{
+  return ~LWIP_CHKSUM(dataptr, len);
+}
+
+/**
+ * Calculate a checksum over a chain of pbufs (without pseudo-header, much like
+ * inet_chksum only pbufs are used).
+ *
+ * @param p pbuf chain over that the checksum should be calculated
+ * @return checksum (as u16_t) to be saved directly in the protocol header
+ */
+u16_t
+inet_chksum_pbuf(struct pbuf *p)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped;
+
+  acc = 0;
+  swapped = 0;
+  for(q = p; q != NULL; q = q->next) {
+    acc += LWIP_CHKSUM(q->payload, q->len);
+    acc = FOLD_U32T(acc);
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = SWAP_BYTES_IN_WORD(acc);
+    }
+  }
+
+  if (swapped) {
+    acc = SWAP_BYTES_IN_WORD(acc);
+  }
+  return (u16_t)~(acc & 0xffffUL);
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/ip.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/ip.c
new file mode 100644
index 0000000..b1e98f3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/ip.c
@@ -0,0 +1,723 @@
+/**
+ * @file
+ * This is the IPv4 layer implementation for incoming and outgoing IP traffic.
+ * 
+ * @see ip_frag.c
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+#include "lwip/ip.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/ip_frag.h"
+#include "lwip/inet.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/netif.h"
+#include "lwip/icmp.h"
+#include "lwip/igmp.h"
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+#include "lwip/snmp.h"
+#include "lwip/dhcp.h"
+#include "lwip/stats.h"
+#include "arch/perf.h"
+
+#include 
+
+/**
+ * The interface that provided the packet for the current callback
+ * invocation.
+ */
+struct netif *current_netif;
+
+/**
+ * Header of the input packet currently being processed.
+ */
+const struct ip_hdr *current_header;
+
+/**
+ * Finds the appropriate network interface for a given IP address. It
+ * searches the list of network interfaces linearly. A match is found
+ * if the masked IP address of the network interface equals the masked
+ * IP address given to the function.
+ *
+ * @param dest the destination IP address for which to find the route
+ * @return the netif on which to send to reach dest
+ */
+struct netif *
+ip_route(struct ip_addr *dest)
+{
+  struct netif *netif;
+
+  /* iterate through netifs */
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+    /* network mask matches? */
+    if (netif_is_up(netif)) {
+      if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) {
+        /* return netif on which to forward IP packet */
+        return netif;
+      }
+    }
+  }
+  if ((netif_default == NULL) || (!netif_is_up(netif_default))) {
+    LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip_route: No route to 0x%"X32_F"\n", dest->addr));
+    IP_STATS_INC(ip.rterr);
+    snmp_inc_ipoutnoroutes();
+    return NULL;
+  }
+  /* no matching netif found, use default netif */
+  return netif_default;
+}
+
+#if IP_FORWARD
+/**
+ * Forwards an IP packet. It finds an appropriate route for the
+ * packet, decrements the TTL value of the packet, adjusts the
+ * checksum and outputs the packet on the appropriate interface.
+ *
+ * @param p the packet to forward (p->payload points to IP header)
+ * @param iphdr the IP header of the input packet
+ * @param inp the netif on which this packet was received
+ * @return the netif on which the packet was sent (NULL if it wasn't sent)
+ */
+static struct netif *
+ip_forward(struct pbuf *p, struct ip_hdr *iphdr, struct netif *inp)
+{
+  struct netif *netif;
+
+  PERF_START;
+  /* Find network interface where to forward this IP packet to. */
+  netif = ip_route((struct ip_addr *)&(iphdr->dest));
+  if (netif == NULL) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_forward: no forwarding route for 0x%"X32_F" found\n",
+                      iphdr->dest.addr));
+    snmp_inc_ipoutnoroutes();
+    return (struct netif *)NULL;
+  }
+  /* Do not forward packets onto the same network interface on which
+   * they arrived. */
+  if (netif == inp) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_forward: not bouncing packets back on incoming interface.\n"));
+    snmp_inc_ipoutnoroutes();
+    return (struct netif *)NULL;
+  }
+
+  /* decrement TTL */
+  IPH_TTL_SET(iphdr, IPH_TTL(iphdr) - 1);
+  /* send ICMP if TTL == 0 */
+  if (IPH_TTL(iphdr) == 0) {
+    snmp_inc_ipinhdrerrors();
+#if LWIP_ICMP
+    /* Don't send ICMP messages in response to ICMP messages */
+    if (IPH_PROTO(iphdr) != IP_PROTO_ICMP) {
+      icmp_time_exceeded(p, ICMP_TE_TTL);
+    }
+#endif /* LWIP_ICMP */
+    return (struct netif *)NULL;
+  }
+
+  /* Incrementally update the IP checksum. */
+  if (IPH_CHKSUM(iphdr) >= htons(0xffff - 0x100)) {
+    IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100) + 1);
+  } else {
+    IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100));
+  }
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to 0x%"X32_F"\n",
+                    iphdr->dest.addr));
+
+  IP_STATS_INC(ip.fw);
+  IP_STATS_INC(ip.xmit);
+  snmp_inc_ipforwdatagrams();
+
+  PERF_STOP("ip_forward");
+  /* transmit pbuf on chosen interface */
+  netif->output(netif, p, (struct ip_addr *)&(iphdr->dest));
+  return netif;
+}
+#endif /* IP_FORWARD */
+
+/**
+ * This function is called by the network interface device driver when
+ * an IP packet is received. The function does the basic checks of the
+ * IP header such as packet size being at least larger than the header
+ * size etc. If the packet was not destined for us, the packet is
+ * forwarded (using ip_forward). The IP checksum is always checked.
+ *
+ * Finally, the packet is sent to the upper layer protocol input function.
+ * 
+ * @param p the received IP packet (p->payload points to IP header)
+ * @param inp the netif on which this packet was received
+ * @return ERR_OK if the packet was processed (could return ERR_* if it wasn't
+ *         processed, but currently always returns ERR_OK)
+ */
+err_t
+ip_input(struct pbuf *p, struct netif *inp)
+{
+  struct ip_hdr *iphdr;
+  struct netif *netif;
+  u16_t iphdr_hlen;
+  u16_t iphdr_len;
+#if LWIP_DHCP
+  int check_ip_src=1;
+#endif /* LWIP_DHCP */
+
+  IP_STATS_INC(ip.recv);
+  snmp_inc_ipinreceives();
+
+  /* identify the IP header */
+  iphdr = p->payload;
+  if (IPH_V(iphdr) != 4) {
+    LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_WARNING, ("IP packet dropped due to bad version number %"U16_F"\n", IPH_V(iphdr)));
+    ip_debug_print(p);
+    pbuf_free(p);
+    IP_STATS_INC(ip.err);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipinhdrerrors();
+    return ERR_OK;
+  }
+
+  /* obtain IP header length in number of 32-bit words */
+  iphdr_hlen = IPH_HL(iphdr);
+  /* calculate IP header length in bytes */
+  iphdr_hlen *= 4;
+  /* obtain ip length in bytes */
+  iphdr_len = ntohs(IPH_LEN(iphdr));
+
+  /* header length exceeds first pbuf length, or ip length exceeds total pbuf length? */
+  if ((iphdr_hlen > p->len) || (iphdr_len > p->tot_len)) {
+    if (iphdr_hlen > p->len) {
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+        ("IP header (len %"U16_F") does not fit in first pbuf (len %"U16_F"), IP packet dropped.\n",
+        iphdr_hlen, p->len));
+    }
+    if (iphdr_len > p->tot_len) {
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+        ("IP (len %"U16_F") is longer than pbuf (len %"U16_F"), IP packet dropped.\n",
+        iphdr_len, p->tot_len));
+    }
+    /* free (drop) packet pbufs */
+    pbuf_free(p);
+    IP_STATS_INC(ip.lenerr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipindiscards();
+    return ERR_OK;
+  }
+
+  /* verify checksum */
+#if CHECKSUM_CHECK_IP
+  if (inet_chksum(iphdr, iphdr_hlen) != 0) {
+
+    LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+      ("Checksum (0x%"X16_F") failed, IP packet dropped.\n", inet_chksum(iphdr, iphdr_hlen)));
+    ip_debug_print(p);
+    pbuf_free(p);
+    IP_STATS_INC(ip.chkerr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipinhdrerrors();
+    return ERR_OK;
+  }
+#endif
+
+  /* Trim pbuf. This should have been done at the netif layer,
+   * but we'll do it anyway just to be sure that its done. */
+  pbuf_realloc(p, iphdr_len);
+
+  /* match packet against an interface, i.e. is this packet for us? */
+#if LWIP_IGMP
+  if (ip_addr_ismulticast(&(iphdr->dest))) {
+    if ((inp->flags & NETIF_FLAG_IGMP) && (igmp_lookfor_group(inp, &(iphdr->dest)))) {
+      netif = inp;
+    } else {
+      netif = NULL;
+    }
+  } else
+#endif /* LWIP_IGMP */
+  {
+    /* start trying with inp. if that's not acceptable, start walking the
+       list of configured netifs.
+       'first' is used as a boolean to mark whether we started walking the list */
+    int first = 1;
+    netif = inp;
+    do {
+      LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest 0x%"X32_F" netif->ip_addr 0x%"X32_F" (0x%"X32_F", 0x%"X32_F", 0x%"X32_F")\n",
+          iphdr->dest.addr, netif->ip_addr.addr,
+          iphdr->dest.addr & netif->netmask.addr,
+          netif->ip_addr.addr & netif->netmask.addr,
+          iphdr->dest.addr & ~(netif->netmask.addr)));
+
+      /* interface is up and configured? */
+      if ((netif_is_up(netif)) && (!ip_addr_isany(&(netif->ip_addr)))) {
+        /* unicast to this interface address? */
+        if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr)) ||
+            /* or broadcast on this interface network address? */
+            ip_addr_isbroadcast(&(iphdr->dest), netif)) {
+          LWIP_DEBUGF(IP_DEBUG, ("ip_input: packet accepted on interface %c%c\n",
+              netif->name[0], netif->name[1]));
+          /* break out of for loop */
+          break;
+        }
+      }
+      if (first) {
+        first = 0;
+        netif = netif_list;
+      } else {
+        netif = netif->next;
+      }
+      if (netif == inp) {
+        netif = netif->next;
+      }
+    } while(netif != NULL);
+  }
+
+#if LWIP_DHCP
+  /* Pass DHCP messages regardless of destination address. DHCP traffic is addressed
+   * using link layer addressing (such as Ethernet MAC) so we must not filter on IP.
+   * According to RFC 1542 section 3.1.1, referred by RFC 2131).
+   */
+  if (netif == NULL) {
+    /* remote port is DHCP server? */
+    if (IPH_PROTO(iphdr) == IP_PROTO_UDP) {
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip_input: UDP packet to DHCP client port %"U16_F"\n",
+        ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdr_hlen))->dest)));
+      if (ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdr_hlen))->dest) == DHCP_CLIENT_PORT) {
+        LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip_input: DHCP packet accepted.\n"));
+        netif = inp;
+        check_ip_src = 0;
+      }
+    }
+  }
+#endif /* LWIP_DHCP */
+
+  /* broadcast or multicast packet source address? Compliant with RFC 1122: 3.2.1.3 */
+#if LWIP_DHCP
+  /* DHCP servers need 0.0.0.0 to be allowed as source address (RFC 1.1.2.2: 3.2.1.3/a) */
+  if (check_ip_src && (iphdr->src.addr != 0))
+#endif /* LWIP_DHCP */
+  {  if ((ip_addr_isbroadcast(&(iphdr->src), inp)) ||
+         (ip_addr_ismulticast(&(iphdr->src)))) {
+      /* packet source is not valid */
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("ip_input: packet source is not valid.\n"));
+      /* free (drop) packet pbufs */
+      pbuf_free(p);
+      IP_STATS_INC(ip.drop);
+      snmp_inc_ipinaddrerrors();
+      snmp_inc_ipindiscards();
+      return ERR_OK;
+    }
+  }
+
+  /* packet not for us? */
+  if (netif == NULL) {
+    /* packet not for us, route or discard */
+    LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip_input: packet not for us.\n"));
+#if IP_FORWARD
+    /* non-broadcast packet? */
+    if (!ip_addr_isbroadcast(&(iphdr->dest), inp)) {
+      /* try to forward IP packet on (other) interfaces */
+      ip_forward(p, iphdr, inp);
+    } else
+#endif /* IP_FORWARD */
+    {
+      snmp_inc_ipinaddrerrors();
+      snmp_inc_ipindiscards();
+    }
+    pbuf_free(p);
+    return ERR_OK;
+  }
+  /* packet consists of multiple fragments? */
+  if ((IPH_OFFSET(iphdr) & htons(IP_OFFMASK | IP_MF)) != 0) {
+#if IP_REASSEMBLY /* packet fragment reassembly code present? */
+    LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip_reass()\n",
+      ntohs(IPH_ID(iphdr)), p->tot_len, ntohs(IPH_LEN(iphdr)), !!(IPH_OFFSET(iphdr) & htons(IP_MF)), (ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)*8));
+    /* reassemble the packet*/
+    p = ip_reass(p);
+    /* packet not fully reassembled yet? */
+    if (p == NULL) {
+      return ERR_OK;
+    }
+    iphdr = p->payload;
+#else /* IP_REASSEMBLY == 0, no packet fragment reassembly code present */
+    pbuf_free(p);
+    LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("IP packet dropped since it was fragmented (0x%"X16_F") (while IP_REASSEMBLY == 0).\n",
+      ntohs(IPH_OFFSET(iphdr))));
+    IP_STATS_INC(ip.opterr);
+    IP_STATS_INC(ip.drop);
+    /* unsupported protocol feature */
+    snmp_inc_ipinunknownprotos();
+    return ERR_OK;
+#endif /* IP_REASSEMBLY */
+  }
+
+#if IP_OPTIONS_ALLOWED == 0 /* no support for IP options in the IP header? */
+
+#if LWIP_IGMP
+  /* there is an extra "router alert" option in IGMP messages which we allow for but do not police */
+  if((iphdr_hlen > IP_HLEN &&  (IPH_PROTO(iphdr) != IP_PROTO_IGMP)) {
+#else
+  if (iphdr_hlen > IP_HLEN) {
+#endif /* LWIP_IGMP */
+    LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("IP packet dropped since there were IP options (while IP_OPTIONS_ALLOWED == 0).\n"));
+    pbuf_free(p);
+    IP_STATS_INC(ip.opterr);
+    IP_STATS_INC(ip.drop);
+    /* unsupported protocol feature */
+    snmp_inc_ipinunknownprotos();
+    return ERR_OK;
+  }
+#endif /* IP_OPTIONS_ALLOWED == 0 */
+
+  /* send to upper layers */
+  LWIP_DEBUGF(IP_DEBUG, ("ip_input: \n"));
+  ip_debug_print(p);
+  LWIP_DEBUGF(IP_DEBUG, ("ip_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len));
+
+  current_netif = inp;
+  current_header = iphdr;
+
+#if LWIP_RAW
+  /* raw input did not eat the packet? */
+  if (raw_input(p, inp) == 0)
+#endif /* LWIP_RAW */
+  {
+
+    switch (IPH_PROTO(iphdr)) {
+#if LWIP_UDP
+    case IP_PROTO_UDP:
+#if LWIP_UDPLITE
+    case IP_PROTO_UDPLITE:
+#endif /* LWIP_UDPLITE */
+      snmp_inc_ipindelivers();
+      udp_input(p, inp);
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+    case IP_PROTO_TCP:
+      snmp_inc_ipindelivers();
+      tcp_input(p, inp);
+      break;
+#endif /* LWIP_TCP */
+#if LWIP_ICMP
+    case IP_PROTO_ICMP:
+      snmp_inc_ipindelivers();
+      icmp_input(p, inp);
+      break;
+#endif /* LWIP_ICMP */
+#if LWIP_IGMP
+    case IP_PROTO_IGMP:
+      igmp_input(p,inp,&(iphdr->dest));
+      break;
+#endif /* LWIP_IGMP */
+    default:
+#if LWIP_ICMP
+      /* send ICMP destination protocol unreachable unless is was a broadcast */
+      if (!ip_addr_isbroadcast(&(iphdr->dest), inp) &&
+          !ip_addr_ismulticast(&(iphdr->dest))) {
+        p->payload = iphdr;
+        icmp_dest_unreach(p, ICMP_DUR_PROTO);
+      }
+#endif /* LWIP_ICMP */
+      pbuf_free(p);
+
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("Unsupported transport protocol %"U16_F"\n", IPH_PROTO(iphdr)));
+
+      IP_STATS_INC(ip.proterr);
+      IP_STATS_INC(ip.drop);
+      snmp_inc_ipinunknownprotos();
+    }
+  }
+
+  current_netif = NULL;
+  current_header = NULL;
+
+  return ERR_OK;
+}
+
+/**
+ * Sends an IP packet on a network interface. This function constructs
+ * the IP header and calculates the IP header checksum. If the source
+ * IP address is NULL, the IP address of the outgoing network
+ * interface is filled in as source address.
+ * If the destination IP address is IP_HDRINCL, p is assumed to already
+ * include an IP header and p->payload points to it instead of the data.
+ *
+ * @param p the packet to send (p->payload points to the data, e.g. next
+            protocol header; if dest == IP_HDRINCL, p already includes an IP
+            header and p->payload points to that IP header)
+ * @param src the source IP address to send from (if src == IP_ADDR_ANY, the
+ *         IP  address of the netif used to send is used as source address)
+ * @param dest the destination IP address to send the packet to
+ * @param ttl the TTL value to be set in the IP header
+ * @param tos the TOS value to be set in the IP header
+ * @param proto the PROTOCOL to be set in the IP header
+ * @param netif the netif on which to send this packet
+ * @return ERR_OK if the packet was sent OK
+ *         ERR_BUF if p doesn't have enough space for IP/LINK headers
+ *         returns errors returned by netif->output
+ *
+ * @note ip_id: RFC791 "some host may be able to simply use
+ *  unique identifiers independent of destination"
+ */
+err_t
+ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+             u8_t ttl, u8_t tos,
+             u8_t proto, struct netif *netif)
+{
+#if IP_OPTIONS_SEND
+  return ip_output_if_opt(p, src, dest, ttl, tos, proto, netif, NULL, 0);
+}
+
+/**
+ * Same as ip_output_if() but with the possibility to include IP options:
+ *
+ * @ param ip_options pointer to the IP options, copied into the IP header
+ * @ param optlen length of ip_options
+ */
+err_t ip_output_if_opt(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+       u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options,
+       u16_t optlen)
+{
+#endif /* IP_OPTIONS_SEND */
+  struct ip_hdr *iphdr;
+  static u16_t ip_id = 0;
+
+  snmp_inc_ipoutrequests();
+
+  /* Should the IP header be generated or is it already included in p? */
+  if (dest != IP_HDRINCL) {
+    u16_t ip_hlen = IP_HLEN;
+#if IP_OPTIONS_SEND
+    u16_t optlen_aligned = 0;
+    if (optlen != 0) {
+      /* round up to a multiple of 4 */
+      optlen_aligned = ((optlen + 3) & ~3);
+      ip_hlen += optlen_aligned;
+      /* First write in the IP options */
+      if (pbuf_header(p, optlen_aligned)) {
+        LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip_output_if_opt: not enough room for IP options in pbuf\n"));
+        IP_STATS_INC(ip.err);
+        snmp_inc_ipoutdiscards();
+        return ERR_BUF;
+      }
+      MEMCPY(p->payload, ip_options, optlen);
+      if (optlen < optlen_aligned) {
+        /* zero the remaining bytes */
+        memset(((char*)p->payload) + optlen, 0, optlen_aligned - optlen);
+      }
+    }
+#endif /* IP_OPTIONS_SEND */
+    /* generate IP header */
+    if (pbuf_header(p, IP_HLEN)) {
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip_output: not enough room for IP header in pbuf\n"));
+
+      IP_STATS_INC(ip.err);
+      snmp_inc_ipoutdiscards();
+      return ERR_BUF;
+    }
+
+    iphdr = p->payload;
+    LWIP_ASSERT("check that first pbuf can hold struct ip_hdr",
+               (p->len >= sizeof(struct ip_hdr)));
+
+    IPH_TTL_SET(iphdr, ttl);
+    IPH_PROTO_SET(iphdr, proto);
+
+    ip_addr_set(&(iphdr->dest), dest);
+
+    IPH_VHLTOS_SET(iphdr, 4, ip_hlen / 4, tos);
+    IPH_LEN_SET(iphdr, htons(p->tot_len));
+    IPH_OFFSET_SET(iphdr, 0);
+    IPH_ID_SET(iphdr, htons(ip_id));
+    ++ip_id;
+
+    if (ip_addr_isany(src)) {
+      ip_addr_set(&(iphdr->src), &(netif->ip_addr));
+    } else {
+      ip_addr_set(&(iphdr->src), src);
+    }
+
+    IPH_CHKSUM_SET(iphdr, 0);
+#if CHECKSUM_GEN_IP
+    IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, ip_hlen));
+#endif
+  } else {
+    /* IP header already included in p */
+    iphdr = p->payload;
+    dest = &(iphdr->dest);
+  }
+
+  IP_STATS_INC(ip.xmit);
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c%"U16_F"\n", netif->name[0], netif->name[1], netif->num));
+  ip_debug_print(p);
+
+#if ENABLE_LOOPBACK
+  if (ip_addr_cmp(dest, &netif->ip_addr)) {
+    /* Packet to self, enqueue it for loopback */
+    LWIP_DEBUGF(IP_DEBUG, ("netif_loop_output()"));
+    return netif_loop_output(netif, p, dest);
+  }
+#endif /* ENABLE_LOOPBACK */
+#if IP_FRAG
+  /* don't fragment if interface has mtu set to 0 [loopif] */
+  if (netif->mtu && (p->tot_len > netif->mtu)) {
+    return ip_frag(p,netif,dest);
+  }
+#endif
+
+  LWIP_DEBUGF(IP_DEBUG, ("netif->output()"));
+  return netif->output(netif, p, dest);
+}
+
+/**
+ * Simple interface to ip_output_if. It finds the outgoing network
+ * interface and calls upon ip_output_if to do the actual work.
+ *
+ * @param p the packet to send (p->payload points to the data, e.g. next
+            protocol header; if dest == IP_HDRINCL, p already includes an IP
+            header and p->payload points to that IP header)
+ * @param src the source IP address to send from (if src == IP_ADDR_ANY, the
+ *         IP  address of the netif used to send is used as source address)
+ * @param dest the destination IP address to send the packet to
+ * @param ttl the TTL value to be set in the IP header
+ * @param tos the TOS value to be set in the IP header
+ * @param proto the PROTOCOL to be set in the IP header
+ *
+ * @return ERR_RTE if no route is found
+ *         see ip_output_if() for more return values
+ */
+err_t
+ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+          u8_t ttl, u8_t tos, u8_t proto)
+{
+  struct netif *netif;
+
+  if ((netif = ip_route(dest)) == NULL) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to 0x%"X32_F"\n", dest->addr));
+    IP_STATS_INC(ip.rterr);
+    return ERR_RTE;
+  }
+
+  return ip_output_if(p, src, dest, ttl, tos, proto, netif);
+}
+
+#if LWIP_NETIF_HWADDRHINT
+/** Like ip_output, but takes and addr_hint pointer that is passed on to netif->addr_hint
+ *  before calling ip_output_if.
+ *
+ * @param p the packet to send (p->payload points to the data, e.g. next
+            protocol header; if dest == IP_HDRINCL, p already includes an IP
+            header and p->payload points to that IP header)
+ * @param src the source IP address to send from (if src == IP_ADDR_ANY, the
+ *         IP  address of the netif used to send is used as source address)
+ * @param dest the destination IP address to send the packet to
+ * @param ttl the TTL value to be set in the IP header
+ * @param tos the TOS value to be set in the IP header
+ * @param proto the PROTOCOL to be set in the IP header
+ * @param addr_hint address hint pointer set to netif->addr_hint before
+ *        calling ip_output_if()
+ *
+ * @return ERR_RTE if no route is found
+ *         see ip_output_if() for more return values
+ */
+err_t
+ip_output_hinted(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+          u8_t ttl, u8_t tos, u8_t proto, u8_t *addr_hint)
+{
+  struct netif *netif;
+  err_t err;
+
+  if ((netif = ip_route(dest)) == NULL) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to 0x%"X32_F"\n", dest->addr));
+    IP_STATS_INC(ip.rterr);
+    return ERR_RTE;
+  }
+
+  netif->addr_hint = addr_hint;
+  err = ip_output_if(p, src, dest, ttl, tos, proto, netif);
+  netif->addr_hint = NULL;
+
+  return err;
+}
+#endif /* LWIP_NETIF_HWADDRHINT*/
+
+#if IP_DEBUG
+/* Print an IP header by using LWIP_DEBUGF
+ * @param p an IP packet, p->payload pointing to the IP header
+ */
+void
+ip_debug_print(struct pbuf *p)
+{
+  struct ip_hdr *iphdr = p->payload;
+  u8_t *payload;
+
+  payload = (u8_t *)iphdr + IP_HLEN;
+
+  LWIP_DEBUGF(IP_DEBUG, ("IP header:\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" |%2"S16_F" |  0x%02"X16_F" |     %5"U16_F"     | (v, hl, tos, len)\n",
+                    IPH_V(iphdr),
+                    IPH_HL(iphdr),
+                    IPH_TOS(iphdr),
+                    ntohs(IPH_LEN(iphdr))));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|    %5"U16_F"      |%"U16_F"%"U16_F"%"U16_F"|    %4"U16_F"   | (id, flags, offset)\n",
+                    ntohs(IPH_ID(iphdr)),
+                    ntohs(IPH_OFFSET(iphdr)) >> 15 & 1,
+                    ntohs(IPH_OFFSET(iphdr)) >> 14 & 1,
+                    ntohs(IPH_OFFSET(iphdr)) >> 13 & 1,
+                    ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3"U16_F"  |  %3"U16_F"  |    0x%04"X16_F"     | (ttl, proto, chksum)\n",
+                    IPH_TTL(iphdr),
+                    IPH_PROTO(iphdr),
+                    ntohs(IPH_CHKSUM(iphdr))));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  | (src)\n",
+                    ip4_addr1(&iphdr->src),
+                    ip4_addr2(&iphdr->src),
+                    ip4_addr3(&iphdr->src),
+                    ip4_addr4(&iphdr->src)));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  | (dest)\n",
+                    ip4_addr1(&iphdr->dest),
+                    ip4_addr2(&iphdr->dest),
+                    ip4_addr3(&iphdr->dest),
+                    ip4_addr4(&iphdr->dest)));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+}
+#endif /* IP_DEBUG */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/ip_addr.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/ip_addr.c
new file mode 100644
index 0000000..94bf467
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/ip_addr.c
@@ -0,0 +1,84 @@
+/**
+ * @file
+ * This is the IPv4 address tools implementation.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+#include "lwip/ip_addr.h"
+#include "lwip/inet.h"
+#include "lwip/netif.h"
+
+#define IP_ADDR_ANY_VALUE 0x00000000UL
+#define IP_ADDR_BROADCAST_VALUE 0xffffffffUL
+
+/* used by IP_ADDR_ANY and IP_ADDR_BROADCAST in ip_addr.h */
+const struct ip_addr ip_addr_any = { IP_ADDR_ANY_VALUE };
+const struct ip_addr ip_addr_broadcast = { IP_ADDR_BROADCAST_VALUE };
+
+/**
+ * Determine if an address is a broadcast address on a network interface 
+ * 
+ * @param addr address to be checked
+ * @param netif the network interface against which the address is checked
+ * @return returns non-zero if the address is a broadcast address
+ */
+u8_t ip_addr_isbroadcast(struct ip_addr *addr, struct netif *netif)
+{
+  u32_t addr2test;
+
+  addr2test = addr->addr;
+  /* all ones (broadcast) or all zeroes (old skool broadcast) */
+  if ((~addr2test == IP_ADDR_ANY_VALUE) ||
+      (addr2test == IP_ADDR_ANY_VALUE))
+    return 1;
+  /* no broadcast support on this network interface? */
+  else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0)
+    /* the given address cannot be a broadcast address
+     * nor can we check against any broadcast addresses */
+    return 0;
+  /* address matches network interface address exactly? => no broadcast */
+  else if (addr2test == netif->ip_addr.addr)
+    return 0;
+  /*  on the same (sub) network... */
+  else if (ip_addr_netcmp(addr, &(netif->ip_addr), &(netif->netmask))
+         /* ...and host identifier bits are all ones? =>... */
+          && ((addr2test & ~netif->netmask.addr) ==
+           (IP_ADDR_BROADCAST_VALUE & ~netif->netmask.addr)))
+    /* => network broadcast address */
+    return 1;
+  else
+    return 0;
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/ip_frag.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/ip_frag.c
new file mode 100644
index 0000000..1939d83
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv4/ip_frag.c
@@ -0,0 +1,792 @@
+/**
+ * @file
+ * This is the IPv4 packet segmentation and reassembly implementation.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Jani Monoses  
+ *         Simon Goldschmidt
+ * original reassembly code by Adam Dunkels 
+ * 
+ */
+
+#include "lwip/opt.h"
+#include "lwip/ip_frag.h"
+#include "lwip/ip.h"
+#include "lwip/inet.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/netif.h"
+#include "lwip/snmp.h"
+#include "lwip/stats.h"
+#include "lwip/icmp.h"
+
+#include 
+
+#if IP_REASSEMBLY
+/**
+ * The IP reassembly code currently has the following limitations:
+ * - IP header options are not supported
+ * - fragments must not overlap (e.g. due to different routes),
+ *   currently, overlapping or duplicate fragments are thrown away
+ *   if IP_REASS_CHECK_OVERLAP=1 (the default)!
+ *
+ * @todo: work with IP header options
+ */
+
+/** Setting this to 0, you can turn off checking the fragments for overlapping
+ * regions. The code gets a little smaller. Only use this if you know that
+ * overlapping won't occur on your network! */
+#ifndef IP_REASS_CHECK_OVERLAP
+#define IP_REASS_CHECK_OVERLAP 1
+#endif /* IP_REASS_CHECK_OVERLAP */
+
+/** Set to 0 to prevent freeing the oldest datagram when the reassembly buffer is
+ * full (IP_REASS_MAX_PBUFS pbufs are enqueued). The code gets a little smaller.
+ * Datagrams will be freed by timeout only. Especially useful when MEMP_NUM_REASSDATA
+ * is set to 1, so one datagram can be reassembled at a time, only. */
+#ifndef IP_REASS_FREE_OLDEST
+#define IP_REASS_FREE_OLDEST 1
+#endif /* IP_REASS_FREE_OLDEST */
+
+#define IP_REASS_FLAG_LASTFRAG 0x01
+
+/** This is a helper struct which holds the starting
+ * offset and the ending offset of this fragment to
+ * easily chain the fragments.
+ * It has to be packed since it has to fit inside the IP header.
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_reass_helper {
+  PACK_STRUCT_FIELD(struct pbuf *next_pbuf);
+  PACK_STRUCT_FIELD(u16_t start);
+  PACK_STRUCT_FIELD(u16_t end);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define IP_ADDRESSES_AND_ID_MATCH(iphdrA, iphdrB)  \
+  (ip_addr_cmp(&(iphdrA)->src, &(iphdrB)->src) && \
+   ip_addr_cmp(&(iphdrA)->dest, &(iphdrB)->dest) && \
+   IPH_ID(iphdrA) == IPH_ID(iphdrB)) ? 1 : 0
+
+/* global variables */
+static struct ip_reassdata *reassdatagrams;
+static u16_t ip_reass_pbufcount;
+
+/* function prototypes */
+static void ip_reass_dequeue_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev);
+static int ip_reass_free_complete_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev);
+
+/**
+ * Reassembly timer base function
+ * for both NO_SYS == 0 and 1 (!).
+ *
+ * Should be called every 1000 msec (defined by IP_TMR_INTERVAL).
+ */
+void
+ip_reass_tmr(void)
+{
+  struct ip_reassdata *r, *prev = NULL;
+
+  r = reassdatagrams;
+  while (r != NULL) {
+    /* Decrement the timer. Once it reaches 0,
+     * clean up the incomplete fragment assembly */
+    if (r->timer > 0) {
+      r->timer--;
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer dec %"U16_F"\n",(u16_t)r->timer));
+      prev = r;
+      r = r->next;
+    } else {
+      /* reassembly timed out */
+      struct ip_reassdata *tmp;
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer timed out\n"));
+      tmp = r;
+      /* get the next pointer before freeing */
+      r = r->next;
+      /* free the helper struct and all enqueued pbufs */
+      ip_reass_free_complete_datagram(tmp, prev);
+     }
+   }
+}
+
+/**
+ * Free a datagram (struct ip_reassdata) and all its pbufs.
+ * Updates the total count of enqueued pbufs (ip_reass_pbufcount),
+ * SNMP counters and sends an ICMP time exceeded packet.
+ *
+ * @param ipr datagram to free
+ * @param prev the previous datagram in the linked list
+ * @return the number of pbufs freed
+ */
+static int
+ip_reass_free_complete_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev)
+{
+  int pbufs_freed = 0;
+  struct pbuf *p;
+  struct ip_reass_helper *iprh;
+
+  LWIP_ASSERT("prev != ipr", prev != ipr);
+  if (prev != NULL) {
+    LWIP_ASSERT("prev->next == ipr", prev->next == ipr);
+  }
+
+  snmp_inc_ipreasmfails();
+#if LWIP_ICMP
+  iprh = (struct ip_reass_helper *)ipr->p->payload;
+  if (iprh->start == 0) {
+    /* The first fragment was received, send ICMP time exceeded. */
+    /* First, de-queue the first pbuf from r->p. */
+    p = ipr->p;
+    ipr->p = iprh->next_pbuf;
+    /* Then, copy the original header into it. */
+    SMEMCPY(p->payload, &ipr->iphdr, IP_HLEN);
+    icmp_time_exceeded(p, ICMP_TE_FRAG);
+    pbufs_freed += pbuf_clen(p);
+    pbuf_free(p);
+  }
+#endif /* LWIP_ICMP */
+
+  /* First, free all received pbufs.  The individual pbufs need to be released 
+     separately as they have not yet been chained */
+  p = ipr->p;
+  while (p != NULL) {
+    struct pbuf *pcur;
+    iprh = (struct ip_reass_helper *)p->payload;
+    pcur = p;
+    /* get the next pointer before freeing */
+    p = iprh->next_pbuf;
+    pbufs_freed += pbuf_clen(pcur);
+    pbuf_free(pcur);    
+  }
+  /* Then, unchain the struct ip_reassdata from the list and free it. */
+  ip_reass_dequeue_datagram(ipr, prev);
+  LWIP_ASSERT("ip_reass_pbufcount >= clen", ip_reass_pbufcount >= pbufs_freed);
+  ip_reass_pbufcount -= pbufs_freed;
+
+  return pbufs_freed;
+}
+
+#if IP_REASS_FREE_OLDEST
+/**
+ * Free the oldest datagram to make room for enqueueing new fragments.
+ * The datagram 'fraghdr' belongs to is not freed!
+ *
+ * @param fraghdr IP header of the current fragment
+ * @param pbufs_needed number of pbufs needed to enqueue
+ *        (used for freeing other datagrams if not enough space)
+ * @return the number of pbufs freed
+ */
+static int
+ip_reass_remove_oldest_datagram(struct ip_hdr *fraghdr, int pbufs_needed)
+{
+  /* @todo Can't we simply remove the last datagram in the
+   *       linked list behind reassdatagrams?
+   */
+  struct ip_reassdata *r, *oldest, *prev;
+  int pbufs_freed = 0, pbufs_freed_current;
+  int other_datagrams;
+
+  /* Free datagrams until being allowed to enqueue 'pbufs_needed' pbufs,
+   * but don't free the datagram that 'fraghdr' belongs to! */
+  do {
+    oldest = NULL;
+    prev = NULL;
+    other_datagrams = 0;
+    r = reassdatagrams;
+    while (r != NULL) {
+      if (!IP_ADDRESSES_AND_ID_MATCH(&r->iphdr, fraghdr)) {
+        /* Not the same datagram as fraghdr */
+        other_datagrams++;
+        if (oldest == NULL) {
+          oldest = r;
+        } else if (r->timer <= oldest->timer) {
+          /* older than the previous oldest */
+          oldest = r;
+        }
+      }
+      if (r->next != NULL) {
+        prev = r;
+      }
+      r = r->next;
+    }
+    if (oldest != NULL) {
+      pbufs_freed_current = ip_reass_free_complete_datagram(oldest, prev);
+      pbufs_freed += pbufs_freed_current;
+    }
+  } while ((pbufs_freed < pbufs_needed) && (other_datagrams > 1));
+  return pbufs_freed;
+}
+#endif /* IP_REASS_FREE_OLDEST */
+
+/**
+ * Enqueues a new fragment into the fragment queue
+ * @param fraghdr points to the new fragments IP hdr
+ * @param clen number of pbufs needed to enqueue (used for freeing other datagrams if not enough space)
+ * @return A pointer to the queue location into which the fragment was enqueued
+ */
+static struct ip_reassdata*
+ip_reass_enqueue_new_datagram(struct ip_hdr *fraghdr, int clen)
+{
+  struct ip_reassdata* ipr;
+  /* No matching previous fragment found, allocate a new reassdata struct */
+  ipr = memp_malloc(MEMP_REASSDATA);
+  if (ipr == NULL) {
+#if IP_REASS_FREE_OLDEST
+    if (ip_reass_remove_oldest_datagram(fraghdr, clen) >= clen) {
+      ipr = memp_malloc(MEMP_REASSDATA);
+    }
+    if (ipr == NULL)
+#endif /* IP_REASS_FREE_OLDEST */
+    {
+      IPFRAG_STATS_INC(ip_frag.memerr);
+      LWIP_DEBUGF(IP_REASS_DEBUG,("Failed to alloc reassdata struct\n"));
+      return NULL;
+    }
+  }
+  memset(ipr, 0, sizeof(struct ip_reassdata));
+  ipr->timer = IP_REASS_MAXAGE;
+
+  /* enqueue the new structure to the front of the list */
+  ipr->next = reassdatagrams;
+  reassdatagrams = ipr;
+  /* copy the ip header for later tests and input */
+  /* @todo: no ip options supported? */
+  SMEMCPY(&(ipr->iphdr), fraghdr, IP_HLEN);
+  return ipr;
+}
+
+/**
+ * Dequeues a datagram from the datagram queue. Doesn't deallocate the pbufs.
+ * @param ipr points to the queue entry to dequeue
+ */
+static void
+ip_reass_dequeue_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev)
+{
+  
+  /* dequeue the reass struct  */
+  if (reassdatagrams == ipr) {
+    /* it was the first in the list */
+    reassdatagrams = ipr->next;
+  } else {
+    /* it wasn't the first, so it must have a valid 'prev' */
+    LWIP_ASSERT("sanity check linked list", prev != NULL);
+    prev->next = ipr->next;
+  }
+
+  /* now we can free the ip_reass struct */
+  memp_free(MEMP_REASSDATA, ipr);
+}
+
+/**
+ * Chain a new pbuf into the pbuf list that composes the datagram.  The pbuf list
+ * will grow over time as  new pbufs are rx.
+ * Also checks that the datagram passes basic continuity checks (if the last
+ * fragment was received at least once).
+ * @param root_p points to the 'root' pbuf for the current datagram being assembled.
+ * @param new_p points to the pbuf for the current fragment
+ * @return 0 if invalid, >0 otherwise
+ */
+static int
+ip_reass_chain_frag_into_datagram_and_validate(struct ip_reassdata *ipr, struct pbuf *new_p)
+{
+  struct ip_reass_helper *iprh, *iprh_tmp, *iprh_prev=NULL;
+  struct pbuf *q;
+  u16_t offset,len;
+  struct ip_hdr *fraghdr;
+  int valid = 1;
+
+  /* Extract length and fragment offset from current fragment */
+  fraghdr = (struct ip_hdr*)new_p->payload; 
+  len = ntohs(IPH_LEN(fraghdr)) - IPH_HL(fraghdr) * 4;
+  offset = (ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) * 8;
+
+  /* overwrite the fragment's ip header from the pbuf with our helper struct,
+   * and setup the embedded helper structure. */
+  /* make sure the struct ip_reass_helper fits into the IP header */
+  LWIP_ASSERT("sizeof(struct ip_reass_helper) <= IP_HLEN",
+              sizeof(struct ip_reass_helper) <= IP_HLEN);
+  iprh = (struct ip_reass_helper*)new_p->payload;
+  iprh->next_pbuf = NULL;
+  iprh->start = offset;
+  iprh->end = offset + len;
+
+  /* Iterate through until we either get to the end of the list (append),
+   * or we find on with a larger offset (insert). */
+  for (q = ipr->p; q != NULL;) {
+    iprh_tmp = (struct ip_reass_helper*)q->payload;
+    if (iprh->start < iprh_tmp->start) {
+      /* the new pbuf should be inserted before this */
+      iprh->next_pbuf = q;
+      if (iprh_prev != NULL) {
+        /* not the fragment with the lowest offset */
+#if IP_REASS_CHECK_OVERLAP
+        if ((iprh->start < iprh_prev->end) || (iprh->end > iprh_tmp->start)) {
+          /* fragment overlaps with previous or following, throw away */
+          goto freepbuf;
+        }
+#endif /* IP_REASS_CHECK_OVERLAP */
+        iprh_prev->next_pbuf = new_p;
+      } else {
+        /* fragment with the lowest offset */
+        ipr->p = new_p;
+      }
+      break;
+    } else if(iprh->start == iprh_tmp->start) {
+      /* received the same datagram twice: no need to keep the datagram */
+      goto freepbuf;
+#if IP_REASS_CHECK_OVERLAP
+    } else if(iprh->start < iprh_tmp->end) {
+      /* overlap: no need to keep the new datagram */
+      goto freepbuf;
+#endif /* IP_REASS_CHECK_OVERLAP */
+    } else {
+      /* Check if the fragments received so far have no wholes. */
+      if (iprh_prev != NULL) {
+        if (iprh_prev->end != iprh_tmp->start) {
+          /* There is a fragment missing between the current
+           * and the previous fragment */
+          valid = 0;
+        }
+      }
+    }
+    q = iprh_tmp->next_pbuf;
+    iprh_prev = iprh_tmp;
+  }
+
+  /* If q is NULL, then we made it to the end of the list. Determine what to do now */
+  if (q == NULL) {
+    if (iprh_prev != NULL) {
+      /* this is (for now), the fragment with the highest offset:
+       * chain it to the last fragment */
+#if IP_REASS_CHECK_OVERLAP
+      LWIP_ASSERT("check fragments don't overlap", iprh_prev->end <= iprh->start);
+#endif /* IP_REASS_CHECK_OVERLAP */
+      iprh_prev->next_pbuf = new_p;
+      if (iprh_prev->end != iprh->start) {
+        valid = 0;
+      }
+    } else {
+#if IP_REASS_CHECK_OVERLAP
+      LWIP_ASSERT("no previous fragment, this must be the first fragment!",
+        ipr->p == NULL);
+#endif /* IP_REASS_CHECK_OVERLAP */
+      /* this is the first fragment we ever received for this ip datagram */
+      ipr->p = new_p;
+    }
+  }
+
+  /* At this point, the validation part begins: */
+  /* If we already received the last fragment */
+  if ((ipr->flags & IP_REASS_FLAG_LASTFRAG) != 0) {
+    /* and had no wholes so far */
+    if (valid) {
+      /* then check if the rest of the fragments is here */
+      /* Check if the queue starts with the first datagram */
+      if (((struct ip_reass_helper*)ipr->p->payload)->start != 0) {
+        valid = 0;
+      } else {
+        /* and check that there are no wholes after this datagram */
+        iprh_prev = iprh;
+        q = iprh->next_pbuf;
+        while (q != NULL) {
+          iprh = (struct ip_reass_helper*)q->payload;
+          if (iprh_prev->end != iprh->start) {
+            valid = 0;
+            break;
+          }
+          iprh_prev = iprh;
+          q = iprh->next_pbuf;
+        }
+        /* if still valid, all fragments are received
+         * (because to the MF==0 already arrived */
+        if (valid) {
+          LWIP_ASSERT("sanity check", ipr->p != NULL);
+          LWIP_ASSERT("sanity check",
+            ((struct ip_reass_helper*)ipr->p->payload) != iprh);
+          LWIP_ASSERT("validate_datagram:next_pbuf!=NULL",
+            iprh->next_pbuf == NULL);
+          LWIP_ASSERT("validate_datagram:datagram end!=datagram len",
+            iprh->end == ipr->datagram_len);
+        }
+      }
+    }
+    /* If valid is 0 here, there are some fragments missing in the middle
+     * (since MF == 0 has already arrived). Such datagrams simply time out if
+     * no more fragments are received... */
+    return valid;
+  }
+  /* If we come here, not all fragments were received, yet! */
+  return 0; /* not yet valid! */
+#if IP_REASS_CHECK_OVERLAP
+freepbuf:
+  ip_reass_pbufcount -= pbuf_clen(new_p);
+  pbuf_free(new_p);
+  return 0;
+#endif /* IP_REASS_CHECK_OVERLAP */
+}
+
+/**
+ * Reassembles incoming IP fragments into an IP datagram.
+ *
+ * @param p points to a pbuf chain of the fragment
+ * @return NULL if reassembly is incomplete, ? otherwise
+ */
+struct pbuf *
+ip_reass(struct pbuf *p)
+{
+  struct pbuf *r;
+  struct ip_hdr *fraghdr;
+  struct ip_reassdata *ipr;
+  struct ip_reass_helper *iprh;
+  u16_t offset, len;
+  u8_t clen;
+  struct ip_reassdata *ipr_prev = NULL;
+
+  IPFRAG_STATS_INC(ip_frag.recv);
+  snmp_inc_ipreasmreqds();
+
+  fraghdr = (struct ip_hdr*)p->payload;
+
+  if ((IPH_HL(fraghdr) * 4) != IP_HLEN) {
+    LWIP_DEBUGF(IP_REASS_DEBUG,("ip_reass: IP options currently not supported!\n"));
+    IPFRAG_STATS_INC(ip_frag.err);
+    goto nullreturn;
+  }
+
+  offset = (ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) * 8;
+  len = ntohs(IPH_LEN(fraghdr)) - IPH_HL(fraghdr) * 4;
+
+  /* Check if we are allowed to enqueue more datagrams. */
+  clen = pbuf_clen(p);
+  if ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS) {
+#if IP_REASS_FREE_OLDEST
+    if (!ip_reass_remove_oldest_datagram(fraghdr, clen) ||
+        ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS))
+#endif /* IP_REASS_FREE_OLDEST */
+    {
+      /* No datagram could be freed and still too many pbufs enqueued */
+      LWIP_DEBUGF(IP_REASS_DEBUG,("ip_reass: Overflow condition: pbufct=%d, clen=%d, MAX=%d\n",
+        ip_reass_pbufcount, clen, IP_REASS_MAX_PBUFS));
+      IPFRAG_STATS_INC(ip_frag.memerr);
+      /* @todo: send ICMP time exceeded here? */
+      /* drop this pbuf */
+      goto nullreturn;
+    }
+  }
+
+  /* Look for the datagram the fragment belongs to in the current datagram queue,
+   * remembering the previous in the queue for later dequeueing. */
+  for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) {
+    /* Check if the incoming fragment matches the one currently present
+       in the reassembly buffer. If so, we proceed with copying the
+       fragment into the buffer. */
+    if (IP_ADDRESSES_AND_ID_MATCH(&ipr->iphdr, fraghdr)) {
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: matching previous fragment ID=%"X16_F"\n",
+        ntohs(IPH_ID(fraghdr))));
+      IPFRAG_STATS_INC(ip_frag.cachehit);
+      break;
+    }
+    ipr_prev = ipr;
+  }
+
+  if (ipr == NULL) {
+  /* Enqueue a new datagram into the datagram queue */
+    ipr = ip_reass_enqueue_new_datagram(fraghdr, clen);
+    /* Bail if unable to enqueue */
+    if(ipr == NULL) {
+      goto nullreturn;
+    }
+  } else {
+    if (((ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) && 
+      ((ntohs(IPH_OFFSET(&ipr->iphdr)) & IP_OFFMASK) != 0)) {
+      /* ipr->iphdr is not the header from the first fragment, but fraghdr is
+       * -> copy fraghdr into ipr->iphdr since we want to have the header
+       * of the first fragment (for ICMP time exceeded and later, for copying
+       * all options, if supported)*/
+      SMEMCPY(&ipr->iphdr, fraghdr, IP_HLEN);
+    }
+  }
+  /* Track the current number of pbufs current 'in-flight', in order to limit 
+  the number of fragments that may be enqueued at any one time */
+  ip_reass_pbufcount += clen;
+
+  /* At this point, we have either created a new entry or pointing 
+   * to an existing one */
+
+  /* check for 'no more fragments', and update queue entry*/
+  if ((ntohs(IPH_OFFSET(fraghdr)) & IP_MF) == 0) {
+    ipr->flags |= IP_REASS_FLAG_LASTFRAG;
+    ipr->datagram_len = offset + len;
+    LWIP_DEBUGF(IP_REASS_DEBUG,
+     ("ip_reass: last fragment seen, total len %"S16_F"\n",
+      ipr->datagram_len));
+  }
+  /* find the right place to insert this pbuf */
+  /* @todo: trim pbufs if fragments are overlapping */
+  if (ip_reass_chain_frag_into_datagram_and_validate(ipr, p)) {
+    /* the totally last fragment (flag more fragments = 0) was received at least
+     * once AND all fragments are received */
+    ipr->datagram_len += IP_HLEN;
+
+    /* save the second pbuf before copying the header over the pointer */
+    r = ((struct ip_reass_helper*)ipr->p->payload)->next_pbuf;
+
+    /* copy the original ip header back to the first pbuf */
+    fraghdr = (struct ip_hdr*)(ipr->p->payload);
+    SMEMCPY(fraghdr, &ipr->iphdr, IP_HLEN);
+    IPH_LEN_SET(fraghdr, htons(ipr->datagram_len));
+    IPH_OFFSET_SET(fraghdr, 0);
+    IPH_CHKSUM_SET(fraghdr, 0);
+    /* @todo: do we need to set calculate the correct checksum? */
+    IPH_CHKSUM_SET(fraghdr, inet_chksum(fraghdr, IP_HLEN));
+
+    p = ipr->p;
+
+    /* chain together the pbufs contained within the reass_data list. */
+    while(r != NULL) {
+      iprh = (struct ip_reass_helper*)r->payload;
+
+      /* hide the ip header for every succeding fragment */
+      pbuf_header(r, -IP_HLEN);
+      pbuf_cat(p, r);
+      r = iprh->next_pbuf;
+    }
+    /* release the sources allocate for the fragment queue entry */
+    ip_reass_dequeue_datagram(ipr, ipr_prev);
+
+    /* and adjust the number of pbufs currently queued for reassembly. */
+    ip_reass_pbufcount -= pbuf_clen(p);
+
+    /* Return the pbuf chain */
+    return p;
+  }
+  /* the datagram is not (yet?) reassembled completely */
+  LWIP_DEBUGF(IP_REASS_DEBUG,("ip_reass_pbufcount: %d out\n", ip_reass_pbufcount));
+  return NULL;
+
+nullreturn:
+  LWIP_DEBUGF(IP_REASS_DEBUG,("ip_reass: nullreturn\n"));
+  IPFRAG_STATS_INC(ip_frag.drop);
+  pbuf_free(p);
+  return NULL;
+}
+#endif /* IP_REASSEMBLY */
+
+#if IP_FRAG
+#if IP_FRAG_USES_STATIC_BUF
+static u8_t buf[LWIP_MEM_ALIGN_SIZE(IP_FRAG_MAX_MTU + MEM_ALIGNMENT - 1)];
+#endif /* IP_FRAG_USES_STATIC_BUF */
+
+/**
+ * Fragment an IP datagram if too large for the netif.
+ *
+ * Chop the datagram in MTU sized chunks and send them in order
+ * by using a fixed size static memory buffer (PBUF_REF) or
+ * point PBUF_REFs into p (depending on IP_FRAG_USES_STATIC_BUF).
+ *
+ * @param p ip packet to send
+ * @param netif the netif on which to send
+ * @param dest destination ip address to which to send
+ *
+ * @return ERR_OK if sent successfully, err_t otherwise
+ */
+err_t 
+ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest)
+{
+  struct pbuf *rambuf;
+#if IP_FRAG_USES_STATIC_BUF
+  struct pbuf *header;
+#else
+  struct pbuf *newpbuf;
+  struct ip_hdr *original_iphdr;
+#endif
+  struct ip_hdr *iphdr;
+  u16_t nfb;
+  u16_t left, cop;
+  u16_t mtu = netif->mtu;
+  u16_t ofo, omf;
+  u16_t last;
+  u16_t poff = IP_HLEN;
+  u16_t tmp;
+#if !IP_FRAG_USES_STATIC_BUF
+  u16_t newpbuflen = 0;
+  u16_t left_to_copy;
+#endif
+
+  /* Get a RAM based MTU sized pbuf */
+#if IP_FRAG_USES_STATIC_BUF
+  /* When using a static buffer, we use a PBUF_REF, which we will
+   * use to reference the packet (without link header).
+   * Layer and length is irrelevant.
+   */
+  rambuf = pbuf_alloc(PBUF_LINK, 0, PBUF_REF);
+  if (rambuf == NULL) {
+    LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_frag: pbuf_alloc(PBUF_LINK, 0, PBUF_REF) failed\n"));
+    return ERR_MEM;
+  }
+  rambuf->tot_len = rambuf->len = mtu;
+  rambuf->payload = LWIP_MEM_ALIGN((void *)buf);
+
+  /* Copy the IP header in it */
+  iphdr = rambuf->payload;
+  SMEMCPY(iphdr, p->payload, IP_HLEN);
+#else /* IP_FRAG_USES_STATIC_BUF */
+  original_iphdr = p->payload;
+  iphdr = original_iphdr;
+#endif /* IP_FRAG_USES_STATIC_BUF */
+
+  /* Save original offset */
+  tmp = ntohs(IPH_OFFSET(iphdr));
+  ofo = tmp & IP_OFFMASK;
+  omf = tmp & IP_MF;
+
+  left = p->tot_len - IP_HLEN;
+
+  nfb = (mtu - IP_HLEN) / 8;
+
+  while (left) {
+    last = (left <= mtu - IP_HLEN);
+
+    /* Set new offset and MF flag */
+    tmp = omf | (IP_OFFMASK & (ofo));
+    if (!last)
+      tmp = tmp | IP_MF;
+
+    /* Fill this fragment */
+    cop = last ? left : nfb * 8;
+
+#if IP_FRAG_USES_STATIC_BUF
+    poff += pbuf_copy_partial(p, (u8_t*)iphdr + IP_HLEN, cop, poff);
+#else /* IP_FRAG_USES_STATIC_BUF */
+    /* When not using a static buffer, create a chain of pbufs.
+     * The first will be a PBUF_RAM holding the link and IP header.
+     * The rest will be PBUF_REFs mirroring the pbuf chain to be fragged,
+     * but limited to the size of an mtu.
+     */
+    rambuf = pbuf_alloc(PBUF_LINK, IP_HLEN, PBUF_RAM);
+    if (rambuf == NULL) {
+      return ERR_MEM;
+    }
+    LWIP_ASSERT("this needs a pbuf in one piece!",
+                (p->len >= (IP_HLEN)));
+    SMEMCPY(rambuf->payload, original_iphdr, IP_HLEN);
+    iphdr = rambuf->payload;
+
+    /* Can just adjust p directly for needed offset. */
+    p->payload = (u8_t *)p->payload + poff;
+    p->len -= poff;
+
+    left_to_copy = cop;
+    while (left_to_copy) {
+      newpbuflen = (left_to_copy < p->len) ? left_to_copy : p->len;
+      /* Is this pbuf already empty? */
+      if (!newpbuflen) {
+        p = p->next;
+        continue;
+      }
+      newpbuf = pbuf_alloc(PBUF_RAW, 0, PBUF_REF);
+      if (newpbuf == NULL) {
+        pbuf_free(rambuf);
+        return ERR_MEM;
+      }
+      /* Mirror this pbuf, although we might not need all of it. */
+      newpbuf->payload = p->payload;
+      newpbuf->len = newpbuf->tot_len = newpbuflen;
+      /* Add it to end of rambuf's chain, but using pbuf_cat, not pbuf_chain
+       * so that it is removed when pbuf_dechain is later called on rambuf.
+       */
+      pbuf_cat(rambuf, newpbuf);
+      left_to_copy -= newpbuflen;
+      if (left_to_copy)
+        p = p->next;
+    }
+    poff = newpbuflen;
+#endif /* IP_FRAG_USES_STATIC_BUF */
+
+    /* Correct header */
+    IPH_OFFSET_SET(iphdr, htons(tmp));
+    IPH_LEN_SET(iphdr, htons(cop + IP_HLEN));
+    IPH_CHKSUM_SET(iphdr, 0);
+    IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
+
+#if IP_FRAG_USES_STATIC_BUF
+    if (last)
+      pbuf_realloc(rambuf, left + IP_HLEN);
+
+    /* This part is ugly: we alloc a RAM based pbuf for 
+     * the link level header for each chunk and then 
+     * free it.A PBUF_ROM style pbuf for which pbuf_header
+     * worked would make things simpler.
+     */
+    header = pbuf_alloc(PBUF_LINK, 0, PBUF_RAM);
+    if (header != NULL) {
+      pbuf_chain(header, rambuf);
+      netif->output(netif, header, dest);
+      IPFRAG_STATS_INC(ip_frag.xmit);
+      snmp_inc_ipfragcreates();
+      pbuf_free(header);
+    } else {
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_frag: pbuf_alloc() for header failed\n"));
+      pbuf_free(rambuf);
+      return ERR_MEM;
+    }
+#else /* IP_FRAG_USES_STATIC_BUF */
+    /* No need for separate header pbuf - we allowed room for it in rambuf
+     * when allocated.
+     */
+    netif->output(netif, rambuf, dest);
+    IPFRAG_STATS_INC(ip_frag.xmit);
+
+    /* Unfortunately we can't reuse rambuf - the hardware may still be
+     * using the buffer. Instead we free it (and the ensuing chain) and
+     * recreate it next time round the loop. If we're lucky the hardware
+     * will have already sent the packet, the free will really free, and
+     * there will be zero memory penalty.
+     */
+    
+    pbuf_free(rambuf);
+#endif /* IP_FRAG_USES_STATIC_BUF */
+    left -= cop;
+    ofo += nfb;
+  }
+#if IP_FRAG_USES_STATIC_BUF
+  pbuf_free(rambuf);
+#endif /* IP_FRAG_USES_STATIC_BUF */
+  snmp_inc_ipfragoks();
+  return ERR_OK;
+}
+#endif /* IP_FRAG */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv6/README b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv6/README
new file mode 100644
index 0000000..3620004
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv6/README
@@ -0,0 +1 @@
+IPv6 support in lwIP is very experimental.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv6/icmp6.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv6/icmp6.c
new file mode 100644
index 0000000..4fcc895
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv6/icmp6.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* Some ICMP messages should be passed to the transport protocols. This
+   is not implemented. */
+
+#include "lwip/opt.h"
+
+#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/icmp.h"
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+#include "lwip/def.h"
+#include "lwip/stats.h"
+
+void
+icmp_input(struct pbuf *p, struct netif *inp)
+{
+  u8_t type;
+  struct icmp_echo_hdr *iecho;
+  struct ip_hdr *iphdr;
+  struct ip_addr tmpaddr;
+
+  ICMP_STATS_INC(icmp.recv);
+
+  /* TODO: check length before accessing payload! */
+
+  type = ((u8_t *)p->payload)[0];
+
+  switch (type) {
+  case ICMP6_ECHO:
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
+
+    if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n"));
+
+      pbuf_free(p);
+      ICMP_STATS_INC(icmp.lenerr);
+      return;
+    }
+    iecho = p->payload;
+    iphdr = (struct ip_hdr *)((u8_t *)p->payload - IP_HLEN);
+    if (inet_chksum_pbuf(p) != 0) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%"X16_F")\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len)));
+      ICMP_STATS_INC(icmp.chkerr);
+    /*      return;*/
+    }
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp: p->len %"S16_F" p->tot_len %"S16_F"\n", p->len, p->tot_len));
+    ip_addr_set(&tmpaddr, &(iphdr->src));
+    ip_addr_set(&(iphdr->src), &(iphdr->dest));
+    ip_addr_set(&(iphdr->dest), &tmpaddr);
+    iecho->type = ICMP6_ER;
+    /* adjust the checksum */
+    if (iecho->chksum >= htons(0xffff - (ICMP6_ECHO << 8))) {
+      iecho->chksum += htons(ICMP6_ECHO << 8) + 1;
+    } else {
+      iecho->chksum += htons(ICMP6_ECHO << 8);
+    }
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%"X16_F")\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len)));
+    ICMP_STATS_INC(icmp.xmit);
+
+    /*    LWIP_DEBUGF("icmp: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len);*/
+    ip_output_if (p, &(iphdr->src), IP_HDRINCL,
+     iphdr->hoplim, IP_PROTO_ICMP, inp);
+    break;
+  default:
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" not supported.\n", (s16_t)type));
+    ICMP_STATS_INC(icmp.proterr);
+    ICMP_STATS_INC(icmp.drop);
+  }
+
+  pbuf_free(p);
+}
+
+void
+icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  struct icmp_dur_hdr *idur;
+
+  /* @todo: can this be PBUF_LINK instead of PBUF_IP? */
+  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
+  /* ICMP header + IP header + 8 bytes of data */
+  if (q == NULL) {
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_dest_unreach: failed to allocate pbuf for ICMP packet.\n"));
+    pbuf_free(p);
+    return;
+  }
+  LWIP_ASSERT("check that first pbuf can hold icmp message",
+             (q->len >= (8 + IP_HLEN + 8)));
+
+  iphdr = p->payload;
+
+  idur = q->payload;
+  idur->type = (u8_t)ICMP6_DUR;
+  idur->icode = (u8_t)t;
+
+  SMEMCPY((u8_t *)q->payload + 8, p->payload, IP_HLEN + 8);
+
+  /* calculate checksum */
+  idur->chksum = 0;
+  idur->chksum = inet_chksum(idur, q->len);
+  ICMP_STATS_INC(icmp.xmit);
+
+  ip_output(q, NULL,
+      (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+void
+icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  struct icmp_te_hdr *tehdr;
+
+  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded\n"));
+
+  /* @todo: can this be PBUF_LINK instead of PBUF_IP? */
+  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
+  /* ICMP header + IP header + 8 bytes of data */
+  if (q == NULL) {
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_dest_unreach: failed to allocate pbuf for ICMP packet.\n"));
+    pbuf_free(p);
+    return;
+  }
+  LWIP_ASSERT("check that first pbuf can hold icmp message",
+             (q->len >= (8 + IP_HLEN + 8)));
+
+  iphdr = p->payload;
+
+  tehdr = q->payload;
+  tehdr->type = (u8_t)ICMP6_TE;
+  tehdr->icode = (u8_t)t;
+
+  /* copy fields from original packet */
+  SMEMCPY((u8_t *)q->payload + 8, (u8_t *)p->payload, IP_HLEN + 8);
+
+  /* calculate checksum */
+  tehdr->chksum = 0;
+  tehdr->chksum = inet_chksum(tehdr, q->len);
+  ICMP_STATS_INC(icmp.xmit);
+  ip_output(q, NULL,
+      (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+#endif /* LWIP_ICMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv6/inet6.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv6/inet6.c
new file mode 100644
index 0000000..c3de85c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv6/inet6.c
@@ -0,0 +1,163 @@
+/**
+ * @file
+ * Functions common to all TCP/IPv6 modules, such as the Internet checksum and the
+ * byte order functions.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/inet.h"
+
+/* chksum:
+ *
+ * Sums up all 16 bit words in a memory portion. Also includes any odd byte.
+ * This function is used by the other checksum functions.
+ *
+ * For now, this is not optimized. Must be optimized for the particular processor
+ * arcitecture on which it is to run. Preferebly coded in assembler.
+ */
+
+static u32_t
+chksum(void *dataptr, u16_t len)
+{
+  u16_t *sdataptr = dataptr;
+  u32_t acc;
+  
+  
+  for(acc = 0; len > 1; len -= 2) {
+    acc += *sdataptr++;
+  }
+
+  /* add up any odd byte */
+  if (len == 1) {
+    acc += htons((u16_t)(*(u8_t *)dataptr) << 8);
+  }
+
+  return acc;
+
+}
+
+/* inet_chksum_pseudo:
+ *
+ * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
+ */
+
+u16_t
+inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u32_t proto_len)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped, i;
+
+  acc = 0;
+  swapped = 0;
+  for(q = p; q != NULL; q = q->next) {    
+    acc += chksum(q->payload, q->len);
+    while (acc >> 16) {
+      acc = (acc & 0xffff) + (acc >> 16);
+    }
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+    }
+  }
+
+  if (swapped) {
+    acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+  }
+  
+  for(i = 0; i < 8; i++) {
+    acc += ((u16_t *)src->addr)[i] & 0xffff;
+    acc += ((u16_t *)dest->addr)[i] & 0xffff;
+    while (acc >> 16) {
+      acc = (acc & 0xffff) + (acc >> 16);
+    }
+  }
+  acc += (u16_t)htons((u16_t)proto);
+  acc += ((u16_t *)&proto_len)[0] & 0xffff;
+  acc += ((u16_t *)&proto_len)[1] & 0xffff;
+
+  while (acc >> 16) {
+    acc = (acc & 0xffff) + (acc >> 16);
+  }
+  return ~(acc & 0xffff);
+}
+
+/* inet_chksum:
+ *
+ * Calculates the Internet checksum over a portion of memory. Used primarely for IP
+ * and ICMP.
+ */
+
+u16_t
+inet_chksum(void *dataptr, u16_t len)
+{
+  u32_t acc, sum;
+
+  acc = chksum(dataptr, len);
+  sum = (acc & 0xffff) + (acc >> 16);
+  sum += (sum >> 16);
+  return ~(sum & 0xffff);
+}
+
+u16_t
+inet_chksum_pbuf(struct pbuf *p)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped;
+  
+  acc = 0;
+  swapped = 0;
+  for(q = p; q != NULL; q = q->next) {
+    acc += chksum(q->payload, q->len);
+    while (acc >> 16) {
+      acc = (acc & 0xffff) + (acc >> 16);
+    }    
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = (acc & 0xff << 8) | (acc & 0xff00 >> 8);
+    }
+  }
+ 
+  if (swapped) {
+    acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+  }
+  return ~(acc & 0xffff);
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv6/ip6.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv6/ip6.c
new file mode 100644
index 0000000..7e43420
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv6/ip6.c
@@ -0,0 +1,397 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+
+/* ip.c
+ *
+ * This is the code for the IP layer for IPv6.
+ *
+ */
+
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/ip.h"
+#include "lwip/inet.h"
+#include "lwip/netif.h"
+#include "lwip/icmp.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+
+/* ip_init:
+ *
+ * Initializes the IP layer.
+ */
+
+void
+ip_init(void)
+{
+}
+
+/* ip_route:
+ *
+ * Finds the appropriate network interface for a given IP address. It searches the
+ * list of network interfaces linearly. A match is found if the masked IP address of
+ * the network interface equals the masked IP address given to the function.
+ */
+
+struct netif *
+ip_route(struct ip_addr *dest)
+{
+  struct netif *netif;
+
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+    if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) {
+      return netif;
+    }
+  }
+
+  return netif_default;
+}
+
+/* ip_forward:
+ *
+ * Forwards an IP packet. It finds an appropriate route for the packet, decrements
+ * the TTL value of the packet, adjusts the checksum and outputs the packet on the
+ * appropriate interface.
+ */
+
+static void
+ip_forward(struct pbuf *p, struct ip_hdr *iphdr)
+{
+  struct netif *netif;
+
+  PERF_START;
+
+  if ((netif = ip_route((struct ip_addr *)&(iphdr->dest))) == NULL) {
+
+    LWIP_DEBUGF(IP_DEBUG, ("ip_input: no forwarding route found for "));
+#if IP_DEBUG
+    ip_addr_debug_print(IP_DEBUG, ((struct ip_addr *)&(iphdr->dest)));
+#endif /* IP_DEBUG */
+    LWIP_DEBUGF(IP_DEBUG, ("\n"));
+    pbuf_free(p);
+    return;
+  }
+  /* Decrement TTL and send ICMP if ttl == 0. */
+  if (--iphdr->hoplim == 0) {
+#if LWIP_ICMP
+    /* Don't send ICMP messages in response to ICMP messages */
+    if (iphdr->nexthdr != IP_PROTO_ICMP) {
+      icmp_time_exceeded(p, ICMP_TE_TTL);
+    }
+#endif /* LWIP_ICMP */
+    pbuf_free(p);
+    return;
+  }
+
+  /* Incremental update of the IP checksum. */
+  /*  if (iphdr->chksum >= htons(0xffff - 0x100)) {
+    iphdr->chksum += htons(0x100) + 1;
+  } else {
+    iphdr->chksum += htons(0x100);
+    }*/
+
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to "));
+#if IP_DEBUG
+  ip_addr_debug_print(IP_DEBUG, ((struct ip_addr *)&(iphdr->dest)));
+#endif /* IP_DEBUG */
+  LWIP_DEBUGF(IP_DEBUG, ("\n"));
+
+  IP_STATS_INC(ip.fw);
+  IP_STATS_INC(ip.xmit);
+
+  PERF_STOP("ip_forward");
+
+  netif->output(netif, p, (struct ip_addr *)&(iphdr->dest));
+}
+
+/* ip_input:
+ *
+ * This function is called by the network interface device driver when an IP packet is
+ * received. The function does the basic checks of the IP header such as packet size
+ * being at least larger than the header size etc. If the packet was not destined for
+ * us, the packet is forwarded (using ip_forward). The IP checksum is always checked.
+ *
+ * Finally, the packet is sent to the upper layer protocol input function.
+ */
+
+void
+ip_input(struct pbuf *p, struct netif *inp) {
+  struct ip_hdr *iphdr;
+  struct netif *netif;
+
+
+  PERF_START;
+
+#if IP_DEBUG
+  ip_debug_print(p);
+#endif /* IP_DEBUG */
+
+
+  IP_STATS_INC(ip.recv);
+
+  /* identify the IP header */
+  iphdr = p->payload;
+
+
+  if (iphdr->v != 6) {
+    LWIP_DEBUGF(IP_DEBUG, ("IP packet dropped due to bad version number\n"));
+#if IP_DEBUG
+    ip_debug_print(p);
+#endif /* IP_DEBUG */
+    pbuf_free(p);
+    IP_STATS_INC(ip.err);
+    IP_STATS_INC(ip.drop);
+    return;
+  }
+
+  /* is this packet for us? */
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+#if IP_DEBUG
+    LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest "));
+    ip_addr_debug_print(IP_DEBUG, ((struct ip_addr *)&(iphdr->dest)));
+    LWIP_DEBUGF(IP_DEBUG, ("netif->ip_addr "));
+    ip_addr_debug_print(IP_DEBUG, ((struct ip_addr *)&(iphdr->dest)));
+    LWIP_DEBUGF(IP_DEBUG, ("\n"));
+#endif /* IP_DEBUG */
+    if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr))) {
+      break;
+    }
+  }
+
+
+  if (netif == NULL) {
+    /* packet not for us, route or discard */
+#if IP_FORWARD
+    ip_forward(p, iphdr);
+#endif
+    pbuf_free(p);
+    return;
+  }
+
+  pbuf_realloc(p, IP_HLEN + ntohs(iphdr->len));
+
+  /* send to upper layers */
+#if IP_DEBUG
+  /*  LWIP_DEBUGF("ip_input: \n");
+  ip_debug_print(p);
+  LWIP_DEBUGF("ip_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len);*/
+#endif /* IP_DEBUG */
+
+  if(pbuf_header(p, -IP_HLEN)) {
+    LWIP_ASSERT("Can't move over header in packet", 0);
+    return;
+  }
+
+  switch (iphdr->nexthdr) {
+  case IP_PROTO_UDP:
+    udp_input(p, inp);
+    break;
+  case IP_PROTO_TCP:
+    tcp_input(p, inp);
+    break;
+#if LWIP_ICMP
+  case IP_PROTO_ICMP:
+    icmp_input(p, inp);
+    break;
+#endif /* LWIP_ICMP */
+  default:
+#if LWIP_ICMP
+    /* send ICMP destination protocol unreachable */
+    icmp_dest_unreach(p, ICMP_DUR_PROTO);
+#endif /* LWIP_ICMP */
+    pbuf_free(p);
+    LWIP_DEBUGF(IP_DEBUG, ("Unsupported transport protocol %"U16_F"\n",
+          iphdr->nexthdr));
+
+    IP_STATS_INC(ip.proterr);
+    IP_STATS_INC(ip.drop);
+  }
+  PERF_STOP("ip_input");
+}
+
+
+/* ip_output_if:
+ *
+ * Sends an IP packet on a network interface. This function constructs the IP header
+ * and calculates the IP header checksum. If the source IP address is NULL,
+ * the IP address of the outgoing network interface is filled in as source address.
+ */
+
+err_t
+ip_output_if (struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+       u8_t ttl,
+       u8_t proto, struct netif *netif)
+{
+  struct ip_hdr *iphdr;
+
+  PERF_START;
+
+  LWIP_DEBUGF(IP_DEBUG, ("len %"U16_F" tot_len %"U16_F"\n", p->len, p->tot_len));
+  if (pbuf_header(p, IP_HLEN)) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_output: not enough room for IP header in pbuf\n"));
+    IP_STATS_INC(ip.err);
+
+    return ERR_BUF;
+  }
+  LWIP_DEBUGF(IP_DEBUG, ("len %"U16_F" tot_len %"U16_F"\n", p->len, p->tot_len));
+
+  iphdr = p->payload;
+
+
+  if (dest != IP_HDRINCL) {
+    LWIP_DEBUGF(IP_DEBUG, ("!IP_HDRLINCL\n"));
+    iphdr->hoplim = ttl;
+    iphdr->nexthdr = proto;
+    iphdr->len = htons(p->tot_len - IP_HLEN);
+    ip_addr_set(&(iphdr->dest), dest);
+
+    iphdr->v = 6;
+
+    if (ip_addr_isany(src)) {
+      ip_addr_set(&(iphdr->src), &(netif->ip_addr));
+    } else {
+      ip_addr_set(&(iphdr->src), src);
+    }
+
+  } else {
+    dest = &(iphdr->dest);
+  }
+
+  IP_STATS_INC(ip.xmit);
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c (len %"U16_F")\n", netif->name[0], netif->name[1], p->tot_len));
+#if IP_DEBUG
+  ip_debug_print(p);
+#endif /* IP_DEBUG */
+
+  PERF_STOP("ip_output_if");
+  return netif->output(netif, p, dest);
+}
+
+/* ip_output:
+ *
+ * Simple interface to ip_output_if. It finds the outgoing network interface and
+ * calls upon ip_output_if to do the actual work.
+ */
+
+err_t
+ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+    u8_t ttl, u8_t proto)
+{
+  struct netif *netif;
+  if ((netif = ip_route(dest)) == NULL) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to 0x%"X32_F"\n", dest->addr));
+    IP_STATS_INC(ip.rterr);
+    return ERR_RTE;
+  }
+
+  return ip_output_if (p, src, dest, ttl, proto, netif);
+}
+
+#if LWIP_NETIF_HWADDRHINT
+err_t
+ip_output_hinted(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+          u8_t ttl, u8_t tos, u8_t proto, u8_t *addr_hint)
+{
+  struct netif *netif;
+  err_t err;
+
+  if ((netif = ip_route(dest)) == NULL) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to 0x%"X32_F"\n", dest->addr));
+    IP_STATS_INC(ip.rterr);
+    return ERR_RTE;
+  }
+
+  netif->addr_hint = addr_hint;
+  err = ip_output_if(p, src, dest, ttl, tos, proto, netif);
+  netif->addr_hint = NULL;
+
+  return err;
+}
+#endif /* LWIP_NETIF_HWADDRHINT*/
+
+#if IP_DEBUG
+void
+ip_debug_print(struct pbuf *p)
+{
+  struct ip_hdr *iphdr = p->payload;
+
+  LWIP_DEBUGF(IP_DEBUG, ("IP header:\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" |  %"X16_F"%"X16_F"  |      %"X16_F"%"X16_F"           | (v, traffic class, flow label)\n",
+        iphdr->v,
+        iphdr->tclass1, iphdr->tclass2,
+        iphdr->flow1, iphdr->flow2));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|    %5"U16_F"      | %2"U16_F"  |  %2"U16_F"   | (len, nexthdr, hoplim)\n",
+        ntohs(iphdr->len),
+        iphdr->nexthdr,
+        iphdr->hoplim));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (src)\n",
+        (ntohl(iphdr->src.addr[0]) >> 16) & 0xffff,
+        ntohl(iphdr->src.addr[0]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (src)\n",
+        (ntohl(iphdr->src.addr[1]) >> 16) & 0xffff,
+        ntohl(iphdr->src.addr[1]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (src)\n",
+        (ntohl(iphdr->src.addr[2]) >> 16) & 0xffff,
+        ntohl(iphdr->src.addr[2]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (src)\n",
+        (ntohl(iphdr->src.addr[3]) >> 16) & 0xffff,
+        ntohl(iphdr->src.addr[3]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (dest)\n",
+        (ntohl(iphdr->dest.addr[0]) >> 16) & 0xffff,
+        ntohl(iphdr->dest.addr[0]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (dest)\n",
+        (ntohl(iphdr->dest.addr[1]) >> 16) & 0xffff,
+        ntohl(iphdr->dest.addr[1]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (dest)\n",
+        (ntohl(iphdr->dest.addr[2]) >> 16) & 0xffff,
+        ntohl(iphdr->dest.addr[2]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (dest)\n",
+        (ntohl(iphdr->dest.addr[3]) >> 16) & 0xffff,
+        ntohl(iphdr->dest.addr[3]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+}
+#endif /* IP_DEBUG */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv6/ip6_addr.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv6/ip6_addr.c
new file mode 100644
index 0000000..2da6cea
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/ipv6/ip6_addr.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+#include "lwip/ip_addr.h"
+#include "lwip/inet.h"
+
+u8_t
+ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2,
+                struct ip_addr *mask)
+{
+  return((addr1->addr[0] & mask->addr[0]) == (addr2->addr[0] & mask->addr[0]) &&
+         (addr1->addr[1] & mask->addr[1]) == (addr2->addr[1] & mask->addr[1]) &&
+         (addr1->addr[2] & mask->addr[2]) == (addr2->addr[2] & mask->addr[2]) &&
+         (addr1->addr[3] & mask->addr[3]) == (addr2->addr[3] & mask->addr[3]));
+        
+}
+
+u8_t
+ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2)
+{
+  return(addr1->addr[0] == addr2->addr[0] &&
+         addr1->addr[1] == addr2->addr[1] &&
+         addr1->addr[2] == addr2->addr[2] &&
+         addr1->addr[3] == addr2->addr[3]);
+}
+
+void
+ip_addr_set(struct ip_addr *dest, struct ip_addr *src)
+{
+  SMEMCPY(dest, src, sizeof(struct ip_addr));
+  /*  dest->addr[0] = src->addr[0];
+  dest->addr[1] = src->addr[1];
+  dest->addr[2] = src->addr[2];
+  dest->addr[3] = src->addr[3];*/
+}
+
+u8_t
+ip_addr_isany(struct ip_addr *addr)
+{
+  if (addr == NULL) return 1;
+  return((addr->addr[0] | addr->addr[1] | addr->addr[2] | addr->addr[3]) == 0);
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/mem.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/mem.c
new file mode 100644
index 0000000..7928e3b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/mem.c
@@ -0,0 +1,633 @@
+/**
+ * @file
+ * Dynamic memory manager
+ *
+ * This is a lightweight replacement for the standard C library malloc().
+ *
+ * If you want to use the standard C library malloc() instead, define
+ * MEM_LIBC_MALLOC to 1 in your lwipopts.h
+ *
+ * To let mem_malloc() use pools (prevents fragmentation and is much faster than
+ * a heap but might waste some memory), define MEM_USE_POOLS to 1, define
+ * MEM_USE_CUSTOM_POOLS to 1 and create a file "lwippools.h" that includes a list
+ * of pools like this (more pools can be added between _START and _END):
+ *
+ * Define three pools with sizes 256, 512, and 1512 bytes
+ * LWIP_MALLOC_MEMPOOL_START
+ * LWIP_MALLOC_MEMPOOL(20, 256)
+ * LWIP_MALLOC_MEMPOOL(10, 512)
+ * LWIP_MALLOC_MEMPOOL(5, 1512)
+ * LWIP_MALLOC_MEMPOOL_END
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *         Simon Goldschmidt
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if !MEM_LIBC_MALLOC /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+
+#include 
+
+#if MEM_USE_POOLS
+/* lwIP head implemented with different sized pools */
+
+/**
+ * Allocate memory: determine the smallest pool that is big enough
+ * to contain an element of 'size' and get an element from that pool.
+ *
+ * @param size the size in bytes of the memory needed
+ * @return a pointer to the allocated memory or NULL if the pool is empty
+ */
+void *
+mem_malloc(mem_size_t size)
+{
+  struct memp_malloc_helper *element;
+  memp_t poolnr;
+  mem_size_t required_size = size + sizeof(struct memp_malloc_helper);
+
+  for (poolnr = MEMP_POOL_FIRST; poolnr <= MEMP_POOL_LAST; poolnr++) {
+#if MEM_USE_POOLS_TRY_BIGGER_POOL
+again:
+#endif /* MEM_USE_POOLS_TRY_BIGGER_POOL */
+    /* is this pool big enough to hold an element of the required size
+       plus a struct memp_malloc_helper that saves the pool this element came from? */
+    if (required_size <= memp_sizes[poolnr]) {
+      break;
+    }
+  }
+  if (poolnr > MEMP_POOL_LAST) {
+    LWIP_ASSERT("mem_malloc(): no pool is that big!", 0);
+    return NULL;
+  }
+  element = (struct memp_malloc_helper*)memp_malloc(poolnr);
+  if (element == NULL) {
+    /* No need to DEBUGF or ASSERT: This error is already
+       taken care of in memp.c */
+#if MEM_USE_POOLS_TRY_BIGGER_POOL
+    /** Try a bigger pool if this one is empty! */
+    if (poolnr < MEMP_POOL_LAST) {
+      poolnr++;
+      goto again;
+    }
+#endif /* MEM_USE_POOLS_TRY_BIGGER_POOL */
+    return NULL;
+  }
+
+  /* save the pool number this element came from */
+  element->poolnr = poolnr;
+  /* and return a pointer to the memory directly after the struct memp_malloc_helper */
+  element++;
+
+  return element;
+}
+
+/**
+ * Free memory previously allocated by mem_malloc. Loads the pool number
+ * and calls memp_free with that pool number to put the element back into
+ * its pool
+ *
+ * @param rmem the memory element to free
+ */
+void
+mem_free(void *rmem)
+{
+  struct memp_malloc_helper *hmem = (struct memp_malloc_helper*)rmem;
+
+  LWIP_ASSERT("rmem != NULL", (rmem != NULL));
+  LWIP_ASSERT("rmem == MEM_ALIGN(rmem)", (rmem == LWIP_MEM_ALIGN(rmem)));
+
+  /* get the original struct memp_malloc_helper */
+  hmem--;
+
+  LWIP_ASSERT("hmem != NULL", (hmem != NULL));
+  LWIP_ASSERT("hmem == MEM_ALIGN(hmem)", (hmem == LWIP_MEM_ALIGN(hmem)));
+  LWIP_ASSERT("hmem->poolnr < MEMP_MAX", (hmem->poolnr < MEMP_MAX));
+
+  /* and put it in the pool we saved earlier */
+  memp_free(hmem->poolnr, hmem);
+}
+
+#else /* MEM_USE_POOLS */
+/* lwIP replacement for your libc malloc() */
+
+/**
+ * The heap is made up as a list of structs of this type.
+ * This does not have to be aligned since for getting its size,
+ * we only use the macro SIZEOF_STRUCT_MEM, which automatically alignes.
+ */
+struct mem {
+  /** index (-> ram[next]) of the next struct */
+  mem_size_t next;
+  /** index (-> ram[next]) of the next struct */
+  mem_size_t prev;
+  /** 1: this area is used; 0: this area is unused */
+  u8_t used;
+};
+
+/** All allocated blocks will be MIN_SIZE bytes big, at least!
+ * MIN_SIZE can be overridden to suit your needs. Smaller values save space,
+ * larger values could prevent too small blocks to fragment the RAM too much. */
+#ifndef MIN_SIZE
+#define MIN_SIZE             12
+#endif /* MIN_SIZE */
+/* some alignment macros: we define them here for better source code layout */
+#define MIN_SIZE_ALIGNED     LWIP_MEM_ALIGN_SIZE(MIN_SIZE)
+#define SIZEOF_STRUCT_MEM    LWIP_MEM_ALIGN_SIZE(sizeof(struct mem))
+#define MEM_SIZE_ALIGNED     LWIP_MEM_ALIGN_SIZE(MEM_SIZE)
+
+/** the heap. we need one struct mem at the end and some room for alignment */
+static u8_t ram_heap[MEM_SIZE_ALIGNED + (2*SIZEOF_STRUCT_MEM) + MEM_ALIGNMENT];
+/** pointer to the heap (ram_heap): for alignment, ram is now a pointer instead of an array */
+static u8_t *ram;
+/** the last entry, always unused! */
+static struct mem *ram_end;
+/** pointer to the lowest free block, this is used for faster search */
+static struct mem *lfree;
+
+/** concurrent access protection */
+static sys_sem_t mem_sem;
+
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+
+static volatile u8_t mem_free_count;
+
+/* Allow mem_free from other (e.g. interrupt) context */
+#define LWIP_MEM_FREE_DECL_PROTECT()  SYS_ARCH_DECL_PROTECT(lev_free)
+#define LWIP_MEM_FREE_PROTECT()       SYS_ARCH_PROTECT(lev_free)
+#define LWIP_MEM_FREE_UNPROTECT()     SYS_ARCH_UNPROTECT(lev_free)
+#define LWIP_MEM_ALLOC_DECL_PROTECT() SYS_ARCH_DECL_PROTECT(lev_alloc)
+#define LWIP_MEM_ALLOC_PROTECT()      SYS_ARCH_PROTECT(lev_alloc)
+#define LWIP_MEM_ALLOC_UNPROTECT()    SYS_ARCH_UNPROTECT(lev_alloc)
+
+#else /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+
+/* Protect the heap only by using a semaphore */
+#define LWIP_MEM_FREE_DECL_PROTECT()
+#define LWIP_MEM_FREE_PROTECT()    sys_arch_sem_wait(mem_sem, 0)
+#define LWIP_MEM_FREE_UNPROTECT()  sys_sem_signal(mem_sem)
+/* mem_malloc is protected using semaphore AND LWIP_MEM_ALLOC_PROTECT */
+#define LWIP_MEM_ALLOC_DECL_PROTECT()
+#define LWIP_MEM_ALLOC_PROTECT()
+#define LWIP_MEM_ALLOC_UNPROTECT()
+
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+
+
+/**
+ * "Plug holes" by combining adjacent empty struct mems.
+ * After this function is through, there should not exist
+ * one empty struct mem pointing to another empty struct mem.
+ *
+ * @param mem this points to a struct mem which just has been freed
+ * @internal this function is only called by mem_free() and mem_realloc()
+ *
+ * This assumes access to the heap is protected by the calling function
+ * already.
+ */
+static void
+plug_holes(struct mem *mem)
+{
+  struct mem *nmem;
+  struct mem *pmem;
+
+  LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram);
+  LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end);
+  LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0);
+
+  /* plug hole forward */
+  LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE_ALIGNED", mem->next <= MEM_SIZE_ALIGNED);
+
+  nmem = (struct mem *)&ram[mem->next];
+  if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) {
+    /* if mem->next is unused and not end of ram, combine mem and mem->next */
+    if (lfree == nmem) {
+      lfree = mem;
+    }
+    mem->next = nmem->next;
+    ((struct mem *)&ram[nmem->next])->prev = (u8_t *)mem - ram;
+  }
+
+  /* plug hole backward */
+  pmem = (struct mem *)&ram[mem->prev];
+  if (pmem != mem && pmem->used == 0) {
+    /* if mem->prev is unused, combine mem and mem->prev */
+    if (lfree == mem) {
+      lfree = pmem;
+    }
+    pmem->next = mem->next;
+    ((struct mem *)&ram[mem->next])->prev = (u8_t *)pmem - ram;
+  }
+}
+
+/**
+ * Zero the heap and initialize start, end and lowest-free
+ */
+void
+mem_init(void)
+{
+  struct mem *mem;
+
+  LWIP_ASSERT("Sanity check alignment",
+    (SIZEOF_STRUCT_MEM & (MEM_ALIGNMENT-1)) == 0);
+
+  /* align the heap */
+  ram = LWIP_MEM_ALIGN(ram_heap);
+  /* initialize the start of the heap */
+  mem = (struct mem *)ram;
+  mem->next = MEM_SIZE_ALIGNED;
+  mem->prev = 0;
+  mem->used = 0;
+  /* initialize the end of the heap */
+  ram_end = (struct mem *)&ram[MEM_SIZE_ALIGNED];
+  ram_end->used = 1;
+  ram_end->next = MEM_SIZE_ALIGNED;
+  ram_end->prev = MEM_SIZE_ALIGNED;
+
+  mem_sem = sys_sem_new(1);
+
+  /* initialize the lowest-free pointer to the start of the heap */
+  lfree = (struct mem *)ram;
+
+  MEM_STATS_AVAIL(avail, MEM_SIZE_ALIGNED);
+}
+
+/**
+ * Put a struct mem back on the heap
+ *
+ * @param rmem is the data portion of a struct mem as returned by a previous
+ *             call to mem_malloc()
+ */
+void
+mem_free(void *rmem)
+{
+  struct mem *mem;
+  LWIP_MEM_FREE_DECL_PROTECT();
+
+  if (rmem == NULL) {
+    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("mem_free(p == NULL) was called.\n"));
+    return;
+  }
+  LWIP_ASSERT("mem_free: sanity check alignment", (((mem_ptr_t)rmem) & (MEM_ALIGNMENT-1)) == 0);
+
+  LWIP_ASSERT("mem_free: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
+    (u8_t *)rmem < (u8_t *)ram_end);
+
+  if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
+    SYS_ARCH_DECL_PROTECT(lev);
+    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory\n"));
+    /* protect mem stats from concurrent access */
+    SYS_ARCH_PROTECT(lev);
+    MEM_STATS_INC(illegal);
+    SYS_ARCH_UNPROTECT(lev);
+    return;
+  }
+  /* protect the heap from concurrent access */
+  LWIP_MEM_FREE_PROTECT();
+  /* Get the corresponding struct mem ... */
+  mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM);
+  /* ... which has to be in a used state ... */
+  LWIP_ASSERT("mem_free: mem->used", mem->used);
+  /* ... and is now unused. */
+  mem->used = 0;
+
+  if (mem < lfree) {
+    /* the newly freed struct is now the lowest */
+    lfree = mem;
+  }
+
+  MEM_STATS_DEC_USED(used, mem->next - ((u8_t *)mem - ram));
+
+  /* finally, see if prev or next are free also */
+  plug_holes(mem);
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+  mem_free_count = 1;
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+  LWIP_MEM_FREE_UNPROTECT();
+}
+
+/**
+ * In contrast to its name, mem_realloc can only shrink memory, not expand it.
+ * Since the only use (for now) is in pbuf_realloc (which also can only shrink),
+ * this shouldn't be a problem!
+ *
+ * @param rmem pointer to memory allocated by mem_malloc the is to be shrinked
+ * @param newsize required size after shrinking (needs to be smaller than or
+ *                equal to the previous size)
+ * @return for compatibility reasons: is always == rmem, at the moment
+ *         or NULL if newsize is > old size, in which case rmem is NOT touched
+ *         or freed!
+ */
+void *
+mem_realloc(void *rmem, mem_size_t newsize)
+{
+  mem_size_t size;
+  mem_size_t ptr, ptr2;
+  struct mem *mem, *mem2;
+  /* use the FREE_PROTECT here: it protects with sem OR SYS_ARCH_PROTECT */
+  LWIP_MEM_FREE_DECL_PROTECT();
+
+  /* Expand the size of the allocated memory region so that we can
+     adjust for alignment. */
+  newsize = LWIP_MEM_ALIGN_SIZE(newsize);
+
+  if(newsize < MIN_SIZE_ALIGNED) {
+    /* every data block must be at least MIN_SIZE_ALIGNED long */
+    newsize = MIN_SIZE_ALIGNED;
+  }
+
+  if (newsize > MEM_SIZE_ALIGNED) {
+    return NULL;
+  }
+
+  LWIP_ASSERT("mem_realloc: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
+   (u8_t *)rmem < (u8_t *)ram_end);
+
+  if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
+    SYS_ARCH_DECL_PROTECT(lev);
+    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_realloc: illegal memory\n"));
+    /* protect mem stats from concurrent access */
+    SYS_ARCH_PROTECT(lev);
+    MEM_STATS_INC(illegal);
+    SYS_ARCH_UNPROTECT(lev);
+    return rmem;
+  }
+  /* Get the corresponding struct mem ... */
+  mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM);
+  /* ... and its offset pointer */
+  ptr = (u8_t *)mem - ram;
+
+  size = mem->next - ptr - SIZEOF_STRUCT_MEM;
+  LWIP_ASSERT("mem_realloc can only shrink memory", newsize <= size);
+  if (newsize > size) {
+    /* not supported */
+    return NULL;
+  }
+  if (newsize == size) {
+    /* No change in size, simply return */
+    return rmem;
+  }
+
+  /* protect the heap from concurrent access */
+  LWIP_MEM_FREE_PROTECT();
+
+  MEM_STATS_DEC_USED(used, (size - newsize));
+
+  mem2 = (struct mem *)&ram[mem->next];
+  if(mem2->used == 0) {
+    /* The next struct is unused, we can simply move it at little */
+    mem_size_t next;
+    /* remember the old next pointer */
+    next = mem2->next;
+    /* create new struct mem which is moved directly after the shrinked mem */
+    ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize;
+    if (lfree == mem2) {
+      lfree = (struct mem *)&ram[ptr2];
+    }
+    mem2 = (struct mem *)&ram[ptr2];
+    mem2->used = 0;
+    /* restore the next pointer */
+    mem2->next = next;
+    /* link it back to mem */
+    mem2->prev = ptr;
+    /* link mem to it */
+    mem->next = ptr2;
+    /* last thing to restore linked list: as we have moved mem2,
+     * let 'mem2->next->prev' point to mem2 again. but only if mem2->next is not
+     * the end of the heap */
+    if (mem2->next != MEM_SIZE_ALIGNED) {
+      ((struct mem *)&ram[mem2->next])->prev = ptr2;
+    }
+    /* no need to plug holes, we've already done that */
+  } else if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED <= size) {
+    /* Next struct is used but there's room for another struct mem with
+     * at least MIN_SIZE_ALIGNED of data.
+     * Old size ('size') must be big enough to contain at least 'newsize' plus a struct mem
+     * ('SIZEOF_STRUCT_MEM') with some data ('MIN_SIZE_ALIGNED').
+     * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty
+     *       region that couldn't hold data, but when mem->next gets freed,
+     *       the 2 regions would be combined, resulting in more free memory */
+    ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize;
+    mem2 = (struct mem *)&ram[ptr2];
+    if (mem2 < lfree) {
+      lfree = mem2;
+    }
+    mem2->used = 0;
+    mem2->next = mem->next;
+    mem2->prev = ptr;
+    mem->next = ptr2;
+    if (mem2->next != MEM_SIZE_ALIGNED) {
+      ((struct mem *)&ram[mem2->next])->prev = ptr2;
+    }
+    /* the original mem->next is used, so no need to plug holes! */
+  }
+  /* else {
+    next struct mem is used but size between mem and mem2 is not big enough
+    to create another struct mem
+    -> don't do anyhting. 
+    -> the remaining space stays unused since it is too small
+  } */
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+  mem_free_count = 1;
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+  LWIP_MEM_FREE_UNPROTECT();
+  return rmem;
+}
+
+/**
+ * Adam's mem_malloc() plus solution for bug #17922
+ * Allocate a block of memory with a minimum of 'size' bytes.
+ *
+ * @param size is the minimum size of the requested block in bytes.
+ * @return pointer to allocated memory or NULL if no free memory was found.
+ *
+ * Note that the returned value will always be aligned (as defined by MEM_ALIGNMENT).
+ */
+void *
+mem_malloc(mem_size_t size)
+{
+  mem_size_t ptr, ptr2;
+  struct mem *mem, *mem2;
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+  u8_t local_mem_free_count = 0;
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+  LWIP_MEM_ALLOC_DECL_PROTECT();
+
+  if (size == 0) {
+    return NULL;
+  }
+
+  /* Expand the size of the allocated memory region so that we can
+     adjust for alignment. */
+  size = LWIP_MEM_ALIGN_SIZE(size);
+
+  if(size < MIN_SIZE_ALIGNED) {
+    /* every data block must be at least MIN_SIZE_ALIGNED long */
+    size = MIN_SIZE_ALIGNED;
+  }
+
+  if (size > MEM_SIZE_ALIGNED) {
+    return NULL;
+  }
+
+  /* protect the heap from concurrent access */
+  sys_arch_sem_wait(mem_sem, 0);
+  LWIP_MEM_ALLOC_PROTECT();
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+  /* run as long as a mem_free disturbed mem_malloc */
+  do {
+    local_mem_free_count = 0;
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+
+    /* Scan through the heap searching for a free block that is big enough,
+     * beginning with the lowest free block.
+     */
+    for (ptr = (u8_t *)lfree - ram; ptr < MEM_SIZE_ALIGNED - size;
+         ptr = ((struct mem *)&ram[ptr])->next) {
+      mem = (struct mem *)&ram[ptr];
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+      mem_free_count = 0;
+      LWIP_MEM_ALLOC_UNPROTECT();
+      /* allow mem_free to run */
+      LWIP_MEM_ALLOC_PROTECT();
+      if (mem_free_count != 0) {
+        local_mem_free_count = mem_free_count;
+      }
+      mem_free_count = 0;
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+
+      if ((!mem->used) &&
+          (mem->next - (ptr + SIZEOF_STRUCT_MEM)) >= size) {
+        /* mem is not used and at least perfect fit is possible:
+         * mem->next - (ptr + SIZEOF_STRUCT_MEM) gives us the 'user data size' of mem */
+
+        if (mem->next - (ptr + SIZEOF_STRUCT_MEM) >= (size + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED)) {
+          /* (in addition to the above, we test if another struct mem (SIZEOF_STRUCT_MEM) containing
+           * at least MIN_SIZE_ALIGNED of data also fits in the 'user data space' of 'mem')
+           * -> split large block, create empty remainder,
+           * remainder must be large enough to contain MIN_SIZE_ALIGNED data: if
+           * mem->next - (ptr + (2*SIZEOF_STRUCT_MEM)) == size,
+           * struct mem would fit in but no data between mem2 and mem2->next
+           * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty
+           *       region that couldn't hold data, but when mem->next gets freed,
+           *       the 2 regions would be combined, resulting in more free memory
+           */
+          ptr2 = ptr + SIZEOF_STRUCT_MEM + size;
+          /* create mem2 struct */
+          mem2 = (struct mem *)&ram[ptr2];
+          mem2->used = 0;
+          mem2->next = mem->next;
+          mem2->prev = ptr;
+          /* and insert it between mem and mem->next */
+          mem->next = ptr2;
+          mem->used = 1;
+
+          if (mem2->next != MEM_SIZE_ALIGNED) {
+            ((struct mem *)&ram[mem2->next])->prev = ptr2;
+          }
+          MEM_STATS_INC_USED(used, (size + SIZEOF_STRUCT_MEM));
+        } else {
+          /* (a mem2 struct does no fit into the user data space of mem and mem->next will always
+           * be used at this point: if not we have 2 unused structs in a row, plug_holes should have
+           * take care of this).
+           * -> near fit or excact fit: do not split, no mem2 creation
+           * also can't move mem->next directly behind mem, since mem->next
+           * will always be used at this point!
+           */
+          mem->used = 1;
+          MEM_STATS_INC_USED(used, mem->next - ((u8_t *)mem - ram));
+        }
+
+        if (mem == lfree) {
+          /* Find next free block after mem and update lowest free pointer */
+          while (lfree->used && lfree != ram_end) {
+            LWIP_MEM_ALLOC_UNPROTECT();
+            /* prevent high interrupt latency... */
+            LWIP_MEM_ALLOC_PROTECT();
+            lfree = (struct mem *)&ram[lfree->next];
+          }
+          LWIP_ASSERT("mem_malloc: !lfree->used", ((lfree == ram_end) || (!lfree->used)));
+        }
+        LWIP_MEM_ALLOC_UNPROTECT();
+        sys_sem_signal(mem_sem);
+        LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.",
+         (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end);
+        LWIP_ASSERT("mem_malloc: allocated memory properly aligned.",
+         ((mem_ptr_t)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0);
+        LWIP_ASSERT("mem_malloc: sanity check alignment",
+          (((mem_ptr_t)mem) & (MEM_ALIGNMENT-1)) == 0);
+
+        return (u8_t *)mem + SIZEOF_STRUCT_MEM;
+      }
+    }
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+    /* if we got interrupted by a mem_free, try again */
+  } while(local_mem_free_count != 0);
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+  LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size));
+  MEM_STATS_INC(err);
+  LWIP_MEM_ALLOC_UNPROTECT();
+  sys_sem_signal(mem_sem);
+  return NULL;
+}
+
+#endif /* MEM_USE_POOLS */
+/**
+ * Contiguously allocates enough space for count objects that are size bytes
+ * of memory each and returns a pointer to the allocated memory.
+ *
+ * The allocated memory is filled with bytes of value zero.
+ *
+ * @param count number of objects to allocate
+ * @param size size of the objects to allocate
+ * @return pointer to allocated memory / NULL pointer if there is an error
+ */
+void *mem_calloc(mem_size_t count, mem_size_t size)
+{
+  void *p;
+
+  /* allocate 'count' objects of size 'size' */
+  p = mem_malloc(count * size);
+  if (p) {
+    /* zero the memory */
+    memset(p, 0, count * size);
+  }
+  return p;
+}
+
+#endif /* !MEM_LIBC_MALLOC */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/memp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/memp.c
new file mode 100644
index 0000000..dea1815
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/memp.c
@@ -0,0 +1,386 @@
+/**
+ * @file
+ * Dynamic pool memory manager
+ *
+ * lwIP has dedicated pools for many structures (netconn, protocol control blocks,
+ * packet buffers, ...). All these pools are managed here.
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/memp.h"
+#include "lwip/pbuf.h"
+#include "lwip/udp.h"
+#include "lwip/raw.h"
+#include "lwip/tcp.h"
+#include "lwip/igmp.h"
+#include "lwip/api.h"
+#include "lwip/api_msg.h"
+#include "lwip/tcpip.h"
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+#include "netif/etharp.h"
+#include "lwip/ip_frag.h"
+
+#include 
+
+#if !MEMP_MEM_MALLOC /* don't build if not configured for use in lwipopts.h */
+
+struct memp {
+  struct memp *next;
+#if MEMP_OVERFLOW_CHECK
+  const char *file;
+  int line;
+#endif /* MEMP_OVERFLOW_CHECK */
+};
+
+#if MEMP_OVERFLOW_CHECK
+/* if MEMP_OVERFLOW_CHECK is turned on, we reserve some bytes at the beginning
+ * and at the end of each element, initialize them as 0xcd and check
+ * them later. */
+/* If MEMP_OVERFLOW_CHECK is >= 2, on every call to memp_malloc or memp_free,
+ * every single element in each pool is checked!
+ * This is VERY SLOW but also very helpful. */
+/* MEMP_SANITY_REGION_BEFORE and MEMP_SANITY_REGION_AFTER can be overridden in
+ * lwipopts.h to change the amount reserved for checking. */
+#ifndef MEMP_SANITY_REGION_BEFORE
+#define MEMP_SANITY_REGION_BEFORE  16
+#endif /* MEMP_SANITY_REGION_BEFORE*/
+#if MEMP_SANITY_REGION_BEFORE > 0
+#define MEMP_SANITY_REGION_BEFORE_ALIGNED    LWIP_MEM_ALIGN_SIZE(MEMP_SANITY_REGION_BEFORE)
+#else
+#define MEMP_SANITY_REGION_BEFORE_ALIGNED    0
+#endif /* MEMP_SANITY_REGION_BEFORE*/
+#ifndef MEMP_SANITY_REGION_AFTER
+#define MEMP_SANITY_REGION_AFTER   16
+#endif /* MEMP_SANITY_REGION_AFTER*/
+#if MEMP_SANITY_REGION_AFTER > 0
+#define MEMP_SANITY_REGION_AFTER_ALIGNED     LWIP_MEM_ALIGN_SIZE(MEMP_SANITY_REGION_AFTER)
+#else
+#define MEMP_SANITY_REGION_AFTER_ALIGNED     0
+#endif /* MEMP_SANITY_REGION_AFTER*/
+
+/* MEMP_SIZE: save space for struct memp and for sanity check */
+#define MEMP_SIZE          (LWIP_MEM_ALIGN_SIZE(sizeof(struct memp)) + MEMP_SANITY_REGION_BEFORE_ALIGNED)
+#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x) + MEMP_SANITY_REGION_AFTER_ALIGNED)
+
+#else /* MEMP_OVERFLOW_CHECK */
+
+/* No sanity checks
+ * We don't need to preserve the struct memp while not allocated, so we
+ * can save a little space and set MEMP_SIZE to 0.
+ */
+#define MEMP_SIZE           0
+#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x))
+
+#endif /* MEMP_OVERFLOW_CHECK */
+
+/** This array holds the first free element of each pool.
+ *  Elements form a linked list. */
+static struct memp *memp_tab[MEMP_MAX];
+
+#else /* MEMP_MEM_MALLOC */
+
+#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x))
+
+#endif /* MEMP_MEM_MALLOC */
+
+/** This array holds the element sizes of each pool. */
+#if !MEM_USE_POOLS && !MEMP_MEM_MALLOC
+static
+#endif
+const u16_t memp_sizes[MEMP_MAX] = {
+#define LWIP_MEMPOOL(name,num,size,desc)  LWIP_MEM_ALIGN_SIZE(size),
+#include "lwip/memp_std.h"
+};
+
+#if !MEMP_MEM_MALLOC /* don't build if not configured for use in lwipopts.h */
+
+/** This array holds the number of elements in each pool. */
+static const u16_t memp_num[MEMP_MAX] = {
+#define LWIP_MEMPOOL(name,num,size,desc)  (num),
+#include "lwip/memp_std.h"
+};
+
+/** This array holds a textual description of each pool. */
+#ifdef LWIP_DEBUG
+static const char *memp_desc[MEMP_MAX] = {
+#define LWIP_MEMPOOL(name,num,size,desc)  (desc),
+#include "lwip/memp_std.h"
+};
+#endif /* LWIP_DEBUG */
+
+/** This is the actual memory used by the pools. */
+static u8_t memp_memory[MEM_ALIGNMENT - 1 
+#define LWIP_MEMPOOL(name,num,size,desc) + ( (num) * (MEMP_SIZE + MEMP_ALIGN_SIZE(size) ) )
+#include "lwip/memp_std.h"
+];
+
+#if MEMP_SANITY_CHECK
+/**
+ * Check that memp-lists don't form a circle
+ */
+static int
+memp_sanity(void)
+{
+  s16_t i, c;
+  struct memp *m, *n;
+
+  for (i = 0; i < MEMP_MAX; i++) {
+    for (m = memp_tab[i]; m != NULL; m = m->next) {
+      c = 1;
+      for (n = memp_tab[i]; n != NULL; n = n->next) {
+        if (n == m && --c < 0) {
+          return 0;
+        }
+      }
+    }
+  }
+  return 1;
+}
+#endif /* MEMP_SANITY_CHECK*/
+#if MEMP_OVERFLOW_CHECK
+/**
+ * Check if a memp element was victim of an overflow
+ * (e.g. the restricted area after it has been altered)
+ *
+ * @param p the memp element to check
+ * @param memp_size the element size of the pool p comes from
+ */
+static void
+memp_overflow_check_element(struct memp *p, u16_t memp_size)
+{
+  u16_t k;
+  u8_t *m;
+#if MEMP_SANITY_REGION_BEFORE_ALIGNED > 0
+  m = (u8_t*)p + MEMP_SIZE - MEMP_SANITY_REGION_BEFORE_ALIGNED;
+  for (k = 0; k < MEMP_SANITY_REGION_BEFORE_ALIGNED; k++) {
+    if (m[k] != 0xcd) {
+      LWIP_ASSERT("detected memp underflow!", 0);
+    }
+  }
+#endif
+#if MEMP_SANITY_REGION_AFTER_ALIGNED > 0
+  m = (u8_t*)p + MEMP_SIZE + memp_size;
+  for (k = 0; k < MEMP_SANITY_REGION_AFTER_ALIGNED; k++) {
+    if (m[k] != 0xcd) {
+      LWIP_ASSERT("detected memp overflow!", 0);
+    }
+  }
+#endif
+}
+
+/**
+ * Do an overflow check for all elements in every pool.
+ *
+ * @see memp_overflow_check_element for a description of the check
+ */
+static void
+memp_overflow_check_all(void)
+{
+  u16_t i, j;
+  struct memp *p;
+
+  p = LWIP_MEM_ALIGN(memp_memory);
+  for (i = 0; i < MEMP_MAX; ++i) {
+    p = p;
+    for (j = 0; j < memp_num[i]; ++j) {
+      memp_overflow_check_element(p, memp_sizes[i]);
+      p = (struct memp*)((u8_t*)p + MEMP_SIZE + memp_sizes[i] + MEMP_SANITY_REGION_AFTER_ALIGNED);
+    }
+  }
+}
+
+/**
+ * Initialize the restricted areas of all memp elements in every pool.
+ */
+static void
+memp_overflow_init(void)
+{
+  u16_t i, j;
+  struct memp *p;
+  u8_t *m;
+
+  p = LWIP_MEM_ALIGN(memp_memory);
+  for (i = 0; i < MEMP_MAX; ++i) {
+    p = p;
+    for (j = 0; j < memp_num[i]; ++j) {
+#if MEMP_SANITY_REGION_BEFORE_ALIGNED > 0
+      m = (u8_t*)p + MEMP_SIZE - MEMP_SANITY_REGION_BEFORE_ALIGNED;
+      memset(m, 0xcd, MEMP_SANITY_REGION_BEFORE_ALIGNED);
+#endif
+#if MEMP_SANITY_REGION_AFTER_ALIGNED > 0
+      m = (u8_t*)p + MEMP_SIZE + memp_sizes[i];
+      memset(m, 0xcd, MEMP_SANITY_REGION_AFTER_ALIGNED);
+#endif
+      p = (struct memp*)((u8_t*)p + MEMP_SIZE + memp_sizes[i] + MEMP_SANITY_REGION_AFTER_ALIGNED);
+    }
+  }
+}
+#endif /* MEMP_OVERFLOW_CHECK */
+
+/**
+ * Initialize this module.
+ * 
+ * Carves out memp_memory into linked lists for each pool-type.
+ */
+void
+memp_init(void)
+{
+  struct memp *memp;
+  u16_t i, j;
+
+  for (i = 0; i < MEMP_MAX; ++i) {
+    MEMP_STATS_AVAIL(used, i, 0);
+    MEMP_STATS_AVAIL(max, i, 0);
+    MEMP_STATS_AVAIL(err, i, 0);
+    MEMP_STATS_AVAIL(avail, i, memp_num[i]);
+  }
+
+  memp = LWIP_MEM_ALIGN(memp_memory);
+  /* for every pool: */
+  for (i = 0; i < MEMP_MAX; ++i) {
+    memp_tab[i] = NULL;
+    /* create a linked list of memp elements */
+    for (j = 0; j < memp_num[i]; ++j) {
+      memp->next = memp_tab[i];
+      memp_tab[i] = memp;
+      memp = (struct memp *)((u8_t *)memp + MEMP_SIZE + memp_sizes[i]
+#if MEMP_OVERFLOW_CHECK
+        + MEMP_SANITY_REGION_AFTER_ALIGNED
+#endif
+      );
+    }
+  }
+#if MEMP_OVERFLOW_CHECK
+  memp_overflow_init();
+  /* check everything a first time to see if it worked */
+  memp_overflow_check_all();
+#endif /* MEMP_OVERFLOW_CHECK */
+}
+
+/**
+ * Get an element from a specific pool.
+ *
+ * @param type the pool to get an element from
+ *
+ * the debug version has two more parameters:
+ * @param file file name calling this function
+ * @param line number of line where this function is called
+ *
+ * @return a pointer to the allocated memory or a NULL pointer on error
+ */
+void *
+#if !MEMP_OVERFLOW_CHECK
+memp_malloc(memp_t type)
+#else
+memp_malloc_fn(memp_t type, const char* file, const int line)
+#endif
+{
+  struct memp *memp;
+  SYS_ARCH_DECL_PROTECT(old_level);
+ 
+  LWIP_ERROR("memp_malloc: type < MEMP_MAX", (type < MEMP_MAX), return NULL;);
+
+  SYS_ARCH_PROTECT(old_level);
+#if MEMP_OVERFLOW_CHECK >= 2
+  memp_overflow_check_all();
+#endif /* MEMP_OVERFLOW_CHECK >= 2 */
+
+  memp = memp_tab[type];
+  
+  if (memp != NULL) {
+    memp_tab[type] = memp->next;
+#if MEMP_OVERFLOW_CHECK
+    memp->next = NULL;
+    memp->file = file;
+    memp->line = line;
+#endif /* MEMP_OVERFLOW_CHECK */
+    MEMP_STATS_INC_USED(used, type);
+    LWIP_ASSERT("memp_malloc: memp properly aligned",
+                ((mem_ptr_t)memp % MEM_ALIGNMENT) == 0);
+    memp = (struct memp*)((u8_t*)memp + MEMP_SIZE);
+  } else {
+    LWIP_DEBUGF(MEMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("memp_malloc: out of memory in pool %s\n", memp_desc[type]));
+    MEMP_STATS_INC(err, type);
+  }
+
+  SYS_ARCH_UNPROTECT(old_level);
+
+  return memp;
+}
+
+/**
+ * Put an element back into its pool.
+ *
+ * @param type the pool where to put mem
+ * @param mem the memp element to free
+ */
+void
+memp_free(memp_t type, void *mem)
+{
+  struct memp *memp;
+  SYS_ARCH_DECL_PROTECT(old_level);
+
+  if (mem == NULL) {
+    return;
+  }
+  LWIP_ASSERT("memp_free: mem properly aligned",
+                ((mem_ptr_t)mem % MEM_ALIGNMENT) == 0);
+
+  memp = (struct memp *)((u8_t*)mem - MEMP_SIZE);
+
+  SYS_ARCH_PROTECT(old_level);
+#if MEMP_OVERFLOW_CHECK
+#if MEMP_OVERFLOW_CHECK >= 2
+  memp_overflow_check_all();
+#else
+  memp_overflow_check_element(memp, memp_sizes[type]);
+#endif /* MEMP_OVERFLOW_CHECK >= 2 */
+#endif /* MEMP_OVERFLOW_CHECK */
+
+  MEMP_STATS_DEC(used, type); 
+  
+  memp->next = memp_tab[type]; 
+  memp_tab[type] = memp;
+
+#if MEMP_SANITY_CHECK
+  LWIP_ASSERT("memp sanity", memp_sanity());
+#endif /* MEMP_SANITY_CHECK */
+
+  SYS_ARCH_UNPROTECT(old_level);
+}
+
+#endif /* MEMP_MEM_MALLOC */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/netif.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/netif.c
new file mode 100644
index 0000000..b52cd02
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/netif.c
@@ -0,0 +1,681 @@
+/**
+ * @file
+ * lwIP network interface abstraction
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/tcp.h"
+#include "lwip/snmp.h"
+#include "lwip/igmp.h"
+#include "netif/etharp.h"
+#if ENABLE_LOOPBACK
+#include "lwip/sys.h"
+#if LWIP_NETIF_LOOPBACK_MULTITHREADING
+#include "lwip/tcpip.h"
+#endif /* LWIP_NETIF_LOOPBACK_MULTITHREADING */
+#endif /* ENABLE_LOOPBACK */
+
+#if LWIP_AUTOIP
+#include "lwip/autoip.h"
+#endif /* LWIP_AUTOIP */
+#if LWIP_DHCP
+#include "lwip/dhcp.h"
+#endif /* LWIP_DHCP */
+
+#if LWIP_NETIF_STATUS_CALLBACK
+#define NETIF_STATUS_CALLBACK(n) { if (n->status_callback) (n->status_callback)(n); }
+#else
+#define NETIF_STATUS_CALLBACK(n) { /* NOP */ }
+#endif /* LWIP_NETIF_STATUS_CALLBACK */ 
+
+#if LWIP_NETIF_LINK_CALLBACK
+#define NETIF_LINK_CALLBACK(n) { if (n->link_callback) (n->link_callback)(n); }
+#else
+#define NETIF_LINK_CALLBACK(n) { /* NOP */ }
+#endif /* LWIP_NETIF_LINK_CALLBACK */ 
+
+struct netif *netif_list;
+struct netif *netif_default;
+
+/**
+ * Add a network interface to the list of lwIP netifs.
+ *
+ * @param netif a pre-allocated netif structure
+ * @param ipaddr IP address for the new netif
+ * @param netmask network mask for the new netif
+ * @param gw default gateway IP address for the new netif
+ * @param state opaque data passed to the new netif
+ * @param init callback function that initializes the interface
+ * @param input callback function that is called to pass
+ * ingress packets up in the protocol layer stack.
+ *
+ * @return netif, or NULL if failed.
+ */
+struct netif *
+netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
+  struct ip_addr *gw,
+  void *state,
+  err_t (* init)(struct netif *netif),
+  err_t (* input)(struct pbuf *p, struct netif *netif))
+{
+  static u8_t netifnum = 0;
+
+  /* reset new interface configuration state */
+  netif->ip_addr.addr = 0;
+  netif->netmask.addr = 0;
+  netif->gw.addr = 0;
+  netif->flags = 0;
+#if LWIP_DHCP
+  /* netif not under DHCP control by default */
+  netif->dhcp = NULL;
+#endif /* LWIP_DHCP */
+#if LWIP_AUTOIP
+  /* netif not under AutoIP control by default */
+  netif->autoip = NULL;
+#endif /* LWIP_AUTOIP */
+#if LWIP_NETIF_STATUS_CALLBACK
+  netif->status_callback = NULL;
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+#if LWIP_NETIF_LINK_CALLBACK
+  netif->link_callback = NULL;
+#endif /* LWIP_NETIF_LINK_CALLBACK */
+#if LWIP_IGMP
+  netif->igmp_mac_filter = NULL;
+#endif /* LWIP_IGMP */
+#if ENABLE_LOOPBACK
+  netif->loop_first = NULL;
+  netif->loop_last = NULL;
+#endif /* ENABLE_LOOPBACK */
+
+  /* remember netif specific state information data */
+  netif->state = state;
+  netif->num = netifnum++;
+  netif->input = input;
+#if LWIP_NETIF_HWADDRHINT
+  netif->addr_hint = NULL;
+#endif /* LWIP_NETIF_HWADDRHINT*/
+#if ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS
+  netif->loop_cnt_current = 0;
+#endif /* ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS */
+
+  netif_set_addr(netif, ipaddr, netmask, gw);
+
+  /* call user specified initialization function for netif */
+  if (init(netif) != ERR_OK) {
+    return NULL;
+  }
+
+  /* add this netif to the list */
+  netif->next = netif_list;
+  netif_list = netif;
+  snmp_inc_iflist();
+
+#if LWIP_IGMP
+  /* start IGMP processing */
+  if (netif->flags & NETIF_FLAG_IGMP) {
+    igmp_start( netif);
+  }
+#endif /* LWIP_IGMP */
+
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP addr ",
+    netif->name[0], netif->name[1]));
+  ip_addr_debug_print(NETIF_DEBUG, ipaddr);
+  LWIP_DEBUGF(NETIF_DEBUG, (" netmask "));
+  ip_addr_debug_print(NETIF_DEBUG, netmask);
+  LWIP_DEBUGF(NETIF_DEBUG, (" gw "));
+  ip_addr_debug_print(NETIF_DEBUG, gw);
+  LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
+  return netif;
+}
+
+/**
+ * Change IP address configuration for a network interface (including netmask
+ * and default gateway).
+ *
+ * @param netif the network interface to change
+ * @param ipaddr the new IP address
+ * @param netmask the new netmask
+ * @param gw the new default gateway
+ */
+void
+netif_set_addr(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
+    struct ip_addr *gw)
+{
+  netif_set_ipaddr(netif, ipaddr);
+  netif_set_netmask(netif, netmask);
+  netif_set_gw(netif, gw);
+}
+
+/**
+ * Remove a network interface from the list of lwIP netifs.
+ *
+ * @param netif the network interface to remove
+ */
+void netif_remove(struct netif * netif)
+{
+  if ( netif == NULL ) return;
+
+#if LWIP_IGMP
+  /* stop IGMP processing */
+  if (netif->flags & NETIF_FLAG_IGMP) {
+    igmp_stop( netif);
+  }
+#endif /* LWIP_IGMP */
+
+  snmp_delete_ipaddridx_tree(netif);
+
+  /*  is it the first netif? */
+  if (netif_list == netif) {
+    netif_list = netif->next;
+    snmp_dec_iflist();
+  }
+  else {
+    /*  look for netif further down the list */
+    struct netif * tmpNetif;
+    for (tmpNetif = netif_list; tmpNetif != NULL; tmpNetif = tmpNetif->next) {
+      if (tmpNetif->next == netif) {
+        tmpNetif->next = netif->next;
+        snmp_dec_iflist();
+        break;
+      }
+    }
+    if (tmpNetif == NULL)
+      return; /*  we didn't find any netif today */
+  }
+  /* this netif is default? */
+  if (netif_default == netif)
+    /* reset default netif */
+    netif_set_default(NULL);
+  LWIP_DEBUGF( NETIF_DEBUG, ("netif_remove: removed netif\n") );
+}
+
+/**
+ * Find a network interface by searching for its name
+ *
+ * @param name the name of the netif (like netif->name) plus concatenated number
+ * in ascii representation (e.g. 'en0')
+ */
+struct netif *
+netif_find(char *name)
+{
+  struct netif *netif;
+  u8_t num;
+
+  if (name == NULL) {
+    return NULL;
+  }
+
+  num = name[2] - '0';
+
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+    if (num == netif->num &&
+       name[0] == netif->name[0] &&
+       name[1] == netif->name[1]) {
+      LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: found %c%c\n", name[0], name[1]));
+      return netif;
+    }
+  }
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: didn't find %c%c\n", name[0], name[1]));
+  return NULL;
+}
+
+/**
+ * Change the IP address of a network interface
+ *
+ * @param netif the network interface to change
+ * @param ipaddr the new IP address
+ *
+ * @note call netif_set_addr() if you also want to change netmask and
+ * default gateway
+ */
+void
+netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr)
+{
+  /* TODO: Handling of obsolete pcbs */
+  /* See:  http://mail.gnu.org/archive/html/lwip-users/2003-03/msg00118.html */
+#if LWIP_TCP
+  struct tcp_pcb *pcb;
+  struct tcp_pcb_listen *lpcb;
+
+  /* address is actually being changed? */
+  if ((ip_addr_cmp(ipaddr, &(netif->ip_addr))) == 0)
+  {
+    /* extern struct tcp_pcb *tcp_active_pcbs; defined by tcp.h */
+    LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: netif address being changed\n"));
+    pcb = tcp_active_pcbs;
+    while (pcb != NULL) {
+      /* PCB bound to current local interface address? */
+      if (ip_addr_cmp(&(pcb->local_ip), &(netif->ip_addr))) {
+        /* this connection must be aborted */
+        struct tcp_pcb *next = pcb->next;
+        LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb));
+        tcp_abort(pcb);
+        pcb = next;
+      } else {
+        pcb = pcb->next;
+      }
+    }
+    for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+      /* PCB bound to current local interface address? */
+      if ((!(ip_addr_isany(&(lpcb->local_ip)))) &&
+          (ip_addr_cmp(&(lpcb->local_ip), &(netif->ip_addr)))) {
+        /* The PCB is listening to the old ipaddr and
+         * is set to listen to the new one instead */
+        ip_addr_set(&(lpcb->local_ip), ipaddr);
+      }
+    }
+  }
+#endif
+  snmp_delete_ipaddridx_tree(netif);
+  snmp_delete_iprteidx_tree(0,netif);
+  /* set new IP address to netif */
+  ip_addr_set(&(netif->ip_addr), ipaddr);
+  snmp_insert_ipaddridx_tree(netif);
+  snmp_insert_iprteidx_tree(0,netif);
+
+  LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: IP address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+    netif->name[0], netif->name[1],
+    ip4_addr1(&netif->ip_addr),
+    ip4_addr2(&netif->ip_addr),
+    ip4_addr3(&netif->ip_addr),
+    ip4_addr4(&netif->ip_addr)));
+}
+
+/**
+ * Change the default gateway for a network interface
+ *
+ * @param netif the network interface to change
+ * @param gw the new default gateway
+ *
+ * @note call netif_set_addr() if you also want to change ip address and netmask
+ */
+void
+netif_set_gw(struct netif *netif, struct ip_addr *gw)
+{
+  ip_addr_set(&(netif->gw), gw);
+  LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: GW address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+    netif->name[0], netif->name[1],
+    ip4_addr1(&netif->gw),
+    ip4_addr2(&netif->gw),
+    ip4_addr3(&netif->gw),
+    ip4_addr4(&netif->gw)));
+}
+
+/**
+ * Change the netmask of a network interface
+ *
+ * @param netif the network interface to change
+ * @param netmask the new netmask
+ *
+ * @note call netif_set_addr() if you also want to change ip address and
+ * default gateway
+ */
+void
+netif_set_netmask(struct netif *netif, struct ip_addr *netmask)
+{
+  snmp_delete_iprteidx_tree(0, netif);
+  /* set new netmask to netif */
+  ip_addr_set(&(netif->netmask), netmask);
+  snmp_insert_iprteidx_tree(0, netif);
+  LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: netmask of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+    netif->name[0], netif->name[1],
+    ip4_addr1(&netif->netmask),
+    ip4_addr2(&netif->netmask),
+    ip4_addr3(&netif->netmask),
+    ip4_addr4(&netif->netmask)));
+}
+
+/**
+ * Set a network interface as the default network interface
+ * (used to output all packets for which no specific route is found)
+ *
+ * @param netif the default network interface
+ */
+void
+netif_set_default(struct netif *netif)
+{
+  if (netif == NULL)
+  {
+    /* remove default route */
+    snmp_delete_iprteidx_tree(1, netif);
+  }
+  else
+  {
+    /* install default route */
+    snmp_insert_iprteidx_tree(1, netif);
+  }
+  netif_default = netif;
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n",
+           netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\''));
+}
+
+/**
+ * Bring an interface up, available for processing
+ * traffic.
+ * 
+ * @note: Enabling DHCP on a down interface will make it come
+ * up once configured.
+ * 
+ * @see dhcp_start()
+ */ 
+void netif_set_up(struct netif *netif)
+{
+  if ( !(netif->flags & NETIF_FLAG_UP )) {
+    netif->flags |= NETIF_FLAG_UP;
+    
+#if LWIP_SNMP
+    snmp_get_sysuptime(&netif->ts);
+#endif /* LWIP_SNMP */
+
+    NETIF_LINK_CALLBACK(netif);
+    NETIF_STATUS_CALLBACK(netif);
+
+#if LWIP_ARP
+    /* For Ethernet network interfaces, we would like to send a "gratuitous ARP" */ 
+    if (netif->flags & NETIF_FLAG_ETHARP) {
+      etharp_gratuitous(netif);
+    }
+#endif /* LWIP_ARP */
+
+#if LWIP_IGMP
+    /* resend IGMP memberships */
+    if (netif->flags & NETIF_FLAG_IGMP) {
+      igmp_report_groups( netif);
+    }
+#endif /* LWIP_IGMP */
+  }
+}
+
+/**
+ * Bring an interface down, disabling any traffic processing.
+ *
+ * @note: Enabling DHCP on a down interface will make it come
+ * up once configured.
+ * 
+ * @see dhcp_start()
+ */ 
+void netif_set_down(struct netif *netif)
+{
+  if ( netif->flags & NETIF_FLAG_UP )
+    {
+      netif->flags &= ~NETIF_FLAG_UP;
+#if LWIP_SNMP
+      snmp_get_sysuptime(&netif->ts);
+#endif
+      
+      NETIF_LINK_CALLBACK(netif);
+      NETIF_STATUS_CALLBACK(netif);
+    }
+}
+
+/**
+ * Ask if an interface is up
+ */ 
+u8_t netif_is_up(struct netif *netif)
+{
+  return (netif->flags & NETIF_FLAG_UP)?1:0;
+}
+
+#if LWIP_NETIF_STATUS_CALLBACK
+/**
+ * Set callback to be called when interface is brought up/down
+ */
+void netif_set_status_callback(struct netif *netif, void (* status_callback)(struct netif *netif ))
+{
+    if ( netif )
+        netif->status_callback = status_callback;
+}
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+
+#if LWIP_NETIF_LINK_CALLBACK
+/**
+ * Called by a driver when its link goes up
+ */
+void netif_set_link_up(struct netif *netif )
+{
+  netif->flags |= NETIF_FLAG_LINK_UP;
+
+#if LWIP_DHCP
+  if (netif->dhcp) {
+    dhcp_network_changed(netif);
+  }
+#endif /* LWIP_DHCP */
+
+#if LWIP_AUTOIP
+  if (netif->autoip) {
+    autoip_network_changed(netif);
+  }
+#endif /* LWIP_AUTOIP */
+
+  if (netif->flags & NETIF_FLAG_UP) {
+#if LWIP_ARP
+  /* For Ethernet network interfaces, we would like to send a "gratuitous ARP" */ 
+  if (netif->flags & NETIF_FLAG_ETHARP) {
+    etharp_gratuitous(netif);
+  }
+#endif /* LWIP_ARP */
+
+#if LWIP_IGMP
+    /* resend IGMP memberships */
+    if (netif->flags & NETIF_FLAG_IGMP) {
+      igmp_report_groups( netif);
+    }
+#endif /* LWIP_IGMP */
+  }
+  NETIF_LINK_CALLBACK(netif);
+}
+
+/**
+ * Called by a driver when its link goes down
+ */
+void netif_set_link_down(struct netif *netif )
+{
+  netif->flags &= ~NETIF_FLAG_LINK_UP;
+  NETIF_LINK_CALLBACK(netif);
+}
+
+/**
+ * Ask if a link is up
+ */ 
+u8_t netif_is_link_up(struct netif *netif)
+{
+  return (netif->flags & NETIF_FLAG_LINK_UP) ? 1 : 0;
+}
+
+/**
+ * Set callback to be called when link is brought up/down
+ */
+void netif_set_link_callback(struct netif *netif, void (* link_callback)(struct netif *netif ))
+{
+  if (netif) {
+    netif->link_callback = link_callback;
+  }
+}
+#endif /* LWIP_NETIF_LINK_CALLBACK */
+
+#if ENABLE_LOOPBACK
+/**
+ * Send an IP packet to be received on the same netif (loopif-like).
+ * The pbuf is simply copied and handed back to netif->input.
+ * In multithreaded mode, this is done directly since netif->input must put
+ * the packet on a queue.
+ * In callback mode, the packet is put on an internal queue and is fed to
+ * netif->input by netif_poll().
+ *
+ * @param netif the lwip network interface structure
+ * @param p the (IP) packet to 'send'
+ * @param ipaddr the ip address to send the packet to (not used)
+ * @return ERR_OK if the packet has been sent
+ *         ERR_MEM if the pbuf used to copy the packet couldn't be allocated
+ */
+err_t
+netif_loop_output(struct netif *netif, struct pbuf *p,
+       struct ip_addr *ipaddr)
+{
+  struct pbuf *r;
+  err_t err;
+  struct pbuf *last;
+#if LWIP_LOOPBACK_MAX_PBUFS
+  u8_t clen = 0;
+#endif /* LWIP_LOOPBACK_MAX_PBUFS */
+  SYS_ARCH_DECL_PROTECT(lev);
+  LWIP_UNUSED_ARG(ipaddr);
+
+  /* Allocate a new pbuf */
+  r = pbuf_alloc(PBUF_LINK, p->tot_len, PBUF_RAM);
+  if (r == NULL) {
+    return ERR_MEM;
+  }
+#if LWIP_LOOPBACK_MAX_PBUFS
+  clen = pbuf_clen(r);
+  /* check for overflow or too many pbuf on queue */
+  if(((netif->loop_cnt_current + clen) < netif->loop_cnt_current) ||
+    ((netif->loop_cnt_current + clen) > LWIP_LOOPBACK_MAX_PBUFS)) {
+      pbuf_free(r);
+      r = NULL;
+      return ERR_MEM;
+  }
+  netif->loop_cnt_current += clen;
+#endif /* LWIP_LOOPBACK_MAX_PBUFS */
+
+  /* Copy the whole pbuf queue p into the single pbuf r */
+  if ((err = pbuf_copy(r, p)) != ERR_OK) {
+    pbuf_free(r);
+    r = NULL;
+    return err;
+  }
+
+  /* Put the packet on a linked list which gets emptied through calling
+     netif_poll(). */
+
+  /* let last point to the last pbuf in chain r */
+  for (last = r; last->next != NULL; last = last->next);
+
+  SYS_ARCH_PROTECT(lev);
+  if(netif->loop_first != NULL) {
+    LWIP_ASSERT("if first != NULL, last must also be != NULL", netif->loop_last != NULL);
+    netif->loop_last->next = r;
+    netif->loop_last = last;
+  } else {
+    netif->loop_first = r;
+    netif->loop_last = last;
+  }
+  SYS_ARCH_UNPROTECT(lev);
+
+#if LWIP_NETIF_LOOPBACK_MULTITHREADING
+  /* For multithreading environment, schedule a call to netif_poll */
+  tcpip_callback((void (*)(void *))(netif_poll), netif);
+#endif /* LWIP_NETIF_LOOPBACK_MULTITHREADING */
+
+  return ERR_OK;
+}
+
+/**
+ * Call netif_poll() in the main loop of your application. This is to prevent
+ * reentering non-reentrant functions like tcp_input(). Packets passed to
+ * netif_loop_output() are put on a list that is passed to netif->input() by
+ * netif_poll().
+ */
+void
+netif_poll(struct netif *netif)
+{
+  struct pbuf *in;
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  do {
+    /* Get a packet from the list. With SYS_LIGHTWEIGHT_PROT=1, this is protected */
+    SYS_ARCH_PROTECT(lev);
+    in = netif->loop_first;
+    if(in != NULL) {
+      struct pbuf *in_end = in;
+#if LWIP_LOOPBACK_MAX_PBUFS
+      u8_t clen = pbuf_clen(in);
+      /* adjust the number of pbufs on queue */
+      LWIP_ASSERT("netif->loop_cnt_current underflow",
+        ((netif->loop_cnt_current - clen) < netif->loop_cnt_current));
+      netif->loop_cnt_current -= clen;
+#endif /* LWIP_LOOPBACK_MAX_PBUFS */
+      while(in_end->len != in_end->tot_len) {
+        LWIP_ASSERT("bogus pbuf: len != tot_len but next == NULL!", in_end->next != NULL);
+        in_end = in_end->next;
+      }
+      /* 'in_end' now points to the last pbuf from 'in' */
+      if(in_end == netif->loop_last) {
+        /* this was the last pbuf in the list */
+        netif->loop_first = netif->loop_last = NULL;
+      } else {
+        /* pop the pbuf off the list */
+        netif->loop_first = in_end->next;
+        LWIP_ASSERT("should not be null since first != last!", netif->loop_first != NULL);
+      }
+      /* De-queue the pbuf from its successors on the 'loop_' list. */
+      in_end->next = NULL;
+    }
+    SYS_ARCH_UNPROTECT(lev);
+
+    if(in != NULL) {
+      /* loopback packets are always IP packets! */
+      if(ip_input(in, netif) != ERR_OK) {
+        pbuf_free(in);
+      }
+      /* Don't reference the packet any more! */
+      in = NULL;
+    }
+  /* go on while there is a packet on the list */
+  } while(netif->loop_first != NULL);
+}
+
+#if !LWIP_NETIF_LOOPBACK_MULTITHREADING
+/**
+ * Calls netif_poll() for every netif on the netif_list.
+ */
+void
+netif_poll_all(void)
+{
+  struct netif *netif = netif_list;
+  /* loop through netifs */
+  while (netif != NULL) {
+    netif_poll(netif);
+    /* proceed to next network interface */
+    netif = netif->next;
+  }
+}
+#endif /* !LWIP_NETIF_LOOPBACK_MULTITHREADING */
+#endif /* ENABLE_LOOPBACK */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/pbuf.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/pbuf.c
new file mode 100644
index 0000000..11cc2e6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/pbuf.c
@@ -0,0 +1,929 @@
+/**
+ * @file
+ * Packet buffer management
+ *
+ * Packets are built from the pbuf data structure. It supports dynamic
+ * memory allocation for packet contents or can reference externally
+ * managed packet contents both in RAM and ROM. Quick allocation for
+ * incoming packets is provided through pools with fixed sized pbufs.
+ *
+ * A packet may span over multiple pbufs, chained as a singly linked
+ * list. This is called a "pbuf chain".
+ *
+ * Multiple packets may be queued, also using this singly linked list.
+ * This is called a "packet queue".
+ * 
+ * So, a packet queue consists of one or more pbuf chains, each of
+ * which consist of one or more pbufs. CURRENTLY, PACKET QUEUES ARE
+ * NOT SUPPORTED!!! Use helper structs to queue multiple packets.
+ * 
+ * The differences between a pbuf chain and a packet queue are very
+ * precise but subtle. 
+ *
+ * The last pbuf of a packet has a ->tot_len field that equals the
+ * ->len field. It can be found by traversing the list. If the last
+ * pbuf of a packet has a ->next field other than NULL, more packets
+ * are on the queue.
+ *
+ * Therefore, looping through a pbuf of a single packet, has an
+ * loop end condition (tot_len == p->len), NOT (next == NULL).
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/stats.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include "arch/perf.h"
+#if TCP_QUEUE_OOSEQ
+#include "lwip/tcp.h"
+#endif
+
+#include 
+
+#define SIZEOF_STRUCT_PBUF        LWIP_MEM_ALIGN_SIZE(sizeof(struct pbuf))
+/* Since the pool is created in memp, PBUF_POOL_BUFSIZE will be automatically
+   aligned there. Therefore, PBUF_POOL_BUFSIZE_ALIGNED can be used here. */
+#define PBUF_POOL_BUFSIZE_ALIGNED LWIP_MEM_ALIGN_SIZE(PBUF_POOL_BUFSIZE)
+
+#if !TCP_QUEUE_OOSEQ || NO_SYS
+#define PBUF_POOL_IS_EMPTY()
+#else /* !TCP_QUEUE_OOSEQ || NO_SYS */
+/** Define this to 0 to prevent freeing ooseq pbufs when the PBUF_POOL is empty */
+#ifndef PBUF_POOL_FREE_OOSEQ
+#define PBUF_POOL_FREE_OOSEQ 1
+#endif /* PBUF_POOL_FREE_OOSEQ */
+
+#if PBUF_POOL_FREE_OOSEQ
+#include "lwip/tcpip.h"
+#define PBUF_POOL_IS_EMPTY() pbuf_pool_is_empty()
+static u8_t pbuf_free_ooseq_queued;
+/**
+ * Attempt to reclaim some memory from queued out-of-sequence TCP segments
+ * if we run out of pool pbufs. It's better to give priority to new packets
+ * if we're running out.
+ *
+ * This must be done in the correct thread context therefore this function
+ * can only be used with NO_SYS=0 and through tcpip_callback.
+ */
+static void
+pbuf_free_ooseq(void* arg)
+{
+  struct tcp_pcb* pcb;
+  SYS_ARCH_DECL_PROTECT(old_level);
+  LWIP_UNUSED_ARG(arg);
+
+  SYS_ARCH_PROTECT(old_level);
+  pbuf_free_ooseq_queued = 0;
+  SYS_ARCH_UNPROTECT(old_level);
+
+  for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) {
+    if (NULL != pcb->ooseq) {
+      /** Free the ooseq pbufs of one PCB only */
+      LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free_ooseq: freeing out-of-sequence pbufs\n"));
+      tcp_segs_free(pcb->ooseq);
+      pcb->ooseq = NULL;
+      return;
+    }
+  }
+}
+
+/** Queue a call to pbuf_free_ooseq if not already queued. */
+static void
+pbuf_pool_is_empty(void)
+{
+  u8_t queued;
+  SYS_ARCH_DECL_PROTECT(old_level);
+
+  SYS_ARCH_PROTECT(old_level);
+  queued = pbuf_free_ooseq_queued;
+  pbuf_free_ooseq_queued = 1;
+  SYS_ARCH_UNPROTECT(old_level);
+
+  if(!queued) {
+    /* queue a call to pbuf_free_ooseq if not already queued */
+    if(tcpip_callback_with_block(pbuf_free_ooseq, NULL, 0) != ERR_OK) {
+      SYS_ARCH_PROTECT(old_level);
+      pbuf_free_ooseq_queued = 0;
+      SYS_ARCH_UNPROTECT(old_level);
+    }
+  }
+}
+#endif /* PBUF_POOL_FREE_OOSEQ */
+#endif /* !TCP_QUEUE_OOSEQ || NO_SYS */
+
+/**
+ * Allocates a pbuf of the given type (possibly a chain for PBUF_POOL type).
+ *
+ * The actual memory allocated for the pbuf is determined by the
+ * layer at which the pbuf is allocated and the requested size
+ * (from the size parameter).
+ *
+ * @param layer flag to define header size
+ * @param length size of the pbuf's payload
+ * @param type this parameter decides how and where the pbuf
+ * should be allocated as follows:
+ *
+ * - PBUF_RAM: buffer memory for pbuf is allocated as one large
+ *             chunk. This includes protocol headers as well.
+ * - PBUF_ROM: no buffer memory is allocated for the pbuf, even for
+ *             protocol headers. Additional headers must be prepended
+ *             by allocating another pbuf and chain in to the front of
+ *             the ROM pbuf. It is assumed that the memory used is really
+ *             similar to ROM in that it is immutable and will not be
+ *             changed. Memory which is dynamic should generally not
+ *             be attached to PBUF_ROM pbufs. Use PBUF_REF instead.
+ * - PBUF_REF: no buffer memory is allocated for the pbuf, even for
+ *             protocol headers. It is assumed that the pbuf is only
+ *             being used in a single thread. If the pbuf gets queued,
+ *             then pbuf_take should be called to copy the buffer.
+ * - PBUF_POOL: the pbuf is allocated as a pbuf chain, with pbufs from
+ *              the pbuf pool that is allocated during pbuf_init().
+ *
+ * @return the allocated pbuf. If multiple pbufs where allocated, this
+ * is the first pbuf of a pbuf chain.
+ */
+struct pbuf *
+pbuf_alloc(pbuf_layer layer, u16_t length, pbuf_type type)
+{
+  struct pbuf *p, *q, *r;
+  u16_t offset;
+  s32_t rem_len; /* remaining length */
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F")\n", length));
+
+  /* determine header offset */
+  offset = 0;
+  switch (layer) {
+  case PBUF_TRANSPORT:
+    /* add room for transport (often TCP) layer header */
+    offset += PBUF_TRANSPORT_HLEN;
+    /* FALLTHROUGH */
+  case PBUF_IP:
+    /* add room for IP layer header */
+    offset += PBUF_IP_HLEN;
+    /* FALLTHROUGH */
+  case PBUF_LINK:
+    /* add room for link layer header */
+    offset += PBUF_LINK_HLEN;
+    break;
+  case PBUF_RAW:
+    break;
+  default:
+    LWIP_ASSERT("pbuf_alloc: bad pbuf layer", 0);
+    return NULL;
+  }
+
+  switch (type) {
+  case PBUF_POOL:
+    /* allocate head of pbuf chain into p */
+    p = memp_malloc(MEMP_PBUF_POOL);
+    LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc: allocated pbuf %p\n", (void *)p));
+    if (p == NULL) {
+      PBUF_POOL_IS_EMPTY();
+      return NULL;
+    }
+    p->type = type;
+    p->next = NULL;
+
+    /* make the payload pointer point 'offset' bytes into pbuf data memory */
+    p->payload = LWIP_MEM_ALIGN((void *)((u8_t *)p + (SIZEOF_STRUCT_PBUF + offset)));
+    LWIP_ASSERT("pbuf_alloc: pbuf p->payload properly aligned",
+            ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
+    /* the total length of the pbuf chain is the requested size */
+    p->tot_len = length;
+    /* set the length of the first pbuf in the chain */
+    p->len = LWIP_MIN(length, PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset));
+    LWIP_ASSERT("check p->payload + p->len does not overflow pbuf",
+                ((u8_t*)p->payload + p->len <=
+                 (u8_t*)p + SIZEOF_STRUCT_PBUF + PBUF_POOL_BUFSIZE_ALIGNED));
+    LWIP_ASSERT("PBUF_POOL_BUFSIZE must be bigger than MEM_ALIGNMENT",
+      (PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)) > 0 );
+    /* set reference count (needed here in case we fail) */
+    p->ref = 1;
+
+    /* now allocate the tail of the pbuf chain */
+
+    /* remember first pbuf for linkage in next iteration */
+    r = p;
+    /* remaining length to be allocated */
+    rem_len = length - p->len;
+    /* any remaining pbufs to be allocated? */
+    while (rem_len > 0) {
+      q = memp_malloc(MEMP_PBUF_POOL);
+      if (q == NULL) {
+        PBUF_POOL_IS_EMPTY();
+        /* free chain so far allocated */
+        pbuf_free(p);
+        /* bail out unsuccesfully */
+        return NULL;
+      }
+      q->type = type;
+      q->flags = 0;
+      q->next = NULL;
+      /* make previous pbuf point to this pbuf */
+      r->next = q;
+      /* set total length of this pbuf and next in chain */
+      LWIP_ASSERT("rem_len < max_u16_t", rem_len < 0xffff);
+      q->tot_len = (u16_t)rem_len;
+      /* this pbuf length is pool size, unless smaller sized tail */
+      q->len = LWIP_MIN((u16_t)rem_len, PBUF_POOL_BUFSIZE_ALIGNED);
+      q->payload = (void *)((u8_t *)q + SIZEOF_STRUCT_PBUF);
+      LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned",
+              ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0);
+      LWIP_ASSERT("check p->payload + p->len does not overflow pbuf",
+                  ((u8_t*)p->payload + p->len <=
+                   (u8_t*)p + SIZEOF_STRUCT_PBUF + PBUF_POOL_BUFSIZE_ALIGNED));
+      q->ref = 1;
+      /* calculate remaining length to be allocated */
+      rem_len -= q->len;
+      /* remember this pbuf for linkage in next iteration */
+      r = q;
+    }
+    /* end of chain */
+    /*r->next = NULL;*/
+
+    break;
+  case PBUF_RAM:
+    /* If pbuf is to be allocated in RAM, allocate memory for it. */
+    p = (struct pbuf*)mem_malloc(LWIP_MEM_ALIGN_SIZE(SIZEOF_STRUCT_PBUF + offset) + LWIP_MEM_ALIGN_SIZE(length));
+    if (p == NULL) {
+      return NULL;
+    }
+    /* Set up internal structure of the pbuf. */
+    p->payload = LWIP_MEM_ALIGN((void *)((u8_t *)p + SIZEOF_STRUCT_PBUF + offset));
+    p->len = p->tot_len = length;
+    p->next = NULL;
+    p->type = type;
+
+    LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned",
+           ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
+    break;
+  /* pbuf references existing (non-volatile static constant) ROM payload? */
+  case PBUF_ROM:
+  /* pbuf references existing (externally allocated) RAM payload? */
+  case PBUF_REF:
+    /* only allocate memory for the pbuf structure */
+    p = memp_malloc(MEMP_PBUF);
+    if (p == NULL) {
+      LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+                  ("pbuf_alloc: Could not allocate MEMP_PBUF for PBUF_%s.\n",
+                  (type == PBUF_ROM) ? "ROM" : "REF"));
+      return NULL;
+    }
+    /* caller must set this field properly, afterwards */
+    p->payload = NULL;
+    p->len = p->tot_len = length;
+    p->next = NULL;
+    p->type = type;
+    break;
+  default:
+    LWIP_ASSERT("pbuf_alloc: erroneous type", 0);
+    return NULL;
+  }
+  /* set reference count */
+  p->ref = 1;
+  /* set flags */
+  p->flags = 0;
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p));
+  return p;
+}
+
+
+/**
+ * Shrink a pbuf chain to a desired length.
+ *
+ * @param p pbuf to shrink.
+ * @param new_len desired new length of pbuf chain
+ *
+ * Depending on the desired length, the first few pbufs in a chain might
+ * be skipped and left unchanged. The new last pbuf in the chain will be
+ * resized, and any remaining pbufs will be freed.
+ *
+ * @note If the pbuf is ROM/REF, only the ->tot_len and ->len fields are adjusted.
+ * @note May not be called on a packet queue.
+ *
+ * @note Despite its name, pbuf_realloc cannot grow the size of a pbuf (chain).
+ */
+void
+pbuf_realloc(struct pbuf *p, u16_t new_len)
+{
+  struct pbuf *q;
+  u16_t rem_len; /* remaining length */
+  s32_t grow;
+
+  LWIP_ASSERT("pbuf_realloc: p != NULL", p != NULL);
+  LWIP_ASSERT("pbuf_realloc: sane p->type", p->type == PBUF_POOL ||
+              p->type == PBUF_ROM ||
+              p->type == PBUF_RAM ||
+              p->type == PBUF_REF);
+
+  /* desired length larger than current length? */
+  if (new_len >= p->tot_len) {
+    /* enlarging not yet supported */
+    return;
+  }
+
+  /* the pbuf chain grows by (new_len - p->tot_len) bytes
+   * (which may be negative in case of shrinking) */
+  grow = new_len - p->tot_len;
+
+  /* first, step over any pbufs that should remain in the chain */
+  rem_len = new_len;
+  q = p;
+  /* should this pbuf be kept? */
+  while (rem_len > q->len) {
+    /* decrease remaining length by pbuf length */
+    rem_len -= q->len;
+    /* decrease total length indicator */
+    LWIP_ASSERT("grow < max_u16_t", grow < 0xffff);
+    q->tot_len += (u16_t)grow;
+    /* proceed to next pbuf in chain */
+    q = q->next;
+    LWIP_ASSERT("pbuf_realloc: q != NULL", q != NULL);
+  }
+  /* we have now reached the new last pbuf (in q) */
+  /* rem_len == desired length for pbuf q */
+
+  /* shrink allocated memory for PBUF_RAM */
+  /* (other types merely adjust their length fields */
+  if ((q->type == PBUF_RAM) && (rem_len != q->len)) {
+    /* reallocate and adjust the length of the pbuf that will be split */
+    q = mem_realloc(q, (u8_t *)q->payload - (u8_t *)q + rem_len);
+    LWIP_ASSERT("mem_realloc give q == NULL", q != NULL);
+  }
+  /* adjust length fields for new last pbuf */
+  q->len = rem_len;
+  q->tot_len = q->len;
+
+  /* any remaining pbufs in chain? */
+  if (q->next != NULL) {
+    /* free remaining pbufs in chain */
+    pbuf_free(q->next);
+  }
+  /* q is last packet in chain */
+  q->next = NULL;
+
+}
+
+/**
+ * Adjusts the payload pointer to hide or reveal headers in the payload.
+ *
+ * Adjusts the ->payload pointer so that space for a header
+ * (dis)appears in the pbuf payload.
+ *
+ * The ->payload, ->tot_len and ->len fields are adjusted.
+ *
+ * @param p pbuf to change the header size.
+ * @param header_size_increment Number of bytes to increment header size which
+ * increases the size of the pbuf. New space is on the front.
+ * (Using a negative value decreases the header size.)
+ * If hdr_size_inc is 0, this function does nothing and returns succesful.
+ *
+ * PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so
+ * the call will fail. A check is made that the increase in header size does
+ * not move the payload pointer in front of the start of the buffer.
+ * @return non-zero on failure, zero on success.
+ *
+ */
+u8_t
+pbuf_header(struct pbuf *p, s16_t header_size_increment)
+{
+  u16_t type;
+  void *payload;
+  u16_t increment_magnitude;
+
+  LWIP_ASSERT("p != NULL", p != NULL);
+  if ((header_size_increment == 0) || (p == NULL))
+    return 0;
+ 
+  if (header_size_increment < 0){
+    increment_magnitude = -header_size_increment;
+    /* Check that we aren't going to move off the end of the pbuf */
+    LWIP_ERROR("increment_magnitude <= p->len", (increment_magnitude <= p->len), return 1;);
+  } else {
+    increment_magnitude = header_size_increment;
+#if 0
+    /* Can't assert these as some callers speculatively call
+         pbuf_header() to see if it's OK.  Will return 1 below instead. */
+    /* Check that we've got the correct type of pbuf to work with */
+    LWIP_ASSERT("p->type == PBUF_RAM || p->type == PBUF_POOL", 
+                p->type == PBUF_RAM || p->type == PBUF_POOL);
+    /* Check that we aren't going to move off the beginning of the pbuf */
+    LWIP_ASSERT("p->payload - increment_magnitude >= p + SIZEOF_STRUCT_PBUF",
+                (u8_t *)p->payload - increment_magnitude >= (u8_t *)p + SIZEOF_STRUCT_PBUF);
+#endif
+  }
+
+  type = p->type;
+  /* remember current payload pointer */
+  payload = p->payload;
+
+  /* pbuf types containing payloads? */
+  if (type == PBUF_RAM || type == PBUF_POOL) {
+    /* set new payload pointer */
+    p->payload = (u8_t *)p->payload - header_size_increment;
+    /* boundary check fails? */
+    if ((u8_t *)p->payload < (u8_t *)p + SIZEOF_STRUCT_PBUF) {
+      LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+        ("pbuf_header: failed as %p < %p (not enough space for new header size)\n",
+        (void *)p->payload, (void *)(p + 1)));
+      /* restore old payload pointer */
+      p->payload = payload;
+      /* bail out unsuccesfully */
+      return 1;
+    }
+  /* pbuf types refering to external payloads? */
+  } else if (type == PBUF_REF || type == PBUF_ROM) {
+    /* hide a header in the payload? */
+    if ((header_size_increment < 0) && (increment_magnitude <= p->len)) {
+      /* increase payload pointer */
+      p->payload = (u8_t *)p->payload - header_size_increment;
+    } else {
+      /* cannot expand payload to front (yet!)
+       * bail out unsuccesfully */
+      return 1;
+    }
+  }
+  else {
+    /* Unknown type */
+    LWIP_ASSERT("bad pbuf type", 0);
+    return 1;
+  }
+  /* modify pbuf length fields */
+  p->len += header_size_increment;
+  p->tot_len += header_size_increment;
+
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_header: old %p new %p (%"S16_F")\n",
+    (void *)payload, (void *)p->payload, header_size_increment));
+
+  return 0;
+}
+
+/**
+ * Dereference a pbuf chain or queue and deallocate any no-longer-used
+ * pbufs at the head of this chain or queue.
+ *
+ * Decrements the pbuf reference count. If it reaches zero, the pbuf is
+ * deallocated.
+ *
+ * For a pbuf chain, this is repeated for each pbuf in the chain,
+ * up to the first pbuf which has a non-zero reference count after
+ * decrementing. So, when all reference counts are one, the whole
+ * chain is free'd.
+ *
+ * @param p The pbuf (chain) to be dereferenced.
+ *
+ * @return the number of pbufs that were de-allocated
+ * from the head of the chain.
+ *
+ * @note MUST NOT be called on a packet queue (Not verified to work yet).
+ * @note the reference counter of a pbuf equals the number of pointers
+ * that refer to the pbuf (or into the pbuf).
+ *
+ * @internal examples:
+ *
+ * Assuming existing chains a->b->c with the following reference
+ * counts, calling pbuf_free(a) results in:
+ * 
+ * 1->2->3 becomes ...1->3
+ * 3->3->3 becomes 2->3->3
+ * 1->1->2 becomes ......1
+ * 2->1->1 becomes 1->1->1
+ * 1->1->1 becomes .......
+ *
+ */
+u8_t
+pbuf_free(struct pbuf *p)
+{
+  u16_t type;
+  struct pbuf *q;
+  u8_t count;
+
+  if (p == NULL) {
+    LWIP_ASSERT("p != NULL", p != NULL);
+    /* if assertions are disabled, proceed with debug output */
+    LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+      ("pbuf_free(p == NULL) was called.\n"));
+    return 0;
+  }
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free(%p)\n", (void *)p));
+
+  PERF_START;
+
+  LWIP_ASSERT("pbuf_free: sane type",
+    p->type == PBUF_RAM || p->type == PBUF_ROM ||
+    p->type == PBUF_REF || p->type == PBUF_POOL);
+
+  count = 0;
+  /* de-allocate all consecutive pbufs from the head of the chain that
+   * obtain a zero reference count after decrementing*/
+  while (p != NULL) {
+    u16_t ref;
+    SYS_ARCH_DECL_PROTECT(old_level);
+    /* Since decrementing ref cannot be guaranteed to be a single machine operation
+     * we must protect it. We put the new ref into a local variable to prevent
+     * further protection. */
+    SYS_ARCH_PROTECT(old_level);
+    /* all pbufs in a chain are referenced at least once */
+    LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0);
+    /* decrease reference count (number of pointers to pbuf) */
+    ref = --(p->ref);
+    SYS_ARCH_UNPROTECT(old_level);
+    /* this pbuf is no longer referenced to? */
+    if (ref == 0) {
+      /* remember next pbuf in chain for next iteration */
+      q = p->next;
+      LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: deallocating %p\n", (void *)p));
+      type = p->type;
+      /* is this a pbuf from the pool? */
+      if (type == PBUF_POOL) {
+        memp_free(MEMP_PBUF_POOL, p);
+      /* is this a ROM or RAM referencing pbuf? */
+      } else if (type == PBUF_ROM || type == PBUF_REF) {
+        memp_free(MEMP_PBUF, p);
+      /* type == PBUF_RAM */
+      } else {
+        mem_free(p);
+      }
+      count++;
+      /* proceed to next pbuf */
+      p = q;
+    /* p->ref > 0, this pbuf is still referenced to */
+    /* (and so the remaining pbufs in chain as well) */
+    } else {
+      LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, ref));
+      /* stop walking through the chain */
+      p = NULL;
+    }
+  }
+  PERF_STOP("pbuf_free");
+  /* return number of de-allocated pbufs */
+  return count;
+}
+
+/**
+ * Count number of pbufs in a chain
+ *
+ * @param p first pbuf of chain
+ * @return the number of pbufs in a chain
+ */
+
+u8_t
+pbuf_clen(struct pbuf *p)
+{
+  u8_t len;
+
+  len = 0;
+  while (p != NULL) {
+    ++len;
+    p = p->next;
+  }
+  return len;
+}
+
+/**
+ * Increment the reference count of the pbuf.
+ *
+ * @param p pbuf to increase reference counter of
+ *
+ */
+void
+pbuf_ref(struct pbuf *p)
+{
+  SYS_ARCH_DECL_PROTECT(old_level);
+  /* pbuf given? */
+  if (p != NULL) {
+    SYS_ARCH_PROTECT(old_level);
+    ++(p->ref);
+    SYS_ARCH_UNPROTECT(old_level);
+  }
+}
+
+/**
+ * Concatenate two pbufs (each may be a pbuf chain) and take over
+ * the caller's reference of the tail pbuf.
+ * 
+ * @note The caller MAY NOT reference the tail pbuf afterwards.
+ * Use pbuf_chain() for that purpose.
+ * 
+ * @see pbuf_chain()
+ */
+
+void
+pbuf_cat(struct pbuf *h, struct pbuf *t)
+{
+  struct pbuf *p;
+
+  LWIP_ERROR("(h != NULL) && (t != NULL) (programmer violates API)",
+             ((h != NULL) && (t != NULL)), return;);
+
+  /* proceed to last pbuf of chain */
+  for (p = h; p->next != NULL; p = p->next) {
+    /* add total length of second chain to all totals of first chain */
+    p->tot_len += t->tot_len;
+  }
+  /* { p is last pbuf of first h chain, p->next == NULL } */
+  LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len);
+  LWIP_ASSERT("p->next == NULL", p->next == NULL);
+  /* add total length of second chain to last pbuf total of first chain */
+  p->tot_len += t->tot_len;
+  /* chain last pbuf of head (p) with first of tail (t) */
+  p->next = t;
+  /* p->next now references t, but the caller will drop its reference to t,
+   * so netto there is no change to the reference count of t.
+   */
+}
+
+/**
+ * Chain two pbufs (or pbuf chains) together.
+ * 
+ * The caller MUST call pbuf_free(t) once it has stopped
+ * using it. Use pbuf_cat() instead if you no longer use t.
+ * 
+ * @param h head pbuf (chain)
+ * @param t tail pbuf (chain)
+ * @note The pbufs MUST belong to the same packet.
+ * @note MAY NOT be called on a packet queue.
+ *
+ * The ->tot_len fields of all pbufs of the head chain are adjusted.
+ * The ->next field of the last pbuf of the head chain is adjusted.
+ * The ->ref field of the first pbuf of the tail chain is adjusted.
+ *
+ */
+void
+pbuf_chain(struct pbuf *h, struct pbuf *t)
+{
+  pbuf_cat(h, t);
+  /* t is now referenced by h */
+  pbuf_ref(t);
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t));
+}
+
+/**
+ * Dechains the first pbuf from its succeeding pbufs in the chain.
+ *
+ * Makes p->tot_len field equal to p->len.
+ * @param p pbuf to dechain
+ * @return remainder of the pbuf chain, or NULL if it was de-allocated.
+ * @note May not be called on a packet queue.
+ */
+struct pbuf *
+pbuf_dechain(struct pbuf *p)
+{
+  struct pbuf *q;
+  u8_t tail_gone = 1;
+  /* tail */
+  q = p->next;
+  /* pbuf has successor in chain? */
+  if (q != NULL) {
+    /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */
+    LWIP_ASSERT("p->tot_len == p->len + q->tot_len", q->tot_len == p->tot_len - p->len);
+    /* enforce invariant if assertion is disabled */
+    q->tot_len = p->tot_len - p->len;
+    /* decouple pbuf from remainder */
+    p->next = NULL;
+    /* total length of pbuf p is its own length only */
+    p->tot_len = p->len;
+    /* q is no longer referenced by p, free it */
+    LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_dechain: unreferencing %p\n", (void *)q));
+    tail_gone = pbuf_free(q);
+    if (tail_gone > 0) {
+      LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE,
+                  ("pbuf_dechain: deallocated %p (as it is no longer referenced)\n", (void *)q));
+    }
+    /* return remaining tail or NULL if deallocated */
+  }
+  /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */
+  LWIP_ASSERT("p->tot_len == p->len", p->tot_len == p->len);
+  return ((tail_gone > 0) ? NULL : q);
+}
+
+/**
+ *
+ * Create PBUF_RAM copies of pbufs.
+ *
+ * Used to queue packets on behalf of the lwIP stack, such as
+ * ARP based queueing.
+ *
+ * @note You MUST explicitly use p = pbuf_take(p);
+ *
+ * @note Only one packet is copied, no packet queue!
+ *
+ * @param p_to pbuf destination of the copy
+ * @param p_from pbuf source of the copy
+ *
+ * @return ERR_OK if pbuf was copied
+ *         ERR_ARG if one of the pbufs is NULL or p_to is not big
+ *                 enough to hold p_from
+ */
+err_t
+pbuf_copy(struct pbuf *p_to, struct pbuf *p_from)
+{
+  u16_t offset_to=0, offset_from=0, len;
+
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy(%p, %p)\n",
+    (void*)p_to, (void*)p_from));
+
+  /* is the target big enough to hold the source? */
+  LWIP_ERROR("pbuf_copy: target not big enough to hold source", ((p_to != NULL) &&
+             (p_from != NULL) && (p_to->tot_len >= p_from->tot_len)), return ERR_ARG;);
+
+  /* iterate through pbuf chain */
+  do
+  {
+    LWIP_ASSERT("p_to != NULL", p_to != NULL);
+    /* copy one part of the original chain */
+    if ((p_to->len - offset_to) >= (p_from->len - offset_from)) {
+      /* complete current p_from fits into current p_to */
+      len = p_from->len - offset_from;
+    } else {
+      /* current p_from does not fit into current p_to */
+      len = p_to->len - offset_to;
+    }
+    MEMCPY((u8_t*)p_to->payload + offset_to, (u8_t*)p_from->payload + offset_from, len);
+    offset_to += len;
+    offset_from += len;
+    LWIP_ASSERT("offset_to <= p_to->len", offset_to <= p_to->len);
+    if (offset_to == p_to->len) {
+      /* on to next p_to (if any) */
+      offset_to = 0;
+      p_to = p_to->next;
+    }
+    LWIP_ASSERT("offset_from <= p_from->len", offset_from <= p_from->len);
+    if (offset_from >= p_from->len) {
+      /* on to next p_from (if any) */
+      offset_from = 0;
+      p_from = p_from->next;
+    }
+
+    if((p_from != NULL) && (p_from->len == p_from->tot_len)) {
+      /* don't copy more than one packet! */
+      LWIP_ERROR("pbuf_copy() does not allow packet queues!\n",
+                 (p_from->next == NULL), return ERR_VAL;);
+    }
+    if((p_to != NULL) && (p_to->len == p_to->tot_len)) {
+      /* don't copy more than one packet! */
+      LWIP_ERROR("pbuf_copy() does not allow packet queues!\n",
+                  (p_to->next == NULL), return ERR_VAL;);
+    }
+  } while (p_from);
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy: end of chain reached.\n"));
+  return ERR_OK;
+}
+
+/**
+ * Copy (part of) the contents of a packet buffer
+ * to an application supplied buffer.
+ *
+ * @param buf the pbuf from which to copy data
+ * @param dataptr the application supplied buffer
+ * @param len length of data to copy (dataptr must be big enough). No more 
+ * than buf->tot_len will be copied, irrespective of len
+ * @param offset offset into the packet buffer from where to begin copying len bytes
+ * @return the number of bytes copied, or 0 on failure
+ */
+u16_t
+pbuf_copy_partial(struct pbuf *buf, void *dataptr, u16_t len, u16_t offset)
+{
+  struct pbuf *p;
+  u16_t left;
+  u16_t buf_copy_len;
+  u16_t copied_total = 0;
+
+  LWIP_ERROR("pbuf_copy_partial: invalid buf", (buf != NULL), return 0;);
+  LWIP_ERROR("pbuf_copy_partial: invalid dataptr", (dataptr != NULL), return 0;);
+
+  left = 0;
+
+  if((buf == NULL) || (dataptr == NULL)) {
+    return 0;
+  }
+
+  /* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */
+  for(p = buf; len != 0 && p != NULL; p = p->next) {
+    if ((offset != 0) && (offset >= p->len)) {
+      /* don't copy from this buffer -> on to the next */
+      offset -= p->len;
+    } else {
+      /* copy from this buffer. maybe only partially. */
+      buf_copy_len = p->len - offset;
+      if (buf_copy_len > len)
+          buf_copy_len = len;
+      /* copy the necessary parts of the buffer */
+      MEMCPY(&((char*)dataptr)[left], &((char*)p->payload)[offset], buf_copy_len);
+      copied_total += buf_copy_len;
+      left += buf_copy_len;
+      len -= buf_copy_len;
+      offset = 0;
+    }
+  }
+  return copied_total;
+}
+
+/**
+ * Copy application supplied data into a pbuf.
+ * This function can only be used to copy the equivalent of buf->tot_len data.
+ *
+ * @param buf pbuf to fill with data
+ * @param dataptr application supplied data buffer
+ * @param len length of the application supplied data buffer
+ *
+ * @return ERR_OK if successful, ERR_MEM if the pbuf is not big enough
+ */
+err_t
+pbuf_take(struct pbuf *buf, const void *dataptr, u16_t len)
+{
+  struct pbuf *p;
+  u16_t buf_copy_len;
+  u16_t total_copy_len = len;
+  u16_t copied_total = 0;
+
+  LWIP_ERROR("pbuf_take: invalid buf", (buf != NULL), return 0;);
+  LWIP_ERROR("pbuf_take: invalid dataptr", (dataptr != NULL), return 0;);
+
+  if ((buf == NULL) || (dataptr == NULL) || (buf->tot_len < len)) {
+    return ERR_ARG;
+  }
+
+  /* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */
+  for(p = buf; total_copy_len != 0; p = p->next) {
+    LWIP_ASSERT("pbuf_take: invalid pbuf", p != NULL);
+    buf_copy_len = total_copy_len;
+    if (buf_copy_len > p->len) {
+      /* this pbuf cannot hold all remaining data */
+      buf_copy_len = p->len;
+    }
+    /* copy the necessary parts of the buffer */
+    MEMCPY(p->payload, &((char*)dataptr)[copied_total], buf_copy_len);
+    total_copy_len -= buf_copy_len;
+    copied_total += buf_copy_len;
+  }
+  LWIP_ASSERT("did not copy all data", total_copy_len == 0 && copied_total == len);
+  return ERR_OK;
+}
+
+/**
+ * Creates a single pbuf out of a queue of pbufs.
+ *
+ * @remark: The source pbuf 'p' is not freed by this function because that can
+ *          be illegal in some places!
+ *
+ * @param p the source pbuf
+ * @param layer pbuf_layer of the new pbuf
+ *
+ * @return a new, single pbuf (p->next is NULL)
+ *         or the old pbuf if allocation fails
+ */
+struct pbuf*
+pbuf_coalesce(struct pbuf *p, pbuf_layer layer)
+{
+  struct pbuf *q;
+  err_t err;
+  if (p->next == NULL) {
+    return p;
+  }
+  q = pbuf_alloc(layer, p->tot_len, PBUF_RAM);
+  if (q == NULL) {
+    /* @todo: what do we do now? */
+    return p;
+  }
+  err = pbuf_copy(q, p);
+  LWIP_ASSERT("pbuf_copy failed", err == ERR_OK);
+  pbuf_free(p);
+  return q;
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/raw.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/raw.c
new file mode 100644
index 0000000..2f105fe
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/raw.c
@@ -0,0 +1,353 @@
+/**
+ * @file
+ * Implementation of raw protocol PCBs for low-level handling of
+ * different types of protocols besides (or overriding) those
+ * already available in lwIP.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/def.h"
+#include "lwip/memp.h"
+#include "lwip/inet.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/raw.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+#include "arch/perf.h"
+
+#include 
+
+/** The list of RAW PCBs */
+static struct raw_pcb *raw_pcbs;
+
+/**
+ * Determine if in incoming IP packet is covered by a RAW PCB
+ * and if so, pass it to a user-provided receive callback function.
+ *
+ * Given an incoming IP datagram (as a chain of pbufs) this function
+ * finds a corresponding RAW PCB and calls the corresponding receive
+ * callback function.
+ *
+ * @param p pbuf to be demultiplexed to a RAW PCB.
+ * @param inp network interface on which the datagram was received.
+ * @return - 1 if the packet has been eaten by a RAW PCB receive
+ *           callback function. The caller MAY NOT not reference the
+ *           packet any longer, and MAY NOT call pbuf_free().
+ * @return - 0 if packet is not eaten (pbuf is still referenced by the
+ *           caller).
+ *
+ */
+u8_t
+raw_input(struct pbuf *p, struct netif *inp)
+{
+  struct raw_pcb *pcb, *prev;
+  struct ip_hdr *iphdr;
+  s16_t proto;
+  u8_t eaten = 0;
+
+  LWIP_UNUSED_ARG(inp);
+
+  iphdr = p->payload;
+  proto = IPH_PROTO(iphdr);
+
+  prev = NULL;
+  pcb = raw_pcbs;
+  /* loop through all raw pcbs until the packet is eaten by one */
+  /* this allows multiple pcbs to match against the packet by design */
+  while ((eaten == 0) && (pcb != NULL)) {
+    if (pcb->protocol == proto) {
+#if IP_SOF_BROADCAST_RECV
+      /* broadcast filter? */
+      if ((pcb->so_options & SOF_BROADCAST) || !ip_addr_isbroadcast(&(iphdr->dest), inp))
+#endif /* IP_SOF_BROADCAST_RECV */
+      {
+        /* receive callback function available? */
+        if (pcb->recv != NULL) {
+          /* the receive callback function did not eat the packet? */
+          if (pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src)) != 0) {
+            /* receive function ate the packet */
+            p = NULL;
+            eaten = 1;
+            if (prev != NULL) {
+            /* move the pcb to the front of raw_pcbs so that is
+               found faster next time */
+              prev->next = pcb->next;
+              pcb->next = raw_pcbs;
+              raw_pcbs = pcb;
+            }
+          }
+        }
+        /* no receive callback function was set for this raw PCB */
+      }
+      /* drop the packet */
+    }
+    prev = pcb;
+    pcb = pcb->next;
+  }
+  return eaten;
+}
+
+/**
+ * Bind a RAW PCB.
+ *
+ * @param pcb RAW PCB to be bound with a local address ipaddr.
+ * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to
+ * bind to all local interfaces.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_USE. The specified IP address is already bound to by
+ * another RAW PCB.
+ *
+ * @see raw_disconnect()
+ */
+err_t
+raw_bind(struct raw_pcb *pcb, struct ip_addr *ipaddr)
+{
+  ip_addr_set(&pcb->local_ip, ipaddr);
+  return ERR_OK;
+}
+
+/**
+ * Connect an RAW PCB. This function is required by upper layers
+ * of lwip. Using the raw api you could use raw_sendto() instead
+ *
+ * This will associate the RAW PCB with the remote address.
+ *
+ * @param pcb RAW PCB to be connected with remote address ipaddr and port.
+ * @param ipaddr remote IP address to connect with.
+ *
+ * @return lwIP error code
+ *
+ * @see raw_disconnect() and raw_sendto()
+ */
+err_t
+raw_connect(struct raw_pcb *pcb, struct ip_addr *ipaddr)
+{
+  ip_addr_set(&pcb->remote_ip, ipaddr);
+  return ERR_OK;
+}
+
+
+/**
+ * Set the callback function for received packets that match the
+ * raw PCB's protocol and binding. 
+ * 
+ * The callback function MUST either
+ * - eat the packet by calling pbuf_free() and returning non-zero. The
+ *   packet will not be passed to other raw PCBs or other protocol layers.
+ * - not free the packet, and return zero. The packet will be matched
+ *   against further PCBs and/or forwarded to another protocol layers.
+ * 
+ * @return non-zero if the packet was free()d, zero if the packet remains
+ * available for others.
+ */
+void
+raw_recv(struct raw_pcb *pcb,
+         u8_t (* recv)(void *arg, struct raw_pcb *upcb, struct pbuf *p,
+                      struct ip_addr *addr),
+         void *recv_arg)
+{
+  /* remember recv() callback and user data */
+  pcb->recv = recv;
+  pcb->recv_arg = recv_arg;
+}
+
+/**
+ * Send the raw IP packet to the given address. Note that actually you cannot
+ * modify the IP headers (this is inconsistent with the receive callback where
+ * you actually get the IP headers), you can only specify the IP payload here.
+ * It requires some more changes in lwIP. (there will be a raw_send() function
+ * then.)
+ *
+ * @param pcb the raw pcb which to send
+ * @param p the IP payload to send
+ * @param ipaddr the destination address of the IP packet
+ *
+ */
+err_t
+raw_sendto(struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr)
+{
+  err_t err;
+  struct netif *netif;
+  struct ip_addr *src_ip;
+  struct pbuf *q; /* q will be sent down the stack */
+  
+  LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE, ("raw_sendto\n"));
+  
+  /* not enough space to add an IP header to first pbuf in given p chain? */
+  if (pbuf_header(p, IP_HLEN)) {
+    /* allocate header in new pbuf */
+    q = pbuf_alloc(PBUF_IP, 0, PBUF_RAM);
+    /* new header pbuf could not be allocated? */
+    if (q == NULL) {
+      LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("raw_sendto: could not allocate header\n"));
+      return ERR_MEM;
+    }
+    /* chain header q in front of given pbuf p */
+    pbuf_chain(q, p);
+    /* { first pbuf q points to header pbuf } */
+    LWIP_DEBUGF(RAW_DEBUG, ("raw_sendto: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
+  }  else {
+    /* first pbuf q equals given pbuf */
+    q = p;
+    if(pbuf_header(q, -IP_HLEN)) {
+      LWIP_ASSERT("Can't restore header we just removed!", 0);
+      return ERR_MEM;
+    }
+  }
+
+  if ((netif = ip_route(ipaddr)) == NULL) {
+    LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_LEVEL_WARNING, ("raw_sendto: No route to 0x%"X32_F"\n", ipaddr->addr));
+    /* free any temporary header pbuf allocated by pbuf_header() */
+    if (q != p) {
+      pbuf_free(q);
+    }
+    return ERR_RTE;
+  }
+
+#if IP_SOF_BROADCAST
+  /* broadcast filter? */
+  if ( ((pcb->so_options & SOF_BROADCAST) == 0) && ip_addr_isbroadcast(ipaddr, netif) ) {
+    LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_LEVEL_WARNING, ("raw_sendto: SOF_BROADCAST not enabled on pcb %p\n", (void *)pcb));
+    /* free any temporary header pbuf allocated by pbuf_header() */
+    if (q != p) {
+      pbuf_free(q);
+    }
+    return ERR_VAL;
+  }
+#endif /* IP_SOF_BROADCAST */
+
+  if (ip_addr_isany(&pcb->local_ip)) {
+    /* use outgoing network interface IP address as source address */
+    src_ip = &(netif->ip_addr);
+  } else {
+    /* use RAW PCB local IP address as source address */
+    src_ip = &(pcb->local_ip);
+  }
+
+#if LWIP_NETIF_HWADDRHINT
+  netif->addr_hint = &(pcb->addr_hint);
+#endif /* LWIP_NETIF_HWADDRHINT*/
+  err = ip_output_if (q, src_ip, ipaddr, pcb->ttl, pcb->tos, pcb->protocol, netif);
+#if LWIP_NETIF_HWADDRHINT
+  netif->addr_hint = NULL;
+#endif /* LWIP_NETIF_HWADDRHINT*/
+
+  /* did we chain a header earlier? */
+  if (q != p) {
+    /* free the header */
+    pbuf_free(q);
+  }
+  return err;
+}
+
+/**
+ * Send the raw IP packet to the address given by raw_connect()
+ *
+ * @param pcb the raw pcb which to send
+ * @param p the IP payload to send
+ *
+ */
+err_t
+raw_send(struct raw_pcb *pcb, struct pbuf *p)
+{
+  return raw_sendto(pcb, p, &pcb->remote_ip);
+}
+
+/**
+ * Remove an RAW PCB.
+ *
+ * @param pcb RAW PCB to be removed. The PCB is removed from the list of
+ * RAW PCB's and the data structure is freed from memory.
+ *
+ * @see raw_new()
+ */
+void
+raw_remove(struct raw_pcb *pcb)
+{
+  struct raw_pcb *pcb2;
+  /* pcb to be removed is first in list? */
+  if (raw_pcbs == pcb) {
+    /* make list start at 2nd pcb */
+    raw_pcbs = raw_pcbs->next;
+    /* pcb not 1st in list */
+  } else {
+    for(pcb2 = raw_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
+      /* find pcb in raw_pcbs list */
+      if (pcb2->next != NULL && pcb2->next == pcb) {
+        /* remove pcb from list */
+        pcb2->next = pcb->next;
+      }
+    }
+  }
+  memp_free(MEMP_RAW_PCB, pcb);
+}
+
+/**
+ * Create a RAW PCB.
+ *
+ * @return The RAW PCB which was created. NULL if the PCB data structure
+ * could not be allocated.
+ *
+ * @param proto the protocol number of the IPs payload (e.g. IP_PROTO_ICMP)
+ *
+ * @see raw_remove()
+ */
+struct raw_pcb *
+raw_new(u8_t proto) {
+  struct raw_pcb *pcb;
+
+  LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE, ("raw_new\n"));
+
+  pcb = memp_malloc(MEMP_RAW_PCB);
+  /* could allocate RAW PCB? */
+  if (pcb != NULL) {
+    /* initialize PCB to all zeroes */
+    memset(pcb, 0, sizeof(struct raw_pcb));
+    pcb->protocol = proto;
+    pcb->ttl = RAW_TTL;
+    pcb->next = raw_pcbs;
+    raw_pcbs = pcb;
+  }
+  return pcb;
+}
+
+#endif /* LWIP_RAW */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/snmp/asn1_dec.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/snmp/asn1_dec.c
new file mode 100644
index 0000000..650fb40
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/snmp/asn1_dec.c
@@ -0,0 +1,657 @@
+/**
+ * @file
+ * Abstract Syntax Notation One (ISO 8824, 8825) decoding
+ *
+ * @todo not optimised (yet), favor correctness over speed, favor speed over size
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/snmp_asn1.h"
+
+/**
+ * Retrieves type field from incoming pbuf chain.
+ *
+ * @param p points to a pbuf holding an ASN1 coded type field
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded type field
+ * @param type return ASN1 type
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ */
+err_t
+snmp_asn1_dec_type(struct pbuf *p, u16_t ofs, u8_t *type)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+      *type = *msg_ptr;
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Decodes length field from incoming pbuf chain into host length.
+ *
+ * @param p points to a pbuf holding an ASN1 coded length
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded length
+ * @param octets_used returns number of octets used by the length code
+ * @param length return host order length, upto 64k
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ */
+err_t
+snmp_asn1_dec_length(struct pbuf *p, u16_t ofs, u8_t *octets_used, u16_t *length)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+
+      if (*msg_ptr < 0x80)
+      {
+        /* primitive definite length format */
+        *octets_used = 1;
+        *length = *msg_ptr;
+        return ERR_OK;
+      }
+      else if (*msg_ptr == 0x80)
+      {
+        /* constructed indefinite length format, termination with two zero octets */
+        u8_t zeros;
+        u8_t i;
+
+        *length = 0;
+        zeros = 0;
+        while (zeros != 2)
+        {
+          i = 2;
+          while (i > 0)
+          {
+            i--;
+            (*length) += 1;
+            ofs += 1;
+            if (ofs >= plen)
+            {
+              /* next octet in next pbuf */
+              p = p->next;
+              if (p == NULL) { return ERR_ARG; }
+              msg_ptr = p->payload;
+              plen += p->len;
+            }
+            else
+            {
+              /* next octet in same pbuf */
+              msg_ptr++;
+            }
+            if (*msg_ptr == 0)
+            {
+              zeros++;
+              if (zeros == 2)
+              {
+                /* stop while (i > 0) */
+                i = 0;
+              }
+            }
+            else
+            {
+              zeros = 0;
+            }
+          }
+        }
+        *octets_used = 1;
+        return ERR_OK;
+      }
+      else if (*msg_ptr == 0x81)
+      {
+        /* constructed definite length format, one octet */
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+        *length = *msg_ptr;
+        *octets_used = 2;
+        return ERR_OK;
+      }
+      else if (*msg_ptr == 0x82)
+      {
+        u8_t i;
+
+        /* constructed definite length format, two octets */
+        i = 2;
+        while (i > 0)
+        {
+          i--;
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+          if (i == 0)
+          {
+            /* least significant length octet */
+            *length |= *msg_ptr;
+          }
+          else
+          {
+            /* most significant length octet */
+            *length = (*msg_ptr) << 8;
+          }
+        }
+        *octets_used = 3;
+        return ERR_OK;
+      }
+      else
+      {
+        /* constructed definite length format 3..127 octets, this is too big (>64k) */
+        /**  @todo: do we need to accept inefficient codings with many leading zero's? */
+        *octets_used = 1 + ((*msg_ptr) & 0x7f);
+        return ERR_ARG;
+      }
+    }
+    p = p->next;
+  }
+
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Decodes positive integer (counter, gauge, timeticks) into u32_t.
+ *
+ * @param p points to a pbuf holding an ASN1 coded integer
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded integer
+ * @param len length of the coded integer field
+ * @param value return host order integer
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ *
+ * @note ASN coded integers are _always_ signed. E.g. +0xFFFF is coded
+ * as 0x00,0xFF,0xFF. Note the leading sign octet. A positive value
+ * of 0xFFFFFFFF is preceded with 0x00 and the length is 5 octets!!
+ */
+err_t
+snmp_asn1_dec_u32t(struct pbuf *p, u16_t ofs, u16_t len, u32_t *value)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+      if ((len > 0) && (len < 6))
+      {
+        /* start from zero */
+        *value = 0;
+        if (*msg_ptr & 0x80)
+        {
+          /* negative, expecting zero sign bit! */
+          return ERR_ARG;
+        }
+        else
+        {
+          /* positive */
+          if ((len > 1) && (*msg_ptr == 0))
+          {
+            /* skip leading "sign byte" octet 0x00 */
+            len--;
+            ofs += 1;
+            if (ofs >= plen)
+            {
+              /* next octet in next pbuf */
+              p = p->next;
+              if (p == NULL) { return ERR_ARG; }
+              msg_ptr = p->payload;
+              plen += p->len;
+            }
+            else
+            {
+              /* next octet in same pbuf */
+              msg_ptr++;
+            }
+          }
+        }
+        /* OR octets with value */
+        while (len > 1)
+        {
+          len--;
+          *value |= *msg_ptr;
+          *value <<= 8;
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+        }
+        *value |= *msg_ptr;
+        return ERR_OK;
+      }
+      else
+      {
+        return ERR_ARG;
+      }
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Decodes integer into s32_t.
+ *
+ * @param p points to a pbuf holding an ASN1 coded integer
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded integer
+ * @param len length of the coded integer field
+ * @param value return host order integer
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ *
+ * @note ASN coded integers are _always_ signed!
+ */
+err_t
+snmp_asn1_dec_s32t(struct pbuf *p, u16_t ofs, u16_t len, s32_t *value)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+#if BYTE_ORDER == LITTLE_ENDIAN
+  u8_t *lsb_ptr = (u8_t*)value;
+#endif
+#if BYTE_ORDER == BIG_ENDIAN
+  u8_t *lsb_ptr = (u8_t*)value + sizeof(s32_t) - 1;
+#endif
+  u8_t sign;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+      if ((len > 0) && (len < 5))
+      {
+        if (*msg_ptr & 0x80)
+        {
+          /* negative, start from -1 */
+          *value = -1;
+          sign = 1;
+        }
+        else
+        {
+          /* positive, start from 0 */
+          *value = 0;
+          sign = 0;
+        }
+        /* OR/AND octets with value */
+        while (len > 1)
+        {
+          len--;
+          if (sign)
+          {
+            *lsb_ptr &= *msg_ptr;
+            *value <<= 8;
+            *lsb_ptr |= 255;
+          }
+          else
+          {
+            *lsb_ptr |= *msg_ptr;
+            *value <<= 8;
+          }
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+        }
+        if (sign)
+        {
+          *lsb_ptr &= *msg_ptr;
+        }
+        else
+        {
+          *lsb_ptr |= *msg_ptr;
+        }
+        return ERR_OK;
+      }
+      else
+      {
+        return ERR_ARG;
+      }
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Decodes object identifier from incoming message into array of s32_t.
+ *
+ * @param p points to a pbuf holding an ASN1 coded object identifier
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded object identifier
+ * @param len length of the coded object identifier
+ * @param oid return object identifier struct
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ */
+err_t
+snmp_asn1_dec_oid(struct pbuf *p, u16_t ofs, u16_t len, struct snmp_obj_id *oid)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+  s32_t *oid_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+
+      oid->len = 0;
+      oid_ptr = &oid->id[0];
+      if (len > 0)
+      {
+        /* first compressed octet */
+        if (*msg_ptr == 0x2B)
+        {
+          /* (most) common case 1.3 (iso.org) */
+          *oid_ptr = 1;
+          oid_ptr++;
+          *oid_ptr = 3;
+          oid_ptr++;
+        }
+        else if (*msg_ptr < 40)
+        {
+          *oid_ptr = 0;
+          oid_ptr++;
+          *oid_ptr = *msg_ptr;
+          oid_ptr++;
+        }
+        else if (*msg_ptr < 80)
+        {
+          *oid_ptr = 1;
+          oid_ptr++;
+          *oid_ptr = (*msg_ptr) - 40;
+          oid_ptr++;
+        }
+        else
+        {
+          *oid_ptr = 2;
+          oid_ptr++;
+          *oid_ptr = (*msg_ptr) - 80;
+          oid_ptr++;
+        }
+        oid->len = 2;
+      }
+      else
+      {
+        /* accepting zero length identifiers e.g. for
+           getnext operation. uncommon but valid */
+        return ERR_OK;
+      }
+      len--;
+      if (len > 0)
+      {
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+      }
+      while ((len > 0) && (oid->len < LWIP_SNMP_OBJ_ID_LEN))
+      {
+        /* sub-identifier uses multiple octets */
+        if (*msg_ptr & 0x80)
+        {
+          s32_t sub_id = 0;
+
+          while ((*msg_ptr & 0x80) && (len > 1))
+          {
+            len--;
+            sub_id = (sub_id << 7) + (*msg_ptr & ~0x80);
+            ofs += 1;
+            if (ofs >= plen)
+            {
+              /* next octet in next pbuf */
+              p = p->next;
+              if (p == NULL) { return ERR_ARG; }
+              msg_ptr = p->payload;
+              plen += p->len;
+            }
+            else
+            {
+              /* next octet in same pbuf */
+              msg_ptr++;
+            }
+          }
+          if (!(*msg_ptr & 0x80) && (len > 0))
+          {
+            /* last octet sub-identifier */
+            len--;
+            sub_id = (sub_id << 7) + *msg_ptr;
+            *oid_ptr = sub_id;
+          }
+        }
+        else
+        {
+          /* !(*msg_ptr & 0x80) sub-identifier uses single octet */
+          len--;
+          *oid_ptr = *msg_ptr;
+        }
+        if (len > 0)
+        {
+          /* remaining oid bytes available ... */
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+        }
+        oid_ptr++;
+        oid->len++;
+      }
+      if (len == 0)
+      {
+        /* len == 0, end of oid */
+        return ERR_OK;
+      }
+      else
+      {
+        /* len > 0, oid->len == LWIP_SNMP_OBJ_ID_LEN or malformed encoding */
+        return ERR_ARG;
+      }
+
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Decodes (copies) raw data (ip-addresses, octet strings, opaque encoding)
+ * from incoming message into array.
+ *
+ * @param p points to a pbuf holding an ASN1 coded raw data
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded raw data
+ * @param len length of the coded raw data (zero is valid, e.g. empty string!)
+ * @param raw_len length of the raw return value
+ * @param raw return raw bytes
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ */
+err_t
+snmp_asn1_dec_raw(struct pbuf *p, u16_t ofs, u16_t len, u16_t raw_len, u8_t *raw)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  if (len > 0)
+  {
+    plen = 0;
+    while (p != NULL)
+    {
+      base = plen;
+      plen += p->len;
+      if (ofs < plen)
+      {
+        msg_ptr = p->payload;
+        msg_ptr += ofs - base;
+        if (raw_len >= len)
+        {
+          while (len > 1)
+          {
+            /* copy len - 1 octets */
+            len--;
+            *raw = *msg_ptr;
+            raw++;
+            ofs += 1;
+            if (ofs >= plen)
+            {
+              /* next octet in next pbuf */
+              p = p->next;
+              if (p == NULL) { return ERR_ARG; }
+              msg_ptr = p->payload;
+              plen += p->len;
+            }
+            else
+            {
+              /* next octet in same pbuf */
+              msg_ptr++;
+            }
+          }
+          /* copy last octet */
+          *raw = *msg_ptr;
+          return ERR_OK;
+        }
+        else
+        {
+          /* raw_len < len, not enough dst space */
+          return ERR_ARG;
+        }
+      }
+      p = p->next;
+    }
+    /* p == NULL, ofs >= plen */
+    return ERR_ARG;
+  }
+  else
+  {
+    /* len == 0, empty string */
+    return ERR_OK;
+  }
+}
+
+#endif /* LWIP_SNMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/snmp/asn1_enc.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/snmp/asn1_enc.c
new file mode 100644
index 0000000..77af6b4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/snmp/asn1_enc.c
@@ -0,0 +1,611 @@
+/**
+ * @file
+ * Abstract Syntax Notation One (ISO 8824, 8825) encoding
+ *
+ * @todo not optimised (yet), favor correctness over speed, favor speed over size
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/snmp_asn1.h"
+
+/**
+ * Returns octet count for length.
+ *
+ * @param length
+ * @param octets_needed points to the return value
+ */
+void
+snmp_asn1_enc_length_cnt(u16_t length, u8_t *octets_needed)
+{
+  if (length < 0x80U)
+  {
+    *octets_needed = 1;
+  }
+  else if (length < 0x100U)
+  {
+    *octets_needed = 2;
+  }
+  else
+  {
+    *octets_needed = 3;
+  }
+}
+
+/**
+ * Returns octet count for an u32_t.
+ *
+ * @param value
+ * @param octets_needed points to the return value
+ *
+ * @note ASN coded integers are _always_ signed. E.g. +0xFFFF is coded
+ * as 0x00,0xFF,0xFF. Note the leading sign octet. A positive value
+ * of 0xFFFFFFFF is preceded with 0x00 and the length is 5 octets!!
+ */
+void
+snmp_asn1_enc_u32t_cnt(u32_t value, u16_t *octets_needed)
+{
+  if (value < 0x80UL)
+  {
+    *octets_needed = 1;
+  }
+  else if (value < 0x8000UL)
+  {
+    *octets_needed = 2;
+  }
+  else if (value < 0x800000UL)
+  {
+    *octets_needed = 3;
+  }
+  else if (value < 0x80000000UL)
+  {
+    *octets_needed = 4;
+  }
+  else
+  {
+    *octets_needed = 5;
+  }
+}
+
+/**
+ * Returns octet count for an s32_t.
+ *
+ * @param value
+ * @param octets_needed points to the return value
+ *
+ * @note ASN coded integers are _always_ signed.
+ */
+void
+snmp_asn1_enc_s32t_cnt(s32_t value, u16_t *octets_needed)
+{
+  if (value < 0)
+  {
+    value = ~value;
+  }
+  if (value < 0x80L)
+  {
+    *octets_needed = 1;
+  }
+  else if (value < 0x8000L)
+  {
+    *octets_needed = 2;
+  }
+  else if (value < 0x800000L)
+  {
+    *octets_needed = 3;
+  }
+  else
+  {
+    *octets_needed = 4;
+  }
+}
+
+/**
+ * Returns octet count for an object identifier.
+ *
+ * @param ident_len object identifier array length
+ * @param ident points to object identifier array
+ * @param octets_needed points to the return value
+ */
+void
+snmp_asn1_enc_oid_cnt(u8_t ident_len, s32_t *ident, u16_t *octets_needed)
+{
+  s32_t sub_id;
+  u8_t cnt;
+
+  cnt = 0;
+  if (ident_len > 1)
+  {
+    /* compressed prefix in one octet */
+    cnt++;
+    ident_len -= 2;
+    ident += 2;
+  }
+  while(ident_len > 0)
+  {
+    ident_len--;
+    sub_id = *ident;
+
+    sub_id >>= 7;
+    cnt++;
+    while(sub_id > 0)
+    {
+      sub_id >>= 7;
+      cnt++;
+    }
+    ident++;
+  }
+  *octets_needed = cnt;
+}
+
+/**
+ * Encodes ASN type field into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode value into
+ * @param ofs points to the offset within the pbuf chain
+ * @param type input ASN1 type
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ */
+err_t
+snmp_asn1_enc_type(struct pbuf *p, u16_t ofs, u8_t type)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+      *msg_ptr = type;
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Encodes host order length field into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode length into
+ * @param ofs points to the offset within the pbuf chain
+ * @param length is the host order length to be encoded
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ */
+err_t
+snmp_asn1_enc_length(struct pbuf *p, u16_t ofs, u16_t length)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+
+      if (length < 0x80)
+      {
+        *msg_ptr = length;
+        return ERR_OK;
+      }
+      else if (length < 0x100)
+      {
+        *msg_ptr = 0x81;
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+        *msg_ptr = length;
+        return ERR_OK;
+      }
+      else
+      {
+        u8_t i;
+
+        /* length >= 0x100 && length <= 0xFFFF */
+        *msg_ptr = 0x82;
+        i = 2;
+        while (i > 0)
+        {
+          i--;
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+          if (i == 0)
+          {
+            /* least significant length octet */
+            *msg_ptr = length;
+          }
+          else
+          {
+            /* most significant length octet */
+            *msg_ptr = length >> 8;
+          }
+        }
+        return ERR_OK;
+      }
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Encodes u32_t (counter, gauge, timeticks) into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode value into
+ * @param ofs points to the offset within the pbuf chain
+ * @param octets_needed encoding length (from snmp_asn1_enc_u32t_cnt())
+ * @param value is the host order u32_t value to be encoded
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ *
+ * @see snmp_asn1_enc_u32t_cnt()
+ */
+err_t
+snmp_asn1_enc_u32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, u32_t value)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+
+      if (octets_needed == 5)
+      {
+        /* not enough bits in 'value' add leading 0x00 */
+        octets_needed--;
+        *msg_ptr = 0x00;
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+      }
+      while (octets_needed > 1)
+      {
+        octets_needed--;
+        *msg_ptr = value >> (octets_needed << 3);
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+      }
+      /* (only) one least significant octet */
+      *msg_ptr = value;
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Encodes s32_t integer into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode value into
+ * @param ofs points to the offset within the pbuf chain
+ * @param octets_needed encoding length (from snmp_asn1_enc_s32t_cnt())
+ * @param value is the host order s32_t value to be encoded
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ *
+ * @see snmp_asn1_enc_s32t_cnt()
+ */
+err_t
+snmp_asn1_enc_s32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, s32_t value)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+
+      while (octets_needed > 1)
+      {
+        octets_needed--;
+        *msg_ptr = value >> (octets_needed << 3);
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+      }
+      /* (only) one least significant octet */
+      *msg_ptr = value;
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Encodes object identifier into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode oid into
+ * @param ofs points to the offset within the pbuf chain
+ * @param ident_len object identifier array length
+ * @param ident points to object identifier array
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ */
+err_t
+snmp_asn1_enc_oid(struct pbuf *p, u16_t ofs, u8_t ident_len, s32_t *ident)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+
+      if (ident_len > 1)
+      {
+        if ((ident[0] == 1) && (ident[1] == 3))
+        {
+          /* compressed (most common) prefix .iso.org */
+          *msg_ptr = 0x2b;
+        }
+        else
+        {
+          /* calculate prefix */
+          *msg_ptr = (ident[0] * 40) + ident[1];
+        }
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+        ident_len -= 2;
+        ident += 2;
+      }
+      else
+      {
+/* @bug:  allow empty varbinds for symmetry (we must decode them for getnext), allow partial compression??  */
+        /* ident_len <= 1, at least we need zeroDotZero (0.0) (ident_len == 2) */
+        return ERR_ARG;
+      }
+      while (ident_len > 0)
+      {
+        s32_t sub_id;
+        u8_t shift, tail;
+
+        ident_len--;
+        sub_id = *ident;
+        tail = 0;
+        shift = 28;
+        while(shift > 0)
+        {
+          u8_t code;
+
+          code = sub_id >> shift;
+          if ((code != 0) || (tail != 0))
+          {
+            tail = 1;
+            *msg_ptr = code | 0x80;
+            ofs += 1;
+            if (ofs >= plen)
+            {
+              /* next octet in next pbuf */
+              p = p->next;
+              if (p == NULL) { return ERR_ARG; }
+              msg_ptr = p->payload;
+              plen += p->len;
+            }
+            else
+            {
+              /* next octet in same pbuf */
+              msg_ptr++;
+            }
+          }
+          shift -= 7;
+        }
+        *msg_ptr = (u8_t)sub_id & 0x7F;
+        if (ident_len > 0)
+        {
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+        }
+        /* proceed to next sub-identifier */
+        ident++;
+      }
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Encodes raw data (octet string, opaque) into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode raw data into
+ * @param ofs points to the offset within the pbuf chain
+ * @param raw_len raw data length
+ * @param raw points raw data
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ */
+err_t
+snmp_asn1_enc_raw(struct pbuf *p, u16_t ofs, u8_t raw_len, u8_t *raw)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = p->payload;
+      msg_ptr += ofs - base;
+
+      while (raw_len > 1)
+      {
+        /* copy raw_len - 1 octets */
+        raw_len--;
+        *msg_ptr = *raw;
+        raw++;
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+      }
+      if (raw_len > 0)
+      {
+        /* copy last or single octet */
+        *msg_ptr = *raw;
+      }
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+#endif /* LWIP_SNMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/snmp/mib2.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/snmp/mib2.c
new file mode 100644
index 0000000..bc5830d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/snmp/mib2.c
@@ -0,0 +1,4128 @@
+/**
+ * @file
+ * Management Information Base II (RFC1213) objects and functions.
+ *
+ * @note the object identifiers for this MIB-2 and private MIB tree
+ * must be kept in sorted ascending order. This to ensure correct getnext operation.
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/snmp.h"
+#include "lwip/netif.h"
+#include "lwip/ip.h"
+#include "lwip/ip_frag.h"
+#include "lwip/tcp.h"
+#include "lwip/udp.h"
+#include "lwip/snmp_asn1.h"
+#include "lwip/snmp_structs.h"
+#include "netif/etharp.h"
+
+/**
+ * IANA assigned enterprise ID for lwIP is 26381
+ * @see http://www.iana.org/assignments/enterprise-numbers
+ *
+ * @note this enterprise ID is assigned to the lwIP project,
+ * all object identifiers living under this ID are assigned
+ * by the lwIP maintainers (contact Christiaan Simons)!
+ * @note don't change this define, use snmp_set_sysobjid()
+ *
+ * If you need to create your own private MIB you'll need
+ * to apply for your own enterprise ID with IANA:
+ * http://www.iana.org/numbers.html
+ */
+#define SNMP_ENTERPRISE_ID 26381
+#define SNMP_SYSOBJID_LEN 7
+#define SNMP_SYSOBJID {1, 3, 6, 1, 4, 1, SNMP_ENTERPRISE_ID}
+
+#ifndef SNMP_SYSSERVICES
+#define SNMP_SYSSERVICES ((1 << 6) | (1 << 3) | ((IP_FORWARD) << 2))
+#endif
+
+#ifndef SNMP_GET_SYSUPTIME
+#define SNMP_GET_SYSUPTIME(sysuptime)
+#endif
+
+static void system_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void system_get_value(struct obj_def *od, u16_t len, void *value);
+static u8_t system_set_test(struct obj_def *od, u16_t len, void *value);
+static void system_set_value(struct obj_def *od, u16_t len, void *value);
+static void interfaces_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void interfaces_get_value(struct obj_def *od, u16_t len, void *value);
+static void ifentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void ifentry_get_value(struct obj_def *od, u16_t len, void *value);
+#if !SNMP_SAFE_REQUESTS
+static u8_t ifentry_set_test (struct obj_def *od, u16_t len, void *value);
+static void ifentry_set_value (struct obj_def *od, u16_t len, void *value);
+#endif /* SNMP_SAFE_REQUESTS */
+static void atentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void atentry_get_value(struct obj_def *od, u16_t len, void *value);
+static void ip_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void ip_get_value(struct obj_def *od, u16_t len, void *value);
+static u8_t ip_set_test(struct obj_def *od, u16_t len, void *value);
+static void ip_addrentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void ip_addrentry_get_value(struct obj_def *od, u16_t len, void *value);
+static void ip_rteentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void ip_rteentry_get_value(struct obj_def *od, u16_t len, void *value);
+static void ip_ntomentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void ip_ntomentry_get_value(struct obj_def *od, u16_t len, void *value);
+static void icmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void icmp_get_value(struct obj_def *od, u16_t len, void *value);
+#if LWIP_TCP
+static void tcp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void tcp_get_value(struct obj_def *od, u16_t len, void *value);
+#ifdef THIS_SEEMS_UNUSED
+static void tcpconnentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void tcpconnentry_get_value(struct obj_def *od, u16_t len, void *value);
+#endif
+#endif
+static void udp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void udp_get_value(struct obj_def *od, u16_t len, void *value);
+static void udpentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void udpentry_get_value(struct obj_def *od, u16_t len, void *value);
+static void snmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void snmp_get_value(struct obj_def *od, u16_t len, void *value);
+static u8_t snmp_set_test(struct obj_def *od, u16_t len, void *value);
+static void snmp_set_value(struct obj_def *od, u16_t len, void *value);
+
+
+/* snmp .1.3.6.1.2.1.11 */
+const mib_scalar_node snmp_scalar = {
+  &snmp_get_object_def,
+  &snmp_get_value,
+  &snmp_set_test,
+  &snmp_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t snmp_ids[28] = {
+  1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+  17, 18, 19, 20, 21, 22, 24, 25, 26, 27, 28, 29, 30
+};
+struct mib_node* const snmp_nodes[28] = {
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar,
+  (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar
+};
+const struct mib_array_node snmp = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  28,
+  snmp_ids,
+  snmp_nodes
+};
+
+/* dot3 and EtherLike MIB not planned. (transmission .1.3.6.1.2.1.10) */
+/* historical (some say hysterical). (cmot .1.3.6.1.2.1.9) */
+/* lwIP has no EGP, thus may not implement it. (egp .1.3.6.1.2.1.8) */
+
+/* udp .1.3.6.1.2.1.7 */
+/** index root node for udpTable */
+struct mib_list_rootnode udp_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t udpentry_ids[2] = { 1, 2 };
+struct mib_node* const udpentry_nodes[2] = {
+  (struct mib_node* const)&udp_root, (struct mib_node* const)&udp_root,
+};
+const struct mib_array_node udpentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  2,
+  udpentry_ids,
+  udpentry_nodes
+};
+
+s32_t udptable_id = 1;
+struct mib_node* udptable_node = (struct mib_node* const)&udpentry;
+struct mib_ram_array_node udptable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &udptable_id,
+  &udptable_node
+};
+
+const mib_scalar_node udp_scalar = {
+  &udp_get_object_def,
+  &udp_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t udp_ids[5] = { 1, 2, 3, 4, 5 };
+struct mib_node* const udp_nodes[5] = {
+  (struct mib_node* const)&udp_scalar, (struct mib_node* const)&udp_scalar,
+  (struct mib_node* const)&udp_scalar, (struct mib_node* const)&udp_scalar,
+  (struct mib_node* const)&udptable
+};
+const struct mib_array_node udp = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  5,
+  udp_ids,
+  udp_nodes
+};
+
+/* tcp .1.3.6.1.2.1.6 */
+#if LWIP_TCP
+/* only if the TCP protocol is available may implement this group */
+/** index root node for tcpConnTable */
+struct mib_list_rootnode tcpconntree_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t tcpconnentry_ids[5] = { 1, 2, 3, 4, 5 };
+struct mib_node* const tcpconnentry_nodes[5] = {
+  (struct mib_node* const)&tcpconntree_root, (struct mib_node* const)&tcpconntree_root,
+  (struct mib_node* const)&tcpconntree_root, (struct mib_node* const)&tcpconntree_root,
+  (struct mib_node* const)&tcpconntree_root
+};
+const struct mib_array_node tcpconnentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  5,
+  tcpconnentry_ids,
+  tcpconnentry_nodes
+};
+
+s32_t tcpconntable_id = 1;
+struct mib_node* tcpconntable_node = (struct mib_node* const)&tcpconnentry;
+struct mib_ram_array_node tcpconntable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+/** @todo update maxlength when inserting / deleting from table
+   0 when table is empty, 1 when more than one entry */
+  0,
+  &tcpconntable_id,
+  &tcpconntable_node
+};
+
+const mib_scalar_node tcp_scalar = {
+  &tcp_get_object_def,
+  &tcp_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t tcp_ids[15] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
+struct mib_node* const tcp_nodes[15] = {
+  (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar,
+  (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar,
+  (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar,
+  (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar,
+  (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar,
+  (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar,
+  (struct mib_node* const)&tcpconntable, (struct mib_node* const)&tcp_scalar,
+  (struct mib_node* const)&tcp_scalar
+};
+const struct mib_array_node tcp = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  15,
+  tcp_ids,
+  tcp_nodes
+};
+#endif
+
+/* icmp .1.3.6.1.2.1.5 */
+const mib_scalar_node icmp_scalar = {
+  &icmp_get_object_def,
+  &icmp_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t icmp_ids[26] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 };
+struct mib_node* const icmp_nodes[26] = {
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar,
+  (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar
+};
+const struct mib_array_node icmp = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  26,
+  icmp_ids,
+  icmp_nodes
+};
+
+/** index root node for ipNetToMediaTable */
+struct mib_list_rootnode ipntomtree_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t ipntomentry_ids[4] = { 1, 2, 3, 4 };
+struct mib_node* const ipntomentry_nodes[4] = {
+  (struct mib_node* const)&ipntomtree_root, (struct mib_node* const)&ipntomtree_root,
+  (struct mib_node* const)&ipntomtree_root, (struct mib_node* const)&ipntomtree_root
+};
+const struct mib_array_node ipntomentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  4,
+  ipntomentry_ids,
+  ipntomentry_nodes
+};
+
+s32_t ipntomtable_id = 1;
+struct mib_node* ipntomtable_node = (struct mib_node* const)&ipntomentry;
+struct mib_ram_array_node ipntomtable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &ipntomtable_id,
+  &ipntomtable_node
+};
+
+/** index root node for ipRouteTable */
+struct mib_list_rootnode iprtetree_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t iprteentry_ids[13] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 };
+struct mib_node* const iprteentry_nodes[13] = {
+  (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root,
+  (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root,
+  (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root,
+  (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root,
+  (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root,
+  (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root,
+  (struct mib_node* const)&iprtetree_root
+};
+const struct mib_array_node iprteentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  13,
+  iprteentry_ids,
+  iprteentry_nodes
+};
+
+s32_t iprtetable_id = 1;
+struct mib_node* iprtetable_node = (struct mib_node* const)&iprteentry;
+struct mib_ram_array_node iprtetable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &iprtetable_id,
+  &iprtetable_node
+};
+
+/** index root node for ipAddrTable */
+struct mib_list_rootnode ipaddrtree_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t ipaddrentry_ids[5] = { 1, 2, 3, 4, 5 };
+struct mib_node* const ipaddrentry_nodes[5] = {
+  (struct mib_node* const)&ipaddrtree_root,
+  (struct mib_node* const)&ipaddrtree_root,
+  (struct mib_node* const)&ipaddrtree_root,
+  (struct mib_node* const)&ipaddrtree_root,
+  (struct mib_node* const)&ipaddrtree_root
+};
+const struct mib_array_node ipaddrentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  5,
+  ipaddrentry_ids,
+  ipaddrentry_nodes
+};
+
+s32_t ipaddrtable_id = 1;
+struct mib_node* ipaddrtable_node = (struct mib_node* const)&ipaddrentry;
+struct mib_ram_array_node ipaddrtable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &ipaddrtable_id,
+  &ipaddrtable_node
+};
+
+/* ip .1.3.6.1.2.1.4 */
+const mib_scalar_node ip_scalar = {
+  &ip_get_object_def,
+  &ip_get_value,
+  &ip_set_test,
+  &noleafs_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t ip_ids[23] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 };
+struct mib_node* const ip_nodes[23] = {
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar,
+  (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ipaddrtable,
+  (struct mib_node* const)&iprtetable, (struct mib_node* const)&ipntomtable,
+  (struct mib_node* const)&ip_scalar
+};
+const struct mib_array_node mib2_ip = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  23,
+  ip_ids,
+  ip_nodes
+};
+
+/** index root node for atTable */
+struct mib_list_rootnode arptree_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t atentry_ids[3] = { 1, 2, 3 };
+struct mib_node* const atentry_nodes[3] = {
+  (struct mib_node* const)&arptree_root,
+  (struct mib_node* const)&arptree_root,
+  (struct mib_node* const)&arptree_root
+};
+const struct mib_array_node atentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  3,
+  atentry_ids,
+  atentry_nodes
+};
+
+const s32_t attable_id = 1;
+struct mib_node* const attable_node = (struct mib_node* const)&atentry;
+const struct mib_array_node attable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  1,
+  &attable_id,
+  &attable_node
+};
+
+/* at .1.3.6.1.2.1.3 */
+s32_t at_id = 1;
+struct mib_node* mib2_at_node = (struct mib_node* const)&attable;
+struct mib_ram_array_node at = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &at_id,
+  &mib2_at_node
+};
+
+/** index root node for ifTable */
+struct mib_list_rootnode iflist_root = {
+  &ifentry_get_object_def,
+  &ifentry_get_value,
+#if SNMP_SAFE_REQUESTS
+  &noleafs_set_test,
+  &noleafs_set_value,
+#else /* SNMP_SAFE_REQUESTS */
+  &ifentry_set_test,
+  &ifentry_set_value,
+#endif /* SNMP_SAFE_REQUESTS */
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t ifentry_ids[22] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 };
+struct mib_node* const ifentry_nodes[22] = {
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root,
+  (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root
+};
+const struct mib_array_node ifentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  22,
+  ifentry_ids,
+  ifentry_nodes
+};
+
+s32_t iftable_id = 1;
+struct mib_node* iftable_node = (struct mib_node* const)&ifentry;
+struct mib_ram_array_node iftable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &iftable_id,
+  &iftable_node
+};
+
+/* interfaces .1.3.6.1.2.1.2 */
+const mib_scalar_node interfaces_scalar = {
+  &interfaces_get_object_def,
+  &interfaces_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t interfaces_ids[2] = { 1, 2 };
+struct mib_node* const interfaces_nodes[2] = {
+  (struct mib_node* const)&interfaces_scalar, (struct mib_node* const)&iftable
+};
+const struct mib_array_node interfaces = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  2,
+  interfaces_ids,
+  interfaces_nodes
+};
+
+
+/*             0 1 2 3 4 5 6 */
+/* system .1.3.6.1.2.1.1 */
+const mib_scalar_node sys_tem_scalar = {
+  &system_get_object_def,
+  &system_get_value,
+  &system_set_test,
+  &system_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t sys_tem_ids[7] = { 1, 2, 3, 4, 5, 6, 7 };
+struct mib_node* const sys_tem_nodes[7] = {
+  (struct mib_node* const)&sys_tem_scalar, (struct mib_node* const)&sys_tem_scalar,
+  (struct mib_node* const)&sys_tem_scalar, (struct mib_node* const)&sys_tem_scalar,
+  (struct mib_node* const)&sys_tem_scalar, (struct mib_node* const)&sys_tem_scalar,
+  (struct mib_node* const)&sys_tem_scalar
+};
+/* work around name issue with 'sys_tem', some compiler(s?) seem to reserve 'system' */
+const struct mib_array_node sys_tem = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  7,
+  sys_tem_ids,
+  sys_tem_nodes
+};
+
+/* mib-2 .1.3.6.1.2.1 */
+#if LWIP_TCP
+#define MIB2_GROUPS 8
+#else
+#define MIB2_GROUPS 7
+#endif
+const s32_t mib2_ids[MIB2_GROUPS] =
+{
+  1,
+  2,
+  3,
+  4,
+  5,
+#if LWIP_TCP
+  6,
+#endif
+  7,
+  11
+};
+struct mib_node* const mib2_nodes[MIB2_GROUPS] = {
+  (struct mib_node* const)&sys_tem,
+  (struct mib_node* const)&interfaces,
+  (struct mib_node* const)&at,
+  (struct mib_node* const)&mib2_ip,
+  (struct mib_node* const)&icmp,
+#if LWIP_TCP
+  (struct mib_node* const)&tcp,
+#endif
+  (struct mib_node* const)&udp,
+  (struct mib_node* const)&snmp
+};
+
+const struct mib_array_node mib2 = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  MIB2_GROUPS,
+  mib2_ids,
+  mib2_nodes
+};
+
+/* mgmt .1.3.6.1.2 */
+const s32_t mgmt_ids[1] = { 1 };
+struct mib_node* const mgmt_nodes[1] = { (struct mib_node* const)&mib2 };
+const struct mib_array_node mgmt = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  1,
+  mgmt_ids,
+  mgmt_nodes
+};
+
+/* internet .1.3.6.1 */
+#if SNMP_PRIVATE_MIB
+s32_t internet_ids[2] = { 2, 4 };
+struct mib_node* const internet_nodes[2] = { (struct mib_node* const)&mgmt, (struct mib_node* const)&private };
+const struct mib_array_node internet = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  2,
+  internet_ids,
+  internet_nodes
+};
+#else
+const s32_t internet_ids[1] = { 2 };
+struct mib_node* const internet_nodes[1] = { (struct mib_node* const)&mgmt };
+const struct mib_array_node internet = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  1,
+  internet_ids,
+  internet_nodes
+};
+#endif
+
+/** mib-2.system.sysObjectID  */
+static struct snmp_obj_id sysobjid = {SNMP_SYSOBJID_LEN, SNMP_SYSOBJID};
+/** enterprise ID for generic TRAPs, .iso.org.dod.internet.mgmt.mib-2.snmp */
+static struct snmp_obj_id snmpgrp_id = {7,{1,3,6,1,2,1,11}};
+/** mib-2.system.sysServices */
+static const s32_t sysservices = SNMP_SYSSERVICES;
+
+/** mib-2.system.sysDescr */
+static const u8_t sysdescr_len_default = 4;
+static const u8_t sysdescr_default[] = "lwIP";
+static u8_t* sysdescr_len_ptr = (u8_t*)&sysdescr_len_default;
+static u8_t* sysdescr_ptr = (u8_t*)&sysdescr_default[0];
+/** mib-2.system.sysContact */
+static const u8_t syscontact_len_default = 0;
+static const u8_t syscontact_default[] = "";
+static u8_t* syscontact_len_ptr = (u8_t*)&syscontact_len_default;
+static u8_t* syscontact_ptr = (u8_t*)&syscontact_default[0];
+/** mib-2.system.sysName */
+static const u8_t sysname_len_default = 8;
+static const u8_t sysname_default[] = "FQDN-unk";
+static u8_t* sysname_len_ptr = (u8_t*)&sysname_len_default;
+static u8_t* sysname_ptr = (u8_t*)&sysname_default[0];
+/** mib-2.system.sysLocation */
+static const u8_t syslocation_len_default = 0;
+static const u8_t syslocation_default[] = "";
+static u8_t* syslocation_len_ptr = (u8_t*)&syslocation_len_default;
+static u8_t* syslocation_ptr = (u8_t*)&syslocation_default[0];
+/** mib-2.snmp.snmpEnableAuthenTraps */
+static const u8_t snmpenableauthentraps_default = 2; /* disabled */
+static u8_t* snmpenableauthentraps_ptr = (u8_t*)&snmpenableauthentraps_default;
+
+/** mib-2.interfaces.ifTable.ifEntry.ifSpecific (zeroDotZero) */
+static const struct snmp_obj_id ifspecific = {2, {0, 0}};
+/** mib-2.ip.ipRouteTable.ipRouteEntry.ipRouteInfo (zeroDotZero) */
+static const struct snmp_obj_id iprouteinfo = {2, {0, 0}};
+
+
+
+/* mib-2.system counter(s) */
+static u32_t sysuptime = 0;
+
+/* mib-2.ip counter(s) */
+static u32_t ipinreceives = 0,
+             ipinhdrerrors = 0,
+             ipinaddrerrors = 0,
+             ipforwdatagrams = 0,
+             ipinunknownprotos = 0,
+             ipindiscards = 0,
+             ipindelivers = 0,
+             ipoutrequests = 0,
+             ipoutdiscards = 0,
+             ipoutnoroutes = 0,
+             ipreasmreqds = 0,
+             ipreasmoks = 0,
+             ipreasmfails = 0,
+             ipfragoks = 0,
+             ipfragfails = 0,
+             ipfragcreates = 0,
+             iproutingdiscards = 0;
+/* mib-2.icmp counter(s) */
+static u32_t icmpinmsgs = 0,
+             icmpinerrors = 0,
+             icmpindestunreachs = 0,
+             icmpintimeexcds = 0,
+             icmpinparmprobs = 0,
+             icmpinsrcquenchs = 0,
+             icmpinredirects = 0,
+             icmpinechos = 0,
+             icmpinechoreps = 0,
+             icmpintimestamps = 0,
+             icmpintimestampreps = 0,
+             icmpinaddrmasks = 0,
+             icmpinaddrmaskreps = 0,
+             icmpoutmsgs = 0,
+             icmpouterrors = 0,
+             icmpoutdestunreachs = 0,
+             icmpouttimeexcds = 0,
+             icmpoutparmprobs = 0,
+             icmpoutsrcquenchs = 0,
+             icmpoutredirects = 0,
+             icmpoutechos = 0,
+             icmpoutechoreps = 0,
+             icmpouttimestamps = 0,
+             icmpouttimestampreps = 0,
+             icmpoutaddrmasks = 0,
+             icmpoutaddrmaskreps = 0;
+/* mib-2.tcp counter(s) */
+static u32_t tcpactiveopens = 0,
+             tcppassiveopens = 0,
+             tcpattemptfails = 0,
+             tcpestabresets = 0,
+             tcpinsegs = 0,
+             tcpoutsegs = 0,
+             tcpretranssegs = 0,
+             tcpinerrs = 0,
+             tcpoutrsts = 0;
+/* mib-2.udp counter(s) */
+static u32_t udpindatagrams = 0,
+             udpnoports = 0,
+             udpinerrors = 0,
+             udpoutdatagrams = 0;
+/* mib-2.snmp counter(s) */
+static u32_t snmpinpkts = 0,
+             snmpoutpkts = 0,
+             snmpinbadversions = 0,
+             snmpinbadcommunitynames = 0,
+             snmpinbadcommunityuses = 0,
+             snmpinasnparseerrs = 0,
+             snmpintoobigs = 0,
+             snmpinnosuchnames = 0,
+             snmpinbadvalues = 0,
+             snmpinreadonlys = 0,
+             snmpingenerrs = 0,
+             snmpintotalreqvars = 0,
+             snmpintotalsetvars = 0,
+             snmpingetrequests = 0,
+             snmpingetnexts = 0,
+             snmpinsetrequests = 0,
+             snmpingetresponses = 0,
+             snmpintraps = 0,
+             snmpouttoobigs = 0,
+             snmpoutnosuchnames = 0,
+             snmpoutbadvalues = 0,
+             snmpoutgenerrs = 0,
+             snmpoutgetrequests = 0,
+             snmpoutgetnexts = 0,
+             snmpoutsetrequests = 0,
+             snmpoutgetresponses = 0,
+             snmpouttraps = 0;
+
+
+
+/* prototypes of the following functions are in lwip/src/include/lwip/snmp.h */
+/**
+ * Copy octet string.
+ *
+ * @param dst points to destination
+ * @param src points to source
+ * @param n number of octets to copy.
+ */
+void ocstrncpy(u8_t *dst, u8_t *src, u8_t n)
+{
+  while (n > 0)
+  {
+    n--;
+    *dst++ = *src++;
+  }
+}
+
+/**
+ * Copy object identifier (s32_t) array.
+ *
+ * @param dst points to destination
+ * @param src points to source
+ * @param n number of sub identifiers to copy.
+ */
+void objectidncpy(s32_t *dst, s32_t *src, u8_t n)
+{
+  while(n > 0)
+  {
+    n--;
+    *dst++ = *src++;
+  }
+}
+
+/**
+ * Initializes sysDescr pointers.
+ *
+ * @param str if non-NULL then copy str pointer
+ * @param len points to string length, excluding zero terminator
+ */
+void snmp_set_sysdesr(u8_t *str, u8_t *len)
+{
+  if (str != NULL)
+  {
+    sysdescr_ptr = str;
+    sysdescr_len_ptr = len;
+  }
+}
+
+void snmp_get_sysobjid_ptr(struct snmp_obj_id **oid)
+{
+  *oid = &sysobjid;
+}
+
+/**
+ * Initializes sysObjectID value.
+ *
+ * @param oid points to stuct snmp_obj_id to copy
+ */
+void snmp_set_sysobjid(struct snmp_obj_id *oid)
+{
+  sysobjid = *oid;
+}
+
+/**
+ * Must be called at regular 10 msec interval from a timer interrupt
+ * or signal handler depending on your runtime environment.
+ */
+void snmp_inc_sysuptime(void)
+{
+  sysuptime++;
+}
+
+void snmp_add_sysuptime(u32_t value)
+{
+  sysuptime+=value;
+}
+
+void snmp_get_sysuptime(u32_t *value)
+{
+  SNMP_GET_SYSUPTIME(sysuptime);
+  *value = sysuptime;
+}
+
+/**
+ * Initializes sysContact pointers,
+ * e.g. ptrs to non-volatile memory external to lwIP.
+ *
+ * @param ocstr if non-NULL then copy str pointer
+ * @param ocstrlen points to string length, excluding zero terminator
+ */
+void snmp_set_syscontact(u8_t *ocstr, u8_t *ocstrlen)
+{
+  if (ocstr != NULL)
+  {
+    syscontact_ptr = ocstr;
+    syscontact_len_ptr = ocstrlen;
+  }
+}
+
+/**
+ * Initializes sysName pointers,
+ * e.g. ptrs to non-volatile memory external to lwIP.
+ *
+ * @param ocstr if non-NULL then copy str pointer
+ * @param ocstrlen points to string length, excluding zero terminator
+ */
+void snmp_set_sysname(u8_t *ocstr, u8_t *ocstrlen)
+{
+  if (ocstr != NULL)
+  {
+    sysname_ptr = ocstr;
+    sysname_len_ptr = ocstrlen;
+  }
+}
+
+/**
+ * Initializes sysLocation pointers,
+ * e.g. ptrs to non-volatile memory external to lwIP.
+ *
+ * @param ocstr if non-NULL then copy str pointer
+ * @param ocstrlen points to string length, excluding zero terminator
+ */
+void snmp_set_syslocation(u8_t *ocstr, u8_t *ocstrlen)
+{
+  if (ocstr != NULL)
+  {
+    syslocation_ptr = ocstr;
+    syslocation_len_ptr = ocstrlen;
+  }
+}
+
+
+void snmp_add_ifinoctets(struct netif *ni, u32_t value)
+{
+  ni->ifinoctets += value;
+}
+
+void snmp_inc_ifinucastpkts(struct netif *ni)
+{
+  (ni->ifinucastpkts)++;
+}
+
+void snmp_inc_ifinnucastpkts(struct netif *ni)
+{
+  (ni->ifinnucastpkts)++;
+}
+
+void snmp_inc_ifindiscards(struct netif *ni)
+{
+  (ni->ifindiscards)++;
+}
+
+void snmp_add_ifoutoctets(struct netif *ni, u32_t value)
+{
+  ni->ifoutoctets += value;
+}
+
+void snmp_inc_ifoutucastpkts(struct netif *ni)
+{
+  (ni->ifoutucastpkts)++;
+}
+
+void snmp_inc_ifoutnucastpkts(struct netif *ni)
+{
+  (ni->ifoutnucastpkts)++;
+}
+
+void snmp_inc_ifoutdiscards(struct netif *ni)
+{
+  (ni->ifoutdiscards)++;
+}
+
+void snmp_inc_iflist(void)
+{
+  struct mib_list_node *if_node = NULL;
+
+  snmp_mib_node_insert(&iflist_root, iflist_root.count + 1, &if_node);
+  /* enable getnext traversal on filled table */
+  iftable.maxlength = 1;
+}
+
+void snmp_dec_iflist(void)
+{
+  snmp_mib_node_delete(&iflist_root, iflist_root.tail);
+  /* disable getnext traversal on empty table */
+  if(iflist_root.count == 0) iftable.maxlength = 0;
+}
+
+/**
+ * Inserts ARP table indexes (.xIfIndex.xNetAddress)
+ * into arp table index trees (both atTable and ipNetToMediaTable).
+ */
+void snmp_insert_arpidx_tree(struct netif *ni, struct ip_addr *ip)
+{
+  struct mib_list_rootnode *at_rn;
+  struct mib_list_node *at_node;
+  struct ip_addr hip;
+  s32_t arpidx[5];
+  u8_t level, tree;
+
+  LWIP_ASSERT("ni != NULL", ni != NULL);
+  snmp_netiftoifindex(ni, &arpidx[0]);
+  hip.addr = ntohl(ip->addr);
+  snmp_iptooid(&hip, &arpidx[1]);
+
+  for (tree = 0; tree < 2; tree++)
+  {
+    if (tree == 0)
+    {
+      at_rn = &arptree_root;
+    }
+    else
+    {
+      at_rn = &ipntomtree_root;
+    }
+    for (level = 0; level < 5; level++)
+    {
+      at_node = NULL;
+      snmp_mib_node_insert(at_rn, arpidx[level], &at_node);
+      if ((level != 4) && (at_node != NULL))
+      {
+        if (at_node->nptr == NULL)
+        {
+          at_rn = snmp_mib_lrn_alloc();
+          at_node->nptr = (struct mib_node*)at_rn;
+          if (at_rn != NULL)
+          {
+            if (level == 3)
+            {
+              if (tree == 0)
+              {
+                at_rn->get_object_def = atentry_get_object_def;
+                at_rn->get_value = atentry_get_value;
+              }
+              else
+              {
+                at_rn->get_object_def = ip_ntomentry_get_object_def;
+                at_rn->get_value = ip_ntomentry_get_value;
+              }
+              at_rn->set_test = noleafs_set_test;
+              at_rn->set_value = noleafs_set_value;
+            }
+          }
+          else
+          {
+            /* at_rn == NULL, malloc failure */
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_arpidx_tree() insert failed, mem full"));
+            break;
+          }
+        }
+        else
+        {
+          at_rn = (struct mib_list_rootnode*)at_node->nptr;
+        }
+      }
+    }
+  }
+  /* enable getnext traversal on filled tables */
+  at.maxlength = 1;
+  ipntomtable.maxlength = 1;
+}
+
+/**
+ * Removes ARP table indexes (.xIfIndex.xNetAddress)
+ * from arp table index trees.
+ */
+void snmp_delete_arpidx_tree(struct netif *ni, struct ip_addr *ip)
+{
+  struct mib_list_rootnode *at_rn, *next, *del_rn[5];
+  struct mib_list_node *at_n, *del_n[5];
+  struct ip_addr hip;
+  s32_t arpidx[5];
+  u8_t fc, tree, level, del_cnt;
+
+  snmp_netiftoifindex(ni, &arpidx[0]);
+  hip.addr = ntohl(ip->addr);
+  snmp_iptooid(&hip, &arpidx[1]);
+
+  for (tree = 0; tree < 2; tree++)
+  {
+    /* mark nodes for deletion */
+    if (tree == 0)
+    {
+      at_rn = &arptree_root;
+    }
+    else
+    {
+      at_rn = &ipntomtree_root;
+    }
+    level = 0;
+    del_cnt = 0;
+    while ((level < 5) && (at_rn != NULL))
+    {
+      fc = snmp_mib_node_find(at_rn, arpidx[level], &at_n);
+      if (fc == 0)
+      {
+        /* arpidx[level] does not exist */
+        del_cnt = 0;
+        at_rn = NULL;
+      }
+      else if (fc == 1)
+      {
+        del_rn[del_cnt] = at_rn;
+        del_n[del_cnt] = at_n;
+        del_cnt++;
+        at_rn = (struct mib_list_rootnode*)(at_n->nptr);
+      }
+      else if (fc == 2)
+      {
+        /* reset delete (2 or more childs) */
+        del_cnt = 0;
+        at_rn = (struct mib_list_rootnode*)(at_n->nptr);
+      }
+      level++;
+    }
+    /* delete marked index nodes */
+    while (del_cnt > 0)
+    {
+      del_cnt--;
+
+      at_rn = del_rn[del_cnt];
+      at_n = del_n[del_cnt];
+
+      next = snmp_mib_node_delete(at_rn, at_n);
+      if (next != NULL)
+      {
+        LWIP_ASSERT("next_count == 0",next->count == 0);
+        snmp_mib_lrn_free(next);
+      }
+    }
+  }
+  /* disable getnext traversal on empty tables */
+  if(arptree_root.count == 0) at.maxlength = 0;
+  if(ipntomtree_root.count == 0) ipntomtable.maxlength = 0;
+}
+
+void snmp_inc_ipinreceives(void)
+{
+  ipinreceives++;
+}
+
+void snmp_inc_ipinhdrerrors(void)
+{
+  ipinhdrerrors++;
+}
+
+void snmp_inc_ipinaddrerrors(void)
+{
+  ipinaddrerrors++;
+}
+
+void snmp_inc_ipforwdatagrams(void)
+{
+  ipforwdatagrams++;
+}
+
+void snmp_inc_ipinunknownprotos(void)
+{
+  ipinunknownprotos++;
+}
+
+void snmp_inc_ipindiscards(void)
+{
+  ipindiscards++;
+}
+
+void snmp_inc_ipindelivers(void)
+{
+  ipindelivers++;
+}
+
+void snmp_inc_ipoutrequests(void)
+{
+  ipoutrequests++;
+}
+
+void snmp_inc_ipoutdiscards(void)
+{
+  ipoutdiscards++;
+}
+
+void snmp_inc_ipoutnoroutes(void)
+{
+  ipoutnoroutes++;
+}
+
+void snmp_inc_ipreasmreqds(void)
+{
+  ipreasmreqds++;
+}
+
+void snmp_inc_ipreasmoks(void)
+{
+  ipreasmoks++;
+}
+
+void snmp_inc_ipreasmfails(void)
+{
+  ipreasmfails++;
+}
+
+void snmp_inc_ipfragoks(void)
+{
+  ipfragoks++;
+}
+
+void snmp_inc_ipfragfails(void)
+{
+  ipfragfails++;
+}
+
+void snmp_inc_ipfragcreates(void)
+{
+  ipfragcreates++;
+}
+
+void snmp_inc_iproutingdiscards(void)
+{
+  iproutingdiscards++;
+}
+
+/**
+ * Inserts ipAddrTable indexes (.ipAdEntAddr)
+ * into index tree.
+ */
+void snmp_insert_ipaddridx_tree(struct netif *ni)
+{
+  struct mib_list_rootnode *ipa_rn;
+  struct mib_list_node *ipa_node;
+  struct ip_addr ip;
+  s32_t ipaddridx[4];
+  u8_t level;
+
+  LWIP_ASSERT("ni != NULL", ni != NULL);
+  ip.addr = ntohl(ni->ip_addr.addr);
+  snmp_iptooid(&ip, &ipaddridx[0]);
+
+  level = 0;
+  ipa_rn = &ipaddrtree_root;
+  while (level < 4)
+  {
+    ipa_node = NULL;
+    snmp_mib_node_insert(ipa_rn, ipaddridx[level], &ipa_node);
+    if ((level != 3) && (ipa_node != NULL))
+    {
+      if (ipa_node->nptr == NULL)
+      {
+        ipa_rn = snmp_mib_lrn_alloc();
+        ipa_node->nptr = (struct mib_node*)ipa_rn;
+        if (ipa_rn != NULL)
+        {
+          if (level == 2)
+          {
+            ipa_rn->get_object_def = ip_addrentry_get_object_def;
+            ipa_rn->get_value = ip_addrentry_get_value;
+            ipa_rn->set_test = noleafs_set_test;
+            ipa_rn->set_value = noleafs_set_value;
+          }
+        }
+        else
+        {
+          /* ipa_rn == NULL, malloc failure */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_ipaddridx_tree() insert failed, mem full"));
+          break;
+        }
+      }
+      else
+      {
+        ipa_rn = (struct mib_list_rootnode*)ipa_node->nptr;
+      }
+    }
+    level++;
+  }
+  /* enable getnext traversal on filled table */
+  ipaddrtable.maxlength = 1;
+}
+
+/**
+ * Removes ipAddrTable indexes (.ipAdEntAddr)
+ * from index tree.
+ */
+void snmp_delete_ipaddridx_tree(struct netif *ni)
+{
+  struct mib_list_rootnode *ipa_rn, *next, *del_rn[4];
+  struct mib_list_node *ipa_n, *del_n[4];
+  struct ip_addr ip;
+  s32_t ipaddridx[4];
+  u8_t fc, level, del_cnt;
+
+  LWIP_ASSERT("ni != NULL", ni != NULL);
+  ip.addr = ntohl(ni->ip_addr.addr);
+  snmp_iptooid(&ip, &ipaddridx[0]);
+
+  /* mark nodes for deletion */
+  level = 0;
+  del_cnt = 0;
+  ipa_rn = &ipaddrtree_root;
+  while ((level < 4) && (ipa_rn != NULL))
+  {
+    fc = snmp_mib_node_find(ipa_rn, ipaddridx[level], &ipa_n);
+    if (fc == 0)
+    {
+      /* ipaddridx[level] does not exist */
+      del_cnt = 0;
+      ipa_rn = NULL;
+    }
+    else if (fc == 1)
+    {
+      del_rn[del_cnt] = ipa_rn;
+      del_n[del_cnt] = ipa_n;
+      del_cnt++;
+      ipa_rn = (struct mib_list_rootnode*)(ipa_n->nptr);
+    }
+    else if (fc == 2)
+    {
+      /* reset delete (2 or more childs) */
+      del_cnt = 0;
+      ipa_rn = (struct mib_list_rootnode*)(ipa_n->nptr);
+    }
+    level++;
+  }
+  /* delete marked index nodes */
+  while (del_cnt > 0)
+  {
+    del_cnt--;
+
+    ipa_rn = del_rn[del_cnt];
+    ipa_n = del_n[del_cnt];
+
+    next = snmp_mib_node_delete(ipa_rn, ipa_n);
+    if (next != NULL)
+    {
+      LWIP_ASSERT("next_count == 0",next->count == 0);
+      snmp_mib_lrn_free(next);
+    }
+  }
+  /* disable getnext traversal on empty table */
+  if (ipaddrtree_root.count == 0) ipaddrtable.maxlength = 0;
+}
+
+/**
+ * Inserts ipRouteTable indexes (.ipRouteDest)
+ * into index tree.
+ *
+ * @param dflt non-zero for the default rte, zero for network rte
+ * @param ni points to network interface for this rte
+ *
+ * @todo record sysuptime for _this_ route when it is installed
+ *   (needed for ipRouteAge) in the netif.
+ */
+void snmp_insert_iprteidx_tree(u8_t dflt, struct netif *ni)
+{
+  u8_t insert = 0;
+  struct ip_addr dst;
+
+  if (dflt != 0)
+  {
+    /* the default route 0.0.0.0 */
+    dst.addr = 0;
+    insert = 1;
+  }
+  else
+  {
+    /* route to the network address */
+    dst.addr = ntohl(ni->ip_addr.addr & ni->netmask.addr);
+    /* exclude 0.0.0.0 network (reserved for default rte) */
+    if (dst.addr != 0) insert = 1;
+  }
+  if (insert)
+  {
+    struct mib_list_rootnode *iprte_rn;
+    struct mib_list_node *iprte_node;
+    s32_t iprteidx[4];
+    u8_t level;
+
+    snmp_iptooid(&dst, &iprteidx[0]);
+    level = 0;
+    iprte_rn = &iprtetree_root;
+    while (level < 4)
+    {
+      iprte_node = NULL;
+      snmp_mib_node_insert(iprte_rn, iprteidx[level], &iprte_node);
+      if ((level != 3) && (iprte_node != NULL))
+      {
+        if (iprte_node->nptr == NULL)
+        {
+          iprte_rn = snmp_mib_lrn_alloc();
+          iprte_node->nptr = (struct mib_node*)iprte_rn;
+          if (iprte_rn != NULL)
+          {
+            if (level == 2)
+            {
+              iprte_rn->get_object_def = ip_rteentry_get_object_def;
+              iprte_rn->get_value = ip_rteentry_get_value;
+              iprte_rn->set_test = noleafs_set_test;
+              iprte_rn->set_value = noleafs_set_value;
+            }
+          }
+          else
+          {
+            /* iprte_rn == NULL, malloc failure */
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_iprteidx_tree() insert failed, mem full"));
+            break;
+          }
+        }
+        else
+        {
+          iprte_rn = (struct mib_list_rootnode*)iprte_node->nptr;
+        }
+      }
+      level++;
+    }
+  }
+  /* enable getnext traversal on filled table */
+  iprtetable.maxlength = 1;
+}
+
+/**
+ * Removes ipRouteTable indexes (.ipRouteDest)
+ * from index tree.
+ *
+ * @param dflt non-zero for the default rte, zero for network rte
+ * @param ni points to network interface for this rte or NULL
+ *   for default route to be removed.
+ */
+void snmp_delete_iprteidx_tree(u8_t dflt, struct netif *ni)
+{
+  u8_t delete = 0;
+  struct ip_addr dst;
+
+  if (dflt != 0)
+  {
+    /* the default route 0.0.0.0 */
+    dst.addr = 0;
+    delete = 1;
+  }
+  else
+  {
+    /* route to the network address */
+    dst.addr = ntohl(ni->ip_addr.addr & ni->netmask.addr);
+    /* exclude 0.0.0.0 network (reserved for default rte) */
+    if (dst.addr != 0) delete = 1;
+  }
+  if (delete)
+  {
+    struct mib_list_rootnode *iprte_rn, *next, *del_rn[4];
+    struct mib_list_node *iprte_n, *del_n[4];
+    s32_t iprteidx[4];
+    u8_t fc, level, del_cnt;
+
+    snmp_iptooid(&dst, &iprteidx[0]);
+    /* mark nodes for deletion */
+    level = 0;
+    del_cnt = 0;
+    iprte_rn = &iprtetree_root;
+    while ((level < 4) && (iprte_rn != NULL))
+    {
+      fc = snmp_mib_node_find(iprte_rn, iprteidx[level], &iprte_n);
+      if (fc == 0)
+      {
+        /* iprteidx[level] does not exist */
+        del_cnt = 0;
+        iprte_rn = NULL;
+      }
+      else if (fc == 1)
+      {
+        del_rn[del_cnt] = iprte_rn;
+        del_n[del_cnt] = iprte_n;
+        del_cnt++;
+        iprte_rn = (struct mib_list_rootnode*)(iprte_n->nptr);
+      }
+      else if (fc == 2)
+      {
+        /* reset delete (2 or more childs) */
+        del_cnt = 0;
+        iprte_rn = (struct mib_list_rootnode*)(iprte_n->nptr);
+      }
+      level++;
+    }
+    /* delete marked index nodes */
+    while (del_cnt > 0)
+    {
+      del_cnt--;
+
+      iprte_rn = del_rn[del_cnt];
+      iprte_n = del_n[del_cnt];
+
+      next = snmp_mib_node_delete(iprte_rn, iprte_n);
+      if (next != NULL)
+      {
+        LWIP_ASSERT("next_count == 0",next->count == 0);
+        snmp_mib_lrn_free(next);
+      }
+    }
+  }
+  /* disable getnext traversal on empty table */
+  if (iprtetree_root.count == 0) iprtetable.maxlength = 0;
+}
+
+
+void snmp_inc_icmpinmsgs(void)
+{
+  icmpinmsgs++;
+}
+
+void snmp_inc_icmpinerrors(void)
+{
+  icmpinerrors++;
+}
+
+void snmp_inc_icmpindestunreachs(void)
+{
+  icmpindestunreachs++;
+}
+
+void snmp_inc_icmpintimeexcds(void)
+{
+  icmpintimeexcds++;
+}
+
+void snmp_inc_icmpinparmprobs(void)
+{
+  icmpinparmprobs++;
+}
+
+void snmp_inc_icmpinsrcquenchs(void)
+{
+  icmpinsrcquenchs++;
+}
+
+void snmp_inc_icmpinredirects(void)
+{
+  icmpinredirects++;
+}
+
+void snmp_inc_icmpinechos(void)
+{
+  icmpinechos++;
+}
+
+void snmp_inc_icmpinechoreps(void)
+{
+  icmpinechoreps++;
+}
+
+void snmp_inc_icmpintimestamps(void)
+{
+  icmpintimestamps++;
+}
+
+void snmp_inc_icmpintimestampreps(void)
+{
+  icmpintimestampreps++;
+}
+
+void snmp_inc_icmpinaddrmasks(void)
+{
+  icmpinaddrmasks++;
+}
+
+void snmp_inc_icmpinaddrmaskreps(void)
+{
+  icmpinaddrmaskreps++;
+}
+
+void snmp_inc_icmpoutmsgs(void)
+{
+  icmpoutmsgs++;
+}
+
+void snmp_inc_icmpouterrors(void)
+{
+  icmpouterrors++;
+}
+
+void snmp_inc_icmpoutdestunreachs(void)
+{
+  icmpoutdestunreachs++;
+}
+
+void snmp_inc_icmpouttimeexcds(void)
+{
+  icmpouttimeexcds++;
+}
+
+void snmp_inc_icmpoutparmprobs(void)
+{
+  icmpoutparmprobs++;
+}
+
+void snmp_inc_icmpoutsrcquenchs(void)
+{
+  icmpoutsrcquenchs++;
+}
+
+void snmp_inc_icmpoutredirects(void)
+{
+  icmpoutredirects++;
+}
+
+void snmp_inc_icmpoutechos(void)
+{
+  icmpoutechos++;
+}
+
+void snmp_inc_icmpoutechoreps(void)
+{
+  icmpoutechoreps++;
+}
+
+void snmp_inc_icmpouttimestamps(void)
+{
+  icmpouttimestamps++;
+}
+
+void snmp_inc_icmpouttimestampreps(void)
+{
+  icmpouttimestampreps++;
+}
+
+void snmp_inc_icmpoutaddrmasks(void)
+{
+  icmpoutaddrmasks++;
+}
+
+void snmp_inc_icmpoutaddrmaskreps(void)
+{
+  icmpoutaddrmaskreps++;
+}
+
+void snmp_inc_tcpactiveopens(void)
+{
+  tcpactiveopens++;
+}
+
+void snmp_inc_tcppassiveopens(void)
+{
+  tcppassiveopens++;
+}
+
+void snmp_inc_tcpattemptfails(void)
+{
+  tcpattemptfails++;
+}
+
+void snmp_inc_tcpestabresets(void)
+{
+  tcpestabresets++;
+}
+
+void snmp_inc_tcpinsegs(void)
+{
+  tcpinsegs++;
+}
+
+void snmp_inc_tcpoutsegs(void)
+{
+  tcpoutsegs++;
+}
+
+void snmp_inc_tcpretranssegs(void)
+{
+  tcpretranssegs++;
+}
+
+void snmp_inc_tcpinerrs(void)
+{
+  tcpinerrs++;
+}
+
+void snmp_inc_tcpoutrsts(void)
+{
+  tcpoutrsts++;
+}
+
+void snmp_inc_udpindatagrams(void)
+{
+  udpindatagrams++;
+}
+
+void snmp_inc_udpnoports(void)
+{
+  udpnoports++;
+}
+
+void snmp_inc_udpinerrors(void)
+{
+  udpinerrors++;
+}
+
+void snmp_inc_udpoutdatagrams(void)
+{
+  udpoutdatagrams++;
+}
+
+/**
+ * Inserts udpTable indexes (.udpLocalAddress.udpLocalPort)
+ * into index tree.
+ */
+void snmp_insert_udpidx_tree(struct udp_pcb *pcb)
+{
+  struct mib_list_rootnode *udp_rn;
+  struct mib_list_node *udp_node;
+  struct ip_addr ip;
+  s32_t udpidx[5];
+  u8_t level;
+
+  LWIP_ASSERT("pcb != NULL", pcb != NULL);
+  ip.addr = ntohl(pcb->local_ip.addr);
+  snmp_iptooid(&ip, &udpidx[0]);
+  udpidx[4] = pcb->local_port;
+
+  udp_rn = &udp_root;
+  for (level = 0; level < 5; level++)
+  {
+    udp_node = NULL;
+    snmp_mib_node_insert(udp_rn, udpidx[level], &udp_node);
+    if ((level != 4) && (udp_node != NULL))
+    {
+      if (udp_node->nptr == NULL)
+      {
+        udp_rn = snmp_mib_lrn_alloc();
+        udp_node->nptr = (struct mib_node*)udp_rn;
+        if (udp_rn != NULL)
+        {
+          if (level == 3)
+          {
+            udp_rn->get_object_def = udpentry_get_object_def;
+            udp_rn->get_value = udpentry_get_value;
+            udp_rn->set_test = noleafs_set_test;
+            udp_rn->set_value = noleafs_set_value;
+          }
+        }
+        else
+        {
+          /* udp_rn == NULL, malloc failure */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_udpidx_tree() insert failed, mem full"));
+          break;
+        }
+      }
+      else
+      {
+        udp_rn = (struct mib_list_rootnode*)udp_node->nptr;
+      }
+    }
+  }
+  udptable.maxlength = 1;
+}
+
+/**
+ * Removes udpTable indexes (.udpLocalAddress.udpLocalPort)
+ * from index tree.
+ */
+void snmp_delete_udpidx_tree(struct udp_pcb *pcb)
+{
+  struct mib_list_rootnode *udp_rn, *next, *del_rn[5];
+  struct mib_list_node *udp_n, *del_n[5];
+  struct ip_addr ip;
+  s32_t udpidx[5];
+  u8_t bindings, fc, level, del_cnt;
+
+  LWIP_ASSERT("pcb != NULL", pcb != NULL);
+  ip.addr = ntohl(pcb->local_ip.addr);
+  snmp_iptooid(&ip, &udpidx[0]);
+  udpidx[4] = pcb->local_port;
+
+  /* count PCBs for a given binding
+     (e.g. when reusing ports or for temp output PCBs) */
+  bindings = 0;
+  pcb = udp_pcbs;
+  while ((pcb != NULL))
+  {
+    if ((pcb->local_ip.addr == ip.addr) &&
+        (pcb->local_port == udpidx[4]))
+    {
+      bindings++;
+    }
+    pcb = pcb->next;
+  }
+  if (bindings == 1)
+  {
+    /* selectively remove */
+    /* mark nodes for deletion */
+    level = 0;
+    del_cnt = 0;
+    udp_rn = &udp_root;
+    while ((level < 5) && (udp_rn != NULL))
+    {
+      fc = snmp_mib_node_find(udp_rn, udpidx[level], &udp_n);
+      if (fc == 0)
+      {
+        /* udpidx[level] does not exist */
+        del_cnt = 0;
+        udp_rn = NULL;
+      }
+      else if (fc == 1)
+      {
+        del_rn[del_cnt] = udp_rn;
+        del_n[del_cnt] = udp_n;
+        del_cnt++;
+        udp_rn = (struct mib_list_rootnode*)(udp_n->nptr);
+      }
+      else if (fc == 2)
+      {
+        /* reset delete (2 or more childs) */
+        del_cnt = 0;
+        udp_rn = (struct mib_list_rootnode*)(udp_n->nptr);
+      }
+      level++;
+    }
+    /* delete marked index nodes */
+    while (del_cnt > 0)
+    {
+      del_cnt--;
+
+      udp_rn = del_rn[del_cnt];
+      udp_n = del_n[del_cnt];
+
+      next = snmp_mib_node_delete(udp_rn, udp_n);
+      if (next != NULL)
+      {
+        LWIP_ASSERT("next_count == 0",next->count == 0);
+        snmp_mib_lrn_free(next);
+      }
+    }
+  }
+  /* disable getnext traversal on empty table */
+  if (udp_root.count == 0) udptable.maxlength = 0;
+}
+
+
+void snmp_inc_snmpinpkts(void)
+{
+  snmpinpkts++;
+}
+
+void snmp_inc_snmpoutpkts(void)
+{
+  snmpoutpkts++;
+}
+
+void snmp_inc_snmpinbadversions(void)
+{
+  snmpinbadversions++;
+}
+
+void snmp_inc_snmpinbadcommunitynames(void)
+{
+  snmpinbadcommunitynames++;
+}
+
+void snmp_inc_snmpinbadcommunityuses(void)
+{
+  snmpinbadcommunityuses++;
+}
+
+void snmp_inc_snmpinasnparseerrs(void)
+{
+  snmpinasnparseerrs++;
+}
+
+void snmp_inc_snmpintoobigs(void)
+{
+  snmpintoobigs++;
+}
+
+void snmp_inc_snmpinnosuchnames(void)
+{
+  snmpinnosuchnames++;
+}
+
+void snmp_inc_snmpinbadvalues(void)
+{
+  snmpinbadvalues++;
+}
+
+void snmp_inc_snmpinreadonlys(void)
+{
+  snmpinreadonlys++;
+}
+
+void snmp_inc_snmpingenerrs(void)
+{
+  snmpingenerrs++;
+}
+
+void snmp_add_snmpintotalreqvars(u8_t value)
+{
+  snmpintotalreqvars += value;
+}
+
+void snmp_add_snmpintotalsetvars(u8_t value)
+{
+  snmpintotalsetvars += value;
+}
+
+void snmp_inc_snmpingetrequests(void)
+{
+  snmpingetrequests++;
+}
+
+void snmp_inc_snmpingetnexts(void)
+{
+  snmpingetnexts++;
+}
+
+void snmp_inc_snmpinsetrequests(void)
+{
+  snmpinsetrequests++;
+}
+
+void snmp_inc_snmpingetresponses(void)
+{
+  snmpingetresponses++;
+}
+
+void snmp_inc_snmpintraps(void)
+{
+  snmpintraps++;
+}
+
+void snmp_inc_snmpouttoobigs(void)
+{
+  snmpouttoobigs++;
+}
+
+void snmp_inc_snmpoutnosuchnames(void)
+{
+  snmpoutnosuchnames++;
+}
+
+void snmp_inc_snmpoutbadvalues(void)
+{
+  snmpoutbadvalues++;
+}
+
+void snmp_inc_snmpoutgenerrs(void)
+{
+  snmpoutgenerrs++;
+}
+
+void snmp_inc_snmpoutgetrequests(void)
+{
+  snmpoutgetrequests++;
+}
+
+void snmp_inc_snmpoutgetnexts(void)
+{
+  snmpoutgetnexts++;
+}
+
+void snmp_inc_snmpoutsetrequests(void)
+{
+  snmpoutsetrequests++;
+}
+
+void snmp_inc_snmpoutgetresponses(void)
+{
+  snmpoutgetresponses++;
+}
+
+void snmp_inc_snmpouttraps(void)
+{
+  snmpouttraps++;
+}
+
+void snmp_get_snmpgrpid_ptr(struct snmp_obj_id **oid)
+{
+  *oid = &snmpgrp_id;
+}
+
+void snmp_set_snmpenableauthentraps(u8_t *value)
+{
+  if (value != NULL)
+  {
+    snmpenableauthentraps_ptr = value;
+  }
+}
+
+void snmp_get_snmpenableauthentraps(u8_t *value)
+{
+  *value = *snmpenableauthentraps_ptr;
+}
+
+void
+noleafs_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  LWIP_UNUSED_ARG(ident_len);
+  LWIP_UNUSED_ARG(ident);
+  od->instance = MIB_OBJECT_NONE;
+}
+
+void
+noleafs_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  LWIP_UNUSED_ARG(od);
+  LWIP_UNUSED_ARG(len);
+  LWIP_UNUSED_ARG(value);
+}
+
+u8_t
+noleafs_set_test(struct obj_def *od, u16_t len, void *value)
+{
+  LWIP_UNUSED_ARG(od);
+  LWIP_UNUSED_ARG(len);
+  LWIP_UNUSED_ARG(value);
+  /* can't set */
+  return 0;
+}
+
+void
+noleafs_set_value(struct obj_def *od, u16_t len, void *value)
+{
+  LWIP_UNUSED_ARG(od);
+  LWIP_UNUSED_ARG(len);
+  LWIP_UNUSED_ARG(value);
+}
+
+
+/**
+ * Returns systems object definitions.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.0 (object id trailer)
+ * @param od points to object definition.
+ */
+static void
+system_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  u8_t id;
+
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def system.%"U16_F".0\n",(u16_t)id));
+    switch (id)
+    {
+      case 1: /* sysDescr */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = *sysdescr_len_ptr;
+        break;
+      case 2: /* sysObjectID */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID);
+        od->v_len = sysobjid.len * sizeof(s32_t);
+        break;
+      case 3: /* sysUpTime */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 4: /* sysContact */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = *syscontact_len_ptr;
+        break;
+      case 5: /* sysName */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = *sysname_len_ptr;
+        break;
+      case 6: /* sysLocation */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = *syslocation_len_ptr;
+        break;
+      case 7: /* sysServices */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("system_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("system_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+/**
+ * Returns system object value.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.0 (object id trailer)
+ * @param len return value space (in bytes)
+ * @param value points to (varbind) space to copy value into.
+ */
+static void
+system_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* sysDescr */
+      ocstrncpy(value,sysdescr_ptr, len);
+      break;
+    case 2: /* sysObjectID */
+      objectidncpy((s32_t*)value, (s32_t*)sysobjid.id, (u8_t)(len / sizeof(s32_t)));
+      break;
+    case 3: /* sysUpTime */
+      {
+        snmp_get_sysuptime(value);
+      }
+      break;
+    case 4: /* sysContact */
+      ocstrncpy(value,syscontact_ptr,len);
+      break;
+    case 5: /* sysName */
+      ocstrncpy(value,sysname_ptr,len);
+      break;
+    case 6: /* sysLocation */
+      ocstrncpy(value,syslocation_ptr,len);
+      break;
+    case 7: /* sysServices */
+      {
+        s32_t *sint_ptr = value;
+        *sint_ptr = sysservices;
+      }
+      break;
+  };
+}
+
+static u8_t
+system_set_test(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id, set_ok;
+
+  LWIP_UNUSED_ARG(value);
+  set_ok = 0;
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 4: /* sysContact */
+      if ((syscontact_ptr != syscontact_default) &&
+          (len <= 255))
+      {
+        set_ok = 1;
+      }
+      break;
+    case 5: /* sysName */
+      if ((sysname_ptr != sysname_default) &&
+          (len <= 255))
+      {
+        set_ok = 1;
+      }
+      break;
+    case 6: /* sysLocation */
+      if ((syslocation_ptr != syslocation_default) &&
+          (len <= 255))
+      {
+        set_ok = 1;
+      }
+      break;
+  };
+  return set_ok;
+}
+
+static void
+system_set_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 4: /* sysContact */
+      ocstrncpy(syscontact_ptr,value,len);
+      *syscontact_len_ptr = len;
+      break;
+    case 5: /* sysName */
+      ocstrncpy(sysname_ptr,value,len);
+      *sysname_len_ptr = len;
+      break;
+    case 6: /* sysLocation */
+      ocstrncpy(syslocation_ptr,value,len);
+      *syslocation_len_ptr = len;
+      break;
+  };
+}
+
+/**
+ * Returns interfaces.ifnumber object definition.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.index
+ * @param od points to object definition.
+ */
+static void
+interfaces_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    od->instance = MIB_OBJECT_SCALAR;
+    od->access = MIB_OBJECT_READ_ONLY;
+    od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+    od->v_len = sizeof(s32_t);
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("interfaces_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+/**
+ * Returns interfaces.ifnumber object value.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.0 (object id trailer)
+ * @param len return value space (in bytes)
+ * @param value points to (varbind) space to copy value into.
+ */
+static void
+interfaces_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  LWIP_UNUSED_ARG(len);
+  if (od->id_inst_ptr[0] == 1)
+  {
+    s32_t *sint_ptr = value;
+    *sint_ptr = iflist_root.count;
+  }
+}
+
+/**
+ * Returns ifentry object definitions.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.index
+ * @param od points to object definition.
+ */
+static void
+ifentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  u8_t id;
+
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def ifentry.%"U16_F"\n",(u16_t)id));
+    switch (id)
+    {
+      case 1: /* ifIndex */
+      case 3: /* ifType */
+      case 4: /* ifMtu */
+      case 8: /* ifOperStatus */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 2: /* ifDescr */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        /** @todo this should be some sort of sizeof(struct netif.name) */
+        od->v_len = 2;
+        break;
+      case 5: /* ifSpeed */
+      case 21: /* ifOutQLen */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 6: /* ifPhysAddress */
+        {
+          struct netif *netif;
+
+          snmp_ifindextonetif(ident[1], &netif);
+          od->instance = MIB_OBJECT_TAB;
+          od->access = MIB_OBJECT_READ_ONLY;
+          od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+          od->v_len = netif->hwaddr_len;
+        }
+        break;
+      case 7: /* ifAdminStatus */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 9: /* ifLastChange */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 10: /* ifInOctets */
+      case 11: /* ifInUcastPkts */
+      case 12: /* ifInNUcastPkts */
+      case 13: /* ifInDiscarts */
+      case 14: /* ifInErrors */
+      case 15: /* ifInUnkownProtos */
+      case 16: /* ifOutOctets */
+      case 17: /* ifOutUcastPkts */
+      case 18: /* ifOutNUcastPkts */
+      case 19: /* ifOutDiscarts */
+      case 20: /* ifOutErrors */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 22: /* ifSpecific */
+        /** @note returning zeroDotZero (0.0) no media specific MIB support */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID);
+        od->v_len = ifspecific.len * sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ifentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("ifentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+/**
+ * Returns ifentry object value.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.0 (object id trailer)
+ * @param len return value space (in bytes)
+ * @param value points to (varbind) space to copy value into.
+ */
+static void
+ifentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  struct netif *netif;
+  u8_t id;
+
+  snmp_ifindextonetif(od->id_inst_ptr[1], &netif);
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* ifIndex */
+      {
+        s32_t *sint_ptr = value;
+        *sint_ptr = od->id_inst_ptr[1];
+      }
+      break;
+    case 2: /* ifDescr */
+      ocstrncpy(value,(u8_t*)netif->name,len);
+      break;
+    case 3: /* ifType */
+      {
+        s32_t *sint_ptr = value;
+        *sint_ptr = netif->link_type;
+      }
+      break;
+    case 4: /* ifMtu */
+      {
+        s32_t *sint_ptr = value;
+        *sint_ptr = netif->mtu;
+      }
+      break;
+    case 5: /* ifSpeed */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->link_speed;
+      }
+      break;
+    case 6: /* ifPhysAddress */
+      ocstrncpy(value,netif->hwaddr,len);
+      break;
+    case 7: /* ifAdminStatus */
+#if LWIP_NETIF_LINK_CALLBACK
+      {
+        s32_t *sint_ptr = value;
+        if (netif_is_up(netif))
+        {
+          if (netif_is_link_up(netif))
+          {
+            *sint_ptr = 1; /* up */
+          }
+          else
+          {
+            *sint_ptr = 7; /* lowerLayerDown */
+          }
+        }
+        else
+        {
+          *sint_ptr = 2; /* down */
+        }
+      }
+      break;
+#endif
+    case 8: /* ifOperStatus */
+      {
+        s32_t *sint_ptr = value;
+        if (netif_is_up(netif))
+        {
+          *sint_ptr = 1;
+        }
+        else
+        {
+          *sint_ptr = 2;
+        }
+      }
+      break;
+    case 9: /* ifLastChange */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ts;
+      }
+      break;
+    case 10: /* ifInOctets */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifinoctets;
+      }
+      break;
+    case 11: /* ifInUcastPkts */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifinucastpkts;
+      }
+      break;
+    case 12: /* ifInNUcastPkts */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifinnucastpkts;
+      }
+      break;
+    case 13: /* ifInDiscarts */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifindiscards;
+      }
+      break;
+    case 14: /* ifInErrors */
+    case 15: /* ifInUnkownProtos */
+      /** @todo add these counters! */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = 0;
+      }
+      break;
+    case 16: /* ifOutOctets */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifoutoctets;
+      }
+      break;
+    case 17: /* ifOutUcastPkts */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifoutucastpkts;
+      }
+      break;
+    case 18: /* ifOutNUcastPkts */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifoutnucastpkts;
+      }
+      break;
+    case 19: /* ifOutDiscarts */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = netif->ifoutdiscards;
+      }
+      break;
+    case 20: /* ifOutErrors */
+       /** @todo add this counter! */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = 0;
+      }
+      break;
+    case 21: /* ifOutQLen */
+      /** @todo figure out if this must be 0 (no queue) or 1? */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = 0;
+      }
+      break;
+    case 22: /* ifSpecific */
+      objectidncpy((s32_t*)value, (s32_t*)ifspecific.id, (u8_t)(len / sizeof(s32_t)));
+      break;
+  };
+}
+
+#if !SNMP_SAFE_REQUESTS
+static u8_t
+ifentry_set_test (struct obj_def *od, u16_t len, void *value)
+{
+  struct netif *netif;
+  u8_t id, set_ok;
+
+  set_ok = 0;
+  snmp_ifindextonetif(od->id_inst_ptr[1], &netif);
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 7: /* ifAdminStatus */
+      {
+        s32_t *sint_ptr = value;
+        if (*sint_ptr == 1 || *sint_ptr == 2)
+          set_ok = 1;
+      }
+      break;
+  }
+  return set_ok;
+}
+
+static void
+ifentry_set_value (struct obj_def *od, u16_t len, void *value)
+{
+  struct netif *netif;
+  u8_t id;
+
+  snmp_ifindextonetif(od->id_inst_ptr[1], &netif);
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 7: /* ifAdminStatus */
+      {
+        s32_t *sint_ptr = value;
+        if (*sint_ptr == 1)
+        {
+          netif_set_up(netif);
+        }
+        else if (*sint_ptr == 2)
+        {
+          netif_set_down(netif);
+         }
+      }
+      break;
+  }
+}
+#endif /* SNMP_SAFE_REQUESTS */
+
+/**
+ * Returns atentry object definitions.
+ *
+ * @param ident_len the address length (6)
+ * @param ident points to objectname.atifindex.atnetaddress
+ * @param od points to object definition.
+ */
+static void
+atentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (5) */
+  ident_len += 5;
+  ident -= 5;
+
+  if (ident_len == 6)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    switch (ident[0])
+    {
+      case 1: /* atIfIndex */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 2: /* atPhysAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = 6; /** @todo try to use netif::hwaddr_len */
+        break;
+      case 3: /* atNetAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("atentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    }
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("atentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+atentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+#if LWIP_ARP
+  u8_t id;
+  struct eth_addr* ethaddr_ret;
+  struct ip_addr* ipaddr_ret;
+#endif /* LWIP_ARP */
+  struct ip_addr ip;
+  struct netif *netif;
+
+  LWIP_UNUSED_ARG(len);
+  LWIP_UNUSED_ARG(value);/* if !LWIP_ARP */
+
+  snmp_ifindextonetif(od->id_inst_ptr[1], &netif);
+  snmp_oidtoip(&od->id_inst_ptr[2], &ip);
+  ip.addr = htonl(ip.addr);
+
+#if LWIP_ARP /** @todo implement a netif_find_addr */
+  if (etharp_find_addr(netif, &ip, ðaddr_ret, &ipaddr_ret) > -1)
+  {
+    id = od->id_inst_ptr[0];
+    switch (id)
+    {
+      case 1: /* atIfIndex */
+        {
+          s32_t *sint_ptr = value;
+          *sint_ptr = od->id_inst_ptr[1];
+        }
+        break;
+      case 2: /* atPhysAddress */
+        {
+          struct eth_addr *dst = value;
+
+          *dst = *ethaddr_ret;
+        }
+        break;
+      case 3: /* atNetAddress */
+        {
+          struct ip_addr *dst = value;
+
+          *dst = *ipaddr_ret;
+        }
+        break;
+    }
+  }
+#endif /* LWIP_ARP */
+}
+
+static void
+ip_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  u8_t id;
+
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def ip.%"U16_F".0\n",(u16_t)id));
+    switch (id)
+    {
+      case 1: /* ipForwarding */
+      case 2: /* ipDefaultTTL */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 3: /* ipInReceives */
+      case 4: /* ipInHdrErrors */
+      case 5: /* ipInAddrErrors */
+      case 6: /* ipForwDatagrams */
+      case 7: /* ipInUnknownProtos */
+      case 8: /* ipInDiscards */
+      case 9: /* ipInDelivers */
+      case 10: /* ipOutRequests */
+      case 11: /* ipOutDiscards */
+      case 12: /* ipOutNoRoutes */
+      case 14: /* ipReasmReqds */
+      case 15: /* ipReasmOKs */
+      case 16: /* ipReasmFails */
+      case 17: /* ipFragOKs */
+      case 18: /* ipFragFails */
+      case 19: /* ipFragCreates */
+      case 23: /* ipRoutingDiscards */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 13: /* ipReasmTimeout */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+ip_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+
+  LWIP_UNUSED_ARG(len);
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* ipForwarding */
+      {
+        s32_t *sint_ptr = value;
+#if IP_FORWARD
+        /* forwarding */
+        *sint_ptr = 1;
+#else
+        /* not-forwarding */
+        *sint_ptr = 2;
+#endif
+      }
+      break;
+    case 2: /* ipDefaultTTL */
+      {
+        s32_t *sint_ptr = value;
+        *sint_ptr = IP_DEFAULT_TTL;
+      }
+      break;
+    case 3: /* ipInReceives */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipinreceives;
+      }
+      break;
+    case 4: /* ipInHdrErrors */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipinhdrerrors;
+      }
+      break;
+    case 5: /* ipInAddrErrors */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipinaddrerrors;
+      }
+      break;
+    case 6: /* ipForwDatagrams */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipforwdatagrams;
+      }
+      break;
+    case 7: /* ipInUnknownProtos */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipinunknownprotos;
+      }
+      break;
+    case 8: /* ipInDiscards */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipindiscards;
+      }
+      break;
+    case 9: /* ipInDelivers */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipindelivers;
+      }
+      break;
+    case 10: /* ipOutRequests */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipoutrequests;
+      }
+      break;
+    case 11: /* ipOutDiscards */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipoutdiscards;
+      }
+      break;
+    case 12: /* ipOutNoRoutes */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipoutnoroutes;
+      }
+      break;
+    case 13: /* ipReasmTimeout */
+      {
+        s32_t *sint_ptr = value;
+#if IP_REASSEMBLY
+        *sint_ptr = IP_REASS_MAXAGE;
+#else
+        *sint_ptr = 0;
+#endif
+      }
+      break;
+    case 14: /* ipReasmReqds */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipreasmreqds;
+      }
+      break;
+    case 15: /* ipReasmOKs */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipreasmoks;
+      }
+      break;
+    case 16: /* ipReasmFails */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipreasmfails;
+      }
+      break;
+    case 17: /* ipFragOKs */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipfragoks;
+      }
+      break;
+    case 18: /* ipFragFails */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipfragfails;
+      }
+      break;
+    case 19: /* ipFragCreates */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = ipfragcreates;
+      }
+      break;
+    case 23: /* ipRoutingDiscards */
+      /** @todo can lwIP discard routes at all?? hardwire this to 0?? */
+      {
+        u32_t *uint_ptr = value;
+        *uint_ptr = iproutingdiscards;
+      }
+      break;
+  };
+}
+
+/**
+ * Test ip object value before setting.
+ *
+ * @param od is the object definition
+ * @param len return value space (in bytes)
+ * @param value points to (varbind) space to copy value from.
+ *
+ * @note we allow set if the value matches the hardwired value,
+ *   otherwise return badvalue.
+ */
+static u8_t
+ip_set_test(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id, set_ok;
+  s32_t *sint_ptr = value;
+
+  LWIP_UNUSED_ARG(len);
+  set_ok = 0;
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* ipForwarding */
+#if IP_FORWARD
+      /* forwarding */
+      if (*sint_ptr == 1)
+#else
+      /* not-forwarding */
+      if (*sint_ptr == 2)
+#endif
+      {
+        set_ok = 1;
+      }
+      break;
+    case 2: /* ipDefaultTTL */
+      if (*sint_ptr == IP_DEFAULT_TTL)
+      {
+        set_ok = 1;
+      }
+      break;
+  };
+  return set_ok;
+}
+
+static void
+ip_addrentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (4) */
+  ident_len += 4;
+  ident -= 4;
+
+  if (ident_len == 5)
+  {
+    u8_t id;
+
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    switch (id)
+    {
+      case 1: /* ipAdEntAddr */
+      case 3: /* ipAdEntNetMask */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      case 2: /* ipAdEntIfIndex */
+      case 4: /* ipAdEntBcastAddr */
+      case 5: /* ipAdEntReasmMaxSize */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_addrentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    }
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_addrentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+ip_addrentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+  u16_t ifidx;
+  struct ip_addr ip;
+  struct netif *netif = netif_list;
+
+  LWIP_UNUSED_ARG(len);
+  snmp_oidtoip(&od->id_inst_ptr[1], &ip);
+  ip.addr = htonl(ip.addr);
+  ifidx = 0;
+  while ((netif != NULL) && !ip_addr_cmp(&ip, &netif->ip_addr))
+  {
+    netif = netif->next;
+    ifidx++;
+  }
+
+  if (netif != NULL)
+  {
+    id = od->id_inst_ptr[0];
+    switch (id)
+    {
+      case 1: /* ipAdEntAddr */
+        {
+          struct ip_addr *dst = value;
+          *dst = netif->ip_addr;
+        }
+        break;
+      case 2: /* ipAdEntIfIndex */
+        {
+          s32_t *sint_ptr = value;
+          *sint_ptr = ifidx + 1;
+        }
+        break;
+      case 3: /* ipAdEntNetMask */
+        {
+          struct ip_addr *dst = value;
+          *dst = netif->netmask;
+        }
+        break;
+      case 4: /* ipAdEntBcastAddr */
+        {
+          s32_t *sint_ptr = value;
+
+          /* lwIP oddity, there's no broadcast
+            address in the netif we can rely on */
+          *sint_ptr = ip_addr_broadcast.addr & 1;
+        }
+        break;
+      case 5: /* ipAdEntReasmMaxSize */
+        {
+          s32_t *sint_ptr = value;
+#if IP_REASSEMBLY
+          /* @todo The theoretical maximum is IP_REASS_MAX_PBUFS * size of the pbufs,
+           * but only if receiving one fragmented packet at a time.
+           * The current solution is to calculate for 2 simultaneous packets...
+           */
+          *sint_ptr = (IP_HLEN + ((IP_REASS_MAX_PBUFS/2) *
+            (PBUF_POOL_BUFSIZE - PBUF_LINK_HLEN - IP_HLEN)));
+#else
+          /** @todo returning MTU would be a bad thing and
+             returning a wild guess like '576' isn't good either */
+          *sint_ptr = 0;
+#endif
+        }
+        break;
+    }
+  }
+}
+
+/**
+ * @note
+ * lwIP IP routing is currently using the network addresses in netif_list.
+ * if no suitable network IP is found in netif_list, the default_netif is used.
+ */
+static void
+ip_rteentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  u8_t id;
+
+  /* return to object name, adding index depth (4) */
+  ident_len += 4;
+  ident -= 4;
+
+  if (ident_len == 5)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    switch (id)
+    {
+      case 1: /* ipRouteDest */
+      case 7: /* ipRouteNextHop */
+      case 11: /* ipRouteMask */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      case 2: /* ipRouteIfIndex */
+      case 3: /* ipRouteMetric1 */
+      case 4: /* ipRouteMetric2 */
+      case 5: /* ipRouteMetric3 */
+      case 6: /* ipRouteMetric4 */
+      case 8: /* ipRouteType */
+      case 10: /* ipRouteAge */
+      case 12: /* ipRouteMetric5 */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 9: /* ipRouteProto */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 13: /* ipRouteInfo */
+        /** @note returning zeroDotZero (0.0) no routing protocol specific MIB */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID);
+        od->v_len = iprouteinfo.len * sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_rteentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    }
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_rteentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+ip_rteentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  struct netif *netif;
+  struct ip_addr dest;
+  s32_t *ident;
+  u8_t id;
+
+  ident = od->id_inst_ptr;
+  snmp_oidtoip(&ident[1], &dest);
+  dest.addr = htonl(dest.addr);
+
+  if (dest.addr == 0)
+  {
+    /* ip_route() uses default netif for default route */
+    netif = netif_default;
+  }
+  else
+  {
+    /* not using ip_route(), need exact match! */
+    netif = netif_list;
+    while ((netif != NULL) &&
+            !ip_addr_netcmp(&dest, &(netif->ip_addr), &(netif->netmask)) )
+    {
+      netif = netif->next;
+    }
+  }
+  if (netif != NULL)
+  {
+    id = ident[0];
+    switch (id)
+    {
+      case 1: /* ipRouteDest */
+        {
+          struct ip_addr *dst = value;
+
+          if (dest.addr == 0)
+          {
+            /* default rte has 0.0.0.0 dest */
+            dst->addr = 0;
+          }
+          else
+          {
+            /* netifs have netaddress dest */
+            dst->addr = netif->ip_addr.addr & netif->netmask.addr;
+          }
+        }
+        break;
+      case 2: /* ipRouteIfIndex */
+        {
+          s32_t *sint_ptr = value;
+
+          snmp_netiftoifindex(netif, sint_ptr);
+        }
+        break;
+      case 3: /* ipRouteMetric1 */
+        {
+          s32_t *sint_ptr = value;
+
+          if (dest.addr == 0)
+          {
+            /* default rte has metric 1 */
+            *sint_ptr = 1;
+          }
+          else
+          {
+            /* other rtes have metric 0 */
+            *sint_ptr = 0;
+          }
+        }
+        break;
+      case 4: /* ipRouteMetric2 */
+      case 5: /* ipRouteMetric3 */
+      case 6: /* ipRouteMetric4 */
+      case 12: /* ipRouteMetric5 */
+        {
+          s32_t *sint_ptr = value;
+          /* not used */
+          *sint_ptr = -1;
+        }
+        break;
+      case 7: /* ipRouteNextHop */
+        {
+          struct ip_addr *dst = value;
+
+          if (dest.addr == 0)
+          {
+            /* default rte: gateway */
+            *dst = netif->gw;
+          }
+          else
+          {
+            /* other rtes: netif ip_addr  */
+            *dst = netif->ip_addr;
+          }
+        }
+        break;
+      case 8: /* ipRouteType */
+        {
+          s32_t *sint_ptr = value;
+
+          if (dest.addr == 0)
+          {
+            /* default rte is indirect */
+            *sint_ptr = 4;
+          }
+          else
+          {
+            /* other rtes are direct */
+            *sint_ptr = 3;
+          }
+        }
+        break;
+      case 9: /* ipRouteProto */
+        {
+          s32_t *sint_ptr = value;
+          /* locally defined routes */
+          *sint_ptr = 2;
+        }
+        break;
+      case 10: /* ipRouteAge */
+        {
+          s32_t *sint_ptr = value;
+          /** @todo (sysuptime - timestamp last change) / 100
+              @see snmp_insert_iprteidx_tree() */
+          *sint_ptr = 0;
+        }
+        break;
+      case 11: /* ipRouteMask */
+        {
+          struct ip_addr *dst = value;
+
+          if (dest.addr == 0)
+          {
+            /* default rte use 0.0.0.0 mask */
+            dst->addr = 0;
+          }
+          else
+          {
+            /* other rtes use netmask */
+            *dst = netif->netmask;
+          }
+        }
+        break;
+      case 13: /* ipRouteInfo */
+        objectidncpy((s32_t*)value, (s32_t*)iprouteinfo.id, (u8_t)(len / sizeof(s32_t)));
+        break;
+    }
+  }
+}
+
+static void
+ip_ntomentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (5) */
+  ident_len += 5;
+  ident -= 5;
+
+  if (ident_len == 6)
+  {
+    u8_t id;
+
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    switch (id)
+    {
+      case 1: /* ipNetToMediaIfIndex */
+      case 4: /* ipNetToMediaType */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 2: /* ipNetToMediaPhysAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = 6; /** @todo try to use netif::hwaddr_len */
+        break;
+      case 3: /* ipNetToMediaNetAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_ntomentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    }
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_ntomentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+ip_ntomentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+#if LWIP_ARP
+  u8_t id;
+  struct eth_addr* ethaddr_ret;
+  struct ip_addr* ipaddr_ret;
+#endif /* LWIP_ARP */
+  struct ip_addr ip;
+  struct netif *netif;
+
+  LWIP_UNUSED_ARG(len);
+  LWIP_UNUSED_ARG(value);/* if !LWIP_ARP */
+
+  snmp_ifindextonetif(od->id_inst_ptr[1], &netif);
+  snmp_oidtoip(&od->id_inst_ptr[2], &ip);
+  ip.addr = htonl(ip.addr);
+
+#if LWIP_ARP /** @todo implement a netif_find_addr */
+  if (etharp_find_addr(netif, &ip, ðaddr_ret, &ipaddr_ret) > -1)
+  {
+    id = od->id_inst_ptr[0];
+    switch (id)
+    {
+      case 1: /* ipNetToMediaIfIndex */
+        {
+          s32_t *sint_ptr = value;
+          *sint_ptr = od->id_inst_ptr[1];
+        }
+        break;
+      case 2: /* ipNetToMediaPhysAddress */
+        {
+          struct eth_addr *dst = value;
+
+          *dst = *ethaddr_ret;
+        }
+        break;
+      case 3: /* ipNetToMediaNetAddress */
+        {
+          struct ip_addr *dst = value;
+
+          *dst = *ipaddr_ret;
+        }
+        break;
+      case 4: /* ipNetToMediaType */
+        {
+          s32_t *sint_ptr = value;
+          /* dynamic (?) */
+          *sint_ptr = 3;
+        }
+        break;
+    }
+  }
+#endif /* LWIP_ARP */
+}
+
+static void
+icmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if ((ident_len == 2) &&
+      (ident[0] > 0) && (ident[0] < 27))
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    od->instance = MIB_OBJECT_SCALAR;
+    od->access = MIB_OBJECT_READ_ONLY;
+    od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+    od->v_len = sizeof(u32_t);
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("icmp_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+icmp_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u32_t *uint_ptr = value;
+  u8_t id;
+
+  LWIP_UNUSED_ARG(len);
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* icmpInMsgs */
+      *uint_ptr = icmpinmsgs;
+      break;
+    case 2: /* icmpInErrors */
+      *uint_ptr = icmpinerrors;
+      break;
+    case 3: /* icmpInDestUnreachs */
+      *uint_ptr = icmpindestunreachs;
+      break;
+    case 4: /* icmpInTimeExcds */
+      *uint_ptr = icmpintimeexcds;
+      break;
+    case 5: /* icmpInParmProbs */
+      *uint_ptr = icmpinparmprobs;
+      break;
+    case 6: /* icmpInSrcQuenchs */
+      *uint_ptr = icmpinsrcquenchs;
+      break;
+    case 7: /* icmpInRedirects */
+      *uint_ptr = icmpinredirects;
+      break;
+    case 8: /* icmpInEchos */
+      *uint_ptr = icmpinechos;
+      break;
+    case 9: /* icmpInEchoReps */
+      *uint_ptr = icmpinechoreps;
+      break;
+    case 10: /* icmpInTimestamps */
+      *uint_ptr = icmpintimestamps;
+      break;
+    case 11: /* icmpInTimestampReps */
+      *uint_ptr = icmpintimestampreps;
+      break;
+    case 12: /* icmpInAddrMasks */
+      *uint_ptr = icmpinaddrmasks;
+      break;
+    case 13: /* icmpInAddrMaskReps */
+      *uint_ptr = icmpinaddrmaskreps;
+      break;
+    case 14: /* icmpOutMsgs */
+      *uint_ptr = icmpoutmsgs;
+      break;
+    case 15: /* icmpOutErrors */
+      *uint_ptr = icmpouterrors;
+      break;
+    case 16: /* icmpOutDestUnreachs */
+      *uint_ptr = icmpoutdestunreachs;
+      break;
+    case 17: /* icmpOutTimeExcds */
+      *uint_ptr = icmpouttimeexcds;
+      break;
+    case 18: /* icmpOutParmProbs */
+      *uint_ptr = icmpoutparmprobs;
+      break;
+    case 19: /* icmpOutSrcQuenchs */
+      *uint_ptr = icmpoutsrcquenchs;
+      break;
+    case 20: /* icmpOutRedirects */
+      *uint_ptr = icmpoutredirects;
+      break;
+    case 21: /* icmpOutEchos */
+      *uint_ptr = icmpoutechos;
+      break;
+    case 22: /* icmpOutEchoReps */
+      *uint_ptr = icmpoutechoreps;
+      break;
+    case 23: /* icmpOutTimestamps */
+      *uint_ptr = icmpouttimestamps;
+      break;
+    case 24: /* icmpOutTimestampReps */
+      *uint_ptr = icmpouttimestampreps;
+      break;
+    case 25: /* icmpOutAddrMasks */
+      *uint_ptr = icmpoutaddrmasks;
+      break;
+    case 26: /* icmpOutAddrMaskReps */
+      *uint_ptr = icmpoutaddrmaskreps;
+      break;
+  }
+}
+
+#if LWIP_TCP
+/** @todo tcp grp */
+static void
+tcp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  u8_t id;
+
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def tcp.%"U16_F".0\n",(u16_t)id));
+
+    switch (id)
+    {
+      case 1: /* tcpRtoAlgorithm */
+      case 2: /* tcpRtoMin */
+      case 3: /* tcpRtoMax */
+      case 4: /* tcpMaxConn */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 5: /* tcpActiveOpens */
+      case 6: /* tcpPassiveOpens */
+      case 7: /* tcpAttemptFails */
+      case 8: /* tcpEstabResets */
+      case 10: /* tcpInSegs */
+      case 11: /* tcpOutSegs */
+      case 12: /* tcpRetransSegs */
+      case 14: /* tcpInErrs */
+      case 15: /* tcpOutRsts */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 9: /* tcpCurrEstab */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE);
+        od->v_len = sizeof(u32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcp_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcp_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+tcp_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u32_t *uint_ptr = value;
+  s32_t *sint_ptr = value;
+  u8_t id;
+
+  LWIP_UNUSED_ARG(len);
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* tcpRtoAlgorithm, vanj(4) */
+      *sint_ptr = 4;
+      break;
+    case 2: /* tcpRtoMin */
+      /* @todo not the actual value, a guess,
+          needs to be calculated */
+      *sint_ptr = 1000;
+      break;
+    case 3: /* tcpRtoMax */
+      /* @todo not the actual value, a guess,
+         needs to be calculated */
+      *sint_ptr = 60000;
+      break;
+    case 4: /* tcpMaxConn */
+      *sint_ptr = MEMP_NUM_TCP_PCB;
+      break;
+    case 5: /* tcpActiveOpens */
+      *uint_ptr = tcpactiveopens;
+      break;
+    case 6: /* tcpPassiveOpens */
+      *uint_ptr = tcppassiveopens;
+      break;
+    case 7: /* tcpAttemptFails */
+      *uint_ptr = tcpattemptfails;
+      break;
+    case 8: /* tcpEstabResets */
+      *uint_ptr = tcpestabresets;
+      break;
+    case 9: /* tcpCurrEstab */
+      {
+        u16_t tcpcurrestab = 0;
+        struct tcp_pcb *pcb = tcp_active_pcbs;
+        while (pcb != NULL)
+        {
+          if ((pcb->state == ESTABLISHED) ||
+              (pcb->state == CLOSE_WAIT))
+          {
+            tcpcurrestab++;
+          }
+          pcb = pcb->next;
+        }
+        *uint_ptr = tcpcurrestab;
+      }
+      break;
+    case 10: /* tcpInSegs */
+      *uint_ptr = tcpinsegs;
+      break;
+    case 11: /* tcpOutSegs */
+      *uint_ptr = tcpoutsegs;
+      break;
+    case 12: /* tcpRetransSegs */
+      *uint_ptr = tcpretranssegs;
+      break;
+    case 14: /* tcpInErrs */
+      *uint_ptr = tcpinerrs;
+      break;
+    case 15: /* tcpOutRsts */
+      *uint_ptr = tcpoutrsts;
+      break;
+  }
+}
+#ifdef THIS_SEEMS_UNUSED
+static void
+tcpconnentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (10) */
+  ident_len += 10;
+  ident -= 10;
+
+  if (ident_len == 11)
+  {
+    u8_t id;
+
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def tcp.%"U16_F".0\n",(u16_t)id));
+
+    switch (id)
+    {
+      case 1: /* tcpConnState */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 2: /* tcpConnLocalAddress */
+      case 4: /* tcpConnRemAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      case 3: /* tcpConnLocalPort */
+      case 5: /* tcpConnRemPort */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcpconnentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcpconnentry_get_object_def: no such object\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+tcpconnentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  struct ip_addr lip, rip;
+  u16_t lport, rport;
+  s32_t *ident;
+
+  ident = od->id_inst_ptr;
+  snmp_oidtoip(&ident[1], &lip);
+  lip.addr = htonl(lip.addr);
+  lport = ident[5];
+  snmp_oidtoip(&ident[6], &rip);
+  rip.addr = htonl(rip.addr);
+  rport = ident[10];
+
+  /** @todo find matching PCB */
+}
+#endif /* if 0 */
+#endif
+
+static void
+udp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if ((ident_len == 2) &&
+      (ident[0] > 0) && (ident[0] < 6))
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    od->instance = MIB_OBJECT_SCALAR;
+    od->access = MIB_OBJECT_READ_ONLY;
+    od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+    od->v_len = sizeof(u32_t);
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("udp_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+udp_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u32_t *uint_ptr = value;
+  u8_t id;
+
+  LWIP_UNUSED_ARG(len);
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* udpInDatagrams */
+      *uint_ptr = udpindatagrams;
+      break;
+    case 2: /* udpNoPorts */
+      *uint_ptr = udpnoports;
+      break;
+    case 3: /* udpInErrors */
+      *uint_ptr = udpinerrors;
+      break;
+    case 4: /* udpOutDatagrams */
+      *uint_ptr = udpoutdatagrams;
+      break;
+  }
+}
+
+static void
+udpentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (5) */
+  ident_len += 5;
+  ident -= 5;
+
+  if (ident_len == 6)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    switch (ident[0])
+    {
+      case 1: /* udpLocalAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      case 2: /* udpLocalPort */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("udpentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    }
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("udpentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+udpentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+  struct udp_pcb *pcb;
+  struct ip_addr ip;
+  u16_t port;
+
+  LWIP_UNUSED_ARG(len);
+  snmp_oidtoip(&od->id_inst_ptr[1], &ip);
+  ip.addr = htonl(ip.addr);
+  port = od->id_inst_ptr[5];
+
+  pcb = udp_pcbs;
+  while ((pcb != NULL) &&
+         !((pcb->local_ip.addr == ip.addr) &&
+           (pcb->local_port == port)))
+  {
+    pcb = pcb->next;
+  }
+
+  if (pcb != NULL)
+  {
+    id = od->id_inst_ptr[0];
+    switch (id)
+    {
+      case 1: /* udpLocalAddress */
+        {
+          struct ip_addr *dst = value;
+          *dst = pcb->local_ip;
+        }
+        break;
+      case 2: /* udpLocalPort */
+        {
+          s32_t *sint_ptr = value;
+          *sint_ptr = pcb->local_port;
+        }
+        break;
+    }
+  }
+}
+
+static void
+snmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    u8_t id;
+
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    switch (id)
+    {
+      case 1: /* snmpInPkts */
+      case 2: /* snmpOutPkts */
+      case 3: /* snmpInBadVersions */
+      case 4: /* snmpInBadCommunityNames */
+      case 5: /* snmpInBadCommunityUses */
+      case 6: /* snmpInASNParseErrs */
+      case 8: /* snmpInTooBigs */
+      case 9: /* snmpInNoSuchNames */
+      case 10: /* snmpInBadValues */
+      case 11: /* snmpInReadOnlys */
+      case 12: /* snmpInGenErrs */
+      case 13: /* snmpInTotalReqVars */
+      case 14: /* snmpInTotalSetVars */
+      case 15: /* snmpInGetRequests */
+      case 16: /* snmpInGetNexts */
+      case 17: /* snmpInSetRequests */
+      case 18: /* snmpInGetResponses */
+      case 19: /* snmpInTraps */
+      case 20: /* snmpOutTooBigs */
+      case 21: /* snmpOutNoSuchNames */
+      case 22: /* snmpOutBadValues */
+      case 24: /* snmpOutGenErrs */
+      case 25: /* snmpOutGetRequests */
+      case 26: /* snmpOutGetNexts */
+      case 27: /* snmpOutSetRequests */
+      case 28: /* snmpOutGetResponses */
+      case 29: /* snmpOutTraps */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 30: /* snmpEnableAuthenTraps */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+snmp_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u32_t *uint_ptr = value;
+  u8_t id;
+
+  LWIP_UNUSED_ARG(len);
+  id = od->id_inst_ptr[0];
+  switch (id)
+  {
+      case 1: /* snmpInPkts */
+        *uint_ptr = snmpinpkts;
+        break;
+      case 2: /* snmpOutPkts */
+        *uint_ptr = snmpoutpkts;
+        break;
+      case 3: /* snmpInBadVersions */
+        *uint_ptr = snmpinbadversions;
+        break;
+      case 4: /* snmpInBadCommunityNames */
+        *uint_ptr = snmpinbadcommunitynames;
+        break;
+      case 5: /* snmpInBadCommunityUses */
+        *uint_ptr = snmpinbadcommunityuses;
+        break;
+      case 6: /* snmpInASNParseErrs */
+        *uint_ptr = snmpinasnparseerrs;
+        break;
+      case 8: /* snmpInTooBigs */
+        *uint_ptr = snmpintoobigs;
+        break;
+      case 9: /* snmpInNoSuchNames */
+        *uint_ptr = snmpinnosuchnames;
+        break;
+      case 10: /* snmpInBadValues */
+        *uint_ptr = snmpinbadvalues;
+        break;
+      case 11: /* snmpInReadOnlys */
+        *uint_ptr = snmpinreadonlys;
+        break;
+      case 12: /* snmpInGenErrs */
+        *uint_ptr = snmpingenerrs;
+        break;
+      case 13: /* snmpInTotalReqVars */
+        *uint_ptr = snmpintotalreqvars;
+        break;
+      case 14: /* snmpInTotalSetVars */
+        *uint_ptr = snmpintotalsetvars;
+        break;
+      case 15: /* snmpInGetRequests */
+        *uint_ptr = snmpingetrequests;
+        break;
+      case 16: /* snmpInGetNexts */
+        *uint_ptr = snmpingetnexts;
+        break;
+      case 17: /* snmpInSetRequests */
+        *uint_ptr = snmpinsetrequests;
+        break;
+      case 18: /* snmpInGetResponses */
+        *uint_ptr = snmpingetresponses;
+        break;
+      case 19: /* snmpInTraps */
+        *uint_ptr = snmpintraps;
+        break;
+      case 20: /* snmpOutTooBigs */
+        *uint_ptr = snmpouttoobigs;
+        break;
+      case 21: /* snmpOutNoSuchNames */
+        *uint_ptr = snmpoutnosuchnames;
+        break;
+      case 22: /* snmpOutBadValues */
+        *uint_ptr = snmpoutbadvalues;
+        break;
+      case 24: /* snmpOutGenErrs */
+        *uint_ptr = snmpoutgenerrs;
+        break;
+      case 25: /* snmpOutGetRequests */
+        *uint_ptr = snmpoutgetrequests;
+        break;
+      case 26: /* snmpOutGetNexts */
+        *uint_ptr = snmpoutgetnexts;
+        break;
+      case 27: /* snmpOutSetRequests */
+        *uint_ptr = snmpoutsetrequests;
+        break;
+      case 28: /* snmpOutGetResponses */
+        *uint_ptr = snmpoutgetresponses;
+        break;
+      case 29: /* snmpOutTraps */
+        *uint_ptr = snmpouttraps;
+        break;
+      case 30: /* snmpEnableAuthenTraps */
+        *uint_ptr = *snmpenableauthentraps_ptr;
+        break;
+  };
+}
+
+/**
+ * Test snmp object value before setting.
+ *
+ * @param od is the object definition
+ * @param len return value space (in bytes)
+ * @param value points to (varbind) space to copy value from.
+ */
+static u8_t
+snmp_set_test(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id, set_ok;
+
+  LWIP_UNUSED_ARG(len);
+  set_ok = 0;
+  id = od->id_inst_ptr[0];
+  if (id == 30)
+  {
+    /* snmpEnableAuthenTraps */
+    s32_t *sint_ptr = value;
+
+    if (snmpenableauthentraps_ptr != &snmpenableauthentraps_default)
+    {
+      /* we should have writable non-volatile mem here */
+      if ((*sint_ptr == 1) || (*sint_ptr == 2))
+      {
+        set_ok = 1;
+      }
+    }
+    else
+    {
+      /* const or hardwired value */
+      if (*sint_ptr == snmpenableauthentraps_default)
+      {
+        set_ok = 1;
+      }
+    }
+  }
+  return set_ok;
+}
+
+static void
+snmp_set_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+
+  LWIP_UNUSED_ARG(len);
+  id = od->id_inst_ptr[0];
+  if (id == 30)
+  {
+    /* snmpEnableAuthenTraps */
+    s32_t *sint_ptr = value;
+    *snmpenableauthentraps_ptr = *sint_ptr;
+  }
+}
+
+#endif /* LWIP_SNMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/snmp/mib_structs.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/snmp/mib_structs.c
new file mode 100644
index 0000000..39a2949
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/snmp/mib_structs.c
@@ -0,0 +1,1183 @@
+/**
+ * @file
+ * MIB tree access/construction functions.
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/snmp_structs.h"
+#include "lwip/mem.h"
+
+/** .iso.org.dod.internet address prefix, @see snmp_iso_*() */
+const s32_t prefix[4] = {1, 3, 6, 1};
+
+#define NODE_STACK_SIZE (LWIP_SNMP_OBJ_ID_LEN)
+/** node stack entry (old news?) */
+struct nse
+{
+  /** right child */
+  struct mib_node* r_ptr;
+  /** right child identifier */
+  s32_t r_id;
+  /** right child next level */
+  u8_t r_nl;
+};
+static u8_t node_stack_cnt;
+static struct nse node_stack[NODE_STACK_SIZE];
+
+/**
+ * Pushes nse struct onto stack.
+ */
+static void
+push_node(struct nse* node)
+{
+  LWIP_ASSERT("node_stack_cnt < NODE_STACK_SIZE",node_stack_cnt < NODE_STACK_SIZE);
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("push_node() node=%p id=%"S32_F"\n",(void*)(node->r_ptr),node->r_id));
+  if (node_stack_cnt < NODE_STACK_SIZE)
+  {
+    node_stack[node_stack_cnt] = *node;
+    node_stack_cnt++;
+  }
+}
+
+/**
+ * Pops nse struct from stack.
+ */
+static void
+pop_node(struct nse* node)
+{
+  if (node_stack_cnt > 0)
+  {
+    node_stack_cnt--;
+    *node = node_stack[node_stack_cnt];
+  }
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("pop_node() node=%p id=%"S32_F"\n",(void *)(node->r_ptr),node->r_id));
+}
+
+/**
+ * Conversion from ifIndex to lwIP netif
+ * @param ifindex is a s32_t object sub-identifier
+ * @param netif points to returned netif struct pointer
+ */
+void
+snmp_ifindextonetif(s32_t ifindex, struct netif **netif)
+{
+  struct netif *nif = netif_list;
+  u16_t i, ifidx;
+
+  ifidx = ifindex - 1;
+  i = 0;
+  while ((nif != NULL) && (i < ifidx))
+  {
+    nif = nif->next;
+    i++;
+  }
+  *netif = nif;
+}
+
+/**
+ * Conversion from lwIP netif to ifIndex
+ * @param netif points to a netif struct
+ * @param ifidx points to s32_t object sub-identifier
+ */
+void
+snmp_netiftoifindex(struct netif *netif, s32_t *ifidx)
+{
+  struct netif *nif = netif_list;
+  u16_t i;
+
+  i = 0;
+  while ((nif != NULL) && (nif != netif))
+  {
+    nif = nif->next;
+    i++;
+  }
+  *ifidx = i+1;
+}
+
+/**
+ * Conversion from oid to lwIP ip_addr
+ * @param ident points to s32_t ident[4] input
+ * @param ip points to output struct
+ */
+void
+snmp_oidtoip(s32_t *ident, struct ip_addr *ip)
+{
+  u32_t ipa;
+
+  ipa = ident[0];
+  ipa <<= 8;
+  ipa |= ident[1];
+  ipa <<= 8;
+  ipa |= ident[2];
+  ipa <<= 8;
+  ipa |= ident[3];
+  ip->addr = ipa;
+}
+
+/**
+ * Conversion from lwIP ip_addr to oid
+ * @param ip points to input struct
+ * @param ident points to s32_t ident[4] output
+ */
+void
+snmp_iptooid(struct ip_addr *ip, s32_t *ident)
+{
+  u32_t ipa;
+
+  ipa = ip->addr;
+  ident[0] = (ipa >> 24) & 0xff;
+  ident[1] = (ipa >> 16) & 0xff;
+  ident[2] = (ipa >> 8) & 0xff;
+  ident[3] = ipa & 0xff;
+}
+
+struct mib_list_node *
+snmp_mib_ln_alloc(s32_t id)
+{
+  struct mib_list_node *ln;
+
+  ln = (struct mib_list_node *)mem_malloc(sizeof(struct mib_list_node));
+  if (ln != NULL)
+  {
+    ln->prev = NULL;
+    ln->next = NULL;
+    ln->objid = id;
+    ln->nptr = NULL;
+  }
+  return ln;
+}
+
+void
+snmp_mib_ln_free(struct mib_list_node *ln)
+{
+  mem_free(ln);
+}
+
+struct mib_list_rootnode *
+snmp_mib_lrn_alloc(void)
+{
+  struct mib_list_rootnode *lrn;
+
+  lrn = (struct mib_list_rootnode*)mem_malloc(sizeof(struct mib_list_rootnode));
+  if (lrn != NULL)
+  {
+    lrn->get_object_def = noleafs_get_object_def;
+    lrn->get_value = noleafs_get_value;
+    lrn->set_test = noleafs_set_test;
+    lrn->set_value = noleafs_set_value;
+    lrn->node_type = MIB_NODE_LR;
+    lrn->maxlength = 0;
+    lrn->head = NULL;
+    lrn->tail = NULL;
+    lrn->count = 0;
+  }
+  return lrn;
+}
+
+void
+snmp_mib_lrn_free(struct mib_list_rootnode *lrn)
+{
+  mem_free(lrn);
+}
+
+/**
+ * Inserts node in idx list in a sorted
+ * (ascending order) fashion and
+ * allocates the node if needed.
+ *
+ * @param rn points to the root node
+ * @param objid is the object sub identifier
+ * @param insn points to a pointer to the inserted node
+ *   used for constructing the tree.
+ * @return -1 if failed, 1 if inserted, 2 if present.
+ */
+s8_t
+snmp_mib_node_insert(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **insn)
+{
+  struct mib_list_node *nn;
+  s8_t insert;
+
+  LWIP_ASSERT("rn != NULL",rn != NULL);
+
+  /* -1 = malloc failure, 0 = not inserted, 1 = inserted, 2 = was present */
+  insert = 0;
+  if (rn->head == NULL)
+  {
+    /* empty list, add first node */
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc empty list objid==%"S32_F"\n",objid));
+    nn = snmp_mib_ln_alloc(objid);
+    if (nn != NULL)
+    {
+      rn->head = nn;
+      rn->tail = nn;
+      *insn = nn;
+      insert = 1;
+    }
+    else
+    {
+      insert = -1;
+    }
+  }
+  else
+  {
+    struct mib_list_node *n;
+    /* at least one node is present */
+    n = rn->head;
+    while ((n != NULL) && (insert == 0))
+    {
+      if (n->objid == objid)
+      {
+        /* node is already there */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("node already there objid==%"S32_F"\n",objid));
+        *insn = n;
+        insert = 2;
+      }
+      else if (n->objid < objid)
+      {
+        if (n->next == NULL)
+        {
+          /* alloc and insert at the tail */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc ins tail objid==%"S32_F"\n",objid));
+          nn = snmp_mib_ln_alloc(objid);
+          if (nn != NULL)
+          {
+            nn->next = NULL;
+            nn->prev = n;
+            n->next = nn;
+            rn->tail = nn;
+            *insn = nn;
+            insert = 1;
+          }
+          else
+          {
+            /* insertion failure */
+            insert = -1;
+          }
+        }
+        else
+        {
+          /* there's more to explore: traverse list */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("traverse list\n"));
+          n = n->next;
+        }
+      }
+      else
+      {
+        /* n->objid > objid */
+        /* alloc and insert between n->prev and n */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc ins n->prev, objid==%"S32_F", n\n",objid));
+        nn = snmp_mib_ln_alloc(objid);
+        if (nn != NULL)
+        {
+          if (n->prev == NULL)
+          {
+            /* insert at the head */
+            nn->next = n;
+            nn->prev = NULL;
+            rn->head = nn;
+            n->prev = nn;
+          }
+          else
+          {
+            /* insert in the middle */
+            nn->next = n;
+            nn->prev = n->prev;
+            n->prev->next = nn;
+            n->prev = nn;
+          }
+          *insn = nn;
+          insert = 1;
+        }
+        else
+        {
+          /* insertion failure */
+          insert = -1;
+        }
+      }
+    }
+  }
+  if (insert == 1)
+  {
+    rn->count += 1;
+  }
+  LWIP_ASSERT("insert != 0",insert != 0);
+  return insert;
+}
+
+/**
+ * Finds node in idx list and returns deletion mark.
+ *
+ * @param rn points to the root node
+ * @param objid  is the object sub identifier
+ * @param fn returns pointer to found node
+ * @return 0 if not found, 1 if deletable,
+ *   2 can't delete (2 or more children), 3 not a list_node
+ */
+s8_t
+snmp_mib_node_find(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **fn)
+{
+  s8_t fc;
+  struct mib_list_node *n;
+
+  LWIP_ASSERT("rn != NULL",rn != NULL);
+  n = rn->head;
+  while ((n != NULL) && (n->objid != objid))
+  {
+    n = n->next;
+  }
+  if (n == NULL)
+  {
+    fc = 0;
+  }
+  else if (n->nptr == NULL)
+  {
+    /* leaf, can delete node */
+    fc = 1;
+  }
+  else
+  {
+    struct mib_list_rootnode *r;
+
+    if (n->nptr->node_type == MIB_NODE_LR)
+    {
+      r = (struct mib_list_rootnode *)n->nptr;
+      if (r->count > 1)
+      {
+        /* can't delete node */
+        fc = 2;
+      }
+      else
+      {
+        /* count <= 1, can delete node */
+        fc = 1;
+      }
+    }
+    else
+    {
+      /* other node type */
+      fc = 3;
+    }
+  }
+  *fn = n;
+  return fc;
+}
+
+/**
+ * Removes node from idx list
+ * if it has a single child left.
+ *
+ * @param rn points to the root node
+ * @param n points to the node to delete
+ * @return the nptr to be freed by caller
+ */
+struct mib_list_rootnode *
+snmp_mib_node_delete(struct mib_list_rootnode *rn, struct mib_list_node *n)
+{
+  struct mib_list_rootnode *next;
+
+  LWIP_ASSERT("rn != NULL",rn != NULL);
+  LWIP_ASSERT("n != NULL",n != NULL);
+
+  /* caller must remove this sub-tree */
+  next = (struct mib_list_rootnode*)(n->nptr);
+  rn->count -= 1;
+
+  if (n == rn->head)
+  {
+    rn->head = n->next;
+    if (n->next != NULL)
+    {
+      /* not last node, new list begin */
+      n->next->prev = NULL;
+    }
+  }
+  else if (n == rn->tail)
+  {
+    rn->tail = n->prev;
+    if (n->prev != NULL)
+    {
+      /* not last node, new list end */
+      n->prev->next = NULL;
+    }
+  }
+  else
+  {
+    /* node must be in the middle */
+    n->prev->next = n->next;
+    n->next->prev = n->prev;
+  }
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("free list objid==%"S32_F"\n",n->objid));
+  snmp_mib_ln_free(n);
+  if (rn->count == 0)
+  {
+    rn->head = NULL;
+    rn->tail = NULL;
+  }
+  return next;
+}
+
+
+
+/**
+ * Searches tree for the supplied (scalar?) object identifier.
+ *
+ * @param node points to the root of the tree ('.internet')
+ * @param ident_len the length of the supplied object identifier
+ * @param ident points to the array of sub identifiers
+ * @param np points to the found object instance (rerurn)
+ * @return pointer to the requested parent (!) node if success, NULL otherwise
+ */
+struct mib_node *
+snmp_search_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_name_ptr *np)
+{
+  u8_t node_type, ext_level;
+
+  ext_level = 0;
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("node==%p *ident==%"S32_F"\n",(void*)node,*ident));
+  while (node != NULL)
+  {
+    node_type = node->node_type;
+    if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA))
+    {
+      struct mib_array_node *an;
+      u16_t i;
+
+      if (ident_len > 0)
+      {
+        /* array node (internal ROM or RAM, fixed length) */
+        an = (struct mib_array_node *)node;
+        i = 0;
+        while ((i < an->maxlength) && (an->objid[i] != *ident))
+        {
+          i++;
+        }
+        if (i < an->maxlength)
+        {
+          /* found it, if available proceed to child, otherwise inspect leaf */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("an->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,an->objid[i],*ident));
+          if (an->nptr[i] == NULL)
+          {
+            /* a scalar leaf OR table,
+               inspect remaining instance number / table index */
+            np->ident_len = ident_len;
+            np->ident = ident;
+            return (struct mib_node*)an;
+          }
+          else
+          {
+            /* follow next child pointer */
+            ident++;
+            ident_len--;
+            node = an->nptr[i];
+          }
+        }
+        else
+        {
+          /* search failed, identifier mismatch (nosuchname) */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("an search failed *ident==%"S32_F"\n",*ident));
+          return NULL;
+        }
+      }
+      else
+      {
+        /* search failed, short object identifier (nosuchname) */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("an search failed, short object identifier\n"));
+        return NULL;
+      }
+    }
+    else if(node_type == MIB_NODE_LR)
+    {
+      struct mib_list_rootnode *lrn;
+      struct mib_list_node *ln;
+
+      if (ident_len > 0)
+      {
+        /* list root node (internal 'RAM', variable length) */
+        lrn = (struct mib_list_rootnode *)node;
+        ln = lrn->head;
+        /* iterate over list, head to tail */
+        while ((ln != NULL) && (ln->objid != *ident))
+        {
+          ln = ln->next;
+        }
+        if (ln != NULL)
+        {
+          /* found it, proceed to child */;
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln->objid==%"S32_F" *ident==%"S32_F"\n",ln->objid,*ident));
+          if (ln->nptr == NULL)
+          {
+            np->ident_len = ident_len;
+            np->ident = ident;
+            return (struct mib_node*)lrn;
+          }
+          else
+          {
+            /* follow next child pointer */
+            ident_len--;
+            ident++;
+            node = ln->nptr;
+          }
+        }
+        else
+        {
+          /* search failed */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln search failed *ident==%"S32_F"\n",*ident));
+          return NULL;
+        }
+      }
+      else
+      {
+        /* search failed, short object identifier (nosuchname) */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln search failed, short object identifier\n"));
+        return NULL;
+      }
+    }
+    else if(node_type == MIB_NODE_EX)
+    {
+      struct mib_external_node *en;
+      u16_t i, len;
+
+      if (ident_len > 0)
+      {
+        /* external node (addressing and access via functions) */
+        en = (struct mib_external_node *)node;
+
+        i = 0;
+        len = en->level_length(en->addr_inf,ext_level);
+        while ((i < len) && (en->ident_cmp(en->addr_inf,ext_level,i,*ident) != 0))
+        {
+          i++;
+        }
+        if (i < len)
+        {
+          s32_t debug_id;
+
+          en->get_objid(en->addr_inf,ext_level,i,&debug_id);
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("en->objid==%"S32_F" *ident==%"S32_F"\n",debug_id,*ident));
+          if ((ext_level + 1) == en->tree_levels)
+          {
+            np->ident_len = ident_len;
+            np->ident = ident;
+            return (struct mib_node*)en;
+          }
+          else
+          {
+            /* found it, proceed to child */
+            ident_len--;
+            ident++;
+            ext_level++;
+          }
+        }
+        else
+        {
+          /* search failed */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("en search failed *ident==%"S32_F"\n",*ident));
+          return NULL;
+        }
+      }
+      else
+      {
+        /* search failed, short object identifier (nosuchname) */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("en search failed, short object identifier\n"));
+        return NULL;
+      }
+    }
+    else if (node_type == MIB_NODE_SC)
+    {
+      mib_scalar_node *sn;
+
+      sn = (mib_scalar_node *)node;
+      if ((ident_len == 1) && (*ident == 0))
+      {
+        np->ident_len = ident_len;
+        np->ident = ident;
+        return (struct mib_node*)sn;
+      }
+      else
+      {
+        /* search failed, short object identifier (nosuchname) */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed, invalid object identifier length\n"));
+        return NULL;
+      }
+    }
+    else
+    {
+      /* unknown node_type */
+      LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed node_type %"U16_F" unkown\n",(u16_t)node_type));
+      return NULL;
+    }
+  }
+  /* done, found nothing */
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed node==%p\n",(void*)node));
+  return NULL;
+}
+
+/**
+ * Test table for presence of at least one table entry.
+ */
+static u8_t
+empty_table(struct mib_node *node)
+{
+  u8_t node_type;
+  u8_t empty = 0;
+
+  if (node != NULL)
+  {
+    node_type = node->node_type;
+    if (node_type == MIB_NODE_LR)
+    {
+      struct mib_list_rootnode *lrn;
+      lrn = (struct mib_list_rootnode *)node;
+      if ((lrn->count == 0) || (lrn->head == NULL))
+      {
+        empty = 1;
+      }
+    }
+    else if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA))
+    {
+      struct mib_array_node *an;
+      an = (struct mib_array_node *)node;
+      if ((an->maxlength == 0) || (an->nptr == NULL))
+      {
+        empty = 1;
+      }
+    }
+    else if (node_type == MIB_NODE_EX)
+    {
+      struct mib_external_node *en;
+      en = (struct mib_external_node *)node;
+      if (en->tree_levels == 0)
+      {
+        empty = 1;
+      }
+    }
+  }
+  return empty;
+}
+
+/**
+ * Tree expansion.
+ */
+struct mib_node *
+snmp_expand_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret)
+{
+  u8_t node_type, ext_level, climb_tree;
+
+  ext_level = 0;
+  /* reset node stack */
+  node_stack_cnt = 0;
+  while (node != NULL)
+  {
+    climb_tree = 0;
+    node_type = node->node_type;
+    if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA))
+    {
+      struct mib_array_node *an;
+      u16_t i;
+
+      /* array node (internal ROM or RAM, fixed length) */
+      an = (struct mib_array_node *)node;
+      if (ident_len > 0)
+      {
+        i = 0;
+        while ((i < an->maxlength) && (an->objid[i] < *ident))
+        {
+          i++;
+        }
+        if (i < an->maxlength)
+        {
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("an->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,an->objid[i],*ident));
+          /* add identifier to oidret */
+          oidret->id[oidret->len] = an->objid[i];
+          (oidret->len)++;
+
+          if (an->nptr[i] == NULL)
+          {
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("leaf node\n"));
+            /* leaf node (e.g. in a fixed size table) */
+            if (an->objid[i] > *ident)
+            {
+              return (struct mib_node*)an;
+            }
+            else if ((i + 1) < an->maxlength)
+            {
+              /* an->objid[i] == *ident */
+              (oidret->len)--;
+              oidret->id[oidret->len] = an->objid[i + 1];
+              (oidret->len)++;
+              return (struct mib_node*)an;
+            }
+            else
+            {
+              /* (i + 1) == an->maxlength */
+              (oidret->len)--;
+              climb_tree = 1;
+            }
+          }
+          else
+          {
+            u8_t j;
+            struct nse cur_node;
+
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("non-leaf node\n"));
+            /* non-leaf, store right child ptr and id */
+            j = i + 1;
+            while ((j < an->maxlength) && (empty_table(an->nptr[j])))
+            {
+              j++;
+            }
+            if (j < an->maxlength)
+            {
+              cur_node.r_ptr = an->nptr[j];
+              cur_node.r_id = an->objid[j];
+              cur_node.r_nl = 0;
+            }
+            else
+            {
+              cur_node.r_ptr = NULL;
+            }
+            push_node(&cur_node);
+            if (an->objid[i] == *ident)
+            {
+              ident_len--;
+              ident++;
+            }
+            else
+            {
+              /* an->objid[i] < *ident */
+              ident_len = 0;
+            }
+            /* follow next child pointer */
+            node = an->nptr[i];
+          }
+        }
+        else
+        {
+          /* i == an->maxlength */
+          climb_tree = 1;
+        }
+      }
+      else
+      {
+        u8_t j;
+        /* ident_len == 0, complete with leftmost '.thing' */
+        j = 0;
+        while ((j < an->maxlength) && empty_table(an->nptr[j]))
+        {
+          j++;
+        }
+        if (j < an->maxlength)
+        {
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("left an->objid[j]==%"S32_F"\n",an->objid[j]));
+          oidret->id[oidret->len] = an->objid[j];
+          (oidret->len)++;
+          if (an->nptr[j] == NULL)
+          {
+            /* leaf node */
+            return (struct mib_node*)an;
+          }
+          else
+          {
+            /* no leaf, continue */
+            node = an->nptr[j];
+          }
+        }
+        else
+        {
+          /* j == an->maxlength */
+          climb_tree = 1;
+        }
+      }
+    }
+    else if(node_type == MIB_NODE_LR)
+    {
+      struct mib_list_rootnode *lrn;
+      struct mib_list_node *ln;
+
+      /* list root node (internal 'RAM', variable length) */
+      lrn = (struct mib_list_rootnode *)node;
+      if (ident_len > 0)
+      {
+        ln = lrn->head;
+        /* iterate over list, head to tail */
+        while ((ln != NULL) && (ln->objid < *ident))
+        {
+          ln = ln->next;
+        }
+        if (ln != NULL)
+        {
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln->objid==%"S32_F" *ident==%"S32_F"\n",ln->objid,*ident));
+          oidret->id[oidret->len] = ln->objid;
+          (oidret->len)++;
+          if (ln->nptr == NULL)
+          {
+            /* leaf node */
+            if (ln->objid > *ident)
+            {
+              return (struct mib_node*)lrn;
+            }
+            else if (ln->next != NULL)
+            {
+              /* ln->objid == *ident */
+              (oidret->len)--;
+              oidret->id[oidret->len] = ln->next->objid;
+              (oidret->len)++;
+              return (struct mib_node*)lrn;
+            }
+            else
+            {
+              /* ln->next == NULL */
+              (oidret->len)--;
+              climb_tree = 1;
+            }
+          }
+          else
+          {
+            struct mib_list_node *jn;
+            struct nse cur_node;
+
+            /* non-leaf, store right child ptr and id */
+            jn = ln->next;
+            while ((jn != NULL) && empty_table(jn->nptr))
+            {
+              jn = jn->next;
+            }
+            if (jn != NULL)
+            {
+              cur_node.r_ptr = jn->nptr;
+              cur_node.r_id = jn->objid;
+              cur_node.r_nl = 0;
+            }
+            else
+            {
+              cur_node.r_ptr = NULL;
+            }
+            push_node(&cur_node);
+            if (ln->objid == *ident)
+            {
+              ident_len--;
+              ident++;
+            }
+            else
+            {
+              /* ln->objid < *ident */
+              ident_len = 0;
+            }
+            /* follow next child pointer */
+            node = ln->nptr;
+          }
+
+        }
+        else
+        {
+          /* ln == NULL */
+          climb_tree = 1;
+        }
+      }
+      else
+      {
+        struct mib_list_node *jn;
+        /* ident_len == 0, complete with leftmost '.thing' */
+        jn = lrn->head;
+        while ((jn != NULL) && empty_table(jn->nptr))
+        {
+          jn = jn->next;
+        }
+        if (jn != NULL)
+        {
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("left jn->objid==%"S32_F"\n",jn->objid));
+          oidret->id[oidret->len] = jn->objid;
+          (oidret->len)++;
+          if (jn->nptr == NULL)
+          {
+            /* leaf node */
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("jn->nptr == NULL\n"));
+            return (struct mib_node*)lrn;
+          }
+          else
+          {
+            /* no leaf, continue */
+            node = jn->nptr;
+          }
+        }
+        else
+        {
+          /* jn == NULL */
+          climb_tree = 1;
+        }
+      }
+    }
+    else if(node_type == MIB_NODE_EX)
+    {
+      struct mib_external_node *en;
+      s32_t ex_id;
+
+      /* external node (addressing and access via functions) */
+      en = (struct mib_external_node *)node;
+      if (ident_len > 0)
+      {
+        u16_t i, len;
+
+        i = 0;
+        len = en->level_length(en->addr_inf,ext_level);
+        while ((i < len) && (en->ident_cmp(en->addr_inf,ext_level,i,*ident) < 0))
+        {
+          i++;
+        }
+        if (i < len)
+        {
+          /* add identifier to oidret */
+          en->get_objid(en->addr_inf,ext_level,i,&ex_id);
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("en->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,ex_id,*ident));
+          oidret->id[oidret->len] = ex_id;
+          (oidret->len)++;
+
+          if ((ext_level + 1) == en->tree_levels)
+          {
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("leaf node\n"));
+            /* leaf node */
+            if (ex_id > *ident)
+            {
+              return (struct mib_node*)en;
+            }
+            else if ((i + 1) < len)
+            {
+              /* ex_id == *ident */
+              en->get_objid(en->addr_inf,ext_level,i + 1,&ex_id);
+              (oidret->len)--;
+              oidret->id[oidret->len] = ex_id;
+              (oidret->len)++;
+              return (struct mib_node*)en;
+            }
+            else
+            {
+              /* (i + 1) == len */
+              (oidret->len)--;
+              climb_tree = 1;
+            }
+          }
+          else
+          {
+            u8_t j;
+            struct nse cur_node;
+
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("non-leaf node\n"));
+            /* non-leaf, store right child ptr and id */
+            j = i + 1;
+            if (j < len)
+            {
+              /* right node is the current external node */
+              cur_node.r_ptr = node;
+              en->get_objid(en->addr_inf,ext_level,j,&cur_node.r_id);
+              cur_node.r_nl = ext_level + 1;
+            }
+            else
+            {
+              cur_node.r_ptr = NULL;
+            }
+            push_node(&cur_node);
+            if (en->ident_cmp(en->addr_inf,ext_level,i,*ident) == 0)
+            {
+              ident_len--;
+              ident++;
+            }
+            else
+            {
+              /* external id < *ident */
+              ident_len = 0;
+            }
+            /* proceed to child */
+            ext_level++;
+          }
+        }
+        else
+        {
+          /* i == len (en->level_len()) */
+          climb_tree = 1;
+        }
+      }
+      else
+      {
+        /* ident_len == 0, complete with leftmost '.thing' */
+        en->get_objid(en->addr_inf,ext_level,0,&ex_id);
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("left en->objid==%"S32_F"\n",ex_id));
+        oidret->id[oidret->len] = ex_id;
+        (oidret->len)++;
+        if ((ext_level + 1) == en->tree_levels)
+        {
+          /* leaf node */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("(ext_level + 1) == en->tree_levels\n"));
+          return (struct mib_node*)en;
+        }
+        else
+        {
+          /* no leaf, proceed to child */
+          ext_level++;
+        }
+      }
+    }
+    else if(node_type == MIB_NODE_SC)
+    {
+      mib_scalar_node *sn;
+
+      /* scalar node  */
+      sn = (mib_scalar_node *)node;
+      if (ident_len > 0)
+      {
+        /* at .0 */
+        climb_tree = 1;
+      }
+      else
+      {
+        /* ident_len == 0, complete object identifier */
+        oidret->id[oidret->len] = 0;
+        (oidret->len)++;
+        /* leaf node */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("completed scalar leaf\n"));
+        return (struct mib_node*)sn;
+      }
+    }
+    else
+    {
+      /* unknown/unhandled node_type */
+      LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed node_type %"U16_F" unkown\n",(u16_t)node_type));
+      return NULL;
+    }
+
+    if (climb_tree)
+    {
+      struct nse child;
+
+      /* find right child ptr */
+      child.r_ptr = NULL;
+      child.r_id = 0;
+      child.r_nl = 0;
+      while ((node_stack_cnt > 0) && (child.r_ptr == NULL))
+      {
+        pop_node(&child);
+        /* trim returned oid */
+        (oidret->len)--;
+      }
+      if (child.r_ptr != NULL)
+      {
+        /* incoming ident is useless beyond this point */
+        ident_len = 0;
+        oidret->id[oidret->len] = child.r_id;
+        oidret->len++;
+        node = child.r_ptr;
+        ext_level = child.r_nl;
+      }
+      else
+      {
+        /* tree ends here ... */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed, tree ends here\n"));
+        return NULL;
+      }
+    }
+  }
+  /* done, found nothing */
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed node==%p\n",(void*)node));
+  return NULL;
+}
+
+/**
+ * Test object identifier for the iso.org.dod.internet prefix.
+ *
+ * @param ident_len the length of the supplied object identifier
+ * @param ident points to the array of sub identifiers
+ * @return 1 if it matches, 0 otherwise
+ */
+u8_t
+snmp_iso_prefix_tst(u8_t ident_len, s32_t *ident)
+{
+  if ((ident_len > 3) &&
+      (ident[0] == 1) && (ident[1] == 3) &&
+      (ident[2] == 6) && (ident[3] == 1))
+  {
+    return 1;
+  }
+  else
+  {
+    return 0;
+  }
+}
+
+/**
+ * Expands object identifier to the iso.org.dod.internet
+ * prefix for use in getnext operation.
+ *
+ * @param ident_len the length of the supplied object identifier
+ * @param ident points to the array of sub identifiers
+ * @param oidret points to returned expanded object identifier
+ * @return 1 if it matches, 0 otherwise
+ *
+ * @note ident_len 0 is allowed, expanding to the first known object id!!
+ */
+u8_t
+snmp_iso_prefix_expand(u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret)
+{
+  const s32_t *prefix_ptr;
+  s32_t *ret_ptr;
+  u8_t i;
+
+  i = 0;
+  prefix_ptr = &prefix[0];
+  ret_ptr = &oidret->id[0];
+  ident_len = ((ident_len < 4)?ident_len:4);
+  while ((i < ident_len) && ((*ident) <= (*prefix_ptr)))
+  {
+    *ret_ptr++ = *prefix_ptr++;
+    ident++;
+    i++;
+  }
+  if (i == ident_len)
+  {
+    /* match, complete missing bits */
+    while (i < 4)
+    {
+      *ret_ptr++ = *prefix_ptr++;
+      i++;
+    }
+    oidret->len = i;
+    return 1;
+  }
+  else
+  {
+    /* i != ident_len */
+    return 0;
+  }
+}
+
+#endif /* LWIP_SNMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/snmp/msg_in.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/snmp/msg_in.c
new file mode 100644
index 0000000..d0c3c75
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/snmp/msg_in.c
@@ -0,0 +1,1454 @@
+/**
+ * @file
+ * SNMP input message processing (RFC1157).
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/ip_addr.h"
+#include "lwip/mem.h"
+#include "lwip/udp.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+#include "lwip/snmp_asn1.h"
+#include "lwip/snmp_msg.h"
+#include "lwip/snmp_structs.h"
+
+#include 
+
+/* public (non-static) constants */
+/** SNMP v1 == 0 */
+const s32_t snmp_version = 0;
+/** default SNMP community string */
+const char snmp_publiccommunity[7] = "public";
+
+/* statically allocated buffers for SNMP_CONCURRENT_REQUESTS */
+struct snmp_msg_pstat msg_input_list[SNMP_CONCURRENT_REQUESTS];
+/* UDP Protocol Control Block */
+struct udp_pcb *snmp1_pcb;
+
+static void snmp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port);
+static err_t snmp_pdu_header_check(struct pbuf *p, u16_t ofs, u16_t pdu_len, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat);
+static err_t snmp_pdu_dec_varbindlist(struct pbuf *p, u16_t ofs, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat);
+
+
+/**
+ * Starts SNMP Agent.
+ * Allocates UDP pcb and binds it to IP_ADDR_ANY port 161.
+ */
+void
+snmp_init(void)
+{
+  struct snmp_msg_pstat *msg_ps;
+  u8_t i;
+
+  snmp1_pcb = udp_new();
+  if (snmp1_pcb != NULL)
+  {
+    udp_recv(snmp1_pcb, snmp_recv, (void *)SNMP_IN_PORT);
+    udp_bind(snmp1_pcb, IP_ADDR_ANY, SNMP_IN_PORT);
+  }
+  msg_ps = &msg_input_list[0];
+  for (i=0; istate = SNMP_MSG_EMPTY;
+    msg_ps->error_index = 0;
+    msg_ps->error_status = SNMP_ES_NOERROR;
+    msg_ps++;
+  }
+  trap_msg.pcb = snmp1_pcb;
+  /* The coldstart trap will only be output
+     if our outgoing interface is up & configured  */
+  snmp_coldstart_trap();
+}
+
+static void
+snmp_error_response(struct snmp_msg_pstat *msg_ps, u8_t error)
+{
+  snmp_varbind_list_free(&msg_ps->outvb);
+  msg_ps->outvb = msg_ps->invb;
+  msg_ps->invb.head = NULL;
+  msg_ps->invb.tail = NULL;
+  msg_ps->invb.count = 0;
+  msg_ps->error_status = error;
+  msg_ps->error_index = 1 + msg_ps->vb_idx;
+  snmp_send_response(msg_ps);
+  snmp_varbind_list_free(&msg_ps->outvb);
+  msg_ps->state = SNMP_MSG_EMPTY;
+}
+
+static void
+snmp_ok_response(struct snmp_msg_pstat *msg_ps)
+{
+  err_t err_ret;
+
+  err_ret = snmp_send_response(msg_ps);
+  if (err_ret == ERR_MEM)
+  {
+    /* serious memory problem, can't return tooBig */
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event = %"S32_F"\n",msg_ps->error_status));
+  }
+  /* free varbinds (if available) */
+  snmp_varbind_list_free(&msg_ps->invb);
+  snmp_varbind_list_free(&msg_ps->outvb);
+  msg_ps->state = SNMP_MSG_EMPTY;
+}
+
+/**
+ * Service an internal or external event for SNMP GET.
+ *
+ * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1)
+ * @param msg_ps points to the assosicated message process state
+ */
+static void
+snmp_msg_get_event(u8_t request_id, struct snmp_msg_pstat *msg_ps)
+{
+  LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_get_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state));
+
+  if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF)
+  {
+    struct mib_external_node *en;
+    struct snmp_name_ptr np;
+
+    /* get_object_def() answer*/
+    en = msg_ps->ext_mib_node;
+    np = msg_ps->ext_name_ptr;
+
+    /* translate answer into a known lifeform */
+    en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def);
+    if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE)
+    {
+      msg_ps->state = SNMP_MSG_EXTERNAL_GET_VALUE;
+      en->get_value_q(request_id, &msg_ps->ext_object_def);
+    }
+    else
+    {
+      en->get_object_def_pc(request_id, np.ident_len, np.ident);
+      /* search failed, object id points to unknown object (nosuchname) */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_VALUE)
+  {
+    struct mib_external_node *en;
+    struct snmp_varbind *vb;
+
+    /* get_value() answer */
+    en = msg_ps->ext_mib_node;
+
+    /* allocate output varbind */
+    vb = (struct snmp_varbind *)mem_malloc(sizeof(struct snmp_varbind));
+    LWIP_ASSERT("vb != NULL",vb != NULL);
+    if (vb != NULL)
+    {
+      vb->next = NULL;
+      vb->prev = NULL;
+
+      /* move name from invb to outvb */
+      vb->ident = msg_ps->vb_ptr->ident;
+      vb->ident_len = msg_ps->vb_ptr->ident_len;
+      /* ensure this memory is refereced once only */
+      msg_ps->vb_ptr->ident = NULL;
+      msg_ps->vb_ptr->ident_len = 0;
+
+      vb->value_type = msg_ps->ext_object_def.asn_type;
+      vb->value_len =  msg_ps->ext_object_def.v_len;
+      if (vb->value_len > 0)
+      {
+        vb->value = mem_malloc(vb->value_len);
+        LWIP_ASSERT("vb->value != NULL",vb->value != NULL);
+        if (vb->value != NULL)
+        {
+          en->get_value_a(request_id, &msg_ps->ext_object_def, vb->value_len, vb->value);
+          snmp_varbind_tail_add(&msg_ps->outvb, vb);
+          /* search again (if vb_idx < msg_ps->invb.count) */
+          msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+          msg_ps->vb_idx += 1;
+        }
+        else
+        {
+          en->get_value_pc(request_id, &msg_ps->ext_object_def);
+          LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: no variable space\n"));
+          msg_ps->vb_ptr->ident = vb->ident;
+          msg_ps->vb_ptr->ident_len = vb->ident_len;
+          mem_free(vb);
+          snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+        }
+      }
+      else
+      {
+        /* vb->value_len == 0, empty value (e.g. empty string) */
+        en->get_value_a(request_id, &msg_ps->ext_object_def, 0, NULL);
+        vb->value = NULL;
+        snmp_varbind_tail_add(&msg_ps->outvb, vb);
+        /* search again (if vb_idx < msg_ps->invb.count) */
+        msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+        msg_ps->vb_idx += 1;
+      }
+    }
+    else
+    {
+      en->get_value_pc(request_id, &msg_ps->ext_object_def);
+      LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: no outvb space\n"));
+      snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+    }
+  }
+
+  while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+         (msg_ps->vb_idx < msg_ps->invb.count))
+  {
+    struct mib_node *mn;
+    struct snmp_name_ptr np;
+
+    if (msg_ps->vb_idx == 0)
+    {
+      msg_ps->vb_ptr = msg_ps->invb.head;
+    }
+    else
+    {
+      msg_ps->vb_ptr = msg_ps->vb_ptr->next;
+    }
+    /** test object identifier for .iso.org.dod.internet prefix */
+    if (snmp_iso_prefix_tst(msg_ps->vb_ptr->ident_len,  msg_ps->vb_ptr->ident))
+    {
+      mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4,
+                             msg_ps->vb_ptr->ident + 4, &np);
+      if (mn != NULL)
+      {
+        if (mn->node_type == MIB_NODE_EX)
+        {
+          /* external object */
+          struct mib_external_node *en = (struct mib_external_node*)mn;
+
+          msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF;
+          /* save en && args in msg_ps!! */
+          msg_ps->ext_mib_node = en;
+          msg_ps->ext_name_ptr = np;
+
+          en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident);
+        }
+        else
+        {
+          /* internal object */
+          struct obj_def object_def;
+
+          msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF;
+          mn->get_object_def(np.ident_len, np.ident, &object_def);
+          if (object_def.instance != MIB_OBJECT_NONE)
+          {
+            mn = mn;
+          }
+          else
+          {
+            /* search failed, object id points to unknown object (nosuchname) */
+            mn =  NULL;
+          }
+          if (mn != NULL)
+          {
+            struct snmp_varbind *vb;
+
+            msg_ps->state = SNMP_MSG_INTERNAL_GET_VALUE;
+            /* allocate output varbind */
+            vb = (struct snmp_varbind *)mem_malloc(sizeof(struct snmp_varbind));
+            LWIP_ASSERT("vb != NULL",vb != NULL);
+            if (vb != NULL)
+            {
+              vb->next = NULL;
+              vb->prev = NULL;
+
+              /* move name from invb to outvb */
+              vb->ident = msg_ps->vb_ptr->ident;
+              vb->ident_len = msg_ps->vb_ptr->ident_len;
+              /* ensure this memory is refereced once only */
+              msg_ps->vb_ptr->ident = NULL;
+              msg_ps->vb_ptr->ident_len = 0;
+
+              vb->value_type = object_def.asn_type;
+              vb->value_len = object_def.v_len;
+              if (vb->value_len > 0)
+              {
+                vb->value = mem_malloc(vb->value_len);
+                LWIP_ASSERT("vb->value != NULL",vb->value != NULL);
+                if (vb->value != NULL)
+                {
+                  mn->get_value(&object_def, vb->value_len, vb->value);
+                  snmp_varbind_tail_add(&msg_ps->outvb, vb);
+                  msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+                  msg_ps->vb_idx += 1;
+                }
+                else
+                {
+                  LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: couldn't allocate variable space\n"));
+                  msg_ps->vb_ptr->ident = vb->ident;
+                  msg_ps->vb_ptr->ident_len = vb->ident_len;
+                  mem_free(vb);
+                  snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+                }
+              }
+              else
+              {
+                /* vb->value_len == 0, empty value (e.g. empty string) */
+                vb->value = NULL;
+                snmp_varbind_tail_add(&msg_ps->outvb, vb);
+                msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+                msg_ps->vb_idx += 1;
+              }
+            }
+            else
+            {
+              LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: couldn't allocate outvb space\n"));
+              snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+            }
+          }
+        }
+      }
+    }
+    else
+    {
+      mn = NULL;
+    }
+    if (mn == NULL)
+    {
+      /* mn == NULL, noSuchName */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+      (msg_ps->vb_idx == msg_ps->invb.count))
+  {
+    snmp_ok_response(msg_ps);
+  }
+}
+
+/**
+ * Service an internal or external event for SNMP GETNEXT.
+ *
+ * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1)
+ * @param msg_ps points to the assosicated message process state
+ */
+static void
+snmp_msg_getnext_event(u8_t request_id, struct snmp_msg_pstat *msg_ps)
+{
+  LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_getnext_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state));
+
+  if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF)
+  {
+    struct mib_external_node *en;
+
+    /* get_object_def() answer*/
+    en = msg_ps->ext_mib_node;
+
+    /* translate answer into a known lifeform */
+    en->get_object_def_a(request_id, 1, &msg_ps->ext_oid.id[msg_ps->ext_oid.len - 1], &msg_ps->ext_object_def);
+    if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE)
+    {
+      msg_ps->state = SNMP_MSG_EXTERNAL_GET_VALUE;
+      en->get_value_q(request_id, &msg_ps->ext_object_def);
+    }
+    else
+    {
+      en->get_object_def_pc(request_id, 1, &msg_ps->ext_oid.id[msg_ps->ext_oid.len - 1]);
+      /* search failed, object id points to unknown object (nosuchname) */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_VALUE)
+  {
+    struct mib_external_node *en;
+    struct snmp_varbind *vb;
+
+    /* get_value() answer */
+    en = msg_ps->ext_mib_node;
+
+    vb = snmp_varbind_alloc(&msg_ps->ext_oid,
+                            msg_ps->ext_object_def.asn_type,
+                            msg_ps->ext_object_def.v_len);
+    if (vb != NULL)
+    {
+      en->get_value_a(request_id, &msg_ps->ext_object_def, vb->value_len, vb->value);
+      snmp_varbind_tail_add(&msg_ps->outvb, vb);
+      msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+      msg_ps->vb_idx += 1;
+    }
+    else
+    {
+      en->get_value_pc(request_id, &msg_ps->ext_object_def);
+      LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_getnext_event: couldn't allocate outvb space\n"));
+      snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+    }
+  }
+
+  while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+         (msg_ps->vb_idx < msg_ps->invb.count))
+  {
+    struct mib_node *mn;
+    struct snmp_obj_id oid;
+
+    if (msg_ps->vb_idx == 0)
+    {
+      msg_ps->vb_ptr = msg_ps->invb.head;
+    }
+    else
+    {
+      msg_ps->vb_ptr = msg_ps->vb_ptr->next;
+    }
+    if (snmp_iso_prefix_expand(msg_ps->vb_ptr->ident_len, msg_ps->vb_ptr->ident, &oid))
+    {
+      if (msg_ps->vb_ptr->ident_len > 3)
+      {
+        /* can offset ident_len and ident */
+        mn = snmp_expand_tree((struct mib_node*)&internet,
+                              msg_ps->vb_ptr->ident_len - 4,
+                              msg_ps->vb_ptr->ident + 4, &oid);
+      }
+      else
+      {
+        /* can't offset ident_len -4, ident + 4 */
+        mn = snmp_expand_tree((struct mib_node*)&internet, 0, NULL, &oid);
+      }
+    }
+    else
+    {
+      mn = NULL;
+    }
+    if (mn != NULL)
+    {
+      if (mn->node_type == MIB_NODE_EX)
+      {
+        /* external object */
+        struct mib_external_node *en = (struct mib_external_node*)mn;
+
+        msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF;
+        /* save en && args in msg_ps!! */
+        msg_ps->ext_mib_node = en;
+        msg_ps->ext_oid = oid;
+
+        en->get_object_def_q(en->addr_inf, request_id, 1, &oid.id[oid.len - 1]);
+      }
+      else
+      {
+        /* internal object */
+        struct obj_def object_def;
+        struct snmp_varbind *vb;
+
+        msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF;
+        mn->get_object_def(1, &oid.id[oid.len - 1], &object_def);
+
+        vb = snmp_varbind_alloc(&oid, object_def.asn_type, object_def.v_len);
+        if (vb != NULL)
+        {
+          msg_ps->state = SNMP_MSG_INTERNAL_GET_VALUE;
+          mn->get_value(&object_def, object_def.v_len, vb->value);
+          snmp_varbind_tail_add(&msg_ps->outvb, vb);
+          msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+          msg_ps->vb_idx += 1;
+        }
+        else
+        {
+          LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv couldn't allocate outvb space\n"));
+          snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+        }
+      }
+    }
+    if (mn == NULL)
+    {
+      /* mn == NULL, noSuchName */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+      (msg_ps->vb_idx == msg_ps->invb.count))
+  {
+    snmp_ok_response(msg_ps);
+  }
+}
+
+/**
+ * Service an internal or external event for SNMP SET.
+ *
+ * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1)
+ * @param msg_ps points to the assosicated message process state
+ */
+static void
+snmp_msg_set_event(u8_t request_id, struct snmp_msg_pstat *msg_ps)
+{
+  LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_set_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state));
+
+  if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF)
+  {
+    struct mib_external_node *en;
+    struct snmp_name_ptr np;
+
+    /* get_object_def() answer*/
+    en = msg_ps->ext_mib_node;
+    np = msg_ps->ext_name_ptr;
+
+    /* translate answer into a known lifeform */
+    en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def);
+    if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE)
+    {
+      msg_ps->state = SNMP_MSG_EXTERNAL_SET_TEST;
+      en->set_test_q(request_id, &msg_ps->ext_object_def);
+    }
+    else
+    {
+      en->get_object_def_pc(request_id, np.ident_len, np.ident);
+      /* search failed, object id points to unknown object (nosuchname) */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  else if (msg_ps->state == SNMP_MSG_EXTERNAL_SET_TEST)
+  {
+    struct mib_external_node *en;
+
+    /* set_test() answer*/
+    en = msg_ps->ext_mib_node;
+
+    if (msg_ps->ext_object_def.access == MIB_OBJECT_READ_WRITE)
+    {
+       if ((msg_ps->ext_object_def.asn_type == msg_ps->vb_ptr->value_type) &&
+           (en->set_test_a(request_id,&msg_ps->ext_object_def,
+                           msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value) != 0))
+      {
+        msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+        msg_ps->vb_idx += 1;
+      }
+      else
+      {
+        en->set_test_pc(request_id,&msg_ps->ext_object_def);
+        /* bad value */
+        snmp_error_response(msg_ps,SNMP_ES_BADVALUE);
+      }
+    }
+    else
+    {
+      en->set_test_pc(request_id,&msg_ps->ext_object_def);
+      /* object not available for set */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF_S)
+  {
+    struct mib_external_node *en;
+    struct snmp_name_ptr np;
+
+    /* get_object_def() answer*/
+    en = msg_ps->ext_mib_node;
+    np = msg_ps->ext_name_ptr;
+
+    /* translate answer into a known lifeform */
+    en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def);
+    if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE)
+    {
+      msg_ps->state = SNMP_MSG_EXTERNAL_SET_VALUE;
+      en->set_value_q(request_id, &msg_ps->ext_object_def,
+                      msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value);
+    }
+    else
+    {
+      en->get_object_def_pc(request_id, np.ident_len, np.ident);
+      /* set_value failed, object has disappeared for some odd reason?? */
+      snmp_error_response(msg_ps,SNMP_ES_GENERROR);
+    }
+  }
+  else if (msg_ps->state == SNMP_MSG_EXTERNAL_SET_VALUE)
+  {
+    struct mib_external_node *en;
+
+    /** set_value_a() */
+    en = msg_ps->ext_mib_node;
+    en->set_value_a(request_id, &msg_ps->ext_object_def,
+      msg_ps->vb_ptr->value_len, msg_ps->vb_ptr->value);
+
+    /** @todo use set_value_pc() if toobig */
+    msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE;
+    msg_ps->vb_idx += 1;
+  }
+
+  /* test all values before setting */
+  while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+         (msg_ps->vb_idx < msg_ps->invb.count))
+  {
+    struct mib_node *mn;
+    struct snmp_name_ptr np;
+
+    if (msg_ps->vb_idx == 0)
+    {
+      msg_ps->vb_ptr = msg_ps->invb.head;
+    }
+    else
+    {
+      msg_ps->vb_ptr = msg_ps->vb_ptr->next;
+    }
+    /** test object identifier for .iso.org.dod.internet prefix */
+    if (snmp_iso_prefix_tst(msg_ps->vb_ptr->ident_len,  msg_ps->vb_ptr->ident))
+    {
+      mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4,
+                             msg_ps->vb_ptr->ident + 4, &np);
+      if (mn != NULL)
+      {
+        if (mn->node_type == MIB_NODE_EX)
+        {
+          /* external object */
+          struct mib_external_node *en = (struct mib_external_node*)mn;
+
+          msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF;
+          /* save en && args in msg_ps!! */
+          msg_ps->ext_mib_node = en;
+          msg_ps->ext_name_ptr = np;
+
+          en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident);
+        }
+        else
+        {
+          /* internal object */
+          struct obj_def object_def;
+
+          msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF;
+          mn->get_object_def(np.ident_len, np.ident, &object_def);
+          if (object_def.instance != MIB_OBJECT_NONE)
+          {
+            mn = mn;
+          }
+          else
+          {
+            /* search failed, object id points to unknown object (nosuchname) */
+            mn = NULL;
+          }
+          if (mn != NULL)
+          {
+            msg_ps->state = SNMP_MSG_INTERNAL_SET_TEST;
+
+            if (object_def.access == MIB_OBJECT_READ_WRITE)
+            {
+              if ((object_def.asn_type == msg_ps->vb_ptr->value_type) &&
+                  (mn->set_test(&object_def,msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value) != 0))
+              {
+                msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+                msg_ps->vb_idx += 1;
+              }
+              else
+              {
+                /* bad value */
+                snmp_error_response(msg_ps,SNMP_ES_BADVALUE);
+              }
+            }
+            else
+            {
+              /* object not available for set */
+              snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+            }
+          }
+        }
+      }
+    }
+    else
+    {
+      mn = NULL;
+    }
+    if (mn == NULL)
+    {
+      /* mn == NULL, noSuchName */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+
+  if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+      (msg_ps->vb_idx == msg_ps->invb.count))
+  {
+    msg_ps->vb_idx = 0;
+    msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE;
+  }
+
+  /* set all values "atomically" (be as "atomic" as possible) */
+  while ((msg_ps->state == SNMP_MSG_INTERNAL_SET_VALUE) &&
+         (msg_ps->vb_idx < msg_ps->invb.count))
+  {
+    struct mib_node *mn;
+    struct snmp_name_ptr np;
+
+    if (msg_ps->vb_idx == 0)
+    {
+      msg_ps->vb_ptr = msg_ps->invb.head;
+    }
+    else
+    {
+      msg_ps->vb_ptr = msg_ps->vb_ptr->next;
+    }
+    /* skip iso prefix test, was done previously while settesting() */
+    mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4,
+                           msg_ps->vb_ptr->ident + 4, &np);
+    /* check if object is still available
+       (e.g. external hot-plug thingy present?) */
+    if (mn != NULL)
+    {
+      if (mn->node_type == MIB_NODE_EX)
+      {
+        /* external object */
+        struct mib_external_node *en = (struct mib_external_node*)mn;
+
+        msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF_S;
+        /* save en && args in msg_ps!! */
+        msg_ps->ext_mib_node = en;
+        msg_ps->ext_name_ptr = np;
+
+        en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident);
+      }
+      else
+      {
+        /* internal object */
+        struct obj_def object_def;
+
+        msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF_S;
+        mn->get_object_def(np.ident_len, np.ident, &object_def);
+        msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE;
+        mn->set_value(&object_def,msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value);
+        msg_ps->vb_idx += 1;
+      }
+    }
+  }
+  if ((msg_ps->state == SNMP_MSG_INTERNAL_SET_VALUE) &&
+      (msg_ps->vb_idx == msg_ps->invb.count))
+  {
+    /* simply echo the input if we can set it
+       @todo do we need to return the actual value?
+       e.g. if value is silently modified or behaves sticky? */
+    msg_ps->outvb = msg_ps->invb;
+    msg_ps->invb.head = NULL;
+    msg_ps->invb.tail = NULL;
+    msg_ps->invb.count = 0;
+    snmp_ok_response(msg_ps);
+  }
+}
+
+
+/**
+ * Handle one internal or external event.
+ * Called for one async event. (recv external/private answer)
+ *
+ * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1)
+ */
+void
+snmp_msg_event(u8_t request_id)
+{
+  struct snmp_msg_pstat *msg_ps;
+
+  if (request_id < SNMP_CONCURRENT_REQUESTS)
+  {
+    msg_ps = &msg_input_list[request_id];
+    if (msg_ps->rt == SNMP_ASN1_PDU_GET_NEXT_REQ)
+    {
+      snmp_msg_getnext_event(request_id, msg_ps);
+    }
+    else if (msg_ps->rt == SNMP_ASN1_PDU_GET_REQ)
+    {
+      snmp_msg_get_event(request_id, msg_ps);
+    }
+    else if(msg_ps->rt == SNMP_ASN1_PDU_SET_REQ)
+    {
+      snmp_msg_set_event(request_id, msg_ps);
+    }
+  }
+}
+
+
+/* lwIP UDP receive callback function */
+static void
+snmp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port)
+{
+  struct udp_hdr *udphdr;
+
+  /* suppress unused argument warning */
+  LWIP_UNUSED_ARG(arg);
+  /* peek in the UDP header (goto IP payload) */
+  if(pbuf_header(p, UDP_HLEN)){
+    LWIP_ASSERT("Can't move to UDP header", 0);
+    pbuf_free(p);
+    return;
+  }
+  udphdr = p->payload;
+
+  /* check if datagram is really directed at us (including broadcast requests) */
+  if ((pcb == snmp1_pcb) && (ntohs(udphdr->dest) == SNMP_IN_PORT))
+  {
+    struct snmp_msg_pstat *msg_ps;
+    u8_t req_idx;
+
+    /* traverse input message process list, look for SNMP_MSG_EMPTY */
+    msg_ps = &msg_input_list[0];
+    req_idx = 0;
+    while ((req_idxstate != SNMP_MSG_EMPTY))
+    {
+      req_idx++;
+      msg_ps++;
+    }
+    if (req_idx != SNMP_CONCURRENT_REQUESTS)
+    {
+      err_t err_ret;
+      u16_t payload_len;
+      u16_t payload_ofs;
+      u16_t varbind_ofs = 0;
+
+      /* accepting request */
+      snmp_inc_snmpinpkts();
+      /* record used 'protocol control block' */
+      msg_ps->pcb = pcb;
+      /* source address (network order) */
+      msg_ps->sip = *addr;
+      /* source port (host order (lwIP oddity)) */
+      msg_ps->sp = port;
+      /* read UDP payload length from UDP header */
+      payload_len = ntohs(udphdr->len) - UDP_HLEN;
+
+      /* adjust to UDP payload */
+      payload_ofs = UDP_HLEN;
+
+      /* check total length, version, community, pdu type */
+      err_ret = snmp_pdu_header_check(p, payload_ofs, payload_len, &varbind_ofs, msg_ps);
+      if (((msg_ps->rt == SNMP_ASN1_PDU_GET_REQ) ||
+           (msg_ps->rt == SNMP_ASN1_PDU_GET_NEXT_REQ) ||
+           (msg_ps->rt == SNMP_ASN1_PDU_SET_REQ)) &&
+          ((msg_ps->error_status == SNMP_ES_NOERROR) &&
+           (msg_ps->error_index == 0)) )
+      {
+        /* Only accept requests and requests without error (be robust) */
+        err_ret = err_ret;
+      }
+      else
+      {
+        /* Reject response and trap headers or error requests as input! */
+        err_ret = ERR_ARG;
+      }
+      if (err_ret == ERR_OK)
+      {
+        LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv ok, community %s\n", msg_ps->community));
+
+        /* Builds a list of variable bindings. Copy the varbinds from the pbuf
+          chain to glue them when these are divided over two or more pbuf's. */
+        err_ret = snmp_pdu_dec_varbindlist(p, varbind_ofs, &varbind_ofs, msg_ps);
+        if ((err_ret == ERR_OK) && (msg_ps->invb.count > 0))
+        {
+          /* we've decoded the incoming message, release input msg now */
+          pbuf_free(p);
+
+          msg_ps->error_status = SNMP_ES_NOERROR;
+          msg_ps->error_index = 0;
+          /* find object for each variable binding */
+          msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+          /* first variable binding from list to inspect */
+          msg_ps->vb_idx = 0;
+
+          LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv varbind cnt=%"U16_F"\n",(u16_t)msg_ps->invb.count));
+
+          /* handle input event and as much objects as possible in one go */
+          snmp_msg_event(req_idx);
+        }
+        else
+        {
+          /* varbind-list decode failed, or varbind list empty.
+             drop request silently, do not return error!
+             (errors are only returned for a specific varbind failure) */
+          pbuf_free(p);
+          LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_pdu_dec_varbindlist() failed\n"));
+        }
+      }
+      else
+      {
+        /* header check failed
+           drop request silently, do not return error! */
+        pbuf_free(p);
+        LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_pdu_header_check() failed\n"));
+      }
+    }
+    else
+    {
+      /* exceeding number of concurrent requests */
+      pbuf_free(p);
+    }
+  }
+  else
+  {
+    /* datagram not for us */
+    pbuf_free(p);
+  }
+}
+
+/**
+ * Checks and decodes incoming SNMP message header, logs header errors.
+ *
+ * @param p points to pbuf chain of SNMP message (UDP payload)
+ * @param ofs points to first octet of SNMP message
+ * @param pdu_len the length of the UDP payload
+ * @param ofs_ret returns the ofset of the variable bindings
+ * @param m_stat points to the current message request state return
+ * @return
+ * - ERR_OK SNMP header is sane and accepted
+ * - ERR_ARG SNMP header is either malformed or rejected
+ */
+static err_t
+snmp_pdu_header_check(struct pbuf *p, u16_t ofs, u16_t pdu_len, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat)
+{
+  err_t derr;
+  u16_t len, ofs_base;
+  u8_t  len_octets;
+  u8_t  type;
+  s32_t version;
+
+  ofs_base = ofs;
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) ||
+      (pdu_len != (1 + len_octets + len)) ||
+      (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)))
+  {
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets);
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)))
+  {
+    /* can't decode or no integer (version) */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &version);
+  if (derr != ERR_OK)
+  {
+    /* can't decode */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  if (version != 0)
+  {
+    /* not version 1 */
+    snmp_inc_snmpinbadversions();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets + len);
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR)))
+  {
+    /* can't decode or no octet string (community) */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, SNMP_COMMUNITY_STR_LEN, m_stat->community);
+  if (derr != ERR_OK)
+  {
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  /* add zero terminator */
+  len = ((len < (SNMP_COMMUNITY_STR_LEN))?(len):(SNMP_COMMUNITY_STR_LEN));
+  m_stat->community[len] = 0;
+  m_stat->com_strlen = len;
+  if (strncmp(snmp_publiccommunity, (const char*)m_stat->community, SNMP_COMMUNITY_STR_LEN) != 0)
+  {
+    /** @todo: move this if we need to check more names */
+    snmp_inc_snmpinbadcommunitynames();
+    snmp_authfail_trap();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets + len);
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if (derr != ERR_OK)
+  {
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  switch(type)
+  {
+    case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_REQ):
+      /* GetRequest PDU */
+      snmp_inc_snmpingetrequests();
+      derr = ERR_OK;
+      break;
+    case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_NEXT_REQ):
+      /* GetNextRequest PDU */
+      snmp_inc_snmpingetnexts();
+      derr = ERR_OK;
+      break;
+    case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_RESP):
+      /* GetResponse PDU */
+      snmp_inc_snmpingetresponses();
+      derr = ERR_ARG;
+      break;
+    case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_SET_REQ):
+      /* SetRequest PDU */
+      snmp_inc_snmpinsetrequests();
+      derr = ERR_OK;
+      break;
+    case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_TRAP):
+      /* Trap PDU */
+      snmp_inc_snmpintraps();
+      derr = ERR_ARG;
+      break;
+    default:
+      snmp_inc_snmpinasnparseerrs();
+      derr = ERR_ARG;
+      break;
+  }
+  if (derr != ERR_OK)
+  {
+    /* unsupported input PDU for this agent (no parse error) */
+    return ERR_ARG;
+  }
+  m_stat->rt = type & 0x1F;
+  ofs += (1 + len_octets);
+  if (len != (pdu_len - (ofs - ofs_base)))
+  {
+    /* decoded PDU length does not equal actual payload length */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)))
+  {
+    /* can't decode or no integer (request ID) */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->rid);
+  if (derr != ERR_OK)
+  {
+    /* can't decode */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets + len);
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)))
+  {
+    /* can't decode or no integer (error-status) */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  /* must be noError (0) for incoming requests.
+     log errors for mib-2 completeness and for debug purposes */
+  derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->error_status);
+  if (derr != ERR_OK)
+  {
+    /* can't decode */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  switch (m_stat->error_status)
+  {
+    case SNMP_ES_TOOBIG:
+      snmp_inc_snmpintoobigs();
+      break;
+    case SNMP_ES_NOSUCHNAME:
+      snmp_inc_snmpinnosuchnames();
+      break;
+    case SNMP_ES_BADVALUE:
+      snmp_inc_snmpinbadvalues();
+      break;
+    case SNMP_ES_READONLY:
+      snmp_inc_snmpinreadonlys();
+      break;
+    case SNMP_ES_GENERROR:
+      snmp_inc_snmpingenerrs();
+      break;
+  }
+  ofs += (1 + len_octets + len);
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)))
+  {
+    /* can't decode or no integer (error-index) */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  /* must be 0 for incoming requests.
+     decode anyway to catch bad integers (and dirty tricks) */
+  derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->error_index);
+  if (derr != ERR_OK)
+  {
+    /* can't decode */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets + len);
+  *ofs_ret = ofs;
+  return ERR_OK;
+}
+
+static err_t
+snmp_pdu_dec_varbindlist(struct pbuf *p, u16_t ofs, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat)
+{
+  err_t derr;
+  u16_t len, vb_len;
+  u8_t  len_octets;
+  u8_t type;
+
+  /* variable binding list */
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &vb_len);
+  if ((derr != ERR_OK) ||
+      (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)))
+  {
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets);
+
+  /* start with empty list */
+  m_stat->invb.count = 0;
+  m_stat->invb.head = NULL;
+  m_stat->invb.tail = NULL;
+
+  while (vb_len > 0)
+  {
+    struct snmp_obj_id oid, oid_value;
+    struct snmp_varbind *vb;
+
+    snmp_asn1_dec_type(p, ofs, &type);
+    derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+    if ((derr != ERR_OK) ||
+        (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)) ||
+        (len == 0) || (len > vb_len))
+    {
+      snmp_inc_snmpinasnparseerrs();
+      /* free varbinds (if available) */
+      snmp_varbind_list_free(&m_stat->invb);
+      return ERR_ARG;
+    }
+    ofs += (1 + len_octets);
+    vb_len -= (1 + len_octets);
+
+    snmp_asn1_dec_type(p, ofs, &type);
+    derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+    if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID)))
+    {
+      /* can't decode object name length */
+      snmp_inc_snmpinasnparseerrs();
+      /* free varbinds (if available) */
+      snmp_varbind_list_free(&m_stat->invb);
+      return ERR_ARG;
+    }
+    derr = snmp_asn1_dec_oid(p, ofs + 1 + len_octets, len, &oid);
+    if (derr != ERR_OK)
+    {
+      /* can't decode object name */
+      snmp_inc_snmpinasnparseerrs();
+      /* free varbinds (if available) */
+      snmp_varbind_list_free(&m_stat->invb);
+      return ERR_ARG;
+    }
+    ofs += (1 + len_octets + len);
+    vb_len -= (1 + len_octets + len);
+
+    snmp_asn1_dec_type(p, ofs, &type);
+    derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+    if (derr != ERR_OK)
+    {
+      /* can't decode object value length */
+      snmp_inc_snmpinasnparseerrs();
+      /* free varbinds (if available) */
+      snmp_varbind_list_free(&m_stat->invb);
+      return ERR_ARG;
+    }
+
+    switch (type)
+    {
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG):
+        vb = snmp_varbind_alloc(&oid, type, sizeof(s32_t));
+        if (vb != NULL)
+        {
+          s32_t *vptr = vb->value;
+
+          derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, vptr);
+          snmp_varbind_tail_add(&m_stat->invb, vb);
+        }
+        else
+        {
+          derr = ERR_ARG;
+        }
+        break;
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS):
+        vb = snmp_varbind_alloc(&oid, type, sizeof(u32_t));
+        if (vb != NULL)
+        {
+          u32_t *vptr = vb->value;
+
+          derr = snmp_asn1_dec_u32t(p, ofs + 1 + len_octets, len, vptr);
+          snmp_varbind_tail_add(&m_stat->invb, vb);
+        }
+        else
+        {
+          derr = ERR_ARG;
+        }
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE):
+        vb = snmp_varbind_alloc(&oid, type, len);
+        if (vb != NULL)
+        {
+          derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, vb->value_len, vb->value);
+          snmp_varbind_tail_add(&m_stat->invb, vb);
+        }
+        else
+        {
+          derr = ERR_ARG;
+        }
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL):
+        vb = snmp_varbind_alloc(&oid, type, 0);
+        if (vb != NULL)
+        {
+          snmp_varbind_tail_add(&m_stat->invb, vb);
+          derr = ERR_OK;
+        }
+        else
+        {
+          derr = ERR_ARG;
+        }
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID):
+        derr = snmp_asn1_dec_oid(p, ofs + 1 + len_octets, len, &oid_value);
+        if (derr == ERR_OK)
+        {
+          vb = snmp_varbind_alloc(&oid, type, oid_value.len * sizeof(s32_t));
+          if (vb != NULL)
+          {
+            u8_t i = oid_value.len;
+            s32_t *vptr = vb->value;
+
+            while(i > 0)
+            {
+              i--;
+              vptr[i] = oid_value.id[i];
+            }
+            snmp_varbind_tail_add(&m_stat->invb, vb);
+            derr = ERR_OK;
+          }
+          else
+          {
+            derr = ERR_ARG;
+          }
+        }
+        break;
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR):
+        if (len == 4)
+        {
+          /* must be exactly 4 octets! */
+          vb = snmp_varbind_alloc(&oid, type, 4);
+          if (vb != NULL)
+          {
+            derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, vb->value_len, vb->value);
+            snmp_varbind_tail_add(&m_stat->invb, vb);
+          }
+          else
+          {
+            derr = ERR_ARG;
+          }
+        }
+        else
+        {
+          derr = ERR_ARG;
+        }
+        break;
+      default:
+        derr = ERR_ARG;
+        break;
+    }
+    if (derr != ERR_OK)
+    {
+      snmp_inc_snmpinasnparseerrs();
+      /* free varbinds (if available) */
+      snmp_varbind_list_free(&m_stat->invb);
+      return ERR_ARG;
+    }
+    ofs += (1 + len_octets + len);
+    vb_len -= (1 + len_octets + len);
+  }
+
+  if (m_stat->rt == SNMP_ASN1_PDU_SET_REQ)
+  {
+    snmp_add_snmpintotalsetvars(m_stat->invb.count);
+  }
+  else
+  {
+    snmp_add_snmpintotalreqvars(m_stat->invb.count);
+  }
+
+  *ofs_ret = ofs;
+  return ERR_OK;
+}
+
+struct snmp_varbind*
+snmp_varbind_alloc(struct snmp_obj_id *oid, u8_t type, u8_t len)
+{
+  struct snmp_varbind *vb;
+
+  vb = (struct snmp_varbind *)mem_malloc(sizeof(struct snmp_varbind));
+  LWIP_ASSERT("vb != NULL",vb != NULL);
+  if (vb != NULL)
+  {
+    u8_t i;
+
+    vb->next = NULL;
+    vb->prev = NULL;
+    i = oid->len;
+    vb->ident_len = i;
+    if (i > 0)
+    {
+      /* allocate array of s32_t for our object identifier */
+      vb->ident = (s32_t*)mem_malloc(sizeof(s32_t) * i);
+      LWIP_ASSERT("vb->ident != NULL",vb->ident != NULL);
+      if (vb->ident == NULL)
+      {
+        mem_free(vb);
+        return NULL;
+      }
+      while(i > 0)
+      {
+        i--;
+        vb->ident[i] = oid->id[i];
+      }
+    }
+    else
+    {
+      /* i == 0, pass zero length object identifier */
+      vb->ident = NULL;
+    }
+    vb->value_type = type;
+    vb->value_len = len;
+    if (len > 0)
+    {
+      /* allocate raw bytes for our object value */
+      vb->value = mem_malloc(len);
+      LWIP_ASSERT("vb->value != NULL",vb->value != NULL);
+      if (vb->value == NULL)
+      {
+        if (vb->ident != NULL)
+        {
+          mem_free(vb->ident);
+        }
+        mem_free(vb);
+        return NULL;
+      }
+    }
+    else
+    {
+      /* ASN1_NUL type, or zero length ASN1_OC_STR */
+      vb->value = NULL;
+    }
+  }
+  return vb;
+}
+
+void
+snmp_varbind_free(struct snmp_varbind *vb)
+{
+  if (vb->value != NULL )
+  {
+    mem_free(vb->value);
+  }
+  if (vb->ident != NULL )
+  {
+    mem_free(vb->ident);
+  }
+  mem_free(vb);
+}
+
+void
+snmp_varbind_list_free(struct snmp_varbind_root *root)
+{
+  struct snmp_varbind *vb, *prev;
+
+  vb = root->tail;
+  while ( vb != NULL )
+  {
+    prev = vb->prev;
+    snmp_varbind_free(vb);
+    vb = prev;
+  }
+  root->count = 0;
+  root->head = NULL;
+  root->tail = NULL;
+}
+
+void
+snmp_varbind_tail_add(struct snmp_varbind_root *root, struct snmp_varbind *vb)
+{
+  if (root->count == 0)
+  {
+    /* add first varbind to list */
+    root->head = vb;
+    root->tail = vb;
+  }
+  else
+  {
+    /* add nth varbind to list tail */
+    root->tail->next = vb;
+    vb->prev = root->tail;
+    root->tail = vb;
+  }
+  root->count += 1;
+}
+
+struct snmp_varbind*
+snmp_varbind_tail_remove(struct snmp_varbind_root *root)
+{
+  struct snmp_varbind* vb;
+
+  if (root->count > 0)
+  {
+    /* remove tail varbind */
+    vb = root->tail;
+    root->tail = vb->prev;
+    vb->prev->next = NULL;
+    root->count -= 1;
+  }
+  else
+  {
+    /* nothing to remove */
+    vb = NULL;
+  }
+  return vb;
+}
+
+#endif /* LWIP_SNMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/snmp/msg_out.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/snmp/msg_out.c
new file mode 100644
index 0000000..b705aac
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/snmp/msg_out.c
@@ -0,0 +1,683 @@
+/**
+ * @file
+ * SNMP output message processing (RFC1157).
+ *
+ * Output responses and traps are build in two passes:
+ *
+ * Pass 0: iterate over the output message backwards to determine encoding lengths
+ * Pass 1: the actual forward encoding of internal form into ASN1
+ *
+ * The single-pass encoding method described by Comer & Stevens
+ * requires extra buffer space and copying for reversal of the packet.
+ * The buffer requirement can be prohibitively large for big payloads
+ * (>= 484) therefore we use the two encoding passes.
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/udp.h"
+#include "lwip/netif.h"
+#include "lwip/snmp.h"
+#include "lwip/snmp_asn1.h"
+#include "lwip/snmp_msg.h"
+
+struct snmp_trap_dst
+{
+  /* destination IP address in network order */
+  struct ip_addr dip;
+  /* set to 0 when disabled, >0 when enabled */
+  u8_t enable;
+};
+struct snmp_trap_dst trap_dst[SNMP_TRAP_DESTINATIONS];
+
+/** TRAP message structure */
+struct snmp_msg_trap trap_msg;
+
+static u16_t snmp_resp_header_sum(struct snmp_msg_pstat *m_stat, u16_t vb_len);
+static u16_t snmp_trap_header_sum(struct snmp_msg_trap *m_trap, u16_t vb_len);
+static u16_t snmp_varbind_list_sum(struct snmp_varbind_root *root);
+
+static u16_t snmp_resp_header_enc(struct snmp_msg_pstat *m_stat, struct pbuf *p);
+static u16_t snmp_trap_header_enc(struct snmp_msg_trap *m_trap, struct pbuf *p);
+static u16_t snmp_varbind_list_enc(struct snmp_varbind_root *root, struct pbuf *p, u16_t ofs);
+
+/**
+ * Sets enable switch for this trap destination.
+ * @param dst_idx index in 0 .. SNMP_TRAP_DESTINATIONS-1
+ * @param enable switch if 0 destination is disabled >0 enabled.
+ */
+void
+snmp_trap_dst_enable(u8_t dst_idx, u8_t enable)
+{
+  if (dst_idx < SNMP_TRAP_DESTINATIONS)
+  {
+    trap_dst[dst_idx].enable = enable;
+  }
+}
+
+/**
+ * Sets IPv4 address for this trap destination.
+ * @param dst_idx index in 0 .. SNMP_TRAP_DESTINATIONS-1
+ * @param dst IPv4 address in host order.
+ */
+void
+snmp_trap_dst_ip_set(u8_t dst_idx, struct ip_addr *dst)
+{
+  if (dst_idx < SNMP_TRAP_DESTINATIONS)
+  {
+    trap_dst[dst_idx].dip.addr = htonl(dst->addr);
+  }
+}
+
+/**
+ * Sends a 'getresponse' message to the request originator.
+ *
+ * @param m_stat points to the current message request state source
+ * @return ERR_OK when success, ERR_MEM if we're out of memory
+ *
+ * @note the caller is responsible for filling in outvb in the m_stat
+ * and provide error-status and index (except for tooBig errors) ...
+ */
+err_t
+snmp_send_response(struct snmp_msg_pstat *m_stat)
+{
+  struct snmp_varbind_root emptyvb = {NULL, NULL, 0, 0, 0};
+  struct pbuf *p;
+  u16_t tot_len;
+  err_t err;
+
+  /* pass 0, calculate length fields */
+  tot_len = snmp_varbind_list_sum(&m_stat->outvb);
+  tot_len = snmp_resp_header_sum(m_stat, tot_len);
+
+  /* try allocating pbuf(s) for complete response */
+  p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL);
+  if (p == NULL)
+  {
+    LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() tooBig\n"));
+
+    /* can't construct reply, return error-status tooBig */
+    m_stat->error_status = SNMP_ES_TOOBIG;
+    m_stat->error_index = 0;
+    /* pass 0, recalculate lengths, for empty varbind-list */
+    tot_len = snmp_varbind_list_sum(&emptyvb);
+    tot_len = snmp_resp_header_sum(m_stat, tot_len);
+    /* retry allocation once for header and empty varbind-list */
+    p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL);
+  }
+  if (p != NULL)
+  {
+    /* first pbuf alloc try or retry alloc success */
+    u16_t ofs;
+
+    LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() p != NULL\n"));
+
+    /* pass 1, size error, encode packet ino the pbuf(s) */
+    ofs = snmp_resp_header_enc(m_stat, p);
+    if (m_stat->error_status == SNMP_ES_TOOBIG)
+    {
+      snmp_varbind_list_enc(&emptyvb, p, ofs);
+    }
+    else
+    {
+      snmp_varbind_list_enc(&m_stat->outvb, p, ofs);
+    }
+
+    switch (m_stat->error_status)
+    {
+      case SNMP_ES_TOOBIG:
+        snmp_inc_snmpouttoobigs();
+        break;
+      case SNMP_ES_NOSUCHNAME:
+        snmp_inc_snmpoutnosuchnames();
+        break;
+      case SNMP_ES_BADVALUE:
+        snmp_inc_snmpoutbadvalues();
+        break;
+      case SNMP_ES_GENERROR:
+        snmp_inc_snmpoutgenerrs();
+        break;
+    }
+    snmp_inc_snmpoutgetresponses();
+    snmp_inc_snmpoutpkts();
+
+    /** @todo do we need separate rx and tx pcbs for threaded case? */
+    /** connect to the originating source */
+    udp_connect(m_stat->pcb, &m_stat->sip, m_stat->sp);
+    err = udp_send(m_stat->pcb, p);
+    if (err == ERR_MEM)
+    {
+      /** @todo release some memory, retry and return tooBig? tooMuchHassle? */
+      err = ERR_MEM;
+    }
+    else
+    {
+      err = ERR_OK;
+    }
+    /** disassociate remote address and port with this pcb */
+    udp_disconnect(m_stat->pcb);
+
+    pbuf_free(p);
+    LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() done\n"));
+    return err;
+  }
+  else
+  {
+    /* first pbuf alloc try or retry alloc failed
+       very low on memory, couldn't return tooBig */
+    return ERR_MEM;
+  }
+}
+
+
+/**
+ * Sends an generic or enterprise specific trap message.
+ *
+ * @param generic_trap is the trap code
+ * @param eoid points to enterprise object identifier
+ * @param specific_trap used for enterprise traps when generic_trap == 6
+ * @return ERR_OK when success, ERR_MEM if we're out of memory
+ *
+ * @note the caller is responsible for filling in outvb in the trap_msg
+ * @note the use of the enterpise identifier field
+ * is per RFC1215.
+ * Use .iso.org.dod.internet.mgmt.mib-2.snmp for generic traps
+ * and .iso.org.dod.internet.private.enterprises.yourenterprise
+ * (sysObjectID) for specific traps.
+ */
+err_t
+snmp_send_trap(s8_t generic_trap, struct snmp_obj_id *eoid, s32_t specific_trap)
+{
+  struct snmp_trap_dst *td;
+  struct netif *dst_if;
+  struct ip_addr dst_ip;
+  struct pbuf *p;
+  u16_t i,tot_len;
+
+  for (i=0, td = &trap_dst[0]; ienable != 0) && (td->dip.addr != 0))
+    {
+      /* network order trap destination */
+      trap_msg.dip.addr = td->dip.addr;
+      /* lookup current source address for this dst */
+      dst_if = ip_route(&td->dip);
+      dst_ip.addr = ntohl(dst_if->ip_addr.addr);
+      trap_msg.sip_raw[0] = dst_ip.addr >> 24;
+      trap_msg.sip_raw[1] = dst_ip.addr >> 16;
+      trap_msg.sip_raw[2] = dst_ip.addr >> 8;
+      trap_msg.sip_raw[3] = dst_ip.addr;
+      trap_msg.gen_trap = generic_trap;
+      trap_msg.spc_trap = specific_trap;
+      if (generic_trap == SNMP_GENTRAP_ENTERPRISESPC)
+      {
+        /* enterprise-Specific trap */
+        trap_msg.enterprise = eoid;
+      }
+      else
+      {
+        /* generic (MIB-II) trap */
+        snmp_get_snmpgrpid_ptr(&trap_msg.enterprise);
+      }
+      snmp_get_sysuptime(&trap_msg.ts);
+
+      /* pass 0, calculate length fields */
+      tot_len = snmp_varbind_list_sum(&trap_msg.outvb);
+      tot_len = snmp_trap_header_sum(&trap_msg, tot_len);
+
+      /* allocate pbuf(s) */
+      p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL);
+      if (p != NULL)
+      {
+        u16_t ofs;
+
+        /* pass 1, encode packet ino the pbuf(s) */
+        ofs = snmp_trap_header_enc(&trap_msg, p);
+        snmp_varbind_list_enc(&trap_msg.outvb, p, ofs);
+
+        snmp_inc_snmpouttraps();
+        snmp_inc_snmpoutpkts();
+
+        /** connect to the TRAP destination */
+        udp_connect(trap_msg.pcb, &trap_msg.dip, SNMP_TRAP_PORT);
+        udp_send(trap_msg.pcb, p);
+        /** disassociate remote address and port with this pcb */
+        udp_disconnect(trap_msg.pcb);
+
+        pbuf_free(p);
+      }
+      else
+      {
+        return ERR_MEM;
+      }
+    }
+  }
+  return ERR_OK;
+}
+
+void
+snmp_coldstart_trap(void)
+{
+  trap_msg.outvb.head = NULL;
+  trap_msg.outvb.tail = NULL;
+  trap_msg.outvb.count = 0;
+  snmp_send_trap(SNMP_GENTRAP_COLDSTART, NULL, 0);
+}
+
+void
+snmp_authfail_trap(void)
+{
+  u8_t enable;
+  snmp_get_snmpenableauthentraps(&enable);
+  if (enable == 1)
+  {
+    trap_msg.outvb.head = NULL;
+    trap_msg.outvb.tail = NULL;
+    trap_msg.outvb.count = 0;
+    snmp_send_trap(SNMP_GENTRAP_AUTHFAIL, NULL, 0);
+  }
+}
+
+/**
+ * Sums response header field lengths from tail to head and
+ * returns resp_header_lengths for second encoding pass.
+ *
+ * @param vb_len varbind-list length
+ * @param rhl points to returned header lengths
+ * @return the required lenght for encoding the response header
+ */
+static u16_t
+snmp_resp_header_sum(struct snmp_msg_pstat *m_stat, u16_t vb_len)
+{
+  u16_t tot_len;
+  struct snmp_resp_header_lengths *rhl;
+
+  rhl = &m_stat->rhl;
+  tot_len = vb_len;
+  snmp_asn1_enc_s32t_cnt(m_stat->error_index, &rhl->erridxlen);
+  snmp_asn1_enc_length_cnt(rhl->erridxlen, &rhl->erridxlenlen);
+  tot_len += 1 + rhl->erridxlenlen + rhl->erridxlen;
+
+  snmp_asn1_enc_s32t_cnt(m_stat->error_status, &rhl->errstatlen);
+  snmp_asn1_enc_length_cnt(rhl->errstatlen, &rhl->errstatlenlen);
+  tot_len += 1 + rhl->errstatlenlen + rhl->errstatlen;
+
+  snmp_asn1_enc_s32t_cnt(m_stat->rid, &rhl->ridlen);
+  snmp_asn1_enc_length_cnt(rhl->ridlen, &rhl->ridlenlen);
+  tot_len += 1 + rhl->ridlenlen + rhl->ridlen;
+
+  rhl->pdulen = tot_len;
+  snmp_asn1_enc_length_cnt(rhl->pdulen, &rhl->pdulenlen);
+  tot_len += 1 + rhl->pdulenlen;
+
+  rhl->comlen = m_stat->com_strlen;
+  snmp_asn1_enc_length_cnt(rhl->comlen, &rhl->comlenlen);
+  tot_len += 1 + rhl->comlenlen + rhl->comlen;
+
+  snmp_asn1_enc_s32t_cnt(snmp_version, &rhl->verlen);
+  snmp_asn1_enc_length_cnt(rhl->verlen, &rhl->verlenlen);
+  tot_len += 1 + rhl->verlen + rhl->verlenlen;
+
+  rhl->seqlen = tot_len;
+  snmp_asn1_enc_length_cnt(rhl->seqlen, &rhl->seqlenlen);
+  tot_len += 1 + rhl->seqlenlen;
+
+  return tot_len;
+}
+
+/**
+ * Sums trap header field lengths from tail to head and
+ * returns trap_header_lengths for second encoding pass.
+ *
+ * @param vb_len varbind-list length
+ * @param thl points to returned header lengths
+ * @return the required lenght for encoding the trap header
+ */
+static u16_t
+snmp_trap_header_sum(struct snmp_msg_trap *m_trap, u16_t vb_len)
+{
+  u16_t tot_len;
+  struct snmp_trap_header_lengths *thl;
+
+  thl = &m_trap->thl;
+  tot_len = vb_len;
+
+  snmp_asn1_enc_u32t_cnt(m_trap->ts, &thl->tslen);
+  snmp_asn1_enc_length_cnt(thl->tslen, &thl->tslenlen);
+  tot_len += 1 + thl->tslen + thl->tslenlen;
+
+  snmp_asn1_enc_s32t_cnt(m_trap->spc_trap, &thl->strplen);
+  snmp_asn1_enc_length_cnt(thl->strplen, &thl->strplenlen);
+  tot_len += 1 + thl->strplen + thl->strplenlen;
+
+  snmp_asn1_enc_s32t_cnt(m_trap->gen_trap, &thl->gtrplen);
+  snmp_asn1_enc_length_cnt(thl->gtrplen, &thl->gtrplenlen);
+  tot_len += 1 + thl->gtrplen + thl->gtrplenlen;
+
+  thl->aaddrlen = 4;
+  snmp_asn1_enc_length_cnt(thl->aaddrlen, &thl->aaddrlenlen);
+  tot_len += 1 + thl->aaddrlen + thl->aaddrlenlen;
+
+  snmp_asn1_enc_oid_cnt(m_trap->enterprise->len, &m_trap->enterprise->id[0], &thl->eidlen);
+  snmp_asn1_enc_length_cnt(thl->eidlen, &thl->eidlenlen);
+  tot_len += 1 + thl->eidlen + thl->eidlenlen;
+
+  thl->pdulen = tot_len;
+  snmp_asn1_enc_length_cnt(thl->pdulen, &thl->pdulenlen);
+  tot_len += 1 + thl->pdulenlen;
+
+  thl->comlen = sizeof(snmp_publiccommunity) - 1;
+  snmp_asn1_enc_length_cnt(thl->comlen, &thl->comlenlen);
+  tot_len += 1 + thl->comlenlen + thl->comlen;
+
+  snmp_asn1_enc_s32t_cnt(snmp_version, &thl->verlen);
+  snmp_asn1_enc_length_cnt(thl->verlen, &thl->verlenlen);
+  tot_len += 1 + thl->verlen + thl->verlenlen;
+
+  thl->seqlen = tot_len;
+  snmp_asn1_enc_length_cnt(thl->seqlen, &thl->seqlenlen);
+  tot_len += 1 + thl->seqlenlen;
+
+  return tot_len;
+}
+
+/**
+ * Sums varbind lengths from tail to head and
+ * annotates lengths in varbind for second encoding pass.
+ *
+ * @param root points to the root of the variable binding list
+ * @return the required lenght for encoding the variable bindings
+ */
+static u16_t
+snmp_varbind_list_sum(struct snmp_varbind_root *root)
+{
+  struct snmp_varbind *vb;
+  u32_t *uint_ptr;
+  s32_t *sint_ptr;
+  u16_t tot_len;
+
+  tot_len = 0;
+  vb = root->tail;
+  while ( vb != NULL )
+  {
+    /* encoded value lenght depends on type */
+    switch (vb->value_type)
+    {
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG):
+        sint_ptr = vb->value;
+        snmp_asn1_enc_s32t_cnt(*sint_ptr, &vb->vlen);
+        break;
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS):
+        uint_ptr = vb->value;
+        snmp_asn1_enc_u32t_cnt(*uint_ptr, &vb->vlen);
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR):
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE):
+        vb->vlen = vb->value_len;
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID):
+        sint_ptr = vb->value;
+        snmp_asn1_enc_oid_cnt(vb->value_len / sizeof(s32_t), sint_ptr, &vb->vlen);
+        break;
+      default:
+        /* unsupported type */
+        vb->vlen = 0;
+        break;
+    };
+    /* encoding length of value length field */
+    snmp_asn1_enc_length_cnt(vb->vlen, &vb->vlenlen);
+    snmp_asn1_enc_oid_cnt(vb->ident_len, vb->ident, &vb->olen);
+    snmp_asn1_enc_length_cnt(vb->olen, &vb->olenlen);
+
+    vb->seqlen = 1 + vb->vlenlen + vb->vlen;
+    vb->seqlen += 1 + vb->olenlen + vb->olen;
+    snmp_asn1_enc_length_cnt(vb->seqlen, &vb->seqlenlen);
+
+    /* varbind seq */
+    tot_len += 1 + vb->seqlenlen + vb->seqlen;
+
+    vb = vb->prev;
+  }
+
+  /* varbind-list seq */
+  root->seqlen = tot_len;
+  snmp_asn1_enc_length_cnt(root->seqlen, &root->seqlenlen);
+  tot_len += 1 + root->seqlenlen;
+
+  return tot_len;
+}
+
+/**
+ * Encodes response header from head to tail.
+ */
+static u16_t
+snmp_resp_header_enc(struct snmp_msg_pstat *m_stat, struct pbuf *p)
+{
+  u16_t ofs;
+
+  ofs = 0;
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.seqlen);
+  ofs += m_stat->rhl.seqlenlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.verlen);
+  ofs += m_stat->rhl.verlenlen;
+  snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.verlen, snmp_version);
+  ofs += m_stat->rhl.verlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.comlen);
+  ofs += m_stat->rhl.comlenlen;
+  snmp_asn1_enc_raw(p, ofs, m_stat->rhl.comlen, m_stat->community);
+  ofs += m_stat->rhl.comlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_RESP));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.pdulen);
+  ofs += m_stat->rhl.pdulenlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.ridlen);
+  ofs += m_stat->rhl.ridlenlen;
+  snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.ridlen, m_stat->rid);
+  ofs += m_stat->rhl.ridlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.errstatlen);
+  ofs += m_stat->rhl.errstatlenlen;
+  snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.errstatlen, m_stat->error_status);
+  ofs += m_stat->rhl.errstatlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.erridxlen);
+  ofs += m_stat->rhl.erridxlenlen;
+  snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.erridxlen, m_stat->error_index);
+  ofs += m_stat->rhl.erridxlen;
+
+  return ofs;
+}
+
+/**
+ * Encodes trap header from head to tail.
+ */
+static u16_t
+snmp_trap_header_enc(struct snmp_msg_trap *m_trap, struct pbuf *p)
+{
+  u16_t ofs;
+
+  ofs = 0;
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.seqlen);
+  ofs += m_trap->thl.seqlenlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.verlen);
+  ofs += m_trap->thl.verlenlen;
+  snmp_asn1_enc_s32t(p, ofs, m_trap->thl.verlen, snmp_version);
+  ofs += m_trap->thl.verlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.comlen);
+  ofs += m_trap->thl.comlenlen;
+  snmp_asn1_enc_raw(p, ofs, m_trap->thl.comlen, (u8_t *)&snmp_publiccommunity[0]);
+  ofs += m_trap->thl.comlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_TRAP));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.pdulen);
+  ofs += m_trap->thl.pdulenlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.eidlen);
+  ofs += m_trap->thl.eidlenlen;
+  snmp_asn1_enc_oid(p, ofs, m_trap->enterprise->len, &m_trap->enterprise->id[0]);
+  ofs += m_trap->thl.eidlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.aaddrlen);
+  ofs += m_trap->thl.aaddrlenlen;
+  snmp_asn1_enc_raw(p, ofs, m_trap->thl.aaddrlen, &m_trap->sip_raw[0]);
+  ofs += m_trap->thl.aaddrlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.gtrplen);
+  ofs += m_trap->thl.gtrplenlen;
+  snmp_asn1_enc_u32t(p, ofs, m_trap->thl.gtrplen, m_trap->gen_trap);
+  ofs += m_trap->thl.gtrplen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.strplen);
+  ofs += m_trap->thl.strplenlen;
+  snmp_asn1_enc_u32t(p, ofs, m_trap->thl.strplen, m_trap->spc_trap);
+  ofs += m_trap->thl.strplen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.tslen);
+  ofs += m_trap->thl.tslenlen;
+  snmp_asn1_enc_u32t(p, ofs, m_trap->thl.tslen, m_trap->ts);
+  ofs += m_trap->thl.tslen;
+
+  return ofs;
+}
+
+/**
+ * Encodes varbind list from head to tail.
+ */
+static u16_t
+snmp_varbind_list_enc(struct snmp_varbind_root *root, struct pbuf *p, u16_t ofs)
+{
+  struct snmp_varbind *vb;
+  s32_t *sint_ptr;
+  u32_t *uint_ptr;
+  u8_t *raw_ptr;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, root->seqlen);
+  ofs += root->seqlenlen;
+
+  vb = root->head;
+  while ( vb != NULL )
+  {
+    snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ));
+    ofs += 1;
+    snmp_asn1_enc_length(p, ofs, vb->seqlen);
+    ofs += vb->seqlenlen;
+
+    snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID));
+    ofs += 1;
+    snmp_asn1_enc_length(p, ofs, vb->olen);
+    ofs += vb->olenlen;
+    snmp_asn1_enc_oid(p, ofs, vb->ident_len, &vb->ident[0]);
+    ofs += vb->olen;
+
+    snmp_asn1_enc_type(p, ofs, vb->value_type);
+    ofs += 1;
+    snmp_asn1_enc_length(p, ofs, vb->vlen);
+    ofs += vb->vlenlen;
+
+    switch (vb->value_type)
+    {
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG):
+        sint_ptr = vb->value;
+        snmp_asn1_enc_s32t(p, ofs, vb->vlen, *sint_ptr);
+        break;
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS):
+        uint_ptr = vb->value;
+        snmp_asn1_enc_u32t(p, ofs, vb->vlen, *uint_ptr);
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE):
+        raw_ptr = vb->value;
+        snmp_asn1_enc_raw(p, ofs, vb->vlen, raw_ptr);
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL):
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID):
+        sint_ptr = vb->value;
+        snmp_asn1_enc_oid(p, ofs, vb->value_len / sizeof(s32_t), sint_ptr);
+        break;
+      default:
+        /* unsupported type */
+        break;
+    };
+    ofs += vb->vlen;
+    vb = vb->next;
+  }
+  return ofs;
+}
+
+#endif /* LWIP_SNMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/stats.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/stats.c
new file mode 100644
index 0000000..a036d83
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/stats.c
@@ -0,0 +1,149 @@
+/**
+ * @file
+ * Statistics module
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_STATS /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/def.h"
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+
+#include 
+
+struct stats_ lwip_stats;
+
+#if LWIP_STATS_DISPLAY
+void
+stats_display_proto(struct stats_proto *proto, char *name)
+{
+  LWIP_PLATFORM_DIAG(("\n%s\n\t", name));
+  LWIP_PLATFORM_DIAG(("xmit: %"STAT_COUNTER_F"\n\t", proto->xmit)); 
+  LWIP_PLATFORM_DIAG(("recv: %"STAT_COUNTER_F"\n\t", proto->recv)); 
+  LWIP_PLATFORM_DIAG(("fw: %"STAT_COUNTER_F"\n\t", proto->fw)); 
+  LWIP_PLATFORM_DIAG(("drop: %"STAT_COUNTER_F"\n\t", proto->drop)); 
+  LWIP_PLATFORM_DIAG(("chkerr: %"STAT_COUNTER_F"\n\t", proto->chkerr)); 
+  LWIP_PLATFORM_DIAG(("lenerr: %"STAT_COUNTER_F"\n\t", proto->lenerr)); 
+  LWIP_PLATFORM_DIAG(("memerr: %"STAT_COUNTER_F"\n\t", proto->memerr)); 
+  LWIP_PLATFORM_DIAG(("rterr: %"STAT_COUNTER_F"\n\t", proto->rterr)); 
+  LWIP_PLATFORM_DIAG(("proterr: %"STAT_COUNTER_F"\n\t", proto->proterr)); 
+  LWIP_PLATFORM_DIAG(("opterr: %"STAT_COUNTER_F"\n\t", proto->opterr)); 
+  LWIP_PLATFORM_DIAG(("err: %"STAT_COUNTER_F"\n\t", proto->err)); 
+  LWIP_PLATFORM_DIAG(("cachehit: %"STAT_COUNTER_F"\n", proto->cachehit)); 
+}
+
+#if IGMP_STATS
+void
+stats_display_igmp(struct stats_igmp *igmp)
+{
+  LWIP_PLATFORM_DIAG(("\nIGMP\n\t"));
+  LWIP_PLATFORM_DIAG(("lenerr: %"STAT_COUNTER_F"\n\t", igmp->lenerr)); 
+  LWIP_PLATFORM_DIAG(("chkerr: %"STAT_COUNTER_F"\n\t", igmp->chkerr)); 
+  LWIP_PLATFORM_DIAG(("v1_rxed: %"STAT_COUNTER_F"\n\t", igmp->v1_rxed)); 
+  LWIP_PLATFORM_DIAG(("join_sent: %"STAT_COUNTER_F"\n\t", igmp->join_sent)); 
+  LWIP_PLATFORM_DIAG(("leave_sent: %"STAT_COUNTER_F"\n\t", igmp->leave_sent)); 
+  LWIP_PLATFORM_DIAG(("unicast_query: %"STAT_COUNTER_F"\n\t", igmp->unicast_query)); 
+  LWIP_PLATFORM_DIAG(("report_sent: %"STAT_COUNTER_F"\n\t", igmp->report_sent)); 
+  LWIP_PLATFORM_DIAG(("report_rxed: %"STAT_COUNTER_F"\n\t", igmp->report_rxed)); 
+  LWIP_PLATFORM_DIAG(("group_query_rxed: %"STAT_COUNTER_F"\n", igmp->group_query_rxed));
+}
+#endif /* IGMP_STATS */
+
+#if MEM_STATS || MEMP_STATS
+void
+stats_display_mem(struct stats_mem *mem, char *name)
+{
+  LWIP_PLATFORM_DIAG(("\nMEM %s\n\t", name));
+  LWIP_PLATFORM_DIAG(("avail: %"U32_F"\n\t", (u32_t)mem->avail)); 
+  LWIP_PLATFORM_DIAG(("used: %"U32_F"\n\t", (u32_t)mem->used)); 
+  LWIP_PLATFORM_DIAG(("max: %"U32_F"\n\t", (u32_t)mem->max)); 
+  LWIP_PLATFORM_DIAG(("err: %"U32_F"\n", (u32_t)mem->err));
+}
+
+#if MEMP_STATS
+void
+stats_display_memp(struct stats_mem *mem, int index)
+{
+  char * memp_names[] = {
+#define LWIP_MEMPOOL(name,num,size,desc) desc,
+#include "lwip/memp_std.h"
+  };
+  if(index < MEMP_MAX) {
+    stats_display_mem(mem, memp_names[index]);
+  }
+}
+#endif /* MEMP_STATS */
+#endif /* MEM_STATS || MEMP_STATS */
+
+#if SYS_STATS
+void
+stats_display_sys(struct stats_sys *sys)
+{
+  LWIP_PLATFORM_DIAG(("\nSYS\n\t"));
+  LWIP_PLATFORM_DIAG(("sem.used: %"U32_F"\n\t", (u32_t)sys->sem.used)); 
+  LWIP_PLATFORM_DIAG(("sem.max:  %"U32_F"\n\t", (u32_t)sys->sem.max)); 
+  LWIP_PLATFORM_DIAG(("sem.err:  %"U32_F"\n\t", (u32_t)sys->sem.err)); 
+  LWIP_PLATFORM_DIAG(("mbox.used: %"U32_F"\n\t", (u32_t)sys->mbox.used)); 
+  LWIP_PLATFORM_DIAG(("mbox.max:  %"U32_F"\n\t", (u32_t)sys->mbox.max)); 
+  LWIP_PLATFORM_DIAG(("mbox.err:  %"U32_F"\n\t", (u32_t)sys->mbox.err)); 
+}
+#endif /* SYS_STATS */
+
+void
+stats_display(void)
+{
+  s16_t i;
+
+  LINK_STATS_DISPLAY();
+  ETHARP_STATS_DISPLAY();
+  IPFRAG_STATS_DISPLAY();
+  IP_STATS_DISPLAY();
+  IGMP_STATS_DISPLAY();
+  ICMP_STATS_DISPLAY();
+  UDP_STATS_DISPLAY();
+  TCP_STATS_DISPLAY();
+  MEM_STATS_DISPLAY();
+  for (i = 0; i < MEMP_MAX; i++) {
+    MEMP_STATS_DISPLAY(i);
+  }
+  SYS_STATS_DISPLAY();
+}
+#endif /* LWIP_STATS_DISPLAY */
+
+#endif /* LWIP_STATS */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/sys.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/sys.c
new file mode 100644
index 0000000..cb5e86a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/sys.c
@@ -0,0 +1,346 @@
+/**
+ * @file
+ * lwIP Operating System abstraction
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if (NO_SYS == 0) /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/sys.h"
+#include "lwip/def.h"
+#include "lwip/memp.h"
+#include "lwip/tcpip.h"
+
+/**
+ * Struct used for sys_sem_wait_timeout() to tell wether the time
+ * has run out or the semaphore has really become available.
+ */
+struct sswt_cb
+{
+  s16_t timeflag;
+  sys_sem_t *psem;
+};
+
+/**
+ * Wait (forever) for a message to arrive in an mbox.
+ * While waiting, timeouts (for this thread) are processed.
+ *
+ * @param mbox the mbox to fetch the message from
+ * @param msg the place to store the message
+ */
+void
+sys_mbox_fetch(sys_mbox_t mbox, void **msg)
+{
+  u32_t time_needed;
+  struct sys_timeouts *timeouts;
+  struct sys_timeo *tmptimeout;
+  sys_timeout_handler h;
+  void *arg;
+
+ again:
+  timeouts = sys_arch_timeouts();
+
+  if (!timeouts || !timeouts->next) {
+    UNLOCK_TCPIP_CORE();
+    time_needed = sys_arch_mbox_fetch(mbox, msg, 0);
+    LOCK_TCPIP_CORE();
+  } else {
+    if (timeouts->next->time > 0) {
+      UNLOCK_TCPIP_CORE();
+      time_needed = sys_arch_mbox_fetch(mbox, msg, timeouts->next->time);
+      LOCK_TCPIP_CORE();
+    } else {
+      time_needed = SYS_ARCH_TIMEOUT;
+    }
+
+    if (time_needed == SYS_ARCH_TIMEOUT) {
+      /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message
+         could be fetched. We should now call the timeout handler and
+         deallocate the memory allocated for the timeout. */
+      tmptimeout = timeouts->next;
+      timeouts->next = tmptimeout->next;
+      h   = tmptimeout->h;
+      arg = tmptimeout->arg;
+      memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
+      if (h != NULL) {
+        LWIP_DEBUGF(SYS_DEBUG, ("smf calling h=%p(%p)\n", *(void**)&h, arg));
+        h(arg);
+      }
+
+      /* We try again to fetch a message from the mbox. */
+      goto again;
+    } else {
+      /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout
+         occured. The time variable is set to the number of
+         milliseconds we waited for the message. */
+      if (time_needed < timeouts->next->time) {
+        timeouts->next->time -= time_needed;
+      } else {
+        timeouts->next->time = 0;
+      }
+    }
+  }
+}
+
+/**
+ * Wait (forever) for a semaphore to become available.
+ * While waiting, timeouts (for this thread) are processed.
+ *
+ * @param sem semaphore to wait for
+ */
+void
+sys_sem_wait(sys_sem_t sem)
+{
+  u32_t time_needed;
+  struct sys_timeouts *timeouts;
+  struct sys_timeo *tmptimeout;
+  sys_timeout_handler h;
+  void *arg;
+
+ again:
+
+  timeouts = sys_arch_timeouts();
+
+  if (!timeouts || !timeouts->next) {
+    sys_arch_sem_wait(sem, 0);
+  } else {
+    if (timeouts->next->time > 0) {
+      time_needed = sys_arch_sem_wait(sem, timeouts->next->time);
+    } else {
+      time_needed = SYS_ARCH_TIMEOUT;
+    }
+
+    if (time_needed == SYS_ARCH_TIMEOUT) {
+      /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message
+        could be fetched. We should now call the timeout handler and
+        deallocate the memory allocated for the timeout. */
+      tmptimeout = timeouts->next;
+      timeouts->next = tmptimeout->next;
+      h = tmptimeout->h;
+      arg = tmptimeout->arg;
+      memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
+      if (h != NULL) {
+        LWIP_DEBUGF(SYS_DEBUG, ("ssw h=%p(%p)\n", *(void**)&h, (void *)arg));
+        h(arg);
+      }
+
+      /* We try again to fetch a message from the mbox. */
+      goto again;
+    } else {
+      /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout
+         occured. The time variable is set to the number of
+         milliseconds we waited for the message. */
+      if (time_needed < timeouts->next->time) {
+        timeouts->next->time -= time_needed;
+      } else {
+        timeouts->next->time = 0;
+      }
+    }
+  }
+}
+
+/**
+ * Create a one-shot timer (aka timeout). Timeouts are processed in the
+ * following cases:
+ * - while waiting for a message using sys_mbox_fetch()
+ * - while waiting for a semaphore using sys_sem_wait() or sys_sem_wait_timeout()
+ * - while sleeping using the inbuilt sys_msleep()
+ *
+ * @param msecs time in milliseconds after that the timer should expire
+ * @param h callback function to call when msecs have elapsed
+ * @param arg argument to pass to the callback function
+ */
+void
+sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg)
+{
+  struct sys_timeouts *timeouts;
+  struct sys_timeo *timeout, *t;
+
+  timeout = memp_malloc(MEMP_SYS_TIMEOUT);
+  if (timeout == NULL) {
+    LWIP_ASSERT("sys_timeout: timeout != NULL", timeout != NULL);
+    return;
+  }
+  timeout->next = NULL;
+  timeout->h = h;
+  timeout->arg = arg;
+  timeout->time = msecs;
+
+  timeouts = sys_arch_timeouts();
+
+  LWIP_DEBUGF(SYS_DEBUG, ("sys_timeout: %p msecs=%"U32_F" h=%p arg=%p\n",
+    (void *)timeout, msecs, *(void**)&h, (void *)arg));
+
+  if (timeouts == NULL) {
+    LWIP_ASSERT("sys_timeout: timeouts != NULL", timeouts != NULL);
+    return;
+  }
+
+  if (timeouts->next == NULL) {
+    timeouts->next = timeout;
+    return;
+  }
+
+  if (timeouts->next->time > msecs) {
+    timeouts->next->time -= msecs;
+    timeout->next = timeouts->next;
+    timeouts->next = timeout;
+  } else {
+    for(t = timeouts->next; t != NULL; t = t->next) {
+      timeout->time -= t->time;
+      if (t->next == NULL || t->next->time > timeout->time) {
+        if (t->next != NULL) {
+          t->next->time -= timeout->time;
+        }
+        timeout->next = t->next;
+        t->next = timeout;
+        break;
+      }
+    }
+  }
+}
+
+/**
+ * Go through timeout list (for this task only) and remove the first matching
+ * entry, even though the timeout has not triggered yet.
+ *
+ * @note This function only works as expected if there is only one timeout
+ * calling 'h' in the list of timeouts.
+ *
+ * @param h callback function that would be called by the timeout
+ * @param arg callback argument that would be passed to h
+*/
+void
+sys_untimeout(sys_timeout_handler h, void *arg)
+{
+  struct sys_timeouts *timeouts;
+  struct sys_timeo *prev_t, *t;
+
+  timeouts = sys_arch_timeouts();
+
+  if (timeouts == NULL) {
+    LWIP_ASSERT("sys_untimeout: timeouts != NULL", timeouts != NULL);
+    return;
+  }
+  if (timeouts->next == NULL) {
+    return;
+  }
+
+  for (t = timeouts->next, prev_t = NULL; t != NULL; prev_t = t, t = t->next) {
+    if ((t->h == h) && (t->arg == arg)) {
+      /* We have a match */
+      /* Unlink from previous in list */
+      if (prev_t == NULL) {
+        timeouts->next = t->next;
+      } else {
+        prev_t->next = t->next;
+      }
+      /* If not the last one, add time of this one back to next */
+      if (t->next != NULL) {
+        t->next->time += t->time;
+      }
+      memp_free(MEMP_SYS_TIMEOUT, t);
+      return;
+    }
+  }
+  return;
+}
+
+/**
+ * Timeout handler function for sys_sem_wait_timeout()
+ *
+ * @param arg struct sswt_cb* used to signal a semaphore and end waiting.
+ */
+static void
+sswt_handler(void *arg)
+{
+  struct sswt_cb *sswt_cb = (struct sswt_cb *) arg;
+
+  /* Timeout. Set flag to TRUE and signal semaphore */
+  sswt_cb->timeflag = 1;
+  sys_sem_signal(*(sswt_cb->psem));
+}
+
+/**
+ * Wait for a semaphore with timeout (specified in ms)
+ *
+ * @param sem semaphore to wait
+ * @param timeout timeout in ms (0: wait forever)
+ * @return 0 on timeout, 1 otherwise
+ */
+int
+sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout)
+{
+  struct sswt_cb sswt_cb;
+
+  sswt_cb.psem = &sem;
+  sswt_cb.timeflag = 0;
+
+  /* If timeout is zero, then just wait forever */
+  if (timeout > 0) {
+    /* Create a timer and pass it the address of our flag */
+    sys_timeout(timeout, sswt_handler, &sswt_cb);
+  }
+  sys_sem_wait(sem);
+  /* Was it a timeout? */
+  if (sswt_cb.timeflag) {
+    /* timeout */
+    return 0;
+  } else {
+    /* Not a timeout. Remove timeout entry */
+    sys_untimeout(sswt_handler, &sswt_cb);
+    return 1;
+  }
+}
+
+/**
+ * Sleep for some ms. Timeouts are processed while sleeping.
+ *
+ * @param ms number of milliseconds to sleep
+ */
+void
+sys_msleep(u32_t ms)
+{
+  sys_sem_t delaysem = sys_sem_new(0);
+
+  sys_sem_wait_timeout(delaysem, ms);
+
+  sys_sem_free(delaysem);
+}
+
+
+#endif /* NO_SYS */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/tcp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/tcp.c
new file mode 100644
index 0000000..29cdf18
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/tcp.c
@@ -0,0 +1,1461 @@
+/**
+ * @file
+ * Transmission Control Protocol for IP
+ *
+ * This file contains common functions for the TCP implementation, such as functinos
+ * for manipulating the data structures and the TCP timer functions. TCP functions
+ * related to input and output is found in tcp_in.c and tcp_out.c respectively.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/snmp.h"
+#include "lwip/tcp.h"
+#include "lwip/debug.h"
+#include "lwip/stats.h"
+
+#include 
+
+const char *tcp_state_str[] = {
+  "CLOSED",      
+  "LISTEN",      
+  "SYN_SENT",    
+  "SYN_RCVD",    
+  "ESTABLISHED", 
+  "FIN_WAIT_1",  
+  "FIN_WAIT_2",  
+  "CLOSE_WAIT",  
+  "CLOSING",     
+  "LAST_ACK",    
+  "TIME_WAIT"   
+};
+
+/* Incremented every coarse grained timer shot (typically every 500 ms). */
+u32_t tcp_ticks;
+const u8_t tcp_backoff[13] =
+    { 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7};
+ /* Times per slowtmr hits */
+const u8_t tcp_persist_backoff[7] = { 3, 6, 12, 24, 48, 96, 120 };
+
+/* The TCP PCB lists. */
+
+/** List of all TCP PCBs bound but not yet (connected || listening) */
+struct tcp_pcb *tcp_bound_pcbs;  
+/** List of all TCP PCBs in LISTEN state */
+union tcp_listen_pcbs_t tcp_listen_pcbs;
+/** List of all TCP PCBs that are in a state in which
+ * they accept or send data. */
+struct tcp_pcb *tcp_active_pcbs;  
+/** List of all TCP PCBs in TIME-WAIT state */
+struct tcp_pcb *tcp_tw_pcbs;
+
+struct tcp_pcb *tcp_tmp_pcb;
+
+static u8_t tcp_timer;
+static u16_t tcp_new_port(void);
+
+/**
+ * Called periodically to dispatch TCP timers.
+ *
+ */
+void
+tcp_tmr(void)
+{
+  /* Call tcp_fasttmr() every 250 ms */
+  tcp_fasttmr();
+
+  if (++tcp_timer & 1) {
+    /* Call tcp_tmr() every 500 ms, i.e., every other timer
+       tcp_tmr() is called. */
+    tcp_slowtmr();
+  }
+}
+
+/**
+ * Closes the connection held by the PCB.
+ *
+ * Listening pcbs are freed and may not be referenced any more.
+ * Connection pcbs are freed if not yet connected and may not be referenced
+ * any more. If a connection is established (at least SYN received or in
+ * a closing state), the connection is closed, and put in a closing state.
+ * The pcb is then automatically freed in tcp_slowtmr(). It is therefore
+ * unsafe to reference it.
+ *
+ * @param pcb the tcp_pcb to close
+ * @return ERR_OK if connection has been closed
+ *         another err_t if closing failed and pcb is not freed
+ */
+err_t
+tcp_close(struct tcp_pcb *pcb)
+{
+  err_t err;
+
+#if TCP_DEBUG
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in "));
+  tcp_debug_print_state(pcb->state);
+#endif /* TCP_DEBUG */
+
+  switch (pcb->state) {
+  case CLOSED:
+    /* Closing a pcb in the CLOSED state might seem erroneous,
+     * however, it is in this state once allocated and as yet unused
+     * and the user needs some way to free it should the need arise.
+     * Calling tcp_close() with a pcb that has already been closed, (i.e. twice)
+     * or for a pcb that has been used and then entered the CLOSED state 
+     * is erroneous, but this should never happen as the pcb has in those cases
+     * been freed, and so any remaining handles are bogus. */
+    err = ERR_OK;
+    TCP_RMV(&tcp_bound_pcbs, pcb);
+    memp_free(MEMP_TCP_PCB, pcb);
+    pcb = NULL;
+    break;
+  case LISTEN:
+    err = ERR_OK;
+    tcp_pcb_remove((struct tcp_pcb **)&tcp_listen_pcbs.pcbs, pcb);
+    memp_free(MEMP_TCP_PCB_LISTEN, pcb);
+    pcb = NULL;
+    break;
+  case SYN_SENT:
+    err = ERR_OK;
+    tcp_pcb_remove(&tcp_active_pcbs, pcb);
+    memp_free(MEMP_TCP_PCB, pcb);
+    pcb = NULL;
+    snmp_inc_tcpattemptfails();
+    break;
+  case SYN_RCVD:
+    err = tcp_send_ctrl(pcb, TCP_FIN);
+    if (err == ERR_OK) {
+      snmp_inc_tcpattemptfails();
+      pcb->state = FIN_WAIT_1;
+    }
+    break;
+  case ESTABLISHED:
+    err = tcp_send_ctrl(pcb, TCP_FIN);
+    if (err == ERR_OK) {
+      snmp_inc_tcpestabresets();
+      pcb->state = FIN_WAIT_1;
+    }
+    break;
+  case CLOSE_WAIT:
+    err = tcp_send_ctrl(pcb, TCP_FIN);
+    if (err == ERR_OK) {
+      snmp_inc_tcpestabresets();
+      pcb->state = LAST_ACK;
+    }
+    break;
+  default:
+    /* Has already been closed, do nothing. */
+    err = ERR_OK;
+    pcb = NULL;
+    break;
+  }
+
+  if (pcb != NULL && err == ERR_OK) {
+    /* To ensure all data has been sent when tcp_close returns, we have
+       to make sure tcp_output doesn't fail.
+       Since we don't really have to ensure all data has been sent when tcp_close
+       returns (unsent data is sent from tcp timer functions, also), we don't care
+       for the return value of tcp_output for now. */
+    /* @todo: When implementing SO_LINGER, this must be changed somehow:
+       If SOF_LINGER is set, the data should be sent when tcp_close returns. */
+    tcp_output(pcb);
+  }
+  return err;
+}
+
+/**
+ * Abandons a connection and optionally sends a RST to the remote
+ * host.  Deletes the local protocol control block. This is done when
+ * a connection is killed because of shortage of memory.
+ *
+ * @param pcb the tcp_pcb to abort
+ * @param reset boolean to indicate whether a reset should be sent
+ */
+void
+tcp_abandon(struct tcp_pcb *pcb, int reset)
+{
+  u32_t seqno, ackno;
+  u16_t remote_port, local_port;
+  struct ip_addr remote_ip, local_ip;
+#if LWIP_CALLBACK_API  
+  void (* errf)(void *arg, err_t err);
+#endif /* LWIP_CALLBACK_API */
+  void *errf_arg;
+
+  
+  /* Figure out on which TCP PCB list we are, and remove us. If we
+     are in an active state, call the receive function associated with
+     the PCB with a NULL argument, and send an RST to the remote end. */
+  if (pcb->state == TIME_WAIT) {
+    tcp_pcb_remove(&tcp_tw_pcbs, pcb);
+    memp_free(MEMP_TCP_PCB, pcb);
+  } else {
+    seqno = pcb->snd_nxt;
+    ackno = pcb->rcv_nxt;
+    ip_addr_set(&local_ip, &(pcb->local_ip));
+    ip_addr_set(&remote_ip, &(pcb->remote_ip));
+    local_port = pcb->local_port;
+    remote_port = pcb->remote_port;
+#if LWIP_CALLBACK_API
+    errf = pcb->errf;
+#endif /* LWIP_CALLBACK_API */
+    errf_arg = pcb->callback_arg;
+    tcp_pcb_remove(&tcp_active_pcbs, pcb);
+    if (pcb->unacked != NULL) {
+      tcp_segs_free(pcb->unacked);
+    }
+    if (pcb->unsent != NULL) {
+      tcp_segs_free(pcb->unsent);
+    }
+#if TCP_QUEUE_OOSEQ    
+    if (pcb->ooseq != NULL) {
+      tcp_segs_free(pcb->ooseq);
+    }
+#endif /* TCP_QUEUE_OOSEQ */
+    memp_free(MEMP_TCP_PCB, pcb);
+    TCP_EVENT_ERR(errf, errf_arg, ERR_ABRT);
+    if (reset) {
+      LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abandon: sending RST\n"));
+      tcp_rst(seqno, ackno, &local_ip, &remote_ip, local_port, remote_port);
+    }
+  }
+}
+
+/**
+ * Binds the connection to a local portnumber and IP address. If the
+ * IP address is not given (i.e., ipaddr == NULL), the IP address of
+ * the outgoing network interface is used instead.
+ *
+ * @param pcb the tcp_pcb to bind (no check is done whether this pcb is
+ *        already bound!)
+ * @param ipaddr the local ip address to bind to (use IP_ADDR_ANY to bind
+ *        to any local address
+ * @param port the local port to bind to
+ * @return ERR_USE if the port is already in use
+ *         ERR_OK if bound
+ */
+err_t
+tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
+{
+  struct tcp_pcb *cpcb;
+
+  LWIP_ERROR("tcp_bind: can only bind in state CLOSED", pcb->state == CLOSED, return ERR_ISCONN);
+
+  if (port == 0) {
+    port = tcp_new_port();
+  }
+  /* Check if the address already is in use. */
+  /* Check the listen pcbs. */
+  for(cpcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs;
+      cpcb != NULL; cpcb = cpcb->next) {
+    if (cpcb->local_port == port) {
+      if (ip_addr_isany(&(cpcb->local_ip)) ||
+          ip_addr_isany(ipaddr) ||
+          ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
+        return ERR_USE;
+      }
+    }
+  }
+  /* Check the connected pcbs. */
+  for(cpcb = tcp_active_pcbs;
+      cpcb != NULL; cpcb = cpcb->next) {
+    if (cpcb->local_port == port) {
+      if (ip_addr_isany(&(cpcb->local_ip)) ||
+          ip_addr_isany(ipaddr) ||
+          ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
+        return ERR_USE;
+      }
+    }
+  }
+  /* Check the bound, not yet connected pcbs. */
+  for(cpcb = tcp_bound_pcbs; cpcb != NULL; cpcb = cpcb->next) {
+    if (cpcb->local_port == port) {
+      if (ip_addr_isany(&(cpcb->local_ip)) ||
+          ip_addr_isany(ipaddr) ||
+          ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
+        return ERR_USE;
+      }
+    }
+  }
+  /* @todo: until SO_REUSEADDR is implemented (see task #6995 on savannah),
+   * we have to check the pcbs in TIME-WAIT state, also: */
+  for(cpcb = tcp_tw_pcbs; cpcb != NULL; cpcb = cpcb->next) {
+    if (cpcb->local_port == port) {
+      if (ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
+        return ERR_USE;
+      }
+    }
+  }
+
+  if (!ip_addr_isany(ipaddr)) {
+    pcb->local_ip = *ipaddr;
+  }
+  pcb->local_port = port;
+  TCP_REG(&tcp_bound_pcbs, pcb);
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %"U16_F"\n", port));
+  return ERR_OK;
+}
+#if LWIP_CALLBACK_API
+/**
+ * Default accept callback if no accept callback is specified by the user.
+ */
+static err_t
+tcp_accept_null(void *arg, struct tcp_pcb *pcb, err_t err)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_UNUSED_ARG(err);
+
+  return ERR_ABRT;
+}
+#endif /* LWIP_CALLBACK_API */
+
+/**
+ * Set the state of the connection to be LISTEN, which means that it
+ * is able to accept incoming connections. The protocol control block
+ * is reallocated in order to consume less memory. Setting the
+ * connection to LISTEN is an irreversible process.
+ *
+ * @param pcb the original tcp_pcb
+ * @param backlog the incoming connections queue limit
+ * @return tcp_pcb used for listening, consumes less memory.
+ *
+ * @note The original tcp_pcb is freed. This function therefore has to be
+ *       called like this:
+ *             tpcb = tcp_listen(tpcb);
+ */
+struct tcp_pcb *
+tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog)
+{
+  struct tcp_pcb_listen *lpcb;
+
+  LWIP_UNUSED_ARG(backlog);
+  LWIP_ERROR("tcp_listen: pcb already connected", pcb->state == CLOSED, return NULL);
+
+  /* already listening? */
+  if (pcb->state == LISTEN) {
+    return pcb;
+  }
+  lpcb = memp_malloc(MEMP_TCP_PCB_LISTEN);
+  if (lpcb == NULL) {
+    return NULL;
+  }
+  lpcb->callback_arg = pcb->callback_arg;
+  lpcb->local_port = pcb->local_port;
+  lpcb->state = LISTEN;
+  lpcb->so_options = pcb->so_options;
+  lpcb->so_options |= SOF_ACCEPTCONN;
+  lpcb->ttl = pcb->ttl;
+  lpcb->tos = pcb->tos;
+  ip_addr_set(&lpcb->local_ip, &pcb->local_ip);
+  TCP_RMV(&tcp_bound_pcbs, pcb);
+  memp_free(MEMP_TCP_PCB, pcb);
+#if LWIP_CALLBACK_API
+  lpcb->accept = tcp_accept_null;
+#endif /* LWIP_CALLBACK_API */
+#if TCP_LISTEN_BACKLOG
+  lpcb->accepts_pending = 0;
+  lpcb->backlog = (backlog ? backlog : 1);
+#endif /* TCP_LISTEN_BACKLOG */
+  TCP_REG(&tcp_listen_pcbs.listen_pcbs, lpcb);
+  return (struct tcp_pcb *)lpcb;
+}
+
+/** 
+ * Update the state that tracks the available window space to advertise.
+ *
+ * Returns how much extra window would be advertised if we sent an
+ * update now.
+ */
+u32_t tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb)
+{
+  u32_t new_right_edge = pcb->rcv_nxt + pcb->rcv_wnd;
+
+  if (TCP_SEQ_GEQ(new_right_edge, pcb->rcv_ann_right_edge + LWIP_MIN((TCP_WND / 2), pcb->mss))) {
+    /* we can advertise more window */
+    pcb->rcv_ann_wnd = pcb->rcv_wnd;
+    return new_right_edge - pcb->rcv_ann_right_edge;
+  } else {
+    if (TCP_SEQ_GT(pcb->rcv_nxt, pcb->rcv_ann_right_edge)) {
+      /* Can happen due to other end sending out of advertised window,
+       * but within actual available (but not yet advertised) window */
+      pcb->rcv_ann_wnd = 0;
+    } else {
+      /* keep the right edge of window constant */
+      pcb->rcv_ann_wnd = pcb->rcv_ann_right_edge - pcb->rcv_nxt;
+    }
+    return 0;
+  }
+}
+
+/**
+ * This function should be called by the application when it has
+ * processed the data. The purpose is to advertise a larger window
+ * when the data has been processed.
+ *
+ * @param pcb the tcp_pcb for which data is read
+ * @param len the amount of bytes that have been read by the application
+ */
+void
+tcp_recved(struct tcp_pcb *pcb, u16_t len)
+{
+  int wnd_inflation;
+
+  LWIP_ASSERT("tcp_recved: len would wrap rcv_wnd\n",
+              len <= 0xffff - pcb->rcv_wnd );
+
+  pcb->rcv_wnd += len;
+  if (pcb->rcv_wnd > TCP_WND)
+    pcb->rcv_wnd = TCP_WND;
+
+  wnd_inflation = tcp_update_rcv_ann_wnd(pcb);
+
+  /* If the change in the right edge of window is significant (default
+   * watermark is TCP_WND/2), then send an explicit update now.
+   * Otherwise wait for a packet to be sent in the normal course of
+   * events (or more window to be available later) */
+  if (wnd_inflation >= TCP_WND_UPDATE_THRESHOLD) 
+    tcp_ack_now(pcb);
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: recveived %"U16_F" bytes, wnd %"U16_F" (%"U16_F").\n",
+         len, pcb->rcv_wnd, TCP_WND - pcb->rcv_wnd));
+}
+
+/**
+ * A nastly hack featuring 'goto' statements that allocates a
+ * new TCP local port.
+ *
+ * @return a new (free) local TCP port number
+ */
+static u16_t
+tcp_new_port(void)
+{
+  struct tcp_pcb *pcb;
+#ifndef TCP_LOCAL_PORT_RANGE_START
+#define TCP_LOCAL_PORT_RANGE_START 4096
+#define TCP_LOCAL_PORT_RANGE_END   0x7fff
+#endif
+  static u16_t port = TCP_LOCAL_PORT_RANGE_START;
+  
+ again:
+  if (++port > TCP_LOCAL_PORT_RANGE_END) {
+    port = TCP_LOCAL_PORT_RANGE_START;
+  }
+  
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->local_port == port) {
+      goto again;
+    }
+  }
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->local_port == port) {
+      goto again;
+    }
+  }
+  for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->local_port == port) {
+      goto again;
+    }
+  }
+  return port;
+}
+
+/**
+ * Connects to another host. The function given as the "connected"
+ * argument will be called when the connection has been established.
+ *
+ * @param pcb the tcp_pcb used to establish the connection
+ * @param ipaddr the remote ip address to connect to
+ * @param port the remote tcp port to connect to
+ * @param connected callback function to call when connected (or on error)
+ * @return ERR_VAL if invalid arguments are given
+ *         ERR_OK if connect request has been sent
+ *         other err_t values if connect request couldn't be sent
+ */
+err_t
+tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port,
+      err_t (* connected)(void *arg, struct tcp_pcb *tpcb, err_t err))
+{
+  err_t ret;
+  u32_t iss;
+
+  LWIP_ERROR("tcp_connect: can only connected from state CLOSED", pcb->state == CLOSED, return ERR_ISCONN);
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %"U16_F"\n", port));
+  if (ipaddr != NULL) {
+    pcb->remote_ip = *ipaddr;
+  } else {
+    return ERR_VAL;
+  }
+  pcb->remote_port = port;
+  if (pcb->local_port == 0) {
+    pcb->local_port = tcp_new_port();
+  }
+  iss = tcp_next_iss();
+  pcb->rcv_nxt = 0;
+  pcb->snd_nxt = iss;
+  pcb->lastack = iss - 1;
+  pcb->snd_lbb = iss - 1;
+  pcb->rcv_wnd = TCP_WND;
+  pcb->rcv_ann_wnd = TCP_WND;
+  pcb->rcv_ann_right_edge = pcb->rcv_nxt;
+  pcb->snd_wnd = TCP_WND;
+  /* As initial send MSS, we use TCP_MSS but limit it to 536.
+     The send MSS is updated when an MSS option is received. */
+  pcb->mss = (TCP_MSS > 536) ? 536 : TCP_MSS;
+#if TCP_CALCULATE_EFF_SEND_MSS
+  pcb->mss = tcp_eff_send_mss(pcb->mss, ipaddr);
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+  pcb->cwnd = 1;
+  pcb->ssthresh = pcb->mss * 10;
+  pcb->state = SYN_SENT;
+#if LWIP_CALLBACK_API  
+  pcb->connected = connected;
+#endif /* LWIP_CALLBACK_API */
+  TCP_RMV(&tcp_bound_pcbs, pcb);
+  TCP_REG(&tcp_active_pcbs, pcb);
+
+  snmp_inc_tcpactiveopens();
+  
+  ret = tcp_enqueue(pcb, NULL, 0, TCP_SYN, 0, TF_SEG_OPTS_MSS
+#if LWIP_TCP_TIMESTAMPS
+                    | TF_SEG_OPTS_TS
+#endif
+                    );
+  if (ret == ERR_OK) { 
+    tcp_output(pcb);
+  }
+  return ret;
+} 
+
+/**
+ * Called every 500 ms and implements the retransmission timer and the timer that
+ * removes PCBs that have been in TIME-WAIT for enough time. It also increments
+ * various timers such as the inactivity timer in each PCB.
+ *
+ * Automatically called from tcp_tmr().
+ */
+void
+tcp_slowtmr(void)
+{
+  struct tcp_pcb *pcb, *pcb2, *prev;
+  u16_t eff_wnd;
+  u8_t pcb_remove;      /* flag if a PCB should be removed */
+  u8_t pcb_reset;       /* flag if a RST should be sent when removing */
+  err_t err;
+
+  err = ERR_OK;
+
+  ++tcp_ticks;
+
+  /* Steps through all of the active PCBs. */
+  prev = NULL;
+  pcb = tcp_active_pcbs;
+  if (pcb == NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n"));
+  }
+  while (pcb != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n"));
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN);
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT);
+
+    pcb_remove = 0;
+    pcb_reset = 0;
+
+    if (pcb->state == SYN_SENT && pcb->nrtx == TCP_SYNMAXRTX) {
+      ++pcb_remove;
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n"));
+    }
+    else if (pcb->nrtx == TCP_MAXRTX) {
+      ++pcb_remove;
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n"));
+    } else {
+      if (pcb->persist_backoff > 0) {
+        /* If snd_wnd is zero, use persist timer to send 1 byte probes
+         * instead of using the standard retransmission mechanism. */
+        pcb->persist_cnt++;
+        if (pcb->persist_cnt >= tcp_persist_backoff[pcb->persist_backoff-1]) {
+          pcb->persist_cnt = 0;
+          if (pcb->persist_backoff < sizeof(tcp_persist_backoff)) {
+            pcb->persist_backoff++;
+          }
+          tcp_zero_window_probe(pcb);
+        }
+      } else {
+        /* Increase the retransmission timer if it is running */
+        if(pcb->rtime >= 0)
+          ++pcb->rtime;
+
+        if (pcb->unacked != NULL && pcb->rtime >= pcb->rto) {
+          /* Time for a retransmission. */
+          LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_slowtmr: rtime %"S16_F
+                                      " pcb->rto %"S16_F"\n",
+                                      pcb->rtime, pcb->rto));
+
+          /* Double retransmission time-out unless we are trying to
+           * connect to somebody (i.e., we are in SYN_SENT). */
+          if (pcb->state != SYN_SENT) {
+            pcb->rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[pcb->nrtx];
+          }
+
+          /* Reset the retransmission timer. */
+          pcb->rtime = 0;
+
+          /* Reduce congestion window and ssthresh. */
+          eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd);
+          pcb->ssthresh = eff_wnd >> 1;
+          if (pcb->ssthresh < pcb->mss) {
+            pcb->ssthresh = pcb->mss * 2;
+          }
+          pcb->cwnd = pcb->mss;
+          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"U16_F
+                                       " ssthresh %"U16_F"\n",
+                                       pcb->cwnd, pcb->ssthresh));
+ 
+          /* The following needs to be called AFTER cwnd is set to one
+             mss - STJ */
+          tcp_rexmit_rto(pcb);
+        }
+      }
+    }
+    /* Check if this PCB has stayed too long in FIN-WAIT-2 */
+    if (pcb->state == FIN_WAIT_2) {
+      if ((u32_t)(tcp_ticks - pcb->tmr) >
+          TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) {
+        ++pcb_remove;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in FIN-WAIT-2\n"));
+      }
+    }
+
+    /* Check if KEEPALIVE should be sent */
+    if((pcb->so_options & SOF_KEEPALIVE) && 
+       ((pcb->state == ESTABLISHED) || 
+        (pcb->state == CLOSE_WAIT))) {
+#if LWIP_TCP_KEEPALIVE
+      if((u32_t)(tcp_ticks - pcb->tmr) > 
+         (pcb->keep_idle + (pcb->keep_cnt*pcb->keep_intvl))
+         / TCP_SLOW_INTERVAL)
+#else      
+      if((u32_t)(tcp_ticks - pcb->tmr) > 
+         (pcb->keep_idle + TCP_MAXIDLE) / TCP_SLOW_INTERVAL)
+#endif /* LWIP_TCP_KEEPALIVE */
+      {
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to %"U16_F".%"U16_F".%"U16_F".%"U16_F".\n",
+                                ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+                                ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip)));
+        
+        ++pcb_remove;
+        ++pcb_reset;
+      }
+#if LWIP_TCP_KEEPALIVE
+      else if((u32_t)(tcp_ticks - pcb->tmr) > 
+              (pcb->keep_idle + pcb->keep_cnt_sent * pcb->keep_intvl)
+              / TCP_SLOW_INTERVAL)
+#else
+      else if((u32_t)(tcp_ticks - pcb->tmr) > 
+              (pcb->keep_idle + pcb->keep_cnt_sent * TCP_KEEPINTVL_DEFAULT) 
+              / TCP_SLOW_INTERVAL)
+#endif /* LWIP_TCP_KEEPALIVE */
+      {
+        tcp_keepalive(pcb);
+        pcb->keep_cnt_sent++;
+      }
+    }
+
+    /* If this PCB has queued out of sequence data, but has been
+       inactive for too long, will drop the data (it will eventually
+       be retransmitted). */
+#if TCP_QUEUE_OOSEQ    
+    if (pcb->ooseq != NULL &&
+        (u32_t)tcp_ticks - pcb->tmr >= pcb->rto * TCP_OOSEQ_TIMEOUT) {
+      tcp_segs_free(pcb->ooseq);
+      pcb->ooseq = NULL;
+      LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n"));
+    }
+#endif /* TCP_QUEUE_OOSEQ */
+
+    /* Check if this PCB has stayed too long in SYN-RCVD */
+    if (pcb->state == SYN_RCVD) {
+      if ((u32_t)(tcp_ticks - pcb->tmr) >
+          TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) {
+        ++pcb_remove;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n"));
+      }
+    }
+
+    /* Check if this PCB has stayed too long in LAST-ACK */
+    if (pcb->state == LAST_ACK) {
+      if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
+        ++pcb_remove;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n"));
+      }
+    }
+
+    /* If the PCB should be removed, do it. */
+    if (pcb_remove) {
+      tcp_pcb_purge(pcb);      
+      /* Remove PCB from tcp_active_pcbs list. */
+      if (prev != NULL) {
+        LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs);
+        prev->next = pcb->next;
+      } else {
+        /* This PCB was the first. */
+        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb);
+        tcp_active_pcbs = pcb->next;
+      }
+
+      TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_ABRT);
+      if (pcb_reset) {
+        tcp_rst(pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip,
+          pcb->local_port, pcb->remote_port);
+      }
+
+      pcb2 = pcb->next;
+      memp_free(MEMP_TCP_PCB, pcb);
+      pcb = pcb2;
+    } else {
+
+      /* We check if we should poll the connection. */
+      ++pcb->polltmr;
+      if (pcb->polltmr >= pcb->pollinterval) {
+        pcb->polltmr = 0;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n"));
+        TCP_EVENT_POLL(pcb, err);
+        if (err == ERR_OK) {
+          tcp_output(pcb);
+        }
+      }
+      
+      prev = pcb;
+      pcb = pcb->next;
+    }
+  }
+
+  
+  /* Steps through all of the TIME-WAIT PCBs. */
+  prev = NULL;    
+  pcb = tcp_tw_pcbs;
+  while (pcb != NULL) {
+    LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+    pcb_remove = 0;
+
+    /* Check if this PCB has stayed long enough in TIME-WAIT */
+    if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
+      ++pcb_remove;
+    }
+    
+
+
+    /* If the PCB should be removed, do it. */
+    if (pcb_remove) {
+      tcp_pcb_purge(pcb);      
+      /* Remove PCB from tcp_tw_pcbs list. */
+      if (prev != NULL) {
+        LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs);
+        prev->next = pcb->next;
+      } else {
+        /* This PCB was the first. */
+        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb);
+        tcp_tw_pcbs = pcb->next;
+      }
+      pcb2 = pcb->next;
+      memp_free(MEMP_TCP_PCB, pcb);
+      pcb = pcb2;
+    } else {
+      prev = pcb;
+      pcb = pcb->next;
+    }
+  }
+}
+
+/**
+ * Is called every TCP_FAST_INTERVAL (250 ms) and process data previously
+ * "refused" by upper layer (application) and sends delayed ACKs.
+ *
+ * Automatically called from tcp_tmr().
+ */
+void
+tcp_fasttmr(void)
+{
+  struct tcp_pcb *pcb;
+
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    /* If there is data which was previously "refused" by upper layer */
+    if (pcb->refused_data != NULL) {
+      /* Notify again application with data previously received. */
+      err_t err;
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_fasttmr: notify kept packet\n"));
+      TCP_EVENT_RECV(pcb, pcb->refused_data, ERR_OK, err);
+      if (err == ERR_OK) {
+        pcb->refused_data = NULL;
+      }
+    }
+
+    /* send delayed ACKs */  
+    if (pcb->flags & TF_ACK_DELAY) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n"));
+      tcp_ack_now(pcb);
+      pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
+    }
+  }
+}
+
+/**
+ * Deallocates a list of TCP segments (tcp_seg structures).
+ *
+ * @param seg tcp_seg list of TCP segments to free
+ * @return the number of pbufs that were deallocated
+ */
+u8_t
+tcp_segs_free(struct tcp_seg *seg)
+{
+  u8_t count = 0;
+  struct tcp_seg *next;
+  while (seg != NULL) {
+    next = seg->next;
+    count += tcp_seg_free(seg);
+    seg = next;
+  }
+  return count;
+}
+
+/**
+ * Frees a TCP segment (tcp_seg structure).
+ *
+ * @param seg single tcp_seg to free
+ * @return the number of pbufs that were deallocated
+ */
+u8_t
+tcp_seg_free(struct tcp_seg *seg)
+{
+  u8_t count = 0;
+  
+  if (seg != NULL) {
+    if (seg->p != NULL) {
+      count = pbuf_free(seg->p);
+#if TCP_DEBUG
+      seg->p = NULL;
+#endif /* TCP_DEBUG */
+    }
+    memp_free(MEMP_TCP_SEG, seg);
+  }
+  return count;
+}
+
+/**
+ * Sets the priority of a connection.
+ *
+ * @param pcb the tcp_pcb to manipulate
+ * @param prio new priority
+ */
+void
+tcp_setprio(struct tcp_pcb *pcb, u8_t prio)
+{
+  pcb->prio = prio;
+}
+#if TCP_QUEUE_OOSEQ
+
+/**
+ * Returns a copy of the given TCP segment.
+ * The pbuf and data are not copied, only the pointers
+ *
+ * @param seg the old tcp_seg
+ * @return a copy of seg
+ */ 
+struct tcp_seg *
+tcp_seg_copy(struct tcp_seg *seg)
+{
+  struct tcp_seg *cseg;
+
+  cseg = memp_malloc(MEMP_TCP_SEG);
+  if (cseg == NULL) {
+    return NULL;
+  }
+  SMEMCPY((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg)); 
+  pbuf_ref(cseg->p);
+  return cseg;
+}
+#endif
+
+#if LWIP_CALLBACK_API
+/**
+ * Default receive callback that is called if the user didn't register
+ * a recv callback for the pcb.
+ */
+err_t
+tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
+{
+  LWIP_UNUSED_ARG(arg);
+  if (p != NULL) {
+    tcp_recved(pcb, p->tot_len);
+    pbuf_free(p);
+  } else if (err == ERR_OK) {
+    return tcp_close(pcb);
+  }
+  return ERR_OK;
+}
+#endif /* LWIP_CALLBACK_API */
+
+/**
+ * Kills the oldest active connection that has lower priority than prio.
+ *
+ * @param prio minimum priority
+ */
+static void
+tcp_kill_prio(u8_t prio)
+{
+  struct tcp_pcb *pcb, *inactive;
+  u32_t inactivity;
+  u8_t mprio;
+
+
+  mprio = TCP_PRIO_MAX;
+  
+  /* We kill the oldest active connection that has lower priority than prio. */
+  inactivity = 0;
+  inactive = NULL;
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->prio <= prio &&
+       pcb->prio <= mprio &&
+       (u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
+      inactivity = tcp_ticks - pcb->tmr;
+      inactive = pcb;
+      mprio = pcb->prio;
+    }
+  }
+  if (inactive != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n",
+           (void *)inactive, inactivity));
+    tcp_abort(inactive);
+  }      
+}
+
+/**
+ * Kills the oldest connection that is in TIME_WAIT state.
+ * Called from tcp_alloc() if no more connections are available.
+ */
+static void
+tcp_kill_timewait(void)
+{
+  struct tcp_pcb *pcb, *inactive;
+  u32_t inactivity;
+
+  inactivity = 0;
+  inactive = NULL;
+  /* Go through the list of TIME_WAIT pcbs and get the oldest pcb. */
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
+      inactivity = tcp_ticks - pcb->tmr;
+      inactive = pcb;
+    }
+  }
+  if (inactive != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n",
+           (void *)inactive, inactivity));
+    tcp_abort(inactive);
+  }      
+}
+
+/**
+ * Allocate a new tcp_pcb structure.
+ *
+ * @param prio priority for the new pcb
+ * @return a new tcp_pcb that initially is in state CLOSED
+ */
+struct tcp_pcb *
+tcp_alloc(u8_t prio)
+{
+  struct tcp_pcb *pcb;
+  u32_t iss;
+  
+  pcb = memp_malloc(MEMP_TCP_PCB);
+  if (pcb == NULL) {
+    /* Try killing oldest connection in TIME-WAIT. */
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n"));
+    tcp_kill_timewait();
+    /* Try to allocate a tcp_pcb again. */
+    pcb = memp_malloc(MEMP_TCP_PCB);
+    if (pcb == NULL) {
+      /* Try killing active connections with lower priority than the new one. */
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing connection with prio lower than %d\n", prio));
+      tcp_kill_prio(prio);
+      /* Try to allocate a tcp_pcb again. */
+      pcb = memp_malloc(MEMP_TCP_PCB);
+      if (pcb != NULL) {
+        /* adjust err stats: memp_malloc failed twice before */
+        MEMP_STATS_DEC(err, MEMP_TCP_PCB);
+      }
+    }
+    if (pcb != NULL) {
+      /* adjust err stats: timewait PCB was freed above */
+      MEMP_STATS_DEC(err, MEMP_TCP_PCB);
+    }
+  }
+  if (pcb != NULL) {
+    memset(pcb, 0, sizeof(struct tcp_pcb));
+    pcb->prio = TCP_PRIO_NORMAL;
+    pcb->snd_buf = TCP_SND_BUF;
+    pcb->snd_queuelen = 0;
+    pcb->rcv_wnd = TCP_WND;
+    pcb->rcv_ann_wnd = TCP_WND;
+    pcb->tos = 0;
+    pcb->ttl = TCP_TTL;
+    /* As initial send MSS, we use TCP_MSS but limit it to 536.
+       The send MSS is updated when an MSS option is received. */
+    pcb->mss = (TCP_MSS > 536) ? 536 : TCP_MSS;
+    pcb->rto = 3000 / TCP_SLOW_INTERVAL;
+    pcb->sa = 0;
+    pcb->sv = 3000 / TCP_SLOW_INTERVAL;
+    pcb->rtime = -1;
+    pcb->cwnd = 1;
+    iss = tcp_next_iss();
+    pcb->snd_wl2 = iss;
+    pcb->snd_nxt = iss;
+    pcb->lastack = iss;
+    pcb->snd_lbb = iss;   
+    pcb->tmr = tcp_ticks;
+
+    pcb->polltmr = 0;
+
+#if LWIP_CALLBACK_API
+    pcb->recv = tcp_recv_null;
+#endif /* LWIP_CALLBACK_API */  
+    
+    /* Init KEEPALIVE timer */
+    pcb->keep_idle  = TCP_KEEPIDLE_DEFAULT;
+    
+#if LWIP_TCP_KEEPALIVE
+    pcb->keep_intvl = TCP_KEEPINTVL_DEFAULT;
+    pcb->keep_cnt   = TCP_KEEPCNT_DEFAULT;
+#endif /* LWIP_TCP_KEEPALIVE */
+
+    pcb->keep_cnt_sent = 0;
+  }
+  return pcb;
+}
+
+/**
+ * Creates a new TCP protocol control block but doesn't place it on
+ * any of the TCP PCB lists.
+ * The pcb is not put on any list until binding using tcp_bind().
+ *
+ * @internal: Maybe there should be a idle TCP PCB list where these
+ * PCBs are put on. Port reservation using tcp_bind() is implemented but
+ * allocated pcbs that are not bound can't be killed automatically if wanting
+ * to allocate a pcb with higher prio (@see tcp_kill_prio())
+ *
+ * @return a new tcp_pcb that initially is in state CLOSED
+ */
+struct tcp_pcb *
+tcp_new(void)
+{
+  return tcp_alloc(TCP_PRIO_NORMAL);
+}
+
+/**
+ * Used to specify the argument that should be passed callback
+ * functions.
+ *
+ * @param pcb tcp_pcb to set the callback argument
+ * @param arg void pointer argument to pass to callback functions
+ */ 
+void
+tcp_arg(struct tcp_pcb *pcb, void *arg)
+{  
+  pcb->callback_arg = arg;
+}
+#if LWIP_CALLBACK_API
+
+/**
+ * Used to specify the function that should be called when a TCP
+ * connection receives data.
+ *
+ * @param pcb tcp_pcb to set the recv callback
+ * @param recv callback function to call for this pcb when data is received
+ */ 
+void
+tcp_recv(struct tcp_pcb *pcb,
+   err_t (* recv)(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err))
+{
+  pcb->recv = recv;
+}
+
+/**
+ * Used to specify the function that should be called when TCP data
+ * has been successfully delivered to the remote host.
+ *
+ * @param pcb tcp_pcb to set the sent callback
+ * @param sent callback function to call for this pcb when data is successfully sent
+ */ 
+void
+tcp_sent(struct tcp_pcb *pcb,
+   err_t (* sent)(void *arg, struct tcp_pcb *tpcb, u16_t len))
+{
+  pcb->sent = sent;
+}
+
+/**
+ * Used to specify the function that should be called when a fatal error
+ * has occured on the connection.
+ *
+ * @param pcb tcp_pcb to set the err callback
+ * @param errf callback function to call for this pcb when a fatal error
+ *        has occured on the connection
+ */ 
+void
+tcp_err(struct tcp_pcb *pcb,
+   void (* errf)(void *arg, err_t err))
+{
+  pcb->errf = errf;
+}
+
+/**
+ * Used for specifying the function that should be called when a
+ * LISTENing connection has been connected to another host.
+ *
+ * @param pcb tcp_pcb to set the accept callback
+ * @param accept callback function to call for this pcb when LISTENing
+ *        connection has been connected to another host
+ */ 
+void
+tcp_accept(struct tcp_pcb *pcb,
+     err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err))
+{
+  pcb->accept = accept;
+}
+#endif /* LWIP_CALLBACK_API */
+
+
+/**
+ * Used to specify the function that should be called periodically
+ * from TCP. The interval is specified in terms of the TCP coarse
+ * timer interval, which is called twice a second.
+ *
+ */ 
+void
+tcp_poll(struct tcp_pcb *pcb,
+   err_t (* poll)(void *arg, struct tcp_pcb *tpcb), u8_t interval)
+{
+#if LWIP_CALLBACK_API
+  pcb->poll = poll;
+#endif /* LWIP_CALLBACK_API */  
+  pcb->pollinterval = interval;
+}
+
+/**
+ * Purges a TCP PCB. Removes any buffered data and frees the buffer memory
+ * (pcb->ooseq, pcb->unsent and pcb->unacked are freed).
+ *
+ * @param pcb tcp_pcb to purge. The pcb itself is not deallocated!
+ */
+void
+tcp_pcb_purge(struct tcp_pcb *pcb)
+{
+  if (pcb->state != CLOSED &&
+     pcb->state != TIME_WAIT &&
+     pcb->state != LISTEN) {
+
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n"));
+
+#if TCP_LISTEN_BACKLOG
+    if (pcb->state == SYN_RCVD) {
+      /* Need to find the corresponding listen_pcb and decrease its accepts_pending */
+      struct tcp_pcb_listen *lpcb;
+      LWIP_ASSERT("tcp_pcb_purge: pcb->state == SYN_RCVD but tcp_listen_pcbs is NULL",
+        tcp_listen_pcbs.listen_pcbs != NULL);
+      for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+        if ((lpcb->local_port == pcb->local_port) &&
+            (ip_addr_isany(&lpcb->local_ip) ||
+             ip_addr_cmp(&pcb->local_ip, &lpcb->local_ip))) {
+            /* port and address of the listen pcb match the timed-out pcb */
+            LWIP_ASSERT("tcp_pcb_purge: listen pcb does not have accepts pending",
+              lpcb->accepts_pending > 0);
+            lpcb->accepts_pending--;
+            break;
+          }
+      }
+    }
+#endif /* TCP_LISTEN_BACKLOG */
+
+
+    if (pcb->refused_data != NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->refused_data\n"));
+      pbuf_free(pcb->refused_data);
+      pcb->refused_data = NULL;
+    }
+    if (pcb->unsent != NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: not all data sent\n"));
+    }
+    if (pcb->unacked != NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n"));
+    }
+#if TCP_QUEUE_OOSEQ /* LW */
+    if (pcb->ooseq != NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n"));
+    }
+
+    /* Stop the retransmission timer as it will expect data on unacked
+       queue if it fires */
+    pcb->rtime = -1;
+
+    tcp_segs_free(pcb->ooseq);
+    pcb->ooseq = NULL;
+#endif /* TCP_QUEUE_OOSEQ */
+    tcp_segs_free(pcb->unsent);
+    tcp_segs_free(pcb->unacked);
+    pcb->unacked = pcb->unsent = NULL;
+  }
+}
+
+/**
+ * Purges the PCB and removes it from a PCB list. Any delayed ACKs are sent first.
+ *
+ * @param pcblist PCB list to purge.
+ * @param pcb tcp_pcb to purge. The pcb itself is NOT deallocated!
+ */
+void
+tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb)
+{
+  TCP_RMV(pcblist, pcb);
+
+  tcp_pcb_purge(pcb);
+  
+  /* if there is an outstanding delayed ACKs, send it */
+  if (pcb->state != TIME_WAIT &&
+     pcb->state != LISTEN &&
+     pcb->flags & TF_ACK_DELAY) {
+    pcb->flags |= TF_ACK_NOW;
+    tcp_output(pcb);
+  }
+
+  if (pcb->state != LISTEN) {
+    LWIP_ASSERT("unsent segments leaking", pcb->unsent == NULL);
+    LWIP_ASSERT("unacked segments leaking", pcb->unacked == NULL);
+#if TCP_QUEUE_OOSEQ
+    LWIP_ASSERT("ooseq segments leaking", pcb->ooseq == NULL);
+#endif /* TCP_QUEUE_OOSEQ */
+  }
+
+  pcb->state = CLOSED;
+
+  LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane());
+}
+
+/**
+ * Calculates a new initial sequence number for new connections.
+ *
+ * @return u32_t pseudo random sequence number
+ */
+u32_t
+tcp_next_iss(void)
+{
+  static u32_t iss = 6510;
+  
+  iss += tcp_ticks;       /* XXX */
+  return iss;
+}
+
+#if TCP_CALCULATE_EFF_SEND_MSS
+/**
+ * Calcluates the effective send mss that can be used for a specific IP address
+ * by using ip_route to determin the netif used to send to the address and
+ * calculating the minimum of TCP_MSS and that netif's mtu (if set).
+ */
+u16_t
+tcp_eff_send_mss(u16_t sendmss, struct ip_addr *addr)
+{
+  u16_t mss_s;
+  struct netif *outif;
+
+  outif = ip_route(addr);
+  if ((outif != NULL) && (outif->mtu != 0)) {
+    mss_s = outif->mtu - IP_HLEN - TCP_HLEN;
+    /* RFC 1122, chap 4.2.2.6:
+     * Eff.snd.MSS = min(SendMSS+20, MMS_S) - TCPhdrsize - IPoptionsize
+     * We correct for TCP options in tcp_enqueue(), and don't support
+     * IP options
+     */
+    sendmss = LWIP_MIN(sendmss, mss_s);
+  }
+  return sendmss;
+}
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+
+const char*
+tcp_debug_state_str(enum tcp_state s)
+{
+  return tcp_state_str[s];
+}
+
+#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
+/**
+ * Print a tcp header for debugging purposes.
+ *
+ * @param tcphdr pointer to a struct tcp_hdr
+ */
+void
+tcp_debug_print(struct tcp_hdr *tcphdr)
+{
+  LWIP_DEBUGF(TCP_DEBUG, ("TCP header:\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|    %5"U16_F"      |    %5"U16_F"      | (src port, dest port)\n",
+         ntohs(tcphdr->src), ntohs(tcphdr->dest)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|           %010"U32_F"          | (seq no)\n",
+          ntohl(tcphdr->seqno)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|           %010"U32_F"          | (ack no)\n",
+         ntohl(tcphdr->ackno)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("| %2"U16_F" |   |%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"|     %5"U16_F"     | (hdrlen, flags (",
+       TCPH_HDRLEN(tcphdr),
+         TCPH_FLAGS(tcphdr) >> 5 & 1,
+         TCPH_FLAGS(tcphdr) >> 4 & 1,
+         TCPH_FLAGS(tcphdr) >> 3 & 1,
+         TCPH_FLAGS(tcphdr) >> 2 & 1,
+         TCPH_FLAGS(tcphdr) >> 1 & 1,
+         TCPH_FLAGS(tcphdr) & 1,
+         ntohs(tcphdr->wnd)));
+  tcp_debug_print_flags(TCPH_FLAGS(tcphdr));
+  LWIP_DEBUGF(TCP_DEBUG, ("), win)\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|    0x%04"X16_F"     |     %5"U16_F"     | (chksum, urgp)\n",
+         ntohs(tcphdr->chksum), ntohs(tcphdr->urgp)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+}
+
+/**
+ * Print a tcp state for debugging purposes.
+ *
+ * @param s enum tcp_state to print
+ */
+void
+tcp_debug_print_state(enum tcp_state s)
+{
+  LWIP_DEBUGF(TCP_DEBUG, ("State: %s\n", tcp_state_str[s]));
+}
+
+/**
+ * Print tcp flags for debugging purposes.
+ *
+ * @param flags tcp flags, all active flags are printed
+ */
+void
+tcp_debug_print_flags(u8_t flags)
+{
+  if (flags & TCP_FIN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("FIN "));
+  }
+  if (flags & TCP_SYN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("SYN "));
+  }
+  if (flags & TCP_RST) {
+    LWIP_DEBUGF(TCP_DEBUG, ("RST "));
+  }
+  if (flags & TCP_PSH) {
+    LWIP_DEBUGF(TCP_DEBUG, ("PSH "));
+  }
+  if (flags & TCP_ACK) {
+    LWIP_DEBUGF(TCP_DEBUG, ("ACK "));
+  }
+  if (flags & TCP_URG) {
+    LWIP_DEBUGF(TCP_DEBUG, ("URG "));
+  }
+  if (flags & TCP_ECE) {
+    LWIP_DEBUGF(TCP_DEBUG, ("ECE "));
+  }
+  if (flags & TCP_CWR) {
+    LWIP_DEBUGF(TCP_DEBUG, ("CWR "));
+  }
+  LWIP_DEBUGF(TCP_DEBUG, ("\n"));
+}
+
+/**
+ * Print all tcp_pcbs in every list for debugging purposes.
+ */
+void
+tcp_debug_print_pcbs(void)
+{
+  struct tcp_pcb *pcb;
+  LWIP_DEBUGF(TCP_DEBUG, ("Active PCB states:\n"));
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ",
+                       pcb->local_port, pcb->remote_port,
+                       pcb->snd_nxt, pcb->rcv_nxt));
+    tcp_debug_print_state(pcb->state);
+  }    
+  LWIP_DEBUGF(TCP_DEBUG, ("Listen PCB states:\n"));
+  for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ",
+                       pcb->local_port, pcb->remote_port,
+                       pcb->snd_nxt, pcb->rcv_nxt));
+    tcp_debug_print_state(pcb->state);
+  }    
+  LWIP_DEBUGF(TCP_DEBUG, ("TIME-WAIT PCB states:\n"));
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ",
+                       pcb->local_port, pcb->remote_port,
+                       pcb->snd_nxt, pcb->rcv_nxt));
+    tcp_debug_print_state(pcb->state);
+  }    
+}
+
+/**
+ * Check state consistency of the tcp_pcb lists.
+ */
+s16_t
+tcp_pcbs_sane(void)
+{
+  struct tcp_pcb *pcb;
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != CLOSED", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != LISTEN", pcb->state != LISTEN);
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
+  }
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_ASSERT("tcp_pcbs_sane: tw pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+  }
+  return 1;
+}
+#endif /* TCP_DEBUG */
+
+#endif /* LWIP_TCP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/tcp_in.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/tcp_in.c
new file mode 100644
index 0000000..51e8775
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/tcp_in.c
@@ -0,0 +1,1506 @@
+/**
+ * @file
+ * Transmission Control Protocol, incoming traffic
+ *
+ * The input processing functions of the TCP layer.
+ *
+ * These functions are generally called in the order (ip_input() ->)
+ * tcp_input() -> * tcp_process() -> tcp_receive() (-> application).
+ * 
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/tcp.h"
+#include "lwip/def.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/inet.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+#include "arch/perf.h"
+
+/* These variables are global to all functions involved in the input
+   processing of TCP segments. They are set by the tcp_input()
+   function. */
+static struct tcp_seg inseg;
+static struct tcp_hdr *tcphdr;
+static struct ip_hdr *iphdr;
+static u32_t seqno, ackno;
+static u8_t flags;
+static u16_t tcplen;
+
+static u8_t recv_flags;
+static struct pbuf *recv_data;
+
+struct tcp_pcb *tcp_input_pcb;
+
+/* Forward declarations. */
+static err_t tcp_process(struct tcp_pcb *pcb);
+static void tcp_receive(struct tcp_pcb *pcb);
+static void tcp_parseopt(struct tcp_pcb *pcb);
+
+static err_t tcp_listen_input(struct tcp_pcb_listen *pcb);
+static err_t tcp_timewait_input(struct tcp_pcb *pcb);
+
+/**
+ * The initial input processing of TCP. It verifies the TCP header, demultiplexes
+ * the segment between the PCBs and passes it on to tcp_process(), which implements
+ * the TCP finite state machine. This function is called by the IP layer (in
+ * ip_input()).
+ *
+ * @param p received TCP segment to process (p->payload pointing to the IP header)
+ * @param inp network interface on which this segment was received
+ */
+void
+tcp_input(struct pbuf *p, struct netif *inp)
+{
+  struct tcp_pcb *pcb, *prev;
+  struct tcp_pcb_listen *lpcb;
+  u8_t hdrlen;
+  err_t err;
+
+  PERF_START;
+
+  TCP_STATS_INC(tcp.recv);
+  snmp_inc_tcpinsegs();
+
+  iphdr = p->payload;
+  tcphdr = (struct tcp_hdr *)((u8_t *)p->payload + IPH_HL(iphdr) * 4);
+
+#if TCP_INPUT_DEBUG
+  tcp_debug_print(tcphdr);
+#endif
+
+  /* remove header from payload */
+  if (pbuf_header(p, -((s16_t)(IPH_HL(iphdr) * 4))) || (p->tot_len < sizeof(struct tcp_hdr))) {
+    /* drop short packets */
+    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet (%"U16_F" bytes) discarded\n", p->tot_len));
+    TCP_STATS_INC(tcp.lenerr);
+    TCP_STATS_INC(tcp.drop);
+    snmp_inc_tcpinerrs();
+    pbuf_free(p);
+    return;
+  }
+
+  /* Don't even process incoming broadcasts/multicasts. */
+  if (ip_addr_isbroadcast(&(iphdr->dest), inp) ||
+      ip_addr_ismulticast(&(iphdr->dest))) {
+    TCP_STATS_INC(tcp.proterr);
+    TCP_STATS_INC(tcp.drop);
+    snmp_inc_tcpinerrs();
+    pbuf_free(p);
+    return;
+  }
+
+#if CHECKSUM_CHECK_TCP
+  /* Verify TCP checksum. */
+  if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
+      (struct ip_addr *)&(iphdr->dest),
+      IP_PROTO_TCP, p->tot_len) != 0) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packet discarded due to failing checksum 0x%04"X16_F"\n",
+        inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), (struct ip_addr *)&(iphdr->dest),
+      IP_PROTO_TCP, p->tot_len)));
+#if TCP_DEBUG
+    tcp_debug_print(tcphdr);
+#endif /* TCP_DEBUG */
+    TCP_STATS_INC(tcp.chkerr);
+    TCP_STATS_INC(tcp.drop);
+    snmp_inc_tcpinerrs();
+    pbuf_free(p);
+    return;
+  }
+#endif
+
+  /* Move the payload pointer in the pbuf so that it points to the
+     TCP data instead of the TCP header. */
+  hdrlen = TCPH_HDRLEN(tcphdr);
+  if(pbuf_header(p, -(hdrlen * 4))){
+    /* drop short packets */
+    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet\n"));
+    TCP_STATS_INC(tcp.lenerr);
+    TCP_STATS_INC(tcp.drop);
+    snmp_inc_tcpinerrs();
+    pbuf_free(p);
+    return;
+  }
+
+  /* Convert fields in TCP header to host byte order. */
+  tcphdr->src = ntohs(tcphdr->src);
+  tcphdr->dest = ntohs(tcphdr->dest);
+  seqno = tcphdr->seqno = ntohl(tcphdr->seqno);
+  ackno = tcphdr->ackno = ntohl(tcphdr->ackno);
+  tcphdr->wnd = ntohs(tcphdr->wnd);
+
+  flags = TCPH_FLAGS(tcphdr);
+  tcplen = p->tot_len + ((flags & (TCP_FIN | TCP_SYN)) ? 1 : 0);
+
+  /* Demultiplex an incoming segment. First, we check if it is destined
+     for an active connection. */
+  prev = NULL;
+
+  
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
+    LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN);
+    if (pcb->remote_port == tcphdr->src &&
+       pcb->local_port == tcphdr->dest &&
+       ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) &&
+       ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) {
+
+      /* Move this PCB to the front of the list so that subsequent
+         lookups will be faster (we exploit locality in TCP segment
+         arrivals). */
+      LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb);
+      if (prev != NULL) {
+        prev->next = pcb->next;
+        pcb->next = tcp_active_pcbs;
+        tcp_active_pcbs = pcb;
+      }
+      LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb);
+      break;
+    }
+    prev = pcb;
+  }
+
+  if (pcb == NULL) {
+    /* If it did not go to an active connection, we check the connections
+       in the TIME-WAIT state. */
+    for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+      LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+      if (pcb->remote_port == tcphdr->src &&
+         pcb->local_port == tcphdr->dest &&
+         ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) &&
+         ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) {
+        /* We don't really care enough to move this PCB to the front
+           of the list since we are not very likely to receive that
+           many segments for connections in TIME-WAIT. */
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for TIME_WAITing connection.\n"));
+        tcp_timewait_input(pcb);
+        pbuf_free(p);
+        return;
+      }
+    }
+
+  /* Finally, if we still did not get a match, we check all PCBs that
+     are LISTENing for incoming connections. */
+    prev = NULL;
+    for(lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+      if ((ip_addr_isany(&(lpcb->local_ip)) ||
+        ip_addr_cmp(&(lpcb->local_ip), &(iphdr->dest))) &&
+        lpcb->local_port == tcphdr->dest) {
+        /* Move this PCB to the front of the list so that subsequent
+           lookups will be faster (we exploit locality in TCP segment
+           arrivals). */
+        if (prev != NULL) {
+          ((struct tcp_pcb_listen *)prev)->next = lpcb->next;
+                /* our successor is the remainder of the listening list */
+          lpcb->next = tcp_listen_pcbs.listen_pcbs;
+                /* put this listening pcb at the head of the listening list */
+          tcp_listen_pcbs.listen_pcbs = lpcb;
+        }
+      
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for LISTENing connection.\n"));
+        tcp_listen_input(lpcb);
+        pbuf_free(p);
+        return;
+      }
+      prev = (struct tcp_pcb *)lpcb;
+    }
+  }
+
+#if TCP_INPUT_DEBUG
+  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("+-+-+-+-+-+-+-+-+-+-+-+-+-+- tcp_input: flags "));
+  tcp_debug_print_flags(TCPH_FLAGS(tcphdr));
+  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n"));
+#endif /* TCP_INPUT_DEBUG */
+
+
+  if (pcb != NULL) {
+    /* The incoming segment belongs to a connection. */
+#if TCP_INPUT_DEBUG
+#if TCP_DEBUG
+    tcp_debug_print_state(pcb->state);
+#endif /* TCP_DEBUG */
+#endif /* TCP_INPUT_DEBUG */
+
+    /* Set up a tcp_seg structure. */
+    inseg.next = NULL;
+    inseg.len = p->tot_len;
+    inseg.dataptr = p->payload;
+    inseg.p = p;
+    inseg.tcphdr = tcphdr;
+
+    recv_data = NULL;
+    recv_flags = 0;
+
+    /* If there is data which was previously "refused" by upper layer */
+    if (pcb->refused_data != NULL) {
+      /* Notify again application with data previously received. */
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: notify kept packet\n"));
+      TCP_EVENT_RECV(pcb, pcb->refused_data, ERR_OK, err);
+      if (err == ERR_OK) {
+        pcb->refused_data = NULL;
+      } else {
+        /* drop incoming packets, because pcb is "full" */
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: drop incoming packets, because pcb is \"full\"\n"));
+        TCP_STATS_INC(tcp.drop);
+        snmp_inc_tcpinerrs();
+        pbuf_free(p);
+        return;
+      }
+    }
+    tcp_input_pcb = pcb;
+    err = tcp_process(pcb);
+    /* A return value of ERR_ABRT means that tcp_abort() was called
+       and that the pcb has been freed. If so, we don't do anything. */
+    if (err != ERR_ABRT) {
+      if (recv_flags & TF_RESET) {
+        /* TF_RESET means that the connection was reset by the other
+           end. We then call the error callback to inform the
+           application that the connection is dead before we
+           deallocate the PCB. */
+        TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_RST);
+        tcp_pcb_remove(&tcp_active_pcbs, pcb);
+        memp_free(MEMP_TCP_PCB, pcb);
+      } else if (recv_flags & TF_CLOSED) {
+        /* The connection has been closed and we will deallocate the
+           PCB. */
+        tcp_pcb_remove(&tcp_active_pcbs, pcb);
+        memp_free(MEMP_TCP_PCB, pcb);
+      } else {
+        err = ERR_OK;
+        /* If the application has registered a "sent" function to be
+           called when new send buffer space is available, we call it
+           now. */
+        if (pcb->acked > 0) {
+          TCP_EVENT_SENT(pcb, pcb->acked, err);
+        }
+      
+        if (recv_data != NULL) {
+          if(flags & TCP_PSH) {
+            recv_data->flags |= PBUF_FLAG_PUSH;
+          }
+
+          /* Notify application that data has been received. */
+          TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err);
+
+          /* If the upper layer can't receive this data, store it */
+          if (err != ERR_OK) {
+            pcb->refused_data = recv_data;
+            LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: keep incoming packet, because pcb is \"full\"\n"));
+          }
+        }
+
+        /* If a FIN segment was received, we call the callback
+           function with a NULL buffer to indicate EOF. */
+        if (recv_flags & TF_GOT_FIN) {
+          TCP_EVENT_RECV(pcb, NULL, ERR_OK, err);
+        }
+
+        tcp_input_pcb = NULL;
+        /* Try to send something out. */
+        tcp_output(pcb);
+#if TCP_INPUT_DEBUG
+#if TCP_DEBUG
+        tcp_debug_print_state(pcb->state);
+#endif /* TCP_DEBUG */
+#endif /* TCP_INPUT_DEBUG */
+      }
+    }
+    tcp_input_pcb = NULL;
+
+
+    /* give up our reference to inseg.p */
+    if (inseg.p != NULL)
+    {
+      pbuf_free(inseg.p);
+      inseg.p = NULL;
+    }
+  } else {
+
+    /* If no matching PCB was found, send a TCP RST (reset) to the
+       sender. */
+    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_input: no PCB match found, resetting.\n"));
+    if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) {
+      TCP_STATS_INC(tcp.proterr);
+      TCP_STATS_INC(tcp.drop);
+      tcp_rst(ackno, seqno + tcplen,
+        &(iphdr->dest), &(iphdr->src),
+        tcphdr->dest, tcphdr->src);
+    }
+    pbuf_free(p);
+  }
+
+  LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane());
+  PERF_STOP("tcp_input");
+}
+
+/**
+ * Called by tcp_input() when a segment arrives for a listening
+ * connection (from tcp_input()).
+ *
+ * @param pcb the tcp_pcb_listen for which a segment arrived
+ * @return ERR_OK if the segment was processed
+ *         another err_t on error
+ *
+ * @note the return value is not (yet?) used in tcp_input()
+ * @note the segment which arrived is saved in global variables, therefore only the pcb
+ *       involved is passed as a parameter to this function
+ */
+static err_t
+tcp_listen_input(struct tcp_pcb_listen *pcb)
+{
+  struct tcp_pcb *npcb;
+  err_t rc;
+
+  /* In the LISTEN state, we check for incoming SYN segments,
+     creates a new PCB, and responds with a SYN|ACK. */
+  if (flags & TCP_ACK) {
+    /* For incoming segments with the ACK flag set, respond with a
+       RST. */
+    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n"));
+    tcp_rst(ackno + 1, seqno + tcplen,
+      &(iphdr->dest), &(iphdr->src),
+      tcphdr->dest, tcphdr->src);
+  } else if (flags & TCP_SYN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("TCP connection request %"U16_F" -> %"U16_F".\n", tcphdr->src, tcphdr->dest));
+#if TCP_LISTEN_BACKLOG
+    if (pcb->accepts_pending >= pcb->backlog) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: listen backlog exceeded for port %"U16_F"\n", tcphdr->dest));
+      return ERR_ABRT;
+    }
+#endif /* TCP_LISTEN_BACKLOG */
+    npcb = tcp_alloc(pcb->prio);
+    /* If a new PCB could not be created (probably due to lack of memory),
+       we don't do anything, but rely on the sender will retransmit the
+       SYN at a time when we have more memory available. */
+    if (npcb == NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: could not allocate PCB\n"));
+      TCP_STATS_INC(tcp.memerr);
+      return ERR_MEM;
+    }
+#if TCP_LISTEN_BACKLOG
+    pcb->accepts_pending++;
+#endif /* TCP_LISTEN_BACKLOG */
+    /* Set up the new PCB. */
+    ip_addr_set(&(npcb->local_ip), &(iphdr->dest));
+    npcb->local_port = pcb->local_port;
+    ip_addr_set(&(npcb->remote_ip), &(iphdr->src));
+    npcb->remote_port = tcphdr->src;
+    npcb->state = SYN_RCVD;
+    npcb->rcv_nxt = seqno + 1;
+    npcb->rcv_ann_right_edge = npcb->rcv_nxt;
+    npcb->snd_wnd = tcphdr->wnd;
+    npcb->ssthresh = npcb->snd_wnd;
+    npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */
+    npcb->callback_arg = pcb->callback_arg;
+#if LWIP_CALLBACK_API
+    npcb->accept = pcb->accept;
+#endif /* LWIP_CALLBACK_API */
+    /* inherit socket options */
+    npcb->so_options = pcb->so_options & (SOF_DEBUG|SOF_DONTROUTE|SOF_KEEPALIVE|SOF_OOBINLINE|SOF_LINGER);
+    /* Register the new PCB so that we can begin receiving segments
+       for it. */
+    TCP_REG(&tcp_active_pcbs, npcb);
+
+    /* Parse any options in the SYN. */
+    tcp_parseopt(npcb);
+#if TCP_CALCULATE_EFF_SEND_MSS
+    npcb->mss = tcp_eff_send_mss(npcb->mss, &(npcb->remote_ip));
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+
+    snmp_inc_tcppassiveopens();
+
+    /* Send a SYN|ACK together with the MSS option. */
+    rc = tcp_enqueue(npcb, NULL, 0, TCP_SYN | TCP_ACK, 0, TF_SEG_OPTS_MSS
+#if LWIP_TCP_TIMESTAMPS
+      /* and maybe include the TIMESTAMP option */
+     | (npcb->flags & TF_TIMESTAMP ? TF_SEG_OPTS_TS : 0)
+#endif
+      );
+    if (rc != ERR_OK) {
+      tcp_abandon(npcb, 0);
+      return rc;
+    }
+    return tcp_output(npcb);
+  }
+  return ERR_OK;
+}
+
+/**
+ * Called by tcp_input() when a segment arrives for a connection in
+ * TIME_WAIT.
+ *
+ * @param pcb the tcp_pcb for which a segment arrived
+ *
+ * @note the segment which arrived is saved in global variables, therefore only the pcb
+ *       involved is passed as a parameter to this function
+ */
+static err_t
+tcp_timewait_input(struct tcp_pcb *pcb)
+{
+  /* RFC 1337: in TIME_WAIT, ignore RST and ACK FINs + any 'acceptable' segments */
+  /* RFC 793 3.9 Event Processing - Segment Arrives:
+   * - first check sequence number - we skip that one in TIME_WAIT (always
+   *   acceptable since we only send ACKs)
+   * - second check the RST bit (... return) */
+  if (flags & TCP_RST)  {
+    return ERR_OK;
+  }
+  /* - fourth, check the SYN bit, */
+  if (flags & TCP_SYN) {
+    /* If an incoming segment is not acceptable, an acknowledgment
+       should be sent in reply */
+    if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt+pcb->rcv_wnd)) {
+      /* If the SYN is in the window it is an error, send a reset */
+      tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src),
+        tcphdr->dest, tcphdr->src);
+      return ERR_OK;
+    }
+  } else if (flags & TCP_FIN) {
+    /* - eighth, check the FIN bit: Remain in the TIME-WAIT state.
+         Restart the 2 MSL time-wait timeout.*/
+    pcb->tmr = tcp_ticks;
+  }
+
+  if ((tcplen > 0))  {
+    /* Acknowledge data, FIN or out-of-window SYN */
+    pcb->flags |= TF_ACK_NOW;
+    return tcp_output(pcb);
+  }
+  return ERR_OK;
+}
+
+/**
+ * Implements the TCP state machine. Called by tcp_input. In some
+ * states tcp_receive() is called to receive data. The tcp_seg
+ * argument will be freed by the caller (tcp_input()) unless the
+ * recv_data pointer in the pcb is set.
+ *
+ * @param pcb the tcp_pcb for which a segment arrived
+ *
+ * @note the segment which arrived is saved in global variables, therefore only the pcb
+ *       involved is passed as a parameter to this function
+ */
+static err_t
+tcp_process(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *rseg;
+  u8_t acceptable = 0;
+  err_t err;
+
+  err = ERR_OK;
+
+  /* Process incoming RST segments. */
+  if (flags & TCP_RST) {
+    /* First, determine if the reset is acceptable. */
+    if (pcb->state == SYN_SENT) {
+      if (ackno == pcb->snd_nxt) {
+        acceptable = 1;
+      }
+    } else {
+      if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, 
+                          pcb->rcv_nxt+pcb->rcv_wnd)) {
+        acceptable = 1;
+      }
+    }
+
+    if (acceptable) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n"));
+      LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED);
+      recv_flags |= TF_RESET;
+      pcb->flags &= ~TF_ACK_DELAY;
+      return ERR_RST;
+    } else {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
+       seqno, pcb->rcv_nxt));
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
+       seqno, pcb->rcv_nxt));
+      return ERR_OK;
+    }
+  }
+
+  if ((flags & TCP_SYN) && (pcb->state != SYN_SENT && pcb->state != SYN_RCVD)) { 
+    /* Cope with new connection attempt after remote end crashed */
+    tcp_ack_now(pcb);
+    return ERR_OK;
+  }
+  
+  /* Update the PCB (in)activity timer. */
+  pcb->tmr = tcp_ticks;
+  pcb->keep_cnt_sent = 0;
+
+  tcp_parseopt(pcb);
+
+  /* Do different things depending on the TCP state. */
+  switch (pcb->state) {
+  case SYN_SENT:
+    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno,
+     pcb->snd_nxt, ntohl(pcb->unacked->tcphdr->seqno)));
+    /* received SYN ACK with expected sequence number? */
+    if ((flags & TCP_ACK) && (flags & TCP_SYN)
+        && ackno == ntohl(pcb->unacked->tcphdr->seqno) + 1) {
+      pcb->snd_buf++;
+      pcb->rcv_nxt = seqno + 1;
+      pcb->rcv_ann_right_edge = pcb->rcv_nxt;
+      pcb->lastack = ackno;
+      pcb->snd_wnd = tcphdr->wnd;
+      pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */
+      pcb->state = ESTABLISHED;
+
+#if TCP_CALCULATE_EFF_SEND_MSS
+      pcb->mss = tcp_eff_send_mss(pcb->mss, &(pcb->remote_ip));
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+
+      /* Set ssthresh again after changing pcb->mss (already set in tcp_connect
+       * but for the default value of pcb->mss) */
+      pcb->ssthresh = pcb->mss * 10;
+
+      pcb->cwnd = ((pcb->cwnd == 1) ? (pcb->mss * 2) : pcb->mss);
+      LWIP_ASSERT("pcb->snd_queuelen > 0", (pcb->snd_queuelen > 0));
+      --pcb->snd_queuelen;
+      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"U16_F"\n", (u16_t)pcb->snd_queuelen));
+      rseg = pcb->unacked;
+      pcb->unacked = rseg->next;
+
+      /* If there's nothing left to acknowledge, stop the retransmit
+         timer, otherwise reset it to start again */
+      if(pcb->unacked == NULL)
+        pcb->rtime = -1;
+      else {
+        pcb->rtime = 0;
+        pcb->nrtx = 0;
+      }
+
+      tcp_seg_free(rseg);
+
+      /* Call the user specified function to call when sucessfully
+       * connected. */
+      TCP_EVENT_CONNECTED(pcb, ERR_OK, err);
+      tcp_ack_now(pcb);
+    }
+    /* received ACK? possibly a half-open connection */
+    else if (flags & TCP_ACK) {
+      /* send a RST to bring the other side in a non-synchronized state. */
+      tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src),
+        tcphdr->dest, tcphdr->src);
+    }
+    break;
+  case SYN_RCVD:
+    if (flags & TCP_ACK) {
+      /* expected ACK number? */
+      if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)) {
+        u16_t old_cwnd;
+        pcb->state = ESTABLISHED;
+        LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+#if LWIP_CALLBACK_API
+        LWIP_ASSERT("pcb->accept != NULL", pcb->accept != NULL);
+#endif
+        /* Call the accept function. */
+        TCP_EVENT_ACCEPT(pcb, ERR_OK, err);
+        if (err != ERR_OK) {
+          /* If the accept function returns with an error, we abort
+           * the connection. */
+          tcp_abort(pcb);
+          return ERR_ABRT;
+        }
+        old_cwnd = pcb->cwnd;
+        /* If there was any data contained within this ACK,
+         * we'd better pass it on to the application as well. */
+        tcp_receive(pcb);
+
+        /* Prevent ACK for SYN to generate a sent event */
+        if (pcb->acked != 0) {
+          pcb->acked--;
+        }
+
+        pcb->cwnd = ((old_cwnd == 1) ? (pcb->mss * 2) : pcb->mss);
+
+        if (recv_flags & TF_GOT_FIN) {
+          tcp_ack_now(pcb);
+          pcb->state = CLOSE_WAIT;
+        }
+      }
+      /* incorrect ACK number */
+      else {
+        /* send RST */
+        tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src),
+                tcphdr->dest, tcphdr->src);
+      }
+    } else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) {
+      /* Looks like another copy of the SYN - retransmit our SYN-ACK */
+      tcp_rexmit(pcb);
+    }
+    break;
+  case CLOSE_WAIT:
+    /* FALLTHROUGH */
+  case ESTABLISHED:
+    tcp_receive(pcb);
+    if (recv_flags & TF_GOT_FIN) { /* passive close */
+      tcp_ack_now(pcb);
+      pcb->state = CLOSE_WAIT;
+    }
+    break;
+  case FIN_WAIT_1:
+    tcp_receive(pcb);
+    if (recv_flags & TF_GOT_FIN) {
+      if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt)) {
+        LWIP_DEBUGF(TCP_DEBUG,
+          ("TCP connection closed: FIN_WAIT_1 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+        tcp_ack_now(pcb);
+        tcp_pcb_purge(pcb);
+        TCP_RMV(&tcp_active_pcbs, pcb);
+        pcb->state = TIME_WAIT;
+        TCP_REG(&tcp_tw_pcbs, pcb);
+      } else {
+        tcp_ack_now(pcb);
+        pcb->state = CLOSING;
+      }
+    } else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt)) {
+      pcb->state = FIN_WAIT_2;
+    }
+    break;
+  case FIN_WAIT_2:
+    tcp_receive(pcb);
+    if (recv_flags & TF_GOT_FIN) {
+      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: FIN_WAIT_2 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+      tcp_ack_now(pcb);
+      tcp_pcb_purge(pcb);
+      TCP_RMV(&tcp_active_pcbs, pcb);
+      pcb->state = TIME_WAIT;
+      TCP_REG(&tcp_tw_pcbs, pcb);
+    }
+    break;
+  case CLOSING:
+    tcp_receive(pcb);
+    if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: CLOSING %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+      tcp_pcb_purge(pcb);
+      TCP_RMV(&tcp_active_pcbs, pcb);
+      pcb->state = TIME_WAIT;
+      TCP_REG(&tcp_tw_pcbs, pcb);
+    }
+    break;
+  case LAST_ACK:
+    tcp_receive(pcb);
+    if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: LAST_ACK %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+      /* bugfix #21699: don't set pcb->state to CLOSED here or we risk leaking segments */
+      recv_flags |= TF_CLOSED;
+    }
+    break;
+  default:
+    break;
+  }
+  return ERR_OK;
+}
+
+#if TCP_QUEUE_OOSEQ
+/**
+ * Insert segment into the list (segments covered with new one will be deleted)
+ *
+ * Called from tcp_receive()
+ */
+static void
+tcp_oos_insert_segment(struct tcp_seg *cseg, struct tcp_seg *next)
+{
+  struct tcp_seg *old_seg;
+
+  if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
+    /* received segment overlaps all following segments */
+    tcp_segs_free(next);
+    next = NULL;
+  }
+  else {
+    /* delete some following segments
+       oos queue may have segments with FIN flag */
+    while (next &&
+           TCP_SEQ_GEQ((seqno + cseg->len),
+                      (next->tcphdr->seqno + next->len))) {
+      /* cseg with FIN already processed */
+      if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) {
+        TCPH_FLAGS_SET(cseg->tcphdr, TCPH_FLAGS(cseg->tcphdr) | TCP_FIN);
+      }
+      old_seg = next;
+      next = next->next;
+      tcp_seg_free(old_seg);
+    }
+    if (next &&
+        TCP_SEQ_GT(seqno + cseg->len, next->tcphdr->seqno)) {
+      /* We need to trim the incoming segment. */
+      cseg->len = (u16_t)(next->tcphdr->seqno - seqno);
+      pbuf_realloc(cseg->p, cseg->len);
+    }
+  }
+  cseg->next = next;
+}
+#endif
+
+/**
+ * Called by tcp_process. Checks if the given segment is an ACK for outstanding
+ * data, and if so frees the memory of the buffered data. Next, is places the
+ * segment on any of the receive queues (pcb->recved or pcb->ooseq). If the segment
+ * is buffered, the pbuf is referenced by pbuf_ref so that it will not be freed until
+ * i it has been removed from the buffer.
+ *
+ * If the incoming segment constitutes an ACK for a segment that was used for RTT
+ * estimation, the RTT is estimated here as well.
+ *
+ * Called from tcp_process().
+ */
+static void
+tcp_receive(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *next;
+#if TCP_QUEUE_OOSEQ
+  struct tcp_seg *prev, *cseg;
+#endif
+  struct pbuf *p;
+  s32_t off;
+  s16_t m;
+  u32_t right_wnd_edge;
+  u16_t new_tot_len;
+  int found_dupack = 0;
+
+  if (flags & TCP_ACK) {
+    right_wnd_edge = pcb->snd_wnd + pcb->snd_wl2;
+
+    /* Update window. */
+    if (TCP_SEQ_LT(pcb->snd_wl1, seqno) ||
+       (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
+       (pcb->snd_wl2 == ackno && tcphdr->wnd > pcb->snd_wnd)) {
+      pcb->snd_wnd = tcphdr->wnd;
+      pcb->snd_wl1 = seqno;
+      pcb->snd_wl2 = ackno;
+      if (pcb->snd_wnd > 0 && pcb->persist_backoff > 0) {
+          pcb->persist_backoff = 0;
+      }
+      LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: window update %"U16_F"\n", pcb->snd_wnd));
+#if TCP_WND_DEBUG
+    } else {
+      if (pcb->snd_wnd != tcphdr->wnd) {
+        LWIP_DEBUGF(TCP_WND_DEBUG, 
+                    ("tcp_receive: no window update lastack %"U32_F" ackno %"
+                     U32_F" wl1 %"U32_F" seqno %"U32_F" wl2 %"U32_F"\n",
+                     pcb->lastack, ackno, pcb->snd_wl1, seqno, pcb->snd_wl2));
+      }
+#endif /* TCP_WND_DEBUG */
+    }
+
+    /* (From Stevens TCP/IP Illustrated Vol II, p970.) Its only a
+     * duplicate ack if:
+     * 1) It doesn't ACK new data 
+     * 2) length of received packet is zero (i.e. no payload) 
+     * 3) the advertised window hasn't changed 
+     * 4) There is outstanding unacknowledged data (retransmission timer running)
+     * 5) The ACK is == biggest ACK sequence number so far seen (snd_una)
+     * 
+     * If it passes all five, should process as a dupack: 
+     * a) dupacks < 3: do nothing 
+     * b) dupacks == 3: fast retransmit 
+     * c) dupacks > 3: increase cwnd 
+     * 
+     * If it only passes 1-3, should reset dupack counter (and add to
+     * stats, which we don't do in lwIP)
+     *
+     * If it only passes 1, should reset dupack counter
+     *
+     */
+
+    /* Clause 1 */
+    if (TCP_SEQ_LEQ(ackno, pcb->lastack)) {
+      pcb->acked = 0;
+      /* Clause 2 */
+      if (tcplen == 0) {
+        /* Clause 3 */
+        if (pcb->snd_wl2 + pcb->snd_wnd == right_wnd_edge){
+          /* Clause 4 */
+          if (pcb->rtime >= 0) {
+            /* Clause 5 */
+            if (pcb->lastack == ackno) {
+              found_dupack = 1;
+              if (pcb->dupacks + 1 > pcb->dupacks)
+                ++pcb->dupacks;
+              if (pcb->dupacks > 3) {
+                /* Inflate the congestion window, but not if it means that
+                   the value overflows. */
+                if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) {
+                  pcb->cwnd += pcb->mss;
+                }
+              } else if (pcb->dupacks == 3) {
+                /* Do fast retransmit */
+                tcp_rexmit_fast(pcb);
+              }
+            }
+          }
+        }
+      }
+      /* If Clause (1) or more is true, but not a duplicate ack, reset
+       * count of consecutive duplicate acks */
+      if (!found_dupack) {
+        pcb->dupacks = 0;
+      }
+    } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)){
+      /* We come here when the ACK acknowledges new data. */
+
+      /* Reset the "IN Fast Retransmit" flag, since we are no longer
+         in fast retransmit. Also reset the congestion window to the
+         slow start threshold. */
+      if (pcb->flags & TF_INFR) {
+        pcb->flags &= ~TF_INFR;
+        pcb->cwnd = pcb->ssthresh;
+      }
+
+      /* Reset the number of retransmissions. */
+      pcb->nrtx = 0;
+
+      /* Reset the retransmission time-out. */
+      pcb->rto = (pcb->sa >> 3) + pcb->sv;
+
+      /* Update the send buffer space. Diff between the two can never exceed 64K? */
+      pcb->acked = (u16_t)(ackno - pcb->lastack);
+
+      pcb->snd_buf += pcb->acked;
+
+      /* Reset the fast retransmit variables. */
+      pcb->dupacks = 0;
+      pcb->lastack = ackno;
+
+      /* Update the congestion control variables (cwnd and
+         ssthresh). */
+      if (pcb->state >= ESTABLISHED) {
+        if (pcb->cwnd < pcb->ssthresh) {
+          if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) {
+            pcb->cwnd += pcb->mss;
+          }
+          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"U16_F"\n", pcb->cwnd));
+        } else {
+          u16_t new_cwnd = (pcb->cwnd + pcb->mss * pcb->mss / pcb->cwnd);
+          if (new_cwnd > pcb->cwnd) {
+            pcb->cwnd = new_cwnd;
+          }
+          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: congestion avoidance cwnd %"U16_F"\n", pcb->cwnd));
+        }
+      }
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: ACK for %"U32_F", unacked->seqno %"U32_F":%"U32_F"\n",
+                                    ackno,
+                                    pcb->unacked != NULL?
+                                    ntohl(pcb->unacked->tcphdr->seqno): 0,
+                                    pcb->unacked != NULL?
+                                    ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked): 0));
+
+      /* Remove segment from the unacknowledged list if the incoming
+         ACK acknowlegdes them. */
+      while (pcb->unacked != NULL &&
+             TCP_SEQ_LEQ(ntohl(pcb->unacked->tcphdr->seqno) +
+                         TCP_TCPLEN(pcb->unacked), ackno)) {
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unacked\n",
+                                      ntohl(pcb->unacked->tcphdr->seqno),
+                                      ntohl(pcb->unacked->tcphdr->seqno) +
+                                      TCP_TCPLEN(pcb->unacked)));
+
+        next = pcb->unacked;
+        pcb->unacked = pcb->unacked->next;
+
+        LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen));
+        LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= pbuf_clen(next->p)));
+        /* Prevent ACK for FIN to generate a sent event */
+        if ((pcb->acked != 0) && ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0)) {
+          pcb->acked--;
+        }
+
+        pcb->snd_queuelen -= pbuf_clen(next->p);
+        tcp_seg_free(next);
+
+        LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unacked)\n", (u16_t)pcb->snd_queuelen));
+        if (pcb->snd_queuelen != 0) {
+          LWIP_ASSERT("tcp_receive: valid queue length", pcb->unacked != NULL ||
+                      pcb->unsent != NULL);
+        }
+      }
+
+      /* If there's nothing left to acknowledge, stop the retransmit
+         timer, otherwise reset it to start again */
+      if(pcb->unacked == NULL)
+        pcb->rtime = -1;
+      else
+        pcb->rtime = 0;
+
+      pcb->polltmr = 0;
+    } else {
+      /* Fix bug bug #21582: out of sequence ACK, didn't really ack anything */
+      pcb->acked = 0;
+    }
+
+    /* We go through the ->unsent list to see if any of the segments
+       on the list are acknowledged by the ACK. This may seem
+       strange since an "unsent" segment shouldn't be acked. The
+       rationale is that lwIP puts all outstanding segments on the
+       ->unsent list after a retransmission, so these segments may
+       in fact have been sent once. */
+    while (pcb->unsent != NULL &&
+           TCP_SEQ_BETWEEN(ackno, ntohl(pcb->unsent->tcphdr->seqno) + 
+                           TCP_TCPLEN(pcb->unsent), pcb->snd_nxt)) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unsent\n",
+                                    ntohl(pcb->unsent->tcphdr->seqno), ntohl(pcb->unsent->tcphdr->seqno) +
+                                    TCP_TCPLEN(pcb->unsent)));
+
+      next = pcb->unsent;
+      pcb->unsent = pcb->unsent->next;
+      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen));
+      LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= pbuf_clen(next->p)));
+      /* Prevent ACK for FIN to generate a sent event */
+      if ((pcb->acked != 0) && ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0)) {
+        pcb->acked--;
+      }
+      pcb->snd_queuelen -= pbuf_clen(next->p);
+      tcp_seg_free(next);
+      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unsent)\n", (u16_t)pcb->snd_queuelen));
+      if (pcb->snd_queuelen != 0) {
+        LWIP_ASSERT("tcp_receive: valid queue length",
+          pcb->unacked != NULL || pcb->unsent != NULL);
+      }
+    }
+    /* End of ACK for new data processing. */
+
+    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: pcb->rttest %"U32_F" rtseq %"U32_F" ackno %"U32_F"\n",
+                                pcb->rttest, pcb->rtseq, ackno));
+
+    /* RTT estimation calculations. This is done by checking if the
+       incoming segment acknowledges the segment we use to take a
+       round-trip time measurement. */
+    if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) {
+      /* diff between this shouldn't exceed 32K since this are tcp timer ticks
+         and a round-trip shouldn't be that long... */
+      m = (s16_t)(tcp_ticks - pcb->rttest);
+
+      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n",
+                                  m, m * TCP_SLOW_INTERVAL));
+
+      /* This is taken directly from VJs original code in his paper */
+      m = m - (pcb->sa >> 3);
+      pcb->sa += m;
+      if (m < 0) {
+        m = -m;
+      }
+      m = m - (pcb->sv >> 2);
+      pcb->sv += m;
+      pcb->rto = (pcb->sa >> 3) + pcb->sv;
+
+      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" milliseconds)\n",
+                                  pcb->rto, pcb->rto * TCP_SLOW_INTERVAL));
+
+      pcb->rttest = 0;
+    }
+  }
+
+  /* If the incoming segment contains data, we must process it
+     further. */
+  if (tcplen > 0) {
+    /* This code basically does three things:
+
+    +) If the incoming segment contains data that is the next
+    in-sequence data, this data is passed to the application. This
+    might involve trimming the first edge of the data. The rcv_nxt
+    variable and the advertised window are adjusted.
+
+    +) If the incoming segment has data that is above the next
+    sequence number expected (->rcv_nxt), the segment is placed on
+    the ->ooseq queue. This is done by finding the appropriate
+    place in the ->ooseq queue (which is ordered by sequence
+    number) and trim the segment in both ends if needed. An
+    immediate ACK is sent to indicate that we received an
+    out-of-sequence segment.
+
+    +) Finally, we check if the first segment on the ->ooseq queue
+    now is in sequence (i.e., if rcv_nxt >= ooseq->seqno). If
+    rcv_nxt > ooseq->seqno, we must trim the first edge of the
+    segment on ->ooseq before we adjust rcv_nxt. The data in the
+    segments that are now on sequence are chained onto the
+    incoming segment so that we only need to call the application
+    once.
+    */
+
+    /* First, we check if we must trim the first edge. We have to do
+       this if the sequence number of the incoming segment is less
+       than rcv_nxt, and the sequence number plus the length of the
+       segment is larger than rcv_nxt. */
+    /*    if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){
+          if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/
+    if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)){
+      /* Trimming the first edge is done by pushing the payload
+         pointer in the pbuf downwards. This is somewhat tricky since
+         we do not want to discard the full contents of the pbuf up to
+         the new starting point of the data since we have to keep the
+         TCP header which is present in the first pbuf in the chain.
+
+         What is done is really quite a nasty hack: the first pbuf in
+         the pbuf chain is pointed to by inseg.p. Since we need to be
+         able to deallocate the whole pbuf, we cannot change this
+         inseg.p pointer to point to any of the later pbufs in the
+         chain. Instead, we point the ->payload pointer in the first
+         pbuf to data in one of the later pbufs. We also set the
+         inseg.data pointer to point to the right place. This way, the
+         ->p pointer will still point to the first pbuf, but the
+         ->p->payload pointer will point to data in another pbuf.
+
+         After we are done with adjusting the pbuf pointers we must
+         adjust the ->data pointer in the seg and the segment
+         length.*/
+
+      off = pcb->rcv_nxt - seqno;
+      p = inseg.p;
+      LWIP_ASSERT("inseg.p != NULL", inseg.p);
+      LWIP_ASSERT("insane offset!", (off < 0x7fff));
+      if (inseg.p->len < off) {
+        LWIP_ASSERT("pbuf too short!", (((s32_t)inseg.p->tot_len) >= off));
+        new_tot_len = (u16_t)(inseg.p->tot_len - off);
+        while (p->len < off) {
+          off -= p->len;
+          /* KJM following line changed (with addition of new_tot_len var)
+             to fix bug #9076
+             inseg.p->tot_len -= p->len; */
+          p->tot_len = new_tot_len;
+          p->len = 0;
+          p = p->next;
+        }
+        if(pbuf_header(p, (s16_t)-off)) {
+          /* Do we need to cope with this failing?  Assert for now */
+          LWIP_ASSERT("pbuf_header failed", 0);
+        }
+      } else {
+        if(pbuf_header(inseg.p, (s16_t)-off)) {
+          /* Do we need to cope with this failing?  Assert for now */
+          LWIP_ASSERT("pbuf_header failed", 0);
+        }
+      }
+      /* KJM following line changed to use p->payload rather than inseg->p->payload
+         to fix bug #9076 */
+      inseg.dataptr = p->payload;
+      inseg.len -= (u16_t)(pcb->rcv_nxt - seqno);
+      inseg.tcphdr->seqno = seqno = pcb->rcv_nxt;
+    }
+    else {
+      if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){
+        /* the whole segment is < rcv_nxt */
+        /* must be a duplicate of a packet that has already been correctly handled */
+
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno));
+        tcp_ack_now(pcb);
+      }
+    }
+
+    /* The sequence number must be within the window (above rcv_nxt
+       and below rcv_nxt + rcv_wnd) in order to be further
+       processed. */
+    if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, 
+                        pcb->rcv_nxt + pcb->rcv_wnd - 1)){
+      if (pcb->rcv_nxt == seqno) {
+        /* The incoming segment is the next in sequence. We check if
+           we have to trim the end of the segment and update rcv_nxt
+           and pass the data to the application. */
+        tcplen = TCP_TCPLEN(&inseg);
+
+        if (tcplen > pcb->rcv_wnd) {
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, 
+                      ("tcp_receive: other end overran receive window"
+                       "seqno %"U32_F" len %"U32_F" right edge %"U32_F"\n",
+                       seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd));
+          if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
+            /* Must remove the FIN from the header as we're trimming 
+             * that byte of sequence-space from the packet */
+            TCPH_FLAGS_SET(inseg.tcphdr, TCPH_FLAGS(inseg.tcphdr) &~ TCP_FIN);
+          }
+          /* Adjust length of segment to fit in the window. */
+          inseg.len = pcb->rcv_wnd;
+          if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) {
+            inseg.len -= 1;
+          }
+          pbuf_realloc(inseg.p, inseg.len);
+          tcplen = TCP_TCPLEN(&inseg);
+          LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n",
+                      (seqno + tcplen) == (pcb->rcv_nxt + pcb->rcv_wnd));
+        }
+#if TCP_QUEUE_OOSEQ
+        if (pcb->ooseq != NULL) {
+          if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
+            LWIP_DEBUGF(TCP_INPUT_DEBUG, 
+                        ("tcp_receive: received in-order FIN, binning ooseq queue\n"));
+            /* Received in-order FIN means anything that was received
+             * out of order must now have been received in-order, so
+             * bin the ooseq queue
+             * rcv_nxt
+             * .    |--ooseq--|
+             * .==seg============|FIN
+             */
+            while (pcb->ooseq != NULL) {
+              struct tcp_seg *old_ooseq = pcb->ooseq;
+              pcb->ooseq = pcb->ooseq->next;
+              tcp_seg_free(old_ooseq);
+            }               
+          } 
+          else {
+            struct tcp_seg* next = pcb->ooseq;
+            struct tcp_seg *old_seg;
+            /* rcv_nxt
+             * .    |--ooseq--|
+             * .==seg============|
+             */
+            while (next &&
+                   TCP_SEQ_GEQ(seqno + tcplen,
+                               next->tcphdr->seqno + next->len)) {
+              /* inseg doesn't have FIN (already processed) */
+              if (TCPH_FLAGS(next->tcphdr) & TCP_FIN &&
+                  (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) == 0) {
+                TCPH_FLAGS_SET(inseg.tcphdr, 
+                               TCPH_FLAGS(inseg.tcphdr) | TCP_FIN);
+                tcplen = TCP_TCPLEN(&inseg);
+              }
+              old_seg = next;
+              next = next->next;
+              tcp_seg_free(old_seg);
+            }
+            /* rcv_nxt
+             * .             |--ooseq--|
+             * .==seg============|
+             */
+            if (next &&
+                TCP_SEQ_GT(seqno + tcplen,
+                           next->tcphdr->seqno)) {
+              /* FIN in inseg already handled by dropping whole ooseq queue */
+              inseg.len = (u16_t)(pcb->ooseq->tcphdr->seqno - seqno);
+              if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) {
+                inseg.len -= 1;
+              }
+              pbuf_realloc(inseg.p, inseg.len);
+              tcplen = TCP_TCPLEN(&inseg);
+              LWIP_ASSERT("tcp_receive: segment not trimmed correctly to ooseq queue\n",
+                          (seqno + tcplen) == pcb->ooseq->tcphdr->seqno);
+            }
+            pcb->ooseq = next;
+          }
+        }
+#endif /* TCP_QUEUE_OOSEQ */
+
+        pcb->rcv_nxt = seqno + tcplen;
+
+        /* Update the receiver's (our) window. */
+        LWIP_ASSERT("tcp_receive: tcplen > rcv_wnd\n", pcb->rcv_wnd >= tcplen);
+        pcb->rcv_wnd -= tcplen;
+
+        tcp_update_rcv_ann_wnd(pcb);
+
+        /* If there is data in the segment, we make preparations to
+           pass this up to the application. The ->recv_data variable
+           is used for holding the pbuf that goes to the
+           application. The code for reassembling out-of-sequence data
+           chains its data on this pbuf as well.
+
+           If the segment was a FIN, we set the TF_GOT_FIN flag that will
+           be used to indicate to the application that the remote side has
+           closed its end of the connection. */
+        if (inseg.p->tot_len > 0) {
+          recv_data = inseg.p;
+          /* Since this pbuf now is the responsibility of the
+             application, we delete our reference to it so that we won't
+             (mistakingly) deallocate it. */
+          inseg.p = NULL;
+        }
+        if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n"));
+          recv_flags |= TF_GOT_FIN;
+        }
+
+#if TCP_QUEUE_OOSEQ
+        /* We now check if we have segments on the ->ooseq queue that
+           is now in sequence. */
+        while (pcb->ooseq != NULL &&
+               pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) {
+
+          cseg = pcb->ooseq;
+          seqno = pcb->ooseq->tcphdr->seqno;
+
+          pcb->rcv_nxt += TCP_TCPLEN(cseg);
+          LWIP_ASSERT("tcp_receive: ooseq tcplen > rcv_wnd\n",
+                      pcb->rcv_wnd >= TCP_TCPLEN(cseg));
+          pcb->rcv_wnd -= TCP_TCPLEN(cseg);
+
+          tcp_update_rcv_ann_wnd(pcb);
+
+          if (cseg->p->tot_len > 0) {
+            /* Chain this pbuf onto the pbuf that we will pass to
+               the application. */
+            if (recv_data) {
+              pbuf_cat(recv_data, cseg->p);
+            } else {
+              recv_data = cseg->p;
+            }
+            cseg->p = NULL;
+          }
+          if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
+            LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n"));
+            recv_flags |= TF_GOT_FIN;
+            if (pcb->state == ESTABLISHED) { /* force passive close or we can move to active close */
+              pcb->state = CLOSE_WAIT;
+            } 
+          }
+
+          pcb->ooseq = cseg->next;
+          tcp_seg_free(cseg);
+        }
+#endif /* TCP_QUEUE_OOSEQ */
+
+
+        /* Acknowledge the segment(s). */
+        tcp_ack(pcb);
+
+      } else {
+        /* We get here if the incoming segment is out-of-sequence. */
+        tcp_send_empty_ack(pcb);
+#if TCP_QUEUE_OOSEQ
+        /* We queue the segment on the ->ooseq queue. */
+        if (pcb->ooseq == NULL) {
+          pcb->ooseq = tcp_seg_copy(&inseg);
+        } else {
+          /* If the queue is not empty, we walk through the queue and
+             try to find a place where the sequence number of the
+             incoming segment is between the sequence numbers of the
+             previous and the next segment on the ->ooseq queue. That is
+             the place where we put the incoming segment. If needed, we
+             trim the second edges of the previous and the incoming
+             segment so that it will fit into the sequence.
+
+             If the incoming segment has the same sequence number as a
+             segment on the ->ooseq queue, we discard the segment that
+             contains less data. */
+
+          prev = NULL;
+          for(next = pcb->ooseq; next != NULL; next = next->next) {
+            if (seqno == next->tcphdr->seqno) {
+              /* The sequence number of the incoming segment is the
+                 same as the sequence number of the segment on
+                 ->ooseq. We check the lengths to see which one to
+                 discard. */
+              if (inseg.len > next->len) {
+                /* The incoming segment is larger than the old
+                   segment. We replace some segments with the new
+                   one. */
+                cseg = tcp_seg_copy(&inseg);
+                if (cseg != NULL) {
+                  if (prev != NULL) {
+                    prev->next = cseg;
+                  } else {
+                    pcb->ooseq = cseg;
+                  }
+                  tcp_oos_insert_segment(cseg, next);
+                }
+                break;
+              } else {
+                /* Either the lenghts are the same or the incoming
+                   segment was smaller than the old one; in either
+                   case, we ditch the incoming segment. */
+                break;
+              }
+            } else {
+              if (prev == NULL) {
+                if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {
+                  /* The sequence number of the incoming segment is lower
+                     than the sequence number of the first segment on the
+                     queue. We put the incoming segment first on the
+                     queue. */
+                  cseg = tcp_seg_copy(&inseg);
+                  if (cseg != NULL) {
+                    pcb->ooseq = cseg;
+                    tcp_oos_insert_segment(cseg, next);
+                  }
+                  break;
+                }
+              } else {
+                /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) &&
+                  TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/
+                if (TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno+1, next->tcphdr->seqno-1)) {
+                  /* The sequence number of the incoming segment is in
+                     between the sequence numbers of the previous and
+                     the next segment on ->ooseq. We trim trim the previous
+                     segment, delete next segments that included in received segment
+                     and trim received, if needed. */
+                  cseg = tcp_seg_copy(&inseg);
+                  if (cseg != NULL) {
+                    if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) {
+                      /* We need to trim the prev segment. */
+                      prev->len = (u16_t)(seqno - prev->tcphdr->seqno);
+                      pbuf_realloc(prev->p, prev->len);
+                    }
+                    prev->next = cseg;
+                    tcp_oos_insert_segment(cseg, next);
+                  }
+                  break;
+                }
+              }
+              /* If the "next" segment is the last segment on the
+                 ooseq queue, we add the incoming segment to the end
+                 of the list. */
+              if (next->next == NULL &&
+                  TCP_SEQ_GT(seqno, next->tcphdr->seqno)) {
+                if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) {
+                  /* segment "next" already contains all data */
+                  break;
+                }
+                next->next = tcp_seg_copy(&inseg);
+                if (next->next != NULL) {
+                  if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) {
+                    /* We need to trim the last segment. */
+                    next->len = (u16_t)(seqno - next->tcphdr->seqno);
+                    pbuf_realloc(next->p, next->len);
+                  }
+                }
+                break;
+              }
+            }
+            prev = next;
+          }
+        }
+#endif /* TCP_QUEUE_OOSEQ */
+
+      }
+    } else {
+      /* The incoming segment is not withing the window. */
+      tcp_send_empty_ack(pcb);
+    }
+  } else {
+    /* Segments with length 0 is taken care of here. Segments that
+       fall out of the window are ACKed. */
+    /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) ||
+      TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
+    if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){
+      tcp_ack_now(pcb);
+    }
+  }
+}
+
+/**
+ * Parses the options contained in the incoming segment. 
+ *
+ * Called from tcp_listen_input() and tcp_process().
+ * Currently, only the MSS option is supported!
+ *
+ * @param pcb the tcp_pcb for which a segment arrived
+ */
+static void
+tcp_parseopt(struct tcp_pcb *pcb)
+{
+  u16_t c, max_c;
+  u16_t mss;
+  u8_t *opts, opt;
+#if LWIP_TCP_TIMESTAMPS
+  u32_t tsval;
+#endif
+
+  opts = (u8_t *)tcphdr + TCP_HLEN;
+
+  /* Parse the TCP MSS option, if present. */
+  if(TCPH_HDRLEN(tcphdr) > 0x5) {
+    max_c = (TCPH_HDRLEN(tcphdr) - 5) << 2;
+    for (c = 0; c < max_c; ) {
+      opt = opts[c];
+      switch (opt) {
+      case 0x00:
+        /* End of options. */
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: EOL\n"));
+        return;
+      case 0x01:
+        /* NOP option. */
+        ++c;
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: NOP\n"));
+        break;
+      case 0x02:
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: MSS\n"));
+        if (opts[c + 1] != 0x04 || c + 0x04 > max_c) {
+          /* Bad length */
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n"));
+          return;
+        }
+        /* An MSS option with the right option length. */
+        mss = (opts[c + 2] << 8) | opts[c + 3];
+        /* Limit the mss to the configured TCP_MSS and prevent division by zero */
+        pcb->mss = ((mss > TCP_MSS) || (mss == 0)) ? TCP_MSS : mss;
+        /* Advance to next option */
+        c += 0x04;
+        break;
+#if LWIP_TCP_TIMESTAMPS
+      case 0x08:
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: TS\n"));
+        if (opts[c + 1] != 0x0A || c + 0x0A > max_c) {
+          /* Bad length */
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n"));
+          return;
+        }
+        /* TCP timestamp option with valid length */
+        tsval = (opts[c+2]) | (opts[c+3] << 8) | 
+          (opts[c+4] << 16) | (opts[c+5] << 24);
+        if (flags & TCP_SYN) {
+          pcb->ts_recent = ntohl(tsval);
+          pcb->flags |= TF_TIMESTAMP;
+        } else if (TCP_SEQ_BETWEEN(pcb->ts_lastacksent, seqno, seqno+tcplen)) {
+          pcb->ts_recent = ntohl(tsval);
+        }
+        /* Advance to next option */
+        c += 0x0A;
+        break;
+#endif
+      default:
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: other\n"));
+        if (opts[c + 1] == 0) {
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n"));
+          /* If the length field is zero, the options are malformed
+             and we don't process them further. */
+          return;
+        }
+        /* All other options have a length field, so that we easily
+           can skip past them. */
+        c += opts[c + 1];
+      }
+    }
+  }
+}
+
+#endif /* LWIP_TCP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/tcp_out.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/tcp_out.c
new file mode 100644
index 0000000..ddada42
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/tcp_out.c
@@ -0,0 +1,1054 @@
+/**
+ * @file
+ * Transmission Control Protocol, outgoing traffic
+ *
+ * The output functions of TCP.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/tcp.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/sys.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/inet.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+
+#include 
+
+/* Forward declarations.*/
+static void tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb);
+
+static struct tcp_hdr *
+tcp_output_set_header(struct tcp_pcb *pcb, struct pbuf *p, int optlen,
+                      u32_t seqno_be /* already in network byte order */)
+{
+  struct tcp_hdr *tcphdr = p->payload;
+  tcphdr->src = htons(pcb->local_port);
+  tcphdr->dest = htons(pcb->remote_port);
+  tcphdr->seqno = seqno_be;
+  tcphdr->ackno = htonl(pcb->rcv_nxt);
+  TCPH_FLAGS_SET(tcphdr, TCP_ACK);
+  tcphdr->wnd = htons(pcb->rcv_ann_wnd);
+  tcphdr->urgp = 0;
+  TCPH_HDRLEN_SET(tcphdr, (5 + optlen / 4));
+  tcphdr->chksum = 0;
+
+  /* If we're sending a packet, update the announced right window edge */
+  pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd;
+
+  return tcphdr;
+}
+
+/**
+ * Called by tcp_close() to send a segment including flags but not data.
+ *
+ * @param pcb the tcp_pcb over which to send a segment
+ * @param flags the flags to set in the segment header
+ * @return ERR_OK if sent, another err_t otherwise
+ */
+err_t
+tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags)
+{
+  /* no data, no length, flags, copy=1, no optdata */
+  return tcp_enqueue(pcb, NULL, 0, flags, TCP_WRITE_FLAG_COPY, 0);
+}
+
+/**
+ * Write data for sending (but does not send it immediately).
+ *
+ * It waits in the expectation of more data being sent soon (as
+ * it can send them more efficiently by combining them together).
+ * To prompt the system to send data now, call tcp_output() after
+ * calling tcp_write().
+ * 
+ * @param pcb Protocol control block of the TCP connection to enqueue data for.
+ * @param data pointer to the data to send
+ * @param len length (in bytes) of the data to send
+ * @param apiflags combination of following flags :
+ * - TCP_WRITE_FLAG_COPY (0x01) data will be copied into memory belonging to the stack
+ * - TCP_WRITE_FLAG_MORE (0x02) for TCP connection, PSH flag will be set on last segment sent,
+ * @return ERR_OK if enqueued, another err_t on error
+ * 
+ * @see tcp_write()
+ */
+err_t
+tcp_write(struct tcp_pcb *pcb, const void *data, u16_t len, u8_t apiflags)
+{
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, data=%p, len=%"U16_F", apiflags=%"U16_F")\n", (void *)pcb,
+    data, len, (u16_t)apiflags));
+  /* connection is in valid state for data transmission? */
+  if (pcb->state == ESTABLISHED ||
+     pcb->state == CLOSE_WAIT ||
+     pcb->state == SYN_SENT ||
+     pcb->state == SYN_RCVD) {
+    if (len > 0) {
+#if LWIP_TCP_TIMESTAMPS
+      return tcp_enqueue(pcb, (void *)data, len, 0, apiflags, 
+                         pcb->flags & TF_TIMESTAMP ? TF_SEG_OPTS_TS : 0);
+#else
+      return tcp_enqueue(pcb, (void *)data, len, 0, apiflags, 0);
+#endif
+    }
+    return ERR_OK;
+  } else {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_STATE | LWIP_DBG_LEVEL_SEVERE, ("tcp_write() called in invalid state\n"));
+    return ERR_CONN;
+  }
+}
+
+/**
+ * Enqueue data and/or TCP options for transmission
+ *
+ * Called by tcp_connect(), tcp_listen_input(), tcp_send_ctrl() and tcp_write().
+ *
+ * @param pcb Protocol control block for the TCP connection to enqueue data for.
+ * @param arg Pointer to the data to be enqueued for sending.
+ * @param len Data length in bytes
+ * @param flags tcp header flags to set in the outgoing segment
+ * @param apiflags combination of following flags :
+ * - TCP_WRITE_FLAG_COPY (0x01) data will be copied into memory belonging to the stack
+ * - TCP_WRITE_FLAG_MORE (0x02) for TCP connection, PSH flag will be set on last segment sent,
+ * @param optflags options to include in segment later on (see definition of struct tcp_seg)
+ */
+err_t
+tcp_enqueue(struct tcp_pcb *pcb, void *arg, u16_t len,
+            u8_t flags, u8_t apiflags, u8_t optflags)
+{
+  struct pbuf *p;
+  struct tcp_seg *seg, *useg, *queue;
+  u32_t seqno;
+  u16_t left, seglen;
+  void *ptr;
+  u16_t queuelen;
+  u8_t optlen;
+
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, 
+              ("tcp_enqueue(pcb=%p, arg=%p, len=%"U16_F", flags=%"X16_F", apiflags=%"U16_F")\n",
+               (void *)pcb, arg, len, (u16_t)flags, (u16_t)apiflags));
+  LWIP_ERROR("tcp_enqueue: packet needs payload, options, or SYN/FIN (programmer violates API)",
+             ((len != 0) || (optflags != 0) || ((flags & (TCP_SYN | TCP_FIN)) != 0)),
+             return ERR_ARG;);
+  LWIP_ERROR("tcp_enqueue: len != 0 || arg == NULL (programmer violates API)", 
+             ((len != 0) || (arg == NULL)), return ERR_ARG;);
+
+  /* fail on too much data */
+  if (len > pcb->snd_buf) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_WARNING,
+      ("tcp_enqueue: too much data (len=%"U16_F" > snd_buf=%"U16_F")\n", len, pcb->snd_buf));
+    pcb->flags |= TF_NAGLEMEMERR;
+    return ERR_MEM;
+  }
+  left = len;
+  ptr = arg;
+
+  optlen = LWIP_TCP_OPT_LENGTH(optflags);
+
+  /* seqno will be the sequence number of the first segment enqueued
+   * by the call to this function. */
+  seqno = pcb->snd_lbb;
+
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen));
+
+  /* If total number of pbufs on the unsent/unacked queues exceeds the
+   * configured maximum, return an error */
+  queuelen = pcb->snd_queuelen;
+  /* check for configured max queuelen and possible overflow */
+  if ((queuelen >= TCP_SND_QUEUELEN) || (queuelen > TCP_SNDQUEUELEN_OVERFLOW)) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_WARNING,
+      ("tcp_enqueue: too long queue %"U16_F" (max %"U16_F")\n", queuelen, TCP_SND_QUEUELEN));
+    TCP_STATS_INC(tcp.memerr);
+    pcb->flags |= TF_NAGLEMEMERR;
+    return ERR_MEM;
+  }
+  if (queuelen != 0) {
+    LWIP_ASSERT("tcp_enqueue: pbufs on queue => at least one queue non-empty",
+      pcb->unacked != NULL || pcb->unsent != NULL);
+  } else {
+    LWIP_ASSERT("tcp_enqueue: no pbufs on queue => both queues empty",
+      pcb->unacked == NULL && pcb->unsent == NULL);
+  }
+
+  /* First, break up the data into segments and tuck them together in
+   * the local "queue" variable. */
+  useg = queue = seg = NULL;
+  seglen = 0;
+  while (queue == NULL || left > 0) {
+    /* The segment length (including options) should be at most the MSS */
+    seglen = left > (pcb->mss - optlen) ? (pcb->mss - optlen) : left;
+
+    /* Allocate memory for tcp_seg, and fill in fields. */
+    seg = memp_malloc(MEMP_TCP_SEG);
+    if (seg == NULL) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, 
+                  ("tcp_enqueue: could not allocate memory for tcp_seg\n"));
+      goto memerr;
+    }
+    seg->next = NULL;
+    seg->p = NULL;
+
+    /* first segment of to-be-queued data? */
+    if (queue == NULL) {
+      queue = seg;
+    }
+    /* subsequent segments of to-be-queued data */
+    else {
+      /* Attach the segment to the end of the queued segments */
+      LWIP_ASSERT("useg != NULL", useg != NULL);
+      useg->next = seg;
+    }
+    /* remember last segment of to-be-queued data for next iteration */
+    useg = seg;
+
+    /* If copy is set, memory should be allocated
+     * and data copied into pbuf, otherwise data comes from
+     * ROM or other static memory, and need not be copied.  */
+    if (apiflags & TCP_WRITE_FLAG_COPY) {
+      if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, seglen + optlen, PBUF_RAM)) == NULL) {
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, 
+                    ("tcp_enqueue : could not allocate memory for pbuf copy size %"U16_F"\n", seglen));
+        goto memerr;
+      }
+      LWIP_ASSERT("check that first pbuf can hold the complete seglen",
+                  (seg->p->len >= seglen + optlen));
+      queuelen += pbuf_clen(seg->p);
+      if (arg != NULL) {
+        MEMCPY((char *)seg->p->payload + optlen, ptr, seglen);
+      }
+      seg->dataptr = seg->p->payload;
+    }
+    /* do not copy data */
+    else {
+      /* First, allocate a pbuf for the headers. */
+      if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) {
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, 
+                    ("tcp_enqueue: could not allocate memory for header pbuf\n"));
+        goto memerr;
+      }
+      queuelen += pbuf_clen(seg->p);
+
+      /* Second, allocate a pbuf for holding the data.
+       * since the referenced data is available at least until it is sent out on the
+       * link (as it has to be ACKed by the remote party) we can safely use PBUF_ROM
+       * instead of PBUF_REF here.
+       */
+      if (left > 0) {
+        if ((p = pbuf_alloc(PBUF_RAW, seglen, PBUF_ROM)) == NULL) {
+          /* If allocation fails, we have to deallocate the header pbuf as well. */
+          pbuf_free(seg->p);
+          seg->p = NULL;
+          LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, 
+                      ("tcp_enqueue: could not allocate memory for zero-copy pbuf\n"));
+          goto memerr;
+        }
+        ++queuelen;
+        /* reference the non-volatile payload data */
+        p->payload = ptr;
+        seg->dataptr = ptr;
+
+        /* Concatenate the headers and data pbufs together. */
+        pbuf_cat(seg->p/*header*/, p/*data*/);
+        p = NULL;
+      }
+    }
+
+    /* Now that there are more segments queued, we check again if the
+    length of the queue exceeds the configured maximum or overflows. */
+    if ((queuelen > TCP_SND_QUEUELEN) || (queuelen > TCP_SNDQUEUELEN_OVERFLOW)) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+        ("tcp_enqueue: queue too long %"U16_F" (%"U16_F")\n", queuelen, TCP_SND_QUEUELEN));
+      goto memerr;
+    }
+
+    seg->len = seglen;
+
+    /* build TCP header */
+    if (pbuf_header(seg->p, TCP_HLEN)) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_enqueue: no room for TCP header in pbuf.\n"));
+      TCP_STATS_INC(tcp.err);
+      goto memerr;
+    }
+    seg->tcphdr = seg->p->payload;
+    seg->tcphdr->src = htons(pcb->local_port);
+    seg->tcphdr->dest = htons(pcb->remote_port);
+    seg->tcphdr->seqno = htonl(seqno);
+    seg->tcphdr->urgp = 0;
+    TCPH_FLAGS_SET(seg->tcphdr, flags);
+    /* don't fill in tcphdr->ackno and tcphdr->wnd until later */
+
+    seg->flags = optflags;
+
+    /* Set the length of the header */
+    TCPH_HDRLEN_SET(seg->tcphdr, (5 + optlen / 4));
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_TRACE, ("tcp_enqueue: queueing %"U32_F":%"U32_F" (0x%"X16_F")\n",
+      ntohl(seg->tcphdr->seqno),
+      ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg),
+      (u16_t)flags));
+
+    left -= seglen;
+    seqno += seglen;
+    ptr = (void *)((u8_t *)ptr + seglen);
+  }
+
+  /* Now that the data to be enqueued has been broken up into TCP
+  segments in the queue variable, we add them to the end of the
+  pcb->unsent queue. */
+  if (pcb->unsent == NULL) {
+    useg = NULL;
+  }
+  else {
+    for (useg = pcb->unsent; useg->next != NULL; useg = useg->next);
+  }
+  /* { useg is last segment on the unsent queue, NULL if list is empty } */
+
+  /* If there is room in the last pbuf on the unsent queue,
+  chain the first pbuf on the queue together with that. */
+  if (useg != NULL &&
+    TCP_TCPLEN(useg) != 0 &&
+    !(TCPH_FLAGS(useg->tcphdr) & (TCP_SYN | TCP_FIN)) &&
+    (!(flags & (TCP_SYN | TCP_FIN)) || (flags == TCP_FIN)) &&
+    /* fit within max seg size */
+    (useg->len + queue->len <= pcb->mss) &&
+    /* only concatenate segments with the same options */
+    (useg->flags == queue->flags) &&
+    /* segments are consecutive */
+    (ntohl(useg->tcphdr->seqno) + useg->len == ntohl(queue->tcphdr->seqno)) ) {
+    /* Remove TCP header from first segment of our to-be-queued list */
+    if(pbuf_header(queue->p, -(TCP_HLEN + optlen))) {
+      /* Can we cope with this failing?  Just assert for now */
+      LWIP_ASSERT("pbuf_header failed\n", 0);
+      TCP_STATS_INC(tcp.err);
+      goto memerr;
+    }
+    if (queue->p->len == 0) {
+      /* free the first (header-only) pbuf if it is now empty (contained only headers) */
+      struct pbuf *old_q = queue->p;
+      queue->p = queue->p->next;
+      old_q->next = NULL;
+      queuelen--;
+      pbuf_free(old_q);
+    }
+    if (flags & TCP_FIN) {
+      /* the new segment contains only FIN, no data -> put the FIN into the last segment */
+      LWIP_ASSERT("FIN enqueued together with data", queue->p == NULL && queue->len == 0);
+      TCPH_SET_FLAG(useg->tcphdr, TCP_FIN);
+    } else {
+      LWIP_ASSERT("zero-length pbuf", (queue->p != NULL) && (queue->p->len > 0));
+      pbuf_cat(useg->p, queue->p);
+      useg->len += queue->len;
+      useg->next = queue->next;
+    }
+
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("tcp_enqueue: chaining segments, new len %"U16_F"\n", useg->len));
+    if (seg == queue) {
+      seg = useg;
+      seglen = useg->len;
+    }
+    memp_free(MEMP_TCP_SEG, queue);
+  }
+  else {
+    /* empty list */
+    if (useg == NULL) {
+      /* initialize list with this segment */
+      pcb->unsent = queue;
+    }
+    /* enqueue segment */
+    else {
+      useg->next = queue;
+    }
+  }
+  if ((flags & TCP_SYN) || (flags & TCP_FIN)) {
+    ++len;
+  }
+  if (flags & TCP_FIN) {
+    pcb->flags |= TF_FIN;
+  }
+  pcb->snd_lbb += len;
+
+  pcb->snd_buf -= len;
+
+  /* update number of segments on the queues */
+  pcb->snd_queuelen = queuelen;
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: %"S16_F" (after enqueued)\n", pcb->snd_queuelen));
+  if (pcb->snd_queuelen != 0) {
+    LWIP_ASSERT("tcp_enqueue: valid queue length",
+      pcb->unacked != NULL || pcb->unsent != NULL);
+  }
+
+  /* Set the PSH flag in the last segment that we enqueued, but only
+  if the segment has data (indicated by seglen > 0). */
+  if (seg != NULL && seglen > 0 && seg->tcphdr != NULL && ((apiflags & TCP_WRITE_FLAG_MORE)==0)) {
+    TCPH_SET_FLAG(seg->tcphdr, TCP_PSH);
+  }
+
+  return ERR_OK;
+memerr:
+  pcb->flags |= TF_NAGLEMEMERR;
+  TCP_STATS_INC(tcp.memerr);
+
+  if (queue != NULL) {
+    tcp_segs_free(queue);
+  }
+  if (pcb->snd_queuelen != 0) {
+    LWIP_ASSERT("tcp_enqueue: valid queue length", pcb->unacked != NULL ||
+      pcb->unsent != NULL);
+  }
+  LWIP_DEBUGF(TCP_QLEN_DEBUG | LWIP_DBG_STATE, ("tcp_enqueue: %"S16_F" (with mem err)\n", pcb->snd_queuelen));
+  return ERR_MEM;
+}
+
+
+#if LWIP_TCP_TIMESTAMPS
+/* Build a timestamp option (12 bytes long) at the specified options pointer)
+ *
+ * @param pcb tcp_pcb
+ * @param opts option pointer where to store the timestamp option
+ */
+static void
+tcp_build_timestamp_option(struct tcp_pcb *pcb, u32_t *opts)
+{
+  /* Pad with two NOP options to make everything nicely aligned */
+  opts[0] = htonl(0x0101080A);
+  opts[1] = htonl(sys_now());
+  opts[2] = htonl(pcb->ts_recent);
+}
+#endif
+
+/** Send an ACK without data.
+ *
+ * @param pcb Protocol control block for the TCP connection to send the ACK
+ */
+err_t
+tcp_send_empty_ack(struct tcp_pcb *pcb)
+{
+  struct pbuf *p;
+  struct tcp_hdr *tcphdr;
+  u8_t optlen = 0;
+
+#if LWIP_TCP_TIMESTAMPS
+  if (pcb->flags & TF_TIMESTAMP) {
+    optlen = LWIP_TCP_OPT_LENGTH(TF_SEG_OPTS_TS);
+  }
+#endif
+  p = pbuf_alloc(PBUF_IP, TCP_HLEN + optlen, PBUF_RAM);
+  if (p == NULL) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n"));
+    return ERR_BUF;
+  }
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, 
+              ("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt));
+  /* remove ACK flags from the PCB, as we send an empty ACK now */
+  pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
+
+  tcphdr = tcp_output_set_header(pcb, p, optlen, htonl(pcb->snd_nxt));
+
+  /* NB. MSS option is only sent on SYNs, so ignore it here */
+#if LWIP_TCP_TIMESTAMPS
+  pcb->ts_lastacksent = pcb->rcv_nxt;
+
+  if (pcb->flags & TF_TIMESTAMP) {
+    tcp_build_timestamp_option(pcb, (u32_t *)(tcphdr + 1));
+  }
+#endif 
+
+#if CHECKSUM_GEN_TCP
+  tcphdr->chksum = inet_chksum_pseudo(p, &(pcb->local_ip), &(pcb->remote_ip),
+        IP_PROTO_TCP, p->tot_len);
+#endif
+#if LWIP_NETIF_HWADDRHINT
+  ip_output_hinted(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,
+      IP_PROTO_TCP, &(pcb->addr_hint));
+#else /* LWIP_NETIF_HWADDRHINT*/
+  ip_output(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,
+      IP_PROTO_TCP);
+#endif /* LWIP_NETIF_HWADDRHINT*/
+  pbuf_free(p);
+
+  return ERR_OK;
+}
+
+/**
+ * Find out what we can send and send it
+ *
+ * @param pcb Protocol control block for the TCP connection to send data
+ * @return ERR_OK if data has been sent or nothing to send
+ *         another err_t on error
+ */
+err_t
+tcp_output(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *seg, *useg;
+  u32_t wnd, snd_nxt;
+#if TCP_CWND_DEBUG
+  s16_t i = 0;
+#endif /* TCP_CWND_DEBUG */
+
+  /* First, check if we are invoked by the TCP input processing
+     code. If so, we do not output anything. Instead, we rely on the
+     input processing code to call us when input processing is done
+     with. */
+  if (tcp_input_pcb == pcb) {
+    return ERR_OK;
+  }
+
+  wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd);
+
+  seg = pcb->unsent;
+
+  /* If the TF_ACK_NOW flag is set and no data will be sent (either
+   * because the ->unsent queue is empty or because the window does
+   * not allow it), construct an empty ACK segment and send it.
+   *
+   * If data is to be sent, we will just piggyback the ACK (see below).
+   */
+  if (pcb->flags & TF_ACK_NOW &&
+     (seg == NULL ||
+      ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd)) {
+     return tcp_send_empty_ack(pcb);
+  }
+
+  /* useg should point to last segment on unacked queue */
+  useg = pcb->unacked;
+  if (useg != NULL) {
+    for (; useg->next != NULL; useg = useg->next);
+  }
+
+#if TCP_OUTPUT_DEBUG
+  if (seg == NULL) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: nothing to send (%p)\n",
+                                   (void*)pcb->unsent));
+  }
+#endif /* TCP_OUTPUT_DEBUG */
+#if TCP_CWND_DEBUG
+  if (seg == NULL) {
+    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U16_F
+                                 ", cwnd %"U16_F", wnd %"U32_F
+                                 ", seg == NULL, ack %"U32_F"\n",
+                                 pcb->snd_wnd, pcb->cwnd, wnd, pcb->lastack));
+  } else {
+    LWIP_DEBUGF(TCP_CWND_DEBUG, 
+                ("tcp_output: snd_wnd %"U16_F", cwnd %"U16_F", wnd %"U32_F
+                 ", effwnd %"U32_F", seq %"U32_F", ack %"U32_F"\n",
+                 pcb->snd_wnd, pcb->cwnd, wnd,
+                 ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len,
+                 ntohl(seg->tcphdr->seqno), pcb->lastack));
+  }
+#endif /* TCP_CWND_DEBUG */
+  /* data available and window allows it to be sent? */
+  while (seg != NULL &&
+         ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) {
+    LWIP_ASSERT("RST not expected here!", 
+                (TCPH_FLAGS(seg->tcphdr) & TCP_RST) == 0);
+    /* Stop sending if the nagle algorithm would prevent it
+     * Don't stop:
+     * - if tcp_enqueue had a memory error before (prevent delayed ACK timeout) or
+     * - if FIN was already enqueued for this PCB (SYN is always alone in a segment -
+     *   either seg->next != NULL or pcb->unacked == NULL;
+     *   RST is no sent using tcp_enqueue/tcp_output.
+     */
+    if((tcp_do_output_nagle(pcb) == 0) &&
+      ((pcb->flags & (TF_NAGLEMEMERR | TF_FIN)) == 0)){
+      break;
+    }
+#if TCP_CWND_DEBUG
+    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U16_F", cwnd %"U16_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F", i %"S16_F"\n",
+                            pcb->snd_wnd, pcb->cwnd, wnd,
+                            ntohl(seg->tcphdr->seqno) + seg->len -
+                            pcb->lastack,
+                            ntohl(seg->tcphdr->seqno), pcb->lastack, i));
+    ++i;
+#endif /* TCP_CWND_DEBUG */
+
+    pcb->unsent = seg->next;
+
+    if (pcb->state != SYN_SENT) {
+      TCPH_SET_FLAG(seg->tcphdr, TCP_ACK);
+      pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
+    }
+
+    tcp_output_segment(seg, pcb);
+    snd_nxt = ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);
+    if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) {
+      pcb->snd_nxt = snd_nxt;
+    }
+    /* put segment on unacknowledged list if length > 0 */
+    if (TCP_TCPLEN(seg) > 0) {
+      seg->next = NULL;
+      /* unacked list is empty? */
+      if (pcb->unacked == NULL) {
+        pcb->unacked = seg;
+        useg = seg;
+      /* unacked list is not empty? */
+      } else {
+        /* In the case of fast retransmit, the packet should not go to the tail
+         * of the unacked queue, but rather somewhere before it. We need to check for
+         * this case. -STJ Jul 27, 2004 */
+        if (TCP_SEQ_LT(ntohl(seg->tcphdr->seqno), ntohl(useg->tcphdr->seqno))){
+          /* add segment to before tail of unacked list, keeping the list sorted */
+          struct tcp_seg **cur_seg = &(pcb->unacked);
+          while (*cur_seg &&
+            TCP_SEQ_LT(ntohl((*cur_seg)->tcphdr->seqno), ntohl(seg->tcphdr->seqno))) {
+              cur_seg = &((*cur_seg)->next );
+          }
+          seg->next = (*cur_seg);
+          (*cur_seg) = seg;
+        } else {
+          /* add segment to tail of unacked list */
+          useg->next = seg;
+          useg = useg->next;
+        }
+      }
+    /* do not queue empty segments on the unacked list */
+    } else {
+      tcp_seg_free(seg);
+    }
+    seg = pcb->unsent;
+  }
+
+  if (seg != NULL && pcb->persist_backoff == 0 && 
+      ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > pcb->snd_wnd) {
+    /* prepare for persist timer */
+    pcb->persist_cnt = 0;
+    pcb->persist_backoff = 1;
+  }
+
+  pcb->flags &= ~TF_NAGLEMEMERR;
+  return ERR_OK;
+}
+
+/**
+ * Called by tcp_output() to actually send a TCP segment over IP.
+ *
+ * @param seg the tcp_seg to send
+ * @param pcb the tcp_pcb for the TCP connection used to send the segment
+ */
+static void
+tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb)
+{
+  u16_t len;
+  struct netif *netif;
+  u32_t *opts;
+
+  /** @bug Exclude retransmitted segments from this count. */
+  snmp_inc_tcpoutsegs();
+
+  /* The TCP header has already been constructed, but the ackno and
+   wnd fields remain. */
+  seg->tcphdr->ackno = htonl(pcb->rcv_nxt);
+
+  /* advertise our receive window size in this TCP segment */
+  seg->tcphdr->wnd = htons(pcb->rcv_ann_wnd);
+
+  pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd;
+
+  /* Add any requested options.  NB MSS option is only set on SYN
+     packets, so ignore it here */
+  opts = (u32_t *)(seg->tcphdr + 1);
+  if (seg->flags & TF_SEG_OPTS_MSS) {
+    TCP_BUILD_MSS_OPTION(*opts);
+    opts += 1;
+  }
+#if LWIP_TCP_TIMESTAMPS
+  pcb->ts_lastacksent = pcb->rcv_nxt;
+
+  if (seg->flags & TF_SEG_OPTS_TS) {
+    tcp_build_timestamp_option(pcb, opts);
+    opts += 3;
+  }
+#endif
+
+  /* If we don't have a local IP address, we get one by
+     calling ip_route(). */
+  if (ip_addr_isany(&(pcb->local_ip))) {
+    netif = ip_route(&(pcb->remote_ip));
+    if (netif == NULL) {
+      return;
+    }
+    ip_addr_set(&(pcb->local_ip), &(netif->ip_addr));
+  }
+
+  /* Set retransmission timer running if it is not currently enabled */
+  if(pcb->rtime == -1)
+    pcb->rtime = 0;
+
+  if (pcb->rttest == 0) {
+    pcb->rttest = tcp_ticks;
+    pcb->rtseq = ntohl(seg->tcphdr->seqno);
+
+    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_output_segment: rtseq %"U32_F"\n", pcb->rtseq));
+  }
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n",
+          htonl(seg->tcphdr->seqno), htonl(seg->tcphdr->seqno) +
+          seg->len));
+
+  len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload);
+
+  seg->p->len -= len;
+  seg->p->tot_len -= len;
+
+  seg->p->payload = seg->tcphdr;
+
+  seg->tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+  seg->tcphdr->chksum = inet_chksum_pseudo(seg->p,
+             &(pcb->local_ip),
+             &(pcb->remote_ip),
+             IP_PROTO_TCP, seg->p->tot_len);
+#endif
+  TCP_STATS_INC(tcp.xmit);
+
+#if LWIP_NETIF_HWADDRHINT
+  ip_output_hinted(seg->p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,
+      IP_PROTO_TCP, &(pcb->addr_hint));
+#else /* LWIP_NETIF_HWADDRHINT*/
+  ip_output(seg->p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,
+      IP_PROTO_TCP);
+#endif /* LWIP_NETIF_HWADDRHINT*/
+}
+
+/**
+ * Send a TCP RESET packet (empty segment with RST flag set) either to
+ * abort a connection or to show that there is no matching local connection
+ * for a received segment.
+ *
+ * Called by tcp_abort() (to abort a local connection), tcp_input() (if no
+ * matching local pcb was found), tcp_listen_input() (if incoming segment
+ * has ACK flag set) and tcp_process() (received segment in the wrong state)
+ *
+ * Since a RST segment is in most cases not sent for an active connection,
+ * tcp_rst() has a number of arguments that are taken from a tcp_pcb for
+ * most other segment output functions.
+ *
+ * @param seqno the sequence number to use for the outgoing segment
+ * @param ackno the acknowledge number to use for the outgoing segment
+ * @param local_ip the local IP address to send the segment from
+ * @param remote_ip the remote IP address to send the segment to
+ * @param local_port the local TCP port to send the segment from
+ * @param remote_port the remote TCP port to send the segment to
+ */
+void
+tcp_rst(u32_t seqno, u32_t ackno,
+  struct ip_addr *local_ip, struct ip_addr *remote_ip,
+  u16_t local_port, u16_t remote_port)
+{
+  struct pbuf *p;
+  struct tcp_hdr *tcphdr;
+  p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
+  if (p == NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n"));
+      return;
+  }
+  LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr",
+              (p->len >= sizeof(struct tcp_hdr)));
+
+  tcphdr = p->payload;
+  tcphdr->src = htons(local_port);
+  tcphdr->dest = htons(remote_port);
+  tcphdr->seqno = htonl(seqno);
+  tcphdr->ackno = htonl(ackno);
+  TCPH_FLAGS_SET(tcphdr, TCP_RST | TCP_ACK);
+  tcphdr->wnd = htons(TCP_WND);
+  tcphdr->urgp = 0;
+  TCPH_HDRLEN_SET(tcphdr, 5);
+
+  tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+  tcphdr->chksum = inet_chksum_pseudo(p, local_ip, remote_ip,
+              IP_PROTO_TCP, p->tot_len);
+#endif
+  TCP_STATS_INC(tcp.xmit);
+  snmp_inc_tcpoutrsts();
+   /* Send output with hardcoded TTL since we have no access to the pcb */
+  ip_output(p, local_ip, remote_ip, TCP_TTL, 0, IP_PROTO_TCP);
+  pbuf_free(p);
+  LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno));
+}
+
+/**
+ * Requeue all unacked segments for retransmission
+ *
+ * Called by tcp_slowtmr() for slow retransmission.
+ *
+ * @param pcb the tcp_pcb for which to re-enqueue all unacked segments
+ */
+void
+tcp_rexmit_rto(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *seg;
+
+  if (pcb->unacked == NULL) {
+    return;
+  }
+
+  /* Move all unacked segments to the head of the unsent queue */
+  for (seg = pcb->unacked; seg->next != NULL; seg = seg->next);
+  /* concatenate unsent queue after unacked queue */
+  seg->next = pcb->unsent;
+  /* unsent queue is the concatenated queue (of unacked, unsent) */
+  pcb->unsent = pcb->unacked;
+  /* unacked queue is now empty */
+  pcb->unacked = NULL;
+
+  /* increment number of retransmissions */
+  ++pcb->nrtx;
+
+  /* Don't take any RTT measurements after retransmitting. */
+  pcb->rttest = 0;
+
+  /* Do the actual retransmission */
+  tcp_output(pcb);
+}
+
+/**
+ * Requeue the first unacked segment for retransmission
+ *
+ * Called by tcp_receive() for fast retramsmit.
+ *
+ * @param pcb the tcp_pcb for which to retransmit the first unacked segment
+ */
+void
+tcp_rexmit(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *seg;
+  struct tcp_seg **cur_seg;
+
+  if (pcb->unacked == NULL) {
+    return;
+  }
+
+  /* Move the first unacked segment to the unsent queue */
+  /* Keep the unsent queue sorted. */
+  seg = pcb->unacked;
+  pcb->unacked = seg->next;
+
+  cur_seg = &(pcb->unsent);
+  while (*cur_seg &&
+    TCP_SEQ_LT(ntohl((*cur_seg)->tcphdr->seqno), ntohl(seg->tcphdr->seqno))) {
+      cur_seg = &((*cur_seg)->next );
+  }
+  seg->next = *cur_seg;
+  *cur_seg = seg;
+
+  ++pcb->nrtx;
+
+  /* Don't take any rtt measurements after retransmitting. */
+  pcb->rttest = 0;
+
+  /* Do the actual retransmission. */
+  snmp_inc_tcpretranssegs();
+  /* No need to call tcp_output: we are always called from tcp_input()
+     and thus tcp_output directly returns. */
+}
+
+
+/**
+ * Handle retransmission after three dupacks received
+ *
+ * @param pcb the tcp_pcb for which to retransmit the first unacked segment
+ */
+void 
+tcp_rexmit_fast(struct tcp_pcb *pcb)
+{
+  if (pcb->unacked != NULL && !(pcb->flags & TF_INFR)) {
+    /* This is fast retransmit. Retransmit the first unacked segment. */
+    LWIP_DEBUGF(TCP_FR_DEBUG, 
+                ("tcp_receive: dupacks %"U16_F" (%"U32_F
+                 "), fast retransmit %"U32_F"\n",
+                 (u16_t)pcb->dupacks, pcb->lastack,
+                 ntohl(pcb->unacked->tcphdr->seqno)));
+    tcp_rexmit(pcb);
+
+    /* Set ssthresh to half of the minimum of the current
+     * cwnd and the advertised window */
+    if (pcb->cwnd > pcb->snd_wnd)
+      pcb->ssthresh = pcb->snd_wnd / 2;
+    else
+      pcb->ssthresh = pcb->cwnd / 2;
+    
+    /* The minimum value for ssthresh should be 2 MSS */
+    if (pcb->ssthresh < 2*pcb->mss) {
+      LWIP_DEBUGF(TCP_FR_DEBUG, 
+                  ("tcp_receive: The minimum value for ssthresh %"U16_F
+                   " should be min 2 mss %"U16_F"...\n",
+                   pcb->ssthresh, 2*pcb->mss));
+      pcb->ssthresh = 2*pcb->mss;
+    }
+    
+    pcb->cwnd = pcb->ssthresh + 3 * pcb->mss;
+    pcb->flags |= TF_INFR;
+  } 
+}
+
+
+/**
+ * Send keepalive packets to keep a connection active although
+ * no data is sent over it.
+ *
+ * Called by tcp_slowtmr()
+ *
+ * @param pcb the tcp_pcb for which to send a keepalive packet
+ */
+void
+tcp_keepalive(struct tcp_pcb *pcb)
+{
+  struct pbuf *p;
+  struct tcp_hdr *tcphdr;
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: sending KEEPALIVE probe to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+                          ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+                          ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip)));
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F"   pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n", 
+                          tcp_ticks, pcb->tmr, pcb->keep_cnt_sent));
+   
+  p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
+   
+  if(p == NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, 
+                ("tcp_keepalive: could not allocate memory for pbuf\n"));
+    return;
+  }
+  LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr",
+              (p->len >= sizeof(struct tcp_hdr)));
+
+  tcphdr = tcp_output_set_header(pcb, p, 0, htonl(pcb->snd_nxt - 1));
+
+#if CHECKSUM_GEN_TCP
+  tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip,
+                                      IP_PROTO_TCP, p->tot_len);
+#endif
+  TCP_STATS_INC(tcp.xmit);
+
+  /* Send output to IP */
+#if LWIP_NETIF_HWADDRHINT
+  ip_output_hinted(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP,
+    &(pcb->addr_hint));
+#else /* LWIP_NETIF_HWADDRHINT*/
+  ip_output(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP);
+#endif /* LWIP_NETIF_HWADDRHINT*/
+
+  pbuf_free(p);
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F".\n",
+                          pcb->snd_nxt - 1, pcb->rcv_nxt));
+}
+
+
+/**
+ * Send persist timer zero-window probes to keep a connection active
+ * when a window update is lost.
+ *
+ * Called by tcp_slowtmr()
+ *
+ * @param pcb the tcp_pcb for which to send a zero-window probe packet
+ */
+void
+tcp_zero_window_probe(struct tcp_pcb *pcb)
+{
+  struct pbuf *p;
+  struct tcp_hdr *tcphdr;
+  struct tcp_seg *seg;
+  u16_t len;
+  u8_t is_fin;
+
+  LWIP_DEBUGF(TCP_DEBUG, 
+              ("tcp_zero_window_probe: sending ZERO WINDOW probe to %"
+               U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+               ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+               ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip)));
+
+  LWIP_DEBUGF(TCP_DEBUG, 
+              ("tcp_zero_window_probe: tcp_ticks %"U32_F
+               "   pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n", 
+               tcp_ticks, pcb->tmr, pcb->keep_cnt_sent));
+
+  seg = pcb->unacked;
+
+  if(seg == NULL)
+    seg = pcb->unsent;
+
+  if(seg == NULL)
+    return;
+
+  is_fin = ((TCPH_FLAGS(seg->tcphdr) & TCP_FIN) != 0) && (seg->len == 0);
+  len = is_fin ? TCP_HLEN : TCP_HLEN + 1;
+
+  p = pbuf_alloc(PBUF_IP, len, PBUF_RAM);
+  if(p == NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: no memory for pbuf\n"));
+    return;
+  }
+  LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr",
+              (p->len >= sizeof(struct tcp_hdr)));
+
+  tcphdr = tcp_output_set_header(pcb, p, 0, seg->tcphdr->seqno);
+
+  if (is_fin) {
+    /* FIN segment, no data */
+    TCPH_FLAGS_SET(tcphdr, TCP_ACK | TCP_FIN);
+  } else {
+    /* Data segment, copy in one byte from the head of the unacked queue */
+    *((char *)p->payload + sizeof(struct tcp_hdr)) = *(char *)seg->dataptr;
+  }
+
+#if CHECKSUM_GEN_TCP
+  tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip,
+                                      IP_PROTO_TCP, p->tot_len);
+#endif
+  TCP_STATS_INC(tcp.xmit);
+
+  /* Send output to IP */
+#if LWIP_NETIF_HWADDRHINT
+  ip_output_hinted(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP,
+    &(pcb->addr_hint));
+#else /* LWIP_NETIF_HWADDRHINT*/
+  ip_output(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP);
+#endif /* LWIP_NETIF_HWADDRHINT*/
+
+  pbuf_free(p);
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: seqno %"U32_F
+                          " ackno %"U32_F".\n",
+                          pcb->snd_nxt - 1, pcb->rcv_nxt));
+}
+#endif /* LWIP_TCP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/udp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/udp.c
new file mode 100644
index 0000000..96dab41
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/core/udp.c
@@ -0,0 +1,841 @@
+/**
+ * @file
+ * User Datagram Protocol module
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+/* udp.c
+ *
+ * The code for the User Datagram Protocol UDP & UDPLite (RFC 3828).
+ *
+ */
+
+/* @todo Check the use of '(struct udp_pcb).chksum_len_rx'!
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_UDP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/udp.h"
+#include "lwip/def.h"
+#include "lwip/memp.h"
+#include "lwip/inet.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/icmp.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+#include "arch/perf.h"
+#include "lwip/dhcp.h"
+
+#include 
+
+/* The list of UDP PCBs */
+/* exported in udp.h (was static) */
+struct udp_pcb *udp_pcbs;
+
+/**
+ * Process an incoming UDP datagram.
+ *
+ * Given an incoming UDP datagram (as a chain of pbufs) this function
+ * finds a corresponding UDP PCB and hands over the pbuf to the pcbs
+ * recv function. If no pcb is found or the datagram is incorrect, the
+ * pbuf is freed.
+ *
+ * @param p pbuf to be demultiplexed to a UDP PCB.
+ * @param inp network interface on which the datagram was received.
+ *
+ */
+void
+udp_input(struct pbuf *p, struct netif *inp)
+{
+  struct udp_hdr *udphdr;
+  struct udp_pcb *pcb, *prev;
+  struct udp_pcb *uncon_pcb;
+  struct ip_hdr *iphdr;
+  u16_t src, dest;
+  u8_t local_match;
+  u8_t broadcast;
+
+  PERF_START;
+
+  UDP_STATS_INC(udp.recv);
+
+  iphdr = p->payload;
+
+  /* Check minimum length (IP header + UDP header)
+   * and move payload pointer to UDP header */
+  if (p->tot_len < (IPH_HL(iphdr) * 4 + UDP_HLEN) || pbuf_header(p, -(s16_t)(IPH_HL(iphdr) * 4))) {
+    /* drop short packets */
+    LWIP_DEBUGF(UDP_DEBUG,
+                ("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len));
+    UDP_STATS_INC(udp.lenerr);
+    UDP_STATS_INC(udp.drop);
+    snmp_inc_udpinerrors();
+    pbuf_free(p);
+    goto end;
+  }
+
+  udphdr = (struct udp_hdr *)p->payload;
+
+  /* is broadcast packet ? */
+  broadcast = ip_addr_isbroadcast(&(iphdr->dest), inp);
+
+  LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len));
+
+  /* convert src and dest ports to host byte order */
+  src = ntohs(udphdr->src);
+  dest = ntohs(udphdr->dest);
+
+  udp_debug_print(udphdr);
+
+  /* print the UDP source and destination */
+  LWIP_DEBUGF(UDP_DEBUG,
+              ("udp (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") <-- "
+               "(%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n",
+               ip4_addr1(&iphdr->dest), ip4_addr2(&iphdr->dest),
+               ip4_addr3(&iphdr->dest), ip4_addr4(&iphdr->dest), ntohs(udphdr->dest),
+               ip4_addr1(&iphdr->src), ip4_addr2(&iphdr->src),
+               ip4_addr3(&iphdr->src), ip4_addr4(&iphdr->src), ntohs(udphdr->src)));
+
+#if LWIP_DHCP
+  pcb = NULL;
+  /* when LWIP_DHCP is active, packets to DHCP_CLIENT_PORT may only be processed by
+     the dhcp module, no other UDP pcb may use the local UDP port DHCP_CLIENT_PORT */
+  if (dest == DHCP_CLIENT_PORT) {
+    /* all packets for DHCP_CLIENT_PORT not coming from DHCP_SERVER_PORT are dropped! */
+    if (src == DHCP_SERVER_PORT) {
+      if ((inp->dhcp != NULL) && (inp->dhcp->pcb != NULL)) {
+        /* accept the packe if 
+           (- broadcast or directed to us) -> DHCP is link-layer-addressed, local ip is always ANY!
+           - inp->dhcp->pcb->remote == ANY or iphdr->src */
+        if ((ip_addr_isany(&inp->dhcp->pcb->remote_ip) ||
+           ip_addr_cmp(&(inp->dhcp->pcb->remote_ip), &(iphdr->src)))) {
+          pcb = inp->dhcp->pcb;
+        }
+      }
+    }
+  } else
+#endif /* LWIP_DHCP */
+  {
+    prev = NULL;
+    local_match = 0;
+    uncon_pcb = NULL;
+    /* Iterate through the UDP pcb list for a matching pcb.
+     * 'Perfect match' pcbs (connected to the remote port & ip address) are
+     * preferred. If no perfect match is found, the first unconnected pcb that
+     * matches the local port and ip address gets the datagram. */
+    for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
+      local_match = 0;
+      /* print the PCB local and remote address */
+      LWIP_DEBUGF(UDP_DEBUG,
+                  ("pcb (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") --- "
+                   "(%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n",
+                   ip4_addr1(&pcb->local_ip), ip4_addr2(&pcb->local_ip),
+                   ip4_addr3(&pcb->local_ip), ip4_addr4(&pcb->local_ip), pcb->local_port,
+                   ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+                   ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip), pcb->remote_port));
+
+      /* compare PCB local addr+port to UDP destination addr+port */
+      if ((pcb->local_port == dest) &&
+          ((!broadcast && ip_addr_isany(&pcb->local_ip)) ||
+           ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest)) ||
+#if LWIP_IGMP
+           ip_addr_ismulticast(&(iphdr->dest)) ||
+#endif /* LWIP_IGMP */
+#if IP_SOF_BROADCAST_RECV
+           (broadcast && (pcb->so_options & SOF_BROADCAST)))) {
+#else  /* IP_SOF_BROADCAST_RECV */
+           (broadcast))) {
+#endif /* IP_SOF_BROADCAST_RECV */
+        local_match = 1;
+        if ((uncon_pcb == NULL) && 
+            ((pcb->flags & UDP_FLAGS_CONNECTED) == 0)) {
+          /* the first unconnected matching PCB */
+          uncon_pcb = pcb;
+        }
+      }
+      /* compare PCB remote addr+port to UDP source addr+port */
+      if ((local_match != 0) &&
+          (pcb->remote_port == src) &&
+          (ip_addr_isany(&pcb->remote_ip) ||
+           ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)))) {
+        /* the first fully matching PCB */
+        if (prev != NULL) {
+          /* move the pcb to the front of udp_pcbs so that is
+             found faster next time */
+          prev->next = pcb->next;
+          pcb->next = udp_pcbs;
+          udp_pcbs = pcb;
+        } else {
+          UDP_STATS_INC(udp.cachehit);
+        }
+        break;
+      }
+      prev = pcb;
+    }
+    /* no fully matching pcb found? then look for an unconnected pcb */
+    if (pcb == NULL) {
+      pcb = uncon_pcb;
+    }
+  }
+
+  /* Check checksum if this is a match or if it was directed at us. */
+  if (pcb != NULL || ip_addr_cmp(&inp->ip_addr, &iphdr->dest)) {
+    LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_input: calculating checksum\n"));
+#if LWIP_UDPLITE
+    if (IPH_PROTO(iphdr) == IP_PROTO_UDPLITE) {
+      /* Do the UDP Lite checksum */
+#if CHECKSUM_CHECK_UDP
+      u16_t chklen = ntohs(udphdr->len);
+      if (chklen < sizeof(struct udp_hdr)) {
+        if (chklen == 0) {
+          /* For UDP-Lite, checksum length of 0 means checksum
+             over the complete packet (See RFC 3828 chap. 3.1) */
+          chklen = p->tot_len;
+        } else {
+          /* At least the UDP-Lite header must be covered by the
+             checksum! (Again, see RFC 3828 chap. 3.1) */
+          UDP_STATS_INC(udp.chkerr);
+          UDP_STATS_INC(udp.drop);
+          snmp_inc_udpinerrors();
+          pbuf_free(p);
+          goto end;
+        }
+      }
+      if (inet_chksum_pseudo_partial(p, (struct ip_addr *)&(iphdr->src),
+                             (struct ip_addr *)&(iphdr->dest),
+                             IP_PROTO_UDPLITE, p->tot_len, chklen) != 0) {
+       LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+                   ("udp_input: UDP Lite datagram discarded due to failing checksum\n"));
+        UDP_STATS_INC(udp.chkerr);
+        UDP_STATS_INC(udp.drop);
+        snmp_inc_udpinerrors();
+        pbuf_free(p);
+        goto end;
+      }
+#endif /* CHECKSUM_CHECK_UDP */
+    } else
+#endif /* LWIP_UDPLITE */
+    {
+#if CHECKSUM_CHECK_UDP
+      if (udphdr->chksum != 0) {
+        if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
+                               (struct ip_addr *)&(iphdr->dest),
+                               IP_PROTO_UDP, p->tot_len) != 0) {
+          LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+                      ("udp_input: UDP datagram discarded due to failing checksum\n"));
+          UDP_STATS_INC(udp.chkerr);
+          UDP_STATS_INC(udp.drop);
+          snmp_inc_udpinerrors();
+          pbuf_free(p);
+          goto end;
+        }
+      }
+#endif /* CHECKSUM_CHECK_UDP */
+    }
+    if(pbuf_header(p, -UDP_HLEN)) {
+      /* Can we cope with this failing? Just assert for now */
+      LWIP_ASSERT("pbuf_header failed\n", 0);
+      UDP_STATS_INC(udp.drop);
+      snmp_inc_udpinerrors();
+      pbuf_free(p);
+      goto end;
+    }
+    if (pcb != NULL) {
+      snmp_inc_udpindatagrams();
+      /* callback */
+      if (pcb->recv != NULL) {
+        /* now the recv function is responsible for freeing p */
+        pcb->recv(pcb->recv_arg, pcb, p, &iphdr->src, src);
+      } else {
+        /* no recv function registered? then we have to free the pbuf! */
+        pbuf_free(p);
+        goto end;
+      }
+    } else {
+      LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_input: not for us.\n"));
+
+#if LWIP_ICMP
+      /* No match was found, send ICMP destination port unreachable unless
+         destination address was broadcast/multicast. */
+      if (!broadcast &&
+          !ip_addr_ismulticast(&iphdr->dest)) {
+        /* move payload pointer back to ip header */
+        pbuf_header(p, (IPH_HL(iphdr) * 4) + UDP_HLEN);
+        LWIP_ASSERT("p->payload == iphdr", (p->payload == iphdr));
+        icmp_dest_unreach(p, ICMP_DUR_PORT);
+      }
+#endif /* LWIP_ICMP */
+      UDP_STATS_INC(udp.proterr);
+      UDP_STATS_INC(udp.drop);
+      snmp_inc_udpnoports();
+      pbuf_free(p);
+    }
+  } else {
+    pbuf_free(p);
+  }
+end:
+  PERF_STOP("udp_input");
+}
+
+/**
+ * Send data using UDP.
+ *
+ * @param pcb UDP PCB used to send the data.
+ * @param p chain of pbuf's to be sent.
+ *
+ * The datagram will be sent to the current remote_ip & remote_port
+ * stored in pcb. If the pcb is not bound to a port, it will
+ * automatically be bound to a random port.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_MEM. Out of memory.
+ * - ERR_RTE. Could not find route to destination address.
+ * - More errors could be returned by lower protocol layers.
+ *
+ * @see udp_disconnect() udp_sendto()
+ */
+err_t
+udp_send(struct udp_pcb *pcb, struct pbuf *p)
+{
+  /* send to the packet using remote ip and port stored in the pcb */
+  return udp_sendto(pcb, p, &pcb->remote_ip, pcb->remote_port);
+}
+
+/**
+ * Send data to a specified address using UDP.
+ *
+ * @param pcb UDP PCB used to send the data.
+ * @param p chain of pbuf's to be sent.
+ * @param dst_ip Destination IP address.
+ * @param dst_port Destination UDP port.
+ *
+ * dst_ip & dst_port are expected to be in the same byte order as in the pcb.
+ *
+ * If the PCB already has a remote address association, it will
+ * be restored after the data is sent.
+ * 
+ * @return lwIP error code (@see udp_send for possible error codes)
+ *
+ * @see udp_disconnect() udp_send()
+ */
+err_t
+udp_sendto(struct udp_pcb *pcb, struct pbuf *p,
+  struct ip_addr *dst_ip, u16_t dst_port)
+{
+  struct netif *netif;
+
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_send\n"));
+
+  /* find the outgoing network interface for this packet */
+#if LWIP_IGMP
+  netif = ip_route((ip_addr_ismulticast(dst_ip))?(&(pcb->multicast_ip)):(dst_ip));
+#else
+  netif = ip_route(dst_ip);
+#endif /* LWIP_IGMP */
+
+  /* no outgoing network interface could be found? */
+  if (netif == NULL) {
+    LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: No route to 0x%"X32_F"\n", dst_ip->addr));
+    UDP_STATS_INC(udp.rterr);
+    return ERR_RTE;
+  }
+  return udp_sendto_if(pcb, p, dst_ip, dst_port, netif);
+}
+
+/**
+ * Send data to a specified address using UDP.
+ * The netif used for sending can be specified.
+ *
+ * This function exists mainly for DHCP, to be able to send UDP packets
+ * on a netif that is still down.
+ *
+ * @param pcb UDP PCB used to send the data.
+ * @param p chain of pbuf's to be sent.
+ * @param dst_ip Destination IP address.
+ * @param dst_port Destination UDP port.
+ * @param netif the netif used for sending.
+ *
+ * dst_ip & dst_port are expected to be in the same byte order as in the pcb.
+ *
+ * @return lwIP error code (@see udp_send for possible error codes)
+ *
+ * @see udp_disconnect() udp_send()
+ */
+err_t
+udp_sendto_if(struct udp_pcb *pcb, struct pbuf *p,
+  struct ip_addr *dst_ip, u16_t dst_port, struct netif *netif)
+{
+  struct udp_hdr *udphdr;
+  struct ip_addr *src_ip;
+  err_t err;
+  struct pbuf *q; /* q will be sent down the stack */
+
+#if IP_SOF_BROADCAST
+  /* broadcast filter? */
+  if ( ((pcb->so_options & SOF_BROADCAST) == 0) && ip_addr_isbroadcast(dst_ip, netif) ) {
+    LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+      ("udp_sendto_if: SOF_BROADCAST not enabled on pcb %p\n", (void *)pcb));
+    return ERR_VAL;
+  }
+#endif /* IP_SOF_BROADCAST */
+
+  /* if the PCB is not yet bound to a port, bind it here */
+  if (pcb->local_port == 0) {
+    LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_send: not yet bound to a port, binding now\n"));
+    err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
+    if (err != ERR_OK) {
+      LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: forced port bind failed\n"));
+      return err;
+    }
+  }
+
+  /* not enough space to add an UDP header to first pbuf in given p chain? */
+  if (pbuf_header(p, UDP_HLEN)) {
+    /* allocate header in a separate new pbuf */
+    q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM);
+    /* new header pbuf could not be allocated? */
+    if (q == NULL) {
+      LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: could not allocate header\n"));
+      return ERR_MEM;
+    }
+    /* chain header q in front of given pbuf p */
+    pbuf_chain(q, p);
+    /* first pbuf q points to header pbuf */
+    LWIP_DEBUGF(UDP_DEBUG,
+                ("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
+  } else {
+    /* adding space for header within p succeeded */
+    /* first pbuf q equals given pbuf */
+    q = p;
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p));
+  }
+  LWIP_ASSERT("check that first pbuf can hold struct udp_hdr",
+              (q->len >= sizeof(struct udp_hdr)));
+  /* q now represents the packet to be sent */
+  udphdr = q->payload;
+  udphdr->src = htons(pcb->local_port);
+  udphdr->dest = htons(dst_port);
+  /* in UDP, 0 checksum means 'no checksum' */
+  udphdr->chksum = 0x0000; 
+
+  /* PCB local address is IP_ANY_ADDR? */
+  if (ip_addr_isany(&pcb->local_ip)) {
+    /* use outgoing network interface IP address as source address */
+    src_ip = &(netif->ip_addr);
+  } else {
+    /* check if UDP PCB local IP address is correct
+     * this could be an old address if netif->ip_addr has changed */
+    if (!ip_addr_cmp(&(pcb->local_ip), &(netif->ip_addr))) {
+      /* local_ip doesn't match, drop the packet */
+      if (q != p) {
+        /* free the header pbuf */
+        pbuf_free(q);
+        q = NULL;
+        /* p is still referenced by the caller, and will live on */
+      }
+      return ERR_VAL;
+    }
+    /* use UDP PCB local IP address as source address */
+    src_ip = &(pcb->local_ip);
+  }
+
+  LWIP_DEBUGF(UDP_DEBUG, ("udp_send: sending datagram of length %"U16_F"\n", q->tot_len));
+
+#if LWIP_UDPLITE
+  /* UDP Lite protocol? */
+  if (pcb->flags & UDP_FLAGS_UDPLITE) {
+    u16_t chklen, chklen_hdr;
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE packet length %"U16_F"\n", q->tot_len));
+    /* set UDP message length in UDP header */
+    chklen_hdr = chklen = pcb->chksum_len_tx;
+    if ((chklen < sizeof(struct udp_hdr)) || (chklen > q->tot_len)) {
+      if (chklen != 0) {
+        LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE pcb->chksum_len is illegal: %"U16_F"\n", chklen));
+      }
+      /* For UDP-Lite, checksum length of 0 means checksum
+         over the complete packet. (See RFC 3828 chap. 3.1)
+         At least the UDP-Lite header must be covered by the
+         checksum, therefore, if chksum_len has an illegal
+         value, we generate the checksum over the complete
+         packet to be safe. */
+      chklen_hdr = 0;
+      chklen = q->tot_len;
+    }
+    udphdr->len = htons(chklen_hdr);
+    /* calculate checksum */
+#if CHECKSUM_GEN_UDP
+    udphdr->chksum = inet_chksum_pseudo_partial(q, src_ip, dst_ip,
+                                        IP_PROTO_UDPLITE, q->tot_len, chklen);
+    /* chksum zero must become 0xffff, as zero means 'no checksum' */
+    if (udphdr->chksum == 0x0000)
+      udphdr->chksum = 0xffff;
+#endif /* CHECKSUM_CHECK_UDP */
+    /* output to IP */
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDPLITE,)\n"));
+#if LWIP_NETIF_HWADDRHINT
+    netif->addr_hint = &(pcb->addr_hint);
+#endif /* LWIP_NETIF_HWADDRHINT*/
+    err = ip_output_if(q, src_ip, dst_ip, pcb->ttl, pcb->tos, IP_PROTO_UDPLITE, netif);
+#if LWIP_NETIF_HWADDRHINT
+    netif->addr_hint = NULL;
+#endif /* LWIP_NETIF_HWADDRHINT*/
+  } else
+#endif /* LWIP_UDPLITE */
+  {      /* UDP */
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %"U16_F"\n", q->tot_len));
+    udphdr->len = htons(q->tot_len);
+    /* calculate checksum */
+#if CHECKSUM_GEN_UDP
+    if ((pcb->flags & UDP_FLAGS_NOCHKSUM) == 0) {
+      udphdr->chksum = inet_chksum_pseudo(q, src_ip, dst_ip, IP_PROTO_UDP, q->tot_len);
+      /* chksum zero must become 0xffff, as zero means 'no checksum' */
+      if (udphdr->chksum == 0x0000) udphdr->chksum = 0xffff;
+    }
+#endif /* CHECKSUM_CHECK_UDP */
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04"X16_F"\n", udphdr->chksum));
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDP,)\n"));
+    /* output to IP */
+#if LWIP_NETIF_HWADDRHINT
+    netif->addr_hint = &(pcb->addr_hint);
+#endif /* LWIP_NETIF_HWADDRHINT*/
+    err = ip_output_if(q, src_ip, dst_ip, pcb->ttl, pcb->tos, IP_PROTO_UDP, netif);
+#if LWIP_NETIF_HWADDRHINT
+    netif->addr_hint = NULL;
+#endif /* LWIP_NETIF_HWADDRHINT*/
+  }
+  /* TODO: must this be increased even if error occured? */
+  snmp_inc_udpoutdatagrams();
+
+  /* did we chain a separate header pbuf earlier? */
+  if (q != p) {
+    /* free the header pbuf */
+    pbuf_free(q);
+    q = NULL;
+    /* p is still referenced by the caller, and will live on */
+  }
+
+  UDP_STATS_INC(udp.xmit);
+  return err;
+}
+
+/**
+ * Bind an UDP PCB.
+ *
+ * @param pcb UDP PCB to be bound with a local address ipaddr and port.
+ * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to
+ * bind to all local interfaces.
+ * @param port local UDP port to bind with. Use 0 to automatically bind
+ * to a random port between UDP_LOCAL_PORT_RANGE_START and
+ * UDP_LOCAL_PORT_RANGE_END.
+ *
+ * ipaddr & port are expected to be in the same byte order as in the pcb.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_USE. The specified ipaddr and port are already bound to by
+ * another UDP PCB.
+ *
+ * @see udp_disconnect()
+ */
+err_t
+udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
+{
+  struct udp_pcb *ipcb;
+  u8_t rebind;
+
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_bind(ipaddr = "));
+  ip_addr_debug_print(UDP_DEBUG, ipaddr);
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, (", port = %"U16_F")\n", port));
+
+  rebind = 0;
+  /* Check for double bind and rebind of the same pcb */
+  for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+    /* is this UDP PCB already on active list? */
+    if (pcb == ipcb) {
+      /* pcb may occur at most once in active list */
+      LWIP_ASSERT("rebind == 0", rebind == 0);
+      /* pcb already in list, just rebind */
+      rebind = 1;
+    }
+
+    /* this code does not allow upper layer to share a UDP port for
+       listening to broadcast or multicast traffic (See SO_REUSE_ADDR and
+       SO_REUSE_PORT under *BSD). TODO: See where it fits instead, OR
+       combine with implementation of UDP PCB flags. Leon Woestenberg. */
+#ifdef LWIP_UDP_TODO
+    /* port matches that of PCB in list? */
+    else
+      if ((ipcb->local_port == port) &&
+          /* IP address matches, or one is IP_ADDR_ANY? */
+          (ip_addr_isany(&(ipcb->local_ip)) ||
+           ip_addr_isany(ipaddr) ||
+           ip_addr_cmp(&(ipcb->local_ip), ipaddr))) {
+        /* other PCB already binds to this local IP and port */
+        LWIP_DEBUGF(UDP_DEBUG,
+                    ("udp_bind: local port %"U16_F" already bound by another pcb\n", port));
+        return ERR_USE;
+      }
+#endif
+  }
+
+  ip_addr_set(&pcb->local_ip, ipaddr);
+
+  /* no port specified? */
+  if (port == 0) {
+#ifndef UDP_LOCAL_PORT_RANGE_START
+#define UDP_LOCAL_PORT_RANGE_START 4096
+#define UDP_LOCAL_PORT_RANGE_END   0x7fff
+#endif
+    port = UDP_LOCAL_PORT_RANGE_START;
+    ipcb = udp_pcbs;
+    while ((ipcb != NULL) && (port != UDP_LOCAL_PORT_RANGE_END)) {
+      if (ipcb->local_port == port) {
+        /* port is already used by another udp_pcb */
+        port++;
+        /* restart scanning all udp pcbs */
+        ipcb = udp_pcbs;
+      } else
+        /* go on with next udp pcb */
+        ipcb = ipcb->next;
+    }
+    if (ipcb != NULL) {
+      /* no more ports available in local range */
+      LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n"));
+      return ERR_USE;
+    }
+  }
+  pcb->local_port = port;
+  snmp_insert_udpidx_tree(pcb);
+  /* pcb not active yet? */
+  if (rebind == 0) {
+    /* place the PCB on the active list if not already there */
+    pcb->next = udp_pcbs;
+    udp_pcbs = pcb;
+  }
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+              ("udp_bind: bound to %"U16_F".%"U16_F".%"U16_F".%"U16_F", port %"U16_F"\n",
+               (u16_t)((ntohl(pcb->local_ip.addr) >> 24) & 0xff),
+               (u16_t)((ntohl(pcb->local_ip.addr) >> 16) & 0xff),
+               (u16_t)((ntohl(pcb->local_ip.addr) >> 8) & 0xff),
+               (u16_t)(ntohl(pcb->local_ip.addr) & 0xff), pcb->local_port));
+  return ERR_OK;
+}
+/**
+ * Connect an UDP PCB.
+ *
+ * This will associate the UDP PCB with the remote address.
+ *
+ * @param pcb UDP PCB to be connected with remote address ipaddr and port.
+ * @param ipaddr remote IP address to connect with.
+ * @param port remote UDP port to connect with.
+ *
+ * @return lwIP error code
+ *
+ * ipaddr & port are expected to be in the same byte order as in the pcb.
+ *
+ * The udp pcb is bound to a random local port if not already bound.
+ *
+ * @see udp_disconnect()
+ */
+err_t
+udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
+{
+  struct udp_pcb *ipcb;
+
+  if (pcb->local_port == 0) {
+    err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
+    if (err != ERR_OK)
+      return err;
+  }
+
+  ip_addr_set(&pcb->remote_ip, ipaddr);
+  pcb->remote_port = port;
+  pcb->flags |= UDP_FLAGS_CONNECTED;
+/** TODO: this functionality belongs in upper layers */
+#ifdef LWIP_UDP_TODO
+  /* Nail down local IP for netconn_addr()/getsockname() */
+  if (ip_addr_isany(&pcb->local_ip) && !ip_addr_isany(&pcb->remote_ip)) {
+    struct netif *netif;
+
+    if ((netif = ip_route(&(pcb->remote_ip))) == NULL) {
+      LWIP_DEBUGF(UDP_DEBUG, ("udp_connect: No route to 0x%lx\n", pcb->remote_ip.addr));
+      UDP_STATS_INC(udp.rterr);
+      return ERR_RTE;
+    }
+    /** TODO: this will bind the udp pcb locally, to the interface which
+        is used to route output packets to the remote address. However, we
+        might want to accept incoming packets on any interface! */
+    pcb->local_ip = netif->ip_addr;
+  } else if (ip_addr_isany(&pcb->remote_ip)) {
+    pcb->local_ip.addr = 0;
+  }
+#endif
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+              ("udp_connect: connected to %"U16_F".%"U16_F".%"U16_F".%"U16_F",port %"U16_F"\n",
+               (u16_t)((ntohl(pcb->remote_ip.addr) >> 24) & 0xff),
+               (u16_t)((ntohl(pcb->remote_ip.addr) >> 16) & 0xff),
+               (u16_t)((ntohl(pcb->remote_ip.addr) >> 8) & 0xff),
+               (u16_t)(ntohl(pcb->remote_ip.addr) & 0xff), pcb->remote_port));
+
+  /* Insert UDP PCB into the list of active UDP PCBs. */
+  for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+    if (pcb == ipcb) {
+      /* already on the list, just return */
+      return ERR_OK;
+    }
+  }
+  /* PCB not yet on the list, add PCB now */
+  pcb->next = udp_pcbs;
+  udp_pcbs = pcb;
+  return ERR_OK;
+}
+
+/**
+ * Disconnect a UDP PCB
+ *
+ * @param pcb the udp pcb to disconnect.
+ */
+void
+udp_disconnect(struct udp_pcb *pcb)
+{
+  /* reset remote address association */
+  ip_addr_set(&pcb->remote_ip, IP_ADDR_ANY);
+  pcb->remote_port = 0;
+  /* mark PCB as unconnected */
+  pcb->flags &= ~UDP_FLAGS_CONNECTED;
+}
+
+/**
+ * Set a receive callback for a UDP PCB
+ *
+ * This callback will be called when receiving a datagram for the pcb.
+ *
+ * @param pcb the pcb for wich to set the recv callback
+ * @param recv function pointer of the callback function
+ * @param recv_arg additional argument to pass to the callback function
+ */
+void
+udp_recv(struct udp_pcb *pcb,
+         void (* recv)(void *arg, struct udp_pcb *upcb, struct pbuf *p,
+                       struct ip_addr *addr, u16_t port),
+         void *recv_arg)
+{
+  /* remember recv() callback and user data */
+  pcb->recv = recv;
+  pcb->recv_arg = recv_arg;
+}
+
+/**
+ * Remove an UDP PCB.
+ *
+ * @param pcb UDP PCB to be removed. The PCB is removed from the list of
+ * UDP PCB's and the data structure is freed from memory.
+ *
+ * @see udp_new()
+ */
+void
+udp_remove(struct udp_pcb *pcb)
+{
+  struct udp_pcb *pcb2;
+
+  snmp_delete_udpidx_tree(pcb);
+  /* pcb to be removed is first in list? */
+  if (udp_pcbs == pcb) {
+    /* make list start at 2nd pcb */
+    udp_pcbs = udp_pcbs->next;
+    /* pcb not 1st in list */
+  } else
+    for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
+      /* find pcb in udp_pcbs list */
+      if (pcb2->next != NULL && pcb2->next == pcb) {
+        /* remove pcb from list */
+        pcb2->next = pcb->next;
+      }
+    }
+  memp_free(MEMP_UDP_PCB, pcb);
+}
+
+/**
+ * Create a UDP PCB.
+ *
+ * @return The UDP PCB which was created. NULL if the PCB data structure
+ * could not be allocated.
+ *
+ * @see udp_remove()
+ */
+struct udp_pcb *
+udp_new(void)
+{
+  struct udp_pcb *pcb;
+  pcb = memp_malloc(MEMP_UDP_PCB);
+  /* could allocate UDP PCB? */
+  if (pcb != NULL) {
+    /* UDP Lite: by initializing to all zeroes, chksum_len is set to 0
+     * which means checksum is generated over the whole datagram per default
+     * (recommended as default by RFC 3828). */
+    /* initialize PCB to all zeroes */
+    memset(pcb, 0, sizeof(struct udp_pcb));
+    pcb->ttl = UDP_TTL;
+  }
+  return pcb;
+}
+
+#if UDP_DEBUG
+/**
+ * Print UDP header information for debug purposes.
+ *
+ * @param udphdr pointer to the udp header in memory.
+ */
+void
+udp_debug_print(struct udp_hdr *udphdr)
+{
+  LWIP_DEBUGF(UDP_DEBUG, ("UDP header:\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("|     %5"U16_F"     |     %5"U16_F"     | (src port, dest port)\n",
+                          ntohs(udphdr->src), ntohs(udphdr->dest)));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("|     %5"U16_F"     |     0x%04"X16_F"    | (len, chksum)\n",
+                          ntohs(udphdr->len), ntohs(udphdr->chksum)));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+}
+#endif /* UDP_DEBUG */
+
+#endif /* LWIP_UDP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/autoip.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/autoip.h
new file mode 100644
index 0000000..f262165
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/autoip.h
@@ -0,0 +1,116 @@
+/**
+ * @file
+ *
+ * AutoIP Automatic LinkLocal IP Configuration
+ */
+
+/*
+ *
+ * Copyright (c) 2007 Dominik Spies 
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Dominik Spies 
+ *
+ * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform
+ * with RFC 3927.
+ *
+ *
+ * Please coordinate changes and requests with Dominik Spies
+ * 
+ */
+ 
+#ifndef __LWIP_AUTOIP_H__
+#define __LWIP_AUTOIP_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_AUTOIP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+#include "netif/etharp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* AutoIP Timing */
+#define AUTOIP_TMR_INTERVAL      100
+#define AUTOIP_TICKS_PER_SECOND (1000 / AUTOIP_TMR_INTERVAL)
+
+/* RFC 3927 Constants */
+#define PROBE_WAIT               1   /* second   (initial random delay)                 */
+#define PROBE_MIN                1   /* second   (minimum delay till repeated probe)    */
+#define PROBE_MAX                2   /* seconds  (maximum delay till repeated probe)    */
+#define PROBE_NUM                3   /*          (number of probe packets)              */
+#define ANNOUNCE_NUM             2   /*          (number of announcement packets)       */
+#define ANNOUNCE_INTERVAL        2   /* seconds  (time between announcement packets)    */
+#define ANNOUNCE_WAIT            2   /* seconds  (delay before announcing)              */
+#define MAX_CONFLICTS            10  /*          (max conflicts before rate limiting)   */
+#define RATE_LIMIT_INTERVAL      60  /* seconds  (delay between successive attempts)    */
+#define DEFEND_INTERVAL          10  /* seconds  (min. wait between defensive ARPs)     */
+
+/* AutoIP client states */
+#define AUTOIP_STATE_OFF         0
+#define AUTOIP_STATE_PROBING     1
+#define AUTOIP_STATE_ANNOUNCING  2
+#define AUTOIP_STATE_BOUND       3
+
+struct autoip
+{
+  struct ip_addr llipaddr;  /* the currently selected, probed, announced or used LL IP-Address */
+  u8_t state;               /* current AutoIP state machine state */
+  u8_t sent_num;            /* sent number of probes or announces, dependent on state */
+  u16_t ttw;                /* ticks to wait, tick is AUTOIP_TMR_INTERVAL long */
+  u8_t lastconflict;        /* ticks until a conflict can be solved by defending */
+  u8_t tried_llipaddr;      /* total number of probed/used Link Local IP-Addresses */
+};
+
+
+/** Init srand, has to be called before entering mainloop */
+void autoip_init(void);
+
+/** Start AutoIP client */
+err_t autoip_start(struct netif *netif);
+
+/** Stop AutoIP client */
+err_t autoip_stop(struct netif *netif);
+
+/** Handles every incoming ARP Packet, called by etharp_arp_input */
+void autoip_arp_reply(struct netif *netif, struct etharp_hdr *hdr);
+
+/** Has to be called in loop every AUTOIP_TMR_INTERVAL milliseconds */
+void autoip_tmr(void);
+
+/** Handle a possible change in the network configuration */
+void autoip_network_changed(struct netif *netif);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_AUTOIP */
+
+#endif /* __LWIP_AUTOIP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/icmp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/icmp.h
new file mode 100644
index 0000000..c73961c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/icmp.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ICMP_H__
+#define __LWIP_ICMP_H__
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ICMP_ER 0      /* echo reply */
+#define ICMP_DUR 3     /* destination unreachable */
+#define ICMP_SQ 4      /* source quench */
+#define ICMP_RD 5      /* redirect */
+#define ICMP_ECHO 8    /* echo */
+#define ICMP_TE 11     /* time exceeded */
+#define ICMP_PP 12     /* parameter problem */
+#define ICMP_TS 13     /* timestamp */
+#define ICMP_TSR 14    /* timestamp reply */
+#define ICMP_IRQ 15    /* information request */
+#define ICMP_IR 16     /* information reply */
+
+enum icmp_dur_type {
+  ICMP_DUR_NET = 0,    /* net unreachable */
+  ICMP_DUR_HOST = 1,   /* host unreachable */
+  ICMP_DUR_PROTO = 2,  /* protocol unreachable */
+  ICMP_DUR_PORT = 3,   /* port unreachable */
+  ICMP_DUR_FRAG = 4,   /* fragmentation needed and DF set */
+  ICMP_DUR_SR = 5      /* source route failed */
+};
+
+enum icmp_te_type {
+  ICMP_TE_TTL = 0,     /* time to live exceeded in transit */
+  ICMP_TE_FRAG = 1     /* fragment reassembly time exceeded */
+};
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+/** This is the standard ICMP header only that the u32_t data
+ *  is splitted to two u16_t like ICMP echo needs it.
+ *  This header is also used for other ICMP types that do not
+ *  use the data part.
+ */
+PACK_STRUCT_BEGIN
+struct icmp_echo_hdr {
+  PACK_STRUCT_FIELD(u8_t type);
+  PACK_STRUCT_FIELD(u8_t code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u16_t id);
+  PACK_STRUCT_FIELD(u16_t seqno);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define ICMPH_TYPE(hdr) ((hdr)->type)
+#define ICMPH_CODE(hdr) ((hdr)->code)
+
+/** Combines type and code to an u16_t */
+#define ICMPH_TYPE_SET(hdr, t) ((hdr)->type = (t))
+#define ICMPH_CODE_SET(hdr, c) ((hdr)->code = (c))
+
+
+#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */
+
+void icmp_input(struct pbuf *p, struct netif *inp);
+void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
+void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
+
+#endif /* LWIP_ICMP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_ICMP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/igmp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/igmp.h
new file mode 100644
index 0000000..59c933f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/igmp.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2002 CITEL Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS''
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is a contribution to the lwIP TCP/IP stack.
+ * The Swedish Institute of Computer Science and Adam Dunkels
+ * are specifically granted permission to redistribute this
+ * source code.
+*/
+
+#ifndef __LWIP_IGMP_H__
+#define __LWIP_IGMP_H__
+
+#include "lwip/opt.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/pbuf.h"
+
+#if LWIP_IGMP /* don't build if not configured for use in lwipopts.h */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* 
+ * IGMP constants
+ */
+#define IP_PROTO_IGMP                  2
+#define IGMP_TTL                       1
+#define IGMP_MINLEN                    8
+#define ROUTER_ALERT                   0x9404
+#define ROUTER_ALERTLEN                4
+
+/*
+ * IGMP message types, including version number.
+ */
+#define IGMP_MEMB_QUERY                0x11 /* Membership query         */
+#define IGMP_V1_MEMB_REPORT            0x12 /* Ver. 1 membership report */
+#define IGMP_V2_MEMB_REPORT            0x16 /* Ver. 2 membership report */
+#define IGMP_LEAVE_GROUP               0x17 /* Leave-group message      */
+
+/* IGMP timer */
+#define IGMP_TMR_INTERVAL              100 /* Milliseconds */
+#define IGMP_V1_DELAYING_MEMBER_TMR   (1000/IGMP_TMR_INTERVAL)
+#define IGMP_JOIN_DELAYING_MEMBER_TMR (500 /IGMP_TMR_INTERVAL)
+
+/* MAC Filter Actions */
+#define IGMP_DEL_MAC_FILTER            0
+#define IGMP_ADD_MAC_FILTER            1
+
+/* Group  membership states */
+#define IGMP_GROUP_NON_MEMBER          0
+#define IGMP_GROUP_DELAYING_MEMBER     1
+#define IGMP_GROUP_IDLE_MEMBER         2
+
+/*
+ * IGMP packet format.
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct igmp_msg {
+ PACK_STRUCT_FIELD(u8_t           igmp_msgtype);
+ PACK_STRUCT_FIELD(u8_t           igmp_maxresp);
+ PACK_STRUCT_FIELD(u16_t          igmp_checksum);
+ PACK_STRUCT_FIELD(struct ip_addr igmp_group_address);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/* 
+ * now a group structure - there is
+ * a list of groups for each interface
+ * these should really be linked from the interface, but
+ * if we keep them separate we will not affect the lwip original code
+ * too much
+ * 
+ * There will be a group for the all systems group address but this 
+ * will not run the state machine as it is used to kick off reports
+ * from all the other groups
+ */
+
+struct igmp_group {
+  struct igmp_group *next;
+  struct netif      *interface;
+  struct ip_addr     group_address;
+  u8_t               last_reporter_flag; /* signifies we were the last person to report */
+  u8_t               group_state;
+  u16_t              timer;
+  u8_t               use; /* counter of simultaneous uses */
+};
+
+
+/*  Prototypes */
+void   igmp_init(void);
+
+err_t  igmp_start( struct netif *netif);
+
+err_t  igmp_stop( struct netif *netif);
+
+void   igmp_report_groups( struct netif *netif);
+
+struct igmp_group *igmp_lookfor_group( struct netif *ifp, struct ip_addr *addr);
+
+struct igmp_group *igmp_lookup_group( struct netif *ifp, struct ip_addr *addr);
+
+err_t  igmp_remove_group( struct igmp_group *group);
+
+void   igmp_input( struct pbuf *p, struct netif *inp, struct ip_addr *dest);
+
+err_t  igmp_joingroup( struct ip_addr *ifaddr, struct ip_addr *groupaddr);
+
+err_t  igmp_leavegroup( struct ip_addr *ifaddr, struct ip_addr *groupaddr);
+
+void   igmp_tmr(void);
+
+void   igmp_timeout( struct igmp_group *group);
+
+void   igmp_start_timer( struct igmp_group *group, u8_t max_time);
+
+void   igmp_stop_timer( struct igmp_group *group);
+
+void   igmp_delaying_member( struct igmp_group *group, u8_t maxresp);
+
+err_t  igmp_ip_output_if( struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, u8_t ttl, u8_t proto, struct netif *netif);
+
+void   igmp_send( struct igmp_group *group, u8_t type);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IGMP */
+
+#endif /* __LWIP_IGMP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/inet.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/inet.h
new file mode 100644
index 0000000..6f30d0d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/inet.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_INET_H__
+#define __LWIP_INET_H__
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* For compatibility with BSD code */
+struct in_addr {
+  u32_t s_addr;
+};
+
+#define INADDR_NONE         ((u32_t)0xffffffffUL)  /* 255.255.255.255 */
+#define INADDR_LOOPBACK     ((u32_t)0x7f000001UL)  /* 127.0.0.1 */
+#define INADDR_ANY          ((u32_t)0x00000000UL)  /* 0.0.0.0 */
+#define INADDR_BROADCAST    ((u32_t)0xffffffffUL)  /* 255.255.255.255 */
+
+u32_t inet_addr(const char *cp);
+int inet_aton(const char *cp, struct in_addr *addr);
+char *inet_ntoa(struct in_addr addr); /* returns ptr to static buffer; not reentrant! */
+
+#ifdef htons
+#undef htons
+#endif /* htons */
+#ifdef htonl
+#undef htonl
+#endif /* htonl */
+#ifdef ntohs
+#undef ntohs
+#endif /* ntohs */
+#ifdef ntohl
+#undef ntohl
+#endif /* ntohl */
+
+#ifndef LWIP_PLATFORM_BYTESWAP
+#define LWIP_PLATFORM_BYTESWAP 0
+#endif
+
+#if BYTE_ORDER == BIG_ENDIAN
+#define htons(x) (x)
+#define ntohs(x) (x)
+#define htonl(x) (x)
+#define ntohl(x) (x)
+#else /* BYTE_ORDER != BIG_ENDIAN */
+#ifdef LWIP_PREFIX_BYTEORDER_FUNCS
+/* workaround for naming collisions on some platforms */
+#define htons lwip_htons
+#define ntohs lwip_ntohs
+#define htonl lwip_htonl
+#define ntohl lwip_ntohl
+#endif /* LWIP_PREFIX_BYTEORDER_FUNCS */
+#if LWIP_PLATFORM_BYTESWAP
+#define htons(x) LWIP_PLATFORM_HTONS(x)
+#define ntohs(x) LWIP_PLATFORM_HTONS(x)
+#define htonl(x) LWIP_PLATFORM_HTONL(x)
+#define ntohl(x) LWIP_PLATFORM_HTONL(x)
+#else /* LWIP_PLATFORM_BYTESWAP */
+u16_t htons(u16_t x);
+u16_t ntohs(u16_t x);
+u32_t htonl(u32_t x);
+u32_t ntohl(u32_t x);
+#endif /* LWIP_PLATFORM_BYTESWAP */
+
+#endif /* BYTE_ORDER == BIG_ENDIAN */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_INET_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/inet_chksum.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/inet_chksum.h
new file mode 100644
index 0000000..5cae59c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/inet_chksum.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_INET_CHKSUM_H__
+#define __LWIP_INET_CHKSUM_H__
+
+#include "lwip/opt.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+u16_t inet_chksum(void *dataptr, u16_t len);
+u16_t inet_chksum_pbuf(struct pbuf *p);
+u16_t inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u16_t proto_len);
+#if LWIP_UDPLITE
+u16_t inet_chksum_pseudo_partial(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u16_t proto_len, u16_t chksum_len);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_INET_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/ip.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/ip.h
new file mode 100644
index 0000000..fd84f30
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/ip.h
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_H__
+#define __LWIP_IP_H__
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Currently, the function ip_output_if_opt() is only used with IGMP */
+#define IP_OPTIONS_SEND   LWIP_IGMP
+
+#define IP_HLEN 20
+
+#define IP_PROTO_ICMP    1
+#define IP_PROTO_UDP     17
+#define IP_PROTO_UDPLITE 136
+#define IP_PROTO_TCP     6
+
+/* This is passed as the destination address to ip_output_if (not
+   to ip_output), meaning that an IP header already is constructed
+   in the pbuf. This is used when TCP retransmits. */
+#ifdef IP_HDRINCL
+#undef IP_HDRINCL
+#endif /* IP_HDRINCL */
+#define IP_HDRINCL  NULL
+
+#if LWIP_NETIF_HWADDRHINT
+#define IP_PCB_ADDRHINT ;u8_t addr_hint
+#else
+#define IP_PCB_ADDRHINT
+#endif /* LWIP_NETIF_HWADDRHINT */
+
+/* This is the common part of all PCB types. It needs to be at the
+   beginning of a PCB type definition. It is located here so that
+   changes to this common part are made in one location instead of
+   having to change all PCB structs. */
+#define IP_PCB \
+  /* ip addresses in network byte order */ \
+  struct ip_addr local_ip; \
+  struct ip_addr remote_ip; \
+   /* Socket options */  \
+  u16_t so_options;      \
+   /* Type Of Service */ \
+  u8_t tos;              \
+  /* Time To Live */     \
+  u8_t ttl               \
+  /* link layer address resolution hint */ \
+  IP_PCB_ADDRHINT
+
+struct ip_pcb {
+/* Common members of all PCB types */
+  IP_PCB;
+};
+
+/*
+ * Option flags per-socket. These are the same like SO_XXX.
+ */
+#define SOF_DEBUG       (u16_t)0x0001U    /* turn on debugging info recording */
+#define SOF_ACCEPTCONN  (u16_t)0x0002U    /* socket has had listen() */
+#define SOF_REUSEADDR   (u16_t)0x0004U    /* allow local address reuse */
+#define SOF_KEEPALIVE   (u16_t)0x0008U    /* keep connections alive */
+#define SOF_DONTROUTE   (u16_t)0x0010U    /* just use interface addresses */
+#define SOF_BROADCAST   (u16_t)0x0020U    /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */
+#define SOF_USELOOPBACK (u16_t)0x0040U    /* bypass hardware when possible */
+#define SOF_LINGER      (u16_t)0x0080U    /* linger on close if data present */
+#define SOF_OOBINLINE   (u16_t)0x0100U    /* leave received OOB data in line */
+#define SOF_REUSEPORT   (u16_t)0x0200U    /* allow local address & port reuse */
+
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_hdr {
+  /* version / header length / type of service */
+  PACK_STRUCT_FIELD(u16_t _v_hl_tos);
+  /* total length */
+  PACK_STRUCT_FIELD(u16_t _len);
+  /* identification */
+  PACK_STRUCT_FIELD(u16_t _id);
+  /* fragment offset field */
+  PACK_STRUCT_FIELD(u16_t _offset);
+#define IP_RF 0x8000        /* reserved fragment flag */
+#define IP_DF 0x4000        /* dont fragment flag */
+#define IP_MF 0x2000        /* more fragments flag */
+#define IP_OFFMASK 0x1fff   /* mask for fragmenting bits */
+  /* time to live / protocol*/
+  PACK_STRUCT_FIELD(u16_t _ttl_proto);
+  /* checksum */
+  PACK_STRUCT_FIELD(u16_t _chksum);
+  /* source and destination IP addresses */
+  PACK_STRUCT_FIELD(struct ip_addr src);
+  PACK_STRUCT_FIELD(struct ip_addr dest); 
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define IPH_V(hdr)  (ntohs((hdr)->_v_hl_tos) >> 12)
+#define IPH_HL(hdr) ((ntohs((hdr)->_v_hl_tos) >> 8) & 0x0f)
+#define IPH_TOS(hdr) (ntohs((hdr)->_v_hl_tos) & 0xff)
+#define IPH_LEN(hdr) ((hdr)->_len)
+#define IPH_ID(hdr) ((hdr)->_id)
+#define IPH_OFFSET(hdr) ((hdr)->_offset)
+#define IPH_TTL(hdr) (ntohs((hdr)->_ttl_proto) >> 8)
+#define IPH_PROTO(hdr) (ntohs((hdr)->_ttl_proto) & 0xff)
+#define IPH_CHKSUM(hdr) ((hdr)->_chksum)
+
+#define IPH_VHLTOS_SET(hdr, v, hl, tos) (hdr)->_v_hl_tos = (htons(((v) << 12) | ((hl) << 8) | (tos)))
+#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len)
+#define IPH_ID_SET(hdr, id) (hdr)->_id = (id)
+#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off)
+#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl_proto = (htons(IPH_PROTO(hdr) | ((u16_t)(ttl) << 8)))
+#define IPH_PROTO_SET(hdr, proto) (hdr)->_ttl_proto = (htons((proto) | (IPH_TTL(hdr) << 8)))
+#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum)
+
+/** The interface that provided the packet for the current callback invocation. */
+extern struct netif *current_netif;
+/** Header of the input packet currently being processed. */
+extern const struct ip_hdr *current_header;
+
+#define ip_init() /* Compatibility define, not init needed. */
+struct netif *ip_route(struct ip_addr *dest);
+err_t ip_input(struct pbuf *p, struct netif *inp);
+err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+       u8_t ttl, u8_t tos, u8_t proto);
+err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+       u8_t ttl, u8_t tos, u8_t proto,
+       struct netif *netif);
+#if LWIP_NETIF_HWADDRHINT
+err_t ip_output_hinted(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+       u8_t ttl, u8_t tos, u8_t proto, u8_t *addr_hint);
+#endif /* LWIP_NETIF_HWADDRHINT */
+#if IP_OPTIONS_SEND
+err_t ip_output_if_opt(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+       u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options,
+       u16_t optlen);
+#endif /* IP_OPTIONS_SEND */
+/** Get the interface that received the current packet.
+ * This function must only be called from a receive callback (udp_recv,
+ * raw_recv, tcp_accept). It will return NULL otherwise. */
+#define ip_current_netif()  (current_netif)
+/** Get the IP header of the current packet.
+ * This function must only be called from a receive callback (udp_recv,
+ * raw_recv, tcp_accept). It will return NULL otherwise. */
+#define ip_current_header() (current_header)
+#if IP_DEBUG
+void ip_debug_print(struct pbuf *p);
+#else
+#define ip_debug_print(p)
+#endif /* IP_DEBUG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_IP_H__ */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/ip_addr.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/ip_addr.h
new file mode 100644
index 0000000..298e657
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/ip_addr.h
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_ADDR_H__
+#define __LWIP_IP_ADDR_H__
+
+#include "lwip/opt.h"
+
+#include "lwip/inet.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_addr {
+  PACK_STRUCT_FIELD(u32_t addr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/*
+ * struct ipaddr2 is used in the definition of the ARP packet format in
+ * order to support compilers that don't have structure packing.
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_addr2 {
+  PACK_STRUCT_FIELD(u16_t addrw[2]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+struct netif;
+
+extern const struct ip_addr ip_addr_any;
+extern const struct ip_addr ip_addr_broadcast;
+
+/** IP_ADDR_ can be used as a fixed IP address
+ *  for the wildcard and the broadcast address
+ */
+#define IP_ADDR_ANY         ((struct ip_addr *)&ip_addr_any)
+#define IP_ADDR_BROADCAST   ((struct ip_addr *)&ip_addr_broadcast)
+
+/* Definitions of the bits in an Internet address integer.
+
+   On subnets, host and network parts are found according to
+   the subnet mask, not these masks.  */
+
+#define IN_CLASSA(a)        ((((u32_t)(a)) & 0x80000000UL) == 0)
+#define IN_CLASSA_NET       0xff000000
+#define IN_CLASSA_NSHIFT    24
+#define IN_CLASSA_HOST      (0xffffffff & ~IN_CLASSA_NET)
+#define IN_CLASSA_MAX       128
+
+#define IN_CLASSB(a)        ((((u32_t)(a)) & 0xc0000000UL) == 0x80000000UL)
+#define IN_CLASSB_NET       0xffff0000
+#define IN_CLASSB_NSHIFT    16
+#define IN_CLASSB_HOST      (0xffffffff & ~IN_CLASSB_NET)
+#define IN_CLASSB_MAX       65536
+
+#define IN_CLASSC(a)        ((((u32_t)(a)) & 0xe0000000UL) == 0xc0000000UL)
+#define IN_CLASSC_NET       0xffffff00
+#define IN_CLASSC_NSHIFT    8
+#define IN_CLASSC_HOST      (0xffffffff & ~IN_CLASSC_NET)
+
+#define IN_CLASSD(a)        (((u32_t)(a) & 0xf0000000UL) == 0xe0000000UL)
+#define IN_CLASSD_NET       0xf0000000          /* These ones aren't really */
+#define IN_CLASSD_NSHIFT    28                  /*   net and host fields, but */
+#define IN_CLASSD_HOST      0x0fffffff          /*   routing needn't know. */
+#define IN_MULTICAST(a)     IN_CLASSD(a)
+
+#define IN_EXPERIMENTAL(a)  (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL)
+#define IN_BADCLASS(a)      (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL)
+
+#define IN_LOOPBACKNET      127                 /* official! */
+
+#define IP4_ADDR(ipaddr, a,b,c,d) \
+        (ipaddr)->addr = htonl(((u32_t)((a) & 0xff) << 24) | \
+                               ((u32_t)((b) & 0xff) << 16) | \
+                               ((u32_t)((c) & 0xff) << 8) | \
+                                (u32_t)((d) & 0xff))
+
+#define ip_addr_set(dest, src) (dest)->addr = \
+                               ((src) == NULL? 0:\
+                               (src)->addr)
+/**
+ * Determine if two address are on the same network.
+ *
+ * @arg addr1 IP address 1
+ * @arg addr2 IP address 2
+ * @arg mask network identifier mask
+ * @return !0 if the network identifiers of both address match
+ */
+#define ip_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \
+                                              (mask)->addr) == \
+                                             ((addr2)->addr & \
+                                              (mask)->addr))
+#define ip_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr)
+
+#define ip_addr_isany(addr1) ((addr1) == NULL || (addr1)->addr == 0)
+
+u8_t ip_addr_isbroadcast(struct ip_addr *, struct netif *);
+
+#define ip_addr_ismulticast(addr1) (((addr1)->addr & ntohl(0xf0000000UL)) == ntohl(0xe0000000UL))
+
+#define ip_addr_islinklocal(addr1) (((addr1)->addr & ntohl(0xffff0000UL)) == ntohl(0xa9fe0000UL))
+
+#define ip_addr_debug_print(debug, ipaddr) \
+  LWIP_DEBUGF(debug, ("%"U16_F".%"U16_F".%"U16_F".%"U16_F,              \
+                      ipaddr != NULL ?                                  \
+                      (u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff : 0,  \
+                      ipaddr != NULL ?                                  \
+                      (u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff : 0,  \
+                      ipaddr != NULL ?                                  \
+                      (u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff : 0,   \
+                      ipaddr != NULL ?                                  \
+                      (u16_t)ntohl((ipaddr)->addr) & 0xff : 0))
+
+/* These are cast to u16_t, with the intent that they are often arguments
+ * to printf using the U16_F format from cc.h. */
+#define ip4_addr1(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff)
+#define ip4_addr2(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff)
+#define ip4_addr3(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff)
+#define ip4_addr4(ipaddr) ((u16_t)(ntohl((ipaddr)->addr)) & 0xff)
+
+/**
+ * Same as inet_ntoa() but takes a struct ip_addr*
+ */
+#define ip_ntoa(addr)  ((addr != NULL) ? inet_ntoa(*((struct in_addr*)(addr))) : "NULL")
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_IP_ADDR_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/ip_frag.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/ip_frag.h
new file mode 100644
index 0000000..380e604
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv4/lwip/ip_frag.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Jani Monoses 
+ *
+ */
+
+#ifndef __LWIP_IP_FRAG_H__
+#define __LWIP_IP_FRAG_H__
+
+#include "lwip/opt.h"
+#include "lwip/err.h"
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/ip_addr.h"
+#include "lwip/ip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if IP_REASSEMBLY
+/* The IP reassembly timer interval in milliseconds. */
+#define IP_TMR_INTERVAL 1000
+
+/* IP reassembly helper struct.
+ * This is exported because memp needs to know the size.
+ */
+struct ip_reassdata {
+  struct ip_reassdata *next;
+  struct pbuf *p;
+  struct ip_hdr iphdr;
+  u16_t datagram_len;
+  u8_t flags;
+  u8_t timer;
+};
+
+void ip_reass_init(void);
+void ip_reass_tmr(void);
+struct pbuf * ip_reass(struct pbuf *p);
+#endif /* IP_REASSEMBLY */
+
+#if IP_FRAG
+err_t ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest);
+#endif /* IP_FRAG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_IP_FRAG_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv6/lwip/icmp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv6/lwip/icmp.h
new file mode 100644
index 0000000..87e9ffd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv6/lwip/icmp.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ICMP_H__
+#define __LWIP_ICMP_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ICMP6_DUR  1
+#define ICMP6_TE   3
+#define ICMP6_ECHO 128    /* echo */
+#define ICMP6_ER   129      /* echo reply */
+
+
+enum icmp_dur_type {
+  ICMP_DUR_NET = 0,    /* net unreachable */
+  ICMP_DUR_HOST = 1,   /* host unreachable */
+  ICMP_DUR_PROTO = 2,  /* protocol unreachable */
+  ICMP_DUR_PORT = 3,   /* port unreachable */
+  ICMP_DUR_FRAG = 4,   /* fragmentation needed and DF set */
+  ICMP_DUR_SR = 5      /* source route failed */
+};
+
+enum icmp_te_type {
+  ICMP_TE_TTL = 0,     /* time to live exceeded in transit */
+  ICMP_TE_FRAG = 1     /* fragment reassembly time exceeded */
+};
+
+void icmp_input(struct pbuf *p, struct netif *inp);
+
+void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
+void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
+
+struct icmp_echo_hdr {
+  u8_t type;
+  u8_t icode;
+  u16_t chksum;
+  u16_t id;
+  u16_t seqno;
+};
+
+struct icmp_dur_hdr {
+  u8_t type;
+  u8_t icode;
+  u16_t chksum;
+  u32_t unused;
+};
+
+struct icmp_te_hdr {
+  u8_t type;
+  u8_t icode;
+  u16_t chksum;
+  u32_t unused;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_ICMP */
+
+#endif /* __LWIP_ICMP_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv6/lwip/inet.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv6/lwip/inet.h
new file mode 100644
index 0000000..de1a0b6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv6/lwip/inet.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_INET_H__
+#define __LWIP_INET_H__
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+u16_t inet_chksum(void *data, u16_t len);
+u16_t inet_chksum_pbuf(struct pbuf *p);
+u16_t inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u32_t proto_len);
+
+u32_t inet_addr(const char *cp);
+s8_t inet_aton(const char *cp, struct in_addr *addr);
+
+#ifndef _MACHINE_ENDIAN_H_
+#ifndef _NETINET_IN_H
+#ifndef _LINUX_BYTEORDER_GENERIC_H
+u16_t htons(u16_t n);
+u16_t ntohs(u16_t n);
+u32_t htonl(u32_t n);
+u32_t ntohl(u32_t n);
+#endif /* _LINUX_BYTEORDER_GENERIC_H */
+#endif /* _NETINET_IN_H */
+#endif /* _MACHINE_ENDIAN_H_ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_INET_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv6/lwip/ip.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv6/lwip/ip.h
new file mode 100644
index 0000000..a01cfc6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv6/lwip/ip.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_H__
+#define __LWIP_IP_H__
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IP_HLEN 40
+
+#define IP_PROTO_ICMP    58
+#define IP_PROTO_UDP     17
+#define IP_PROTO_UDPLITE 136
+#define IP_PROTO_TCP     6
+
+/* This is passed as the destination address to ip_output_if (not
+   to ip_output), meaning that an IP header already is constructed
+   in the pbuf. This is used when TCP retransmits. */
+#ifdef IP_HDRINCL
+#undef IP_HDRINCL
+#endif /* IP_HDRINCL */
+#define IP_HDRINCL  NULL
+
+#if LWIP_NETIF_HWADDRHINT
+#define IP_PCB_ADDRHINT ;u8_t addr_hint
+#else
+#define IP_PCB_ADDRHINT
+#endif /* LWIP_NETIF_HWADDRHINT */
+
+/* This is the common part of all PCB types. It needs to be at the
+   beginning of a PCB type definition. It is located here so that
+   changes to this common part are made in one location instead of
+   having to change all PCB structs. */
+#define IP_PCB struct ip_addr local_ip; \
+  struct ip_addr remote_ip; \
+   /* Socket options */  \
+  u16_t so_options;      \
+   /* Type Of Service */ \
+  u8_t tos;              \
+  /* Time To Live */     \
+  u8_t ttl;              \
+  /* link layer address resolution hint */ \
+  IP_PCB_ADDRHINT
+
+
+/* The IPv6 header. */
+struct ip_hdr {
+#if BYTE_ORDER == LITTLE_ENDIAN
+  u8_t tclass1:4, v:4;
+  u8_t flow1:4, tclass2:4;  
+#else
+  u8_t v:4, tclass1:4;
+  u8_t tclass2:8, flow1:4;
+#endif
+  u16_t flow2;
+  u16_t len;                /* payload length */
+  u8_t nexthdr;             /* next header */
+  u8_t hoplim;              /* hop limit (TTL) */
+  struct ip_addr src, dest;          /* source and destination IP addresses */
+};
+
+#define IPH_PROTO(hdr) (iphdr->nexthdr)
+
+void ip_init(void);
+
+#include "lwip/netif.h"
+
+struct netif *ip_route(struct ip_addr *dest);
+
+void ip_input(struct pbuf *p, struct netif *inp);
+
+/* source and destination addresses in network byte order, please */
+err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+         u8_t ttl, u8_t proto);
+
+err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+      u8_t ttl, u8_t proto,
+      struct netif *netif);
+
+#define ip_current_netif() NULL
+#define ip_current_header() NULL
+
+#if IP_DEBUG
+void ip_debug_print(struct pbuf *p);
+#endif /* IP_DEBUG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_IP_H__ */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv6/lwip/ip_addr.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv6/lwip/ip_addr.h
new file mode 100644
index 0000000..b2d8ae5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/ipv6/lwip/ip_addr.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_ADDR_H__
+#define __LWIP_IP_ADDR_H__
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IP_ADDR_ANY 0
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+ struct ip_addr {
+  PACK_STRUCT_FIELD(u32_t addr[4]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/*
+ * struct ipaddr2 is used in the definition of the ARP packet format in
+ * order to support compilers that don't have structure packing.
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_addr2 {
+  PACK_STRUCT_FIELD(u16_t addrw[2]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define IP6_ADDR(ipaddr, a,b,c,d,e,f,g,h) do { (ipaddr)->addr[0] = htonl((u32_t)((a & 0xffff) << 16) | (b & 0xffff)); \
+                                               (ipaddr)->addr[1] = htonl(((c & 0xffff) << 16) | (d & 0xffff)); \
+                                               (ipaddr)->addr[2] = htonl(((e & 0xffff) << 16) | (f & 0xffff)); \
+                                               (ipaddr)->addr[3] = htonl(((g & 0xffff) << 16) | (h & 0xffff)); } while(0)
+
+u8_t ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2,
+        struct ip_addr *mask);
+u8_t ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2);
+void ip_addr_set(struct ip_addr *dest, struct ip_addr *src);
+u8_t ip_addr_isany(struct ip_addr *addr);
+
+#define ip_addr_debug_print(debug, ipaddr) \
+        LWIP_DEBUGF(debug, ("%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F"\n", \
+         (ntohl(ipaddr->addr[0]) >> 16) & 0xffff, \
+         ntohl(ipaddr->addr[0]) & 0xffff, \
+         (ntohl(ipaddr->addr[1]) >> 16) & 0xffff, \
+         ntohl(ipaddr->addr[1]) & 0xffff, \
+         (ntohl(ipaddr->addr[2]) >> 16) & 0xffff, \
+         ntohl(ipaddr->addr[2]) & 0xffff, \
+         (ntohl(ipaddr->addr[3]) >> 16) & 0xffff, \
+         ntohl(ipaddr->addr[3]) & 0xffff));
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_IP_ADDR_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/api.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/api.h
new file mode 100644
index 0000000..f6b1f74
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/api.h
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_API_H__
+#define __LWIP_API_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */
+
+#include  /* for size_t */
+
+#include "lwip/netbuf.h"
+#include "lwip/sys.h"
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Throughout this file, IP addresses and port numbers are expected to be in
+ * the same byte order as in the corresponding pcb.
+ */
+
+/* Flags for netconn_write */
+#define NETCONN_NOFLAG 0x00
+#define NETCONN_NOCOPY 0x00 /* Only for source code compatibility */
+#define NETCONN_COPY   0x01
+#define NETCONN_MORE   0x02
+
+/* Helpers to process several netconn_types by the same code */
+#define NETCONNTYPE_GROUP(t)    (t&0xF0)
+#define NETCONNTYPE_DATAGRAM(t) (t&0xE0)
+
+enum netconn_type {
+  NETCONN_INVALID    = 0,
+  /* NETCONN_TCP Group */
+  NETCONN_TCP        = 0x10,
+  /* NETCONN_UDP Group */
+  NETCONN_UDP        = 0x20,
+  NETCONN_UDPLITE    = 0x21,
+  NETCONN_UDPNOCHKSUM= 0x22,
+  /* NETCONN_RAW Group */
+  NETCONN_RAW        = 0x40
+};
+
+enum netconn_state {
+  NETCONN_NONE,
+  NETCONN_WRITE,
+  NETCONN_LISTEN,
+  NETCONN_CONNECT,
+  NETCONN_CLOSE
+};
+
+enum netconn_evt {
+  NETCONN_EVT_RCVPLUS,
+  NETCONN_EVT_RCVMINUS,
+  NETCONN_EVT_SENDPLUS,
+  NETCONN_EVT_SENDMINUS
+};
+
+#if LWIP_IGMP
+enum netconn_igmp {
+  NETCONN_JOIN,
+  NETCONN_LEAVE
+};
+#endif /* LWIP_IGMP */
+
+/* forward-declare some structs to avoid to include their headers */
+struct ip_pcb;
+struct tcp_pcb;
+struct udp_pcb;
+struct raw_pcb;
+struct netconn;
+
+/** A callback prototype to inform about events for a netconn */
+typedef void (* netconn_callback)(struct netconn *, enum netconn_evt, u16_t len);
+
+/** A netconn descriptor */
+struct netconn {
+  /** type of the netconn (TCP, UDP or RAW) */
+  enum netconn_type type;
+  /** current state of the netconn */
+  enum netconn_state state;
+  /** the lwIP internal protocol control block */
+  union {
+    struct ip_pcb  *ip;
+    struct tcp_pcb *tcp;
+    struct udp_pcb *udp;
+    struct raw_pcb *raw;
+  } pcb;
+  /** the last error this netconn had */
+  err_t err;
+  /** sem that is used to synchroneously execute functions in the core context */
+  sys_sem_t op_completed;
+  /** mbox where received packets are stored until they are fetched
+      by the netconn application thread (can grow quite big) */
+  sys_mbox_t recvmbox;
+  /** mbox where new connections are stored until processed
+      by the application thread */
+  sys_mbox_t acceptmbox;
+  /** only used for socket layer */
+  int socket;
+#if LWIP_SO_RCVTIMEO
+  /** timeout to wait for new data to be received
+      (or connections to arrive for listening netconns) */
+  int recv_timeout;
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+  /** maximum amount of bytes queued in recvmbox */
+  int recv_bufsize;
+#endif /* LWIP_SO_RCVBUF */
+  s16_t recv_avail;
+#if LWIP_TCP
+  /** TCP: when data passed to netconn_write doesn't fit into the send buffer,
+      this temporarily stores the message. */
+  struct api_msg_msg *write_msg;
+  /** TCP: when data passed to netconn_write doesn't fit into the send buffer,
+      this temporarily stores how much is already sent. */
+  size_t write_offset;
+#if LWIP_TCPIP_CORE_LOCKING
+  /** TCP: when data passed to netconn_write doesn't fit into the send buffer,
+      this temporarily stores whether to wake up the original application task
+      if data couldn't be sent in the first try. */
+  u8_t write_delayed;
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+#endif /* LWIP_TCP */
+  /** A callback function that is informed about events for this netconn */
+  netconn_callback callback;
+};
+
+/* Register an Network connection event */
+#define API_EVENT(c,e,l) if (c->callback) {         \
+                           (*c->callback)(c, e, l); \
+                         }
+
+/* Network connection functions: */
+#define netconn_new(t)                  netconn_new_with_proto_and_callback(t, 0, NULL)
+#define netconn_new_with_callback(t, c) netconn_new_with_proto_and_callback(t, 0, c)
+struct
+netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto,
+                                   netconn_callback callback);
+err_t             netconn_delete  (struct netconn *conn);
+/** Get the type of a netconn (as enum netconn_type). */
+#define netconn_type(conn) (conn->type)
+
+err_t             netconn_getaddr (struct netconn *conn,
+                                   struct ip_addr *addr,
+                                   u16_t *port,
+                                   u8_t local);
+#define netconn_peer(c,i,p) netconn_getaddr(c,i,p,0)
+#define netconn_addr(c,i,p) netconn_getaddr(c,i,p,1)
+
+err_t             netconn_bind    (struct netconn *conn,
+                                   struct ip_addr *addr,
+                                   u16_t port);
+err_t             netconn_connect (struct netconn *conn,
+                                   struct ip_addr *addr,
+                                   u16_t port);
+err_t             netconn_disconnect (struct netconn *conn);
+err_t             netconn_listen_with_backlog(struct netconn *conn, u8_t backlog);
+#define netconn_listen(conn) netconn_listen_with_backlog(conn, TCP_DEFAULT_LISTEN_BACKLOG)
+struct netconn *  netconn_accept  (struct netconn *conn);
+struct netbuf *   netconn_recv    (struct netconn *conn);
+err_t             netconn_sendto  (struct netconn *conn,
+                                   struct netbuf *buf, struct ip_addr *addr, u16_t port);
+err_t             netconn_send    (struct netconn *conn,
+                                   struct netbuf *buf);
+err_t             netconn_write   (struct netconn *conn,
+                                   const void *dataptr, size_t size,
+                                   u8_t apiflags);
+err_t             netconn_close   (struct netconn *conn);
+
+#if LWIP_IGMP
+err_t             netconn_join_leave_group (struct netconn *conn,
+                                            struct ip_addr *multiaddr,
+                                            struct ip_addr *interface,
+                                            enum netconn_igmp join_or_leave);
+#endif /* LWIP_IGMP */
+#if LWIP_DNS
+err_t             netconn_gethostbyname(const char *name, struct ip_addr *addr);
+#endif /* LWIP_DNS */
+
+#define netconn_err(conn)          ((conn)->err)
+#define netconn_recv_bufsize(conn) ((conn)->recv_bufsize)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_NETCONN */
+
+#endif /* __LWIP_API_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/api_msg.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/api_msg.h
new file mode 100644
index 0000000..d3b0456
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/api_msg.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_API_MSG_H__
+#define __LWIP_API_MSG_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */
+
+#include  /* for size_t */
+
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+#include "lwip/sys.h"
+#include "lwip/igmp.h"
+#include "lwip/api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* IP addresses and port numbers are expected to be in
+ * the same byte order as in the corresponding pcb.
+ */
+/** This struct includes everything that is necessary to execute a function
+    for a netconn in another thread context (mainly used to process netconns
+    in the tcpip_thread context to be thread safe). */
+struct api_msg_msg {
+  /** The netconn which to process - always needed: it includes the semaphore
+      which is used to block the application thread until the function finished. */
+  struct netconn *conn;
+  /** Depending on the executed function, one of these union members is used */
+  union {
+    /** used for do_send */
+    struct netbuf *b;
+    /** used for do_newconn */
+    struct {
+      u8_t proto;
+    } n;
+    /** used for do_bind and do_connect */
+    struct {
+      struct ip_addr *ipaddr;
+      u16_t port;
+    } bc;
+    /** used for do_getaddr */
+    struct {
+      struct ip_addr *ipaddr;
+      u16_t *port;
+      u8_t local;
+    } ad;
+    /** used for do_write */
+    struct {
+      const void *dataptr;
+      size_t len;
+      u8_t apiflags;
+    } w;
+    /** used for do_recv */
+    struct {
+      u16_t len;
+    } r;
+#if LWIP_IGMP
+    /** used for do_join_leave_group */
+    struct {
+      struct ip_addr *multiaddr;
+      struct ip_addr *interface;
+      enum netconn_igmp join_or_leave;
+    } jl;
+#endif /* LWIP_IGMP */
+#if TCP_LISTEN_BACKLOG
+    struct {
+      u8_t backlog;
+    } lb;
+#endif /* TCP_LISTEN_BACKLOG */
+  } msg;
+};
+
+/** This struct contains a function to execute in another thread context and
+    a struct api_msg_msg that serves as an argument for this function.
+    This is passed to tcpip_apimsg to execute functions in tcpip_thread context. */
+struct api_msg {
+  /** function to execute in tcpip_thread context */
+  void (* function)(struct api_msg_msg *msg);
+  /** arguments for this function */
+  struct api_msg_msg msg;
+};
+
+#if LWIP_DNS
+/** As do_gethostbyname requires more arguments but doesn't require a netconn,
+    it has its own struct (to avoid struct api_msg getting bigger than necessary).
+    do_gethostbyname must be called using tcpip_callback instead of tcpip_apimsg
+    (see netconn_gethostbyname). */
+struct dns_api_msg {
+  /** Hostname to query or dotted IP address string */
+  const char *name;
+  /** Rhe resolved address is stored here */
+  struct ip_addr *addr;
+  /** This semaphore is posted when the name is resolved, the application thread
+      should wait on it. */
+  sys_sem_t sem;
+  /** Errors are given back here */
+  err_t *err;
+};
+#endif /* LWIP_DNS */
+
+void do_newconn         ( struct api_msg_msg *msg);
+void do_delconn         ( struct api_msg_msg *msg);
+void do_bind            ( struct api_msg_msg *msg);
+void do_connect         ( struct api_msg_msg *msg);
+void do_disconnect      ( struct api_msg_msg *msg);
+void do_listen          ( struct api_msg_msg *msg);
+void do_send            ( struct api_msg_msg *msg);
+void do_recv            ( struct api_msg_msg *msg);
+void do_write           ( struct api_msg_msg *msg);
+void do_getaddr         ( struct api_msg_msg *msg);
+void do_close           ( struct api_msg_msg *msg);
+#if LWIP_IGMP
+void do_join_leave_group( struct api_msg_msg *msg);
+#endif /* LWIP_IGMP */
+
+#if LWIP_DNS
+void do_gethostbyname(void *arg);
+#endif /* LWIP_DNS */
+
+struct netconn* netconn_alloc(enum netconn_type t, netconn_callback callback);
+void netconn_free(struct netconn *conn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_NETCONN */
+
+#endif /* __LWIP_API_MSG_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/arch.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/arch.h
new file mode 100644
index 0000000..3a5a0e4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/arch.h
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ARCH_H__
+#define __LWIP_ARCH_H__
+
+#ifndef LITTLE_ENDIAN
+#define LITTLE_ENDIAN 1234
+#endif
+
+#ifndef BIG_ENDIAN
+#define BIG_ENDIAN 4321
+#endif
+
+#include "arch/cc.h"
+
+/** Temporary: define format string for size_t if not defined in cc.h */
+#ifndef SZT_F
+#define SZT_F U32_F
+#endif /* SZT_F */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef PACK_STRUCT_BEGIN
+#define PACK_STRUCT_BEGIN
+#endif /* PACK_STRUCT_BEGIN */
+
+#ifndef PACK_STRUCT_END
+#define PACK_STRUCT_END
+#endif /* PACK_STRUCT_END */
+
+#ifndef PACK_STRUCT_FIELD
+#define PACK_STRUCT_FIELD(x) x
+#endif /* PACK_STRUCT_FIELD */
+
+
+#ifndef LWIP_UNUSED_ARG
+#define LWIP_UNUSED_ARG(x) (void)x
+#endif /* LWIP_UNUSED_ARG */ 
+
+
+#ifdef LWIP_PROVIDE_ERRNO
+
+#define  EPERM     1  /* Operation not permitted */
+#define  ENOENT     2  /* No such file or directory */
+#define  ESRCH     3  /* No such process */
+#define  EINTR     4  /* Interrupted system call */
+#define  EIO     5  /* I/O error */
+#define  ENXIO     6  /* No such device or address */
+#define  E2BIG     7  /* Arg list too long */
+#define  ENOEXEC     8  /* Exec format error */
+#define  EBADF     9  /* Bad file number */
+#define  ECHILD    10  /* No child processes */
+#define  EAGAIN    11  /* Try again */
+#define  ENOMEM    12  /* Out of memory */
+#define  EACCES    13  /* Permission denied */
+#define  EFAULT    14  /* Bad address */
+#define  ENOTBLK    15  /* Block device required */
+#define  EBUSY    16  /* Device or resource busy */
+#define  EEXIST    17  /* File exists */
+#define  EXDEV    18  /* Cross-device link */
+#define  ENODEV    19  /* No such device */
+#define  ENOTDIR    20  /* Not a directory */
+#define  EISDIR    21  /* Is a directory */
+#define  EINVAL    22  /* Invalid argument */
+#define  ENFILE    23  /* File table overflow */
+#define  EMFILE    24  /* Too many open files */
+#define  ENOTTY    25  /* Not a typewriter */
+#define  ETXTBSY    26  /* Text file busy */
+#define  EFBIG    27  /* File too large */
+#define  ENOSPC    28  /* No space left on device */
+#define  ESPIPE    29  /* Illegal seek */
+#define  EROFS    30  /* Read-only file system */
+#define  EMLINK    31  /* Too many links */
+#define  EPIPE    32  /* Broken pipe */
+#define  EDOM    33  /* Math argument out of domain of func */
+#define  ERANGE    34  /* Math result not representable */
+#define  EDEADLK    35  /* Resource deadlock would occur */
+#define  ENAMETOOLONG  36  /* File name too long */
+#define  ENOLCK    37  /* No record locks available */
+#define  ENOSYS    38  /* Function not implemented */
+#define  ENOTEMPTY  39  /* Directory not empty */
+#define  ELOOP    40  /* Too many symbolic links encountered */
+#define  EWOULDBLOCK  EAGAIN  /* Operation would block */
+#define  ENOMSG    42  /* No message of desired type */
+#define  EIDRM    43  /* Identifier removed */
+#define  ECHRNG    44  /* Channel number out of range */
+#define  EL2NSYNC  45  /* Level 2 not synchronized */
+#define  EL3HLT    46  /* Level 3 halted */
+#define  EL3RST    47  /* Level 3 reset */
+#define  ELNRNG    48  /* Link number out of range */
+#define  EUNATCH    49  /* Protocol driver not attached */
+#define  ENOCSI    50  /* No CSI structure available */
+#define  EL2HLT    51  /* Level 2 halted */
+#define  EBADE    52  /* Invalid exchange */
+#define  EBADR    53  /* Invalid request descriptor */
+#define  EXFULL    54  /* Exchange full */
+#define  ENOANO    55  /* No anode */
+#define  EBADRQC    56  /* Invalid request code */
+#define  EBADSLT    57  /* Invalid slot */
+
+#define  EDEADLOCK  EDEADLK
+
+#define  EBFONT    59  /* Bad font file format */
+#define  ENOSTR    60  /* Device not a stream */
+#define  ENODATA    61  /* No data available */
+#define  ETIME    62  /* Timer expired */
+#define  ENOSR    63  /* Out of streams resources */
+#define  ENONET    64  /* Machine is not on the network */
+#define  ENOPKG    65  /* Package not installed */
+#define  EREMOTE    66  /* Object is remote */
+#define  ENOLINK    67  /* Link has been severed */
+#define  EADV    68  /* Advertise error */
+#define  ESRMNT    69  /* Srmount error */
+#define  ECOMM    70  /* Communication error on send */
+#define  EPROTO    71  /* Protocol error */
+#define  EMULTIHOP  72  /* Multihop attempted */
+#define  EDOTDOT    73  /* RFS specific error */
+#define  EBADMSG    74  /* Not a data message */
+#define  EOVERFLOW  75  /* Value too large for defined data type */
+#define  ENOTUNIQ  76  /* Name not unique on network */
+#define  EBADFD    77  /* File descriptor in bad state */
+#define  EREMCHG    78  /* Remote address changed */
+#define  ELIBACC    79  /* Can not access a needed shared library */
+#define  ELIBBAD    80  /* Accessing a corrupted shared library */
+#define  ELIBSCN    81  /* .lib section in a.out corrupted */
+#define  ELIBMAX    82  /* Attempting to link in too many shared libraries */
+#define  ELIBEXEC  83  /* Cannot exec a shared library directly */
+#define  EILSEQ    84  /* Illegal byte sequence */
+#define  ERESTART  85  /* Interrupted system call should be restarted */
+#define  ESTRPIPE  86  /* Streams pipe error */
+#define  EUSERS    87  /* Too many users */
+#define  ENOTSOCK  88  /* Socket operation on non-socket */
+#define  EDESTADDRREQ  89  /* Destination address required */
+#define  EMSGSIZE  90  /* Message too long */
+#define  EPROTOTYPE  91  /* Protocol wrong type for socket */
+#define  ENOPROTOOPT  92  /* Protocol not available */
+#define  EPROTONOSUPPORT  93  /* Protocol not supported */
+#define  ESOCKTNOSUPPORT  94  /* Socket type not supported */
+#define  EOPNOTSUPP  95  /* Operation not supported on transport endpoint */
+#define  EPFNOSUPPORT  96  /* Protocol family not supported */
+#define  EAFNOSUPPORT  97  /* Address family not supported by protocol */
+#define  EADDRINUSE  98  /* Address already in use */
+#define  EADDRNOTAVAIL  99  /* Cannot assign requested address */
+#define  ENETDOWN  100  /* Network is down */
+#define  ENETUNREACH  101  /* Network is unreachable */
+#define  ENETRESET  102  /* Network dropped connection because of reset */
+#define  ECONNABORTED  103  /* Software caused connection abort */
+#define  ECONNRESET  104  /* Connection reset by peer */
+#define  ENOBUFS    105  /* No buffer space available */
+#define  EISCONN    106  /* Transport endpoint is already connected */
+#define  ENOTCONN  107  /* Transport endpoint is not connected */
+#define  ESHUTDOWN  108  /* Cannot send after transport endpoint shutdown */
+#define  ETOOMANYREFS  109  /* Too many references: cannot splice */
+#define  ETIMEDOUT  110  /* Connection timed out */
+#define  ECONNREFUSED  111  /* Connection refused */
+#define  EHOSTDOWN  112  /* Host is down */
+#define  EHOSTUNREACH  113  /* No route to host */
+#define  EALREADY  114  /* Operation already in progress */
+#define  EINPROGRESS  115  /* Operation now in progress */
+#define  ESTALE    116  /* Stale NFS file handle */
+#define  EUCLEAN    117  /* Structure needs cleaning */
+#define  ENOTNAM    118  /* Not a XENIX named type file */
+#define  ENAVAIL    119  /* No XENIX semaphores available */
+#define  EISNAM    120  /* Is a named type file */
+#define  EREMOTEIO  121  /* Remote I/O error */
+#define  EDQUOT    122  /* Quota exceeded */
+
+#define  ENOMEDIUM  123  /* No medium found */
+#define  EMEDIUMTYPE  124  /* Wrong medium type */
+
+
+#define ENSROK    0 /* DNS server returned answer with no data */
+#define ENSRNODATA  160 /* DNS server returned answer with no data */
+#define ENSRFORMERR 161 /* DNS server claims query was misformatted */
+#define ENSRSERVFAIL 162  /* DNS server returned general failure */
+#define ENSRNOTFOUND 163  /* Domain name not found */
+#define ENSRNOTIMP  164 /* DNS server does not implement requested operation */
+#define ENSRREFUSED 165 /* DNS server refused query */
+#define ENSRBADQUERY 166  /* Misformatted DNS query */
+#define ENSRBADNAME 167 /* Misformatted domain name */
+#define ENSRBADFAMILY 168 /* Unsupported address family */
+#define ENSRBADRESP 169 /* Misformatted DNS reply */
+#define ENSRCONNREFUSED 170 /* Could not contact DNS servers */
+#define ENSRTIMEOUT 171 /* Timeout while contacting DNS servers */
+#define ENSROF    172 /* End of file */
+#define ENSRFILE  173 /* Error reading file */
+#define ENSRNOMEM 174 /* Out of memory */
+#define ENSRDESTRUCTION 175 /* Application terminated lookup */
+#define ENSRQUERYDOMAINTOOLONG  176 /* Domain name is too long */
+#define ENSRCNAMELOOP 177 /* Domain name is too long */
+
+#ifndef errno
+extern int errno;
+#endif
+
+#endif /* LWIP_PROVIDE_ERRNO */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_ARCH_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/debug.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/debug.h
new file mode 100644
index 0000000..d8359ea
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/debug.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_DEBUG_H__
+#define __LWIP_DEBUG_H__
+
+#include "lwip/arch.h"
+
+/** lower two bits indicate debug level
+ * - 0 all
+ * - 1 warning
+ * - 2 serious
+ * - 3 severe
+ */
+#define LWIP_DBG_LEVEL_ALL     0x00
+#define LWIP_DBG_LEVEL_OFF     LWIP_DBG_LEVEL_ALL /* compatibility define only */
+#define LWIP_DBG_LEVEL_WARNING 0x01 /* bad checksums, dropped packets, ... */
+#define LWIP_DBG_LEVEL_SERIOUS 0x02 /* memory allocation failures, ... */
+#define LWIP_DBG_LEVEL_SEVERE  0x03
+#define LWIP_DBG_MASK_LEVEL    0x03
+
+/** flag for LWIP_DEBUGF to enable that debug message */
+#define LWIP_DBG_ON            0x80U
+/** flag for LWIP_DEBUGF to disable that debug message */
+#define LWIP_DBG_OFF           0x00U
+
+/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */
+#define LWIP_DBG_TRACE         0x40U
+/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */
+#define LWIP_DBG_STATE         0x20U
+/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */
+#define LWIP_DBG_FRESH         0x10U
+/** flag for LWIP_DEBUGF to halt after printing this debug message */
+#define LWIP_DBG_HALT          0x08U
+
+#ifndef LWIP_NOASSERT
+#define LWIP_ASSERT(message, assertion) do { if(!(assertion)) \
+  LWIP_PLATFORM_ASSERT(message); } while(0)
+#else  /* LWIP_NOASSERT */
+#define LWIP_ASSERT(message, assertion) 
+#endif /* LWIP_NOASSERT */
+
+/** if "expression" isn't true, then print "message" and execute "handler" expression */
+#ifndef LWIP_ERROR
+#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \
+  LWIP_PLATFORM_ASSERT(message); handler;}} while(0)
+#endif /* LWIP_ERROR */
+
+#ifdef LWIP_DEBUG
+/** print debug message only if debug message type is enabled...
+ *  AND is of correct type AND is at least LWIP_DBG_LEVEL
+ */
+#define LWIP_DEBUGF(debug, message) do { \
+                               if ( \
+                                   ((debug) & LWIP_DBG_ON) && \
+                                   ((debug) & LWIP_DBG_TYPES_ON) && \
+                                   ((s16_t)((debug) & LWIP_DBG_MASK_LEVEL) >= LWIP_DBG_MIN_LEVEL)) { \
+                                 LWIP_PLATFORM_DIAG(message); \
+                                 if ((debug) & LWIP_DBG_HALT) { \
+                                   while(1); \
+                                 } \
+                               } \
+                             } while(0)
+
+#else  /* LWIP_DEBUG */
+#define LWIP_DEBUGF(debug, message) 
+#endif /* LWIP_DEBUG */
+
+#endif /* __LWIP_DEBUG_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/def.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/def.h
new file mode 100644
index 0000000..d2ed251
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/def.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_DEF_H__
+#define __LWIP_DEF_H__
+
+/* this might define NULL already */
+#include "lwip/arch.h"
+
+#define LWIP_MAX(x , y)  (((x) > (y)) ? (x) : (y))
+#define LWIP_MIN(x , y)  (((x) < (y)) ? (x) : (y))
+
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+
+
+#endif /* __LWIP_DEF_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/dhcp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/dhcp.h
new file mode 100644
index 0000000..db37e88
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/dhcp.h
@@ -0,0 +1,246 @@
+/** @file
+ */
+
+#ifndef __LWIP_DHCP_H__
+#define __LWIP_DHCP_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_DHCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** period (in seconds) of the application calling dhcp_coarse_tmr() */
+#define DHCP_COARSE_TIMER_SECS 60 
+/** period (in milliseconds) of the application calling dhcp_coarse_tmr() */
+#define DHCP_COARSE_TIMER_MSECS (DHCP_COARSE_TIMER_SECS * 1000UL)
+/** period (in milliseconds) of the application calling dhcp_fine_tmr() */
+#define DHCP_FINE_TIMER_MSECS 500 
+
+struct dhcp
+{
+  /** transaction identifier of last sent request */ 
+  u32_t xid;
+  /** our connection to the DHCP server */ 
+  struct udp_pcb *pcb;
+  /** incoming msg */
+  struct dhcp_msg *msg_in;
+  /** incoming msg options */
+  void *options_in; 
+  /** ingoing msg options length */
+  u16_t options_in_len;
+  /** current DHCP state machine state */
+  u8_t state;
+  /** retries of current request */
+  u8_t tries;
+
+  struct pbuf *p_out; /* pbuf of outcoming msg */
+  struct dhcp_msg *msg_out; /* outgoing msg */
+  u16_t options_out_len; /* outgoing msg options length */
+  u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */
+  u16_t t1_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */
+  u16_t t2_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */
+  struct ip_addr server_ip_addr; /* dhcp server address that offered this lease */
+  struct ip_addr offered_ip_addr;
+  struct ip_addr offered_sn_mask;
+  struct ip_addr offered_gw_addr;
+  struct ip_addr offered_bc_addr;
+#define DHCP_MAX_DNS 2
+  u32_t dns_count; /* actual number of DNS servers obtained */
+  struct ip_addr offered_dns_addr[DHCP_MAX_DNS]; /* DNS server addresses */
+ 
+  u32_t offered_t0_lease; /* lease period (in seconds) */
+  u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */
+  u32_t offered_t2_rebind; /* recommended rebind time (usually 66% of lease period)  */
+#if LWIP_DHCP_AUTOIP_COOP
+  u8_t autoip_coop_state;
+#endif
+/** Patch #1308
+ *  TODO: See dhcp.c "TODO"s
+ */
+#if 0
+  struct ip_addr offered_si_addr;
+  u8_t *boot_file_name;
+#endif
+};
+
+/* MUST be compiled with "pack structs" or equivalent! */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** minimum set of fields of any DHCP message */
+struct dhcp_msg
+{
+  PACK_STRUCT_FIELD(u8_t op);
+  PACK_STRUCT_FIELD(u8_t htype);
+  PACK_STRUCT_FIELD(u8_t hlen);
+  PACK_STRUCT_FIELD(u8_t hops);
+  PACK_STRUCT_FIELD(u32_t xid);
+  PACK_STRUCT_FIELD(u16_t secs);
+  PACK_STRUCT_FIELD(u16_t flags);
+  PACK_STRUCT_FIELD(struct ip_addr ciaddr);
+  PACK_STRUCT_FIELD(struct ip_addr yiaddr);
+  PACK_STRUCT_FIELD(struct ip_addr siaddr);
+  PACK_STRUCT_FIELD(struct ip_addr giaddr);
+#define DHCP_CHADDR_LEN 16U
+  PACK_STRUCT_FIELD(u8_t chaddr[DHCP_CHADDR_LEN]);
+#define DHCP_SNAME_LEN 64U
+  PACK_STRUCT_FIELD(u8_t sname[DHCP_SNAME_LEN]);
+#define DHCP_FILE_LEN 128U
+  PACK_STRUCT_FIELD(u8_t file[DHCP_FILE_LEN]);
+  PACK_STRUCT_FIELD(u32_t cookie);
+#define DHCP_MIN_OPTIONS_LEN 68U
+/** make sure user does not configure this too small */
+#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN))
+#  undef DHCP_OPTIONS_LEN
+#endif
+/** allow this to be configured in lwipopts.h, but not too small */
+#if (!defined(DHCP_OPTIONS_LEN))
+/** set this to be sufficient for your options in outgoing DHCP msgs */
+#  define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN
+#endif
+  PACK_STRUCT_FIELD(u8_t options[DHCP_OPTIONS_LEN]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** start DHCP configuration */
+err_t dhcp_start(struct netif *netif);
+/** enforce early lease renewal (not needed normally)*/
+err_t dhcp_renew(struct netif *netif);
+/** release the DHCP lease, usually called before dhcp_stop()*/
+err_t dhcp_release(struct netif *netif);
+/** stop DHCP configuration */
+void dhcp_stop(struct netif *netif);
+/** inform server of our manual IP address */
+void dhcp_inform(struct netif *netif);
+/** Handle a possible change in the network configuration */
+void dhcp_network_changed(struct netif *netif);
+
+/** if enabled, check whether the offered IP address is not in use, using ARP */
+#if DHCP_DOES_ARP_CHECK
+void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr);
+#endif
+
+/** to be called every minute */
+void dhcp_coarse_tmr(void);
+/** to be called every half second */
+void dhcp_fine_tmr(void);
+ 
+/** DHCP message item offsets and length */
+#define DHCP_MSG_OFS (UDP_DATA_OFS)  
+  #define DHCP_OP_OFS (DHCP_MSG_OFS + 0)
+  #define DHCP_HTYPE_OFS (DHCP_MSG_OFS + 1)
+  #define DHCP_HLEN_OFS (DHCP_MSG_OFS + 2)
+  #define DHCP_HOPS_OFS (DHCP_MSG_OFS + 3)
+  #define DHCP_XID_OFS (DHCP_MSG_OFS + 4)
+  #define DHCP_SECS_OFS (DHCP_MSG_OFS + 8)
+  #define DHCP_FLAGS_OFS (DHCP_MSG_OFS + 10)
+  #define DHCP_CIADDR_OFS (DHCP_MSG_OFS + 12)
+  #define DHCP_YIADDR_OFS (DHCP_MSG_OFS + 16)
+  #define DHCP_SIADDR_OFS (DHCP_MSG_OFS + 20)
+  #define DHCP_GIADDR_OFS (DHCP_MSG_OFS + 24)
+  #define DHCP_CHADDR_OFS (DHCP_MSG_OFS + 28)
+  #define DHCP_SNAME_OFS (DHCP_MSG_OFS + 44)
+  #define DHCP_FILE_OFS (DHCP_MSG_OFS + 108)
+#define DHCP_MSG_LEN 236
+
+#define DHCP_COOKIE_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN)
+#define DHCP_OPTIONS_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN + 4)
+
+#define DHCP_CLIENT_PORT 68  
+#define DHCP_SERVER_PORT 67
+
+/** DHCP client states */
+#define DHCP_REQUESTING 1
+#define DHCP_INIT 2
+#define DHCP_REBOOTING 3
+#define DHCP_REBINDING 4
+#define DHCP_RENEWING 5
+#define DHCP_SELECTING 6
+#define DHCP_INFORMING 7
+#define DHCP_CHECKING 8
+#define DHCP_PERMANENT 9
+#define DHCP_BOUND 10
+/** not yet implemented #define DHCP_RELEASING 11 */
+#define DHCP_BACKING_OFF 12
+#define DHCP_OFF 13
+
+/** AUTOIP cooperatation flags */
+#define DHCP_AUTOIP_COOP_STATE_OFF 0
+#define DHCP_AUTOIP_COOP_STATE_ON 1
+ 
+#define DHCP_BOOTREQUEST 1
+#define DHCP_BOOTREPLY 2
+
+#define DHCP_DISCOVER 1
+#define DHCP_OFFER 2
+#define DHCP_REQUEST 3
+#define DHCP_DECLINE 4
+#define DHCP_ACK 5
+#define DHCP_NAK 6
+#define DHCP_RELEASE 7
+#define DHCP_INFORM 8
+
+#define DHCP_HTYPE_ETH 1
+
+#define DHCP_HLEN_ETH 6
+
+#define DHCP_BROADCAST_FLAG 15
+#define DHCP_BROADCAST_MASK (1 << DHCP_FLAG_BROADCAST)
+
+/** BootP options */
+#define DHCP_OPTION_PAD 0
+#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */
+#define DHCP_OPTION_ROUTER 3
+#define DHCP_OPTION_DNS_SERVER 6 
+#define DHCP_OPTION_HOSTNAME 12
+#define DHCP_OPTION_IP_TTL 23
+#define DHCP_OPTION_MTU 26
+#define DHCP_OPTION_BROADCAST 28
+#define DHCP_OPTION_TCP_TTL 37
+#define DHCP_OPTION_END 255
+
+/** DHCP options */
+#define DHCP_OPTION_REQUESTED_IP 50 /* RFC 2132 9.1, requested IP address */
+#define DHCP_OPTION_LEASE_TIME 51 /* RFC 2132 9.2, time in seconds, in 4 bytes */
+#define DHCP_OPTION_OVERLOAD 52 /* RFC2132 9.3, use file and/or sname field for options */
+
+#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */
+#define DHCP_OPTION_MESSAGE_TYPE_LEN 1
+
+
+#define DHCP_OPTION_SERVER_ID 54 /* RFC 2132 9.7, server IP address */
+#define DHCP_OPTION_PARAMETER_REQUEST_LIST 55 /* RFC 2132 9.8, requested option types */
+
+#define DHCP_OPTION_MAX_MSG_SIZE 57 /* RFC 2132 9.10, message size accepted >= 576 */
+#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2
+
+#define DHCP_OPTION_T1 58 /* T1 renewal time */
+#define DHCP_OPTION_T2 59 /* T2 rebinding time */
+#define DHCP_OPTION_US 60
+#define DHCP_OPTION_CLIENT_ID 61
+#define DHCP_OPTION_TFTP_SERVERNAME 66
+#define DHCP_OPTION_BOOTFILE 67
+
+/** possible combinations of overloading the file and sname fields with options */
+#define DHCP_OVERLOAD_NONE 0
+#define DHCP_OVERLOAD_FILE 1
+#define DHCP_OVERLOAD_SNAME  2
+#define DHCP_OVERLOAD_SNAME_FILE 3
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_DHCP */
+
+#endif /*__LWIP_DHCP_H__*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/dns.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/dns.h
new file mode 100644
index 0000000..e5f4b7a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/dns.h
@@ -0,0 +1,97 @@
+/**
+ * lwip DNS resolver header file.
+
+ * Author: Jim Pettinato 
+ *   April 2007
+
+ * ported from uIP resolv.c Copyright (c) 2002-2003, Adam Dunkels.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __LWIP_DNS_H__
+#define __LWIP_DNS_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_DNS /* don't build if not configured for use in lwipopts.h */
+
+/** DNS timer period */
+#define DNS_TMR_INTERVAL          1000
+
+/** DNS field TYPE used for "Resource Records" */
+#define DNS_RRTYPE_A              1     /* a host address */
+#define DNS_RRTYPE_NS             2     /* an authoritative name server */
+#define DNS_RRTYPE_MD             3     /* a mail destination (Obsolete - use MX) */
+#define DNS_RRTYPE_MF             4     /* a mail forwarder (Obsolete - use MX) */
+#define DNS_RRTYPE_CNAME          5     /* the canonical name for an alias */
+#define DNS_RRTYPE_SOA            6     /* marks the start of a zone of authority */
+#define DNS_RRTYPE_MB             7     /* a mailbox domain name (EXPERIMENTAL) */
+#define DNS_RRTYPE_MG             8     /* a mail group member (EXPERIMENTAL) */
+#define DNS_RRTYPE_MR             9     /* a mail rename domain name (EXPERIMENTAL) */
+#define DNS_RRTYPE_NULL           10    /* a null RR (EXPERIMENTAL) */
+#define DNS_RRTYPE_WKS            11    /* a well known service description */
+#define DNS_RRTYPE_PTR            12    /* a domain name pointer */
+#define DNS_RRTYPE_HINFO          13    /* host information */
+#define DNS_RRTYPE_MINFO          14    /* mailbox or mail list information */
+#define DNS_RRTYPE_MX             15    /* mail exchange */
+#define DNS_RRTYPE_TXT            16    /* text strings */
+
+/** DNS field CLASS used for "Resource Records" */
+#define DNS_RRCLASS_IN            1     /* the Internet */
+#define DNS_RRCLASS_CS            2     /* the CSNET class (Obsolete - used only for examples in some obsolete RFCs) */
+#define DNS_RRCLASS_CH            3     /* the CHAOS class */
+#define DNS_RRCLASS_HS            4     /* Hesiod [Dyer 87] */
+#define DNS_RRCLASS_FLUSH         0x800 /* Flush bit */
+
+/** Callback which is invoked when a hostname is found.
+ * A function of this type must be implemented by the application using the DNS resolver.
+ * @param name pointer to the name that was looked up.
+ * @param ipaddr pointer to a struct ip_addr containing the IP address of the hostname,
+ *        or NULL if the name could not be found (or on any other error).
+ * @param callback_arg a user-specified callback argument passed to dns_gethostbyname
+*/
+typedef void (*dns_found_callback)(const char *name, struct ip_addr *ipaddr, void *callback_arg);
+
+
+void           dns_init(void);
+
+void           dns_tmr(void);
+
+void           dns_setserver(u8_t numdns, struct ip_addr *dnsserver);
+
+struct ip_addr dns_getserver(u8_t numdns);
+
+err_t          dns_gethostbyname(const char *hostname, struct ip_addr *addr,
+                                 dns_found_callback found, void *callback_arg);
+
+#if DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+int            dns_local_removehost(const char *hostname, const struct ip_addr *addr);
+err_t          dns_local_addhost(const char *hostname, const struct ip_addr *addr);
+#endif /* DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+
+#endif /* LWIP_DNS */
+
+#endif /* __LWIP_DNS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/err.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/err.h
new file mode 100644
index 0000000..6967644
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/err.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ERR_H__
+#define __LWIP_ERR_H__
+
+#include "lwip/opt.h"
+#include "lwip/arch.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Define LWIP_ERR_T in cc.h if you want to use
+ *  a different type for your platform (must be signed). */
+#ifdef LWIP_ERR_T
+typedef LWIP_ERR_T err_t;
+#else /* LWIP_ERR_T */
+ typedef s8_t err_t;
+#endif /* LWIP_ERR_T*/
+
+/* Definitions for error constants. */
+
+#define ERR_OK          0    /* No error, everything OK. */
+#define ERR_MEM        -1    /* Out of memory error.     */
+#define ERR_BUF        -2    /* Buffer error.            */
+#define ERR_TIMEOUT    -3    /* Timeout.                 */
+#define ERR_RTE        -4    /* Routing problem.         */
+
+#define ERR_IS_FATAL(e) ((e) < ERR_RTE)
+
+#define ERR_ABRT       -5    /* Connection aborted.      */
+#define ERR_RST        -6    /* Connection reset.        */
+#define ERR_CLSD       -7    /* Connection closed.       */
+#define ERR_CONN       -8    /* Not connected.           */
+
+#define ERR_VAL        -9    /* Illegal value.           */
+
+#define ERR_ARG        -10   /* Illegal argument.        */
+
+#define ERR_USE        -11   /* Address in use.          */
+
+#define ERR_IF         -12   /* Low-level netif error    */
+#define ERR_ISCONN     -13   /* Already connected.       */
+
+#define ERR_INPROGRESS -14   /* Operation in progress    */
+
+
+#ifdef LWIP_DEBUG
+extern const char *lwip_strerr(err_t err);
+#else
+#define lwip_strerr(x) ""
+#endif /* LWIP_DEBUG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_ERR_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/init.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/init.h
new file mode 100644
index 0000000..c1455f5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/init.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_INIT_H__
+#define __LWIP_INIT_H__
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** X.x.x: Major version of the stack */
+#define LWIP_VERSION_MAJOR      1U
+/** x.X.x: Minor version of the stack */
+#define LWIP_VERSION_MINOR      3U
+/** x.x.X: Revision of the stack */
+#define LWIP_VERSION_REVISION   2U
+/** For release candidates, this is set to 1..254
+  * For official releases, this is set to 255 (LWIP_RC_RELEASE)
+  * For development versions (CVS), this is set to 0 (LWIP_RC_DEVELOPMENT) */
+#define LWIP_VERSION_RC         255U
+
+/** LWIP_VERSION_RC is set to LWIP_RC_RELEASE for official releases */
+#define LWIP_RC_RELEASE         255U
+/** LWIP_VERSION_RC is set to LWIP_RC_DEVELOPMENT for CVS versions */
+#define LWIP_RC_DEVELOPMENT     0U
+
+#define LWIP_VERSION_IS_RELEASE     (LWIP_VERSION_RC == LWIP_RC_RELEASE)
+#define LWIP_VERSION_IS_DEVELOPMENT (LWIP_VERSION_RC == LWIP_RC_DEVELOPMENT)
+#define LWIP_VERSION_IS_RC          ((LWIP_VERSION_RC != LWIP_RC_RELEASE) && (LWIP_VERSION_RC != LWIP_RC_DEVELOPMENT))
+
+/** Provides the version of the stack */
+#define LWIP_VERSION   (LWIP_VERSION_MAJOR << 24   | LWIP_VERSION_MINOR << 16 | \
+                        LWIP_VERSION_REVISION << 8 | LWIP_VERSION_RC)
+
+/* Modules initialization */
+void lwip_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_INIT_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/mem.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/mem.h
new file mode 100644
index 0000000..327c204
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/mem.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_MEM_H__
+#define __LWIP_MEM_H__
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if MEM_LIBC_MALLOC
+
+#include  /* for size_t */
+
+typedef size_t mem_size_t;
+
+/* aliases for C library malloc() */
+#define mem_init()
+/* in case C library malloc() needs extra protection,
+ * allow these defines to be overridden.
+ */
+#ifndef mem_free
+#define mem_free free
+#endif
+#ifndef mem_malloc
+#define mem_malloc malloc
+#endif
+#ifndef mem_calloc
+#define mem_calloc calloc
+#endif
+#ifndef mem_realloc
+static void *mem_realloc(void *mem, mem_size_t size)
+{
+  LWIP_UNUSED_ARG(size);
+  return mem;
+}
+#endif
+#else /* MEM_LIBC_MALLOC */
+
+/* MEM_SIZE would have to be aligned, but using 64000 here instead of
+ * 65535 leaves some room for alignment...
+ */
+#if MEM_SIZE > 64000l
+typedef u32_t mem_size_t;
+#else
+typedef u16_t mem_size_t;
+#endif /* MEM_SIZE > 64000 */
+
+#if MEM_USE_POOLS
+/** mem_init is not used when using pools instead of a heap */
+#define mem_init()
+/** mem_realloc is not used when using pools instead of a heap:
+    we can't free part of a pool element and don't want to copy the rest */
+#define mem_realloc(mem, size) (mem)
+#else /* MEM_USE_POOLS */
+/* lwIP alternative malloc */
+void  mem_init(void);
+void *mem_realloc(void *mem, mem_size_t size);
+#endif /* MEM_USE_POOLS */
+void *mem_malloc(mem_size_t size);
+void *mem_calloc(mem_size_t count, mem_size_t size);
+void  mem_free(void *mem);
+#endif /* MEM_LIBC_MALLOC */
+
+#ifndef LWIP_MEM_ALIGN_SIZE
+#define LWIP_MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1) & ~(MEM_ALIGNMENT-1))
+#endif
+
+#ifndef LWIP_MEM_ALIGN
+#define LWIP_MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1)))
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_MEM_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/memp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/memp.h
new file mode 100644
index 0000000..f0d0739
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/memp.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef __LWIP_MEMP_H__
+#define __LWIP_MEMP_H__
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Create the list of all memory pools managed by memp. MEMP_MAX represents a NULL pool at the end */
+typedef enum {
+#define LWIP_MEMPOOL(name,num,size,desc)  MEMP_##name,
+#include "lwip/memp_std.h"
+  MEMP_MAX
+} memp_t;
+
+#if MEM_USE_POOLS
+/* Use a helper type to get the start and end of the user "memory pools" for mem_malloc */
+typedef enum {
+    /* Get the first (via:
+       MEMP_POOL_HELPER_START = ((u8_t) 1*MEMP_POOL_A + 0*MEMP_POOL_B + 0*MEMP_POOL_C + 0)*/
+    MEMP_POOL_HELPER_FIRST = ((u8_t)
+#define LWIP_MEMPOOL(name,num,size,desc)
+#define LWIP_MALLOC_MEMPOOL_START 1
+#define LWIP_MALLOC_MEMPOOL(num, size) * MEMP_POOL_##size + 0
+#define LWIP_MALLOC_MEMPOOL_END
+#include "lwip/memp_std.h"
+    ) ,
+    /* Get the last (via:
+       MEMP_POOL_HELPER_END = ((u8_t) 0 + MEMP_POOL_A*0 + MEMP_POOL_B*0 + MEMP_POOL_C*1) */
+    MEMP_POOL_HELPER_LAST = ((u8_t)
+#define LWIP_MEMPOOL(name,num,size,desc)
+#define LWIP_MALLOC_MEMPOOL_START
+#define LWIP_MALLOC_MEMPOOL(num, size) 0 + MEMP_POOL_##size *
+#define LWIP_MALLOC_MEMPOOL_END 1
+#include "lwip/memp_std.h"
+    )
+} memp_pool_helper_t;
+
+/* The actual start and stop values are here (cast them over)
+   We use this helper type and these defines so we can avoid using const memp_t values */
+#define MEMP_POOL_FIRST ((memp_t) MEMP_POOL_HELPER_FIRST)
+#define MEMP_POOL_LAST   ((memp_t) MEMP_POOL_HELPER_LAST)
+#endif /* MEM_USE_POOLS */
+
+#if MEMP_MEM_MALLOC || MEM_USE_POOLS
+extern const u16_t memp_sizes[MEMP_MAX];
+#endif /* MEMP_MEM_MALLOC || MEM_USE_POOLS */
+
+#if MEMP_MEM_MALLOC
+
+#include "mem.h"
+
+#define memp_init()
+#define memp_malloc(type)     mem_malloc(memp_sizes[type])
+#define memp_free(type, mem)  mem_free(mem)
+
+#else /* MEMP_MEM_MALLOC */
+
+#if MEM_USE_POOLS
+/** This structure is used to save the pool one element came from. */
+struct memp_malloc_helper
+{
+   memp_t poolnr;
+};
+#endif /* MEM_USE_POOLS */
+
+void  memp_init(void);
+
+#if MEMP_OVERFLOW_CHECK
+void *memp_malloc_fn(memp_t type, const char* file, const int line);
+#define memp_malloc(t) memp_malloc_fn((t), __FILE__, __LINE__)
+#else
+void *memp_malloc(memp_t type);
+#endif
+void  memp_free(memp_t type, void *mem);
+
+#endif /* MEMP_MEM_MALLOC */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_MEMP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/memp_std.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/memp_std.h
new file mode 100644
index 0000000..3446903
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/memp_std.h
@@ -0,0 +1,102 @@
+/*
+ * SETUP: Make sure we define everything we will need.
+ *
+ * We have create three types of pools:
+ *   1) MEMPOOL - standard pools
+ *   2) MALLOC_MEMPOOL - to be used by mem_malloc in mem.c
+ *   3) PBUF_MEMPOOL - a mempool of pbuf's, so include space for the pbuf struct
+ *
+ * If the include'r doesn't require any special treatment of each of the types
+ * above, then will declare #2 & #3 to be just standard mempools.
+ */
+#ifndef LWIP_MALLOC_MEMPOOL
+/* This treats "malloc pools" just like any other pool.
+   The pools are a little bigger to provide 'size' as the amount of user data. */
+#define LWIP_MALLOC_MEMPOOL(num, size) LWIP_MEMPOOL(POOL_##size, num, (size + sizeof(struct memp_malloc_helper)), "MALLOC_"#size)
+#define LWIP_MALLOC_MEMPOOL_START
+#define LWIP_MALLOC_MEMPOOL_END
+#endif /* LWIP_MALLOC_MEMPOOL */ 
+
+#ifndef LWIP_PBUF_MEMPOOL
+/* This treats "pbuf pools" just like any other pool.
+ * Allocates buffers for a pbuf struct AND a payload size */
+#define LWIP_PBUF_MEMPOOL(name, num, payload, desc) LWIP_MEMPOOL(name, num, (MEMP_ALIGN_SIZE(sizeof(struct pbuf)) + MEMP_ALIGN_SIZE(payload)), desc)
+#endif /* LWIP_PBUF_MEMPOOL */
+
+
+/*
+ * A list of internal pools used by LWIP.
+ *
+ * LWIP_MEMPOOL(pool_name, number_elements, element_size, pool_description)
+ *     creates a pool name MEMP_pool_name. description is used in stats.c
+ */
+#if LWIP_RAW
+LWIP_MEMPOOL(RAW_PCB,        MEMP_NUM_RAW_PCB,         sizeof(struct raw_pcb),        "RAW_PCB")
+#endif /* LWIP_RAW */
+
+#if LWIP_UDP
+LWIP_MEMPOOL(UDP_PCB,        MEMP_NUM_UDP_PCB,         sizeof(struct udp_pcb),        "UDP_PCB")
+#endif /* LWIP_UDP */
+
+#if LWIP_TCP
+LWIP_MEMPOOL(TCP_PCB,        MEMP_NUM_TCP_PCB,         sizeof(struct tcp_pcb),        "TCP_PCB")
+LWIP_MEMPOOL(TCP_PCB_LISTEN, MEMP_NUM_TCP_PCB_LISTEN,  sizeof(struct tcp_pcb_listen), "TCP_PCB_LISTEN")
+LWIP_MEMPOOL(TCP_SEG,        MEMP_NUM_TCP_SEG,         sizeof(struct tcp_seg),        "TCP_SEG")
+#endif /* LWIP_TCP */
+
+#if IP_REASSEMBLY
+LWIP_MEMPOOL(REASSDATA,      MEMP_NUM_REASSDATA,       sizeof(struct ip_reassdata),   "REASSDATA")
+#endif /* IP_REASSEMBLY */
+
+#if LWIP_NETCONN
+LWIP_MEMPOOL(NETBUF,         MEMP_NUM_NETBUF,          sizeof(struct netbuf),         "NETBUF")
+LWIP_MEMPOOL(NETCONN,        MEMP_NUM_NETCONN,         sizeof(struct netconn),        "NETCONN")
+#endif /* LWIP_NETCONN */
+
+#if NO_SYS==0
+LWIP_MEMPOOL(TCPIP_MSG_API,  MEMP_NUM_TCPIP_MSG_API,   sizeof(struct tcpip_msg),      "TCPIP_MSG_API")
+LWIP_MEMPOOL(TCPIP_MSG_INPKT,MEMP_NUM_TCPIP_MSG_INPKT, sizeof(struct tcpip_msg),      "TCPIP_MSG_INPKT")
+#endif /* NO_SYS==0 */
+
+#if ARP_QUEUEING
+LWIP_MEMPOOL(ARP_QUEUE,      MEMP_NUM_ARP_QUEUE,       sizeof(struct etharp_q_entry), "ARP_QUEUE")
+#endif /* ARP_QUEUEING */
+
+#if LWIP_IGMP
+LWIP_MEMPOOL(IGMP_GROUP,     MEMP_NUM_IGMP_GROUP,      sizeof(struct igmp_group),     "IGMP_GROUP")
+#endif /* LWIP_IGMP */
+
+#if NO_SYS==0
+LWIP_MEMPOOL(SYS_TIMEOUT,    MEMP_NUM_SYS_TIMEOUT,     sizeof(struct sys_timeo),      "SYS_TIMEOUT")
+#endif /* NO_SYS==0 */
+
+
+/*
+ * A list of pools of pbuf's used by LWIP.
+ *
+ * LWIP_PBUF_MEMPOOL(pool_name, number_elements, pbuf_payload_size, pool_description)
+ *     creates a pool name MEMP_pool_name. description is used in stats.c
+ *     This allocates enough space for the pbuf struct and a payload.
+ *     (Example: pbuf_payload_size=0 allocates only size for the struct)
+ */
+LWIP_PBUF_MEMPOOL(PBUF,      MEMP_NUM_PBUF,            0,                             "PBUF_REF/ROM")
+LWIP_PBUF_MEMPOOL(PBUF_POOL, PBUF_POOL_SIZE,           PBUF_POOL_BUFSIZE,             "PBUF_POOL")
+
+
+/*
+ * Allow for user-defined pools; this must be explicitly set in lwipopts.h
+ * since the default is to NOT look for lwippools.h
+ */
+#if MEMP_USE_CUSTOM_POOLS
+#include "lwippools.h"
+#endif /* MEMP_USE_CUSTOM_POOLS */
+
+/*
+ * REQUIRED CLEANUP: Clear up so we don't get "multiply defined" error later
+ * (#undef is ignored for something that is not defined)
+ */
+#undef LWIP_MEMPOOL
+#undef LWIP_MALLOC_MEMPOOL
+#undef LWIP_MALLOC_MEMPOOL_START
+#undef LWIP_MALLOC_MEMPOOL_END
+#undef LWIP_PBUF_MEMPOOL
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/netbuf.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/netbuf.h
new file mode 100644
index 0000000..0dfb367
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/netbuf.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_NETBUF_H__
+#define __LWIP_NETBUF_H__
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct netbuf {
+  struct pbuf *p, *ptr;
+  struct ip_addr *addr;
+  u16_t port;
+#if LWIP_NETBUF_RECVINFO
+  struct ip_addr *toaddr;
+  u16_t toport;
+#endif /* LWIP_NETBUF_RECVINFO */
+};
+
+/* Network buffer functions: */
+struct netbuf *   netbuf_new      (void);
+void              netbuf_delete   (struct netbuf *buf);
+void *            netbuf_alloc    (struct netbuf *buf, u16_t size);
+void              netbuf_free     (struct netbuf *buf);
+err_t             netbuf_ref      (struct netbuf *buf,
+           const void *dataptr, u16_t size);
+void              netbuf_chain    (struct netbuf *head,
+           struct netbuf *tail);
+
+u16_t             netbuf_len      (struct netbuf *buf);
+err_t             netbuf_data     (struct netbuf *buf,
+           void **dataptr, u16_t *len);
+s8_t              netbuf_next     (struct netbuf *buf);
+void              netbuf_first    (struct netbuf *buf);
+
+
+#define netbuf_copy_partial(buf, dataptr, len, offset) \
+  pbuf_copy_partial((buf)->p, (dataptr), (len), (offset))
+#define netbuf_copy(buf,dataptr,len) netbuf_copy_partial(buf, dataptr, len, 0)
+#define netbuf_take(buf, dataptr, len) pbuf_take((buf)->p, dataptr, len)
+#define netbuf_len(buf)              ((buf)->p->tot_len)
+#define netbuf_fromaddr(buf)         ((buf)->addr)
+#define netbuf_fromport(buf)         ((buf)->port)
+#if LWIP_NETBUF_RECVINFO
+#define netbuf_destaddr(buf)         ((buf)->toaddr)
+#define netbuf_destport(buf)         ((buf)->toport)
+#endif /* LWIP_NETBUF_RECVINFO */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_NETBUF_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/netdb.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/netdb.h
new file mode 100644
index 0000000..29c9847
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/netdb.h
@@ -0,0 +1,111 @@
+/*
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Simon Goldschmidt
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_DNS && LWIP_SOCKET
+
+#include  /* for size_t */
+
+#include "lwip/sockets.h"
+
+/* some rarely used options */
+#ifndef LWIP_DNS_API_DECLARE_H_ERRNO
+#define LWIP_DNS_API_DECLARE_H_ERRNO 1
+#endif
+
+#ifndef LWIP_DNS_API_DEFINE_ERRORS
+#define LWIP_DNS_API_DEFINE_ERRORS 1
+#endif
+
+#ifndef LWIP_DNS_API_DECLARE_STRUCTS
+#define LWIP_DNS_API_DECLARE_STRUCTS 1
+#endif
+
+#if LWIP_DNS_API_DEFINE_ERRORS
+/** Errors used by the DNS API functions, h_errno can be one of them */
+#define EAI_NONAME      200
+#define EAI_SERVICE     201
+#define EAI_FAIL        202
+#define EAI_MEMORY      203
+
+#define HOST_NOT_FOUND  210
+#define NO_DATA         211
+#define NO_RECOVERY     212
+#define TRY_AGAIN       213
+#endif /* LWIP_DNS_API_DEFINE_ERRORS */
+
+#if LWIP_DNS_API_DECLARE_STRUCTS
+struct hostent {
+    char  *h_name;      /* Official name of the host. */
+    char **h_aliases;   /* A pointer to an array of pointers to alternative host names,
+                           terminated by a null pointer. */
+    int    h_addrtype;  /* Address type. */
+    int    h_length;    /* The length, in bytes, of the address. */
+    char **h_addr_list; /* A pointer to an array of pointers to network addresses (in
+                           network byte order) for the host, terminated by a null pointer. */
+#define h_addr h_addr_list[0] /* for backward compatibility */
+};
+
+struct addrinfo {
+    int               ai_flags;      /* Input flags. */
+    int               ai_family;     /* Address family of socket. */
+    int               ai_socktype;   /* Socket type. */
+    int               ai_protocol;   /* Protocol of socket. */
+    socklen_t         ai_addrlen;    /* Length of socket address. */
+    struct sockaddr  *ai_addr;       /* Socket address of socket. */
+    char             *ai_canonname;  /* Canonical name of service location. */
+    struct addrinfo  *ai_next;       /* Pointer to next in list. */
+};
+#endif /* LWIP_DNS_API_DECLARE_STRUCTS */
+
+#if LWIP_DNS_API_DECLARE_H_ERRNO
+/* application accessable error code set by the DNS API functions */
+extern int h_errno;
+#endif /* LWIP_DNS_API_DECLARE_H_ERRNO*/
+
+struct hostent *lwip_gethostbyname(const char *name);
+int lwip_gethostbyname_r(const char *name, struct hostent *ret, char *buf,
+                size_t buflen, struct hostent **result, int *h_errnop);
+void lwip_freeaddrinfo(struct addrinfo *ai);
+int lwip_getaddrinfo(const char *nodename,
+       const char *servname,
+       const struct addrinfo *hints,
+       struct addrinfo **res);
+
+#if LWIP_COMPAT_SOCKETS
+#define gethostbyname(name) lwip_gethostbyname(name)
+#define gethostbyname_r(name, ret, buf, buflen, result, h_errnop) \
+       lwip_gethostbyname_r(name, ret, buf, buflen, result, h_errnop)
+#define freeaddrinfo(addrinfo) lwip_freeaddrinfo(addrinfo)
+#define getaddrinfo(nodname, servname, hints, res) \
+       lwip_getaddrinfo(nodname, servname, hints, res)
+#endif /* LWIP_COMPAT_SOCKETS */
+
+#endif /* LWIP_DNS && LWIP_SOCKET */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/netif.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/netif.h
new file mode 100644
index 0000000..c50a6da
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/netif.h
@@ -0,0 +1,263 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_NETIF_H__
+#define __LWIP_NETIF_H__
+
+#include "lwip/opt.h"
+
+#define ENABLE_LOOPBACK (LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF)
+
+#include "lwip/err.h"
+
+#include "lwip/ip_addr.h"
+
+#include "lwip/inet.h"
+#include "lwip/pbuf.h"
+#if LWIP_DHCP
+struct dhcp;
+#endif
+#if LWIP_AUTOIP
+struct autoip;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Throughout this file, IP addresses are expected to be in
+ * the same byte order as in IP_PCB. */
+
+/** must be the maximum of all used hardware address lengths
+    across all types of interfaces in use */
+#define NETIF_MAX_HWADDR_LEN 6U
+
+/** TODO: define the use (where, when, whom) of netif flags */
+
+/** whether the network interface is 'up'. this is
+ * a software flag used to control whether this network
+ * interface is enabled and processes traffic.
+ */
+#define NETIF_FLAG_UP           0x01U
+/** if set, the netif has broadcast capability */
+#define NETIF_FLAG_BROADCAST    0x02U
+/** if set, the netif is one end of a point-to-point connection */
+#define NETIF_FLAG_POINTTOPOINT 0x04U
+/** if set, the interface is configured using DHCP */
+#define NETIF_FLAG_DHCP         0x08U
+/** if set, the interface has an active link
+ *  (set by the network interface driver) */
+#define NETIF_FLAG_LINK_UP      0x10U
+/** if set, the netif is an device using ARP */
+#define NETIF_FLAG_ETHARP       0x20U
+/** if set, the netif has IGMP capability */
+#define NETIF_FLAG_IGMP         0x40U
+
+/** Generic data structure used for all lwIP network interfaces.
+ *  The following fields should be filled in by the initialization
+ *  function for the device driver: hwaddr_len, hwaddr[], mtu, flags */
+
+struct netif {
+  /** pointer to next in linked list */
+  struct netif *next;
+
+  /** IP address configuration in network byte order */
+  struct ip_addr ip_addr;
+  struct ip_addr netmask;
+  struct ip_addr gw;
+
+  /** This function is called by the network device driver
+   *  to pass a packet up the TCP/IP stack. */
+  err_t (* input)(struct pbuf *p, struct netif *inp);
+  /** This function is called by the IP module when it wants
+   *  to send a packet on the interface. This function typically
+   *  first resolves the hardware address, then sends the packet. */
+  err_t (* output)(struct netif *netif, struct pbuf *p,
+       struct ip_addr *ipaddr);
+  /** This function is called by the ARP module when it wants
+   *  to send a packet on the interface. This function outputs
+   *  the pbuf as-is on the link medium. */
+  err_t (* linkoutput)(struct netif *netif, struct pbuf *p);
+#if LWIP_NETIF_STATUS_CALLBACK
+  /** This function is called when the netif state is set to up or down
+   */
+  void (* status_callback)(struct netif *netif);
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+#if LWIP_NETIF_LINK_CALLBACK
+  /** This function is called when the netif link is set to up or down
+   */
+  void (* link_callback)(struct netif *netif);
+#endif /* LWIP_NETIF_LINK_CALLBACK */
+  /** This field can be set by the device driver and could point
+   *  to state information for the device. */
+  void *state;
+#if LWIP_DHCP
+  /** the DHCP client state information for this netif */
+  struct dhcp *dhcp;
+#endif /* LWIP_DHCP */
+#if LWIP_AUTOIP
+  /** the AutoIP client state information for this netif */
+  struct autoip *autoip;
+#endif
+#if LWIP_NETIF_HOSTNAME
+  /* the hostname for this netif, NULL is a valid value */
+  char*  hostname;
+#endif /* LWIP_NETIF_HOSTNAME */
+  /** maximum transfer unit (in bytes) */
+  u16_t mtu;
+  /** number of bytes used in hwaddr */
+  u8_t hwaddr_len;
+  /** link level hardware address of this interface */
+  u8_t hwaddr[NETIF_MAX_HWADDR_LEN];
+  /** flags (see NETIF_FLAG_ above) */
+  u8_t flags;
+  /** descriptive abbreviation */
+  char name[2];
+  /** number of this interface */
+  u8_t num;
+#if LWIP_SNMP
+  /** link type (from "snmp_ifType" enum from snmp.h) */
+  u8_t link_type;
+  /** (estimate) link speed */
+  u32_t link_speed;
+  /** timestamp at last change made (up/down) */
+  u32_t ts;
+  /** counters */
+  u32_t ifinoctets;
+  u32_t ifinucastpkts;
+  u32_t ifinnucastpkts;
+  u32_t ifindiscards;
+  u32_t ifoutoctets;
+  u32_t ifoutucastpkts;
+  u32_t ifoutnucastpkts;
+  u32_t ifoutdiscards;
+#endif /* LWIP_SNMP */
+#if LWIP_IGMP
+  /* This function could be called to add or delete a entry in the multicast filter table of the ethernet MAC.*/
+  err_t (*igmp_mac_filter)( struct netif *netif, struct ip_addr *group, u8_t action);
+#endif /* LWIP_IGMP */
+#if LWIP_NETIF_HWADDRHINT
+  u8_t *addr_hint;
+#endif /* LWIP_NETIF_HWADDRHINT */
+#if ENABLE_LOOPBACK
+  /* List of packets to be queued for ourselves. */
+  struct pbuf *loop_first;
+  struct pbuf *loop_last;
+#if LWIP_LOOPBACK_MAX_PBUFS
+  u16_t loop_cnt_current;
+#endif /* LWIP_LOOPBACK_MAX_PBUFS */
+#endif /* ENABLE_LOOPBACK */
+};
+
+#if LWIP_SNMP
+#define NETIF_INIT_SNMP(netif, type, speed) \
+  /* use "snmp_ifType" enum from snmp.h for "type", snmp_ifType_ethernet_csmacd by example */ \
+  netif->link_type = type;    \
+  /* your link speed here (units: bits per second) */  \
+  netif->link_speed = speed;  \
+  netif->ts = 0;              \
+  netif->ifinoctets = 0;      \
+  netif->ifinucastpkts = 0;   \
+  netif->ifinnucastpkts = 0;  \
+  netif->ifindiscards = 0;    \
+  netif->ifoutoctets = 0;     \
+  netif->ifoutucastpkts = 0;  \
+  netif->ifoutnucastpkts = 0; \
+  netif->ifoutdiscards = 0
+#else /* LWIP_SNMP */
+#define NETIF_INIT_SNMP(netif, type, speed)
+#endif /* LWIP_SNMP */
+
+
+/** The list of network interfaces. */
+extern struct netif *netif_list;
+/** The default network interface. */
+extern struct netif *netif_default;
+
+#define netif_init() /* Compatibility define, not init needed. */
+
+struct netif *netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
+      struct ip_addr *gw,
+      void *state,
+      err_t (* init)(struct netif *netif),
+      err_t (* input)(struct pbuf *p, struct netif *netif));
+
+void
+netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask,
+    struct ip_addr *gw);
+void netif_remove(struct netif * netif);
+
+/* Returns a network interface given its name. The name is of the form
+   "et0", where the first two letters are the "name" field in the
+   netif structure, and the digit is in the num field in the same
+   structure. */
+struct netif *netif_find(char *name);
+
+void netif_set_default(struct netif *netif);
+
+void netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr);
+void netif_set_netmask(struct netif *netif, struct ip_addr *netmask);
+void netif_set_gw(struct netif *netif, struct ip_addr *gw);
+
+void netif_set_up(struct netif *netif);
+void netif_set_down(struct netif *netif);
+u8_t netif_is_up(struct netif *netif);
+
+#if LWIP_NETIF_STATUS_CALLBACK
+/*
+ * Set callback to be called when interface is brought up/down
+ */
+void netif_set_status_callback(struct netif *netif, void (* status_callback)(struct netif *netif));
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+
+#if LWIP_NETIF_LINK_CALLBACK
+void netif_set_link_up(struct netif *netif);
+void netif_set_link_down(struct netif *netif);
+u8_t netif_is_link_up(struct netif *netif);
+/*
+ * Set callback to be called when link is brought up/down
+ */
+void netif_set_link_callback(struct netif *netif, void (* link_callback)(struct netif *netif));
+#endif /* LWIP_NETIF_LINK_CALLBACK */
+
+#ifdef __cplusplus
+}
+#endif
+
+#if ENABLE_LOOPBACK
+err_t netif_loop_output(struct netif *netif, struct pbuf *p, struct ip_addr *dest_ip);
+void netif_poll(struct netif *netif);
+#if !LWIP_NETIF_LOOPBACK_MULTITHREADING
+void netif_poll_all(void);
+#endif /* !LWIP_NETIF_LOOPBACK_MULTITHREADING */
+#endif /* ENABLE_LOOPBACK */
+
+#endif /* __LWIP_NETIF_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/netifapi.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/netifapi.h
new file mode 100644
index 0000000..4145dd7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/netifapi.h
@@ -0,0 +1,105 @@
+/*
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ */
+ 
+#ifndef __LWIP_NETIFAPI_H__
+#define __LWIP_NETIFAPI_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/sys.h"
+#include "lwip/netif.h"
+#include "lwip/dhcp.h"
+#include "lwip/autoip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct netifapi_msg_msg {
+#if !LWIP_TCPIP_CORE_LOCKING
+  sys_sem_t sem;
+#endif /* !LWIP_TCPIP_CORE_LOCKING */
+  err_t err;
+  struct netif *netif;
+  union {
+    struct {
+      struct ip_addr *ipaddr;
+      struct ip_addr *netmask;
+      struct ip_addr *gw;
+      void *state;
+      err_t (* init) (struct netif *netif);
+      err_t (* input)(struct pbuf *p, struct netif *netif);
+    } add;
+    struct {
+      void  (* voidfunc)(struct netif *netif);
+      err_t (* errtfunc)(struct netif *netif);
+    } common;
+  } msg;
+};
+
+struct netifapi_msg {
+  void (* function)(struct netifapi_msg_msg *msg);
+  struct netifapi_msg_msg msg;
+};
+
+
+/* API for application */
+err_t netifapi_netif_add       ( struct netif *netif,
+                                 struct ip_addr *ipaddr,
+                                 struct ip_addr *netmask,
+                                 struct ip_addr *gw,
+                                 void *state,
+                                 err_t (* init)(struct netif *netif),
+                                 err_t (* input)(struct pbuf *p, struct netif *netif) );
+
+err_t netifapi_netif_set_addr  ( struct netif *netif,
+                                 struct ip_addr *ipaddr,
+                                 struct ip_addr *netmask,
+                                 struct ip_addr *gw );
+
+err_t netifapi_netif_common    ( struct netif *netif,
+                                 void  (* voidfunc)(struct netif *netif),
+                                 err_t (* errtfunc)(struct netif *netif) );
+
+#define netifapi_netif_remove(n)      netifapi_netif_common(n, netif_remove, NULL)
+#define netifapi_netif_set_up(n)      netifapi_netif_common(n, netif_set_up, NULL)
+#define netifapi_netif_set_down(n)    netifapi_netif_common(n, netif_set_down, NULL)
+#define netifapi_netif_set_default(n) netifapi_netif_common(n, netif_set_default, NULL)
+#define netifapi_dhcp_start(n)        netifapi_netif_common(n, NULL, dhcp_start)
+#define netifapi_dhcp_stop(n)         netifapi_netif_common(n, dhcp_stop, NULL)
+#define netifapi_autoip_start(n)      netifapi_netif_common(n, NULL, autoip_start)
+#define netifapi_autoip_stop(n)       netifapi_netif_common(n, NULL, autoip_stop)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_NETIF_API */
+
+#endif /* __LWIP_NETIFAPI_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/opt.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/opt.h
new file mode 100644
index 0000000..eb99a77
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/opt.h
@@ -0,0 +1,1840 @@
+/**
+ * @file
+ *
+ * lwIP Options Configuration
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_OPT_H__
+#define __LWIP_OPT_H__
+
+/*
+ * Include user defined options first. Anything not defined in these files
+ * will be set to standard values. Override anything you dont like!
+ */
+#include "lwipopts.h"
+#include "lwip/debug.h"
+
+/*
+   -----------------------------------------------
+   ---------- Platform specific locking ----------
+   -----------------------------------------------
+*/
+
+/**
+ * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
+ * critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#ifndef SYS_LIGHTWEIGHT_PROT
+#define SYS_LIGHTWEIGHT_PROT            0
+#endif
+
+/** 
+ * NO_SYS==1: Provides VERY minimal functionality. Otherwise,
+ * use lwIP facilities.
+ */
+#ifndef NO_SYS
+#define NO_SYS                          0
+#endif
+
+/**
+ * MEMCPY: override this if you have a faster implementation at hand than the
+ * one included in your C library
+ */
+#ifndef MEMCPY
+#define MEMCPY(dst,src,len)             memcpy(dst,src,len)
+#endif
+
+/**
+ * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a
+ * call to memcpy() if the length is known at compile time and is small.
+ */
+#ifndef SMEMCPY
+#define SMEMCPY(dst,src,len)            memcpy(dst,src,len)
+#endif
+
+/*
+   ------------------------------------
+   ---------- Memory options ----------
+   ------------------------------------
+*/
+/**
+ * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library
+ * instead of the lwip internal allocator. Can save code size if you
+ * already use it.
+ */
+#ifndef MEM_LIBC_MALLOC
+#define MEM_LIBC_MALLOC                 0
+#endif
+
+/**
+* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator.
+* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution
+* speed and usage from interrupts!
+*/
+#ifndef MEMP_MEM_MALLOC
+#define MEMP_MEM_MALLOC                 0
+#endif
+
+/**
+ * MEM_ALIGNMENT: should be set to the alignment of the CPU
+ *    4 byte alignment -> #define MEM_ALIGNMENT 4
+ *    2 byte alignment -> #define MEM_ALIGNMENT 2
+ */
+#ifndef MEM_ALIGNMENT
+#define MEM_ALIGNMENT                   1
+#endif
+
+/**
+ * MEM_SIZE: the size of the heap memory. If the application will send
+ * a lot of data that needs to be copied, this should be set high.
+ */
+#ifndef MEM_SIZE
+#define MEM_SIZE                        1600
+#endif
+
+/**
+ * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable
+ * amount of bytes before and after each memp element in every pool and fills
+ * it with a prominent default value.
+ *    MEMP_OVERFLOW_CHECK == 0 no checking
+ *    MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed
+ *    MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time
+ *      memp_malloc() or memp_free() is called (useful but slow!)
+ */
+#ifndef MEMP_OVERFLOW_CHECK
+#define MEMP_OVERFLOW_CHECK             0
+#endif
+
+/**
+ * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make
+ * sure that there are no cycles in the linked lists.
+ */
+#ifndef MEMP_SANITY_CHECK
+#define MEMP_SANITY_CHECK               0
+#endif
+
+/**
+ * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set
+ * of memory pools of various sizes. When mem_malloc is called, an element of
+ * the smallest pool that can provide the length needed is returned.
+ * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled.
+ */
+#ifndef MEM_USE_POOLS
+#define MEM_USE_POOLS                   0
+#endif
+
+/**
+ * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next
+ * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more
+ * reliable. */
+#ifndef MEM_USE_POOLS_TRY_BIGGER_POOL
+#define MEM_USE_POOLS_TRY_BIGGER_POOL   0
+#endif
+
+/**
+ * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h
+ * that defines additional pools beyond the "standard" ones required
+ * by lwIP. If you set this to 1, you must have lwippools.h in your 
+ * inlude path somewhere. 
+ */
+#ifndef MEMP_USE_CUSTOM_POOLS
+#define MEMP_USE_CUSTOM_POOLS           0
+#endif
+
+/**
+ * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from
+ * interrupt context (or another context that doesn't allow waiting for a
+ * semaphore).
+ * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT,
+ * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs
+ * with each loop so that mem_free can run.
+ *
+ * ATTENTION: As you can see from the above description, this leads to dis-/
+ * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc
+ * can need longer.
+ *
+ * If you don't want that, at least for NO_SYS=0, you can still use the following
+ * functions to enqueue a deallocation call which then runs in the tcpip_thread
+ * context:
+ * - pbuf_free_callback(p);
+ * - mem_free_callback(m);
+ */
+#ifndef LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0
+#endif
+
+/*
+   ------------------------------------------------
+   ---------- Internal Memory Pool Sizes ----------
+   ------------------------------------------------
+*/
+/**
+ * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF).
+ * If the application sends a lot of data out of ROM (or other static memory),
+ * this should be set high.
+ */
+#ifndef MEMP_NUM_PBUF
+#define MEMP_NUM_PBUF                   16
+#endif
+
+/**
+ * MEMP_NUM_RAW_PCB: Number of raw connection PCBs
+ * (requires the LWIP_RAW option)
+ */
+#ifndef MEMP_NUM_RAW_PCB
+#define MEMP_NUM_RAW_PCB                4
+#endif
+
+/**
+ * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+ * per active UDP "connection".
+ * (requires the LWIP_UDP option)
+ */
+#ifndef MEMP_NUM_UDP_PCB
+#define MEMP_NUM_UDP_PCB                4
+#endif
+
+/**
+ * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections.
+ * (requires the LWIP_TCP option)
+ */
+#ifndef MEMP_NUM_TCP_PCB
+#define MEMP_NUM_TCP_PCB                5
+#endif
+
+/**
+ * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections.
+ * (requires the LWIP_TCP option)
+ */
+#ifndef MEMP_NUM_TCP_PCB_LISTEN
+#define MEMP_NUM_TCP_PCB_LISTEN         8
+#endif
+
+/**
+ * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments.
+ * (requires the LWIP_TCP option)
+ */
+#ifndef MEMP_NUM_TCP_SEG
+#define MEMP_NUM_TCP_SEG                16
+#endif
+
+/**
+ * MEMP_NUM_REASSDATA: the number of simultaneously IP packets queued for
+ * reassembly (whole packets, not fragments!)
+ */
+#ifndef MEMP_NUM_REASSDATA
+#define MEMP_NUM_REASSDATA              5
+#endif
+
+/**
+ * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing
+ * packets (pbufs) that are waiting for an ARP request (to resolve
+ * their destination address) to finish.
+ * (requires the ARP_QUEUEING option)
+ */
+#ifndef MEMP_NUM_ARP_QUEUE
+#define MEMP_NUM_ARP_QUEUE              30
+#endif
+
+/**
+ * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces
+ * can be members et the same time (one per netif - allsystems group -, plus one
+ * per netif membership).
+ * (requires the LWIP_IGMP option)
+ */
+#ifndef MEMP_NUM_IGMP_GROUP
+#define MEMP_NUM_IGMP_GROUP             8
+#endif
+
+/**
+ * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts.
+ * (requires NO_SYS==0)
+ */
+#ifndef MEMP_NUM_SYS_TIMEOUT
+#define MEMP_NUM_SYS_TIMEOUT            3
+#endif
+
+/**
+ * MEMP_NUM_NETBUF: the number of struct netbufs.
+ * (only needed if you use the sequential API, like api_lib.c)
+ */
+#ifndef MEMP_NUM_NETBUF
+#define MEMP_NUM_NETBUF                 2
+#endif
+
+/**
+ * MEMP_NUM_NETCONN: the number of struct netconns.
+ * (only needed if you use the sequential API, like api_lib.c)
+ */
+#ifndef MEMP_NUM_NETCONN
+#define MEMP_NUM_NETCONN                4
+#endif
+
+/**
+ * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used
+ * for callback/timeout API communication. 
+ * (only needed if you use tcpip.c)
+ */
+#ifndef MEMP_NUM_TCPIP_MSG_API
+#define MEMP_NUM_TCPIP_MSG_API          8
+#endif
+
+/**
+ * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used
+ * for incoming packets. 
+ * (only needed if you use tcpip.c)
+ */
+#ifndef MEMP_NUM_TCPIP_MSG_INPKT
+#define MEMP_NUM_TCPIP_MSG_INPKT        8
+#endif
+
+/**
+ * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. 
+ */
+#ifndef PBUF_POOL_SIZE
+#define PBUF_POOL_SIZE                  16
+#endif
+
+/*
+   ---------------------------------
+   ---------- ARP options ----------
+   ---------------------------------
+*/
+/**
+ * LWIP_ARP==1: Enable ARP functionality.
+ */
+#ifndef LWIP_ARP
+#define LWIP_ARP                        1
+#endif
+
+/**
+ * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached.
+ */
+#ifndef ARP_TABLE_SIZE
+#define ARP_TABLE_SIZE                  10
+#endif
+
+/**
+ * ARP_QUEUEING==1: Outgoing packets are queued during hardware address
+ * resolution.
+ */
+#ifndef ARP_QUEUEING
+#define ARP_QUEUEING                    1
+#endif
+
+/**
+ * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be
+ * updated with the source MAC and IP addresses supplied in the packet.
+ * You may want to disable this if you do not trust LAN peers to have the
+ * correct addresses, or as a limited approach to attempt to handle
+ * spoofing. If disabled, lwIP will need to make a new ARP request if
+ * the peer is not already in the ARP table, adding a little latency.
+ */
+#ifndef ETHARP_TRUST_IP_MAC
+#define ETHARP_TRUST_IP_MAC             1
+#endif
+
+/**
+ * ETHARP_SUPPORT_VLAN==1: support receiving ethernet packets with VLAN header.
+ * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check.
+ * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted.
+ * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted.
+ */
+#ifndef ETHARP_SUPPORT_VLAN
+#define ETHARP_SUPPORT_VLAN             0
+#endif
+
+/*
+   --------------------------------
+   ---------- IP options ----------
+   --------------------------------
+*/
+/**
+ * IP_FORWARD==1: Enables the ability to forward IP packets across network
+ * interfaces. If you are going to run lwIP on a device with only one network
+ * interface, define this to 0.
+ */
+#ifndef IP_FORWARD
+#define IP_FORWARD                      0
+#endif
+
+/**
+ * IP_OPTIONS_ALLOWED: Defines the behavior for IP options.
+ *      IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped.
+ *      IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed).
+ */
+#ifndef IP_OPTIONS_ALLOWED
+#define IP_OPTIONS_ALLOWED              1
+#endif
+
+/**
+ * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that
+ * this option does not affect outgoing packet sizes, which can be controlled
+ * via IP_FRAG.
+ */
+#ifndef IP_REASSEMBLY
+#define IP_REASSEMBLY                   1
+#endif
+
+/**
+ * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note
+ * that this option does not affect incoming packet sizes, which can be
+ * controlled via IP_REASSEMBLY.
+ */
+#ifndef IP_FRAG
+#define IP_FRAG                         1
+#endif
+
+/**
+ * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally)
+ * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived
+ * in this time, the whole packet is discarded.
+ */
+#ifndef IP_REASS_MAXAGE
+#define IP_REASS_MAXAGE                 3
+#endif
+
+/**
+ * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled.
+ * Since the received pbufs are enqueued, be sure to configure
+ * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive
+ * packets even if the maximum amount of fragments is enqueued for reassembly!
+ */
+#ifndef IP_REASS_MAX_PBUFS
+#define IP_REASS_MAX_PBUFS              10
+#endif
+
+/**
+ * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP
+ * fragmentation. Otherwise pbufs are allocated and reference the original
+ * packet data to be fragmented.
+ */
+#ifndef IP_FRAG_USES_STATIC_BUF
+#define IP_FRAG_USES_STATIC_BUF         1
+#endif
+
+/**
+ * IP_FRAG_MAX_MTU: Assumed max MTU on any interface for IP frag buffer
+ * (requires IP_FRAG_USES_STATIC_BUF==1)
+ */
+#if IP_FRAG_USES_STATIC_BUF && !defined(IP_FRAG_MAX_MTU)
+#define IP_FRAG_MAX_MTU                 1500
+#endif
+
+/**
+ * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers.
+ */
+#ifndef IP_DEFAULT_TTL
+#define IP_DEFAULT_TTL                  255
+#endif
+
+/**
+ * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast
+ * filter per pcb on udp and raw send operations. To enable broadcast filter
+ * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1.
+ */
+#ifndef IP_SOF_BROADCAST
+#define IP_SOF_BROADCAST                0
+#endif
+
+/**
+ * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast
+ * filter on recv operations.
+ */
+#ifndef IP_SOF_BROADCAST_RECV
+#define IP_SOF_BROADCAST_RECV           0
+#endif
+
+/*
+   ----------------------------------
+   ---------- ICMP options ----------
+   ----------------------------------
+*/
+/**
+ * LWIP_ICMP==1: Enable ICMP module inside the IP stack.
+ * Be careful, disable that make your product non-compliant to RFC1122
+ */
+#ifndef LWIP_ICMP
+#define LWIP_ICMP                       1
+#endif
+
+/**
+ * ICMP_TTL: Default value for Time-To-Live used by ICMP packets.
+ */
+#ifndef ICMP_TTL
+#define ICMP_TTL                       (IP_DEFAULT_TTL)
+#endif
+
+/**
+ * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only)
+ */
+#ifndef LWIP_BROADCAST_PING
+#define LWIP_BROADCAST_PING             0
+#endif
+
+/**
+ * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only)
+ */
+#ifndef LWIP_MULTICAST_PING
+#define LWIP_MULTICAST_PING             0
+#endif
+
+/*
+   ---------------------------------
+   ---------- RAW options ----------
+   ---------------------------------
+*/
+/**
+ * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
+ */
+#ifndef LWIP_RAW
+#define LWIP_RAW                        1
+#endif
+
+/**
+ * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
+ */
+#ifndef RAW_TTL
+#define RAW_TTL                        (IP_DEFAULT_TTL)
+#endif
+
+/*
+   ----------------------------------
+   ---------- DHCP options ----------
+   ----------------------------------
+*/
+/**
+ * LWIP_DHCP==1: Enable DHCP module.
+ */
+#ifndef LWIP_DHCP
+#define LWIP_DHCP                       0
+#endif
+
+/**
+ * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address.
+ */
+#ifndef DHCP_DOES_ARP_CHECK
+#define DHCP_DOES_ARP_CHECK             ((LWIP_DHCP) && (LWIP_ARP))
+#endif
+
+/*
+   ------------------------------------
+   ---------- AUTOIP options ----------
+   ------------------------------------
+*/
+/**
+ * LWIP_AUTOIP==1: Enable AUTOIP module.
+ */
+#ifndef LWIP_AUTOIP
+#define LWIP_AUTOIP                     0
+#endif
+
+/**
+ * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on
+ * the same interface at the same time.
+ */
+#ifndef LWIP_DHCP_AUTOIP_COOP
+#define LWIP_DHCP_AUTOIP_COOP           0
+#endif
+
+/**
+ * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes
+ * that should be sent before falling back on AUTOIP. This can be set
+ * as low as 1 to get an AutoIP address very quickly, but you should
+ * be prepared to handle a changing IP address when DHCP overrides
+ * AutoIP.
+ */
+#ifndef LWIP_DHCP_AUTOIP_COOP_TRIES
+#define LWIP_DHCP_AUTOIP_COOP_TRIES     9
+#endif
+
+/*
+   ----------------------------------
+   ---------- SNMP options ----------
+   ----------------------------------
+*/
+/**
+ * LWIP_SNMP==1: Turn on SNMP module. UDP must be available for SNMP
+ * transport.
+ */
+#ifndef LWIP_SNMP
+#define LWIP_SNMP                       0
+#endif
+
+/**
+ * SNMP_CONCURRENT_REQUESTS: Number of concurrent requests the module will
+ * allow. At least one request buffer is required. 
+ */
+#ifndef SNMP_CONCURRENT_REQUESTS
+#define SNMP_CONCURRENT_REQUESTS        1
+#endif
+
+/**
+ * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap
+ * destination is required
+ */
+#ifndef SNMP_TRAP_DESTINATIONS
+#define SNMP_TRAP_DESTINATIONS          1
+#endif
+
+/**
+ * SNMP_PRIVATE_MIB: 
+ */
+#ifndef SNMP_PRIVATE_MIB
+#define SNMP_PRIVATE_MIB                0
+#endif
+
+/**
+ * Only allow SNMP write actions that are 'safe' (e.g. disabeling netifs is not
+ * a safe action and disabled when SNMP_SAFE_REQUESTS = 1).
+ * Unsafe requests are disabled by default!
+ */
+#ifndef SNMP_SAFE_REQUESTS
+#define SNMP_SAFE_REQUESTS              1
+#endif
+
+/*
+   ----------------------------------
+   ---------- IGMP options ----------
+   ----------------------------------
+*/
+/**
+ * LWIP_IGMP==1: Turn on IGMP module. 
+ */
+#ifndef LWIP_IGMP
+#define LWIP_IGMP                       0
+#endif
+
+/*
+   ----------------------------------
+   ---------- DNS options -----------
+   ----------------------------------
+*/
+/**
+ * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS
+ * transport.
+ */
+#ifndef LWIP_DNS
+#define LWIP_DNS                        0
+#endif
+
+/** DNS maximum number of entries to maintain locally. */
+#ifndef DNS_TABLE_SIZE
+#define DNS_TABLE_SIZE                  4
+#endif
+
+/** DNS maximum host name length supported in the name table. */
+#ifndef DNS_MAX_NAME_LENGTH
+#define DNS_MAX_NAME_LENGTH             256
+#endif
+
+/** The maximum of DNS servers */
+#ifndef DNS_MAX_SERVERS
+#define DNS_MAX_SERVERS                 2
+#endif
+
+/** DNS do a name checking between the query and the response. */
+#ifndef DNS_DOES_NAME_CHECK
+#define DNS_DOES_NAME_CHECK             1
+#endif
+
+/** DNS use a local buffer if DNS_USES_STATIC_BUF=0, a static one if
+    DNS_USES_STATIC_BUF=1, or a dynamic one if DNS_USES_STATIC_BUF=2.
+    The buffer will be of size DNS_MSG_SIZE */
+#ifndef DNS_USES_STATIC_BUF
+#define DNS_USES_STATIC_BUF             1
+#endif
+
+/** DNS message max. size. Default value is RFC compliant. */
+#ifndef DNS_MSG_SIZE
+#define DNS_MSG_SIZE                    512
+#endif
+
+/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled,
+ *  you have to define
+ *    #define DNS_LOCAL_HOSTLIST_INIT {{"host1", 0x123}, {"host2", 0x234}}
+ *  (an array of structs name/address, where address is an u32_t in network
+ *  byte order).
+ *
+ *  Instead, you can also use an external function:
+ *  #define DNS_LOOKUP_LOCAL_EXTERN(x) extern u32_t my_lookup_function(const char *name)
+ *  that returns the IP address or INADDR_NONE if not found.
+ */
+#ifndef DNS_LOCAL_HOSTLIST
+#define DNS_LOCAL_HOSTLIST              0
+#endif /* DNS_LOCAL_HOSTLIST */
+
+/** If this is turned on, the local host-list can be dynamically changed
+ *  at runtime. */
+#ifndef DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC   0
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+
+/*
+   ---------------------------------
+   ---------- UDP options ----------
+   ---------------------------------
+*/
+/**
+ * LWIP_UDP==1: Turn on UDP.
+ */
+#ifndef LWIP_UDP
+#define LWIP_UDP                        1
+#endif
+
+/**
+ * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP)
+ */
+#ifndef LWIP_UDPLITE
+#define LWIP_UDPLITE                    0
+#endif
+
+/**
+ * UDP_TTL: Default Time-To-Live value.
+ */
+#ifndef UDP_TTL
+#define UDP_TTL                         (IP_DEFAULT_TTL)
+#endif
+
+/**
+ * LWIP_NETBUF_RECVINFO==1: append destination addr and port to every netbuf.
+ */
+#ifndef LWIP_NETBUF_RECVINFO
+#define LWIP_NETBUF_RECVINFO            0
+#endif
+
+/*
+   ---------------------------------
+   ---------- TCP options ----------
+   ---------------------------------
+*/
+/**
+ * LWIP_TCP==1: Turn on TCP.
+ */
+#ifndef LWIP_TCP
+#define LWIP_TCP                        1
+#endif
+
+/**
+ * TCP_TTL: Default Time-To-Live value.
+ */
+#ifndef TCP_TTL
+#define TCP_TTL                         (IP_DEFAULT_TTL)
+#endif
+
+/**
+ * TCP_WND: The size of a TCP window.  This must be at least 
+ * (2 * TCP_MSS) for things to work well
+ */
+#ifndef TCP_WND
+#define TCP_WND                         (4 * TCP_MSS)
+#endif 
+
+/**
+ * TCP_MAXRTX: Maximum number of retransmissions of data segments.
+ */
+#ifndef TCP_MAXRTX
+#define TCP_MAXRTX                      12
+#endif
+
+/**
+ * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments.
+ */
+#ifndef TCP_SYNMAXRTX
+#define TCP_SYNMAXRTX                   6
+#endif
+
+/**
+ * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order.
+ * Define to 0 if your device is low on memory.
+ */
+#ifndef TCP_QUEUE_OOSEQ
+#define TCP_QUEUE_OOSEQ                 (LWIP_TCP)
+#endif
+
+/**
+ * TCP_MSS: TCP Maximum segment size. (default is 536, a conservative default,
+ * you might want to increase this.)
+ * For the receive side, this MSS is advertised to the remote side
+ * when opening a connection. For the transmit size, this MSS sets
+ * an upper limit on the MSS advertised by the remote host.
+ */
+#ifndef TCP_MSS
+#define TCP_MSS                         536
+#endif
+
+/**
+ * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really
+ * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which
+ * reflects the available reassembly buffer size at the remote host) and the
+ * largest size permitted by the IP layer" (RFC 1122)
+ * Setting this to 1 enables code that checks TCP_MSS against the MTU of the
+ * netif used for a connection and limits the MSS if it would be too big otherwise.
+ */
+#ifndef TCP_CALCULATE_EFF_SEND_MSS
+#define TCP_CALCULATE_EFF_SEND_MSS      1
+#endif
+
+
+/**
+ * TCP_SND_BUF: TCP sender buffer space (bytes). 
+ */
+#ifndef TCP_SND_BUF
+#define TCP_SND_BUF                     256
+#endif
+
+/**
+ * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least
+ * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work.
+ */
+#ifndef TCP_SND_QUEUELEN
+#define TCP_SND_QUEUELEN                (4 * (TCP_SND_BUF)/(TCP_MSS))
+#endif
+
+/**
+ * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than or equal
+ * to TCP_SND_BUF. It is the amount of space which must be available in the
+ * TCP snd_buf for select to return writable.
+ */
+#ifndef TCP_SNDLOWAT
+#define TCP_SNDLOWAT                    ((TCP_SND_BUF)/2)
+#endif
+
+/**
+ * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb.
+ */
+#ifndef TCP_LISTEN_BACKLOG
+#define TCP_LISTEN_BACKLOG              0
+#endif
+
+/**
+ * The maximum allowed backlog for TCP listen netconns.
+ * This backlog is used unless another is explicitly specified.
+ * 0xff is the maximum (u8_t).
+ */
+#ifndef TCP_DEFAULT_LISTEN_BACKLOG
+#define TCP_DEFAULT_LISTEN_BACKLOG      0xff
+#endif
+
+/**
+ * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option.
+ */
+#ifndef LWIP_TCP_TIMESTAMPS
+#define LWIP_TCP_TIMESTAMPS             0
+#endif
+
+/**
+ * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an
+ * explicit window update
+ */
+#ifndef TCP_WND_UPDATE_THRESHOLD
+#define TCP_WND_UPDATE_THRESHOLD   (TCP_WND / 4)
+#endif
+
+/**
+ * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1.
+ *     LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all
+ *         events (accept, sent, etc) that happen in the system.
+ *     LWIP_CALLBACK_API==1: The PCB callback function is called directly
+ *         for the event.
+ */
+#ifndef LWIP_EVENT_API
+#define LWIP_EVENT_API                  0
+#define LWIP_CALLBACK_API               1
+#else 
+#define LWIP_EVENT_API                  1
+#define LWIP_CALLBACK_API               0
+#endif
+
+
+/*
+   ----------------------------------
+   ---------- Pbuf options ----------
+   ----------------------------------
+*/
+/**
+ * PBUF_LINK_HLEN: the number of bytes that should be allocated for a
+ * link level header. The default is 14, the standard value for
+ * Ethernet.
+ */
+#ifndef PBUF_LINK_HLEN
+#define PBUF_LINK_HLEN                  14
+#endif
+
+/**
+ * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is
+ * designed to accomodate single full size TCP frame in one pbuf, including
+ * TCP_MSS, IP header, and link header.
+ */
+#ifndef PBUF_POOL_BUFSIZE
+#define PBUF_POOL_BUFSIZE               LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN)
+#endif
+
+/*
+   ------------------------------------------------
+   ---------- Network Interfaces options ----------
+   ------------------------------------------------
+*/
+/**
+ * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname
+ * field.
+ */
+#ifndef LWIP_NETIF_HOSTNAME
+#define LWIP_NETIF_HOSTNAME             0
+#endif
+
+/**
+ * LWIP_NETIF_API==1: Support netif api (in netifapi.c)
+ */
+#ifndef LWIP_NETIF_API
+#define LWIP_NETIF_API                  0
+#endif
+
+/**
+ * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface
+ * changes its up/down status (i.e., due to DHCP IP acquistion)
+ */
+#ifndef LWIP_NETIF_STATUS_CALLBACK
+#define LWIP_NETIF_STATUS_CALLBACK      0
+#endif
+
+/**
+ * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface
+ * whenever the link changes (i.e., link down)
+ */
+#ifndef LWIP_NETIF_LINK_CALLBACK
+#define LWIP_NETIF_LINK_CALLBACK        0
+#endif
+
+/**
+ * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table
+ * indices) in struct netif. TCP and UDP can make use of this to prevent
+ * scanning the ARP table for every sent packet. While this is faster for big
+ * ARP tables or many concurrent connections, it might be counterproductive
+ * if you have a tiny ARP table or if there never are concurrent connections.
+ */
+#ifndef LWIP_NETIF_HWADDRHINT
+#define LWIP_NETIF_HWADDRHINT           0
+#endif
+
+/**
+ * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP
+ * address equal to the netif IP address, looping them back up the stack.
+ */
+#ifndef LWIP_NETIF_LOOPBACK
+#define LWIP_NETIF_LOOPBACK             0
+#endif
+
+/**
+ * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback
+ * sending for each netif (0 = disabled)
+ */
+#ifndef LWIP_LOOPBACK_MAX_PBUFS
+#define LWIP_LOOPBACK_MAX_PBUFS         0
+#endif
+
+/**
+ * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in
+ * the system, as netifs must change how they behave depending on this setting
+ * for the LWIP_NETIF_LOOPBACK option to work.
+ * Setting this is needed to avoid reentering non-reentrant functions like
+ * tcp_input().
+ *    LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a
+ *       multithreaded environment like tcpip.c. In this case, netif->input()
+ *       is called directly.
+ *    LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup.
+ *       The packets are put on a list and netif_poll() must be called in
+ *       the main application loop.
+ */
+#ifndef LWIP_NETIF_LOOPBACK_MULTITHREADING
+#define LWIP_NETIF_LOOPBACK_MULTITHREADING    (!NO_SYS)
+#endif
+
+/**
+ * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data
+ * to be sent into one single pbuf. This is for compatibility with DMA-enabled
+ * MACs that do not support scatter-gather.
+ * Beware that this might involve CPU-memcpy before transmitting that would not
+ * be needed without this flag! Use this only if you need to!
+ *
+ * @todo: TCP and IP-frag do not work with this, yet:
+ */
+#ifndef LWIP_NETIF_TX_SINGLE_PBUF
+#define LWIP_NETIF_TX_SINGLE_PBUF             0
+#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
+
+/*
+   ------------------------------------
+   ---------- LOOPIF options ----------
+   ------------------------------------
+*/
+/**
+ * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c
+ */
+#ifndef LWIP_HAVE_LOOPIF
+#define LWIP_HAVE_LOOPIF                0
+#endif
+
+/*
+   ------------------------------------
+   ---------- SLIPIF options ----------
+   ------------------------------------
+*/
+/**
+ * LWIP_HAVE_SLIPIF==1: Support slip interface and slipif.c
+ */
+#ifndef LWIP_HAVE_SLIPIF
+#define LWIP_HAVE_SLIPIF                0
+#endif
+
+/*
+   ------------------------------------
+   ---------- Thread options ----------
+   ------------------------------------
+*/
+/**
+ * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread.
+ */
+#ifndef TCPIP_THREAD_NAME
+#define TCPIP_THREAD_NAME              "tcpip_thread"
+#endif
+
+/**
+ * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef TCPIP_THREAD_STACKSIZE
+#define TCPIP_THREAD_STACKSIZE          0
+#endif
+
+/**
+ * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef TCPIP_THREAD_PRIO
+#define TCPIP_THREAD_PRIO               1
+#endif
+
+/**
+ * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages
+ * The queue size value itself is platform-dependent, but is passed to
+ * sys_mbox_new() when tcpip_init is called.
+ */
+#ifndef TCPIP_MBOX_SIZE
+#define TCPIP_MBOX_SIZE                 0
+#endif
+
+/**
+ * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread.
+ */
+#ifndef SLIPIF_THREAD_NAME
+#define SLIPIF_THREAD_NAME             "slipif_loop"
+#endif
+
+/**
+ * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef SLIPIF_THREAD_STACKSIZE
+#define SLIPIF_THREAD_STACKSIZE         0
+#endif
+
+/**
+ * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef SLIPIF_THREAD_PRIO
+#define SLIPIF_THREAD_PRIO              1
+#endif
+
+/**
+ * PPP_THREAD_NAME: The name assigned to the pppMain thread.
+ */
+#ifndef PPP_THREAD_NAME
+#define PPP_THREAD_NAME                "pppMain"
+#endif
+
+/**
+ * PPP_THREAD_STACKSIZE: The stack size used by the pppMain thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef PPP_THREAD_STACKSIZE
+#define PPP_THREAD_STACKSIZE            0
+#endif
+
+/**
+ * PPP_THREAD_PRIO: The priority assigned to the pppMain thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef PPP_THREAD_PRIO
+#define PPP_THREAD_PRIO                 1
+#endif
+
+/**
+ * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread.
+ */
+#ifndef DEFAULT_THREAD_NAME
+#define DEFAULT_THREAD_NAME            "lwIP"
+#endif
+
+/**
+ * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef DEFAULT_THREAD_STACKSIZE
+#define DEFAULT_THREAD_STACKSIZE        0
+#endif
+
+/**
+ * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef DEFAULT_THREAD_PRIO
+#define DEFAULT_THREAD_PRIO             1
+#endif
+
+/**
+ * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#ifndef DEFAULT_RAW_RECVMBOX_SIZE
+#define DEFAULT_RAW_RECVMBOX_SIZE       0
+#endif
+
+/**
+ * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#ifndef DEFAULT_UDP_RECVMBOX_SIZE
+#define DEFAULT_UDP_RECVMBOX_SIZE       0
+#endif
+
+/**
+ * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#ifndef DEFAULT_TCP_RECVMBOX_SIZE
+#define DEFAULT_TCP_RECVMBOX_SIZE       0
+#endif
+
+/**
+ * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections.
+ * The queue size value itself is platform-dependent, but is passed to
+ * sys_mbox_new() when the acceptmbox is created.
+ */
+#ifndef DEFAULT_ACCEPTMBOX_SIZE
+#define DEFAULT_ACCEPTMBOX_SIZE         0
+#endif
+
+/*
+   ----------------------------------------------
+   ---------- Sequential layer options ----------
+   ----------------------------------------------
+*/
+/**
+ * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!)
+ * Don't use it if you're not an active lwIP project member
+ */
+#ifndef LWIP_TCPIP_CORE_LOCKING
+#define LWIP_TCPIP_CORE_LOCKING         0
+#endif
+
+/**
+ * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c)
+ */
+#ifndef LWIP_NETCONN
+#define LWIP_NETCONN                    1
+#endif
+
+/*
+   ------------------------------------
+   ---------- Socket options ----------
+   ------------------------------------
+*/
+/**
+ * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)
+ */
+#ifndef LWIP_SOCKET
+#define LWIP_SOCKET                     1
+#endif
+
+/**
+ * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names.
+ * (only used if you use sockets.c)
+ */
+#ifndef LWIP_COMPAT_SOCKETS
+#define LWIP_COMPAT_SOCKETS             1
+#endif
+
+/**
+ * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names.
+ * Disable this option if you use a POSIX operating system that uses the same
+ * names (read, write & close). (only used if you use sockets.c)
+ */
+#ifndef LWIP_POSIX_SOCKETS_IO_NAMES
+#define LWIP_POSIX_SOCKETS_IO_NAMES     1
+#endif
+
+/**
+ * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT
+ * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set
+ * in seconds. (does not require sockets.c, and will affect tcp.c)
+ */
+#ifndef LWIP_TCP_KEEPALIVE
+#define LWIP_TCP_KEEPALIVE              0
+#endif
+
+/**
+ * LWIP_SO_RCVTIMEO==1: Enable SO_RCVTIMEO processing.
+ */
+#ifndef LWIP_SO_RCVTIMEO
+#define LWIP_SO_RCVTIMEO                0
+#endif
+
+/**
+ * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing.
+ */
+#ifndef LWIP_SO_RCVBUF
+#define LWIP_SO_RCVBUF                  0
+#endif
+
+/**
+ * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize.
+ */
+#ifndef RECV_BUFSIZE_DEFAULT
+#define RECV_BUFSIZE_DEFAULT            INT_MAX
+#endif
+
+/**
+ * SO_REUSE==1: Enable SO_REUSEADDR and SO_REUSEPORT options. DO NOT USE!
+ */
+#ifndef SO_REUSE
+#define SO_REUSE                        0
+#endif
+
+/*
+   ----------------------------------------
+   ---------- Statistics options ----------
+   ----------------------------------------
+*/
+/**
+ * LWIP_STATS==1: Enable statistics collection in lwip_stats.
+ */
+#ifndef LWIP_STATS
+#define LWIP_STATS                      1
+#endif
+
+#if LWIP_STATS
+
+/**
+ * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions.
+ */
+#ifndef LWIP_STATS_DISPLAY
+#define LWIP_STATS_DISPLAY              0
+#endif
+
+/**
+ * LINK_STATS==1: Enable link stats.
+ */
+#ifndef LINK_STATS
+#define LINK_STATS                      1
+#endif
+
+/**
+ * ETHARP_STATS==1: Enable etharp stats.
+ */
+#ifndef ETHARP_STATS
+#define ETHARP_STATS                    (LWIP_ARP)
+#endif
+
+/**
+ * IP_STATS==1: Enable IP stats.
+ */
+#ifndef IP_STATS
+#define IP_STATS                        1
+#endif
+
+/**
+ * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is
+ * on if using either frag or reass.
+ */
+#ifndef IPFRAG_STATS
+#define IPFRAG_STATS                    (IP_REASSEMBLY || IP_FRAG)
+#endif
+
+/**
+ * ICMP_STATS==1: Enable ICMP stats.
+ */
+#ifndef ICMP_STATS
+#define ICMP_STATS                      1
+#endif
+
+/**
+ * IGMP_STATS==1: Enable IGMP stats.
+ */
+#ifndef IGMP_STATS
+#define IGMP_STATS                      (LWIP_IGMP)
+#endif
+
+/**
+ * UDP_STATS==1: Enable UDP stats. Default is on if
+ * UDP enabled, otherwise off.
+ */
+#ifndef UDP_STATS
+#define UDP_STATS                       (LWIP_UDP)
+#endif
+
+/**
+ * TCP_STATS==1: Enable TCP stats. Default is on if TCP
+ * enabled, otherwise off.
+ */
+#ifndef TCP_STATS
+#define TCP_STATS                       (LWIP_TCP)
+#endif
+
+/**
+ * MEM_STATS==1: Enable mem.c stats.
+ */
+#ifndef MEM_STATS
+#define MEM_STATS                       ((MEM_LIBC_MALLOC == 0) && (MEM_USE_POOLS == 0))
+#endif
+
+/**
+ * MEMP_STATS==1: Enable memp.c pool stats.
+ */
+#ifndef MEMP_STATS
+#define MEMP_STATS                      (MEMP_MEM_MALLOC == 0)
+#endif
+
+/**
+ * SYS_STATS==1: Enable system stats (sem and mbox counts, etc).
+ */
+#ifndef SYS_STATS
+#define SYS_STATS                       (NO_SYS == 0)
+#endif
+
+#else
+
+#define LINK_STATS                      0
+#define IP_STATS                        0
+#define IPFRAG_STATS                    0
+#define ICMP_STATS                      0
+#define IGMP_STATS                      0
+#define UDP_STATS                       0
+#define TCP_STATS                       0
+#define MEM_STATS                       0
+#define MEMP_STATS                      0
+#define SYS_STATS                       0
+#define LWIP_STATS_DISPLAY              0
+
+#endif /* LWIP_STATS */
+
+/*
+   ---------------------------------
+   ---------- PPP options ----------
+   ---------------------------------
+*/
+/**
+ * PPP_SUPPORT==1: Enable PPP.
+ */
+#ifndef PPP_SUPPORT
+#define PPP_SUPPORT                     0
+#endif
+
+/**
+ * PPPOE_SUPPORT==1: Enable PPP Over Ethernet
+ */
+#ifndef PPPOE_SUPPORT
+#define PPPOE_SUPPORT                   0
+#endif
+
+/**
+ * PPPOS_SUPPORT==1: Enable PPP Over Serial
+ */
+#ifndef PPPOS_SUPPORT
+#define PPPOS_SUPPORT                   PPP_SUPPORT
+#endif
+
+#if PPP_SUPPORT
+
+/**
+ * NUM_PPP: Max PPP sessions.
+ */
+#ifndef NUM_PPP
+#define NUM_PPP                         1
+#endif
+
+/**
+ * PAP_SUPPORT==1: Support PAP.
+ */
+#ifndef PAP_SUPPORT
+#define PAP_SUPPORT                     0
+#endif
+
+/**
+ * CHAP_SUPPORT==1: Support CHAP.
+ */
+#ifndef CHAP_SUPPORT
+#define CHAP_SUPPORT                    0
+#endif
+
+/**
+ * MSCHAP_SUPPORT==1: Support MSCHAP. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef MSCHAP_SUPPORT
+#define MSCHAP_SUPPORT                  0
+#endif
+
+/**
+ * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef CBCP_SUPPORT
+#define CBCP_SUPPORT                    0
+#endif
+
+/**
+ * CCP_SUPPORT==1: Support CCP. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef CCP_SUPPORT
+#define CCP_SUPPORT                     0
+#endif
+
+/**
+ * VJ_SUPPORT==1: Support VJ header compression.
+ */
+#ifndef VJ_SUPPORT
+#define VJ_SUPPORT                      0
+#endif
+
+/**
+ * MD5_SUPPORT==1: Support MD5 (see also CHAP).
+ */
+#ifndef MD5_SUPPORT
+#define MD5_SUPPORT                     0
+#endif
+
+/*
+ * Timeouts
+ */
+#ifndef FSM_DEFTIMEOUT
+#define FSM_DEFTIMEOUT                  6       /* Timeout time in seconds */
+#endif
+
+#ifndef FSM_DEFMAXTERMREQS
+#define FSM_DEFMAXTERMREQS              2       /* Maximum Terminate-Request transmissions */
+#endif
+
+#ifndef FSM_DEFMAXCONFREQS
+#define FSM_DEFMAXCONFREQS              10      /* Maximum Configure-Request transmissions */
+#endif
+
+#ifndef FSM_DEFMAXNAKLOOPS
+#define FSM_DEFMAXNAKLOOPS              5       /* Maximum number of nak loops */
+#endif
+
+#ifndef UPAP_DEFTIMEOUT
+#define UPAP_DEFTIMEOUT                 6       /* Timeout (seconds) for retransmitting req */
+#endif
+
+#ifndef UPAP_DEFREQTIME
+#define UPAP_DEFREQTIME                 30      /* Time to wait for auth-req from peer */
+#endif
+
+#ifndef CHAP_DEFTIMEOUT
+#define CHAP_DEFTIMEOUT                 6       /* Timeout time in seconds */
+#endif
+
+#ifndef CHAP_DEFTRANSMITS
+#define CHAP_DEFTRANSMITS               10      /* max # times to send challenge */
+#endif
+
+/* Interval in seconds between keepalive echo requests, 0 to disable. */
+#ifndef LCP_ECHOINTERVAL
+#define LCP_ECHOINTERVAL                0
+#endif
+
+/* Number of unanswered echo requests before failure. */
+#ifndef LCP_MAXECHOFAILS
+#define LCP_MAXECHOFAILS                3
+#endif
+
+/* Max Xmit idle time (in jiffies) before resend flag char. */
+#ifndef PPP_MAXIDLEFLAG
+#define PPP_MAXIDLEFLAG                 100
+#endif
+
+/*
+ * Packet sizes
+ *
+ * Note - lcp shouldn't be allowed to negotiate stuff outside these
+ *    limits.  See lcp.h in the pppd directory.
+ * (XXX - these constants should simply be shared by lcp.c instead
+ *    of living in lcp.h)
+ */
+#define PPP_MTU                         1500     /* Default MTU (size of Info field) */
+#ifndef PPP_MAXMTU
+/* #define PPP_MAXMTU  65535 - (PPP_HDRLEN + PPP_FCSLEN) */
+#define PPP_MAXMTU                      1500 /* Largest MTU we allow */
+#endif
+#define PPP_MINMTU                      64
+#define PPP_MRU                         1500     /* default MRU = max length of info field */
+#define PPP_MAXMRU                      1500     /* Largest MRU we allow */
+#ifndef PPP_DEFMRU
+#define PPP_DEFMRU                      296             /* Try for this */
+#endif
+#define PPP_MINMRU                      128             /* No MRUs below this */
+
+#ifndef MAXNAMELEN
+#define MAXNAMELEN                      256     /* max length of hostname or name for auth */
+#endif
+#ifndef MAXSECRETLEN
+#define MAXSECRETLEN                    256     /* max length of password or secret */
+#endif
+
+#endif /* PPP_SUPPORT */
+
+/*
+   --------------------------------------
+   ---------- Checksum options ----------
+   --------------------------------------
+*/
+/**
+ * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.
+ */
+#ifndef CHECKSUM_GEN_IP
+#define CHECKSUM_GEN_IP                 1
+#endif
+ 
+/**
+ * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.
+ */
+#ifndef CHECKSUM_GEN_UDP
+#define CHECKSUM_GEN_UDP                1
+#endif
+ 
+/**
+ * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.
+ */
+#ifndef CHECKSUM_GEN_TCP
+#define CHECKSUM_GEN_TCP                1
+#endif
+ 
+/**
+ * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.
+ */
+#ifndef CHECKSUM_CHECK_IP
+#define CHECKSUM_CHECK_IP               1
+#endif
+ 
+/**
+ * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.
+ */
+#ifndef CHECKSUM_CHECK_UDP
+#define CHECKSUM_CHECK_UDP              1
+#endif
+
+/**
+ * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.
+ */
+#ifndef CHECKSUM_CHECK_TCP
+#define CHECKSUM_CHECK_TCP              1
+#endif
+
+/*
+   ---------------------------------------
+   ---------- Debugging options ----------
+   ---------------------------------------
+*/
+/**
+ * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is
+ * compared against this value. If it is smaller, then debugging
+ * messages are written.
+ */
+#ifndef LWIP_DBG_MIN_LEVEL
+#define LWIP_DBG_MIN_LEVEL              LWIP_DBG_LEVEL_ALL
+#endif
+
+/**
+ * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable
+ * debug messages of certain types.
+ */
+#ifndef LWIP_DBG_TYPES_ON
+#define LWIP_DBG_TYPES_ON               LWIP_DBG_ON
+#endif
+
+/**
+ * ETHARP_DEBUG: Enable debugging in etharp.c.
+ */
+#ifndef ETHARP_DEBUG
+#define ETHARP_DEBUG                    LWIP_DBG_OFF
+#endif
+
+/**
+ * NETIF_DEBUG: Enable debugging in netif.c.
+ */
+#ifndef NETIF_DEBUG
+#define NETIF_DEBUG                     LWIP_DBG_OFF
+#endif
+
+/**
+ * PBUF_DEBUG: Enable debugging in pbuf.c.
+ */
+#ifndef PBUF_DEBUG
+#define PBUF_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * API_LIB_DEBUG: Enable debugging in api_lib.c.
+ */
+#ifndef API_LIB_DEBUG
+#define API_LIB_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * API_MSG_DEBUG: Enable debugging in api_msg.c.
+ */
+#ifndef API_MSG_DEBUG
+#define API_MSG_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * SOCKETS_DEBUG: Enable debugging in sockets.c.
+ */
+#ifndef SOCKETS_DEBUG
+#define SOCKETS_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * ICMP_DEBUG: Enable debugging in icmp.c.
+ */
+#ifndef ICMP_DEBUG
+#define ICMP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * IGMP_DEBUG: Enable debugging in igmp.c.
+ */
+#ifndef IGMP_DEBUG
+#define IGMP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * INET_DEBUG: Enable debugging in inet.c.
+ */
+#ifndef INET_DEBUG
+#define INET_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * IP_DEBUG: Enable debugging for IP.
+ */
+#ifndef IP_DEBUG
+#define IP_DEBUG                        LWIP_DBG_OFF
+#endif
+
+/**
+ * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass.
+ */
+#ifndef IP_REASS_DEBUG
+#define IP_REASS_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * RAW_DEBUG: Enable debugging in raw.c.
+ */
+#ifndef RAW_DEBUG
+#define RAW_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * MEM_DEBUG: Enable debugging in mem.c.
+ */
+#ifndef MEM_DEBUG
+#define MEM_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * MEMP_DEBUG: Enable debugging in memp.c.
+ */
+#ifndef MEMP_DEBUG
+#define MEMP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * SYS_DEBUG: Enable debugging in sys.c.
+ */
+#ifndef SYS_DEBUG
+#define SYS_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_DEBUG: Enable debugging for TCP.
+ */
+#ifndef TCP_DEBUG
+#define TCP_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug.
+ */
+#ifndef TCP_INPUT_DEBUG
+#define TCP_INPUT_DEBUG                 LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit.
+ */
+#ifndef TCP_FR_DEBUG
+#define TCP_FR_DEBUG                    LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit
+ * timeout.
+ */
+#ifndef TCP_RTO_DEBUG
+#define TCP_RTO_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_CWND_DEBUG: Enable debugging for TCP congestion window.
+ */
+#ifndef TCP_CWND_DEBUG
+#define TCP_CWND_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating.
+ */
+#ifndef TCP_WND_DEBUG
+#define TCP_WND_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions.
+ */
+#ifndef TCP_OUTPUT_DEBUG
+#define TCP_OUTPUT_DEBUG                LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_RST_DEBUG: Enable debugging for TCP with the RST message.
+ */
+#ifndef TCP_RST_DEBUG
+#define TCP_RST_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths.
+ */
+#ifndef TCP_QLEN_DEBUG
+#define TCP_QLEN_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * UDP_DEBUG: Enable debugging in UDP.
+ */
+#ifndef UDP_DEBUG
+#define UDP_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * TCPIP_DEBUG: Enable debugging in tcpip.c.
+ */
+#ifndef TCPIP_DEBUG
+#define TCPIP_DEBUG                     LWIP_DBG_OFF
+#endif
+
+/**
+ * PPP_DEBUG: Enable debugging for PPP.
+ */
+#ifndef PPP_DEBUG
+#define PPP_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * SLIP_DEBUG: Enable debugging in slipif.c.
+ */
+#ifndef SLIP_DEBUG
+#define SLIP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * DHCP_DEBUG: Enable debugging in dhcp.c.
+ */
+#ifndef DHCP_DEBUG
+#define DHCP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * AUTOIP_DEBUG: Enable debugging in autoip.c.
+ */
+#ifndef AUTOIP_DEBUG
+#define AUTOIP_DEBUG                    LWIP_DBG_OFF
+#endif
+
+/**
+ * SNMP_MSG_DEBUG: Enable debugging for SNMP messages.
+ */
+#ifndef SNMP_MSG_DEBUG
+#define SNMP_MSG_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs.
+ */
+#ifndef SNMP_MIB_DEBUG
+#define SNMP_MIB_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * DNS_DEBUG: Enable debugging for DNS.
+ */
+#ifndef DNS_DEBUG
+#define DNS_DEBUG                       LWIP_DBG_OFF
+#endif
+
+#endif /* __LWIP_OPT_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/pbuf.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/pbuf.h
new file mode 100644
index 0000000..8380f65
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/pbuf.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef __LWIP_PBUF_H__
+#define __LWIP_PBUF_H__
+
+#include "lwip/opt.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PBUF_TRANSPORT_HLEN 20
+#define PBUF_IP_HLEN        20
+
+typedef enum {
+  PBUF_TRANSPORT,
+  PBUF_IP,
+  PBUF_LINK,
+  PBUF_RAW
+} pbuf_layer;
+
+typedef enum {
+  PBUF_RAM, /* pbuf data is stored in RAM */
+  PBUF_ROM, /* pbuf data is stored in ROM */
+  PBUF_REF, /* pbuf comes from the pbuf pool */
+  PBUF_POOL /* pbuf payload refers to RAM */
+} pbuf_type;
+
+
+/** indicates this packet's data should be immediately passed to the application */
+#define PBUF_FLAG_PUSH 0x01U
+
+struct pbuf {
+  /** next pbuf in singly linked pbuf chain */
+  struct pbuf *next;
+
+  /** pointer to the actual data in the buffer */
+  void *payload;
+  
+  /**
+   * total length of this buffer and all next buffers in chain
+   * belonging to the same packet.
+   *
+   * For non-queue packet chains this is the invariant:
+   * p->tot_len == p->len + (p->next? p->next->tot_len: 0)
+   */
+  u16_t tot_len;
+  
+  /** length of this buffer */
+  u16_t len;  
+
+  /** pbuf_type as u8_t instead of enum to save space */
+  u8_t /*pbuf_type*/ type;
+
+  /** misc flags */
+  u8_t flags;
+
+  /**
+   * the reference count always equals the number of pointers
+   * that refer to this pbuf. This can be pointers from an application,
+   * the stack itself, or pbuf->next pointers from a chain.
+   */
+  u16_t ref;
+  
+};
+
+/* Initializes the pbuf module. This call is empty for now, but may not be in future. */
+#define pbuf_init()
+
+struct pbuf *pbuf_alloc(pbuf_layer l, u16_t size, pbuf_type type);
+void pbuf_realloc(struct pbuf *p, u16_t size); 
+u8_t pbuf_header(struct pbuf *p, s16_t header_size);
+void pbuf_ref(struct pbuf *p);
+void pbuf_ref_chain(struct pbuf *p);
+u8_t pbuf_free(struct pbuf *p);
+u8_t pbuf_clen(struct pbuf *p);  
+void pbuf_cat(struct pbuf *head, struct pbuf *tail);
+void pbuf_chain(struct pbuf *head, struct pbuf *tail);
+struct pbuf *pbuf_dechain(struct pbuf *p);
+err_t pbuf_copy(struct pbuf *p_to, struct pbuf *p_from);
+u16_t pbuf_copy_partial(struct pbuf *p, void *dataptr, u16_t len, u16_t offset);
+err_t pbuf_take(struct pbuf *buf, const void *dataptr, u16_t len);
+struct pbuf *pbuf_coalesce(struct pbuf *p, pbuf_layer layer);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_PBUF_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/raw.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/raw.h
new file mode 100644
index 0000000..20b0a11
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/raw.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_RAW_H__
+#define __LWIP_RAW_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct raw_pcb {
+/* Common members of all PCB types */
+  IP_PCB;
+
+  struct raw_pcb *next;
+
+  u8_t protocol;
+
+  /* receive callback function
+   * @param arg user supplied argument (raw_pcb.recv_arg)
+   * @param pcb the raw_pcb which received data
+   * @param p the packet buffer that was received
+   * @param addr the remote IP address from which the packet was received
+   * @return 1 if the packet was 'eaten' (aka. deleted),
+   *         0 if the packet lives on
+   * If returning 1, the callback is responsible for freeing the pbuf
+   * if it's not used any more.
+   */
+  u8_t (* recv)(void *arg, struct raw_pcb *pcb, struct pbuf *p,
+    struct ip_addr *addr);
+  /* user-supplied argument for the recv callback */
+  void *recv_arg;
+};
+
+/* The following functions is the application layer interface to the
+   RAW code. */
+struct raw_pcb * raw_new        (u8_t proto);
+void             raw_remove     (struct raw_pcb *pcb);
+err_t            raw_bind       (struct raw_pcb *pcb, struct ip_addr *ipaddr);
+err_t            raw_connect    (struct raw_pcb *pcb, struct ip_addr *ipaddr);
+
+void             raw_recv       (struct raw_pcb *pcb,
+                                 u8_t (* recv)(void *arg, struct raw_pcb *pcb,
+                                              struct pbuf *p,
+                                              struct ip_addr *addr),
+                                 void *recv_arg);
+err_t            raw_sendto     (struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr);
+err_t            raw_send       (struct raw_pcb *pcb, struct pbuf *p);
+
+/* The following functions are the lower layer interface to RAW. */
+u8_t             raw_input      (struct pbuf *p, struct netif *inp);
+#define raw_init() /* Compatibility define, not init needed. */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_RAW */
+
+#endif /* __LWIP_RAW_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/sio.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/sio.h
new file mode 100644
index 0000000..28ae2f2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/sio.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ */
+
+/*
+ * This is the interface to the platform specific serial IO module
+ * It needs to be implemented by those platforms which need SLIP or PPP
+ */
+
+#ifndef __SIO_H__
+#define __SIO_H__
+
+#include "lwip/arch.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* If you want to define sio_fd_t elsewhere or differently,
+   define this in your cc.h file. */
+#ifndef __sio_fd_t_defined
+typedef void * sio_fd_t;
+#endif
+
+/* The following functions can be defined to something else in your cc.h file
+   or be implemented in your custom sio.c file. */
+
+#ifndef sio_open
+/**
+ * Opens a serial device for communication.
+ * 
+ * @param devnum device number
+ * @return handle to serial device if successful, NULL otherwise
+ */
+sio_fd_t sio_open(u8_t devnum);
+#endif
+
+#ifndef sio_send
+/**
+ * Sends a single character to the serial device.
+ * 
+ * @param c character to send
+ * @param fd serial device handle
+ * 
+ * @note This function will block until the character can be sent.
+ */
+void sio_send(u8_t c, sio_fd_t fd);
+#endif
+
+#ifndef sio_recv
+/**
+ * Receives a single character from the serial device.
+ * 
+ * @param fd serial device handle
+ * 
+ * @note This function will block until a character is received.
+ */
+u8_t sio_recv(sio_fd_t fd);
+#endif
+
+#ifndef sio_read
+/**
+ * Reads from the serial device.
+ * 
+ * @param fd serial device handle
+ * @param data pointer to data buffer for receiving
+ * @param len maximum length (in bytes) of data to receive
+ * @return number of bytes actually received - may be 0 if aborted by sio_read_abort
+ * 
+ * @note This function will block until data can be received. The blocking
+ * can be cancelled by calling sio_read_abort().
+ */
+u32_t sio_read(sio_fd_t fd, u8_t *data, u32_t len);
+#endif
+
+#ifndef sio_tryread
+/**
+ * Tries to read from the serial device. Same as sio_read but returns
+ * immediately if no data is available and never blocks.
+ * 
+ * @param fd serial device handle
+ * @param data pointer to data buffer for receiving
+ * @param len maximum length (in bytes) of data to receive
+ * @return number of bytes actually received
+ */
+u32_t sio_tryread(sio_fd_t fd, u8_t *data, u32_t len);
+#endif
+
+#ifndef sio_write
+/**
+ * Writes to the serial device.
+ * 
+ * @param fd serial device handle
+ * @param data pointer to data to send
+ * @param len length (in bytes) of data to send
+ * @return number of bytes actually sent
+ * 
+ * @note This function will block until all data can be sent.
+ */
+u32_t sio_write(sio_fd_t fd, u8_t *data, u32_t len);
+#endif
+
+#ifndef sio_read_abort
+/**
+ * Aborts a blocking sio_read() call.
+ * 
+ * @param fd serial device handle
+ */
+void sio_read_abort(sio_fd_t fd);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SIO_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/snmp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/snmp.h
new file mode 100644
index 0000000..dd03d5d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/snmp.h
@@ -0,0 +1,364 @@
+/*
+ * Copyright (c) 2001, 2002 Leon Woestenberg 
+ * Copyright (c) 2001, 2002 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Leon Woestenberg 
+ *
+ */
+#ifndef __LWIP_SNMP_H__
+#define __LWIP_SNMP_H__
+
+#include "lwip/opt.h"
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @see RFC1213, "MIB-II, 6. Definitions"
+ */
+enum snmp_ifType {
+  snmp_ifType_other=1,                /* none of the following */
+  snmp_ifType_regular1822,
+  snmp_ifType_hdh1822,
+  snmp_ifType_ddn_x25,
+  snmp_ifType_rfc877_x25,
+  snmp_ifType_ethernet_csmacd,
+  snmp_ifType_iso88023_csmacd,
+  snmp_ifType_iso88024_tokenBus,
+  snmp_ifType_iso88025_tokenRing,
+  snmp_ifType_iso88026_man,
+  snmp_ifType_starLan,
+  snmp_ifType_proteon_10Mbit,
+  snmp_ifType_proteon_80Mbit,
+  snmp_ifType_hyperchannel,
+  snmp_ifType_fddi,
+  snmp_ifType_lapb,
+  snmp_ifType_sdlc,
+  snmp_ifType_ds1,                    /* T-1 */
+  snmp_ifType_e1,                     /* european equiv. of T-1 */
+  snmp_ifType_basicISDN,
+  snmp_ifType_primaryISDN,            /* proprietary serial */
+  snmp_ifType_propPointToPointSerial,
+  snmp_ifType_ppp,
+  snmp_ifType_softwareLoopback,
+  snmp_ifType_eon,                    /* CLNP over IP [11] */
+  snmp_ifType_ethernet_3Mbit,
+  snmp_ifType_nsip,                   /* XNS over IP */
+  snmp_ifType_slip,                   /* generic SLIP */
+  snmp_ifType_ultra,                  /* ULTRA technologies */
+  snmp_ifType_ds3,                    /* T-3 */
+  snmp_ifType_sip,                    /* SMDS */
+  snmp_ifType_frame_relay
+};
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+/** SNMP "sysuptime" Interval */
+#define SNMP_SYSUPTIME_INTERVAL 10
+
+/** fixed maximum length for object identifier type */
+#define LWIP_SNMP_OBJ_ID_LEN 32
+
+/** internal object identifier representation */
+struct snmp_obj_id
+{
+  u8_t len;
+  s32_t id[LWIP_SNMP_OBJ_ID_LEN];
+};
+
+/* system */
+void snmp_set_sysdesr(u8_t* str, u8_t* len);
+void snmp_set_sysobjid(struct snmp_obj_id *oid);
+void snmp_get_sysobjid_ptr(struct snmp_obj_id **oid);
+void snmp_inc_sysuptime(void);
+void snmp_add_sysuptime(u32_t value);
+void snmp_get_sysuptime(u32_t *value);
+void snmp_set_syscontact(u8_t *ocstr, u8_t *ocstrlen);
+void snmp_set_sysname(u8_t *ocstr, u8_t *ocstrlen);
+void snmp_set_syslocation(u8_t *ocstr, u8_t *ocstrlen);
+
+/* network interface */
+void snmp_add_ifinoctets(struct netif *ni, u32_t value); 
+void snmp_inc_ifinucastpkts(struct netif *ni);
+void snmp_inc_ifinnucastpkts(struct netif *ni);
+void snmp_inc_ifindiscards(struct netif *ni);
+void snmp_add_ifoutoctets(struct netif *ni, u32_t value);
+void snmp_inc_ifoutucastpkts(struct netif *ni);
+void snmp_inc_ifoutnucastpkts(struct netif *ni);
+void snmp_inc_ifoutdiscards(struct netif *ni);
+void snmp_inc_iflist(void);
+void snmp_dec_iflist(void);
+
+/* ARP (for atTable and ipNetToMediaTable) */
+void snmp_insert_arpidx_tree(struct netif *ni, struct ip_addr *ip);
+void snmp_delete_arpidx_tree(struct netif *ni, struct ip_addr *ip);
+
+/* IP */
+void snmp_inc_ipinreceives(void);
+void snmp_inc_ipinhdrerrors(void);
+void snmp_inc_ipinaddrerrors(void);
+void snmp_inc_ipforwdatagrams(void);
+void snmp_inc_ipinunknownprotos(void);
+void snmp_inc_ipindiscards(void);
+void snmp_inc_ipindelivers(void);
+void snmp_inc_ipoutrequests(void);
+void snmp_inc_ipoutdiscards(void);
+void snmp_inc_ipoutnoroutes(void);
+void snmp_inc_ipreasmreqds(void);
+void snmp_inc_ipreasmoks(void);
+void snmp_inc_ipreasmfails(void);
+void snmp_inc_ipfragoks(void);
+void snmp_inc_ipfragfails(void);
+void snmp_inc_ipfragcreates(void);
+void snmp_inc_iproutingdiscards(void);
+void snmp_insert_ipaddridx_tree(struct netif *ni);
+void snmp_delete_ipaddridx_tree(struct netif *ni);
+void snmp_insert_iprteidx_tree(u8_t dflt, struct netif *ni);
+void snmp_delete_iprteidx_tree(u8_t dflt, struct netif *ni);
+
+/* ICMP */
+void snmp_inc_icmpinmsgs(void);
+void snmp_inc_icmpinerrors(void);
+void snmp_inc_icmpindestunreachs(void);
+void snmp_inc_icmpintimeexcds(void);
+void snmp_inc_icmpinparmprobs(void);
+void snmp_inc_icmpinsrcquenchs(void);
+void snmp_inc_icmpinredirects(void);
+void snmp_inc_icmpinechos(void);
+void snmp_inc_icmpinechoreps(void);
+void snmp_inc_icmpintimestamps(void);
+void snmp_inc_icmpintimestampreps(void);
+void snmp_inc_icmpinaddrmasks(void);
+void snmp_inc_icmpinaddrmaskreps(void);
+void snmp_inc_icmpoutmsgs(void);
+void snmp_inc_icmpouterrors(void);
+void snmp_inc_icmpoutdestunreachs(void);
+void snmp_inc_icmpouttimeexcds(void);
+void snmp_inc_icmpoutparmprobs(void);
+void snmp_inc_icmpoutsrcquenchs(void);
+void snmp_inc_icmpoutredirects(void); 
+void snmp_inc_icmpoutechos(void);
+void snmp_inc_icmpoutechoreps(void);
+void snmp_inc_icmpouttimestamps(void);
+void snmp_inc_icmpouttimestampreps(void);
+void snmp_inc_icmpoutaddrmasks(void);
+void snmp_inc_icmpoutaddrmaskreps(void);
+
+/* TCP */
+void snmp_inc_tcpactiveopens(void);
+void snmp_inc_tcppassiveopens(void);
+void snmp_inc_tcpattemptfails(void);
+void snmp_inc_tcpestabresets(void);
+void snmp_inc_tcpinsegs(void);
+void snmp_inc_tcpoutsegs(void);
+void snmp_inc_tcpretranssegs(void);
+void snmp_inc_tcpinerrs(void);
+void snmp_inc_tcpoutrsts(void);
+
+/* UDP */
+void snmp_inc_udpindatagrams(void);
+void snmp_inc_udpnoports(void);
+void snmp_inc_udpinerrors(void);
+void snmp_inc_udpoutdatagrams(void);
+void snmp_insert_udpidx_tree(struct udp_pcb *pcb);
+void snmp_delete_udpidx_tree(struct udp_pcb *pcb);
+
+/* SNMP */
+void snmp_inc_snmpinpkts(void);
+void snmp_inc_snmpoutpkts(void);
+void snmp_inc_snmpinbadversions(void);
+void snmp_inc_snmpinbadcommunitynames(void);
+void snmp_inc_snmpinbadcommunityuses(void);
+void snmp_inc_snmpinasnparseerrs(void);
+void snmp_inc_snmpintoobigs(void);
+void snmp_inc_snmpinnosuchnames(void);
+void snmp_inc_snmpinbadvalues(void);
+void snmp_inc_snmpinreadonlys(void);
+void snmp_inc_snmpingenerrs(void);
+void snmp_add_snmpintotalreqvars(u8_t value);
+void snmp_add_snmpintotalsetvars(u8_t value);
+void snmp_inc_snmpingetrequests(void);
+void snmp_inc_snmpingetnexts(void);
+void snmp_inc_snmpinsetrequests(void);
+void snmp_inc_snmpingetresponses(void);
+void snmp_inc_snmpintraps(void);
+void snmp_inc_snmpouttoobigs(void);
+void snmp_inc_snmpoutnosuchnames(void);
+void snmp_inc_snmpoutbadvalues(void);
+void snmp_inc_snmpoutgenerrs(void);
+void snmp_inc_snmpoutgetrequests(void);
+void snmp_inc_snmpoutgetnexts(void);
+void snmp_inc_snmpoutsetrequests(void);
+void snmp_inc_snmpoutgetresponses(void);
+void snmp_inc_snmpouttraps(void);
+void snmp_get_snmpgrpid_ptr(struct snmp_obj_id **oid);
+void snmp_set_snmpenableauthentraps(u8_t *value);
+void snmp_get_snmpenableauthentraps(u8_t *value);
+
+/* LWIP_SNMP support not available */
+/* define everything to be empty */
+#else
+
+/* system */
+#define snmp_set_sysdesr(str, len)
+#define snmp_set_sysobjid(oid);
+#define snmp_get_sysobjid_ptr(oid)
+#define snmp_inc_sysuptime()
+#define snmp_add_sysuptime(value)
+#define snmp_get_sysuptime(value)
+#define snmp_set_syscontact(ocstr, ocstrlen);
+#define snmp_set_sysname(ocstr, ocstrlen);
+#define snmp_set_syslocation(ocstr, ocstrlen);
+
+/* network interface */
+#define snmp_add_ifinoctets(ni,value) 
+#define snmp_inc_ifinucastpkts(ni)
+#define snmp_inc_ifinnucastpkts(ni)
+#define snmp_inc_ifindiscards(ni)
+#define snmp_add_ifoutoctets(ni,value)
+#define snmp_inc_ifoutucastpkts(ni)
+#define snmp_inc_ifoutnucastpkts(ni)
+#define snmp_inc_ifoutdiscards(ni)
+#define snmp_inc_iflist()
+#define snmp_dec_iflist()
+
+/* ARP */
+#define snmp_insert_arpidx_tree(ni,ip)
+#define snmp_delete_arpidx_tree(ni,ip)
+
+/* IP */
+#define snmp_inc_ipinreceives()
+#define snmp_inc_ipinhdrerrors()
+#define snmp_inc_ipinaddrerrors()
+#define snmp_inc_ipforwdatagrams()
+#define snmp_inc_ipinunknownprotos()
+#define snmp_inc_ipindiscards()
+#define snmp_inc_ipindelivers()
+#define snmp_inc_ipoutrequests()
+#define snmp_inc_ipoutdiscards()
+#define snmp_inc_ipoutnoroutes()
+#define snmp_inc_ipreasmreqds()
+#define snmp_inc_ipreasmoks()
+#define snmp_inc_ipreasmfails()
+#define snmp_inc_ipfragoks()
+#define snmp_inc_ipfragfails()
+#define snmp_inc_ipfragcreates()
+#define snmp_inc_iproutingdiscards()
+#define snmp_insert_ipaddridx_tree(ni)
+#define snmp_delete_ipaddridx_tree(ni)
+#define snmp_insert_iprteidx_tree(dflt, ni)
+#define snmp_delete_iprteidx_tree(dflt, ni)
+
+/* ICMP */
+#define snmp_inc_icmpinmsgs()
+#define snmp_inc_icmpinerrors() 
+#define snmp_inc_icmpindestunreachs() 
+#define snmp_inc_icmpintimeexcds()
+#define snmp_inc_icmpinparmprobs() 
+#define snmp_inc_icmpinsrcquenchs() 
+#define snmp_inc_icmpinredirects() 
+#define snmp_inc_icmpinechos() 
+#define snmp_inc_icmpinechoreps()
+#define snmp_inc_icmpintimestamps() 
+#define snmp_inc_icmpintimestampreps()
+#define snmp_inc_icmpinaddrmasks()
+#define snmp_inc_icmpinaddrmaskreps()
+#define snmp_inc_icmpoutmsgs()
+#define snmp_inc_icmpouterrors()
+#define snmp_inc_icmpoutdestunreachs() 
+#define snmp_inc_icmpouttimeexcds() 
+#define snmp_inc_icmpoutparmprobs()
+#define snmp_inc_icmpoutsrcquenchs()
+#define snmp_inc_icmpoutredirects() 
+#define snmp_inc_icmpoutechos() 
+#define snmp_inc_icmpoutechoreps()
+#define snmp_inc_icmpouttimestamps()
+#define snmp_inc_icmpouttimestampreps()
+#define snmp_inc_icmpoutaddrmasks()
+#define snmp_inc_icmpoutaddrmaskreps()
+/* TCP */
+#define snmp_inc_tcpactiveopens()
+#define snmp_inc_tcppassiveopens()
+#define snmp_inc_tcpattemptfails()
+#define snmp_inc_tcpestabresets()
+#define snmp_inc_tcpinsegs()
+#define snmp_inc_tcpoutsegs()
+#define snmp_inc_tcpretranssegs()
+#define snmp_inc_tcpinerrs()
+#define snmp_inc_tcpoutrsts()
+
+/* UDP */
+#define snmp_inc_udpindatagrams()
+#define snmp_inc_udpnoports()
+#define snmp_inc_udpinerrors()
+#define snmp_inc_udpoutdatagrams()
+#define snmp_insert_udpidx_tree(pcb)
+#define snmp_delete_udpidx_tree(pcb)
+
+/* SNMP */
+#define snmp_inc_snmpinpkts()
+#define snmp_inc_snmpoutpkts()
+#define snmp_inc_snmpinbadversions()
+#define snmp_inc_snmpinbadcommunitynames()
+#define snmp_inc_snmpinbadcommunityuses()
+#define snmp_inc_snmpinasnparseerrs()
+#define snmp_inc_snmpintoobigs()
+#define snmp_inc_snmpinnosuchnames()
+#define snmp_inc_snmpinbadvalues()
+#define snmp_inc_snmpinreadonlys()
+#define snmp_inc_snmpingenerrs()
+#define snmp_add_snmpintotalreqvars(value)
+#define snmp_add_snmpintotalsetvars(value)
+#define snmp_inc_snmpingetrequests()
+#define snmp_inc_snmpingetnexts()
+#define snmp_inc_snmpinsetrequests()
+#define snmp_inc_snmpingetresponses()
+#define snmp_inc_snmpintraps()
+#define snmp_inc_snmpouttoobigs()
+#define snmp_inc_snmpoutnosuchnames()
+#define snmp_inc_snmpoutbadvalues()
+#define snmp_inc_snmpoutgenerrs()
+#define snmp_inc_snmpoutgetrequests()
+#define snmp_inc_snmpoutgetnexts()
+#define snmp_inc_snmpoutsetrequests()
+#define snmp_inc_snmpoutgetresponses()
+#define snmp_inc_snmpouttraps()
+#define snmp_get_snmpgrpid_ptr(oid)
+#define snmp_set_snmpenableauthentraps(value)
+#define snmp_get_snmpenableauthentraps(value)
+
+#endif /* LWIP_SNMP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_SNMP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/snmp_asn1.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/snmp_asn1.h
new file mode 100644
index 0000000..8a60288
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/snmp_asn1.h
@@ -0,0 +1,101 @@
+/**
+ * @file
+ * Abstract Syntax Notation One (ISO 8824, 8825) codec.
+ */
+ 
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#ifndef __LWIP_SNMP_ASN1_H__
+#define __LWIP_SNMP_ASN1_H__
+
+#include "lwip/opt.h"
+#include "lwip/err.h"
+#include "lwip/pbuf.h"
+#include "lwip/snmp.h"
+
+#if LWIP_SNMP
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SNMP_ASN1_UNIV   (!0x80 | !0x40)
+#define SNMP_ASN1_APPLIC (!0x80 |  0x40)
+#define SNMP_ASN1_CONTXT ( 0x80 | !0x40)
+
+#define SNMP_ASN1_CONSTR (0x20)
+#define SNMP_ASN1_PRIMIT (!0x20)
+
+/* universal tags */
+#define SNMP_ASN1_INTEG  2
+#define SNMP_ASN1_OC_STR 4
+#define SNMP_ASN1_NUL    5
+#define SNMP_ASN1_OBJ_ID 6
+#define SNMP_ASN1_SEQ    16
+
+/* application specific (SNMP) tags */
+#define SNMP_ASN1_IPADDR 0    /* octet string size(4) */
+#define SNMP_ASN1_COUNTER 1   /* u32_t */
+#define SNMP_ASN1_GAUGE 2     /* u32_t */
+#define SNMP_ASN1_TIMETICKS 3 /* u32_t */
+#define SNMP_ASN1_OPAQUE 4    /* octet string */
+
+/* context specific (SNMP) tags */
+#define SNMP_ASN1_PDU_GET_REQ 0
+#define SNMP_ASN1_PDU_GET_NEXT_REQ 1
+#define SNMP_ASN1_PDU_GET_RESP 2
+#define SNMP_ASN1_PDU_SET_REQ 3
+#define SNMP_ASN1_PDU_TRAP 4
+
+err_t snmp_asn1_dec_type(struct pbuf *p, u16_t ofs, u8_t *type);
+err_t snmp_asn1_dec_length(struct pbuf *p, u16_t ofs, u8_t *octets_used, u16_t *length);
+err_t snmp_asn1_dec_u32t(struct pbuf *p, u16_t ofs, u16_t len, u32_t *value);
+err_t snmp_asn1_dec_s32t(struct pbuf *p, u16_t ofs, u16_t len, s32_t *value);
+err_t snmp_asn1_dec_oid(struct pbuf *p, u16_t ofs, u16_t len, struct snmp_obj_id *oid);
+err_t snmp_asn1_dec_raw(struct pbuf *p, u16_t ofs, u16_t len, u16_t raw_len, u8_t *raw);
+
+void snmp_asn1_enc_length_cnt(u16_t length, u8_t *octets_needed);
+void snmp_asn1_enc_u32t_cnt(u32_t value, u16_t *octets_needed);
+void snmp_asn1_enc_s32t_cnt(s32_t value, u16_t *octets_needed);
+void snmp_asn1_enc_oid_cnt(u8_t ident_len, s32_t *ident, u16_t *octets_needed);
+err_t snmp_asn1_enc_type(struct pbuf *p, u16_t ofs, u8_t type);
+err_t snmp_asn1_enc_length(struct pbuf *p, u16_t ofs, u16_t length);
+err_t snmp_asn1_enc_u32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, u32_t value);
+err_t snmp_asn1_enc_s32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, s32_t value);
+err_t snmp_asn1_enc_oid(struct pbuf *p, u16_t ofs, u8_t ident_len, s32_t *ident);
+err_t snmp_asn1_enc_raw(struct pbuf *p, u16_t ofs, u8_t raw_len, u8_t *raw);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_SNMP */
+
+#endif /* __LWIP_SNMP_ASN1_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/snmp_msg.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/snmp_msg.h
new file mode 100644
index 0000000..b2f69c4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/snmp_msg.h
@@ -0,0 +1,311 @@
+/**
+ * @file
+ * SNMP Agent message handling structures.
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#ifndef __LWIP_SNMP_MSG_H__
+#define __LWIP_SNMP_MSG_H__
+
+#include "lwip/opt.h"
+#include "lwip/snmp.h"
+#include "lwip/snmp_structs.h"
+
+#if LWIP_SNMP
+
+#if SNMP_PRIVATE_MIB
+#include "private_mib.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* The listen port of the SNMP agent. Clients have to make their requests to
+   this port. Most standard clients won't work if you change this! */
+#ifndef SNMP_IN_PORT
+#define SNMP_IN_PORT 161
+#endif
+/* The remote port the SNMP agent sends traps to. Most standard trap sinks won't
+   work if you change this! */
+#ifndef SNMP_TRAP_PORT
+#define SNMP_TRAP_PORT 162
+#endif
+
+#define SNMP_ES_NOERROR 0
+#define SNMP_ES_TOOBIG 1
+#define SNMP_ES_NOSUCHNAME 2
+#define SNMP_ES_BADVALUE 3
+#define SNMP_ES_READONLY 4
+#define SNMP_ES_GENERROR 5
+
+#define SNMP_GENTRAP_COLDSTART 0
+#define SNMP_GENTRAP_WARMSTART 1
+#define SNMP_GENTRAP_AUTHFAIL 4
+#define SNMP_GENTRAP_ENTERPRISESPC 6
+
+struct snmp_varbind
+{
+  /* next pointer, NULL for last in list */
+  struct snmp_varbind *next;
+  /* previous pointer, NULL for first in list */
+  struct snmp_varbind *prev;
+
+  /* object identifier length (in s32_t) */
+  u8_t ident_len;
+  /* object identifier array */
+  s32_t *ident;
+
+  /* object value ASN1 type */
+  u8_t value_type;
+  /* object value length (in u8_t) */
+  u8_t value_len;
+  /* object value */
+  void *value;
+
+  /* encoding varbind seq length length */
+  u8_t seqlenlen;
+  /* encoding object identifier length length */
+  u8_t olenlen;
+  /* encoding object value length length */
+  u8_t vlenlen;
+  /* encoding varbind seq length */
+  u16_t seqlen;
+  /* encoding object identifier length */
+  u16_t olen;
+  /* encoding object value length */
+  u16_t vlen;
+};
+
+struct snmp_varbind_root
+{
+  struct snmp_varbind *head;
+  struct snmp_varbind *tail;
+  /* number of variable bindings in list */
+  u8_t count;
+  /* encoding varbind-list seq length length */
+  u8_t seqlenlen;
+  /* encoding varbind-list seq length */
+  u16_t seqlen;
+};
+
+/** output response message header length fields */
+struct snmp_resp_header_lengths
+{
+  /* encoding error-index length length */
+  u8_t erridxlenlen;
+  /* encoding error-status length length */
+  u8_t errstatlenlen;
+  /* encoding request id length length */
+  u8_t ridlenlen;
+  /* encoding pdu length length */
+  u8_t pdulenlen;
+  /* encoding community length length */
+  u8_t comlenlen;
+  /* encoding version length length */
+  u8_t verlenlen;
+  /* encoding sequence length length */
+  u8_t seqlenlen;
+
+  /* encoding error-index length */
+  u16_t erridxlen;
+  /* encoding error-status length */
+  u16_t errstatlen;
+  /* encoding request id length */
+  u16_t ridlen;
+  /* encoding pdu length */
+  u16_t pdulen;
+  /* encoding community length */
+  u16_t comlen;
+  /* encoding version length */
+  u16_t verlen;
+  /* encoding sequence length */
+  u16_t seqlen;
+};
+
+/** output response message header length fields */
+struct snmp_trap_header_lengths
+{
+  /* encoding timestamp length length */
+  u8_t tslenlen;
+  /* encoding specific-trap length length */
+  u8_t strplenlen;
+  /* encoding generic-trap length length */
+  u8_t gtrplenlen;
+  /* encoding agent-addr length length */
+  u8_t aaddrlenlen;
+  /* encoding enterprise-id length length */
+  u8_t eidlenlen;
+  /* encoding pdu length length */
+  u8_t pdulenlen;
+  /* encoding community length length */
+  u8_t comlenlen;
+  /* encoding version length length */
+  u8_t verlenlen;
+  /* encoding sequence length length */
+  u8_t seqlenlen;
+
+  /* encoding timestamp length */
+  u16_t tslen;
+  /* encoding specific-trap length */
+  u16_t strplen;
+  /* encoding generic-trap length */
+  u16_t gtrplen;
+  /* encoding agent-addr length */
+  u16_t aaddrlen;
+  /* encoding enterprise-id length */
+  u16_t eidlen;
+  /* encoding pdu length */
+  u16_t pdulen;
+  /* encoding community length */
+  u16_t comlen;
+  /* encoding version length */
+  u16_t verlen;
+  /* encoding sequence length */
+  u16_t seqlen;
+};
+
+/* Accepting new SNMP messages. */
+#define SNMP_MSG_EMPTY                 0
+/* Search for matching object for variable binding. */
+#define SNMP_MSG_SEARCH_OBJ            1
+/* Perform SNMP operation on in-memory object.
+   Pass-through states, for symmetry only. */
+#define SNMP_MSG_INTERNAL_GET_OBJDEF   2
+#define SNMP_MSG_INTERNAL_GET_VALUE    3
+#define SNMP_MSG_INTERNAL_SET_TEST     4
+#define SNMP_MSG_INTERNAL_GET_OBJDEF_S 5
+#define SNMP_MSG_INTERNAL_SET_VALUE    6
+/* Perform SNMP operation on object located externally.
+   In theory this could be used for building a proxy agent.
+   Practical use is for an enterprise spc. app. gateway. */
+#define SNMP_MSG_EXTERNAL_GET_OBJDEF   7
+#define SNMP_MSG_EXTERNAL_GET_VALUE    8
+#define SNMP_MSG_EXTERNAL_SET_TEST     9
+#define SNMP_MSG_EXTERNAL_GET_OBJDEF_S 10
+#define SNMP_MSG_EXTERNAL_SET_VALUE    11
+
+#define SNMP_COMMUNITY_STR_LEN 64
+struct snmp_msg_pstat
+{
+  /* lwIP local port (161) binding */
+  struct udp_pcb *pcb;
+  /* source IP address */
+  struct ip_addr sip;
+  /* source UDP port */
+  u16_t sp;
+  /* request type */
+  u8_t rt;
+  /* request ID */
+  s32_t rid;
+  /* error status */
+  s32_t error_status;
+  /* error index */
+  s32_t error_index;
+  /* community name (zero terminated) */
+  u8_t community[SNMP_COMMUNITY_STR_LEN + 1];
+  /* community string length (exclusive zero term) */
+  u8_t com_strlen;
+  /* one out of MSG_EMPTY, MSG_DEMUX, MSG_INTERNAL, MSG_EXTERNAL_x */
+  u8_t state;
+  /* saved arguments for MSG_EXTERNAL_x */
+  struct mib_external_node *ext_mib_node;
+  struct snmp_name_ptr ext_name_ptr;
+  struct obj_def ext_object_def;
+  struct snmp_obj_id ext_oid;
+  /* index into input variable binding list */
+  u8_t vb_idx;
+  /* ptr into input variable binding list */
+  struct snmp_varbind *vb_ptr;
+  /* list of variable bindings from input */
+  struct snmp_varbind_root invb;
+  /* list of variable bindings to output */
+  struct snmp_varbind_root outvb;
+  /* output response lengths used in ASN encoding */
+  struct snmp_resp_header_lengths rhl;
+};
+
+struct snmp_msg_trap
+{
+  /* lwIP local port (161) binding */
+  struct udp_pcb *pcb;
+  /* destination IP address in network order */
+  struct ip_addr dip;
+
+  /* source enterprise ID (sysObjectID) */
+  struct snmp_obj_id *enterprise;
+  /* source IP address, raw network order format */
+  u8_t sip_raw[4];
+  /* generic trap code */
+  u32_t gen_trap;
+  /* specific trap code */
+  u32_t spc_trap;
+  /* timestamp */
+  u32_t ts;
+  /* list of variable bindings to output */
+  struct snmp_varbind_root outvb;
+  /* output trap lengths used in ASN encoding */
+  struct snmp_trap_header_lengths thl;
+};
+
+/** Agent Version constant, 0 = v1 oddity */
+extern const s32_t snmp_version;
+/** Agent default "public" community string */
+extern const char snmp_publiccommunity[7];
+
+extern struct snmp_msg_trap trap_msg;
+
+/** Agent setup, start listening to port 161. */
+void snmp_init(void);
+void snmp_trap_dst_enable(u8_t dst_idx, u8_t enable);
+void snmp_trap_dst_ip_set(u8_t dst_idx, struct ip_addr *dst);
+
+/** Varbind-list functions. */
+struct snmp_varbind* snmp_varbind_alloc(struct snmp_obj_id *oid, u8_t type, u8_t len);
+void snmp_varbind_free(struct snmp_varbind *vb);
+void snmp_varbind_list_free(struct snmp_varbind_root *root);
+void snmp_varbind_tail_add(struct snmp_varbind_root *root, struct snmp_varbind *vb);
+struct snmp_varbind* snmp_varbind_tail_remove(struct snmp_varbind_root *root);
+
+/** Handle an internal (recv) or external (private response) event. */
+void snmp_msg_event(u8_t request_id);
+err_t snmp_send_response(struct snmp_msg_pstat *m_stat);
+err_t snmp_send_trap(s8_t generic_trap, struct snmp_obj_id *eoid, s32_t specific_trap);
+void snmp_coldstart_trap(void);
+void snmp_authfail_trap(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_SNMP */
+
+#endif /* __LWIP_SNMP_MSG_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/snmp_structs.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/snmp_structs.h
new file mode 100644
index 0000000..9f3f8a9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/snmp_structs.h
@@ -0,0 +1,262 @@
+/**
+ * @file
+ * Generic MIB tree structures.
+ *
+ * @todo namespace prefixes
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#ifndef __LWIP_SNMP_STRUCTS_H__
+#define __LWIP_SNMP_STRUCTS_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/snmp.h"
+
+#if SNMP_PRIVATE_MIB
+#include "private_mib.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* MIB object instance */
+#define MIB_OBJECT_NONE 0 
+#define MIB_OBJECT_SCALAR 1
+#define MIB_OBJECT_TAB 2
+
+/* MIB object access */
+#define MIB_OBJECT_READ_ONLY 0
+#define MIB_OBJECT_READ_WRITE 1
+#define MIB_OBJECT_WRITE_ONLY 2
+#define MIB_OBJECT_NOT_ACCESSIBLE 3
+
+/** object definition returned by (get_object_def)() */
+struct obj_def
+{
+  /* MIB_OBJECT_NONE (0), MIB_OBJECT_SCALAR (1), MIB_OBJECT_TAB (2) */
+  u8_t instance;
+  /* 0 read-only, 1 read-write, 2 write-only, 3 not-accessible */
+  u8_t access;
+  /* ASN type for this object */
+  u8_t asn_type;
+  /* value length (host length) */
+  u16_t v_len;
+  /* length of instance part of supplied object identifier */
+  u8_t  id_inst_len;
+  /* instance part of supplied object identifier */
+  s32_t *id_inst_ptr;
+};
+
+struct snmp_name_ptr
+{
+  u8_t ident_len;
+  s32_t *ident;
+};
+
+/** MIB const scalar (.0) node */
+#define MIB_NODE_SC 0x01
+/** MIB const array node */
+#define MIB_NODE_AR 0x02
+/** MIB array node (mem_malloced from RAM) */
+#define MIB_NODE_RA 0x03
+/** MIB list root node (mem_malloced from RAM) */
+#define MIB_NODE_LR 0x04
+/** MIB node for external objects */
+#define MIB_NODE_EX 0x05
+
+/** node "base class" layout, the mandatory fields for a node  */
+struct mib_node
+{
+  /** returns struct obj_def for the given object identifier */
+  void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od);
+  /** returns object value for the given object identifier,
+     @note the caller must allocate at least len bytes for the value */
+  void (*get_value)(struct obj_def *od, u16_t len, void *value);
+  /** tests length and/or range BEFORE setting */
+  u8_t (*set_test)(struct obj_def *od, u16_t len, void *value);
+  /** sets object value, only to be called when set_test()  */
+  void (*set_value)(struct obj_def *od, u16_t len, void *value);  
+  /** One out of MIB_NODE_AR, MIB_NODE_LR or MIB_NODE_EX */
+  const u8_t node_type;
+  /* array or max list length */
+  const u16_t maxlength;
+};
+
+/** derived node for scalars .0 index */
+typedef struct mib_node mib_scalar_node;
+
+/** derived node, points to a fixed size const array
+    of sub-identifiers plus a 'child' pointer */
+struct mib_array_node
+{
+  /* inherited "base class" members */
+  void (* const get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od);
+  void (* const get_value)(struct obj_def *od, u16_t len, void *value);
+  u8_t (*set_test)(struct obj_def *od, u16_t len, void *value);
+  void (*set_value)(struct obj_def *od, u16_t len, void *value);
+
+  const u8_t node_type;
+  const u16_t maxlength;
+
+  /* aditional struct members */
+  const s32_t *objid;
+  struct mib_node* const *nptr;
+};
+
+/** derived node, points to a fixed size mem_malloced array
+    of sub-identifiers plus a 'child' pointer */
+struct mib_ram_array_node
+{
+  /* inherited "base class" members */
+  void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od);
+  void (*get_value)(struct obj_def *od, u16_t len, void *value);
+  u8_t (*set_test)(struct obj_def *od, u16_t len, void *value);
+  void (*set_value)(struct obj_def *od, u16_t len, void *value);
+
+  u8_t node_type;
+  u16_t maxlength;
+
+  /* aditional struct members */
+  s32_t *objid;
+  struct mib_node **nptr;
+};
+
+struct mib_list_node
+{
+  struct mib_list_node *prev;  
+  struct mib_list_node *next;
+  s32_t objid;
+  struct mib_node *nptr;
+};
+
+/** derived node, points to a doubly linked list
+    of sub-identifiers plus a 'child' pointer */
+struct mib_list_rootnode
+{
+  /* inherited "base class" members */
+  void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od);
+  void (*get_value)(struct obj_def *od, u16_t len, void *value);
+  u8_t (*set_test)(struct obj_def *od, u16_t len, void *value);
+  void (*set_value)(struct obj_def *od, u16_t len, void *value);
+
+  u8_t node_type;
+  u16_t maxlength;
+
+  /* aditional struct members */
+  struct mib_list_node *head;
+  struct mib_list_node *tail;
+  /* counts list nodes in list  */
+  u16_t count;
+};
+
+/** derived node, has access functions for mib object in external memory or device
+    using 'tree_level' and 'idx', with a range 0 .. (level_length() - 1) */
+struct mib_external_node
+{
+  /* inherited "base class" members */
+  void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od);
+  void (*get_value)(struct obj_def *od, u16_t len, void *value);
+  u8_t (*set_test)(struct obj_def *od, u16_t len, void *value);
+  void (*set_value)(struct obj_def *od, u16_t len, void *value);
+
+  u8_t node_type;
+  u16_t maxlength;
+
+  /* aditional struct members */
+  /** points to an extenal (in memory) record of some sort of addressing
+      information, passed to and interpreted by the funtions below */
+  void* addr_inf;
+  /** tree levels under this node */
+  u8_t tree_levels;
+  /** number of objects at this level */
+  u16_t (*level_length)(void* addr_inf, u8_t level);
+  /** compares object sub identifier with external id
+      return zero when equal, nonzero when unequal */
+  s32_t (*ident_cmp)(void* addr_inf, u8_t level, u16_t idx, s32_t sub_id);
+  void (*get_objid)(void* addr_inf, u8_t level, u16_t idx, s32_t *sub_id);
+
+  /** async Questions */
+  void (*get_object_def_q)(void* addr_inf, u8_t rid, u8_t ident_len, s32_t *ident);
+  void (*get_value_q)(u8_t rid, struct obj_def *od);
+  void (*set_test_q)(u8_t rid, struct obj_def *od);
+  void (*set_value_q)(u8_t rid, struct obj_def *od, u16_t len, void *value);
+  /** async Answers */
+  void (*get_object_def_a)(u8_t rid, u8_t ident_len, s32_t *ident, struct obj_def *od);
+  void (*get_value_a)(u8_t rid, struct obj_def *od, u16_t len, void *value);
+  u8_t (*set_test_a)(u8_t rid, struct obj_def *od, u16_t len, void *value);
+  void (*set_value_a)(u8_t rid, struct obj_def *od, u16_t len, void *value);
+  /** async Panic Close (agent returns error reply, 
+      e.g. used for external transaction cleanup) */
+  void (*get_object_def_pc)(u8_t rid, u8_t ident_len, s32_t *ident);
+  void (*get_value_pc)(u8_t rid, struct obj_def *od);
+  void (*set_test_pc)(u8_t rid, struct obj_def *od);
+  void (*set_value_pc)(u8_t rid, struct obj_def *od);
+};
+
+/** export MIB tree from mib2.c */
+extern const struct mib_array_node internet;
+
+/** dummy function pointers for non-leaf MIB nodes from mib2.c */
+void noleafs_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+void noleafs_get_value(struct obj_def *od, u16_t len, void *value);
+u8_t noleafs_set_test(struct obj_def *od, u16_t len, void *value);
+void noleafs_set_value(struct obj_def *od, u16_t len, void *value);
+
+void snmp_oidtoip(s32_t *ident, struct ip_addr *ip);
+void snmp_iptooid(struct ip_addr *ip, s32_t *ident);
+void snmp_ifindextonetif(s32_t ifindex, struct netif **netif);
+void snmp_netiftoifindex(struct netif *netif, s32_t *ifidx);
+
+struct mib_list_node* snmp_mib_ln_alloc(s32_t id);
+void snmp_mib_ln_free(struct mib_list_node *ln);
+struct mib_list_rootnode* snmp_mib_lrn_alloc(void);
+void snmp_mib_lrn_free(struct mib_list_rootnode *lrn);
+
+s8_t snmp_mib_node_insert(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **insn);
+s8_t snmp_mib_node_find(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **fn);
+struct mib_list_rootnode *snmp_mib_node_delete(struct mib_list_rootnode *rn, struct mib_list_node *n);
+
+struct mib_node* snmp_search_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_name_ptr *np);
+struct mib_node* snmp_expand_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret);
+u8_t snmp_iso_prefix_tst(u8_t ident_len, s32_t *ident);
+u8_t snmp_iso_prefix_expand(u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_SNMP */
+
+#endif /* __LWIP_SNMP_STRUCTS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/sockets.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/sockets.h
new file mode 100644
index 0000000..7b52e15
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/sockets.h
@@ -0,0 +1,357 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+#ifndef __LWIP_SOCKETS_H__
+#define __LWIP_SOCKETS_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+
+#include  /* for size_t */
+
+#include "lwip/ip_addr.h"
+#include "lwip/inet.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* members are in network byte order */
+struct sockaddr_in {
+  u8_t sin_len;
+  u8_t sin_family;
+  u16_t sin_port;
+  struct in_addr sin_addr;
+  char sin_zero[8];
+};
+
+struct sockaddr {
+  u8_t sa_len;
+  u8_t sa_family;
+  char sa_data[14];
+};
+
+#ifndef socklen_t
+#  define socklen_t u32_t
+#endif
+
+/* Socket protocol types (TCP/UDP/RAW) */
+#define SOCK_STREAM     1
+#define SOCK_DGRAM      2
+#define SOCK_RAW        3
+
+/*
+ * Option flags per-socket. These must match the SOF_ flags in ip.h!
+ */
+#define  SO_DEBUG       0x0001 /* Unimplemented: turn on debugging info recording */
+#define  SO_ACCEPTCONN  0x0002 /* socket has had listen() */
+#define  SO_REUSEADDR   0x0004 /* Unimplemented: allow local address reuse */
+#define  SO_KEEPALIVE   0x0008 /* keep connections alive */
+#define  SO_DONTROUTE   0x0010 /* Unimplemented: just use interface addresses */
+#define  SO_BROADCAST   0x0020 /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */
+#define  SO_USELOOPBACK 0x0040 /* Unimplemented: bypass hardware when possible */
+#define  SO_LINGER      0x0080 /* linger on close if data present */
+#define  SO_OOBINLINE   0x0100 /* Unimplemented: leave received OOB data in line */
+#define  SO_REUSEPORT   0x0200 /* Unimplemented: allow local address & port reuse */
+
+#define SO_DONTLINGER   ((int)(~SO_LINGER))
+
+/*
+ * Additional options, not kept in so_options.
+ */
+#define SO_SNDBUF    0x1001    /* Unimplemented: send buffer size */
+#define SO_RCVBUF    0x1002    /* receive buffer size */
+#define SO_SNDLOWAT  0x1003    /* Unimplemented: send low-water mark */
+#define SO_RCVLOWAT  0x1004    /* Unimplemented: receive low-water mark */
+#define SO_SNDTIMEO  0x1005    /* Unimplemented: send timeout */
+#define SO_RCVTIMEO  0x1006    /* receive timeout */
+#define SO_ERROR     0x1007    /* get error status and clear */
+#define SO_TYPE      0x1008    /* get socket type */
+#define SO_CONTIMEO  0x1009    /* Unimplemented: connect timeout */
+#define SO_NO_CHECK  0x100a    /* don't create UDP checksum */
+
+
+/*
+ * Structure used for manipulating linger option.
+ */
+struct linger {
+       int l_onoff;                /* option on/off */
+       int l_linger;               /* linger time */
+};
+
+/*
+ * Level number for (get/set)sockopt() to apply to socket itself.
+ */
+#define  SOL_SOCKET  0xfff    /* options for socket level */
+
+
+#define AF_UNSPEC       0
+#define AF_INET         2
+#define PF_INET         AF_INET
+#define PF_UNSPEC       AF_UNSPEC
+
+#define IPPROTO_IP      0
+#define IPPROTO_TCP     6
+#define IPPROTO_UDP     17
+#define IPPROTO_UDPLITE 136
+
+/* Flags we can use with send and recv. */
+#define MSG_PEEK       0x01    /* Peeks at an incoming message */
+#define MSG_WAITALL    0x02    /* Unimplemented: Requests that the function block until the full amount of data requested can be returned */
+#define MSG_OOB        0x04    /* Unimplemented: Requests out-of-band data. The significance and semantics of out-of-band data are protocol-specific */
+#define MSG_DONTWAIT   0x08    /* Nonblocking i/o for this operation only */
+#define MSG_MORE       0x10    /* Sender will send more */
+
+
+/*
+ * Options for level IPPROTO_IP
+ */
+#define IP_TOS             1
+#define IP_TTL             2
+
+#if LWIP_TCP
+/*
+ * Options for level IPPROTO_TCP
+ */
+#define TCP_NODELAY    0x01    /* don't delay send to coalesce packets */
+#define TCP_KEEPALIVE  0x02    /* send KEEPALIVE probes when idle for pcb->keep_idle milliseconds */
+#define TCP_KEEPIDLE   0x03    /* set pcb->keep_idle  - Same as TCP_KEEPALIVE, but use seconds for get/setsockopt */
+#define TCP_KEEPINTVL  0x04    /* set pcb->keep_intvl - Use seconds for get/setsockopt */
+#define TCP_KEEPCNT    0x05    /* set pcb->keep_cnt   - Use number of probes sent for get/setsockopt */
+#endif /* LWIP_TCP */
+
+#if LWIP_UDP && LWIP_UDPLITE
+/*
+ * Options for level IPPROTO_UDPLITE
+ */
+#define UDPLITE_SEND_CSCOV 0x01 /* sender checksum coverage */
+#define UDPLITE_RECV_CSCOV 0x02 /* minimal receiver checksum coverage */
+#endif /* LWIP_UDP && LWIP_UDPLITE*/
+
+
+#if LWIP_IGMP
+/*
+ * Options and types for UDP multicast traffic handling
+ */
+#define IP_ADD_MEMBERSHIP  3
+#define IP_DROP_MEMBERSHIP 4
+#define IP_MULTICAST_TTL   5
+#define IP_MULTICAST_IF    6
+#define IP_MULTICAST_LOOP  7
+
+typedef struct ip_mreq {
+    struct in_addr imr_multiaddr; /* IP multicast address of group */
+    struct in_addr imr_interface; /* local IP address of interface */
+} ip_mreq;
+#endif /* LWIP_IGMP */
+
+/*
+ * The Type of Service provides an indication of the abstract
+ * parameters of the quality of service desired.  These parameters are
+ * to be used to guide the selection of the actual service parameters
+ * when transmitting a datagram through a particular network.  Several
+ * networks offer service precedence, which somehow treats high
+ * precedence traffic as more important than other traffic (generally
+ * by accepting only traffic above a certain precedence at time of high
+ * load).  The major choice is a three way tradeoff between low-delay,
+ * high-reliability, and high-throughput.
+ * The use of the Delay, Throughput, and Reliability indications may
+ * increase the cost (in some sense) of the service.  In many networks
+ * better performance for one of these parameters is coupled with worse
+ * performance on another.  Except for very unusual cases at most two
+ * of these three indications should be set.
+ */
+#define IPTOS_TOS_MASK          0x1E
+#define IPTOS_TOS(tos)          ((tos) & IPTOS_TOS_MASK)
+#define IPTOS_LOWDELAY          0x10
+#define IPTOS_THROUGHPUT        0x08
+#define IPTOS_RELIABILITY       0x04
+#define IPTOS_LOWCOST           0x02
+#define IPTOS_MINCOST           IPTOS_LOWCOST
+
+/*
+ * The Network Control precedence designation is intended to be used
+ * within a network only.  The actual use and control of that
+ * designation is up to each network. The Internetwork Control
+ * designation is intended for use by gateway control originators only.
+ * If the actual use of these precedence designations is of concern to
+ * a particular network, it is the responsibility of that network to
+ * control the access to, and use of, those precedence designations.
+ */
+#define IPTOS_PREC_MASK                 0xe0
+#define IPTOS_PREC(tos)                ((tos) & IPTOS_PREC_MASK)
+#define IPTOS_PREC_NETCONTROL           0xe0
+#define IPTOS_PREC_INTERNETCONTROL      0xc0
+#define IPTOS_PREC_CRITIC_ECP           0xa0
+#define IPTOS_PREC_FLASHOVERRIDE        0x80
+#define IPTOS_PREC_FLASH                0x60
+#define IPTOS_PREC_IMMEDIATE            0x40
+#define IPTOS_PREC_PRIORITY             0x20
+#define IPTOS_PREC_ROUTINE              0x00
+
+
+/*
+ * Commands for ioctlsocket(),  taken from the BSD file fcntl.h.
+ * lwip_ioctl only supports FIONREAD and FIONBIO, for now
+ *
+ * Ioctl's have the command encoded in the lower word,
+ * and the size of any in or out parameters in the upper
+ * word.  The high 2 bits of the upper word are used
+ * to encode the in/out status of the parameter; for now
+ * we restrict parameters to at most 128 bytes.
+ */
+#if !defined(FIONREAD) || !defined(FIONBIO)
+#define IOCPARM_MASK    0x7fU           /* parameters must be < 128 bytes */
+#define IOC_VOID        0x20000000UL    /* no parameters */
+#define IOC_OUT         0x40000000UL    /* copy out parameters */
+#define IOC_IN          0x80000000UL    /* copy in parameters */
+#define IOC_INOUT       (IOC_IN|IOC_OUT)
+                                        /* 0x20000000 distinguishes new &
+                                           old ioctl's */
+#define _IO(x,y)        (IOC_VOID|((x)<<8)|(y))
+
+#define _IOR(x,y,t)     (IOC_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
+
+#define _IOW(x,y,t)     (IOC_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
+#endif /* !defined(FIONREAD) || !defined(FIONBIO) */
+
+#ifndef FIONREAD
+#define FIONREAD    _IOR('f', 127, unsigned long) /* get # bytes to read */
+#endif
+#ifndef FIONBIO
+#define FIONBIO     _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */
+#endif
+
+/* Socket I/O Controls: unimplemented */
+#ifndef SIOCSHIWAT
+#define SIOCSHIWAT  _IOW('s',  0, unsigned long)  /* set high watermark */
+#define SIOCGHIWAT  _IOR('s',  1, unsigned long)  /* get high watermark */
+#define SIOCSLOWAT  _IOW('s',  2, unsigned long)  /* set low watermark */
+#define SIOCGLOWAT  _IOR('s',  3, unsigned long)  /* get low watermark */
+#define SIOCATMARK  _IOR('s',  7, unsigned long)  /* at oob mark? */
+#endif
+
+/* Socket flags: */
+#ifndef O_NONBLOCK
+#define O_NONBLOCK    04000U
+#endif
+
+/* FD_SET used for lwip_select */
+#ifndef FD_SET
+  #undef  FD_SETSIZE
+  /* Make FD_SETSIZE match NUM_SOCKETS in socket.c */
+  #define FD_SETSIZE    MEMP_NUM_NETCONN
+  #define FD_SET(n, p)  ((p)->fd_bits[(n)/8] |=  (1 << ((n) & 7)))
+  #define FD_CLR(n, p)  ((p)->fd_bits[(n)/8] &= ~(1 << ((n) & 7)))
+  #define FD_ISSET(n,p) ((p)->fd_bits[(n)/8] &   (1 << ((n) & 7)))
+  #define FD_ZERO(p)    memset((void*)(p),0,sizeof(*(p)))
+
+  typedef struct fd_set {
+          unsigned char fd_bits [(FD_SETSIZE+7)/8];
+        } fd_set;
+
+#endif /* FD_SET */
+
+/** LWIP_TIMEVAL_PRIVATE: if you want to use the struct timeval provided
+ * by your system, set this to 0 and include  in cc.h */ 
+#ifndef LWIP_TIMEVAL_PRIVATE
+#define LWIP_TIMEVAL_PRIVATE 1
+#endif
+
+#if LWIP_TIMEVAL_PRIVATE
+struct timeval {
+  long    tv_sec;         /* seconds */
+  long    tv_usec;        /* and microseconds */
+};
+#endif /* LWIP_TIMEVAL_PRIVATE */
+
+void lwip_socket_init(void);
+
+int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen);
+int lwip_bind(int s, const struct sockaddr *name, socklen_t namelen);
+int lwip_shutdown(int s, int how);
+int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen);
+int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen);
+int lwip_close(int s);
+int lwip_connect(int s, const struct sockaddr *name, socklen_t namelen);
+int lwip_listen(int s, int backlog);
+int lwip_recv(int s, void *mem, size_t len, int flags);
+int lwip_read(int s, void *mem, size_t len);
+int lwip_recvfrom(int s, void *mem, size_t len, int flags,
+      struct sockaddr *from, socklen_t *fromlen);
+int lwip_send(int s, const void *dataptr, size_t size, int flags);
+int lwip_sendto(int s, const void *dataptr, size_t size, int flags,
+    const struct sockaddr *to, socklen_t tolen);
+int lwip_socket(int domain, int type, int protocol);
+int lwip_write(int s, const void *dataptr, size_t size);
+int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
+                struct timeval *timeout);
+int lwip_ioctl(int s, long cmd, void *argp);
+
+#if LWIP_COMPAT_SOCKETS
+#define accept(a,b,c)         lwip_accept(a,b,c)
+#define bind(a,b,c)           lwip_bind(a,b,c)
+#define shutdown(a,b)         lwip_shutdown(a,b)
+#define closesocket(s)        lwip_close(s)
+#define connect(a,b,c)        lwip_connect(a,b,c)
+#define getsockname(a,b,c)    lwip_getsockname(a,b,c)
+#define getpeername(a,b,c)    lwip_getpeername(a,b,c)
+#define setsockopt(a,b,c,d,e) lwip_setsockopt(a,b,c,d,e)
+#define getsockopt(a,b,c,d,e) lwip_getsockopt(a,b,c,d,e)
+#define listen(a,b)           lwip_listen(a,b)
+#define recv(a,b,c,d)         lwip_recv(a,b,c,d)
+#define recvfrom(a,b,c,d,e,f) lwip_recvfrom(a,b,c,d,e,f)
+#define send(a,b,c,d)         lwip_send(a,b,c,d)
+#define sendto(a,b,c,d,e,f)   lwip_sendto(a,b,c,d,e,f)
+#define socket(a,b,c)         lwip_socket(a,b,c)
+#define select(a,b,c,d,e)     lwip_select(a,b,c,d,e)
+#define ioctlsocket(a,b,c)    lwip_ioctl(a,b,c)
+
+#if LWIP_POSIX_SOCKETS_IO_NAMES
+#define read(a,b,c)           lwip_read(a,b,c)
+#define write(a,b,c)          lwip_write(a,b,c)
+#define close(s)              lwip_close(s)
+#endif /* LWIP_POSIX_SOCKETS_IO_NAMES */
+
+#endif /* LWIP_COMPAT_SOCKETS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_SOCKET */
+
+#endif /* __LWIP_SOCKETS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/stats.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/stats.h
new file mode 100644
index 0000000..aa179f5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/stats.h
@@ -0,0 +1,283 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_STATS_H__
+#define __LWIP_STATS_H__
+
+#include "lwip/opt.h"
+
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_STATS
+
+#ifndef LWIP_STATS_LARGE
+#define LWIP_STATS_LARGE 0
+#endif
+
+#if LWIP_STATS_LARGE
+#define STAT_COUNTER     u32_t
+#define STAT_COUNTER_F   U32_F
+#else
+#define STAT_COUNTER     u16_t
+#define STAT_COUNTER_F   U16_F
+#endif 
+
+struct stats_proto {
+  STAT_COUNTER xmit;             /* Transmitted packets. */
+  STAT_COUNTER recv;             /* Received packets. */
+  STAT_COUNTER fw;               /* Forwarded packets. */
+  STAT_COUNTER drop;             /* Dropped packets. */
+  STAT_COUNTER chkerr;           /* Checksum error. */
+  STAT_COUNTER lenerr;           /* Invalid length error. */
+  STAT_COUNTER memerr;           /* Out of memory error. */
+  STAT_COUNTER rterr;            /* Routing error. */
+  STAT_COUNTER proterr;          /* Protocol error. */
+  STAT_COUNTER opterr;           /* Error in options. */
+  STAT_COUNTER err;              /* Misc error. */
+  STAT_COUNTER cachehit;
+};
+
+struct stats_igmp {
+  STAT_COUNTER lenerr;           /* Invalid length error. */
+  STAT_COUNTER chkerr;           /* Checksum error. */
+  STAT_COUNTER v1_rxed;          /* */
+  STAT_COUNTER join_sent;        /* */
+  STAT_COUNTER leave_sent;       /* */
+  STAT_COUNTER unicast_query;    /* */
+  STAT_COUNTER report_sent;      /* */
+  STAT_COUNTER report_rxed;      /* */
+  STAT_COUNTER group_query_rxed; /* */
+};
+
+struct stats_mem {
+  mem_size_t avail;
+  mem_size_t used;
+  mem_size_t max;
+  STAT_COUNTER err;
+  STAT_COUNTER illegal;
+};
+
+struct stats_syselem {
+  STAT_COUNTER used;
+  STAT_COUNTER max;
+  STAT_COUNTER err;
+};
+
+struct stats_sys {
+  struct stats_syselem sem;
+  struct stats_syselem mbox;
+};
+
+struct stats_ {
+#if LINK_STATS
+  struct stats_proto link;
+#endif
+#if ETHARP_STATS
+  struct stats_proto etharp;
+#endif
+#if IPFRAG_STATS
+  struct stats_proto ip_frag;
+#endif
+#if IP_STATS
+  struct stats_proto ip;
+#endif
+#if ICMP_STATS
+  struct stats_proto icmp;
+#endif
+#if IGMP_STATS
+  struct stats_igmp igmp;
+#endif
+#if UDP_STATS
+  struct stats_proto udp;
+#endif
+#if TCP_STATS
+  struct stats_proto tcp;
+#endif
+#if MEM_STATS
+  struct stats_mem mem;
+#endif
+#if MEMP_STATS
+  struct stats_mem memp[MEMP_MAX];
+#endif
+#if SYS_STATS
+  struct stats_sys sys;
+#endif
+};
+
+extern struct stats_ lwip_stats;
+
+#define stats_init() /* Compatibility define, not init needed. */
+
+#define STATS_INC(x) ++lwip_stats.x
+#define STATS_DEC(x) --lwip_stats.x
+#else
+#define stats_init()
+#define STATS_INC(x)
+#define STATS_DEC(x)
+#endif /* LWIP_STATS */
+
+#if TCP_STATS
+#define TCP_STATS_INC(x) STATS_INC(x)
+#define TCP_STATS_DISPLAY() stats_display_proto(&lwip_stats.tcp, "TCP")
+#else
+#define TCP_STATS_INC(x)
+#define TCP_STATS_DISPLAY()
+#endif
+
+#if UDP_STATS
+#define UDP_STATS_INC(x) STATS_INC(x)
+#define UDP_STATS_DISPLAY() stats_display_proto(&lwip_stats.udp, "UDP")
+#else
+#define UDP_STATS_INC(x)
+#define UDP_STATS_DISPLAY()
+#endif
+
+#if ICMP_STATS
+#define ICMP_STATS_INC(x) STATS_INC(x)
+#define ICMP_STATS_DISPLAY() stats_display_proto(&lwip_stats.icmp, "ICMP")
+#else
+#define ICMP_STATS_INC(x)
+#define ICMP_STATS_DISPLAY()
+#endif
+
+#if IGMP_STATS
+#define IGMP_STATS_INC(x) STATS_INC(x)
+#define IGMP_STATS_DISPLAY() stats_display_igmp(&lwip_stats.igmp)
+#else
+#define IGMP_STATS_INC(x)
+#define IGMP_STATS_DISPLAY()
+#endif
+
+#if IP_STATS
+#define IP_STATS_INC(x) STATS_INC(x)
+#define IP_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip, "IP")
+#else
+#define IP_STATS_INC(x)
+#define IP_STATS_DISPLAY()
+#endif
+
+#if IPFRAG_STATS
+#define IPFRAG_STATS_INC(x) STATS_INC(x)
+#define IPFRAG_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG")
+#else
+#define IPFRAG_STATS_INC(x)
+#define IPFRAG_STATS_DISPLAY()
+#endif
+
+#if ETHARP_STATS
+#define ETHARP_STATS_INC(x) STATS_INC(x)
+#define ETHARP_STATS_DISPLAY() stats_display_proto(&lwip_stats.etharp, "ETHARP")
+#else
+#define ETHARP_STATS_INC(x)
+#define ETHARP_STATS_DISPLAY()
+#endif
+
+#if LINK_STATS
+#define LINK_STATS_INC(x) STATS_INC(x)
+#define LINK_STATS_DISPLAY() stats_display_proto(&lwip_stats.link, "LINK")
+#else
+#define LINK_STATS_INC(x)
+#define LINK_STATS_DISPLAY()
+#endif
+
+#if MEM_STATS
+#define MEM_STATS_AVAIL(x, y) lwip_stats.mem.x = y
+#define MEM_STATS_INC(x) STATS_INC(mem.x)
+#define MEM_STATS_INC_USED(x, y) do { lwip_stats.mem.used += y; \
+                                    if (lwip_stats.mem.max < lwip_stats.mem.used) { \
+                                        lwip_stats.mem.max = lwip_stats.mem.used; \
+                                    } \
+                                 } while(0)
+#define MEM_STATS_DEC_USED(x, y) lwip_stats.mem.x -= y
+#define MEM_STATS_DISPLAY() stats_display_mem(&lwip_stats.mem, "HEAP")
+#else
+#define MEM_STATS_AVAIL(x, y)
+#define MEM_STATS_INC(x)
+#define MEM_STATS_INC_USED(x, y)
+#define MEM_STATS_DEC_USED(x, y)
+#define MEM_STATS_DISPLAY()
+#endif
+
+#if MEMP_STATS
+#define MEMP_STATS_AVAIL(x, i, y) lwip_stats.memp[i].x = y
+#define MEMP_STATS_INC(x, i) STATS_INC(memp[i].x)
+#define MEMP_STATS_DEC(x, i) STATS_DEC(memp[i].x)
+#define MEMP_STATS_INC_USED(x, i) do { ++lwip_stats.memp[i].used; \
+                                    if (lwip_stats.memp[i].max < lwip_stats.memp[i].used) { \
+                                        lwip_stats.memp[i].max = lwip_stats.memp[i].used; \
+                                    } \
+                                 } while(0)
+#define MEMP_STATS_DISPLAY(i) stats_display_memp(&lwip_stats.memp[i], i)
+#else
+#define MEMP_STATS_AVAIL(x, i, y)
+#define MEMP_STATS_INC(x, i)
+#define MEMP_STATS_DEC(x, i)
+#define MEMP_STATS_INC_USED(x, i)
+#define MEMP_STATS_DISPLAY(i)
+#endif
+
+#if SYS_STATS
+#define SYS_STATS_INC(x) STATS_INC(sys.x)
+#define SYS_STATS_DEC(x) STATS_DEC(sys.x)
+#define SYS_STATS_DISPLAY() stats_display_sys(&lwip_stats.sys)
+#else
+#define SYS_STATS_INC(x)
+#define SYS_STATS_DEC(x)
+#define SYS_STATS_DISPLAY()
+#endif
+
+/* Display of statistics */
+#if LWIP_STATS_DISPLAY
+void stats_display(void);
+void stats_display_proto(struct stats_proto *proto, char *name);
+void stats_display_igmp(struct stats_igmp *igmp);
+void stats_display_mem(struct stats_mem *mem, char *name);
+void stats_display_memp(struct stats_mem *mem, int index);
+void stats_display_sys(struct stats_sys *sys);
+#else
+#define stats_display()
+#define stats_display_proto(proto, name)
+#define stats_display_igmp(igmp)
+#define stats_display_mem(mem, name)
+#define stats_display_memp(mem, index)
+#define stats_display_sys(sys)
+#endif /* LWIP_STATS_DISPLAY */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_STATS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/sys.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/sys.h
new file mode 100644
index 0000000..0cc84dd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/sys.h
@@ -0,0 +1,243 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_SYS_H__
+#define __LWIP_SYS_H__
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if NO_SYS
+
+/* For a totally minimal and standalone system, we provide null
+   definitions of the sys_ functions. */
+typedef u8_t sys_sem_t;
+typedef u8_t sys_mbox_t;
+struct sys_timeo {u8_t dummy;};
+
+#define sys_init()
+#define sys_timeout(m,h,a)
+#define sys_untimeout(m,a)
+#define sys_sem_new(c) c
+#define sys_sem_signal(s)
+#define sys_sem_wait(s)
+#define sys_sem_wait_timeout(s,t)
+#define sys_arch_sem_wait(s,t)
+#define sys_sem_free(s)
+#define sys_mbox_new(s) 0
+#define sys_mbox_fetch(m,d)
+#define sys_mbox_tryfetch(m,d)
+#define sys_mbox_post(m,d)
+#define sys_mbox_trypost(m,d)
+#define sys_mbox_free(m)
+
+#define sys_thread_new(n,t,a,s,p)
+
+#else /* NO_SYS */
+
+/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */
+#define SYS_ARCH_TIMEOUT 0xffffffffUL
+
+/* sys_mbox_tryfetch returns SYS_MBOX_EMPTY if appropriate.
+ * For now we use the same magic value, but we allow this to change in future.
+ */
+#define SYS_MBOX_EMPTY SYS_ARCH_TIMEOUT 
+
+#include "lwip/err.h"
+#include "arch/sys_arch.h"
+
+typedef void (* sys_timeout_handler)(void *arg);
+
+struct sys_timeo {
+  struct sys_timeo *next;
+  u32_t time;
+  sys_timeout_handler h;
+  void *arg;
+};
+
+struct sys_timeouts {
+  struct sys_timeo *next;
+};
+
+/* sys_init() must be called before anthing else. */
+void sys_init(void);
+
+/*
+ * sys_timeout():
+ *
+ * Schedule a timeout a specified amount of milliseconds in the
+ * future. When the timeout occurs, the specified timeout handler will
+ * be called. The handler will be passed the "arg" argument when
+ * called.
+ *
+ */
+void sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg);
+void sys_untimeout(sys_timeout_handler h, void *arg);
+struct sys_timeouts *sys_arch_timeouts(void);
+
+/* Semaphore functions. */
+sys_sem_t sys_sem_new(u8_t count);
+void sys_sem_signal(sys_sem_t sem);
+u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout);
+void sys_sem_free(sys_sem_t sem);
+void sys_sem_wait(sys_sem_t sem);
+int sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout);
+
+/* Time functions. */
+#ifndef sys_msleep
+void sys_msleep(u32_t ms); /* only has a (close to) 1 jiffy resolution. */
+#endif
+#ifndef sys_jiffies
+u32_t sys_jiffies(void); /* since power up. */
+#endif
+
+/* Mailbox functions. */
+sys_mbox_t sys_mbox_new(int size);
+void sys_mbox_post(sys_mbox_t mbox, void *msg);
+err_t sys_mbox_trypost(sys_mbox_t mbox, void *msg);
+u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout);
+#ifndef sys_arch_mbox_tryfetch /* Allow port to override with a macro */
+u32_t sys_arch_mbox_tryfetch(sys_mbox_t mbox, void **msg);
+#endif
+/* For now, we map straight to sys_arch implementation. */
+#define sys_mbox_tryfetch(mbox, msg) sys_arch_mbox_tryfetch(mbox, msg)
+void sys_mbox_free(sys_mbox_t mbox);
+void sys_mbox_fetch(sys_mbox_t mbox, void **msg);
+
+/* Thread functions. */
+sys_thread_t sys_thread_new(char *name, void (* thread)(void *arg), void *arg, int stacksize, int prio);
+
+#endif /* NO_SYS */
+
+/** Returns the current time in milliseconds. */
+u32_t sys_now(void);
+
+/* Critical Region Protection */
+/* These functions must be implemented in the sys_arch.c file.
+   In some implementations they can provide a more light-weight protection
+   mechanism than using semaphores. Otherwise semaphores can be used for
+   implementation */
+#ifndef SYS_ARCH_PROTECT
+/** SYS_LIGHTWEIGHT_PROT
+ * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
+ * for certain critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#if SYS_LIGHTWEIGHT_PROT
+
+/** SYS_ARCH_DECL_PROTECT
+ * declare a protection variable. This macro will default to defining a variable of
+ * type sys_prot_t. If a particular port needs a different implementation, then
+ * this macro may be defined in sys_arch.h.
+ */
+#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev
+/** SYS_ARCH_PROTECT
+ * Perform a "fast" protect. This could be implemented by
+ * disabling interrupts for an embedded system or by using a semaphore or
+ * mutex. The implementation should allow calling SYS_ARCH_PROTECT when
+ * already protected. The old protection level is returned in the variable
+ * "lev". This macro will default to calling the sys_arch_protect() function
+ * which should be implemented in sys_arch.c. If a particular port needs a
+ * different implementation, then this macro may be defined in sys_arch.h
+ */
+#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect()
+/** SYS_ARCH_UNPROTECT
+ * Perform a "fast" set of the protection level to "lev". This could be
+ * implemented by setting the interrupt level to "lev" within the MACRO or by
+ * using a semaphore or mutex.  This macro will default to calling the
+ * sys_arch_unprotect() function which should be implemented in
+ * sys_arch.c. If a particular port needs a different implementation, then
+ * this macro may be defined in sys_arch.h
+ */
+#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev)
+sys_prot_t sys_arch_protect(void);
+void sys_arch_unprotect(sys_prot_t pval);
+
+#else
+
+#define SYS_ARCH_DECL_PROTECT(lev)
+#define SYS_ARCH_PROTECT(lev)
+#define SYS_ARCH_UNPROTECT(lev)
+
+#endif /* SYS_LIGHTWEIGHT_PROT */
+
+#endif /* SYS_ARCH_PROTECT */
+
+/*
+ * Macros to set/get and increase/decrease variables in a thread-safe way.
+ * Use these for accessing variable that are used from more than one thread.
+ */
+
+#ifndef SYS_ARCH_INC
+#define SYS_ARCH_INC(var, val) do { \
+                                SYS_ARCH_DECL_PROTECT(old_level); \
+                                SYS_ARCH_PROTECT(old_level); \
+                                var += val; \
+                                SYS_ARCH_UNPROTECT(old_level); \
+                              } while(0)
+#endif /* SYS_ARCH_INC */
+
+#ifndef SYS_ARCH_DEC
+#define SYS_ARCH_DEC(var, val) do { \
+                                SYS_ARCH_DECL_PROTECT(old_level); \
+                                SYS_ARCH_PROTECT(old_level); \
+                                var -= val; \
+                                SYS_ARCH_UNPROTECT(old_level); \
+                              } while(0)
+#endif /* SYS_ARCH_DEC */
+
+#ifndef SYS_ARCH_GET
+#define SYS_ARCH_GET(var, ret) do { \
+                                SYS_ARCH_DECL_PROTECT(old_level); \
+                                SYS_ARCH_PROTECT(old_level); \
+                                ret = var; \
+                                SYS_ARCH_UNPROTECT(old_level); \
+                              } while(0)
+#endif /* SYS_ARCH_GET */
+
+#ifndef SYS_ARCH_SET
+#define SYS_ARCH_SET(var, val) do { \
+                                SYS_ARCH_DECL_PROTECT(old_level); \
+                                SYS_ARCH_PROTECT(old_level); \
+                                var = val; \
+                                SYS_ARCH_UNPROTECT(old_level); \
+                              } while(0)
+#endif /* SYS_ARCH_SET */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_SYS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/tcp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/tcp.h
new file mode 100644
index 0000000..c88d25d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/tcp.h
@@ -0,0 +1,707 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_TCP_H__
+#define __LWIP_TCP_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip.h"
+#include "lwip/icmp.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct tcp_pcb;
+
+/* Functions for interfacing with TCP: */
+
+/* Lower layer interface to TCP: */
+#define tcp_init() /* Compatibility define, not init needed. */
+void             tcp_tmr     (void);  /* Must be called every
+                                         TCP_TMR_INTERVAL
+                                         ms. (Typically 250 ms). */
+/* Application program's interface: */
+struct tcp_pcb * tcp_new     (void);
+struct tcp_pcb * tcp_alloc   (u8_t prio);
+
+void             tcp_arg     (struct tcp_pcb *pcb, void *arg);
+void             tcp_accept  (struct tcp_pcb *pcb,
+                              err_t (* accept)(void *arg, struct tcp_pcb *newpcb,
+                 err_t err));
+void             tcp_recv    (struct tcp_pcb *pcb,
+                              err_t (* recv)(void *arg, struct tcp_pcb *tpcb,
+                              struct pbuf *p, err_t err));
+void             tcp_sent    (struct tcp_pcb *pcb,
+                              err_t (* sent)(void *arg, struct tcp_pcb *tpcb,
+                              u16_t len));
+void             tcp_poll    (struct tcp_pcb *pcb,
+                              err_t (* poll)(void *arg, struct tcp_pcb *tpcb),
+                              u8_t interval);
+void             tcp_err     (struct tcp_pcb *pcb,
+                              void (* err)(void *arg, err_t err));
+
+#define          tcp_mss(pcb)      ((pcb)->mss)
+#define          tcp_sndbuf(pcb)   ((pcb)->snd_buf)
+#define          tcp_nagle_disable(pcb)  ((pcb)->flags |= TF_NODELAY)
+#define          tcp_nagle_enable(pcb) ((pcb)->flags &= ~TF_NODELAY)
+#define          tcp_nagle_disabled(pcb) (((pcb)->flags & TF_NODELAY) != 0)
+
+#if TCP_LISTEN_BACKLOG
+#define          tcp_accepted(pcb) (((struct tcp_pcb_listen *)(pcb))->accepts_pending--)
+#else  /* TCP_LISTEN_BACKLOG */
+#define          tcp_accepted(pcb)
+#endif /* TCP_LISTEN_BACKLOG */
+
+void             tcp_recved  (struct tcp_pcb *pcb, u16_t len);
+err_t            tcp_bind    (struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+                              u16_t port);
+err_t            tcp_connect (struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+                              u16_t port, err_t (* connected)(void *arg,
+                              struct tcp_pcb *tpcb,
+                              err_t err));
+
+struct tcp_pcb * tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog);
+#define          tcp_listen(pcb) tcp_listen_with_backlog(pcb, TCP_DEFAULT_LISTEN_BACKLOG)
+
+void             tcp_abandon (struct tcp_pcb *pcb, int reset);
+#define          tcp_abort(pcb) tcp_abandon((pcb), 1)
+err_t            tcp_close   (struct tcp_pcb *pcb);
+
+/* Flags for "apiflags" parameter in tcp_write and tcp_enqueue */
+#define TCP_WRITE_FLAG_COPY 0x01
+#define TCP_WRITE_FLAG_MORE 0x02
+
+err_t            tcp_write   (struct tcp_pcb *pcb, const void *dataptr, u16_t len,
+                              u8_t apiflags);
+
+void             tcp_setprio (struct tcp_pcb *pcb, u8_t prio);
+
+#define TCP_PRIO_MIN    1
+#define TCP_PRIO_NORMAL 64
+#define TCP_PRIO_MAX    127
+
+/* It is also possible to call these two functions at the right
+   intervals (instead of calling tcp_tmr()). */
+void             tcp_slowtmr (void);
+void             tcp_fasttmr (void);
+
+
+/* Only used by IP to pass a TCP segment to TCP: */
+void             tcp_input   (struct pbuf *p, struct netif *inp);
+/* Used within the TCP code only: */
+err_t            tcp_send_empty_ack(struct tcp_pcb *pcb);
+err_t            tcp_output  (struct tcp_pcb *pcb);
+void             tcp_rexmit  (struct tcp_pcb *pcb);
+void             tcp_rexmit_rto  (struct tcp_pcb *pcb);
+void             tcp_rexmit_fast (struct tcp_pcb *pcb);
+u32_t            tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb);
+
+/**
+ * This is the Nagle algorithm: try to combine user data to send as few TCP
+ * segments as possible. Only send if
+ * - no previously transmitted data on the connection remains unacknowledged or
+ * - the TF_NODELAY flag is set (nagle algorithm turned off for this pcb) or
+ * - the only unsent segment is at least pcb->mss bytes long (or there is more
+ *   than one unsent segment - with lwIP, this can happen although unsent->len < mss)
+ * - or if we are in fast-retransmit (TF_INFR)
+ */
+#define tcp_do_output_nagle(tpcb) ((((tpcb)->unacked == NULL) || \
+                            ((tpcb)->flags & (TF_NODELAY | TF_INFR)) || \
+                            (((tpcb)->unsent != NULL) && (((tpcb)->unsent->next != NULL) || \
+                              ((tpcb)->unsent->len >= (tpcb)->mss))) \
+                            ) ? 1 : 0)
+#define tcp_output_nagle(tpcb) (tcp_do_output_nagle(tpcb) ? tcp_output(tpcb) : ERR_OK)
+
+
+#define TCP_SEQ_LT(a,b)     ((s32_t)((a)-(b)) < 0)
+#define TCP_SEQ_LEQ(a,b)    ((s32_t)((a)-(b)) <= 0)
+#define TCP_SEQ_GT(a,b)     ((s32_t)((a)-(b)) > 0)
+#define TCP_SEQ_GEQ(a,b)    ((s32_t)((a)-(b)) >= 0)
+/* is b<=a<=c? */
+#if 0 /* see bug #10548 */
+#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b))
+#endif
+#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c))
+#define TCP_FIN 0x01U
+#define TCP_SYN 0x02U
+#define TCP_RST 0x04U
+#define TCP_PSH 0x08U
+#define TCP_ACK 0x10U
+#define TCP_URG 0x20U
+#define TCP_ECE 0x40U
+#define TCP_CWR 0x80U
+
+#define TCP_FLAGS 0x3fU
+
+/* Length of the TCP header, excluding options. */
+#define TCP_HLEN 20
+
+#ifndef TCP_TMR_INTERVAL
+#define TCP_TMR_INTERVAL       250  /* The TCP timer interval in milliseconds. */
+#endif /* TCP_TMR_INTERVAL */
+
+#ifndef TCP_FAST_INTERVAL
+#define TCP_FAST_INTERVAL      TCP_TMR_INTERVAL /* the fine grained timeout in milliseconds */
+#endif /* TCP_FAST_INTERVAL */
+
+#ifndef TCP_SLOW_INTERVAL
+#define TCP_SLOW_INTERVAL      (2*TCP_TMR_INTERVAL)  /* the coarse grained timeout in milliseconds */
+#endif /* TCP_SLOW_INTERVAL */
+
+#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */
+#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */
+
+#define TCP_OOSEQ_TIMEOUT        6U /* x RTO */
+
+#ifndef TCP_MSL
+#define TCP_MSL 60000UL /* The maximum segment lifetime in milliseconds */
+#endif
+
+/* Keepalive values, compliant with RFC 1122. Don't change this unless you know what you're doing */
+#ifndef  TCP_KEEPIDLE_DEFAULT
+#define  TCP_KEEPIDLE_DEFAULT     7200000UL /* Default KEEPALIVE timer in milliseconds */
+#endif
+
+#ifndef  TCP_KEEPINTVL_DEFAULT
+#define  TCP_KEEPINTVL_DEFAULT    75000UL   /* Default Time between KEEPALIVE probes in milliseconds */
+#endif
+
+#ifndef  TCP_KEEPCNT_DEFAULT
+#define  TCP_KEEPCNT_DEFAULT      9U        /* Default Counter for KEEPALIVE probes */
+#endif
+
+#define  TCP_MAXIDLE              TCP_KEEPCNT_DEFAULT * TCP_KEEPINTVL_DEFAULT  /* Maximum KEEPALIVE probe time */
+
+/* Fields are (of course) in network byte order.
+ * Some fields are converted to host byte order in tcp_input().
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct tcp_hdr {
+  PACK_STRUCT_FIELD(u16_t src);
+  PACK_STRUCT_FIELD(u16_t dest);
+  PACK_STRUCT_FIELD(u32_t seqno);
+  PACK_STRUCT_FIELD(u32_t ackno);
+  PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags);
+  PACK_STRUCT_FIELD(u16_t wnd);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u16_t urgp);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define TCPH_OFFSET(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 8)
+#define TCPH_HDRLEN(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 12)
+#define TCPH_FLAGS(phdr)  (ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS)
+
+#define TCPH_OFFSET_SET(phdr, offset) (phdr)->_hdrlen_rsvd_flags = htons(((offset) << 8) | TCPH_FLAGS(phdr))
+#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | TCPH_FLAGS(phdr))
+#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = (((phdr)->_hdrlen_rsvd_flags & htons((u16_t)(~(u16_t)(TCP_FLAGS)))) | htons(flags))
+#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = ((phdr)->_hdrlen_rsvd_flags | htons(flags))
+#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (TCPH_FLAGS(phdr) & ~(flags)) )
+
+#define TCP_TCPLEN(seg) ((seg)->len + ((TCPH_FLAGS((seg)->tcphdr) & (TCP_FIN | TCP_SYN)) != 0))
+
+enum tcp_state {
+  CLOSED      = 0,
+  LISTEN      = 1,
+  SYN_SENT    = 2,
+  SYN_RCVD    = 3,
+  ESTABLISHED = 4,
+  FIN_WAIT_1  = 5,
+  FIN_WAIT_2  = 6,
+  CLOSE_WAIT  = 7,
+  CLOSING     = 8,
+  LAST_ACK    = 9,
+  TIME_WAIT   = 10
+};
+
+/** Flags used on input processing, not on pcb->flags
+*/
+#define TF_RESET     (u8_t)0x08U   /* Connection was reset. */
+#define TF_CLOSED    (u8_t)0x10U   /* Connection was sucessfully closed. */
+#define TF_GOT_FIN   (u8_t)0x20U   /* Connection was closed by the remote end. */
+
+
+#if LWIP_CALLBACK_API
+  /* Function to call when a listener has been connected.
+   * @param arg user-supplied argument (tcp_pcb.callback_arg)
+   * @param pcb a new tcp_pcb that now is connected
+   * @param err an error argument (TODO: that is current always ERR_OK?)
+   * @return ERR_OK: accept the new connection,
+   *                 any other err_t abortsthe new connection
+   */
+#define DEF_ACCEPT_CALLBACK  err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err)
+#else /* LWIP_CALLBACK_API */
+#define DEF_ACCEPT_CALLBACK
+#endif /* LWIP_CALLBACK_API */
+
+/**
+ * members common to struct tcp_pcb and struct tcp_listen_pcb
+ */
+#define TCP_PCB_COMMON(type) \
+  type *next; /* for the linked list */ \
+  enum tcp_state state; /* TCP state */ \
+  u8_t prio; \
+  void *callback_arg; \
+  /* ports are in host byte order */ \
+  u16_t local_port; \
+  /* the accept callback for listen- and normal pcbs, if LWIP_CALLBACK_API */ \
+  DEF_ACCEPT_CALLBACK
+
+
+/* the TCP protocol control block */
+struct tcp_pcb {
+/** common PCB members */
+  IP_PCB;
+/** protocol specific PCB members */
+  TCP_PCB_COMMON(struct tcp_pcb);
+
+  /* ports are in host byte order */
+  u16_t remote_port;
+  
+  u8_t flags;
+#define TF_ACK_DELAY   ((u8_t)0x01U)   /* Delayed ACK. */
+#define TF_ACK_NOW     ((u8_t)0x02U)   /* Immediate ACK. */
+#define TF_INFR        ((u8_t)0x04U)   /* In fast recovery. */
+#define TF_TIMESTAMP   ((u8_t)0x08U)   /* Timestamp option enabled */
+#define TF_FIN         ((u8_t)0x20U)   /* Connection was closed locally (FIN segment enqueued). */
+#define TF_NODELAY     ((u8_t)0x40U)   /* Disable Nagle algorithm */
+#define TF_NAGLEMEMERR ((u8_t)0x80U)   /* nagle enabled, memerr, try to output to prevent delayed ACK to happen */
+
+  /* the rest of the fields are in host byte order
+     as we have to do some math with them */
+  /* receiver variables */
+  u32_t rcv_nxt;   /* next seqno expected */
+  u16_t rcv_wnd;   /* receiver window available */
+  u16_t rcv_ann_wnd; /* receiver window to announce */
+  u32_t rcv_ann_right_edge; /* announced right edge of window */
+
+  /* Timers */
+  u32_t tmr;
+  u8_t polltmr, pollinterval;
+  
+  /* Retransmission timer. */
+  s16_t rtime;
+  
+  u16_t mss;   /* maximum segment size */
+  
+  /* RTT (round trip time) estimation variables */
+  u32_t rttest; /* RTT estimate in 500ms ticks */
+  u32_t rtseq;  /* sequence number being timed */
+  s16_t sa, sv; /* @todo document this */
+
+  s16_t rto;    /* retransmission time-out */
+  u8_t nrtx;    /* number of retransmissions */
+
+  /* fast retransmit/recovery */
+  u32_t lastack; /* Highest acknowledged seqno. */
+  u8_t dupacks;
+  
+  /* congestion avoidance/control variables */
+  u16_t cwnd;  
+  u16_t ssthresh;
+
+  /* sender variables */
+  u32_t snd_nxt;   /* next new seqno to be sent */
+  u16_t snd_wnd;   /* sender window */
+  u32_t snd_wl1, snd_wl2; /* Sequence and acknowledgement numbers of last
+                             window update. */
+  u32_t snd_lbb;       /* Sequence number of next byte to be buffered. */
+
+  u16_t acked;
+  
+  u16_t snd_buf;   /* Available buffer space for sending (in bytes). */
+#define TCP_SNDQUEUELEN_OVERFLOW (0xffff-3)
+  u16_t snd_queuelen; /* Available buffer space for sending (in tcp_segs). */
+  
+  
+  /* These are ordered by sequence number: */
+  struct tcp_seg *unsent;   /* Unsent (queued) segments. */
+  struct tcp_seg *unacked;  /* Sent but unacknowledged segments. */
+#if TCP_QUEUE_OOSEQ  
+  struct tcp_seg *ooseq;    /* Received out of sequence segments. */
+#endif /* TCP_QUEUE_OOSEQ */
+
+  struct pbuf *refused_data; /* Data previously received but not yet taken by upper layer */
+
+#if LWIP_CALLBACK_API
+  /* Function to be called when more send buffer space is available.
+   * @param arg user-supplied argument (tcp_pcb.callback_arg)
+   * @param pcb the tcp_pcb which has send buffer space available
+   * @param space the amount of bytes available
+   * @return ERR_OK: try to send some data by calling tcp_output
+   */
+  err_t (* sent)(void *arg, struct tcp_pcb *pcb, u16_t space);
+  
+  /* Function to be called when (in-sequence) data has arrived.
+   * @param arg user-supplied argument (tcp_pcb.callback_arg)
+   * @param pcb the tcp_pcb for which data has arrived
+   * @param p the packet buffer which arrived
+   * @param err an error argument (TODO: that is current always ERR_OK?)
+   * @return ERR_OK: try to send some data by calling tcp_output
+   */
+  err_t (* recv)(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err);
+
+  /* Function to be called when a connection has been set up.
+   * @param arg user-supplied argument (tcp_pcb.callback_arg)
+   * @param pcb the tcp_pcb that now is connected
+   * @param err an error argument (TODO: that is current always ERR_OK?)
+   * @return value is currently ignored
+   */
+  err_t (* connected)(void *arg, struct tcp_pcb *pcb, err_t err);
+
+  /* Function which is called periodically.
+   * The period can be adjusted in multiples of the TCP slow timer interval
+   * by changing tcp_pcb.polltmr.
+   * @param arg user-supplied argument (tcp_pcb.callback_arg)
+   * @param pcb the tcp_pcb to poll for
+   * @return ERR_OK: try to send some data by calling tcp_output
+   */
+  err_t (* poll)(void *arg, struct tcp_pcb *pcb);
+
+  /* Function to be called whenever a fatal error occurs.
+   * There is no pcb parameter since most of the times, the pcb is
+   * already deallocated (or there is no pcb) when this function is called.
+   * @param arg user-supplied argument (tcp_pcb.callback_arg)
+   * @param err an indication why the error callback is called:
+   *            ERR_ABRT: aborted through tcp_abort or by a TCP timer
+   *            ERR_RST: the connection was reset by the remote host
+   */
+  void (* errf)(void *arg, err_t err);
+#endif /* LWIP_CALLBACK_API */
+
+#if LWIP_TCP_TIMESTAMPS
+  u32_t ts_lastacksent;
+  u32_t ts_recent;
+#endif /* LWIP_TCP_TIMESTAMPS */
+
+  /* idle time before KEEPALIVE is sent */
+  u32_t keep_idle;
+#if LWIP_TCP_KEEPALIVE
+  u32_t keep_intvl;
+  u32_t keep_cnt;
+#endif /* LWIP_TCP_KEEPALIVE */
+  
+  /* Persist timer counter */
+  u32_t persist_cnt;
+  /* Persist timer back-off */
+  u8_t persist_backoff;
+
+  /* KEEPALIVE counter */
+  u8_t keep_cnt_sent;
+};
+
+struct tcp_pcb_listen {  
+/* Common members of all PCB types */
+  IP_PCB;
+/* Protocol specific PCB members */
+  TCP_PCB_COMMON(struct tcp_pcb_listen);
+
+#if TCP_LISTEN_BACKLOG
+  u8_t backlog;
+  u8_t accepts_pending;
+#endif /* TCP_LISTEN_BACKLOG */
+};
+
+#if LWIP_EVENT_API
+
+enum lwip_event {
+  LWIP_EVENT_ACCEPT,
+  LWIP_EVENT_SENT,
+  LWIP_EVENT_RECV,
+  LWIP_EVENT_CONNECTED,
+  LWIP_EVENT_POLL,
+  LWIP_EVENT_ERR
+};
+
+err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb,
+         enum lwip_event,
+         struct pbuf *p,
+         u16_t size,
+         err_t err);
+
+#define TCP_EVENT_ACCEPT(pcb,err,ret)    ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_ACCEPT, NULL, 0, err)
+#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                   LWIP_EVENT_SENT, NULL, space, ERR_OK)
+#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_RECV, (p), 0, (err))
+#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_CONNECTED, NULL, 0, (err))
+#define TCP_EVENT_POLL(pcb,ret)       ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_POLL, NULL, 0, ERR_OK)
+#define TCP_EVENT_ERR(errf,arg,err)  lwip_tcp_event((arg), NULL, \
+                LWIP_EVENT_ERR, NULL, 0, (err))
+#else /* LWIP_EVENT_API */
+
+#define TCP_EVENT_ACCEPT(pcb,err,ret)                          \
+  do {                                                         \
+    if((pcb)->accept != NULL)                                  \
+      (ret) = (pcb)->accept((pcb)->callback_arg,(pcb),(err));  \
+    else (ret) = ERR_OK;                                       \
+  } while (0)
+
+#define TCP_EVENT_SENT(pcb,space,ret)                          \
+  do {                                                         \
+    if((pcb)->sent != NULL)                                    \
+      (ret) = (pcb)->sent((pcb)->callback_arg,(pcb),(space));  \
+    else (ret) = ERR_OK;                                       \
+  } while (0)
+
+#define TCP_EVENT_RECV(pcb,p,err,ret)                           \
+  do {                                                          \
+    if((pcb)->recv != NULL) {                                   \
+      (ret) = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err)); \
+    } else {                                                    \
+      (ret) = tcp_recv_null(NULL, (pcb), (p), (err));           \
+    }                                                           \
+  } while (0)
+
+#define TCP_EVENT_CONNECTED(pcb,err,ret)                         \
+  do {                                                           \
+    if((pcb)->connected != NULL)                                 \
+      (ret) = (pcb)->connected((pcb)->callback_arg,(pcb),(err)); \
+    else (ret) = ERR_OK;                                         \
+  } while (0)
+
+#define TCP_EVENT_POLL(pcb,ret)                                \
+  do {                                                         \
+    if((pcb)->poll != NULL)                                    \
+      (ret) = (pcb)->poll((pcb)->callback_arg,(pcb));          \
+    else (ret) = ERR_OK;                                       \
+  } while (0)
+
+#define TCP_EVENT_ERR(errf,arg,err)                            \
+  do {                                                         \
+    if((errf) != NULL)                                         \
+      (errf)((arg),(err));                                     \
+  } while (0)
+
+#endif /* LWIP_EVENT_API */
+
+/* This structure represents a TCP segment on the unsent and unacked queues */
+struct tcp_seg {
+  struct tcp_seg *next;    /* used when putting segements on a queue */
+  struct pbuf *p;          /* buffer containing data + TCP header */
+  void *dataptr;           /* pointer to the TCP data in the pbuf */
+  u16_t len;               /* the TCP length of this segment */
+  u8_t  flags;
+#define TF_SEG_OPTS_MSS   (u8_t)0x01U   /* Include MSS option. */
+#define TF_SEG_OPTS_TS    (u8_t)0x02U   /* Include timestamp option. */
+  struct tcp_hdr *tcphdr;  /* the TCP header */
+};
+
+#define LWIP_TCP_OPT_LENGTH(flags)              \
+  (flags & TF_SEG_OPTS_MSS ? 4  : 0) +          \
+  (flags & TF_SEG_OPTS_TS  ? 12 : 0)
+
+/** This returns a TCP header option for MSS in an u32_t */
+#define TCP_BUILD_MSS_OPTION(x) (x) = htonl(((u32_t)2 << 24) |          \
+                                            ((u32_t)4 << 16) |          \
+                                            (((u32_t)TCP_MSS / 256) << 8) | \
+                                            (TCP_MSS & 255))
+
+/* Internal functions and global variables: */
+struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb);
+void tcp_pcb_purge(struct tcp_pcb *pcb);
+void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb);
+
+u8_t tcp_segs_free(struct tcp_seg *seg);
+u8_t tcp_seg_free(struct tcp_seg *seg);
+struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg);
+
+#define tcp_ack(pcb)                               \
+  do {                                             \
+    if((pcb)->flags & TF_ACK_DELAY) {              \
+      (pcb)->flags &= ~TF_ACK_DELAY;               \
+      (pcb)->flags |= TF_ACK_NOW;                  \
+      tcp_output(pcb);                             \
+    }                                              \
+    else {                                         \
+      (pcb)->flags |= TF_ACK_DELAY;                \
+    }                                              \
+  } while (0)
+
+#define tcp_ack_now(pcb)                           \
+  do {                                             \
+    (pcb)->flags |= TF_ACK_NOW;                    \
+    tcp_output(pcb);                               \
+  } while (0)
+
+err_t tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags);
+err_t tcp_enqueue(struct tcp_pcb *pcb, void *dataptr, u16_t len,
+                  u8_t flags, u8_t apiflags, u8_t optflags);
+
+void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg);
+
+void tcp_rst(u32_t seqno, u32_t ackno,
+       struct ip_addr *local_ip, struct ip_addr *remote_ip,
+       u16_t local_port, u16_t remote_port);
+
+u32_t tcp_next_iss(void);
+
+void tcp_keepalive(struct tcp_pcb *pcb);
+void tcp_zero_window_probe(struct tcp_pcb *pcb);
+
+#if TCP_CALCULATE_EFF_SEND_MSS
+u16_t tcp_eff_send_mss(u16_t sendmss, struct ip_addr *addr);
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+
+#if LWIP_CALLBACK_API
+err_t tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err);
+#endif /* LWIP_CALLBACK_API */
+
+extern struct tcp_pcb *tcp_input_pcb;
+extern u32_t tcp_ticks;
+
+const char* tcp_debug_state_str(enum tcp_state s);
+#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
+void tcp_debug_print(struct tcp_hdr *tcphdr);
+void tcp_debug_print_flags(u8_t flags);
+void tcp_debug_print_state(enum tcp_state s);
+void tcp_debug_print_pcbs(void);
+s16_t tcp_pcbs_sane(void);
+#else
+#  define tcp_debug_print(tcphdr)
+#  define tcp_debug_print_flags(flags)
+#  define tcp_debug_print_state(s)
+#  define tcp_debug_print_pcbs()
+#  define tcp_pcbs_sane() 1
+#endif /* TCP_DEBUG */
+
+#if NO_SYS
+#define tcp_timer_needed()
+#else
+void tcp_timer_needed(void);
+#endif
+
+/* The TCP PCB lists. */
+union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */
+  struct tcp_pcb_listen *listen_pcbs; 
+  struct tcp_pcb *pcbs;
+};
+extern union tcp_listen_pcbs_t tcp_listen_pcbs;
+extern struct tcp_pcb *tcp_active_pcbs;  /* List of all TCP PCBs that are in a
+              state in which they accept or send
+              data. */
+extern struct tcp_pcb *tcp_tw_pcbs;      /* List of all TCP PCBs in TIME-WAIT. */
+
+extern struct tcp_pcb *tcp_tmp_pcb;      /* Only used for temporary storage. */
+
+/* Axioms about the above lists:   
+   1) Every TCP PCB that is not CLOSED is in one of the lists.
+   2) A PCB is only in one of the lists.
+   3) All PCBs in the tcp_listen_pcbs list is in LISTEN state.
+   4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state.
+*/
+
+/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB
+   with a PCB list or removes a PCB from a list, respectively. */
+#if 0
+#define TCP_REG(pcbs, npcb) do {\
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %d\n", npcb, npcb->local_port)); \
+                            for(tcp_tmp_pcb = *pcbs; \
+          tcp_tmp_pcb != NULL; \
+        tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+                                LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != npcb); \
+                            } \
+                            LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", npcb->state != CLOSED); \
+                            npcb->next = *pcbs; \
+                            LWIP_ASSERT("TCP_REG: npcb->next != npcb", npcb->next != npcb); \
+                            *(pcbs) = npcb; \
+                            LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
+              tcp_timer_needed(); \
+                            } while(0)
+#define TCP_RMV(pcbs, npcb) do { \
+                            LWIP_ASSERT("TCP_RMV: pcbs != NULL", *pcbs != NULL); \
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", npcb, *pcbs)); \
+                            if(*pcbs == npcb) { \
+                               *pcbs = (*pcbs)->next; \
+                            } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+                               if(tcp_tmp_pcb->next == npcb) { \
+                                  tcp_tmp_pcb->next = npcb->next; \
+                                  break; \
+                               } \
+                            } \
+                            npcb->next = NULL; \
+                            LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", npcb, *pcbs)); \
+                            } while(0)
+
+#else /* LWIP_DEBUG */
+
+#define TCP_REG(pcbs, npcb)                        \
+  do {                                             \
+    npcb->next = *pcbs;                            \
+    *(pcbs) = npcb;                                \
+    tcp_timer_needed();                            \
+  } while (0)
+
+#define TCP_RMV(pcbs, npcb)                        \
+  do {                                             \
+    if(*(pcbs) == npcb) {                          \
+      (*(pcbs)) = (*pcbs)->next;                   \
+    }                                              \
+    else {                                         \
+      for(tcp_tmp_pcb = *pcbs;                                         \
+          tcp_tmp_pcb != NULL;                                         \
+          tcp_tmp_pcb = tcp_tmp_pcb->next) {                           \
+        if(tcp_tmp_pcb->next == npcb) {   \
+          tcp_tmp_pcb->next = npcb->next;          \
+          break;                                   \
+        }                                          \
+      }                                            \
+    }                                              \
+    npcb->next = NULL;                             \
+  } while(0)
+
+#endif /* LWIP_DEBUG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_TCP */
+
+#endif /* __LWIP_TCP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/tcpip.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/tcpip.h
new file mode 100644
index 0000000..75393ee
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/tcpip.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_TCPIP_H__
+#define __LWIP_TCPIP_H__
+
+#include "lwip/opt.h"
+
+#if !NO_SYS /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/api_msg.h"
+#include "lwip/netifapi.h"
+#include "lwip/pbuf.h"
+#include "lwip/api.h"
+#include "lwip/sys.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_TCPIP_CORE_LOCKING
+/** The global semaphore to lock the stack. */
+extern sys_sem_t lock_tcpip_core;
+#define LOCK_TCPIP_CORE()     sys_sem_wait(lock_tcpip_core)
+#define UNLOCK_TCPIP_CORE()   sys_sem_signal(lock_tcpip_core)
+#define TCPIP_APIMSG(m)       tcpip_apimsg_lock(m)
+#define TCPIP_APIMSG_ACK(m)
+#define TCPIP_NETIFAPI(m)     tcpip_netifapi_lock(m)
+#define TCPIP_NETIFAPI_ACK(m)
+#else
+#define LOCK_TCPIP_CORE()
+#define UNLOCK_TCPIP_CORE()
+#define TCPIP_APIMSG(m)       tcpip_apimsg(m)
+#define TCPIP_APIMSG_ACK(m)   sys_sem_signal(m->conn->op_completed)
+#define TCPIP_NETIFAPI(m)     tcpip_netifapi(m)
+#define TCPIP_NETIFAPI_ACK(m) sys_sem_signal(m->sem)
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+
+void tcpip_init(void (* tcpip_init_done)(void *), void *arg);
+
+#if LWIP_NETCONN
+err_t tcpip_apimsg(struct api_msg *apimsg);
+#if LWIP_TCPIP_CORE_LOCKING
+err_t tcpip_apimsg_lock(struct api_msg *apimsg);
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+#endif /* LWIP_NETCONN */
+
+err_t tcpip_input(struct pbuf *p, struct netif *inp);
+
+#if LWIP_NETIF_API
+err_t tcpip_netifapi(struct netifapi_msg *netifapimsg);
+#if LWIP_TCPIP_CORE_LOCKING
+err_t tcpip_netifapi_lock(struct netifapi_msg *netifapimsg);
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+#endif /* LWIP_NETIF_API */
+
+err_t tcpip_callback_with_block(void (*f)(void *ctx), void *ctx, u8_t block);
+#define tcpip_callback(f, ctx)              tcpip_callback_with_block(f, ctx, 1)
+
+/* free pbufs or heap memory from another context without blocking */
+err_t pbuf_free_callback(struct pbuf *p);
+err_t mem_free_callback(void *m);
+
+err_t tcpip_timeout(u32_t msecs, sys_timeout_handler h, void *arg);
+err_t tcpip_untimeout(sys_timeout_handler h, void *arg);
+
+enum tcpip_msg_type {
+#if LWIP_NETCONN
+  TCPIP_MSG_API,
+#endif /* LWIP_NETCONN */
+  TCPIP_MSG_INPKT,
+#if LWIP_NETIF_API
+  TCPIP_MSG_NETIFAPI,
+#endif /* LWIP_NETIF_API */
+  TCPIP_MSG_CALLBACK,
+  TCPIP_MSG_TIMEOUT,
+  TCPIP_MSG_UNTIMEOUT
+};
+
+struct tcpip_msg {
+  enum tcpip_msg_type type;
+  sys_sem_t *sem;
+  union {
+#if LWIP_NETCONN
+    struct api_msg *apimsg;
+#endif /* LWIP_NETCONN */
+#if LWIP_NETIF_API
+    struct netifapi_msg *netifapimsg;
+#endif /* LWIP_NETIF_API */
+    struct {
+      struct pbuf *p;
+      struct netif *netif;
+    } inp;
+    struct {
+      void (*f)(void *ctx);
+      void *ctx;
+    } cb;
+    struct {
+      u32_t msecs;
+      sys_timeout_handler h;
+      void *arg;
+    } tmo;
+  } msg;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !NO_SYS */
+
+#endif /* __LWIP_TCPIP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/udp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/udp.h
new file mode 100644
index 0000000..08d1817
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/lwip/udp.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_UDP_H__
+#define __LWIP_UDP_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_UDP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/ip_addr.h"
+#include "lwip/ip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define UDP_HLEN 8
+
+/* Fields are (of course) in network byte order. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct udp_hdr {
+  PACK_STRUCT_FIELD(u16_t src);
+  PACK_STRUCT_FIELD(u16_t dest);  /* src/dest UDP ports */
+  PACK_STRUCT_FIELD(u16_t len);
+  PACK_STRUCT_FIELD(u16_t chksum);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define UDP_FLAGS_NOCHKSUM 0x01U
+#define UDP_FLAGS_UDPLITE  0x02U
+#define UDP_FLAGS_CONNECTED  0x04U
+
+struct udp_pcb {
+/* Common members of all PCB types */
+  IP_PCB;
+
+/* Protocol specific PCB members */
+
+  struct udp_pcb *next;
+
+  u8_t flags;
+  /* ports are in host byte order */
+  u16_t local_port, remote_port;
+
+#if LWIP_IGMP
+  /* outgoing network interface for multicast packets */
+  struct ip_addr multicast_ip;
+#endif /* LWIP_IGMP */
+
+#if LWIP_UDPLITE
+  /* used for UDP_LITE only */
+  u16_t chksum_len_rx, chksum_len_tx;
+#endif /* LWIP_UDPLITE */
+
+  /* receive callback function
+   * addr and port are in same byte order as in the pcb
+   * The callback is responsible for freeing the pbuf
+   * if it's not used any more.
+   *
+   * ATTENTION: Be aware that 'addr' points into the pbuf 'p' so freeing this pbuf
+   *            makes 'addr' invalid, too.
+   *
+   * @param arg user supplied argument (udp_pcb.recv_arg)
+   * @param pcb the udp_pcb which received data
+   * @param p the packet buffer that was received
+   * @param addr the remote IP address from which the packet was received
+   * @param port the remote port from which the packet was received
+   */
+  void (* recv)(void *arg, struct udp_pcb *pcb, struct pbuf *p,
+    struct ip_addr *addr, u16_t port);
+  /* user-supplied argument for the recv callback */
+  void *recv_arg;  
+};
+/* udp_pcbs export for exernal reference (e.g. SNMP agent) */
+extern struct udp_pcb *udp_pcbs;
+
+/* The following functions is the application layer interface to the
+   UDP code. */
+struct udp_pcb * udp_new        (void);
+void             udp_remove     (struct udp_pcb *pcb);
+err_t            udp_bind       (struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port);
+err_t            udp_connect    (struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port);
+void             udp_disconnect    (struct udp_pcb *pcb);
+void             udp_recv       (struct udp_pcb *pcb,
+         void (* recv)(void *arg, struct udp_pcb *upcb,
+                 struct pbuf *p,
+                 struct ip_addr *addr,
+                 u16_t port),
+         void *recv_arg);
+err_t            udp_sendto_if  (struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *dst_ip, u16_t dst_port, struct netif *netif);
+err_t            udp_sendto     (struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *dst_ip, u16_t dst_port);
+err_t            udp_send       (struct udp_pcb *pcb, struct pbuf *p);
+
+#define          udp_flags(pcb)  ((pcb)->flags)
+#define          udp_setflags(pcb, f)  ((pcb)->flags = (f))
+
+/* The following functions are the lower layer interface to UDP. */
+void             udp_input      (struct pbuf *p, struct netif *inp);
+
+#define udp_init() /* Compatibility define, not init needed. */
+
+#if UDP_DEBUG
+void udp_debug_print(struct udp_hdr *udphdr);
+#else
+#define udp_debug_print(udphdr)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_UDP */
+
+#endif /* __LWIP_UDP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/netif/etharp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/netif/etharp.h
new file mode 100644
index 0000000..72b8d79
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/netif/etharp.h
@@ -0,0 +1,192 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (c) 2003-2004 Leon Woestenberg 
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef __NETIF_ETHARP_H__
+#define __NETIF_ETHARP_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_ARP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/ip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef ETH_PAD_SIZE
+#define ETH_PAD_SIZE          0
+#endif
+
+#ifndef ETHARP_HWADDR_LEN
+#define ETHARP_HWADDR_LEN     6
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct eth_addr {
+  PACK_STRUCT_FIELD(u8_t addr[ETHARP_HWADDR_LEN]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct eth_hdr {
+#if ETH_PAD_SIZE
+  PACK_STRUCT_FIELD(u8_t padding[ETH_PAD_SIZE]);
+#endif
+  PACK_STRUCT_FIELD(struct eth_addr dest);
+  PACK_STRUCT_FIELD(struct eth_addr src);
+  PACK_STRUCT_FIELD(u16_t type);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define SIZEOF_ETH_HDR (14 + ETH_PAD_SIZE)
+
+#if ETHARP_SUPPORT_VLAN
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct eth_vlan_hdr {
+  PACK_STRUCT_FIELD(u16_t tpid);
+  PACK_STRUCT_FIELD(u16_t prio_vid);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define SIZEOF_VLAN_HDR 4
+#define VLAN_ID(vlan_hdr) (htons((vlan_hdr)->prio_vid) & 0xFFF)
+
+#endif /* ETHARP_SUPPORT_VLAN */
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** the ARP message */
+struct etharp_hdr {
+  PACK_STRUCT_FIELD(u16_t hwtype);
+  PACK_STRUCT_FIELD(u16_t proto);
+  PACK_STRUCT_FIELD(u16_t _hwlen_protolen);
+  PACK_STRUCT_FIELD(u16_t opcode);
+  PACK_STRUCT_FIELD(struct eth_addr shwaddr);
+  PACK_STRUCT_FIELD(struct ip_addr2 sipaddr);
+  PACK_STRUCT_FIELD(struct eth_addr dhwaddr);
+  PACK_STRUCT_FIELD(struct ip_addr2 dipaddr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define SIZEOF_ETHARP_HDR 28
+#define SIZEOF_ETHARP_PACKET (SIZEOF_ETH_HDR + SIZEOF_ETHARP_HDR)
+
+/** 5 seconds period */
+#define ARP_TMR_INTERVAL 5000
+
+#define ETHTYPE_ARP       0x0806
+#define ETHTYPE_IP        0x0800
+#define ETHTYPE_VLAN      0x8100
+#define ETHTYPE_PPPOEDISC 0x8863  /* PPP Over Ethernet Discovery Stage */
+#define ETHTYPE_PPPOE     0x8864  /* PPP Over Ethernet Session Stage */
+
+/** ARP message types (opcodes) */
+#define ARP_REQUEST 1
+#define ARP_REPLY   2
+
+#if ARP_QUEUEING
+/** struct for queueing outgoing packets for unknown address
+  * defined here to be accessed by memp.h
+  */
+struct etharp_q_entry {
+  struct etharp_q_entry *next;
+  struct pbuf *p;
+};
+#endif /* ARP_QUEUEING */
+
+#define etharp_init() /* Compatibility define, not init needed. */
+void etharp_tmr(void);
+s8_t etharp_find_addr(struct netif *netif, struct ip_addr *ipaddr,
+         struct eth_addr **eth_ret, struct ip_addr **ip_ret);
+void etharp_ip_input(struct netif *netif, struct pbuf *p);
+void etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr,
+         struct pbuf *p);
+err_t etharp_output(struct netif *netif, struct pbuf *q, struct ip_addr *ipaddr);
+err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q);
+err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr);
+/** For Ethernet network interfaces, we might want to send "gratuitous ARP";
+ *  this is an ARP packet sent by a node in order to spontaneously cause other
+ *  nodes to update an entry in their ARP cache.
+ *  From RFC 3220 "IP Mobility Support for IPv4" section 4.6. */
+#define etharp_gratuitous(netif) etharp_request((netif), &(netif)->ip_addr)
+
+err_t ethernet_input(struct pbuf *p, struct netif *netif);
+
+#if LWIP_AUTOIP
+err_t etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr,
+                 const struct eth_addr *ethdst_addr,
+                 const struct eth_addr *hwsrc_addr, const struct ip_addr *ipsrc_addr,
+                 const struct eth_addr *hwdst_addr, const struct ip_addr *ipdst_addr,
+                 const u16_t opcode);
+#endif /* LWIP_AUTOIP */
+
+#define eth_addr_cmp(addr1, addr2) (memcmp((addr1)->addr, (addr2)->addr, ETHARP_HWADDR_LEN) == 0)
+
+extern const struct eth_addr ethbroadcast, ethzero;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_ARP */
+
+#endif /* __NETIF_ARP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/netif/loopif.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/netif/loopif.h
new file mode 100644
index 0000000..304af4b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/netif/loopif.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __NETIF_LOOPIF_H__
+#define __NETIF_LOOPIF_H__
+
+#include "lwip/opt.h"
+#include "lwip/netif.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !LWIP_NETIF_LOOPBACK_MULTITHREADING
+#define loopif_poll netif_poll
+#endif /* !LWIP_NETIF_LOOPBACK_MULTITHREADING */
+
+err_t loopif_init(struct netif *netif);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NETIF_LOOPIF_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/netif/ppp_oe.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/netif/ppp_oe.h
new file mode 100644
index 0000000..3aa55ae
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/netif/ppp_oe.h
@@ -0,0 +1,161 @@
+/*****************************************************************************
+* ppp_oe.h - PPP Over Ethernet implementation for lwIP.
+*
+* Copyright (c) 2006 by Marc Boucher, Services Informatiques (MBSI) inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 06-01-01 Marc Boucher 
+*   Ported to lwIP.
+*****************************************************************************/
+
+
+
+/* based on NetBSD: if_pppoe.c,v 1.64 2006/01/31 23:50:15 martin Exp */
+
+/*-
+ * Copyright (c) 2002 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Martin Husemann .
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef PPP_OE_H
+#define PPP_OE_H
+
+#include "lwip/opt.h"
+
+#if PPPOE_SUPPORT > 0
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct pppoehdr {
+	PACK_STRUCT_FIELD(u8_t vertype);
+	PACK_STRUCT_FIELD(u8_t code);
+	PACK_STRUCT_FIELD(u16_t session);
+	PACK_STRUCT_FIELD(u16_t plen);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct pppoetag {
+	PACK_STRUCT_FIELD(u16_t tag);
+	PACK_STRUCT_FIELD(u16_t len);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+
+#define PPPOE_STATE_INITIAL	0
+#define PPPOE_STATE_PADI_SENT	1
+#define	PPPOE_STATE_PADR_SENT	2
+#define	PPPOE_STATE_SESSION	3
+#define	PPPOE_STATE_CLOSING	4
+/* passive */
+#define	PPPOE_STATE_PADO_SENT	1
+
+#define PPPOE_HEADERLEN	sizeof(struct pppoehdr)
+#define	PPPOE_VERTYPE	0x11	/* VER=1, TYPE = 1 */
+
+#define	PPPOE_TAG_EOL		0x0000		/* end of list */
+#define	PPPOE_TAG_SNAME		0x0101		/* service name */
+#define	PPPOE_TAG_ACNAME	0x0102		/* access concentrator name */
+#define	PPPOE_TAG_HUNIQUE	0x0103		/* host unique */
+#define	PPPOE_TAG_ACCOOKIE	0x0104		/* AC cookie */
+#define	PPPOE_TAG_VENDOR	0x0105		/* vendor specific */
+#define	PPPOE_TAG_RELAYSID	0x0110		/* relay session id */
+#define	PPPOE_TAG_SNAME_ERR	0x0201		/* service name error */
+#define	PPPOE_TAG_ACSYS_ERR	0x0202		/* AC system error */
+#define	PPPOE_TAG_GENERIC_ERR	0x0203		/* gerneric error */
+
+#define PPPOE_CODE_PADI		0x09		/* Active Discovery Initiation */
+#define	PPPOE_CODE_PADO		0x07		/* Active Discovery Offer */
+#define	PPPOE_CODE_PADR		0x19		/* Active Discovery Request */
+#define	PPPOE_CODE_PADS		0x65		/* Active Discovery Session confirmation */
+#define	PPPOE_CODE_PADT		0xA7		/* Active Discovery Terminate */
+
+#ifndef ETHERMTU
+#define ETHERMTU 1500
+#endif
+
+/* two byte PPP protocol discriminator, then IP data */
+#define	PPPOE_MAXMTU	(ETHERMTU-PPPOE_HEADERLEN-2)
+
+struct pppoe_softc;
+
+
+void pppoe_init(void);
+
+err_t pppoe_create(struct netif *ethif, int pd, void (*linkStatusCB)(int pd, int up), struct pppoe_softc **scptr);
+err_t pppoe_destroy(struct netif *ifp);
+
+int pppoe_connect(struct pppoe_softc *sc);
+void pppoe_disconnect(struct pppoe_softc *sc);
+
+void pppoe_disc_input(struct netif *netif, struct pbuf *p);
+void pppoe_data_input(struct netif *netif, struct pbuf *p);
+
+err_t pppoe_xmit(struct pppoe_softc *sc, struct pbuf *pb);
+
+extern int pppoe_hdrlen;
+
+#endif /* PPPOE_SUPPORT */
+
+#endif /* PPP_OE_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/netif/slipif.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/netif/slipif.h
new file mode 100644
index 0000000..ccd03c8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/include/netif/slipif.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __NETIF_SLIPIF_H__
+#define __NETIF_SLIPIF_H__
+
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+err_t slipif_init(struct netif * netif);
+void slipif_poll(struct netif *netif);
+
+#ifdef __cplusplus
+}
+#endif
+ 
+#endif 
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/FILES b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/FILES
new file mode 100644
index 0000000..099dbf3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/FILES
@@ -0,0 +1,29 @@
+This directory contains generic network interface device drivers that
+do not contain any hardware or architecture specific code. The files
+are:
+
+etharp.c
+          Implements the ARP (Address Resolution Protocol) over
+          Ethernet. The code in this file should be used together with
+          Ethernet device drivers. Note that this module has been
+          largely made Ethernet independent so you should be able to
+          adapt this for other link layers (such as Firewire).
+
+ethernetif.c
+          An example of how an Ethernet device driver could look. This
+          file can be used as a "skeleton" for developing new Ethernet
+          network device drivers. It uses the etharp.c ARP code.
+
+loopif.c
+          A "loopback" network interface driver. It requires configuration
+          through the define LWIP_LOOPIF_MULTITHREADING (see opt.h).
+
+slipif.c
+          A generic implementation of the SLIP (Serial Line IP)
+          protocol. It requires a sio (serial I/O) module to work.
+
+ppp/      Point-to-Point Protocol stack
+          The PPP stack has been ported from ucip (http://ucip.sourceforge.net).
+          It matches quite well to pppd 2.3.1 (http://ppp.samba.org), although
+          compared to that, it has some modifications for embedded systems and
+          the source code has been reordered a bit.
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/etharp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/etharp.c
new file mode 100644
index 0000000..8f6872f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/etharp.c
@@ -0,0 +1,1222 @@
+/**
+ * @file
+ * Address Resolution Protocol module for IP over Ethernet
+ *
+ * Functionally, ARP is divided into two parts. The first maps an IP address
+ * to a physical address when sending a packet, and the second part answers
+ * requests from other machines for our physical address.
+ *
+ * This implementation complies with RFC 826 (Ethernet ARP). It supports
+ * Gratuitious ARP from RFC3220 (IP Mobility Support for IPv4) section 4.6
+ * if an interface calls etharp_gratuitous(our_netif) upon address change.
+ */
+
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (c) 2003-2004 Leon Woestenberg 
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+ 
+#include "lwip/opt.h"
+
+#if LWIP_ARP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+#include "lwip/dhcp.h"
+#include "lwip/autoip.h"
+#include "netif/etharp.h"
+
+#if PPPOE_SUPPORT
+#include "netif/ppp_oe.h"
+#endif /* PPPOE_SUPPORT */
+
+#include 
+
+/** the time an ARP entry stays valid after its last update,
+ *  for ARP_TMR_INTERVAL = 5000, this is
+ *  (240 * 5) seconds = 20 minutes.
+ */
+#define ARP_MAXAGE 240
+/** the time an ARP entry stays pending after first request,
+ *  for ARP_TMR_INTERVAL = 5000, this is
+ *  (2 * 5) seconds = 10 seconds.
+ * 
+ *  @internal Keep this number at least 2, otherwise it might
+ *  run out instantly if the timeout occurs directly after a request.
+ */
+#define ARP_MAXPENDING 2
+
+#define HWTYPE_ETHERNET 1
+
+#define ARPH_HWLEN(hdr) (ntohs((hdr)->_hwlen_protolen) >> 8)
+#define ARPH_PROTOLEN(hdr) (ntohs((hdr)->_hwlen_protolen) & 0xff)
+
+#define ARPH_HWLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons(ARPH_PROTOLEN(hdr) | ((len) << 8))
+#define ARPH_PROTOLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons((len) | (ARPH_HWLEN(hdr) << 8))
+
+enum etharp_state {
+  ETHARP_STATE_EMPTY = 0,
+  ETHARP_STATE_PENDING,
+  ETHARP_STATE_STABLE
+};
+
+struct etharp_entry {
+#if ARP_QUEUEING
+  /** 
+   * Pointer to queue of pending outgoing packets on this ARP entry.
+   */
+  struct etharp_q_entry *q;
+#endif
+  struct ip_addr ipaddr;
+  struct eth_addr ethaddr;
+  enum etharp_state state;
+  u8_t ctime;
+  struct netif *netif;
+};
+
+const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}};
+const struct eth_addr ethzero = {{0,0,0,0,0,0}};
+static struct etharp_entry arp_table[ARP_TABLE_SIZE];
+#if !LWIP_NETIF_HWADDRHINT
+static u8_t etharp_cached_entry;
+#endif
+
+/**
+ * Try hard to create a new entry - we want the IP address to appear in
+ * the cache (even if this means removing an active entry or so). */
+#define ETHARP_TRY_HARD 1
+#define ETHARP_FIND_ONLY  2
+
+#if LWIP_NETIF_HWADDRHINT
+#define NETIF_SET_HINT(netif, hint)  if (((netif) != NULL) && ((netif)->addr_hint != NULL))  \
+                                      *((netif)->addr_hint) = (hint);
+static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags, struct netif *netif);
+#else /* LWIP_NETIF_HWADDRHINT */
+static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags);
+#endif /* LWIP_NETIF_HWADDRHINT */
+
+static err_t update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags);
+
+
+/* Some checks, instead of etharp_init(): */
+#if (LWIP_ARP && (ARP_TABLE_SIZE > 0x7f))
+  #error "If you want to use ARP, ARP_TABLE_SIZE must fit in an s8_t, so, you have to reduce it in your lwipopts.h"
+#endif
+
+
+#if ARP_QUEUEING
+/**
+ * Free a complete queue of etharp entries
+ *
+ * @param q a qeueue of etharp_q_entry's to free
+ */
+static void
+free_etharp_q(struct etharp_q_entry *q)
+{
+  struct etharp_q_entry *r;
+  LWIP_ASSERT("q != NULL", q != NULL);
+  LWIP_ASSERT("q->p != NULL", q->p != NULL);
+  while (q) {
+    r = q;
+    q = q->next;
+    LWIP_ASSERT("r->p != NULL", (r->p != NULL));
+    pbuf_free(r->p);
+    memp_free(MEMP_ARP_QUEUE, r);
+  }
+}
+#endif
+
+/**
+ * Clears expired entries in the ARP table.
+ *
+ * This function should be called every ETHARP_TMR_INTERVAL microseconds (5 seconds),
+ * in order to expire entries in the ARP table.
+ */
+void
+etharp_tmr(void)
+{
+  u8_t i;
+
+  LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n"));
+  /* remove expired entries from the ARP table */
+  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
+    arp_table[i].ctime++;
+    if (((arp_table[i].state == ETHARP_STATE_STABLE) &&
+         (arp_table[i].ctime >= ARP_MAXAGE)) ||
+        ((arp_table[i].state == ETHARP_STATE_PENDING)  &&
+         (arp_table[i].ctime >= ARP_MAXPENDING))) {
+         /* pending or stable entry has become old! */
+      LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired %s entry %"U16_F".\n",
+           arp_table[i].state == ETHARP_STATE_STABLE ? "stable" : "pending", (u16_t)i));
+      /* clean up entries that have just been expired */
+      /* remove from SNMP ARP index tree */
+      snmp_delete_arpidx_tree(arp_table[i].netif, &arp_table[i].ipaddr);
+#if ARP_QUEUEING
+      /* and empty packet queue */
+      if (arp_table[i].q != NULL) {
+        /* remove all queued packets */
+        LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].q)));
+        free_etharp_q(arp_table[i].q);
+        arp_table[i].q = NULL;
+      }
+#endif
+      /* recycle entry for re-use */      
+      arp_table[i].state = ETHARP_STATE_EMPTY;
+    }
+#if ARP_QUEUEING
+    /* still pending entry? (not expired) */
+    if (arp_table[i].state == ETHARP_STATE_PENDING) {
+        /* resend an ARP query here? */
+    }
+#endif
+  }
+}
+
+/**
+ * Search the ARP table for a matching or new entry.
+ * 
+ * If an IP address is given, return a pending or stable ARP entry that matches
+ * the address. If no match is found, create a new entry with this address set,
+ * but in state ETHARP_EMPTY. The caller must check and possibly change the
+ * state of the returned entry.
+ * 
+ * If ipaddr is NULL, return a initialized new entry in state ETHARP_EMPTY.
+ * 
+ * In all cases, attempt to create new entries from an empty entry. If no
+ * empty entries are available and ETHARP_TRY_HARD flag is set, recycle
+ * old entries. Heuristic choose the least important entry for recycling.
+ *
+ * @param ipaddr IP address to find in ARP cache, or to add if not found.
+ * @param flags
+ * - ETHARP_TRY_HARD: Try hard to create a entry by allowing recycling of
+ * active (stable or pending) entries.
+ *  
+ * @return The ARP entry index that matched or is created, ERR_MEM if no
+ * entry is found or could be recycled.
+ */
+static s8_t
+#if LWIP_NETIF_HWADDRHINT
+find_entry(struct ip_addr *ipaddr, u8_t flags, struct netif *netif)
+#else /* LWIP_NETIF_HWADDRHINT */
+find_entry(struct ip_addr *ipaddr, u8_t flags)
+#endif /* LWIP_NETIF_HWADDRHINT */
+{
+  s8_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE;
+  s8_t empty = ARP_TABLE_SIZE;
+  u8_t i = 0, age_pending = 0, age_stable = 0;
+#if ARP_QUEUEING
+  /* oldest entry with packets on queue */
+  s8_t old_queue = ARP_TABLE_SIZE;
+  /* its age */
+  u8_t age_queue = 0;
+#endif
+
+  /* First, test if the last call to this function asked for the
+   * same address. If so, we're really fast! */
+  if (ipaddr) {
+    /* ipaddr to search for was given */
+#if LWIP_NETIF_HWADDRHINT
+    if ((netif != NULL) && (netif->addr_hint != NULL)) {
+      /* per-pcb cached entry was given */
+      u8_t per_pcb_cache = *(netif->addr_hint);
+      if ((per_pcb_cache < ARP_TABLE_SIZE) && arp_table[per_pcb_cache].state == ETHARP_STATE_STABLE) {
+        /* the per-pcb-cached entry is stable */
+        if (ip_addr_cmp(ipaddr, &arp_table[per_pcb_cache].ipaddr)) {
+          /* per-pcb cached entry was the right one! */
+          ETHARP_STATS_INC(etharp.cachehit);
+          return per_pcb_cache;
+        }
+      }
+    }
+#else /* #if LWIP_NETIF_HWADDRHINT */
+    if (arp_table[etharp_cached_entry].state == ETHARP_STATE_STABLE) {
+      /* the cached entry is stable */
+      if (ip_addr_cmp(ipaddr, &arp_table[etharp_cached_entry].ipaddr)) {
+        /* cached entry was the right one! */
+        ETHARP_STATS_INC(etharp.cachehit);
+        return etharp_cached_entry;
+      }
+    }
+#endif /* #if LWIP_NETIF_HWADDRHINT */
+  }
+
+  /**
+   * a) do a search through the cache, remember candidates
+   * b) select candidate entry
+   * c) create new entry
+   */
+
+  /* a) in a single search sweep, do all of this
+   * 1) remember the first empty entry (if any)
+   * 2) remember the oldest stable entry (if any)
+   * 3) remember the oldest pending entry without queued packets (if any)
+   * 4) remember the oldest pending entry with queued packets (if any)
+   * 5) search for a matching IP entry, either pending or stable
+   *    until 5 matches, or all entries are searched for.
+   */
+
+  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
+    /* no empty entry found yet and now we do find one? */
+    if ((empty == ARP_TABLE_SIZE) && (arp_table[i].state == ETHARP_STATE_EMPTY)) {
+      LWIP_DEBUGF(ETHARP_DEBUG, ("find_entry: found empty entry %"U16_F"\n", (u16_t)i));
+      /* remember first empty entry */
+      empty = i;
+    }
+    /* pending entry? */
+    else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+      /* if given, does IP address match IP address in ARP entry? */
+      if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: found matching pending entry %"U16_F"\n", (u16_t)i));
+        /* found exact IP address match, simply bail out */
+#if LWIP_NETIF_HWADDRHINT
+        NETIF_SET_HINT(netif, i);
+#else /* #if LWIP_NETIF_HWADDRHINT */
+        etharp_cached_entry = i;
+#endif /* #if LWIP_NETIF_HWADDRHINT */
+        return i;
+#if ARP_QUEUEING
+      /* pending with queued packets? */
+      } else if (arp_table[i].q != NULL) {
+        if (arp_table[i].ctime >= age_queue) {
+          old_queue = i;
+          age_queue = arp_table[i].ctime;
+        }
+#endif
+      /* pending without queued packets? */
+      } else {
+        if (arp_table[i].ctime >= age_pending) {
+          old_pending = i;
+          age_pending = arp_table[i].ctime;
+        }
+      }        
+    }
+    /* stable entry? */
+    else if (arp_table[i].state == ETHARP_STATE_STABLE) {
+      /* if given, does IP address match IP address in ARP entry? */
+      if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: found matching stable entry %"U16_F"\n", (u16_t)i));
+        /* found exact IP address match, simply bail out */
+#if LWIP_NETIF_HWADDRHINT
+        NETIF_SET_HINT(netif, i);
+#else /* #if LWIP_NETIF_HWADDRHINT */
+        etharp_cached_entry = i;
+#endif /* #if LWIP_NETIF_HWADDRHINT */
+        return i;
+      /* remember entry with oldest stable entry in oldest, its age in maxtime */
+      } else if (arp_table[i].ctime >= age_stable) {
+        old_stable = i;
+        age_stable = arp_table[i].ctime;
+      }
+    }
+  }
+  /* { we have no match } => try to create a new entry */
+   
+  /* no empty entry found and not allowed to recycle? */
+  if (((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_TRY_HARD) == 0))
+      /* or don't create new entry, only search? */
+      || ((flags & ETHARP_FIND_ONLY) != 0)) {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: no empty entry found and not allowed to recycle\n"));
+    return (s8_t)ERR_MEM;
+  }
+  
+  /* b) choose the least destructive entry to recycle:
+   * 1) empty entry
+   * 2) oldest stable entry
+   * 3) oldest pending entry without queued packets
+   * 4) oldest pending entry with queued packets
+   * 
+   * { ETHARP_TRY_HARD is set at this point }
+   */ 
+
+  /* 1) empty entry available? */
+  if (empty < ARP_TABLE_SIZE) {
+    i = empty;
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting empty entry %"U16_F"\n", (u16_t)i));
+  }
+  /* 2) found recyclable stable entry? */
+  else if (old_stable < ARP_TABLE_SIZE) {
+    /* recycle oldest stable*/
+    i = old_stable;
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting oldest stable entry %"U16_F"\n", (u16_t)i));
+#if ARP_QUEUEING
+    /* no queued packets should exist on stable entries */
+    LWIP_ASSERT("arp_table[i].q == NULL", arp_table[i].q == NULL);
+#endif
+  /* 3) found recyclable pending entry without queued packets? */
+  } else if (old_pending < ARP_TABLE_SIZE) {
+    /* recycle oldest pending */
+    i = old_pending;
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F" (without queue)\n", (u16_t)i));
+#if ARP_QUEUEING
+  /* 4) found recyclable pending entry with queued packets? */
+  } else if (old_queue < ARP_TABLE_SIZE) {
+    /* recycle oldest pending */
+    i = old_queue;
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F", freeing packet queue %p\n", (u16_t)i, (void *)(arp_table[i].q)));
+    free_etharp_q(arp_table[i].q);
+    arp_table[i].q = NULL;
+#endif
+    /* no empty or recyclable entries found */
+  } else {
+    return (s8_t)ERR_MEM;
+  }
+
+  /* { empty or recyclable entry found } */
+  LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
+
+  if (arp_table[i].state != ETHARP_STATE_EMPTY)
+  {
+    snmp_delete_arpidx_tree(arp_table[i].netif, &arp_table[i].ipaddr);
+  }
+  /* recycle entry (no-op for an already empty entry) */
+  arp_table[i].state = ETHARP_STATE_EMPTY;
+
+  /* IP address given? */
+  if (ipaddr != NULL) {
+    /* set IP address */
+    ip_addr_set(&arp_table[i].ipaddr, ipaddr);
+  }
+  arp_table[i].ctime = 0;
+#if LWIP_NETIF_HWADDRHINT
+  NETIF_SET_HINT(netif, i);
+#else /* #if LWIP_NETIF_HWADDRHINT */
+  etharp_cached_entry = i;
+#endif /* #if LWIP_NETIF_HWADDRHINT */
+  return (err_t)i;
+}
+
+/**
+ * Send an IP packet on the network using netif->linkoutput
+ * The ethernet header is filled in before sending.
+ *
+ * @params netif the lwIP network interface on which to send the packet
+ * @params p the packet to send, p->payload pointing to the (uninitialized) ethernet header
+ * @params src the source MAC address to be copied into the ethernet header
+ * @params dst the destination MAC address to be copied into the ethernet header
+ * @return ERR_OK if the packet was sent, any other err_t on failure
+ */
+static err_t
+etharp_send_ip(struct netif *netif, struct pbuf *p, struct eth_addr *src, struct eth_addr *dst)
+{
+  struct eth_hdr *ethhdr = p->payload;
+  u8_t k;
+
+  LWIP_ASSERT("netif->hwaddr_len must be the same as ETHARP_HWADDR_LEN for etharp!",
+              (netif->hwaddr_len == ETHARP_HWADDR_LEN));
+  k = ETHARP_HWADDR_LEN;
+  while(k > 0) {
+    k--;
+    ethhdr->dest.addr[k] = dst->addr[k];
+    ethhdr->src.addr[k]  = src->addr[k];
+  }
+  ethhdr->type = htons(ETHTYPE_IP);
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_send_ip: sending packet %p\n", (void *)p));
+  /* send the packet */
+  return netif->linkoutput(netif, p);
+}
+
+/**
+ * Update (or insert) a IP/MAC address pair in the ARP cache.
+ *
+ * If a pending entry is resolved, any queued packets will be sent
+ * at this point.
+ * 
+ * @param ipaddr IP address of the inserted ARP entry.
+ * @param ethaddr Ethernet address of the inserted ARP entry.
+ * @param flags Defines behaviour:
+ * - ETHARP_TRY_HARD Allows ARP to insert this as a new item. If not specified,
+ * only existing ARP entries will be updated.
+ *
+ * @return
+ * - ERR_OK Succesfully updated ARP cache.
+ * - ERR_MEM If we could not add a new ARP entry when ETHARP_TRY_HARD was set.
+ * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
+ *
+ * @see pbuf_free()
+ */
+static err_t
+update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags)
+{
+  s8_t i;
+  u8_t k;
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("update_arp_entry()\n"));
+  LWIP_ASSERT("netif->hwaddr_len == ETHARP_HWADDR_LEN", netif->hwaddr_len == ETHARP_HWADDR_LEN);
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n",
+                                        ip4_addr1(ipaddr), ip4_addr2(ipaddr), ip4_addr3(ipaddr), ip4_addr4(ipaddr), 
+                                        ethaddr->addr[0], ethaddr->addr[1], ethaddr->addr[2],
+                                        ethaddr->addr[3], ethaddr->addr[4], ethaddr->addr[5]));
+  /* non-unicast address? */
+  if (ip_addr_isany(ipaddr) ||
+      ip_addr_isbroadcast(ipaddr, netif) ||
+      ip_addr_ismulticast(ipaddr)) {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("update_arp_entry: will not add non-unicast IP address to ARP cache\n"));
+    return ERR_ARG;
+  }
+  /* find or create ARP entry */
+#if LWIP_NETIF_HWADDRHINT
+  i = find_entry(ipaddr, flags, netif);
+#else /* LWIP_NETIF_HWADDRHINT */
+  i = find_entry(ipaddr, flags);
+#endif /* LWIP_NETIF_HWADDRHINT */
+  /* bail out if no entry could be found */
+  if (i < 0)
+    return (err_t)i;
+  
+  /* mark it stable */
+  arp_table[i].state = ETHARP_STATE_STABLE;
+  /* record network interface */
+  arp_table[i].netif = netif;
+
+  /* insert in SNMP ARP index tree */
+  snmp_insert_arpidx_tree(netif, &arp_table[i].ipaddr);
+
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("update_arp_entry: updating stable entry %"S16_F"\n", (s16_t)i));
+  /* update address */
+  k = ETHARP_HWADDR_LEN;
+  while (k > 0) {
+    k--;
+    arp_table[i].ethaddr.addr[k] = ethaddr->addr[k];
+  }
+  /* reset time stamp */
+  arp_table[i].ctime = 0;
+#if ARP_QUEUEING
+  /* this is where we will send out queued packets! */
+  while (arp_table[i].q != NULL) {
+    struct pbuf *p;
+    /* remember remainder of queue */
+    struct etharp_q_entry *q = arp_table[i].q;
+    /* pop first item off the queue */
+    arp_table[i].q = q->next;
+    /* get the packet pointer */
+    p = q->p;
+    /* now queue entry can be freed */
+    memp_free(MEMP_ARP_QUEUE, q);
+    /* send the queued IP packet */
+    etharp_send_ip(netif, p, (struct eth_addr*)(netif->hwaddr), ethaddr);
+    /* free the queued IP packet */
+    pbuf_free(p);
+  }
+#endif
+  return ERR_OK;
+}
+
+/**
+ * Finds (stable) ethernet/IP address pair from ARP table
+ * using interface and IP address index.
+ * @note the addresses in the ARP table are in network order!
+ *
+ * @param netif points to interface index
+ * @param ipaddr points to the (network order) IP address index
+ * @param eth_ret points to return pointer
+ * @param ip_ret points to return pointer
+ * @return table index if found, -1 otherwise
+ */
+s8_t
+etharp_find_addr(struct netif *netif, struct ip_addr *ipaddr,
+         struct eth_addr **eth_ret, struct ip_addr **ip_ret)
+{
+  s8_t i;
+
+  LWIP_UNUSED_ARG(netif);
+
+#if LWIP_NETIF_HWADDRHINT
+  i = find_entry(ipaddr, ETHARP_FIND_ONLY, NULL);
+#else /* LWIP_NETIF_HWADDRHINT */
+  i = find_entry(ipaddr, ETHARP_FIND_ONLY);
+#endif /* LWIP_NETIF_HWADDRHINT */
+  if((i >= 0) && arp_table[i].state == ETHARP_STATE_STABLE) {
+      *eth_ret = &arp_table[i].ethaddr;
+      *ip_ret = &arp_table[i].ipaddr;
+      return i;
+  }
+  return -1;
+}
+
+/**
+ * Updates the ARP table using the given IP packet.
+ *
+ * Uses the incoming IP packet's source address to update the
+ * ARP cache for the local network. The function does not alter
+ * or free the packet. This function must be called before the
+ * packet p is passed to the IP layer.
+ *
+ * @param netif The lwIP network interface on which the IP packet pbuf arrived.
+ * @param p The IP packet that arrived on netif.
+ *
+ * @return NULL
+ *
+ * @see pbuf_free()
+ */
+void
+etharp_ip_input(struct netif *netif, struct pbuf *p)
+{
+  struct eth_hdr *ethhdr;
+  struct ip_hdr *iphdr;
+  LWIP_ERROR("netif != NULL", (netif != NULL), return;);
+  /* Only insert an entry if the source IP address of the
+     incoming IP packet comes from a host on the local network. */
+  ethhdr = p->payload;
+  iphdr = (struct ip_hdr *)((u8_t*)ethhdr + SIZEOF_ETH_HDR);
+#if ETHARP_SUPPORT_VLAN
+  if (ethhdr->type == ETHTYPE_VLAN) {
+    iphdr = (struct ip_hdr *)((u8_t*)ethhdr + SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR);
+  }
+#endif /* ETHARP_SUPPORT_VLAN */
+
+  /* source is not on the local network? */
+  if (!ip_addr_netcmp(&(iphdr->src), &(netif->ip_addr), &(netif->netmask))) {
+    /* do nothing */
+    return;
+  }
+
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_ip_input: updating ETHARP table.\n"));
+  /* update ARP table */
+  /* @todo We could use ETHARP_TRY_HARD if we think we are going to talk
+   * back soon (for example, if the destination IP address is ours. */
+  update_arp_entry(netif, &(iphdr->src), &(ethhdr->src), 0);
+}
+
+
+/**
+ * Responds to ARP requests to us. Upon ARP replies to us, add entry to cache  
+ * send out queued IP packets. Updates cache with snooped address pairs.
+ *
+ * Should be called for incoming ARP packets. The pbuf in the argument
+ * is freed by this function.
+ *
+ * @param netif The lwIP network interface on which the ARP packet pbuf arrived.
+ * @param ethaddr Ethernet address of netif.
+ * @param p The ARP packet that arrived on netif. Is freed by this function.
+ *
+ * @return NULL
+ *
+ * @see pbuf_free()
+ */
+void
+etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, struct pbuf *p)
+{
+  struct etharp_hdr *hdr;
+  struct eth_hdr *ethhdr;
+  /* these are aligned properly, whereas the ARP header fields might not be */
+  struct ip_addr sipaddr, dipaddr;
+  u8_t i;
+  u8_t for_us;
+#if LWIP_AUTOIP
+  const u8_t * ethdst_hwaddr;
+#endif /* LWIP_AUTOIP */
+
+  LWIP_ERROR("netif != NULL", (netif != NULL), return;);
+  
+  /* drop short ARP packets: we have to check for p->len instead of p->tot_len here
+     since a struct etharp_hdr is pointed to p->payload, so it musn't be chained! */
+  if (p->len < SIZEOF_ETHARP_PACKET) {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
+      ("etharp_arp_input: packet dropped, too short (%"S16_F"/%"S16_F")\n", p->tot_len,
+      (s16_t)SIZEOF_ETHARP_PACKET));
+    ETHARP_STATS_INC(etharp.lenerr);
+    ETHARP_STATS_INC(etharp.drop);
+    pbuf_free(p);
+    return;
+  }
+
+  ethhdr = p->payload;
+  hdr = (struct etharp_hdr *)((u8_t*)ethhdr + SIZEOF_ETH_HDR);
+#if ETHARP_SUPPORT_VLAN
+  if (ethhdr->type == ETHTYPE_VLAN) {
+    hdr = (struct etharp_hdr *)(((u8_t*)ethhdr) + SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR);
+  }
+#endif /* ETHARP_SUPPORT_VLAN */
+
+  /* RFC 826 "Packet Reception": */
+  if ((hdr->hwtype != htons(HWTYPE_ETHERNET)) ||
+      (hdr->_hwlen_protolen != htons((ETHARP_HWADDR_LEN << 8) | sizeof(struct ip_addr))) ||
+      (hdr->proto != htons(ETHTYPE_IP)) ||
+      (ethhdr->type != htons(ETHTYPE_ARP)))  {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
+      ("etharp_arp_input: packet dropped, wrong hw type, hwlen, proto, protolen or ethernet type (%"U16_F"/%"U16_F"/%"U16_F"/%"U16_F"/%"U16_F")\n",
+      hdr->hwtype, ARPH_HWLEN(hdr), hdr->proto, ARPH_PROTOLEN(hdr), ethhdr->type));
+    ETHARP_STATS_INC(etharp.proterr);
+    ETHARP_STATS_INC(etharp.drop);
+    pbuf_free(p);
+    return;
+  }
+  ETHARP_STATS_INC(etharp.recv);
+
+#if LWIP_AUTOIP
+  /* We have to check if a host already has configured our random
+   * created link local address and continously check if there is
+   * a host with this IP-address so we can detect collisions */
+  autoip_arp_reply(netif, hdr);
+#endif /* LWIP_AUTOIP */
+
+  /* Copy struct ip_addr2 to aligned ip_addr, to support compilers without
+   * structure packing (not using structure copy which breaks strict-aliasing rules). */
+  SMEMCPY(&sipaddr, &hdr->sipaddr, sizeof(sipaddr));
+  SMEMCPY(&dipaddr, &hdr->dipaddr, sizeof(dipaddr));
+
+  /* this interface is not configured? */
+  if (netif->ip_addr.addr == 0) {
+    for_us = 0;
+  } else {
+    /* ARP packet directed to us? */
+    for_us = ip_addr_cmp(&dipaddr, &(netif->ip_addr));
+  }
+
+  /* ARP message directed to us? */
+  if (for_us) {
+    /* add IP address in ARP cache; assume requester wants to talk to us.
+     * can result in directly sending the queued packets for this host. */
+    update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), ETHARP_TRY_HARD);
+  /* ARP message not directed to us? */
+  } else {
+    /* update the source IP address in the cache, if present */
+    update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), 0);
+  }
+
+  /* now act on the message itself */
+  switch (htons(hdr->opcode)) {
+  /* ARP request? */
+  case ARP_REQUEST:
+    /* ARP request. If it asked for our address, we send out a
+     * reply. In any case, we time-stamp any existing ARP entry,
+     * and possiby send out an IP packet that was queued on it. */
+
+    LWIP_DEBUGF (ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: incoming ARP request\n"));
+    /* ARP request for our address? */
+    if (for_us) {
+
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: replying to ARP request for our IP address\n"));
+      /* Re-use pbuf to send ARP reply.
+         Since we are re-using an existing pbuf, we can't call etharp_raw since
+         that would allocate a new pbuf. */
+      hdr->opcode = htons(ARP_REPLY);
+
+      hdr->dipaddr = hdr->sipaddr;
+      SMEMCPY(&hdr->sipaddr, &netif->ip_addr, sizeof(hdr->sipaddr));
+
+      LWIP_ASSERT("netif->hwaddr_len must be the same as ETHARP_HWADDR_LEN for etharp!",
+                  (netif->hwaddr_len == ETHARP_HWADDR_LEN));
+      i = ETHARP_HWADDR_LEN;
+#if LWIP_AUTOIP
+      /* If we are using Link-Local, ARP packets must be broadcast on the
+       * link layer. (See RFC3927 Section 2.5) */
+      ethdst_hwaddr = ((netif->autoip != NULL) && (netif->autoip->state != AUTOIP_STATE_OFF)) ? (u8_t*)(ethbroadcast.addr) : hdr->shwaddr.addr;
+#endif /* LWIP_AUTOIP */
+
+      while(i > 0) {
+        i--;
+        hdr->dhwaddr.addr[i] = hdr->shwaddr.addr[i];
+#if LWIP_AUTOIP
+        ethhdr->dest.addr[i] = ethdst_hwaddr[i];
+#else  /* LWIP_AUTOIP */
+        ethhdr->dest.addr[i] = hdr->shwaddr.addr[i];
+#endif /* LWIP_AUTOIP */
+        hdr->shwaddr.addr[i] = ethaddr->addr[i];
+        ethhdr->src.addr[i] = ethaddr->addr[i];
+      }
+
+      /* hwtype, hwaddr_len, proto, protolen and the type in the ethernet header
+         are already correct, we tested that before */
+
+      /* return ARP reply */
+      netif->linkoutput(netif, p);
+    /* we are not configured? */
+    } else if (netif->ip_addr.addr == 0) {
+      /* { for_us == 0 and netif->ip_addr.addr == 0 } */
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: we are unconfigured, ARP request ignored.\n"));
+    /* request was not directed to us */
+    } else {
+      /* { for_us == 0 and netif->ip_addr.addr != 0 } */
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: ARP request was not for us.\n"));
+    }
+    break;
+  case ARP_REPLY:
+    /* ARP reply. We already updated the ARP cache earlier. */
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: incoming ARP reply\n"));
+#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK)
+    /* DHCP wants to know about ARP replies from any host with an
+     * IP address also offered to us by the DHCP server. We do not
+     * want to take a duplicate IP address on a single network.
+     * @todo How should we handle redundant (fail-over) interfaces? */
+    dhcp_arp_reply(netif, &sipaddr);
+#endif
+    break;
+  default:
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: ARP unknown opcode type %"S16_F"\n", htons(hdr->opcode)));
+    ETHARP_STATS_INC(etharp.err);
+    break;
+  }
+  /* free ARP packet */
+  pbuf_free(p);
+}
+
+/**
+ * Resolve and fill-in Ethernet address header for outgoing IP packet.
+ *
+ * For IP multicast and broadcast, corresponding Ethernet addresses
+ * are selected and the packet is transmitted on the link.
+ *
+ * For unicast addresses, the packet is submitted to etharp_query(). In
+ * case the IP address is outside the local network, the IP address of
+ * the gateway is used.
+ *
+ * @param netif The lwIP network interface which the IP packet will be sent on.
+ * @param q The pbuf(s) containing the IP packet to be sent.
+ * @param ipaddr The IP address of the packet destination.
+ *
+ * @return
+ * - ERR_RTE No route to destination (no gateway to external networks),
+ * or the return type of either etharp_query() or etharp_send_ip().
+ */
+err_t
+etharp_output(struct netif *netif, struct pbuf *q, struct ip_addr *ipaddr)
+{
+  struct eth_addr *dest, mcastaddr;
+
+  /* make room for Ethernet header - should not fail */
+  if (pbuf_header(q, sizeof(struct eth_hdr)) != 0) {
+    /* bail out */
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
+      ("etharp_output: could not allocate room for header.\n"));
+    LINK_STATS_INC(link.lenerr);
+    return ERR_BUF;
+  }
+
+  /* assume unresolved Ethernet address */
+  dest = NULL;
+  /* Determine on destination hardware address. Broadcasts and multicasts
+   * are special, other IP addresses are looked up in the ARP table. */
+
+  /* broadcast destination IP address? */
+  if (ip_addr_isbroadcast(ipaddr, netif)) {
+    /* broadcast on Ethernet also */
+    dest = (struct eth_addr *)ðbroadcast;
+  /* multicast destination IP address? */
+  } else if (ip_addr_ismulticast(ipaddr)) {
+    /* Hash IP multicast address to MAC address.*/
+    mcastaddr.addr[0] = 0x01;
+    mcastaddr.addr[1] = 0x00;
+    mcastaddr.addr[2] = 0x5e;
+    mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f;
+    mcastaddr.addr[4] = ip4_addr3(ipaddr);
+    mcastaddr.addr[5] = ip4_addr4(ipaddr);
+    /* destination Ethernet address is multicast */
+    dest = &mcastaddr;
+  /* unicast destination IP address? */
+  } else {
+    /* outside local network? */
+    if (!ip_addr_netcmp(ipaddr, &(netif->ip_addr), &(netif->netmask))) {
+      /* interface has default gateway? */
+      if (netif->gw.addr != 0) {
+        /* send to hardware address of default gateway IP address */
+        ipaddr = &(netif->gw);
+      /* no default gateway available */
+      } else {
+        /* no route to destination error (default gateway missing) */
+        return ERR_RTE;
+      }
+    }
+    /* queue on destination Ethernet address belonging to ipaddr */
+    return etharp_query(netif, ipaddr, q);
+  }
+
+  /* continuation for multicast/broadcast destinations */
+  /* obtain source Ethernet address of the given interface */
+  /* send packet directly on the link */
+  return etharp_send_ip(netif, q, (struct eth_addr*)(netif->hwaddr), dest);
+}
+
+/**
+ * Send an ARP request for the given IP address and/or queue a packet.
+ *
+ * If the IP address was not yet in the cache, a pending ARP cache entry
+ * is added and an ARP request is sent for the given address. The packet
+ * is queued on this entry.
+ *
+ * If the IP address was already pending in the cache, a new ARP request
+ * is sent for the given address. The packet is queued on this entry.
+ *
+ * If the IP address was already stable in the cache, and a packet is
+ * given, it is directly sent and no ARP request is sent out. 
+ * 
+ * If the IP address was already stable in the cache, and no packet is
+ * given, an ARP request is sent out.
+ * 
+ * @param netif The lwIP network interface on which ipaddr
+ * must be queried for.
+ * @param ipaddr The IP address to be resolved.
+ * @param q If non-NULL, a pbuf that must be delivered to the IP address.
+ * q is not freed by this function.
+ *
+ * @note q must only be ONE packet, not a packet queue!
+ *
+ * @return
+ * - ERR_BUF Could not make room for Ethernet header.
+ * - ERR_MEM Hardware address unknown, and no more ARP entries available
+ *   to query for address or queue the packet.
+ * - ERR_MEM Could not queue packet due to memory shortage.
+ * - ERR_RTE No route to destination (no gateway to external networks).
+ * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
+ *
+ */
+err_t
+etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q)
+{
+  struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr;
+  err_t result = ERR_MEM;
+  s8_t i; /* ARP entry index */
+
+  /* non-unicast address? */
+  if (ip_addr_isbroadcast(ipaddr, netif) ||
+      ip_addr_ismulticast(ipaddr) ||
+      ip_addr_isany(ipaddr)) {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n"));
+    return ERR_ARG;
+  }
+
+  /* find entry in ARP cache, ask to create entry if queueing packet */
+#if LWIP_NETIF_HWADDRHINT
+  i = find_entry(ipaddr, ETHARP_TRY_HARD, netif);
+#else /* LWIP_NETIF_HWADDRHINT */
+  i = find_entry(ipaddr, ETHARP_TRY_HARD);
+#endif /* LWIP_NETIF_HWADDRHINT */
+
+  /* could not find or create entry? */
+  if (i < 0) {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not create ARP entry\n"));
+    if (q) {
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: packet dropped\n"));
+      ETHARP_STATS_INC(etharp.memerr);
+    }
+    return (err_t)i;
+  }
+
+  /* mark a fresh entry as pending (we just sent a request) */
+  if (arp_table[i].state == ETHARP_STATE_EMPTY) {
+    arp_table[i].state = ETHARP_STATE_PENDING;
+  }
+
+  /* { i is either a STABLE or (new or existing) PENDING entry } */
+  LWIP_ASSERT("arp_table[i].state == PENDING or STABLE",
+  ((arp_table[i].state == ETHARP_STATE_PENDING) ||
+   (arp_table[i].state == ETHARP_STATE_STABLE)));
+
+  /* do we have a pending entry? or an implicit query request? */
+  if ((arp_table[i].state == ETHARP_STATE_PENDING) || (q == NULL)) {
+    /* try to resolve it; send out ARP request */
+    result = etharp_request(netif, ipaddr);
+    if (result != ERR_OK) {
+      /* ARP request couldn't be sent */
+      /* We don't re-send arp request in etharp_tmr, but we still queue packets,
+         since this failure could be temporary, and the next packet calling
+         etharp_query again could lead to sending the queued packets. */
+    }
+  }
+  
+  /* packet given? */
+  if (q != NULL) {
+    /* stable entry? */
+    if (arp_table[i].state == ETHARP_STATE_STABLE) {
+      /* we have a valid IP->Ethernet address mapping */
+      /* send the packet */
+      result = etharp_send_ip(netif, q, srcaddr, &(arp_table[i].ethaddr));
+    /* pending entry? (either just created or already pending */
+    } else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+#if ARP_QUEUEING /* queue the given q packet */
+      struct pbuf *p;
+      int copy_needed = 0;
+      /* IF q includes a PBUF_REF, PBUF_POOL or PBUF_RAM, we have no choice but
+       * to copy the whole queue into a new PBUF_RAM (see bug #11400) 
+       * PBUF_ROMs can be left as they are, since ROM must not get changed. */
+      p = q;
+      while (p) {
+        LWIP_ASSERT("no packet queues allowed!", (p->len != p->tot_len) || (p->next == 0));
+        if(p->type != PBUF_ROM) {
+          copy_needed = 1;
+          break;
+        }
+        p = p->next;
+      }
+      if(copy_needed) {
+        /* copy the whole packet into new pbufs */
+        p = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
+        if(p != NULL) {
+          if (pbuf_copy(p, q) != ERR_OK) {
+            pbuf_free(p);
+            p = NULL;
+          }
+        }
+      } else {
+        /* referencing the old pbuf is enough */
+        p = q;
+        pbuf_ref(p);
+      }
+      /* packet could be taken over? */
+      if (p != NULL) {
+        /* queue packet ... */
+        struct etharp_q_entry *new_entry;
+        /* allocate a new arp queue entry */
+        new_entry = memp_malloc(MEMP_ARP_QUEUE);
+        if (new_entry != NULL) {
+          new_entry->next = 0;
+          new_entry->p = p;
+          if(arp_table[i].q != NULL) {
+            /* queue was already existent, append the new entry to the end */
+            struct etharp_q_entry *r;
+            r = arp_table[i].q;
+            while (r->next != NULL) {
+              r = r->next;
+            }
+            r->next = new_entry;
+          } else {
+            /* queue did not exist, first item in queue */
+            arp_table[i].q = new_entry;
+          }
+          LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"S16_F"\n", (void *)q, (s16_t)i));
+          result = ERR_OK;
+        } else {
+          /* the pool MEMP_ARP_QUEUE is empty */
+          pbuf_free(p);
+          LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
+          /* { result == ERR_MEM } through initialization */
+        }
+      } else {
+        ETHARP_STATS_INC(etharp.memerr);
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
+        /* { result == ERR_MEM } through initialization */
+      }
+#else /* ARP_QUEUEING == 0 */
+      /* q && state == PENDING && ARP_QUEUEING == 0 => result = ERR_MEM */
+      /* { result == ERR_MEM } through initialization */
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: Ethernet destination address unknown, queueing disabled, packet %p dropped\n", (void *)q));
+#endif
+    }
+  }
+  return result;
+}
+
+/**
+ * Send a raw ARP packet (opcode and all addresses can be modified)
+ *
+ * @param netif the lwip network interface on which to send the ARP packet
+ * @param ethsrc_addr the source MAC address for the ethernet header
+ * @param ethdst_addr the destination MAC address for the ethernet header
+ * @param hwsrc_addr the source MAC address for the ARP protocol header
+ * @param ipsrc_addr the source IP address for the ARP protocol header
+ * @param hwdst_addr the destination MAC address for the ARP protocol header
+ * @param ipdst_addr the destination IP address for the ARP protocol header
+ * @param opcode the type of the ARP packet
+ * @return ERR_OK if the ARP packet has been sent
+ *         ERR_MEM if the ARP packet couldn't be allocated
+ *         any other err_t on failure
+ */
+#if !LWIP_AUTOIP
+static
+#endif /* LWIP_AUTOIP */
+err_t
+etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr,
+           const struct eth_addr *ethdst_addr,
+           const struct eth_addr *hwsrc_addr, const struct ip_addr *ipsrc_addr,
+           const struct eth_addr *hwdst_addr, const struct ip_addr *ipdst_addr,
+           const u16_t opcode)
+{
+  struct pbuf *p;
+  err_t result = ERR_OK;
+  u8_t k; /* ARP entry index */
+  struct eth_hdr *ethhdr;
+  struct etharp_hdr *hdr;
+#if LWIP_AUTOIP
+  const u8_t * ethdst_hwaddr;
+#endif /* LWIP_AUTOIP */
+
+  /* allocate a pbuf for the outgoing ARP request packet */
+  p = pbuf_alloc(PBUF_RAW, SIZEOF_ETHARP_PACKET, PBUF_RAM);
+  /* could allocate a pbuf for an ARP request? */
+  if (p == NULL) {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
+      ("etharp_raw: could not allocate pbuf for ARP request.\n"));
+    ETHARP_STATS_INC(etharp.memerr);
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("check that first pbuf can hold struct etharp_hdr",
+              (p->len >= SIZEOF_ETHARP_PACKET));
+
+  ethhdr = p->payload;
+  hdr = (struct etharp_hdr *)((u8_t*)ethhdr + SIZEOF_ETH_HDR);
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_raw: sending raw ARP packet.\n"));
+  hdr->opcode = htons(opcode);
+
+  LWIP_ASSERT("netif->hwaddr_len must be the same as ETHARP_HWADDR_LEN for etharp!",
+              (netif->hwaddr_len == ETHARP_HWADDR_LEN));
+  k = ETHARP_HWADDR_LEN;
+#if LWIP_AUTOIP
+  /* If we are using Link-Local, ARP packets must be broadcast on the
+   * link layer. (See RFC3927 Section 2.5) */
+  ethdst_hwaddr = ((netif->autoip != NULL) && (netif->autoip->state != AUTOIP_STATE_OFF)) ? (u8_t*)(ethbroadcast.addr) : ethdst_addr->addr;
+#endif /* LWIP_AUTOIP */
+  /* Write MAC-Addresses (combined loop for both headers) */
+  while(k > 0) {
+    k--;
+    /* Write the ARP MAC-Addresses */
+    hdr->shwaddr.addr[k] = hwsrc_addr->addr[k];
+    hdr->dhwaddr.addr[k] = hwdst_addr->addr[k];
+    /* Write the Ethernet MAC-Addresses */
+#if LWIP_AUTOIP
+    ethhdr->dest.addr[k] = ethdst_hwaddr[k];
+#else  /* LWIP_AUTOIP */
+    ethhdr->dest.addr[k] = ethdst_addr->addr[k];
+#endif /* LWIP_AUTOIP */
+    ethhdr->src.addr[k]  = ethsrc_addr->addr[k];
+  }
+  hdr->sipaddr = *(struct ip_addr2 *)ipsrc_addr;
+  hdr->dipaddr = *(struct ip_addr2 *)ipdst_addr;
+
+  hdr->hwtype = htons(HWTYPE_ETHERNET);
+  hdr->proto = htons(ETHTYPE_IP);
+  /* set hwlen and protolen together */
+  hdr->_hwlen_protolen = htons((ETHARP_HWADDR_LEN << 8) | sizeof(struct ip_addr));
+
+  ethhdr->type = htons(ETHTYPE_ARP);
+  /* send ARP query */
+  result = netif->linkoutput(netif, p);
+  ETHARP_STATS_INC(etharp.xmit);
+  /* free ARP query packet */
+  pbuf_free(p);
+  p = NULL;
+  /* could not allocate pbuf for ARP request */
+
+  return result;
+}
+
+/**
+ * Send an ARP request packet asking for ipaddr.
+ *
+ * @param netif the lwip network interface on which to send the request
+ * @param ipaddr the IP address for which to ask
+ * @return ERR_OK if the request has been sent
+ *         ERR_MEM if the ARP packet couldn't be allocated
+ *         any other err_t on failure
+ */
+err_t
+etharp_request(struct netif *netif, struct ip_addr *ipaddr)
+{
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_request: sending ARP request.\n"));
+  return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, ðbroadcast,
+                    (struct eth_addr *)netif->hwaddr, &netif->ip_addr, ðzero,
+                    ipaddr, ARP_REQUEST);
+}
+
+/**
+ * Process received ethernet frames. Using this function instead of directly
+ * calling ip_input and passing ARP frames through etharp in ethernetif_input,
+ * the ARP cache is protected from concurrent access.
+ *
+ * @param p the recevied packet, p->payload pointing to the ethernet header
+ * @param netif the network interface on which the packet was received
+ */
+err_t
+ethernet_input(struct pbuf *p, struct netif *netif)
+{
+  struct eth_hdr* ethhdr;
+  u16_t type;
+
+  /* points to packet payload, which starts with an Ethernet header */
+  ethhdr = p->payload;
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE,
+    ("ethernet_input: dest:%02x:%02x:%02x:%02x:%02x:%02x, src:%02x:%02x:%02x:%02x:%02x:%02x, type:%2hx\n",
+     (unsigned)ethhdr->dest.addr[0], (unsigned)ethhdr->dest.addr[1], (unsigned)ethhdr->dest.addr[2],
+     (unsigned)ethhdr->dest.addr[3], (unsigned)ethhdr->dest.addr[4], (unsigned)ethhdr->dest.addr[5],
+     (unsigned)ethhdr->src.addr[0], (unsigned)ethhdr->src.addr[1], (unsigned)ethhdr->src.addr[2],
+     (unsigned)ethhdr->src.addr[3], (unsigned)ethhdr->src.addr[4], (unsigned)ethhdr->src.addr[5],
+     (unsigned)htons(ethhdr->type)));
+
+  type = htons(ethhdr->type);
+#if ETHARP_SUPPORT_VLAN
+  if (type == ETHTYPE_VLAN) {
+    struct eth_vlan_hdr *vlan = (struct eth_vlan_hdr*)(((char*)ethhdr) + SIZEOF_ETH_HDR);
+#ifdef ETHARP_VLAN_CHECK /* if not, allow all VLANs */
+    if (VLAN_ID(vlan) != ETHARP_VLAN_CHECK) {
+      /* silently ignore this packet: not for our VLAN */
+      pbuf_free(p);
+      return ERR_OK;
+    }
+#endif /* ETHARP_VLAN_CHECK */
+    type = htons(vlan->tpid);
+  }
+#endif /* ETHARP_SUPPORT_VLAN */
+
+  switch (type) {
+    /* IP packet? */
+    case ETHTYPE_IP:
+#if ETHARP_TRUST_IP_MAC
+      /* update ARP table */
+      etharp_ip_input(netif, p);
+#endif /* ETHARP_TRUST_IP_MAC */
+      /* skip Ethernet header */
+      if(pbuf_header(p, -(s16_t)SIZEOF_ETH_HDR)) {
+        LWIP_ASSERT("Can't move over header in packet", 0);
+        pbuf_free(p);
+        p = NULL;
+      } else {
+        /* pass to IP layer */
+        ip_input(p, netif);
+      }
+      break;
+      
+    case ETHTYPE_ARP:
+      /* pass p to ARP module */
+      etharp_arp_input(netif, (struct eth_addr*)(netif->hwaddr), p);
+      break;
+
+#if PPPOE_SUPPORT
+    case ETHTYPE_PPPOEDISC: /* PPP Over Ethernet Discovery Stage */
+      pppoe_disc_input(netif, p);
+      break;
+
+    case ETHTYPE_PPPOE: /* PPP Over Ethernet Session Stage */
+      pppoe_data_input(netif, p);
+      break;
+#endif /* PPPOE_SUPPORT */
+
+    default:
+      ETHARP_STATS_INC(etharp.proterr);
+      ETHARP_STATS_INC(etharp.drop);
+      pbuf_free(p);
+      p = NULL;
+      break;
+  }
+
+  /* This means the pbuf is freed or consumed,
+     so the caller doesn't have to free it again */
+  return ERR_OK;
+}
+#endif /* LWIP_ARP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ethernetif.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ethernetif.c
new file mode 100644
index 0000000..a5b7d99
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ethernetif.c
@@ -0,0 +1,318 @@
+/**
+ * @file
+ * Ethernet Interface Skeleton
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+/*
+ * This file is a skeleton for developing Ethernet network interface
+ * drivers for lwIP. Add code to the low_level functions and do a
+ * search-and-replace for the word "ethernetif" to replace it with
+ * something that better describes your network interface.
+ */
+
+#include "lwip/opt.h"
+
+#if 0 /* don't build, this is only a skeleton, see previous comment */
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include 
+#include 
+#include "netif/etharp.h"
+#include "netif/ppp_oe.h"
+
+/* Define those to better describe your network interface. */
+#define IFNAME0 'e'
+#define IFNAME1 'n'
+
+/**
+ * Helper struct to hold private data used to operate your ethernet interface.
+ * Keeping the ethernet address of the MAC in this struct is not necessary
+ * as it is already kept in the struct netif.
+ * But this is only an example, anyway...
+ */
+struct ethernetif {
+  struct eth_addr *ethaddr;
+  /* Add whatever per-interface state that is needed here. */
+};
+
+/* Forward declarations. */
+static void  ethernetif_input(struct netif *netif);
+
+/**
+ * In this function, the hardware should be initialized.
+ * Called from ethernetif_init().
+ *
+ * @param netif the already initialized lwip network interface structure
+ *        for this ethernetif
+ */
+static void
+low_level_init(struct netif *netif)
+{
+  struct ethernetif *ethernetif = netif->state;
+  
+  /* set MAC hardware address length */
+  netif->hwaddr_len = ETHARP_HWADDR_LEN;
+
+  /* set MAC hardware address */
+  netif->hwaddr[0] = ;
+  ...
+  netif->hwaddr[5] = ;
+
+  /* maximum transfer unit */
+  netif->mtu = 1500;
+  
+  /* device capabilities */
+  /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
+  netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
+ 
+  /* Do whatever else is needed to initialize interface. */  
+}
+
+/**
+ * This function should do the actual transmission of the packet. The packet is
+ * contained in the pbuf that is passed to the function. This pbuf
+ * might be chained.
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)
+ * @return ERR_OK if the packet could be sent
+ *         an err_t value if the packet couldn't be sent
+ *
+ * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to
+ *       strange results. You might consider waiting for space in the DMA queue
+ *       to become availale since the stack doesn't retry to send a packet
+ *       dropped because of memory failure (except for the TCP timers).
+ */
+
+static err_t
+low_level_output(struct netif *netif, struct pbuf *p)
+{
+  struct ethernetif *ethernetif = netif->state;
+  struct pbuf *q;
+
+  initiate transfer();
+  
+#if ETH_PAD_SIZE
+  pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
+#endif
+
+  for(q = p; q != NULL; q = q->next) {
+    /* Send the data from the pbuf to the interface, one pbuf at a
+       time. The size of the data in each pbuf is kept in the ->len
+       variable. */
+    send data from(q->payload, q->len);
+  }
+
+  signal that packet should be sent();
+
+#if ETH_PAD_SIZE
+  pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
+#endif
+  
+  LINK_STATS_INC(link.xmit);
+
+  return ERR_OK;
+}
+
+/**
+ * Should allocate a pbuf and transfer the bytes of the incoming
+ * packet from the interface into the pbuf.
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ * @return a pbuf filled with the received packet (including MAC header)
+ *         NULL on memory error
+ */
+static struct pbuf *
+low_level_input(struct netif *netif)
+{
+  struct ethernetif *ethernetif = netif->state;
+  struct pbuf *p, *q;
+  u16_t len;
+
+  /* Obtain the size of the packet and put it into the "len"
+     variable. */
+  len = ;
+
+#if ETH_PAD_SIZE
+  len += ETH_PAD_SIZE; /* allow room for Ethernet padding */
+#endif
+
+  /* We allocate a pbuf chain of pbufs from the pool. */
+  p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
+  
+  if (p != NULL) {
+
+#if ETH_PAD_SIZE
+    pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
+#endif
+
+    /* We iterate over the pbuf chain until we have read the entire
+     * packet into the pbuf. */
+    for(q = p; q != NULL; q = q->next) {
+      /* Read enough bytes to fill this pbuf in the chain. The
+       * available data in the pbuf is given by the q->len
+       * variable.
+       * This does not necessarily have to be a memcpy, you can also preallocate
+       * pbufs for a DMA-enabled MAC and after receiving truncate it to the
+       * actually received size. In this case, ensure the tot_len member of the
+       * pbuf is the sum of the chained pbuf len members.
+       */
+      read data into(q->payload, q->len);
+    }
+    acknowledge that packet has been read();
+
+#if ETH_PAD_SIZE
+    pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
+#endif
+
+    LINK_STATS_INC(link.recv);
+  } else {
+    drop packet();
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.drop);
+  }
+
+  return p;  
+}
+
+/**
+ * This function should be called when a packet is ready to be read
+ * from the interface. It uses the function low_level_input() that
+ * should handle the actual reception of bytes from the network
+ * interface. Then the type of the received packet is determined and
+ * the appropriate input function is called.
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ */
+static void
+ethernetif_input(struct netif *netif)
+{
+  struct ethernetif *ethernetif;
+  struct eth_hdr *ethhdr;
+  struct pbuf *p;
+
+  ethernetif = netif->state;
+
+  /* move received packet into a new pbuf */
+  p = low_level_input(netif);
+  /* no packet could be read, silently ignore this */
+  if (p == NULL) return;
+  /* points to packet payload, which starts with an Ethernet header */
+  ethhdr = p->payload;
+
+  switch (htons(ethhdr->type)) {
+  /* IP or ARP packet? */
+  case ETHTYPE_IP:
+  case ETHTYPE_ARP:
+#if PPPOE_SUPPORT
+  /* PPPoE packet? */
+  case ETHTYPE_PPPOEDISC:
+  case ETHTYPE_PPPOE:
+#endif /* PPPOE_SUPPORT */
+    /* full packet send to tcpip_thread to process */
+    if (netif->input(p, netif)!=ERR_OK)
+     { LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n"));
+       pbuf_free(p);
+       p = NULL;
+     }
+    break;
+
+  default:
+    pbuf_free(p);
+    p = NULL;
+    break;
+  }
+}
+
+/**
+ * Should be called at the beginning of the program to set up the
+ * network interface. It calls the function low_level_init() to do the
+ * actual setup of the hardware.
+ *
+ * This function should be passed as a parameter to netif_add().
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ * @return ERR_OK if the loopif is initialized
+ *         ERR_MEM if private data couldn't be allocated
+ *         any other err_t on error
+ */
+err_t
+ethernetif_init(struct netif *netif)
+{
+  struct ethernetif *ethernetif;
+
+  LWIP_ASSERT("netif != NULL", (netif != NULL));
+    
+  ethernetif = mem_malloc(sizeof(struct ethernetif));
+  if (ethernetif == NULL) {
+    LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n"));
+    return ERR_MEM;
+  }
+
+#if LWIP_NETIF_HOSTNAME
+  /* Initialize interface hostname */
+  netif->hostname = "lwip";
+#endif /* LWIP_NETIF_HOSTNAME */
+
+  /*
+   * Initialize the snmp variables and counters inside the struct netif.
+   * The last argument should be replaced with your link speed, in units
+   * of bits per second.
+   */
+  NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, LINK_SPEED_OF_YOUR_NETIF_IN_BPS);
+
+  netif->state = ethernetif;
+  netif->name[0] = IFNAME0;
+  netif->name[1] = IFNAME1;
+  /* We directly use etharp_output() here to save a function call.
+   * You can instead declare your own function an call etharp_output()
+   * from it if you have to do some checks before sending (e.g. if link
+   * is available...) */
+  netif->output = etharp_output;
+  netif->linkoutput = low_level_output;
+  
+  ethernetif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]);
+  
+  /* initialize the hardware */
+  low_level_init(netif);
+
+  return ERR_OK;
+}
+
+#endif /* 0 */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/loopif.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/loopif.c
new file mode 100644
index 0000000..1e1f28c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/loopif.c
@@ -0,0 +1,66 @@
+/**
+ * @file
+ * Loop Interface
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#include "lwip/opt.h"
+
+#if LWIP_HAVE_LOOPIF
+
+#include "netif/loopif.h"
+#include "lwip/snmp.h"
+
+/**
+ * Initialize a lwip network interface structure for a loopback interface
+ *
+ * @param netif the lwip network interface structure for this loopif
+ * @return ERR_OK if the loopif is initialized
+ *         ERR_MEM if private data couldn't be allocated
+ */
+err_t
+loopif_init(struct netif *netif)
+{
+  /* initialize the snmp variables and counters inside the struct netif
+   * ifSpeed: no assumption can be made!
+   */
+  NETIF_INIT_SNMP(netif, snmp_ifType_softwareLoopback, 0);
+
+  netif->name[0] = 'l';
+  netif->name[1] = 'o';
+  netif->output = netif_loop_output;
+  return ERR_OK;
+}
+
+#endif /* LWIP_HAVE_LOOPIF */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/auth.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/auth.c
new file mode 100644
index 0000000..cbd3eb2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/auth.c
@@ -0,0 +1,990 @@
+/*****************************************************************************
+* auth.c - Network Authentication and Phase Control program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 by Global Election Systems Inc.  All rights reserved.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-08 Guy Lancaster , Global Election Systems Inc.
+*   Ported from public pppd code.
+*****************************************************************************/
+/*
+ * auth.c - PPP authentication and phase control.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University.  The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "fsm.h"
+#include "lcp.h"
+#include "pap.h"
+#include "chap.h"
+#include "auth.h"
+#include "ipcp.h"
+
+#if CBCP_SUPPORT
+#include "cbcp.h"
+#endif /* CBCP_SUPPORT */
+
+#include 
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+/* Bits in auth_pending[] */
+#define PAP_WITHPEER    1
+#define PAP_PEER        2
+#define CHAP_WITHPEER   4
+#define CHAP_PEER       8
+
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+/* Used for storing a sequence of words.  Usually malloced. */
+struct wordlist {
+  struct wordlist *next;
+  char        word[1];
+};
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+extern char *crypt (const char *, const char *);
+
+/* Prototypes for procedures local to this file. */
+
+static void network_phase (int);
+static void check_idle (void *);
+static void connect_time_expired (void *);
+#if 0
+static int  login (char *, char *, char **, int *);
+#endif
+static void logout (void);
+static int  null_login (int);
+static int  get_pap_passwd (int, char *, char *);
+static int  have_pap_secret (void);
+static int  have_chap_secret (char *, char *, u32_t);
+static int  ip_addr_check (u32_t, struct wordlist *);
+#if 0 /* PAP_SUPPORT || CHAP_SUPPORT */
+static void set_allowed_addrs(int unit, struct wordlist *addrs);
+static void free_wordlist (struct wordlist *);
+#endif /* 0 */ /* PAP_SUPPORT || CHAP_SUPPORT */
+#if CBCP_SUPPORT
+static void callback_phase (int);
+#endif /* CBCP_SUPPORT */
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+#if PAP_SUPPORT || CHAP_SUPPORT
+/* The name by which the peer authenticated itself to us. */
+static char peer_authname[MAXNAMELEN];
+#endif /* PAP_SUPPORT || CHAP_SUPPORT */
+
+/* Records which authentication operations haven't completed yet. */
+static int auth_pending[NUM_PPP];
+
+/* Set if we have successfully called login() */
+static int logged_in;
+
+/* Set if we have run the /etc/ppp/auth-up script. */
+static int did_authup;
+
+/* List of addresses which the peer may use. */
+static struct wordlist *addresses[NUM_PPP];
+
+/* Number of network protocols which we have opened. */
+static int num_np_open;
+
+/* Number of network protocols which have come up. */
+static int num_np_up;
+
+#if PAP_SUPPORT || CHAP_SUPPORT
+/* Set if we got the contents of passwd[] from the pap-secrets file. */
+static int passwd_from_file;
+#endif /* PAP_SUPPORT || CHAP_SUPPORT */
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * An Open on LCP has requested a change from Dead to Establish phase.
+ * Do what's necessary to bring the physical layer up.
+ */
+void
+link_required(int unit)
+{
+  LWIP_UNUSED_ARG(unit);
+
+  AUTHDEBUG((LOG_INFO, "link_required: %d\n", unit));
+}
+
+/*
+ * LCP has terminated the link; go to the Dead phase and take the
+ * physical layer down.
+ */
+void
+link_terminated(int unit)
+{
+  AUTHDEBUG((LOG_INFO, "link_terminated: %d\n", unit));
+  if (lcp_phase[unit] == PHASE_DEAD) {
+    return;
+  }
+  if (logged_in) {
+    logout();
+  }
+  lcp_phase[unit] = PHASE_DEAD;
+  AUTHDEBUG((LOG_NOTICE, "Connection terminated.\n"));
+  pppLinkTerminated(unit);
+}
+
+/*
+ * LCP has gone down; it will either die or try to re-establish.
+ */
+void
+link_down(int unit)
+{
+  int i;
+  struct protent *protp;
+  
+  AUTHDEBUG((LOG_INFO, "link_down: %d\n", unit));
+  if (did_authup) {
+    /* XXX Do link down processing. */
+    did_authup = 0;
+  }
+  for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+    if (!protp->enabled_flag) {
+      continue;
+    }
+    if (protp->protocol != PPP_LCP && protp->lowerdown != NULL) {
+      (*protp->lowerdown)(unit);
+    }
+    if (protp->protocol < 0xC000 && protp->close != NULL) {
+      (*protp->close)(unit, "LCP down");
+    }
+  }
+  num_np_open = 0;
+  num_np_up = 0;
+  if (lcp_phase[unit] != PHASE_DEAD) {
+    lcp_phase[unit] = PHASE_TERMINATE;
+  }
+  pppLinkDown(unit);
+}
+
+/*
+ * The link is established.
+ * Proceed to the Dead, Authenticate or Network phase as appropriate.
+ */
+void
+link_established(int unit)
+{
+  int auth;
+  int i;
+  struct protent *protp;
+  lcp_options *wo = &lcp_wantoptions[unit];
+  lcp_options *go = &lcp_gotoptions[unit];
+#if PAP_SUPPORT || CHAP_SUPPORT
+  lcp_options *ho = &lcp_hisoptions[unit];
+#endif /* PAP_SUPPORT || CHAP_SUPPORT */
+
+  AUTHDEBUG((LOG_INFO, "link_established: %d\n", unit));
+  /*
+   * Tell higher-level protocols that LCP is up.
+   */
+  for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+    if (protp->protocol != PPP_LCP && protp->enabled_flag && protp->lowerup != NULL) {
+      (*protp->lowerup)(unit);
+    }
+  }
+  if (ppp_settings.auth_required && !(go->neg_chap || go->neg_upap)) {
+    /*
+     * We wanted the peer to authenticate itself, and it refused:
+     * treat it as though it authenticated with PAP using a username
+     * of "" and a password of "".  If that's not OK, boot it out.
+     */
+    if (!wo->neg_upap || !null_login(unit)) {
+      AUTHDEBUG((LOG_WARNING, "peer refused to authenticate\n"));
+      lcp_close(unit, "peer refused to authenticate");
+      return;
+    }
+  }
+    
+  lcp_phase[unit] = PHASE_AUTHENTICATE;
+  auth = 0;
+#if CHAP_SUPPORT
+  if (go->neg_chap) {
+    ChapAuthPeer(unit, ppp_settings.our_name, go->chap_mdtype);
+    auth |= CHAP_PEER;
+  } 
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT && CHAP_SUPPORT
+  else
+#endif /* PAP_SUPPORT && CHAP_SUPPORT */
+#if PAP_SUPPORT
+  if (go->neg_upap) {
+    upap_authpeer(unit);
+    auth |= PAP_PEER;
+  }
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+  if (ho->neg_chap) {
+    ChapAuthWithPeer(unit, ppp_settings.user, ho->chap_mdtype);
+    auth |= CHAP_WITHPEER;
+  }
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT && CHAP_SUPPORT
+  else
+#endif /* PAP_SUPPORT && CHAP_SUPPORT */
+#if PAP_SUPPORT
+  if (ho->neg_upap) {
+    if (ppp_settings.passwd[0] == 0) {
+      passwd_from_file = 1;
+      if (!get_pap_passwd(unit, ppp_settings.user, ppp_settings.passwd)) {
+        AUTHDEBUG((LOG_ERR, "No secret found for PAP login\n"));
+      }
+    }
+    upap_authwithpeer(unit, ppp_settings.user, ppp_settings.passwd);
+    auth |= PAP_WITHPEER;
+  }
+#endif /* PAP_SUPPORT */
+  auth_pending[unit] = auth;
+
+  if (!auth) {
+    network_phase(unit);
+  }
+}
+
+/*
+ * The peer has failed to authenticate himself using `protocol'.
+ */
+void
+auth_peer_fail(int unit, u16_t protocol)
+{
+  LWIP_UNUSED_ARG(protocol);
+
+  AUTHDEBUG((LOG_INFO, "auth_peer_fail: %d proto=%X\n", unit, protocol));
+  /*
+   * Authentication failure: take the link down
+   */
+  lcp_close(unit, "Authentication failed");
+}
+
+
+#if PAP_SUPPORT || CHAP_SUPPORT
+/*
+ * The peer has been successfully authenticated using `protocol'.
+ */
+void
+auth_peer_success(int unit, u16_t protocol, char *name, int namelen)
+{
+  int pbit;
+  
+  AUTHDEBUG((LOG_INFO, "auth_peer_success: %d proto=%X\n", unit, protocol));
+  switch (protocol) {
+    case PPP_CHAP:
+      pbit = CHAP_PEER;
+      break;
+    case PPP_PAP:
+      pbit = PAP_PEER;
+      break;
+    default:
+      AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n", protocol));
+      return;
+  }
+  
+  /*
+   * Save the authenticated name of the peer for later.
+   */
+  if (namelen > sizeof(peer_authname) - 1) {
+    namelen = sizeof(peer_authname) - 1;
+  }
+  BCOPY(name, peer_authname, namelen);
+  peer_authname[namelen] = 0;
+  
+  /*
+   * If there is no more authentication still to be done,
+   * proceed to the network (or callback) phase.
+   */
+  if ((auth_pending[unit] &= ~pbit) == 0) {
+    network_phase(unit);
+  }
+}
+
+/*
+ * We have failed to authenticate ourselves to the peer using `protocol'.
+ */
+void
+auth_withpeer_fail(int unit, u16_t protocol)
+{
+  int errCode = PPPERR_AUTHFAIL;
+  
+  LWIP_UNUSED_ARG(protocol);
+
+  AUTHDEBUG((LOG_INFO, "auth_withpeer_fail: %d proto=%X\n", unit, protocol));
+  if (passwd_from_file) {
+    BZERO(ppp_settings.passwd, MAXSECRETLEN);
+  }
+  /* 
+   * XXX Warning: the unit number indicates the interface which is
+   * not necessarily the PPP connection.  It works here as long
+   * as we are only supporting PPP interfaces.
+   */
+  pppIOCtl(unit, PPPCTLS_ERRCODE, &errCode);
+
+  /*
+   * We've failed to authenticate ourselves to our peer.
+   * He'll probably take the link down, and there's not much
+   * we can do except wait for that.
+   */
+}
+
+/*
+ * We have successfully authenticated ourselves with the peer using `protocol'.
+ */
+void
+auth_withpeer_success(int unit, u16_t protocol)
+{
+  int pbit;
+  
+  AUTHDEBUG((LOG_INFO, "auth_withpeer_success: %d proto=%X\n", unit, protocol));
+  switch (protocol) {
+    case PPP_CHAP:
+      pbit = CHAP_WITHPEER;
+      break;
+    case PPP_PAP:
+      if (passwd_from_file) {
+        BZERO(ppp_settings.passwd, MAXSECRETLEN);
+      }
+      pbit = PAP_WITHPEER;
+      break;
+    default:
+      AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n", protocol));
+      pbit = 0;
+  }
+  
+  /*
+   * If there is no more authentication still being done,
+   * proceed to the network (or callback) phase.
+   */
+  if ((auth_pending[unit] &= ~pbit) == 0) {
+    network_phase(unit);
+  }
+}
+#endif /* PAP_SUPPORT || CHAP_SUPPORT */
+
+
+/*
+ * np_up - a network protocol has come up.
+ */
+void
+np_up(int unit, u16_t proto)
+{
+  LWIP_UNUSED_ARG(unit);
+  LWIP_UNUSED_ARG(proto);
+
+  AUTHDEBUG((LOG_INFO, "np_up: %d proto=%X\n", unit, proto));
+  if (num_np_up == 0) {
+    AUTHDEBUG((LOG_INFO, "np_up: maxconnect=%d idle_time_limit=%d\n",ppp_settings.maxconnect,ppp_settings.idle_time_limit));
+    /*
+     * At this point we consider that the link has come up successfully.
+     */
+    if (ppp_settings.idle_time_limit > 0) {
+      TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit);
+    }
+    
+    /*
+     * Set a timeout to close the connection once the maximum
+     * connect time has expired.
+     */
+    if (ppp_settings.maxconnect > 0) {
+      TIMEOUT(connect_time_expired, 0, ppp_settings.maxconnect);
+    }
+  }
+  ++num_np_up;
+}
+
+/*
+ * np_down - a network protocol has gone down.
+ */
+void
+np_down(int unit, u16_t proto)
+{
+  LWIP_UNUSED_ARG(unit);
+  LWIP_UNUSED_ARG(proto);
+
+  AUTHDEBUG((LOG_INFO, "np_down: %d proto=%X\n", unit, proto));
+  if (--num_np_up == 0 && ppp_settings.idle_time_limit > 0) {
+    UNTIMEOUT(check_idle, NULL);
+  }
+}
+
+/*
+ * np_finished - a network protocol has finished using the link.
+ */
+void
+np_finished(int unit, u16_t proto)
+{
+  LWIP_UNUSED_ARG(unit);
+  LWIP_UNUSED_ARG(proto);
+
+  AUTHDEBUG((LOG_INFO, "np_finished: %d proto=%X\n", unit, proto));
+  if (--num_np_open <= 0) {
+    /* no further use for the link: shut up shop. */
+    lcp_close(0, "No network protocols running");
+  }
+}
+
+/*
+ * auth_reset - called when LCP is starting negotiations to recheck
+ * authentication options, i.e. whether we have appropriate secrets
+ * to use for authenticating ourselves and/or the peer.
+ */
+void
+auth_reset(int unit)
+{
+  lcp_options *go = &lcp_gotoptions[unit];
+  lcp_options *ao = &lcp_allowoptions[0];
+  ipcp_options *ipwo = &ipcp_wantoptions[0];
+  u32_t remote;
+
+  AUTHDEBUG((LOG_INFO, "auth_reset: %d\n", unit));
+  ao->neg_upap = !ppp_settings.refuse_pap && (ppp_settings.passwd[0] != 0 || get_pap_passwd(unit, NULL, NULL));
+  ao->neg_chap = !ppp_settings.refuse_chap && ppp_settings.passwd[0] != 0 /*have_chap_secret(ppp_settings.user, ppp_settings.remote_name, (u32_t)0)*/;
+
+  if (go->neg_upap && !have_pap_secret()) {
+    go->neg_upap = 0;
+  }
+  if (go->neg_chap) {
+    remote = ipwo->accept_remote? 0: ipwo->hisaddr;
+    if (!have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote)) {
+      go->neg_chap = 0;
+    }
+  }
+}
+
+#if PAP_SUPPORT
+/*
+ * check_passwd - Check the user name and passwd against the PAP secrets
+ * file.  If requested, also check against the system password database,
+ * and login the user if OK.
+ *
+ * returns:
+ *  UPAP_AUTHNAK: Authentication failed.
+ *  UPAP_AUTHACK: Authentication succeeded.
+ * In either case, msg points to an appropriate message.
+ */
+int
+check_passwd( int unit, char *auser, int userlen, char *apasswd, int passwdlen, char **msg, int *msglen)
+{
+#if 1
+  LWIP_UNUSED_ARG(unit);
+  LWIP_UNUSED_ARG(auser);
+  LWIP_UNUSED_ARG(userlen);
+  LWIP_UNUSED_ARG(apasswd);
+  LWIP_UNUSED_ARG(passwdlen);
+  LWIP_UNUSED_ARG(msglen);
+  *msg = (char *) 0;
+  return UPAP_AUTHACK;     /* XXX Assume all entries OK. */
+#else
+  int ret = 0;
+  struct wordlist *addrs = NULL;
+  char passwd[256], user[256];
+  char secret[MAXWORDLEN];
+  static u_short attempts = 0;
+  
+  /*
+   * Make copies of apasswd and auser, then null-terminate them.
+   */
+  BCOPY(apasswd, passwd, passwdlen);
+  passwd[passwdlen] = '\0';
+  BCOPY(auser, user, userlen);
+  user[userlen] = '\0';
+  *msg = (char *) 0;
+
+  /* XXX Validate user name and password. */
+  ret = UPAP_AUTHACK;     /* XXX Assume all entries OK. */
+      
+  if (ret == UPAP_AUTHNAK) {
+    if (*msg == (char *) 0) {
+      *msg = "Login incorrect";
+    }
+    *msglen = strlen(*msg);
+    /*
+     * Frustrate passwd stealer programs.
+     * Allow 10 tries, but start backing off after 3 (stolen from login).
+     * On 10'th, drop the connection.
+     */
+    if (attempts++ >= 10) {
+      AUTHDEBUG((LOG_WARNING, "%d LOGIN FAILURES BY %s\n", attempts, user));
+      /*ppp_panic("Excess Bad Logins");*/
+    }
+    if (attempts > 3) {
+      sys_msleep((attempts - 3) * 5);
+    }
+    if (addrs != NULL) {
+      free_wordlist(addrs);
+    }
+  } else {
+    attempts = 0; /* Reset count */
+    if (*msg == (char *) 0) {
+      *msg = "Login ok";
+    }
+    *msglen = strlen(*msg);
+    set_allowed_addrs(unit, addrs);
+  }
+
+  BZERO(passwd, sizeof(passwd));
+  BZERO(secret, sizeof(secret));
+
+  return ret;
+#endif
+}
+#endif /* PAP_SUPPORT */
+
+
+/*
+ * auth_ip_addr - check whether the peer is authorized to use
+ * a given IP address.  Returns 1 if authorized, 0 otherwise.
+ */
+int
+auth_ip_addr(int unit, u32_t addr)
+{
+  return ip_addr_check(addr, addresses[unit]);
+}
+
+/*
+ * bad_ip_adrs - return 1 if the IP address is one we don't want
+ * to use, such as an address in the loopback net or a multicast address.
+ * addr is in network byte order.
+ */
+int
+bad_ip_adrs(u32_t addr)
+{
+  addr = ntohl(addr);
+  return (addr >> IN_CLASSA_NSHIFT) == IN_LOOPBACKNET
+      || IN_MULTICAST(addr) || IN_BADCLASS(addr);
+}
+
+
+#if CHAP_SUPPORT
+/*
+ * get_secret - open the CHAP secret file and return the secret
+ * for authenticating the given client on the given server.
+ * (We could be either client or server).
+ */
+int get_secret( int unit, char *client, char *server, char *secret, int *secret_len, int save_addrs)
+{
+#if 1
+  int len;
+  struct wordlist *addrs;
+
+  LWIP_UNUSED_ARG(unit);
+  LWIP_UNUSED_ARG(server);
+  LWIP_UNUSED_ARG(save_addrs);
+
+  addrs = NULL;
+
+  if(!client || !client[0] || strcmp(client, ppp_settings.user)) {
+    return 0;
+  }
+
+  len = strlen(ppp_settings.passwd);
+  if (len > MAXSECRETLEN) {
+    AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server));
+    len = MAXSECRETLEN;
+  }
+
+  BCOPY(ppp_settings.passwd, secret, len);
+  *secret_len = len;
+
+  return 1;
+#else
+  int ret = 0, len;
+  struct wordlist *addrs;
+  char secbuf[MAXWORDLEN];
+  
+  addrs = NULL;
+  secbuf[0] = 0;
+
+  /* XXX Find secret. */
+  if (ret < 0) {
+    return 0;
+  }
+
+  if (save_addrs) {
+    set_allowed_addrs(unit, addrs);
+  }
+
+  len = strlen(secbuf);
+  if (len > MAXSECRETLEN) {
+    AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server));
+    len = MAXSECRETLEN;
+  }
+
+  BCOPY(secbuf, secret, len);
+  BZERO(secbuf, sizeof(secbuf));
+  *secret_len = len;
+
+  return 1;
+#endif
+}
+#endif /* CHAP_SUPPORT */
+
+
+#if 0 /* UNUSED */
+/*
+ * auth_check_options - called to check authentication options.
+ */
+void
+auth_check_options(void)
+{
+  lcp_options *wo = &lcp_wantoptions[0];
+  int can_auth;
+  ipcp_options *ipwo = &ipcp_wantoptions[0];
+  u32_t remote;
+
+  /* Default our_name to hostname, and user to our_name */
+  if (ppp_settings.our_name[0] == 0 || ppp_settings.usehostname) {
+      strcpy(ppp_settings.our_name, ppp_settings.hostname);
+  }
+
+  if (ppp_settings.user[0] == 0) {
+    strcpy(ppp_settings.user, ppp_settings.our_name);
+  }
+
+  /* If authentication is required, ask peer for CHAP or PAP. */
+  if (ppp_settings.auth_required && !wo->neg_chap && !wo->neg_upap) {
+    wo->neg_chap = 1;
+    wo->neg_upap = 1;
+  }
+  
+  /*
+   * Check whether we have appropriate secrets to use
+   * to authenticate the peer.
+   */
+  can_auth = wo->neg_upap && have_pap_secret();
+  if (!can_auth && wo->neg_chap) {
+    remote = ipwo->accept_remote? 0: ipwo->hisaddr;
+    can_auth = have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote);
+  }
+
+  if (ppp_settings.auth_required && !can_auth) {
+    ppp_panic("No auth secret");
+  }
+}
+#endif
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * Proceed to the network phase.
+ */
+static void
+network_phase(int unit)
+{
+  int i;
+  struct protent *protp;
+  lcp_options *go = &lcp_gotoptions[unit];
+  
+  /*
+   * If the peer had to authenticate, run the auth-up script now.
+   */
+  if ((go->neg_chap || go->neg_upap) && !did_authup) {
+    /* XXX Do setup for peer authentication. */
+    did_authup = 1;
+  }
+
+#if CBCP_SUPPORT
+  /*
+   * If we negotiated callback, do it now.
+   */
+  if (go->neg_cbcp) {
+    lcp_phase[unit] = PHASE_CALLBACK;
+    (*cbcp_protent.open)(unit);
+    return;
+  }
+#endif /* CBCP_SUPPORT */
+
+  lcp_phase[unit] = PHASE_NETWORK;
+  for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+    if (protp->protocol < 0xC000 && protp->enabled_flag && protp->open != NULL) {
+      (*protp->open)(unit);
+      if (protp->protocol != PPP_CCP) {
+        ++num_np_open;
+      }
+    }
+  }
+
+  if (num_np_open == 0) {
+    /* nothing to do */
+    lcp_close(0, "No network protocols running");
+  }
+}
+
+/*
+ * check_idle - check whether the link has been idle for long
+ * enough that we can shut it down.
+ */
+static void
+check_idle(void *arg)
+{
+  struct ppp_idle idle;
+  u_short itime;
+  
+  LWIP_UNUSED_ARG(arg);
+  if (!get_idle_time(0, &idle)) {
+    return;
+  }
+  itime = LWIP_MIN(idle.xmit_idle, idle.recv_idle);
+  if (itime >= ppp_settings.idle_time_limit) {
+    /* link is idle: shut it down. */
+    AUTHDEBUG((LOG_INFO, "Terminating connection due to lack of activity.\n"));
+    lcp_close(0, "Link inactive");
+  } else {
+    TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit - itime);
+  }
+}
+
+/*
+ * connect_time_expired - log a message and close the connection.
+ */
+static void
+connect_time_expired(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+
+  AUTHDEBUG((LOG_INFO, "Connect time expired\n"));
+  lcp_close(0, "Connect time expired");   /* Close connection */
+}
+
+#if 0
+/*
+ * login - Check the user name and password against the system
+ * password database, and login the user if OK.
+ *
+ * returns:
+ *  UPAP_AUTHNAK: Login failed.
+ *  UPAP_AUTHACK: Login succeeded.
+ * In either case, msg points to an appropriate message.
+ */
+static int
+login(char *user, char *passwd, char **msg, int *msglen)
+{
+  /* XXX Fail until we decide that we want to support logins. */
+  return (UPAP_AUTHNAK);
+}
+#endif
+
+/*
+ * logout - Logout the user.
+ */
+static void
+logout(void)
+{
+  logged_in = 0;
+}
+
+/*
+ * null_login - Check if a username of "" and a password of "" are
+ * acceptable, and iff so, set the list of acceptable IP addresses
+ * and return 1.
+ */
+static int
+null_login(int unit)
+{
+  LWIP_UNUSED_ARG(unit);
+  /* XXX Fail until we decide that we want to support logins. */
+  return 0;
+}
+
+/*
+ * get_pap_passwd - get a password for authenticating ourselves with
+ * our peer using PAP.  Returns 1 on success, 0 if no suitable password
+ * could be found.
+ */
+static int
+get_pap_passwd(int unit, char *user, char *passwd)
+{
+  LWIP_UNUSED_ARG(unit);
+/* normally we would reject PAP if no password is provided,
+   but this causes problems with some providers (like CHT in Taiwan)
+   who incorrectly request PAP and expect a bogus/empty password, so
+   always provide a default user/passwd of "none"/"none"
+*/
+  if(user) {
+    strcpy(user, "none");
+  }
+  if(passwd) {
+    strcpy(passwd, "none");
+  }
+  return 1;
+}
+
+/*
+ * have_pap_secret - check whether we have a PAP file with any
+ * secrets that we could possibly use for authenticating the peer.
+ */
+static int
+have_pap_secret(void)
+{
+  /* XXX Fail until we set up our passwords. */
+  return 0;
+}
+
+/*
+ * have_chap_secret - check whether we have a CHAP file with a
+ * secret that we could possibly use for authenticating `client'
+ * on `server'.  Either can be the null string, meaning we don't
+ * know the identity yet.
+ */
+static int
+have_chap_secret(char *client, char *server, u32_t remote)
+{
+  LWIP_UNUSED_ARG(client);
+  LWIP_UNUSED_ARG(server);
+  LWIP_UNUSED_ARG(remote);
+  /* XXX Fail until we set up our passwords. */
+  return 0;
+}
+
+#if 0 /* PAP_SUPPORT || CHAP_SUPPORT */
+/*
+ * set_allowed_addrs() - set the list of allowed addresses.
+ */
+static void
+set_allowed_addrs(int unit, struct wordlist *addrs)
+{
+  if (addresses[unit] != NULL) {
+    free_wordlist(addresses[unit]);
+  }
+  addresses[unit] = addrs;
+
+#if 0
+  /*
+   * If there's only one authorized address we might as well
+   * ask our peer for that one right away
+   */
+  if (addrs != NULL && addrs->next == NULL) {
+    char *p = addrs->word;
+    struct ipcp_options *wo = &ipcp_wantoptions[unit];
+    u32_t a;
+    struct hostent *hp;
+    
+    if (wo->hisaddr == 0 && *p != '!' && *p != '-' && strchr(p, '/') == NULL) {
+      hp = gethostbyname(p);
+      if (hp != NULL && hp->h_addrtype == AF_INET) {
+        a = *(u32_t *)hp->h_addr;
+      } else {
+        a = inet_addr(p);
+      }
+      if (a != (u32_t) -1) {
+        wo->hisaddr = a;
+      }
+    }
+  }
+#endif
+}
+#endif /* 0 */ /* PAP_SUPPORT || CHAP_SUPPORT */
+
+static int
+ip_addr_check(u32_t addr, struct wordlist *addrs)
+{
+  /* don't allow loopback or multicast address */
+  if (bad_ip_adrs(addr)) {
+    return 0;
+  }
+
+  if (addrs == NULL) {
+    return !ppp_settings.auth_required; /* no addresses authorized */
+  }
+
+  /* XXX All other addresses allowed. */
+  return 1;
+}
+
+#if 0 /* PAP_SUPPORT || CHAP_SUPPORT */
+/*
+ * free_wordlist - release memory allocated for a wordlist.
+ */
+static void
+free_wordlist(struct wordlist *wp)
+{
+  struct wordlist *next;
+  
+  while (wp != NULL) {
+    next = wp->next;
+    free(wp);
+    wp = next;
+  }
+}
+#endif  /* 0 */ /* PAP_SUPPORT || CHAP_SUPPORT */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/auth.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/auth.h
new file mode 100644
index 0000000..86ff049
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/auth.h
@@ -0,0 +1,111 @@
+/*****************************************************************************
+* auth.h -  PPP Authentication and phase control header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD pppd.h.
+*****************************************************************************/
+/*
+ * pppd.h - PPP daemon global declarations.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ */
+
+#ifndef AUTH_H
+#define AUTH_H
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+/* we are starting to use the link */
+void link_required (int);
+
+/* we are finished with the link */
+void link_terminated (int);
+
+/* the LCP layer has left the Opened state */
+void link_down (int);
+
+/* the link is up; authenticate now */
+void link_established (int);
+
+/* a network protocol has come up */
+void np_up (int, u16_t);
+
+/* a network protocol has gone down */
+void np_down (int, u16_t);
+
+/* a network protocol no longer needs link */
+void np_finished (int, u16_t);
+
+/* peer failed to authenticate itself */
+void auth_peer_fail (int, u16_t);
+
+/* peer successfully authenticated itself */
+void auth_peer_success (int, u16_t, char *, int);
+
+/* we failed to authenticate ourselves */
+void auth_withpeer_fail (int, u16_t);
+
+/* we successfully authenticated ourselves */
+void auth_withpeer_success (int, u16_t);
+
+/* check authentication options supplied */
+void auth_check_options (void);
+
+/* check what secrets we have */
+void auth_reset (int);
+
+/* Check peer-supplied username/password */
+int  check_passwd (int, char *, int, char *, int, char **, int *);
+
+/* get "secret" for chap */
+int  get_secret (int, char *, char *, char *, int *, int);
+
+/* check if IP address is authorized */
+int  auth_ip_addr (int, u32_t);
+
+/* check if IP address is unreasonable */
+int  bad_ip_adrs (u32_t);
+
+#endif /* AUTH_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/chap.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/chap.c
new file mode 100644
index 0000000..b3ea6b2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/chap.c
@@ -0,0 +1,903 @@
+/*** WARNING - THIS HAS NEVER BEEN FINISHED ***/
+/*****************************************************************************
+* chap.c - Network Challenge Handshake Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*   Original based on BSD chap.c.
+*****************************************************************************/
+/*
+ * chap.c - Challenge Handshake Authentication Protocol.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University.  The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1991 Gregory M. Christy.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Gregory M. Christy.  The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#if CHAP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "magic.h"
+#include "randm.h"
+#include "auth.h"
+#include "md5.h"
+#include "chap.h"
+#include "chpms.h"
+
+#include 
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Protocol entry points.
+ */
+static void ChapInit (int);
+static void ChapLowerUp (int);
+static void ChapLowerDown (int);
+static void ChapInput (int, u_char *, int);
+static void ChapProtocolReject (int);
+#if 0
+static int  ChapPrintPkt (u_char *, int, void (*) (void *, char *, ...), void *);
+#endif
+
+static void ChapChallengeTimeout (void *);
+static void ChapResponseTimeout (void *);
+static void ChapReceiveChallenge (chap_state *, u_char *, int, int);
+static void ChapRechallenge (void *);
+static void ChapReceiveResponse (chap_state *, u_char *, int, int);
+static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len);
+static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len);
+static void ChapSendStatus (chap_state *, int);
+static void ChapSendChallenge (chap_state *);
+static void ChapSendResponse (chap_state *);
+static void ChapGenChallenge (chap_state *);
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+chap_state chap[NUM_PPP]; /* CHAP state; one for each unit */
+
+struct protent chap_protent = {
+  PPP_CHAP,
+  ChapInit,
+  ChapInput,
+  ChapProtocolReject,
+  ChapLowerUp,
+  ChapLowerDown,
+  NULL,
+  NULL,
+#if 0
+  ChapPrintPkt,
+  NULL,
+#endif
+  1,
+  "CHAP",
+#if 0
+  NULL,
+  NULL,
+  NULL
+#endif
+};
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * ChapAuthWithPeer - Authenticate us with our peer (start client).
+ *
+ */
+void
+ChapAuthWithPeer(int unit, char *our_name, int digest)
+{
+  chap_state *cstate = &chap[unit];
+
+  cstate->resp_name = our_name;
+  cstate->resp_type = digest;
+
+  if (cstate->clientstate == CHAPCS_INITIAL ||
+      cstate->clientstate == CHAPCS_PENDING) {
+    /* lower layer isn't up - wait until later */
+    cstate->clientstate = CHAPCS_PENDING;
+    return;
+  }
+
+  /*
+   * We get here as a result of LCP coming up.
+   * So even if CHAP was open before, we will 
+   * have to re-authenticate ourselves.
+   */
+  cstate->clientstate = CHAPCS_LISTEN;
+}
+
+
+/*
+ * ChapAuthPeer - Authenticate our peer (start server).
+ */
+void
+ChapAuthPeer(int unit, char *our_name, int digest)
+{
+  chap_state *cstate = &chap[unit];
+
+  cstate->chal_name = our_name;
+  cstate->chal_type = digest;
+  
+  if (cstate->serverstate == CHAPSS_INITIAL ||
+      cstate->serverstate == CHAPSS_PENDING) {
+    /* lower layer isn't up - wait until later */
+    cstate->serverstate = CHAPSS_PENDING;
+    return;
+  }
+
+  ChapGenChallenge(cstate);
+  ChapSendChallenge(cstate);    /* crank it up dude! */
+  cstate->serverstate = CHAPSS_INITIAL_CHAL;
+}
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * ChapInit - Initialize a CHAP unit.
+ */
+static void
+ChapInit(int unit)
+{
+  chap_state *cstate = &chap[unit];
+
+  BZERO(cstate, sizeof(*cstate));
+  cstate->unit = unit;
+  cstate->clientstate = CHAPCS_INITIAL;
+  cstate->serverstate = CHAPSS_INITIAL;
+  cstate->timeouttime = CHAP_DEFTIMEOUT;
+  cstate->max_transmits = CHAP_DEFTRANSMITS;
+  /* random number generator is initialized in magic_init */
+}
+
+
+/*
+ * ChapChallengeTimeout - Timeout expired on sending challenge.
+ */
+static void
+ChapChallengeTimeout(void *arg)
+{
+  chap_state *cstate = (chap_state *) arg;
+
+  /* if we aren't sending challenges, don't worry.  then again we */
+  /* probably shouldn't be here either */
+  if (cstate->serverstate != CHAPSS_INITIAL_CHAL &&
+      cstate->serverstate != CHAPSS_RECHALLENGE) {
+    return;
+  }
+
+  if (cstate->chal_transmits >= cstate->max_transmits) {
+    /* give up on peer */
+    CHAPDEBUG((LOG_ERR, "Peer failed to respond to CHAP challenge\n"));
+    cstate->serverstate = CHAPSS_BADAUTH;
+    auth_peer_fail(cstate->unit, PPP_CHAP);
+    return;
+  }
+
+  ChapSendChallenge(cstate); /* Re-send challenge */
+}
+
+
+/*
+ * ChapResponseTimeout - Timeout expired on sending response.
+ */
+static void
+ChapResponseTimeout(void *arg)
+{
+  chap_state *cstate = (chap_state *) arg;
+
+  /* if we aren't sending a response, don't worry. */
+  if (cstate->clientstate != CHAPCS_RESPONSE) {
+    return;
+  }
+
+  ChapSendResponse(cstate);    /* re-send response */
+}
+
+
+/*
+ * ChapRechallenge - Time to challenge the peer again.
+ */
+static void
+ChapRechallenge(void *arg)
+{
+  chap_state *cstate = (chap_state *) arg;
+  
+  /* if we aren't sending a response, don't worry. */
+  if (cstate->serverstate != CHAPSS_OPEN) {
+    return;
+  }
+
+  ChapGenChallenge(cstate);
+  ChapSendChallenge(cstate);
+  cstate->serverstate = CHAPSS_RECHALLENGE;
+}
+
+
+/*
+ * ChapLowerUp - The lower layer is up.
+ *
+ * Start up if we have pending requests.
+ */
+static void
+ChapLowerUp(int unit)
+{
+  chap_state *cstate = &chap[unit];
+
+  if (cstate->clientstate == CHAPCS_INITIAL) {
+    cstate->clientstate = CHAPCS_CLOSED;
+  } else if (cstate->clientstate == CHAPCS_PENDING) {
+    cstate->clientstate = CHAPCS_LISTEN;
+  }
+
+  if (cstate->serverstate == CHAPSS_INITIAL) {
+    cstate->serverstate = CHAPSS_CLOSED;
+  } else if (cstate->serverstate == CHAPSS_PENDING) {
+    ChapGenChallenge(cstate);
+    ChapSendChallenge(cstate);
+    cstate->serverstate = CHAPSS_INITIAL_CHAL;
+  }
+}
+
+
+/*
+ * ChapLowerDown - The lower layer is down.
+ *
+ * Cancel all timeouts.
+ */
+static void
+ChapLowerDown(int unit)
+{
+  chap_state *cstate = &chap[unit];
+
+  /* Timeout(s) pending?  Cancel if so. */
+  if (cstate->serverstate == CHAPSS_INITIAL_CHAL ||
+      cstate->serverstate == CHAPSS_RECHALLENGE) {
+    UNTIMEOUT(ChapChallengeTimeout, cstate);
+  } else if (cstate->serverstate == CHAPSS_OPEN
+      && cstate->chal_interval != 0) {
+    UNTIMEOUT(ChapRechallenge, cstate);
+  }
+  if (cstate->clientstate == CHAPCS_RESPONSE) {
+    UNTIMEOUT(ChapResponseTimeout, cstate);
+  }
+  cstate->clientstate = CHAPCS_INITIAL;
+  cstate->serverstate = CHAPSS_INITIAL;
+}
+
+
+/*
+ * ChapProtocolReject - Peer doesn't grok CHAP.
+ */
+static void
+ChapProtocolReject(int unit)
+{
+  chap_state *cstate = &chap[unit];
+  
+  if (cstate->serverstate != CHAPSS_INITIAL &&
+      cstate->serverstate != CHAPSS_CLOSED) {
+    auth_peer_fail(unit, PPP_CHAP);
+  }
+  if (cstate->clientstate != CHAPCS_INITIAL &&
+      cstate->clientstate != CHAPCS_CLOSED) {
+    auth_withpeer_fail(unit, PPP_CHAP);
+  }
+  ChapLowerDown(unit); /* shutdown chap */
+}
+
+
+/*
+ * ChapInput - Input CHAP packet.
+ */
+static void
+ChapInput(int unit, u_char *inpacket, int packet_len)
+{
+  chap_state *cstate = &chap[unit];
+  u_char *inp;
+  u_char code, id;
+  int len;
+  
+  /*
+   * Parse header (code, id and length).
+   * If packet too short, drop it.
+   */
+  inp = inpacket;
+  if (packet_len < CHAP_HEADERLEN) {
+    CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short header.\n"));
+    return;
+  }
+  GETCHAR(code, inp);
+  GETCHAR(id, inp);
+  GETSHORT(len, inp);
+  if (len < CHAP_HEADERLEN) {
+    CHAPDEBUG((LOG_INFO, "ChapInput: rcvd illegal length.\n"));
+    return;
+  }
+  if (len > packet_len) {
+    CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short packet.\n"));
+    return;
+  }
+  len -= CHAP_HEADERLEN;
+  
+  /*
+   * Action depends on code (as in fact it usually does :-).
+   */
+  switch (code) {
+    case CHAP_CHALLENGE:
+      ChapReceiveChallenge(cstate, inp, id, len);
+      break;
+    
+    case CHAP_RESPONSE:
+      ChapReceiveResponse(cstate, inp, id, len);
+      break;
+    
+    case CHAP_FAILURE:
+      ChapReceiveFailure(cstate, inp, id, len);
+      break;
+    
+    case CHAP_SUCCESS:
+      ChapReceiveSuccess(cstate, inp, id, len);
+      break;
+    
+    default:        /* Need code reject? */
+      CHAPDEBUG((LOG_WARNING, "Unknown CHAP code (%d) received.\n", code));
+      break;
+  }
+}
+
+
+/*
+ * ChapReceiveChallenge - Receive Challenge and send Response.
+ */
+static void
+ChapReceiveChallenge(chap_state *cstate, u_char *inp, int id, int len)
+{
+  int rchallenge_len;
+  u_char *rchallenge;
+  int secret_len;
+  char secret[MAXSECRETLEN];
+  char rhostname[256];
+  MD5_CTX mdContext;
+  u_char hash[MD5_SIGNATURE_SIZE];
+  
+  CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: Rcvd id %d.\n", id));
+  if (cstate->clientstate == CHAPCS_CLOSED ||
+    cstate->clientstate == CHAPCS_PENDING) {
+    CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: in state %d\n",
+         cstate->clientstate));
+    return;
+  }
+
+  if (len < 2) {
+    CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n"));
+    return;
+  }
+
+  GETCHAR(rchallenge_len, inp);
+  len -= sizeof (u_char) + rchallenge_len;  /* now name field length */
+  if (len < 0) {
+    CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n"));
+    return;
+  }
+  rchallenge = inp;
+  INCPTR(rchallenge_len, inp);
+
+  if (len >= sizeof(rhostname)) {
+    len = sizeof(rhostname) - 1;
+  }
+  BCOPY(inp, rhostname, len);
+  rhostname[len] = '\000';
+
+  CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: received name field '%s'\n", rhostname));
+
+  /* Microsoft doesn't send their name back in the PPP packet */
+  if (ppp_settings.remote_name[0] != 0 && (ppp_settings.explicit_remote || rhostname[0] == 0)) {
+    strncpy(rhostname, ppp_settings.remote_name, sizeof(rhostname));
+    rhostname[sizeof(rhostname) - 1] = 0;
+    CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: using '%s' as remote name\n", rhostname));
+  }
+
+  /* get secret for authenticating ourselves with the specified host */
+  if (!get_secret(cstate->unit, cstate->resp_name, rhostname, secret, &secret_len, 0)) {
+    secret_len = 0;    /* assume null secret if can't find one */
+    CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating us to %s\n", rhostname));
+  }
+
+  /* cancel response send timeout if necessary */
+  if (cstate->clientstate == CHAPCS_RESPONSE) {
+    UNTIMEOUT(ChapResponseTimeout, cstate);
+  }
+
+  cstate->resp_id = id;
+  cstate->resp_transmits = 0;
+
+  /*  generate MD based on negotiated type */
+  switch (cstate->resp_type) { 
+
+  case CHAP_DIGEST_MD5:
+    MD5Init(&mdContext);
+    MD5Update(&mdContext, &cstate->resp_id, 1);
+    MD5Update(&mdContext, (u_char*)secret, secret_len);
+    MD5Update(&mdContext, rchallenge, rchallenge_len);
+    MD5Final(hash, &mdContext);
+    BCOPY(hash, cstate->response, MD5_SIGNATURE_SIZE);
+    cstate->resp_length = MD5_SIGNATURE_SIZE;
+    break;
+  
+#ifdef CHAPMS
+  case CHAP_MICROSOFT:
+    ChapMS(cstate, rchallenge, rchallenge_len, secret, secret_len);
+    break;
+#endif
+
+  default:
+    CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->resp_type));
+    return;
+  }
+
+  BZERO(secret, sizeof(secret));
+  ChapSendResponse(cstate);
+}
+
+
+/*
+ * ChapReceiveResponse - Receive and process response.
+ */
+static void
+ChapReceiveResponse(chap_state *cstate, u_char *inp, int id, int len)
+{
+  u_char *remmd, remmd_len;
+  int secret_len, old_state;
+  int code;
+  char rhostname[256];
+  MD5_CTX mdContext;
+  char secret[MAXSECRETLEN];
+  u_char hash[MD5_SIGNATURE_SIZE];
+  
+  CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: Rcvd id %d.\n", id));
+  
+  if (cstate->serverstate == CHAPSS_CLOSED ||
+      cstate->serverstate == CHAPSS_PENDING) {
+    CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: in state %d\n",
+    cstate->serverstate));
+    return;
+  }
+
+  if (id != cstate->chal_id) {
+    return;      /* doesn't match ID of last challenge */
+  }
+
+  /*
+  * If we have received a duplicate or bogus Response,
+  * we have to send the same answer (Success/Failure)
+  * as we did for the first Response we saw.
+  */
+  if (cstate->serverstate == CHAPSS_OPEN) {
+    ChapSendStatus(cstate, CHAP_SUCCESS);
+    return;
+  }
+  if (cstate->serverstate == CHAPSS_BADAUTH) {
+    ChapSendStatus(cstate, CHAP_FAILURE);
+    return;
+  }
+  
+  if (len < 2) {
+    CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n"));
+    return;
+  }
+  GETCHAR(remmd_len, inp); /* get length of MD */
+  remmd = inp;             /* get pointer to MD */
+  INCPTR(remmd_len, inp);
+  
+  len -= sizeof (u_char) + remmd_len;
+  if (len < 0) {
+    CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n"));
+    return;
+  }
+
+  UNTIMEOUT(ChapChallengeTimeout, cstate);
+  
+  if (len >= sizeof(rhostname)) {
+    len = sizeof(rhostname) - 1;
+  }
+  BCOPY(inp, rhostname, len);
+  rhostname[len] = '\000';
+
+  CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: received name field: %s\n", rhostname));
+
+  /*
+  * Get secret for authenticating them with us,
+  * do the hash ourselves, and compare the result.
+  */
+  code = CHAP_FAILURE;
+  if (!get_secret(cstate->unit, rhostname, cstate->chal_name, secret, &secret_len, 1)) {
+    /* CHAPDEBUG((LOG_WARNING, TL_CHAP, "No CHAP secret found for authenticating %s\n", rhostname)); */
+    CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating %s\n",
+    rhostname));
+  } else {
+    /*  generate MD based on negotiated type */
+    switch (cstate->chal_type) {
+
+      case CHAP_DIGEST_MD5:    /* only MD5 is defined for now */
+        if (remmd_len != MD5_SIGNATURE_SIZE) {
+          break;      /* it's not even the right length */
+        }
+        MD5Init(&mdContext);
+        MD5Update(&mdContext, &cstate->chal_id, 1);
+        MD5Update(&mdContext, (u_char*)secret, secret_len);
+        MD5Update(&mdContext, cstate->challenge, cstate->chal_len);
+        MD5Final(hash, &mdContext); 
+        
+        /* compare local and remote MDs and send the appropriate status */
+        if (memcmp (hash, remmd, MD5_SIGNATURE_SIZE) == 0) {
+          code = CHAP_SUCCESS;  /* they are the same! */
+        }
+        break;
+      
+      default:
+        CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->chal_type));
+    }
+  }
+  
+  BZERO(secret, sizeof(secret));
+  ChapSendStatus(cstate, code);
+
+  if (code == CHAP_SUCCESS) {
+    old_state = cstate->serverstate;
+    cstate->serverstate = CHAPSS_OPEN;
+    if (old_state == CHAPSS_INITIAL_CHAL) {
+      auth_peer_success(cstate->unit, PPP_CHAP, rhostname, len);
+    }
+    if (cstate->chal_interval != 0) {
+      TIMEOUT(ChapRechallenge, cstate, cstate->chal_interval);
+    }
+  } else {
+    CHAPDEBUG((LOG_ERR, "CHAP peer authentication failed\n"));
+    cstate->serverstate = CHAPSS_BADAUTH;
+    auth_peer_fail(cstate->unit, PPP_CHAP);
+  }
+}
+
+/*
+ * ChapReceiveSuccess - Receive Success
+ */
+static void
+ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len)
+{
+  LWIP_UNUSED_ARG(id);
+  LWIP_UNUSED_ARG(inp);
+
+  CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: Rcvd id %d.\n", id));
+
+  if (cstate->clientstate == CHAPCS_OPEN) {
+    /* presumably an answer to a duplicate response */
+    return;
+  }
+
+  if (cstate->clientstate != CHAPCS_RESPONSE) {
+    /* don't know what this is */
+    CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: in state %d\n", cstate->clientstate));
+    return;
+  }
+  
+  UNTIMEOUT(ChapResponseTimeout, cstate);
+  
+  /*
+   * Print message.
+   */
+  if (len > 0) {
+    PRINTMSG(inp, len);
+  }
+
+  cstate->clientstate = CHAPCS_OPEN;
+
+  auth_withpeer_success(cstate->unit, PPP_CHAP);
+}
+
+
+/*
+ * ChapReceiveFailure - Receive failure.
+ */
+static void
+ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len)
+{
+  LWIP_UNUSED_ARG(id);
+  LWIP_UNUSED_ARG(inp);
+
+  CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: Rcvd id %d.\n", id));
+
+  if (cstate->clientstate != CHAPCS_RESPONSE) {
+    /* don't know what this is */
+    CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: in state %d\n", cstate->clientstate));
+    return;
+  }
+
+  UNTIMEOUT(ChapResponseTimeout, cstate);
+
+  /*
+   * Print message.
+   */
+  if (len > 0) {
+    PRINTMSG(inp, len);
+  }
+
+  CHAPDEBUG((LOG_ERR, "CHAP authentication failed\n"));
+  auth_withpeer_fail(cstate->unit, PPP_CHAP);
+}
+
+
+/*
+ * ChapSendChallenge - Send an Authenticate challenge.
+ */
+static void
+ChapSendChallenge(chap_state *cstate)
+{
+  u_char *outp;
+  int chal_len, name_len;
+  int outlen;
+  
+  chal_len = cstate->chal_len;
+  name_len = strlen(cstate->chal_name);
+  outlen = CHAP_HEADERLEN + sizeof (u_char) + chal_len + name_len;
+  outp = outpacket_buf[cstate->unit];
+  
+  MAKEHEADER(outp, PPP_CHAP);    /* paste in a CHAP header */
+  
+  PUTCHAR(CHAP_CHALLENGE, outp);
+  PUTCHAR(cstate->chal_id, outp);
+  PUTSHORT(outlen, outp);
+  
+  PUTCHAR(chal_len, outp);    /* put length of challenge */
+  BCOPY(cstate->challenge, outp, chal_len);
+  INCPTR(chal_len, outp);
+  
+  BCOPY(cstate->chal_name, outp, name_len);  /* append hostname */
+  
+  pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+  
+  CHAPDEBUG((LOG_INFO, "ChapSendChallenge: Sent id %d.\n", cstate->chal_id));
+  
+  TIMEOUT(ChapChallengeTimeout, cstate, cstate->timeouttime);
+  ++cstate->chal_transmits;
+}
+
+
+/*
+ * ChapSendStatus - Send a status response (ack or nak).
+ */
+static void
+ChapSendStatus(chap_state *cstate, int code)
+{
+  u_char *outp;
+  int outlen, msglen;
+  char msg[256];
+  
+  if (code == CHAP_SUCCESS) {
+    strcpy(msg, "Welcome!");
+  } else {
+    strcpy(msg, "I don't like you.  Go 'way.");
+  }
+  msglen = strlen(msg);
+  
+  outlen = CHAP_HEADERLEN + msglen;
+  outp = outpacket_buf[cstate->unit];
+  
+  MAKEHEADER(outp, PPP_CHAP);    /* paste in a header */
+  
+  PUTCHAR(code, outp);
+  PUTCHAR(cstate->chal_id, outp);
+  PUTSHORT(outlen, outp);
+  BCOPY(msg, outp, msglen);
+  pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+  
+  CHAPDEBUG((LOG_INFO, "ChapSendStatus: Sent code %d, id %d.\n", code, cstate->chal_id));
+}
+
+/*
+ * ChapGenChallenge is used to generate a pseudo-random challenge string of
+ * a pseudo-random length between min_len and max_len.  The challenge
+ * string and its length are stored in *cstate, and various other fields of
+ * *cstate are initialized.
+ */
+
+static void
+ChapGenChallenge(chap_state *cstate)
+{
+  int chal_len;
+  u_char *ptr = cstate->challenge;
+  int i;
+  
+  /* pick a random challenge length between MIN_CHALLENGE_LENGTH and 
+     MAX_CHALLENGE_LENGTH */  
+  chal_len = (unsigned)
+        ((((magic() >> 16) *
+              (MAX_CHALLENGE_LENGTH - MIN_CHALLENGE_LENGTH)) >> 16)
+           + MIN_CHALLENGE_LENGTH);
+  cstate->chal_len = chal_len;
+  cstate->chal_id = ++cstate->id;
+  cstate->chal_transmits = 0;
+  
+  /* generate a random string */
+  for (i = 0; i < chal_len; i++ ) {
+    *ptr++ = (char) (magic() & 0xff);
+  }
+}
+
+/*
+ * ChapSendResponse - send a response packet with values as specified
+ * in *cstate.
+ */
+/* ARGSUSED */
+static void
+ChapSendResponse(chap_state *cstate)
+{
+  u_char *outp;
+  int outlen, md_len, name_len;
+  
+  md_len = cstate->resp_length;
+  name_len = strlen(cstate->resp_name);
+  outlen = CHAP_HEADERLEN + sizeof (u_char) + md_len + name_len;
+  outp = outpacket_buf[cstate->unit];
+  
+  MAKEHEADER(outp, PPP_CHAP);
+  
+  PUTCHAR(CHAP_RESPONSE, outp);  /* we are a response */
+  PUTCHAR(cstate->resp_id, outp);  /* copy id from challenge packet */
+  PUTSHORT(outlen, outp);      /* packet length */
+  
+  PUTCHAR(md_len, outp);      /* length of MD */
+  BCOPY(cstate->response, outp, md_len);    /* copy MD to buffer */
+  INCPTR(md_len, outp);
+  
+  BCOPY(cstate->resp_name, outp, name_len);  /* append our name */
+  
+  /* send the packet */
+  pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+  
+  cstate->clientstate = CHAPCS_RESPONSE;
+  TIMEOUT(ChapResponseTimeout, cstate, cstate->timeouttime);
+  ++cstate->resp_transmits;
+}
+
+#if 0
+static char *ChapCodenames[] = {
+  "Challenge", "Response", "Success", "Failure"
+};
+/*
+ * ChapPrintPkt - print the contents of a CHAP packet.
+ */
+static int
+ChapPrintPkt( u_char *p, int plen, void (*printer) (void *, char *, ...), void *arg)
+{
+  int code, id, len;
+  int clen, nlen;
+  u_char x;
+  
+  if (plen < CHAP_HEADERLEN) {
+    return 0;
+  }
+  GETCHAR(code, p);
+  GETCHAR(id, p);
+  GETSHORT(len, p);
+  if (len < CHAP_HEADERLEN || len > plen) {
+    return 0;
+  }
+  if (code >= 1 && code <= sizeof(ChapCodenames) / sizeof(char *)) {
+    printer(arg, " %s", ChapCodenames[code-1]);
+  } else {
+    printer(arg, " code=0x%x", code);
+  }
+  printer(arg, " id=0x%x", id);
+  len -= CHAP_HEADERLEN;
+  switch (code) {
+    case CHAP_CHALLENGE:
+    case CHAP_RESPONSE:
+      if (len < 1) {
+        break;
+      }
+      clen = p[0];
+      if (len < clen + 1) {
+        break;
+      }
+      ++p;
+      nlen = len - clen - 1;
+      printer(arg, " <");
+      for (; clen > 0; --clen) {
+        GETCHAR(x, p);
+        printer(arg, "%.2x", x);
+      }
+      printer(arg, ">, name = %.*Z", nlen, p);
+      break;
+    case CHAP_FAILURE:
+    case CHAP_SUCCESS:
+      printer(arg, " %.*Z", len, p);
+      break;
+    default:
+      for (clen = len; clen > 0; --clen) {
+        GETCHAR(x, p);
+        printer(arg, " %.2x", x);
+      }
+  }
+
+  return len + CHAP_HEADERLEN;
+}
+#endif
+
+#endif /* CHAP_SUPPORT */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/chap.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/chap.h
new file mode 100644
index 0000000..83dafd7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/chap.h
@@ -0,0 +1,166 @@
+/*****************************************************************************
+* chap.h - Network Challenge Handshake Authentication Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-03 Guy Lancaster , Global Election Systems Inc.
+*   Original built from BSD network code.
+******************************************************************************/
+/*
+ * chap.h - Challenge Handshake Authentication Protocol definitions.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University.  The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1991 Gregory M. Christy
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the author.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: chap.h,v 1.4 2007/12/19 20:47:22 fbernon Exp $
+ */
+
+#ifndef CHAP_H
+#define CHAP_H
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+
+/* Code + ID + length */
+#define CHAP_HEADERLEN 4
+
+/*
+ * CHAP codes.
+ */
+
+#define CHAP_DIGEST_MD5      5    /* use MD5 algorithm */
+#define MD5_SIGNATURE_SIZE   16   /* 16 bytes in a MD5 message digest */
+#define CHAP_MICROSOFT       0x80 /* use Microsoft-compatible alg. */
+#define MS_CHAP_RESPONSE_LEN 49   /* Response length for MS-CHAP */
+
+#define CHAP_CHALLENGE       1
+#define CHAP_RESPONSE        2
+#define CHAP_SUCCESS         3
+#define CHAP_FAILURE         4
+
+/*
+ *  Challenge lengths (for challenges we send) and other limits.
+ */
+#define MIN_CHALLENGE_LENGTH 32
+#define MAX_CHALLENGE_LENGTH 64
+#define MAX_RESPONSE_LENGTH  64 /* sufficient for MD5 or MS-CHAP */
+
+/*
+ * Client (peer) states.
+ */
+#define CHAPCS_INITIAL       0 /* Lower layer down, not opened */
+#define CHAPCS_CLOSED        1 /* Lower layer up, not opened */
+#define CHAPCS_PENDING       2 /* Auth us to peer when lower up */
+#define CHAPCS_LISTEN        3 /* Listening for a challenge */
+#define CHAPCS_RESPONSE      4 /* Sent response, waiting for status */
+#define CHAPCS_OPEN          5 /* We've received Success */
+
+/*
+ * Server (authenticator) states.
+ */
+#define CHAPSS_INITIAL       0 /* Lower layer down, not opened */
+#define CHAPSS_CLOSED        1 /* Lower layer up, not opened */
+#define CHAPSS_PENDING       2 /* Auth peer when lower up */
+#define CHAPSS_INITIAL_CHAL  3 /* We've sent the first challenge */
+#define CHAPSS_OPEN          4 /* We've sent a Success msg */
+#define CHAPSS_RECHALLENGE   5 /* We've sent another challenge */
+#define CHAPSS_BADAUTH       6 /* We've sent a Failure msg */
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * Each interface is described by a chap structure.
+ */
+
+typedef struct chap_state {
+  int unit;                               /* Interface unit number */
+  int clientstate;                        /* Client state */
+  int serverstate;                        /* Server state */
+  u_char challenge[MAX_CHALLENGE_LENGTH]; /* last challenge string sent */
+  u_char chal_len;                        /* challenge length */
+  u_char chal_id;                         /* ID of last challenge */
+  u_char chal_type;                       /* hash algorithm for challenges */
+  u_char id;                              /* Current id */
+  char *chal_name;                        /* Our name to use with challenge */
+  int chal_interval;                      /* Time until we challenge peer again */
+  int timeouttime;                        /* Timeout time in seconds */
+  int max_transmits;                      /* Maximum # of challenge transmissions */
+  int chal_transmits;                     /* Number of transmissions of challenge */
+  int resp_transmits;                     /* Number of transmissions of response */
+  u_char response[MAX_RESPONSE_LENGTH];   /* Response to send */
+  u_char resp_length;                     /* length of response */
+  u_char resp_id;                         /* ID for response messages */
+  u_char resp_type;                       /* hash algorithm for responses */
+  char *resp_name;                        /* Our name to send with response */
+} chap_state;
+
+
+/******************
+*** PUBLIC DATA ***
+******************/
+extern chap_state chap[];
+
+extern struct protent chap_protent;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+void ChapAuthWithPeer (int, char *, int);
+void ChapAuthPeer (int, char *, int);
+
+#endif /* CHAP_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/chpms.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/chpms.c
new file mode 100644
index 0000000..582cfd2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/chpms.c
@@ -0,0 +1,399 @@
+/*** WARNING - THIS CODE HAS NOT BEEN FINISHED! ***/
+/*** The original PPPD code is written in a way to require either the UNIX DES
+     encryption functions encrypt(3) and setkey(3) or the DES library libdes.
+     Since both is not included in lwIP, MSCHAP currently does not work! */
+/*****************************************************************************
+* chpms.c - Network MicroSoft Challenge Handshake Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 by Global Election Systems Inc.  All rights reserved.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-08 Guy Lancaster , Global Election Systems Inc.
+*   Original based on BSD chap_ms.c.
+*****************************************************************************/
+/*
+ * chap_ms.c - Microsoft MS-CHAP compatible implementation.
+ *
+ * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited.
+ * http://www.strataware.com/
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Eric Rosenquist.  The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+/*
+ * Modifications by Lauri Pesonen / lpesonen@clinet.fi, april 1997
+ *
+ *   Implemented LANManager type password response to MS-CHAP challenges.
+ *   Now pppd provides both NT style and LANMan style blocks, and the
+ *   prefered is set by option "ms-lanman". Default is to use NT.
+ *   The hash text (StdText) was taken from Win95 RASAPI32.DLL.
+ *
+ *   You should also use DOMAIN\\USERNAME as described in README.MSCHAP80
+ */
+
+#define USE_CRYPT
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#if MSCHAP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "md4.h"
+#ifndef USE_CRYPT
+#include "des.h"
+#endif
+#include "chap.h"
+#include "chpms.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+typedef struct {
+    u_char LANManResp[24];
+    u_char NTResp[24];
+    u_char UseNT; /* If 1, ignore the LANMan response field */
+} MS_ChapResponse;
+/* We use MS_CHAP_RESPONSE_LEN, rather than sizeof(MS_ChapResponse),
+   in case this struct gets padded. */
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+
+/* XXX Don't know what to do with these. */
+extern void setkey(const char *);
+extern void encrypt(char *, int);
+
+static void DesEncrypt (u_char *, u_char *, u_char *);
+static void MakeKey (u_char *, u_char *);
+
+#ifdef USE_CRYPT
+static void Expand (u_char *, u_char *);
+static void Collapse (u_char *, u_char *);
+#endif
+
+static void ChallengeResponse(
+  u_char *challenge, /* IN   8 octets */
+  u_char *pwHash,    /* IN  16 octets */
+  u_char *response   /* OUT 24 octets */
+);
+static void ChapMS_NT(
+  char *rchallenge,
+  int rchallenge_len,
+  char *secret,
+  int secret_len,
+  MS_ChapResponse *response
+);
+static u_char Get7Bits(
+  u_char *input,
+  int startBit
+);
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+void
+ChapMS( chap_state *cstate, char *rchallenge, int rchallenge_len, char *secret, int secret_len)
+{
+  MS_ChapResponse response;
+#ifdef MSLANMAN
+  extern int ms_lanman;
+#endif
+
+#if 0
+  CHAPDEBUG((LOG_INFO, "ChapMS: secret is '%.*s'\n", secret_len, secret));
+#endif
+  BZERO(&response, sizeof(response));
+
+  /* Calculate both always */
+  ChapMS_NT(rchallenge, rchallenge_len, secret, secret_len, &response);
+
+#ifdef MSLANMAN
+  ChapMS_LANMan(rchallenge, rchallenge_len, secret, secret_len, &response);
+
+  /* prefered method is set by option  */
+  response.UseNT = !ms_lanman;
+#else
+  response.UseNT = 1;
+#endif
+
+  BCOPY(&response, cstate->response, MS_CHAP_RESPONSE_LEN);
+  cstate->resp_length = MS_CHAP_RESPONSE_LEN;
+}
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+static void
+ChallengeResponse( u_char *challenge, /* IN   8 octets */
+                   u_char *pwHash,    /* IN  16 octets */
+                   u_char *response   /* OUT 24 octets */)
+{
+  char    ZPasswordHash[21];
+
+  BZERO(ZPasswordHash, sizeof(ZPasswordHash));
+  BCOPY(pwHash, ZPasswordHash, 16);
+
+#if 0
+  log_packet(ZPasswordHash, sizeof(ZPasswordHash), "ChallengeResponse - ZPasswordHash", LOG_DEBUG);
+#endif
+
+  DesEncrypt(challenge, ZPasswordHash +  0, response + 0);
+  DesEncrypt(challenge, ZPasswordHash +  7, response + 8);
+  DesEncrypt(challenge, ZPasswordHash + 14, response + 16);
+
+#if 0
+  log_packet(response, 24, "ChallengeResponse - response", LOG_DEBUG);
+#endif
+}
+
+
+#ifdef USE_CRYPT
+static void
+DesEncrypt( u_char *clear, /* IN  8 octets */
+            u_char *key,   /* IN  7 octets */
+            u_char *cipher /* OUT 8 octets */)
+{
+  u_char des_key[8];
+  u_char crypt_key[66];
+  u_char des_input[66];
+
+  MakeKey(key, des_key);
+
+  Expand(des_key, crypt_key);
+  setkey(crypt_key);
+
+#if 0
+  CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n",
+             clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7]));
+#endif
+
+  Expand(clear, des_input);
+  encrypt(des_input, 0);
+  Collapse(des_input, cipher);
+
+#if 0
+  CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+             cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7]));
+#endif
+}
+
+#else /* USE_CRYPT */
+
+static void
+DesEncrypt( u_char *clear, /* IN  8 octets */
+            u_char *key,   /* IN  7 octets */
+            u_char *cipher /* OUT 8 octets */)
+{
+  des_cblock    des_key;
+  des_key_schedule  key_schedule;
+
+  MakeKey(key, des_key);
+
+  des_set_key(&des_key, key_schedule);
+
+#if 0
+  CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n",
+             clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7]));
+#endif
+
+  des_ecb_encrypt((des_cblock *)clear, (des_cblock *)cipher, key_schedule, 1);
+
+#if 0
+  CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+             cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7]));
+#endif
+}
+
+#endif /* USE_CRYPT */
+
+
+static u_char
+Get7Bits( u_char *input, int startBit)
+{
+  register unsigned int  word;
+
+  word  = (unsigned)input[startBit / 8] << 8;
+  word |= (unsigned)input[startBit / 8 + 1];
+
+  word >>= 15 - (startBit % 8 + 7);
+
+  return word & 0xFE;
+}
+
+#ifdef USE_CRYPT
+
+/* in == 8-byte string (expanded version of the 56-bit key)
+ * out == 64-byte string where each byte is either 1 or 0
+ * Note that the low-order "bit" is always ignored by by setkey()
+ */
+static void
+Expand(u_char *in, u_char *out)
+{
+  int j, c;
+  int i;
+
+  for(i = 0; i < 64; in++){
+    c = *in;
+    for(j = 7; j >= 0; j--) {
+      *out++ = (c >> j) & 01;
+    }
+    i += 8;
+  }
+}
+
+/* The inverse of Expand
+ */
+static void
+Collapse(u_char *in, u_char *out)
+{
+  int j;
+  int i;
+  unsigned int c;
+
+  for (i = 0; i < 64; i += 8, out++) {
+    c = 0;
+    for (j = 7; j >= 0; j--, in++) {
+      c |= *in << j;
+    }
+    *out = c & 0xff;
+  }
+}
+#endif
+
+static void
+MakeKey( u_char *key,    /* IN  56 bit DES key missing parity bits */
+         u_char *des_key /* OUT 64 bit DES key with parity bits added */)
+{
+  des_key[0] = Get7Bits(key,  0);
+  des_key[1] = Get7Bits(key,  7);
+  des_key[2] = Get7Bits(key, 14);
+  des_key[3] = Get7Bits(key, 21);
+  des_key[4] = Get7Bits(key, 28);
+  des_key[5] = Get7Bits(key, 35);
+  des_key[6] = Get7Bits(key, 42);
+  des_key[7] = Get7Bits(key, 49);
+  
+#ifndef USE_CRYPT
+  des_set_odd_parity((des_cblock *)des_key);
+#endif
+  
+#if 0
+  CHAPDEBUG((LOG_INFO, "MakeKey: 56-bit input : %02X%02X%02X%02X%02X%02X%02X\n",
+             key[0], key[1], key[2], key[3], key[4], key[5], key[6]));
+  CHAPDEBUG((LOG_INFO, "MakeKey: 64-bit output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+             des_key[0], des_key[1], des_key[2], des_key[3], des_key[4], des_key[5], des_key[6], des_key[7]));
+#endif
+}
+
+static void
+ChapMS_NT( char *rchallenge,
+           int rchallenge_len,
+           char *secret,
+           int secret_len,
+           MS_ChapResponse *response)
+{
+  int      i;
+  MDstruct  md4Context;
+  u_char    unicodePassword[MAX_NT_PASSWORD * 2];
+  static int  low_byte_first = -1;
+
+  /* Initialize the Unicode version of the secret (== password). */
+  /* This implicitly supports 8-bit ISO8859/1 characters. */
+  BZERO(unicodePassword, sizeof(unicodePassword));
+  for (i = 0; i < secret_len; i++) {
+    unicodePassword[i * 2] = (u_char)secret[i];
+  }
+  MDbegin(&md4Context);
+  MDupdate(&md4Context, unicodePassword, secret_len * 2 * 8);  /* Unicode is 2 bytes/char, *8 for bit count */
+
+  if (low_byte_first == -1) {
+    low_byte_first = (htons((unsigned short int)1) != 1);
+  }
+  if (low_byte_first == 0) {
+    MDreverse((u_long *)&md4Context);  /*  sfb 961105 */
+  }
+
+  MDupdate(&md4Context, NULL, 0);  /* Tell MD4 we're done */
+
+  ChallengeResponse(rchallenge, (char *)md4Context.buffer, response->NTResp);
+}
+
+#ifdef MSLANMAN
+static u_char *StdText = (u_char *)"KGS!@#$%"; /* key from rasapi32.dll */
+
+static void
+ChapMS_LANMan( char *rchallenge,
+               int rchallenge_len,
+               char *secret,
+               int secret_len,
+               MS_ChapResponse  *response)
+{
+  int      i;
+  u_char    UcasePassword[MAX_NT_PASSWORD]; /* max is actually 14 */
+  u_char    PasswordHash[16];
+  
+  /* LANMan password is case insensitive */
+  BZERO(UcasePassword, sizeof(UcasePassword));
+  for (i = 0; i < secret_len; i++) {
+    UcasePassword[i] = (u_char)toupper(secret[i]);
+  }
+  DesEncrypt( StdText, UcasePassword + 0, PasswordHash + 0 );
+  DesEncrypt( StdText, UcasePassword + 7, PasswordHash + 8 );
+  ChallengeResponse(rchallenge, PasswordHash, response->LANManResp);
+}
+#endif
+
+#endif /* MSCHAP_SUPPORT */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/chpms.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/chpms.h
new file mode 100644
index 0000000..df070fb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/chpms.h
@@ -0,0 +1,64 @@
+/*****************************************************************************
+* chpms.h - Network Microsoft Challenge Handshake Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-01-30 Guy Lancaster , Global Election Systems Inc.
+*   Original built from BSD network code.
+******************************************************************************/
+/*
+ * chap.h - Challenge Handshake Authentication Protocol definitions.
+ *
+ * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited.
+ * http://www.strataware.com/
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Eric Rosenquist.  The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: chpms.h,v 1.5 2007/12/19 20:47:23 fbernon Exp $
+ */
+
+#ifndef CHPMS_H
+#define CHPMS_H
+
+#define MAX_NT_PASSWORD 256 /* Maximum number of (Unicode) chars in an NT password */
+
+void ChapMS (chap_state *, char *, int, char *, int);
+
+#endif /* CHPMS_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/fsm.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/fsm.c
new file mode 100644
index 0000000..ee549f2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/fsm.c
@@ -0,0 +1,908 @@
+/*****************************************************************************
+* fsm.c - Network Control Protocol Finite State Machine program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-01 Guy Lancaster , Global Election Systems Inc.
+*   Original based on BSD fsm.c.
+*****************************************************************************/
+/*
+ * fsm.c - {Link, IP} Control Protocol Finite State Machine.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+/*
+ * TODO:
+ * Randomize fsm id on link/init.
+ * Deal with variable outgoing MTU.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "fsm.h"
+
+#include 
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+#if PPP_DEBUG
+
+static const char *ppperr_strerr[] = {
+           "LS_INITIAL",  /* LS_INITIAL  0 */
+           "LS_STARTING", /* LS_STARTING 1 */
+           "LS_CLOSED",   /* LS_CLOSED   2 */
+           "LS_STOPPED",  /* LS_STOPPED  3 */
+           "LS_CLOSING",  /* LS_CLOSING  4 */
+           "LS_STOPPING", /* LS_STOPPING 5 */
+           "LS_REQSENT",  /* LS_REQSENT  6 */
+           "LS_ACKRCVD",  /* LS_ACKRCVD  7 */
+           "LS_ACKSENT",  /* LS_ACKSENT  8 */
+           "LS_OPENED"    /* LS_OPENED   9 */
+};
+
+#endif /* PPP_DEBUG */
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+static void fsm_timeout (void *);
+static void fsm_rconfreq (fsm *, u_char, u_char *, int);
+static void fsm_rconfack (fsm *, int, u_char *, int);
+static void fsm_rconfnakrej (fsm *, int, int, u_char *, int);
+static void fsm_rtermreq (fsm *, int, u_char *, int);
+static void fsm_rtermack (fsm *);
+static void fsm_rcoderej (fsm *, u_char *, int);
+static void fsm_sconfreq (fsm *, int);
+
+#define PROTO_NAME(f) ((f)->callbacks->proto_name)
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+int peer_mru[NUM_PPP];
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+
+/*
+ * fsm_init - Initialize fsm.
+ *
+ * Initialize fsm state.
+ */
+void
+fsm_init(fsm *f)
+{
+  f->state = LS_INITIAL;
+  f->flags = 0;
+  f->id = 0;        /* XXX Start with random id? */
+  f->timeouttime = FSM_DEFTIMEOUT;
+  f->maxconfreqtransmits = FSM_DEFMAXCONFREQS;
+  f->maxtermtransmits = FSM_DEFMAXTERMREQS;
+  f->maxnakloops = FSM_DEFMAXNAKLOOPS;
+  f->term_reason_len = 0;
+}
+
+
+/*
+ * fsm_lowerup - The lower layer is up.
+ */
+void
+fsm_lowerup(fsm *f)
+{
+  int oldState = f->state;
+
+  LWIP_UNUSED_ARG(oldState);
+
+  switch( f->state ) {
+    case LS_INITIAL:
+      f->state = LS_CLOSED;
+      break;
+
+    case LS_STARTING:
+      if( f->flags & OPT_SILENT ) {
+        f->state = LS_STOPPED;
+      } else {
+        /* Send an initial configure-request */
+        fsm_sconfreq(f, 0);
+        f->state = LS_REQSENT;
+      }
+    break;
+
+    default:
+      FSMDEBUG((LOG_INFO, "%s: Up event in state %d (%s)!\n",
+          PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+  }
+  
+  FSMDEBUG((LOG_INFO, "%s: lowerup state %d (%s) -> %d (%s)\n",
+      PROTO_NAME(f), oldState, ppperr_strerr[oldState], f->state, ppperr_strerr[f->state]));
+}
+
+
+/*
+ * fsm_lowerdown - The lower layer is down.
+ *
+ * Cancel all timeouts and inform upper layers.
+ */
+void
+fsm_lowerdown(fsm *f)
+{
+  int oldState = f->state;
+
+  LWIP_UNUSED_ARG(oldState);
+
+  switch( f->state ) {
+    case LS_CLOSED:
+      f->state = LS_INITIAL;
+      break;
+
+    case LS_STOPPED:
+      f->state = LS_STARTING;
+      if( f->callbacks->starting ) {
+        (*f->callbacks->starting)(f);
+      }
+      break;
+
+    case LS_CLOSING:
+      f->state = LS_INITIAL;
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      break;
+
+    case LS_STOPPING:
+    case LS_REQSENT:
+    case LS_ACKRCVD:
+    case LS_ACKSENT:
+      f->state = LS_STARTING;
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      break;
+
+    case LS_OPENED:
+      if( f->callbacks->down ) {
+        (*f->callbacks->down)(f);
+      }
+      f->state = LS_STARTING;
+      break;
+
+    default:
+      FSMDEBUG((LOG_INFO, "%s: Down event in state %d (%s)!\n",
+          PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+  }
+
+  FSMDEBUG((LOG_INFO, "%s: lowerdown state %d (%s) -> %d (%s)\n",
+      PROTO_NAME(f), oldState, ppperr_strerr[oldState], f->state, ppperr_strerr[f->state]));
+}
+
+
+/*
+ * fsm_open - Link is allowed to come up.
+ */
+void
+fsm_open(fsm *f)
+{
+  int oldState = f->state;
+
+  LWIP_UNUSED_ARG(oldState);
+
+  switch( f->state ) {
+    case LS_INITIAL:
+      f->state = LS_STARTING;
+      if( f->callbacks->starting ) {
+        (*f->callbacks->starting)(f);
+      }
+      break;
+
+    case LS_CLOSED:
+      if( f->flags & OPT_SILENT ) {
+        f->state = LS_STOPPED;
+      } else {
+        /* Send an initial configure-request */
+        fsm_sconfreq(f, 0);
+        f->state = LS_REQSENT;
+      }
+      break;
+  
+    case LS_CLOSING:
+      f->state = LS_STOPPING;
+      /* fall through */
+    case LS_STOPPED:
+    case LS_OPENED:
+      if( f->flags & OPT_RESTART ) {
+        fsm_lowerdown(f);
+        fsm_lowerup(f);
+      }
+      break;
+  }
+
+  FSMDEBUG((LOG_INFO, "%s: open state %d (%s) -> %d (%s)\n",
+      PROTO_NAME(f), oldState, ppperr_strerr[oldState], f->state, ppperr_strerr[f->state]));
+}
+
+
+/*
+ * fsm_close - Start closing connection.
+ *
+ * Cancel timeouts and either initiate close or possibly go directly to
+ * the LS_CLOSED state.
+ */
+void
+fsm_close(fsm *f, char *reason)
+{
+  int oldState = f->state;
+
+  LWIP_UNUSED_ARG(oldState);
+
+  f->term_reason = reason;
+  f->term_reason_len = (reason == NULL? 0: strlen(reason));
+  switch( f->state ) {
+    case LS_STARTING:
+      f->state = LS_INITIAL;
+      break;
+    case LS_STOPPED:
+      f->state = LS_CLOSED;
+      break;
+    case LS_STOPPING:
+      f->state = LS_CLOSING;
+      break;
+
+    case LS_REQSENT:
+    case LS_ACKRCVD:
+    case LS_ACKSENT:
+    case LS_OPENED:
+      if( f->state != LS_OPENED ) {
+        UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      } else if( f->callbacks->down ) {
+        (*f->callbacks->down)(f);  /* Inform upper layers we're down */
+      }
+      /* Init restart counter, send Terminate-Request */
+      f->retransmits = f->maxtermtransmits;
+      fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+            (u_char *) f->term_reason, f->term_reason_len);
+      TIMEOUT(fsm_timeout, f, f->timeouttime);
+      --f->retransmits;
+
+      f->state = LS_CLOSING;
+      break;
+  }
+
+  FSMDEBUG((LOG_INFO, "%s: close reason=%s state %d (%s) -> %d (%s)\n",
+      PROTO_NAME(f), reason, oldState, ppperr_strerr[oldState], f->state, ppperr_strerr[f->state]));
+}
+
+
+/*
+ * fsm_sdata - Send some data.
+ *
+ * Used for all packets sent to our peer by this module.
+ */
+void
+fsm_sdata( fsm *f, u_char code, u_char id, u_char *data, int datalen)
+{
+  u_char *outp;
+  int outlen;
+
+  /* Adjust length to be smaller than MTU */
+  outp = outpacket_buf[f->unit];
+  if (datalen > peer_mru[f->unit] - (int)HEADERLEN) {
+    datalen = peer_mru[f->unit] - HEADERLEN;
+  }
+  if (datalen && data != outp + PPP_HDRLEN + HEADERLEN) {
+    BCOPY(data, outp + PPP_HDRLEN + HEADERLEN, datalen);
+  }
+  outlen = datalen + HEADERLEN;
+  MAKEHEADER(outp, f->protocol);
+  PUTCHAR(code, outp);
+  PUTCHAR(id, outp);
+  PUTSHORT(outlen, outp);
+  pppWrite(f->unit, outpacket_buf[f->unit], outlen + PPP_HDRLEN);
+  FSMDEBUG((LOG_INFO, "fsm_sdata(%s): Sent code %d,%d,%d.\n",
+        PROTO_NAME(f), code, id, outlen));
+}
+
+
+/*
+ * fsm_input - Input packet.
+ */
+void
+fsm_input(fsm *f, u_char *inpacket, int l)
+{
+  u_char *inp = inpacket;
+  u_char code, id;
+  int len;
+
+  /*
+  * Parse header (code, id and length).
+  * If packet too short, drop it.
+  */
+  if (l < HEADERLEN) {
+    FSMDEBUG((LOG_WARNING, "fsm_input(%x): Rcvd short header.\n",
+          f->protocol));
+    return;
+  }
+  GETCHAR(code, inp);
+  GETCHAR(id, inp);
+  GETSHORT(len, inp);
+  if (len < HEADERLEN) {
+    FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd illegal length.\n",
+        f->protocol));
+    return;
+  }
+  if (len > l) {
+    FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd short packet.\n",
+        f->protocol));
+    return;
+  }
+  len -= HEADERLEN;    /* subtract header length */
+
+  if( f->state == LS_INITIAL || f->state == LS_STARTING ) {
+    FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd packet in state %d (%s).\n",
+        f->protocol, f->state, ppperr_strerr[f->state]));
+    return;
+  }
+  FSMDEBUG((LOG_INFO, "fsm_input(%s):%d,%d,%d\n", PROTO_NAME(f), code, id, l));
+  /*
+   * Action depends on code.
+   */
+  switch (code) {
+    case CONFREQ:
+      fsm_rconfreq(f, id, inp, len);
+      break;
+    
+    case CONFACK:
+      fsm_rconfack(f, id, inp, len);
+      break;
+    
+    case CONFNAK:
+    case CONFREJ:
+      fsm_rconfnakrej(f, code, id, inp, len);
+      break;
+    
+    case TERMREQ:
+      fsm_rtermreq(f, id, inp, len);
+      break;
+    
+    case TERMACK:
+      fsm_rtermack(f);
+      break;
+    
+    case CODEREJ:
+      fsm_rcoderej(f, inp, len);
+      break;
+    
+    default:
+      if( !f->callbacks->extcode ||
+          !(*f->callbacks->extcode)(f, code, id, inp, len) ) {
+        fsm_sdata(f, CODEREJ, ++f->id, inpacket, len + HEADERLEN);
+      }
+      break;
+  }
+}
+
+
+/*
+ * fsm_protreject - Peer doesn't speak this protocol.
+ *
+ * Treat this as a catastrophic error (RXJ-).
+ */
+void
+fsm_protreject(fsm *f)
+{
+  switch( f->state ) {
+    case LS_CLOSING:
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      /* fall through */
+    case LS_CLOSED:
+      f->state = LS_CLOSED;
+      if( f->callbacks->finished ) {
+        (*f->callbacks->finished)(f);
+      }
+      break;
+
+    case LS_STOPPING:
+    case LS_REQSENT:
+    case LS_ACKRCVD:
+    case LS_ACKSENT:
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      /* fall through */
+    case LS_STOPPED:
+      f->state = LS_STOPPED;
+      if( f->callbacks->finished ) {
+        (*f->callbacks->finished)(f);
+      }
+      break;
+    
+    case LS_OPENED:
+      if( f->callbacks->down ) {
+        (*f->callbacks->down)(f);
+      }
+      /* Init restart counter, send Terminate-Request */
+      f->retransmits = f->maxtermtransmits;
+      fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+            (u_char *) f->term_reason, f->term_reason_len);
+      TIMEOUT(fsm_timeout, f, f->timeouttime);
+      --f->retransmits;
+      
+      f->state = LS_STOPPING;
+      break;
+    
+    default:
+      FSMDEBUG((LOG_INFO, "%s: Protocol-reject event in state %d (%s)!\n",
+            PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+    }
+}
+
+
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+
+/*
+ * fsm_timeout - Timeout expired.
+ */
+static void
+fsm_timeout(void *arg)
+{
+  fsm *f = (fsm *) arg;
+
+  switch (f->state) {
+    case LS_CLOSING:
+    case LS_STOPPING:
+      if( f->retransmits <= 0 ) {
+        FSMDEBUG((LOG_WARNING, "%s: timeout sending Terminate-Request state=%d (%s)\n",
+             PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+        /*
+         * We've waited for an ack long enough.  Peer probably heard us.
+         */
+        f->state = (f->state == LS_CLOSING)? LS_CLOSED: LS_STOPPED;
+        if( f->callbacks->finished ) {
+          (*f->callbacks->finished)(f);
+        }
+      } else {
+        FSMDEBUG((LOG_WARNING, "%s: timeout resending Terminate-Requests state=%d (%s)\n",
+             PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+        /* Send Terminate-Request */
+        fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+            (u_char *) f->term_reason, f->term_reason_len);
+        TIMEOUT(fsm_timeout, f, f->timeouttime);
+        --f->retransmits;
+      }
+      break;
+
+    case LS_REQSENT:
+    case LS_ACKRCVD:
+    case LS_ACKSENT:
+      if (f->retransmits <= 0) {
+        FSMDEBUG((LOG_WARNING, "%s: timeout sending Config-Requests state=%d (%s)\n",
+         PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+        f->state = LS_STOPPED;
+        if( (f->flags & OPT_PASSIVE) == 0 && f->callbacks->finished ) {
+          (*f->callbacks->finished)(f);
+        }
+      } else {
+        FSMDEBUG((LOG_WARNING, "%s: timeout resending Config-Request state=%d (%s)\n",
+         PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+        /* Retransmit the configure-request */
+        if (f->callbacks->retransmit) {
+          (*f->callbacks->retransmit)(f);
+        }
+        fsm_sconfreq(f, 1);    /* Re-send Configure-Request */
+        if( f->state == LS_ACKRCVD ) {
+          f->state = LS_REQSENT;
+        }
+      }
+      break;
+
+    default:
+      FSMDEBUG((LOG_INFO, "%s: UNHANDLED timeout event in state %d (%s)!\n",
+          PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+  }
+}
+
+
+/*
+ * fsm_rconfreq - Receive Configure-Request.
+ */
+static void
+fsm_rconfreq(fsm *f, u_char id, u_char *inp, int len)
+{
+  int code, reject_if_disagree;
+
+  FSMDEBUG((LOG_INFO, "fsm_rconfreq(%s): Rcvd id %d state=%d (%s)\n", 
+        PROTO_NAME(f), id, f->state, ppperr_strerr[f->state]));
+  switch( f->state ) {
+    case LS_CLOSED:
+      /* Go away, we're closed */
+      fsm_sdata(f, TERMACK, id, NULL, 0);
+      return;
+    case LS_CLOSING:
+    case LS_STOPPING:
+      return;
+
+    case LS_OPENED:
+      /* Go down and restart negotiation */
+      if( f->callbacks->down ) {
+        (*f->callbacks->down)(f);  /* Inform upper layers */
+      }
+      fsm_sconfreq(f, 0);    /* Send initial Configure-Request */
+      break;
+
+    case LS_STOPPED:
+      /* Negotiation started by our peer */
+      fsm_sconfreq(f, 0);    /* Send initial Configure-Request */
+      f->state = LS_REQSENT;
+      break;
+  }
+  
+  /*
+  * Pass the requested configuration options
+  * to protocol-specific code for checking.
+  */
+  if (f->callbacks->reqci) {    /* Check CI */
+    reject_if_disagree = (f->nakloops >= f->maxnakloops);
+    code = (*f->callbacks->reqci)(f, inp, &len, reject_if_disagree);
+  } else if (len) {
+    code = CONFREJ;      /* Reject all CI */
+  } else {
+    code = CONFACK;
+  }
+  
+  /* send the Ack, Nak or Rej to the peer */
+  fsm_sdata(f, (u_char)code, id, inp, len);
+  
+  if (code == CONFACK) {
+    if (f->state == LS_ACKRCVD) {
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      f->state = LS_OPENED;
+      if (f->callbacks->up) {
+        (*f->callbacks->up)(f);  /* Inform upper layers */
+      }
+    } else {
+      f->state = LS_ACKSENT;
+    }
+    f->nakloops = 0;
+  } else {
+    /* we sent CONFACK or CONFREJ */
+    if (f->state != LS_ACKRCVD) {
+      f->state = LS_REQSENT;
+    }
+    if( code == CONFNAK ) {
+      ++f->nakloops;
+    }
+  }
+}
+
+
+/*
+ * fsm_rconfack - Receive Configure-Ack.
+ */
+static void
+fsm_rconfack(fsm *f, int id, u_char *inp, int len)
+{
+  FSMDEBUG((LOG_INFO, "fsm_rconfack(%s): Rcvd id %d state=%d (%s)\n",
+        PROTO_NAME(f), id, f->state, ppperr_strerr[f->state]));
+  
+  if (id != f->reqid || f->seen_ack) {   /* Expected id? */
+    return; /* Nope, toss... */
+  }
+  if( !(f->callbacks->ackci? (*f->callbacks->ackci)(f, inp, len): (len == 0)) ) {
+    /* Ack is bad - ignore it */
+    FSMDEBUG((LOG_INFO, "%s: received bad Ack (length %d)\n",
+          PROTO_NAME(f), len));
+    return;
+  }
+  f->seen_ack = 1;
+  
+  switch (f->state) {
+    case LS_CLOSED:
+    case LS_STOPPED:
+      fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+      break;
+    
+    case LS_REQSENT:
+      f->state = LS_ACKRCVD;
+      f->retransmits = f->maxconfreqtransmits;
+      break;
+    
+    case LS_ACKRCVD:
+      /* Huh? an extra valid Ack? oh well... */
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      fsm_sconfreq(f, 0);
+      f->state = LS_REQSENT;
+      break;
+    
+    case LS_ACKSENT:
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      f->state = LS_OPENED;
+      f->retransmits = f->maxconfreqtransmits;
+      if (f->callbacks->up) {
+        (*f->callbacks->up)(f);  /* Inform upper layers */
+      }
+      break;
+    
+    case LS_OPENED:
+      /* Go down and restart negotiation */
+      if (f->callbacks->down) {
+        (*f->callbacks->down)(f);  /* Inform upper layers */
+      }
+      fsm_sconfreq(f, 0);    /* Send initial Configure-Request */
+      f->state = LS_REQSENT;
+      break;
+  }
+}
+
+
+/*
+ * fsm_rconfnakrej - Receive Configure-Nak or Configure-Reject.
+ */
+static void
+fsm_rconfnakrej(fsm *f, int code, int id, u_char *inp, int len)
+{
+  int (*proc) (fsm *, u_char *, int);
+  int ret;
+
+  FSMDEBUG((LOG_INFO, "fsm_rconfnakrej(%s): Rcvd id %d state=%d (%s)\n",
+        PROTO_NAME(f), id, f->state, ppperr_strerr[f->state]));
+
+  if (id != f->reqid || f->seen_ack) { /* Expected id? */
+    return;        /* Nope, toss... */
+  }
+  proc = (code == CONFNAK)? f->callbacks->nakci: f->callbacks->rejci;
+  if (!proc || !((ret = proc(f, inp, len)))) {
+    /* Nak/reject is bad - ignore it */
+    FSMDEBUG((LOG_INFO, "%s: received bad %s (length %d)\n",
+          PROTO_NAME(f), (code==CONFNAK? "Nak": "reject"), len));
+    return;
+  }
+  f->seen_ack = 1;
+
+  switch (f->state) {
+    case LS_CLOSED:
+    case LS_STOPPED:
+      fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+      break;
+    
+    case LS_REQSENT:
+    case LS_ACKSENT:
+      /* They didn't agree to what we wanted - try another request */
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      if (ret < 0) {
+        f->state = LS_STOPPED;    /* kludge for stopping CCP */
+      } else {
+        fsm_sconfreq(f, 0);    /* Send Configure-Request */
+      }
+      break;
+    
+    case LS_ACKRCVD:
+      /* Got a Nak/reject when we had already had an Ack?? oh well... */
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      fsm_sconfreq(f, 0);
+      f->state = LS_REQSENT;
+      break;
+    
+    case LS_OPENED:
+      /* Go down and restart negotiation */
+      if (f->callbacks->down) {
+        (*f->callbacks->down)(f);  /* Inform upper layers */
+      }
+      fsm_sconfreq(f, 0);    /* Send initial Configure-Request */
+      f->state = LS_REQSENT;
+      break;
+  }
+}
+
+
+/*
+ * fsm_rtermreq - Receive Terminate-Req.
+ */
+static void
+fsm_rtermreq(fsm *f, int id, u_char *p, int len)
+{
+  LWIP_UNUSED_ARG(p);
+
+  FSMDEBUG((LOG_INFO, "fsm_rtermreq(%s): Rcvd id %d state=%d (%s)\n",
+        PROTO_NAME(f), id, f->state, ppperr_strerr[f->state]));
+
+  switch (f->state) {
+    case LS_ACKRCVD:
+    case LS_ACKSENT:
+      f->state = LS_REQSENT;    /* Start over but keep trying */
+      break;
+
+    case LS_OPENED:
+      if (len > 0) {
+        FSMDEBUG((LOG_INFO, "%s terminated by peer (%x)\n", PROTO_NAME(f), p));
+      } else {
+        FSMDEBUG((LOG_INFO, "%s terminated by peer\n", PROTO_NAME(f)));
+      }
+      if (f->callbacks->down) {
+        (*f->callbacks->down)(f);  /* Inform upper layers */
+      }
+      f->retransmits = 0;
+      f->state = LS_STOPPING;
+      TIMEOUT(fsm_timeout, f, f->timeouttime);
+      break;
+  }
+
+  fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+}
+
+
+/*
+ * fsm_rtermack - Receive Terminate-Ack.
+ */
+static void
+fsm_rtermack(fsm *f)
+{
+  FSMDEBUG((LOG_INFO, "fsm_rtermack(%s): state=%d (%s)\n", 
+        PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+  
+  switch (f->state) {
+    case LS_CLOSING:
+      UNTIMEOUT(fsm_timeout, f);
+      f->state = LS_CLOSED;
+      if( f->callbacks->finished ) {
+        (*f->callbacks->finished)(f);
+      }
+      break;
+
+    case LS_STOPPING:
+      UNTIMEOUT(fsm_timeout, f);
+      f->state = LS_STOPPED;
+      if( f->callbacks->finished ) {
+        (*f->callbacks->finished)(f);
+      }
+      break;
+    
+    case LS_ACKRCVD:
+      f->state = LS_REQSENT;
+      break;
+    
+    case LS_OPENED:
+      if (f->callbacks->down) {
+        (*f->callbacks->down)(f);  /* Inform upper layers */
+      }
+      fsm_sconfreq(f, 0);
+      break;
+  }
+}
+
+
+/*
+ * fsm_rcoderej - Receive an Code-Reject.
+ */
+static void
+fsm_rcoderej(fsm *f, u_char *inp, int len)
+{
+  u_char code, id;
+  
+  FSMDEBUG((LOG_INFO, "fsm_rcoderej(%s): state=%d (%s)\n", 
+        PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+  
+  if (len < HEADERLEN) {
+    FSMDEBUG((LOG_INFO, "fsm_rcoderej: Rcvd short Code-Reject packet!\n"));
+    return;
+  }
+  GETCHAR(code, inp);
+  GETCHAR(id, inp);
+  FSMDEBUG((LOG_WARNING, "%s: Rcvd Code-Reject for code %d, id %d\n",
+        PROTO_NAME(f), code, id));
+  
+  if( f->state == LS_ACKRCVD ) {
+    f->state = LS_REQSENT;
+  }
+}
+
+
+/*
+ * fsm_sconfreq - Send a Configure-Request.
+ */
+static void
+fsm_sconfreq(fsm *f, int retransmit)
+{
+  u_char *outp;
+  int cilen;
+  
+  if( f->state != LS_REQSENT && f->state != LS_ACKRCVD && f->state != LS_ACKSENT ) {
+    /* Not currently negotiating - reset options */
+    if( f->callbacks->resetci ) {
+      (*f->callbacks->resetci)(f);
+    }
+    f->nakloops = 0;
+  }
+  
+  if( !retransmit ) {
+    /* New request - reset retransmission counter, use new ID */
+    f->retransmits = f->maxconfreqtransmits;
+    f->reqid = ++f->id;
+  }
+  
+  f->seen_ack = 0;
+  
+  /*
+   * Make up the request packet
+   */
+  outp = outpacket_buf[f->unit] + PPP_HDRLEN + HEADERLEN;
+  if( f->callbacks->cilen && f->callbacks->addci ) {
+    cilen = (*f->callbacks->cilen)(f);
+    if( cilen > peer_mru[f->unit] - (int)HEADERLEN ) {
+      cilen = peer_mru[f->unit] - HEADERLEN;
+    }
+    if (f->callbacks->addci) {
+      (*f->callbacks->addci)(f, outp, &cilen);
+    }
+  } else {
+    cilen = 0;
+  }
+
+  /* send the request to our peer */
+  fsm_sdata(f, CONFREQ, f->reqid, outp, cilen);
+  
+  /* start the retransmit timer */
+  --f->retransmits;
+  TIMEOUT(fsm_timeout, f, f->timeouttime);
+  
+  FSMDEBUG((LOG_INFO, "%s: sending Configure-Request, id %d\n",
+        PROTO_NAME(f), f->reqid));
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/fsm.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/fsm.h
new file mode 100644
index 0000000..14034ec
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/fsm.h
@@ -0,0 +1,169 @@
+/*****************************************************************************
+* fsm.h - Network Control Protocol Finite State Machine header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*   Original based on BSD code.
+*****************************************************************************/
+/*
+ * fsm.h - {Link, IP} Control Protocol Finite State Machine definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: fsm.h,v 1.4 2007/12/19 20:47:23 fbernon Exp $
+ */
+
+#ifndef FSM_H
+#define FSM_H
+
+/*****************************************************************************
+************************* PUBLIC DEFINITIONS *********************************
+*****************************************************************************/
+/*
+ * LCP Packet header = Code, id, length.
+ */
+#define HEADERLEN (sizeof (u_char) + sizeof (u_char) + sizeof (u_short))
+
+
+/*
+ *  CP (LCP, IPCP, etc.) codes.
+ */
+#define CONFREQ     1 /* Configuration Request */
+#define CONFACK     2 /* Configuration Ack */
+#define CONFNAK     3 /* Configuration Nak */
+#define CONFREJ     4 /* Configuration Reject */
+#define TERMREQ     5 /* Termination Request */
+#define TERMACK     6 /* Termination Ack */
+#define CODEREJ     7 /* Code Reject */
+
+/*
+ * Link states.
+ */
+#define LS_INITIAL  0 /* Down, hasn't been opened */
+#define LS_STARTING 1 /* Down, been opened */
+#define LS_CLOSED   2 /* Up, hasn't been opened */
+#define LS_STOPPED  3 /* Open, waiting for down event */
+#define LS_CLOSING  4 /* Terminating the connection, not open */
+#define LS_STOPPING 5 /* Terminating, but open */
+#define LS_REQSENT  6 /* We've sent a Config Request */
+#define LS_ACKRCVD  7 /* We've received a Config Ack */
+#define LS_ACKSENT  8 /* We've sent a Config Ack */
+#define LS_OPENED   9 /* Connection available */
+
+/*
+ * Flags - indicate options controlling FSM operation
+ */
+#define OPT_PASSIVE 1 /* Don't die if we don't get a response */
+#define OPT_RESTART 2 /* Treat 2nd OPEN as DOWN, UP */
+#define OPT_SILENT  4 /* Wait for peer to speak first */
+
+
+/*****************************************************************************
+************************* PUBLIC DATA TYPES **********************************
+*****************************************************************************/
+/*
+ * Each FSM is described by an fsm structure and fsm callbacks.
+ */
+typedef struct fsm {
+  int unit;                        /* Interface unit number */
+  u_short protocol;                /* Data Link Layer Protocol field value */
+  int state;                       /* State */
+  int flags;                       /* Contains option bits */
+  u_char id;                       /* Current id */
+  u_char reqid;                    /* Current request id */
+  u_char seen_ack;                 /* Have received valid Ack/Nak/Rej to Req */
+  int timeouttime;                 /* Timeout time in milliseconds */
+  int maxconfreqtransmits;         /* Maximum Configure-Request transmissions */
+  int retransmits;                 /* Number of retransmissions left */
+  int maxtermtransmits;            /* Maximum Terminate-Request transmissions */
+  int nakloops;                    /* Number of nak loops since last ack */
+  int maxnakloops;                 /* Maximum number of nak loops tolerated */
+  struct fsm_callbacks* callbacks; /* Callback routines */
+  char* term_reason;               /* Reason for closing protocol */
+  int term_reason_len;             /* Length of term_reason */
+} fsm;
+
+
+typedef struct fsm_callbacks {
+  void (*resetci)(fsm*);                            /* Reset our Configuration Information */
+  int  (*cilen)(fsm*);                              /* Length of our Configuration Information */
+  void (*addci)(fsm*, u_char*, int*);               /* Add our Configuration Information */
+  int  (*ackci)(fsm*, u_char*, int);                /* ACK our Configuration Information */
+  int  (*nakci)(fsm*, u_char*, int);                /* NAK our Configuration Information */
+  int  (*rejci)(fsm*, u_char*, int);                /* Reject our Configuration Information */
+  int  (*reqci)(fsm*, u_char*, int*, int);          /* Request peer's Configuration Information */
+  void (*up)(fsm*);                                 /* Called when fsm reaches LS_OPENED state */
+  void (*down)(fsm*);                               /* Called when fsm leaves LS_OPENED state */
+  void (*starting)(fsm*);                           /* Called when we want the lower layer */
+  void (*finished)(fsm*);                           /* Called when we don't want the lower layer */
+  void (*protreject)(int);                          /* Called when Protocol-Reject received */
+  void (*retransmit)(fsm*);                         /* Retransmission is necessary */
+  int  (*extcode)(fsm*, int, u_char, u_char*, int); /* Called when unknown code received */
+  char *proto_name;                                 /* String name for protocol (for messages) */
+} fsm_callbacks;
+
+
+/*****************************************************************************
+*********************** PUBLIC DATA STRUCTURES *******************************
+*****************************************************************************/
+/*
+ * Variables
+ */
+extern int peer_mru[]; /* currently negotiated peer MRU (per unit) */
+
+
+/*****************************************************************************
+************************** PUBLIC FUNCTIONS **********************************
+*****************************************************************************/
+
+/*
+ * Prototypes
+ */
+void fsm_init (fsm*);
+void fsm_lowerup (fsm*);
+void fsm_lowerdown (fsm*);
+void fsm_open (fsm*);
+void fsm_close (fsm*, char*);
+void fsm_input (fsm*, u_char*, int);
+void fsm_protreject (fsm*);
+void fsm_sdata (fsm*, u_char, u_char, u_char*, int);
+
+#endif /* FSM_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/ipcp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/ipcp.c
new file mode 100644
index 0000000..0ff4ce3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/ipcp.c
@@ -0,0 +1,1427 @@
+/*****************************************************************************
+* ipcp.c - Network PPP IP Control Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-08 Guy Lancaster , Global Election Systems Inc.
+*   Original.
+*****************************************************************************/
+/*
+ * ipcp.c - PPP IP Control Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "auth.h"
+#include "fsm.h"
+#include "vj.h"
+#include "ipcp.h"
+
+#include 
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+/* #define OLD_CI_ADDRS 1 */ /* Support deprecated address negotiation. */
+
+/*
+ * Lengths of configuration options.
+ */
+#define CILEN_VOID     2
+#define CILEN_COMPRESS 4  /* min length for compression protocol opt. */
+#define CILEN_VJ       6  /* length for RFC1332 Van-Jacobson opt. */
+#define CILEN_ADDR     6  /* new-style single address option */
+#define CILEN_ADDRS    10 /* old-style dual address option */
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Callbacks for fsm code.  (CI = Configuration Information)
+ */
+static void ipcp_resetci (fsm *);                     /* Reset our CI */
+static int  ipcp_cilen (fsm *);                       /* Return length of our CI */
+static void ipcp_addci (fsm *, u_char *, int *);      /* Add our CI */
+static int  ipcp_ackci (fsm *, u_char *, int);        /* Peer ack'd our CI */
+static int  ipcp_nakci (fsm *, u_char *, int);        /* Peer nak'd our CI */
+static int  ipcp_rejci (fsm *, u_char *, int);        /* Peer rej'd our CI */
+static int  ipcp_reqci (fsm *, u_char *, int *, int); /* Rcv CI */
+static void ipcp_up (fsm *);                          /* We're UP */
+static void ipcp_down (fsm *);                        /* We're DOWN */
+#if 0
+static void ipcp_script (fsm *, char *); /* Run an up/down script */
+#endif
+static void ipcp_finished (fsm *);                    /* Don't need lower layer */
+
+/*
+ * Protocol entry points from main code.
+ */
+static void ipcp_init (int);
+static void ipcp_open (int);
+static void ipcp_close (int, char *);
+static void ipcp_lowerup (int);
+static void ipcp_lowerdown (int);
+static void ipcp_input (int, u_char *, int);
+static void ipcp_protrej (int);
+
+static void ipcp_clear_addrs (int);
+
+#define CODENAME(x) ((x) == CONFACK ? "ACK" : \
+                     (x) == CONFNAK ? "NAK" : "REJ")
+
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+/* global vars */
+ipcp_options ipcp_wantoptions[NUM_PPP];  /* Options that we want to request */
+ipcp_options ipcp_gotoptions[NUM_PPP];   /* Options that peer ack'd */
+ipcp_options ipcp_allowoptions[NUM_PPP]; /* Options we allow peer to request */
+ipcp_options ipcp_hisoptions[NUM_PPP];   /* Options that we ack'd */
+
+fsm ipcp_fsm[NUM_PPP]; /* IPCP fsm structure */
+
+struct protent ipcp_protent = {
+  PPP_IPCP,
+  ipcp_init,
+  ipcp_input,
+  ipcp_protrej,
+  ipcp_lowerup,
+  ipcp_lowerdown,
+  ipcp_open,
+  ipcp_close,
+#if 0
+  ipcp_printpkt,
+  NULL,
+#endif
+  1,
+  "IPCP",
+#if 0
+  ip_check_options,
+  NULL,
+  ip_active_pkt
+#endif
+};
+
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+/* local vars */
+static int cis_received[NUM_PPP];      /* # Conf-Reqs received */
+static int default_route_set[NUM_PPP]; /* Have set up a default route */
+
+static fsm_callbacks ipcp_callbacks = { /* IPCP callback routines */
+  ipcp_resetci,  /* Reset our Configuration Information */
+  ipcp_cilen,    /* Length of our Configuration Information */
+  ipcp_addci,    /* Add our Configuration Information */
+  ipcp_ackci,    /* ACK our Configuration Information */
+  ipcp_nakci,    /* NAK our Configuration Information */
+  ipcp_rejci,    /* Reject our Configuration Information */
+  ipcp_reqci,    /* Request peer's Configuration Information */
+  ipcp_up,       /* Called when fsm reaches LS_OPENED state */
+  ipcp_down,     /* Called when fsm leaves LS_OPENED state */
+  NULL,          /* Called when we want the lower layer up */
+  ipcp_finished, /* Called when we want the lower layer down */
+  NULL,          /* Called when Protocol-Reject received */
+  NULL,          /* Retransmission is necessary */
+  NULL,          /* Called to handle protocol-specific codes */
+  "IPCP"         /* String name of protocol */
+};
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+
+#define inet_ntoa(addr) ip_ntoa(((struct ip_addr*)&(addr)))
+
+/*
+ * ipcp_init - Initialize IPCP.
+ */
+static void
+ipcp_init(int unit)
+{
+  fsm           *f = &ipcp_fsm[unit];
+  ipcp_options *wo = &ipcp_wantoptions[unit];
+  ipcp_options *ao = &ipcp_allowoptions[unit];
+
+  f->unit      = unit;
+  f->protocol  = PPP_IPCP;
+  f->callbacks = &ipcp_callbacks;
+  fsm_init(&ipcp_fsm[unit]);
+
+  memset(wo, 0, sizeof(*wo));
+  memset(ao, 0, sizeof(*ao));
+
+  wo->neg_addr      = 1;
+  wo->ouraddr       = 0;
+#if VJ_SUPPORT
+  wo->neg_vj        = 1;
+#else  /* VJ_SUPPORT */
+  wo->neg_vj        = 0;
+#endif /* VJ_SUPPORT */
+  wo->vj_protocol   = IPCP_VJ_COMP;
+  wo->maxslotindex  = MAX_SLOTS - 1;
+  wo->cflag         = 0;
+  wo->default_route = 1;
+
+  ao->neg_addr      = 1;
+#if VJ_SUPPORT
+  ao->neg_vj        = 1;
+#else  /* VJ_SUPPORT */
+  ao->neg_vj        = 0;
+#endif /* VJ_SUPPORT */
+  ao->maxslotindex  = MAX_SLOTS - 1;
+  ao->cflag         = 1;
+  ao->default_route = 1;
+}
+
+
+/*
+ * ipcp_open - IPCP is allowed to come up.
+ */
+static void
+ipcp_open(int unit)
+{
+  fsm_open(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_close - Take IPCP down.
+ */
+static void
+ipcp_close(int unit, char *reason)
+{
+  fsm_close(&ipcp_fsm[unit], reason);
+}
+
+
+/*
+ * ipcp_lowerup - The lower layer is up.
+ */
+static void
+ipcp_lowerup(int unit)
+{
+  fsm_lowerup(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_lowerdown - The lower layer is down.
+ */
+static void
+ipcp_lowerdown(int unit)
+{
+  fsm_lowerdown(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_input - Input IPCP packet.
+ */
+static void
+ipcp_input(int unit, u_char *p, int len)
+{
+  fsm_input(&ipcp_fsm[unit], p, len);
+}
+
+
+/*
+ * ipcp_protrej - A Protocol-Reject was received for IPCP.
+ *
+ * Pretend the lower layer went down, so we shut up.
+ */
+static void
+ipcp_protrej(int unit)
+{
+  fsm_lowerdown(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_resetci - Reset our CI.
+ */
+static void
+ipcp_resetci(fsm *f)
+{
+  ipcp_options *wo = &ipcp_wantoptions[f->unit];
+  
+  wo->req_addr = wo->neg_addr && ipcp_allowoptions[f->unit].neg_addr;
+  if (wo->ouraddr == 0) {
+    wo->accept_local = 1;
+  }
+  if (wo->hisaddr == 0) {
+    wo->accept_remote = 1;
+  }
+  /* Request DNS addresses from the peer */
+  wo->req_dns1 = ppp_settings.usepeerdns;
+  wo->req_dns2 = ppp_settings.usepeerdns;
+  ipcp_gotoptions[f->unit] = *wo;
+  cis_received[f->unit] = 0;
+}
+
+
+/*
+ * ipcp_cilen - Return length of our CI.
+ */
+static int
+ipcp_cilen(fsm *f)
+{
+  ipcp_options *go = &ipcp_gotoptions[f->unit];
+  ipcp_options *wo = &ipcp_wantoptions[f->unit];
+  ipcp_options *ho = &ipcp_hisoptions[f->unit];
+
+#define LENCIVJ(neg, old)   (neg ? (old? CILEN_COMPRESS : CILEN_VJ) : 0)
+#define LENCIADDR(neg, old) (neg ? (old? CILEN_ADDRS : CILEN_ADDR) : 0)
+#define LENCIDNS(neg)       (neg ? (CILEN_ADDR) : 0)
+
+  /*
+   * First see if we want to change our options to the old
+   * forms because we have received old forms from the peer.
+   */
+  if (wo->neg_addr && !go->neg_addr && !go->old_addrs) {
+    /* use the old style of address negotiation */
+    go->neg_addr = 1;
+    go->old_addrs = 1;
+  }
+  if (wo->neg_vj && !go->neg_vj && !go->old_vj) {
+    /* try an older style of VJ negotiation */
+    if (cis_received[f->unit] == 0) {
+      /* keep trying the new style until we see some CI from the peer */
+      go->neg_vj = 1;
+    } else {
+      /* use the old style only if the peer did */
+      if (ho->neg_vj && ho->old_vj) {
+        go->neg_vj = 1;
+        go->old_vj = 1;
+        go->vj_protocol = ho->vj_protocol;
+      }
+    }
+  }
+
+  return (LENCIADDR(go->neg_addr, go->old_addrs) +
+          LENCIVJ(go->neg_vj, go->old_vj) +
+          LENCIDNS(go->req_dns1) +
+          LENCIDNS(go->req_dns2));
+}
+
+
+/*
+ * ipcp_addci - Add our desired CIs to a packet.
+ */
+static void
+ipcp_addci(fsm *f, u_char *ucp, int *lenp)
+{
+  ipcp_options *go = &ipcp_gotoptions[f->unit];
+  int len = *lenp;
+
+#define ADDCIVJ(opt, neg, val, old, maxslotindex, cflag) \
+  if (neg) { \
+    int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \
+    if (len >= vjlen) { \
+      PUTCHAR(opt, ucp); \
+      PUTCHAR(vjlen, ucp); \
+      PUTSHORT(val, ucp); \
+      if (!old) { \
+        PUTCHAR(maxslotindex, ucp); \
+        PUTCHAR(cflag, ucp); \
+      } \
+      len -= vjlen; \
+    } else { \
+      neg = 0; \
+    } \
+  }
+
+#define ADDCIADDR(opt, neg, old, val1, val2) \
+  if (neg) { \
+    int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \
+    if (len >= addrlen) { \
+      u32_t l; \
+      PUTCHAR(opt, ucp); \
+      PUTCHAR(addrlen, ucp); \
+      l = ntohl(val1); \
+      PUTLONG(l, ucp); \
+      if (old) { \
+        l = ntohl(val2); \
+        PUTLONG(l, ucp); \
+      } \
+      len -= addrlen; \
+    } else { \
+      neg = 0; \
+    } \
+  }
+
+#define ADDCIDNS(opt, neg, addr) \
+  if (neg) { \
+    if (len >= CILEN_ADDR) { \
+      u32_t l; \
+      PUTCHAR(opt, ucp); \
+      PUTCHAR(CILEN_ADDR, ucp); \
+      l = ntohl(addr); \
+      PUTLONG(l, ucp); \
+      len -= CILEN_ADDR; \
+    } else { \
+      neg = 0; \
+    } \
+  }
+
+  ADDCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr,
+      go->old_addrs, go->ouraddr, go->hisaddr);
+
+  ADDCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj,
+      go->maxslotindex, go->cflag);
+
+  ADDCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]);
+
+  ADDCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]);
+
+  *lenp -= len;
+}
+
+
+/*
+ * ipcp_ackci - Ack our CIs.
+ *
+ * Returns:
+ *  0 - Ack was bad.
+ *  1 - Ack was good.
+ */
+static int
+ipcp_ackci(fsm *f, u_char *p, int len)
+{
+  ipcp_options *go = &ipcp_gotoptions[f->unit];
+  u_short cilen, citype, cishort;
+  u32_t cilong;
+  u_char cimaxslotindex, cicflag;
+
+  /*
+   * CIs must be in exactly the same order that we sent...
+   * Check packet length and CI length at each step.
+   * If we find any deviations, then this packet is bad.
+   */
+
+#define ACKCIVJ(opt, neg, val, old, maxslotindex, cflag) \
+  if (neg) { \
+    int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \
+    if ((len -= vjlen) < 0) { \
+      goto bad; \
+    } \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != vjlen || \
+        citype != opt) { \
+      goto bad; \
+    } \
+    GETSHORT(cishort, p); \
+    if (cishort != val) { \
+      goto bad; \
+    } \
+    if (!old) { \
+      GETCHAR(cimaxslotindex, p); \
+      if (cimaxslotindex != maxslotindex) { \
+        goto bad; \
+      } \
+      GETCHAR(cicflag, p); \
+      if (cicflag != cflag) { \
+        goto bad; \
+      } \
+    } \
+  }
+  
+#define ACKCIADDR(opt, neg, old, val1, val2) \
+  if (neg) { \
+    int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \
+    u32_t l; \
+    if ((len -= addrlen) < 0) { \
+      goto bad; \
+    } \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != addrlen || \
+        citype != opt) { \
+      goto bad; \
+    } \
+    GETLONG(l, p); \
+    cilong = htonl(l); \
+    if (val1 != cilong) { \
+      goto bad; \
+    } \
+    if (old) { \
+      GETLONG(l, p); \
+      cilong = htonl(l); \
+      if (val2 != cilong) { \
+        goto bad; \
+      } \
+    } \
+  }
+
+#define ACKCIDNS(opt, neg, addr) \
+  if (neg) { \
+    u32_t l; \
+    if ((len -= CILEN_ADDR) < 0) { \
+      goto bad; \
+    } \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != CILEN_ADDR || \
+        citype != opt) { \
+      goto bad; \
+    } \
+    GETLONG(l, p); \
+    cilong = htonl(l); \
+    if (addr != cilong) { \
+      goto bad; \
+    } \
+  }
+
+  ACKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr,
+        go->old_addrs, go->ouraddr, go->hisaddr);
+
+  ACKCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj,
+      go->maxslotindex, go->cflag);
+
+  ACKCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]);
+
+  ACKCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]);
+
+  /*
+   * If there are any remaining CIs, then this packet is bad.
+   */
+  if (len != 0) {
+    goto bad;
+  }
+  return (1);
+  
+bad:
+  IPCPDEBUG((LOG_INFO, "ipcp_ackci: received bad Ack!\n"));
+  return (0);
+}
+
+/*
+ * ipcp_nakci - Peer has sent a NAK for some of our CIs.
+ * This should not modify any state if the Nak is bad
+ * or if IPCP is in the LS_OPENED state.
+ *
+ * Returns:
+ *  0 - Nak was bad.
+ *  1 - Nak was good.
+ */
+static int
+ipcp_nakci(fsm *f, u_char *p, int len)
+{
+  ipcp_options *go = &ipcp_gotoptions[f->unit];
+  u_char cimaxslotindex, cicflag;
+  u_char citype, cilen, *next;
+  u_short cishort;
+  u32_t ciaddr1, ciaddr2, l, cidnsaddr;
+  ipcp_options no;    /* options we've seen Naks for */
+  ipcp_options try;    /* options to request next time */
+
+  BZERO(&no, sizeof(no));
+  try = *go;
+
+  /*
+   * Any Nak'd CIs must be in exactly the same order that we sent.
+   * Check packet length and CI length at each step.
+   * If we find any deviations, then this packet is bad.
+   */
+#define NAKCIADDR(opt, neg, old, code) \
+  if (go->neg && \
+      len >= (cilen = (old? CILEN_ADDRS: CILEN_ADDR)) && \
+      p[1] == cilen && \
+      p[0] == opt) { \
+    len -= cilen; \
+    INCPTR(2, p); \
+    GETLONG(l, p); \
+    ciaddr1 = htonl(l); \
+    if (old) { \
+      GETLONG(l, p); \
+      ciaddr2 = htonl(l); \
+      no.old_addrs = 1; \
+    } else { \
+      ciaddr2 = 0; \
+    } \
+    no.neg = 1; \
+    code \
+  }
+
+#define NAKCIVJ(opt, neg, code) \
+  if (go->neg && \
+      ((cilen = p[1]) == CILEN_COMPRESS || cilen == CILEN_VJ) && \
+      len >= cilen && \
+      p[0] == opt) { \
+    len -= cilen; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    no.neg = 1; \
+    code \
+  }
+  
+#define NAKCIDNS(opt, neg, code) \
+  if (go->neg && \
+      ((cilen = p[1]) == CILEN_ADDR) && \
+      len >= cilen && \
+      p[0] == opt) { \
+    len -= cilen; \
+    INCPTR(2, p); \
+    GETLONG(l, p); \
+    cidnsaddr = htonl(l); \
+    no.neg = 1; \
+    code \
+  }
+
+  /*
+   * Accept the peer's idea of {our,his} address, if different
+   * from our idea, only if the accept_{local,remote} flag is set.
+   */
+  NAKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr, go->old_addrs,
+    if (go->accept_local && ciaddr1) { /* Do we know our address? */
+      try.ouraddr = ciaddr1;
+      IPCPDEBUG((LOG_INFO, "local IP address %s\n",
+           inet_ntoa(ciaddr1)));
+    }
+    if (go->accept_remote && ciaddr2) { /* Does he know his? */
+      try.hisaddr = ciaddr2;
+      IPCPDEBUG((LOG_INFO, "remote IP address %s\n",
+           inet_ntoa(ciaddr2)));
+    }
+  );
+
+  /*
+   * Accept the peer's value of maxslotindex provided that it
+   * is less than what we asked for.  Turn off slot-ID compression
+   * if the peer wants.  Send old-style compress-type option if
+   * the peer wants.
+   */
+  NAKCIVJ(CI_COMPRESSTYPE, neg_vj,
+    if (cilen == CILEN_VJ) {
+      GETCHAR(cimaxslotindex, p);
+      GETCHAR(cicflag, p);
+      if (cishort == IPCP_VJ_COMP) {
+        try.old_vj = 0;
+        if (cimaxslotindex < go->maxslotindex) {
+          try.maxslotindex = cimaxslotindex;
+        }
+        if (!cicflag) {
+          try.cflag = 0;
+        }
+      } else {
+        try.neg_vj = 0;
+      }
+    } else {
+      if (cishort == IPCP_VJ_COMP || cishort == IPCP_VJ_COMP_OLD) {
+        try.old_vj = 1;
+        try.vj_protocol = cishort;
+      } else {
+        try.neg_vj = 0;
+      }
+    }
+  );
+
+  NAKCIDNS(CI_MS_DNS1, req_dns1,
+      try.dnsaddr[0] = cidnsaddr;
+        IPCPDEBUG((LOG_INFO, "primary DNS address %s\n", inet_ntoa(cidnsaddr)));
+      );
+
+  NAKCIDNS(CI_MS_DNS2, req_dns2,
+      try.dnsaddr[1] = cidnsaddr;
+        IPCPDEBUG((LOG_INFO, "secondary DNS address %s\n", inet_ntoa(cidnsaddr)));
+      );
+
+  /*
+  * There may be remaining CIs, if the peer is requesting negotiation
+  * on an option that we didn't include in our request packet.
+  * If they want to negotiate about IP addresses, we comply.
+  * If they want us to ask for compression, we refuse.
+  */
+  while (len > CILEN_VOID) {
+    GETCHAR(citype, p);
+    GETCHAR(cilen, p);
+    if( (len -= cilen) < 0 ) {
+      goto bad;
+    }
+    next = p + cilen - 2;
+
+    switch (citype) {
+      case CI_COMPRESSTYPE:
+        if (go->neg_vj || no.neg_vj ||
+            (cilen != CILEN_VJ && cilen != CILEN_COMPRESS)) {
+          goto bad;
+        }
+        no.neg_vj = 1;
+        break;
+      case CI_ADDRS:
+        if ((go->neg_addr && go->old_addrs) || no.old_addrs
+            || cilen != CILEN_ADDRS) {
+          goto bad;
+        }
+        try.neg_addr = 1;
+        try.old_addrs = 1;
+        GETLONG(l, p);
+        ciaddr1 = htonl(l);
+        if (ciaddr1 && go->accept_local) {
+          try.ouraddr = ciaddr1;
+        }
+        GETLONG(l, p);
+        ciaddr2 = htonl(l);
+        if (ciaddr2 && go->accept_remote) {
+          try.hisaddr = ciaddr2;
+        }
+        no.old_addrs = 1;
+        break;
+      case CI_ADDR:
+        if (go->neg_addr || no.neg_addr || cilen != CILEN_ADDR) {
+          goto bad;
+        }
+        try.old_addrs = 0;
+        GETLONG(l, p);
+        ciaddr1 = htonl(l);
+        if (ciaddr1 && go->accept_local) {
+          try.ouraddr = ciaddr1;
+        }
+        if (try.ouraddr != 0) {
+          try.neg_addr = 1;
+        }
+        no.neg_addr = 1;
+        break;
+    }
+    p = next;
+  }
+
+  /* If there is still anything left, this packet is bad. */
+  if (len != 0) {
+    goto bad;
+  }
+
+  /*
+   * OK, the Nak is good.  Now we can update state.
+   */
+  if (f->state != LS_OPENED) {
+    *go = try;
+  }
+
+  return 1;
+
+bad:
+  IPCPDEBUG((LOG_INFO, "ipcp_nakci: received bad Nak!\n"));
+  return 0;
+}
+
+
+/*
+ * ipcp_rejci - Reject some of our CIs.
+ */
+static int
+ipcp_rejci(fsm *f, u_char *p, int len)
+{
+  ipcp_options *go = &ipcp_gotoptions[f->unit];
+  u_char cimaxslotindex, ciflag, cilen;
+  u_short cishort;
+  u32_t cilong;
+  ipcp_options try;    /* options to request next time */
+
+  try = *go;
+  /*
+   * Any Rejected CIs must be in exactly the same order that we sent.
+   * Check packet length and CI length at each step.
+   * If we find any deviations, then this packet is bad.
+   */
+#define REJCIADDR(opt, neg, old, val1, val2) \
+  if (go->neg && \
+      len >= (cilen = old? CILEN_ADDRS: CILEN_ADDR) && \
+      p[1] == cilen && \
+      p[0] == opt) { \
+    u32_t l; \
+    len -= cilen; \
+    INCPTR(2, p); \
+    GETLONG(l, p); \
+    cilong = htonl(l); \
+    /* Check rejected value. */ \
+    if (cilong != val1) { \
+      goto bad; \
+    } \
+    if (old) { \
+      GETLONG(l, p); \
+      cilong = htonl(l); \
+      /* Check rejected value. */ \
+      if (cilong != val2) { \
+        goto bad; \
+      } \
+    } \
+    try.neg = 0; \
+  }
+
+#define REJCIVJ(opt, neg, val, old, maxslot, cflag) \
+  if (go->neg && \
+      p[1] == (old? CILEN_COMPRESS : CILEN_VJ) && \
+      len >= p[1] && \
+      p[0] == opt) { \
+    len -= p[1]; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    /* Check rejected value. */  \
+    if (cishort != val) { \
+      goto bad; \
+    } \
+    if (!old) { \
+      GETCHAR(cimaxslotindex, p); \
+      if (cimaxslotindex != maxslot) { \
+        goto bad; \
+      } \
+      GETCHAR(ciflag, p); \
+      if (ciflag != cflag) { \
+        goto bad; \
+      } \
+    } \
+    try.neg = 0; \
+  }
+
+#define REJCIDNS(opt, neg, dnsaddr) \
+  if (go->neg && \
+      ((cilen = p[1]) == CILEN_ADDR) && \
+      len >= cilen && \
+      p[0] == opt) { \
+    u32_t l; \
+    len -= cilen; \
+    INCPTR(2, p); \
+    GETLONG(l, p); \
+    cilong = htonl(l); \
+    /* Check rejected value. */ \
+    if (cilong != dnsaddr) { \
+      goto bad; \
+    } \
+    try.neg = 0; \
+  }
+
+  REJCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr,
+        go->old_addrs, go->ouraddr, go->hisaddr);
+
+  REJCIVJ(CI_COMPRESSTYPE, neg_vj, go->vj_protocol, go->old_vj,
+      go->maxslotindex, go->cflag);
+
+  REJCIDNS(CI_MS_DNS1, req_dns1, go->dnsaddr[0]);
+
+  REJCIDNS(CI_MS_DNS2, req_dns2, go->dnsaddr[1]);
+
+  /*
+   * If there are any remaining CIs, then this packet is bad.
+   */
+  if (len != 0) {
+    goto bad;
+  }
+  /*
+   * Now we can update state.
+   */
+  if (f->state != LS_OPENED) {
+    *go = try;
+  }
+  return 1;
+
+bad:
+  IPCPDEBUG((LOG_INFO, "ipcp_rejci: received bad Reject!\n"));
+  return 0;
+}
+
+
+/*
+ * ipcp_reqci - Check the peer's requested CIs and send appropriate response.
+ *
+ * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified
+ * appropriately.  If reject_if_disagree is non-zero, doesn't return
+ * CONFNAK; returns CONFREJ if it can't return CONFACK.
+ */
+static int
+ipcp_reqci(fsm *f, u_char *inp/* Requested CIs */,int *len/* Length of requested CIs */,int reject_if_disagree)
+{
+  ipcp_options *wo = &ipcp_wantoptions[f->unit];
+  ipcp_options *ho = &ipcp_hisoptions[f->unit];
+  ipcp_options *ao = &ipcp_allowoptions[f->unit];
+#ifdef OLD_CI_ADDRS
+  ipcp_options *go = &ipcp_gotoptions[f->unit];
+#endif
+  u_char *cip, *next;     /* Pointer to current and next CIs */
+  u_short cilen, citype;  /* Parsed len, type */
+  u_short cishort;        /* Parsed short value */
+  u32_t tl, ciaddr1;      /* Parsed address values */
+#ifdef OLD_CI_ADDRS
+  u32_t ciaddr2;          /* Parsed address values */
+#endif
+  int rc = CONFACK;       /* Final packet return code */
+  int orc;                /* Individual option return code */
+  u_char *p;              /* Pointer to next char to parse */
+  u_char *ucp = inp;      /* Pointer to current output char */
+  int l = *len;           /* Length left */
+  u_char maxslotindex, cflag;
+  int d;
+
+  cis_received[f->unit] = 1;
+
+  /*
+   * Reset all his options.
+   */
+  BZERO(ho, sizeof(*ho));
+
+  /*
+   * Process all his options.
+   */
+  next = inp;
+  while (l) {
+    orc = CONFACK;       /* Assume success */
+    cip = p = next;      /* Remember begining of CI */
+    if (l < 2 ||         /* Not enough data for CI header or */
+        p[1] < 2 ||      /*  CI length too small or */
+        p[1] > l) {      /*  CI length too big? */
+      IPCPDEBUG((LOG_INFO, "ipcp_reqci: bad CI length!\n"));
+      orc = CONFREJ;     /* Reject bad CI */
+      cilen = l;         /* Reject till end of packet */
+      l = 0;             /* Don't loop again */
+      goto endswitch;
+    }
+    GETCHAR(citype, p);  /* Parse CI type */
+    GETCHAR(cilen, p);   /* Parse CI length */
+    l -= cilen;          /* Adjust remaining length */
+    next += cilen;       /* Step to next CI */
+
+    switch (citype) {      /* Check CI type */
+#ifdef OLD_CI_ADDRS /* Need to save space... */
+      case CI_ADDRS:
+        IPCPDEBUG((LOG_INFO, "ipcp_reqci: received ADDRS\n"));
+        if (!ao->neg_addr ||
+            cilen != CILEN_ADDRS) {  /* Check CI length */
+          orc = CONFREJ;    /* Reject CI */
+          break;
+        }
+
+        /*
+         * If he has no address, or if we both have his address but
+         * disagree about it, then NAK it with our idea.
+         * In particular, if we don't know his address, but he does,
+         * then accept it.
+         */
+        GETLONG(tl, p);    /* Parse source address (his) */
+        ciaddr1 = htonl(tl);
+        IPCPDEBUG((LOG_INFO, "his addr %s\n", inet_ntoa(ciaddr1)));
+        if (ciaddr1 != wo->hisaddr
+            && (ciaddr1 == 0 || !wo->accept_remote)) {
+          orc = CONFNAK;
+          if (!reject_if_disagree) {
+            DECPTR(sizeof(u32_t), p);
+            tl = ntohl(wo->hisaddr);
+            PUTLONG(tl, p);
+          }
+        } else if (ciaddr1 == 0 && wo->hisaddr == 0) {
+          /*
+           * If neither we nor he knows his address, reject the option.
+           */
+          orc = CONFREJ;
+          wo->req_addr = 0;  /* don't NAK with 0.0.0.0 later */
+          break;
+        }
+
+        /*
+         * If he doesn't know our address, or if we both have our address
+         * but disagree about it, then NAK it with our idea.
+         */
+        GETLONG(tl, p);    /* Parse desination address (ours) */
+        ciaddr2 = htonl(tl);
+        IPCPDEBUG((LOG_INFO, "our addr %s\n", inet_ntoa(ciaddr2)));
+        if (ciaddr2 != wo->ouraddr) {
+          if (ciaddr2 == 0 || !wo->accept_local) {
+            orc = CONFNAK;
+            if (!reject_if_disagree) {
+              DECPTR(sizeof(u32_t), p);
+              tl = ntohl(wo->ouraddr);
+              PUTLONG(tl, p);
+            }
+          } else {
+            go->ouraddr = ciaddr2;  /* accept peer's idea */
+          }
+        }
+
+        ho->neg_addr = 1;
+        ho->old_addrs = 1;
+        ho->hisaddr = ciaddr1;
+        ho->ouraddr = ciaddr2;
+        break;
+#endif
+
+      case CI_ADDR:
+        if (!ao->neg_addr) {
+          IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR not allowed\n"));
+          orc = CONFREJ;        /* Reject CI */
+          break;
+        } else if (cilen != CILEN_ADDR) {  /* Check CI length */
+          IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR bad len\n"));
+          orc = CONFREJ;        /* Reject CI */
+          break;
+        }
+
+        /*
+         * If he has no address, or if we both have his address but
+         * disagree about it, then NAK it with our idea.
+         * In particular, if we don't know his address, but he does,
+         * then accept it.
+         */
+        GETLONG(tl, p);  /* Parse source address (his) */
+        ciaddr1 = htonl(tl);
+        if (ciaddr1 != wo->hisaddr
+            && (ciaddr1 == 0 || !wo->accept_remote)) {
+          orc = CONFNAK;
+          if (!reject_if_disagree) {
+            DECPTR(sizeof(u32_t), p);
+            tl = ntohl(wo->hisaddr);
+            PUTLONG(tl, p);
+          }
+          IPCPDEBUG((LOG_INFO, "ipcp_reqci: Nak ADDR %s\n", inet_ntoa(ciaddr1)));
+        } else if (ciaddr1 == 0 && wo->hisaddr == 0) {
+          /*
+           * Don't ACK an address of 0.0.0.0 - reject it instead.
+           */
+          IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR %s\n", inet_ntoa(ciaddr1)));
+          orc = CONFREJ;
+          wo->req_addr = 0;  /* don't NAK with 0.0.0.0 later */
+          break;
+        }
+
+        ho->neg_addr = 1;
+        ho->hisaddr = ciaddr1;
+        IPCPDEBUG((LOG_INFO, "ipcp_reqci: ADDR %s\n", inet_ntoa(ciaddr1)));
+        break;
+
+      case CI_MS_DNS1:
+      case CI_MS_DNS2:
+        /* Microsoft primary or secondary DNS request */
+        d = citype == CI_MS_DNS2;
+
+        /* If we do not have a DNS address then we cannot send it */
+        if (ao->dnsaddr[d] == 0 ||
+            cilen != CILEN_ADDR) {  /* Check CI length */
+          IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting DNS%d Request\n", d+1));
+          orc = CONFREJ;        /* Reject CI */
+          break;
+        }
+        GETLONG(tl, p);
+        if (htonl(tl) != ao->dnsaddr[d]) {
+          IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking DNS%d Request %d\n",
+                d+1, inet_ntoa(tl)));
+          DECPTR(sizeof(u32_t), p);
+          tl = ntohl(ao->dnsaddr[d]);
+          PUTLONG(tl, p);
+          orc = CONFNAK;
+        }
+        IPCPDEBUG((LOG_INFO, "ipcp_reqci: received DNS%d Request\n", d+1));
+        break;
+
+      case CI_MS_WINS1:
+      case CI_MS_WINS2:
+        /* Microsoft primary or secondary WINS request */
+        d = citype == CI_MS_WINS2;
+        IPCPDEBUG((LOG_INFO, "ipcp_reqci: received WINS%d Request\n", d+1));
+
+        /* If we do not have a DNS address then we cannot send it */
+        if (ao->winsaddr[d] == 0 ||
+          cilen != CILEN_ADDR) {  /* Check CI length */
+          orc = CONFREJ;      /* Reject CI */
+          break;
+        }
+        GETLONG(tl, p);
+        if (htonl(tl) != ao->winsaddr[d]) {
+          DECPTR(sizeof(u32_t), p);
+          tl = ntohl(ao->winsaddr[d]);
+          PUTLONG(tl, p);
+          orc = CONFNAK;
+        }
+        break;
+
+      case CI_COMPRESSTYPE:
+        if (!ao->neg_vj) {
+          IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE not allowed\n"));
+          orc = CONFREJ;
+          break;
+        } else if (cilen != CILEN_VJ && cilen != CILEN_COMPRESS) {
+          IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE len=%d\n", cilen));
+          orc = CONFREJ;
+          break;
+        }
+        GETSHORT(cishort, p);
+
+        if (!(cishort == IPCP_VJ_COMP ||
+            (cishort == IPCP_VJ_COMP_OLD && cilen == CILEN_COMPRESS))) {
+          IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE %d\n", cishort));
+          orc = CONFREJ;
+          break;
+        }
+
+        ho->neg_vj = 1;
+        ho->vj_protocol = cishort;
+        if (cilen == CILEN_VJ) {
+          GETCHAR(maxslotindex, p);
+          if (maxslotindex > ao->maxslotindex) { 
+            IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ max slot %d\n", maxslotindex));
+            orc = CONFNAK;
+            if (!reject_if_disagree) {
+              DECPTR(1, p);
+              PUTCHAR(ao->maxslotindex, p);
+            }
+          }
+          GETCHAR(cflag, p);
+          if (cflag && !ao->cflag) {
+            IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ cflag %d\n", cflag));
+            orc = CONFNAK;
+            if (!reject_if_disagree) {
+              DECPTR(1, p);
+              PUTCHAR(wo->cflag, p);
+            }
+          }
+          ho->maxslotindex = maxslotindex;
+          ho->cflag = cflag;
+        } else {
+          ho->old_vj = 1;
+          ho->maxslotindex = MAX_SLOTS - 1;
+          ho->cflag = 1;
+        }
+        IPCPDEBUG((LOG_INFO, 
+              "ipcp_reqci: received COMPRESSTYPE p=%d old=%d maxslot=%d cflag=%d\n",
+              ho->vj_protocol, ho->old_vj, ho->maxslotindex, ho->cflag));
+        break;
+
+      default:
+        IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting unknown CI type %d\n", citype));
+        orc = CONFREJ;
+        break;
+    }
+
+endswitch:
+    if (orc == CONFACK &&    /* Good CI */
+        rc != CONFACK) {     /*  but prior CI wasnt? */
+      continue;              /* Don't send this one */
+    }
+
+    if (orc == CONFNAK) {    /* Nak this CI? */
+      if (reject_if_disagree) {  /* Getting fed up with sending NAKs? */
+        IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting too many naks\n"));
+        orc = CONFREJ;       /* Get tough if so */
+      } else {
+        if (rc == CONFREJ) { /* Rejecting prior CI? */
+          continue;          /* Don't send this one */
+        }
+        if (rc == CONFACK) { /* Ack'd all prior CIs? */
+          rc = CONFNAK;      /* Not anymore... */
+          ucp = inp;         /* Backup */
+        }
+      }
+    }
+
+    if (orc == CONFREJ &&    /* Reject this CI */
+        rc != CONFREJ) {  /*  but no prior ones? */
+      rc = CONFREJ;
+      ucp = inp;        /* Backup */
+    }
+    
+    /* Need to move CI? */
+    if (ucp != cip) {
+      BCOPY(cip, ucp, cilen);  /* Move it */
+    }
+
+    /* Update output pointer */
+    INCPTR(cilen, ucp);
+  }
+
+  /*
+   * If we aren't rejecting this packet, and we want to negotiate
+   * their address, and they didn't send their address, then we
+   * send a NAK with a CI_ADDR option appended.  We assume the
+   * input buffer is long enough that we can append the extra
+   * option safely.
+   */
+  if (rc != CONFREJ && !ho->neg_addr &&
+      wo->req_addr && !reject_if_disagree) {
+    IPCPDEBUG((LOG_INFO, "ipcp_reqci: Requesting peer address\n"));
+    if (rc == CONFACK) {
+      rc = CONFNAK;
+      ucp = inp;        /* reset pointer */
+      wo->req_addr = 0;    /* don't ask again */
+    }
+    PUTCHAR(CI_ADDR, ucp);
+    PUTCHAR(CILEN_ADDR, ucp);
+    tl = ntohl(wo->hisaddr);
+    PUTLONG(tl, ucp);
+  }
+
+  *len = (int)(ucp - inp);    /* Compute output length */
+  IPCPDEBUG((LOG_INFO, "ipcp_reqci: returning Configure-%s\n", CODENAME(rc)));
+  return (rc);      /* Return final code */
+}
+
+
+#if 0
+/*
+ * ip_check_options - check that any IP-related options are OK,
+ * and assign appropriate defaults.
+ */
+static void
+ip_check_options(u_long localAddr)
+{
+  ipcp_options *wo = &ipcp_wantoptions[0];
+
+  /*
+   * Load our default IP address but allow the remote host to give us
+   * a new address.
+   */
+  if (wo->ouraddr == 0 && !ppp_settings.disable_defaultip) {
+    wo->accept_local = 1;  /* don't insist on this default value */
+    wo->ouraddr = htonl(localAddr);
+  }
+}
+#endif
+
+
+/*
+ * ipcp_up - IPCP has come UP.
+ *
+ * Configure the IP network interface appropriately and bring it up.
+ */
+static void
+ipcp_up(fsm *f)
+{
+  u32_t mask;
+  ipcp_options *ho = &ipcp_hisoptions[f->unit];
+  ipcp_options *go = &ipcp_gotoptions[f->unit];
+  ipcp_options *wo = &ipcp_wantoptions[f->unit];
+
+  np_up(f->unit, PPP_IP);
+  IPCPDEBUG((LOG_INFO, "ipcp: up\n"));
+
+  /*
+   * We must have a non-zero IP address for both ends of the link.
+   */
+  if (!ho->neg_addr) {
+    ho->hisaddr = wo->hisaddr;
+  }
+
+  if (ho->hisaddr == 0) {
+    IPCPDEBUG((LOG_ERR, "Could not determine remote IP address\n"));
+    ipcp_close(f->unit, "Could not determine remote IP address");
+    return;
+  }
+  if (go->ouraddr == 0) {
+    IPCPDEBUG((LOG_ERR, "Could not determine local IP address\n"));
+    ipcp_close(f->unit, "Could not determine local IP address");
+    return;
+  }
+
+  if (ppp_settings.usepeerdns && (go->dnsaddr[0] || go->dnsaddr[1])) {
+    /*pppGotDNSAddrs(go->dnsaddr[0], go->dnsaddr[1]);*/
+  }
+
+  /*
+   * Check that the peer is allowed to use the IP address it wants.
+   */
+  if (!auth_ip_addr(f->unit, ho->hisaddr)) {
+    IPCPDEBUG((LOG_ERR, "Peer is not authorized to use remote address %s\n",
+        inet_ntoa(ho->hisaddr)));
+    ipcp_close(f->unit, "Unauthorized remote IP address");
+    return;
+  }
+
+  /* set tcp compression */
+  sifvjcomp(f->unit, ho->neg_vj, ho->cflag, ho->maxslotindex);
+
+  /*
+   * Set IP addresses and (if specified) netmask.
+   */
+  mask = GetMask(go->ouraddr);
+
+  if (!sifaddr(f->unit, go->ouraddr, ho->hisaddr, mask, go->dnsaddr[0], go->dnsaddr[1])) {
+    IPCPDEBUG((LOG_WARNING, "sifaddr failed\n"));
+    ipcp_close(f->unit, "Interface configuration failed");
+    return;
+  }
+
+  /* bring the interface up for IP */
+  if (!sifup(f->unit)) {
+    IPCPDEBUG((LOG_WARNING, "sifup failed\n"));
+    ipcp_close(f->unit, "Interface configuration failed");
+    return;
+  }
+
+  sifnpmode(f->unit, PPP_IP, NPMODE_PASS);
+
+  /* assign a default route through the interface if required */
+  if (ipcp_wantoptions[f->unit].default_route) {
+    if (sifdefaultroute(f->unit, go->ouraddr, ho->hisaddr)) {
+      default_route_set[f->unit] = 1;
+    }
+  }
+
+  IPCPDEBUG((LOG_NOTICE, "local  IP address %s\n", inet_ntoa(go->ouraddr)));
+  IPCPDEBUG((LOG_NOTICE, "remote IP address %s\n", inet_ntoa(ho->hisaddr)));
+  if (go->dnsaddr[0]) {
+    IPCPDEBUG((LOG_NOTICE, "primary   DNS address %s\n", inet_ntoa(go->dnsaddr[0])));
+  }
+  if (go->dnsaddr[1]) {
+    IPCPDEBUG((LOG_NOTICE, "secondary DNS address %s\n", inet_ntoa(go->dnsaddr[1])));
+  }
+}
+
+
+/*
+ * ipcp_down - IPCP has gone DOWN.
+ *
+ * Take the IP network interface down, clear its addresses
+ * and delete routes through it.
+ */
+static void
+ipcp_down(fsm *f)
+{
+  IPCPDEBUG((LOG_INFO, "ipcp: down\n"));
+  np_down(f->unit, PPP_IP);
+  sifvjcomp(f->unit, 0, 0, 0);
+
+  sifdown(f->unit);
+  ipcp_clear_addrs(f->unit);
+}
+
+
+/*
+ * ipcp_clear_addrs() - clear the interface addresses, routes, etc.
+ */
+static void
+ipcp_clear_addrs(int unit)
+{
+  u32_t ouraddr, hisaddr;
+
+  ouraddr = ipcp_gotoptions[unit].ouraddr;
+  hisaddr = ipcp_hisoptions[unit].hisaddr;
+  if (default_route_set[unit]) {
+    cifdefaultroute(unit, ouraddr, hisaddr);
+    default_route_set[unit] = 0;
+  }
+  cifaddr(unit, ouraddr, hisaddr);
+}
+
+
+/*
+ * ipcp_finished - possibly shut down the lower layers.
+ */
+static void
+ipcp_finished(fsm *f)
+{
+  np_finished(f->unit, PPP_IP);
+}
+
+#if 0
+static int
+ipcp_printpkt(u_char *p, int plen, void (*printer) (void *, char *, ...), void *arg)
+{
+  LWIP_UNUSED_ARG(p);
+  LWIP_UNUSED_ARG(plen);
+  LWIP_UNUSED_ARG(printer);
+  LWIP_UNUSED_ARG(arg);
+  return 0;
+}
+
+/*
+ * ip_active_pkt - see if this IP packet is worth bringing the link up for.
+ * We don't bring the link up for IP fragments or for TCP FIN packets
+ * with no data.
+ */
+#define IP_HDRLEN   20  /* bytes */
+#define IP_OFFMASK  0x1fff
+#define IPPROTO_TCP 6
+#define TCP_HDRLEN  20
+#define TH_FIN      0x01
+
+/*
+ * We use these macros because the IP header may be at an odd address,
+ * and some compilers might use word loads to get th_off or ip_hl.
+ */
+
+#define net_short(x)    (((x)[0] << 8) + (x)[1])
+#define get_iphl(x)     (((unsigned char *)(x))[0] & 0xF)
+#define get_ipoff(x)    net_short((unsigned char *)(x) + 6)
+#define get_ipproto(x)  (((unsigned char *)(x))[9])
+#define get_tcpoff(x)   (((unsigned char *)(x))[12] >> 4)
+#define get_tcpflags(x) (((unsigned char *)(x))[13])
+
+static int
+ip_active_pkt(u_char *pkt, int len)
+{
+  u_char *tcp;
+  int hlen;
+
+  len -= PPP_HDRLEN;
+  pkt += PPP_HDRLEN;
+  if (len < IP_HDRLEN) {
+    return 0;
+  }
+  if ((get_ipoff(pkt) & IP_OFFMASK) != 0) {
+    return 0;
+  }
+  if (get_ipproto(pkt) != IPPROTO_TCP) {
+    return 1;
+  }
+  hlen = get_iphl(pkt) * 4;
+  if (len < hlen + TCP_HDRLEN) {
+    return 0;
+  }
+  tcp = pkt + hlen;
+  if ((get_tcpflags(tcp) & TH_FIN) != 0 && len == hlen + get_tcpoff(tcp) * 4) {
+    return 0;
+  }
+  return 1;
+}
+#endif
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/ipcp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/ipcp.h
new file mode 100644
index 0000000..dfcf4fb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/ipcp.h
@@ -0,0 +1,124 @@
+/*****************************************************************************
+* ipcp.h -  PPP IP NCP: Internet Protocol Network Control Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * ipcp.h - IP Control Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: ipcp.h,v 1.3 2007/12/19 20:47:23 fbernon Exp $
+ */
+
+#ifndef IPCP_H
+#define IPCP_H
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+/*
+ * Options.
+ */
+#define CI_ADDRS            1      /* IP Addresses */
+#define CI_COMPRESSTYPE     2      /* Compression Type */
+#define CI_ADDR             3
+
+#define CI_MS_WINS1         128    /* Primary WINS value */
+#define CI_MS_DNS1          129    /* Primary DNS value */
+#define CI_MS_WINS2         130    /* Secondary WINS value */
+#define CI_MS_DNS2          131    /* Secondary DNS value */
+
+#define IPCP_VJMODE_OLD     1      /* "old" mode (option # = 0x0037) */
+#define IPCP_VJMODE_RFC1172 2      /* "old-rfc"mode (option # = 0x002d) */
+#define IPCP_VJMODE_RFC1332 3      /* "new-rfc"mode (option # = 0x002d, */
+                                   /*  maxslot and slot number compression) */
+
+#define IPCP_VJ_COMP        0x002d /* current value for VJ compression option */
+#define IPCP_VJ_COMP_OLD    0x0037 /* "old" (i.e, broken) value for VJ */
+                                   /* compression option */ 
+
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+typedef struct ipcp_options {
+  u_int   neg_addr      : 1; /* Negotiate IP Address? */
+  u_int   old_addrs     : 1; /* Use old (IP-Addresses) option? */
+  u_int   req_addr      : 1; /* Ask peer to send IP address? */
+  u_int   default_route : 1; /* Assign default route through interface? */
+  u_int   proxy_arp     : 1; /* Make proxy ARP entry for peer? */
+  u_int   neg_vj        : 1; /* Van Jacobson Compression? */
+  u_int   old_vj        : 1; /* use old (short) form of VJ option? */
+  u_int   accept_local  : 1; /* accept peer's value for ouraddr */
+  u_int   accept_remote : 1; /* accept peer's value for hisaddr */
+  u_int   req_dns1      : 1; /* Ask peer to send primary DNS address? */
+  u_int   req_dns2      : 1; /* Ask peer to send secondary DNS address? */
+  u_short vj_protocol;       /* protocol value to use in VJ option */
+  u_char  maxslotindex;      /* VJ slots - 1. */
+  u_char  cflag;             /* VJ slot compression flag. */
+  u32_t   ouraddr, hisaddr;  /* Addresses in NETWORK BYTE ORDER */
+  u32_t   dnsaddr[2];        /* Primary and secondary MS DNS entries */
+  u32_t   winsaddr[2];       /* Primary and secondary MS WINS entries */
+} ipcp_options;
+
+
+/*****************************
+*** PUBLIC DATA STRUCTURES ***
+*****************************/
+
+extern fsm ipcp_fsm[];
+extern ipcp_options ipcp_wantoptions[];
+extern ipcp_options ipcp_gotoptions[];
+extern ipcp_options ipcp_allowoptions[];
+extern ipcp_options ipcp_hisoptions[];
+
+extern struct protent ipcp_protent;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+#endif /* IPCP_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/lcp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/lcp.c
new file mode 100644
index 0000000..85a0add
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/lcp.c
@@ -0,0 +1,2035 @@
+/*****************************************************************************
+* lcp.c - Network Link Control Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-01 Guy Lancaster , Global Election Systems Inc.
+*   Original.
+*****************************************************************************/
+
+/*
+ * lcp.c - PPP Link Control Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+ 
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "fsm.h"
+#include "chap.h"
+#include "magic.h"
+#include "auth.h"
+#include "lcp.h"
+
+#include 
+
+#if PPPOE_SUPPORT
+#include "netif/ppp_oe.h"
+#else
+#define PPPOE_MAXMTU PPP_MAXMRU
+#endif
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+/*
+ * Length of each type of configuration option (in octets)
+ */
+#define CILEN_VOID  2
+#define CILEN_CHAR  3
+#define CILEN_SHORT 4 /* CILEN_VOID + sizeof(short) */
+#define CILEN_CHAP  5 /* CILEN_VOID + sizeof(short) + 1 */
+#define CILEN_LONG  6 /* CILEN_VOID + sizeof(long) */
+#define CILEN_LQR   8 /* CILEN_VOID + sizeof(short) + sizeof(long) */
+#define CILEN_CBCP  3
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Callbacks for fsm code.  (CI = Configuration Information)
+ */
+static void lcp_resetci (fsm*);                   /* Reset our CI */
+static int  lcp_cilen (fsm*);                     /* Return length of our CI */
+static void lcp_addci (fsm*, u_char*, int*);      /* Add our CI to pkt */
+static int  lcp_ackci (fsm*, u_char*, int);       /* Peer ack'd our CI */
+static int  lcp_nakci (fsm*, u_char*, int);       /* Peer nak'd our CI */
+static int  lcp_rejci (fsm*, u_char*, int);       /* Peer rej'd our CI */
+static int  lcp_reqci (fsm*, u_char*, int*, int); /* Rcv peer CI */
+static void lcp_up (fsm*);                        /* We're UP */
+static void lcp_down (fsm*);                      /* We're DOWN */
+static void lcp_starting (fsm*);                  /* We need lower layer up */
+static void lcp_finished (fsm*);                  /* We need lower layer down */
+static int  lcp_extcode (fsm*, int, u_char, u_char*, int);
+
+static void lcp_rprotrej (fsm*, u_char*, int);
+
+/*
+ * routines to send LCP echos to peer
+ */
+static void lcp_echo_lowerup (int);
+static void lcp_echo_lowerdown (int);
+static void LcpEchoTimeout (void*);
+static void lcp_received_echo_reply (fsm*, int, u_char*, int);
+static void LcpSendEchoRequest (fsm*);
+static void LcpLinkFailure (fsm*);
+static void LcpEchoCheck (fsm*);
+
+/*
+ * Protocol entry points.
+ * Some of these are called directly.
+ */
+static void lcp_input (int, u_char *, int);
+static void lcp_protrej (int);
+
+#define CODENAME(x) ((x) == CONFACK ? "ACK" : (x) == CONFNAK ? "NAK" : "REJ")
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+/* global vars */
+LinkPhase lcp_phase[NUM_PPP];          /* Phase of link session (RFC 1661) */
+lcp_options lcp_wantoptions[NUM_PPP];  /* Options that we want to request */
+lcp_options lcp_gotoptions[NUM_PPP];   /* Options that peer ack'd */
+lcp_options lcp_allowoptions[NUM_PPP]; /* Options we allow peer to request */
+lcp_options lcp_hisoptions[NUM_PPP];   /* Options that we ack'd */
+ext_accm xmit_accm[NUM_PPP];           /* extended transmit ACCM */
+
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static fsm lcp_fsm[NUM_PPP];                            /* LCP fsm structure (global)*/
+static u_int lcp_echo_interval      = LCP_ECHOINTERVAL; /* Interval between LCP echo-requests */
+static u_int lcp_echo_fails         = LCP_MAXECHOFAILS; /* Tolerance to unanswered echo-requests */
+static u32_t lcp_echos_pending      = 0;                /* Number of outstanding echo msgs */
+static u32_t lcp_echo_number        = 0;                /* ID number of next echo frame */
+static u32_t lcp_echo_timer_running = 0;                /* TRUE if a timer is running */
+
+static u_char nak_buffer[PPP_MRU]; /* where we construct a nak packet */
+
+static fsm_callbacks lcp_callbacks = { /* LCP callback routines */
+  lcp_resetci,  /* Reset our Configuration Information */
+  lcp_cilen,    /* Length of our Configuration Information */
+  lcp_addci,    /* Add our Configuration Information */
+  lcp_ackci,    /* ACK our Configuration Information */
+  lcp_nakci,    /* NAK our Configuration Information */
+  lcp_rejci,    /* Reject our Configuration Information */
+  lcp_reqci,    /* Request peer's Configuration Information */
+  lcp_up,       /* Called when fsm reaches LS_OPENED state */
+  lcp_down,     /* Called when fsm leaves LS_OPENED state */
+  lcp_starting, /* Called when we want the lower layer up */
+  lcp_finished, /* Called when we want the lower layer down */
+  NULL,         /* Called when Protocol-Reject received */
+  NULL,         /* Retransmission is necessary */
+  lcp_extcode,  /* Called to handle LCP-specific codes */
+  "LCP"         /* String name of protocol */
+};
+
+struct protent lcp_protent = {
+    PPP_LCP,
+    lcp_init,
+    lcp_input,
+    lcp_protrej,
+    lcp_lowerup,
+    lcp_lowerdown,
+    lcp_open,
+    lcp_close,
+#if 0
+    lcp_printpkt,
+    NULL,
+#endif
+    1,
+    "LCP",
+#if 0
+    NULL,
+    NULL,
+    NULL
+#endif
+};
+
+int lcp_loopbackfail = DEFLOOPBACKFAIL;
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * lcp_init - Initialize LCP.
+ */
+void
+lcp_init(int unit)
+{
+  fsm         *f  = &lcp_fsm[unit];
+  lcp_options *wo = &lcp_wantoptions[unit];
+  lcp_options *ao = &lcp_allowoptions[unit];
+  
+  f->unit      = unit;
+  f->protocol  = PPP_LCP;
+  f->callbacks = &lcp_callbacks;
+  
+  fsm_init(f);
+  
+  wo->passive           = 0;
+  wo->silent            = 0;
+  wo->restart           = 0;               /* Set to 1 in kernels or multi-line implementations */
+  wo->neg_mru           = 1;
+  wo->mru               = PPP_DEFMRU;
+  wo->neg_asyncmap      = 1;
+  wo->asyncmap          = 0x00000000l;     /* Assume don't need to escape any ctl chars. */
+  wo->neg_chap          = 0;               /* Set to 1 on server */
+  wo->neg_upap          = 0;               /* Set to 1 on server */
+  wo->chap_mdtype       = CHAP_DIGEST_MD5;
+  wo->neg_magicnumber   = 1;
+  wo->neg_pcompression  = 1;
+  wo->neg_accompression = 1;
+  wo->neg_lqr           = 0;               /* no LQR implementation yet */
+  wo->neg_cbcp          = 0;
+  
+  ao->neg_mru           = 1;
+  ao->mru               = PPP_MAXMRU;
+  ao->neg_asyncmap      = 1;
+  ao->asyncmap          = 0x00000000l;     /* Assume don't need to escape any ctl chars. */
+  ao->neg_chap          = (CHAP_SUPPORT != 0);
+  ao->chap_mdtype       = CHAP_DIGEST_MD5;
+  ao->neg_upap          = (PAP_SUPPORT != 0);
+  ao->neg_magicnumber   = 1;
+  ao->neg_pcompression  = 1;
+  ao->neg_accompression = 1;
+  ao->neg_lqr           = 0;               /* no LQR implementation yet */
+  ao->neg_cbcp          = (CBCP_SUPPORT != 0);
+
+  /* 
+   * Set transmit escape for the flag and escape characters plus anything
+   * set for the allowable options.
+   */
+  memset(xmit_accm[unit], 0, sizeof(xmit_accm[0]));
+  xmit_accm[unit][15] = 0x60;
+  xmit_accm[unit][0]  = (u_char)((ao->asyncmap        & 0xFF));
+  xmit_accm[unit][1]  = (u_char)((ao->asyncmap >> 8)  & 0xFF);
+  xmit_accm[unit][2]  = (u_char)((ao->asyncmap >> 16) & 0xFF);
+  xmit_accm[unit][3]  = (u_char)((ao->asyncmap >> 24) & 0xFF);
+  LCPDEBUG((LOG_INFO, "lcp_init: xmit_accm=%X %X %X %X\n",
+        xmit_accm[unit][0],
+        xmit_accm[unit][1],
+        xmit_accm[unit][2],
+        xmit_accm[unit][3]));
+  
+  lcp_phase[unit] = PHASE_INITIALIZE;
+}
+
+
+/*
+ * lcp_open - LCP is allowed to come up.
+ */
+void
+lcp_open(int unit)
+{
+  fsm         *f  = &lcp_fsm[unit];
+  lcp_options *wo = &lcp_wantoptions[unit];
+
+  f->flags = 0;
+  if (wo->passive) {
+    f->flags |= OPT_PASSIVE;
+  }
+  if (wo->silent) {
+    f->flags |= OPT_SILENT;
+  }
+  fsm_open(f);
+
+  lcp_phase[unit] = PHASE_ESTABLISH;
+}
+
+
+/*
+ * lcp_close - Take LCP down.
+ */
+void
+lcp_close(int unit, char *reason)
+{
+  fsm *f = &lcp_fsm[unit];
+
+  if (lcp_phase[unit] != PHASE_DEAD) {
+    lcp_phase[unit] = PHASE_TERMINATE;
+  }
+  if (f->state == LS_STOPPED && f->flags & (OPT_PASSIVE|OPT_SILENT)) {
+    /*
+     * This action is not strictly according to the FSM in RFC1548,
+     * but it does mean that the program terminates if you do an
+     * lcp_close() in passive/silent mode when a connection hasn't
+     * been established.
+     */
+    f->state = LS_CLOSED;
+    lcp_finished(f);
+  } else {
+    fsm_close(&lcp_fsm[unit], reason);
+  }
+}
+
+
+/*
+ * lcp_lowerup - The lower layer is up.
+ */
+void
+lcp_lowerup(int unit)
+{
+  lcp_options *wo = &lcp_wantoptions[unit];
+
+  /*
+   * Don't use A/C or protocol compression on transmission,
+   * but accept A/C and protocol compressed packets
+   * if we are going to ask for A/C and protocol compression.
+   */
+  ppp_set_xaccm(unit, &xmit_accm[unit]);
+  ppp_send_config(unit, PPP_MRU, 0xffffffffl, 0, 0);
+  ppp_recv_config(unit, PPP_MRU, 0x00000000l,
+  wo->neg_pcompression, wo->neg_accompression);
+  peer_mru[unit] = PPP_MRU;
+  lcp_allowoptions[unit].asyncmap = (u_long)xmit_accm[unit][0]
+                                 | ((u_long)xmit_accm[unit][1] << 8)
+                                 | ((u_long)xmit_accm[unit][2] << 16)
+                                 | ((u_long)xmit_accm[unit][3] << 24);
+  LCPDEBUG((LOG_INFO, "lcp_lowerup: asyncmap=%X %X %X %X\n",
+            xmit_accm[unit][3],
+            xmit_accm[unit][2],
+            xmit_accm[unit][1],
+            xmit_accm[unit][0]));
+
+  fsm_lowerup(&lcp_fsm[unit]);
+}
+
+
+/*
+ * lcp_lowerdown - The lower layer is down.
+ */
+void
+lcp_lowerdown(int unit)
+{
+  fsm_lowerdown(&lcp_fsm[unit]);
+}
+
+/*
+ * lcp_sprotrej - Send a Protocol-Reject for some protocol.
+ */
+void
+lcp_sprotrej(int unit, u_char *p, int len)
+{
+  /*
+   * Send back the protocol and the information field of the
+   * rejected packet.  We only get here if LCP is in the LS_OPENED state.
+   */
+
+  fsm_sdata(&lcp_fsm[unit], PROTREJ, ++lcp_fsm[unit].id, p, len);
+}
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * lcp_input - Input LCP packet.
+ */
+static void
+lcp_input(int unit, u_char *p, int len)
+{
+  fsm *f = &lcp_fsm[unit];
+
+  fsm_input(f, p, len);
+}
+
+
+/*
+ * lcp_extcode - Handle a LCP-specific code.
+ */
+static int
+lcp_extcode(fsm *f, int code, u_char id, u_char *inp, int len)
+{
+  u_char *magp;
+
+  switch( code ){
+    case PROTREJ:
+      lcp_rprotrej(f, inp, len);
+      break;
+  
+    case ECHOREQ:
+      if (f->state != LS_OPENED) {
+        break;
+      }
+      LCPDEBUG((LOG_INFO, "lcp: Echo-Request, Rcvd id %d\n", id));
+      magp = inp;
+      PUTLONG(lcp_gotoptions[f->unit].magicnumber, magp);
+      fsm_sdata(f, ECHOREP, id, inp, len);
+      break;
+
+    case ECHOREP:
+      lcp_received_echo_reply(f, id, inp, len);
+      break;
+    
+    case DISCREQ:
+      break;
+    
+    default:
+      return 0;
+  }
+  return 1;
+}
+
+
+/*
+ * lcp_rprotrej - Receive an Protocol-Reject.
+ *
+ * Figure out which protocol is rejected and inform it.
+ */
+static void
+lcp_rprotrej(fsm *f, u_char *inp, int len)
+{
+  int i;
+  struct protent *protp;
+  u_short prot;
+
+  if (len < sizeof (u_short)) {
+    LCPDEBUG((LOG_INFO, "lcp_rprotrej: Rcvd short Protocol-Reject packet!\n"));
+    return;
+  }
+
+  GETSHORT(prot, inp);
+
+  LCPDEBUG((LOG_INFO, "lcp_rprotrej: Rcvd Protocol-Reject packet for %x!\n", prot));
+
+  /*
+   * Protocol-Reject packets received in any state other than the LCP
+   * LS_OPENED state SHOULD be silently discarded.
+   */
+  if( f->state != LS_OPENED ) {
+    LCPDEBUG((LOG_INFO, "Protocol-Reject discarded: LCP in state %d\n", f->state));
+    return;
+  }
+
+  /*
+   * Upcall the proper Protocol-Reject routine.
+   */
+  for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+    if (protp->protocol == prot && protp->enabled_flag) {
+      (*protp->protrej)(f->unit);
+      return;
+    }
+  }
+
+  LCPDEBUG((LOG_WARNING, "Protocol-Reject for unsupported protocol 0x%x\n", prot));
+}
+
+
+/*
+ * lcp_protrej - A Protocol-Reject was received.
+ */
+static void
+lcp_protrej(int unit)
+{
+  LWIP_UNUSED_ARG(unit);
+  /*
+   * Can't reject LCP!
+   */
+  LCPDEBUG((LOG_WARNING, "lcp_protrej: Received Protocol-Reject for LCP!\n"));
+  fsm_protreject(&lcp_fsm[unit]);
+}
+
+
+/*
+ * lcp_resetci - Reset our CI.
+ */
+static void
+lcp_resetci(fsm *f)
+{
+  lcp_wantoptions[f->unit].magicnumber = magic();
+  lcp_wantoptions[f->unit].numloops = 0;
+  lcp_gotoptions[f->unit] = lcp_wantoptions[f->unit];
+  peer_mru[f->unit] = PPP_MRU;
+  auth_reset(f->unit);
+}
+
+
+/*
+ * lcp_cilen - Return length of our CI.
+ */
+static int lcp_cilen(fsm *f)
+{
+  lcp_options *go = &lcp_gotoptions[f->unit];
+
+#define LENCIVOID(neg)  ((neg) ? CILEN_VOID : 0)
+#define LENCICHAP(neg)  ((neg) ? CILEN_CHAP : 0)
+#define LENCISHORT(neg) ((neg) ? CILEN_SHORT : 0)
+#define LENCILONG(neg)  ((neg) ? CILEN_LONG : 0)
+#define LENCILQR(neg)   ((neg) ? CILEN_LQR: 0)
+#define LENCICBCP(neg)  ((neg) ? CILEN_CBCP: 0)
+  /*
+   * NB: we only ask for one of CHAP and UPAP, even if we will
+   * accept either.
+   */
+  return (LENCISHORT(go->neg_mru && go->mru != PPP_DEFMRU) +
+          LENCILONG(go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) +
+          LENCICHAP(go->neg_chap) +
+          LENCISHORT(!go->neg_chap && go->neg_upap) +
+          LENCILQR(go->neg_lqr) +
+          LENCICBCP(go->neg_cbcp) +
+          LENCILONG(go->neg_magicnumber) +
+          LENCIVOID(go->neg_pcompression) +
+          LENCIVOID(go->neg_accompression));
+}
+
+
+/*
+ * lcp_addci - Add our desired CIs to a packet.
+ */
+static void
+lcp_addci(fsm *f, u_char *ucp, int *lenp)
+{
+  lcp_options *go = &lcp_gotoptions[f->unit];
+  u_char *start_ucp = ucp;
+
+#define ADDCIVOID(opt, neg) \
+  if (neg) { \
+    LCPDEBUG((LOG_INFO, "lcp_addci: opt=%d\n", opt)); \
+    PUTCHAR(opt, ucp); \
+    PUTCHAR(CILEN_VOID, ucp); \
+  }
+#define ADDCISHORT(opt, neg, val) \
+  if (neg) { \
+    LCPDEBUG((LOG_INFO, "lcp_addci: INT opt=%d %X\n", opt, val)); \
+    PUTCHAR(opt, ucp); \
+    PUTCHAR(CILEN_SHORT, ucp); \
+    PUTSHORT(val, ucp); \
+  }
+#define ADDCICHAP(opt, neg, val, digest) \
+  if (neg) { \
+    LCPDEBUG((LOG_INFO, "lcp_addci: CHAP opt=%d %X\n", opt, val)); \
+    PUTCHAR(opt, ucp); \
+    PUTCHAR(CILEN_CHAP, ucp); \
+    PUTSHORT(val, ucp); \
+    PUTCHAR(digest, ucp); \
+  }
+#define ADDCILONG(opt, neg, val) \
+  if (neg) { \
+    LCPDEBUG((LOG_INFO, "lcp_addci: L opt=%d %lX\n", opt, val)); \
+    PUTCHAR(opt, ucp); \
+    PUTCHAR(CILEN_LONG, ucp); \
+    PUTLONG(val, ucp); \
+  }
+#define ADDCILQR(opt, neg, val) \
+  if (neg) { \
+    LCPDEBUG((LOG_INFO, "lcp_addci: LQR opt=%d %lX\n", opt, val)); \
+    PUTCHAR(opt, ucp); \
+    PUTCHAR(CILEN_LQR, ucp); \
+    PUTSHORT(PPP_LQR, ucp); \
+    PUTLONG(val, ucp); \
+  }
+#define ADDCICHAR(opt, neg, val) \
+  if (neg) { \
+    LCPDEBUG((LOG_INFO, "lcp_addci: CHAR opt=%d %X '%z'\n", opt, val, val)); \
+    PUTCHAR(opt, ucp); \
+    PUTCHAR(CILEN_CHAR, ucp); \
+    PUTCHAR(val, ucp); \
+  }
+
+  ADDCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru);
+  ADDCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl, go->asyncmap);
+  ADDCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype);
+  ADDCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP);
+  ADDCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period);
+  ADDCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT);
+  ADDCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber);
+  ADDCIVOID(CI_PCOMPRESSION, go->neg_pcompression);
+  ADDCIVOID(CI_ACCOMPRESSION, go->neg_accompression);
+
+  if (ucp - start_ucp != *lenp) {
+    /* this should never happen, because peer_mtu should be 1500 */
+    LCPDEBUG((LOG_ERR, "Bug in lcp_addci: wrong length\n"));
+  }
+}
+
+
+/*
+ * lcp_ackci - Ack our CIs.
+ * This should not modify any state if the Ack is bad.
+ *
+ * Returns:
+ *  0 - Ack was bad.
+ *  1 - Ack was good.
+ */
+static int
+lcp_ackci(fsm *f, u_char *p, int len)
+{
+  lcp_options *go = &lcp_gotoptions[f->unit];
+  u_char cilen, citype, cichar;
+  u_short cishort;
+  u32_t cilong;
+
+  /*
+   * CIs must be in exactly the same order that we sent.
+   * Check packet length and CI length at each step.
+   * If we find any deviations, then this packet is bad.
+   */
+#define ACKCIVOID(opt, neg) \
+  if (neg) { \
+    if ((len -= CILEN_VOID) < 0) \
+      goto bad; \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != CILEN_VOID || citype != opt) \
+      goto bad; \
+  }
+#define ACKCISHORT(opt, neg, val) \
+  if (neg) { \
+    if ((len -= CILEN_SHORT) < 0) \
+      goto bad; \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != CILEN_SHORT || citype != opt) \
+      goto bad; \
+    GETSHORT(cishort, p); \
+    if (cishort != val) \
+      goto bad; \
+  }
+#define ACKCICHAR(opt, neg, val) \
+  if (neg) { \
+    if ((len -= CILEN_CHAR) < 0) \
+      goto bad; \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != CILEN_CHAR || citype != opt) \
+      goto bad; \
+    GETCHAR(cichar, p); \
+    if (cichar != val) \
+      goto bad; \
+  }
+#define ACKCICHAP(opt, neg, val, digest) \
+  if (neg) { \
+    if ((len -= CILEN_CHAP) < 0) \
+      goto bad; \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != CILEN_CHAP || citype != opt) \
+      goto bad; \
+    GETSHORT(cishort, p); \
+    if (cishort != val) \
+      goto bad; \
+    GETCHAR(cichar, p); \
+    if (cichar != digest) \
+      goto bad; \
+  }
+#define ACKCILONG(opt, neg, val) \
+  if (neg) { \
+    if ((len -= CILEN_LONG) < 0) \
+      goto bad; \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != CILEN_LONG ||  citype != opt) \
+      goto bad; \
+    GETLONG(cilong, p); \
+    if (cilong != val) \
+      goto bad; \
+  }
+#define ACKCILQR(opt, neg, val) \
+  if (neg) { \
+    if ((len -= CILEN_LQR) < 0) \
+      goto bad; \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != CILEN_LQR || citype != opt) \
+      goto bad; \
+    GETSHORT(cishort, p); \
+    if (cishort != PPP_LQR) \
+      goto bad; \
+    GETLONG(cilong, p); \
+    if (cilong != val) \
+      goto bad; \
+  }
+
+  ACKCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru);
+  ACKCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl, go->asyncmap);
+  ACKCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype);
+  ACKCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP);
+  ACKCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period);
+  ACKCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT);
+  ACKCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber);
+  ACKCIVOID(CI_PCOMPRESSION, go->neg_pcompression);
+  ACKCIVOID(CI_ACCOMPRESSION, go->neg_accompression);
+
+  /*
+   * If there are any remaining CIs, then this packet is bad.
+   */
+  if (len != 0) {
+    goto bad;
+  }
+  LCPDEBUG((LOG_INFO, "lcp_acki: Ack\n"));
+  return (1);
+bad:
+  LCPDEBUG((LOG_WARNING, "lcp_acki: received bad Ack!\n"));
+  return (0);
+}
+
+
+/*
+ * lcp_nakci - Peer has sent a NAK for some of our CIs.
+ * This should not modify any state if the Nak is bad
+ * or if LCP is in the LS_OPENED state.
+ *
+ * Returns:
+ *  0 - Nak was bad.
+ *  1 - Nak was good.
+ */
+static int
+lcp_nakci(fsm *f, u_char *p, int len)
+{
+  lcp_options *go = &lcp_gotoptions[f->unit];
+  lcp_options *wo = &lcp_wantoptions[f->unit];
+  u_char citype, cichar, *next;
+  u_short cishort;
+  u32_t cilong;
+  lcp_options no;     /* options we've seen Naks for */
+  lcp_options try;    /* options to request next time */
+  int looped_back = 0;
+  int cilen;
+
+  BZERO(&no, sizeof(no));
+  try = *go;
+
+  /*
+   * Any Nak'd CIs must be in exactly the same order that we sent.
+   * Check packet length and CI length at each step.
+   * If we find any deviations, then this packet is bad.
+   */
+#define NAKCIVOID(opt, neg, code) \
+  if (go->neg && \
+      len >= CILEN_VOID && \
+      p[1] == CILEN_VOID && \
+      p[0] == opt) { \
+    len -= CILEN_VOID; \
+    INCPTR(CILEN_VOID, p); \
+    no.neg = 1; \
+    code \
+  }
+#define NAKCICHAP(opt, neg, code) \
+  if (go->neg && \
+      len >= CILEN_CHAP && \
+      p[1] == CILEN_CHAP && \
+      p[0] == opt) { \
+    len -= CILEN_CHAP; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    GETCHAR(cichar, p); \
+    no.neg = 1; \
+    code \
+  }
+#define NAKCICHAR(opt, neg, code) \
+  if (go->neg && \
+      len >= CILEN_CHAR && \
+      p[1] == CILEN_CHAR && \
+      p[0] == opt) { \
+    len -= CILEN_CHAR; \
+    INCPTR(2, p); \
+    GETCHAR(cichar, p); \
+    no.neg = 1; \
+    code \
+  }
+#define NAKCISHORT(opt, neg, code) \
+  if (go->neg && \
+      len >= CILEN_SHORT && \
+      p[1] == CILEN_SHORT && \
+      p[0] == opt) { \
+    len -= CILEN_SHORT; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    no.neg = 1; \
+    code \
+  }
+#define NAKCILONG(opt, neg, code) \
+  if (go->neg && \
+      len >= CILEN_LONG && \
+      p[1] == CILEN_LONG && \
+      p[0] == opt) { \
+    len -= CILEN_LONG; \
+    INCPTR(2, p); \
+    GETLONG(cilong, p); \
+    no.neg = 1; \
+    code \
+  }
+#define NAKCILQR(opt, neg, code) \
+  if (go->neg && \
+      len >= CILEN_LQR && \
+      p[1] == CILEN_LQR && \
+      p[0] == opt) { \
+    len -= CILEN_LQR; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    GETLONG(cilong, p); \
+    no.neg = 1; \
+    code \
+  }
+
+  /*
+   * We don't care if they want to send us smaller packets than
+   * we want.  Therefore, accept any MRU less than what we asked for,
+   * but then ignore the new value when setting the MRU in the kernel.
+   * If they send us a bigger MRU than what we asked, accept it, up to
+   * the limit of the default MRU we'd get if we didn't negotiate.
+   */
+  if (go->neg_mru && go->mru != PPP_DEFMRU) {
+    NAKCISHORT(CI_MRU, neg_mru,
+      if (cishort <= wo->mru || cishort < PPP_DEFMRU) {
+        try.mru = cishort;
+      }
+    );
+  }
+
+  /*
+   * Add any characters they want to our (receive-side) asyncmap.
+   */
+  if (go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) {
+    NAKCILONG(CI_ASYNCMAP, neg_asyncmap,
+      try.asyncmap = go->asyncmap | cilong;
+    );
+  }
+
+  /*
+   * If they've nak'd our authentication-protocol, check whether
+   * they are proposing a different protocol, or a different
+   * hash algorithm for CHAP.
+   */
+  if ((go->neg_chap || go->neg_upap)
+      && len >= CILEN_SHORT
+      && p[0] == CI_AUTHTYPE && p[1] >= CILEN_SHORT && p[1] <= len) {
+    cilen = p[1];
+    len -= cilen;
+    no.neg_chap = go->neg_chap;
+    no.neg_upap = go->neg_upap;
+    INCPTR(2, p);
+    GETSHORT(cishort, p);
+    if (cishort == PPP_PAP && cilen == CILEN_SHORT) {
+      /*
+       * If we were asking for CHAP, they obviously don't want to do it.
+       * If we weren't asking for CHAP, then we were asking for PAP,
+       * in which case this Nak is bad.
+       */
+      if (!go->neg_chap) {
+        goto bad;
+      }
+      try.neg_chap = 0;
+    
+    } else if (cishort == PPP_CHAP && cilen == CILEN_CHAP) {
+      GETCHAR(cichar, p);
+      if (go->neg_chap) {
+        /*
+         * We were asking for CHAP/MD5; they must want a different
+         * algorithm.  If they can't do MD5, we'll have to stop
+         * asking for CHAP.
+         */
+        if (cichar != go->chap_mdtype) {
+          try.neg_chap = 0;
+        }
+      } else {
+        /*
+         * Stop asking for PAP if we were asking for it.
+         */
+        try.neg_upap = 0;
+      }
+    
+    } else {
+      /*
+       * We don't recognize what they're suggesting.
+       * Stop asking for what we were asking for.
+       */
+      if (go->neg_chap) {
+        try.neg_chap = 0;
+      } else {
+        try.neg_upap = 0;
+      }
+      p += cilen - CILEN_SHORT;
+    }
+  }
+
+  /*
+   * If they can't cope with our link quality protocol, we'll have
+   * to stop asking for LQR.  We haven't got any other protocol.
+   * If they Nak the reporting period, take their value XXX ?
+   */
+  NAKCILQR(CI_QUALITY, neg_lqr,
+    if (cishort != PPP_LQR) {
+      try.neg_lqr = 0;
+    } else {
+      try.lqr_period = cilong;
+    }
+  );
+
+  /*
+   * Only implementing CBCP...not the rest of the callback options
+   */
+  NAKCICHAR(CI_CALLBACK, neg_cbcp,
+    try.neg_cbcp = 0;
+  );
+
+  /*
+   * Check for a looped-back line.
+   */
+  NAKCILONG(CI_MAGICNUMBER, neg_magicnumber,
+    try.magicnumber = magic();
+    looped_back = 1;
+  );
+
+  /*
+   * Peer shouldn't send Nak for protocol compression or
+   * address/control compression requests; they should send
+   * a Reject instead.  If they send a Nak, treat it as a Reject.
+   */
+  NAKCIVOID(CI_PCOMPRESSION, neg_pcompression,
+    try.neg_pcompression = 0;
+  );
+  NAKCIVOID(CI_ACCOMPRESSION, neg_accompression,
+    try.neg_accompression = 0;
+  );
+
+  /*
+   * There may be remaining CIs, if the peer is requesting negotiation
+   * on an option that we didn't include in our request packet.
+   * If we see an option that we requested, or one we've already seen
+   * in this packet, then this packet is bad.
+   * If we wanted to respond by starting to negotiate on the requested
+   * option(s), we could, but we don't, because except for the
+   * authentication type and quality protocol, if we are not negotiating
+   * an option, it is because we were told not to.
+   * For the authentication type, the Nak from the peer means
+   * `let me authenticate myself with you' which is a bit pointless.
+   * For the quality protocol, the Nak means `ask me to send you quality
+   * reports', but if we didn't ask for them, we don't want them.
+   * An option we don't recognize represents the peer asking to
+   * negotiate some option we don't support, so ignore it.
+   */
+  while (len > CILEN_VOID) {
+    GETCHAR(citype, p);
+    GETCHAR(cilen, p);
+    if (cilen < CILEN_VOID || (len -= cilen) < 0) {
+      goto bad;
+    }
+    next = p + cilen - 2;
+
+    switch (citype) {
+      case CI_MRU:
+        if ((go->neg_mru && go->mru != PPP_DEFMRU)
+            || no.neg_mru || cilen != CILEN_SHORT) {
+          goto bad;
+        }
+        GETSHORT(cishort, p);
+        if (cishort < PPP_DEFMRU) {
+          try.mru = cishort;
+        }
+        break;
+      case CI_ASYNCMAP:
+        if ((go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl)
+            || no.neg_asyncmap || cilen != CILEN_LONG) {
+          goto bad;
+        }
+        break;
+      case CI_AUTHTYPE:
+        if (go->neg_chap || no.neg_chap || go->neg_upap || no.neg_upap) {
+          goto bad;
+        }
+        break;
+      case CI_MAGICNUMBER:
+        if (go->neg_magicnumber || no.neg_magicnumber ||
+            cilen != CILEN_LONG) {
+          goto bad;
+        }
+        break;
+      case CI_PCOMPRESSION:
+        if (go->neg_pcompression || no.neg_pcompression
+            || cilen != CILEN_VOID) {
+          goto bad;
+        }
+        break;
+      case CI_ACCOMPRESSION:
+        if (go->neg_accompression || no.neg_accompression
+            || cilen != CILEN_VOID) {
+          goto bad;
+        }
+        break;
+      case CI_QUALITY:
+        if (go->neg_lqr || no.neg_lqr || cilen != CILEN_LQR) {
+          goto bad;
+        }
+        break;
+    }
+    p = next;
+  }
+
+  /* If there is still anything left, this packet is bad. */
+  if (len != 0) {
+    goto bad;
+  }
+
+  /*
+  * OK, the Nak is good.  Now we can update state.
+  */
+  if (f->state != LS_OPENED) {
+    if (looped_back) {
+      if (++try.numloops >= lcp_loopbackfail) {
+        LCPDEBUG((LOG_NOTICE, "Serial line is looped back.\n"));
+        lcp_close(f->unit, "Loopback detected");
+      }
+    } else {
+      try.numloops = 0;
+    }
+    *go = try;
+  }
+
+  return 1;
+
+bad:
+  LCPDEBUG((LOG_WARNING, "lcp_nakci: received bad Nak!\n"));
+  return 0;
+}
+
+
+/*
+ * lcp_rejci - Peer has Rejected some of our CIs.
+ * This should not modify any state if the Reject is bad
+ * or if LCP is in the LS_OPENED state.
+ *
+ * Returns:
+ *  0 - Reject was bad.
+ *  1 - Reject was good.
+ */
+static int
+lcp_rejci(fsm *f, u_char *p, int len)
+{
+  lcp_options *go = &lcp_gotoptions[f->unit];
+  u_char cichar;
+  u_short cishort;
+  u32_t cilong;
+  lcp_options try; /* options to request next time */
+
+  try = *go;
+
+  /*
+   * Any Rejected CIs must be in exactly the same order that we sent.
+   * Check packet length and CI length at each step.
+   * If we find any deviations, then this packet is bad.
+   */
+#define REJCIVOID(opt, neg) \
+  if (go->neg && \
+      len >= CILEN_VOID && \
+      p[1] == CILEN_VOID && \
+      p[0] == opt) { \
+    len -= CILEN_VOID; \
+    INCPTR(CILEN_VOID, p); \
+    try.neg = 0; \
+    LCPDEBUG((LOG_INFO, "lcp_rejci: void opt %d rejected\n", opt)); \
+  }
+#define REJCISHORT(opt, neg, val) \
+  if (go->neg && \
+      len >= CILEN_SHORT && \
+      p[1] == CILEN_SHORT && \
+      p[0] == opt) { \
+    len -= CILEN_SHORT; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    /* Check rejected value. */ \
+    if (cishort != val) { \
+      goto bad; \
+    } \
+    try.neg = 0; \
+    LCPDEBUG((LOG_INFO,"lcp_rejci: short opt %d rejected\n", opt)); \
+  }
+#define REJCICHAP(opt, neg, val, digest) \
+  if (go->neg && \
+      len >= CILEN_CHAP && \
+      p[1] == CILEN_CHAP && \
+      p[0] == opt) { \
+    len -= CILEN_CHAP; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    GETCHAR(cichar, p); \
+    /* Check rejected value. */ \
+    if (cishort != val || cichar != digest) { \
+      goto bad; \
+    } \
+    try.neg = 0; \
+    try.neg_upap = 0; \
+    LCPDEBUG((LOG_INFO,"lcp_rejci: chap opt %d rejected\n", opt)); \
+  }
+#define REJCILONG(opt, neg, val) \
+  if (go->neg && \
+      len >= CILEN_LONG && \
+      p[1] == CILEN_LONG && \
+      p[0] == opt) { \
+    len -= CILEN_LONG; \
+    INCPTR(2, p); \
+    GETLONG(cilong, p); \
+    /* Check rejected value. */ \
+    if (cilong != val) { \
+      goto bad; \
+    } \
+    try.neg = 0; \
+    LCPDEBUG((LOG_INFO,"lcp_rejci: long opt %d rejected\n", opt)); \
+  }
+#define REJCILQR(opt, neg, val) \
+  if (go->neg && \
+      len >= CILEN_LQR && \
+      p[1] == CILEN_LQR && \
+      p[0] == opt) { \
+    len -= CILEN_LQR; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    GETLONG(cilong, p); \
+    /* Check rejected value. */ \
+    if (cishort != PPP_LQR || cilong != val) { \
+      goto bad; \
+    } \
+    try.neg = 0; \
+    LCPDEBUG((LOG_INFO,"lcp_rejci: LQR opt %d rejected\n", opt)); \
+  }
+#define REJCICBCP(opt, neg, val) \
+  if (go->neg && \
+      len >= CILEN_CBCP && \
+      p[1] == CILEN_CBCP && \
+      p[0] == opt) { \
+    len -= CILEN_CBCP; \
+    INCPTR(2, p); \
+    GETCHAR(cichar, p); \
+    /* Check rejected value. */ \
+    if (cichar != val) { \
+      goto bad; \
+    } \
+    try.neg = 0; \
+    LCPDEBUG((LOG_INFO,"lcp_rejci: Callback opt %d rejected\n", opt)); \
+  }
+  
+  REJCISHORT(CI_MRU, neg_mru, go->mru);
+  REJCILONG(CI_ASYNCMAP, neg_asyncmap, go->asyncmap);
+  REJCICHAP(CI_AUTHTYPE, neg_chap, PPP_CHAP, go->chap_mdtype);
+  if (!go->neg_chap) {
+    REJCISHORT(CI_AUTHTYPE, neg_upap, PPP_PAP);
+  }
+  REJCILQR(CI_QUALITY, neg_lqr, go->lqr_period);
+  REJCICBCP(CI_CALLBACK, neg_cbcp, CBCP_OPT);
+  REJCILONG(CI_MAGICNUMBER, neg_magicnumber, go->magicnumber);
+  REJCIVOID(CI_PCOMPRESSION, neg_pcompression);
+  REJCIVOID(CI_ACCOMPRESSION, neg_accompression);
+  
+  /*
+   * If there are any remaining CIs, then this packet is bad.
+   */
+  if (len != 0) {
+    goto bad;
+  }
+  /*
+   * Now we can update state.
+   */
+  if (f->state != LS_OPENED) {
+    *go = try;
+  }
+  return 1;
+  
+bad:
+  LCPDEBUG((LOG_WARNING, "lcp_rejci: received bad Reject!\n"));
+  return 0;
+}
+
+
+/*
+ * lcp_reqci - Check the peer's requested CIs and send appropriate response.
+ *
+ * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified
+ * appropriately.  If reject_if_disagree is non-zero, doesn't return
+ * CONFNAK; returns CONFREJ if it can't return CONFACK.
+ */
+static int
+lcp_reqci(fsm *f, 
+          u_char *inp,    /* Requested CIs */
+          int *lenp,      /* Length of requested CIs */
+          int reject_if_disagree)
+{
+  lcp_options *go = &lcp_gotoptions[f->unit];
+  lcp_options *ho = &lcp_hisoptions[f->unit];
+  lcp_options *ao = &lcp_allowoptions[f->unit];
+  u_char *cip, *next;         /* Pointer to current and next CIs */
+  int cilen, citype, cichar;  /* Parsed len, type, char value */
+  u_short cishort;            /* Parsed short value */
+  u32_t cilong;               /* Parse long value */
+  int rc = CONFACK;           /* Final packet return code */
+  int orc;                    /* Individual option return code */
+  u_char *p;                  /* Pointer to next char to parse */
+  u_char *rejp;               /* Pointer to next char in reject frame */
+  u_char *nakp;               /* Pointer to next char in Nak frame */
+  int l = *lenp;              /* Length left */
+#if TRACELCP > 0
+  char traceBuf[80];
+  int traceNdx = 0;
+#endif
+
+  /*
+   * Reset all his options.
+   */
+  BZERO(ho, sizeof(*ho));
+
+  /*
+   * Process all his options.
+   */
+  next = inp;
+  nakp = nak_buffer;
+  rejp = inp;
+  while (l) {
+    orc = CONFACK;      /* Assume success */
+    cip = p = next;     /* Remember begining of CI */
+    if (l < 2 ||        /* Not enough data for CI header or */
+        p[1] < 2 ||     /*  CI length too small or */
+        p[1] > l) {     /*  CI length too big? */
+      LCPDEBUG((LOG_WARNING, "lcp_reqci: bad CI length!\n"));
+      orc = CONFREJ;    /* Reject bad CI */
+      cilen = l;        /* Reject till end of packet */
+      l = 0;            /* Don't loop again */
+      citype = 0;
+      goto endswitch;
+    }
+    GETCHAR(citype, p); /* Parse CI type */
+    GETCHAR(cilen, p);  /* Parse CI length */
+    l -= cilen;         /* Adjust remaining length */
+    next += cilen;      /* Step to next CI */
+
+    switch (citype) {   /* Check CI type */
+      case CI_MRU:
+        if (!ao->neg_mru) {    /* Allow option? */
+          LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - not allowed\n"));
+          orc = CONFREJ;    /* Reject CI */
+          break;
+        } else if (cilen != CILEN_SHORT) {  /* Check CI length */
+          LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - bad length\n"));
+          orc = CONFREJ;    /* Reject CI */
+          break;
+        }
+        GETSHORT(cishort, p);  /* Parse MRU */
+
+        /*
+         * He must be able to receive at least our minimum.
+         * No need to check a maximum.  If he sends a large number,
+         * we'll just ignore it.
+         */
+        if (cishort < PPP_MINMRU) {
+          LCPDEBUG((LOG_INFO, "lcp_reqci: Nak - MRU too small\n"));
+          orc = CONFNAK;    /* Nak CI */
+          PUTCHAR(CI_MRU, nakp);
+          PUTCHAR(CILEN_SHORT, nakp);
+          PUTSHORT(PPP_MINMRU, nakp);  /* Give him a hint */
+          break;
+        }
+        ho->neg_mru = 1;    /* Remember he sent MRU */
+        ho->mru = cishort;    /* And remember value */
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MRU %d", cishort);
+        traceNdx = strlen(traceBuf);
+#endif
+        break;
+
+      case CI_ASYNCMAP:
+        if (!ao->neg_asyncmap) {
+          LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP not allowed\n"));
+          orc = CONFREJ;
+          break;
+        } else if (cilen != CILEN_LONG) {
+          LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP bad length\n"));
+          orc = CONFREJ;
+          break;
+        }
+        GETLONG(cilong, p);
+        
+        /*
+         * Asyncmap must have set at least the bits
+         * which are set in lcp_allowoptions[unit].asyncmap.
+         */
+        if ((ao->asyncmap & ~cilong) != 0) {
+          LCPDEBUG((LOG_INFO, "lcp_reqci: Nak ASYNCMAP %lX missing %lX\n", 
+                    cilong, ao->asyncmap));
+          orc = CONFNAK;
+          PUTCHAR(CI_ASYNCMAP, nakp);
+          PUTCHAR(CILEN_LONG, nakp);
+          PUTLONG(ao->asyncmap | cilong, nakp);
+          break;
+        }
+        ho->neg_asyncmap = 1;
+        ho->asyncmap = cilong;
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ASYNCMAP=%lX", cilong);
+        traceNdx = strlen(traceBuf);
+#endif
+        break;
+
+      case CI_AUTHTYPE:
+        if (cilen < CILEN_SHORT) {
+          LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE missing arg\n"));
+          orc = CONFREJ;
+          break;
+        } else if (!(ao->neg_upap || ao->neg_chap)) {
+          /*
+           * Reject the option if we're not willing to authenticate.
+           */
+          LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE not allowed\n"));
+          orc = CONFREJ;
+          break;
+        }
+        GETSHORT(cishort, p);
+        
+        /*
+         * Authtype must be UPAP or CHAP.
+         *
+         * Note: if both ao->neg_upap and ao->neg_chap are set,
+         * and the peer sends a Configure-Request with two
+         * authenticate-protocol requests, one for CHAP and one
+         * for UPAP, then we will reject the second request.
+         * Whether we end up doing CHAP or UPAP depends then on
+         * the ordering of the CIs in the peer's Configure-Request.
+         */
+        
+        if (cishort == PPP_PAP) {
+          if (ho->neg_chap) {  /* we've already accepted CHAP */
+            LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP already accepted\n"));
+            orc = CONFREJ;
+            break;
+          } else if (cilen != CILEN_SHORT) {
+            LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP bad len\n"));
+            orc = CONFREJ;
+            break;
+          }
+          if (!ao->neg_upap) {  /* we don't want to do PAP */
+            LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE PAP not allowed\n"));
+            orc = CONFNAK;  /* NAK it and suggest CHAP */
+            PUTCHAR(CI_AUTHTYPE, nakp);
+            PUTCHAR(CILEN_CHAP, nakp);
+            PUTSHORT(PPP_CHAP, nakp);
+            PUTCHAR(ao->chap_mdtype, nakp);
+            break;
+          }
+          ho->neg_upap = 1;
+#if TRACELCP > 0
+          snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PAP (%X)", cishort);
+          traceNdx = strlen(traceBuf);
+#endif
+          break;
+        }
+        if (cishort == PPP_CHAP) {
+          if (ho->neg_upap) {  /* we've already accepted PAP */
+            LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP accepted PAP\n"));
+            orc = CONFREJ;
+            break;
+          } else if (cilen != CILEN_CHAP) {
+            LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP bad len\n"));
+            orc = CONFREJ;
+            break;
+          }
+          if (!ao->neg_chap) {  /* we don't want to do CHAP */
+            LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP not allowed\n"));
+            orc = CONFNAK;  /* NAK it and suggest PAP */
+            PUTCHAR(CI_AUTHTYPE, nakp);
+            PUTCHAR(CILEN_SHORT, nakp);
+            PUTSHORT(PPP_PAP, nakp);
+            break;
+          }
+          GETCHAR(cichar, p);  /* get digest type*/
+          if (cichar != CHAP_DIGEST_MD5
+#ifdef CHAPMS
+              && cichar != CHAP_MICROSOFT
+#endif
+          ) {
+            LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP digest=%d\n", cichar));
+            orc = CONFNAK;
+            PUTCHAR(CI_AUTHTYPE, nakp);
+            PUTCHAR(CILEN_CHAP, nakp);
+            PUTSHORT(PPP_CHAP, nakp);
+            PUTCHAR(ao->chap_mdtype, nakp);
+            break;
+          }
+#if TRACELCP > 0
+          snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CHAP %X,%d", cishort, cichar);
+          traceNdx = strlen(traceBuf);
+#endif
+          ho->chap_mdtype = cichar; /* save md type */
+          ho->neg_chap = 1;
+          break;
+        }
+        
+        /*
+         * We don't recognize the protocol they're asking for.
+         * Nak it with something we're willing to do.
+         * (At this point we know ao->neg_upap || ao->neg_chap.)
+         */
+        orc = CONFNAK;
+        PUTCHAR(CI_AUTHTYPE, nakp);
+        if (ao->neg_chap) {
+          LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req CHAP\n", cishort));
+          PUTCHAR(CILEN_CHAP, nakp);
+          PUTSHORT(PPP_CHAP, nakp);
+          PUTCHAR(ao->chap_mdtype, nakp);
+        } else {
+          LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req PAP\n", cishort));
+          PUTCHAR(CILEN_SHORT, nakp);
+          PUTSHORT(PPP_PAP, nakp);
+        }
+        break;
+      
+      case CI_QUALITY:
+        GETSHORT(cishort, p);
+        GETLONG(cilong, p);
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " QUALITY (%x %x)", cishort, (unsigned int) cilong);
+        traceNdx = strlen(traceBuf);
+#endif
+
+        if (!ao->neg_lqr ||
+            cilen != CILEN_LQR) {
+          orc = CONFREJ;
+          break;
+        }
+        
+        /*
+         * Check the protocol and the reporting period.
+         * XXX When should we Nak this, and what with?
+         */
+        if (cishort != PPP_LQR) {
+          orc = CONFNAK;
+          PUTCHAR(CI_QUALITY, nakp);
+          PUTCHAR(CILEN_LQR, nakp);
+          PUTSHORT(PPP_LQR, nakp);
+          PUTLONG(ao->lqr_period, nakp);
+          break;
+        }
+        break;
+      
+      case CI_MAGICNUMBER:
+        if (!(ao->neg_magicnumber || go->neg_magicnumber) ||
+            cilen != CILEN_LONG) {
+          orc = CONFREJ;
+          break;
+        }
+        GETLONG(cilong, p);
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MAGICNUMBER (%lX)", cilong);
+        traceNdx = strlen(traceBuf);
+#endif
+
+        /*
+         * He must have a different magic number.
+         */
+        if (go->neg_magicnumber &&
+            cilong == go->magicnumber) {
+          cilong = magic();  /* Don't put magic() inside macro! */
+          orc = CONFNAK;
+          PUTCHAR(CI_MAGICNUMBER, nakp);
+          PUTCHAR(CILEN_LONG, nakp);
+          PUTLONG(cilong, nakp);
+          break;
+        }
+        ho->neg_magicnumber = 1;
+        ho->magicnumber = cilong;
+        break;
+      
+      
+      case CI_PCOMPRESSION:
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PCOMPRESSION");
+        traceNdx = strlen(traceBuf);
+#endif
+        if (!ao->neg_pcompression ||
+            cilen != CILEN_VOID) {
+          orc = CONFREJ;
+          break;
+        }
+        ho->neg_pcompression = 1;
+        break;
+      
+      case CI_ACCOMPRESSION:
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ACCOMPRESSION");
+        traceNdx = strlen(traceBuf);
+#endif
+        if (!ao->neg_accompression ||
+            cilen != CILEN_VOID) {
+          orc = CONFREJ;
+          break;
+        }
+        ho->neg_accompression = 1;
+        break;
+      
+      case CI_MRRU:
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_MRRU");
+        traceNdx = strlen(traceBuf);
+#endif
+        orc = CONFREJ;
+        break;
+      
+      case CI_SSNHF:
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_SSNHF");
+        traceNdx = strlen(traceBuf);
+#endif
+        orc = CONFREJ;
+        break;
+      
+      case CI_EPDISC:
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_EPDISC");
+        traceNdx = strlen(traceBuf);
+#endif
+        orc = CONFREJ;
+        break;
+      
+      default:
+#if TRACELCP
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " unknown %d", citype);
+        traceNdx = strlen(traceBuf);
+#endif
+        orc = CONFREJ;
+        break;
+    }
+
+  endswitch:
+#if TRACELCP
+    if (traceNdx >= 80 - 32) {
+      LCPDEBUG((LOG_INFO, "lcp_reqci: rcvd%s\n", traceBuf));
+      traceNdx = 0;
+    }
+#endif
+    if (orc == CONFACK && /* Good CI */
+        rc != CONFACK) {  /*  but prior CI wasnt? */
+      continue;           /* Don't send this one */
+    }
+
+    if (orc == CONFNAK) {     /* Nak this CI? */
+      if (reject_if_disagree  /* Getting fed up with sending NAKs? */
+          && citype != CI_MAGICNUMBER) {
+        orc = CONFREJ;        /* Get tough if so */
+      } else {
+        if (rc == CONFREJ) {  /* Rejecting prior CI? */
+          continue;           /* Don't send this one */
+        }
+        rc = CONFNAK;
+      }
+    }
+    if (orc == CONFREJ) {        /* Reject this CI */
+      rc = CONFREJ;
+      if (cip != rejp) {         /* Need to move rejected CI? */
+        BCOPY(cip, rejp, cilen); /* Move it */
+      }
+      INCPTR(cilen, rejp);       /* Update output pointer */
+    }
+  }
+
+  /*
+   * If we wanted to send additional NAKs (for unsent CIs), the
+   * code would go here.  The extra NAKs would go at *nakp.
+   * At present there are no cases where we want to ask the
+   * peer to negotiate an option.
+   */
+
+  switch (rc) {
+    case CONFACK:
+      *lenp = (int)(next - inp);
+      break;
+    case CONFNAK:
+      /*
+       * Copy the Nak'd options from the nak_buffer to the caller's buffer.
+       */
+      *lenp = (int)(nakp - nak_buffer);
+      BCOPY(nak_buffer, inp, *lenp);
+      break;
+    case CONFREJ:
+      *lenp = (int)(rejp - inp);
+      break;
+  }
+
+#if TRACELCP > 0
+  if (traceNdx > 0) {
+    LCPDEBUG((LOG_INFO, "lcp_reqci: %s\n", traceBuf));
+  }
+#endif
+  LCPDEBUG((LOG_INFO, "lcp_reqci: returning CONF%s.\n", CODENAME(rc)));
+  return (rc);      /* Return final code */
+}
+
+
+/*
+ * lcp_up - LCP has come UP.
+ */
+static void
+lcp_up(fsm *f)
+{
+  lcp_options *wo = &lcp_wantoptions[f->unit];
+  lcp_options *ho = &lcp_hisoptions[f->unit];
+  lcp_options *go = &lcp_gotoptions[f->unit];
+  lcp_options *ao = &lcp_allowoptions[f->unit];
+
+  if (!go->neg_magicnumber) {
+    go->magicnumber = 0;
+  }
+  if (!ho->neg_magicnumber) {
+    ho->magicnumber = 0;
+  }
+
+  /*
+   * Set our MTU to the smaller of the MTU we wanted and
+   * the MRU our peer wanted.  If we negotiated an MRU,
+   * set our MRU to the larger of value we wanted and
+   * the value we got in the negotiation.
+   */
+  ppp_send_config(f->unit, LWIP_MIN(ao->mru, (ho->neg_mru? ho->mru: PPP_MRU)),
+                 (ho->neg_asyncmap? ho->asyncmap: 0xffffffffl),
+                  ho->neg_pcompression, ho->neg_accompression);
+  /*
+   * If the asyncmap hasn't been negotiated, we really should
+   * set the receive asyncmap to ffffffff, but we set it to 0
+   * for backwards contemptibility.
+   */
+  ppp_recv_config(f->unit, (go->neg_mru? LWIP_MAX(wo->mru, go->mru): PPP_MRU),
+                 (go->neg_asyncmap? go->asyncmap: 0x00000000),
+                  go->neg_pcompression, go->neg_accompression);
+
+  if (ho->neg_mru) {
+    peer_mru[f->unit] = ho->mru;
+  }
+
+  lcp_echo_lowerup(f->unit); /* Enable echo messages */
+
+  link_established(f->unit);
+}
+
+
+/*
+ * lcp_down - LCP has gone DOWN.
+ *
+ * Alert other protocols.
+ */
+static void
+lcp_down(fsm *f)
+{
+  lcp_options *go = &lcp_gotoptions[f->unit];
+
+  lcp_echo_lowerdown(f->unit);
+
+  link_down(f->unit);
+
+  ppp_send_config(f->unit, PPP_MRU, 0xffffffffl, 0, 0);
+  ppp_recv_config(f->unit, PPP_MRU,
+                  (go->neg_asyncmap? go->asyncmap: 0x00000000),
+                   go->neg_pcompression, go->neg_accompression);
+  peer_mru[f->unit] = PPP_MRU;
+}
+
+
+/*
+ * lcp_starting - LCP needs the lower layer up.
+ */
+static void
+lcp_starting(fsm *f)
+{
+  link_required(f->unit);
+}
+
+
+/*
+ * lcp_finished - LCP has finished with the lower layer.
+ */
+static void
+lcp_finished(fsm *f)
+{
+  link_terminated(f->unit);
+}
+
+
+#if 0
+/*
+ * print_string - print a readable representation of a string using
+ * printer.
+ */
+static void
+print_string( char *p, int len, void (*printer) (void *, char *, ...), void *arg)
+{
+  int c;
+  
+  printer(arg, "\"");
+  for (; len > 0; --len) {
+    c = *p++;
+    if (' ' <= c && c <= '~') {
+        if (c == '\\' || c == '"') {
+          printer(arg, "\\");
+        }
+        printer(arg, "%c", c);
+    } else {
+      switch (c) {
+        case '\n':
+          printer(arg, "\\n");
+          break;
+        case '\r':
+          printer(arg, "\\r");
+          break;
+        case '\t':
+          printer(arg, "\\t");
+          break;
+        default:
+          printer(arg, "\\%.3o", c);
+        }
+    }
+  }
+  printer(arg, "\"");
+}
+
+
+/*
+ * lcp_printpkt - print the contents of an LCP packet.
+ */
+static char *lcp_codenames[] = {
+  "ConfReq", "ConfAck", "ConfNak", "ConfRej",
+  "TermReq", "TermAck", "CodeRej", "ProtRej",
+  "EchoReq", "EchoRep", "DiscReq"
+};
+
+static int
+lcp_printpkt( u_char *p, int plen, void (*printer) (void *, char *, ...), void *arg)
+{
+  int code, id, len, olen;
+  u_char *pstart, *optend;
+  u_short cishort;
+  u32_t cilong;
+
+  if (plen < HEADERLEN) {
+    return 0;
+  }
+  pstart = p;
+  GETCHAR(code, p);
+  GETCHAR(id, p);
+  GETSHORT(len, p);
+  if (len < HEADERLEN || len > plen) {
+    return 0;
+  }
+
+  if (code >= 1 && code <= sizeof(lcp_codenames) / sizeof(char *)) {
+    printer(arg, " %s", lcp_codenames[code-1]);
+  } else {
+    printer(arg, " code=0x%x", code);
+  }
+  printer(arg, " id=0x%x", id);
+  len -= HEADERLEN;
+  switch (code) {
+    case CONFREQ:
+    case CONFACK:
+    case CONFNAK:
+    case CONFREJ:
+      /* print option list */
+      while (len >= 2) {
+        GETCHAR(code, p);
+        GETCHAR(olen, p);
+        p -= 2;
+        if (olen < 2 || olen > len) {
+          break;
+        }
+        printer(arg, " <");
+        len -= olen;
+        optend = p + olen;
+        switch (code) {
+          case CI_MRU:
+            if (olen == CILEN_SHORT) {
+              p += 2;
+              GETSHORT(cishort, p);
+              printer(arg, "mru %d", cishort);
+            }
+            break;
+          case CI_ASYNCMAP:
+            if (olen == CILEN_LONG) {
+              p += 2;
+              GETLONG(cilong, p);
+              printer(arg, "asyncmap 0x%lx", cilong);
+            }
+            break;
+          case CI_AUTHTYPE:
+            if (olen >= CILEN_SHORT) {
+              p += 2;
+              printer(arg, "auth ");
+              GETSHORT(cishort, p);
+              switch (cishort) {
+                case PPP_PAP:
+                  printer(arg, "pap");
+                  break;
+                case PPP_CHAP:
+                  printer(arg, "chap");
+                  break;
+                default:
+                  printer(arg, "0x%x", cishort);
+              }
+            }
+            break;
+          case CI_QUALITY:
+            if (olen >= CILEN_SHORT) {
+              p += 2;
+              printer(arg, "quality ");
+              GETSHORT(cishort, p);
+              switch (cishort) {
+                case PPP_LQR:
+                  printer(arg, "lqr");
+                  break;
+                default:
+                  printer(arg, "0x%x", cishort);
+              }
+            }
+            break;
+          case CI_CALLBACK:
+            if (olen >= CILEN_CHAR) {
+              p += 2;
+              printer(arg, "callback ");
+              GETSHORT(cishort, p);
+              switch (cishort) {
+                case CBCP_OPT:
+                  printer(arg, "CBCP");
+                  break;
+                default:
+                  printer(arg, "0x%x", cishort);
+              }
+            }
+            break;
+          case CI_MAGICNUMBER:
+            if (olen == CILEN_LONG) {
+              p += 2;
+              GETLONG(cilong, p);
+              printer(arg, "magic 0x%x", cilong);
+            }
+            break;
+          case CI_PCOMPRESSION:
+            if (olen == CILEN_VOID) {
+              p += 2;
+              printer(arg, "pcomp");
+            }
+            break;
+          case CI_ACCOMPRESSION:
+            if (olen == CILEN_VOID) {
+              p += 2;
+              printer(arg, "accomp");
+            }
+            break;
+        }
+        while (p < optend) {
+          GETCHAR(code, p);
+          printer(arg, " %.2x", code);
+        }
+        printer(arg, ">");
+      }
+      break;
+    
+    case TERMACK:
+    case TERMREQ:
+      if (len > 0 && *p >= ' ' && *p < 0x7f) {
+        printer(arg, " ");
+        print_string((char*)p, len, printer, arg);
+        p += len;
+        len = 0;
+      }
+      break;
+    
+    case ECHOREQ:
+    case ECHOREP:
+    case DISCREQ:
+      if (len >= 4) {
+        GETLONG(cilong, p);
+        printer(arg, " magic=0x%x", cilong);
+        p += 4;
+        len -= 4;
+      }
+      break;
+  }
+
+  /* print the rest of the bytes in the packet */
+  for (; len > 0; --len) {
+    GETCHAR(code, p);
+    printer(arg, " %.2x", code);
+  }
+
+  return (int)(p - pstart);
+}
+#endif
+
+/*
+ * Time to shut down the link because there is nothing out there.
+ */
+static void
+LcpLinkFailure (fsm *f)
+{
+  if (f->state == LS_OPENED) {
+    LCPDEBUG((LOG_INFO, "No response to %d echo-requests\n", lcp_echos_pending));
+    LCPDEBUG((LOG_NOTICE, "Serial link appears to be disconnected.\n"));
+    lcp_close(f->unit, "Peer not responding");
+  }
+}
+
+/*
+ * Timer expired for the LCP echo requests from this process.
+ */
+static void
+LcpEchoCheck (fsm *f)
+{
+  LcpSendEchoRequest (f);
+
+  /*
+   * Start the timer for the next interval.
+   */
+  LWIP_ASSERT("lcp_echo_timer_running == 0", lcp_echo_timer_running == 0);
+
+  TIMEOUT (LcpEchoTimeout, f, lcp_echo_interval);
+  lcp_echo_timer_running = 1;
+}
+
+/*
+ * LcpEchoTimeout - Timer expired on the LCP echo
+ */
+static void
+LcpEchoTimeout (void *arg)
+{
+  if (lcp_echo_timer_running != 0) {
+    lcp_echo_timer_running = 0;
+    LcpEchoCheck ((fsm *) arg);
+  }
+}
+
+/*
+ * LcpEchoReply - LCP has received a reply to the echo
+ */
+static void
+lcp_received_echo_reply (fsm *f, int id, u_char *inp, int len)
+{
+  u32_t magic;
+
+  LWIP_UNUSED_ARG(id);
+
+  /* Check the magic number - don't count replies from ourselves. */
+  if (len < 4) {
+    LCPDEBUG((LOG_WARNING, "lcp: received short Echo-Reply, length %d\n", len));
+    return;
+  }
+  GETLONG(magic, inp);
+  if (lcp_gotoptions[f->unit].neg_magicnumber && magic == lcp_gotoptions[f->unit].magicnumber) {
+    LCPDEBUG((LOG_WARNING, "appear to have received our own echo-reply!\n"));
+    return;
+  }
+  
+  /* Reset the number of outstanding echo frames */
+  lcp_echos_pending = 0;
+}
+
+/*
+ * LcpSendEchoRequest - Send an echo request frame to the peer
+ */
+static void
+LcpSendEchoRequest (fsm *f)
+{
+  u32_t lcp_magic;
+  u_char pkt[4], *pktp;
+
+  /*
+   * Detect the failure of the peer at this point.
+   */
+  if (lcp_echo_fails != 0) {
+    if (lcp_echos_pending++ >= lcp_echo_fails) {
+      LcpLinkFailure(f);
+      lcp_echos_pending = 0;
+    }
+  }
+
+  /*
+   * Make and send the echo request frame.
+   */
+  if (f->state == LS_OPENED) {
+    lcp_magic = lcp_gotoptions[f->unit].magicnumber;
+    pktp = pkt;
+    PUTLONG(lcp_magic, pktp);
+    fsm_sdata(f, ECHOREQ, (u_char)(lcp_echo_number++ & 0xFF), pkt, (int)(pktp - pkt));
+  }
+}
+
+/*
+ * lcp_echo_lowerup - Start the timer for the LCP frame
+ */
+
+static void
+lcp_echo_lowerup (int unit)
+{
+  fsm *f = &lcp_fsm[unit];
+
+  /* Clear the parameters for generating echo frames */
+  lcp_echos_pending      = 0;
+  lcp_echo_number        = 0;
+  lcp_echo_timer_running = 0;
+
+  /* If a timeout interval is specified then start the timer */
+  if (lcp_echo_interval != 0) {
+    LcpEchoCheck (f);
+  }
+}
+
+/*
+ * lcp_echo_lowerdown - Stop the timer for the LCP frame
+ */
+
+static void
+lcp_echo_lowerdown (int unit)
+{
+  fsm *f = &lcp_fsm[unit];
+
+  if (lcp_echo_timer_running != 0) {
+    UNTIMEOUT (LcpEchoTimeout, f);
+    lcp_echo_timer_running = 0;
+  }
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/lcp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/lcp.h
new file mode 100644
index 0000000..1a5e5a4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/lcp.h
@@ -0,0 +1,167 @@
+/*****************************************************************************
+* lcp.h - Network Link Control Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * lcp.h - Link Control Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: lcp.h,v 1.3 2007/12/19 20:47:23 fbernon Exp $
+ */
+
+#ifndef LCP_H
+#define LCP_H
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+/*
+ * Options.
+ */
+#define CI_MRU           1  /* Maximum Receive Unit */
+#define CI_ASYNCMAP      2  /* Async Control Character Map */
+#define CI_AUTHTYPE      3  /* Authentication Type */
+#define CI_QUALITY       4  /* Quality Protocol */
+#define CI_MAGICNUMBER   5  /* Magic Number */
+#define CI_PCOMPRESSION  7  /* Protocol Field Compression */
+#define CI_ACCOMPRESSION 8  /* Address/Control Field Compression */
+#define CI_CALLBACK      13 /* callback */
+#define CI_MRRU          17 /* max reconstructed receive unit; multilink */
+#define CI_SSNHF         18 /* short sequence numbers for multilink */
+#define CI_EPDISC        19 /* endpoint discriminator */
+
+/*
+ * LCP-specific packet types.
+ */
+#define PROTREJ          8  /* Protocol Reject */
+#define ECHOREQ          9  /* Echo Request */
+#define ECHOREP          10 /* Echo Reply */
+#define DISCREQ          11 /* Discard Request */
+#define CBCP_OPT         6  /* Use callback control protocol */
+
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * The state of options is described by an lcp_options structure.
+ */
+typedef struct lcp_options {
+    u_int passive           : 1; /* Don't die if we don't get a response */
+    u_int silent            : 1; /* Wait for the other end to start first */
+    u_int restart           : 1; /* Restart vs. exit after close */
+    u_int neg_mru           : 1; /* Negotiate the MRU? */
+    u_int neg_asyncmap      : 1; /* Negotiate the async map? */
+    u_int neg_upap          : 1; /* Ask for UPAP authentication? */
+    u_int neg_chap          : 1; /* Ask for CHAP authentication? */
+    u_int neg_magicnumber   : 1; /* Ask for magic number? */
+    u_int neg_pcompression  : 1; /* HDLC Protocol Field Compression? */
+    u_int neg_accompression : 1; /* HDLC Address/Control Field Compression? */
+    u_int neg_lqr           : 1; /* Negotiate use of Link Quality Reports */
+    u_int neg_cbcp          : 1; /* Negotiate use of CBCP */
+#ifdef PPP_MULTILINK
+    u_int neg_mrru          : 1; /* Negotiate multilink MRRU */
+    u_int neg_ssnhf         : 1; /* Negotiate short sequence numbers */
+    u_int neg_endpoint      : 1; /* Negotiate endpoint discriminator */
+#endif
+    u_short mru;                 /* Value of MRU */
+#ifdef PPP_MULTILINK
+    u_short mrru;                /* Value of MRRU, and multilink enable */
+#endif
+    u_char chap_mdtype;          /* which MD type (hashing algorithm) */
+    u32_t asyncmap;              /* Value of async map */
+    u32_t magicnumber;
+    int numloops;                /* Number of loops during magic number neg. */
+    u32_t lqr_period;            /* Reporting period for LQR 1/100ths second */
+#ifdef PPP_MULTILINK
+    struct epdisc endpoint;      /* endpoint discriminator */
+#endif
+} lcp_options;
+
+/*
+ * Values for phase from BSD pppd.h based on RFC 1661.
+ */
+typedef enum {
+  PHASE_DEAD = 0,
+  PHASE_INITIALIZE,
+  PHASE_ESTABLISH,
+  PHASE_AUTHENTICATE,
+  PHASE_CALLBACK,
+  PHASE_NETWORK,
+  PHASE_TERMINATE
+} LinkPhase;
+
+
+/*****************************
+*** PUBLIC DATA STRUCTURES ***
+*****************************/
+
+extern LinkPhase lcp_phase[NUM_PPP]; /* Phase of link session (RFC 1661) */
+extern lcp_options lcp_wantoptions[];
+extern lcp_options lcp_gotoptions[];
+extern lcp_options lcp_allowoptions[];
+extern lcp_options lcp_hisoptions[];
+extern ext_accm xmit_accm[];
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+void lcp_init     (int);
+void lcp_open     (int);
+void lcp_close    (int, char *);
+void lcp_lowerup  (int);
+void lcp_lowerdown(int);
+void lcp_sprotrej (int, u_char *, int); /* send protocol reject */
+
+extern struct protent lcp_protent;
+
+/* Default number of times we receive our magic number from the peer
+   before deciding the link is looped-back. */
+#define DEFLOOPBACKFAIL 10
+
+#endif /* LCP_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/magic.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/magic.c
new file mode 100644
index 0000000..d3922bb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/magic.c
@@ -0,0 +1,82 @@
+/*****************************************************************************
+* magic.c - Network Random Number Generator program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*   Original based on BSD magic.c.
+*****************************************************************************/
+/*
+ * magic.c - PPP Magic Number routines.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT
+
+#include "ppp.h"
+#include "randm.h"
+#include "magic.h"
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * magicInit - Initialize the magic number generator.
+ *
+ * Since we use another random number generator that has its own
+ * initialization, we do nothing here.
+ */
+void magicInit()
+{
+  return;
+}
+
+/*
+ * magic - Returns the next magic number.
+ */
+u32_t magic()
+{
+  return avRandom();
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/magic.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/magic.h
new file mode 100644
index 0000000..bc51749
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/magic.h
@@ -0,0 +1,67 @@
+/*****************************************************************************
+* magic.h - Network Random Number Generator header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * magic.h - PPP Magic Number definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: magic.h,v 1.2 2007/12/02 22:35:55 fbernon Exp $
+ */
+
+#ifndef MAGIC_H
+#define MAGIC_H
+
+/*****************************************************************************
+************************** PUBLIC FUNCTIONS **********************************
+*****************************************************************************/
+
+/* Initialize the magic number generator */
+void  magicInit(void);
+
+/* Returns the next magic number */
+u32_t magic(void);
+
+#endif /* MAGIC_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/md5.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/md5.c
new file mode 100644
index 0000000..7a60d78
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/md5.c
@@ -0,0 +1,320 @@
+/*
+ ***********************************************************************
+ ** md5.c -- the source code for MD5 routines                         **
+ ** RSA Data Security, Inc. MD5 Message-Digest Algorithm              **
+ ** Created: 2/17/90 RLR                                              **
+ ** Revised: 1/91 SRD,AJ,BSK,JT Reference C ver., 7/10 constant corr. **
+ ***********************************************************************
+ */
+
+/*
+ ***********************************************************************
+ ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved.  **
+ **                                                                   **
+ ** License to copy and use this software is granted provided that    **
+ ** it is identified as the "RSA Data Security, Inc. MD5 Message-     **
+ ** Digest Algorithm" in all material mentioning or referencing this  **
+ ** software or this function.                                        **
+ **                                                                   **
+ ** License is also granted to make and use derivative works          **
+ ** provided that such works are identified as "derived from the RSA  **
+ ** Data Security, Inc. MD5 Message-Digest Algorithm" in all          **
+ ** material mentioning or referencing the derived work.              **
+ **                                                                   **
+ ** RSA Data Security, Inc. makes no representations concerning       **
+ ** either the merchantability of this software or the suitability    **
+ ** of this software for any particular purpose.  It is provided "as  **
+ ** is" without express or implied warranty of any kind.              **
+ **                                                                   **
+ ** These notices must be retained in any copies of any part of this  **
+ ** documentation and/or software.                                    **
+ ***********************************************************************
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#if CHAP_SUPPORT || MD5_SUPPORT
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "md5.h"
+
+#include 
+
+/*
+ ***********************************************************************
+ **  Message-digest routines:                                         **
+ **  To form the message digest for a message M                       **
+ **    (1) Initialize a context buffer mdContext using MD5Init        **
+ **    (2) Call MD5Update on mdContext and M                          **
+ **    (3) Call MD5Final on mdContext                                 **
+ **  The message digest is now in mdContext->digest[0...15]           **
+ ***********************************************************************
+ */
+
+/* forward declaration */
+static void Transform (u32_t *buf, u32_t *in);
+
+static unsigned char PADDING[64] = {
+  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+/* F, G, H and I are basic MD5 functions */
+#define F(x, y, z) (((x) & (y)) | ((~x) & (z)))
+#define G(x, y, z) (((x) & (z)) | ((y) & (~z)))
+#define H(x, y, z) ((x) ^ (y) ^ (z))
+#define I(x, y, z) ((y) ^ ((x) | (~z)))
+
+/* ROTATE_LEFT rotates x left n bits */
+#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n))))
+
+/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4 */
+/* Rotation is separate from addition to prevent recomputation */
+#define FF(a, b, c, d, x, s, ac) \
+  {(a) += F ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+#define GG(a, b, c, d, x, s, ac) \
+  {(a) += G ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+#define HH(a, b, c, d, x, s, ac) \
+  {(a) += H ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+#define II(a, b, c, d, x, s, ac) \
+  {(a) += I ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+
+#ifdef __STDC__
+#define UL(x) x##UL
+#else
+#ifdef WIN32
+#define UL(x) x##UL
+#else
+#define UL(x) x
+#endif
+#endif
+
+/* The routine MD5Init initializes the message-digest context
+   mdContext. All fields are set to zero.
+ */
+void
+MD5Init (MD5_CTX *mdContext)
+{
+  mdContext->i[0] = mdContext->i[1] = (u32_t)0;
+
+  /* Load magic initialization constants. */
+  mdContext->buf[0] = (u32_t)0x67452301UL;
+  mdContext->buf[1] = (u32_t)0xefcdab89UL;
+  mdContext->buf[2] = (u32_t)0x98badcfeUL;
+  mdContext->buf[3] = (u32_t)0x10325476UL;
+}
+
+/* The routine MD5Update updates the message-digest context to
+   account for the presence of each of the characters inBuf[0..inLen-1]
+   in the message whose digest is being computed.
+ */
+void
+MD5Update(MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen)
+{
+  u32_t in[16];
+  int mdi;
+  unsigned int i, ii;
+
+#if 0
+  ppp_trace(LOG_INFO, "MD5Update: %u:%.*H\n", inLen, MIN(inLen, 20) * 2, inBuf);
+  ppp_trace(LOG_INFO, "MD5Update: %u:%s\n", inLen, inBuf);
+#endif
+  
+  /* compute number of bytes mod 64 */
+  mdi = (int)((mdContext->i[0] >> 3) & 0x3F);
+
+  /* update number of bits */
+  if ((mdContext->i[0] + ((u32_t)inLen << 3)) < mdContext->i[0]) {
+    mdContext->i[1]++;
+  }
+  mdContext->i[0] += ((u32_t)inLen << 3);
+  mdContext->i[1] += ((u32_t)inLen >> 29);
+
+  while (inLen--) {
+    /* add new character to buffer, increment mdi */
+    mdContext->in[mdi++] = *inBuf++;
+
+    /* transform if necessary */
+    if (mdi == 0x40) {
+      for (i = 0, ii = 0; i < 16; i++, ii += 4) {
+        in[i] = (((u32_t)mdContext->in[ii+3]) << 24) |
+                (((u32_t)mdContext->in[ii+2]) << 16) |
+                (((u32_t)mdContext->in[ii+1]) << 8)  |
+                ((u32_t)mdContext->in[ii]);
+      }
+      Transform (mdContext->buf, in);
+      mdi = 0;
+    }
+  }
+}
+
+/* The routine MD5Final terminates the message-digest computation and
+   ends with the desired message digest in mdContext->digest[0...15].
+ */
+void
+MD5Final (unsigned char hash[], MD5_CTX *mdContext)
+{
+  u32_t in[16];
+  int mdi;
+  unsigned int i, ii;
+  unsigned int padLen;
+
+  /* save number of bits */
+  in[14] = mdContext->i[0];
+  in[15] = mdContext->i[1];
+
+  /* compute number of bytes mod 64 */
+  mdi = (int)((mdContext->i[0] >> 3) & 0x3F);
+
+  /* pad out to 56 mod 64 */
+  padLen = (mdi < 56) ? (56 - mdi) : (120 - mdi);
+  MD5Update (mdContext, PADDING, padLen);
+
+  /* append length in bits and transform */
+  for (i = 0, ii = 0; i < 14; i++, ii += 4) {
+    in[i] = (((u32_t)mdContext->in[ii+3]) << 24) |
+            (((u32_t)mdContext->in[ii+2]) << 16) |
+            (((u32_t)mdContext->in[ii+1]) << 8)  |
+            ((u32_t)mdContext->in[ii]);
+  }
+  Transform (mdContext->buf, in);
+
+  /* store buffer in digest */
+  for (i = 0, ii = 0; i < 4; i++, ii += 4) {
+    mdContext->digest[ii]   = (unsigned char)(mdContext->buf[i] & 0xFF);
+    mdContext->digest[ii+1] =
+      (unsigned char)((mdContext->buf[i] >> 8)  & 0xFF);
+    mdContext->digest[ii+2] =
+      (unsigned char)((mdContext->buf[i] >> 16) & 0xFF);
+    mdContext->digest[ii+3] =
+      (unsigned char)((mdContext->buf[i] >> 24) & 0xFF);
+  }
+  SMEMCPY(hash, mdContext->digest, 16);
+}
+
+/* Basic MD5 step. Transforms buf based on in.
+ */
+static void
+Transform (u32_t *buf, u32_t *in)
+{
+  u32_t a = buf[0], b = buf[1], c = buf[2], d = buf[3];
+
+  /* Round 1 */
+#define S11 7
+#define S12 12
+#define S13 17
+#define S14 22
+  FF ( a, b, c, d, in[ 0], S11, UL(3614090360)); /* 1 */
+  FF ( d, a, b, c, in[ 1], S12, UL(3905402710)); /* 2 */
+  FF ( c, d, a, b, in[ 2], S13, UL( 606105819)); /* 3 */
+  FF ( b, c, d, a, in[ 3], S14, UL(3250441966)); /* 4 */
+  FF ( a, b, c, d, in[ 4], S11, UL(4118548399)); /* 5 */
+  FF ( d, a, b, c, in[ 5], S12, UL(1200080426)); /* 6 */
+  FF ( c, d, a, b, in[ 6], S13, UL(2821735955)); /* 7 */
+  FF ( b, c, d, a, in[ 7], S14, UL(4249261313)); /* 8 */
+  FF ( a, b, c, d, in[ 8], S11, UL(1770035416)); /* 9 */
+  FF ( d, a, b, c, in[ 9], S12, UL(2336552879)); /* 10 */
+  FF ( c, d, a, b, in[10], S13, UL(4294925233)); /* 11 */
+  FF ( b, c, d, a, in[11], S14, UL(2304563134)); /* 12 */
+  FF ( a, b, c, d, in[12], S11, UL(1804603682)); /* 13 */
+  FF ( d, a, b, c, in[13], S12, UL(4254626195)); /* 14 */
+  FF ( c, d, a, b, in[14], S13, UL(2792965006)); /* 15 */
+  FF ( b, c, d, a, in[15], S14, UL(1236535329)); /* 16 */
+
+  /* Round 2 */
+#define S21 5
+#define S22 9
+#define S23 14
+#define S24 20
+  GG ( a, b, c, d, in[ 1], S21, UL(4129170786)); /* 17 */
+  GG ( d, a, b, c, in[ 6], S22, UL(3225465664)); /* 18 */
+  GG ( c, d, a, b, in[11], S23, UL( 643717713)); /* 19 */
+  GG ( b, c, d, a, in[ 0], S24, UL(3921069994)); /* 20 */
+  GG ( a, b, c, d, in[ 5], S21, UL(3593408605)); /* 21 */
+  GG ( d, a, b, c, in[10], S22, UL(  38016083)); /* 22 */
+  GG ( c, d, a, b, in[15], S23, UL(3634488961)); /* 23 */
+  GG ( b, c, d, a, in[ 4], S24, UL(3889429448)); /* 24 */
+  GG ( a, b, c, d, in[ 9], S21, UL( 568446438)); /* 25 */
+  GG ( d, a, b, c, in[14], S22, UL(3275163606)); /* 26 */
+  GG ( c, d, a, b, in[ 3], S23, UL(4107603335)); /* 27 */
+  GG ( b, c, d, a, in[ 8], S24, UL(1163531501)); /* 28 */
+  GG ( a, b, c, d, in[13], S21, UL(2850285829)); /* 29 */
+  GG ( d, a, b, c, in[ 2], S22, UL(4243563512)); /* 30 */
+  GG ( c, d, a, b, in[ 7], S23, UL(1735328473)); /* 31 */
+  GG ( b, c, d, a, in[12], S24, UL(2368359562)); /* 32 */
+
+  /* Round 3 */
+#define S31 4
+#define S32 11
+#define S33 16
+#define S34 23
+  HH ( a, b, c, d, in[ 5], S31, UL(4294588738)); /* 33 */
+  HH ( d, a, b, c, in[ 8], S32, UL(2272392833)); /* 34 */
+  HH ( c, d, a, b, in[11], S33, UL(1839030562)); /* 35 */
+  HH ( b, c, d, a, in[14], S34, UL(4259657740)); /* 36 */
+  HH ( a, b, c, d, in[ 1], S31, UL(2763975236)); /* 37 */
+  HH ( d, a, b, c, in[ 4], S32, UL(1272893353)); /* 38 */
+  HH ( c, d, a, b, in[ 7], S33, UL(4139469664)); /* 39 */
+  HH ( b, c, d, a, in[10], S34, UL(3200236656)); /* 40 */
+  HH ( a, b, c, d, in[13], S31, UL( 681279174)); /* 41 */
+  HH ( d, a, b, c, in[ 0], S32, UL(3936430074)); /* 42 */
+  HH ( c, d, a, b, in[ 3], S33, UL(3572445317)); /* 43 */
+  HH ( b, c, d, a, in[ 6], S34, UL(  76029189)); /* 44 */
+  HH ( a, b, c, d, in[ 9], S31, UL(3654602809)); /* 45 */
+  HH ( d, a, b, c, in[12], S32, UL(3873151461)); /* 46 */
+  HH ( c, d, a, b, in[15], S33, UL( 530742520)); /* 47 */
+  HH ( b, c, d, a, in[ 2], S34, UL(3299628645)); /* 48 */
+
+  /* Round 4 */
+#define S41 6
+#define S42 10
+#define S43 15
+#define S44 21
+  II ( a, b, c, d, in[ 0], S41, UL(4096336452)); /* 49 */
+  II ( d, a, b, c, in[ 7], S42, UL(1126891415)); /* 50 */
+  II ( c, d, a, b, in[14], S43, UL(2878612391)); /* 51 */
+  II ( b, c, d, a, in[ 5], S44, UL(4237533241)); /* 52 */
+  II ( a, b, c, d, in[12], S41, UL(1700485571)); /* 53 */
+  II ( d, a, b, c, in[ 3], S42, UL(2399980690)); /* 54 */
+  II ( c, d, a, b, in[10], S43, UL(4293915773)); /* 55 */
+  II ( b, c, d, a, in[ 1], S44, UL(2240044497)); /* 56 */
+  II ( a, b, c, d, in[ 8], S41, UL(1873313359)); /* 57 */
+  II ( d, a, b, c, in[15], S42, UL(4264355552)); /* 58 */
+  II ( c, d, a, b, in[ 6], S43, UL(2734768916)); /* 59 */
+  II ( b, c, d, a, in[13], S44, UL(1309151649)); /* 60 */
+  II ( a, b, c, d, in[ 4], S41, UL(4149444226)); /* 61 */
+  II ( d, a, b, c, in[11], S42, UL(3174756917)); /* 62 */
+  II ( c, d, a, b, in[ 2], S43, UL( 718787259)); /* 63 */
+  II ( b, c, d, a, in[ 9], S44, UL(3951481745)); /* 64 */
+
+  buf[0] += a;
+  buf[1] += b;
+  buf[2] += c;
+  buf[3] += d;
+}
+
+#endif /* CHAP_SUPPORT || MD5_SUPPORT */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/md5.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/md5.h
new file mode 100644
index 0000000..e129533
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/md5.h
@@ -0,0 +1,55 @@
+/*
+ ***********************************************************************
+ ** md5.h -- header file for implementation of MD5                    **
+ ** RSA Data Security, Inc. MD5 Message-Digest Algorithm              **
+ ** Created: 2/17/90 RLR                                              **
+ ** Revised: 12/27/90 SRD,AJ,BSK,JT Reference C version               **
+ ** Revised (for MD5): RLR 4/27/91                                    **
+ **   -- G modified to have y&~z instead of y&z                       **
+ **   -- FF, GG, HH modified to add in last register done             **
+ **   -- Access pattern: round 2 works mod 5, round 3 works mod 3     **
+ **   -- distinct additive constant for each step                     **
+ **   -- round 4 added, working mod 7                                 **
+ ***********************************************************************
+ */
+
+/*
+ ***********************************************************************
+ ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved.  **
+ **                                                                   **
+ ** License to copy and use this software is granted provided that    **
+ ** it is identified as the "RSA Data Security, Inc. MD5 Message-     **
+ ** Digest Algorithm" in all material mentioning or referencing this  **
+ ** software or this function.                                        **
+ **                                                                   **
+ ** License is also granted to make and use derivative works          **
+ ** provided that such works are identified as "derived from the RSA  **
+ ** Data Security, Inc. MD5 Message-Digest Algorithm" in all          **
+ ** material mentioning or referencing the derived work.              **
+ **                                                                   **
+ ** RSA Data Security, Inc. makes no representations concerning       **
+ ** either the merchantability of this software or the suitability    **
+ ** of this software for any particular purpose.  It is provided "as  **
+ ** is" without express or implied warranty of any kind.              **
+ **                                                                   **
+ ** These notices must be retained in any copies of any part of this  **
+ ** documentation and/or software.                                    **
+ ***********************************************************************
+ */
+
+#ifndef MD5_H
+#define MD5_H
+
+/* Data structure for MD5 (Message-Digest) computation */
+typedef struct {
+  u32_t i[2];               /* number of _bits_ handled mod 2^64 */
+  u32_t buf[4];             /* scratch buffer */
+  unsigned char in[64];     /* input buffer */
+  unsigned char digest[16]; /* actual digest after MD5Final call */
+} MD5_CTX;
+
+void MD5Init  ( MD5_CTX *mdContext);
+void MD5Update( MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen);
+void MD5Final ( unsigned char hash[], MD5_CTX *mdContext);
+
+#endif /* MD5_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/pap.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/pap.c
new file mode 100644
index 0000000..e8c45df
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/pap.c
@@ -0,0 +1,622 @@
+/*****************************************************************************
+* pap.c - Network Password Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-12 Guy Lancaster , Global Election Systems Inc.
+*   Original.
+*****************************************************************************/
+/*
+ * upap.c - User/Password Authentication Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#if PAP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "auth.h"
+#include "pap.h"
+
+#include 
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Protocol entry points.
+ */
+static void upap_init      (int);
+static void upap_lowerup   (int);
+static void upap_lowerdown (int);
+static void upap_input     (int, u_char *, int);
+static void upap_protrej   (int);
+
+static void upap_timeout   (void *);
+static void upap_reqtimeout(void *);
+static void upap_rauthreq  (upap_state *, u_char *, int, int);
+static void upap_rauthack  (upap_state *, u_char *, int, int);
+static void upap_rauthnak  (upap_state *, u_char *, int, int);
+static void upap_sauthreq  (upap_state *);
+static void upap_sresp     (upap_state *, u_char, u_char, char *, int);
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+struct protent pap_protent = {
+  PPP_PAP,
+  upap_init,
+  upap_input,
+  upap_protrej,
+  upap_lowerup,
+  upap_lowerdown,
+  NULL,
+  NULL,
+#if 0
+  upap_printpkt,
+  NULL,
+#endif
+  1,
+  "PAP",
+#if 0
+  NULL,
+  NULL,
+  NULL
+#endif
+};
+
+upap_state upap[NUM_PPP]; /* UPAP state; one for each unit */
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ *  Set the default login name and password for the pap sessions
+ */
+void
+upap_setloginpasswd(int unit, const char *luser, const char *lpassword)
+{
+  upap_state *u = &upap[unit];
+  
+  /* Save the username and password we're given */
+  u->us_user = luser;
+  u->us_userlen = strlen(luser);
+  u->us_passwd = lpassword;
+  u->us_passwdlen = strlen(lpassword);
+}
+
+
+/*
+ * upap_authwithpeer - Authenticate us with our peer (start client).
+ *
+ * Set new state and send authenticate's.
+ */
+void
+upap_authwithpeer(int unit, char *user, char *password)
+{
+  upap_state *u = &upap[unit];
+
+  UPAPDEBUG((LOG_INFO, "upap_authwithpeer: %d user=%s password=%s s=%d\n",
+             unit, user, password, u->us_clientstate));
+
+  upap_setloginpasswd(unit, user, password);
+
+  u->us_transmits = 0;
+
+  /* Lower layer up yet? */
+  if (u->us_clientstate == UPAPCS_INITIAL ||
+      u->us_clientstate == UPAPCS_PENDING) {
+    u->us_clientstate = UPAPCS_PENDING;
+    return;
+  }
+
+  upap_sauthreq(u);      /* Start protocol */
+}
+
+
+/*
+ * upap_authpeer - Authenticate our peer (start server).
+ *
+ * Set new state.
+ */
+void
+upap_authpeer(int unit)
+{
+  upap_state *u = &upap[unit];
+
+  /* Lower layer up yet? */
+  if (u->us_serverstate == UPAPSS_INITIAL ||
+      u->us_serverstate == UPAPSS_PENDING) {
+    u->us_serverstate = UPAPSS_PENDING;
+    return;
+  }
+
+  u->us_serverstate = UPAPSS_LISTEN;
+  if (u->us_reqtimeout > 0) {
+    TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout);
+  }
+}
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * upap_init - Initialize a UPAP unit.
+ */
+static void
+upap_init(int unit)
+{
+  upap_state *u = &upap[unit];
+
+  UPAPDEBUG((LOG_INFO, "upap_init: %d\n", unit));
+  u->us_unit         = unit;
+  u->us_user         = NULL;
+  u->us_userlen      = 0;
+  u->us_passwd       = NULL;
+  u->us_passwdlen    = 0;
+  u->us_clientstate  = UPAPCS_INITIAL;
+  u->us_serverstate  = UPAPSS_INITIAL;
+  u->us_id           = 0;
+  u->us_timeouttime  = UPAP_DEFTIMEOUT;
+  u->us_maxtransmits = 10;
+  u->us_reqtimeout   = UPAP_DEFREQTIME;
+}
+
+/*
+ * upap_timeout - Retransmission timer for sending auth-reqs expired.
+ */
+static void
+upap_timeout(void *arg)
+{
+  upap_state *u = (upap_state *) arg;
+
+  UPAPDEBUG((LOG_INFO, "upap_timeout: %d timeout %d expired s=%d\n", 
+        u->us_unit, u->us_timeouttime, u->us_clientstate));
+
+  if (u->us_clientstate != UPAPCS_AUTHREQ) {
+    return;
+  }
+
+  if (u->us_transmits >= u->us_maxtransmits) {
+    /* give up in disgust */
+    UPAPDEBUG((LOG_ERR, "No response to PAP authenticate-requests\n"));
+    u->us_clientstate = UPAPCS_BADAUTH;
+    auth_withpeer_fail(u->us_unit, PPP_PAP);
+    return;
+  }
+
+  upap_sauthreq(u);    /* Send Authenticate-Request */
+}
+
+
+/*
+ * upap_reqtimeout - Give up waiting for the peer to send an auth-req.
+ */
+static void
+upap_reqtimeout(void *arg)
+{
+  upap_state *u = (upap_state *) arg;
+
+  if (u->us_serverstate != UPAPSS_LISTEN) {
+    return; /* huh?? */
+  }
+
+  auth_peer_fail(u->us_unit, PPP_PAP);
+  u->us_serverstate = UPAPSS_BADAUTH;
+}
+
+
+/*
+ * upap_lowerup - The lower layer is up.
+ *
+ * Start authenticating if pending.
+ */
+static void
+upap_lowerup(int unit)
+{
+  upap_state *u = &upap[unit];
+
+  UPAPDEBUG((LOG_INFO, "upap_lowerup: %d s=%d\n", unit, u->us_clientstate));
+
+  if (u->us_clientstate == UPAPCS_INITIAL) {
+    u->us_clientstate = UPAPCS_CLOSED;
+  } else if (u->us_clientstate == UPAPCS_PENDING) {
+    upap_sauthreq(u);  /* send an auth-request */
+  }
+
+  if (u->us_serverstate == UPAPSS_INITIAL) {
+    u->us_serverstate = UPAPSS_CLOSED;
+  } else if (u->us_serverstate == UPAPSS_PENDING) {
+    u->us_serverstate = UPAPSS_LISTEN;
+    if (u->us_reqtimeout > 0) {
+      TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout);
+    }
+  }
+}
+
+
+/*
+ * upap_lowerdown - The lower layer is down.
+ *
+ * Cancel all timeouts.
+ */
+static void
+upap_lowerdown(int unit)
+{
+  upap_state *u = &upap[unit];
+
+  UPAPDEBUG((LOG_INFO, "upap_lowerdown: %d s=%d\n", unit, u->us_clientstate));
+
+  if (u->us_clientstate == UPAPCS_AUTHREQ) { /* Timeout pending? */
+    UNTIMEOUT(upap_timeout, u);    /* Cancel timeout */
+  }
+  if (u->us_serverstate == UPAPSS_LISTEN && u->us_reqtimeout > 0) {
+    UNTIMEOUT(upap_reqtimeout, u);
+  }
+
+  u->us_clientstate = UPAPCS_INITIAL;
+  u->us_serverstate = UPAPSS_INITIAL;
+}
+
+
+/*
+ * upap_protrej - Peer doesn't speak this protocol.
+ *
+ * This shouldn't happen.  In any case, pretend lower layer went down.
+ */
+static void
+upap_protrej(int unit)
+{
+  upap_state *u = &upap[unit];
+
+  if (u->us_clientstate == UPAPCS_AUTHREQ) {
+    UPAPDEBUG((LOG_ERR, "PAP authentication failed due to protocol-reject\n"));
+    auth_withpeer_fail(unit, PPP_PAP);
+  }
+  if (u->us_serverstate == UPAPSS_LISTEN) {
+    UPAPDEBUG((LOG_ERR, "PAP authentication of peer failed (protocol-reject)\n"));
+    auth_peer_fail(unit, PPP_PAP);
+  }
+  upap_lowerdown(unit);
+}
+
+
+/*
+ * upap_input - Input UPAP packet.
+ */
+static void
+upap_input(int unit, u_char *inpacket, int l)
+{
+  upap_state *u = &upap[unit];
+  u_char *inp;
+  u_char code, id;
+  int len;
+
+  /*
+   * Parse header (code, id and length).
+   * If packet too short, drop it.
+   */
+  inp = inpacket;
+  if (l < UPAP_HEADERLEN) {
+    UPAPDEBUG((LOG_INFO, "pap_input: rcvd short header.\n"));
+    return;
+  }
+  GETCHAR(code, inp);
+  GETCHAR(id, inp);
+  GETSHORT(len, inp);
+  if (len < UPAP_HEADERLEN) {
+    UPAPDEBUG((LOG_INFO, "pap_input: rcvd illegal length.\n"));
+    return;
+  }
+  if (len > l) {
+    UPAPDEBUG((LOG_INFO, "pap_input: rcvd short packet.\n"));
+    return;
+  }
+  len -= UPAP_HEADERLEN;
+
+  /*
+   * Action depends on code.
+   */
+  switch (code) {
+    case UPAP_AUTHREQ:
+      upap_rauthreq(u, inp, id, len);
+      break;
+
+    case UPAP_AUTHACK:
+      upap_rauthack(u, inp, id, len);
+      break;
+
+    case UPAP_AUTHNAK:
+      upap_rauthnak(u, inp, id, len);
+      break;
+
+    default:        /* XXX Need code reject */
+      break;
+  }
+}
+
+
+/*
+ * upap_rauth - Receive Authenticate.
+ */
+static void
+upap_rauthreq(upap_state *u, u_char *inp, int id, int len)
+{
+  u_char ruserlen, rpasswdlen;
+  char *ruser, *rpasswd;
+  int retcode;
+  char *msg;
+  int msglen;
+
+  UPAPDEBUG((LOG_INFO, "pap_rauth: Rcvd id %d.\n", id));
+
+  if (u->us_serverstate < UPAPSS_LISTEN) {
+    return;
+  }
+
+  /*
+   * If we receive a duplicate authenticate-request, we are
+   * supposed to return the same status as for the first request.
+   */
+  if (u->us_serverstate == UPAPSS_OPEN) {
+    upap_sresp(u, UPAP_AUTHACK, id, "", 0);  /* return auth-ack */
+    return;
+  }
+  if (u->us_serverstate == UPAPSS_BADAUTH) {
+    upap_sresp(u, UPAP_AUTHNAK, id, "", 0);  /* return auth-nak */
+    return;
+  }
+
+  /*
+   * Parse user/passwd.
+   */
+  if (len < sizeof (u_char)) {
+    UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
+    return;
+  }
+  GETCHAR(ruserlen, inp);
+  len -= sizeof (u_char) + ruserlen + sizeof (u_char);
+  if (len < 0) {
+    UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
+    return;
+  }
+  ruser = (char *) inp;
+  INCPTR(ruserlen, inp);
+  GETCHAR(rpasswdlen, inp);
+  if (len < rpasswdlen) {
+    UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
+    return;
+  }
+  rpasswd = (char *) inp;
+
+  /*
+   * Check the username and password given.
+   */
+  retcode = check_passwd(u->us_unit, ruser, ruserlen, rpasswd, rpasswdlen, &msg, &msglen);
+  BZERO(rpasswd, rpasswdlen);
+
+  upap_sresp(u, retcode, id, msg, msglen);
+
+  if (retcode == UPAP_AUTHACK) {
+    u->us_serverstate = UPAPSS_OPEN;
+    auth_peer_success(u->us_unit, PPP_PAP, ruser, ruserlen);
+  } else {
+    u->us_serverstate = UPAPSS_BADAUTH;
+    auth_peer_fail(u->us_unit, PPP_PAP);
+  }
+
+  if (u->us_reqtimeout > 0) {
+    UNTIMEOUT(upap_reqtimeout, u);
+  }
+}
+
+
+/*
+ * upap_rauthack - Receive Authenticate-Ack.
+ */
+static void
+upap_rauthack(upap_state *u, u_char *inp, int id, int len)
+{
+  u_char msglen;
+  char *msg;
+
+  LWIP_UNUSED_ARG(id);
+
+  UPAPDEBUG((LOG_INFO, "pap_rauthack: Rcvd id %d s=%d\n", id, u->us_clientstate));
+
+  if (u->us_clientstate != UPAPCS_AUTHREQ) { /* XXX */
+    return;
+  }
+
+  /*
+   * Parse message.
+   */
+  if (len < sizeof (u_char)) {
+    UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n"));
+    return;
+  }
+  GETCHAR(msglen, inp);
+  len -= sizeof (u_char);
+  if (len < msglen) {
+    UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n"));
+    return;
+  }
+  msg = (char *) inp;
+  PRINTMSG(msg, msglen);
+
+  UNTIMEOUT(upap_timeout, u);    /* Cancel timeout */
+  u->us_clientstate = UPAPCS_OPEN;
+
+  auth_withpeer_success(u->us_unit, PPP_PAP);
+}
+
+
+/*
+ * upap_rauthnak - Receive Authenticate-Nakk.
+ */
+static void
+upap_rauthnak(upap_state *u, u_char *inp, int id, int len)
+{
+  u_char msglen;
+  char *msg;
+
+  LWIP_UNUSED_ARG(id);
+
+  UPAPDEBUG((LOG_INFO, "pap_rauthnak: Rcvd id %d s=%d\n", id, u->us_clientstate));
+
+  if (u->us_clientstate != UPAPCS_AUTHREQ) { /* XXX */
+    return;
+  }
+
+  /*
+   * Parse message.
+   */
+  if (len < sizeof (u_char)) {
+    UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n"));
+  } else {
+    GETCHAR(msglen, inp);
+    if(msglen > 0) {
+      len -= sizeof (u_char);
+      if (len < msglen) {
+        UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n"));
+        return;
+      }
+      msg = (char *) inp;
+      PRINTMSG(msg, msglen);
+    }
+  }
+
+  u->us_clientstate = UPAPCS_BADAUTH;
+
+  UPAPDEBUG((LOG_ERR, "PAP authentication failed\n"));
+  auth_withpeer_fail(u->us_unit, PPP_PAP);
+}
+
+
+/*
+ * upap_sauthreq - Send an Authenticate-Request.
+ */
+static void
+upap_sauthreq(upap_state *u)
+{
+  u_char *outp;
+  int outlen;
+
+  outlen = UPAP_HEADERLEN + 2 * sizeof (u_char) 
+         + u->us_userlen + u->us_passwdlen;
+  outp = outpacket_buf[u->us_unit];
+
+  MAKEHEADER(outp, PPP_PAP);
+
+  PUTCHAR(UPAP_AUTHREQ, outp);
+  PUTCHAR(++u->us_id, outp);
+  PUTSHORT(outlen, outp);
+  PUTCHAR(u->us_userlen, outp);
+  BCOPY(u->us_user, outp, u->us_userlen);
+  INCPTR(u->us_userlen, outp);
+  PUTCHAR(u->us_passwdlen, outp);
+  BCOPY(u->us_passwd, outp, u->us_passwdlen);
+
+  pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN);
+
+  UPAPDEBUG((LOG_INFO, "pap_sauth: Sent id %d\n", u->us_id));
+
+  TIMEOUT(upap_timeout, u, u->us_timeouttime);
+  ++u->us_transmits;
+  u->us_clientstate = UPAPCS_AUTHREQ;
+}
+
+
+/*
+ * upap_sresp - Send a response (ack or nak).
+ */
+static void
+upap_sresp(upap_state *u, u_char code, u_char id, char *msg, int msglen)
+{
+  u_char *outp;
+  int outlen;
+
+  outlen = UPAP_HEADERLEN + sizeof (u_char) + msglen;
+  outp = outpacket_buf[u->us_unit];
+  MAKEHEADER(outp, PPP_PAP);
+
+  PUTCHAR(code, outp);
+  PUTCHAR(id, outp);
+  PUTSHORT(outlen, outp);
+  PUTCHAR(msglen, outp);
+  BCOPY(msg, outp, msglen);
+  pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN);
+
+  UPAPDEBUG((LOG_INFO, "pap_sresp: Sent code %d, id %d s=%d\n", code, id, u->us_clientstate));
+}
+
+#if 0
+/*
+ * upap_printpkt - print the contents of a PAP packet.
+ */
+static int upap_printpkt(
+  u_char *p,
+  int plen,
+  void (*printer) (void *, char *, ...),
+  void *arg
+)
+{
+  LWIP_UNUSED_ARG(p);
+  LWIP_UNUSED_ARG(plen);
+  LWIP_UNUSED_ARG(printer);
+  LWIP_UNUSED_ARG(arg);
+  return 0;
+}
+#endif /* 0 */
+
+#endif /* PAP_SUPPORT */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/pap.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/pap.h
new file mode 100644
index 0000000..0a09fc8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/pap.h
@@ -0,0 +1,131 @@
+/*****************************************************************************
+* pap.h -  PPP Password Authentication Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * upap.h - User/Password Authentication Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef PAP_H
+#define PAP_H
+
+#if PAP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+/*
+ * Packet header = Code, id, length.
+ */
+#define UPAP_HEADERLEN (sizeof (u_char) + sizeof (u_char) + sizeof (u_short))
+
+
+/*
+ * UPAP codes.
+ */
+#define UPAP_AUTHREQ 1 /* Authenticate-Request */
+#define UPAP_AUTHACK 2 /* Authenticate-Ack */
+#define UPAP_AUTHNAK 3 /* Authenticate-Nak */
+
+/*
+ * Client states.
+ */
+#define UPAPCS_INITIAL 0 /* Connection down */
+#define UPAPCS_CLOSED  1 /* Connection up, haven't requested auth */
+#define UPAPCS_PENDING 2 /* Connection down, have requested auth */
+#define UPAPCS_AUTHREQ 3 /* We've sent an Authenticate-Request */
+#define UPAPCS_OPEN    4 /* We've received an Ack */
+#define UPAPCS_BADAUTH 5 /* We've received a Nak */
+
+/*
+ * Server states.
+ */
+#define UPAPSS_INITIAL 0 /* Connection down */
+#define UPAPSS_CLOSED  1 /* Connection up, haven't requested auth */
+#define UPAPSS_PENDING 2 /* Connection down, have requested auth */
+#define UPAPSS_LISTEN  3 /* Listening for an Authenticate */
+#define UPAPSS_OPEN    4 /* We've sent an Ack */
+#define UPAPSS_BADAUTH 5 /* We've sent a Nak */
+
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * Each interface is described by upap structure.
+ */
+typedef struct upap_state {
+  int us_unit;           /* Interface unit number */
+  const char *us_user;   /* User */
+  int us_userlen;        /* User length */
+  const char *us_passwd; /* Password */
+  int us_passwdlen;      /* Password length */
+  int us_clientstate;    /* Client state */
+  int us_serverstate;    /* Server state */
+  u_char us_id;          /* Current id */
+  int us_timeouttime;    /* Timeout (seconds) for auth-req retrans. */
+  int us_transmits;      /* Number of auth-reqs sent */
+  int us_maxtransmits;   /* Maximum number of auth-reqs to send */
+  int us_reqtimeout;     /* Time to wait for auth-req from peer */
+} upap_state;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+extern upap_state upap[];
+
+void upap_setloginpasswd(int unit, const char *luser, const char *lpassword);
+void upap_authwithpeer  (int, char *, char *);
+void upap_authpeer      (int);
+
+extern struct protent pap_protent;
+
+#endif /* PAP_SUPPORT */
+
+#endif /* PAP_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/ppp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/ppp.c
new file mode 100644
index 0000000..13fa5ed
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/ppp.c
@@ -0,0 +1,1989 @@
+/*****************************************************************************
+* ppp.c - Network Point to Point Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*   Original.
+*****************************************************************************/
+
+/*
+ * ppp_defs.h - PPP definitions.
+ *
+ * if_pppvar.h - private structures and declarations for PPP.
+ *
+ * Copyright (c) 1994 The Australian National University.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, provided that the above copyright
+ * notice appears in all copies.  This software is provided without any
+ * warranty, express or implied. The Australian National University
+ * makes no representations about the suitability of this software for
+ * any purpose.
+ *
+ * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY
+ * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
+ * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
+ * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS,
+ * OR MODIFICATIONS.
+ */
+
+/*
+ * if_ppp.h - Point-to-Point Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/ip.h" /* for ip_input() */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "randm.h"
+#include "fsm.h"
+#if PAP_SUPPORT
+#include "pap.h"
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+#include "chap.h"
+#endif /* CHAP_SUPPORT */
+#include "ipcp.h"
+#include "lcp.h"
+#include "magic.h"
+#include "auth.h"
+#if VJ_SUPPORT
+#include "vj.h"
+#endif /* VJ_SUPPORT */
+#if PPPOE_SUPPORT
+#include "netif/ppp_oe.h"
+#endif /* PPPOE_SUPPORT */
+
+#include 
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+/*
+ * The basic PPP frame.
+ */
+#define PPP_ADDRESS(p)  (((u_char *)(p))[0])
+#define PPP_CONTROL(p)  (((u_char *)(p))[1])
+#define PPP_PROTOCOL(p) ((((u_char *)(p))[2] << 8) + ((u_char *)(p))[3])
+
+/* PPP packet parser states.  Current state indicates operation yet to be
+ * completed. */
+typedef enum {
+  PDIDLE = 0,  /* Idle state - waiting. */
+  PDSTART,     /* Process start flag. */
+  PDADDRESS,   /* Process address field. */
+  PDCONTROL,   /* Process control field. */
+  PDPROTOCOL1, /* Process protocol field 1. */
+  PDPROTOCOL2, /* Process protocol field 2. */
+  PDDATA       /* Process data byte. */
+} PPPDevStates;
+
+#define ESCAPE_P(accm, c) ((accm)[(c) >> 3] & pppACCMMask[c & 0x07])
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+/*
+ * PPP interface control block.
+ */
+typedef struct PPPControl_s {
+  char openFlag;                /* True when in use. */
+#if PPPOE_SUPPORT
+  struct netif *ethif;
+  struct pppoe_softc *pppoe_sc;
+#endif /* PPPOE_SUPPORT */
+  int  if_up;                   /* True when the interface is up. */
+  int  errCode;                 /* Code indicating why interface is down. */
+#if PPPOS_SUPPORT
+  sio_fd_t fd;                  /* File device ID of port. */
+  int  kill_link;               /* Shut the link down. */
+  int  sig_hup;                 /* Carrier lost. */
+  struct pbuf *inHead, *inTail; /* The input packet. */
+  PPPDevStates inState;         /* The input process state. */
+  char inEscaped;               /* Escape next character. */
+  u16_t inProtocol;             /* The input protocol code. */
+  u16_t inFCS;                  /* Input Frame Check Sequence value. */
+#endif /* PPPOS_SUPPORT */
+  int  mtu;                     /* Peer's mru */
+  int  pcomp;                   /* Does peer accept protocol compression? */
+  int  accomp;                  /* Does peer accept addr/ctl compression? */
+  u_long lastXMit;              /* Time of last transmission. */
+  ext_accm inACCM;              /* Async-Ctl-Char-Map for input. */
+  ext_accm outACCM;             /* Async-Ctl-Char-Map for output. */
+#if PPPOS_SUPPORT && VJ_SUPPORT
+  int  vjEnabled;               /* Flag indicating VJ compression enabled. */
+  struct vjcompress vjComp;     /* Van Jacobson compression header. */
+#endif /* PPPOS_SUPPORT && VJ_SUPPORT */
+
+  struct netif netif;
+
+  struct ppp_addrs addrs;
+
+  void (*linkStatusCB)(void *ctx, int errCode, void *arg);
+  void *linkStatusCtx;
+
+} PPPControl;
+
+
+/*
+ * Ioctl definitions.
+ */
+
+struct npioctl {
+  int         protocol; /* PPP procotol, e.g. PPP_IP */
+  enum NPmode mode;
+};
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+#if PPPOS_SUPPORT
+static void pppMain(void *pd);
+static void pppDrop(PPPControl *pc);
+static void pppInProc(int pd, u_char *s, int l);
+#endif /* PPPOS_SUPPORT */
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+u_long subnetMask;
+
+static PPPControl pppControl[NUM_PPP]; /* The PPP interface control blocks. */
+
+/*
+ * PPP Data Link Layer "protocol" table.
+ * One entry per supported protocol.
+ * The last entry must be NULL.
+ */
+struct protent *ppp_protocols[] = {
+  &lcp_protent,
+#if PAP_SUPPORT
+  &pap_protent,
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+  &chap_protent,
+#endif /* CHAP_SUPPORT */
+#if CBCP_SUPPORT
+  &cbcp_protent,
+#endif /* CBCP_SUPPORT */
+  &ipcp_protent,
+#if CCP_SUPPORT
+  &ccp_protent,
+#endif /* CCP_SUPPORT */
+  NULL
+};
+
+
+/*
+ * Buffers for outgoing packets.  This must be accessed only from the appropriate
+ * PPP task so that it doesn't need to be protected to avoid collisions.
+ */
+u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN];
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+
+#if PPPOS_SUPPORT
+/*
+ * FCS lookup table as calculated by genfcstab.
+ */
+static const u_short fcstab[256] = {
+  0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
+  0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
+  0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
+  0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
+  0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
+  0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
+  0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
+  0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
+  0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
+  0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
+  0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
+  0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
+  0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
+  0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
+  0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
+  0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
+  0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
+  0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
+  0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
+  0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
+  0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
+  0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
+  0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
+  0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
+  0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
+  0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
+  0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
+  0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
+  0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
+  0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
+  0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
+  0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
+};
+
+/* PPP's Asynchronous-Control-Character-Map.  The mask array is used
+ * to select the specific bit for a character. */
+static u_char pppACCMMask[] = {
+  0x01,
+  0x02,
+  0x04,
+  0x08,
+  0x10,
+  0x20,
+  0x40,
+  0x80
+};
+
+
+void
+pppMainWakeup(int pd)
+{
+  PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d\n", pd));
+  sio_read_abort(pppControl[pd].fd);
+}
+#endif /* PPPOS_SUPPORT */
+
+void
+pppLinkTerminated(int pd)
+{
+  PPPDEBUG((LOG_DEBUG, "pppLinkTerminated: unit %d\n", pd));
+
+#if PPPOE_SUPPORT
+  if(pppControl[pd].ethif) {
+    pppoe_disconnect(pppControl[pd].pppoe_sc);
+  } else
+#endif /* PPPOE_SUPPORT */
+  {
+#if PPPOS_SUPPORT
+    pppMainWakeup(pd);
+#endif /* PPPOS_SUPPORT */
+  }
+}
+
+void
+pppLinkDown(int pd)
+{
+  PPPDEBUG((LOG_DEBUG, "pppLinkDown: unit %d\n", pd));
+
+#if PPPOE_SUPPORT
+  if(pppControl[pd].ethif) {
+    pppoe_disconnect(pppControl[pd].pppoe_sc);
+  } else
+#endif /* PPPOE_SUPPORT */
+  {
+#if PPPOS_SUPPORT
+    pppMainWakeup(pd);
+#endif /* PPPOS_SUPPORT */
+  }
+}
+
+/* these callbacks are necessary because lcp_* functions
+   must be called in the same context as pppInput(),
+   namely the tcpip_thread(), essentially because
+   they manipulate timeouts which are thread-private
+*/
+
+static void
+pppStartCB(void *arg)
+{
+  int pd = (int)arg;
+
+  PPPDEBUG((LOG_DEBUG, "pppStartCB: unit %d\n", pd));
+  lcp_lowerup(pd);
+  lcp_open(pd); /* Start protocol */
+}
+
+static void
+pppStopCB(void *arg)
+{
+  int pd = (int)arg;
+
+  PPPDEBUG((LOG_DEBUG, "pppStopCB: unit %d\n", pd));
+  lcp_close(pd, "User request");
+}
+
+static void
+pppHupCB(void *arg)
+{
+  int pd = (int)arg;
+
+  PPPDEBUG((LOG_DEBUG, "pppHupCB: unit %d\n", pd));
+  lcp_lowerdown(pd);
+  link_terminated(pd);
+}
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/* Initialize the PPP subsystem. */
+
+struct ppp_settings ppp_settings;
+
+void
+pppInit(void)
+{
+  struct protent *protp;
+  int i, j;
+
+  memset(&ppp_settings, 0, sizeof(ppp_settings));
+  ppp_settings.usepeerdns = 1;
+  pppSetAuth(PPPAUTHTYPE_NONE, NULL, NULL);
+
+  magicInit();
+
+  subnetMask = htonl(0xffffff00);
+
+  for (i = 0; i < NUM_PPP; i++) {
+    pppControl[i].openFlag = 0;
+
+    /*
+     * Initialize to the standard option set.
+     */
+    for (j = 0; (protp = ppp_protocols[j]) != NULL; ++j) {
+      (*protp->init)(i);
+    }
+  }
+
+#if PPPOE_SUPPORT
+  pppoe_init();
+#endif /* PPPOE_SUPPORT */
+}
+
+void
+pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd)
+{
+  switch(authType) {
+    case PPPAUTHTYPE_NONE:
+    default:
+#ifdef LWIP_PPP_STRICT_PAP_REJECT
+      ppp_settings.refuse_pap = 1;
+#else  /* LWIP_PPP_STRICT_PAP_REJECT */
+      /* some providers request pap and accept an empty login/pw */
+      ppp_settings.refuse_pap = 0;
+#endif /* LWIP_PPP_STRICT_PAP_REJECT */
+      ppp_settings.refuse_chap = 1;
+      break;
+
+    case PPPAUTHTYPE_ANY:
+      /* Warning: Using PPPAUTHTYPE_ANY might have security consequences.
+       * RFC 1994 says:
+       *
+       * In practice, within or associated with each PPP server, there is a
+       * database which associates "user" names with authentication
+       * information ("secrets").  It is not anticipated that a particular
+       * named user would be authenticated by multiple methods.  This would
+       * make the user vulnerable to attacks which negotiate the least secure
+       * method from among a set (such as PAP rather than CHAP).  If the same
+       * secret was used, PAP would reveal the secret to be used later with
+       * CHAP.
+       *
+       * Instead, for each user name there should be an indication of exactly
+       * one method used to authenticate that user name.  If a user needs to
+       * make use of different authentication methods under different
+       * circumstances, then distinct user names SHOULD be employed, each of
+       * which identifies exactly one authentication method.
+       *
+       */
+      ppp_settings.refuse_pap = 0;
+      ppp_settings.refuse_chap = 0;
+      break;
+
+    case PPPAUTHTYPE_PAP:
+      ppp_settings.refuse_pap = 0;
+      ppp_settings.refuse_chap = 1;
+      break;
+
+    case PPPAUTHTYPE_CHAP:
+      ppp_settings.refuse_pap = 1;
+      ppp_settings.refuse_chap = 0;
+      break;
+  }
+
+  if(user) {
+    strncpy(ppp_settings.user, user, sizeof(ppp_settings.user)-1);
+    ppp_settings.user[sizeof(ppp_settings.user)-1] = '\0';
+  } else {
+    ppp_settings.user[0] = '\0';
+  }
+
+  if(passwd) {
+    strncpy(ppp_settings.passwd, passwd, sizeof(ppp_settings.passwd)-1);
+    ppp_settings.passwd[sizeof(ppp_settings.passwd)-1] = '\0';
+  } else {
+    ppp_settings.passwd[0] = '\0';
+  }
+}
+
+#if PPPOS_SUPPORT
+/* Open a new PPP connection using the given I/O device.
+ * This initializes the PPP control block but does not
+ * attempt to negotiate the LCP session.  If this port
+ * connects to a modem, the modem connection must be
+ * established before calling this.
+ * Return a new PPP connection descriptor on success or
+ * an error code (negative) on failure. */
+int
+pppOverSerialOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx)
+{
+  PPPControl *pc;
+  int pd;
+
+  /* Find a free PPP session descriptor. Critical region? */
+  for (pd = 0; pd < NUM_PPP && pppControl[pd].openFlag != 0; pd++);
+
+  if (pd >= NUM_PPP) {
+    pd = PPPERR_OPEN;
+  } else {
+    pppControl[pd].openFlag = !0;
+  }
+
+  /* Launch a deamon thread. */
+  if (pd >= 0) {
+    pppControl[pd].openFlag = 1;
+
+    lcp_init(pd);
+    pc = &pppControl[pd];
+    pc->fd = fd;
+#if PPPOE_SUPPORT
+    pc->ethif= NULL;
+#endif /* PPPOE_SUPPORT */
+    pc->kill_link = 0;
+    pc->sig_hup = 0;
+    pc->if_up = 0;
+    pc->errCode = 0;
+    pc->inState = PDIDLE;
+    pc->inHead = NULL;
+    pc->inTail = NULL;
+    pc->inEscaped = 0;
+    pc->lastXMit = 0;
+
+#if VJ_SUPPORT
+    pc->vjEnabled = 0;
+    vj_compress_init(&pc->vjComp);
+#endif /* VJ_SUPPORT */
+
+    /* 
+     * Default the in and out accm so that escape and flag characters
+     * are always escaped. 
+     */
+    memset(pc->inACCM, 0, sizeof(ext_accm));
+    pc->inACCM[15] = 0x60;
+    memset(pc->outACCM, 0, sizeof(ext_accm));
+    pc->outACCM[15] = 0x60;
+
+    pc->linkStatusCB = linkStatusCB;
+    pc->linkStatusCtx = linkStatusCtx;
+
+    sys_thread_new(PPP_THREAD_NAME, pppMain, (void*)pd, PPP_THREAD_STACKSIZE, PPP_THREAD_PRIO);
+    if(!linkStatusCB) {
+      while(pd >= 0 && !pc->if_up) {
+        sys_msleep(500);
+        if (lcp_phase[pd] == PHASE_DEAD) {
+          pppClose(pd);
+          if (pc->errCode) {
+            pd = pc->errCode;
+          } else {
+            pd = PPPERR_CONNECT;
+          }
+        }
+      }
+    }
+  }
+
+  return pd;
+}
+#endif /* PPPOS_SUPPORT */
+
+#if PPPOE_SUPPORT
+static void pppOverEthernetLinkStatusCB(int pd, int up);
+
+void
+pppOverEthernetClose(int pd)
+{
+  PPPControl* pc = &pppControl[pd];
+
+  /* *TJL* There's no lcp_deinit */
+  lcp_close(pd, NULL);
+
+  pppoe_destroy(&pc->netif);
+}
+
+int pppOverEthernetOpen(struct netif *ethif, const char *service_name, const char *concentrator_name, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx)
+{
+  PPPControl *pc;
+  int pd;
+
+  LWIP_UNUSED_ARG(service_name);
+  LWIP_UNUSED_ARG(concentrator_name);
+
+  /* Find a free PPP session descriptor. Critical region? */
+  for (pd = 0; pd < NUM_PPP && pppControl[pd].openFlag != 0; pd++);
+  if (pd >= NUM_PPP) {
+    pd = PPPERR_OPEN;
+  } else {
+    pppControl[pd].openFlag = !0;
+  }
+
+  /* PPP session descriptor found, start PPPoE */
+  if (pd >= 0) {
+
+    pppControl[pd].openFlag = 1;
+
+    lcp_init(pd);
+
+    lcp_wantoptions[pd].mru = PPPOE_MAXMTU;
+    lcp_wantoptions[pd].neg_asyncmap = 0;
+    lcp_wantoptions[pd].neg_pcompression = 0;
+    lcp_wantoptions[pd].neg_accompression = 0;
+
+    lcp_allowoptions[pd].mru = PPPOE_MAXMTU;
+    lcp_allowoptions[pd].neg_asyncmap = 0;
+    lcp_allowoptions[pd].neg_pcompression = 0;
+    lcp_allowoptions[pd].neg_accompression = 0;
+
+    pc = &pppControl[pd];
+    pc->if_up = 0;
+    pc->errCode = 0;
+    pc->lastXMit = 0;
+#if PPPOS_SUPPORT
+    pc->kill_link = 0;
+    pc->sig_hup = 0;
+    pc->inState = PDIDLE;
+    pc->inHead = NULL;
+    pc->inTail = NULL;
+    pc->inEscaped = 0;
+#if VJ_SUPPORT
+    pc->vjEnabled = 0;
+#endif /* VJ_SUPPORT */
+#endif /* PPPOS_SUPPORT */
+    pc->ethif= ethif;
+
+    memset(pc->inACCM,  0, sizeof(ext_accm));
+    memset(pc->outACCM, 0, sizeof(ext_accm));
+
+    pc->linkStatusCB  = linkStatusCB;
+    pc->linkStatusCtx = linkStatusCtx;
+
+    if(pppoe_create(ethif, pd, pppOverEthernetLinkStatusCB, &pc->pppoe_sc) != ERR_OK) {
+      pc->openFlag = 0;
+      return PPPERR_OPEN;
+    }
+
+    pppoe_connect(pc->pppoe_sc);
+
+    if(!linkStatusCB) {
+      while(pd >= 0 && !pc->if_up) {
+        sys_msleep(500);
+        if (lcp_phase[pd] == PHASE_DEAD) {
+          pppClose(pd);
+          if (pc->errCode) {
+            pd = pc->errCode;
+          } else {
+            pd = PPPERR_CONNECT;
+          }
+        }
+      }
+    }
+  }
+
+  return pd;
+}
+#endif /* PPPOE_SUPPORT */
+
+
+/* Close a PPP connection and release the descriptor. 
+ * Any outstanding packets in the queues are dropped.
+ * Return 0 on success, an error code on failure. */
+int
+pppClose(int pd)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 0;
+
+  /* Disconnect */
+#if PPPOE_SUPPORT
+  if(pc->ethif) {
+    PPPDEBUG((LOG_DEBUG, "pppClose: unit %d kill_link -> pppStopCB\n", pd));
+    pc->errCode = PPPERR_USER;
+    /* This will leave us at PHASE_DEAD. */
+    tcpip_callback(pppStopCB, (void*)pd);
+  } else
+#endif /* PPPOE_SUPPORT */
+  {
+#if PPPOS_SUPPORT
+    pc->kill_link = !0;
+    pppMainWakeup(pd);
+#endif /* PPPOS_SUPPORT */
+  }
+
+  if(!pc->linkStatusCB) {
+    while(st >= 0 && lcp_phase[pd] != PHASE_DEAD) {
+      sys_msleep(500);
+      break;
+    }
+  }
+
+  return st;
+}
+
+/* This function is called when carrier is lost on the PPP channel. */
+void
+pppSigHUP(int pd)
+{
+  PPPControl *pc = &pppControl[pd];
+
+#if PPPOE_SUPPORT
+  if(pc->ethif) {
+    PPPDEBUG((LOG_DEBUG, "pppSigHUP: unit %d sig_hup -> pppHupCB\n", pd));
+    tcpip_callback(pppHupCB, (void*)pd);
+  } else
+#endif /* PPPOE_SUPPORT */
+  {
+#if PPPOS_SUPPORT
+    pc->sig_hup = 1;
+    pppMainWakeup(pd);
+#endif /* PPPOS_SUPPORT */
+  }
+}
+
+#if PPPOS_SUPPORT
+static void
+nPut(PPPControl *pc, struct pbuf *nb)
+{
+  struct pbuf *b;
+  int c;
+
+  for(b = nb; b != NULL; b = b->next) {
+    if((c = sio_write(pc->fd, b->payload, b->len)) != b->len) {
+      PPPDEBUG((LOG_WARNING,
+               "PPP nPut: incomplete sio_write(%d,, %u) = %d\n", pc->fd, b->len, c));
+      LINK_STATS_INC(link.err);
+      pc->lastXMit = 0; /* prepend PPP_FLAG to next packet */
+      break;
+    }
+  }
+
+  pbuf_free(nb);
+  LINK_STATS_INC(link.xmit);
+}
+
+/* 
+ * pppAppend - append given character to end of given pbuf.  If outACCM
+ * is not NULL and the character needs to be escaped, do so.
+ * If pbuf is full, append another.
+ * Return the current pbuf.
+ */
+static struct pbuf *
+pppAppend(u_char c, struct pbuf *nb, ext_accm *outACCM)
+{
+  struct pbuf *tb = nb;
+  
+  /* Make sure there is room for the character and an escape code.
+   * Sure we don't quite fill the buffer if the character doesn't
+   * get escaped but is one character worth complicating this? */
+  /* Note: We assume no packet header. */
+  if (nb && (PBUF_POOL_BUFSIZE - nb->len) < 2) {
+    tb = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+    if (tb) {
+      nb->next = tb;
+    } else {
+      LINK_STATS_INC(link.memerr);
+    }
+    nb = tb;
+  }
+
+  if (nb) {
+    if (outACCM && ESCAPE_P(*outACCM, c)) {
+      *((u_char*)nb->payload + nb->len++) = PPP_ESCAPE;
+      *((u_char*)nb->payload + nb->len++) = c ^ PPP_TRANS;
+    } else {
+      *((u_char*)nb->payload + nb->len++) = c;
+    }
+  }
+
+  return tb;
+}
+#endif /* PPPOS_SUPPORT */
+
+#if PPPOE_SUPPORT
+static err_t
+pppifOutputOverEthernet(int pd, struct pbuf *p)
+{
+  PPPControl *pc = &pppControl[pd];
+  struct pbuf *pb;
+  u_short protocol = PPP_IP;
+  int i=0;
+
+  pb = pbuf_alloc(PBUF_LINK, pppoe_hdrlen + sizeof(protocol), PBUF_RAM);
+  if(!pb) {
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.proterr);
+    return ERR_MEM;
+  }
+
+  pbuf_header(pb, -pppoe_hdrlen);
+
+  pc->lastXMit = sys_jiffies();
+
+  if (!pc->pcomp || protocol > 0xFF) {
+    *((u_char*)pb->payload + i++) = (protocol >> 8) & 0xFF;
+  }
+  *((u_char*)pb->payload + i) = protocol & 0xFF;
+
+  pbuf_chain(pb, p);
+
+  if(pppoe_xmit(pc->pppoe_sc, pb) != ERR_OK) {
+    LINK_STATS_INC(link.err);
+    return PPPERR_DEVICE;
+  }
+
+  LINK_STATS_INC(link.xmit);
+  return ERR_OK;
+}
+#endif /* PPPOE_SUPPORT */
+
+/* Send a packet on the given connection. */
+static err_t
+pppifOutput(struct netif *netif, struct pbuf *pb, struct ip_addr *ipaddr)
+{
+  int pd = (int)netif->state;
+  PPPControl *pc = &pppControl[pd];
+#if PPPOS_SUPPORT
+  u_short protocol = PPP_IP;
+  u_int fcsOut = PPP_INITFCS;
+  struct pbuf *headMB = NULL, *tailMB = NULL, *p;
+  u_char c;
+#endif /* PPPOS_SUPPORT */
+
+  LWIP_UNUSED_ARG(ipaddr);
+
+  /* Validate parameters. */
+  /* We let any protocol value go through - it can't hurt us
+   * and the peer will just drop it if it's not accepting it. */
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag || !pb) {
+    PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad parms prot=%d pb=%p\n",
+              pd, PPP_IP, pb));
+    LINK_STATS_INC(link.opterr);
+    LINK_STATS_INC(link.drop);
+    return ERR_ARG;
+  }
+
+  /* Check that the link is up. */
+  if (lcp_phase[pd] == PHASE_DEAD) {
+    PPPDEBUG((LOG_ERR, "pppifOutput[%d]: link not up\n", pd));
+    LINK_STATS_INC(link.rterr);
+    LINK_STATS_INC(link.drop);
+    return ERR_RTE;
+  }
+
+#if PPPOE_SUPPORT
+  if(pc->ethif) {
+    return pppifOutputOverEthernet(pd, pb);
+  }
+#endif /* PPPOE_SUPPORT */
+
+#if PPPOS_SUPPORT
+  /* Grab an output buffer. */
+  headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+  if (headMB == NULL) {
+    PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: first alloc fail\n", pd));
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.drop);
+    return ERR_MEM;
+  }
+
+#if VJ_SUPPORT
+  /* 
+   * Attempt Van Jacobson header compression if VJ is configured and
+   * this is an IP packet. 
+   */
+  if (protocol == PPP_IP && pc->vjEnabled) {
+    switch (vj_compress_tcp(&pc->vjComp, pb)) {
+      case TYPE_IP:
+        /* No change...
+           protocol = PPP_IP_PROTOCOL; */
+        break;
+      case TYPE_COMPRESSED_TCP:
+        protocol = PPP_VJC_COMP;
+        break;
+      case TYPE_UNCOMPRESSED_TCP:
+        protocol = PPP_VJC_UNCOMP;
+        break;
+      default:
+        PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad IP packet\n", pd));
+        LINK_STATS_INC(link.proterr);
+        LINK_STATS_INC(link.drop);
+        pbuf_free(headMB);
+        return ERR_VAL;
+    }
+  }
+#endif /* VJ_SUPPORT */
+
+  tailMB = headMB;
+
+  /* Build the PPP header. */
+  if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG) {
+    tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+  }
+
+  pc->lastXMit = sys_jiffies();
+  if (!pc->accomp) {
+    fcsOut = PPP_FCS(fcsOut, PPP_ALLSTATIONS);
+    tailMB = pppAppend(PPP_ALLSTATIONS, tailMB, &pc->outACCM);
+    fcsOut = PPP_FCS(fcsOut, PPP_UI);
+    tailMB = pppAppend(PPP_UI, tailMB, &pc->outACCM);
+  }
+  if (!pc->pcomp || protocol > 0xFF) {
+    c = (protocol >> 8) & 0xFF;
+    fcsOut = PPP_FCS(fcsOut, c);
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+  }
+  c = protocol & 0xFF;
+  fcsOut = PPP_FCS(fcsOut, c);
+  tailMB = pppAppend(c, tailMB, &pc->outACCM);
+
+  /* Load packet. */
+  for(p = pb; p; p = p->next) {
+    int n;
+    u_char *sPtr;
+
+    sPtr = (u_char*)p->payload;
+    n = p->len;
+    while (n-- > 0) {
+      c = *sPtr++;
+
+      /* Update FCS before checking for special characters. */
+      fcsOut = PPP_FCS(fcsOut, c);
+      
+      /* Copy to output buffer escaping special characters. */
+      tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    }
+  }
+
+  /* Add FCS and trailing flag. */
+  c = ~fcsOut & 0xFF;
+  tailMB = pppAppend(c, tailMB, &pc->outACCM);
+  c = (~fcsOut >> 8) & 0xFF;
+  tailMB = pppAppend(c, tailMB, &pc->outACCM);
+  tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+
+  /* If we failed to complete the packet, throw it away. */
+  if (!tailMB) {
+    PPPDEBUG((LOG_WARNING,
+             "pppifOutput[%d]: Alloc err - dropping proto=%d\n", 
+              pd, protocol));
+    pbuf_free(headMB);
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.drop);
+    return ERR_MEM;
+  }
+
+  /* Send it. */
+  PPPDEBUG((LOG_INFO, "pppifOutput[%d]: proto=0x%04X\n", pd, protocol));
+
+  nPut(pc, headMB);
+#endif /* PPPOS_SUPPORT */
+
+  return ERR_OK;
+}
+
+/* Get and set parameters for the given connection.
+ * Return 0 on success, an error code on failure. */
+int
+pppIOCtl(int pd, int cmd, void *arg)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 0;
+
+  if (pd < 0 || pd >= NUM_PPP) {
+    st = PPPERR_PARAM;
+  } else {
+    switch(cmd) {
+    case PPPCTLG_UPSTATUS:      /* Get the PPP up status. */
+      if (arg) {
+        *(int *)arg = (int)(pc->if_up);
+      } else {
+        st = PPPERR_PARAM;
+      }
+      break;
+    case PPPCTLS_ERRCODE:       /* Set the PPP error code. */
+      if (arg) {
+        pc->errCode = *(int *)arg;
+      } else {
+        st = PPPERR_PARAM;
+      }
+      break;
+    case PPPCTLG_ERRCODE:       /* Get the PPP error code. */
+      if (arg) {
+        *(int *)arg = (int)(pc->errCode);
+      } else {
+        st = PPPERR_PARAM;
+      }
+      break;
+#if PPPOS_SUPPORT
+    case PPPCTLG_FD:
+      if (arg) {
+        *(sio_fd_t *)arg = pc->fd;
+      } else {
+        st = PPPERR_PARAM;
+      }
+      break;
+#endif /* PPPOS_SUPPORT */
+    default:
+      st = PPPERR_PARAM;
+      break;
+    }
+  }
+
+  return st;
+}
+
+/*
+ * Return the Maximum Transmission Unit for the given PPP connection.
+ */
+u_int
+pppMTU(int pd)
+{
+  PPPControl *pc = &pppControl[pd];
+  u_int st;
+
+  /* Validate parameters. */
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+    st = 0;
+  } else {
+    st = pc->mtu;
+  }
+
+  return st;
+}
+
+#if PPPOE_SUPPORT
+int
+pppWriteOverEthernet(int pd, const u_char *s, int n)
+{
+  PPPControl *pc = &pppControl[pd];
+  struct pbuf *pb;
+
+  /* skip address & flags */
+  s += 2;
+  n -= 2;
+
+  pb = pbuf_alloc(PBUF_LINK, pppoe_hdrlen + n, PBUF_RAM);
+  if(!pb) {
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.proterr);
+    return PPPERR_ALLOC;
+  }
+
+  pbuf_header(pb, -pppoe_hdrlen);
+
+  pc->lastXMit = sys_jiffies();
+
+  MEMCPY(pb->payload, s, n);
+
+  if(pppoe_xmit(pc->pppoe_sc, pb) != ERR_OK) {
+    LINK_STATS_INC(link.err);
+    return PPPERR_DEVICE;
+  }
+
+  LINK_STATS_INC(link.xmit);
+  return PPPERR_NONE;
+}
+#endif /* PPPOE_SUPPORT */
+
+/*
+ * Write n characters to a ppp link.
+ *  RETURN: >= 0 Number of characters written
+ *           -1 Failed to write to device
+ */
+int
+pppWrite(int pd, const u_char *s, int n)
+{
+  PPPControl *pc = &pppControl[pd];
+#if PPPOS_SUPPORT
+  u_char c;
+  u_int fcsOut;
+  struct pbuf *headMB, *tailMB;
+#endif /* PPPOS_SUPPORT */
+
+#if PPPOE_SUPPORT
+  if(pc->ethif) {
+    return pppWriteOverEthernet(pd, s, n);
+  }
+#endif /* PPPOE_SUPPORT */
+
+#if PPPOS_SUPPORT
+  headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+  if (headMB == NULL) {
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.proterr);
+    return PPPERR_ALLOC;
+  }
+
+  tailMB = headMB;
+
+  /* If the link has been idle, we'll send a fresh flag character to
+   * flush any noise. */
+  if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG) {
+    tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+  }
+  pc->lastXMit = sys_jiffies();
+
+  fcsOut = PPP_INITFCS;
+  /* Load output buffer. */
+  while (n-- > 0) {
+    c = *s++;
+
+    /* Update FCS before checking for special characters. */
+    fcsOut = PPP_FCS(fcsOut, c);
+
+    /* Copy to output buffer escaping special characters. */
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+  }
+    
+  /* Add FCS and trailing flag. */
+  c = ~fcsOut & 0xFF;
+  tailMB = pppAppend(c, tailMB, &pc->outACCM);
+  c = (~fcsOut >> 8) & 0xFF;
+  tailMB = pppAppend(c, tailMB, &pc->outACCM);
+  tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+
+  /* If we failed to complete the packet, throw it away.
+   * Otherwise send it. */
+  if (!tailMB) {
+    PPPDEBUG((LOG_WARNING,
+             "pppWrite[%d]: Alloc err - dropping pbuf len=%d\n", pd, headMB->len));
+           /*"pppWrite[%d]: Alloc err - dropping %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */
+    pbuf_free(headMB);
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.proterr);
+    return PPPERR_ALLOC;
+  }
+
+  PPPDEBUG((LOG_INFO, "pppWrite[%d]: len=%d\n", pd, headMB->len));
+                   /* "pppWrite[%d]: %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */
+  nPut(pc, headMB);
+#endif /* PPPOS_SUPPORT */
+
+  return PPPERR_NONE;
+}
+
+/*
+ * ppp_send_config - configure the transmit characteristics of
+ * the ppp interface.
+ */
+void
+ppp_send_config( int unit, int mtu, u32_t asyncmap, int pcomp, int accomp)
+{
+  PPPControl *pc = &pppControl[unit];
+  int i;
+  
+  pc->mtu = mtu;
+  pc->pcomp = pcomp;
+  pc->accomp = accomp;
+  
+  /* Load the ACCM bits for the 32 control codes. */
+  for (i = 0; i < 32/8; i++) {
+    pc->outACCM[i] = (u_char)((asyncmap >> (8 * i)) & 0xFF);
+  }
+  PPPDEBUG((LOG_INFO, "ppp_send_config[%d]: outACCM=%X %X %X %X\n",
+            unit,
+            pc->outACCM[0], pc->outACCM[1], pc->outACCM[2], pc->outACCM[3]));
+}
+
+
+/*
+ * ppp_set_xaccm - set the extended transmit ACCM for the interface.
+ */
+void
+ppp_set_xaccm(int unit, ext_accm *accm)
+{
+  SMEMCPY(pppControl[unit].outACCM, accm, sizeof(ext_accm));
+  PPPDEBUG((LOG_INFO, "ppp_set_xaccm[%d]: outACCM=%X %X %X %X\n",
+            unit,
+            pppControl[unit].outACCM[0],
+            pppControl[unit].outACCM[1],
+            pppControl[unit].outACCM[2],
+            pppControl[unit].outACCM[3]));
+}
+
+
+/*
+ * ppp_recv_config - configure the receive-side characteristics of
+ * the ppp interface.
+ */
+void
+ppp_recv_config( int unit, int mru, u32_t asyncmap, int pcomp, int accomp)
+{
+  PPPControl *pc = &pppControl[unit];
+  int i;
+
+  LWIP_UNUSED_ARG(accomp);
+  LWIP_UNUSED_ARG(pcomp);
+  LWIP_UNUSED_ARG(mru);
+
+  /* Load the ACCM bits for the 32 control codes. */
+  for (i = 0; i < 32 / 8; i++) {
+    pc->inACCM[i] = (u_char)(asyncmap >> (i * 8));
+  }
+  PPPDEBUG((LOG_INFO, "ppp_recv_config[%d]: inACCM=%X %X %X %X\n",
+            unit,
+            pc->inACCM[0], pc->inACCM[1], pc->inACCM[2], pc->inACCM[3]));
+}
+
+#if 0
+/*
+ * ccp_test - ask kernel whether a given compression method
+ * is acceptable for use.  Returns 1 if the method and parameters
+ * are OK, 0 if the method is known but the parameters are not OK
+ * (e.g. code size should be reduced), or -1 if the method is unknown.
+ */
+int
+ccp_test( int unit, int opt_len,  int for_transmit, u_char *opt_ptr)
+{
+  return 0; /* XXX Currently no compression. */
+}
+
+/*
+ * ccp_flags_set - inform kernel about the current state of CCP.
+ */
+void
+ccp_flags_set(int unit, int isopen, int isup)
+{
+  /* XXX */
+}
+
+/*
+ * ccp_fatal_error - returns 1 if decompression was disabled as a
+ * result of an error detected after decompression of a packet,
+ * 0 otherwise.  This is necessary because of patent nonsense.
+ */
+int
+ccp_fatal_error(int unit)
+{
+  /* XXX */
+  return 0;
+}
+#endif
+
+/*
+ * get_idle_time - return how long the link has been idle.
+ */
+int
+get_idle_time(int u, struct ppp_idle *ip)
+{
+  /* XXX */
+  LWIP_UNUSED_ARG(u);
+  LWIP_UNUSED_ARG(ip);
+
+  return 0;
+}
+
+
+/*
+ * Return user specified netmask, modified by any mask we might determine
+ * for address `addr' (in network byte order).
+ * Here we scan through the system's list of interfaces, looking for
+ * any non-point-to-point interfaces which might appear to be on the same
+ * network as `addr'.  If we find any, we OR in their netmask to the
+ * user-specified netmask.
+ */
+u32_t
+GetMask(u32_t addr)
+{
+  u32_t mask, nmask;
+
+  htonl(addr);
+  if (IN_CLASSA(addr)) { /* determine network mask for address class */
+    nmask = IN_CLASSA_NET;
+  } else if (IN_CLASSB(addr)) {
+    nmask = IN_CLASSB_NET;
+  } else { 
+    nmask = IN_CLASSC_NET;
+  }
+
+  /* class D nets are disallowed by bad_ip_adrs */
+  mask = subnetMask | htonl(nmask);
+  
+  /* XXX
+   * Scan through the system's network interfaces.
+   * Get each netmask and OR them into our mask.
+   */
+
+  return mask;
+}
+
+/*
+ * sifvjcomp - config tcp header compression
+ */
+int
+sifvjcomp(int pd, int vjcomp, int cidcomp, int maxcid)
+{
+#if PPPOS_SUPPORT && VJ_SUPPORT
+  PPPControl *pc = &pppControl[pd];
+  
+  pc->vjEnabled = vjcomp;
+  pc->vjComp.compressSlot = cidcomp;
+  pc->vjComp.maxSlotIndex = maxcid;
+  PPPDEBUG((LOG_INFO, "sifvjcomp: VJ compress enable=%d slot=%d max slot=%d\n",
+            vjcomp, cidcomp, maxcid));
+#else /* PPPOS_SUPPORT && VJ_SUPPORT */
+  LWIP_UNUSED_ARG(pd);
+  LWIP_UNUSED_ARG(vjcomp);
+  LWIP_UNUSED_ARG(cidcomp);
+  LWIP_UNUSED_ARG(maxcid);
+#endif /* PPPOS_SUPPORT && VJ_SUPPORT */
+
+  return 0;
+}
+
+/*
+ * pppifNetifInit - netif init callback
+ */
+static err_t
+pppifNetifInit(struct netif *netif)
+{
+  netif->name[0] = 'p';
+  netif->name[1] = 'p';
+  netif->output = pppifOutput;
+  netif->mtu = pppMTU((int)netif->state);
+  return ERR_OK;
+}
+
+
+/*
+ * sifup - Config the interface up and enable IP packets to pass.
+ */
+int
+sifup(int pd)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 1;
+  
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+    st = 0;
+    PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+  } else {
+    netif_remove(&pc->netif);
+    if (netif_add(&pc->netif, &pc->addrs.our_ipaddr, &pc->addrs.netmask, &pc->addrs.his_ipaddr, (void *)pd, pppifNetifInit, ip_input)) {
+      netif_set_up(&pc->netif);
+      pc->if_up = 1;
+      pc->errCode = PPPERR_NONE;
+
+      PPPDEBUG((LOG_DEBUG, "sifup: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+      if(pc->linkStatusCB) {
+        pc->linkStatusCB(pc->linkStatusCtx, pc->errCode, &pc->addrs);
+      }
+    } else {
+      st = 0;
+      PPPDEBUG((LOG_ERR, "sifup[%d]: netif_add failed\n", pd));
+    }
+  }
+
+  return st;
+}
+
+/*
+ * sifnpmode - Set the mode for handling packets for a given NP.
+ */
+int
+sifnpmode(int u, int proto, enum NPmode mode)
+{
+  LWIP_UNUSED_ARG(u);
+  LWIP_UNUSED_ARG(proto);
+  LWIP_UNUSED_ARG(mode);
+  return 0;
+}
+
+/*
+ * sifdown - Config the interface down and disable IP.
+ */
+int
+sifdown(int pd)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 1;
+  
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+    st = 0;
+    PPPDEBUG((LOG_WARNING, "sifdown[%d]: bad parms\n", pd));
+  } else {
+    pc->if_up = 0;
+    /* make sure the netif status callback is called */
+    netif_set_down(&pc->netif);
+    netif_remove(&pc->netif);
+    PPPDEBUG((LOG_DEBUG, "sifdown: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+    if(pc->linkStatusCB) {
+      pc->linkStatusCB(pc->linkStatusCtx, PPPERR_CONNECT, NULL);
+    }
+  }
+  return st;
+}
+
+/**
+ * sifaddr - Config the interface IP addresses and netmask.
+ * @param pd Interface unit ???
+ * @param o Our IP address ???
+ * @param h His IP address ???
+ * @param m IP subnet mask ???
+ * @param ns1 Primary DNS
+ * @param ns2 Secondary DNS
+ */
+int
+sifaddr( int pd, u32_t o, u32_t h, u32_t m, u32_t ns1, u32_t ns2)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 1;
+  
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+    st = 0;
+    PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+  } else {
+    SMEMCPY(&pc->addrs.our_ipaddr, &o, sizeof(o));
+    SMEMCPY(&pc->addrs.his_ipaddr, &h, sizeof(h));
+    SMEMCPY(&pc->addrs.netmask, &m, sizeof(m));
+    SMEMCPY(&pc->addrs.dns1, &ns1, sizeof(ns1));
+    SMEMCPY(&pc->addrs.dns2, &ns2, sizeof(ns2));
+  }
+  return st;
+}
+
+/**
+ * cifaddr - Clear the interface IP addresses, and delete routes
+ * through the interface if possible.
+ * @param pd Interface unit ???
+ * @param o Our IP address ???
+ * @param h IP broadcast address ???
+ */
+int
+cifaddr( int pd, u32_t o, u32_t h)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 1;
+  
+  LWIP_UNUSED_ARG(o);
+  LWIP_UNUSED_ARG(h);
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+    st = 0;
+    PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+  } else {
+    IP4_ADDR(&pc->addrs.our_ipaddr, 0,0,0,0);
+    IP4_ADDR(&pc->addrs.his_ipaddr, 0,0,0,0);
+    IP4_ADDR(&pc->addrs.netmask, 255,255,255,0);
+    IP4_ADDR(&pc->addrs.dns1, 0,0,0,0);
+    IP4_ADDR(&pc->addrs.dns2, 0,0,0,0);
+  }
+  return st;
+}
+
+/*
+ * sifdefaultroute - assign a default route through the address given.
+ */
+int
+sifdefaultroute(int pd, u32_t l, u32_t g)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 1;
+
+  LWIP_UNUSED_ARG(l);
+  LWIP_UNUSED_ARG(g);
+
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+    st = 0;
+    PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+  } else {
+    netif_set_default(&pc->netif);
+  }
+
+  /* TODO: check how PPP handled the netMask, previously not set by ipSetDefault */
+
+  return st;
+}
+
+/*
+ * cifdefaultroute - delete a default route through the address given.
+ */
+int
+cifdefaultroute(int pd, u32_t l, u32_t g)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 1;
+
+  LWIP_UNUSED_ARG(l);
+  LWIP_UNUSED_ARG(g);
+
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+    st = 0;
+    PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+  } else {
+    netif_set_default(NULL);
+  }
+
+  return st;
+}
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+
+#if PPPOS_SUPPORT
+/* The main PPP process function.  This implements the state machine according
+ * to section 4 of RFC 1661: The Point-To-Point Protocol. */
+static void
+pppMain(void *arg)
+{
+  int pd = (int)arg;
+  struct pbuf *p;
+  PPPControl* pc;
+  int c;
+
+  pc = &pppControl[pd];
+
+  p = pbuf_alloc(PBUF_RAW, PPP_MRU+PPP_HDRLEN, PBUF_RAM);
+  if (!p) {
+    LWIP_ASSERT("p != NULL", p);
+    pc->errCode = PPPERR_ALLOC;
+    goto out;
+  }
+
+  /*
+   * Start the connection and handle incoming events (packet or timeout).
+   */
+  PPPDEBUG((LOG_INFO, "pppMain: unit %d: Connecting\n", pd));
+  tcpip_callback(pppStartCB, arg);
+  while (lcp_phase[pd] != PHASE_DEAD) {
+    if (pc->kill_link) {
+      PPPDEBUG((LOG_DEBUG, "pppMain: unit %d kill_link -> pppStopCB\n", pd));
+      pc->errCode = PPPERR_USER;
+      /* This will leave us at PHASE_DEAD. */
+      tcpip_callback(pppStopCB, arg);
+      pc->kill_link = 0;
+    } else if (pc->sig_hup) {
+      PPPDEBUG((LOG_DEBUG, "pppMain: unit %d sig_hup -> pppHupCB\n", pd));
+      pc->sig_hup = 0;
+      tcpip_callback(pppHupCB, arg);
+    } else {
+      c = sio_read(pc->fd, p->payload, p->len);
+      if(c > 0) {
+        pppInProc(pd, p->payload, c);
+      } else {
+        /* nothing received, give other tasks a chance to run */
+        sys_msleep(1);
+      }
+    }
+  }
+  PPPDEBUG((LOG_INFO, "pppMain: unit %d: PHASE_DEAD\n", pd));
+  pppDrop(pc); /* bug fix #17726 */
+  pbuf_free(p);
+
+out:
+  PPPDEBUG((LOG_DEBUG, "pppMain: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+  if(pc->linkStatusCB) {
+    pc->linkStatusCB(pc->linkStatusCtx, pc->errCode ? pc->errCode : PPPERR_PROTOCOL, NULL);
+  }
+
+  pc->openFlag = 0;
+}
+#endif /* PPPOS_SUPPORT */
+
+#if PPPOE_SUPPORT
+
+void
+pppOverEthernetInitFailed(void* arg)
+{
+  PPPControl* pc;
+  int pd = (int)arg;
+
+  pppHupCB(arg);
+  pppStopCB(arg);
+
+  pc = &pppControl[pd];
+  pppoe_destroy(&pc->netif);
+  pc->openFlag = 0;
+
+  if(pc->linkStatusCB) {
+    pc->linkStatusCB(pc->linkStatusCtx, pc->errCode ? pc->errCode : PPPERR_PROTOCOL, NULL);
+  }
+}
+
+static void
+pppOverEthernetLinkStatusCB(int pd, int up)
+{
+  if(up) {
+    PPPDEBUG((LOG_INFO, "pppMain: unit %d: Connecting\n", pd));
+    tcpip_callback(pppStartCB, (void*)pd);
+  } else {
+    PPPControl* pc;
+    pc = &pppControl[pd];
+    tcpip_callback(pppOverEthernetInitFailed, (void*)pd);
+  }
+}
+#endif /* PPPOE_SUPPORT */
+
+struct pbuf *
+pppSingleBuf(struct pbuf *p)
+{
+  struct pbuf *q, *b;
+  u_char *pl;
+
+  if(p->tot_len == p->len) {
+    return p;
+  }
+
+  q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
+  if(!q) {
+    PPPDEBUG((LOG_ERR,
+             "pppSingleBuf: unable to alloc new buf (%d)\n", p->tot_len));
+    return p; /* live dangerously */
+  }
+
+  for(b = p, pl = q->payload; b != NULL; b = b->next) {
+    MEMCPY(pl, b->payload, b->len);
+    pl += b->len;
+  }
+
+  pbuf_free(p);
+
+  return q;
+}
+
+struct pppInputHeader {
+  int unit;
+  u16_t proto;
+};
+
+/*
+ * Pass the processed input packet to the appropriate handler.
+ * This function and all handlers run in the context of the tcpip_thread
+ */
+static void
+pppInput(void *arg)
+{
+  struct pbuf *nb = (struct pbuf *)arg;
+  u16_t protocol;
+  int pd;
+
+  pd = ((struct pppInputHeader *)nb->payload)->unit;
+  protocol = ((struct pppInputHeader *)nb->payload)->proto;
+    
+  if(pbuf_header(nb, -(int)sizeof(struct pppInputHeader))) {
+    LWIP_ASSERT("pbuf_header failed\n", 0);
+    goto drop;
+  }
+
+  LINK_STATS_INC(link.recv);
+
+  /*
+   * Toss all non-LCP packets unless LCP is OPEN.
+   * Until we get past the authentication phase, toss all packets
+   * except LCP, LQR and authentication packets.
+   */
+  if((lcp_phase[pd] <= PHASE_AUTHENTICATE) && (protocol != PPP_LCP)) {
+    if(!((protocol == PPP_LQR) || (protocol == PPP_PAP) || (protocol == PPP_CHAP)) ||
+        (lcp_phase[pd] != PHASE_AUTHENTICATE)) {
+      PPPDEBUG((LOG_INFO, "pppInput: discarding proto 0x%04X in phase %d\n", protocol, lcp_phase[pd]));
+      goto drop;
+    }
+  }
+
+  switch(protocol) {
+    case PPP_VJC_COMP:      /* VJ compressed TCP */
+#if PPPOS_SUPPORT && VJ_SUPPORT
+      PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_comp in pbuf len=%d\n", pd, nb->len));
+      /*
+       * Clip off the VJ header and prepend the rebuilt TCP/IP header and
+       * pass the result to IP.
+       */
+      if ((vj_uncompress_tcp(&nb, &pppControl[pd].vjComp) >= 0) && (pppControl[pd].netif.input)) {
+        pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+        return;
+      }
+      /* Something's wrong so drop it. */
+      PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ compressed\n", pd));
+#else  /* PPPOS_SUPPORT && VJ_SUPPORT */
+      /* No handler for this protocol so drop the packet. */
+      PPPDEBUG((LOG_INFO, "pppInput[%d]: drop VJ Comp in %d:%s\n", pd, nb->len, nb->payload));
+#endif /* PPPOS_SUPPORT && VJ_SUPPORT */
+      break;
+
+    case PPP_VJC_UNCOMP:    /* VJ uncompressed TCP */
+#if PPPOS_SUPPORT && VJ_SUPPORT
+      PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_un in pbuf len=%d\n", pd, nb->len));
+      /*
+       * Process the TCP/IP header for VJ header compression and then pass
+       * the packet to IP.
+       */
+      if ((vj_uncompress_uncomp(nb, &pppControl[pd].vjComp) >= 0) && pppControl[pd].netif.input) {
+        pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+        return;
+      }
+      /* Something's wrong so drop it. */
+      PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ uncompressed\n", pd));
+#else  /* PPPOS_SUPPORT && VJ_SUPPORT */
+      /* No handler for this protocol so drop the packet. */
+      PPPDEBUG((LOG_INFO,
+               "pppInput[%d]: drop VJ UnComp in %d:.*H\n", 
+                pd, nb->len, LWIP_MIN(nb->len * 2, 40), nb->payload));
+#endif /* PPPOS_SUPPORT && VJ_SUPPORT */
+      break;
+
+    case PPP_IP:            /* Internet Protocol */
+      PPPDEBUG((LOG_INFO, "pppInput[%d]: ip in pbuf len=%d\n", pd, nb->len));
+      if (pppControl[pd].netif.input) {
+        pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+        return;
+      }
+      break;
+
+    default: {
+      struct protent *protp;
+      int i;
+
+      /*
+       * Upcall the proper protocol input routine.
+       */
+      for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+        if (protp->protocol == protocol && protp->enabled_flag) {
+          PPPDEBUG((LOG_INFO, "pppInput[%d]: %s len=%d\n", pd, protp->name, nb->len));
+          nb = pppSingleBuf(nb);
+          (*protp->input)(pd, nb->payload, nb->len);
+          goto out;
+        }
+      }
+
+      /* No handler for this protocol so reject the packet. */
+      PPPDEBUG((LOG_INFO, "pppInput[%d]: rejecting unsupported proto 0x%04X len=%d\n", pd, protocol, nb->len));
+      if (pbuf_header(nb, sizeof(protocol))) {
+        LWIP_ASSERT("pbuf_header failed\n", 0);
+        goto drop;
+      }
+#if BYTE_ORDER == LITTLE_ENDIAN
+      protocol = htons(protocol);
+      SMEMCPY(nb->payload, &protocol, sizeof(protocol));
+#endif /* BYTE_ORDER == LITTLE_ENDIAN */
+      lcp_sprotrej(pd, nb->payload, nb->len);
+    }
+    break;
+  }
+
+drop:
+  LINK_STATS_INC(link.drop);
+
+out:
+  pbuf_free(nb);
+  return;
+}
+
+#if PPPOS_SUPPORT
+/*
+ * Drop the input packet.
+ */
+static void
+pppDrop(PPPControl *pc)
+{
+  if (pc->inHead != NULL) {
+#if 0
+    PPPDEBUG((LOG_INFO, "pppDrop: %d:%.*H\n", pc->inHead->len, min(60, pc->inHead->len * 2), pc->inHead->payload));
+#endif
+    PPPDEBUG((LOG_INFO, "pppDrop: pbuf len=%d\n", pc->inHead->len));
+    if (pc->inTail && (pc->inTail != pc->inHead)) {
+      pbuf_free(pc->inTail);
+    }
+    pbuf_free(pc->inHead);
+    pc->inHead = NULL;
+    pc->inTail = NULL;
+  }
+#if VJ_SUPPORT
+  vj_uncompress_err(&pc->vjComp);
+#endif /* VJ_SUPPORT */
+
+  LINK_STATS_INC(link.drop);
+}
+
+/**
+ * Process a received octet string.
+ */
+static void
+pppInProc(int pd, u_char *s, int l)
+{
+  PPPControl *pc = &pppControl[pd];
+  struct pbuf *nextNBuf;
+  u_char curChar;
+
+  PPPDEBUG((LOG_DEBUG, "pppInProc[%d]: got %d bytes\n", pd, l));
+  while (l-- > 0) {
+    curChar = *s++;
+    
+    /* Handle special characters. */
+    if (ESCAPE_P(pc->inACCM, curChar)) {
+      /* Check for escape sequences. */
+      /* XXX Note that this does not handle an escaped 0x5d character which
+       * would appear as an escape character.  Since this is an ASCII ']'
+       * and there is no reason that I know of to escape it, I won't complicate
+       * the code to handle this case. GLL */
+      if (curChar == PPP_ESCAPE) {
+        pc->inEscaped = 1;
+      /* Check for the flag character. */
+      } else if (curChar == PPP_FLAG) {
+         /* If this is just an extra flag character, ignore it. */
+         if (pc->inState <= PDADDRESS) {
+           /* ignore it */;
+         /* If we haven't received the packet header, drop what has come in. */
+         } else if (pc->inState < PDDATA) {
+           PPPDEBUG((LOG_WARNING,
+                    "pppInProc[%d]: Dropping incomplete packet %d\n", 
+                     pd, pc->inState));
+           LINK_STATS_INC(link.lenerr);
+           pppDrop(pc);
+         /* If the fcs is invalid, drop the packet. */
+         } else if (pc->inFCS != PPP_GOODFCS) {
+           PPPDEBUG((LOG_INFO,
+                    "pppInProc[%d]: Dropping bad fcs 0x%04X proto=0x%04X\n", 
+                     pd, pc->inFCS, pc->inProtocol));
+           LINK_STATS_INC(link.chkerr);
+           pppDrop(pc);
+         /* Otherwise it's a good packet so pass it on. */
+         } else {
+           /* Trim off the checksum. */
+           if(pc->inTail->len >= 2) {
+             pc->inTail->len -= 2;
+
+             pc->inTail->tot_len = pc->inTail->len;
+             if (pc->inTail != pc->inHead) {
+               pbuf_cat(pc->inHead, pc->inTail);
+             }
+           } else {
+             pc->inTail->tot_len = pc->inTail->len;
+             if (pc->inTail != pc->inHead) {
+               pbuf_cat(pc->inHead, pc->inTail);
+             }
+
+             pbuf_realloc(pc->inHead, pc->inHead->tot_len - 2);
+           }
+
+           /* Dispatch the packet thereby consuming it. */
+           if(tcpip_callback(pppInput, pc->inHead) != ERR_OK) {
+             PPPDEBUG((LOG_ERR, "pppInProc[%d]: tcpip_callback() failed, dropping packet\n", pd));
+             pbuf_free(pc->inHead);
+             LINK_STATS_INC(link.drop);
+           }
+           pc->inHead = NULL;
+           pc->inTail = NULL;
+         }
+
+         /* Prepare for a new packet. */
+         pc->inFCS = PPP_INITFCS;
+         pc->inState = PDADDRESS;
+         pc->inEscaped = 0;
+      /* Other characters are usually control characters that may have
+       * been inserted by the physical layer so here we just drop them. */
+      } else {
+        PPPDEBUG((LOG_WARNING,
+                 "pppInProc[%d]: Dropping ACCM char <%d>\n", pd, curChar));
+      }
+    /* Process other characters. */
+    } else {
+      /* Unencode escaped characters. */
+      if (pc->inEscaped) {
+        pc->inEscaped = 0;
+        curChar ^= PPP_TRANS;
+      }
+
+      /* Process character relative to current state. */
+      switch(pc->inState) {
+        case PDIDLE:                    /* Idle state - waiting. */
+          /* Drop the character if it's not 0xff
+           * we would have processed a flag character above. */
+          if (curChar != PPP_ALLSTATIONS) {
+            break;
+          }
+
+        /* Fall through */
+        case PDSTART:                   /* Process start flag. */
+          /* Prepare for a new packet. */
+          pc->inFCS = PPP_INITFCS;
+
+        /* Fall through */
+        case PDADDRESS:                 /* Process address field. */
+          if (curChar == PPP_ALLSTATIONS) {
+            pc->inState = PDCONTROL;
+            break;
+          }
+          /* Else assume compressed address and control fields so
+           * fall through to get the protocol... */
+        case PDCONTROL:                 /* Process control field. */
+          /* If we don't get a valid control code, restart. */
+          if (curChar == PPP_UI) {
+            pc->inState = PDPROTOCOL1;
+            break;
+          }
+#if 0
+          else {
+            PPPDEBUG((LOG_WARNING,
+                     "pppInProc[%d]: Invalid control <%d>\n", pd, curChar));
+                      pc->inState = PDSTART;
+          }
+#endif
+        case PDPROTOCOL1:               /* Process protocol field 1. */
+          /* If the lower bit is set, this is the end of the protocol
+           * field. */
+          if (curChar & 1) {
+            pc->inProtocol = curChar;
+            pc->inState = PDDATA;
+          } else {
+            pc->inProtocol = (u_int)curChar << 8;
+            pc->inState = PDPROTOCOL2;
+          }
+          break;
+        case PDPROTOCOL2:               /* Process protocol field 2. */
+          pc->inProtocol |= curChar;
+          pc->inState = PDDATA;
+          break;
+        case PDDATA:                    /* Process data byte. */
+          /* Make space to receive processed data. */
+          if (pc->inTail == NULL || pc->inTail->len == PBUF_POOL_BUFSIZE) {
+            if(pc->inTail) {
+              pc->inTail->tot_len = pc->inTail->len;
+              if (pc->inTail != pc->inHead) {
+                pbuf_cat(pc->inHead, pc->inTail);
+              }
+            }
+            /* If we haven't started a packet, we need a packet header. */
+            nextNBuf = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+            if (nextNBuf == NULL) {
+              /* No free buffers.  Drop the input packet and let the
+               * higher layers deal with it.  Continue processing
+               * the received pbuf chain in case a new packet starts. */
+              PPPDEBUG((LOG_ERR, "pppInProc[%d]: NO FREE MBUFS!\n", pd));
+              LINK_STATS_INC(link.memerr);
+              pppDrop(pc);
+              pc->inState = PDSTART;  /* Wait for flag sequence. */
+              break;
+            }
+            if (pc->inHead == NULL) {
+              struct pppInputHeader *pih = nextNBuf->payload;
+
+              pih->unit = pd;
+              pih->proto = pc->inProtocol;
+
+              nextNBuf->len += sizeof(*pih);
+
+              pc->inHead = nextNBuf;
+            }
+            pc->inTail = nextNBuf;
+          }
+          /* Load character into buffer. */
+          ((u_char*)pc->inTail->payload)[pc->inTail->len++] = curChar;
+          break;
+      }
+
+      /* update the frame check sequence number. */
+      pc->inFCS = PPP_FCS(pc->inFCS, curChar);
+    }
+  }
+
+  avRandomize();
+}
+#endif /* PPPOS_SUPPORT */
+
+#if PPPOE_SUPPORT
+void
+pppInProcOverEthernet(int pd, struct pbuf *pb)
+{
+  struct pppInputHeader *pih;
+  u16_t inProtocol;
+
+  if(pb->len < sizeof(inProtocol)) {
+    PPPDEBUG((LOG_ERR, "pppInProcOverEthernet: too small for protocol field\n"));
+    goto drop;
+  }
+
+  inProtocol = (((u8_t *)pb->payload)[0] << 8) | ((u8_t*)pb->payload)[1];
+
+  /* make room for pppInputHeader - should not fail */
+  if (pbuf_header(pb, sizeof(*pih) - sizeof(inProtocol)) != 0) {
+    PPPDEBUG((LOG_ERR, "pppInProcOverEthernet: could not allocate room for header\n"));
+    goto drop;
+  }
+
+  pih = pb->payload;
+
+  pih->unit = pd;
+  pih->proto = inProtocol;
+
+  /* Dispatch the packet thereby consuming it. */
+  if(tcpip_callback(pppInput, pb) != ERR_OK) {
+    PPPDEBUG((LOG_ERR, "pppInProcOverEthernet[%d]: tcpip_callback() failed, dropping packet\n", pd));
+    goto drop;
+  }
+
+  return;
+
+drop:
+  LINK_STATS_INC(link.drop);
+  pbuf_free(pb);
+  return;
+}
+#endif /* PPPOE_SUPPORT */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/ppp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/ppp.h
new file mode 100644
index 0000000..ebc733b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/ppp.h
@@ -0,0 +1,465 @@
+/*****************************************************************************
+* ppp.h - Network Point to Point Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD codes.
+*****************************************************************************/
+
+#ifndef PPP_H
+#define PPP_H
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/def.h"
+#include "lwip/sio.h"
+#include "lwip/api.h"
+#include "lwip/sockets.h"
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+#include "lwip/tcpip.h"
+#include "lwip/netif.h"
+
+/*
+ * pppd.h - PPP daemon global declarations.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ */
+/*
+ * ppp_defs.h - PPP definitions.
+ *
+ * Copyright (c) 1994 The Australian National University.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, provided that the above copyright
+ * notice appears in all copies.  This software is provided without any
+ * warranty, express or implied. The Australian National University
+ * makes no representations about the suitability of this software for
+ * any purpose.
+ *
+ * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY
+ * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
+ * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
+ * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS,
+ * OR MODIFICATIONS.
+ */
+
+#define TIMEOUT(f, a, t)    sys_untimeout((f), (a)), sys_timeout((t)*1000, (f), (a))
+#define UNTIMEOUT(f, a)     sys_untimeout((f), (a))
+
+
+#ifndef __u_char_defined
+
+/* Type definitions for BSD code. */
+typedef unsigned long  u_long;
+typedef unsigned int   u_int;
+typedef unsigned short u_short;
+typedef unsigned char  u_char;
+
+#endif
+
+/*
+ * Constants and structures defined by the internet system,
+ * Per RFC 790, September 1981, and numerous additions.
+ */
+
+/*
+ * The basic PPP frame.
+ */
+#define PPP_HDRLEN      4       /* octets for standard ppp header */
+#define PPP_FCSLEN      2       /* octets for FCS */
+
+
+/*
+ * Significant octet values.
+ */
+#define PPP_ALLSTATIONS 0xff    /* All-Stations broadcast address */
+#define PPP_UI          0x03    /* Unnumbered Information */
+#define PPP_FLAG        0x7e    /* Flag Sequence */
+#define PPP_ESCAPE      0x7d    /* Asynchronous Control Escape */
+#define PPP_TRANS       0x20    /* Asynchronous transparency modifier */
+
+/*
+ * Protocol field values.
+ */
+#define PPP_IP          0x21    /* Internet Protocol */
+#define PPP_AT          0x29    /* AppleTalk Protocol */
+#define PPP_VJC_COMP    0x2d    /* VJ compressed TCP */
+#define PPP_VJC_UNCOMP  0x2f    /* VJ uncompressed TCP */
+#define PPP_COMP        0xfd    /* compressed packet */
+#define PPP_IPCP        0x8021  /* IP Control Protocol */
+#define PPP_ATCP        0x8029  /* AppleTalk Control Protocol */
+#define PPP_CCP         0x80fd  /* Compression Control Protocol */
+#define PPP_LCP         0xc021  /* Link Control Protocol */
+#define PPP_PAP         0xc023  /* Password Authentication Protocol */
+#define PPP_LQR         0xc025  /* Link Quality Report protocol */
+#define PPP_CHAP        0xc223  /* Cryptographic Handshake Auth. Protocol */
+#define PPP_CBCP        0xc029  /* Callback Control Protocol */
+
+/*
+ * Values for FCS calculations.
+ */
+#define PPP_INITFCS     0xffff  /* Initial FCS value */
+#define PPP_GOODFCS     0xf0b8  /* Good final FCS value */
+#define PPP_FCS(fcs, c) (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff])
+
+/*
+ * Extended asyncmap - allows any character to be escaped.
+ */
+typedef u_char  ext_accm[32];
+
+/*
+ * What to do with network protocol (NP) packets.
+ */
+enum NPmode {
+  NPMODE_PASS,        /* pass the packet through */
+  NPMODE_DROP,        /* silently drop the packet */
+  NPMODE_ERROR,       /* return an error */
+  NPMODE_QUEUE        /* save it up for later. */
+};
+
+/*
+ * Inline versions of get/put char/short/long.
+ * Pointer is advanced; we assume that both arguments
+ * are lvalues and will already be in registers.
+ * cp MUST be u_char *.
+ */
+#define GETCHAR(c, cp) { \
+    (c) = *(cp)++; \
+}
+#define PUTCHAR(c, cp) { \
+    *(cp)++ = (u_char) (c); \
+}
+
+
+#define GETSHORT(s, cp) { \
+    (s) = *(cp); (cp)++; (s) <<= 8; \
+    (s) |= *(cp); (cp)++; \
+}
+#define PUTSHORT(s, cp) { \
+    *(cp)++ = (u_char) ((s) >> 8); \
+    *(cp)++ = (u_char) (s & 0xff); \
+}
+
+#define GETLONG(l, cp) { \
+    (l) = *(cp); (cp)++; (l) <<= 8; \
+    (l) |= *(cp); (cp)++; (l) <<= 8; \
+    (l) |= *(cp); (cp)++; (l) <<= 8; \
+    (l) |= *(cp); (cp)++; \
+}
+#define PUTLONG(l, cp) { \
+    *(cp)++ = (u_char) ((l) >> 24); \
+    *(cp)++ = (u_char) ((l) >> 16); \
+    *(cp)++ = (u_char) ((l) >> 8); \
+    *(cp)++ = (u_char) (l); \
+}
+
+
+#define INCPTR(n, cp)   ((cp) += (n))
+#define DECPTR(n, cp)   ((cp) -= (n))
+
+#define BCMP(s0, s1, l)     memcmp((u_char *)(s0), (u_char *)(s1), (l))
+#define BCOPY(s, d, l)      MEMCPY((d), (s), (l))
+#define BZERO(s, n)         memset(s, 0, n)
+
+#if PPP_DEBUG
+#define PRINTMSG(m, l)  { m[l] = '\0'; ppp_trace(LOG_INFO, "Remote message: %s\n", m); }
+#else  /* PPP_DEBUG */
+#define PRINTMSG(m, l)
+#endif /* PPP_DEBUG */
+
+/*
+ * MAKEHEADER - Add PPP Header fields to a packet.
+ */
+#define MAKEHEADER(p, t) { \
+    PUTCHAR(PPP_ALLSTATIONS, p); \
+    PUTCHAR(PPP_UI, p); \
+    PUTSHORT(t, p); }
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+
+/* Error codes. */
+#define PPPERR_NONE      0 /* No error. */
+#define PPPERR_PARAM    -1 /* Invalid parameter. */
+#define PPPERR_OPEN     -2 /* Unable to open PPP session. */
+#define PPPERR_DEVICE   -3 /* Invalid I/O device for PPP. */
+#define PPPERR_ALLOC    -4 /* Unable to allocate resources. */
+#define PPPERR_USER     -5 /* User interrupt. */
+#define PPPERR_CONNECT  -6 /* Connection lost. */
+#define PPPERR_AUTHFAIL -7 /* Failed authentication challenge. */
+#define PPPERR_PROTOCOL -8 /* Failed to meet protocol. */
+
+/*
+ * PPP IOCTL commands.
+ */
+/*
+ * Get the up status - 0 for down, non-zero for up.  The argument must
+ * point to an int.
+ */
+#define PPPCTLG_UPSTATUS 100 /* Get the up status - 0 down else up */
+#define PPPCTLS_ERRCODE  101 /* Set the error code */
+#define PPPCTLG_ERRCODE  102 /* Get the error code */
+#define PPPCTLG_FD       103 /* Get the fd associated with the ppp */
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * The following struct gives the addresses of procedures to call
+ * for a particular protocol.
+ */
+struct protent {
+    u_short protocol;       /* PPP protocol number */
+    /* Initialization procedure */
+    void (*init) (int unit);
+    /* Process a received packet */
+    void (*input) (int unit, u_char *pkt, int len);
+    /* Process a received protocol-reject */
+    void (*protrej) (int unit);
+    /* Lower layer has come up */
+    void (*lowerup) (int unit);
+    /* Lower layer has gone down */
+    void (*lowerdown) (int unit);
+    /* Open the protocol */
+    void (*open) (int unit);
+    /* Close the protocol */
+    void (*close) (int unit, char *reason);
+#if 0
+    /* Print a packet in readable form */
+    int  (*printpkt) (u_char *pkt, int len,
+              void (*printer) (void *, char *, ...),
+              void *arg);
+    /* Process a received data packet */
+    void (*datainput) (int unit, u_char *pkt, int len);
+#endif
+    int  enabled_flag;      /* 0 iff protocol is disabled */
+    char *name;         /* Text name of protocol */
+#if 0
+    /* Check requested options, assign defaults */
+    void (*check_options) (u_long);
+    /* Configure interface for demand-dial */
+    int  (*demand_conf) (int unit);
+    /* Say whether to bring up link for this pkt */
+    int  (*active_pkt) (u_char *pkt, int len);
+#endif
+};
+
+/*
+ * The following structure records the time in seconds since
+ * the last NP packet was sent or received.
+ */
+struct ppp_idle {
+  u_short xmit_idle;      /* seconds since last NP packet sent */
+  u_short recv_idle;      /* seconds since last NP packet received */
+};
+
+struct ppp_settings {
+
+  u_int  disable_defaultip : 1;       /* Don't use hostname for default IP addrs */
+  u_int  auth_required     : 1;       /* Peer is required to authenticate */
+  u_int  explicit_remote   : 1;       /* remote_name specified with remotename opt */
+  u_int  refuse_pap        : 1;       /* Don't wanna auth. ourselves with PAP */
+  u_int  refuse_chap       : 1;       /* Don't wanna auth. ourselves with CHAP */
+  u_int  usehostname       : 1;       /* Use hostname for our_name */
+  u_int  usepeerdns        : 1;       /* Ask peer for DNS adds */
+
+  u_short idle_time_limit;            /* Shut down link if idle for this long */
+  int  maxconnect;                    /* Maximum connect time (seconds) */
+
+  char user       [MAXNAMELEN   + 1]; /* Username for PAP */
+  char passwd     [MAXSECRETLEN + 1]; /* Password for PAP, secret for CHAP */
+  char our_name   [MAXNAMELEN   + 1]; /* Our name for authentication purposes */
+  char remote_name[MAXNAMELEN   + 1]; /* Peer's name for authentication */
+};
+
+struct ppp_addrs {
+  struct ip_addr our_ipaddr, his_ipaddr, netmask, dns1, dns2;
+};
+
+/*****************************
+*** PUBLIC DATA STRUCTURES ***
+*****************************/
+
+/* Buffers for outgoing packets. */
+extern u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN];
+
+extern struct ppp_settings ppp_settings;
+
+extern struct protent *ppp_protocols[]; /* Table of pointers to supported protocols */
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+/* Initialize the PPP subsystem. */
+void pppInit(void);
+
+/* Warning: Using PPPAUTHTYPE_ANY might have security consequences.
+ * RFC 1994 says:
+ *
+ * In practice, within or associated with each PPP server, there is a
+ * database which associates "user" names with authentication
+ * information ("secrets").  It is not anticipated that a particular
+ * named user would be authenticated by multiple methods.  This would
+ * make the user vulnerable to attacks which negotiate the least secure
+ * method from among a set (such as PAP rather than CHAP).  If the same
+ * secret was used, PAP would reveal the secret to be used later with
+ * CHAP.
+ *
+ * Instead, for each user name there should be an indication of exactly
+ * one method used to authenticate that user name.  If a user needs to
+ * make use of different authentication methods under different
+ * circumstances, then distinct user names SHOULD be employed, each of
+ * which identifies exactly one authentication method.
+ *
+ */
+enum pppAuthType {
+    PPPAUTHTYPE_NONE,
+    PPPAUTHTYPE_ANY,
+    PPPAUTHTYPE_PAP,
+    PPPAUTHTYPE_CHAP
+};
+
+void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd);
+
+/*
+ * Open a new PPP connection using the given serial I/O device.
+ * This initializes the PPP control block but does not
+ * attempt to negotiate the LCP session.
+ * Return a new PPP connection descriptor on success or
+ * an error code (negative) on failure. 
+ */
+int pppOverSerialOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx);
+
+/*
+ * Open a new PPP Over Ethernet (PPPOE) connection.
+ */
+int pppOverEthernetOpen(struct netif *ethif, const char *service_name, const char *concentrator_name, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx);
+
+/* for source code compatibility */
+#define pppOpen(fd,cb,ls) pppOverSerialOpen(fd,cb,ls)
+
+/*
+ * Close a PPP connection and release the descriptor. 
+ * Any outstanding packets in the queues are dropped.
+ * Return 0 on success, an error code on failure. 
+ */
+int pppClose(int pd);
+
+/*
+ * Indicate to the PPP process that the line has disconnected.
+ */
+void pppSigHUP(int pd);
+
+/*
+ * Get and set parameters for the given connection.
+ * Return 0 on success, an error code on failure. 
+ */
+int  pppIOCtl(int pd, int cmd, void *arg);
+
+/*
+ * Return the Maximum Transmission Unit for the given PPP connection.
+ */
+u_int pppMTU(int pd);
+
+/*
+ * Write n characters to a ppp link.
+ * RETURN: >= 0 Number of characters written, -1 Failed to write to device.
+ */
+int pppWrite(int pd, const u_char *s, int n);
+
+void pppInProcOverEthernet(int pd, struct pbuf *pb);
+
+struct pbuf *pppSingleBuf(struct pbuf *p);
+
+void pppLinkTerminated(int pd);
+
+void pppLinkDown(int pd);
+
+void pppMainWakeup(int pd);
+
+/* Configure i/f transmit parameters */
+void ppp_send_config (int, int, u32_t, int, int);
+/* Set extended transmit ACCM */
+void ppp_set_xaccm (int, ext_accm *);
+/* Configure i/f receive parameters */
+void ppp_recv_config (int, int, u32_t, int, int);
+/* Find out how long link has been idle */
+int  get_idle_time (int, struct ppp_idle *);
+
+/* Configure VJ TCP header compression */
+int  sifvjcomp (int, int, int, int);
+/* Configure i/f down (for IP) */
+int  sifup (int);
+/* Set mode for handling packets for proto */
+int  sifnpmode (int u, int proto, enum NPmode mode);
+/* Configure i/f down (for IP) */
+int  sifdown (int);
+/* Configure IP addresses for i/f */
+int  sifaddr (int, u32_t, u32_t, u32_t, u32_t, u32_t);
+/* Reset i/f IP addresses */
+int  cifaddr (int, u32_t, u32_t);
+/* Create default route through i/f */
+int  sifdefaultroute (int, u32_t, u32_t);
+/* Delete default route through i/f */
+int  cifdefaultroute (int, u32_t, u32_t);
+
+/* Get appropriate netmask for address */
+u32_t GetMask (u32_t); 
+
+#endif /* PPP_SUPPORT */
+
+#endif /* PPP_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/ppp_oe.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/ppp_oe.c
new file mode 100644
index 0000000..5a8a45c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/ppp_oe.c
@@ -0,0 +1,1227 @@
+/*****************************************************************************
+* ppp_oe.c - PPP Over Ethernet implementation for lwIP.
+*
+* Copyright (c) 2006 by Marc Boucher, Services Informatiques (MBSI) inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 06-01-01 Marc Boucher 
+*   Ported to lwIP.
+*****************************************************************************/
+
+
+
+/* based on NetBSD: if_pppoe.c,v 1.64 2006/01/31 23:50:15 martin Exp */
+
+/*-
+ * Copyright (c) 2002 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Martin Husemann .
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "lwip/opt.h"
+
+#if PPPOE_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "lwip/sys.h"
+
+#include "netif/ppp_oe.h"
+#include "netif/etharp.h"
+
+#include 
+#include 
+
+/** @todo Replace this part with a simple list like other lwIP lists */
+#ifndef _SYS_QUEUE_H_
+#define _SYS_QUEUE_H_
+
+/*
+ * A list is headed by a single forward pointer (or an array of forward
+ * pointers for a hash table header). The elements are doubly linked
+ * so that an arbitrary element can be removed without a need to
+ * traverse the list. New elements can be added to the list before
+ * or after an existing element or at the head of the list. A list
+ * may only be traversed in the forward direction.
+ *
+ * For details on the use of these macros, see the queue(3) manual page.
+ */
+
+/*
+ * List declarations.
+ */
+#define  LIST_HEAD(name, type)                                                 \
+struct name {                                                                  \
+  struct type *lh_first;  /* first element */                                  \
+}
+
+#define  LIST_HEAD_INITIALIZER(head)                                           \
+  { NULL }
+
+#define  LIST_ENTRY(type)                                                      \
+struct {                                                                       \
+  struct type *le_next;  /* next element */                                    \
+  struct type **le_prev; /* address of previous next element */                \
+}
+
+/*
+ * List functions.
+ */
+
+#define  LIST_EMPTY(head)  ((head)->lh_first == NULL)
+
+#define  LIST_FIRST(head)  ((head)->lh_first)
+
+#define  LIST_FOREACH(var, head, field)                                        \
+  for ((var) = LIST_FIRST((head));                                             \
+      (var);                                                                   \
+      (var) = LIST_NEXT((var), field))
+
+#define  LIST_INIT(head) do {                                                  \
+  LIST_FIRST((head)) = NULL;                                                   \
+} while (0)
+
+#define  LIST_INSERT_AFTER(listelm, elm, field) do {                           \
+  if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)         \
+    LIST_NEXT((listelm), field)->field.le_prev =                               \
+        &LIST_NEXT((elm), field);                                              \
+  LIST_NEXT((listelm), field) = (elm);                                         \
+  (elm)->field.le_prev = &LIST_NEXT((listelm), field);                         \
+} while (0)
+
+#define  LIST_INSERT_BEFORE(listelm, elm, field) do {                          \
+  (elm)->field.le_prev = (listelm)->field.le_prev;                             \
+  LIST_NEXT((elm), field) = (listelm);                                         \
+  *(listelm)->field.le_prev = (elm);                                           \
+  (listelm)->field.le_prev = &LIST_NEXT((elm), field);                         \
+} while (0)
+
+#define  LIST_INSERT_HEAD(head, elm, field) do {                               \
+  if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL)                  \
+    LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);              \
+  LIST_FIRST((head)) = (elm);                                                  \
+  (elm)->field.le_prev = &LIST_FIRST((head));                                  \
+} while (0)
+
+#define  LIST_NEXT(elm, field)  ((elm)->field.le_next)
+
+#define  LIST_REMOVE(elm, field) do {                                          \
+  if (LIST_NEXT((elm), field) != NULL)                                         \
+    LIST_NEXT((elm), field)->field.le_prev =                                   \
+        (elm)->field.le_prev;                                                  \
+  *(elm)->field.le_prev = LIST_NEXT((elm), field);                             \
+} while (0)
+
+#endif /* !_SYS_QUEUE_H_ */
+
+
+/* Add a 16 bit unsigned value to a buffer pointed to by PTR */
+#define PPPOE_ADD_16(PTR, VAL) \
+    *(PTR)++ = (VAL) / 256;    \
+    *(PTR)++ = (VAL) % 256
+
+/* Add a complete PPPoE header to the buffer pointed to by PTR */
+#define PPPOE_ADD_HEADER(PTR, CODE, SESS, LEN)  \
+    *(PTR)++ = PPPOE_VERTYPE;  \
+    *(PTR)++ = (CODE);         \
+    PPPOE_ADD_16(PTR, SESS);   \
+    PPPOE_ADD_16(PTR, LEN)
+
+#define PPPOE_DISC_TIMEOUT (5*1000)  /* base for quick timeout calculation */
+#define PPPOE_SLOW_RETRY   (60*1000) /* persistent retry interval */
+#define PPPOE_DISC_MAXPADI  4        /* retry PADI four times (quickly) */
+#define PPPOE_DISC_MAXPADR  2        /* retry PADR twice */
+
+#ifdef PPPOE_SERVER
+/* from if_spppsubr.c */
+#define IFF_PASSIVE IFF_LINK0 /* wait passively for connection */
+#endif
+
+struct pppoe_softc {
+  LIST_ENTRY(pppoe_softc) sc_list;
+  struct netif *sc_ethif;      /* ethernet interface we are using */
+  int sc_pd;                   /* ppp unit number */
+  void (*sc_linkStatusCB)(int pd, int up);
+
+  int sc_state;                /* discovery phase or session connected */
+  struct eth_addr sc_dest;     /* hardware address of concentrator */
+  u16_t sc_session;            /* PPPoE session id */
+
+  char *sc_service_name;       /* if != NULL: requested name of service */
+  char *sc_concentrator_name;  /* if != NULL: requested concentrator id */
+  u8_t *sc_ac_cookie;          /* content of AC cookie we must echo back */
+  size_t sc_ac_cookie_len;     /* length of cookie data */
+#ifdef PPPOE_SERVER
+  u8_t *sc_hunique;            /* content of host unique we must echo back */
+  size_t sc_hunique_len;       /* length of host unique */
+#endif
+  int sc_padi_retried;         /* number of PADI retries already done */
+  int sc_padr_retried;         /* number of PADR retries already done */
+};
+
+/* input routines */
+static void pppoe_dispatch_disc_pkt(struct netif *, struct pbuf *);
+
+/* management routines */
+static int pppoe_do_disconnect(struct pppoe_softc *);
+static void pppoe_abort_connect(struct pppoe_softc *);
+static void pppoe_clear_softc(struct pppoe_softc *, const char *);
+
+/* internal timeout handling */
+static void pppoe_timeout(void *);
+
+/* sending actual protocol controll packets */
+static err_t pppoe_send_padi(struct pppoe_softc *);
+static err_t pppoe_send_padr(struct pppoe_softc *);
+#ifdef PPPOE_SERVER
+static err_t pppoe_send_pado(struct pppoe_softc *);
+static err_t pppoe_send_pads(struct pppoe_softc *);
+#endif
+static err_t pppoe_send_padt(struct netif *, u_int, const u8_t *);
+
+/* internal helper functions */
+static struct pppoe_softc * pppoe_find_softc_by_session(u_int, struct netif *);
+static struct pppoe_softc * pppoe_find_softc_by_hunique(u8_t *, size_t, struct netif *);
+
+static LIST_HEAD(pppoe_softc_head, pppoe_softc) pppoe_softc_list;
+
+int pppoe_hdrlen;
+
+void
+pppoe_init(void)
+{
+  pppoe_hdrlen = sizeof(struct eth_hdr) + PPPOE_HEADERLEN;
+  LIST_INIT(&pppoe_softc_list);
+}
+
+err_t
+pppoe_create(struct netif *ethif, int pd, void (*linkStatusCB)(int pd, int up), struct pppoe_softc **scptr)
+{
+  struct pppoe_softc *sc;
+
+  sc = mem_malloc(sizeof(struct pppoe_softc));
+  if(!sc) {
+    *scptr = NULL;
+    return ERR_MEM;
+  }
+  memset(sc, 0, sizeof(struct pppoe_softc));
+
+  /* changed to real address later */
+  MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest));
+
+  sc->sc_pd = pd;
+  sc->sc_linkStatusCB = linkStatusCB;
+  sc->sc_ethif = ethif;
+
+  LIST_INSERT_HEAD(&pppoe_softc_list, sc, sc_list);
+
+  *scptr = sc;
+
+  return ERR_OK;
+}
+
+err_t
+pppoe_destroy(struct netif *ifp)
+{
+  struct pppoe_softc * sc;
+
+  LIST_FOREACH(sc, &pppoe_softc_list, sc_list) {
+    if (sc->sc_ethif == ifp) {
+      break;
+    }
+  }
+
+  if(!(sc && (sc->sc_ethif == ifp))) {
+    return ERR_IF;
+  }
+
+  tcpip_untimeout(pppoe_timeout, sc);
+  LIST_REMOVE(sc, sc_list);
+
+  if (sc->sc_concentrator_name) {
+    mem_free(sc->sc_concentrator_name);
+  }
+  if (sc->sc_service_name) {
+    mem_free(sc->sc_service_name);
+  }
+  if (sc->sc_ac_cookie) {
+    mem_free(sc->sc_ac_cookie);
+  }
+  mem_free(sc);
+
+  return ERR_OK;
+}
+
+/*
+ * Find the interface handling the specified session.
+ * Note: O(number of sessions open), this is a client-side only, mean
+ * and lean implementation, so number of open sessions typically should
+ * be 1.
+ */
+static struct pppoe_softc *
+pppoe_find_softc_by_session(u_int session, struct netif *rcvif)
+{
+  struct pppoe_softc *sc;
+
+  if (session == 0) {
+    return NULL;
+  }
+
+  LIST_FOREACH(sc, &pppoe_softc_list, sc_list) {
+    if (sc->sc_state == PPPOE_STATE_SESSION
+        && sc->sc_session == session) {
+      if (sc->sc_ethif == rcvif) {
+        return sc;
+      } else {
+        return NULL;
+      }
+    }
+  }
+  return NULL;
+}
+
+/* Check host unique token passed and return appropriate softc pointer,
+ * or NULL if token is bogus. */
+static struct pppoe_softc *
+pppoe_find_softc_by_hunique(u8_t *token, size_t len, struct netif *rcvif)
+{
+  struct pppoe_softc *sc, *t;
+
+  if (LIST_EMPTY(&pppoe_softc_list)) {
+    return NULL;
+  }
+
+  if (len != sizeof sc) {
+    return NULL;
+  }
+  MEMCPY(&t, token, len);
+
+  LIST_FOREACH(sc, &pppoe_softc_list, sc_list) {
+    if (sc == t) {
+      break;
+    }
+  }
+
+  if (sc == NULL) {
+    PPPDEBUG((LOG_DEBUG, "pppoe: alien host unique tag, no session found\n"));
+    return NULL;
+  }
+
+  /* should be safe to access *sc now */
+  if (sc->sc_state < PPPOE_STATE_PADI_SENT || sc->sc_state >= PPPOE_STATE_SESSION) {
+    printf("%c%c%"U16_F": host unique tag found, but it belongs to a connection in state %d\n",
+      sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, sc->sc_state);
+    return NULL;
+  }
+  if (sc->sc_ethif != rcvif) {
+    printf("%c%c%"U16_F": wrong interface, not accepting host unique\n",
+      sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num);
+    return NULL;
+  }
+  return sc;
+}
+
+static void
+pppoe_linkstatus_up(void *arg)
+{
+  struct pppoe_softc *sc = (struct pppoe_softc*)arg;
+
+  sc->sc_linkStatusCB(sc->sc_pd, 1);
+}
+
+/* analyze and handle a single received packet while not in session state */
+static void
+pppoe_dispatch_disc_pkt(struct netif *netif, struct pbuf *pb)
+{
+  u16_t tag, len;
+  u16_t session, plen;
+  struct pppoe_softc *sc;
+  const char *err_msg;
+  char devname[6];
+  char *error;
+  u8_t *ac_cookie;
+  size_t ac_cookie_len;
+#ifdef PPPOE_SERVER
+  u8_t *hunique;
+  size_t hunique_len;
+#endif
+  struct pppoehdr *ph;
+  struct pppoetag pt;
+  int off, err, errortag;
+  struct eth_hdr *ethhdr;
+
+  pb = pppSingleBuf(pb);
+
+  strcpy(devname, "pppoe");  /* as long as we don't know which instance */
+  err_msg = NULL;
+  errortag = 0;
+  if (pb->len < sizeof(*ethhdr)) {
+    goto done;
+  }
+  ethhdr = (struct eth_hdr *)pb->payload;
+  off = sizeof(*ethhdr);
+
+  ac_cookie = NULL;
+  ac_cookie_len = 0;
+#ifdef PPPOE_SERVER
+  hunique = NULL;
+  hunique_len = 0;
+#endif
+  session = 0;
+  if (pb->len - off < PPPOE_HEADERLEN) {
+    printf("pppoe: packet too short: %d\n", pb->len);
+    goto done;
+  }
+
+  ph = (struct pppoehdr *) (ethhdr + 1);
+  if (ph->vertype != PPPOE_VERTYPE) {
+    printf("pppoe: unknown version/type packet: 0x%x\n", ph->vertype);
+    goto done;
+  }
+  session = ntohs(ph->session);
+  plen = ntohs(ph->plen);
+  off += sizeof(*ph);
+
+  if (plen + off > pb->len) {
+    printf("pppoe: packet content does not fit: data available = %d, packet size = %u\n",
+        pb->len - off, plen);
+    goto done;
+  }
+  if(pb->tot_len == pb->len) {
+    pb->tot_len = pb->len = off + plen; /* ignore trailing garbage */
+  }
+  tag = 0;
+  len = 0;
+  sc = NULL;
+  while (off + sizeof(pt) <= pb->len) {
+    MEMCPY(&pt, (u8_t*)pb->payload + off, sizeof(pt));
+    tag = ntohs(pt.tag);
+    len = ntohs(pt.len);
+    if (off + sizeof(pt) + len > pb->len) {
+      printf("pppoe: tag 0x%x len 0x%x is too long\n", tag, len);
+      goto done;
+    }
+    switch (tag) {
+      case PPPOE_TAG_EOL:
+        goto breakbreak;
+      case PPPOE_TAG_SNAME:
+        break;  /* ignored */
+      case PPPOE_TAG_ACNAME:
+        break;  /* ignored */
+      case PPPOE_TAG_HUNIQUE:
+        if (sc != NULL) {
+          break;
+        }
+#ifdef PPPOE_SERVER
+        hunique = (u8_t*)pb->payload + off + sizeof(pt);
+        hunique_len = len;
+#endif
+        sc = pppoe_find_softc_by_hunique((u8_t*)pb->payload + off + sizeof(pt), len, netif);
+        if (sc != NULL) {
+          snprintf(devname, sizeof(devname), "%c%c%"U16_F, sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num);
+        }
+        break;
+      case PPPOE_TAG_ACCOOKIE:
+        if (ac_cookie == NULL) {
+          ac_cookie = (u8_t*)pb->payload + off + sizeof(pt);
+          ac_cookie_len = len;
+        }
+        break;
+      case PPPOE_TAG_SNAME_ERR:
+        err_msg = "SERVICE NAME ERROR";
+        errortag = 1;
+        break;
+      case PPPOE_TAG_ACSYS_ERR:
+        err_msg = "AC SYSTEM ERROR";
+        errortag = 1;
+        break;
+      case PPPOE_TAG_GENERIC_ERR:
+        err_msg = "GENERIC ERROR";
+        errortag = 1;
+        break;
+    }
+    if (err_msg) {
+      error = NULL;
+      if (errortag && len) {
+        error = mem_malloc(len+1);
+        if (error) {
+          strncpy(error, (char*)pb->payload + off + sizeof(pt), len);
+          error[len-1] = '\0';
+        }
+      }
+      if (error) {
+        printf("%s: %s: %s\n", devname, err_msg, error);
+        mem_free(error);
+      } else {
+        printf("%s: %s\n", devname, err_msg);
+      }
+      if (errortag) {
+        goto done;
+      }
+    }
+    off += sizeof(pt) + len;
+  }
+
+breakbreak:;
+  switch (ph->code) {
+    case PPPOE_CODE_PADI:
+#ifdef PPPOE_SERVER
+      /*
+       * got service name, concentrator name, and/or host unique.
+       * ignore if we have no interfaces with IFF_PASSIVE|IFF_UP.
+       */
+      if (LIST_EMPTY(&pppoe_softc_list)) {
+        goto done;
+      }
+      LIST_FOREACH(sc, &pppoe_softc_list, sc_list) {
+        if (!(sc->sc_sppp.pp_if.if_flags & IFF_UP)) {
+          continue;
+        }
+        if (!(sc->sc_sppp.pp_if.if_flags & IFF_PASSIVE)) {
+          continue;
+        }
+        if (sc->sc_state == PPPOE_STATE_INITIAL) {
+          break;
+        }
+      }
+      if (sc == NULL) {
+        /* printf("pppoe: free passive interface is not found\n"); */
+        goto done;
+      }
+      if (hunique) {
+        if (sc->sc_hunique) {
+          mem_free(sc->sc_hunique);
+        }
+        sc->sc_hunique = mem_malloc(hunique_len);
+        if (sc->sc_hunique == NULL) {
+          goto done;
+        }
+        sc->sc_hunique_len = hunique_len;
+        MEMCPY(sc->sc_hunique, hunique, hunique_len);
+      }
+      MEMCPY(&sc->sc_dest, eh->ether_shost, sizeof sc->sc_dest);
+      sc->sc_state = PPPOE_STATE_PADO_SENT;
+      pppoe_send_pado(sc);
+      break;
+  #endif /* PPPOE_SERVER */
+    case PPPOE_CODE_PADR:
+  #ifdef PPPOE_SERVER
+      /*
+       * get sc from ac_cookie if IFF_PASSIVE
+       */
+      if (ac_cookie == NULL) {
+        /* be quiet if there is not a single pppoe instance */
+        printf("pppoe: received PADR but not includes ac_cookie\n");
+        goto done;
+      }
+      sc = pppoe_find_softc_by_hunique(ac_cookie, ac_cookie_len, netif);
+      if (sc == NULL) {
+        /* be quiet if there is not a single pppoe instance */
+        if (!LIST_EMPTY(&pppoe_softc_list)) {
+          printf("pppoe: received PADR but could not find request for it\n");
+        }
+        goto done;
+      }
+      if (sc->sc_state != PPPOE_STATE_PADO_SENT) {
+        printf("%c%c%"U16_F": received unexpected PADR\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num);
+        goto done;
+      }
+      if (hunique) {
+        if (sc->sc_hunique) {
+          mem_free(sc->sc_hunique);
+        }
+        sc->sc_hunique = mem_malloc(hunique_len);
+        if (sc->sc_hunique == NULL) {
+          goto done;
+        }
+        sc->sc_hunique_len = hunique_len;
+        MEMCPY(sc->sc_hunique, hunique, hunique_len);
+      }
+      pppoe_send_pads(sc);
+      sc->sc_state = PPPOE_STATE_SESSION;
+      tcpip_timeout (100, pppoe_linkstatus_up, sc); /* notify upper layers */
+      break;
+  #else
+      /* ignore, we are no access concentrator */
+      goto done;
+  #endif /* PPPOE_SERVER */
+    case PPPOE_CODE_PADO:
+      if (sc == NULL) {
+        /* be quiet if there is not a single pppoe instance */
+        if (!LIST_EMPTY(&pppoe_softc_list)) {
+          printf("pppoe: received PADO but could not find request for it\n");
+        }
+        goto done;
+      }
+      if (sc->sc_state != PPPOE_STATE_PADI_SENT) {
+        printf("%c%c%"U16_F": received unexpected PADO\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num);
+        goto done;
+      }
+      if (ac_cookie) {
+        if (sc->sc_ac_cookie) {
+          mem_free(sc->sc_ac_cookie);
+        }
+        sc->sc_ac_cookie = mem_malloc(ac_cookie_len);
+        if (sc->sc_ac_cookie == NULL) {
+          goto done;
+        }
+        sc->sc_ac_cookie_len = ac_cookie_len;
+        MEMCPY(sc->sc_ac_cookie, ac_cookie, ac_cookie_len);
+      }
+      MEMCPY(&sc->sc_dest, ethhdr->src.addr, sizeof(sc->sc_dest.addr));
+      tcpip_untimeout(pppoe_timeout, sc);
+      sc->sc_padr_retried = 0;
+      sc->sc_state = PPPOE_STATE_PADR_SENT;
+      if ((err = pppoe_send_padr(sc)) != 0) {
+        PPPDEBUG((LOG_DEBUG, "pppoe: %c%c%"U16_F": failed to send PADR, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err));
+      }
+      tcpip_timeout(PPPOE_DISC_TIMEOUT * (1 + sc->sc_padr_retried), pppoe_timeout, sc);
+      break;
+    case PPPOE_CODE_PADS:
+      if (sc == NULL) {
+        goto done;
+      }
+      sc->sc_session = session;
+      tcpip_untimeout(pppoe_timeout, sc);
+      PPPDEBUG((LOG_DEBUG, "pppoe: %c%c%"U16_F": session 0x%x connected\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, session));
+      sc->sc_state = PPPOE_STATE_SESSION;
+      tcpip_timeout (100, pppoe_linkstatus_up, sc); /* notify upper layers */
+      break;
+    case PPPOE_CODE_PADT:
+      if (sc == NULL) {
+        goto done;
+      }
+      pppoe_clear_softc(sc, "received PADT");
+      break;
+    default:
+      if(sc) {
+        printf("%c%c%"U16_F": unknown code (0x%04x) session = 0x%04x\n",
+            sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num,
+            ph->code, session);
+      } else {
+        printf("pppoe: unknown code (0x%04x) session = 0x%04x\n", ph->code, session);
+      }
+      break;
+  }
+
+done:
+  pbuf_free(pb);
+  return;
+}
+
+void
+pppoe_disc_input(struct netif *netif, struct pbuf *p)
+{
+  /* avoid error messages if there is not a single pppoe instance */
+  if (!LIST_EMPTY(&pppoe_softc_list)) {
+    pppoe_dispatch_disc_pkt(netif, p);
+  } else {
+    pbuf_free(p);
+  }
+}
+
+void
+pppoe_data_input(struct netif *netif, struct pbuf *pb)
+{
+  u16_t session, plen;
+  struct pppoe_softc *sc;
+  struct pppoehdr *ph;
+#ifdef PPPOE_TERM_UNKNOWN_SESSIONS
+  u8_t shost[ETHER_ADDR_LEN];
+#endif
+
+#ifdef PPPOE_TERM_UNKNOWN_SESSIONS
+  MEMCPY(shost, ((struct eth_hdr *)pb->payload)->src.addr, sizeof(shost));
+#endif
+  if (pbuf_header(pb, -(int)sizeof(struct eth_hdr)) != 0) {
+    /* bail out */
+    PPPDEBUG((LOG_ERR, "pppoe_data_input: pbuf_header failed\n"));
+    LINK_STATS_INC(link.lenerr);
+    goto drop;
+  } 
+
+  pb = pppSingleBuf (pb);
+
+  if (pb->len <= PPPOE_HEADERLEN) {
+    printf("pppoe (data): dropping too short packet: %d bytes\n", pb->len);
+    goto drop;
+  }
+
+  if (pb->len < sizeof(*ph)) {
+    printf("pppoe_data_input: could not get PPPoE header\n");
+    goto drop;
+  }
+  ph = (struct pppoehdr *)pb->payload;
+
+  if (ph->vertype != PPPOE_VERTYPE) {
+    printf("pppoe (data): unknown version/type packet: 0x%x\n", ph->vertype);
+    goto drop;
+  }
+  if (ph->code != 0) {
+    goto drop;
+  }
+
+  session = ntohs(ph->session);
+  sc = pppoe_find_softc_by_session(session, netif);
+  if (sc == NULL) {
+#ifdef PPPOE_TERM_UNKNOWN_SESSIONS
+    printf("pppoe: input for unknown session 0x%x, sending PADT\n", session);
+    pppoe_send_padt(netif, session, shost);
+#endif
+    goto drop;
+  }
+
+  plen = ntohs(ph->plen);
+
+  if (pbuf_header(pb, -(int)(PPPOE_HEADERLEN)) != 0) {
+    /* bail out */
+    PPPDEBUG((LOG_ERR, "pppoe_data_input: pbuf_header PPPOE_HEADERLEN failed\n"));
+    LINK_STATS_INC(link.lenerr);
+    goto drop;
+  } 
+
+  PPPDEBUG((LOG_DEBUG, "pppoe_data_input: %c%c%"U16_F": pkthdr.len=%d, pppoe.len=%d\n",
+        sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num,
+        pb->len, plen));
+
+  if (pb->len < plen) {
+    goto drop;
+  }
+
+  pppInProcOverEthernet(sc->sc_pd, pb);
+
+  return;
+
+drop:
+  pbuf_free(pb);
+}
+
+static err_t
+pppoe_output(struct pppoe_softc *sc, struct pbuf *pb)
+{
+  struct eth_hdr *ethhdr;
+  u16_t etype;
+  err_t res;
+
+  if (!sc->sc_ethif) {
+    pbuf_free(pb);
+    return ERR_IF;
+  }
+
+  ethhdr = (struct eth_hdr *)pb->payload;
+  etype = sc->sc_state == PPPOE_STATE_SESSION ? ETHTYPE_PPPOE : ETHTYPE_PPPOEDISC;
+  ethhdr->type = htons(etype);
+  MEMCPY(ethhdr->dest.addr, sc->sc_dest.addr, sizeof(ethhdr->dest.addr));
+  MEMCPY(ethhdr->src.addr, ((struct eth_addr *)sc->sc_ethif->hwaddr)->addr, sizeof(ethhdr->src.addr));
+
+  PPPDEBUG((LOG_DEBUG, "pppoe: %c%c%"U16_F" (%x) state=%d, session=0x%x output -> %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F", len=%d\n",
+      sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, etype,
+      sc->sc_state, sc->sc_session,
+      sc->sc_dest.addr[0], sc->sc_dest.addr[1], sc->sc_dest.addr[2], sc->sc_dest.addr[3], sc->sc_dest.addr[4], sc->sc_dest.addr[5],
+      pb->tot_len));
+
+  res = sc->sc_ethif->linkoutput(sc->sc_ethif, pb);
+
+  pbuf_free(pb);
+
+  return res;
+}
+
+static err_t
+pppoe_send_padi(struct pppoe_softc *sc)
+{
+  struct pbuf *pb;
+  u8_t *p;
+  int len, l1 = 0, l2 = 0; /* XXX: gcc */
+
+  if (sc->sc_state >PPPOE_STATE_PADI_SENT) {
+    PPPDEBUG((LOG_ERR, "ERROR: pppoe_send_padi in state %d", sc->sc_state));
+  }
+
+  /* calculate length of frame (excluding ethernet header + pppoe header) */
+  len = 2 + 2 + 2 + 2 + sizeof sc;  /* service name tag is required, host unique is send too */
+  if (sc->sc_service_name != NULL) {
+    l1 = strlen(sc->sc_service_name);
+    len += l1;
+  }
+  if (sc->sc_concentrator_name != NULL) {
+    l2 = strlen(sc->sc_concentrator_name);
+    len += 2 + 2 + l2;
+  }
+
+  /* allocate a buffer */
+  pb = pbuf_alloc(PBUF_LINK, sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len, PBUF_RAM);
+  if (!pb) {
+    return ERR_MEM;
+  }
+
+  p = (u8_t*)pb->payload + sizeof (struct eth_hdr);
+  /* fill in pkt */
+  PPPOE_ADD_HEADER(p, PPPOE_CODE_PADI, 0, len);
+  PPPOE_ADD_16(p, PPPOE_TAG_SNAME);
+  if (sc->sc_service_name != NULL) {
+    PPPOE_ADD_16(p, l1);
+    MEMCPY(p, sc->sc_service_name, l1);
+    p += l1;
+  } else {
+    PPPOE_ADD_16(p, 0);
+  }
+  if (sc->sc_concentrator_name != NULL) {
+    PPPOE_ADD_16(p, PPPOE_TAG_ACNAME);
+    PPPOE_ADD_16(p, l2);
+    MEMCPY(p, sc->sc_concentrator_name, l2);
+    p += l2;
+  }
+  PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE);
+  PPPOE_ADD_16(p, sizeof(sc));
+  MEMCPY(p, &sc, sizeof sc);
+
+  /* send pkt */
+  return pppoe_output(sc, pb);
+}
+
+static void
+pppoe_timeout(void *arg)
+{
+  int retry_wait, err;
+  struct pppoe_softc *sc = (struct pppoe_softc*)arg;
+
+  PPPDEBUG((LOG_DEBUG, "pppoe: %c%c%"U16_F": timeout\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num));
+
+  switch (sc->sc_state) {
+    case PPPOE_STATE_PADI_SENT:
+      /*
+       * We have two basic ways of retrying:
+       *  - Quick retry mode: try a few times in short sequence
+       *  - Slow retry mode: we already had a connection successfully
+       *    established and will try infinitely (without user
+       *    intervention)
+       * We only enter slow retry mode if IFF_LINK1 (aka autodial)
+       * is not set.
+       */
+
+      /* initialize for quick retry mode */
+      retry_wait = PPPOE_DISC_TIMEOUT * (1 + sc->sc_padi_retried);
+
+      sc->sc_padi_retried++;
+      if (sc->sc_padi_retried >= PPPOE_DISC_MAXPADI) {
+#if 0
+        if ((sc->sc_sppp.pp_if.if_flags & IFF_LINK1) == 0) {
+          /* slow retry mode */
+          retry_wait = PPPOE_SLOW_RETRY;
+        } else
+#endif
+        {
+          pppoe_abort_connect(sc);
+          return;
+        }
+      }
+      if ((err = pppoe_send_padi(sc)) != 0) {
+        sc->sc_padi_retried--;
+        PPPDEBUG((LOG_DEBUG, "pppoe: %c%c%"U16_F": failed to transmit PADI, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err));
+      }
+      tcpip_timeout(retry_wait, pppoe_timeout, sc);
+      break;
+
+    case PPPOE_STATE_PADR_SENT:
+      sc->sc_padr_retried++;
+      if (sc->sc_padr_retried >= PPPOE_DISC_MAXPADR) {
+        MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest));
+        sc->sc_state = PPPOE_STATE_PADI_SENT;
+        sc->sc_padr_retried = 0;
+        if ((err = pppoe_send_padi(sc)) != 0) {
+          PPPDEBUG((LOG_DEBUG, "pppoe: %c%c%"U16_F": failed to send PADI, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err));
+        }
+        tcpip_timeout(PPPOE_DISC_TIMEOUT * (1 + sc->sc_padi_retried), pppoe_timeout, sc);
+        return;
+      }
+      if ((err = pppoe_send_padr(sc)) != 0) {
+        sc->sc_padr_retried--;
+        PPPDEBUG((LOG_DEBUG, "pppoe: %c%c%"U16_F": failed to send PADR, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err));
+      }
+      tcpip_timeout(PPPOE_DISC_TIMEOUT * (1 + sc->sc_padr_retried), pppoe_timeout, sc);
+      break;
+    case PPPOE_STATE_CLOSING:
+      pppoe_do_disconnect(sc);
+      break;
+    default:
+      return;  /* all done, work in peace */
+  }
+}
+
+/* Start a connection (i.e. initiate discovery phase) */
+int
+pppoe_connect(struct pppoe_softc *sc)
+{
+  int err;
+
+  if (sc->sc_state != PPPOE_STATE_INITIAL) {
+    return EBUSY;
+  }
+
+#ifdef PPPOE_SERVER
+  /* wait PADI if IFF_PASSIVE */
+  if ((sc->sc_sppp.pp_if.if_flags & IFF_PASSIVE)) {
+    return 0;
+  }
+#endif
+  /* save state, in case we fail to send PADI */
+  sc->sc_state = PPPOE_STATE_PADI_SENT;
+  sc->sc_padr_retried = 0;
+  err = pppoe_send_padi(sc);
+  PPPDEBUG((LOG_DEBUG, "pppoe: %c%c%"U16_F": failed to send PADI, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err));
+  tcpip_timeout(PPPOE_DISC_TIMEOUT, pppoe_timeout, sc);
+  return err;
+}
+
+/* disconnect */
+void
+pppoe_disconnect(struct pppoe_softc *sc)
+{
+  if (sc->sc_state < PPPOE_STATE_SESSION) {
+    return;
+  }
+  /*
+   * Do not call pppoe_disconnect here, the upper layer state
+   * machine gets confused by this. We must return from this
+   * function and defer disconnecting to the timeout handler.
+   */
+  sc->sc_state = PPPOE_STATE_CLOSING;
+  tcpip_timeout(20, pppoe_timeout, sc);
+}
+
+static int
+pppoe_do_disconnect(struct pppoe_softc *sc)
+{
+  int err;
+
+  if (sc->sc_state < PPPOE_STATE_SESSION) {
+    err = EBUSY;
+  } else {
+    PPPDEBUG((LOG_DEBUG, "pppoe: %c%c%"U16_F": disconnecting\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num));
+    err = pppoe_send_padt(sc->sc_ethif, sc->sc_session, (const u8_t *)&sc->sc_dest);
+  }
+
+  /* cleanup softc */
+  sc->sc_state = PPPOE_STATE_INITIAL;
+  MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest));
+  if (sc->sc_ac_cookie) {
+    mem_free(sc->sc_ac_cookie);
+    sc->sc_ac_cookie = NULL;
+  }
+  sc->sc_ac_cookie_len = 0;
+#ifdef PPPOE_SERVER
+  if (sc->sc_hunique) {
+    mem_free(sc->sc_hunique);
+    sc->sc_hunique = NULL;
+  }
+  sc->sc_hunique_len = 0;
+#endif
+  sc->sc_session = 0;
+
+  sc->sc_linkStatusCB(sc->sc_pd, 0); /* notify upper layers */
+
+  return err;
+}
+
+/* Connection attempt aborted */
+static void
+pppoe_abort_connect(struct pppoe_softc *sc)
+{
+  printf("%c%c%"U16_F": could not establish connection\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num);
+  sc->sc_state = PPPOE_STATE_CLOSING;
+
+  sc->sc_linkStatusCB(sc->sc_pd, 0); /* notify upper layers */
+
+  /* clear connection state */
+  MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest));
+  sc->sc_state = PPPOE_STATE_INITIAL;
+}
+
+/* Send a PADR packet */
+static err_t
+pppoe_send_padr(struct pppoe_softc *sc)
+{
+  struct pbuf *pb;
+  u8_t *p;
+  size_t len, l1 = 0; /* XXX: gcc */
+
+  if (sc->sc_state != PPPOE_STATE_PADR_SENT) {
+    return ERR_CONN;
+  }
+
+  len = 2 + 2 + 2 + 2 + sizeof(sc);    /* service name, host unique */
+  if (sc->sc_service_name != NULL) {    /* service name tag maybe empty */
+    l1 = strlen(sc->sc_service_name);
+    len += l1;
+  }
+  if (sc->sc_ac_cookie_len > 0) {
+    len += 2 + 2 + sc->sc_ac_cookie_len;  /* AC cookie */
+  }
+  pb = pbuf_alloc(PBUF_LINK, sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len, PBUF_RAM);
+  if (!pb) {
+    return ERR_MEM;
+  }
+  p = (u8_t*)pb->payload + sizeof (struct eth_hdr);
+  PPPOE_ADD_HEADER(p, PPPOE_CODE_PADR, 0, len);
+  PPPOE_ADD_16(p, PPPOE_TAG_SNAME);
+  if (sc->sc_service_name != NULL) {
+    PPPOE_ADD_16(p, l1);
+    MEMCPY(p, sc->sc_service_name, l1);
+    p += l1;
+  } else {
+    PPPOE_ADD_16(p, 0);
+  }
+  if (sc->sc_ac_cookie_len > 0) {
+    PPPOE_ADD_16(p, PPPOE_TAG_ACCOOKIE);
+    PPPOE_ADD_16(p, sc->sc_ac_cookie_len);
+    MEMCPY(p, sc->sc_ac_cookie, sc->sc_ac_cookie_len);
+    p += sc->sc_ac_cookie_len;
+  }
+  PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE);
+  PPPOE_ADD_16(p, sizeof(sc));
+  MEMCPY(p, &sc, sizeof sc);
+
+  return pppoe_output(sc, pb);
+}
+
+/* send a PADT packet */
+static err_t
+pppoe_send_padt(struct netif *outgoing_if, u_int session, const u8_t *dest)
+{
+  struct pbuf *pb;
+  struct eth_hdr *ethhdr;
+  err_t res;
+  u8_t *p;
+
+  pb = pbuf_alloc(PBUF_LINK, sizeof(struct eth_hdr) + PPPOE_HEADERLEN, PBUF_RAM);
+  if (!pb) {
+    return ERR_MEM;
+  }
+
+  ethhdr = (struct eth_hdr *)pb->payload;
+  ethhdr->type = htons(ETHTYPE_PPPOEDISC);
+  MEMCPY(ethhdr->dest.addr, dest, sizeof(ethhdr->dest.addr));
+  MEMCPY(ethhdr->src.addr, ((struct eth_addr *)outgoing_if->hwaddr)->addr, sizeof(ethhdr->src.addr));
+
+  p = (u8_t*)(ethhdr + 1);
+  PPPOE_ADD_HEADER(p, PPPOE_CODE_PADT, session, 0);
+
+  res = outgoing_if->linkoutput(outgoing_if, pb);
+
+  pbuf_free(pb);
+
+  return res;
+}
+
+#ifdef PPPOE_SERVER
+static err_t
+pppoe_send_pado(struct pppoe_softc *sc)
+{
+  struct pbuf *pb;
+  u8_t *p;
+  size_t len;
+
+  if (sc->sc_state != PPPOE_STATE_PADO_SENT) {
+    return ERR_CONN;
+  }
+
+  /* calc length */
+  len = 0;
+  /* include ac_cookie */
+  len += 2 + 2 + sizeof(sc);
+  /* include hunique */
+  len += 2 + 2 + sc->sc_hunique_len;
+  pb = pbuf_alloc(PBUF_LINK, sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len, PBUF_RAM);
+  if (!pb) {
+    return ERR_MEM;
+  }
+  p = (u8_t*)pb->payload + sizeof (struct eth_hdr);
+  PPPOE_ADD_HEADER(p, PPPOE_CODE_PADO, 0, len);
+  PPPOE_ADD_16(p, PPPOE_TAG_ACCOOKIE);
+  PPPOE_ADD_16(p, sizeof(sc));
+  MEMCPY(p, &sc, sizeof(sc));
+  p += sizeof(sc);
+  PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE);
+  PPPOE_ADD_16(p, sc->sc_hunique_len);
+  MEMCPY(p, sc->sc_hunique, sc->sc_hunique_len);
+  return pppoe_output(sc, pb);
+}
+
+static err_t
+pppoe_send_pads(struct pppoe_softc *sc)
+{
+  struct pbuf *pb;
+  u8_t *p;
+  size_t len, l1 = 0;  /* XXX: gcc */
+
+  if (sc->sc_state != PPPOE_STATE_PADO_SENT) {
+    return ERR_CONN;
+  }
+
+  sc->sc_session = mono_time.tv_sec % 0xff + 1;
+  /* calc length */
+  len = 0;
+  /* include hunique */
+  len += 2 + 2 + 2 + 2 + sc->sc_hunique_len;  /* service name, host unique*/
+  if (sc->sc_service_name != NULL) {    /* service name tag maybe empty */
+    l1 = strlen(sc->sc_service_name);
+    len += l1;
+  }
+  pb = pbuf_alloc(PBUF_LINK, sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len, PBUF_RAM);
+  if (!pb) {
+    return ERR_MEM;
+  }
+  p = (u8_t*)pb->payload + sizeof (struct eth_hdr);
+  PPPOE_ADD_HEADER(p, PPPOE_CODE_PADS, sc->sc_session, len);
+  PPPOE_ADD_16(p, PPPOE_TAG_SNAME);
+  if (sc->sc_service_name != NULL) {
+    PPPOE_ADD_16(p, l1);
+    MEMCPY(p, sc->sc_service_name, l1);
+    p += l1;
+  } else {
+    PPPOE_ADD_16(p, 0);
+  }
+  PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE);
+  PPPOE_ADD_16(p, sc->sc_hunique_len);
+  MEMCPY(p, sc->sc_hunique, sc->sc_hunique_len);
+  return pppoe_output(sc, pb);
+}
+#endif
+
+err_t
+pppoe_xmit(struct pppoe_softc *sc, struct pbuf *pb)
+{
+  u8_t *p;
+  size_t len;
+
+  /* are we ready to process data yet? */
+  if (sc->sc_state < PPPOE_STATE_SESSION) {
+    /*sppp_flush(&sc->sc_sppp.pp_if);*/
+    pbuf_free(pb);
+    return ERR_CONN;
+  }
+
+  len = pb->tot_len;
+
+  /* make room for Ethernet header - should not fail */
+  if (pbuf_header(pb, sizeof(struct eth_hdr) + PPPOE_HEADERLEN) != 0) {
+    /* bail out */
+    PPPDEBUG((LOG_ERR, "pppoe: %c%c%"U16_F": pppoe_xmit: could not allocate room for header\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num));
+    LINK_STATS_INC(link.lenerr);
+    pbuf_free(pb);
+    return ERR_BUF;
+  } 
+
+  p = (u8_t*)pb->payload + sizeof(struct eth_hdr);
+  PPPOE_ADD_HEADER(p, 0, sc->sc_session, len);
+
+  return pppoe_output(sc, pb);
+}
+
+#if 0 /*def PFIL_HOOKS*/
+static int
+pppoe_ifattach_hook(void *arg, struct pbuf **mp, struct netif *ifp, int dir)
+{
+  struct pppoe_softc *sc;
+  int s;
+
+  if (mp != (struct pbuf **)PFIL_IFNET_DETACH) {
+    return 0;
+  }
+
+  LIST_FOREACH(sc, &pppoe_softc_list, sc_list) {
+    if (sc->sc_ethif != ifp) {
+      continue;
+    }
+    if (sc->sc_sppp.pp_if.if_flags & IFF_UP) {
+      sc->sc_sppp.pp_if.if_flags &= ~(IFF_UP|IFF_RUNNING);
+      printf("%c%c%"U16_F": ethernet interface detached, going down\n",
+          sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num);
+    }
+    sc->sc_ethif = NULL;
+    pppoe_clear_softc(sc, "ethernet interface detached");
+  }
+
+  return 0;
+}
+#endif
+
+static void
+pppoe_clear_softc(struct pppoe_softc *sc, const char *message)
+{
+  LWIP_UNUSED_ARG(message);
+
+  /* stop timer */
+  tcpip_untimeout(pppoe_timeout, sc);
+  PPPDEBUG((LOG_DEBUG, "pppoe: %c%c%"U16_F": session 0x%x terminated, %s\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, sc->sc_session, message));
+
+  /* fix our state */
+  sc->sc_state = PPPOE_STATE_INITIAL;
+
+  /* notify upper layers */
+  sc->sc_linkStatusCB(sc->sc_pd, 0);
+
+  /* clean up softc */
+  MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest));
+  if (sc->sc_ac_cookie) {
+    mem_free(sc->sc_ac_cookie);
+    sc->sc_ac_cookie = NULL;
+  }
+  sc->sc_ac_cookie_len = 0;
+  sc->sc_session = 0;
+}
+
+#endif /* PPPOE_SUPPORT */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/pppdebug.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/pppdebug.h
new file mode 100644
index 0000000..6253863
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/pppdebug.h
@@ -0,0 +1,86 @@
+/*****************************************************************************
+* pppdebug.h - System debugging utilities.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+* portions Copyright (c) 2001 by Cognizant Pty Ltd.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY (please don't use tabs!)
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-07-29 Guy Lancaster , Global Election Systems Inc.
+*   Original.
+*
+*****************************************************************************
+*/
+#ifndef PPPDEBUG_H
+#define PPPDEBUG_H
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+/* Trace levels. */
+typedef enum {
+LOG_CRITICAL = 0,
+LOG_ERR      = 1,
+LOG_NOTICE   = 2,
+LOG_WARNING  = 3,
+LOG_INFO     = 5,
+LOG_DETAIL   = 6,
+LOG_DEBUG    = 7
+} LogCodes;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+/*
+ * ppp_trace - a form of printf to send tracing information to stderr
+ */
+void ppp_trace(int level, const char *format,...);
+
+#define TRACELCP PPP_DEBUG
+
+#if PPP_DEBUG
+
+#define AUTHDEBUG(a) ppp_trace a
+#define IPCPDEBUG(a) ppp_trace a
+#define UPAPDEBUG(a) ppp_trace a
+#define LCPDEBUG(a)  ppp_trace a
+#define FSMDEBUG(a)  ppp_trace a
+#define CHAPDEBUG(a) ppp_trace a
+#define PPPDEBUG(a)  ppp_trace a
+
+#else /* PPP_DEBUG */
+
+#define AUTHDEBUG(a)
+#define IPCPDEBUG(a)
+#define UPAPDEBUG(a)
+#define LCPDEBUG(a)
+#define FSMDEBUG(a)
+#define CHAPDEBUG(a)
+#define PPPDEBUG(a)
+
+#endif /* PPP_DEBUG */
+
+#endif /* PPPDEBUG_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/randm.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/randm.c
new file mode 100644
index 0000000..83c4174
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/randm.c
@@ -0,0 +1,249 @@
+/*****************************************************************************
+* randm.c - Random number generator program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1998 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-06-03 Guy Lancaster , Global Election Systems Inc.
+*   Extracted from avos.
+*****************************************************************************/
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "md5.h"
+#include "randm.h"
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include 
+
+#if MD5_SUPPORT /* this module depends on MD5 */
+#define RANDPOOLSZ 16   /* Bytes stored in the pool of randomness. */
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static char randPool[RANDPOOLSZ];   /* Pool of randomness. */
+static long randCount = 0;      /* Pseudo-random incrementer */
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * Initialize the random number generator.
+ *
+ * Since this is to be called on power up, we don't have much
+ *  system randomess to work with.  Here all we use is the
+ *  real-time clock.  We'll accumulate more randomness as soon
+ *  as things start happening.
+ */
+void
+avRandomInit()
+{
+  avChurnRand(NULL, 0);
+}
+
+/*
+ * Churn the randomness pool on a random event.  Call this early and often
+ *  on random and semi-random system events to build randomness in time for
+ *  usage.  For randomly timed events, pass a null pointer and a zero length
+ *  and this will use the system timer and other sources to add randomness.
+ *  If new random data is available, pass a pointer to that and it will be
+ *  included.
+ *
+ * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427
+ */
+void
+avChurnRand(char *randData, u32_t randLen)
+{
+  MD5_CTX md5;
+
+  /* ppp_trace(LOG_INFO, "churnRand: %u@%P\n", randLen, randData); */
+  MD5Init(&md5);
+  MD5Update(&md5, (u_char *)randPool, sizeof(randPool));
+  if (randData) {
+    MD5Update(&md5, (u_char *)randData, randLen);
+  } else {
+    struct {
+      /* INCLUDE fields for any system sources of randomness */
+      char foobar;
+    } sysData;
+
+    /* Load sysData fields here. */
+    MD5Update(&md5, (u_char *)&sysData, sizeof(sysData));
+  }
+  MD5Final((u_char *)randPool, &md5);
+/*  ppp_trace(LOG_INFO, "churnRand: -> 0\n"); */
+}
+
+/*
+ * Use the random pool to generate random data.  This degrades to pseudo
+ *  random when used faster than randomness is supplied using churnRand().
+ * Note: It's important that there be sufficient randomness in randPool
+ *  before this is called for otherwise the range of the result may be
+ *  narrow enough to make a search feasible.
+ *
+ * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427
+ *
+ * XXX Why does he not just call churnRand() for each block?  Probably
+ *  so that you don't ever publish the seed which could possibly help
+ *  predict future values.
+ * XXX Why don't we preserve md5 between blocks and just update it with
+ *  randCount each time?  Probably there is a weakness but I wish that
+ *  it was documented.
+ */
+void
+avGenRand(char *buf, u32_t bufLen)
+{
+  MD5_CTX md5;
+  u_char tmp[16];
+  u32_t n;
+
+  while (bufLen > 0) {
+    n = LWIP_MIN(bufLen, RANDPOOLSZ);
+    MD5Init(&md5);
+    MD5Update(&md5, (u_char *)randPool, sizeof(randPool));
+    MD5Update(&md5, (u_char *)&randCount, sizeof(randCount));
+    MD5Final(tmp, &md5);
+    randCount++;
+    MEMCPY(buf, tmp, n);
+    buf += n;
+    bufLen -= n;
+  }
+}
+
+/*
+ * Return a new random number.
+ */
+u32_t
+avRandom()
+{
+  u32_t newRand;
+
+  avGenRand((char *)&newRand, sizeof(newRand));
+
+  return newRand;
+}
+
+#else /* MD5_SUPPORT */
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static int  avRandomized = 0;       /* Set when truely randomized. */
+static u32_t avRandomSeed = 0;      /* Seed used for random number generation. */
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * Initialize the random number generator.
+ *
+ * Here we attempt to compute a random number seed but even if
+ * it isn't random, we'll randomize it later.
+ *
+ * The current method uses the fields from the real time clock,
+ * the idle process counter, the millisecond counter, and the
+ * hardware timer tick counter.  When this is invoked
+ * in startup(), then the idle counter and timer values may
+ * repeat after each boot and the real time clock may not be
+ * operational.  Thus we call it again on the first random
+ * event.
+ */
+void
+avRandomInit()
+{
+#if 0
+  /* Get a pointer into the last 4 bytes of clockBuf. */
+  u32_t *lptr1 = (u32_t *)((char *)&clockBuf[3]);
+
+  /*
+   * Initialize our seed using the real-time clock, the idle
+   * counter, the millisecond timer, and the hardware timer
+   * tick counter.  The real-time clock and the hardware
+   * tick counter are the best sources of randomness but
+   * since the tick counter is only 16 bit (and truncated
+   * at that), the idle counter and millisecond timer
+   * (which may be small values) are added to help
+   * randomize the lower 16 bits of the seed.
+   */
+  readClk();
+  avRandomSeed += *(u32_t *)clockBuf + *lptr1 + OSIdleCtr
+           + ppp_mtime() + ((u32_t)TM1 << 16) + TM1;
+#else
+  avRandomSeed += sys_jiffies(); /* XXX */
+#endif
+
+  /* Initialize the Borland random number generator. */
+  srand((unsigned)avRandomSeed);
+}
+
+/*
+ * Randomize our random seed value.  Here we use the fact that
+ * this function is called at *truely random* times by the polling
+ * and network functions.  Here we only get 16 bits of new random
+ * value but we use the previous value to randomize the other 16
+ * bits.
+ */
+void
+avRandomize(void)
+{
+  static u32_t last_jiffies;
+
+  if (!avRandomized) {
+    avRandomized = !0;
+    avRandomInit();
+    /* The initialization function also updates the seed. */
+  } else {
+    /* avRandomSeed += (avRandomSeed << 16) + TM1; */
+    avRandomSeed += (sys_jiffies() - last_jiffies); /* XXX */
+  }
+  last_jiffies = sys_jiffies();
+}
+
+/*
+ * Return a new random number.
+ * Here we use the Borland rand() function to supply a pseudo random
+ * number which we make truely random by combining it with our own
+ * seed which is randomized by truely random events. 
+ * Thus the numbers will be truely random unless there have been no
+ * operator or network events in which case it will be pseudo random
+ * seeded by the real time clock.
+ */
+u32_t
+avRandom()
+{
+  return ((((u32_t)rand() << 16) + rand()) + avRandomSeed);
+}
+
+#endif /* MD5_SUPPORT */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/randm.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/randm.h
new file mode 100644
index 0000000..a0984b0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/randm.h
@@ -0,0 +1,81 @@
+/*****************************************************************************
+* randm.h - Random number generator header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-05-29 Guy Lancaster , Global Election Systems Inc.
+*   Extracted from avos.
+*****************************************************************************/
+
+#ifndef RANDM_H
+#define RANDM_H
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+/*
+ * Initialize the random number generator.
+ */
+void avRandomInit(void);
+
+/*
+ * Churn the randomness pool on a random event.  Call this early and often
+ * on random and semi-random system events to build randomness in time for
+ * usage.  For randomly timed events, pass a null pointer and a zero length
+ * and this will use the system timer and other sources to add randomness.
+ * If new random data is available, pass a pointer to that and it will be
+ * included.
+ */
+void avChurnRand(char *randData, u32_t randLen);
+
+/*
+ * Randomize our random seed value.  To be called for truely random events
+ * such as user operations and network traffic.
+ */
+#if MD5_SUPPORT
+#define avRandomize() avChurnRand(NULL, 0)
+#else  /* MD5_SUPPORT */
+void avRandomize(void);
+#endif /* MD5_SUPPORT */
+
+/*
+ * Use the random pool to generate random data.  This degrades to pseudo
+ * random when used faster than randomness is supplied using churnRand().
+ * Thus it's important to make sure that the results of this are not
+ * published directly because one could predict the next result to at
+ * least some degree.  Also, it's important to get a good seed before
+ * the first use.
+ */
+void avGenRand(char *buf, u32_t bufLen);
+
+/*
+ * Return a new random number.
+ */
+u32_t avRandom(void);
+
+
+#endif /* RANDM_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/vj.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/vj.c
new file mode 100644
index 0000000..694b702
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/vj.c
@@ -0,0 +1,660 @@
+/*
+ * Routines to compress and uncompess tcp packets (for transmission
+ * over low speed serial lines.
+ *
+ * Copyright (c) 1989 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Berkeley.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
+ *   Initial distribution.
+ *
+ * Modified June 1993 by Paul Mackerras, paulus@cs.anu.edu.au,
+ * so that the entire packet being decompressed doesn't have
+ * to be in contiguous memory (just the compressed header).
+ *
+ * Modified March 1998 by Guy Lancaster, glanca@gesn.com,
+ * for a 16 bit processor.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "vj.h"
+
+#include 
+
+#if VJ_SUPPORT
+
+#if LINK_STATS
+#define INCR(counter) ++comp->stats.counter
+#else
+#define INCR(counter)
+#endif
+
+#if defined(NO_CHAR_BITFIELDS)
+#define getip_hl(base)  ((base).ip_hl_v&0xf)
+#define getth_off(base) (((base).th_x2_off&0xf0)>>4)
+#else
+#define getip_hl(base)  ((base).ip_hl)
+#define getth_off(base) ((base).th_off)
+#endif
+
+void
+vj_compress_init(struct vjcompress *comp)
+{
+  register u_int i;
+  register struct cstate *tstate = comp->tstate;
+  
+#if MAX_SLOTS == 0
+  memset((char *)comp, 0, sizeof(*comp));
+#endif
+  comp->maxSlotIndex = MAX_SLOTS - 1;
+  comp->compressSlot = 0;    /* Disable slot ID compression by default. */
+  for (i = MAX_SLOTS - 1; i > 0; --i) {
+    tstate[i].cs_id = i;
+    tstate[i].cs_next = &tstate[i - 1];
+  }
+  tstate[0].cs_next = &tstate[MAX_SLOTS - 1];
+  tstate[0].cs_id = 0;
+  comp->last_cs = &tstate[0];
+  comp->last_recv = 255;
+  comp->last_xmit = 255;
+  comp->flags = VJF_TOSS;
+}
+
+
+/* ENCODE encodes a number that is known to be non-zero.  ENCODEZ
+ * checks for zero (since zero has to be encoded in the long, 3 byte
+ * form).
+ */
+#define ENCODE(n) { \
+  if ((u_short)(n) >= 256) { \
+    *cp++ = 0; \
+    cp[1] = (n); \
+    cp[0] = (n) >> 8; \
+    cp += 2; \
+  } else { \
+    *cp++ = (n); \
+  } \
+}
+#define ENCODEZ(n) { \
+  if ((u_short)(n) >= 256 || (u_short)(n) == 0) { \
+    *cp++ = 0; \
+    cp[1] = (n); \
+    cp[0] = (n) >> 8; \
+    cp += 2; \
+  } else { \
+    *cp++ = (n); \
+  } \
+}
+
+#define DECODEL(f) { \
+  if (*cp == 0) {\
+    u32_t tmp = ntohl(f) + ((cp[1] << 8) | cp[2]); \
+    (f) = htonl(tmp); \
+    cp += 3; \
+  } else { \
+    u32_t tmp = ntohl(f) + (u32_t)*cp++; \
+    (f) = htonl(tmp); \
+  } \
+}
+
+#define DECODES(f) { \
+  if (*cp == 0) {\
+    u_short tmp = ntohs(f) + (((u_short)cp[1] << 8) | cp[2]); \
+    (f) = htons(tmp); \
+    cp += 3; \
+  } else { \
+    u_short tmp = ntohs(f) + (u_short)*cp++; \
+    (f) = htons(tmp); \
+  } \
+}
+
+#define DECODEU(f) { \
+  if (*cp == 0) {\
+    (f) = htons(((u_short)cp[1] << 8) | cp[2]); \
+    cp += 3; \
+  } else { \
+    (f) = htons((u_short)*cp++); \
+  } \
+}
+
+/*
+ * vj_compress_tcp - Attempt to do Van Jacobson header compression on a
+ * packet.  This assumes that nb and comp are not null and that the first
+ * buffer of the chain contains a valid IP header.
+ * Return the VJ type code indicating whether or not the packet was
+ * compressed.
+ */
+u_int
+vj_compress_tcp(struct vjcompress *comp, struct pbuf *pb)
+{
+  register struct ip *ip = (struct ip *)pb->payload;
+  register struct cstate *cs = comp->last_cs->cs_next;
+  register u_short hlen = getip_hl(*ip);
+  register struct tcphdr *oth;
+  register struct tcphdr *th;
+  register u_short deltaS, deltaA;
+  register u_long deltaL;
+  register u_int changes = 0;
+  u_char new_seq[16];
+  register u_char *cp = new_seq;
+
+  /*  
+   * Check that the packet is IP proto TCP.
+   */
+  if (ip->ip_p != IPPROTO_TCP) {
+    return (TYPE_IP);
+  }
+
+  /*
+   * Bail if this is an IP fragment or if the TCP packet isn't
+   * `compressible' (i.e., ACK isn't set or some other control bit is
+   * set).  
+   */
+  if ((ip->ip_off & htons(0x3fff)) || pb->tot_len < 40) {
+    return (TYPE_IP);
+  }
+  th = (struct tcphdr *)&((long *)ip)[hlen];
+  if ((th->th_flags & (TCP_SYN|TCP_FIN|TCP_RST|TCP_ACK)) != TCP_ACK) {
+    return (TYPE_IP);
+  }
+  /*
+   * Packet is compressible -- we're going to send either a
+   * COMPRESSED_TCP or UNCOMPRESSED_TCP packet.  Either way we need
+   * to locate (or create) the connection state.  Special case the
+   * most recently used connection since it's most likely to be used
+   * again & we don't have to do any reordering if it's used.
+   */
+  INCR(vjs_packets);
+  if (ip->ip_src.s_addr != cs->cs_ip.ip_src.s_addr 
+      || ip->ip_dst.s_addr != cs->cs_ip.ip_dst.s_addr 
+      || *(long *)th != ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)]) {
+    /*
+     * Wasn't the first -- search for it.
+     *
+     * States are kept in a circularly linked list with
+     * last_cs pointing to the end of the list.  The
+     * list is kept in lru order by moving a state to the
+     * head of the list whenever it is referenced.  Since
+     * the list is short and, empirically, the connection
+     * we want is almost always near the front, we locate
+     * states via linear search.  If we don't find a state
+     * for the datagram, the oldest state is (re-)used.
+     */
+    register struct cstate *lcs;
+    register struct cstate *lastcs = comp->last_cs;
+    
+    do {
+      lcs = cs; cs = cs->cs_next;
+      INCR(vjs_searches);
+      if (ip->ip_src.s_addr == cs->cs_ip.ip_src.s_addr
+          && ip->ip_dst.s_addr == cs->cs_ip.ip_dst.s_addr
+          && *(long *)th == ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)]) {
+        goto found;
+      }
+    } while (cs != lastcs);
+
+    /*
+     * Didn't find it -- re-use oldest cstate.  Send an
+     * uncompressed packet that tells the other side what
+     * connection number we're using for this conversation.
+     * Note that since the state list is circular, the oldest
+     * state points to the newest and we only need to set
+     * last_cs to update the lru linkage.
+     */
+    INCR(vjs_misses);
+    comp->last_cs = lcs;
+    hlen += getth_off(*th);
+    hlen <<= 2;
+    /* Check that the IP/TCP headers are contained in the first buffer. */
+    if (hlen > pb->len) {
+      return (TYPE_IP);
+    }
+    goto uncompressed;
+
+    found:
+    /*
+     * Found it -- move to the front on the connection list.
+     */
+    if (cs == lastcs) {
+      comp->last_cs = lcs;
+    } else {
+      lcs->cs_next = cs->cs_next;
+      cs->cs_next = lastcs->cs_next;
+      lastcs->cs_next = cs;
+    }
+  }
+
+  oth = (struct tcphdr *)&((long *)&cs->cs_ip)[hlen];
+  deltaS = hlen;
+  hlen += getth_off(*th);
+  hlen <<= 2;
+  /* Check that the IP/TCP headers are contained in the first buffer. */
+  if (hlen > pb->len) {
+    PPPDEBUG((LOG_INFO, "vj_compress_tcp: header len %d spans buffers\n", hlen));
+    return (TYPE_IP);
+  }
+
+  /*
+   * Make sure that only what we expect to change changed. The first
+   * line of the `if' checks the IP protocol version, header length &
+   * type of service.  The 2nd line checks the "Don't fragment" bit.
+   * The 3rd line checks the time-to-live and protocol (the protocol
+   * check is unnecessary but costless).  The 4th line checks the TCP
+   * header length.  The 5th line checks IP options, if any.  The 6th
+   * line checks TCP options, if any.  If any of these things are
+   * different between the previous & current datagram, we send the
+   * current datagram `uncompressed'.
+   */
+  if (((u_short *)ip)[0] != ((u_short *)&cs->cs_ip)[0] 
+      || ((u_short *)ip)[3] != ((u_short *)&cs->cs_ip)[3] 
+      || ((u_short *)ip)[4] != ((u_short *)&cs->cs_ip)[4] 
+      || getth_off(*th) != getth_off(*oth) 
+      || (deltaS > 5 && BCMP(ip + 1, &cs->cs_ip + 1, (deltaS - 5) << 2)) 
+      || (getth_off(*th) > 5 && BCMP(th + 1, oth + 1, (getth_off(*th) - 5) << 2))) {
+    goto uncompressed;
+  }
+
+  /*
+   * Figure out which of the changing fields changed.  The
+   * receiver expects changes in the order: urgent, window,
+   * ack, seq (the order minimizes the number of temporaries
+   * needed in this section of code).
+   */
+  if (th->th_flags & TCP_URG) {
+    deltaS = ntohs(th->th_urp);
+    ENCODEZ(deltaS);
+    changes |= NEW_U;
+  } else if (th->th_urp != oth->th_urp) {
+    /* argh! URG not set but urp changed -- a sensible
+     * implementation should never do this but RFC793
+     * doesn't prohibit the change so we have to deal
+     * with it. */
+    goto uncompressed;
+  }
+
+  if ((deltaS = (u_short)(ntohs(th->th_win) - ntohs(oth->th_win))) != 0) {
+    ENCODE(deltaS);
+    changes |= NEW_W;
+  }
+
+  if ((deltaL = ntohl(th->th_ack) - ntohl(oth->th_ack)) != 0) {
+    if (deltaL > 0xffff) {
+      goto uncompressed;
+    }
+    deltaA = (u_short)deltaL;
+    ENCODE(deltaA);
+    changes |= NEW_A;
+  }
+
+  if ((deltaL = ntohl(th->th_seq) - ntohl(oth->th_seq)) != 0) {
+    if (deltaL > 0xffff) {
+      goto uncompressed;
+    }
+    deltaS = (u_short)deltaL;
+    ENCODE(deltaS);
+    changes |= NEW_S;
+  }
+
+  switch(changes) {
+  case 0:
+    /*
+     * Nothing changed. If this packet contains data and the
+     * last one didn't, this is probably a data packet following
+     * an ack (normal on an interactive connection) and we send
+     * it compressed.  Otherwise it's probably a retransmit,
+     * retransmitted ack or window probe.  Send it uncompressed
+     * in case the other side missed the compressed version.
+     */
+    if (ip->ip_len != cs->cs_ip.ip_len &&
+      ntohs(cs->cs_ip.ip_len) == hlen) {
+      break;
+    }
+
+  /* (fall through) */
+
+  case SPECIAL_I:
+  case SPECIAL_D:
+    /*
+     * actual changes match one of our special case encodings --
+     * send packet uncompressed.
+     */
+    goto uncompressed;
+
+  case NEW_S|NEW_A:
+    if (deltaS == deltaA && deltaS == ntohs(cs->cs_ip.ip_len) - hlen) {
+      /* special case for echoed terminal traffic */
+      changes = SPECIAL_I;
+      cp = new_seq;
+    }
+    break;
+
+  case NEW_S:
+    if (deltaS == ntohs(cs->cs_ip.ip_len) - hlen) {
+      /* special case for data xfer */
+      changes = SPECIAL_D;
+      cp = new_seq;
+    }
+    break;
+  }
+
+  deltaS = (u_short)(ntohs(ip->ip_id) - ntohs(cs->cs_ip.ip_id));
+  if (deltaS != 1) {
+    ENCODEZ(deltaS);
+    changes |= NEW_I;
+  }
+  if (th->th_flags & TCP_PSH) {
+    changes |= TCP_PUSH_BIT;
+  }
+  /*
+   * Grab the cksum before we overwrite it below.  Then update our
+   * state with this packet's header.
+   */
+  deltaA = ntohs(th->th_sum);
+  BCOPY(ip, &cs->cs_ip, hlen);
+
+  /*
+   * We want to use the original packet as our compressed packet.
+   * (cp - new_seq) is the number of bytes we need for compressed
+   * sequence numbers.  In addition we need one byte for the change
+   * mask, one for the connection id and two for the tcp checksum.
+   * So, (cp - new_seq) + 4 bytes of header are needed.  hlen is how
+   * many bytes of the original packet to toss so subtract the two to
+   * get the new packet size.
+   */
+  deltaS = (u_short)(cp - new_seq);
+  if (!comp->compressSlot || comp->last_xmit != cs->cs_id) {
+    comp->last_xmit = cs->cs_id;
+    hlen -= deltaS + 4;
+    if(pbuf_header(pb, -hlen)){
+      /* Can we cope with this failing?  Just assert for now */
+      LWIP_ASSERT("pbuf_header failed\n", 0);
+    }
+    cp = (u_char *)pb->payload;
+    *cp++ = changes | NEW_C;
+    *cp++ = cs->cs_id;
+  } else {
+    hlen -= deltaS + 3;
+    if(pbuf_header(pb, -hlen)) {
+      /* Can we cope with this failing?  Just assert for now */
+      LWIP_ASSERT("pbuf_header failed\n", 0);
+    }
+    cp = (u_char *)pb->payload;
+    *cp++ = changes;
+  }
+  *cp++ = deltaA >> 8;
+  *cp++ = deltaA;
+  BCOPY(new_seq, cp, deltaS);
+  INCR(vjs_compressed);
+  return (TYPE_COMPRESSED_TCP);
+
+  /*
+   * Update connection state cs & send uncompressed packet (that is,
+   * a regular ip/tcp packet but with the 'conversation id' we hope
+   * to use on future compressed packets in the protocol field).
+   */
+uncompressed:
+  BCOPY(ip, &cs->cs_ip, hlen);
+  ip->ip_p = cs->cs_id;
+  comp->last_xmit = cs->cs_id;
+  return (TYPE_UNCOMPRESSED_TCP);
+}
+
+/*
+ * Called when we may have missed a packet.
+ */
+void
+vj_uncompress_err(struct vjcompress *comp)
+{
+  comp->flags |= VJF_TOSS;
+  INCR(vjs_errorin);
+}
+
+/*
+ * "Uncompress" a packet of type TYPE_UNCOMPRESSED_TCP.
+ * Return 0 on success, -1 on failure.
+ */
+int
+vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp)
+{
+  register u_int hlen;
+  register struct cstate *cs;
+  register struct ip *ip;
+  
+  ip = (struct ip *)nb->payload;
+  hlen = getip_hl(*ip) << 2;
+  if (ip->ip_p >= MAX_SLOTS
+      || hlen + sizeof(struct tcphdr) > nb->len
+      || (hlen += getth_off(*((struct tcphdr *)&((char *)ip)[hlen])) << 2)
+          > nb->len
+      || hlen > MAX_HDR) {
+    PPPDEBUG((LOG_INFO, "vj_uncompress_uncomp: bad cid=%d, hlen=%d buflen=%d\n", 
+          ip->ip_p, hlen, nb->len));
+    comp->flags |= VJF_TOSS;
+    INCR(vjs_errorin);
+    return -1;
+  }
+  cs = &comp->rstate[comp->last_recv = ip->ip_p];
+  comp->flags &=~ VJF_TOSS;
+  ip->ip_p = IPPROTO_TCP;
+  BCOPY(ip, &cs->cs_ip, hlen);
+  cs->cs_hlen = hlen;
+  INCR(vjs_uncompressedin);
+  return 0;
+}
+
+/*
+ * Uncompress a packet of type TYPE_COMPRESSED_TCP.
+ * The packet is composed of a buffer chain and the first buffer
+ * must contain an accurate chain length.
+ * The first buffer must include the entire compressed TCP/IP header. 
+ * This procedure replaces the compressed header with the uncompressed
+ * header and returns the length of the VJ header.
+ */
+int
+vj_uncompress_tcp(struct pbuf **nb, struct vjcompress *comp)
+{
+  u_char *cp;
+  struct tcphdr *th;
+  struct cstate *cs;
+  u_short *bp;
+  struct pbuf *n0 = *nb;
+  u32_t tmp;
+  u_int vjlen, hlen, changes;
+
+  INCR(vjs_compressedin);
+  cp = (u_char *)n0->payload;
+  changes = *cp++;
+  if (changes & NEW_C) {
+    /* 
+     * Make sure the state index is in range, then grab the state.
+     * If we have a good state index, clear the 'discard' flag. 
+     */
+    if (*cp >= MAX_SLOTS) {
+      PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: bad cid=%d\n", *cp));
+      goto bad;
+    }
+
+    comp->flags &=~ VJF_TOSS;
+    comp->last_recv = *cp++;
+  } else {
+    /* 
+     * this packet has an implicit state index.  If we've
+     * had a line error since the last time we got an
+     * explicit state index, we have to toss the packet. 
+     */
+    if (comp->flags & VJF_TOSS) {
+      PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: tossing\n"));
+      INCR(vjs_tossed);
+      return (-1);
+    }
+  }
+  cs = &comp->rstate[comp->last_recv];
+  hlen = getip_hl(cs->cs_ip) << 2;
+  th = (struct tcphdr *)&((u_char *)&cs->cs_ip)[hlen];
+  th->th_sum = htons((*cp << 8) | cp[1]);
+  cp += 2;
+  if (changes & TCP_PUSH_BIT) {
+    th->th_flags |= TCP_PSH;
+  } else {
+    th->th_flags &=~ TCP_PSH;
+  }
+
+  switch (changes & SPECIALS_MASK) {
+  case SPECIAL_I:
+    {
+      register u32_t i = ntohs(cs->cs_ip.ip_len) - cs->cs_hlen;
+      /* some compilers can't nest inline assembler.. */
+      tmp = ntohl(th->th_ack) + i;
+      th->th_ack = htonl(tmp);
+      tmp = ntohl(th->th_seq) + i;
+      th->th_seq = htonl(tmp);
+    }
+    break;
+
+  case SPECIAL_D:
+    /* some compilers can't nest inline assembler.. */
+    tmp = ntohl(th->th_seq) + ntohs(cs->cs_ip.ip_len) - cs->cs_hlen;
+    th->th_seq = htonl(tmp);
+    break;
+
+  default:
+    if (changes & NEW_U) {
+      th->th_flags |= TCP_URG;
+      DECODEU(th->th_urp);
+    } else {
+      th->th_flags &=~ TCP_URG;
+    }
+    if (changes & NEW_W) {
+      DECODES(th->th_win);
+    }
+    if (changes & NEW_A) {
+      DECODEL(th->th_ack);
+    }
+    if (changes & NEW_S) {
+      DECODEL(th->th_seq);
+    }
+    break;
+  }
+  if (changes & NEW_I) {
+    DECODES(cs->cs_ip.ip_id);
+  } else {
+    cs->cs_ip.ip_id = ntohs(cs->cs_ip.ip_id) + 1;
+    cs->cs_ip.ip_id = htons(cs->cs_ip.ip_id);
+  }
+
+  /*
+   * At this point, cp points to the first byte of data in the
+   * packet.  Fill in the IP total length and update the IP
+   * header checksum.
+   */
+  vjlen = (u_short)(cp - (u_char*)n0->payload);
+  if (n0->len < vjlen) {
+    /* 
+     * We must have dropped some characters (crc should detect
+     * this but the old slip framing won't) 
+     */
+    PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: head buffer %d too short %d\n", 
+          n0->len, vjlen));
+    goto bad;
+  }
+
+#if BYTE_ORDER == LITTLE_ENDIAN
+  tmp = n0->tot_len - vjlen + cs->cs_hlen;
+  cs->cs_ip.ip_len = htons(tmp);
+#else
+  cs->cs_ip.ip_len = htons(n0->tot_len - vjlen + cs->cs_hlen);
+#endif
+
+  /* recompute the ip header checksum */
+  bp = (u_short *) &cs->cs_ip;
+  cs->cs_ip.ip_sum = 0;
+  for (tmp = 0; hlen > 0; hlen -= 2) {
+    tmp += *bp++;
+  }
+  tmp = (tmp & 0xffff) + (tmp >> 16);
+  tmp = (tmp & 0xffff) + (tmp >> 16);
+  cs->cs_ip.ip_sum = (u_short)(~tmp);
+  
+  /* Remove the compressed header and prepend the uncompressed header. */
+  if(pbuf_header(n0, -((s16_t)(vjlen)))) {
+    /* Can we cope with this failing?  Just assert for now */
+    LWIP_ASSERT("pbuf_header failed\n", 0);
+    goto bad;
+  }
+
+  if(LWIP_MEM_ALIGN(n0->payload) != n0->payload) {
+    struct pbuf *np, *q;
+    u8_t *bufptr;
+
+    np = pbuf_alloc(PBUF_RAW, n0->len + cs->cs_hlen, PBUF_POOL);
+    if(!np) {
+      PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: realign failed\n"));
+      goto bad;
+    }
+
+    if(pbuf_header(np, -cs->cs_hlen)) {
+      /* Can we cope with this failing?  Just assert for now */
+      LWIP_ASSERT("pbuf_header failed\n", 0);
+      goto bad;
+    }
+
+    bufptr = n0->payload;
+    for(q = np; q != NULL; q = q->next) {
+      MEMCPY(q->payload, bufptr, q->len);
+      bufptr += q->len;
+    }
+
+    if(n0->next) {
+      pbuf_chain(np, n0->next);
+      pbuf_dechain(n0);
+    }
+    pbuf_free(n0);
+    n0 = np;
+  }
+
+  if(pbuf_header(n0, cs->cs_hlen)) {
+    struct pbuf *np;
+
+    LWIP_ASSERT("vj_uncompress_tcp: cs->cs_hlen <= PBUF_POOL_BUFSIZE", cs->cs_hlen <= PBUF_POOL_BUFSIZE);
+    np = pbuf_alloc(PBUF_RAW, cs->cs_hlen, PBUF_POOL);
+    if(!np) {
+      PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: prepend failed\n"));
+      goto bad;
+    }
+    pbuf_cat(np, n0);
+    n0 = np;
+  }
+  LWIP_ASSERT("n0->len >= cs->cs_hlen", n0->len >= cs->cs_hlen);
+  MEMCPY(n0->payload, &cs->cs_ip, cs->cs_hlen);
+
+  *nb = n0;
+
+  return vjlen;
+
+bad:
+  comp->flags |= VJF_TOSS;
+  INCR(vjs_errorin);
+  return (-1);
+}
+
+#endif /* VJ_SUPPORT */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/vj.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/vj.h
new file mode 100644
index 0000000..b9617da
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/vj.h
@@ -0,0 +1,155 @@
+/*
+ * Definitions for tcp compression routines.
+ *
+ * $Id: vj.h,v 1.5 2007/12/19 20:47:23 fbernon Exp $
+ *
+ * Copyright (c) 1989 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Berkeley.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
+ * - Initial distribution.
+ */
+
+#ifndef VJ_H
+#define VJ_H
+
+#include "vjbsdhdr.h"
+
+#define MAX_SLOTS 16 /* must be > 2 and < 256 */
+#define MAX_HDR   128
+
+/*
+ * Compressed packet format:
+ *
+ * The first octet contains the packet type (top 3 bits), TCP
+ * 'push' bit, and flags that indicate which of the 4 TCP sequence
+ * numbers have changed (bottom 5 bits).  The next octet is a
+ * conversation number that associates a saved IP/TCP header with
+ * the compressed packet.  The next two octets are the TCP checksum
+ * from the original datagram.  The next 0 to 15 octets are
+ * sequence number changes, one change per bit set in the header
+ * (there may be no changes and there are two special cases where
+ * the receiver implicitly knows what changed -- see below).
+ * 
+ * There are 5 numbers which can change (they are always inserted
+ * in the following order): TCP urgent pointer, window,
+ * acknowlegement, sequence number and IP ID.  (The urgent pointer
+ * is different from the others in that its value is sent, not the
+ * change in value.)  Since typical use of SLIP links is biased
+ * toward small packets (see comments on MTU/MSS below), changes
+ * use a variable length coding with one octet for numbers in the
+ * range 1 - 255 and 3 octets (0, MSB, LSB) for numbers in the
+ * range 256 - 65535 or 0.  (If the change in sequence number or
+ * ack is more than 65535, an uncompressed packet is sent.)
+ */
+
+/*
+ * Packet types (must not conflict with IP protocol version)
+ *
+ * The top nibble of the first octet is the packet type.  There are
+ * three possible types: IP (not proto TCP or tcp with one of the
+ * control flags set); uncompressed TCP (a normal IP/TCP packet but
+ * with the 8-bit protocol field replaced by an 8-bit connection id --
+ * this type of packet syncs the sender & receiver); and compressed
+ * TCP (described above).
+ *
+ * LSB of 4-bit field is TCP "PUSH" bit (a worthless anachronism) and
+ * is logically part of the 4-bit "changes" field that follows.  Top
+ * three bits are actual packet type.  For backward compatibility
+ * and in the interest of conserving bits, numbers are chosen so the
+ * IP protocol version number (4) which normally appears in this nibble
+ * means "IP packet".
+ */
+
+/* packet types */
+#define TYPE_IP               0x40
+#define TYPE_UNCOMPRESSED_TCP 0x70
+#define TYPE_COMPRESSED_TCP   0x80
+#define TYPE_ERROR            0x00
+
+/* Bits in first octet of compressed packet */
+#define NEW_C 0x40 /* flag bits for what changed in a packet */
+#define NEW_I 0x20
+#define NEW_S 0x08
+#define NEW_A 0x04
+#define NEW_W 0x02
+#define NEW_U 0x01
+
+/* reserved, special-case values of above */
+#define SPECIAL_I (NEW_S|NEW_W|NEW_U) /* echoed interactive traffic */
+#define SPECIAL_D (NEW_S|NEW_A|NEW_W|NEW_U) /* unidirectional data */
+#define SPECIALS_MASK (NEW_S|NEW_A|NEW_W|NEW_U)
+
+#define TCP_PUSH_BIT 0x10
+
+
+/*
+ * "state" data for each active tcp conversation on the wire.  This is
+ * basically a copy of the entire IP/TCP header from the last packet
+ * we saw from the conversation together with a small identifier
+ * the transmit & receive ends of the line use to locate saved header.
+ */
+struct cstate {
+  struct cstate *cs_next; /* next most recently used state (xmit only) */
+  u_short cs_hlen;        /* size of hdr (receive only) */
+  u_char cs_id;           /* connection # associated with this state */
+  u_char cs_filler;
+  union {
+    char csu_hdr[MAX_HDR];
+    struct ip csu_ip;     /* ip/tcp hdr from most recent packet */
+  } vjcs_u;
+};
+#define cs_ip vjcs_u.csu_ip
+#define cs_hdr vjcs_u.csu_hdr
+
+
+struct vjstat {
+  unsigned long vjs_packets;        /* outbound packets */
+  unsigned long vjs_compressed;     /* outbound compressed packets */
+  unsigned long vjs_searches;       /* searches for connection state */
+  unsigned long vjs_misses;         /* times couldn't find conn. state */
+  unsigned long vjs_uncompressedin; /* inbound uncompressed packets */
+  unsigned long vjs_compressedin;   /* inbound compressed packets */
+  unsigned long vjs_errorin;        /* inbound unknown type packets */
+  unsigned long vjs_tossed;         /* inbound packets tossed because of error */
+};
+
+/*
+ * all the state data for one serial line (we need one of these per line).
+ */
+struct vjcompress {
+  struct cstate *last_cs;          /* most recently used tstate */
+  u_char last_recv;                /* last rcvd conn. id */
+  u_char last_xmit;                /* last sent conn. id */
+  u_short flags;
+  u_char maxSlotIndex;
+  u_char compressSlot;             /* Flag indicating OK to compress slot ID. */
+#if LINK_STATS
+  struct vjstat stats;
+#endif
+  struct cstate tstate[MAX_SLOTS]; /* xmit connection states */
+  struct cstate rstate[MAX_SLOTS]; /* receive connection states */
+};
+
+/* flag values */
+#define VJF_TOSS 1U /* tossing rcvd frames because of input err */
+
+extern void  vj_compress_init    (struct vjcompress *comp);
+extern u_int vj_compress_tcp     (struct vjcompress *comp, struct pbuf *pb);
+extern void  vj_uncompress_err   (struct vjcompress *comp);
+extern int   vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp);
+extern int   vj_uncompress_tcp   (struct pbuf **nb, struct vjcompress *comp);
+
+#endif /* VJ_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/vjbsdhdr.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/vjbsdhdr.h
new file mode 100644
index 0000000..f462676
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/ppp/vjbsdhdr.h
@@ -0,0 +1,75 @@
+#ifndef VJBSDHDR_H
+#define VJBSDHDR_H
+
+#include "lwip/tcp.h"
+
+/*
+ * Structure of an internet header, naked of options.
+ *
+ * We declare ip_len and ip_off to be short, rather than u_short
+ * pragmatically since otherwise unsigned comparisons can result
+ * against negative integers quite easily, and fail in subtle ways.
+ */
+PACK_STRUCT_BEGIN
+struct ip
+{
+#if defined(NO_CHAR_BITFIELDS)
+  u_char   ip_hl_v;  /* bug in GCC for mips means the bitfield stuff will sometimes break - so we use a char for both and get round it with macro's instead... */
+#else
+#if BYTE_ORDER == LITTLE_ENDIAN
+  unsigned ip_hl:4,              /* header length */
+           ip_v :4;              /* version */
+#elif BYTE_ORDER == BIG_ENDIAN 
+  unsigned ip_v :4,              /* version */
+           ip_hl:4;              /* header length */
+#else
+  COMPLAIN - NO BYTE ORDER SELECTED!
+#endif
+#endif
+  u_char  ip_tos;                /* type of service */
+  u_short ip_len;                /* total length */
+  u_short ip_id;                 /* identification */
+  u_short ip_off;                /* fragment offset field */
+#define  IP_DF 0x4000            /* dont fragment flag */
+#define  IP_MF 0x2000            /* more fragments flag */
+#define  IP_OFFMASK 0x1fff       /* mask for fragmenting bits */
+  u_char  ip_ttl;                /* time to live */
+  u_char  ip_p;                  /* protocol */
+  u_short ip_sum;                /* checksum */
+  struct  in_addr ip_src,ip_dst; /* source and dest address */
+};
+PACK_STRUCT_END
+
+typedef u32_t tcp_seq;
+
+/*
+ * TCP header.
+ * Per RFC 793, September, 1981.
+ */
+PACK_STRUCT_BEGIN
+struct tcphdr  
+{
+  u_short  th_sport;    /* source port */
+  u_short  th_dport;    /* destination port */
+  tcp_seq  th_seq;      /* sequence number */
+  tcp_seq  th_ack;      /* acknowledgement number */
+#if defined(NO_CHAR_BITFIELDS)
+  u_char   th_x2_off;
+#else
+#if BYTE_ORDER == LITTLE_ENDIAN
+  unsigned th_x2 :4,    /* (unused) */
+           th_off:4;    /* data offset */
+#endif
+#if BYTE_ORDER == BIG_ENDIAN 
+  unsigned th_off:4,    /* data offset */
+           th_x2 :4;    /* (unused) */
+#endif
+#endif
+  u_char   th_flags;
+  u_short  th_win;      /* window */
+  u_short  th_sum;      /* checksum */
+  u_short  th_urp;      /* urgent pointer */
+};
+PACK_STRUCT_END
+
+#endif /* VJBSDHDR_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/slipif.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/slipif.c
new file mode 100644
index 0000000..089d2d3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwIP_132/src/netif/slipif.c
@@ -0,0 +1,367 @@
+/**
+ * @file
+ * SLIP Interface
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is built upon the file: src/arch/rtxc/netif/sioslip.c
+ *
+ * Author: Magnus Ivarsson  
+ */
+
+/* 
+ * This is an arch independent SLIP netif. The specific serial hooks must be
+ * provided by another file. They are sio_open, sio_read/sio_tryread and sio_send
+ */
+
+#include "netif/slipif.h"
+#include "lwip/opt.h"
+
+#if LWIP_HAVE_SLIPIF
+
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+#include "lwip/sio.h"
+
+#define SLIP_BLOCK     1
+#define SLIP_DONTBLOCK 0
+
+#define SLIP_END     0300 /* 0xC0 */
+#define SLIP_ESC     0333 /* 0xDB */
+#define SLIP_ESC_END 0334 /* 0xDC */
+#define SLIP_ESC_ESC 0335 /* 0xDD */
+
+#define SLIP_MAX_SIZE 1500
+
+enum slipif_recv_state {
+    SLIP_RECV_NORMAL,
+    SLIP_RECV_ESCAPE,
+};
+
+struct slipif_priv {
+  sio_fd_t sd;
+  /* q is the whole pbuf chain for a packet, p is the current pbuf in the chain */
+  struct pbuf *p, *q;
+  enum slipif_recv_state state;
+  u16_t i, recved;
+};
+
+/**
+ * Send a pbuf doing the necessary SLIP encapsulation
+ *
+ * Uses the serial layer's sio_send()
+ *
+ * @param netif the lwip network interface structure for this slipif
+ * @param p the pbuf chaing packet to send
+ * @param ipaddr the ip address to send the packet to (not used for slipif)
+ * @return always returns ERR_OK since the serial layer does not provide return values
+ */
+err_t
+slipif_output(struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr)
+{
+  struct slipif_priv *priv;
+  struct pbuf *q;
+  u16_t i;
+  u8_t c;
+
+  LWIP_ASSERT("netif != NULL", (netif != NULL));
+  LWIP_ASSERT("netif->state != NULL", (netif->state != NULL));
+  LWIP_ASSERT("p != NULL", (p != NULL));
+
+  LWIP_UNUSED_ARG(ipaddr);
+
+  priv = netif->state;
+
+  /* Send pbuf out on the serial I/O device. */
+  sio_send(SLIP_END, priv->sd);
+
+  for (q = p; q != NULL; q = q->next) {
+    for (i = 0; i < q->len; i++) {
+      c = ((u8_t *)q->payload)[i];
+      switch (c) {
+      case SLIP_END:
+        sio_send(SLIP_ESC, priv->sd);
+        sio_send(SLIP_ESC_END, priv->sd);
+        break;
+      case SLIP_ESC:
+        sio_send(SLIP_ESC, priv->sd);
+        sio_send(SLIP_ESC_ESC, priv->sd);
+        break;
+      default:
+        sio_send(c, priv->sd);
+        break;
+      }
+    }
+  }
+  sio_send(SLIP_END, priv->sd);
+  return ERR_OK;
+}
+
+/**
+ * Static function for easy use of blockig or non-blocking
+ * sio_read
+ *
+ * @param fd serial device handle
+ * @param data pointer to data buffer for receiving
+ * @param len maximum length (in bytes) of data to receive
+ * @param block if 1, call sio_read; if 0, call sio_tryread
+ * @return return value of sio_read of sio_tryread
+ */
+static u32_t
+slip_sio_read(sio_fd_t fd, u8_t* data, u32_t len, u8_t block)
+{
+  if (block) {
+    return sio_read(fd, data, len);
+  } else {
+    return sio_tryread(fd, data, len);
+  }
+}
+
+/**
+ * Handle the incoming SLIP stream character by character
+ *
+ * Poll the serial layer by calling sio_read() or sio_tryread().
+ *
+ * @param netif the lwip network interface structure for this slipif
+ * @param block if 1, block until data is received; if 0, return when all data
+ *        from the buffer is received (multiple calls to this function will
+ *        return a complete packet, NULL is returned before - used for polling)
+ * @return The IP packet when SLIP_END is received
+ */
+static struct pbuf *
+slipif_input(struct netif *netif, u8_t block)
+{
+  struct slipif_priv *priv;
+  u8_t c;
+  struct pbuf *t;
+
+  LWIP_ASSERT("netif != NULL", (netif != NULL));
+  LWIP_ASSERT("netif->state != NULL", (netif->state != NULL));
+
+  priv = netif->state;
+
+  while (slip_sio_read(priv->sd, &c, 1, block) > 0) {
+    switch (priv->state) {
+    case SLIP_RECV_NORMAL:
+      switch (c) {
+      case SLIP_END:
+        if (priv->recved > 0) {
+          /* Received whole packet. */
+          /* Trim the pbuf to the size of the received packet. */
+          pbuf_realloc(priv->q, priv->recved);
+
+          LINK_STATS_INC(link.recv);
+
+          LWIP_DEBUGF(SLIP_DEBUG, ("slipif: Got packet\n"));
+          t = priv->q;
+          priv->p = priv->q = NULL;
+          priv->i = priv->recved = 0;
+          return t;
+        }
+        continue;
+      case SLIP_ESC:
+        priv->state = SLIP_RECV_ESCAPE;
+        continue;
+      }
+      break;
+    case SLIP_RECV_ESCAPE:
+      switch (c) {
+      case SLIP_ESC_END:
+        c = SLIP_END;
+        break;
+      case SLIP_ESC_ESC:
+        c = SLIP_ESC;
+        break;
+      }
+      priv->state = SLIP_RECV_NORMAL;
+      /* FALLTHROUGH */
+    }
+
+    /* byte received, packet not yet completely received */
+    if (priv->p == NULL) {
+      /* allocate a new pbuf */
+      LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: alloc\n"));
+      priv->p = pbuf_alloc(PBUF_LINK, (PBUF_POOL_BUFSIZE - PBUF_LINK_HLEN), PBUF_POOL);
+
+      if (priv->p == NULL) {
+        LINK_STATS_INC(link.drop);
+        LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: no new pbuf! (DROP)\n"));
+        /* don't process any further since we got no pbuf to receive to */
+        break;
+      }
+
+      if (priv->q != NULL) {
+        /* 'chain' the pbuf to the existing chain */
+        pbuf_cat(priv->q, priv->p);
+      } else {
+        /* p is the first pbuf in the chain */
+        priv->q = priv->p;
+      }
+    }
+
+    /* this automatically drops bytes if > SLIP_MAX_SIZE */
+    if ((priv->p != NULL) && (priv->recved <= SLIP_MAX_SIZE)) {
+      ((u8_t *)priv->p->payload)[priv->i] = c;
+      priv->recved++;
+      priv->i++;
+      if (priv->i >= priv->p->len) {
+        /* on to the next pbuf */
+        priv->i = 0;
+        if (priv->p->next != NULL && priv->p->next->len > 0) {
+          /* p is a chain, on to the next in the chain */
+            priv->p = priv->p->next;
+        } else {
+          /* p is a single pbuf, set it to NULL so next time a new
+           * pbuf is allocated */
+            priv->p = NULL;
+        }
+      }
+    }
+  }
+
+  return NULL;
+}
+
+#if !NO_SYS
+/**
+ * The SLIP input thread.
+ *
+ * Feed the IP layer with incoming packets
+ *
+ * @param nf the lwip network interface structure for this slipif
+ */
+static void
+slipif_loop_thread(void *nf)
+{
+  struct pbuf *p;
+  struct netif *netif = (struct netif *)nf;
+
+  while (1) {
+    p = slipif_input(netif, SLIP_BLOCK);
+    if (p != NULL) {
+      if (netif->input(p, netif) != ERR_OK) {
+        pbuf_free(p);
+        p = NULL;
+      }
+    }
+  }
+}
+#endif /* !NO_SYS */
+
+/**
+ * SLIP netif initialization
+ *
+ * Call the arch specific sio_open and remember
+ * the opened device in the state field of the netif.
+ *
+ * @param netif the lwip network interface structure for this slipif
+ * @return ERR_OK if serial line could be opened,
+ *         ERR_MEM if no memory could be allocated,
+ *         ERR_IF is serial line couldn't be opened
+ *
+ * @note netif->num must contain the number of the serial port to open
+ *       (0 by default)
+ */
+err_t
+slipif_init(struct netif *netif)
+{
+  struct slipif_priv *priv;
+
+  LWIP_DEBUGF(SLIP_DEBUG, ("slipif_init: netif->num=%"U16_F"\n", (u16_t)netif->num));
+
+  /* Allocate private data */
+  priv = mem_malloc(sizeof(struct slipif_priv));
+  if (!priv) {
+    return ERR_MEM;
+  }
+
+  netif->name[0] = 's';
+  netif->name[1] = 'l';
+  netif->output = slipif_output;
+  netif->mtu = SLIP_MAX_SIZE;
+  netif->flags |= NETIF_FLAG_POINTTOPOINT;
+
+  /* Try to open the serial port (netif->num contains the port number). */
+  priv->sd = sio_open(netif->num);
+  if (!priv->sd) {
+    /* Opening the serial port failed. */
+    mem_free(priv);
+    return ERR_IF;
+  }
+
+  /* Initialize private data */
+  priv->p = NULL;
+  priv->q = NULL;
+  priv->state = SLIP_RECV_NORMAL;
+  priv->i = 0;
+  priv->recved = 0;
+
+  netif->state = priv;
+
+  /* initialize the snmp variables and counters inside the struct netif
+   * ifSpeed: no assumption can be made without knowing more about the
+   * serial line!
+   */
+  NETIF_INIT_SNMP(netif, snmp_ifType_slip, 0);
+
+  /* Create a thread to poll the serial line. */
+  sys_thread_new(SLIPIF_THREAD_NAME, slipif_loop_thread, netif,
+    SLIPIF_THREAD_STACKSIZE, SLIPIF_THREAD_PRIO);
+  return ERR_OK;
+}
+
+/**
+ * Polls the serial device and feeds the IP layer with incoming packets.
+ *
+ * @param netif The lwip network interface structure for this slipif
+ */
+void
+slipif_poll(struct netif *netif)
+{
+  struct pbuf *p;
+  struct slipif_priv *priv;
+
+  LWIP_ASSERT("netif != NULL", (netif != NULL));
+  LWIP_ASSERT("netif->state != NULL", (netif->state != NULL));
+
+  priv = netif->state;
+
+  while ((p = slipif_input(netif, SLIP_DONTBLOCK)) != NULL) {
+    if (netif->input(p, netif) != ERR_OK) {
+      pbuf_free(p);
+    }
+  }
+}
+
+#endif /* LWIP_HAVE_SLIPIF */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/CHANGELOG b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/CHANGELOG
new file mode 100644
index 0000000..6e27a66
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/CHANGELOG
@@ -0,0 +1,3050 @@
+HISTORY
+
+(CVS HEAD)
+
+  * [Enter new changes just after this line - do not remove this line]
+
+ ++ New features:
+
+
+ ++ Bugfixes:
+
+
+
+
+(STABLE-1.4.0)
+
+  ++ New features:
+
+  2011-03-27: Simon Goldschmidt
+  * tcp_impl.h, tcp_in.c, tcp_out.c: Removed 'dataptr' from 'struct tcp_seg' and
+    calculate it in tcp_zero_window_probe (the only place where it was used).
+
+  2010-11-21: Simon Goldschmidt
+  * dhcp.c/.h: Added a function to deallocate the struct dhcp from a netif
+    (fixes bug #31525).
+
+  2010-07-12: Simon Goldschmidt (patch by Stephane Lesage)
+  * ip.c, udp.c/.h, pbuf.h, sockets.c: task #10495: Added support for
+    IP_MULTICAST_LOOP at socket- and raw-API level.
+
+  2010-06-16: Simon Goldschmidt
+  * ip.c: Added an optional define (LWIP_IP_ACCEPT_UDP_PORT) that can allow
+    link-layer-addressed UDP traffic to be received while a netif is down (just
+    like DHCP during configuration)
+
+  2010-05-22: Simon Goldschmidt
+  * many many files: bug #27352: removed packing from ip_addr_t, the packed
+    version is now only used in protocol headers. Added global storage for
+    current src/dest IP address while in input functions.
+
+  2010-05-16: Simon Goldschmidt
+  * def.h: task #10391: Add preprocessor-macros for compile-time htonl
+    calculation (and use them throughout the stack where applicable)
+
+  2010-05-16: Simon Goldschmidt
+  * opt.h, memp_std.h, memp.c, ppp_oe.h/.c: PPPoE now uses its own MEMP pool
+    instead of the heap (moved struct pppoe_softc from ppp_oe.c to ppp_oe.h)
+
+  2010-05-16: Simon Goldschmidt
+  * opt.h, memp_std.h, dns.h/.c: DNS_LOCAL_HOSTLIST_IS_DYNAMIC uses its own
+    MEMP pool instead of the heap
+
+  2010-05-13: Simon Goldschmidt
+  * tcp.c, udp.c: task #6995: Implement SO_REUSEADDR (correctly), added
+    new option SO_REUSE_RXTOALL to pass received UDP broadcast/multicast
+    packets to more than one pcb.
+
+  2010-05-02: Simon Goldschmidt
+  * netbuf.h/.c, sockets.c, api_msg.c: use checksum-on-copy for sending
+    UDP data for LWIP_NETIF_TX_SINGLE_PBUF==1
+
+  2010-04-30: Simon Goldschmidt
+  * udp.h/.c, pbuf.h/.c: task #6849: added udp_send(_to/_if) functions that
+    take a precalculated checksum, added pbuf_fill_chksum() to copy data
+    into a pbuf and at the same time calculating the checksum for that data
+
+  2010-04-29: Simon Goldschmidt
+  * ip_addr.h, etharp.h/.c, autoip.c: Create overridable macros for copying
+    2-byte-aligned IP addresses and MAC addresses
+
+  2010-04-28: Patch by Bill Auerbach
+  * ip.c: Inline generating IP checksum to save a function call
+
+  2010-04-14: Simon Goldschmidt
+  * tcpip.h/.c, timers.c: Added an overridable define to get informed when the
+    tcpip_thread processes messages or timeouts to implement a watchdog.
+
+  2010-03-28: Simon Goldschmidt
+  * ip_frag.c: create a new (contiguous) PBUF_RAM for every outgoing
+    fragment if LWIP_NETIF_TX_SINGLE_PBUF==1
+
+  2010-03-27: Simon Goldschmidt
+  * etharp.c: Speedup TX by moving code from find_entry to etharp_output/
+    etharp_query to prevent unnecessary function calls (inspired by
+    patch #7135).
+
+  2010-03-20: Simon Goldschmidt
+  * opt.h, tcpip.c/.h: Added an option to disable tcpip_(un)timeout code
+    since the linker cannot do this automatically to save space.
+
+  2010-03-20: Simon Goldschmidt
+  * opt.h, etharp.c/.h: Added support for static ARP table entries
+
+  2010-03-14: Simon Goldschmidt
+  * tcp_impl.h, tcp_out.c, inet_chksum.h/.c: task #6849: Calculate checksum
+    when creating TCP segments, not when (re-)transmitting them.
+
+  2010-03-07: Simon Goldschmidt
+  * sockets.c: bug #28775 (select/event_callback: only check select_cb_list
+    on change) plus use SYS_LIGHTWEIGHT_PROT to protect the select code.
+    This should speed up receiving data on sockets as the select code in
+    event_callback is only executed when select is waiting.
+
+  2010-03-06: Simon Goldschmidt
+  * tcp_out.c: task #7013 (Create option to have all packets delivered to
+    netif->output in one piece): Always copy to try to create single pbufs
+    in tcp_write.
+
+  2010-03-06: Simon Goldschmidt
+  * api.h, api_lib.c, sockets.c: task #10167 (sockets: speed up TCP recv
+    by not allocating a netbuf): added function netconn_recv_tcp_pbuf()
+    for tcp netconns to receive pbufs, not netbufs; use that function
+    for tcp sockets.
+
+  2010-03-05: Jakob Ole Stoklundsen / Simon Goldschmidt
+  * opt.h, tcp.h, tcp_impl.h, tcp.c, tcp_in.c, tcp_out.c: task #7040:
+    Work on tcp_enqueue: Don't waste memory when chaining segments,
+    added option TCP_OVERSIZE to prevent creating many small pbufs when
+    calling tcp_write with many small blocks of data. Instead, pbufs are
+    allocated larger than needed and the space is used for later calls to
+    tcp_write.
+
+  2010-02-21: Simon Goldschmidt
+  * stats.c/.h: Added const char* name to mem- and memp-stats for easier
+    debugging.
+
+  2010-02-21: Simon Goldschmidt
+  * tcp.h (and usages), added tcp_impl.h: Splitted API and internal
+    implementation of tcp to make API usage cleare to application programmers
+
+  2010-02-14: Simon Goldschmidt/Stephane Lesage
+  * ip_addr.h: Improved some defines working on ip addresses, added faster
+    macro to copy addresses that cannot be NULL
+
+  2010-02-13: Simon Goldschmidt
+  * api.h, api_lib.c, api_msg.c, sockets.c: task #7865 (implement non-
+    blocking send operation)
+
+  2010-02-12: Simon Goldschmidt
+  * sockets.c/.h: Added a minimal version of posix fctl() to have a
+    standardised way to set O_NONBLOCK for nonblocking sockets.
+
+  2010-02-12: Simon Goldschmidt
+  * dhcp.c/.h, autoip.c/.h: task #10139 (Prefer statically allocated
+    memory): added autoip_set_struct() and dhcp_set_struct() to let autoip
+    and dhcp work with user-allocated structs instead of callin mem_malloc
+
+  2010-02-12: Simon Goldschmidt/Jeff Barber
+  * tcp.c/h: patch #6865 (SO_REUSEADDR for TCP): if pcb.so_options has
+    SOF_REUSEADDR set, allow binding to endpoint in TIME_WAIT
+
+  2010-02-12: Simon Goldschmidt
+  * sys layer: task #10139 (Prefer statically allocated memory): converted
+    mbox and semaphore functions to take pointers to sys_mbox_t/sys_sem_t;
+    converted sys_mbox_new/sys_sem_new to take pointers and return err_t;
+    task #7212: Add Mutex concept in sys_arch (define LWIP_COMPAT_MUTEX
+    to let sys.h use binary semaphores instead of mutexes - as before)
+
+  2010-02-09: Simon Goldschmidt (Simon Kallweit)
+  * timers.c/.h: Added function sys_restart_timeouts() from patch #7085
+    (Restart system timeout handling)
+
+  2010-02-09: Simon Goldschmidt
+  * netif.c/.h, removed loopif.c/.h: task #10153 (Integrate loopif into
+    netif.c) - loopif does not have to be created by the port any more,
+    just define LWIP_HAVE_LOOPIF to 1.
+
+  2010-02-08: Simon Goldschmidt
+  * inet.h, ip_addr.c/.h: Added reentrant versions of inet_ntoa/ipaddr_ntoa
+    inet_ntoa_r/ipaddr_ntoa_r
+
+  2010-02-08: Simon Goldschmidt
+  * netif.h: Added netif_s/get_igmp_mac_filter() macros
+
+  2010-02-05: Simon Goldschmidt
+  * netif.h: Added function-like macros to get/set the hostname on a netif
+
+  2010-02-04: Simon Goldschmidt
+  * nearly every file: Replaced struct ip_addr by typedef ip_addr_t to
+    make changing the actual implementation behind the typedef easier.
+
+  2010-02-01: Simon Goldschmidt
+  * opt.h, memp_std.h, dns.h, netdb.c, memp.c: Let netdb use a memp pool
+    for allocating memory when getaddrinfo() is called.
+
+  2010-01-31: Simon Goldschmidt
+  * dhcp.h, dhcp.c: Reworked the code that parses DHCP options: parse
+    them once instead of parsing for every option. This also removes
+    the need for mem_malloc from dhcp_recv and makes it possible to
+    correctly retrieve the BOOTP file.
+
+  2010-01-30: simon Goldschmidt
+  * sockets.c: Use SYS_LIGHTWEIGHT_PROT instead of a semaphore to protect
+    the sockets array.
+
+  2010-01-29: Simon Goldschmidt (patch by Laura Garrett)
+  * api.h, api_msg.c, sockets.c: Added except set support in select
+    (patch #6860)
+
+  2010-01-29: Simon Goldschmidt (patch by Laura Garrett)
+  * api.h, sockets.h, err.h, api_lib.c, api_msg.c, sockets.c, err.c:
+    Add non-blocking support for connect (partly from patch #6860),
+    plus many cleanups in socket & netconn API.
+
+  2010-01-27: Simon Goldschmidt
+  * opt.h, tcp.h, init.c, api_msg.c: Added TCP_SNDQUEUELOWAT corresponding
+    to TCP_SNDLOWAT and added tcp_sndqueuelen() - this fixes bug #28605
+
+  2010-01-26: Simon Goldschmidt
+  * snmp: Use memp pools for snmp instead of the heap; added 4 new pools.
+
+  2010-01-14: Simon Goldschmidt
+  * ppp.c/.h: Fixed bug #27856: PPP: Set netif link- and status-callback
+    by adding ppp_set_netif_statuscallback()/ppp_set_netif_linkcallback()
+
+  2010-01-13: Simon Goldschmidt
+  * mem.c: The heap now may be moved to user-defined memory by defining
+    LWIP_RAM_HEAP_POINTER as a void pointer to that memory's address
+    (patch #6966 and bug #26133)
+
+  2010-01-10: Simon Goldschmidt (Bill Auerbach)
+  * opt.h, memp.c: patch #6822 (Add option to place memory pools in
+    separate arrays)
+
+  2010-01-10: Simon Goldschmidt
+  * init.c, igmp.c: patch #6463 (IGMP - Adding Random Delay): added define
+    LWIP_RAND() for lwip-wide randomization (to be defined in cc.h)
+
+  2009-12-31: Simon Goldschmidt
+  * tcpip.c, init.c, memp.c, sys.c, memp_std.h, sys.h, tcpip.h
+    added timers.c/.h: Separated timer implementation from semaphore/mbox
+    implementation, moved timer implementation to timers.c/.h, timers are
+    now only called from tcpip_thread or by explicitly checking them.
+    (TASK#7235)
+
+  2009-12-27: Simon Goldschmidt
+  * opt.h, etharp.h/.c, init.c, tcpip.c: Added an additional option
+    LWIP_ETHERNET to support ethernet without ARP (necessary for pure PPPoE)
+
+
+  ++ Bugfixes:
+
+  2011-04-20: Simon Goldschmidt
+  * sys_arch.txt: sys_arch_timeouts() is not needed any more.
+
+  2011-04-13: Simon Goldschmidt
+  * tcp.c, udp.c: Fixed bug #33048 (Bad range for IP source port numbers) by
+    using ports in the IANA private/dynamic range (49152 through 65535).
+
+  2011-03-29: Simon Goldschmidt, patch by Emil Lhungdahl:
+  * etharp.h/.c: Fixed broken VLAN support.
+
+  2011-03-27: Simon Goldschmidt
+  * tcp.c: Fixed bug #32926 (TCP_RMV(&tcp_bound_pcbs) is called on unbound tcp
+    pcbs) by checking if the pcb was bound (local_port != 0).
+
+  2011-03-27: Simon Goldschmidt
+  * ppp.c: Fixed bug #32280 (ppp: a pbuf is freed twice)
+
+  2011-03-27: Simon Goldschmidt
+  * sockets.c: Fixed bug #32906: lwip_connect+lwip_send did not work for udp and
+    raw pcbs with LWIP_TCPIP_CORE_LOCKING==1.
+  
+  2011-03-27: Simon Goldschmidt
+  * tcp_out.c: Fixed bug #32820 (Outgoing TCP connections created before route
+    is present never times out) by starting retransmission timer before checking
+    route.
+
+  2011-03-22: Simon Goldschmidt
+  * ppp.c: Fixed bug #32648 (PPP code crashes when terminating a link) by only
+    calling sio_read_abort() if the file descriptor is valid.
+
+  2011-03-14: Simon Goldschmidt
+  * err.h/.c, sockets.c, api_msg.c: fixed bug #31748 (Calling non-blocking connect
+    more than once can render a socket useless) since it mainly involves changing
+    "FATAL" classification of error codes: ERR_USE and ERR_ISCONN just aren't fatal.
+
+  2011-03-13: Simon Goldschmidt
+  * sockets.c: fixed bug #32769 (ESHUTDOWN is linux-specific) by fixing
+    err_to_errno_table (ERR_CLSD: ENOTCONN instead of ESHUTDOWN), ERR_ISCONN:
+    use EALRADY instead of -1
+
+  2011-03-13: Simon Goldschmidt
+  * api_lib.c: netconn_accept: return ERR_ABRT instead of ERR_CLSD if the
+    connection has been aborted by err_tcp (since this is not a normal closing
+    procedure).
+
+  2011-03-13: Simon Goldschmidt
+  * tcp.c: tcp_bind: return ERR_VAL instead of ERR_ISCONN when trying to bind
+    with pcb->state != CLOSED
+
+  2011-02-17: Simon Goldschmidt
+  * rawapi.txt: Fixed bug #32561 tcp_poll argument definition out-of-order in
+    documentation
+
+  2011-02-17: Simon Goldschmidt
+  * many files: Added missing U/UL modifiers to fix 16-bit-arch portability.
+
+  2011-01-24: Simon Goldschmidt
+  * sockets.c: Fixed bug #31741: lwip_select seems to have threading problems
+
+  2010-12-02: Simon Goldschmidt
+  * err.h: Fixed ERR_IS_FATAL so that ERR_WOULDBLOCK is not fatal.
+
+  2010-11-23: Simon Goldschmidt
+  * api.h, api_lib.c, api_msg.c, sockets.c: netconn.recv_avail is only used for
+    LWIP_SO_RCVBUF and ioctl/FIONREAD.
+
+  2010-11-23: Simon Goldschmidt
+  * etharp.c: Fixed bug #31720: ARP-queueing: RFC 1122 recommends to queue at
+    least 1 packet -> ARP_QUEUEING==0 now queues the most recent packet.
+
+  2010-11-23: Simon Goldschmidt
+  * tcp_in.c: Fixed bug #30577: tcp_input: don't discard ACK-only packets after
+    refusing 'refused_data' again.
+  
+  2010-11-22: Simon Goldschmidt
+  * sockets.c: Fixed bug #31590: getsockopt(... SO_ERROR ...) gives EINPROGRESS
+    after a successful nonblocking connection.
+
+  2010-11-22: Simon Goldschmidt
+  * etharp.c: Fixed bug #31722: IP packets sent with an AutoIP source addr
+    must be sent link-local
+
+  2010-11-22: Simon Goldschmidt
+  * timers.c: patch #7329: tcp_timer_needed prototype was ifdef'ed out for
+    LWIP_TIMERS==0
+
+  2010-11-20: Simon Goldschmidt
+  * sockets.c: Fixed bug #31170: lwip_setsockopt() does not set socket number
+
+  2010-11-20: Simon Goldschmidt
+  * sockets.h: Fixed bug #31304: Changed SHUT_RD, SHUT_WR and SHUT_RDWR to
+    resemble other stacks.
+
+  2010-11-20: Simon Goldschmidt
+  * dns.c: Fixed bug #31535: TCP_SND_QUEUELEN must be at least 2 or else
+    no-copy TCP writes will never succeed.
+
+  2010-11-20: Simon Goldschmidt
+  * dns.c: Fixed bug #31701: Error return value from dns_gethostbyname() does
+    not match documentation: return ERR_ARG instead of ERR_VAL if not
+    initialized or wrong argument.
+
+  2010-10-20: Simon Goldschmidt
+  * sockets.h: Fixed bug #31385: sizeof(struct sockaddr) is 30 but should be 16
+
+  2010-10-05: Simon Goldschmidt
+  * dhcp.c: Once again fixed #30038: DHCP/AutoIP cooperation failed when
+    replugging the network cable after an AutoIP address was assigned.
+
+  2010-08-10: Simon Goldschmidt
+  * tcp.c: Fixed bug #30728: tcp_new_port() did not check listen pcbs
+
+  2010-08-03: Simon Goldschmidt
+  * udp.c, raw.c: Don't chain empty pbufs when sending them (fixes bug #30625)
+
+  2010-08-01: Simon Goldschmidt (patch by Greg Renda)
+  * ppp.c: Applied patch #7264 (PPP protocols are rejected incorrectly on big
+    endian architectures)
+  
+  2010-07-28: Simon Goldschmidt
+  * api_lib.c, api_msg.c, sockets.c, mib2.c: Fixed compilation with TCP or UDP
+    disabled.
+  
+  2010-07-27: Simon Goldschmidt
+  * tcp.c: Fixed bug #30565 (tcp_connect() check bound list): that check did no
+    harm but never did anything
+  
+  2010-07-21: Simon Goldschmidt
+  * ip.c: Fixed invalid fix for bug #30402 (CHECKSUM_GEN_IP_INLINE does not
+    add IP options)
+
+  2010-07-16: Kieran Mansley
+  * msg_in.c: Fixed SNMP ASN constant defines to not use ! operator 
+
+  2010-07-10: Simon Goldschmidt
+  * ip.c: Fixed bug #30402: CHECKSUM_GEN_IP_INLINE does not add IP options
+
+  2010-06-30: Simon Goldschmidt
+  * api_msg.c: fixed bug #30300 (shutdown parameter was not initialized in
+    netconn_delete)
+
+  2010-06-28: Kieran Mansley
+  * timers.c remove unportable printing of C function pointers
+
+  2010-06-24: Simon Goldschmidt
+  * init.c, timers.c/.h, opt.h, memp_std.h: From patch #7221: added flag
+    NO_SYS_NO_TIMERS to drop timer support for NO_SYS==1 for easier upgrading
+
+  2010-06-24: Simon Goldschmidt
+  * api(_lib).c/.h, api_msg.c/.h, sockets.c/.h: Fixed bug #10088: Correctly
+    implemented shutdown at socket level.
+
+  2010-06-21: Simon Goldschmidt
+  * pbuf.c/.h, ip_frag.c/.h, opt.h, memp_std.h: Fixed bug #29361 (ip_frag has
+    problems with zero-copy DMA MACs) by adding custom pbufs and implementing
+    custom pbufs that reference other (original) pbufs. Additionally set
+    IP_FRAG_USES_STATIC_BUF=0 as default to be on the safe side.
+
+  2010-06-15: Simon Goldschmidt
+  * dhcp.c: Fixed bug #29970: DHCP endian issue parsing option responses
+
+  2010-06-14: Simon Goldschmidt
+  * autoip.c: Fixed bug #30039: AutoIP does not reuse previous addresses
+
+  2010-06-12: Simon Goldschmidt
+  * dhcp.c: Fixed bug #30038: dhcp_network_changed doesn't reset AUTOIP coop
+    state
+
+  2010-05-17: Simon Goldschmidt
+  * netdb.c: Correctly NULL-terminate h_addr_list
+
+  2010-05-16: Simon Goldschmidt
+  * def.h/.c: changed the semantics of LWIP_PREFIX_BYTEORDER_FUNCS to prevent
+    "symbol already defined" i.e. when linking to winsock
+
+  2010-05-05: Simon Goldschmidt
+  * def.h, timers.c: Fixed bug #29769 (sys_check_timeouts: sys_now() may
+    overflow)
+
+  2010-04-21: Simon Goldschmidt
+  * api_msg.c: Fixed bug #29617 (sometime cause stall on delete listening
+    connection)
+
+  2010-03-28: Luca Ceresoli
+  * ip_addr.c/.h: patch #7143: Add a few missing const qualifiers
+
+  2010-03-27: Luca Ceresoli
+  * mib2.c: patch #7130: remove meaningless const qualifiers
+
+  2010-03-26: Simon Goldschmidt
+  * tcp_out.c: Make LWIP_NETIF_TX_SINGLE_PBUF work for TCP, too
+
+  2010-03-26: Simon Goldschmidt
+  * various files: Fixed compiling with different options disabled (TCP/UDP),
+    triggered by bug #29345; don't allocate acceptmbox if LWIP_TCP is disabled
+
+  2010-03-25: Simon Goldschmidt
+  * sockets.c: Fixed bug #29332: lwip_select() processes readset incorrectly
+
+  2010-03-25: Simon Goldschmidt
+  * tcp_in.c, test_tcp_oos.c: Fixed bug #29080: Correctly handle remote side
+    overrunning our rcv_wnd in ooseq case.
+
+  2010-03-22: Simon Goldschmidt
+  * tcp.c: tcp_listen() did not copy the pcb's prio.
+
+  2010-03-19: Simon Goldschmidt
+  * snmp_msg.c: Fixed bug #29256: SNMP Trap address was not correctly set
+
+  2010-03-14: Simon Goldschmidt
+  * opt.h, etharp.h: Fixed bug #29148 (Incorrect PBUF_POOL_BUFSIZE for ports
+    where ETH_PAD_SIZE > 0) by moving definition of ETH_PAD_SIZE to opt.h
+    and basing PBUF_LINK_HLEN on it.
+
+  2010-03-08: Simon Goldschmidt
+  * netif.c, ipv4/ip.c: task #10241 (AutoIP: don't break existing connections
+    when assiging routable address): when checking incoming packets and
+    aborting existing connection on address change, filter out link-local
+    addresses.
+
+  2010-03-06: Simon Goldschmidt
+  * sockets.c: Fixed LWIP_NETIF_TX_SINGLE_PBUF for LWIP_TCPIP_CORE_LOCKING
+
+  2010-03-06: Simon Goldschmidt
+  * ipv4/ip.c: Don't try to forward link-local addresses
+
+  2010-03-06: Simon Goldschmidt
+  * etharp.c: Fixed bug #29087: etharp: don't send packets for LinkLocal-
+    addresses to gw
+
+  2010-03-05: Simon Goldschmidt
+  * dhcp.c: Fixed bug #29072: Correctly set ciaddr based on message-type
+    and state.
+
+  2010-03-05: Simon Goldschmidt
+  * api_msg.c: Correctly set TCP_WRITE_FLAG_MORE when netconn_write is split
+    into multiple calls to tcp_write.    
+
+  2010-02-21: Simon Goldschmidt
+  * opt.h, mem.h, dns.c: task #10140: Remove DNS_USES_STATIC_BUF (keep
+    the implementation of DNS_USES_STATIC_BUF==1)
+
+  2010-02-20: Simon Goldschmidt
+  * tcp.h, tcp.c, tcp_in.c, tcp_out.c: Task #10088: Correctly implement
+    close() vs. shutdown(). Now the application does not get any more
+    recv callbacks after calling tcp_close(). Added tcp_shutdown().
+
+  2010-02-19: Simon Goldschmidt
+  * mem.c/.h, pbuf.c: Renamed mem_realloc() to mem_trim() to prevent
+    confusion with realloc()
+
+  2010-02-15: Simon Goldschmidt/Stephane Lesage
+  * netif.c/.h: Link status does not depend on LWIP_NETIF_LINK_CALLBACK
+    (fixes bug #28899)
+
+  2010-02-14: Simon Goldschmidt
+  * netif.c: Fixed bug #28877 (Duplicate ARP gratuitous packet with
+    LWIP_NETIF_LINK_CALLBACK set on) by only sending if both link- and
+    admin-status of a netif are up
+
+  2010-02-14: Simon Goldschmidt
+  * opt.h: Disable ETHARP_TRUST_IP_MAC by default since it slows down packet
+    reception and is not really necessary
+
+  2010-02-14: Simon Goldschmidt
+  * etharp.c/.h: Fixed ARP input processing: only add a new entry if a
+    request was directed as us (RFC 826, Packet Reception), otherwise
+    only update existing entries; internalized some functions
+
+  2010-02-14: Simon Goldschmidt
+  * netif.h, etharp.c, tcpip.c: Fixed bug #28183 (ARP and TCP/IP cannot be
+    disabled on netif used for PPPoE) by adding a new netif flag
+    (NETIF_FLAG_ETHERNET) that tells the stack the device is an ethernet
+    device but prevents usage of ARP (so that ethernet_input can be used
+    for PPPoE).
+
+  2010-02-12: Simon Goldschmidt
+  * netif.c: netif_set_link_up/down: only do something if the link state
+    actually changes
+
+  2010-02-12: Simon Goldschmidt/Stephane Lesage
+  * api_msg.c: Fixed bug #28865 (Cannot close socket/netconn in non-blocking
+    connect)
+
+  2010-02-12: Simon Goldschmidt
+  * mem.h: Fixed bug #28866 (mem_realloc function defined in mem.h)
+
+  2010-02-09: Simon Goldschmidt
+  * api_lib.c, api_msg.c, sockets.c, api.h, api_msg.h: Fixed bug #22110
+   (recv() makes receive window update for data that wasn't received by
+    application)
+
+  2010-02-09: Simon Goldschmidt/Stephane Lesage
+  * sockets.c: Fixed bug #28853 (lwip_recvfrom() returns 0 on receive time-out
+    or any netconn_recv() error)
+
+  2010-02-09: Simon Goldschmidt
+  * ppp.c: task #10154 (PPP: Update snmp in/out counters for tx/rx packets)
+
+  2010-02-09: Simon Goldschmidt
+  * netif.c: For loopback packets, adjust the stats- and snmp-counters
+    for the loopback netif.
+
+  2010-02-08: Simon Goldschmidt
+  * igmp.c/.h, ip.h: Moved most defines from igmp.h to igmp.c for clarity
+    since they are not used anywhere else.
+
+  2010-02-08: Simon Goldschmidt (Stéphane Lesage)
+  * igmp.c, igmp.h, stats.c, stats.h: Improved IGMP stats
+    (patch from bug #28798)
+
+  2010-02-08: Simon Goldschmidt (Stéphane Lesage)
+  * igmp.c: Fixed bug #28798 (Error in "Max Response Time" processing) and
+    another bug when LWIP_RAND() returns zero.
+
+  2010-02-04: Simon Goldschmidt
+  * nearly every file: Use macros defined in ip_addr.h (some of them new)
+    to work with IP addresses (preparation for bug #27352 - Change ip_addr
+    from struct to typedef (u32_t) - and better code).
+
+  2010-01-31: Simon Goldschmidt
+  * netif.c: Don't call the link-callback from netif_set_up/down() since
+    this invalidly retriggers DHCP.
+
+  2010-01-29: Simon Goldschmidt
+  * ip_addr.h, inet.h, def.h, inet.c, def.c, more: Cleanly separate the
+    portability file inet.h and its contents from the stack: moved htonX-
+    functions to def.h (and the new def.c - they are not ipv4 dependent),
+    let inet.h depend on ip_addr.h and not the other way round.
+    This fixes bug #28732.
+
+  2010-01-28: Kieran Mansley
+  * tcp.c: Ensure ssthresh >= 2*MSS
+
+  2010-01-27: Simon Goldschmidt
+  * tcp.h, tcp.c, tcp_in.c: Fixed bug #27871: Calling tcp_abort() in recv
+    callback can lead to accessing unallocated memory. As a consequence,
+    ERR_ABRT means the application has called tcp_abort()!
+
+  2010-01-25: Simon Goldschmidt
+  * snmp_structs.h, msg_in.c: Partly fixed bug #22070 (MIB_OBJECT_WRITE_ONLY
+    not implemented in SNMP): write-only or not-accessible are still
+    returned by getnext (though not by get)
+
+  2010-01-24: Simon Goldschmidt
+  * snmp: Renamed the private mib node from 'private' to 'mib_private' to
+    not use reserved C/C++ keywords
+
+  2010-01-23: Simon Goldschmidt
+  * sockets.c: Fixed bug #28716: select() returns 0 after waiting for less
+    than 1 ms
+
+  2010-01-21: Simon Goldschmidt
+  * tcp.c, api_msg.c: Fixed bug #28651 (tcp_connect: no callbacks called
+    if tcp_enqueue fails) both in raw- and netconn-API
+
+  2010-01-19: Simon Goldschmidt
+  * api_msg.c: Fixed bug #27316: netconn: Possible deadlock in err_tcp
+
+  2010-01-18: Iordan Neshev/Simon Goldschmidt
+  * src/netif/ppp: reorganised PPP sourcecode to 2.3.11 including some
+    bugfix backports from 2.4.x.
+
+  2010-01-18: Simon Goldschmidt
+  * mem.c: Fixed bug #28679: mem_realloc calculates mem_stats wrong
+
+  2010-01-17: Simon Goldschmidt
+  * api_lib.c, api_msg.c, (api_msg.h, api.h, sockets.c, tcpip.c):
+    task #10102: "netconn: clean up conn->err threading issues" by adding
+    error return value to struct api_msg_msg
+
+  2010-01-17: Simon Goldschmidt
+  * api.h, api_lib.c, sockets.c: Changed netconn_recv() and netconn_accept()
+    to return err_t (bugs #27709 and #28087)
+
+  2010-01-14: Simon Goldschmidt
+  * ...: Use typedef for function prototypes throughout the stack.
+
+  2010-01-13: Simon Goldschmidt
+  * api_msg.h/.c, api_lib.c: Fixed bug #26672 (close connection when receive
+    window = 0) by correctly draining recvmbox/acceptmbox
+
+  2010-01-11: Simon Goldschmidt
+  * pap.c: Fixed bug #13315 (PPP PAP authentication can result in
+    erroneous callbacks) by copying the code from recent pppd
+
+  2010-01-10: Simon Goldschmidt
+  * raw.c: Fixed bug #28506 (raw_bind should filter received packets)
+
+  2010-01-10: Simon Goldschmidt
+  * tcp.h/.c: bug #28127 (remove call to tcp_output() from tcp_ack(_now)())
+
+  2010-01-08: Simon Goldschmidt
+  * sockets.c: Fixed bug #28519 (lwip_recvfrom bug with len > 65535)
+
+  2010-01-08: Simon Goldschmidt
+  * dns.c: Copy hostname for DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1 since string
+    passed to dns_local_addhost() might be volatile
+
+  2010-01-07: Simon Goldschmidt
+  * timers.c, tcp.h: Call tcp_timer_needed() with NO_SYS==1, too
+
+  2010-01-06: Simon Goldschmidt
+  * netdb.h: Fixed bug #28496: missing include guards in netdb.h
+
+  2009-12-31: Simon Goldschmidt
+  * many ppp files: Reorganised PPP source code from ucip structure to pppd
+    structure to easily compare our code against the pppd code (around v2.3.1)
+
+  2009-12-27: Simon Goldschmidt
+  * tcp_in.c: Another fix for bug #28241 (ooseq processing) and adapted
+    unit test
+
+
+(STABLE-1.3.2)
+
+  ++ New features:
+
+  2009-10-27 Simon Goldschmidt/Stephan Lesage
+  * netifapi.c/.h: Added netifapi_netif_set_addr()
+
+  2009-10-07 Simon Goldschmidt/Fabian Koch
+  * api_msg.c, netbuf.c/.h, opt.h: patch #6888: Patch for UDP Netbufs to
+    support dest-addr and dest-port (optional: LWIP_NETBUF_RECVINFO)
+
+  2009-08-26 Simon Goldschmidt/Simon Kallweit
+  * slipif.c/.h: bug #26397: SLIP polling support
+
+  2009-08-25 Simon Goldschmidt
+  * opt.h, etharp.h/.c: task #9033: Support IEEE 802.1q tagged frame (VLAN),
+    New configuration options ETHARP_SUPPORT_VLAN and ETHARP_VLAN_CHECK.
+
+  2009-08-25 Simon Goldschmidt
+  * ip_addr.h, netdb.c: patch #6900: added define ip_ntoa(struct ip_addr*)
+
+  2009-08-24 Jakob Stoklund Olesen
+  * autoip.c, dhcp.c, netif.c: patch #6725: Teach AutoIP and DHCP to respond
+    to netif_set_link_up().
+
+  2009-08-23 Simon Goldschmidt
+  * tcp.h/.c: Added function tcp_debug_state_str() to convert a tcp state
+    to a human-readable string.
+
+  ++ Bugfixes:
+
+  2009-12-24: Kieran Mansley
+  * tcp_in.c Apply patches from Oleg Tyshev to improve OOS processing
+    (BUG#28241)
+
+  2009-12-06: Simon Goldschmidt
+  * ppp.h/.c: Fixed bug #27079 (Yet another leak in PPP): outpacket_buf can
+    be statically allocated (like in ucip)
+
+  2009-12-04: Simon Goldschmidt (patch by Ioardan Neshev)
+  * pap.c: patch #6969: PPP: missing PAP authentication UNTIMEOUT
+
+  2009-12-03: Simon Goldschmidt
+  * tcp.h, tcp_in.c, tcp_out.c: Fixed bug #28106: dup ack for fast retransmit
+    could have non-zero length
+
+  2009-12-02: Simon Goldschmidt
+  * tcp_in.c: Fixed bug #27904: TCP sends too many ACKs: delay resetting
+    tcp_input_pcb until after calling the pcb's callbacks
+
+  2009-11-29: Simon Goldschmidt
+  * tcp_in.c: Fixed bug #28054: Two segments with FIN flag on the out-of-
+    sequence queue, also fixed PBUF_POOL leak in the out-of-sequence code
+
+  2009-11-29: Simon Goldschmidt
+  * pbuf.c: Fixed bug #28064: pbuf_alloc(PBUF_POOL) is not thread-safe by
+    queueing a call into tcpip_thread to free ooseq-bufs if the pool is empty
+
+  2009-11-26: Simon Goldschmidt
+  * tcp.h: Fixed bug #28098: Nagle can prevent fast retransmit from sending
+    segment
+
+  2009-11-26: Simon Goldschmidt
+  * tcp.h, sockets.c: Fixed bug #28099: API required to disable Nagle
+    algorithm at PCB level
+
+  2009-11-22: Simon Goldschmidt
+  * tcp_out.c: Fixed bug #27905: FIN isn't combined with data on unsent
+
+  2009-11-22: Simon Goldschmidt (suggested by Bill Auerbach)
+  * tcp.c: tcp_alloc: prevent increasing stats.err for MEMP_TCP_PCB when
+    reusing time-wait pcb
+
+  2009-11-20: Simon Goldschmidt (patch by Albert Bartel)
+  * sockets.c: Fixed bug #28062: Data received directly after accepting
+    does not wake up select
+
+  2009-11-11: Simon Goldschmidt
+  * netdb.h: Fixed bug #27994: incorrect define for freeaddrinfo(addrinfo)
+
+  2009-10-30: Simon Goldschmidt
+  * opt.h: Increased default value for TCP_MSS to 536, updated default
+    value for TCP_WND to 4*TCP_MSS to keep delayed ACK working.
+
+  2009-10-28: Kieran Mansley
+  * tcp_in.c, tcp_out.c, tcp.h: re-work the fast retransmission code
+    to follow algorithm from TCP/IP Illustrated
+
+  2009-10-27: Kieran Mansley
+  * tcp_in.c: fix BUG#27445: grow cwnd with every duplicate ACK
+
+  2009-10-25: Simon Goldschmidt
+  * tcp.h: bug-fix in the TCP_EVENT_RECV macro (has to call tcp_recved if
+    pcb->recv is NULL to keep rcv_wnd correct)
+
+  2009-10-25: Simon Goldschmidt
+  * tcp_in.c: Fixed bug #26251: RST process in TIME_WAIT TCP state
+
+  2009-10-23: Simon Goldschmidt (David Empson)
+  * tcp.c: Fixed bug #27783: Silly window avoidance for small window sizes
+
+  2009-10-21: Simon Goldschmidt
+  * tcp_in.c: Fixed bug #27215: TCP sent() callback gives leading and
+    trailing 1 byte len (SYN/FIN)
+
+  2009-10-21: Simon Goldschmidt
+  * tcp_out.c: Fixed bug #27315: zero window probe and FIN
+
+  2009-10-19: Simon Goldschmidt
+  * dhcp.c/.h: Minor code simplification (don't store received pbuf, change
+    conditional code to assert where applicable), check pbuf length before
+    testing for valid reply
+
+  2009-10-19: Simon Goldschmidt
+  * dhcp.c: Removed most calls to udp_connect since they aren't necessary
+    when using udp_sendto_if() - always stay connected to IP_ADDR_ANY.
+
+  2009-10-16: Simon Goldschmidt
+  * ip.c: Fixed bug #27390: Source IP check in ip_input() causes it to drop
+    valid DHCP packets -> allow 0.0.0.0 as source address when LWIP_DHCP is
+    enabled
+
+  2009-10-15: Simon Goldschmidt (Oleg Tyshev)
+  * tcp_in.c: Fixed bug #27329: dupacks by unidirectional data transmit
+
+  2009-10-15: Simon Goldschmidt
+  * api_lib.c: Fixed bug #27709: conn->err race condition on netconn_recv()
+    timeout
+
+  2009-10-15: Simon Goldschmidt
+  * autoip.c: Fixed bug #27704: autoip starts with wrong address
+    LWIP_AUTOIP_CREATE_SEED_ADDR() returned address in host byte order instead
+    of network byte order
+
+  2009-10-11 Simon Goldschmidt (Jörg Kesten)
+  * tcp_out.c: Fixed bug #27504: tcp_enqueue wrongly concatenates segments
+    which are not consecutive when retransmitting unacked segments
+
+  2009-10-09 Simon Goldschmidt
+  * opt.h: Fixed default values of some stats to only be enabled if used
+    Fixes bug #27338: sys_stats is defined when NO_SYS = 1
+
+  2009-08-30 Simon Goldschmidt
+  * ip.c: Fixed bug bug #27345: "ip_frag() does not use the LWIP_NETIF_LOOPBACK
+    function" by checking for loopback before calling ip_frag
+
+  2009-08-25 Simon Goldschmidt
+  * dhcp.c: fixed invalid dependency to etharp_query if DHCP_DOES_ARP_CHECK==0
+
+  2009-08-23 Simon Goldschmidt
+  * ppp.c: bug #27078: Possible memory leak in pppInit()
+
+  2009-08-23 Simon Goldschmidt
+  * netdb.c, dns.c: bug #26657: DNS, if host name is "localhost", result
+    is error.
+
+  2009-08-23 Simon Goldschmidt
+  * opt.h, init.c: bug #26649: TCP fails when TCP_MSS > TCP_SND_BUF
+    Fixed wrong parenthesis, added check in init.c
+
+  2009-08-23 Simon Goldschmidt
+  * ppp.c: bug #27266: wait-state debug message in pppMain occurs every ms
+
+  2009-08-23 Simon Goldschmidt
+  * many ppp files: bug #27267: Added include to string.h where needed
+
+  2009-08-23 Simon Goldschmidt
+  * tcp.h: patch #6843: tcp.h macro optimization patch (for little endian)
+
+
+(STABLE-1.3.1)
+
+  ++ New features:
+
+  2009-05-10 Simon Goldschmidt
+  * opt.h, sockets.c, pbuf.c, netbuf.h, pbuf.h: task #7013: Added option
+    LWIP_NETIF_TX_SINGLE_PBUF to try to create transmit packets from only
+    one pbuf to help MACs that don't support scatter-gather DMA.
+
+  2009-05-09 Simon Goldschmidt
+  * icmp.h, icmp.c: Shrinked ICMP code, added option to NOT check icoming
+    ECHO pbuf for size (just use it): LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN
+
+  2009-05-05 Simon Goldschmidt, Jakob Stoklund Olesen
+  * ip.h, ip.c: Added ip_current_netif() & ip_current_header() to receive
+    extended info about the currently received packet.
+
+  2009-04-27 Simon Goldschmidt
+  * sys.h: Made SYS_LIGHTWEIGHT_PROT and sys_now() work with NO_SYS=1
+
+  2009-04-25 Simon Goldschmidt
+  * mem.c, opt.h: Added option MEM_USE_POOLS_TRY_BIGGER_POOL to try the next
+    bigger malloc pool if one is empty (only usable with MEM_USE_POOLS).
+
+  2009-04-21 Simon Goldschmidt
+  * dns.c, init.c, dns.h, opt.h: task #7507, patch #6786: DNS supports static
+    hosts table. New configuration options DNS_LOCAL_HOSTLIST and
+    DNS_LOCAL_HOSTLIST_IS_DYNAMIC. Also, DNS_LOOKUP_LOCAL_EXTERN() can be defined
+    as an external function for lookup.
+
+  2009-04-15 Simon Goldschmidt
+  * dhcp.c: patch #6763: Global DHCP XID can be redefined to something more unique
+
+  2009-03-31 Kieran Mansley
+  * tcp.c, tcp_out.c, tcp_in.c, sys.h, tcp.h, opts.h: add support for
+    TCP timestamp options, off by default.  Rework tcp_enqueue() to
+    take option flags rather than specified option data
+
+  2009-02-18 Simon Goldschmidt
+  * cc.h: Added printf formatter for size_t: SZT_F
+
+  2009-02-16 Simon Goldschmidt (patch by Rishi Khan)
+  * icmp.c, opt.h: patch #6539: (configurable) response to broadcast- and multicast
+    pings
+
+  2009-02-12 Simon Goldschmidt
+  * init.h: Added LWIP_VERSION to get the current version of the stack
+
+  2009-02-11 Simon Goldschmidt (suggested by Gottfried Spitaler)
+  * opt.h, memp.h/.c: added MEMP_MEM_MALLOC to use mem_malloc/mem_free instead
+    of the pool allocator (can save code size with MEM_LIBC_MALLOC if libc-malloc
+    is otherwise used)
+
+  2009-01-28 Jonathan Larmour (suggested by Bill Bauerbach)
+  * ipv4/inet_chksum.c, ipv4/lwip/inet_chksum.h: inet_chksum_pseudo_partial()
+  is only used by UDPLITE at present, so conditionalise it.
+
+  2008-12-03 Simon Goldschmidt (base on patch from Luca Ceresoli)
+  * autoip.c: checked in (slightly modified) patch #6683: Customizable AUTOIP
+    "seed" address. This should reduce AUTOIP conflicts if
+    LWIP_AUTOIP_CREATE_SEED_ADDR is overridden.
+
+  2008-10-02 Jonathan Larmour and Rishi Khan
+  * sockets.c (lwip_accept): Return EWOULDBLOCK if would block on non-blocking
+    socket.
+
+  2008-06-30 Simon Goldschmidt
+  * mem.c, opt.h, stats.h: fixed bug #21433: Calling mem_free/pbuf_free from
+    interrupt context isn't safe: LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT allows
+    mem_free to run between mem_malloc iterations. Added illegal counter for
+    mem stats.
+
+  2008-06-27 Simon Goldschmidt
+  * stats.h/.c, some other files: patch #6483: stats module improvement:
+    Added defines to display each module's statistic individually, added stats
+    defines for MEM, MEMP and SYS modules, removed (unused) rexmit counter.
+
+  2008-06-17 Simon Goldschmidt
+  * err.h: patch #6459: Made err_t overridable to use a more efficient type
+    (define LWIP_ERR_T in cc.h)
+
+  2008-06-17 Simon Goldschmidt
+  * slipif.c: patch #6480: Added a configuration option for slipif for symmetry
+    to loopif
+
+  2008-06-17 Simon Goldschmidt (patch by Luca Ceresoli)
+  * netif.c, loopif.c, ip.c, netif.h, loopif.h, opt.h: Checked in slightly
+    modified version of patch # 6370: Moved loopif code to netif.c so that
+    loopback traffic is supported on all netifs (all local IPs).
+    Added option to limit loopback packets for each netifs.
+
+
+  ++ Bugfixes:
+  2009-08-12 Kieran Mansley
+  * tcp_in.c, tcp.c: Fix bug #27209: handle trimming of segments when
+    out of window or out of order properly
+
+  2009-08-12 Kieran Mansley
+  * tcp_in.c: Fix bug #27199: use snd_wl2 instead of snd_wl1
+
+  2009-07-28 Simon Goldschmidt
+  * mem.h: Fixed bug #27105: "realloc() cannot replace mem_realloc()"s
+
+  2009-07-27 Kieran Mansley
+  * api.h api_msg.h netdb.h sockets.h: add missing #include directives
+
+  2009-07-09 Kieran Mansley
+  * api_msg.c, sockets.c, api.h: BUG23240 use signed counters for
+    recv_avail and don't increment counters until message successfully
+    sent to mbox
+
+  2009-06-25 Kieran Mansley
+  * api_msg.c api.h: BUG26722: initialise netconn write variables 
+    in netconn_alloc
+
+  2009-06-25 Kieran Mansley
+  * tcp.h: BUG26879: set ret value in TCP_EVENT macros when function is not set
+
+  2009-06-25 Kieran Mansley
+  * tcp.c, tcp_in.c, tcp_out.c, tcp.h: BUG26301 and BUG26267: correct
+    simultaneous close behaviour, and make snd_nxt have the same meaning 
+    as in the RFCs.
+
+  2009-05-12 Simon Goldschmidt
+  * etharp.h, etharp.c, netif.c: fixed bug #26507: "Gratuitous ARP depends on
+    arp_table / uses etharp_query" by adding etharp_gratuitous()
+
+  2009-05-12 Simon Goldschmidt
+  * ip.h, ip.c, igmp.c: bug #26487: Added ip_output_if_opt that can add IP options
+    to the IP header (used by igmp_ip_output_if)
+
+  2009-05-06 Simon Goldschmidt
+  * inet_chksum.c: On little endian architectures, use LWIP_PLATFORM_HTONS (if
+    defined) for SWAP_BYTES_IN_WORD to speed up checksumming.
+
+  2009-05-05 Simon Goldschmidt
+  * sockets.c: bug #26405: Prematurely released semaphore causes lwip_select()
+    to crash
+
+  2009-05-04 Simon Goldschmidt
+  * init.c: snmp was not initialized in lwip_init()
+
+  2009-05-04 Frédéric Bernon
+  * dhcp.c, netbios.c: Changes if IP_SOF_BROADCAST is enabled.
+
+  2009-05-03 Simon Goldschmidt
+  * tcp.h: bug #26349: Nagle algorithm doesn't send although segment is full
+    (and unsent->next == NULL)
+
+  2009-05-02 Simon Goldschmidt
+  * tcpip.h, tcpip.c: fixed tcpip_untimeout (does not need the time, broken after
+    1.3.0 in CVS only) - fixes compilation of ppp_oe.c
+
+  2009-05-02 Simon Goldschmidt
+  * msg_in.c: fixed bug #25636: SNMPSET value is ignored for integer fields
+
+  2009-05-01 Simon Goldschmidt
+  * pap.c: bug #21680: PPP upap_rauthnak() drops legal NAK packets
+
+  2009-05-01 Simon Goldschmidt
+  * ppp.c: bug #24228: Memory corruption with PPP and DHCP
+
+  2009-04-29 Frédéric Bernon
+  * raw.c, udp.c, init.c, opt.h, ip.h, sockets.h: bug #26309: Implement the
+    SO(F)_BROADCAST filter for all API layers. Avoid the unindented reception
+    of broadcast packets even when this option wasn't set. Port maintainers
+    which want to enable this filter have to set IP_SOF_BROADCAST=1 in opt.h.
+    If you want this option also filter broadcast on recv operations, you also
+    have to set IP_SOF_BROADCAST_RECV=1 in opt.h.
+
+  2009-04-28 Simon Goldschmidt, Jakob Stoklund Olesen
+  * dhcp.c: patch #6721, bugs #25575, #25576: Some small fixes to DHCP and
+    DHCP/AUTOIP cooperation
+
+  2009-04-25 Simon Goldschmidt, Oleg Tyshev
+  * tcp_out.c: bug #24212: Deadlocked tcp_retransmit due to exceeded pcb->cwnd
+    Fixed by sorting the unsent and unacked queues (segments are inserted at the
+    right place in tcp_output and tcp_rexmit).
+
+  2009-04-25 Simon Goldschmidt
+  * memp.c, mem.c, memp.h, mem_std.h: bug #26213 "Problem with memory allocation
+    when debugging": memp_sizes contained the wrong sizes (including sanity
+    regions); memp pools for MEM_USE_POOLS were too small
+
+  2009-04-24 Simon Goldschmidt, Frédéric Bernon
+  * inet.c: patch #6765: Fix a small problem with the last changes (incorrect
+    behavior, with with ip address string not ended by a '\0', a space or a
+    end of line)
+
+  2009-04-19 Simon Goldschmidt
+  * rawapi.txt: Fixed bug #26069: Corrected documentation: if tcp_connect fails,
+    pcb->err is called, not pcb->connected (with an error code).
+
+  2009-04-19 Simon Goldschmidt
+  * tcp_out.c: Fixed bug #26236: "TCP options (timestamp) don't work with
+    no-copy-tcpwrite": deallocate option data, only concat segments with same flags
+
+  2009-04-19 Simon Goldschmidt
+  * tcp_out.c: Fixed bug #25094: "Zero-length pbuf" (options are now allocated
+    in the header pbuf, not the data pbuf)
+
+  2009-04-18 Simon Goldschmidt
+  * api_msg.c: fixed bug #25695: Segmentation fault in do_writemore()
+
+  2009-04-15 Simon Goldschmidt
+  * sockets.c: tried to fix bug #23559: lwip_recvfrom problem with tcp
+
+  2009-04-15 Simon Goldschmidt
+  * dhcp.c: task #9192: mem_free of dhcp->options_in and dhcp->msg_in
+
+  2009-04-15 Simon Goldschmidt
+  * ip.c, ip6.c, tcp_out.c, ip.h: patch #6808: Add a utility function
+    ip_hinted_output() (for smaller code mainly)
+
+  2009-04-15 Simon Goldschmidt
+  * inet.c: patch #6765: Supporting new line characters in inet_aton()
+
+  2009-04-15 Simon Goldschmidt
+  * dhcp.c: patch #6764: DHCP rebind and renew did not send hostnam option;
+    Converted constant OPTION_MAX_MSG_SIZE to netif->mtu, check if netif->mtu
+    is big enough in dhcp_start
+
+  2009-04-15 Simon Goldschmidt
+  * netbuf.c: bug #26027: netbuf_chain resulted in pbuf memory leak
+
+  2009-04-15 Simon Goldschmidt
+  * sockets.c, ppp.c: bug #25763: corrected 4 occurrences of SMEMCPY to MEMCPY
+
+  2009-04-15 Simon Goldschmidt
+  * sockets.c: bug #26121: set_errno can be overridden
+
+  2009-04-09 Kieran Mansley (patch from Luca Ceresoli )
+  * init.c, opt.h: Patch#6774 TCP_QUEUE_OOSEQ breaks compilation when
+    LWIP_TCP==0
+
+  2009-04-09 Kieran Mansley (patch from Roy Lee )
+  * tcp.h: Patch#6802 Add do-while-clauses to those function like
+    macros in tcp.h
+
+  2009-03-31 Kieran Mansley
+  * tcp.c, tcp_in.c, tcp_out.c, tcp.h, opt.h: Rework the way window
+    updates are calculated and sent (BUG20515)
+
+  * tcp_in.c: cope with SYN packets received during established states,
+    and retransmission of initial SYN.
+
+  * tcp_out.c: set push bit correctly when tcp segments are merged
+
+  2009-03-27 Kieran Mansley
+  * tcp_out.c set window correctly on probes (correcting change made
+    yesterday)
+
+  2009-03-26 Kieran Mansley
+  * tcp.c, tcp_in.c, tcp.h: add tcp_abandon() to cope with dropping
+    connections where no reset required (bug #25622)
+
+  * tcp_out.c: set TCP_ACK flag on keepalive and zero window probes 
+    (bug #20779)
+
+  2009-02-18 Simon Goldschmidt (Jonathan Larmour and Bill Auerbach)
+  * ip_frag.c: patch #6528: the buffer used for IP_FRAG_USES_STATIC_BUF could be
+    too small depending on MEM_ALIGNMENT
+
+  2009-02-16 Simon Goldschmidt
+  * sockets.h/.c, api_*.h/.c: fixed arguments of socket functions to match the standard;
+    converted size argument of netconn_write to 'size_t'
+
+  2009-02-16 Simon Goldschmidt
+  * tcp.h, tcp.c: fixed bug #24440: TCP connection close problem on 64-bit host
+    by moving accept callback function pointer to TCP_PCB_COMMON
+
+  2009-02-12 Simon Goldschmidt
+  * dhcp.c: fixed bug #25345 (DHCPDECLINE is sent with "Maximum message size"
+    option)
+
+  2009-02-11 Simon Goldschmidt
+  * dhcp.c: fixed bug #24480 (releasing old udp_pdb and pbuf in dhcp_start)
+
+  2009-02-11 Simon Goldschmidt
+  * opt.h, api_msg.c: added configurable default valud for netconn->recv_bufsize:
+    RECV_BUFSIZE_DEFAULT (fixes bug #23726: pbuf pool exhaustion on slow recv())
+
+  2009-02-10 Simon Goldschmidt
+  * tcp.c: fixed bug #25467: Listen backlog is not reset on timeout in SYN_RCVD:
+    Accepts_pending is decrease on a corresponding listen pcb when a connection
+    in state SYN_RCVD is close.
+
+  2009-01-28 Jonathan Larmour
+  * pbuf.c: reclaim pbufs from TCP out-of-sequence segments if we run
+    out of pool pbufs.
+
+  2008-12-19 Simon Goldschmidt
+  * many files: patch #6699: fixed some warnings on platform where sizeof(int) == 2 
+
+  2008-12-10 Tamas Somogyi, Frédéric Bernon
+  * sockets.c: fixed bug #25051: lwip_recvfrom problem with udp: fromaddr and
+    port uses deleted netbuf.
+
+  2008-10-18 Simon Goldschmidt
+  * tcp_in.c: fixed bug ##24596: Vulnerability on faulty TCP options length
+    in tcp_parseopt
+
+  2008-10-15 Simon Goldschmidt
+  * ip_frag.c: fixed bug #24517: IP reassembly crashes on unaligned IP headers
+    by packing the struct ip_reass_helper.
+
+  2008-10-03 David Woodhouse, Jonathan Larmour
+  * etharp.c (etharp_arp_input): Fix type aliasing problem copying ip address.
+
+  2008-10-02 Jonathan Larmour
+  * dns.c: Hard-code structure sizes, to avoid issues on some compilers where
+    padding is included.
+
+  2008-09-30 Jonathan Larmour
+  * sockets.c (lwip_accept): check addr isn't NULL. If it's valid, do an
+    assertion check that addrlen isn't NULL.
+
+  2008-09-30 Jonathan Larmour
+  * tcp.c: Fix bug #24227, wrong error message in tcp_bind.
+
+  2008-08-26 Simon Goldschmidt
+  * inet.h, ip_addr.h: fixed bug #24132: Cross-dependency between ip_addr.h and
+    inet.h -> moved declaration of struct in_addr from ip_addr.h to inet.h
+
+  2008-08-14 Simon Goldschmidt
+  * api_msg.c: fixed bug #23847: do_close_internal references freed memory (when
+    tcp_close returns != ERR_OK)
+
+  2008-07-08 Frédéric Bernon
+  * stats.h: Fix some build bugs introduced with patch #6483 (missing some parameters
+    in macros, mainly if MEM_STATS=0 and MEMP_STATS=0).
+
+  2008-06-24 Jonathan Larmour
+  * tcp_in.c: Fix for bug #23693 as suggested by Art R. Ensure cseg is unused
+    if tcp_seg_copy fails.
+
+  2008-06-17 Simon Goldschmidt
+  * inet_chksum.c: Checked in some ideas of patch #6460 (loop optimizations)
+    and created defines for swapping bytes and folding u32 to u16.
+
+  2008-05-30 Kieran Mansley
+  * tcp_in.c Remove redundant "if" statement, and use real rcv_wnd
+    rather than rcv_ann_wnd when deciding if packets are in-window.
+    Contributed by 
+
+  2008-05-30 Kieran Mansley
+  * mem.h: Fix BUG#23254.  Change macro definition of mem_* to allow
+    passing as function pointers when MEM_LIBC_MALLOC is defined.
+
+  2008-05-09 Jonathan Larmour
+  * err.h, err.c, sockets.c: Fix bug #23119: Reorder timeout error code to
+    stop it being treated as a fatal error.
+
+  2008-04-15 Simon Goldschmidt
+  * dhcp.c: fixed bug #22804: dhcp_stop doesn't clear NETIF_FLAG_DHCP
+    (flag now cleared)
+
+  2008-03-27 Simon Goldschmidt
+  * mem.c, tcpip.c, tcpip.h, opt.h: fixed bug #21433 (Calling mem_free/pbuf_free
+    from interrupt context isn't safe): set LWIP_USE_HEAP_FROM_INTERRUPT to 1
+    in lwipopts.h or use pbuf_free_callback(p)/mem_free_callback(m) to free pbufs
+    or heap memory from interrupt context
+
+  2008-03-26 Simon Goldschmidt
+  * tcp_in.c, tcp.c: fixed bug #22249: division by zero could occur if a remote
+    host sent a zero mss as TCP option.
+
+
+(STABLE-1.3.0)
+
+  ++ New features:
+
+  2008-03-10 Jonathan Larmour
+  * inet_chksum.c: Allow choice of one of the sample algorithms to be
+    made from lwipopts.h. Fix comment on how to override LWIP_CHKSUM.
+
+  2008-01-22 Frédéric Bernon
+  * tcp.c, tcp_in.c, tcp.h, opt.h: Rename LWIP_CALCULATE_EFF_SEND_MSS in 
+    TCP_CALCULATE_EFF_SEND_MSS to have coherent TCP options names.
+
+  2008-01-14 Frédéric Bernon
+  * rawapi.txt, api_msg.c, tcp.c, tcp_in.c, tcp.h: changes for task #7675 "Enable
+    to refuse data on a TCP_EVENT_RECV call". Important, behavior changes for the
+    tcp_recv callback (see rawapi.txt).
+
+  2008-01-14 Frédéric Bernon, Marc Chaland
+  * ip.c: Integrate patch #6369" ip_input : checking before realloc".
+  
+  2008-01-12 Frédéric Bernon
+  * tcpip.h, tcpip.c, api.h, api_lib.c, api_msg.c, sockets.c: replace the field
+    netconn::sem per netconn::op_completed like suggested for the task #7490
+    "Add return value to sys_mbox_post".
+
+  2008-01-12 Frédéric Bernon
+  * api_msg.c, opt.h: replace DEFAULT_RECVMBOX_SIZE per DEFAULT_TCP_RECVMBOX_SIZE,
+    DEFAULT_UDP_RECVMBOX_SIZE and DEFAULT_RAW_RECVMBOX_SIZE (to optimize queues
+    sizes), like suggested for the task #7490 "Add return value to sys_mbox_post".
+
+  2008-01-10 Frédéric Bernon
+  * tcpip.h, tcpip.c: add tcpip_callback_with_block function for the task #7490
+    "Add return value to sys_mbox_post". tcpip_callback is always defined as
+    "blocking" ("block" parameter = 1).
+
+  2008-01-10 Frédéric Bernon
+  * tcpip.h, tcpip.c, api.h, api_lib.c, api_msg.c, sockets.c: replace the field
+    netconn::mbox (sys_mbox_t) per netconn::sem (sys_sem_t) for the task #7490
+    "Add return value to sys_mbox_post".
+
+  2008-01-05 Frédéric Bernon
+  * sys_arch.txt, api.h, api_lib.c, api_msg.h, api_msg.c, tcpip.c, sys.h, opt.h:
+    Introduce changes for task #7490 "Add return value to sys_mbox_post" with some
+    modifications in the sys_mbox api: sys_mbox_new take a "size" parameters which
+    indicate the number of pointers query by the mailbox. There is three defines
+    in opt.h to indicate sizes for tcpip::mbox, netconn::recvmbox, and for the 
+    netconn::acceptmbox. Port maintainers, you can decide to just add this new 
+    parameter in your implementation, but to ignore it to keep the previous behavior.
+    The new sys_mbox_trypost function return a value to know if the mailbox is
+    full or if the message is posted. Take a look to sys_arch.txt for more details.
+    This new function is used in tcpip_input (so, can be called in an interrupt
+    context since the function is not blocking), and in recv_udp and recv_raw.
+
+  2008-01-04 Frédéric Bernon, Simon Goldschmidt, Jonathan Larmour
+  * rawapi.txt, api.h, api_lib.c, api_msg.h, api_msg.c, sockets.c, tcp.h, tcp.c,
+    tcp_in.c, init.c, opt.h: rename backlog options with TCP_ prefix, limit the
+    "backlog" parameter in an u8_t, 0 is interpreted as "smallest queue", add
+    documentation in the rawapi.txt file.
+
+  2007-12-31 Kieran Mansley (based on patch from Per-Henrik Lundbolm)
+  * tcp.c, tcp_in.c, tcp_out.c, tcp.h: Add TCP persist timer
+
+  2007-12-31 Frédéric Bernon, Luca Ceresoli
+  * autoip.c, etharp.c: ip_addr.h: Integrate patch #6348: "Broadcast ARP packets
+    in autoip". The change in etharp_raw could be removed, since all calls to
+    etharp_raw use ethbroadcast for the "ethdst_addr" parameter. But it could be
+    wrong in the future.
+
+  2007-12-30 Frédéric Bernon, Tom Evans
+  * ip.c: Fix bug #21846 "LwIP doesn't appear to perform any IP Source Address
+    Filtering" reported by Tom Evans.
+
+  2007-12-21 Frédéric Bernon, Simon Goldschmidt, Jonathan Larmour
+  * tcp.h, opt.h, api.h, api_msg.h, tcp.c, tcp_in.c, api_lib.c, api_msg.c,
+    sockets.c, init.c: task #7252: Implement TCP listen backlog: Warning: raw API
+    applications have to call 'tcp_accepted(pcb)' in their accept callback to
+    keep accepting new connections.
+
+  2007-12-13 Frédéric Bernon
+  * api_msg.c, err.h, err.c, sockets.c, dns.c, dns.h: replace "enum dns_result"
+    by err_t type. Add a new err_t code "ERR_INPROGRESS".
+
+  2007-12-12 Frédéric Bernon
+  * dns.h, dns.c, opt.h: move DNS options to the "right" place. Most visibles
+    are the one which have ram usage.
+
+  2007-12-05 Frédéric Bernon
+  * netdb.c: add a LWIP_DNS_API_HOSTENT_STORAGE option to decide to use a static
+    set of variables (=0) or a local one (=1). In this last case, your port should
+    provide a function "struct hostent* sys_thread_hostent( struct hostent* h)"
+    which have to do a copy of "h" and return a pointer ont the "per-thread" copy.
+
+  2007-12-03 Simon Goldschmidt
+  * ip.c: ip_input: check if a packet is for inp first before checking all other
+    netifs on netif_list (speeds up packet receiving in most cases)
+
+  2007-11-30 Simon Goldschmidt
+  * udp.c, raw.c: task #7497: Sort lists (pcb, netif, ...) for faster access
+    UDP: move a (connected) pcb selected for input to the front of the list of
+    pcbs so that it is found faster next time. Same for RAW pcbs that have eaten
+    a packet.
+
+  2007-11-28 Simon Goldschmidt
+  * etharp.c, stats.c, stats.h, opt.h: Introduced ETHARP_STATS
+
+  2007-11-25 Simon Goldschmidt
+  * dhcp.c: dhcp_unfold_reply() uses pbuf_copy_partial instead of its own copy
+    algorithm.
+
+  2007-11-24 Simon Goldschmidt
+  * netdb.h, netdb.c, sockets.h/.c: Moved lwip_gethostbyname from sockets.c
+    to the new file netdb.c; included lwip_getaddrinfo.
+
+  2007-11-21 Simon Goldschmidt
+  * tcp.h, opt.h, tcp.c, tcp_in.c: implemented calculating the effective send-mss
+    based on the MTU of the netif used to send. Enabled by default. Disable by
+    setting LWIP_CALCULATE_EFF_SEND_MSS to 0. This fixes bug #21492.
+
+  2007-11-19 Frédéric Bernon
+  * api_msg.c, dns.h, dns.c: Implement DNS_DOES_NAME_CHECK option (check if name
+    received match the name query), implement DNS_USES_STATIC_BUF (the place where
+    copy dns payload to parse the response), return an error if there is no place
+    for a new query, and fix some minor problems.
+
+  2007-11-16 Simon Goldschmidt
+  * new files: ipv4/inet.c, ipv4/inet_chksum.c, ipv6/inet6.c
+    removed files: core/inet.c, core/inet6.c
+    Moved inet files into ipv4/ipv6 directory; splitted inet.c/inet.h into
+    inet and chksum part; changed includes in all lwIP files as appropriate
+
+  2007-11-16 Simon Goldschmidt
+  * api.h, api_msg.h, api_lib.c, api_msg.c, socket.h, socket.c: Added sequential
+    dns resolver function for netconn api (netconn_gethostbyname) and socket api
+    (gethostbyname/gethostbyname_r).
+
+  2007-11-15 Jim Pettinato, Frédéric Bernon
+  * opt.h, init.c, tcpip.c, dhcp.c, dns.h, dns.c: add DNS client for simple name
+    requests with RAW api interface. Initialization is done in lwip_init() with
+    build time options. DNS timer is added in tcpip_thread context. DHCP can set
+    DNS server ip addresses when options are received. You need to set LWIP_DNS=1
+    in your lwipopts.h file (LWIP_DNS=0 in opt.h). DNS_DEBUG can be set to get
+    some traces with LWIP_DEBUGF. Sanity check have been added. There is a "todo"
+    list with points to improve.
+
+  2007-11-06 Simon Goldschmidt
+  * opt.h, mib2.c: Patch #6215: added ifAdminStatus write support (if explicitly
+    enabled by defining SNMP_SAFE_REQUESTS to 0); added code to check link status
+    for ifOperStatus if LWIP_NETIF_LINK_CALLBACK is defined.
+
+  2007-11-06 Simon Goldschmidt
+  * api.h, api_msg.h and dependent files: Task #7410: Removed the need to include
+    core header files in api.h (ip/tcp/udp/raw.h) to hide the internal
+    implementation from netconn api applications.
+
+  2007-11-03 Frédéric Bernon
+  * api.h, api_lib.c, api_msg.c, sockets.c, opt.h: add SO_RCVBUF option for UDP &
+    RAW netconn. You need to set LWIP_SO_RCVBUF=1 in your lwipopts.h (it's disabled
+    by default). Netconn API users can use the netconn_recv_bufsize macro to access
+    it. This is a first release which have to be improve for TCP. Note it used the
+    netconn::recv_avail which need to be more "thread-safe" (note there is already
+    the problem for FIONREAD with lwip_ioctl/ioctlsocket).
+
+  2007-11-01 Frédéric Bernon, Marc Chaland
+  * sockets.h, sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c, tcp.h, tcp_out.c:
+    Integrate "patch #6250 : MSG_MORE flag for send". MSG_MORE is used at socket api
+    layer, NETCONN_MORE at netconn api layer, and TCP_WRITE_FLAG_MORE at raw api
+    layer. This option enable to delayed TCP PUSH flag on multiple "write" calls.
+    Note that previous "copy" parameter for "write" APIs is now called "apiflags".
+
+  2007-10-24 Frédéric Bernon
+  * api.h, api_lib.c, api_msg.c: Add macro API_EVENT in the same spirit than 
+    TCP_EVENT_xxx macros to get a code more readable. It could also help to remove
+    some code (like we have talk in "patch #5919 : Create compile switch to remove
+    select code"), but it could be done later.
+
+  2007-10-08 Simon Goldschmidt
+  * many files: Changed initialization: many init functions are not needed any
+    more since we now rely on the compiler initializing global and static
+    variables to zero!
+
+  2007-10-06 Simon Goldschmidt
+  * ip_frag.c, memp.c, mib2.c, ip_frag.h, memp_std.h, opt.h: Changed IP_REASSEMBLY
+    to enqueue the received pbufs so that multiple packets can be reassembled
+    simultaneously and no static reassembly buffer is needed.
+
+  2007-10-05 Simon Goldschmidt
+  * tcpip.c, etharp.h, etharp.c: moved ethernet_input from tcpip.c to etharp.c so
+    all netifs (or ports) can use it.
+
+  2007-10-05 Frédéric Bernon
+  * netifapi.h, netifapi.c: add function netifapi_netif_set_default. Change the 
+    common function to reduce a little bit the footprint (for all functions using
+    only the "netif" parameter).
+
+  2007-10-03 Frédéric Bernon
+  * netifapi.h, netifapi.c: add functions netifapi_netif_set_up, netifapi_netif_set_down,
+    netifapi_autoip_start and netifapi_autoip_stop. Use a common function to reduce
+    a little bit the footprint (for all functions using only the "netif" parameter).
+
+  2007-09-15 Frédéric Bernon
+  * udp.h, udp.c, sockets.c: Changes for "#20503 IGMP Improvement". Add IP_MULTICAST_IF
+    option in socket API, and a new field "multicast_ip" in "struct udp_pcb" (for
+    netconn and raw API users), only if LWIP_IGMP=1. Add getsockopt processing for
+    IP_MULTICAST_TTL and IP_MULTICAST_IF.
+
+  2007-09-10 Frédéric Bernon
+  * snmp.h, mib2.c: enable to remove SNMP timer (which consumne several cycles
+    even when it's not necessary). snmp_agent.txt tell to call snmp_inc_sysuptime()
+    each 10ms (but, it's intrusive if you use sys_timeout feature). Now, you can
+    decide to call snmp_add_sysuptime(100) each 1000ms (which is bigger "step", but
+    call to a lower frequency). Or, you can decide to not call snmp_inc_sysuptime()
+    or snmp_add_sysuptime(), and to define the SNMP_GET_SYSUPTIME(sysuptime) macro.
+    This one is undefined by default in mib2.c. SNMP_GET_SYSUPTIME is called inside
+    snmp_get_sysuptime(u32_t *value), and enable to change "sysuptime" value only
+    when it's queried (any direct call to "sysuptime" is changed by a call to 
+    snmp_get_sysuptime).
+
+  2007-09-09 Frédéric Bernon, Bill Florac
+  * igmp.h, igmp.c, netif.h, netif.c, ip.c: To enable to have interfaces with IGMP,
+    and others without it, there is a new NETIF_FLAG_IGMP flag to set in netif->flags
+    if you want IGMP on an interface. igmp_stop() is now called inside netif_remove().
+    igmp_report_groups() is now called inside netif_set_link_up() (need to have
+    LWIP_NETIF_LINK_CALLBACK=1) to resend reports once the link is up (avoid to wait
+    the next query message to receive the matching multicast streams).
+
+  2007-09-08 Frédéric Bernon
+  * sockets.c, ip.h, api.h, tcp.h: declare a "struct ip_pcb" which only contains
+    IP_PCB. Add in the netconn's "pcb" union a "struct ip_pcb *ip;" (no size change).
+    Use this new field to access to common pcb fields (ttl, tos, so_options, etc...).
+    Enable to access to these fields with LWIP_TCP=0.
+
+  2007-09-05 Frédéric Bernon
+  * udp.c, ipv4/icmp.c, ipv4/ip.c, ipv6/icmp.c, ipv6/ip6.c, ipv4/icmp.h,
+    ipv6/icmp.h, opt.h: Integrate "task #7272 : LWIP_ICMP option". The new option
+    LWIP_ICMP enable/disable ICMP module inside the IP stack (enable per default).
+    Be careful, disabling ICMP make your product non-compliant to RFC1122, but
+    help to reduce footprint, and to reduce "visibility" on the Internet.
+
+  2007-09-05 Frédéric Bernon, Bill Florac
+  * opt.h, sys.h, tcpip.c, slipif.c, ppp.c, sys_arch.txt: Change parameters list
+    for sys_thread_new (see "task #7252 : Create sys_thread_new_ex()"). Two new
+    parameters have to be provided: a task name, and a task stack size. For this
+    one, since it's platform dependant, you could define the best one for you in
+    your lwipopts.h. For port maintainers, you can just add these new parameters
+    in your sys_arch.c file, and but it's not mandatory, use them in your OS
+    specific functions.
+
+  2007-09-05 Frédéric Bernon
+  * inet.c, autoip.c, msg_in.c, msg_out.c, init.c: Move some build time checkings
+    inside init.c for task #7142 "Sanity check user-configurable values".
+
+  2007-09-04 Frédéric Bernon, Bill Florac
+  * igmp.h, igmp.c, memp_std.h, memp.c, init.c, opt.h: Replace mem_malloc call by
+    memp_malloc, and use a new MEMP_NUM_IGMP_GROUP option (see opt.h to define the
+    value). It will avoid potential fragmentation problems, use a counter to know
+    how many times a group is used on an netif, and free it when all applications
+    leave it. MEMP_NUM_IGMP_GROUP got 8 as default value (and init.c got a sanity
+    check if LWIP_IGMP!=0).
+
+  2007-09-03 Frédéric Bernon
+  * igmp.h, igmp.c, sockets.c, api_msg.c: Changes for "#20503 IGMP Improvement".
+    Initialize igmp_mac_filter to NULL in netif_add (this field should be set in
+    the netif's "init" function). Use the "imr_interface" field (for socket layer)
+    and/or the "interface" field (for netconn layer), for join/leave operations.
+    The igmp_join/leavegroup first parameter change from a netif to an ipaddr.
+    This field could be a netif's ipaddr, or "any" (same meaning than ip_addr_isany).
+
+  2007-08-30 Frédéric Bernon
+  * Add netbuf.h, netbuf.c, Change api.h, api_lib.c: #7249 "Split netbuf functions
+    from api/api_lib". Now netbuf API is independant of netconn, and can be used
+    with other API (application based on raw API, or future "socket2" API). Ports
+    maintainers just have to add src/api/netbuf.c in their makefile/projects.
+
+  2007-08-30 Frédéric Bernon, Jonathan Larmour
+  * init.c: Add first version of lwip_sanity_check for task #7142 "Sanity check
+    user-configurable values".
+
+  2007-08-29 Frédéric Bernon
+  * igmp.h, igmp.c, tcpip.c, init.c, netif.c: change igmp_init and add igmp_start.
+    igmp_start is call inside netif_add. Now, igmp initialization is in the same
+    spirit than the others modules. Modify some IGMP debug traces.
+
+  2007-08-29 Frédéric Bernon
+  * Add init.h, init.c, Change opt.h, tcpip.c: Task  #7213 "Add a lwip_init function"
+    Add lwip_init function to regroup all modules initializations, and to provide
+    a place to add code for task #7142 "Sanity check user-configurable values".
+    Ports maintainers should remove direct initializations calls from their code,
+    and add init.c in their makefiles. Note that lwip_init() function is called
+    inside tcpip_init, but can also be used by raw api users since all calls are
+    disabled when matching options are disabled. Also note that their is new options
+    in opt.h, you should configure in your lwipopts.h (they are enabled per default).
+
+  2007-08-26 Marc Boucher
+  * api_msg.c: do_close_internal(): Reset the callbacks and arg (conn) to NULL
+    since they can under certain circumstances be called with an invalid conn
+    pointer after the connection has been closed (and conn has been freed). 
+
+  2007-08-25 Frédéric Bernon (Artem Migaev's Patch)
+  * netif.h, netif.c: Integrate "patch #6163 : Function to check if link layer is up".
+    Add a netif_is_link_up() function if LWIP_NETIF_LINK_CALLBACK option is set.
+
+  2007-08-22 Frédéric Bernon
+  * netif.h, netif.c, opt.h: Rename LWIP_NETIF_CALLBACK in LWIP_NETIF_STATUS_CALLBACK
+    to be coherent with new LWIP_NETIF_LINK_CALLBACK option before next release.
+
+  2007-08-22 Frédéric Bernon
+  * tcpip.h, tcpip.c, ethernetif.c, opt.h: remove options ETHARP_TCPIP_INPUT &
+    ETHARP_TCPIP_ETHINPUT, now, only "ethinput" code is supported, even if the 
+    name is tcpip_input (we keep the name of 1.2.0 function).
+
+  2007-08-17 Jared Grubb
+  * memp_std.h, memp.h, memp.c, mem.c, stats.c: (Task #7136) Centralize mempool 
+    settings into new memp_std.h and optional user file lwippools.h. This adds
+    more dynamic mempools, and allows the user to create an arbitrary number of
+    mempools for mem_malloc.
+
+  2007-08-16 Marc Boucher
+  * api_msg.c: Initialize newconn->state to NETCONN_NONE in accept_function;
+    otherwise it was left to NETCONN_CLOSE and sent_tcp() could prematurely
+    close the connection.
+
+  2007-08-16 Marc Boucher
+  * sockets.c: lwip_accept(): check netconn_peer() error return.
+
+  2007-08-16 Marc Boucher
+  * mem.c, mem.h: Added mem_calloc().
+
+  2007-08-16 Marc Boucher
+  * tcpip.c, tcpip.h memp.c, memp.h: Added distinct memp (MEMP_TCPIP_MSG_INPKT)
+    for input packets to prevent floods from consuming all of MEMP_TCPIP_MSG
+    and starving other message types.
+    Renamed MEMP_TCPIP_MSG to MEMP_TCPIP_MSG_API
+
+  2007-08-16 Marc Boucher
+  * pbuf.c, pbuf.h, etharp.c, tcp_in.c, sockets.c: Split pbuf flags in pbuf
+    type and flgs (later renamed to flags).
+    Use enum pbuf_flag as pbuf_type.  Renumber PBUF_FLAG_*.
+    Improved lwip_recvfrom().  TCP push now propagated.
+
+  2007-08-16 Marc Boucher
+  * ethernetif.c, contrib/ports/various: ethbroadcast now a shared global
+    provided by etharp.
+
+  2007-08-16 Marc Boucher
+  * ppp_oe.c ppp_oe.h, auth.c chap.c fsm.c lcp.c ppp.c ppp.h,
+    etharp.c ethernetif.c, etharp.h, opt.h tcpip.h, tcpip.c:
+    Added PPPoE support and various PPP improvements.
+
+  2007-07-25 Simon Goldschmidt
+  * api_lib.c, ip_frag.c, pbuf.c, api.h, pbuf.h: Introduced pbuf_copy_partial,
+    making netbuf_copy_partial use this function.
+
+  2007-07-25 Simon Goldschmidt
+  * tcp_in.c: Fix bug #20506: Slow start / initial congestion window starts with
+    2 * mss (instead of 1 * mss previously) to comply with some newer RFCs and
+    other stacks.
+
+  2007-07-13 Jared Grubb (integrated by Frédéric Bernon)
+  * opt.h, netif.h, netif.c, ethernetif.c: Add new configuration option to add
+    a link callback in the netif struct, and functions to handle it. Be carefull
+    for port maintainers to add the NETIF_FLAG_LINK_UP flag (like in ethernetif.c)
+    if you want to be sure to be compatible with future changes...
+
+  2007-06-30 Frédéric Bernon
+  * sockets.h, sockets.c: Implement MSG_PEEK flag for recv/recvfrom functions.
+
+  2007-06-21 Simon Goldschmidt
+  * etharp.h, etharp.c: Combined etharp_request with etharp_raw for both
+    LWIP_AUTOIP =0 and =1 to remove redundant code.
+
+  2007-06-21 Simon Goldschmidt
+  * mem.c, memp.c, mem.h, memp.h, opt.h: task #6863: Introduced the option
+    MEM_USE_POOLS to use 4 pools with different sized elements instead of a
+    heap. This both prevents memory fragmentation and gives a higher speed
+    at the cost of more memory consumption. Turned off by default.
+
+  2007-06-21 Simon Goldschmidt
+  * api_lib.c, api_msg.c, api.h, api_msg.h: Converted the length argument of
+    netconn_write (and therefore also api_msg_msg.msg.w.len) from u16_t into
+    int to be able to send a bigger buffer than 64K with one time (mainly
+    used from lwip_send).
+
+  2007-06-21 Simon Goldschmidt
+  * tcp.h, api_msg.c: Moved the nagle algorithm from netconn_write/do_write
+    into a define (tcp_output_nagle) in tcp.h to provide it to raw api users, too.
+
+  2007-06-21 Simon Goldschmidt
+  * api.h, api_lib.c, api_msg.c: Fixed bug #20021: Moved sendbuf-processing in
+    netconn_write from api_lib.c to api_msg.c to also prevent multiple context-
+    changes on low memory or empty send-buffer.
+
+  2007-06-18 Simon Goldschmidt
+  * etharp.c, etharp.h: Changed etharp to use a defined hardware address length
+    of 6 to avoid loading netif->hwaddr_len every time (since this file is only
+    used for ethernet and struct eth_addr already had a defined length of 6).
+
+  2007-06-17 Simon Goldschmidt
+  * sockets.c, sockets.h: Implemented socket options SO_NO_CHECK for UDP sockets
+    to disable UDP checksum generation on transmit.
+
+  2007-06-13 Frédéric Bernon, Simon Goldschmidt
+  * debug.h, api_msg.c: change LWIP_ERROR to use it to check errors like invalid
+    pointers or parameters, and let the possibility to redefined it in cc.h. Use
+    this macro to check "conn" parameter in api_msg.c functions.
+
+  2007-06-11 Simon Goldschmidt
+  * sockets.c, sockets.h: Added UDP lite support for sockets
+
+  2007-06-10 Simon Goldschmidt
+  * udp.h, opt.h, api_msg.c, ip.c, udp.c: Included switch LWIP_UDPLITE (enabled
+    by default) to switch off UDP-Lite support if not needed (reduces udp.c code
+    size)
+
+  2007-06-09 Dominik Spies (integrated by Frédéric Bernon)
+  * autoip.h, autoip.c, dhcp.h, dhcp.c, netif.h, netif.c, etharp.h, etharp.c, opt.h:
+    AutoIP implementation available for IPv4, with new options LWIP_AUTOIP and
+    LWIP_DHCP_AUTOIP_COOP if you want to cooperate with DHCP. Some tips to adapt
+    (see TODO mark in the source code).
+
+  2007-06-09 Simon Goldschmidt
+  * etharp.h, etharp.c, ethernetif.c: Modified order of parameters for
+    etharp_output() to match netif->output so etharp_output() can be used
+    directly as netif->output to save one function call.
+
+  2007-06-08 Simon Goldschmidt
+  * netif.h, ethernetif.c, slipif.c, loopif.c: Added define
+    NETIF_INIT_SNMP(netif, type, speed) to initialize per-netif snmp variables,
+    added initialization of those to ethernetif, slipif and loopif.
+
+  2007-05-18 Simon Goldschmidt
+  * opt.h, ip_frag.c, ip_frag.h, ip.c: Added option IP_FRAG_USES_STATIC_BUF
+    (defaulting to off for now) that can be set to 0 to send fragmented
+    packets by passing PBUF_REFs down the stack.
+
+  2007-05-23 Frédéric Bernon
+  * api_lib.c: Implement SO_RCVTIMEO for accept and recv on TCP
+    connections, such present in patch #5959.
+
+  2007-05-23 Frédéric Bernon
+  * api.h, api_lib.c, api_msg.c, sockets.c: group the different NETCONN_UDPxxx
+    code in only one part...
+
+  2007-05-18 Simon Goldschmidt
+  * opt.h, memp.h, memp.c: Added option MEMP_OVERFLOW_CHECK to check for memp
+    elements to overflow. This is achieved by adding some bytes before and after
+    each pool element (increasing their size, of course), filling them with a
+    prominent value and checking them on freeing the element.
+    Set it to 2 to also check every element in every pool each time memp_malloc()
+    or memp_free() is called (slower but more helpful).
+
+  2007-05-10 Simon Goldschmidt
+  * opt.h, memp.h, memp.c, pbuf.c (see task #6831): use a new memp pool for
+    PBUF_POOL pbufs instead of the old pool implementation in pbuf.c to reduce
+    code size.
+
+  2007-05-11 Frédéric Bernon
+  * sockets.c, api_lib.c, api_msg.h, api_msg.c, netifapi.h, netifapi.c, tcpip.c:
+    Include a function pointer instead of a table index in the message to reduce
+    footprint. Disable some part of lwip_send and lwip_sendto if some options are
+    not set (LWIP_TCP, LWIP_UDP, LWIP_RAW).
+
+  2007-05-10 Simon Goldschmidt
+  * *.h (except netif/ppp/*.h): Included patch #5448: include '#ifdef __cplusplus
+    \ extern "C" {' in all header files. Now you can write your application using
+    the lwIP stack in C++ and simply #include the core files. Note I have left
+    out the netif/ppp/*h header files for now, since I don't know which files are
+    included by applications and which are for internal use only.
+
+  2007-05-09 Simon Goldschmidt
+  * opt.h, *.c/*.h: Included patch #5920: Create define to override C-library
+    memcpy. 2 Defines are created: MEMCPY() for normal memcpy, SMEMCPY() for
+    situations where some compilers might inline the copy and save a function
+    call. Also replaced all calls to memcpy() with calls to (S)MEMCPY().
+
+  2007-05-08 Simon Goldschmidt
+  * mem.h: If MEM_LIBC_MALLOC==1, allow the defines (e.g. mem_malloc() -> malloc())
+    to be overriden in case the C-library malloc implementation is not protected
+    against concurrent access.
+
+  2007-05-04 Simon Goldschmidt (Atte Kojo)
+  * etharp.c: Introduced fast one-entry-cache to speed up ARP lookup when sending
+    multiple packets to the same host.
+
+  2007-05-04 Frédéric Bernon, Jonathan Larmour
+  * sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c: Fix bug #19162 "lwip_sento: a possible
+    to corrupt remote addr/port connection state". Reduce problems "not enought memory" with
+    netbuf (if we receive lot of datagrams). Improve lwip_sendto (only one exchange between
+    sockets api and api_msg which run in tcpip_thread context). Add netconn_sento function.
+    Warning, if you directly access to "fromaddr" & "fromport" field from netbuf struct,
+    these fields are now renamed "addr" & "port".
+
+  2007-04-11 Jonathan Larmour
+  * sys.h, api_lib.c: Provide new sys_mbox_tryfetch function. Require ports to provide new
+    sys_arch_mbox_tryfetch function to get a message if one is there, otherwise return
+    with SYS_MBOX_EMPTY. sys_arch_mbox_tryfetch can be implemented as a function-like macro
+    by the port in sys_arch.h if desired.
+
+  2007-04-06 Frédéric Bernon, Simon Goldschmidt
+  * opt.h, tcpip.h, tcpip.c, netifapi.h, netifapi.c: New configuration option LWIP_NETIF_API
+    allow to use thread-safe functions to add/remove netif in list, and to start/stop dhcp
+    clients, using new functions from netifapi.h. Disable as default (no port change to do).
+
+  2007-04-05 Frédéric Bernon
+  * sockets.c: remplace ENOBUFS errors on alloc_socket by ENFILE to be more BSD compliant.
+
+  2007-04-04 Simon Goldschmidt
+  * arch.h, api_msg.c, dhcp.c, msg_in.c, sockets.c: Introduced #define LWIP_UNUSED_ARG(x)
+    use this for and architecture-independent form to tell the compiler you intentionally
+    are not using this variable. Can be overriden in cc.h.
+
+  2007-03-28 Frédéric Bernon
+  * opt.h, netif.h, dhcp.h, dhcp.c: New configuration option LWIP_NETIF_HOSTNAME allow to
+    define a hostname in netif struct (this is just a pointer, so, you can use a hardcoded
+    string, point on one of your's ethernetif field, or alloc a string you will free yourself).
+    It will be used by DHCP to register a client hostname, but can also be use when you call
+    snmp_set_sysname.
+
+  2007-03-28 Frédéric Bernon
+  * netif.h, netif.c: A new NETIF_FLAG_ETHARP flag is defined in netif.h, to allow to 
+    initialize a network interface's flag with. It tell this interface is an ethernet
+    device, and we can use ARP with it to do a "gratuitous ARP" (RFC 3220 "IP Mobility
+    Support for IPv4" section 4.6) when interface is "up" with netif_set_up().
+
+  2007-03-26 Frédéric Bernon, Jonathan Larmour
+  * opt.h, tcpip.c: New configuration option LWIP_ARP allow to disable ARP init at build
+    time if you only use PPP or SLIP. The default is enable. Note we don't have to call 
+    etharp_init in your port's initilization sequence if you use tcpip.c, because this call
+    is done in tcpip_init function.
+
+  2007-03-22 Frédéric Bernon
+  * stats.h, stats.c, msg_in.c: Stats counters can be change to u32_t if necessary with the
+    new option LWIP_STATS_LARGE. If you need this option, define LWIP_STATS_LARGE to 1 in
+    your lwipopts.h. More, unused counters are not defined in the stats structs, and not 
+    display by stats_display(). Note that some options (SYS_STATS and RAW_STATS) are defined
+    but never used. Fix msg_in.c with the correct #if test for a stat display.
+
+  2007-03-21 Kieran Mansley
+  * netif.c, netif.h: Apply patch#4197 with some changes (originator: rireland@hmgsl.com). 
+    Provides callback on netif up/down state change.
+
+  2007-03-11 Frédéric Bernon, Mace Gael, Steve Reynolds
+  * sockets.h, sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c, igmp.h, igmp.c,
+    ip.c, netif.h, tcpip.c, opt.h:
+    New configuration option LWIP_IGMP to enable IGMP processing. Based on only one 
+    filter per all network interfaces. Declare a new function in netif to enable to
+    control the MAC filter (to reduce lwIP traffic processing).
+
+  2007-03-11 Frédéric Bernon
+  * tcp.h, tcp.c, sockets.c, tcp_out.c, tcp_in.c, opt.h: Keepalive values can
+    be configured at run time with LWIP_TCP_KEEPALIVE, but don't change this
+    unless you know what you're doing (default are RFC1122 compliant). Note
+    that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set in seconds.
+
+  2007-03-08 Frédéric Bernon
+  * tcp.h: Keepalive values can be configured at compile time, but don't change
+    this unless you know what you're doing (default are RFC1122 compliant).
+
+  2007-03-08 Frédéric Bernon
+  * sockets.c, api.h, api_lib.c, tcpip.c, sys.h, sys.c, err.c, opt.h:
+    Implement LWIP_SO_RCVTIMEO configuration option to enable/disable SO_RCVTIMEO
+    on UDP sockets/netconn.
+
+  2007-03-08 Simon Goldschmidt
+  * snmp_msg.h, msg_in.c: SNMP UDP ports can be configured at compile time.
+
+  2007-03-06 Frédéric Bernon
+  * api.h, api_lib.c, sockets.h, sockets.c, tcpip.c, sys.h, sys.c, err.h: 
+    Implement SO_RCVTIMEO on UDP sockets/netconn.
+
+  2007-02-28 Kieran Mansley (based on patch from Simon Goldschmidt)
+  * api_lib.c, tcpip.c, memp.c, memp.h: make API msg structs allocated
+    on the stack and remove the API msg type from memp
+
+  2007-02-26 Jonathan Larmour (based on patch from Simon Goldschmidt)
+  * sockets.h, sockets.c: Move socket initialization to new
+    lwip_socket_init() function.
+    NOTE: this changes the API with ports. Ports will have to be
+    updated to call lwip_socket_init() now.
+
+  2007-02-26 Jonathan Larmour (based on patch from Simon Goldschmidt)
+  * api_lib.c: Use memcpy in netbuf_copy_partial.
+
+
+  ++ Bug fixes:
+
+  2008-03-17 Frédéric Bernon, Ed Kerekes
+  * igmp.h, igmp.c: Fix bug #22613 "IGMP iphdr problem" (could have
+    some problems to fill the IP header on some targets, use now the
+    ip.h macros to do it).
+
+  2008-03-13 Frédéric Bernon
+  * sockets.c: Fix bug #22435 "lwip_recvfrom with TCP break;". Using
+    (lwip_)recvfrom with valid "from" and "fromlen" parameters, on a
+    TCP connection caused a crash. Note that using (lwip_)recvfrom
+    like this is a bit slow and that using (lwip)getpeername is the
+    good lwip way to do it (so, using recv is faster on tcp sockets).
+
+  2008-03-12 Frédéric Bernon, Jonathan Larmour
+  * api_msg.c, contrib/apps/ping.c: Fix bug #22530 "api_msg.c's
+    recv_raw() does not consume data", and the ping sample (with
+    LWIP_SOCKET=1, the code did the wrong supposition that lwip_recvfrom
+    returned the IP payload, without the IP header).
+
+  2008-03-04 Jonathan Larmour
+  * mem.c, stats.c, mem.h: apply patch #6414 to avoid compiler errors
+  and/or warnings on some systems where mem_size_t and size_t differ.
+  * pbuf.c, ppp.c: Fix warnings on some systems with mem_malloc.
+
+  2008-03-04 Kieran Mansley (contributions by others) 
+  * Numerous small compiler error/warning fixes from contributions to
+    mailing list after 1.3.0 release candidate made.
+
+  2008-01-25 Cui hengbin (integrated by Frédéric Bernon)
+  * dns.c: Fix bug #22108 "DNS problem" caused by unaligned structures.
+
+  2008-01-15 Kieran Mansley
+  * tcp_out.c: BUG20511.  Modify persist timer to start when we are
+    prevented from sending by a small send window, not just a zero
+    send window.
+
+  2008-01-09 Jonathan Larmour
+  * opt.h, ip.c: Rename IP_OPTIONS define to IP_OPTIONS_ALLOWED to avoid
+    conflict with Linux system headers.
+
+  2008-01-06 Jonathan Larmour
+  * dhcp.c: fix bug #19927: "DHCP NACK problem" by clearing any existing set IP
+    address entirely on receiving a DHCPNAK, and restarting discovery.
+
+  2007-12-21 Simon Goldschmidt
+  * sys.h, api_lib.c, api_msg.c, sockets.c: fix bug #21698: "netconn->recv_avail
+    is not protected" by using new macros for interlocked access to modify/test
+    netconn->recv_avail.
+
+  2007-12-20 Kieran Mansley (based on patch from Oleg Tyshev)
+  * tcp_in.c: fix bug# 21535 (nrtx not reset correctly in SYN_SENT state)
+
+  2007-12-20 Kieran Mansley (based on patch from Per-Henrik Lundbolm)
+  * tcp.c, tcp_in.c, tcp_out.c, tcp.h: fix bug #20199 (better handling
+    of silly window avoidance and prevent lwIP from shrinking the window)
+
+  2007-12-04 Simon Goldschmidt
+  * tcp.c, tcp_in.c: fix bug #21699 (segment leak in ooseq processing when last
+    data packet was lost): add assert that all segment lists are empty in
+    tcp_pcb_remove before setting pcb to CLOSED state; don't directly set CLOSED
+    state from LAST_ACK in tcp_process
+
+  2007-12-02 Simon Goldschmidt
+  * sockets.h: fix bug #21654: exclude definition of struct timeval from #ifndef FD_SET
+    If including  for system-struct timeval, LWIP_TIMEVAL_PRIVATE now
+    has to be set to 0 in lwipopts.h
+
+  2007-12-02 Simon Goldschmidt
+  * api_msg.c, api_lib.c: fix bug #21656 (recvmbox problem in netconn API): always
+    allocate a recvmbox in netconn_new_with_proto_and_callback. For a tcp-listen
+    netconn, this recvmbox is later freed and a new mbox is allocated for acceptmbox.
+    This is a fix for thread-safety and allocates all items needed for a netconn
+    when the netconn is created.
+
+  2007-11-30 Simon Goldschmidt
+  * udp.c: first attempt to fix bug #21655 (DHCP doesn't work reliably with multiple
+    netifs): if LWIP_DHCP is enabled, UDP packets to DHCP_CLIENT_PORT are passed
+    to netif->dhcp->pcb only (if that exists) and not to any other pcb for the same
+    port (only solution to let UDP pcbs 'bind' to a netif instead of an IP address)
+
+  2007-11-27 Simon Goldschmidt
+  * ip.c: fixed bug #21643 (udp_send/raw_send don't fail if netif is down) by
+    letting ip_route only use netifs that are up.
+
+  2007-11-27 Simon Goldschmidt
+  * err.h, api_lib.c, api_msg.c, sockets.c: Changed error handling: ERR_MEM, ERR_BUF
+    and ERR_RTE are seen as non-fatal, all other errors are fatal. netconns and
+    sockets block most operations once they have seen a fatal error.
+
+  2007-11-27 Simon Goldschmidt
+  * udp.h, udp.c, dhcp.c: Implemented new function udp_sendto_if which takes the
+    netif to send as an argument (to be able to send on netifs that are down).
+
+  2007-11-26 Simon Goldschmidt
+  * tcp_in.c: Fixed bug #21582: pcb->acked accounting can be wrong when ACKs
+    arrive out-of-order
+
+  2007-11-21 Simon Goldschmidt
+  * tcp.h, tcp_out.c, api_msg.c: Fixed bug #20287: tcp_output_nagle sends too early
+    Fixed the nagle algorithm; nagle now also works for all raw API applications
+    and has to be explicitly disabled with 'tcp_pcb->flags |= TF_NODELAY'
+
+  2007-11-12 Frédéric Bernon
+  * sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c: Fixed bug #20900. Now, most
+    of the netconn_peer and netconn_addr processing is done inside tcpip_thread
+    context in do_getaddr.
+
+  2007-11-10 Simon Goldschmidt
+  * etharp.c: Fixed bug: assert fired when MEMP_ARP_QUEUE was empty (which can
+    happen any time). Now the packet simply isn't enqueued when out of memory.
+
+  2007-11-01 Simon Goldschmidt
+  * tcp.c, tcp_in.c: Fixed bug #21494: The send mss (pcb->mss) is set to 536 (or
+    TCP_MSS if that is smaller) as long as no MSS option is received from the
+    remote host.
+
+  2007-11-01 Simon Goldschmidt
+  * tcp.h, tcp.c, tcp_in.c: Fixed bug #21491: The MSS option sent (with SYN)
+    is now based on TCP_MSS instead of pcb->mss (on passive open now effectively
+    sending our configured TCP_MSS instead of the one received).
+
+  2007-11-01 Simon Goldschmidt
+  * tcp_in.c: Fixed bug #21181: On active open, the initial congestion window was
+    calculated based on the configured TCP_MSS, not on the MSS option received
+    with SYN+ACK.
+
+  2007-10-09 Simon Goldschmidt
+  * udp.c, inet.c, inet.h: Fixed UDPLite: send: Checksum was always generated too
+    short and also was generated wrong if checksum coverage != tot_len;
+    receive: checksum was calculated wrong if checksum coverage != tot_len
+
+  2007-10-08 Simon Goldschmidt
+  * mem.c: lfree was not updated in mem_realloc!
+
+  2007-10-07 Frédéric Bernon
+  * sockets.c, api.h, api_lib.c: First step to fix "bug #20900 : Potential
+    crash error problem with netconn_peer & netconn_addr". VERY IMPORTANT:
+    this change cause an API breakage for netconn_addr, since a parameter
+    type change. Any compiler should cause an error without any changes in
+    yours netconn_peer calls (so, it can't be a "silent change"). It also
+    reduce a little bit the footprint for socket layer (lwip_getpeername &
+    lwip_getsockname use now a common lwip_getaddrname function since 
+    netconn_peer & netconn_addr have the same parameters).
+
+  2007-09-20 Simon Goldschmidt
+  * tcp.c: Fixed bug #21080 (tcp_bind without check pcbs in TIME_WAIT state)
+    by checking  tcp_tw_pcbs also
+
+  2007-09-19 Simon Goldschmidt
+  * icmp.c: Fixed bug #21107 (didn't reset IP TTL in ICMP echo replies)
+
+  2007-09-15 Mike Kleshov
+  * mem.c: Fixed bug #21077 (inaccuracy in calculation of lwip_stat.mem.used)
+
+  2007-09-06 Frédéric Bernon
+  * several-files: replace some #include "arch/cc.h" by "lwip/arch.h", or simply remove
+    it as long as "lwip/opt.h" is included before (this one include "lwip/debug.h" which
+    already include "lwip/arch.h"). Like that, default defines are provided by "lwip/arch.h"
+    if they are not defined in cc.h, in the same spirit than "lwip/opt.h" for lwipopts.h.
+
+  2007-08-30 Frédéric Bernon
+  * igmp.h, igmp.c: Some changes to remove some redundant code, add some traces, 
+    and fix some coding style.
+
+  2007-08-28 Frédéric Bernon
+  * tcpip.c: Fix TCPIP_MSG_INPKT processing: now, tcpip_input can be used for any
+    kind of packets. These packets are considered like Ethernet packets (payload 
+    pointing to ethhdr) if the netif got the NETIF_FLAG_ETHARP flag. Else, packets 
+    are considered like IP packets (payload pointing to iphdr).
+
+  2007-08-27 Frédéric Bernon
+  * api.h, api_lib.c, api_msg.c: First fix for "bug #20900 : Potential crash error
+    problem with netconn_peer & netconn_addr". Introduce NETCONN_LISTEN netconn_state
+    and remove obsolete ones (NETCONN_RECV & NETCONN_ACCEPT).
+
+  2007-08-24 Kieran Mansley
+  * inet.c Modify (acc >> 16) test to ((acc >> 16) != 0) to help buggy
+    compiler (Paradigm C++)
+
+  2007-08-09 Frédéric Bernon, Bill Florac
+  * stats.h, stats.c, igmp.h, igmp.c, opt.h: Fix for bug #20503 : IGMP Improvement.
+    Introduce IGMP_STATS to centralize statistics management.
+
+  2007-08-09 Frédéric Bernon, Bill Florac
+  * udp.c: Fix for bug #20503 : IGMP Improvement. Enable to receive a multicast
+    packet on a udp pcb binded on an netif's IP address, and not on "any".
+
+  2007-08-09 Frédéric Bernon, Bill Florac
+  * igmp.h, igmp.c, ip.c: Fix minor changes from bug #20503 : IGMP Improvement.
+    This is mainly on using lookup/lookfor, and some coding styles...
+
+  2007-07-26 Frédéric Bernon (and "thedoctor")
+  * igmp.c: Fix bug #20595 to accept IGMPv3 "Query" messages.
+
+  2007-07-25 Simon Goldschmidt
+  * api_msg.c, tcp.c: Another fix for bug #20021: by not returning an error if
+    tcp_output fails in tcp_close, the code in do_close_internal gets simpler
+    (tcp_output is called again later from tcp timers).
+
+  2007-07-25 Simon Goldschmidt
+  * ip_frag.c: Fixed bug #20429: use the new pbuf_copy_partial instead of the old
+    copy_from_pbuf, which illegally modified the given pbuf.
+
+  2007-07-25 Simon Goldschmidt
+  * tcp_out.c: tcp_enqueue: pcb->snd_queuelen didn't work for chaine PBUF_RAMs:
+    changed snd_queuelen++ to snd_queuelen += pbuf_clen(p).
+
+  2007-07-24 Simon Goldschmidt
+  * api_msg.c, tcp.c: Fix bug #20480: Check the pcb passed to tcp_listen() for the
+    correct state (must be CLOSED).
+
+  2007-07-13 Thomas Taranowski (commited by Jared Grubb)
+  * memp.c: Fix bug #20478: memp_malloc returned NULL+MEMP_SIZE on failed
+    allocation. It now returns NULL.
+
+  2007-07-13 Frédéric Bernon
+  * api_msg.c: Fix bug #20318: api_msg "recv" callbacks don't call pbuf_free in
+    all error cases.
+
+  2007-07-13 Frédéric Bernon
+  * api_msg.c: Fix bug #20315: possible memory leak problem if tcp_listen failed,
+    because current code doesn't follow rawapi.txt documentation.
+
+  2007-07-13 Kieran Mansley
+  * src/core/tcp_in.c Apply patch#5741 from Oleg Tyshev to fix bug in
+    out of sequence processing of received packets
+
+  2007-07-03 Simon Goldschmidt
+  * nearly-all-files: Added assertions where PBUF_RAM pbufs are used and an
+    assumption is made that this pbuf is in one piece (i.e. not chained). These
+    assumptions clash with the possibility of converting to fully pool-based
+    pbuf implementations, where PBUF_RAM pbufs might be chained.
+
+  2007-07-03 Simon Goldschmidt
+  * api.h, api_lib.c, api_msg.c: Final fix for bug #20021 and some other problems
+    when closing tcp netconns: removed conn->sem, less context switches when
+    closing, both netconn_close and netconn_delete should safely close tcp
+    connections.
+
+  2007-07-02 Simon Goldschmidt
+  * ipv4/ip.h, ipv6/ip.h, opt.h, netif.h, etharp.h, ipv4/ip.c, netif.c, raw.c,
+    tcp_out.c, udp.c, etharp.c: Added option LWIP_NETIF_HWADDRHINT (default=off)
+    to cache ARP table indices with each pcb instead of single-entry cache for
+    the complete stack.
+
+  2007-07-02 Simon Goldschmidt
+  * tcp.h, tcp.c, tcp_in.c, tcp_out.c: Added some ASSERTS and casts to prevent
+    warnings when assigning to smaller types.
+
+  2007-06-28 Simon Goldschmidt
+  * tcp_out.c: Added check to prevent tcp_pcb->snd_queuelen from overflowing.
+
+  2007-06-28 Simon Goldschmidt
+  * tcp.h: Fixed bug #20287: Fixed nagle algorithm (sending was done too early if
+    a segment contained chained pbufs)
+
+  2007-06-28 Frédéric Bernon
+  * autoip.c: replace most of rand() calls by a macro LWIP_AUTOIP_RAND which compute
+    a "pseudo-random" value based on netif's MAC and some autoip fields. It's always
+    possible to define this macro in your own lwipopts.h to always use C library's
+    rand(). Note that autoip_create_rand_addr doesn't use this macro.
+
+  2007-06-28 Frédéric Bernon
+  * netifapi.h, netifapi.c, tcpip.h, tcpip.c: Update code to handle the option
+    LWIP_TCPIP_CORE_LOCKING, and do some changes to be coherent with last modifications
+    in api_lib/api_msg (use pointers and not type with table, etc...) 
+
+  2007-06-26 Simon Goldschmidt
+  * udp.h: Fixed bug #20259: struct udp_hdr was lacking the packin defines.
+
+  2007-06-25 Simon Goldschmidt
+  * udp.c: Fixed bug #20253: icmp_dest_unreach was called with a wrong p->payload
+    for udp packets with no matching pcb.
+
+  2007-06-25 Simon Goldschmidt
+  * udp.c: Fixed bug #20220: UDP PCB search in udp_input(): a non-local match
+    could get udp input packets if the remote side matched.
+
+  2007-06-13 Simon Goldschmidt
+  * netif.c: Fixed bug #20180 (TCP pcbs listening on IP_ADDR_ANY could get
+    changed in netif_set_ipaddr if previous netif->ip_addr.addr was 0.
+
+  2007-06-13 Simon Goldschmidt
+  * api_msg.c: pcb_new sets conn->err if protocol is not implemented
+    -> netconn_new_..() does not allocate a new connection for unsupported
+    protocols.
+
+  2007-06-13 Frédéric Bernon, Simon Goldschmidt
+  * api_lib.c: change return expression in netconn_addr and netconn_peer, because
+    conn->err was reset to ERR_OK without any reasons (and error was lost)...
+
+  2007-06-13 Frédéric Bernon, Matthias Weisser
+  * opt.h, mem.h, mem.c, memp.c, pbuf.c, ip_frag.c, vj.c: Fix bug #20162. Rename
+    MEM_ALIGN in LWIP_MEM_ALIGN and MEM_ALIGN_SIZE in LWIP_MEM_ALIGN_SIZE to avoid
+    some macro names collision with some OS macros.
+
+  2007-06-11 Simon Goldschmidt
+  * udp.c: UDP Lite: corrected the use of chksum_len (based on RFC3828: if it's 0,
+    create checksum over the complete packet. On RX, if it's < 8 (and not 0),
+    discard the packet. Also removed the duplicate 'udphdr->chksum = 0' for both
+    UDP & UDP Lite.
+
+  2007-06-11 Srinivas Gollakota & Oleg Tyshev
+  * tcp_out.c: Fix for bug #20075 : "A problem with keep-alive timer and TCP flags"
+    where TCP flags wasn't initialized in tcp_keepalive.
+
+  2007-06-03 Simon Goldschmidt
+  * udp.c: udp_input(): Input pbuf was not freed if pcb had no recv function
+    registered, p->payload was modified without modifying p->len if sending
+    icmp_dest_unreach() (had no negative effect but was definitively wrong).
+
+  2007-06-03 Simon Goldschmidt
+  * icmp.c: Corrected bug #19937: For responding to an icmp echo request, icmp
+    re-used the input pbuf even if that didn't have enough space to include the
+    link headers. Now the space is tested and a new pbuf is allocated for the
+    echo response packet if the echo request pbuf isn't big enough.
+
+  2007-06-01 Simon Goldschmidt
+  * sockets.c: Checked in patch #5914: Moved sockopt processing into tcpip_thread.
+
+  2007-05-23 Frédéric Bernon
+  * api_lib.c, sockets.c: Fixed bug #5958 for netconn_listen (acceptmbox only
+    allocated by do_listen if success) and netconn_accept errors handling. In
+    most of api_lib functions, we replace some errors checkings like "if (conn==NULL)"
+    by ASSERT, except for netconn_delete.
+
+  2007-05-23 Frédéric Bernon
+  * api_lib.c: Fixed bug #5957 "Safe-thread problem inside netconn_recv" to return
+    an error code if it's impossible to fetch a pbuf on a TCP connection (and not
+    directly close the recvmbox).
+
+  2007-05-22 Simon Goldschmidt
+  * tcp.c: Fixed bug #1895 (tcp_bind not correct) by introducing a list of
+    bound but unconnected (and non-listening) tcp_pcbs.
+
+  2007-05-22 Frédéric Bernon
+  * sys.h, sys.c, api_lib.c, tcpip.c: remove sys_mbox_fetch_timeout() (was only
+    used for LWIP_SO_RCVTIMEO option) and use sys_arch_mbox_fetch() instead of
+    sys_mbox_fetch() in api files. Now, users SHOULD NOT use internal lwIP features
+    like "sys_timeout" in their application threads.
+
+  2007-05-22 Frédéric Bernon
+  * api.h, api_lib.c, api_msg.h, api_msg.c: change the struct api_msg_msg to see
+    which parameters are used by which do_xxx function, and to avoid "misusing"
+    parameters (patch #5938).
+
+  2007-05-22 Simon Goldschmidt
+  * api_lib.c, api_msg.c, raw.c, api.h, api_msg.h, raw.h: Included patch #5938:
+    changed raw_pcb.protocol from u16_t to u8_t since for IPv4 and IPv6, proto
+    is only 8 bits wide. This affects the api, as there, the protocol was
+    u16_t, too.
+
+  2007-05-18 Simon Goldschmidt
+  * memp.c: addition to patch #5913: smaller pointer was returned but
+    memp_memory was the same size -> did not save memory.
+
+  2007-05-16 Simon Goldschmidt
+  * loopif.c, slipif.c: Fix bug #19729: free pbuf if netif->input() returns
+    != ERR_OK.
+
+  2007-05-16 Simon Goldschmidt
+  * api_msg.c, udp.c: If a udp_pcb has a local_ip set, check if it is the same
+    as the one of the netif used for sending to prevent sending from old
+    addresses after a netif address gets changed (partly fixes bug #3168).
+
+  2007-05-16 Frédéric Bernon
+  * tcpip.c, igmp.h, igmp.c: Fixed bug "#19800 : IGMP: igmp_tick() will not work
+    with NO_SYS=1". Note that igmp_init is always in tcpip_thread (and not in 
+    tcpip_init) because we have to be sure that network interfaces are already
+    added (mac filter is updated only in igmp_init for the moment).
+
+  2007-05-16 Simon Goldschmidt
+  * mem.c, memp.c: Removed semaphores from memp, changed sys_sem_wait calls
+    into sys_arch_sem_wait calls to prevent timers from running while waiting
+    for the heap. This fixes bug #19167.
+
+  2007-05-13 Simon Goldschmidt
+  * tcp.h, sockets.h, sockets.c: Fixed bug from patch #5865 by moving the defines
+    for socket options (lwip_set/-getsockopt) used with level IPPROTO_TCP from
+    tcp.h to sockets.h.
+
+  2007-05-07 Simon Goldschmidt
+  * mem.c: Another attempt to fix bug #17922.
+
+  2007-05-04 Simon Goldschmidt
+  * pbuf.c, pbuf.h, etharp.c: Further update to ARP queueing: Changed pbuf_copy()
+    implementation so that it can be reused (don't allocate the target
+    pbuf inside pbuf_copy()).
+
+  2007-05-04 Simon Goldschmidt
+  * memp.c: checked in patch #5913: in memp_malloc() we can return memp as mem
+    to save a little RAM (next pointer of memp is not used while not in pool).
+
+  2007-05-03 "maq"
+  * sockets.c: Fix ioctl FIONREAD when some data remains from last recv.
+    (patch #3574).
+
+  2007-04-23 Simon Goldschmidt
+  * loopif.c, loopif.h, opt.h, src/netif/FILES: fix bug #2595: "loopif results
+    in NULL reference for incoming TCP packets". Loopif has to be configured
+    (using LWIP_LOOPIF_MULTITHREADING) to directly call netif->input()
+    (multithreading environments, e.g. netif->input() = tcpip_input()) or
+    putting packets on a list that is fed to the stack by calling loopif_poll()
+    (single-thread / NO_SYS / polling environment where e.g.
+    netif->input() = ip_input).
+
+  2007-04-17 Jonathan Larmour
+  * pbuf.c: Use s32_t in pbuf_realloc(), as an s16_t can't reliably hold
+    the difference between two u16_t's.
+  * sockets.h: FD_SETSIZE needs to match number of sockets, which is
+    MEMP_NUM_NETCONN in sockets.c right now.
+
+  2007-04-12 Jonathan Larmour
+  * icmp.c: Reset IP header TTL in ICMP ECHO responses (bug #19580).
+
+  2007-04-12 Kieran Mansley
+  * tcp.c, tcp_in.c, tcp_out.c, tcp.h: Modify way the retransmission
+    timer is reset to fix bug#19434, with help from Oleg Tyshev.
+
+  2007-04-11 Simon Goldschmidt
+  * etharp.c, pbuf.c, pbuf.h: 3rd fix for bug #11400 (arp-queuing): More pbufs than
+    previously thought need to be copied (everything but PBUF_ROM!). Cleaned up
+    pbuf.c: removed functions no needed any more (by etharp).
+
+  2007-04-11 Kieran Mansley
+  * inet.c, ip_addr.h, sockets.h, sys.h, tcp.h: Apply patch #5745: Fix
+    "Constant is long" warnings with 16bit compilers.  Contributed by
+    avatar@mmlab.cse.yzu.edu.tw
+
+  2007-04-05 Frédéric Bernon, Jonathan Larmour
+  * api_msg.c: Fix bug #16830: "err_tcp() posts to connection mailbox when no pend on
+    the mailbox is active". Now, the post is only done during a connect, and do_send,
+    do_write and do_join_leave_group don't do anything if a previous error was signaled.
+
+  2007-04-03 Frédéric Bernon
+  * ip.c: Don't set the IP_DF ("Don't fragment") flag in the IP header in IP output
+    packets. See patch #5834.
+
+  2007-03-30 Frédéric Bernon
+  * api_msg.c: add a "pcb_new" helper function to avoid redundant code, and to add
+    missing  pcb allocations checking (in do_bind, and for each raw_new). Fix style.
+
+  2007-03-30 Frédéric Bernon
+  * most of files: prefix all debug.h define with "LWIP_" to avoid any conflict with
+    others environment defines (these were too "generic").
+
+  2007-03-28 Frédéric Bernon
+  * api.h, api_lib.c, sockets.c: netbuf_ref doesn't check its internal pbuf_alloc call
+    result and can cause a crash. lwip_send now check netbuf_ref result.
+
+  2007-03-28 Simon Goldschmidt
+  * sockets.c Remove "#include " from sockets.c to avoid multiple
+    definition of macros (in errno.h and lwip/arch.h) if LWIP_PROVIDE_ERRNO is
+    defined. This is the way it should have been already (looking at
+    doc/sys_arch.txt)
+
+  2007-03-28 Kieran Mansley
+  * opt.h Change default PBUF_POOL_BUFSIZE (again) to accomodate default MSS +
+    IP and TCP headers *and* physical link headers
+
+  2007-03-26 Frédéric Bernon (based on patch from Dmitry Potapov)
+  * api_lib.c: patch for netconn_write(), fixes a possible race condition which cause
+    to send some garbage. It is not a definitive solution, but the patch does solve
+    the problem for most cases.
+
+  2007-03-22 Frédéric Bernon
+  * api_msg.h, api_msg.c: Remove obsolete API_MSG_ACCEPT and do_accept (never used).
+
+  2007-03-22 Frédéric Bernon
+  * api_lib.c: somes resources couldn't be freed if there was errors during
+    netconn_new_with_proto_and_callback.
+
+  2007-03-22 Frédéric Bernon
+  * ethernetif.c: update netif->input calls to check return value. In older ports,
+    it's a good idea to upgrade them, even if before, there could be another problem
+    (access to an uninitialized mailbox).
+
+  2007-03-21 Simon Goldschmidt
+  * sockets.c: fixed bug #5067 (essentialy a signed/unsigned warning fixed
+    by casting to unsigned).
+
+  2007-03-21 Frédéric Bernon
+  * api_lib.c, api_msg.c, tcpip.c: integrate sys_mbox_fetch(conn->mbox, NULL) calls from
+    api_lib.c to tcpip.c's tcpip_apimsg(). Now, use a local variable and not a
+    dynamic one from memp to send tcpip_msg to tcpip_thread in a synchrone call.
+    Free tcpip_msg from tcpip_apimsg is not done in tcpip_thread. This give a
+    faster and more reliable communication between api_lib and tcpip.
+
+  2007-03-21 Frédéric Bernon
+  * opt.h: Add LWIP_NETIF_CALLBACK (to avoid compiler warning) and set it to 0.
+
+  2007-03-21 Frédéric Bernon
+  * api_msg.c, igmp.c, igmp.h: Fix C++ style comments
+
+  2007-03-21 Kieran Mansley
+  * opt.h Change default PBUF_POOL_BUFSIZE to accomodate default MSS +
+    IP and TCP headers
+
+  2007-03-21 Kieran Mansley
+  * Fix all uses of pbuf_header to check the return value.  In some
+    cases just assert if it fails as I'm not sure how to fix them, but
+    this is no worse than before when they would carry on regardless
+    of the failure.
+
+  2007-03-21 Kieran Mansley
+  * sockets.c, igmp.c, igmp.h, memp.h: Fix C++ style comments and
+    comment out missing header include in icmp.c
+
+  2007-03-20 Frédéric Bernon
+  * memp.h, stats.c: Fix stats_display function where memp_names table wasn't
+    synchronized with memp.h.
+
+  2007-03-20 Frédéric Bernon
+  * tcpip.c: Initialize tcpip's mbox, and verify if initialized in tcpip_input,
+    tcpip_ethinput, tcpip_callback, tcpip_apimsg, to fix a init problem with 
+    network interfaces. Also fix a compiler warning.
+
+  2007-03-20 Kieran Mansley
+  * udp.c: Only try and use pbuf_header() to make space for headers if
+    not a ROM or REF pbuf.
+
+  2007-03-19 Frédéric Bernon
+  * api_msg.h, api_msg.c, tcpip.h, tcpip.c: Add return types to tcpip_apimsg()
+    and api_msg_post().
+
+  2007-03-19 Frédéric Bernon
+  * Remove unimplemented "memp_realloc" function from memp.h.
+
+  2007-03-11 Simon Goldschmidt
+  * pbuf.c: checked in patch #5796: pbuf_alloc: len field claculation caused
+    memory corruption.
+
+  2007-03-11 Simon Goldschmidt (based on patch from Dmitry Potapov)
+  * api_lib.c, sockets.c, api.h, api_msg.h, sockets.h: Fixed bug #19251
+    (missing `const' qualifier in socket functions), to get more compatible to
+    standard POSIX sockets.
+
+  2007-03-11 Frédéric Bernon (based on patch from Dmitry Potapov)
+  * sockets.c: Add asserts inside bind, connect and sendto to check input
+    parameters. Remove excessive set_errno() calls after get_socket(), because
+    errno is set inside of get_socket(). Move last sock_set_errno() inside
+    lwip_close.
+
+  2007-03-09 Simon Goldschmidt
+  * memp.c: Fixed bug #11400: New etharp queueing introduced bug: memp_memory
+    was allocated too small.
+
+  2007-03-06 Simon Goldschmidt
+  * tcpip.c: Initialize dhcp timers in tcpip_thread (if LWIP_DHCP) to protect
+    the stack from concurrent access.
+
+  2007-03-06 Frédéric Bernon, Dmitry Potapov
+  * tcpip.c, ip_frag.c, ethernetif.c: Fix some build problems, and a redundancy
+    call to "lwip_stats.link.recv++;" in low_level_input() & ethernetif_input().
+
+  2007-03-06 Simon Goldschmidt
+  * ip_frag.c, ip_frag.h: Reduce code size: don't include code in those files
+    if IP_FRAG == 0 and IP_REASSEMBLY == 0
+
+  2007-03-06 Frédéric Bernon, Simon Goldschmidt
+  * opt.h, ip_frag.h, tcpip.h, tcpip.c, ethernetif.c: add new configuration
+    option named ETHARP_TCPIP_ETHINPUT, which enable the new tcpip_ethinput.
+    Allow to do ARP processing for incoming packets inside tcpip_thread
+    (protecting ARP layer against concurrent access). You can also disable
+    old code using tcp_input with new define ETHARP_TCPIP_INPUT set to 0.
+    Older ports have to use tcpip_ethinput.
+
+  2007-03-06 Simon Goldschmidt (based on patch from Dmitry Potapov)
+  * err.h, err.c: fixed compiler warning "initialization dircards qualifiers
+    from pointer target type"
+
+  2007-03-05 Frédéric Bernon
+  * opt.h, sockets.h: add new configuration options (LWIP_POSIX_SOCKETS_IO_NAMES,
+    ETHARP_TRUST_IP_MAC, review SO_REUSE)
+
+  2007-03-04 Frédéric Bernon
+  * api_msg.c: Remove some compiler warnings : parameter "pcb" was never
+    referenced.
+
+  2007-03-04 Frédéric Bernon
+  * api_lib.c: Fix "[patch #5764] api_lib.c cleanup: after patch #5687" (from
+    Dmitry Potapov).
+    The api_msg struct stay on the stack (not moved to netconn struct).
+
+  2007-03-04 Simon Goldschmidt (based on patch from Dmitry Potapov)
+  * pbuf.c: Fix BUG#19168 - pbuf_free can cause deadlock (if
+    SYS_LIGHTWEIGHT_PROT=1 & freeing PBUF_RAM when mem_sem is not available)
+    Also fixed cast warning in pbuf_alloc()
+
+  2007-03-04 Simon Goldschmidt
+  * etharp.c, etharp.h, memp.c, memp.h, opt.h: Fix BUG#11400 - don't corrupt
+    existing pbuf chain when enqueuing multiple pbufs to a pending ARP request
+
+  2007-03-03 Frédéric Bernon
+  * udp.c: remove obsolete line "static struct udp_pcb *pcb_cache = NULL;"
+    It is static, and never used in udp.c except udp_init().
+
+  2007-03-02 Simon Goldschmidt
+  * tcpip.c: Moved call to ip_init(), udp_init() and tcp_init() from
+    tcpip_thread() to tcpip_init(). This way, raw API connections can be
+    initialized before tcpip_thread is running (e.g. before OS is started)
+
+  2007-03-02 Frédéric Bernon
+  * rawapi.txt: Fix documentation mismatch with etharp.h about etharp_tmr's call
+    interval.
+
+  2007-02-28 Kieran Mansley 
+  * pbuf.c: Fix BUG#17645 - ensure pbuf payload pointer is not moved
+    outside the region of the pbuf by pbuf_header()
+
+  2007-02-28 Kieran Mansley 
+  * sockets.c: Fix BUG#19161 - ensure milliseconds timeout is non-zero
+    when supplied timeout is also non-zero 
+
+(STABLE-1.2.0)
+
+  2006-12-05 Leon Woestenberg
+  * CHANGELOG: Mention STABLE-1.2.0 release.
+
+  ++ New features:
+
+  2006-12-01 Christiaan Simons
+  * mem.h, opt.h: Added MEM_LIBC_MALLOC option.
+    Note this is a workaround. Currently I have no other options left.
+
+  2006-10-26 Christiaan Simons (accepted patch by Jonathan Larmour)
+  * ipv4/ip_frag.c: rename MAX_MTU to IP_FRAG_MAX_MTU and move define
+    to include/lwip/opt.h.
+  * ipv4/lwip/ip_frag.h: Remove unused IP_REASS_INTERVAL.
+    Move IP_REASS_MAXAGE and IP_REASS_BUFSIZE to include/lwip/opt.h.
+  * opt.h: Add above new options.
+
+  2006-08-18 Christiaan Simons
+  * tcp_{in,out}.c: added SNMP counters.
+  * ipv4/ip.c: added SNMP counters.
+  * ipv4/ip_frag.c: added SNMP counters.
+
+  2006-08-08 Christiaan Simons
+  * etharp.{c,h}: added etharp_find_addr() to read
+    (stable) ethernet/IP address pair from ARP table
+
+  2006-07-14 Christiaan Simons
+  * mib_structs.c: added
+  * include/lwip/snmp_structs.h: added
+  * netif.{c,h}, netif/ethernetif.c: added SNMP statistics to netif struct
+
+  2006-07-06 Christiaan Simons
+  * snmp/asn1_{enc,dec}.c added
+  * snmp/mib2.c added
+  * snmp/msg_{in,out}.c added
+  * include/lwip/snmp_asn1.h added
+  * include/lwip/snmp_msg.h added
+  * doc/snmp_agent.txt added
+
+  2006-03-29 Christiaan Simons
+  * inet.c, inet.h: Added platform byteswap support.
+    Added LWIP_PLATFORM_BYTESWAP define (defaults to 0) and
+    optional LWIP_PLATFORM_HTONS(), LWIP_PLATFORM_HTONL() macros.
+
+  ++ Bug fixes:
+
+  2006-11-30 Christiaan Simons
+  * dhcp.c: Fixed false triggers of request_timeout.
+
+  2006-11-28 Christiaan Simons
+  * netif.c: In netif_add() fixed missing clear of ip_addr, netmask, gw and flags.
+
+  2006-10-11 Christiaan Simons
+  * api_lib.c etharp.c, ip.c, memp.c, stats.c, sys.{c,h} tcp.h:
+    Partially accepted patch #5449 for ANSI C compatibility / build fixes.
+  * ipv4/lwip/ip.h ipv6/lwip/ip.h: Corrected UDP-Lite protocol
+    identifier from 170 to 136 (bug #17574).
+
+  2006-10-10 Christiaan Simons
+  * api_msg.c: Fixed Nagle algorithm as reported by Bob Grice.
+
+  2006-08-17 Christiaan Simons
+  * udp.c: Fixed bug #17200, added check for broadcast
+    destinations for PCBs bound to a unicast address.
+
+  2006-08-07 Christiaan Simons
+  * api_msg.c: Flushing TCP output in do_close() (bug #15926).
+
+  2006-06-27 Christiaan Simons
+  * api_msg.c: Applied patch for cold case (bug #11135).
+    In accept_function() ensure newconn->callback is always initialized.
+
+  2006-06-15 Christiaan Simons
+  * mem.h: added MEM_SIZE_F alias to fix an ancient cold case (bug #1748),
+    facilitate printing of mem_size_t and u16_t statistics.
+
+  2006-06-14 Christiaan Simons
+  * api_msg.c: Applied patch #5146 to handle allocation failures
+    in accept() by Kevin Lawson.
+
+  2006-05-26 Christiaan Simons
+  * api_lib.c: Removed conn->sem creation and destruction 
+    from netconn_write() and added sys_sem_new to netconn_new_*.
+
+(STABLE-1_1_1)
+
+  2006-03-03  Christiaan Simons
+  * ipv4/ip_frag.c: Added bound-checking assertions on ip_reassbitmap
+    access and added pbuf_alloc() return value checks.
+
+  2006-01-01  Leon Woestenberg 
+  * tcp_{in,out}.c, tcp_out.c: Removed 'even sndbuf' fix in TCP, which is
+    now handled by the checksum routine properly.
+
+  2006-02-27  Leon Woestenberg 
+   * pbuf.c: Fix alignment; pbuf_init() would not work unless
+     pbuf_pool_memory[] was properly aligned. (Patch by Curt McDowell.)
+
+  2005-12-20  Leon Woestenberg 
+  * tcp.c: Remove PCBs which stay in LAST_ACK state too long. Patch
+    submitted by Mitrani Hiroshi.
+
+  2005-12-15  Christiaan Simons
+  * inet.c: Disabled the added summing routine to preserve code space.
+
+  2005-12-14  Leon Woestenberg 
+  * tcp_in.c: Duplicate FIN ACK race condition fix by Kelvin Lawson.
+    Added Curt McDowell's optimized checksumming routine for future
+    inclusion. Need to create test case for unaliged, aligned, odd,
+    even length combination of cases on various endianess machines.
+
+  2005-12-09  Christiaan Simons
+  * inet.c: Rewrote standard checksum routine in proper portable C.
+
+  2005-11-25  Christiaan Simons
+  * udp.c tcp.c: Removed SO_REUSE hack. Should reside in socket code only.
+  * *.c: introduced cc.h LWIP_DEBUG formatters matching the u16_t, s16_t,
+    u32_t, s32_t typedefs. This solves most debug word-length assumes.
+
+  2005-07-17 Leon Woestenberg 
+  * inet.c: Fixed unaligned 16-bit access in the standard checksum
+    routine by Peter Jolasson.
+  * slipif.c: Fixed implementation assumption of single-pbuf datagrams.
+
+  2005-02-04 Leon Woestenberg 
+  * tcp_out.c: Fixed uninitialized 'queue' referenced in memerr branch.
+  * tcp_{out|in}.c: Applied patch fixing unaligned access.
+
+  2005-01-04 Leon Woestenberg 
+  * pbuf.c: Fixed missing semicolon after LWIP_DEBUG statement.
+
+  2005-01-03 Leon Woestenberg 
+  * udp.c: UDP pcb->recv() was called even when it was NULL.
+
+(STABLE-1_1_0)
+
+  2004-12-28 Leon Woestenberg 
+  * etharp.*: Disabled multiple packets on the ARP queue.
+    This clashes with TCP queueing.
+
+  2004-11-28 Leon Woestenberg 
+  * etharp.*: Fixed race condition from ARP request to ARP timeout.
+    Halved the ARP period, doubled the period counts.
+    ETHARP_MAX_PENDING now should be at least 2. This prevents
+    the counter from reaching 0 right away (which would allow
+    too little time for ARP responses to be received).
+
+  2004-11-25 Leon Woestenberg 
+  * dhcp.c: Decline messages were not multicast but unicast.
+  * etharp.c: ETHARP_CREATE is renamed to ETHARP_TRY_HARD.
+    Do not try hard to insert arbitrary packet's source address,
+    etharp_ip_input() now calls etharp_update() without ETHARP_TRY_HARD. 
+    etharp_query() now always DOES call ETHARP_TRY_HARD so that users
+    querying an address will see it appear in the cache (DHCP could
+    suffer from this when a server invalidly gave an in-use address.)
+  * ipv4/ip_addr.h: Renamed ip_addr_maskcmp() to _netcmp() as we are
+    comparing network addresses (identifiers), not the network masks
+    themselves.
+  * ipv4/ip_addr.c: ip_addr_isbroadcast() now checks that the given
+    IP address actually belongs to the network of the given interface.
+
+  2004-11-24 Kieran Mansley 
+  * tcp.c: Increment pcb->snd_buf when ACK is received in SYN_SENT state.
+
+(STABLE-1_1_0-RC1)
+
+  2004-10-16 Kieran Mansley 
+  * tcp.c: Add code to tcp_recved() to send an ACK (window update) immediately,
+    even if one is already pending, if the rcv_wnd is above a threshold
+    (currently TCP_WND/2). This avoids waiting for a timer to expire to send a
+    delayed ACK in order to open the window if the stack is only receiving data.
+
+  2004-09-12 Kieran Mansley 
+  * tcp*.*: Retransmit time-out handling improvement by Sam Jansen.
+
+  2004-08-20 Tony Mountifield 
+  * etharp.c: Make sure the first pbuf queued on an ARP entry
+    is properly ref counted.
+
+  2004-07-27 Tony Mountifield 
+  * debug.h: Added (int) cast in LWIP_DEBUGF() to avoid compiler
+    warnings about comparison.
+  * pbuf.c: Stopped compiler complaining of empty if statement
+    when LWIP_DEBUGF() empty.  Closed an unclosed comment.
+  * tcp.c: Stopped compiler complaining of empty if statement
+    when LWIP_DEBUGF() empty.
+  * ip.h Corrected IPH_TOS() macro: returns a byte, so doesn't need htons().
+  * inet.c: Added a couple of casts to quiet the compiler.
+    No need to test isascii(c) before isdigit(c) or isxdigit(c).
+
+  2004-07-22 Tony Mountifield 
+  * inet.c: Made data types consistent in inet_ntoa().
+    Added casts for return values of checksum routines, to pacify compiler.
+  * ip_frag.c, tcp_out.c, sockets.c, pbuf.c
+    Small corrections to some debugging statements, to pacify compiler.
+
+  2004-07-21 Tony Mountifield 
+  * etharp.c: Removed spurious semicolon and added missing end-of-comment.
+  * ethernetif.c Updated low_level_output() to match prototype for
+    netif->linkoutput and changed low_level_input() similarly for consistency.
+  * api_msg.c: Changed recv_raw() from int to u8_t, to match prototype
+    of raw_recv() in raw.h and so avoid compiler error.
+  * sockets.c: Added trivial (int) cast to keep compiler happier.
+  * ip.c, netif.c Changed debug statements to use the tidier ip4_addrN() macros.
+
+(STABLE-1_0_0)
+
+  ++ Changes:
+
+  2004-07-05 Leon Woestenberg 
+  * sockets.*: Restructured LWIP_PRIVATE_TIMEVAL. Make sure
+    your cc.h file defines this either 1 or 0. If non-defined,
+    defaults to 1.
+  * .c: Added  and  includes where used.
+  * etharp.c: Made some array indices unsigned.
+
+  2004-06-27 Leon Woestenberg 
+  * netif.*: Added netif_set_up()/down().
+  * dhcp.c: Changes to restart program flow.
+
+  2004-05-07 Leon Woestenberg 
+  * etharp.c: In find_entry(), instead of a list traversal per candidate, do a
+    single-pass lookup for different candidates. Should exploit locality.
+
+  2004-04-29 Leon Woestenberg 
+  * tcp*.c: Cleaned up source comment documentation for Doxygen processing.
+  * opt.h: ETHARP_ALWAYS_INSERT option removed to comply with ARP RFC.
+  * etharp.c: update_arp_entry() only adds new ARP entries when adviced to by
+    the caller. This deprecates the ETHARP_ALWAYS_INSERT overrule option.
+
+  ++ Bug fixes:
+
+  2004-04-27 Leon Woestenberg 
+  * etharp.c: Applied patch of bug #8708 by Toni Mountifield with a solution
+    suggested by Timmy Brolin. Fix for 32-bit processors that cannot access
+    non-aligned 32-bit words, such as soms 32-bit TCP/IP header fields. Fix
+    is to prefix the 14-bit Ethernet headers with two padding bytes.
+
+  2004-04-23 Leon Woestenberg 
+  * ip_addr.c: Fix in the ip_addr_isbroadcast() check.
+  * etharp.c: Fixed the case where the packet that initiates the ARP request
+    is not queued, and gets lost. Fixed the case where the packets destination
+    address is already known; we now always queue the packet and perform an ARP
+    request.
+
+(STABLE-0_7_0)
+
+  ++ Bug fixes:
+
+  * Fixed TCP bug for SYN_SENT to ESTABLISHED state transition.
+  * Fixed TCP bug in dequeueing of FIN from out of order segment queue.
+  * Fixed two possible NULL references in rare cases.
+
+(STABLE-0_6_6)
+
+  ++ Bug fixes:
+
+  * Fixed DHCP which did not include the IP address in DECLINE messages.
+
+  ++ Changes:
+
+  * etharp.c has been hauled over a bit.
+
+(STABLE-0_6_5)
+
+  ++ Bug fixes:
+
+  * Fixed TCP bug induced by bad window resizing with unidirectional TCP traffic.
+  * Packets sent from ARP queue had invalid source hardware address.
+
+  ++ Changes:
+
+  * Pass-by ARP requests do now update the cache.
+
+  ++ New features:
+
+  * No longer dependent on ctype.h.
+  * New socket options.
+  * Raw IP pcb support.
+
+(STABLE-0_6_4)
+
+  ++ Bug fixes:
+
+  * Some debug formatters and casts fixed.
+  * Numereous fixes in PPP.
+
+  ++ Changes:
+
+  * DEBUGF now is LWIP_DEBUGF
+  * pbuf_dechain() has been re-enabled.
+  * Mentioned the changed use of CVS branches in README.
+
+(STABLE-0_6_3)
+
+  ++ Bug fixes:
+
+  * Fixed pool pbuf memory leak in pbuf_alloc().
+    Occured if not enough PBUF_POOL pbufs for a packet pbuf chain.
+    Reported by Savin Zlobec.
+
+  * PBUF_POOL chains had their tot_len field not set for non-first
+    pbufs. Fixed in pbuf_alloc().
+
+  ++ New features:
+
+  * Added PPP stack contributed by Marc Boucher
+
+  ++ Changes:
+
+  * Now drops short packets for ICMP/UDP/TCP protocols. More robust.
+
+  * ARP queueuing now queues the latest packet instead of the first.
+    This is the RFC recommended behaviour, but can be overridden in
+    lwipopts.h.
+
+(0.6.2)
+
+  ++ Bugfixes:
+
+  * TCP has been fixed to deal with the new use of the pbuf->ref
+    counter.
+
+  * DHCP dhcp_inform() crash bug fixed.
+
+  ++ Changes:
+
+  * Removed pbuf_pool_free_cache and pbuf_pool_alloc_cache. Also removed
+    pbuf_refresh(). This has sped up pbuf pool operations considerably.
+    Implemented by David Haas.
+
+(0.6.1)
+
+  ++ New features:
+
+  * The packet buffer implementation has been enhanced to support
+    zero-copy and copy-on-demand for packet buffers which have their
+    payloads in application-managed memory.
+    Implemented by David Haas.
+
+    Use PBUF_REF to make a pbuf refer to RAM. lwIP will use zero-copy
+    if an outgoing packet can be directly sent on the link, or perform
+    a copy-on-demand when necessary.
+
+    The application can safely assume the packet is sent, and the RAM
+    is available to the application directly after calling udp_send()
+    or similar function.
+
+  ++ Bugfixes:
+
+  * ARP_QUEUEING should now correctly work for all cases, including
+    PBUF_REF.
+    Implemented by Leon Woestenberg.
+
+  ++ Changes:
+
+  * IP_ADDR_ANY is no longer a NULL pointer. Instead, it is a pointer
+    to a '0.0.0.0' IP address.
+
+  * The packet buffer implementation is changed. The pbuf->ref counter
+    meaning has changed, and several pbuf functions have been
+    adapted accordingly.
+
+  * netif drivers have to be changed to set the hardware address length field
+    that must be initialized correctly by the driver (hint: 6 for Ethernet MAC).
+    See the contrib/ports/c16x cs8900 driver as a driver example.
+
+  * netif's have a dhcp field that must be initialized to NULL by the driver.
+    See the contrib/ports/c16x cs8900 driver as a driver example.
+
+(0.5.x) This file has been unmaintained up to 0.6.1. All changes are
+  logged in CVS but have not been explained here.
+
+(0.5.3) Changes since version 0.5.2
+
+  ++ Bugfixes:
+
+  * memp_malloc(MEMP_API_MSG) could fail with multiple application
+    threads because it wasn't protected by semaphores.
+
+  ++ Other changes:
+
+  * struct ip_addr now packed.
+
+  * The name of the time variable in arp.c has been changed to ctime
+    to avoid conflicts with the time() function.
+
+(0.5.2) Changes since version 0.5.1
+
+  ++ New features:
+
+  * A new TCP function, tcp_tmr(), now handles both TCP timers.
+
+  ++ Bugfixes:
+
+  * A bug in tcp_parseopt() could cause the stack to hang because of a
+    malformed TCP option.
+
+  * The address of new connections in the accept() function in the BSD
+    socket library was not handled correctly.
+
+  * pbuf_dechain() did not update the ->tot_len field of the tail.
+
+  * Aborted TCP connections were not handled correctly in all
+    situations.
+
+  ++ Other changes:
+
+  * All protocol header structs are now packed.
+
+  * The ->len field in the tcp_seg structure now counts the actual
+    amount of data, and does not add one for SYN and FIN segments.
+
+(0.5.1) Changes since version 0.5.0
+
+  ++ New features:
+
+  * Possible to run as a user process under Linux.
+
+  * Preliminary support for cross platform packed structs.
+
+  * ARP timer now implemented.
+
+  ++ Bugfixes:
+
+  * TCP output queue length was badly initialized when opening
+    connections.
+
+  * TCP delayed ACKs were not sent correctly.
+
+  * Explicit initialization of BSS segment variables.
+
+  * read() in BSD socket library could drop data.
+
+  * Problems with memory alignment.
+
+  * Situations when all TCP buffers were used could lead to
+    starvation.
+
+  * TCP MSS option wasn't parsed correctly.
+
+  * Problems with UDP checksum calculation.
+
+  * IP multicast address tests had endianess problems.
+
+  * ARP requests had wrong destination hardware address.
+
+  ++ Other changes:
+
+  * struct eth_addr changed from u16_t[3] array to u8_t[6].
+
+  * A ->linkoutput() member was added to struct netif.
+
+  * TCP and UDP ->dest_* struct members where changed to ->remote_*.
+
+  * ntoh* macros are now null definitions for big endian CPUs.
+
+(0.5.0) Changes since version 0.4.2
+
+  ++ New features:
+
+  * Redesigned operating system emulation layer to make porting easier.
+
+  * Better control over TCP output buffers.
+
+  * Documenation added.
+
+  ++ Bugfixes:
+
+  * Locking issues in buffer management.
+
+  * Bugfixes in the sequential API.
+
+  * IP forwarding could cause memory leakage. This has been fixed.
+
+  ++ Other changes:
+
+  * Directory structure somewhat changed; the core/ tree has been
+    collapsed.
+
+(0.4.2) Changes since version 0.4.1
+
+  ++ New features:
+
+  * Experimental ARP implementation added.
+
+  * Skeleton Ethernet driver added.
+
+  * Experimental BSD socket API library added.
+
+  ++ Bugfixes:
+
+  * In very intense situations, memory leakage could occur. This has
+    been fixed.
+
+  ++ Other changes:
+
+  * Variables named "data" and "code" have been renamed in order to
+    avoid name conflicts in certain compilers.
+
+  * Variable++ have in appliciable cases been translated to ++variable
+    since some compilers generate better code in the latter case.
+
+(0.4.1) Changes since version 0.4
+
+  ++ New features:
+
+  * TCP: Connection attempts time out earlier than data
+    transmissions. Nagle algorithm implemented. Push flag set on the
+    last segment in a burst.
+
+  * UDP: experimental support for UDP-Lite extensions.
+
+  ++ Bugfixes:
+
+  * TCP: out of order segments were in some cases handled incorrectly,
+    and this has now been fixed. Delayed acknowledgements was broken
+    in 0.4, has now been fixed. Binding to an address that is in use
+    now results in an error. Reset connections sometimes hung an
+    application; this has been fixed.
+
+  * Checksum calculation sometimes failed for chained pbufs with odd
+    lengths. This has been fixed.
+
+  * API: a lot of bug fixes in the API. The UDP API has been improved
+    and tested. Error reporting and handling has been
+    improved. Logical flaws and race conditions for incoming TCP
+    connections has been found and removed.
+
+  * Memory manager: alignment issues. Reallocating memory sometimes
+    failed, this has been fixed.
+
+  * Generic library: bcopy was flawed and has been fixed.
+
+  ++ Other changes:
+
+  * API: all datatypes has been changed from generic ones such as
+    ints, to specified ones such as u16_t. Functions that return
+    errors now have the correct type (err_t).
+
+  * General: A lot of code cleaned up and debugging code removed. Many
+    portability issues have been fixed.
+
+  * The license was changed; the advertising clause was removed.
+
+  * C64 port added.
+
+  * Thanks: Huge thanks go to Dagan Galarneau, Horst Garnetzke, Petri
+    Kosunen, Mikael Caleres, and Frits Wilmink for reporting and
+    fixing bugs!
+
+(0.4) Changes since version 0.3.1
+
+  * Memory management has been radically changed; instead of
+    allocating memory from a shared heap, memory for objects that are
+    rapidly allocated and deallocated is now kept in pools. Allocation
+    and deallocation from those memory pools is very fast. The shared
+    heap is still present but is used less frequently.
+
+  * The memory, memory pool, and packet buffer subsystems now support
+    4-, 2-, or 1-byte alignment.
+
+  * "Out of memory" situations are handled in a more robust way.
+
+  * Stack usage has been reduced.
+
+  * Easier configuration of lwIP parameters such as memory usage,
+    TTLs, statistics gathering, etc. All configuration parameters are
+    now kept in a single header file "lwipopts.h".
+
+  * The directory structure has been changed slightly so that all
+    architecture specific files are kept under the src/arch
+    hierarchy.
+
+  * Error propagation has been improved, both in the protocol modules
+    and in the API.
+
+  * The code for the RTXC architecture has been implemented, tested
+    and put to use.
+
+  * Bugs have been found and corrected in the TCP, UDP, IP, API, and
+    the Internet checksum modules.
+
+  * Bugs related to porting between a 32-bit and a 16-bit architecture
+    have been found and corrected.
+
+  * The license has been changed slightly to conform more with the
+    original BSD license, including the advertisement clause.
+
+(0.3.1) Changes since version 0.3
+
+  * Fix of a fatal bug in the buffer management. Pbufs with allocated
+    RAM never returned the RAM when the pbuf was deallocated.
+
+  * TCP congestion control, window updates and retransmissions did not
+    work correctly. This has now been fixed.
+
+  * Bugfixes in the API.
+
+(0.3) Changes since version 0.2
+
+  * New and improved directory structure. All include files are now
+    kept in a dedicated include/ directory.
+
+  * The API now has proper error handling. A new function,
+    netconn_err(), now returns an error code for the connection in
+    case of errors.
+
+  * Improvements in the memory management subsystem. The system now
+    keeps a pointer to the lowest free memory block. A new function,
+    mem_malloc2() tries to allocate memory once, and if it fails tries
+    to free some memory and retry the allocation.
+
+  * Much testing has been done with limited memory
+    configurations. lwIP now does a better job when overloaded.
+
+  * Some bugfixes and improvements to the buffer (pbuf) subsystem.
+
+  * Many bugfixes in the TCP code:
+
+    - Fixed a bug in tcp_close().
+
+    - The TCP receive window was incorrectly closed when out of
+      sequence segments was received. This has been fixed.
+
+    - Connections are now timed-out of the FIN-WAIT-2 state.
+
+    - The initial congestion window could in some cases be too
+      large. This has been fixed.
+
+    - The retransmission queue could in some cases be screwed up. This
+      has been fixed.
+
+    - TCP RST flag now handled correctly.
+
+    - Out of sequence data was in some cases never delivered to the
+      application. This has been fixed.
+
+    - Retransmitted segments now contain the correct acknowledgment
+      number and advertised window.
+
+    - TCP retransmission timeout backoffs are not correctly computed
+      (ala BSD). After a number of retransmissions, TCP now gives up
+      the connection.
+
+  * TCP connections now are kept on three lists, one for active
+    connections, one for listening connections, and one for
+    connections that are in TIME-WAIT. This greatly speeds up the fast
+    timeout processing for sending delayed ACKs.
+
+  * TCP now provides proper feedback to the application when a
+    connection has been successfully set up.
+
+  * More comments have been added to the code. The code has also been
+    somewhat cleaned up.
+
+(0.2) Initial public release.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/COPYING b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/COPYING
new file mode 100644
index 0000000..e23898b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/COPYING
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2001, 2002 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/FILES b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/FILES
new file mode 100644
index 0000000..6625319
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/FILES
@@ -0,0 +1,4 @@
+src/      - The source code for the lwIP TCP/IP stack.
+doc/      - The documentation for lwIP.
+
+See also the FILES file in each subdirectory.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/README b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/README
new file mode 100644
index 0000000..a62cc4f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/README
@@ -0,0 +1,89 @@
+INTRODUCTION
+
+lwIP is a small independent implementation of the TCP/IP protocol
+suite that has been developed by Adam Dunkels at the Computer and
+Networks Architectures (CNA) lab at the Swedish Institute of Computer
+Science (SICS).
+
+The focus of the lwIP TCP/IP implementation is to reduce the RAM usage
+while still having a full scale TCP. This making lwIP suitable for use
+in embedded systems with tens of kilobytes of free RAM and room for
+around 40 kilobytes of code ROM.
+
+FEATURES
+
+  * IP (Internet Protocol) including packet forwarding over multiple network
+    interfaces
+  * ICMP (Internet Control Message Protocol) for network maintenance and debugging
+  * IGMP (Internet Group Management Protocol) for multicast traffic management
+  * UDP (User Datagram Protocol) including experimental UDP-lite extensions
+  * TCP (Transmission Control Protocol) with congestion control, RTT estimation
+    and fast recovery/fast retransmit
+  * Specialized raw/native API for enhanced performance
+  * Optional Berkeley-like socket API
+  * DNS (Domain names resolver)
+  * SNMP (Simple Network Management Protocol)
+  * DHCP (Dynamic Host Configuration Protocol)
+  * AUTOIP (for IPv4, conform with RFC 3927)
+  * PPP (Point-to-Point Protocol)
+  * ARP (Address Resolution Protocol) for Ethernet
+
+LICENSE
+
+lwIP is freely available under a BSD license.
+
+DEVELOPMENT
+
+lwIP has grown into an excellent TCP/IP stack for embedded devices,
+and developers using the stack often submit bug fixes, improvements,
+and additions to the stack to further increase its usefulness.
+
+Development of lwIP is hosted on Savannah, a central point for
+software development, maintenance and distribution. Everyone can
+help improve lwIP by use of Savannah's interface, CVS and the
+mailing list. A core team of developers will commit changes to the
+CVS source tree.
+
+The lwIP TCP/IP stack is maintained in the 'lwip' CVS module and
+contributions (such as platform ports) are in the 'contrib' module.
+
+See doc/savannah.txt for details on CVS server access for users and
+developers.
+
+Last night's CVS tar ball can be downloaded from:
+  http://savannah.gnu.org/cvs.backups/lwip.tar.gz [CHANGED - NEEDS FIXING]
+
+The current CVS trees are web-browsable:
+  http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/lwip/
+  http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/contrib/
+
+Submit patches and bugs via the lwIP project page:
+  http://savannah.nongnu.org/projects/lwip/
+
+
+DOCUMENTATION
+
+The original out-dated homepage of lwIP and Adam Dunkels' papers on
+lwIP are at the official lwIP home page:
+  http://www.sics.se/~adam/lwip/
+
+Self documentation of the source code is regularly extracted from the
+current CVS sources and is available from this web page:
+  http://www.nongnu.org/lwip/
+
+There is now a constantly growin wiki about lwIP at
+  http://lwip.wikia.com/wiki/LwIP_Wiki
+
+Also, there are mailing lists you can subscribe at
+  http://savannah.nongnu.org/mail/?group=lwip
+plus searchable archives:
+  http://lists.nongnu.org/archive/html/lwip-users/
+  http://lists.nongnu.org/archive/html/lwip-devel/
+
+Reading Adam's papers, the files in docs/, browsing the source code
+documentation and browsing the mailing list archives is a good way to
+become familiar with the design of lwIP.
+
+Adam Dunkels 
+Leon Woestenberg 
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/UPGRADING b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/UPGRADING
new file mode 100644
index 0000000..6501107
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/UPGRADING
@@ -0,0 +1,144 @@
+This file lists major changes between release versions that require
+ports or applications to be changed. Use it to update a port or an
+application written for an older version of lwIP to correctly work
+with newer versions.
+
+
+(CVS HEAD)
+
+  * [Enter new changes just after this line - do not remove this line]
+
+  ++ Application changes:
+
+  * Replaced struct ip_addr by typedef ip_addr_t (struct ip_addr is kept for
+    compatibility to old applications, but will be removed in the future).
+
+  * Renamed mem_realloc() to mem_trim() to prevent confusion with realloc()
+
+  +++ Raw API:
+    * Changed the semantics of tcp_close() (since it was rather a
+      shutdown before): Now the application does *NOT* get any calls to the recv
+      callback (aside from NULL/closed) after calling tcp_close()
+
+    * When calling tcp_abort() from a raw API TCP callback function,
+      make sure you return ERR_ABRT to prevent accessing unallocated memory.
+      (ERR_ABRT now means the applicaiton has called tcp_abort!)
+
+  +++ Netconn API:
+    * Changed netconn_receive() and netconn_accept() to return
+      err_t, not a pointer to new data/netconn.
+
+  +++ Socket API:
+    * LWIP_SO_RCVTIMEO: when accept() or recv() time out, they
+      now set errno to EWOULDBLOCK/EAGAIN, not ETIMEDOUT.
+
+    * Added a minimal version of posix fctl() to have a
+      standardised way to set O_NONBLOCK for nonblocking sockets.
+
+  +++ all APIs:
+    * correctly implemented SO(F)_REUSEADDR
+
+  ++ Port changes
+
+  +++ new files:
+
+    * Added 4 new files: def.c, timers.c, timers.h, tcp_impl.h:
+
+    * Moved stack-internal parts of tcp.h to tcp_impl.h, tcp.h now only contains
+      the actual application programmer's API
+  
+    * Separated timer implementation from sys.h/.c, moved to timers.h/.c;
+      Added timer implementation for NO_SYS==1, set NO_SYS_NO_TIMERS==1 if you
+      still want to use your own timer implementation for NO_SYS==0 (as before).
+
+  +++ sys layer:
+
+    * Converted mbox- and semaphore-functions to take pointers to sys_mbox_t/
+      sys_sem_t;
+
+    * Converted sys_mbox_new/sys_sem_new to take pointers and return err_t;
+
+    * Added Mutex concept in sys_arch (define LWIP_COMPAT_MUTEX to let sys.h use
+      binary semaphores instead of mutexes - as before)
+
+  +++ new options:
+
+     * Don't waste memory when chaining segments, added option TCP_OVERSIZE to
+       prevent creating many small pbufs when calling tcp_write with many small
+       blocks of data. Instead, pbufs are allocated larger than needed and the
+       space is used for later calls to tcp_write.
+
+     * Added LWIP_NETIF_TX_SINGLE_PBUF to always copy to try to create single pbufs
+       in tcp_write/udp_send.
+
+    * Added an additional option LWIP_ETHERNET to support ethernet without ARP
+      (necessary for pure PPPoE)
+
+    * Add MEMP_SEPARATE_POOLS to place memory pools in separate arrays. This may
+      be used to place these pools into user-defined memory by using external
+      declaration.
+
+    * Added TCP_SNDQUEUELOWAT corresponding to TCP_SNDLOWAT
+
+  +++ new pools:
+
+     * Netdb uses a memp pool for allocating memory when getaddrinfo() is called,
+       so MEMP_NUM_NETDB has to be set accordingly.
+
+     * DNS_LOCAL_HOSTLIST_IS_DYNAMIC uses a memp pool instead of the heap, so
+       MEMP_NUM_LOCALHOSTLIST has to be set accordingly.
+
+     * Snmp-agent uses a memp pools instead of the heap, so MEMP_NUM_SNMP_* have
+       to be set accordingly.
+
+     * PPPoE uses a MEMP pool instead of the heap, so MEMP_NUM_PPPOE_INTERFACES
+       has to be set accordingly
+
+  * Integrated loopif into netif.c - loopif does not have to be created by the
+    port any more, just define LWIP_HAVE_LOOPIF to 1.
+
+  * Added define LWIP_RAND() for lwip-wide randomization (needs to be defined
+    in cc.h, e.g. used by igmp)
+
+  * Added printf-formatter X8_F to printf u8_t as hex
+
+  * The heap now may be moved to user-defined memory by defining
+    LWIP_RAM_HEAP_POINTER as a void pointer to that memory's address
+
+  * added autoip_set_struct() and dhcp_set_struct() to let autoip and dhcp work
+    with user-allocated structs instead of calling mem_malloc
+
+  * Added const char* name to mem- and memp-stats for easier debugging.
+
+  * Calculate the TCP/UDP checksum while copying to only fetch data once:
+    Define LWIP_CHKSUM_COPY to a memcpy-like function that returns the checksum
+
+  * Added SO_REUSE_RXTOALL to pass received UDP broadcast/multicast packets to
+    more than one pcb.
+
+  * Changed the semantics of ARP_QUEUEING==0: ARP_QUEUEING now cannot be turned
+    off any more, if this is set to 0, only one packet (the most recent one) is
+    queued (like demanded by RFC 1122).
+
+  
+  ++ Major bugfixes/improvements
+
+  * Implemented tcp_shutdown() to only shut down one end of a connection
+  * Implemented shutdown() at socket- and netconn-level
+  * Added errorset support to select() + improved select speed overhead
+  * Merged pppd to v2.3.11 (including some backported bugfixes from 2.4.x)
+  * Added timer implementation for NO_SYS==1 (may be disabled with NO_SYS_NO_TIMERS==1
+  * Use macros defined in ip_addr.h to work with IP addresses
+  * Implemented many nonblocking socket/netconn functions
+  * Fixed ARP input processing: only add a new entry if a request was directed as us
+  * mem_realloc() to mem_trim() to prevent confusion with realloc()
+  * Some improvements for AutoIP (don't route/forward link-local addresses, don't break
+    existing connections when assigning a routable address)
+  * Correctly handle remote side overrunning our rcv_wnd in ooseq case
+  * Removed packing from ip_addr_t, the packed version is now only used in protocol headers
+  * Corrected PBUF_POOL_BUFSIZE for ports where ETH_PAD_SIZE > 0
+  * Added support for static ARP table entries
+
+(STABLE-1.3.2)
+
+  * initial version of this file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/doc/FILES b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/doc/FILES
new file mode 100644
index 0000000..05d356f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/doc/FILES
@@ -0,0 +1,6 @@
+savannah.txt   - How to obtain the current development source code.
+contrib.txt    - How to contribute to lwIP as a developer.
+rawapi.txt     - The documentation for the core API of lwIP.
+                 Also provides an overview about the other APIs and multithreading.
+snmp_agent.txt - The documentation for the lwIP SNMP agent.
+sys_arch.txt   - The documentation for a system abstraction layer of lwIP.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/doc/contrib.txt b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/doc/contrib.txt
new file mode 100644
index 0000000..39596fc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/doc/contrib.txt
@@ -0,0 +1,63 @@
+1 Introduction
+
+This document describes some guidelines for people participating
+in lwIP development.
+
+2 How to contribute to lwIP
+
+Here is a short list of suggestions to anybody working with lwIP and 
+trying to contribute bug reports, fixes, enhancements, platform ports etc.
+First of all as you may already know lwIP is a volunteer project so feedback
+to fixes or questions might often come late. Hopefully the bug and patch tracking 
+features of Savannah help us not lose users' input.
+
+2.1 Source code style:
+
+1. do not use tabs.
+2. indentation is two spaces per level (i.e. per tab).
+3. end debug messages with a trailing newline (\n).
+4. one space between keyword and opening bracket.
+5. no space between function and opening bracket.
+6. one space and no newline before opening curly braces of a block.
+7. closing curly brace on a single line.
+8. spaces surrounding assignment and comparisons.
+9. don't initialize static and/or global variables to zero, the compiler takes care of that.
+10. use current source code style as further reference.
+
+2.2 Source code documentation style:
+
+1. JavaDoc compliant and Doxygen compatible.
+2. Function documentation above functions in .c files, not .h files.
+   (This forces you to synchronize documentation and implementation.)
+3. Use current documentation style as further reference.
+ 
+2.3 Bug reports and patches:
+
+1. Make sure you are reporting bugs or send patches against the latest
+   sources. (From the latest release and/or the current CVS sources.)
+2. If you think you found a bug make sure it's not already filed in the
+   bugtracker at Savannah.
+3. If you have a fix put the patch on Savannah. If it is a patch that affects
+   both core and arch specific stuff please separate them so that the core can
+   be applied separately while leaving the other patch 'open'. The prefered way
+   is to NOT touch archs you can't test and let maintainers take care of them.
+   This is a good way to see if they are used at all - the same goes for unix
+   netifs except tapif.
+4. Do not file a bug and post a fix to it to the patch area. Either a bug report
+   or a patch will be enough.
+   If you correct an existing bug then attach the patch to the bug rather than creating a new entry in the patch area.
+5. Trivial patches (compiler warning, indentation and spelling fixes or anything obvious which takes a line or two)
+   can go to the lwip-users list. This is still the fastest way of interaction and the list is not so crowded
+   as to allow for loss of fixes. Putting bugs on Savannah and subsequently closing them is too much an overhead
+   for reporting a compiler warning fix.
+6. Patches should be specific to a single change or to related changes.Do not mix bugfixes with spelling and other
+   trivial fixes unless the bugfix is trivial too.Do not reorganize code and rename identifiers in the same patch you
+   change behaviour if not necessary.A patch is easier to read and understand if it's to the point and short than
+   if it's not to the point and long :) so the chances for it to be applied are greater. 
+
+2.4 Platform porters:
+
+1. If you have ported lwIP to a platform (an OS, a uC/processor or a combination of these) and
+   you think it could benefit others[1] you might want discuss this on the mailing list. You
+   can also ask for CVS access to submit and maintain your port in the contrib CVS module.
+   
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/doc/rawapi.txt b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/doc/rawapi.txt
new file mode 100644
index 0000000..bd452cf
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/doc/rawapi.txt
@@ -0,0 +1,505 @@
+Raw TCP/IP interface for lwIP
+
+Authors: Adam Dunkels, Leon Woestenberg, Christiaan Simons
+
+lwIP provides three Application Program's Interfaces (APIs) for programs
+to use for communication with the TCP/IP code:
+* low-level "core" / "callback" or "raw" API.
+* higher-level "sequential" API.
+* BSD-style socket API.
+
+The sequential API provides a way for ordinary, sequential, programs
+to use the lwIP stack. It is quite similar to the BSD socket API. The
+model of execution is based on the blocking open-read-write-close
+paradigm. Since the TCP/IP stack is event based by nature, the TCP/IP
+code and the application program must reside in different execution
+contexts (threads).
+
+The socket API is a compatibility API for existing applications,
+currently it is built on top of the sequential API. It is meant to
+provide all functions needed to run socket API applications running
+on other platforms (e.g. unix / windows etc.). However, due to limitations
+in the specification of this API, there might be incompatibilities
+that require small modifications of existing programs.
+
+** Threading
+
+lwIP started targeting single-threaded environments. When adding multi-
+threading support, instead of making the core thread-safe, another
+approach was chosen: there is one main thread running the lwIP core
+(also known as the "tcpip_thread"). The raw API may only be used from
+this thread! Application threads using the sequential- or socket API
+communicate with this main thread through message passing.
+
+      As such, the list of functions that may be called from
+      other threads or an ISR is very limited! Only functions
+      from these API header files are thread-safe:
+      - api.h
+      - netbuf.h
+      - netdb.h
+      - netifapi.h
+      - sockets.h
+      - sys.h
+
+      Additionaly, memory (de-)allocation functions may be
+      called from multiple threads (not ISR!) with NO_SYS=0
+      since they are protected by SYS_LIGHTWEIGHT_PROT and/or
+      semaphores.
+
+      Only since 1.3.0, if SYS_LIGHTWEIGHT_PROT is set to 1
+      and LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT is set to 1,
+      pbuf_free() may also be called from another thread or
+      an ISR (since only then, mem_free - for PBUF_RAM - may
+      be called from an ISR: otherwise, the HEAP is only
+      protected by semaphores).
+      
+
+** The remainder of this document discusses the "raw" API. **
+
+The raw TCP/IP interface allows the application program to integrate
+better with the TCP/IP code. Program execution is event based by
+having callback functions being called from within the TCP/IP
+code. The TCP/IP code and the application program both run in the same
+thread. The sequential API has a much higher overhead and is not very
+well suited for small systems since it forces a multithreaded paradigm
+on the application.
+
+The raw TCP/IP interface is not only faster in terms of code execution
+time but is also less memory intensive. The drawback is that program
+development is somewhat harder and application programs written for
+the raw TCP/IP interface are more difficult to understand. Still, this
+is the preferred way of writing applications that should be small in
+code size and memory usage.
+
+Both APIs can be used simultaneously by different application
+programs. In fact, the sequential API is implemented as an application
+program using the raw TCP/IP interface.
+
+--- Callbacks
+
+Program execution is driven by callbacks. Each callback is an ordinary
+C function that is called from within the TCP/IP code. Every callback
+function is passed the current TCP or UDP connection state as an
+argument. Also, in order to be able to keep program specific state,
+the callback functions are called with a program specified argument
+that is independent of the TCP/IP state.
+
+The function for setting the application connection state is:
+
+- void tcp_arg(struct tcp_pcb *pcb, void *arg)
+
+  Specifies the program specific state that should be passed to all
+  other callback functions. The "pcb" argument is the current TCP
+  connection control block, and the "arg" argument is the argument
+  that will be passed to the callbacks.
+
+  
+--- TCP connection setup
+
+The functions used for setting up connections is similar to that of
+the sequential API and of the BSD socket API. A new TCP connection
+identifier (i.e., a protocol control block - PCB) is created with the
+tcp_new() function. This PCB can then be either set to listen for new
+incoming connections or be explicitly connected to another host.
+
+- struct tcp_pcb *tcp_new(void)
+
+  Creates a new connection identifier (PCB). If memory is not
+  available for creating the new pcb, NULL is returned.
+
+- err_t tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port)
+
+  Binds the pcb to a local IP address and port number. The IP address
+  can be specified as IP_ADDR_ANY in order to bind the connection to
+  all local IP addresses.
+
+  If another connection is bound to the same port, the function will
+  return ERR_USE, otherwise ERR_OK is returned.
+
+- struct tcp_pcb *tcp_listen(struct tcp_pcb *pcb)
+
+  Commands a pcb to start listening for incoming connections. When an
+  incoming connection is accepted, the function specified with the
+  tcp_accept() function will be called. The pcb will have to be bound
+  to a local port with the tcp_bind() function.
+
+  The tcp_listen() function returns a new connection identifier, and
+  the one passed as an argument to the function will be
+  deallocated. The reason for this behavior is that less memory is
+  needed for a connection that is listening, so tcp_listen() will
+  reclaim the memory needed for the original connection and allocate a
+  new smaller memory block for the listening connection.
+
+  tcp_listen() may return NULL if no memory was available for the
+  listening connection. If so, the memory associated with the pcb
+  passed as an argument to tcp_listen() will not be deallocated.
+
+- struct tcp_pcb *tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog)
+
+  Same as tcp_listen, but limits the number of outstanding connections
+  in the listen queue to the value specified by the backlog argument.
+  To use it, your need to set TCP_LISTEN_BACKLOG=1 in your lwipopts.h.
+
+- void tcp_accepted(struct tcp_pcb *pcb)
+
+  Inform lwIP that an incoming connection has been accepted. This would
+  usually be called from the accept callback. This allows lwIP to perform
+  housekeeping tasks, such as allowing further incoming connections to be
+  queued in the listen backlog.
+
+- void tcp_accept(struct tcp_pcb *pcb,
+                  err_t (* accept)(void *arg, struct tcp_pcb *newpcb,
+                                   err_t err))
+
+  Specified the callback function that should be called when a new
+  connection arrives on a listening connection.
+      
+- err_t tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+                    u16_t port, err_t (* connected)(void *arg,
+                                                    struct tcp_pcb *tpcb,
+                                                    err_t err));
+
+  Sets up the pcb to connect to the remote host and sends the
+  initial SYN segment which opens the connection. 
+
+  The tcp_connect() function returns immediately; it does not wait for
+  the connection to be properly setup. Instead, it will call the
+  function specified as the fourth argument (the "connected" argument)
+  when the connection is established. If the connection could not be
+  properly established, either because the other host refused the
+  connection or because the other host didn't answer, the "err"
+  callback function of this pcb (registered with tcp_err, see below)
+  will be called.
+
+  The tcp_connect() function can return ERR_MEM if no memory is
+  available for enqueueing the SYN segment. If the SYN indeed was
+  enqueued successfully, the tcp_connect() function returns ERR_OK.
+
+  
+--- Sending TCP data
+
+TCP data is sent by enqueueing the data with a call to
+tcp_write(). When the data is successfully transmitted to the remote
+host, the application will be notified with a call to a specified
+callback function.
+
+- err_t tcp_write(struct tcp_pcb *pcb, void *dataptr, u16_t len,
+                  u8_t copy)
+
+  Enqueues the data pointed to by the argument dataptr. The length of
+  the data is passed as the len parameter. The copy argument is either
+  0 or 1 and indicates whether the new memory should be allocated for
+  the data to be copied into. If the argument is 0, no new memory
+  should be allocated and the data should only be referenced by
+  pointer.
+
+  The tcp_write() function will fail and return ERR_MEM if the length
+  of the data exceeds the current send buffer size or if the length of
+  the queue of outgoing segment is larger than the upper limit defined
+  in lwipopts.h. The number of bytes available in the output queue can
+  be retrieved with the tcp_sndbuf() function.
+
+  The proper way to use this function is to call the function with at
+  most tcp_sndbuf() bytes of data. If the function returns ERR_MEM,
+  the application should wait until some of the currently enqueued
+  data has been successfully received by the other host and try again.
+
+- void tcp_sent(struct tcp_pcb *pcb,
+                err_t (* sent)(void *arg, struct tcp_pcb *tpcb,
+                u16_t len))
+
+  Specifies the callback function that should be called when data has
+  successfully been received (i.e., acknowledged) by the remote
+  host. The len argument passed to the callback function gives the
+  amount bytes that was acknowledged by the last acknowledgment.
+
+  
+--- Receiving TCP data
+
+TCP data reception is callback based - an application specified
+callback function is called when new data arrives. When the
+application has taken the data, it has to call the tcp_recved()
+function to indicate that TCP can advertise increase the receive
+window.
+
+- void tcp_recv(struct tcp_pcb *pcb,
+                err_t (* recv)(void *arg, struct tcp_pcb *tpcb,
+                               struct pbuf *p, err_t err))
+
+  Sets the callback function that will be called when new data
+  arrives. The callback function will be passed a NULL pbuf to
+  indicate that the remote host has closed the connection. If
+  there are no errors and the callback function is to return
+  ERR_OK, then it must free the pbuf. Otherwise, it must not
+  free the pbuf so that lwIP core code can store it.
+
+- void tcp_recved(struct tcp_pcb *pcb, u16_t len)
+
+  Must be called when the application has received the data. The len
+  argument indicates the length of the received data.
+    
+
+--- Application polling
+
+When a connection is idle (i.e., no data is either transmitted or
+received), lwIP will repeatedly poll the application by calling a
+specified callback function. This can be used either as a watchdog
+timer for killing connections that have stayed idle for too long, or
+as a method of waiting for memory to become available. For instance,
+if a call to tcp_write() has failed because memory wasn't available,
+the application may use the polling functionality to call tcp_write()
+again when the connection has been idle for a while.
+
+- void tcp_poll(struct tcp_pcb *pcb, 
+                err_t (* poll)(void *arg, struct tcp_pcb *tpcb),
+				u8_t interval)
+
+  Specifies the polling interval and the callback function that should
+  be called to poll the application. The interval is specified in
+  number of TCP coarse grained timer shots, which typically occurs
+  twice a second. An interval of 10 means that the application would
+  be polled every 5 seconds.
+
+
+--- Closing and aborting connections
+
+- err_t tcp_close(struct tcp_pcb *pcb)
+
+  Closes the connection. The function may return ERR_MEM if no memory
+  was available for closing the connection. If so, the application
+  should wait and try again either by using the acknowledgment
+  callback or the polling functionality. If the close succeeds, the
+  function returns ERR_OK.
+
+  The pcb is deallocated by the TCP code after a call to tcp_close(). 
+
+- void tcp_abort(struct tcp_pcb *pcb)
+
+  Aborts the connection by sending a RST (reset) segment to the remote
+  host. The pcb is deallocated. This function never fails.
+
+  ATTENTION: When calling this from one of the TCP callbacks, make
+  sure you always return ERR_ABRT (and never return ERR_ABRT otherwise
+  or you will risk accessing deallocated memory or memory leaks!
+
+
+If a connection is aborted because of an error, the application is
+alerted of this event by the err callback. Errors that might abort a
+connection are when there is a shortage of memory. The callback
+function to be called is set using the tcp_err() function.
+
+- void tcp_err(struct tcp_pcb *pcb, void (* err)(void *arg,
+       err_t err))
+
+  The error callback function does not get the pcb passed to it as a
+  parameter since the pcb may already have been deallocated.
+
+
+--- Lower layer TCP interface
+
+TCP provides a simple interface to the lower layers of the
+system. During system initialization, the function tcp_init() has
+to be called before any other TCP function is called. When the system
+is running, the two timer functions tcp_fasttmr() and tcp_slowtmr()
+must be called with regular intervals. The tcp_fasttmr() should be
+called every TCP_FAST_INTERVAL milliseconds (defined in tcp.h) and
+tcp_slowtmr() should be called every TCP_SLOW_INTERVAL milliseconds. 
+
+
+--- UDP interface
+
+The UDP interface is similar to that of TCP, but due to the lower
+level of complexity of UDP, the interface is significantly simpler.
+
+- struct udp_pcb *udp_new(void)
+
+  Creates a new UDP pcb which can be used for UDP communication. The
+  pcb is not active until it has either been bound to a local address
+  or connected to a remote address.
+
+- void udp_remove(struct udp_pcb *pcb)
+
+  Removes and deallocates the pcb.  
+  
+- err_t udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port)
+
+  Binds the pcb to a local address. The IP-address argument "ipaddr"
+  can be IP_ADDR_ANY to indicate that it should listen to any local IP
+  address. The function currently always return ERR_OK.
+
+- err_t udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                    u16_t port)
+
+  Sets the remote end of the pcb. This function does not generate any
+  network traffic, but only set the remote address of the pcb.
+
+- err_t udp_disconnect(struct udp_pcb *pcb)
+
+  Remove the remote end of the pcb. This function does not generate
+  any network traffic, but only removes the remote address of the pcb.
+
+- err_t udp_send(struct udp_pcb *pcb, struct pbuf *p)
+
+  Sends the pbuf p. The pbuf is not deallocated.
+
+- void udp_recv(struct udp_pcb *pcb,
+                void (* recv)(void *arg, struct udp_pcb *upcb,
+                                         struct pbuf *p,
+                                         struct ip_addr *addr,
+                                         u16_t port),
+                              void *recv_arg)
+
+  Specifies a callback function that should be called when a UDP
+  datagram is received.
+  
+
+--- System initalization
+
+A truly complete and generic sequence for initializing the lwip stack
+cannot be given because it depends on the build configuration (lwipopts.h)
+and additional initializations for your runtime environment (e.g. timers).
+
+We can give you some idea on how to proceed when using the raw API.
+We assume a configuration using a single Ethernet netif and the
+UDP and TCP transport layers, IPv4 and the DHCP client.
+
+Call these functions in the order of appearance:
+
+- stats_init()
+
+  Clears the structure where runtime statistics are gathered.
+
+- sys_init()
+  
+  Not of much use since we set the NO_SYS 1 option in lwipopts.h,
+  to be called for easy configuration changes.
+
+- mem_init()
+
+  Initializes the dynamic memory heap defined by MEM_SIZE.
+
+- memp_init()
+
+  Initializes the memory pools defined by MEMP_NUM_x.
+
+- pbuf_init()
+
+  Initializes the pbuf memory pool defined by PBUF_POOL_SIZE.
+  
+- etharp_init()
+
+  Initializes the ARP table and queue.
+  Note: you must call etharp_tmr at a ARP_TMR_INTERVAL (5 seconds) regular interval
+  after this initialization.
+
+- ip_init()
+
+  Doesn't do much, it should be called to handle future changes.
+
+- udp_init()
+
+  Clears the UDP PCB list.
+
+- tcp_init()
+
+  Clears the TCP PCB list and clears some internal TCP timers.
+  Note: you must call tcp_fasttmr() and tcp_slowtmr() at the
+  predefined regular intervals after this initialization. 
+  
+- netif_add(struct netif *netif, struct ip_addr *ipaddr,
+            struct ip_addr *netmask, struct ip_addr *gw,
+            void *state, err_t (* init)(struct netif *netif),
+            err_t (* input)(struct pbuf *p, struct netif *netif))
+
+  Adds your network interface to the netif_list. Allocate a struct
+  netif and pass a pointer to this structure as the first argument.
+  Give pointers to cleared ip_addr structures when using DHCP,
+  or fill them with sane numbers otherwise. The state pointer may be NULL.
+
+  The init function pointer must point to a initialization function for
+  your ethernet netif interface. The following code illustrates it's use.
+  
+  err_t netif_if_init(struct netif *netif)
+  {
+    u8_t i;
+    
+    for(i = 0; i < ETHARP_HWADDR_LEN; i++) netif->hwaddr[i] = some_eth_addr[i];
+    init_my_eth_device();
+    return ERR_OK;
+  }
+  
+  For ethernet drivers, the input function pointer must point to the lwip
+  function ethernet_input() declared in "netif/etharp.h". Other drivers
+  must use ip_input() declared in "lwip/ip.h".
+  
+- netif_set_default(struct netif *netif)
+
+  Registers the default network interface.
+
+- netif_set_up(struct netif *netif)
+
+  When the netif is fully configured this function must be called.
+
+- dhcp_start(struct netif *netif)
+
+  Creates a new DHCP client for this interface on the first call.
+  Note: you must call dhcp_fine_tmr() and dhcp_coarse_tmr() at
+  the predefined regular intervals after starting the client.
+  
+  You can peek in the netif->dhcp struct for the actual DHCP status.
+
+
+--- Optimalization hints
+
+The first thing you want to optimize is the lwip_standard_checksum()
+routine from src/core/inet.c. You can override this standard
+function with the #define LWIP_CHKSUM .
+
+There are C examples given in inet.c or you might want to
+craft an assembly function for this. RFC1071 is a good
+introduction to this subject.
+
+Other significant improvements can be made by supplying
+assembly or inline replacements for htons() and htonl()
+if you're using a little-endian architecture.
+#define LWIP_PLATFORM_BYTESWAP 1
+#define LWIP_PLATFORM_HTONS(x) 
+#define LWIP_PLATFORM_HTONL(x) 
+
+Check your network interface driver if it reads at
+a higher speed than the maximum wire-speed. If the
+hardware isn't serviced frequently and fast enough
+buffer overflows are likely to occur.
+
+E.g. when using the cs8900 driver, call cs8900if_service(ethif)
+as frequently as possible. When using an RTOS let the cs8900 interrupt
+wake a high priority task that services your driver using a binary
+semaphore or event flag. Some drivers might allow additional tuning
+to match your application and network.
+
+For a production release it is recommended to set LWIP_STATS to 0.
+Note that speed performance isn't influenced much by simply setting
+high values to the memory options.
+
+For more optimization hints take a look at the lwIP wiki.
+
+--- Zero-copy MACs
+
+To achieve zero-copy on transmit, the data passed to the raw API must
+remain unchanged until sent. Because the send- (or write-)functions return
+when the packets have been enqueued for sending, data must be kept stable
+after that, too.
+
+This implies that PBUF_RAM/PBUF_POOL pbufs passed to raw-API send functions
+must *not* be reused by the application unless their ref-count is 1.
+
+For no-copy pbufs (PBUF_ROM/PBUF_REF), data must be kept unchanged, too,
+but the stack/driver will/must copy PBUF_REF'ed data when enqueueing, while
+PBUF_ROM-pbufs are just enqueued (as ROM-data is expected to never change).
+
+Also, data passed to tcp_write without the copy-flag must not be changed!
+
+Therefore, be careful which type of PBUF you use and if you copy TCP data
+or not!
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/doc/savannah.txt b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/doc/savannah.txt
new file mode 100644
index 0000000..409905b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/doc/savannah.txt
@@ -0,0 +1,135 @@
+Daily Use Guide for using Savannah for lwIP
+
+Table of Contents:
+
+1 - Obtaining lwIP from the CVS repository
+2 - Committers/developers CVS access using SSH (to be written)
+3 - Merging from DEVEL branch to main trunk (stable branch)
+4 - How to release lwIP
+
+
+
+1 Obtaining lwIP from the CVS repository
+----------------------------------------
+
+To perform an anonymous CVS checkout of the main trunk (this is where
+bug fixes and incremental enhancements occur), do this:
+
+cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout lwip
+ 
+Or, obtain a stable branch (updated with bug fixes only) as follows:
+cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \
+  -r STABLE-0_7 -d lwip-0.7 lwip
+
+Or, obtain a specific (fixed) release as follows:
+cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \
+  -r STABLE-0_7_0 -d lwip-0.7.0 lwip
+
+3 Committers/developers CVS access using SSH
+--------------------------------------------
+
+The Savannah server uses SSH (Secure Shell) protocol 2 authentication and encryption.
+As such, CVS commits to the server occur through a SSH tunnel for project members.
+To create a SSH2 key pair in UNIX-like environments, do this:
+
+ssh-keygen -t dsa
+
+Under Windows, a recommended SSH client is "PuTTY", freely available with good
+documentation and a graphic user interface. Use its key generator.
+
+Now paste the id_dsa.pub contents into your Savannah account public key list. Wait
+a while so that Savannah can update its configuration (This can take minutes).
+
+Try to login using SSH:
+
+ssh -v your_login@cvs.sv.gnu.org
+
+If it tells you:
+
+Authenticating with public key "your_key_name"...
+Server refused to allocate pty
+
+then you could login; Savannah refuses to give you a shell - which is OK, as we
+are allowed to use SSH for CVS only. Now, you should be able to do this:
+
+export CVS_RSH=ssh
+cvs -z3 -d:ext:your_login@cvs.sv.gnu.org:/sources/lwip co lwip
+ 
+after which you can edit your local files with bug fixes or new features and
+commit them. Make sure you know what you are doing when using CVS to make
+changes on the repository. If in doubt, ask on the lwip-members mailing list.
+
+(If SSH asks about authenticity of the host, you can check the key
+ fingerprint against http://savannah.nongnu.org/cvs/?group=lwip)
+
+
+3 Merging from DEVEL branch to main trunk (stable)
+--------------------------------------------------
+
+Merging is a delicate process in CVS and requires the
+following disciplined steps in order to prevent conflicts
+in the future. Conflicts can be hard to solve!
+
+Merging from branch A to branch B requires that the A branch
+has a tag indicating the previous merger. This tag is called
+'merged_from_A_to_B'. After merging, the tag is moved in the
+A branch to remember this merger for future merge actions.
+
+IMPORTANT: AFTER COMMITTING A SUCCESFUL MERGE IN THE
+REPOSITORY, THE TAG MUST BE SET ON THE SOURCE BRANCH OF THE
+MERGE ACTION (REPLACING EXISTING TAGS WITH THE SAME NAME).
+
+Merge all changes in DEVEL since our last merge to main:
+
+In the working copy of the main trunk:
+cvs update -P -jmerged_from_DEVEL_to_main -jDEVEL 
+
+(This will apply the changes between 'merged_from_DEVEL_to_main'
+and 'DEVEL' to your work set of files)
+
+We can now commit the merge result.
+cvs commit -R -m "Merged from DEVEL to main." 
+
+If this worked out OK, we now move the tag in the DEVEL branch
+to this merge point, so we can use this point for future merges:
+
+cvs rtag -F -r DEVEL merged_from_DEVEL_to_main lwip 
+
+4 How to release lwIP
+---------------------
+
+First, checkout a clean copy of the branch to be released. Tag this set with
+tag name "STABLE-0_6_3". (I use release number 0.6.3 throughout this example).
+
+Login CVS using pserver authentication, then export a clean copy of the
+tagged tree. Export is similar to a checkout, except that the CVS metadata
+is not created locally. 
+
+export CVS_RSH=ssh
+cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \
+  -r STABLE-0_6_3 -d lwip-0.6.3 lwip
+
+Archive this directory using tar, gzip'd, bzip2'd and zip'd.
+
+tar czvf lwip-0.6.3.tar.gz lwip-0.6.3
+tar cjvf lwip-0.6.3.tar.bz2 lwip-0.6.3
+zip -r lwip-0.6.3.zip lwip-0.6.3
+
+Now, sign the archives with a detached GPG binary signature as follows:
+
+gpg -b lwip-0.6.3.tar.gz
+gpg -b lwip-0.6.3.tar.bz2
+gpg -b lwip-0.6.3.zip
+
+Upload these files using anonymous FTP:
+ncftp ftp://savannah.gnu.org/incoming/savannah/lwip
+
+ncftp>mput *0.6.3.*
+
+Additionally, you may post a news item on Savannah, like this:
+
+A new 0.6.3 release is now available here:
+http://savannah.nongnu.org/files/?group=lwip&highlight=0.6.3
+
+You will have to submit this via the user News interface, then approve
+this via the Administrator News interface.
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/doc/snmp_agent.txt b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/doc/snmp_agent.txt
new file mode 100644
index 0000000..2653230
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/doc/snmp_agent.txt
@@ -0,0 +1,181 @@
+SNMPv1 agent for lwIP
+
+Author: Christiaan Simons
+
+This is a brief introduction how to use and configure the SNMP agent.
+Note the agent uses the raw-API UDP interface so you may also want to
+read rawapi.txt to gain a better understanding of the SNMP message handling.
+
+0 Agent Capabilities
+====================
+
+SNMPv1 per RFC1157
+  This is an old(er) standard but is still widely supported.
+  For SNMPv2c and v3 have a greater complexity and need many
+  more lines of code. IMHO this breaks the idea of "lightweight IP".
+
+  Note the S in SNMP stands for "Simple". Note that "Simple" is
+  relative. SNMP is simple compared to the complex ISO network
+  management protocols CMIP (Common Management Information Protocol)
+  and CMOT (CMip Over Tcp).
+
+MIB II per RFC1213
+  The standard lwIP stack management information base.
+  This is a required MIB, so this is always enabled.
+  When builing lwIP without TCP, the mib-2.tcp group is omitted.
+  The groups EGP, CMOT and transmission are disabled by default.
+  
+  Most mib-2 objects are not writable except:
+  sysName, sysLocation, sysContact, snmpEnableAuthenTraps.
+  Writing to or changing the ARP and IP address and route
+  tables is not possible.
+ 
+  Note lwIP has a very limited notion of IP routing. It currently
+  doen't have a route table and doesn't have a notion of the U,G,H flags.
+  Instead lwIP uses the interface list with only one default interface
+  acting as a single gateway interface (G) for the default route.
+
+  The agent returns a "virtual table" with the default route 0.0.0.0
+  for the default interface and network routes (no H) for each
+  network interface in the netif_list.
+  All routes are considered to be up (U).
+
+Loading additional MIBs
+  MIBs can only be added in compile-time, not in run-time.
+  There is no MIB compiler thus additional MIBs must be hand coded.
+
+Large SNMP message support
+  The packet decoding and encoding routines are designed
+  to use pbuf-chains. Larger payloads than the minimum
+  SNMP requirement of 484 octets are supported if the 
+  PBUF_POOL_SIZE and IP_REASS_BUFSIZE are set to match your
+  local requirement.
+
+1 Building the Agent
+====================
+
+First of all you'll need to add the following define
+to your local lwipopts.h:
+
+#define LWIP_SNMP               1
+
+and add the source files in lwip/src/core/snmp
+and some snmp headers in lwip/src/include/lwip to your makefile.
+
+Note you'll might need to adapt you network driver to update
+the mib2 variables for your interface.
+
+2 Running the Agent
+===================
+
+The following function calls must be made in your program to
+actually get the SNMP agent running.
+
+Before starting the agent you should supply pointers
+to non-volatile memory for sysContact, sysLocation,
+and snmpEnableAuthenTraps. You can do this by calling
+
+snmp_set_syscontact()
+snmp_set_syslocation()
+snmp_set_snmpenableauthentraps()
+
+Additionally you may want to set
+
+snmp_set_sysdescr()
+snmp_set_sysobjid() (if you have a private MIB)
+snmp_set_sysname()
+
+Also before starting the agent you need to setup
+one or more trap destinations using these calls:
+
+snmp_trap_dst_enable();
+snmp_trap_dst_ip_set();
+
+In the lwIP initialisation sequence call snmp_init() just after
+the call to udp_init().
+
+Exactly every 10 msec the SNMP uptime timestamp must be updated with
+snmp_inc_sysuptime(). You should call this from a timer interrupt
+or a timer signal handler depending on your runtime environment.
+
+An alternative way to update the SNMP uptime timestamp is to do a call like
+snmp_add_sysuptime(100) each 1000ms (which is bigger "step", but call to
+a lower frequency). Another one is to not call snmp_inc_sysuptime() or
+snmp_add_sysuptime(), and to define the SNMP_GET_SYSUPTIME(sysuptime) macro.
+This one is undefined by default in mib2.c. SNMP_GET_SYSUPTIME is called inside
+snmp_get_sysuptime(u32_t *value), and enable to change "sysuptime" value only
+when it's queried (any function which need "sysuptime" have to call
+snmp_get_sysuptime).
+
+
+3 Private MIBs
+==============
+
+If want to extend the agent with your own private MIB you'll need to
+add the following define to your local lwipopts.h:
+
+#define SNMP_PRIVATE_MIB        1
+
+You must provide the private_mib.h and associated files yourself.
+Note we don't have a "MIB compiler" that generates C source from a MIB,
+so you're required to do some serious coding if you enable this!
+
+Note the lwIP enterprise ID (26381) is assigned to the lwIP project,
+ALL OBJECT IDENTIFIERS LIVING UNDER THIS ID ARE ASSIGNED BY THE lwIP
+MAINTAINERS!
+
+If you need to create your own private MIB you'll need
+to apply for your own enterprise ID with IANA: http://www.iana.org/numbers.html 
+
+You can set it by passing a struct snmp_obj_id to the agent
+using snmp_set_sysobjid(&my_object_id), just before snmp_init().
+
+Note the object identifiers for thes MIB-2 and your private MIB
+tree must be kept in sorted ascending (lexicographical) order.
+This to ensure correct getnext operation.
+
+An example for a private MIB is part of the "minimal Unix" project:
+contrib/ports/unix/proj/minimal/lwip_prvmib.c
+
+The next chapter gives a more detailed description of the
+MIB-2 tree and the optional private MIB.
+
+4 The Gory Details
+==================
+
+4.0 Object identifiers and the MIB tree.
+
+We have three distinct parts for all object identifiers:
+
+The prefix
+  .iso.org.dod.internet
+
+the middle part 
+  .mgmt.mib-2.ip.ipNetToMediaTable.ipNetToMediaEntry.ipNetToMediaPhysAddress
+
+and the index part
+  .1.192.168.0.1
+
+Objects located above the .internet hierarchy aren't supported.
+Currently only the .mgmt sub-tree is available and
+when the SNMP_PRIVATE_MIB is enabled the .private tree
+becomes available too.
+
+Object identifiers from incoming requests are checked
+for a matching prefix, middle part and index part
+or are expanded(*) for GetNext requests with short
+or inexisting names in the request.
+(* we call this "expansion" but this also
+resembles the "auto-completion" operation)
+
+The middle part is usually located in ROM (const)
+to preserve precious RAM on small microcontrollers.
+However RAM location is possible for a dynamically
+changing private tree.
+
+The index part is handled by functions which in
+turn use dynamically allocated index trees from RAM.
+These trees are updated by e.g. the etharp code
+when new entries are made or removed form the ARP cache.
+
+/** @todo more gory details */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/doc/sys_arch.txt b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/doc/sys_arch.txt
new file mode 100644
index 0000000..38377b6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/doc/sys_arch.txt
@@ -0,0 +1,216 @@
+sys_arch interface for lwIP 0.6++
+
+Author: Adam Dunkels
+
+The operating system emulation layer provides a common interface
+between the lwIP code and the underlying operating system kernel. The
+general idea is that porting lwIP to new architectures requires only
+small changes to a few header files and a new sys_arch
+implementation. It is also possible to do a sys_arch implementation
+that does not rely on any underlying operating system.
+
+The sys_arch provides semaphores and mailboxes to lwIP. For the full
+lwIP functionality, multiple threads support can be implemented in the
+sys_arch, but this is not required for the basic lwIP
+functionality. Previous versions of lwIP required the sys_arch to
+implement timer scheduling as well but as of lwIP 0.5 this is
+implemented in a higher layer.
+
+In addition to the source file providing the functionality of sys_arch,
+the OS emulation layer must provide several header files defining
+macros used throughout lwip.  The files required and the macros they
+must define are listed below the sys_arch description.
+
+Semaphores can be either counting or binary - lwIP works with both
+kinds. Mailboxes are used for message passing and can be implemented
+either as a queue which allows multiple messages to be posted to a
+mailbox, or as a rendez-vous point where only one message can be
+posted at a time. lwIP works with both kinds, but the former type will
+be more efficient. A message in a mailbox is just a pointer, nothing
+more. 
+
+Semaphores are represented by the type "sys_sem_t" which is typedef'd
+in the sys_arch.h file. Mailboxes are equivalently represented by the
+type "sys_mbox_t". lwIP does not place any restrictions on how
+sys_sem_t or sys_mbox_t are represented internally.
+
+The following functions must be implemented by the sys_arch:
+
+- void sys_init(void)
+
+  Is called to initialize the sys_arch layer.
+
+- sys_sem_t sys_sem_new(u8_t count)
+
+  Creates and returns a new semaphore. The "count" argument specifies
+  the initial state of the semaphore.
+
+- void sys_sem_free(sys_sem_t sem)
+
+  Deallocates a semaphore.
+
+- void sys_sem_signal(sys_sem_t sem)
+
+  Signals a semaphore.
+
+- u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout)
+
+  Blocks the thread while waiting for the semaphore to be
+  signaled. If the "timeout" argument is non-zero, the thread should
+  only be blocked for the specified time (measured in
+  milliseconds). If the "timeout" argument is zero, the thread should be
+  blocked until the semaphore is signalled.
+
+  If the timeout argument is non-zero, the return value is the number of
+  milliseconds spent waiting for the semaphore to be signaled. If the
+  semaphore wasn't signaled within the specified time, the return value is
+  SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
+  (i.e., it was already signaled), the function may return zero.
+
+  Notice that lwIP implements a function with a similar name,
+  sys_sem_wait(), that uses the sys_arch_sem_wait() function.
+
+- sys_mbox_t sys_mbox_new(int size)
+
+  Creates an empty mailbox for maximum "size" elements. Elements stored
+  in mailboxes are pointers. You have to define macros "_MBOX_SIZE"
+  in your lwipopts.h, or ignore this parameter in your implementation
+  and use a default size.
+
+- void sys_mbox_free(sys_mbox_t mbox)
+
+  Deallocates a mailbox. If there are messages still present in the
+  mailbox when the mailbox is deallocated, it is an indication of a
+  programming error in lwIP and the developer should be notified.
+
+- void sys_mbox_post(sys_mbox_t mbox, void *msg)
+
+  Posts the "msg" to the mailbox. This function have to block until
+  the "msg" is really posted.
+
+- err_t sys_mbox_trypost(sys_mbox_t mbox, void *msg)
+
+  Try to post the "msg" to the mailbox. Returns ERR_MEM if this one
+  is full, else, ERR_OK if the "msg" is posted.
+
+- u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout)
+
+  Blocks the thread until a message arrives in the mailbox, but does
+  not block the thread longer than "timeout" milliseconds (similar to
+  the sys_arch_sem_wait() function). If "timeout" is 0, the thread should
+  be blocked until a message arrives. The "msg" argument is a result
+  parameter that is set by the function (i.e., by doing "*msg =
+  ptr"). The "msg" parameter maybe NULL to indicate that the message
+  should be dropped.
+
+  The return values are the same as for the sys_arch_sem_wait() function:
+  Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a
+  timeout.
+
+  Note that a function with a similar name, sys_mbox_fetch(), is
+  implemented by lwIP. 
+
+- u32_t sys_arch_mbox_tryfetch(sys_mbox_t mbox, void **msg)
+
+  This is similar to sys_arch_mbox_fetch, however if a message is not
+  present in the mailbox, it immediately returns with the code
+  SYS_MBOX_EMPTY. On success 0 is returned.
+
+  To allow for efficient implementations, this can be defined as a
+  function-like macro in sys_arch.h instead of a normal function. For
+  example, a naive implementation could be:
+    #define sys_arch_mbox_tryfetch(mbox,msg) \
+      sys_arch_mbox_fetch(mbox,msg,1)
+  although this would introduce unnecessary delays.
+  
+If threads are supported by the underlying operating system and if
+such functionality is needed in lwIP, the following function will have
+to be implemented as well:
+
+- sys_thread_t sys_thread_new(char *name, void (* thread)(void *arg), void *arg, int stacksize, int prio)
+
+  Starts a new thread named "name" with priority "prio" that will begin its
+  execution in the function "thread()". The "arg" argument will be passed as an
+  argument to the thread() function. The stack size to used for this thread is
+  the "stacksize" parameter. The id of the new thread is returned. Both the id
+  and the priority are system dependent.
+
+- sys_prot_t sys_arch_protect(void)
+
+  This optional function does a "fast" critical region protection and returns
+  the previous protection level. This function is only called during very short
+  critical regions. An embedded system which supports ISR-based drivers might
+  want to implement this function by disabling interrupts. Task-based systems
+  might want to implement this by using a mutex or disabling tasking. This
+  function should support recursive calls from the same task or interrupt. In
+  other words, sys_arch_protect() could be called while already protected. In
+  that case the return value indicates that it is already protected.
+
+  sys_arch_protect() is only required if your port is supporting an operating
+  system.
+
+- void sys_arch_unprotect(sys_prot_t pval)
+
+  This optional function does a "fast" set of critical region protection to the
+  value specified by pval. See the documentation for sys_arch_protect() for
+  more information. This function is only required if your port is supporting
+  an operating system.
+
+Note:
+
+Be carefull with using mem_malloc() in sys_arch. When malloc() refers to
+mem_malloc() you can run into a circular function call problem. In mem.c
+mem_init() tries to allcate a semaphore using mem_malloc, which of course
+can't be performed when sys_arch uses mem_malloc.
+
+-------------------------------------------------------------------------------
+Additional files required for the "OS support" emulation layer:
+-------------------------------------------------------------------------------
+
+cc.h       - Architecture environment, some compiler specific, some
+             environment specific (probably should move env stuff 
+             to sys_arch.h.)
+
+  Typedefs for the types used by lwip -
+    u8_t, s8_t, u16_t, s16_t, u32_t, s32_t, mem_ptr_t
+
+  Compiler hints for packing lwip's structures -
+    PACK_STRUCT_FIELD(x)
+    PACK_STRUCT_STRUCT
+    PACK_STRUCT_BEGIN
+    PACK_STRUCT_END
+
+  Platform specific diagnostic output -
+    LWIP_PLATFORM_DIAG(x)    - non-fatal, print a message.
+    LWIP_PLATFORM_ASSERT(x)  - fatal, print message and abandon execution.
+    Portability defines for printf formatters:
+    U16_F, S16_F, X16_F, U32_F, S32_F, X32_F, SZT_F
+
+  "lightweight" synchronization mechanisms -
+    SYS_ARCH_DECL_PROTECT(x) - declare a protection state variable.
+    SYS_ARCH_PROTECT(x)      - enter protection mode.
+    SYS_ARCH_UNPROTECT(x)    - leave protection mode.
+
+  If the compiler does not provide memset() this file must include a
+  definition of it, or include a file which defines it.
+
+  This file must either include a system-local  which defines
+  the standard *nix error codes, or it should #define LWIP_PROVIDE_ERRNO
+  to make lwip/arch.h define the codes which are used throughout.
+
+
+perf.h     - Architecture specific performance measurement.
+  Measurement calls made throughout lwip, these can be defined to nothing.
+    PERF_START               - start measuring something.
+    PERF_STOP(x)             - stop measuring something, and record the result.
+
+sys_arch.h - Tied to sys_arch.c
+
+  Arch dependent types for the following objects:
+    sys_sem_t, sys_mbox_t, sys_thread_t,
+  And, optionally:
+    sys_prot_t
+
+  Defines to set vars of sys_mbox_t and sys_sem_t to NULL.
+    SYS_MBOX_NULL NULL
+    SYS_SEM_NULL NULL
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/SP605_PHY.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/SP605_PHY.c
new file mode 100644
index 0000000..003af44
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/SP605_PHY.c
@@ -0,0 +1,163 @@
+/*
+ * Code provided by Xilinx.
+ */
+
+/* BSP includes. */
+#include "xemaclite.h"
+
+/* lwIP includes. */
+#include "lwip/opt.h"
+
+
+/* Advertisement control register. */
+#define ADVERTISE_10HALF		0x0020  /* Try for 10mbps half-duplex  */
+#define ADVERTISE_10FULL		0x0040  /* Try for 10mbps full-duplex  */
+#define ADVERTISE_100HALF		0x0080  /* Try for 100mbps half-duplex */
+#define ADVERTISE_100FULL		0x0100  /* Try for 100mbps full-duplex */
+#define ADVERTISE_100_AND_10	(ADVERTISE_10FULL | ADVERTISE_100FULL | ADVERTISE_10HALF | ADVERTISE_100HALF)
+
+/* PHY registers/offsets. */
+#define IEEE_CONTROL_REG_OFFSET					0
+#define IEEE_STATUS_REG_OFFSET					1
+#define IEEE_AUTONEGO_ADVERTISE_REG				4
+#define IEEE_PARTNER_ABILITIES_1_REG_OFFSET		5
+#define IEEE_PARTNER_ABILITIES_3_REG_OFFSET		10
+#define IEEE_1000_ADVERTISE_REG_OFFSET			9
+#define IEEE_CTRL_1GBPS_LINKSPEED_MASK			0x2040
+#define IEEE_CTRL_LINKSPEED_MASK				0x0040
+#define IEEE_CTRL_LINKSPEED_1000M				0x0040
+#define IEEE_CTRL_LINKSPEED_100M				0x2000
+#define IEEE_CTRL_LINKSPEED_10M					0x0000
+#define IEEE_CTRL_AUTONEGOTIATE_ENABLE			0x1000
+#define IEEE_STAT_AUTONEGOTIATE_CAPABLE			0x0008
+#define IEEE_STAT_AUTONEGOTIATE_COMPLETE		0x0020
+#define IEEE_STAT_AUTONEGOTIATE_RESTART			0x0200
+#define IEEE_STAT_1GBPS_EXTENSIONS				0x0100
+#define IEEE_AN3_ABILITY_MASK_1GBPS				0x0C00
+#define IEEE_AN1_ABILITY_MASK_100MBPS			0x0380
+#define IEEE_AN1_ABILITY_MASK_10MBPS			0x0060
+
+#define PHY_DETECT_REG							1
+#define PHY_DETECT_MASK							0x1808
+
+static int detect_phy_emaclite(XEmacLite *pxEMACLiteInstance);
+
+unsigned short vInitialisePHY( XEmacLite *pxEMACLiteInstance )
+{
+u16 control;
+u16 status;
+u16 partner_capabilities;
+u16 partner_capabilities_1000;
+u16 phylinkspeed;
+u32 phy_addr = detect_phy_emaclite(pxEMACLiteInstance);
+
+	/* Dont advertise PHY speed of 1000 Mbps */
+	XEmacLite_PhyWrite(pxEMACLiteInstance, phy_addr,
+				IEEE_1000_ADVERTISE_REG_OFFSET,
+				0);
+	/* Advertise PHY speed of 100 and 10 Mbps */
+	XEmacLite_PhyWrite(pxEMACLiteInstance, phy_addr,
+				IEEE_AUTONEGO_ADVERTISE_REG,
+				ADVERTISE_100_AND_10);
+
+	XEmacLite_PhyRead(pxEMACLiteInstance, phy_addr,
+				     IEEE_CONTROL_REG_OFFSET,
+				     &control);
+	control |= (IEEE_CTRL_AUTONEGOTIATE_ENABLE |
+					IEEE_STAT_AUTONEGOTIATE_RESTART);
+
+	XEmacLite_PhyWrite(pxEMACLiteInstance, phy_addr,
+				IEEE_CONTROL_REG_OFFSET,
+				control);
+
+	/* Read PHY control and status registers is successful. */
+	XEmacLite_PhyRead(pxEMACLiteInstance, phy_addr,
+				     IEEE_CONTROL_REG_OFFSET,
+				     &control);
+	XEmacLite_PhyRead(pxEMACLiteInstance, phy_addr,
+				     IEEE_STATUS_REG_OFFSET,
+				     &status);
+
+	if ((control & IEEE_CTRL_AUTONEGOTIATE_ENABLE) &&
+			(status & IEEE_STAT_AUTONEGOTIATE_CAPABLE)) {
+
+		while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {
+			XEmacLite_PhyRead(pxEMACLiteInstance, phy_addr,
+						     IEEE_STATUS_REG_OFFSET,
+						     &status);
+		}
+
+		XEmacLite_PhyRead(pxEMACLiteInstance, phy_addr,
+					     IEEE_PARTNER_ABILITIES_1_REG_OFFSET,
+					     &partner_capabilities);
+
+		if (status & IEEE_STAT_1GBPS_EXTENSIONS) {
+			XEmacLite_PhyRead(pxEMACLiteInstance, phy_addr,
+						     IEEE_PARTNER_ABILITIES_3_REG_OFFSET,
+						     &partner_capabilities_1000);
+			if (partner_capabilities_1000 & IEEE_AN3_ABILITY_MASK_1GBPS) return 1000;
+		}
+
+		if (partner_capabilities & IEEE_AN1_ABILITY_MASK_100MBPS) return 100;
+		if (partner_capabilities & IEEE_AN1_ABILITY_MASK_10MBPS) return 10;
+
+		xil_printf("%s: unknown PHY link speed, setting TEMAC speed to be 10 Mbps\r\n",
+				__FUNCTION__);
+		return 10;
+
+
+	} else {
+
+		/* Update TEMAC speed accordingly */
+		if (status & IEEE_STAT_1GBPS_EXTENSIONS) {
+
+			/* Get commanded link speed */
+			phylinkspeed = control & IEEE_CTRL_1GBPS_LINKSPEED_MASK;
+
+			switch (phylinkspeed) {
+				case (IEEE_CTRL_LINKSPEED_1000M):
+					return 1000;
+				case (IEEE_CTRL_LINKSPEED_100M):
+					return 100;
+				case (IEEE_CTRL_LINKSPEED_10M):
+					return 10;
+				default:
+					xil_printf("%s: unknown PHY link speed (%d), setting TEMAC speed to be 10 Mbps\r\n",
+							__FUNCTION__, phylinkspeed);
+					return 10;
+			}
+
+		} else {
+
+			return (control & IEEE_CTRL_LINKSPEED_MASK) ? 100 : 10;
+
+		}
+
+	}
+}
+
+
+static int detect_phy_emaclite(XEmacLite *pxEMACLiteInstance)
+{
+	u16 phy_reg;
+	u32 phy_addr;
+
+	for (phy_addr = 31; phy_addr > 0; phy_addr--) {
+		XEmacLite_PhyRead(pxEMACLiteInstance, phy_addr, PHY_DETECT_REG, &phy_reg);
+
+		if ((phy_reg != 0xFFFF) &&
+			((phy_reg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
+			/* Found a valid PHY address */
+			LWIP_DEBUGF(NETIF_DEBUG, ("XEMacLite detect_phy: PHY detected at address %d.\r\n", phy_addr));
+			LWIP_DEBUGF(NETIF_DEBUG, ("XEMacLite detect_phy: PHY detected.\r\n"));
+			return phy_addr;
+		}
+	}
+
+	LWIP_DEBUGF(NETIF_DEBUG, ("XEMacLite detect_phy: No PHY detected.  Assuming a PHY at address 0\r\n"));
+
+	/* default to zero */
+	return 0;
+}
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/ethernetif.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/ethernetif.c
new file mode 100644
index 0000000..1570c4b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/ethernetif.c
@@ -0,0 +1,474 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* BSP includes. */
+#include "xemaclite.h"
+#include "xintc_l.h"
+
+/* lwIP includes. */
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include 
+#include 
+#include "netif/etharp.h"
+
+/* Define those to better describe your network interface. */
+#define IFNAME0 'e'
+#define IFNAME1 'l'
+
+/* When a packet is ready to be sent, if it cannot be sent immediately then
+ * the task performing the transmit will block for netifTX_BUFFER_FREE_WAIT
+ * milliseconds.  It will do this a maximum of netifMAX_TX_ATTEMPTS before
+ * giving up.
+ */
+#define netifTX_BUFFER_FREE_WAIT	( ( TickType_t ) 2UL / portTICK_PERIOD_MS )
+#define netifMAX_TX_ATTEMPTS		( 5 )
+
+#define netifMAX_MTU 1500
+
+struct xEthernetIf
+{
+	struct eth_addr *ethaddr;
+	/* Add whatever per-interface state that is needed here. */
+};
+
+/*
+ * Copy the received data into a pbuf.
+ */
+static struct pbuf *prvLowLevelInput( const unsigned char * const pucInputData, unsigned short usDataLength );
+
+/*
+ * Send data from a pbuf to the hardware.
+ */
+static err_t prvLowLevelOutput( struct netif *pxNetIf, struct pbuf *p );
+
+/*
+ * Perform any hardware and/or driver initialisation necessary.
+ */
+static void prvLowLevelInit( struct netif *pxNetIf );
+
+/*
+ * Functions that get registered as the Rx and Tx interrupt handers
+ * respectively.
+ */
+static void prvRxHandler( void *pvNetIf );
+static void prvTxHandler( void *pvUnused );
+
+
+/*-----------------------------------------------------------*/
+
+/* The instance of the xEmacLite IP being used in this driver. */
+static XEmacLite xEMACInstance;
+
+/*-----------------------------------------------------------*/
+
+/**
+ * In this function, the hardware should be initialized.
+ * Called from ethernetif_init().
+ *
+ * @param pxNetIf the already initialized lwip network interface structure
+ *		for this etherpxNetIf
+ */
+static void prvLowLevelInit( struct netif *pxNetIf )
+{
+portBASE_TYPE xStatus;
+extern void vInitialisePHY( XEmacLite *xemaclitep );
+unsigned portBASE_TYPE uxOriginalPriority;
+
+	/* Hardware initialisation can take some time, so temporarily lower the
+	task priority to ensure other functionality is not adversely effected.
+	The priority will get raised again before this function exits. */
+	uxOriginalPriority = uxTaskPriorityGet( NULL );
+	vTaskPrioritySet( NULL, tskIDLE_PRIORITY );
+
+	/* set MAC hardware address length */
+	pxNetIf->hwaddr_len = ETHARP_HWADDR_LEN;
+
+	/* set MAC hardware address */
+	pxNetIf->hwaddr[ 0 ] = configMAC_ADDR0;
+	pxNetIf->hwaddr[ 1 ] = configMAC_ADDR1;
+	pxNetIf->hwaddr[ 2 ] = configMAC_ADDR2;
+	pxNetIf->hwaddr[ 3 ] = configMAC_ADDR3;
+	pxNetIf->hwaddr[ 4 ] = configMAC_ADDR4;
+	pxNetIf->hwaddr[ 5 ] = configMAC_ADDR5;
+
+	/* device capabilities */
+	pxNetIf->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
+
+	/* maximum transfer unit */
+	pxNetIf->mtu = netifMAX_MTU;
+
+	/* Broadcast capability */
+	pxNetIf->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
+
+	/* Initialize the mac */
+	xStatus = XEmacLite_Initialize( &xEMACInstance, XPAR_EMACLITE_0_DEVICE_ID );
+
+	if( xStatus == XST_SUCCESS )
+	{
+		/* Set mac address */
+		XEmacLite_SetMacAddress( &xEMACInstance, ( Xuint8* )( pxNetIf->hwaddr ) );
+
+		/* Flush any frames already received */
+		XEmacLite_FlushReceive( &xEMACInstance );
+
+		/* Set Rx, Tx interrupt handlers */
+		XEmacLite_SetRecvHandler( &xEMACInstance, ( void * ) pxNetIf, prvRxHandler );
+		XEmacLite_SetSendHandler( &xEMACInstance, NULL, prvTxHandler );
+
+		/* Enable Rx, Tx interrupts */
+		XEmacLite_EnableInterrupts( &xEMACInstance );
+
+		/* Install the standard Xilinx library interrupt handler itself.
+		*NOTE* The xPortInstallInterruptHandler() API function must be used
+		for	this purpose. */
+		xStatus = xPortInstallInterruptHandler( XPAR_INTC_0_EMACLITE_0_VEC_ID, ( XInterruptHandler ) XEmacLite_InterruptHandler, &xEMACInstance );
+
+		vInitialisePHY( &xEMACInstance );
+
+		/* Enable the interrupt in the interrupt controller.
+		*NOTE* The vPortEnableInterrupt() API function must be used for this
+		purpose. */
+		vPortEnableInterrupt( XPAR_INTC_0_EMACLITE_0_VEC_ID );
+	}
+
+	/* Reset the task priority back to its original value. */
+	vTaskPrioritySet( NULL, uxOriginalPriority );
+
+	configASSERT( xStatus == pdPASS );
+}
+
+/**
+ * This function should do the actual transmission of the packet. The packet is
+ * contained in the pbuf that is passed to the function. This pbuf
+ * might be chained.
+ *
+ * @param pxNetIf the lwip network interface structure for this etherpxNetIf
+ * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)
+ * @return ERR_OK if the packet could be sent
+ *		 an err_t value if the packet couldn't be sent
+ *
+ * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to
+ *	   strange results. You might consider waiting for space in the DMA queue
+ *	   to become availale since the stack doesn't retry to send a packet
+ *	   dropped because of memory failure (except for the TCP timers).
+ */
+
+static err_t prvLowLevelOutput( struct netif *pxNetIf, struct pbuf *p )
+{
+
+	/* This is taken from lwIP example code and therefore does not conform
+	to the FreeRTOS coding standard. */
+
+struct pbuf *q;
+static unsigned char ucBuffer[ 1520 ] __attribute__((aligned(32)));
+unsigned char *pucBuffer = ucBuffer;
+unsigned char *pucChar;
+struct eth_hdr *pxHeader;
+u16_t usTotalLength = p->tot_len - ETH_PAD_SIZE;
+err_t xReturn = ERR_OK;
+long x;
+
+	( void ) pxNetIf;
+
+	#if defined(LWIP_DEBUG) && LWIP_NETIF_TX_SINGLE_PBUF
+		LWIP_ASSERT("p->next == NULL && p->len == p->tot_len", p->next == NULL && p->len == p->tot_len);
+	#endif
+
+	/* Initiate transfer. */
+	if( p->len == p->tot_len ) 
+	{
+		/* No pbuf chain, don't have to copy -> faster. */
+		pucBuffer = &( ( unsigned char * ) p->payload )[ ETH_PAD_SIZE ];
+	} 
+	else 
+	{
+		/* pbuf chain, copy into contiguous ucBuffer. */
+		if( p->tot_len >= sizeof( ucBuffer ) )
+		{
+			LINK_STATS_INC( link.lenerr );
+			LINK_STATS_INC( link.drop );
+			snmp_inc_ifoutdiscards( pxNetIf );
+			xReturn = ERR_BUF;
+		}
+		else
+		{
+			pucChar = ucBuffer;
+
+			for( q = p; q != NULL; q = q->next )
+			{
+				/* Send the data from the pbuf to the interface, one pbuf at a
+				time. The size of the data in each pbuf is kept in the ->len
+				variable. */
+				/* send data from(q->payload, q->len); */
+				LWIP_DEBUGF( NETIF_DEBUG, ( "NETIF: send pucChar %p q->payload %p q->len %i q->next %p\n", pucChar, q->payload, ( int ) q->len, ( void* ) q->next ) );
+				if( q == p )
+				{
+					memcpy( pucChar, &( ( char * ) q->payload )[ ETH_PAD_SIZE ], q->len - ETH_PAD_SIZE );
+					pucChar += q->len - ETH_PAD_SIZE;
+				}
+				else
+				{
+					memcpy( pucChar, q->payload, q->len );
+					pucChar += q->len;
+				}
+			}
+		}
+	}
+
+	if( xReturn == ERR_OK )
+	{
+		for( x = 0; x < netifMAX_TX_ATTEMPTS; x++ )
+		{
+			xReturn =  XEmacLite_Send( &xEMACInstance, pucBuffer, ( int ) usTotalLength );
+			if( xReturn == XST_SUCCESS )
+			{
+				break;
+			}
+			else
+			{
+				vTaskDelay( netifTX_BUFFER_FREE_WAIT );
+			}
+		}
+
+		if( xReturn != XST_SUCCESS )
+		{
+			LINK_STATS_INC( link.memerr );
+			LINK_STATS_INC( link.drop );
+			snmp_inc_ifoutdiscards( pxNetIf );
+			xReturn = ERR_BUF;
+		}
+		else
+		{
+			LINK_STATS_INC( link.xmit );
+			snmp_add_ifoutoctets( pxNetIf, usTotalLength );
+			pxHeader = ( struct eth_hdr * )p->payload;
+
+			if( ( pxHeader->dest.addr[ 0 ] & 1 ) != 0 ) 
+			{
+				/* broadcast or multicast packet*/
+				snmp_inc_ifoutnucastpkts( pxNetIf );
+			} 
+			else 
+			{
+				/* unicast packet */
+				snmp_inc_ifoutucastpkts( pxNetIf );
+			}
+		}
+	}
+
+	return xReturn;
+}
+
+/**
+ * Should allocate a pbuf and transfer the bytes of the incoming
+ * packet from the interface into the pbuf.
+ *
+ * @param pxNetIf the lwip network interface structure for this etherpxNetIf
+ * @return a pbuf filled with the received packet (including MAC header)
+ *		 NULL on memory error
+ */
+static struct pbuf *prvLowLevelInput( const unsigned char * const pucInputData, unsigned short usDataLength )
+{
+struct pbuf *p = NULL, *q;
+
+	if( usDataLength > 0U )
+	{
+		#if ETH_PAD_SIZE
+			len += ETH_PAD_SIZE; /* allow room for Ethernet padding */
+		#endif
+
+		/* We allocate a pbuf chain of pbufs from the pool. */
+		p = pbuf_alloc( PBUF_RAW, usDataLength, PBUF_POOL );
+  
+		if( p != NULL ) 
+		{
+			#if ETH_PAD_SIZE
+				pbuf_header( p, -ETH_PAD_SIZE ); /* drop the padding word */
+			#endif
+
+			/* We iterate over the pbuf chain until we have read the entire
+			* packet into the pbuf. */
+			usDataLength = 0U;
+			for( q = p; q != NULL; q = q->next ) 
+			{
+				/* Read enough bytes to fill this pbuf in the chain. The
+				* available data in the pbuf is given by the q->len
+				* variable.
+				* This does not necessarily have to be a memcpy, you can also preallocate
+				* pbufs for a DMA-enabled MAC and after receiving truncate it to the
+				* actually received size. In this case, ensure the usTotalLength member of the
+				* pbuf is the sum of the chained pbuf len members.
+				*/
+				memcpy( q->payload, &( pucInputData[ usDataLength ] ), q->len );
+				usDataLength += q->len;
+			}
+
+			#if ETH_PAD_SIZE
+				pbuf_header( p, ETH_PAD_SIZE ); /* reclaim the padding word */
+			#endif
+
+			LINK_STATS_INC(link.recv);
+		}
+	}
+
+	return p;  
+}
+
+/**
+ * Should be called at the beginning of the program to set up the
+ * network interface. It calls the function prvLowLevelInit() to do the
+ * actual setup of the hardware.
+ *
+ * This function should be passed as a parameter to pxNetIf_add().
+ *
+ * @param pxNetIf the lwip network interface structure for this etherpxNetIf
+ * @return ERR_OK if the loopif is initialized
+ *		 ERR_MEM if private data couldn't be allocated
+ *		 any other err_t on error
+ */
+err_t ethernetif_init( struct netif *pxNetIf )
+{
+err_t xReturn = ERR_OK;
+
+	/* This is taken from lwIP example code and therefore does not conform
+	to the FreeRTOS coding standard. */
+	
+struct xEthernetIf *pxEthernetIf;
+
+	LWIP_ASSERT( "pxNetIf != NULL", ( pxNetIf != NULL ) );
+	
+	pxEthernetIf = mem_malloc( sizeof( struct xEthernetIf ) );
+	if( pxEthernetIf == NULL ) 
+	{
+		LWIP_DEBUGF(NETIF_DEBUG, ( "ethernetif_init: out of memory\n" ) );
+		xReturn = ERR_MEM;
+	}
+	else
+	{
+		#if LWIP_NETIF_HOSTNAME
+		{
+			/* Initialize interface hostname */
+			pxNetIf->hostname = "lwip";
+		}
+		#endif /* LWIP_NETIF_HOSTNAME */
+
+		pxNetIf->state = pxEthernetIf;
+		pxNetIf->name[ 0 ] = IFNAME0;
+		pxNetIf->name[ 1 ] = IFNAME1;
+
+		/* We directly use etharp_output() here to save a function call.
+		* You can instead declare your own function an call etharp_output()
+		* from it if you have to do some checks before sending (e.g. if link
+		* is available...) */
+		pxNetIf->output = etharp_output;
+		pxNetIf->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_IGMP;
+		pxNetIf->hwaddr_len = ETHARP_HWADDR_LEN;
+		pxNetIf->mtu = netifMAX_MTU;
+		pxNetIf->linkoutput = prvLowLevelOutput;
+
+		pxEthernetIf->ethaddr = ( struct eth_addr * ) &( pxNetIf->hwaddr[ 0 ] );
+
+		/* initialize the hardware */
+		prvLowLevelInit( pxNetIf );
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void prvRxHandler( void *pvNetIf )
+{
+	/* This is taken from lwIP example code and therefore does not conform
+	to the FreeRTOS coding standard. */
+
+struct eth_hdr *pxHeader;
+struct pbuf *p;
+unsigned short usInputLength;
+static unsigned char ucBuffer[ 1520 ] __attribute__((aligned(32)));
+extern portBASE_TYPE xInsideISR;
+struct netif *pxNetIf = ( struct netif * ) pvNetIf;
+
+	XIntc_AckIntr( XPAR_ETHERNET_LITE_BASEADDR, XPAR_ETHERNET_LITE_IP2INTC_IRPT_MASK );
+
+	/* Ensure the pbuf handling functions don't attempt to use critical
+	sections. */
+	xInsideISR++;
+
+	usInputLength = ( long ) XEmacLite_Recv( &xEMACInstance, ucBuffer );
+
+	/* move received packet into a new pbuf */
+	p = prvLowLevelInput( ucBuffer, usInputLength );
+
+	/* no packet could be read, silently ignore this */
+	if( p != NULL )
+	{
+		/* points to packet payload, which starts with an Ethernet header */
+		pxHeader = p->payload;
+
+		switch( htons( pxHeader->type ) )
+		{
+			/* IP or ARP packet? */
+			case ETHTYPE_IP:
+			case ETHTYPE_ARP:
+								/* full packet send to tcpip_thread to process */
+								if( pxNetIf->input( p, pxNetIf ) != ERR_OK )
+								{
+									LWIP_DEBUGF(NETIF_DEBUG, ( "ethernetif_input: IP input error\n" ) );
+									pbuf_free(p);
+									p = NULL;
+								}
+								break;
+
+			default:
+								pbuf_free( p );
+								p = NULL;
+			break;
+		}
+	}
+
+	xInsideISR--;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTxHandler( void *pvUnused )
+{
+	( void ) pvUnused;
+	XIntc_AckIntr( XPAR_ETHERNET_LITE_BASEADDR, XPAR_ETHERNET_LITE_IP2INTC_IRPT_MASK );
+}
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/bpstruct.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/bpstruct.h
new file mode 100644
index 0000000..1d81e3f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/bpstruct.h
@@ -0,0 +1 @@
+#pragma pack(push,1)
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/cc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/cc.h
new file mode 100644
index 0000000..4075cc2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/cc.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __ARCH_CC_H__
+#define __ARCH_CC_H__
+
+/* Include some files for defining library routines */
+#include  /* printf, fflush, FILE */
+#include  /* abort */
+
+
+
+/** @todo fix some warnings: don't use #pragma if compiling with cygwin gcc */
+#ifndef __GNUC__
+	#include 
+	#pragma warning (disable: 4244) /* disable conversion warning (implicit integer promotion!) */
+	#pragma warning (disable: 4127) /* conditional expression is constant */
+	#pragma warning (disable: 4996) /* 'strncpy' was declared deprecated */
+	#pragma warning (disable: 4103) /* structure packing changed by including file */
+#endif
+
+#define LWIP_PROVIDE_ERRNO
+
+/* Define generic types used in lwIP */
+typedef unsigned   char    u8_t;
+typedef signed     char    s8_t;
+typedef unsigned   short   u16_t;
+typedef signed     short   s16_t;
+typedef unsigned   long    u32_t;
+typedef signed     long    s32_t;
+
+typedef size_t mem_ptr_t;
+typedef u32_t sys_prot_t;
+
+/* Define (sn)printf formatters for these lwIP types */
+#define X8_F  "02x"
+#define U16_F "hu"
+#define S16_F "hd"
+#define X16_F "hx"
+#define U32_F "lu"
+#define S32_F "ld"
+#define X32_F "lx"
+#define SZT_F U32_F
+
+/* Compiler hints for packing structures */
+#define PACK_STRUCT_STRUCT __attribute__( (packed) )
+
+/* Plaform specific diagnostic output */
+#define LWIP_PLATFORM_DIAG(x)   do { printf x; } while(0)
+
+#define LWIP_PLATFORM_ASSERT(x) do { printf("Assertion \"%s\" failed at line %d in %s\n", \
+                                     x, __LINE__, __FILE__); fflush(NULL); abort(); } while(0)
+
+#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \
+  printf("Assertion \"%s\" failed at line %d in %s\n", message, __LINE__, __FILE__); \
+  fflush(NULL);handler;} } while(0)
+
+/* C runtime functions redefined */
+#define snprintf _snprintf
+
+u32_t dns_lookup_external_hosts_file(const char *name);
+
+#define LWIP_RAND() ((u32_t)rand())
+
+#endif /* __ARCH_CC_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/epstruct.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/epstruct.h
new file mode 100644
index 0000000..65898b5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/epstruct.h
@@ -0,0 +1 @@
+#pragma pack(pop)
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/perf.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/perf.h
new file mode 100644
index 0000000..089faca
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/perf.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __PERF_H__
+#define __PERF_H__
+
+#define PERF_START    /* null definition */
+#define PERF_STOP(x)  /* null definition */
+
+#endif /* __PERF_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/sys_arch.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/sys_arch.h
new file mode 100644
index 0000000..3fc3739
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/include/arch/sys_arch.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __ARCH_SYS_ARCH_H__
+#define __ARCH_SYS_ARCH_H__
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+
+#define SYS_MBOX_NULL					( ( QueueHandle_t ) NULL )
+#define SYS_SEM_NULL					( ( SemaphoreHandle_t ) NULL )
+#define SYS_DEFAULT_THREAD_STACK_DEPTH	configMINIMAL_STACK_SIZE
+
+typedef SemaphoreHandle_t sys_sem_t;
+typedef SemaphoreHandle_t sys_mutex_t;
+typedef QueueHandle_t sys_mbox_t;
+typedef TaskHandle_t sys_thread_t;
+
+#define sys_mbox_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE )
+#define sys_mbox_set_invalid( x ) ( ( *x ) = NULL )
+#define sys_sem_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE )
+#define sys_sem_set_invalid( x ) ( ( *x ) = NULL )
+
+
+#endif /* __ARCH_SYS_ARCH_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/sys_arch.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/sys_arch.c
new file mode 100644
index 0000000..fa1c20e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/sys_arch.c
@@ -0,0 +1,584 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+//*****************************************************************************
+//
+// Include OS functionality.
+//
+//*****************************************************************************
+
+/* ------------------------ System architecture includes ----------------------------- */
+#include "arch/sys_arch.h"
+
+/* ------------------------ lwIP includes --------------------------------- */
+#include "lwip/opt.h"
+
+#include "lwip/debug.h"
+#include "lwip/def.h"
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+#include "lwip/stats.h"
+
+/* Very crude mechanism used to determine if the critical section handling
+functions are being called from an interrupt context or not.  This relies on
+the interrupt handler setting this variable manually. */
+portBASE_TYPE xInsideISR = pdFALSE;
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_mbox_new
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Creates a new mailbox
+ * Inputs:
+ *      int size                -- Size of elements in the mailbox
+ * Outputs:
+ *      sys_mbox_t              -- Handle to new mailbox
+ *---------------------------------------------------------------------------*/
+err_t sys_mbox_new( sys_mbox_t *pxMailBox, int iSize )
+{
+err_t xReturn = ERR_MEM;
+
+	*pxMailBox = xQueueCreate( iSize, sizeof( void * ) );
+
+	if( *pxMailBox != NULL )
+	{
+		xReturn = ERR_OK;
+		SYS_STATS_INC_USED( mbox );
+	}
+
+	return xReturn;
+}
+
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_mbox_free
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Deallocates a mailbox. If there are messages still present in the
+ *      mailbox when the mailbox is deallocated, it is an indication of a
+ *      programming error in lwIP and the developer should be notified.
+ * Inputs:
+ *      sys_mbox_t mbox         -- Handle of mailbox
+ * Outputs:
+ *      sys_mbox_t              -- Handle to new mailbox
+ *---------------------------------------------------------------------------*/
+void sys_mbox_free( sys_mbox_t *pxMailBox )
+{
+unsigned long ulMessagesWaiting;
+
+	ulMessagesWaiting = uxQueueMessagesWaiting( *pxMailBox );
+	configASSERT( ( ulMessagesWaiting == 0 ) );
+
+	#if SYS_STATS
+	{
+		if( ulMessagesWaiting != 0UL )
+		{
+			SYS_STATS_INC( mbox.err );
+		}
+
+		SYS_STATS_DEC( mbox.used );
+	}
+	#endif /* SYS_STATS */
+
+	vQueueDelete( *pxMailBox );
+}
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_mbox_post
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Post the "msg" to the mailbox.
+ * Inputs:
+ *      sys_mbox_t mbox         -- Handle of mailbox
+ *      void *data              -- Pointer to data to post
+ *---------------------------------------------------------------------------*/
+void sys_mbox_post( sys_mbox_t *pxMailBox, void *pxMessageToPost )
+{
+	while( xQueueSendToBack( *pxMailBox, &pxMessageToPost, portMAX_DELAY ) != pdTRUE );
+}
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_mbox_trypost
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Try to post the "msg" to the mailbox.  Returns immediately with
+ *      error if cannot.
+ * Inputs:
+ *      sys_mbox_t mbox         -- Handle of mailbox
+ *      void *msg               -- Pointer to data to post
+ * Outputs:
+ *      err_t                   -- ERR_OK if message posted, else ERR_MEM
+ *                                  if not.
+ *---------------------------------------------------------------------------*/
+err_t sys_mbox_trypost( sys_mbox_t *pxMailBox, void *pxMessageToPost )
+{
+err_t xReturn;
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
+
+	if( xInsideISR != pdFALSE )
+	{
+		xReturn = xQueueSendFromISR( *pxMailBox, &pxMessageToPost, &xHigherPriorityTaskWoken );
+	}
+	else
+	{
+		xReturn = xQueueSend( *pxMailBox, &pxMessageToPost, ( TickType_t ) 0 );
+	}
+
+	if( xReturn == pdPASS )
+	{
+		xReturn = ERR_OK;
+	}
+	else
+	{
+		/* The queue was already full. */
+		xReturn = ERR_MEM;
+		SYS_STATS_INC( mbox.err );
+	}
+
+	return xReturn;
+}
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_arch_mbox_fetch
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Blocks the thread until a message arrives in the mailbox, but does
+ *      not block the thread longer than "timeout" milliseconds (similar to
+ *      the sys_arch_sem_wait() function). The "msg" argument is a result
+ *      parameter that is set by the function (i.e., by doing "*msg =
+ *      ptr"). The "msg" parameter maybe NULL to indicate that the message
+ *      should be dropped.
+ *
+ *      The return values are the same as for the sys_arch_sem_wait() function:
+ *      Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a
+ *      timeout.
+ *
+ *      Note that a function with a similar name, sys_mbox_fetch(), is
+ *      implemented by lwIP.
+ * Inputs:
+ *      sys_mbox_t mbox         -- Handle of mailbox
+ *      void **msg              -- Pointer to pointer to msg received
+ *      u32_t timeout           -- Number of milliseconds until timeout
+ * Outputs:
+ *      u32_t                   -- SYS_ARCH_TIMEOUT if timeout, else number
+ *                                  of milliseconds until received.
+ *---------------------------------------------------------------------------*/
+u32_t sys_arch_mbox_fetch( sys_mbox_t *pxMailBox, void **ppvBuffer, u32_t ulTimeOut )
+{
+void *pvDummy;
+TickType_t xStartTime, xEndTime, xElapsed;
+unsigned long ulReturn;
+
+	xStartTime = xTaskGetTickCount();
+
+	if( NULL == ppvBuffer )
+	{
+		ppvBuffer = &pvDummy;
+	}
+
+	if( ulTimeOut != 0UL )
+	{
+		configASSERT( xInsideISR == ( portBASE_TYPE ) 0 );
+
+		if( pdTRUE == xQueueReceive( *pxMailBox, &( *ppvBuffer ), ulTimeOut/ portTICK_PERIOD_MS ) )
+		{
+			xEndTime = xTaskGetTickCount();
+			xElapsed = ( xEndTime - xStartTime ) * portTICK_PERIOD_MS;
+
+			ulReturn = xElapsed;
+		}
+		else
+		{
+			/* Timed out. */
+			*ppvBuffer = NULL;
+			ulReturn = SYS_ARCH_TIMEOUT;
+		}
+	}
+	else
+	{
+		while( pdTRUE != xQueueReceive( *pxMailBox, &( *ppvBuffer ), portMAX_DELAY ) );
+		xEndTime = xTaskGetTickCount();
+		xElapsed = ( xEndTime - xStartTime ) * portTICK_PERIOD_MS;
+
+		if( xElapsed == 0UL )
+		{
+			xElapsed = 1UL;
+		}
+
+		ulReturn = xElapsed;
+	}
+
+	return ulReturn;
+}
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_arch_mbox_tryfetch
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Similar to sys_arch_mbox_fetch, but if message is not ready
+ *      immediately, we'll return with SYS_MBOX_EMPTY.  On success, 0 is
+ *      returned.
+ * Inputs:
+ *      sys_mbox_t mbox         -- Handle of mailbox
+ *      void **msg              -- Pointer to pointer to msg received
+ * Outputs:
+ *      u32_t                   -- SYS_MBOX_EMPTY if no messages.  Otherwise,
+ *                                  return ERR_OK.
+ *---------------------------------------------------------------------------*/
+u32_t sys_arch_mbox_tryfetch( sys_mbox_t *pxMailBox, void **ppvBuffer )
+{
+void *pvDummy;
+unsigned long ulReturn;
+long lResult;
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
+
+	if( ppvBuffer== NULL )
+	{
+		ppvBuffer = &pvDummy;
+	}
+
+	if( xInsideISR != pdFALSE )
+	{
+		lResult = xQueueReceiveFromISR( *pxMailBox, &( *ppvBuffer ), &xHigherPriorityTaskWoken );
+	}
+	else
+	{
+		lResult = xQueueReceive( *pxMailBox, &( *ppvBuffer ), 0UL );
+	}
+
+	if( lResult == pdPASS )
+	{
+		ulReturn = ERR_OK;
+	}
+	else
+	{
+		ulReturn = SYS_MBOX_EMPTY;
+	}
+
+	return ulReturn;
+}
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_sem_new
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Creates and returns a new semaphore. The "ucCount" argument specifies
+ *      the initial state of the semaphore.
+ *      NOTE: Currently this routine only creates counts of 1 or 0
+ * Inputs:
+ *      sys_mbox_t mbox         -- Handle of mailbox
+ *      u8_t ucCount              -- Initial ucCount of semaphore (1 or 0)
+ * Outputs:
+ *      sys_sem_t               -- Created semaphore or 0 if could not create.
+ *---------------------------------------------------------------------------*/
+err_t sys_sem_new( sys_sem_t *pxSemaphore, u8_t ucCount )
+{
+err_t xReturn = ERR_MEM;
+
+	vSemaphoreCreateBinary( ( *pxSemaphore ) );
+
+	if( *pxSemaphore != NULL )
+	{
+		if( ucCount == 0U )
+		{
+			xSemaphoreTake( *pxSemaphore, 1UL );
+		}
+
+		xReturn = ERR_OK;
+		SYS_STATS_INC_USED( sem );
+	}
+	else
+	{
+		SYS_STATS_INC( sem.err );
+	}
+
+	return xReturn;
+}
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_arch_sem_wait
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Blocks the thread while waiting for the semaphore to be
+ *      signaled. If the "timeout" argument is non-zero, the thread should
+ *      only be blocked for the specified time (measured in
+ *      milliseconds).
+ *
+ *      If the timeout argument is non-zero, the return value is the number of
+ *      milliseconds spent waiting for the semaphore to be signaled. If the
+ *      semaphore wasn't signaled within the specified time, the return value is
+ *      SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
+ *      (i.e., it was already signaled), the function may return zero.
+ *
+ *      Notice that lwIP implements a function with a similar name,
+ *      sys_sem_wait(), that uses the sys_arch_sem_wait() function.
+ * Inputs:
+ *      sys_sem_t sem           -- Semaphore to wait on
+ *      u32_t timeout           -- Number of milliseconds until timeout
+ * Outputs:
+ *      u32_t                   -- Time elapsed or SYS_ARCH_TIMEOUT.
+ *---------------------------------------------------------------------------*/
+u32_t sys_arch_sem_wait( sys_sem_t *pxSemaphore, u32_t ulTimeout )
+{
+TickType_t xStartTime, xEndTime, xElapsed;
+unsigned long ulReturn;
+
+	xStartTime = xTaskGetTickCount();
+
+	if( ulTimeout != 0UL )
+	{
+		if( xSemaphoreTake( *pxSemaphore, ulTimeout / portTICK_PERIOD_MS ) == pdTRUE )
+		{
+			xEndTime = xTaskGetTickCount();
+			xElapsed = (xEndTime - xStartTime) * portTICK_PERIOD_MS;
+			ulReturn = xElapsed;
+		}
+		else
+		{
+			ulReturn = SYS_ARCH_TIMEOUT;
+		}
+	}
+	else
+	{
+		while( xSemaphoreTake( *pxSemaphore, portMAX_DELAY ) != pdTRUE );
+		xEndTime = xTaskGetTickCount();
+		xElapsed = ( xEndTime - xStartTime ) * portTICK_PERIOD_MS;
+
+		if( xElapsed == 0UL )
+		{
+			xElapsed = 1UL;
+		}
+
+		ulReturn = xElapsed;
+	}
+
+	return ulReturn;
+}
+
+/** Create a new mutex
+ * @param mutex pointer to the mutex to create
+ * @return a new mutex */
+err_t sys_mutex_new( sys_mutex_t *pxMutex )
+{
+err_t xReturn = ERR_MEM;
+
+	*pxMutex = xSemaphoreCreateMutex();
+
+	if( *pxMutex != NULL )
+	{
+		xReturn = ERR_OK;
+		SYS_STATS_INC_USED( mutex );
+	}
+	else
+	{
+		SYS_STATS_INC( mutex.err );
+	}
+
+	return xReturn;
+}
+
+/** Lock a mutex
+ * @param mutex the mutex to lock */
+void sys_mutex_lock( sys_mutex_t *pxMutex )
+{
+	while( xSemaphoreTake( *pxMutex, portMAX_DELAY ) != pdPASS );
+}
+
+/** Unlock a mutex
+ * @param mutex the mutex to unlock */
+void sys_mutex_unlock(sys_mutex_t *pxMutex )
+{
+	xSemaphoreGive( *pxMutex );
+}
+
+
+/** Delete a semaphore
+ * @param mutex the mutex to delete */
+void sys_mutex_free( sys_mutex_t *pxMutex )
+{
+	SYS_STATS_DEC( mutex.used );
+	vQueueDelete( *pxMutex );
+}
+
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_sem_signal
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Signals (releases) a semaphore
+ * Inputs:
+ *      sys_sem_t sem           -- Semaphore to signal
+ *---------------------------------------------------------------------------*/
+void sys_sem_signal( sys_sem_t *pxSemaphore )
+{
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
+
+	if( xInsideISR != pdFALSE )
+	{
+		xSemaphoreGiveFromISR( *pxSemaphore, &xHigherPriorityTaskWoken );
+	}
+	else
+	{
+		xSemaphoreGive( *pxSemaphore );
+	}
+}
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_sem_free
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Deallocates a semaphore
+ * Inputs:
+ *      sys_sem_t sem           -- Semaphore to free
+ *---------------------------------------------------------------------------*/
+void sys_sem_free( sys_sem_t *pxSemaphore )
+{
+	SYS_STATS_DEC(sem.used);
+	vQueueDelete( *pxSemaphore );
+}
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_init
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Initialize sys arch
+ *---------------------------------------------------------------------------*/
+void sys_init(void)
+{
+}
+
+u32_t sys_now(void)
+{
+	return xTaskGetTickCount();
+}
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_thread_new
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Starts a new thread with priority "prio" that will begin its
+ *      execution in the function "thread()". The "arg" argument will be
+ *      passed as an argument to the thread() function. The id of the new
+ *      thread is returned. Both the id and the priority are system
+ *      dependent.
+ * Inputs:
+ *      char *name              -- Name of thread
+ *      void (* thread)(void *arg) -- Pointer to function to run.
+ *      void *arg               -- Argument passed into function
+ *      int stacksize           -- Required stack amount in bytes
+ *      int prio                -- Thread priority
+ * Outputs:
+ *      sys_thread_t            -- Pointer to per-thread timeouts.
+ *---------------------------------------------------------------------------*/
+sys_thread_t sys_thread_new( const char *pcName, void( *pxThread )( void *pvParameters ), void *pvArg, int iStackSize, int iPriority )
+{
+TaskHandle_t xCreatedTask;
+portBASE_TYPE xResult;
+sys_thread_t xReturn;
+
+	xResult = xTaskCreate( pxThread, pcName, iStackSize, pvArg, iPriority, &xCreatedTask );
+
+	if( xResult == pdPASS )
+	{
+		xReturn = xCreatedTask;
+	}
+	else
+	{
+		xReturn = NULL;
+	}
+
+	return xReturn;
+}
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_arch_protect
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      This optional function does a "fast" critical region protection and
+ *      returns the previous protection level. This function is only called
+ *      during very short critical regions. An embedded system which supports
+ *      ISR-based drivers might want to implement this function by disabling
+ *      interrupts. Task-based systems might want to implement this by using
+ *      a mutex or disabling tasking. This function should support recursive
+ *      calls from the same task or interrupt. In other words,
+ *      sys_arch_protect() could be called while already protected. In
+ *      that case the return value indicates that it is already protected.
+ *
+ *      sys_arch_protect() is only required if your port is supporting an
+ *      operating system.
+ * Outputs:
+ *      sys_prot_t              -- Previous protection level (not used here)
+ *---------------------------------------------------------------------------*/
+sys_prot_t sys_arch_protect( void )
+{
+	if( xInsideISR == pdFALSE )
+	{
+		taskENTER_CRITICAL();
+	}
+	return ( sys_prot_t ) 1;
+}
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_arch_unprotect
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      This optional function does a "fast" set of critical region
+ *      protection to the value specified by pval. See the documentation for
+ *      sys_arch_protect() for more information. This function is only
+ *      required if your port is supporting an operating system.
+ * Inputs:
+ *      sys_prot_t              -- Previous protection level (not used here)
+ *---------------------------------------------------------------------------*/
+void sys_arch_unprotect( sys_prot_t xValue )
+{
+	(void) xValue;
+	if( xInsideISR == pdFALSE )
+	{
+		taskEXIT_CRITICAL();
+	}
+}
+
+/*
+ * Prints an assertion messages and aborts execution.
+ */
+void sys_assert( const char *pcMessage )
+{
+	(void) pcMessage;
+
+	for (;;)
+	{
+	}
+}
+/*-------------------------------------------------------------------------*
+ * End of File:  sys_arch.c
+ *-------------------------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/Packet32.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/Packet32.h
new file mode 100644
index 0000000..1e0eacd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/Packet32.h
@@ -0,0 +1,359 @@
+/*
+ * Copyright (c) 1999 - 2005 NetGroup, Politecnico di Torino (Italy)
+ * Copyright (c) 2005 - 2007 CACE Technologies, Davis (California)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Politecnico di Torino, CACE Technologies 
+ * nor the names of its contributors may be used to endorse or promote 
+ * products derived from this software without specific prior written 
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** @ingroup packetapi
+ *  @{ 
+ */
+
+/** @defgroup packet32h Packet.dll definitions and data structures
+ *  Packet32.h contains the data structures and the definitions used by packet.dll.
+ *  The file is used both by the Win9x and the WinNTx versions of packet.dll, and can be included
+ *  by the applications that use the functions of this library
+ *  @{
+ */
+
+#ifndef __PACKET32
+#define __PACKET32
+
+#include 
+
+#ifdef HAVE_AIRPCAP_API
+#include 
+#else
+#if !defined(AIRPCAP_HANDLE__EAE405F5_0171_9592_B3C2_C19EC426AD34__DEFINED_)
+#define AIRPCAP_HANDLE__EAE405F5_0171_9592_B3C2_C19EC426AD34__DEFINED_
+typedef struct _AirpcapHandle *PAirpcapHandle;
+#endif /* AIRPCAP_HANDLE__EAE405F5_0171_9592_B3C2_C19EC426AD34__DEFINED_ */
+#endif /* HAVE_AIRPCAP_API */
+
+#ifdef HAVE_DAG_API
+#include 
+#endif /* HAVE_DAG_API */
+
+// Working modes
+#define PACKET_MODE_CAPT 0x0 ///< Capture mode
+#define PACKET_MODE_STAT 0x1 ///< Statistical mode
+#define PACKET_MODE_MON 0x2 ///< Monitoring mode
+#define PACKET_MODE_DUMP 0x10 ///< Dump mode
+#define PACKET_MODE_STAT_DUMP MODE_DUMP | MODE_STAT ///< Statistical dump Mode
+
+
+/// Alignment macro. Defines the alignment size.
+#define Packet_ALIGNMENT sizeof(int)
+/// Alignment macro. Rounds up to the next even multiple of Packet_ALIGNMENT. 
+#define Packet_WORDALIGN(x) (((x)+(Packet_ALIGNMENT-1))&~(Packet_ALIGNMENT-1))
+
+#define NdisMediumNull	-1		///< Custom linktype: NDIS doesn't provide an equivalent
+#define NdisMediumCHDLC	-2		///< Custom linktype: NDIS doesn't provide an equivalent
+#define NdisMediumPPPSerial	-3	///< Custom linktype: NDIS doesn't provide an equivalent
+#define NdisMediumBare80211	-4	///< Custom linktype: NDIS doesn't provide an equivalent
+#define NdisMediumRadio80211	-5	///< Custom linktype: NDIS doesn't provide an equivalent
+#define NdisMediumPpi		-6	///< Custom linktype: NDIS doesn't provide an equivalent
+
+// Loopback behaviour definitions
+#define NPF_DISABLE_LOOPBACK	1	///< Drop the packets sent by the NPF driver
+#define NPF_ENABLE_LOOPBACK		2	///< Capture the packets sent by the NPF driver
+
+/*!
+  \brief Network type structure.
+
+  This structure is used by the PacketGetNetType() function to return information on the current adapter's type and speed.
+*/
+typedef struct NetType
+{
+	UINT LinkType;	///< The MAC of the current network adapter (see function PacketGetNetType() for more information)
+	ULONGLONG LinkSpeed;	///< The speed of the network in bits per second
+}NetType;
+
+
+//some definitions stolen from libpcap
+
+#ifndef BPF_MAJOR_VERSION
+
+/*!
+  \brief A BPF pseudo-assembly program.
+
+  The program will be injected in the kernel by the PacketSetBPF() function and applied to every incoming packet. 
+*/
+struct bpf_program 
+{
+	UINT bf_len;				///< Indicates the number of instructions of the program, i.e. the number of struct bpf_insn that will follow.
+	struct bpf_insn *bf_insns;	///< A pointer to the first instruction of the program.
+};
+
+/*!
+  \brief A single BPF pseudo-instruction.
+
+  bpf_insn contains a single instruction for the BPF register-machine. It is used to send a filter program to the driver.
+*/
+struct bpf_insn 
+{
+	USHORT	code;		///< Instruction type and addressing mode.
+	UCHAR 	jt;			///< Jump if true
+	UCHAR 	jf;			///< Jump if false
+	int k;				///< Generic field used for various purposes.
+};
+
+/*!
+  \brief Structure that contains a couple of statistics values on the current capture.
+
+  It is used by packet.dll to return statistics about a capture session.
+*/
+struct bpf_stat 
+{
+	UINT bs_recv;		///< Number of packets that the driver received from the network adapter 
+						///< from the beginning of the current capture. This value includes the packets 
+						///< lost by the driver.
+	UINT bs_drop;		///< number of packets that the driver lost from the beginning of a capture. 
+						///< Basically, a packet is lost when the the buffer of the driver is full. 
+						///< In this situation the packet cannot be stored and the driver rejects it.
+	UINT ps_ifdrop;		///< drops by interface. XXX not yet supported
+	UINT bs_capt;		///< number of packets that pass the filter, find place in the kernel buffer and
+						///< thus reach the application.
+};
+
+/*!
+  \brief Packet header.
+
+  This structure defines the header associated with every packet delivered to the application.
+*/
+struct bpf_hdr 
+{
+	struct timeval	bh_tstamp;	///< The timestamp associated with the captured packet. 
+								///< It is stored in a TimeVal structure.
+	UINT	bh_caplen;			///< Length of captured portion. The captured portion can be different
+								///< from the original packet, because it is possible (with a proper filter)
+								///< to instruct the driver to capture only a portion of the packets.
+	UINT	bh_datalen;			///< Original length of packet
+	USHORT		bh_hdrlen;		///< Length of bpf header (this struct plus alignment padding). In some cases,
+								///< a padding could be added between the end of this structure and the packet
+								///< data for performance reasons. This filed can be used to retrieve the actual data 
+								///< of the packet.
+};
+
+/*!
+  \brief Dump packet header.
+
+  This structure defines the header associated with the packets in a buffer to be used with PacketSendPackets().
+  It is simpler than the bpf_hdr, because it corresponds to the header associated by WinPcap and libpcap to a
+  packet in a dump file. This makes straightforward sending WinPcap dump files to the network.
+*/
+struct dump_bpf_hdr{
+    struct timeval	ts;			///< Time stamp of the packet
+    UINT			caplen;		///< Length of captured portion. The captured portion can smaller than the 
+								///< the original packet, because it is possible (with a proper filter) to 
+								///< instruct the driver to capture only a portion of the packets. 
+    UINT			len;		///< Length of the original packet (off wire).
+};
+
+
+#endif
+
+struct bpf_stat;
+
+#define        DOSNAMEPREFIX   TEXT("Packet_")	///< Prefix added to the adapters device names to create the WinPcap devices
+#define        MAX_LINK_NAME_LENGTH	64			//< Maximum length of the devices symbolic links
+#define        NMAX_PACKET 65535
+
+/*!
+  \brief Addresses of a network adapter.
+
+  This structure is used by the PacketGetNetInfoEx() function to return the IP addresses associated with 
+  an adapter.
+*/
+typedef struct npf_if_addr {
+	struct sockaddr_storage IPAddress;	///< IP address.
+	struct sockaddr_storage SubnetMask;	///< Netmask for that address.
+	struct sockaddr_storage Broadcast;	///< Broadcast address.
+}npf_if_addr;
+
+
+#define ADAPTER_NAME_LENGTH 256 + 12	///<  Maximum length for the name of an adapter. The value is the same used by the IP Helper API.
+#define ADAPTER_DESC_LENGTH 128			///<  Maximum length for the description of an adapter. The value is the same used by the IP Helper API.
+#define MAX_MAC_ADDR_LENGTH 8			///<  Maximum length for the link layer address of an adapter. The value is the same used by the IP Helper API.
+#define MAX_NETWORK_ADDRESSES 16		///<  Maximum length for the link layer address of an adapter. The value is the same used by the IP Helper API.
+
+
+typedef struct WAN_ADAPTER_INT WAN_ADAPTER; ///< Describes an opened wan (dialup, VPN...) network adapter using the NetMon API
+typedef WAN_ADAPTER *PWAN_ADAPTER; ///< Describes an opened wan (dialup, VPN...) network adapter using the NetMon API
+
+#define INFO_FLAG_NDIS_ADAPTER		0	///< Flag for ADAPTER_INFO: this is a traditional ndis adapter
+#define INFO_FLAG_NDISWAN_ADAPTER	1	///< Flag for ADAPTER_INFO: this is a NdisWan adapter, and it's managed by WANPACKET
+#define INFO_FLAG_DAG_CARD			2	///< Flag for ADAPTER_INFO: this is a DAG card
+#define INFO_FLAG_DAG_FILE			6	///< Flag for ADAPTER_INFO: this is a DAG file
+#define INFO_FLAG_DONT_EXPORT		8	///< Flag for ADAPTER_INFO: when this flag is set, the adapter will not be listed or openend by winpcap. This allows to prevent exporting broken network adapters, like for example FireWire ones.
+#define INFO_FLAG_AIRPCAP_CARD		16	///< Flag for ADAPTER_INFO: this is an airpcap card
+#define INFO_FLAG_NPFIM_DEVICE		32
+
+/*!
+  \brief Describes an opened network adapter.
+
+  This structure is the most important for the functioning of packet.dll, but the great part of its fields
+  should be ignored by the user, since the library offers functions that avoid to cope with low-level parameters
+*/
+typedef struct _ADAPTER  { 
+	HANDLE hFile;				///< \internal Handle to an open instance of the NPF driver.
+	CHAR  SymbolicLink[MAX_LINK_NAME_LENGTH]; ///< \internal A string containing the name of the network adapter currently opened.
+	int NumWrites;				///< \internal Number of times a packets written on this adapter will be repeated 
+								///< on the wire.
+	HANDLE ReadEvent;			///< A notification event associated with the read calls on the adapter.
+								///< It can be passed to standard Win32 functions (like WaitForSingleObject
+								///< or WaitForMultipleObjects) to wait until the driver's buffer contains some 
+								///< data. It is particularly useful in GUI applications that need to wait 
+								///< concurrently on several events. In Windows NT/2000 the PacketSetMinToCopy()
+								///< function can be used to define the minimum amount of data in the kernel buffer
+								///< that will cause the event to be signalled. 
+	
+	UINT ReadTimeOut;			///< \internal The amount of time after which a read on the driver will be released and 
+								///< ReadEvent will be signaled, also if no packets were captured
+	CHAR Name[ADAPTER_NAME_LENGTH];
+	PWAN_ADAPTER pWanAdapter;
+	UINT Flags;					///< Adapter's flags. Tell if this adapter must be treated in a different way, using the Netmon API or the dagc API.
+
+#ifdef HAVE_AIRPCAP_API
+	PAirpcapHandle	AirpcapAd;
+#endif // HAVE_AIRPCAP_API
+
+#ifdef HAVE_NPFIM_API
+	void* NpfImHandle;
+#endif // HAVE_NPFIM_API
+
+#ifdef HAVE_DAG_API
+	dagc_t *pDagCard;			///< Pointer to the dagc API adapter descriptor for this adapter
+	PCHAR DagBuffer;			///< Pointer to the buffer with the packets that is received from the DAG card
+	struct timeval DagReadTimeout;	///< Read timeout. The dagc API requires a timeval structure
+	unsigned DagFcsLen;			///< Length of the frame check sequence attached to any packet by the card. Obtained from the registry
+	DWORD DagFastProcess;		///< True if the user requests fast capture processing on this card. Higher level applications can use this value to provide a faster but possibly unprecise capture (for example, libpcap doesn't convert the timestamps).
+#endif // HAVE_DAG_API
+}  ADAPTER, *LPADAPTER;
+
+/*!
+  \brief Structure that contains a group of packets coming from the driver.
+
+  This structure defines the header associated with every packet delivered to the application.
+*/
+typedef struct _PACKET {  
+	HANDLE       hEvent;		///< \deprecated Still present for compatibility with old applications.
+	OVERLAPPED   OverLapped;	///< \deprecated Still present for compatibility with old applications.
+	PVOID        Buffer;		///< Buffer with containing the packets. See the PacketReceivePacket() for
+								///< details about the organization of the data in this buffer
+	UINT         Length;		///< Length of the buffer
+	DWORD        ulBytesReceived;	///< Number of valid bytes present in the buffer, i.e. amount of data
+									///< received by the last call to PacketReceivePacket()
+	BOOLEAN      bIoComplete;	///< \deprecated Still present for compatibility with old applications.
+}  PACKET, *LPPACKET;
+
+/*!
+  \brief Structure containing an OID request.
+
+  It is used by the PacketRequest() function to send an OID to the interface card driver. 
+  It can be used, for example, to retrieve the status of the error counters on the adapter, its MAC address, 
+  the list of the multicast groups defined on it, and so on.
+*/
+struct _PACKET_OID_DATA {
+    ULONG Oid;					///< OID code. See the Microsoft DDK documentation or the file ntddndis.h
+								///< for a complete list of valid codes.
+    ULONG Length;				///< Length of the data field
+    UCHAR Data[1];				///< variable-lenght field that contains the information passed to or received 
+								///< from the adapter.
+}; 
+typedef struct _PACKET_OID_DATA PACKET_OID_DATA, *PPACKET_OID_DATA;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ *  @}
+ */
+
+/*
+BOOLEAN QueryWinPcapRegistryStringA(CHAR *SubKeyName,
+								 CHAR *Value,
+								 UINT *pValueLen,
+								 CHAR *DefaultVal);
+
+BOOLEAN QueryWinPcapRegistryStringW(WCHAR *SubKeyName,
+								 WCHAR *Value,
+								 UINT *pValueLen,
+								 WCHAR *DefaultVal);
+*/
+								 
+//---------------------------------------------------------------------------
+// EXPORTED FUNCTIONS
+//---------------------------------------------------------------------------
+
+PCHAR PacketGetVersion();
+PCHAR PacketGetDriverVersion();
+BOOLEAN PacketSetMinToCopy(LPADAPTER AdapterObject,int nbytes);
+BOOLEAN PacketSetNumWrites(LPADAPTER AdapterObject,int nwrites);
+BOOLEAN PacketSetMode(LPADAPTER AdapterObject,int mode);
+BOOLEAN PacketSetReadTimeout(LPADAPTER AdapterObject,int timeout);
+BOOLEAN PacketSetBpf(LPADAPTER AdapterObject,struct bpf_program *fp);
+BOOLEAN PacketSetLoopbackBehavior(LPADAPTER  AdapterObject, UINT LoopbackBehavior);
+INT PacketSetSnapLen(LPADAPTER AdapterObject,int snaplen);
+BOOLEAN PacketGetStats(LPADAPTER AdapterObject,struct bpf_stat *s);
+BOOLEAN PacketGetStatsEx(LPADAPTER AdapterObject,struct bpf_stat *s);
+BOOLEAN PacketSetBuff(LPADAPTER AdapterObject,int dim);
+BOOLEAN PacketGetNetType (LPADAPTER AdapterObject,NetType *type);
+LPADAPTER PacketOpenAdapter(PCHAR AdapterName);
+BOOLEAN PacketSendPacket(LPADAPTER AdapterObject,LPPACKET pPacket,BOOLEAN Sync);
+INT PacketSendPackets(LPADAPTER AdapterObject,PVOID PacketBuff,ULONG Size, BOOLEAN Sync);
+LPPACKET PacketAllocatePacket(void);
+VOID PacketInitPacket(LPPACKET lpPacket,PVOID  Buffer,UINT  Length);
+VOID PacketFreePacket(LPPACKET lpPacket);
+BOOLEAN PacketReceivePacket(LPADAPTER AdapterObject,LPPACKET lpPacket,BOOLEAN Sync);
+BOOLEAN PacketSetHwFilter(LPADAPTER AdapterObject,ULONG Filter);
+BOOLEAN PacketGetAdapterNames(PTSTR pStr,PULONG  BufferSize);
+BOOLEAN PacketGetNetInfoEx(PCHAR AdapterName, npf_if_addr* buffer, PLONG NEntries);
+BOOLEAN PacketRequest(LPADAPTER  AdapterObject,BOOLEAN Set,PPACKET_OID_DATA  OidData);
+HANDLE PacketGetReadEvent(LPADAPTER AdapterObject);
+BOOLEAN PacketSetDumpName(LPADAPTER AdapterObject, void *name, int len);
+BOOLEAN PacketSetDumpLimits(LPADAPTER AdapterObject, UINT maxfilesize, UINT maxnpacks);
+BOOLEAN PacketIsDumpEnded(LPADAPTER AdapterObject, BOOLEAN sync);
+BOOL PacketStopDriver();
+VOID PacketCloseAdapter(LPADAPTER lpAdapter);
+BOOLEAN PacketStartOem(PCHAR errorString, UINT errorStringLength);
+BOOLEAN PacketStartOemEx(PCHAR errorString, UINT errorStringLength, ULONG flags);
+PAirpcapHandle PacketGetAirPcapHandle(LPADAPTER AdapterObject);
+
+//
+// Used by PacketStartOemEx
+//
+#define PACKET_START_OEM_NO_NETMON	0x00000001
+
+#ifdef __cplusplus
+}
+#endif 
+
+#endif //__PACKET32
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/PacketData.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/PacketData.h
new file mode 100644
index 0000000..8124db6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/PacketData.h
@@ -0,0 +1,267 @@
+char pkt1[] = {
+0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14,
+0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00,
+0x00, 0x30, 0x09, 0x9c, 0x40, 0x00, 0x80, 0x06,
+0x6f, 0x07, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8,
+0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7,
+0xc7, 0x35, 0x00, 0x00, 0x00, 0x00, 0x70, 0x02,
+0x40, 0x00, 0xdf, 0xab, 0x00, 0x00, 0x02, 0x04,
+0x05, 0xb4, 0x01, 0x01, 0x04, 0x02 };
+
+char pkt2[] = {
+0x00, 0x14, 0x22, 0xcb, 0x18, 0x2d, 0x00, 0x01,
+0x02, 0x45, 0x09, 0x11, 0x08, 0x00, 0x45, 0x00,
+0x00, 0x2c, 0x00, 0x01, 0x00, 0x00, 0x40, 0x06,
+0xf8, 0xa6, 0xc0, 0xa8, 0x00, 0x0c, 0xc0, 0xa8,
+0x00, 0xc8, 0x00, 0x50, 0x0f, 0xe2, 0x00, 0x00,
+0x06, 0x68, 0x09, 0xe7, 0xc7, 0x36, 0x60, 0x12,
+0x05, 0x92, 0x28, 0xca, 0x00, 0x00, 0x02, 0x04,
+0x05, 0x92 };
+
+char pkt3[] = {
+0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14,
+0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00,
+0x00, 0x28, 0x09, 0x9e, 0x40, 0x00, 0x80, 0x06,
+0x6f, 0x0d, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8,
+0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7,
+0xc7, 0x36, 0x00, 0x00, 0x06, 0x69, 0x50, 0x10,
+0x42, 0xd8, 0x82, 0x3f, 0x00, 0x00 };
+
+char pkt4[] = {
+0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14,
+0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00,
+0x02, 0x27, 0x09, 0x9f, 0x40, 0x00, 0x80, 0x06,
+0x6d, 0x0d, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8,
+0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7,
+0xc7, 0x36, 0x00, 0x00, 0x06, 0x69, 0x50, 0x18,
+0x42, 0xd8, 0x84, 0x3e, 0x00, 0x00, 0x47, 0x45,
+0x54, 0x20, 0x2f, 0x20, 0x48, 0x54, 0x54, 0x50,
+0x2f, 0x31, 0x2e, 0x31, 0x0d, 0x0a, 0x41, 0x63,
+0x63, 0x65, 0x70, 0x74, 0x3a, 0x20, 0x69, 0x6d,
+0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0x2c,
+0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x78,
+0x2d, 0x78, 0x62, 0x69, 0x74, 0x6d, 0x61, 0x70,
+0x2c, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f,
+0x6a, 0x70, 0x65, 0x67, 0x2c, 0x20, 0x69, 0x6d,
+0x61, 0x67, 0x65, 0x2f, 0x70, 0x6a, 0x70, 0x65,
+0x67, 0x2c, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69,
+0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x76,
+0x6e, 0x64, 0x2e, 0x6d, 0x73, 0x2d, 0x65, 0x78,
+0x63, 0x65, 0x6c, 0x2c, 0x20, 0x61, 0x70, 0x70,
+0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e,
+0x2f, 0x6d, 0x73, 0x77, 0x6f, 0x72, 0x64, 0x2c,
+0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61,
+0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x76, 0x6e, 0x64,
+0x2e, 0x6d, 0x73, 0x2d, 0x70, 0x6f, 0x77, 0x65,
+0x72, 0x70, 0x6f, 0x69, 0x6e, 0x74, 0x2c, 0x20,
+0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74,
+0x69, 0x6f, 0x6e, 0x2f, 0x78, 0x2d, 0x6d, 0x73,
+0x2d, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61,
+0x74, 0x69, 0x6f, 0x6e, 0x2c, 0x20, 0x61, 0x70,
+0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f,
+0x6e, 0x2f, 0x78, 0x2d, 0x6d, 0x73, 0x2d, 0x78,
+0x62, 0x61, 0x70, 0x2c, 0x20, 0x61, 0x70, 0x70,
+0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e,
+0x2f, 0x76, 0x6e, 0x64, 0x2e, 0x6d, 0x73, 0x2d,
+0x78, 0x70, 0x73, 0x64, 0x6f, 0x63, 0x75, 0x6d,
+0x65, 0x6e, 0x74, 0x2c, 0x20, 0x61, 0x70, 0x70,
+0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e,
+0x2f, 0x78, 0x61, 0x6d, 0x6c, 0x2b, 0x78, 0x6d,
+0x6c, 0x2c, 0x20, 0x2a, 0x2f, 0x2a, 0x0d, 0x0a,
+0x41, 0x63, 0x63, 0x65, 0x70, 0x74, 0x2d, 0x4c,
+0x61, 0x6e, 0x67, 0x75, 0x61, 0x67, 0x65, 0x3a,
+0x20, 0x65, 0x6e, 0x2d, 0x67, 0x62, 0x0d, 0x0a,
+0x41, 0x63, 0x63, 0x65, 0x70, 0x74, 0x2d, 0x45,
+0x6e, 0x63, 0x6f, 0x64, 0x69, 0x6e, 0x67, 0x3a,
+0x20, 0x67, 0x7a, 0x69, 0x70, 0x2c, 0x20, 0x64,
+0x65, 0x66, 0x6c, 0x61, 0x74, 0x65, 0x0d, 0x0a,
+0x55, 0x73, 0x65, 0x72, 0x2d, 0x41, 0x67, 0x65,
+0x6e, 0x74, 0x3a, 0x20, 0x4d, 0x6f, 0x7a, 0x69,
+0x6c, 0x6c, 0x61, 0x2f, 0x34, 0x2e, 0x30, 0x20,
+0x28, 0x63, 0x6f, 0x6d, 0x70, 0x61, 0x74, 0x69,
+0x62, 0x6c, 0x65, 0x3b, 0x20, 0x4d, 0x53, 0x49,
+0x45, 0x20, 0x36, 0x2e, 0x30, 0x3b, 0x20, 0x57,
+0x69, 0x6e, 0x64, 0x6f, 0x77, 0x73, 0x20, 0x4e,
+0x54, 0x20, 0x35, 0x2e, 0x31, 0x3b, 0x20, 0x53,
+0x56, 0x31, 0x3b, 0x20, 0x47, 0x6f, 0x6f, 0x67,
+0x6c, 0x65, 0x54, 0x35, 0x3b, 0x20, 0x2e, 0x4e,
+0x45, 0x54, 0x20, 0x43, 0x4c, 0x52, 0x20, 0x32,
+0x2e, 0x30, 0x2e, 0x35, 0x30, 0x37, 0x32, 0x37,
+0x3b, 0x20, 0x2e, 0x4e, 0x45, 0x54, 0x20, 0x43,
+0x4c, 0x52, 0x20, 0x33, 0x2e, 0x30, 0x2e, 0x30,
+0x34, 0x35, 0x30, 0x36, 0x2e, 0x36, 0x34, 0x38,
+0x3b, 0x20, 0x2e, 0x4e, 0x45, 0x54, 0x20, 0x43,
+0x4c, 0x52, 0x20, 0x33, 0x2e, 0x35, 0x2e, 0x32,
+0x31, 0x30, 0x32, 0x32, 0x29, 0x0d, 0x0a, 0x48,
+0x6f, 0x73, 0x74, 0x3a, 0x20, 0x31, 0x39, 0x32,
+0x2e, 0x31, 0x36, 0x38, 0x2e, 0x30, 0x2e, 0x31,
+0x32, 0x0d, 0x0a, 0x43, 0x6f, 0x6e, 0x6e, 0x65,
+0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x4b,
+0x65, 0x65, 0x70, 0x2d, 0x41, 0x6c, 0x69, 0x76,
+0x65, 0x0d, 0x0a, 0x0d, 0x0a };
+
+char pkt5[] = {
+0x00, 0x14, 0x22, 0xcb, 0x18, 0x2d, 0x00, 0x01,
+0x02, 0x45, 0x09, 0x11, 0x08, 0x00, 0x45, 0x00,
+0x00, 0x2c, 0x00, 0x02, 0x00, 0x00, 0x40, 0x06,
+0xf8, 0xa5, 0xc0, 0xa8, 0x00, 0x0c, 0xc0, 0xa8,
+0x00, 0xc8, 0x00, 0x50, 0x0f, 0xe2, 0x00, 0x00,
+0x06, 0x68, 0x09, 0xe7, 0xc7, 0x36, 0x60, 0x12,
+0x05, 0x92, 0x28, 0xca, 0x00, 0x00, 0x02, 0x04,
+0x05, 0x92 };
+
+char pkt6[] = {
+0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14,
+0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00,
+0x00, 0x28, 0x09, 0xa1, 0x40, 0x00, 0x80, 0x06,
+0x6f, 0x0a, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8,
+0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7,
+0xc9, 0x35, 0x00, 0x00, 0x06, 0x69, 0x50, 0x10,
+0x42, 0xd8, 0x82, 0x3f, 0x00, 0x00 };
+
+char pkt7[] = {
+0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14,
+0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00,
+0x02, 0x27, 0x09, 0xa2, 0x40, 0x00, 0x80, 0x06,
+0x6d, 0x0a, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8,
+0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7,
+0xc7, 0x36, 0x00, 0x00, 0x06, 0x69, 0x50, 0x18,
+0x42, 0xd8, 0x84, 0x3e, 0x00, 0x00, 0x47, 0x45,
+0x54, 0x20, 0x2f, 0x20, 0x48, 0x54, 0x54, 0x50,
+0x2f, 0x31, 0x2e, 0x31, 0x0d, 0x0a, 0x41, 0x63,
+0x63, 0x65, 0x70, 0x74, 0x3a, 0x20, 0x69, 0x6d,
+0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0x2c,
+0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x78,
+0x2d, 0x78, 0x62, 0x69, 0x74, 0x6d, 0x61, 0x70,
+0x2c, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f,
+0x6a, 0x70, 0x65, 0x67, 0x2c, 0x20, 0x69, 0x6d,
+0x61, 0x67, 0x65, 0x2f, 0x70, 0x6a, 0x70, 0x65,
+0x67, 0x2c, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69,
+0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x76,
+0x6e, 0x64, 0x2e, 0x6d, 0x73, 0x2d, 0x65, 0x78,
+0x63, 0x65, 0x6c, 0x2c, 0x20, 0x61, 0x70, 0x70,
+0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e,
+0x2f, 0x6d, 0x73, 0x77, 0x6f, 0x72, 0x64, 0x2c,
+0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61,
+0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x76, 0x6e, 0x64,
+0x2e, 0x6d, 0x73, 0x2d, 0x70, 0x6f, 0x77, 0x65,
+0x72, 0x70, 0x6f, 0x69, 0x6e, 0x74, 0x2c, 0x20,
+0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74,
+0x69, 0x6f, 0x6e, 0x2f, 0x78, 0x2d, 0x6d, 0x73,
+0x2d, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61,
+0x74, 0x69, 0x6f, 0x6e, 0x2c, 0x20, 0x61, 0x70,
+0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f,
+0x6e, 0x2f, 0x78, 0x2d, 0x6d, 0x73, 0x2d, 0x78,
+0x62, 0x61, 0x70, 0x2c, 0x20, 0x61, 0x70, 0x70,
+0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e,
+0x2f, 0x76, 0x6e, 0x64, 0x2e, 0x6d, 0x73, 0x2d,
+0x78, 0x70, 0x73, 0x64, 0x6f, 0x63, 0x75, 0x6d,
+0x65, 0x6e, 0x74, 0x2c, 0x20, 0x61, 0x70, 0x70,
+0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e,
+0x2f, 0x78, 0x61, 0x6d, 0x6c, 0x2b, 0x78, 0x6d,
+0x6c, 0x2c, 0x20, 0x2a, 0x2f, 0x2a, 0x0d, 0x0a,
+0x41, 0x63, 0x63, 0x65, 0x70, 0x74, 0x2d, 0x4c,
+0x61, 0x6e, 0x67, 0x75, 0x61, 0x67, 0x65, 0x3a,
+0x20, 0x65, 0x6e, 0x2d, 0x67, 0x62, 0x0d, 0x0a,
+0x41, 0x63, 0x63, 0x65, 0x70, 0x74, 0x2d, 0x45,
+0x6e, 0x63, 0x6f, 0x64, 0x69, 0x6e, 0x67, 0x3a,
+0x20, 0x67, 0x7a, 0x69, 0x70, 0x2c, 0x20, 0x64,
+0x65, 0x66, 0x6c, 0x61, 0x74, 0x65, 0x0d, 0x0a,
+0x55, 0x73, 0x65, 0x72, 0x2d, 0x41, 0x67, 0x65,
+0x6e, 0x74, 0x3a, 0x20, 0x4d, 0x6f, 0x7a, 0x69,
+0x6c, 0x6c, 0x61, 0x2f, 0x34, 0x2e, 0x30, 0x20,
+0x28, 0x63, 0x6f, 0x6d, 0x70, 0x61, 0x74, 0x69,
+0x62, 0x6c, 0x65, 0x3b, 0x20, 0x4d, 0x53, 0x49,
+0x45, 0x20, 0x36, 0x2e, 0x30, 0x3b, 0x20, 0x57,
+0x69, 0x6e, 0x64, 0x6f, 0x77, 0x73, 0x20, 0x4e,
+0x54, 0x20, 0x35, 0x2e, 0x31, 0x3b, 0x20, 0x53,
+0x56, 0x31, 0x3b, 0x20, 0x47, 0x6f, 0x6f, 0x67,
+0x6c, 0x65, 0x54, 0x35, 0x3b, 0x20, 0x2e, 0x4e,
+0x45, 0x54, 0x20, 0x43, 0x4c, 0x52, 0x20, 0x32,
+0x2e, 0x30, 0x2e, 0x35, 0x30, 0x37, 0x32, 0x37,
+0x3b, 0x20, 0x2e, 0x4e, 0x45, 0x54, 0x20, 0x43,
+0x4c, 0x52, 0x20, 0x33, 0x2e, 0x30, 0x2e, 0x30,
+0x34, 0x35, 0x30, 0x36, 0x2e, 0x36, 0x34, 0x38,
+0x3b, 0x20, 0x2e, 0x4e, 0x45, 0x54, 0x20, 0x43,
+0x4c, 0x52, 0x20, 0x33, 0x2e, 0x35, 0x2e, 0x32,
+0x31, 0x30, 0x32, 0x32, 0x29, 0x0d, 0x0a, 0x48,
+0x6f, 0x73, 0x74, 0x3a, 0x20, 0x31, 0x39, 0x32,
+0x2e, 0x31, 0x36, 0x38, 0x2e, 0x30, 0x2e, 0x31,
+0x32, 0x0d, 0x0a, 0x43, 0x6f, 0x6e, 0x6e, 0x65,
+0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x4b,
+0x65, 0x65, 0x70, 0x2d, 0x41, 0x6c, 0x69, 0x76,
+0x65, 0x0d, 0x0a, 0x0d, 0x0a };
+
+char pkt8[] = {
+0x00, 0x14, 0x22, 0xcb, 0x18, 0x2d, 0x00, 0x01,
+0x02, 0x45, 0x09, 0x11, 0x08, 0x00, 0x45, 0x00,
+0x00, 0x2c, 0x00, 0x03, 0x00, 0x00, 0x40, 0x06,
+0xf8, 0xa4, 0xc0, 0xa8, 0x00, 0x0c, 0xc0, 0xa8,
+0x00, 0xc8, 0x00, 0x50, 0x0f, 0xe2, 0x00, 0x00,
+0x06, 0x68, 0x09, 0xe7, 0xc7, 0x36, 0x60, 0x12,
+0x05, 0x92, 0x28, 0xca, 0x00, 0x00, 0x02, 0x04,
+0x05, 0x92 };
+
+char pkt9[] = {
+0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14,
+0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00,
+0x00, 0x28, 0x09, 0xa3, 0x40, 0x00, 0x80, 0x06,
+0x6f, 0x08, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8,
+0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7,
+0xc9, 0x35, 0x00, 0x00, 0x06, 0x69, 0x50, 0x10,
+0x42, 0xd8, 0x82, 0x3f, 0x00, 0x00 };
+
+char pkt10[] = {
+0x00, 0x14, 0x22, 0xcb, 0x18, 0x2d, 0x00, 0x01,
+0x02, 0x45, 0x09, 0x11, 0x08, 0x00, 0x45, 0x00,
+0x00, 0x2c, 0x00, 0x04, 0x00, 0x00, 0x40, 0x06,
+0xf8, 0xa3, 0xc0, 0xa8, 0x00, 0x0c, 0xc0, 0xa8,
+0x00, 0xc8, 0x00, 0x50, 0x0f, 0xe2, 0x00, 0x00,
+0x06, 0x68, 0x09, 0xe7, 0xc7, 0x36, 0x60, 0x12,
+0x05, 0x92, 0x28, 0xca, 0x00, 0x00, 0x02, 0x04,
+0x05, 0x92 };
+
+char pkt11[] = {
+0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14,
+0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00,
+0x00, 0x28, 0x09, 0xa6, 0x40, 0x00, 0x80, 0x06,
+0x6f, 0x05, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8,
+0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7,
+0xc9, 0x35, 0x00, 0x00, 0x06, 0x69, 0x50, 0x10,
+0x42, 0xd8, 0x82, 0x3f, 0x00, 0x00 };
+
+char pkt12[] = {
+0x00, 0x01, 0x02, 0x45, 0x09, 0x11, 0x00, 0x14,
+0x22, 0xcb, 0x18, 0x2d, 0x08, 0x00, 0x45, 0x00,
+0x00, 0x28, 0x09, 0xa7, 0x40, 0x00, 0x80, 0x06,
+0x6f, 0x04, 0xc0, 0xa8, 0x00, 0xc8, 0xc0, 0xa8,
+0x00, 0x0c, 0x0f, 0xe2, 0x00, 0x50, 0x09, 0xe7,
+0xc9, 0x35, 0x00, 0x00, 0x06, 0x69, 0x50, 0x14,
+0x00, 0x00, 0x43, 0xf4, 0x00, 0x00 };
+
+
+typedef struct
+{
+	char *pcData;
+	int iDataLen;
+} xPacketData;
+
+xPacketData xAllPackets[] =
+{
+	{ pkt1, sizeof( pkt1 ) },
+//	{ pkt2, sizeof( pkt2 ) },
+	{ pkt3, sizeof( pkt3 ) },
+	{ pkt4, sizeof( pkt4 ) },
+//	{ pkt5, sizeof( pkt5 ) },
+	{ pkt6, sizeof( pkt6 ) },
+	{ pkt7, sizeof( pkt7 ) },
+	{ pkt8, sizeof( pkt8 ) },
+	{ pkt9, sizeof( pkt9 ) },
+	{ pkt10, sizeof( pkt10 ) },
+//	{ pkt11, sizeof( pkt11 ) },
+//	{ pkt12, sizeof( pkt12 ) },
+//	{ pkt13, sizeof( pkt13 ) },
+//	{ pkt14, sizeof( pkt14 ) },
+//	{ pkt15, sizeof( pkt15 ) },
+//	{ pkt16, sizeof( pkt16 ) },
+};
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/Win32-Extensions.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/Win32-Extensions.h
new file mode 100644
index 0000000..d3b063b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/Win32-Extensions.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 1999 - 2005 NetGroup, Politecnico di Torino (Italy)
+ * Copyright (c) 2005 - 2006 CACE Technologies, Davis (California)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Politecnico di Torino, CACE Technologies 
+ * nor the names of its contributors may be used to endorse or promote 
+ * products derived from this software without specific prior written 
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __WIN32_EXTENSIONS_H__
+#define __WIN32_EXTENSIONS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Definitions */
+
+/*!
+  \brief A queue of raw packets that will be sent to the network with pcap_sendqueue_transmit().
+*/
+struct pcap_send_queue
+{
+	u_int maxlen;		///< Maximum size of the the queue, in bytes. This variable contains the size of the buffer field.
+	u_int len;			///< Current size of the queue, in bytes.
+	char *buffer;		///< Buffer containing the packets to be sent.
+};
+
+typedef struct pcap_send_queue pcap_send_queue;
+
+/*!
+  \brief This typedef is a support for the pcap_get_airpcap_handle() function
+*/
+#if !defined(AIRPCAP_HANDLE__EAE405F5_0171_9592_B3C2_C19EC426AD34__DEFINED_)
+#define AIRPCAP_HANDLE__EAE405F5_0171_9592_B3C2_C19EC426AD34__DEFINED_
+typedef struct _AirpcapHandle *PAirpcapHandle;
+#endif
+
+#define		BPF_MEM_EX_IMM	0xc0
+#define		BPF_MEM_EX_IND	0xe0
+
+/*used for ST*/
+#define		BPF_MEM_EX		0xc0
+#define		BPF_TME					0x08
+
+#define		BPF_LOOKUP				0x90   
+#define		BPF_EXECUTE				0xa0
+#define		BPF_INIT				0xb0
+#define		BPF_VALIDATE			0xc0
+#define		BPF_SET_ACTIVE			0xd0
+#define		BPF_RESET				0xe0
+#define		BPF_SET_MEMORY			0x80
+#define		BPF_GET_REGISTER_VALUE	0x70
+#define		BPF_SET_REGISTER_VALUE	0x60
+#define		BPF_SET_WORKING			0x50
+#define		BPF_SET_ACTIVE_READ		0x40
+#define		BPF_SET_AUTODELETION	0x30
+#define		BPF_SEPARATION			0xff
+
+/* Prototypes */
+pcap_send_queue* pcap_sendqueue_alloc(u_int memsize);
+
+void pcap_sendqueue_destroy(pcap_send_queue* queue);
+
+int pcap_sendqueue_queue(pcap_send_queue* queue, const struct pcap_pkthdr *pkt_header, const u_char *pkt_data);
+
+u_int pcap_sendqueue_transmit(pcap_t *p, pcap_send_queue* queue, int sync);
+
+HANDLE pcap_getevent(pcap_t *p);
+
+struct pcap_stat *pcap_stats_ex(pcap_t *p, int *pcap_stat_size);
+
+int pcap_setuserbuffer(pcap_t *p, int size);
+
+int pcap_live_dump(pcap_t *p, char *filename, int maxsize, int maxpacks);
+
+int pcap_live_dump_ended(pcap_t *p, int sync);
+
+int pcap_offline_filter(struct bpf_program *prog, const struct pcap_pkthdr *header, const u_char *pkt_data);
+
+int pcap_start_oem(char* err_str, int flags);
+
+PAirpcapHandle pcap_get_airpcap_handle(pcap_t *p);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__WIN32_EXTENSIONS_H__
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/arch.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/arch.c
new file mode 100644
index 0000000..7b2ffba
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/arch.c
@@ -0,0 +1,336 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* WinPCap includes. */
+#include "pcap.h"
+#include "remote-ext.h"
+
+/* uIP includes. */
+#include "net/uip.h"
+#include "net/uip_arp.h"
+#include "net/clock-arch.h"
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/*
+ * Query the computer the simulation is being executed on to find the network
+ * interfaces it has installed.
+ */
+static pcap_if_t * prvPrintAvailableNetworkInterfaces( void );
+
+/*
+ * Open the network interface.  The number of the interface to be opened is set
+ * by the configNETWORK_INTERFACE_TO_USE constant in FreeRTOSConfig.h.
+ */
+static void prvOpenSelectedNetworkInterface( pcap_if_t *pxAllNetworkInterfaces );
+
+/*
+ * Configure the capture filter to allow blocking reads, and to filter out
+ * packets that are not of interest to this demo.
+ */
+static void prvConfigureCaptureBehaviour( void );
+
+pcap_t *pxOpenedInterfaceHandle = NULL;
+LARGE_INTEGER freq, sys_start_time;
+
+#define archNUM_BUFFERS	5
+#define archNUM_BUFFER_POINTERS ( archNUM_BUFFERS - 1 )
+
+static void prvInterruptSimulator( void *pvParameters );
+
+static unsigned char ucEthernetBuffer[ archNUM_BUFFERS ][ UIP_CONF_BUFFER_SIZE ];
+static unsigned char *pucEthernetBufferPointers[ archNUM_BUFFER_POINTERS ];
+
+static long lLengthOfDataInBuffer[ archNUM_BUFFER_POINTERS ] = { 0 };
+static unsigned char ucNextBufferToFill = 0U, ucNextBufferToProcess = 0U;
+
+unsigned char *uip_buf = NULL;
+char cErrorBuffer[PCAP_ERRBUF_SIZE];
+
+void vNetifTx( void )
+{
+	pcap_sendpacket( pxOpenedInterfaceHandle, uip_buf, uip_len );
+	pcap_sendpacket( pxOpenedInterfaceHandle, uip_buf, uip_len );
+}
+/*-----------------------------------------------------------*/
+
+unsigned portBASE_TYPE uxNetifRx( void )
+{
+unsigned portBASE_TYPE xDataLen;
+unsigned char *pucTemp;
+
+	/* Check there is really data available. */
+	xDataLen = lLengthOfDataInBuffer[ ucNextBufferToProcess ];
+	if( xDataLen != 0L )
+	{
+
+		/* The buffer pointed to by uip_buf is going to change.  Remember which
+		buffer uip_buf is currently pointing to. */
+		pucTemp = uip_buf;
+
+		/* Point uip_buf at the next buffer that contains data. */
+		uip_buf = pucEthernetBufferPointers[ ucNextBufferToProcess ];
+
+		/* The buffer pointed to by 
+		pucEthernetBufferPointeres[ ucNextBufferToProcess ] is now in use by
+		uip_buf, but the buffer uip_buf was pointing to on entry to this
+		function is free.  Set 
+		pucEthernetBufferPointeres[ ucNextBufferToProcess ] to the free 
+		buffer. */
+		pucEthernetBufferPointers[ ucNextBufferToProcess ] = pucTemp;
+		lLengthOfDataInBuffer[ ucNextBufferToProcess ] = 0L;
+
+		ucNextBufferToProcess++;
+		if( ucNextBufferToProcess >= archNUM_BUFFER_POINTERS )
+		{
+			ucNextBufferToProcess = 0L;
+		}
+	}
+
+	return xDataLen;
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xNetifInit( void )
+{
+portBASE_TYPE x;
+pcap_if_t *pxAllNetworkInterfaces;
+
+	/* Allocate a free buffer to each buffer pointer. */
+	for( x = 0; x < sizeof( pucEthernetBufferPointers ) / sizeof( unsigned char * ); x++ )
+	{
+		pucEthernetBufferPointers[ x ] = &( ucEthernetBuffer[ x ][ 0 ] );
+	}
+
+	/* Start with uip_buf pointing to a buffer that is not referenced from the
+	pucEthernetBufferPointers[] array. */
+	uip_buf = &( ucEthernetBuffer[ archNUM_BUFFERS - 1 ][ 0 ] );
+
+	/* Query the computer the simulation is being executed on to find the 
+	network interfaces it has installed. */
+	pxAllNetworkInterfaces = prvPrintAvailableNetworkInterfaces();
+	
+	/* Open the network interface.  The number of the interface to be opened is 
+	set by the configNETWORK_INTERFACE_TO_USE constant in FreeRTOSConfig.h.
+	Calling this function will set the pxOpenedInterfaceHandle variable.  If,
+	after calling this function, pxOpenedInterfaceHandle is equal to NULL, then
+	the interface could not be opened. */
+	if( pxAllNetworkInterfaces != NULL )
+	{
+		prvOpenSelectedNetworkInterface( pxAllNetworkInterfaces );
+	}
+	
+
+	return x;
+}
+/*-----------------------------------------------------------*/
+
+static pcap_if_t * prvPrintAvailableNetworkInterfaces( void )
+{    
+pcap_if_t * pxAllNetworkInterfaces = NULL, *xInterface;
+long lInterfaceNumber = 1;
+
+    if( pcap_findalldevs_ex( PCAP_SRC_IF_STRING, NULL, &pxAllNetworkInterfaces, cErrorBuffer ) == -1 )
+    {
+        printf( "\r\nCould not obtain a list of network interfaces\r\n%s\r\n", cErrorBuffer );
+        pxAllNetworkInterfaces = NULL;
+    }
+
+	if( pxAllNetworkInterfaces != NULL )
+	{
+		/* Print out the list of network interfaces.  The first in the list
+		is interface '1', not interface '0'. */
+		for( xInterface = pxAllNetworkInterfaces; xInterface != NULL; xInterface = xInterface->next )
+		{
+			printf( "%d. %s", lInterfaceNumber, xInterface->name );
+			
+			if( xInterface->description != NULL )
+			{
+				printf( " (%s)\r\n", xInterface->description );
+			}
+			else
+			{
+				printf( " (No description available)\r\n") ;
+			}
+			
+			lInterfaceNumber++;
+		}
+	}
+
+    if( lInterfaceNumber == 1 )
+    {
+		/* The interface number was never incremented, so the above for() loop
+		did not execute meaning no interfaces were found. */
+        printf( " \r\nNo network interfaces were found.\r\n" );
+        pxAllNetworkInterfaces = NULL;
+    }
+
+	printf( "\r\nThe interface that will be opened is set by configNETWORK_INTERFACE_TO_USE which should be defined in FreeRTOSConfig.h\r\n" );
+	printf( "Attempting to open interface number %d.\r\n", configNETWORK_INTERFACE_TO_USE );
+	
+    if( ( configNETWORK_INTERFACE_TO_USE < 1L ) || ( configNETWORK_INTERFACE_TO_USE > lInterfaceNumber ) )
+    {
+        printf("\r\nconfigNETWORK_INTERFACE_TO_USE is not in the valid range.\r\n" );
+		
+		if( pxAllNetworkInterfaces != NULL )
+		{
+			/* Free the device list, as no devices are going to be opened. */
+			pcap_freealldevs( pxAllNetworkInterfaces );
+			pxAllNetworkInterfaces = NULL;
+		}
+    }
+
+	return pxAllNetworkInterfaces;
+}
+/*-----------------------------------------------------------*/
+
+static void prvOpenSelectedNetworkInterface( pcap_if_t *pxAllNetworkInterfaces )
+{
+pcap_if_t *xInterface;
+long x;
+
+    /* Walk the list of devices until the selected device is located. */
+	xInterface = pxAllNetworkInterfaces;
+    for( x = 0L; x < ( configNETWORK_INTERFACE_TO_USE - 1L ); x++ )
+	{
+		xInterface = xInterface->next;
+	}
+
+    /* Open the selected interface. */
+	pxOpenedInterfaceHandle = pcap_open(	xInterface->name,          	/* The name of the selected interface. */
+											UIP_CONF_BUFFER_SIZE, 		/* The size of the packet to capture. */
+											PCAP_OPENFLAG_PROMISCUOUS,	/* Open in promiscious mode as the MAC and 
+																		IP address is going to be "simulated", and 
+																		not be the real MAC and IP address.  This allows
+																		trafic to the simulated IP address to be routed
+																		to uIP, and trafic to the real IP address to be
+																		routed to the Windows TCP/IP stack. */
+											0xfffffffL,             	/* The read time out.  This is going to block
+																		until data is available. */
+											NULL,             			/* No authentication is required as this is
+																		not a remote capture session. */
+											cErrorBuffer            
+									   );
+									   
+    if ( pxOpenedInterfaceHandle == NULL )
+    {
+        printf( "\r\n%s is not supported by WinPcap and cannot be opened\r\n", xInterface->name );
+    }
+	else
+	{
+		/* Configure the capture filter to allow blocking reads, and to filter 
+		out packets that are not of interest to this demo. */
+		prvConfigureCaptureBehaviour();
+	}
+
+	/* The device list is no longer required. */
+	pcap_freealldevs( pxAllNetworkInterfaces );
+}
+/*-----------------------------------------------------------*/
+
+static void prvConfigureCaptureBehaviour( void )
+{
+struct bpf_program xFilterCode;
+const long lMinBytesToCopy = 10L, lBlocking = 0L;
+unsigned long ulNetMask;
+
+	/* Unblock a read as soon as anything is received. */
+	pcap_setmintocopy( pxOpenedInterfaceHandle, lMinBytesToCopy );
+
+	/* Allow blocking. */
+	pcap_setnonblock( pxOpenedInterfaceHandle, lBlocking, cErrorBuffer );
+
+	/* Set up a filter so only the packets of interest are passed to the uIP
+	stack.  cErrorBuffer is used for convenience to create the string.  Don't
+	confuse this with an error message. */
+	sprintf( cErrorBuffer, "broadcast or multicast or host %d.%d.%d.%d", configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 );
+
+	ulNetMask = ( configNET_MASK3 << 24UL ) | ( configNET_MASK2 << 16UL ) | ( configNET_MASK1 << 8L ) | configNET_MASK0;
+
+	if( pcap_compile(pxOpenedInterfaceHandle, &xFilterCode, cErrorBuffer, 1, ulNetMask ) < 0 )
+    {
+        printf("\r\nThe packet filter string is invalid\r\n" );
+    }
+	else
+	{    
+		if( pcap_setfilter( pxOpenedInterfaceHandle, &xFilterCode ) < 0 )
+		{
+			printf( "\r\nAn error occurred setting the packet filter.\r\n" );
+		}
+	}
+
+	/* Create a task that simulates an interrupt in a real system.  This will
+	block waiting for packets, then send a message to the uIP task when data
+	is available. */
+	xTaskCreate( prvInterruptSimulator, "MAC_ISR", configMINIMAL_STACK_SIZE, NULL, ( configuIP_TASK_PRIORITY - 1 ), NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInterruptSimulator( void *pvParameters )
+{
+static struct pcap_pkthdr *pxHeader;
+const unsigned char *pucPacketData;
+extern QueueHandle_t xEMACEventQueue;
+const unsigned long ulRxEvent = uipETHERNET_RX_EVENT;
+long lResult;
+
+	/* Just to kill the compiler warning. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		/* Get the next packet. */
+		lResult = pcap_next_ex( pxOpenedInterfaceHandle, &pxHeader, &pucPacketData );
+		if( lResult )
+		{
+			/* Is the next buffer into which data should be placed free? */
+			if( lLengthOfDataInBuffer[ ucNextBufferToFill ] == 0L )
+			{
+				/* Copy the data from the captured packet into the buffer. */
+				memcpy( pucEthernetBufferPointers[ ucNextBufferToFill ], pucPacketData, pxHeader->len );
+
+				/* Note the amount of data that was copied. */
+				lLengthOfDataInBuffer[ ucNextBufferToFill ] = pxHeader->len;
+
+				/* Move onto the next buffer, wrapping around if necessary. */
+				ucNextBufferToFill++;
+				if( ucNextBufferToFill >= archNUM_BUFFER_POINTERS )
+				{
+					ucNextBufferToFill = 0U;
+				}
+
+				/* Data was received and stored.  Send a message to the uIP task
+				to let it know. */
+				xQueueSendToBack( xEMACEventQueue, &ulRxEvent, portMAX_DELAY );
+			}
+		}
+	}
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/bittypes.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/bittypes.h
new file mode 100644
index 0000000..f55fcec
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/bittypes.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (C) 1999 WIDE Project.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the project nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+#ifndef _BITTYPES_H
+#define _BITTYPES_H
+
+#ifndef HAVE_U_INT8_T
+
+#if SIZEOF_CHAR == 1
+typedef unsigned char u_int8_t;
+typedef signed char _int8_t;
+#elif SIZEOF_INT == 1
+typedef unsigned int u_int8_t;
+typedef signed int int8_t;
+#else  /* XXX */
+#error "there's no appropriate type for u_int8_t"
+#endif
+#define HAVE_U_INT8_T 1
+#define HAVE_INT8_T 1
+
+#endif /* HAVE_U_INT8_T */
+
+#ifndef HAVE_U_INT16_T 
+
+#if SIZEOF_SHORT == 2
+typedef unsigned short u_int16_t;
+typedef signed short _int16_t;
+#elif SIZEOF_INT == 2
+typedef unsigned int u_int16_t;
+typedef signed int int16_t;
+#elif SIZEOF_CHAR == 2
+typedef unsigned char u_int16_t;
+typedef signed char int16_t;
+#else  /* XXX */
+#error "there's no appropriate type for u_int16_t"
+#endif
+#define HAVE_U_INT16_T 1
+#define HAVE_INT16_T 1
+
+#endif /* HAVE_U_INT16_T */
+
+#ifndef HAVE_U_INT32_T
+
+#if SIZEOF_INT == 4
+typedef unsigned int u_int32_t;
+typedef signed int _int32_t;
+#elif SIZEOF_LONG == 4
+typedef unsigned long u_int32_t;
+typedef signed long int32_t;
+#elif SIZEOF_SHORT == 4
+typedef unsigned short u_int32_t;
+typedef signed short int32_t;
+#else  /* XXX */
+#error "there's no appropriate type for u_int32_t"
+#endif
+#define HAVE_U_INT32_T 1
+#define HAVE_INT32_T 1
+
+#endif /* HAVE_U_INT32_T */
+
+#ifndef HAVE_U_INT64_T
+#if SIZEOF_LONG_LONG == 8
+typedef unsigned long long u_int64_t;
+typedef long long int64_t;
+#elif defined(_MSC_EXTENSIONS)
+typedef unsigned _int64 u_int64_t;
+typedef _int64 int64_t;
+#elif SIZEOF_INT == 8
+typedef unsigned int u_int64_t;
+#elif SIZEOF_LONG == 8
+typedef unsigned long u_int64_t;
+#elif SIZEOF_SHORT == 8
+typedef unsigned short u_int64_t;
+#else  /* XXX */
+#error "there's no appropriate type for u_int64_t"
+#endif
+
+#endif /* HAVE_U_INT64_T */
+
+#ifndef PRId64
+#ifdef _MSC_EXTENSIONS
+#define PRId64	"I64d"
+#else /* _MSC_EXTENSIONS */
+#define PRId64	"lld"
+#endif /* _MSC_EXTENSIONS */
+#endif /* PRId64 */
+
+#ifndef PRIo64
+#ifdef _MSC_EXTENSIONS
+#define PRIo64	"I64o"
+#else /* _MSC_EXTENSIONS */
+#define PRIo64	"llo"
+#endif /* _MSC_EXTENSIONS */
+#endif /* PRIo64 */
+
+#ifndef PRIx64
+#ifdef _MSC_EXTENSIONS
+#define PRIx64	"I64x"
+#else /* _MSC_EXTENSIONS */
+#define PRIx64	"llx"
+#endif /* _MSC_EXTENSIONS */
+#endif /* PRIx64 */
+
+#ifndef PRIu64
+#ifdef _MSC_EXTENSIONS
+#define PRIu64	"I64u"
+#else /* _MSC_EXTENSIONS */
+#define PRIu64	"llu"
+#endif /* _MSC_EXTENSIONS */
+#endif /* PRIu64 */
+
+#endif /* _BITTYPES_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/ip6_misc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/ip6_misc.h
new file mode 100644
index 0000000..562fa61
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/ip6_misc.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 1993, 1994, 1997
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * @(#) $Header: /tcpdump/master/libpcap/Win32/Include/ip6_misc.h,v 1.5 2006-01-22 18:02:18 gianluca Exp $ (LBL)
+ */
+
+/*
+ * This file contains a collage of declarations for IPv6 from FreeBSD not present in Windows
+ */
+
+#include 
+
+#include 
+
+#ifndef __MINGW32__
+#define	IN_MULTICAST(a)		IN_CLASSD(a)
+#endif
+
+#define	IN_EXPERIMENTAL(a)	((((u_int32_t) (a)) & 0xf0000000) == 0xf0000000)
+
+#define	IN_LOOPBACKNET		127
+
+#if defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF)
+/* IPv6 address */
+struct in6_addr
+  {
+    union
+      {
+	u_int8_t		u6_addr8[16];
+	u_int16_t	u6_addr16[8];
+	u_int32_t	u6_addr32[4];
+      } in6_u;
+#define s6_addr			in6_u.u6_addr8
+#define s6_addr16		in6_u.u6_addr16
+#define s6_addr32		in6_u.u6_addr32
+#define s6_addr64		in6_u.u6_addr64
+  };
+
+#define IN6ADDR_ANY_INIT { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+#define IN6ADDR_LOOPBACK_INIT { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1 }
+#endif /* __MINGW32__ */
+
+
+#if (defined _MSC_VER) || (defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF))
+typedef unsigned short	sa_family_t;
+#endif
+
+
+#if defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF)
+
+#define	__SOCKADDR_COMMON(sa_prefix) \
+  sa_family_t sa_prefix##family
+
+/* Ditto, for IPv6.  */
+struct sockaddr_in6
+  {
+    __SOCKADDR_COMMON (sin6_);
+    u_int16_t sin6_port;		/* Transport layer port # */
+    u_int32_t sin6_flowinfo;	/* IPv6 flow information */
+    struct in6_addr sin6_addr;	/* IPv6 address */
+  };
+
+#define IN6_IS_ADDR_V4MAPPED(a) \
+	((((u_int32_t *) (a))[0] == 0) && (((u_int32_t *) (a))[1] == 0) && \
+	 (((u_int32_t *) (a))[2] == htonl (0xffff)))
+
+#define IN6_IS_ADDR_MULTICAST(a) (((u_int8_t *) (a))[0] == 0xff)
+
+#define IN6_IS_ADDR_LINKLOCAL(a) \
+	((((u_int32_t *) (a))[0] & htonl (0xffc00000)) == htonl (0xfe800000))
+
+#define IN6_IS_ADDR_LOOPBACK(a) \
+	(((u_int32_t *) (a))[0] == 0 && ((u_int32_t *) (a))[1] == 0 && \
+	 ((u_int32_t *) (a))[2] == 0 && ((u_int32_t *) (a))[3] == htonl (1))
+#endif /* __MINGW32__ */
+
+#define ip6_vfc   ip6_ctlun.ip6_un2_vfc
+#define ip6_flow  ip6_ctlun.ip6_un1.ip6_un1_flow
+#define ip6_plen  ip6_ctlun.ip6_un1.ip6_un1_plen
+#define ip6_nxt   ip6_ctlun.ip6_un1.ip6_un1_nxt
+#define ip6_hlim  ip6_ctlun.ip6_un1.ip6_un1_hlim
+#define ip6_hops  ip6_ctlun.ip6_un1.ip6_un1_hlim
+
+#define nd_rd_type               nd_rd_hdr.icmp6_type
+#define nd_rd_code               nd_rd_hdr.icmp6_code
+#define nd_rd_cksum              nd_rd_hdr.icmp6_cksum
+#define nd_rd_reserved           nd_rd_hdr.icmp6_data32[0]
+
+/*
+ *	IPV6 extension headers
+ */
+#define IPPROTO_HOPOPTS		0	/* IPv6 hop-by-hop options	*/
+#define IPPROTO_IPV6		41  /* IPv6 header.  */
+#define IPPROTO_ROUTING		43	/* IPv6 routing header		*/
+#define IPPROTO_FRAGMENT	44	/* IPv6 fragmentation header	*/
+#define IPPROTO_ESP		50	/* encapsulating security payload */
+#define IPPROTO_AH		51	/* authentication header	*/
+#define IPPROTO_ICMPV6		58	/* ICMPv6			*/
+#define IPPROTO_NONE		59	/* IPv6 no next header		*/
+#define IPPROTO_DSTOPTS		60	/* IPv6 destination options	*/
+#define IPPROTO_PIM			103 /* Protocol Independent Multicast.  */
+
+#define	 IPV6_RTHDR_TYPE_0 0
+
+/* Option types and related macros */
+#define IP6OPT_PAD1		0x00	/* 00 0 00000 */
+#define IP6OPT_PADN		0x01	/* 00 0 00001 */
+#define IP6OPT_JUMBO		0xC2	/* 11 0 00010 = 194 */
+#define IP6OPT_JUMBO_LEN	6
+#define IP6OPT_ROUTER_ALERT	0x05	/* 00 0 00101 */
+
+#define IP6OPT_RTALERT_LEN	4
+#define IP6OPT_RTALERT_MLD	0	/* Datagram contains an MLD message */
+#define IP6OPT_RTALERT_RSVP	1	/* Datagram contains an RSVP message */
+#define IP6OPT_RTALERT_ACTNET	2 	/* contains an Active Networks msg */
+#define IP6OPT_MINLEN		2
+
+#define IP6OPT_BINDING_UPDATE	0xc6	/* 11 0 00110 */
+#define IP6OPT_BINDING_ACK	0x07	/* 00 0 00111 */
+#define IP6OPT_BINDING_REQ	0x08	/* 00 0 01000 */
+#define IP6OPT_HOME_ADDRESS	0xc9	/* 11 0 01001 */
+#define IP6OPT_EID		0x8a	/* 10 0 01010 */
+
+#define IP6OPT_TYPE(o)		((o) & 0xC0)
+#define IP6OPT_TYPE_SKIP	0x00
+#define IP6OPT_TYPE_DISCARD	0x40
+#define IP6OPT_TYPE_FORCEICMP	0x80
+#define IP6OPT_TYPE_ICMP	0xC0
+
+#define IP6OPT_MUTABLE		0x20
+
+
+#if defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF)
+#ifndef EAI_ADDRFAMILY
+struct addrinfo {
+	int	ai_flags;	/* AI_PASSIVE, AI_CANONNAME */
+	int	ai_family;	/* PF_xxx */
+	int	ai_socktype;	/* SOCK_xxx */
+	int	ai_protocol;	/* 0 or IPPROTO_xxx for IPv4 and IPv6 */
+	size_t	ai_addrlen;	/* length of ai_addr */
+	char	*ai_canonname;	/* canonical name for hostname */
+	struct sockaddr *ai_addr;	/* binary address */
+	struct addrinfo *ai_next;	/* next structure in linked list */
+};
+#endif
+#endif /* __MINGW32__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/netif.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/netif.h
new file mode 100644
index 0000000..114bdf3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/netif.h
@@ -0,0 +1,52 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef NET_IF_H
+#define NET_IF_H
+
+/*
+ * Send uip_len bytes from uip_buf to the network interface selected by the 
+ * configNETWORK_INTERFACE_TO_USE constant (defined in FreeRTOSConfig.h). 
+ */
+void vNetifTx( void );
+
+/*
+ * Receive bytes from the network interface selected by the 
+ * configNETWORK_INTERFACE_TO_USE constant (defined in FreeRTOSConfig.h).  The
+ * bytes are placed in uip_buf.  The number of bytes copied into uip_buf is
+ * returned.
+ */
+unsigned portBASE_TYPE uxNetifRx( void );
+
+/*
+ * Prepare a packet capture session.  This will print out all the network 
+ * interfaces available, and the one actually used is set by the 
+ * configNETWORK_INTERFACE_TO_USE constant that is defined in 
+ * FreeRTOSConfig.h. */
+portBASE_TYPE xNetifInit( void );
+
+#endif /* NET_IF_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap-bpf.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap-bpf.h
new file mode 100644
index 0000000..5fe129d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap-bpf.h
@@ -0,0 +1,47 @@
+/*-
+ * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * This code is derived from the Stanford/CMU enet packet filter,
+ * (net/enet.c) distributed as part of 4.3BSD, and code contributed
+ * to Berkeley by Steven McCanne and Van Jacobson both of Lawrence 
+ * Berkeley Laboratory.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by the University of
+ *      California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#) $Header: /tcpdump/master/libpcap/pcap-bpf.h,v 1.50 2007/04/01 21:43:55 guy Exp $ (LBL)
+ */
+
+/*
+ * For backwards compatibility.
+ *
+ * Note to OS vendors: do NOT get rid of this file!  Some applications
+ * might expect to be able to include .
+ */
+#include 
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap-namedb.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap-namedb.h
new file mode 100644
index 0000000..80a2f00
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap-namedb.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 1994, 1996
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the Computer Systems
+ *	Engineering Group at Lawrence Berkeley Laboratory.
+ * 4. Neither the name of the University nor of the Laboratory may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#) $Header: /tcpdump/master/libpcap/pcap-namedb.h,v 1.13 2006/10/04 18:13:32 guy Exp $ (LBL)
+ */
+
+/*
+ * For backwards compatibility.
+ *
+ * Note to OS vendors: do NOT get rid of this file!  Some applications
+ * might expect to be able to include .
+ */
+#include 
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap-stdinc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap-stdinc.h
new file mode 100644
index 0000000..f1ea03f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap-stdinc.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2002 - 2005 NetGroup, Politecnico di Torino (Italy)
+ * Copyright (c) 2005 - 2009 CACE Technologies, Inc. Davis (California)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Politecnico di Torino nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * @(#) $Header: /tcpdump/master/libpcap/pcap-stdinc.h,v 1.10.2.1 2008-10-06 15:38:39 gianluca Exp $ (LBL)
+ */
+
+#define SIZEOF_CHAR 1
+#define SIZEOF_SHORT 2
+#define SIZEOF_INT 4
+#ifndef _MSC_EXTENSIONS
+#define SIZEOF_LONG_LONG 8
+#endif
+
+/*
+ * Avoids a compiler warning in case this was already defined      
+ * (someone defined _WINSOCKAPI_ when including 'windows.h', in order
+ * to prevent it from including 'winsock.h')
+ */
+#ifdef _WINSOCKAPI_
+#undef _WINSOCKAPI_
+#endif
+//_RB_#include 
+
+#include 
+
+#include "bittypes.h"
+#include 
+#include 
+
+#ifndef __MINGW32__
+#include "IP6_misc.h"
+#endif
+
+#define caddr_t char*
+
+#if _MSC_VER < 1500
+#define snprintf _snprintf
+#define vsnprintf _vsnprintf
+#define strdup _strdup
+#endif
+
+#define inline __inline 
+
+#ifdef __MINGW32__
+#include 
+#else /*__MINGW32__*/
+/* MSVC compiler */
+#ifndef _UINTPTR_T_DEFINED
+#ifdef  _WIN64
+typedef unsigned __int64    uintptr_t;
+#else
+typedef _W64 unsigned int   uintptr_t;
+#endif
+#define _UINTPTR_T_DEFINED
+#endif
+
+#ifndef _INTPTR_T_DEFINED
+#ifdef  _WIN64
+typedef __int64    intptr_t;
+#else
+typedef _W64 int   intptr_t;
+#endif
+#define _INTPTR_T_DEFINED
+#endif 
+
+#endif /*__MINGW32__*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap.h
new file mode 100644
index 0000000..ad8fc40
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap.h
@@ -0,0 +1,407 @@
+/* -*- Mode: c; tab-width: 8; indent-tabs-mode: 1; c-basic-offset: 8; -*- */
+/*
+ * Copyright (c) 1993, 1994, 1995, 1996, 1997
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the Computer Systems
+ *	Engineering Group at Lawrence Berkeley Laboratory.
+ * 4. Neither the name of the University nor of the Laboratory may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#) $Header: /tcpdump/master/libpcap/pcap/pcap.h,v 1.4.2.11 2008-10-06 15:38:39 gianluca Exp $ (LBL)
+ */
+
+#ifndef lib_pcap_pcap_h
+#define lib_pcap_pcap_h
+
+#if defined(WIN32)
+  #include 
+#elif defined(MSDOS)
+  #include 
+  #include   /* u_int, u_char etc. */
+#else /* UN*X */
+  #include 
+  #include 
+#endif /* WIN32/MSDOS/UN*X */
+
+#ifndef PCAP_DONT_INCLUDE_PCAP_BPF_H
+#include 
+#endif
+
+#include 
+
+#ifdef HAVE_REMOTE
+	// We have to define the SOCKET here, although it has been defined in sockutils.h
+	// This is to avoid the distribution of the 'sockutils.h' file around
+	// (for example in the WinPcap developer's pack)
+	#ifndef SOCKET
+		#ifdef WIN32
+			#define SOCKET unsigned int
+		#else
+			#define SOCKET int
+		#endif
+	#endif
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PCAP_VERSION_MAJOR 2
+#define PCAP_VERSION_MINOR 4
+
+#define PCAP_ERRBUF_SIZE 256
+
+/*
+ * Compatibility for systems that have a bpf.h that
+ * predates the bpf typedefs for 64-bit support.
+ */
+#if BPF_RELEASE - 0 < 199406
+typedef	int bpf_int32;
+typedef	u_int bpf_u_int32;
+#endif
+
+typedef struct pcap pcap_t;
+typedef struct pcap_dumper pcap_dumper_t;
+typedef struct pcap_if pcap_if_t;
+typedef struct pcap_addr pcap_addr_t;
+
+/*
+ * The first record in the file contains saved values for some
+ * of the flags used in the printout phases of tcpdump.
+ * Many fields here are 32 bit ints so compilers won't insert unwanted
+ * padding; these files need to be interchangeable across architectures.
+ *
+ * Do not change the layout of this structure, in any way (this includes
+ * changes that only affect the length of fields in this structure).
+ *
+ * Also, do not change the interpretation of any of the members of this
+ * structure, in any way (this includes using values other than
+ * LINKTYPE_ values, as defined in "savefile.c", in the "linktype"
+ * field).
+ *
+ * Instead:
+ *
+ *	introduce a new structure for the new format, if the layout
+ *	of the structure changed;
+ *
+ *	send mail to "tcpdump-workers@lists.tcpdump.org", requesting
+ *	a new magic number for your new capture file format, and, when
+ *	you get the new magic number, put it in "savefile.c";
+ *
+ *	use that magic number for save files with the changed file
+ *	header;
+ *
+ *	make the code in "savefile.c" capable of reading files with
+ *	the old file header as well as files with the new file header
+ *	(using the magic number to determine the header format).
+ *
+ * Then supply the changes as a patch at
+ *
+ *	http://sourceforge.net/projects/libpcap/
+ *
+ * so that future versions of libpcap and programs that use it (such as
+ * tcpdump) will be able to read your new capture file format.
+ */
+struct pcap_file_header {
+	bpf_u_int32 magic;
+	u_short version_major;
+	u_short version_minor;
+	bpf_int32 thiszone;	/* gmt to local correction */
+	bpf_u_int32 sigfigs;	/* accuracy of timestamps */
+	bpf_u_int32 snaplen;	/* max length saved portion of each pkt */
+	bpf_u_int32 linktype;	/* data link type (LINKTYPE_*) */
+};
+
+/*
+ * Macros for the value returned by pcap_datalink_ext().
+ * 
+ * If LT_FCS_LENGTH_PRESENT(x) is true, the LT_FCS_LENGTH(x) macro
+ * gives the FCS length of packets in the capture.
+ */
+#define LT_FCS_LENGTH_PRESENT(x)	((x) & 0x04000000)
+#define LT_FCS_LENGTH(x)		(((x) & 0xF0000000) >> 28)
+#define LT_FCS_DATALINK_EXT(x)		((((x) & 0xF) << 28) | 0x04000000)
+
+typedef enum {
+       PCAP_D_INOUT = 0,
+       PCAP_D_IN,
+       PCAP_D_OUT
+} pcap_direction_t;
+
+/*
+ * Generic per-packet information, as supplied by libpcap.
+ *
+ * The time stamp can and should be a "struct timeval", regardless of
+ * whether your system supports 32-bit tv_sec in "struct timeval",
+ * 64-bit tv_sec in "struct timeval", or both if it supports both 32-bit
+ * and 64-bit applications.  The on-disk format of savefiles uses 32-bit
+ * tv_sec (and tv_usec); this structure is irrelevant to that.  32-bit
+ * and 64-bit versions of libpcap, even if they're on the same platform,
+ * should supply the appropriate version of "struct timeval", even if
+ * that's not what the underlying packet capture mechanism supplies.
+ */
+struct pcap_pkthdr {
+	struct timeval ts;	/* time stamp */
+	bpf_u_int32 caplen;	/* length of portion present */
+	bpf_u_int32 len;	/* length this packet (off wire) */
+};
+
+/*
+ * As returned by the pcap_stats()
+ */
+struct pcap_stat {
+	u_int ps_recv;		/* number of packets received */
+	u_int ps_drop;		/* number of packets dropped */
+	u_int ps_ifdrop;	/* drops by interface XXX not yet supported */
+#ifdef HAVE_REMOTE
+	u_int ps_capt;		/* number of packets that are received by the application; please get rid off the Win32 ifdef */
+	u_int ps_sent;		/* number of packets sent by the server on the network */
+	u_int ps_netdrop;	/* number of packets lost on the network */
+#endif /* HAVE_REMOTE */
+};
+
+#ifdef MSDOS
+/*
+ * As returned by the pcap_stats_ex()
+ */
+struct pcap_stat_ex {
+       u_long  rx_packets;        /* total packets received       */
+       u_long  tx_packets;        /* total packets transmitted    */
+       u_long  rx_bytes;          /* total bytes received         */
+       u_long  tx_bytes;          /* total bytes transmitted      */
+       u_long  rx_errors;         /* bad packets received         */
+       u_long  tx_errors;         /* packet transmit problems     */
+       u_long  rx_dropped;        /* no space in Rx buffers       */
+       u_long  tx_dropped;        /* no space available for Tx    */
+       u_long  multicast;         /* multicast packets received   */
+       u_long  collisions;
+
+       /* detailed rx_errors: */
+       u_long  rx_length_errors;
+       u_long  rx_over_errors;    /* receiver ring buff overflow  */
+       u_long  rx_crc_errors;     /* recv'd pkt with crc error    */
+       u_long  rx_frame_errors;   /* recv'd frame alignment error */
+       u_long  rx_fifo_errors;    /* recv'r fifo overrun          */
+       u_long  rx_missed_errors;  /* recv'r missed packet         */
+
+       /* detailed tx_errors */
+       u_long  tx_aborted_errors;
+       u_long  tx_carrier_errors;
+       u_long  tx_fifo_errors;
+       u_long  tx_heartbeat_errors;
+       u_long  tx_window_errors;
+     };
+#endif
+
+/*
+ * Item in a list of interfaces.
+ */
+struct pcap_if {
+	struct pcap_if *next;
+	char *name;		/* name to hand to "pcap_open_live()" */
+	char *description;	/* textual description of interface, or NULL */
+	struct pcap_addr *addresses;
+	bpf_u_int32 flags;	/* PCAP_IF_ interface flags */
+};
+
+#define PCAP_IF_LOOPBACK	0x00000001	/* interface is loopback */
+
+/*
+ * Representation of an interface address.
+ */
+struct pcap_addr {
+	struct pcap_addr *next;
+	struct sockaddr *addr;		/* address */
+	struct sockaddr *netmask;	/* netmask for that address */
+	struct sockaddr *broadaddr;	/* broadcast address for that address */
+	struct sockaddr *dstaddr;	/* P2P destination address for that address */
+};
+
+typedef void (*pcap_handler)(u_char *, const struct pcap_pkthdr *,
+			     const u_char *);
+
+/*
+ * Error codes for the pcap API.
+ * These will all be negative, so you can check for the success or
+ * failure of a call that returns these codes by checking for a
+ * negative value.
+ */
+#define PCAP_ERROR			-1	/* generic error code */
+#define PCAP_ERROR_BREAK		-2	/* loop terminated by pcap_breakloop */
+#define PCAP_ERROR_NOT_ACTIVATED	-3	/* the capture needs to be activated */
+#define PCAP_ERROR_ACTIVATED		-4	/* the operation can't be performed on already activated captures */
+#define PCAP_ERROR_NO_SUCH_DEVICE	-5	/* no such device exists */
+#define PCAP_ERROR_RFMON_NOTSUP		-6	/* this device doesn't support rfmon (monitor) mode */
+#define PCAP_ERROR_NOT_RFMON		-7	/* operation supported only in monitor mode */
+#define PCAP_ERROR_PERM_DENIED		-8	/* no permission to open the device */
+#define PCAP_ERROR_IFACE_NOT_UP		-9	/* interface isn't up */
+
+/*
+ * Warning codes for the pcap API.
+ * These will all be positive and non-zero, so they won't look like
+ * errors.
+ */
+#define PCAP_WARNING			1	/* generic warning code */
+#define PCAP_WARNING_PROMISC_NOTSUP	2	/* this device doesn't support promiscuous mode */
+
+char	*pcap_lookupdev(char *);
+int	pcap_lookupnet(const char *, bpf_u_int32 *, bpf_u_int32 *, char *);
+
+pcap_t	*pcap_create(const char *, char *);
+int	pcap_set_snaplen(pcap_t *, int);
+int	pcap_set_promisc(pcap_t *, int);
+int	pcap_can_set_rfmon(pcap_t *);
+int	pcap_set_rfmon(pcap_t *, int);
+int	pcap_set_timeout(pcap_t *, int);
+int	pcap_set_buffer_size(pcap_t *, int);
+int	pcap_activate(pcap_t *);
+
+pcap_t	*pcap_open_live(const char *, int, int, int, char *);
+pcap_t	*pcap_open_dead(int, int);
+pcap_t	*pcap_open_offline(const char *, char *);
+#if defined(WIN32)
+pcap_t  *pcap_hopen_offline(intptr_t, char *);
+#if !defined(LIBPCAP_EXPORTS)
+#define pcap_fopen_offline(f,b) \
+	pcap_hopen_offline(_get_osfhandle(_fileno(f)), b)
+#else /*LIBPCAP_EXPORTS*/
+static pcap_t *pcap_fopen_offline(FILE *, char *);
+#endif
+#else /*WIN32*/
+pcap_t	*pcap_fopen_offline(FILE *, char *);
+#endif /*WIN32*/
+
+void	pcap_close(pcap_t *);
+int	pcap_loop(pcap_t *, int, pcap_handler, u_char *);
+int	pcap_dispatch(pcap_t *, int, pcap_handler, u_char *);
+const u_char*
+	pcap_next(pcap_t *, struct pcap_pkthdr *);
+int 	pcap_next_ex(pcap_t *, struct pcap_pkthdr **, const u_char **);
+void	pcap_breakloop(pcap_t *);
+int	pcap_stats(pcap_t *, struct pcap_stat *);
+int	pcap_setfilter(pcap_t *, struct bpf_program *);
+int 	pcap_setdirection(pcap_t *, pcap_direction_t);
+int	pcap_getnonblock(pcap_t *, char *);
+int	pcap_setnonblock(pcap_t *, int, char *);
+int	pcap_inject(pcap_t *, const void *, size_t);
+int	pcap_sendpacket(pcap_t *, const u_char *, int);
+const char *pcap_statustostr(int);
+const char *pcap_strerror(int);
+char	*pcap_geterr(pcap_t *);
+void	pcap_perror(pcap_t *, char *);
+int	pcap_compile(pcap_t *, struct bpf_program *, const char *, int,
+	    bpf_u_int32);
+int	pcap_compile_nopcap(int, int, struct bpf_program *,
+	    const char *, int, bpf_u_int32);
+void	pcap_freecode(struct bpf_program *);
+int	pcap_offline_filter(struct bpf_program *, const struct pcap_pkthdr *,
+	    const u_char *);
+int	pcap_datalink(pcap_t *);
+int	pcap_datalink_ext(pcap_t *);
+int	pcap_list_datalinks(pcap_t *, int **);
+int	pcap_set_datalink(pcap_t *, int);
+void	pcap_free_datalinks(int *);
+int	pcap_datalink_name_to_val(const char *);
+const char *pcap_datalink_val_to_name(int);
+const char *pcap_datalink_val_to_description(int);
+int	pcap_snapshot(pcap_t *);
+int	pcap_is_swapped(pcap_t *);
+int	pcap_major_version(pcap_t *);
+int	pcap_minor_version(pcap_t *);
+
+/* XXX */
+FILE	*pcap_file(pcap_t *);
+int	pcap_fileno(pcap_t *);
+
+pcap_dumper_t *pcap_dump_open(pcap_t *, const char *);
+pcap_dumper_t *pcap_dump_fopen(pcap_t *, FILE *fp);
+FILE	*pcap_dump_file(pcap_dumper_t *);
+long	pcap_dump_ftell(pcap_dumper_t *);
+int	pcap_dump_flush(pcap_dumper_t *);
+void	pcap_dump_close(pcap_dumper_t *);
+void	pcap_dump(u_char *, const struct pcap_pkthdr *, const u_char *);
+
+int	pcap_findalldevs(pcap_if_t **, char *);
+void	pcap_freealldevs(pcap_if_t *);
+
+const char *pcap_lib_version(void);
+
+/* XXX this guy lives in the bpf tree */
+u_int	bpf_filter(const struct bpf_insn *, const u_char *, u_int, u_int);
+int	bpf_validate(const struct bpf_insn *f, int len);
+char	*bpf_image(const struct bpf_insn *, int);
+void	bpf_dump(const struct bpf_program *, int);
+
+#if defined(WIN32)
+
+/*
+ * Win32 definitions
+ */
+
+int pcap_setbuff(pcap_t *p, int dim);
+int pcap_setmode(pcap_t *p, int mode);
+int pcap_setmintocopy(pcap_t *p, int size);
+
+#ifdef WPCAP
+/* Include file with the wpcap-specific extensions */
+#include 
+#endif /* WPCAP */
+
+#define MODE_CAPT 0
+#define MODE_STAT 1
+#define MODE_MON 2
+
+#elif defined(MSDOS)
+
+/*
+ * MS-DOS definitions
+ */
+
+int  pcap_stats_ex (pcap_t *, struct pcap_stat_ex *);
+void pcap_set_wait (pcap_t *p, void (*yield)(void), int wait);
+u_long pcap_mac_packets (void);
+
+#else /* UN*X */
+
+/*
+ * UN*X definitions
+ */
+
+int	pcap_get_selectable_fd(pcap_t *);
+
+#endif /* WIN32/MSDOS/UN*X */
+
+#ifdef HAVE_REMOTE
+/* Includes most of the public stuff that is needed for the remote capture */
+#include 
+#endif	 /* HAVE_REMOTE */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/bluetooth.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/bluetooth.h
new file mode 100644
index 0000000..7bf65df
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/bluetooth.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2006 Paolo Abeni (Italy)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote 
+ * products derived from this software without specific prior written 
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * bluetooth data struct
+ * By Paolo Abeni 
+ *
+ * @(#) $Header: /tcpdump/master/libpcap/pcap/bluetooth.h,v 1.1 2007/09/22 02:10:17 guy Exp $
+ */
+ 
+#ifndef _PCAP_BLUETOOTH_STRUCTS_H__
+#define _PCAP_BLUETOOTH_STRUCTS_H__
+
+/*
+ * Header prepended libpcap to each bluetooth h:4 frame.
+ * fields are in network byte order
+ */
+typedef struct _pcap_bluetooth_h4_header {
+	u_int32_t direction; /* if first bit is set direction is incoming */
+} pcap_bluetooth_h4_header;
+
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/bpf.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/bpf.h
new file mode 100644
index 0000000..9f4ca33
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/bpf.h
@@ -0,0 +1,934 @@
+/*-
+ * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * This code is derived from the Stanford/CMU enet packet filter,
+ * (net/enet.c) distributed as part of 4.3BSD, and code contributed
+ * to Berkeley by Steven McCanne and Van Jacobson both of Lawrence 
+ * Berkeley Laboratory.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by the University of
+ *      California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *      @(#)bpf.h       7.1 (Berkeley) 5/7/91
+ *
+ * @(#) $Header: /tcpdump/master/libpcap/pcap/bpf.h,v 1.19.2.8 2008-09-22 20:16:01 guy Exp $ (LBL)
+ */
+
+/*
+ * This is libpcap's cut-down version of bpf.h; it includes only
+ * the stuff needed for the code generator and the userland BPF
+ * interpreter, and the libpcap APIs for setting filters, etc..
+ *
+ * "pcap-bpf.c" will include the native OS version, as it deals with
+ * the OS's BPF implementation.
+ *
+ * XXX - should this all just be moved to "pcap.h"?
+ */
+
+#ifndef BPF_MAJOR_VERSION
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* BSD style release date */
+#define BPF_RELEASE 199606
+
+#ifdef MSDOS /* must be 32-bit */
+typedef long          bpf_int32;
+typedef unsigned long bpf_u_int32;
+#else
+typedef	int bpf_int32;
+typedef	u_int bpf_u_int32;
+#endif
+
+/*
+ * Alignment macros.  BPF_WORDALIGN rounds up to the next 
+ * even multiple of BPF_ALIGNMENT. 
+ */
+#ifndef __NetBSD__
+#define BPF_ALIGNMENT sizeof(bpf_int32)
+#else
+#define BPF_ALIGNMENT sizeof(long)
+#endif
+#define BPF_WORDALIGN(x) (((x)+(BPF_ALIGNMENT-1))&~(BPF_ALIGNMENT-1))
+
+#define BPF_MAXBUFSIZE 0x8000
+#define BPF_MINBUFSIZE 32
+
+/*
+ * Structure for "pcap_compile()", "pcap_setfilter()", etc..
+ */
+struct bpf_program {
+	u_int bf_len;
+	struct bpf_insn *bf_insns;
+};
+ 
+/*
+ * Struct return by BIOCVERSION.  This represents the version number of 
+ * the filter language described by the instruction encodings below.
+ * bpf understands a program iff kernel_major == filter_major &&
+ * kernel_minor >= filter_minor, that is, if the value returned by the
+ * running kernel has the same major number and a minor number equal
+ * equal to or less than the filter being downloaded.  Otherwise, the
+ * results are undefined, meaning an error may be returned or packets
+ * may be accepted haphazardly.
+ * It has nothing to do with the source code version.
+ */
+struct bpf_version {
+	u_short bv_major;
+	u_short bv_minor;
+};
+/* Current version number of filter architecture. */
+#define BPF_MAJOR_VERSION 1
+#define BPF_MINOR_VERSION 1
+
+/*
+ * Data-link level type codes.
+ *
+ * Do *NOT* add new values to this list without asking
+ * "tcpdump-workers@lists.tcpdump.org" for a value.  Otherwise, you run
+ * the risk of using a value that's already being used for some other
+ * purpose, and of having tools that read libpcap-format captures not
+ * being able to handle captures with your new DLT_ value, with no hope
+ * that they will ever be changed to do so (as that would destroy their
+ * ability to read captures using that value for that other purpose).
+ */
+
+/*
+ * These are the types that are the same on all platforms, and that
+ * have been defined by  for ages.
+ */
+#define DLT_NULL	0	/* BSD loopback encapsulation */
+#define DLT_EN10MB	1	/* Ethernet (10Mb) */
+#define DLT_EN3MB	2	/* Experimental Ethernet (3Mb) */
+#define DLT_AX25	3	/* Amateur Radio AX.25 */
+#define DLT_PRONET	4	/* Proteon ProNET Token Ring */
+#define DLT_CHAOS	5	/* Chaos */
+#define DLT_IEEE802	6	/* 802.5 Token Ring */
+#define DLT_ARCNET	7	/* ARCNET, with BSD-style header */
+#define DLT_SLIP	8	/* Serial Line IP */
+#define DLT_PPP		9	/* Point-to-point Protocol */
+#define DLT_FDDI	10	/* FDDI */
+
+/*
+ * These are types that are different on some platforms, and that
+ * have been defined by  for ages.  We use #ifdefs to
+ * detect the BSDs that define them differently from the traditional
+ * libpcap 
+ *
+ * XXX - DLT_ATM_RFC1483 is 13 in BSD/OS, and DLT_RAW is 14 in BSD/OS,
+ * but I don't know what the right #define is for BSD/OS.
+ */
+#define DLT_ATM_RFC1483	11	/* LLC-encapsulated ATM */
+
+#ifdef __OpenBSD__
+#define DLT_RAW		14	/* raw IP */
+#else
+#define DLT_RAW		12	/* raw IP */
+#endif
+
+/*
+ * Given that the only OS that currently generates BSD/OS SLIP or PPP
+ * is, well, BSD/OS, arguably everybody should have chosen its values
+ * for DLT_SLIP_BSDOS and DLT_PPP_BSDOS, which are 15 and 16, but they
+ * didn't.  So it goes.
+ */
+#if defined(__NetBSD__) || defined(__FreeBSD__)
+#ifndef DLT_SLIP_BSDOS
+#define DLT_SLIP_BSDOS	13	/* BSD/OS Serial Line IP */
+#define DLT_PPP_BSDOS	14	/* BSD/OS Point-to-point Protocol */
+#endif
+#else
+#define DLT_SLIP_BSDOS	15	/* BSD/OS Serial Line IP */
+#define DLT_PPP_BSDOS	16	/* BSD/OS Point-to-point Protocol */
+#endif
+
+/*
+ * 17 is used for DLT_OLD_PFLOG in OpenBSD;
+ *     OBSOLETE: DLT_PFLOG is 117 in OpenBSD now as well. See below.
+ * 18 is used for DLT_PFSYNC in OpenBSD; don't use it for anything else.
+ */
+
+#define DLT_ATM_CLIP	19	/* Linux Classical-IP over ATM */
+
+/*
+ * Apparently Redback uses this for its SmartEdge 400/800.  I hope
+ * nobody else decided to use it, too.
+ */
+#define DLT_REDBACK_SMARTEDGE	32
+
+/*
+ * These values are defined by NetBSD; other platforms should refrain from
+ * using them for other purposes, so that NetBSD savefiles with link
+ * types of 50 or 51 can be read as this type on all platforms.
+ */
+#define DLT_PPP_SERIAL	50	/* PPP over serial with HDLC encapsulation */
+#define DLT_PPP_ETHER	51	/* PPP over Ethernet */
+
+/*
+ * The Axent Raptor firewall - now the Symantec Enterprise Firewall - uses
+ * a link-layer type of 99 for the tcpdump it supplies.  The link-layer
+ * header has 6 bytes of unknown data, something that appears to be an
+ * Ethernet type, and 36 bytes that appear to be 0 in at least one capture
+ * I've seen.
+ */
+#define DLT_SYMANTEC_FIREWALL	99
+
+/*
+ * Values between 100 and 103 are used in capture file headers as
+ * link-layer types corresponding to DLT_ types that differ
+ * between platforms; don't use those values for new DLT_ new types.
+ */
+
+/*
+ * This value was defined by libpcap 0.5; platforms that have defined
+ * it with a different value should define it here with that value -
+ * a link type of 104 in a save file will be mapped to DLT_C_HDLC,
+ * whatever value that happens to be, so programs will correctly
+ * handle files with that link type regardless of the value of
+ * DLT_C_HDLC.
+ *
+ * The name DLT_C_HDLC was used by BSD/OS; we use that name for source
+ * compatibility with programs written for BSD/OS.
+ *
+ * libpcap 0.5 defined it as DLT_CHDLC; we define DLT_CHDLC as well,
+ * for source compatibility with programs written for libpcap 0.5.
+ */
+#define DLT_C_HDLC	104	/* Cisco HDLC */
+#define DLT_CHDLC	DLT_C_HDLC
+
+#define DLT_IEEE802_11	105	/* IEEE 802.11 wireless */
+
+/*
+ * 106 is reserved for Linux Classical IP over ATM; it's like DLT_RAW,
+ * except when it isn't.  (I.e., sometimes it's just raw IP, and
+ * sometimes it isn't.)  We currently handle it as DLT_LINUX_SLL,
+ * so that we don't have to worry about the link-layer header.)
+ */
+
+/*
+ * Frame Relay; BSD/OS has a DLT_FR with a value of 11, but that collides
+ * with other values.
+ * DLT_FR and DLT_FRELAY packets start with the Q.922 Frame Relay header
+ * (DLCI, etc.).
+ */
+#define DLT_FRELAY	107
+
+/*
+ * OpenBSD DLT_LOOP, for loopback devices; it's like DLT_NULL, except
+ * that the AF_ type in the link-layer header is in network byte order.
+ *
+ * DLT_LOOP is 12 in OpenBSD, but that's DLT_RAW in other OSes, so
+ * we don't use 12 for it in OSes other than OpenBSD.
+ */
+#ifdef __OpenBSD__
+#define DLT_LOOP	12
+#else
+#define DLT_LOOP	108
+#endif
+
+/*
+ * Encapsulated packets for IPsec; DLT_ENC is 13 in OpenBSD, but that's
+ * DLT_SLIP_BSDOS in NetBSD, so we don't use 13 for it in OSes other
+ * than OpenBSD.
+ */
+#ifdef __OpenBSD__
+#define DLT_ENC		13
+#else
+#define DLT_ENC		109
+#endif
+
+/*
+ * Values between 110 and 112 are reserved for use in capture file headers
+ * as link-layer types corresponding to DLT_ types that might differ
+ * between platforms; don't use those values for new DLT_ types
+ * other than the corresponding DLT_ types.
+ */
+
+/*
+ * This is for Linux cooked sockets.
+ */
+#define DLT_LINUX_SLL	113
+
+/*
+ * Apple LocalTalk hardware.
+ */
+#define DLT_LTALK	114
+
+/*
+ * Acorn Econet.
+ */
+#define DLT_ECONET	115
+
+/*
+ * Reserved for use with OpenBSD ipfilter.
+ */
+#define DLT_IPFILTER	116
+
+/*
+ * OpenBSD DLT_PFLOG; DLT_PFLOG is 17 in OpenBSD, but that's DLT_LANE8023
+ * in SuSE 6.3, so we can't use 17 for it in capture-file headers.
+ *
+ * XXX: is there a conflict with DLT_PFSYNC 18 as well?
+ */
+#ifdef __OpenBSD__
+#define DLT_OLD_PFLOG	17
+#define DLT_PFSYNC	18
+#endif
+#define DLT_PFLOG	117
+
+/*
+ * Registered for Cisco-internal use.
+ */
+#define DLT_CISCO_IOS	118
+
+/*
+ * For 802.11 cards using the Prism II chips, with a link-layer
+ * header including Prism monitor mode information plus an 802.11
+ * header.
+ */
+#define DLT_PRISM_HEADER	119
+
+/*
+ * Reserved for Aironet 802.11 cards, with an Aironet link-layer header
+ * (see Doug Ambrisko's FreeBSD patches).
+ */
+#define DLT_AIRONET_HEADER	120
+
+/*
+ * Reserved for Siemens HiPath HDLC.
+ */
+#define DLT_HHDLC		121
+
+/*
+ * This is for RFC 2625 IP-over-Fibre Channel.
+ *
+ * This is not for use with raw Fibre Channel, where the link-layer
+ * header starts with a Fibre Channel frame header; it's for IP-over-FC,
+ * where the link-layer header starts with an RFC 2625 Network_Header
+ * field.
+ */
+#define DLT_IP_OVER_FC		122
+
+/*
+ * This is for Full Frontal ATM on Solaris with SunATM, with a
+ * pseudo-header followed by an AALn PDU.
+ *
+ * There may be other forms of Full Frontal ATM on other OSes,
+ * with different pseudo-headers.
+ *
+ * If ATM software returns a pseudo-header with VPI/VCI information
+ * (and, ideally, packet type information, e.g. signalling, ILMI,
+ * LANE, LLC-multiplexed traffic, etc.), it should not use
+ * DLT_ATM_RFC1483, but should get a new DLT_ value, so tcpdump
+ * and the like don't have to infer the presence or absence of a
+ * pseudo-header and the form of the pseudo-header.
+ */
+#define DLT_SUNATM		123	/* Solaris+SunATM */
+
+/* 
+ * Reserved as per request from Kent Dahlgren 
+ * for private use.
+ */
+#define DLT_RIO                 124     /* RapidIO */
+#define DLT_PCI_EXP             125     /* PCI Express */
+#define DLT_AURORA              126     /* Xilinx Aurora link layer */
+
+/*
+ * Header for 802.11 plus a number of bits of link-layer information
+ * including radio information, used by some recent BSD drivers as
+ * well as the madwifi Atheros driver for Linux.
+ */
+#define DLT_IEEE802_11_RADIO	127	/* 802.11 plus radiotap radio header */
+
+/*
+ * Reserved for the TZSP encapsulation, as per request from
+ * Chris Waters 
+ * TZSP is a generic encapsulation for any other link type,
+ * which includes a means to include meta-information
+ * with the packet, e.g. signal strength and channel
+ * for 802.11 packets.
+ */
+#define DLT_TZSP                128     /* Tazmen Sniffer Protocol */
+
+/*
+ * BSD's ARCNET headers have the source host, destination host,
+ * and type at the beginning of the packet; that's what's handed
+ * up to userland via BPF.
+ *
+ * Linux's ARCNET headers, however, have a 2-byte offset field
+ * between the host IDs and the type; that's what's handed up
+ * to userland via PF_PACKET sockets.
+ *
+ * We therefore have to have separate DLT_ values for them.
+ */
+#define DLT_ARCNET_LINUX	129	/* ARCNET */
+
+/*
+ * Juniper-private data link types, as per request from
+ * Hannes Gredler .  The DLT_s are used
+ * for passing on chassis-internal metainformation such as
+ * QOS profiles, etc..
+ */
+#define DLT_JUNIPER_MLPPP       130
+#define DLT_JUNIPER_MLFR        131
+#define DLT_JUNIPER_ES          132
+#define DLT_JUNIPER_GGSN        133
+#define DLT_JUNIPER_MFR         134
+#define DLT_JUNIPER_ATM2        135
+#define DLT_JUNIPER_SERVICES    136
+#define DLT_JUNIPER_ATM1        137
+
+/*
+ * Apple IP-over-IEEE 1394, as per a request from Dieter Siegmund
+ * .  The header that's presented is an Ethernet-like
+ * header:
+ *
+ *	#define FIREWIRE_EUI64_LEN	8
+ *	struct firewire_header {
+ *		u_char  firewire_dhost[FIREWIRE_EUI64_LEN];
+ *		u_char  firewire_shost[FIREWIRE_EUI64_LEN];
+ *		u_short firewire_type;
+ *	};
+ *
+ * with "firewire_type" being an Ethernet type value, rather than,
+ * for example, raw GASP frames being handed up.
+ */
+#define DLT_APPLE_IP_OVER_IEEE1394	138
+
+/*
+ * Various SS7 encapsulations, as per a request from Jeff Morriss
+ *  and subsequent discussions.
+ */
+#define DLT_MTP2_WITH_PHDR	139	/* pseudo-header with various info, followed by MTP2 */
+#define DLT_MTP2		140	/* MTP2, without pseudo-header */
+#define DLT_MTP3		141	/* MTP3, without pseudo-header or MTP2 */
+#define DLT_SCCP		142	/* SCCP, without pseudo-header or MTP2 or MTP3 */
+
+/*
+ * DOCSIS MAC frames.
+ */
+#define DLT_DOCSIS		143
+
+/*
+ * Linux-IrDA packets. Protocol defined at http://www.irda.org.
+ * Those packets include IrLAP headers and above (IrLMP...), but
+ * don't include Phy framing (SOF/EOF/CRC & byte stuffing), because Phy
+ * framing can be handled by the hardware and depend on the bitrate.
+ * This is exactly the format you would get capturing on a Linux-IrDA
+ * interface (irdaX), but not on a raw serial port.
+ * Note the capture is done in "Linux-cooked" mode, so each packet include
+ * a fake packet header (struct sll_header). This is because IrDA packet
+ * decoding is dependant on the direction of the packet (incomming or
+ * outgoing).
+ * When/if other platform implement IrDA capture, we may revisit the
+ * issue and define a real DLT_IRDA...
+ * Jean II
+ */
+#define DLT_LINUX_IRDA		144
+
+/*
+ * Reserved for IBM SP switch and IBM Next Federation switch.
+ */
+#define DLT_IBM_SP		145
+#define DLT_IBM_SN		146
+
+/*
+ * Reserved for private use.  If you have some link-layer header type
+ * that you want to use within your organization, with the capture files
+ * using that link-layer header type not ever be sent outside your
+ * organization, you can use these values.
+ *
+ * No libpcap release will use these for any purpose, nor will any
+ * tcpdump release use them, either.
+ *
+ * Do *NOT* use these in capture files that you expect anybody not using
+ * your private versions of capture-file-reading tools to read; in
+ * particular, do *NOT* use them in products, otherwise you may find that
+ * people won't be able to use tcpdump, or snort, or Ethereal, or... to
+ * read capture files from your firewall/intrusion detection/traffic
+ * monitoring/etc. appliance, or whatever product uses that DLT_ value,
+ * and you may also find that the developers of those applications will
+ * not accept patches to let them read those files.
+ *
+ * Also, do not use them if somebody might send you a capture using them
+ * for *their* private type and tools using them for *your* private type
+ * would have to read them.
+ *
+ * Instead, ask "tcpdump-workers@lists.tcpdump.org" for a new DLT_ value,
+ * as per the comment above, and use the type you're given.
+ */
+#define DLT_USER0		147
+#define DLT_USER1		148
+#define DLT_USER2		149
+#define DLT_USER3		150
+#define DLT_USER4		151
+#define DLT_USER5		152
+#define DLT_USER6		153
+#define DLT_USER7		154
+#define DLT_USER8		155
+#define DLT_USER9		156
+#define DLT_USER10		157
+#define DLT_USER11		158
+#define DLT_USER12		159
+#define DLT_USER13		160
+#define DLT_USER14		161
+#define DLT_USER15		162
+
+/*
+ * For future use with 802.11 captures - defined by AbsoluteValue
+ * Systems to store a number of bits of link-layer information
+ * including radio information:
+ *
+ *	http://www.shaftnet.org/~pizza/software/capturefrm.txt
+ *
+ * but it might be used by some non-AVS drivers now or in the
+ * future.
+ */
+#define DLT_IEEE802_11_RADIO_AVS 163	/* 802.11 plus AVS radio header */
+
+/*
+ * Juniper-private data link type, as per request from
+ * Hannes Gredler .  The DLT_s are used
+ * for passing on chassis-internal metainformation such as
+ * QOS profiles, etc..
+ */
+#define DLT_JUNIPER_MONITOR     164
+
+/*
+ * Reserved for BACnet MS/TP.
+ */
+#define DLT_BACNET_MS_TP	165
+
+/*
+ * Another PPP variant as per request from Karsten Keil .
+ *
+ * This is used in some OSes to allow a kernel socket filter to distinguish
+ * between incoming and outgoing packets, on a socket intended to
+ * supply pppd with outgoing packets so it can do dial-on-demand and
+ * hangup-on-lack-of-demand; incoming packets are filtered out so they
+ * don't cause pppd to hold the connection up (you don't want random
+ * input packets such as port scans, packets from old lost connections,
+ * etc. to force the connection to stay up).
+ *
+ * The first byte of the PPP header (0xff03) is modified to accomodate
+ * the direction - 0x00 = IN, 0x01 = OUT.
+ */
+#define DLT_PPP_PPPD		166
+
+/*
+ * Names for backwards compatibility with older versions of some PPP
+ * software; new software should use DLT_PPP_PPPD.
+ */
+#define DLT_PPP_WITH_DIRECTION	DLT_PPP_PPPD
+#define DLT_LINUX_PPP_WITHDIRECTION	DLT_PPP_PPPD
+
+/*
+ * Juniper-private data link type, as per request from
+ * Hannes Gredler .  The DLT_s are used
+ * for passing on chassis-internal metainformation such as
+ * QOS profiles, cookies, etc..
+ */
+#define DLT_JUNIPER_PPPOE       167
+#define DLT_JUNIPER_PPPOE_ATM   168
+
+#define DLT_GPRS_LLC		169	/* GPRS LLC */
+#define DLT_GPF_T		170	/* GPF-T (ITU-T G.7041/Y.1303) */
+#define DLT_GPF_F		171	/* GPF-F (ITU-T G.7041/Y.1303) */
+
+/*
+ * Requested by Oolan Zimmer  for use in Gcom's T1/E1 line
+ * monitoring equipment.
+ */
+#define DLT_GCOM_T1E1		172
+#define DLT_GCOM_SERIAL		173
+
+/*
+ * Juniper-private data link type, as per request from
+ * Hannes Gredler .  The DLT_ is used
+ * for internal communication to Physical Interface Cards (PIC)
+ */
+#define DLT_JUNIPER_PIC_PEER    174
+
+/*
+ * Link types requested by Gregor Maier  of Endace
+ * Measurement Systems.  They add an ERF header (see
+ * http://www.endace.com/support/EndaceRecordFormat.pdf) in front of
+ * the link-layer header.
+ */
+#define DLT_ERF_ETH		175	/* Ethernet */
+#define DLT_ERF_POS		176	/* Packet-over-SONET */
+
+/*
+ * Requested by Daniele Orlandi  for raw LAPD
+ * for vISDN (http://www.orlandi.com/visdn/).  Its link-layer header
+ * includes additional information before the LAPD header, so it's
+ * not necessarily a generic LAPD header.
+ */
+#define DLT_LINUX_LAPD		177
+
+/*
+ * Juniper-private data link type, as per request from
+ * Hannes Gredler . 
+ * The DLT_ are used for prepending meta-information
+ * like interface index, interface name
+ * before standard Ethernet, PPP, Frelay & C-HDLC Frames
+ */
+#define DLT_JUNIPER_ETHER       178
+#define DLT_JUNIPER_PPP         179
+#define DLT_JUNIPER_FRELAY      180
+#define DLT_JUNIPER_CHDLC       181
+
+/*
+ * Multi Link Frame Relay (FRF.16)
+ */
+#define DLT_MFR                 182
+
+/*
+ * Juniper-private data link type, as per request from
+ * Hannes Gredler . 
+ * The DLT_ is used for internal communication with a
+ * voice Adapter Card (PIC)
+ */
+#define DLT_JUNIPER_VP          183
+
+/*
+ * Arinc 429 frames.
+ * DLT_ requested by Gianluca Varenni .
+ * Every frame contains a 32bit A429 label.
+ * More documentation on Arinc 429 can be found at
+ * http://www.condoreng.com/support/downloads/tutorials/ARINCTutorial.pdf
+ */
+#define DLT_A429                184
+
+/*
+ * Arinc 653 Interpartition Communication messages.
+ * DLT_ requested by Gianluca Varenni .
+ * Please refer to the A653-1 standard for more information.
+ */
+#define DLT_A653_ICM            185
+
+/*
+ * USB packets, beginning with a USB setup header; requested by
+ * Paolo Abeni .
+ */
+#define DLT_USB			186
+
+/*
+ * Bluetooth HCI UART transport layer (part H:4); requested by
+ * Paolo Abeni.
+ */
+#define DLT_BLUETOOTH_HCI_H4	187
+
+/*
+ * IEEE 802.16 MAC Common Part Sublayer; requested by Maria Cruz
+ * .
+ */
+#define DLT_IEEE802_16_MAC_CPS	188
+
+/*
+ * USB packets, beginning with a Linux USB header; requested by
+ * Paolo Abeni .
+ */
+#define DLT_USB_LINUX		189
+
+/*
+ * Controller Area Network (CAN) v. 2.0B packets.
+ * DLT_ requested by Gianluca Varenni .
+ * Used to dump CAN packets coming from a CAN Vector board.
+ * More documentation on the CAN v2.0B frames can be found at
+ * http://www.can-cia.org/downloads/?269
+ */
+#define DLT_CAN20B              190
+
+/*
+ * IEEE 802.15.4, with address fields padded, as is done by Linux
+ * drivers; requested by Juergen Schimmer.
+ */
+#define DLT_IEEE802_15_4_LINUX	191
+
+/*
+ * Per Packet Information encapsulated packets.
+ * DLT_ requested by Gianluca Varenni .
+ */
+#define DLT_PPI			192
+
+/*
+ * Header for 802.16 MAC Common Part Sublayer plus a radiotap radio header;
+ * requested by Charles Clancy.
+ */
+#define DLT_IEEE802_16_MAC_CPS_RADIO	193
+
+/*
+ * Juniper-private data link type, as per request from
+ * Hannes Gredler . 
+ * The DLT_ is used for internal communication with a
+ * integrated service module (ISM).
+ */
+#define DLT_JUNIPER_ISM         194
+
+/*
+ * IEEE 802.15.4, exactly as it appears in the spec (no padding, no
+ * nothing); requested by Mikko Saarnivala .
+ */
+#define DLT_IEEE802_15_4	195
+
+/*
+ * Various link-layer types, with a pseudo-header, for SITA
+ * (http://www.sita.aero/); requested by Fulko Hew (fulko.hew@gmail.com).
+ */
+#define DLT_SITA		196
+
+/*
+ * Various link-layer types, with a pseudo-header, for Endace DAG cards;
+ * encapsulates Endace ERF records.  Requested by Stephen Donnelly
+ * .
+ */
+#define DLT_ERF			197
+
+/*
+ * Special header prepended to Ethernet packets when capturing from a
+ * u10 Networks board.  Requested by Phil Mulholland
+ * .
+ */
+#define DLT_RAIF1		198
+
+/*
+ * IPMB packet for IPMI, beginning with the I2C slave address, followed
+ * by the netFn and LUN, etc..  Requested by Chanthy Toeung
+ * .
+ */
+#define DLT_IPMB		199
+
+/*
+ * Juniper-private data link type, as per request from
+ * Hannes Gredler . 
+ * The DLT_ is used for capturing data on a secure tunnel interface.
+ */
+#define DLT_JUNIPER_ST          200
+
+/*
+ * Bluetooth HCI UART transport layer (part H:4), with pseudo-header
+ * that includes direction information; requested by Paolo Abeni.
+ */
+#define DLT_BLUETOOTH_HCI_H4_WITH_PHDR	201
+
+/*
+ * AX.25 packet with a 1-byte KISS header; see
+ *
+ *	http://www.ax25.net/kiss.htm
+ *
+ * as per Richard Stearn .
+ */
+#define DLT_AX25_KISS		202
+
+/*
+ * LAPD packets from an ISDN channel, starting with the address field,
+ * with no pseudo-header.
+ * Requested by Varuna De Silva .
+ */
+#define DLT_LAPD		203
+
+/*
+ * Variants of various link-layer headers, with a one-byte direction
+ * pseudo-header prepended - zero means "received by this host",
+ * non-zero (any non-zero value) means "sent by this host" - as per
+ * Will Barker .
+ */
+#define DLT_PPP_WITH_DIR	204	/* PPP - don't confuse with DLT_PPP_WITH_DIRECTION */
+#define DLT_C_HDLC_WITH_DIR	205	/* Cisco HDLC */
+#define DLT_FRELAY_WITH_DIR	206	/* Frame Relay */
+#define DLT_LAPB_WITH_DIR	207	/* LAPB */
+
+/*
+ * 208 is reserved for an as-yet-unspecified proprietary link-layer
+ * type, as requested by Will Barker.
+ */
+
+/*
+ * IPMB with a Linux-specific pseudo-header; as requested by Alexey Neyman
+ * .
+ */
+#define DLT_IPMB_LINUX		209
+
+/*
+ * FlexRay automotive bus - http://www.flexray.com/ - as requested
+ * by Hannes Kaelber .
+ */
+#define DLT_FLEXRAY		210
+
+/*
+ * Media Oriented Systems Transport (MOST) bus for multimedia
+ * transport - http://www.mostcooperation.com/ - as requested
+ * by Hannes Kaelber .
+ */
+#define DLT_MOST		211
+
+/*
+ * Local Interconnect Network (LIN) bus for vehicle networks -
+ * http://www.lin-subbus.org/ - as requested by Hannes Kaelber
+ * .
+ */
+#define DLT_LIN			212
+
+/*
+ * X2E-private data link type used for serial line capture,
+ * as requested by Hannes Kaelber .
+ */
+#define DLT_X2E_SERIAL		213
+
+/*
+ * X2E-private data link type used for the Xoraya data logger
+ * family, as requested by Hannes Kaelber .
+ */
+#define DLT_X2E_XORAYA		214
+
+/*
+ * IEEE 802.15.4, exactly as it appears in the spec (no padding, no
+ * nothing), but with the PHY-level data for non-ASK PHYs (4 octets
+ * of 0 as preamble, one octet of SFD, one octet of frame length+
+ * reserved bit, and then the MAC-layer data, starting with the
+ * frame control field).
+ *
+ * Requested by Max Filippov .
+ */
+#define DLT_IEEE802_15_4_NONASK_PHY	215
+
+
+/*
+ * DLT and savefile link type values are split into a class and
+ * a member of that class.  A class value of 0 indicates a regular
+ * DLT_/LINKTYPE_ value.
+ */
+#define DLT_CLASS(x)		((x) & 0x03ff0000)
+
+/*
+ * NetBSD-specific generic "raw" link type.  The class value indicates
+ * that this is the generic raw type, and the lower 16 bits are the
+ * address family we're dealing with.  Those values are NetBSD-specific;
+ * do not assume that they correspond to AF_ values for your operating
+ * system.
+ */
+#define	DLT_CLASS_NETBSD_RAWAF	0x02240000
+#define	DLT_NETBSD_RAWAF(af)	(DLT_CLASS_NETBSD_RAWAF | (af))
+#define	DLT_NETBSD_RAWAF_AF(x)	((x) & 0x0000ffff)
+#define	DLT_IS_NETBSD_RAWAF(x)	(DLT_CLASS(x) == DLT_CLASS_NETBSD_RAWAF)
+
+
+/*
+ * The instruction encodings.
+ */
+/* instruction classes */
+#define BPF_CLASS(code) ((code) & 0x07)
+#define		BPF_LD		0x00
+#define		BPF_LDX		0x01
+#define		BPF_ST		0x02
+#define		BPF_STX		0x03
+#define		BPF_ALU		0x04
+#define		BPF_JMP		0x05
+#define		BPF_RET		0x06
+#define		BPF_MISC	0x07
+
+/* ld/ldx fields */
+#define BPF_SIZE(code)	((code) & 0x18)
+#define		BPF_W		0x00
+#define		BPF_H		0x08
+#define		BPF_B		0x10
+#define BPF_MODE(code)	((code) & 0xe0)
+#define		BPF_IMM 	0x00
+#define		BPF_ABS		0x20
+#define		BPF_IND		0x40
+#define		BPF_MEM		0x60
+#define		BPF_LEN		0x80
+#define		BPF_MSH		0xa0
+
+/* alu/jmp fields */
+#define BPF_OP(code)	((code) & 0xf0)
+#define		BPF_ADD		0x00
+#define		BPF_SUB		0x10
+#define		BPF_MUL		0x20
+#define		BPF_DIV		0x30
+#define		BPF_OR		0x40
+#define		BPF_AND		0x50
+#define		BPF_LSH		0x60
+#define		BPF_RSH		0x70
+#define		BPF_NEG		0x80
+#define		BPF_JA		0x00
+#define		BPF_JEQ		0x10
+#define		BPF_JGT		0x20
+#define		BPF_JGE		0x30
+#define		BPF_JSET	0x40
+#define BPF_SRC(code)	((code) & 0x08)
+#define		BPF_K		0x00
+#define		BPF_X		0x08
+
+/* ret - BPF_K and BPF_X also apply */
+#define BPF_RVAL(code)	((code) & 0x18)
+#define		BPF_A		0x10
+
+/* misc */
+#define BPF_MISCOP(code) ((code) & 0xf8)
+#define		BPF_TAX		0x00
+#define		BPF_TXA		0x80
+
+/*
+ * The instruction data structure.
+ */
+struct bpf_insn {
+	u_short	code;
+	u_char 	jt;
+	u_char 	jf;
+	bpf_u_int32 k;
+};
+
+/*
+ * Macros for insn array initializers.
+ */
+#define BPF_STMT(code, k) { (u_short)(code), 0, 0, k }
+#define BPF_JUMP(code, k, jt, jf) { (u_short)(code), jt, jf, k }
+
+#if __STDC__ || defined(__cplusplus)
+extern int bpf_validate(const struct bpf_insn *, int);
+extern u_int bpf_filter(const struct bpf_insn *, const u_char *, u_int, u_int);
+#else
+extern int bpf_validate();
+extern u_int bpf_filter();
+#endif
+
+/*
+ * Number of scratch memory words (for BPF_LD|BPF_MEM and BPF_ST).
+ */
+#define BPF_MEMWORDS 16
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/namedb.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/namedb.h
new file mode 100644
index 0000000..9002c75
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/namedb.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 1994, 1996
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the Computer Systems
+ *	Engineering Group at Lawrence Berkeley Laboratory.
+ * 4. Neither the name of the University nor of the Laboratory may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#) $Header: /tcpdump/master/libpcap/pcap/namedb.h,v 1.1 2006/10/04 18:09:22 guy Exp $ (LBL)
+ */
+
+#ifndef lib_pcap_namedb_h
+#define lib_pcap_namedb_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * As returned by the pcap_next_etherent()
+ * XXX this stuff doesn't belong in this interface, but this
+ * library already must do name to address translation, so
+ * on systems that don't have support for /etc/ethers, we
+ * export these hooks since they'll
+ */
+struct pcap_etherent {
+	u_char addr[6];
+	char name[122];
+};
+#ifndef PCAP_ETHERS_FILE
+#define PCAP_ETHERS_FILE "/etc/ethers"
+#endif
+struct	pcap_etherent *pcap_next_etherent(FILE *);
+u_char *pcap_ether_hostton(const char*);
+u_char *pcap_ether_aton(const char *);
+
+bpf_u_int32 **pcap_nametoaddr(const char *);
+#ifdef INET6
+struct addrinfo *pcap_nametoaddrinfo(const char *);
+#endif
+bpf_u_int32 pcap_nametonetaddr(const char *);
+
+int	pcap_nametoport(const char *, int *, int *);
+int	pcap_nametoportrange(const char *, int *, int *, int *);
+int	pcap_nametoproto(const char *);
+int	pcap_nametoeproto(const char *);
+int	pcap_nametollc(const char *);
+/*
+ * If a protocol is unknown, PROTO_UNDEF is returned.
+ * Also, pcap_nametoport() returns the protocol along with the port number.
+ * If there are ambiguous entried in /etc/services (i.e. domain
+ * can be either tcp or udp) PROTO_UNDEF is returned.
+ */
+#define PROTO_UNDEF		-1
+
+/* XXX move these to pcap-int.h? */
+int __pcap_atodn(const char *, bpf_u_int32 *);
+int __pcap_atoin(const char *, bpf_u_int32 *);
+u_short	__pcap_nametodnaddr(const char *);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/sll.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/sll.h
new file mode 100644
index 0000000..e9d5452
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/sll.h
@@ -0,0 +1,129 @@
+/*-
+ * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * This code is derived from the Stanford/CMU enet packet filter,
+ * (net/enet.c) distributed as part of 4.3BSD, and code contributed
+ * to Berkeley by Steven McCanne and Van Jacobson both of Lawrence
+ * Berkeley Laboratory.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by the University of
+ *      California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#) $Header: /tcpdump/master/libpcap/pcap/sll.h,v 1.2.2.1 2008-05-30 01:36:06 guy Exp $ (LBL)
+ */
+
+/*
+ * For captures on Linux cooked sockets, we construct a fake header
+ * that includes:
+ *
+ *	a 2-byte "packet type" which is one of:
+ *
+ *		LINUX_SLL_HOST		packet was sent to us
+ *		LINUX_SLL_BROADCAST	packet was broadcast
+ *		LINUX_SLL_MULTICAST	packet was multicast
+ *		LINUX_SLL_OTHERHOST	packet was sent to somebody else
+ *		LINUX_SLL_OUTGOING	packet was sent *by* us;
+ *
+ *	a 2-byte Ethernet protocol field;
+ *
+ *	a 2-byte link-layer type;
+ *
+ *	a 2-byte link-layer address length;
+ *
+ *	an 8-byte source link-layer address, whose actual length is
+ *	specified by the previous value.
+ *
+ * All fields except for the link-layer address are in network byte order.
+ *
+ * DO NOT change the layout of this structure, or change any of the
+ * LINUX_SLL_ values below.  If you must change the link-layer header
+ * for a "cooked" Linux capture, introduce a new DLT_ type (ask
+ * "tcpdump-workers@lists.tcpdump.org" for one, so that you don't give it
+ * a value that collides with a value already being used), and use the
+ * new header in captures of that type, so that programs that can
+ * handle DLT_LINUX_SLL captures will continue to handle them correctly
+ * without any change, and so that capture files with different headers
+ * can be told apart and programs that read them can dissect the
+ * packets in them.
+ */
+
+#ifndef lib_pcap_sll_h
+#define lib_pcap_sll_h
+
+/*
+ * A DLT_LINUX_SLL fake link-layer header.
+ */
+#define SLL_HDR_LEN	16		/* total header length */
+#define SLL_ADDRLEN	8		/* length of address field */
+
+struct sll_header {
+	u_int16_t sll_pkttype;		/* packet type */
+	u_int16_t sll_hatype;		/* link-layer address type */
+	u_int16_t sll_halen;		/* link-layer address length */
+	u_int8_t sll_addr[SLL_ADDRLEN];	/* link-layer address */
+	u_int16_t sll_protocol;		/* protocol */
+};
+
+/*
+ * The LINUX_SLL_ values for "sll_pkttype"; these correspond to the
+ * PACKET_ values on Linux, but are defined here so that they're
+ * available even on systems other than Linux, and so that they
+ * don't change even if the PACKET_ values change.
+ */
+#define LINUX_SLL_HOST		0
+#define LINUX_SLL_BROADCAST	1
+#define LINUX_SLL_MULTICAST	2
+#define LINUX_SLL_OTHERHOST	3
+#define LINUX_SLL_OUTGOING	4
+
+/*
+ * The LINUX_SLL_ values for "sll_protocol"; these correspond to the
+ * ETH_P_ values on Linux, but are defined here so that they're
+ * available even on systems other than Linux.  We assume, for now,
+ * that the ETH_P_ values won't change in Linux; if they do, then:
+ *
+ *	if we don't translate them in "pcap-linux.c", capture files
+ *	won't necessarily be readable if captured on a system that
+ *	defines ETH_P_ values that don't match these values;
+ *
+ *	if we do translate them in "pcap-linux.c", that makes life
+ *	unpleasant for the BPF code generator, as the values you test
+ *	for in the kernel aren't the values that you test for when
+ *	reading a capture file, so the fixup code run on BPF programs
+ *	handed to the kernel ends up having to do more work.
+ *
+ * Add other values here as necessary, for handling packet types that
+ * might show up on non-Ethernet, non-802.x networks.  (Not all the ones
+ * in the Linux "if_ether.h" will, I suspect, actually show up in
+ * captures.)
+ */
+#define LINUX_SLL_P_802_3	0x0001	/* Novell 802.3 frames without 802.2 LLC header */
+#define LINUX_SLL_P_802_2	0x0004	/* 802.2 frames (not D/I/X Ethernet) */
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/usb.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/usb.h
new file mode 100644
index 0000000..adcd19c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/usb.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2006 Paolo Abeni (Italy)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote 
+ * products derived from this software without specific prior written 
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Basic USB data struct
+ * By Paolo Abeni 
+ *
+ * @(#) $Header: /tcpdump/master/libpcap/pcap/usb.h,v 1.6 2007/09/22 02:06:08 guy Exp $
+ */
+ 
+#ifndef _PCAP_USB_STRUCTS_H__
+#define _PCAP_USB_STRUCTS_H__
+
+/* 
+ * possible transfer mode
+ */
+#define URB_TRANSFER_IN   0x80
+#define URB_ISOCHRONOUS   0x0
+#define URB_INTERRUPT     0x1
+#define URB_CONTROL       0x2
+#define URB_BULK          0x3
+
+/*
+ * possible event type
+ */
+#define URB_SUBMIT        'S'
+#define URB_COMPLETE      'C'
+#define URB_ERROR         'E'
+
+/*
+ * USB setup header as defined in USB specification.
+ * Appears at the front of each packet in DLT_USB captures.
+ */
+typedef struct _usb_setup {
+	u_int8_t bmRequestType;
+	u_int8_t bRequest;
+	u_int16_t wValue;
+	u_int16_t wIndex;
+	u_int16_t wLength;
+} pcap_usb_setup;
+
+
+/*
+ * Header prepended by linux kernel to each event.
+ * Appears at the front of each packet in DLT_USB_LINUX captures.
+ */
+typedef struct _usb_header {
+	u_int64_t id;
+	u_int8_t event_type;
+	u_int8_t transfer_type;
+	u_int8_t endpoint_number;
+	u_int8_t device_address;
+	u_int16_t bus_id;
+	char setup_flag;/*if !=0 the urb setup header is not present*/
+	char data_flag; /*if !=0 no urb data is present*/
+	int64_t ts_sec;
+	int32_t ts_usec;
+	int32_t status;
+	u_int32_t urb_len;
+	u_int32_t data_len; /* amount of urb data really present in this event*/
+	pcap_usb_setup setup;
+} pcap_usb_header;
+
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/vlan.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/vlan.h
new file mode 100644
index 0000000..b0cb794
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/pcap/vlan.h
@@ -0,0 +1,46 @@
+/*-
+ * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by the University of
+ *      California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#) $Header: /tcpdump/master/libpcap/pcap/vlan.h,v 1.1.2.2 2008-08-06 07:45:59 guy Exp $
+ */
+
+#ifndef lib_pcap_vlan_h
+#define lib_pcap_vlan_h
+
+struct vlan_tag {
+	u_int16_t	vlan_tpid;		/* ETH_P_8021Q */
+	u_int16_t	vlan_tci;		/* VLAN TCI */
+};
+
+#define VLAN_TAG_LEN	4
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/remote-ext.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/remote-ext.h
new file mode 100644
index 0000000..9f54d69
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/remote-ext.h
@@ -0,0 +1,444 @@
+/*
+ * Copyright (c) 2002 - 2003
+ * NetGroup, Politecnico di Torino (Italy)
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met:
+ * 
+ * 1. Redistributions of source code must retain the above copyright 
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ * notice, this list of conditions and the following disclaimer in the 
+ * documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Politecnico di Torino nor the names of its 
+ * contributors may be used to endorse or promote products derived from 
+ * this software without specific prior written permission. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef __REMOTE_EXT_H__
+#define __REMOTE_EXT_H__
+
+
+#ifndef HAVE_REMOTE
+#error Please do not include this file directly. Just define HAVE_REMOTE and then include pcap.h
+#endif
+
+// Definition for Microsoft Visual Studio
+#if _MSC_VER > 1000
+#pragma once
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+	\file remote-ext.h
+
+	The goal of this file it to include most of the new definitions that should be
+	placed into the pcap.h file.
+
+	It includes all new definitions (structures and functions like pcap_open().
+    Some of the functions are not really a remote feature, but, right now, 
+	they are placed here.
+*/
+
+
+
+// All this stuff is public
+/*! \addtogroup remote_struct
+	\{
+*/
+
+
+
+
+/*!
+	\brief Defines the maximum buffer size in which address, port, interface names are kept.
+
+	In case the adapter name or such is larger than this value, it is truncated.
+	This is not used by the user; however it must be aware that an hostname / interface
+	name longer than this value will be truncated.
+*/
+#define PCAP_BUF_SIZE 1024
+
+
+/*! \addtogroup remote_source_ID
+	\{
+*/
+
+
+/*!
+	\brief Internal representation of the type of source in use (file, 
+	remote/local interface).
+
+	This indicates a file, i.e. the user want to open a capture from a local file.
+*/
+#define PCAP_SRC_FILE 2
+/*!
+	\brief Internal representation of the type of source in use (file, 
+	remote/local interface).
+
+	This indicates a local interface, i.e. the user want to open a capture from 
+	a local interface. This does not involve the RPCAP protocol.
+*/
+#define PCAP_SRC_IFLOCAL 3
+/*!
+	\brief Internal representation of the type of source in use (file, 
+	remote/local interface).
+
+	This indicates a remote interface, i.e. the user want to open a capture from 
+	an interface on a remote host. This does involve the RPCAP protocol.
+*/
+#define PCAP_SRC_IFREMOTE 4
+
+/*!
+	\}
+*/
+
+
+
+/*! \addtogroup remote_source_string
+
+	The formats allowed by the pcap_open() are the following:
+	- file://path_and_filename [opens a local file]
+	- rpcap://devicename [opens the selected device devices available on the local host, without using the RPCAP protocol]
+	- rpcap://host/devicename [opens the selected device available on a remote host]
+	- rpcap://host:port/devicename [opens the selected device available on a remote host, using a non-standard port for RPCAP]
+	- adaptername [to open a local adapter; kept for compability, but it is strongly discouraged]
+	- (NULL) [to open the first local adapter; kept for compability, but it is strongly discouraged]
+
+	The formats allowed by the pcap_findalldevs_ex() are the following:
+	- file://folder/ [lists all the files in the given folder]
+	- rpcap:// [lists all local adapters]
+	- rpcap://host:port/ [lists the devices available on a remote host]
+
+	Referring to the 'host' and 'port' paramters, they can be either numeric or literal. Since
+	IPv6 is fully supported, these are the allowed formats:
+
+	- host (literal): e.g. host.foo.bar
+	- host (numeric IPv4): e.g. 10.11.12.13
+	- host (numeric IPv4, IPv6 style): e.g. [10.11.12.13]
+	- host (numeric IPv6): e.g. [1:2:3::4]
+	- port: can be either numeric (e.g. '80') or literal (e.g. 'http')
+
+	Here you find some allowed examples:
+	- rpcap://host.foo.bar/devicename [everything literal, no port number]
+	- rpcap://host.foo.bar:1234/devicename [everything literal, with port number]
+	- rpcap://10.11.12.13/devicename [IPv4 numeric, no port number]
+	- rpcap://10.11.12.13:1234/devicename [IPv4 numeric, with port number]
+	- rpcap://[10.11.12.13]:1234/devicename [IPv4 numeric with IPv6 format, with port number]
+	- rpcap://[1:2:3::4]/devicename [IPv6 numeric, no port number]
+	- rpcap://[1:2:3::4]:1234/devicename [IPv6 numeric, with port number]
+	- rpcap://[1:2:3::4]:http/devicename [IPv6 numeric, with literal port number]
+	
+	\{
+*/
+
+
+/*!
+	\brief String that will be used to determine the type of source in use (file,
+	remote/local interface).
+
+	This string will be prepended to the interface name in order to create a string
+	that contains all the information required to open the source.
+
+	This string indicates that the user wants to open a capture from a local file.
+*/
+#define PCAP_SRC_FILE_STRING "file://"
+/*!
+	\brief String that will be used to determine the type of source in use (file,
+	remote/local interface).
+
+	This string will be prepended to the interface name in order to create a string
+	that contains all the information required to open the source.
+
+	This string indicates that the user wants to open a capture from a network interface.
+	This string does not necessarily involve the use of the RPCAP protocol. If the
+	interface required resides on the local host, the RPCAP protocol is not involved
+	and the local functions are used.
+*/
+#define PCAP_SRC_IF_STRING "rpcap://"
+
+/*!
+	\}
+*/
+
+
+
+
+
+/*!
+	\addtogroup remote_open_flags
+	\{
+*/
+
+/*!
+	\brief Defines if the adapter has to go in promiscuous mode.
+
+	It is '1' if you have to open the adapter in promiscuous mode, '0' otherwise.
+	Note that even if this parameter is false, the interface could well be in promiscuous
+	mode for some other reason (for example because another capture process with 
+	promiscuous mode enabled is currently using that interface).
+	On on Linux systems with 2.2 or later kernels (that have the "any" device), this
+	flag does not work on the "any" device; if an argument of "any" is supplied,
+	the 'promisc' flag is ignored.
+*/
+#define PCAP_OPENFLAG_PROMISCUOUS		1
+
+/*!
+	\brief Defines if the data trasfer (in case of a remote
+	capture) has to be done with UDP protocol.
+
+	If it is '1' if you want a UDP data connection, '0' if you want
+	a TCP data connection; control connection is always TCP-based.
+	A UDP connection is much lighter, but it does not guarantee that all
+	the captured packets arrive to the client workstation. Moreover, 
+	it could be harmful in case of network congestion.
+	This flag is meaningless if the source is not a remote interface.
+	In that case, it is simply ignored.
+*/
+#define PCAP_OPENFLAG_DATATX_UDP			2
+
+
+/*!
+	\brief Defines if the remote probe will capture its own generated traffic.
+
+	In case the remote probe uses the same interface to capture traffic and to send
+	data back to the caller, the captured traffic includes the RPCAP traffic as well.
+	If this flag is turned on, the RPCAP traffic is excluded from the capture, so that
+	the trace returned back to the collector is does not include this traffic.
+*/
+#define PCAP_OPENFLAG_NOCAPTURE_RPCAP	4
+
+/*!
+	\brief Defines if the local adapter will capture its own generated traffic.
+
+	This flag tells the underlying capture driver to drop the packets that were sent by itself. 
+	This is usefult when building applications like bridges, that should ignore the traffic
+	they just sent.
+*/
+#define PCAP_OPENFLAG_NOCAPTURE_LOCAL	8
+
+/*!
+	\brief This flag configures the adapter for maximum responsiveness.
+
+	In presence of a large value for nbytes, WinPcap waits for the arrival of several packets before 
+	copying the data to the user. This guarantees a low number of system calls, i.e. lower processor usage, 
+	i.e. better performance, which is good for applications like sniffers. If the user sets the 
+	PCAP_OPENFLAG_MAX_RESPONSIVENESS flag, the capture driver will copy the packets as soon as the application 
+	is ready to receive them. This is suggested for real time applications (like, for example, a bridge) 
+	that need the best responsiveness.*/
+#define PCAP_OPENFLAG_MAX_RESPONSIVENESS	16
+
+/*!
+	\}
+*/
+
+
+/*!
+	\addtogroup remote_samp_methods
+	\{
+*/
+
+/*!
+	\brief No sampling has to be done on the current capture.
+
+	In this case, no sampling algorithms are applied to the current capture.
+*/
+#define PCAP_SAMP_NOSAMP	0
+
+/*!
+	\brief It defines that only 1 out of N packets must be returned to the user.
+
+	In this case, the 'value' field of the 'pcap_samp' structure indicates the
+	number of packets (minus 1) that must be discarded before one packet got accepted.
+	In other words, if 'value = 10', the first packet is returned to the caller, while
+	the following 9 are discarded.
+*/
+#define PCAP_SAMP_1_EVERY_N	1
+
+/*!
+	\brief It defines that we have to return 1 packet every N milliseconds.
+
+	In this case, the 'value' field of the 'pcap_samp' structure indicates the 'waiting
+	time' in milliseconds before one packet got accepted.
+	In other words, if 'value = 10', the first packet is returned to the caller; the next 
+	returned one will be the first packet that arrives when 10ms have elapsed. 
+*/
+#define PCAP_SAMP_FIRST_AFTER_N_MS 2
+
+/*!
+	\}
+*/
+
+
+/*!
+	\addtogroup remote_auth_methods
+	\{
+*/
+
+/*!
+	\brief It defines the NULL authentication.
+
+	This value has to be used within the 'type' member of the pcap_rmtauth structure.
+	The 'NULL' authentication has to be equal to 'zero', so that old applications
+	can just put every field of struct pcap_rmtauth to zero, and it does work.
+*/
+#define RPCAP_RMTAUTH_NULL 0
+/*!
+	\brief It defines the username/password authentication.
+
+	With this type of authentication, the RPCAP protocol will use the username/
+	password provided to authenticate the user on the remote machine. If the
+	authentication is successful (and the user has the right to open network devices)
+	the RPCAP connection will continue; otherwise it will be dropped.
+
+	This value has to be used within the 'type' member of the pcap_rmtauth structure.
+*/
+#define RPCAP_RMTAUTH_PWD 1
+
+/*!
+	\}
+*/
+
+
+
+
+/*!
+
+	\brief This structure keeps the information needed to autheticate
+	the user on a remote machine.
+	
+	The remote machine can either grant or refuse the access according 
+	to the information provided.
+	In case the NULL authentication is required, both 'username' and
+	'password' can be NULL pointers.
+	
+	This structure is meaningless if the source is not a remote interface;
+	in that case, the functions which requires such a structure can accept
+	a NULL pointer as well.
+*/
+struct pcap_rmtauth
+{
+	/*!
+		\brief Type of the authentication required.
+
+		In order to provide maximum flexibility, we can support different types
+		of authentication based on the value of this 'type' variable. The currently 
+		supported authentication methods are defined into the
+		\link remote_auth_methods Remote Authentication Methods Section\endlink.
+
+	*/
+	int type;
+	/*!
+		\brief Zero-terminated string containing the username that has to be 
+		used on the remote machine for authentication.
+		
+		This field is meaningless in case of the RPCAP_RMTAUTH_NULL authentication
+		and it can be NULL.
+	*/
+	char *username;
+	/*!
+		\brief Zero-terminated string containing the password that has to be 
+		used on the remote machine for authentication.
+		
+		This field is meaningless in case of the RPCAP_RMTAUTH_NULL authentication
+		and it can be NULL.
+	*/
+	char *password;
+};
+
+
+/*!
+	\brief This structure defines the information related to sampling.
+
+	In case the sampling is requested, the capturing device should read
+	only a subset of the packets coming from the source. The returned packets depend
+	on the sampling parameters.
+
+	\warning The sampling process is applied after the filtering process.
+	In other words, packets are filtered first, then the sampling process selects a
+	subset of the 'filtered' packets and it returns them to the caller.
+*/
+struct pcap_samp
+{
+	/*!
+		Method used for sampling. Currently, the supported methods are listed in the
+		\link remote_samp_methods Sampling Methods Section\endlink.
+	*/
+	int method;
+
+	/*!
+		This value depends on the sampling method defined. For its meaning, please check
+		at the \link remote_samp_methods Sampling Methods Section\endlink.
+	*/
+	int value;
+};
+
+
+
+
+//! Maximum lenght of an host name (needed for the RPCAP active mode)
+#define RPCAP_HOSTLIST_SIZE 1024
+
+
+/*!
+	\}
+*/ // end of public documentation
+
+
+// Exported functions
+
+
+
+/** \name New WinPcap functions
+
+	This section lists the new functions that are able to help considerably in writing
+	WinPcap programs because of their easiness of use.
+ */
+//\{
+pcap_t *pcap_open(const char *source, int snaplen, int flags, int read_timeout, struct pcap_rmtauth *auth, char *errbuf);
+int pcap_createsrcstr(char *source, int type, const char *host, const char *port, const char *name, char *errbuf);
+int pcap_parsesrcstr(const char *source, int *type, char *host, char *port, char *name, char *errbuf);
+int pcap_findalldevs_ex(char *source, struct pcap_rmtauth *auth, pcap_if_t **alldevs, char *errbuf);
+struct pcap_samp *pcap_setsampling(pcap_t *p);
+
+//\}
+// End of new winpcap functions
+
+
+
+/** \name Remote Capture functions
+ */
+//\{ 
+SOCKET pcap_remoteact_accept(const char *address, const char *port, const char *hostlist, char *connectinghost, struct pcap_rmtauth *auth, char *errbuf);
+int pcap_remoteact_list(char *hostlist, char sep, int size, char *errbuf);
+int pcap_remoteact_close(const char *host, char *errbuf);
+void pcap_remoteact_cleanup();
+//\}
+// End of remote capture functions
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/wpcap.lib b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/wpcap.lib
new file mode 100644
index 0000000..f832e04
Binary files /dev/null and b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/wpcap.lib differ
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/ethernetif.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/ethernetif.c
new file mode 100644
index 0000000..bebadc5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/ethernetif.c
@@ -0,0 +1,615 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* WinPCap includes. */
+#define HAVE_REMOTE
+#include "pcap.h"
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* lwIP includes. */
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include 
+#include 
+#include "netif/etharp.h"
+
+/* Define those to better describe your network interface. */
+#define IFNAME0 'w'
+#define IFNAME1 'p'
+
+#define netifMAX_MTU 1500
+
+struct xEthernetIf
+{
+	struct eth_addr *ethaddr;
+	/* Add whatever per-interface state that is needed here. */
+};
+
+/*
+ * Place received packet in a pbuf and send a message to the tcpip task to let
+ * it know new data has arrived.
+ */
+static void prvEthernetInput( const unsigned char * const pucInputData, long lInputLength );
+
+/*
+ * Copy the received data into a pbuf.
+ */
+static struct pbuf *prvLowLevelInput( const unsigned char * const pucInputData, long lDataLength );
+
+/*
+ * Send data from a pbuf to the hardware.
+ */
+static err_t prvLowLevelOutput( struct netif *pxNetIf, struct pbuf *p );
+
+/*
+ * Perform any hardware and/or driver initialisation necessary.
+ */
+static void prvLowLevelInit( struct netif *pxNetIf );
+
+/*
+ * Query the computer the simulation is being executed on to find the network
+ * interfaces it has installed.
+ */
+static pcap_if_t * prvPrintAvailableNetworkInterfaces( void );
+
+/*
+ * Open the network interface.  The number of the interface to be opened is set
+ * by the configNETWORK_INTERFACE_TO_USE constant in FreeRTOSConfig.h.
+ */
+static void prvOpenSelectedNetworkInterface( pcap_if_t *pxAllNetworkInterfaces );
+
+/*
+ * Interrupts cannot truely be simulated using WinPCap.  In reality this task
+ * just polls the interface. 
+ */
+static void prvInterruptSimulator( void *pvParameters );
+
+/*
+ * Configure the capture filter to allow blocking reads, and to filter out
+ * packets that are not of interest to this demo.
+ */
+static void prvConfigureCaptureBehaviour( void );
+
+/*-----------------------------------------------------------*/
+
+/* The WinPCap interface being used. */
+static pcap_t *pxOpenedInterfaceHandle = NULL;
+
+/* Parameter required for WinPCap API functions. */
+static char cErrorBuffer[ PCAP_ERRBUF_SIZE ];
+
+/* The network interface that was opened. */
+static struct netif *pxlwIPNetIf = NULL;
+
+/*-----------------------------------------------------------*/
+
+/**
+ * In this function, the hardware should be initialized.
+ * Called from ethernetif_init().
+ *
+ * @param pxNetIf the already initialized lwip network interface structure
+ *		for this ethernetif.
+ */
+static void prvLowLevelInit( struct netif *pxNetIf )
+{
+pcap_if_t *pxAllNetworkInterfaces;
+  
+	/* set MAC hardware address length */
+	pxNetIf->hwaddr_len = ETHARP_HWADDR_LEN;
+
+	/* set MAC hardware address */
+	pxNetIf->hwaddr[ 0 ] = configMAC_ADDR0;
+	pxNetIf->hwaddr[ 1 ] = configMAC_ADDR1;
+	pxNetIf->hwaddr[ 2 ] = configMAC_ADDR2;
+	pxNetIf->hwaddr[ 3 ] = configMAC_ADDR3;
+	pxNetIf->hwaddr[ 4 ] = configMAC_ADDR4;
+	pxNetIf->hwaddr[ 5 ] = configMAC_ADDR5;
+
+	/* device capabilities */
+	/* don't set pxNetIf_FLAG_ETHARP if this device is not an ethernet one */
+	pxNetIf->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
+ 
+	/* Query the computer the simulation is being executed on to find the 
+	network interfaces it has installed. */
+	pxAllNetworkInterfaces = prvPrintAvailableNetworkInterfaces();
+	
+	/* Open the network interface.  The number of the interface to be opened is 
+	set by the configNETWORK_INTERFACE_TO_USE constant in FreeRTOSConfig.h.
+	Calling this function will set the pxOpenedInterfaceHandle variable.  If,
+	after calling this function, pxOpenedInterfaceHandle is equal to NULL, then
+	the interface could not be opened. */
+	if( pxAllNetworkInterfaces != NULL )
+	{
+		prvOpenSelectedNetworkInterface( pxAllNetworkInterfaces );
+	}
+
+	/* Remember which interface was opened as it is used in the interrupt 
+	simulator task. */
+	pxlwIPNetIf = pxNetIf;
+}
+
+/**
+ * This function should do the actual transmission of the packet. The packet is
+ * contained in the pbuf that is passed to the function. This pbuf
+ * might be chained.
+ *
+ * @param pxNetIf the lwip network interface structure for this ethernetif
+ * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)
+ * @return ERR_OK if the packet could be sent
+ *		 an err_t value if the packet couldn't be sent
+ *
+ * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to
+ *	   strange results. You might consider waiting for space in the DMA queue
+ *	   to become availale since the stack doesn't retry to send a packet
+ *	   dropped because of memory failure (except for the TCP timers).
+ */
+
+static err_t prvLowLevelOutput( struct netif *pxNetIf, struct pbuf *p )
+{
+
+	/* This is taken from lwIP example code and therefore does not conform
+	to the FreeRTOS coding standard. */
+
+struct pbuf *q;
+static unsigned char ucBuffer[ 1520 ];
+unsigned char *pucBuffer = ucBuffer;
+unsigned char *pucChar;
+struct eth_hdr *pxHeader;
+u16_t usTotalLength = p->tot_len - ETH_PAD_SIZE;
+err_t xReturn = ERR_OK;
+
+	( void ) pxNetIf;
+
+	#if defined(LWIP_DEBUG) && LWIP_NETIF_TX_SINGLE_PBUF
+		LWIP_ASSERT("p->next == NULL && p->len == p->tot_len", p->next == NULL && p->len == p->tot_len);
+	#endif
+
+	/* Initiate transfer. */
+	if( p->len == p->tot_len ) 
+	{
+		/* No pbuf chain, don't have to copy -> faster. */
+		pucBuffer = &( ( unsigned char * ) p->payload )[ ETH_PAD_SIZE ];
+	} 
+	else 
+	{
+		/* pbuf chain, copy into contiguous ucBuffer. */
+		if( p->tot_len >= sizeof( ucBuffer ) ) 
+		{
+			LINK_STATS_INC( link.lenerr );
+			LINK_STATS_INC( link.drop );
+			snmp_inc_ifoutdiscards( pxNetIf );
+			xReturn = ERR_BUF;
+		}
+		else
+		{
+			pucChar = ucBuffer;
+
+			for( q = p; q != NULL; q = q->next ) 
+			{
+				/* Send the data from the pbuf to the interface, one pbuf at a
+				time. The size of the data in each pbuf is kept in the ->len
+				variable. */
+				/* send data from(q->payload, q->len); */
+				LWIP_DEBUGF( NETIF_DEBUG, ("NETIF: send pucChar %p q->payload %p q->len %i q->next %p\n", pucChar, q->payload, ( int ) q->len, ( void* ) q->next ) );
+				if( q == p ) 
+				{
+					memcpy( pucChar, &( ( char * ) q->payload )[ ETH_PAD_SIZE ], q->len - ETH_PAD_SIZE );
+					pucChar += q->len - ETH_PAD_SIZE;
+				} 
+				else 
+				{
+					memcpy( pucChar, q->payload, q->len );
+					pucChar += q->len;
+				}
+			}
+		}
+	}
+
+	if( xReturn == ERR_OK )
+	{
+		/* signal that packet should be sent */
+		if( pcap_sendpacket( pxOpenedInterfaceHandle, pucBuffer, usTotalLength ) < 0 ) 
+		{
+			LINK_STATS_INC( link.memerr );
+			LINK_STATS_INC( link.drop );
+			snmp_inc_ifoutdiscards( pxNetIf );
+			xReturn = ERR_BUF;
+		}
+		else
+		{
+			LINK_STATS_INC( link.xmit );
+			snmp_add_ifoutoctets( pxNetIf, usTotalLength );
+			pxHeader = ( struct eth_hdr * )p->payload;
+
+			if( ( pxHeader->dest.addr[ 0 ] & 1 ) != 0 ) 
+			{
+				/* broadcast or multicast packet*/
+				snmp_inc_ifoutnucastpkts( pxNetIf );
+			} 
+			else 
+			{
+				/* unicast packet */
+				snmp_inc_ifoutucastpkts( pxNetIf );
+			}
+		}
+	}
+	
+	return xReturn;
+}
+
+/**
+ * Should allocate a pbuf and transfer the bytes of the incoming
+ * packet from the interface into the pbuf.
+ *
+ * @param pxNetIf the lwip network interface structure for this ethernetif
+ * @return a pbuf filled with the received packet (including MAC header)
+ *		 NULL on memory error
+ */
+static struct pbuf *prvLowLevelInput( const unsigned char * const pucInputData, long lDataLength )
+{
+struct pbuf *p = NULL, *q;
+
+	if( lDataLength > 0 )
+	{
+		#if ETH_PAD_SIZE
+			len += ETH_PAD_SIZE; /* allow room for Ethernet padding */
+		#endif
+
+		/* We allocate a pbuf chain of pbufs from the pool. */
+		p = pbuf_alloc( PBUF_RAW, lDataLength, PBUF_POOL );
+  
+		if( p != NULL ) 
+		{
+			#if ETH_PAD_SIZE
+				pbuf_header( p, -ETH_PAD_SIZE ); /* drop the padding word */
+			#endif
+
+			/* We iterate over the pbuf chain until we have read the entire
+			* packet into the pbuf. */
+			lDataLength = 0;
+			for( q = p; q != NULL; q = q->next ) 
+			{
+				/* Read enough bytes to fill this pbuf in the chain. The
+				* available data in the pbuf is given by the q->len
+				* variable.
+				* This does not necessarily have to be a memcpy, you can also preallocate
+				* pbufs for a DMA-enabled MAC and after receiving truncate it to the
+				* actually received size. In this case, ensure the usTotalLength member of the
+				* pbuf is the sum of the chained pbuf len members.
+				*/
+				memcpy( q->payload, &( pucInputData[ lDataLength ] ), q->len );
+				lDataLength += q->len;
+			}
+
+			#if ETH_PAD_SIZE
+				pbuf_header( p, ETH_PAD_SIZE ); /* reclaim the padding word */
+			#endif
+
+			LINK_STATS_INC( link.recv );
+		}
+	}
+
+	return p;  
+}
+
+/**
+ * This function should be called when a packet is ready to be read
+ * from the interface. It uses the function prvLowLevelInput() that
+ * should handle the actual reception of bytes from the network
+ * interface. Then the type of the received packet is determined and
+ * the appropriate input function is called.
+ *
+ * @param pxNetIf the lwip network interface structure for this ethernetif
+ */
+static void prvEthernetInput( const unsigned char * const pucInputData, long lInputLength )
+{
+	/* This is taken from lwIP example code and therefore does not conform
+	to the FreeRTOS coding standard. */
+	
+struct eth_hdr *pxHeader;
+struct pbuf *p;
+
+	/* move received packet into a new pbuf */
+	p = prvLowLevelInput( pucInputData, lInputLength );
+
+	/* no packet could be read, silently ignore this */
+	if( p != NULL ) 
+	{
+		/* points to packet payload, which starts with an Ethernet header */
+		pxHeader = p->payload;
+
+		switch( htons( pxHeader->type ) ) 
+		{
+			/* IP or ARP packet? */
+			case ETHTYPE_IP:
+			case ETHTYPE_ARP:
+								/* full packet send to tcpip_thread to process */
+								if( pxlwIPNetIf->input( p, pxlwIPNetIf ) != ERR_OK )
+								{ 
+									LWIP_DEBUGF(NETIF_DEBUG, ( "ethernetif_input: IP input error\n" ) );
+									pbuf_free(p);
+									p = NULL;
+								}
+								break;
+
+			default:
+								pbuf_free( p );
+								p = NULL;
+			break;
+		}
+	}
+}
+
+/**
+ * Should be called at the beginning of the program to set up the
+ * network interface. It calls the function prvLowLevelInit() to do the
+ * actual setup of the hardware.
+ *
+ * This function should be passed as a parameter to netif_add().
+ *
+ * @param pxNetIf the lwip network interface structure for this ethernetif
+ * @return ERR_OK if the loopif is initialized
+ *		 ERR_MEM if private data couldn't be allocated
+ *		 any other err_t on error
+ */
+err_t ethernetif_init( struct netif *pxNetIf )
+{
+err_t xReturn = ERR_OK;
+
+	/* This is taken from lwIP example code and therefore does not conform
+	to the FreeRTOS coding standard. */
+	
+struct xEthernetIf *pxEthernetIf;
+
+	LWIP_ASSERT( "pxNetIf != NULL", ( pxNetIf != NULL ) );
+	
+	pxEthernetIf = mem_malloc( sizeof( struct xEthernetIf ) );
+	if( pxEthernetIf == NULL ) 
+	{
+		LWIP_DEBUGF(NETIF_DEBUG, ( "ethernetif_init: out of memory\n" ) );
+		xReturn = ERR_MEM;
+	}
+	else
+	{
+		#if LWIP_NETIF_HOSTNAME
+		{
+			/* Initialize interface hostname */
+			pxNetIf->hostname = "lwip";
+		}
+		#endif /* LWIP_NETIF_HOSTNAME */
+
+		pxNetIf->state = pxEthernetIf;
+		pxNetIf->name[ 0 ] = IFNAME0;
+		pxNetIf->name[ 1 ] = IFNAME1;
+
+		/* We directly use etharp_output() here to save a function call.
+		* You can instead declare your own function an call etharp_output()
+		* from it if you have to do some checks before sending (e.g. if link
+		* is available...) */
+		pxNetIf->output = etharp_output;
+		pxNetIf->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_IGMP;
+		pxNetIf->hwaddr_len = ETHARP_HWADDR_LEN;
+		pxNetIf->mtu = netifMAX_MTU;
+		pxNetIf->linkoutput = prvLowLevelOutput;
+
+		pxEthernetIf->ethaddr = ( struct eth_addr * ) &( pxNetIf->hwaddr[ 0 ] );
+  
+		/* initialize the hardware */
+		prvLowLevelInit( pxNetIf );
+
+		/* Was an interface opened? */
+		if( pxOpenedInterfaceHandle == NULL )
+		{
+			/* Probably an invalid adapter number was defined in 
+			FreeRTOSConfig.h. */
+			xReturn = ERR_VAL;
+			configASSERT( pxOpenedInterfaceHandle );
+		}
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static pcap_if_t * prvPrintAvailableNetworkInterfaces( void )
+{	
+pcap_if_t * pxAllNetworkInterfaces = NULL, *xInterface;
+long lInterfaceNumber = 1;
+
+	if( pcap_findalldevs_ex( PCAP_SRC_IF_STRING, NULL, &pxAllNetworkInterfaces, cErrorBuffer ) == -1 )
+	{
+		printf( "\r\nCould not obtain a list of network interfaces\r\n%s\r\n", cErrorBuffer );
+		pxAllNetworkInterfaces = NULL;
+	}
+
+	if( pxAllNetworkInterfaces != NULL )
+	{
+		/* Print out the list of network interfaces.  The first in the list
+		is interface '1', not interface '0'. */
+		for( xInterface = pxAllNetworkInterfaces; xInterface != NULL; xInterface = xInterface->next )
+		{
+			printf( "%d. %s", lInterfaceNumber, xInterface->name );
+			
+			if( xInterface->description != NULL )
+			{
+				printf( " (%s)\r\n", xInterface->description );
+			}
+			else
+			{
+				printf( " (No description available)\r\n") ;
+			}
+			
+			lInterfaceNumber++;
+		}
+	}
+
+	if( lInterfaceNumber == 1 )
+	{
+		/* The interface number was never incremented, so the above for() loop
+		did not execute meaning no interfaces were found. */
+		printf( " \r\nNo network interfaces were found.\r\n" );
+		pxAllNetworkInterfaces = NULL;
+	}
+
+	printf( "\r\nThe interface that will be opened is set by configNETWORK_INTERFACE_TO_USE which should be defined in FreeRTOSConfig.h\r\n" );
+	printf( "Attempting to open interface number %d.\r\n", configNETWORK_INTERFACE_TO_USE );
+	
+	if( ( configNETWORK_INTERFACE_TO_USE < 1L ) || ( configNETWORK_INTERFACE_TO_USE > lInterfaceNumber ) )
+	{
+		printf("\r\nconfigNETWORK_INTERFACE_TO_USE is not in the valid range.\r\n" );
+		
+		if( pxAllNetworkInterfaces != NULL )
+		{
+			/* Free the device list, as no devices are going to be opened. */
+			pcap_freealldevs( pxAllNetworkInterfaces );
+			pxAllNetworkInterfaces = NULL;
+		}
+	}
+
+	return pxAllNetworkInterfaces;
+}
+/*-----------------------------------------------------------*/
+
+static void prvOpenSelectedNetworkInterface( pcap_if_t *pxAllNetworkInterfaces )
+{
+pcap_if_t *xInterface;
+long x;
+
+	/* Walk the list of devices until the selected device is located. */
+	xInterface = pxAllNetworkInterfaces;
+	for( x = 0L; x < ( configNETWORK_INTERFACE_TO_USE - 1L ); x++ )
+	{
+		xInterface = xInterface->next;
+	}
+
+	/* Open the selected interface. */
+	pxOpenedInterfaceHandle = pcap_open(	xInterface->name,		  	/* The name of the selected interface. */
+											netifMAX_MTU, 				/* The size of the packet to capture. */
+											PCAP_OPENFLAG_PROMISCUOUS,	/* Open in promiscious mode as the MAC and 
+																		IP address is going to be "simulated", and 
+																		not be the real MAC and IP address.  This allows
+																		trafic to the simulated IP address to be routed
+																		to uIP, and trafic to the real IP address to be
+																		routed to the Windows TCP/IP stack. */
+											0L,			 			/* The read time out.  This is going to block
+																		until data is available. */
+											NULL,			 			/* No authentication is required as this is
+																		not a remote capture session. */
+											cErrorBuffer			
+									   );
+									   
+	if ( pxOpenedInterfaceHandle == NULL )
+	{
+		printf( "\r\n%s is not supported by WinPcap and cannot be opened\r\n", xInterface->name );
+	}
+	else
+	{
+		/* Configure the capture filter to allow blocking reads, and to filter 
+		out packets that are not of interest to this demo. */
+		prvConfigureCaptureBehaviour();
+	}
+
+	/* The device list is no longer required. */
+	pcap_freealldevs( pxAllNetworkInterfaces );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInterruptSimulator( void *pvParameters )
+{
+static struct pcap_pkthdr *pxHeader;
+const unsigned char *pucPacketData;
+extern QueueHandle_t xEMACEventQueue;
+long lResult;
+
+	/* Just to kill the compiler warning. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		/* Get the next packet. */
+		lResult = pcap_next_ex( pxOpenedInterfaceHandle, &pxHeader, &pucPacketData );
+		if( lResult == 1 )
+		{
+			if( pxlwIPNetIf != NULL )
+			{
+				prvEthernetInput( pucPacketData, pxHeader->len );
+			}
+		}
+		else
+		{
+			/* There is no real way of simulating an interrupt.  
+			Make sure other tasks can run. */
+			vTaskDelay( 5 );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvConfigureCaptureBehaviour( void )
+{
+struct bpf_program xFilterCode;
+const long lMinBytesToCopy = 10L, lBlocking = 1L;
+unsigned long ulNetMask;
+
+	/* Unblock a read as soon as anything is received. */
+	pcap_setmintocopy( pxOpenedInterfaceHandle, lMinBytesToCopy );
+
+	/* Allow blocking. */
+	pcap_setnonblock( pxOpenedInterfaceHandle, lBlocking, cErrorBuffer );
+
+	/* Set up a filter so only the packets of interest are passed to the lwIP
+	stack.  cErrorBuffer is used for convenience to create the string.  Don't
+	confuse this with an error message. */
+	sprintf( cErrorBuffer, "broadcast or multicast or host %d.%d.%d.%d", configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 );
+
+	ulNetMask = ( configNET_MASK3 << 24UL ) | ( configNET_MASK2 << 16UL ) | ( configNET_MASK1 << 8L ) | configNET_MASK0;
+
+	if( pcap_compile(pxOpenedInterfaceHandle, &xFilterCode, cErrorBuffer, 1, ulNetMask ) < 0 )
+	{
+		printf( "\r\nThe packet filter string is invalid\r\n" );
+	}
+	else
+	{	
+		if( pcap_setfilter( pxOpenedInterfaceHandle, &xFilterCode ) < 0 )
+		{
+			printf( "\r\nAn error occurred setting the packet filter.\r\n" );
+		}
+	}
+
+	/* Create a task that simulates an interrupt in a real system.  This will
+	block waiting for packets, then send a message to the uIP task when data
+	is available. */
+	xTaskCreate( prvInterruptSimulator, "MAC_ISR", configMINIMAL_STACK_SIZE, NULL, configMAC_ISR_SIMULATOR_PRIORITY, NULL );
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/bpstruct.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/bpstruct.h
new file mode 100644
index 0000000..1d81e3f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/bpstruct.h
@@ -0,0 +1 @@
+#pragma pack(push,1)
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/cc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/cc.h
new file mode 100644
index 0000000..8c64b5d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/cc.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __ARCH_CC_H__
+#define __ARCH_CC_H__
+
+#if 1
+/* Include some files for defining library routines */
+#include  /* printf, fflush, FILE */
+#include  /* abort */
+#else
+/* Declare fuction prototypes for assert/diag/error - leads to some warnings,
+ * but good to test if no includes are missing. */
+int printf(const char *format, ...);
+void abort(void);
+struct _iobuf;
+typedef struct _iobuf FILE;
+int fflush(FILE *stream);
+#endif
+
+
+
+/** @todo fix some warnings: don't use #pragma if compiling with cygwin gcc */
+#ifndef __GNUC__
+#include 
+#pragma warning (disable: 4244) /* disable conversion warning (implicit integer promotion!) */
+#pragma warning (disable: 4127) /* conditional expression is constant */
+#pragma warning (disable: 4996) /* 'strncpy' was declared deprecated */
+#pragma warning (disable: 4103) /* structure packing changed by including file */
+#endif
+
+#define LWIP_PROVIDE_ERRNO
+
+/* Define platform endianness (might already be defined) */
+#ifndef BYTE_ORDER
+#define BYTE_ORDER LITTLE_ENDIAN
+#endif /* BYTE_ORDER */
+
+/* Define generic types used in lwIP */
+typedef unsigned   char    u8_t;
+typedef signed     char    s8_t;
+typedef unsigned   short   u16_t;
+typedef signed     short   s16_t;
+typedef unsigned   long    u32_t;
+typedef signed     long    s32_t;
+
+typedef size_t mem_ptr_t;
+typedef u32_t sys_prot_t;
+
+/* Define (sn)printf formatters for these lwIP types */
+#define X8_F  "02x"
+#define U16_F "hu"
+#define S16_F "hd"
+#define X16_F "hx"
+#define U32_F "lu"
+#define S32_F "ld"
+#define X32_F "lx"
+#define SZT_F U32_F
+
+/* Compiler hints for packing structures */
+#define PACK_STRUCT_STRUCT
+#define PACK_STRUCT_USE_INCLUDES
+
+/* Plaform specific diagnostic output */
+#define LWIP_PLATFORM_DIAG(x)   do { printf x; } while(0)
+
+#define LWIP_PLATFORM_ASSERT(x) do { printf("Assertion \"%s\" failed at line %d in %s\n", \
+                                     x, __LINE__, __FILE__); fflush(NULL); abort(); } while(0)
+
+#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \
+  printf("Assertion \"%s\" failed at line %d in %s\n", message, __LINE__, __FILE__); \
+  fflush(NULL);handler;} } while(0)
+
+/* C runtime functions redefined */
+#define snprintf _snprintf
+
+u32_t dns_lookup_external_hosts_file(const char *name);
+
+#define LWIP_RAND() ((u32_t)rand())
+
+#endif /* __ARCH_CC_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/epstruct.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/epstruct.h
new file mode 100644
index 0000000..65898b5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/epstruct.h
@@ -0,0 +1 @@
+#pragma pack(pop)
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/perf.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/perf.h
new file mode 100644
index 0000000..089faca
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/perf.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __PERF_H__
+#define __PERF_H__
+
+#define PERF_START    /* null definition */
+#define PERF_STOP(x)  /* null definition */
+
+#endif /* __PERF_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/sys_arch.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/sys_arch.h
new file mode 100644
index 0000000..f9eae84
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/include/arch/sys_arch.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __ARCH_SYS_ARCH_H__
+#define __ARCH_SYS_ARCH_H__
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+
+#define SYS_MBOX_NULL					( ( QueueHandle_t ) NULL )
+#define SYS_SEM_NULL					( ( SemaphoreHandle_t ) NULL )
+#define SYS_DEFAULT_THREAD_STACK_DEPTH	configMINIMAL_STACK_SIZE
+
+typedef SemaphoreHandle_t sys_sem_t;
+typedef SemaphoreHandle_t sys_mutex_t;
+typedef QueueHandle_t sys_mbox_t;
+typedef TaskHandle_t sys_thread_t;
+
+typedef unsigned long sys_prot_t;
+
+#define sys_mbox_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE )
+#define sys_mbox_set_invalid( x ) ( ( *x ) = NULL )
+#define sys_sem_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE )
+#define sys_sem_set_invalid( x ) ( ( *x ) = NULL )
+
+
+#endif /* __ARCH_SYS_ARCH_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/lwipcfg_msvc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/lwipcfg_msvc.h
new file mode 100644
index 0000000..a6b5208
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/lwipcfg_msvc.h
@@ -0,0 +1,45 @@
+/**
+ * Additional settings for the win32 port.
+ * Copy this to lwipcfg_msvc.h and make the config changes you need.
+ */
+
+/* configuration for this port */
+#define PPP_USERNAME  "Admin"
+#define PPP_PASSWORD  "pass"
+
+/** Define this to the index of the windows network adapter to use */
+#define PACKET_LIB_ADAPTER_NR         2
+/** Define this to the GUID of the windows network adapter to use
+ * or NOT define this if you want PACKET_LIB_ADAPTER_NR to be used */ 
+/*#define PACKET_LIB_ADAPTER_GUID       "00000000-0000-0000-0000-000000000000"*/
+/*#define PACKET_LIB_GET_ADAPTER_NETADDRESS(addr) IP4_ADDR((addr), 192,168,1,0)*/
+/*#define PACKET_LIB_QUIET*/
+
+#define LWIP_PORT_INIT_IPADDR(addr)   IP4_ADDR((addr), 192,168,0,200)
+#define LWIP_PORT_INIT_GW(addr)       IP4_ADDR((addr), 192,168,0,3)
+#define LWIP_PORT_INIT_NETMASK(addr)  IP4_ADDR((addr), 255,255,255,0)
+
+/* remember to change this MAC address to suit your needs!
+   the last octet will be increased by netif->num for each netif */
+#define LWIP_MAC_ADDR_BASE            {0x00,0x01,0x02,0x03,0x04,0x05}
+
+/* configuration for applications */
+
+#define LWIP_CHARGEN_APP              0
+#define LWIP_DNS_APP                  0
+#define LWIP_HTTPD_APP                1
+/* Set this to 1 to use the netconn http server,
+ * otherwise the raw api server will be used. */
+/*#define LWIP_HTTPD_APP_NETCONN     */
+#define LWIP_NETBIOS_APP              0
+#define LWIP_NETIO_APP                0
+#define LWIP_PING_APP                 0
+#define LWIP_RTP_APP                  0
+#define LWIP_SHELL_APP                0
+#define LWIP_SNTP_APP                 0
+#define LWIP_SOCKET_EXAMPLES_APP      0
+#define LWIP_TCPECHO_APP              0
+/* Set this to 1 to use the netconn tcpecho server,
+ * otherwise the raw api server will be used. */
+/*#define LWIP_TCPECHO_APP_NETCONN   */
+#define LWIP_UDPECHO_APP              0
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/sys_arch.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/sys_arch.c
new file mode 100644
index 0000000..78b1298
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/ports/win32/sys_arch.c
@@ -0,0 +1,541 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+//*****************************************************************************
+//
+// Include OS functionality.
+//
+//*****************************************************************************
+
+/* ------------------------ System architecture includes ----------------------------- */
+#include "arch/sys_arch.h"
+
+/* ------------------------ lwIP includes --------------------------------- */
+#include "lwip/opt.h"
+
+#include "lwip/debug.h"
+#include "lwip/def.h"
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+#include "lwip/stats.h"
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_mbox_new
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Creates a new mailbox
+ * Inputs:
+ *      int size                -- Size of elements in the mailbox
+ * Outputs:
+ *      sys_mbox_t              -- Handle to new mailbox
+ *---------------------------------------------------------------------------*/
+err_t sys_mbox_new( sys_mbox_t *pxMailBox, int iSize )
+{
+err_t xReturn = ERR_MEM;
+
+	*pxMailBox = xQueueCreate( iSize, sizeof( void * ) );
+
+	if( *pxMailBox != NULL )
+	{
+		xReturn = ERR_OK;
+		SYS_STATS_INC_USED( mbox );
+	}
+
+	return xReturn;
+}
+
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_mbox_free
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Deallocates a mailbox. If there are messages still present in the
+ *      mailbox when the mailbox is deallocated, it is an indication of a
+ *      programming error in lwIP and the developer should be notified.
+ * Inputs:
+ *      sys_mbox_t mbox         -- Handle of mailbox
+ * Outputs:
+ *      sys_mbox_t              -- Handle to new mailbox
+ *---------------------------------------------------------------------------*/
+void sys_mbox_free( sys_mbox_t *pxMailBox )
+{
+unsigned long ulMessagesWaiting;
+
+	ulMessagesWaiting = uxQueueMessagesWaiting( *pxMailBox );
+	configASSERT( ( ulMessagesWaiting == 0 ) );
+
+	#if SYS_STATS
+	{
+		if( ulMessagesWaiting != 0UL )
+		{
+			SYS_STATS_INC( mbox.err );
+		}
+
+		SYS_STATS_DEC( mbox.used );
+	}
+	#endif /* SYS_STATS */
+
+	vQueueDelete( *pxMailBox );
+}
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_mbox_post
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Post the "msg" to the mailbox.
+ * Inputs:
+ *      sys_mbox_t mbox         -- Handle of mailbox
+ *      void *data              -- Pointer to data to post
+ *---------------------------------------------------------------------------*/
+void sys_mbox_post( sys_mbox_t *pxMailBox, void *pxMessageToPost )
+{
+	while( xQueueSendToBack( *pxMailBox, &pxMessageToPost, portMAX_DELAY ) != pdTRUE );
+}
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_mbox_trypost
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Try to post the "msg" to the mailbox.  Returns immediately with
+ *      error if cannot.
+ * Inputs:
+ *      sys_mbox_t mbox         -- Handle of mailbox
+ *      void *msg               -- Pointer to data to post
+ * Outputs:
+ *      err_t                   -- ERR_OK if message posted, else ERR_MEM
+ *                                  if not.
+ *---------------------------------------------------------------------------*/
+err_t sys_mbox_trypost( sys_mbox_t *pxMailBox, void *pxMessageToPost )
+{
+err_t xReturn;
+
+	if( xQueueSend( *pxMailBox, &pxMessageToPost, 0UL ) == pdPASS )
+	{
+		xReturn = ERR_OK;
+	}
+	else
+	{
+		/* The queue was already full. */
+		xReturn = ERR_MEM;
+		SYS_STATS_INC( mbox.err );
+	}
+
+	return xReturn;
+}
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_arch_mbox_fetch
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Blocks the thread until a message arrives in the mailbox, but does
+ *      not block the thread longer than "timeout" milliseconds (similar to
+ *      the sys_arch_sem_wait() function). The "msg" argument is a result
+ *      parameter that is set by the function (i.e., by doing "*msg =
+ *      ptr"). The "msg" parameter maybe NULL to indicate that the message
+ *      should be dropped.
+ *
+ *      The return values are the same as for the sys_arch_sem_wait() function:
+ *      Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a
+ *      timeout.
+ *
+ *      Note that a function with a similar name, sys_mbox_fetch(), is
+ *      implemented by lwIP.
+ * Inputs:
+ *      sys_mbox_t mbox         -- Handle of mailbox
+ *      void **msg              -- Pointer to pointer to msg received
+ *      u32_t timeout           -- Number of milliseconds until timeout
+ * Outputs:
+ *      u32_t                   -- SYS_ARCH_TIMEOUT if timeout, else number
+ *                                  of milliseconds until received.
+ *---------------------------------------------------------------------------*/
+u32_t sys_arch_mbox_fetch( sys_mbox_t *pxMailBox, void **ppvBuffer, u32_t ulTimeOut )
+{
+void *pvDummy;
+TickType_t xStartTime, xEndTime, xElapsed;
+unsigned long ulReturn;
+
+	xStartTime = xTaskGetTickCount();
+
+	if( NULL == ppvBuffer )
+	{
+		ppvBuffer = &pvDummy;
+	}
+
+	if( ulTimeOut != 0UL )
+	{
+		if( pdTRUE == xQueueReceive( *pxMailBox, &( *ppvBuffer ), ulTimeOut/ portTICK_PERIOD_MS ) )
+		{
+			xEndTime = xTaskGetTickCount();
+			xElapsed = ( xEndTime - xStartTime ) * portTICK_PERIOD_MS;
+
+			ulReturn = xElapsed;
+		}
+		else
+		{
+			/* Timed out. */
+			*ppvBuffer = NULL;
+			ulReturn = SYS_ARCH_TIMEOUT;
+		}
+	}
+	else
+	{
+		while( pdTRUE != xQueueReceive( *pxMailBox, &( *ppvBuffer ), portMAX_DELAY ) );
+		xEndTime = xTaskGetTickCount();
+		xElapsed = ( xEndTime - xStartTime ) * portTICK_PERIOD_MS;
+
+		if( xElapsed == 0UL )
+		{
+			xElapsed = 1UL;
+		}
+
+		ulReturn = xElapsed;
+	}
+
+	return ulReturn;
+}
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_arch_mbox_tryfetch
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Similar to sys_arch_mbox_fetch, but if message is not ready
+ *      immediately, we'll return with SYS_MBOX_EMPTY.  On success, 0 is
+ *      returned.
+ * Inputs:
+ *      sys_mbox_t mbox         -- Handle of mailbox
+ *      void **msg              -- Pointer to pointer to msg received
+ * Outputs:
+ *      u32_t                   -- SYS_MBOX_EMPTY if no messages.  Otherwise,
+ *                                  return ERR_OK.
+ *---------------------------------------------------------------------------*/
+u32_t sys_arch_mbox_tryfetch( sys_mbox_t *pxMailBox, void **ppvBuffer )
+{
+void *pvDummy;
+unsigned long ulReturn;
+
+	if( ppvBuffer== NULL )
+	{
+		ppvBuffer = &pvDummy;
+	}
+
+	if( pdTRUE == xQueueReceive( *pxMailBox, &( *ppvBuffer ), 0UL ) )
+	{
+		ulReturn = ERR_OK;
+	}
+	else
+	{
+		ulReturn = SYS_MBOX_EMPTY;
+	}
+
+	return ulReturn;
+}
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_sem_new
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Creates and returns a new semaphore. The "ucCount" argument specifies
+ *      the initial state of the semaphore.
+ *      NOTE: Currently this routine only creates counts of 1 or 0
+ * Inputs:
+ *      sys_mbox_t mbox         -- Handle of mailbox
+ *      u8_t ucCount              -- Initial ucCount of semaphore (1 or 0)
+ * Outputs:
+ *      sys_sem_t               -- Created semaphore or 0 if could not create.
+ *---------------------------------------------------------------------------*/
+err_t sys_sem_new( sys_sem_t *pxSemaphore, u8_t ucCount )
+{
+err_t xReturn = ERR_MEM;
+
+	vSemaphoreCreateBinary( ( *pxSemaphore ) );
+
+	if( *pxSemaphore != NULL )
+	{
+		if( ucCount == 0U )
+		{
+			xSemaphoreTake( *pxSemaphore, 1UL );
+		}
+
+		xReturn = ERR_OK;
+		SYS_STATS_INC_USED( sem );
+	}
+	else
+	{
+		SYS_STATS_INC( sem.err );
+	}
+
+	return xReturn;
+}
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_arch_sem_wait
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Blocks the thread while waiting for the semaphore to be
+ *      signaled. If the "timeout" argument is non-zero, the thread should
+ *      only be blocked for the specified time (measured in
+ *      milliseconds).
+ *
+ *      If the timeout argument is non-zero, the return value is the number of
+ *      milliseconds spent waiting for the semaphore to be signaled. If the
+ *      semaphore wasn't signaled within the specified time, the return value is
+ *      SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
+ *      (i.e., it was already signaled), the function may return zero.
+ *
+ *      Notice that lwIP implements a function with a similar name,
+ *      sys_sem_wait(), that uses the sys_arch_sem_wait() function.
+ * Inputs:
+ *      sys_sem_t sem           -- Semaphore to wait on
+ *      u32_t timeout           -- Number of milliseconds until timeout
+ * Outputs:
+ *      u32_t                   -- Time elapsed or SYS_ARCH_TIMEOUT.
+ *---------------------------------------------------------------------------*/
+u32_t sys_arch_sem_wait( sys_sem_t *pxSemaphore, u32_t ulTimeout )
+{
+TickType_t xStartTime, xEndTime, xElapsed;
+unsigned long ulReturn;
+
+	xStartTime = xTaskGetTickCount();
+
+	if( ulTimeout != 0UL )
+	{
+		if( xSemaphoreTake( *pxSemaphore, ulTimeout / portTICK_PERIOD_MS ) == pdTRUE )
+		{
+			xEndTime = xTaskGetTickCount();
+			xElapsed = (xEndTime - xStartTime) * portTICK_PERIOD_MS;
+			ulReturn = xElapsed;
+		}
+		else
+		{
+			ulReturn = SYS_ARCH_TIMEOUT;
+		}
+	}
+	else
+	{
+		while( xSemaphoreTake( *pxSemaphore, portMAX_DELAY ) != pdTRUE );
+		xEndTime = xTaskGetTickCount();
+		xElapsed = ( xEndTime - xStartTime ) * portTICK_PERIOD_MS;
+
+		if( xElapsed == 0UL )
+		{
+			xElapsed = 1UL;
+		}
+
+		ulReturn = xElapsed;
+	}
+
+	return ulReturn;
+}
+
+/** Create a new mutex
+ * @param mutex pointer to the mutex to create
+ * @return a new mutex */
+err_t sys_mutex_new( sys_mutex_t *pxMutex )
+{
+err_t xReturn = ERR_MEM;
+
+	*pxMutex = xSemaphoreCreateMutex();
+
+	if( *pxMutex != NULL )
+	{
+		xReturn = ERR_OK;
+		SYS_STATS_INC_USED( mutex );
+	}
+	else
+	{
+		SYS_STATS_INC( mutex.err );
+	}
+
+	return xReturn;
+}
+
+/** Lock a mutex
+ * @param mutex the mutex to lock */
+void sys_mutex_lock( sys_mutex_t *pxMutex )
+{
+	while( xSemaphoreTake( *pxMutex, portMAX_DELAY ) != pdPASS );
+}
+
+/** Unlock a mutex
+ * @param mutex the mutex to unlock */
+void sys_mutex_unlock(sys_mutex_t *pxMutex )
+{
+	xSemaphoreGive( *pxMutex );
+}
+
+
+/** Delete a semaphore
+ * @param mutex the mutex to delete */
+void sys_mutex_free( sys_mutex_t *pxMutex )
+{
+	SYS_STATS_DEC( mutex.used );
+	vQueueDelete( *pxMutex );
+}
+
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_sem_signal
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Signals (releases) a semaphore
+ * Inputs:
+ *      sys_sem_t sem           -- Semaphore to signal
+ *---------------------------------------------------------------------------*/
+void sys_sem_signal( sys_sem_t *pxSemaphore )
+{
+	xSemaphoreGive( *pxSemaphore );
+}
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_sem_free
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Deallocates a semaphore
+ * Inputs:
+ *      sys_sem_t sem           -- Semaphore to free
+ *---------------------------------------------------------------------------*/
+void sys_sem_free( sys_sem_t *pxSemaphore )
+{
+	SYS_STATS_DEC(sem.used);
+	vQueueDelete( *pxSemaphore );
+}
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_init
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Initialize sys arch
+ *---------------------------------------------------------------------------*/
+void sys_init(void)
+{
+}
+
+u32_t sys_now(void)
+{
+	return xTaskGetTickCount();
+}
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_thread_new
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      Starts a new thread with priority "prio" that will begin its
+ *      execution in the function "thread()". The "arg" argument will be
+ *      passed as an argument to the thread() function. The id of the new
+ *      thread is returned. Both the id and the priority are system
+ *      dependent.
+ * Inputs:
+ *      char *name              -- Name of thread
+ *      void (* thread)(void *arg) -- Pointer to function to run.
+ *      void *arg               -- Argument passed into function
+ *      int stacksize           -- Required stack amount in bytes
+ *      int prio                -- Thread priority
+ * Outputs:
+ *      sys_thread_t            -- Pointer to per-thread timeouts.
+ *---------------------------------------------------------------------------*/
+sys_thread_t sys_thread_new( const char *pcName, void( *pxThread )( void *pvParameters ), void *pvArg, int iStackSize, int iPriority )
+{
+TaskHandle_t xCreatedTask;
+portBASE_TYPE xResult;
+sys_thread_t xReturn;
+
+	xResult = xTaskCreate( pxThread, pcName, iStackSize, pvArg, iPriority, &xCreatedTask );
+
+	if( xResult == pdPASS )
+	{
+		xReturn = xCreatedTask;
+	}
+	else
+	{
+		xReturn = NULL;
+	}
+
+	return xReturn;
+}
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_arch_protect
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      This optional function does a "fast" critical region protection and
+ *      returns the previous protection level. This function is only called
+ *      during very short critical regions. An embedded system which supports
+ *      ISR-based drivers might want to implement this function by disabling
+ *      interrupts. Task-based systems might want to implement this by using
+ *      a mutex or disabling tasking. This function should support recursive
+ *      calls from the same task or interrupt. In other words,
+ *      sys_arch_protect() could be called while already protected. In
+ *      that case the return value indicates that it is already protected.
+ *
+ *      sys_arch_protect() is only required if your port is supporting an
+ *      operating system.
+ * Outputs:
+ *      sys_prot_t              -- Previous protection level (not used here)
+ *---------------------------------------------------------------------------*/
+sys_prot_t sys_arch_protect( void )
+{
+	vPortEnterCritical();
+	return ( sys_prot_t ) 1;
+}
+
+/*---------------------------------------------------------------------------*
+ * Routine:  sys_arch_unprotect
+ *---------------------------------------------------------------------------*
+ * Description:
+ *      This optional function does a "fast" set of critical region
+ *      protection to the value specified by pval. See the documentation for
+ *      sys_arch_protect() for more information. This function is only
+ *      required if your port is supporting an operating system.
+ * Inputs:
+ *      sys_prot_t              -- Previous protection level (not used here)
+ *---------------------------------------------------------------------------*/
+void sys_arch_unprotect( sys_prot_t xValue )
+{
+	(void) xValue;
+	taskEXIT_CRITICAL();
+}
+
+/*
+ * Prints an assertion messages and aborts execution.
+ */
+void sys_assert( const char *pcMessage )
+{
+	(void) pcMessage;
+
+	for (;;)
+	{
+	}
+}
+/*-------------------------------------------------------------------------*
+ * End of File:  sys_arch.c
+ *-------------------------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/.hgignore b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/.hgignore
new file mode 100644
index 0000000..f88587d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/.hgignore
@@ -0,0 +1,26 @@
+syntax: glob 
+ 
+*.pyc 
+*.orig 
+*.rej 
+*~ 
+TAGS 
+Module.symvers 
+*.ncb
+*.suo
+*.bak
+*.orig
+*.rej
+
+syntax: regexp
+\.\#.+
+[\\/]CVS$
+^CVS$
+^build$
+^install$
+^logs.build_tree$
+[\\/]bin$
+^bin$
+[\\/]obj$
+^obj$
+\.cvsignore
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/FILES b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/FILES
new file mode 100644
index 0000000..952aeab
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/FILES
@@ -0,0 +1,13 @@
+api/      - The code for the high-level wrapper API. Not needed if
+            you use the lowel-level call-back/raw API.
+
+core/     - The core of the TPC/IP stack; protocol implementations,
+            memory and buffer management, and the low-level raw API.
+
+include/  - lwIP include files.
+
+netif/    - Generic network interface device drivers are kept here,
+            as well as the ARP module.
+
+For more information on the various subdirectories, check the FILES
+file in each directory.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/api_lib.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/api_lib.c
new file mode 100644
index 0000000..b1a9e52
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/api_lib.c
@@ -0,0 +1,740 @@
+/**
+ * @file
+ * Sequential API External module
+ *
+ */
+ 
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* This is the part of the API that is linked with
+   the application */
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/api.h"
+#include "lwip/tcpip.h"
+#include "lwip/memp.h"
+
+#include "lwip/ip.h"
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include 
+
+/**
+ * Create a new netconn (of a specific type) that has a callback function.
+ * The corresponding pcb is also created.
+ *
+ * @param t the type of 'connection' to create (@see enum netconn_type)
+ * @param proto the IP protocol for RAW IP pcbs
+ * @param callback a function to call on status changes (RX available, TX'ed)
+ * @return a newly allocated struct netconn or
+ *         NULL on memory error
+ */
+struct netconn*
+netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto, netconn_callback callback)
+{
+  struct netconn *conn;
+  struct api_msg msg;
+
+  conn = netconn_alloc(t, callback);
+  if (conn != NULL) {
+    msg.function = do_newconn;
+    msg.msg.msg.n.proto = proto;
+    msg.msg.conn = conn;
+    if (TCPIP_APIMSG(&msg) != ERR_OK) {
+      LWIP_ASSERT("freeing conn without freeing pcb", conn->pcb.tcp == NULL);
+      LWIP_ASSERT("conn has no op_completed", sys_sem_valid(&conn->op_completed));
+      LWIP_ASSERT("conn has no recvmbox", sys_mbox_valid(&conn->recvmbox));
+#if LWIP_TCP
+      LWIP_ASSERT("conn->acceptmbox shouldn't exist", !sys_mbox_valid(&conn->acceptmbox));
+#endif /* LWIP_TCP */
+      sys_sem_free(&conn->op_completed);
+      sys_mbox_free(&conn->recvmbox);
+      memp_free(MEMP_NETCONN, conn);
+      return NULL;
+    }
+  }
+  return conn;
+}
+
+/**
+ * Close a netconn 'connection' and free its resources.
+ * UDP and RAW connection are completely closed, TCP pcbs might still be in a waitstate
+ * after this returns.
+ *
+ * @param conn the netconn to delete
+ * @return ERR_OK if the connection was deleted
+ */
+err_t
+netconn_delete(struct netconn *conn)
+{
+  struct api_msg msg;
+
+  /* No ASSERT here because possible to get a (conn == NULL) if we got an accept error */
+  if (conn == NULL) {
+    return ERR_OK;
+  }
+
+  msg.function = do_delconn;
+  msg.msg.conn = conn;
+  tcpip_apimsg(&msg);
+
+  netconn_free(conn);
+
+  /* don't care for return value of do_delconn since it only calls void functions */
+
+  return ERR_OK;
+}
+
+/**
+ * Get the local or remote IP address and port of a netconn.
+ * For RAW netconns, this returns the protocol instead of a port!
+ *
+ * @param conn the netconn to query
+ * @param addr a pointer to which to save the IP address
+ * @param port a pointer to which to save the port (or protocol for RAW)
+ * @param local 1 to get the local IP address, 0 to get the remote one
+ * @return ERR_CONN for invalid connections
+ *         ERR_OK if the information was retrieved
+ */
+err_t
+netconn_getaddr(struct netconn *conn, ip_addr_t *addr, u16_t *port, u8_t local)
+{
+  struct api_msg msg;
+  err_t err;
+
+  LWIP_ERROR("netconn_getaddr: invalid conn", (conn != NULL), return ERR_ARG;);
+  LWIP_ERROR("netconn_getaddr: invalid addr", (addr != NULL), return ERR_ARG;);
+  LWIP_ERROR("netconn_getaddr: invalid port", (port != NULL), return ERR_ARG;);
+
+  msg.function = do_getaddr;
+  msg.msg.conn = conn;
+  msg.msg.msg.ad.ipaddr = addr;
+  msg.msg.msg.ad.port = port;
+  msg.msg.msg.ad.local = local;
+  err = TCPIP_APIMSG(&msg);
+
+  NETCONN_SET_SAFE_ERR(conn, err);
+  return err;
+}
+
+/**
+ * Bind a netconn to a specific local IP address and port.
+ * Binding one netconn twice might not always be checked correctly!
+ *
+ * @param conn the netconn to bind
+ * @param addr the local IP address to bind the netconn to (use IP_ADDR_ANY
+ *             to bind to all addresses)
+ * @param port the local port to bind the netconn to (not used for RAW)
+ * @return ERR_OK if bound, any other err_t on failure
+ */
+err_t
+netconn_bind(struct netconn *conn, ip_addr_t *addr, u16_t port)
+{
+  struct api_msg msg;
+  err_t err;
+
+  LWIP_ERROR("netconn_bind: invalid conn", (conn != NULL), return ERR_ARG;);
+
+  msg.function = do_bind;
+  msg.msg.conn = conn;
+  msg.msg.msg.bc.ipaddr = addr;
+  msg.msg.msg.bc.port = port;
+  err = TCPIP_APIMSG(&msg);
+
+  NETCONN_SET_SAFE_ERR(conn, err);
+  return err;
+}
+
+/**
+ * Connect a netconn to a specific remote IP address and port.
+ *
+ * @param conn the netconn to connect
+ * @param addr the remote IP address to connect to
+ * @param port the remote port to connect to (no used for RAW)
+ * @return ERR_OK if connected, return value of tcp_/udp_/raw_connect otherwise
+ */
+err_t
+netconn_connect(struct netconn *conn, ip_addr_t *addr, u16_t port)
+{
+  struct api_msg msg;
+  err_t err;
+
+  LWIP_ERROR("netconn_connect: invalid conn", (conn != NULL), return ERR_ARG;);
+
+  msg.function = do_connect;
+  msg.msg.conn = conn;
+  msg.msg.msg.bc.ipaddr = addr;
+  msg.msg.msg.bc.port = port;
+  /* This is the only function which need to not block tcpip_thread */
+  err = tcpip_apimsg(&msg);
+
+  NETCONN_SET_SAFE_ERR(conn, err);
+  return err;
+}
+
+/**
+ * Disconnect a netconn from its current peer (only valid for UDP netconns).
+ *
+ * @param conn the netconn to disconnect
+ * @return TODO: return value is not set here...
+ */
+err_t
+netconn_disconnect(struct netconn *conn)
+{
+  struct api_msg msg;
+  err_t err;
+
+  LWIP_ERROR("netconn_disconnect: invalid conn", (conn != NULL), return ERR_ARG;);
+
+  msg.function = do_disconnect;
+  msg.msg.conn = conn;
+  err = TCPIP_APIMSG(&msg);
+
+  NETCONN_SET_SAFE_ERR(conn, err);
+  return err;
+}
+
+/**
+ * Set a TCP netconn into listen mode
+ *
+ * @param conn the tcp netconn to set to listen mode
+ * @param backlog the listen backlog, only used if TCP_LISTEN_BACKLOG==1
+ * @return ERR_OK if the netconn was set to listen (UDP and RAW netconns
+ *         don't return any error (yet?))
+ */
+err_t
+netconn_listen_with_backlog(struct netconn *conn, u8_t backlog)
+{
+#if LWIP_TCP
+  struct api_msg msg;
+  err_t err;
+
+  /* This does no harm. If TCP_LISTEN_BACKLOG is off, backlog is unused. */
+  LWIP_UNUSED_ARG(backlog);
+
+  LWIP_ERROR("netconn_listen: invalid conn", (conn != NULL), return ERR_ARG;);
+
+  msg.function = do_listen;
+  msg.msg.conn = conn;
+#if TCP_LISTEN_BACKLOG
+  msg.msg.msg.lb.backlog = backlog;
+#endif /* TCP_LISTEN_BACKLOG */
+  err = TCPIP_APIMSG(&msg);
+
+  NETCONN_SET_SAFE_ERR(conn, err);
+  return err;
+#else /* LWIP_TCP */
+  LWIP_UNUSED_ARG(conn);
+  LWIP_UNUSED_ARG(backlog);
+  return ERR_ARG;
+#endif /* LWIP_TCP */
+}
+
+/**
+ * Accept a new connection on a TCP listening netconn.
+ *
+ * @param conn the TCP listen netconn
+ * @param new_conn pointer where the new connection is stored
+ * @return ERR_OK if a new connection has been received or an error
+ *                code otherwise
+ */
+err_t
+netconn_accept(struct netconn *conn, struct netconn **new_conn)
+{
+#if LWIP_TCP
+  struct netconn *newconn;
+  err_t err;
+#if TCP_LISTEN_BACKLOG
+  struct api_msg msg;
+#endif /* TCP_LISTEN_BACKLOG */
+
+  LWIP_ERROR("netconn_accept: invalid pointer",    (new_conn != NULL),                  return ERR_ARG;);
+  *new_conn = NULL;
+  LWIP_ERROR("netconn_accept: invalid conn",       (conn != NULL),                      return ERR_ARG;);
+  LWIP_ERROR("netconn_accept: invalid acceptmbox", sys_mbox_valid(&conn->acceptmbox),   return ERR_ARG;);
+
+  err = conn->last_err;
+  if (ERR_IS_FATAL(err)) {
+    /* don't recv on fatal errors: this might block the application task
+       waiting on acceptmbox forever! */
+    return err;
+  }
+
+#if LWIP_SO_RCVTIMEO
+  if (sys_arch_mbox_fetch(&conn->acceptmbox, (void **)&newconn, conn->recv_timeout) == SYS_ARCH_TIMEOUT) {
+    NETCONN_SET_SAFE_ERR(conn, ERR_TIMEOUT);
+    return ERR_TIMEOUT;
+  }
+#else
+  sys_arch_mbox_fetch(&conn->acceptmbox, (void **)&newconn, 0);
+#endif /* LWIP_SO_RCVTIMEO*/
+  /* Register event with callback */
+  API_EVENT(conn, NETCONN_EVT_RCVMINUS, 0);
+
+  if (newconn == NULL) {
+    /* connection has been aborted */
+    NETCONN_SET_SAFE_ERR(conn, ERR_ABRT);
+    return ERR_ABRT;
+  }
+#if TCP_LISTEN_BACKLOG
+  /* Let the stack know that we have accepted the connection. */
+  msg.function = do_recv;
+  msg.msg.conn = conn;
+  /* don't care for the return value of do_recv */
+  TCPIP_APIMSG(&msg);
+#endif /* TCP_LISTEN_BACKLOG */
+
+  *new_conn = newconn;
+  /* don't set conn->last_err: it's only ERR_OK, anyway */
+  return ERR_OK;
+#else /* LWIP_TCP */
+  LWIP_UNUSED_ARG(conn);
+  LWIP_UNUSED_ARG(new_conn);
+  return ERR_ARG;
+#endif /* LWIP_TCP */
+}
+
+/**
+ * Receive data: actual implementation that doesn't care whether pbuf or netbuf
+ * is received
+ *
+ * @param conn the netconn from which to receive data
+ * @param new_buf pointer where a new pbuf/netbuf is stored when received data
+ * @return ERR_OK if data has been received, an error code otherwise (timeout,
+ *                memory error or another error)
+ */
+static err_t
+netconn_recv_data(struct netconn *conn, void **new_buf)
+{
+  void *buf = NULL;
+  u16_t len;
+  err_t err;
+#if LWIP_TCP
+  struct api_msg msg;
+#endif /* LWIP_TCP */
+
+  LWIP_ERROR("netconn_recv: invalid pointer", (new_buf != NULL), return ERR_ARG;);
+  *new_buf = NULL;
+  LWIP_ERROR("netconn_recv: invalid conn",    (conn != NULL),    return ERR_ARG;);
+  LWIP_ERROR("netconn_accept: invalid recvmbox", sys_mbox_valid(&conn->recvmbox), return ERR_CONN;);
+
+  err = conn->last_err;
+  if (ERR_IS_FATAL(err)) {
+    /* don't recv on fatal errors: this might block the application task
+       waiting on recvmbox forever! */
+    /* @todo: this does not allow us to fetch data that has been put into recvmbox
+       before the fatal error occurred - is that a problem? */
+    return err;
+  }
+
+#if LWIP_SO_RCVTIMEO
+  if (sys_arch_mbox_fetch(&conn->recvmbox, &buf, conn->recv_timeout) == SYS_ARCH_TIMEOUT) {
+    NETCONN_SET_SAFE_ERR(conn, ERR_TIMEOUT);
+    return ERR_TIMEOUT;
+  }
+#else
+  sys_arch_mbox_fetch(&conn->recvmbox, &buf, 0);
+#endif /* LWIP_SO_RCVTIMEO*/
+
+#if LWIP_TCP
+  if (conn->type == NETCONN_TCP) {
+    if (!netconn_get_noautorecved(conn) || (buf == NULL)) {
+      /* Let the stack know that we have taken the data. */
+      /* TODO: Speedup: Don't block and wait for the answer here
+         (to prevent multiple thread-switches). */
+      msg.function = do_recv;
+      msg.msg.conn = conn;
+      if (buf != NULL) {
+        msg.msg.msg.r.len = ((struct pbuf *)buf)->tot_len;
+      } else {
+        msg.msg.msg.r.len = 1;
+      }
+      /* don't care for the return value of do_recv */
+      TCPIP_APIMSG(&msg);
+    }
+
+    /* If we are closed, we indicate that we no longer wish to use the socket */
+    if (buf == NULL) {
+      API_EVENT(conn, NETCONN_EVT_RCVMINUS, 0);
+      /* Avoid to lose any previous error code */
+      NETCONN_SET_SAFE_ERR(conn, ERR_CLSD);
+      return ERR_CLSD;
+    }
+    len = ((struct pbuf *)buf)->tot_len;
+  }
+#endif /* LWIP_TCP */
+#if LWIP_TCP && (LWIP_UDP || LWIP_RAW)
+  else
+#endif /* LWIP_TCP && (LWIP_UDP || LWIP_RAW) */
+#if (LWIP_UDP || LWIP_RAW)
+  {
+    LWIP_ASSERT("buf != NULL", buf != NULL);
+    len = netbuf_len((struct netbuf *)buf);
+  }
+#endif /* (LWIP_UDP || LWIP_RAW) */
+
+#if LWIP_SO_RCVBUF
+  SYS_ARCH_DEC(conn->recv_avail, len);
+#endif /* LWIP_SO_RCVBUF */
+  /* Register event with callback */
+  API_EVENT(conn, NETCONN_EVT_RCVMINUS, len);
+
+  LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_recv_data: received %p, len=%"U16_F"\n", buf, len));
+
+  *new_buf = buf;
+  /* don't set conn->last_err: it's only ERR_OK, anyway */
+  return ERR_OK;
+}
+
+/**
+ * Receive data (in form of a pbuf) from a TCP netconn
+ *
+ * @param conn the netconn from which to receive data
+ * @param new_buf pointer where a new pbuf is stored when received data
+ * @return ERR_OK if data has been received, an error code otherwise (timeout,
+ *                memory error or another error)
+ *         ERR_ARG if conn is not a TCP netconn
+ */
+err_t
+netconn_recv_tcp_pbuf(struct netconn *conn, struct pbuf **new_buf)
+{
+  LWIP_ERROR("netconn_recv: invalid conn", (conn != NULL) &&
+             netconn_type(conn) == NETCONN_TCP, return ERR_ARG;);
+
+  return netconn_recv_data(conn, (void **)new_buf);
+}
+
+/**
+ * Receive data (in form of a netbuf containing a packet buffer) from a netconn
+ *
+ * @param conn the netconn from which to receive data
+ * @param new_buf pointer where a new netbuf is stored when received data
+ * @return ERR_OK if data has been received, an error code otherwise (timeout,
+ *                memory error or another error)
+ */
+err_t
+netconn_recv(struct netconn *conn, struct netbuf **new_buf)
+{
+#if LWIP_TCP
+  struct netbuf *buf = NULL;
+  err_t err;
+#endif /* LWIP_TCP */
+
+  LWIP_ERROR("netconn_recv: invalid pointer", (new_buf != NULL), return ERR_ARG;);
+  *new_buf = NULL;
+  LWIP_ERROR("netconn_recv: invalid conn",    (conn != NULL),    return ERR_ARG;);
+  LWIP_ERROR("netconn_accept: invalid recvmbox", sys_mbox_valid(&conn->recvmbox), return ERR_CONN;);
+
+#if LWIP_TCP
+  if (conn->type == NETCONN_TCP) {
+    struct pbuf *p = NULL;
+    /* This is not a listening netconn, since recvmbox is set */
+
+    buf = (struct netbuf *)memp_malloc(MEMP_NETBUF);
+    if (buf == NULL) {
+      NETCONN_SET_SAFE_ERR(conn, ERR_MEM);
+      return ERR_MEM;
+    }
+
+    err = netconn_recv_data(conn, (void **)&p);
+    if (err != ERR_OK) {
+      memp_free(MEMP_NETBUF, buf);
+      return err;
+    }
+    LWIP_ASSERT("p != NULL", p != NULL);
+
+    buf->p = p;
+    buf->ptr = p;
+    buf->port = 0;
+    ip_addr_set_any(&buf->addr);
+    *new_buf = buf;
+    /* don't set conn->last_err: it's only ERR_OK, anyway */
+    return ERR_OK;
+  } else
+#endif /* LWIP_TCP */
+  {
+#if (LWIP_UDP || LWIP_RAW)
+    return netconn_recv_data(conn, (void **)new_buf);
+#endif /* (LWIP_UDP || LWIP_RAW) */
+  }
+}
+
+/**
+ * TCP: update the receive window: by calling this, the application
+ * tells the stack that it has processed data and is able to accept
+ * new data.
+ * ATTENTION: use with care, this is mainly used for sockets!
+ * Can only be used when calling netconn_set_noautorecved(conn, 1) before.
+ *
+ * @param conn the netconn for which to update the receive window
+ * @param length amount of data processed (ATTENTION: this must be accurate!)
+ */
+void
+netconn_recved(struct netconn *conn, u32_t length)
+{
+#if LWIP_TCP
+  if ((conn != NULL) && (conn->type == NETCONN_TCP) &&
+      (netconn_get_noautorecved(conn))) {
+    struct api_msg msg;
+    /* Let the stack know that we have taken the data. */
+    /* TODO: Speedup: Don't block and wait for the answer here
+       (to prevent multiple thread-switches). */
+    msg.function = do_recv;
+    msg.msg.conn = conn;
+    msg.msg.msg.r.len = length;
+    /* don't care for the return value of do_recv */
+    TCPIP_APIMSG(&msg);
+  }
+#else /* LWIP_TCP */
+  LWIP_UNUSED_ARG(conn);
+  LWIP_UNUSED_ARG(length);
+#endif /* LWIP_TCP */
+}
+
+/**
+ * Send data (in form of a netbuf) to a specific remote IP address and port.
+ * Only to be used for UDP and RAW netconns (not TCP).
+ *
+ * @param conn the netconn over which to send data
+ * @param buf a netbuf containing the data to send
+ * @param addr the remote IP address to which to send the data
+ * @param port the remote port to which to send the data
+ * @return ERR_OK if data was sent, any other err_t on error
+ */
+err_t
+netconn_sendto(struct netconn *conn, struct netbuf *buf, ip_addr_t *addr, u16_t port)
+{
+  if (buf != NULL) {
+    ip_addr_set(&buf->addr, addr);
+    buf->port = port;
+    return netconn_send(conn, buf);
+  }
+  return ERR_VAL;
+}
+
+/**
+ * Send data over a UDP or RAW netconn (that is already connected).
+ *
+ * @param conn the UDP or RAW netconn over which to send data
+ * @param buf a netbuf containing the data to send
+ * @return ERR_OK if data was sent, any other err_t on error
+ */
+err_t
+netconn_send(struct netconn *conn, struct netbuf *buf)
+{
+  struct api_msg msg;
+  err_t err;
+
+  LWIP_ERROR("netconn_send: invalid conn",  (conn != NULL), return ERR_ARG;);
+
+  LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_send: sending %"U16_F" bytes\n", buf->p->tot_len));
+  msg.function = do_send;
+  msg.msg.conn = conn;
+  msg.msg.msg.b = buf;
+  err = TCPIP_APIMSG(&msg);
+
+  NETCONN_SET_SAFE_ERR(conn, err);
+  return err;
+}
+
+/**
+ * Send data over a TCP netconn.
+ *
+ * @param conn the TCP netconn over which to send data
+ * @param dataptr pointer to the application buffer that contains the data to send
+ * @param size size of the application data to send
+ * @param apiflags combination of following flags :
+ * - NETCONN_COPY: data will be copied into memory belonging to the stack
+ * - NETCONN_MORE: for TCP connection, PSH flag will be set on last segment sent
+ * - NETCONN_DONTBLOCK: only write the data if all dat can be written at once
+ * @return ERR_OK if data was sent, any other err_t on error
+ */
+err_t
+netconn_write(struct netconn *conn, const void *dataptr, size_t size, u8_t apiflags)
+{
+  struct api_msg msg;
+  err_t err;
+
+  LWIP_ERROR("netconn_write: invalid conn",  (conn != NULL), return ERR_ARG;);
+  LWIP_ERROR("netconn_write: invalid conn->type",  (conn->type == NETCONN_TCP), return ERR_VAL;);
+  if (size == 0) {
+    return ERR_OK;
+  }
+
+  /* @todo: for non-blocking write, check if 'size' would ever fit into
+            snd_queue or snd_buf */
+  msg.function = do_write;
+  msg.msg.conn = conn;
+  msg.msg.msg.w.dataptr = dataptr;
+  msg.msg.msg.w.apiflags = apiflags;
+  msg.msg.msg.w.len = size;
+  /* For locking the core: this _can_ be delayed on low memory/low send buffer,
+     but if it is, this is done inside api_msg.c:do_write(), so we can use the
+     non-blocking version here. */
+  err = TCPIP_APIMSG(&msg);
+
+  NETCONN_SET_SAFE_ERR(conn, err);
+  return err;
+}
+
+/**
+ * Close ot shutdown a TCP netconn (doesn't delete it).
+ *
+ * @param conn the TCP netconn to close or shutdown
+ * @param how fully close or only shutdown one side?
+ * @return ERR_OK if the netconn was closed, any other err_t on error
+ */
+static err_t
+netconn_close_shutdown(struct netconn *conn, u8_t how)
+{
+  struct api_msg msg;
+  err_t err;
+
+  LWIP_ERROR("netconn_close: invalid conn",  (conn != NULL), return ERR_ARG;);
+
+  msg.function = do_close;
+  msg.msg.conn = conn;
+  /* shutting down both ends is the same as closing */
+  msg.msg.msg.sd.shut = how;
+  /* because of the LWIP_TCPIP_CORE_LOCKING implementation of do_close,
+     don't use TCPIP_APIMSG here */
+  err = tcpip_apimsg(&msg);
+
+  NETCONN_SET_SAFE_ERR(conn, err);
+  return err;
+}
+
+/**
+ * Close a TCP netconn (doesn't delete it).
+ *
+ * @param conn the TCP netconn to close
+ * @return ERR_OK if the netconn was closed, any other err_t on error
+ */
+err_t
+netconn_close(struct netconn *conn)
+{
+  /* shutting down both ends is the same as closing */
+  return netconn_close_shutdown(conn, NETCONN_SHUT_RDWR);
+}
+
+/**
+ * Shut down one or both sides of a TCP netconn (doesn't delete it).
+ *
+ * @param conn the TCP netconn to shut down
+ * @return ERR_OK if the netconn was closed, any other err_t on error
+ */
+err_t
+netconn_shutdown(struct netconn *conn, u8_t shut_rx, u8_t shut_tx)
+{
+  return netconn_close_shutdown(conn, (shut_rx ? NETCONN_SHUT_RD : 0) | (shut_tx ? NETCONN_SHUT_WR : 0));
+}
+
+#if LWIP_IGMP
+/**
+ * Join multicast groups for UDP netconns.
+ *
+ * @param conn the UDP netconn for which to change multicast addresses
+ * @param multiaddr IP address of the multicast group to join or leave
+ * @param netif_addr the IP address of the network interface on which to send
+ *                  the igmp message
+ * @param join_or_leave flag whether to send a join- or leave-message
+ * @return ERR_OK if the action was taken, any err_t on error
+ */
+err_t
+netconn_join_leave_group(struct netconn *conn,
+                         ip_addr_t *multiaddr,
+                         ip_addr_t *netif_addr,
+                         enum netconn_igmp join_or_leave)
+{
+  struct api_msg msg;
+  err_t err;
+
+  LWIP_ERROR("netconn_join_leave_group: invalid conn",  (conn != NULL), return ERR_ARG;);
+
+  msg.function = do_join_leave_group;
+  msg.msg.conn = conn;
+  msg.msg.msg.jl.multiaddr = multiaddr;
+  msg.msg.msg.jl.netif_addr = netif_addr;
+  msg.msg.msg.jl.join_or_leave = join_or_leave;
+  err = TCPIP_APIMSG(&msg);
+
+  NETCONN_SET_SAFE_ERR(conn, err);
+  return err;
+}
+#endif /* LWIP_IGMP */
+
+#if LWIP_DNS
+/**
+ * Execute a DNS query, only one IP address is returned
+ *
+ * @param name a string representation of the DNS host name to query
+ * @param addr a preallocated ip_addr_t where to store the resolved IP address
+ * @return ERR_OK: resolving succeeded
+ *         ERR_MEM: memory error, try again later
+ *         ERR_ARG: dns client not initialized or invalid hostname
+ *         ERR_VAL: dns server response was invalid
+ */
+err_t
+netconn_gethostbyname(const char *name, ip_addr_t *addr)
+{
+  struct dns_api_msg msg;
+  err_t err;
+  sys_sem_t sem;
+
+  LWIP_ERROR("netconn_gethostbyname: invalid name", (name != NULL), return ERR_ARG;);
+  LWIP_ERROR("netconn_gethostbyname: invalid addr", (addr != NULL), return ERR_ARG;);
+
+  err = sys_sem_new(&sem, 0);
+  if (err != ERR_OK) {
+    return err;
+  }
+
+  msg.name = name;
+  msg.addr = addr;
+  msg.err = &err;
+  msg.sem = &sem;
+
+  tcpip_callback(do_gethostbyname, &msg);
+  sys_sem_wait(&sem);
+  sys_sem_free(&sem);
+
+  return err;
+}
+#endif /* LWIP_DNS*/
+
+#endif /* LWIP_NETCONN */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/api_msg.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/api_msg.c
new file mode 100644
index 0000000..448f96d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/api_msg.c
@@ -0,0 +1,1535 @@
+/**
+ * @file
+ * Sequential API Internal module
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/api_msg.h"
+
+#include "lwip/ip.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+#include "lwip/raw.h"
+
+#include "lwip/memp.h"
+#include "lwip/tcpip.h"
+#include "lwip/igmp.h"
+#include "lwip/dns.h"
+
+#include 
+
+#define SET_NONBLOCKING_CONNECT(conn, val)  do { if(val) { \
+  (conn)->flags |= NETCONN_FLAG_IN_NONBLOCKING_CONNECT; \
+} else { \
+  (conn)->flags &= ~ NETCONN_FLAG_IN_NONBLOCKING_CONNECT; }} while(0)
+#define IN_NONBLOCKING_CONNECT(conn) (((conn)->flags & NETCONN_FLAG_IN_NONBLOCKING_CONNECT) != 0)
+
+/* forward declarations */
+#if LWIP_TCP
+static err_t do_writemore(struct netconn *conn);
+static void do_close_internal(struct netconn *conn);
+#endif
+
+#if LWIP_RAW
+/**
+ * Receive callback function for RAW netconns.
+ * Doesn't 'eat' the packet, only references it and sends it to
+ * conn->recvmbox
+ *
+ * @see raw.h (struct raw_pcb.recv) for parameters and return value
+ */
+static u8_t
+recv_raw(void *arg, struct raw_pcb *pcb, struct pbuf *p,
+    ip_addr_t *addr)
+{
+  struct pbuf *q;
+  struct netbuf *buf;
+  struct netconn *conn;
+
+  LWIP_UNUSED_ARG(addr);
+  conn = (struct netconn *)arg;
+
+  if ((conn != NULL) && sys_mbox_valid(&conn->recvmbox)) {
+#if LWIP_SO_RCVBUF
+    int recv_avail;
+    SYS_ARCH_GET(conn->recv_avail, recv_avail);
+    if ((recv_avail + (int)(p->tot_len)) > conn->recv_bufsize) {
+      return 0;
+    }
+#endif /* LWIP_SO_RCVBUF */
+    /* copy the whole packet into new pbufs */
+    q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
+    if(q != NULL) {
+      if (pbuf_copy(q, p) != ERR_OK) {
+        pbuf_free(q);
+        q = NULL;
+      }
+    }
+
+    if (q != NULL) {
+      u16_t len;
+      buf = (struct netbuf *)memp_malloc(MEMP_NETBUF);
+      if (buf == NULL) {
+        pbuf_free(q);
+        return 0;
+      }
+
+      buf->p = q;
+      buf->ptr = q;
+      ip_addr_copy(buf->addr, *ip_current_src_addr());
+      buf->port = pcb->protocol;
+
+      len = q->tot_len;
+      if (sys_mbox_trypost(&conn->recvmbox, buf) != ERR_OK) {
+        netbuf_delete(buf);
+        return 0;
+      } else {
+#if LWIP_SO_RCVBUF
+        SYS_ARCH_INC(conn->recv_avail, len);
+#endif /* LWIP_SO_RCVBUF */
+        /* Register event with callback */
+        API_EVENT(conn, NETCONN_EVT_RCVPLUS, len);
+      }
+    }
+  }
+
+  return 0; /* do not eat the packet */
+}
+#endif /* LWIP_RAW*/
+
+#if LWIP_UDP
+/**
+ * Receive callback function for UDP netconns.
+ * Posts the packet to conn->recvmbox or deletes it on memory error.
+ *
+ * @see udp.h (struct udp_pcb.recv) for parameters
+ */
+static void
+recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p,
+   ip_addr_t *addr, u16_t port)
+{
+  struct netbuf *buf;
+  struct netconn *conn;
+  u16_t len;
+#if LWIP_SO_RCVBUF
+  int recv_avail;
+#endif /* LWIP_SO_RCVBUF */
+
+  LWIP_UNUSED_ARG(pcb); /* only used for asserts... */
+  LWIP_ASSERT("recv_udp must have a pcb argument", pcb != NULL);
+  LWIP_ASSERT("recv_udp must have an argument", arg != NULL);
+  conn = (struct netconn *)arg;
+  LWIP_ASSERT("recv_udp: recv for wrong pcb!", conn->pcb.udp == pcb);
+
+#if LWIP_SO_RCVBUF
+  SYS_ARCH_GET(conn->recv_avail, recv_avail);
+  if ((conn == NULL) || !sys_mbox_valid(&conn->recvmbox) ||
+      ((recv_avail + (int)(p->tot_len)) > conn->recv_bufsize)) {
+#else  /* LWIP_SO_RCVBUF */
+  if ((conn == NULL) || !sys_mbox_valid(&conn->recvmbox)) {
+#endif /* LWIP_SO_RCVBUF */
+    pbuf_free(p);
+    return;
+  }
+
+  buf = (struct netbuf *)memp_malloc(MEMP_NETBUF);
+  if (buf == NULL) {
+    pbuf_free(p);
+    return;
+  } else {
+    buf->p = p;
+    buf->ptr = p;
+    ip_addr_set(&buf->addr, addr);
+    buf->port = port;
+#if LWIP_NETBUF_RECVINFO
+    {
+      const struct ip_hdr* iphdr = ip_current_header();
+      /* get the UDP header - always in the first pbuf, ensured by udp_input */
+      const struct udp_hdr* udphdr = (void*)(((char*)iphdr) + IPH_LEN(iphdr));
+#if LWIP_CHECKSUM_ON_COPY
+      buf->flags = NETBUF_FLAG_DESTADDR;
+#endif /* LWIP_CHECKSUM_ON_COPY */
+      ip_addr_set(&buf->toaddr, ip_current_dest_addr());
+      buf->toport_chksum = udphdr->dest;
+    }
+#endif /* LWIP_NETBUF_RECVINFO */
+  }
+
+  len = p->tot_len;
+  if (sys_mbox_trypost(&conn->recvmbox, buf) != ERR_OK) {
+    netbuf_delete(buf);
+    return;
+  } else {
+#if LWIP_SO_RCVBUF
+    SYS_ARCH_INC(conn->recv_avail, len);
+#endif /* LWIP_SO_RCVBUF */
+    /* Register event with callback */
+    API_EVENT(conn, NETCONN_EVT_RCVPLUS, len);
+  }
+}
+#endif /* LWIP_UDP */
+
+#if LWIP_TCP
+/**
+ * Receive callback function for TCP netconns.
+ * Posts the packet to conn->recvmbox, but doesn't delete it on errors.
+ *
+ * @see tcp.h (struct tcp_pcb.recv) for parameters and return value
+ */
+static err_t
+recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
+{
+  struct netconn *conn;
+  u16_t len;
+
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_ASSERT("recv_tcp must have a pcb argument", pcb != NULL);
+  LWIP_ASSERT("recv_tcp must have an argument", arg != NULL);
+  conn = (struct netconn *)arg;
+  LWIP_ASSERT("recv_tcp: recv for wrong pcb!", conn->pcb.tcp == pcb);
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+  if (!sys_mbox_valid(&conn->recvmbox)) {
+    /* recvmbox already deleted */
+    if (p != NULL) {
+      tcp_recved(pcb, p->tot_len);
+      pbuf_free(p);
+    }
+    return ERR_OK;
+  }
+  /* Unlike for UDP or RAW pcbs, don't check for available space
+     using recv_avail since that could break the connection
+     (data is already ACKed) */
+
+  /* don't overwrite fatal errors! */
+  NETCONN_SET_SAFE_ERR(conn, err);
+
+  if (p != NULL) {
+    len = p->tot_len;
+  } else {
+    len = 0;
+  }
+
+  if (sys_mbox_trypost(&conn->recvmbox, p) != ERR_OK) {
+    /* don't deallocate p: it is presented to us later again from tcp_fasttmr! */
+    return ERR_MEM;
+  } else {
+#if LWIP_SO_RCVBUF
+    SYS_ARCH_INC(conn->recv_avail, len);
+#endif /* LWIP_SO_RCVBUF */
+    /* Register event with callback */
+    API_EVENT(conn, NETCONN_EVT_RCVPLUS, len);
+  }
+
+  return ERR_OK;
+}
+
+/**
+ * Poll callback function for TCP netconns.
+ * Wakes up an application thread that waits for a connection to close
+ * or data to be sent. The application thread then takes the
+ * appropriate action to go on.
+ *
+ * Signals the conn->sem.
+ * netconn_close waits for conn->sem if closing failed.
+ *
+ * @see tcp.h (struct tcp_pcb.poll) for parameters and return value
+ */
+static err_t
+poll_tcp(void *arg, struct tcp_pcb *pcb)
+{
+  struct netconn *conn = (struct netconn *)arg;
+
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_ASSERT("conn != NULL", (conn != NULL));
+
+  if (conn->state == NETCONN_WRITE) {
+    do_writemore(conn);
+  } else if (conn->state == NETCONN_CLOSE) {
+    do_close_internal(conn);
+  }
+  /* @todo: implement connect timeout here? */
+
+  /* Did a nonblocking write fail before? Then check available write-space. */
+  if (conn->flags & NETCONN_FLAG_CHECK_WRITESPACE) {
+    /* If the queued byte- or pbuf-count drops below the configured low-water limit,
+       let select mark this pcb as writable again. */
+    if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) &&
+      (tcp_sndqueuelen(conn->pcb.tcp) < TCP_SNDQUEUELOWAT)) {
+      conn->flags &= ~NETCONN_FLAG_CHECK_WRITESPACE;
+      API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0);
+    }
+  }
+
+  return ERR_OK;
+}
+
+/**
+ * Sent callback function for TCP netconns.
+ * Signals the conn->sem and calls API_EVENT.
+ * netconn_write waits for conn->sem if send buffer is low.
+ *
+ * @see tcp.h (struct tcp_pcb.sent) for parameters and return value
+ */
+static err_t
+sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len)
+{
+  struct netconn *conn = (struct netconn *)arg;
+
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_ASSERT("conn != NULL", (conn != NULL));
+
+  if (conn->state == NETCONN_WRITE) {
+    do_writemore(conn);
+  } else if (conn->state == NETCONN_CLOSE) {
+    do_close_internal(conn);
+  }
+
+  if (conn) {
+    /* If the queued byte- or pbuf-count drops below the configured low-water limit,
+       let select mark this pcb as writable again. */
+    if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) &&
+      (tcp_sndqueuelen(conn->pcb.tcp) < TCP_SNDQUEUELOWAT)) {
+      conn->flags &= ~NETCONN_FLAG_CHECK_WRITESPACE;
+      API_EVENT(conn, NETCONN_EVT_SENDPLUS, len);
+    }
+  }
+  
+  return ERR_OK;
+}
+
+/**
+ * Error callback function for TCP netconns.
+ * Signals conn->sem, posts to all conn mboxes and calls API_EVENT.
+ * The application thread has then to decide what to do.
+ *
+ * @see tcp.h (struct tcp_pcb.err) for parameters
+ */
+static void
+err_tcp(void *arg, err_t err)
+{
+  struct netconn *conn;
+  enum netconn_state old_state;
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  conn = (struct netconn *)arg;
+  LWIP_ASSERT("conn != NULL", (conn != NULL));
+
+  conn->pcb.tcp = NULL;
+
+  /* no check since this is always fatal! */
+  SYS_ARCH_PROTECT(lev);
+  conn->last_err = err;
+  SYS_ARCH_UNPROTECT(lev);
+
+  /* reset conn->state now before waking up other threads */
+  old_state = conn->state;
+  conn->state = NETCONN_NONE;
+
+  /* Notify the user layer about a connection error. Used to signal
+     select. */
+  API_EVENT(conn, NETCONN_EVT_ERROR, 0);
+  /* Try to release selects pending on 'read' or 'write', too.
+     They will get an error if they actually try to read or write. */
+  API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0);
+  API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0);
+
+  /* pass NULL-message to recvmbox to wake up pending recv */
+  if (sys_mbox_valid(&conn->recvmbox)) {
+    /* use trypost to prevent deadlock */
+    sys_mbox_trypost(&conn->recvmbox, NULL);
+  }
+  /* pass NULL-message to acceptmbox to wake up pending accept */
+  if (sys_mbox_valid(&conn->acceptmbox)) {
+    /* use trypost to preven deadlock */
+    sys_mbox_trypost(&conn->acceptmbox, NULL);
+  }
+
+  if ((old_state == NETCONN_WRITE) || (old_state == NETCONN_CLOSE) ||
+      (old_state == NETCONN_CONNECT)) {
+    /* calling do_writemore/do_close_internal is not necessary
+       since the pcb has already been deleted! */
+    int was_nonblocking_connect = IN_NONBLOCKING_CONNECT(conn);
+    SET_NONBLOCKING_CONNECT(conn, 0);
+
+    if (!was_nonblocking_connect) {
+      /* set error return code */
+      LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL);
+      conn->current_msg->err = err;
+      conn->current_msg = NULL;
+      /* wake up the waiting task */
+      sys_sem_signal(&conn->op_completed);
+    }
+  } else {
+    LWIP_ASSERT("conn->current_msg == NULL", conn->current_msg == NULL);
+  }
+}
+
+/**
+ * Setup a tcp_pcb with the correct callback function pointers
+ * and their arguments.
+ *
+ * @param conn the TCP netconn to setup
+ */
+static void
+setup_tcp(struct netconn *conn)
+{
+  struct tcp_pcb *pcb;
+
+  pcb = conn->pcb.tcp;
+  tcp_arg(pcb, conn);
+  tcp_recv(pcb, recv_tcp);
+  tcp_sent(pcb, sent_tcp);
+  tcp_poll(pcb, poll_tcp, 4);
+  tcp_err(pcb, err_tcp);
+}
+
+/**
+ * Accept callback function for TCP netconns.
+ * Allocates a new netconn and posts that to conn->acceptmbox.
+ *
+ * @see tcp.h (struct tcp_pcb_listen.accept) for parameters and return value
+ */
+static err_t
+accept_function(void *arg, struct tcp_pcb *newpcb, err_t err)
+{
+  struct netconn *newconn;
+  struct netconn *conn = (struct netconn *)arg;
+
+  LWIP_DEBUGF(API_MSG_DEBUG, ("accept_function: newpcb->tate: %s\n", tcp_debug_state_str(newpcb->state)));
+
+  if (!sys_mbox_valid(&conn->acceptmbox)) {
+    LWIP_DEBUGF(API_MSG_DEBUG, ("accept_function: acceptmbox already deleted\n"));
+    return ERR_VAL;
+  }
+
+  /* We have to set the callback here even though
+   * the new socket is unknown. conn->socket is marked as -1. */
+  newconn = netconn_alloc(conn->type, conn->callback);
+  if (newconn == NULL) {
+    return ERR_MEM;
+  }
+  newconn->pcb.tcp = newpcb;
+  setup_tcp(newconn);
+  /* no protection: when creating the pcb, the netconn is not yet known
+     to the application thread */
+  newconn->last_err = err;
+
+  if (sys_mbox_trypost(&conn->acceptmbox, newconn) != ERR_OK) {
+    /* When returning != ERR_OK, the pcb is aborted in tcp_process(),
+       so do nothing here! */
+    newconn->pcb.tcp = NULL;
+    /* no need to drain since we know the recvmbox is empty. */
+    sys_mbox_free(&newconn->recvmbox);
+    sys_mbox_set_invalid(&newconn->recvmbox);
+    netconn_free(newconn);
+    return ERR_MEM;
+  } else {
+    /* Register event with callback */
+    API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0);
+  }
+
+  return ERR_OK;
+}
+#endif /* LWIP_TCP */
+
+/**
+ * Create a new pcb of a specific type.
+ * Called from do_newconn().
+ *
+ * @param msg the api_msg_msg describing the connection type
+ * @return msg->conn->err, but the return value is currently ignored
+ */
+static void
+pcb_new(struct api_msg_msg *msg)
+{
+  LWIP_ASSERT("pcb_new: pcb already allocated", msg->conn->pcb.tcp == NULL);
+
+  /* Allocate a PCB for this connection */
+  switch(NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+  case NETCONN_RAW:
+    msg->conn->pcb.raw = raw_new(msg->msg.n.proto);
+    if(msg->conn->pcb.raw == NULL) {
+      msg->err = ERR_MEM;
+      break;
+    }
+    raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
+    break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+  case NETCONN_UDP:
+    msg->conn->pcb.udp = udp_new();
+    if(msg->conn->pcb.udp == NULL) {
+      msg->err = ERR_MEM;
+      break;
+    }
+#if LWIP_UDPLITE
+    if (msg->conn->type==NETCONN_UDPLITE) {
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
+    }
+#endif /* LWIP_UDPLITE */
+    if (msg->conn->type==NETCONN_UDPNOCHKSUM) {
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
+    }
+    udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+    break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+  case NETCONN_TCP:
+    msg->conn->pcb.tcp = tcp_new();
+    if(msg->conn->pcb.tcp == NULL) {
+      msg->err = ERR_MEM;
+      break;
+    }
+    setup_tcp(msg->conn);
+    break;
+#endif /* LWIP_TCP */
+  default:
+    /* Unsupported netconn type, e.g. protocol disabled */
+    msg->err = ERR_VAL;
+    break;
+  }
+}
+
+/**
+ * Create a new pcb of a specific type inside a netconn.
+ * Called from netconn_new_with_proto_and_callback.
+ *
+ * @param msg the api_msg_msg describing the connection type
+ */
+void
+do_newconn(struct api_msg_msg *msg)
+{
+  msg->err = ERR_OK;
+  if(msg->conn->pcb.tcp == NULL) {
+    pcb_new(msg);
+  }
+  /* Else? This "new" connection already has a PCB allocated. */
+  /* Is this an error condition? Should it be deleted? */
+  /* We currently just are happy and return. */
+
+  TCPIP_APIMSG_ACK(msg);
+}
+
+/**
+ * Create a new netconn (of a specific type) that has a callback function.
+ * The corresponding pcb is NOT created!
+ *
+ * @param t the type of 'connection' to create (@see enum netconn_type)
+ * @param proto the IP protocol for RAW IP pcbs
+ * @param callback a function to call on status changes (RX available, TX'ed)
+ * @return a newly allocated struct netconn or
+ *         NULL on memory error
+ */
+struct netconn*
+netconn_alloc(enum netconn_type t, netconn_callback callback)
+{
+  struct netconn *conn;
+  int size;
+
+  conn = (struct netconn *)memp_malloc(MEMP_NETCONN);
+  if (conn == NULL) {
+    return NULL;
+  }
+
+  conn->last_err = ERR_OK;
+  conn->type = t;
+  conn->pcb.tcp = NULL;
+
+#if (DEFAULT_RAW_RECVMBOX_SIZE == DEFAULT_UDP_RECVMBOX_SIZE) && \
+    (DEFAULT_RAW_RECVMBOX_SIZE == DEFAULT_TCP_RECVMBOX_SIZE)
+  size = DEFAULT_RAW_RECVMBOX_SIZE;
+#else
+  switch(NETCONNTYPE_GROUP(t)) {
+#if LWIP_RAW
+  case NETCONN_RAW:
+    size = DEFAULT_RAW_RECVMBOX_SIZE;
+    break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+  case NETCONN_UDP:
+    size = DEFAULT_UDP_RECVMBOX_SIZE;
+    break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+  case NETCONN_TCP:
+    size = DEFAULT_TCP_RECVMBOX_SIZE;
+    break;
+#endif /* LWIP_TCP */
+  default:
+    LWIP_ASSERT("netconn_alloc: undefined netconn_type", 0);
+    break;
+  }
+#endif
+
+  if (sys_sem_new(&conn->op_completed, 0) != ERR_OK) {
+    memp_free(MEMP_NETCONN, conn);
+    return NULL;
+  }
+  if (sys_mbox_new(&conn->recvmbox, size) != ERR_OK) {
+    sys_sem_free(&conn->op_completed);
+    memp_free(MEMP_NETCONN, conn);
+    return NULL;
+  }
+
+#if LWIP_TCP
+  sys_mbox_set_invalid(&conn->acceptmbox);
+#endif
+  conn->state        = NETCONN_NONE;
+#if LWIP_SOCKET
+  /* initialize socket to -1 since 0 is a valid socket */
+  conn->socket       = -1;
+#endif /* LWIP_SOCKET */
+  conn->callback     = callback;
+#if LWIP_TCP
+  conn->current_msg  = NULL;
+  conn->write_offset = 0;
+#endif /* LWIP_TCP */
+#if LWIP_SO_RCVTIMEO
+  conn->recv_timeout = 0;
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+  conn->recv_bufsize = RECV_BUFSIZE_DEFAULT;
+  conn->recv_avail   = 0;
+#endif /* LWIP_SO_RCVBUF */
+  conn->flags = 0;
+  return conn;
+}
+
+/**
+ * Delete a netconn and all its resources.
+ * The pcb is NOT freed (since we might not be in the right thread context do this).
+ *
+ * @param conn the netconn to free
+ */
+void
+netconn_free(struct netconn *conn)
+{
+  LWIP_ASSERT("PCB must be deallocated outside this function", conn->pcb.tcp == NULL);
+  LWIP_ASSERT("recvmbox must be deallocated before calling this function",
+    !sys_mbox_valid(&conn->recvmbox));
+#if LWIP_TCP
+  LWIP_ASSERT("acceptmbox must be deallocated before calling this function",
+    !sys_mbox_valid(&conn->acceptmbox));
+#endif /* LWIP_TCP */
+
+  sys_sem_free(&conn->op_completed);
+  sys_sem_set_invalid(&conn->op_completed);
+
+  memp_free(MEMP_NETCONN, conn);
+}
+
+/**
+ * Delete rcvmbox and acceptmbox of a netconn and free the left-over data in
+ * these mboxes
+ *
+ * @param conn the netconn to free
+ * @bytes_drained bytes drained from recvmbox
+ * @accepts_drained pending connections drained from acceptmbox
+ */
+static void
+netconn_drain(struct netconn *conn)
+{
+  void *mem;
+#if LWIP_TCP
+  struct pbuf *p;
+#endif /* LWIP_TCP */
+
+  /* This runs in tcpip_thread, so we don't need to lock against rx packets */
+
+  /* Delete and drain the recvmbox. */
+  if (sys_mbox_valid(&conn->recvmbox)) {
+    while (sys_mbox_tryfetch(&conn->recvmbox, &mem) != SYS_MBOX_EMPTY) {
+#if LWIP_TCP
+      if (conn->type == NETCONN_TCP) {
+        if(mem != NULL) {
+          p = (struct pbuf*)mem;
+          /* pcb might be set to NULL already by err_tcp() */
+          if (conn->pcb.tcp != NULL) {
+            tcp_recved(conn->pcb.tcp, p->tot_len);
+          }
+          pbuf_free(p);
+        }
+      } else
+#endif /* LWIP_TCP */
+      {
+        netbuf_delete((struct netbuf *)mem);
+      }
+    }
+    sys_mbox_free(&conn->recvmbox);
+    sys_mbox_set_invalid(&conn->recvmbox);
+  }
+
+  /* Delete and drain the acceptmbox. */
+#if LWIP_TCP
+  if (sys_mbox_valid(&conn->acceptmbox)) {
+    while (sys_mbox_tryfetch(&conn->acceptmbox, &mem) != SYS_MBOX_EMPTY) {
+      struct netconn *newconn = (struct netconn *)mem;
+      /* Only tcp pcbs have an acceptmbox, so no need to check conn->type */
+      /* pcb might be set to NULL already by err_tcp() */
+      if (conn->pcb.tcp != NULL) {
+        tcp_accepted(conn->pcb.tcp);
+      }
+      /* drain recvmbox */
+      netconn_drain(newconn);
+      if (newconn->pcb.tcp != NULL) {
+        tcp_abort(newconn->pcb.tcp);
+        newconn->pcb.tcp = NULL;
+      }
+      netconn_free(newconn);
+    }
+    sys_mbox_free(&conn->acceptmbox);
+    sys_mbox_set_invalid(&conn->acceptmbox);
+  }
+#endif /* LWIP_TCP */
+}
+
+#if LWIP_TCP
+/**
+ * Internal helper function to close a TCP netconn: since this sometimes
+ * doesn't work at the first attempt, this function is called from multiple
+ * places.
+ *
+ * @param conn the TCP netconn to close
+ */
+static void
+do_close_internal(struct netconn *conn)
+{
+  err_t err;
+  u8_t shut, shut_rx, shut_tx, close;
+
+  LWIP_ASSERT("invalid conn", (conn != NULL));
+  LWIP_ASSERT("this is for tcp netconns only", (conn->type == NETCONN_TCP));
+  LWIP_ASSERT("conn must be in state NETCONN_CLOSE", (conn->state == NETCONN_CLOSE));
+  LWIP_ASSERT("pcb already closed", (conn->pcb.tcp != NULL));
+  LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL);
+
+  shut = conn->current_msg->msg.sd.shut;
+  shut_rx = shut & NETCONN_SHUT_RD;
+  shut_tx = shut & NETCONN_SHUT_WR;
+  /* shutting down both ends is the same as closing */
+  close = shut == NETCONN_SHUT_RDWR;
+
+  /* Set back some callback pointers */
+  if (close) {
+    tcp_arg(conn->pcb.tcp, NULL);
+  }
+  if (conn->pcb.tcp->state == LISTEN) {
+    tcp_accept(conn->pcb.tcp, NULL);
+  } else {
+    /* some callbacks have to be reset if tcp_close is not successful */
+    if (shut_rx) {
+      tcp_recv(conn->pcb.tcp, NULL);
+      tcp_accept(conn->pcb.tcp, NULL);
+    }
+    if (shut_tx) {
+      tcp_sent(conn->pcb.tcp, NULL);
+    }
+    if (close) {
+      tcp_poll(conn->pcb.tcp, NULL, 4);
+      tcp_err(conn->pcb.tcp, NULL);
+    }
+  }
+  /* Try to close the connection */
+  if (shut == NETCONN_SHUT_RDWR) {
+    err = tcp_close(conn->pcb.tcp);
+  } else {
+    err = tcp_shutdown(conn->pcb.tcp, shut & NETCONN_SHUT_RD, shut & NETCONN_SHUT_WR);
+  }
+  if (err == ERR_OK) {
+    /* Closing succeeded */
+    conn->current_msg->err = ERR_OK;
+    conn->current_msg = NULL;
+    conn->state = NETCONN_NONE;
+    /* Set back some callback pointers as conn is going away */
+    conn->pcb.tcp = NULL;
+    /* Trigger select() in socket layer. Make sure everybody notices activity
+       on the connection, error first! */
+    if (close) {
+      API_EVENT(conn, NETCONN_EVT_ERROR, 0);
+    }
+    if (shut_rx) {
+      API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0);
+    }
+    if (shut_tx) {
+      API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0);
+    }
+    /* wake up the application task */
+    sys_sem_signal(&conn->op_completed);
+  } else {
+    /* Closing failed, restore some of the callbacks */
+    /* Closing of listen pcb will never fail! */
+    LWIP_ASSERT("Closing a listen pcb may not fail!", (conn->pcb.tcp->state != LISTEN));
+    tcp_sent(conn->pcb.tcp, sent_tcp);
+    tcp_poll(conn->pcb.tcp, poll_tcp, 4);
+    tcp_err(conn->pcb.tcp, err_tcp);
+    tcp_arg(conn->pcb.tcp, conn);
+    /* don't restore recv callback: we don't want to receive any more data */
+  }
+  /* If closing didn't succeed, we get called again either
+     from poll_tcp or from sent_tcp */
+}
+#endif /* LWIP_TCP */
+
+/**
+ * Delete the pcb inside a netconn.
+ * Called from netconn_delete.
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_delconn(struct api_msg_msg *msg)
+{
+  /* @todo TCP: abort running write/connect? */
+ if ((msg->conn->state != NETCONN_NONE) &&
+     (msg->conn->state != NETCONN_LISTEN) &&
+     (msg->conn->state != NETCONN_CONNECT)) {
+    /* this only happens for TCP netconns */
+    LWIP_ASSERT("msg->conn->type == NETCONN_TCP", msg->conn->type == NETCONN_TCP);
+    msg->err = ERR_INPROGRESS;
+  } else {
+    LWIP_ASSERT("blocking connect in progress",
+      (msg->conn->state != NETCONN_CONNECT) || IN_NONBLOCKING_CONNECT(msg->conn));
+    /* Drain and delete mboxes */
+    netconn_drain(msg->conn);
+
+    if (msg->conn->pcb.tcp != NULL) {
+
+      switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+      case NETCONN_RAW:
+        raw_remove(msg->conn->pcb.raw);
+        break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+      case NETCONN_UDP:
+        msg->conn->pcb.udp->recv_arg = NULL;
+        udp_remove(msg->conn->pcb.udp);
+        break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+      case NETCONN_TCP:
+        LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL &&
+          msg->conn->write_offset == 0);
+        msg->conn->state = NETCONN_CLOSE;
+        msg->msg.sd.shut = NETCONN_SHUT_RDWR;
+        msg->conn->current_msg = msg;
+        do_close_internal(msg->conn);
+        /* API_EVENT is called inside do_close_internal, before releasing
+           the application thread, so we can return at this point! */
+        return;
+#endif /* LWIP_TCP */
+      default:
+        break;
+      }
+      msg->conn->pcb.tcp = NULL;
+    }
+    /* tcp netconns don't come here! */
+
+    /* @todo: this lets select make the socket readable and writable,
+       which is wrong! errfd instead? */
+    API_EVENT(msg->conn, NETCONN_EVT_RCVPLUS, 0);
+    API_EVENT(msg->conn, NETCONN_EVT_SENDPLUS, 0);
+  }
+  if (sys_sem_valid(&msg->conn->op_completed)) {
+    sys_sem_signal(&msg->conn->op_completed);
+  }
+}
+
+/**
+ * Bind a pcb contained in a netconn
+ * Called from netconn_bind.
+ *
+ * @param msg the api_msg_msg pointing to the connection and containing
+ *            the IP address and port to bind to
+ */
+void
+do_bind(struct api_msg_msg *msg)
+{
+  if (ERR_IS_FATAL(msg->conn->last_err)) {
+    msg->err = msg->conn->last_err;
+  } else {
+    msg->err = ERR_VAL;
+    if (msg->conn->pcb.tcp != NULL) {
+      switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+      case NETCONN_RAW:
+        msg->err = raw_bind(msg->conn->pcb.raw, msg->msg.bc.ipaddr);
+        break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+      case NETCONN_UDP:
+        msg->err = udp_bind(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port);
+        break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+      case NETCONN_TCP:
+        msg->err = tcp_bind(msg->conn->pcb.tcp, msg->msg.bc.ipaddr, msg->msg.bc.port);
+        break;
+#endif /* LWIP_TCP */
+      default:
+        break;
+      }
+    }
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+
+#if LWIP_TCP
+/**
+ * TCP callback function if a connection (opened by tcp_connect/do_connect) has
+ * been established (or reset by the remote host).
+ *
+ * @see tcp.h (struct tcp_pcb.connected) for parameters and return values
+ */
+static err_t
+do_connected(void *arg, struct tcp_pcb *pcb, err_t err)
+{
+  struct netconn *conn;
+  int was_blocking;
+
+  LWIP_UNUSED_ARG(pcb);
+
+  conn = (struct netconn *)arg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  LWIP_ASSERT("conn->state == NETCONN_CONNECT", conn->state == NETCONN_CONNECT);
+  LWIP_ASSERT("(conn->current_msg != NULL) || conn->in_non_blocking_connect",
+    (conn->current_msg != NULL) || IN_NONBLOCKING_CONNECT(conn));
+
+  if (conn->current_msg != NULL) {
+    conn->current_msg->err = err;
+  }
+  if ((conn->type == NETCONN_TCP) && (err == ERR_OK)) {
+    setup_tcp(conn);
+  }
+  was_blocking = !IN_NONBLOCKING_CONNECT(conn);
+  SET_NONBLOCKING_CONNECT(conn, 0);
+  conn->current_msg = NULL;
+  conn->state = NETCONN_NONE;
+  if (!was_blocking) {
+    NETCONN_SET_SAFE_ERR(conn, ERR_OK);
+  }
+  API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0);
+
+  if (was_blocking) {
+    sys_sem_signal(&conn->op_completed);
+  }
+  return ERR_OK;
+}
+#endif /* LWIP_TCP */
+
+/**
+ * Connect a pcb contained inside a netconn
+ * Called from netconn_connect.
+ *
+ * @param msg the api_msg_msg pointing to the connection and containing
+ *            the IP address and port to connect to
+ */
+void
+do_connect(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp == NULL) {
+    /* This may happen when calling netconn_connect() a second time */
+    msg->err = ERR_CLSD;
+  } else {
+    switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+  case NETCONN_RAW:
+    msg->err = raw_connect(msg->conn->pcb.raw, msg->msg.bc.ipaddr);
+    break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+  case NETCONN_UDP:
+    msg->err = udp_connect(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port);
+    break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+  case NETCONN_TCP:
+    /* Prevent connect while doing any other action. */
+    if (msg->conn->state != NETCONN_NONE) {
+      msg->err = ERR_ISCONN;
+    } else {
+      setup_tcp(msg->conn);
+      msg->err = tcp_connect(msg->conn->pcb.tcp, msg->msg.bc.ipaddr,
+        msg->msg.bc.port, do_connected);
+      if (msg->err == ERR_OK) {
+        u8_t non_blocking = netconn_is_nonblocking(msg->conn);
+        msg->conn->state = NETCONN_CONNECT;
+        SET_NONBLOCKING_CONNECT(msg->conn, non_blocking);
+        if (non_blocking) {
+          msg->err = ERR_INPROGRESS;
+        } else {
+          msg->conn->current_msg = msg;
+          /* sys_sem_signal() is called from do_connected (or err_tcp()),
+          * when the connection is established! */
+          return;
+        }
+      }
+    }
+    break;
+#endif /* LWIP_TCP */
+  default:
+    LWIP_ERROR("Invalid netconn type", 0, do{ msg->err = ERR_VAL; }while(0));
+    break;
+    }
+  }
+  sys_sem_signal(&msg->conn->op_completed);
+}
+
+/**
+ * Connect a pcb contained inside a netconn
+ * Only used for UDP netconns.
+ * Called from netconn_disconnect.
+ *
+ * @param msg the api_msg_msg pointing to the connection to disconnect
+ */
+void
+do_disconnect(struct api_msg_msg *msg)
+{
+#if LWIP_UDP
+  if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_UDP) {
+    udp_disconnect(msg->conn->pcb.udp);
+    msg->err = ERR_OK;
+  } else
+#endif /* LWIP_UDP */
+  {
+    msg->err = ERR_VAL;
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+
+#if LWIP_TCP
+/**
+ * Set a TCP pcb contained in a netconn into listen mode
+ * Called from netconn_listen.
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_listen(struct api_msg_msg *msg)
+{
+  if (ERR_IS_FATAL(msg->conn->last_err)) {
+    msg->err = msg->conn->last_err;
+  } else {
+    msg->err = ERR_CONN;
+    if (msg->conn->pcb.tcp != NULL) {
+      if (msg->conn->type == NETCONN_TCP) {
+        if (msg->conn->state == NETCONN_NONE) {
+#if TCP_LISTEN_BACKLOG
+          struct tcp_pcb* lpcb = tcp_listen_with_backlog(msg->conn->pcb.tcp, msg->msg.lb.backlog);
+#else  /* TCP_LISTEN_BACKLOG */
+          struct tcp_pcb* lpcb = tcp_listen(msg->conn->pcb.tcp);
+#endif /* TCP_LISTEN_BACKLOG */
+          if (lpcb == NULL) {
+            /* in this case, the old pcb is still allocated */
+            msg->err = ERR_MEM;
+          } else {
+            /* delete the recvmbox and allocate the acceptmbox */
+            if (sys_mbox_valid(&msg->conn->recvmbox)) {
+              /** @todo: should we drain the recvmbox here? */
+              sys_mbox_free(&msg->conn->recvmbox);
+              sys_mbox_set_invalid(&msg->conn->recvmbox);
+            }
+            msg->err = ERR_OK;
+            if (!sys_mbox_valid(&msg->conn->acceptmbox)) {
+              msg->err = sys_mbox_new(&msg->conn->acceptmbox, DEFAULT_ACCEPTMBOX_SIZE);
+            }
+            if (msg->err == ERR_OK) {
+              msg->conn->state = NETCONN_LISTEN;
+              msg->conn->pcb.tcp = lpcb;
+              tcp_arg(msg->conn->pcb.tcp, msg->conn);
+              tcp_accept(msg->conn->pcb.tcp, accept_function);
+            } else {
+              /* since the old pcb is already deallocated, free lpcb now */
+              tcp_close(lpcb);
+              msg->conn->pcb.tcp = NULL;
+            }
+          }
+        }
+      }
+    }
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+#endif /* LWIP_TCP */
+
+/**
+ * Send some data on a RAW or UDP pcb contained in a netconn
+ * Called from netconn_send
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_send(struct api_msg_msg *msg)
+{
+  if (ERR_IS_FATAL(msg->conn->last_err)) {
+    msg->err = msg->conn->last_err;
+  } else {
+    msg->err = ERR_CONN;
+    if (msg->conn->pcb.tcp != NULL) {
+      switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+      case NETCONN_RAW:
+        if (ip_addr_isany(&msg->msg.b->addr)) {
+          msg->err = raw_send(msg->conn->pcb.raw, msg->msg.b->p);
+        } else {
+          msg->err = raw_sendto(msg->conn->pcb.raw, msg->msg.b->p, &msg->msg.b->addr);
+        }
+        break;
+#endif
+#if LWIP_UDP
+      case NETCONN_UDP:
+#if LWIP_CHECKSUM_ON_COPY
+        if (ip_addr_isany(&msg->msg.b->addr)) {
+          msg->err = udp_send_chksum(msg->conn->pcb.udp, msg->msg.b->p,
+            msg->msg.b->flags & NETBUF_FLAG_CHKSUM, msg->msg.b->toport_chksum);
+        } else {
+          msg->err = udp_sendto_chksum(msg->conn->pcb.udp, msg->msg.b->p,
+            &msg->msg.b->addr, msg->msg.b->port,
+            msg->msg.b->flags & NETBUF_FLAG_CHKSUM, msg->msg.b->toport_chksum);
+        }
+#else /* LWIP_CHECKSUM_ON_COPY */
+        if (ip_addr_isany(&msg->msg.b->addr)) {
+          msg->err = udp_send(msg->conn->pcb.udp, msg->msg.b->p);
+        } else {
+          msg->err = udp_sendto(msg->conn->pcb.udp, msg->msg.b->p, &msg->msg.b->addr, msg->msg.b->port);
+        }
+#endif /* LWIP_CHECKSUM_ON_COPY */
+        break;
+#endif /* LWIP_UDP */
+      default:
+        break;
+      }
+    }
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+
+#if LWIP_TCP
+/**
+ * Indicate data has been received from a TCP pcb contained in a netconn
+ * Called from netconn_recv
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_recv(struct api_msg_msg *msg)
+{
+  msg->err = ERR_OK;
+  if (msg->conn->pcb.tcp != NULL) {
+    if (msg->conn->type == NETCONN_TCP) {
+#if TCP_LISTEN_BACKLOG
+      if (msg->conn->pcb.tcp->state == LISTEN) {
+        tcp_accepted(msg->conn->pcb.tcp);
+      } else
+#endif /* TCP_LISTEN_BACKLOG */
+      {
+        u32_t remaining = msg->msg.r.len;
+        do {
+          u16_t recved = (remaining > 0xffff) ? 0xffff : (u16_t)remaining;
+          tcp_recved(msg->conn->pcb.tcp, recved);
+          remaining -= recved;
+        }while(remaining != 0);
+      }
+    }
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+
+/**
+ * See if more data needs to be written from a previous call to netconn_write.
+ * Called initially from do_write. If the first call can't send all data
+ * (because of low memory or empty send-buffer), this function is called again
+ * from sent_tcp() or poll_tcp() to send more data. If all data is sent, the
+ * blocking application thread (waiting in netconn_write) is released.
+ *
+ * @param conn netconn (that is currently in state NETCONN_WRITE) to process
+ * @return ERR_OK
+ *         ERR_MEM if LWIP_TCPIP_CORE_LOCKING=1 and sending hasn't yet finished
+ */
+static err_t
+do_writemore(struct netconn *conn)
+{
+  err_t err = ERR_OK;
+  void *dataptr;
+  u16_t len, available;
+  u8_t write_finished = 0;
+  size_t diff;
+  u8_t dontblock = netconn_is_nonblocking(conn) ||
+       (conn->current_msg->msg.w.apiflags & NETCONN_DONTBLOCK);
+  u8_t apiflags = conn->current_msg->msg.w.apiflags;
+
+  LWIP_ASSERT("conn != NULL", conn != NULL);
+  LWIP_ASSERT("conn->state == NETCONN_WRITE", (conn->state == NETCONN_WRITE));
+  LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL);
+  LWIP_ASSERT("conn->pcb.tcp != NULL", conn->pcb.tcp != NULL);
+  LWIP_ASSERT("conn->write_offset < conn->current_msg->msg.w.len",
+    conn->write_offset < conn->current_msg->msg.w.len);
+
+  dataptr = (u8_t*)conn->current_msg->msg.w.dataptr + conn->write_offset;
+  diff = conn->current_msg->msg.w.len - conn->write_offset;
+  if (diff > 0xffffUL) { /* max_u16_t */
+    len = 0xffff;
+#if LWIP_TCPIP_CORE_LOCKING
+    conn->flags |= NETCONN_FLAG_WRITE_DELAYED;
+#endif
+    apiflags |= TCP_WRITE_FLAG_MORE;
+  } else {
+    len = (u16_t)diff;
+  }
+  available = tcp_sndbuf(conn->pcb.tcp);
+  if (available < len) {
+    /* don't try to write more than sendbuf */
+    len = available;
+#if LWIP_TCPIP_CORE_LOCKING
+    conn->flags |= NETCONN_FLAG_WRITE_DELAYED;
+#endif
+    apiflags |= TCP_WRITE_FLAG_MORE;
+  }
+  if (dontblock && (len < conn->current_msg->msg.w.len)) {
+    /* failed to send all data at once -> nonblocking write not possible */
+    err = ERR_MEM;
+  }
+  if (err == ERR_OK) {
+    LWIP_ASSERT("do_writemore: invalid length!", ((conn->write_offset + len) <= conn->current_msg->msg.w.len));
+    err = tcp_write(conn->pcb.tcp, dataptr, len, apiflags);
+  }
+  if (dontblock && (err == ERR_MEM)) {
+    /* nonblocking write failed */
+    write_finished = 1;
+    err = ERR_WOULDBLOCK;
+    /* let poll_tcp check writable space to mark the pcb
+       writable again */
+    conn->flags |= NETCONN_FLAG_CHECK_WRITESPACE;
+    /* let select mark this pcb as non-writable. */
+    API_EVENT(conn, NETCONN_EVT_SENDMINUS, len);
+  } else {
+    /* if OK or memory error, check available space */
+    if (((err == ERR_OK) || (err == ERR_MEM)) &&
+        ((tcp_sndbuf(conn->pcb.tcp) <= TCP_SNDLOWAT) ||
+         (tcp_sndqueuelen(conn->pcb.tcp) >= TCP_SNDQUEUELOWAT))) {
+      /* The queued byte- or pbuf-count exceeds the configured low-water limit,
+         let select mark this pcb as non-writable. */
+      API_EVENT(conn, NETCONN_EVT_SENDMINUS, len);
+    }
+
+    if (err == ERR_OK) {
+      conn->write_offset += len;
+      if (conn->write_offset == conn->current_msg->msg.w.len) {
+        /* everything was written */
+        write_finished = 1;
+        conn->write_offset = 0;
+      }
+      tcp_output(conn->pcb.tcp);
+    } else if (err == ERR_MEM) {
+      /* If ERR_MEM, we wait for sent_tcp or poll_tcp to be called
+         we do NOT return to the application thread, since ERR_MEM is
+         only a temporary error! */
+
+      /* tcp_write returned ERR_MEM, try tcp_output anyway */
+      tcp_output(conn->pcb.tcp);
+
+  #if LWIP_TCPIP_CORE_LOCKING
+      conn->flags |= NETCONN_FLAG_WRITE_DELAYED;
+  #endif
+    } else {
+      /* On errors != ERR_MEM, we don't try writing any more but return
+         the error to the application thread. */
+      write_finished = 1;
+    }
+  }
+
+  if (write_finished) {
+    /* everything was written: set back connection state
+       and back to application task */
+    conn->current_msg->err = err;
+    conn->current_msg = NULL;
+    conn->state = NETCONN_NONE;
+#if LWIP_TCPIP_CORE_LOCKING
+    if ((conn->flags & NETCONN_FLAG_WRITE_DELAYED) != 0)
+#endif
+    {
+      sys_sem_signal(&conn->op_completed);
+    }
+  }
+#if LWIP_TCPIP_CORE_LOCKING
+  else
+    return ERR_MEM;
+#endif
+  return ERR_OK;
+}
+#endif /* LWIP_TCP */
+
+/**
+ * Send some data on a TCP pcb contained in a netconn
+ * Called from netconn_write
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_write(struct api_msg_msg *msg)
+{
+  if (ERR_IS_FATAL(msg->conn->last_err)) {
+    msg->err = msg->conn->last_err;
+  } else {
+    if (msg->conn->type == NETCONN_TCP) {
+#if LWIP_TCP
+      if (msg->conn->state != NETCONN_NONE) {
+        /* netconn is connecting, closing or in blocking write */
+        msg->err = ERR_INPROGRESS;
+      } else if (msg->conn->pcb.tcp != NULL) {
+        msg->conn->state = NETCONN_WRITE;
+        /* set all the variables used by do_writemore */
+        LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL &&
+          msg->conn->write_offset == 0);
+        LWIP_ASSERT("msg->msg.w.len != 0", msg->msg.w.len != 0);
+        msg->conn->current_msg = msg;
+        msg->conn->write_offset = 0;
+#if LWIP_TCPIP_CORE_LOCKING
+        msg->conn->flags &= ~NETCONN_FLAG_WRITE_DELAYED;
+        if (do_writemore(msg->conn) != ERR_OK) {
+          LWIP_ASSERT("state!", msg->conn->state == NETCONN_WRITE);
+          UNLOCK_TCPIP_CORE();
+          sys_arch_sem_wait(&msg->conn->op_completed, 0);
+          LOCK_TCPIP_CORE();
+          LWIP_ASSERT("state!", msg->conn->state == NETCONN_NONE);
+        }
+#else /* LWIP_TCPIP_CORE_LOCKING */
+        do_writemore(msg->conn);
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+        /* for both cases: if do_writemore was called, don't ACK the APIMSG
+           since do_writemore ACKs it! */
+        return;
+      } else {
+        msg->err = ERR_CONN;
+      }
+#else /* LWIP_TCP */
+      msg->err = ERR_VAL;
+#endif /* LWIP_TCP */
+#if (LWIP_UDP || LWIP_RAW)
+    } else {
+      msg->err = ERR_VAL;
+#endif /* (LWIP_UDP || LWIP_RAW) */
+    }
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+
+/**
+ * Return a connection's local or remote address
+ * Called from netconn_getaddr
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_getaddr(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.ip != NULL) {
+    *(msg->msg.ad.ipaddr) = (msg->msg.ad.local ? msg->conn->pcb.ip->local_ip :
+                             msg->conn->pcb.ip->remote_ip);
+
+    msg->err = ERR_OK;
+    switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      if (msg->msg.ad.local) {
+        *(msg->msg.ad.port) = msg->conn->pcb.raw->protocol;
+      } else {
+        /* return an error as connecting is only a helper for upper layers */
+        msg->err = ERR_CONN;
+      }
+      break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+    case NETCONN_UDP:
+      if (msg->msg.ad.local) {
+        *(msg->msg.ad.port) = msg->conn->pcb.udp->local_port;
+      } else {
+        if ((msg->conn->pcb.udp->flags & UDP_FLAGS_CONNECTED) == 0) {
+          msg->err = ERR_CONN;
+        } else {
+          *(msg->msg.ad.port) = msg->conn->pcb.udp->remote_port;
+        }
+      }
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+    case NETCONN_TCP:
+      *(msg->msg.ad.port) = (msg->msg.ad.local?msg->conn->pcb.tcp->local_port:msg->conn->pcb.tcp->remote_port);
+      break;
+#endif /* LWIP_TCP */
+    default:
+      LWIP_ASSERT("invalid netconn_type", 0);
+      break;
+    }
+  } else {
+    msg->err = ERR_CONN;
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+
+/**
+ * Close a TCP pcb contained in a netconn
+ * Called from netconn_close
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_close(struct api_msg_msg *msg)
+{
+#if LWIP_TCP
+  /* @todo: abort running write/connect? */
+  if ((msg->conn->state != NETCONN_NONE) && (msg->conn->state != NETCONN_LISTEN)) {
+    /* this only happens for TCP netconns */
+    LWIP_ASSERT("msg->conn->type == NETCONN_TCP", msg->conn->type == NETCONN_TCP);
+    msg->err = ERR_INPROGRESS;
+  } else if ((msg->conn->pcb.tcp != NULL) && (msg->conn->type == NETCONN_TCP)) {
+    if ((msg->msg.sd.shut != NETCONN_SHUT_RDWR) && (msg->conn->state == NETCONN_LISTEN)) {
+      /* LISTEN doesn't support half shutdown */
+      msg->err = ERR_CONN;
+    } else {
+      if (msg->msg.sd.shut & NETCONN_SHUT_RD) {
+        /* Drain and delete mboxes */
+        netconn_drain(msg->conn);
+      }
+      LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL &&
+        msg->conn->write_offset == 0);
+      msg->conn->state = NETCONN_CLOSE;
+      msg->conn->current_msg = msg;
+      do_close_internal(msg->conn);
+      /* for tcp netconns, do_close_internal ACKs the message */
+      return;
+    }
+  } else
+#endif /* LWIP_TCP */
+  {
+    msg->err = ERR_VAL;
+  }
+  sys_sem_signal(&msg->conn->op_completed);
+}
+
+#if LWIP_IGMP
+/**
+ * Join multicast groups for UDP netconns.
+ * Called from netconn_join_leave_group
+ *
+ * @param msg the api_msg_msg pointing to the connection
+ */
+void
+do_join_leave_group(struct api_msg_msg *msg)
+{ 
+  if (ERR_IS_FATAL(msg->conn->last_err)) {
+    msg->err = msg->conn->last_err;
+  } else {
+    if (msg->conn->pcb.tcp != NULL) {
+      if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_UDP) {
+#if LWIP_UDP
+        if (msg->msg.jl.join_or_leave == NETCONN_JOIN) {
+          msg->err = igmp_joingroup(msg->msg.jl.netif_addr, msg->msg.jl.multiaddr);
+        } else {
+          msg->err = igmp_leavegroup(msg->msg.jl.netif_addr, msg->msg.jl.multiaddr);
+        }
+#endif /* LWIP_UDP */
+#if (LWIP_TCP || LWIP_RAW)
+      } else {
+        msg->err = ERR_VAL;
+#endif /* (LWIP_TCP || LWIP_RAW) */
+      }
+    } else {
+      msg->err = ERR_CONN;
+    }
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+#endif /* LWIP_IGMP */
+
+#if LWIP_DNS
+/**
+ * Callback function that is called when DNS name is resolved
+ * (or on timeout). A waiting application thread is waked up by
+ * signaling the semaphore.
+ */
+static void
+do_dns_found(const char *name, ip_addr_t *ipaddr, void *arg)
+{
+  struct dns_api_msg *msg = (struct dns_api_msg*)arg;
+
+  LWIP_ASSERT("DNS response for wrong host name", strcmp(msg->name, name) == 0);
+  LWIP_UNUSED_ARG(name);
+
+  if (ipaddr == NULL) {
+    /* timeout or memory error */
+    *msg->err = ERR_VAL;
+  } else {
+    /* address was resolved */
+    *msg->err = ERR_OK;
+    *msg->addr = *ipaddr;
+  }
+  /* wake up the application task waiting in netconn_gethostbyname */
+  sys_sem_signal(msg->sem);
+}
+
+/**
+ * Execute a DNS query
+ * Called from netconn_gethostbyname
+ *
+ * @param arg the dns_api_msg pointing to the query
+ */
+void
+do_gethostbyname(void *arg)
+{
+  struct dns_api_msg *msg = (struct dns_api_msg*)arg;
+
+  *msg->err = dns_gethostbyname(msg->name, msg->addr, do_dns_found, msg);
+  if (*msg->err != ERR_INPROGRESS) {
+    /* on error or immediate success, wake up the application
+     * task waiting in netconn_gethostbyname */
+    sys_sem_signal(msg->sem);
+  }
+}
+#endif /* LWIP_DNS */
+
+#endif /* LWIP_NETCONN */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/err.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/err.c
new file mode 100644
index 0000000..92fa8b7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/err.c
@@ -0,0 +1,75 @@
+/**
+ * @file
+ * Error Management module
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/err.h"
+
+#ifdef LWIP_DEBUG
+
+static const char *err_strerr[] = {
+           "Ok.",                    /* ERR_OK          0  */
+           "Out of memory error.",   /* ERR_MEM        -1  */
+           "Buffer error.",          /* ERR_BUF        -2  */
+           "Timeout.",               /* ERR_TIMEOUT    -3  */
+           "Routing problem.",       /* ERR_RTE        -4  */
+           "Operation in progress.", /* ERR_INPROGRESS -5  */
+           "Illegal value.",         /* ERR_VAL        -6  */
+           "Operation would block.", /* ERR_WOULDBLOCK -7  */
+           "Address in use.",        /* ERR_USE        -8  */
+           "Already connected.",     /* ERR_ISCONN     -9  */
+           "Connection aborted.",    /* ERR_ABRT       -10 */
+           "Connection reset.",      /* ERR_RST        -11 */
+           "Connection closed.",     /* ERR_CLSD       -12 */
+           "Not connected.",         /* ERR_CONN       -13 */
+           "Illegal argument.",      /* ERR_ARG        -14 */
+           "Low-level netif error.", /* ERR_IF         -15 */
+};
+
+/**
+ * Convert an lwip internal error to a string representation.
+ *
+ * @param err an lwip internal err_t
+ * @return a string representation for err
+ */
+const char *
+lwip_strerr(err_t err)
+{
+  return err_strerr[-err];
+
+}
+
+#endif /* LWIP_DEBUG */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/netbuf.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/netbuf.c
new file mode 100644
index 0000000..9390c9e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/netbuf.c
@@ -0,0 +1,245 @@
+/**
+ * @file
+ * Network buffer management
+ *
+ */
+ 
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netbuf.h"
+#include "lwip/memp.h"
+
+#include 
+
+/**
+ * Create (allocate) and initialize a new netbuf.
+ * The netbuf doesn't yet contain a packet buffer!
+ *
+ * @return a pointer to a new netbuf
+ *         NULL on lack of memory
+ */
+struct
+netbuf *netbuf_new(void)
+{
+  struct netbuf *buf;
+
+  buf = (struct netbuf *)memp_malloc(MEMP_NETBUF);
+  if (buf != NULL) {
+    buf->p = NULL;
+    buf->ptr = NULL;
+    ip_addr_set_any(&buf->addr);
+    buf->port = 0;
+#if LWIP_NETBUF_RECVINFO || LWIP_CHECKSUM_ON_COPY
+#if LWIP_CHECKSUM_ON_COPY
+    buf->flags = 0;
+#endif /* LWIP_CHECKSUM_ON_COPY */
+    buf->toport_chksum = 0;
+#if LWIP_NETBUF_RECVINFO
+    ip_addr_set_any(&buf->toaddr);
+#endif /* LWIP_NETBUF_RECVINFO */
+#endif /* LWIP_NETBUF_RECVINFO || LWIP_CHECKSUM_ON_COPY */
+    return buf;
+  } else {
+    return NULL;
+  }
+}
+
+/**
+ * Deallocate a netbuf allocated by netbuf_new().
+ *
+ * @param buf pointer to a netbuf allocated by netbuf_new()
+ */
+void
+netbuf_delete(struct netbuf *buf)
+{
+  if (buf != NULL) {
+    if (buf->p != NULL) {
+      pbuf_free(buf->p);
+      buf->p = buf->ptr = NULL;
+    }
+    memp_free(MEMP_NETBUF, buf);
+  }
+}
+
+/**
+ * Allocate memory for a packet buffer for a given netbuf.
+ *
+ * @param buf the netbuf for which to allocate a packet buffer
+ * @param size the size of the packet buffer to allocate
+ * @return pointer to the allocated memory
+ *         NULL if no memory could be allocated
+ */
+void *
+netbuf_alloc(struct netbuf *buf, u16_t size)
+{
+  LWIP_ERROR("netbuf_alloc: invalid buf", (buf != NULL), return NULL;);
+
+  /* Deallocate any previously allocated memory. */
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = pbuf_alloc(PBUF_TRANSPORT, size, PBUF_RAM);
+  if (buf->p == NULL) {
+     return NULL;
+  }
+  LWIP_ASSERT("check that first pbuf can hold size",
+             (buf->p->len >= size));
+  buf->ptr = buf->p;
+  return buf->p->payload;
+}
+
+/**
+ * Free the packet buffer included in a netbuf
+ *
+ * @param buf pointer to the netbuf which contains the packet buffer to free
+ */
+void
+netbuf_free(struct netbuf *buf)
+{
+  LWIP_ERROR("netbuf_free: invalid buf", (buf != NULL), return;);
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = buf->ptr = NULL;
+}
+
+/**
+ * Let a netbuf reference existing (non-volatile) data.
+ *
+ * @param buf netbuf which should reference the data
+ * @param dataptr pointer to the data to reference
+ * @param size size of the data
+ * @return ERR_OK if data is referenced
+ *         ERR_MEM if data couldn't be referenced due to lack of memory
+ */
+err_t
+netbuf_ref(struct netbuf *buf, const void *dataptr, u16_t size)
+{
+  LWIP_ERROR("netbuf_ref: invalid buf", (buf != NULL), return ERR_ARG;);
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF);
+  if (buf->p == NULL) {
+    buf->ptr = NULL;
+    return ERR_MEM;
+  }
+  buf->p->payload = (void*)dataptr;
+  buf->p->len = buf->p->tot_len = size;
+  buf->ptr = buf->p;
+  return ERR_OK;
+}
+
+/**
+ * Chain one netbuf to another (@see pbuf_chain)
+ *
+ * @param head the first netbuf
+ * @param tail netbuf to chain after head, freed by this function, may not be reference after returning
+ */
+void
+netbuf_chain(struct netbuf *head, struct netbuf *tail)
+{
+  LWIP_ERROR("netbuf_ref: invalid head", (head != NULL), return;);
+  LWIP_ERROR("netbuf_chain: invalid tail", (tail != NULL), return;);
+  pbuf_cat(head->p, tail->p);
+  head->ptr = head->p;
+  memp_free(MEMP_NETBUF, tail);
+}
+
+/**
+ * Get the data pointer and length of the data inside a netbuf.
+ *
+ * @param buf netbuf to get the data from
+ * @param dataptr pointer to a void pointer where to store the data pointer
+ * @param len pointer to an u16_t where the length of the data is stored
+ * @return ERR_OK if the information was retreived,
+ *         ERR_BUF on error.
+ */
+err_t
+netbuf_data(struct netbuf *buf, void **dataptr, u16_t *len)
+{
+  LWIP_ERROR("netbuf_data: invalid buf", (buf != NULL), return ERR_ARG;);
+  LWIP_ERROR("netbuf_data: invalid dataptr", (dataptr != NULL), return ERR_ARG;);
+  LWIP_ERROR("netbuf_data: invalid len", (len != NULL), return ERR_ARG;);
+
+  if (buf->ptr == NULL) {
+    return ERR_BUF;
+  }
+  *dataptr = buf->ptr->payload;
+  *len = buf->ptr->len;
+  return ERR_OK;
+}
+
+/**
+ * Move the current data pointer of a packet buffer contained in a netbuf
+ * to the next part.
+ * The packet buffer itself is not modified.
+ *
+ * @param buf the netbuf to modify
+ * @return -1 if there is no next part
+ *         1  if moved to the next part but now there is no next part
+ *         0  if moved to the next part and there are still more parts
+ */
+s8_t
+netbuf_next(struct netbuf *buf)
+{
+  LWIP_ERROR("netbuf_free: invalid buf", (buf != NULL), return -1;);
+  if (buf->ptr->next == NULL) {
+    return -1;
+  }
+  buf->ptr = buf->ptr->next;
+  if (buf->ptr->next == NULL) {
+    return 1;
+  }
+  return 0;
+}
+
+/**
+ * Move the current data pointer of a packet buffer contained in a netbuf
+ * to the beginning of the packet.
+ * The packet buffer itself is not modified.
+ *
+ * @param buf the netbuf to modify
+ */
+void
+netbuf_first(struct netbuf *buf)
+{
+  LWIP_ERROR("netbuf_free: invalid buf", (buf != NULL), return;);
+  buf->ptr = buf->p;
+}
+
+#endif /* LWIP_NETCONN */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/netdb.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/netdb.c
new file mode 100644
index 0000000..a7e4e06
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/netdb.c
@@ -0,0 +1,352 @@
+/**
+ * @file
+ * API functions for name resolving
+ *
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Simon Goldschmidt
+ *
+ */
+
+#include "lwip/netdb.h"
+
+#if LWIP_DNS && LWIP_SOCKET
+
+#include "lwip/err.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/ip_addr.h"
+#include "lwip/api.h"
+#include "lwip/dns.h"
+
+#include 
+#include 
+
+/** helper struct for gethostbyname_r to access the char* buffer */
+struct gethostbyname_r_helper {
+  ip_addr_t *addrs;
+  ip_addr_t addr;
+  char *aliases;
+};
+
+/** h_errno is exported in netdb.h for access by applications. */
+#if LWIP_DNS_API_DECLARE_H_ERRNO
+int h_errno;
+#endif /* LWIP_DNS_API_DECLARE_H_ERRNO */
+
+/** define "hostent" variables storage: 0 if we use a static (but unprotected)
+ * set of variables for lwip_gethostbyname, 1 if we use a local storage */
+#ifndef LWIP_DNS_API_HOSTENT_STORAGE
+#define LWIP_DNS_API_HOSTENT_STORAGE 0
+#endif
+
+/** define "hostent" variables storage */
+#if LWIP_DNS_API_HOSTENT_STORAGE
+#define HOSTENT_STORAGE
+#else
+#define HOSTENT_STORAGE static
+#endif /* LWIP_DNS_API_STATIC_HOSTENT */
+
+/**
+ * Returns an entry containing addresses of address family AF_INET
+ * for the host with name name.
+ * Due to dns_gethostbyname limitations, only one address is returned.
+ *
+ * @param name the hostname to resolve
+ * @return an entry containing addresses of address family AF_INET
+ *         for the host with name name
+ */
+struct hostent*
+lwip_gethostbyname(const char *name)
+{
+  err_t err;
+  ip_addr_t addr;
+
+  /* buffer variables for lwip_gethostbyname() */
+  HOSTENT_STORAGE struct hostent s_hostent;
+  HOSTENT_STORAGE char *s_aliases;
+  HOSTENT_STORAGE ip_addr_t s_hostent_addr;
+  HOSTENT_STORAGE ip_addr_t *s_phostent_addr[2];
+
+  /* query host IP address */
+  err = netconn_gethostbyname(name, &addr);
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(DNS_DEBUG, ("lwip_gethostbyname(%s) failed, err=%d\n", name, err));
+    h_errno = HOST_NOT_FOUND;
+    return NULL;
+  }
+
+  /* fill hostent */
+  s_hostent_addr = addr;
+  s_phostent_addr[0] = &s_hostent_addr;
+  s_phostent_addr[1] = NULL;
+  s_hostent.h_name = (char*)name;
+  s_hostent.h_aliases = &s_aliases;
+  s_hostent.h_addrtype = AF_INET;
+  s_hostent.h_length = sizeof(ip_addr_t);
+  s_hostent.h_addr_list = (char**)&s_phostent_addr;
+
+#if DNS_DEBUG
+  /* dump hostent */
+  LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_name           == %s\n", s_hostent.h_name));
+  LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_aliases        == %p\n", s_hostent.h_aliases));
+  if (s_hostent.h_aliases != NULL) {
+    u8_t idx;
+    for ( idx=0; s_hostent.h_aliases[idx]; idx++) {
+      LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_aliases[%i]->   == %p\n", idx, s_hostent.h_aliases[idx]));
+      LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_aliases[%i]->   == %s\n", idx, s_hostent.h_aliases[idx]));
+    }
+  }
+  LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addrtype       == %d\n", s_hostent.h_addrtype));
+  LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_length         == %d\n", s_hostent.h_length));
+  LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addr_list      == %p\n", s_hostent.h_addr_list));
+  if (s_hostent.h_addr_list != NULL) {
+    u8_t idx;
+    for ( idx=0; s_hostent.h_addr_list[idx]; idx++) {
+      LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addr_list[%i]   == %p\n", idx, s_hostent.h_addr_list[idx]));
+      LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addr_list[%i]-> == %s\n", idx, ip_ntoa((ip_addr_t*)s_hostent.h_addr_list[idx])));
+    }
+  }
+#endif /* DNS_DEBUG */
+
+#if LWIP_DNS_API_HOSTENT_STORAGE
+  /* this function should return the "per-thread" hostent after copy from s_hostent */
+  return sys_thread_hostent(&s_hostent);
+#else
+  return &s_hostent;
+#endif /* LWIP_DNS_API_HOSTENT_STORAGE */
+}
+
+/**
+ * Thread-safe variant of lwip_gethostbyname: instead of using a static
+ * buffer, this function takes buffer and errno pointers as arguments
+ * and uses these for the result.
+ *
+ * @param name the hostname to resolve
+ * @param ret pre-allocated struct where to store the result
+ * @param buf pre-allocated buffer where to store additional data
+ * @param buflen the size of buf
+ * @param result pointer to a hostent pointer that is set to ret on success
+ *               and set to zero on error
+ * @param h_errnop pointer to an int where to store errors (instead of modifying
+ *                 the global h_errno)
+ * @return 0 on success, non-zero on error, additional error information
+ *         is stored in *h_errnop instead of h_errno to be thread-safe
+ */
+int
+lwip_gethostbyname_r(const char *name, struct hostent *ret, char *buf,
+                size_t buflen, struct hostent **result, int *h_errnop)
+{
+  err_t err;
+  struct gethostbyname_r_helper *h;
+  char *hostname;
+  size_t namelen;
+  int lh_errno;
+
+  if (h_errnop == NULL) {
+    /* ensure h_errnop is never NULL */
+    h_errnop = &lh_errno;
+  }
+
+  if (result == NULL) {
+    /* not all arguments given */
+    *h_errnop = EINVAL;
+    return -1;
+  }
+  /* first thing to do: set *result to nothing */
+  *result = NULL;
+  if ((name == NULL) || (ret == NULL) || (buf == 0)) {
+    /* not all arguments given */
+    *h_errnop = EINVAL;
+    return -1;
+  }
+
+  namelen = strlen(name);
+  if (buflen < (sizeof(struct gethostbyname_r_helper) + namelen + 1 + (MEM_ALIGNMENT - 1))) {
+    /* buf can't hold the data needed + a copy of name */
+    *h_errnop = ERANGE;
+    return -1;
+  }
+
+  h = (struct gethostbyname_r_helper*)LWIP_MEM_ALIGN(buf);
+  hostname = ((char*)h) + sizeof(struct gethostbyname_r_helper);
+
+  /* query host IP address */
+  err = netconn_gethostbyname(name, &(h->addr));
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(DNS_DEBUG, ("lwip_gethostbyname(%s) failed, err=%d\n", name, err));
+    *h_errnop = ENSRNOTFOUND;
+    return -1;
+  }
+
+  /* copy the hostname into buf */
+  MEMCPY(hostname, name, namelen);
+  hostname[namelen] = 0;
+
+  /* fill hostent */
+  h->addrs = &(h->addr);
+  h->aliases = NULL;
+  ret->h_name = (char*)hostname;
+  ret->h_aliases = &(h->aliases);
+  ret->h_addrtype = AF_INET;
+  ret->h_length = sizeof(ip_addr_t);
+  ret->h_addr_list = (char**)&(h->addrs);
+
+  /* set result != NULL */
+  *result = ret;
+
+  /* return success */
+  return 0;
+}
+
+/**
+ * Frees one or more addrinfo structures returned by getaddrinfo(), along with
+ * any additional storage associated with those structures. If the ai_next field
+ * of the structure is not null, the entire list of structures is freed.
+ *
+ * @param ai struct addrinfo to free
+ */
+void
+lwip_freeaddrinfo(struct addrinfo *ai)
+{
+  struct addrinfo *next;
+
+  while (ai != NULL) {
+    next = ai->ai_next;
+    memp_free(MEMP_NETDB, ai);
+    ai = next;
+  }
+}
+
+/**
+ * Translates the name of a service location (for example, a host name) and/or
+ * a service name and returns a set of socket addresses and associated
+ * information to be used in creating a socket with which to address the
+ * specified service.
+ * Memory for the result is allocated internally and must be freed by calling
+ * lwip_freeaddrinfo()!
+ *
+ * Due to a limitation in dns_gethostbyname, only the first address of a
+ * host is returned.
+ * Also, service names are not supported (only port numbers)!
+ *
+ * @param nodename descriptive name or address string of the host
+ *                 (may be NULL -> local address)
+ * @param servname port number as string of NULL 
+ * @param hints structure containing input values that set socktype and protocol
+ * @param res pointer to a pointer where to store the result (set to NULL on failure)
+ * @return 0 on success, non-zero on failure
+ */
+int
+lwip_getaddrinfo(const char *nodename, const char *servname,
+       const struct addrinfo *hints, struct addrinfo **res)
+{
+  err_t err;
+  ip_addr_t addr;
+  struct addrinfo *ai;
+  struct sockaddr_in *sa = NULL;
+  int port_nr = 0;
+  size_t total_size;
+  size_t namelen = 0;
+
+  if (res == NULL) {
+    return EAI_FAIL;
+  }
+  *res = NULL;
+  if ((nodename == NULL) && (servname == NULL)) {
+    return EAI_NONAME;
+  }
+
+  if (servname != NULL) {
+    /* service name specified: convert to port number
+     * @todo?: currently, only ASCII integers (port numbers) are supported! */
+    port_nr = atoi(servname);
+    if ((port_nr <= 0) || (port_nr > 0xffff)) {
+      return EAI_SERVICE;
+    }
+  }
+
+  if (nodename != NULL) {
+    /* service location specified, try to resolve */
+    err = netconn_gethostbyname(nodename, &addr);
+    if (err != ERR_OK) {
+      return EAI_FAIL;
+    }
+  } else {
+    /* service location specified, use loopback address */
+    ip_addr_set_loopback(&addr);
+  }
+
+  total_size = sizeof(struct addrinfo) + sizeof(struct sockaddr_in);
+  if (nodename != NULL) {
+    namelen = strlen(nodename);
+    LWIP_ASSERT("namelen is too long", (namelen + 1) <= (mem_size_t)-1);
+    total_size += namelen + 1;
+  }
+  /* If this fails, please report to lwip-devel! :-) */
+  LWIP_ASSERT("total_size <= NETDB_ELEM_SIZE: please report this!",
+    total_size <= NETDB_ELEM_SIZE);
+  ai = (struct addrinfo *)memp_malloc(MEMP_NETDB);
+  if (ai == NULL) {
+    goto memerr;
+  }
+  memset(ai, 0, total_size);
+  sa = (struct sockaddr_in*)((u8_t*)ai + sizeof(struct addrinfo));
+  /* set up sockaddr */
+  inet_addr_from_ipaddr(&sa->sin_addr, &addr);
+  sa->sin_family = AF_INET;
+  sa->sin_len = sizeof(struct sockaddr_in);
+  sa->sin_port = htons((u16_t)port_nr);
+
+  /* set up addrinfo */
+  ai->ai_family = AF_INET;
+  if (hints != NULL) {
+    /* copy socktype & protocol from hints if specified */
+    ai->ai_socktype = hints->ai_socktype;
+    ai->ai_protocol = hints->ai_protocol;
+  }
+  if (nodename != NULL) {
+    /* copy nodename to canonname if specified */
+    ai->ai_canonname = ((char*)ai + sizeof(struct addrinfo) + sizeof(struct sockaddr_in));
+    MEMCPY(ai->ai_canonname, nodename, namelen);
+    ai->ai_canonname[namelen] = 0;
+  }
+  ai->ai_addrlen = sizeof(struct sockaddr_in);
+  ai->ai_addr = (struct sockaddr*)sa;
+
+  *res = ai;
+
+  return 0;
+memerr:
+  if (ai != NULL) {
+    memp_free(MEMP_NETDB, ai);
+  }
+  return EAI_MEMORY;
+}
+
+#endif /* LWIP_DNS && LWIP_SOCKET */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/netifapi.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/netifapi.c
new file mode 100644
index 0000000..43e4720
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/netifapi.c
@@ -0,0 +1,160 @@
+/**
+ * @file
+ * Network Interface Sequential API module
+ *
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netifapi.h"
+#include "lwip/tcpip.h"
+
+/**
+ * Call netif_add() inside the tcpip_thread context.
+ */
+void
+do_netifapi_netif_add(struct netifapi_msg_msg *msg)
+{
+  if (!netif_add( msg->netif,
+                  msg->msg.add.ipaddr,
+                  msg->msg.add.netmask,
+                  msg->msg.add.gw,
+                  msg->msg.add.state,
+                  msg->msg.add.init,
+                  msg->msg.add.input)) {
+    msg->err = ERR_IF;
+  } else {
+    msg->err = ERR_OK;
+  }
+  TCPIP_NETIFAPI_ACK(msg);
+}
+
+/**
+ * Call netif_set_addr() inside the tcpip_thread context.
+ */
+void
+do_netifapi_netif_set_addr(struct netifapi_msg_msg *msg)
+{
+  netif_set_addr( msg->netif,
+                  msg->msg.add.ipaddr,
+                  msg->msg.add.netmask,
+                  msg->msg.add.gw);
+  msg->err = ERR_OK;
+  TCPIP_NETIFAPI_ACK(msg);
+}
+
+/**
+ * Call the "errtfunc" (or the "voidfunc" if "errtfunc" is NULL) inside the
+ * tcpip_thread context.
+ */
+void
+do_netifapi_netif_common(struct netifapi_msg_msg *msg)
+{
+  if (msg->msg.common.errtfunc != NULL) {
+    msg->err = msg->msg.common.errtfunc(msg->netif);
+  } else {
+    msg->err = ERR_OK;
+    msg->msg.common.voidfunc(msg->netif);
+  }
+  TCPIP_NETIFAPI_ACK(msg);
+}
+
+/**
+ * Call netif_add() in a thread-safe way by running that function inside the
+ * tcpip_thread context.
+ *
+ * @note for params @see netif_add()
+ */
+err_t
+netifapi_netif_add(struct netif *netif,
+                   ip_addr_t *ipaddr,
+                   ip_addr_t *netmask,
+                   ip_addr_t *gw,
+                   void *state,
+                   netif_init_fn init,
+                   netif_input_fn input)
+{
+  struct netifapi_msg msg;
+  msg.function = do_netifapi_netif_add;
+  msg.msg.netif = netif;
+  msg.msg.msg.add.ipaddr  = ipaddr;
+  msg.msg.msg.add.netmask = netmask;
+  msg.msg.msg.add.gw      = gw;
+  msg.msg.msg.add.state   = state;
+  msg.msg.msg.add.init    = init;
+  msg.msg.msg.add.input   = input;
+  TCPIP_NETIFAPI(&msg);
+  return msg.msg.err;
+}
+
+/**
+ * Call netif_set_addr() in a thread-safe way by running that function inside the
+ * tcpip_thread context.
+ *
+ * @note for params @see netif_set_addr()
+ */
+err_t
+netifapi_netif_set_addr(struct netif *netif,
+                        ip_addr_t *ipaddr,
+                        ip_addr_t *netmask,
+                        ip_addr_t *gw)
+{
+  struct netifapi_msg msg;
+  msg.function = do_netifapi_netif_set_addr;
+  msg.msg.netif = netif;
+  msg.msg.msg.add.ipaddr  = ipaddr;
+  msg.msg.msg.add.netmask = netmask;
+  msg.msg.msg.add.gw      = gw;
+  TCPIP_NETIFAPI(&msg);
+  return msg.msg.err;
+}
+
+/**
+ * call the "errtfunc" (or the "voidfunc" if "errtfunc" is NULL) in a thread-safe
+ * way by running that function inside the tcpip_thread context.
+ *
+ * @note use only for functions where there is only "netif" parameter.
+ */
+err_t
+netifapi_netif_common(struct netif *netif, netifapi_void_fn voidfunc,
+                       netifapi_errt_fn errtfunc)
+{
+  struct netifapi_msg msg;
+  msg.function = do_netifapi_netif_common;
+  msg.msg.netif = netif;
+  msg.msg.msg.common.voidfunc = voidfunc;
+  msg.msg.msg.common.errtfunc = errtfunc;
+  TCPIP_NETIFAPI(&msg);
+  return msg.msg.err;
+}
+
+#endif /* LWIP_NETIF_API */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/sockets.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/sockets.c
new file mode 100644
index 0000000..0f39bd2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/sockets.c
@@ -0,0 +1,2347 @@
+/**
+ * @file
+ * Sockets BSD-Like API module
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ * Improved by Marc Boucher  and David Haas 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/sockets.h"
+#include "lwip/api.h"
+#include "lwip/sys.h"
+#include "lwip/igmp.h"
+#include "lwip/inet.h"
+#include "lwip/tcp.h"
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/tcpip.h"
+#include "lwip/pbuf.h"
+#if LWIP_CHECKSUM_ON_COPY
+#include "lwip/inet_chksum.h"
+#endif
+
+#include 
+
+#define NUM_SOCKETS MEMP_NUM_NETCONN
+
+/** Contains all internal pointers and states used for a socket */
+struct lwip_sock {
+  /** sockets currently are built on netconns, each socket has one netconn */
+  struct netconn *conn;
+  /** data that was left from the previous read */
+  void *lastdata;
+  /** offset in the data that was left from the previous read */
+  u16_t lastoffset;
+  /** number of times data was received, set by event_callback(),
+      tested by the receive and select functions */
+  s16_t rcvevent;
+  /** number of times data was ACKed (free send buffer), set by event_callback(),
+      tested by select */
+  u16_t sendevent;
+  /** error happened for this socket, set by event_callback(), tested by select */
+  u16_t errevent; 
+  /** last error that occurred on this socket */
+  int err;
+  /** counter of how many threads are waiting for this socket using select */
+  int select_waiting;
+};
+
+/** Description for a task waiting in select */
+struct lwip_select_cb {
+  /** Pointer to the next waiting task */
+  struct lwip_select_cb *next;
+  /** Pointer to the previous waiting task */
+  struct lwip_select_cb *prev;
+  /** readset passed to select */
+  fd_set *readset;
+  /** writeset passed to select */
+  fd_set *writeset;
+  /** unimplemented: exceptset passed to select */
+  fd_set *exceptset;
+  /** don't signal the same semaphore twice: set to 1 when signalled */
+  int sem_signalled;
+  /** semaphore to wake up a task waiting for select */
+  sys_sem_t sem;
+};
+
+/** This struct is used to pass data to the set/getsockopt_internal
+ * functions running in tcpip_thread context (only a void* is allowed) */
+struct lwip_setgetsockopt_data {
+  /** socket struct for which to change options */
+  struct lwip_sock *sock;
+#ifdef LWIP_DEBUG
+  /** socket index for which to change options */
+  int s;
+#endif /* LWIP_DEBUG */
+  /** level of the option to process */
+  int level;
+  /** name of the option to process */
+  int optname;
+  /** set: value to set the option to
+    * get: value of the option is stored here */
+  void *optval;
+  /** size of *optval */
+  socklen_t *optlen;
+  /** if an error occures, it is temporarily stored here */
+  err_t err;
+};
+
+/** The global array of available sockets */
+static struct lwip_sock sockets[NUM_SOCKETS];
+/** The global list of tasks waiting for select */
+static struct lwip_select_cb *select_cb_list;
+/** This counter is increased from lwip_select when the list is chagned
+    and checked in event_callback to see if it has changed. */
+static volatile int select_cb_ctr;
+
+/** Table to quickly map an lwIP error (err_t) to a socket error
+  * by using -err as an index */
+static const int err_to_errno_table[] = {
+  0,             /* ERR_OK          0      No error, everything OK. */
+  ENOMEM,        /* ERR_MEM        -1      Out of memory error.     */
+  ENOBUFS,       /* ERR_BUF        -2      Buffer error.            */
+  EWOULDBLOCK,   /* ERR_TIMEOUT    -3      Timeout                  */
+  EHOSTUNREACH,  /* ERR_RTE        -4      Routing problem.         */
+  EINPROGRESS,   /* ERR_INPROGRESS -5      Operation in progress    */
+  EINVAL,        /* ERR_VAL        -6      Illegal value.           */
+  EWOULDBLOCK,   /* ERR_WOULDBLOCK -7      Operation would block.   */
+  EADDRINUSE,    /* ERR_USE        -8      Address in use.          */
+  EALREADY,      /* ERR_ISCONN     -9      Already connected.       */
+  ECONNABORTED,  /* ERR_ABRT       -10     Connection aborted.      */
+  ECONNRESET,    /* ERR_RST        -11     Connection reset.        */
+  ENOTCONN,      /* ERR_CLSD       -12     Connection closed.       */
+  ENOTCONN,      /* ERR_CONN       -13     Not connected.           */
+  EIO,           /* ERR_ARG        -14     Illegal argument.        */
+  -1,            /* ERR_IF         -15     Low-level netif error    */
+};
+
+#define ERR_TO_ERRNO_TABLE_SIZE \
+  (sizeof(err_to_errno_table)/sizeof(err_to_errno_table[0]))
+
+#define err_to_errno(err) \
+  ((unsigned)(-(err)) < ERR_TO_ERRNO_TABLE_SIZE ? \
+    err_to_errno_table[-(err)] : EIO)
+
+#ifdef ERRNO
+#ifndef set_errno
+#define set_errno(err) errno = (err)
+#endif
+#else /* ERRNO */
+#define set_errno(err)
+#endif /* ERRNO */
+
+#define sock_set_errno(sk, e) do { \
+  sk->err = (e); \
+  set_errno(sk->err); \
+} while (0)
+
+/* Forward delcaration of some functions */
+static void event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len);
+static void lwip_getsockopt_internal(void *arg);
+static void lwip_setsockopt_internal(void *arg);
+
+/**
+ * Initialize this module. This function has to be called before any other
+ * functions in this module!
+ */
+void
+lwip_socket_init(void)
+{
+}
+
+/**
+ * Map a externally used socket index to the internal socket representation.
+ *
+ * @param s externally used socket index
+ * @return struct lwip_sock for the socket or NULL if not found
+ */
+static struct lwip_sock *
+get_socket(int s)
+{
+  struct lwip_sock *sock;
+
+  if ((s < 0) || (s >= NUM_SOCKETS)) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): invalid\n", s));
+    set_errno(EBADF);
+    return NULL;
+  }
+
+  sock = &sockets[s];
+
+  if (!sock->conn) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): not active\n", s));
+    set_errno(EBADF);
+    return NULL;
+  }
+
+  return sock;
+}
+
+/**
+ * Same as get_socket but doesn't set errno
+ *
+ * @param s externally used socket index
+ * @return struct lwip_sock for the socket or NULL if not found
+ */
+static struct lwip_sock *
+tryget_socket(int s)
+{
+  if ((s < 0) || (s >= NUM_SOCKETS)) {
+    return NULL;
+  }
+  if (!sockets[s].conn) {
+    return NULL;
+  }
+  return &sockets[s];
+}
+
+/**
+ * Allocate a new socket for a given netconn.
+ *
+ * @param newconn the netconn for which to allocate a socket
+ * @param accepted 1 if socket has been created by accept(),
+ *                 0 if socket has been created by socket()
+ * @return the index of the new socket; -1 on error
+ */
+static int
+alloc_socket(struct netconn *newconn, int accepted)
+{
+  int i;
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  /* allocate a new socket identifier */
+  for (i = 0; i < NUM_SOCKETS; ++i) {
+    /* Protect socket array */
+    SYS_ARCH_PROTECT(lev);
+    if (!sockets[i].conn) {
+      sockets[i].conn       = newconn;
+      /* The socket is not yet known to anyone, so no need to protect
+         after having marked it as used. */
+      SYS_ARCH_UNPROTECT(lev);
+      sockets[i].lastdata   = NULL;
+      sockets[i].lastoffset = 0;
+      sockets[i].rcvevent   = 0;
+      /* TCP sendbuf is empty, but the socket is not yet writable until connected
+       * (unless it has been created by accept()). */
+      sockets[i].sendevent  = (newconn->type == NETCONN_TCP ? (accepted != 0) : 1);
+      sockets[i].errevent   = 0;
+      sockets[i].err        = 0;
+      sockets[i].select_waiting = 0;
+      return i;
+    }
+    SYS_ARCH_UNPROTECT(lev);
+  }
+  return -1;
+}
+
+/** Free a socket. The socket's netconn must have been
+ * delete before!
+ *
+ * @param sock the socket to free
+ * @param is_tcp != 0 for TCP sockets, used to free lastdata
+ */
+static void
+free_socket(struct lwip_sock *sock, int is_tcp)
+{
+  void *lastdata;
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  lastdata         = sock->lastdata;
+  sock->lastdata   = NULL;
+  sock->lastoffset = 0;
+  sock->err        = 0;
+
+  /* Protect socket array */
+  SYS_ARCH_PROTECT(lev);
+  sock->conn       = NULL;
+  SYS_ARCH_UNPROTECT(lev);
+  /* don't use 'sock' after this line, as another task might have allocated it */
+
+  if (lastdata != NULL) {
+    if (is_tcp) {
+      pbuf_free((struct pbuf *)lastdata);
+    } else {
+      netbuf_delete((struct netbuf *)lastdata);
+    }
+  }
+}
+
+/* Below this, the well-known socket functions are implemented.
+ * Use google.com or opengroup.org to get a good description :-)
+ *
+ * Exceptions are documented!
+ */
+
+int
+lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen)
+{
+  struct lwip_sock *sock, *nsock;
+  struct netconn *newconn;
+  ip_addr_t naddr;
+  u16_t port;
+  int newsock;
+  struct sockaddr_in sin;
+  err_t err;
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d)...\n", s));
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+
+  if (netconn_is_nonblocking(sock->conn) && (sock->rcvevent <= 0)) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d): returning EWOULDBLOCK\n", s));
+    sock_set_errno(sock, EWOULDBLOCK);
+    return -1;
+  }
+
+  /* wait for a new connection */
+  err = netconn_accept(sock->conn, &newconn);
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d): netconn_acept failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+  LWIP_ASSERT("newconn != NULL", newconn != NULL);
+  /* Prevent automatic window updates, we do this on our own! */
+  netconn_set_noautorecved(newconn, 1);
+
+  /* get the IP address and port of the remote host */
+  err = netconn_peer(newconn, &naddr, &port);
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d): netconn_peer failed, err=%d\n", s, err));
+    netconn_delete(newconn);
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  /* Note that POSIX only requires us to check addr is non-NULL. addrlen must
+   * not be NULL if addr is valid.
+   */
+  if (NULL != addr) {
+    LWIP_ASSERT("addr valid but addrlen NULL", addrlen != NULL);
+    memset(&sin, 0, sizeof(sin));
+    sin.sin_len = sizeof(sin);
+    sin.sin_family = AF_INET;
+    sin.sin_port = htons(port);
+    inet_addr_from_ipaddr(&sin.sin_addr, &naddr);
+
+    if (*addrlen > sizeof(sin))
+      *addrlen = sizeof(sin);
+
+    MEMCPY(addr, &sin, *addrlen);
+  }
+
+  newsock = alloc_socket(newconn, 1);
+  if (newsock == -1) {
+    netconn_delete(newconn);
+    sock_set_errno(sock, ENFILE);
+    return -1;
+  }
+  LWIP_ASSERT("invalid socket index", (newsock >= 0) && (newsock < NUM_SOCKETS));
+  LWIP_ASSERT("newconn->callback == event_callback", newconn->callback == event_callback);
+  nsock = &sockets[newsock];
+
+  /* See event_callback: If data comes in right away after an accept, even
+   * though the server task might not have created a new socket yet.
+   * In that case, newconn->socket is counted down (newconn->socket--),
+   * so nsock->rcvevent is >= 1 here!
+   */
+  SYS_ARCH_PROTECT(lev);
+  nsock->rcvevent += (s16_t)(-1 - newconn->socket);
+  newconn->socket = newsock;
+  SYS_ARCH_UNPROTECT(lev);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d addr=", s, newsock));
+  ip_addr_debug_print(SOCKETS_DEBUG, &naddr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F"\n", port));
+
+  sock_set_errno(sock, 0);
+  return newsock;
+}
+
+int
+lwip_bind(int s, const struct sockaddr *name, socklen_t namelen)
+{
+  struct lwip_sock *sock;
+  ip_addr_t local_addr;
+  u16_t local_port;
+  err_t err;
+  const struct sockaddr_in *name_in;
+
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+
+  /* check size, familiy and alignment of 'name' */
+  LWIP_ERROR("lwip_bind: invalid address", ((namelen == sizeof(struct sockaddr_in)) &&
+             ((name->sa_family) == AF_INET) && ((((mem_ptr_t)name) % 4) == 0)),
+             sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;);
+  name_in = (const struct sockaddr_in *)(void*)name;
+
+  inet_addr_to_ipaddr(&local_addr, &name_in->sin_addr);
+  local_port = name_in->sin_port;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d, addr=", s));
+  ip_addr_debug_print(SOCKETS_DEBUG, &local_addr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", ntohs(local_port)));
+
+  err = netconn_bind(sock->conn, &local_addr, ntohs(local_port));
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) succeeded\n", s));
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_close(int s)
+{
+  struct lwip_sock *sock;
+  int is_tcp = 0;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_close(%d)\n", s));
+
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+
+  if(sock->conn != NULL) {
+    is_tcp = netconn_type(sock->conn) == NETCONN_TCP;
+  } else {
+    LWIP_ASSERT("sock->lastdata == NULL", sock->lastdata == NULL);
+  }
+
+  netconn_delete(sock->conn);
+
+  free_socket(sock, is_tcp);
+  set_errno(0);
+  return 0;
+}
+
+int
+lwip_connect(int s, const struct sockaddr *name, socklen_t namelen)
+{
+  struct lwip_sock *sock;
+  err_t err;
+  const struct sockaddr_in *name_in;
+
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+
+  /* check size, familiy and alignment of 'name' */
+  LWIP_ERROR("lwip_connect: invalid address", ((namelen == sizeof(struct sockaddr_in)) &&
+             ((name->sa_family) == AF_INET) && ((((mem_ptr_t)name) % 4) == 0)),
+             sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;);
+  name_in = (const struct sockaddr_in *)(void*)name;
+
+  if (name_in->sin_family == AF_UNSPEC) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, AF_UNSPEC)\n", s));
+    err = netconn_disconnect(sock->conn);
+  } else {
+    ip_addr_t remote_addr;
+    u16_t remote_port;
+
+    inet_addr_to_ipaddr(&remote_addr, &name_in->sin_addr);
+    remote_port = name_in->sin_port;
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, addr=", s));
+    ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr);
+    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", ntohs(remote_port)));
+
+    err = netconn_connect(sock->conn, &remote_addr, ntohs(remote_port));
+  }
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) succeeded\n", s));
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+/**
+ * Set a socket into listen mode.
+ * The socket may not have been used for another connection previously.
+ *
+ * @param s the socket to set to listening mode
+ * @param backlog (ATTENTION: needs TCP_LISTEN_BACKLOG=1)
+ * @return 0 on success, non-zero on failure
+ */
+int
+lwip_listen(int s, int backlog)
+{
+  struct lwip_sock *sock;
+  err_t err;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d, backlog=%d)\n", s, backlog));
+
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+
+  /* limit the "backlog" parameter to fit in an u8_t */
+  backlog = LWIP_MIN(LWIP_MAX(backlog, 0), 0xff);
+
+  err = netconn_listen_with_backlog(sock->conn, (u8_t)backlog);
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d) failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_recvfrom(int s, void *mem, size_t len, int flags,
+        struct sockaddr *from, socklen_t *fromlen)
+{
+  struct lwip_sock *sock;
+  void             *buf = NULL;
+  struct pbuf      *p;
+  u16_t            buflen, copylen;
+  int              off = 0;
+  ip_addr_t        *addr;
+  u16_t            port;
+  u8_t             done = 0;
+  err_t            err;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d, %p, %"SZT_F", 0x%x, ..)\n", s, mem, len, flags));
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+
+  do {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: top while sock->lastdata=%p\n", sock->lastdata));
+    /* Check if there is data left from the last recv operation. */
+    if (sock->lastdata) {
+      buf = sock->lastdata;
+    } else {
+      /* If this is non-blocking call, then check first */
+      if (((flags & MSG_DONTWAIT) || netconn_is_nonblocking(sock->conn)) && 
+          (sock->rcvevent <= 0)) {
+        if (off > 0) {
+          /* update receive window */
+          netconn_recved(sock->conn, (u32_t)off);
+          /* already received data, return that */
+          sock_set_errno(sock, 0);
+          return off;
+        }
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): returning EWOULDBLOCK\n", s));
+        sock_set_errno(sock, EWOULDBLOCK);
+        return -1;
+      }
+
+      /* No data was left from the previous operation, so we try to get
+         some from the network. */
+      if (netconn_type(sock->conn) == NETCONN_TCP) {
+        err = netconn_recv_tcp_pbuf(sock->conn, (struct pbuf **)&buf);
+      } else {
+        err = netconn_recv(sock->conn, (struct netbuf **)&buf);
+      }
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: netconn_recv err=%d, netbuf=%p\n",
+        err, buf));
+
+      if (err != ERR_OK) {
+        if (off > 0) {
+          /* update receive window */
+          netconn_recved(sock->conn, (u32_t)off);
+          /* already received data, return that */
+          sock_set_errno(sock, 0);
+          return off;
+        }
+        /* We should really do some error checking here. */
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): buf == NULL, error is \"%s\"!\n",
+          s, lwip_strerr(err)));
+        sock_set_errno(sock, err_to_errno(err));
+        if (err == ERR_CLSD) {
+          return 0;
+        } else {
+          return -1;
+        }
+      }
+      LWIP_ASSERT("buf != NULL", buf != NULL);
+      sock->lastdata = buf;
+    }
+
+    if (netconn_type(sock->conn) == NETCONN_TCP) {
+      p = (struct pbuf *)buf;
+    } else {
+      p = ((struct netbuf *)buf)->p;
+    }
+    buflen = p->tot_len;
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: buflen=%"U16_F" len=%"SZT_F" off=%d sock->lastoffset=%"U16_F"\n",
+      buflen, len, off, sock->lastoffset));
+
+    buflen -= sock->lastoffset;
+
+    if (len > buflen) {
+      copylen = buflen;
+    } else {
+      copylen = (u16_t)len;
+    }
+
+    /* copy the contents of the received buffer into
+    the supplied memory pointer mem */
+    pbuf_copy_partial(p, (u8_t*)mem + off, copylen, sock->lastoffset);
+
+    off += copylen;
+
+    if (netconn_type(sock->conn) == NETCONN_TCP) {
+      LWIP_ASSERT("invalid copylen, len would underflow", len >= copylen);
+      len -= copylen;
+      if ( (len <= 0) || 
+           (p->flags & PBUF_FLAG_PUSH) || 
+           (sock->rcvevent <= 0) || 
+           ((flags & MSG_PEEK)!=0)) {
+        done = 1;
+      }
+    } else {
+      done = 1;
+    }
+
+    /* Check to see from where the data was.*/
+    if (done) {
+      ip_addr_t fromaddr;
+      if (from && fromlen) {
+        struct sockaddr_in sin;
+
+        if (netconn_type(sock->conn) == NETCONN_TCP) {
+          addr = &fromaddr;
+          netconn_getaddr(sock->conn, addr, &port, 0);
+        } else {
+          addr = netbuf_fromaddr((struct netbuf *)buf);
+          port = netbuf_fromport((struct netbuf *)buf);
+        }
+
+        memset(&sin, 0, sizeof(sin));
+        sin.sin_len = sizeof(sin);
+        sin.sin_family = AF_INET;
+        sin.sin_port = htons(port);
+        inet_addr_from_ipaddr(&sin.sin_addr, addr);
+
+        if (*fromlen > sizeof(sin)) {
+          *fromlen = sizeof(sin);
+        }
+
+        MEMCPY(from, &sin, *fromlen);
+
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s));
+        ip_addr_debug_print(SOCKETS_DEBUG, addr);
+        LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F" len=%d\n", port, off));
+      } else {
+#if SOCKETS_DEBUG
+        if (netconn_type(sock->conn) == NETCONN_TCP) {
+          addr = &fromaddr;
+          netconn_getaddr(sock->conn, addr, &port, 0);
+        } else {
+          addr = netbuf_fromaddr((struct netbuf *)buf);
+          port = netbuf_fromport((struct netbuf *)buf);
+        }
+
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s));
+        ip_addr_debug_print(SOCKETS_DEBUG, addr);
+        LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F" len=%d\n", port, off));
+#endif /*  SOCKETS_DEBUG */
+      }
+    }
+
+    /* If we don't peek the incoming message... */
+    if ((flags & MSG_PEEK) == 0) {
+      /* If this is a TCP socket, check if there is data left in the
+         buffer. If so, it should be saved in the sock structure for next
+         time around. */
+      if ((netconn_type(sock->conn) == NETCONN_TCP) && (buflen - copylen > 0)) {
+        sock->lastdata = buf;
+        sock->lastoffset += copylen;
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: lastdata now netbuf=%p\n", buf));
+      } else {
+        sock->lastdata = NULL;
+        sock->lastoffset = 0;
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: deleting netbuf=%p\n", buf));
+        if (netconn_type(sock->conn) == NETCONN_TCP) {
+          pbuf_free((struct pbuf *)buf);
+        } else {
+          netbuf_delete((struct netbuf *)buf);
+        }
+      }
+    }
+  } while (!done);
+
+  if (off > 0) {
+    /* update receive window */
+    netconn_recved(sock->conn, (u32_t)off);
+  }
+  sock_set_errno(sock, 0);
+  return off;
+}
+
+int
+lwip_read(int s, void *mem, size_t len)
+{
+  return lwip_recvfrom(s, mem, len, 0, NULL, NULL);
+}
+
+int
+lwip_recv(int s, void *mem, size_t len, int flags)
+{
+  return lwip_recvfrom(s, mem, len, flags, NULL, NULL);
+}
+
+int
+lwip_send(int s, const void *data, size_t size, int flags)
+{
+  struct lwip_sock *sock;
+  err_t err;
+  u8_t write_flags;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d, data=%p, size=%"SZT_F", flags=0x%x)\n",
+                              s, data, size, flags));
+
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+
+  if (sock->conn->type != NETCONN_TCP) {
+#if (LWIP_UDP || LWIP_RAW)
+    return lwip_sendto(s, data, size, flags, NULL, 0);
+#else /* (LWIP_UDP || LWIP_RAW) */
+    sock_set_errno(sock, err_to_errno(ERR_ARG));
+    return -1;
+#endif /* (LWIP_UDP || LWIP_RAW) */
+  }
+
+  if ((flags & MSG_DONTWAIT) || netconn_is_nonblocking(sock->conn)) {
+    if ((size > TCP_SND_BUF) || ((size / TCP_MSS) > TCP_SND_QUEUELEN)) {
+      /* too much data to ever send nonblocking! */
+      sock_set_errno(sock, EMSGSIZE);
+      return -1;
+    }
+  }
+
+  write_flags = NETCONN_COPY |
+    ((flags & MSG_MORE)     ? NETCONN_MORE      : 0) |
+    ((flags & MSG_DONTWAIT) ? NETCONN_DONTBLOCK : 0);
+  err = netconn_write(sock->conn, data, size, write_flags);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) err=%d size=%"SZT_F"\n", s, err, size));
+  sock_set_errno(sock, err_to_errno(err));
+  return (err == ERR_OK ? (int)size : -1);
+}
+
+int
+lwip_sendto(int s, const void *data, size_t size, int flags,
+       const struct sockaddr *to, socklen_t tolen)
+{
+  struct lwip_sock *sock;
+  err_t err;
+  u16_t short_size;
+  const struct sockaddr_in *to_in;
+  u16_t remote_port;
+#if !LWIP_TCPIP_CORE_LOCKING
+  struct netbuf buf;
+#endif
+
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+
+  if (sock->conn->type == NETCONN_TCP) {
+#if LWIP_TCP
+    return lwip_send(s, data, size, flags);
+#else /* LWIP_TCP */
+    LWIP_UNUSED_ARG(flags);
+    sock_set_errno(sock, err_to_errno(ERR_ARG));
+    return -1;
+#endif /* LWIP_TCP */
+  }
+
+  /* @todo: split into multiple sendto's? */
+  LWIP_ASSERT("lwip_sendto: size must fit in u16_t", size <= 0xffff);
+  short_size = (u16_t)size;
+  LWIP_ERROR("lwip_sendto: invalid address", (((to == NULL) && (tolen == 0)) ||
+             ((tolen == sizeof(struct sockaddr_in)) &&
+             ((to->sa_family) == AF_INET) && ((((mem_ptr_t)to) % 4) == 0))),
+             sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;);
+  to_in = (const struct sockaddr_in *)(void*)to;
+
+#if LWIP_TCPIP_CORE_LOCKING
+  /* Should only be consider like a sample or a simple way to experiment this option (no check of "to" field...) */
+  {
+    struct pbuf* p;
+    ip_addr_t *remote_addr;
+
+#if LWIP_NETIF_TX_SINGLE_PBUF
+    p = pbuf_alloc(PBUF_TRANSPORT, short_size, PBUF_RAM);
+    if (p != NULL) {
+#if LWIP_CHECKSUM_ON_COPY
+      u16_t chksum = 0;
+      if (sock->conn->type != NETCONN_RAW) {
+        chksum = LWIP_CHKSUM_COPY(p->payload, data, short_size);
+      } else
+#endif /* LWIP_CHECKSUM_ON_COPY */
+      MEMCPY(p->payload, data, size);
+#else /* LWIP_NETIF_TX_SINGLE_PBUF */
+    p = pbuf_alloc(PBUF_TRANSPORT, short_size, PBUF_REF);
+    if (p != NULL) {
+      p->payload = (void*)data;
+#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
+
+      if (to_in != NULL) {
+        inet_addr_to_ipaddr_p(remote_addr, &to_in->sin_addr);
+        remote_port = ntohs(to_in->sin_port);
+      } else {
+        remote_addr = &sock->conn->pcb.raw->remote_ip;
+        if (sock->conn->type == NETCONN_RAW) {
+          remote_port = 0;
+        } else {
+          remote_port = sock->conn->pcb.udp->remote_port;
+        }
+      }
+
+      LOCK_TCPIP_CORE();
+      if (sock->conn->type == NETCONN_RAW) {
+        err = sock->conn->last_err = raw_sendto(sock->conn->pcb.raw, p, remote_addr);
+      } else {
+#if LWIP_UDP
+#if LWIP_CHECKSUM_ON_COPY && LWIP_NETIF_TX_SINGLE_PBUF
+        err = sock->conn->last_err = udp_sendto_chksum(sock->conn->pcb.udp, p,
+          remote_addr, remote_port, 1, chksum);
+#else /* LWIP_CHECKSUM_ON_COPY && LWIP_NETIF_TX_SINGLE_PBUF */
+        err = sock->conn->last_err = udp_sendto(sock->conn->pcb.udp, p,
+          remote_addr, remote_port);
+#endif /* LWIP_CHECKSUM_ON_COPY && LWIP_NETIF_TX_SINGLE_PBUF */
+#else /* LWIP_UDP */
+        err = ERR_ARG;
+#endif /* LWIP_UDP */
+      }
+      UNLOCK_TCPIP_CORE();
+      
+      pbuf_free(p);
+    } else {
+      err = ERR_MEM;
+    }
+  }
+#else /* LWIP_TCPIP_CORE_LOCKING */
+  /* initialize a buffer */
+  buf.p = buf.ptr = NULL;
+#if LWIP_CHECKSUM_ON_COPY
+  buf.flags = 0;
+#endif /* LWIP_CHECKSUM_ON_COPY */
+  if (to) {
+    inet_addr_to_ipaddr(&buf.addr, &to_in->sin_addr);
+    remote_port           = ntohs(to_in->sin_port);
+    netbuf_fromport(&buf) = remote_port;
+  } else {
+    remote_port           = 0;
+    ip_addr_set_any(&buf.addr);
+    netbuf_fromport(&buf) = 0;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_sendto(%d, data=%p, short_size=%"U16_F", flags=0x%x to=",
+              s, data, short_size, flags));
+  ip_addr_debug_print(SOCKETS_DEBUG, &buf.addr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F"\n", remote_port));
+
+  /* make the buffer point to the data that should be sent */
+#if LWIP_NETIF_TX_SINGLE_PBUF
+  /* Allocate a new netbuf and copy the data into it. */
+  if (netbuf_alloc(&buf, short_size) == NULL) {
+    err = ERR_MEM;
+  } else {
+#if LWIP_CHECKSUM_ON_COPY
+    if (sock->conn->type != NETCONN_RAW) {
+      u16_t chksum = LWIP_CHKSUM_COPY(buf.p->payload, data, short_size);
+      netbuf_set_chksum(&buf, chksum);
+      err = ERR_OK;
+    } else
+#endif /* LWIP_CHECKSUM_ON_COPY */
+    {
+      err = netbuf_take(&buf, data, short_size);
+    }
+  }
+#else /* LWIP_NETIF_TX_SINGLE_PBUF */
+  err = netbuf_ref(&buf, data, short_size);
+#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
+  if (err == ERR_OK) {
+    /* send the data */
+    err = netconn_send(sock->conn, &buf);
+  }
+
+  /* deallocated the buffer */
+  netbuf_free(&buf);
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+  sock_set_errno(sock, err_to_errno(err));
+  return (err == ERR_OK ? short_size : -1);
+}
+
+int
+lwip_socket(int domain, int type, int protocol)
+{
+  struct netconn *conn;
+  int i;
+
+  LWIP_UNUSED_ARG(domain);
+
+  /* create a netconn */
+  switch (type) {
+  case SOCK_RAW:
+    conn = netconn_new_with_proto_and_callback(NETCONN_RAW, (u8_t)protocol, event_callback);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_RAW, %d) = ",
+                                 domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+    break;
+  case SOCK_DGRAM:
+    conn = netconn_new_with_callback( (protocol == IPPROTO_UDPLITE) ?
+                 NETCONN_UDPLITE : NETCONN_UDP, event_callback);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_DGRAM, %d) = ",
+                                 domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+    break;
+  case SOCK_STREAM:
+    conn = netconn_new_with_callback(NETCONN_TCP, event_callback);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_STREAM, %d) = ",
+                                 domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+    if (conn != NULL) {
+      /* Prevent automatic window updates, we do this on our own! */
+      netconn_set_noautorecved(conn, 1);
+    }
+    break;
+  default:
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%d, %d/UNKNOWN, %d) = -1\n",
+                                 domain, type, protocol));
+    set_errno(EINVAL);
+    return -1;
+  }
+
+  if (!conn) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("-1 / ENOBUFS (could not create netconn)\n"));
+    set_errno(ENOBUFS);
+    return -1;
+  }
+
+  i = alloc_socket(conn, 0);
+
+  if (i == -1) {
+    netconn_delete(conn);
+    set_errno(ENFILE);
+    return -1;
+  }
+  conn->socket = i;
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("%d\n", i));
+  set_errno(0);
+  return i;
+}
+
+int
+lwip_write(int s, const void *data, size_t size)
+{
+  return lwip_send(s, data, size, 0);
+}
+
+/**
+ * Go through the readset and writeset lists and see which socket of the sockets
+ * set in the sets has events. On return, readset, writeset and exceptset have
+ * the sockets enabled that had events.
+ *
+ * exceptset is not used for now!!!
+ *
+ * @param maxfdp1 the highest socket index in the sets
+ * @param readset_in:    set of sockets to check for read events
+ * @param writeset_in:   set of sockets to check for write events
+ * @param exceptset_in:  set of sockets to check for error events
+ * @param readset_out:   set of sockets that had read events
+ * @param writeset_out:  set of sockets that had write events
+ * @param exceptset_out: set os sockets that had error events
+ * @return number of sockets that had events (read/write/exception) (>= 0)
+ */
+static int
+lwip_selscan(int maxfdp1, fd_set *readset_in, fd_set *writeset_in, fd_set *exceptset_in,
+             fd_set *readset_out, fd_set *writeset_out, fd_set *exceptset_out)
+{
+  int i, nready = 0;
+  fd_set lreadset, lwriteset, lexceptset;
+  struct lwip_sock *sock;
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  FD_ZERO(&lreadset);
+  FD_ZERO(&lwriteset);
+  FD_ZERO(&lexceptset);
+
+  /* Go through each socket in each list to count number of sockets which
+     currently match */
+  for(i = 0; i < maxfdp1; i++) {
+    void* lastdata = NULL;
+    s16_t rcvevent = 0;
+    u16_t sendevent = 0;
+    u16_t errevent = 0;
+    /* First get the socket's status (protected)... */
+    SYS_ARCH_PROTECT(lev);
+    sock = tryget_socket(i);
+    if (sock != NULL) {
+      lastdata = sock->lastdata;
+      rcvevent = sock->rcvevent;
+      sendevent = sock->sendevent;
+      errevent = sock->errevent;
+    }
+    SYS_ARCH_UNPROTECT(lev);
+    /* ... then examine it: */
+    /* See if netconn of this socket is ready for read */
+    if (readset_in && FD_ISSET(i, readset_in) && ((lastdata != NULL) || (rcvevent > 0))) {
+      FD_SET(i, &lreadset);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for reading\n", i));
+      nready++;
+    }
+    /* See if netconn of this socket is ready for write */
+    if (writeset_in && FD_ISSET(i, writeset_in) && (sendevent != 0)) {
+      FD_SET(i, &lwriteset);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for writing\n", i));
+      nready++;
+    }
+    /* See if netconn of this socket had an error */
+    if (exceptset_in && FD_ISSET(i, exceptset_in) && (errevent != 0)) {
+      FD_SET(i, &lexceptset);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for exception\n", i));
+      nready++;
+    }
+  }
+  /* copy local sets to the ones provided as arguments */
+  *readset_out = lreadset;
+  *writeset_out = lwriteset;
+  *exceptset_out = lexceptset;
+
+  LWIP_ASSERT("nready >= 0", nready >= 0);
+  return nready;
+}
+
+/**
+ * Processing exceptset is not yet implemented.
+ */
+int
+lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
+            struct timeval *timeout)
+{
+  u32_t waitres = 0;
+  int nready;
+  fd_set lreadset, lwriteset, lexceptset;
+  u32_t msectimeout;
+  struct lwip_select_cb select_cb;
+  err_t err;
+  int i;
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select(%d, %p, %p, %p, tvsec=%"S32_F" tvusec=%"S32_F")\n",
+                  maxfdp1, (void *)readset, (void *) writeset, (void *) exceptset,
+                  timeout ? (s32_t)timeout->tv_sec : (s32_t)-1,
+                  timeout ? (s32_t)timeout->tv_usec : (s32_t)-1));
+
+  /* Go through each socket in each list to count number of sockets which
+     currently match */
+  nready = lwip_selscan(maxfdp1, readset, writeset, exceptset, &lreadset, &lwriteset, &lexceptset);
+
+  /* If we don't have any current events, then suspend if we are supposed to */
+  if (!nready) {
+    if (timeout && timeout->tv_sec == 0 && timeout->tv_usec == 0) {
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: no timeout, returning 0\n"));
+      /* This is OK as the local fdsets are empty and nready is zero,
+         or we would have returned earlier. */
+      goto return_copy_fdsets;
+    }
+
+    /* None ready: add our semaphore to list:
+       We don't actually need any dynamic memory. Our entry on the
+       list is only valid while we are in this function, so it's ok
+       to use local variables. */
+
+    select_cb.next = NULL;
+    select_cb.prev = NULL;
+    select_cb.readset = readset;
+    select_cb.writeset = writeset;
+    select_cb.exceptset = exceptset;
+    select_cb.sem_signalled = 0;
+    err = sys_sem_new(&select_cb.sem, 0);
+    if (err != ERR_OK) {
+      /* failed to create semaphore */
+      set_errno(ENOMEM);
+      return -1;
+    }
+
+    /* Protect the select_cb_list */
+    SYS_ARCH_PROTECT(lev);
+
+    /* Put this select_cb on top of list */
+    select_cb.next = select_cb_list;
+    if (select_cb_list != NULL) {
+      select_cb_list->prev = &select_cb;
+    }
+    select_cb_list = &select_cb;
+    /* Increasing this counter tells even_callback that the list has changed. */
+    select_cb_ctr++;
+
+    /* Now we can safely unprotect */
+    SYS_ARCH_UNPROTECT(lev);
+
+    /* Increase select_waiting for each socket we are interested in */
+    for(i = 0; i < maxfdp1; i++) {
+      if ((readset && FD_ISSET(i, readset)) ||
+          (writeset && FD_ISSET(i, writeset)) ||
+          (exceptset && FD_ISSET(i, exceptset))) {
+        struct lwip_sock *sock = tryget_socket(i);
+        LWIP_ASSERT("sock != NULL", sock != NULL);
+        SYS_ARCH_PROTECT(lev);
+        sock->select_waiting++;
+        LWIP_ASSERT("sock->select_waiting > 0", sock->select_waiting > 0);
+        SYS_ARCH_UNPROTECT(lev);
+      }
+    }
+
+    /* Call lwip_selscan again: there could have been events between
+       the last scan (whithout us on the list) and putting us on the list! */
+    nready = lwip_selscan(maxfdp1, readset, writeset, exceptset, &lreadset, &lwriteset, &lexceptset);
+    if (!nready) {
+      /* Still none ready, just wait to be woken */
+      if (timeout == 0) {
+        /* Wait forever */
+        msectimeout = 0;
+      } else {
+        msectimeout =  ((timeout->tv_sec * 1000) + ((timeout->tv_usec + 500)/1000));
+        if (msectimeout == 0) {
+          /* Wait 1ms at least (0 means wait forever) */
+          msectimeout = 1;
+        }
+      }
+
+      waitres = sys_arch_sem_wait(&select_cb.sem, msectimeout);
+    }
+    /* Increase select_waiting for each socket we are interested in */
+    for(i = 0; i < maxfdp1; i++) {
+      if ((readset && FD_ISSET(i, readset)) ||
+          (writeset && FD_ISSET(i, writeset)) ||
+          (exceptset && FD_ISSET(i, exceptset))) {
+        struct lwip_sock *sock = tryget_socket(i);
+        LWIP_ASSERT("sock != NULL", sock != NULL);
+        SYS_ARCH_PROTECT(lev);
+        sock->select_waiting--;
+        LWIP_ASSERT("sock->select_waiting >= 0", sock->select_waiting >= 0);
+        SYS_ARCH_UNPROTECT(lev);
+      }
+    }
+    /* Take us off the list */
+    SYS_ARCH_PROTECT(lev);
+    if (select_cb.next != NULL) {
+      select_cb.next->prev = select_cb.prev;
+    }
+    if (select_cb_list == &select_cb) {
+      LWIP_ASSERT("select_cb.prev == NULL", select_cb.prev == NULL);
+      select_cb_list = select_cb.next;
+    } else {
+      LWIP_ASSERT("select_cb.prev != NULL", select_cb.prev != NULL);
+      select_cb.prev->next = select_cb.next;
+    }
+    /* Increasing this counter tells even_callback that the list has changed. */
+    select_cb_ctr++;
+    SYS_ARCH_UNPROTECT(lev);
+
+    sys_sem_free(&select_cb.sem);
+    if (waitres == SYS_ARCH_TIMEOUT)  {
+      /* Timeout */
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: timeout expired\n"));
+      /* This is OK as the local fdsets are empty and nready is zero,
+         or we would have returned earlier. */
+      goto return_copy_fdsets;
+    }
+
+    /* See what's set */
+    nready = lwip_selscan(maxfdp1, readset, writeset, exceptset, &lreadset, &lwriteset, &lexceptset);
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: nready=%d\n", nready));
+return_copy_fdsets:
+  set_errno(0);
+  if (readset) {
+    *readset = lreadset;
+  }
+  if (writeset) {
+    *writeset = lwriteset;
+  }
+  if (exceptset) {
+    *exceptset = lexceptset;
+  }
+
+
+  return nready;
+}
+
+/**
+ * Callback registered in the netconn layer for each socket-netconn.
+ * Processes recvevent (data available) and wakes up tasks waiting for select.
+ */
+static void
+event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len)
+{
+  int s;
+  struct lwip_sock *sock;
+  struct lwip_select_cb *scb;
+  int last_select_cb_ctr;
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  LWIP_UNUSED_ARG(len);
+
+  /* Get socket */
+  if (conn) {
+    s = conn->socket;
+    if (s < 0) {
+      /* Data comes in right away after an accept, even though
+       * the server task might not have created a new socket yet.
+       * Just count down (or up) if that's the case and we
+       * will use the data later. Note that only receive events
+       * can happen before the new socket is set up. */
+      SYS_ARCH_PROTECT(lev);
+      if (conn->socket < 0) {
+        if (evt == NETCONN_EVT_RCVPLUS) {
+          conn->socket--;
+        }
+        SYS_ARCH_UNPROTECT(lev);
+        return;
+      }
+      s = conn->socket;
+      SYS_ARCH_UNPROTECT(lev);
+    }
+
+    sock = get_socket(s);
+    if (!sock) {
+      return;
+    }
+  } else {
+    return;
+  }
+
+  SYS_ARCH_PROTECT(lev);
+  /* Set event as required */
+  switch (evt) {
+    case NETCONN_EVT_RCVPLUS:
+      sock->rcvevent++;
+      break;
+    case NETCONN_EVT_RCVMINUS:
+      sock->rcvevent--;
+      break;
+    case NETCONN_EVT_SENDPLUS:
+      sock->sendevent = 1;
+      break;
+    case NETCONN_EVT_SENDMINUS:
+      sock->sendevent = 0;
+      break;
+    case NETCONN_EVT_ERROR:
+      sock->errevent = 1;
+      break;
+    default:
+      LWIP_ASSERT("unknown event", 0);
+      break;
+  }
+
+  if (sock->select_waiting == 0) {
+    /* noone is waiting for this socket, no need to check select_cb_list */
+    SYS_ARCH_UNPROTECT(lev);
+    return;
+  }
+
+  /* Now decide if anyone is waiting for this socket */
+  /* NOTE: This code goes through the select_cb_list list multiple times
+     ONLY IF a select was actually waiting. We go through the list the number
+     of waiting select calls + 1. This list is expected to be small. */
+
+  /* At this point, SYS_ARCH is still protected! */
+again:
+  for (scb = select_cb_list; scb != NULL; scb = scb->next) {
+    if (scb->sem_signalled == 0) {
+      /* semaphore not signalled yet */
+      int do_signal = 0;
+      /* Test this select call for our socket */
+      if (sock->rcvevent > 0) {
+        if (scb->readset && FD_ISSET(s, scb->readset)) {
+          do_signal = 1;
+        }
+      }
+      if (sock->sendevent != 0) {
+        if (!do_signal && scb->writeset && FD_ISSET(s, scb->writeset)) {
+          do_signal = 1;
+        }
+      }
+      if (sock->errevent != 0) {
+        if (!do_signal && scb->exceptset && FD_ISSET(s, scb->exceptset)) {
+          do_signal = 1;
+        }
+      }
+      if (do_signal) {
+        scb->sem_signalled = 1;
+        /* Don't call SYS_ARCH_UNPROTECT() before signaling the semaphore, as this might
+           lead to the select thread taking itself off the list, invalidagin the semaphore. */
+        sys_sem_signal(&scb->sem);
+      }
+    }
+    /* unlock interrupts with each step */
+    last_select_cb_ctr = select_cb_ctr;
+    SYS_ARCH_UNPROTECT(lev);
+    /* this makes sure interrupt protection time is short */
+    SYS_ARCH_PROTECT(lev);
+    if (last_select_cb_ctr != select_cb_ctr) {
+      /* someone has changed select_cb_list, restart at the beginning */
+      goto again;
+    }
+  }
+  SYS_ARCH_UNPROTECT(lev);
+}
+
+/**
+ * Unimplemented: Close one end of a full-duplex connection.
+ * Currently, the full connection is closed.
+ */
+int
+lwip_shutdown(int s, int how)
+{
+  struct lwip_sock *sock;
+  err_t err;
+  u8_t shut_rx = 0, shut_tx = 0;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_shutdown(%d, how=%d)\n", s, how));
+
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+
+  if (sock->conn != NULL) {
+    if (netconn_type(sock->conn) != NETCONN_TCP) {
+      sock_set_errno(sock, EOPNOTSUPP);
+      return EOPNOTSUPP;
+    }
+  } else {
+    sock_set_errno(sock, ENOTCONN);
+    return ENOTCONN;
+  }
+
+  if (how == SHUT_RD) {
+    shut_rx = 1;
+  } else if (how == SHUT_WR) {
+    shut_tx = 1;
+  } else if(how == SHUT_RDWR) {
+    shut_rx = 1;
+    shut_tx = 1;
+  } else {
+    sock_set_errno(sock, EINVAL);
+    return EINVAL;
+  }
+  err = netconn_shutdown(sock->conn, shut_rx, shut_tx);
+
+  sock_set_errno(sock, err_to_errno(err));
+  return (err == ERR_OK ? 0 : -1);
+}
+
+static int
+lwip_getaddrname(int s, struct sockaddr *name, socklen_t *namelen, u8_t local)
+{
+  struct lwip_sock *sock;
+  struct sockaddr_in sin;
+  ip_addr_t naddr;
+
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+
+  memset(&sin, 0, sizeof(sin));
+  sin.sin_len = sizeof(sin);
+  sin.sin_family = AF_INET;
+
+  /* get the IP address and port */
+  netconn_getaddr(sock->conn, &naddr, &sin.sin_port, local);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getaddrname(%d, addr=", s));
+  ip_addr_debug_print(SOCKETS_DEBUG, &naddr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", sin.sin_port));
+
+  sin.sin_port = htons(sin.sin_port);
+  inet_addr_from_ipaddr(&sin.sin_addr, &naddr);
+
+  if (*namelen > sizeof(sin)) {
+    *namelen = sizeof(sin);
+  }
+
+  MEMCPY(name, &sin, *namelen);
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_getpeername(int s, struct sockaddr *name, socklen_t *namelen)
+{
+  return lwip_getaddrname(s, name, namelen, 0);
+}
+
+int
+lwip_getsockname(int s, struct sockaddr *name, socklen_t *namelen)
+{
+  return lwip_getaddrname(s, name, namelen, 1);
+}
+
+int
+lwip_getsockopt(int s, int level, int optname, void *optval, socklen_t *optlen)
+{
+  err_t err = ERR_OK;
+  struct lwip_sock *sock = get_socket(s);
+  struct lwip_setgetsockopt_data data;
+
+  if (!sock) {
+    return -1;
+  }
+
+  if ((NULL == optval) || (NULL == optlen)) {
+    sock_set_errno(sock, EFAULT);
+    return -1;
+  }
+
+  /* Do length and type checks for the various options first, to keep it readable. */
+  switch (level) {
+   
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch (optname) {
+       
+    case SO_ACCEPTCONN:
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_ERROR:
+    case SO_KEEPALIVE:
+    /* UNIMPL case SO_CONTIMEO: */
+    /* UNIMPL case SO_SNDTIMEO: */
+#if LWIP_SO_RCVTIMEO
+    case SO_RCVTIMEO:
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+    case SO_RCVBUF:
+#endif /* LWIP_SO_RCVBUF */
+    /* UNIMPL case SO_OOBINLINE: */
+    /* UNIMPL case SO_SNDBUF: */
+    /* UNIMPL case SO_RCVLOWAT: */
+    /* UNIMPL case SO_SNDLOWAT: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    case SO_TYPE:
+    /* UNIMPL case SO_USELOOPBACK: */
+      if (*optlen < sizeof(int)) {
+        err = EINVAL;
+      }
+      break;
+
+    case SO_NO_CHECK:
+      if (*optlen < sizeof(int)) {
+        err = EINVAL;
+      }
+#if LWIP_UDP
+      if ((sock->conn->type != NETCONN_UDP) ||
+          ((udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_UDPLITE) != 0)) {
+        /* this flag is only available for UDP, not for UDP lite */
+        err = EAFNOSUPPORT;
+      }
+#endif /* LWIP_UDP */
+      break;
+
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n",
+                                  s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+                     
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch (optname) {
+    /* UNIMPL case IP_HDRINCL: */
+    /* UNIMPL case IP_RCVDSTADDR: */
+    /* UNIMPL case IP_RCVIF: */
+    case IP_TTL:
+    case IP_TOS:
+      if (*optlen < sizeof(int)) {
+        err = EINVAL;
+      }
+      break;
+#if LWIP_IGMP
+    case IP_MULTICAST_TTL:
+      if (*optlen < sizeof(u8_t)) {
+        err = EINVAL;
+      }
+      break;
+    case IP_MULTICAST_IF:
+      if (*optlen < sizeof(struct in_addr)) {
+        err = EINVAL;
+      }
+      break;
+    case IP_MULTICAST_LOOP:
+      if (*optlen < sizeof(u8_t)) {
+        err = EINVAL;
+      }
+      if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_UDP) {
+        err = EAFNOSUPPORT;
+      }
+      break;
+#endif /* LWIP_IGMP */
+
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n",
+                                  s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+         
+#if LWIP_TCP
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    if (*optlen < sizeof(int)) {
+      err = EINVAL;
+      break;
+    }
+    
+    /* If this is no TCP socket, ignore any options. */
+    if (sock->conn->type != NETCONN_TCP)
+      return 0;
+
+    switch (optname) {
+    case TCP_NODELAY:
+    case TCP_KEEPALIVE:
+#if LWIP_TCP_KEEPALIVE
+    case TCP_KEEPIDLE:
+    case TCP_KEEPINTVL:
+    case TCP_KEEPCNT:
+#endif /* LWIP_TCP_KEEPALIVE */
+      break;
+       
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n",
+                                  s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_TCP */
+#if LWIP_UDP && LWIP_UDPLITE
+/* Level: IPPROTO_UDPLITE */
+  case IPPROTO_UDPLITE:
+    if (*optlen < sizeof(int)) {
+      err = EINVAL;
+      break;
+    }
+    
+    /* If this is no UDP lite socket, ignore any options. */
+    if (sock->conn->type != NETCONN_UDPLITE) {
+      return 0;
+    }
+
+    switch (optname) {
+    case UDPLITE_SEND_CSCOV:
+    case UDPLITE_RECV_CSCOV:
+      break;
+       
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UNIMPL: optname=0x%x, ..)\n",
+                                  s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_UDP && LWIP_UDPLITE*/
+/* UNDEFINED LEVEL */
+  default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n",
+                                  s, level, optname));
+      err = ENOPROTOOPT;
+  }  /* switch */
+
+   
+  if (err != ERR_OK) {
+    sock_set_errno(sock, err);
+    return -1;
+  }
+
+  /* Now do the actual option processing */
+  data.sock = sock;
+#ifdef LWIP_DEBUG
+  data.s = s;
+#endif /* LWIP_DEBUG */
+  data.level = level;
+  data.optname = optname;
+  data.optval = optval;
+  data.optlen = optlen;
+  data.err = err;
+  tcpip_callback(lwip_getsockopt_internal, &data);
+  sys_arch_sem_wait(&sock->conn->op_completed, 0);
+  /* maybe lwip_getsockopt_internal has changed err */
+  err = data.err;
+
+  sock_set_errno(sock, err);
+  return err ? -1 : 0;
+}
+
+static void
+lwip_getsockopt_internal(void *arg)
+{
+  struct lwip_sock *sock;
+#ifdef LWIP_DEBUG
+  int s;
+#endif /* LWIP_DEBUG */
+  int level, optname;
+  void *optval;
+  struct lwip_setgetsockopt_data *data;
+
+  LWIP_ASSERT("arg != NULL", arg != NULL);
+
+  data = (struct lwip_setgetsockopt_data*)arg;
+  sock = data->sock;
+#ifdef LWIP_DEBUG
+  s = data->s;
+#endif /* LWIP_DEBUG */
+  level = data->level;
+  optname = data->optname;
+  optval = data->optval;
+
+  switch (level) {
+
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch (optname) {
+
+    /* The option flags */
+    case SO_ACCEPTCONN:
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_KEEPALIVE:
+    /* UNIMPL case SO_OOBINCLUDE: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    /*case SO_USELOOPBACK: UNIMPL */
+      *(int*)optval = sock->conn->pcb.ip->so_options & optname;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, optname=0x%x, ..) = %s\n",
+                                  s, optname, (*(int*)optval?"on":"off")));
+      break;
+
+    case SO_TYPE:
+      switch (NETCONNTYPE_GROUP(sock->conn->type)) {
+      case NETCONN_RAW:
+        *(int*)optval = SOCK_RAW;
+        break;
+      case NETCONN_TCP:
+        *(int*)optval = SOCK_STREAM;
+        break;
+      case NETCONN_UDP:
+        *(int*)optval = SOCK_DGRAM;
+        break;
+      default: /* unrecognized socket type */
+        *(int*)optval = sock->conn->type;
+        LWIP_DEBUGF(SOCKETS_DEBUG,
+                    ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE): unrecognized socket type %d\n",
+                    s, *(int *)optval));
+      }  /* switch (sock->conn->type) */
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE) = %d\n",
+                  s, *(int *)optval));
+      break;
+
+    case SO_ERROR:
+      /* only overwrite ERR_OK or tempoary errors */
+      if ((sock->err == 0) || (sock->err == EINPROGRESS)) {
+        sock_set_errno(sock, err_to_errno(sock->conn->last_err));
+      } 
+      *(int *)optval = sock->err;
+      sock->err = 0;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_ERROR) = %d\n",
+                  s, *(int *)optval));
+      break;
+
+#if LWIP_SO_RCVTIMEO
+    case SO_RCVTIMEO:
+      *(int *)optval = netconn_get_recvtimeout(sock->conn);
+      break;
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+    case SO_RCVBUF:
+      *(int *)optval = netconn_get_recvbufsize(sock->conn);
+      break;
+#endif /* LWIP_SO_RCVBUF */
+#if LWIP_UDP
+    case SO_NO_CHECK:
+      *(int*)optval = (udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_NOCHKSUM) ? 1 : 0;
+      break;
+#endif /* LWIP_UDP*/
+    default:
+      LWIP_ASSERT("unhandled optname", 0);
+      break;
+    }  /* switch (optname) */
+    break;
+
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch (optname) {
+    case IP_TTL:
+      *(int*)optval = sock->conn->pcb.ip->ttl;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TTL) = %d\n",
+                  s, *(int *)optval));
+      break;
+    case IP_TOS:
+      *(int*)optval = sock->conn->pcb.ip->tos;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TOS) = %d\n",
+                  s, *(int *)optval));
+      break;
+#if LWIP_IGMP
+    case IP_MULTICAST_TTL:
+      *(u8_t*)optval = sock->conn->pcb.ip->ttl;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_TTL) = %d\n",
+                  s, *(int *)optval));
+      break;
+    case IP_MULTICAST_IF:
+      inet_addr_from_ipaddr((struct in_addr*)optval, &sock->conn->pcb.udp->multicast_ip);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_IF) = 0x%"X32_F"\n",
+                  s, *(u32_t *)optval));
+      break;
+    case IP_MULTICAST_LOOP:
+      if ((sock->conn->pcb.udp->flags & UDP_FLAGS_MULTICAST_LOOP) != 0) {
+        *(u8_t*)optval = 1;
+      } else {
+        *(u8_t*)optval = 0;
+      }
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_LOOP) = %d\n",
+                  s, *(int *)optval));
+      break;
+#endif /* LWIP_IGMP */
+    default:
+      LWIP_ASSERT("unhandled optname", 0);
+      break;
+    }  /* switch (optname) */
+    break;
+
+#if LWIP_TCP
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    switch (optname) {
+    case TCP_NODELAY:
+      *(int*)optval = tcp_nagle_disabled(sock->conn->pcb.tcp);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_NODELAY) = %s\n",
+                  s, (*(int*)optval)?"on":"off") );
+      break;
+    case TCP_KEEPALIVE:
+      *(int*)optval = (int)sock->conn->pcb.tcp->keep_idle;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPALIVE) = %d\n",
+                  s, *(int *)optval));
+      break;
+
+#if LWIP_TCP_KEEPALIVE
+    case TCP_KEEPIDLE:
+      *(int*)optval = (int)(sock->conn->pcb.tcp->keep_idle/1000);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPIDLE) = %d\n",
+                  s, *(int *)optval));
+      break;
+    case TCP_KEEPINTVL:
+      *(int*)optval = (int)(sock->conn->pcb.tcp->keep_intvl/1000);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPINTVL) = %d\n",
+                  s, *(int *)optval));
+      break;
+    case TCP_KEEPCNT:
+      *(int*)optval = (int)sock->conn->pcb.tcp->keep_cnt;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPCNT) = %d\n",
+                  s, *(int *)optval));
+      break;
+#endif /* LWIP_TCP_KEEPALIVE */
+    default:
+      LWIP_ASSERT("unhandled optname", 0);
+      break;
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_TCP */
+#if LWIP_UDP && LWIP_UDPLITE
+  /* Level: IPPROTO_UDPLITE */
+  case IPPROTO_UDPLITE:
+    switch (optname) {
+    case UDPLITE_SEND_CSCOV:
+      *(int*)optval = sock->conn->pcb.udp->chksum_len_tx;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UDPLITE_SEND_CSCOV) = %d\n",
+                  s, (*(int*)optval)) );
+      break;
+    case UDPLITE_RECV_CSCOV:
+      *(int*)optval = sock->conn->pcb.udp->chksum_len_rx;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UDPLITE_RECV_CSCOV) = %d\n",
+                  s, (*(int*)optval)) );
+      break;
+    default:
+      LWIP_ASSERT("unhandled optname", 0);
+      break;
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_UDP */
+  default:
+    LWIP_ASSERT("unhandled level", 0);
+    break;
+  } /* switch (level) */
+  sys_sem_signal(&sock->conn->op_completed);
+}
+
+int
+lwip_setsockopt(int s, int level, int optname, const void *optval, socklen_t optlen)
+{
+  struct lwip_sock *sock = get_socket(s);
+  err_t err = ERR_OK;
+  struct lwip_setgetsockopt_data data;
+
+  if (!sock) {
+    return -1;
+  }
+
+  if (NULL == optval) {
+    sock_set_errno(sock, EFAULT);
+    return -1;
+  }
+
+  /* Do length and type checks for the various options first, to keep it readable. */
+  switch (level) {
+
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch (optname) {
+
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_KEEPALIVE:
+    /* UNIMPL case case SO_CONTIMEO: */
+    /* UNIMPL case case SO_SNDTIMEO: */
+#if LWIP_SO_RCVTIMEO
+    case SO_RCVTIMEO:
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+    case SO_RCVBUF:
+#endif /* LWIP_SO_RCVBUF */
+    /* UNIMPL case SO_OOBINLINE: */
+    /* UNIMPL case SO_SNDBUF: */
+    /* UNIMPL case SO_RCVLOWAT: */
+    /* UNIMPL case SO_SNDLOWAT: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    /* UNIMPL case SO_USELOOPBACK: */
+      if (optlen < sizeof(int)) {
+        err = EINVAL;
+      }
+      break;
+    case SO_NO_CHECK:
+      if (optlen < sizeof(int)) {
+        err = EINVAL;
+      }
+#if LWIP_UDP
+      if ((sock->conn->type != NETCONN_UDP) ||
+          ((udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_UDPLITE) != 0)) {
+        /* this flag is only available for UDP, not for UDP lite */
+        err = EAFNOSUPPORT;
+      }
+#endif /* LWIP_UDP */
+      break;
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n",
+                  s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch (optname) {
+    /* UNIMPL case IP_HDRINCL: */
+    /* UNIMPL case IP_RCVDSTADDR: */
+    /* UNIMPL case IP_RCVIF: */
+    case IP_TTL:
+    case IP_TOS:
+      if (optlen < sizeof(int)) {
+        err = EINVAL;
+      }
+      break;
+#if LWIP_IGMP
+    case IP_MULTICAST_TTL:
+      if (optlen < sizeof(u8_t)) {
+        err = EINVAL;
+      }
+      if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_UDP) {
+        err = EAFNOSUPPORT;
+      }
+      break;
+    case IP_MULTICAST_IF:
+      if (optlen < sizeof(struct in_addr)) {
+        err = EINVAL;
+      }
+      if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_UDP) {
+        err = EAFNOSUPPORT;
+      }
+      break;
+    case IP_MULTICAST_LOOP:
+      if (optlen < sizeof(u8_t)) {
+        err = EINVAL;
+      }
+      if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_UDP) {
+        err = EAFNOSUPPORT;
+      }
+      break;
+    case IP_ADD_MEMBERSHIP:
+    case IP_DROP_MEMBERSHIP:
+      if (optlen < sizeof(struct ip_mreq)) {
+        err = EINVAL;
+      }
+      if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_UDP) {
+        err = EAFNOSUPPORT;
+      }
+      break;
+#endif /* LWIP_IGMP */
+      default:
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n",
+                    s, optname));
+        err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+
+#if LWIP_TCP
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    if (optlen < sizeof(int)) {
+      err = EINVAL;
+      break;
+    }
+
+    /* If this is no TCP socket, ignore any options. */
+    if (sock->conn->type != NETCONN_TCP)
+      return 0;
+
+    switch (optname) {
+    case TCP_NODELAY:
+    case TCP_KEEPALIVE:
+#if LWIP_TCP_KEEPALIVE
+    case TCP_KEEPIDLE:
+    case TCP_KEEPINTVL:
+    case TCP_KEEPCNT:
+#endif /* LWIP_TCP_KEEPALIVE */
+      break;
+
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n",
+                  s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_TCP */
+#if LWIP_UDP && LWIP_UDPLITE
+/* Level: IPPROTO_UDPLITE */
+  case IPPROTO_UDPLITE:
+    if (optlen < sizeof(int)) {
+      err = EINVAL;
+      break;
+    }
+
+    /* If this is no UDP lite socket, ignore any options. */
+    if (sock->conn->type != NETCONN_UDPLITE)
+      return 0;
+
+    switch (optname) {
+    case UDPLITE_SEND_CSCOV:
+    case UDPLITE_RECV_CSCOV:
+      break;
+
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UNIMPL: optname=0x%x, ..)\n",
+                  s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_UDP && LWIP_UDPLITE */
+/* UNDEFINED LEVEL */
+  default:
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n",
+                s, level, optname));
+    err = ENOPROTOOPT;
+  }  /* switch (level) */
+
+
+  if (err != ERR_OK) {
+    sock_set_errno(sock, err);
+    return -1;
+  }
+
+
+  /* Now do the actual option processing */
+  data.sock = sock;
+#ifdef LWIP_DEBUG
+  data.s = s;
+#endif /* LWIP_DEBUG */
+  data.level = level;
+  data.optname = optname;
+  data.optval = (void*)optval;
+  data.optlen = &optlen;
+  data.err = err;
+  tcpip_callback(lwip_setsockopt_internal, &data);
+  sys_arch_sem_wait(&sock->conn->op_completed, 0);
+  /* maybe lwip_setsockopt_internal has changed err */
+  err = data.err;
+
+  sock_set_errno(sock, err);
+  return err ? -1 : 0;
+}
+
+static void
+lwip_setsockopt_internal(void *arg)
+{
+  struct lwip_sock *sock;
+#ifdef LWIP_DEBUG
+  int s;
+#endif /* LWIP_DEBUG */
+  int level, optname;
+  const void *optval;
+  struct lwip_setgetsockopt_data *data;
+
+  LWIP_ASSERT("arg != NULL", arg != NULL);
+
+  data = (struct lwip_setgetsockopt_data*)arg;
+  sock = data->sock;
+#ifdef LWIP_DEBUG
+  s = data->s;
+#endif /* LWIP_DEBUG */
+  level = data->level;
+  optname = data->optname;
+  optval = data->optval;
+
+  switch (level) {
+
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch (optname) {
+
+    /* The option flags */
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_KEEPALIVE:
+    /* UNIMPL case SO_OOBINCLUDE: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    /* UNIMPL case SO_USELOOPBACK: */
+      if (*(int*)optval) {
+        sock->conn->pcb.ip->so_options |= optname;
+      } else {
+        sock->conn->pcb.ip->so_options &= ~optname;
+      }
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, optname=0x%x, ..) -> %s\n",
+                  s, optname, (*(int*)optval?"on":"off")));
+      break;
+#if LWIP_SO_RCVTIMEO
+    case SO_RCVTIMEO:
+      netconn_set_recvtimeout(sock->conn, *(int*)optval);
+      break;
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+    case SO_RCVBUF:
+      netconn_set_recvbufsize(sock->conn, *(int*)optval);
+      break;
+#endif /* LWIP_SO_RCVBUF */
+#if LWIP_UDP
+    case SO_NO_CHECK:
+      if (*(int*)optval) {
+        udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) | UDP_FLAGS_NOCHKSUM);
+      } else {
+        udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) & ~UDP_FLAGS_NOCHKSUM);
+      }
+      break;
+#endif /* LWIP_UDP */
+    default:
+      LWIP_ASSERT("unhandled optname", 0);
+      break;
+    }  /* switch (optname) */
+    break;
+
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch (optname) {
+    case IP_TTL:
+      sock->conn->pcb.ip->ttl = (u8_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TTL, ..) -> %d\n",
+                  s, sock->conn->pcb.ip->ttl));
+      break;
+    case IP_TOS:
+      sock->conn->pcb.ip->tos = (u8_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TOS, ..)-> %d\n",
+                  s, sock->conn->pcb.ip->tos));
+      break;
+#if LWIP_IGMP
+    case IP_MULTICAST_TTL:
+      sock->conn->pcb.udp->ttl = (u8_t)(*(u8_t*)optval);
+      break;
+    case IP_MULTICAST_IF:
+      inet_addr_to_ipaddr(&sock->conn->pcb.udp->multicast_ip, (struct in_addr*)optval);
+      break;
+    case IP_MULTICAST_LOOP:
+      if (*(u8_t*)optval) {
+        udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) | UDP_FLAGS_MULTICAST_LOOP);
+      } else {
+        udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) & ~UDP_FLAGS_MULTICAST_LOOP);
+      }
+      break;
+    case IP_ADD_MEMBERSHIP:
+    case IP_DROP_MEMBERSHIP:
+      {
+        /* If this is a TCP or a RAW socket, ignore these options. */
+        struct ip_mreq *imr = (struct ip_mreq *)optval;
+        ip_addr_t if_addr;
+        ip_addr_t multi_addr;
+        inet_addr_to_ipaddr(&if_addr, &imr->imr_interface);
+        inet_addr_to_ipaddr(&multi_addr, &imr->imr_multiaddr);
+        if(optname == IP_ADD_MEMBERSHIP){
+          data->err = igmp_joingroup(&if_addr, &multi_addr);
+        } else {
+          data->err = igmp_leavegroup(&if_addr, &multi_addr);
+        }
+        if(data->err != ERR_OK) {
+          data->err = EADDRNOTAVAIL;
+        }
+      }
+      break;
+#endif /* LWIP_IGMP */
+    default:
+      LWIP_ASSERT("unhandled optname", 0);
+      break;
+    }  /* switch (optname) */
+    break;
+
+#if LWIP_TCP
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    switch (optname) {
+    case TCP_NODELAY:
+      if (*(int*)optval) {
+        tcp_nagle_disable(sock->conn->pcb.tcp);
+      } else {
+        tcp_nagle_enable(sock->conn->pcb.tcp);
+      }
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_NODELAY) -> %s\n",
+                  s, (*(int *)optval)?"on":"off") );
+      break;
+    case TCP_KEEPALIVE:
+      sock->conn->pcb.tcp->keep_idle = (u32_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) -> %"U32_F"\n",
+                  s, sock->conn->pcb.tcp->keep_idle));
+      break;
+
+#if LWIP_TCP_KEEPALIVE
+    case TCP_KEEPIDLE:
+      sock->conn->pcb.tcp->keep_idle = 1000*(u32_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPIDLE) -> %"U32_F"\n",
+                  s, sock->conn->pcb.tcp->keep_idle));
+      break;
+    case TCP_KEEPINTVL:
+      sock->conn->pcb.tcp->keep_intvl = 1000*(u32_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPINTVL) -> %"U32_F"\n",
+                  s, sock->conn->pcb.tcp->keep_intvl));
+      break;
+    case TCP_KEEPCNT:
+      sock->conn->pcb.tcp->keep_cnt = (u32_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPCNT) -> %"U32_F"\n",
+                  s, sock->conn->pcb.tcp->keep_cnt));
+      break;
+#endif /* LWIP_TCP_KEEPALIVE */
+    default:
+      LWIP_ASSERT("unhandled optname", 0);
+      break;
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_TCP*/
+#if LWIP_UDP && LWIP_UDPLITE
+  /* Level: IPPROTO_UDPLITE */
+  case IPPROTO_UDPLITE:
+    switch (optname) {
+    case UDPLITE_SEND_CSCOV:
+      if (((*(int*)optval != 0) && ((*(int*)optval < 8)) ) || (*(int*)optval > 0xffff)) {
+        /* don't allow illegal values! */
+        sock->conn->pcb.udp->chksum_len_tx = 8;
+      } else {
+        sock->conn->pcb.udp->chksum_len_tx = (u16_t)*(int*)optval;
+      }
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UDPLITE_SEND_CSCOV) -> %d\n",
+                  s, (*(int*)optval)) );
+      break;
+    case UDPLITE_RECV_CSCOV:
+      if (((*(int*)optval != 0) && ((*(int*)optval < 8))) || (*(int*)optval > 0xffff)) {
+        /* don't allow illegal values! */
+        sock->conn->pcb.udp->chksum_len_rx = 8;
+      } else {
+        sock->conn->pcb.udp->chksum_len_rx = (u16_t)*(int*)optval;
+      }
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UDPLITE_RECV_CSCOV) -> %d\n",
+                  s, (*(int*)optval)) );
+      break;
+    default:
+      LWIP_ASSERT("unhandled optname", 0);
+      break;
+    }  /* switch (optname) */
+    break;
+#endif /* LWIP_UDP */
+  default:
+    LWIP_ASSERT("unhandled level", 0);
+    break;
+  }  /* switch (level) */
+  sys_sem_signal(&sock->conn->op_completed);
+}
+
+int
+lwip_ioctl(int s, long cmd, void *argp)
+{
+  struct lwip_sock *sock = get_socket(s);
+  u8_t val;
+#if LWIP_SO_RCVBUF
+  u16_t buflen = 0;
+  s16_t recv_avail;
+#endif /* LWIP_SO_RCVBUF */
+
+  if (!sock) {
+    return -1;
+  }
+
+  switch (cmd) {
+#if LWIP_SO_RCVBUF
+  case FIONREAD:
+    if (!argp) {
+      sock_set_errno(sock, EINVAL);
+      return -1;
+    }
+
+    SYS_ARCH_GET(sock->conn->recv_avail, recv_avail);
+    if (recv_avail < 0) {
+      recv_avail = 0;
+    }
+    *((u16_t*)argp) = (u16_t)recv_avail;
+
+    /* Check if there is data left from the last recv operation. /maq 041215 */
+    if (sock->lastdata) {
+      struct pbuf *p = (struct pbuf *)sock->lastdata;
+      if (netconn_type(sock->conn) != NETCONN_TCP) {
+        p = ((struct netbuf *)p)->p;
+      }
+      buflen = p->tot_len;
+      buflen -= sock->lastoffset;
+
+      *((u16_t*)argp) += buflen;
+    }
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONREAD, %p) = %"U16_F"\n", s, argp, *((u16_t*)argp)));
+    sock_set_errno(sock, 0);
+    return 0;
+#endif /* LWIP_SO_RCVBUF */
+
+  case FIONBIO:
+    val = 0;
+    if (argp && *(u32_t*)argp) {
+      val = 1;
+    }
+    netconn_set_nonblocking(sock->conn, val);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONBIO, %d)\n", s, val));
+    sock_set_errno(sock, 0);
+    return 0;
+
+  default:
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, UNIMPL: 0x%lx, %p)\n", s, cmd, argp));
+    sock_set_errno(sock, ENOSYS); /* not yet implemented */
+    return -1;
+  } /* switch (cmd) */
+}
+
+/** A minimal implementation of fcntl.
+ * Currently only the commands F_GETFL and F_SETFL are implemented.
+ * Only the flag O_NONBLOCK is implemented.
+ */
+int
+lwip_fcntl(int s, int cmd, int val)
+{
+  struct lwip_sock *sock = get_socket(s);
+  int ret = -1;
+
+  if (!sock || !sock->conn) {
+    return -1;
+  }
+
+  switch (cmd) {
+  case F_GETFL:
+    ret = netconn_is_nonblocking(sock->conn) ? O_NONBLOCK : 0;
+    break;
+  case F_SETFL:
+    if ((val & ~O_NONBLOCK) == 0) {
+      /* only O_NONBLOCK, all other bits are zero */
+      netconn_set_nonblocking(sock->conn, val & O_NONBLOCK);
+      ret = 0;
+    }
+    break;
+  default:
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_fcntl(%d, UNIMPL: %d, %d)\n", s, cmd, val));
+    break;
+  }
+  return ret;
+}
+
+#endif /* LWIP_SOCKET */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/tcpip.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/tcpip.c
new file mode 100644
index 0000000..857e7d9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/api/tcpip.c
@@ -0,0 +1,460 @@
+/**
+ * @file
+ * Sequential API Main thread module
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if !NO_SYS /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/sys.h"
+#include "lwip/memp.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/tcpip.h"
+#include "lwip/init.h"
+#include "netif/etharp.h"
+#include "netif/ppp_oe.h"
+
+/* global variables */
+static tcpip_init_done_fn tcpip_init_done;
+static void *tcpip_init_done_arg;
+static sys_mbox_t mbox;
+
+#if LWIP_TCPIP_CORE_LOCKING
+/** The global semaphore to lock the stack. */
+sys_mutex_t lock_tcpip_core;
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+
+
+/**
+ * The main lwIP thread. This thread has exclusive access to lwIP core functions
+ * (unless access to them is not locked). Other threads communicate with this
+ * thread using message boxes.
+ *
+ * It also starts all the timers to make sure they are running in the right
+ * thread context.
+ *
+ * @param arg unused argument
+ */
+static void
+tcpip_thread(void *arg)
+{
+  struct tcpip_msg *msg;
+  LWIP_UNUSED_ARG(arg);
+
+  if (tcpip_init_done != NULL) {
+    tcpip_init_done(tcpip_init_done_arg);
+  }
+
+  LOCK_TCPIP_CORE();
+  while (1) {                          /* MAIN Loop */
+    UNLOCK_TCPIP_CORE();
+    LWIP_TCPIP_THREAD_ALIVE();
+    /* wait for a message, timeouts are processed while waiting */
+    sys_timeouts_mbox_fetch(&mbox, (void **)&msg);
+    LOCK_TCPIP_CORE();
+    switch (msg->type) {
+#if LWIP_NETCONN
+    case TCPIP_MSG_API:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: API message %p\n", (void *)msg));
+      msg->msg.apimsg->function(&(msg->msg.apimsg->msg));
+      break;
+#endif /* LWIP_NETCONN */
+
+#if !LWIP_TCPIP_CORE_LOCKING_INPUT
+    case TCPIP_MSG_INPKT:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: PACKET %p\n", (void *)msg));
+#if LWIP_ETHERNET
+      if (msg->msg.inp.netif->flags & (NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET)) {
+        ethernet_input(msg->msg.inp.p, msg->msg.inp.netif);
+      } else
+#endif /* LWIP_ETHERNET */
+      {
+        ip_input(msg->msg.inp.p, msg->msg.inp.netif);
+      }
+      memp_free(MEMP_TCPIP_MSG_INPKT, msg);
+      break;
+#endif /* LWIP_TCPIP_CORE_LOCKING_INPUT */
+
+#if LWIP_NETIF_API
+    case TCPIP_MSG_NETIFAPI:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: Netif API message %p\n", (void *)msg));
+      msg->msg.netifapimsg->function(&(msg->msg.netifapimsg->msg));
+      break;
+#endif /* LWIP_NETIF_API */
+
+    case TCPIP_MSG_CALLBACK:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg));
+      msg->msg.cb.function(msg->msg.cb.ctx);
+      memp_free(MEMP_TCPIP_MSG_API, msg);
+      break;
+
+#if LWIP_TCPIP_TIMEOUT
+    case TCPIP_MSG_TIMEOUT:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: TIMEOUT %p\n", (void *)msg));
+      sys_timeout(msg->msg.tmo.msecs, msg->msg.tmo.h, msg->msg.tmo.arg);
+      memp_free(MEMP_TCPIP_MSG_API, msg);
+      break;
+    case TCPIP_MSG_UNTIMEOUT:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: UNTIMEOUT %p\n", (void *)msg));
+      sys_untimeout(msg->msg.tmo.h, msg->msg.tmo.arg);
+      memp_free(MEMP_TCPIP_MSG_API, msg);
+      break;
+#endif /* LWIP_TCPIP_TIMEOUT */
+
+    default:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: invalid message: %d\n", msg->type));
+      LWIP_ASSERT("tcpip_thread: invalid message", 0);
+      break;
+    }
+  }
+}
+
+/**
+ * Pass a received packet to tcpip_thread for input processing
+ *
+ * @param p the received packet, p->payload pointing to the Ethernet header or
+ *          to an IP header (if inp doesn't have NETIF_FLAG_ETHARP or
+ *          NETIF_FLAG_ETHERNET flags)
+ * @param inp the network interface on which the packet was received
+ */
+err_t
+tcpip_input(struct pbuf *p, struct netif *inp)
+{
+#if LWIP_TCPIP_CORE_LOCKING_INPUT
+  err_t ret;
+  LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_input: PACKET %p/%p\n", (void *)p, (void *)inp));
+  LOCK_TCPIP_CORE();
+#if LWIP_ETHERNET
+  if (inp->flags & (NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET)) {
+    ret = ethernet_input(p, inp);
+  } else
+#endif /* LWIP_ETHERNET */
+  {
+    ret = ip_input(p, inp);
+  }
+  UNLOCK_TCPIP_CORE();
+  return ret;
+#else /* LWIP_TCPIP_CORE_LOCKING_INPUT */
+  struct tcpip_msg *msg;
+
+  if (sys_mbox_valid(&mbox)) {
+    msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_INPKT);
+    if (msg == NULL) {
+      return ERR_MEM;
+    }
+
+    msg->type = TCPIP_MSG_INPKT;
+    msg->msg.inp.p = p;
+    msg->msg.inp.netif = inp;
+    if (sys_mbox_trypost(&mbox, msg) != ERR_OK) {
+      memp_free(MEMP_TCPIP_MSG_INPKT, msg);
+      return ERR_MEM;
+    }
+    return ERR_OK;
+  }
+  return ERR_VAL;
+#endif /* LWIP_TCPIP_CORE_LOCKING_INPUT */
+}
+
+/**
+ * Call a specific function in the thread context of
+ * tcpip_thread for easy access synchronization.
+ * A function called in that way may access lwIP core code
+ * without fearing concurrent access.
+ *
+ * @param f the function to call
+ * @param ctx parameter passed to f
+ * @param block 1 to block until the request is posted, 0 to non-blocking mode
+ * @return ERR_OK if the function was called, another err_t if not
+ */
+err_t
+tcpip_callback_with_block(tcpip_callback_fn function, void *ctx, u8_t block)
+{
+  struct tcpip_msg *msg;
+
+  if (sys_mbox_valid(&mbox)) {
+    msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API);
+    if (msg == NULL) {
+      return ERR_MEM;
+    }
+
+    msg->type = TCPIP_MSG_CALLBACK;
+    msg->msg.cb.function = function;
+    msg->msg.cb.ctx = ctx;
+    if (block) {
+      sys_mbox_post(&mbox, msg);
+    } else {
+      if (sys_mbox_trypost(&mbox, msg) != ERR_OK) {
+        memp_free(MEMP_TCPIP_MSG_API, msg);
+        return ERR_MEM;
+      }
+    }
+    return ERR_OK;
+  }
+  return ERR_VAL;
+}
+
+#if LWIP_TCPIP_TIMEOUT
+/**
+ * call sys_timeout in tcpip_thread
+ *
+ * @param msec time in milliseconds for timeout
+ * @param h function to be called on timeout
+ * @param arg argument to pass to timeout function h
+ * @return ERR_MEM on memory error, ERR_OK otherwise
+ */
+err_t
+tcpip_timeout(u32_t msecs, sys_timeout_handler h, void *arg)
+{
+  struct tcpip_msg *msg;
+
+  if (sys_mbox_valid(&mbox)) {
+    msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API);
+    if (msg == NULL) {
+      return ERR_MEM;
+    }
+
+    msg->type = TCPIP_MSG_TIMEOUT;
+    msg->msg.tmo.msecs = msecs;
+    msg->msg.tmo.h = h;
+    msg->msg.tmo.arg = arg;
+    sys_mbox_post(&mbox, msg);
+    return ERR_OK;
+  }
+  return ERR_VAL;
+}
+
+/**
+ * call sys_untimeout in tcpip_thread
+ *
+ * @param msec time in milliseconds for timeout
+ * @param h function to be called on timeout
+ * @param arg argument to pass to timeout function h
+ * @return ERR_MEM on memory error, ERR_OK otherwise
+ */
+err_t
+tcpip_untimeout(sys_timeout_handler h, void *arg)
+{
+  struct tcpip_msg *msg;
+
+  if (sys_mbox_valid(&mbox)) {
+    msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API);
+    if (msg == NULL) {
+      return ERR_MEM;
+    }
+
+    msg->type = TCPIP_MSG_UNTIMEOUT;
+    msg->msg.tmo.h = h;
+    msg->msg.tmo.arg = arg;
+    sys_mbox_post(&mbox, msg);
+    return ERR_OK;
+  }
+  return ERR_VAL;
+}
+#endif /* LWIP_TCPIP_TIMEOUT */
+
+#if LWIP_NETCONN
+/**
+ * Call the lower part of a netconn_* function
+ * This function is then running in the thread context
+ * of tcpip_thread and has exclusive access to lwIP core code.
+ *
+ * @param apimsg a struct containing the function to call and its parameters
+ * @return ERR_OK if the function was called, another err_t if not
+ */
+err_t
+tcpip_apimsg(struct api_msg *apimsg)
+{
+  struct tcpip_msg msg;
+#ifdef LWIP_DEBUG
+  /* catch functions that don't set err */
+  apimsg->msg.err = ERR_VAL;
+#endif
+  
+  if (sys_mbox_valid(&mbox)) {
+    msg.type = TCPIP_MSG_API;
+    msg.msg.apimsg = apimsg;
+    sys_mbox_post(&mbox, &msg);
+    sys_arch_sem_wait(&apimsg->msg.conn->op_completed, 0);
+    return apimsg->msg.err;
+  }
+  return ERR_VAL;
+}
+
+#if LWIP_TCPIP_CORE_LOCKING
+/**
+ * Call the lower part of a netconn_* function
+ * This function has exclusive access to lwIP core code by locking it
+ * before the function is called.
+ *
+ * @param apimsg a struct containing the function to call and its parameters
+ * @return ERR_OK (only for compatibility fo tcpip_apimsg())
+ */
+err_t
+tcpip_apimsg_lock(struct api_msg *apimsg)
+{
+#ifdef LWIP_DEBUG
+  /* catch functions that don't set err */
+  apimsg->msg.err = ERR_VAL;
+#endif
+
+  LOCK_TCPIP_CORE();
+  apimsg->function(&(apimsg->msg));
+  UNLOCK_TCPIP_CORE();
+  return apimsg->msg.err;
+
+}
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+#endif /* LWIP_NETCONN */
+
+#if LWIP_NETIF_API
+#if !LWIP_TCPIP_CORE_LOCKING
+/**
+ * Much like tcpip_apimsg, but calls the lower part of a netifapi_*
+ * function.
+ *
+ * @param netifapimsg a struct containing the function to call and its parameters
+ * @return error code given back by the function that was called
+ */
+err_t
+tcpip_netifapi(struct netifapi_msg* netifapimsg)
+{
+  struct tcpip_msg msg;
+  
+  if (sys_mbox_valid(&mbox)) {
+    err_t err = sys_sem_new(&netifapimsg->msg.sem, 0);
+    if (err != ERR_OK) {
+      netifapimsg->msg.err = err;
+      return err;
+    }
+    
+    msg.type = TCPIP_MSG_NETIFAPI;
+    msg.msg.netifapimsg = netifapimsg;
+    sys_mbox_post(&mbox, &msg);
+    sys_sem_wait(&netifapimsg->msg.sem);
+    sys_sem_free(&netifapimsg->msg.sem);
+    return netifapimsg->msg.err;
+  }
+  return ERR_VAL;
+}
+#else /* !LWIP_TCPIP_CORE_LOCKING */
+/**
+ * Call the lower part of a netifapi_* function
+ * This function has exclusive access to lwIP core code by locking it
+ * before the function is called.
+ *
+ * @param netifapimsg a struct containing the function to call and its parameters
+ * @return ERR_OK (only for compatibility fo tcpip_netifapi())
+ */
+err_t
+tcpip_netifapi_lock(struct netifapi_msg* netifapimsg)
+{
+  LOCK_TCPIP_CORE();  
+  netifapimsg->function(&(netifapimsg->msg));
+  UNLOCK_TCPIP_CORE();
+  return netifapimsg->msg.err;
+}
+#endif /* !LWIP_TCPIP_CORE_LOCKING */
+#endif /* LWIP_NETIF_API */
+
+/**
+ * Initialize this module:
+ * - initialize all sub modules
+ * - start the tcpip_thread
+ *
+ * @param initfunc a function to call when tcpip_thread is running and finished initializing
+ * @param arg argument to pass to initfunc
+ */
+void
+tcpip_init(tcpip_init_done_fn initfunc, void *arg)
+{
+  lwip_init();
+
+  tcpip_init_done = initfunc;
+  tcpip_init_done_arg = arg;
+  if(sys_mbox_new(&mbox, TCPIP_MBOX_SIZE) != ERR_OK) {
+    LWIP_ASSERT("failed to create tcpip_thread mbox", 0);
+  }
+#if LWIP_TCPIP_CORE_LOCKING
+  if(sys_mutex_new(&lock_tcpip_core) != ERR_OK) {
+    LWIP_ASSERT("failed to create lock_tcpip_core", 0);
+  }
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+
+  sys_thread_new(TCPIP_THREAD_NAME, tcpip_thread, NULL, TCPIP_THREAD_STACKSIZE, TCPIP_THREAD_PRIO);
+}
+
+/**
+ * Simple callback function used with tcpip_callback to free a pbuf
+ * (pbuf_free has a wrong signature for tcpip_callback)
+ *
+ * @param p The pbuf (chain) to be dereferenced.
+ */
+static void
+pbuf_free_int(void *p)
+{
+  struct pbuf *q = (struct pbuf *)p;
+  pbuf_free(q);
+}
+
+/**
+ * A simple wrapper function that allows you to free a pbuf from interrupt context.
+ *
+ * @param p The pbuf (chain) to be dereferenced.
+ * @return ERR_OK if callback could be enqueued, an err_t if not
+ */
+err_t
+pbuf_free_callback(struct pbuf *p)
+{
+  return tcpip_callback_with_block(pbuf_free_int, p, 0);
+}
+
+/**
+ * A simple wrapper function that allows you to free heap memory from
+ * interrupt context.
+ *
+ * @param m the heap memory to free
+ * @return ERR_OK if callback could be enqueued, an err_t if not
+ */
+err_t
+mem_free_callback(void *m)
+{
+  return tcpip_callback_with_block(mem_free, m, 0);
+}
+
+#endif /* !NO_SYS */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/def.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/def.c
new file mode 100644
index 0000000..352b552
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/def.c
@@ -0,0 +1,108 @@
+/**
+ * @file
+ * Common functions used throughout the stack.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt
+ *
+ */
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+
+/**
+ * These are reference implementations of the byte swapping functions.
+ * Again with the aim of being simple, correct and fully portable.
+ * Byte swapping is the second thing you would want to optimize. You will
+ * need to port it to your architecture and in your cc.h:
+ * 
+ * #define LWIP_PLATFORM_BYTESWAP 1
+ * #define LWIP_PLATFORM_HTONS(x) 
+ * #define LWIP_PLATFORM_HTONL(x) 
+ *
+ * Note ntohs() and ntohl() are merely references to the htonx counterparts.
+ */
+
+#if (LWIP_PLATFORM_BYTESWAP == 0) && (BYTE_ORDER == LITTLE_ENDIAN)
+
+/**
+ * Convert an u16_t from host- to network byte order.
+ *
+ * @param n u16_t in host byte order
+ * @return n in network byte order
+ */
+u16_t
+lwip_htons(u16_t n)
+{
+  return ((n & 0xff) << 8) | ((n & 0xff00) >> 8);
+}
+
+/**
+ * Convert an u16_t from network- to host byte order.
+ *
+ * @param n u16_t in network byte order
+ * @return n in host byte order
+ */
+u16_t
+lwip_ntohs(u16_t n)
+{
+  return lwip_htons(n);
+}
+
+/**
+ * Convert an u32_t from host- to network byte order.
+ *
+ * @param n u32_t in host byte order
+ * @return n in network byte order
+ */
+u32_t
+lwip_htonl(u32_t n)
+{
+  return ((n & 0xff) << 24) |
+    ((n & 0xff00) << 8) |
+    ((n & 0xff0000UL) >> 8) |
+    ((n & 0xff000000UL) >> 24);
+}
+
+/**
+ * Convert an u32_t from network- to host byte order.
+ *
+ * @param n u32_t in network byte order
+ * @return n in host byte order
+ */
+u32_t
+lwip_ntohl(u32_t n)
+{
+  return lwip_htonl(n);
+}
+
+#endif /* (LWIP_PLATFORM_BYTESWAP == 0) && (BYTE_ORDER == LITTLE_ENDIAN) */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/dhcp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/dhcp.c
new file mode 100644
index 0000000..81b4be2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/dhcp.c
@@ -0,0 +1,1745 @@
+/**
+ * @file
+ * Dynamic Host Configuration Protocol client
+ *
+ */
+
+/*
+ *
+ * Copyright (c) 2001-2004 Leon Woestenberg 
+ * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is a contribution to the lwIP TCP/IP stack.
+ * The Swedish Institute of Computer Science and Adam Dunkels
+ * are specifically granted permission to redistribute this
+ * source code.
+ *
+ * Author: Leon Woestenberg 
+ *
+ * This is a DHCP client for the lwIP TCP/IP stack. It aims to conform
+ * with RFC 2131 and RFC 2132.
+ *
+ * TODO:
+ * - Support for interfaces other than Ethernet (SLIP, PPP, ...)
+ *
+ * Please coordinate changes and requests with Leon Woestenberg
+ * 
+ *
+ * Integration with your code:
+ *
+ * In lwip/dhcp.h
+ * #define DHCP_COARSE_TIMER_SECS (recommended 60 which is a minute)
+ * #define DHCP_FINE_TIMER_MSECS (recommended 500 which equals TCP coarse timer)
+ *
+ * Then have your application call dhcp_coarse_tmr() and
+ * dhcp_fine_tmr() on the defined intervals.
+ *
+ * dhcp_start(struct netif *netif);
+ * starts a DHCP client instance which configures the interface by
+ * obtaining an IP address lease and maintaining it.
+ *
+ * Use dhcp_release(netif) to end the lease and use dhcp_stop(netif)
+ * to remove the DHCP client.
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_DHCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+#include "lwip/udp.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/def.h"
+#include "lwip/sys.h"
+#include "lwip/dhcp.h"
+#include "lwip/autoip.h"
+#include "lwip/dns.h"
+#include "netif/etharp.h"
+
+#include 
+
+/** Default for DHCP_GLOBAL_XID is 0xABCD0000
+ * This can be changed by defining DHCP_GLOBAL_XID and DHCP_GLOBAL_XID_HEADER, e.g.
+ *  #define DHCP_GLOBAL_XID_HEADER "stdlib.h"
+ *  #define DHCP_GLOBAL_XID rand()
+ */
+#ifdef DHCP_GLOBAL_XID_HEADER
+#include DHCP_GLOBAL_XID_HEADER /* include optional starting XID generation prototypes */
+#endif
+
+/** DHCP_OPTION_MAX_MSG_SIZE is set to the MTU
+ * MTU is checked to be big enough in dhcp_start */
+#define DHCP_MAX_MSG_LEN(netif)        (netif->mtu)
+#define DHCP_MAX_MSG_LEN_MIN_REQUIRED  576
+/** Minimum length for reply before packet is parsed */
+#define DHCP_MIN_REPLY_LEN             44
+
+#define REBOOT_TRIES 2
+
+/** Option handling: options are parsed in dhcp_parse_reply
+ * and saved in an array where other functions can load them from.
+ * This might be moved into the struct dhcp (not necessarily since
+ * lwIP is single-threaded and the array is only used while in recv
+ * callback). */
+#define DHCP_OPTION_IDX_OVERLOAD    0
+#define DHCP_OPTION_IDX_MSG_TYPE    1
+#define DHCP_OPTION_IDX_SERVER_ID   2
+#define DHCP_OPTION_IDX_LEASE_TIME  3
+#define DHCP_OPTION_IDX_T1          4
+#define DHCP_OPTION_IDX_T2          5
+#define DHCP_OPTION_IDX_SUBNET_MASK 6
+#define DHCP_OPTION_IDX_ROUTER      7
+#define DHCP_OPTION_IDX_DNS_SERVER	8
+#define DHCP_OPTION_IDX_MAX         (DHCP_OPTION_IDX_DNS_SERVER + DNS_MAX_SERVERS)
+
+/** Holds the decoded option values, only valid while in dhcp_recv.
+    @todo: move this into struct dhcp? */
+u32_t dhcp_rx_options_val[DHCP_OPTION_IDX_MAX];
+/** Holds a flag which option was received and is contained in dhcp_rx_options_val,
+    only valid while in dhcp_recv.
+    @todo: move this into struct dhcp? */
+u8_t  dhcp_rx_options_given[DHCP_OPTION_IDX_MAX];
+
+#define dhcp_option_given(dhcp, idx)          (dhcp_rx_options_given[idx] != 0)
+#define dhcp_got_option(dhcp, idx)            (dhcp_rx_options_given[idx] = 1)
+#define dhcp_clear_option(dhcp, idx)          (dhcp_rx_options_given[idx] = 0)
+#define dhcp_clear_all_options(dhcp)          (memset(dhcp_rx_options_given, 0, sizeof(dhcp_rx_options_given)))
+#define dhcp_get_option_value(dhcp, idx)      (dhcp_rx_options_val[idx])
+#define dhcp_set_option_value(dhcp, idx, val) (dhcp_rx_options_val[idx] = (val))
+
+
+/* DHCP client state machine functions */
+static err_t dhcp_discover(struct netif *netif);
+static err_t dhcp_select(struct netif *netif);
+static void dhcp_bind(struct netif *netif);
+#if DHCP_DOES_ARP_CHECK
+static err_t dhcp_decline(struct netif *netif);
+#endif /* DHCP_DOES_ARP_CHECK */
+static err_t dhcp_rebind(struct netif *netif);
+static err_t dhcp_reboot(struct netif *netif);
+static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state);
+
+/* receive, unfold, parse and free incoming messages */
+static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, ip_addr_t *addr, u16_t port);
+
+/* set the DHCP timers */
+static void dhcp_timeout(struct netif *netif);
+static void dhcp_t1_timeout(struct netif *netif);
+static void dhcp_t2_timeout(struct netif *netif);
+
+/* build outgoing messages */
+/* create a DHCP message, fill in common headers */
+static err_t dhcp_create_msg(struct netif *netif, struct dhcp *dhcp, u8_t message_type);
+/* free a DHCP request */
+static void dhcp_delete_msg(struct dhcp *dhcp);
+/* add a DHCP option (type, then length in bytes) */
+static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len);
+/* add option values */
+static void dhcp_option_byte(struct dhcp *dhcp, u8_t value);
+static void dhcp_option_short(struct dhcp *dhcp, u16_t value);
+static void dhcp_option_long(struct dhcp *dhcp, u32_t value);
+/* always add the DHCP options trailer to end and pad */
+static void dhcp_option_trailer(struct dhcp *dhcp);
+
+/**
+ * Back-off the DHCP client (because of a received NAK response).
+ *
+ * Back-off the DHCP client because of a received NAK. Receiving a
+ * NAK means the client asked for something non-sensible, for
+ * example when it tries to renew a lease obtained on another network.
+ *
+ * We clear any existing set IP address and restart DHCP negotiation
+ * afresh (as per RFC2131 3.2.3).
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_handle_nak(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_nak(netif=%p) %c%c%"U16_F"\n", 
+    (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+  /* Set the interface down since the address must no longer be used, as per RFC2131 */
+  netif_set_down(netif);
+  /* remove IP address from interface */
+  netif_set_ipaddr(netif, IP_ADDR_ANY);
+  netif_set_gw(netif, IP_ADDR_ANY);
+  netif_set_netmask(netif, IP_ADDR_ANY); 
+  /* Change to a defined state */
+  dhcp_set_state(dhcp, DHCP_BACKING_OFF);
+  /* We can immediately restart discovery */
+  dhcp_discover(netif);
+}
+
+#if DHCP_DOES_ARP_CHECK
+/**
+ * Checks if the offered IP address is already in use.
+ *
+ * It does so by sending an ARP request for the offered address and
+ * entering CHECKING state. If no ARP reply is received within a small
+ * interval, the address is assumed to be free for use by us.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_check(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (s16_t)netif->name[0],
+    (s16_t)netif->name[1]));
+  dhcp_set_state(dhcp, DHCP_CHECKING);
+  /* create an ARP query for the offered IP address, expecting that no host
+     responds, as the IP address should not be in use. */
+  result = etharp_query(netif, &dhcp->offered_ip_addr, NULL);
+  if (result != ERR_OK) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_check: could not perform ARP query\n"));
+  }
+  dhcp->tries++;
+  msecs = 500;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_check(): set request timeout %"U16_F" msecs\n", msecs));
+}
+#endif /* DHCP_DOES_ARP_CHECK */
+
+/**
+ * Remember the configuration offered by a DHCP server.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_handle_offer(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_offer(netif=%p) %c%c%"U16_F"\n",
+    (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+  /* obtain the server address */
+  if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_SERVER_ID)) {
+    ip4_addr_set_u32(&dhcp->server_ip_addr, htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_SERVER_ID)));
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): server 0x%08"X32_F"\n",
+      ip4_addr_get_u32(&dhcp->server_ip_addr)));
+    /* remember offered address */
+    ip_addr_copy(dhcp->offered_ip_addr, dhcp->msg_in->yiaddr);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08"X32_F"\n",
+      ip4_addr_get_u32(&dhcp->offered_ip_addr)));
+
+    dhcp_select(netif);
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
+      ("dhcp_handle_offer(netif=%p) did not get server ID!\n", (void*)netif));
+  }
+}
+
+/**
+ * Select a DHCP server offer out of all offers.
+ *
+ * Simply select the first offer received.
+ *
+ * @param netif the netif under DHCP control
+ * @return lwIP specific error (see error.h)
+ */
+static err_t
+dhcp_select(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_select(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+  dhcp_set_state(dhcp, DHCP_REQUESTING);
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_msg(netif, dhcp, DHCP_REQUEST);
+  if (result == ERR_OK) {
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif));
+
+    /* MUST request the offered IP address */
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr)));
+
+    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+    dhcp_option_long(dhcp, ntohl(ip4_addr_get_u32(&dhcp->server_ip_addr)));
+
+    dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/);
+    dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK);
+    dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER);
+    dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST);
+    dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER);
+
+#if LWIP_NETIF_HOSTNAME
+    if (netif->hostname != NULL) {
+      const char *p = (const char*)netif->hostname;
+      u8_t namelen = (u8_t)strlen(p);
+      if (namelen > 0) {
+        LWIP_ASSERT("DHCP: hostname is too long!", namelen < 255);
+        dhcp_option(dhcp, DHCP_OPTION_HOSTNAME, namelen);
+        while (*p) {
+          dhcp_option_byte(dhcp, *p++);
+        }
+      }
+    }
+#endif /* LWIP_NETIF_HOSTNAME */
+
+    dhcp_option_trailer(dhcp);
+    /* shrink the pbuf to the actual content length */
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    /* send broadcast to any DHCP server */
+    udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif);
+    dhcp_delete_msg(dhcp);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_select: REQUESTING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_select: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = (dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_select(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+/**
+ * The DHCP timer that checks for lease renewal/rebind timeouts.
+ */
+void
+dhcp_coarse_tmr()
+{
+  struct netif *netif = netif_list;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_coarse_tmr()\n"));
+  /* iterate through all network interfaces */
+  while (netif != NULL) {
+    /* only act on DHCP configured interfaces */
+    if (netif->dhcp != NULL) {
+      /* timer is active (non zero), and triggers (zeroes) now? */
+      if (netif->dhcp->t2_timeout-- == 1) {
+        LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n"));
+        /* this clients' rebind timeout triggered */
+        dhcp_t2_timeout(netif);
+      /* timer is active (non zero), and triggers (zeroes) now */
+      } else if (netif->dhcp->t1_timeout-- == 1) {
+        LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n"));
+        /* this clients' renewal timeout triggered */
+        dhcp_t1_timeout(netif);
+      }
+    }
+    /* proceed to next netif */
+    netif = netif->next;
+  }
+}
+
+/**
+ * DHCP transaction timeout handling
+ *
+ * A DHCP server is expected to respond within a short period of time.
+ * This timer checks whether an outstanding DHCP request is timed out.
+ */
+void
+dhcp_fine_tmr()
+{
+  struct netif *netif = netif_list;
+  /* loop through netif's */
+  while (netif != NULL) {
+    /* only act on DHCP configured interfaces */
+    if (netif->dhcp != NULL) {
+      /* timer is active (non zero), and is about to trigger now */      
+      if (netif->dhcp->request_timeout > 1) {
+        netif->dhcp->request_timeout--;
+      }
+      else if (netif->dhcp->request_timeout == 1) {
+        netif->dhcp->request_timeout--;
+        /* { netif->dhcp->request_timeout == 0 } */
+        LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_fine_tmr(): request timeout\n"));
+        /* this client's request timeout triggered */
+        dhcp_timeout(netif);
+      }
+    }
+    /* proceed to next network interface */
+    netif = netif->next;
+  }
+}
+
+/**
+ * A DHCP negotiation transaction, or ARP request, has timed out.
+ *
+ * The timer that was started with the DHCP or ARP request has
+ * timed out, indicating no response was received in time.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout()\n"));
+  /* back-off period has passed, or server selection timed out */
+  if ((dhcp->state == DHCP_BACKING_OFF) || (dhcp->state == DHCP_SELECTING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout(): restarting discovery\n"));
+    dhcp_discover(netif);
+  /* receiving the requested lease timed out */
+  } else if (dhcp->state == DHCP_REQUESTING) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): REQUESTING, DHCP request timed out\n"));
+    if (dhcp->tries <= 5) {
+      dhcp_select(netif);
+    } else {
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): REQUESTING, releasing, restarting\n"));
+      dhcp_release(netif);
+      dhcp_discover(netif);
+    }
+#if DHCP_DOES_ARP_CHECK
+  /* received no ARP reply for the offered address (which is good) */
+  } else if (dhcp->state == DHCP_CHECKING) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): CHECKING, ARP request timed out\n"));
+    if (dhcp->tries <= 1) {
+      dhcp_check(netif);
+    /* no ARP replies on the offered address,
+       looks like the IP address is indeed free */
+    } else {
+      /* bind the interface to the offered address */
+      dhcp_bind(netif);
+    }
+#endif /* DHCP_DOES_ARP_CHECK */
+  }
+  /* did not get response to renew request? */
+  else if (dhcp->state == DHCP_RENEWING) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): RENEWING, DHCP request timed out\n"));
+    /* just retry renewal */
+    /* note that the rebind timer will eventually time-out if renew does not work */
+    dhcp_renew(netif);
+  /* did not get response to rebind request? */
+  } else if (dhcp->state == DHCP_REBINDING) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): REBINDING, DHCP request timed out\n"));
+    if (dhcp->tries <= 8) {
+      dhcp_rebind(netif);
+    } else {
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): RELEASING, DISCOVERING\n"));
+      dhcp_release(netif);
+      dhcp_discover(netif);
+    }
+  } else if (dhcp->state == DHCP_REBOOTING) {
+    if (dhcp->tries < REBOOT_TRIES) {
+      dhcp_reboot(netif);
+    } else {
+      dhcp_discover(netif);
+    }
+  }
+}
+
+/**
+ * The renewal period has timed out.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_t1_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_t1_timeout()\n"));
+  if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) ||
+      (dhcp->state == DHCP_RENEWING)) {
+    /* just retry to renew - note that the rebind timer (t2) will
+     * eventually time-out if renew tries fail. */
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+                ("dhcp_t1_timeout(): must renew\n"));
+    /* This slightly different to RFC2131: DHCPREQUEST will be sent from state
+       DHCP_RENEWING, not DHCP_BOUND */
+    dhcp_renew(netif);
+  }
+}
+
+/**
+ * The rebind period has timed out.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_t2_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_t2_timeout()\n"));
+  if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) ||
+      (dhcp->state == DHCP_RENEWING)) {
+    /* just retry to rebind */
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+                ("dhcp_t2_timeout(): must rebind\n"));
+    /* This slightly different to RFC2131: DHCPREQUEST will be sent from state
+       DHCP_REBINDING, not DHCP_BOUND */
+    dhcp_rebind(netif);
+  }
+}
+
+/**
+ * Handle a DHCP ACK packet
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_handle_ack(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+#if LWIP_DNS
+  u8_t n;
+#endif /* LWIP_DNS */
+
+  /* clear options we might not get from the ACK */
+  ip_addr_set_zero(&dhcp->offered_sn_mask);
+  ip_addr_set_zero(&dhcp->offered_gw_addr);
+#if LWIP_DHCP_BOOTP_FILE
+  ip_addr_set_zero(&dhcp->offered_si_addr);
+#endif /* LWIP_DHCP_BOOTP_FILE */
+
+  /* lease time given? */
+  if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_LEASE_TIME)) {
+    /* remember offered lease time */
+    dhcp->offered_t0_lease = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_LEASE_TIME);
+  }
+  /* renewal period given? */
+  if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_T1)) {
+    /* remember given renewal period */
+    dhcp->offered_t1_renew = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_T1);
+  } else {
+    /* calculate safe periods for renewal */
+    dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2;
+  }
+
+  /* renewal period given? */
+  if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_T2)) {
+    /* remember given rebind period */
+    dhcp->offered_t2_rebind = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_T2);
+  } else {
+    /* calculate safe periods for rebinding */
+    dhcp->offered_t2_rebind = dhcp->offered_t0_lease;
+  }
+
+  /* (y)our internet address */
+  ip_addr_copy(dhcp->offered_ip_addr, dhcp->msg_in->yiaddr);
+
+#if LWIP_DHCP_BOOTP_FILE
+  /* copy boot server address,
+     boot file name copied in dhcp_parse_reply if not overloaded */
+  ip_addr_copy(dhcp->offered_si_addr, dhcp->msg_in->siaddr);
+#endif /* LWIP_DHCP_BOOTP_FILE */
+
+  /* subnet mask given? */
+  if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_SUBNET_MASK)) {
+    /* remember given subnet mask */
+    ip4_addr_set_u32(&dhcp->offered_sn_mask, htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_SUBNET_MASK)));
+    dhcp->subnet_mask_given = 1;
+  } else {
+    dhcp->subnet_mask_given = 0;
+  }
+
+  /* gateway router */
+  if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_ROUTER)) {
+    ip4_addr_set_u32(&dhcp->offered_gw_addr, htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_ROUTER)));
+  }
+  
+#if LWIP_DNS
+  /* DNS servers */
+  n = 0;
+  while(dhcp_option_given(dhcp, DHCP_OPTION_IDX_DNS_SERVER + n) && (n < DNS_MAX_SERVERS)) {
+    ip_addr_t dns_addr;
+    ip4_addr_set_u32(&dns_addr, htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_DNS_SERVER + n)));
+    dns_setserver(n, &dns_addr);
+    n++;
+  }
+#endif /* LWIP_DNS */
+}
+
+/** Set a statically allocated struct dhcp to work with.
+ * Using this prevents dhcp_start to allocate it using mem_malloc.
+ *
+ * @param netif the netif for which to set the struct dhcp
+ * @param dhcp (uninitialised) dhcp struct allocated by the application
+ */
+void
+dhcp_set_struct(struct netif *netif, struct dhcp *dhcp)
+{
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+  LWIP_ASSERT("dhcp != NULL", dhcp != NULL);
+  LWIP_ASSERT("netif already has a struct dhcp set", netif->dhcp == NULL);
+
+  /* clear data structure */
+  memset(dhcp, 0, sizeof(struct dhcp));
+  /* dhcp_set_state(&dhcp, DHCP_OFF); */
+  netif->dhcp = dhcp;
+}
+
+/** Removes a struct dhcp from a netif.
+ *
+ * ATTENTION: Only use this when not using dhcp_set_struct() to allocate the
+ *            struct dhcp since the memory is passed back to the heap.
+ *
+ * @param netif the netif from which to remove the struct dhcp
+ */
+void dhcp_cleanup(struct netif *netif)
+{
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+
+  if (netif->dhcp != NULL) {
+    mem_free(netif->dhcp);
+    netif->dhcp = NULL;
+  }
+}
+
+/**
+ * Start DHCP negotiation for a network interface.
+ *
+ * If no DHCP client instance was attached to this interface,
+ * a new client is created first. If a DHCP client instance
+ * was already present, it restarts negotiation.
+ *
+ * @param netif The lwIP network interface
+ * @return lwIP error code
+ * - ERR_OK - No error
+ * - ERR_MEM - Out of memory
+ */
+err_t
+dhcp_start(struct netif *netif)
+{
+  struct dhcp *dhcp;
+  err_t result = ERR_OK;
+
+  LWIP_ERROR("netif != NULL", (netif != NULL), return ERR_ARG;);
+  dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+  /* Remove the flag that says this netif is handled by DHCP,
+     it is set when we succeeded starting. */
+  netif->flags &= ~NETIF_FLAG_DHCP;
+
+  /* check hwtype of the netif */
+  if ((netif->flags & NETIF_FLAG_ETHARP) == 0) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): No ETHARP netif\n"));
+    return ERR_ARG;
+  }
+
+  /* check MTU of the netif */
+  if (netif->mtu < DHCP_MAX_MSG_LEN_MIN_REQUIRED) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): Cannot use this netif with DHCP: MTU is too small\n"));
+    return ERR_MEM;
+  }
+
+  /* no DHCP client attached yet? */
+  if (dhcp == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): starting new DHCP client\n"));
+    dhcp = (struct dhcp *)mem_malloc(sizeof(struct dhcp));
+    if (dhcp == NULL) {
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n"));
+      return ERR_MEM;
+    }
+    /* store this dhcp client in the netif */
+    netif->dhcp = dhcp;
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): allocated dhcp"));
+  /* already has DHCP client attached */
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(): restarting DHCP configuration\n"));
+    if (dhcp->pcb != NULL) {
+      udp_remove(dhcp->pcb);
+    }
+    LWIP_ASSERT("pbuf p_out wasn't freed", dhcp->p_out == NULL);
+    LWIP_ASSERT("reply wasn't freed", dhcp->msg_in == NULL );
+  }
+    
+  /* clear data structure */
+  memset(dhcp, 0, sizeof(struct dhcp));
+  /* dhcp_set_state(&dhcp, DHCP_OFF); */
+  /* allocate UDP PCB */
+  dhcp->pcb = udp_new();
+  if (dhcp->pcb == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG  | LWIP_DBG_TRACE, ("dhcp_start(): could not obtain pcb\n"));
+    return ERR_MEM;
+  }
+  dhcp->pcb->so_options |= SOF_BROADCAST;
+  /* set up local and remote port for the pcb */
+  udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+  udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+  /* set up the recv callback and argument */
+  udp_recv(dhcp->pcb, dhcp_recv, netif);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n"));
+  /* (re)start the DHCP negotiation */
+  result = dhcp_discover(netif);
+  if (result != ERR_OK) {
+    /* free resources allocated above */
+    dhcp_stop(netif);
+    return ERR_MEM;
+  }
+  /* Set the flag that says this netif is handled by DHCP. */
+  netif->flags |= NETIF_FLAG_DHCP;
+  return result;
+}
+
+/**
+ * Inform a DHCP server of our manual configuration.
+ *
+ * This informs DHCP servers of our fixed IP address configuration
+ * by sending an INFORM message. It does not involve DHCP address
+ * configuration, it is just here to be nice to the network.
+ *
+ * @param netif The lwIP network interface
+ */
+void
+dhcp_inform(struct netif *netif)
+{
+  struct dhcp dhcp;
+  err_t result = ERR_OK;
+  struct udp_pcb *pcb;
+
+  LWIP_ERROR("netif != NULL", (netif != NULL), return;);
+
+  memset(&dhcp, 0, sizeof(struct dhcp));
+  dhcp_set_state(&dhcp, DHCP_INFORM);
+
+  if ((netif->dhcp != NULL) && (netif->dhcp->pcb != NULL)) {
+    /* re-use existing pcb */
+    pcb = netif->dhcp->pcb;
+  } else {
+    pcb = udp_new();
+    if (pcb == NULL) {
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_inform(): could not obtain pcb"));
+      return;
+    }
+    dhcp.pcb = pcb;
+    dhcp.pcb->so_options |= SOF_BROADCAST;
+    udp_bind(dhcp.pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_inform(): created new udp pcb\n"));
+  }
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_msg(netif, &dhcp, DHCP_INFORM);
+  if (result == ERR_OK) {
+    dhcp_option(&dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(&dhcp, DHCP_MAX_MSG_LEN(netif));
+
+    dhcp_option_trailer(&dhcp);
+
+    pbuf_realloc(dhcp.p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp.options_out_len);
+
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_inform: INFORMING\n"));
+    udp_sendto_if(pcb, dhcp.p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif);
+    dhcp_delete_msg(&dhcp);
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_inform: could not allocate DHCP request\n"));
+  }
+
+  if (dhcp.pcb != NULL) {
+    /* otherwise, the existing pcb was used */
+    udp_remove(dhcp.pcb);
+  }
+}
+
+/** Handle a possible change in the network configuration.
+ *
+ * This enters the REBOOTING state to verify that the currently bound
+ * address is still valid.
+ */
+void
+dhcp_network_changed(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  if (!dhcp)
+    return;
+  switch (dhcp->state) {
+  case DHCP_REBINDING:
+  case DHCP_RENEWING:
+  case DHCP_BOUND:
+  case DHCP_REBOOTING:
+    netif_set_down(netif);
+    dhcp->tries = 0;
+    dhcp_reboot(netif);
+    break;
+  case DHCP_OFF:
+    /* stay off */
+    break;
+  default:
+    dhcp->tries = 0;
+#if LWIP_DHCP_AUTOIP_COOP
+    if(dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_ON) {
+      autoip_stop(netif);
+      dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF;
+    }
+#endif /* LWIP_DHCP_AUTOIP_COOP */
+    dhcp_discover(netif);
+    break;
+  }
+}
+
+#if DHCP_DOES_ARP_CHECK
+/**
+ * Match an ARP reply with the offered IP address.
+ *
+ * @param netif the network interface on which the reply was received
+ * @param addr The IP address we received a reply from
+ */
+void dhcp_arp_reply(struct netif *netif, ip_addr_t *addr)
+{
+  LWIP_ERROR("netif != NULL", (netif != NULL), return;);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_arp_reply()\n"));
+  /* is a DHCP client doing an ARP check? */
+  if ((netif->dhcp != NULL) && (netif->dhcp->state == DHCP_CHECKING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08"X32_F"\n",
+      ip4_addr_get_u32(addr)));
+    /* did a host respond with the address we
+       were offered by the DHCP server? */
+    if (ip_addr_cmp(addr, &netif->dhcp->offered_ip_addr)) {
+      /* we will not accept the offered address */
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING,
+        ("dhcp_arp_reply(): arp reply matched with offered address, declining\n"));
+      dhcp_decline(netif);
+    }
+  }
+}
+
+/**
+ * Decline an offered lease.
+ *
+ * Tell the DHCP server we do not accept the offered address.
+ * One reason to decline the lease is when we find out the address
+ * is already in use by another host (through ARP).
+ *
+ * @param netif the netif under DHCP control
+ */
+static err_t
+dhcp_decline(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result = ERR_OK;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline()\n"));
+  dhcp_set_state(dhcp, DHCP_BACKING_OFF);
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_msg(netif, dhcp, DHCP_DECLINE);
+  if (result == ERR_OK) {
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr)));
+
+    dhcp_option_trailer(dhcp);
+    /* resize pbuf to reflect true size of options */
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    /* per section 4.4.4, broadcast DECLINE messages */
+    udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif);
+    dhcp_delete_msg(dhcp);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_decline: BACKING OFF\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
+      ("dhcp_decline: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = 10*1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+#endif /* DHCP_DOES_ARP_CHECK */
+
+
+/**
+ * Start the DHCP process, discover a DHCP server.
+ *
+ * @param netif the netif under DHCP control
+ */
+static err_t
+dhcp_discover(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result = ERR_OK;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover()\n"));
+  ip_addr_set_any(&dhcp->offered_ip_addr);
+  dhcp_set_state(dhcp, DHCP_SELECTING);
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_msg(netif, dhcp, DHCP_DISCOVER);
+  if (result == ERR_OK) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: making request\n"));
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif));
+
+    dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/);
+    dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK);
+    dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER);
+    dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST);
+    dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER);
+
+    dhcp_option_trailer(dhcp);
+
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: realloc()ing\n"));
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, DHCP_SERVER_PORT)\n"));
+    udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: deleting()ing\n"));
+    dhcp_delete_msg(dhcp);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover: SELECTING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_discover: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+#if LWIP_DHCP_AUTOIP_COOP
+  if(dhcp->tries >= LWIP_DHCP_AUTOIP_COOP_TRIES && dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_OFF) {
+    dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_ON;
+    autoip_start(netif);
+  }
+#endif /* LWIP_DHCP_AUTOIP_COOP */
+  msecs = (dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+
+/**
+ * Bind the interface to the offered IP address.
+ *
+ * @param netif network interface to bind to the offered address
+ */
+static void
+dhcp_bind(struct netif *netif)
+{
+  u32_t timeout;
+  struct dhcp *dhcp;
+  ip_addr_t sn_mask, gw_addr;
+  LWIP_ERROR("dhcp_bind: netif != NULL", (netif != NULL), return;);
+  dhcp = netif->dhcp;
+  LWIP_ERROR("dhcp_bind: dhcp != NULL", (dhcp != NULL), return;);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+
+  /* temporary DHCP lease? */
+  if (dhcp->offered_t1_renew != 0xffffffffUL) {
+    /* set renewal period timer */
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t1 renewal timer %"U32_F" secs\n", dhcp->offered_t1_renew));
+    timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
+    if(timeout > 0xffff) {
+      timeout = 0xffff;
+    }
+    dhcp->t1_timeout = (u16_t)timeout;
+    if (dhcp->t1_timeout == 0) {
+      dhcp->t1_timeout = 1;
+    }
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t1_renew*1000));
+  }
+  /* set renewal period timer */
+  if (dhcp->offered_t2_rebind != 0xffffffffUL) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t2 rebind timer %"U32_F" secs\n", dhcp->offered_t2_rebind));
+    timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
+    if(timeout > 0xffff) {
+      timeout = 0xffff;
+    }
+    dhcp->t2_timeout = (u16_t)timeout;
+    if (dhcp->t2_timeout == 0) {
+      dhcp->t2_timeout = 1;
+    }
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t2_rebind*1000));
+  }
+
+  if (dhcp->subnet_mask_given) {
+    /* copy offered network mask */
+    ip_addr_copy(sn_mask, dhcp->offered_sn_mask);
+  } else {
+    /* subnet mask not given, choose a safe subnet mask given the network class */
+    u8_t first_octet = ip4_addr1(&dhcp->offered_ip_addr);
+    if (first_octet <= 127) {
+      ip4_addr_set_u32(&sn_mask, PP_HTONL(0xff000000UL));
+    } else if (first_octet >= 192) {
+      ip4_addr_set_u32(&sn_mask, PP_HTONL(0xffffff00UL));
+    } else {
+      ip4_addr_set_u32(&sn_mask, PP_HTONL(0xffff0000UL));
+    }
+  }
+
+  ip_addr_copy(gw_addr, dhcp->offered_gw_addr);
+  /* gateway address not given? */
+  if (ip_addr_isany(&gw_addr)) {
+    /* copy network address */
+    ip_addr_get_network(&gw_addr, &dhcp->offered_ip_addr, &sn_mask);
+    /* use first host address on network as gateway */
+    ip4_addr_set_u32(&gw_addr, ip4_addr_get_u32(&gw_addr) | PP_HTONL(0x00000001UL));
+  }
+
+#if LWIP_DHCP_AUTOIP_COOP
+  if(dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_ON) {
+    autoip_stop(netif);
+    dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF;
+  }
+#endif /* LWIP_DHCP_AUTOIP_COOP */
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): IP: 0x%08"X32_F"\n",
+    ip4_addr_get_u32(&dhcp->offered_ip_addr)));
+  netif_set_ipaddr(netif, &dhcp->offered_ip_addr);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): SN: 0x%08"X32_F"\n",
+    ip4_addr_get_u32(&sn_mask)));
+  netif_set_netmask(netif, &sn_mask);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): GW: 0x%08"X32_F"\n",
+    ip4_addr_get_u32(&gw_addr)));
+  netif_set_gw(netif, &gw_addr);
+  /* bring the interface up */
+  netif_set_up(netif);
+  /* netif is now bound to DHCP leased address */
+  dhcp_set_state(dhcp, DHCP_BOUND);
+}
+
+/**
+ * Renew an existing DHCP lease at the involved DHCP server.
+ *
+ * @param netif network interface which must renew its lease
+ */
+err_t
+dhcp_renew(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_renew()\n"));
+  dhcp_set_state(dhcp, DHCP_RENEWING);
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_msg(netif, dhcp, DHCP_REQUEST);
+  if (result == ERR_OK) {
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif));
+
+#if LWIP_NETIF_HOSTNAME
+    if (netif->hostname != NULL) {
+      const char *p = (const char*)netif->hostname;
+      u8_t namelen = (u8_t)strlen(p);
+      if (namelen > 0) {
+        LWIP_ASSERT("DHCP: hostname is too long!", namelen < 255);
+        dhcp_option(dhcp, DHCP_OPTION_HOSTNAME, namelen);
+        while (*p) {
+          dhcp_option_byte(dhcp, *p++);
+        }
+      }
+    }
+#endif /* LWIP_NETIF_HOSTNAME */
+
+#if 0
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+#endif
+
+#if 0
+    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
+#endif
+    /* append DHCP message trailer */
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_sendto_if(dhcp->pcb, dhcp->p_out, &dhcp->server_ip_addr, DHCP_SERVER_PORT, netif);
+    dhcp_delete_msg(dhcp);
+
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew: RENEWING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_renew: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  /* back-off on retries, but to a maximum of 20 seconds */
+  msecs = dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+/**
+ * Rebind with a DHCP server for an existing DHCP lease.
+ *
+ * @param netif network interface which must rebind with a DHCP server
+ */
+static err_t
+dhcp_rebind(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind()\n"));
+  dhcp_set_state(dhcp, DHCP_REBINDING);
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_msg(netif, dhcp, DHCP_REQUEST);
+  if (result == ERR_OK) {
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif));
+
+#if LWIP_NETIF_HOSTNAME
+    if (netif->hostname != NULL) {
+      const char *p = (const char*)netif->hostname;
+      u8_t namelen = (u8_t)strlen(p);
+      if (namelen > 0) {
+        LWIP_ASSERT("DHCP: hostname is too long!", namelen < 255);
+        dhcp_option(dhcp, DHCP_OPTION_HOSTNAME, namelen);
+        while (*p) {
+          dhcp_option_byte(dhcp, *p++);
+        }
+      }
+    }
+#endif /* LWIP_NETIF_HOSTNAME */
+
+#if 0
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+
+    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
+#endif
+
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    /* broadcast to server */
+    udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif);
+    dhcp_delete_msg(dhcp);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind: REBINDING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_rebind: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+/**
+ * Enter REBOOTING state to verify an existing lease
+ *
+ * @param netif network interface which must reboot
+ */
+static err_t
+dhcp_reboot(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot()\n"));
+  dhcp_set_state(dhcp, DHCP_REBOOTING);
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_msg(netif, dhcp, DHCP_REQUEST);
+  if (result == ERR_OK) {
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, 576);
+
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr)));
+
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    /* broadcast to server */
+    udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif);
+    dhcp_delete_msg(dhcp);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot: REBOOTING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_reboot: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+
+/**
+ * Release a DHCP lease.
+ *
+ * @param netif network interface which must release its lease
+ */
+err_t
+dhcp_release(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_release()\n"));
+
+  /* idle DHCP client */
+  dhcp_set_state(dhcp, DHCP_OFF);
+  /* clean old DHCP offer */
+  ip_addr_set_zero(&dhcp->server_ip_addr);
+  ip_addr_set_zero(&dhcp->offered_ip_addr);
+  ip_addr_set_zero(&dhcp->offered_sn_mask);
+  ip_addr_set_zero(&dhcp->offered_gw_addr);
+#if LWIP_DHCP_BOOTP_FILE
+  ip_addr_set_zero(&dhcp->offered_si_addr);
+#endif /* LWIP_DHCP_BOOTP_FILE */
+  dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0;
+  
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_msg(netif, dhcp, DHCP_RELEASE);
+  if (result == ERR_OK) {
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_sendto_if(dhcp->pcb, dhcp->p_out, &dhcp->server_ip_addr, DHCP_SERVER_PORT, netif);
+    dhcp_delete_msg(dhcp);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_release: RELEASED, DHCP_OFF\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_release: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_release(): set request timeout %"U16_F" msecs\n", msecs));
+  /* bring the interface down */
+  netif_set_down(netif);
+  /* remove IP address from interface */
+  netif_set_ipaddr(netif, IP_ADDR_ANY);
+  netif_set_gw(netif, IP_ADDR_ANY);
+  netif_set_netmask(netif, IP_ADDR_ANY);
+  
+  return result;
+}
+
+/**
+ * Remove the DHCP client from the interface.
+ *
+ * @param netif The network interface to stop DHCP on
+ */
+void
+dhcp_stop(struct netif *netif)
+{
+  struct dhcp *dhcp;
+  LWIP_ERROR("dhcp_stop: netif != NULL", (netif != NULL), return;);
+  dhcp = netif->dhcp;
+  /* Remove the flag that says this netif is handled by DHCP. */
+  netif->flags &= ~NETIF_FLAG_DHCP;
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_stop()\n"));
+  /* netif is DHCP configured? */
+  if (dhcp != NULL) {
+#if LWIP_DHCP_AUTOIP_COOP
+    if(dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_ON) {
+      autoip_stop(netif);
+      dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF;
+    }
+#endif /* LWIP_DHCP_AUTOIP_COOP */
+
+    if (dhcp->pcb != NULL) {
+      udp_remove(dhcp->pcb);
+      dhcp->pcb = NULL;
+    }
+    LWIP_ASSERT("reply wasn't freed", dhcp->msg_in == NULL);
+    dhcp_set_state(dhcp, DHCP_OFF);
+  }
+}
+
+/*
+ * Set the DHCP state of a DHCP client.
+ *
+ * If the state changed, reset the number of tries.
+ */
+static void
+dhcp_set_state(struct dhcp *dhcp, u8_t new_state)
+{
+  if (new_state != dhcp->state) {
+    dhcp->state = new_state;
+    dhcp->tries = 0;
+    dhcp->request_timeout = 0;
+  }
+}
+
+/*
+ * Concatenate an option type and length field to the outgoing
+ * DHCP message.
+ *
+ */
+static void
+dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len)
+{
+  LWIP_ASSERT("dhcp_option: dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2U + option_len <= DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = option_type;
+  dhcp->msg_out->options[dhcp->options_out_len++] = option_len;
+}
+/*
+ * Concatenate a single byte to the outgoing DHCP message.
+ *
+ */
+static void
+dhcp_option_byte(struct dhcp *dhcp, u8_t value)
+{
+  LWIP_ASSERT("dhcp_option_byte: dhcp->options_out_len < DHCP_OPTIONS_LEN", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = value;
+}
+
+static void
+dhcp_option_short(struct dhcp *dhcp, u16_t value)
+{
+  LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2U <= DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0xff00U) >> 8);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t) (value & 0x00ffU);
+}
+
+static void
+dhcp_option_long(struct dhcp *dhcp, u32_t value)
+{
+  LWIP_ASSERT("dhcp_option_long: dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 4U <= DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0xff000000UL) >> 24);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0x00ff0000UL) >> 16);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0x0000ff00UL) >> 8);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0x000000ffUL));
+}
+
+/**
+ * Extract the DHCP message and the DHCP options.
+ *
+ * Extract the DHCP message and the DHCP options, each into a contiguous
+ * piece of memory. As a DHCP message is variable sized by its options,
+ * and also allows overriding some fields for options, the easy approach
+ * is to first unfold the options into a conitguous piece of memory, and
+ * use that further on.
+ *
+ */
+static err_t
+dhcp_parse_reply(struct dhcp *dhcp, struct pbuf *p)
+{
+  u8_t *options;
+  u16_t offset;
+  u16_t offset_max;
+  u16_t options_idx;
+  u16_t options_idx_max;
+  struct pbuf *q;
+  int parse_file_as_options = 0;
+  int parse_sname_as_options = 0;
+
+  /* clear received options */
+  dhcp_clear_all_options(dhcp);
+  /* check that beginning of dhcp_msg (up to and including chaddr) is in first pbuf */
+  if (p->len < DHCP_SNAME_OFS) {
+    return ERR_BUF;
+  }
+  dhcp->msg_in = (struct dhcp_msg *)p->payload;
+#if LWIP_DHCP_BOOTP_FILE
+  /* clear boot file name */
+  dhcp->boot_file_name[0] = 0;
+#endif /* LWIP_DHCP_BOOTP_FILE */
+
+  /* parse options */
+
+  /* start with options field */
+  options_idx = DHCP_OPTIONS_OFS;
+  /* parse options to the end of the received packet */
+  options_idx_max = p->tot_len;
+again:
+  q = p;
+  while((q != NULL) && (options_idx >= q->len)) {
+    options_idx -= q->len;
+    options_idx_max -= q->len;
+    q = q->next;
+  }
+  if (q == NULL) {
+    return ERR_BUF;
+  }
+  offset = options_idx;
+  offset_max = options_idx_max;
+  options = (u8_t*)q->payload;
+  /* at least 1 byte to read and no end marker, then at least 3 bytes to read? */
+  while((q != NULL) && (options[offset] != DHCP_OPTION_END) && (offset < offset_max)) {
+    u8_t op = options[offset];
+    u8_t len;
+    u8_t decode_len = 0;
+    int decode_idx = -1;
+    u16_t val_offset = offset + 2;
+    /* len byte might be in the next pbuf */
+    if (offset + 1 < q->len) {
+      len = options[offset + 1];
+    } else {
+      len = (q->next != NULL ? ((u8_t*)q->next->payload)[0] : 0);
+    }
+    /* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%"U16_F", q->len=%"U16_F, msg_offset, q->len)); */
+    decode_len = len;
+    switch(op) {
+      /* case(DHCP_OPTION_END): handled above */
+      case(DHCP_OPTION_PAD):
+        /* special option: no len encoded */
+        decode_len = len = 0;
+        /* will be increased below */
+        offset--;
+        break;
+      case(DHCP_OPTION_SUBNET_MASK):
+        LWIP_ASSERT("len == 4", len == 4);
+        decode_idx = DHCP_OPTION_IDX_SUBNET_MASK;
+        break;
+      case(DHCP_OPTION_ROUTER):
+        decode_len = 4; /* only copy the first given router */
+        LWIP_ASSERT("len >= decode_len", len >= decode_len);
+        decode_idx = DHCP_OPTION_IDX_ROUTER;
+        break;
+      case(DHCP_OPTION_DNS_SERVER):
+        /* special case: there might be more than one server */
+        LWIP_ASSERT("len % 4 == 0", len % 4 == 0);
+        /* limit number of DNS servers */
+        decode_len = LWIP_MIN(len, 4 * DNS_MAX_SERVERS);
+        LWIP_ASSERT("len >= decode_len", len >= decode_len);
+        decode_idx = DHCP_OPTION_IDX_DNS_SERVER;
+        break;
+      case(DHCP_OPTION_LEASE_TIME):
+        LWIP_ASSERT("len == 4", len == 4);
+        decode_idx = DHCP_OPTION_IDX_LEASE_TIME;
+        break;
+      case(DHCP_OPTION_OVERLOAD):
+        LWIP_ASSERT("len == 1", len == 1);
+        decode_idx = DHCP_OPTION_IDX_OVERLOAD;
+        break;
+      case(DHCP_OPTION_MESSAGE_TYPE):
+        LWIP_ASSERT("len == 1", len == 1);
+        decode_idx = DHCP_OPTION_IDX_MSG_TYPE;
+        break;
+      case(DHCP_OPTION_SERVER_ID):
+        LWIP_ASSERT("len == 4", len == 4);
+        decode_idx = DHCP_OPTION_IDX_SERVER_ID;
+        break;
+      case(DHCP_OPTION_T1):
+        LWIP_ASSERT("len == 4", len == 4);
+        decode_idx = DHCP_OPTION_IDX_T1;
+        break;
+      case(DHCP_OPTION_T2):
+        LWIP_ASSERT("len == 4", len == 4);
+        decode_idx = DHCP_OPTION_IDX_T2;
+        break;
+      default:
+        decode_len = 0;
+        LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %"U16_F" in options\n", op));
+        break;
+    }
+    offset += len + 2;
+    if (decode_len > 0) {
+      u32_t value = 0;
+      u16_t copy_len;
+decode_next:
+      LWIP_ASSERT("check decode_idx", decode_idx >= 0 && decode_idx < DHCP_OPTION_IDX_MAX);
+      LWIP_ASSERT("option already decoded", !dhcp_option_given(dhcp, decode_idx));
+      copy_len = LWIP_MIN(decode_len, 4);
+      pbuf_copy_partial(q, &value, copy_len, val_offset);
+      if (decode_len > 4) {
+        /* decode more than one u32_t */
+        LWIP_ASSERT("decode_len % 4 == 0", decode_len % 4 == 0);
+        dhcp_got_option(dhcp, decode_idx);
+        dhcp_set_option_value(dhcp, decode_idx, htonl(value));
+        decode_len -= 4;
+        val_offset += 4;
+        decode_idx++;
+        goto decode_next;
+      } else if (decode_len == 4) {
+        value = ntohl(value);
+      } else {
+        LWIP_ASSERT("invalid decode_len", decode_len == 1);
+        value = ((u8_t*)&value)[0];
+      }
+      dhcp_got_option(dhcp, decode_idx);
+      dhcp_set_option_value(dhcp, decode_idx, value);
+    }
+    if (offset >= q->len) {
+      offset -= q->len;
+      offset_max -= q->len;
+      q = q->next;
+      options = (u8_t*)q->payload;
+    }
+  }
+  /* is this an overloaded message? */
+  if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_OVERLOAD)) {
+    u32_t overload = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_OVERLOAD);
+    dhcp_clear_option(dhcp, DHCP_OPTION_IDX_OVERLOAD);
+    if (overload == DHCP_OVERLOAD_FILE) {
+      parse_file_as_options = 1;
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded file field\n"));
+    } else if (overload == DHCP_OVERLOAD_SNAME) {
+      parse_sname_as_options = 1;
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname field\n"));
+    } else if (overload == DHCP_OVERLOAD_SNAME_FILE) {
+      parse_sname_as_options = 1;
+      parse_file_as_options = 1;
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname and file field\n"));
+    } else {
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("invalid overload option: %d\n", (int)overload));
+    }
+#if LWIP_DHCP_BOOTP_FILE
+    if (!parse_file_as_options) {
+      /* only do this for ACK messages */
+      if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE) &&
+        (dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE) == DHCP_ACK))
+      /* copy bootp file name, don't care for sname (server hostname) */
+      pbuf_copy_partial(p, dhcp->boot_file_name, DHCP_FILE_LEN-1, DHCP_FILE_OFS);
+      /* make sure the string is really NULL-terminated */
+      dhcp->boot_file_name[DHCP_FILE_LEN-1] = 0;
+    }
+#endif /* LWIP_DHCP_BOOTP_FILE */
+  }
+  if (parse_file_as_options) {
+    /* if both are overloaded, parse file first and then sname (RFC 2131 ch. 4.1) */
+    parse_file_as_options = 0;
+    options_idx = DHCP_FILE_OFS;
+    options_idx_max = DHCP_FILE_OFS + DHCP_FILE_LEN;
+    goto again;
+  } else if (parse_sname_as_options) {
+    parse_sname_as_options = 0;
+    options_idx = DHCP_SNAME_OFS;
+    options_idx_max = DHCP_SNAME_OFS + DHCP_SNAME_LEN;
+    goto again;
+  }
+  return ERR_OK;
+}
+
+/**
+ * If an incoming DHCP message is in response to us, then trigger the state machine
+ */
+static void
+dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, ip_addr_t *addr, u16_t port)
+{
+  struct netif *netif = (struct netif *)arg;
+  struct dhcp *dhcp = netif->dhcp;
+  struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload;
+  u8_t msg_type;
+  u8_t i;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_recv(pbuf = %p) from DHCP server %"U16_F".%"U16_F".%"U16_F".%"U16_F" port %"U16_F"\n", (void*)p,
+    ip4_addr1_16(addr), ip4_addr2_16(addr), ip4_addr3_16(addr), ip4_addr4_16(addr), port));
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("pbuf->len = %"U16_F"\n", p->len));
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("pbuf->tot_len = %"U16_F"\n", p->tot_len));
+  /* prevent warnings about unused arguments */
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_UNUSED_ARG(addr);
+  LWIP_UNUSED_ARG(port);
+
+  LWIP_ASSERT("reply wasn't freed", dhcp->msg_in == NULL);
+
+  if (p->len < DHCP_MIN_REPLY_LEN) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP reply message or pbuf too short\n"));
+    goto free_pbuf_and_return;
+  }
+
+  if (reply_msg->op != DHCP_BOOTREPLY) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("not a DHCP reply message, but type %"U16_F"\n", (u16_t)reply_msg->op));
+    goto free_pbuf_and_return;
+  }
+  /* iterate through hardware address and match against DHCP message */
+  for (i = 0; i < netif->hwaddr_len; i++) {
+    if (netif->hwaddr[i] != reply_msg->chaddr[i]) {
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
+        ("netif->hwaddr[%"U16_F"]==%02"X16_F" != reply_msg->chaddr[%"U16_F"]==%02"X16_F"\n",
+        (u16_t)i, (u16_t)netif->hwaddr[i], (u16_t)i, (u16_t)reply_msg->chaddr[i]));
+      goto free_pbuf_and_return;
+    }
+  }
+  /* match transaction ID against what we expected */
+  if (ntohl(reply_msg->xid) != dhcp->xid) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
+      ("transaction id mismatch reply_msg->xid(%"X32_F")!=dhcp->xid(%"X32_F")\n",ntohl(reply_msg->xid),dhcp->xid));
+    goto free_pbuf_and_return;
+  }
+  /* option fields could be unfold? */
+  if (dhcp_parse_reply(dhcp, p) != ERR_OK) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
+      ("problem unfolding DHCP message - too short on memory?\n"));
+    goto free_pbuf_and_return;
+  }
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n"));
+  /* obtain pointer to DHCP message type */
+  if (!dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE)) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP_OPTION_MESSAGE_TYPE option not found\n"));
+    goto free_pbuf_and_return;
+  }
+
+  /* read DHCP message type */
+  msg_type = (u8_t)dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE);
+  /* message type is DHCP ACK? */
+  if (msg_type == DHCP_ACK) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_ACK received\n"));
+    /* in requesting state? */
+    if (dhcp->state == DHCP_REQUESTING) {
+      dhcp_handle_ack(netif);
+#if DHCP_DOES_ARP_CHECK
+      /* check if the acknowledged lease address is already in use */
+      dhcp_check(netif);
+#else
+      /* bind interface to the acknowledged lease address */
+      dhcp_bind(netif);
+#endif
+    }
+    /* already bound to the given lease address? */
+    else if ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING)) {
+      dhcp_bind(netif);
+    }
+  }
+  /* received a DHCP_NAK in appropriate state? */
+  else if ((msg_type == DHCP_NAK) &&
+    ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REQUESTING) ||
+     (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING  ))) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_NAK received\n"));
+    dhcp_handle_nak(netif);
+  }
+  /* received a DHCP_OFFER in DHCP_SELECTING state? */
+  else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_SELECTING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_OFFER received in DHCP_SELECTING state\n"));
+    dhcp->request_timeout = 0;
+    /* remember offered lease */
+    dhcp_handle_offer(netif);
+  }
+free_pbuf_and_return:
+  dhcp->msg_in = NULL;
+  pbuf_free(p);
+}
+
+/**
+ * Create a DHCP request, fill in common headers
+ *
+ * @param netif the netif under DHCP control
+ * @param dhcp dhcp control struct
+ * @param message_type message type of the request
+ */
+static err_t
+dhcp_create_msg(struct netif *netif, struct dhcp *dhcp, u8_t message_type)
+{
+  u16_t i;
+#ifndef DHCP_GLOBAL_XID
+  /** default global transaction identifier starting value (easy to match
+   *  with a packet analyser). We simply increment for each new request.
+   *  Predefine DHCP_GLOBAL_XID to a better value or a function call to generate one
+   *  at runtime, any supporting function prototypes can be defined in DHCP_GLOBAL_XID_HEADER */
+  static u32_t xid = 0xABCD0000;
+#else
+  static u32_t xid;
+  static u8_t xid_initialised = 0;
+  if (!xid_initialised) {
+    xid = DHCP_GLOBAL_XID;
+    xid_initialised = !xid_initialised;
+  }
+#endif
+  LWIP_ERROR("dhcp_create_msg: netif != NULL", (netif != NULL), return ERR_ARG;);
+  LWIP_ERROR("dhcp_create_msg: dhcp != NULL", (dhcp != NULL), return ERR_VAL;);
+  LWIP_ASSERT("dhcp_create_msg: dhcp->p_out == NULL", dhcp->p_out == NULL);
+  LWIP_ASSERT("dhcp_create_msg: dhcp->msg_out == NULL", dhcp->msg_out == NULL);
+  dhcp->p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM);
+  if (dhcp->p_out == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
+      ("dhcp_create_msg(): could not allocate pbuf\n"));
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("dhcp_create_msg: check that first pbuf can hold struct dhcp_msg",
+           (dhcp->p_out->len >= sizeof(struct dhcp_msg)));
+
+  /* reuse transaction identifier in retransmissions */
+  if (dhcp->tries == 0) {
+      xid++;
+  }
+  dhcp->xid = xid;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE,
+              ("transaction id xid(%"X32_F")\n", xid));
+
+  dhcp->msg_out = (struct dhcp_msg *)dhcp->p_out->payload;
+
+  dhcp->msg_out->op = DHCP_BOOTREQUEST;
+  /* TODO: make link layer independent */
+  dhcp->msg_out->htype = DHCP_HTYPE_ETH;
+  dhcp->msg_out->hlen = netif->hwaddr_len;
+  dhcp->msg_out->hops = 0;
+  dhcp->msg_out->xid = htonl(dhcp->xid);
+  dhcp->msg_out->secs = 0;
+  /* we don't need the broadcast flag since we can receive unicast traffic
+     before being fully configured! */
+  dhcp->msg_out->flags = 0;
+  ip_addr_set_zero(&dhcp->msg_out->ciaddr);
+  /* set ciaddr to netif->ip_addr based on message_type and state */
+  if ((message_type == DHCP_INFORM) || (message_type == DHCP_DECLINE) ||
+      ((message_type == DHCP_REQUEST) && /* DHCP_BOUND not used for sending! */
+       ((dhcp->state==DHCP_RENEWING) || dhcp->state==DHCP_REBINDING))) {
+    ip_addr_copy(dhcp->msg_out->ciaddr, netif->ip_addr);
+  }
+  ip_addr_set_zero(&dhcp->msg_out->yiaddr);
+  ip_addr_set_zero(&dhcp->msg_out->siaddr);
+  ip_addr_set_zero(&dhcp->msg_out->giaddr);
+  for (i = 0; i < DHCP_CHADDR_LEN; i++) {
+    /* copy netif hardware address, pad with zeroes */
+    dhcp->msg_out->chaddr[i] = (i < netif->hwaddr_len) ? netif->hwaddr[i] : 0/* pad byte*/;
+  }
+  for (i = 0; i < DHCP_SNAME_LEN; i++) {
+    dhcp->msg_out->sname[i] = 0;
+  }
+  for (i = 0; i < DHCP_FILE_LEN; i++) {
+    dhcp->msg_out->file[i] = 0;
+  }
+  dhcp->msg_out->cookie = PP_HTONL(DHCP_MAGIC_COOKIE);
+  dhcp->options_out_len = 0;
+  /* fill options field with an incrementing array (for debugging purposes) */
+  for (i = 0; i < DHCP_OPTIONS_LEN; i++) {
+    dhcp->msg_out->options[i] = (u8_t)i; /* for debugging only, no matter if truncated */
+  }
+  /* Add option MESSAGE_TYPE */
+  dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+  dhcp_option_byte(dhcp, message_type);
+  return ERR_OK;
+}
+
+/**
+ * Free previously allocated memory used to send a DHCP request.
+ *
+ * @param dhcp the dhcp struct to free the request from
+ */
+static void
+dhcp_delete_msg(struct dhcp *dhcp)
+{
+  LWIP_ERROR("dhcp_delete_msg: dhcp != NULL", (dhcp != NULL), return;);
+  LWIP_ASSERT("dhcp_delete_msg: dhcp->p_out != NULL", dhcp->p_out != NULL);
+  LWIP_ASSERT("dhcp_delete_msg: dhcp->msg_out != NULL", dhcp->msg_out != NULL);
+  if (dhcp->p_out != NULL) {
+    pbuf_free(dhcp->p_out);
+  }
+  dhcp->p_out = NULL;
+  dhcp->msg_out = NULL;
+}
+
+/**
+ * Add a DHCP message trailer
+ *
+ * Adds the END option to the DHCP message, and if
+ * necessary, up to three padding bytes.
+ *
+ * @param dhcp DHCP state structure
+ */
+static void
+dhcp_option_trailer(struct dhcp *dhcp)
+{
+  LWIP_ERROR("dhcp_option_trailer: dhcp != NULL", (dhcp != NULL), return;);
+  LWIP_ASSERT("dhcp_option_trailer: dhcp->msg_out != NULL\n", dhcp->msg_out != NULL);
+  LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = DHCP_OPTION_END;
+  /* packet is too small, or not 4 byte aligned? */
+  while ((dhcp->options_out_len < DHCP_MIN_OPTIONS_LEN) || (dhcp->options_out_len & 3)) {
+    /* LWIP_DEBUGF(DHCP_DEBUG,("dhcp_option_trailer:dhcp->options_out_len=%"U16_F", DHCP_OPTIONS_LEN=%"U16_F, dhcp->options_out_len, DHCP_OPTIONS_LEN)); */
+    LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+    /* add a fill/padding byte */
+    dhcp->msg_out->options[dhcp->options_out_len++] = 0;
+  }
+}
+
+#endif /* LWIP_DHCP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/dns.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/dns.c
new file mode 100644
index 0000000..d633612
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/dns.c
@@ -0,0 +1,970 @@
+/**
+ * @file
+ * DNS - host name to IP address resolver.
+ *
+ */
+
+/**
+
+ * This file implements a DNS host name to IP address resolver.
+
+ * Port to lwIP from uIP
+ * by Jim Pettinato April 2007
+
+ * uIP version Copyright (c) 2002-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * DNS.C
+ *
+ * The lwIP DNS resolver functions are used to lookup a host name and
+ * map it to a numerical IP address. It maintains a list of resolved
+ * hostnames that can be queried with the dns_lookup() function.
+ * New hostnames can be resolved using the dns_query() function.
+ *
+ * The lwIP version of the resolver also adds a non-blocking version of
+ * gethostbyname() that will work with a raw API application. This function
+ * checks for an IP address string first and converts it if it is valid.
+ * gethostbyname() then does a dns_lookup() to see if the name is 
+ * already in the table. If so, the IP is returned. If not, a query is 
+ * issued and the function returns with a ERR_INPROGRESS status. The app
+ * using the dns client must then go into a waiting state.
+ *
+ * Once a hostname has been resolved (or found to be non-existent),
+ * the resolver code calls a specified callback function (which 
+ * must be implemented by the module that uses the resolver).
+ */
+
+/*-----------------------------------------------------------------------------
+ * RFC 1035 - Domain names - implementation and specification
+ * RFC 2181 - Clarifications to the DNS Specification
+ *----------------------------------------------------------------------------*/
+
+/** @todo: define good default values (rfc compliance) */
+/** @todo: improve answer parsing, more checkings... */
+/** @todo: check RFC1035 - 7.3. Processing responses */
+
+/*-----------------------------------------------------------------------------
+ * Includes
+ *----------------------------------------------------------------------------*/
+
+#include "lwip/opt.h"
+
+#if LWIP_DNS /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/udp.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/dns.h"
+
+#include 
+
+/** DNS server IP address */
+#ifndef DNS_SERVER_ADDRESS
+#define DNS_SERVER_ADDRESS(ipaddr)        (ip4_addr_set_u32(ipaddr, ipaddr_addr("208.67.222.222"))) /* resolver1.opendns.com */
+#endif
+
+/** DNS server port address */
+#ifndef DNS_SERVER_PORT
+#define DNS_SERVER_PORT           53
+#endif
+
+/** DNS maximum number of retries when asking for a name, before "timeout". */
+#ifndef DNS_MAX_RETRIES
+#define DNS_MAX_RETRIES           4
+#endif
+
+/** DNS resource record max. TTL (one week as default) */
+#ifndef DNS_MAX_TTL
+#define DNS_MAX_TTL               604800
+#endif
+
+/* DNS protocol flags */
+#define DNS_FLAG1_RESPONSE        0x80
+#define DNS_FLAG1_OPCODE_STATUS   0x10
+#define DNS_FLAG1_OPCODE_INVERSE  0x08
+#define DNS_FLAG1_OPCODE_STANDARD 0x00
+#define DNS_FLAG1_AUTHORATIVE     0x04
+#define DNS_FLAG1_TRUNC           0x02
+#define DNS_FLAG1_RD              0x01
+#define DNS_FLAG2_RA              0x80
+#define DNS_FLAG2_ERR_MASK        0x0f
+#define DNS_FLAG2_ERR_NONE        0x00
+#define DNS_FLAG2_ERR_NAME        0x03
+
+/* DNS protocol states */
+#define DNS_STATE_UNUSED          0
+#define DNS_STATE_NEW             1
+#define DNS_STATE_ASKING          2
+#define DNS_STATE_DONE            3
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** DNS message header */
+struct dns_hdr {
+  PACK_STRUCT_FIELD(u16_t id);
+  PACK_STRUCT_FIELD(u8_t flags1);
+  PACK_STRUCT_FIELD(u8_t flags2);
+  PACK_STRUCT_FIELD(u16_t numquestions);
+  PACK_STRUCT_FIELD(u16_t numanswers);
+  PACK_STRUCT_FIELD(u16_t numauthrr);
+  PACK_STRUCT_FIELD(u16_t numextrarr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+#define SIZEOF_DNS_HDR 12
+
+/** DNS query message structure.
+    No packing needed: only used locally on the stack. */
+struct dns_query {
+  /* DNS query record starts with either a domain name or a pointer
+     to a name already present somewhere in the packet. */
+  u16_t type;
+  u16_t cls;
+};
+#define SIZEOF_DNS_QUERY 4
+
+/** DNS answer message structure.
+    No packing needed: only used locally on the stack. */
+struct dns_answer {
+  /* DNS answer record starts with either a domain name or a pointer
+     to a name already present somewhere in the packet. */
+  u16_t type;
+  u16_t cls;
+  u32_t ttl;
+  u16_t len;
+};
+#define SIZEOF_DNS_ANSWER 10
+
+/** DNS table entry */
+struct dns_table_entry {
+  u8_t  state;
+  u8_t  numdns;
+  u8_t  tmr;
+  u8_t  retries;
+  u8_t  seqno;
+  u8_t  err;
+  u32_t ttl;
+  char name[DNS_MAX_NAME_LENGTH];
+  ip_addr_t ipaddr;
+  /* pointer to callback on DNS query done */
+  dns_found_callback found;
+  void *arg;
+};
+
+#if DNS_LOCAL_HOSTLIST
+
+#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+/** Local host-list. For hostnames in this list, no
+ *  external name resolution is performed */
+static struct local_hostlist_entry *local_hostlist_dynamic;
+#else /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+
+/** Defining this allows the local_hostlist_static to be placed in a different
+ * linker section (e.g. FLASH) */
+#ifndef DNS_LOCAL_HOSTLIST_STORAGE_PRE
+#define DNS_LOCAL_HOSTLIST_STORAGE_PRE static
+#endif /* DNS_LOCAL_HOSTLIST_STORAGE_PRE */
+/** Defining this allows the local_hostlist_static to be placed in a different
+ * linker section (e.g. FLASH) */
+#ifndef DNS_LOCAL_HOSTLIST_STORAGE_POST
+#define DNS_LOCAL_HOSTLIST_STORAGE_POST
+#endif /* DNS_LOCAL_HOSTLIST_STORAGE_POST */
+DNS_LOCAL_HOSTLIST_STORAGE_PRE struct local_hostlist_entry local_hostlist_static[]
+  DNS_LOCAL_HOSTLIST_STORAGE_POST = DNS_LOCAL_HOSTLIST_INIT;
+
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+
+static void dns_init_local();
+#endif /* DNS_LOCAL_HOSTLIST */
+
+
+/* forward declarations */
+static void dns_recv(void *s, struct udp_pcb *pcb, struct pbuf *p, ip_addr_t *addr, u16_t port);
+static void dns_check_entries(void);
+
+/*-----------------------------------------------------------------------------
+ * Globales
+ *----------------------------------------------------------------------------*/
+
+/* DNS variables */
+static struct udp_pcb        *dns_pcb;
+static u8_t                   dns_seqno;
+static struct dns_table_entry dns_table[DNS_TABLE_SIZE];
+static ip_addr_t              dns_servers[DNS_MAX_SERVERS];
+/** Contiguous buffer for processing responses */
+static u8_t                   dns_payload_buffer[LWIP_MEM_ALIGN_BUFFER(DNS_MSG_SIZE)];
+static u8_t*                  dns_payload;
+
+/**
+ * Initialize the resolver: set up the UDP pcb and configure the default server
+ * (DNS_SERVER_ADDRESS).
+ */
+void
+dns_init()
+{
+  ip_addr_t dnsserver;
+
+  dns_payload = (u8_t *)LWIP_MEM_ALIGN(dns_payload_buffer);
+  
+  /* initialize default DNS server address */
+  DNS_SERVER_ADDRESS(&dnsserver);
+
+  LWIP_DEBUGF(DNS_DEBUG, ("dns_init: initializing\n"));
+
+  /* if dns client not yet initialized... */
+  if (dns_pcb == NULL) {
+    dns_pcb = udp_new();
+
+    if (dns_pcb != NULL) {
+      /* initialize DNS table not needed (initialized to zero since it is a
+       * global variable) */
+      LWIP_ASSERT("For implicit initialization to work, DNS_STATE_UNUSED needs to be 0",
+        DNS_STATE_UNUSED == 0);
+
+      /* initialize DNS client */
+      udp_bind(dns_pcb, IP_ADDR_ANY, 0);
+      udp_recv(dns_pcb, dns_recv, NULL);
+
+      /* initialize default DNS primary server */
+      dns_setserver(0, &dnsserver);
+    }
+  }
+#if DNS_LOCAL_HOSTLIST
+  dns_init_local();
+#endif
+}
+
+/**
+ * Initialize one of the DNS servers.
+ *
+ * @param numdns the index of the DNS server to set must be < DNS_MAX_SERVERS
+ * @param dnsserver IP address of the DNS server to set
+ */
+void
+dns_setserver(u8_t numdns, ip_addr_t *dnsserver)
+{
+  if ((numdns < DNS_MAX_SERVERS) && (dns_pcb != NULL) &&
+      (dnsserver != NULL) && !ip_addr_isany(dnsserver)) {
+    dns_servers[numdns] = (*dnsserver);
+  }
+}
+
+/**
+ * Obtain one of the currently configured DNS server.
+ *
+ * @param numdns the index of the DNS server
+ * @return IP address of the indexed DNS server or "ip_addr_any" if the DNS
+ *         server has not been configured.
+ */
+ip_addr_t
+dns_getserver(u8_t numdns)
+{
+  if (numdns < DNS_MAX_SERVERS) {
+    return dns_servers[numdns];
+  } else {
+    return *IP_ADDR_ANY;
+  }
+}
+
+/**
+ * The DNS resolver client timer - handle retries and timeouts and should
+ * be called every DNS_TMR_INTERVAL milliseconds (every second by default).
+ */
+void
+dns_tmr(void)
+{
+  if (dns_pcb != NULL) {
+    LWIP_DEBUGF(DNS_DEBUG, ("dns_tmr: dns_check_entries\n"));
+    dns_check_entries();
+  }
+}
+
+#if DNS_LOCAL_HOSTLIST
+static void
+dns_init_local()
+{
+#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC && defined(DNS_LOCAL_HOSTLIST_INIT)
+  int i;
+  struct local_hostlist_entry *entry;
+  /* Dynamic: copy entries from DNS_LOCAL_HOSTLIST_INIT to list */
+  struct local_hostlist_entry local_hostlist_init[] = DNS_LOCAL_HOSTLIST_INIT;
+  size_t namelen;
+  for (i = 0; i < sizeof(local_hostlist_init) / sizeof(struct local_hostlist_entry); i++) {
+    struct local_hostlist_entry *init_entry = &local_hostlist_init[i];
+    LWIP_ASSERT("invalid host name (NULL)", init_entry->name != NULL);
+    namelen = strlen(init_entry->name);
+    LWIP_ASSERT("namelen <= DNS_LOCAL_HOSTLIST_MAX_NAMELEN", namelen <= DNS_LOCAL_HOSTLIST_MAX_NAMELEN);
+    entry = (struct local_hostlist_entry *)memp_malloc(MEMP_LOCALHOSTLIST);
+    LWIP_ASSERT("mem-error in dns_init_local", entry != NULL);
+    if (entry != NULL) {
+      entry->name = (char*)entry + sizeof(struct local_hostlist_entry);
+      MEMCPY((char*)entry->name, init_entry->name, namelen);
+      ((char*)entry->name)[namelen] = 0;
+      entry->addr = init_entry->addr;
+      entry->next = local_hostlist_dynamic;
+      local_hostlist_dynamic = entry;
+    }
+  }
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC && defined(DNS_LOCAL_HOSTLIST_INIT) */
+}
+
+/**
+ * Scans the local host-list for a hostname.
+ *
+ * @param hostname Hostname to look for in the local host-list
+ * @return The first IP address for the hostname in the local host-list or
+ *         IPADDR_NONE if not found.
+ */
+static u32_t
+dns_lookup_local(const char *hostname)
+{
+#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+  struct local_hostlist_entry *entry = local_hostlist_dynamic;
+  while(entry != NULL) {
+    if(strcmp(entry->name, hostname) == 0) {
+      return ip4_addr_get_u32(&entry->addr);
+    }
+    entry = entry->next;
+  }
+#else /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+  int i;
+  for (i = 0; i < sizeof(local_hostlist_static) / sizeof(struct local_hostlist_entry); i++) {
+    if(strcmp(local_hostlist_static[i].name, hostname) == 0) {
+      return ip4_addr_get_u32(&local_hostlist_static[i].addr);
+    }
+  }
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+  return IPADDR_NONE;
+}
+
+#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+/** Remove all entries from the local host-list for a specific hostname
+ * and/or IP addess
+ *
+ * @param hostname hostname for which entries shall be removed from the local
+ *                 host-list
+ * @param addr address for which entries shall be removed from the local host-list
+ * @return the number of removed entries
+ */
+int
+dns_local_removehost(const char *hostname, const ip_addr_t *addr)
+{
+  int removed = 0;
+  struct local_hostlist_entry *entry = local_hostlist_dynamic;
+  struct local_hostlist_entry *last_entry = NULL;
+  while (entry != NULL) {
+    if (((hostname == NULL) || !strcmp(entry->name, hostname)) &&
+        ((addr == NULL) || ip_addr_cmp(&entry->addr, addr))) {
+      struct local_hostlist_entry *free_entry;
+      if (last_entry != NULL) {
+        last_entry->next = entry->next;
+      } else {
+        local_hostlist_dynamic = entry->next;
+      }
+      free_entry = entry;
+      entry = entry->next;
+      memp_free(MEMP_LOCALHOSTLIST, free_entry);
+      removed++;
+    } else {
+      last_entry = entry;
+      entry = entry->next;
+    }
+  }
+  return removed;
+}
+
+/**
+ * Add a hostname/IP address pair to the local host-list.
+ * Duplicates are not checked.
+ *
+ * @param hostname hostname of the new entry
+ * @param addr IP address of the new entry
+ * @return ERR_OK if succeeded or ERR_MEM on memory error
+ */
+err_t
+dns_local_addhost(const char *hostname, const ip_addr_t *addr)
+{
+  struct local_hostlist_entry *entry;
+  size_t namelen;
+  LWIP_ASSERT("invalid host name (NULL)", hostname != NULL);
+  namelen = strlen(hostname);
+  LWIP_ASSERT("namelen <= DNS_LOCAL_HOSTLIST_MAX_NAMELEN", namelen <= DNS_LOCAL_HOSTLIST_MAX_NAMELEN);
+  entry = (struct local_hostlist_entry *)memp_malloc(MEMP_LOCALHOSTLIST);
+  if (entry == NULL) {
+    return ERR_MEM;
+  }
+  entry->name = (char*)entry + sizeof(struct local_hostlist_entry);
+  MEMCPY((char*)entry->name, hostname, namelen);
+  ((char*)entry->name)[namelen] = 0;
+  ip_addr_copy(entry->addr, *addr);
+  entry->next = local_hostlist_dynamic;
+  local_hostlist_dynamic = entry;
+  return ERR_OK;
+}
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC*/
+#endif /* DNS_LOCAL_HOSTLIST */
+
+/**
+ * Look up a hostname in the array of known hostnames.
+ *
+ * @note This function only looks in the internal array of known
+ * hostnames, it does not send out a query for the hostname if none
+ * was found. The function dns_enqueue() can be used to send a query
+ * for a hostname.
+ *
+ * @param name the hostname to look up
+ * @return the hostname's IP address, as u32_t (instead of ip_addr_t to
+ *         better check for failure: != IPADDR_NONE) or IPADDR_NONE if the hostname
+ *         was not found in the cached dns_table.
+ */
+static u32_t
+dns_lookup(const char *name)
+{
+  u8_t i;
+#if DNS_LOCAL_HOSTLIST || defined(DNS_LOOKUP_LOCAL_EXTERN)
+  u32_t addr;
+#endif /* DNS_LOCAL_HOSTLIST || defined(DNS_LOOKUP_LOCAL_EXTERN) */
+#if DNS_LOCAL_HOSTLIST
+  if ((addr = dns_lookup_local(name)) != IPADDR_NONE) {
+    return addr;
+  }
+#endif /* DNS_LOCAL_HOSTLIST */
+#ifdef DNS_LOOKUP_LOCAL_EXTERN
+  if((addr = DNS_LOOKUP_LOCAL_EXTERN(name)) != IPADDR_NONE) {
+    return addr;
+  }
+#endif /* DNS_LOOKUP_LOCAL_EXTERN */
+
+  /* Walk through name list, return entry if found. If not, return NULL. */
+  for (i = 0; i < DNS_TABLE_SIZE; ++i) {
+    if ((dns_table[i].state == DNS_STATE_DONE) &&
+        (strcmp(name, dns_table[i].name) == 0)) {
+      LWIP_DEBUGF(DNS_DEBUG, ("dns_lookup: \"%s\": found = ", name));
+      ip_addr_debug_print(DNS_DEBUG, &(dns_table[i].ipaddr));
+      LWIP_DEBUGF(DNS_DEBUG, ("\n"));
+      return ip4_addr_get_u32(&dns_table[i].ipaddr);
+    }
+  }
+
+  return IPADDR_NONE;
+}
+
+#if DNS_DOES_NAME_CHECK
+/**
+ * Compare the "dotted" name "query" with the encoded name "response"
+ * to make sure an answer from the DNS server matches the current dns_table
+ * entry (otherwise, answers might arrive late for hostname not on the list
+ * any more).
+ *
+ * @param query hostname (not encoded) from the dns_table
+ * @param response encoded hostname in the DNS response
+ * @return 0: names equal; 1: names differ
+ */
+static u8_t
+dns_compare_name(unsigned char *query, unsigned char *response)
+{
+  unsigned char n;
+
+  do {
+    n = *response++;
+    /** @see RFC 1035 - 4.1.4. Message compression */
+    if ((n & 0xc0) == 0xc0) {
+      /* Compressed name */
+      break;
+    } else {
+      /* Not compressed name */
+      while (n > 0) {
+        if ((*query) != (*response)) {
+          return 1;
+        }
+        ++response;
+        ++query;
+        --n;
+      };
+      ++query;
+    }
+  } while (*response != 0);
+
+  return 0;
+}
+#endif /* DNS_DOES_NAME_CHECK */
+
+/**
+ * Walk through a compact encoded DNS name and return the end of the name.
+ *
+ * @param query encoded DNS name in the DNS server response
+ * @return end of the name
+ */
+static unsigned char *
+dns_parse_name(unsigned char *query)
+{
+  unsigned char n;
+
+  do {
+    n = *query++;
+    /** @see RFC 1035 - 4.1.4. Message compression */
+    if ((n & 0xc0) == 0xc0) {
+      /* Compressed name */
+      break;
+    } else {
+      /* Not compressed name */
+      while (n > 0) {
+        ++query;
+        --n;
+      };
+    }
+  } while (*query != 0);
+
+  return query + 1;
+}
+
+/**
+ * Send a DNS query packet.
+ *
+ * @param numdns index of the DNS server in the dns_servers table
+ * @param name hostname to query
+ * @param id index of the hostname in dns_table, used as transaction ID in the
+ *        DNS query packet
+ * @return ERR_OK if packet is sent; an err_t indicating the problem otherwise
+ */
+static err_t
+dns_send(u8_t numdns, const char* name, u8_t id)
+{
+  err_t err;
+  struct dns_hdr *hdr;
+  struct dns_query qry;
+  struct pbuf *p;
+  char *query, *nptr;
+  const char *pHostname;
+  u8_t n;
+
+  LWIP_DEBUGF(DNS_DEBUG, ("dns_send: dns_servers[%"U16_F"] \"%s\": request\n",
+              (u16_t)(numdns), name));
+  LWIP_ASSERT("dns server out of array", numdns < DNS_MAX_SERVERS);
+  LWIP_ASSERT("dns server has no IP address set", !ip_addr_isany(&dns_servers[numdns]));
+
+  /* if here, we have either a new query or a retry on a previous query to process */
+  p = pbuf_alloc(PBUF_TRANSPORT, SIZEOF_DNS_HDR + DNS_MAX_NAME_LENGTH +
+                 SIZEOF_DNS_QUERY, PBUF_RAM);
+  if (p != NULL) {
+    LWIP_ASSERT("pbuf must be in one piece", p->next == NULL);
+    /* fill dns header */
+    hdr = (struct dns_hdr*)p->payload;
+    memset(hdr, 0, SIZEOF_DNS_HDR);
+    hdr->id = htons(id);
+    hdr->flags1 = DNS_FLAG1_RD;
+    hdr->numquestions = PP_HTONS(1);
+    query = (char*)hdr + SIZEOF_DNS_HDR;
+    pHostname = name;
+    --pHostname;
+
+    /* convert hostname into suitable query format. */
+    do {
+      ++pHostname;
+      nptr = query;
+      ++query;
+      for(n = 0; *pHostname != '.' && *pHostname != 0; ++pHostname) {
+        *query = *pHostname;
+        ++query;
+        ++n;
+      }
+      *nptr = n;
+    } while(*pHostname != 0);
+    *query++='\0';
+
+    /* fill dns query */
+    qry.type = PP_HTONS(DNS_RRTYPE_A);
+    qry.cls = PP_HTONS(DNS_RRCLASS_IN);
+    SMEMCPY(query, &qry, SIZEOF_DNS_QUERY);
+
+    /* resize pbuf to the exact dns query */
+    pbuf_realloc(p, (u16_t)((query + SIZEOF_DNS_QUERY) - ((char*)(p->payload))));
+
+    /* connect to the server for faster receiving */
+    udp_connect(dns_pcb, &dns_servers[numdns], DNS_SERVER_PORT);
+    /* send dns packet */
+    err = udp_sendto(dns_pcb, p, &dns_servers[numdns], DNS_SERVER_PORT);
+
+    /* free pbuf */
+    pbuf_free(p);
+  } else {
+    err = ERR_MEM;
+  }
+
+  return err;
+}
+
+/**
+ * dns_check_entry() - see if pEntry has not yet been queried and, if so, sends out a query.
+ * Check an entry in the dns_table:
+ * - send out query for new entries
+ * - retry old pending entries on timeout (also with different servers)
+ * - remove completed entries from the table if their TTL has expired
+ *
+ * @param i index of the dns_table entry to check
+ */
+static void
+dns_check_entry(u8_t i)
+{
+  err_t err;
+  struct dns_table_entry *pEntry = &dns_table[i];
+
+  LWIP_ASSERT("array index out of bounds", i < DNS_TABLE_SIZE);
+
+  switch(pEntry->state) {
+
+    case DNS_STATE_NEW: {
+      /* initialize new entry */
+      pEntry->state   = DNS_STATE_ASKING;
+      pEntry->numdns  = 0;
+      pEntry->tmr     = 1;
+      pEntry->retries = 0;
+      
+      /* send DNS packet for this entry */
+      err = dns_send(pEntry->numdns, pEntry->name, i);
+      if (err != ERR_OK) {
+        LWIP_DEBUGF(DNS_DEBUG | LWIP_DBG_LEVEL_WARNING,
+                    ("dns_send returned error: %s\n", lwip_strerr(err)));
+      }
+      break;
+    }
+
+    case DNS_STATE_ASKING: {
+      if (--pEntry->tmr == 0) {
+        if (++pEntry->retries == DNS_MAX_RETRIES) {
+          if ((pEntry->numdns+1numdns+1])) {
+            /* change of server */
+            pEntry->numdns++;
+            pEntry->tmr     = 1;
+            pEntry->retries = 0;
+            break;
+          } else {
+            LWIP_DEBUGF(DNS_DEBUG, ("dns_check_entry: \"%s\": timeout\n", pEntry->name));
+            /* call specified callback function if provided */
+            if (pEntry->found)
+              (*pEntry->found)(pEntry->name, NULL, pEntry->arg);
+            /* flush this entry */
+            pEntry->state   = DNS_STATE_UNUSED;
+            pEntry->found   = NULL;
+            break;
+          }
+        }
+
+        /* wait longer for the next retry */
+        pEntry->tmr = pEntry->retries;
+
+        /* send DNS packet for this entry */
+        err = dns_send(pEntry->numdns, pEntry->name, i);
+        if (err != ERR_OK) {
+          LWIP_DEBUGF(DNS_DEBUG | LWIP_DBG_LEVEL_WARNING,
+                      ("dns_send returned error: %s\n", lwip_strerr(err)));
+        }
+      }
+      break;
+    }
+
+    case DNS_STATE_DONE: {
+      /* if the time to live is nul */
+      if (--pEntry->ttl == 0) {
+        LWIP_DEBUGF(DNS_DEBUG, ("dns_check_entry: \"%s\": flush\n", pEntry->name));
+        /* flush this entry */
+        pEntry->state = DNS_STATE_UNUSED;
+        pEntry->found = NULL;
+      }
+      break;
+    }
+    case DNS_STATE_UNUSED:
+      /* nothing to do */
+      break;
+    default:
+      LWIP_ASSERT("unknown dns_table entry state:", 0);
+      break;
+  }
+}
+
+/**
+ * Call dns_check_entry for each entry in dns_table - check all entries.
+ */
+static void
+dns_check_entries(void)
+{
+  u8_t i;
+
+  for (i = 0; i < DNS_TABLE_SIZE; ++i) {
+    dns_check_entry(i);
+  }
+}
+
+/**
+ * Receive input function for DNS response packets arriving for the dns UDP pcb.
+ *
+ * @params see udp.h
+ */
+static void
+dns_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, ip_addr_t *addr, u16_t port)
+{
+  u16_t i;
+  char *pHostname;
+  struct dns_hdr *hdr;
+  struct dns_answer ans;
+  struct dns_table_entry *pEntry;
+  u16_t nquestions, nanswers;
+
+  LWIP_UNUSED_ARG(arg);
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_UNUSED_ARG(addr);
+  LWIP_UNUSED_ARG(port);
+
+  /* is the dns message too big ? */
+  if (p->tot_len > DNS_MSG_SIZE) {
+    LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: pbuf too big\n"));
+    /* free pbuf and return */
+    goto memerr;
+  }
+
+  /* is the dns message big enough ? */
+  if (p->tot_len < (SIZEOF_DNS_HDR + SIZEOF_DNS_QUERY + SIZEOF_DNS_ANSWER)) {
+    LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: pbuf too small\n"));
+    /* free pbuf and return */
+    goto memerr;
+  }
+
+  /* copy dns payload inside static buffer for processing */ 
+  if (pbuf_copy_partial(p, dns_payload, p->tot_len, 0) == p->tot_len) {
+    /* The ID in the DNS header should be our entry into the name table. */
+    hdr = (struct dns_hdr*)dns_payload;
+    i = htons(hdr->id);
+    if (i < DNS_TABLE_SIZE) {
+      pEntry = &dns_table[i];
+      if(pEntry->state == DNS_STATE_ASKING) {
+        /* This entry is now completed. */
+        pEntry->state = DNS_STATE_DONE;
+        pEntry->err   = hdr->flags2 & DNS_FLAG2_ERR_MASK;
+
+        /* We only care about the question(s) and the answers. The authrr
+           and the extrarr are simply discarded. */
+        nquestions = htons(hdr->numquestions);
+        nanswers   = htons(hdr->numanswers);
+
+        /* Check for error. If so, call callback to inform. */
+        if (((hdr->flags1 & DNS_FLAG1_RESPONSE) == 0) || (pEntry->err != 0) || (nquestions != 1)) {
+          LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": error in flags\n", pEntry->name));
+          /* call callback to indicate error, clean up memory and return */
+          goto responseerr;
+        }
+
+#if DNS_DOES_NAME_CHECK
+        /* Check if the name in the "question" part match with the name in the entry. */
+        if (dns_compare_name((unsigned char *)(pEntry->name), (unsigned char *)dns_payload + SIZEOF_DNS_HDR) != 0) {
+          LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response not match to query\n", pEntry->name));
+          /* call callback to indicate error, clean up memory and return */
+          goto responseerr;
+        }
+#endif /* DNS_DOES_NAME_CHECK */
+
+        /* Skip the name in the "question" part */
+        pHostname = (char *) dns_parse_name((unsigned char *)dns_payload + SIZEOF_DNS_HDR) + SIZEOF_DNS_QUERY;
+
+        while (nanswers > 0) {
+          /* skip answer resource record's host name */
+          pHostname = (char *) dns_parse_name((unsigned char *)pHostname);
+
+          /* Check for IP address type and Internet class. Others are discarded. */
+          SMEMCPY(&ans, pHostname, SIZEOF_DNS_ANSWER);
+          if((ans.type == PP_HTONS(DNS_RRTYPE_A)) && (ans.cls == PP_HTONS(DNS_RRCLASS_IN)) &&
+             (ans.len == PP_HTONS(sizeof(ip_addr_t))) ) {
+            /* read the answer resource record's TTL, and maximize it if needed */
+            pEntry->ttl = ntohl(ans.ttl);
+            if (pEntry->ttl > DNS_MAX_TTL) {
+              pEntry->ttl = DNS_MAX_TTL;
+            }
+            /* read the IP address after answer resource record's header */
+            SMEMCPY(&(pEntry->ipaddr), (pHostname+SIZEOF_DNS_ANSWER), sizeof(ip_addr_t));
+            LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response = ", pEntry->name));
+            ip_addr_debug_print(DNS_DEBUG, (&(pEntry->ipaddr)));
+            LWIP_DEBUGF(DNS_DEBUG, ("\n"));
+            /* call specified callback function if provided */
+            if (pEntry->found) {
+              (*pEntry->found)(pEntry->name, &pEntry->ipaddr, pEntry->arg);
+            }
+            /* deallocate memory and return */
+            goto memerr;
+          } else {
+            pHostname = pHostname + SIZEOF_DNS_ANSWER + htons(ans.len);
+          }
+          --nanswers;
+        }
+        LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": error in response\n", pEntry->name));
+        /* call callback to indicate error, clean up memory and return */
+        goto responseerr;
+      }
+    }
+  }
+
+  /* deallocate memory and return */
+  goto memerr;
+
+responseerr:
+  /* ERROR: call specified callback function with NULL as name to indicate an error */
+  if (pEntry->found) {
+    (*pEntry->found)(pEntry->name, NULL, pEntry->arg);
+  }
+  /* flush this entry */
+  pEntry->state = DNS_STATE_UNUSED;
+  pEntry->found = NULL;
+
+memerr:
+  /* free pbuf */
+  pbuf_free(p);
+  return;
+}
+
+/**
+ * Queues a new hostname to resolve and sends out a DNS query for that hostname
+ *
+ * @param name the hostname that is to be queried
+ * @param found a callback founction to be called on success, failure or timeout
+ * @param callback_arg argument to pass to the callback function
+ * @return @return a err_t return code.
+ */
+static err_t
+dns_enqueue(const char *name, dns_found_callback found, void *callback_arg)
+{
+  u8_t i;
+  u8_t lseq, lseqi;
+  struct dns_table_entry *pEntry = NULL;
+  size_t namelen;
+
+  /* search an unused entry, or the oldest one */
+  lseq = lseqi = 0;
+  for (i = 0; i < DNS_TABLE_SIZE; ++i) {
+    pEntry = &dns_table[i];
+    /* is it an unused entry ? */
+    if (pEntry->state == DNS_STATE_UNUSED)
+      break;
+
+    /* check if this is the oldest completed entry */
+    if (pEntry->state == DNS_STATE_DONE) {
+      if ((dns_seqno - pEntry->seqno) > lseq) {
+        lseq = dns_seqno - pEntry->seqno;
+        lseqi = i;
+      }
+    }
+  }
+
+  /* if we don't have found an unused entry, use the oldest completed one */
+  if (i == DNS_TABLE_SIZE) {
+    if ((lseqi >= DNS_TABLE_SIZE) || (dns_table[lseqi].state != DNS_STATE_DONE)) {
+      /* no entry can't be used now, table is full */
+      LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": DNS entries table is full\n", name));
+      return ERR_MEM;
+    } else {
+      /* use the oldest completed one */
+      i = lseqi;
+      pEntry = &dns_table[i];
+    }
+  }
+
+  /* use this entry */
+  LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": use DNS entry %"U16_F"\n", name, (u16_t)(i)));
+
+  /* fill the entry */
+  pEntry->state = DNS_STATE_NEW;
+  pEntry->seqno = dns_seqno++;
+  pEntry->found = found;
+  pEntry->arg   = callback_arg;
+  namelen = LWIP_MIN(strlen(name), DNS_MAX_NAME_LENGTH-1);
+  MEMCPY(pEntry->name, name, namelen);
+  pEntry->name[namelen] = 0;
+
+  /* force to send query without waiting timer */
+  dns_check_entry(i);
+
+  /* dns query is enqueued */
+  return ERR_INPROGRESS;
+}
+
+/**
+ * Resolve a hostname (string) into an IP address.
+ * NON-BLOCKING callback version for use with raw API!!!
+ *
+ * Returns immediately with one of err_t return codes:
+ * - ERR_OK if hostname is a valid IP address string or the host
+ *   name is already in the local names table.
+ * - ERR_INPROGRESS enqueue a request to be sent to the DNS server
+ *   for resolution if no errors are present.
+ * - ERR_ARG: dns client not initialized or invalid hostname
+ *
+ * @param hostname the hostname that is to be queried
+ * @param addr pointer to a ip_addr_t where to store the address if it is already
+ *             cached in the dns_table (only valid if ERR_OK is returned!)
+ * @param found a callback function to be called on success, failure or timeout (only if
+ *              ERR_INPROGRESS is returned!)
+ * @param callback_arg argument to pass to the callback function
+ * @return a err_t return code.
+ */
+err_t
+dns_gethostbyname(const char *hostname, ip_addr_t *addr, dns_found_callback found,
+                  void *callback_arg)
+{
+  u32_t ipaddr;
+  /* not initialized or no valid server yet, or invalid addr pointer
+   * or invalid hostname or invalid hostname length */
+  if ((dns_pcb == NULL) || (addr == NULL) ||
+      (!hostname) || (!hostname[0]) ||
+      (strlen(hostname) >= DNS_MAX_NAME_LENGTH)) {
+    return ERR_ARG;
+  }
+
+#if LWIP_HAVE_LOOPIF
+  if (strcmp(hostname, "localhost")==0) {
+    ip_addr_set_loopback(addr);
+    return ERR_OK;
+  }
+#endif /* LWIP_HAVE_LOOPIF */
+
+  /* host name already in octet notation? set ip addr and return ERR_OK */
+  ipaddr = ipaddr_addr(hostname);
+  if (ipaddr == IPADDR_NONE) {
+    /* already have this address cached? */
+    ipaddr = dns_lookup(hostname);
+  }
+  if (ipaddr != IPADDR_NONE) {
+    ip4_addr_set_u32(addr, ipaddr);
+    return ERR_OK;
+  }
+
+  /* queue query with specified callback */
+  return dns_enqueue(hostname, found, callback_arg);
+}
+
+#endif /* LWIP_DNS */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/init.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/init.c
new file mode 100644
index 0000000..bf5c79d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/init.c
@@ -0,0 +1,306 @@
+/**
+ * @file
+ * Modules initialization
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/init.h"
+#include "lwip/stats.h"
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/sockets.h"
+#include "lwip/ip.h"
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/tcp_impl.h"
+#include "lwip/snmp_msg.h"
+#include "lwip/autoip.h"
+#include "lwip/igmp.h"
+#include "lwip/dns.h"
+#include "lwip/timers.h"
+#include "netif/etharp.h"
+
+/* Compile-time sanity checks for configuration errors.
+ * These can be done independently of LWIP_DEBUG, without penalty.
+ */
+#ifndef BYTE_ORDER
+  #error "BYTE_ORDER is not defined, you have to define it in your cc.h"
+#endif
+#if (!IP_SOF_BROADCAST && IP_SOF_BROADCAST_RECV)
+  #error "If you want to use broadcast filter per pcb on recv operations, you have to define IP_SOF_BROADCAST=1 in your lwipopts.h"
+#endif
+#if (!LWIP_ARP && ARP_QUEUEING)
+  #error "If you want to use ARP Queueing, you have to define LWIP_ARP=1 in your lwipopts.h"
+#endif
+#if (!LWIP_UDP && LWIP_UDPLITE)
+  #error "If you want to use UDP Lite, you have to define LWIP_UDP=1 in your lwipopts.h"
+#endif
+#if (!LWIP_UDP && LWIP_SNMP)
+  #error "If you want to use SNMP, you have to define LWIP_UDP=1 in your lwipopts.h"
+#endif
+#if (!LWIP_UDP && LWIP_DHCP)
+  #error "If you want to use DHCP, you have to define LWIP_UDP=1 in your lwipopts.h"
+#endif
+#if (!LWIP_UDP && LWIP_IGMP)
+  #error "If you want to use IGMP, you have to define LWIP_UDP=1 in your lwipopts.h"
+#endif
+#if (!LWIP_UDP && LWIP_SNMP)
+  #error "If you want to use SNMP, you have to define LWIP_UDP=1 in your lwipopts.h"
+#endif
+#if (!LWIP_UDP && LWIP_DNS)
+  #error "If you want to use DNS, you have to define LWIP_UDP=1 in your lwipopts.h"
+#endif
+#if (LWIP_ARP && ARP_QUEUEING && (MEMP_NUM_ARP_QUEUE<=0))
+  #error "If you want to use ARP Queueing, you have to define MEMP_NUM_ARP_QUEUE>=1 in your lwipopts.h"
+#endif
+#if (LWIP_RAW && (MEMP_NUM_RAW_PCB<=0))
+  #error "If you want to use RAW, you have to define MEMP_NUM_RAW_PCB>=1 in your lwipopts.h"
+#endif
+#if (LWIP_UDP && (MEMP_NUM_UDP_PCB<=0))
+  #error "If you want to use UDP, you have to define MEMP_NUM_UDP_PCB>=1 in your lwipopts.h"
+#endif
+#if (LWIP_TCP && (MEMP_NUM_TCP_PCB<=0))
+  #error "If you want to use TCP, you have to define MEMP_NUM_TCP_PCB>=1 in your lwipopts.h"
+#endif
+#if (LWIP_TCP && (TCP_WND > 0xffff))
+  #error "If you want to use TCP, TCP_WND must fit in an u16_t, so, you have to reduce it in your lwipopts.h"
+#endif
+#if (LWIP_TCP && (TCP_SND_QUEUELEN > 0xffff))
+  #error "If you want to use TCP, TCP_SND_QUEUELEN must fit in an u16_t, so, you have to reduce it in your lwipopts.h"
+#endif
+#if (LWIP_TCP && (TCP_SND_QUEUELEN < 2))
+  #error "TCP_SND_QUEUELEN must be at least 2 for no-copy TCP writes to work"
+#endif
+#if (LWIP_TCP && ((TCP_MAXRTX > 12) || (TCP_SYNMAXRTX > 12)))
+  #error "If you want to use TCP, TCP_MAXRTX and TCP_SYNMAXRTX must less or equal to 12 (due to tcp_backoff table), so, you have to reduce them in your lwipopts.h"
+#endif
+#if (LWIP_TCP && TCP_LISTEN_BACKLOG && (TCP_DEFAULT_LISTEN_BACKLOG < 0) || (TCP_DEFAULT_LISTEN_BACKLOG > 0xff))
+  #error "If you want to use TCP backlog, TCP_DEFAULT_LISTEN_BACKLOG must fit into an u8_t"
+#endif
+#if (LWIP_IGMP && (MEMP_NUM_IGMP_GROUP<=1))
+  #error "If you want to use IGMP, you have to define MEMP_NUM_IGMP_GROUP>1 in your lwipopts.h"
+#endif
+#if (LWIP_NETIF_API && (NO_SYS==1))
+  #error "If you want to use NETIF API, you have to define NO_SYS=0 in your lwipopts.h"
+#endif
+#if ((LWIP_SOCKET || LWIP_NETCONN) && (NO_SYS==1))
+  #error "If you want to use Sequential API, you have to define NO_SYS=0 in your lwipopts.h"
+#endif
+#if ((LWIP_NETCONN || LWIP_SOCKET) && (MEMP_NUM_TCPIP_MSG_API<=0))
+  #error "If you want to use Sequential API, you have to define MEMP_NUM_TCPIP_MSG_API>=1 in your lwipopts.h"
+#endif
+#if (!LWIP_NETCONN && LWIP_SOCKET)
+  #error "If you want to use Socket API, you have to define LWIP_NETCONN=1 in your lwipopts.h"
+#endif
+#if (((!LWIP_DHCP) || (!LWIP_AUTOIP)) && LWIP_DHCP_AUTOIP_COOP)
+  #error "If you want to use DHCP/AUTOIP cooperation mode, you have to define LWIP_DHCP=1 and LWIP_AUTOIP=1 in your lwipopts.h"
+#endif
+#if (((!LWIP_DHCP) || (!LWIP_ARP)) && DHCP_DOES_ARP_CHECK)
+  #error "If you want to use DHCP ARP checking, you have to define LWIP_DHCP=1 and LWIP_ARP=1 in your lwipopts.h"
+#endif
+#if (!LWIP_ARP && LWIP_AUTOIP)
+  #error "If you want to use AUTOIP, you have to define LWIP_ARP=1 in your lwipopts.h"
+#endif
+#if (LWIP_SNMP && (SNMP_CONCURRENT_REQUESTS<=0))
+  #error "If you want to use SNMP, you have to define SNMP_CONCURRENT_REQUESTS>=1 in your lwipopts.h"
+#endif
+#if (LWIP_SNMP && (SNMP_TRAP_DESTINATIONS<=0))
+  #error "If you want to use SNMP, you have to define SNMP_TRAP_DESTINATIONS>=1 in your lwipopts.h"
+#endif
+#if (LWIP_TCP && ((LWIP_EVENT_API && LWIP_CALLBACK_API) || (!LWIP_EVENT_API && !LWIP_CALLBACK_API)))
+  #error "One and exactly one of LWIP_EVENT_API and LWIP_CALLBACK_API has to be enabled in your lwipopts.h"
+#endif
+/* There must be sufficient timeouts, taking into account requirements of the subsystems. */
+#if LWIP_TIMERS && (MEMP_NUM_SYS_TIMEOUT < (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + PPP_SUPPORT))
+  #error "MEMP_NUM_SYS_TIMEOUT is too low to accomodate all required timeouts"
+#endif
+#if (IP_REASSEMBLY && (MEMP_NUM_REASSDATA > IP_REASS_MAX_PBUFS))
+  #error "MEMP_NUM_REASSDATA > IP_REASS_MAX_PBUFS doesn't make sense since each struct ip_reassdata must hold 2 pbufs at least!"
+#endif
+#if (MEM_LIBC_MALLOC && MEM_USE_POOLS)
+  #error "MEM_LIBC_MALLOC and MEM_USE_POOLS may not both be simultaneously enabled in your lwipopts.h"
+#endif
+#if (MEM_USE_POOLS && !MEMP_USE_CUSTOM_POOLS)
+  #error "MEM_USE_POOLS requires custom pools (MEMP_USE_CUSTOM_POOLS) to be enabled in your lwipopts.h"
+#endif
+#if (PBUF_POOL_BUFSIZE <= MEM_ALIGNMENT)
+  #error "PBUF_POOL_BUFSIZE must be greater than MEM_ALIGNMENT or the offset may take the full first pbuf"
+#endif
+#if (TCP_QUEUE_OOSEQ && !LWIP_TCP)
+  #error "TCP_QUEUE_OOSEQ requires LWIP_TCP"
+#endif
+#if (DNS_LOCAL_HOSTLIST && !DNS_LOCAL_HOSTLIST_IS_DYNAMIC && !(defined(DNS_LOCAL_HOSTLIST_INIT)))
+  #error "you have to define define DNS_LOCAL_HOSTLIST_INIT {{'host1', 0x123}, {'host2', 0x234}} to initialize DNS_LOCAL_HOSTLIST"
+#endif
+#if PPP_SUPPORT && !PPPOS_SUPPORT & !PPPOE_SUPPORT
+  #error "PPP_SUPPORT needs either PPPOS_SUPPORT or PPPOE_SUPPORT turned on"
+#endif
+#if !LWIP_ETHERNET && (LWIP_ARP || PPPOE_SUPPORT)
+  #error "LWIP_ETHERNET needs to be turned on for LWIP_ARP or PPPOE_SUPPORT"
+#endif
+#if LWIP_IGMP && !defined(LWIP_RAND)
+  #error "When using IGMP, LWIP_RAND() needs to be defined to a random-function returning an u32_t random value"
+#endif
+#if LWIP_TCPIP_CORE_LOCKING_INPUT && !LWIP_TCPIP_CORE_LOCKING
+  #error "When using LWIP_TCPIP_CORE_LOCKING_INPUT, LWIP_TCPIP_CORE_LOCKING must be enabled, too"
+#endif
+#if LWIP_TCP && LWIP_NETIF_TX_SINGLE_PBUF && !TCP_OVERSIZE
+  #error "LWIP_NETIF_TX_SINGLE_PBUF needs TCP_OVERSIZE enabled to create single-pbuf TCP packets"
+#endif
+#if IP_FRAG && IP_FRAG_USES_STATIC_BUF && LWIP_NETIF_TX_SINGLE_PBUF
+  #error "LWIP_NETIF_TX_SINGLE_PBUF does not work with IP_FRAG_USES_STATIC_BUF==1 as that creates pbuf queues"
+#endif
+
+
+/* Compile-time checks for deprecated options.
+ */
+#ifdef MEMP_NUM_TCPIP_MSG
+  #error "MEMP_NUM_TCPIP_MSG option is deprecated. Remove it from your lwipopts.h."
+#endif
+#ifdef MEMP_NUM_API_MSG
+  #error "MEMP_NUM_API_MSG option is deprecated. Remove it from your lwipopts.h."
+#endif
+#ifdef TCP_REXMIT_DEBUG
+  #error "TCP_REXMIT_DEBUG option is deprecated. Remove it from your lwipopts.h."
+#endif
+#ifdef RAW_STATS
+  #error "RAW_STATS option is deprecated. Remove it from your lwipopts.h."
+#endif
+#ifdef ETHARP_QUEUE_FIRST
+  #error "ETHARP_QUEUE_FIRST option is deprecated. Remove it from your lwipopts.h."
+#endif
+#ifdef ETHARP_ALWAYS_INSERT
+  #error "ETHARP_ALWAYS_INSERT option is deprecated. Remove it from your lwipopts.h."
+#endif
+
+#ifdef LWIP_DEBUG
+static void
+lwip_sanity_check(void)
+{
+  /* Warnings */
+#if LWIP_NETCONN
+  if (MEMP_NUM_NETCONN > (MEMP_NUM_TCP_PCB+MEMP_NUM_TCP_PCB_LISTEN+MEMP_NUM_UDP_PCB+MEMP_NUM_RAW_PCB))
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: MEMP_NUM_NETCONN should be less than the sum of MEMP_NUM_{TCP,RAW,UDP}_PCB+MEMP_NUM_TCP_PCB_LISTEN\n"));
+#endif /* LWIP_NETCONN */
+#if LWIP_TCP
+  if (MEMP_NUM_TCP_SEG < TCP_SND_QUEUELEN)
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: MEMP_NUM_TCP_SEG should be at least as big as TCP_SND_QUEUELEN\n"));
+  if (TCP_SND_BUF < 2 * TCP_MSS)
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_SND_BUF must be at least as much as (2 * TCP_MSS) for things to work smoothly\n"));
+  if (TCP_SND_QUEUELEN < (2 * (TCP_SND_BUF/TCP_MSS)))
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_SND_QUEUELEN must be at least as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work\n"));
+  if (TCP_SNDLOWAT >= TCP_SND_BUF)
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_SNDLOWAT must be less than TCP_SND_BUF.\n"));
+  if (TCP_SNDQUEUELOWAT >= TCP_SND_QUEUELEN)
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_SNDQUEUELOWAT must be less than TCP_SND_QUEUELEN.\n"));
+  if (TCP_WND > (PBUF_POOL_SIZE*PBUF_POOL_BUFSIZE))
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_WND is larger than space provided by PBUF_POOL_SIZE*PBUF_POOL_BUFSIZE\n"));
+  if (TCP_WND < TCP_MSS)
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: TCP_WND is smaller than MSS\n"));
+#endif /* LWIP_TCP */
+#if LWIP_SOCKET
+  /* Check that the SO_* socket options and SOF_* lwIP-internal flags match */
+  if (SO_ACCEPTCONN != SOF_ACCEPTCONN)
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: SO_ACCEPTCONN != SOF_ACCEPTCONN\n"));
+  if (SO_REUSEADDR != SOF_REUSEADDR)
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: SO_REUSEADDR != SOF_REUSEADDR\n"));
+  if (SO_KEEPALIVE != SOF_KEEPALIVE)
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: SO_KEEPALIVE != SOF_KEEPALIVE\n"));
+  if (SO_BROADCAST != SOF_BROADCAST)
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: SO_BROADCAST != SOF_BROADCAST\n"));
+  if (SO_LINGER != SOF_LINGER)
+    LWIP_PLATFORM_DIAG(("lwip_sanity_check: WARNING: SO_LINGER != SOF_LINGER\n"));
+#endif /* LWIP_SOCKET */
+}
+#else  /* LWIP_DEBUG */
+#define lwip_sanity_check()
+#endif /* LWIP_DEBUG */
+
+/**
+ * Perform Sanity check of user-configurable values, and initialize all modules.
+ */
+void
+lwip_init(void)
+{
+  /* Sanity check user-configurable values */
+  lwip_sanity_check();
+
+  /* Modules initialization */
+  stats_init();
+#if !NO_SYS
+  sys_init();
+#endif /* !NO_SYS */
+  mem_init();
+  memp_init();
+  pbuf_init();
+  netif_init();
+#if LWIP_SOCKET
+  lwip_socket_init();
+#endif /* LWIP_SOCKET */
+  ip_init();
+#if LWIP_ARP
+  etharp_init();
+#endif /* LWIP_ARP */
+#if LWIP_RAW
+  raw_init();
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+  udp_init();
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+  tcp_init();
+#endif /* LWIP_TCP */
+#if LWIP_SNMP
+  snmp_init();
+#endif /* LWIP_SNMP */
+#if LWIP_AUTOIP
+  autoip_init();
+#endif /* LWIP_AUTOIP */
+#if LWIP_IGMP
+  igmp_init();
+#endif /* LWIP_IGMP */
+#if LWIP_DNS
+  dns_init();
+#endif /* LWIP_DNS */
+
+#if LWIP_TIMERS
+  sys_timeouts_init();
+#endif /* LWIP_TIMERS */
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/autoip.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/autoip.c
new file mode 100644
index 0000000..92bb459
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/autoip.c
@@ -0,0 +1,536 @@
+/**
+ * @file
+ * AutoIP Automatic LinkLocal IP Configuration
+ *
+ */
+
+/*
+ *
+ * Copyright (c) 2007 Dominik Spies 
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Dominik Spies 
+ *
+ * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform
+ * with RFC 3927.
+ *
+ *
+ * Please coordinate changes and requests with Dominik Spies
+ * 
+ */
+
+/*******************************************************************************
+ * USAGE:
+ * 
+ * define LWIP_AUTOIP 1  in your lwipopts.h
+ * 
+ * If you don't use tcpip.c (so, don't call, you don't call tcpip_init):
+ * - First, call autoip_init().
+ * - call autoip_tmr() all AUTOIP_TMR_INTERVAL msces,
+ *   that should be defined in autoip.h.
+ *   I recommend a value of 100. The value must divide 1000 with a remainder almost 0.
+ *   Possible values are 1000, 500, 333, 250, 200, 166, 142, 125, 111, 100 ....
+ *
+ * Without DHCP:
+ * - Call autoip_start() after netif_add().
+ * 
+ * With DHCP:
+ * - define LWIP_DHCP_AUTOIP_COOP 1 in your lwipopts.h.
+ * - Configure your DHCP Client.
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_AUTOIP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/mem.h"
+#include "lwip/udp.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/autoip.h"
+#include "netif/etharp.h"
+
+#include 
+#include 
+
+/* 169.254.0.0 */
+#define AUTOIP_NET         0xA9FE0000
+/* 169.254.1.0 */
+#define AUTOIP_RANGE_START (AUTOIP_NET | 0x0100)
+/* 169.254.254.255 */
+#define AUTOIP_RANGE_END   (AUTOIP_NET | 0xFEFF)
+
+
+/** Pseudo random macro based on netif informations.
+ * You could use "rand()" from the C Library if you define LWIP_AUTOIP_RAND in lwipopts.h */
+#ifndef LWIP_AUTOIP_RAND
+#define LWIP_AUTOIP_RAND(netif) ( (((u32_t)((netif->hwaddr[5]) & 0xff) << 24) | \
+                                   ((u32_t)((netif->hwaddr[3]) & 0xff) << 16) | \
+                                   ((u32_t)((netif->hwaddr[2]) & 0xff) << 8) | \
+                                   ((u32_t)((netif->hwaddr[4]) & 0xff))) + \
+                                   (netif->autoip?netif->autoip->tried_llipaddr:0))
+#endif /* LWIP_AUTOIP_RAND */
+
+/**
+ * Macro that generates the initial IP address to be tried by AUTOIP.
+ * If you want to override this, define it to something else in lwipopts.h.
+ */
+#ifndef LWIP_AUTOIP_CREATE_SEED_ADDR
+#define LWIP_AUTOIP_CREATE_SEED_ADDR(netif) \
+  htonl(AUTOIP_RANGE_START + ((u32_t)(((u8_t)(netif->hwaddr[4])) | \
+                 ((u32_t)((u8_t)(netif->hwaddr[5]))) << 8)))
+#endif /* LWIP_AUTOIP_CREATE_SEED_ADDR */
+
+/* static functions */
+static void autoip_handle_arp_conflict(struct netif *netif);
+
+/* creates a pseudo random LL IP-Address for a network interface */
+static void autoip_create_addr(struct netif *netif, ip_addr_t *ipaddr);
+
+/* sends an ARP probe */
+static err_t autoip_arp_probe(struct netif *netif);
+
+/* sends an ARP announce */
+static err_t autoip_arp_announce(struct netif *netif);
+
+/* configure interface for use with current LL IP-Address */
+static err_t autoip_bind(struct netif *netif);
+
+/* start sending probes for llipaddr */
+static void autoip_start_probing(struct netif *netif);
+
+/**
+ * Initialize this module
+ */
+void
+autoip_init(void)
+{
+  LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, ("autoip_init()\n"));
+}
+
+/** Set a statically allocated struct autoip to work with.
+ * Using this prevents autoip_start to allocate it using mem_malloc.
+ *
+ * @param netif the netif for which to set the struct autoip
+ * @param dhcp (uninitialised) dhcp struct allocated by the application
+ */
+void
+autoip_set_struct(struct netif *netif, struct autoip *autoip)
+{
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+  LWIP_ASSERT("autoip != NULL", autoip != NULL);
+  LWIP_ASSERT("netif already has a struct autoip set", netif->autoip == NULL);
+
+  /* clear data structure */
+  memset(autoip, 0, sizeof(struct autoip));
+  /* autoip->state = AUTOIP_STATE_OFF; */
+  netif->autoip = autoip;
+}
+
+/** Restart AutoIP client and check the next address (conflict detected)
+ *
+ * @param netif The netif under AutoIP control
+ */
+static void
+autoip_restart(struct netif *netif)
+{
+  netif->autoip->tried_llipaddr++;
+  autoip_start(netif);
+}
+
+/**
+ * Handle a IP address conflict after an ARP conflict detection
+ */
+static void
+autoip_handle_arp_conflict(struct netif *netif)
+{
+  /* Somehow detect if we are defending or retreating */
+  unsigned char defend = 1; /* tbd */
+
+  if(defend) {
+    if(netif->autoip->lastconflict > 0) {
+      /* retreat, there was a conflicting ARP in the last
+       * DEFEND_INTERVAL seconds
+       */
+      LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+        ("autoip_handle_arp_conflict(): we are defending, but in DEFEND_INTERVAL, retreating\n"));
+
+      /* TODO: close all TCP sessions */
+      autoip_restart(netif);
+    } else {
+      LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+        ("autoip_handle_arp_conflict(): we are defend, send ARP Announce\n"));
+      autoip_arp_announce(netif);
+      netif->autoip->lastconflict = DEFEND_INTERVAL * AUTOIP_TICKS_PER_SECOND;
+    }
+  } else {
+    LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+      ("autoip_handle_arp_conflict(): we do not defend, retreating\n"));
+    /* TODO: close all TCP sessions */
+    autoip_restart(netif);
+  }
+}
+
+/**
+ * Create an IP-Address out of range 169.254.1.0 to 169.254.254.255
+ *
+ * @param netif network interface on which create the IP-Address
+ * @param ipaddr ip address to initialize
+ */
+static void
+autoip_create_addr(struct netif *netif, ip_addr_t *ipaddr)
+{
+  /* Here we create an IP-Address out of range 169.254.1.0 to 169.254.254.255
+   * compliant to RFC 3927 Section 2.1
+   * We have 254 * 256 possibilities */
+
+  u32_t addr = ntohl(LWIP_AUTOIP_CREATE_SEED_ADDR(netif));
+  addr += netif->autoip->tried_llipaddr;
+  addr = AUTOIP_NET | (addr & 0xffff);
+  /* Now, 169.254.0.0 <= addr <= 169.254.255.255 */ 
+
+  if (addr < AUTOIP_RANGE_START) {
+    addr += AUTOIP_RANGE_END - AUTOIP_RANGE_START + 1;
+  }
+  if (addr > AUTOIP_RANGE_END) {
+    addr -= AUTOIP_RANGE_END - AUTOIP_RANGE_START + 1;
+  }
+  LWIP_ASSERT("AUTOIP address not in range", (addr >= AUTOIP_RANGE_START) &&
+    (addr <= AUTOIP_RANGE_END));
+  ip4_addr_set_u32(ipaddr, htonl(addr));
+  
+  LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+    ("autoip_create_addr(): tried_llipaddr=%"U16_F", %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+    (u16_t)(netif->autoip->tried_llipaddr), ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr),
+    ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr)));
+}
+
+/**
+ * Sends an ARP probe from a network interface
+ *
+ * @param netif network interface used to send the probe
+ */
+static err_t
+autoip_arp_probe(struct netif *netif)
+{
+  return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, ðbroadcast,
+    (struct eth_addr *)netif->hwaddr, IP_ADDR_ANY, ðzero,
+    &netif->autoip->llipaddr, ARP_REQUEST);
+}
+
+/**
+ * Sends an ARP announce from a network interface
+ *
+ * @param netif network interface used to send the announce
+ */
+static err_t
+autoip_arp_announce(struct netif *netif)
+{
+  return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, ðbroadcast,
+    (struct eth_addr *)netif->hwaddr, &netif->autoip->llipaddr, ðzero,
+    &netif->autoip->llipaddr, ARP_REQUEST);
+}
+
+/**
+ * Configure interface for use with current LL IP-Address
+ *
+ * @param netif network interface to configure with current LL IP-Address
+ */
+static err_t
+autoip_bind(struct netif *netif)
+{
+  struct autoip *autoip = netif->autoip;
+  ip_addr_t sn_mask, gw_addr;
+
+  LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE,
+    ("autoip_bind(netif=%p) %c%c%"U16_F" %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+    (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num,
+    ip4_addr1_16(&autoip->llipaddr), ip4_addr2_16(&autoip->llipaddr),
+    ip4_addr3_16(&autoip->llipaddr), ip4_addr4_16(&autoip->llipaddr)));
+
+  IP4_ADDR(&sn_mask, 255, 255, 0, 0);
+  IP4_ADDR(&gw_addr, 0, 0, 0, 0);
+
+  netif_set_ipaddr(netif, &autoip->llipaddr);
+  netif_set_netmask(netif, &sn_mask);
+  netif_set_gw(netif, &gw_addr);  
+
+  /* bring the interface up */
+  netif_set_up(netif);
+
+  return ERR_OK;
+}
+
+/**
+ * Start AutoIP client
+ *
+ * @param netif network interface on which start the AutoIP client
+ */
+err_t
+autoip_start(struct netif *netif)
+{
+  struct autoip *autoip = netif->autoip;
+  err_t result = ERR_OK;
+
+  if(netif_is_up(netif)) {
+    netif_set_down(netif);
+  }
+
+  /* Set IP-Address, Netmask and Gateway to 0 to make sure that
+   * ARP Packets are formed correctly
+   */
+  ip_addr_set_zero(&netif->ip_addr);
+  ip_addr_set_zero(&netif->netmask);
+  ip_addr_set_zero(&netif->gw);
+
+  LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+    ("autoip_start(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0],
+    netif->name[1], (u16_t)netif->num));
+  if(autoip == NULL) {
+    /* no AutoIP client attached yet? */
+    LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE,
+      ("autoip_start(): starting new AUTOIP client\n"));
+    autoip = (struct autoip *)mem_malloc(sizeof(struct autoip));
+    if(autoip == NULL) {
+      LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE,
+        ("autoip_start(): could not allocate autoip\n"));
+      return ERR_MEM;
+    }
+    memset(autoip, 0, sizeof(struct autoip));
+    /* store this AutoIP client in the netif */
+    netif->autoip = autoip;
+    LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, ("autoip_start(): allocated autoip"));
+  } else {
+    autoip->state = AUTOIP_STATE_OFF;
+    autoip->ttw = 0;
+    autoip->sent_num = 0;
+    ip_addr_set_zero(&autoip->llipaddr);
+    autoip->lastconflict = 0;
+  }
+
+  autoip_create_addr(netif, &(autoip->llipaddr));
+  autoip_start_probing(netif);
+
+  return result;
+}
+
+static void
+autoip_start_probing(struct netif *netif)
+{
+  struct autoip *autoip = netif->autoip;
+
+  autoip->state = AUTOIP_STATE_PROBING;
+  autoip->sent_num = 0;
+  LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+     ("autoip_start_probing(): changing state to PROBING: %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+      ip4_addr1_16(&netif->autoip->llipaddr), ip4_addr2_16(&netif->autoip->llipaddr),
+      ip4_addr3_16(&netif->autoip->llipaddr), ip4_addr4_16(&netif->autoip->llipaddr)));
+
+  /* time to wait to first probe, this is randomly
+   * choosen out of 0 to PROBE_WAIT seconds.
+   * compliant to RFC 3927 Section 2.2.1
+   */
+  autoip->ttw = (u16_t)(LWIP_AUTOIP_RAND(netif) % (PROBE_WAIT * AUTOIP_TICKS_PER_SECOND));
+
+  /*
+   * if we tried more then MAX_CONFLICTS we must limit our rate for
+   * accquiring and probing address
+   * compliant to RFC 3927 Section 2.2.1
+   */
+  if(autoip->tried_llipaddr > MAX_CONFLICTS) {
+    autoip->ttw = RATE_LIMIT_INTERVAL * AUTOIP_TICKS_PER_SECOND;
+  }
+}
+
+/**
+ * Handle a possible change in the network configuration.
+ *
+ * If there is an AutoIP address configured, take the interface down
+ * and begin probing with the same address.
+ */
+void
+autoip_network_changed(struct netif *netif)
+{
+  if (netif->autoip && netif->autoip->state != AUTOIP_STATE_OFF) {
+    netif_set_down(netif);
+    autoip_start_probing(netif);
+  }
+}
+
+/**
+ * Stop AutoIP client
+ *
+ * @param netif network interface on which stop the AutoIP client
+ */
+err_t
+autoip_stop(struct netif *netif)
+{
+  netif->autoip->state = AUTOIP_STATE_OFF;
+  netif_set_down(netif);
+  return ERR_OK;
+}
+
+/**
+ * Has to be called in loop every AUTOIP_TMR_INTERVAL milliseconds
+ */
+void
+autoip_tmr()
+{
+  struct netif *netif = netif_list;
+  /* loop through netif's */
+  while (netif != NULL) {
+    /* only act on AutoIP configured interfaces */
+    if (netif->autoip != NULL) {
+      if(netif->autoip->lastconflict > 0) {
+        netif->autoip->lastconflict--;
+      }
+
+      LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE,
+        ("autoip_tmr() AutoIP-State: %"U16_F", ttw=%"U16_F"\n",
+        (u16_t)(netif->autoip->state), netif->autoip->ttw));
+
+      switch(netif->autoip->state) {
+        case AUTOIP_STATE_PROBING:
+          if(netif->autoip->ttw > 0) {
+            netif->autoip->ttw--;
+          } else {
+            if(netif->autoip->sent_num >= PROBE_NUM) {
+              netif->autoip->state = AUTOIP_STATE_ANNOUNCING;
+              netif->autoip->sent_num = 0;
+              netif->autoip->ttw = ANNOUNCE_WAIT * AUTOIP_TICKS_PER_SECOND;
+              LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+                 ("autoip_tmr(): changing state to ANNOUNCING: %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+                  ip4_addr1_16(&netif->autoip->llipaddr), ip4_addr2_16(&netif->autoip->llipaddr),
+                  ip4_addr3_16(&netif->autoip->llipaddr), ip4_addr4_16(&netif->autoip->llipaddr)));
+            } else {
+              autoip_arp_probe(netif);
+              LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE,
+                ("autoip_tmr() PROBING Sent Probe\n"));
+              netif->autoip->sent_num++;
+              /* calculate time to wait to next probe */
+              netif->autoip->ttw = (u16_t)((LWIP_AUTOIP_RAND(netif) %
+                ((PROBE_MAX - PROBE_MIN) * AUTOIP_TICKS_PER_SECOND) ) +
+                PROBE_MIN * AUTOIP_TICKS_PER_SECOND);
+            }
+          }
+          break;
+
+        case AUTOIP_STATE_ANNOUNCING:
+          if(netif->autoip->ttw > 0) {
+            netif->autoip->ttw--;
+          } else {
+            if(netif->autoip->sent_num == 0) {
+             /* We are here the first time, so we waited ANNOUNCE_WAIT seconds
+              * Now we can bind to an IP address and use it.
+              *
+              * autoip_bind calls netif_set_up. This triggers a gratuitous ARP
+              * which counts as an announcement.
+              */
+              autoip_bind(netif);
+            } else {
+              autoip_arp_announce(netif);
+              LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE,
+                ("autoip_tmr() ANNOUNCING Sent Announce\n"));
+            }
+            netif->autoip->ttw = ANNOUNCE_INTERVAL * AUTOIP_TICKS_PER_SECOND;
+            netif->autoip->sent_num++;
+
+            if(netif->autoip->sent_num >= ANNOUNCE_NUM) {
+                netif->autoip->state = AUTOIP_STATE_BOUND;
+                netif->autoip->sent_num = 0;
+                netif->autoip->ttw = 0;
+                 LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+                    ("autoip_tmr(): changing state to BOUND: %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+                     ip4_addr1_16(&netif->autoip->llipaddr), ip4_addr2_16(&netif->autoip->llipaddr),
+                     ip4_addr3_16(&netif->autoip->llipaddr), ip4_addr4_16(&netif->autoip->llipaddr)));
+            }
+          }
+          break;
+      }
+    }
+    /* proceed to next network interface */
+    netif = netif->next;
+  }
+}
+
+/**
+ * Handles every incoming ARP Packet, called by etharp_arp_input.
+ *
+ * @param netif network interface to use for autoip processing
+ * @param hdr Incoming ARP packet
+ */
+void
+autoip_arp_reply(struct netif *netif, struct etharp_hdr *hdr)
+{
+  LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, ("autoip_arp_reply()\n"));
+  if ((netif->autoip != NULL) && (netif->autoip->state != AUTOIP_STATE_OFF)) {
+   /* when ip.src == llipaddr && hw.src != netif->hwaddr
+    *
+    * when probing  ip.dst == llipaddr && hw.src != netif->hwaddr
+    * we have a conflict and must solve it
+    */
+    ip_addr_t sipaddr, dipaddr;
+    struct eth_addr netifaddr;
+    ETHADDR16_COPY(netifaddr.addr, netif->hwaddr);
+
+    /* Copy struct ip_addr2 to aligned ip_addr, to support compilers without
+     * structure packing (not using structure copy which breaks strict-aliasing rules).
+     */
+    IPADDR2_COPY(&sipaddr, &hdr->sipaddr);
+    IPADDR2_COPY(&dipaddr, &hdr->dipaddr);
+      
+    if ((netif->autoip->state == AUTOIP_STATE_PROBING) ||
+        ((netif->autoip->state == AUTOIP_STATE_ANNOUNCING) &&
+         (netif->autoip->sent_num == 0))) {
+     /* RFC 3927 Section 2.2.1:
+      * from beginning to after ANNOUNCE_WAIT
+      * seconds we have a conflict if
+      * ip.src == llipaddr OR
+      * ip.dst == llipaddr && hw.src != own hwaddr
+      */
+      if ((ip_addr_cmp(&sipaddr, &netif->autoip->llipaddr)) ||
+          (ip_addr_cmp(&dipaddr, &netif->autoip->llipaddr) &&
+           !eth_addr_cmp(&netifaddr, &hdr->shwaddr))) {
+        LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING,
+          ("autoip_arp_reply(): Probe Conflict detected\n"));
+        autoip_restart(netif);
+      }
+    } else {
+     /* RFC 3927 Section 2.5:
+      * in any state we have a conflict if
+      * ip.src == llipaddr && hw.src != own hwaddr
+      */
+      if (ip_addr_cmp(&sipaddr, &netif->autoip->llipaddr) &&
+          !eth_addr_cmp(&netifaddr, &hdr->shwaddr)) {
+        LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING,
+          ("autoip_arp_reply(): Conflicting ARP-Packet detected\n"));
+        autoip_handle_arp_conflict(netif);
+      }
+    }
+  }
+}
+
+#endif /* LWIP_AUTOIP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/icmp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/icmp.c
new file mode 100644
index 0000000..32902a5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/icmp.c
@@ -0,0 +1,335 @@
+/**
+ * @file
+ * ICMP - Internet Control Message Protocol
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* Some ICMP messages should be passed to the transport protocols. This
+   is not implemented. */
+
+#include "lwip/opt.h"
+
+#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/icmp.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/ip.h"
+#include "lwip/def.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+
+#include 
+
+/** Small optimization: set to 0 if incoming PBUF_POOL pbuf always can be
+ * used to modify and send a response packet (and to 1 if this is not the case,
+ * e.g. when link header is stripped of when receiving) */
+#ifndef LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN
+#define LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN 1
+#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */
+
+/* The amount of data from the original packet to return in a dest-unreachable */
+#define ICMP_DEST_UNREACH_DATASIZE 8
+
+static void icmp_send_response(struct pbuf *p, u8_t type, u8_t code);
+
+/**
+ * Processes ICMP input packets, called from ip_input().
+ *
+ * Currently only processes icmp echo requests and sends
+ * out the echo response.
+ *
+ * @param p the icmp echo request packet, p->payload pointing to the ip header
+ * @param inp the netif on which this packet was received
+ */
+void
+icmp_input(struct pbuf *p, struct netif *inp)
+{
+  u8_t type;
+#ifdef LWIP_DEBUG
+  u8_t code;
+#endif /* LWIP_DEBUG */
+  struct icmp_echo_hdr *iecho;
+  struct ip_hdr *iphdr;
+  s16_t hlen;
+
+  ICMP_STATS_INC(icmp.recv);
+  snmp_inc_icmpinmsgs();
+
+
+  iphdr = (struct ip_hdr *)p->payload;
+  hlen = IPH_HL(iphdr) * 4;
+  if (pbuf_header(p, -hlen) || (p->tot_len < sizeof(u16_t)*2)) {
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len));
+    goto lenerr;
+  }
+
+  type = *((u8_t *)p->payload);
+#ifdef LWIP_DEBUG
+  code = *(((u8_t *)p->payload)+1);
+#endif /* LWIP_DEBUG */
+  switch (type) {
+  case ICMP_ER:
+    /* This is OK, echo reply might have been parsed by a raw PCB
+       (as obviously, an echo request has been sent, too). */
+    break; 
+  case ICMP_ECHO:
+#if !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING
+    {
+      int accepted = 1;
+#if !LWIP_MULTICAST_PING
+      /* multicast destination address? */
+      if (ip_addr_ismulticast(¤t_iphdr_dest)) {
+        accepted = 0;
+      }
+#endif /* LWIP_MULTICAST_PING */
+#if !LWIP_BROADCAST_PING
+      /* broadcast destination address? */
+      if (ip_addr_isbroadcast(¤t_iphdr_dest, inp)) {
+        accepted = 0;
+      }
+#endif /* LWIP_BROADCAST_PING */
+      /* broadcast or multicast destination address not acceptd? */
+      if (!accepted) {
+        LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast or broadcast pings\n"));
+        ICMP_STATS_INC(icmp.err);
+        pbuf_free(p);
+        return;
+      }
+    }
+#endif /* !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING */
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
+    if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n"));
+      goto lenerr;
+    }
+    if (inet_chksum_pbuf(p) != 0) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n"));
+      pbuf_free(p);
+      ICMP_STATS_INC(icmp.chkerr);
+      snmp_inc_icmpinerrors();
+      return;
+    }
+#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN
+    if (pbuf_header(p, (PBUF_IP_HLEN + PBUF_LINK_HLEN))) {
+      /* p is not big enough to contain link headers
+       * allocate a new one and copy p into it
+       */
+      struct pbuf *r;
+      /* switch p->payload to ip header */
+      if (pbuf_header(p, hlen)) {
+        LWIP_ASSERT("icmp_input: moving p->payload to ip header failed\n", 0);
+        goto memerr;
+      }
+      /* allocate new packet buffer with space for link headers */
+      r = pbuf_alloc(PBUF_LINK, p->tot_len, PBUF_RAM);
+      if (r == NULL) {
+        LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed\n"));
+        goto memerr;
+      }
+      LWIP_ASSERT("check that first pbuf can hold struct the ICMP header",
+                  (r->len >= hlen + sizeof(struct icmp_echo_hdr)));
+      /* copy the whole packet including ip header */
+      if (pbuf_copy(r, p) != ERR_OK) {
+        LWIP_ASSERT("icmp_input: copying to new pbuf failed\n", 0);
+        goto memerr;
+      }
+      iphdr = (struct ip_hdr *)r->payload;
+      /* switch r->payload back to icmp header */
+      if (pbuf_header(r, -hlen)) {
+        LWIP_ASSERT("icmp_input: restoring original p->payload failed\n", 0);
+        goto memerr;
+      }
+      /* free the original p */
+      pbuf_free(p);
+      /* we now have an identical copy of p that has room for link headers */
+      p = r;
+    } else {
+      /* restore p->payload to point to icmp header */
+      if (pbuf_header(p, -(s16_t)(PBUF_IP_HLEN + PBUF_LINK_HLEN))) {
+        LWIP_ASSERT("icmp_input: restoring original p->payload failed\n", 0);
+        goto memerr;
+      }
+    }
+#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */
+    /* At this point, all checks are OK. */
+    /* We generate an answer by switching the dest and src ip addresses,
+     * setting the icmp type to ECHO_RESPONSE and updating the checksum. */
+    iecho = (struct icmp_echo_hdr *)p->payload;
+    ip_addr_copy(iphdr->src, *ip_current_dest_addr());
+    ip_addr_copy(iphdr->dest, *ip_current_src_addr());
+    ICMPH_TYPE_SET(iecho, ICMP_ER);
+    /* adjust the checksum */
+    if (iecho->chksum >= PP_HTONS(0xffffU - (ICMP_ECHO << 8))) {
+      iecho->chksum += PP_HTONS(ICMP_ECHO << 8) + 1;
+    } else {
+      iecho->chksum += PP_HTONS(ICMP_ECHO << 8);
+    }
+
+    /* Set the correct TTL and recalculate the header checksum. */
+    IPH_TTL_SET(iphdr, ICMP_TTL);
+    IPH_CHKSUM_SET(iphdr, 0);
+#if CHECKSUM_GEN_IP
+    IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
+#endif /* CHECKSUM_GEN_IP */
+
+    ICMP_STATS_INC(icmp.xmit);
+    /* increase number of messages attempted to send */
+    snmp_inc_icmpoutmsgs();
+    /* increase number of echo replies attempted to send */
+    snmp_inc_icmpoutechoreps();
+
+    if(pbuf_header(p, hlen)) {
+      LWIP_ASSERT("Can't move over header in packet", 0);
+    } else {
+      err_t ret;
+      /* send an ICMP packet, src addr is the dest addr of the curren packet */
+      ret = ip_output_if(p, ip_current_dest_addr(), IP_HDRINCL,
+                   ICMP_TTL, 0, IP_PROTO_ICMP, inp);
+      if (ret != ERR_OK) {
+        LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ip_output_if returned an error: %c.\n", ret));
+      }
+    }
+    break;
+  default:
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n", 
+                (s16_t)type, (s16_t)code));
+    ICMP_STATS_INC(icmp.proterr);
+    ICMP_STATS_INC(icmp.drop);
+  }
+  pbuf_free(p);
+  return;
+lenerr:
+  pbuf_free(p);
+  ICMP_STATS_INC(icmp.lenerr);
+  snmp_inc_icmpinerrors();
+  return;
+#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN
+memerr:
+  pbuf_free(p);
+  ICMP_STATS_INC(icmp.err);
+  snmp_inc_icmpinerrors();
+  return;
+#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */
+}
+
+/**
+ * Send an icmp 'destination unreachable' packet, called from ip_input() if
+ * the transport layer protocol is unknown and from udp_input() if the local
+ * port is not bound.
+ *
+ * @param p the input packet for which the 'unreachable' should be sent,
+ *          p->payload pointing to the IP header
+ * @param t type of the 'unreachable' packet
+ */
+void
+icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
+{
+  icmp_send_response(p, ICMP_DUR, t);
+}
+
+#if IP_FORWARD || IP_REASSEMBLY
+/**
+ * Send a 'time exceeded' packet, called from ip_forward() if TTL is 0.
+ *
+ * @param p the input packet for which the 'time exceeded' should be sent,
+ *          p->payload pointing to the IP header
+ * @param t type of the 'time exceeded' packet
+ */
+void
+icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
+{
+  icmp_send_response(p, ICMP_TE, t);
+}
+
+#endif /* IP_FORWARD || IP_REASSEMBLY */
+
+/**
+ * Send an icmp packet in response to an incoming packet.
+ *
+ * @param p the input packet for which the 'unreachable' should be sent,
+ *          p->payload pointing to the IP header
+ * @param type Type of the ICMP header
+ * @param code Code of the ICMP header
+ */
+static void
+icmp_send_response(struct pbuf *p, u8_t type, u8_t code)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  /* we can use the echo header here */
+  struct icmp_echo_hdr *icmphdr;
+  ip_addr_t iphdr_src;
+
+  /* ICMP header + IP header + 8 bytes of data */
+  q = pbuf_alloc(PBUF_IP, sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE,
+                 PBUF_RAM);
+  if (q == NULL) {
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded: failed to allocate pbuf for ICMP packet.\n"));
+    return;
+  }
+  LWIP_ASSERT("check that first pbuf can hold icmp message",
+             (q->len >= (sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE)));
+
+  iphdr = (struct ip_hdr *)p->payload;
+  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded from "));
+  ip_addr_debug_print(ICMP_DEBUG, &(iphdr->src));
+  LWIP_DEBUGF(ICMP_DEBUG, (" to "));
+  ip_addr_debug_print(ICMP_DEBUG, &(iphdr->dest));
+  LWIP_DEBUGF(ICMP_DEBUG, ("\n"));
+
+  icmphdr = (struct icmp_echo_hdr *)q->payload;
+  icmphdr->type = type;
+  icmphdr->code = code;
+  icmphdr->id = 0;
+  icmphdr->seqno = 0;
+
+  /* copy fields from original packet */
+  SMEMCPY((u8_t *)q->payload + sizeof(struct icmp_echo_hdr), (u8_t *)p->payload,
+          IP_HLEN + ICMP_DEST_UNREACH_DATASIZE);
+
+  /* calculate checksum */
+  icmphdr->chksum = 0;
+  icmphdr->chksum = inet_chksum(icmphdr, q->len);
+  ICMP_STATS_INC(icmp.xmit);
+  /* increase number of messages attempted to send */
+  snmp_inc_icmpoutmsgs();
+  /* increase number of destination unreachable messages attempted to send */
+  snmp_inc_icmpouttimeexcds();
+  ip_addr_copy(iphdr_src, iphdr->src);
+  ip_output(q, NULL, &iphdr_src, ICMP_TTL, 0, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+#endif /* LWIP_ICMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/igmp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/igmp.c
new file mode 100644
index 0000000..4e4405e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/igmp.c
@@ -0,0 +1,817 @@
+/**
+ * @file
+ * IGMP - Internet Group Management Protocol
+ *
+ */
+
+/*
+ * Copyright (c) 2002 CITEL Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS''
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is a contribution to the lwIP TCP/IP stack.
+ * The Swedish Institute of Computer Science and Adam Dunkels
+ * are specifically granted permission to redistribute this
+ * source code.
+*/
+
+/*-------------------------------------------------------------
+Note 1)
+Although the rfc requires V1 AND V2 capability
+we will only support v2 since now V1 is very old (August 1989)
+V1 can be added if required
+
+a debug print and statistic have been implemented to
+show this up.
+-------------------------------------------------------------
+-------------------------------------------------------------
+Note 2)
+A query for a specific group address (as opposed to ALLHOSTS)
+has now been implemented as I am unsure if it is required
+
+a debug print and statistic have been implemented to
+show this up.
+-------------------------------------------------------------
+-------------------------------------------------------------
+Note 3)
+The router alert rfc 2113 is implemented in outgoing packets
+but not checked rigorously incoming
+-------------------------------------------------------------
+Steve Reynolds
+------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------------
+ * RFC 988  - Host extensions for IP multicasting                         - V0
+ * RFC 1054 - Host extensions for IP multicasting                         -
+ * RFC 1112 - Host extensions for IP multicasting                         - V1
+ * RFC 2236 - Internet Group Management Protocol, Version 2               - V2  <- this code is based on this RFC (it's the "de facto" standard)
+ * RFC 3376 - Internet Group Management Protocol, Version 3               - V3
+ * RFC 4604 - Using Internet Group Management Protocol Version 3...       - V3+
+ * RFC 2113 - IP Router Alert Option                                      - 
+ *----------------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------------
+ * Includes
+ *----------------------------------------------------------------------------*/
+
+#include "lwip/opt.h"
+
+#if LWIP_IGMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/igmp.h"
+#include "lwip/debug.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/ip.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/netif.h"
+#include "lwip/icmp.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+#include "lwip/stats.h"
+
+#include "string.h"
+
+/* 
+ * IGMP constants
+ */
+#define IGMP_TTL                       1
+#define IGMP_MINLEN                    8
+#define ROUTER_ALERT                   0x9404U
+#define ROUTER_ALERTLEN                4
+
+/*
+ * IGMP message types, including version number.
+ */
+#define IGMP_MEMB_QUERY                0x11 /* Membership query         */
+#define IGMP_V1_MEMB_REPORT            0x12 /* Ver. 1 membership report */
+#define IGMP_V2_MEMB_REPORT            0x16 /* Ver. 2 membership report */
+#define IGMP_LEAVE_GROUP               0x17 /* Leave-group message      */
+
+/* Group  membership states */
+#define IGMP_GROUP_NON_MEMBER          0
+#define IGMP_GROUP_DELAYING_MEMBER     1
+#define IGMP_GROUP_IDLE_MEMBER         2
+
+/**
+ * IGMP packet format.
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct igmp_msg {
+ PACK_STRUCT_FIELD(u8_t           igmp_msgtype);
+ PACK_STRUCT_FIELD(u8_t           igmp_maxresp);
+ PACK_STRUCT_FIELD(u16_t          igmp_checksum);
+ PACK_STRUCT_FIELD(ip_addr_p_t    igmp_group_address);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+
+static struct igmp_group *igmp_lookup_group(struct netif *ifp, ip_addr_t *addr);
+static err_t  igmp_remove_group(struct igmp_group *group);
+static void   igmp_timeout( struct igmp_group *group);
+static void   igmp_start_timer(struct igmp_group *group, u8_t max_time);
+static void   igmp_stop_timer(struct igmp_group *group);
+static void   igmp_delaying_member(struct igmp_group *group, u8_t maxresp);
+static err_t  igmp_ip_output_if(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest, struct netif *netif);
+static void   igmp_send(struct igmp_group *group, u8_t type);
+
+
+static struct igmp_group* igmp_group_list;
+static ip_addr_t     allsystems;
+static ip_addr_t     allrouters;
+
+
+/**
+ * Initialize the IGMP module
+ */
+void
+igmp_init(void)
+{
+  LWIP_DEBUGF(IGMP_DEBUG, ("igmp_init: initializing\n"));
+
+  IP4_ADDR(&allsystems, 224, 0, 0, 1);
+  IP4_ADDR(&allrouters, 224, 0, 0, 2);
+}
+
+#ifdef LWIP_DEBUG
+/**
+ * Dump global IGMP groups list
+ */
+void
+igmp_dump_group_list()
+{ 
+  struct igmp_group *group = igmp_group_list;
+
+  while (group != NULL) {
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_dump_group_list: [%"U32_F"] ", (u32_t)(group->group_state)));
+    ip_addr_debug_print(IGMP_DEBUG, &group->group_address);
+    LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", group->netif));
+    group = group->next;
+  }
+  LWIP_DEBUGF(IGMP_DEBUG, ("\n"));
+}
+#else
+#define igmp_dump_group_list()
+#endif /* LWIP_DEBUG */
+
+/**
+ * Start IGMP processing on interface
+ *
+ * @param netif network interface on which start IGMP processing
+ */
+err_t
+igmp_start(struct netif *netif)
+{
+  struct igmp_group* group;
+
+  LWIP_DEBUGF(IGMP_DEBUG, ("igmp_start: starting IGMP processing on if %p\n", netif));
+
+  group = igmp_lookup_group(netif, &allsystems);
+
+  if (group != NULL) {
+    group->group_state = IGMP_GROUP_IDLE_MEMBER;
+    group->use++;
+
+    /* Allow the igmp messages at the MAC level */
+    if (netif->igmp_mac_filter != NULL) {
+      LWIP_DEBUGF(IGMP_DEBUG, ("igmp_start: igmp_mac_filter(ADD "));
+      ip_addr_debug_print(IGMP_DEBUG, &allsystems);
+      LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", netif));
+      netif->igmp_mac_filter(netif, &allsystems, IGMP_ADD_MAC_FILTER);
+    }
+
+    return ERR_OK;
+  }
+
+  return ERR_MEM;
+}
+
+/**
+ * Stop IGMP processing on interface
+ *
+ * @param netif network interface on which stop IGMP processing
+ */
+err_t
+igmp_stop(struct netif *netif)
+{
+  struct igmp_group *group = igmp_group_list;
+  struct igmp_group *prev  = NULL;
+  struct igmp_group *next;
+
+  /* look for groups joined on this interface further down the list */
+  while (group != NULL) {
+    next = group->next;
+    /* is it a group joined on this interface? */
+    if (group->netif == netif) {
+      /* is it the first group of the list? */
+      if (group == igmp_group_list) {
+        igmp_group_list = next;
+      }
+      /* is there a "previous" group defined? */
+      if (prev != NULL) {
+        prev->next = next;
+      }
+      /* disable the group at the MAC level */
+      if (netif->igmp_mac_filter != NULL) {
+        LWIP_DEBUGF(IGMP_DEBUG, ("igmp_stop: igmp_mac_filter(DEL "));
+        ip_addr_debug_print(IGMP_DEBUG, &group->group_address);
+        LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", netif));
+        netif->igmp_mac_filter(netif, &(group->group_address), IGMP_DEL_MAC_FILTER);
+      }
+      /* free group */
+      memp_free(MEMP_IGMP_GROUP, group);
+    } else {
+      /* change the "previous" */
+      prev = group;
+    }
+    /* move to "next" */
+    group = next;
+  }
+  return ERR_OK;
+}
+
+/**
+ * Report IGMP memberships for this interface
+ *
+ * @param netif network interface on which report IGMP memberships
+ */
+void
+igmp_report_groups(struct netif *netif)
+{
+  struct igmp_group *group = igmp_group_list;
+
+  LWIP_DEBUGF(IGMP_DEBUG, ("igmp_report_groups: sending IGMP reports on if %p\n", netif));
+
+  while (group != NULL) {
+    if (group->netif == netif) {
+      igmp_delaying_member(group, IGMP_JOIN_DELAYING_MEMBER_TMR);
+    }
+    group = group->next;
+  }
+}
+
+/**
+ * Search for a group in the global igmp_group_list
+ *
+ * @param ifp the network interface for which to look
+ * @param addr the group ip address to search for
+ * @return a struct igmp_group* if the group has been found,
+ *         NULL if the group wasn't found.
+ */
+struct igmp_group *
+igmp_lookfor_group(struct netif *ifp, ip_addr_t *addr)
+{
+  struct igmp_group *group = igmp_group_list;
+
+  while (group != NULL) {
+    if ((group->netif == ifp) && (ip_addr_cmp(&(group->group_address), addr))) {
+      return group;
+    }
+    group = group->next;
+  }
+
+  /* to be clearer, we return NULL here instead of
+   * 'group' (which is also NULL at this point).
+   */
+  return NULL;
+}
+
+/**
+ * Search for a specific igmp group and create a new one if not found-
+ *
+ * @param ifp the network interface for which to look
+ * @param addr the group ip address to search
+ * @return a struct igmp_group*,
+ *         NULL on memory error.
+ */
+struct igmp_group *
+igmp_lookup_group(struct netif *ifp, ip_addr_t *addr)
+{
+  struct igmp_group *group = igmp_group_list;
+  
+  /* Search if the group already exists */
+  group = igmp_lookfor_group(ifp, addr);
+  if (group != NULL) {
+    /* Group already exists. */
+    return group;
+  }
+
+  /* Group doesn't exist yet, create a new one */
+  group = (struct igmp_group *)memp_malloc(MEMP_IGMP_GROUP);
+  if (group != NULL) {
+    group->netif              = ifp;
+    ip_addr_set(&(group->group_address), addr);
+    group->timer              = 0; /* Not running */
+    group->group_state        = IGMP_GROUP_NON_MEMBER;
+    group->last_reporter_flag = 0;
+    group->use                = 0;
+    group->next               = igmp_group_list;
+    
+    igmp_group_list = group;
+  }
+
+  LWIP_DEBUGF(IGMP_DEBUG, ("igmp_lookup_group: %sallocated a new group with address ", (group?"":"impossible to ")));
+  ip_addr_debug_print(IGMP_DEBUG, addr);
+  LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", ifp));
+
+  return group;
+}
+
+/**
+ * Remove a group in the global igmp_group_list
+ *
+ * @param group the group to remove from the global igmp_group_list
+ * @return ERR_OK if group was removed from the list, an err_t otherwise
+ */
+static err_t
+igmp_remove_group(struct igmp_group *group)
+{
+  err_t err = ERR_OK;
+
+  /* Is it the first group? */
+  if (igmp_group_list == group) {
+    igmp_group_list = group->next;
+  } else {
+    /* look for group further down the list */
+    struct igmp_group *tmpGroup;
+    for (tmpGroup = igmp_group_list; tmpGroup != NULL; tmpGroup = tmpGroup->next) {
+      if (tmpGroup->next == group) {
+        tmpGroup->next = group->next;
+        break;
+      }
+    }
+    /* Group not found in the global igmp_group_list */
+    if (tmpGroup == NULL)
+      err = ERR_ARG;
+  }
+  /* free group */
+  memp_free(MEMP_IGMP_GROUP, group);
+
+  return err;
+}
+
+/**
+ * Called from ip_input() if a new IGMP packet is received.
+ *
+ * @param p received igmp packet, p->payload pointing to the ip header
+ * @param inp network interface on which the packet was received
+ * @param dest destination ip address of the igmp packet
+ */
+void
+igmp_input(struct pbuf *p, struct netif *inp, ip_addr_t *dest)
+{
+  struct ip_hdr *    iphdr;
+  struct igmp_msg*   igmp;
+  struct igmp_group* group;
+  struct igmp_group* groupref;
+
+  IGMP_STATS_INC(igmp.recv);
+
+  /* Note that the length CAN be greater than 8 but only 8 are used - All are included in the checksum */    
+  iphdr = (struct ip_hdr *)p->payload;
+  if (pbuf_header(p, -(s16_t)(IPH_HL(iphdr) * 4)) || (p->len < IGMP_MINLEN)) {
+    pbuf_free(p);
+    IGMP_STATS_INC(igmp.lenerr);
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: length error\n"));
+    return;
+  }
+
+  LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: message from "));
+  ip_addr_debug_print(IGMP_DEBUG, &(iphdr->src));
+  LWIP_DEBUGF(IGMP_DEBUG, (" to address "));
+  ip_addr_debug_print(IGMP_DEBUG, &(iphdr->dest));
+  LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", inp));
+
+  /* Now calculate and check the checksum */
+  igmp = (struct igmp_msg *)p->payload;
+  if (inet_chksum(igmp, p->len)) {
+    pbuf_free(p);
+    IGMP_STATS_INC(igmp.chkerr);
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: checksum error\n"));
+    return;
+  }
+
+  /* Packet is ok so find an existing group */
+  group = igmp_lookfor_group(inp, dest); /* use the destination IP address of incoming packet */
+  
+  /* If group can be found or create... */
+  if (!group) {
+    pbuf_free(p);
+    IGMP_STATS_INC(igmp.drop);
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP frame not for us\n"));
+    return;
+  }
+
+  /* NOW ACT ON THE INCOMING MESSAGE TYPE... */
+  switch (igmp->igmp_msgtype) {
+   case IGMP_MEMB_QUERY: {
+     /* IGMP_MEMB_QUERY to the "all systems" address ? */
+     if ((ip_addr_cmp(dest, &allsystems)) && ip_addr_isany(&igmp->igmp_group_address)) {
+       /* THIS IS THE GENERAL QUERY */
+       LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: General IGMP_MEMB_QUERY on \"ALL SYSTEMS\" address (224.0.0.1) [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp)));
+
+       if (igmp->igmp_maxresp == 0) {
+         IGMP_STATS_INC(igmp.rx_v1);
+         LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: got an all hosts query with time== 0 - this is V1 and not implemented - treat as v2\n"));
+         igmp->igmp_maxresp = IGMP_V1_DELAYING_MEMBER_TMR;
+       } else {
+         IGMP_STATS_INC(igmp.rx_general);
+       }
+
+       groupref = igmp_group_list;
+       while (groupref) {
+         /* Do not send messages on the all systems group address! */
+         if ((groupref->netif == inp) && (!(ip_addr_cmp(&(groupref->group_address), &allsystems)))) {
+           igmp_delaying_member(groupref, igmp->igmp_maxresp);
+         }
+         groupref = groupref->next;
+       }
+     } else {
+       /* IGMP_MEMB_QUERY to a specific group ? */
+       if (!ip_addr_isany(&igmp->igmp_group_address)) {
+         LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP_MEMB_QUERY to a specific group "));
+         ip_addr_debug_print(IGMP_DEBUG, &igmp->igmp_group_address);
+         if (ip_addr_cmp(dest, &allsystems)) {
+           ip_addr_t groupaddr;
+           LWIP_DEBUGF(IGMP_DEBUG, (" using \"ALL SYSTEMS\" address (224.0.0.1) [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp)));
+           /* we first need to re-look for the group since we used dest last time */
+           ip_addr_copy(groupaddr, igmp->igmp_group_address);
+           group = igmp_lookfor_group(inp, &groupaddr);
+         } else {
+           LWIP_DEBUGF(IGMP_DEBUG, (" with the group address as destination [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp)));
+         }
+
+         if (group != NULL) {
+           IGMP_STATS_INC(igmp.rx_group);
+           igmp_delaying_member(group, igmp->igmp_maxresp);
+         } else {
+           IGMP_STATS_INC(igmp.drop);
+         }
+       } else {
+         IGMP_STATS_INC(igmp.proterr);
+       }
+     }
+     break;
+   }
+   case IGMP_V2_MEMB_REPORT: {
+     LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP_V2_MEMB_REPORT\n"));
+     IGMP_STATS_INC(igmp.rx_report);
+     if (group->group_state == IGMP_GROUP_DELAYING_MEMBER) {
+       /* This is on a specific group we have already looked up */
+       group->timer = 0; /* stopped */
+       group->group_state = IGMP_GROUP_IDLE_MEMBER;
+       group->last_reporter_flag = 0;
+     }
+     break;
+   }
+   default: {
+     LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: unexpected msg %d in state %d on group %p on if %p\n",
+       igmp->igmp_msgtype, group->group_state, &group, group->netif));
+     IGMP_STATS_INC(igmp.proterr);
+     break;
+   }
+  }
+
+  pbuf_free(p);
+  return;
+}
+
+/**
+ * Join a group on one network interface.
+ *
+ * @param ifaddr ip address of the network interface which should join a new group
+ * @param groupaddr the ip address of the group which to join
+ * @return ERR_OK if group was joined on the netif(s), an err_t otherwise
+ */
+err_t
+igmp_joingroup(ip_addr_t *ifaddr, ip_addr_t *groupaddr)
+{
+  err_t              err = ERR_VAL; /* no matching interface */
+  struct igmp_group *group;
+  struct netif      *netif;
+
+  /* make sure it is multicast address */
+  LWIP_ERROR("igmp_joingroup: attempt to join non-multicast address", ip_addr_ismulticast(groupaddr), return ERR_VAL;);
+  LWIP_ERROR("igmp_joingroup: attempt to join allsystems address", (!ip_addr_cmp(groupaddr, &allsystems)), return ERR_VAL;);
+
+  /* loop through netif's */
+  netif = netif_list;
+  while (netif != NULL) {
+    /* Should we join this interface ? */
+    if ((netif->flags & NETIF_FLAG_IGMP) && ((ip_addr_isany(ifaddr) || ip_addr_cmp(&(netif->ip_addr), ifaddr)))) {
+      /* find group or create a new one if not found */
+      group = igmp_lookup_group(netif, groupaddr);
+
+      if (group != NULL) {
+        /* This should create a new group, check the state to make sure */
+        if (group->group_state != IGMP_GROUP_NON_MEMBER) {
+          LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup: join to group not in state IGMP_GROUP_NON_MEMBER\n"));
+        } else {
+          /* OK - it was new group */
+          LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup: join to new group: "));
+          ip_addr_debug_print(IGMP_DEBUG, groupaddr);
+          LWIP_DEBUGF(IGMP_DEBUG, ("\n"));
+
+          /* If first use of the group, allow the group at the MAC level */
+          if ((group->use==0) && (netif->igmp_mac_filter != NULL)) {
+            LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup: igmp_mac_filter(ADD "));
+            ip_addr_debug_print(IGMP_DEBUG, groupaddr);
+            LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", netif));
+            netif->igmp_mac_filter(netif, groupaddr, IGMP_ADD_MAC_FILTER);
+          }
+
+          IGMP_STATS_INC(igmp.tx_join);
+          igmp_send(group, IGMP_V2_MEMB_REPORT);
+
+          igmp_start_timer(group, IGMP_JOIN_DELAYING_MEMBER_TMR);
+
+          /* Need to work out where this timer comes from */
+          group->group_state = IGMP_GROUP_DELAYING_MEMBER;
+        }
+        /* Increment group use */
+        group->use++;
+        /* Join on this interface */
+        err = ERR_OK;
+      } else {
+        /* Return an error even if some network interfaces are joined */
+        /** @todo undo any other netif already joined */
+        LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup: Not enought memory to join to group\n"));
+        return ERR_MEM;
+      }
+    }
+    /* proceed to next network interface */
+    netif = netif->next;
+  }
+
+  return err;
+}
+
+/**
+ * Leave a group on one network interface.
+ *
+ * @param ifaddr ip address of the network interface which should leave a group
+ * @param groupaddr the ip address of the group which to leave
+ * @return ERR_OK if group was left on the netif(s), an err_t otherwise
+ */
+err_t
+igmp_leavegroup(ip_addr_t *ifaddr, ip_addr_t *groupaddr)
+{
+  err_t              err = ERR_VAL; /* no matching interface */
+  struct igmp_group *group;
+  struct netif      *netif;
+
+  /* make sure it is multicast address */
+  LWIP_ERROR("igmp_leavegroup: attempt to leave non-multicast address", ip_addr_ismulticast(groupaddr), return ERR_VAL;);
+  LWIP_ERROR("igmp_leavegroup: attempt to leave allsystems address", (!ip_addr_cmp(groupaddr, &allsystems)), return ERR_VAL;);
+
+  /* loop through netif's */
+  netif = netif_list;
+  while (netif != NULL) {
+    /* Should we leave this interface ? */
+    if ((netif->flags & NETIF_FLAG_IGMP) && ((ip_addr_isany(ifaddr) || ip_addr_cmp(&(netif->ip_addr), ifaddr)))) {
+      /* find group */
+      group = igmp_lookfor_group(netif, groupaddr);
+
+      if (group != NULL) {
+        /* Only send a leave if the flag is set according to the state diagram */
+        LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: Leaving group: "));
+        ip_addr_debug_print(IGMP_DEBUG, groupaddr);
+        LWIP_DEBUGF(IGMP_DEBUG, ("\n"));
+
+        /* If there is no other use of the group */
+        if (group->use <= 1) {
+          /* If we are the last reporter for this group */
+          if (group->last_reporter_flag) {
+            LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: sending leaving group\n"));
+            IGMP_STATS_INC(igmp.tx_leave);
+            igmp_send(group, IGMP_LEAVE_GROUP);
+          }
+          
+          /* Disable the group at the MAC level */
+          if (netif->igmp_mac_filter != NULL) {
+            LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: igmp_mac_filter(DEL "));
+            ip_addr_debug_print(IGMP_DEBUG, groupaddr);
+            LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", netif));
+            netif->igmp_mac_filter(netif, groupaddr, IGMP_DEL_MAC_FILTER);
+          }
+          
+          LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: remove group: "));
+          ip_addr_debug_print(IGMP_DEBUG, groupaddr);
+          LWIP_DEBUGF(IGMP_DEBUG, ("\n"));          
+          
+          /* Free the group */
+          igmp_remove_group(group);
+        } else {
+          /* Decrement group use */
+          group->use--;
+        }
+        /* Leave on this interface */
+        err = ERR_OK;
+      } else {
+        /* It's not a fatal error on "leavegroup" */
+        LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup: not member of group\n"));
+      }
+    }
+    /* proceed to next network interface */
+    netif = netif->next;
+  }
+
+  return err;
+}
+
+/**
+ * The igmp timer function (both for NO_SYS=1 and =0)
+ * Should be called every IGMP_TMR_INTERVAL milliseconds (100 ms is default).
+ */
+void
+igmp_tmr(void)
+{
+  struct igmp_group *group = igmp_group_list;
+
+  while (group != NULL) {
+    if (group->timer > 0) {
+      group->timer--;
+      if (group->timer == 0) {
+        igmp_timeout(group);
+      }
+    }
+    group = group->next;
+  }
+}
+
+/**
+ * Called if a timeout for one group is reached.
+ * Sends a report for this group.
+ *
+ * @param group an igmp_group for which a timeout is reached
+ */
+static void
+igmp_timeout(struct igmp_group *group)
+{
+  /* If the state is IGMP_GROUP_DELAYING_MEMBER then we send a report for this group */
+  if (group->group_state == IGMP_GROUP_DELAYING_MEMBER) {
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_timeout: report membership for group with address "));
+    ip_addr_debug_print(IGMP_DEBUG, &(group->group_address));
+    LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", group->netif));
+
+    IGMP_STATS_INC(igmp.tx_report);
+    igmp_send(group, IGMP_V2_MEMB_REPORT);
+  }
+}
+
+/**
+ * Start a timer for an igmp group
+ *
+ * @param group the igmp_group for which to start a timer
+ * @param max_time the time in multiples of IGMP_TMR_INTERVAL (decrease with
+ *        every call to igmp_tmr())
+ */
+static void
+igmp_start_timer(struct igmp_group *group, u8_t max_time)
+{
+  /* ensure the input value is > 0 */
+  if (max_time == 0) {
+    max_time = 1;
+  }
+  /* ensure the random value is > 0 */
+  group->timer = (LWIP_RAND() % (max_time - 1)) + 1;
+}
+
+/**
+ * Stop a timer for an igmp_group
+ *
+ * @param group the igmp_group for which to stop the timer
+ */
+static void
+igmp_stop_timer(struct igmp_group *group)
+{
+  group->timer = 0;
+}
+
+/**
+ * Delaying membership report for a group if necessary
+ *
+ * @param group the igmp_group for which "delaying" membership report
+ * @param maxresp query delay
+ */
+static void
+igmp_delaying_member(struct igmp_group *group, u8_t maxresp)
+{
+  if ((group->group_state == IGMP_GROUP_IDLE_MEMBER) ||
+     ((group->group_state == IGMP_GROUP_DELAYING_MEMBER) &&
+      ((group->timer == 0) || (maxresp < group->timer)))) {
+    igmp_start_timer(group, maxresp);
+    group->group_state = IGMP_GROUP_DELAYING_MEMBER;
+  }
+}
+
+
+/**
+ * Sends an IP packet on a network interface. This function constructs the IP header
+ * and calculates the IP header checksum. If the source IP address is NULL,
+ * the IP address of the outgoing network interface is filled in as source address.
+ *
+ * @param p the packet to send (p->payload points to the data, e.g. next
+            protocol header; if dest == IP_HDRINCL, p already includes an IP
+            header and p->payload points to that IP header)
+ * @param src the source IP address to send from (if src == IP_ADDR_ANY, the
+ *         IP  address of the netif used to send is used as source address)
+ * @param dest the destination IP address to send the packet to
+ * @param ttl the TTL value to be set in the IP header
+ * @param proto the PROTOCOL to be set in the IP header
+ * @param netif the netif on which to send this packet
+ * @return ERR_OK if the packet was sent OK
+ *         ERR_BUF if p doesn't have enough space for IP/LINK headers
+ *         returns errors returned by netif->output
+ */
+static err_t
+igmp_ip_output_if(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest, struct netif *netif)
+{
+  /* This is the "router alert" option */
+  u16_t ra[2];
+  ra[0] = PP_HTONS(ROUTER_ALERT);
+  ra[1] = 0x0000; /* Router shall examine packet */
+  IGMP_STATS_INC(igmp.xmit);
+  return ip_output_if_opt(p, src, dest, IGMP_TTL, 0, IP_PROTO_IGMP, netif, ra, ROUTER_ALERTLEN);
+}
+
+/**
+ * Send an igmp packet to a specific group.
+ *
+ * @param group the group to which to send the packet
+ * @param type the type of igmp packet to send
+ */
+static void
+igmp_send(struct igmp_group *group, u8_t type)
+{
+  struct pbuf*     p    = NULL;
+  struct igmp_msg* igmp = NULL;
+  ip_addr_t   src  = *IP_ADDR_ANY;
+  ip_addr_t*  dest = NULL;
+
+  /* IP header + "router alert" option + IGMP header */
+  p = pbuf_alloc(PBUF_TRANSPORT, IGMP_MINLEN, PBUF_RAM);
+  
+  if (p) {
+    igmp = (struct igmp_msg *)p->payload;
+    LWIP_ASSERT("igmp_send: check that first pbuf can hold struct igmp_msg",
+               (p->len >= sizeof(struct igmp_msg)));
+    ip_addr_copy(src, group->netif->ip_addr);
+     
+    if (type == IGMP_V2_MEMB_REPORT) {
+      dest = &(group->group_address);
+      ip_addr_copy(igmp->igmp_group_address, group->group_address);
+      group->last_reporter_flag = 1; /* Remember we were the last to report */
+    } else {
+      if (type == IGMP_LEAVE_GROUP) {
+        dest = &allrouters;
+        ip_addr_copy(igmp->igmp_group_address, group->group_address);
+      }
+    }
+
+    if ((type == IGMP_V2_MEMB_REPORT) || (type == IGMP_LEAVE_GROUP)) {
+      igmp->igmp_msgtype  = type;
+      igmp->igmp_maxresp  = 0;
+      igmp->igmp_checksum = 0;
+      igmp->igmp_checksum = inet_chksum(igmp, IGMP_MINLEN);
+
+      igmp_ip_output_if(p, &src, dest, group->netif);
+    }
+
+    pbuf_free(p);
+  } else {
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_send: not enough memory for igmp_send\n"));
+    IGMP_STATS_INC(igmp.memerr);
+  }
+}
+
+#endif /* LWIP_IGMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/inet.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/inet.c
new file mode 100644
index 0000000..e283a57
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/inet.c
@@ -0,0 +1,42 @@
+/**
+ * @file
+ * Functions common to all TCP/IPv4 modules, such as the byte order functions.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/inet.h"
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/inet_chksum.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/inet_chksum.c
new file mode 100644
index 0000000..960252f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/inet_chksum.c
@@ -0,0 +1,450 @@
+/**
+ * @file
+ * Incluse internet checksum functions.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/inet_chksum.h"
+#include "lwip/def.h"
+
+#include 
+#include 
+
+/* These are some reference implementations of the checksum algorithm, with the
+ * aim of being simple, correct and fully portable. Checksumming is the
+ * first thing you would want to optimize for your platform. If you create
+ * your own version, link it in and in your cc.h put:
+ * 
+ * #define LWIP_CHKSUM  
+ *
+ * Or you can select from the implementations below by defining
+ * LWIP_CHKSUM_ALGORITHM to 1, 2 or 3.
+ */
+
+#ifndef LWIP_CHKSUM
+# define LWIP_CHKSUM lwip_standard_chksum
+# ifndef LWIP_CHKSUM_ALGORITHM
+#  define LWIP_CHKSUM_ALGORITHM 2
+# endif
+#endif
+/* If none set: */
+#ifndef LWIP_CHKSUM_ALGORITHM
+# define LWIP_CHKSUM_ALGORITHM 0
+#endif
+
+#if (LWIP_CHKSUM_ALGORITHM == 1) /* Version #1 */
+/**
+ * lwip checksum
+ *
+ * @param dataptr points to start of data to be summed at any boundary
+ * @param len length of data to be summed
+ * @return host order (!) lwip checksum (non-inverted Internet sum) 
+ *
+ * @note accumulator size limits summable length to 64k
+ * @note host endianess is irrelevant (p3 RFC1071)
+ */
+static u16_t
+lwip_standard_chksum(void *dataptr, u16_t len)
+{
+  u32_t acc;
+  u16_t src;
+  u8_t *octetptr;
+
+  acc = 0;
+  /* dataptr may be at odd or even addresses */
+  octetptr = (u8_t*)dataptr;
+  while (len > 1) {
+    /* declare first octet as most significant
+       thus assume network order, ignoring host order */
+    src = (*octetptr) << 8;
+    octetptr++;
+    /* declare second octet as least significant */
+    src |= (*octetptr);
+    octetptr++;
+    acc += src;
+    len -= 2;
+  }
+  if (len > 0) {
+    /* accumulate remaining octet */
+    src = (*octetptr) << 8;
+    acc += src;
+  }
+  /* add deferred carry bits */
+  acc = (acc >> 16) + (acc & 0x0000ffffUL);
+  if ((acc & 0xffff0000UL) != 0) {
+    acc = (acc >> 16) + (acc & 0x0000ffffUL);
+  }
+  /* This maybe a little confusing: reorder sum using htons()
+     instead of ntohs() since it has a little less call overhead.
+     The caller must invert bits for Internet sum ! */
+  return htons((u16_t)acc);
+}
+#endif
+
+#if (LWIP_CHKSUM_ALGORITHM == 2) /* Alternative version #2 */
+/*
+ * Curt McDowell
+ * Broadcom Corp.
+ * csm@broadcom.com
+ *
+ * IP checksum two bytes at a time with support for
+ * unaligned buffer.
+ * Works for len up to and including 0x20000.
+ * by Curt McDowell, Broadcom Corp. 12/08/2005
+ *
+ * @param dataptr points to start of data to be summed at any boundary
+ * @param len length of data to be summed
+ * @return host order (!) lwip checksum (non-inverted Internet sum) 
+ */
+
+static u16_t
+lwip_standard_chksum(void *dataptr, int len)
+{
+  u8_t *pb = (u8_t *)dataptr;
+  u16_t *ps, t = 0;
+  u32_t sum = 0;
+  int odd = ((mem_ptr_t)pb & 1);
+
+  /* Get aligned to u16_t */
+  if (odd && len > 0) {
+    ((u8_t *)&t)[1] = *pb++;
+    len--;
+  }
+
+  /* Add the bulk of the data */
+  ps = (u16_t *)(void *)pb;
+  while (len > 1) {
+    sum += *ps++;
+    len -= 2;
+  }
+
+  /* Consume left-over byte, if any */
+  if (len > 0) {
+    ((u8_t *)&t)[0] = *(u8_t *)ps;
+  }
+
+  /* Add end bytes */
+  sum += t;
+
+  /* Fold 32-bit sum to 16 bits
+     calling this twice is propably faster than if statements... */
+  sum = FOLD_U32T(sum);
+  sum = FOLD_U32T(sum);
+
+  /* Swap if alignment was odd */
+  if (odd) {
+    sum = SWAP_BYTES_IN_WORD(sum);
+  }
+
+  return (u16_t)sum;
+}
+#endif
+
+#if (LWIP_CHKSUM_ALGORITHM == 3) /* Alternative version #3 */
+/**
+ * An optimized checksum routine. Basically, it uses loop-unrolling on
+ * the checksum loop, treating the head and tail bytes specially, whereas
+ * the inner loop acts on 8 bytes at a time. 
+ *
+ * @arg start of buffer to be checksummed. May be an odd byte address.
+ * @len number of bytes in the buffer to be checksummed.
+ * @return host order (!) lwip checksum (non-inverted Internet sum) 
+ * 
+ * by Curt McDowell, Broadcom Corp. December 8th, 2005
+ */
+
+static u16_t
+lwip_standard_chksum(void *dataptr, int len)
+{
+  u8_t *pb = (u8_t *)dataptr;
+  u16_t *ps, t = 0;
+  u32_t *pl;
+  u32_t sum = 0, tmp;
+  /* starts at odd byte address? */
+  int odd = ((mem_ptr_t)pb & 1);
+
+  if (odd && len > 0) {
+    ((u8_t *)&t)[1] = *pb++;
+    len--;
+  }
+
+  ps = (u16_t *)pb;
+
+  if (((mem_ptr_t)ps & 3) && len > 1) {
+    sum += *ps++;
+    len -= 2;
+  }
+
+  pl = (u32_t *)ps;
+
+  while (len > 7)  {
+    tmp = sum + *pl++;          /* ping */
+    if (tmp < sum) {
+      tmp++;                    /* add back carry */
+    }
+
+    sum = tmp + *pl++;          /* pong */
+    if (sum < tmp) {
+      sum++;                    /* add back carry */
+    }
+
+    len -= 8;
+  }
+
+  /* make room in upper bits */
+  sum = FOLD_U32T(sum);
+
+  ps = (u16_t *)pl;
+
+  /* 16-bit aligned word remaining? */
+  while (len > 1) {
+    sum += *ps++;
+    len -= 2;
+  }
+
+  /* dangling tail byte remaining? */
+  if (len > 0) {                /* include odd byte */
+    ((u8_t *)&t)[0] = *(u8_t *)ps;
+  }
+
+  sum += t;                     /* add end bytes */
+
+  /* Fold 32-bit sum to 16 bits
+     calling this twice is propably faster than if statements... */
+  sum = FOLD_U32T(sum);
+  sum = FOLD_U32T(sum);
+
+  if (odd) {
+    sum = SWAP_BYTES_IN_WORD(sum);
+  }
+
+  return (u16_t)sum;
+}
+#endif
+
+/* inet_chksum_pseudo:
+ *
+ * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
+ * IP addresses are expected to be in network byte order.
+ *
+ * @param p chain of pbufs over that a checksum should be calculated (ip data part)
+ * @param src source ip address (used for checksum of pseudo header)
+ * @param dst destination ip address (used for checksum of pseudo header)
+ * @param proto ip protocol (used for checksum of pseudo header)
+ * @param proto_len length of the ip data part (used for checksum of pseudo header)
+ * @return checksum (as u16_t) to be saved directly in the protocol header
+ */
+u16_t
+inet_chksum_pseudo(struct pbuf *p,
+       ip_addr_t *src, ip_addr_t *dest,
+       u8_t proto, u16_t proto_len)
+{
+  u32_t acc;
+  u32_t addr;
+  struct pbuf *q;
+  u8_t swapped;
+
+  acc = 0;
+  swapped = 0;
+  /* iterate through all pbuf in chain */
+  for(q = p; q != NULL; q = q->next) {
+    LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n",
+      (void *)q, (void *)q->next));
+    acc += LWIP_CHKSUM(q->payload, q->len);
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/
+    /* just executing this next line is probably faster that the if statement needed
+       to check whether we really need to execute it, and does no harm */
+    acc = FOLD_U32T(acc);
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = SWAP_BYTES_IN_WORD(acc);
+    }
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/
+  }
+
+  if (swapped) {
+    acc = SWAP_BYTES_IN_WORD(acc);
+  }
+  addr = ip4_addr_get_u32(src);
+  acc += (addr & 0xffffUL);
+  acc += ((addr >> 16) & 0xffffUL);
+  addr = ip4_addr_get_u32(dest);
+  acc += (addr & 0xffffUL);
+  acc += ((addr >> 16) & 0xffffUL);
+  acc += (u32_t)htons((u16_t)proto);
+  acc += (u32_t)htons(proto_len);
+
+  /* Fold 32-bit sum to 16 bits
+     calling this twice is propably faster than if statements... */
+  acc = FOLD_U32T(acc);
+  acc = FOLD_U32T(acc);
+  LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc));
+  return (u16_t)~(acc & 0xffffUL);
+}
+
+/* inet_chksum_pseudo:
+ *
+ * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
+ * IP addresses are expected to be in network byte order.
+ *
+ * @param p chain of pbufs over that a checksum should be calculated (ip data part)
+ * @param src source ip address (used for checksum of pseudo header)
+ * @param dst destination ip address (used for checksum of pseudo header)
+ * @param proto ip protocol (used for checksum of pseudo header)
+ * @param proto_len length of the ip data part (used for checksum of pseudo header)
+ * @return checksum (as u16_t) to be saved directly in the protocol header
+ */
+u16_t
+inet_chksum_pseudo_partial(struct pbuf *p,
+       ip_addr_t *src, ip_addr_t *dest,
+       u8_t proto, u16_t proto_len, u16_t chksum_len)
+{
+  u32_t acc;
+  u32_t addr;
+  struct pbuf *q;
+  u8_t swapped;
+  u16_t chklen;
+
+  acc = 0;
+  swapped = 0;
+  /* iterate through all pbuf in chain */
+  for(q = p; (q != NULL) && (chksum_len > 0); q = q->next) {
+    LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n",
+      (void *)q, (void *)q->next));
+    chklen = q->len;
+    if (chklen > chksum_len) {
+      chklen = chksum_len;
+    }
+    acc += LWIP_CHKSUM(q->payload, chklen);
+    chksum_len -= chklen;
+    LWIP_ASSERT("delete me", chksum_len < 0x7fff);
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/
+    /* fold the upper bit down */
+    acc = FOLD_U32T(acc);
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = SWAP_BYTES_IN_WORD(acc);
+    }
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/
+  }
+
+  if (swapped) {
+    acc = SWAP_BYTES_IN_WORD(acc);
+  }
+  addr = ip4_addr_get_u32(src);
+  acc += (addr & 0xffffUL);
+  acc += ((addr >> 16) & 0xffffUL);
+  addr = ip4_addr_get_u32(dest);
+  acc += (addr & 0xffffUL);
+  acc += ((addr >> 16) & 0xffffUL);
+  acc += (u32_t)htons((u16_t)proto);
+  acc += (u32_t)htons(proto_len);
+
+  /* Fold 32-bit sum to 16 bits
+     calling this twice is propably faster than if statements... */
+  acc = FOLD_U32T(acc);
+  acc = FOLD_U32T(acc);
+  LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc));
+  return (u16_t)~(acc & 0xffffUL);
+}
+
+/* inet_chksum:
+ *
+ * Calculates the Internet checksum over a portion of memory. Used primarily for IP
+ * and ICMP.
+ *
+ * @param dataptr start of the buffer to calculate the checksum (no alignment needed)
+ * @param len length of the buffer to calculate the checksum
+ * @return checksum (as u16_t) to be saved directly in the protocol header
+ */
+
+u16_t
+inet_chksum(void *dataptr, u16_t len)
+{
+  return ~LWIP_CHKSUM(dataptr, len);
+}
+
+/**
+ * Calculate a checksum over a chain of pbufs (without pseudo-header, much like
+ * inet_chksum only pbufs are used).
+ *
+ * @param p pbuf chain over that the checksum should be calculated
+ * @return checksum (as u16_t) to be saved directly in the protocol header
+ */
+u16_t
+inet_chksum_pbuf(struct pbuf *p)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped;
+
+  acc = 0;
+  swapped = 0;
+  for(q = p; q != NULL; q = q->next) {
+    acc += LWIP_CHKSUM(q->payload, q->len);
+    acc = FOLD_U32T(acc);
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = SWAP_BYTES_IN_WORD(acc);
+    }
+  }
+
+  if (swapped) {
+    acc = SWAP_BYTES_IN_WORD(acc);
+  }
+  return (u16_t)~(acc & 0xffffUL);
+}
+
+/* These are some implementations for LWIP_CHKSUM_COPY, which copies data
+ * like MEMCPY but generates a checksum at the same time. Since this is a
+ * performance-sensitive function, you might want to create your own version
+ * in assembly targeted at your hardware by defining it in lwipopts.h:
+ *   #define LWIP_CHKSUM_COPY(dst, src, len) your_chksum_copy(dst, src, len)
+ */
+
+#if (LWIP_CHKSUM_COPY_ALGORITHM == 1) /* Version #1 */
+/** Safe but slow: first call MEMCPY, then call LWIP_CHKSUM.
+ * For architectures with big caches, data might still be in cache when
+ * generating the checksum after copying.
+ */
+u16_t
+lwip_chksum_copy(void *dst, const void *src, u16_t len)
+{
+  MEMCPY(dst, src, len);
+  return LWIP_CHKSUM(dst, len);
+}
+#endif /* (LWIP_CHKSUM_COPY_ALGORITHM == 1) */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/ip.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/ip.c
new file mode 100644
index 0000000..6f24871
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/ip.c
@@ -0,0 +1,857 @@
+/**
+ * @file
+ * This is the IPv4 layer implementation for incoming and outgoing IP traffic.
+ * 
+ * @see ip_frag.c
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+#include "lwip/ip.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/ip_frag.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/netif.h"
+#include "lwip/icmp.h"
+#include "lwip/igmp.h"
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/tcp_impl.h"
+#include "lwip/snmp.h"
+#include "lwip/dhcp.h"
+#include "lwip/autoip.h"
+#include "lwip/stats.h"
+#include "arch/perf.h"
+
+#include 
+
+/** Set this to 0 in the rare case of wanting to call an extra function to
+ * generate the IP checksum (in contrast to calculating it on-the-fly). */
+#ifndef LWIP_INLINE_IP_CHKSUM
+#define LWIP_INLINE_IP_CHKSUM   1
+#endif
+#if LWIP_INLINE_IP_CHKSUM && CHECKSUM_GEN_IP
+#define CHECKSUM_GEN_IP_INLINE  1
+#else
+#define CHECKSUM_GEN_IP_INLINE  0
+#endif
+
+#if LWIP_DHCP || defined(LWIP_IP_ACCEPT_UDP_PORT)
+#define IP_ACCEPT_LINK_LAYER_ADDRESSING 1
+
+/** Some defines for DHCP to let link-layer-addressed packets through while the
+ * netif is down.
+ * To use this in your own application/protocol, define LWIP_IP_ACCEPT_UDP_PORT
+ * to return 1 if the port is accepted and 0 if the port is not accepted.
+ */
+#if LWIP_DHCP && defined(LWIP_IP_ACCEPT_UDP_PORT)
+/* accept DHCP client port and custom port */
+#define IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(port) (((port) == PP_NTOHS(DHCP_CLIENT_PORT)) \
+         || (LWIP_IP_ACCEPT_UDP_PORT(port)))
+#elif defined(LWIP_IP_ACCEPT_UDP_PORT) /* LWIP_DHCP && defined(LWIP_IP_ACCEPT_UDP_PORT) */
+/* accept custom port only */
+#define IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(port) (LWIP_IP_ACCEPT_UDP_PORT(dst_port))
+#else /* LWIP_DHCP && defined(LWIP_IP_ACCEPT_UDP_PORT) */
+/* accept DHCP client port only */
+#define IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(port) ((port) == PP_NTOHS(DHCP_CLIENT_PORT))
+#endif /* LWIP_DHCP && defined(LWIP_IP_ACCEPT_UDP_PORT) */
+
+#else /* LWIP_DHCP */
+#define IP_ACCEPT_LINK_LAYER_ADDRESSING 0
+#endif /* LWIP_DHCP */
+
+/**
+ * The interface that provided the packet for the current callback
+ * invocation.
+ */
+struct netif *current_netif;
+
+/**
+ * Header of the input packet currently being processed.
+ */
+const struct ip_hdr *current_header;
+/** Source IP address of current_header */
+ip_addr_t current_iphdr_src;
+/** Destination IP address of current_header */
+ip_addr_t current_iphdr_dest;
+
+/** The IP header ID of the next outgoing IP packet */
+static u16_t ip_id;
+
+/**
+ * Finds the appropriate network interface for a given IP address. It
+ * searches the list of network interfaces linearly. A match is found
+ * if the masked IP address of the network interface equals the masked
+ * IP address given to the function.
+ *
+ * @param dest the destination IP address for which to find the route
+ * @return the netif on which to send to reach dest
+ */
+struct netif *
+ip_route(ip_addr_t *dest)
+{
+  struct netif *netif;
+
+  /* iterate through netifs */
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+    /* network mask matches? */
+    if (netif_is_up(netif)) {
+      if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) {
+        /* return netif on which to forward IP packet */
+        return netif;
+      }
+    }
+  }
+  if ((netif_default == NULL) || (!netif_is_up(netif_default))) {
+    LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip_route: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+      ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest)));
+    IP_STATS_INC(ip.rterr);
+    snmp_inc_ipoutnoroutes();
+    return NULL;
+  }
+  /* no matching netif found, use default netif */
+  return netif_default;
+}
+
+#if IP_FORWARD
+/**
+ * Forwards an IP packet. It finds an appropriate route for the
+ * packet, decrements the TTL value of the packet, adjusts the
+ * checksum and outputs the packet on the appropriate interface.
+ *
+ * @param p the packet to forward (p->payload points to IP header)
+ * @param iphdr the IP header of the input packet
+ * @param inp the netif on which this packet was received
+ */
+static void
+ip_forward(struct pbuf *p, struct ip_hdr *iphdr, struct netif *inp)
+{
+  struct netif *netif;
+
+  PERF_START;
+
+  /* RFC3927 2.7: do not forward link-local addresses */
+  if (ip_addr_islinklocal(¤t_iphdr_dest)) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_forward: not forwarding LLA %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+      ip4_addr1_16(¤t_iphdr_dest), ip4_addr2_16(¤t_iphdr_dest),
+      ip4_addr3_16(¤t_iphdr_dest), ip4_addr4_16(¤t_iphdr_dest)));
+    goto return_noroute;
+  }
+
+  /* Find network interface where to forward this IP packet to. */
+  netif = ip_route(¤t_iphdr_dest);
+  if (netif == NULL) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_forward: no forwarding route for %"U16_F".%"U16_F".%"U16_F".%"U16_F" found\n",
+      ip4_addr1_16(¤t_iphdr_dest), ip4_addr2_16(¤t_iphdr_dest),
+      ip4_addr3_16(¤t_iphdr_dest), ip4_addr4_16(¤t_iphdr_dest)));
+    goto return_noroute;
+  }
+  /* Do not forward packets onto the same network interface on which
+   * they arrived. */
+  if (netif == inp) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_forward: not bouncing packets back on incoming interface.\n"));
+    goto return_noroute;
+  }
+
+  /* decrement TTL */
+  IPH_TTL_SET(iphdr, IPH_TTL(iphdr) - 1);
+  /* send ICMP if TTL == 0 */
+  if (IPH_TTL(iphdr) == 0) {
+    snmp_inc_ipinhdrerrors();
+#if LWIP_ICMP
+    /* Don't send ICMP messages in response to ICMP messages */
+    if (IPH_PROTO(iphdr) != IP_PROTO_ICMP) {
+      icmp_time_exceeded(p, ICMP_TE_TTL);
+    }
+#endif /* LWIP_ICMP */
+    return;
+  }
+
+  /* Incrementally update the IP checksum. */
+  if (IPH_CHKSUM(iphdr) >= PP_HTONS(0xffffU - 0x100)) {
+    IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + PP_HTONS(0x100) + 1);
+  } else {
+    IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + PP_HTONS(0x100));
+  }
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+    ip4_addr1_16(¤t_iphdr_dest), ip4_addr2_16(¤t_iphdr_dest),
+    ip4_addr3_16(¤t_iphdr_dest), ip4_addr4_16(¤t_iphdr_dest)));
+
+  IP_STATS_INC(ip.fw);
+  IP_STATS_INC(ip.xmit);
+  snmp_inc_ipforwdatagrams();
+
+  PERF_STOP("ip_forward");
+  /* transmit pbuf on chosen interface */
+  netif->output(netif, p, ¤t_iphdr_dest);
+  return;
+return_noroute:
+  snmp_inc_ipoutnoroutes();
+}
+#endif /* IP_FORWARD */
+
+/**
+ * This function is called by the network interface device driver when
+ * an IP packet is received. The function does the basic checks of the
+ * IP header such as packet size being at least larger than the header
+ * size etc. If the packet was not destined for us, the packet is
+ * forwarded (using ip_forward). The IP checksum is always checked.
+ *
+ * Finally, the packet is sent to the upper layer protocol input function.
+ * 
+ * @param p the received IP packet (p->payload points to IP header)
+ * @param inp the netif on which this packet was received
+ * @return ERR_OK if the packet was processed (could return ERR_* if it wasn't
+ *         processed, but currently always returns ERR_OK)
+ */
+err_t
+ip_input(struct pbuf *p, struct netif *inp)
+{
+  struct ip_hdr *iphdr;
+  struct netif *netif;
+  u16_t iphdr_hlen;
+  u16_t iphdr_len;
+#if IP_ACCEPT_LINK_LAYER_ADDRESSING
+  int check_ip_src=1;
+#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */
+
+  IP_STATS_INC(ip.recv);
+  snmp_inc_ipinreceives();
+
+  /* identify the IP header */
+  iphdr = (struct ip_hdr *)p->payload;
+  if (IPH_V(iphdr) != 4) {
+    LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_WARNING, ("IP packet dropped due to bad version number %"U16_F"\n", IPH_V(iphdr)));
+    ip_debug_print(p);
+    pbuf_free(p);
+    IP_STATS_INC(ip.err);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipinhdrerrors();
+    return ERR_OK;
+  }
+
+  /* obtain IP header length in number of 32-bit words */
+  iphdr_hlen = IPH_HL(iphdr);
+  /* calculate IP header length in bytes */
+  iphdr_hlen *= 4;
+  /* obtain ip length in bytes */
+  iphdr_len = ntohs(IPH_LEN(iphdr));
+
+  /* header length exceeds first pbuf length, or ip length exceeds total pbuf length? */
+  if ((iphdr_hlen > p->len) || (iphdr_len > p->tot_len)) {
+    if (iphdr_hlen > p->len) {
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+        ("IP header (len %"U16_F") does not fit in first pbuf (len %"U16_F"), IP packet dropped.\n",
+        iphdr_hlen, p->len));
+    }
+    if (iphdr_len > p->tot_len) {
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+        ("IP (len %"U16_F") is longer than pbuf (len %"U16_F"), IP packet dropped.\n",
+        iphdr_len, p->tot_len));
+    }
+    /* free (drop) packet pbufs */
+    pbuf_free(p);
+    IP_STATS_INC(ip.lenerr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipindiscards();
+    return ERR_OK;
+  }
+
+  /* verify checksum */
+#if CHECKSUM_CHECK_IP
+  if (inet_chksum(iphdr, iphdr_hlen) != 0) {
+
+    LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+      ("Checksum (0x%"X16_F") failed, IP packet dropped.\n", inet_chksum(iphdr, iphdr_hlen)));
+    ip_debug_print(p);
+    pbuf_free(p);
+    IP_STATS_INC(ip.chkerr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipinhdrerrors();
+    return ERR_OK;
+  }
+#endif
+
+  /* Trim pbuf. This should have been done at the netif layer,
+   * but we'll do it anyway just to be sure that its done. */
+  pbuf_realloc(p, iphdr_len);
+
+  /* copy IP addresses to aligned ip_addr_t */
+  ip_addr_copy(current_iphdr_dest, iphdr->dest);
+  ip_addr_copy(current_iphdr_src, iphdr->src);
+
+  /* match packet against an interface, i.e. is this packet for us? */
+#if LWIP_IGMP
+  if (ip_addr_ismulticast(¤t_iphdr_dest)) {
+    if ((inp->flags & NETIF_FLAG_IGMP) && (igmp_lookfor_group(inp, ¤t_iphdr_dest))) {
+      netif = inp;
+    } else {
+      netif = NULL;
+    }
+  } else
+#endif /* LWIP_IGMP */
+  {
+    /* start trying with inp. if that's not acceptable, start walking the
+       list of configured netifs.
+       'first' is used as a boolean to mark whether we started walking the list */
+    int first = 1;
+    netif = inp;
+    do {
+      LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest 0x%"X32_F" netif->ip_addr 0x%"X32_F" (0x%"X32_F", 0x%"X32_F", 0x%"X32_F")\n",
+          ip4_addr_get_u32(&iphdr->dest), ip4_addr_get_u32(&netif->ip_addr),
+          ip4_addr_get_u32(&iphdr->dest) & ip4_addr_get_u32(&netif->netmask),
+          ip4_addr_get_u32(&netif->ip_addr) & ip4_addr_get_u32(&netif->netmask),
+          ip4_addr_get_u32(&iphdr->dest) & ~ip4_addr_get_u32(&netif->netmask)));
+
+      /* interface is up and configured? */
+      if ((netif_is_up(netif)) && (!ip_addr_isany(&(netif->ip_addr)))) {
+        /* unicast to this interface address? */
+        if (ip_addr_cmp(¤t_iphdr_dest, &(netif->ip_addr)) ||
+            /* or broadcast on this interface network address? */
+            ip_addr_isbroadcast(¤t_iphdr_dest, netif)) {
+          LWIP_DEBUGF(IP_DEBUG, ("ip_input: packet accepted on interface %c%c\n",
+              netif->name[0], netif->name[1]));
+          /* break out of for loop */
+          break;
+        }
+#if LWIP_AUTOIP
+        /* connections to link-local addresses must persist after changing
+           the netif's address (RFC3927 ch. 1.9) */
+        if ((netif->autoip != NULL) &&
+            ip_addr_cmp(¤t_iphdr_dest, &(netif->autoip->llipaddr))) {
+          LWIP_DEBUGF(IP_DEBUG, ("ip_input: LLA packet accepted on interface %c%c\n",
+              netif->name[0], netif->name[1]));
+          /* break out of for loop */
+          break;
+        }
+#endif /* LWIP_AUTOIP */
+      }
+      if (first) {
+        first = 0;
+        netif = netif_list;
+      } else {
+        netif = netif->next;
+      }
+      if (netif == inp) {
+        netif = netif->next;
+      }
+    } while(netif != NULL);
+  }
+
+#if IP_ACCEPT_LINK_LAYER_ADDRESSING
+  /* Pass DHCP messages regardless of destination address. DHCP traffic is addressed
+   * using link layer addressing (such as Ethernet MAC) so we must not filter on IP.
+   * According to RFC 1542 section 3.1.1, referred by RFC 2131).
+   *
+   * If you want to accept private broadcast communication while a netif is down,
+   * define LWIP_IP_ACCEPT_UDP_PORT(dst_port), e.g.:
+   *
+   * #define LWIP_IP_ACCEPT_UDP_PORT(dst_port) ((dst_port) == PP_NTOHS(12345))
+   */
+  if (netif == NULL) {
+    /* remote port is DHCP server? */
+    if (IPH_PROTO(iphdr) == IP_PROTO_UDP) {
+      struct udp_hdr *udphdr = (struct udp_hdr *)((u8_t *)iphdr + iphdr_hlen);
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip_input: UDP packet to DHCP client port %"U16_F"\n",
+        ntohs(udphdr->dest)));
+      if (IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(udphdr->dest)) {
+        LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip_input: DHCP packet accepted.\n"));
+        netif = inp;
+        check_ip_src = 0;
+      }
+    }
+  }
+#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */
+
+  /* broadcast or multicast packet source address? Compliant with RFC 1122: 3.2.1.3 */
+#if IP_ACCEPT_LINK_LAYER_ADDRESSING
+  /* DHCP servers need 0.0.0.0 to be allowed as source address (RFC 1.1.2.2: 3.2.1.3/a) */
+  if (check_ip_src && !ip_addr_isany(¤t_iphdr_src))
+#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */
+  {  if ((ip_addr_isbroadcast(¤t_iphdr_src, inp)) ||
+         (ip_addr_ismulticast(¤t_iphdr_src))) {
+      /* packet source is not valid */
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("ip_input: packet source is not valid.\n"));
+      /* free (drop) packet pbufs */
+      pbuf_free(p);
+      IP_STATS_INC(ip.drop);
+      snmp_inc_ipinaddrerrors();
+      snmp_inc_ipindiscards();
+      return ERR_OK;
+    }
+  }
+
+  /* packet not for us? */
+  if (netif == NULL) {
+    /* packet not for us, route or discard */
+    LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip_input: packet not for us.\n"));
+#if IP_FORWARD
+    /* non-broadcast packet? */
+    if (!ip_addr_isbroadcast(¤t_iphdr_dest, inp)) {
+      /* try to forward IP packet on (other) interfaces */
+      ip_forward(p, iphdr, inp);
+    } else
+#endif /* IP_FORWARD */
+    {
+      snmp_inc_ipinaddrerrors();
+      snmp_inc_ipindiscards();
+    }
+    pbuf_free(p);
+    return ERR_OK;
+  }
+  /* packet consists of multiple fragments? */
+  if ((IPH_OFFSET(iphdr) & PP_HTONS(IP_OFFMASK | IP_MF)) != 0) {
+#if IP_REASSEMBLY /* packet fragment reassembly code present? */
+    LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip_reass()\n",
+      ntohs(IPH_ID(iphdr)), p->tot_len, ntohs(IPH_LEN(iphdr)), !!(IPH_OFFSET(iphdr) & PP_HTONS(IP_MF)), (ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)*8));
+    /* reassemble the packet*/
+    p = ip_reass(p);
+    /* packet not fully reassembled yet? */
+    if (p == NULL) {
+      return ERR_OK;
+    }
+    iphdr = (struct ip_hdr *)p->payload;
+#else /* IP_REASSEMBLY == 0, no packet fragment reassembly code present */
+    pbuf_free(p);
+    LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("IP packet dropped since it was fragmented (0x%"X16_F") (while IP_REASSEMBLY == 0).\n",
+      ntohs(IPH_OFFSET(iphdr))));
+    IP_STATS_INC(ip.opterr);
+    IP_STATS_INC(ip.drop);
+    /* unsupported protocol feature */
+    snmp_inc_ipinunknownprotos();
+    return ERR_OK;
+#endif /* IP_REASSEMBLY */
+  }
+
+#if IP_OPTIONS_ALLOWED == 0 /* no support for IP options in the IP header? */
+
+#if LWIP_IGMP
+  /* there is an extra "router alert" option in IGMP messages which we allow for but do not police */
+  if((iphdr_hlen > IP_HLEN) &&  (IPH_PROTO(iphdr) != IP_PROTO_IGMP)) {
+#else
+  if (iphdr_hlen > IP_HLEN) {
+#endif /* LWIP_IGMP */
+    LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("IP packet dropped since there were IP options (while IP_OPTIONS_ALLOWED == 0).\n"));
+    pbuf_free(p);
+    IP_STATS_INC(ip.opterr);
+    IP_STATS_INC(ip.drop);
+    /* unsupported protocol feature */
+    snmp_inc_ipinunknownprotos();
+    return ERR_OK;
+  }
+#endif /* IP_OPTIONS_ALLOWED == 0 */
+
+  /* send to upper layers */
+  LWIP_DEBUGF(IP_DEBUG, ("ip_input: \n"));
+  ip_debug_print(p);
+  LWIP_DEBUGF(IP_DEBUG, ("ip_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len));
+
+  current_netif = inp;
+  current_header = iphdr;
+
+#if LWIP_RAW
+  /* raw input did not eat the packet? */
+  if (raw_input(p, inp) == 0)
+#endif /* LWIP_RAW */
+  {
+
+    switch (IPH_PROTO(iphdr)) {
+#if LWIP_UDP
+    case IP_PROTO_UDP:
+#if LWIP_UDPLITE
+    case IP_PROTO_UDPLITE:
+#endif /* LWIP_UDPLITE */
+      snmp_inc_ipindelivers();
+      udp_input(p, inp);
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+    case IP_PROTO_TCP:
+      snmp_inc_ipindelivers();
+      tcp_input(p, inp);
+      break;
+#endif /* LWIP_TCP */
+#if LWIP_ICMP
+    case IP_PROTO_ICMP:
+      snmp_inc_ipindelivers();
+      icmp_input(p, inp);
+      break;
+#endif /* LWIP_ICMP */
+#if LWIP_IGMP
+    case IP_PROTO_IGMP:
+      igmp_input(p, inp, ¤t_iphdr_dest);
+      break;
+#endif /* LWIP_IGMP */
+    default:
+#if LWIP_ICMP
+      /* send ICMP destination protocol unreachable unless is was a broadcast */
+      if (!ip_addr_isbroadcast(¤t_iphdr_dest, inp) &&
+          !ip_addr_ismulticast(¤t_iphdr_dest)) {
+        p->payload = iphdr;
+        icmp_dest_unreach(p, ICMP_DUR_PROTO);
+      }
+#endif /* LWIP_ICMP */
+      pbuf_free(p);
+
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("Unsupported transport protocol %"U16_F"\n", IPH_PROTO(iphdr)));
+
+      IP_STATS_INC(ip.proterr);
+      IP_STATS_INC(ip.drop);
+      snmp_inc_ipinunknownprotos();
+    }
+  }
+
+  current_netif = NULL;
+  current_header = NULL;
+  ip_addr_set_any(¤t_iphdr_src);
+  ip_addr_set_any(¤t_iphdr_dest);
+
+  return ERR_OK;
+}
+
+/**
+ * Sends an IP packet on a network interface. This function constructs
+ * the IP header and calculates the IP header checksum. If the source
+ * IP address is NULL, the IP address of the outgoing network
+ * interface is filled in as source address.
+ * If the destination IP address is IP_HDRINCL, p is assumed to already
+ * include an IP header and p->payload points to it instead of the data.
+ *
+ * @param p the packet to send (p->payload points to the data, e.g. next
+            protocol header; if dest == IP_HDRINCL, p already includes an IP
+            header and p->payload points to that IP header)
+ * @param src the source IP address to send from (if src == IP_ADDR_ANY, the
+ *         IP  address of the netif used to send is used as source address)
+ * @param dest the destination IP address to send the packet to
+ * @param ttl the TTL value to be set in the IP header
+ * @param tos the TOS value to be set in the IP header
+ * @param proto the PROTOCOL to be set in the IP header
+ * @param netif the netif on which to send this packet
+ * @return ERR_OK if the packet was sent OK
+ *         ERR_BUF if p doesn't have enough space for IP/LINK headers
+ *         returns errors returned by netif->output
+ *
+ * @note ip_id: RFC791 "some host may be able to simply use
+ *  unique identifiers independent of destination"
+ */
+err_t
+ip_output_if(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest,
+             u8_t ttl, u8_t tos,
+             u8_t proto, struct netif *netif)
+{
+#if IP_OPTIONS_SEND
+  return ip_output_if_opt(p, src, dest, ttl, tos, proto, netif, NULL, 0);
+}
+
+/**
+ * Same as ip_output_if() but with the possibility to include IP options:
+ *
+ * @ param ip_options pointer to the IP options, copied into the IP header
+ * @ param optlen length of ip_options
+ */
+err_t ip_output_if_opt(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest,
+       u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options,
+       u16_t optlen)
+{
+#endif /* IP_OPTIONS_SEND */
+  struct ip_hdr *iphdr;
+  ip_addr_t dest_addr;
+#if CHECKSUM_GEN_IP_INLINE
+  u32_t chk_sum = 0;
+#endif /* CHECKSUM_GEN_IP_INLINE */
+
+  /* pbufs passed to IP must have a ref-count of 1 as their payload pointer
+     gets altered as the packet is passed down the stack */
+  LWIP_ASSERT("p->ref == 1", p->ref == 1);
+
+  snmp_inc_ipoutrequests();
+
+  /* Should the IP header be generated or is it already included in p? */
+  if (dest != IP_HDRINCL) {
+    u16_t ip_hlen = IP_HLEN;
+#if IP_OPTIONS_SEND
+    u16_t optlen_aligned = 0;
+    if (optlen != 0) {
+#if CHECKSUM_GEN_IP_INLINE
+      int i;
+#endif /* CHECKSUM_GEN_IP_INLINE */
+      /* round up to a multiple of 4 */
+      optlen_aligned = ((optlen + 3) & ~3);
+      ip_hlen += optlen_aligned;
+      /* First write in the IP options */
+      if (pbuf_header(p, optlen_aligned)) {
+        LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip_output_if_opt: not enough room for IP options in pbuf\n"));
+        IP_STATS_INC(ip.err);
+        snmp_inc_ipoutdiscards();
+        return ERR_BUF;
+      }
+      MEMCPY(p->payload, ip_options, optlen);
+      if (optlen < optlen_aligned) {
+        /* zero the remaining bytes */
+        memset(((char*)p->payload) + optlen, 0, optlen_aligned - optlen);
+      }
+#if CHECKSUM_GEN_IP_INLINE
+      for (i = 0; i < optlen_aligned/2; i++) {
+        chk_sum += ((u16_t*)p->payload)[i];
+      }
+#endif /* CHECKSUM_GEN_IP_INLINE */
+    }
+#endif /* IP_OPTIONS_SEND */
+    /* generate IP header */
+    if (pbuf_header(p, IP_HLEN)) {
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip_output: not enough room for IP header in pbuf\n"));
+
+      IP_STATS_INC(ip.err);
+      snmp_inc_ipoutdiscards();
+      return ERR_BUF;
+    }
+
+    iphdr = (struct ip_hdr *)p->payload;
+    LWIP_ASSERT("check that first pbuf can hold struct ip_hdr",
+               (p->len >= sizeof(struct ip_hdr)));
+
+    IPH_TTL_SET(iphdr, ttl);
+    IPH_PROTO_SET(iphdr, proto);
+#if CHECKSUM_GEN_IP_INLINE
+    chk_sum += LWIP_MAKE_U16(proto, ttl);
+#endif /* CHECKSUM_GEN_IP_INLINE */
+
+    /* dest cannot be NULL here */
+    ip_addr_copy(iphdr->dest, *dest);
+#if CHECKSUM_GEN_IP_INLINE
+    chk_sum += ip4_addr_get_u32(&iphdr->dest) & 0xFFFF;
+    chk_sum += ip4_addr_get_u32(&iphdr->dest) >> 16;
+#endif /* CHECKSUM_GEN_IP_INLINE */
+
+    IPH_VHLTOS_SET(iphdr, 4, ip_hlen / 4, tos);
+#if CHECKSUM_GEN_IP_INLINE
+    chk_sum += iphdr->_v_hl_tos;
+#endif /* CHECKSUM_GEN_IP_INLINE */
+    IPH_LEN_SET(iphdr, htons(p->tot_len));
+#if CHECKSUM_GEN_IP_INLINE
+    chk_sum += iphdr->_len;
+#endif /* CHECKSUM_GEN_IP_INLINE */
+    IPH_OFFSET_SET(iphdr, 0);
+    IPH_ID_SET(iphdr, htons(ip_id));
+#if CHECKSUM_GEN_IP_INLINE
+    chk_sum += iphdr->_id;
+#endif /* CHECKSUM_GEN_IP_INLINE */
+    ++ip_id;
+
+    if (ip_addr_isany(src)) {
+      ip_addr_copy(iphdr->src, netif->ip_addr);
+    } else {
+      /* src cannot be NULL here */
+      ip_addr_copy(iphdr->src, *src);
+    }
+
+#if CHECKSUM_GEN_IP_INLINE
+    chk_sum += ip4_addr_get_u32(&iphdr->src) & 0xFFFF;
+    chk_sum += ip4_addr_get_u32(&iphdr->src) >> 16;
+    chk_sum = (chk_sum >> 16) + (chk_sum & 0xFFFF);
+    chk_sum = (chk_sum >> 16) + chk_sum;
+    chk_sum = ~chk_sum;
+    iphdr->_chksum = chk_sum; /* network order */
+#else /* CHECKSUM_GEN_IP_INLINE */
+    IPH_CHKSUM_SET(iphdr, 0);
+#if CHECKSUM_GEN_IP
+    IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, ip_hlen));
+#endif
+#endif /* CHECKSUM_GEN_IP_INLINE */
+  } else {
+    /* IP header already included in p */
+    iphdr = (struct ip_hdr *)p->payload;
+    ip_addr_copy(dest_addr, iphdr->dest);
+    dest = &dest_addr;
+  }
+
+  IP_STATS_INC(ip.xmit);
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c%"U16_F"\n", netif->name[0], netif->name[1], netif->num));
+  ip_debug_print(p);
+
+#if ENABLE_LOOPBACK
+  if (ip_addr_cmp(dest, &netif->ip_addr)) {
+    /* Packet to self, enqueue it for loopback */
+    LWIP_DEBUGF(IP_DEBUG, ("netif_loop_output()"));
+    return netif_loop_output(netif, p, dest);
+  }
+#if LWIP_IGMP
+  if ((p->flags & PBUF_FLAG_MCASTLOOP) != 0) {
+    netif_loop_output(netif, p, dest);
+  }
+#endif /* LWIP_IGMP */
+#endif /* ENABLE_LOOPBACK */
+#if IP_FRAG
+  /* don't fragment if interface has mtu set to 0 [loopif] */
+  if (netif->mtu && (p->tot_len > netif->mtu)) {
+    return ip_frag(p, netif, dest);
+  }
+#endif /* IP_FRAG */
+
+  LWIP_DEBUGF(IP_DEBUG, ("netif->output()"));
+  return netif->output(netif, p, dest);
+}
+
+/**
+ * Simple interface to ip_output_if. It finds the outgoing network
+ * interface and calls upon ip_output_if to do the actual work.
+ *
+ * @param p the packet to send (p->payload points to the data, e.g. next
+            protocol header; if dest == IP_HDRINCL, p already includes an IP
+            header and p->payload points to that IP header)
+ * @param src the source IP address to send from (if src == IP_ADDR_ANY, the
+ *         IP  address of the netif used to send is used as source address)
+ * @param dest the destination IP address to send the packet to
+ * @param ttl the TTL value to be set in the IP header
+ * @param tos the TOS value to be set in the IP header
+ * @param proto the PROTOCOL to be set in the IP header
+ *
+ * @return ERR_RTE if no route is found
+ *         see ip_output_if() for more return values
+ */
+err_t
+ip_output(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest,
+          u8_t ttl, u8_t tos, u8_t proto)
+{
+  struct netif *netif;
+
+  /* pbufs passed to IP must have a ref-count of 1 as their payload pointer
+     gets altered as the packet is passed down the stack */
+  LWIP_ASSERT("p->ref == 1", p->ref == 1);
+
+  if ((netif = ip_route(dest)) == NULL) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+      ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest)));
+    IP_STATS_INC(ip.rterr);
+    return ERR_RTE;
+  }
+
+  return ip_output_if(p, src, dest, ttl, tos, proto, netif);
+}
+
+#if LWIP_NETIF_HWADDRHINT
+/** Like ip_output, but takes and addr_hint pointer that is passed on to netif->addr_hint
+ *  before calling ip_output_if.
+ *
+ * @param p the packet to send (p->payload points to the data, e.g. next
+            protocol header; if dest == IP_HDRINCL, p already includes an IP
+            header and p->payload points to that IP header)
+ * @param src the source IP address to send from (if src == IP_ADDR_ANY, the
+ *         IP  address of the netif used to send is used as source address)
+ * @param dest the destination IP address to send the packet to
+ * @param ttl the TTL value to be set in the IP header
+ * @param tos the TOS value to be set in the IP header
+ * @param proto the PROTOCOL to be set in the IP header
+ * @param addr_hint address hint pointer set to netif->addr_hint before
+ *        calling ip_output_if()
+ *
+ * @return ERR_RTE if no route is found
+ *         see ip_output_if() for more return values
+ */
+err_t
+ip_output_hinted(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest,
+          u8_t ttl, u8_t tos, u8_t proto, u8_t *addr_hint)
+{
+  struct netif *netif;
+  err_t err;
+
+  /* pbufs passed to IP must have a ref-count of 1 as their payload pointer
+     gets altered as the packet is passed down the stack */
+  LWIP_ASSERT("p->ref == 1", p->ref == 1);
+
+  if ((netif = ip_route(dest)) == NULL) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+      ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest)));
+    IP_STATS_INC(ip.rterr);
+    return ERR_RTE;
+  }
+
+  netif->addr_hint = addr_hint;
+  err = ip_output_if(p, src, dest, ttl, tos, proto, netif);
+  netif->addr_hint = NULL;
+
+  return err;
+}
+#endif /* LWIP_NETIF_HWADDRHINT*/
+
+#if IP_DEBUG
+/* Print an IP header by using LWIP_DEBUGF
+ * @param p an IP packet, p->payload pointing to the IP header
+ */
+void
+ip_debug_print(struct pbuf *p)
+{
+  struct ip_hdr *iphdr = (struct ip_hdr *)p->payload;
+  u8_t *payload;
+
+  payload = (u8_t *)iphdr + IP_HLEN;
+
+  LWIP_DEBUGF(IP_DEBUG, ("IP header:\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" |%2"S16_F" |  0x%02"X16_F" |     %5"U16_F"     | (v, hl, tos, len)\n",
+                    IPH_V(iphdr),
+                    IPH_HL(iphdr),
+                    IPH_TOS(iphdr),
+                    ntohs(IPH_LEN(iphdr))));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|    %5"U16_F"      |%"U16_F"%"U16_F"%"U16_F"|    %4"U16_F"   | (id, flags, offset)\n",
+                    ntohs(IPH_ID(iphdr)),
+                    ntohs(IPH_OFFSET(iphdr)) >> 15 & 1,
+                    ntohs(IPH_OFFSET(iphdr)) >> 14 & 1,
+                    ntohs(IPH_OFFSET(iphdr)) >> 13 & 1,
+                    ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3"U16_F"  |  %3"U16_F"  |    0x%04"X16_F"     | (ttl, proto, chksum)\n",
+                    IPH_TTL(iphdr),
+                    IPH_PROTO(iphdr),
+                    ntohs(IPH_CHKSUM(iphdr))));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  | (src)\n",
+                    ip4_addr1_16(&iphdr->src),
+                    ip4_addr2_16(&iphdr->src),
+                    ip4_addr3_16(&iphdr->src),
+                    ip4_addr4_16(&iphdr->src)));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  | (dest)\n",
+                    ip4_addr1_16(&iphdr->dest),
+                    ip4_addr2_16(&iphdr->dest),
+                    ip4_addr3_16(&iphdr->dest),
+                    ip4_addr4_16(&iphdr->dest)));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+}
+#endif /* IP_DEBUG */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/ip_addr.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/ip_addr.c
new file mode 100644
index 0000000..8f633ff
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/ip_addr.c
@@ -0,0 +1,312 @@
+/**
+ * @file
+ * This is the IPv4 address tools implementation.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+
+/* used by IP_ADDR_ANY and IP_ADDR_BROADCAST in ip_addr.h */
+const ip_addr_t ip_addr_any = { IPADDR_ANY };
+const ip_addr_t ip_addr_broadcast = { IPADDR_BROADCAST };
+
+/**
+ * Determine if an address is a broadcast address on a network interface 
+ * 
+ * @param addr address to be checked
+ * @param netif the network interface against which the address is checked
+ * @return returns non-zero if the address is a broadcast address
+ */
+u8_t
+ip4_addr_isbroadcast(u32_t addr, const struct netif *netif)
+{
+  ip_addr_t ipaddr;
+  ip4_addr_set_u32(&ipaddr, addr);
+
+  /* all ones (broadcast) or all zeroes (old skool broadcast) */
+  if ((~addr == IPADDR_ANY) ||
+      (addr == IPADDR_ANY)) {
+    return 1;
+  /* no broadcast support on this network interface? */
+  } else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0) {
+    /* the given address cannot be a broadcast address
+     * nor can we check against any broadcast addresses */
+    return 0;
+  /* address matches network interface address exactly? => no broadcast */
+  } else if (addr == ip4_addr_get_u32(&netif->ip_addr)) {
+    return 0;
+  /*  on the same (sub) network... */
+  } else if (ip_addr_netcmp(&ipaddr, &(netif->ip_addr), &(netif->netmask))
+         /* ...and host identifier bits are all ones? =>... */
+          && ((addr & ~ip4_addr_get_u32(&netif->netmask)) ==
+           (IPADDR_BROADCAST & ~ip4_addr_get_u32(&netif->netmask)))) {
+    /* => network broadcast address */
+    return 1;
+  } else {
+    return 0;
+  }
+}
+
+/** Checks if a netmask is valid (starting with ones, then only zeros)
+ *
+ * @param netmask the IPv4 netmask to check (in network byte order!)
+ * @return 1 if the netmask is valid, 0 if it is not
+ */
+u8_t
+ip4_addr_netmask_valid(u32_t netmask)
+{
+  u32_t mask;
+  u32_t nm_hostorder = lwip_htonl(netmask);
+
+  /* first, check for the first zero */
+  for (mask = 1UL << 31 ; mask != 0; mask >>= 1) {
+    if ((nm_hostorder & mask) == 0) {
+      break;
+    }
+  }
+  /* then check that there is no one */
+  for (; mask != 0; mask >>= 1) {
+    if ((nm_hostorder & mask) != 0) {
+      /* there is a one after the first zero -> invalid */
+      return 0;
+    }
+  }
+  /* no one after the first zero -> valid */
+  return 1;
+}
+
+/* Here for now until needed in other places in lwIP */
+#ifndef isprint
+#define in_range(c, lo, up)  ((u8_t)c >= lo && (u8_t)c <= up)
+#define isprint(c)           in_range(c, 0x20, 0x7f)
+#define isdigit(c)           in_range(c, '0', '9')
+#define isxdigit(c)          (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F'))
+#define islower(c)           in_range(c, 'a', 'z')
+#define isspace(c)           (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v')
+#endif
+
+/**
+ * Ascii internet address interpretation routine.
+ * The value returned is in network order.
+ *
+ * @param cp IP address in ascii represenation (e.g. "127.0.0.1")
+ * @return ip address in network order
+ */
+u32_t
+ipaddr_addr(const char *cp)
+{
+  ip_addr_t val;
+
+  if (ipaddr_aton(cp, &val)) {
+    return ip4_addr_get_u32(&val);
+  }
+  return (IPADDR_NONE);
+}
+
+/**
+ * Check whether "cp" is a valid ascii representation
+ * of an Internet address and convert to a binary address.
+ * Returns 1 if the address is valid, 0 if not.
+ * This replaces inet_addr, the return value from which
+ * cannot distinguish between failure and a local broadcast address.
+ *
+ * @param cp IP address in ascii represenation (e.g. "127.0.0.1")
+ * @param addr pointer to which to save the ip address in network order
+ * @return 1 if cp could be converted to addr, 0 on failure
+ */
+int
+ipaddr_aton(const char *cp, ip_addr_t *addr)
+{
+  u32_t val;
+  u8_t base;
+  char c;
+  u32_t parts[4];
+  u32_t *pp = parts;
+
+  c = *cp;
+  for (;;) {
+    /*
+     * Collect number up to ``.''.
+     * Values are specified as for C:
+     * 0x=hex, 0=octal, 1-9=decimal.
+     */
+    if (!isdigit(c))
+      return (0);
+    val = 0;
+    base = 10;
+    if (c == '0') {
+      c = *++cp;
+      if (c == 'x' || c == 'X') {
+        base = 16;
+        c = *++cp;
+      } else
+        base = 8;
+    }
+    for (;;) {
+      if (isdigit(c)) {
+        val = (val * base) + (int)(c - '0');
+        c = *++cp;
+      } else if (base == 16 && isxdigit(c)) {
+        val = (val << 4) | (int)(c + 10 - (islower(c) ? 'a' : 'A'));
+        c = *++cp;
+      } else
+        break;
+    }
+    if (c == '.') {
+      /*
+       * Internet format:
+       *  a.b.c.d
+       *  a.b.c   (with c treated as 16 bits)
+       *  a.b (with b treated as 24 bits)
+       */
+      if (pp >= parts + 3) {
+        return (0);
+      }
+      *pp++ = val;
+      c = *++cp;
+    } else
+      break;
+  }
+  /*
+   * Check for trailing characters.
+   */
+  if (c != '\0' && !isspace(c)) {
+    return (0);
+  }
+  /*
+   * Concoct the address according to
+   * the number of parts specified.
+   */
+  switch (pp - parts + 1) {
+
+  case 0:
+    return (0);       /* initial nondigit */
+
+  case 1:             /* a -- 32 bits */
+    break;
+
+  case 2:             /* a.b -- 8.24 bits */
+    if (val > 0xffffffUL) {
+      return (0);
+    }
+    val |= parts[0] << 24;
+    break;
+
+  case 3:             /* a.b.c -- 8.8.16 bits */
+    if (val > 0xffff) {
+      return (0);
+    }
+    val |= (parts[0] << 24) | (parts[1] << 16);
+    break;
+
+  case 4:             /* a.b.c.d -- 8.8.8.8 bits */
+    if (val > 0xff) {
+      return (0);
+    }
+    val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8);
+    break;
+  default:
+    LWIP_ASSERT("unhandled", 0);
+    break;
+  }
+  if (addr) {
+    ip4_addr_set_u32(addr, htonl(val));
+  }
+  return (1);
+}
+
+/**
+ * Convert numeric IP address into decimal dotted ASCII representation.
+ * returns ptr to static buffer; not reentrant!
+ *
+ * @param addr ip address in network order to convert
+ * @return pointer to a global static (!) buffer that holds the ASCII
+ *         represenation of addr
+ */
+char *
+ipaddr_ntoa(const ip_addr_t *addr)
+{
+  static char str[16];
+  return ipaddr_ntoa_r(addr, str, 16);
+}
+
+/**
+ * Same as ipaddr_ntoa, but reentrant since a user-supplied buffer is used.
+ *
+ * @param addr ip address in network order to convert
+ * @param buf target buffer where the string is stored
+ * @param buflen length of buf
+ * @return either pointer to buf which now holds the ASCII
+ *         representation of addr or NULL if buf was too small
+ */
+char *ipaddr_ntoa_r(const ip_addr_t *addr, char *buf, int buflen)
+{
+  u32_t s_addr;
+  char inv[3];
+  char *rp;
+  u8_t *ap;
+  u8_t rem;
+  u8_t n;
+  u8_t i;
+  int len = 0;
+
+  s_addr = ip4_addr_get_u32(addr);
+
+  rp = buf;
+  ap = (u8_t *)&s_addr;
+  for(n = 0; n < 4; n++) {
+    i = 0;
+    do {
+      rem = *ap % (u8_t)10;
+      *ap /= (u8_t)10;
+      inv[i++] = '0' + rem;
+    } while(*ap);
+    while(i--) {
+      if (len++ >= buflen) {
+        return NULL;
+      }
+      *rp++ = inv[i];
+    }
+    if (len++ >= buflen) {
+      return NULL;
+    }
+    *rp++ = '.';
+    ap++;
+  }
+  *--rp = 0;
+  return buf;
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/ip_frag.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/ip_frag.c
new file mode 100644
index 0000000..8d18434
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv4/ip_frag.c
@@ -0,0 +1,863 @@
+/**
+ * @file
+ * This is the IPv4 packet segmentation and reassembly implementation.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Jani Monoses  
+ *         Simon Goldschmidt
+ * original reassembly code by Adam Dunkels 
+ * 
+ */
+
+#include "lwip/opt.h"
+#include "lwip/ip_frag.h"
+#include "lwip/def.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/netif.h"
+#include "lwip/snmp.h"
+#include "lwip/stats.h"
+#include "lwip/icmp.h"
+
+#include 
+
+#if IP_REASSEMBLY
+/**
+ * The IP reassembly code currently has the following limitations:
+ * - IP header options are not supported
+ * - fragments must not overlap (e.g. due to different routes),
+ *   currently, overlapping or duplicate fragments are thrown away
+ *   if IP_REASS_CHECK_OVERLAP=1 (the default)!
+ *
+ * @todo: work with IP header options
+ */
+
+/** Setting this to 0, you can turn off checking the fragments for overlapping
+ * regions. The code gets a little smaller. Only use this if you know that
+ * overlapping won't occur on your network! */
+#ifndef IP_REASS_CHECK_OVERLAP
+#define IP_REASS_CHECK_OVERLAP 1
+#endif /* IP_REASS_CHECK_OVERLAP */
+
+/** Set to 0 to prevent freeing the oldest datagram when the reassembly buffer is
+ * full (IP_REASS_MAX_PBUFS pbufs are enqueued). The code gets a little smaller.
+ * Datagrams will be freed by timeout only. Especially useful when MEMP_NUM_REASSDATA
+ * is set to 1, so one datagram can be reassembled at a time, only. */
+#ifndef IP_REASS_FREE_OLDEST
+#define IP_REASS_FREE_OLDEST 1
+#endif /* IP_REASS_FREE_OLDEST */
+
+#define IP_REASS_FLAG_LASTFRAG 0x01
+
+/** This is a helper struct which holds the starting
+ * offset and the ending offset of this fragment to
+ * easily chain the fragments.
+ * It has the same packing requirements as the IP header, since it replaces
+ * the IP header in memory in incoming fragments (after copying it) to keep
+ * track of the various fragments. (-> If the IP header doesn't need packing,
+ * this struct doesn't need packing, too.)
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_reass_helper {
+  PACK_STRUCT_FIELD(struct pbuf *next_pbuf);
+  PACK_STRUCT_FIELD(u16_t start);
+  PACK_STRUCT_FIELD(u16_t end);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define IP_ADDRESSES_AND_ID_MATCH(iphdrA, iphdrB)  \
+  (ip_addr_cmp(&(iphdrA)->src, &(iphdrB)->src) && \
+   ip_addr_cmp(&(iphdrA)->dest, &(iphdrB)->dest) && \
+   IPH_ID(iphdrA) == IPH_ID(iphdrB)) ? 1 : 0
+
+/* global variables */
+static struct ip_reassdata *reassdatagrams;
+static u16_t ip_reass_pbufcount;
+
+/* function prototypes */
+static void ip_reass_dequeue_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev);
+static int ip_reass_free_complete_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev);
+
+/**
+ * Reassembly timer base function
+ * for both NO_SYS == 0 and 1 (!).
+ *
+ * Should be called every 1000 msec (defined by IP_TMR_INTERVAL).
+ */
+void
+ip_reass_tmr(void)
+{
+  struct ip_reassdata *r, *prev = NULL;
+
+  r = reassdatagrams;
+  while (r != NULL) {
+    /* Decrement the timer. Once it reaches 0,
+     * clean up the incomplete fragment assembly */
+    if (r->timer > 0) {
+      r->timer--;
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer dec %"U16_F"\n",(u16_t)r->timer));
+      prev = r;
+      r = r->next;
+    } else {
+      /* reassembly timed out */
+      struct ip_reassdata *tmp;
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer timed out\n"));
+      tmp = r;
+      /* get the next pointer before freeing */
+      r = r->next;
+      /* free the helper struct and all enqueued pbufs */
+      ip_reass_free_complete_datagram(tmp, prev);
+     }
+   }
+}
+
+/**
+ * Free a datagram (struct ip_reassdata) and all its pbufs.
+ * Updates the total count of enqueued pbufs (ip_reass_pbufcount),
+ * SNMP counters and sends an ICMP time exceeded packet.
+ *
+ * @param ipr datagram to free
+ * @param prev the previous datagram in the linked list
+ * @return the number of pbufs freed
+ */
+static int
+ip_reass_free_complete_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev)
+{
+  u16_t pbufs_freed = 0;
+  u8_t clen;
+  struct pbuf *p;
+  struct ip_reass_helper *iprh;
+
+  LWIP_ASSERT("prev != ipr", prev != ipr);
+  if (prev != NULL) {
+    LWIP_ASSERT("prev->next == ipr", prev->next == ipr);
+  }
+
+  snmp_inc_ipreasmfails();
+#if LWIP_ICMP
+  iprh = (struct ip_reass_helper *)ipr->p->payload;
+  if (iprh->start == 0) {
+    /* The first fragment was received, send ICMP time exceeded. */
+    /* First, de-queue the first pbuf from r->p. */
+    p = ipr->p;
+    ipr->p = iprh->next_pbuf;
+    /* Then, copy the original header into it. */
+    SMEMCPY(p->payload, &ipr->iphdr, IP_HLEN);
+    icmp_time_exceeded(p, ICMP_TE_FRAG);
+    clen = pbuf_clen(p);
+    LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff);
+    pbufs_freed += clen;
+    pbuf_free(p);
+  }
+#endif /* LWIP_ICMP */
+
+  /* First, free all received pbufs.  The individual pbufs need to be released 
+     separately as they have not yet been chained */
+  p = ipr->p;
+  while (p != NULL) {
+    struct pbuf *pcur;
+    iprh = (struct ip_reass_helper *)p->payload;
+    pcur = p;
+    /* get the next pointer before freeing */
+    p = iprh->next_pbuf;
+    clen = pbuf_clen(pcur);
+    LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff);
+    pbufs_freed += clen;
+    pbuf_free(pcur);
+  }
+  /* Then, unchain the struct ip_reassdata from the list and free it. */
+  ip_reass_dequeue_datagram(ipr, prev);
+  LWIP_ASSERT("ip_reass_pbufcount >= clen", ip_reass_pbufcount >= pbufs_freed);
+  ip_reass_pbufcount -= pbufs_freed;
+
+  return pbufs_freed;
+}
+
+#if IP_REASS_FREE_OLDEST
+/**
+ * Free the oldest datagram to make room for enqueueing new fragments.
+ * The datagram 'fraghdr' belongs to is not freed!
+ *
+ * @param fraghdr IP header of the current fragment
+ * @param pbufs_needed number of pbufs needed to enqueue
+ *        (used for freeing other datagrams if not enough space)
+ * @return the number of pbufs freed
+ */
+static int
+ip_reass_remove_oldest_datagram(struct ip_hdr *fraghdr, int pbufs_needed)
+{
+  /* @todo Can't we simply remove the last datagram in the
+   *       linked list behind reassdatagrams?
+   */
+  struct ip_reassdata *r, *oldest, *prev;
+  int pbufs_freed = 0, pbufs_freed_current;
+  int other_datagrams;
+
+  /* Free datagrams until being allowed to enqueue 'pbufs_needed' pbufs,
+   * but don't free the datagram that 'fraghdr' belongs to! */
+  do {
+    oldest = NULL;
+    prev = NULL;
+    other_datagrams = 0;
+    r = reassdatagrams;
+    while (r != NULL) {
+      if (!IP_ADDRESSES_AND_ID_MATCH(&r->iphdr, fraghdr)) {
+        /* Not the same datagram as fraghdr */
+        other_datagrams++;
+        if (oldest == NULL) {
+          oldest = r;
+        } else if (r->timer <= oldest->timer) {
+          /* older than the previous oldest */
+          oldest = r;
+        }
+      }
+      if (r->next != NULL) {
+        prev = r;
+      }
+      r = r->next;
+    }
+    if (oldest != NULL) {
+      pbufs_freed_current = ip_reass_free_complete_datagram(oldest, prev);
+      pbufs_freed += pbufs_freed_current;
+    }
+  } while ((pbufs_freed < pbufs_needed) && (other_datagrams > 1));
+  return pbufs_freed;
+}
+#endif /* IP_REASS_FREE_OLDEST */
+
+/**
+ * Enqueues a new fragment into the fragment queue
+ * @param fraghdr points to the new fragments IP hdr
+ * @param clen number of pbufs needed to enqueue (used for freeing other datagrams if not enough space)
+ * @return A pointer to the queue location into which the fragment was enqueued
+ */
+static struct ip_reassdata*
+ip_reass_enqueue_new_datagram(struct ip_hdr *fraghdr, int clen)
+{
+  struct ip_reassdata* ipr;
+  /* No matching previous fragment found, allocate a new reassdata struct */
+  ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA);
+  if (ipr == NULL) {
+#if IP_REASS_FREE_OLDEST
+    if (ip_reass_remove_oldest_datagram(fraghdr, clen) >= clen) {
+      ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA);
+    }
+    if (ipr == NULL)
+#endif /* IP_REASS_FREE_OLDEST */
+    {
+      IPFRAG_STATS_INC(ip_frag.memerr);
+      LWIP_DEBUGF(IP_REASS_DEBUG,("Failed to alloc reassdata struct\n"));
+      return NULL;
+    }
+  }
+  memset(ipr, 0, sizeof(struct ip_reassdata));
+  ipr->timer = IP_REASS_MAXAGE;
+
+  /* enqueue the new structure to the front of the list */
+  ipr->next = reassdatagrams;
+  reassdatagrams = ipr;
+  /* copy the ip header for later tests and input */
+  /* @todo: no ip options supported? */
+  SMEMCPY(&(ipr->iphdr), fraghdr, IP_HLEN);
+  return ipr;
+}
+
+/**
+ * Dequeues a datagram from the datagram queue. Doesn't deallocate the pbufs.
+ * @param ipr points to the queue entry to dequeue
+ */
+static void
+ip_reass_dequeue_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev)
+{
+  
+  /* dequeue the reass struct  */
+  if (reassdatagrams == ipr) {
+    /* it was the first in the list */
+    reassdatagrams = ipr->next;
+  } else {
+    /* it wasn't the first, so it must have a valid 'prev' */
+    LWIP_ASSERT("sanity check linked list", prev != NULL);
+    prev->next = ipr->next;
+  }
+
+  /* now we can free the ip_reass struct */
+  memp_free(MEMP_REASSDATA, ipr);
+}
+
+/**
+ * Chain a new pbuf into the pbuf list that composes the datagram.  The pbuf list
+ * will grow over time as  new pbufs are rx.
+ * Also checks that the datagram passes basic continuity checks (if the last
+ * fragment was received at least once).
+ * @param root_p points to the 'root' pbuf for the current datagram being assembled.
+ * @param new_p points to the pbuf for the current fragment
+ * @return 0 if invalid, >0 otherwise
+ */
+static int
+ip_reass_chain_frag_into_datagram_and_validate(struct ip_reassdata *ipr, struct pbuf *new_p)
+{
+  struct ip_reass_helper *iprh, *iprh_tmp, *iprh_prev=NULL;
+  struct pbuf *q;
+  u16_t offset,len;
+  struct ip_hdr *fraghdr;
+  int valid = 1;
+
+  /* Extract length and fragment offset from current fragment */
+  fraghdr = (struct ip_hdr*)new_p->payload; 
+  len = ntohs(IPH_LEN(fraghdr)) - IPH_HL(fraghdr) * 4;
+  offset = (ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) * 8;
+
+  /* overwrite the fragment's ip header from the pbuf with our helper struct,
+   * and setup the embedded helper structure. */
+  /* make sure the struct ip_reass_helper fits into the IP header */
+  LWIP_ASSERT("sizeof(struct ip_reass_helper) <= IP_HLEN",
+              sizeof(struct ip_reass_helper) <= IP_HLEN);
+  iprh = (struct ip_reass_helper*)new_p->payload;
+  iprh->next_pbuf = NULL;
+  iprh->start = offset;
+  iprh->end = offset + len;
+
+  /* Iterate through until we either get to the end of the list (append),
+   * or we find on with a larger offset (insert). */
+  for (q = ipr->p; q != NULL;) {
+    iprh_tmp = (struct ip_reass_helper*)q->payload;
+    if (iprh->start < iprh_tmp->start) {
+      /* the new pbuf should be inserted before this */
+      iprh->next_pbuf = q;
+      if (iprh_prev != NULL) {
+        /* not the fragment with the lowest offset */
+#if IP_REASS_CHECK_OVERLAP
+        if ((iprh->start < iprh_prev->end) || (iprh->end > iprh_tmp->start)) {
+          /* fragment overlaps with previous or following, throw away */
+          goto freepbuf;
+        }
+#endif /* IP_REASS_CHECK_OVERLAP */
+        iprh_prev->next_pbuf = new_p;
+      } else {
+        /* fragment with the lowest offset */
+        ipr->p = new_p;
+      }
+      break;
+    } else if(iprh->start == iprh_tmp->start) {
+      /* received the same datagram twice: no need to keep the datagram */
+      goto freepbuf;
+#if IP_REASS_CHECK_OVERLAP
+    } else if(iprh->start < iprh_tmp->end) {
+      /* overlap: no need to keep the new datagram */
+      goto freepbuf;
+#endif /* IP_REASS_CHECK_OVERLAP */
+    } else {
+      /* Check if the fragments received so far have no wholes. */
+      if (iprh_prev != NULL) {
+        if (iprh_prev->end != iprh_tmp->start) {
+          /* There is a fragment missing between the current
+           * and the previous fragment */
+          valid = 0;
+        }
+      }
+    }
+    q = iprh_tmp->next_pbuf;
+    iprh_prev = iprh_tmp;
+  }
+
+  /* If q is NULL, then we made it to the end of the list. Determine what to do now */
+  if (q == NULL) {
+    if (iprh_prev != NULL) {
+      /* this is (for now), the fragment with the highest offset:
+       * chain it to the last fragment */
+#if IP_REASS_CHECK_OVERLAP
+      LWIP_ASSERT("check fragments don't overlap", iprh_prev->end <= iprh->start);
+#endif /* IP_REASS_CHECK_OVERLAP */
+      iprh_prev->next_pbuf = new_p;
+      if (iprh_prev->end != iprh->start) {
+        valid = 0;
+      }
+    } else {
+#if IP_REASS_CHECK_OVERLAP
+      LWIP_ASSERT("no previous fragment, this must be the first fragment!",
+        ipr->p == NULL);
+#endif /* IP_REASS_CHECK_OVERLAP */
+      /* this is the first fragment we ever received for this ip datagram */
+      ipr->p = new_p;
+    }
+  }
+
+  /* At this point, the validation part begins: */
+  /* If we already received the last fragment */
+  if ((ipr->flags & IP_REASS_FLAG_LASTFRAG) != 0) {
+    /* and had no wholes so far */
+    if (valid) {
+      /* then check if the rest of the fragments is here */
+      /* Check if the queue starts with the first datagram */
+      if (((struct ip_reass_helper*)ipr->p->payload)->start != 0) {
+        valid = 0;
+      } else {
+        /* and check that there are no wholes after this datagram */
+        iprh_prev = iprh;
+        q = iprh->next_pbuf;
+        while (q != NULL) {
+          iprh = (struct ip_reass_helper*)q->payload;
+          if (iprh_prev->end != iprh->start) {
+            valid = 0;
+            break;
+          }
+          iprh_prev = iprh;
+          q = iprh->next_pbuf;
+        }
+        /* if still valid, all fragments are received
+         * (because to the MF==0 already arrived */
+        if (valid) {
+          LWIP_ASSERT("sanity check", ipr->p != NULL);
+          LWIP_ASSERT("sanity check",
+            ((struct ip_reass_helper*)ipr->p->payload) != iprh);
+          LWIP_ASSERT("validate_datagram:next_pbuf!=NULL",
+            iprh->next_pbuf == NULL);
+          LWIP_ASSERT("validate_datagram:datagram end!=datagram len",
+            iprh->end == ipr->datagram_len);
+        }
+      }
+    }
+    /* If valid is 0 here, there are some fragments missing in the middle
+     * (since MF == 0 has already arrived). Such datagrams simply time out if
+     * no more fragments are received... */
+    return valid;
+  }
+  /* If we come here, not all fragments were received, yet! */
+  return 0; /* not yet valid! */
+#if IP_REASS_CHECK_OVERLAP
+freepbuf:
+  ip_reass_pbufcount -= pbuf_clen(new_p);
+  pbuf_free(new_p);
+  return 0;
+#endif /* IP_REASS_CHECK_OVERLAP */
+}
+
+/**
+ * Reassembles incoming IP fragments into an IP datagram.
+ *
+ * @param p points to a pbuf chain of the fragment
+ * @return NULL if reassembly is incomplete, ? otherwise
+ */
+struct pbuf *
+ip_reass(struct pbuf *p)
+{
+  struct pbuf *r;
+  struct ip_hdr *fraghdr;
+  struct ip_reassdata *ipr;
+  struct ip_reass_helper *iprh;
+  u16_t offset, len;
+  u8_t clen;
+  struct ip_reassdata *ipr_prev = NULL;
+
+  IPFRAG_STATS_INC(ip_frag.recv);
+  snmp_inc_ipreasmreqds();
+
+  fraghdr = (struct ip_hdr*)p->payload;
+
+  if ((IPH_HL(fraghdr) * 4) != IP_HLEN) {
+    LWIP_DEBUGF(IP_REASS_DEBUG,("ip_reass: IP options currently not supported!\n"));
+    IPFRAG_STATS_INC(ip_frag.err);
+    goto nullreturn;
+  }
+
+  offset = (ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) * 8;
+  len = ntohs(IPH_LEN(fraghdr)) - IPH_HL(fraghdr) * 4;
+
+  /* Check if we are allowed to enqueue more datagrams. */
+  clen = pbuf_clen(p);
+  if ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS) {
+#if IP_REASS_FREE_OLDEST
+    if (!ip_reass_remove_oldest_datagram(fraghdr, clen) ||
+        ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS))
+#endif /* IP_REASS_FREE_OLDEST */
+    {
+      /* No datagram could be freed and still too many pbufs enqueued */
+      LWIP_DEBUGF(IP_REASS_DEBUG,("ip_reass: Overflow condition: pbufct=%d, clen=%d, MAX=%d\n",
+        ip_reass_pbufcount, clen, IP_REASS_MAX_PBUFS));
+      IPFRAG_STATS_INC(ip_frag.memerr);
+      /* @todo: send ICMP time exceeded here? */
+      /* drop this pbuf */
+      goto nullreturn;
+    }
+  }
+
+  /* Look for the datagram the fragment belongs to in the current datagram queue,
+   * remembering the previous in the queue for later dequeueing. */
+  for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) {
+    /* Check if the incoming fragment matches the one currently present
+       in the reassembly buffer. If so, we proceed with copying the
+       fragment into the buffer. */
+    if (IP_ADDRESSES_AND_ID_MATCH(&ipr->iphdr, fraghdr)) {
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: matching previous fragment ID=%"X16_F"\n",
+        ntohs(IPH_ID(fraghdr))));
+      IPFRAG_STATS_INC(ip_frag.cachehit);
+      break;
+    }
+    ipr_prev = ipr;
+  }
+
+  if (ipr == NULL) {
+  /* Enqueue a new datagram into the datagram queue */
+    ipr = ip_reass_enqueue_new_datagram(fraghdr, clen);
+    /* Bail if unable to enqueue */
+    if(ipr == NULL) {
+      goto nullreturn;
+    }
+  } else {
+    if (((ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) && 
+      ((ntohs(IPH_OFFSET(&ipr->iphdr)) & IP_OFFMASK) != 0)) {
+      /* ipr->iphdr is not the header from the first fragment, but fraghdr is
+       * -> copy fraghdr into ipr->iphdr since we want to have the header
+       * of the first fragment (for ICMP time exceeded and later, for copying
+       * all options, if supported)*/
+      SMEMCPY(&ipr->iphdr, fraghdr, IP_HLEN);
+    }
+  }
+  /* Track the current number of pbufs current 'in-flight', in order to limit 
+  the number of fragments that may be enqueued at any one time */
+  ip_reass_pbufcount += clen;
+
+  /* At this point, we have either created a new entry or pointing 
+   * to an existing one */
+
+  /* check for 'no more fragments', and update queue entry*/
+  if ((IPH_OFFSET(fraghdr) & PP_NTOHS(IP_MF)) == 0) {
+    ipr->flags |= IP_REASS_FLAG_LASTFRAG;
+    ipr->datagram_len = offset + len;
+    LWIP_DEBUGF(IP_REASS_DEBUG,
+     ("ip_reass: last fragment seen, total len %"S16_F"\n",
+      ipr->datagram_len));
+  }
+  /* find the right place to insert this pbuf */
+  /* @todo: trim pbufs if fragments are overlapping */
+  if (ip_reass_chain_frag_into_datagram_and_validate(ipr, p)) {
+    /* the totally last fragment (flag more fragments = 0) was received at least
+     * once AND all fragments are received */
+    ipr->datagram_len += IP_HLEN;
+
+    /* save the second pbuf before copying the header over the pointer */
+    r = ((struct ip_reass_helper*)ipr->p->payload)->next_pbuf;
+
+    /* copy the original ip header back to the first pbuf */
+    fraghdr = (struct ip_hdr*)(ipr->p->payload);
+    SMEMCPY(fraghdr, &ipr->iphdr, IP_HLEN);
+    IPH_LEN_SET(fraghdr, htons(ipr->datagram_len));
+    IPH_OFFSET_SET(fraghdr, 0);
+    IPH_CHKSUM_SET(fraghdr, 0);
+    /* @todo: do we need to set calculate the correct checksum? */
+    IPH_CHKSUM_SET(fraghdr, inet_chksum(fraghdr, IP_HLEN));
+
+    p = ipr->p;
+
+    /* chain together the pbufs contained within the reass_data list. */
+    while(r != NULL) {
+      iprh = (struct ip_reass_helper*)r->payload;
+
+      /* hide the ip header for every succeding fragment */
+      pbuf_header(r, -IP_HLEN);
+      pbuf_cat(p, r);
+      r = iprh->next_pbuf;
+    }
+    /* release the sources allocate for the fragment queue entry */
+    ip_reass_dequeue_datagram(ipr, ipr_prev);
+
+    /* and adjust the number of pbufs currently queued for reassembly. */
+    ip_reass_pbufcount -= pbuf_clen(p);
+
+    /* Return the pbuf chain */
+    return p;
+  }
+  /* the datagram is not (yet?) reassembled completely */
+  LWIP_DEBUGF(IP_REASS_DEBUG,("ip_reass_pbufcount: %d out\n", ip_reass_pbufcount));
+  return NULL;
+
+nullreturn:
+  LWIP_DEBUGF(IP_REASS_DEBUG,("ip_reass: nullreturn\n"));
+  IPFRAG_STATS_INC(ip_frag.drop);
+  pbuf_free(p);
+  return NULL;
+}
+#endif /* IP_REASSEMBLY */
+
+#if IP_FRAG
+#if IP_FRAG_USES_STATIC_BUF
+static u8_t buf[LWIP_MEM_ALIGN_SIZE(IP_FRAG_MAX_MTU + MEM_ALIGNMENT - 1)];
+#else /* IP_FRAG_USES_STATIC_BUF */
+
+#if !LWIP_NETIF_TX_SINGLE_PBUF
+/** Allocate a new struct pbuf_custom_ref */
+static struct pbuf_custom_ref*
+ip_frag_alloc_pbuf_custom_ref(void)
+{
+  return (struct pbuf_custom_ref*)memp_malloc(MEMP_FRAG_PBUF);
+}
+
+/** Free a struct pbuf_custom_ref */
+static void
+ip_frag_free_pbuf_custom_ref(struct pbuf_custom_ref* p)
+{
+  LWIP_ASSERT("p != NULL", p != NULL);
+  memp_free(MEMP_FRAG_PBUF, p);
+}
+
+/** Free-callback function to free a 'struct pbuf_custom_ref', called by
+ * pbuf_free. */
+static void
+ipfrag_free_pbuf_custom(struct pbuf *p)
+{
+  struct pbuf_custom_ref *pcr = (struct pbuf_custom_ref*)p;
+  LWIP_ASSERT("pcr != NULL", pcr != NULL);
+  LWIP_ASSERT("pcr == p", (void*)pcr == (void*)p);
+  if (pcr->original != NULL) {
+    pbuf_free(pcr->original);
+  }
+  ip_frag_free_pbuf_custom_ref(pcr);
+}
+#endif /* !LWIP_NETIF_TX_SINGLE_PBUF */
+#endif /* IP_FRAG_USES_STATIC_BUF */
+
+/**
+ * Fragment an IP datagram if too large for the netif.
+ *
+ * Chop the datagram in MTU sized chunks and send them in order
+ * by using a fixed size static memory buffer (PBUF_REF) or
+ * point PBUF_REFs into p (depending on IP_FRAG_USES_STATIC_BUF).
+ *
+ * @param p ip packet to send
+ * @param netif the netif on which to send
+ * @param dest destination ip address to which to send
+ *
+ * @return ERR_OK if sent successfully, err_t otherwise
+ */
+err_t 
+ip_frag(struct pbuf *p, struct netif *netif, ip_addr_t *dest)
+{
+  struct pbuf *rambuf;
+#if IP_FRAG_USES_STATIC_BUF
+  struct pbuf *header;
+#else
+#if !LWIP_NETIF_TX_SINGLE_PBUF
+  struct pbuf *newpbuf;
+#endif
+  struct ip_hdr *original_iphdr;
+#endif
+  struct ip_hdr *iphdr;
+  u16_t nfb;
+  u16_t left, cop;
+  u16_t mtu = netif->mtu;
+  u16_t ofo, omf;
+  u16_t last;
+  u16_t poff = IP_HLEN;
+  u16_t tmp;
+#if !IP_FRAG_USES_STATIC_BUF && !LWIP_NETIF_TX_SINGLE_PBUF
+  u16_t newpbuflen = 0;
+  u16_t left_to_copy;
+#endif
+
+  /* Get a RAM based MTU sized pbuf */
+#if IP_FRAG_USES_STATIC_BUF
+  /* When using a static buffer, we use a PBUF_REF, which we will
+   * use to reference the packet (without link header).
+   * Layer and length is irrelevant.
+   */
+  rambuf = pbuf_alloc(PBUF_LINK, 0, PBUF_REF);
+  if (rambuf == NULL) {
+    LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_frag: pbuf_alloc(PBUF_LINK, 0, PBUF_REF) failed\n"));
+    return ERR_MEM;
+  }
+  rambuf->tot_len = rambuf->len = mtu;
+  rambuf->payload = LWIP_MEM_ALIGN((void *)buf);
+
+  /* Copy the IP header in it */
+  iphdr = (struct ip_hdr *)rambuf->payload;
+  SMEMCPY(iphdr, p->payload, IP_HLEN);
+#else /* IP_FRAG_USES_STATIC_BUF */
+  original_iphdr = (struct ip_hdr *)p->payload;
+  iphdr = original_iphdr;
+#endif /* IP_FRAG_USES_STATIC_BUF */
+
+  /* Save original offset */
+  tmp = ntohs(IPH_OFFSET(iphdr));
+  ofo = tmp & IP_OFFMASK;
+  omf = tmp & IP_MF;
+
+  left = p->tot_len - IP_HLEN;
+
+  nfb = (mtu - IP_HLEN) / 8;
+
+  while (left) {
+    last = (left <= mtu - IP_HLEN);
+
+    /* Set new offset and MF flag */
+    tmp = omf | (IP_OFFMASK & (ofo));
+    if (!last) {
+      tmp = tmp | IP_MF;
+    }
+
+    /* Fill this fragment */
+    cop = last ? left : nfb * 8;
+
+#if IP_FRAG_USES_STATIC_BUF
+    poff += pbuf_copy_partial(p, (u8_t*)iphdr + IP_HLEN, cop, poff);
+#else /* IP_FRAG_USES_STATIC_BUF */
+#if LWIP_NETIF_TX_SINGLE_PBUF
+    rambuf = pbuf_alloc(PBUF_IP, cop, PBUF_RAM);
+    if (rambuf == NULL) {
+      return ERR_MEM;
+    }
+    LWIP_ASSERT("this needs a pbuf in one piece!",
+      (rambuf->len == rambuf->tot_len) && (rambuf->next == NULL));
+    poff += pbuf_copy_partial(p, rambuf->payload, cop, poff);
+    /* make room for the IP header */
+    if(pbuf_header(rambuf, IP_HLEN)) {
+      pbuf_free(rambuf);
+      return ERR_MEM;
+    }
+    /* fill in the IP header */
+    SMEMCPY(rambuf->payload, original_iphdr, IP_HLEN);
+    iphdr = rambuf->payload;
+#else /* LWIP_NETIF_TX_SINGLE_PBUF */
+    /* When not using a static buffer, create a chain of pbufs.
+     * The first will be a PBUF_RAM holding the link and IP header.
+     * The rest will be PBUF_REFs mirroring the pbuf chain to be fragged,
+     * but limited to the size of an mtu.
+     */
+    rambuf = pbuf_alloc(PBUF_LINK, IP_HLEN, PBUF_RAM);
+    if (rambuf == NULL) {
+      return ERR_MEM;
+    }
+    LWIP_ASSERT("this needs a pbuf in one piece!",
+                (p->len >= (IP_HLEN)));
+    SMEMCPY(rambuf->payload, original_iphdr, IP_HLEN);
+    iphdr = (struct ip_hdr *)rambuf->payload;
+
+    /* Can just adjust p directly for needed offset. */
+    p->payload = (u8_t *)p->payload + poff;
+    p->len -= poff;
+
+    left_to_copy = cop;
+    while (left_to_copy) {
+      struct pbuf_custom_ref *pcr;
+      newpbuflen = (left_to_copy < p->len) ? left_to_copy : p->len;
+      /* Is this pbuf already empty? */
+      if (!newpbuflen) {
+        p = p->next;
+        continue;
+      }
+      pcr = ip_frag_alloc_pbuf_custom_ref();
+      if (pcr == NULL) {
+        pbuf_free(rambuf);
+        return ERR_MEM;
+      }
+      /* Mirror this pbuf, although we might not need all of it. */
+      newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc, p->payload, newpbuflen);
+      if (newpbuf == NULL) {
+        ip_frag_free_pbuf_custom_ref(pcr);
+        pbuf_free(rambuf);
+        return ERR_MEM;
+      }
+      pbuf_ref(p);
+      pcr->original = p;
+      pcr->pc.custom_free_function = ipfrag_free_pbuf_custom;
+
+      /* Add it to end of rambuf's chain, but using pbuf_cat, not pbuf_chain
+       * so that it is removed when pbuf_dechain is later called on rambuf.
+       */
+      pbuf_cat(rambuf, newpbuf);
+      left_to_copy -= newpbuflen;
+      if (left_to_copy) {
+        p = p->next;
+      }
+    }
+    poff = newpbuflen;
+#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
+#endif /* IP_FRAG_USES_STATIC_BUF */
+
+    /* Correct header */
+    IPH_OFFSET_SET(iphdr, htons(tmp));
+    IPH_LEN_SET(iphdr, htons(cop + IP_HLEN));
+    IPH_CHKSUM_SET(iphdr, 0);
+    IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
+
+#if IP_FRAG_USES_STATIC_BUF
+    if (last) {
+      pbuf_realloc(rambuf, left + IP_HLEN);
+    }
+
+    /* This part is ugly: we alloc a RAM based pbuf for 
+     * the link level header for each chunk and then 
+     * free it.A PBUF_ROM style pbuf for which pbuf_header
+     * worked would make things simpler.
+     */
+    header = pbuf_alloc(PBUF_LINK, 0, PBUF_RAM);
+    if (header != NULL) {
+      pbuf_chain(header, rambuf);
+      netif->output(netif, header, dest);
+      IPFRAG_STATS_INC(ip_frag.xmit);
+      snmp_inc_ipfragcreates();
+      pbuf_free(header);
+    } else {
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_frag: pbuf_alloc() for header failed\n"));
+      pbuf_free(rambuf);
+      return ERR_MEM;
+    }
+#else /* IP_FRAG_USES_STATIC_BUF */
+    /* No need for separate header pbuf - we allowed room for it in rambuf
+     * when allocated.
+     */
+    netif->output(netif, rambuf, dest);
+    IPFRAG_STATS_INC(ip_frag.xmit);
+
+    /* Unfortunately we can't reuse rambuf - the hardware may still be
+     * using the buffer. Instead we free it (and the ensuing chain) and
+     * recreate it next time round the loop. If we're lucky the hardware
+     * will have already sent the packet, the free will really free, and
+     * there will be zero memory penalty.
+     */
+    
+    pbuf_free(rambuf);
+#endif /* IP_FRAG_USES_STATIC_BUF */
+    left -= cop;
+    ofo += nfb;
+  }
+#if IP_FRAG_USES_STATIC_BUF
+  pbuf_free(rambuf);
+#endif /* IP_FRAG_USES_STATIC_BUF */
+  snmp_inc_ipfragoks();
+  return ERR_OK;
+}
+#endif /* IP_FRAG */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv6/README b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv6/README
new file mode 100644
index 0000000..3620004
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv6/README
@@ -0,0 +1 @@
+IPv6 support in lwIP is very experimental.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv6/icmp6.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv6/icmp6.c
new file mode 100644
index 0000000..4fcc895
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv6/icmp6.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* Some ICMP messages should be passed to the transport protocols. This
+   is not implemented. */
+
+#include "lwip/opt.h"
+
+#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/icmp.h"
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+#include "lwip/def.h"
+#include "lwip/stats.h"
+
+void
+icmp_input(struct pbuf *p, struct netif *inp)
+{
+  u8_t type;
+  struct icmp_echo_hdr *iecho;
+  struct ip_hdr *iphdr;
+  struct ip_addr tmpaddr;
+
+  ICMP_STATS_INC(icmp.recv);
+
+  /* TODO: check length before accessing payload! */
+
+  type = ((u8_t *)p->payload)[0];
+
+  switch (type) {
+  case ICMP6_ECHO:
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
+
+    if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n"));
+
+      pbuf_free(p);
+      ICMP_STATS_INC(icmp.lenerr);
+      return;
+    }
+    iecho = p->payload;
+    iphdr = (struct ip_hdr *)((u8_t *)p->payload - IP_HLEN);
+    if (inet_chksum_pbuf(p) != 0) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%"X16_F")\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len)));
+      ICMP_STATS_INC(icmp.chkerr);
+    /*      return;*/
+    }
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp: p->len %"S16_F" p->tot_len %"S16_F"\n", p->len, p->tot_len));
+    ip_addr_set(&tmpaddr, &(iphdr->src));
+    ip_addr_set(&(iphdr->src), &(iphdr->dest));
+    ip_addr_set(&(iphdr->dest), &tmpaddr);
+    iecho->type = ICMP6_ER;
+    /* adjust the checksum */
+    if (iecho->chksum >= htons(0xffff - (ICMP6_ECHO << 8))) {
+      iecho->chksum += htons(ICMP6_ECHO << 8) + 1;
+    } else {
+      iecho->chksum += htons(ICMP6_ECHO << 8);
+    }
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%"X16_F")\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len)));
+    ICMP_STATS_INC(icmp.xmit);
+
+    /*    LWIP_DEBUGF("icmp: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len);*/
+    ip_output_if (p, &(iphdr->src), IP_HDRINCL,
+     iphdr->hoplim, IP_PROTO_ICMP, inp);
+    break;
+  default:
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" not supported.\n", (s16_t)type));
+    ICMP_STATS_INC(icmp.proterr);
+    ICMP_STATS_INC(icmp.drop);
+  }
+
+  pbuf_free(p);
+}
+
+void
+icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  struct icmp_dur_hdr *idur;
+
+  /* @todo: can this be PBUF_LINK instead of PBUF_IP? */
+  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
+  /* ICMP header + IP header + 8 bytes of data */
+  if (q == NULL) {
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_dest_unreach: failed to allocate pbuf for ICMP packet.\n"));
+    pbuf_free(p);
+    return;
+  }
+  LWIP_ASSERT("check that first pbuf can hold icmp message",
+             (q->len >= (8 + IP_HLEN + 8)));
+
+  iphdr = p->payload;
+
+  idur = q->payload;
+  idur->type = (u8_t)ICMP6_DUR;
+  idur->icode = (u8_t)t;
+
+  SMEMCPY((u8_t *)q->payload + 8, p->payload, IP_HLEN + 8);
+
+  /* calculate checksum */
+  idur->chksum = 0;
+  idur->chksum = inet_chksum(idur, q->len);
+  ICMP_STATS_INC(icmp.xmit);
+
+  ip_output(q, NULL,
+      (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+void
+icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  struct icmp_te_hdr *tehdr;
+
+  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded\n"));
+
+  /* @todo: can this be PBUF_LINK instead of PBUF_IP? */
+  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
+  /* ICMP header + IP header + 8 bytes of data */
+  if (q == NULL) {
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_dest_unreach: failed to allocate pbuf for ICMP packet.\n"));
+    pbuf_free(p);
+    return;
+  }
+  LWIP_ASSERT("check that first pbuf can hold icmp message",
+             (q->len >= (8 + IP_HLEN + 8)));
+
+  iphdr = p->payload;
+
+  tehdr = q->payload;
+  tehdr->type = (u8_t)ICMP6_TE;
+  tehdr->icode = (u8_t)t;
+
+  /* copy fields from original packet */
+  SMEMCPY((u8_t *)q->payload + 8, (u8_t *)p->payload, IP_HLEN + 8);
+
+  /* calculate checksum */
+  tehdr->chksum = 0;
+  tehdr->chksum = inet_chksum(tehdr, q->len);
+  ICMP_STATS_INC(icmp.xmit);
+  ip_output(q, NULL,
+      (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+#endif /* LWIP_ICMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv6/inet6.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv6/inet6.c
new file mode 100644
index 0000000..c3de85c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv6/inet6.c
@@ -0,0 +1,163 @@
+/**
+ * @file
+ * Functions common to all TCP/IPv6 modules, such as the Internet checksum and the
+ * byte order functions.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/inet.h"
+
+/* chksum:
+ *
+ * Sums up all 16 bit words in a memory portion. Also includes any odd byte.
+ * This function is used by the other checksum functions.
+ *
+ * For now, this is not optimized. Must be optimized for the particular processor
+ * arcitecture on which it is to run. Preferebly coded in assembler.
+ */
+
+static u32_t
+chksum(void *dataptr, u16_t len)
+{
+  u16_t *sdataptr = dataptr;
+  u32_t acc;
+  
+  
+  for(acc = 0; len > 1; len -= 2) {
+    acc += *sdataptr++;
+  }
+
+  /* add up any odd byte */
+  if (len == 1) {
+    acc += htons((u16_t)(*(u8_t *)dataptr) << 8);
+  }
+
+  return acc;
+
+}
+
+/* inet_chksum_pseudo:
+ *
+ * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
+ */
+
+u16_t
+inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u32_t proto_len)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped, i;
+
+  acc = 0;
+  swapped = 0;
+  for(q = p; q != NULL; q = q->next) {    
+    acc += chksum(q->payload, q->len);
+    while (acc >> 16) {
+      acc = (acc & 0xffff) + (acc >> 16);
+    }
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+    }
+  }
+
+  if (swapped) {
+    acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+  }
+  
+  for(i = 0; i < 8; i++) {
+    acc += ((u16_t *)src->addr)[i] & 0xffff;
+    acc += ((u16_t *)dest->addr)[i] & 0xffff;
+    while (acc >> 16) {
+      acc = (acc & 0xffff) + (acc >> 16);
+    }
+  }
+  acc += (u16_t)htons((u16_t)proto);
+  acc += ((u16_t *)&proto_len)[0] & 0xffff;
+  acc += ((u16_t *)&proto_len)[1] & 0xffff;
+
+  while (acc >> 16) {
+    acc = (acc & 0xffff) + (acc >> 16);
+  }
+  return ~(acc & 0xffff);
+}
+
+/* inet_chksum:
+ *
+ * Calculates the Internet checksum over a portion of memory. Used primarely for IP
+ * and ICMP.
+ */
+
+u16_t
+inet_chksum(void *dataptr, u16_t len)
+{
+  u32_t acc, sum;
+
+  acc = chksum(dataptr, len);
+  sum = (acc & 0xffff) + (acc >> 16);
+  sum += (sum >> 16);
+  return ~(sum & 0xffff);
+}
+
+u16_t
+inet_chksum_pbuf(struct pbuf *p)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped;
+  
+  acc = 0;
+  swapped = 0;
+  for(q = p; q != NULL; q = q->next) {
+    acc += chksum(q->payload, q->len);
+    while (acc >> 16) {
+      acc = (acc & 0xffff) + (acc >> 16);
+    }    
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = (acc & 0xff << 8) | (acc & 0xff00 >> 8);
+    }
+  }
+ 
+  if (swapped) {
+    acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+  }
+  return ~(acc & 0xffff);
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv6/ip6.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv6/ip6.c
new file mode 100644
index 0000000..b945fc5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv6/ip6.c
@@ -0,0 +1,397 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+
+/* ip.c
+ *
+ * This is the code for the IP layer for IPv6.
+ *
+ */
+
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/ip.h"
+#include "lwip/inet.h"
+#include "lwip/netif.h"
+#include "lwip/icmp.h"
+#include "lwip/udp.h"
+#include "lwip/tcp_impl.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+
+/* ip_init:
+ *
+ * Initializes the IP layer.
+ */
+
+void
+ip_init(void)
+{
+}
+
+/* ip_route:
+ *
+ * Finds the appropriate network interface for a given IP address. It searches the
+ * list of network interfaces linearly. A match is found if the masked IP address of
+ * the network interface equals the masked IP address given to the function.
+ */
+
+struct netif *
+ip_route(struct ip_addr *dest)
+{
+  struct netif *netif;
+
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+    if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) {
+      return netif;
+    }
+  }
+
+  return netif_default;
+}
+
+/* ip_forward:
+ *
+ * Forwards an IP packet. It finds an appropriate route for the packet, decrements
+ * the TTL value of the packet, adjusts the checksum and outputs the packet on the
+ * appropriate interface.
+ */
+
+static void
+ip_forward(struct pbuf *p, struct ip_hdr *iphdr)
+{
+  struct netif *netif;
+
+  PERF_START;
+
+  if ((netif = ip_route((struct ip_addr *)&(iphdr->dest))) == NULL) {
+
+    LWIP_DEBUGF(IP_DEBUG, ("ip_input: no forwarding route found for "));
+#if IP_DEBUG
+    ip_addr_debug_print(IP_DEBUG, ((struct ip_addr *)&(iphdr->dest)));
+#endif /* IP_DEBUG */
+    LWIP_DEBUGF(IP_DEBUG, ("\n"));
+    pbuf_free(p);
+    return;
+  }
+  /* Decrement TTL and send ICMP if ttl == 0. */
+  if (--iphdr->hoplim == 0) {
+#if LWIP_ICMP
+    /* Don't send ICMP messages in response to ICMP messages */
+    if (iphdr->nexthdr != IP_PROTO_ICMP) {
+      icmp_time_exceeded(p, ICMP_TE_TTL);
+    }
+#endif /* LWIP_ICMP */
+    pbuf_free(p);
+    return;
+  }
+
+  /* Incremental update of the IP checksum. */
+  /*  if (iphdr->chksum >= htons(0xffff - 0x100)) {
+    iphdr->chksum += htons(0x100) + 1;
+  } else {
+    iphdr->chksum += htons(0x100);
+    }*/
+
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to "));
+#if IP_DEBUG
+  ip_addr_debug_print(IP_DEBUG, ((struct ip_addr *)&(iphdr->dest)));
+#endif /* IP_DEBUG */
+  LWIP_DEBUGF(IP_DEBUG, ("\n"));
+
+  IP_STATS_INC(ip.fw);
+  IP_STATS_INC(ip.xmit);
+
+  PERF_STOP("ip_forward");
+
+  netif->output(netif, p, (struct ip_addr *)&(iphdr->dest));
+}
+
+/* ip_input:
+ *
+ * This function is called by the network interface device driver when an IP packet is
+ * received. The function does the basic checks of the IP header such as packet size
+ * being at least larger than the header size etc. If the packet was not destined for
+ * us, the packet is forwarded (using ip_forward). The IP checksum is always checked.
+ *
+ * Finally, the packet is sent to the upper layer protocol input function.
+ */
+
+void
+ip_input(struct pbuf *p, struct netif *inp) {
+  struct ip_hdr *iphdr;
+  struct netif *netif;
+
+
+  PERF_START;
+
+#if IP_DEBUG
+  ip_debug_print(p);
+#endif /* IP_DEBUG */
+
+
+  IP_STATS_INC(ip.recv);
+
+  /* identify the IP header */
+  iphdr = p->payload;
+
+
+  if (iphdr->v != 6) {
+    LWIP_DEBUGF(IP_DEBUG, ("IP packet dropped due to bad version number\n"));
+#if IP_DEBUG
+    ip_debug_print(p);
+#endif /* IP_DEBUG */
+    pbuf_free(p);
+    IP_STATS_INC(ip.err);
+    IP_STATS_INC(ip.drop);
+    return;
+  }
+
+  /* is this packet for us? */
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+#if IP_DEBUG
+    LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest "));
+    ip_addr_debug_print(IP_DEBUG, ((struct ip_addr *)&(iphdr->dest)));
+    LWIP_DEBUGF(IP_DEBUG, ("netif->ip_addr "));
+    ip_addr_debug_print(IP_DEBUG, ((struct ip_addr *)&(iphdr->dest)));
+    LWIP_DEBUGF(IP_DEBUG, ("\n"));
+#endif /* IP_DEBUG */
+    if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr))) {
+      break;
+    }
+  }
+
+
+  if (netif == NULL) {
+    /* packet not for us, route or discard */
+#if IP_FORWARD
+    ip_forward(p, iphdr);
+#endif
+    pbuf_free(p);
+    return;
+  }
+
+  pbuf_realloc(p, IP_HLEN + ntohs(iphdr->len));
+
+  /* send to upper layers */
+#if IP_DEBUG
+  /*  LWIP_DEBUGF("ip_input: \n");
+  ip_debug_print(p);
+  LWIP_DEBUGF("ip_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len);*/
+#endif /* IP_DEBUG */
+
+  if(pbuf_header(p, -IP_HLEN)) {
+    LWIP_ASSERT("Can't move over header in packet", 0);
+    return;
+  }
+
+  switch (iphdr->nexthdr) {
+  case IP_PROTO_UDP:
+    udp_input(p, inp);
+    break;
+  case IP_PROTO_TCP:
+    tcp_input(p, inp);
+    break;
+#if LWIP_ICMP
+  case IP_PROTO_ICMP:
+    icmp_input(p, inp);
+    break;
+#endif /* LWIP_ICMP */
+  default:
+#if LWIP_ICMP
+    /* send ICMP destination protocol unreachable */
+    icmp_dest_unreach(p, ICMP_DUR_PROTO);
+#endif /* LWIP_ICMP */
+    pbuf_free(p);
+    LWIP_DEBUGF(IP_DEBUG, ("Unsupported transport protocol %"U16_F"\n",
+          iphdr->nexthdr));
+
+    IP_STATS_INC(ip.proterr);
+    IP_STATS_INC(ip.drop);
+  }
+  PERF_STOP("ip_input");
+}
+
+
+/* ip_output_if:
+ *
+ * Sends an IP packet on a network interface. This function constructs the IP header
+ * and calculates the IP header checksum. If the source IP address is NULL,
+ * the IP address of the outgoing network interface is filled in as source address.
+ */
+
+err_t
+ip_output_if (struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+       u8_t ttl,
+       u8_t proto, struct netif *netif)
+{
+  struct ip_hdr *iphdr;
+
+  PERF_START;
+
+  LWIP_DEBUGF(IP_DEBUG, ("len %"U16_F" tot_len %"U16_F"\n", p->len, p->tot_len));
+  if (pbuf_header(p, IP_HLEN)) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_output: not enough room for IP header in pbuf\n"));
+    IP_STATS_INC(ip.err);
+
+    return ERR_BUF;
+  }
+  LWIP_DEBUGF(IP_DEBUG, ("len %"U16_F" tot_len %"U16_F"\n", p->len, p->tot_len));
+
+  iphdr = p->payload;
+
+
+  if (dest != IP_HDRINCL) {
+    LWIP_DEBUGF(IP_DEBUG, ("!IP_HDRLINCL\n"));
+    iphdr->hoplim = ttl;
+    iphdr->nexthdr = proto;
+    iphdr->len = htons(p->tot_len - IP_HLEN);
+    ip_addr_set(&(iphdr->dest), dest);
+
+    iphdr->v = 6;
+
+    if (ip_addr_isany(src)) {
+      ip_addr_set(&(iphdr->src), &(netif->ip_addr));
+    } else {
+      ip_addr_set(&(iphdr->src), src);
+    }
+
+  } else {
+    dest = &(iphdr->dest);
+  }
+
+  IP_STATS_INC(ip.xmit);
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c (len %"U16_F")\n", netif->name[0], netif->name[1], p->tot_len));
+#if IP_DEBUG
+  ip_debug_print(p);
+#endif /* IP_DEBUG */
+
+  PERF_STOP("ip_output_if");
+  return netif->output(netif, p, dest);
+}
+
+/* ip_output:
+ *
+ * Simple interface to ip_output_if. It finds the outgoing network interface and
+ * calls upon ip_output_if to do the actual work.
+ */
+
+err_t
+ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+    u8_t ttl, u8_t proto)
+{
+  struct netif *netif;
+  if ((netif = ip_route(dest)) == NULL) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to 0x%"X32_F"\n", dest->addr));
+    IP_STATS_INC(ip.rterr);
+    return ERR_RTE;
+  }
+
+  return ip_output_if (p, src, dest, ttl, proto, netif);
+}
+
+#if LWIP_NETIF_HWADDRHINT
+err_t
+ip_output_hinted(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+          u8_t ttl, u8_t tos, u8_t proto, u8_t *addr_hint)
+{
+  struct netif *netif;
+  err_t err;
+
+  if ((netif = ip_route(dest)) == NULL) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to 0x%"X32_F"\n", dest->addr));
+    IP_STATS_INC(ip.rterr);
+    return ERR_RTE;
+  }
+
+  netif->addr_hint = addr_hint;
+  err = ip_output_if(p, src, dest, ttl, tos, proto, netif);
+  netif->addr_hint = NULL;
+
+  return err;
+}
+#endif /* LWIP_NETIF_HWADDRHINT*/
+
+#if IP_DEBUG
+void
+ip_debug_print(struct pbuf *p)
+{
+  struct ip_hdr *iphdr = p->payload;
+
+  LWIP_DEBUGF(IP_DEBUG, ("IP header:\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" |  %"X16_F"%"X16_F"  |      %"X16_F"%"X16_F"           | (v, traffic class, flow label)\n",
+        iphdr->v,
+        iphdr->tclass1, iphdr->tclass2,
+        iphdr->flow1, iphdr->flow2));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|    %5"U16_F"      | %2"U16_F"  |  %2"U16_F"   | (len, nexthdr, hoplim)\n",
+        ntohs(iphdr->len),
+        iphdr->nexthdr,
+        iphdr->hoplim));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (src)\n",
+        (ntohl(iphdr->src.addr[0]) >> 16) & 0xffff,
+        ntohl(iphdr->src.addr[0]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (src)\n",
+        (ntohl(iphdr->src.addr[1]) >> 16) & 0xffff,
+        ntohl(iphdr->src.addr[1]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (src)\n",
+        (ntohl(iphdr->src.addr[2]) >> 16) & 0xffff,
+        ntohl(iphdr->src.addr[2]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (src)\n",
+        (ntohl(iphdr->src.addr[3]) >> 16) & 0xffff,
+        ntohl(iphdr->src.addr[3]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (dest)\n",
+        (ntohl(iphdr->dest.addr[0]) >> 16) & 0xffff,
+        ntohl(iphdr->dest.addr[0]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (dest)\n",
+        (ntohl(iphdr->dest.addr[1]) >> 16) & 0xffff,
+        ntohl(iphdr->dest.addr[1]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (dest)\n",
+        (ntohl(iphdr->dest.addr[2]) >> 16) & 0xffff,
+        ntohl(iphdr->dest.addr[2]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (dest)\n",
+        (ntohl(iphdr->dest.addr[3]) >> 16) & 0xffff,
+        ntohl(iphdr->dest.addr[3]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+}
+#endif /* IP_DEBUG */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv6/ip6_addr.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv6/ip6_addr.c
new file mode 100644
index 0000000..2da6cea
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/ipv6/ip6_addr.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+#include "lwip/ip_addr.h"
+#include "lwip/inet.h"
+
+u8_t
+ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2,
+                struct ip_addr *mask)
+{
+  return((addr1->addr[0] & mask->addr[0]) == (addr2->addr[0] & mask->addr[0]) &&
+         (addr1->addr[1] & mask->addr[1]) == (addr2->addr[1] & mask->addr[1]) &&
+         (addr1->addr[2] & mask->addr[2]) == (addr2->addr[2] & mask->addr[2]) &&
+         (addr1->addr[3] & mask->addr[3]) == (addr2->addr[3] & mask->addr[3]));
+        
+}
+
+u8_t
+ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2)
+{
+  return(addr1->addr[0] == addr2->addr[0] &&
+         addr1->addr[1] == addr2->addr[1] &&
+         addr1->addr[2] == addr2->addr[2] &&
+         addr1->addr[3] == addr2->addr[3]);
+}
+
+void
+ip_addr_set(struct ip_addr *dest, struct ip_addr *src)
+{
+  SMEMCPY(dest, src, sizeof(struct ip_addr));
+  /*  dest->addr[0] = src->addr[0];
+  dest->addr[1] = src->addr[1];
+  dest->addr[2] = src->addr[2];
+  dest->addr[3] = src->addr[3];*/
+}
+
+u8_t
+ip_addr_isany(struct ip_addr *addr)
+{
+  if (addr == NULL) return 1;
+  return((addr->addr[0] | addr->addr[1] | addr->addr[2] | addr->addr[3]) == 0);
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/lwip_timers.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/lwip_timers.c
new file mode 100644
index 0000000..dfed0bc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/lwip_timers.c
@@ -0,0 +1,482 @@
+/**
+ * @file
+ * Stack-internal timers implementation.
+ * This file includes timer callbacks for stack-internal timers as well as
+ * functions to set up or stop timers and check for expired timers.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *         Simon Goldschmidt
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/timers.h"
+#include "lwip/tcp_impl.h"
+
+#if LWIP_TIMERS
+
+#include "lwip/def.h"
+#include "lwip/memp.h"
+#include "lwip/tcpip.h"
+
+#include "lwip/ip_frag.h"
+#include "netif/etharp.h"
+#include "lwip/dhcp.h"
+#include "lwip/autoip.h"
+#include "lwip/igmp.h"
+#include "lwip/dns.h"
+
+
+/** The one and only timeout list */
+static struct sys_timeo *next_timeout;
+#if NO_SYS
+static u32_t timeouts_last_time;
+#endif /* NO_SYS */
+
+#if LWIP_TCP
+/** global variable that shows if the tcp timer is currently scheduled or not */
+static int tcpip_tcp_timer_active;
+
+/**
+ * Timer callback function that calls tcp_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+tcpip_tcp_timer(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+
+  /* call TCP timer handler */
+  tcp_tmr();
+  /* timer still needed? */
+  if (tcp_active_pcbs || tcp_tw_pcbs) {
+    /* restart timer */
+    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
+  } else {
+    /* disable timer */
+    tcpip_tcp_timer_active = 0;
+  }
+}
+
+/**
+ * Called from TCP_REG when registering a new PCB:
+ * the reason is to have the TCP timer only running when
+ * there are active (or time-wait) PCBs.
+ */
+void
+tcp_timer_needed(void)
+{
+  /* timer is off but needed again? */
+  if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) {
+    /* enable and start timer */
+    tcpip_tcp_timer_active = 1;
+    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
+  }
+}
+#endif /* LWIP_TCP */
+
+#if IP_REASSEMBLY
+/**
+ * Timer callback function that calls ip_reass_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+ip_reass_timer(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: ip_reass_tmr()\n"));
+  ip_reass_tmr();
+  sys_timeout(IP_TMR_INTERVAL, ip_reass_timer, NULL);
+}
+#endif /* IP_REASSEMBLY */
+
+#if LWIP_ARP
+/**
+ * Timer callback function that calls etharp_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+arp_timer(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: etharp_tmr()\n"));
+  etharp_tmr();
+  sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL);
+}
+#endif /* LWIP_ARP */
+
+#if LWIP_DHCP
+/**
+ * Timer callback function that calls dhcp_coarse_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+dhcp_timer_coarse(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: dhcp_coarse_tmr()\n"));
+  dhcp_coarse_tmr();
+  sys_timeout(DHCP_COARSE_TIMER_MSECS, dhcp_timer_coarse, NULL);
+}
+
+/**
+ * Timer callback function that calls dhcp_fine_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+dhcp_timer_fine(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: dhcp_fine_tmr()\n"));
+  dhcp_fine_tmr();
+  sys_timeout(DHCP_FINE_TIMER_MSECS, dhcp_timer_fine, NULL);
+}
+#endif /* LWIP_DHCP */
+
+#if LWIP_AUTOIP
+/**
+ * Timer callback function that calls autoip_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+autoip_timer(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: autoip_tmr()\n"));
+  autoip_tmr();
+  sys_timeout(AUTOIP_TMR_INTERVAL, autoip_timer, NULL);
+}
+#endif /* LWIP_AUTOIP */
+
+#if LWIP_IGMP
+/**
+ * Timer callback function that calls igmp_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+igmp_timer(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: igmp_tmr()\n"));
+  igmp_tmr();
+  sys_timeout(IGMP_TMR_INTERVAL, igmp_timer, NULL);
+}
+#endif /* LWIP_IGMP */
+
+#if LWIP_DNS
+/**
+ * Timer callback function that calls dns_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+dns_timer(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: dns_tmr()\n"));
+  dns_tmr();
+  sys_timeout(DNS_TMR_INTERVAL, dns_timer, NULL);
+}
+#endif /* LWIP_DNS */
+
+/** Initialize this module */
+void sys_timeouts_init(void)
+{
+#if IP_REASSEMBLY
+  sys_timeout(IP_TMR_INTERVAL, ip_reass_timer, NULL);
+#endif /* IP_REASSEMBLY */
+#if LWIP_ARP
+  sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL);
+#endif /* LWIP_ARP */
+#if LWIP_DHCP
+  sys_timeout(DHCP_COARSE_TIMER_MSECS, dhcp_timer_coarse, NULL);
+  sys_timeout(DHCP_FINE_TIMER_MSECS, dhcp_timer_fine, NULL);
+#endif /* LWIP_DHCP */
+#if LWIP_AUTOIP
+  sys_timeout(AUTOIP_TMR_INTERVAL, autoip_timer, NULL);
+#endif /* LWIP_AUTOIP */
+#if LWIP_IGMP
+  sys_timeout(IGMP_TMR_INTERVAL, igmp_timer, NULL);
+#endif /* LWIP_IGMP */
+#if LWIP_DNS
+  sys_timeout(DNS_TMR_INTERVAL, dns_timer, NULL);
+#endif /* LWIP_DNS */
+
+#if NO_SYS
+  /* Initialise timestamp for sys_check_timeouts */
+  timeouts_last_time = sys_now();
+#endif
+}
+
+/**
+ * Create a one-shot timer (aka timeout). Timeouts are processed in the
+ * following cases:
+ * - while waiting for a message using sys_timeouts_mbox_fetch()
+ * - by calling sys_check_timeouts() (NO_SYS==1 only)
+ *
+ * @param msecs time in milliseconds after that the timer should expire
+ * @param handler callback function to call when msecs have elapsed
+ * @param arg argument to pass to the callback function
+ */
+#if LWIP_DEBUG_TIMERNAMES
+void
+sys_timeout_debug(u32_t msecs, sys_timeout_handler handler, void *arg, const char* handler_name)
+#else /* LWIP_DEBUG_TIMERNAMES */
+void
+sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg)
+#endif /* LWIP_DEBUG_TIMERNAMES */
+{
+  struct sys_timeo *timeout, *t;
+
+  timeout = (struct sys_timeo *)memp_malloc(MEMP_SYS_TIMEOUT);
+  if (timeout == NULL) {
+    LWIP_ASSERT("sys_timeout: timeout != NULL, pool MEMP_SYS_TIMEOUT is empty", timeout != NULL);
+    return;
+  }
+  timeout->next = NULL;
+  timeout->h = handler;
+  timeout->arg = arg;
+  timeout->time = msecs;
+#if LWIP_DEBUG_TIMERNAMES
+  timeout->handler_name = handler_name;
+  LWIP_DEBUGF(TIMERS_DEBUG, ("sys_timeout: %p msecs=%"U32_F" handler=%s arg=%p\n",
+    (void *)timeout, msecs, handler_name, (void *)arg));
+#endif /* LWIP_DEBUG_TIMERNAMES */
+
+  if (next_timeout == NULL) {
+    next_timeout = timeout;
+    return;
+  }
+
+  if (next_timeout->time > msecs) {
+    next_timeout->time -= msecs;
+    timeout->next = next_timeout;
+    next_timeout = timeout;
+  } else {
+    for(t = next_timeout; t != NULL; t = t->next) {
+      timeout->time -= t->time;
+      if (t->next == NULL || t->next->time > timeout->time) {
+        if (t->next != NULL) {
+          t->next->time -= timeout->time;
+        }
+        timeout->next = t->next;
+        t->next = timeout;
+        break;
+      }
+    }
+  }
+}
+
+/**
+ * Go through timeout list (for this task only) and remove the first matching
+ * entry, even though the timeout has not triggered yet.
+ *
+ * @note This function only works as expected if there is only one timeout
+ * calling 'handler' in the list of timeouts.
+ *
+ * @param handler callback function that would be called by the timeout
+ * @param arg callback argument that would be passed to handler
+*/
+void
+sys_untimeout(sys_timeout_handler handler, void *arg)
+{
+  struct sys_timeo *prev_t, *t;
+
+  if (next_timeout == NULL) {
+    return;
+  }
+
+  for (t = next_timeout, prev_t = NULL; t != NULL; prev_t = t, t = t->next) {
+    if ((t->h == handler) && (t->arg == arg)) {
+      /* We have a match */
+      /* Unlink from previous in list */
+      if (prev_t == NULL) {
+        next_timeout = t->next;
+      } else {
+        prev_t->next = t->next;
+      }
+      /* If not the last one, add time of this one back to next */
+      if (t->next != NULL) {
+        t->next->time += t->time;
+      }
+      memp_free(MEMP_SYS_TIMEOUT, t);
+      return;
+    }
+  }
+  return;
+}
+
+#if NO_SYS
+
+/** Handle timeouts for NO_SYS==1 (i.e. without using
+ * tcpip_thread/sys_timeouts_mbox_fetch(). Uses sys_now() to call timeout
+ * handler functions when timeouts expire.
+ *
+ * Must be called periodically from your main loop.
+ */
+void
+sys_check_timeouts(void)
+{
+  struct sys_timeo *tmptimeout;
+  u32_t diff;
+  sys_timeout_handler handler;
+  void *arg;
+  int had_one;
+  u32_t now;
+
+  now = sys_now();
+  if (next_timeout) {
+    /* this cares for wraparounds */
+    diff = LWIP_U32_DIFF(now, timeouts_last_time);
+    do
+    {
+      had_one = 0;
+      tmptimeout = next_timeout;
+      if (tmptimeout->time <= diff) {
+        /* timeout has expired */
+        had_one = 1;
+        timeouts_last_time = now;
+        diff -= tmptimeout->time;
+        next_timeout = tmptimeout->next;
+        handler = tmptimeout->h;
+        arg = tmptimeout->arg;
+#if LWIP_DEBUG_TIMERNAMES
+        if (handler != NULL) {
+          LWIP_DEBUGF(TIMERS_DEBUG, ("sct calling h=%s arg=%p\n",
+            tmptimeout->handler_name, arg));
+        }
+#endif /* LWIP_DEBUG_TIMERNAMES */
+        memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
+        if (handler != NULL) {
+          handler(arg);
+        }
+      }
+    /* repeat until all expired timers have been called */
+    }while(had_one);
+  }
+}
+
+/** Set back the timestamp of the last call to sys_check_timeouts()
+ * This is necessary if sys_check_timeouts() hasn't been called for a long
+ * time (e.g. while saving energy) to prevent all timer functions of that
+ * period being called.
+ */
+void
+sys_restart_timeouts(void)
+{
+  timeouts_last_time = sys_now();
+}
+
+#else /* NO_SYS */
+
+/**
+ * Wait (forever) for a message to arrive in an mbox.
+ * While waiting, timeouts are processed.
+ *
+ * @param mbox the mbox to fetch the message from
+ * @param msg the place to store the message
+ */
+void
+sys_timeouts_mbox_fetch(sys_mbox_t *mbox, void **msg)
+{
+  u32_t time_needed;
+  struct sys_timeo *tmptimeout;
+  sys_timeout_handler handler;
+  void *arg;
+
+ again:
+  if (!next_timeout) {
+    time_needed = sys_arch_mbox_fetch(mbox, msg, 0);
+  } else {
+    if (next_timeout->time > 0) {
+      time_needed = sys_arch_mbox_fetch(mbox, msg, next_timeout->time);
+    } else {
+      time_needed = SYS_ARCH_TIMEOUT;
+    }
+
+    if (time_needed == SYS_ARCH_TIMEOUT) {
+      /* If time == SYS_ARCH_TIMEOUT, a timeout occurred before a message
+         could be fetched. We should now call the timeout handler and
+         deallocate the memory allocated for the timeout. */
+      tmptimeout = next_timeout;
+      next_timeout = tmptimeout->next;
+      handler = tmptimeout->h;
+      arg = tmptimeout->arg;
+#if LWIP_DEBUG_TIMERNAMES
+      if (handler != NULL) {
+        LWIP_DEBUGF(TIMERS_DEBUG, ("stmf calling h=%s arg=%p\n",
+          tmptimeout->handler_name, arg));
+      }
+#endif /* LWIP_DEBUG_TIMERNAMES */
+      memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
+      if (handler != NULL) {
+        /* For LWIP_TCPIP_CORE_LOCKING, lock the core before calling the
+           timeout handler function. */
+        LOCK_TCPIP_CORE();
+        handler(arg);
+        UNLOCK_TCPIP_CORE();
+      }
+      LWIP_TCPIP_THREAD_ALIVE();
+
+      /* We try again to fetch a message from the mbox. */
+      goto again;
+    } else {
+      /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout
+         occured. The time variable is set to the number of
+         milliseconds we waited for the message. */
+      if (time_needed < next_timeout->time) {
+        next_timeout->time -= time_needed;
+      } else {
+        next_timeout->time = 0;
+      }
+    }
+  }
+}
+
+#endif /* NO_SYS */
+
+#else /* LWIP_TIMERS */
+/* Satisfy the TCP code which calls this function */
+void
+tcp_timer_needed(void)
+{
+}
+#endif /* LWIP_TIMERS */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/mem.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/mem.c
new file mode 100644
index 0000000..9837555
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/mem.c
@@ -0,0 +1,642 @@
+/**
+ * @file
+ * Dynamic memory manager
+ *
+ * This is a lightweight replacement for the standard C library malloc().
+ *
+ * If you want to use the standard C library malloc() instead, define
+ * MEM_LIBC_MALLOC to 1 in your lwipopts.h
+ *
+ * To let mem_malloc() use pools (prevents fragmentation and is much faster than
+ * a heap but might waste some memory), define MEM_USE_POOLS to 1, define
+ * MEM_USE_CUSTOM_POOLS to 1 and create a file "lwippools.h" that includes a list
+ * of pools like this (more pools can be added between _START and _END):
+ *
+ * Define three pools with sizes 256, 512, and 1512 bytes
+ * LWIP_MALLOC_MEMPOOL_START
+ * LWIP_MALLOC_MEMPOOL(20, 256)
+ * LWIP_MALLOC_MEMPOOL(10, 512)
+ * LWIP_MALLOC_MEMPOOL(5, 1512)
+ * LWIP_MALLOC_MEMPOOL_END
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *         Simon Goldschmidt
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if !MEM_LIBC_MALLOC /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+#include "lwip/err.h"
+
+#include 
+
+#if MEM_USE_POOLS
+/* lwIP head implemented with different sized pools */
+
+/**
+ * Allocate memory: determine the smallest pool that is big enough
+ * to contain an element of 'size' and get an element from that pool.
+ *
+ * @param size the size in bytes of the memory needed
+ * @return a pointer to the allocated memory or NULL if the pool is empty
+ */
+void *
+mem_malloc(mem_size_t size)
+{
+  struct memp_malloc_helper *element;
+  memp_t poolnr;
+  mem_size_t required_size = size + sizeof(struct memp_malloc_helper);
+
+  for (poolnr = MEMP_POOL_FIRST; poolnr <= MEMP_POOL_LAST; poolnr = (memp_t)(poolnr + 1)) {
+#if MEM_USE_POOLS_TRY_BIGGER_POOL
+again:
+#endif /* MEM_USE_POOLS_TRY_BIGGER_POOL */
+    /* is this pool big enough to hold an element of the required size
+       plus a struct memp_malloc_helper that saves the pool this element came from? */
+    if (required_size <= memp_sizes[poolnr]) {
+      break;
+    }
+  }
+  if (poolnr > MEMP_POOL_LAST) {
+    LWIP_ASSERT("mem_malloc(): no pool is that big!", 0);
+    return NULL;
+  }
+  element = (struct memp_malloc_helper*)memp_malloc(poolnr);
+  if (element == NULL) {
+    /* No need to DEBUGF or ASSERT: This error is already
+       taken care of in memp.c */
+#if MEM_USE_POOLS_TRY_BIGGER_POOL
+    /** Try a bigger pool if this one is empty! */
+    if (poolnr < MEMP_POOL_LAST) {
+      poolnr++;
+      goto again;
+    }
+#endif /* MEM_USE_POOLS_TRY_BIGGER_POOL */
+    return NULL;
+  }
+
+  /* save the pool number this element came from */
+  element->poolnr = poolnr;
+  /* and return a pointer to the memory directly after the struct memp_malloc_helper */
+  element++;
+
+  return element;
+}
+
+/**
+ * Free memory previously allocated by mem_malloc. Loads the pool number
+ * and calls memp_free with that pool number to put the element back into
+ * its pool
+ *
+ * @param rmem the memory element to free
+ */
+void
+mem_free(void *rmem)
+{
+  struct memp_malloc_helper *hmem = (struct memp_malloc_helper*)rmem;
+
+  LWIP_ASSERT("rmem != NULL", (rmem != NULL));
+  LWIP_ASSERT("rmem == MEM_ALIGN(rmem)", (rmem == LWIP_MEM_ALIGN(rmem)));
+
+  /* get the original struct memp_malloc_helper */
+  hmem--;
+
+  LWIP_ASSERT("hmem != NULL", (hmem != NULL));
+  LWIP_ASSERT("hmem == MEM_ALIGN(hmem)", (hmem == LWIP_MEM_ALIGN(hmem)));
+  LWIP_ASSERT("hmem->poolnr < MEMP_MAX", (hmem->poolnr < MEMP_MAX));
+
+  /* and put it in the pool we saved earlier */
+  memp_free(hmem->poolnr, hmem);
+}
+
+#else /* MEM_USE_POOLS */
+/* lwIP replacement for your libc malloc() */
+
+/**
+ * The heap is made up as a list of structs of this type.
+ * This does not have to be aligned since for getting its size,
+ * we only use the macro SIZEOF_STRUCT_MEM, which automatically alignes.
+ */
+struct mem {
+  /** index (-> ram[next]) of the next struct */
+  mem_size_t next;
+  /** index (-> ram[prev]) of the previous struct */
+  mem_size_t prev;
+  /** 1: this area is used; 0: this area is unused */
+  u8_t used;
+};
+
+/** All allocated blocks will be MIN_SIZE bytes big, at least!
+ * MIN_SIZE can be overridden to suit your needs. Smaller values save space,
+ * larger values could prevent too small blocks to fragment the RAM too much. */
+#ifndef MIN_SIZE
+#define MIN_SIZE             12
+#endif /* MIN_SIZE */
+/* some alignment macros: we define them here for better source code layout */
+#define MIN_SIZE_ALIGNED     LWIP_MEM_ALIGN_SIZE(MIN_SIZE)
+#define SIZEOF_STRUCT_MEM    LWIP_MEM_ALIGN_SIZE(sizeof(struct mem))
+#define MEM_SIZE_ALIGNED     LWIP_MEM_ALIGN_SIZE(MEM_SIZE)
+
+/** If you want to relocate the heap to external memory, simply define
+ * LWIP_RAM_HEAP_POINTER as a void-pointer to that location.
+ * If so, make sure the memory at that location is big enough (see below on
+ * how that space is calculated). */
+#ifndef LWIP_RAM_HEAP_POINTER
+/** the heap. we need one struct mem at the end and some room for alignment */
+u8_t ram_heap[MEM_SIZE_ALIGNED + (2*SIZEOF_STRUCT_MEM) + MEM_ALIGNMENT];
+#define LWIP_RAM_HEAP_POINTER ram_heap
+#endif /* LWIP_RAM_HEAP_POINTER */
+
+/** pointer to the heap (ram_heap): for alignment, ram is now a pointer instead of an array */
+static u8_t *ram;
+/** the last entry, always unused! */
+static struct mem *ram_end;
+/** pointer to the lowest free block, this is used for faster search */
+static struct mem *lfree;
+
+/** concurrent access protection */
+static sys_mutex_t mem_mutex;
+
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+
+static volatile u8_t mem_free_count;
+
+/* Allow mem_free from other (e.g. interrupt) context */
+#define LWIP_MEM_FREE_DECL_PROTECT()  SYS_ARCH_DECL_PROTECT(lev_free)
+#define LWIP_MEM_FREE_PROTECT()       SYS_ARCH_PROTECT(lev_free)
+#define LWIP_MEM_FREE_UNPROTECT()     SYS_ARCH_UNPROTECT(lev_free)
+#define LWIP_MEM_ALLOC_DECL_PROTECT() SYS_ARCH_DECL_PROTECT(lev_alloc)
+#define LWIP_MEM_ALLOC_PROTECT()      SYS_ARCH_PROTECT(lev_alloc)
+#define LWIP_MEM_ALLOC_UNPROTECT()    SYS_ARCH_UNPROTECT(lev_alloc)
+
+#else /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+
+/* Protect the heap only by using a semaphore */
+#define LWIP_MEM_FREE_DECL_PROTECT()
+#define LWIP_MEM_FREE_PROTECT()    sys_mutex_lock(&mem_mutex)
+#define LWIP_MEM_FREE_UNPROTECT()  sys_mutex_unlock(&mem_mutex)
+/* mem_malloc is protected using semaphore AND LWIP_MEM_ALLOC_PROTECT */
+#define LWIP_MEM_ALLOC_DECL_PROTECT()
+#define LWIP_MEM_ALLOC_PROTECT()
+#define LWIP_MEM_ALLOC_UNPROTECT()
+
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+
+
+/**
+ * "Plug holes" by combining adjacent empty struct mems.
+ * After this function is through, there should not exist
+ * one empty struct mem pointing to another empty struct mem.
+ *
+ * @param mem this points to a struct mem which just has been freed
+ * @internal this function is only called by mem_free() and mem_trim()
+ *
+ * This assumes access to the heap is protected by the calling function
+ * already.
+ */
+static void
+plug_holes(struct mem *mem)
+{
+  struct mem *nmem;
+  struct mem *pmem;
+
+  LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram);
+  LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end);
+  LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0);
+
+  /* plug hole forward */
+  LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE_ALIGNED", mem->next <= MEM_SIZE_ALIGNED);
+
+  nmem = (struct mem *)(void *)&ram[mem->next];
+  if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) {
+    /* if mem->next is unused and not end of ram, combine mem and mem->next */
+    if (lfree == nmem) {
+      lfree = mem;
+    }
+    mem->next = nmem->next;
+    ((struct mem *)(void *)&ram[nmem->next])->prev = (mem_size_t)((u8_t *)mem - ram);
+  }
+
+  /* plug hole backward */
+  pmem = (struct mem *)(void *)&ram[mem->prev];
+  if (pmem != mem && pmem->used == 0) {
+    /* if mem->prev is unused, combine mem and mem->prev */
+    if (lfree == mem) {
+      lfree = pmem;
+    }
+    pmem->next = mem->next;
+    ((struct mem *)(void *)&ram[mem->next])->prev = (mem_size_t)((u8_t *)pmem - ram);
+  }
+}
+
+/**
+ * Zero the heap and initialize start, end and lowest-free
+ */
+void
+mem_init(void)
+{
+  struct mem *mem;
+
+  LWIP_ASSERT("Sanity check alignment",
+    (SIZEOF_STRUCT_MEM & (MEM_ALIGNMENT-1)) == 0);
+
+  /* align the heap */
+  ram = (u8_t *)LWIP_MEM_ALIGN(LWIP_RAM_HEAP_POINTER);
+  /* initialize the start of the heap */
+  mem = (struct mem *)(void *)ram;
+  mem->next = MEM_SIZE_ALIGNED;
+  mem->prev = 0;
+  mem->used = 0;
+  /* initialize the end of the heap */
+  ram_end = (struct mem *)(void *)&ram[MEM_SIZE_ALIGNED];
+  ram_end->used = 1;
+  ram_end->next = MEM_SIZE_ALIGNED;
+  ram_end->prev = MEM_SIZE_ALIGNED;
+
+  /* initialize the lowest-free pointer to the start of the heap */
+  lfree = (struct mem *)(void *)ram;
+
+  MEM_STATS_AVAIL(avail, MEM_SIZE_ALIGNED);
+
+  if(sys_mutex_new(&mem_mutex) != ERR_OK) {
+    LWIP_ASSERT("failed to create mem_mutex", 0);
+  }
+}
+
+/**
+ * Put a struct mem back on the heap
+ *
+ * @param rmem is the data portion of a struct mem as returned by a previous
+ *             call to mem_malloc()
+ */
+void
+mem_free(void *rmem)
+{
+  struct mem *mem;
+  LWIP_MEM_FREE_DECL_PROTECT();
+
+  if (rmem == NULL) {
+    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("mem_free(p == NULL) was called.\n"));
+    return;
+  }
+  LWIP_ASSERT("mem_free: sanity check alignment", (((mem_ptr_t)rmem) & (MEM_ALIGNMENT-1)) == 0);
+
+  LWIP_ASSERT("mem_free: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
+    (u8_t *)rmem < (u8_t *)ram_end);
+
+  if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
+    SYS_ARCH_DECL_PROTECT(lev);
+    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory\n"));
+    /* protect mem stats from concurrent access */
+    SYS_ARCH_PROTECT(lev);
+    MEM_STATS_INC(illegal);
+    SYS_ARCH_UNPROTECT(lev);
+    return;
+  }
+  /* protect the heap from concurrent access */
+  LWIP_MEM_FREE_PROTECT();
+  /* Get the corresponding struct mem ... */
+  mem = (struct mem *)(void *)((u8_t *)rmem - SIZEOF_STRUCT_MEM);
+  /* ... which has to be in a used state ... */
+  LWIP_ASSERT("mem_free: mem->used", mem->used);
+  /* ... and is now unused. */
+  mem->used = 0;
+
+  if (mem < lfree) {
+    /* the newly freed struct is now the lowest */
+    lfree = mem;
+  }
+
+  MEM_STATS_DEC_USED(used, mem->next - (mem_size_t)(((u8_t *)mem - ram)));
+
+  /* finally, see if prev or next are free also */
+  plug_holes(mem);
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+  mem_free_count = 1;
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+  LWIP_MEM_FREE_UNPROTECT();
+}
+
+/**
+ * Shrink memory returned by mem_malloc().
+ *
+ * @param rmem pointer to memory allocated by mem_malloc the is to be shrinked
+ * @param newsize required size after shrinking (needs to be smaller than or
+ *                equal to the previous size)
+ * @return for compatibility reasons: is always == rmem, at the moment
+ *         or NULL if newsize is > old size, in which case rmem is NOT touched
+ *         or freed!
+ */
+void *
+mem_trim(void *rmem, mem_size_t newsize)
+{
+  mem_size_t size;
+  mem_size_t ptr, ptr2;
+  struct mem *mem, *mem2;
+  /* use the FREE_PROTECT here: it protects with sem OR SYS_ARCH_PROTECT */
+  LWIP_MEM_FREE_DECL_PROTECT();
+
+  /* Expand the size of the allocated memory region so that we can
+     adjust for alignment. */
+  newsize = LWIP_MEM_ALIGN_SIZE(newsize);
+
+  if(newsize < MIN_SIZE_ALIGNED) {
+    /* every data block must be at least MIN_SIZE_ALIGNED long */
+    newsize = MIN_SIZE_ALIGNED;
+  }
+
+  if (newsize > MEM_SIZE_ALIGNED) {
+    return NULL;
+  }
+
+  LWIP_ASSERT("mem_trim: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
+   (u8_t *)rmem < (u8_t *)ram_end);
+
+  if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
+    SYS_ARCH_DECL_PROTECT(lev);
+    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_trim: illegal memory\n"));
+    /* protect mem stats from concurrent access */
+    SYS_ARCH_PROTECT(lev);
+    MEM_STATS_INC(illegal);
+    SYS_ARCH_UNPROTECT(lev);
+    return rmem;
+  }
+  /* Get the corresponding struct mem ... */
+  mem = (struct mem *)(void *)((u8_t *)rmem - SIZEOF_STRUCT_MEM);
+  /* ... and its offset pointer */
+  ptr = (mem_size_t)((u8_t *)mem - ram);
+
+  size = mem->next - ptr - SIZEOF_STRUCT_MEM;
+  LWIP_ASSERT("mem_trim can only shrink memory", newsize <= size);
+  if (newsize > size) {
+    /* not supported */
+    return NULL;
+  }
+  if (newsize == size) {
+    /* No change in size, simply return */
+    return rmem;
+  }
+
+  /* protect the heap from concurrent access */
+  LWIP_MEM_FREE_PROTECT();
+
+  mem2 = (struct mem *)(void *)&ram[mem->next];
+  if(mem2->used == 0) {
+    /* The next struct is unused, we can simply move it at little */
+    mem_size_t next;
+    /* remember the old next pointer */
+    next = mem2->next;
+    /* create new struct mem which is moved directly after the shrinked mem */
+    ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize;
+    if (lfree == mem2) {
+      lfree = (struct mem *)(void *)&ram[ptr2];
+    }
+    mem2 = (struct mem *)(void *)&ram[ptr2];
+    mem2->used = 0;
+    /* restore the next pointer */
+    mem2->next = next;
+    /* link it back to mem */
+    mem2->prev = ptr;
+    /* link mem to it */
+    mem->next = ptr2;
+    /* last thing to restore linked list: as we have moved mem2,
+     * let 'mem2->next->prev' point to mem2 again. but only if mem2->next is not
+     * the end of the heap */
+    if (mem2->next != MEM_SIZE_ALIGNED) {
+      ((struct mem *)(void *)&ram[mem2->next])->prev = ptr2;
+    }
+    MEM_STATS_DEC_USED(used, (size - newsize));
+    /* no need to plug holes, we've already done that */
+  } else if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED <= size) {
+    /* Next struct is used but there's room for another struct mem with
+     * at least MIN_SIZE_ALIGNED of data.
+     * Old size ('size') must be big enough to contain at least 'newsize' plus a struct mem
+     * ('SIZEOF_STRUCT_MEM') with some data ('MIN_SIZE_ALIGNED').
+     * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty
+     *       region that couldn't hold data, but when mem->next gets freed,
+     *       the 2 regions would be combined, resulting in more free memory */
+    ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize;
+    mem2 = (struct mem *)(void *)&ram[ptr2];
+    if (mem2 < lfree) {
+      lfree = mem2;
+    }
+    mem2->used = 0;
+    mem2->next = mem->next;
+    mem2->prev = ptr;
+    mem->next = ptr2;
+    if (mem2->next != MEM_SIZE_ALIGNED) {
+      ((struct mem *)(void *)&ram[mem2->next])->prev = ptr2;
+    }
+    MEM_STATS_DEC_USED(used, (size - newsize));
+    /* the original mem->next is used, so no need to plug holes! */
+  }
+  /* else {
+    next struct mem is used but size between mem and mem2 is not big enough
+    to create another struct mem
+    -> don't do anyhting. 
+    -> the remaining space stays unused since it is too small
+  } */
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+  mem_free_count = 1;
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+  LWIP_MEM_FREE_UNPROTECT();
+  return rmem;
+}
+
+/**
+ * Adam's mem_malloc() plus solution for bug #17922
+ * Allocate a block of memory with a minimum of 'size' bytes.
+ *
+ * @param size is the minimum size of the requested block in bytes.
+ * @return pointer to allocated memory or NULL if no free memory was found.
+ *
+ * Note that the returned value will always be aligned (as defined by MEM_ALIGNMENT).
+ */
+void *
+mem_malloc(mem_size_t size)
+{
+  mem_size_t ptr, ptr2;
+  struct mem *mem, *mem2;
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+  u8_t local_mem_free_count = 0;
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+  LWIP_MEM_ALLOC_DECL_PROTECT();
+
+  if (size == 0) {
+    return NULL;
+  }
+
+  /* Expand the size of the allocated memory region so that we can
+     adjust for alignment. */
+  size = LWIP_MEM_ALIGN_SIZE(size);
+
+  if(size < MIN_SIZE_ALIGNED) {
+    /* every data block must be at least MIN_SIZE_ALIGNED long */
+    size = MIN_SIZE_ALIGNED;
+  }
+
+  if (size > MEM_SIZE_ALIGNED) {
+    return NULL;
+  }
+
+  /* protect the heap from concurrent access */
+  sys_mutex_lock(&mem_mutex);
+  LWIP_MEM_ALLOC_PROTECT();
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+  /* run as long as a mem_free disturbed mem_malloc */
+  do {
+    local_mem_free_count = 0;
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+
+    /* Scan through the heap searching for a free block that is big enough,
+     * beginning with the lowest free block.
+     */
+    for (ptr = (mem_size_t)((u8_t *)lfree - ram); ptr < MEM_SIZE_ALIGNED - size;
+         ptr = ((struct mem *)(void *)&ram[ptr])->next) {
+      mem = (struct mem *)(void *)&ram[ptr];
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+      mem_free_count = 0;
+      LWIP_MEM_ALLOC_UNPROTECT();
+      /* allow mem_free to run */
+      LWIP_MEM_ALLOC_PROTECT();
+      if (mem_free_count != 0) {
+        local_mem_free_count = mem_free_count;
+      }
+      mem_free_count = 0;
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+
+      if ((!mem->used) &&
+          (mem->next - (ptr + SIZEOF_STRUCT_MEM)) >= size) {
+        /* mem is not used and at least perfect fit is possible:
+         * mem->next - (ptr + SIZEOF_STRUCT_MEM) gives us the 'user data size' of mem */
+
+        if (mem->next - (ptr + SIZEOF_STRUCT_MEM) >= (size + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED)) {
+          /* (in addition to the above, we test if another struct mem (SIZEOF_STRUCT_MEM) containing
+           * at least MIN_SIZE_ALIGNED of data also fits in the 'user data space' of 'mem')
+           * -> split large block, create empty remainder,
+           * remainder must be large enough to contain MIN_SIZE_ALIGNED data: if
+           * mem->next - (ptr + (2*SIZEOF_STRUCT_MEM)) == size,
+           * struct mem would fit in but no data between mem2 and mem2->next
+           * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty
+           *       region that couldn't hold data, but when mem->next gets freed,
+           *       the 2 regions would be combined, resulting in more free memory
+           */
+          ptr2 = ptr + SIZEOF_STRUCT_MEM + size;
+          /* create mem2 struct */
+          mem2 = (struct mem *)(void *)&ram[ptr2];
+          mem2->used = 0;
+          mem2->next = mem->next;
+          mem2->prev = ptr;
+          /* and insert it between mem and mem->next */
+          mem->next = ptr2;
+          mem->used = 1;
+
+          if (mem2->next != MEM_SIZE_ALIGNED) {
+            ((struct mem *)(void *)&ram[mem2->next])->prev = ptr2;
+          }
+          MEM_STATS_INC_USED(used, (size + SIZEOF_STRUCT_MEM));
+        } else {
+          /* (a mem2 struct does no fit into the user data space of mem and mem->next will always
+           * be used at this point: if not we have 2 unused structs in a row, plug_holes should have
+           * take care of this).
+           * -> near fit or excact fit: do not split, no mem2 creation
+           * also can't move mem->next directly behind mem, since mem->next
+           * will always be used at this point!
+           */
+          mem->used = 1;
+          MEM_STATS_INC_USED(used, mem->next - (mem_size_t)((u8_t *)mem - ram));
+        }
+
+        if (mem == lfree) {
+          /* Find next free block after mem and update lowest free pointer */
+          while (lfree->used && lfree != ram_end) {
+            LWIP_MEM_ALLOC_UNPROTECT();
+            /* prevent high interrupt latency... */
+            LWIP_MEM_ALLOC_PROTECT();
+            lfree = (struct mem *)(void *)&ram[lfree->next];
+          }
+          LWIP_ASSERT("mem_malloc: !lfree->used", ((lfree == ram_end) || (!lfree->used)));
+        }
+        LWIP_MEM_ALLOC_UNPROTECT();
+        sys_mutex_unlock(&mem_mutex);
+        LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.",
+         (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end);
+        LWIP_ASSERT("mem_malloc: allocated memory properly aligned.",
+         ((mem_ptr_t)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0);
+        LWIP_ASSERT("mem_malloc: sanity check alignment",
+          (((mem_ptr_t)mem) & (MEM_ALIGNMENT-1)) == 0);
+
+        return (u8_t *)mem + SIZEOF_STRUCT_MEM;
+      }
+    }
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+    /* if we got interrupted by a mem_free, try again */
+  } while(local_mem_free_count != 0);
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+  LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size));
+  MEM_STATS_INC(err);
+  LWIP_MEM_ALLOC_UNPROTECT();
+  sys_mutex_unlock(&mem_mutex);
+  return NULL;
+}
+
+#endif /* MEM_USE_POOLS */
+/**
+ * Contiguously allocates enough space for count objects that are size bytes
+ * of memory each and returns a pointer to the allocated memory.
+ *
+ * The allocated memory is filled with bytes of value zero.
+ *
+ * @param count number of objects to allocate
+ * @param size size of the objects to allocate
+ * @return pointer to allocated memory / NULL pointer if there is an error
+ */
+void *mem_calloc(mem_size_t count, mem_size_t size)
+{
+  void *p;
+
+  /* allocate 'count' objects of size 'size' */
+  p = mem_malloc(count * size);
+  if (p) {
+    /* zero the memory */
+    memset(p, 0, count * size);
+  }
+  return p;
+}
+
+#endif /* !MEM_LIBC_MALLOC */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/memp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/memp.c
new file mode 100644
index 0000000..4da879a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/memp.c
@@ -0,0 +1,469 @@
+/**
+ * @file
+ * Dynamic pool memory manager
+ *
+ * lwIP has dedicated pools for many structures (netconn, protocol control blocks,
+ * packet buffers, ...). All these pools are managed here.
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/memp.h"
+#include "lwip/pbuf.h"
+#include "lwip/udp.h"
+#include "lwip/raw.h"
+#include "lwip/tcp_impl.h"
+#include "lwip/igmp.h"
+#include "lwip/api.h"
+#include "lwip/api_msg.h"
+#include "lwip/tcpip.h"
+#include "lwip/sys.h"
+#include "lwip/timers.h"
+#include "lwip/stats.h"
+#include "netif/etharp.h"
+#include "lwip/ip_frag.h"
+#include "lwip/snmp_structs.h"
+#include "lwip/snmp_msg.h"
+#include "lwip/dns.h"
+#include "netif/ppp_oe.h"
+
+#include 
+
+#if !MEMP_MEM_MALLOC /* don't build if not configured for use in lwipopts.h */
+
+struct memp {
+  struct memp *next;
+#if MEMP_OVERFLOW_CHECK
+  const char *file;
+  int line;
+#endif /* MEMP_OVERFLOW_CHECK */
+};
+
+#if MEMP_OVERFLOW_CHECK
+/* if MEMP_OVERFLOW_CHECK is turned on, we reserve some bytes at the beginning
+ * and at the end of each element, initialize them as 0xcd and check
+ * them later. */
+/* If MEMP_OVERFLOW_CHECK is >= 2, on every call to memp_malloc or memp_free,
+ * every single element in each pool is checked!
+ * This is VERY SLOW but also very helpful. */
+/* MEMP_SANITY_REGION_BEFORE and MEMP_SANITY_REGION_AFTER can be overridden in
+ * lwipopts.h to change the amount reserved for checking. */
+#ifndef MEMP_SANITY_REGION_BEFORE
+#define MEMP_SANITY_REGION_BEFORE  16
+#endif /* MEMP_SANITY_REGION_BEFORE*/
+#if MEMP_SANITY_REGION_BEFORE > 0
+#define MEMP_SANITY_REGION_BEFORE_ALIGNED    LWIP_MEM_ALIGN_SIZE(MEMP_SANITY_REGION_BEFORE)
+#else
+#define MEMP_SANITY_REGION_BEFORE_ALIGNED    0
+#endif /* MEMP_SANITY_REGION_BEFORE*/
+#ifndef MEMP_SANITY_REGION_AFTER
+#define MEMP_SANITY_REGION_AFTER   16
+#endif /* MEMP_SANITY_REGION_AFTER*/
+#if MEMP_SANITY_REGION_AFTER > 0
+#define MEMP_SANITY_REGION_AFTER_ALIGNED     LWIP_MEM_ALIGN_SIZE(MEMP_SANITY_REGION_AFTER)
+#else
+#define MEMP_SANITY_REGION_AFTER_ALIGNED     0
+#endif /* MEMP_SANITY_REGION_AFTER*/
+
+/* MEMP_SIZE: save space for struct memp and for sanity check */
+#define MEMP_SIZE          (LWIP_MEM_ALIGN_SIZE(sizeof(struct memp)) + MEMP_SANITY_REGION_BEFORE_ALIGNED)
+#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x) + MEMP_SANITY_REGION_AFTER_ALIGNED)
+
+#else /* MEMP_OVERFLOW_CHECK */
+
+/* No sanity checks
+ * We don't need to preserve the struct memp while not allocated, so we
+ * can save a little space and set MEMP_SIZE to 0.
+ */
+#define MEMP_SIZE           0
+#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x))
+
+#endif /* MEMP_OVERFLOW_CHECK */
+
+/** This array holds the first free element of each pool.
+ *  Elements form a linked list. */
+static struct memp *memp_tab[MEMP_MAX];
+
+#else /* MEMP_MEM_MALLOC */
+
+#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x))
+
+#endif /* MEMP_MEM_MALLOC */
+
+/** This array holds the element sizes of each pool. */
+#if !MEM_USE_POOLS && !MEMP_MEM_MALLOC
+static
+#endif
+const u16_t memp_sizes[MEMP_MAX] = {
+#define LWIP_MEMPOOL(name,num,size,desc)  LWIP_MEM_ALIGN_SIZE(size),
+#include "lwip/memp_std.h"
+};
+
+#if !MEMP_MEM_MALLOC /* don't build if not configured for use in lwipopts.h */
+
+/** This array holds the number of elements in each pool. */
+static const u16_t memp_num[MEMP_MAX] = {
+#define LWIP_MEMPOOL(name,num,size,desc)  (num),
+#include "lwip/memp_std.h"
+};
+
+/** This array holds a textual description of each pool. */
+#ifdef LWIP_DEBUG
+static const char *memp_desc[MEMP_MAX] = {
+#define LWIP_MEMPOOL(name,num,size,desc)  (desc),
+#include "lwip/memp_std.h"
+};
+#endif /* LWIP_DEBUG */
+
+#if MEMP_SEPARATE_POOLS
+
+/** This creates each memory pool. These are named memp_memory_XXX_base (where
+ * XXX is the name of the pool defined in memp_std.h).
+ * To relocate a pool, declare it as extern in cc.h. Example for GCC:
+ *   extern u8_t __attribute__((section(".onchip_mem"))) memp_memory_UDP_PCB_base[];
+ */
+#define LWIP_MEMPOOL(name,num,size,desc) u8_t memp_memory_ ## name ## _base \
+  [((num) * (MEMP_SIZE + MEMP_ALIGN_SIZE(size)))];   
+#include "lwip/memp_std.h"
+
+/** This array holds the base of each memory pool. */
+static u8_t *const memp_bases[] = { 
+#define LWIP_MEMPOOL(name,num,size,desc) memp_memory_ ## name ## _base,   
+#include "lwip/memp_std.h"
+};
+
+#else /* MEMP_SEPARATE_POOLS */
+
+/** This is the actual memory used by the pools (all pools in one big block). */
+static u8_t memp_memory[MEM_ALIGNMENT - 1 
+#define LWIP_MEMPOOL(name,num,size,desc) + ( (num) * (MEMP_SIZE + MEMP_ALIGN_SIZE(size) ) )
+#include "lwip/memp_std.h"
+];
+
+#endif /* MEMP_SEPARATE_POOLS */
+
+#if MEMP_SANITY_CHECK
+/**
+ * Check that memp-lists don't form a circle
+ */
+static int
+memp_sanity(void)
+{
+  s16_t i, c;
+  struct memp *m, *n;
+
+  for (i = 0; i < MEMP_MAX; i++) {
+    for (m = memp_tab[i]; m != NULL; m = m->next) {
+      c = 1;
+      for (n = memp_tab[i]; n != NULL; n = n->next) {
+        if (n == m && --c < 0) {
+          return 0;
+        }
+      }
+    }
+  }
+  return 1;
+}
+#endif /* MEMP_SANITY_CHECK*/
+#if MEMP_OVERFLOW_CHECK
+#if defined(LWIP_DEBUG) && MEMP_STATS
+static const char * memp_overflow_names[] = {
+#define LWIP_MEMPOOL(name,num,size,desc) "/"desc,
+#include "lwip/memp_std.h"
+  };
+#endif
+
+/**
+ * Check if a memp element was victim of an overflow
+ * (e.g. the restricted area after it has been altered)
+ *
+ * @param p the memp element to check
+ * @param memp_type the pool p comes from
+ */
+static void
+memp_overflow_check_element_overflow(struct memp *p, u16_t memp_type)
+{
+  u16_t k;
+  u8_t *m;
+#if MEMP_SANITY_REGION_AFTER_ALIGNED > 0
+  m = (u8_t*)p + MEMP_SIZE + memp_sizes[memp_type];
+  for (k = 0; k < MEMP_SANITY_REGION_AFTER_ALIGNED; k++) {
+    if (m[k] != 0xcd) {
+      char errstr[128] = "detected memp overflow in pool ";
+      char digit[] = "0";
+      if(memp_type >= 10) {
+        digit[0] = '0' + (memp_type/10);
+        strcat(errstr, digit);
+      }
+      digit[0] = '0' + (memp_type%10);
+      strcat(errstr, digit);
+#if defined(LWIP_DEBUG) && MEMP_STATS
+      strcat(errstr, memp_overflow_names[memp_type]);
+#endif
+      LWIP_ASSERT(errstr, 0);
+    }
+  }
+#endif
+}
+
+/**
+ * Check if a memp element was victim of an underflow
+ * (e.g. the restricted area before it has been altered)
+ *
+ * @param p the memp element to check
+ * @param memp_type the pool p comes from
+ */
+static void
+memp_overflow_check_element_underflow(struct memp *p, u16_t memp_type)
+{
+  u16_t k;
+  u8_t *m;
+#if MEMP_SANITY_REGION_BEFORE_ALIGNED > 0
+  m = (u8_t*)p + MEMP_SIZE - MEMP_SANITY_REGION_BEFORE_ALIGNED;
+  for (k = 0; k < MEMP_SANITY_REGION_BEFORE_ALIGNED; k++) {
+    if (m[k] != 0xcd) {
+      char errstr[128] = "detected memp underflow in pool ";
+      char digit[] = "0";
+      if(memp_type >= 10) {
+        digit[0] = '0' + (memp_type/10);
+        strcat(errstr, digit);
+      }
+      digit[0] = '0' + (memp_type%10);
+      strcat(errstr, digit);
+#if defined(LWIP_DEBUG) && MEMP_STATS
+      strcat(errstr, memp_overflow_names[memp_type]);
+#endif
+      LWIP_ASSERT(errstr, 0);
+    }
+  }
+#endif
+}
+
+/**
+ * Do an overflow check for all elements in every pool.
+ *
+ * @see memp_overflow_check_element for a description of the check
+ */
+static void
+memp_overflow_check_all(void)
+{
+  u16_t i, j;
+  struct memp *p;
+
+  p = (struct memp *)LWIP_MEM_ALIGN(memp_memory);
+  for (i = 0; i < MEMP_MAX; ++i) {
+    p = p;
+    for (j = 0; j < memp_num[i]; ++j) {
+      memp_overflow_check_element_overflow(p, i);
+      p = (struct memp*)((u8_t*)p + MEMP_SIZE + memp_sizes[i] + MEMP_SANITY_REGION_AFTER_ALIGNED);
+    }
+  }
+  p = (struct memp *)LWIP_MEM_ALIGN(memp_memory);
+  for (i = 0; i < MEMP_MAX; ++i) {
+    p = p;
+    for (j = 0; j < memp_num[i]; ++j) {
+      memp_overflow_check_element_underflow(p, i);
+      p = (struct memp*)((u8_t*)p + MEMP_SIZE + memp_sizes[i] + MEMP_SANITY_REGION_AFTER_ALIGNED);
+    }
+  }
+}
+
+/**
+ * Initialize the restricted areas of all memp elements in every pool.
+ */
+static void
+memp_overflow_init(void)
+{
+  u16_t i, j;
+  struct memp *p;
+  u8_t *m;
+
+  p = (struct memp *)LWIP_MEM_ALIGN(memp_memory);
+  for (i = 0; i < MEMP_MAX; ++i) {
+    p = p;
+    for (j = 0; j < memp_num[i]; ++j) {
+#if MEMP_SANITY_REGION_BEFORE_ALIGNED > 0
+      m = (u8_t*)p + MEMP_SIZE - MEMP_SANITY_REGION_BEFORE_ALIGNED;
+      memset(m, 0xcd, MEMP_SANITY_REGION_BEFORE_ALIGNED);
+#endif
+#if MEMP_SANITY_REGION_AFTER_ALIGNED > 0
+      m = (u8_t*)p + MEMP_SIZE + memp_sizes[i];
+      memset(m, 0xcd, MEMP_SANITY_REGION_AFTER_ALIGNED);
+#endif
+      p = (struct memp*)((u8_t*)p + MEMP_SIZE + memp_sizes[i] + MEMP_SANITY_REGION_AFTER_ALIGNED);
+    }
+  }
+}
+#endif /* MEMP_OVERFLOW_CHECK */
+
+/**
+ * Initialize this module.
+ * 
+ * Carves out memp_memory into linked lists for each pool-type.
+ */
+void
+memp_init(void)
+{
+  struct memp *memp;
+  u16_t i, j;
+
+  for (i = 0; i < MEMP_MAX; ++i) {
+    MEMP_STATS_AVAIL(used, i, 0);
+    MEMP_STATS_AVAIL(max, i, 0);
+    MEMP_STATS_AVAIL(err, i, 0);
+    MEMP_STATS_AVAIL(avail, i, memp_num[i]);
+  }
+
+#if !MEMP_SEPARATE_POOLS
+  memp = (struct memp *)LWIP_MEM_ALIGN(memp_memory);
+#endif /* !MEMP_SEPARATE_POOLS */
+  /* for every pool: */
+  for (i = 0; i < MEMP_MAX; ++i) {
+    memp_tab[i] = NULL;
+#if MEMP_SEPARATE_POOLS
+    memp = (struct memp*)memp_bases[i];
+#endif /* MEMP_SEPARATE_POOLS */
+    /* create a linked list of memp elements */
+    for (j = 0; j < memp_num[i]; ++j) {
+      memp->next = memp_tab[i];
+      memp_tab[i] = memp;
+      memp = (struct memp *)(void *)((u8_t *)memp + MEMP_SIZE + memp_sizes[i]
+#if MEMP_OVERFLOW_CHECK
+        + MEMP_SANITY_REGION_AFTER_ALIGNED
+#endif
+      );
+    }
+  }
+#if MEMP_OVERFLOW_CHECK
+  memp_overflow_init();
+  /* check everything a first time to see if it worked */
+  memp_overflow_check_all();
+#endif /* MEMP_OVERFLOW_CHECK */
+}
+
+/**
+ * Get an element from a specific pool.
+ *
+ * @param type the pool to get an element from
+ *
+ * the debug version has two more parameters:
+ * @param file file name calling this function
+ * @param line number of line where this function is called
+ *
+ * @return a pointer to the allocated memory or a NULL pointer on error
+ */
+void *
+#if !MEMP_OVERFLOW_CHECK
+memp_malloc(memp_t type)
+#else
+memp_malloc_fn(memp_t type, const char* file, const int line)
+#endif
+{
+  struct memp *memp;
+  SYS_ARCH_DECL_PROTECT(old_level);
+ 
+  LWIP_ERROR("memp_malloc: type < MEMP_MAX", (type < MEMP_MAX), return NULL;);
+
+  SYS_ARCH_PROTECT(old_level);
+#if MEMP_OVERFLOW_CHECK >= 2
+  memp_overflow_check_all();
+#endif /* MEMP_OVERFLOW_CHECK >= 2 */
+
+  memp = memp_tab[type];
+  
+  if (memp != NULL) {
+    memp_tab[type] = memp->next;
+#if MEMP_OVERFLOW_CHECK
+    memp->next = NULL;
+    memp->file = file;
+    memp->line = line;
+#endif /* MEMP_OVERFLOW_CHECK */
+    MEMP_STATS_INC_USED(used, type);
+    LWIP_ASSERT("memp_malloc: memp properly aligned",
+                ((mem_ptr_t)memp % MEM_ALIGNMENT) == 0);
+    memp = (struct memp*)(void *)((u8_t*)memp + MEMP_SIZE);
+  } else {
+    LWIP_DEBUGF(MEMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("memp_malloc: out of memory in pool %s\n", memp_desc[type]));
+    MEMP_STATS_INC(err, type);
+  }
+
+  SYS_ARCH_UNPROTECT(old_level);
+
+  return memp;
+}
+
+/**
+ * Put an element back into its pool.
+ *
+ * @param type the pool where to put mem
+ * @param mem the memp element to free
+ */
+void
+memp_free(memp_t type, void *mem)
+{
+  struct memp *memp;
+  SYS_ARCH_DECL_PROTECT(old_level);
+
+  if (mem == NULL) {
+    return;
+  }
+  LWIP_ASSERT("memp_free: mem properly aligned",
+                ((mem_ptr_t)mem % MEM_ALIGNMENT) == 0);
+
+  memp = (struct memp *)(void *)((u8_t*)mem - MEMP_SIZE);
+
+  SYS_ARCH_PROTECT(old_level);
+#if MEMP_OVERFLOW_CHECK
+#if MEMP_OVERFLOW_CHECK >= 2
+  memp_overflow_check_all();
+#else
+  memp_overflow_check_element_overflow(memp, type);
+  memp_overflow_check_element_underflow(memp, type);
+#endif /* MEMP_OVERFLOW_CHECK >= 2 */
+#endif /* MEMP_OVERFLOW_CHECK */
+
+  MEMP_STATS_DEC(used, type); 
+  
+  memp->next = memp_tab[type]; 
+  memp_tab[type] = memp;
+
+#if MEMP_SANITY_CHECK
+  LWIP_ASSERT("memp sanity", memp_sanity());
+#endif /* MEMP_SANITY_CHECK */
+
+  SYS_ARCH_UNPROTECT(old_level);
+}
+
+#endif /* MEMP_MEM_MALLOC */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/netif.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/netif.c
new file mode 100644
index 0000000..f190b1f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/netif.c
@@ -0,0 +1,752 @@
+/**
+ * @file
+ * lwIP network interface abstraction
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/tcp_impl.h"
+#include "lwip/snmp.h"
+#include "lwip/igmp.h"
+#include "netif/etharp.h"
+#include "lwip/stats.h"
+#if ENABLE_LOOPBACK
+#include "lwip/sys.h"
+#if LWIP_NETIF_LOOPBACK_MULTITHREADING
+#include "lwip/tcpip.h"
+#endif /* LWIP_NETIF_LOOPBACK_MULTITHREADING */
+#endif /* ENABLE_LOOPBACK */
+
+#if LWIP_AUTOIP
+#include "lwip/autoip.h"
+#endif /* LWIP_AUTOIP */
+#if LWIP_DHCP
+#include "lwip/dhcp.h"
+#endif /* LWIP_DHCP */
+
+#if LWIP_NETIF_STATUS_CALLBACK
+#define NETIF_STATUS_CALLBACK(n) do{ if (n->status_callback) { (n->status_callback)(n); }}while(0)
+#else
+#define NETIF_STATUS_CALLBACK(n)
+#endif /* LWIP_NETIF_STATUS_CALLBACK */ 
+
+#if LWIP_NETIF_LINK_CALLBACK
+#define NETIF_LINK_CALLBACK(n) do{ if (n->link_callback) { (n->link_callback)(n); }}while(0)
+#else
+#define NETIF_LINK_CALLBACK(n)
+#endif /* LWIP_NETIF_LINK_CALLBACK */ 
+
+struct netif *netif_list;
+struct netif *netif_default;
+
+#if LWIP_HAVE_LOOPIF
+static struct netif loop_netif;
+
+/**
+ * Initialize a lwip network interface structure for a loopback interface
+ *
+ * @param netif the lwip network interface structure for this loopif
+ * @return ERR_OK if the loopif is initialized
+ *         ERR_MEM if private data couldn't be allocated
+ */
+static err_t
+netif_loopif_init(struct netif *netif)
+{
+  /* initialize the snmp variables and counters inside the struct netif
+   * ifSpeed: no assumption can be made!
+   */
+  NETIF_INIT_SNMP(netif, snmp_ifType_softwareLoopback, 0);
+
+  netif->name[0] = 'l';
+  netif->name[1] = 'o';
+  netif->output = netif_loop_output;
+  return ERR_OK;
+}
+#endif /* LWIP_HAVE_LOOPIF */
+
+void
+netif_init(void)
+{
+#if LWIP_HAVE_LOOPIF
+  ip_addr_t loop_ipaddr, loop_netmask, loop_gw;
+  IP4_ADDR(&loop_gw, 127,0,0,1);
+  IP4_ADDR(&loop_ipaddr, 127,0,0,1);
+  IP4_ADDR(&loop_netmask, 255,0,0,0);
+
+#if NO_SYS
+  netif_add(&loop_netif, &loop_ipaddr, &loop_netmask, &loop_gw, NULL, netif_loopif_init, ip_input);
+#else  /* NO_SYS */
+  netif_add(&loop_netif, &loop_ipaddr, &loop_netmask, &loop_gw, NULL, netif_loopif_init, tcpip_input);
+#endif /* NO_SYS */
+  netif_set_up(&loop_netif);
+
+#endif /* LWIP_HAVE_LOOPIF */
+}
+
+/**
+ * Add a network interface to the list of lwIP netifs.
+ *
+ * @param netif a pre-allocated netif structure
+ * @param ipaddr IP address for the new netif
+ * @param netmask network mask for the new netif
+ * @param gw default gateway IP address for the new netif
+ * @param state opaque data passed to the new netif
+ * @param init callback function that initializes the interface
+ * @param input callback function that is called to pass
+ * ingress packets up in the protocol layer stack.
+ *
+ * @return netif, or NULL if failed.
+ */
+struct netif *
+netif_add(struct netif *netif, ip_addr_t *ipaddr, ip_addr_t *netmask,
+  ip_addr_t *gw, void *state, netif_init_fn init, netif_input_fn input)
+{
+  static u8_t netifnum = 0;
+
+  LWIP_ASSERT("No init function given", init != NULL);
+
+  /* reset new interface configuration state */
+  ip_addr_set_zero(&netif->ip_addr);
+  ip_addr_set_zero(&netif->netmask);
+  ip_addr_set_zero(&netif->gw);
+  netif->flags = 0;
+#if LWIP_DHCP
+  /* netif not under DHCP control by default */
+  netif->dhcp = NULL;
+#endif /* LWIP_DHCP */
+#if LWIP_AUTOIP
+  /* netif not under AutoIP control by default */
+  netif->autoip = NULL;
+#endif /* LWIP_AUTOIP */
+#if LWIP_NETIF_STATUS_CALLBACK
+  netif->status_callback = NULL;
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+#if LWIP_NETIF_LINK_CALLBACK
+  netif->link_callback = NULL;
+#endif /* LWIP_NETIF_LINK_CALLBACK */
+#if LWIP_IGMP
+  netif->igmp_mac_filter = NULL;
+#endif /* LWIP_IGMP */
+#if ENABLE_LOOPBACK
+  netif->loop_first = NULL;
+  netif->loop_last = NULL;
+#endif /* ENABLE_LOOPBACK */
+
+  /* remember netif specific state information data */
+  netif->state = state;
+  netif->num = netifnum++;
+  netif->input = input;
+#if LWIP_NETIF_HWADDRHINT
+  netif->addr_hint = NULL;
+#endif /* LWIP_NETIF_HWADDRHINT*/
+#if ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS
+  netif->loop_cnt_current = 0;
+#endif /* ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS */
+
+  netif_set_addr(netif, ipaddr, netmask, gw);
+
+  /* call user specified initialization function for netif */
+  if (init(netif) != ERR_OK) {
+    return NULL;
+  }
+
+  /* add this netif to the list */
+  netif->next = netif_list;
+  netif_list = netif;
+  snmp_inc_iflist();
+
+#if LWIP_IGMP
+  /* start IGMP processing */
+  if (netif->flags & NETIF_FLAG_IGMP) {
+    igmp_start(netif);
+  }
+#endif /* LWIP_IGMP */
+
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP addr ",
+    netif->name[0], netif->name[1]));
+  ip_addr_debug_print(NETIF_DEBUG, ipaddr);
+  LWIP_DEBUGF(NETIF_DEBUG, (" netmask "));
+  ip_addr_debug_print(NETIF_DEBUG, netmask);
+  LWIP_DEBUGF(NETIF_DEBUG, (" gw "));
+  ip_addr_debug_print(NETIF_DEBUG, gw);
+  LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
+  return netif;
+}
+
+/**
+ * Change IP address configuration for a network interface (including netmask
+ * and default gateway).
+ *
+ * @param netif the network interface to change
+ * @param ipaddr the new IP address
+ * @param netmask the new netmask
+ * @param gw the new default gateway
+ */
+void
+netif_set_addr(struct netif *netif, ip_addr_t *ipaddr, ip_addr_t *netmask,
+    ip_addr_t *gw)
+{
+  netif_set_ipaddr(netif, ipaddr);
+  netif_set_netmask(netif, netmask);
+  netif_set_gw(netif, gw);
+}
+
+/**
+ * Remove a network interface from the list of lwIP netifs.
+ *
+ * @param netif the network interface to remove
+ */
+void
+netif_remove(struct netif *netif)
+{
+  if (netif == NULL) {
+    return;
+  }
+
+#if LWIP_IGMP
+  /* stop IGMP processing */
+  if (netif->flags & NETIF_FLAG_IGMP) {
+    igmp_stop(netif);
+  }
+#endif /* LWIP_IGMP */
+  if (netif_is_up(netif)) {
+    /* set netif down before removing (call callback function) */
+    netif_set_down(netif);
+  }
+
+  snmp_delete_ipaddridx_tree(netif);
+
+  /*  is it the first netif? */
+  if (netif_list == netif) {
+    netif_list = netif->next;
+  } else {
+    /*  look for netif further down the list */
+    struct netif * tmpNetif;
+    for (tmpNetif = netif_list; tmpNetif != NULL; tmpNetif = tmpNetif->next) {
+      if (tmpNetif->next == netif) {
+        tmpNetif->next = netif->next;
+        break;
+      }
+    }
+    if (tmpNetif == NULL)
+      return; /*  we didn't find any netif today */
+  }
+  snmp_dec_iflist();
+  /* this netif is default? */
+  if (netif_default == netif) {
+    /* reset default netif */
+    netif_set_default(NULL);
+  }
+  LWIP_DEBUGF( NETIF_DEBUG, ("netif_remove: removed netif\n") );
+}
+
+/**
+ * Find a network interface by searching for its name
+ *
+ * @param name the name of the netif (like netif->name) plus concatenated number
+ * in ascii representation (e.g. 'en0')
+ */
+struct netif *
+netif_find(char *name)
+{
+  struct netif *netif;
+  u8_t num;
+
+  if (name == NULL) {
+    return NULL;
+  }
+
+  num = name[2] - '0';
+
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+    if (num == netif->num &&
+       name[0] == netif->name[0] &&
+       name[1] == netif->name[1]) {
+      LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: found %c%c\n", name[0], name[1]));
+      return netif;
+    }
+  }
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: didn't find %c%c\n", name[0], name[1]));
+  return NULL;
+}
+
+/**
+ * Change the IP address of a network interface
+ *
+ * @param netif the network interface to change
+ * @param ipaddr the new IP address
+ *
+ * @note call netif_set_addr() if you also want to change netmask and
+ * default gateway
+ */
+void
+netif_set_ipaddr(struct netif *netif, ip_addr_t *ipaddr)
+{
+  /* TODO: Handling of obsolete pcbs */
+  /* See:  http://mail.gnu.org/archive/html/lwip-users/2003-03/msg00118.html */
+#if LWIP_TCP
+  struct tcp_pcb *pcb;
+  struct tcp_pcb_listen *lpcb;
+
+  /* address is actually being changed? */
+  if ((ip_addr_cmp(ipaddr, &(netif->ip_addr))) == 0) {
+    /* extern struct tcp_pcb *tcp_active_pcbs; defined by tcp.h */
+    LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: netif address being changed\n"));
+    pcb = tcp_active_pcbs;
+    while (pcb != NULL) {
+      /* PCB bound to current local interface address? */
+      if (ip_addr_cmp(&(pcb->local_ip), &(netif->ip_addr))
+#if LWIP_AUTOIP
+        /* connections to link-local addresses must persist (RFC3927 ch. 1.9) */
+        && !ip_addr_islinklocal(&(pcb->local_ip))
+#endif /* LWIP_AUTOIP */
+        ) {
+        /* this connection must be aborted */
+        struct tcp_pcb *next = pcb->next;
+        LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb));
+        tcp_abort(pcb);
+        pcb = next;
+      } else {
+        pcb = pcb->next;
+      }
+    }
+    for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+      /* PCB bound to current local interface address? */
+      if ((!(ip_addr_isany(&(lpcb->local_ip)))) &&
+          (ip_addr_cmp(&(lpcb->local_ip), &(netif->ip_addr)))) {
+        /* The PCB is listening to the old ipaddr and
+         * is set to listen to the new one instead */
+        ip_addr_set(&(lpcb->local_ip), ipaddr);
+      }
+    }
+  }
+#endif
+  snmp_delete_ipaddridx_tree(netif);
+  snmp_delete_iprteidx_tree(0,netif);
+  /* set new IP address to netif */
+  ip_addr_set(&(netif->ip_addr), ipaddr);
+  snmp_insert_ipaddridx_tree(netif);
+  snmp_insert_iprteidx_tree(0,netif);
+
+  LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: IP address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+    netif->name[0], netif->name[1],
+    ip4_addr1_16(&netif->ip_addr),
+    ip4_addr2_16(&netif->ip_addr),
+    ip4_addr3_16(&netif->ip_addr),
+    ip4_addr4_16(&netif->ip_addr)));
+}
+
+/**
+ * Change the default gateway for a network interface
+ *
+ * @param netif the network interface to change
+ * @param gw the new default gateway
+ *
+ * @note call netif_set_addr() if you also want to change ip address and netmask
+ */
+void
+netif_set_gw(struct netif *netif, ip_addr_t *gw)
+{
+  ip_addr_set(&(netif->gw), gw);
+  LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: GW address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+    netif->name[0], netif->name[1],
+    ip4_addr1_16(&netif->gw),
+    ip4_addr2_16(&netif->gw),
+    ip4_addr3_16(&netif->gw),
+    ip4_addr4_16(&netif->gw)));
+}
+
+/**
+ * Change the netmask of a network interface
+ *
+ * @param netif the network interface to change
+ * @param netmask the new netmask
+ *
+ * @note call netif_set_addr() if you also want to change ip address and
+ * default gateway
+ */
+void
+netif_set_netmask(struct netif *netif, ip_addr_t *netmask)
+{
+  snmp_delete_iprteidx_tree(0, netif);
+  /* set new netmask to netif */
+  ip_addr_set(&(netif->netmask), netmask);
+  snmp_insert_iprteidx_tree(0, netif);
+  LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: netmask of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+    netif->name[0], netif->name[1],
+    ip4_addr1_16(&netif->netmask),
+    ip4_addr2_16(&netif->netmask),
+    ip4_addr3_16(&netif->netmask),
+    ip4_addr4_16(&netif->netmask)));
+}
+
+/**
+ * Set a network interface as the default network interface
+ * (used to output all packets for which no specific route is found)
+ *
+ * @param netif the default network interface
+ */
+void
+netif_set_default(struct netif *netif)
+{
+  if (netif == NULL) {
+    /* remove default route */
+    snmp_delete_iprteidx_tree(1, netif);
+  } else {
+    /* install default route */
+    snmp_insert_iprteidx_tree(1, netif);
+  }
+  netif_default = netif;
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n",
+           netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\''));
+}
+
+/**
+ * Bring an interface up, available for processing
+ * traffic.
+ * 
+ * @note: Enabling DHCP on a down interface will make it come
+ * up once configured.
+ * 
+ * @see dhcp_start()
+ */ 
+void netif_set_up(struct netif *netif)
+{
+  if (!(netif->flags & NETIF_FLAG_UP)) {
+    netif->flags |= NETIF_FLAG_UP;
+    
+#if LWIP_SNMP
+    snmp_get_sysuptime(&netif->ts);
+#endif /* LWIP_SNMP */
+
+    NETIF_STATUS_CALLBACK(netif);
+
+    if (netif->flags & NETIF_FLAG_LINK_UP) {
+#if LWIP_ARP
+      /* For Ethernet network interfaces, we would like to send a "gratuitous ARP" */ 
+      if (netif->flags & (NETIF_FLAG_ETHARP)) {
+        etharp_gratuitous(netif);
+      }
+#endif /* LWIP_ARP */
+
+#if LWIP_IGMP
+      /* resend IGMP memberships */
+      if (netif->flags & NETIF_FLAG_IGMP) {
+        igmp_report_groups( netif);
+      }
+#endif /* LWIP_IGMP */
+    }
+  }
+}
+
+/**
+ * Bring an interface down, disabling any traffic processing.
+ *
+ * @note: Enabling DHCP on a down interface will make it come
+ * up once configured.
+ * 
+ * @see dhcp_start()
+ */ 
+void netif_set_down(struct netif *netif)
+{
+  if (netif->flags & NETIF_FLAG_UP) {
+    netif->flags &= ~NETIF_FLAG_UP;
+#if LWIP_SNMP
+    snmp_get_sysuptime(&netif->ts);
+#endif
+
+    NETIF_STATUS_CALLBACK(netif);
+  }
+}
+
+#if LWIP_NETIF_STATUS_CALLBACK
+/**
+ * Set callback to be called when interface is brought up/down
+ */
+void netif_set_status_callback(struct netif *netif, netif_status_callback_fn status_callback)
+{
+  if (netif) {
+    netif->status_callback = status_callback;
+  }
+}
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+
+/**
+ * Called by a driver when its link goes up
+ */
+void netif_set_link_up(struct netif *netif )
+{
+  if (!(netif->flags & NETIF_FLAG_LINK_UP)) {
+    netif->flags |= NETIF_FLAG_LINK_UP;
+
+#if LWIP_DHCP
+    if (netif->dhcp) {
+      dhcp_network_changed(netif);
+    }
+#endif /* LWIP_DHCP */
+
+#if LWIP_AUTOIP
+    if (netif->autoip) {
+      autoip_network_changed(netif);
+    }
+#endif /* LWIP_AUTOIP */
+
+    if (netif->flags & NETIF_FLAG_UP) {
+#if LWIP_ARP
+      /* For Ethernet network interfaces, we would like to send a "gratuitous ARP" */ 
+      if (netif->flags & NETIF_FLAG_ETHARP) {
+        etharp_gratuitous(netif);
+      }
+#endif /* LWIP_ARP */
+
+#if LWIP_IGMP
+      /* resend IGMP memberships */
+      if (netif->flags & NETIF_FLAG_IGMP) {
+        igmp_report_groups( netif);
+      }
+#endif /* LWIP_IGMP */
+    }
+    NETIF_LINK_CALLBACK(netif);
+  }
+}
+
+/**
+ * Called by a driver when its link goes down
+ */
+void netif_set_link_down(struct netif *netif )
+{
+  if (netif->flags & NETIF_FLAG_LINK_UP) {
+    netif->flags &= ~NETIF_FLAG_LINK_UP;
+    NETIF_LINK_CALLBACK(netif);
+  }
+}
+
+#if LWIP_NETIF_LINK_CALLBACK
+/**
+ * Set callback to be called when link is brought up/down
+ */
+void netif_set_link_callback(struct netif *netif, netif_status_callback_fn link_callback)
+{
+  if (netif) {
+    netif->link_callback = link_callback;
+  }
+}
+#endif /* LWIP_NETIF_LINK_CALLBACK */
+
+#if ENABLE_LOOPBACK
+/**
+ * Send an IP packet to be received on the same netif (loopif-like).
+ * The pbuf is simply copied and handed back to netif->input.
+ * In multithreaded mode, this is done directly since netif->input must put
+ * the packet on a queue.
+ * In callback mode, the packet is put on an internal queue and is fed to
+ * netif->input by netif_poll().
+ *
+ * @param netif the lwip network interface structure
+ * @param p the (IP) packet to 'send'
+ * @param ipaddr the ip address to send the packet to (not used)
+ * @return ERR_OK if the packet has been sent
+ *         ERR_MEM if the pbuf used to copy the packet couldn't be allocated
+ */
+err_t
+netif_loop_output(struct netif *netif, struct pbuf *p,
+       ip_addr_t *ipaddr)
+{
+  struct pbuf *r;
+  err_t err;
+  struct pbuf *last;
+#if LWIP_LOOPBACK_MAX_PBUFS
+  u8_t clen = 0;
+#endif /* LWIP_LOOPBACK_MAX_PBUFS */
+  /* If we have a loopif, SNMP counters are adjusted for it,
+   * if not they are adjusted for 'netif'. */
+#if LWIP_SNMP
+#if LWIP_HAVE_LOOPIF
+  struct netif *stats_if = &loop_netif;
+#else /* LWIP_HAVE_LOOPIF */
+  struct netif *stats_if = netif;
+#endif /* LWIP_HAVE_LOOPIF */
+#endif /* LWIP_SNMP */
+  SYS_ARCH_DECL_PROTECT(lev);
+  LWIP_UNUSED_ARG(ipaddr);
+
+  /* Allocate a new pbuf */
+  r = pbuf_alloc(PBUF_LINK, p->tot_len, PBUF_RAM);
+  if (r == NULL) {
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.drop);
+    snmp_inc_ifoutdiscards(stats_if);
+    return ERR_MEM;
+  }
+#if LWIP_LOOPBACK_MAX_PBUFS
+  clen = pbuf_clen(r);
+  /* check for overflow or too many pbuf on queue */
+  if(((netif->loop_cnt_current + clen) < netif->loop_cnt_current) ||
+     ((netif->loop_cnt_current + clen) > LWIP_LOOPBACK_MAX_PBUFS)) {
+    pbuf_free(r);
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.drop);
+    snmp_inc_ifoutdiscards(stats_if);
+    return ERR_MEM;
+  }
+  netif->loop_cnt_current += clen;
+#endif /* LWIP_LOOPBACK_MAX_PBUFS */
+
+  /* Copy the whole pbuf queue p into the single pbuf r */
+  if ((err = pbuf_copy(r, p)) != ERR_OK) {
+    pbuf_free(r);
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.drop);
+    snmp_inc_ifoutdiscards(stats_if);
+    return err;
+  }
+
+  /* Put the packet on a linked list which gets emptied through calling
+     netif_poll(). */
+
+  /* let last point to the last pbuf in chain r */
+  for (last = r; last->next != NULL; last = last->next);
+
+  SYS_ARCH_PROTECT(lev);
+  if(netif->loop_first != NULL) {
+    LWIP_ASSERT("if first != NULL, last must also be != NULL", netif->loop_last != NULL);
+    netif->loop_last->next = r;
+    netif->loop_last = last;
+  } else {
+    netif->loop_first = r;
+    netif->loop_last = last;
+  }
+  SYS_ARCH_UNPROTECT(lev);
+
+  LINK_STATS_INC(link.xmit);
+  snmp_add_ifoutoctets(stats_if, p->tot_len);
+  snmp_inc_ifoutucastpkts(stats_if);
+
+#if LWIP_NETIF_LOOPBACK_MULTITHREADING
+  /* For multithreading environment, schedule a call to netif_poll */
+  tcpip_callback((tcpip_callback_fn)netif_poll, netif);
+#endif /* LWIP_NETIF_LOOPBACK_MULTITHREADING */
+
+  return ERR_OK;
+}
+
+/**
+ * Call netif_poll() in the main loop of your application. This is to prevent
+ * reentering non-reentrant functions like tcp_input(). Packets passed to
+ * netif_loop_output() are put on a list that is passed to netif->input() by
+ * netif_poll().
+ */
+void
+netif_poll(struct netif *netif)
+{
+  struct pbuf *in;
+  /* If we have a loopif, SNMP counters are adjusted for it,
+   * if not they are adjusted for 'netif'. */
+#if LWIP_SNMP
+#if LWIP_HAVE_LOOPIF
+  struct netif *stats_if = &loop_netif;
+#else /* LWIP_HAVE_LOOPIF */
+  struct netif *stats_if = netif;
+#endif /* LWIP_HAVE_LOOPIF */
+#endif /* LWIP_SNMP */
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  do {
+    /* Get a packet from the list. With SYS_LIGHTWEIGHT_PROT=1, this is protected */
+    SYS_ARCH_PROTECT(lev);
+    in = netif->loop_first;
+    if (in != NULL) {
+      struct pbuf *in_end = in;
+#if LWIP_LOOPBACK_MAX_PBUFS
+      u8_t clen = pbuf_clen(in);
+      /* adjust the number of pbufs on queue */
+      LWIP_ASSERT("netif->loop_cnt_current underflow",
+        ((netif->loop_cnt_current - clen) < netif->loop_cnt_current));
+      netif->loop_cnt_current -= clen;
+#endif /* LWIP_LOOPBACK_MAX_PBUFS */
+      while (in_end->len != in_end->tot_len) {
+        LWIP_ASSERT("bogus pbuf: len != tot_len but next == NULL!", in_end->next != NULL);
+        in_end = in_end->next;
+      }
+      /* 'in_end' now points to the last pbuf from 'in' */
+      if (in_end == netif->loop_last) {
+        /* this was the last pbuf in the list */
+        netif->loop_first = netif->loop_last = NULL;
+      } else {
+        /* pop the pbuf off the list */
+        netif->loop_first = in_end->next;
+        LWIP_ASSERT("should not be null since first != last!", netif->loop_first != NULL);
+      }
+      /* De-queue the pbuf from its successors on the 'loop_' list. */
+      in_end->next = NULL;
+    }
+    SYS_ARCH_UNPROTECT(lev);
+
+    if (in != NULL) {
+      LINK_STATS_INC(link.recv);
+      snmp_add_ifinoctets(stats_if, in->tot_len);
+      snmp_inc_ifinucastpkts(stats_if);
+      /* loopback packets are always IP packets! */
+      if (ip_input(in, netif) != ERR_OK) {
+        pbuf_free(in);
+      }
+      /* Don't reference the packet any more! */
+      in = NULL;
+    }
+  /* go on while there is a packet on the list */
+  } while (netif->loop_first != NULL);
+}
+
+#if !LWIP_NETIF_LOOPBACK_MULTITHREADING
+/**
+ * Calls netif_poll() for every netif on the netif_list.
+ */
+void
+netif_poll_all(void)
+{
+  struct netif *netif = netif_list;
+  /* loop through netifs */
+  while (netif != NULL) {
+    netif_poll(netif);
+    /* proceed to next network interface */
+    netif = netif->next;
+  }
+}
+#endif /* !LWIP_NETIF_LOOPBACK_MULTITHREADING */
+#endif /* ENABLE_LOOPBACK */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/pbuf.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/pbuf.c
new file mode 100644
index 0000000..dd9ff64
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/pbuf.c
@@ -0,0 +1,1156 @@
+/**
+ * @file
+ * Packet buffer management
+ *
+ * Packets are built from the pbuf data structure. It supports dynamic
+ * memory allocation for packet contents or can reference externally
+ * managed packet contents both in RAM and ROM. Quick allocation for
+ * incoming packets is provided through pools with fixed sized pbufs.
+ *
+ * A packet may span over multiple pbufs, chained as a singly linked
+ * list. This is called a "pbuf chain".
+ *
+ * Multiple packets may be queued, also using this singly linked list.
+ * This is called a "packet queue".
+ * 
+ * So, a packet queue consists of one or more pbuf chains, each of
+ * which consist of one or more pbufs. CURRENTLY, PACKET QUEUES ARE
+ * NOT SUPPORTED!!! Use helper structs to queue multiple packets.
+ * 
+ * The differences between a pbuf chain and a packet queue are very
+ * precise but subtle. 
+ *
+ * The last pbuf of a packet has a ->tot_len field that equals the
+ * ->len field. It can be found by traversing the list. If the last
+ * pbuf of a packet has a ->next field other than NULL, more packets
+ * are on the queue.
+ *
+ * Therefore, looping through a pbuf of a single packet, has an
+ * loop end condition (tot_len == p->len), NOT (next == NULL).
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/stats.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include "arch/perf.h"
+#if TCP_QUEUE_OOSEQ
+#include "lwip/tcp_impl.h"
+#endif
+#if LWIP_CHECKSUM_ON_COPY
+#include "lwip/inet_chksum.h"
+#endif
+
+#include 
+
+#define SIZEOF_STRUCT_PBUF        LWIP_MEM_ALIGN_SIZE(sizeof(struct pbuf))
+/* Since the pool is created in memp, PBUF_POOL_BUFSIZE will be automatically
+   aligned there. Therefore, PBUF_POOL_BUFSIZE_ALIGNED can be used here. */
+#define PBUF_POOL_BUFSIZE_ALIGNED LWIP_MEM_ALIGN_SIZE(PBUF_POOL_BUFSIZE)
+
+#if !LWIP_TCP || !TCP_QUEUE_OOSEQ || NO_SYS
+#define PBUF_POOL_IS_EMPTY()
+#else /* !LWIP_TCP || !TCP_QUEUE_OOSEQ || NO_SYS */
+/** Define this to 0 to prevent freeing ooseq pbufs when the PBUF_POOL is empty */
+#ifndef PBUF_POOL_FREE_OOSEQ
+#define PBUF_POOL_FREE_OOSEQ 1
+#endif /* PBUF_POOL_FREE_OOSEQ */
+
+#if PBUF_POOL_FREE_OOSEQ
+#include "lwip/tcpip.h"
+#define PBUF_POOL_IS_EMPTY() pbuf_pool_is_empty()
+static u8_t pbuf_free_ooseq_queued;
+/**
+ * Attempt to reclaim some memory from queued out-of-sequence TCP segments
+ * if we run out of pool pbufs. It's better to give priority to new packets
+ * if we're running out.
+ *
+ * This must be done in the correct thread context therefore this function
+ * can only be used with NO_SYS=0 and through tcpip_callback.
+ */
+static void
+pbuf_free_ooseq(void* arg)
+{
+  struct tcp_pcb* pcb;
+  SYS_ARCH_DECL_PROTECT(old_level);
+  LWIP_UNUSED_ARG(arg);
+
+  SYS_ARCH_PROTECT(old_level);
+  pbuf_free_ooseq_queued = 0;
+  SYS_ARCH_UNPROTECT(old_level);
+
+  for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) {
+    if (NULL != pcb->ooseq) {
+      /** Free the ooseq pbufs of one PCB only */
+      LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free_ooseq: freeing out-of-sequence pbufs\n"));
+      tcp_segs_free(pcb->ooseq);
+      pcb->ooseq = NULL;
+      return;
+    }
+  }
+}
+
+/** Queue a call to pbuf_free_ooseq if not already queued. */
+static void
+pbuf_pool_is_empty(void)
+{
+  u8_t queued;
+  SYS_ARCH_DECL_PROTECT(old_level);
+
+  SYS_ARCH_PROTECT(old_level);
+  queued = pbuf_free_ooseq_queued;
+  pbuf_free_ooseq_queued = 1;
+  SYS_ARCH_UNPROTECT(old_level);
+
+  if(!queued) {
+    /* queue a call to pbuf_free_ooseq if not already queued */
+    if(tcpip_callback_with_block(pbuf_free_ooseq, NULL, 0) != ERR_OK) {
+      SYS_ARCH_PROTECT(old_level);
+      pbuf_free_ooseq_queued = 0;
+      SYS_ARCH_UNPROTECT(old_level);
+    }
+  }
+}
+#endif /* PBUF_POOL_FREE_OOSEQ */
+#endif /* !LWIP_TCP || !TCP_QUEUE_OOSEQ || NO_SYS */
+
+/**
+ * Allocates a pbuf of the given type (possibly a chain for PBUF_POOL type).
+ *
+ * The actual memory allocated for the pbuf is determined by the
+ * layer at which the pbuf is allocated and the requested size
+ * (from the size parameter).
+ *
+ * @param layer flag to define header size
+ * @param length size of the pbuf's payload
+ * @param type this parameter decides how and where the pbuf
+ * should be allocated as follows:
+ *
+ * - PBUF_RAM: buffer memory for pbuf is allocated as one large
+ *             chunk. This includes protocol headers as well.
+ * - PBUF_ROM: no buffer memory is allocated for the pbuf, even for
+ *             protocol headers. Additional headers must be prepended
+ *             by allocating another pbuf and chain in to the front of
+ *             the ROM pbuf. It is assumed that the memory used is really
+ *             similar to ROM in that it is immutable and will not be
+ *             changed. Memory which is dynamic should generally not
+ *             be attached to PBUF_ROM pbufs. Use PBUF_REF instead.
+ * - PBUF_REF: no buffer memory is allocated for the pbuf, even for
+ *             protocol headers. It is assumed that the pbuf is only
+ *             being used in a single thread. If the pbuf gets queued,
+ *             then pbuf_take should be called to copy the buffer.
+ * - PBUF_POOL: the pbuf is allocated as a pbuf chain, with pbufs from
+ *              the pbuf pool that is allocated during pbuf_init().
+ *
+ * @return the allocated pbuf. If multiple pbufs where allocated, this
+ * is the first pbuf of a pbuf chain.
+ */
+struct pbuf *
+pbuf_alloc(pbuf_layer layer, u16_t length, pbuf_type type)
+{
+  struct pbuf *p, *q, *r;
+  u16_t offset;
+  s32_t rem_len; /* remaining length */
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F")\n", length));
+
+  /* determine header offset */
+  offset = 0;
+  switch (layer) {
+  case PBUF_TRANSPORT:
+    /* add room for transport (often TCP) layer header */
+    offset += PBUF_TRANSPORT_HLEN;
+    /* FALLTHROUGH */
+  case PBUF_IP:
+    /* add room for IP layer header */
+    offset += PBUF_IP_HLEN;
+    /* FALLTHROUGH */
+  case PBUF_LINK:
+    /* add room for link layer header */
+    offset += PBUF_LINK_HLEN;
+    break;
+  case PBUF_RAW:
+    break;
+  default:
+    LWIP_ASSERT("pbuf_alloc: bad pbuf layer", 0);
+    return NULL;
+  }
+
+  switch (type) {
+  case PBUF_POOL:
+    /* allocate head of pbuf chain into p */
+    p = (struct pbuf *)memp_malloc(MEMP_PBUF_POOL);
+    LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc: allocated pbuf %p\n", (void *)p));
+    if (p == NULL) {
+      PBUF_POOL_IS_EMPTY();
+      return NULL;
+    }
+    p->type = type;
+    p->next = NULL;
+
+    /* make the payload pointer point 'offset' bytes into pbuf data memory */
+    p->payload = LWIP_MEM_ALIGN((void *)((u8_t *)p + (SIZEOF_STRUCT_PBUF + offset)));
+    LWIP_ASSERT("pbuf_alloc: pbuf p->payload properly aligned",
+            ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
+    /* the total length of the pbuf chain is the requested size */
+    p->tot_len = length;
+    /* set the length of the first pbuf in the chain */
+    p->len = LWIP_MIN(length, PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset));
+    LWIP_ASSERT("check p->payload + p->len does not overflow pbuf",
+                ((u8_t*)p->payload + p->len <=
+                 (u8_t*)p + SIZEOF_STRUCT_PBUF + PBUF_POOL_BUFSIZE_ALIGNED));
+    LWIP_ASSERT("PBUF_POOL_BUFSIZE must be bigger than MEM_ALIGNMENT",
+      (PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)) > 0 );
+    /* set reference count (needed here in case we fail) */
+    p->ref = 1;
+
+    /* now allocate the tail of the pbuf chain */
+
+    /* remember first pbuf for linkage in next iteration */
+    r = p;
+    /* remaining length to be allocated */
+    rem_len = length - p->len;
+    /* any remaining pbufs to be allocated? */
+    while (rem_len > 0) {
+      q = (struct pbuf *)memp_malloc(MEMP_PBUF_POOL);
+      if (q == NULL) {
+        PBUF_POOL_IS_EMPTY();
+        /* free chain so far allocated */
+        pbuf_free(p);
+        /* bail out unsuccesfully */
+        return NULL;
+      }
+      q->type = type;
+      q->flags = 0;
+      q->next = NULL;
+      /* make previous pbuf point to this pbuf */
+      r->next = q;
+      /* set total length of this pbuf and next in chain */
+      LWIP_ASSERT("rem_len < max_u16_t", rem_len < 0xffff);
+      q->tot_len = (u16_t)rem_len;
+      /* this pbuf length is pool size, unless smaller sized tail */
+      q->len = LWIP_MIN((u16_t)rem_len, PBUF_POOL_BUFSIZE_ALIGNED);
+      q->payload = (void *)((u8_t *)q + SIZEOF_STRUCT_PBUF);
+      LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned",
+              ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0);
+      LWIP_ASSERT("check p->payload + p->len does not overflow pbuf",
+                  ((u8_t*)p->payload + p->len <=
+                   (u8_t*)p + SIZEOF_STRUCT_PBUF + PBUF_POOL_BUFSIZE_ALIGNED));
+      q->ref = 1;
+      /* calculate remaining length to be allocated */
+      rem_len -= q->len;
+      /* remember this pbuf for linkage in next iteration */
+      r = q;
+    }
+    /* end of chain */
+    /*r->next = NULL;*/
+
+    break;
+  case PBUF_RAM:
+    /* If pbuf is to be allocated in RAM, allocate memory for it. */
+    p = (struct pbuf*)mem_malloc(LWIP_MEM_ALIGN_SIZE(SIZEOF_STRUCT_PBUF + offset) + LWIP_MEM_ALIGN_SIZE(length));
+    if (p == NULL) {
+      return NULL;
+    }
+    /* Set up internal structure of the pbuf. */
+    p->payload = LWIP_MEM_ALIGN((void *)((u8_t *)p + SIZEOF_STRUCT_PBUF + offset));
+    p->len = p->tot_len = length;
+    p->next = NULL;
+    p->type = type;
+
+    LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned",
+           ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
+    break;
+  /* pbuf references existing (non-volatile static constant) ROM payload? */
+  case PBUF_ROM:
+  /* pbuf references existing (externally allocated) RAM payload? */
+  case PBUF_REF:
+    /* only allocate memory for the pbuf structure */
+    p = (struct pbuf *)memp_malloc(MEMP_PBUF);
+    if (p == NULL) {
+      LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+                  ("pbuf_alloc: Could not allocate MEMP_PBUF for PBUF_%s.\n",
+                  (type == PBUF_ROM) ? "ROM" : "REF"));
+      return NULL;
+    }
+    /* caller must set this field properly, afterwards */
+    p->payload = NULL;
+    p->len = p->tot_len = length;
+    p->next = NULL;
+    p->type = type;
+    break;
+  default:
+    LWIP_ASSERT("pbuf_alloc: erroneous type", 0);
+    return NULL;
+  }
+  /* set reference count */
+  p->ref = 1;
+  /* set flags */
+  p->flags = 0;
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p));
+  return p;
+}
+
+#if LWIP_SUPPORT_CUSTOM_PBUF
+/** Initialize a custom pbuf (already allocated).
+ *
+ * @param layer flag to define header size
+ * @param length size of the pbuf's payload
+ * @param type type of the pbuf (only used to treat the pbuf accordingly, as
+ *        this function allocates no memory)
+ * @param p pointer to the custom pbuf to initialize (already allocated)
+ * @param payload_mem pointer to the buffer that is used for payload and headers,
+ *        must be at least big enough to hold 'length' plus the header size,
+ *        may be NULL if set later
+ * @param payload_mem_len the size of the 'payload_mem' buffer, must be at least
+ *        big enough to hold 'length' plus the header size
+ */
+struct pbuf*
+pbuf_alloced_custom(pbuf_layer l, u16_t length, pbuf_type type, struct pbuf_custom *p,
+                    void *payload_mem, u16_t payload_mem_len)
+{
+  u16_t offset;
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloced_custom(length=%"U16_F")\n", length));
+
+  /* determine header offset */
+  offset = 0;
+  switch (l) {
+  case PBUF_TRANSPORT:
+    /* add room for transport (often TCP) layer header */
+    offset += PBUF_TRANSPORT_HLEN;
+    /* FALLTHROUGH */
+  case PBUF_IP:
+    /* add room for IP layer header */
+    offset += PBUF_IP_HLEN;
+    /* FALLTHROUGH */
+  case PBUF_LINK:
+    /* add room for link layer header */
+    offset += PBUF_LINK_HLEN;
+    break;
+  case PBUF_RAW:
+    break;
+  default:
+    LWIP_ASSERT("pbuf_alloced_custom: bad pbuf layer", 0);
+    return NULL;
+  }
+
+  if (LWIP_MEM_ALIGN_SIZE(offset) + length < payload_mem_len) {
+    LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_WARNING, ("pbuf_alloced_custom(length=%"U16_F") buffer too short\n", length));
+    return NULL;
+  }
+
+  p->pbuf.next = NULL;
+  if (payload_mem != NULL) {
+    p->pbuf.payload = LWIP_MEM_ALIGN((void *)((u8_t *)payload_mem + offset));
+  } else {
+    p->pbuf.payload = NULL;
+  }
+  p->pbuf.flags = PBUF_FLAG_IS_CUSTOM;
+  p->pbuf.len = p->pbuf.tot_len = length;
+  p->pbuf.type = type;
+  p->pbuf.ref = 1;
+  return &p->pbuf;
+}
+#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
+
+/**
+ * Shrink a pbuf chain to a desired length.
+ *
+ * @param p pbuf to shrink.
+ * @param new_len desired new length of pbuf chain
+ *
+ * Depending on the desired length, the first few pbufs in a chain might
+ * be skipped and left unchanged. The new last pbuf in the chain will be
+ * resized, and any remaining pbufs will be freed.
+ *
+ * @note If the pbuf is ROM/REF, only the ->tot_len and ->len fields are adjusted.
+ * @note May not be called on a packet queue.
+ *
+ * @note Despite its name, pbuf_realloc cannot grow the size of a pbuf (chain).
+ */
+void
+pbuf_realloc(struct pbuf *p, u16_t new_len)
+{
+  struct pbuf *q;
+  u16_t rem_len; /* remaining length */
+  s32_t grow;
+
+  LWIP_ASSERT("pbuf_realloc: p != NULL", p != NULL);
+  LWIP_ASSERT("pbuf_realloc: sane p->type", p->type == PBUF_POOL ||
+              p->type == PBUF_ROM ||
+              p->type == PBUF_RAM ||
+              p->type == PBUF_REF);
+
+  /* desired length larger than current length? */
+  if (new_len >= p->tot_len) {
+    /* enlarging not yet supported */
+    return;
+  }
+
+  /* the pbuf chain grows by (new_len - p->tot_len) bytes
+   * (which may be negative in case of shrinking) */
+  grow = new_len - p->tot_len;
+
+  /* first, step over any pbufs that should remain in the chain */
+  rem_len = new_len;
+  q = p;
+  /* should this pbuf be kept? */
+  while (rem_len > q->len) {
+    /* decrease remaining length by pbuf length */
+    rem_len -= q->len;
+    /* decrease total length indicator */
+    LWIP_ASSERT("grow < max_u16_t", grow < 0xffff);
+    q->tot_len += (u16_t)grow;
+    /* proceed to next pbuf in chain */
+    q = q->next;
+    LWIP_ASSERT("pbuf_realloc: q != NULL", q != NULL);
+  }
+  /* we have now reached the new last pbuf (in q) */
+  /* rem_len == desired length for pbuf q */
+
+  /* shrink allocated memory for PBUF_RAM */
+  /* (other types merely adjust their length fields */
+  if ((q->type == PBUF_RAM) && (rem_len != q->len)) {
+    /* reallocate and adjust the length of the pbuf that will be split */
+    q = (struct pbuf *)mem_trim(q, (u16_t)((u8_t *)q->payload - (u8_t *)q) + rem_len);
+    LWIP_ASSERT("mem_trim returned q == NULL", q != NULL);
+  }
+  /* adjust length fields for new last pbuf */
+  q->len = rem_len;
+  q->tot_len = q->len;
+
+  /* any remaining pbufs in chain? */
+  if (q->next != NULL) {
+    /* free remaining pbufs in chain */
+    pbuf_free(q->next);
+  }
+  /* q is last packet in chain */
+  q->next = NULL;
+
+}
+
+/**
+ * Adjusts the payload pointer to hide or reveal headers in the payload.
+ *
+ * Adjusts the ->payload pointer so that space for a header
+ * (dis)appears in the pbuf payload.
+ *
+ * The ->payload, ->tot_len and ->len fields are adjusted.
+ *
+ * @param p pbuf to change the header size.
+ * @param header_size_increment Number of bytes to increment header size which
+ * increases the size of the pbuf. New space is on the front.
+ * (Using a negative value decreases the header size.)
+ * If hdr_size_inc is 0, this function does nothing and returns succesful.
+ *
+ * PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so
+ * the call will fail. A check is made that the increase in header size does
+ * not move the payload pointer in front of the start of the buffer.
+ * @return non-zero on failure, zero on success.
+ *
+ */
+u8_t
+pbuf_header(struct pbuf *p, s16_t header_size_increment)
+{
+  u16_t type;
+  void *payload;
+  u16_t increment_magnitude;
+
+  LWIP_ASSERT("p != NULL", p != NULL);
+  if ((header_size_increment == 0) || (p == NULL)) {
+    return 0;
+  }
+ 
+  if (header_size_increment < 0){
+    increment_magnitude = -header_size_increment;
+    /* Check that we aren't going to move off the end of the pbuf */
+    LWIP_ERROR("increment_magnitude <= p->len", (increment_magnitude <= p->len), return 1;);
+  } else {
+    increment_magnitude = header_size_increment;
+#if 0
+    /* Can't assert these as some callers speculatively call
+         pbuf_header() to see if it's OK.  Will return 1 below instead. */
+    /* Check that we've got the correct type of pbuf to work with */
+    LWIP_ASSERT("p->type == PBUF_RAM || p->type == PBUF_POOL", 
+                p->type == PBUF_RAM || p->type == PBUF_POOL);
+    /* Check that we aren't going to move off the beginning of the pbuf */
+    LWIP_ASSERT("p->payload - increment_magnitude >= p + SIZEOF_STRUCT_PBUF",
+                (u8_t *)p->payload - increment_magnitude >= (u8_t *)p + SIZEOF_STRUCT_PBUF);
+#endif
+  }
+
+  type = p->type;
+  /* remember current payload pointer */
+  payload = p->payload;
+
+  /* pbuf types containing payloads? */
+  if (type == PBUF_RAM || type == PBUF_POOL) {
+    /* set new payload pointer */
+    p->payload = (u8_t *)p->payload - header_size_increment;
+    /* boundary check fails? */
+    if ((u8_t *)p->payload < (u8_t *)p + SIZEOF_STRUCT_PBUF) {
+      LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+        ("pbuf_header: failed as %p < %p (not enough space for new header size)\n",
+        (void *)p->payload, (void *)(p + 1)));
+      /* restore old payload pointer */
+      p->payload = payload;
+      /* bail out unsuccesfully */
+      return 1;
+    }
+  /* pbuf types refering to external payloads? */
+  } else if (type == PBUF_REF || type == PBUF_ROM) {
+    /* hide a header in the payload? */
+    if ((header_size_increment < 0) && (increment_magnitude <= p->len)) {
+      /* increase payload pointer */
+      p->payload = (u8_t *)p->payload - header_size_increment;
+    } else {
+      /* cannot expand payload to front (yet!)
+       * bail out unsuccesfully */
+      return 1;
+    }
+  } else {
+    /* Unknown type */
+    LWIP_ASSERT("bad pbuf type", 0);
+    return 1;
+  }
+  /* modify pbuf length fields */
+  p->len += header_size_increment;
+  p->tot_len += header_size_increment;
+
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_header: old %p new %p (%"S16_F")\n",
+    (void *)payload, (void *)p->payload, header_size_increment));
+
+  return 0;
+}
+
+/**
+ * Dereference a pbuf chain or queue and deallocate any no-longer-used
+ * pbufs at the head of this chain or queue.
+ *
+ * Decrements the pbuf reference count. If it reaches zero, the pbuf is
+ * deallocated.
+ *
+ * For a pbuf chain, this is repeated for each pbuf in the chain,
+ * up to the first pbuf which has a non-zero reference count after
+ * decrementing. So, when all reference counts are one, the whole
+ * chain is free'd.
+ *
+ * @param p The pbuf (chain) to be dereferenced.
+ *
+ * @return the number of pbufs that were de-allocated
+ * from the head of the chain.
+ *
+ * @note MUST NOT be called on a packet queue (Not verified to work yet).
+ * @note the reference counter of a pbuf equals the number of pointers
+ * that refer to the pbuf (or into the pbuf).
+ *
+ * @internal examples:
+ *
+ * Assuming existing chains a->b->c with the following reference
+ * counts, calling pbuf_free(a) results in:
+ * 
+ * 1->2->3 becomes ...1->3
+ * 3->3->3 becomes 2->3->3
+ * 1->1->2 becomes ......1
+ * 2->1->1 becomes 1->1->1
+ * 1->1->1 becomes .......
+ *
+ */
+u8_t
+pbuf_free(struct pbuf *p)
+{
+  u16_t type;
+  struct pbuf *q;
+  u8_t count;
+
+  if (p == NULL) {
+    LWIP_ASSERT("p != NULL", p != NULL);
+    /* if assertions are disabled, proceed with debug output */
+    LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+      ("pbuf_free(p == NULL) was called.\n"));
+    return 0;
+  }
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free(%p)\n", (void *)p));
+
+  PERF_START;
+
+  LWIP_ASSERT("pbuf_free: sane type",
+    p->type == PBUF_RAM || p->type == PBUF_ROM ||
+    p->type == PBUF_REF || p->type == PBUF_POOL);
+
+  count = 0;
+  /* de-allocate all consecutive pbufs from the head of the chain that
+   * obtain a zero reference count after decrementing*/
+  while (p != NULL) {
+    u16_t ref;
+    SYS_ARCH_DECL_PROTECT(old_level);
+    /* Since decrementing ref cannot be guaranteed to be a single machine operation
+     * we must protect it. We put the new ref into a local variable to prevent
+     * further protection. */
+    SYS_ARCH_PROTECT(old_level);
+    /* all pbufs in a chain are referenced at least once */
+    LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0);
+    /* decrease reference count (number of pointers to pbuf) */
+    ref = --(p->ref);
+    SYS_ARCH_UNPROTECT(old_level);
+    /* this pbuf is no longer referenced to? */
+    if (ref == 0) {
+      /* remember next pbuf in chain for next iteration */
+      q = p->next;
+      LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: deallocating %p\n", (void *)p));
+      type = p->type;
+#if LWIP_SUPPORT_CUSTOM_PBUF
+      /* is this a custom pbuf? */
+      if ((p->flags & PBUF_FLAG_IS_CUSTOM) != 0) {
+        struct pbuf_custom *pc = (struct pbuf_custom*)p;
+        LWIP_ASSERT("pc->custom_free_function != NULL", pc->custom_free_function != NULL);
+        pc->custom_free_function(p);
+      } else
+#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
+      {
+        /* is this a pbuf from the pool? */
+        if (type == PBUF_POOL) {
+          memp_free(MEMP_PBUF_POOL, p);
+        /* is this a ROM or RAM referencing pbuf? */
+        } else if (type == PBUF_ROM || type == PBUF_REF) {
+          memp_free(MEMP_PBUF, p);
+        /* type == PBUF_RAM */
+        } else {
+          mem_free(p);
+        }
+      }
+      count++;
+      /* proceed to next pbuf */
+      p = q;
+    /* p->ref > 0, this pbuf is still referenced to */
+    /* (and so the remaining pbufs in chain as well) */
+    } else {
+      LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, ref));
+      /* stop walking through the chain */
+      p = NULL;
+    }
+  }
+  PERF_STOP("pbuf_free");
+  /* return number of de-allocated pbufs */
+  return count;
+}
+
+/**
+ * Count number of pbufs in a chain
+ *
+ * @param p first pbuf of chain
+ * @return the number of pbufs in a chain
+ */
+
+u8_t
+pbuf_clen(struct pbuf *p)
+{
+  u8_t len;
+
+  len = 0;
+  while (p != NULL) {
+    ++len;
+    p = p->next;
+  }
+  return len;
+}
+
+/**
+ * Increment the reference count of the pbuf.
+ *
+ * @param p pbuf to increase reference counter of
+ *
+ */
+void
+pbuf_ref(struct pbuf *p)
+{
+  SYS_ARCH_DECL_PROTECT(old_level);
+  /* pbuf given? */
+  if (p != NULL) {
+    SYS_ARCH_PROTECT(old_level);
+    ++(p->ref);
+    SYS_ARCH_UNPROTECT(old_level);
+  }
+}
+
+/**
+ * Concatenate two pbufs (each may be a pbuf chain) and take over
+ * the caller's reference of the tail pbuf.
+ * 
+ * @note The caller MAY NOT reference the tail pbuf afterwards.
+ * Use pbuf_chain() for that purpose.
+ * 
+ * @see pbuf_chain()
+ */
+
+void
+pbuf_cat(struct pbuf *h, struct pbuf *t)
+{
+  struct pbuf *p;
+
+  LWIP_ERROR("(h != NULL) && (t != NULL) (programmer violates API)",
+             ((h != NULL) && (t != NULL)), return;);
+
+  /* proceed to last pbuf of chain */
+  for (p = h; p->next != NULL; p = p->next) {
+    /* add total length of second chain to all totals of first chain */
+    p->tot_len += t->tot_len;
+  }
+  /* { p is last pbuf of first h chain, p->next == NULL } */
+  LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len);
+  LWIP_ASSERT("p->next == NULL", p->next == NULL);
+  /* add total length of second chain to last pbuf total of first chain */
+  p->tot_len += t->tot_len;
+  /* chain last pbuf of head (p) with first of tail (t) */
+  p->next = t;
+  /* p->next now references t, but the caller will drop its reference to t,
+   * so netto there is no change to the reference count of t.
+   */
+}
+
+/**
+ * Chain two pbufs (or pbuf chains) together.
+ * 
+ * The caller MUST call pbuf_free(t) once it has stopped
+ * using it. Use pbuf_cat() instead if you no longer use t.
+ * 
+ * @param h head pbuf (chain)
+ * @param t tail pbuf (chain)
+ * @note The pbufs MUST belong to the same packet.
+ * @note MAY NOT be called on a packet queue.
+ *
+ * The ->tot_len fields of all pbufs of the head chain are adjusted.
+ * The ->next field of the last pbuf of the head chain is adjusted.
+ * The ->ref field of the first pbuf of the tail chain is adjusted.
+ *
+ */
+void
+pbuf_chain(struct pbuf *h, struct pbuf *t)
+{
+  pbuf_cat(h, t);
+  /* t is now referenced by h */
+  pbuf_ref(t);
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t));
+}
+
+/**
+ * Dechains the first pbuf from its succeeding pbufs in the chain.
+ *
+ * Makes p->tot_len field equal to p->len.
+ * @param p pbuf to dechain
+ * @return remainder of the pbuf chain, or NULL if it was de-allocated.
+ * @note May not be called on a packet queue.
+ */
+struct pbuf *
+pbuf_dechain(struct pbuf *p)
+{
+  struct pbuf *q;
+  u8_t tail_gone = 1;
+  /* tail */
+  q = p->next;
+  /* pbuf has successor in chain? */
+  if (q != NULL) {
+    /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */
+    LWIP_ASSERT("p->tot_len == p->len + q->tot_len", q->tot_len == p->tot_len - p->len);
+    /* enforce invariant if assertion is disabled */
+    q->tot_len = p->tot_len - p->len;
+    /* decouple pbuf from remainder */
+    p->next = NULL;
+    /* total length of pbuf p is its own length only */
+    p->tot_len = p->len;
+    /* q is no longer referenced by p, free it */
+    LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_dechain: unreferencing %p\n", (void *)q));
+    tail_gone = pbuf_free(q);
+    if (tail_gone > 0) {
+      LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE,
+                  ("pbuf_dechain: deallocated %p (as it is no longer referenced)\n", (void *)q));
+    }
+    /* return remaining tail or NULL if deallocated */
+  }
+  /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */
+  LWIP_ASSERT("p->tot_len == p->len", p->tot_len == p->len);
+  return ((tail_gone > 0) ? NULL : q);
+}
+
+/**
+ *
+ * Create PBUF_RAM copies of pbufs.
+ *
+ * Used to queue packets on behalf of the lwIP stack, such as
+ * ARP based queueing.
+ *
+ * @note You MUST explicitly use p = pbuf_take(p);
+ *
+ * @note Only one packet is copied, no packet queue!
+ *
+ * @param p_to pbuf destination of the copy
+ * @param p_from pbuf source of the copy
+ *
+ * @return ERR_OK if pbuf was copied
+ *         ERR_ARG if one of the pbufs is NULL or p_to is not big
+ *                 enough to hold p_from
+ */
+err_t
+pbuf_copy(struct pbuf *p_to, struct pbuf *p_from)
+{
+  u16_t offset_to=0, offset_from=0, len;
+
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy(%p, %p)\n",
+    (void*)p_to, (void*)p_from));
+
+  /* is the target big enough to hold the source? */
+  LWIP_ERROR("pbuf_copy: target not big enough to hold source", ((p_to != NULL) &&
+             (p_from != NULL) && (p_to->tot_len >= p_from->tot_len)), return ERR_ARG;);
+
+  /* iterate through pbuf chain */
+  do
+  {
+    LWIP_ASSERT("p_to != NULL", p_to != NULL);
+    /* copy one part of the original chain */
+    if ((p_to->len - offset_to) >= (p_from->len - offset_from)) {
+      /* complete current p_from fits into current p_to */
+      len = p_from->len - offset_from;
+    } else {
+      /* current p_from does not fit into current p_to */
+      len = p_to->len - offset_to;
+    }
+    MEMCPY((u8_t*)p_to->payload + offset_to, (u8_t*)p_from->payload + offset_from, len);
+    offset_to += len;
+    offset_from += len;
+    LWIP_ASSERT("offset_to <= p_to->len", offset_to <= p_to->len);
+    if (offset_to == p_to->len) {
+      /* on to next p_to (if any) */
+      offset_to = 0;
+      p_to = p_to->next;
+    }
+    LWIP_ASSERT("offset_from <= p_from->len", offset_from <= p_from->len);
+    if (offset_from >= p_from->len) {
+      /* on to next p_from (if any) */
+      offset_from = 0;
+      p_from = p_from->next;
+    }
+
+    if((p_from != NULL) && (p_from->len == p_from->tot_len)) {
+      /* don't copy more than one packet! */
+      LWIP_ERROR("pbuf_copy() does not allow packet queues!\n",
+                 (p_from->next == NULL), return ERR_VAL;);
+    }
+    if((p_to != NULL) && (p_to->len == p_to->tot_len)) {
+      /* don't copy more than one packet! */
+      LWIP_ERROR("pbuf_copy() does not allow packet queues!\n",
+                  (p_to->next == NULL), return ERR_VAL;);
+    }
+  } while (p_from);
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy: end of chain reached.\n"));
+  return ERR_OK;
+}
+
+/**
+ * Copy (part of) the contents of a packet buffer
+ * to an application supplied buffer.
+ *
+ * @param buf the pbuf from which to copy data
+ * @param dataptr the application supplied buffer
+ * @param len length of data to copy (dataptr must be big enough). No more 
+ * than buf->tot_len will be copied, irrespective of len
+ * @param offset offset into the packet buffer from where to begin copying len bytes
+ * @return the number of bytes copied, or 0 on failure
+ */
+u16_t
+pbuf_copy_partial(struct pbuf *buf, void *dataptr, u16_t len, u16_t offset)
+{
+  struct pbuf *p;
+  u16_t left;
+  u16_t buf_copy_len;
+  u16_t copied_total = 0;
+
+  LWIP_ERROR("pbuf_copy_partial: invalid buf", (buf != NULL), return 0;);
+  LWIP_ERROR("pbuf_copy_partial: invalid dataptr", (dataptr != NULL), return 0;);
+
+  left = 0;
+
+  if((buf == NULL) || (dataptr == NULL)) {
+    return 0;
+  }
+
+  /* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */
+  for(p = buf; len != 0 && p != NULL; p = p->next) {
+    if ((offset != 0) && (offset >= p->len)) {
+      /* don't copy from this buffer -> on to the next */
+      offset -= p->len;
+    } else {
+      /* copy from this buffer. maybe only partially. */
+      buf_copy_len = p->len - offset;
+      if (buf_copy_len > len)
+          buf_copy_len = len;
+      /* copy the necessary parts of the buffer */
+      MEMCPY(&((char*)dataptr)[left], &((char*)p->payload)[offset], buf_copy_len);
+      copied_total += buf_copy_len;
+      left += buf_copy_len;
+      len -= buf_copy_len;
+      offset = 0;
+    }
+  }
+  return copied_total;
+}
+
+/**
+ * Copy application supplied data into a pbuf.
+ * This function can only be used to copy the equivalent of buf->tot_len data.
+ *
+ * @param buf pbuf to fill with data
+ * @param dataptr application supplied data buffer
+ * @param len length of the application supplied data buffer
+ *
+ * @return ERR_OK if successful, ERR_MEM if the pbuf is not big enough
+ */
+err_t
+pbuf_take(struct pbuf *buf, const void *dataptr, u16_t len)
+{
+  struct pbuf *p;
+  u16_t buf_copy_len;
+  u16_t total_copy_len = len;
+  u16_t copied_total = 0;
+
+  LWIP_ERROR("pbuf_take: invalid buf", (buf != NULL), return 0;);
+  LWIP_ERROR("pbuf_take: invalid dataptr", (dataptr != NULL), return 0;);
+
+  if ((buf == NULL) || (dataptr == NULL) || (buf->tot_len < len)) {
+    return ERR_ARG;
+  }
+
+  /* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */
+  for(p = buf; total_copy_len != 0; p = p->next) {
+    LWIP_ASSERT("pbuf_take: invalid pbuf", p != NULL);
+    buf_copy_len = total_copy_len;
+    if (buf_copy_len > p->len) {
+      /* this pbuf cannot hold all remaining data */
+      buf_copy_len = p->len;
+    }
+    /* copy the necessary parts of the buffer */
+    MEMCPY(p->payload, &((char*)dataptr)[copied_total], buf_copy_len);
+    total_copy_len -= buf_copy_len;
+    copied_total += buf_copy_len;
+  }
+  LWIP_ASSERT("did not copy all data", total_copy_len == 0 && copied_total == len);
+  return ERR_OK;
+}
+
+/**
+ * Creates a single pbuf out of a queue of pbufs.
+ *
+ * @remark: Either the source pbuf 'p' is freed by this function or the original
+ *          pbuf 'p' is returned, therefore the caller has to check the result!
+ *
+ * @param p the source pbuf
+ * @param layer pbuf_layer of the new pbuf
+ *
+ * @return a new, single pbuf (p->next is NULL)
+ *         or the old pbuf if allocation fails
+ */
+struct pbuf*
+pbuf_coalesce(struct pbuf *p, pbuf_layer layer)
+{
+  struct pbuf *q;
+  err_t err;
+  if (p->next == NULL) {
+    return p;
+  }
+  q = pbuf_alloc(layer, p->tot_len, PBUF_RAM);
+  if (q == NULL) {
+    /* @todo: what do we do now? */
+    return p;
+  }
+  err = pbuf_copy(q, p);
+  LWIP_ASSERT("pbuf_copy failed", err == ERR_OK);
+  pbuf_free(p);
+  return q;
+}
+
+#if LWIP_CHECKSUM_ON_COPY
+/**
+ * Copies data into a single pbuf (*not* into a pbuf queue!) and updates
+ * the checksum while copying
+ *
+ * @param p the pbuf to copy data into
+ * @param start_offset offset of p->payload where to copy the data to
+ * @param dataptr data to copy into the pbuf
+ * @param len length of data to copy into the pbuf
+ * @param chksum pointer to the checksum which is updated
+ * @return ERR_OK if successful, another error if the data does not fit
+ *         within the (first) pbuf (no pbuf queues!)
+ */
+err_t
+pbuf_fill_chksum(struct pbuf *p, u16_t start_offset, const void *dataptr,
+                 u16_t len, u16_t *chksum)
+{
+  u32_t acc;
+  u16_t copy_chksum;
+  char *dst_ptr;
+  LWIP_ASSERT("p != NULL", p != NULL);
+  LWIP_ASSERT("dataptr != NULL", dataptr != NULL);
+  LWIP_ASSERT("chksum != NULL", chksum != NULL);
+  LWIP_ASSERT("len != 0", len != 0);
+
+  if ((start_offset >= p->len) || (start_offset + len > p->len)) {
+    return ERR_ARG;
+  }
+
+  dst_ptr = ((char*)p->payload) + start_offset;
+  copy_chksum = LWIP_CHKSUM_COPY(dst_ptr, dataptr, len);
+  if ((start_offset & 1) != 0) {
+    copy_chksum = SWAP_BYTES_IN_WORD(copy_chksum);
+  }
+  acc = *chksum;
+  acc += copy_chksum;
+  *chksum = FOLD_U32T(acc);
+  return ERR_OK;
+}
+#endif /* LWIP_CHECKSUM_ON_COPY */
+
+ /** Get one byte from the specified position in a pbuf
+ * WARNING: returns zero for offset >= p->tot_len
+ *
+ * @param p pbuf to parse
+ * @param offset offset into p of the byte to return
+ * @return byte at an offset into p OR ZERO IF 'offset' >= p->tot_len
+ */
+u8_t
+pbuf_get_at(struct pbuf* p, u16_t offset)
+{
+  u16_t copy_from = offset;
+  struct pbuf* q = p;
+
+  /* get the correct pbuf */
+  while ((q != NULL) && (q->len <= copy_from)) {
+    copy_from -= q->len;
+    q = q->next;
+  }
+  /* return requested data if pbuf is OK */
+  if ((q != NULL) && (q->len > copy_from)) {
+    return ((u8_t*)q->payload)[copy_from];
+  }
+  return 0;
+}
+
+/** Compare pbuf contents at specified offset with memory s2, both of length n
+ *
+ * @param p pbuf to compare
+ * @param offset offset into p at wich to start comparing
+ * @param s2 buffer to compare
+ * @param n length of buffer to compare
+ * @return zero if equal, nonzero otherwise
+ *         (0xffff if p is too short, diffoffset+1 otherwise)
+ */
+u16_t
+pbuf_memcmp(struct pbuf* p, u16_t offset, const void* s2, u16_t n)
+{
+  u16_t start = offset;
+  struct pbuf* q = p;
+
+  /* get the correct pbuf */
+  while ((q != NULL) && (q->len <= start)) {
+    start -= q->len;
+    q = q->next;
+  }
+  /* return requested data if pbuf is OK */
+  if ((q != NULL) && (q->len > start)) {
+    u16_t i;
+    for(i = 0; i < n; i++) {
+      u8_t a = pbuf_get_at(q, start + i);
+      u8_t b = ((u8_t*)s2)[i];
+      if (a != b) {
+        return i+1;
+      }
+    }
+    return 0;
+  }
+  return 0xffff;
+}
+
+/** Find occurrence of mem (with length mem_len) in pbuf p, starting at offset
+ * start_offset.
+ *
+ * @param p pbuf to search, maximum length is 0xFFFE since 0xFFFF is used as
+ *        return value 'not found'
+ * @param mem search for the contents of this buffer
+ * @param mem_len length of 'mem'
+ * @param start_offset offset into p at which to start searching
+ * @return 0xFFFF if substr was not found in p or the index where it was found
+ */
+u16_t
+pbuf_memfind(struct pbuf* p, const void* mem, u16_t mem_len, u16_t start_offset)
+{
+  u16_t i;
+  u16_t max = p->tot_len - mem_len;
+  if (p->tot_len >= mem_len + start_offset) {
+    for(i = start_offset; i <= max; ) {
+      u16_t plus = pbuf_memcmp(p, i, mem, mem_len);
+      if (plus == 0) {
+        return i;
+      } else {
+        i += plus;
+      }
+    }
+  }
+  return 0xFFFF;
+}
+
+/** Find occurrence of substr with length substr_len in pbuf p, start at offset
+ * start_offset
+ * WARNING: in contrast to strstr(), this one does not stop at the first \0 in
+ * the pbuf/source string!
+ *
+ * @param p pbuf to search, maximum length is 0xFFFE since 0xFFFF is used as
+ *        return value 'not found'
+ * @param substr string to search for in p, maximum length is 0xFFFE
+ * @return 0xFFFF if substr was not found in p or the index where it was found
+ */
+u16_t
+pbuf_strstr(struct pbuf* p, const char* substr)
+{
+  size_t substr_len;
+  if ((substr == NULL) || (substr[0] == 0) || (p->tot_len == 0xFFFF)) {
+    return 0xFFFF;
+  }
+  substr_len = strlen(substr);
+  if (substr_len >= 0xFFFF) {
+    return 0xFFFF;
+  }
+  return pbuf_memfind(p, substr, (u16_t)substr_len, 0);
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/raw.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/raw.c
new file mode 100644
index 0000000..9fcb100
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/raw.c
@@ -0,0 +1,354 @@
+/**
+ * @file
+ * Implementation of raw protocol PCBs for low-level handling of
+ * different types of protocols besides (or overriding) those
+ * already available in lwIP.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/def.h"
+#include "lwip/memp.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/raw.h"
+#include "lwip/stats.h"
+#include "arch/perf.h"
+
+#include 
+
+/** The list of RAW PCBs */
+static struct raw_pcb *raw_pcbs;
+
+/**
+ * Determine if in incoming IP packet is covered by a RAW PCB
+ * and if so, pass it to a user-provided receive callback function.
+ *
+ * Given an incoming IP datagram (as a chain of pbufs) this function
+ * finds a corresponding RAW PCB and calls the corresponding receive
+ * callback function.
+ *
+ * @param p pbuf to be demultiplexed to a RAW PCB.
+ * @param inp network interface on which the datagram was received.
+ * @return - 1 if the packet has been eaten by a RAW PCB receive
+ *           callback function. The caller MAY NOT not reference the
+ *           packet any longer, and MAY NOT call pbuf_free().
+ * @return - 0 if packet is not eaten (pbuf is still referenced by the
+ *           caller).
+ *
+ */
+u8_t
+raw_input(struct pbuf *p, struct netif *inp)
+{
+  struct raw_pcb *pcb, *prev;
+  struct ip_hdr *iphdr;
+  s16_t proto;
+  u8_t eaten = 0;
+
+  LWIP_UNUSED_ARG(inp);
+
+  iphdr = (struct ip_hdr *)p->payload;
+  proto = IPH_PROTO(iphdr);
+
+  prev = NULL;
+  pcb = raw_pcbs;
+  /* loop through all raw pcbs until the packet is eaten by one */
+  /* this allows multiple pcbs to match against the packet by design */
+  while ((eaten == 0) && (pcb != NULL)) {
+    if ((pcb->protocol == proto) &&
+        (ip_addr_isany(&pcb->local_ip) ||
+         ip_addr_cmp(&(pcb->local_ip), ¤t_iphdr_dest))) {
+#if IP_SOF_BROADCAST_RECV
+      /* broadcast filter? */
+      if ((pcb->so_options & SOF_BROADCAST) || !ip_addr_isbroadcast(¤t_iphdr_dest, inp))
+#endif /* IP_SOF_BROADCAST_RECV */
+      {
+        /* receive callback function available? */
+        if (pcb->recv != NULL) {
+          /* the receive callback function did not eat the packet? */
+          if (pcb->recv(pcb->recv_arg, pcb, p, ip_current_src_addr()) != 0) {
+            /* receive function ate the packet */
+            p = NULL;
+            eaten = 1;
+            if (prev != NULL) {
+            /* move the pcb to the front of raw_pcbs so that is
+               found faster next time */
+              prev->next = pcb->next;
+              pcb->next = raw_pcbs;
+              raw_pcbs = pcb;
+            }
+          }
+        }
+        /* no receive callback function was set for this raw PCB */
+      }
+      /* drop the packet */
+    }
+    prev = pcb;
+    pcb = pcb->next;
+  }
+  return eaten;
+}
+
+/**
+ * Bind a RAW PCB.
+ *
+ * @param pcb RAW PCB to be bound with a local address ipaddr.
+ * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to
+ * bind to all local interfaces.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_USE. The specified IP address is already bound to by
+ * another RAW PCB.
+ *
+ * @see raw_disconnect()
+ */
+err_t
+raw_bind(struct raw_pcb *pcb, ip_addr_t *ipaddr)
+{
+  ip_addr_set(&pcb->local_ip, ipaddr);
+  return ERR_OK;
+}
+
+/**
+ * Connect an RAW PCB. This function is required by upper layers
+ * of lwip. Using the raw api you could use raw_sendto() instead
+ *
+ * This will associate the RAW PCB with the remote address.
+ *
+ * @param pcb RAW PCB to be connected with remote address ipaddr and port.
+ * @param ipaddr remote IP address to connect with.
+ *
+ * @return lwIP error code
+ *
+ * @see raw_disconnect() and raw_sendto()
+ */
+err_t
+raw_connect(struct raw_pcb *pcb, ip_addr_t *ipaddr)
+{
+  ip_addr_set(&pcb->remote_ip, ipaddr);
+  return ERR_OK;
+}
+
+
+/**
+ * Set the callback function for received packets that match the
+ * raw PCB's protocol and binding. 
+ * 
+ * The callback function MUST either
+ * - eat the packet by calling pbuf_free() and returning non-zero. The
+ *   packet will not be passed to other raw PCBs or other protocol layers.
+ * - not free the packet, and return zero. The packet will be matched
+ *   against further PCBs and/or forwarded to another protocol layers.
+ * 
+ * @return non-zero if the packet was free()d, zero if the packet remains
+ * available for others.
+ */
+void
+raw_recv(struct raw_pcb *pcb, raw_recv_fn recv, void *recv_arg)
+{
+  /* remember recv() callback and user data */
+  pcb->recv = recv;
+  pcb->recv_arg = recv_arg;
+}
+
+/**
+ * Send the raw IP packet to the given address. Note that actually you cannot
+ * modify the IP headers (this is inconsistent with the receive callback where
+ * you actually get the IP headers), you can only specify the IP payload here.
+ * It requires some more changes in lwIP. (there will be a raw_send() function
+ * then.)
+ *
+ * @param pcb the raw pcb which to send
+ * @param p the IP payload to send
+ * @param ipaddr the destination address of the IP packet
+ *
+ */
+err_t
+raw_sendto(struct raw_pcb *pcb, struct pbuf *p, ip_addr_t *ipaddr)
+{
+  err_t err;
+  struct netif *netif;
+  ip_addr_t *src_ip;
+  struct pbuf *q; /* q will be sent down the stack */
+  
+  LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE, ("raw_sendto\n"));
+  
+  /* not enough space to add an IP header to first pbuf in given p chain? */
+  if (pbuf_header(p, IP_HLEN)) {
+    /* allocate header in new pbuf */
+    q = pbuf_alloc(PBUF_IP, 0, PBUF_RAM);
+    /* new header pbuf could not be allocated? */
+    if (q == NULL) {
+      LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("raw_sendto: could not allocate header\n"));
+      return ERR_MEM;
+    }
+    if (p->tot_len != 0) {
+      /* chain header q in front of given pbuf p */
+      pbuf_chain(q, p);
+    }
+    /* { first pbuf q points to header pbuf } */
+    LWIP_DEBUGF(RAW_DEBUG, ("raw_sendto: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
+  }  else {
+    /* first pbuf q equals given pbuf */
+    q = p;
+    if(pbuf_header(q, -IP_HLEN)) {
+      LWIP_ASSERT("Can't restore header we just removed!", 0);
+      return ERR_MEM;
+    }
+  }
+
+  if ((netif = ip_route(ipaddr)) == NULL) {
+    LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_LEVEL_WARNING, ("raw_sendto: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+      ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr)));
+    /* free any temporary header pbuf allocated by pbuf_header() */
+    if (q != p) {
+      pbuf_free(q);
+    }
+    return ERR_RTE;
+  }
+
+#if IP_SOF_BROADCAST
+  /* broadcast filter? */
+  if (((pcb->so_options & SOF_BROADCAST) == 0) && ip_addr_isbroadcast(ipaddr, netif)) {
+    LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_LEVEL_WARNING, ("raw_sendto: SOF_BROADCAST not enabled on pcb %p\n", (void *)pcb));
+    /* free any temporary header pbuf allocated by pbuf_header() */
+    if (q != p) {
+      pbuf_free(q);
+    }
+    return ERR_VAL;
+  }
+#endif /* IP_SOF_BROADCAST */
+
+  if (ip_addr_isany(&pcb->local_ip)) {
+    /* use outgoing network interface IP address as source address */
+    src_ip = &(netif->ip_addr);
+  } else {
+    /* use RAW PCB local IP address as source address */
+    src_ip = &(pcb->local_ip);
+  }
+
+#if LWIP_NETIF_HWADDRHINT
+  netif->addr_hint = &(pcb->addr_hint);
+#endif /* LWIP_NETIF_HWADDRHINT*/
+  err = ip_output_if (q, src_ip, ipaddr, pcb->ttl, pcb->tos, pcb->protocol, netif);
+#if LWIP_NETIF_HWADDRHINT
+  netif->addr_hint = NULL;
+#endif /* LWIP_NETIF_HWADDRHINT*/
+
+  /* did we chain a header earlier? */
+  if (q != p) {
+    /* free the header */
+    pbuf_free(q);
+  }
+  return err;
+}
+
+/**
+ * Send the raw IP packet to the address given by raw_connect()
+ *
+ * @param pcb the raw pcb which to send
+ * @param p the IP payload to send
+ *
+ */
+err_t
+raw_send(struct raw_pcb *pcb, struct pbuf *p)
+{
+  return raw_sendto(pcb, p, &pcb->remote_ip);
+}
+
+/**
+ * Remove an RAW PCB.
+ *
+ * @param pcb RAW PCB to be removed. The PCB is removed from the list of
+ * RAW PCB's and the data structure is freed from memory.
+ *
+ * @see raw_new()
+ */
+void
+raw_remove(struct raw_pcb *pcb)
+{
+  struct raw_pcb *pcb2;
+  /* pcb to be removed is first in list? */
+  if (raw_pcbs == pcb) {
+    /* make list start at 2nd pcb */
+    raw_pcbs = raw_pcbs->next;
+    /* pcb not 1st in list */
+  } else {
+    for(pcb2 = raw_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
+      /* find pcb in raw_pcbs list */
+      if (pcb2->next != NULL && pcb2->next == pcb) {
+        /* remove pcb from list */
+        pcb2->next = pcb->next;
+      }
+    }
+  }
+  memp_free(MEMP_RAW_PCB, pcb);
+}
+
+/**
+ * Create a RAW PCB.
+ *
+ * @return The RAW PCB which was created. NULL if the PCB data structure
+ * could not be allocated.
+ *
+ * @param proto the protocol number of the IPs payload (e.g. IP_PROTO_ICMP)
+ *
+ * @see raw_remove()
+ */
+struct raw_pcb *
+raw_new(u8_t proto)
+{
+  struct raw_pcb *pcb;
+
+  LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE, ("raw_new\n"));
+
+  pcb = (struct raw_pcb *)memp_malloc(MEMP_RAW_PCB);
+  /* could allocate RAW PCB? */
+  if (pcb != NULL) {
+    /* initialize PCB to all zeroes */
+    memset(pcb, 0, sizeof(struct raw_pcb));
+    pcb->protocol = proto;
+    pcb->ttl = RAW_TTL;
+    pcb->next = raw_pcbs;
+    raw_pcbs = pcb;
+  }
+  return pcb;
+}
+
+#endif /* LWIP_RAW */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/snmp/asn1_dec.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/snmp/asn1_dec.c
new file mode 100644
index 0000000..1d56582
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/snmp/asn1_dec.c
@@ -0,0 +1,657 @@
+/**
+ * @file
+ * Abstract Syntax Notation One (ISO 8824, 8825) decoding
+ *
+ * @todo not optimised (yet), favor correctness over speed, favor speed over size
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/snmp_asn1.h"
+
+/**
+ * Retrieves type field from incoming pbuf chain.
+ *
+ * @param p points to a pbuf holding an ASN1 coded type field
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded type field
+ * @param type return ASN1 type
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ */
+err_t
+snmp_asn1_dec_type(struct pbuf *p, u16_t ofs, u8_t *type)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = (u8_t*)p->payload;
+      msg_ptr += ofs - base;
+      *type = *msg_ptr;
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Decodes length field from incoming pbuf chain into host length.
+ *
+ * @param p points to a pbuf holding an ASN1 coded length
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded length
+ * @param octets_used returns number of octets used by the length code
+ * @param length return host order length, upto 64k
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ */
+err_t
+snmp_asn1_dec_length(struct pbuf *p, u16_t ofs, u8_t *octets_used, u16_t *length)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = (u8_t*)p->payload;
+      msg_ptr += ofs - base;
+
+      if (*msg_ptr < 0x80)
+      {
+        /* primitive definite length format */
+        *octets_used = 1;
+        *length = *msg_ptr;
+        return ERR_OK;
+      }
+      else if (*msg_ptr == 0x80)
+      {
+        /* constructed indefinite length format, termination with two zero octets */
+        u8_t zeros;
+        u8_t i;
+
+        *length = 0;
+        zeros = 0;
+        while (zeros != 2)
+        {
+          i = 2;
+          while (i > 0)
+          {
+            i--;
+            (*length) += 1;
+            ofs += 1;
+            if (ofs >= plen)
+            {
+              /* next octet in next pbuf */
+              p = p->next;
+              if (p == NULL) { return ERR_ARG; }
+              msg_ptr = (u8_t*)p->payload;
+              plen += p->len;
+            }
+            else
+            {
+              /* next octet in same pbuf */
+              msg_ptr++;
+            }
+            if (*msg_ptr == 0)
+            {
+              zeros++;
+              if (zeros == 2)
+              {
+                /* stop while (i > 0) */
+                i = 0;
+              }
+            }
+            else
+            {
+              zeros = 0;
+            }
+          }
+        }
+        *octets_used = 1;
+        return ERR_OK;
+      }
+      else if (*msg_ptr == 0x81)
+      {
+        /* constructed definite length format, one octet */
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = (u8_t*)p->payload;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+        *length = *msg_ptr;
+        *octets_used = 2;
+        return ERR_OK;
+      }
+      else if (*msg_ptr == 0x82)
+      {
+        u8_t i;
+
+        /* constructed definite length format, two octets */
+        i = 2;
+        while (i > 0)
+        {
+          i--;
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = (u8_t*)p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+          if (i == 0)
+          {
+            /* least significant length octet */
+            *length |= *msg_ptr;
+          }
+          else
+          {
+            /* most significant length octet */
+            *length = (*msg_ptr) << 8;
+          }
+        }
+        *octets_used = 3;
+        return ERR_OK;
+      }
+      else
+      {
+        /* constructed definite length format 3..127 octets, this is too big (>64k) */
+        /**  @todo: do we need to accept inefficient codings with many leading zero's? */
+        *octets_used = 1 + ((*msg_ptr) & 0x7f);
+        return ERR_ARG;
+      }
+    }
+    p = p->next;
+  }
+
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Decodes positive integer (counter, gauge, timeticks) into u32_t.
+ *
+ * @param p points to a pbuf holding an ASN1 coded integer
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded integer
+ * @param len length of the coded integer field
+ * @param value return host order integer
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ *
+ * @note ASN coded integers are _always_ signed. E.g. +0xFFFF is coded
+ * as 0x00,0xFF,0xFF. Note the leading sign octet. A positive value
+ * of 0xFFFFFFFF is preceded with 0x00 and the length is 5 octets!!
+ */
+err_t
+snmp_asn1_dec_u32t(struct pbuf *p, u16_t ofs, u16_t len, u32_t *value)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = (u8_t*)p->payload;
+      msg_ptr += ofs - base;
+      if ((len > 0) && (len < 6))
+      {
+        /* start from zero */
+        *value = 0;
+        if (*msg_ptr & 0x80)
+        {
+          /* negative, expecting zero sign bit! */
+          return ERR_ARG;
+        }
+        else
+        {
+          /* positive */
+          if ((len > 1) && (*msg_ptr == 0))
+          {
+            /* skip leading "sign byte" octet 0x00 */
+            len--;
+            ofs += 1;
+            if (ofs >= plen)
+            {
+              /* next octet in next pbuf */
+              p = p->next;
+              if (p == NULL) { return ERR_ARG; }
+              msg_ptr = (u8_t*)p->payload;
+              plen += p->len;
+            }
+            else
+            {
+              /* next octet in same pbuf */
+              msg_ptr++;
+            }
+          }
+        }
+        /* OR octets with value */
+        while (len > 1)
+        {
+          len--;
+          *value |= *msg_ptr;
+          *value <<= 8;
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = (u8_t*)p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+        }
+        *value |= *msg_ptr;
+        return ERR_OK;
+      }
+      else
+      {
+        return ERR_ARG;
+      }
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Decodes integer into s32_t.
+ *
+ * @param p points to a pbuf holding an ASN1 coded integer
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded integer
+ * @param len length of the coded integer field
+ * @param value return host order integer
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ *
+ * @note ASN coded integers are _always_ signed!
+ */
+err_t
+snmp_asn1_dec_s32t(struct pbuf *p, u16_t ofs, u16_t len, s32_t *value)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+#if BYTE_ORDER == LITTLE_ENDIAN
+  u8_t *lsb_ptr = (u8_t*)value;
+#endif
+#if BYTE_ORDER == BIG_ENDIAN
+  u8_t *lsb_ptr = (u8_t*)value + sizeof(s32_t) - 1;
+#endif
+  u8_t sign;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = (u8_t*)p->payload;
+      msg_ptr += ofs - base;
+      if ((len > 0) && (len < 5))
+      {
+        if (*msg_ptr & 0x80)
+        {
+          /* negative, start from -1 */
+          *value = -1;
+          sign = 1;
+        }
+        else
+        {
+          /* positive, start from 0 */
+          *value = 0;
+          sign = 0;
+        }
+        /* OR/AND octets with value */
+        while (len > 1)
+        {
+          len--;
+          if (sign)
+          {
+            *lsb_ptr &= *msg_ptr;
+            *value <<= 8;
+            *lsb_ptr |= 255;
+          }
+          else
+          {
+            *lsb_ptr |= *msg_ptr;
+            *value <<= 8;
+          }
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = (u8_t*)p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+        }
+        if (sign)
+        {
+          *lsb_ptr &= *msg_ptr;
+        }
+        else
+        {
+          *lsb_ptr |= *msg_ptr;
+        }
+        return ERR_OK;
+      }
+      else
+      {
+        return ERR_ARG;
+      }
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Decodes object identifier from incoming message into array of s32_t.
+ *
+ * @param p points to a pbuf holding an ASN1 coded object identifier
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded object identifier
+ * @param len length of the coded object identifier
+ * @param oid return object identifier struct
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ */
+err_t
+snmp_asn1_dec_oid(struct pbuf *p, u16_t ofs, u16_t len, struct snmp_obj_id *oid)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+  s32_t *oid_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = (u8_t*)p->payload;
+      msg_ptr += ofs - base;
+
+      oid->len = 0;
+      oid_ptr = &oid->id[0];
+      if (len > 0)
+      {
+        /* first compressed octet */
+        if (*msg_ptr == 0x2B)
+        {
+          /* (most) common case 1.3 (iso.org) */
+          *oid_ptr = 1;
+          oid_ptr++;
+          *oid_ptr = 3;
+          oid_ptr++;
+        }
+        else if (*msg_ptr < 40)
+        {
+          *oid_ptr = 0;
+          oid_ptr++;
+          *oid_ptr = *msg_ptr;
+          oid_ptr++;
+        }
+        else if (*msg_ptr < 80)
+        {
+          *oid_ptr = 1;
+          oid_ptr++;
+          *oid_ptr = (*msg_ptr) - 40;
+          oid_ptr++;
+        }
+        else
+        {
+          *oid_ptr = 2;
+          oid_ptr++;
+          *oid_ptr = (*msg_ptr) - 80;
+          oid_ptr++;
+        }
+        oid->len = 2;
+      }
+      else
+      {
+        /* accepting zero length identifiers e.g. for
+           getnext operation. uncommon but valid */
+        return ERR_OK;
+      }
+      len--;
+      if (len > 0)
+      {
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = (u8_t*)p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+      }
+      while ((len > 0) && (oid->len < LWIP_SNMP_OBJ_ID_LEN))
+      {
+        /* sub-identifier uses multiple octets */
+        if (*msg_ptr & 0x80)
+        {
+          s32_t sub_id = 0;
+
+          while ((*msg_ptr & 0x80) && (len > 1))
+          {
+            len--;
+            sub_id = (sub_id << 7) + (*msg_ptr & ~0x80);
+            ofs += 1;
+            if (ofs >= plen)
+            {
+              /* next octet in next pbuf */
+              p = p->next;
+              if (p == NULL) { return ERR_ARG; }
+              msg_ptr = (u8_t*)p->payload;
+              plen += p->len;
+            }
+            else
+            {
+              /* next octet in same pbuf */
+              msg_ptr++;
+            }
+          }
+          if (!(*msg_ptr & 0x80) && (len > 0))
+          {
+            /* last octet sub-identifier */
+            len--;
+            sub_id = (sub_id << 7) + *msg_ptr;
+            *oid_ptr = sub_id;
+          }
+        }
+        else
+        {
+          /* !(*msg_ptr & 0x80) sub-identifier uses single octet */
+          len--;
+          *oid_ptr = *msg_ptr;
+        }
+        if (len > 0)
+        {
+          /* remaining oid bytes available ... */
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = (u8_t*)p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+        }
+        oid_ptr++;
+        oid->len++;
+      }
+      if (len == 0)
+      {
+        /* len == 0, end of oid */
+        return ERR_OK;
+      }
+      else
+      {
+        /* len > 0, oid->len == LWIP_SNMP_OBJ_ID_LEN or malformed encoding */
+        return ERR_ARG;
+      }
+
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Decodes (copies) raw data (ip-addresses, octet strings, opaque encoding)
+ * from incoming message into array.
+ *
+ * @param p points to a pbuf holding an ASN1 coded raw data
+ * @param ofs points to the offset within the pbuf chain of the ASN1 coded raw data
+ * @param len length of the coded raw data (zero is valid, e.g. empty string!)
+ * @param raw_len length of the raw return value
+ * @param raw return raw bytes
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode
+ */
+err_t
+snmp_asn1_dec_raw(struct pbuf *p, u16_t ofs, u16_t len, u16_t raw_len, u8_t *raw)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  if (len > 0)
+  {
+    plen = 0;
+    while (p != NULL)
+    {
+      base = plen;
+      plen += p->len;
+      if (ofs < plen)
+      {
+        msg_ptr = (u8_t*)p->payload;
+        msg_ptr += ofs - base;
+        if (raw_len >= len)
+        {
+          while (len > 1)
+          {
+            /* copy len - 1 octets */
+            len--;
+            *raw = *msg_ptr;
+            raw++;
+            ofs += 1;
+            if (ofs >= plen)
+            {
+              /* next octet in next pbuf */
+              p = p->next;
+              if (p == NULL) { return ERR_ARG; }
+              msg_ptr = (u8_t*)p->payload;
+              plen += p->len;
+            }
+            else
+            {
+              /* next octet in same pbuf */
+              msg_ptr++;
+            }
+          }
+          /* copy last octet */
+          *raw = *msg_ptr;
+          return ERR_OK;
+        }
+        else
+        {
+          /* raw_len < len, not enough dst space */
+          return ERR_ARG;
+        }
+      }
+      p = p->next;
+    }
+    /* p == NULL, ofs >= plen */
+    return ERR_ARG;
+  }
+  else
+  {
+    /* len == 0, empty string */
+    return ERR_OK;
+  }
+}
+
+#endif /* LWIP_SNMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/snmp/asn1_enc.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/snmp/asn1_enc.c
new file mode 100644
index 0000000..64dfc5f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/snmp/asn1_enc.c
@@ -0,0 +1,611 @@
+/**
+ * @file
+ * Abstract Syntax Notation One (ISO 8824, 8825) encoding
+ *
+ * @todo not optimised (yet), favor correctness over speed, favor speed over size
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/snmp_asn1.h"
+
+/**
+ * Returns octet count for length.
+ *
+ * @param length
+ * @param octets_needed points to the return value
+ */
+void
+snmp_asn1_enc_length_cnt(u16_t length, u8_t *octets_needed)
+{
+  if (length < 0x80U)
+  {
+    *octets_needed = 1;
+  }
+  else if (length < 0x100U)
+  {
+    *octets_needed = 2;
+  }
+  else
+  {
+    *octets_needed = 3;
+  }
+}
+
+/**
+ * Returns octet count for an u32_t.
+ *
+ * @param value
+ * @param octets_needed points to the return value
+ *
+ * @note ASN coded integers are _always_ signed. E.g. +0xFFFF is coded
+ * as 0x00,0xFF,0xFF. Note the leading sign octet. A positive value
+ * of 0xFFFFFFFF is preceded with 0x00 and the length is 5 octets!!
+ */
+void
+snmp_asn1_enc_u32t_cnt(u32_t value, u16_t *octets_needed)
+{
+  if (value < 0x80UL)
+  {
+    *octets_needed = 1;
+  }
+  else if (value < 0x8000UL)
+  {
+    *octets_needed = 2;
+  }
+  else if (value < 0x800000UL)
+  {
+    *octets_needed = 3;
+  }
+  else if (value < 0x80000000UL)
+  {
+    *octets_needed = 4;
+  }
+  else
+  {
+    *octets_needed = 5;
+  }
+}
+
+/**
+ * Returns octet count for an s32_t.
+ *
+ * @param value
+ * @param octets_needed points to the return value
+ *
+ * @note ASN coded integers are _always_ signed.
+ */
+void
+snmp_asn1_enc_s32t_cnt(s32_t value, u16_t *octets_needed)
+{
+  if (value < 0)
+  {
+    value = ~value;
+  }
+  if (value < 0x80L)
+  {
+    *octets_needed = 1;
+  }
+  else if (value < 0x8000L)
+  {
+    *octets_needed = 2;
+  }
+  else if (value < 0x800000L)
+  {
+    *octets_needed = 3;
+  }
+  else
+  {
+    *octets_needed = 4;
+  }
+}
+
+/**
+ * Returns octet count for an object identifier.
+ *
+ * @param ident_len object identifier array length
+ * @param ident points to object identifier array
+ * @param octets_needed points to the return value
+ */
+void
+snmp_asn1_enc_oid_cnt(u8_t ident_len, s32_t *ident, u16_t *octets_needed)
+{
+  s32_t sub_id;
+  u8_t cnt;
+
+  cnt = 0;
+  if (ident_len > 1)
+  {
+    /* compressed prefix in one octet */
+    cnt++;
+    ident_len -= 2;
+    ident += 2;
+  }
+  while(ident_len > 0)
+  {
+    ident_len--;
+    sub_id = *ident;
+
+    sub_id >>= 7;
+    cnt++;
+    while(sub_id > 0)
+    {
+      sub_id >>= 7;
+      cnt++;
+    }
+    ident++;
+  }
+  *octets_needed = cnt;
+}
+
+/**
+ * Encodes ASN type field into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode value into
+ * @param ofs points to the offset within the pbuf chain
+ * @param type input ASN1 type
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ */
+err_t
+snmp_asn1_enc_type(struct pbuf *p, u16_t ofs, u8_t type)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = (u8_t*)p->payload;
+      msg_ptr += ofs - base;
+      *msg_ptr = type;
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Encodes host order length field into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode length into
+ * @param ofs points to the offset within the pbuf chain
+ * @param length is the host order length to be encoded
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ */
+err_t
+snmp_asn1_enc_length(struct pbuf *p, u16_t ofs, u16_t length)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = (u8_t*)p->payload;
+      msg_ptr += ofs - base;
+
+      if (length < 0x80)
+      {
+        *msg_ptr = (u8_t)length;
+        return ERR_OK;
+      }
+      else if (length < 0x100)
+      {
+        *msg_ptr = 0x81;
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = (u8_t*)p->payload;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+        *msg_ptr = (u8_t)length;
+        return ERR_OK;
+      }
+      else
+      {
+        u8_t i;
+
+        /* length >= 0x100 && length <= 0xFFFF */
+        *msg_ptr = 0x82;
+        i = 2;
+        while (i > 0)
+        {
+          i--;
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = (u8_t*)p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+          if (i == 0)
+          {
+            /* least significant length octet */
+            *msg_ptr = (u8_t)length;
+          }
+          else
+          {
+            /* most significant length octet */
+            *msg_ptr = (u8_t)(length >> 8);
+          }
+        }
+        return ERR_OK;
+      }
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Encodes u32_t (counter, gauge, timeticks) into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode value into
+ * @param ofs points to the offset within the pbuf chain
+ * @param octets_needed encoding length (from snmp_asn1_enc_u32t_cnt())
+ * @param value is the host order u32_t value to be encoded
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ *
+ * @see snmp_asn1_enc_u32t_cnt()
+ */
+err_t
+snmp_asn1_enc_u32t(struct pbuf *p, u16_t ofs, u16_t octets_needed, u32_t value)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = (u8_t*)p->payload;
+      msg_ptr += ofs - base;
+
+      if (octets_needed == 5)
+      {
+        /* not enough bits in 'value' add leading 0x00 */
+        octets_needed--;
+        *msg_ptr = 0x00;
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = (u8_t*)p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+      }
+      while (octets_needed > 1)
+      {
+        octets_needed--;
+        *msg_ptr = (u8_t)(value >> (octets_needed << 3));
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = (u8_t*)p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+      }
+      /* (only) one least significant octet */
+      *msg_ptr = (u8_t)value;
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Encodes s32_t integer into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode value into
+ * @param ofs points to the offset within the pbuf chain
+ * @param octets_needed encoding length (from snmp_asn1_enc_s32t_cnt())
+ * @param value is the host order s32_t value to be encoded
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ *
+ * @see snmp_asn1_enc_s32t_cnt()
+ */
+err_t
+snmp_asn1_enc_s32t(struct pbuf *p, u16_t ofs, u16_t octets_needed, s32_t value)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = (u8_t*)p->payload;
+      msg_ptr += ofs - base;
+
+      while (octets_needed > 1)
+      {
+        octets_needed--;
+        *msg_ptr = (u8_t)(value >> (octets_needed << 3));
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = (u8_t*)p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+      }
+      /* (only) one least significant octet */
+      *msg_ptr = (u8_t)value;
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Encodes object identifier into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode oid into
+ * @param ofs points to the offset within the pbuf chain
+ * @param ident_len object identifier array length
+ * @param ident points to object identifier array
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ */
+err_t
+snmp_asn1_enc_oid(struct pbuf *p, u16_t ofs, u8_t ident_len, s32_t *ident)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = (u8_t*)p->payload;
+      msg_ptr += ofs - base;
+
+      if (ident_len > 1)
+      {
+        if ((ident[0] == 1) && (ident[1] == 3))
+        {
+          /* compressed (most common) prefix .iso.org */
+          *msg_ptr = 0x2b;
+        }
+        else
+        {
+          /* calculate prefix */
+          *msg_ptr = (u8_t)((ident[0] * 40) + ident[1]);
+        }
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = (u8_t*)p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+        ident_len -= 2;
+        ident += 2;
+      }
+      else
+      {
+/* @bug:  allow empty varbinds for symmetry (we must decode them for getnext), allow partial compression??  */
+        /* ident_len <= 1, at least we need zeroDotZero (0.0) (ident_len == 2) */
+        return ERR_ARG;
+      }
+      while (ident_len > 0)
+      {
+        s32_t sub_id;
+        u8_t shift, tail;
+
+        ident_len--;
+        sub_id = *ident;
+        tail = 0;
+        shift = 28;
+        while(shift > 0)
+        {
+          u8_t code;
+
+          code = (u8_t)(sub_id >> shift);
+          if ((code != 0) || (tail != 0))
+          {
+            tail = 1;
+            *msg_ptr = code | 0x80;
+            ofs += 1;
+            if (ofs >= plen)
+            {
+              /* next octet in next pbuf */
+              p = p->next;
+              if (p == NULL) { return ERR_ARG; }
+              msg_ptr = (u8_t*)p->payload;
+              plen += p->len;
+            }
+            else
+            {
+              /* next octet in same pbuf */
+              msg_ptr++;
+            }
+          }
+          shift -= 7;
+        }
+        *msg_ptr = (u8_t)sub_id & 0x7F;
+        if (ident_len > 0)
+        {
+          ofs += 1;
+          if (ofs >= plen)
+          {
+            /* next octet in next pbuf */
+            p = p->next;
+            if (p == NULL) { return ERR_ARG; }
+            msg_ptr = (u8_t*)p->payload;
+            plen += p->len;
+          }
+          else
+          {
+            /* next octet in same pbuf */
+            msg_ptr++;
+          }
+        }
+        /* proceed to next sub-identifier */
+        ident++;
+      }
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+/**
+ * Encodes raw data (octet string, opaque) into a pbuf chained ASN1 msg.
+ *
+ * @param p points to output pbuf to encode raw data into
+ * @param ofs points to the offset within the pbuf chain
+ * @param raw_len raw data length
+ * @param raw points raw data
+ * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode
+ */
+err_t
+snmp_asn1_enc_raw(struct pbuf *p, u16_t ofs, u16_t raw_len, u8_t *raw)
+{
+  u16_t plen, base;
+  u8_t *msg_ptr;
+
+  plen = 0;
+  while (p != NULL)
+  {
+    base = plen;
+    plen += p->len;
+    if (ofs < plen)
+    {
+      msg_ptr = (u8_t*)p->payload;
+      msg_ptr += ofs - base;
+
+      while (raw_len > 1)
+      {
+        /* copy raw_len - 1 octets */
+        raw_len--;
+        *msg_ptr = *raw;
+        raw++;
+        ofs += 1;
+        if (ofs >= plen)
+        {
+          /* next octet in next pbuf */
+          p = p->next;
+          if (p == NULL) { return ERR_ARG; }
+          msg_ptr = (u8_t*)p->payload;
+          plen += p->len;
+        }
+        else
+        {
+          /* next octet in same pbuf */
+          msg_ptr++;
+        }
+      }
+      if (raw_len > 0)
+      {
+        /* copy last or single octet */
+        *msg_ptr = *raw;
+      }
+      return ERR_OK;
+    }
+    p = p->next;
+  }
+  /* p == NULL, ofs >= plen */
+  return ERR_ARG;
+}
+
+#endif /* LWIP_SNMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/snmp/mib2.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/snmp/mib2.c
new file mode 100644
index 0000000..29decd3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/snmp/mib2.c
@@ -0,0 +1,4146 @@
+/**
+ * @file
+ * Management Information Base II (RFC1213) objects and functions.
+ *
+ * @note the object identifiers for this MIB-2 and private MIB tree
+ * must be kept in sorted ascending order. This to ensure correct getnext operation.
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/snmp.h"
+#include "lwip/netif.h"
+#include "lwip/ip.h"
+#include "lwip/ip_frag.h"
+#include "lwip/mem.h"
+#include "lwip/tcp_impl.h"
+#include "lwip/udp.h"
+#include "lwip/snmp_asn1.h"
+#include "lwip/snmp_structs.h"
+#include "lwip/sys.h"
+#include "netif/etharp.h"
+
+/**
+ * IANA assigned enterprise ID for lwIP is 26381
+ * @see http://www.iana.org/assignments/enterprise-numbers
+ *
+ * @note this enterprise ID is assigned to the lwIP project,
+ * all object identifiers living under this ID are assigned
+ * by the lwIP maintainers (contact Christiaan Simons)!
+ * @note don't change this define, use snmp_set_sysobjid()
+ *
+ * If you need to create your own private MIB you'll need
+ * to apply for your own enterprise ID with IANA:
+ * http://www.iana.org/numbers.html
+ */
+#define SNMP_ENTERPRISE_ID 26381
+#define SNMP_SYSOBJID_LEN 7
+#define SNMP_SYSOBJID {1, 3, 6, 1, 4, 1, SNMP_ENTERPRISE_ID}
+
+#ifndef SNMP_SYSSERVICES
+#define SNMP_SYSSERVICES ((1 << 6) | (1 << 3) | ((IP_FORWARD) << 2))
+#endif
+
+#ifndef SNMP_GET_SYSUPTIME
+#define SNMP_GET_SYSUPTIME(sysuptime)
+#endif
+
+static void system_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void system_get_value(struct obj_def *od, u16_t len, void *value);
+static u8_t system_set_test(struct obj_def *od, u16_t len, void *value);
+static void system_set_value(struct obj_def *od, u16_t len, void *value);
+static void interfaces_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void interfaces_get_value(struct obj_def *od, u16_t len, void *value);
+static void ifentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void ifentry_get_value(struct obj_def *od, u16_t len, void *value);
+#if !SNMP_SAFE_REQUESTS
+static u8_t ifentry_set_test (struct obj_def *od, u16_t len, void *value);
+static void ifentry_set_value (struct obj_def *od, u16_t len, void *value);
+#endif /* SNMP_SAFE_REQUESTS */
+static void atentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void atentry_get_value(struct obj_def *od, u16_t len, void *value);
+static void ip_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void ip_get_value(struct obj_def *od, u16_t len, void *value);
+static u8_t ip_set_test(struct obj_def *od, u16_t len, void *value);
+static void ip_addrentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void ip_addrentry_get_value(struct obj_def *od, u16_t len, void *value);
+static void ip_rteentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void ip_rteentry_get_value(struct obj_def *od, u16_t len, void *value);
+static void ip_ntomentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void ip_ntomentry_get_value(struct obj_def *od, u16_t len, void *value);
+static void icmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void icmp_get_value(struct obj_def *od, u16_t len, void *value);
+#if LWIP_TCP
+static void tcp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void tcp_get_value(struct obj_def *od, u16_t len, void *value);
+#ifdef THIS_SEEMS_UNUSED
+static void tcpconnentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void tcpconnentry_get_value(struct obj_def *od, u16_t len, void *value);
+#endif
+#endif
+static void udp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void udp_get_value(struct obj_def *od, u16_t len, void *value);
+static void udpentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void udpentry_get_value(struct obj_def *od, u16_t len, void *value);
+static void snmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+static void snmp_get_value(struct obj_def *od, u16_t len, void *value);
+static u8_t snmp_set_test(struct obj_def *od, u16_t len, void *value);
+static void snmp_set_value(struct obj_def *od, u16_t len, void *value);
+
+
+/* snmp .1.3.6.1.2.1.11 */
+const mib_scalar_node snmp_scalar = {
+  &snmp_get_object_def,
+  &snmp_get_value,
+  &snmp_set_test,
+  &snmp_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t snmp_ids[28] = {
+  1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+  17, 18, 19, 20, 21, 22, 24, 25, 26, 27, 28, 29, 30
+};
+struct mib_node* const snmp_nodes[28] = {
+  (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar,
+  (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar,
+  (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar,
+  (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar,
+  (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar,
+  (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar,
+  (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar,
+  (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar,
+  (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar,
+  (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar,
+  (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar,
+  (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar,
+  (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar,
+  (struct mib_node*)&snmp_scalar, (struct mib_node*)&snmp_scalar
+};
+const struct mib_array_node snmp = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  28,
+  snmp_ids,
+  snmp_nodes
+};
+
+/* dot3 and EtherLike MIB not planned. (transmission .1.3.6.1.2.1.10) */
+/* historical (some say hysterical). (cmot .1.3.6.1.2.1.9) */
+/* lwIP has no EGP, thus may not implement it. (egp .1.3.6.1.2.1.8) */
+
+/* udp .1.3.6.1.2.1.7 */
+/** index root node for udpTable */
+struct mib_list_rootnode udp_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t udpentry_ids[2] = { 1, 2 };
+struct mib_node* const udpentry_nodes[2] = {
+  (struct mib_node*)&udp_root, (struct mib_node*)&udp_root,
+};
+const struct mib_array_node udpentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  2,
+  udpentry_ids,
+  udpentry_nodes
+};
+
+s32_t udptable_id = 1;
+struct mib_node* udptable_node = (struct mib_node*)&udpentry;
+struct mib_ram_array_node udptable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &udptable_id,
+  &udptable_node
+};
+
+const mib_scalar_node udp_scalar = {
+  &udp_get_object_def,
+  &udp_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t udp_ids[5] = { 1, 2, 3, 4, 5 };
+struct mib_node* const udp_nodes[5] = {
+  (struct mib_node*)&udp_scalar, (struct mib_node*)&udp_scalar,
+  (struct mib_node*)&udp_scalar, (struct mib_node*)&udp_scalar,
+  (struct mib_node*)&udptable
+};
+const struct mib_array_node udp = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  5,
+  udp_ids,
+  udp_nodes
+};
+
+/* tcp .1.3.6.1.2.1.6 */
+#if LWIP_TCP
+/* only if the TCP protocol is available may implement this group */
+/** index root node for tcpConnTable */
+struct mib_list_rootnode tcpconntree_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t tcpconnentry_ids[5] = { 1, 2, 3, 4, 5 };
+struct mib_node* const tcpconnentry_nodes[5] = {
+  (struct mib_node*)&tcpconntree_root, (struct mib_node*)&tcpconntree_root,
+  (struct mib_node*)&tcpconntree_root, (struct mib_node*)&tcpconntree_root,
+  (struct mib_node*)&tcpconntree_root
+};
+const struct mib_array_node tcpconnentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  5,
+  tcpconnentry_ids,
+  tcpconnentry_nodes
+};
+
+s32_t tcpconntable_id = 1;
+struct mib_node* tcpconntable_node = (struct mib_node*)&tcpconnentry;
+struct mib_ram_array_node tcpconntable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+/** @todo update maxlength when inserting / deleting from table
+   0 when table is empty, 1 when more than one entry */
+  0,
+  &tcpconntable_id,
+  &tcpconntable_node
+};
+
+const mib_scalar_node tcp_scalar = {
+  &tcp_get_object_def,
+  &tcp_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t tcp_ids[15] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
+struct mib_node* const tcp_nodes[15] = {
+  (struct mib_node*)&tcp_scalar, (struct mib_node*)&tcp_scalar,
+  (struct mib_node*)&tcp_scalar, (struct mib_node*)&tcp_scalar,
+  (struct mib_node*)&tcp_scalar, (struct mib_node*)&tcp_scalar,
+  (struct mib_node*)&tcp_scalar, (struct mib_node*)&tcp_scalar,
+  (struct mib_node*)&tcp_scalar, (struct mib_node*)&tcp_scalar,
+  (struct mib_node*)&tcp_scalar, (struct mib_node*)&tcp_scalar,
+  (struct mib_node*)&tcpconntable, (struct mib_node*)&tcp_scalar,
+  (struct mib_node*)&tcp_scalar
+};
+const struct mib_array_node tcp = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  15,
+  tcp_ids,
+  tcp_nodes
+};
+#endif
+
+/* icmp .1.3.6.1.2.1.5 */
+const mib_scalar_node icmp_scalar = {
+  &icmp_get_object_def,
+  &icmp_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t icmp_ids[26] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 };
+struct mib_node* const icmp_nodes[26] = {
+  (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar,
+  (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar,
+  (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar,
+  (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar,
+  (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar,
+  (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar,
+  (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar,
+  (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar,
+  (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar,
+  (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar,
+  (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar,
+  (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar,
+  (struct mib_node*)&icmp_scalar, (struct mib_node*)&icmp_scalar
+};
+const struct mib_array_node icmp = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  26,
+  icmp_ids,
+  icmp_nodes
+};
+
+/** index root node for ipNetToMediaTable */
+struct mib_list_rootnode ipntomtree_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t ipntomentry_ids[4] = { 1, 2, 3, 4 };
+struct mib_node* const ipntomentry_nodes[4] = {
+  (struct mib_node*)&ipntomtree_root, (struct mib_node*)&ipntomtree_root,
+  (struct mib_node*)&ipntomtree_root, (struct mib_node*)&ipntomtree_root
+};
+const struct mib_array_node ipntomentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  4,
+  ipntomentry_ids,
+  ipntomentry_nodes
+};
+
+s32_t ipntomtable_id = 1;
+struct mib_node* ipntomtable_node = (struct mib_node*)&ipntomentry;
+struct mib_ram_array_node ipntomtable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &ipntomtable_id,
+  &ipntomtable_node
+};
+
+/** index root node for ipRouteTable */
+struct mib_list_rootnode iprtetree_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t iprteentry_ids[13] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 };
+struct mib_node* const iprteentry_nodes[13] = {
+  (struct mib_node*)&iprtetree_root, (struct mib_node*)&iprtetree_root,
+  (struct mib_node*)&iprtetree_root, (struct mib_node*)&iprtetree_root,
+  (struct mib_node*)&iprtetree_root, (struct mib_node*)&iprtetree_root,
+  (struct mib_node*)&iprtetree_root, (struct mib_node*)&iprtetree_root,
+  (struct mib_node*)&iprtetree_root, (struct mib_node*)&iprtetree_root,
+  (struct mib_node*)&iprtetree_root, (struct mib_node*)&iprtetree_root,
+  (struct mib_node*)&iprtetree_root
+};
+const struct mib_array_node iprteentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  13,
+  iprteentry_ids,
+  iprteentry_nodes
+};
+
+s32_t iprtetable_id = 1;
+struct mib_node* iprtetable_node = (struct mib_node*)&iprteentry;
+struct mib_ram_array_node iprtetable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &iprtetable_id,
+  &iprtetable_node
+};
+
+/** index root node for ipAddrTable */
+struct mib_list_rootnode ipaddrtree_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t ipaddrentry_ids[5] = { 1, 2, 3, 4, 5 };
+struct mib_node* const ipaddrentry_nodes[5] = {
+  (struct mib_node*)&ipaddrtree_root,
+  (struct mib_node*)&ipaddrtree_root,
+  (struct mib_node*)&ipaddrtree_root,
+  (struct mib_node*)&ipaddrtree_root,
+  (struct mib_node*)&ipaddrtree_root
+};
+const struct mib_array_node ipaddrentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  5,
+  ipaddrentry_ids,
+  ipaddrentry_nodes
+};
+
+s32_t ipaddrtable_id = 1;
+struct mib_node* ipaddrtable_node = (struct mib_node*)&ipaddrentry;
+struct mib_ram_array_node ipaddrtable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &ipaddrtable_id,
+  &ipaddrtable_node
+};
+
+/* ip .1.3.6.1.2.1.4 */
+const mib_scalar_node ip_scalar = {
+  &ip_get_object_def,
+  &ip_get_value,
+  &ip_set_test,
+  &noleafs_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t ip_ids[23] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 };
+struct mib_node* const ip_nodes[23] = {
+  (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar,
+  (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar,
+  (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar,
+  (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar,
+  (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar,
+  (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar,
+  (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar,
+  (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar,
+  (struct mib_node*)&ip_scalar, (struct mib_node*)&ip_scalar,
+  (struct mib_node*)&ip_scalar, (struct mib_node*)&ipaddrtable,
+  (struct mib_node*)&iprtetable, (struct mib_node*)&ipntomtable,
+  (struct mib_node*)&ip_scalar
+};
+const struct mib_array_node mib2_ip = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  23,
+  ip_ids,
+  ip_nodes
+};
+
+/** index root node for atTable */
+struct mib_list_rootnode arptree_root = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t atentry_ids[3] = { 1, 2, 3 };
+struct mib_node* const atentry_nodes[3] = {
+  (struct mib_node*)&arptree_root,
+  (struct mib_node*)&arptree_root,
+  (struct mib_node*)&arptree_root
+};
+const struct mib_array_node atentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  3,
+  atentry_ids,
+  atentry_nodes
+};
+
+const s32_t attable_id = 1;
+struct mib_node* const attable_node = (struct mib_node*)&atentry;
+const struct mib_array_node attable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  1,
+  &attable_id,
+  &attable_node
+};
+
+/* at .1.3.6.1.2.1.3 */
+s32_t at_id = 1;
+struct mib_node* mib2_at_node = (struct mib_node*)&attable;
+struct mib_ram_array_node at = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &at_id,
+  &mib2_at_node
+};
+
+/** index root node for ifTable */
+struct mib_list_rootnode iflist_root = {
+  &ifentry_get_object_def,
+  &ifentry_get_value,
+#if SNMP_SAFE_REQUESTS
+  &noleafs_set_test,
+  &noleafs_set_value,
+#else /* SNMP_SAFE_REQUESTS */
+  &ifentry_set_test,
+  &ifentry_set_value,
+#endif /* SNMP_SAFE_REQUESTS */
+  MIB_NODE_LR,
+  0,
+  NULL,
+  NULL,
+  0
+};
+const s32_t ifentry_ids[22] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 };
+struct mib_node* const ifentry_nodes[22] = {
+  (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root,
+  (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root,
+  (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root,
+  (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root,
+  (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root,
+  (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root,
+  (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root,
+  (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root,
+  (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root,
+  (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root,
+  (struct mib_node*)&iflist_root, (struct mib_node*)&iflist_root
+};
+const struct mib_array_node ifentry = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  22,
+  ifentry_ids,
+  ifentry_nodes
+};
+
+s32_t iftable_id = 1;
+struct mib_node* iftable_node = (struct mib_node*)&ifentry;
+struct mib_ram_array_node iftable = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_RA,
+  0,
+  &iftable_id,
+  &iftable_node
+};
+
+/* interfaces .1.3.6.1.2.1.2 */
+const mib_scalar_node interfaces_scalar = {
+  &interfaces_get_object_def,
+  &interfaces_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t interfaces_ids[2] = { 1, 2 };
+struct mib_node* const interfaces_nodes[2] = {
+  (struct mib_node*)&interfaces_scalar, (struct mib_node*)&iftable
+};
+const struct mib_array_node interfaces = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  2,
+  interfaces_ids,
+  interfaces_nodes
+};
+
+
+/*             0 1 2 3 4 5 6 */
+/* system .1.3.6.1.2.1.1 */
+const mib_scalar_node sys_tem_scalar = {
+  &system_get_object_def,
+  &system_get_value,
+  &system_set_test,
+  &system_set_value,
+  MIB_NODE_SC,
+  0
+};
+const s32_t sys_tem_ids[7] = { 1, 2, 3, 4, 5, 6, 7 };
+struct mib_node* const sys_tem_nodes[7] = {
+  (struct mib_node*)&sys_tem_scalar, (struct mib_node*)&sys_tem_scalar,
+  (struct mib_node*)&sys_tem_scalar, (struct mib_node*)&sys_tem_scalar,
+  (struct mib_node*)&sys_tem_scalar, (struct mib_node*)&sys_tem_scalar,
+  (struct mib_node*)&sys_tem_scalar
+};
+/* work around name issue with 'sys_tem', some compiler(s?) seem to reserve 'system' */
+const struct mib_array_node sys_tem = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  7,
+  sys_tem_ids,
+  sys_tem_nodes
+};
+
+/* mib-2 .1.3.6.1.2.1 */
+#if LWIP_TCP
+#define MIB2_GROUPS 8
+#else
+#define MIB2_GROUPS 7
+#endif
+const s32_t mib2_ids[MIB2_GROUPS] =
+{
+  1,
+  2,
+  3,
+  4,
+  5,
+#if LWIP_TCP
+  6,
+#endif
+  7,
+  11
+};
+struct mib_node* const mib2_nodes[MIB2_GROUPS] = {
+  (struct mib_node*)&sys_tem,
+  (struct mib_node*)&interfaces,
+  (struct mib_node*)&at,
+  (struct mib_node*)&mib2_ip,
+  (struct mib_node*)&icmp,
+#if LWIP_TCP
+  (struct mib_node*)&tcp,
+#endif
+  (struct mib_node*)&udp,
+  (struct mib_node*)&snmp
+};
+
+const struct mib_array_node mib2 = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  MIB2_GROUPS,
+  mib2_ids,
+  mib2_nodes
+};
+
+/* mgmt .1.3.6.1.2 */
+const s32_t mgmt_ids[1] = { 1 };
+struct mib_node* const mgmt_nodes[1] = { (struct mib_node*)&mib2 };
+const struct mib_array_node mgmt = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  1,
+  mgmt_ids,
+  mgmt_nodes
+};
+
+/* internet .1.3.6.1 */
+#if SNMP_PRIVATE_MIB
+/* When using a private MIB, you have to create a file 'private_mib.h' that contains
+ * a 'struct mib_array_node mib_private' which contains your MIB. */
+s32_t internet_ids[2] = { 2, 4 };
+struct mib_node* const internet_nodes[2] = { (struct mib_node*)&mgmt, (struct mib_node*)&mib_private };
+const struct mib_array_node internet = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  2,
+  internet_ids,
+  internet_nodes
+};
+#else
+const s32_t internet_ids[1] = { 2 };
+struct mib_node* const internet_nodes[1] = { (struct mib_node*)&mgmt };
+const struct mib_array_node internet = {
+  &noleafs_get_object_def,
+  &noleafs_get_value,
+  &noleafs_set_test,
+  &noleafs_set_value,
+  MIB_NODE_AR,
+  1,
+  internet_ids,
+  internet_nodes
+};
+#endif
+
+/** mib-2.system.sysObjectID  */
+static struct snmp_obj_id sysobjid = {SNMP_SYSOBJID_LEN, SNMP_SYSOBJID};
+/** enterprise ID for generic TRAPs, .iso.org.dod.internet.mgmt.mib-2.snmp */
+static struct snmp_obj_id snmpgrp_id = {7,{1,3,6,1,2,1,11}};
+/** mib-2.system.sysServices */
+static const s32_t sysservices = SNMP_SYSSERVICES;
+
+/** mib-2.system.sysDescr */
+static const u8_t sysdescr_len_default = 4;
+static const u8_t sysdescr_default[] = "lwIP";
+static u8_t* sysdescr_len_ptr = (u8_t*)&sysdescr_len_default;
+static u8_t* sysdescr_ptr = (u8_t*)&sysdescr_default[0];
+/** mib-2.system.sysContact */
+static const u8_t syscontact_len_default = 0;
+static const u8_t syscontact_default[] = "";
+static u8_t* syscontact_len_ptr = (u8_t*)&syscontact_len_default;
+static u8_t* syscontact_ptr = (u8_t*)&syscontact_default[0];
+/** mib-2.system.sysName */
+static const u8_t sysname_len_default = 8;
+static const u8_t sysname_default[] = "FQDN-unk";
+static u8_t* sysname_len_ptr = (u8_t*)&sysname_len_default;
+static u8_t* sysname_ptr = (u8_t*)&sysname_default[0];
+/** mib-2.system.sysLocation */
+static const u8_t syslocation_len_default = 0;
+static const u8_t syslocation_default[] = "";
+static u8_t* syslocation_len_ptr = (u8_t*)&syslocation_len_default;
+static u8_t* syslocation_ptr = (u8_t*)&syslocation_default[0];
+/** mib-2.snmp.snmpEnableAuthenTraps */
+static const u8_t snmpenableauthentraps_default = 2; /* disabled */
+static u8_t* snmpenableauthentraps_ptr = (u8_t*)&snmpenableauthentraps_default;
+
+/** mib-2.interfaces.ifTable.ifEntry.ifSpecific (zeroDotZero) */
+static const struct snmp_obj_id ifspecific = {2, {0, 0}};
+/** mib-2.ip.ipRouteTable.ipRouteEntry.ipRouteInfo (zeroDotZero) */
+static const struct snmp_obj_id iprouteinfo = {2, {0, 0}};
+
+
+
+/* mib-2.system counter(s) */
+static u32_t sysuptime = 0;
+
+/* mib-2.ip counter(s) */
+static u32_t ipinreceives = 0,
+             ipinhdrerrors = 0,
+             ipinaddrerrors = 0,
+             ipforwdatagrams = 0,
+             ipinunknownprotos = 0,
+             ipindiscards = 0,
+             ipindelivers = 0,
+             ipoutrequests = 0,
+             ipoutdiscards = 0,
+             ipoutnoroutes = 0,
+             ipreasmreqds = 0,
+             ipreasmoks = 0,
+             ipreasmfails = 0,
+             ipfragoks = 0,
+             ipfragfails = 0,
+             ipfragcreates = 0,
+             iproutingdiscards = 0;
+/* mib-2.icmp counter(s) */
+static u32_t icmpinmsgs = 0,
+             icmpinerrors = 0,
+             icmpindestunreachs = 0,
+             icmpintimeexcds = 0,
+             icmpinparmprobs = 0,
+             icmpinsrcquenchs = 0,
+             icmpinredirects = 0,
+             icmpinechos = 0,
+             icmpinechoreps = 0,
+             icmpintimestamps = 0,
+             icmpintimestampreps = 0,
+             icmpinaddrmasks = 0,
+             icmpinaddrmaskreps = 0,
+             icmpoutmsgs = 0,
+             icmpouterrors = 0,
+             icmpoutdestunreachs = 0,
+             icmpouttimeexcds = 0,
+             icmpoutparmprobs = 0,
+             icmpoutsrcquenchs = 0,
+             icmpoutredirects = 0,
+             icmpoutechos = 0,
+             icmpoutechoreps = 0,
+             icmpouttimestamps = 0,
+             icmpouttimestampreps = 0,
+             icmpoutaddrmasks = 0,
+             icmpoutaddrmaskreps = 0;
+/* mib-2.tcp counter(s) */
+static u32_t tcpactiveopens = 0,
+             tcppassiveopens = 0,
+             tcpattemptfails = 0,
+             tcpestabresets = 0,
+             tcpinsegs = 0,
+             tcpoutsegs = 0,
+             tcpretranssegs = 0,
+             tcpinerrs = 0,
+             tcpoutrsts = 0;
+/* mib-2.udp counter(s) */
+static u32_t udpindatagrams = 0,
+             udpnoports = 0,
+             udpinerrors = 0,
+             udpoutdatagrams = 0;
+/* mib-2.snmp counter(s) */
+static u32_t snmpinpkts = 0,
+             snmpoutpkts = 0,
+             snmpinbadversions = 0,
+             snmpinbadcommunitynames = 0,
+             snmpinbadcommunityuses = 0,
+             snmpinasnparseerrs = 0,
+             snmpintoobigs = 0,
+             snmpinnosuchnames = 0,
+             snmpinbadvalues = 0,
+             snmpinreadonlys = 0,
+             snmpingenerrs = 0,
+             snmpintotalreqvars = 0,
+             snmpintotalsetvars = 0,
+             snmpingetrequests = 0,
+             snmpingetnexts = 0,
+             snmpinsetrequests = 0,
+             snmpingetresponses = 0,
+             snmpintraps = 0,
+             snmpouttoobigs = 0,
+             snmpoutnosuchnames = 0,
+             snmpoutbadvalues = 0,
+             snmpoutgenerrs = 0,
+             snmpoutgetrequests = 0,
+             snmpoutgetnexts = 0,
+             snmpoutsetrequests = 0,
+             snmpoutgetresponses = 0,
+             snmpouttraps = 0;
+
+
+
+/* prototypes of the following functions are in lwip/src/include/lwip/snmp.h */
+/**
+ * Copy octet string.
+ *
+ * @param dst points to destination
+ * @param src points to source
+ * @param n number of octets to copy.
+ */
+static void ocstrncpy(u8_t *dst, u8_t *src, u16_t n)
+{
+  u16_t i = n;
+  while (i > 0) {
+    i--;
+    *dst++ = *src++;
+  }
+}
+
+/**
+ * Copy object identifier (s32_t) array.
+ *
+ * @param dst points to destination
+ * @param src points to source
+ * @param n number of sub identifiers to copy.
+ */
+void objectidncpy(s32_t *dst, s32_t *src, u8_t n)
+{
+  u8_t i = n;
+  while(i > 0) {
+    i--;
+    *dst++ = *src++;
+  }
+}
+
+/**
+ * Initializes sysDescr pointers.
+ *
+ * @param str if non-NULL then copy str pointer
+ * @param len points to string length, excluding zero terminator
+ */
+void snmp_set_sysdesr(u8_t *str, u8_t *len)
+{
+  if (str != NULL)
+  {
+    sysdescr_ptr = str;
+    sysdescr_len_ptr = len;
+  }
+}
+
+void snmp_get_sysobjid_ptr(struct snmp_obj_id **oid)
+{
+  *oid = &sysobjid;
+}
+
+/**
+ * Initializes sysObjectID value.
+ *
+ * @param oid points to stuct snmp_obj_id to copy
+ */
+void snmp_set_sysobjid(struct snmp_obj_id *oid)
+{
+  sysobjid = *oid;
+}
+
+/**
+ * Must be called at regular 10 msec interval from a timer interrupt
+ * or signal handler depending on your runtime environment.
+ */
+void snmp_inc_sysuptime(void)
+{
+  sysuptime++;
+}
+
+void snmp_add_sysuptime(u32_t value)
+{
+  sysuptime+=value;
+}
+
+void snmp_get_sysuptime(u32_t *value)
+{
+  SNMP_GET_SYSUPTIME(sysuptime);
+  *value = sysuptime;
+}
+
+/**
+ * Initializes sysContact pointers,
+ * e.g. ptrs to non-volatile memory external to lwIP.
+ *
+ * @param ocstr if non-NULL then copy str pointer
+ * @param ocstrlen points to string length, excluding zero terminator
+ */
+void snmp_set_syscontact(u8_t *ocstr, u8_t *ocstrlen)
+{
+  if (ocstr != NULL)
+  {
+    syscontact_ptr = ocstr;
+    syscontact_len_ptr = ocstrlen;
+  }
+}
+
+/**
+ * Initializes sysName pointers,
+ * e.g. ptrs to non-volatile memory external to lwIP.
+ *
+ * @param ocstr if non-NULL then copy str pointer
+ * @param ocstrlen points to string length, excluding zero terminator
+ */
+void snmp_set_sysname(u8_t *ocstr, u8_t *ocstrlen)
+{
+  if (ocstr != NULL)
+  {
+    sysname_ptr = ocstr;
+    sysname_len_ptr = ocstrlen;
+  }
+}
+
+/**
+ * Initializes sysLocation pointers,
+ * e.g. ptrs to non-volatile memory external to lwIP.
+ *
+ * @param ocstr if non-NULL then copy str pointer
+ * @param ocstrlen points to string length, excluding zero terminator
+ */
+void snmp_set_syslocation(u8_t *ocstr, u8_t *ocstrlen)
+{
+  if (ocstr != NULL)
+  {
+    syslocation_ptr = ocstr;
+    syslocation_len_ptr = ocstrlen;
+  }
+}
+
+
+void snmp_add_ifinoctets(struct netif *ni, u32_t value)
+{
+  ni->ifinoctets += value;
+}
+
+void snmp_inc_ifinucastpkts(struct netif *ni)
+{
+  (ni->ifinucastpkts)++;
+}
+
+void snmp_inc_ifinnucastpkts(struct netif *ni)
+{
+  (ni->ifinnucastpkts)++;
+}
+
+void snmp_inc_ifindiscards(struct netif *ni)
+{
+  (ni->ifindiscards)++;
+}
+
+void snmp_add_ifoutoctets(struct netif *ni, u32_t value)
+{
+  ni->ifoutoctets += value;
+}
+
+void snmp_inc_ifoutucastpkts(struct netif *ni)
+{
+  (ni->ifoutucastpkts)++;
+}
+
+void snmp_inc_ifoutnucastpkts(struct netif *ni)
+{
+  (ni->ifoutnucastpkts)++;
+}
+
+void snmp_inc_ifoutdiscards(struct netif *ni)
+{
+  (ni->ifoutdiscards)++;
+}
+
+void snmp_inc_iflist(void)
+{
+  struct mib_list_node *if_node = NULL;
+
+  snmp_mib_node_insert(&iflist_root, iflist_root.count + 1, &if_node);
+  /* enable getnext traversal on filled table */
+  iftable.maxlength = 1;
+}
+
+void snmp_dec_iflist(void)
+{
+  snmp_mib_node_delete(&iflist_root, iflist_root.tail);
+  /* disable getnext traversal on empty table */
+  if(iflist_root.count == 0) iftable.maxlength = 0;
+}
+
+/**
+ * Inserts ARP table indexes (.xIfIndex.xNetAddress)
+ * into arp table index trees (both atTable and ipNetToMediaTable).
+ */
+void snmp_insert_arpidx_tree(struct netif *ni, ip_addr_t *ip)
+{
+  struct mib_list_rootnode *at_rn;
+  struct mib_list_node *at_node;
+  s32_t arpidx[5];
+  u8_t level, tree;
+
+  LWIP_ASSERT("ni != NULL", ni != NULL);
+  snmp_netiftoifindex(ni, &arpidx[0]);
+  snmp_iptooid(ip, &arpidx[1]);
+
+  for (tree = 0; tree < 2; tree++)
+  {
+    if (tree == 0)
+    {
+      at_rn = &arptree_root;
+    }
+    else
+    {
+      at_rn = &ipntomtree_root;
+    }
+    for (level = 0; level < 5; level++)
+    {
+      at_node = NULL;
+      snmp_mib_node_insert(at_rn, arpidx[level], &at_node);
+      if ((level != 4) && (at_node != NULL))
+      {
+        if (at_node->nptr == NULL)
+        {
+          at_rn = snmp_mib_lrn_alloc();
+          at_node->nptr = (struct mib_node*)at_rn;
+          if (at_rn != NULL)
+          {
+            if (level == 3)
+            {
+              if (tree == 0)
+              {
+                at_rn->get_object_def = atentry_get_object_def;
+                at_rn->get_value = atentry_get_value;
+              }
+              else
+              {
+                at_rn->get_object_def = ip_ntomentry_get_object_def;
+                at_rn->get_value = ip_ntomentry_get_value;
+              }
+              at_rn->set_test = noleafs_set_test;
+              at_rn->set_value = noleafs_set_value;
+            }
+          }
+          else
+          {
+            /* at_rn == NULL, malloc failure */
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_arpidx_tree() insert failed, mem full"));
+            break;
+          }
+        }
+        else
+        {
+          at_rn = (struct mib_list_rootnode*)at_node->nptr;
+        }
+      }
+    }
+  }
+  /* enable getnext traversal on filled tables */
+  at.maxlength = 1;
+  ipntomtable.maxlength = 1;
+}
+
+/**
+ * Removes ARP table indexes (.xIfIndex.xNetAddress)
+ * from arp table index trees.
+ */
+void snmp_delete_arpidx_tree(struct netif *ni, ip_addr_t *ip)
+{
+  struct mib_list_rootnode *at_rn, *next, *del_rn[5];
+  struct mib_list_node *at_n, *del_n[5];
+  s32_t arpidx[5];
+  u8_t fc, tree, level, del_cnt;
+
+  snmp_netiftoifindex(ni, &arpidx[0]);
+  snmp_iptooid(ip, &arpidx[1]);
+
+  for (tree = 0; tree < 2; tree++)
+  {
+    /* mark nodes for deletion */
+    if (tree == 0)
+    {
+      at_rn = &arptree_root;
+    }
+    else
+    {
+      at_rn = &ipntomtree_root;
+    }
+    level = 0;
+    del_cnt = 0;
+    while ((level < 5) && (at_rn != NULL))
+    {
+      fc = snmp_mib_node_find(at_rn, arpidx[level], &at_n);
+      if (fc == 0)
+      {
+        /* arpidx[level] does not exist */
+        del_cnt = 0;
+        at_rn = NULL;
+      }
+      else if (fc == 1)
+      {
+        del_rn[del_cnt] = at_rn;
+        del_n[del_cnt] = at_n;
+        del_cnt++;
+        at_rn = (struct mib_list_rootnode*)(at_n->nptr);
+      }
+      else if (fc == 2)
+      {
+        /* reset delete (2 or more childs) */
+        del_cnt = 0;
+        at_rn = (struct mib_list_rootnode*)(at_n->nptr);
+      }
+      level++;
+    }
+    /* delete marked index nodes */
+    while (del_cnt > 0)
+    {
+      del_cnt--;
+
+      at_rn = del_rn[del_cnt];
+      at_n = del_n[del_cnt];
+
+      next = snmp_mib_node_delete(at_rn, at_n);
+      if (next != NULL)
+      {
+        LWIP_ASSERT("next_count == 0",next->count == 0);
+        snmp_mib_lrn_free(next);
+      }
+    }
+  }
+  /* disable getnext traversal on empty tables */
+  if(arptree_root.count == 0) at.maxlength = 0;
+  if(ipntomtree_root.count == 0) ipntomtable.maxlength = 0;
+}
+
+void snmp_inc_ipinreceives(void)
+{
+  ipinreceives++;
+}
+
+void snmp_inc_ipinhdrerrors(void)
+{
+  ipinhdrerrors++;
+}
+
+void snmp_inc_ipinaddrerrors(void)
+{
+  ipinaddrerrors++;
+}
+
+void snmp_inc_ipforwdatagrams(void)
+{
+  ipforwdatagrams++;
+}
+
+void snmp_inc_ipinunknownprotos(void)
+{
+  ipinunknownprotos++;
+}
+
+void snmp_inc_ipindiscards(void)
+{
+  ipindiscards++;
+}
+
+void snmp_inc_ipindelivers(void)
+{
+  ipindelivers++;
+}
+
+void snmp_inc_ipoutrequests(void)
+{
+  ipoutrequests++;
+}
+
+void snmp_inc_ipoutdiscards(void)
+{
+  ipoutdiscards++;
+}
+
+void snmp_inc_ipoutnoroutes(void)
+{
+  ipoutnoroutes++;
+}
+
+void snmp_inc_ipreasmreqds(void)
+{
+  ipreasmreqds++;
+}
+
+void snmp_inc_ipreasmoks(void)
+{
+  ipreasmoks++;
+}
+
+void snmp_inc_ipreasmfails(void)
+{
+  ipreasmfails++;
+}
+
+void snmp_inc_ipfragoks(void)
+{
+  ipfragoks++;
+}
+
+void snmp_inc_ipfragfails(void)
+{
+  ipfragfails++;
+}
+
+void snmp_inc_ipfragcreates(void)
+{
+  ipfragcreates++;
+}
+
+void snmp_inc_iproutingdiscards(void)
+{
+  iproutingdiscards++;
+}
+
+/**
+ * Inserts ipAddrTable indexes (.ipAdEntAddr)
+ * into index tree.
+ */
+void snmp_insert_ipaddridx_tree(struct netif *ni)
+{
+  struct mib_list_rootnode *ipa_rn;
+  struct mib_list_node *ipa_node;
+  s32_t ipaddridx[4];
+  u8_t level;
+
+  LWIP_ASSERT("ni != NULL", ni != NULL);
+  snmp_iptooid(&ni->ip_addr, &ipaddridx[0]);
+
+  level = 0;
+  ipa_rn = &ipaddrtree_root;
+  while (level < 4)
+  {
+    ipa_node = NULL;
+    snmp_mib_node_insert(ipa_rn, ipaddridx[level], &ipa_node);
+    if ((level != 3) && (ipa_node != NULL))
+    {
+      if (ipa_node->nptr == NULL)
+      {
+        ipa_rn = snmp_mib_lrn_alloc();
+        ipa_node->nptr = (struct mib_node*)ipa_rn;
+        if (ipa_rn != NULL)
+        {
+          if (level == 2)
+          {
+            ipa_rn->get_object_def = ip_addrentry_get_object_def;
+            ipa_rn->get_value = ip_addrentry_get_value;
+            ipa_rn->set_test = noleafs_set_test;
+            ipa_rn->set_value = noleafs_set_value;
+          }
+        }
+        else
+        {
+          /* ipa_rn == NULL, malloc failure */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_ipaddridx_tree() insert failed, mem full"));
+          break;
+        }
+      }
+      else
+      {
+        ipa_rn = (struct mib_list_rootnode*)ipa_node->nptr;
+      }
+    }
+    level++;
+  }
+  /* enable getnext traversal on filled table */
+  ipaddrtable.maxlength = 1;
+}
+
+/**
+ * Removes ipAddrTable indexes (.ipAdEntAddr)
+ * from index tree.
+ */
+void snmp_delete_ipaddridx_tree(struct netif *ni)
+{
+  struct mib_list_rootnode *ipa_rn, *next, *del_rn[4];
+  struct mib_list_node *ipa_n, *del_n[4];
+  s32_t ipaddridx[4];
+  u8_t fc, level, del_cnt;
+
+  LWIP_ASSERT("ni != NULL", ni != NULL);
+  snmp_iptooid(&ni->ip_addr, &ipaddridx[0]);
+
+  /* mark nodes for deletion */
+  level = 0;
+  del_cnt = 0;
+  ipa_rn = &ipaddrtree_root;
+  while ((level < 4) && (ipa_rn != NULL))
+  {
+    fc = snmp_mib_node_find(ipa_rn, ipaddridx[level], &ipa_n);
+    if (fc == 0)
+    {
+      /* ipaddridx[level] does not exist */
+      del_cnt = 0;
+      ipa_rn = NULL;
+    }
+    else if (fc == 1)
+    {
+      del_rn[del_cnt] = ipa_rn;
+      del_n[del_cnt] = ipa_n;
+      del_cnt++;
+      ipa_rn = (struct mib_list_rootnode*)(ipa_n->nptr);
+    }
+    else if (fc == 2)
+    {
+      /* reset delete (2 or more childs) */
+      del_cnt = 0;
+      ipa_rn = (struct mib_list_rootnode*)(ipa_n->nptr);
+    }
+    level++;
+  }
+  /* delete marked index nodes */
+  while (del_cnt > 0)
+  {
+    del_cnt--;
+
+    ipa_rn = del_rn[del_cnt];
+    ipa_n = del_n[del_cnt];
+
+    next = snmp_mib_node_delete(ipa_rn, ipa_n);
+    if (next != NULL)
+    {
+      LWIP_ASSERT("next_count == 0",next->count == 0);
+      snmp_mib_lrn_free(next);
+    }
+  }
+  /* disable getnext traversal on empty table */
+  if (ipaddrtree_root.count == 0) ipaddrtable.maxlength = 0;
+}
+
+/**
+ * Inserts ipRouteTable indexes (.ipRouteDest)
+ * into index tree.
+ *
+ * @param dflt non-zero for the default rte, zero for network rte
+ * @param ni points to network interface for this rte
+ *
+ * @todo record sysuptime for _this_ route when it is installed
+ *   (needed for ipRouteAge) in the netif.
+ */
+void snmp_insert_iprteidx_tree(u8_t dflt, struct netif *ni)
+{
+  u8_t insert = 0;
+  ip_addr_t dst;
+
+  if (dflt != 0)
+  {
+    /* the default route 0.0.0.0 */
+    ip_addr_set_any(&dst);
+    insert = 1;
+  }
+  else
+  {
+    /* route to the network address */
+    ip_addr_get_network(&dst, &ni->ip_addr, &ni->netmask);
+    /* exclude 0.0.0.0 network (reserved for default rte) */
+    if (!ip_addr_isany(&dst)) {
+      insert = 1;
+    }
+  }
+  if (insert)
+  {
+    struct mib_list_rootnode *iprte_rn;
+    struct mib_list_node *iprte_node;
+    s32_t iprteidx[4];
+    u8_t level;
+
+    snmp_iptooid(&dst, &iprteidx[0]);
+    level = 0;
+    iprte_rn = &iprtetree_root;
+    while (level < 4)
+    {
+      iprte_node = NULL;
+      snmp_mib_node_insert(iprte_rn, iprteidx[level], &iprte_node);
+      if ((level != 3) && (iprte_node != NULL))
+      {
+        if (iprte_node->nptr == NULL)
+        {
+          iprte_rn = snmp_mib_lrn_alloc();
+          iprte_node->nptr = (struct mib_node*)iprte_rn;
+          if (iprte_rn != NULL)
+          {
+            if (level == 2)
+            {
+              iprte_rn->get_object_def = ip_rteentry_get_object_def;
+              iprte_rn->get_value = ip_rteentry_get_value;
+              iprte_rn->set_test = noleafs_set_test;
+              iprte_rn->set_value = noleafs_set_value;
+            }
+          }
+          else
+          {
+            /* iprte_rn == NULL, malloc failure */
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_iprteidx_tree() insert failed, mem full"));
+            break;
+          }
+        }
+        else
+        {
+          iprte_rn = (struct mib_list_rootnode*)iprte_node->nptr;
+        }
+      }
+      level++;
+    }
+  }
+  /* enable getnext traversal on filled table */
+  iprtetable.maxlength = 1;
+}
+
+/**
+ * Removes ipRouteTable indexes (.ipRouteDest)
+ * from index tree.
+ *
+ * @param dflt non-zero for the default rte, zero for network rte
+ * @param ni points to network interface for this rte or NULL
+ *   for default route to be removed.
+ */
+void snmp_delete_iprteidx_tree(u8_t dflt, struct netif *ni)
+{
+  u8_t del = 0;
+  ip_addr_t dst;
+
+  if (dflt != 0)
+  {
+    /* the default route 0.0.0.0 */
+    ip_addr_set_any(&dst);
+    del = 1;
+  }
+  else
+  {
+    /* route to the network address */
+    ip_addr_get_network(&dst, &ni->ip_addr, &ni->netmask);
+    /* exclude 0.0.0.0 network (reserved for default rte) */
+    if (!ip_addr_isany(&dst)) {
+      del = 1;
+    }
+  }
+  if (del)
+  {
+    struct mib_list_rootnode *iprte_rn, *next, *del_rn[4];
+    struct mib_list_node *iprte_n, *del_n[4];
+    s32_t iprteidx[4];
+    u8_t fc, level, del_cnt;
+
+    snmp_iptooid(&dst, &iprteidx[0]);
+    /* mark nodes for deletion */
+    level = 0;
+    del_cnt = 0;
+    iprte_rn = &iprtetree_root;
+    while ((level < 4) && (iprte_rn != NULL))
+    {
+      fc = snmp_mib_node_find(iprte_rn, iprteidx[level], &iprte_n);
+      if (fc == 0)
+      {
+        /* iprteidx[level] does not exist */
+        del_cnt = 0;
+        iprte_rn = NULL;
+      }
+      else if (fc == 1)
+      {
+        del_rn[del_cnt] = iprte_rn;
+        del_n[del_cnt] = iprte_n;
+        del_cnt++;
+        iprte_rn = (struct mib_list_rootnode*)(iprte_n->nptr);
+      }
+      else if (fc == 2)
+      {
+        /* reset delete (2 or more childs) */
+        del_cnt = 0;
+        iprte_rn = (struct mib_list_rootnode*)(iprte_n->nptr);
+      }
+      level++;
+    }
+    /* delete marked index nodes */
+    while (del_cnt > 0)
+    {
+      del_cnt--;
+
+      iprte_rn = del_rn[del_cnt];
+      iprte_n = del_n[del_cnt];
+
+      next = snmp_mib_node_delete(iprte_rn, iprte_n);
+      if (next != NULL)
+      {
+        LWIP_ASSERT("next_count == 0",next->count == 0);
+        snmp_mib_lrn_free(next);
+      }
+    }
+  }
+  /* disable getnext traversal on empty table */
+  if (iprtetree_root.count == 0) iprtetable.maxlength = 0;
+}
+
+
+void snmp_inc_icmpinmsgs(void)
+{
+  icmpinmsgs++;
+}
+
+void snmp_inc_icmpinerrors(void)
+{
+  icmpinerrors++;
+}
+
+void snmp_inc_icmpindestunreachs(void)
+{
+  icmpindestunreachs++;
+}
+
+void snmp_inc_icmpintimeexcds(void)
+{
+  icmpintimeexcds++;
+}
+
+void snmp_inc_icmpinparmprobs(void)
+{
+  icmpinparmprobs++;
+}
+
+void snmp_inc_icmpinsrcquenchs(void)
+{
+  icmpinsrcquenchs++;
+}
+
+void snmp_inc_icmpinredirects(void)
+{
+  icmpinredirects++;
+}
+
+void snmp_inc_icmpinechos(void)
+{
+  icmpinechos++;
+}
+
+void snmp_inc_icmpinechoreps(void)
+{
+  icmpinechoreps++;
+}
+
+void snmp_inc_icmpintimestamps(void)
+{
+  icmpintimestamps++;
+}
+
+void snmp_inc_icmpintimestampreps(void)
+{
+  icmpintimestampreps++;
+}
+
+void snmp_inc_icmpinaddrmasks(void)
+{
+  icmpinaddrmasks++;
+}
+
+void snmp_inc_icmpinaddrmaskreps(void)
+{
+  icmpinaddrmaskreps++;
+}
+
+void snmp_inc_icmpoutmsgs(void)
+{
+  icmpoutmsgs++;
+}
+
+void snmp_inc_icmpouterrors(void)
+{
+  icmpouterrors++;
+}
+
+void snmp_inc_icmpoutdestunreachs(void)
+{
+  icmpoutdestunreachs++;
+}
+
+void snmp_inc_icmpouttimeexcds(void)
+{
+  icmpouttimeexcds++;
+}
+
+void snmp_inc_icmpoutparmprobs(void)
+{
+  icmpoutparmprobs++;
+}
+
+void snmp_inc_icmpoutsrcquenchs(void)
+{
+  icmpoutsrcquenchs++;
+}
+
+void snmp_inc_icmpoutredirects(void)
+{
+  icmpoutredirects++;
+}
+
+void snmp_inc_icmpoutechos(void)
+{
+  icmpoutechos++;
+}
+
+void snmp_inc_icmpoutechoreps(void)
+{
+  icmpoutechoreps++;
+}
+
+void snmp_inc_icmpouttimestamps(void)
+{
+  icmpouttimestamps++;
+}
+
+void snmp_inc_icmpouttimestampreps(void)
+{
+  icmpouttimestampreps++;
+}
+
+void snmp_inc_icmpoutaddrmasks(void)
+{
+  icmpoutaddrmasks++;
+}
+
+void snmp_inc_icmpoutaddrmaskreps(void)
+{
+  icmpoutaddrmaskreps++;
+}
+
+void snmp_inc_tcpactiveopens(void)
+{
+  tcpactiveopens++;
+}
+
+void snmp_inc_tcppassiveopens(void)
+{
+  tcppassiveopens++;
+}
+
+void snmp_inc_tcpattemptfails(void)
+{
+  tcpattemptfails++;
+}
+
+void snmp_inc_tcpestabresets(void)
+{
+  tcpestabresets++;
+}
+
+void snmp_inc_tcpinsegs(void)
+{
+  tcpinsegs++;
+}
+
+void snmp_inc_tcpoutsegs(void)
+{
+  tcpoutsegs++;
+}
+
+void snmp_inc_tcpretranssegs(void)
+{
+  tcpretranssegs++;
+}
+
+void snmp_inc_tcpinerrs(void)
+{
+  tcpinerrs++;
+}
+
+void snmp_inc_tcpoutrsts(void)
+{
+  tcpoutrsts++;
+}
+
+void snmp_inc_udpindatagrams(void)
+{
+  udpindatagrams++;
+}
+
+void snmp_inc_udpnoports(void)
+{
+  udpnoports++;
+}
+
+void snmp_inc_udpinerrors(void)
+{
+  udpinerrors++;
+}
+
+void snmp_inc_udpoutdatagrams(void)
+{
+  udpoutdatagrams++;
+}
+
+/**
+ * Inserts udpTable indexes (.udpLocalAddress.udpLocalPort)
+ * into index tree.
+ */
+void snmp_insert_udpidx_tree(struct udp_pcb *pcb)
+{
+  struct mib_list_rootnode *udp_rn;
+  struct mib_list_node *udp_node;
+  s32_t udpidx[5];
+  u8_t level;
+
+  LWIP_ASSERT("pcb != NULL", pcb != NULL);
+  snmp_iptooid(&pcb->local_ip, &udpidx[0]);
+  udpidx[4] = pcb->local_port;
+
+  udp_rn = &udp_root;
+  for (level = 0; level < 5; level++)
+  {
+    udp_node = NULL;
+    snmp_mib_node_insert(udp_rn, udpidx[level], &udp_node);
+    if ((level != 4) && (udp_node != NULL))
+    {
+      if (udp_node->nptr == NULL)
+      {
+        udp_rn = snmp_mib_lrn_alloc();
+        udp_node->nptr = (struct mib_node*)udp_rn;
+        if (udp_rn != NULL)
+        {
+          if (level == 3)
+          {
+            udp_rn->get_object_def = udpentry_get_object_def;
+            udp_rn->get_value = udpentry_get_value;
+            udp_rn->set_test = noleafs_set_test;
+            udp_rn->set_value = noleafs_set_value;
+          }
+        }
+        else
+        {
+          /* udp_rn == NULL, malloc failure */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_udpidx_tree() insert failed, mem full"));
+          break;
+        }
+      }
+      else
+      {
+        udp_rn = (struct mib_list_rootnode*)udp_node->nptr;
+      }
+    }
+  }
+  udptable.maxlength = 1;
+}
+
+/**
+ * Removes udpTable indexes (.udpLocalAddress.udpLocalPort)
+ * from index tree.
+ */
+void snmp_delete_udpidx_tree(struct udp_pcb *pcb)
+{
+  struct udp_pcb *npcb;
+  struct mib_list_rootnode *udp_rn, *next, *del_rn[5];
+  struct mib_list_node *udp_n, *del_n[5];
+  s32_t udpidx[5];
+  u8_t bindings, fc, level, del_cnt;
+
+  LWIP_ASSERT("pcb != NULL", pcb != NULL);
+  snmp_iptooid(&pcb->local_ip, &udpidx[0]);
+  udpidx[4] = pcb->local_port;
+
+  /* count PCBs for a given binding
+     (e.g. when reusing ports or for temp output PCBs) */
+  bindings = 0;
+  npcb = udp_pcbs;
+  while ((npcb != NULL))
+  {
+    if (ip_addr_cmp(&npcb->local_ip, &pcb->local_ip) &&
+        (npcb->local_port == udpidx[4]))
+    {
+      bindings++;
+    }
+    npcb = npcb->next;
+  }
+  if (bindings == 1)
+  {
+    /* selectively remove */
+    /* mark nodes for deletion */
+    level = 0;
+    del_cnt = 0;
+    udp_rn = &udp_root;
+    while ((level < 5) && (udp_rn != NULL))
+    {
+      fc = snmp_mib_node_find(udp_rn, udpidx[level], &udp_n);
+      if (fc == 0)
+      {
+        /* udpidx[level] does not exist */
+        del_cnt = 0;
+        udp_rn = NULL;
+      }
+      else if (fc == 1)
+      {
+        del_rn[del_cnt] = udp_rn;
+        del_n[del_cnt] = udp_n;
+        del_cnt++;
+        udp_rn = (struct mib_list_rootnode*)(udp_n->nptr);
+      }
+      else if (fc == 2)
+      {
+        /* reset delete (2 or more childs) */
+        del_cnt = 0;
+        udp_rn = (struct mib_list_rootnode*)(udp_n->nptr);
+      }
+      level++;
+    }
+    /* delete marked index nodes */
+    while (del_cnt > 0)
+    {
+      del_cnt--;
+
+      udp_rn = del_rn[del_cnt];
+      udp_n = del_n[del_cnt];
+
+      next = snmp_mib_node_delete(udp_rn, udp_n);
+      if (next != NULL)
+      {
+        LWIP_ASSERT("next_count == 0",next->count == 0);
+        snmp_mib_lrn_free(next);
+      }
+    }
+  }
+  /* disable getnext traversal on empty table */
+  if (udp_root.count == 0) udptable.maxlength = 0;
+}
+
+
+void snmp_inc_snmpinpkts(void)
+{
+  snmpinpkts++;
+}
+
+void snmp_inc_snmpoutpkts(void)
+{
+  snmpoutpkts++;
+}
+
+void snmp_inc_snmpinbadversions(void)
+{
+  snmpinbadversions++;
+}
+
+void snmp_inc_snmpinbadcommunitynames(void)
+{
+  snmpinbadcommunitynames++;
+}
+
+void snmp_inc_snmpinbadcommunityuses(void)
+{
+  snmpinbadcommunityuses++;
+}
+
+void snmp_inc_snmpinasnparseerrs(void)
+{
+  snmpinasnparseerrs++;
+}
+
+void snmp_inc_snmpintoobigs(void)
+{
+  snmpintoobigs++;
+}
+
+void snmp_inc_snmpinnosuchnames(void)
+{
+  snmpinnosuchnames++;
+}
+
+void snmp_inc_snmpinbadvalues(void)
+{
+  snmpinbadvalues++;
+}
+
+void snmp_inc_snmpinreadonlys(void)
+{
+  snmpinreadonlys++;
+}
+
+void snmp_inc_snmpingenerrs(void)
+{
+  snmpingenerrs++;
+}
+
+void snmp_add_snmpintotalreqvars(u8_t value)
+{
+  snmpintotalreqvars += value;
+}
+
+void snmp_add_snmpintotalsetvars(u8_t value)
+{
+  snmpintotalsetvars += value;
+}
+
+void snmp_inc_snmpingetrequests(void)
+{
+  snmpingetrequests++;
+}
+
+void snmp_inc_snmpingetnexts(void)
+{
+  snmpingetnexts++;
+}
+
+void snmp_inc_snmpinsetrequests(void)
+{
+  snmpinsetrequests++;
+}
+
+void snmp_inc_snmpingetresponses(void)
+{
+  snmpingetresponses++;
+}
+
+void snmp_inc_snmpintraps(void)
+{
+  snmpintraps++;
+}
+
+void snmp_inc_snmpouttoobigs(void)
+{
+  snmpouttoobigs++;
+}
+
+void snmp_inc_snmpoutnosuchnames(void)
+{
+  snmpoutnosuchnames++;
+}
+
+void snmp_inc_snmpoutbadvalues(void)
+{
+  snmpoutbadvalues++;
+}
+
+void snmp_inc_snmpoutgenerrs(void)
+{
+  snmpoutgenerrs++;
+}
+
+void snmp_inc_snmpoutgetrequests(void)
+{
+  snmpoutgetrequests++;
+}
+
+void snmp_inc_snmpoutgetnexts(void)
+{
+  snmpoutgetnexts++;
+}
+
+void snmp_inc_snmpoutsetrequests(void)
+{
+  snmpoutsetrequests++;
+}
+
+void snmp_inc_snmpoutgetresponses(void)
+{
+  snmpoutgetresponses++;
+}
+
+void snmp_inc_snmpouttraps(void)
+{
+  snmpouttraps++;
+}
+
+void snmp_get_snmpgrpid_ptr(struct snmp_obj_id **oid)
+{
+  *oid = &snmpgrp_id;
+}
+
+void snmp_set_snmpenableauthentraps(u8_t *value)
+{
+  if (value != NULL)
+  {
+    snmpenableauthentraps_ptr = value;
+  }
+}
+
+void snmp_get_snmpenableauthentraps(u8_t *value)
+{
+  *value = *snmpenableauthentraps_ptr;
+}
+
+void
+noleafs_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  LWIP_UNUSED_ARG(ident_len);
+  LWIP_UNUSED_ARG(ident);
+  od->instance = MIB_OBJECT_NONE;
+}
+
+void
+noleafs_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  LWIP_UNUSED_ARG(od);
+  LWIP_UNUSED_ARG(len);
+  LWIP_UNUSED_ARG(value);
+}
+
+u8_t
+noleafs_set_test(struct obj_def *od, u16_t len, void *value)
+{
+  LWIP_UNUSED_ARG(od);
+  LWIP_UNUSED_ARG(len);
+  LWIP_UNUSED_ARG(value);
+  /* can't set */
+  return 0;
+}
+
+void
+noleafs_set_value(struct obj_def *od, u16_t len, void *value)
+{
+  LWIP_UNUSED_ARG(od);
+  LWIP_UNUSED_ARG(len);
+  LWIP_UNUSED_ARG(value);
+}
+
+
+/**
+ * Returns systems object definitions.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.0 (object id trailer)
+ * @param od points to object definition.
+ */
+static void
+system_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  u8_t id;
+
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    LWIP_ASSERT("invalid id", (ident[0] >= 0) && (ident[0] <= 0xff));
+    id = (u8_t)ident[0];
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def system.%"U16_F".0\n",(u16_t)id));
+    switch (id)
+    {
+      case 1: /* sysDescr */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = *sysdescr_len_ptr;
+        break;
+      case 2: /* sysObjectID */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID);
+        od->v_len = sysobjid.len * sizeof(s32_t);
+        break;
+      case 3: /* sysUpTime */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 4: /* sysContact */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = *syscontact_len_ptr;
+        break;
+      case 5: /* sysName */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = *sysname_len_ptr;
+        break;
+      case 6: /* sysLocation */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = *syslocation_len_ptr;
+        break;
+      case 7: /* sysServices */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("system_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("system_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+/**
+ * Returns system object value.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.0 (object id trailer)
+ * @param len return value space (in bytes)
+ * @param value points to (varbind) space to copy value into.
+ */
+static void
+system_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+
+  LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff));
+  id = (u8_t)od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* sysDescr */
+      ocstrncpy((u8_t*)value, sysdescr_ptr, len);
+      break;
+    case 2: /* sysObjectID */
+      objectidncpy((s32_t*)value, (s32_t*)sysobjid.id, (u8_t)(len / sizeof(s32_t)));
+      break;
+    case 3: /* sysUpTime */
+      {
+        snmp_get_sysuptime((u32_t*)value);
+      }
+      break;
+    case 4: /* sysContact */
+      ocstrncpy((u8_t*)value, syscontact_ptr, len);
+      break;
+    case 5: /* sysName */
+      ocstrncpy((u8_t*)value, sysname_ptr, len);
+      break;
+    case 6: /* sysLocation */
+      ocstrncpy((u8_t*)value, syslocation_ptr, len);
+      break;
+    case 7: /* sysServices */
+      {
+        s32_t *sint_ptr = (s32_t*)value;
+        *sint_ptr = sysservices;
+      }
+      break;
+  };
+}
+
+static u8_t
+system_set_test(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id, set_ok;
+
+  LWIP_UNUSED_ARG(value);
+  set_ok = 0;
+  LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff));
+  id = (u8_t)od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 4: /* sysContact */
+      if ((syscontact_ptr != syscontact_default) &&
+          (len <= 255))
+      {
+        set_ok = 1;
+      }
+      break;
+    case 5: /* sysName */
+      if ((sysname_ptr != sysname_default) &&
+          (len <= 255))
+      {
+        set_ok = 1;
+      }
+      break;
+    case 6: /* sysLocation */
+      if ((syslocation_ptr != syslocation_default) &&
+          (len <= 255))
+      {
+        set_ok = 1;
+      }
+      break;
+  };
+  return set_ok;
+}
+
+static void
+system_set_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+
+  LWIP_ASSERT("invalid len", len <= 0xff);
+  LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff));
+  id = (u8_t)od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 4: /* sysContact */
+      ocstrncpy(syscontact_ptr, (u8_t*)value, len);
+      *syscontact_len_ptr = (u8_t)len;
+      break;
+    case 5: /* sysName */
+      ocstrncpy(sysname_ptr, (u8_t*)value, len);
+      *sysname_len_ptr = (u8_t)len;
+      break;
+    case 6: /* sysLocation */
+      ocstrncpy(syslocation_ptr, (u8_t*)value, len);
+      *syslocation_len_ptr = (u8_t)len;
+      break;
+  };
+}
+
+/**
+ * Returns interfaces.ifnumber object definition.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.index
+ * @param od points to object definition.
+ */
+static void
+interfaces_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    od->instance = MIB_OBJECT_SCALAR;
+    od->access = MIB_OBJECT_READ_ONLY;
+    od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+    od->v_len = sizeof(s32_t);
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("interfaces_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+/**
+ * Returns interfaces.ifnumber object value.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.0 (object id trailer)
+ * @param len return value space (in bytes)
+ * @param value points to (varbind) space to copy value into.
+ */
+static void
+interfaces_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  LWIP_UNUSED_ARG(len);
+  if (od->id_inst_ptr[0] == 1)
+  {
+    s32_t *sint_ptr = (s32_t*)value;
+    *sint_ptr = iflist_root.count;
+  }
+}
+
+/**
+ * Returns ifentry object definitions.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.index
+ * @param od points to object definition.
+ */
+static void
+ifentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  u8_t id;
+
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    LWIP_ASSERT("invalid id", (ident[0] >= 0) && (ident[0] <= 0xff));
+    id = (u8_t)ident[0];
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def ifentry.%"U16_F"\n",(u16_t)id));
+    switch (id)
+    {
+      case 1: /* ifIndex */
+      case 3: /* ifType */
+      case 4: /* ifMtu */
+      case 8: /* ifOperStatus */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 2: /* ifDescr */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        /** @todo this should be some sort of sizeof(struct netif.name) */
+        od->v_len = 2;
+        break;
+      case 5: /* ifSpeed */
+      case 21: /* ifOutQLen */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 6: /* ifPhysAddress */
+        {
+          struct netif *netif;
+
+          snmp_ifindextonetif(ident[1], &netif);
+          od->instance = MIB_OBJECT_TAB;
+          od->access = MIB_OBJECT_READ_ONLY;
+          od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+          od->v_len = netif->hwaddr_len;
+        }
+        break;
+      case 7: /* ifAdminStatus */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 9: /* ifLastChange */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 10: /* ifInOctets */
+      case 11: /* ifInUcastPkts */
+      case 12: /* ifInNUcastPkts */
+      case 13: /* ifInDiscarts */
+      case 14: /* ifInErrors */
+      case 15: /* ifInUnkownProtos */
+      case 16: /* ifOutOctets */
+      case 17: /* ifOutUcastPkts */
+      case 18: /* ifOutNUcastPkts */
+      case 19: /* ifOutDiscarts */
+      case 20: /* ifOutErrors */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 22: /* ifSpecific */
+        /** @note returning zeroDotZero (0.0) no media specific MIB support */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID);
+        od->v_len = ifspecific.len * sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ifentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("ifentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+/**
+ * Returns ifentry object value.
+ *
+ * @param ident_len the address length (2)
+ * @param ident points to objectname.0 (object id trailer)
+ * @param len return value space (in bytes)
+ * @param value points to (varbind) space to copy value into.
+ */
+static void
+ifentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  struct netif *netif;
+  u8_t id;
+
+  snmp_ifindextonetif(od->id_inst_ptr[1], &netif);
+  LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff));
+  id = (u8_t)od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* ifIndex */
+      {
+        s32_t *sint_ptr = (s32_t*)value;
+        *sint_ptr = od->id_inst_ptr[1];
+      }
+      break;
+    case 2: /* ifDescr */
+      ocstrncpy((u8_t*)value, (u8_t*)netif->name, len);
+      break;
+    case 3: /* ifType */
+      {
+        s32_t *sint_ptr = (s32_t*)value;
+        *sint_ptr = netif->link_type;
+      }
+      break;
+    case 4: /* ifMtu */
+      {
+        s32_t *sint_ptr = (s32_t*)value;
+        *sint_ptr = netif->mtu;
+      }
+      break;
+    case 5: /* ifSpeed */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = netif->link_speed;
+      }
+      break;
+    case 6: /* ifPhysAddress */
+      ocstrncpy((u8_t*)value, netif->hwaddr, len);
+      break;
+    case 7: /* ifAdminStatus */
+      {
+        s32_t *sint_ptr = (s32_t*)value;
+        if (netif_is_up(netif))
+        {
+          if (netif_is_link_up(netif))
+          {
+            *sint_ptr = 1; /* up */
+          }
+          else
+          {
+            *sint_ptr = 7; /* lowerLayerDown */
+          }
+        }
+        else
+        {
+          *sint_ptr = 2; /* down */
+        }
+      }
+      break;
+    case 8: /* ifOperStatus */
+      {
+        s32_t *sint_ptr = (s32_t*)value;
+        if (netif_is_up(netif))
+        {
+          *sint_ptr = 1;
+        }
+        else
+        {
+          *sint_ptr = 2;
+        }
+      }
+      break;
+    case 9: /* ifLastChange */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = netif->ts;
+      }
+      break;
+    case 10: /* ifInOctets */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = netif->ifinoctets;
+      }
+      break;
+    case 11: /* ifInUcastPkts */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = netif->ifinucastpkts;
+      }
+      break;
+    case 12: /* ifInNUcastPkts */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = netif->ifinnucastpkts;
+      }
+      break;
+    case 13: /* ifInDiscarts */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = netif->ifindiscards;
+      }
+      break;
+    case 14: /* ifInErrors */
+    case 15: /* ifInUnkownProtos */
+      /** @todo add these counters! */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = 0;
+      }
+      break;
+    case 16: /* ifOutOctets */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = netif->ifoutoctets;
+      }
+      break;
+    case 17: /* ifOutUcastPkts */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = netif->ifoutucastpkts;
+      }
+      break;
+    case 18: /* ifOutNUcastPkts */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = netif->ifoutnucastpkts;
+      }
+      break;
+    case 19: /* ifOutDiscarts */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = netif->ifoutdiscards;
+      }
+      break;
+    case 20: /* ifOutErrors */
+       /** @todo add this counter! */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = 0;
+      }
+      break;
+    case 21: /* ifOutQLen */
+      /** @todo figure out if this must be 0 (no queue) or 1? */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = 0;
+      }
+      break;
+    case 22: /* ifSpecific */
+      objectidncpy((s32_t*)value, (s32_t*)ifspecific.id, (u8_t)(len / sizeof(s32_t)));
+      break;
+  };
+}
+
+#if !SNMP_SAFE_REQUESTS
+static u8_t
+ifentry_set_test(struct obj_def *od, u16_t len, void *value)
+{
+  struct netif *netif;
+  u8_t id, set_ok;
+  LWIP_UNUSED_ARG(len);
+
+  set_ok = 0;
+  snmp_ifindextonetif(od->id_inst_ptr[1], &netif);
+  id = (u8_t)od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 7: /* ifAdminStatus */
+      {
+        s32_t *sint_ptr = (s32_t*)value;
+        if (*sint_ptr == 1 || *sint_ptr == 2)
+          set_ok = 1;
+      }
+      break;
+  }
+  return set_ok;
+}
+
+static void
+ifentry_set_value(struct obj_def *od, u16_t len, void *value)
+{
+  struct netif *netif;
+  u8_t id;
+  LWIP_UNUSED_ARG(len);
+
+  snmp_ifindextonetif(od->id_inst_ptr[1], &netif);
+  id = (u8_t)od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 7: /* ifAdminStatus */
+      {
+        s32_t *sint_ptr = (s32_t*)value;
+        if (*sint_ptr == 1)
+        {
+          netif_set_up(netif);
+        }
+        else if (*sint_ptr == 2)
+        {
+          netif_set_down(netif);
+         }
+      }
+      break;
+  }
+}
+#endif /* SNMP_SAFE_REQUESTS */
+
+/**
+ * Returns atentry object definitions.
+ *
+ * @param ident_len the address length (6)
+ * @param ident points to objectname.atifindex.atnetaddress
+ * @param od points to object definition.
+ */
+static void
+atentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (5) */
+  ident_len += 5;
+  ident -= 5;
+
+  if (ident_len == 6)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    switch (ident[0])
+    {
+      case 1: /* atIfIndex */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 2: /* atPhysAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = 6; /** @todo try to use netif::hwaddr_len */
+        break;
+      case 3: /* atNetAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("atentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    }
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("atentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+atentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+#if LWIP_ARP
+  u8_t id;
+  struct eth_addr* ethaddr_ret;
+  ip_addr_t* ipaddr_ret;
+#endif /* LWIP_ARP */
+  ip_addr_t ip;
+  struct netif *netif;
+
+  LWIP_UNUSED_ARG(len);
+  LWIP_UNUSED_ARG(value);/* if !LWIP_ARP */
+
+  snmp_ifindextonetif(od->id_inst_ptr[1], &netif);
+  snmp_oidtoip(&od->id_inst_ptr[2], &ip);
+
+#if LWIP_ARP /** @todo implement a netif_find_addr */
+  if (etharp_find_addr(netif, &ip, ðaddr_ret, &ipaddr_ret) > -1)
+  {
+    LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff));
+    id = (u8_t)od->id_inst_ptr[0];
+    switch (id)
+    {
+      case 1: /* atIfIndex */
+        {
+          s32_t *sint_ptr = (s32_t*)value;
+          *sint_ptr = od->id_inst_ptr[1];
+        }
+        break;
+      case 2: /* atPhysAddress */
+        {
+          struct eth_addr *dst = (struct eth_addr*)value;
+
+          *dst = *ethaddr_ret;
+        }
+        break;
+      case 3: /* atNetAddress */
+        {
+          ip_addr_t *dst = (ip_addr_t*)value;
+
+          *dst = *ipaddr_ret;
+        }
+        break;
+    }
+  }
+#endif /* LWIP_ARP */
+}
+
+static void
+ip_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  u8_t id;
+
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    LWIP_ASSERT("invalid id", (ident[0] >= 0) && (ident[0] <= 0xff));
+    id = (u8_t)ident[0];
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def ip.%"U16_F".0\n",(u16_t)id));
+    switch (id)
+    {
+      case 1: /* ipForwarding */
+      case 2: /* ipDefaultTTL */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 3: /* ipInReceives */
+      case 4: /* ipInHdrErrors */
+      case 5: /* ipInAddrErrors */
+      case 6: /* ipForwDatagrams */
+      case 7: /* ipInUnknownProtos */
+      case 8: /* ipInDiscards */
+      case 9: /* ipInDelivers */
+      case 10: /* ipOutRequests */
+      case 11: /* ipOutDiscards */
+      case 12: /* ipOutNoRoutes */
+      case 14: /* ipReasmReqds */
+      case 15: /* ipReasmOKs */
+      case 16: /* ipReasmFails */
+      case 17: /* ipFragOKs */
+      case 18: /* ipFragFails */
+      case 19: /* ipFragCreates */
+      case 23: /* ipRoutingDiscards */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 13: /* ipReasmTimeout */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+ip_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+
+  LWIP_UNUSED_ARG(len);
+  LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff));
+  id = (u8_t)od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* ipForwarding */
+      {
+        s32_t *sint_ptr = (s32_t*)value;
+#if IP_FORWARD
+        /* forwarding */
+        *sint_ptr = 1;
+#else
+        /* not-forwarding */
+        *sint_ptr = 2;
+#endif
+      }
+      break;
+    case 2: /* ipDefaultTTL */
+      {
+        s32_t *sint_ptr = (s32_t*)value;
+        *sint_ptr = IP_DEFAULT_TTL;
+      }
+      break;
+    case 3: /* ipInReceives */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = ipinreceives;
+      }
+      break;
+    case 4: /* ipInHdrErrors */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = ipinhdrerrors;
+      }
+      break;
+    case 5: /* ipInAddrErrors */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = ipinaddrerrors;
+      }
+      break;
+    case 6: /* ipForwDatagrams */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = ipforwdatagrams;
+      }
+      break;
+    case 7: /* ipInUnknownProtos */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = ipinunknownprotos;
+      }
+      break;
+    case 8: /* ipInDiscards */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = ipindiscards;
+      }
+      break;
+    case 9: /* ipInDelivers */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = ipindelivers;
+      }
+      break;
+    case 10: /* ipOutRequests */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = ipoutrequests;
+      }
+      break;
+    case 11: /* ipOutDiscards */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = ipoutdiscards;
+      }
+      break;
+    case 12: /* ipOutNoRoutes */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = ipoutnoroutes;
+      }
+      break;
+    case 13: /* ipReasmTimeout */
+      {
+        s32_t *sint_ptr = (s32_t*)value;
+#if IP_REASSEMBLY
+        *sint_ptr = IP_REASS_MAXAGE;
+#else
+        *sint_ptr = 0;
+#endif
+      }
+      break;
+    case 14: /* ipReasmReqds */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = ipreasmreqds;
+      }
+      break;
+    case 15: /* ipReasmOKs */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = ipreasmoks;
+      }
+      break;
+    case 16: /* ipReasmFails */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = ipreasmfails;
+      }
+      break;
+    case 17: /* ipFragOKs */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = ipfragoks;
+      }
+      break;
+    case 18: /* ipFragFails */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = ipfragfails;
+      }
+      break;
+    case 19: /* ipFragCreates */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = ipfragcreates;
+      }
+      break;
+    case 23: /* ipRoutingDiscards */
+      /** @todo can lwIP discard routes at all?? hardwire this to 0?? */
+      {
+        u32_t *uint_ptr = (u32_t*)value;
+        *uint_ptr = iproutingdiscards;
+      }
+      break;
+  };
+}
+
+/**
+ * Test ip object value before setting.
+ *
+ * @param od is the object definition
+ * @param len return value space (in bytes)
+ * @param value points to (varbind) space to copy value from.
+ *
+ * @note we allow set if the value matches the hardwired value,
+ *   otherwise return badvalue.
+ */
+static u8_t
+ip_set_test(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id, set_ok;
+  s32_t *sint_ptr = (s32_t*)value;
+
+  LWIP_UNUSED_ARG(len);
+  set_ok = 0;
+  LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff));
+  id = (u8_t)od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* ipForwarding */
+#if IP_FORWARD
+      /* forwarding */
+      if (*sint_ptr == 1)
+#else
+      /* not-forwarding */
+      if (*sint_ptr == 2)
+#endif
+      {
+        set_ok = 1;
+      }
+      break;
+    case 2: /* ipDefaultTTL */
+      if (*sint_ptr == IP_DEFAULT_TTL)
+      {
+        set_ok = 1;
+      }
+      break;
+  };
+  return set_ok;
+}
+
+static void
+ip_addrentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (4) */
+  ident_len += 4;
+  ident -= 4;
+
+  if (ident_len == 5)
+  {
+    u8_t id;
+
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    LWIP_ASSERT("invalid id", (ident[0] >= 0) && (ident[0] <= 0xff));
+    id = (u8_t)ident[0];
+    switch (id)
+    {
+      case 1: /* ipAdEntAddr */
+      case 3: /* ipAdEntNetMask */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      case 2: /* ipAdEntIfIndex */
+      case 4: /* ipAdEntBcastAddr */
+      case 5: /* ipAdEntReasmMaxSize */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_addrentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    }
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_addrentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+ip_addrentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+  u16_t ifidx;
+  ip_addr_t ip;
+  struct netif *netif = netif_list;
+
+  LWIP_UNUSED_ARG(len);
+  snmp_oidtoip(&od->id_inst_ptr[1], &ip);
+  ifidx = 0;
+  while ((netif != NULL) && !ip_addr_cmp(&ip, &netif->ip_addr))
+  {
+    netif = netif->next;
+    ifidx++;
+  }
+
+  if (netif != NULL)
+  {
+    LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff));
+    id = (u8_t)od->id_inst_ptr[0];
+    switch (id)
+    {
+      case 1: /* ipAdEntAddr */
+        {
+          ip_addr_t *dst = (ip_addr_t*)value;
+          *dst = netif->ip_addr;
+        }
+        break;
+      case 2: /* ipAdEntIfIndex */
+        {
+          s32_t *sint_ptr = (s32_t*)value;
+          *sint_ptr = ifidx + 1;
+        }
+        break;
+      case 3: /* ipAdEntNetMask */
+        {
+          ip_addr_t *dst = (ip_addr_t*)value;
+          *dst = netif->netmask;
+        }
+        break;
+      case 4: /* ipAdEntBcastAddr */
+        {
+          s32_t *sint_ptr = (s32_t*)value;
+
+          /* lwIP oddity, there's no broadcast
+            address in the netif we can rely on */
+          *sint_ptr = IPADDR_BROADCAST & 1;
+        }
+        break;
+      case 5: /* ipAdEntReasmMaxSize */
+        {
+          s32_t *sint_ptr = (s32_t*)value;
+#if IP_REASSEMBLY
+          /* @todo The theoretical maximum is IP_REASS_MAX_PBUFS * size of the pbufs,
+           * but only if receiving one fragmented packet at a time.
+           * The current solution is to calculate for 2 simultaneous packets...
+           */
+          *sint_ptr = (IP_HLEN + ((IP_REASS_MAX_PBUFS/2) *
+            (PBUF_POOL_BUFSIZE - PBUF_LINK_HLEN - IP_HLEN)));
+#else
+          /** @todo returning MTU would be a bad thing and
+             returning a wild guess like '576' isn't good either */
+          *sint_ptr = 0;
+#endif
+        }
+        break;
+    }
+  }
+}
+
+/**
+ * @note
+ * lwIP IP routing is currently using the network addresses in netif_list.
+ * if no suitable network IP is found in netif_list, the default_netif is used.
+ */
+static void
+ip_rteentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  u8_t id;
+
+  /* return to object name, adding index depth (4) */
+  ident_len += 4;
+  ident -= 4;
+
+  if (ident_len == 5)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    LWIP_ASSERT("invalid id", (ident[0] >= 0) && (ident[0] <= 0xff));
+    id = (u8_t)ident[0];
+    switch (id)
+    {
+      case 1: /* ipRouteDest */
+      case 7: /* ipRouteNextHop */
+      case 11: /* ipRouteMask */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      case 2: /* ipRouteIfIndex */
+      case 3: /* ipRouteMetric1 */
+      case 4: /* ipRouteMetric2 */
+      case 5: /* ipRouteMetric3 */
+      case 6: /* ipRouteMetric4 */
+      case 8: /* ipRouteType */
+      case 10: /* ipRouteAge */
+      case 12: /* ipRouteMetric5 */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 9: /* ipRouteProto */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 13: /* ipRouteInfo */
+        /** @note returning zeroDotZero (0.0) no routing protocol specific MIB */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID);
+        od->v_len = iprouteinfo.len * sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_rteentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    }
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_rteentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+ip_rteentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  struct netif *netif;
+  ip_addr_t dest;
+  s32_t *ident;
+  u8_t id;
+
+  ident = od->id_inst_ptr;
+  snmp_oidtoip(&ident[1], &dest);
+
+  if (ip_addr_isany(&dest))
+  {
+    /* ip_route() uses default netif for default route */
+    netif = netif_default;
+  }
+  else
+  {
+    /* not using ip_route(), need exact match! */
+    netif = netif_list;
+    while ((netif != NULL) &&
+            !ip_addr_netcmp(&dest, &(netif->ip_addr), &(netif->netmask)) )
+    {
+      netif = netif->next;
+    }
+  }
+  if (netif != NULL)
+  {
+    LWIP_ASSERT("invalid id", (ident[0] >= 0) && (ident[0] <= 0xff));
+    id = (u8_t)ident[0];
+    switch (id)
+    {
+      case 1: /* ipRouteDest */
+        {
+          ip_addr_t *dst = (ip_addr_t*)value;
+
+          if (ip_addr_isany(&dest))
+          {
+            /* default rte has 0.0.0.0 dest */
+            ip_addr_set_zero(dst);
+          }
+          else
+          {
+            /* netifs have netaddress dest */
+            ip_addr_get_network(dst, &netif->ip_addr, &netif->netmask);
+          }
+        }
+        break;
+      case 2: /* ipRouteIfIndex */
+        {
+          s32_t *sint_ptr = (s32_t*)value;
+
+          snmp_netiftoifindex(netif, sint_ptr);
+        }
+        break;
+      case 3: /* ipRouteMetric1 */
+        {
+          s32_t *sint_ptr = (s32_t*)value;
+
+          if (ip_addr_isany(&dest))
+          {
+            /* default rte has metric 1 */
+            *sint_ptr = 1;
+          }
+          else
+          {
+            /* other rtes have metric 0 */
+            *sint_ptr = 0;
+          }
+        }
+        break;
+      case 4: /* ipRouteMetric2 */
+      case 5: /* ipRouteMetric3 */
+      case 6: /* ipRouteMetric4 */
+      case 12: /* ipRouteMetric5 */
+        {
+          s32_t *sint_ptr = (s32_t*)value;
+          /* not used */
+          *sint_ptr = -1;
+        }
+        break;
+      case 7: /* ipRouteNextHop */
+        {
+          ip_addr_t *dst = (ip_addr_t*)value;
+
+          if (ip_addr_isany(&dest))
+          {
+            /* default rte: gateway */
+            *dst = netif->gw;
+          }
+          else
+          {
+            /* other rtes: netif ip_addr  */
+            *dst = netif->ip_addr;
+          }
+        }
+        break;
+      case 8: /* ipRouteType */
+        {
+          s32_t *sint_ptr = (s32_t*)value;
+
+          if (ip_addr_isany(&dest))
+          {
+            /* default rte is indirect */
+            *sint_ptr = 4;
+          }
+          else
+          {
+            /* other rtes are direct */
+            *sint_ptr = 3;
+          }
+        }
+        break;
+      case 9: /* ipRouteProto */
+        {
+          s32_t *sint_ptr = (s32_t*)value;
+          /* locally defined routes */
+          *sint_ptr = 2;
+        }
+        break;
+      case 10: /* ipRouteAge */
+        {
+          s32_t *sint_ptr = (s32_t*)value;
+          /** @todo (sysuptime - timestamp last change) / 100
+              @see snmp_insert_iprteidx_tree() */
+          *sint_ptr = 0;
+        }
+        break;
+      case 11: /* ipRouteMask */
+        {
+          ip_addr_t *dst = (ip_addr_t*)value;
+
+          if (ip_addr_isany(&dest))
+          {
+            /* default rte use 0.0.0.0 mask */
+            ip_addr_set_zero(dst);
+          }
+          else
+          {
+            /* other rtes use netmask */
+            *dst = netif->netmask;
+          }
+        }
+        break;
+      case 13: /* ipRouteInfo */
+        objectidncpy((s32_t*)value, (s32_t*)iprouteinfo.id, (u8_t)(len / sizeof(s32_t)));
+        break;
+    }
+  }
+}
+
+static void
+ip_ntomentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (5) */
+  ident_len += 5;
+  ident -= 5;
+
+  if (ident_len == 6)
+  {
+    u8_t id;
+
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    LWIP_ASSERT("invalid id", (ident[0] >= 0) && (ident[0] <= 0xff));
+    id = (u8_t)ident[0];
+    switch (id)
+    {
+      case 1: /* ipNetToMediaIfIndex */
+      case 4: /* ipNetToMediaType */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 2: /* ipNetToMediaPhysAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR);
+        od->v_len = 6; /** @todo try to use netif::hwaddr_len */
+        break;
+      case 3: /* ipNetToMediaNetAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_ntomentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    }
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_ntomentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+ip_ntomentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+#if LWIP_ARP
+  u8_t id;
+  struct eth_addr* ethaddr_ret;
+  ip_addr_t* ipaddr_ret;
+#endif /* LWIP_ARP */
+  ip_addr_t ip;
+  struct netif *netif;
+
+  LWIP_UNUSED_ARG(len);
+  LWIP_UNUSED_ARG(value);/* if !LWIP_ARP */
+
+  snmp_ifindextonetif(od->id_inst_ptr[1], &netif);
+  snmp_oidtoip(&od->id_inst_ptr[2], &ip);
+
+#if LWIP_ARP /** @todo implement a netif_find_addr */
+  if (etharp_find_addr(netif, &ip, ðaddr_ret, &ipaddr_ret) > -1)
+  {
+    LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff));
+    id = (u8_t)od->id_inst_ptr[0];
+    switch (id)
+    {
+      case 1: /* ipNetToMediaIfIndex */
+        {
+          s32_t *sint_ptr = (s32_t*)value;
+          *sint_ptr = od->id_inst_ptr[1];
+        }
+        break;
+      case 2: /* ipNetToMediaPhysAddress */
+        {
+          struct eth_addr *dst = (struct eth_addr*)value;
+
+          *dst = *ethaddr_ret;
+        }
+        break;
+      case 3: /* ipNetToMediaNetAddress */
+        {
+          ip_addr_t *dst = (ip_addr_t*)value;
+
+          *dst = *ipaddr_ret;
+        }
+        break;
+      case 4: /* ipNetToMediaType */
+        {
+          s32_t *sint_ptr = (s32_t*)value;
+          /* dynamic (?) */
+          *sint_ptr = 3;
+        }
+        break;
+    }
+  }
+#endif /* LWIP_ARP */
+}
+
+static void
+icmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if ((ident_len == 2) &&
+      (ident[0] > 0) && (ident[0] < 27))
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    od->instance = MIB_OBJECT_SCALAR;
+    od->access = MIB_OBJECT_READ_ONLY;
+    od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+    od->v_len = sizeof(u32_t);
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("icmp_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+icmp_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u32_t *uint_ptr = (u32_t*)value;
+  u8_t id;
+
+  LWIP_UNUSED_ARG(len);
+  LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff));
+  id = (u8_t)od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* icmpInMsgs */
+      *uint_ptr = icmpinmsgs;
+      break;
+    case 2: /* icmpInErrors */
+      *uint_ptr = icmpinerrors;
+      break;
+    case 3: /* icmpInDestUnreachs */
+      *uint_ptr = icmpindestunreachs;
+      break;
+    case 4: /* icmpInTimeExcds */
+      *uint_ptr = icmpintimeexcds;
+      break;
+    case 5: /* icmpInParmProbs */
+      *uint_ptr = icmpinparmprobs;
+      break;
+    case 6: /* icmpInSrcQuenchs */
+      *uint_ptr = icmpinsrcquenchs;
+      break;
+    case 7: /* icmpInRedirects */
+      *uint_ptr = icmpinredirects;
+      break;
+    case 8: /* icmpInEchos */
+      *uint_ptr = icmpinechos;
+      break;
+    case 9: /* icmpInEchoReps */
+      *uint_ptr = icmpinechoreps;
+      break;
+    case 10: /* icmpInTimestamps */
+      *uint_ptr = icmpintimestamps;
+      break;
+    case 11: /* icmpInTimestampReps */
+      *uint_ptr = icmpintimestampreps;
+      break;
+    case 12: /* icmpInAddrMasks */
+      *uint_ptr = icmpinaddrmasks;
+      break;
+    case 13: /* icmpInAddrMaskReps */
+      *uint_ptr = icmpinaddrmaskreps;
+      break;
+    case 14: /* icmpOutMsgs */
+      *uint_ptr = icmpoutmsgs;
+      break;
+    case 15: /* icmpOutErrors */
+      *uint_ptr = icmpouterrors;
+      break;
+    case 16: /* icmpOutDestUnreachs */
+      *uint_ptr = icmpoutdestunreachs;
+      break;
+    case 17: /* icmpOutTimeExcds */
+      *uint_ptr = icmpouttimeexcds;
+      break;
+    case 18: /* icmpOutParmProbs */
+      *uint_ptr = icmpoutparmprobs;
+      break;
+    case 19: /* icmpOutSrcQuenchs */
+      *uint_ptr = icmpoutsrcquenchs;
+      break;
+    case 20: /* icmpOutRedirects */
+      *uint_ptr = icmpoutredirects;
+      break;
+    case 21: /* icmpOutEchos */
+      *uint_ptr = icmpoutechos;
+      break;
+    case 22: /* icmpOutEchoReps */
+      *uint_ptr = icmpoutechoreps;
+      break;
+    case 23: /* icmpOutTimestamps */
+      *uint_ptr = icmpouttimestamps;
+      break;
+    case 24: /* icmpOutTimestampReps */
+      *uint_ptr = icmpouttimestampreps;
+      break;
+    case 25: /* icmpOutAddrMasks */
+      *uint_ptr = icmpoutaddrmasks;
+      break;
+    case 26: /* icmpOutAddrMaskReps */
+      *uint_ptr = icmpoutaddrmaskreps;
+      break;
+  }
+}
+
+#if LWIP_TCP
+/** @todo tcp grp */
+static void
+tcp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  u8_t id;
+
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    LWIP_ASSERT("invalid id", (ident[0] >= 0) && (ident[0] <= 0xff));
+    id = (u8_t)ident[0];
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def tcp.%"U16_F".0\n",(u16_t)id));
+
+    switch (id)
+    {
+      case 1: /* tcpRtoAlgorithm */
+      case 2: /* tcpRtoMin */
+      case 3: /* tcpRtoMax */
+      case 4: /* tcpMaxConn */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 5: /* tcpActiveOpens */
+      case 6: /* tcpPassiveOpens */
+      case 7: /* tcpAttemptFails */
+      case 8: /* tcpEstabResets */
+      case 10: /* tcpInSegs */
+      case 11: /* tcpOutSegs */
+      case 12: /* tcpRetransSegs */
+      case 14: /* tcpInErrs */
+      case 15: /* tcpOutRsts */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 9: /* tcpCurrEstab */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE);
+        od->v_len = sizeof(u32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcp_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcp_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+tcp_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u32_t *uint_ptr = (u32_t*)value;
+  s32_t *sint_ptr = (s32_t*)value;
+  u8_t id;
+
+  LWIP_UNUSED_ARG(len);
+  LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff));
+  id = (u8_t)od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* tcpRtoAlgorithm, vanj(4) */
+      *sint_ptr = 4;
+      break;
+    case 2: /* tcpRtoMin */
+      /* @todo not the actual value, a guess,
+          needs to be calculated */
+      *sint_ptr = 1000;
+      break;
+    case 3: /* tcpRtoMax */
+      /* @todo not the actual value, a guess,
+         needs to be calculated */
+      *sint_ptr = 60000;
+      break;
+    case 4: /* tcpMaxConn */
+      *sint_ptr = MEMP_NUM_TCP_PCB;
+      break;
+    case 5: /* tcpActiveOpens */
+      *uint_ptr = tcpactiveopens;
+      break;
+    case 6: /* tcpPassiveOpens */
+      *uint_ptr = tcppassiveopens;
+      break;
+    case 7: /* tcpAttemptFails */
+      *uint_ptr = tcpattemptfails;
+      break;
+    case 8: /* tcpEstabResets */
+      *uint_ptr = tcpestabresets;
+      break;
+    case 9: /* tcpCurrEstab */
+      {
+        u16_t tcpcurrestab = 0;
+        struct tcp_pcb *pcb = tcp_active_pcbs;
+        while (pcb != NULL)
+        {
+          if ((pcb->state == ESTABLISHED) ||
+              (pcb->state == CLOSE_WAIT))
+          {
+            tcpcurrestab++;
+          }
+          pcb = pcb->next;
+        }
+        *uint_ptr = tcpcurrestab;
+      }
+      break;
+    case 10: /* tcpInSegs */
+      *uint_ptr = tcpinsegs;
+      break;
+    case 11: /* tcpOutSegs */
+      *uint_ptr = tcpoutsegs;
+      break;
+    case 12: /* tcpRetransSegs */
+      *uint_ptr = tcpretranssegs;
+      break;
+    case 14: /* tcpInErrs */
+      *uint_ptr = tcpinerrs;
+      break;
+    case 15: /* tcpOutRsts */
+      *uint_ptr = tcpoutrsts;
+      break;
+  }
+}
+#ifdef THIS_SEEMS_UNUSED
+static void
+tcpconnentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (10) */
+  ident_len += 10;
+  ident -= 10;
+
+  if (ident_len == 11)
+  {
+    u8_t id;
+
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    id = ident[0];
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def tcp.%"U16_F".0\n",(u16_t)id));
+
+    switch (id)
+    {
+      case 1: /* tcpConnState */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      case 2: /* tcpConnLocalAddress */
+      case 4: /* tcpConnRemAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      case 3: /* tcpConnLocalPort */
+      case 5: /* tcpConnRemPort */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcpconnentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcpconnentry_get_object_def: no such object\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+tcpconnentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  ip_addr_t lip, rip;
+  u16_t lport, rport;
+  s32_t *ident;
+
+  ident = od->id_inst_ptr;
+  snmp_oidtoip(&ident[1], &lip);
+  lport = ident[5];
+  snmp_oidtoip(&ident[6], &rip);
+  rport = ident[10];
+
+  /** @todo find matching PCB */
+}
+#endif /* if 0 */
+#endif
+
+static void
+udp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if ((ident_len == 2) &&
+      (ident[0] > 0) && (ident[0] < 6))
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    od->instance = MIB_OBJECT_SCALAR;
+    od->access = MIB_OBJECT_READ_ONLY;
+    od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+    od->v_len = sizeof(u32_t);
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("udp_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+udp_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u32_t *uint_ptr = (u32_t*)value;
+  u8_t id;
+
+  LWIP_UNUSED_ARG(len);
+  LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff));
+  id = (u8_t)od->id_inst_ptr[0];
+  switch (id)
+  {
+    case 1: /* udpInDatagrams */
+      *uint_ptr = udpindatagrams;
+      break;
+    case 2: /* udpNoPorts */
+      *uint_ptr = udpnoports;
+      break;
+    case 3: /* udpInErrors */
+      *uint_ptr = udpinerrors;
+      break;
+    case 4: /* udpOutDatagrams */
+      *uint_ptr = udpoutdatagrams;
+      break;
+  }
+}
+
+static void
+udpentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (5) */
+  ident_len += 5;
+  ident -= 5;
+
+  if (ident_len == 6)
+  {
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    switch (ident[0])
+    {
+      case 1: /* udpLocalAddress */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR);
+        od->v_len = 4;
+        break;
+      case 2: /* udpLocalPort */
+        od->instance = MIB_OBJECT_TAB;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("udpentry_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    }
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("udpentry_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+udpentry_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+  struct udp_pcb *pcb;
+  ip_addr_t ip;
+  u16_t port;
+
+  LWIP_UNUSED_ARG(len);
+  snmp_oidtoip(&od->id_inst_ptr[1], &ip);
+  LWIP_ASSERT("invalid port", (od->id_inst_ptr[5] >= 0) && (od->id_inst_ptr[5] <= 0xffff));
+  port = (u16_t)od->id_inst_ptr[5];
+
+  pcb = udp_pcbs;
+  while ((pcb != NULL) &&
+         !(ip_addr_cmp(&pcb->local_ip, &ip) &&
+           (pcb->local_port == port)))
+  {
+    pcb = pcb->next;
+  }
+
+  if (pcb != NULL)
+  {
+    LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff));
+    id = (u8_t)od->id_inst_ptr[0];
+    switch (id)
+    {
+      case 1: /* udpLocalAddress */
+        {
+          ip_addr_t *dst = (ip_addr_t*)value;
+          *dst = pcb->local_ip;
+        }
+        break;
+      case 2: /* udpLocalPort */
+        {
+          s32_t *sint_ptr = (s32_t*)value;
+          *sint_ptr = pcb->local_port;
+        }
+        break;
+    }
+  }
+}
+
+static void
+snmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od)
+{
+  /* return to object name, adding index depth (1) */
+  ident_len += 1;
+  ident -= 1;
+  if (ident_len == 2)
+  {
+    u8_t id;
+
+    od->id_inst_len = ident_len;
+    od->id_inst_ptr = ident;
+
+    LWIP_ASSERT("invalid id", (ident[0] >= 0) && (ident[0] <= 0xff));
+    id = (u8_t)ident[0];
+    switch (id)
+    {
+      case 1: /* snmpInPkts */
+      case 2: /* snmpOutPkts */
+      case 3: /* snmpInBadVersions */
+      case 4: /* snmpInBadCommunityNames */
+      case 5: /* snmpInBadCommunityUses */
+      case 6: /* snmpInASNParseErrs */
+      case 8: /* snmpInTooBigs */
+      case 9: /* snmpInNoSuchNames */
+      case 10: /* snmpInBadValues */
+      case 11: /* snmpInReadOnlys */
+      case 12: /* snmpInGenErrs */
+      case 13: /* snmpInTotalReqVars */
+      case 14: /* snmpInTotalSetVars */
+      case 15: /* snmpInGetRequests */
+      case 16: /* snmpInGetNexts */
+      case 17: /* snmpInSetRequests */
+      case 18: /* snmpInGetResponses */
+      case 19: /* snmpInTraps */
+      case 20: /* snmpOutTooBigs */
+      case 21: /* snmpOutNoSuchNames */
+      case 22: /* snmpOutBadValues */
+      case 24: /* snmpOutGenErrs */
+      case 25: /* snmpOutGetRequests */
+      case 26: /* snmpOutGetNexts */
+      case 27: /* snmpOutSetRequests */
+      case 28: /* snmpOutGetResponses */
+      case 29: /* snmpOutTraps */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_ONLY;
+        od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER);
+        od->v_len = sizeof(u32_t);
+        break;
+      case 30: /* snmpEnableAuthenTraps */
+        od->instance = MIB_OBJECT_SCALAR;
+        od->access = MIB_OBJECT_READ_WRITE;
+        od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG);
+        od->v_len = sizeof(s32_t);
+        break;
+      default:
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_get_object_def: no such object\n"));
+        od->instance = MIB_OBJECT_NONE;
+        break;
+    };
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_get_object_def: no scalar\n"));
+    od->instance = MIB_OBJECT_NONE;
+  }
+}
+
+static void
+snmp_get_value(struct obj_def *od, u16_t len, void *value)
+{
+  u32_t *uint_ptr = (u32_t*)value;
+  u8_t id;
+
+  LWIP_UNUSED_ARG(len);
+  LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff));
+  id = (u8_t)od->id_inst_ptr[0];
+  switch (id)
+  {
+      case 1: /* snmpInPkts */
+        *uint_ptr = snmpinpkts;
+        break;
+      case 2: /* snmpOutPkts */
+        *uint_ptr = snmpoutpkts;
+        break;
+      case 3: /* snmpInBadVersions */
+        *uint_ptr = snmpinbadversions;
+        break;
+      case 4: /* snmpInBadCommunityNames */
+        *uint_ptr = snmpinbadcommunitynames;
+        break;
+      case 5: /* snmpInBadCommunityUses */
+        *uint_ptr = snmpinbadcommunityuses;
+        break;
+      case 6: /* snmpInASNParseErrs */
+        *uint_ptr = snmpinasnparseerrs;
+        break;
+      case 8: /* snmpInTooBigs */
+        *uint_ptr = snmpintoobigs;
+        break;
+      case 9: /* snmpInNoSuchNames */
+        *uint_ptr = snmpinnosuchnames;
+        break;
+      case 10: /* snmpInBadValues */
+        *uint_ptr = snmpinbadvalues;
+        break;
+      case 11: /* snmpInReadOnlys */
+        *uint_ptr = snmpinreadonlys;
+        break;
+      case 12: /* snmpInGenErrs */
+        *uint_ptr = snmpingenerrs;
+        break;
+      case 13: /* snmpInTotalReqVars */
+        *uint_ptr = snmpintotalreqvars;
+        break;
+      case 14: /* snmpInTotalSetVars */
+        *uint_ptr = snmpintotalsetvars;
+        break;
+      case 15: /* snmpInGetRequests */
+        *uint_ptr = snmpingetrequests;
+        break;
+      case 16: /* snmpInGetNexts */
+        *uint_ptr = snmpingetnexts;
+        break;
+      case 17: /* snmpInSetRequests */
+        *uint_ptr = snmpinsetrequests;
+        break;
+      case 18: /* snmpInGetResponses */
+        *uint_ptr = snmpingetresponses;
+        break;
+      case 19: /* snmpInTraps */
+        *uint_ptr = snmpintraps;
+        break;
+      case 20: /* snmpOutTooBigs */
+        *uint_ptr = snmpouttoobigs;
+        break;
+      case 21: /* snmpOutNoSuchNames */
+        *uint_ptr = snmpoutnosuchnames;
+        break;
+      case 22: /* snmpOutBadValues */
+        *uint_ptr = snmpoutbadvalues;
+        break;
+      case 24: /* snmpOutGenErrs */
+        *uint_ptr = snmpoutgenerrs;
+        break;
+      case 25: /* snmpOutGetRequests */
+        *uint_ptr = snmpoutgetrequests;
+        break;
+      case 26: /* snmpOutGetNexts */
+        *uint_ptr = snmpoutgetnexts;
+        break;
+      case 27: /* snmpOutSetRequests */
+        *uint_ptr = snmpoutsetrequests;
+        break;
+      case 28: /* snmpOutGetResponses */
+        *uint_ptr = snmpoutgetresponses;
+        break;
+      case 29: /* snmpOutTraps */
+        *uint_ptr = snmpouttraps;
+        break;
+      case 30: /* snmpEnableAuthenTraps */
+        *uint_ptr = *snmpenableauthentraps_ptr;
+        break;
+  };
+}
+
+/**
+ * Test snmp object value before setting.
+ *
+ * @param od is the object definition
+ * @param len return value space (in bytes)
+ * @param value points to (varbind) space to copy value from.
+ */
+static u8_t
+snmp_set_test(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id, set_ok;
+
+  LWIP_UNUSED_ARG(len);
+  set_ok = 0;
+  LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff));
+  id = (u8_t)od->id_inst_ptr[0];
+  if (id == 30)
+  {
+    /* snmpEnableAuthenTraps */
+    s32_t *sint_ptr = (s32_t*)value;
+
+    if (snmpenableauthentraps_ptr != &snmpenableauthentraps_default)
+    {
+      /* we should have writable non-volatile mem here */
+      if ((*sint_ptr == 1) || (*sint_ptr == 2))
+      {
+        set_ok = 1;
+      }
+    }
+    else
+    {
+      /* const or hardwired value */
+      if (*sint_ptr == snmpenableauthentraps_default)
+      {
+        set_ok = 1;
+      }
+    }
+  }
+  return set_ok;
+}
+
+static void
+snmp_set_value(struct obj_def *od, u16_t len, void *value)
+{
+  u8_t id;
+
+  LWIP_UNUSED_ARG(len);
+  LWIP_ASSERT("invalid id", (od->id_inst_ptr[0] >= 0) && (od->id_inst_ptr[0] <= 0xff));
+  id = (u8_t)od->id_inst_ptr[0];
+  if (id == 30)
+  {
+    /* snmpEnableAuthenTraps */
+    /* @todo @fixme: which kind of pointer is 'value'? s32_t or u8_t??? */
+    u8_t *ptr = (u8_t*)value;
+    *snmpenableauthentraps_ptr = *ptr;
+  }
+}
+
+#endif /* LWIP_SNMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/snmp/mib_structs.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/snmp/mib_structs.c
new file mode 100644
index 0000000..2f185cb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/snmp/mib_structs.c
@@ -0,0 +1,1174 @@
+/**
+ * @file
+ * MIB tree access/construction functions.
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/snmp_structs.h"
+#include "lwip/memp.h"
+#include "lwip/netif.h"
+
+/** .iso.org.dod.internet address prefix, @see snmp_iso_*() */
+const s32_t prefix[4] = {1, 3, 6, 1};
+
+#define NODE_STACK_SIZE (LWIP_SNMP_OBJ_ID_LEN)
+/** node stack entry (old news?) */
+struct nse
+{
+  /** right child */
+  struct mib_node* r_ptr;
+  /** right child identifier */
+  s32_t r_id;
+  /** right child next level */
+  u8_t r_nl;
+};
+static u8_t node_stack_cnt;
+static struct nse node_stack[NODE_STACK_SIZE];
+
+/**
+ * Pushes nse struct onto stack.
+ */
+static void
+push_node(struct nse* node)
+{
+  LWIP_ASSERT("node_stack_cnt < NODE_STACK_SIZE",node_stack_cnt < NODE_STACK_SIZE);
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("push_node() node=%p id=%"S32_F"\n",(void*)(node->r_ptr),node->r_id));
+  if (node_stack_cnt < NODE_STACK_SIZE)
+  {
+    node_stack[node_stack_cnt] = *node;
+    node_stack_cnt++;
+  }
+}
+
+/**
+ * Pops nse struct from stack.
+ */
+static void
+pop_node(struct nse* node)
+{
+  if (node_stack_cnt > 0)
+  {
+    node_stack_cnt--;
+    *node = node_stack[node_stack_cnt];
+  }
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("pop_node() node=%p id=%"S32_F"\n",(void *)(node->r_ptr),node->r_id));
+}
+
+/**
+ * Conversion from ifIndex to lwIP netif
+ * @param ifindex is a s32_t object sub-identifier
+ * @param netif points to returned netif struct pointer
+ */
+void
+snmp_ifindextonetif(s32_t ifindex, struct netif **netif)
+{
+  struct netif *nif = netif_list;
+  s32_t i, ifidx;
+
+  ifidx = ifindex - 1;
+  i = 0;
+  while ((nif != NULL) && (i < ifidx))
+  {
+    nif = nif->next;
+    i++;
+  }
+  *netif = nif;
+}
+
+/**
+ * Conversion from lwIP netif to ifIndex
+ * @param netif points to a netif struct
+ * @param ifidx points to s32_t object sub-identifier
+ */
+void
+snmp_netiftoifindex(struct netif *netif, s32_t *ifidx)
+{
+  struct netif *nif = netif_list;
+  u16_t i;
+
+  i = 0;
+  while ((nif != NULL) && (nif != netif))
+  {
+    nif = nif->next;
+    i++;
+  }
+  *ifidx = i+1;
+}
+
+/**
+ * Conversion from oid to lwIP ip_addr
+ * @param ident points to s32_t ident[4] input
+ * @param ip points to output struct
+ */
+void
+snmp_oidtoip(s32_t *ident, ip_addr_t *ip)
+{
+  IP4_ADDR(ip, ident[0], ident[1], ident[2], ident[3]);
+}
+
+/**
+ * Conversion from lwIP ip_addr to oid
+ * @param ip points to input struct
+ * @param ident points to s32_t ident[4] output
+ */
+void
+snmp_iptooid(ip_addr_t *ip, s32_t *ident)
+{
+  ident[0] = ip4_addr1(ip);
+  ident[1] = ip4_addr2(ip);
+  ident[2] = ip4_addr3(ip);
+  ident[3] = ip4_addr4(ip);
+}
+
+struct mib_list_node *
+snmp_mib_ln_alloc(s32_t id)
+{
+  struct mib_list_node *ln;
+
+  ln = (struct mib_list_node *)memp_malloc(MEMP_SNMP_NODE);
+  if (ln != NULL)
+  {
+    ln->prev = NULL;
+    ln->next = NULL;
+    ln->objid = id;
+    ln->nptr = NULL;
+  }
+  return ln;
+}
+
+void
+snmp_mib_ln_free(struct mib_list_node *ln)
+{
+  memp_free(MEMP_SNMP_NODE, ln);
+}
+
+struct mib_list_rootnode *
+snmp_mib_lrn_alloc(void)
+{
+  struct mib_list_rootnode *lrn;
+
+  lrn = (struct mib_list_rootnode*)memp_malloc(MEMP_SNMP_ROOTNODE);
+  if (lrn != NULL)
+  {
+    lrn->get_object_def = noleafs_get_object_def;
+    lrn->get_value = noleafs_get_value;
+    lrn->set_test = noleafs_set_test;
+    lrn->set_value = noleafs_set_value;
+    lrn->node_type = MIB_NODE_LR;
+    lrn->maxlength = 0;
+    lrn->head = NULL;
+    lrn->tail = NULL;
+    lrn->count = 0;
+  }
+  return lrn;
+}
+
+void
+snmp_mib_lrn_free(struct mib_list_rootnode *lrn)
+{
+  memp_free(MEMP_SNMP_ROOTNODE, lrn);
+}
+
+/**
+ * Inserts node in idx list in a sorted
+ * (ascending order) fashion and
+ * allocates the node if needed.
+ *
+ * @param rn points to the root node
+ * @param objid is the object sub identifier
+ * @param insn points to a pointer to the inserted node
+ *   used for constructing the tree.
+ * @return -1 if failed, 1 if inserted, 2 if present.
+ */
+s8_t
+snmp_mib_node_insert(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **insn)
+{
+  struct mib_list_node *nn;
+  s8_t insert;
+
+  LWIP_ASSERT("rn != NULL",rn != NULL);
+
+  /* -1 = malloc failure, 0 = not inserted, 1 = inserted, 2 = was present */
+  insert = 0;
+  if (rn->head == NULL)
+  {
+    /* empty list, add first node */
+    LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc empty list objid==%"S32_F"\n",objid));
+    nn = snmp_mib_ln_alloc(objid);
+    if (nn != NULL)
+    {
+      rn->head = nn;
+      rn->tail = nn;
+      *insn = nn;
+      insert = 1;
+    }
+    else
+    {
+      insert = -1;
+    }
+  }
+  else
+  {
+    struct mib_list_node *n;
+    /* at least one node is present */
+    n = rn->head;
+    while ((n != NULL) && (insert == 0))
+    {
+      if (n->objid == objid)
+      {
+        /* node is already there */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("node already there objid==%"S32_F"\n",objid));
+        *insn = n;
+        insert = 2;
+      }
+      else if (n->objid < objid)
+      {
+        if (n->next == NULL)
+        {
+          /* alloc and insert at the tail */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc ins tail objid==%"S32_F"\n",objid));
+          nn = snmp_mib_ln_alloc(objid);
+          if (nn != NULL)
+          {
+            nn->next = NULL;
+            nn->prev = n;
+            n->next = nn;
+            rn->tail = nn;
+            *insn = nn;
+            insert = 1;
+          }
+          else
+          {
+            /* insertion failure */
+            insert = -1;
+          }
+        }
+        else
+        {
+          /* there's more to explore: traverse list */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("traverse list\n"));
+          n = n->next;
+        }
+      }
+      else
+      {
+        /* n->objid > objid */
+        /* alloc and insert between n->prev and n */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc ins n->prev, objid==%"S32_F", n\n",objid));
+        nn = snmp_mib_ln_alloc(objid);
+        if (nn != NULL)
+        {
+          if (n->prev == NULL)
+          {
+            /* insert at the head */
+            nn->next = n;
+            nn->prev = NULL;
+            rn->head = nn;
+            n->prev = nn;
+          }
+          else
+          {
+            /* insert in the middle */
+            nn->next = n;
+            nn->prev = n->prev;
+            n->prev->next = nn;
+            n->prev = nn;
+          }
+          *insn = nn;
+          insert = 1;
+        }
+        else
+        {
+          /* insertion failure */
+          insert = -1;
+        }
+      }
+    }
+  }
+  if (insert == 1)
+  {
+    rn->count += 1;
+  }
+  LWIP_ASSERT("insert != 0",insert != 0);
+  return insert;
+}
+
+/**
+ * Finds node in idx list and returns deletion mark.
+ *
+ * @param rn points to the root node
+ * @param objid  is the object sub identifier
+ * @param fn returns pointer to found node
+ * @return 0 if not found, 1 if deletable,
+ *   2 can't delete (2 or more children), 3 not a list_node
+ */
+s8_t
+snmp_mib_node_find(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **fn)
+{
+  s8_t fc;
+  struct mib_list_node *n;
+
+  LWIP_ASSERT("rn != NULL",rn != NULL);
+  n = rn->head;
+  while ((n != NULL) && (n->objid != objid))
+  {
+    n = n->next;
+  }
+  if (n == NULL)
+  {
+    fc = 0;
+  }
+  else if (n->nptr == NULL)
+  {
+    /* leaf, can delete node */
+    fc = 1;
+  }
+  else
+  {
+    struct mib_list_rootnode *r;
+
+    if (n->nptr->node_type == MIB_NODE_LR)
+    {
+      r = (struct mib_list_rootnode *)n->nptr;
+      if (r->count > 1)
+      {
+        /* can't delete node */
+        fc = 2;
+      }
+      else
+      {
+        /* count <= 1, can delete node */
+        fc = 1;
+      }
+    }
+    else
+    {
+      /* other node type */
+      fc = 3;
+    }
+  }
+  *fn = n;
+  return fc;
+}
+
+/**
+ * Removes node from idx list
+ * if it has a single child left.
+ *
+ * @param rn points to the root node
+ * @param n points to the node to delete
+ * @return the nptr to be freed by caller
+ */
+struct mib_list_rootnode *
+snmp_mib_node_delete(struct mib_list_rootnode *rn, struct mib_list_node *n)
+{
+  struct mib_list_rootnode *next;
+
+  LWIP_ASSERT("rn != NULL",rn != NULL);
+  LWIP_ASSERT("n != NULL",n != NULL);
+
+  /* caller must remove this sub-tree */
+  next = (struct mib_list_rootnode*)(n->nptr);
+  rn->count -= 1;
+
+  if (n == rn->head)
+  {
+    rn->head = n->next;
+    if (n->next != NULL)
+    {
+      /* not last node, new list begin */
+      n->next->prev = NULL;
+    }
+  }
+  else if (n == rn->tail)
+  {
+    rn->tail = n->prev;
+    if (n->prev != NULL)
+    {
+      /* not last node, new list end */
+      n->prev->next = NULL;
+    }
+  }
+  else
+  {
+    /* node must be in the middle */
+    n->prev->next = n->next;
+    n->next->prev = n->prev;
+  }
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("free list objid==%"S32_F"\n",n->objid));
+  snmp_mib_ln_free(n);
+  if (rn->count == 0)
+  {
+    rn->head = NULL;
+    rn->tail = NULL;
+  }
+  return next;
+}
+
+
+
+/**
+ * Searches tree for the supplied (scalar?) object identifier.
+ *
+ * @param node points to the root of the tree ('.internet')
+ * @param ident_len the length of the supplied object identifier
+ * @param ident points to the array of sub identifiers
+ * @param np points to the found object instance (return)
+ * @return pointer to the requested parent (!) node if success, NULL otherwise
+ */
+struct mib_node *
+snmp_search_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_name_ptr *np)
+{
+  u8_t node_type, ext_level;
+
+  ext_level = 0;
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("node==%p *ident==%"S32_F"\n",(void*)node,*ident));
+  while (node != NULL)
+  {
+    node_type = node->node_type;
+    if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA))
+    {
+      struct mib_array_node *an;
+      u16_t i;
+
+      if (ident_len > 0)
+      {
+        /* array node (internal ROM or RAM, fixed length) */
+        an = (struct mib_array_node *)node;
+        i = 0;
+        while ((i < an->maxlength) && (an->objid[i] != *ident))
+        {
+          i++;
+        }
+        if (i < an->maxlength)
+        {
+          /* found it, if available proceed to child, otherwise inspect leaf */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("an->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,an->objid[i],*ident));
+          if (an->nptr[i] == NULL)
+          {
+            /* a scalar leaf OR table,
+               inspect remaining instance number / table index */
+            np->ident_len = ident_len;
+            np->ident = ident;
+            return (struct mib_node*)an;
+          }
+          else
+          {
+            /* follow next child pointer */
+            ident++;
+            ident_len--;
+            node = an->nptr[i];
+          }
+        }
+        else
+        {
+          /* search failed, identifier mismatch (nosuchname) */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("an search failed *ident==%"S32_F"\n",*ident));
+          return NULL;
+        }
+      }
+      else
+      {
+        /* search failed, short object identifier (nosuchname) */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("an search failed, short object identifier\n"));
+        return NULL;
+      }
+    }
+    else if(node_type == MIB_NODE_LR)
+    {
+      struct mib_list_rootnode *lrn;
+      struct mib_list_node *ln;
+
+      if (ident_len > 0)
+      {
+        /* list root node (internal 'RAM', variable length) */
+        lrn = (struct mib_list_rootnode *)node;
+        ln = lrn->head;
+        /* iterate over list, head to tail */
+        while ((ln != NULL) && (ln->objid != *ident))
+        {
+          ln = ln->next;
+        }
+        if (ln != NULL)
+        {
+          /* found it, proceed to child */;
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln->objid==%"S32_F" *ident==%"S32_F"\n",ln->objid,*ident));
+          if (ln->nptr == NULL)
+          {
+            np->ident_len = ident_len;
+            np->ident = ident;
+            return (struct mib_node*)lrn;
+          }
+          else
+          {
+            /* follow next child pointer */
+            ident_len--;
+            ident++;
+            node = ln->nptr;
+          }
+        }
+        else
+        {
+          /* search failed */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln search failed *ident==%"S32_F"\n",*ident));
+          return NULL;
+        }
+      }
+      else
+      {
+        /* search failed, short object identifier (nosuchname) */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln search failed, short object identifier\n"));
+        return NULL;
+      }
+    }
+    else if(node_type == MIB_NODE_EX)
+    {
+      struct mib_external_node *en;
+      u16_t i, len;
+
+      if (ident_len > 0)
+      {
+        /* external node (addressing and access via functions) */
+        en = (struct mib_external_node *)node;
+
+        i = 0;
+        len = en->level_length(en->addr_inf,ext_level);
+        while ((i < len) && (en->ident_cmp(en->addr_inf,ext_level,i,*ident) != 0))
+        {
+          i++;
+        }
+        if (i < len)
+        {
+          s32_t debug_id;
+
+          en->get_objid(en->addr_inf,ext_level,i,&debug_id);
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("en->objid==%"S32_F" *ident==%"S32_F"\n",debug_id,*ident));
+          if ((ext_level + 1) == en->tree_levels)
+          {
+            np->ident_len = ident_len;
+            np->ident = ident;
+            return (struct mib_node*)en;
+          }
+          else
+          {
+            /* found it, proceed to child */
+            ident_len--;
+            ident++;
+            ext_level++;
+          }
+        }
+        else
+        {
+          /* search failed */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("en search failed *ident==%"S32_F"\n",*ident));
+          return NULL;
+        }
+      }
+      else
+      {
+        /* search failed, short object identifier (nosuchname) */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("en search failed, short object identifier\n"));
+        return NULL;
+      }
+    }
+    else if (node_type == MIB_NODE_SC)
+    {
+      mib_scalar_node *sn;
+
+      sn = (mib_scalar_node *)node;
+      if ((ident_len == 1) && (*ident == 0))
+      {
+        np->ident_len = ident_len;
+        np->ident = ident;
+        return (struct mib_node*)sn;
+      }
+      else
+      {
+        /* search failed, short object identifier (nosuchname) */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed, invalid object identifier length\n"));
+        return NULL;
+      }
+    }
+    else
+    {
+      /* unknown node_type */
+      LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed node_type %"U16_F" unkown\n",(u16_t)node_type));
+      return NULL;
+    }
+  }
+  /* done, found nothing */
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed node==%p\n",(void*)node));
+  return NULL;
+}
+
+/**
+ * Test table for presence of at least one table entry.
+ */
+static u8_t
+empty_table(struct mib_node *node)
+{
+  u8_t node_type;
+  u8_t empty = 0;
+
+  if (node != NULL)
+  {
+    node_type = node->node_type;
+    if (node_type == MIB_NODE_LR)
+    {
+      struct mib_list_rootnode *lrn;
+      lrn = (struct mib_list_rootnode *)node;
+      if ((lrn->count == 0) || (lrn->head == NULL))
+      {
+        empty = 1;
+      }
+    }
+    else if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA))
+    {
+      struct mib_array_node *an;
+      an = (struct mib_array_node *)node;
+      if ((an->maxlength == 0) || (an->nptr == NULL))
+      {
+        empty = 1;
+      }
+    }
+    else if (node_type == MIB_NODE_EX)
+    {
+      struct mib_external_node *en;
+      en = (struct mib_external_node *)node;
+      if (en->tree_levels == 0)
+      {
+        empty = 1;
+      }
+    }
+  }
+  return empty;
+}
+
+/**
+ * Tree expansion.
+ */
+struct mib_node *
+snmp_expand_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret)
+{
+  u8_t node_type, ext_level, climb_tree;
+
+  ext_level = 0;
+  /* reset node stack */
+  node_stack_cnt = 0;
+  while (node != NULL)
+  {
+    climb_tree = 0;
+    node_type = node->node_type;
+    if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA))
+    {
+      struct mib_array_node *an;
+      u16_t i;
+
+      /* array node (internal ROM or RAM, fixed length) */
+      an = (struct mib_array_node *)node;
+      if (ident_len > 0)
+      {
+        i = 0;
+        while ((i < an->maxlength) && (an->objid[i] < *ident))
+        {
+          i++;
+        }
+        if (i < an->maxlength)
+        {
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("an->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,an->objid[i],*ident));
+          /* add identifier to oidret */
+          oidret->id[oidret->len] = an->objid[i];
+          (oidret->len)++;
+
+          if (an->nptr[i] == NULL)
+          {
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("leaf node\n"));
+            /* leaf node (e.g. in a fixed size table) */
+            if (an->objid[i] > *ident)
+            {
+              return (struct mib_node*)an;
+            }
+            else if ((i + 1) < an->maxlength)
+            {
+              /* an->objid[i] == *ident */
+              (oidret->len)--;
+              oidret->id[oidret->len] = an->objid[i + 1];
+              (oidret->len)++;
+              return (struct mib_node*)an;
+            }
+            else
+            {
+              /* (i + 1) == an->maxlength */
+              (oidret->len)--;
+              climb_tree = 1;
+            }
+          }
+          else
+          {
+            u8_t j;
+            struct nse cur_node;
+
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("non-leaf node\n"));
+            /* non-leaf, store right child ptr and id */
+            LWIP_ASSERT("i < 0xff", i < 0xff);
+            j = (u8_t)i + 1;
+            while ((j < an->maxlength) && (empty_table(an->nptr[j])))
+            {
+              j++;
+            }
+            if (j < an->maxlength)
+            {
+              cur_node.r_ptr = an->nptr[j];
+              cur_node.r_id = an->objid[j];
+              cur_node.r_nl = 0;
+            }
+            else
+            {
+              cur_node.r_ptr = NULL;
+            }
+            push_node(&cur_node);
+            if (an->objid[i] == *ident)
+            {
+              ident_len--;
+              ident++;
+            }
+            else
+            {
+              /* an->objid[i] < *ident */
+              ident_len = 0;
+            }
+            /* follow next child pointer */
+            node = an->nptr[i];
+          }
+        }
+        else
+        {
+          /* i == an->maxlength */
+          climb_tree = 1;
+        }
+      }
+      else
+      {
+        u8_t j;
+        /* ident_len == 0, complete with leftmost '.thing' */
+        j = 0;
+        while ((j < an->maxlength) && empty_table(an->nptr[j]))
+        {
+          j++;
+        }
+        if (j < an->maxlength)
+        {
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("left an->objid[j]==%"S32_F"\n",an->objid[j]));
+          oidret->id[oidret->len] = an->objid[j];
+          (oidret->len)++;
+          if (an->nptr[j] == NULL)
+          {
+            /* leaf node */
+            return (struct mib_node*)an;
+          }
+          else
+          {
+            /* no leaf, continue */
+            node = an->nptr[j];
+          }
+        }
+        else
+        {
+          /* j == an->maxlength */
+          climb_tree = 1;
+        }
+      }
+    }
+    else if(node_type == MIB_NODE_LR)
+    {
+      struct mib_list_rootnode *lrn;
+      struct mib_list_node *ln;
+
+      /* list root node (internal 'RAM', variable length) */
+      lrn = (struct mib_list_rootnode *)node;
+      if (ident_len > 0)
+      {
+        ln = lrn->head;
+        /* iterate over list, head to tail */
+        while ((ln != NULL) && (ln->objid < *ident))
+        {
+          ln = ln->next;
+        }
+        if (ln != NULL)
+        {
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln->objid==%"S32_F" *ident==%"S32_F"\n",ln->objid,*ident));
+          oidret->id[oidret->len] = ln->objid;
+          (oidret->len)++;
+          if (ln->nptr == NULL)
+          {
+            /* leaf node */
+            if (ln->objid > *ident)
+            {
+              return (struct mib_node*)lrn;
+            }
+            else if (ln->next != NULL)
+            {
+              /* ln->objid == *ident */
+              (oidret->len)--;
+              oidret->id[oidret->len] = ln->next->objid;
+              (oidret->len)++;
+              return (struct mib_node*)lrn;
+            }
+            else
+            {
+              /* ln->next == NULL */
+              (oidret->len)--;
+              climb_tree = 1;
+            }
+          }
+          else
+          {
+            struct mib_list_node *jn;
+            struct nse cur_node;
+
+            /* non-leaf, store right child ptr and id */
+            jn = ln->next;
+            while ((jn != NULL) && empty_table(jn->nptr))
+            {
+              jn = jn->next;
+            }
+            if (jn != NULL)
+            {
+              cur_node.r_ptr = jn->nptr;
+              cur_node.r_id = jn->objid;
+              cur_node.r_nl = 0;
+            }
+            else
+            {
+              cur_node.r_ptr = NULL;
+            }
+            push_node(&cur_node);
+            if (ln->objid == *ident)
+            {
+              ident_len--;
+              ident++;
+            }
+            else
+            {
+              /* ln->objid < *ident */
+              ident_len = 0;
+            }
+            /* follow next child pointer */
+            node = ln->nptr;
+          }
+
+        }
+        else
+        {
+          /* ln == NULL */
+          climb_tree = 1;
+        }
+      }
+      else
+      {
+        struct mib_list_node *jn;
+        /* ident_len == 0, complete with leftmost '.thing' */
+        jn = lrn->head;
+        while ((jn != NULL) && empty_table(jn->nptr))
+        {
+          jn = jn->next;
+        }
+        if (jn != NULL)
+        {
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("left jn->objid==%"S32_F"\n",jn->objid));
+          oidret->id[oidret->len] = jn->objid;
+          (oidret->len)++;
+          if (jn->nptr == NULL)
+          {
+            /* leaf node */
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("jn->nptr == NULL\n"));
+            return (struct mib_node*)lrn;
+          }
+          else
+          {
+            /* no leaf, continue */
+            node = jn->nptr;
+          }
+        }
+        else
+        {
+          /* jn == NULL */
+          climb_tree = 1;
+        }
+      }
+    }
+    else if(node_type == MIB_NODE_EX)
+    {
+      struct mib_external_node *en;
+      s32_t ex_id;
+
+      /* external node (addressing and access via functions) */
+      en = (struct mib_external_node *)node;
+      if (ident_len > 0)
+      {
+        u16_t i, len;
+
+        i = 0;
+        len = en->level_length(en->addr_inf,ext_level);
+        while ((i < len) && (en->ident_cmp(en->addr_inf,ext_level,i,*ident) < 0))
+        {
+          i++;
+        }
+        if (i < len)
+        {
+          /* add identifier to oidret */
+          en->get_objid(en->addr_inf,ext_level,i,&ex_id);
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("en->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,ex_id,*ident));
+          oidret->id[oidret->len] = ex_id;
+          (oidret->len)++;
+
+          if ((ext_level + 1) == en->tree_levels)
+          {
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("leaf node\n"));
+            /* leaf node */
+            if (ex_id > *ident)
+            {
+              return (struct mib_node*)en;
+            }
+            else if ((i + 1) < len)
+            {
+              /* ex_id == *ident */
+              en->get_objid(en->addr_inf,ext_level,i + 1,&ex_id);
+              (oidret->len)--;
+              oidret->id[oidret->len] = ex_id;
+              (oidret->len)++;
+              return (struct mib_node*)en;
+            }
+            else
+            {
+              /* (i + 1) == len */
+              (oidret->len)--;
+              climb_tree = 1;
+            }
+          }
+          else
+          {
+            u8_t j;
+            struct nse cur_node;
+
+            LWIP_DEBUGF(SNMP_MIB_DEBUG,("non-leaf node\n"));
+            /* non-leaf, store right child ptr and id */
+            LWIP_ASSERT("i < 0xff", i < 0xff);
+            j = (u8_t)i + 1;
+            if (j < len)
+            {
+              /* right node is the current external node */
+              cur_node.r_ptr = node;
+              en->get_objid(en->addr_inf,ext_level,j,&cur_node.r_id);
+              cur_node.r_nl = ext_level + 1;
+            }
+            else
+            {
+              cur_node.r_ptr = NULL;
+            }
+            push_node(&cur_node);
+            if (en->ident_cmp(en->addr_inf,ext_level,i,*ident) == 0)
+            {
+              ident_len--;
+              ident++;
+            }
+            else
+            {
+              /* external id < *ident */
+              ident_len = 0;
+            }
+            /* proceed to child */
+            ext_level++;
+          }
+        }
+        else
+        {
+          /* i == len (en->level_len()) */
+          climb_tree = 1;
+        }
+      }
+      else
+      {
+        /* ident_len == 0, complete with leftmost '.thing' */
+        en->get_objid(en->addr_inf,ext_level,0,&ex_id);
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("left en->objid==%"S32_F"\n",ex_id));
+        oidret->id[oidret->len] = ex_id;
+        (oidret->len)++;
+        if ((ext_level + 1) == en->tree_levels)
+        {
+          /* leaf node */
+          LWIP_DEBUGF(SNMP_MIB_DEBUG,("(ext_level + 1) == en->tree_levels\n"));
+          return (struct mib_node*)en;
+        }
+        else
+        {
+          /* no leaf, proceed to child */
+          ext_level++;
+        }
+      }
+    }
+    else if(node_type == MIB_NODE_SC)
+    {
+      mib_scalar_node *sn;
+
+      /* scalar node  */
+      sn = (mib_scalar_node *)node;
+      if (ident_len > 0)
+      {
+        /* at .0 */
+        climb_tree = 1;
+      }
+      else
+      {
+        /* ident_len == 0, complete object identifier */
+        oidret->id[oidret->len] = 0;
+        (oidret->len)++;
+        /* leaf node */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("completed scalar leaf\n"));
+        return (struct mib_node*)sn;
+      }
+    }
+    else
+    {
+      /* unknown/unhandled node_type */
+      LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed node_type %"U16_F" unkown\n",(u16_t)node_type));
+      return NULL;
+    }
+
+    if (climb_tree)
+    {
+      struct nse child;
+
+      /* find right child ptr */
+      child.r_ptr = NULL;
+      child.r_id = 0;
+      child.r_nl = 0;
+      while ((node_stack_cnt > 0) && (child.r_ptr == NULL))
+      {
+        pop_node(&child);
+        /* trim returned oid */
+        (oidret->len)--;
+      }
+      if (child.r_ptr != NULL)
+      {
+        /* incoming ident is useless beyond this point */
+        ident_len = 0;
+        oidret->id[oidret->len] = child.r_id;
+        oidret->len++;
+        node = child.r_ptr;
+        ext_level = child.r_nl;
+      }
+      else
+      {
+        /* tree ends here ... */
+        LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed, tree ends here\n"));
+        return NULL;
+      }
+    }
+  }
+  /* done, found nothing */
+  LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed node==%p\n",(void*)node));
+  return NULL;
+}
+
+/**
+ * Test object identifier for the iso.org.dod.internet prefix.
+ *
+ * @param ident_len the length of the supplied object identifier
+ * @param ident points to the array of sub identifiers
+ * @return 1 if it matches, 0 otherwise
+ */
+u8_t
+snmp_iso_prefix_tst(u8_t ident_len, s32_t *ident)
+{
+  if ((ident_len > 3) &&
+      (ident[0] == 1) && (ident[1] == 3) &&
+      (ident[2] == 6) && (ident[3] == 1))
+  {
+    return 1;
+  }
+  else
+  {
+    return 0;
+  }
+}
+
+/**
+ * Expands object identifier to the iso.org.dod.internet
+ * prefix for use in getnext operation.
+ *
+ * @param ident_len the length of the supplied object identifier
+ * @param ident points to the array of sub identifiers
+ * @param oidret points to returned expanded object identifier
+ * @return 1 if it matches, 0 otherwise
+ *
+ * @note ident_len 0 is allowed, expanding to the first known object id!!
+ */
+u8_t
+snmp_iso_prefix_expand(u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret)
+{
+  const s32_t *prefix_ptr;
+  s32_t *ret_ptr;
+  u8_t i;
+
+  i = 0;
+  prefix_ptr = &prefix[0];
+  ret_ptr = &oidret->id[0];
+  ident_len = ((ident_len < 4)?ident_len:4);
+  while ((i < ident_len) && ((*ident) <= (*prefix_ptr)))
+  {
+    *ret_ptr++ = *prefix_ptr++;
+    ident++;
+    i++;
+  }
+  if (i == ident_len)
+  {
+    /* match, complete missing bits */
+    while (i < 4)
+    {
+      *ret_ptr++ = *prefix_ptr++;
+      i++;
+    }
+    oidret->len = i;
+    return 1;
+  }
+  else
+  {
+    /* i != ident_len */
+    return 0;
+  }
+}
+
+#endif /* LWIP_SNMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/snmp/msg_in.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/snmp/msg_in.c
new file mode 100644
index 0000000..2dfb55b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/snmp/msg_in.c
@@ -0,0 +1,1437 @@
+/**
+ * @file
+ * SNMP input message processing (RFC1157).
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/snmp.h"
+#include "lwip/snmp_asn1.h"
+#include "lwip/snmp_msg.h"
+#include "lwip/snmp_structs.h"
+#include "lwip/ip_addr.h"
+#include "lwip/memp.h"
+#include "lwip/udp.h"
+#include "lwip/stats.h"
+
+#include 
+
+/* public (non-static) constants */
+/** SNMP v1 == 0 */
+const s32_t snmp_version = 0;
+/** default SNMP community string */
+const char snmp_publiccommunity[7] = "public";
+
+/* statically allocated buffers for SNMP_CONCURRENT_REQUESTS */
+struct snmp_msg_pstat msg_input_list[SNMP_CONCURRENT_REQUESTS];
+/* UDP Protocol Control Block */
+struct udp_pcb *snmp1_pcb;
+
+static void snmp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, ip_addr_t *addr, u16_t port);
+static err_t snmp_pdu_header_check(struct pbuf *p, u16_t ofs, u16_t pdu_len, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat);
+static err_t snmp_pdu_dec_varbindlist(struct pbuf *p, u16_t ofs, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat);
+
+
+/**
+ * Starts SNMP Agent.
+ * Allocates UDP pcb and binds it to IP_ADDR_ANY port 161.
+ */
+void
+snmp_init(void)
+{
+  struct snmp_msg_pstat *msg_ps;
+  u8_t i;
+
+  snmp1_pcb = udp_new();
+  if (snmp1_pcb != NULL)
+  {
+    udp_recv(snmp1_pcb, snmp_recv, (void *)SNMP_IN_PORT);
+    udp_bind(snmp1_pcb, IP_ADDR_ANY, SNMP_IN_PORT);
+  }
+  msg_ps = &msg_input_list[0];
+  for (i=0; istate = SNMP_MSG_EMPTY;
+    msg_ps->error_index = 0;
+    msg_ps->error_status = SNMP_ES_NOERROR;
+    msg_ps++;
+  }
+  trap_msg.pcb = snmp1_pcb;
+
+#ifdef SNMP_PRIVATE_MIB_INIT
+  /* If defined, rhis must be a function-like define to initialize the
+   * private MIB after the stack has been initialized.
+   * The private MIB can also be initialized in tcpip_callback (or after
+   * the stack is initialized), this define is only for convenience. */
+  SNMP_PRIVATE_MIB_INIT();
+#endif /* SNMP_PRIVATE_MIB_INIT */
+
+  /* The coldstart trap will only be output
+     if our outgoing interface is up & configured  */
+  snmp_coldstart_trap();
+}
+
+static void
+snmp_error_response(struct snmp_msg_pstat *msg_ps, u8_t error)
+{
+  snmp_varbind_list_free(&msg_ps->outvb);
+  msg_ps->outvb = msg_ps->invb;
+  msg_ps->invb.head = NULL;
+  msg_ps->invb.tail = NULL;
+  msg_ps->invb.count = 0;
+  msg_ps->error_status = error;
+  msg_ps->error_index = 1 + msg_ps->vb_idx;
+  snmp_send_response(msg_ps);
+  snmp_varbind_list_free(&msg_ps->outvb);
+  msg_ps->state = SNMP_MSG_EMPTY;
+}
+
+static void
+snmp_ok_response(struct snmp_msg_pstat *msg_ps)
+{
+  err_t err_ret;
+
+  err_ret = snmp_send_response(msg_ps);
+  if (err_ret == ERR_MEM)
+  {
+    /* serious memory problem, can't return tooBig */
+  }
+  else
+  {
+    LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event = %"S32_F"\n",msg_ps->error_status));
+  }
+  /* free varbinds (if available) */
+  snmp_varbind_list_free(&msg_ps->invb);
+  snmp_varbind_list_free(&msg_ps->outvb);
+  msg_ps->state = SNMP_MSG_EMPTY;
+}
+
+/**
+ * Service an internal or external event for SNMP GET.
+ *
+ * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1)
+ * @param msg_ps points to the assosicated message process state
+ */
+static void
+snmp_msg_get_event(u8_t request_id, struct snmp_msg_pstat *msg_ps)
+{
+  LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_get_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state));
+
+  if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF)
+  {
+    struct mib_external_node *en;
+    struct snmp_name_ptr np;
+
+    /* get_object_def() answer*/
+    en = msg_ps->ext_mib_node;
+    np = msg_ps->ext_name_ptr;
+
+    /* translate answer into a known lifeform */
+    en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def);
+    if ((msg_ps->ext_object_def.instance != MIB_OBJECT_NONE) &&
+        (msg_ps->ext_object_def.access & MIB_ACCESS_READ))
+    {
+      msg_ps->state = SNMP_MSG_EXTERNAL_GET_VALUE;
+      en->get_value_q(request_id, &msg_ps->ext_object_def);
+    }
+    else
+    {
+      en->get_object_def_pc(request_id, np.ident_len, np.ident);
+      /* search failed, object id points to unknown object (nosuchname) */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_VALUE)
+  {
+    struct mib_external_node *en;
+    struct snmp_varbind *vb;
+
+    /* get_value() answer */
+    en = msg_ps->ext_mib_node;
+
+    /* allocate output varbind */
+    vb = (struct snmp_varbind *)memp_malloc(MEMP_SNMP_VARBIND);
+    LWIP_ASSERT("vb != NULL",vb != NULL);
+    if (vb != NULL)
+    {
+      vb->next = NULL;
+      vb->prev = NULL;
+
+      /* move name from invb to outvb */
+      vb->ident = msg_ps->vb_ptr->ident;
+      vb->ident_len = msg_ps->vb_ptr->ident_len;
+      /* ensure this memory is refereced once only */
+      msg_ps->vb_ptr->ident = NULL;
+      msg_ps->vb_ptr->ident_len = 0;
+
+      vb->value_type = msg_ps->ext_object_def.asn_type;
+      LWIP_ASSERT("invalid length", msg_ps->ext_object_def.v_len <= 0xff);
+      vb->value_len = (u8_t)msg_ps->ext_object_def.v_len;
+      if (vb->value_len > 0)
+      {
+        LWIP_ASSERT("SNMP_MAX_OCTET_STRING_LEN is configured too low", vb->value_len <= SNMP_MAX_VALUE_SIZE);
+        vb->value = memp_malloc(MEMP_SNMP_VALUE);
+        LWIP_ASSERT("vb->value != NULL",vb->value != NULL);
+        if (vb->value != NULL)
+        {
+          en->get_value_a(request_id, &msg_ps->ext_object_def, vb->value_len, vb->value);
+          snmp_varbind_tail_add(&msg_ps->outvb, vb);
+          /* search again (if vb_idx < msg_ps->invb.count) */
+          msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+          msg_ps->vb_idx += 1;
+        }
+        else
+        {
+          en->get_value_pc(request_id, &msg_ps->ext_object_def);
+          LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: no variable space\n"));
+          msg_ps->vb_ptr->ident = vb->ident;
+          msg_ps->vb_ptr->ident_len = vb->ident_len;
+          memp_free(MEMP_SNMP_VARBIND, vb);
+          snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+        }
+      }
+      else
+      {
+        /* vb->value_len == 0, empty value (e.g. empty string) */
+        en->get_value_a(request_id, &msg_ps->ext_object_def, 0, NULL);
+        vb->value = NULL;
+        snmp_varbind_tail_add(&msg_ps->outvb, vb);
+        /* search again (if vb_idx < msg_ps->invb.count) */
+        msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+        msg_ps->vb_idx += 1;
+      }
+    }
+    else
+    {
+      en->get_value_pc(request_id, &msg_ps->ext_object_def);
+      LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: no outvb space\n"));
+      snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+    }
+  }
+
+  while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+         (msg_ps->vb_idx < msg_ps->invb.count))
+  {
+    struct mib_node *mn;
+    struct snmp_name_ptr np;
+
+    if (msg_ps->vb_idx == 0)
+    {
+      msg_ps->vb_ptr = msg_ps->invb.head;
+    }
+    else
+    {
+      msg_ps->vb_ptr = msg_ps->vb_ptr->next;
+    }
+    /** test object identifier for .iso.org.dod.internet prefix */
+    if (snmp_iso_prefix_tst(msg_ps->vb_ptr->ident_len,  msg_ps->vb_ptr->ident))
+    {
+      mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4,
+                             msg_ps->vb_ptr->ident + 4, &np);
+      if (mn != NULL)
+      {
+        if (mn->node_type == MIB_NODE_EX)
+        {
+          /* external object */
+          struct mib_external_node *en = (struct mib_external_node*)mn;
+
+          msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF;
+          /* save en && args in msg_ps!! */
+          msg_ps->ext_mib_node = en;
+          msg_ps->ext_name_ptr = np;
+
+          en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident);
+        }
+        else
+        {
+          /* internal object */
+          struct obj_def object_def;
+
+          msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF;
+          mn->get_object_def(np.ident_len, np.ident, &object_def);
+          if ((object_def.instance != MIB_OBJECT_NONE) &&
+            (object_def.access & MIB_ACCESS_READ))
+          {
+            mn = mn;
+          }
+          else
+          {
+            /* search failed, object id points to unknown object (nosuchname) */
+            mn =  NULL;
+          }
+          if (mn != NULL)
+          {
+            struct snmp_varbind *vb;
+
+            msg_ps->state = SNMP_MSG_INTERNAL_GET_VALUE;
+            /* allocate output varbind */
+            vb = (struct snmp_varbind *)memp_malloc(MEMP_SNMP_VARBIND);
+            LWIP_ASSERT("vb != NULL",vb != NULL);
+            if (vb != NULL)
+            {
+              vb->next = NULL;
+              vb->prev = NULL;
+
+              /* move name from invb to outvb */
+              vb->ident = msg_ps->vb_ptr->ident;
+              vb->ident_len = msg_ps->vb_ptr->ident_len;
+              /* ensure this memory is refereced once only */
+              msg_ps->vb_ptr->ident = NULL;
+              msg_ps->vb_ptr->ident_len = 0;
+
+              vb->value_type = object_def.asn_type;
+              LWIP_ASSERT("invalid length", object_def.v_len <= 0xff);
+              vb->value_len = (u8_t)object_def.v_len;
+              if (vb->value_len > 0)
+              {
+                LWIP_ASSERT("SNMP_MAX_OCTET_STRING_LEN is configured too low",
+                  vb->value_len <= SNMP_MAX_VALUE_SIZE);
+                vb->value = memp_malloc(MEMP_SNMP_VALUE);
+                LWIP_ASSERT("vb->value != NULL",vb->value != NULL);
+                if (vb->value != NULL)
+                {
+                  mn->get_value(&object_def, vb->value_len, vb->value);
+                  snmp_varbind_tail_add(&msg_ps->outvb, vb);
+                  msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+                  msg_ps->vb_idx += 1;
+                }
+                else
+                {
+                  LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: couldn't allocate variable space\n"));
+                  msg_ps->vb_ptr->ident = vb->ident;
+                  msg_ps->vb_ptr->ident_len = vb->ident_len;
+                  memp_free(MEMP_SNMP_VARBIND, vb);
+                  snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+                }
+              }
+              else
+              {
+                /* vb->value_len == 0, empty value (e.g. empty string) */
+                vb->value = NULL;
+                snmp_varbind_tail_add(&msg_ps->outvb, vb);
+                msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+                msg_ps->vb_idx += 1;
+              }
+            }
+            else
+            {
+              LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: couldn't allocate outvb space\n"));
+              snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+            }
+          }
+        }
+      }
+    }
+    else
+    {
+      mn = NULL;
+    }
+    if (mn == NULL)
+    {
+      /* mn == NULL, noSuchName */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+      (msg_ps->vb_idx == msg_ps->invb.count))
+  {
+    snmp_ok_response(msg_ps);
+  }
+}
+
+/**
+ * Service an internal or external event for SNMP GETNEXT.
+ *
+ * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1)
+ * @param msg_ps points to the assosicated message process state
+ */
+static void
+snmp_msg_getnext_event(u8_t request_id, struct snmp_msg_pstat *msg_ps)
+{
+  LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_getnext_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state));
+
+  if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF)
+  {
+    struct mib_external_node *en;
+
+    /* get_object_def() answer*/
+    en = msg_ps->ext_mib_node;
+
+    /* translate answer into a known lifeform */
+    en->get_object_def_a(request_id, 1, &msg_ps->ext_oid.id[msg_ps->ext_oid.len - 1], &msg_ps->ext_object_def);
+    if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE)
+    {
+      msg_ps->state = SNMP_MSG_EXTERNAL_GET_VALUE;
+      en->get_value_q(request_id, &msg_ps->ext_object_def);
+    }
+    else
+    {
+      en->get_object_def_pc(request_id, 1, &msg_ps->ext_oid.id[msg_ps->ext_oid.len - 1]);
+      /* search failed, object id points to unknown object (nosuchname) */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_VALUE)
+  {
+    struct mib_external_node *en;
+    struct snmp_varbind *vb;
+
+    /* get_value() answer */
+    en = msg_ps->ext_mib_node;
+
+    LWIP_ASSERT("invalid length", msg_ps->ext_object_def.v_len <= 0xff);
+    vb = snmp_varbind_alloc(&msg_ps->ext_oid,
+                            msg_ps->ext_object_def.asn_type,
+                            (u8_t)msg_ps->ext_object_def.v_len);
+    if (vb != NULL)
+    {
+      en->get_value_a(request_id, &msg_ps->ext_object_def, vb->value_len, vb->value);
+      snmp_varbind_tail_add(&msg_ps->outvb, vb);
+      msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+      msg_ps->vb_idx += 1;
+    }
+    else
+    {
+      en->get_value_pc(request_id, &msg_ps->ext_object_def);
+      LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_getnext_event: couldn't allocate outvb space\n"));
+      snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+    }
+  }
+
+  while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+         (msg_ps->vb_idx < msg_ps->invb.count))
+  {
+    struct mib_node *mn;
+    struct snmp_obj_id oid;
+
+    if (msg_ps->vb_idx == 0)
+    {
+      msg_ps->vb_ptr = msg_ps->invb.head;
+    }
+    else
+    {
+      msg_ps->vb_ptr = msg_ps->vb_ptr->next;
+    }
+    if (snmp_iso_prefix_expand(msg_ps->vb_ptr->ident_len, msg_ps->vb_ptr->ident, &oid))
+    {
+      if (msg_ps->vb_ptr->ident_len > 3)
+      {
+        /* can offset ident_len and ident */
+        mn = snmp_expand_tree((struct mib_node*)&internet,
+                              msg_ps->vb_ptr->ident_len - 4,
+                              msg_ps->vb_ptr->ident + 4, &oid);
+      }
+      else
+      {
+        /* can't offset ident_len -4, ident + 4 */
+        mn = snmp_expand_tree((struct mib_node*)&internet, 0, NULL, &oid);
+      }
+    }
+    else
+    {
+      mn = NULL;
+    }
+    if (mn != NULL)
+    {
+      if (mn->node_type == MIB_NODE_EX)
+      {
+        /* external object */
+        struct mib_external_node *en = (struct mib_external_node*)mn;
+
+        msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF;
+        /* save en && args in msg_ps!! */
+        msg_ps->ext_mib_node = en;
+        msg_ps->ext_oid = oid;
+
+        en->get_object_def_q(en->addr_inf, request_id, 1, &oid.id[oid.len - 1]);
+      }
+      else
+      {
+        /* internal object */
+        struct obj_def object_def;
+        struct snmp_varbind *vb;
+
+        msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF;
+        mn->get_object_def(1, &oid.id[oid.len - 1], &object_def);
+
+        LWIP_ASSERT("invalid length", object_def.v_len <= 0xff);
+        vb = snmp_varbind_alloc(&oid, object_def.asn_type, (u8_t)object_def.v_len);
+        if (vb != NULL)
+        {
+          msg_ps->state = SNMP_MSG_INTERNAL_GET_VALUE;
+          mn->get_value(&object_def, object_def.v_len, vb->value);
+          snmp_varbind_tail_add(&msg_ps->outvb, vb);
+          msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+          msg_ps->vb_idx += 1;
+        }
+        else
+        {
+          LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv couldn't allocate outvb space\n"));
+          snmp_error_response(msg_ps,SNMP_ES_TOOBIG);
+        }
+      }
+    }
+    if (mn == NULL)
+    {
+      /* mn == NULL, noSuchName */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+      (msg_ps->vb_idx == msg_ps->invb.count))
+  {
+    snmp_ok_response(msg_ps);
+  }
+}
+
+/**
+ * Service an internal or external event for SNMP SET.
+ *
+ * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1)
+ * @param msg_ps points to the assosicated message process state
+ */
+static void
+snmp_msg_set_event(u8_t request_id, struct snmp_msg_pstat *msg_ps)
+{
+  LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_set_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state));
+
+  if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF)
+  {
+    struct mib_external_node *en;
+    struct snmp_name_ptr np;
+
+    /* get_object_def() answer*/
+    en = msg_ps->ext_mib_node;
+    np = msg_ps->ext_name_ptr;
+
+    /* translate answer into a known lifeform */
+    en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def);
+    if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE)
+    {
+      msg_ps->state = SNMP_MSG_EXTERNAL_SET_TEST;
+      en->set_test_q(request_id, &msg_ps->ext_object_def);
+    }
+    else
+    {
+      en->get_object_def_pc(request_id, np.ident_len, np.ident);
+      /* search failed, object id points to unknown object (nosuchname) */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  else if (msg_ps->state == SNMP_MSG_EXTERNAL_SET_TEST)
+  {
+    struct mib_external_node *en;
+
+    /* set_test() answer*/
+    en = msg_ps->ext_mib_node;
+
+    if (msg_ps->ext_object_def.access & MIB_ACCESS_WRITE)
+    {
+       if ((msg_ps->ext_object_def.asn_type == msg_ps->vb_ptr->value_type) &&
+           (en->set_test_a(request_id,&msg_ps->ext_object_def,
+                           msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value) != 0))
+      {
+        msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+        msg_ps->vb_idx += 1;
+      }
+      else
+      {
+        en->set_test_pc(request_id,&msg_ps->ext_object_def);
+        /* bad value */
+        snmp_error_response(msg_ps,SNMP_ES_BADVALUE);
+      }
+    }
+    else
+    {
+      en->set_test_pc(request_id,&msg_ps->ext_object_def);
+      /* object not available for set */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+  else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF_S)
+  {
+    struct mib_external_node *en;
+    struct snmp_name_ptr np;
+
+    /* get_object_def() answer*/
+    en = msg_ps->ext_mib_node;
+    np = msg_ps->ext_name_ptr;
+
+    /* translate answer into a known lifeform */
+    en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def);
+    if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE)
+    {
+      msg_ps->state = SNMP_MSG_EXTERNAL_SET_VALUE;
+      en->set_value_q(request_id, &msg_ps->ext_object_def,
+                      msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value);
+    }
+    else
+    {
+      en->get_object_def_pc(request_id, np.ident_len, np.ident);
+      /* set_value failed, object has disappeared for some odd reason?? */
+      snmp_error_response(msg_ps,SNMP_ES_GENERROR);
+    }
+  }
+  else if (msg_ps->state == SNMP_MSG_EXTERNAL_SET_VALUE)
+  {
+    struct mib_external_node *en;
+
+    /** set_value_a() */
+    en = msg_ps->ext_mib_node;
+    en->set_value_a(request_id, &msg_ps->ext_object_def,
+      msg_ps->vb_ptr->value_len, msg_ps->vb_ptr->value);
+
+    /** @todo use set_value_pc() if toobig */
+    msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE;
+    msg_ps->vb_idx += 1;
+  }
+
+  /* test all values before setting */
+  while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+         (msg_ps->vb_idx < msg_ps->invb.count))
+  {
+    struct mib_node *mn;
+    struct snmp_name_ptr np;
+
+    if (msg_ps->vb_idx == 0)
+    {
+      msg_ps->vb_ptr = msg_ps->invb.head;
+    }
+    else
+    {
+      msg_ps->vb_ptr = msg_ps->vb_ptr->next;
+    }
+    /** test object identifier for .iso.org.dod.internet prefix */
+    if (snmp_iso_prefix_tst(msg_ps->vb_ptr->ident_len,  msg_ps->vb_ptr->ident))
+    {
+      mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4,
+                             msg_ps->vb_ptr->ident + 4, &np);
+      if (mn != NULL)
+      {
+        if (mn->node_type == MIB_NODE_EX)
+        {
+          /* external object */
+          struct mib_external_node *en = (struct mib_external_node*)mn;
+
+          msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF;
+          /* save en && args in msg_ps!! */
+          msg_ps->ext_mib_node = en;
+          msg_ps->ext_name_ptr = np;
+
+          en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident);
+        }
+        else
+        {
+          /* internal object */
+          struct obj_def object_def;
+
+          msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF;
+          mn->get_object_def(np.ident_len, np.ident, &object_def);
+          if (object_def.instance != MIB_OBJECT_NONE)
+          {
+            mn = mn;
+          }
+          else
+          {
+            /* search failed, object id points to unknown object (nosuchname) */
+            mn = NULL;
+          }
+          if (mn != NULL)
+          {
+            msg_ps->state = SNMP_MSG_INTERNAL_SET_TEST;
+
+            if (object_def.access & MIB_ACCESS_WRITE)
+            {
+              if ((object_def.asn_type == msg_ps->vb_ptr->value_type) &&
+                  (mn->set_test(&object_def,msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value) != 0))
+              {
+                msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+                msg_ps->vb_idx += 1;
+              }
+              else
+              {
+                /* bad value */
+                snmp_error_response(msg_ps,SNMP_ES_BADVALUE);
+              }
+            }
+            else
+            {
+              /* object not available for set */
+              snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+            }
+          }
+        }
+      }
+    }
+    else
+    {
+      mn = NULL;
+    }
+    if (mn == NULL)
+    {
+      /* mn == NULL, noSuchName */
+      snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME);
+    }
+  }
+
+  if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) &&
+      (msg_ps->vb_idx == msg_ps->invb.count))
+  {
+    msg_ps->vb_idx = 0;
+    msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE;
+  }
+
+  /* set all values "atomically" (be as "atomic" as possible) */
+  while ((msg_ps->state == SNMP_MSG_INTERNAL_SET_VALUE) &&
+         (msg_ps->vb_idx < msg_ps->invb.count))
+  {
+    struct mib_node *mn;
+    struct snmp_name_ptr np;
+
+    if (msg_ps->vb_idx == 0)
+    {
+      msg_ps->vb_ptr = msg_ps->invb.head;
+    }
+    else
+    {
+      msg_ps->vb_ptr = msg_ps->vb_ptr->next;
+    }
+    /* skip iso prefix test, was done previously while settesting() */
+    mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4,
+                           msg_ps->vb_ptr->ident + 4, &np);
+    /* check if object is still available
+       (e.g. external hot-plug thingy present?) */
+    if (mn != NULL)
+    {
+      if (mn->node_type == MIB_NODE_EX)
+      {
+        /* external object */
+        struct mib_external_node *en = (struct mib_external_node*)mn;
+
+        msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF_S;
+        /* save en && args in msg_ps!! */
+        msg_ps->ext_mib_node = en;
+        msg_ps->ext_name_ptr = np;
+
+        en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident);
+      }
+      else
+      {
+        /* internal object */
+        struct obj_def object_def;
+
+        msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF_S;
+        mn->get_object_def(np.ident_len, np.ident, &object_def);
+        msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE;
+        mn->set_value(&object_def,msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value);
+        msg_ps->vb_idx += 1;
+      }
+    }
+  }
+  if ((msg_ps->state == SNMP_MSG_INTERNAL_SET_VALUE) &&
+      (msg_ps->vb_idx == msg_ps->invb.count))
+  {
+    /* simply echo the input if we can set it
+       @todo do we need to return the actual value?
+       e.g. if value is silently modified or behaves sticky? */
+    msg_ps->outvb = msg_ps->invb;
+    msg_ps->invb.head = NULL;
+    msg_ps->invb.tail = NULL;
+    msg_ps->invb.count = 0;
+    snmp_ok_response(msg_ps);
+  }
+}
+
+
+/**
+ * Handle one internal or external event.
+ * Called for one async event. (recv external/private answer)
+ *
+ * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1)
+ */
+void
+snmp_msg_event(u8_t request_id)
+{
+  struct snmp_msg_pstat *msg_ps;
+
+  if (request_id < SNMP_CONCURRENT_REQUESTS)
+  {
+    msg_ps = &msg_input_list[request_id];
+    if (msg_ps->rt == SNMP_ASN1_PDU_GET_NEXT_REQ)
+    {
+      snmp_msg_getnext_event(request_id, msg_ps);
+    }
+    else if (msg_ps->rt == SNMP_ASN1_PDU_GET_REQ)
+    {
+      snmp_msg_get_event(request_id, msg_ps);
+    }
+    else if(msg_ps->rt == SNMP_ASN1_PDU_SET_REQ)
+    {
+      snmp_msg_set_event(request_id, msg_ps);
+    }
+  }
+}
+
+
+/* lwIP UDP receive callback function */
+static void
+snmp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, ip_addr_t *addr, u16_t port)
+{
+  struct snmp_msg_pstat *msg_ps;
+  u8_t req_idx;
+  err_t err_ret;
+  u16_t payload_len = p->tot_len;
+  u16_t payload_ofs = 0;
+  u16_t varbind_ofs = 0;
+
+  /* suppress unused argument warning */
+  LWIP_UNUSED_ARG(arg);
+
+  /* traverse input message process list, look for SNMP_MSG_EMPTY */
+  msg_ps = &msg_input_list[0];
+  req_idx = 0;
+  while ((req_idx < SNMP_CONCURRENT_REQUESTS) && (msg_ps->state != SNMP_MSG_EMPTY))
+  {
+    req_idx++;
+    msg_ps++;
+  }
+  if (req_idx == SNMP_CONCURRENT_REQUESTS)
+  {
+    /* exceeding number of concurrent requests */
+    pbuf_free(p);
+    return;
+  }
+
+  /* accepting request */
+  snmp_inc_snmpinpkts();
+  /* record used 'protocol control block' */
+  msg_ps->pcb = pcb;
+  /* source address (network order) */
+  msg_ps->sip = *addr;
+  /* source port (host order (lwIP oddity)) */
+  msg_ps->sp = port;
+
+  /* check total length, version, community, pdu type */
+  err_ret = snmp_pdu_header_check(p, payload_ofs, payload_len, &varbind_ofs, msg_ps);
+  /* Only accept requests and requests without error (be robust) */
+  /* Reject response and trap headers or error requests as input! */
+  if ((err_ret != ERR_OK) ||
+      ((msg_ps->rt != SNMP_ASN1_PDU_GET_REQ) &&
+       (msg_ps->rt != SNMP_ASN1_PDU_GET_NEXT_REQ) &&
+       (msg_ps->rt != SNMP_ASN1_PDU_SET_REQ)) ||
+      ((msg_ps->error_status != SNMP_ES_NOERROR) ||
+       (msg_ps->error_index != 0)) )
+  {
+    /* header check failed drop request silently, do not return error! */
+    pbuf_free(p);
+    LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_pdu_header_check() failed\n"));
+    return;
+  }
+  LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv ok, community %s\n", msg_ps->community));
+
+  /* Builds a list of variable bindings. Copy the varbinds from the pbuf
+    chain to glue them when these are divided over two or more pbuf's. */
+  err_ret = snmp_pdu_dec_varbindlist(p, varbind_ofs, &varbind_ofs, msg_ps);
+  /* we've decoded the incoming message, release input msg now */
+  pbuf_free(p);
+  if ((err_ret != ERR_OK) || (msg_ps->invb.count == 0))
+  {
+    /* varbind-list decode failed, or varbind list empty.
+       drop request silently, do not return error!
+       (errors are only returned for a specific varbind failure) */
+    LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_pdu_dec_varbindlist() failed\n"));
+    return;
+  }
+
+  msg_ps->error_status = SNMP_ES_NOERROR;
+  msg_ps->error_index = 0;
+  /* find object for each variable binding */
+  msg_ps->state = SNMP_MSG_SEARCH_OBJ;
+  /* first variable binding from list to inspect */
+  msg_ps->vb_idx = 0;
+
+  LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv varbind cnt=%"U16_F"\n",(u16_t)msg_ps->invb.count));
+
+  /* handle input event and as much objects as possible in one go */
+  snmp_msg_event(req_idx);
+}
+
+/**
+ * Checks and decodes incoming SNMP message header, logs header errors.
+ *
+ * @param p points to pbuf chain of SNMP message (UDP payload)
+ * @param ofs points to first octet of SNMP message
+ * @param pdu_len the length of the UDP payload
+ * @param ofs_ret returns the ofset of the variable bindings
+ * @param m_stat points to the current message request state return
+ * @return
+ * - ERR_OK SNMP header is sane and accepted
+ * - ERR_ARG SNMP header is either malformed or rejected
+ */
+static err_t
+snmp_pdu_header_check(struct pbuf *p, u16_t ofs, u16_t pdu_len, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat)
+{
+  err_t derr;
+  u16_t len, ofs_base;
+  u8_t  len_octets;
+  u8_t  type;
+  s32_t version;
+
+  ofs_base = ofs;
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) ||
+      (pdu_len != (1 + len_octets + len)) ||
+      (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)))
+  {
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets);
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)))
+  {
+    /* can't decode or no integer (version) */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &version);
+  if (derr != ERR_OK)
+  {
+    /* can't decode */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  if (version != 0)
+  {
+    /* not version 1 */
+    snmp_inc_snmpinbadversions();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets + len);
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR)))
+  {
+    /* can't decode or no octet string (community) */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, SNMP_COMMUNITY_STR_LEN, m_stat->community);
+  if (derr != ERR_OK)
+  {
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  /* add zero terminator */
+  len = ((len < (SNMP_COMMUNITY_STR_LEN))?(len):(SNMP_COMMUNITY_STR_LEN));
+  m_stat->community[len] = 0;
+  m_stat->com_strlen = (u8_t)len;
+  if (strncmp(snmp_publiccommunity, (const char*)m_stat->community, SNMP_COMMUNITY_STR_LEN) != 0)
+  {
+    /** @todo: move this if we need to check more names */
+    snmp_inc_snmpinbadcommunitynames();
+    snmp_authfail_trap();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets + len);
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if (derr != ERR_OK)
+  {
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  switch(type)
+  {
+    case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_REQ):
+      /* GetRequest PDU */
+      snmp_inc_snmpingetrequests();
+      derr = ERR_OK;
+      break;
+    case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_NEXT_REQ):
+      /* GetNextRequest PDU */
+      snmp_inc_snmpingetnexts();
+      derr = ERR_OK;
+      break;
+    case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_RESP):
+      /* GetResponse PDU */
+      snmp_inc_snmpingetresponses();
+      derr = ERR_ARG;
+      break;
+    case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_SET_REQ):
+      /* SetRequest PDU */
+      snmp_inc_snmpinsetrequests();
+      derr = ERR_OK;
+      break;
+    case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_TRAP):
+      /* Trap PDU */
+      snmp_inc_snmpintraps();
+      derr = ERR_ARG;
+      break;
+    default:
+      snmp_inc_snmpinasnparseerrs();
+      derr = ERR_ARG;
+      break;
+  }
+  if (derr != ERR_OK)
+  {
+    /* unsupported input PDU for this agent (no parse error) */
+    return ERR_ARG;
+  }
+  m_stat->rt = type & 0x1F;
+  ofs += (1 + len_octets);
+  if (len != (pdu_len - (ofs - ofs_base)))
+  {
+    /* decoded PDU length does not equal actual payload length */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)))
+  {
+    /* can't decode or no integer (request ID) */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->rid);
+  if (derr != ERR_OK)
+  {
+    /* can't decode */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets + len);
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)))
+  {
+    /* can't decode or no integer (error-status) */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  /* must be noError (0) for incoming requests.
+     log errors for mib-2 completeness and for debug purposes */
+  derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->error_status);
+  if (derr != ERR_OK)
+  {
+    /* can't decode */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  switch (m_stat->error_status)
+  {
+    case SNMP_ES_TOOBIG:
+      snmp_inc_snmpintoobigs();
+      break;
+    case SNMP_ES_NOSUCHNAME:
+      snmp_inc_snmpinnosuchnames();
+      break;
+    case SNMP_ES_BADVALUE:
+      snmp_inc_snmpinbadvalues();
+      break;
+    case SNMP_ES_READONLY:
+      snmp_inc_snmpinreadonlys();
+      break;
+    case SNMP_ES_GENERROR:
+      snmp_inc_snmpingenerrs();
+      break;
+  }
+  ofs += (1 + len_octets + len);
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+  if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)))
+  {
+    /* can't decode or no integer (error-index) */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  /* must be 0 for incoming requests.
+     decode anyway to catch bad integers (and dirty tricks) */
+  derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->error_index);
+  if (derr != ERR_OK)
+  {
+    /* can't decode */
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets + len);
+  *ofs_ret = ofs;
+  return ERR_OK;
+}
+
+static err_t
+snmp_pdu_dec_varbindlist(struct pbuf *p, u16_t ofs, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat)
+{
+  err_t derr;
+  u16_t len, vb_len;
+  u8_t  len_octets;
+  u8_t type;
+
+  /* variable binding list */
+  snmp_asn1_dec_type(p, ofs, &type);
+  derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &vb_len);
+  if ((derr != ERR_OK) ||
+      (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)))
+  {
+    snmp_inc_snmpinasnparseerrs();
+    return ERR_ARG;
+  }
+  ofs += (1 + len_octets);
+
+  /* start with empty list */
+  m_stat->invb.count = 0;
+  m_stat->invb.head = NULL;
+  m_stat->invb.tail = NULL;
+
+  while (vb_len > 0)
+  {
+    struct snmp_obj_id oid, oid_value;
+    struct snmp_varbind *vb;
+
+    snmp_asn1_dec_type(p, ofs, &type);
+    derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+    if ((derr != ERR_OK) ||
+        (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)) ||
+        (len == 0) || (len > vb_len))
+    {
+      snmp_inc_snmpinasnparseerrs();
+      /* free varbinds (if available) */
+      snmp_varbind_list_free(&m_stat->invb);
+      return ERR_ARG;
+    }
+    ofs += (1 + len_octets);
+    vb_len -= (1 + len_octets);
+
+    snmp_asn1_dec_type(p, ofs, &type);
+    derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+    if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID)))
+    {
+      /* can't decode object name length */
+      snmp_inc_snmpinasnparseerrs();
+      /* free varbinds (if available) */
+      snmp_varbind_list_free(&m_stat->invb);
+      return ERR_ARG;
+    }
+    derr = snmp_asn1_dec_oid(p, ofs + 1 + len_octets, len, &oid);
+    if (derr != ERR_OK)
+    {
+      /* can't decode object name */
+      snmp_inc_snmpinasnparseerrs();
+      /* free varbinds (if available) */
+      snmp_varbind_list_free(&m_stat->invb);
+      return ERR_ARG;
+    }
+    ofs += (1 + len_octets + len);
+    vb_len -= (1 + len_octets + len);
+
+    snmp_asn1_dec_type(p, ofs, &type);
+    derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len);
+    if (derr != ERR_OK)
+    {
+      /* can't decode object value length */
+      snmp_inc_snmpinasnparseerrs();
+      /* free varbinds (if available) */
+      snmp_varbind_list_free(&m_stat->invb);
+      return ERR_ARG;
+    }
+
+    switch (type)
+    {
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG):
+        vb = snmp_varbind_alloc(&oid, type, sizeof(s32_t));
+        if (vb != NULL)
+        {
+          s32_t *vptr = (s32_t*)vb->value;
+
+          derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, vptr);
+          snmp_varbind_tail_add(&m_stat->invb, vb);
+        }
+        else
+        {
+          derr = ERR_ARG;
+        }
+        break;
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS):
+        vb = snmp_varbind_alloc(&oid, type, sizeof(u32_t));
+        if (vb != NULL)
+        {
+          u32_t *vptr = (u32_t*)vb->value;
+
+          derr = snmp_asn1_dec_u32t(p, ofs + 1 + len_octets, len, vptr);
+          snmp_varbind_tail_add(&m_stat->invb, vb);
+        }
+        else
+        {
+          derr = ERR_ARG;
+        }
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE):
+        LWIP_ASSERT("invalid length", len <= 0xff);
+        vb = snmp_varbind_alloc(&oid, type, (u8_t)len);
+        if (vb != NULL)
+        {
+          derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, vb->value_len, (u8_t*)vb->value);
+          snmp_varbind_tail_add(&m_stat->invb, vb);
+        }
+        else
+        {
+          derr = ERR_ARG;
+        }
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL):
+        vb = snmp_varbind_alloc(&oid, type, 0);
+        if (vb != NULL)
+        {
+          snmp_varbind_tail_add(&m_stat->invb, vb);
+          derr = ERR_OK;
+        }
+        else
+        {
+          derr = ERR_ARG;
+        }
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID):
+        derr = snmp_asn1_dec_oid(p, ofs + 1 + len_octets, len, &oid_value);
+        if (derr == ERR_OK)
+        {
+          vb = snmp_varbind_alloc(&oid, type, oid_value.len * sizeof(s32_t));
+          if (vb != NULL)
+          {
+            u8_t i = oid_value.len;
+            s32_t *vptr = (s32_t*)vb->value;
+
+            while(i > 0)
+            {
+              i--;
+              vptr[i] = oid_value.id[i];
+            }
+            snmp_varbind_tail_add(&m_stat->invb, vb);
+            derr = ERR_OK;
+          }
+          else
+          {
+            derr = ERR_ARG;
+          }
+        }
+        break;
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR):
+        if (len == 4)
+        {
+          /* must be exactly 4 octets! */
+          vb = snmp_varbind_alloc(&oid, type, 4);
+          if (vb != NULL)
+          {
+            derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, vb->value_len, (u8_t*)vb->value);
+            snmp_varbind_tail_add(&m_stat->invb, vb);
+          }
+          else
+          {
+            derr = ERR_ARG;
+          }
+        }
+        else
+        {
+          derr = ERR_ARG;
+        }
+        break;
+      default:
+        derr = ERR_ARG;
+        break;
+    }
+    if (derr != ERR_OK)
+    {
+      snmp_inc_snmpinasnparseerrs();
+      /* free varbinds (if available) */
+      snmp_varbind_list_free(&m_stat->invb);
+      return ERR_ARG;
+    }
+    ofs += (1 + len_octets + len);
+    vb_len -= (1 + len_octets + len);
+  }
+
+  if (m_stat->rt == SNMP_ASN1_PDU_SET_REQ)
+  {
+    snmp_add_snmpintotalsetvars(m_stat->invb.count);
+  }
+  else
+  {
+    snmp_add_snmpintotalreqvars(m_stat->invb.count);
+  }
+
+  *ofs_ret = ofs;
+  return ERR_OK;
+}
+
+struct snmp_varbind*
+snmp_varbind_alloc(struct snmp_obj_id *oid, u8_t type, u8_t len)
+{
+  struct snmp_varbind *vb;
+
+  vb = (struct snmp_varbind *)memp_malloc(MEMP_SNMP_VARBIND);
+  LWIP_ASSERT("vb != NULL",vb != NULL);
+  if (vb != NULL)
+  {
+    u8_t i;
+
+    vb->next = NULL;
+    vb->prev = NULL;
+    i = oid->len;
+    vb->ident_len = i;
+    if (i > 0)
+    {
+      LWIP_ASSERT("SNMP_MAX_TREE_DEPTH is configured too low", i <= SNMP_MAX_TREE_DEPTH);
+      /* allocate array of s32_t for our object identifier */
+      vb->ident = (s32_t*)memp_malloc(MEMP_SNMP_VALUE);
+      LWIP_ASSERT("vb->ident != NULL",vb->ident != NULL);
+      if (vb->ident == NULL)
+      {
+        memp_free(MEMP_SNMP_VARBIND, vb);
+        return NULL;
+      }
+      while(i > 0)
+      {
+        i--;
+        vb->ident[i] = oid->id[i];
+      }
+    }
+    else
+    {
+      /* i == 0, pass zero length object identifier */
+      vb->ident = NULL;
+    }
+    vb->value_type = type;
+    vb->value_len = len;
+    if (len > 0)
+    {
+      LWIP_ASSERT("SNMP_MAX_OCTET_STRING_LEN is configured too low", vb->value_len <= SNMP_MAX_VALUE_SIZE);
+      /* allocate raw bytes for our object value */
+      vb->value = memp_malloc(MEMP_SNMP_VALUE);
+      LWIP_ASSERT("vb->value != NULL",vb->value != NULL);
+      if (vb->value == NULL)
+      {
+        if (vb->ident != NULL)
+        {
+          memp_free(MEMP_SNMP_VALUE, vb->ident);
+        }
+        memp_free(MEMP_SNMP_VARBIND, vb);
+        return NULL;
+      }
+    }
+    else
+    {
+      /* ASN1_NUL type, or zero length ASN1_OC_STR */
+      vb->value = NULL;
+    }
+  }
+  return vb;
+}
+
+void
+snmp_varbind_free(struct snmp_varbind *vb)
+{
+  if (vb->value != NULL )
+  {
+    memp_free(MEMP_SNMP_VALUE, vb->value);
+  }
+  if (vb->ident != NULL )
+  {
+    memp_free(MEMP_SNMP_VALUE, vb->ident);
+  }
+  memp_free(MEMP_SNMP_VARBIND, vb);
+}
+
+void
+snmp_varbind_list_free(struct snmp_varbind_root *root)
+{
+  struct snmp_varbind *vb, *prev;
+
+  vb = root->tail;
+  while ( vb != NULL )
+  {
+    prev = vb->prev;
+    snmp_varbind_free(vb);
+    vb = prev;
+  }
+  root->count = 0;
+  root->head = NULL;
+  root->tail = NULL;
+}
+
+void
+snmp_varbind_tail_add(struct snmp_varbind_root *root, struct snmp_varbind *vb)
+{
+  if (root->count == 0)
+  {
+    /* add first varbind to list */
+    root->head = vb;
+    root->tail = vb;
+  }
+  else
+  {
+    /* add nth varbind to list tail */
+    root->tail->next = vb;
+    vb->prev = root->tail;
+    root->tail = vb;
+  }
+  root->count += 1;
+}
+
+struct snmp_varbind*
+snmp_varbind_tail_remove(struct snmp_varbind_root *root)
+{
+  struct snmp_varbind* vb;
+
+  if (root->count > 0)
+  {
+    /* remove tail varbind */
+    vb = root->tail;
+    root->tail = vb->prev;
+    vb->prev->next = NULL;
+    root->count -= 1;
+  }
+  else
+  {
+    /* nothing to remove */
+    vb = NULL;
+  }
+  return vb;
+}
+
+#endif /* LWIP_SNMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/snmp/msg_out.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/snmp/msg_out.c
new file mode 100644
index 0000000..4778bee
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/snmp/msg_out.c
@@ -0,0 +1,681 @@
+/**
+ * @file
+ * SNMP output message processing (RFC1157).
+ *
+ * Output responses and traps are build in two passes:
+ *
+ * Pass 0: iterate over the output message backwards to determine encoding lengths
+ * Pass 1: the actual forward encoding of internal form into ASN1
+ *
+ * The single-pass encoding method described by Comer & Stevens
+ * requires extra buffer space and copying for reversal of the packet.
+ * The buffer requirement can be prohibitively large for big payloads
+ * (>= 484) therefore we use the two encoding passes.
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/udp.h"
+#include "lwip/netif.h"
+#include "lwip/snmp.h"
+#include "lwip/snmp_asn1.h"
+#include "lwip/snmp_msg.h"
+
+struct snmp_trap_dst
+{
+  /* destination IP address in network order */
+  ip_addr_t dip;
+  /* set to 0 when disabled, >0 when enabled */
+  u8_t enable;
+};
+struct snmp_trap_dst trap_dst[SNMP_TRAP_DESTINATIONS];
+
+/** TRAP message structure */
+struct snmp_msg_trap trap_msg;
+
+static u16_t snmp_resp_header_sum(struct snmp_msg_pstat *m_stat, u16_t vb_len);
+static u16_t snmp_trap_header_sum(struct snmp_msg_trap *m_trap, u16_t vb_len);
+static u16_t snmp_varbind_list_sum(struct snmp_varbind_root *root);
+
+static u16_t snmp_resp_header_enc(struct snmp_msg_pstat *m_stat, struct pbuf *p);
+static u16_t snmp_trap_header_enc(struct snmp_msg_trap *m_trap, struct pbuf *p);
+static u16_t snmp_varbind_list_enc(struct snmp_varbind_root *root, struct pbuf *p, u16_t ofs);
+
+/**
+ * Sets enable switch for this trap destination.
+ * @param dst_idx index in 0 .. SNMP_TRAP_DESTINATIONS-1
+ * @param enable switch if 0 destination is disabled >0 enabled.
+ */
+void
+snmp_trap_dst_enable(u8_t dst_idx, u8_t enable)
+{
+  if (dst_idx < SNMP_TRAP_DESTINATIONS)
+  {
+    trap_dst[dst_idx].enable = enable;
+  }
+}
+
+/**
+ * Sets IPv4 address for this trap destination.
+ * @param dst_idx index in 0 .. SNMP_TRAP_DESTINATIONS-1
+ * @param dst IPv4 address in host order.
+ */
+void
+snmp_trap_dst_ip_set(u8_t dst_idx, ip_addr_t *dst)
+{
+  if (dst_idx < SNMP_TRAP_DESTINATIONS)
+  {
+    ip_addr_set(&trap_dst[dst_idx].dip, dst);
+  }
+}
+
+/**
+ * Sends a 'getresponse' message to the request originator.
+ *
+ * @param m_stat points to the current message request state source
+ * @return ERR_OK when success, ERR_MEM if we're out of memory
+ *
+ * @note the caller is responsible for filling in outvb in the m_stat
+ * and provide error-status and index (except for tooBig errors) ...
+ */
+err_t
+snmp_send_response(struct snmp_msg_pstat *m_stat)
+{
+  struct snmp_varbind_root emptyvb = {NULL, NULL, 0, 0, 0};
+  struct pbuf *p;
+  u16_t tot_len;
+  err_t err;
+
+  /* pass 0, calculate length fields */
+  tot_len = snmp_varbind_list_sum(&m_stat->outvb);
+  tot_len = snmp_resp_header_sum(m_stat, tot_len);
+
+  /* try allocating pbuf(s) for complete response */
+  p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL);
+  if (p == NULL)
+  {
+    LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() tooBig\n"));
+
+    /* can't construct reply, return error-status tooBig */
+    m_stat->error_status = SNMP_ES_TOOBIG;
+    m_stat->error_index = 0;
+    /* pass 0, recalculate lengths, for empty varbind-list */
+    tot_len = snmp_varbind_list_sum(&emptyvb);
+    tot_len = snmp_resp_header_sum(m_stat, tot_len);
+    /* retry allocation once for header and empty varbind-list */
+    p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL);
+  }
+  if (p != NULL)
+  {
+    /* first pbuf alloc try or retry alloc success */
+    u16_t ofs;
+
+    LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() p != NULL\n"));
+
+    /* pass 1, size error, encode packet ino the pbuf(s) */
+    ofs = snmp_resp_header_enc(m_stat, p);
+    if (m_stat->error_status == SNMP_ES_TOOBIG)
+    {
+      snmp_varbind_list_enc(&emptyvb, p, ofs);
+    }
+    else
+    {
+      snmp_varbind_list_enc(&m_stat->outvb, p, ofs);
+    }
+
+    switch (m_stat->error_status)
+    {
+      case SNMP_ES_TOOBIG:
+        snmp_inc_snmpouttoobigs();
+        break;
+      case SNMP_ES_NOSUCHNAME:
+        snmp_inc_snmpoutnosuchnames();
+        break;
+      case SNMP_ES_BADVALUE:
+        snmp_inc_snmpoutbadvalues();
+        break;
+      case SNMP_ES_GENERROR:
+        snmp_inc_snmpoutgenerrs();
+        break;
+    }
+    snmp_inc_snmpoutgetresponses();
+    snmp_inc_snmpoutpkts();
+
+    /** @todo do we need separate rx and tx pcbs for threaded case? */
+    /** connect to the originating source */
+    udp_connect(m_stat->pcb, &m_stat->sip, m_stat->sp);
+    err = udp_send(m_stat->pcb, p);
+    if (err == ERR_MEM)
+    {
+      /** @todo release some memory, retry and return tooBig? tooMuchHassle? */
+      err = ERR_MEM;
+    }
+    else
+    {
+      err = ERR_OK;
+    }
+    /** disassociate remote address and port with this pcb */
+    udp_disconnect(m_stat->pcb);
+
+    pbuf_free(p);
+    LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() done\n"));
+    return err;
+  }
+  else
+  {
+    /* first pbuf alloc try or retry alloc failed
+       very low on memory, couldn't return tooBig */
+    return ERR_MEM;
+  }
+}
+
+
+/**
+ * Sends an generic or enterprise specific trap message.
+ *
+ * @param generic_trap is the trap code
+ * @param eoid points to enterprise object identifier
+ * @param specific_trap used for enterprise traps when generic_trap == 6
+ * @return ERR_OK when success, ERR_MEM if we're out of memory
+ *
+ * @note the caller is responsible for filling in outvb in the trap_msg
+ * @note the use of the enterpise identifier field
+ * is per RFC1215.
+ * Use .iso.org.dod.internet.mgmt.mib-2.snmp for generic traps
+ * and .iso.org.dod.internet.private.enterprises.yourenterprise
+ * (sysObjectID) for specific traps.
+ */
+err_t
+snmp_send_trap(s8_t generic_trap, struct snmp_obj_id *eoid, s32_t specific_trap)
+{
+  struct snmp_trap_dst *td;
+  struct netif *dst_if;
+  ip_addr_t dst_ip;
+  struct pbuf *p;
+  u16_t i,tot_len;
+
+  for (i=0, td = &trap_dst[0]; ienable != 0) && !ip_addr_isany(&td->dip))
+    {
+      /* network order trap destination */
+      ip_addr_copy(trap_msg.dip, td->dip);
+      /* lookup current source address for this dst */
+      dst_if = ip_route(&td->dip);
+      ip_addr_copy(dst_ip, dst_if->ip_addr);
+      /* @todo: what about IPv6? */
+      trap_msg.sip_raw[0] = ip4_addr1(&dst_ip);
+      trap_msg.sip_raw[1] = ip4_addr2(&dst_ip);
+      trap_msg.sip_raw[2] = ip4_addr3(&dst_ip);
+      trap_msg.sip_raw[3] = ip4_addr4(&dst_ip);
+      trap_msg.gen_trap = generic_trap;
+      trap_msg.spc_trap = specific_trap;
+      if (generic_trap == SNMP_GENTRAP_ENTERPRISESPC)
+      {
+        /* enterprise-Specific trap */
+        trap_msg.enterprise = eoid;
+      }
+      else
+      {
+        /* generic (MIB-II) trap */
+        snmp_get_snmpgrpid_ptr(&trap_msg.enterprise);
+      }
+      snmp_get_sysuptime(&trap_msg.ts);
+
+      /* pass 0, calculate length fields */
+      tot_len = snmp_varbind_list_sum(&trap_msg.outvb);
+      tot_len = snmp_trap_header_sum(&trap_msg, tot_len);
+
+      /* allocate pbuf(s) */
+      p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL);
+      if (p != NULL)
+      {
+        u16_t ofs;
+
+        /* pass 1, encode packet ino the pbuf(s) */
+        ofs = snmp_trap_header_enc(&trap_msg, p);
+        snmp_varbind_list_enc(&trap_msg.outvb, p, ofs);
+
+        snmp_inc_snmpouttraps();
+        snmp_inc_snmpoutpkts();
+
+        /** send to the TRAP destination */
+        udp_sendto(trap_msg.pcb, p, &trap_msg.dip, SNMP_TRAP_PORT);
+
+        pbuf_free(p);
+      }
+      else
+      {
+        return ERR_MEM;
+      }
+    }
+  }
+  return ERR_OK;
+}
+
+void
+snmp_coldstart_trap(void)
+{
+  trap_msg.outvb.head = NULL;
+  trap_msg.outvb.tail = NULL;
+  trap_msg.outvb.count = 0;
+  snmp_send_trap(SNMP_GENTRAP_COLDSTART, NULL, 0);
+}
+
+void
+snmp_authfail_trap(void)
+{
+  u8_t enable;
+  snmp_get_snmpenableauthentraps(&enable);
+  if (enable == 1)
+  {
+    trap_msg.outvb.head = NULL;
+    trap_msg.outvb.tail = NULL;
+    trap_msg.outvb.count = 0;
+    snmp_send_trap(SNMP_GENTRAP_AUTHFAIL, NULL, 0);
+  }
+}
+
+/**
+ * Sums response header field lengths from tail to head and
+ * returns resp_header_lengths for second encoding pass.
+ *
+ * @param vb_len varbind-list length
+ * @param rhl points to returned header lengths
+ * @return the required lenght for encoding the response header
+ */
+static u16_t
+snmp_resp_header_sum(struct snmp_msg_pstat *m_stat, u16_t vb_len)
+{
+  u16_t tot_len;
+  struct snmp_resp_header_lengths *rhl;
+
+  rhl = &m_stat->rhl;
+  tot_len = vb_len;
+  snmp_asn1_enc_s32t_cnt(m_stat->error_index, &rhl->erridxlen);
+  snmp_asn1_enc_length_cnt(rhl->erridxlen, &rhl->erridxlenlen);
+  tot_len += 1 + rhl->erridxlenlen + rhl->erridxlen;
+
+  snmp_asn1_enc_s32t_cnt(m_stat->error_status, &rhl->errstatlen);
+  snmp_asn1_enc_length_cnt(rhl->errstatlen, &rhl->errstatlenlen);
+  tot_len += 1 + rhl->errstatlenlen + rhl->errstatlen;
+
+  snmp_asn1_enc_s32t_cnt(m_stat->rid, &rhl->ridlen);
+  snmp_asn1_enc_length_cnt(rhl->ridlen, &rhl->ridlenlen);
+  tot_len += 1 + rhl->ridlenlen + rhl->ridlen;
+
+  rhl->pdulen = tot_len;
+  snmp_asn1_enc_length_cnt(rhl->pdulen, &rhl->pdulenlen);
+  tot_len += 1 + rhl->pdulenlen;
+
+  rhl->comlen = m_stat->com_strlen;
+  snmp_asn1_enc_length_cnt(rhl->comlen, &rhl->comlenlen);
+  tot_len += 1 + rhl->comlenlen + rhl->comlen;
+
+  snmp_asn1_enc_s32t_cnt(snmp_version, &rhl->verlen);
+  snmp_asn1_enc_length_cnt(rhl->verlen, &rhl->verlenlen);
+  tot_len += 1 + rhl->verlen + rhl->verlenlen;
+
+  rhl->seqlen = tot_len;
+  snmp_asn1_enc_length_cnt(rhl->seqlen, &rhl->seqlenlen);
+  tot_len += 1 + rhl->seqlenlen;
+
+  return tot_len;
+}
+
+/**
+ * Sums trap header field lengths from tail to head and
+ * returns trap_header_lengths for second encoding pass.
+ *
+ * @param vb_len varbind-list length
+ * @param thl points to returned header lengths
+ * @return the required lenght for encoding the trap header
+ */
+static u16_t
+snmp_trap_header_sum(struct snmp_msg_trap *m_trap, u16_t vb_len)
+{
+  u16_t tot_len;
+  struct snmp_trap_header_lengths *thl;
+
+  thl = &m_trap->thl;
+  tot_len = vb_len;
+
+  snmp_asn1_enc_u32t_cnt(m_trap->ts, &thl->tslen);
+  snmp_asn1_enc_length_cnt(thl->tslen, &thl->tslenlen);
+  tot_len += 1 + thl->tslen + thl->tslenlen;
+
+  snmp_asn1_enc_s32t_cnt(m_trap->spc_trap, &thl->strplen);
+  snmp_asn1_enc_length_cnt(thl->strplen, &thl->strplenlen);
+  tot_len += 1 + thl->strplen + thl->strplenlen;
+
+  snmp_asn1_enc_s32t_cnt(m_trap->gen_trap, &thl->gtrplen);
+  snmp_asn1_enc_length_cnt(thl->gtrplen, &thl->gtrplenlen);
+  tot_len += 1 + thl->gtrplen + thl->gtrplenlen;
+
+  thl->aaddrlen = 4;
+  snmp_asn1_enc_length_cnt(thl->aaddrlen, &thl->aaddrlenlen);
+  tot_len += 1 + thl->aaddrlen + thl->aaddrlenlen;
+
+  snmp_asn1_enc_oid_cnt(m_trap->enterprise->len, &m_trap->enterprise->id[0], &thl->eidlen);
+  snmp_asn1_enc_length_cnt(thl->eidlen, &thl->eidlenlen);
+  tot_len += 1 + thl->eidlen + thl->eidlenlen;
+
+  thl->pdulen = tot_len;
+  snmp_asn1_enc_length_cnt(thl->pdulen, &thl->pdulenlen);
+  tot_len += 1 + thl->pdulenlen;
+
+  thl->comlen = sizeof(snmp_publiccommunity) - 1;
+  snmp_asn1_enc_length_cnt(thl->comlen, &thl->comlenlen);
+  tot_len += 1 + thl->comlenlen + thl->comlen;
+
+  snmp_asn1_enc_s32t_cnt(snmp_version, &thl->verlen);
+  snmp_asn1_enc_length_cnt(thl->verlen, &thl->verlenlen);
+  tot_len += 1 + thl->verlen + thl->verlenlen;
+
+  thl->seqlen = tot_len;
+  snmp_asn1_enc_length_cnt(thl->seqlen, &thl->seqlenlen);
+  tot_len += 1 + thl->seqlenlen;
+
+  return tot_len;
+}
+
+/**
+ * Sums varbind lengths from tail to head and
+ * annotates lengths in varbind for second encoding pass.
+ *
+ * @param root points to the root of the variable binding list
+ * @return the required lenght for encoding the variable bindings
+ */
+static u16_t
+snmp_varbind_list_sum(struct snmp_varbind_root *root)
+{
+  struct snmp_varbind *vb;
+  u32_t *uint_ptr;
+  s32_t *sint_ptr;
+  u16_t tot_len;
+
+  tot_len = 0;
+  vb = root->tail;
+  while ( vb != NULL )
+  {
+    /* encoded value lenght depends on type */
+    switch (vb->value_type)
+    {
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG):
+        sint_ptr = (s32_t*)vb->value;
+        snmp_asn1_enc_s32t_cnt(*sint_ptr, &vb->vlen);
+        break;
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS):
+        uint_ptr = (u32_t*)vb->value;
+        snmp_asn1_enc_u32t_cnt(*uint_ptr, &vb->vlen);
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR):
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE):
+        vb->vlen = vb->value_len;
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID):
+        sint_ptr = (s32_t*)vb->value;
+        snmp_asn1_enc_oid_cnt(vb->value_len / sizeof(s32_t), sint_ptr, &vb->vlen);
+        break;
+      default:
+        /* unsupported type */
+        vb->vlen = 0;
+        break;
+    };
+    /* encoding length of value length field */
+    snmp_asn1_enc_length_cnt(vb->vlen, &vb->vlenlen);
+    snmp_asn1_enc_oid_cnt(vb->ident_len, vb->ident, &vb->olen);
+    snmp_asn1_enc_length_cnt(vb->olen, &vb->olenlen);
+
+    vb->seqlen = 1 + vb->vlenlen + vb->vlen;
+    vb->seqlen += 1 + vb->olenlen + vb->olen;
+    snmp_asn1_enc_length_cnt(vb->seqlen, &vb->seqlenlen);
+
+    /* varbind seq */
+    tot_len += 1 + vb->seqlenlen + vb->seqlen;
+
+    vb = vb->prev;
+  }
+
+  /* varbind-list seq */
+  root->seqlen = tot_len;
+  snmp_asn1_enc_length_cnt(root->seqlen, &root->seqlenlen);
+  tot_len += 1 + root->seqlenlen;
+
+  return tot_len;
+}
+
+/**
+ * Encodes response header from head to tail.
+ */
+static u16_t
+snmp_resp_header_enc(struct snmp_msg_pstat *m_stat, struct pbuf *p)
+{
+  u16_t ofs;
+
+  ofs = 0;
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.seqlen);
+  ofs += m_stat->rhl.seqlenlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.verlen);
+  ofs += m_stat->rhl.verlenlen;
+  snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.verlen, snmp_version);
+  ofs += m_stat->rhl.verlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.comlen);
+  ofs += m_stat->rhl.comlenlen;
+  snmp_asn1_enc_raw(p, ofs, m_stat->rhl.comlen, m_stat->community);
+  ofs += m_stat->rhl.comlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_RESP));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.pdulen);
+  ofs += m_stat->rhl.pdulenlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.ridlen);
+  ofs += m_stat->rhl.ridlenlen;
+  snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.ridlen, m_stat->rid);
+  ofs += m_stat->rhl.ridlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.errstatlen);
+  ofs += m_stat->rhl.errstatlenlen;
+  snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.errstatlen, m_stat->error_status);
+  ofs += m_stat->rhl.errstatlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_stat->rhl.erridxlen);
+  ofs += m_stat->rhl.erridxlenlen;
+  snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.erridxlen, m_stat->error_index);
+  ofs += m_stat->rhl.erridxlen;
+
+  return ofs;
+}
+
+/**
+ * Encodes trap header from head to tail.
+ */
+static u16_t
+snmp_trap_header_enc(struct snmp_msg_trap *m_trap, struct pbuf *p)
+{
+  u16_t ofs;
+
+  ofs = 0;
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.seqlen);
+  ofs += m_trap->thl.seqlenlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.verlen);
+  ofs += m_trap->thl.verlenlen;
+  snmp_asn1_enc_s32t(p, ofs, m_trap->thl.verlen, snmp_version);
+  ofs += m_trap->thl.verlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.comlen);
+  ofs += m_trap->thl.comlenlen;
+  snmp_asn1_enc_raw(p, ofs, m_trap->thl.comlen, (u8_t *)&snmp_publiccommunity[0]);
+  ofs += m_trap->thl.comlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_TRAP));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.pdulen);
+  ofs += m_trap->thl.pdulenlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.eidlen);
+  ofs += m_trap->thl.eidlenlen;
+  snmp_asn1_enc_oid(p, ofs, m_trap->enterprise->len, &m_trap->enterprise->id[0]);
+  ofs += m_trap->thl.eidlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.aaddrlen);
+  ofs += m_trap->thl.aaddrlenlen;
+  snmp_asn1_enc_raw(p, ofs, m_trap->thl.aaddrlen, &m_trap->sip_raw[0]);
+  ofs += m_trap->thl.aaddrlen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.gtrplen);
+  ofs += m_trap->thl.gtrplenlen;
+  snmp_asn1_enc_u32t(p, ofs, m_trap->thl.gtrplen, m_trap->gen_trap);
+  ofs += m_trap->thl.gtrplen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.strplen);
+  ofs += m_trap->thl.strplenlen;
+  snmp_asn1_enc_u32t(p, ofs, m_trap->thl.strplen, m_trap->spc_trap);
+  ofs += m_trap->thl.strplen;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, m_trap->thl.tslen);
+  ofs += m_trap->thl.tslenlen;
+  snmp_asn1_enc_u32t(p, ofs, m_trap->thl.tslen, m_trap->ts);
+  ofs += m_trap->thl.tslen;
+
+  return ofs;
+}
+
+/**
+ * Encodes varbind list from head to tail.
+ */
+static u16_t
+snmp_varbind_list_enc(struct snmp_varbind_root *root, struct pbuf *p, u16_t ofs)
+{
+  struct snmp_varbind *vb;
+  s32_t *sint_ptr;
+  u32_t *uint_ptr;
+  u8_t *raw_ptr;
+
+  snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ));
+  ofs += 1;
+  snmp_asn1_enc_length(p, ofs, root->seqlen);
+  ofs += root->seqlenlen;
+
+  vb = root->head;
+  while ( vb != NULL )
+  {
+    snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ));
+    ofs += 1;
+    snmp_asn1_enc_length(p, ofs, vb->seqlen);
+    ofs += vb->seqlenlen;
+
+    snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID));
+    ofs += 1;
+    snmp_asn1_enc_length(p, ofs, vb->olen);
+    ofs += vb->olenlen;
+    snmp_asn1_enc_oid(p, ofs, vb->ident_len, &vb->ident[0]);
+    ofs += vb->olen;
+
+    snmp_asn1_enc_type(p, ofs, vb->value_type);
+    ofs += 1;
+    snmp_asn1_enc_length(p, ofs, vb->vlen);
+    ofs += vb->vlenlen;
+
+    switch (vb->value_type)
+    {
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG):
+        sint_ptr = (s32_t*)vb->value;
+        snmp_asn1_enc_s32t(p, ofs, vb->vlen, *sint_ptr);
+        break;
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS):
+        uint_ptr = (u32_t*)vb->value;
+        snmp_asn1_enc_u32t(p, ofs, vb->vlen, *uint_ptr);
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR):
+      case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE):
+        raw_ptr = (u8_t*)vb->value;
+        snmp_asn1_enc_raw(p, ofs, vb->vlen, raw_ptr);
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL):
+        break;
+      case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID):
+        sint_ptr = (s32_t*)vb->value;
+        snmp_asn1_enc_oid(p, ofs, vb->value_len / sizeof(s32_t), sint_ptr);
+        break;
+      default:
+        /* unsupported type */
+        break;
+    };
+    ofs += vb->vlen;
+    vb = vb->next;
+  }
+  return ofs;
+}
+
+#endif /* LWIP_SNMP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/stats.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/stats.c
new file mode 100644
index 0000000..69f97d4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/stats.c
@@ -0,0 +1,176 @@
+/**
+ * @file
+ * Statistics module
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_STATS /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/def.h"
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+
+#include 
+
+struct stats_ lwip_stats;
+
+void stats_init(void)
+{
+#ifdef LWIP_DEBUG
+#if MEMP_STATS
+  const char * memp_names[] = {
+#define LWIP_MEMPOOL(name,num,size,desc) desc,
+#include "lwip/memp_std.h"
+  };
+  int i;
+  for (i = 0; i < MEMP_MAX; i++) {
+    lwip_stats.memp[i].name = memp_names[i];
+  }
+#endif /* MEMP_STATS */
+#if MEM_STATS
+  lwip_stats.mem.name = "MEM";
+#endif /* MEM_STATS */
+#endif /* LWIP_DEBUG */
+}
+
+#if LWIP_STATS_DISPLAY
+void
+stats_display_proto(struct stats_proto *proto, char *name)
+{
+  LWIP_PLATFORM_DIAG(("\n%s\n\t", name));
+  LWIP_PLATFORM_DIAG(("xmit: %"STAT_COUNTER_F"\n\t", proto->xmit)); 
+  LWIP_PLATFORM_DIAG(("recv: %"STAT_COUNTER_F"\n\t", proto->recv)); 
+  LWIP_PLATFORM_DIAG(("fw: %"STAT_COUNTER_F"\n\t", proto->fw)); 
+  LWIP_PLATFORM_DIAG(("drop: %"STAT_COUNTER_F"\n\t", proto->drop)); 
+  LWIP_PLATFORM_DIAG(("chkerr: %"STAT_COUNTER_F"\n\t", proto->chkerr)); 
+  LWIP_PLATFORM_DIAG(("lenerr: %"STAT_COUNTER_F"\n\t", proto->lenerr)); 
+  LWIP_PLATFORM_DIAG(("memerr: %"STAT_COUNTER_F"\n\t", proto->memerr)); 
+  LWIP_PLATFORM_DIAG(("rterr: %"STAT_COUNTER_F"\n\t", proto->rterr)); 
+  LWIP_PLATFORM_DIAG(("proterr: %"STAT_COUNTER_F"\n\t", proto->proterr)); 
+  LWIP_PLATFORM_DIAG(("opterr: %"STAT_COUNTER_F"\n\t", proto->opterr)); 
+  LWIP_PLATFORM_DIAG(("err: %"STAT_COUNTER_F"\n\t", proto->err)); 
+  LWIP_PLATFORM_DIAG(("cachehit: %"STAT_COUNTER_F"\n", proto->cachehit)); 
+}
+
+#if IGMP_STATS
+void
+stats_display_igmp(struct stats_igmp *igmp)
+{
+  LWIP_PLATFORM_DIAG(("\nIGMP\n\t"));
+  LWIP_PLATFORM_DIAG(("xmit: %"STAT_COUNTER_F"\n\t", igmp->xmit)); 
+  LWIP_PLATFORM_DIAG(("recv: %"STAT_COUNTER_F"\n\t", igmp->recv)); 
+  LWIP_PLATFORM_DIAG(("drop: %"STAT_COUNTER_F"\n\t", igmp->drop)); 
+  LWIP_PLATFORM_DIAG(("chkerr: %"STAT_COUNTER_F"\n\t", igmp->chkerr)); 
+  LWIP_PLATFORM_DIAG(("lenerr: %"STAT_COUNTER_F"\n\t", igmp->lenerr)); 
+  LWIP_PLATFORM_DIAG(("memerr: %"STAT_COUNTER_F"\n\t", igmp->memerr)); 
+  LWIP_PLATFORM_DIAG(("proterr: %"STAT_COUNTER_F"\n\t", igmp->proterr)); 
+  LWIP_PLATFORM_DIAG(("rx_v1: %"STAT_COUNTER_F"\n\t", igmp->rx_v1)); 
+  LWIP_PLATFORM_DIAG(("rx_group: %"STAT_COUNTER_F"\n", igmp->rx_group));
+  LWIP_PLATFORM_DIAG(("rx_general: %"STAT_COUNTER_F"\n", igmp->rx_general));
+  LWIP_PLATFORM_DIAG(("rx_report: %"STAT_COUNTER_F"\n\t", igmp->rx_report)); 
+  LWIP_PLATFORM_DIAG(("tx_join: %"STAT_COUNTER_F"\n\t", igmp->tx_join)); 
+  LWIP_PLATFORM_DIAG(("tx_leave: %"STAT_COUNTER_F"\n\t", igmp->tx_leave)); 
+  LWIP_PLATFORM_DIAG(("tx_report: %"STAT_COUNTER_F"\n\t", igmp->tx_report)); 
+}
+#endif /* IGMP_STATS */
+
+#if MEM_STATS || MEMP_STATS
+void
+stats_display_mem(struct stats_mem *mem, char *name)
+{
+  LWIP_PLATFORM_DIAG(("\nMEM %s\n\t", name));
+  LWIP_PLATFORM_DIAG(("avail: %"U32_F"\n\t", (u32_t)mem->avail)); 
+  LWIP_PLATFORM_DIAG(("used: %"U32_F"\n\t", (u32_t)mem->used)); 
+  LWIP_PLATFORM_DIAG(("max: %"U32_F"\n\t", (u32_t)mem->max)); 
+  LWIP_PLATFORM_DIAG(("err: %"U32_F"\n", (u32_t)mem->err));
+}
+
+#if MEMP_STATS
+void
+stats_display_memp(struct stats_mem *mem, int index)
+{
+  char * memp_names[] = {
+#define LWIP_MEMPOOL(name,num,size,desc) desc,
+#include "lwip/memp_std.h"
+  };
+  if(index < MEMP_MAX) {
+    stats_display_mem(mem, memp_names[index]);
+  }
+}
+#endif /* MEMP_STATS */
+#endif /* MEM_STATS || MEMP_STATS */
+
+#if SYS_STATS
+void
+stats_display_sys(struct stats_sys *sys)
+{
+  LWIP_PLATFORM_DIAG(("\nSYS\n\t"));
+  LWIP_PLATFORM_DIAG(("sem.used:  %"U32_F"\n\t", (u32_t)sys->sem.used)); 
+  LWIP_PLATFORM_DIAG(("sem.max:   %"U32_F"\n\t", (u32_t)sys->sem.max)); 
+  LWIP_PLATFORM_DIAG(("sem.err:   %"U32_F"\n\t", (u32_t)sys->sem.err)); 
+  LWIP_PLATFORM_DIAG(("mutex.used: %"U32_F"\n\t", (u32_t)sys->mutex.used)); 
+  LWIP_PLATFORM_DIAG(("mutex.max:  %"U32_F"\n\t", (u32_t)sys->mutex.max)); 
+  LWIP_PLATFORM_DIAG(("mutex.err:  %"U32_F"\n\t", (u32_t)sys->mutex.err)); 
+  LWIP_PLATFORM_DIAG(("mbox.used:  %"U32_F"\n\t", (u32_t)sys->mbox.used)); 
+  LWIP_PLATFORM_DIAG(("mbox.max:   %"U32_F"\n\t", (u32_t)sys->mbox.max)); 
+  LWIP_PLATFORM_DIAG(("mbox.err:   %"U32_F"\n\t", (u32_t)sys->mbox.err)); 
+}
+#endif /* SYS_STATS */
+
+void
+stats_display(void)
+{
+  s16_t i;
+
+  LINK_STATS_DISPLAY();
+  ETHARP_STATS_DISPLAY();
+  IPFRAG_STATS_DISPLAY();
+  IP_STATS_DISPLAY();
+  IGMP_STATS_DISPLAY();
+  ICMP_STATS_DISPLAY();
+  UDP_STATS_DISPLAY();
+  TCP_STATS_DISPLAY();
+  MEM_STATS_DISPLAY();
+  for (i = 0; i < MEMP_MAX; i++) {
+    MEMP_STATS_DISPLAY(i);
+  }
+  SYS_STATS_DISPLAY();
+}
+#endif /* LWIP_STATS_DISPLAY */
+
+#endif /* LWIP_STATS */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/sys.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/sys.c
new file mode 100644
index 0000000..d3a77de
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/sys.c
@@ -0,0 +1,66 @@
+/**
+ * @file
+ * lwIP Operating System abstraction
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/sys.h"
+
+/* Most of the functions defined in sys.h must be implemented in the
+ * architecture-dependent file sys_arch.c */
+
+#if !NO_SYS
+
+/**
+ * Sleep for some ms. Timeouts are NOT processed while sleeping.
+ *
+ * @param ms number of milliseconds to sleep
+ */
+void
+sys_msleep(u32_t ms)
+{
+  if (ms > 0) {
+    sys_sem_t delaysem;
+    err_t err = sys_sem_new(&delaysem, 0);
+    if (err == ERR_OK) {
+      sys_arch_sem_wait(&delaysem, ms);
+      sys_sem_free(&delaysem);
+    }
+  }
+}
+
+#endif /* !NO_SYS */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/tcp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/tcp.c
new file mode 100644
index 0000000..c629bc4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/tcp.c
@@ -0,0 +1,1635 @@
+/**
+ * @file
+ * Transmission Control Protocol for IP
+ *
+ * This file contains common functions for the TCP implementation, such as functinos
+ * for manipulating the data structures and the TCP timer functions. TCP functions
+ * related to input and output is found in tcp_in.c and tcp_out.c respectively.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/snmp.h"
+#include "lwip/tcp.h"
+#include "lwip/tcp_impl.h"
+#include "lwip/debug.h"
+#include "lwip/stats.h"
+
+#include 
+
+const char * const tcp_state_str[] = {
+  "CLOSED",      
+  "LISTEN",      
+  "SYN_SENT",    
+  "SYN_RCVD",    
+  "ESTABLISHED", 
+  "FIN_WAIT_1",  
+  "FIN_WAIT_2",  
+  "CLOSE_WAIT",  
+  "CLOSING",     
+  "LAST_ACK",    
+  "TIME_WAIT"   
+};
+
+/* Incremented every coarse grained timer shot (typically every 500 ms). */
+u32_t tcp_ticks;
+const u8_t tcp_backoff[13] =
+    { 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7};
+ /* Times per slowtmr hits */
+const u8_t tcp_persist_backoff[7] = { 3, 6, 12, 24, 48, 96, 120 };
+
+/* The TCP PCB lists. */
+
+/** List of all TCP PCBs bound but not yet (connected || listening) */
+struct tcp_pcb *tcp_bound_pcbs;
+/** List of all TCP PCBs in LISTEN state */
+union tcp_listen_pcbs_t tcp_listen_pcbs;
+/** List of all TCP PCBs that are in a state in which
+ * they accept or send data. */
+struct tcp_pcb *tcp_active_pcbs;
+/** List of all TCP PCBs in TIME-WAIT state */
+struct tcp_pcb *tcp_tw_pcbs;
+
+#define NUM_TCP_PCB_LISTS               4
+#define NUM_TCP_PCB_LISTS_NO_TIME_WAIT  3
+/** An array with all (non-temporary) PCB lists, mainly used for smaller code size */
+struct tcp_pcb ** const tcp_pcb_lists[] = {&tcp_listen_pcbs.pcbs, &tcp_bound_pcbs,
+  &tcp_active_pcbs, &tcp_tw_pcbs};
+
+/** Only used for temporary storage. */
+struct tcp_pcb *tcp_tmp_pcb;
+
+/** Timer counter to handle calling slow-timer from tcp_tmr() */ 
+static u8_t tcp_timer;
+static u16_t tcp_new_port(void);
+
+/**
+ * Called periodically to dispatch TCP timers.
+ *
+ */
+void
+tcp_tmr(void)
+{
+  /* Call tcp_fasttmr() every 250 ms */
+  tcp_fasttmr();
+
+  if (++tcp_timer & 1) {
+    /* Call tcp_tmr() every 500 ms, i.e., every other timer
+       tcp_tmr() is called. */
+    tcp_slowtmr();
+  }
+}
+
+/**
+ * Closes the TX side of a connection held by the PCB.
+ * For tcp_close(), a RST is sent if the application didn't receive all data
+ * (tcp_recved() not called for all data passed to recv callback).
+ *
+ * Listening pcbs are freed and may not be referenced any more.
+ * Connection pcbs are freed if not yet connected and may not be referenced
+ * any more. If a connection is established (at least SYN received or in
+ * a closing state), the connection is closed, and put in a closing state.
+ * The pcb is then automatically freed in tcp_slowtmr(). It is therefore
+ * unsafe to reference it.
+ *
+ * @param pcb the tcp_pcb to close
+ * @return ERR_OK if connection has been closed
+ *         another err_t if closing failed and pcb is not freed
+ */
+static err_t
+tcp_close_shutdown(struct tcp_pcb *pcb, u8_t rst_on_unacked_data)
+{
+  err_t err;
+
+  if (rst_on_unacked_data && (pcb->state != LISTEN)) {
+    if ((pcb->refused_data != NULL) || (pcb->rcv_wnd != TCP_WND)) {
+      /* Not all data received by application, send RST to tell the remote
+         side about this. */
+      LWIP_ASSERT("pcb->flags & TF_RXCLOSED", pcb->flags & TF_RXCLOSED);
+
+      /* don't call tcp_abort here: we must not deallocate the pcb since
+         that might not be expected when calling tcp_close */
+      tcp_rst(pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip,
+        pcb->local_port, pcb->remote_port);
+
+      tcp_pcb_purge(pcb);
+
+      /* TODO: to which state do we move now? */
+
+      /* move to TIME_WAIT since we close actively */
+      TCP_RMV(&tcp_active_pcbs, pcb);
+      pcb->state = TIME_WAIT;
+      TCP_REG(&tcp_tw_pcbs, pcb);
+
+      return ERR_OK;
+    }
+  }
+
+  switch (pcb->state) {
+  case CLOSED:
+    /* Closing a pcb in the CLOSED state might seem erroneous,
+     * however, it is in this state once allocated and as yet unused
+     * and the user needs some way to free it should the need arise.
+     * Calling tcp_close() with a pcb that has already been closed, (i.e. twice)
+     * or for a pcb that has been used and then entered the CLOSED state 
+     * is erroneous, but this should never happen as the pcb has in those cases
+     * been freed, and so any remaining handles are bogus. */
+    err = ERR_OK;
+    if (pcb->local_port != 0) {
+      TCP_RMV(&tcp_bound_pcbs, pcb);
+    }
+    memp_free(MEMP_TCP_PCB, pcb);
+    pcb = NULL;
+    break;
+  case LISTEN:
+    err = ERR_OK;
+    tcp_pcb_remove(&tcp_listen_pcbs.pcbs, pcb);
+    memp_free(MEMP_TCP_PCB_LISTEN, pcb);
+    pcb = NULL;
+    break;
+  case SYN_SENT:
+    err = ERR_OK;
+    tcp_pcb_remove(&tcp_active_pcbs, pcb);
+    memp_free(MEMP_TCP_PCB, pcb);
+    pcb = NULL;
+    snmp_inc_tcpattemptfails();
+    break;
+  case SYN_RCVD:
+    err = tcp_send_fin(pcb);
+    if (err == ERR_OK) {
+      snmp_inc_tcpattemptfails();
+      pcb->state = FIN_WAIT_1;
+    }
+    break;
+  case ESTABLISHED:
+    err = tcp_send_fin(pcb);
+    if (err == ERR_OK) {
+      snmp_inc_tcpestabresets();
+      pcb->state = FIN_WAIT_1;
+    }
+    break;
+  case CLOSE_WAIT:
+    err = tcp_send_fin(pcb);
+    if (err == ERR_OK) {
+      snmp_inc_tcpestabresets();
+      pcb->state = LAST_ACK;
+    }
+    break;
+  default:
+    /* Has already been closed, do nothing. */
+    err = ERR_OK;
+    pcb = NULL;
+    break;
+  }
+
+  if (pcb != NULL && err == ERR_OK) {
+    /* To ensure all data has been sent when tcp_close returns, we have
+       to make sure tcp_output doesn't fail.
+       Since we don't really have to ensure all data has been sent when tcp_close
+       returns (unsent data is sent from tcp timer functions, also), we don't care
+       for the return value of tcp_output for now. */
+    /* @todo: When implementing SO_LINGER, this must be changed somehow:
+       If SOF_LINGER is set, the data should be sent and acked before close returns.
+       This can only be valid for sequential APIs, not for the raw API. */
+    tcp_output(pcb);
+  }
+  return err;
+}
+
+/**
+ * Closes the connection held by the PCB.
+ *
+ * Listening pcbs are freed and may not be referenced any more.
+ * Connection pcbs are freed if not yet connected and may not be referenced
+ * any more. If a connection is established (at least SYN received or in
+ * a closing state), the connection is closed, and put in a closing state.
+ * The pcb is then automatically freed in tcp_slowtmr(). It is therefore
+ * unsafe to reference it (unless an error is returned).
+ *
+ * @param pcb the tcp_pcb to close
+ * @return ERR_OK if connection has been closed
+ *         another err_t if closing failed and pcb is not freed
+ */
+err_t
+tcp_close(struct tcp_pcb *pcb)
+{
+#if TCP_DEBUG
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in "));
+  tcp_debug_print_state(pcb->state);
+#endif /* TCP_DEBUG */
+
+  if (pcb->state != LISTEN) {
+    /* Set a flag not to receive any more data... */
+    pcb->flags |= TF_RXCLOSED;
+  }
+  /* ... and close */
+  return tcp_close_shutdown(pcb, 1);
+}
+
+/**
+ * Causes all or part of a full-duplex connection of this PCB to be shut down.
+ * This doesn't deallocate the PCB!
+ *
+ * @param pcb PCB to shutdown
+ * @param shut_rx shut down receive side if this is != 0
+ * @param shut_tx shut down send side if this is != 0
+ * @return ERR_OK if shutdown succeeded (or the PCB has already been shut down)
+ *         another err_t on error.
+ */
+err_t
+tcp_shutdown(struct tcp_pcb *pcb, int shut_rx, int shut_tx)
+{
+  if (pcb->state == LISTEN) {
+    return ERR_CONN;
+  }
+  if (shut_rx) {
+    /* shut down the receive side: free buffered data... */
+    if (pcb->refused_data != NULL) {
+      pbuf_free(pcb->refused_data);
+      pcb->refused_data = NULL;
+    }
+    /* ... and set a flag not to receive any more data */
+    pcb->flags |= TF_RXCLOSED;
+  }
+  if (shut_tx) {
+    /* This can't happen twice since if it succeeds, the pcb's state is changed.
+       Only close in these states as the others directly deallocate the PCB */
+    switch (pcb->state) {
+  case SYN_RCVD:
+  case ESTABLISHED:
+  case CLOSE_WAIT:
+    return tcp_close_shutdown(pcb, 0);
+  default:
+    /* don't shut down other states */
+    break;
+    }
+  }
+  /* @todo: return another err_t if not in correct state or already shut? */
+  return ERR_OK;
+}
+
+/**
+ * Abandons a connection and optionally sends a RST to the remote
+ * host.  Deletes the local protocol control block. This is done when
+ * a connection is killed because of shortage of memory.
+ *
+ * @param pcb the tcp_pcb to abort
+ * @param reset boolean to indicate whether a reset should be sent
+ */
+void
+tcp_abandon(struct tcp_pcb *pcb, int reset)
+{
+  u32_t seqno, ackno;
+  u16_t remote_port, local_port;
+  ip_addr_t remote_ip, local_ip;
+#if LWIP_CALLBACK_API  
+  tcp_err_fn errf;
+#endif /* LWIP_CALLBACK_API */
+  void *errf_arg;
+
+  /* pcb->state LISTEN not allowed here */
+  LWIP_ASSERT("don't call tcp_abort/tcp_abandon for listen-pcbs",
+    pcb->state != LISTEN);
+  /* Figure out on which TCP PCB list we are, and remove us. If we
+     are in an active state, call the receive function associated with
+     the PCB with a NULL argument, and send an RST to the remote end. */
+  if (pcb->state == TIME_WAIT) {
+    tcp_pcb_remove(&tcp_tw_pcbs, pcb);
+    memp_free(MEMP_TCP_PCB, pcb);
+  } else {
+    seqno = pcb->snd_nxt;
+    ackno = pcb->rcv_nxt;
+    ip_addr_copy(local_ip, pcb->local_ip);
+    ip_addr_copy(remote_ip, pcb->remote_ip);
+    local_port = pcb->local_port;
+    remote_port = pcb->remote_port;
+#if LWIP_CALLBACK_API
+    errf = pcb->errf;
+#endif /* LWIP_CALLBACK_API */
+    errf_arg = pcb->callback_arg;
+    tcp_pcb_remove(&tcp_active_pcbs, pcb);
+    if (pcb->unacked != NULL) {
+      tcp_segs_free(pcb->unacked);
+    }
+    if (pcb->unsent != NULL) {
+      tcp_segs_free(pcb->unsent);
+    }
+#if TCP_QUEUE_OOSEQ    
+    if (pcb->ooseq != NULL) {
+      tcp_segs_free(pcb->ooseq);
+    }
+#endif /* TCP_QUEUE_OOSEQ */
+    memp_free(MEMP_TCP_PCB, pcb);
+    TCP_EVENT_ERR(errf, errf_arg, ERR_ABRT);
+    if (reset) {
+      LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abandon: sending RST\n"));
+      tcp_rst(seqno, ackno, &local_ip, &remote_ip, local_port, remote_port);
+    }
+  }
+}
+
+/**
+ * Aborts the connection by sending a RST (reset) segment to the remote
+ * host. The pcb is deallocated. This function never fails.
+ *
+ * ATTENTION: When calling this from one of the TCP callbacks, make
+ * sure you always return ERR_ABRT (and never return ERR_ABRT otherwise
+ * or you will risk accessing deallocated memory or memory leaks!
+ *
+ * @param pcb the tcp pcb to abort
+ */
+void
+tcp_abort(struct tcp_pcb *pcb)
+{
+  tcp_abandon(pcb, 1);
+}
+
+/**
+ * Binds the connection to a local portnumber and IP address. If the
+ * IP address is not given (i.e., ipaddr == NULL), the IP address of
+ * the outgoing network interface is used instead.
+ *
+ * @param pcb the tcp_pcb to bind (no check is done whether this pcb is
+ *        already bound!)
+ * @param ipaddr the local ip address to bind to (use IP_ADDR_ANY to bind
+ *        to any local address
+ * @param port the local port to bind to
+ * @return ERR_USE if the port is already in use
+ *         ERR_VAL if bind failed because the PCB is not in a valid state
+ *         ERR_OK if bound
+ */
+err_t
+tcp_bind(struct tcp_pcb *pcb, ip_addr_t *ipaddr, u16_t port)
+{
+  int i;
+  int max_pcb_list = NUM_TCP_PCB_LISTS;
+  struct tcp_pcb *cpcb;
+
+  LWIP_ERROR("tcp_bind: can only bind in state CLOSED", pcb->state == CLOSED, return ERR_VAL);
+
+#if SO_REUSE
+  /* Unless the REUSEADDR flag is set,
+     we have to check the pcbs in TIME-WAIT state, also.
+     We do not dump TIME_WAIT pcb's; they can still be matched by incoming
+     packets using both local and remote IP addresses and ports to distinguish.
+   */
+  if ((pcb->so_options & SOF_REUSEADDR) != 0) {
+    max_pcb_list = NUM_TCP_PCB_LISTS_NO_TIME_WAIT;
+  }
+#endif /* SO_REUSE */
+
+  if (port == 0) {
+    port = tcp_new_port();
+  }
+
+  /* Check if the address already is in use (on all lists) */
+  for (i = 0; i < max_pcb_list; i++) {
+    for(cpcb = *tcp_pcb_lists[i]; cpcb != NULL; cpcb = cpcb->next) {
+      if (cpcb->local_port == port) {
+#if SO_REUSE
+        /* Omit checking for the same port if both pcbs have REUSEADDR set.
+           For SO_REUSEADDR, the duplicate-check for a 5-tuple is done in
+           tcp_connect. */
+        if (((pcb->so_options & SOF_REUSEADDR) == 0) ||
+          ((cpcb->so_options & SOF_REUSEADDR) == 0))
+#endif /* SO_REUSE */
+        {
+          if (ip_addr_isany(&(cpcb->local_ip)) ||
+              ip_addr_isany(ipaddr) ||
+              ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
+            return ERR_USE;
+          }
+        }
+      }
+    }
+  }
+
+  if (!ip_addr_isany(ipaddr)) {
+    pcb->local_ip = *ipaddr;
+  }
+  pcb->local_port = port;
+  TCP_REG(&tcp_bound_pcbs, pcb);
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %"U16_F"\n", port));
+  return ERR_OK;
+}
+#if LWIP_CALLBACK_API
+/**
+ * Default accept callback if no accept callback is specified by the user.
+ */
+static err_t
+tcp_accept_null(void *arg, struct tcp_pcb *pcb, err_t err)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_UNUSED_ARG(err);
+
+  return ERR_ABRT;
+}
+#endif /* LWIP_CALLBACK_API */
+
+/**
+ * Set the state of the connection to be LISTEN, which means that it
+ * is able to accept incoming connections. The protocol control block
+ * is reallocated in order to consume less memory. Setting the
+ * connection to LISTEN is an irreversible process.
+ *
+ * @param pcb the original tcp_pcb
+ * @param backlog the incoming connections queue limit
+ * @return tcp_pcb used for listening, consumes less memory.
+ *
+ * @note The original tcp_pcb is freed. This function therefore has to be
+ *       called like this:
+ *             tpcb = tcp_listen(tpcb);
+ */
+struct tcp_pcb *
+tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog)
+{
+  struct tcp_pcb_listen *lpcb;
+
+  LWIP_UNUSED_ARG(backlog);
+  LWIP_ERROR("tcp_listen: pcb already connected", pcb->state == CLOSED, return NULL);
+
+  /* already listening? */
+  if (pcb->state == LISTEN) {
+    return pcb;
+  }
+#if SO_REUSE
+  if ((pcb->so_options & SOF_REUSEADDR) != 0) {
+    /* Since SOF_REUSEADDR allows reusing a local address before the pcb's usage
+       is declared (listen-/connection-pcb), we have to make sure now that
+       this port is only used once for every local IP. */
+    for(lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+      if (lpcb->local_port == pcb->local_port) {
+        if (ip_addr_cmp(&lpcb->local_ip, &pcb->local_ip)) {
+          /* this address/port is already used */
+          return NULL;
+        }
+      }
+    }
+  }
+#endif /* SO_REUSE */
+  lpcb = (struct tcp_pcb_listen *)memp_malloc(MEMP_TCP_PCB_LISTEN);
+  if (lpcb == NULL) {
+    return NULL;
+  }
+  lpcb->callback_arg = pcb->callback_arg;
+  lpcb->local_port = pcb->local_port;
+  lpcb->state = LISTEN;
+  lpcb->prio = pcb->prio;
+  lpcb->so_options = pcb->so_options;
+  lpcb->so_options |= SOF_ACCEPTCONN;
+  lpcb->ttl = pcb->ttl;
+  lpcb->tos = pcb->tos;
+  ip_addr_copy(lpcb->local_ip, pcb->local_ip);
+  if (pcb->local_port != 0) {
+    TCP_RMV(&tcp_bound_pcbs, pcb);
+  }
+  memp_free(MEMP_TCP_PCB, pcb);
+#if LWIP_CALLBACK_API
+  lpcb->accept = tcp_accept_null;
+#endif /* LWIP_CALLBACK_API */
+#if TCP_LISTEN_BACKLOG
+  lpcb->accepts_pending = 0;
+  lpcb->backlog = (backlog ? backlog : 1);
+#endif /* TCP_LISTEN_BACKLOG */
+  TCP_REG(&tcp_listen_pcbs.pcbs, (struct tcp_pcb *)lpcb);
+  return (struct tcp_pcb *)lpcb;
+}
+
+/** 
+ * Update the state that tracks the available window space to advertise.
+ *
+ * Returns how much extra window would be advertised if we sent an
+ * update now.
+ */
+u32_t tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb)
+{
+  u32_t new_right_edge = pcb->rcv_nxt + pcb->rcv_wnd;
+
+  if (TCP_SEQ_GEQ(new_right_edge, pcb->rcv_ann_right_edge + LWIP_MIN((TCP_WND / 2), pcb->mss))) {
+    /* we can advertise more window */
+    pcb->rcv_ann_wnd = pcb->rcv_wnd;
+    return new_right_edge - pcb->rcv_ann_right_edge;
+  } else {
+    if (TCP_SEQ_GT(pcb->rcv_nxt, pcb->rcv_ann_right_edge)) {
+      /* Can happen due to other end sending out of advertised window,
+       * but within actual available (but not yet advertised) window */
+      pcb->rcv_ann_wnd = 0;
+    } else {
+      /* keep the right edge of window constant */
+      u32_t new_rcv_ann_wnd = pcb->rcv_ann_right_edge - pcb->rcv_nxt;
+      LWIP_ASSERT("new_rcv_ann_wnd <= 0xffff", new_rcv_ann_wnd <= 0xffff);
+      pcb->rcv_ann_wnd = (u16_t)new_rcv_ann_wnd;
+    }
+    return 0;
+  }
+}
+
+/**
+ * This function should be called by the application when it has
+ * processed the data. The purpose is to advertise a larger window
+ * when the data has been processed.
+ *
+ * @param pcb the tcp_pcb for which data is read
+ * @param len the amount of bytes that have been read by the application
+ */
+void
+tcp_recved(struct tcp_pcb *pcb, u16_t len)
+{
+  int wnd_inflation;
+
+  LWIP_ASSERT("tcp_recved: len would wrap rcv_wnd\n",
+              len <= 0xffff - pcb->rcv_wnd );
+
+  pcb->rcv_wnd += len;
+  if (pcb->rcv_wnd > TCP_WND) {
+    pcb->rcv_wnd = TCP_WND;
+  }
+
+  wnd_inflation = tcp_update_rcv_ann_wnd(pcb);
+
+  /* If the change in the right edge of window is significant (default
+   * watermark is TCP_WND/4), then send an explicit update now.
+   * Otherwise wait for a packet to be sent in the normal course of
+   * events (or more window to be available later) */
+  if (wnd_inflation >= TCP_WND_UPDATE_THRESHOLD) {
+    tcp_ack_now(pcb);
+    tcp_output(pcb);
+  }
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: recveived %"U16_F" bytes, wnd %"U16_F" (%"U16_F").\n",
+         len, pcb->rcv_wnd, TCP_WND - pcb->rcv_wnd));
+}
+
+/**
+ * A nastly hack featuring 'goto' statements that allocates a
+ * new TCP local port.
+ *
+ * @return a new (free) local TCP port number
+ */
+static u16_t
+tcp_new_port(void)
+{
+  int i;
+  struct tcp_pcb *pcb;
+#ifndef TCP_LOCAL_PORT_RANGE_START
+/* From http://www.iana.org/assignments/port-numbers:
+   "The Dynamic and/or Private Ports are those from 49152 through 65535" */
+#define TCP_LOCAL_PORT_RANGE_START  0xc000
+#define TCP_LOCAL_PORT_RANGE_END    0xffff
+#endif
+  static u16_t port = TCP_LOCAL_PORT_RANGE_START;
+  
+ again:
+  if (port++ >= TCP_LOCAL_PORT_RANGE_END) {
+    port = TCP_LOCAL_PORT_RANGE_START;
+  }
+  /* Check all PCB lists. */
+  for (i = 0; i < NUM_TCP_PCB_LISTS; i++) {
+    for(pcb = *tcp_pcb_lists[i]; pcb != NULL; pcb = pcb->next) {
+      if (pcb->local_port == port) {
+        goto again;
+      }
+    }
+  }
+  return port;
+}
+
+/**
+ * Connects to another host. The function given as the "connected"
+ * argument will be called when the connection has been established.
+ *
+ * @param pcb the tcp_pcb used to establish the connection
+ * @param ipaddr the remote ip address to connect to
+ * @param port the remote tcp port to connect to
+ * @param connected callback function to call when connected (or on error)
+ * @return ERR_VAL if invalid arguments are given
+ *         ERR_OK if connect request has been sent
+ *         other err_t values if connect request couldn't be sent
+ */
+err_t
+tcp_connect(struct tcp_pcb *pcb, ip_addr_t *ipaddr, u16_t port,
+      tcp_connected_fn connected)
+{
+  err_t ret;
+  u32_t iss;
+  u16_t old_local_port;
+
+  LWIP_ERROR("tcp_connect: can only connect from state CLOSED", pcb->state == CLOSED, return ERR_ISCONN);
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %"U16_F"\n", port));
+  if (ipaddr != NULL) {
+    pcb->remote_ip = *ipaddr;
+  } else {
+    return ERR_VAL;
+  }
+  pcb->remote_port = port;
+
+  /* check if we have a route to the remote host */
+  if (ip_addr_isany(&(pcb->local_ip))) {
+    /* no local IP address set, yet. */
+    struct netif *netif = ip_route(&(pcb->remote_ip));
+    if (netif == NULL) {
+      /* Don't even try to send a SYN packet if we have no route
+         since that will fail. */
+      return ERR_RTE;
+    }
+    /* Use the netif's IP address as local address. */
+    ip_addr_copy(pcb->local_ip, netif->ip_addr);
+  }
+
+  old_local_port = pcb->local_port;
+  if (pcb->local_port == 0) {
+    pcb->local_port = tcp_new_port();
+  }
+#if SO_REUSE
+  if ((pcb->so_options & SOF_REUSEADDR) != 0) {
+    /* Since SOF_REUSEADDR allows reusing a local address, we have to make sure
+       now that the 5-tuple is unique. */
+    struct tcp_pcb *cpcb;
+    int i;
+    /* Don't check listen- and bound-PCBs, check active- and TIME-WAIT PCBs. */
+    for (i = 2; i < NUM_TCP_PCB_LISTS; i++) {
+      for(cpcb = *tcp_pcb_lists[i]; cpcb != NULL; cpcb = cpcb->next) {
+        if ((cpcb->local_port == pcb->local_port) &&
+            (cpcb->remote_port == port) &&
+            ip_addr_cmp(&cpcb->local_ip, &pcb->local_ip) &&
+            ip_addr_cmp(&cpcb->remote_ip, ipaddr)) {
+          /* linux returns EISCONN here, but ERR_USE should be OK for us */
+          return ERR_USE;
+        }
+      }
+    }
+  }
+#endif /* SO_REUSE */
+  iss = tcp_next_iss();
+  pcb->rcv_nxt = 0;
+  pcb->snd_nxt = iss;
+  pcb->lastack = iss - 1;
+  pcb->snd_lbb = iss - 1;
+  pcb->rcv_wnd = TCP_WND;
+  pcb->rcv_ann_wnd = TCP_WND;
+  pcb->rcv_ann_right_edge = pcb->rcv_nxt;
+  pcb->snd_wnd = TCP_WND;
+  /* As initial send MSS, we use TCP_MSS but limit it to 536.
+     The send MSS is updated when an MSS option is received. */
+  pcb->mss = (TCP_MSS > 536) ? 536 : TCP_MSS;
+#if TCP_CALCULATE_EFF_SEND_MSS
+  pcb->mss = tcp_eff_send_mss(pcb->mss, ipaddr);
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+  pcb->cwnd = 1;
+  pcb->ssthresh = pcb->mss * 10;
+#if LWIP_CALLBACK_API
+  pcb->connected = connected;
+#else /* LWIP_CALLBACK_API */  
+  LWIP_UNUSED_ARG(connected);
+#endif /* LWIP_CALLBACK_API */
+
+  /* Send a SYN together with the MSS option. */
+  ret = tcp_enqueue_flags(pcb, TCP_SYN);
+  if (ret == ERR_OK) {
+    /* SYN segment was enqueued, changed the pcbs state now */
+    pcb->state = SYN_SENT;
+    if (old_local_port != 0) {
+      TCP_RMV(&tcp_bound_pcbs, pcb);
+    }
+    TCP_REG(&tcp_active_pcbs, pcb);
+    snmp_inc_tcpactiveopens();
+
+    tcp_output(pcb);
+  }
+  return ret;
+}
+
+/**
+ * Called every 500 ms and implements the retransmission timer and the timer that
+ * removes PCBs that have been in TIME-WAIT for enough time. It also increments
+ * various timers such as the inactivity timer in each PCB.
+ *
+ * Automatically called from tcp_tmr().
+ */
+void
+tcp_slowtmr(void)
+{
+  struct tcp_pcb *pcb, *prev;
+  u16_t eff_wnd;
+  u8_t pcb_remove;      /* flag if a PCB should be removed */
+  u8_t pcb_reset;       /* flag if a RST should be sent when removing */
+  err_t err;
+
+  err = ERR_OK;
+
+  ++tcp_ticks;
+
+  /* Steps through all of the active PCBs. */
+  prev = NULL;
+  pcb = tcp_active_pcbs;
+  if (pcb == NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n"));
+  }
+  while (pcb != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n"));
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN);
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT);
+
+    pcb_remove = 0;
+    pcb_reset = 0;
+
+    if (pcb->state == SYN_SENT && pcb->nrtx == TCP_SYNMAXRTX) {
+      ++pcb_remove;
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n"));
+    }
+    else if (pcb->nrtx == TCP_MAXRTX) {
+      ++pcb_remove;
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n"));
+    } else {
+      if (pcb->persist_backoff > 0) {
+        /* If snd_wnd is zero, use persist timer to send 1 byte probes
+         * instead of using the standard retransmission mechanism. */
+        pcb->persist_cnt++;
+        if (pcb->persist_cnt >= tcp_persist_backoff[pcb->persist_backoff-1]) {
+          pcb->persist_cnt = 0;
+          if (pcb->persist_backoff < sizeof(tcp_persist_backoff)) {
+            pcb->persist_backoff++;
+          }
+          tcp_zero_window_probe(pcb);
+        }
+      } else {
+        /* Increase the retransmission timer if it is running */
+        if(pcb->rtime >= 0)
+          ++pcb->rtime;
+
+        if (pcb->unacked != NULL && pcb->rtime >= pcb->rto) {
+          /* Time for a retransmission. */
+          LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_slowtmr: rtime %"S16_F
+                                      " pcb->rto %"S16_F"\n",
+                                      pcb->rtime, pcb->rto));
+
+          /* Double retransmission time-out unless we are trying to
+           * connect to somebody (i.e., we are in SYN_SENT). */
+          if (pcb->state != SYN_SENT) {
+            pcb->rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[pcb->nrtx];
+          }
+
+          /* Reset the retransmission timer. */
+          pcb->rtime = 0;
+
+          /* Reduce congestion window and ssthresh. */
+          eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd);
+          pcb->ssthresh = eff_wnd >> 1;
+          if (pcb->ssthresh < (pcb->mss << 1)) {
+            pcb->ssthresh = (pcb->mss << 1);
+          }
+          pcb->cwnd = pcb->mss;
+          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"U16_F
+                                       " ssthresh %"U16_F"\n",
+                                       pcb->cwnd, pcb->ssthresh));
+ 
+          /* The following needs to be called AFTER cwnd is set to one
+             mss - STJ */
+          tcp_rexmit_rto(pcb);
+        }
+      }
+    }
+    /* Check if this PCB has stayed too long in FIN-WAIT-2 */
+    if (pcb->state == FIN_WAIT_2) {
+      if ((u32_t)(tcp_ticks - pcb->tmr) >
+          TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) {
+        ++pcb_remove;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in FIN-WAIT-2\n"));
+      }
+    }
+
+    /* Check if KEEPALIVE should be sent */
+    if((pcb->so_options & SOF_KEEPALIVE) &&
+       ((pcb->state == ESTABLISHED) ||
+        (pcb->state == CLOSE_WAIT))) {
+#if LWIP_TCP_KEEPALIVE
+      if((u32_t)(tcp_ticks - pcb->tmr) >
+         (pcb->keep_idle + (pcb->keep_cnt*pcb->keep_intvl))
+         / TCP_SLOW_INTERVAL)
+#else      
+      if((u32_t)(tcp_ticks - pcb->tmr) >
+         (pcb->keep_idle + TCP_MAXIDLE) / TCP_SLOW_INTERVAL)
+#endif /* LWIP_TCP_KEEPALIVE */
+      {
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to %"U16_F".%"U16_F".%"U16_F".%"U16_F".\n",
+                                ip4_addr1_16(&pcb->remote_ip), ip4_addr2_16(&pcb->remote_ip),
+                                ip4_addr3_16(&pcb->remote_ip), ip4_addr4_16(&pcb->remote_ip)));
+        
+        ++pcb_remove;
+        ++pcb_reset;
+      }
+#if LWIP_TCP_KEEPALIVE
+      else if((u32_t)(tcp_ticks - pcb->tmr) > 
+              (pcb->keep_idle + pcb->keep_cnt_sent * pcb->keep_intvl)
+              / TCP_SLOW_INTERVAL)
+#else
+      else if((u32_t)(tcp_ticks - pcb->tmr) > 
+              (pcb->keep_idle + pcb->keep_cnt_sent * TCP_KEEPINTVL_DEFAULT) 
+              / TCP_SLOW_INTERVAL)
+#endif /* LWIP_TCP_KEEPALIVE */
+      {
+        tcp_keepalive(pcb);
+        pcb->keep_cnt_sent++;
+      }
+    }
+
+    /* If this PCB has queued out of sequence data, but has been
+       inactive for too long, will drop the data (it will eventually
+       be retransmitted). */
+#if TCP_QUEUE_OOSEQ
+    if (pcb->ooseq != NULL &&
+        (u32_t)tcp_ticks - pcb->tmr >= pcb->rto * TCP_OOSEQ_TIMEOUT) {
+      tcp_segs_free(pcb->ooseq);
+      pcb->ooseq = NULL;
+      LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n"));
+    }
+#endif /* TCP_QUEUE_OOSEQ */
+
+    /* Check if this PCB has stayed too long in SYN-RCVD */
+    if (pcb->state == SYN_RCVD) {
+      if ((u32_t)(tcp_ticks - pcb->tmr) >
+          TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) {
+        ++pcb_remove;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n"));
+      }
+    }
+
+    /* Check if this PCB has stayed too long in LAST-ACK */
+    if (pcb->state == LAST_ACK) {
+      if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
+        ++pcb_remove;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n"));
+      }
+    }
+
+    /* If the PCB should be removed, do it. */
+    if (pcb_remove) {
+      struct tcp_pcb *pcb2;
+      tcp_pcb_purge(pcb);
+      /* Remove PCB from tcp_active_pcbs list. */
+      if (prev != NULL) {
+        LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs);
+        prev->next = pcb->next;
+      } else {
+        /* This PCB was the first. */
+        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb);
+        tcp_active_pcbs = pcb->next;
+      }
+
+      TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_ABRT);
+      if (pcb_reset) {
+        tcp_rst(pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip,
+          pcb->local_port, pcb->remote_port);
+      }
+
+      pcb2 = pcb;
+      pcb = pcb->next;
+      memp_free(MEMP_TCP_PCB, pcb2);
+    } else {
+      /* get the 'next' element now and work with 'prev' below (in case of abort) */
+      prev = pcb;
+      pcb = pcb->next;
+
+      /* We check if we should poll the connection. */
+      ++prev->polltmr;
+      if (prev->polltmr >= prev->pollinterval) {
+        prev->polltmr = 0;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n"));
+        TCP_EVENT_POLL(prev, err);
+        /* if err == ERR_ABRT, 'prev' is already deallocated */
+        if (err == ERR_OK) {
+          tcp_output(prev);
+        }
+      }
+    }
+  }
+
+  
+  /* Steps through all of the TIME-WAIT PCBs. */
+  prev = NULL;
+  pcb = tcp_tw_pcbs;
+  while (pcb != NULL) {
+    LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+    pcb_remove = 0;
+
+    /* Check if this PCB has stayed long enough in TIME-WAIT */
+    if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
+      ++pcb_remove;
+    }
+    
+
+
+    /* If the PCB should be removed, do it. */
+    if (pcb_remove) {
+      struct tcp_pcb *pcb2;
+      tcp_pcb_purge(pcb);
+      /* Remove PCB from tcp_tw_pcbs list. */
+      if (prev != NULL) {
+        LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs);
+        prev->next = pcb->next;
+      } else {
+        /* This PCB was the first. */
+        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb);
+        tcp_tw_pcbs = pcb->next;
+      }
+      pcb2 = pcb;
+      pcb = pcb->next;
+      memp_free(MEMP_TCP_PCB, pcb2);
+    } else {
+      prev = pcb;
+      pcb = pcb->next;
+    }
+  }
+}
+
+/**
+ * Is called every TCP_FAST_INTERVAL (250 ms) and process data previously
+ * "refused" by upper layer (application) and sends delayed ACKs.
+ *
+ * Automatically called from tcp_tmr().
+ */
+void
+tcp_fasttmr(void)
+{
+  struct tcp_pcb *pcb = tcp_active_pcbs;
+
+  while(pcb != NULL) {
+    struct tcp_pcb *next = pcb->next;
+    /* If there is data which was previously "refused" by upper layer */
+    if (pcb->refused_data != NULL) {
+      /* Notify again application with data previously received. */
+      err_t err;
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_fasttmr: notify kept packet\n"));
+      TCP_EVENT_RECV(pcb, pcb->refused_data, ERR_OK, err);
+      if (err == ERR_OK) {
+        pcb->refused_data = NULL;
+      } else if (err == ERR_ABRT) {
+        /* if err == ERR_ABRT, 'pcb' is already deallocated */
+        pcb = NULL;
+      }
+    }
+
+    /* send delayed ACKs */
+    if (pcb && (pcb->flags & TF_ACK_DELAY)) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n"));
+      tcp_ack_now(pcb);
+      tcp_output(pcb);
+      pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
+    }
+
+    pcb = next;
+  }
+}
+
+/**
+ * Deallocates a list of TCP segments (tcp_seg structures).
+ *
+ * @param seg tcp_seg list of TCP segments to free
+ */
+void
+tcp_segs_free(struct tcp_seg *seg)
+{
+  while (seg != NULL) {
+    struct tcp_seg *next = seg->next;
+    tcp_seg_free(seg);
+    seg = next;
+  }
+}
+
+/**
+ * Frees a TCP segment (tcp_seg structure).
+ *
+ * @param seg single tcp_seg to free
+ */
+void
+tcp_seg_free(struct tcp_seg *seg)
+{
+  if (seg != NULL) {
+    if (seg->p != NULL) {
+      pbuf_free(seg->p);
+#if TCP_DEBUG
+      seg->p = NULL;
+#endif /* TCP_DEBUG */
+    }
+    memp_free(MEMP_TCP_SEG, seg);
+  }
+}
+
+/**
+ * Sets the priority of a connection.
+ *
+ * @param pcb the tcp_pcb to manipulate
+ * @param prio new priority
+ */
+void
+tcp_setprio(struct tcp_pcb *pcb, u8_t prio)
+{
+  pcb->prio = prio;
+}
+
+#if TCP_QUEUE_OOSEQ
+/**
+ * Returns a copy of the given TCP segment.
+ * The pbuf and data are not copied, only the pointers
+ *
+ * @param seg the old tcp_seg
+ * @return a copy of seg
+ */ 
+struct tcp_seg *
+tcp_seg_copy(struct tcp_seg *seg)
+{
+  struct tcp_seg *cseg;
+
+  cseg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG);
+  if (cseg == NULL) {
+    return NULL;
+  }
+  SMEMCPY((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg)); 
+  pbuf_ref(cseg->p);
+  return cseg;
+}
+#endif /* TCP_QUEUE_OOSEQ */
+
+#if LWIP_CALLBACK_API
+/**
+ * Default receive callback that is called if the user didn't register
+ * a recv callback for the pcb.
+ */
+err_t
+tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
+{
+  LWIP_UNUSED_ARG(arg);
+  if (p != NULL) {
+    tcp_recved(pcb, p->tot_len);
+    pbuf_free(p);
+  } else if (err == ERR_OK) {
+    return tcp_close(pcb);
+  }
+  return ERR_OK;
+}
+#endif /* LWIP_CALLBACK_API */
+
+/**
+ * Kills the oldest active connection that has lower priority than prio.
+ *
+ * @param prio minimum priority
+ */
+static void
+tcp_kill_prio(u8_t prio)
+{
+  struct tcp_pcb *pcb, *inactive;
+  u32_t inactivity;
+  u8_t mprio;
+
+
+  mprio = TCP_PRIO_MAX;
+  
+  /* We kill the oldest active connection that has lower priority than prio. */
+  inactivity = 0;
+  inactive = NULL;
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->prio <= prio &&
+       pcb->prio <= mprio &&
+       (u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
+      inactivity = tcp_ticks - pcb->tmr;
+      inactive = pcb;
+      mprio = pcb->prio;
+    }
+  }
+  if (inactive != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n",
+           (void *)inactive, inactivity));
+    tcp_abort(inactive);
+  }
+}
+
+/**
+ * Kills the oldest connection that is in TIME_WAIT state.
+ * Called from tcp_alloc() if no more connections are available.
+ */
+static void
+tcp_kill_timewait(void)
+{
+  struct tcp_pcb *pcb, *inactive;
+  u32_t inactivity;
+
+  inactivity = 0;
+  inactive = NULL;
+  /* Go through the list of TIME_WAIT pcbs and get the oldest pcb. */
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
+      inactivity = tcp_ticks - pcb->tmr;
+      inactive = pcb;
+    }
+  }
+  if (inactive != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n",
+           (void *)inactive, inactivity));
+    tcp_abort(inactive);
+  }
+}
+
+/**
+ * Allocate a new tcp_pcb structure.
+ *
+ * @param prio priority for the new pcb
+ * @return a new tcp_pcb that initially is in state CLOSED
+ */
+struct tcp_pcb *
+tcp_alloc(u8_t prio)
+{
+  struct tcp_pcb *pcb;
+  u32_t iss;
+  
+  pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
+  if (pcb == NULL) {
+    /* Try killing oldest connection in TIME-WAIT. */
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n"));
+    tcp_kill_timewait();
+    /* Try to allocate a tcp_pcb again. */
+    pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
+    if (pcb == NULL) {
+      /* Try killing active connections with lower priority than the new one. */
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing connection with prio lower than %d\n", prio));
+      tcp_kill_prio(prio);
+      /* Try to allocate a tcp_pcb again. */
+      pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
+      if (pcb != NULL) {
+        /* adjust err stats: memp_malloc failed twice before */
+        MEMP_STATS_DEC(err, MEMP_TCP_PCB);
+      }
+    }
+    if (pcb != NULL) {
+      /* adjust err stats: timewait PCB was freed above */
+      MEMP_STATS_DEC(err, MEMP_TCP_PCB);
+    }
+  }
+  if (pcb != NULL) {
+    memset(pcb, 0, sizeof(struct tcp_pcb));
+    pcb->prio = prio;
+    pcb->snd_buf = TCP_SND_BUF;
+    pcb->snd_queuelen = 0;
+    pcb->rcv_wnd = TCP_WND;
+    pcb->rcv_ann_wnd = TCP_WND;
+    pcb->tos = 0;
+    pcb->ttl = TCP_TTL;
+    /* As initial send MSS, we use TCP_MSS but limit it to 536.
+       The send MSS is updated when an MSS option is received. */
+    pcb->mss = (TCP_MSS > 536) ? 536 : TCP_MSS;
+    pcb->rto = 3000 / TCP_SLOW_INTERVAL;
+    pcb->sa = 0;
+    pcb->sv = 3000 / TCP_SLOW_INTERVAL;
+    pcb->rtime = -1;
+    pcb->cwnd = 1;
+    iss = tcp_next_iss();
+    pcb->snd_wl2 = iss;
+    pcb->snd_nxt = iss;
+    pcb->lastack = iss;
+    pcb->snd_lbb = iss;   
+    pcb->tmr = tcp_ticks;
+
+    pcb->polltmr = 0;
+
+#if LWIP_CALLBACK_API
+    pcb->recv = tcp_recv_null;
+#endif /* LWIP_CALLBACK_API */  
+    
+    /* Init KEEPALIVE timer */
+    pcb->keep_idle  = TCP_KEEPIDLE_DEFAULT;
+    
+#if LWIP_TCP_KEEPALIVE
+    pcb->keep_intvl = TCP_KEEPINTVL_DEFAULT;
+    pcb->keep_cnt   = TCP_KEEPCNT_DEFAULT;
+#endif /* LWIP_TCP_KEEPALIVE */
+
+    pcb->keep_cnt_sent = 0;
+  }
+  return pcb;
+}
+
+/**
+ * Creates a new TCP protocol control block but doesn't place it on
+ * any of the TCP PCB lists.
+ * The pcb is not put on any list until binding using tcp_bind().
+ *
+ * @internal: Maybe there should be a idle TCP PCB list where these
+ * PCBs are put on. Port reservation using tcp_bind() is implemented but
+ * allocated pcbs that are not bound can't be killed automatically if wanting
+ * to allocate a pcb with higher prio (@see tcp_kill_prio())
+ *
+ * @return a new tcp_pcb that initially is in state CLOSED
+ */
+struct tcp_pcb *
+tcp_new(void)
+{
+  return tcp_alloc(TCP_PRIO_NORMAL);
+}
+
+/**
+ * Used to specify the argument that should be passed callback
+ * functions.
+ *
+ * @param pcb tcp_pcb to set the callback argument
+ * @param arg void pointer argument to pass to callback functions
+ */ 
+void
+tcp_arg(struct tcp_pcb *pcb, void *arg)
+{  
+  pcb->callback_arg = arg;
+}
+#if LWIP_CALLBACK_API
+
+/**
+ * Used to specify the function that should be called when a TCP
+ * connection receives data.
+ *
+ * @param pcb tcp_pcb to set the recv callback
+ * @param recv callback function to call for this pcb when data is received
+ */ 
+void
+tcp_recv(struct tcp_pcb *pcb, tcp_recv_fn recv)
+{
+  pcb->recv = recv;
+}
+
+/**
+ * Used to specify the function that should be called when TCP data
+ * has been successfully delivered to the remote host.
+ *
+ * @param pcb tcp_pcb to set the sent callback
+ * @param sent callback function to call for this pcb when data is successfully sent
+ */ 
+void
+tcp_sent(struct tcp_pcb *pcb, tcp_sent_fn sent)
+{
+  pcb->sent = sent;
+}
+
+/**
+ * Used to specify the function that should be called when a fatal error
+ * has occured on the connection.
+ *
+ * @param pcb tcp_pcb to set the err callback
+ * @param err callback function to call for this pcb when a fatal error
+ *        has occured on the connection
+ */ 
+void
+tcp_err(struct tcp_pcb *pcb, tcp_err_fn err)
+{
+  pcb->errf = err;
+}
+
+/**
+ * Used for specifying the function that should be called when a
+ * LISTENing connection has been connected to another host.
+ *
+ * @param pcb tcp_pcb to set the accept callback
+ * @param accept callback function to call for this pcb when LISTENing
+ *        connection has been connected to another host
+ */ 
+void
+tcp_accept(struct tcp_pcb *pcb, tcp_accept_fn accept)
+{
+  pcb->accept = accept;
+}
+#endif /* LWIP_CALLBACK_API */
+
+
+/**
+ * Used to specify the function that should be called periodically
+ * from TCP. The interval is specified in terms of the TCP coarse
+ * timer interval, which is called twice a second.
+ *
+ */ 
+void
+tcp_poll(struct tcp_pcb *pcb, tcp_poll_fn poll, u8_t interval)
+{
+#if LWIP_CALLBACK_API
+  pcb->poll = poll;
+#else /* LWIP_CALLBACK_API */  
+  LWIP_UNUSED_ARG(poll);
+#endif /* LWIP_CALLBACK_API */  
+  pcb->pollinterval = interval;
+}
+
+/**
+ * Purges a TCP PCB. Removes any buffered data and frees the buffer memory
+ * (pcb->ooseq, pcb->unsent and pcb->unacked are freed).
+ *
+ * @param pcb tcp_pcb to purge. The pcb itself is not deallocated!
+ */
+void
+tcp_pcb_purge(struct tcp_pcb *pcb)
+{
+  if (pcb->state != CLOSED &&
+     pcb->state != TIME_WAIT &&
+     pcb->state != LISTEN) {
+
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n"));
+
+#if TCP_LISTEN_BACKLOG
+    if (pcb->state == SYN_RCVD) {
+      /* Need to find the corresponding listen_pcb and decrease its accepts_pending */
+      struct tcp_pcb_listen *lpcb;
+      LWIP_ASSERT("tcp_pcb_purge: pcb->state == SYN_RCVD but tcp_listen_pcbs is NULL",
+        tcp_listen_pcbs.listen_pcbs != NULL);
+      for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+        if ((lpcb->local_port == pcb->local_port) &&
+            (ip_addr_isany(&lpcb->local_ip) ||
+             ip_addr_cmp(&pcb->local_ip, &lpcb->local_ip))) {
+            /* port and address of the listen pcb match the timed-out pcb */
+            LWIP_ASSERT("tcp_pcb_purge: listen pcb does not have accepts pending",
+              lpcb->accepts_pending > 0);
+            lpcb->accepts_pending--;
+            break;
+          }
+      }
+    }
+#endif /* TCP_LISTEN_BACKLOG */
+
+
+    if (pcb->refused_data != NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->refused_data\n"));
+      pbuf_free(pcb->refused_data);
+      pcb->refused_data = NULL;
+    }
+    if (pcb->unsent != NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: not all data sent\n"));
+    }
+    if (pcb->unacked != NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n"));
+    }
+#if TCP_QUEUE_OOSEQ
+    if (pcb->ooseq != NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n"));
+    }
+    tcp_segs_free(pcb->ooseq);
+    pcb->ooseq = NULL;
+#endif /* TCP_QUEUE_OOSEQ */
+
+    /* Stop the retransmission timer as it will expect data on unacked
+       queue if it fires */
+    pcb->rtime = -1;
+
+    tcp_segs_free(pcb->unsent);
+    tcp_segs_free(pcb->unacked);
+    pcb->unacked = pcb->unsent = NULL;
+#if TCP_OVERSIZE
+    pcb->unsent_oversize = 0;
+#endif /* TCP_OVERSIZE */
+  }
+}
+
+/**
+ * Purges the PCB and removes it from a PCB list. Any delayed ACKs are sent first.
+ *
+ * @param pcblist PCB list to purge.
+ * @param pcb tcp_pcb to purge. The pcb itself is NOT deallocated!
+ */
+void
+tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb)
+{
+  TCP_RMV(pcblist, pcb);
+
+  tcp_pcb_purge(pcb);
+  
+  /* if there is an outstanding delayed ACKs, send it */
+  if (pcb->state != TIME_WAIT &&
+     pcb->state != LISTEN &&
+     pcb->flags & TF_ACK_DELAY) {
+    pcb->flags |= TF_ACK_NOW;
+    tcp_output(pcb);
+  }
+
+  if (pcb->state != LISTEN) {
+    LWIP_ASSERT("unsent segments leaking", pcb->unsent == NULL);
+    LWIP_ASSERT("unacked segments leaking", pcb->unacked == NULL);
+#if TCP_QUEUE_OOSEQ
+    LWIP_ASSERT("ooseq segments leaking", pcb->ooseq == NULL);
+#endif /* TCP_QUEUE_OOSEQ */
+  }
+
+  pcb->state = CLOSED;
+
+  LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane());
+}
+
+/**
+ * Calculates a new initial sequence number for new connections.
+ *
+ * @return u32_t pseudo random sequence number
+ */
+u32_t
+tcp_next_iss(void)
+{
+  static u32_t iss = 6510;
+  
+  iss += tcp_ticks;       /* XXX */
+  return iss;
+}
+
+#if TCP_CALCULATE_EFF_SEND_MSS
+/**
+ * Calcluates the effective send mss that can be used for a specific IP address
+ * by using ip_route to determin the netif used to send to the address and
+ * calculating the minimum of TCP_MSS and that netif's mtu (if set).
+ */
+u16_t
+tcp_eff_send_mss(u16_t sendmss, ip_addr_t *addr)
+{
+  u16_t mss_s;
+  struct netif *outif;
+
+  outif = ip_route(addr);
+  if ((outif != NULL) && (outif->mtu != 0)) {
+    mss_s = outif->mtu - IP_HLEN - TCP_HLEN;
+    /* RFC 1122, chap 4.2.2.6:
+     * Eff.snd.MSS = min(SendMSS+20, MMS_S) - TCPhdrsize - IPoptionsize
+     * We correct for TCP options in tcp_write(), and don't support IP options.
+     */
+    sendmss = LWIP_MIN(sendmss, mss_s);
+  }
+  return sendmss;
+}
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+
+const char*
+tcp_debug_state_str(enum tcp_state s)
+{
+  return tcp_state_str[s];
+}
+
+#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
+/**
+ * Print a tcp header for debugging purposes.
+ *
+ * @param tcphdr pointer to a struct tcp_hdr
+ */
+void
+tcp_debug_print(struct tcp_hdr *tcphdr)
+{
+  LWIP_DEBUGF(TCP_DEBUG, ("TCP header:\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|    %5"U16_F"      |    %5"U16_F"      | (src port, dest port)\n",
+         ntohs(tcphdr->src), ntohs(tcphdr->dest)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|           %010"U32_F"          | (seq no)\n",
+          ntohl(tcphdr->seqno)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|           %010"U32_F"          | (ack no)\n",
+         ntohl(tcphdr->ackno)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("| %2"U16_F" |   |%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"|     %5"U16_F"     | (hdrlen, flags (",
+       TCPH_HDRLEN(tcphdr),
+         TCPH_FLAGS(tcphdr) >> 5 & 1,
+         TCPH_FLAGS(tcphdr) >> 4 & 1,
+         TCPH_FLAGS(tcphdr) >> 3 & 1,
+         TCPH_FLAGS(tcphdr) >> 2 & 1,
+         TCPH_FLAGS(tcphdr) >> 1 & 1,
+         TCPH_FLAGS(tcphdr) & 1,
+         ntohs(tcphdr->wnd)));
+  tcp_debug_print_flags(TCPH_FLAGS(tcphdr));
+  LWIP_DEBUGF(TCP_DEBUG, ("), win)\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|    0x%04"X16_F"     |     %5"U16_F"     | (chksum, urgp)\n",
+         ntohs(tcphdr->chksum), ntohs(tcphdr->urgp)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+}
+
+/**
+ * Print a tcp state for debugging purposes.
+ *
+ * @param s enum tcp_state to print
+ */
+void
+tcp_debug_print_state(enum tcp_state s)
+{
+  LWIP_DEBUGF(TCP_DEBUG, ("State: %s\n", tcp_state_str[s]));
+}
+
+/**
+ * Print tcp flags for debugging purposes.
+ *
+ * @param flags tcp flags, all active flags are printed
+ */
+void
+tcp_debug_print_flags(u8_t flags)
+{
+  if (flags & TCP_FIN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("FIN "));
+  }
+  if (flags & TCP_SYN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("SYN "));
+  }
+  if (flags & TCP_RST) {
+    LWIP_DEBUGF(TCP_DEBUG, ("RST "));
+  }
+  if (flags & TCP_PSH) {
+    LWIP_DEBUGF(TCP_DEBUG, ("PSH "));
+  }
+  if (flags & TCP_ACK) {
+    LWIP_DEBUGF(TCP_DEBUG, ("ACK "));
+  }
+  if (flags & TCP_URG) {
+    LWIP_DEBUGF(TCP_DEBUG, ("URG "));
+  }
+  if (flags & TCP_ECE) {
+    LWIP_DEBUGF(TCP_DEBUG, ("ECE "));
+  }
+  if (flags & TCP_CWR) {
+    LWIP_DEBUGF(TCP_DEBUG, ("CWR "));
+  }
+  LWIP_DEBUGF(TCP_DEBUG, ("\n"));
+}
+
+/**
+ * Print all tcp_pcbs in every list for debugging purposes.
+ */
+void
+tcp_debug_print_pcbs(void)
+{
+  struct tcp_pcb *pcb;
+  LWIP_DEBUGF(TCP_DEBUG, ("Active PCB states:\n"));
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ",
+                       pcb->local_port, pcb->remote_port,
+                       pcb->snd_nxt, pcb->rcv_nxt));
+    tcp_debug_print_state(pcb->state);
+  }    
+  LWIP_DEBUGF(TCP_DEBUG, ("Listen PCB states:\n"));
+  for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ",
+                       pcb->local_port, pcb->remote_port,
+                       pcb->snd_nxt, pcb->rcv_nxt));
+    tcp_debug_print_state(pcb->state);
+  }    
+  LWIP_DEBUGF(TCP_DEBUG, ("TIME-WAIT PCB states:\n"));
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ",
+                       pcb->local_port, pcb->remote_port,
+                       pcb->snd_nxt, pcb->rcv_nxt));
+    tcp_debug_print_state(pcb->state);
+  }    
+}
+
+/**
+ * Check state consistency of the tcp_pcb lists.
+ */
+s16_t
+tcp_pcbs_sane(void)
+{
+  struct tcp_pcb *pcb;
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != CLOSED", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != LISTEN", pcb->state != LISTEN);
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
+  }
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_ASSERT("tcp_pcbs_sane: tw pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+  }
+  return 1;
+}
+#endif /* TCP_DEBUG */
+
+#endif /* LWIP_TCP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/tcp_in.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/tcp_in.c
new file mode 100644
index 0000000..9095264
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/tcp_in.c
@@ -0,0 +1,1567 @@
+/**
+ * @file
+ * Transmission Control Protocol, incoming traffic
+ *
+ * The input processing functions of the TCP layer.
+ *
+ * These functions are generally called in the order (ip_input() ->)
+ * tcp_input() -> * tcp_process() -> tcp_receive() (-> application).
+ * 
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/tcp_impl.h"
+#include "lwip/def.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+#include "arch/perf.h"
+
+/* These variables are global to all functions involved in the input
+   processing of TCP segments. They are set by the tcp_input()
+   function. */
+static struct tcp_seg inseg;
+static struct tcp_hdr *tcphdr;
+static struct ip_hdr *iphdr;
+static u32_t seqno, ackno;
+static u8_t flags;
+static u16_t tcplen;
+
+static u8_t recv_flags;
+static struct pbuf *recv_data;
+
+struct tcp_pcb *tcp_input_pcb;
+
+/* Forward declarations. */
+static err_t tcp_process(struct tcp_pcb *pcb);
+static void tcp_receive(struct tcp_pcb *pcb);
+static void tcp_parseopt(struct tcp_pcb *pcb);
+
+static err_t tcp_listen_input(struct tcp_pcb_listen *pcb);
+static err_t tcp_timewait_input(struct tcp_pcb *pcb);
+
+/**
+ * The initial input processing of TCP. It verifies the TCP header, demultiplexes
+ * the segment between the PCBs and passes it on to tcp_process(), which implements
+ * the TCP finite state machine. This function is called by the IP layer (in
+ * ip_input()).
+ *
+ * @param p received TCP segment to process (p->payload pointing to the IP header)
+ * @param inp network interface on which this segment was received
+ */
+void
+tcp_input(struct pbuf *p, struct netif *inp)
+{
+  struct tcp_pcb *pcb, *prev;
+  struct tcp_pcb_listen *lpcb;
+#if SO_REUSE
+  struct tcp_pcb *lpcb_prev = NULL;
+  struct tcp_pcb_listen *lpcb_any = NULL;
+#endif /* SO_REUSE */
+  u8_t hdrlen;
+  err_t err;
+
+  PERF_START;
+
+  TCP_STATS_INC(tcp.recv);
+  snmp_inc_tcpinsegs();
+
+  iphdr = (struct ip_hdr *)p->payload;
+  tcphdr = (struct tcp_hdr *)((u8_t *)p->payload + IPH_HL(iphdr) * 4);
+
+#if TCP_INPUT_DEBUG
+  tcp_debug_print(tcphdr);
+#endif
+
+  /* remove header from payload */
+  if (pbuf_header(p, -((s16_t)(IPH_HL(iphdr) * 4))) || (p->tot_len < sizeof(struct tcp_hdr))) {
+    /* drop short packets */
+    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet (%"U16_F" bytes) discarded\n", p->tot_len));
+    TCP_STATS_INC(tcp.lenerr);
+    TCP_STATS_INC(tcp.drop);
+    snmp_inc_tcpinerrs();
+    pbuf_free(p);
+    return;
+  }
+
+  /* Don't even process incoming broadcasts/multicasts. */
+  if (ip_addr_isbroadcast(¤t_iphdr_dest, inp) ||
+      ip_addr_ismulticast(¤t_iphdr_dest)) {
+    TCP_STATS_INC(tcp.proterr);
+    TCP_STATS_INC(tcp.drop);
+    snmp_inc_tcpinerrs();
+    pbuf_free(p);
+    return;
+  }
+
+#if CHECKSUM_CHECK_TCP
+  /* Verify TCP checksum. */
+  if (inet_chksum_pseudo(p, ip_current_src_addr(), ip_current_dest_addr(),
+      IP_PROTO_TCP, p->tot_len) != 0) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packet discarded due to failing checksum 0x%04"X16_F"\n",
+        inet_chksum_pseudo(p, ip_current_src_addr(), ip_current_dest_addr(),
+      IP_PROTO_TCP, p->tot_len)));
+#if TCP_DEBUG
+    tcp_debug_print(tcphdr);
+#endif /* TCP_DEBUG */
+    TCP_STATS_INC(tcp.chkerr);
+    TCP_STATS_INC(tcp.drop);
+    snmp_inc_tcpinerrs();
+    pbuf_free(p);
+    return;
+  }
+#endif
+
+  /* Move the payload pointer in the pbuf so that it points to the
+     TCP data instead of the TCP header. */
+  hdrlen = TCPH_HDRLEN(tcphdr);
+  if(pbuf_header(p, -(hdrlen * 4))){
+    /* drop short packets */
+    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet\n"));
+    TCP_STATS_INC(tcp.lenerr);
+    TCP_STATS_INC(tcp.drop);
+    snmp_inc_tcpinerrs();
+    pbuf_free(p);
+    return;
+  }
+
+  /* Convert fields in TCP header to host byte order. */
+  tcphdr->src = ntohs(tcphdr->src);
+  tcphdr->dest = ntohs(tcphdr->dest);
+  seqno = tcphdr->seqno = ntohl(tcphdr->seqno);
+  ackno = tcphdr->ackno = ntohl(tcphdr->ackno);
+  tcphdr->wnd = ntohs(tcphdr->wnd);
+
+  flags = TCPH_FLAGS(tcphdr);
+  tcplen = p->tot_len + ((flags & (TCP_FIN | TCP_SYN)) ? 1 : 0);
+
+  /* Demultiplex an incoming segment. First, we check if it is destined
+     for an active connection. */
+  prev = NULL;
+
+  
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
+    LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN);
+    if (pcb->remote_port == tcphdr->src &&
+       pcb->local_port == tcphdr->dest &&
+       ip_addr_cmp(&(pcb->remote_ip), ¤t_iphdr_src) &&
+       ip_addr_cmp(&(pcb->local_ip), ¤t_iphdr_dest)) {
+
+      /* Move this PCB to the front of the list so that subsequent
+         lookups will be faster (we exploit locality in TCP segment
+         arrivals). */
+      LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb);
+      if (prev != NULL) {
+        prev->next = pcb->next;
+        pcb->next = tcp_active_pcbs;
+        tcp_active_pcbs = pcb;
+      }
+      LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb);
+      break;
+    }
+    prev = pcb;
+  }
+
+  if (pcb == NULL) {
+    /* If it did not go to an active connection, we check the connections
+       in the TIME-WAIT state. */
+    for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+      LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+      if (pcb->remote_port == tcphdr->src &&
+         pcb->local_port == tcphdr->dest &&
+         ip_addr_cmp(&(pcb->remote_ip), ¤t_iphdr_src) &&
+         ip_addr_cmp(&(pcb->local_ip), ¤t_iphdr_dest)) {
+        /* We don't really care enough to move this PCB to the front
+           of the list since we are not very likely to receive that
+           many segments for connections in TIME-WAIT. */
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for TIME_WAITing connection.\n"));
+        tcp_timewait_input(pcb);
+        pbuf_free(p);
+        return;
+      }
+    }
+
+    /* Finally, if we still did not get a match, we check all PCBs that
+       are LISTENing for incoming connections. */
+    prev = NULL;
+    for(lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+      if (lpcb->local_port == tcphdr->dest) {
+#if SO_REUSE
+        if (ip_addr_cmp(&(lpcb->local_ip), ¤t_iphdr_dest)) {
+          /* found an exact match */
+          break;
+        } else if(ip_addr_isany(&(lpcb->local_ip))) {
+          /* found an ANY-match */
+          lpcb_any = lpcb;
+          lpcb_prev = prev;
+        }
+#else /* SO_REUSE */
+        if (ip_addr_cmp(&(lpcb->local_ip), ¤t_iphdr_dest) ||
+            ip_addr_isany(&(lpcb->local_ip))) {
+          /* found a match */
+          break;
+        }
+#endif /* SO_REUSE */
+      }
+      prev = (struct tcp_pcb *)lpcb;
+    }
+#if SO_REUSE
+    /* first try specific local IP */
+    if (lpcb == NULL) {
+      /* only pass to ANY if no specific local IP has been found */
+      lpcb = lpcb_any;
+      prev = lpcb_prev;
+    }
+#endif /* SO_REUSE */
+    if (lpcb != NULL) {
+      /* Move this PCB to the front of the list so that subsequent
+         lookups will be faster (we exploit locality in TCP segment
+         arrivals). */
+      if (prev != NULL) {
+        ((struct tcp_pcb_listen *)prev)->next = lpcb->next;
+              /* our successor is the remainder of the listening list */
+        lpcb->next = tcp_listen_pcbs.listen_pcbs;
+              /* put this listening pcb at the head of the listening list */
+        tcp_listen_pcbs.listen_pcbs = lpcb;
+      }
+    
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for LISTENing connection.\n"));
+      tcp_listen_input(lpcb);
+      pbuf_free(p);
+      return;
+    }
+  }
+
+#if TCP_INPUT_DEBUG
+  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("+-+-+-+-+-+-+-+-+-+-+-+-+-+- tcp_input: flags "));
+  tcp_debug_print_flags(TCPH_FLAGS(tcphdr));
+  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n"));
+#endif /* TCP_INPUT_DEBUG */
+
+
+  if (pcb != NULL) {
+    /* The incoming segment belongs to a connection. */
+#if TCP_INPUT_DEBUG
+#if TCP_DEBUG
+    tcp_debug_print_state(pcb->state);
+#endif /* TCP_DEBUG */
+#endif /* TCP_INPUT_DEBUG */
+
+    /* Set up a tcp_seg structure. */
+    inseg.next = NULL;
+    inseg.len = p->tot_len;
+    inseg.p = p;
+    inseg.tcphdr = tcphdr;
+
+    recv_data = NULL;
+    recv_flags = 0;
+
+    /* If there is data which was previously "refused" by upper layer */
+    if (pcb->refused_data != NULL) {
+      /* Notify again application with data previously received. */
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: notify kept packet\n"));
+      TCP_EVENT_RECV(pcb, pcb->refused_data, ERR_OK, err);
+      if (err == ERR_OK) {
+        pcb->refused_data = NULL;
+      } else if ((err == ERR_ABRT) || (tcplen > 0)) {
+        /* if err == ERR_ABRT, 'pcb' is already deallocated */
+        /* Drop incoming packets because pcb is "full" (only if the incoming
+           segment contains data). */
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: drop incoming packets, because pcb is \"full\"\n"));
+        TCP_STATS_INC(tcp.drop);
+        snmp_inc_tcpinerrs();
+        pbuf_free(p);
+        return;
+      }
+    }
+    tcp_input_pcb = pcb;
+    err = tcp_process(pcb);
+    /* A return value of ERR_ABRT means that tcp_abort() was called
+       and that the pcb has been freed. If so, we don't do anything. */
+    if (err != ERR_ABRT) {
+      if (recv_flags & TF_RESET) {
+        /* TF_RESET means that the connection was reset by the other
+           end. We then call the error callback to inform the
+           application that the connection is dead before we
+           deallocate the PCB. */
+        TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_RST);
+        tcp_pcb_remove(&tcp_active_pcbs, pcb);
+        memp_free(MEMP_TCP_PCB, pcb);
+      } else if (recv_flags & TF_CLOSED) {
+        /* The connection has been closed and we will deallocate the
+           PCB. */
+        tcp_pcb_remove(&tcp_active_pcbs, pcb);
+        memp_free(MEMP_TCP_PCB, pcb);
+      } else {
+        err = ERR_OK;
+        /* If the application has registered a "sent" function to be
+           called when new send buffer space is available, we call it
+           now. */
+        if (pcb->acked > 0) {
+          TCP_EVENT_SENT(pcb, pcb->acked, err);
+          if (err == ERR_ABRT) {
+            goto aborted;
+          }
+        }
+
+        if (recv_data != NULL) {
+          LWIP_ASSERT("pcb->refused_data == NULL", pcb->refused_data == NULL);
+          if (pcb->flags & TF_RXCLOSED) {
+            /* received data although already closed -> abort (send RST) to
+               notify the remote host that not all data has been processed */
+            pbuf_free(recv_data);
+            tcp_abort(pcb);
+            goto aborted;
+          }
+          if (flags & TCP_PSH) {
+            recv_data->flags |= PBUF_FLAG_PUSH;
+          }
+
+          /* Notify application that data has been received. */
+          TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err);
+          if (err == ERR_ABRT) {
+            goto aborted;
+          }
+
+          /* If the upper layer can't receive this data, store it */
+          if (err != ERR_OK) {
+            pcb->refused_data = recv_data;
+            LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: keep incoming packet, because pcb is \"full\"\n"));
+          }
+        }
+
+        /* If a FIN segment was received, we call the callback
+           function with a NULL buffer to indicate EOF. */
+        if (recv_flags & TF_GOT_FIN) {
+          /* correct rcv_wnd as the application won't call tcp_recved()
+             for the FIN's seqno */
+          if (pcb->rcv_wnd != TCP_WND) {
+            pcb->rcv_wnd++;
+          }
+          TCP_EVENT_CLOSED(pcb, err);
+          if (err == ERR_ABRT) {
+            goto aborted;
+          }
+        }
+
+        tcp_input_pcb = NULL;
+        /* Try to send something out. */
+        tcp_output(pcb);
+#if TCP_INPUT_DEBUG
+#if TCP_DEBUG
+        tcp_debug_print_state(pcb->state);
+#endif /* TCP_DEBUG */
+#endif /* TCP_INPUT_DEBUG */
+      }
+    }
+    /* Jump target if pcb has been aborted in a callback (by calling tcp_abort()).
+       Below this line, 'pcb' may not be dereferenced! */
+aborted:
+    tcp_input_pcb = NULL;
+    recv_data = NULL;
+
+    /* give up our reference to inseg.p */
+    if (inseg.p != NULL)
+    {
+      pbuf_free(inseg.p);
+      inseg.p = NULL;
+    }
+  } else {
+
+    /* If no matching PCB was found, send a TCP RST (reset) to the
+       sender. */
+    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_input: no PCB match found, resetting.\n"));
+    if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) {
+      TCP_STATS_INC(tcp.proterr);
+      TCP_STATS_INC(tcp.drop);
+      tcp_rst(ackno, seqno + tcplen,
+        ip_current_dest_addr(), ip_current_src_addr(),
+        tcphdr->dest, tcphdr->src);
+    }
+    pbuf_free(p);
+  }
+
+  LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane());
+  PERF_STOP("tcp_input");
+}
+
+/**
+ * Called by tcp_input() when a segment arrives for a listening
+ * connection (from tcp_input()).
+ *
+ * @param pcb the tcp_pcb_listen for which a segment arrived
+ * @return ERR_OK if the segment was processed
+ *         another err_t on error
+ *
+ * @note the return value is not (yet?) used in tcp_input()
+ * @note the segment which arrived is saved in global variables, therefore only the pcb
+ *       involved is passed as a parameter to this function
+ */
+static err_t
+tcp_listen_input(struct tcp_pcb_listen *pcb)
+{
+  struct tcp_pcb *npcb;
+  err_t rc;
+
+  /* In the LISTEN state, we check for incoming SYN segments,
+     creates a new PCB, and responds with a SYN|ACK. */
+  if (flags & TCP_ACK) {
+    /* For incoming segments with the ACK flag set, respond with a
+       RST. */
+    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n"));
+    tcp_rst(ackno + 1, seqno + tcplen,
+      ip_current_dest_addr(), ip_current_src_addr(),
+      tcphdr->dest, tcphdr->src);
+  } else if (flags & TCP_SYN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("TCP connection request %"U16_F" -> %"U16_F".\n", tcphdr->src, tcphdr->dest));
+#if TCP_LISTEN_BACKLOG
+    if (pcb->accepts_pending >= pcb->backlog) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: listen backlog exceeded for port %"U16_F"\n", tcphdr->dest));
+      return ERR_ABRT;
+    }
+#endif /* TCP_LISTEN_BACKLOG */
+    npcb = tcp_alloc(pcb->prio);
+    /* If a new PCB could not be created (probably due to lack of memory),
+       we don't do anything, but rely on the sender will retransmit the
+       SYN at a time when we have more memory available. */
+    if (npcb == NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: could not allocate PCB\n"));
+      TCP_STATS_INC(tcp.memerr);
+      return ERR_MEM;
+    }
+#if TCP_LISTEN_BACKLOG
+    pcb->accepts_pending++;
+#endif /* TCP_LISTEN_BACKLOG */
+    /* Set up the new PCB. */
+    ip_addr_copy(npcb->local_ip, current_iphdr_dest);
+    npcb->local_port = pcb->local_port;
+    ip_addr_copy(npcb->remote_ip, current_iphdr_src);
+    npcb->remote_port = tcphdr->src;
+    npcb->state = SYN_RCVD;
+    npcb->rcv_nxt = seqno + 1;
+    npcb->rcv_ann_right_edge = npcb->rcv_nxt;
+    npcb->snd_wnd = tcphdr->wnd;
+    npcb->ssthresh = npcb->snd_wnd;
+    npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */
+    npcb->callback_arg = pcb->callback_arg;
+#if LWIP_CALLBACK_API
+    npcb->accept = pcb->accept;
+#endif /* LWIP_CALLBACK_API */
+    /* inherit socket options */
+    npcb->so_options = pcb->so_options & SOF_INHERITED;
+    /* Register the new PCB so that we can begin receiving segments
+       for it. */
+    TCP_REG(&tcp_active_pcbs, npcb);
+
+    /* Parse any options in the SYN. */
+    tcp_parseopt(npcb);
+#if TCP_CALCULATE_EFF_SEND_MSS
+    npcb->mss = tcp_eff_send_mss(npcb->mss, &(npcb->remote_ip));
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+
+    snmp_inc_tcppassiveopens();
+
+    /* Send a SYN|ACK together with the MSS option. */
+    rc = tcp_enqueue_flags(npcb, TCP_SYN | TCP_ACK);
+    if (rc != ERR_OK) {
+      tcp_abandon(npcb, 0);
+      return rc;
+    }
+    return tcp_output(npcb);
+  }
+  return ERR_OK;
+}
+
+/**
+ * Called by tcp_input() when a segment arrives for a connection in
+ * TIME_WAIT.
+ *
+ * @param pcb the tcp_pcb for which a segment arrived
+ *
+ * @note the segment which arrived is saved in global variables, therefore only the pcb
+ *       involved is passed as a parameter to this function
+ */
+static err_t
+tcp_timewait_input(struct tcp_pcb *pcb)
+{
+  /* RFC 1337: in TIME_WAIT, ignore RST and ACK FINs + any 'acceptable' segments */
+  /* RFC 793 3.9 Event Processing - Segment Arrives:
+   * - first check sequence number - we skip that one in TIME_WAIT (always
+   *   acceptable since we only send ACKs)
+   * - second check the RST bit (... return) */
+  if (flags & TCP_RST)  {
+    return ERR_OK;
+  }
+  /* - fourth, check the SYN bit, */
+  if (flags & TCP_SYN) {
+    /* If an incoming segment is not acceptable, an acknowledgment
+       should be sent in reply */
+    if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt+pcb->rcv_wnd)) {
+      /* If the SYN is in the window it is an error, send a reset */
+      tcp_rst(ackno, seqno + tcplen, ip_current_dest_addr(), ip_current_src_addr(),
+        tcphdr->dest, tcphdr->src);
+      return ERR_OK;
+    }
+  } else if (flags & TCP_FIN) {
+    /* - eighth, check the FIN bit: Remain in the TIME-WAIT state.
+         Restart the 2 MSL time-wait timeout.*/
+    pcb->tmr = tcp_ticks;
+  }
+
+  if ((tcplen > 0))  {
+    /* Acknowledge data, FIN or out-of-window SYN */
+    pcb->flags |= TF_ACK_NOW;
+    return tcp_output(pcb);
+  }
+  return ERR_OK;
+}
+
+/**
+ * Implements the TCP state machine. Called by tcp_input. In some
+ * states tcp_receive() is called to receive data. The tcp_seg
+ * argument will be freed by the caller (tcp_input()) unless the
+ * recv_data pointer in the pcb is set.
+ *
+ * @param pcb the tcp_pcb for which a segment arrived
+ *
+ * @note the segment which arrived is saved in global variables, therefore only the pcb
+ *       involved is passed as a parameter to this function
+ */
+static err_t
+tcp_process(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *rseg;
+  u8_t acceptable = 0;
+  err_t err;
+
+  err = ERR_OK;
+
+  /* Process incoming RST segments. */
+  if (flags & TCP_RST) {
+    /* First, determine if the reset is acceptable. */
+    if (pcb->state == SYN_SENT) {
+      if (ackno == pcb->snd_nxt) {
+        acceptable = 1;
+      }
+    } else {
+      if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, 
+                          pcb->rcv_nxt+pcb->rcv_wnd)) {
+        acceptable = 1;
+      }
+    }
+
+    if (acceptable) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n"));
+      LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED);
+      recv_flags |= TF_RESET;
+      pcb->flags &= ~TF_ACK_DELAY;
+      return ERR_RST;
+    } else {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
+       seqno, pcb->rcv_nxt));
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
+       seqno, pcb->rcv_nxt));
+      return ERR_OK;
+    }
+  }
+
+  if ((flags & TCP_SYN) && (pcb->state != SYN_SENT && pcb->state != SYN_RCVD)) { 
+    /* Cope with new connection attempt after remote end crashed */
+    tcp_ack_now(pcb);
+    return ERR_OK;
+  }
+  
+  if ((pcb->flags & TF_RXCLOSED) == 0) {
+    /* Update the PCB (in)activity timer unless rx is closed (see tcp_shutdown) */
+    pcb->tmr = tcp_ticks;
+  }
+  pcb->keep_cnt_sent = 0;
+
+  tcp_parseopt(pcb);
+
+  /* Do different things depending on the TCP state. */
+  switch (pcb->state) {
+  case SYN_SENT:
+    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno,
+     pcb->snd_nxt, ntohl(pcb->unacked->tcphdr->seqno)));
+    /* received SYN ACK with expected sequence number? */
+    if ((flags & TCP_ACK) && (flags & TCP_SYN)
+        && ackno == ntohl(pcb->unacked->tcphdr->seqno) + 1) {
+      pcb->snd_buf++;
+      pcb->rcv_nxt = seqno + 1;
+      pcb->rcv_ann_right_edge = pcb->rcv_nxt;
+      pcb->lastack = ackno;
+      pcb->snd_wnd = tcphdr->wnd;
+      pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */
+      pcb->state = ESTABLISHED;
+
+#if TCP_CALCULATE_EFF_SEND_MSS
+      pcb->mss = tcp_eff_send_mss(pcb->mss, &(pcb->remote_ip));
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+
+      /* Set ssthresh again after changing pcb->mss (already set in tcp_connect
+       * but for the default value of pcb->mss) */
+      pcb->ssthresh = pcb->mss * 10;
+
+      pcb->cwnd = ((pcb->cwnd == 1) ? (pcb->mss * 2) : pcb->mss);
+      LWIP_ASSERT("pcb->snd_queuelen > 0", (pcb->snd_queuelen > 0));
+      --pcb->snd_queuelen;
+      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"U16_F"\n", (u16_t)pcb->snd_queuelen));
+      rseg = pcb->unacked;
+      pcb->unacked = rseg->next;
+
+      /* If there's nothing left to acknowledge, stop the retransmit
+         timer, otherwise reset it to start again */
+      if(pcb->unacked == NULL)
+        pcb->rtime = -1;
+      else {
+        pcb->rtime = 0;
+        pcb->nrtx = 0;
+      }
+
+      tcp_seg_free(rseg);
+
+      /* Call the user specified function to call when sucessfully
+       * connected. */
+      TCP_EVENT_CONNECTED(pcb, ERR_OK, err);
+      if (err == ERR_ABRT) {
+        return ERR_ABRT;
+      }
+      tcp_ack_now(pcb);
+    }
+    /* received ACK? possibly a half-open connection */
+    else if (flags & TCP_ACK) {
+      /* send a RST to bring the other side in a non-synchronized state. */
+      tcp_rst(ackno, seqno + tcplen, ip_current_dest_addr(), ip_current_src_addr(),
+        tcphdr->dest, tcphdr->src);
+    }
+    break;
+  case SYN_RCVD:
+    if (flags & TCP_ACK) {
+      /* expected ACK number? */
+      if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)) {
+        u16_t old_cwnd;
+        pcb->state = ESTABLISHED;
+        LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+#if LWIP_CALLBACK_API
+        LWIP_ASSERT("pcb->accept != NULL", pcb->accept != NULL);
+#endif
+        /* Call the accept function. */
+        TCP_EVENT_ACCEPT(pcb, ERR_OK, err);
+        if (err != ERR_OK) {
+          /* If the accept function returns with an error, we abort
+           * the connection. */
+          /* Already aborted? */
+          if (err != ERR_ABRT) {
+            tcp_abort(pcb);
+          }
+          return ERR_ABRT;
+        }
+        old_cwnd = pcb->cwnd;
+        /* If there was any data contained within this ACK,
+         * we'd better pass it on to the application as well. */
+        tcp_receive(pcb);
+
+        /* Prevent ACK for SYN to generate a sent event */
+        if (pcb->acked != 0) {
+          pcb->acked--;
+        }
+
+        pcb->cwnd = ((old_cwnd == 1) ? (pcb->mss * 2) : pcb->mss);
+
+        if (recv_flags & TF_GOT_FIN) {
+          tcp_ack_now(pcb);
+          pcb->state = CLOSE_WAIT;
+        }
+      } else {
+        /* incorrect ACK number, send RST */
+        tcp_rst(ackno, seqno + tcplen, ip_current_dest_addr(), ip_current_src_addr(),
+                tcphdr->dest, tcphdr->src);
+      }
+    } else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) {
+      /* Looks like another copy of the SYN - retransmit our SYN-ACK */
+      tcp_rexmit(pcb);
+    }
+    break;
+  case CLOSE_WAIT:
+    /* FALLTHROUGH */
+  case ESTABLISHED:
+    tcp_receive(pcb);
+    if (recv_flags & TF_GOT_FIN) { /* passive close */
+      tcp_ack_now(pcb);
+      pcb->state = CLOSE_WAIT;
+    }
+    break;
+  case FIN_WAIT_1:
+    tcp_receive(pcb);
+    if (recv_flags & TF_GOT_FIN) {
+      if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt)) {
+        LWIP_DEBUGF(TCP_DEBUG,
+          ("TCP connection closed: FIN_WAIT_1 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+        tcp_ack_now(pcb);
+        tcp_pcb_purge(pcb);
+        TCP_RMV(&tcp_active_pcbs, pcb);
+        pcb->state = TIME_WAIT;
+        TCP_REG(&tcp_tw_pcbs, pcb);
+      } else {
+        tcp_ack_now(pcb);
+        pcb->state = CLOSING;
+      }
+    } else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt)) {
+      pcb->state = FIN_WAIT_2;
+    }
+    break;
+  case FIN_WAIT_2:
+    tcp_receive(pcb);
+    if (recv_flags & TF_GOT_FIN) {
+      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: FIN_WAIT_2 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+      tcp_ack_now(pcb);
+      tcp_pcb_purge(pcb);
+      TCP_RMV(&tcp_active_pcbs, pcb);
+      pcb->state = TIME_WAIT;
+      TCP_REG(&tcp_tw_pcbs, pcb);
+    }
+    break;
+  case CLOSING:
+    tcp_receive(pcb);
+    if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: CLOSING %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+      tcp_pcb_purge(pcb);
+      TCP_RMV(&tcp_active_pcbs, pcb);
+      pcb->state = TIME_WAIT;
+      TCP_REG(&tcp_tw_pcbs, pcb);
+    }
+    break;
+  case LAST_ACK:
+    tcp_receive(pcb);
+    if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: LAST_ACK %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+      /* bugfix #21699: don't set pcb->state to CLOSED here or we risk leaking segments */
+      recv_flags |= TF_CLOSED;
+    }
+    break;
+  default:
+    break;
+  }
+  return ERR_OK;
+}
+
+#if TCP_QUEUE_OOSEQ
+/**
+ * Insert segment into the list (segments covered with new one will be deleted)
+ *
+ * Called from tcp_receive()
+ */
+static void
+tcp_oos_insert_segment(struct tcp_seg *cseg, struct tcp_seg *next)
+{
+  struct tcp_seg *old_seg;
+
+  if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
+    /* received segment overlaps all following segments */
+    tcp_segs_free(next);
+    next = NULL;
+  }
+  else {
+    /* delete some following segments
+       oos queue may have segments with FIN flag */
+    while (next &&
+           TCP_SEQ_GEQ((seqno + cseg->len),
+                      (next->tcphdr->seqno + next->len))) {
+      /* cseg with FIN already processed */
+      if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) {
+        TCPH_SET_FLAG(cseg->tcphdr, TCP_FIN);
+      }
+      old_seg = next;
+      next = next->next;
+      tcp_seg_free(old_seg);
+    }
+    if (next &&
+        TCP_SEQ_GT(seqno + cseg->len, next->tcphdr->seqno)) {
+      /* We need to trim the incoming segment. */
+      cseg->len = (u16_t)(next->tcphdr->seqno - seqno);
+      pbuf_realloc(cseg->p, cseg->len);
+    }
+  }
+  cseg->next = next;
+}
+#endif /* TCP_QUEUE_OOSEQ */
+
+/**
+ * Called by tcp_process. Checks if the given segment is an ACK for outstanding
+ * data, and if so frees the memory of the buffered data. Next, is places the
+ * segment on any of the receive queues (pcb->recved or pcb->ooseq). If the segment
+ * is buffered, the pbuf is referenced by pbuf_ref so that it will not be freed until
+ * i it has been removed from the buffer.
+ *
+ * If the incoming segment constitutes an ACK for a segment that was used for RTT
+ * estimation, the RTT is estimated here as well.
+ *
+ * Called from tcp_process().
+ */
+static void
+tcp_receive(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *next;
+#if TCP_QUEUE_OOSEQ
+  struct tcp_seg *prev, *cseg;
+#endif /* TCP_QUEUE_OOSEQ */
+  struct pbuf *p;
+  s32_t off;
+  s16_t m;
+  u32_t right_wnd_edge;
+  u16_t new_tot_len;
+  int found_dupack = 0;
+
+  if (flags & TCP_ACK) {
+    right_wnd_edge = pcb->snd_wnd + pcb->snd_wl2;
+
+    /* Update window. */
+    if (TCP_SEQ_LT(pcb->snd_wl1, seqno) ||
+       (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
+       (pcb->snd_wl2 == ackno && tcphdr->wnd > pcb->snd_wnd)) {
+      pcb->snd_wnd = tcphdr->wnd;
+      pcb->snd_wl1 = seqno;
+      pcb->snd_wl2 = ackno;
+      if (pcb->snd_wnd > 0 && pcb->persist_backoff > 0) {
+          pcb->persist_backoff = 0;
+      }
+      LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: window update %"U16_F"\n", pcb->snd_wnd));
+#if TCP_WND_DEBUG
+    } else {
+      if (pcb->snd_wnd != tcphdr->wnd) {
+        LWIP_DEBUGF(TCP_WND_DEBUG, 
+                    ("tcp_receive: no window update lastack %"U32_F" ackno %"
+                     U32_F" wl1 %"U32_F" seqno %"U32_F" wl2 %"U32_F"\n",
+                     pcb->lastack, ackno, pcb->snd_wl1, seqno, pcb->snd_wl2));
+      }
+#endif /* TCP_WND_DEBUG */
+    }
+
+    /* (From Stevens TCP/IP Illustrated Vol II, p970.) Its only a
+     * duplicate ack if:
+     * 1) It doesn't ACK new data 
+     * 2) length of received packet is zero (i.e. no payload) 
+     * 3) the advertised window hasn't changed 
+     * 4) There is outstanding unacknowledged data (retransmission timer running)
+     * 5) The ACK is == biggest ACK sequence number so far seen (snd_una)
+     * 
+     * If it passes all five, should process as a dupack: 
+     * a) dupacks < 3: do nothing 
+     * b) dupacks == 3: fast retransmit 
+     * c) dupacks > 3: increase cwnd 
+     * 
+     * If it only passes 1-3, should reset dupack counter (and add to
+     * stats, which we don't do in lwIP)
+     *
+     * If it only passes 1, should reset dupack counter
+     *
+     */
+
+    /* Clause 1 */
+    if (TCP_SEQ_LEQ(ackno, pcb->lastack)) {
+      pcb->acked = 0;
+      /* Clause 2 */
+      if (tcplen == 0) {
+        /* Clause 3 */
+        if (pcb->snd_wl2 + pcb->snd_wnd == right_wnd_edge){
+          /* Clause 4 */
+          if (pcb->rtime >= 0) {
+            /* Clause 5 */
+            if (pcb->lastack == ackno) {
+              found_dupack = 1;
+              if (pcb->dupacks + 1 > pcb->dupacks)
+                ++pcb->dupacks;
+              if (pcb->dupacks > 3) {
+                /* Inflate the congestion window, but not if it means that
+                   the value overflows. */
+                if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) {
+                  pcb->cwnd += pcb->mss;
+                }
+              } else if (pcb->dupacks == 3) {
+                /* Do fast retransmit */
+                tcp_rexmit_fast(pcb);
+              }
+            }
+          }
+        }
+      }
+      /* If Clause (1) or more is true, but not a duplicate ack, reset
+       * count of consecutive duplicate acks */
+      if (!found_dupack) {
+        pcb->dupacks = 0;
+      }
+    } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)){
+      /* We come here when the ACK acknowledges new data. */
+
+      /* Reset the "IN Fast Retransmit" flag, since we are no longer
+         in fast retransmit. Also reset the congestion window to the
+         slow start threshold. */
+      if (pcb->flags & TF_INFR) {
+        pcb->flags &= ~TF_INFR;
+        pcb->cwnd = pcb->ssthresh;
+      }
+
+      /* Reset the number of retransmissions. */
+      pcb->nrtx = 0;
+
+      /* Reset the retransmission time-out. */
+      pcb->rto = (pcb->sa >> 3) + pcb->sv;
+
+      /* Update the send buffer space. Diff between the two can never exceed 64K? */
+      pcb->acked = (u16_t)(ackno - pcb->lastack);
+
+      pcb->snd_buf += pcb->acked;
+
+      /* Reset the fast retransmit variables. */
+      pcb->dupacks = 0;
+      pcb->lastack = ackno;
+
+      /* Update the congestion control variables (cwnd and
+         ssthresh). */
+      if (pcb->state >= ESTABLISHED) {
+        if (pcb->cwnd < pcb->ssthresh) {
+          if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) {
+            pcb->cwnd += pcb->mss;
+          }
+          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"U16_F"\n", pcb->cwnd));
+        } else {
+          u16_t new_cwnd = (pcb->cwnd + pcb->mss * pcb->mss / pcb->cwnd);
+          if (new_cwnd > pcb->cwnd) {
+            pcb->cwnd = new_cwnd;
+          }
+          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: congestion avoidance cwnd %"U16_F"\n", pcb->cwnd));
+        }
+      }
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: ACK for %"U32_F", unacked->seqno %"U32_F":%"U32_F"\n",
+                                    ackno,
+                                    pcb->unacked != NULL?
+                                    ntohl(pcb->unacked->tcphdr->seqno): 0,
+                                    pcb->unacked != NULL?
+                                    ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked): 0));
+
+      /* Remove segment from the unacknowledged list if the incoming
+         ACK acknowlegdes them. */
+      while (pcb->unacked != NULL &&
+             TCP_SEQ_LEQ(ntohl(pcb->unacked->tcphdr->seqno) +
+                         TCP_TCPLEN(pcb->unacked), ackno)) {
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unacked\n",
+                                      ntohl(pcb->unacked->tcphdr->seqno),
+                                      ntohl(pcb->unacked->tcphdr->seqno) +
+                                      TCP_TCPLEN(pcb->unacked)));
+
+        next = pcb->unacked;
+        pcb->unacked = pcb->unacked->next;
+
+        LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen));
+        LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= pbuf_clen(next->p)));
+        /* Prevent ACK for FIN to generate a sent event */
+        if ((pcb->acked != 0) && ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0)) {
+          pcb->acked--;
+        }
+
+        pcb->snd_queuelen -= pbuf_clen(next->p);
+        tcp_seg_free(next);
+
+        LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unacked)\n", (u16_t)pcb->snd_queuelen));
+        if (pcb->snd_queuelen != 0) {
+          LWIP_ASSERT("tcp_receive: valid queue length", pcb->unacked != NULL ||
+                      pcb->unsent != NULL);
+        }
+      }
+
+      /* If there's nothing left to acknowledge, stop the retransmit
+         timer, otherwise reset it to start again */
+      if(pcb->unacked == NULL)
+        pcb->rtime = -1;
+      else
+        pcb->rtime = 0;
+
+      pcb->polltmr = 0;
+    } else {
+      /* Fix bug bug #21582: out of sequence ACK, didn't really ack anything */
+      pcb->acked = 0;
+    }
+
+    /* We go through the ->unsent list to see if any of the segments
+       on the list are acknowledged by the ACK. This may seem
+       strange since an "unsent" segment shouldn't be acked. The
+       rationale is that lwIP puts all outstanding segments on the
+       ->unsent list after a retransmission, so these segments may
+       in fact have been sent once. */
+    while (pcb->unsent != NULL &&
+           TCP_SEQ_BETWEEN(ackno, ntohl(pcb->unsent->tcphdr->seqno) + 
+                           TCP_TCPLEN(pcb->unsent), pcb->snd_nxt)) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unsent\n",
+                                    ntohl(pcb->unsent->tcphdr->seqno), ntohl(pcb->unsent->tcphdr->seqno) +
+                                    TCP_TCPLEN(pcb->unsent)));
+
+      next = pcb->unsent;
+      pcb->unsent = pcb->unsent->next;
+      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen));
+      LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= pbuf_clen(next->p)));
+      /* Prevent ACK for FIN to generate a sent event */
+      if ((pcb->acked != 0) && ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0)) {
+        pcb->acked--;
+      }
+      pcb->snd_queuelen -= pbuf_clen(next->p);
+      tcp_seg_free(next);
+      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unsent)\n", (u16_t)pcb->snd_queuelen));
+      if (pcb->snd_queuelen != 0) {
+        LWIP_ASSERT("tcp_receive: valid queue length",
+          pcb->unacked != NULL || pcb->unsent != NULL);
+      }
+    }
+    /* End of ACK for new data processing. */
+
+    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: pcb->rttest %"U32_F" rtseq %"U32_F" ackno %"U32_F"\n",
+                                pcb->rttest, pcb->rtseq, ackno));
+
+    /* RTT estimation calculations. This is done by checking if the
+       incoming segment acknowledges the segment we use to take a
+       round-trip time measurement. */
+    if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) {
+      /* diff between this shouldn't exceed 32K since this are tcp timer ticks
+         and a round-trip shouldn't be that long... */
+      m = (s16_t)(tcp_ticks - pcb->rttest);
+
+      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n",
+                                  m, m * TCP_SLOW_INTERVAL));
+
+      /* This is taken directly from VJs original code in his paper */
+      m = m - (pcb->sa >> 3);
+      pcb->sa += m;
+      if (m < 0) {
+        m = -m;
+      }
+      m = m - (pcb->sv >> 2);
+      pcb->sv += m;
+      pcb->rto = (pcb->sa >> 3) + pcb->sv;
+
+      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" milliseconds)\n",
+                                  pcb->rto, pcb->rto * TCP_SLOW_INTERVAL));
+
+      pcb->rttest = 0;
+    }
+  }
+
+  /* If the incoming segment contains data, we must process it
+     further. */
+  if (tcplen > 0) {
+    /* This code basically does three things:
+
+    +) If the incoming segment contains data that is the next
+    in-sequence data, this data is passed to the application. This
+    might involve trimming the first edge of the data. The rcv_nxt
+    variable and the advertised window are adjusted.
+
+    +) If the incoming segment has data that is above the next
+    sequence number expected (->rcv_nxt), the segment is placed on
+    the ->ooseq queue. This is done by finding the appropriate
+    place in the ->ooseq queue (which is ordered by sequence
+    number) and trim the segment in both ends if needed. An
+    immediate ACK is sent to indicate that we received an
+    out-of-sequence segment.
+
+    +) Finally, we check if the first segment on the ->ooseq queue
+    now is in sequence (i.e., if rcv_nxt >= ooseq->seqno). If
+    rcv_nxt > ooseq->seqno, we must trim the first edge of the
+    segment on ->ooseq before we adjust rcv_nxt. The data in the
+    segments that are now on sequence are chained onto the
+    incoming segment so that we only need to call the application
+    once.
+    */
+
+    /* First, we check if we must trim the first edge. We have to do
+       this if the sequence number of the incoming segment is less
+       than rcv_nxt, and the sequence number plus the length of the
+       segment is larger than rcv_nxt. */
+    /*    if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){
+          if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/
+    if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)){
+      /* Trimming the first edge is done by pushing the payload
+         pointer in the pbuf downwards. This is somewhat tricky since
+         we do not want to discard the full contents of the pbuf up to
+         the new starting point of the data since we have to keep the
+         TCP header which is present in the first pbuf in the chain.
+
+         What is done is really quite a nasty hack: the first pbuf in
+         the pbuf chain is pointed to by inseg.p. Since we need to be
+         able to deallocate the whole pbuf, we cannot change this
+         inseg.p pointer to point to any of the later pbufs in the
+         chain. Instead, we point the ->payload pointer in the first
+         pbuf to data in one of the later pbufs. We also set the
+         inseg.data pointer to point to the right place. This way, the
+         ->p pointer will still point to the first pbuf, but the
+         ->p->payload pointer will point to data in another pbuf.
+
+         After we are done with adjusting the pbuf pointers we must
+         adjust the ->data pointer in the seg and the segment
+         length.*/
+
+      off = pcb->rcv_nxt - seqno;
+      p = inseg.p;
+      LWIP_ASSERT("inseg.p != NULL", inseg.p);
+      LWIP_ASSERT("insane offset!", (off < 0x7fff));
+      if (inseg.p->len < off) {
+        LWIP_ASSERT("pbuf too short!", (((s32_t)inseg.p->tot_len) >= off));
+        new_tot_len = (u16_t)(inseg.p->tot_len - off);
+        while (p->len < off) {
+          off -= p->len;
+          /* KJM following line changed (with addition of new_tot_len var)
+             to fix bug #9076
+             inseg.p->tot_len -= p->len; */
+          p->tot_len = new_tot_len;
+          p->len = 0;
+          p = p->next;
+        }
+        if(pbuf_header(p, (s16_t)-off)) {
+          /* Do we need to cope with this failing?  Assert for now */
+          LWIP_ASSERT("pbuf_header failed", 0);
+        }
+      } else {
+        if(pbuf_header(inseg.p, (s16_t)-off)) {
+          /* Do we need to cope with this failing?  Assert for now */
+          LWIP_ASSERT("pbuf_header failed", 0);
+        }
+      }
+      inseg.len -= (u16_t)(pcb->rcv_nxt - seqno);
+      inseg.tcphdr->seqno = seqno = pcb->rcv_nxt;
+    }
+    else {
+      if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){
+        /* the whole segment is < rcv_nxt */
+        /* must be a duplicate of a packet that has already been correctly handled */
+
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno));
+        tcp_ack_now(pcb);
+      }
+    }
+
+    /* The sequence number must be within the window (above rcv_nxt
+       and below rcv_nxt + rcv_wnd) in order to be further
+       processed. */
+    if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, 
+                        pcb->rcv_nxt + pcb->rcv_wnd - 1)){
+      if (pcb->rcv_nxt == seqno) {
+        /* The incoming segment is the next in sequence. We check if
+           we have to trim the end of the segment and update rcv_nxt
+           and pass the data to the application. */
+        tcplen = TCP_TCPLEN(&inseg);
+
+        if (tcplen > pcb->rcv_wnd) {
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, 
+                      ("tcp_receive: other end overran receive window"
+                       "seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n",
+                       seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd));
+          if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
+            /* Must remove the FIN from the header as we're trimming 
+             * that byte of sequence-space from the packet */
+            TCPH_FLAGS_SET(inseg.tcphdr, TCPH_FLAGS(inseg.tcphdr) &~ TCP_FIN);
+          }
+          /* Adjust length of segment to fit in the window. */
+          inseg.len = pcb->rcv_wnd;
+          if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) {
+            inseg.len -= 1;
+          }
+          pbuf_realloc(inseg.p, inseg.len);
+          tcplen = TCP_TCPLEN(&inseg);
+          LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n",
+                      (seqno + tcplen) == (pcb->rcv_nxt + pcb->rcv_wnd));
+        }
+#if TCP_QUEUE_OOSEQ
+        /* Received in-sequence data, adjust ooseq data if:
+           - FIN has been received or
+           - inseq overlaps with ooseq */
+        if (pcb->ooseq != NULL) {
+          if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
+            LWIP_DEBUGF(TCP_INPUT_DEBUG, 
+                        ("tcp_receive: received in-order FIN, binning ooseq queue\n"));
+            /* Received in-order FIN means anything that was received
+             * out of order must now have been received in-order, so
+             * bin the ooseq queue */
+            while (pcb->ooseq != NULL) {
+              struct tcp_seg *old_ooseq = pcb->ooseq;
+              pcb->ooseq = pcb->ooseq->next;
+              tcp_seg_free(old_ooseq);
+            }
+          }
+          else {
+            next = pcb->ooseq;
+            /* Remove all segments on ooseq that are covered by inseg already.
+             * FIN is copied from ooseq to inseg if present. */
+            while (next &&
+                   TCP_SEQ_GEQ(seqno + tcplen,
+                               next->tcphdr->seqno + next->len)) {
+              /* inseg cannot have FIN here (already processed above) */
+              if (TCPH_FLAGS(next->tcphdr) & TCP_FIN &&
+                  (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) == 0) {
+                TCPH_SET_FLAG(inseg.tcphdr, TCP_FIN);
+                tcplen = TCP_TCPLEN(&inseg);
+              }
+              prev = next;
+              next = next->next;
+              tcp_seg_free(prev);
+            }
+            /* Now trim right side of inseg if it overlaps with the first
+             * segment on ooseq */
+            if (next &&
+                TCP_SEQ_GT(seqno + tcplen,
+                           next->tcphdr->seqno)) {
+              /* inseg cannot have FIN here (already processed above) */
+              inseg.len = (u16_t)(next->tcphdr->seqno - seqno);
+              if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) {
+                inseg.len -= 1;
+              }
+              pbuf_realloc(inseg.p, inseg.len);
+              tcplen = TCP_TCPLEN(&inseg);
+              LWIP_ASSERT("tcp_receive: segment not trimmed correctly to ooseq queue\n",
+                          (seqno + tcplen) == next->tcphdr->seqno);
+            }
+            pcb->ooseq = next;
+          }
+        }
+#endif /* TCP_QUEUE_OOSEQ */
+
+        pcb->rcv_nxt = seqno + tcplen;
+
+        /* Update the receiver's (our) window. */
+        LWIP_ASSERT("tcp_receive: tcplen > rcv_wnd\n", pcb->rcv_wnd >= tcplen);
+        pcb->rcv_wnd -= tcplen;
+
+        tcp_update_rcv_ann_wnd(pcb);
+
+        /* If there is data in the segment, we make preparations to
+           pass this up to the application. The ->recv_data variable
+           is used for holding the pbuf that goes to the
+           application. The code for reassembling out-of-sequence data
+           chains its data on this pbuf as well.
+
+           If the segment was a FIN, we set the TF_GOT_FIN flag that will
+           be used to indicate to the application that the remote side has
+           closed its end of the connection. */
+        if (inseg.p->tot_len > 0) {
+          recv_data = inseg.p;
+          /* Since this pbuf now is the responsibility of the
+             application, we delete our reference to it so that we won't
+             (mistakingly) deallocate it. */
+          inseg.p = NULL;
+        }
+        if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n"));
+          recv_flags |= TF_GOT_FIN;
+        }
+
+#if TCP_QUEUE_OOSEQ
+        /* We now check if we have segments on the ->ooseq queue that
+           are now in sequence. */
+        while (pcb->ooseq != NULL &&
+               pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) {
+
+          cseg = pcb->ooseq;
+          seqno = pcb->ooseq->tcphdr->seqno;
+
+          pcb->rcv_nxt += TCP_TCPLEN(cseg);
+          LWIP_ASSERT("tcp_receive: ooseq tcplen > rcv_wnd\n",
+                      pcb->rcv_wnd >= TCP_TCPLEN(cseg));
+          pcb->rcv_wnd -= TCP_TCPLEN(cseg);
+
+          tcp_update_rcv_ann_wnd(pcb);
+
+          if (cseg->p->tot_len > 0) {
+            /* Chain this pbuf onto the pbuf that we will pass to
+               the application. */
+            if (recv_data) {
+              pbuf_cat(recv_data, cseg->p);
+            } else {
+              recv_data = cseg->p;
+            }
+            cseg->p = NULL;
+          }
+          if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
+            LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n"));
+            recv_flags |= TF_GOT_FIN;
+            if (pcb->state == ESTABLISHED) { /* force passive close or we can move to active close */
+              pcb->state = CLOSE_WAIT;
+            } 
+          }
+
+          pcb->ooseq = cseg->next;
+          tcp_seg_free(cseg);
+        }
+#endif /* TCP_QUEUE_OOSEQ */
+
+
+        /* Acknowledge the segment(s). */
+        tcp_ack(pcb);
+
+      } else {
+        /* We get here if the incoming segment is out-of-sequence. */
+        tcp_send_empty_ack(pcb);
+#if TCP_QUEUE_OOSEQ
+        /* We queue the segment on the ->ooseq queue. */
+        if (pcb->ooseq == NULL) {
+          pcb->ooseq = tcp_seg_copy(&inseg);
+        } else {
+          /* If the queue is not empty, we walk through the queue and
+             try to find a place where the sequence number of the
+             incoming segment is between the sequence numbers of the
+             previous and the next segment on the ->ooseq queue. That is
+             the place where we put the incoming segment. If needed, we
+             trim the second edges of the previous and the incoming
+             segment so that it will fit into the sequence.
+
+             If the incoming segment has the same sequence number as a
+             segment on the ->ooseq queue, we discard the segment that
+             contains less data. */
+
+          prev = NULL;
+          for(next = pcb->ooseq; next != NULL; next = next->next) {
+            if (seqno == next->tcphdr->seqno) {
+              /* The sequence number of the incoming segment is the
+                 same as the sequence number of the segment on
+                 ->ooseq. We check the lengths to see which one to
+                 discard. */
+              if (inseg.len > next->len) {
+                /* The incoming segment is larger than the old
+                   segment. We replace some segments with the new
+                   one. */
+                cseg = tcp_seg_copy(&inseg);
+                if (cseg != NULL) {
+                  if (prev != NULL) {
+                    prev->next = cseg;
+                  } else {
+                    pcb->ooseq = cseg;
+                  }
+                  tcp_oos_insert_segment(cseg, next);
+                }
+                break;
+              } else {
+                /* Either the lenghts are the same or the incoming
+                   segment was smaller than the old one; in either
+                   case, we ditch the incoming segment. */
+                break;
+              }
+            } else {
+              if (prev == NULL) {
+                if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {
+                  /* The sequence number of the incoming segment is lower
+                     than the sequence number of the first segment on the
+                     queue. We put the incoming segment first on the
+                     queue. */
+                  cseg = tcp_seg_copy(&inseg);
+                  if (cseg != NULL) {
+                    pcb->ooseq = cseg;
+                    tcp_oos_insert_segment(cseg, next);
+                  }
+                  break;
+                }
+              } else {
+                /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) &&
+                  TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/
+                if (TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno+1, next->tcphdr->seqno-1)) {
+                  /* The sequence number of the incoming segment is in
+                     between the sequence numbers of the previous and
+                     the next segment on ->ooseq. We trim trim the previous
+                     segment, delete next segments that included in received segment
+                     and trim received, if needed. */
+                  cseg = tcp_seg_copy(&inseg);
+                  if (cseg != NULL) {
+                    if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) {
+                      /* We need to trim the prev segment. */
+                      prev->len = (u16_t)(seqno - prev->tcphdr->seqno);
+                      pbuf_realloc(prev->p, prev->len);
+                    }
+                    prev->next = cseg;
+                    tcp_oos_insert_segment(cseg, next);
+                  }
+                  break;
+                }
+              }
+              /* If the "next" segment is the last segment on the
+                 ooseq queue, we add the incoming segment to the end
+                 of the list. */
+              if (next->next == NULL &&
+                  TCP_SEQ_GT(seqno, next->tcphdr->seqno)) {
+                if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) {
+                  /* segment "next" already contains all data */
+                  break;
+                }
+                next->next = tcp_seg_copy(&inseg);
+                if (next->next != NULL) {
+                  if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) {
+                    /* We need to trim the last segment. */
+                    next->len = (u16_t)(seqno - next->tcphdr->seqno);
+                    pbuf_realloc(next->p, next->len);
+                  }
+                  /* check if the remote side overruns our receive window */
+                  if ((u32_t)tcplen + seqno > pcb->rcv_nxt + (u32_t)pcb->rcv_wnd) {
+                    LWIP_DEBUGF(TCP_INPUT_DEBUG, 
+                                ("tcp_receive: other end overran receive window"
+                                 "seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n",
+                                 seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd));
+                    if (TCPH_FLAGS(next->next->tcphdr) & TCP_FIN) {
+                      /* Must remove the FIN from the header as we're trimming 
+                       * that byte of sequence-space from the packet */
+                      TCPH_FLAGS_SET(next->next->tcphdr, TCPH_FLAGS(next->next->tcphdr) &~ TCP_FIN);
+                    }
+                    /* Adjust length of segment to fit in the window. */
+                    next->next->len = pcb->rcv_nxt + pcb->rcv_wnd - seqno;
+                    pbuf_realloc(next->next->p, next->next->len);
+                    tcplen = TCP_TCPLEN(next->next);
+                    LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n",
+                                (seqno + tcplen) == (pcb->rcv_nxt + pcb->rcv_wnd));
+                  }
+                }
+                break;
+              }
+            }
+            prev = next;
+          }
+        }
+#endif /* TCP_QUEUE_OOSEQ */
+
+      }
+    } else {
+      /* The incoming segment is not withing the window. */
+      tcp_send_empty_ack(pcb);
+    }
+  } else {
+    /* Segments with length 0 is taken care of here. Segments that
+       fall out of the window are ACKed. */
+    /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) ||
+      TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
+    if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){
+      tcp_ack_now(pcb);
+    }
+  }
+}
+
+/**
+ * Parses the options contained in the incoming segment. 
+ *
+ * Called from tcp_listen_input() and tcp_process().
+ * Currently, only the MSS option is supported!
+ *
+ * @param pcb the tcp_pcb for which a segment arrived
+ */
+static void
+tcp_parseopt(struct tcp_pcb *pcb)
+{
+  u16_t c, max_c;
+  u16_t mss;
+  u8_t *opts, opt;
+#if LWIP_TCP_TIMESTAMPS
+  u32_t tsval;
+#endif
+
+  opts = (u8_t *)tcphdr + TCP_HLEN;
+
+  /* Parse the TCP MSS option, if present. */
+  if(TCPH_HDRLEN(tcphdr) > 0x5) {
+    max_c = (TCPH_HDRLEN(tcphdr) - 5) << 2;
+    for (c = 0; c < max_c; ) {
+      opt = opts[c];
+      switch (opt) {
+      case 0x00:
+        /* End of options. */
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: EOL\n"));
+        return;
+      case 0x01:
+        /* NOP option. */
+        ++c;
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: NOP\n"));
+        break;
+      case 0x02:
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: MSS\n"));
+        if (opts[c + 1] != 0x04 || c + 0x04 > max_c) {
+          /* Bad length */
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n"));
+          return;
+        }
+        /* An MSS option with the right option length. */
+        mss = (opts[c + 2] << 8) | opts[c + 3];
+        /* Limit the mss to the configured TCP_MSS and prevent division by zero */
+        pcb->mss = ((mss > TCP_MSS) || (mss == 0)) ? TCP_MSS : mss;
+        /* Advance to next option */
+        c += 0x04;
+        break;
+#if LWIP_TCP_TIMESTAMPS
+      case 0x08:
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: TS\n"));
+        if (opts[c + 1] != 0x0A || c + 0x0A > max_c) {
+          /* Bad length */
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n"));
+          return;
+        }
+        /* TCP timestamp option with valid length */
+        tsval = (opts[c+2]) | (opts[c+3] << 8) | 
+          (opts[c+4] << 16) | (opts[c+5] << 24);
+        if (flags & TCP_SYN) {
+          pcb->ts_recent = ntohl(tsval);
+          pcb->flags |= TF_TIMESTAMP;
+        } else if (TCP_SEQ_BETWEEN(pcb->ts_lastacksent, seqno, seqno+tcplen)) {
+          pcb->ts_recent = ntohl(tsval);
+        }
+        /* Advance to next option */
+        c += 0x0A;
+        break;
+#endif
+      default:
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: other\n"));
+        if (opts[c + 1] == 0) {
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n"));
+          /* If the length field is zero, the options are malformed
+             and we don't process them further. */
+          return;
+        }
+        /* All other options have a length field, so that we easily
+           can skip past them. */
+        c += opts[c + 1];
+      }
+    }
+  }
+}
+
+#endif /* LWIP_TCP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/tcp_out.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/tcp_out.c
new file mode 100644
index 0000000..1b8308d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/tcp_out.c
@@ -0,0 +1,1468 @@
+/**
+ * @file
+ * Transmission Control Protocol, outgoing traffic
+ *
+ * The output functions of TCP.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/tcp_impl.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/sys.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+
+#include 
+
+/* Define some copy-macros for checksum-on-copy so that the code looks
+   nicer by preventing too many ifdef's. */
+#if TCP_CHECKSUM_ON_COPY
+#define TCP_DATA_COPY(dst, src, len, seg) do { \
+  tcp_seg_add_chksum(LWIP_CHKSUM_COPY(dst, src, len), \
+                     len, &seg->chksum, &seg->chksum_swapped); \
+  seg->flags |= TF_SEG_DATA_CHECKSUMMED; } while(0)
+#define TCP_DATA_COPY2(dst, src, len, chksum, chksum_swapped)  \
+  tcp_seg_add_chksum(LWIP_CHKSUM_COPY(dst, src, len), len, chksum, chksum_swapped);
+#else /* TCP_CHECKSUM_ON_COPY*/
+#define TCP_DATA_COPY(dst, src, len, seg)                     MEMCPY(dst, src, len)
+#define TCP_DATA_COPY2(dst, src, len, chksum, chksum_swapped) MEMCPY(dst, src, len)
+#endif /* TCP_CHECKSUM_ON_COPY*/
+
+/** Define this to 1 for an extra check that the output checksum is valid
+ * (usefule when the checksum is generated by the application, not the stack) */
+#ifndef TCP_CHECKSUM_ON_COPY_SANITY_CHECK
+#define TCP_CHECKSUM_ON_COPY_SANITY_CHECK   0
+#endif
+
+/* Forward declarations.*/
+static void tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb);
+
+/** Allocate a pbuf and create a tcphdr at p->payload, used for output
+ * functions other than the default tcp_output -> tcp_output_segment
+ * (e.g. tcp_send_empty_ack, etc.)
+ *
+ * @param pcb tcp pcb for which to send a packet (used to initialize tcp_hdr)
+ * @param optlen length of header-options
+ * @param datalen length of tcp data to reserve in pbuf
+ * @param seqno_be seqno in network byte order (big-endian)
+ * @return pbuf with p->payload being the tcp_hdr
+ */
+static struct pbuf *
+tcp_output_alloc_header(struct tcp_pcb *pcb, u16_t optlen, u16_t datalen,
+                      u32_t seqno_be /* already in network byte order */)
+{
+  struct tcp_hdr *tcphdr;
+  struct pbuf *p = pbuf_alloc(PBUF_IP, TCP_HLEN + optlen + datalen, PBUF_RAM);
+  if (p != NULL) {
+    LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr",
+                 (p->len >= TCP_HLEN + optlen));
+    tcphdr = (struct tcp_hdr *)p->payload;
+    tcphdr->src = htons(pcb->local_port);
+    tcphdr->dest = htons(pcb->remote_port);
+    tcphdr->seqno = seqno_be;
+    tcphdr->ackno = htonl(pcb->rcv_nxt);
+    TCPH_HDRLEN_FLAGS_SET(tcphdr, (5 + optlen / 4), TCP_ACK);
+    tcphdr->wnd = htons(pcb->rcv_ann_wnd);
+    tcphdr->chksum = 0;
+    tcphdr->urgp = 0;
+
+    /* If we're sending a packet, update the announced right window edge */
+    pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd;
+  }
+  return p;
+}
+
+/**
+ * Called by tcp_close() to send a segment including FIN flag but not data.
+ *
+ * @param pcb the tcp_pcb over which to send a segment
+ * @return ERR_OK if sent, another err_t otherwise
+ */
+err_t
+tcp_send_fin(struct tcp_pcb *pcb)
+{
+  /* first, try to add the fin to the last unsent segment */
+  if (pcb->unsent != NULL) {
+    struct tcp_seg *last_unsent;
+    for (last_unsent = pcb->unsent; last_unsent->next != NULL;
+         last_unsent = last_unsent->next);
+
+    if ((TCPH_FLAGS(last_unsent->tcphdr) & (TCP_SYN | TCP_FIN | TCP_RST)) == 0) {
+      /* no SYN/FIN/RST flag in the header, we can add the FIN flag */
+      TCPH_SET_FLAG(last_unsent->tcphdr, TCP_FIN);
+      return ERR_OK;
+    }
+  }
+  /* no data, no length, flags, copy=1, no optdata */
+  return tcp_enqueue_flags(pcb, TCP_FIN);
+}
+
+/**
+ * Create a TCP segment with prefilled header.
+ *
+ * Called by tcp_write and tcp_enqueue_flags.
+ *
+ * @param pcb Protocol control block for the TCP connection.
+ * @param p pbuf that is used to hold the TCP header.
+ * @param flags TCP flags for header.
+ * @param seqno TCP sequence number of this packet
+ * @param optflags options to include in TCP header
+ * @return a new tcp_seg pointing to p, or NULL.
+ * The TCP header is filled in except ackno and wnd.
+ * p is freed on failure.
+ */
+static struct tcp_seg *
+tcp_create_segment(struct tcp_pcb *pcb, struct pbuf *p, u8_t flags, u32_t seqno, u8_t optflags)
+{
+  struct tcp_seg *seg;
+  u8_t optlen = LWIP_TCP_OPT_LENGTH(optflags);
+
+  if ((seg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG)) == NULL) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_create_segment: no memory.\n"));
+    pbuf_free(p);
+    return NULL;
+  }
+  seg->flags = optflags;
+  seg->next = NULL;
+  seg->p = p;
+  seg->len = p->tot_len - optlen;
+#if TCP_OVERSIZE_DBGCHECK
+  seg->oversize_left = 0;
+#endif /* TCP_OVERSIZE_DBGCHECK */
+#if TCP_CHECKSUM_ON_COPY
+  seg->chksum = 0;
+  seg->chksum_swapped = 0;
+  /* check optflags */
+  LWIP_ASSERT("invalid optflags passed: TF_SEG_DATA_CHECKSUMMED",
+              (optflags & TF_SEG_DATA_CHECKSUMMED) == 0);
+#endif /* TCP_CHECKSUM_ON_COPY */
+
+  /* build TCP header */
+  if (pbuf_header(p, TCP_HLEN)) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_create_segment: no room for TCP header in pbuf.\n"));
+    TCP_STATS_INC(tcp.err);
+    tcp_seg_free(seg);
+    return NULL;
+  }
+  seg->tcphdr = (struct tcp_hdr *)seg->p->payload;
+  seg->tcphdr->src = htons(pcb->local_port);
+  seg->tcphdr->dest = htons(pcb->remote_port);
+  seg->tcphdr->seqno = htonl(seqno);
+  /* ackno is set in tcp_output */
+  TCPH_HDRLEN_FLAGS_SET(seg->tcphdr, (5 + optlen / 4), flags);
+  /* wnd and chksum are set in tcp_output */
+  seg->tcphdr->urgp = 0;
+  return seg;
+} 
+
+/**
+ * Allocate a PBUF_RAM pbuf, perhaps with extra space at the end.
+ *
+ * This function is like pbuf_alloc(layer, length, PBUF_RAM) except
+ * there may be extra bytes available at the end.
+ *
+ * @param layer flag to define header size.
+ * @param length size of the pbuf's payload.
+ * @param max_length maximum usable size of payload+oversize.
+ * @param oversize pointer to a u16_t that will receive the number of usable tail bytes.
+ * @param pcb The TCP connection that willo enqueue the pbuf.
+ * @param apiflags API flags given to tcp_write.
+ * @param first_seg true when this pbuf will be used in the first enqueued segment.
+ * @param 
+ */
+#if TCP_OVERSIZE
+static struct pbuf *
+tcp_pbuf_prealloc(pbuf_layer layer, u16_t length, u16_t max_length,
+                  u16_t *oversize, struct tcp_pcb *pcb, u8_t apiflags,
+                  u8_t first_seg)
+{
+  struct pbuf *p;
+  u16_t alloc = length;
+
+#if LWIP_NETIF_TX_SINGLE_PBUF
+  LWIP_UNUSED_ARG(max_length);
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_UNUSED_ARG(apiflags);
+  LWIP_UNUSED_ARG(first_seg);
+  /* always create MSS-sized pbufs */
+  alloc = TCP_MSS;
+#else /* LWIP_NETIF_TX_SINGLE_PBUF */
+  if (length < max_length) {
+    /* Should we allocate an oversized pbuf, or just the minimum
+     * length required? If tcp_write is going to be called again
+     * before this segment is transmitted, we want the oversized
+     * buffer. If the segment will be transmitted immediately, we can
+     * save memory by allocating only length. We use a simple
+     * heuristic based on the following information:
+     *
+     * Did the user set TCP_WRITE_FLAG_MORE?
+     *
+     * Will the Nagle algorithm defer transmission of this segment?
+     */
+    if ((apiflags & TCP_WRITE_FLAG_MORE) ||
+        (!(pcb->flags & TF_NODELAY) &&
+         (!first_seg ||
+          pcb->unsent != NULL ||
+          pcb->unacked != NULL))) {
+      alloc = LWIP_MIN(max_length, LWIP_MEM_ALIGN_SIZE(length + TCP_OVERSIZE));
+    }
+  }
+#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
+  p = pbuf_alloc(layer, alloc, PBUF_RAM);
+  if (p == NULL) {
+    return NULL;
+  }
+  LWIP_ASSERT("need unchained pbuf", p->next == NULL);
+  *oversize = p->len - length;
+  /* trim p->len to the currently used size */
+  p->len = p->tot_len = length;
+  return p;
+}
+#else /* TCP_OVERSIZE */
+#define tcp_pbuf_prealloc(layer, length, mx, os, pcb, api, fst) pbuf_alloc((layer), (length), PBUF_RAM)
+#endif /* TCP_OVERSIZE */
+
+#if TCP_CHECKSUM_ON_COPY
+/** Add a checksum of newly added data to the segment */
+static void
+tcp_seg_add_chksum(u16_t chksum, u16_t len, u16_t *seg_chksum,
+                   u8_t *seg_chksum_swapped)
+{
+  u32_t helper;
+  /* add chksum to old chksum and fold to u16_t */
+  helper = chksum + *seg_chksum;
+  chksum = FOLD_U32T(helper);
+  if ((len & 1) != 0) {
+    *seg_chksum_swapped = 1 - *seg_chksum_swapped;
+    chksum = SWAP_BYTES_IN_WORD(chksum);
+  }
+  *seg_chksum = chksum;
+}
+#endif /* TCP_CHECKSUM_ON_COPY */
+
+/** Checks if tcp_write is allowed or not (checks state, snd_buf and snd_queuelen).
+ *
+ * @param pcb the tcp pcb to check for
+ * @param len length of data to send (checked agains snd_buf)
+ * @return ERR_OK if tcp_write is allowed to proceed, another err_t otherwise
+ */
+static err_t
+tcp_write_checks(struct tcp_pcb *pcb, u16_t len)
+{
+  /* connection is in invalid state for data transmission? */
+  if ((pcb->state != ESTABLISHED) &&
+      (pcb->state != CLOSE_WAIT) &&
+      (pcb->state != SYN_SENT) &&
+      (pcb->state != SYN_RCVD)) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_STATE | LWIP_DBG_LEVEL_SEVERE, ("tcp_write() called in invalid state\n"));
+    return ERR_CONN;
+  } else if (len == 0) {
+    return ERR_OK;
+  }
+
+  /* fail on too much data */
+  if (len > pcb->snd_buf) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_write: too much data (len=%"U16_F" > snd_buf=%"U16_F")\n",
+      len, pcb->snd_buf));
+    pcb->flags |= TF_NAGLEMEMERR;
+    return ERR_MEM;
+  }
+
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_write: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen));
+
+  /* If total number of pbufs on the unsent/unacked queues exceeds the
+   * configured maximum, return an error */
+  /* check for configured max queuelen and possible overflow */
+  if ((pcb->snd_queuelen >= TCP_SND_QUEUELEN) || (pcb->snd_queuelen > TCP_SNDQUEUELEN_OVERFLOW)) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_write: too long queue %"U16_F" (max %"U16_F")\n",
+      pcb->snd_queuelen, TCP_SND_QUEUELEN));
+    TCP_STATS_INC(tcp.memerr);
+    pcb->flags |= TF_NAGLEMEMERR;
+    return ERR_MEM;
+  }
+  if (pcb->snd_queuelen != 0) {
+    LWIP_ASSERT("tcp_write: pbufs on queue => at least one queue non-empty",
+      pcb->unacked != NULL || pcb->unsent != NULL);
+  } else {
+    LWIP_ASSERT("tcp_write: no pbufs on queue => both queues empty",
+      pcb->unacked == NULL && pcb->unsent == NULL);
+  }
+  return ERR_OK;
+}
+
+/**
+ * Write data for sending (but does not send it immediately).
+ *
+ * It waits in the expectation of more data being sent soon (as
+ * it can send them more efficiently by combining them together).
+ * To prompt the system to send data now, call tcp_output() after
+ * calling tcp_write().
+ *
+ * @param pcb Protocol control block for the TCP connection to enqueue data for.
+ * @param arg Pointer to the data to be enqueued for sending.
+ * @param len Data length in bytes
+ * @param apiflags combination of following flags :
+ * - TCP_WRITE_FLAG_COPY (0x01) data will be copied into memory belonging to the stack
+ * - TCP_WRITE_FLAG_MORE (0x02) for TCP connection, PSH flag will be set on last segment sent,
+ * @return ERR_OK if enqueued, another err_t on error
+ */
+err_t
+tcp_write(struct tcp_pcb *pcb, const void *arg, u16_t len, u8_t apiflags)
+{
+  struct pbuf *concat_p = NULL;
+  struct tcp_seg *last_unsent = NULL, *seg = NULL, *prev_seg = NULL, *queue = NULL;
+  u16_t pos = 0; /* position in 'arg' data */
+  u16_t queuelen;
+  u8_t optlen = 0;
+  u8_t optflags = 0;
+#if TCP_OVERSIZE
+  u16_t oversize = 0;
+  u16_t oversize_used = 0;
+#endif /* TCP_OVERSIZE */
+#if TCP_CHECKSUM_ON_COPY
+  u16_t concat_chksum = 0;
+  u8_t concat_chksum_swapped = 0;
+  u16_t concat_chksummed = 0;
+#endif /* TCP_CHECKSUM_ON_COPY */
+  err_t err;
+
+#if LWIP_NETIF_TX_SINGLE_PBUF
+  /* Always copy to try to create single pbufs for TX */
+  apiflags |= TCP_WRITE_FLAG_COPY;
+#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
+
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, data=%p, len=%"U16_F", apiflags=%"U16_F")\n",
+    (void *)pcb, arg, len, (u16_t)apiflags));
+  LWIP_ERROR("tcp_write: arg == NULL (programmer violates API)", 
+             arg != NULL, return ERR_ARG;);
+
+  err = tcp_write_checks(pcb, len);
+  if (err != ERR_OK) {
+    return err;
+  }
+  queuelen = pcb->snd_queuelen;
+
+#if LWIP_TCP_TIMESTAMPS
+  if ((pcb->flags & TF_TIMESTAMP)) {
+    optflags = TF_SEG_OPTS_TS;
+    optlen = LWIP_TCP_OPT_LENGTH(TF_SEG_OPTS_TS);
+  }
+#endif /* LWIP_TCP_TIMESTAMPS */
+
+
+  /*
+   * TCP segmentation is done in three phases with increasing complexity:
+   *
+   * 1. Copy data directly into an oversized pbuf.
+   * 2. Chain a new pbuf to the end of pcb->unsent.
+   * 3. Create new segments.
+   *
+   * We may run out of memory at any point. In that case we must
+   * return ERR_MEM and not change anything in pcb. Therefore, all
+   * changes are recorded in local variables and committed at the end
+   * of the function. Some pcb fields are maintained in local copies:
+   *
+   * queuelen = pcb->snd_queuelen
+   * oversize = pcb->unsent_oversize
+   *
+   * These variables are set consistently by the phases:
+   *
+   * seg points to the last segment tampered with.
+   *
+   * pos records progress as data is segmented.
+   */
+
+  /* Find the tail of the unsent queue. */
+  if (pcb->unsent != NULL) {
+    u16_t space;
+    u16_t unsent_optlen;
+
+    /* @todo: this could be sped up by keeping last_unsent in the pcb */
+    for (last_unsent = pcb->unsent; last_unsent->next != NULL;
+         last_unsent = last_unsent->next);
+
+    /* Usable space at the end of the last unsent segment */
+    unsent_optlen = LWIP_TCP_OPT_LENGTH(last_unsent->flags);
+    space = pcb->mss - (last_unsent->len + unsent_optlen);
+
+    /*
+     * Phase 1: Copy data directly into an oversized pbuf.
+     *
+     * The number of bytes copied is recorded in the oversize_used
+     * variable. The actual copying is done at the bottom of the
+     * function.
+     */
+#if TCP_OVERSIZE
+#if TCP_OVERSIZE_DBGCHECK
+    /* check that pcb->unsent_oversize matches last_unsent->unsent_oversize */
+    LWIP_ASSERT("unsent_oversize mismatch (pcb vs. last_unsent)",
+                pcb->unsent_oversize == last_unsent->oversize_left);
+#endif /* TCP_OVERSIZE_DBGCHECK */
+    oversize = pcb->unsent_oversize;
+    if (oversize > 0) {
+      LWIP_ASSERT("inconsistent oversize vs. space", oversize_used <= space);
+      seg = last_unsent;
+      oversize_used = oversize < len ? oversize : len;
+      pos += oversize_used;
+      oversize -= oversize_used;
+      space -= oversize_used;
+    }
+    /* now we are either finished or oversize is zero */
+    LWIP_ASSERT("inconsistend oversize vs. len", (oversize == 0) || (pos == len));
+#endif /* TCP_OVERSIZE */
+
+    /*
+     * Phase 2: Chain a new pbuf to the end of pcb->unsent.
+     *
+     * We don't extend segments containing SYN/FIN flags or options
+     * (len==0). The new pbuf is kept in concat_p and pbuf_cat'ed at
+     * the end.
+     */
+    if ((pos < len) && (space > 0) && (last_unsent->len > 0)) {
+      u16_t seglen = space < len - pos ? space : len - pos;
+      seg = last_unsent;
+
+      /* Create a pbuf with a copy or reference to seglen bytes. We
+       * can use PBUF_RAW here since the data appears in the middle of
+       * a segment. A header will never be prepended. */
+      if (apiflags & TCP_WRITE_FLAG_COPY) {
+        /* Data is copied */
+        if ((concat_p = tcp_pbuf_prealloc(PBUF_RAW, seglen, space, &oversize, pcb, apiflags, 1)) == NULL) {
+          LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2,
+                      ("tcp_write : could not allocate memory for pbuf copy size %"U16_F"\n",
+                       seglen));
+          goto memerr;
+        }
+#if TCP_OVERSIZE_DBGCHECK
+        last_unsent->oversize_left = oversize;
+#endif /* TCP_OVERSIZE_DBGCHECK */
+        TCP_DATA_COPY2(concat_p->payload, (u8_t*)arg + pos, seglen, &concat_chksum, &concat_chksum_swapped);
+#if TCP_CHECKSUM_ON_COPY
+        concat_chksummed += seglen;
+#endif /* TCP_CHECKSUM_ON_COPY */
+      } else {
+        /* Data is not copied */
+        if ((concat_p = pbuf_alloc(PBUF_RAW, seglen, PBUF_ROM)) == NULL) {
+          LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2,
+                      ("tcp_write: could not allocate memory for zero-copy pbuf\n"));
+          goto memerr;
+        }
+#if TCP_CHECKSUM_ON_COPY
+        /* calculate the checksum of nocopy-data */
+        tcp_seg_add_chksum(~inet_chksum((u8_t*)arg + pos, seglen), seglen,
+          &concat_chksum, &concat_chksum_swapped);
+        concat_chksummed += seglen;
+#endif /* TCP_CHECKSUM_ON_COPY */
+        /* reference the non-volatile payload data */
+        concat_p->payload = (u8_t*)arg + pos;
+      }
+
+      pos += seglen;
+      queuelen += pbuf_clen(concat_p);
+    }
+  } else {
+#if TCP_OVERSIZE
+    LWIP_ASSERT("unsent_oversize mismatch (pcb->unsent is NULL)",
+                pcb->unsent_oversize == 0);
+#endif /* TCP_OVERSIZE */
+  }
+
+  /*
+   * Phase 3: Create new segments.
+   *
+   * The new segments are chained together in the local 'queue'
+   * variable, ready to be appended to pcb->unsent.
+   */
+  while (pos < len) {
+    struct pbuf *p;
+    u16_t left = len - pos;
+    u16_t max_len = pcb->mss - optlen;
+    u16_t seglen = left > max_len ? max_len : left;
+#if TCP_CHECKSUM_ON_COPY
+    u16_t chksum = 0;
+    u8_t chksum_swapped = 0;
+#endif /* TCP_CHECKSUM_ON_COPY */
+
+    if (apiflags & TCP_WRITE_FLAG_COPY) {
+      /* If copy is set, memory should be allocated and data copied
+       * into pbuf */
+      if ((p = tcp_pbuf_prealloc(PBUF_TRANSPORT, seglen + optlen, pcb->mss, &oversize, pcb, apiflags, queue == NULL)) == NULL) {
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_write : could not allocate memory for pbuf copy size %"U16_F"\n", seglen));
+        goto memerr;
+      }
+      LWIP_ASSERT("tcp_write: check that first pbuf can hold the complete seglen",
+                  (p->len >= seglen));
+      TCP_DATA_COPY2((char *)p->payload + optlen, (u8_t*)arg + pos, seglen, &chksum, &chksum_swapped);
+    } else {
+      /* Copy is not set: First allocate a pbuf for holding the data.
+       * Since the referenced data is available at least until it is
+       * sent out on the link (as it has to be ACKed by the remote
+       * party) we can safely use PBUF_ROM instead of PBUF_REF here.
+       */
+      struct pbuf *p2;
+#if TCP_OVERSIZE
+      LWIP_ASSERT("oversize == 0", oversize == 0);
+#endif /* TCP_OVERSIZE */
+      if ((p2 = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_ROM)) == NULL) {
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_write: could not allocate memory for zero-copy pbuf\n"));
+        goto memerr;
+      }
+#if TCP_CHECKSUM_ON_COPY
+      /* calculate the checksum of nocopy-data */
+      chksum = ~inet_chksum((u8_t*)arg + pos, seglen);
+#endif /* TCP_CHECKSUM_ON_COPY */
+      /* reference the non-volatile payload data */
+      p2->payload = (u8_t*)arg + pos;
+
+      /* Second, allocate a pbuf for the headers. */
+      if ((p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) {
+        /* If allocation fails, we have to deallocate the data pbuf as
+         * well. */
+        pbuf_free(p2);
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_write: could not allocate memory for header pbuf\n"));
+        goto memerr;
+      }
+      /* Concatenate the headers and data pbufs together. */
+      pbuf_cat(p/*header*/, p2/*data*/);
+    }
+
+    queuelen += pbuf_clen(p);
+
+    /* Now that there are more segments queued, we check again if the
+     * length of the queue exceeds the configured maximum or
+     * overflows. */
+    if ((queuelen > TCP_SND_QUEUELEN) || (queuelen > TCP_SNDQUEUELEN_OVERFLOW)) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_write: queue too long %"U16_F" (%"U16_F")\n", queuelen, TCP_SND_QUEUELEN));
+      pbuf_free(p);
+      goto memerr;
+    }
+
+    if ((seg = tcp_create_segment(pcb, p, 0, pcb->snd_lbb + pos, optflags)) == NULL) {
+      goto memerr;
+    }
+#if TCP_OVERSIZE_DBGCHECK
+    seg->oversize_left = oversize;
+#endif /* TCP_OVERSIZE_DBGCHECK */
+#if TCP_CHECKSUM_ON_COPY
+    seg->chksum = chksum;
+    seg->chksum_swapped = chksum_swapped;
+    seg->flags |= TF_SEG_DATA_CHECKSUMMED;
+#endif /* TCP_CHECKSUM_ON_COPY */
+
+    /* first segment of to-be-queued data? */
+    if (queue == NULL) {
+      queue = seg;
+    } else {
+      /* Attach the segment to the end of the queued segments */
+      LWIP_ASSERT("prev_seg != NULL", prev_seg != NULL);
+      prev_seg->next = seg;
+    }
+    /* remember last segment of to-be-queued data for next iteration */
+    prev_seg = seg;
+
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_TRACE, ("tcp_write: queueing %"U32_F":%"U32_F"\n",
+      ntohl(seg->tcphdr->seqno),
+      ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg)));
+
+    pos += seglen;
+  }
+
+  /*
+   * All three segmentation phases were successful. We can commit the
+   * transaction.
+   */
+
+  /*
+   * Phase 1: If data has been added to the preallocated tail of
+   * last_unsent, we update the length fields of the pbuf chain.
+   */
+#if TCP_OVERSIZE
+  if (oversize_used > 0) {
+    struct pbuf *p;
+    /* Bump tot_len of whole chain, len of tail */
+    for (p = last_unsent->p; p; p = p->next) {
+      p->tot_len += oversize_used;
+      if (p->next == NULL) {
+        TCP_DATA_COPY((char *)p->payload + p->len, arg, oversize_used, last_unsent);
+        p->len += oversize_used;
+      }
+    }
+    last_unsent->len += oversize_used;
+#if TCP_OVERSIZE_DBGCHECK
+    last_unsent->oversize_left -= oversize_used;
+#endif /* TCP_OVERSIZE_DBGCHECK */
+  }
+  pcb->unsent_oversize = oversize;
+#endif /* TCP_OVERSIZE */
+
+  /*
+   * Phase 2: concat_p can be concatenated onto last_unsent->p
+   */
+  if (concat_p != NULL) {
+    LWIP_ASSERT("tcp_write: cannot concatenate when pcb->unsent is empty",
+      (last_unsent != NULL));
+    pbuf_cat(last_unsent->p, concat_p);
+    last_unsent->len += concat_p->tot_len;
+#if TCP_CHECKSUM_ON_COPY
+    if (concat_chksummed) {
+      tcp_seg_add_chksum(concat_chksum, concat_chksummed, &last_unsent->chksum,
+        &last_unsent->chksum_swapped);
+      last_unsent->flags |= TF_SEG_DATA_CHECKSUMMED;
+    }
+#endif /* TCP_CHECKSUM_ON_COPY */
+  }
+
+  /*
+   * Phase 3: Append queue to pcb->unsent. Queue may be NULL, but that
+   * is harmless
+   */
+  if (last_unsent == NULL) {
+    pcb->unsent = queue;
+  } else {
+    last_unsent->next = queue;
+  }
+
+  /*
+   * Finally update the pcb state.
+   */
+  pcb->snd_lbb += len;
+  pcb->snd_buf -= len;
+  pcb->snd_queuelen = queuelen;
+
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_write: %"S16_F" (after enqueued)\n",
+    pcb->snd_queuelen));
+  if (pcb->snd_queuelen != 0) {
+    LWIP_ASSERT("tcp_write: valid queue length",
+                pcb->unacked != NULL || pcb->unsent != NULL);
+  }
+
+  /* Set the PSH flag in the last segment that we enqueued. */
+  if (seg != NULL && seg->tcphdr != NULL && ((apiflags & TCP_WRITE_FLAG_MORE)==0)) {
+    TCPH_SET_FLAG(seg->tcphdr, TCP_PSH);
+  }
+
+  return ERR_OK;
+memerr:
+  pcb->flags |= TF_NAGLEMEMERR;
+  TCP_STATS_INC(tcp.memerr);
+
+  if (concat_p != NULL) {
+    pbuf_free(concat_p);
+  }
+  if (queue != NULL) {
+    tcp_segs_free(queue);
+  }
+  if (pcb->snd_queuelen != 0) {
+    LWIP_ASSERT("tcp_write: valid queue length", pcb->unacked != NULL ||
+      pcb->unsent != NULL);
+  }
+  LWIP_DEBUGF(TCP_QLEN_DEBUG | LWIP_DBG_STATE, ("tcp_write: %"S16_F" (with mem err)\n", pcb->snd_queuelen));
+  return ERR_MEM;
+}
+
+/**
+ * Enqueue TCP options for transmission.
+ *
+ * Called by tcp_connect(), tcp_listen_input(), and tcp_send_ctrl().
+ *
+ * @param pcb Protocol control block for the TCP connection.
+ * @param flags TCP header flags to set in the outgoing segment.
+ * @param optdata pointer to TCP options, or NULL.
+ * @param optlen length of TCP options in bytes.
+ */
+err_t
+tcp_enqueue_flags(struct tcp_pcb *pcb, u8_t flags)
+{
+  struct pbuf *p;
+  struct tcp_seg *seg;
+  u8_t optflags = 0;
+  u8_t optlen = 0;
+
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen));
+
+  LWIP_ASSERT("tcp_enqueue_flags: need either TCP_SYN or TCP_FIN in flags (programmer violates API)",
+              (flags & (TCP_SYN | TCP_FIN)) != 0);
+
+  /* check for configured max queuelen and possible overflow */
+  if ((pcb->snd_queuelen >= TCP_SND_QUEUELEN) || (pcb->snd_queuelen > TCP_SNDQUEUELEN_OVERFLOW)) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue_flags: too long queue %"U16_F" (max %"U16_F")\n",
+                                       pcb->snd_queuelen, TCP_SND_QUEUELEN));
+    TCP_STATS_INC(tcp.memerr);
+    pcb->flags |= TF_NAGLEMEMERR;
+    return ERR_MEM;
+  }
+
+  if (flags & TCP_SYN) {
+    optflags = TF_SEG_OPTS_MSS;
+  }
+#if LWIP_TCP_TIMESTAMPS
+  if ((pcb->flags & TF_TIMESTAMP)) {
+    optflags |= TF_SEG_OPTS_TS;
+  }
+#endif /* LWIP_TCP_TIMESTAMPS */
+  optlen = LWIP_TCP_OPT_LENGTH(optflags);
+
+  /* tcp_enqueue_flags is always called with either SYN or FIN in flags.
+   * We need one available snd_buf byte to do that.
+   * This means we can't send FIN while snd_buf==0. A better fix would be to
+   * not include SYN and FIN sequence numbers in the snd_buf count. */
+  if (pcb->snd_buf == 0) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue_flags: no send buffer available\n"));
+    TCP_STATS_INC(tcp.memerr);
+    return ERR_MEM;
+  }
+
+  /* Allocate pbuf with room for TCP header + options */
+  if ((p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) {
+    pcb->flags |= TF_NAGLEMEMERR;
+    TCP_STATS_INC(tcp.memerr);
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("tcp_enqueue_flags: check that first pbuf can hold optlen",
+              (p->len >= optlen));
+
+  /* Allocate memory for tcp_seg, and fill in fields. */
+  if ((seg = tcp_create_segment(pcb, p, flags, pcb->snd_lbb, optflags)) == NULL) {
+    pcb->flags |= TF_NAGLEMEMERR;
+    TCP_STATS_INC(tcp.memerr);
+    return ERR_MEM;
+  }
+//_RB_ Triggers with MEM_ALIGNMENT is 64  LWIP_ASSERT("seg->tcphdr not aligned", ((mem_ptr_t)seg->tcphdr % MEM_ALIGNMENT) == 0);
+  LWIP_ASSERT("tcp_enqueue_flags: invalid segment length", seg->len == 0);
+
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_TRACE,
+              ("tcp_enqueue_flags: queueing %"U32_F":%"U32_F" (0x%"X16_F")\n",
+               ntohl(seg->tcphdr->seqno),
+               ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg),
+               (u16_t)flags));
+
+  /* Now append seg to pcb->unsent queue */
+  if (pcb->unsent == NULL) {
+    pcb->unsent = seg;
+  } else {
+    struct tcp_seg *useg;
+    for (useg = pcb->unsent; useg->next != NULL; useg = useg->next);
+    useg->next = seg;
+  }
+#if TCP_OVERSIZE
+  /* The new unsent tail has no space */
+  pcb->unsent_oversize = 0;
+#endif /* TCP_OVERSIZE */
+
+  /* SYN and FIN bump the sequence number */
+  if ((flags & TCP_SYN) || (flags & TCP_FIN)) {
+    pcb->snd_lbb++;
+    /* optlen does not influence snd_buf */
+    pcb->snd_buf--;
+  }
+  if (flags & TCP_FIN) {
+    pcb->flags |= TF_FIN;
+  }
+
+  /* update number of segments on the queues */
+  pcb->snd_queuelen += pbuf_clen(seg->p);
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: %"S16_F" (after enqueued)\n", pcb->snd_queuelen));
+  if (pcb->snd_queuelen != 0) {
+    LWIP_ASSERT("tcp_enqueue_flags: invalid queue length",
+      pcb->unacked != NULL || pcb->unsent != NULL);
+  }
+
+  return ERR_OK;
+}
+ 
+
+#if LWIP_TCP_TIMESTAMPS
+/* Build a timestamp option (12 bytes long) at the specified options pointer)
+ *
+ * @param pcb tcp_pcb
+ * @param opts option pointer where to store the timestamp option
+ */
+static void
+tcp_build_timestamp_option(struct tcp_pcb *pcb, u32_t *opts)
+{
+  /* Pad with two NOP options to make everything nicely aligned */
+  opts[0] = PP_HTONL(0x0101080A);
+  opts[1] = htonl(sys_now());
+  opts[2] = htonl(pcb->ts_recent);
+}
+#endif
+
+/** Send an ACK without data.
+ *
+ * @param pcb Protocol control block for the TCP connection to send the ACK
+ */
+err_t
+tcp_send_empty_ack(struct tcp_pcb *pcb)
+{
+  struct pbuf *p;
+  struct tcp_hdr *tcphdr;
+  u8_t optlen = 0;
+
+#if LWIP_TCP_TIMESTAMPS
+  if (pcb->flags & TF_TIMESTAMP) {
+    optlen = LWIP_TCP_OPT_LENGTH(TF_SEG_OPTS_TS);
+  }
+#endif
+
+  p = tcp_output_alloc_header(pcb, optlen, 0, htonl(pcb->snd_nxt));
+  if (p == NULL) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n"));
+    return ERR_BUF;
+  }
+  tcphdr = (struct tcp_hdr *)p->payload;
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, 
+              ("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt));
+  /* remove ACK flags from the PCB, as we send an empty ACK now */
+  pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
+
+  /* NB. MSS option is only sent on SYNs, so ignore it here */
+#if LWIP_TCP_TIMESTAMPS
+  pcb->ts_lastacksent = pcb->rcv_nxt;
+
+  if (pcb->flags & TF_TIMESTAMP) {
+    tcp_build_timestamp_option(pcb, (u32_t *)(tcphdr + 1));
+  }
+#endif 
+
+#if CHECKSUM_GEN_TCP
+  tcphdr->chksum = inet_chksum_pseudo(p, &(pcb->local_ip), &(pcb->remote_ip),
+        IP_PROTO_TCP, p->tot_len);
+#endif
+#if LWIP_NETIF_HWADDRHINT
+  ip_output_hinted(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,
+      IP_PROTO_TCP, &(pcb->addr_hint));
+#else /* LWIP_NETIF_HWADDRHINT*/
+  ip_output(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,
+      IP_PROTO_TCP);
+#endif /* LWIP_NETIF_HWADDRHINT*/
+  pbuf_free(p);
+
+  return ERR_OK;
+}
+
+/**
+ * Find out what we can send and send it
+ *
+ * @param pcb Protocol control block for the TCP connection to send data
+ * @return ERR_OK if data has been sent or nothing to send
+ *         another err_t on error
+ */
+err_t
+tcp_output(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *seg, *useg;
+  u32_t wnd, snd_nxt;
+#if TCP_CWND_DEBUG
+  s16_t i = 0;
+#endif /* TCP_CWND_DEBUG */
+
+  /* First, check if we are invoked by the TCP input processing
+     code. If so, we do not output anything. Instead, we rely on the
+     input processing code to call us when input processing is done
+     with. */
+  if (tcp_input_pcb == pcb) {
+    return ERR_OK;
+  }
+
+  wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd);
+
+  seg = pcb->unsent;
+
+  /* If the TF_ACK_NOW flag is set and no data will be sent (either
+   * because the ->unsent queue is empty or because the window does
+   * not allow it), construct an empty ACK segment and send it.
+   *
+   * If data is to be sent, we will just piggyback the ACK (see below).
+   */
+  if (pcb->flags & TF_ACK_NOW &&
+     (seg == NULL ||
+      ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd)) {
+     return tcp_send_empty_ack(pcb);
+  }
+
+  /* useg should point to last segment on unacked queue */
+  useg = pcb->unacked;
+  if (useg != NULL) {
+    for (; useg->next != NULL; useg = useg->next);
+  }
+
+#if TCP_OUTPUT_DEBUG
+  if (seg == NULL) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: nothing to send (%p)\n",
+                                   (void*)pcb->unsent));
+  }
+#endif /* TCP_OUTPUT_DEBUG */
+#if TCP_CWND_DEBUG
+  if (seg == NULL) {
+    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U16_F
+                                 ", cwnd %"U16_F", wnd %"U32_F
+                                 ", seg == NULL, ack %"U32_F"\n",
+                                 pcb->snd_wnd, pcb->cwnd, wnd, pcb->lastack));
+  } else {
+    LWIP_DEBUGF(TCP_CWND_DEBUG, 
+                ("tcp_output: snd_wnd %"U16_F", cwnd %"U16_F", wnd %"U32_F
+                 ", effwnd %"U32_F", seq %"U32_F", ack %"U32_F"\n",
+                 pcb->snd_wnd, pcb->cwnd, wnd,
+                 ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len,
+                 ntohl(seg->tcphdr->seqno), pcb->lastack));
+  }
+#endif /* TCP_CWND_DEBUG */
+  /* data available and window allows it to be sent? */
+  while (seg != NULL &&
+         ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) {
+    LWIP_ASSERT("RST not expected here!", 
+                (TCPH_FLAGS(seg->tcphdr) & TCP_RST) == 0);
+    /* Stop sending if the nagle algorithm would prevent it
+     * Don't stop:
+     * - if tcp_write had a memory error before (prevent delayed ACK timeout) or
+     * - if FIN was already enqueued for this PCB (SYN is always alone in a segment -
+     *   either seg->next != NULL or pcb->unacked == NULL;
+     *   RST is no sent using tcp_write/tcp_output.
+     */
+    if((tcp_do_output_nagle(pcb) == 0) &&
+      ((pcb->flags & (TF_NAGLEMEMERR | TF_FIN)) == 0)){
+      break;
+    }
+#if TCP_CWND_DEBUG
+    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U16_F", cwnd %"U16_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F", i %"S16_F"\n",
+                            pcb->snd_wnd, pcb->cwnd, wnd,
+                            ntohl(seg->tcphdr->seqno) + seg->len -
+                            pcb->lastack,
+                            ntohl(seg->tcphdr->seqno), pcb->lastack, i));
+    ++i;
+#endif /* TCP_CWND_DEBUG */
+
+    pcb->unsent = seg->next;
+
+    if (pcb->state != SYN_SENT) {
+      TCPH_SET_FLAG(seg->tcphdr, TCP_ACK);
+      pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
+    }
+
+    tcp_output_segment(seg, pcb);
+    snd_nxt = ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);
+    if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) {
+      pcb->snd_nxt = snd_nxt;
+    }
+    /* put segment on unacknowledged list if length > 0 */
+    if (TCP_TCPLEN(seg) > 0) {
+      seg->next = NULL;
+      /* unacked list is empty? */
+      if (pcb->unacked == NULL) {
+        pcb->unacked = seg;
+        useg = seg;
+      /* unacked list is not empty? */
+      } else {
+        /* In the case of fast retransmit, the packet should not go to the tail
+         * of the unacked queue, but rather somewhere before it. We need to check for
+         * this case. -STJ Jul 27, 2004 */
+        if (TCP_SEQ_LT(ntohl(seg->tcphdr->seqno), ntohl(useg->tcphdr->seqno))) {
+          /* add segment to before tail of unacked list, keeping the list sorted */
+          struct tcp_seg **cur_seg = &(pcb->unacked);
+          while (*cur_seg &&
+            TCP_SEQ_LT(ntohl((*cur_seg)->tcphdr->seqno), ntohl(seg->tcphdr->seqno))) {
+              cur_seg = &((*cur_seg)->next );
+          }
+          seg->next = (*cur_seg);
+          (*cur_seg) = seg;
+        } else {
+          /* add segment to tail of unacked list */
+          useg->next = seg;
+          useg = useg->next;
+        }
+      }
+    /* do not queue empty segments on the unacked list */
+    } else {
+      tcp_seg_free(seg);
+    }
+    seg = pcb->unsent;
+  }
+#if TCP_OVERSIZE
+  if (pcb->unsent == NULL) {
+    /* last unsent has been removed, reset unsent_oversize */
+    pcb->unsent_oversize = 0;
+  }
+#endif /* TCP_OVERSIZE */
+
+  if (seg != NULL && pcb->persist_backoff == 0 && 
+      ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > pcb->snd_wnd) {
+    /* prepare for persist timer */
+    pcb->persist_cnt = 0;
+    pcb->persist_backoff = 1;
+  }
+
+  pcb->flags &= ~TF_NAGLEMEMERR;
+  return ERR_OK;
+}
+
+/**
+ * Called by tcp_output() to actually send a TCP segment over IP.
+ *
+ * @param seg the tcp_seg to send
+ * @param pcb the tcp_pcb for the TCP connection used to send the segment
+ */
+static void
+tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb)
+{
+  u16_t len;
+  struct netif *netif;
+  u32_t *opts;
+
+  /** @bug Exclude retransmitted segments from this count. */
+  snmp_inc_tcpoutsegs();
+
+  /* The TCP header has already been constructed, but the ackno and
+   wnd fields remain. */
+  seg->tcphdr->ackno = htonl(pcb->rcv_nxt);
+
+  /* advertise our receive window size in this TCP segment */
+  seg->tcphdr->wnd = htons(pcb->rcv_ann_wnd);
+
+  pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd;
+
+  /* Add any requested options.  NB MSS option is only set on SYN
+     packets, so ignore it here */
+//_RB_  LWIP_ASSERT("seg->tcphdr not aligned", ((mem_ptr_t)seg->tcphdr % MEM_ALIGNMENT) == 0);
+  opts = (u32_t *)(void *)(seg->tcphdr + 1);
+  if (seg->flags & TF_SEG_OPTS_MSS) {
+    TCP_BUILD_MSS_OPTION(*opts);
+    opts += 1;
+  }
+#if LWIP_TCP_TIMESTAMPS
+  pcb->ts_lastacksent = pcb->rcv_nxt;
+
+  if (seg->flags & TF_SEG_OPTS_TS) {
+    tcp_build_timestamp_option(pcb, opts);
+    opts += 3;
+  }
+#endif
+
+  /* Set retransmission timer running if it is not currently enabled 
+     This must be set before checking the route. */
+  if (pcb->rtime == -1) {
+    pcb->rtime = 0;
+  }
+
+  /* If we don't have a local IP address, we get one by
+     calling ip_route(). */
+  if (ip_addr_isany(&(pcb->local_ip))) {
+    netif = ip_route(&(pcb->remote_ip));
+    if (netif == NULL) {
+      return;
+    }
+    ip_addr_copy(pcb->local_ip, netif->ip_addr);
+  }
+
+  if (pcb->rttest == 0) {
+    pcb->rttest = tcp_ticks;
+    pcb->rtseq = ntohl(seg->tcphdr->seqno);
+
+    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_output_segment: rtseq %"U32_F"\n", pcb->rtseq));
+  }
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n",
+          htonl(seg->tcphdr->seqno), htonl(seg->tcphdr->seqno) +
+          seg->len));
+
+  len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload);
+
+  seg->p->len -= len;
+  seg->p->tot_len -= len;
+
+  seg->p->payload = seg->tcphdr;
+
+  seg->tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+#if TCP_CHECKSUM_ON_COPY
+  {
+    u32_t acc;
+#if TCP_CHECKSUM_ON_COPY_SANITY_CHECK
+    u16_t chksum_slow = inet_chksum_pseudo(seg->p, &(pcb->local_ip),
+           &(pcb->remote_ip),
+           IP_PROTO_TCP, seg->p->tot_len);
+#endif /* TCP_CHECKSUM_ON_COPY_SANITY_CHECK */
+    if ((seg->flags & TF_SEG_DATA_CHECKSUMMED) == 0) {
+      LWIP_ASSERT("data included but not checksummed",
+        seg->p->tot_len == (TCPH_HDRLEN(seg->tcphdr) * 4));
+    }
+
+    /* rebuild TCP header checksum (TCP header changes for retransmissions!) */
+    acc = inet_chksum_pseudo_partial(seg->p, &(pcb->local_ip),
+             &(pcb->remote_ip),
+             IP_PROTO_TCP, seg->p->tot_len, TCPH_HDRLEN(seg->tcphdr) * 4);
+    /* add payload checksum */
+    if (seg->chksum_swapped) {
+      seg->chksum = SWAP_BYTES_IN_WORD(seg->chksum);
+      seg->chksum_swapped = 0;
+    }
+    acc += (u16_t)~(seg->chksum);
+    seg->tcphdr->chksum = FOLD_U32T(acc);
+#if TCP_CHECKSUM_ON_COPY_SANITY_CHECK
+    if (chksum_slow != seg->tcphdr->chksum) {
+      LWIP_DEBUGF(TCP_DEBUG | LWIP_DBG_LEVEL_WARNING,
+                  ("tcp_output_segment: calculated checksum is %"X16_F" instead of %"X16_F"\n",
+                  seg->tcphdr->chksum, chksum_slow));
+      seg->tcphdr->chksum = chksum_slow;
+    }
+#endif /* TCP_CHECKSUM_ON_COPY_SANITY_CHECK */
+  }
+#else /* TCP_CHECKSUM_ON_COPY */
+  seg->tcphdr->chksum = inet_chksum_pseudo(seg->p, &(pcb->local_ip),
+         &(pcb->remote_ip),
+         IP_PROTO_TCP, seg->p->tot_len);
+#endif /* TCP_CHECKSUM_ON_COPY */
+#endif /* CHECKSUM_GEN_TCP */
+  TCP_STATS_INC(tcp.xmit);
+
+#if LWIP_NETIF_HWADDRHINT
+  ip_output_hinted(seg->p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,
+      IP_PROTO_TCP, &(pcb->addr_hint));
+#else /* LWIP_NETIF_HWADDRHINT*/
+  ip_output(seg->p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,
+      IP_PROTO_TCP);
+#endif /* LWIP_NETIF_HWADDRHINT*/
+}
+
+/**
+ * Send a TCP RESET packet (empty segment with RST flag set) either to
+ * abort a connection or to show that there is no matching local connection
+ * for a received segment.
+ *
+ * Called by tcp_abort() (to abort a local connection), tcp_input() (if no
+ * matching local pcb was found), tcp_listen_input() (if incoming segment
+ * has ACK flag set) and tcp_process() (received segment in the wrong state)
+ *
+ * Since a RST segment is in most cases not sent for an active connection,
+ * tcp_rst() has a number of arguments that are taken from a tcp_pcb for
+ * most other segment output functions.
+ *
+ * @param seqno the sequence number to use for the outgoing segment
+ * @param ackno the acknowledge number to use for the outgoing segment
+ * @param local_ip the local IP address to send the segment from
+ * @param remote_ip the remote IP address to send the segment to
+ * @param local_port the local TCP port to send the segment from
+ * @param remote_port the remote TCP port to send the segment to
+ */
+void
+tcp_rst(u32_t seqno, u32_t ackno,
+  ip_addr_t *local_ip, ip_addr_t *remote_ip,
+  u16_t local_port, u16_t remote_port)
+{
+  struct pbuf *p;
+  struct tcp_hdr *tcphdr;
+  p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
+  if (p == NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n"));
+      return;
+  }
+  LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr",
+              (p->len >= sizeof(struct tcp_hdr)));
+
+  tcphdr = (struct tcp_hdr *)p->payload;
+  tcphdr->src = htons(local_port);
+  tcphdr->dest = htons(remote_port);
+  tcphdr->seqno = htonl(seqno);
+  tcphdr->ackno = htonl(ackno);
+  TCPH_HDRLEN_FLAGS_SET(tcphdr, TCP_HLEN/4, TCP_RST | TCP_ACK);
+  tcphdr->wnd = PP_HTONS(TCP_WND);
+  tcphdr->chksum = 0;
+  tcphdr->urgp = 0;
+
+#if CHECKSUM_GEN_TCP
+  tcphdr->chksum = inet_chksum_pseudo(p, local_ip, remote_ip,
+              IP_PROTO_TCP, p->tot_len);
+#endif
+  TCP_STATS_INC(tcp.xmit);
+  snmp_inc_tcpoutrsts();
+   /* Send output with hardcoded TTL since we have no access to the pcb */
+  ip_output(p, local_ip, remote_ip, TCP_TTL, 0, IP_PROTO_TCP);
+  pbuf_free(p);
+  LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno));
+}
+
+/**
+ * Requeue all unacked segments for retransmission
+ *
+ * Called by tcp_slowtmr() for slow retransmission.
+ *
+ * @param pcb the tcp_pcb for which to re-enqueue all unacked segments
+ */
+void
+tcp_rexmit_rto(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *seg;
+
+  if (pcb->unacked == NULL) {
+    return;
+  }
+
+  /* Move all unacked segments to the head of the unsent queue */
+  for (seg = pcb->unacked; seg->next != NULL; seg = seg->next);
+  /* concatenate unsent queue after unacked queue */
+  seg->next = pcb->unsent;
+  /* unsent queue is the concatenated queue (of unacked, unsent) */
+  pcb->unsent = pcb->unacked;
+  /* unacked queue is now empty */
+  pcb->unacked = NULL;
+
+  /* increment number of retransmissions */
+  ++pcb->nrtx;
+
+  /* Don't take any RTT measurements after retransmitting. */
+  pcb->rttest = 0;
+
+  /* Do the actual retransmission */
+  tcp_output(pcb);
+}
+
+/**
+ * Requeue the first unacked segment for retransmission
+ *
+ * Called by tcp_receive() for fast retramsmit.
+ *
+ * @param pcb the tcp_pcb for which to retransmit the first unacked segment
+ */
+void
+tcp_rexmit(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *seg;
+  struct tcp_seg **cur_seg;
+
+  if (pcb->unacked == NULL) {
+    return;
+  }
+
+  /* Move the first unacked segment to the unsent queue */
+  /* Keep the unsent queue sorted. */
+  seg = pcb->unacked;
+  pcb->unacked = seg->next;
+
+  cur_seg = &(pcb->unsent);
+  while (*cur_seg &&
+    TCP_SEQ_LT(ntohl((*cur_seg)->tcphdr->seqno), ntohl(seg->tcphdr->seqno))) {
+      cur_seg = &((*cur_seg)->next );
+  }
+  seg->next = *cur_seg;
+  *cur_seg = seg;
+
+  ++pcb->nrtx;
+
+  /* Don't take any rtt measurements after retransmitting. */
+  pcb->rttest = 0;
+
+  /* Do the actual retransmission. */
+  snmp_inc_tcpretranssegs();
+  /* No need to call tcp_output: we are always called from tcp_input()
+     and thus tcp_output directly returns. */
+}
+
+
+/**
+ * Handle retransmission after three dupacks received
+ *
+ * @param pcb the tcp_pcb for which to retransmit the first unacked segment
+ */
+void 
+tcp_rexmit_fast(struct tcp_pcb *pcb)
+{
+  if (pcb->unacked != NULL && !(pcb->flags & TF_INFR)) {
+    /* This is fast retransmit. Retransmit the first unacked segment. */
+    LWIP_DEBUGF(TCP_FR_DEBUG, 
+                ("tcp_receive: dupacks %"U16_F" (%"U32_F
+                 "), fast retransmit %"U32_F"\n",
+                 (u16_t)pcb->dupacks, pcb->lastack,
+                 ntohl(pcb->unacked->tcphdr->seqno)));
+    tcp_rexmit(pcb);
+
+    /* Set ssthresh to half of the minimum of the current
+     * cwnd and the advertised window */
+    if (pcb->cwnd > pcb->snd_wnd) {
+      pcb->ssthresh = pcb->snd_wnd / 2;
+    } else {
+      pcb->ssthresh = pcb->cwnd / 2;
+    }
+    
+    /* The minimum value for ssthresh should be 2 MSS */
+    if (pcb->ssthresh < 2*pcb->mss) {
+      LWIP_DEBUGF(TCP_FR_DEBUG, 
+                  ("tcp_receive: The minimum value for ssthresh %"U16_F
+                   " should be min 2 mss %"U16_F"...\n",
+                   pcb->ssthresh, 2*pcb->mss));
+      pcb->ssthresh = 2*pcb->mss;
+    }
+    
+    pcb->cwnd = pcb->ssthresh + 3 * pcb->mss;
+    pcb->flags |= TF_INFR;
+  } 
+}
+
+
+/**
+ * Send keepalive packets to keep a connection active although
+ * no data is sent over it.
+ *
+ * Called by tcp_slowtmr()
+ *
+ * @param pcb the tcp_pcb for which to send a keepalive packet
+ */
+void
+tcp_keepalive(struct tcp_pcb *pcb)
+{
+  struct pbuf *p;
+  struct tcp_hdr *tcphdr;
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: sending KEEPALIVE probe to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+                          ip4_addr1_16(&pcb->remote_ip), ip4_addr2_16(&pcb->remote_ip),
+                          ip4_addr3_16(&pcb->remote_ip), ip4_addr4_16(&pcb->remote_ip)));
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F"   pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n", 
+                          tcp_ticks, pcb->tmr, pcb->keep_cnt_sent));
+   
+  p = tcp_output_alloc_header(pcb, 0, 0, htonl(pcb->snd_nxt - 1));
+  if(p == NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, 
+                ("tcp_keepalive: could not allocate memory for pbuf\n"));
+    return;
+  }
+  tcphdr = (struct tcp_hdr *)p->payload;
+
+#if CHECKSUM_GEN_TCP
+  tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip,
+                                      IP_PROTO_TCP, p->tot_len);
+#endif
+  TCP_STATS_INC(tcp.xmit);
+
+  /* Send output to IP */
+#if LWIP_NETIF_HWADDRHINT
+  ip_output_hinted(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP,
+    &(pcb->addr_hint));
+#else /* LWIP_NETIF_HWADDRHINT*/
+  ip_output(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP);
+#endif /* LWIP_NETIF_HWADDRHINT*/
+
+  pbuf_free(p);
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F".\n",
+                          pcb->snd_nxt - 1, pcb->rcv_nxt));
+}
+
+
+/**
+ * Send persist timer zero-window probes to keep a connection active
+ * when a window update is lost.
+ *
+ * Called by tcp_slowtmr()
+ *
+ * @param pcb the tcp_pcb for which to send a zero-window probe packet
+ */
+void
+tcp_zero_window_probe(struct tcp_pcb *pcb)
+{
+  struct pbuf *p;
+  struct tcp_hdr *tcphdr;
+  struct tcp_seg *seg;
+  u16_t len;
+  u8_t is_fin;
+
+  LWIP_DEBUGF(TCP_DEBUG, 
+              ("tcp_zero_window_probe: sending ZERO WINDOW probe to %"
+               U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+               ip4_addr1_16(&pcb->remote_ip), ip4_addr2_16(&pcb->remote_ip),
+               ip4_addr3_16(&pcb->remote_ip), ip4_addr4_16(&pcb->remote_ip)));
+
+  LWIP_DEBUGF(TCP_DEBUG, 
+              ("tcp_zero_window_probe: tcp_ticks %"U32_F
+               "   pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n", 
+               tcp_ticks, pcb->tmr, pcb->keep_cnt_sent));
+
+  seg = pcb->unacked;
+
+  if(seg == NULL) {
+    seg = pcb->unsent;
+  }
+  if(seg == NULL) {
+    return;
+  }
+
+  is_fin = ((TCPH_FLAGS(seg->tcphdr) & TCP_FIN) != 0) && (seg->len == 0);
+  /* we want to send one seqno: either FIN or data (no options) */
+  len = is_fin ? 0 : 1;
+
+  p = tcp_output_alloc_header(pcb, 0, len, seg->tcphdr->seqno);
+  if(p == NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: no memory for pbuf\n"));
+    return;
+  }
+  tcphdr = (struct tcp_hdr *)p->payload;
+
+  if (is_fin) {
+    /* FIN segment, no data */
+    TCPH_FLAGS_SET(tcphdr, TCP_ACK | TCP_FIN);
+  } else {
+    /* Data segment, copy in one byte from the head of the unacked queue */
+    struct tcp_hdr *thdr = (struct tcp_hdr *)seg->p->payload;
+    char *d = ((char *)p->payload + TCP_HLEN);
+    pbuf_copy_partial(seg->p, d, 1, TCPH_HDRLEN(thdr) * 4);
+  }
+
+#if CHECKSUM_GEN_TCP
+  tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip,
+                                      IP_PROTO_TCP, p->tot_len);
+#endif
+  TCP_STATS_INC(tcp.xmit);
+
+  /* Send output to IP */
+#if LWIP_NETIF_HWADDRHINT
+  ip_output_hinted(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP,
+    &(pcb->addr_hint));
+#else /* LWIP_NETIF_HWADDRHINT*/
+  ip_output(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP);
+#endif /* LWIP_NETIF_HWADDRHINT*/
+
+  pbuf_free(p);
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: seqno %"U32_F
+                          " ackno %"U32_F".\n",
+                          pcb->snd_nxt - 1, pcb->rcv_nxt));
+}
+#endif /* LWIP_TCP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/udp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/udp.c
new file mode 100644
index 0000000..4596ba2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/core/udp.c
@@ -0,0 +1,966 @@
+/**
+ * @file
+ * User Datagram Protocol module
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+/* udp.c
+ *
+ * The code for the User Datagram Protocol UDP & UDPLite (RFC 3828).
+ *
+ */
+
+/* @todo Check the use of '(struct udp_pcb).chksum_len_rx'!
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_UDP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/udp.h"
+#include "lwip/def.h"
+#include "lwip/memp.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/icmp.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+#include "arch/perf.h"
+#include "lwip/dhcp.h"
+
+#include 
+
+/* The list of UDP PCBs */
+/* exported in udp.h (was static) */
+struct udp_pcb *udp_pcbs;
+
+/**
+ * Process an incoming UDP datagram.
+ *
+ * Given an incoming UDP datagram (as a chain of pbufs) this function
+ * finds a corresponding UDP PCB and hands over the pbuf to the pcbs
+ * recv function. If no pcb is found or the datagram is incorrect, the
+ * pbuf is freed.
+ *
+ * @param p pbuf to be demultiplexed to a UDP PCB.
+ * @param inp network interface on which the datagram was received.
+ *
+ */
+void
+udp_input(struct pbuf *p, struct netif *inp)
+{
+  struct udp_hdr *udphdr;
+  struct udp_pcb *pcb, *prev;
+  struct udp_pcb *uncon_pcb;
+  struct ip_hdr *iphdr;
+  u16_t src, dest;
+  u8_t local_match;
+  u8_t broadcast;
+
+  PERF_START;
+
+  UDP_STATS_INC(udp.recv);
+
+  iphdr = (struct ip_hdr *)p->payload;
+
+  /* Check minimum length (IP header + UDP header)
+   * and move payload pointer to UDP header */
+  if (p->tot_len < (IPH_HL(iphdr) * 4 + UDP_HLEN) || pbuf_header(p, -(s16_t)(IPH_HL(iphdr) * 4))) {
+    /* drop short packets */
+    LWIP_DEBUGF(UDP_DEBUG,
+                ("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len));
+    UDP_STATS_INC(udp.lenerr);
+    UDP_STATS_INC(udp.drop);
+    snmp_inc_udpinerrors();
+    pbuf_free(p);
+    goto end;
+  }
+
+  udphdr = (struct udp_hdr *)p->payload;
+
+  /* is broadcast packet ? */
+  broadcast = ip_addr_isbroadcast(¤t_iphdr_dest, inp);
+
+  LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len));
+
+  /* convert src and dest ports to host byte order */
+  src = ntohs(udphdr->src);
+  dest = ntohs(udphdr->dest);
+
+  udp_debug_print(udphdr);
+
+  /* print the UDP source and destination */
+  LWIP_DEBUGF(UDP_DEBUG,
+              ("udp (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") <-- "
+               "(%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n",
+               ip4_addr1_16(&iphdr->dest), ip4_addr2_16(&iphdr->dest),
+               ip4_addr3_16(&iphdr->dest), ip4_addr4_16(&iphdr->dest), ntohs(udphdr->dest),
+               ip4_addr1_16(&iphdr->src), ip4_addr2_16(&iphdr->src),
+               ip4_addr3_16(&iphdr->src), ip4_addr4_16(&iphdr->src), ntohs(udphdr->src)));
+
+#if LWIP_DHCP
+  pcb = NULL;
+  /* when LWIP_DHCP is active, packets to DHCP_CLIENT_PORT may only be processed by
+     the dhcp module, no other UDP pcb may use the local UDP port DHCP_CLIENT_PORT */
+  if (dest == DHCP_CLIENT_PORT) {
+    /* all packets for DHCP_CLIENT_PORT not coming from DHCP_SERVER_PORT are dropped! */
+    if (src == DHCP_SERVER_PORT) {
+      if ((inp->dhcp != NULL) && (inp->dhcp->pcb != NULL)) {
+        /* accept the packe if 
+           (- broadcast or directed to us) -> DHCP is link-layer-addressed, local ip is always ANY!
+           - inp->dhcp->pcb->remote == ANY or iphdr->src */
+        if ((ip_addr_isany(&inp->dhcp->pcb->remote_ip) ||
+           ip_addr_cmp(&(inp->dhcp->pcb->remote_ip), ¤t_iphdr_src))) {
+          pcb = inp->dhcp->pcb;
+        }
+      }
+    }
+  } else
+#endif /* LWIP_DHCP */
+  {
+    prev = NULL;
+    local_match = 0;
+    uncon_pcb = NULL;
+    /* Iterate through the UDP pcb list for a matching pcb.
+     * 'Perfect match' pcbs (connected to the remote port & ip address) are
+     * preferred. If no perfect match is found, the first unconnected pcb that
+     * matches the local port and ip address gets the datagram. */
+    for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
+      local_match = 0;
+      /* print the PCB local and remote address */
+      LWIP_DEBUGF(UDP_DEBUG,
+                  ("pcb (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") --- "
+                   "(%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n",
+                   ip4_addr1_16(&pcb->local_ip), ip4_addr2_16(&pcb->local_ip),
+                   ip4_addr3_16(&pcb->local_ip), ip4_addr4_16(&pcb->local_ip), pcb->local_port,
+                   ip4_addr1_16(&pcb->remote_ip), ip4_addr2_16(&pcb->remote_ip),
+                   ip4_addr3_16(&pcb->remote_ip), ip4_addr4_16(&pcb->remote_ip), pcb->remote_port));
+
+      /* compare PCB local addr+port to UDP destination addr+port */
+      if ((pcb->local_port == dest) &&
+          ((!broadcast && ip_addr_isany(&pcb->local_ip)) ||
+           ip_addr_cmp(&(pcb->local_ip), ¤t_iphdr_dest) ||
+#if LWIP_IGMP
+           ip_addr_ismulticast(¤t_iphdr_dest) ||
+#endif /* LWIP_IGMP */
+#if IP_SOF_BROADCAST_RECV
+           (broadcast && (pcb->so_options & SOF_BROADCAST)))) {
+#else  /* IP_SOF_BROADCAST_RECV */
+           (broadcast))) {
+#endif /* IP_SOF_BROADCAST_RECV */
+        local_match = 1;
+        if ((uncon_pcb == NULL) && 
+            ((pcb->flags & UDP_FLAGS_CONNECTED) == 0)) {
+          /* the first unconnected matching PCB */
+          uncon_pcb = pcb;
+        }
+      }
+      /* compare PCB remote addr+port to UDP source addr+port */
+      if ((local_match != 0) &&
+          (pcb->remote_port == src) &&
+          (ip_addr_isany(&pcb->remote_ip) ||
+           ip_addr_cmp(&(pcb->remote_ip), ¤t_iphdr_src))) {
+        /* the first fully matching PCB */
+        if (prev != NULL) {
+          /* move the pcb to the front of udp_pcbs so that is
+             found faster next time */
+          prev->next = pcb->next;
+          pcb->next = udp_pcbs;
+          udp_pcbs = pcb;
+        } else {
+          UDP_STATS_INC(udp.cachehit);
+        }
+        break;
+      }
+      prev = pcb;
+    }
+    /* no fully matching pcb found? then look for an unconnected pcb */
+    if (pcb == NULL) {
+      pcb = uncon_pcb;
+    }
+  }
+
+  /* Check checksum if this is a match or if it was directed at us. */
+  if (pcb != NULL || ip_addr_cmp(&inp->ip_addr, ¤t_iphdr_dest)) {
+    LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_input: calculating checksum\n"));
+#if LWIP_UDPLITE
+    if (IPH_PROTO(iphdr) == IP_PROTO_UDPLITE) {
+      /* Do the UDP Lite checksum */
+#if CHECKSUM_CHECK_UDP
+      u16_t chklen = ntohs(udphdr->len);
+      if (chklen < sizeof(struct udp_hdr)) {
+        if (chklen == 0) {
+          /* For UDP-Lite, checksum length of 0 means checksum
+             over the complete packet (See RFC 3828 chap. 3.1) */
+          chklen = p->tot_len;
+        } else {
+          /* At least the UDP-Lite header must be covered by the
+             checksum! (Again, see RFC 3828 chap. 3.1) */
+          UDP_STATS_INC(udp.chkerr);
+          UDP_STATS_INC(udp.drop);
+          snmp_inc_udpinerrors();
+          pbuf_free(p);
+          goto end;
+        }
+      }
+      if (inet_chksum_pseudo_partial(p, ¤t_iphdr_src, ¤t_iphdr_dest,
+                             IP_PROTO_UDPLITE, p->tot_len, chklen) != 0) {
+       LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+                   ("udp_input: UDP Lite datagram discarded due to failing checksum\n"));
+        UDP_STATS_INC(udp.chkerr);
+        UDP_STATS_INC(udp.drop);
+        snmp_inc_udpinerrors();
+        pbuf_free(p);
+        goto end;
+      }
+#endif /* CHECKSUM_CHECK_UDP */
+    } else
+#endif /* LWIP_UDPLITE */
+    {
+#if CHECKSUM_CHECK_UDP
+      if (udphdr->chksum != 0) {
+        if (inet_chksum_pseudo(p, ip_current_src_addr(), ip_current_dest_addr(),
+                               IP_PROTO_UDP, p->tot_len) != 0) {
+          LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+                      ("udp_input: UDP datagram discarded due to failing checksum\n"));
+          UDP_STATS_INC(udp.chkerr);
+          UDP_STATS_INC(udp.drop);
+          snmp_inc_udpinerrors();
+          pbuf_free(p);
+          goto end;
+        }
+      }
+#endif /* CHECKSUM_CHECK_UDP */
+    }
+    if(pbuf_header(p, -UDP_HLEN)) {
+      /* Can we cope with this failing? Just assert for now */
+      LWIP_ASSERT("pbuf_header failed\n", 0);
+      UDP_STATS_INC(udp.drop);
+      snmp_inc_udpinerrors();
+      pbuf_free(p);
+      goto end;
+    }
+    if (pcb != NULL) {
+      snmp_inc_udpindatagrams();
+#if SO_REUSE && SO_REUSE_RXTOALL
+      if ((broadcast || ip_addr_ismulticast(¤t_iphdr_dest)) &&
+          ((pcb->so_options & SOF_REUSEADDR) != 0)) {
+        /* pass broadcast- or multicast packets to all multicast pcbs
+           if SOF_REUSEADDR is set on the first match */
+        struct udp_pcb *mpcb;
+        u8_t p_header_changed = 0;
+        for (mpcb = udp_pcbs; mpcb != NULL; mpcb = mpcb->next) {
+          if (mpcb != pcb) {
+            /* compare PCB local addr+port to UDP destination addr+port */
+            if ((mpcb->local_port == dest) &&
+                ((!broadcast && ip_addr_isany(&mpcb->local_ip)) ||
+                 ip_addr_cmp(&(mpcb->local_ip), ¤t_iphdr_dest) ||
+#if LWIP_IGMP
+                 ip_addr_ismulticast(¤t_iphdr_dest) ||
+#endif /* LWIP_IGMP */
+#if IP_SOF_BROADCAST_RECV
+                 (broadcast && (mpcb->so_options & SOF_BROADCAST)))) {
+#else  /* IP_SOF_BROADCAST_RECV */
+                 (broadcast))) {
+#endif /* IP_SOF_BROADCAST_RECV */
+              /* pass a copy of the packet to all local matches */
+              if (mpcb->recv != NULL) {
+                struct pbuf *q;
+                /* for that, move payload to IP header again */
+                if (p_header_changed == 0) {
+                  pbuf_header(p, (s16_t)((IPH_HL(iphdr) * 4) + UDP_HLEN));
+                  p_header_changed = 1;
+                }
+                q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
+                if (q != NULL) {
+                  err_t err = pbuf_copy(q, p);
+                  if (err == ERR_OK) {
+                    /* move payload to UDP data */
+                    pbuf_header(q, -(s16_t)((IPH_HL(iphdr) * 4) + UDP_HLEN));
+                    mpcb->recv(mpcb->recv_arg, mpcb, q, ip_current_src_addr(), src);
+                  }
+                }
+              }
+            }
+          }
+        }
+        if (p_header_changed) {
+          /* and move payload to UDP data again */
+          pbuf_header(p, -(s16_t)((IPH_HL(iphdr) * 4) + UDP_HLEN));
+        }
+      }
+#endif /* SO_REUSE && SO_REUSE_RXTOALL */
+      /* callback */
+      if (pcb->recv != NULL) {
+        /* now the recv function is responsible for freeing p */
+        pcb->recv(pcb->recv_arg, pcb, p, ip_current_src_addr(), src);
+      } else {
+        /* no recv function registered? then we have to free the pbuf! */
+        pbuf_free(p);
+        goto end;
+      }
+    } else {
+      LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_input: not for us.\n"));
+
+#if LWIP_ICMP
+      /* No match was found, send ICMP destination port unreachable unless
+         destination address was broadcast/multicast. */
+      if (!broadcast &&
+          !ip_addr_ismulticast(¤t_iphdr_dest)) {
+        /* move payload pointer back to ip header */
+        pbuf_header(p, (IPH_HL(iphdr) * 4) + UDP_HLEN);
+        LWIP_ASSERT("p->payload == iphdr", (p->payload == iphdr));
+        icmp_dest_unreach(p, ICMP_DUR_PORT);
+      }
+#endif /* LWIP_ICMP */
+      UDP_STATS_INC(udp.proterr);
+      UDP_STATS_INC(udp.drop);
+      snmp_inc_udpnoports();
+      pbuf_free(p);
+    }
+  } else {
+    pbuf_free(p);
+  }
+end:
+  PERF_STOP("udp_input");
+}
+
+/**
+ * Send data using UDP.
+ *
+ * @param pcb UDP PCB used to send the data.
+ * @param p chain of pbuf's to be sent.
+ *
+ * The datagram will be sent to the current remote_ip & remote_port
+ * stored in pcb. If the pcb is not bound to a port, it will
+ * automatically be bound to a random port.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_MEM. Out of memory.
+ * - ERR_RTE. Could not find route to destination address.
+ * - More errors could be returned by lower protocol layers.
+ *
+ * @see udp_disconnect() udp_sendto()
+ */
+err_t
+udp_send(struct udp_pcb *pcb, struct pbuf *p)
+{
+  /* send to the packet using remote ip and port stored in the pcb */
+  return udp_sendto(pcb, p, &pcb->remote_ip, pcb->remote_port);
+}
+
+#if LWIP_CHECKSUM_ON_COPY
+/** Same as udp_send() but with checksum
+ */
+err_t
+udp_send_chksum(struct udp_pcb *pcb, struct pbuf *p,
+                u8_t have_chksum, u16_t chksum)
+{
+  /* send to the packet using remote ip and port stored in the pcb */
+  return udp_sendto_chksum(pcb, p, &pcb->remote_ip, pcb->remote_port,
+    have_chksum, chksum);
+}
+#endif /* LWIP_CHECKSUM_ON_COPY */
+
+/**
+ * Send data to a specified address using UDP.
+ *
+ * @param pcb UDP PCB used to send the data.
+ * @param p chain of pbuf's to be sent.
+ * @param dst_ip Destination IP address.
+ * @param dst_port Destination UDP port.
+ *
+ * dst_ip & dst_port are expected to be in the same byte order as in the pcb.
+ *
+ * If the PCB already has a remote address association, it will
+ * be restored after the data is sent.
+ * 
+ * @return lwIP error code (@see udp_send for possible error codes)
+ *
+ * @see udp_disconnect() udp_send()
+ */
+err_t
+udp_sendto(struct udp_pcb *pcb, struct pbuf *p,
+  ip_addr_t *dst_ip, u16_t dst_port)
+{
+#if LWIP_CHECKSUM_ON_COPY
+  return udp_sendto_chksum(pcb, p, dst_ip, dst_port, 0, 0);
+}
+
+/** Same as udp_sendto(), but with checksum */
+err_t
+udp_sendto_chksum(struct udp_pcb *pcb, struct pbuf *p, ip_addr_t *dst_ip,
+                  u16_t dst_port, u8_t have_chksum, u16_t chksum)
+{
+#endif /* LWIP_CHECKSUM_ON_COPY */
+  struct netif *netif;
+
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_send\n"));
+
+  /* find the outgoing network interface for this packet */
+#if LWIP_IGMP
+  netif = ip_route((ip_addr_ismulticast(dst_ip))?(&(pcb->multicast_ip)):(dst_ip));
+#else
+  netif = ip_route(dst_ip);
+#endif /* LWIP_IGMP */
+
+  /* no outgoing network interface could be found? */
+  if (netif == NULL) {
+    LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+      ip4_addr1_16(dst_ip), ip4_addr2_16(dst_ip), ip4_addr3_16(dst_ip), ip4_addr4_16(dst_ip)));
+    UDP_STATS_INC(udp.rterr);
+    return ERR_RTE;
+  }
+#if LWIP_CHECKSUM_ON_COPY
+  return udp_sendto_if_chksum(pcb, p, dst_ip, dst_port, netif, have_chksum, chksum);
+#else /* LWIP_CHECKSUM_ON_COPY */
+  return udp_sendto_if(pcb, p, dst_ip, dst_port, netif);
+#endif /* LWIP_CHECKSUM_ON_COPY */
+}
+
+/**
+ * Send data to a specified address using UDP.
+ * The netif used for sending can be specified.
+ *
+ * This function exists mainly for DHCP, to be able to send UDP packets
+ * on a netif that is still down.
+ *
+ * @param pcb UDP PCB used to send the data.
+ * @param p chain of pbuf's to be sent.
+ * @param dst_ip Destination IP address.
+ * @param dst_port Destination UDP port.
+ * @param netif the netif used for sending.
+ *
+ * dst_ip & dst_port are expected to be in the same byte order as in the pcb.
+ *
+ * @return lwIP error code (@see udp_send for possible error codes)
+ *
+ * @see udp_disconnect() udp_send()
+ */
+err_t
+udp_sendto_if(struct udp_pcb *pcb, struct pbuf *p,
+  ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif)
+{
+#if LWIP_CHECKSUM_ON_COPY
+  return udp_sendto_if_chksum(pcb, p, dst_ip, dst_port, netif, 0, 0);
+}
+
+/** Same as udp_sendto_if(), but with checksum */
+err_t
+udp_sendto_if_chksum(struct udp_pcb *pcb, struct pbuf *p, ip_addr_t *dst_ip,
+                     u16_t dst_port, struct netif *netif, u8_t have_chksum,
+                     u16_t chksum)
+{
+#endif /* LWIP_CHECKSUM_ON_COPY */
+  struct udp_hdr *udphdr;
+  ip_addr_t *src_ip;
+  err_t err;
+  struct pbuf *q; /* q will be sent down the stack */
+
+#if IP_SOF_BROADCAST
+  /* broadcast filter? */
+  if ( ((pcb->so_options & SOF_BROADCAST) == 0) && ip_addr_isbroadcast(dst_ip, netif) ) {
+    LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+      ("udp_sendto_if: SOF_BROADCAST not enabled on pcb %p\n", (void *)pcb));
+    return ERR_VAL;
+  }
+#endif /* IP_SOF_BROADCAST */
+
+  /* if the PCB is not yet bound to a port, bind it here */
+  if (pcb->local_port == 0) {
+    LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_send: not yet bound to a port, binding now\n"));
+    err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
+    if (err != ERR_OK) {
+      LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: forced port bind failed\n"));
+      return err;
+    }
+  }
+
+  /* not enough space to add an UDP header to first pbuf in given p chain? */
+  if (pbuf_header(p, UDP_HLEN)) {
+    /* allocate header in a separate new pbuf */
+    q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM);
+    /* new header pbuf could not be allocated? */
+    if (q == NULL) {
+      LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: could not allocate header\n"));
+      return ERR_MEM;
+    }
+    if (p->tot_len != 0) {
+      /* chain header q in front of given pbuf p (only if p contains data) */
+      pbuf_chain(q, p);
+    }
+    /* first pbuf q points to header pbuf */
+    LWIP_DEBUGF(UDP_DEBUG,
+                ("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
+  } else {
+    /* adding space for header within p succeeded */
+    /* first pbuf q equals given pbuf */
+    q = p;
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p));
+  }
+  LWIP_ASSERT("check that first pbuf can hold struct udp_hdr",
+              (q->len >= sizeof(struct udp_hdr)));
+  /* q now represents the packet to be sent */
+  udphdr = (struct udp_hdr *)q->payload;
+  udphdr->src = htons(pcb->local_port);
+  udphdr->dest = htons(dst_port);
+  /* in UDP, 0 checksum means 'no checksum' */
+  udphdr->chksum = 0x0000; 
+
+  /* Multicast Loop? */
+#if LWIP_IGMP
+  if (ip_addr_ismulticast(dst_ip) && ((pcb->flags & UDP_FLAGS_MULTICAST_LOOP) != 0)) {
+    q->flags |= PBUF_FLAG_MCASTLOOP;
+  }
+#endif /* LWIP_IGMP */
+
+
+  /* PCB local address is IP_ANY_ADDR? */
+  if (ip_addr_isany(&pcb->local_ip)) {
+    /* use outgoing network interface IP address as source address */
+    src_ip = &(netif->ip_addr);
+  } else {
+    /* check if UDP PCB local IP address is correct
+     * this could be an old address if netif->ip_addr has changed */
+    if (!ip_addr_cmp(&(pcb->local_ip), &(netif->ip_addr))) {
+      /* local_ip doesn't match, drop the packet */
+      if (q != p) {
+        /* free the header pbuf */
+        pbuf_free(q);
+        q = NULL;
+        /* p is still referenced by the caller, and will live on */
+      }
+      return ERR_VAL;
+    }
+    /* use UDP PCB local IP address as source address */
+    src_ip = &(pcb->local_ip);
+  }
+
+  LWIP_DEBUGF(UDP_DEBUG, ("udp_send: sending datagram of length %"U16_F"\n", q->tot_len));
+
+#if LWIP_UDPLITE
+  /* UDP Lite protocol? */
+  if (pcb->flags & UDP_FLAGS_UDPLITE) {
+    u16_t chklen, chklen_hdr;
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE packet length %"U16_F"\n", q->tot_len));
+    /* set UDP message length in UDP header */
+    chklen_hdr = chklen = pcb->chksum_len_tx;
+    if ((chklen < sizeof(struct udp_hdr)) || (chklen > q->tot_len)) {
+      if (chklen != 0) {
+        LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE pcb->chksum_len is illegal: %"U16_F"\n", chklen));
+      }
+      /* For UDP-Lite, checksum length of 0 means checksum
+         over the complete packet. (See RFC 3828 chap. 3.1)
+         At least the UDP-Lite header must be covered by the
+         checksum, therefore, if chksum_len has an illegal
+         value, we generate the checksum over the complete
+         packet to be safe. */
+      chklen_hdr = 0;
+      chklen = q->tot_len;
+    }
+    udphdr->len = htons(chklen_hdr);
+    /* calculate checksum */
+#if CHECKSUM_GEN_UDP
+    udphdr->chksum = inet_chksum_pseudo_partial(q, src_ip, dst_ip,
+      IP_PROTO_UDPLITE, q->tot_len,
+#if !LWIP_CHECKSUM_ON_COPY
+      chklen);
+#else /* !LWIP_CHECKSUM_ON_COPY */
+      (have_chksum ? UDP_HLEN : chklen));
+    if (have_chksum) {
+      u32_t acc;
+      acc = udphdr->chksum + (u16_t)~(chksum);
+      udphdr->chksum = FOLD_U32T(acc);
+    }
+#endif /* !LWIP_CHECKSUM_ON_COPY */
+
+    /* chksum zero must become 0xffff, as zero means 'no checksum' */
+    if (udphdr->chksum == 0x0000) {
+      udphdr->chksum = 0xffff;
+    }
+#endif /* CHECKSUM_GEN_UDP */
+    /* output to IP */
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDPLITE,)\n"));
+#if LWIP_NETIF_HWADDRHINT
+    netif->addr_hint = &(pcb->addr_hint);
+#endif /* LWIP_NETIF_HWADDRHINT*/
+    err = ip_output_if(q, src_ip, dst_ip, pcb->ttl, pcb->tos, IP_PROTO_UDPLITE, netif);
+#if LWIP_NETIF_HWADDRHINT
+    netif->addr_hint = NULL;
+#endif /* LWIP_NETIF_HWADDRHINT*/
+  } else
+#endif /* LWIP_UDPLITE */
+  {      /* UDP */
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %"U16_F"\n", q->tot_len));
+    udphdr->len = htons(q->tot_len);
+    /* calculate checksum */
+#if CHECKSUM_GEN_UDP
+    if ((pcb->flags & UDP_FLAGS_NOCHKSUM) == 0) {
+      u16_t udpchksum;
+#if LWIP_CHECKSUM_ON_COPY
+      if (have_chksum) {
+        u32_t acc;
+        udpchksum = inet_chksum_pseudo_partial(q, src_ip, dst_ip, IP_PROTO_UDP,
+          q->tot_len, UDP_HLEN);
+        acc = udpchksum + (u16_t)~(chksum);
+        udpchksum = FOLD_U32T(acc);
+      } else
+#endif /* LWIP_CHECKSUM_ON_COPY */
+      {
+        udpchksum = inet_chksum_pseudo(q, src_ip, dst_ip, IP_PROTO_UDP, q->tot_len);
+      }
+
+      /* chksum zero must become 0xffff, as zero means 'no checksum' */
+      if (udpchksum == 0x0000) {
+        udpchksum = 0xffff;
+      }
+      udphdr->chksum = udpchksum;
+    }
+#endif /* CHECKSUM_GEN_UDP */
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04"X16_F"\n", udphdr->chksum));
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDP,)\n"));
+    /* output to IP */
+#if LWIP_NETIF_HWADDRHINT
+    netif->addr_hint = &(pcb->addr_hint);
+#endif /* LWIP_NETIF_HWADDRHINT*/
+    err = ip_output_if(q, src_ip, dst_ip, pcb->ttl, pcb->tos, IP_PROTO_UDP, netif);
+#if LWIP_NETIF_HWADDRHINT
+    netif->addr_hint = NULL;
+#endif /* LWIP_NETIF_HWADDRHINT*/
+  }
+  /* TODO: must this be increased even if error occured? */
+  snmp_inc_udpoutdatagrams();
+
+  /* did we chain a separate header pbuf earlier? */
+  if (q != p) {
+    /* free the header pbuf */
+    pbuf_free(q);
+    q = NULL;
+    /* p is still referenced by the caller, and will live on */
+  }
+
+  UDP_STATS_INC(udp.xmit);
+  return err;
+}
+
+/**
+ * Bind an UDP PCB.
+ *
+ * @param pcb UDP PCB to be bound with a local address ipaddr and port.
+ * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to
+ * bind to all local interfaces.
+ * @param port local UDP port to bind with. Use 0 to automatically bind
+ * to a random port between UDP_LOCAL_PORT_RANGE_START and
+ * UDP_LOCAL_PORT_RANGE_END.
+ *
+ * ipaddr & port are expected to be in the same byte order as in the pcb.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_USE. The specified ipaddr and port are already bound to by
+ * another UDP PCB.
+ *
+ * @see udp_disconnect()
+ */
+err_t
+udp_bind(struct udp_pcb *pcb, ip_addr_t *ipaddr, u16_t port)
+{
+  struct udp_pcb *ipcb;
+  u8_t rebind;
+
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_bind(ipaddr = "));
+  ip_addr_debug_print(UDP_DEBUG, ipaddr);
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, (", port = %"U16_F")\n", port));
+
+  rebind = 0;
+  /* Check for double bind and rebind of the same pcb */
+  for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+    /* is this UDP PCB already on active list? */
+    if (pcb == ipcb) {
+      /* pcb may occur at most once in active list */
+      LWIP_ASSERT("rebind == 0", rebind == 0);
+      /* pcb already in list, just rebind */
+      rebind = 1;
+    }
+
+    /* By default, we don't allow to bind to a port that any other udp
+       PCB is alread bound to, unless *all* PCBs with that port have tha
+       REUSEADDR flag set. */
+#if SO_REUSE
+    else if (((pcb->so_options & SOF_REUSEADDR) == 0) &&
+             ((ipcb->so_options & SOF_REUSEADDR) == 0)) {
+#else /* SO_REUSE */
+    /* port matches that of PCB in list and REUSEADDR not set -> reject */
+    else {
+#endif /* SO_REUSE */
+      if ((ipcb->local_port == port) &&
+          /* IP address matches, or one is IP_ADDR_ANY? */
+          (ip_addr_isany(&(ipcb->local_ip)) ||
+           ip_addr_isany(ipaddr) ||
+           ip_addr_cmp(&(ipcb->local_ip), ipaddr))) {
+        /* other PCB already binds to this local IP and port */
+        LWIP_DEBUGF(UDP_DEBUG,
+                    ("udp_bind: local port %"U16_F" already bound by another pcb\n", port));
+        return ERR_USE;
+      }
+    }
+  }
+
+  ip_addr_set(&pcb->local_ip, ipaddr);
+
+  /* no port specified? */
+  if (port == 0) {
+#ifndef UDP_LOCAL_PORT_RANGE_START
+/* From http://www.iana.org/assignments/port-numbers:
+   "The Dynamic and/or Private Ports are those from 49152 through 65535" */
+#define UDP_LOCAL_PORT_RANGE_START  0xc000
+#define UDP_LOCAL_PORT_RANGE_END    0xffff
+#endif
+    port = UDP_LOCAL_PORT_RANGE_START;
+    ipcb = udp_pcbs;
+    while ((ipcb != NULL) && (port != UDP_LOCAL_PORT_RANGE_END)) {
+      if (ipcb->local_port == port) {
+        /* port is already used by another udp_pcb */
+        port++;
+        /* restart scanning all udp pcbs */
+        ipcb = udp_pcbs;
+      } else {
+        /* go on with next udp pcb */
+        ipcb = ipcb->next;
+      }
+    }
+    if (ipcb != NULL) {
+      /* no more ports available in local range */
+      LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n"));
+      return ERR_USE;
+    }
+  }
+  pcb->local_port = port;
+  snmp_insert_udpidx_tree(pcb);
+  /* pcb not active yet? */
+  if (rebind == 0) {
+    /* place the PCB on the active list if not already there */
+    pcb->next = udp_pcbs;
+    udp_pcbs = pcb;
+  }
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+              ("udp_bind: bound to %"U16_F".%"U16_F".%"U16_F".%"U16_F", port %"U16_F"\n",
+               ip4_addr1_16(&pcb->local_ip), ip4_addr2_16(&pcb->local_ip),
+               ip4_addr3_16(&pcb->local_ip), ip4_addr4_16(&pcb->local_ip),
+               pcb->local_port));
+  return ERR_OK;
+}
+/**
+ * Connect an UDP PCB.
+ *
+ * This will associate the UDP PCB with the remote address.
+ *
+ * @param pcb UDP PCB to be connected with remote address ipaddr and port.
+ * @param ipaddr remote IP address to connect with.
+ * @param port remote UDP port to connect with.
+ *
+ * @return lwIP error code
+ *
+ * ipaddr & port are expected to be in the same byte order as in the pcb.
+ *
+ * The udp pcb is bound to a random local port if not already bound.
+ *
+ * @see udp_disconnect()
+ */
+err_t
+udp_connect(struct udp_pcb *pcb, ip_addr_t *ipaddr, u16_t port)
+{
+  struct udp_pcb *ipcb;
+
+  if (pcb->local_port == 0) {
+    err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
+    if (err != ERR_OK) {
+      return err;
+    }
+  }
+
+  ip_addr_set(&pcb->remote_ip, ipaddr);
+  pcb->remote_port = port;
+  pcb->flags |= UDP_FLAGS_CONNECTED;
+/** TODO: this functionality belongs in upper layers */
+#ifdef LWIP_UDP_TODO
+  /* Nail down local IP for netconn_addr()/getsockname() */
+  if (ip_addr_isany(&pcb->local_ip) && !ip_addr_isany(&pcb->remote_ip)) {
+    struct netif *netif;
+
+    if ((netif = ip_route(&(pcb->remote_ip))) == NULL) {
+      LWIP_DEBUGF(UDP_DEBUG, ("udp_connect: No route to 0x%lx\n", pcb->remote_ip.addr));
+      UDP_STATS_INC(udp.rterr);
+      return ERR_RTE;
+    }
+    /** TODO: this will bind the udp pcb locally, to the interface which
+        is used to route output packets to the remote address. However, we
+        might want to accept incoming packets on any interface! */
+    pcb->local_ip = netif->ip_addr;
+  } else if (ip_addr_isany(&pcb->remote_ip)) {
+    pcb->local_ip.addr = 0;
+  }
+#endif
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+              ("udp_connect: connected to %"U16_F".%"U16_F".%"U16_F".%"U16_F",port %"U16_F"\n",
+               ip4_addr1_16(&pcb->local_ip), ip4_addr2_16(&pcb->local_ip),
+               ip4_addr3_16(&pcb->local_ip), ip4_addr4_16(&pcb->local_ip),
+               pcb->local_port));
+
+  /* Insert UDP PCB into the list of active UDP PCBs. */
+  for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+    if (pcb == ipcb) {
+      /* already on the list, just return */
+      return ERR_OK;
+    }
+  }
+  /* PCB not yet on the list, add PCB now */
+  pcb->next = udp_pcbs;
+  udp_pcbs = pcb;
+  return ERR_OK;
+}
+
+/**
+ * Disconnect a UDP PCB
+ *
+ * @param pcb the udp pcb to disconnect.
+ */
+void
+udp_disconnect(struct udp_pcb *pcb)
+{
+  /* reset remote address association */
+  ip_addr_set_any(&pcb->remote_ip);
+  pcb->remote_port = 0;
+  /* mark PCB as unconnected */
+  pcb->flags &= ~UDP_FLAGS_CONNECTED;
+}
+
+/**
+ * Set a receive callback for a UDP PCB
+ *
+ * This callback will be called when receiving a datagram for the pcb.
+ *
+ * @param pcb the pcb for wich to set the recv callback
+ * @param recv function pointer of the callback function
+ * @param recv_arg additional argument to pass to the callback function
+ */
+void
+udp_recv(struct udp_pcb *pcb, udp_recv_fn recv, void *recv_arg)
+{
+  /* remember recv() callback and user data */
+  pcb->recv = recv;
+  pcb->recv_arg = recv_arg;
+}
+
+/**
+ * Remove an UDP PCB.
+ *
+ * @param pcb UDP PCB to be removed. The PCB is removed from the list of
+ * UDP PCB's and the data structure is freed from memory.
+ *
+ * @see udp_new()
+ */
+void
+udp_remove(struct udp_pcb *pcb)
+{
+  struct udp_pcb *pcb2;
+
+  snmp_delete_udpidx_tree(pcb);
+  /* pcb to be removed is first in list? */
+  if (udp_pcbs == pcb) {
+    /* make list start at 2nd pcb */
+    udp_pcbs = udp_pcbs->next;
+    /* pcb not 1st in list */
+  } else {
+    for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
+      /* find pcb in udp_pcbs list */
+      if (pcb2->next != NULL && pcb2->next == pcb) {
+        /* remove pcb from list */
+        pcb2->next = pcb->next;
+      }
+    }
+  }
+  memp_free(MEMP_UDP_PCB, pcb);
+}
+
+/**
+ * Create a UDP PCB.
+ *
+ * @return The UDP PCB which was created. NULL if the PCB data structure
+ * could not be allocated.
+ *
+ * @see udp_remove()
+ */
+struct udp_pcb *
+udp_new(void)
+{
+  struct udp_pcb *pcb;
+  pcb = (struct udp_pcb *)memp_malloc(MEMP_UDP_PCB);
+  /* could allocate UDP PCB? */
+  if (pcb != NULL) {
+    /* UDP Lite: by initializing to all zeroes, chksum_len is set to 0
+     * which means checksum is generated over the whole datagram per default
+     * (recommended as default by RFC 3828). */
+    /* initialize PCB to all zeroes */
+    memset(pcb, 0, sizeof(struct udp_pcb));
+    pcb->ttl = UDP_TTL;
+  }
+  return pcb;
+}
+
+#if UDP_DEBUG
+/**
+ * Print UDP header information for debug purposes.
+ *
+ * @param udphdr pointer to the udp header in memory.
+ */
+void
+udp_debug_print(struct udp_hdr *udphdr)
+{
+  LWIP_DEBUGF(UDP_DEBUG, ("UDP header:\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("|     %5"U16_F"     |     %5"U16_F"     | (src port, dest port)\n",
+                          ntohs(udphdr->src), ntohs(udphdr->dest)));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("|     %5"U16_F"     |     0x%04"X16_F"    | (len, chksum)\n",
+                          ntohs(udphdr->len), ntohs(udphdr->chksum)));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+}
+#endif /* UDP_DEBUG */
+
+#endif /* LWIP_UDP */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/autoip.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/autoip.h
new file mode 100644
index 0000000..23c264a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/autoip.h
@@ -0,0 +1,119 @@
+/**
+ * @file
+ *
+ * AutoIP Automatic LinkLocal IP Configuration
+ */
+
+/*
+ *
+ * Copyright (c) 2007 Dominik Spies 
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Dominik Spies 
+ *
+ * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform
+ * with RFC 3927.
+ *
+ *
+ * Please coordinate changes and requests with Dominik Spies
+ * 
+ */
+ 
+#ifndef __LWIP_AUTOIP_H__
+#define __LWIP_AUTOIP_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_AUTOIP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+#include "netif/etharp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* AutoIP Timing */
+#define AUTOIP_TMR_INTERVAL      100
+#define AUTOIP_TICKS_PER_SECOND (1000 / AUTOIP_TMR_INTERVAL)
+
+/* RFC 3927 Constants */
+#define PROBE_WAIT               1   /* second   (initial random delay)                 */
+#define PROBE_MIN                1   /* second   (minimum delay till repeated probe)    */
+#define PROBE_MAX                2   /* seconds  (maximum delay till repeated probe)    */
+#define PROBE_NUM                3   /*          (number of probe packets)              */
+#define ANNOUNCE_NUM             2   /*          (number of announcement packets)       */
+#define ANNOUNCE_INTERVAL        2   /* seconds  (time between announcement packets)    */
+#define ANNOUNCE_WAIT            2   /* seconds  (delay before announcing)              */
+#define MAX_CONFLICTS            10  /*          (max conflicts before rate limiting)   */
+#define RATE_LIMIT_INTERVAL      60  /* seconds  (delay between successive attempts)    */
+#define DEFEND_INTERVAL          10  /* seconds  (min. wait between defensive ARPs)     */
+
+/* AutoIP client states */
+#define AUTOIP_STATE_OFF         0
+#define AUTOIP_STATE_PROBING     1
+#define AUTOIP_STATE_ANNOUNCING  2
+#define AUTOIP_STATE_BOUND       3
+
+struct autoip
+{
+  ip_addr_t llipaddr;       /* the currently selected, probed, announced or used LL IP-Address */
+  u8_t state;               /* current AutoIP state machine state */
+  u8_t sent_num;            /* sent number of probes or announces, dependent on state */
+  u16_t ttw;                /* ticks to wait, tick is AUTOIP_TMR_INTERVAL long */
+  u8_t lastconflict;        /* ticks until a conflict can be solved by defending */
+  u8_t tried_llipaddr;      /* total number of probed/used Link Local IP-Addresses */
+};
+
+
+/** Init srand, has to be called before entering mainloop */
+void autoip_init(void);
+
+/** Set a struct autoip allocated by the application to work with */
+void autoip_set_struct(struct netif *netif, struct autoip *autoip);
+
+/** Start AutoIP client */
+err_t autoip_start(struct netif *netif);
+
+/** Stop AutoIP client */
+err_t autoip_stop(struct netif *netif);
+
+/** Handles every incoming ARP Packet, called by etharp_arp_input */
+void autoip_arp_reply(struct netif *netif, struct etharp_hdr *hdr);
+
+/** Has to be called in loop every AUTOIP_TMR_INTERVAL milliseconds */
+void autoip_tmr(void);
+
+/** Handle a possible change in the network configuration */
+void autoip_network_changed(struct netif *netif);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_AUTOIP */
+
+#endif /* __LWIP_AUTOIP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/icmp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/icmp.h
new file mode 100644
index 0000000..d47a7d8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/icmp.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ICMP_H__
+#define __LWIP_ICMP_H__
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ICMP_ER   0    /* echo reply */
+#define ICMP_DUR  3    /* destination unreachable */
+#define ICMP_SQ   4    /* source quench */
+#define ICMP_RD   5    /* redirect */
+#define ICMP_ECHO 8    /* echo */
+#define ICMP_TE  11    /* time exceeded */
+#define ICMP_PP  12    /* parameter problem */
+#define ICMP_TS  13    /* timestamp */
+#define ICMP_TSR 14    /* timestamp reply */
+#define ICMP_IRQ 15    /* information request */
+#define ICMP_IR  16    /* information reply */
+
+enum icmp_dur_type {
+  ICMP_DUR_NET   = 0,  /* net unreachable */
+  ICMP_DUR_HOST  = 1,  /* host unreachable */
+  ICMP_DUR_PROTO = 2,  /* protocol unreachable */
+  ICMP_DUR_PORT  = 3,  /* port unreachable */
+  ICMP_DUR_FRAG  = 4,  /* fragmentation needed and DF set */
+  ICMP_DUR_SR    = 5   /* source route failed */
+};
+
+enum icmp_te_type {
+  ICMP_TE_TTL  = 0,    /* time to live exceeded in transit */
+  ICMP_TE_FRAG = 1     /* fragment reassembly time exceeded */
+};
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+/** This is the standard ICMP header only that the u32_t data
+ *  is splitted to two u16_t like ICMP echo needs it.
+ *  This header is also used for other ICMP types that do not
+ *  use the data part.
+ */
+PACK_STRUCT_BEGIN
+struct icmp_echo_hdr {
+  PACK_STRUCT_FIELD(u8_t type);
+  PACK_STRUCT_FIELD(u8_t code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u16_t id);
+  PACK_STRUCT_FIELD(u16_t seqno);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define ICMPH_TYPE(hdr) ((hdr)->type)
+#define ICMPH_CODE(hdr) ((hdr)->code)
+
+/** Combines type and code to an u16_t */
+#define ICMPH_TYPE_SET(hdr, t) ((hdr)->type = (t))
+#define ICMPH_CODE_SET(hdr, c) ((hdr)->code = (c))
+
+
+#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */
+
+void icmp_input(struct pbuf *p, struct netif *inp);
+void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
+void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
+
+#endif /* LWIP_ICMP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_ICMP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/igmp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/igmp.h
new file mode 100644
index 0000000..8aabac2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/igmp.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2002 CITEL Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS''
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is a contribution to the lwIP TCP/IP stack.
+ * The Swedish Institute of Computer Science and Adam Dunkels
+ * are specifically granted permission to redistribute this
+ * source code.
+*/
+
+#ifndef __LWIP_IGMP_H__
+#define __LWIP_IGMP_H__
+
+#include "lwip/opt.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/pbuf.h"
+
+#if LWIP_IGMP /* don't build if not configured for use in lwipopts.h */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* IGMP timer */
+#define IGMP_TMR_INTERVAL              100 /* Milliseconds */
+#define IGMP_V1_DELAYING_MEMBER_TMR   (1000/IGMP_TMR_INTERVAL)
+#define IGMP_JOIN_DELAYING_MEMBER_TMR (500 /IGMP_TMR_INTERVAL)
+
+/* MAC Filter Actions, these are passed to a netif's
+ * igmp_mac_filter callback function. */
+#define IGMP_DEL_MAC_FILTER            0
+#define IGMP_ADD_MAC_FILTER            1
+
+
+/**
+ * igmp group structure - there is
+ * a list of groups for each interface
+ * these should really be linked from the interface, but
+ * if we keep them separate we will not affect the lwip original code
+ * too much
+ * 
+ * There will be a group for the all systems group address but this 
+ * will not run the state machine as it is used to kick off reports
+ * from all the other groups
+ */
+struct igmp_group {
+  /** next link */
+  struct igmp_group *next;
+  /** interface on which the group is active */
+  struct netif      *netif;
+  /** multicast address */
+  ip_addr_t          group_address;
+  /** signifies we were the last person to report */
+  u8_t               last_reporter_flag;
+  /** current state of the group */
+  u8_t               group_state;
+  /** timer for reporting, negative is OFF */
+  u16_t              timer;
+  /** counter of simultaneous uses */
+  u8_t               use;
+};
+
+/*  Prototypes */
+void   igmp_init(void);
+err_t  igmp_start(struct netif *netif);
+err_t  igmp_stop(struct netif *netif);
+void   igmp_report_groups(struct netif *netif);
+struct igmp_group *igmp_lookfor_group(struct netif *ifp, ip_addr_t *addr);
+void   igmp_input(struct pbuf *p, struct netif *inp, ip_addr_t *dest);
+err_t  igmp_joingroup(ip_addr_t *ifaddr, ip_addr_t *groupaddr);
+err_t  igmp_leavegroup(ip_addr_t *ifaddr, ip_addr_t *groupaddr);
+void   igmp_tmr(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IGMP */
+
+#endif /* __LWIP_IGMP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/inet.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/inet.h
new file mode 100644
index 0000000..7bff49b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/inet.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_INET_H__
+#define __LWIP_INET_H__
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** For compatibility with BSD code */
+struct in_addr {
+  u32_t s_addr;
+};
+
+/** 255.255.255.255 */
+#define INADDR_NONE         IPADDR_NONE
+/** 127.0.0.1 */
+#define INADDR_LOOPBACK     IPADDR_LOOPBACK
+/** 0.0.0.0 */
+#define INADDR_ANY          IPADDR_ANY
+/** 255.255.255.255 */
+#define INADDR_BROADCAST    IPADDR_BROADCAST
+
+/* Definitions of the bits in an Internet address integer.
+
+   On subnets, host and network parts are found according to
+   the subnet mask, not these masks.  */
+#define IN_CLASSA(a)        IP_CLASSA(a)
+#define IN_CLASSA_NET       IP_CLASSA_NET
+#define IN_CLASSA_NSHIFT    IP_CLASSA_NSHIFT
+#define IN_CLASSA_HOST      IP_CLASSA_HOST
+#define IN_CLASSA_MAX       IP_CLASSA_MAX
+
+#define IN_CLASSB(b)        IP_CLASSB(b)
+#define IN_CLASSB_NET       IP_CLASSB_NET
+#define IN_CLASSB_NSHIFT    IP_CLASSB_NSHIFT
+#define IN_CLASSB_HOST      IP_CLASSB_HOST
+#define IN_CLASSB_MAX       IP_CLASSB_MAX
+
+#define IN_CLASSC(c)        IP_CLASSC(c)
+#define IN_CLASSC_NET       IP_CLASSC_NET
+#define IN_CLASSC_NSHIFT    IP_CLASSC_NSHIFT
+#define IN_CLASSC_HOST      IP_CLASSC_HOST
+#define IN_CLASSC_MAX       IP_CLASSC_MAX
+
+#define IN_CLASSD(d)        IP_CLASSD(d)
+#define IN_CLASSD_NET       IP_CLASSD_NET     /* These ones aren't really */
+#define IN_CLASSD_NSHIFT    IP_CLASSD_NSHIFT  /*   net and host fields, but */
+#define IN_CLASSD_HOST      IP_CLASSD_HOST    /*   routing needn't know. */
+#define IN_CLASSD_MAX       IP_CLASSD_MAX
+
+#define IN_MULTICAST(a)     IP_MULTICAST(a)
+
+#define IN_EXPERIMENTAL(a)  IP_EXPERIMENTAL(a)
+#define IN_BADCLASS(a)      IP_BADCLASS(a)
+
+#define IN_LOOPBACKNET      IP_LOOPBACKNET
+
+#define inet_addr_from_ipaddr(target_inaddr, source_ipaddr) ((target_inaddr)->s_addr = ip4_addr_get_u32(source_ipaddr))
+#define inet_addr_to_ipaddr(target_ipaddr, source_inaddr)   (ip4_addr_set_u32(target_ipaddr, (source_inaddr)->s_addr))
+/* ATTENTION: the next define only works because both s_addr and ip_addr_t are an u32_t effectively! */
+#define inet_addr_to_ipaddr_p(target_ipaddr_p, source_inaddr)   ((target_ipaddr_p) = (ip_addr_t*)&((source_inaddr)->s_addr))
+
+/* directly map this to the lwip internal functions */
+#define inet_addr(cp)         ipaddr_addr(cp)
+#define inet_aton(cp, addr)   ipaddr_aton(cp, (ip_addr_t*)addr)
+#define inet_ntoa(addr)       ipaddr_ntoa((ip_addr_t*)&(addr))
+#define inet_ntoa_r(addr, buf, buflen) ipaddr_ntoa_r((ip_addr_t*)&(addr), buf, buflen)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_INET_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/inet_chksum.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/inet_chksum.h
new file mode 100644
index 0000000..79a2d90
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/inet_chksum.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_INET_CHKSUM_H__
+#define __LWIP_INET_CHKSUM_H__
+
+#include "lwip/opt.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+/** Swap the bytes in an u16_t: much like htons() for little-endian */
+#ifndef SWAP_BYTES_IN_WORD
+#if LWIP_PLATFORM_BYTESWAP && (BYTE_ORDER == LITTLE_ENDIAN)
+/* little endian and PLATFORM_BYTESWAP defined */
+#define SWAP_BYTES_IN_WORD(w) LWIP_PLATFORM_HTONS(w)
+#else /* LWIP_PLATFORM_BYTESWAP && (BYTE_ORDER == LITTLE_ENDIAN) */
+/* can't use htons on big endian (or PLATFORM_BYTESWAP not defined)... */
+#define SWAP_BYTES_IN_WORD(w) (((w) & 0xff) << 8) | (((w) & 0xff00) >> 8)
+#endif /* LWIP_PLATFORM_BYTESWAP && (BYTE_ORDER == LITTLE_ENDIAN)*/
+#endif /* SWAP_BYTES_IN_WORD */
+
+/** Split an u32_t in two u16_ts and add them up */
+#ifndef FOLD_U32T
+#define FOLD_U32T(u)          (((u) >> 16) + ((u) & 0x0000ffffUL))
+#endif
+
+#if LWIP_CHECKSUM_ON_COPY
+/** Function-like macro: same as MEMCPY but returns the checksum of copied data
+    as u16_t */
+#ifndef LWIP_CHKSUM_COPY
+#define LWIP_CHKSUM_COPY(dst, src, len) lwip_chksum_copy(dst, src, len)
+#ifndef LWIP_CHKSUM_COPY_ALGORITHM
+#define LWIP_CHKSUM_COPY_ALGORITHM 1
+#endif /* LWIP_CHKSUM_COPY_ALGORITHM */
+#endif /* LWIP_CHKSUM_COPY */
+#else /* LWIP_CHECKSUM_ON_COPY */
+#define LWIP_CHKSUM_COPY_ALGORITHM 0
+#endif /* LWIP_CHECKSUM_ON_COPY */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+u16_t inet_chksum(void *dataptr, u16_t len);
+u16_t inet_chksum_pbuf(struct pbuf *p);
+u16_t inet_chksum_pseudo(struct pbuf *p,
+       ip_addr_t *src, ip_addr_t *dest,
+       u8_t proto, u16_t proto_len);
+u16_t inet_chksum_pseudo_partial(struct pbuf *p,
+       ip_addr_t *src, ip_addr_t *dest,
+       u8_t proto, u16_t proto_len, u16_t chksum_len);
+#if LWIP_CHKSUM_COPY_ALGORITHM
+u16_t lwip_chksum_copy(void *dst, const void *src, u16_t len);
+#endif /* LWIP_CHKSUM_COPY_ALGORITHM */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_INET_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/ip.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/ip.h
new file mode 100644
index 0000000..74f501d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/ip.h
@@ -0,0 +1,213 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_H__
+#define __LWIP_IP_H__
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Currently, the function ip_output_if_opt() is only used with IGMP */
+#define IP_OPTIONS_SEND   LWIP_IGMP
+
+#define IP_HLEN 20
+
+#define IP_PROTO_ICMP    1
+#define IP_PROTO_IGMP    2
+#define IP_PROTO_UDP     17
+#define IP_PROTO_UDPLITE 136
+#define IP_PROTO_TCP     6
+
+/* This is passed as the destination address to ip_output_if (not
+   to ip_output), meaning that an IP header already is constructed
+   in the pbuf. This is used when TCP retransmits. */
+#ifdef IP_HDRINCL
+#undef IP_HDRINCL
+#endif /* IP_HDRINCL */
+#define IP_HDRINCL  NULL
+
+#if LWIP_NETIF_HWADDRHINT
+#define IP_PCB_ADDRHINT ;u8_t addr_hint
+#else
+#define IP_PCB_ADDRHINT
+#endif /* LWIP_NETIF_HWADDRHINT */
+
+/* This is the common part of all PCB types. It needs to be at the
+   beginning of a PCB type definition. It is located here so that
+   changes to this common part are made in one location instead of
+   having to change all PCB structs. */
+#define IP_PCB \
+  /* ip addresses in network byte order */ \
+  ip_addr_t local_ip; \
+  ip_addr_t remote_ip; \
+   /* Socket options */  \
+  u8_t so_options;      \
+   /* Type Of Service */ \
+  u8_t tos;              \
+  /* Time To Live */     \
+  u8_t ttl               \
+  /* link layer address resolution hint */ \
+  IP_PCB_ADDRHINT
+
+struct ip_pcb {
+/* Common members of all PCB types */
+  IP_PCB;
+};
+
+/*
+ * Option flags per-socket. These are the same like SO_XXX.
+ */
+/*#define SOF_DEBUG       (u8_t)0x01U     Unimplemented: turn on debugging info recording */
+#define SOF_ACCEPTCONN    (u8_t)0x02U  /* socket has had listen() */
+#define SOF_REUSEADDR     (u8_t)0x04U  /* allow local address reuse */
+#define SOF_KEEPALIVE     (u8_t)0x08U  /* keep connections alive */
+/*#define SOF_DONTROUTE   (u8_t)0x10U     Unimplemented: just use interface addresses */
+#define SOF_BROADCAST     (u8_t)0x20U  /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */
+/*#define SOF_USELOOPBACK (u8_t)0x40U     Unimplemented: bypass hardware when possible */
+#define SOF_LINGER        (u8_t)0x80U  /* linger on close if data present */
+/*#define SOF_OOBINLINE   (u16_t)0x0100U     Unimplemented: leave received OOB data in line */
+/*#define SOF_REUSEPORT   (u16_t)0x0200U     Unimplemented: allow local address & port reuse */
+
+/* These flags are inherited (e.g. from a listen-pcb to a connection-pcb): */
+#define SOF_INHERITED   (SOF_REUSEADDR|SOF_KEEPALIVE|SOF_LINGER/*|SOF_DEBUG|SOF_DONTROUTE|SOF_OOBINLINE*/)
+
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_hdr {
+  /* version / header length / type of service */
+  PACK_STRUCT_FIELD(u16_t _v_hl_tos);
+  /* total length */
+  PACK_STRUCT_FIELD(u16_t _len);
+  /* identification */
+  PACK_STRUCT_FIELD(u16_t _id);
+  /* fragment offset field */
+  PACK_STRUCT_FIELD(u16_t _offset);
+#define IP_RF 0x8000U        /* reserved fragment flag */
+#define IP_DF 0x4000U        /* dont fragment flag */
+#define IP_MF 0x2000U        /* more fragments flag */
+#define IP_OFFMASK 0x1fffU   /* mask for fragmenting bits */
+  /* time to live */
+  PACK_STRUCT_FIELD(u8_t _ttl);
+  /* protocol*/
+  PACK_STRUCT_FIELD(u8_t _proto);
+  /* checksum */
+  PACK_STRUCT_FIELD(u16_t _chksum);
+  /* source and destination IP addresses */
+  PACK_STRUCT_FIELD(ip_addr_p_t src);
+  PACK_STRUCT_FIELD(ip_addr_p_t dest); 
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define IPH_V(hdr)  (ntohs((hdr)->_v_hl_tos) >> 12)
+#define IPH_HL(hdr) ((ntohs((hdr)->_v_hl_tos) >> 8) & 0x0f)
+#define IPH_TOS(hdr) (ntohs((hdr)->_v_hl_tos) & 0xff)
+#define IPH_LEN(hdr) ((hdr)->_len)
+#define IPH_ID(hdr) ((hdr)->_id)
+#define IPH_OFFSET(hdr) ((hdr)->_offset)
+#define IPH_TTL(hdr) ((hdr)->_ttl)
+#define IPH_PROTO(hdr) ((hdr)->_proto)
+#define IPH_CHKSUM(hdr) ((hdr)->_chksum)
+
+#define IPH_VHLTOS_SET(hdr, v, hl, tos) (hdr)->_v_hl_tos = (htons(((v) << 12) | ((hl) << 8) | (tos)))
+#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len)
+#define IPH_ID_SET(hdr, id) (hdr)->_id = (id)
+#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off)
+#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl = (u8_t)(ttl)
+#define IPH_PROTO_SET(hdr, proto) (hdr)->_proto = (u8_t)(proto)
+#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum)
+
+/** The interface that provided the packet for the current callback invocation. */
+extern struct netif *current_netif;
+/** Header of the input packet currently being processed. */
+extern const struct ip_hdr *current_header;
+/** Source IP address of current_header */
+extern ip_addr_t current_iphdr_src;
+/** Destination IP address of current_header */
+extern ip_addr_t current_iphdr_dest;
+
+#define ip_init() /* Compatibility define, not init needed. */
+struct netif *ip_route(ip_addr_t *dest);
+err_t ip_input(struct pbuf *p, struct netif *inp);
+err_t ip_output(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest,
+       u8_t ttl, u8_t tos, u8_t proto);
+err_t ip_output_if(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest,
+       u8_t ttl, u8_t tos, u8_t proto,
+       struct netif *netif);
+#if LWIP_NETIF_HWADDRHINT
+err_t ip_output_hinted(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest,
+       u8_t ttl, u8_t tos, u8_t proto, u8_t *addr_hint);
+#endif /* LWIP_NETIF_HWADDRHINT */
+#if IP_OPTIONS_SEND
+err_t ip_output_if_opt(struct pbuf *p, ip_addr_t *src, ip_addr_t *dest,
+       u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options,
+       u16_t optlen);
+#endif /* IP_OPTIONS_SEND */
+/** Get the interface that received the current packet.
+ * This function must only be called from a receive callback (udp_recv,
+ * raw_recv, tcp_accept). It will return NULL otherwise. */
+#define ip_current_netif()  (current_netif)
+/** Get the IP header of the current packet.
+ * This function must only be called from a receive callback (udp_recv,
+ * raw_recv, tcp_accept). It will return NULL otherwise. */
+#define ip_current_header() (current_header)
+/** Source IP address of current_header */
+#define ip_current_src_addr()  (¤t_iphdr_src)
+/** Destination IP address of current_header */
+#define ip_current_dest_addr() (¤t_iphdr_dest)
+
+#if IP_DEBUG
+void ip_debug_print(struct pbuf *p);
+#else
+#define ip_debug_print(p)
+#endif /* IP_DEBUG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_IP_H__ */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/ip_addr.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/ip_addr.h
new file mode 100644
index 0000000..77f84e0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/ip_addr.h
@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_ADDR_H__
+#define __LWIP_IP_ADDR_H__
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* This is the aligned version of ip_addr_t,
+   used as local variable, on the stack, etc. */
+struct ip_addr {
+  u32_t addr;
+};
+
+/* This is the packed version of ip_addr_t,
+   used in network headers that are itself packed */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_addr_packed {
+  PACK_STRUCT_FIELD(u32_t addr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** ip_addr_t uses a struct for convenience only, so that the same defines can
+ * operate both on ip_addr_t as well as on ip_addr_p_t. */
+typedef struct ip_addr ip_addr_t;
+typedef struct ip_addr_packed ip_addr_p_t;
+
+/*
+ * struct ipaddr2 is used in the definition of the ARP packet format in
+ * order to support compilers that don't have structure packing.
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_addr2 {
+  PACK_STRUCT_FIELD(u16_t addrw[2]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/* Forward declaration to not include netif.h */
+struct netif;
+
+extern const ip_addr_t ip_addr_any;
+extern const ip_addr_t ip_addr_broadcast;
+
+/** IP_ADDR_ can be used as a fixed IP address
+ *  for the wildcard and the broadcast address
+ */
+#define IP_ADDR_ANY         ((ip_addr_t *)&ip_addr_any)
+#define IP_ADDR_BROADCAST   ((ip_addr_t *)&ip_addr_broadcast)
+
+/** 255.255.255.255 */
+#define IPADDR_NONE         ((u32_t)0xffffffffUL)
+/** 127.0.0.1 */
+#define IPADDR_LOOPBACK     ((u32_t)0x7f000001UL)
+/** 0.0.0.0 */
+#define IPADDR_ANY          ((u32_t)0x00000000UL)
+/** 255.255.255.255 */
+#define IPADDR_BROADCAST    ((u32_t)0xffffffffUL)
+
+/* Definitions of the bits in an Internet address integer.
+
+   On subnets, host and network parts are found according to
+   the subnet mask, not these masks.  */
+#define IP_CLASSA(a)        ((((u32_t)(a)) & 0x80000000UL) == 0)
+#define IP_CLASSA_NET       0xff000000
+#define IP_CLASSA_NSHIFT    24
+#define IP_CLASSA_HOST      (0xffffffff & ~IP_CLASSA_NET)
+#define IP_CLASSA_MAX       128
+
+#define IP_CLASSB(a)        ((((u32_t)(a)) & 0xc0000000UL) == 0x80000000UL)
+#define IP_CLASSB_NET       0xffff0000
+#define IP_CLASSB_NSHIFT    16
+#define IP_CLASSB_HOST      (0xffffffff & ~IP_CLASSB_NET)
+#define IP_CLASSB_MAX       65536
+
+#define IP_CLASSC(a)        ((((u32_t)(a)) & 0xe0000000UL) == 0xc0000000UL)
+#define IP_CLASSC_NET       0xffffff00
+#define IP_CLASSC_NSHIFT    8
+#define IP_CLASSC_HOST      (0xffffffff & ~IP_CLASSC_NET)
+
+#define IP_CLASSD(a)        (((u32_t)(a) & 0xf0000000UL) == 0xe0000000UL)
+#define IP_CLASSD_NET       0xf0000000          /* These ones aren't really */
+#define IP_CLASSD_NSHIFT    28                  /*   net and host fields, but */
+#define IP_CLASSD_HOST      0x0fffffff          /*   routing needn't know. */
+#define IP_MULTICAST(a)     IP_CLASSD(a)
+
+#define IP_EXPERIMENTAL(a)  (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL)
+#define IP_BADCLASS(a)      (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL)
+
+#define IP_LOOPBACKNET      127                 /* official! */
+
+
+#if BYTE_ORDER == BIG_ENDIAN
+/** Set an IP address given by the four byte-parts */
+#define IP4_ADDR(ipaddr, a,b,c,d) \
+        (ipaddr)->addr = ((u32_t)((a) & 0xff) << 24) | \
+                         ((u32_t)((b) & 0xff) << 16) | \
+                         ((u32_t)((c) & 0xff) << 8)  | \
+                          (u32_t)((d) & 0xff)
+#else
+/** Set an IP address given by the four byte-parts.
+    Little-endian version that prevents the use of htonl. */
+#define IP4_ADDR(ipaddr, a,b,c,d) \
+        (ipaddr)->addr = ((u32_t)((d) & 0xff) << 24) | \
+                         ((u32_t)((c) & 0xff) << 16) | \
+                         ((u32_t)((b) & 0xff) << 8)  | \
+                          (u32_t)((a) & 0xff)
+#endif
+
+/** MEMCPY-like copying of IP addresses where addresses are known to be
+ * 16-bit-aligned if the port is correctly configured (so a port could define
+ * this to copying 2 u16_t's) - no NULL-pointer-checking needed. */
+#ifndef IPADDR2_COPY
+#define IPADDR2_COPY(dest, src) SMEMCPY(dest, src, sizeof(ip_addr_t))
+#endif
+
+/** Copy IP address - faster than ip_addr_set: no NULL check */
+#define ip_addr_copy(dest, src) ((dest).addr = (src).addr)
+/** Safely copy one IP address to another (src may be NULL) */
+#define ip_addr_set(dest, src) ((dest)->addr = \
+                                    ((src) == NULL ? 0 : \
+                                    (src)->addr))
+/** Set complete address to zero */
+#define ip_addr_set_zero(ipaddr)      ((ipaddr)->addr = 0)
+/** Set address to IPADDR_ANY (no need for htonl()) */
+#define ip_addr_set_any(ipaddr)       ((ipaddr)->addr = IPADDR_ANY)
+/** Set address to loopback address */
+#define ip_addr_set_loopback(ipaddr)  ((ipaddr)->addr = PP_HTONL(IPADDR_LOOPBACK))
+/** Safely copy one IP address to another and change byte order
+ * from host- to network-order. */
+#define ip_addr_set_hton(dest, src) ((dest)->addr = \
+                               ((src) == NULL ? 0:\
+                               htonl((src)->addr)))
+/** IPv4 only: set the IP address given as an u32_t */
+#define ip4_addr_set_u32(dest_ipaddr, src_u32) ((dest_ipaddr)->addr = (src_u32))
+/** IPv4 only: get the IP address as an u32_t */
+#define ip4_addr_get_u32(src_ipaddr) ((src_ipaddr)->addr)
+
+/** Get the network address by combining host address with netmask */
+#define ip_addr_get_network(target, host, netmask) ((target)->addr = ((host)->addr) & ((netmask)->addr))
+
+/**
+ * Determine if two address are on the same network.
+ *
+ * @arg addr1 IP address 1
+ * @arg addr2 IP address 2
+ * @arg mask network identifier mask
+ * @return !0 if the network identifiers of both address match
+ */
+#define ip_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \
+                                              (mask)->addr) == \
+                                             ((addr2)->addr & \
+                                              (mask)->addr))
+#define ip_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr)
+
+#define ip_addr_isany(addr1) ((addr1) == NULL || (addr1)->addr == IPADDR_ANY)
+
+#define ip_addr_isbroadcast(ipaddr, netif) ip4_addr_isbroadcast((ipaddr)->addr, (netif))
+u8_t ip4_addr_isbroadcast(u32_t addr, const struct netif *netif);
+
+#define ip_addr_netmask_valid(netmask) ip4_addr_netmask_valid((netmask)->addr)
+u8_t ip4_addr_netmask_valid(u32_t netmask);
+
+#define ip_addr_ismulticast(addr1) (((addr1)->addr & PP_HTONL(0xf0000000UL)) == PP_HTONL(0xe0000000UL))
+
+#define ip_addr_islinklocal(addr1) (((addr1)->addr & PP_HTONL(0xffff0000UL)) == PP_HTONL(0xa9fe0000UL))
+
+#define ip_addr_debug_print(debug, ipaddr) \
+  LWIP_DEBUGF(debug, ("%"U16_F".%"U16_F".%"U16_F".%"U16_F,             \
+                      ipaddr != NULL ? ip4_addr1_16(ipaddr) : 0,       \
+                      ipaddr != NULL ? ip4_addr2_16(ipaddr) : 0,       \
+                      ipaddr != NULL ? ip4_addr3_16(ipaddr) : 0,       \
+                      ipaddr != NULL ? ip4_addr4_16(ipaddr) : 0))
+
+/* Get one byte from the 4-byte address */
+#define ip4_addr1(ipaddr) (((u8_t*)(ipaddr))[0])
+#define ip4_addr2(ipaddr) (((u8_t*)(ipaddr))[1])
+#define ip4_addr3(ipaddr) (((u8_t*)(ipaddr))[2])
+#define ip4_addr4(ipaddr) (((u8_t*)(ipaddr))[3])
+/* These are cast to u16_t, with the intent that they are often arguments
+ * to printf using the U16_F format from cc.h. */
+#define ip4_addr1_16(ipaddr) ((u16_t)ip4_addr1(ipaddr))
+#define ip4_addr2_16(ipaddr) ((u16_t)ip4_addr2(ipaddr))
+#define ip4_addr3_16(ipaddr) ((u16_t)ip4_addr3(ipaddr))
+#define ip4_addr4_16(ipaddr) ((u16_t)ip4_addr4(ipaddr))
+
+/** For backwards compatibility */
+#define ip_ntoa(ipaddr)  ipaddr_ntoa(ipaddr)
+
+u32_t ipaddr_addr(const char *cp);
+int ipaddr_aton(const char *cp, ip_addr_t *addr);
+/** returns ptr to static buffer; not reentrant! */
+char *ipaddr_ntoa(const ip_addr_t *addr);
+char *ipaddr_ntoa_r(const ip_addr_t *addr, char *buf, int buflen);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_IP_ADDR_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/ip_frag.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/ip_frag.h
new file mode 100644
index 0000000..77b5eb1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv4/lwip/ip_frag.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Jani Monoses 
+ *
+ */
+
+#ifndef __LWIP_IP_FRAG_H__
+#define __LWIP_IP_FRAG_H__
+
+#include "lwip/opt.h"
+#include "lwip/err.h"
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/ip_addr.h"
+#include "lwip/ip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if IP_REASSEMBLY
+/* The IP reassembly timer interval in milliseconds. */
+#define IP_TMR_INTERVAL 1000
+
+/* IP reassembly helper struct.
+ * This is exported because memp needs to know the size.
+ */
+struct ip_reassdata {
+  struct ip_reassdata *next;
+  struct pbuf *p;
+  struct ip_hdr iphdr;
+  u16_t datagram_len;
+  u8_t flags;
+  u8_t timer;
+};
+
+void ip_reass_init(void);
+void ip_reass_tmr(void);
+struct pbuf * ip_reass(struct pbuf *p);
+#endif /* IP_REASSEMBLY */
+
+#if IP_FRAG
+#if !IP_FRAG_USES_STATIC_BUF && !LWIP_NETIF_TX_SINGLE_PBUF
+/** A custom pbuf that holds a reference to another pbuf, which is freed
+ * when this custom pbuf is freed. This is used to create a custom PBUF_REF
+ * that points into the original pbuf. */
+struct pbuf_custom_ref {
+  /** 'base class' */
+  struct pbuf_custom pc;
+  /** pointer to the original pbuf that is referenced */
+  struct pbuf *original;
+};
+#endif /* !IP_FRAG_USES_STATIC_BUF && !LWIP_NETIF_TX_SINGLE_PBUF */
+
+err_t ip_frag(struct pbuf *p, struct netif *netif, ip_addr_t *dest);
+#endif /* IP_FRAG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_IP_FRAG_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/icmp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/icmp.h
new file mode 100644
index 0000000..87e9ffd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/icmp.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ICMP_H__
+#define __LWIP_ICMP_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ICMP6_DUR  1
+#define ICMP6_TE   3
+#define ICMP6_ECHO 128    /* echo */
+#define ICMP6_ER   129      /* echo reply */
+
+
+enum icmp_dur_type {
+  ICMP_DUR_NET = 0,    /* net unreachable */
+  ICMP_DUR_HOST = 1,   /* host unreachable */
+  ICMP_DUR_PROTO = 2,  /* protocol unreachable */
+  ICMP_DUR_PORT = 3,   /* port unreachable */
+  ICMP_DUR_FRAG = 4,   /* fragmentation needed and DF set */
+  ICMP_DUR_SR = 5      /* source route failed */
+};
+
+enum icmp_te_type {
+  ICMP_TE_TTL = 0,     /* time to live exceeded in transit */
+  ICMP_TE_FRAG = 1     /* fragment reassembly time exceeded */
+};
+
+void icmp_input(struct pbuf *p, struct netif *inp);
+
+void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
+void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
+
+struct icmp_echo_hdr {
+  u8_t type;
+  u8_t icode;
+  u16_t chksum;
+  u16_t id;
+  u16_t seqno;
+};
+
+struct icmp_dur_hdr {
+  u8_t type;
+  u8_t icode;
+  u16_t chksum;
+  u32_t unused;
+};
+
+struct icmp_te_hdr {
+  u8_t type;
+  u8_t icode;
+  u16_t chksum;
+  u32_t unused;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_ICMP */
+
+#endif /* __LWIP_ICMP_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/inet.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/inet.h
new file mode 100644
index 0000000..de1a0b6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/inet.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_INET_H__
+#define __LWIP_INET_H__
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+u16_t inet_chksum(void *data, u16_t len);
+u16_t inet_chksum_pbuf(struct pbuf *p);
+u16_t inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u32_t proto_len);
+
+u32_t inet_addr(const char *cp);
+s8_t inet_aton(const char *cp, struct in_addr *addr);
+
+#ifndef _MACHINE_ENDIAN_H_
+#ifndef _NETINET_IN_H
+#ifndef _LINUX_BYTEORDER_GENERIC_H
+u16_t htons(u16_t n);
+u16_t ntohs(u16_t n);
+u32_t htonl(u32_t n);
+u32_t ntohl(u32_t n);
+#endif /* _LINUX_BYTEORDER_GENERIC_H */
+#endif /* _NETINET_IN_H */
+#endif /* _MACHINE_ENDIAN_H_ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_INET_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/ip.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/ip.h
new file mode 100644
index 0000000..a01cfc6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/ip.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_H__
+#define __LWIP_IP_H__
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IP_HLEN 40
+
+#define IP_PROTO_ICMP    58
+#define IP_PROTO_UDP     17
+#define IP_PROTO_UDPLITE 136
+#define IP_PROTO_TCP     6
+
+/* This is passed as the destination address to ip_output_if (not
+   to ip_output), meaning that an IP header already is constructed
+   in the pbuf. This is used when TCP retransmits. */
+#ifdef IP_HDRINCL
+#undef IP_HDRINCL
+#endif /* IP_HDRINCL */
+#define IP_HDRINCL  NULL
+
+#if LWIP_NETIF_HWADDRHINT
+#define IP_PCB_ADDRHINT ;u8_t addr_hint
+#else
+#define IP_PCB_ADDRHINT
+#endif /* LWIP_NETIF_HWADDRHINT */
+
+/* This is the common part of all PCB types. It needs to be at the
+   beginning of a PCB type definition. It is located here so that
+   changes to this common part are made in one location instead of
+   having to change all PCB structs. */
+#define IP_PCB struct ip_addr local_ip; \
+  struct ip_addr remote_ip; \
+   /* Socket options */  \
+  u16_t so_options;      \
+   /* Type Of Service */ \
+  u8_t tos;              \
+  /* Time To Live */     \
+  u8_t ttl;              \
+  /* link layer address resolution hint */ \
+  IP_PCB_ADDRHINT
+
+
+/* The IPv6 header. */
+struct ip_hdr {
+#if BYTE_ORDER == LITTLE_ENDIAN
+  u8_t tclass1:4, v:4;
+  u8_t flow1:4, tclass2:4;  
+#else
+  u8_t v:4, tclass1:4;
+  u8_t tclass2:8, flow1:4;
+#endif
+  u16_t flow2;
+  u16_t len;                /* payload length */
+  u8_t nexthdr;             /* next header */
+  u8_t hoplim;              /* hop limit (TTL) */
+  struct ip_addr src, dest;          /* source and destination IP addresses */
+};
+
+#define IPH_PROTO(hdr) (iphdr->nexthdr)
+
+void ip_init(void);
+
+#include "lwip/netif.h"
+
+struct netif *ip_route(struct ip_addr *dest);
+
+void ip_input(struct pbuf *p, struct netif *inp);
+
+/* source and destination addresses in network byte order, please */
+err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+         u8_t ttl, u8_t proto);
+
+err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+      u8_t ttl, u8_t proto,
+      struct netif *netif);
+
+#define ip_current_netif() NULL
+#define ip_current_header() NULL
+
+#if IP_DEBUG
+void ip_debug_print(struct pbuf *p);
+#endif /* IP_DEBUG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_IP_H__ */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/ip_addr.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/ip_addr.h
new file mode 100644
index 0000000..b2d8ae5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/ipv6/lwip/ip_addr.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_ADDR_H__
+#define __LWIP_IP_ADDR_H__
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IP_ADDR_ANY 0
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+ struct ip_addr {
+  PACK_STRUCT_FIELD(u32_t addr[4]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/*
+ * struct ipaddr2 is used in the definition of the ARP packet format in
+ * order to support compilers that don't have structure packing.
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_addr2 {
+  PACK_STRUCT_FIELD(u16_t addrw[2]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define IP6_ADDR(ipaddr, a,b,c,d,e,f,g,h) do { (ipaddr)->addr[0] = htonl((u32_t)((a & 0xffff) << 16) | (b & 0xffff)); \
+                                               (ipaddr)->addr[1] = htonl(((c & 0xffff) << 16) | (d & 0xffff)); \
+                                               (ipaddr)->addr[2] = htonl(((e & 0xffff) << 16) | (f & 0xffff)); \
+                                               (ipaddr)->addr[3] = htonl(((g & 0xffff) << 16) | (h & 0xffff)); } while(0)
+
+u8_t ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2,
+        struct ip_addr *mask);
+u8_t ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2);
+void ip_addr_set(struct ip_addr *dest, struct ip_addr *src);
+u8_t ip_addr_isany(struct ip_addr *addr);
+
+#define ip_addr_debug_print(debug, ipaddr) \
+        LWIP_DEBUGF(debug, ("%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F"\n", \
+         (ntohl(ipaddr->addr[0]) >> 16) & 0xffff, \
+         ntohl(ipaddr->addr[0]) & 0xffff, \
+         (ntohl(ipaddr->addr[1]) >> 16) & 0xffff, \
+         ntohl(ipaddr->addr[1]) & 0xffff, \
+         (ntohl(ipaddr->addr[2]) >> 16) & 0xffff, \
+         ntohl(ipaddr->addr[2]) & 0xffff, \
+         (ntohl(ipaddr->addr[3]) >> 16) & 0xffff, \
+         ntohl(ipaddr->addr[3]) & 0xffff));
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_IP_ADDR_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/api.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/api.h
new file mode 100644
index 0000000..91b9e5d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/api.h
@@ -0,0 +1,284 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_API_H__
+#define __LWIP_API_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */
+
+#include  /* for size_t */
+
+#include "lwip/netbuf.h"
+#include "lwip/sys.h"
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Throughout this file, IP addresses and port numbers are expected to be in
+ * the same byte order as in the corresponding pcb.
+ */
+
+/* Flags for netconn_write (u8_t) */
+#define NETCONN_NOFLAG    0x00
+#define NETCONN_NOCOPY    0x00 /* Only for source code compatibility */
+#define NETCONN_COPY      0x01
+#define NETCONN_MORE      0x02
+#define NETCONN_DONTBLOCK 0x04
+
+/* Flags for struct netconn.flags (u8_t) */
+/** TCP: when data passed to netconn_write doesn't fit into the send buffer,
+    this temporarily stores whether to wake up the original application task
+    if data couldn't be sent in the first try. */
+#define NETCONN_FLAG_WRITE_DELAYED            0x01
+/** Should this netconn avoid blocking? */
+#define NETCONN_FLAG_NON_BLOCKING             0x02
+/** Was the last connect action a non-blocking one? */
+#define NETCONN_FLAG_IN_NONBLOCKING_CONNECT   0x04
+/** If this is set, a TCP netconn must call netconn_recved() to update
+    the TCP receive window (done automatically if not set). */
+#define NETCONN_FLAG_NO_AUTO_RECVED           0x08
+/** If a nonblocking write has been rejected before, poll_tcp needs to
+    check if the netconn is writable again */
+#define NETCONN_FLAG_CHECK_WRITESPACE         0x10
+
+
+/* Helpers to process several netconn_types by the same code */
+#define NETCONNTYPE_GROUP(t)    (t&0xF0)
+#define NETCONNTYPE_DATAGRAM(t) (t&0xE0)
+
+/** Protocol family and type of the netconn */
+enum netconn_type {
+  NETCONN_INVALID    = 0,
+  /* NETCONN_TCP Group */
+  NETCONN_TCP        = 0x10,
+  /* NETCONN_UDP Group */
+  NETCONN_UDP        = 0x20,
+  NETCONN_UDPLITE    = 0x21,
+  NETCONN_UDPNOCHKSUM= 0x22,
+  /* NETCONN_RAW Group */
+  NETCONN_RAW        = 0x40
+};
+
+/** Current state of the netconn. Non-TCP netconns are always
+ * in state NETCONN_NONE! */
+enum netconn_state {
+  NETCONN_NONE,
+  NETCONN_WRITE,
+  NETCONN_LISTEN,
+  NETCONN_CONNECT,
+  NETCONN_CLOSE
+};
+
+/** Use to inform the callback function about changes */
+enum netconn_evt {
+  NETCONN_EVT_RCVPLUS,
+  NETCONN_EVT_RCVMINUS,
+  NETCONN_EVT_SENDPLUS,
+  NETCONN_EVT_SENDMINUS,
+  NETCONN_EVT_ERROR
+};
+
+#if LWIP_IGMP
+/** Used for netconn_join_leave_group() */
+enum netconn_igmp {
+  NETCONN_JOIN,
+  NETCONN_LEAVE
+};
+#endif /* LWIP_IGMP */
+
+/* forward-declare some structs to avoid to include their headers */
+struct ip_pcb;
+struct tcp_pcb;
+struct udp_pcb;
+struct raw_pcb;
+struct netconn;
+struct api_msg_msg;
+
+/** A callback prototype to inform about events for a netconn */
+typedef void (* netconn_callback)(struct netconn *, enum netconn_evt, u16_t len);
+
+/** A netconn descriptor */
+struct netconn {
+  /** type of the netconn (TCP, UDP or RAW) */
+  enum netconn_type type;
+  /** current state of the netconn */
+  enum netconn_state state;
+  /** the lwIP internal protocol control block */
+  union {
+    struct ip_pcb  *ip;
+    struct tcp_pcb *tcp;
+    struct udp_pcb *udp;
+    struct raw_pcb *raw;
+  } pcb;
+  /** the last error this netconn had */
+  err_t last_err;
+  /** sem that is used to synchroneously execute functions in the core context */
+  sys_sem_t op_completed;
+  /** mbox where received packets are stored until they are fetched
+      by the netconn application thread (can grow quite big) */
+  sys_mbox_t recvmbox;
+#if LWIP_TCP
+  /** mbox where new connections are stored until processed
+      by the application thread */
+  sys_mbox_t acceptmbox;
+#endif /* LWIP_TCP */
+  /** only used for socket layer */
+#if LWIP_SOCKET
+  int socket;
+#endif /* LWIP_SOCKET */
+#if LWIP_SO_RCVTIMEO
+  /** timeout to wait for new data to be received
+      (or connections to arrive for listening netconns) */
+  int recv_timeout;
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+  /** maximum amount of bytes queued in recvmbox
+      not used for TCP: adjust TCP_WND instead! */
+  int recv_bufsize;
+  /** number of bytes currently in recvmbox to be received,
+      tested against recv_bufsize to limit bytes on recvmbox
+      for UDP and RAW, used for FIONREAD */
+  s16_t recv_avail;
+#endif /* LWIP_SO_RCVBUF */
+  /** flags holding more netconn-internal state, see NETCONN_FLAG_* defines */
+  u8_t flags;
+#if LWIP_TCP
+  /** TCP: when data passed to netconn_write doesn't fit into the send buffer,
+      this temporarily stores how much is already sent. */
+  size_t write_offset;
+  /** TCP: when data passed to netconn_write doesn't fit into the send buffer,
+      this temporarily stores the message.
+      Also used during connect and close. */
+  struct api_msg_msg *current_msg;
+#endif /* LWIP_TCP */
+  /** A callback function that is informed about events for this netconn */
+  netconn_callback callback;
+};
+
+/** Register an Network connection event */
+#define API_EVENT(c,e,l) if (c->callback) {         \
+                           (*c->callback)(c, e, l); \
+                         }
+
+/** Set conn->last_err to err but don't overwrite fatal errors */
+#define NETCONN_SET_SAFE_ERR(conn, err) do { \
+  SYS_ARCH_DECL_PROTECT(lev); \
+  SYS_ARCH_PROTECT(lev); \
+  if (!ERR_IS_FATAL((conn)->last_err)) { \
+    (conn)->last_err = err; \
+  } \
+  SYS_ARCH_UNPROTECT(lev); \
+} while(0);
+
+/* Network connection functions: */
+#define netconn_new(t)                  netconn_new_with_proto_and_callback(t, 0, NULL)
+#define netconn_new_with_callback(t, c) netconn_new_with_proto_and_callback(t, 0, c)
+struct
+netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto,
+                                             netconn_callback callback);
+err_t   netconn_delete(struct netconn *conn);
+/** Get the type of a netconn (as enum netconn_type). */
+#define netconn_type(conn) (conn->type)
+
+err_t   netconn_getaddr(struct netconn *conn, ip_addr_t *addr,
+                        u16_t *port, u8_t local);
+#define netconn_peer(c,i,p) netconn_getaddr(c,i,p,0)
+#define netconn_addr(c,i,p) netconn_getaddr(c,i,p,1)
+
+err_t   netconn_bind(struct netconn *conn, ip_addr_t *addr, u16_t port);
+err_t   netconn_connect(struct netconn *conn, ip_addr_t *addr, u16_t port);
+err_t   netconn_disconnect (struct netconn *conn);
+err_t   netconn_listen_with_backlog(struct netconn *conn, u8_t backlog);
+#define netconn_listen(conn) netconn_listen_with_backlog(conn, TCP_DEFAULT_LISTEN_BACKLOG)
+err_t   netconn_accept(struct netconn *conn, struct netconn **new_conn);
+err_t   netconn_recv(struct netconn *conn, struct netbuf **new_buf);
+err_t   netconn_recv_tcp_pbuf(struct netconn *conn, struct pbuf **new_buf);
+void    netconn_recved(struct netconn *conn, u32_t length);
+err_t   netconn_sendto(struct netconn *conn, struct netbuf *buf,
+                       ip_addr_t *addr, u16_t port);
+err_t   netconn_send(struct netconn *conn, struct netbuf *buf);
+err_t   netconn_write(struct netconn *conn, const void *dataptr, size_t size,
+                      u8_t apiflags);
+err_t   netconn_close(struct netconn *conn);
+err_t   netconn_shutdown(struct netconn *conn, u8_t shut_rx, u8_t shut_tx);
+
+#if LWIP_IGMP
+err_t   netconn_join_leave_group(struct netconn *conn, ip_addr_t *multiaddr,
+                                 ip_addr_t *netif_addr, enum netconn_igmp join_or_leave);
+#endif /* LWIP_IGMP */
+#if LWIP_DNS
+err_t   netconn_gethostbyname(const char *name, ip_addr_t *addr);
+#endif /* LWIP_DNS */
+
+#define netconn_err(conn)               ((conn)->last_err)
+#define netconn_recv_bufsize(conn)      ((conn)->recv_bufsize)
+
+/** Set the blocking status of netconn calls (@todo: write/send is missing) */
+#define netconn_set_nonblocking(conn, val)  do { if(val) { \
+  (conn)->flags |= NETCONN_FLAG_NON_BLOCKING; \
+} else { \
+  (conn)->flags &= ~ NETCONN_FLAG_NON_BLOCKING; }} while(0)
+/** Get the blocking status of netconn calls (@todo: write/send is missing) */
+#define netconn_is_nonblocking(conn)        (((conn)->flags & NETCONN_FLAG_NON_BLOCKING) != 0)
+
+/** TCP: Set the no-auto-recved status of netconn calls (see NETCONN_FLAG_NO_AUTO_RECVED) */
+#define netconn_set_noautorecved(conn, val)  do { if(val) { \
+  (conn)->flags |= NETCONN_FLAG_NO_AUTO_RECVED; \
+} else { \
+  (conn)->flags &= ~ NETCONN_FLAG_NO_AUTO_RECVED; }} while(0)
+/** TCP: Get the no-auto-recved status of netconn calls (see NETCONN_FLAG_NO_AUTO_RECVED) */
+#define netconn_get_noautorecved(conn)        (((conn)->flags & NETCONN_FLAG_NO_AUTO_RECVED) != 0)
+
+#if LWIP_SO_RCVTIMEO
+/** Set the receive timeout in milliseconds */
+#define netconn_set_recvtimeout(conn, timeout)      ((conn)->recv_timeout = (timeout))
+/** Get the receive timeout in milliseconds */
+#define netconn_get_recvtimeout(conn)               ((conn)->recv_timeout)
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+/** Set the receive buffer in bytes */
+#define netconn_set_recvbufsize(conn, recvbufsize)  ((conn)->recv_bufsize = (recvbufsize))
+/** Get the receive buffer in bytes */
+#define netconn_get_recvbufsize(conn)               ((conn)->recv_bufsize)
+#endif /* LWIP_SO_RCVBUF*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_NETCONN */
+
+#endif /* __LWIP_API_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/api_msg.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/api_msg.h
new file mode 100644
index 0000000..f99d8c3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/api_msg.h
@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_API_MSG_H__
+#define __LWIP_API_MSG_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */
+
+#include  /* for size_t */
+
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+#include "lwip/sys.h"
+#include "lwip/igmp.h"
+#include "lwip/api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* For the netconn API, these values are use as a bitmask! */
+#define NETCONN_SHUT_RD   1
+#define NETCONN_SHUT_WR   2
+#define NETCONN_SHUT_RDWR (NETCONN_SHUT_RD | NETCONN_SHUT_WR)
+
+/* IP addresses and port numbers are expected to be in
+ * the same byte order as in the corresponding pcb.
+ */
+/** This struct includes everything that is necessary to execute a function
+    for a netconn in another thread context (mainly used to process netconns
+    in the tcpip_thread context to be thread safe). */
+struct api_msg_msg {
+  /** The netconn which to process - always needed: it includes the semaphore
+      which is used to block the application thread until the function finished. */
+  struct netconn *conn;
+  /** The return value of the function executed in tcpip_thread. */
+  err_t err;
+  /** Depending on the executed function, one of these union members is used */
+  union {
+    /** used for do_send */
+    struct netbuf *b;
+    /** used for do_newconn */
+    struct {
+      u8_t proto;
+    } n;
+    /** used for do_bind and do_connect */
+    struct {
+      ip_addr_t *ipaddr;
+      u16_t port;
+    } bc;
+    /** used for do_getaddr */
+    struct {
+      ip_addr_t *ipaddr;
+      u16_t *port;
+      u8_t local;
+    } ad;
+    /** used for do_write */
+    struct {
+      const void *dataptr;
+      size_t len;
+      u8_t apiflags;
+    } w;
+    /** used for do_recv */
+    struct {
+      u32_t len;
+    } r;
+    /** used for do_close (/shutdown) */
+    struct {
+      u8_t shut;
+    } sd;
+#if LWIP_IGMP
+    /** used for do_join_leave_group */
+    struct {
+      ip_addr_t *multiaddr;
+      ip_addr_t *netif_addr;
+      enum netconn_igmp join_or_leave;
+    } jl;
+#endif /* LWIP_IGMP */
+#if TCP_LISTEN_BACKLOG
+    struct {
+      u8_t backlog;
+    } lb;
+#endif /* TCP_LISTEN_BACKLOG */
+  } msg;
+};
+
+/** This struct contains a function to execute in another thread context and
+    a struct api_msg_msg that serves as an argument for this function.
+    This is passed to tcpip_apimsg to execute functions in tcpip_thread context. */
+struct api_msg {
+  /** function to execute in tcpip_thread context */
+  void (* function)(struct api_msg_msg *msg);
+  /** arguments for this function */
+  struct api_msg_msg msg;
+};
+
+#if LWIP_DNS
+/** As do_gethostbyname requires more arguments but doesn't require a netconn,
+    it has its own struct (to avoid struct api_msg getting bigger than necessary).
+    do_gethostbyname must be called using tcpip_callback instead of tcpip_apimsg
+    (see netconn_gethostbyname). */
+struct dns_api_msg {
+  /** Hostname to query or dotted IP address string */
+  const char *name;
+  /** Rhe resolved address is stored here */
+  ip_addr_t *addr;
+  /** This semaphore is posted when the name is resolved, the application thread
+      should wait on it. */
+  sys_sem_t *sem;
+  /** Errors are given back here */
+  err_t *err;
+};
+#endif /* LWIP_DNS */
+
+void do_newconn         ( struct api_msg_msg *msg);
+void do_delconn         ( struct api_msg_msg *msg);
+void do_bind            ( struct api_msg_msg *msg);
+void do_connect         ( struct api_msg_msg *msg);
+void do_disconnect      ( struct api_msg_msg *msg);
+void do_listen          ( struct api_msg_msg *msg);
+void do_send            ( struct api_msg_msg *msg);
+void do_recv            ( struct api_msg_msg *msg);
+void do_write           ( struct api_msg_msg *msg);
+void do_getaddr         ( struct api_msg_msg *msg);
+void do_close           ( struct api_msg_msg *msg);
+void do_shutdown        ( struct api_msg_msg *msg);
+#if LWIP_IGMP
+void do_join_leave_group( struct api_msg_msg *msg);
+#endif /* LWIP_IGMP */
+
+#if LWIP_DNS
+void do_gethostbyname(void *arg);
+#endif /* LWIP_DNS */
+
+struct netconn* netconn_alloc(enum netconn_type t, netconn_callback callback);
+void netconn_free(struct netconn *conn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_NETCONN */
+
+#endif /* __LWIP_API_MSG_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/arch.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/arch.h
new file mode 100644
index 0000000..524af6b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/arch.h
@@ -0,0 +1,238 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ARCH_H__
+#define __LWIP_ARCH_H__
+
+#ifndef LITTLE_ENDIAN
+#define LITTLE_ENDIAN 1234
+#endif
+
+#ifndef BIG_ENDIAN
+#define BIG_ENDIAN 4321
+#endif
+
+#include "arch/cc.h"
+
+/** Temporary: define format string for size_t if not defined in cc.h */
+#ifndef SZT_F
+#define SZT_F U32_F
+#endif /* SZT_F */
+/** Temporary upgrade helper: define format string for u8_t as hex if not
+    defined in cc.h */
+#ifndef X8_F
+#define X8_F  "02x"
+#endif /* X8_F */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef PACK_STRUCT_BEGIN
+#define PACK_STRUCT_BEGIN
+#endif /* PACK_STRUCT_BEGIN */
+
+#ifndef PACK_STRUCT_END
+#define PACK_STRUCT_END
+#endif /* PACK_STRUCT_END */
+
+#ifndef PACK_STRUCT_FIELD
+#define PACK_STRUCT_FIELD(x) x
+#endif /* PACK_STRUCT_FIELD */
+
+
+#ifndef LWIP_UNUSED_ARG
+#define LWIP_UNUSED_ARG(x) (void)x
+#endif /* LWIP_UNUSED_ARG */ 
+
+
+#ifdef LWIP_PROVIDE_ERRNO
+
+#define  EPERM         1  /* Operation not permitted */
+#define  ENOENT        2  /* No such file or directory */
+#define  ESRCH         3  /* No such process */
+#define  EINTR         4  /* Interrupted system call */
+#define  EIO           5  /* I/O error */
+#define  ENXIO         6  /* No such device or address */
+#define  E2BIG         7  /* Arg list too long */
+#define  ENOEXEC       8  /* Exec format error */
+#define  EBADF         9  /* Bad file number */
+#define  ECHILD       10  /* No child processes */
+#define  EAGAIN       11  /* Try again */
+#define  ENOMEM       12  /* Out of memory */
+#define  EACCES       13  /* Permission denied */
+#define  EFAULT       14  /* Bad address */
+#define  ENOTBLK      15  /* Block device required */
+#define  EBUSY        16  /* Device or resource busy */
+#define  EEXIST       17  /* File exists */
+#define  EXDEV        18  /* Cross-device link */
+#define  ENODEV       19  /* No such device */
+#define  ENOTDIR      20  /* Not a directory */
+#define  EISDIR       21  /* Is a directory */
+#define  EINVAL       22  /* Invalid argument */
+#define  ENFILE       23  /* File table overflow */
+#define  EMFILE       24  /* Too many open files */
+#define  ENOTTY       25  /* Not a typewriter */
+#define  ETXTBSY      26  /* Text file busy */
+#define  EFBIG        27  /* File too large */
+#define  ENOSPC       28  /* No space left on device */
+#define  ESPIPE       29  /* Illegal seek */
+#define  EROFS        30  /* Read-only file system */
+#define  EMLINK       31  /* Too many links */
+#define  EPIPE        32  /* Broken pipe */
+#define  EDOM         33  /* Math argument out of domain of func */
+#define  ERANGE       34  /* Math result not representable */
+#define  EDEADLK      35  /* Resource deadlock would occur */
+#define  ENAMETOOLONG 36  /* File name too long */
+#define  ENOLCK       37  /* No record locks available */
+#define  ENOSYS       38  /* Function not implemented */
+#define  ENOTEMPTY    39  /* Directory not empty */
+#define  ELOOP        40  /* Too many symbolic links encountered */
+#define  EWOULDBLOCK  EAGAIN  /* Operation would block */
+#define  ENOMSG       42  /* No message of desired type */
+#define  EIDRM        43  /* Identifier removed */
+#define  ECHRNG       44  /* Channel number out of range */
+#define  EL2NSYNC     45  /* Level 2 not synchronized */
+#define  EL3HLT       46  /* Level 3 halted */
+#define  EL3RST       47  /* Level 3 reset */
+#define  ELNRNG       48  /* Link number out of range */
+#define  EUNATCH      49  /* Protocol driver not attached */
+#define  ENOCSI       50  /* No CSI structure available */
+#define  EL2HLT       51  /* Level 2 halted */
+#define  EBADE        52  /* Invalid exchange */
+#define  EBADR        53  /* Invalid request descriptor */
+#define  EXFULL       54  /* Exchange full */
+#define  ENOANO       55  /* No anode */
+#define  EBADRQC      56  /* Invalid request code */
+#define  EBADSLT      57  /* Invalid slot */
+
+#define  EDEADLOCK    EDEADLK
+
+#define  EBFONT       59  /* Bad font file format */
+#define  ENOSTR       60  /* Device not a stream */
+#define  ENODATA      61  /* No data available */
+#define  ETIME        62  /* Timer expired */
+#define  ENOSR        63  /* Out of streams resources */
+#define  ENONET       64  /* Machine is not on the network */
+#define  ENOPKG       65  /* Package not installed */
+#define  EREMOTE      66  /* Object is remote */
+#define  ENOLINK      67  /* Link has been severed */
+#define  EADV         68  /* Advertise error */
+#define  ESRMNT       69  /* Srmount error */
+#define  ECOMM        70  /* Communication error on send */
+#define  EPROTO       71  /* Protocol error */
+#define  EMULTIHOP    72  /* Multihop attempted */
+#define  EDOTDOT      73  /* RFS specific error */
+#define  EBADMSG      74  /* Not a data message */
+#define  EOVERFLOW    75  /* Value too large for defined data type */
+#define  ENOTUNIQ     76  /* Name not unique on network */
+#define  EBADFD       77  /* File descriptor in bad state */
+#define  EREMCHG      78  /* Remote address changed */
+#define  ELIBACC      79  /* Can not access a needed shared library */
+#define  ELIBBAD      80  /* Accessing a corrupted shared library */
+#define  ELIBSCN      81  /* .lib section in a.out corrupted */
+#define  ELIBMAX      82  /* Attempting to link in too many shared libraries */
+#define  ELIBEXEC     83  /* Cannot exec a shared library directly */
+#define  EILSEQ       84  /* Illegal byte sequence */
+#define  ERESTART     85  /* Interrupted system call should be restarted */
+#define  ESTRPIPE     86  /* Streams pipe error */
+#define  EUSERS       87  /* Too many users */
+#define  ENOTSOCK     88  /* Socket operation on non-socket */
+#define  EDESTADDRREQ 89  /* Destination address required */
+#define  EMSGSIZE     90  /* Message too long */
+#define  EPROTOTYPE   91  /* Protocol wrong type for socket */
+#define  ENOPROTOOPT  92  /* Protocol not available */
+#define  EPROTONOSUPPORT 93  /* Protocol not supported */
+#define  ESOCKTNOSUPPORT 94  /* Socket type not supported */
+#define  EOPNOTSUPP      95  /* Operation not supported on transport endpoint */
+#define  EPFNOSUPPORT    96  /* Protocol family not supported */
+#define  EAFNOSUPPORT    97  /* Address family not supported by protocol */
+#define  EADDRINUSE      98  /* Address already in use */
+#define  EADDRNOTAVAIL   99  /* Cannot assign requested address */
+#define  ENETDOWN       100  /* Network is down */
+#define  ENETUNREACH    101  /* Network is unreachable */
+#define  ENETRESET      102  /* Network dropped connection because of reset */
+#define  ECONNABORTED   103  /* Software caused connection abort */
+#define  ECONNRESET     104  /* Connection reset by peer */
+#define  ENOBUFS        105  /* No buffer space available */
+#define  EISCONN        106  /* Transport endpoint is already connected */
+#define  ENOTCONN       107  /* Transport endpoint is not connected */
+#define  ESHUTDOWN      108  /* Cannot send after transport endpoint shutdown */
+#define  ETOOMANYREFS   109  /* Too many references: cannot splice */
+#define  ETIMEDOUT      110  /* Connection timed out */
+#define  ECONNREFUSED   111  /* Connection refused */
+#define  EHOSTDOWN      112  /* Host is down */
+#define  EHOSTUNREACH   113  /* No route to host */
+#define  EALREADY       114  /* Operation already in progress */
+#define  EINPROGRESS    115  /* Operation now in progress */
+#define  ESTALE         116  /* Stale NFS file handle */
+#define  EUCLEAN        117  /* Structure needs cleaning */
+#define  ENOTNAM        118  /* Not a XENIX named type file */
+#define  ENAVAIL        119  /* No XENIX semaphores available */
+#define  EISNAM         120  /* Is a named type file */
+#define  EREMOTEIO      121  /* Remote I/O error */
+#define  EDQUOT         122  /* Quota exceeded */
+
+#define  ENOMEDIUM      123  /* No medium found */
+#define  EMEDIUMTYPE    124  /* Wrong medium type */
+
+
+#define ENSROK                    0 /* DNS server returned answer with no data */
+#define ENSRNODATA              160 /* DNS server returned answer with no data */
+#define ENSRFORMERR             161 /* DNS server claims query was misformatted */
+#define ENSRSERVFAIL            162 /* DNS server returned general failure */
+#define ENSRNOTFOUND            163 /* Domain name not found */
+#define ENSRNOTIMP              164 /* DNS server does not implement requested operation */
+#define ENSRREFUSED             165 /* DNS server refused query */
+#define ENSRBADQUERY            166 /* Misformatted DNS query */
+#define ENSRBADNAME             167 /* Misformatted domain name */
+#define ENSRBADFAMILY           168 /* Unsupported address family */
+#define ENSRBADRESP             169 /* Misformatted DNS reply */
+#define ENSRCONNREFUSED         170 /* Could not contact DNS servers */
+#define ENSRTIMEOUT             171 /* Timeout while contacting DNS servers */
+#define ENSROF                  172 /* End of file */
+#define ENSRFILE                173 /* Error reading file */
+#define ENSRNOMEM               174 /* Out of memory */
+#define ENSRDESTRUCTION         175 /* Application terminated lookup */
+#define ENSRQUERYDOMAINTOOLONG  176 /* Domain name is too long */
+#define ENSRCNAMELOOP           177 /* Domain name is too long */
+
+#ifndef errno
+extern int errno;
+#endif
+
+#endif /* LWIP_PROVIDE_ERRNO */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_ARCH_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/debug.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/debug.h
new file mode 100644
index 0000000..1950a3e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/debug.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_DEBUG_H__
+#define __LWIP_DEBUG_H__
+
+#include "lwip/arch.h"
+
+/** lower two bits indicate debug level
+ * - 0 all
+ * - 1 warning
+ * - 2 serious
+ * - 3 severe
+ */
+#define LWIP_DBG_LEVEL_ALL     0x00
+#define LWIP_DBG_LEVEL_OFF     LWIP_DBG_LEVEL_ALL /* compatibility define only */
+#define LWIP_DBG_LEVEL_WARNING 0x01 /* bad checksums, dropped packets, ... */
+#define LWIP_DBG_LEVEL_SERIOUS 0x02 /* memory allocation failures, ... */
+#define LWIP_DBG_LEVEL_SEVERE  0x03
+#define LWIP_DBG_MASK_LEVEL    0x03
+
+/** flag for LWIP_DEBUGF to enable that debug message */
+#define LWIP_DBG_ON            0x80U
+/** flag for LWIP_DEBUGF to disable that debug message */
+#define LWIP_DBG_OFF           0x00U
+
+/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */
+#define LWIP_DBG_TRACE         0x40U
+/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */
+#define LWIP_DBG_STATE         0x20U
+/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */
+#define LWIP_DBG_FRESH         0x10U
+/** flag for LWIP_DEBUGF to halt after printing this debug message */
+#define LWIP_DBG_HALT          0x08U
+
+#ifndef LWIP_NOASSERT
+#define LWIP_ASSERT(message, assertion) do { if(!(assertion)) \
+	{ LWIP_PLATFORM_ASSERT(message); } } while(0)
+#else  /* LWIP_NOASSERT */
+#define LWIP_ASSERT(message, assertion) 
+#endif /* LWIP_NOASSERT */
+
+/** if "expression" isn't true, then print "message" and execute "handler" expression */
+#ifndef LWIP_ERROR
+#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \
+  LWIP_PLATFORM_ASSERT(message); handler;}} while(0)
+#endif /* LWIP_ERROR */
+
+#ifdef LWIP_DEBUG
+/** print debug message only if debug message type is enabled...
+ *  AND is of correct type AND is at least LWIP_DBG_LEVEL
+ */
+#define LWIP_DEBUGF(debug, message) do { \
+                               if ( \
+                                   ((debug) & LWIP_DBG_ON) && \
+                                   ((debug) & LWIP_DBG_TYPES_ON) && \
+                                   ((s16_t)((debug) & LWIP_DBG_MASK_LEVEL) >= LWIP_DBG_MIN_LEVEL)) { \
+                                 LWIP_PLATFORM_DIAG(message); \
+                                 if ((debug) & LWIP_DBG_HALT) { \
+                                   while(1); \
+                                 } \
+                               } \
+                             } while(0)
+
+#else  /* LWIP_DEBUG */
+#define LWIP_DEBUGF(debug, message) 
+#endif /* LWIP_DEBUG */
+
+#endif /* __LWIP_DEBUG_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/def.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/def.h
new file mode 100644
index 0000000..9b6de6a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/def.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_DEF_H__
+#define __LWIP_DEF_H__
+
+/* arch.h might define NULL already */
+#include "lwip/arch.h"
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LWIP_MAX(x , y)  (((x) > (y)) ? (x) : (y))
+#define LWIP_MIN(x , y)  (((x) < (y)) ? (x) : (y))
+
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+
+/** Get the absolute difference between 2 u32_t values (correcting overflows)
+ * 'a' is expected to be 'higher' (without overflow) than 'b'. */
+#define LWIP_U32_DIFF(a, b) (((a) >= (b)) ? ((a) - (b)) : (((a) + ((b) ^ 0xFFFFFFFF) + 1))) 
+
+/* Endianess-optimized shifting of two u8_t to create one u16_t */
+#if BYTE_ORDER == LITTLE_ENDIAN
+#define LWIP_MAKE_U16(a, b) ((a << 8) | b)
+#else
+#define LWIP_MAKE_U16(a, b) ((b << 8) | a)
+#endif 
+
+#ifndef LWIP_PLATFORM_BYTESWAP
+#define LWIP_PLATFORM_BYTESWAP 0
+#endif
+
+#ifndef LWIP_PREFIX_BYTEORDER_FUNCS
+/* workaround for naming collisions on some platforms */
+
+#ifdef htons
+#undef htons
+#endif /* htons */
+#ifdef htonl
+#undef htonl
+#endif /* htonl */
+#ifdef ntohs
+#undef ntohs
+#endif /* ntohs */
+#ifdef ntohl
+#undef ntohl
+#endif /* ntohl */
+
+#define htons(x) lwip_htons(x)
+#define ntohs(x) lwip_ntohs(x)
+#define htonl(x) lwip_htonl(x)
+#define ntohl(x) lwip_ntohl(x)
+#endif /* LWIP_PREFIX_BYTEORDER_FUNCS */
+
+#if BYTE_ORDER == BIG_ENDIAN
+#define lwip_htons(x) (x)
+#define lwip_ntohs(x) (x)
+#define lwip_htonl(x) (x)
+#define lwip_ntohl(x) (x)
+#define PP_HTONS(x) (x)
+#define PP_NTOHS(x) (x)
+#define PP_HTONL(x) (x)
+#define PP_NTOHL(x) (x)
+#else /* BYTE_ORDER != BIG_ENDIAN */
+#if LWIP_PLATFORM_BYTESWAP
+#define lwip_htons(x) LWIP_PLATFORM_HTONS(x)
+#define lwip_ntohs(x) LWIP_PLATFORM_HTONS(x)
+#define lwip_htonl(x) LWIP_PLATFORM_HTONL(x)
+#define lwip_ntohl(x) LWIP_PLATFORM_HTONL(x)
+#else /* LWIP_PLATFORM_BYTESWAP */
+u16_t lwip_htons(u16_t x);
+u16_t lwip_ntohs(u16_t x);
+u32_t lwip_htonl(u32_t x);
+u32_t lwip_ntohl(u32_t x);
+#endif /* LWIP_PLATFORM_BYTESWAP */
+
+/* These macros should be calculated by the preprocessor and are used
+   with compile-time constants only (so that there is no little-endian
+   overhead at runtime). */
+#define PP_HTONS(x) ((((x) & 0xff) << 8) | (((x) & 0xff00) >> 8))
+#define PP_NTOHS(x) PP_HTONS(x)
+#define PP_HTONL(x) ((((x) & 0xff) << 24) | \
+                     (((x) & 0xff00) << 8) | \
+                     (((x) & 0xff0000UL) >> 8) | \
+                     (((x) & 0xff000000UL) >> 24))
+#define PP_NTOHL(x) PP_HTONL(x)
+
+#endif /* BYTE_ORDER == BIG_ENDIAN */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_DEF_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/dhcp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/dhcp.h
new file mode 100644
index 0000000..32d9338
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/dhcp.h
@@ -0,0 +1,242 @@
+/** @file
+ */
+
+#ifndef __LWIP_DHCP_H__
+#define __LWIP_DHCP_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_DHCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** period (in seconds) of the application calling dhcp_coarse_tmr() */
+#define DHCP_COARSE_TIMER_SECS 60 
+/** period (in milliseconds) of the application calling dhcp_coarse_tmr() */
+#define DHCP_COARSE_TIMER_MSECS (DHCP_COARSE_TIMER_SECS * 1000UL)
+/** period (in milliseconds) of the application calling dhcp_fine_tmr() */
+#define DHCP_FINE_TIMER_MSECS 500 
+
+#define DHCP_CHADDR_LEN 16U
+#define DHCP_SNAME_LEN  64U
+#define DHCP_FILE_LEN   128U
+
+struct dhcp
+{
+  /** transaction identifier of last sent request */ 
+  u32_t xid;
+  /** our connection to the DHCP server */ 
+  struct udp_pcb *pcb;
+  /** incoming msg */
+  struct dhcp_msg *msg_in;
+  /** current DHCP state machine state */
+  u8_t state;
+  /** retries of current request */
+  u8_t tries;
+#if LWIP_DHCP_AUTOIP_COOP
+  u8_t autoip_coop_state;
+#endif
+  u8_t subnet_mask_given;
+
+  struct pbuf *p_out; /* pbuf of outcoming msg */
+  struct dhcp_msg *msg_out; /* outgoing msg */
+  u16_t options_out_len; /* outgoing msg options length */
+  u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */
+  u16_t t1_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */
+  u16_t t2_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */
+  ip_addr_t server_ip_addr; /* dhcp server address that offered this lease */
+  ip_addr_t offered_ip_addr;
+  ip_addr_t offered_sn_mask;
+  ip_addr_t offered_gw_addr;
+ 
+  u32_t offered_t0_lease; /* lease period (in seconds) */
+  u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */
+  u32_t offered_t2_rebind; /* recommended rebind time (usually 66% of lease period)  */
+  /* @todo: LWIP_DHCP_BOOTP_FILE configuration option?
+     integrate with possible TFTP-client for booting? */
+#if LWIP_DHCP_BOOTP_FILE
+  ip_addr_t offered_si_addr;
+  char boot_file_name[DHCP_FILE_LEN];
+#endif /* LWIP_DHCP_BOOTPFILE */
+};
+
+/* MUST be compiled with "pack structs" or equivalent! */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** minimum set of fields of any DHCP message */
+struct dhcp_msg
+{
+  PACK_STRUCT_FIELD(u8_t op);
+  PACK_STRUCT_FIELD(u8_t htype);
+  PACK_STRUCT_FIELD(u8_t hlen);
+  PACK_STRUCT_FIELD(u8_t hops);
+  PACK_STRUCT_FIELD(u32_t xid);
+  PACK_STRUCT_FIELD(u16_t secs);
+  PACK_STRUCT_FIELD(u16_t flags);
+  PACK_STRUCT_FIELD(ip_addr_p_t ciaddr);
+  PACK_STRUCT_FIELD(ip_addr_p_t yiaddr);
+  PACK_STRUCT_FIELD(ip_addr_p_t siaddr);
+  PACK_STRUCT_FIELD(ip_addr_p_t giaddr);
+  PACK_STRUCT_FIELD(u8_t chaddr[DHCP_CHADDR_LEN]);
+  PACK_STRUCT_FIELD(u8_t sname[DHCP_SNAME_LEN]);
+  PACK_STRUCT_FIELD(u8_t file[DHCP_FILE_LEN]);
+  PACK_STRUCT_FIELD(u32_t cookie);
+#define DHCP_MIN_OPTIONS_LEN 68U
+/** make sure user does not configure this too small */
+#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN))
+#  undef DHCP_OPTIONS_LEN
+#endif
+/** allow this to be configured in lwipopts.h, but not too small */
+#if (!defined(DHCP_OPTIONS_LEN))
+/** set this to be sufficient for your options in outgoing DHCP msgs */
+#  define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN
+#endif
+  PACK_STRUCT_FIELD(u8_t options[DHCP_OPTIONS_LEN]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+void dhcp_set_struct(struct netif *netif, struct dhcp *dhcp);
+/** Remove a struct dhcp previously set to the netif using dhcp_set_struct() */
+#define dhcp_remove_struct(netif) do { (netif)->dhcp = NULL; } while(0)
+void dhcp_cleanup(struct netif *netif);
+/** start DHCP configuration */
+err_t dhcp_start(struct netif *netif);
+/** enforce early lease renewal (not needed normally)*/
+err_t dhcp_renew(struct netif *netif);
+/** release the DHCP lease, usually called before dhcp_stop()*/
+err_t dhcp_release(struct netif *netif);
+/** stop DHCP configuration */
+void dhcp_stop(struct netif *netif);
+/** inform server of our manual IP address */
+void dhcp_inform(struct netif *netif);
+/** Handle a possible change in the network configuration */
+void dhcp_network_changed(struct netif *netif);
+
+/** if enabled, check whether the offered IP address is not in use, using ARP */
+#if DHCP_DOES_ARP_CHECK
+void dhcp_arp_reply(struct netif *netif, ip_addr_t *addr);
+#endif
+
+/** to be called every minute */
+void dhcp_coarse_tmr(void);
+/** to be called every half second */
+void dhcp_fine_tmr(void);
+ 
+/** DHCP message item offsets and length */
+#define DHCP_OP_OFS       0
+#define DHCP_HTYPE_OFS    1
+#define DHCP_HLEN_OFS     2
+#define DHCP_HOPS_OFS     3
+#define DHCP_XID_OFS      4
+#define DHCP_SECS_OFS     8
+#define DHCP_FLAGS_OFS    10
+#define DHCP_CIADDR_OFS   12
+#define DHCP_YIADDR_OFS   16
+#define DHCP_SIADDR_OFS   20
+#define DHCP_GIADDR_OFS   24
+#define DHCP_CHADDR_OFS   28
+#define DHCP_SNAME_OFS    44
+#define DHCP_FILE_OFS     108
+#define DHCP_MSG_LEN      236
+
+#define DHCP_COOKIE_OFS   DHCP_MSG_LEN
+#define DHCP_OPTIONS_OFS  (DHCP_MSG_LEN + 4)
+
+#define DHCP_CLIENT_PORT  68  
+#define DHCP_SERVER_PORT  67
+
+/** DHCP client states */
+#define DHCP_OFF          0
+#define DHCP_REQUESTING   1
+#define DHCP_INIT         2
+#define DHCP_REBOOTING    3
+#define DHCP_REBINDING    4
+#define DHCP_RENEWING     5
+#define DHCP_SELECTING    6
+#define DHCP_INFORMING    7
+#define DHCP_CHECKING     8
+#define DHCP_PERMANENT    9
+#define DHCP_BOUND        10
+/** not yet implemented #define DHCP_RELEASING 11 */
+#define DHCP_BACKING_OFF  12
+
+/** AUTOIP cooperatation flags */
+#define DHCP_AUTOIP_COOP_STATE_OFF  0
+#define DHCP_AUTOIP_COOP_STATE_ON   1
+ 
+#define DHCP_BOOTREQUEST  1
+#define DHCP_BOOTREPLY    2
+
+/** DHCP message types */
+#define DHCP_DISCOVER 1
+#define DHCP_OFFER    2
+#define DHCP_REQUEST  3
+#define DHCP_DECLINE  4
+#define DHCP_ACK      5
+#define DHCP_NAK      6
+#define DHCP_RELEASE  7
+#define DHCP_INFORM   8
+
+/** DHCP hardware type, currently only ethernet is supported */
+#define DHCP_HTYPE_ETH 1
+
+#define DHCP_MAGIC_COOKIE 0x63825363UL
+
+/* This is a list of options for BOOTP and DHCP, see RFC 2132 for descriptions */
+
+/** BootP options */
+#define DHCP_OPTION_PAD 0
+#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */
+#define DHCP_OPTION_ROUTER 3
+#define DHCP_OPTION_DNS_SERVER 6 
+#define DHCP_OPTION_HOSTNAME 12
+#define DHCP_OPTION_IP_TTL 23
+#define DHCP_OPTION_MTU 26
+#define DHCP_OPTION_BROADCAST 28
+#define DHCP_OPTION_TCP_TTL 37
+#define DHCP_OPTION_END 255
+
+/** DHCP options */
+#define DHCP_OPTION_REQUESTED_IP 50 /* RFC 2132 9.1, requested IP address */
+#define DHCP_OPTION_LEASE_TIME 51 /* RFC 2132 9.2, time in seconds, in 4 bytes */
+#define DHCP_OPTION_OVERLOAD 52 /* RFC2132 9.3, use file and/or sname field for options */
+
+#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */
+#define DHCP_OPTION_MESSAGE_TYPE_LEN 1
+
+#define DHCP_OPTION_SERVER_ID 54 /* RFC 2132 9.7, server IP address */
+#define DHCP_OPTION_PARAMETER_REQUEST_LIST 55 /* RFC 2132 9.8, requested option types */
+
+#define DHCP_OPTION_MAX_MSG_SIZE 57 /* RFC 2132 9.10, message size accepted >= 576 */
+#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2
+
+#define DHCP_OPTION_T1 58 /* T1 renewal time */
+#define DHCP_OPTION_T2 59 /* T2 rebinding time */
+#define DHCP_OPTION_US 60
+#define DHCP_OPTION_CLIENT_ID 61
+#define DHCP_OPTION_TFTP_SERVERNAME 66
+#define DHCP_OPTION_BOOTFILE 67
+
+/** possible combinations of overloading the file and sname fields with options */
+#define DHCP_OVERLOAD_NONE 0
+#define DHCP_OVERLOAD_FILE 1
+#define DHCP_OVERLOAD_SNAME  2
+#define DHCP_OVERLOAD_SNAME_FILE 3
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_DHCP */
+
+#endif /*__LWIP_DHCP_H__*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/dns.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/dns.h
new file mode 100644
index 0000000..6c7d9b0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/dns.h
@@ -0,0 +1,124 @@
+/**
+ * lwip DNS resolver header file.
+
+ * Author: Jim Pettinato 
+ *   April 2007
+
+ * ported from uIP resolv.c Copyright (c) 2002-2003, Adam Dunkels.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __LWIP_DNS_H__
+#define __LWIP_DNS_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_DNS /* don't build if not configured for use in lwipopts.h */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** DNS timer period */
+#define DNS_TMR_INTERVAL          1000
+
+/** DNS field TYPE used for "Resource Records" */
+#define DNS_RRTYPE_A              1     /* a host address */
+#define DNS_RRTYPE_NS             2     /* an authoritative name server */
+#define DNS_RRTYPE_MD             3     /* a mail destination (Obsolete - use MX) */
+#define DNS_RRTYPE_MF             4     /* a mail forwarder (Obsolete - use MX) */
+#define DNS_RRTYPE_CNAME          5     /* the canonical name for an alias */
+#define DNS_RRTYPE_SOA            6     /* marks the start of a zone of authority */
+#define DNS_RRTYPE_MB             7     /* a mailbox domain name (EXPERIMENTAL) */
+#define DNS_RRTYPE_MG             8     /* a mail group member (EXPERIMENTAL) */
+#define DNS_RRTYPE_MR             9     /* a mail rename domain name (EXPERIMENTAL) */
+#define DNS_RRTYPE_NULL           10    /* a null RR (EXPERIMENTAL) */
+#define DNS_RRTYPE_WKS            11    /* a well known service description */
+#define DNS_RRTYPE_PTR            12    /* a domain name pointer */
+#define DNS_RRTYPE_HINFO          13    /* host information */
+#define DNS_RRTYPE_MINFO          14    /* mailbox or mail list information */
+#define DNS_RRTYPE_MX             15    /* mail exchange */
+#define DNS_RRTYPE_TXT            16    /* text strings */
+
+/** DNS field CLASS used for "Resource Records" */
+#define DNS_RRCLASS_IN            1     /* the Internet */
+#define DNS_RRCLASS_CS            2     /* the CSNET class (Obsolete - used only for examples in some obsolete RFCs) */
+#define DNS_RRCLASS_CH            3     /* the CHAOS class */
+#define DNS_RRCLASS_HS            4     /* Hesiod [Dyer 87] */
+#define DNS_RRCLASS_FLUSH         0x800 /* Flush bit */
+
+/* The size used for the next line is rather a hack, but it prevents including socket.h in all files
+   that include memp.h, and that would possibly break portability (since socket.h defines some types
+   and constants possibly already define by the OS).
+   Calculation rule:
+   sizeof(struct addrinfo) + sizeof(struct sockaddr_in) + DNS_MAX_NAME_LENGTH + 1 byte zero-termination */
+#define NETDB_ELEM_SIZE           (32 + 16 + DNS_MAX_NAME_LENGTH + 1)
+
+#if DNS_LOCAL_HOSTLIST
+/** struct used for local host-list */
+struct local_hostlist_entry {
+  /** static hostname */
+  const char *name;
+  /** static host address in network byteorder */
+  ip_addr_t addr;
+  struct local_hostlist_entry *next;
+};
+#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+#ifndef DNS_LOCAL_HOSTLIST_MAX_NAMELEN
+#define DNS_LOCAL_HOSTLIST_MAX_NAMELEN  DNS_MAX_NAME_LENGTH
+#endif
+#define LOCALHOSTLIST_ELEM_SIZE ((sizeof(struct local_hostlist_entry) + DNS_LOCAL_HOSTLIST_MAX_NAMELEN + 1))
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+#endif /* DNS_LOCAL_HOSTLIST */
+
+/** Callback which is invoked when a hostname is found.
+ * A function of this type must be implemented by the application using the DNS resolver.
+ * @param name pointer to the name that was looked up.
+ * @param ipaddr pointer to an ip_addr_t containing the IP address of the hostname,
+ *        or NULL if the name could not be found (or on any other error).
+ * @param callback_arg a user-specified callback argument passed to dns_gethostbyname
+*/
+typedef void (*dns_found_callback)(const char *name, ip_addr_t *ipaddr, void *callback_arg);
+
+void           dns_init(void);
+void           dns_tmr(void);
+void           dns_setserver(u8_t numdns, ip_addr_t *dnsserver);
+ip_addr_t      dns_getserver(u8_t numdns);
+err_t          dns_gethostbyname(const char *hostname, ip_addr_t *addr,
+                                 dns_found_callback found, void *callback_arg);
+
+#if DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+int            dns_local_removehost(const char *hostname, const ip_addr_t *addr);
+err_t          dns_local_addhost(const char *hostname, const ip_addr_t *addr);
+#endif /* DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_DNS */
+
+#endif /* __LWIP_DNS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/err.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/err.h
new file mode 100644
index 0000000..ac90772
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/err.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ERR_H__
+#define __LWIP_ERR_H__
+
+#include "lwip/opt.h"
+#include "lwip/arch.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Define LWIP_ERR_T in cc.h if you want to use
+ *  a different type for your platform (must be signed). */
+#ifdef LWIP_ERR_T
+typedef LWIP_ERR_T err_t;
+#else /* LWIP_ERR_T */
+typedef s8_t err_t;
+#endif /* LWIP_ERR_T*/
+
+/* Definitions for error constants. */
+
+#define ERR_OK          0    /* No error, everything OK. */
+#define ERR_MEM        -1    /* Out of memory error.     */
+#define ERR_BUF        -2    /* Buffer error.            */
+#define ERR_TIMEOUT    -3    /* Timeout.                 */
+#define ERR_RTE        -4    /* Routing problem.         */
+#define ERR_INPROGRESS -5    /* Operation in progress    */
+#define ERR_VAL        -6    /* Illegal value.           */
+#define ERR_WOULDBLOCK -7    /* Operation would block.   */
+#define ERR_USE        -8    /* Address in use.          */
+#define ERR_ISCONN     -9    /* Already connected.       */
+
+#define ERR_IS_FATAL(e) ((e) < ERR_ISCONN)
+
+#define ERR_ABRT       -10   /* Connection aborted.      */
+#define ERR_RST        -11   /* Connection reset.        */
+#define ERR_CLSD       -12   /* Connection closed.       */
+#define ERR_CONN       -13   /* Not connected.           */
+
+#define ERR_ARG        -14   /* Illegal argument.        */
+
+#define ERR_IF         -15   /* Low-level netif error    */
+
+
+#ifdef LWIP_DEBUG
+extern const char *lwip_strerr(err_t err);
+#else
+#define lwip_strerr(x) ""
+#endif /* LWIP_DEBUG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_ERR_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/init.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/init.h
new file mode 100644
index 0000000..77dcdfc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/init.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_INIT_H__
+#define __LWIP_INIT_H__
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** X.x.x: Major version of the stack */
+#define LWIP_VERSION_MAJOR      1U
+/** x.X.x: Minor version of the stack */
+#define LWIP_VERSION_MINOR      4U
+/** x.x.X: Revision of the stack */
+#define LWIP_VERSION_REVISION   0U
+/** For release candidates, this is set to 1..254
+  * For official releases, this is set to 255 (LWIP_RC_RELEASE)
+  * For development versions (CVS), this is set to 0 (LWIP_RC_DEVELOPMENT) */
+#define LWIP_VERSION_RC         255U
+
+/** LWIP_VERSION_RC is set to LWIP_RC_RELEASE for official releases */
+#define LWIP_RC_RELEASE         255U
+/** LWIP_VERSION_RC is set to LWIP_RC_DEVELOPMENT for CVS versions */
+#define LWIP_RC_DEVELOPMENT     0U
+
+#define LWIP_VERSION_IS_RELEASE     (LWIP_VERSION_RC == LWIP_RC_RELEASE)
+#define LWIP_VERSION_IS_DEVELOPMENT (LWIP_VERSION_RC == LWIP_RC_DEVELOPMENT)
+#define LWIP_VERSION_IS_RC          ((LWIP_VERSION_RC != LWIP_RC_RELEASE) && (LWIP_VERSION_RC != LWIP_RC_DEVELOPMENT))
+
+/** Provides the version of the stack */
+#define LWIP_VERSION   (LWIP_VERSION_MAJOR << 24   | LWIP_VERSION_MINOR << 16 | \
+                        LWIP_VERSION_REVISION << 8 | LWIP_VERSION_RC)
+
+/* Modules initialization */
+void lwip_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_INIT_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/mem.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/mem.h
new file mode 100644
index 0000000..9507c0a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/mem.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_MEM_H__
+#define __LWIP_MEM_H__
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if MEM_LIBC_MALLOC
+
+#include  /* for size_t */
+
+typedef size_t mem_size_t;
+
+/* aliases for C library malloc() */
+#define mem_init()
+/* in case C library malloc() needs extra protection,
+ * allow these defines to be overridden.
+ */
+#ifndef mem_free
+#define mem_free free
+#endif
+#ifndef mem_malloc
+#define mem_malloc malloc
+#endif
+#ifndef mem_calloc
+#define mem_calloc calloc
+#endif
+/* Since there is no C library allocation function to shrink memory without
+   moving it, define this to nothing. */
+#ifndef mem_trim
+#define mem_trim(mem, size) (mem)
+#endif
+#else /* MEM_LIBC_MALLOC */
+
+/* MEM_SIZE would have to be aligned, but using 64000 here instead of
+ * 65535 leaves some room for alignment...
+ */
+#if MEM_SIZE > 64000L
+typedef u32_t mem_size_t;
+#define MEM_SIZE_F U32_F
+#else
+typedef u16_t mem_size_t;
+#define MEM_SIZE_F U16_F
+#endif /* MEM_SIZE > 64000 */
+
+#if MEM_USE_POOLS
+/** mem_init is not used when using pools instead of a heap */
+#define mem_init()
+/** mem_trim is not used when using pools instead of a heap:
+    we can't free part of a pool element and don't want to copy the rest */
+#define mem_trim(mem, size) (mem)
+#else /* MEM_USE_POOLS */
+/* lwIP alternative malloc */
+void  mem_init(void);
+void *mem_trim(void *mem, mem_size_t size);
+#endif /* MEM_USE_POOLS */
+void *mem_malloc(mem_size_t size);
+void *mem_calloc(mem_size_t count, mem_size_t size);
+void  mem_free(void *mem);
+#endif /* MEM_LIBC_MALLOC */
+
+/** Calculate memory size for an aligned buffer - returns the next highest
+ * multiple of MEM_ALIGNMENT (e.g. LWIP_MEM_ALIGN_SIZE(3) and
+ * LWIP_MEM_ALIGN_SIZE(4) will both yield 4 for MEM_ALIGNMENT == 4).
+ */
+#ifndef LWIP_MEM_ALIGN_SIZE
+#define LWIP_MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1) & ~(MEM_ALIGNMENT-1))
+#endif
+
+/** Calculate safe memory size for an aligned buffer when using an unaligned
+ * type as storage. This includes a safety-margin on (MEM_ALIGNMENT - 1) at the
+ * start (e.g. if buffer is u8_t[] and actual data will be u32_t*)
+ */
+#ifndef LWIP_MEM_ALIGN_BUFFER
+#define LWIP_MEM_ALIGN_BUFFER(size) (((size) + MEM_ALIGNMENT - 1))
+#endif
+
+/** Align a memory pointer to the alignment defined by MEM_ALIGNMENT
+ * so that ADDR % MEM_ALIGNMENT == 0
+ */
+#ifndef LWIP_MEM_ALIGN
+#define LWIP_MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1)))
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_MEM_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/memp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/memp.h
new file mode 100644
index 0000000..f0d0739
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/memp.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef __LWIP_MEMP_H__
+#define __LWIP_MEMP_H__
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Create the list of all memory pools managed by memp. MEMP_MAX represents a NULL pool at the end */
+typedef enum {
+#define LWIP_MEMPOOL(name,num,size,desc)  MEMP_##name,
+#include "lwip/memp_std.h"
+  MEMP_MAX
+} memp_t;
+
+#if MEM_USE_POOLS
+/* Use a helper type to get the start and end of the user "memory pools" for mem_malloc */
+typedef enum {
+    /* Get the first (via:
+       MEMP_POOL_HELPER_START = ((u8_t) 1*MEMP_POOL_A + 0*MEMP_POOL_B + 0*MEMP_POOL_C + 0)*/
+    MEMP_POOL_HELPER_FIRST = ((u8_t)
+#define LWIP_MEMPOOL(name,num,size,desc)
+#define LWIP_MALLOC_MEMPOOL_START 1
+#define LWIP_MALLOC_MEMPOOL(num, size) * MEMP_POOL_##size + 0
+#define LWIP_MALLOC_MEMPOOL_END
+#include "lwip/memp_std.h"
+    ) ,
+    /* Get the last (via:
+       MEMP_POOL_HELPER_END = ((u8_t) 0 + MEMP_POOL_A*0 + MEMP_POOL_B*0 + MEMP_POOL_C*1) */
+    MEMP_POOL_HELPER_LAST = ((u8_t)
+#define LWIP_MEMPOOL(name,num,size,desc)
+#define LWIP_MALLOC_MEMPOOL_START
+#define LWIP_MALLOC_MEMPOOL(num, size) 0 + MEMP_POOL_##size *
+#define LWIP_MALLOC_MEMPOOL_END 1
+#include "lwip/memp_std.h"
+    )
+} memp_pool_helper_t;
+
+/* The actual start and stop values are here (cast them over)
+   We use this helper type and these defines so we can avoid using const memp_t values */
+#define MEMP_POOL_FIRST ((memp_t) MEMP_POOL_HELPER_FIRST)
+#define MEMP_POOL_LAST   ((memp_t) MEMP_POOL_HELPER_LAST)
+#endif /* MEM_USE_POOLS */
+
+#if MEMP_MEM_MALLOC || MEM_USE_POOLS
+extern const u16_t memp_sizes[MEMP_MAX];
+#endif /* MEMP_MEM_MALLOC || MEM_USE_POOLS */
+
+#if MEMP_MEM_MALLOC
+
+#include "mem.h"
+
+#define memp_init()
+#define memp_malloc(type)     mem_malloc(memp_sizes[type])
+#define memp_free(type, mem)  mem_free(mem)
+
+#else /* MEMP_MEM_MALLOC */
+
+#if MEM_USE_POOLS
+/** This structure is used to save the pool one element came from. */
+struct memp_malloc_helper
+{
+   memp_t poolnr;
+};
+#endif /* MEM_USE_POOLS */
+
+void  memp_init(void);
+
+#if MEMP_OVERFLOW_CHECK
+void *memp_malloc_fn(memp_t type, const char* file, const int line);
+#define memp_malloc(t) memp_malloc_fn((t), __FILE__, __LINE__)
+#else
+void *memp_malloc(memp_t type);
+#endif
+void  memp_free(memp_t type, void *mem);
+
+#endif /* MEMP_MEM_MALLOC */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_MEMP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/memp_std.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/memp_std.h
new file mode 100644
index 0000000..6ce408f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/memp_std.h
@@ -0,0 +1,122 @@
+/*
+ * SETUP: Make sure we define everything we will need.
+ *
+ * We have create three types of pools:
+ *   1) MEMPOOL - standard pools
+ *   2) MALLOC_MEMPOOL - to be used by mem_malloc in mem.c
+ *   3) PBUF_MEMPOOL - a mempool of pbuf's, so include space for the pbuf struct
+ *
+ * If the include'r doesn't require any special treatment of each of the types
+ * above, then will declare #2 & #3 to be just standard mempools.
+ */
+#ifndef LWIP_MALLOC_MEMPOOL
+/* This treats "malloc pools" just like any other pool.
+   The pools are a little bigger to provide 'size' as the amount of user data. */
+#define LWIP_MALLOC_MEMPOOL(num, size) LWIP_MEMPOOL(POOL_##size, num, (size + sizeof(struct memp_malloc_helper)), "MALLOC_"#size)
+#define LWIP_MALLOC_MEMPOOL_START
+#define LWIP_MALLOC_MEMPOOL_END
+#endif /* LWIP_MALLOC_MEMPOOL */ 
+
+#ifndef LWIP_PBUF_MEMPOOL
+/* This treats "pbuf pools" just like any other pool.
+ * Allocates buffers for a pbuf struct AND a payload size */
+#define LWIP_PBUF_MEMPOOL(name, num, payload, desc) LWIP_MEMPOOL(name, num, (MEMP_ALIGN_SIZE(sizeof(struct pbuf)) + MEMP_ALIGN_SIZE(payload)), desc)
+#endif /* LWIP_PBUF_MEMPOOL */
+
+
+/*
+ * A list of internal pools used by LWIP.
+ *
+ * LWIP_MEMPOOL(pool_name, number_elements, element_size, pool_description)
+ *     creates a pool name MEMP_pool_name. description is used in stats.c
+ */
+#if LWIP_RAW
+LWIP_MEMPOOL(RAW_PCB,        MEMP_NUM_RAW_PCB,         sizeof(struct raw_pcb),        "RAW_PCB")
+#endif /* LWIP_RAW */
+
+#if LWIP_UDP
+LWIP_MEMPOOL(UDP_PCB,        MEMP_NUM_UDP_PCB,         sizeof(struct udp_pcb),        "UDP_PCB")
+#endif /* LWIP_UDP */
+
+#if LWIP_TCP
+LWIP_MEMPOOL(TCP_PCB,        MEMP_NUM_TCP_PCB,         sizeof(struct tcp_pcb),        "TCP_PCB")
+LWIP_MEMPOOL(TCP_PCB_LISTEN, MEMP_NUM_TCP_PCB_LISTEN,  sizeof(struct tcp_pcb_listen), "TCP_PCB_LISTEN")
+LWIP_MEMPOOL(TCP_SEG,        MEMP_NUM_TCP_SEG,         sizeof(struct tcp_seg),        "TCP_SEG")
+#endif /* LWIP_TCP */
+
+#if IP_REASSEMBLY
+LWIP_MEMPOOL(REASSDATA,      MEMP_NUM_REASSDATA,       sizeof(struct ip_reassdata),   "REASSDATA")
+#endif /* IP_REASSEMBLY */
+#if IP_FRAG && !IP_FRAG_USES_STATIC_BUF && !LWIP_NETIF_TX_SINGLE_PBUF
+LWIP_MEMPOOL(FRAG_PBUF,      MEMP_NUM_FRAG_PBUF,       sizeof(struct pbuf_custom_ref),"FRAG_PBUF")
+#endif /* IP_FRAG && !IP_FRAG_USES_STATIC_BUF && !LWIP_NETIF_TX_SINGLE_PBUF */
+
+#if LWIP_NETCONN
+LWIP_MEMPOOL(NETBUF,         MEMP_NUM_NETBUF,          sizeof(struct netbuf),         "NETBUF")
+LWIP_MEMPOOL(NETCONN,        MEMP_NUM_NETCONN,         sizeof(struct netconn),        "NETCONN")
+#endif /* LWIP_NETCONN */
+
+#if NO_SYS==0
+LWIP_MEMPOOL(TCPIP_MSG_API,  MEMP_NUM_TCPIP_MSG_API,   sizeof(struct tcpip_msg),      "TCPIP_MSG_API")
+#if !LWIP_TCPIP_CORE_LOCKING_INPUT
+LWIP_MEMPOOL(TCPIP_MSG_INPKT,MEMP_NUM_TCPIP_MSG_INPKT, sizeof(struct tcpip_msg),      "TCPIP_MSG_INPKT")
+#endif /* !LWIP_TCPIP_CORE_LOCKING_INPUT */
+#endif /* NO_SYS==0 */
+
+#if ARP_QUEUEING
+LWIP_MEMPOOL(ARP_QUEUE,      MEMP_NUM_ARP_QUEUE,       sizeof(struct etharp_q_entry), "ARP_QUEUE")
+#endif /* ARP_QUEUEING */
+
+#if LWIP_IGMP
+LWIP_MEMPOOL(IGMP_GROUP,     MEMP_NUM_IGMP_GROUP,      sizeof(struct igmp_group),     "IGMP_GROUP")
+#endif /* LWIP_IGMP */
+
+#if (!NO_SYS || (NO_SYS && !NO_SYS_NO_TIMERS)) /* LWIP_TIMERS */
+LWIP_MEMPOOL(SYS_TIMEOUT,    MEMP_NUM_SYS_TIMEOUT,     sizeof(struct sys_timeo),      "SYS_TIMEOUT")
+#endif /* LWIP_TIMERS */
+
+#if LWIP_SNMP
+LWIP_MEMPOOL(SNMP_ROOTNODE,  MEMP_NUM_SNMP_ROOTNODE,   sizeof(struct mib_list_rootnode), "SNMP_ROOTNODE")
+LWIP_MEMPOOL(SNMP_NODE,      MEMP_NUM_SNMP_NODE,       sizeof(struct mib_list_node),     "SNMP_NODE")
+LWIP_MEMPOOL(SNMP_VARBIND,   MEMP_NUM_SNMP_VARBIND,    sizeof(struct snmp_varbind),      "SNMP_VARBIND")
+LWIP_MEMPOOL(SNMP_VALUE,     MEMP_NUM_SNMP_VALUE,      SNMP_MAX_VALUE_SIZE,              "SNMP_VALUE")
+#endif /* LWIP_SNMP */
+#if LWIP_DNS && LWIP_SOCKET
+LWIP_MEMPOOL(NETDB,          MEMP_NUM_NETDB,           NETDB_ELEM_SIZE,               "NETDB")
+#endif /* LWIP_DNS && LWIP_SOCKET */
+#if LWIP_DNS && DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+LWIP_MEMPOOL(LOCALHOSTLIST,  MEMP_NUM_LOCALHOSTLIST,   LOCALHOSTLIST_ELEM_SIZE,       "LOCALHOSTLIST")
+#endif /* LWIP_DNS && DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+#if PPP_SUPPORT && PPPOE_SUPPORT
+LWIP_MEMPOOL(PPPOE_IF,      MEMP_NUM_PPPOE_INTERFACES, sizeof(struct pppoe_softc),    "PPPOE_IF")
+#endif /* PPP_SUPPORT && PPPOE_SUPPORT */
+
+/*
+ * A list of pools of pbuf's used by LWIP.
+ *
+ * LWIP_PBUF_MEMPOOL(pool_name, number_elements, pbuf_payload_size, pool_description)
+ *     creates a pool name MEMP_pool_name. description is used in stats.c
+ *     This allocates enough space for the pbuf struct and a payload.
+ *     (Example: pbuf_payload_size=0 allocates only size for the struct)
+ */
+LWIP_PBUF_MEMPOOL(PBUF,      MEMP_NUM_PBUF,            0,                             "PBUF_REF/ROM")
+LWIP_PBUF_MEMPOOL(PBUF_POOL, PBUF_POOL_SIZE,           PBUF_POOL_BUFSIZE,             "PBUF_POOL")
+
+
+/*
+ * Allow for user-defined pools; this must be explicitly set in lwipopts.h
+ * since the default is to NOT look for lwippools.h
+ */
+#if MEMP_USE_CUSTOM_POOLS
+#include "lwippools.h"
+#endif /* MEMP_USE_CUSTOM_POOLS */
+
+/*
+ * REQUIRED CLEANUP: Clear up so we don't get "multiply defined" error later
+ * (#undef is ignored for something that is not defined)
+ */
+#undef LWIP_MEMPOOL
+#undef LWIP_MALLOC_MEMPOOL
+#undef LWIP_MALLOC_MEMPOOL_START
+#undef LWIP_MALLOC_MEMPOOL_END
+#undef LWIP_PBUF_MEMPOOL
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/netbuf.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/netbuf.h
new file mode 100644
index 0000000..7d247d7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/netbuf.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_NETBUF_H__
+#define __LWIP_NETBUF_H__
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** This netbuf has dest-addr/port set */
+#define NETBUF_FLAG_DESTADDR    0x01
+/** This netbuf includes a checksum */
+#define NETBUF_FLAG_CHKSUM      0x02
+
+struct netbuf {
+  struct pbuf *p, *ptr;
+  ip_addr_t addr;
+  u16_t port;
+#if LWIP_NETBUF_RECVINFO || LWIP_CHECKSUM_ON_COPY
+#if LWIP_CHECKSUM_ON_COPY
+  u8_t flags;
+#endif /* LWIP_CHECKSUM_ON_COPY */
+  u16_t toport_chksum;
+#if LWIP_NETBUF_RECVINFO
+  ip_addr_t toaddr;
+#endif /* LWIP_NETBUF_RECVINFO */
+#endif /* LWIP_NETBUF_RECVINFO || LWIP_CHECKSUM_ON_COPY */
+};
+
+/* Network buffer functions: */
+struct netbuf *   netbuf_new      (void);
+void              netbuf_delete   (struct netbuf *buf);
+void *            netbuf_alloc    (struct netbuf *buf, u16_t size);
+void              netbuf_free     (struct netbuf *buf);
+err_t             netbuf_ref      (struct netbuf *buf,
+                                   const void *dataptr, u16_t size);
+void              netbuf_chain    (struct netbuf *head,
+           struct netbuf *tail);
+
+err_t             netbuf_data     (struct netbuf *buf,
+                                   void **dataptr, u16_t *len);
+s8_t              netbuf_next     (struct netbuf *buf);
+void              netbuf_first    (struct netbuf *buf);
+
+
+#define netbuf_copy_partial(buf, dataptr, len, offset) \
+  pbuf_copy_partial((buf)->p, (dataptr), (len), (offset))
+#define netbuf_copy(buf,dataptr,len) netbuf_copy_partial(buf, dataptr, len, 0)
+#define netbuf_take(buf, dataptr, len) pbuf_take((buf)->p, dataptr, len)
+#define netbuf_len(buf)              ((buf)->p->tot_len)
+#define netbuf_fromaddr(buf)         (&((buf)->addr))
+#define netbuf_set_fromaddr(buf, fromaddr) ip_addr_set((&(buf)->addr), fromaddr)
+#define netbuf_fromport(buf)         ((buf)->port)
+#if LWIP_NETBUF_RECVINFO
+#define netbuf_destaddr(buf)         (&((buf)->toaddr))
+#define netbuf_set_destaddr(buf, destaddr) ip_addr_set((&(buf)->addr), destaddr)
+#define netbuf_destport(buf)         (((buf)->flags & NETBUF_FLAG_DESTADDR) ? (buf)->toport_chksum : 0)
+#endif /* LWIP_NETBUF_RECVINFO */
+#if LWIP_CHECKSUM_ON_COPY
+#define netbuf_set_chksum(buf, chksum) do { (buf)->flags = NETBUF_FLAG_CHKSUM; \
+                                            (buf)->toport_chksum = chksum; } while(0)
+#endif /* LWIP_CHECKSUM_ON_COPY */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_NETBUF_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/netdb.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/netdb.h
new file mode 100644
index 0000000..7587e2f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/netdb.h
@@ -0,0 +1,124 @@
+/*
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Simon Goldschmidt
+ *
+ */
+#ifndef __LWIP_NETDB_H__
+#define __LWIP_NETDB_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_DNS && LWIP_SOCKET
+
+#include  /* for size_t */
+
+#include "lwip/inet.h"
+#include "lwip/sockets.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* some rarely used options */
+#ifndef LWIP_DNS_API_DECLARE_H_ERRNO
+#define LWIP_DNS_API_DECLARE_H_ERRNO 1
+#endif
+
+#ifndef LWIP_DNS_API_DEFINE_ERRORS
+#define LWIP_DNS_API_DEFINE_ERRORS 1
+#endif
+
+#ifndef LWIP_DNS_API_DECLARE_STRUCTS
+#define LWIP_DNS_API_DECLARE_STRUCTS 1
+#endif
+
+#if LWIP_DNS_API_DEFINE_ERRORS
+/** Errors used by the DNS API functions, h_errno can be one of them */
+#define EAI_NONAME      200
+#define EAI_SERVICE     201
+#define EAI_FAIL        202
+#define EAI_MEMORY      203
+
+#define HOST_NOT_FOUND  210
+#define NO_DATA         211
+#define NO_RECOVERY     212
+#define TRY_AGAIN       213
+#endif /* LWIP_DNS_API_DEFINE_ERRORS */
+
+#if LWIP_DNS_API_DECLARE_STRUCTS
+struct hostent {
+    char  *h_name;      /* Official name of the host. */
+    char **h_aliases;   /* A pointer to an array of pointers to alternative host names,
+                           terminated by a null pointer. */
+    int    h_addrtype;  /* Address type. */
+    int    h_length;    /* The length, in bytes, of the address. */
+    char **h_addr_list; /* A pointer to an array of pointers to network addresses (in
+                           network byte order) for the host, terminated by a null pointer. */
+#define h_addr h_addr_list[0] /* for backward compatibility */
+};
+
+struct addrinfo {
+    int               ai_flags;      /* Input flags. */
+    int               ai_family;     /* Address family of socket. */
+    int               ai_socktype;   /* Socket type. */
+    int               ai_protocol;   /* Protocol of socket. */
+    socklen_t         ai_addrlen;    /* Length of socket address. */
+    struct sockaddr  *ai_addr;       /* Socket address of socket. */
+    char             *ai_canonname;  /* Canonical name of service location. */
+    struct addrinfo  *ai_next;       /* Pointer to next in list. */
+};
+#endif /* LWIP_DNS_API_DECLARE_STRUCTS */
+
+#if LWIP_DNS_API_DECLARE_H_ERRNO
+/* application accessable error code set by the DNS API functions */
+extern int h_errno;
+#endif /* LWIP_DNS_API_DECLARE_H_ERRNO*/
+
+struct hostent *lwip_gethostbyname(const char *name);
+int lwip_gethostbyname_r(const char *name, struct hostent *ret, char *buf,
+                size_t buflen, struct hostent **result, int *h_errnop);
+void lwip_freeaddrinfo(struct addrinfo *ai);
+int lwip_getaddrinfo(const char *nodename,
+       const char *servname,
+       const struct addrinfo *hints,
+       struct addrinfo **res);
+
+#if LWIP_COMPAT_SOCKETS
+#define gethostbyname(name) lwip_gethostbyname(name)
+#define gethostbyname_r(name, ret, buf, buflen, result, h_errnop) \
+       lwip_gethostbyname_r(name, ret, buf, buflen, result, h_errnop)
+#define freeaddrinfo(addrinfo) lwip_freeaddrinfo(addrinfo)
+#define getaddrinfo(nodname, servname, hints, res) \
+       lwip_getaddrinfo(nodname, servname, hints, res)
+#endif /* LWIP_COMPAT_SOCKETS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_DNS && LWIP_SOCKET */
+
+#endif /* __LWIP_NETDB_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/netif.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/netif.h
new file mode 100644
index 0000000..a8790b5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/netif.h
@@ -0,0 +1,315 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_NETIF_H__
+#define __LWIP_NETIF_H__
+
+#include "lwip/opt.h"
+
+#define ENABLE_LOOPBACK (LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF)
+
+#include "lwip/err.h"
+
+#include "lwip/ip_addr.h"
+
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#if LWIP_DHCP
+struct dhcp;
+#endif
+#if LWIP_AUTOIP
+struct autoip;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Throughout this file, IP addresses are expected to be in
+ * the same byte order as in IP_PCB. */
+
+/** must be the maximum of all used hardware address lengths
+    across all types of interfaces in use */
+#define NETIF_MAX_HWADDR_LEN 6U
+
+/** Whether the network interface is 'up'. This is
+ * a software flag used to control whether this network
+ * interface is enabled and processes traffic.
+ * It is set by the startup code (for static IP configuration) or
+ * by dhcp/autoip when an address has been assigned.
+ */
+#define NETIF_FLAG_UP           0x01U
+/** If set, the netif has broadcast capability.
+ * Set by the netif driver in its init function. */
+#define NETIF_FLAG_BROADCAST    0x02U
+/** If set, the netif is one end of a point-to-point connection.
+ * Set by the netif driver in its init function. */
+#define NETIF_FLAG_POINTTOPOINT 0x04U
+/** If set, the interface is configured using DHCP.
+ * Set by the DHCP code when starting or stopping DHCP. */
+#define NETIF_FLAG_DHCP         0x08U
+/** If set, the interface has an active link
+ *  (set by the network interface driver).
+ * Either set by the netif driver in its init function (if the link
+ * is up at that time) or at a later point once the link comes up
+ * (if link detection is supported by the hardware). */
+#define NETIF_FLAG_LINK_UP      0x10U
+/** If set, the netif is an ethernet device using ARP.
+ * Set by the netif driver in its init function.
+ * Used to check input packet types and use of DHCP. */
+#define NETIF_FLAG_ETHARP       0x20U
+/** If set, the netif is an ethernet device. It might not use
+ * ARP or TCP/IP if it is used for PPPoE only.
+ */
+#define NETIF_FLAG_ETHERNET     0x40U
+/** If set, the netif has IGMP capability.
+ * Set by the netif driver in its init function. */
+#define NETIF_FLAG_IGMP         0x80U
+
+/** Function prototype for netif init functions. Set up flags and output/linkoutput
+ * callback functions in this function.
+ *
+ * @param netif The netif to initialize
+ */
+typedef err_t (*netif_init_fn)(struct netif *netif);
+/** Function prototype for netif->input functions. This function is saved as 'input'
+ * callback function in the netif struct. Call it when a packet has been received.
+ *
+ * @param p The received packet, copied into a pbuf
+ * @param inp The netif which received the packet
+ */
+typedef err_t (*netif_input_fn)(struct pbuf *p, struct netif *inp);
+/** Function prototype for netif->output functions. Called by lwIP when a packet
+ * shall be sent. For ethernet netif, set this to 'etharp_output' and set
+ * 'linkoutput'.
+ *
+ * @param netif The netif which shall send a packet
+ * @param p The packet to send (p->payload points to IP header)
+ * @param ipaddr The IP address to which the packet shall be sent
+ */
+typedef err_t (*netif_output_fn)(struct netif *netif, struct pbuf *p,
+       ip_addr_t *ipaddr);
+/** Function prototype for netif->linkoutput functions. Only used for ethernet
+ * netifs. This function is called by ARP when a packet shall be sent.
+ *
+ * @param netif The netif which shall send a packet
+ * @param p The packet to send (raw ethernet packet)
+ */
+typedef err_t (*netif_linkoutput_fn)(struct netif *netif, struct pbuf *p);
+/** Function prototype for netif status- or link-callback functions. */
+typedef void (*netif_status_callback_fn)(struct netif *netif);
+/** Function prototype for netif igmp_mac_filter functions */
+typedef err_t (*netif_igmp_mac_filter_fn)(struct netif *netif,
+       ip_addr_t *group, u8_t action);
+
+/** Generic data structure used for all lwIP network interfaces.
+ *  The following fields should be filled in by the initialization
+ *  function for the device driver: hwaddr_len, hwaddr[], mtu, flags */
+struct netif {
+  /** pointer to next in linked list */
+  struct netif *next;
+
+  /** IP address configuration in network byte order */
+  ip_addr_t ip_addr;
+  ip_addr_t netmask;
+  ip_addr_t gw;
+
+  /** This function is called by the network device driver
+   *  to pass a packet up the TCP/IP stack. */
+  netif_input_fn input;
+  /** This function is called by the IP module when it wants
+   *  to send a packet on the interface. This function typically
+   *  first resolves the hardware address, then sends the packet. */
+  netif_output_fn output;
+  /** This function is called by the ARP module when it wants
+   *  to send a packet on the interface. This function outputs
+   *  the pbuf as-is on the link medium. */
+  netif_linkoutput_fn linkoutput;
+#if LWIP_NETIF_STATUS_CALLBACK
+  /** This function is called when the netif state is set to up or down
+   */
+  netif_status_callback_fn status_callback;
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+#if LWIP_NETIF_LINK_CALLBACK
+  /** This function is called when the netif link is set to up or down
+   */
+  netif_status_callback_fn link_callback;
+#endif /* LWIP_NETIF_LINK_CALLBACK */
+  /** This field can be set by the device driver and could point
+   *  to state information for the device. */
+  void *state;
+#if LWIP_DHCP
+  /** the DHCP client state information for this netif */
+  struct dhcp *dhcp;
+#endif /* LWIP_DHCP */
+#if LWIP_AUTOIP
+  /** the AutoIP client state information for this netif */
+  struct autoip *autoip;
+#endif
+#if LWIP_NETIF_HOSTNAME
+  /* the hostname for this netif, NULL is a valid value */
+  char*  hostname;
+#endif /* LWIP_NETIF_HOSTNAME */
+  /** maximum transfer unit (in bytes) */
+  u16_t mtu;
+  /** number of bytes used in hwaddr */
+  u8_t hwaddr_len;
+  /** link level hardware address of this interface */
+  u8_t hwaddr[NETIF_MAX_HWADDR_LEN];
+  /** flags (see NETIF_FLAG_ above) */
+  u8_t flags;
+  /** descriptive abbreviation */
+  char name[2];
+  /** number of this interface */
+  u8_t num;
+#if LWIP_SNMP
+  /** link type (from "snmp_ifType" enum from snmp.h) */
+  u8_t link_type;
+  /** (estimate) link speed */
+  u32_t link_speed;
+  /** timestamp at last change made (up/down) */
+  u32_t ts;
+  /** counters */
+  u32_t ifinoctets;
+  u32_t ifinucastpkts;
+  u32_t ifinnucastpkts;
+  u32_t ifindiscards;
+  u32_t ifoutoctets;
+  u32_t ifoutucastpkts;
+  u32_t ifoutnucastpkts;
+  u32_t ifoutdiscards;
+#endif /* LWIP_SNMP */
+#if LWIP_IGMP
+  /** This function could be called to add or delete a entry in the multicast
+      filter table of the ethernet MAC.*/
+  netif_igmp_mac_filter_fn igmp_mac_filter;
+#endif /* LWIP_IGMP */
+#if LWIP_NETIF_HWADDRHINT
+  u8_t *addr_hint;
+#endif /* LWIP_NETIF_HWADDRHINT */
+#if ENABLE_LOOPBACK
+  /* List of packets to be queued for ourselves. */
+  struct pbuf *loop_first;
+  struct pbuf *loop_last;
+#if LWIP_LOOPBACK_MAX_PBUFS
+  u16_t loop_cnt_current;
+#endif /* LWIP_LOOPBACK_MAX_PBUFS */
+#endif /* ENABLE_LOOPBACK */
+};
+
+#if LWIP_SNMP
+#define NETIF_INIT_SNMP(netif, type, speed) \
+  /* use "snmp_ifType" enum from snmp.h for "type", snmp_ifType_ethernet_csmacd by example */ \
+  (netif)->link_type = (type);    \
+  /* your link speed here (units: bits per second) */  \
+  (netif)->link_speed = (speed);  \
+  (netif)->ts = 0;              \
+  (netif)->ifinoctets = 0;      \
+  (netif)->ifinucastpkts = 0;   \
+  (netif)->ifinnucastpkts = 0;  \
+  (netif)->ifindiscards = 0;    \
+  (netif)->ifoutoctets = 0;     \
+  (netif)->ifoutucastpkts = 0;  \
+  (netif)->ifoutnucastpkts = 0; \
+  (netif)->ifoutdiscards = 0
+#else /* LWIP_SNMP */
+#define NETIF_INIT_SNMP(netif, type, speed)
+#endif /* LWIP_SNMP */
+
+
+/** The list of network interfaces. */
+extern struct netif *netif_list;
+/** The default network interface. */
+extern struct netif *netif_default;
+
+void netif_init(void);
+
+struct netif *netif_add(struct netif *netif, ip_addr_t *ipaddr, ip_addr_t *netmask,
+      ip_addr_t *gw, void *state, netif_init_fn init, netif_input_fn input);
+
+void
+netif_set_addr(struct netif *netif, ip_addr_t *ipaddr, ip_addr_t *netmask,
+      ip_addr_t *gw);
+void netif_remove(struct netif * netif);
+
+/* Returns a network interface given its name. The name is of the form
+   "et0", where the first two letters are the "name" field in the
+   netif structure, and the digit is in the num field in the same
+   structure. */
+struct netif *netif_find(char *name);
+
+void netif_set_default(struct netif *netif);
+
+void netif_set_ipaddr(struct netif *netif, ip_addr_t *ipaddr);
+void netif_set_netmask(struct netif *netif, ip_addr_t *netmask);
+void netif_set_gw(struct netif *netif, ip_addr_t *gw);
+
+void netif_set_up(struct netif *netif);
+void netif_set_down(struct netif *netif);
+/** Ask if an interface is up */
+#define netif_is_up(netif) (((netif)->flags & NETIF_FLAG_UP) ? (u8_t)1 : (u8_t)0)
+
+#if LWIP_NETIF_STATUS_CALLBACK
+void netif_set_status_callback(struct netif *netif, netif_status_callback_fn status_callback);
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+
+void netif_set_link_up(struct netif *netif);
+void netif_set_link_down(struct netif *netif);
+/** Ask if a link is up */ 
+#define netif_is_link_up(netif) (((netif)->flags & NETIF_FLAG_LINK_UP) ? (u8_t)1 : (u8_t)0)
+
+#if LWIP_NETIF_LINK_CALLBACK
+void netif_set_link_callback(struct netif *netif, netif_status_callback_fn link_callback);
+#endif /* LWIP_NETIF_LINK_CALLBACK */
+
+#if LWIP_NETIF_HOSTNAME
+#define netif_set_hostname(netif, name) do { if((netif) != NULL) { (netif)->hostname = name; }}while(0)
+#define netif_get_hostname(netif) (((netif) != NULL) ? ((netif)->hostname) : NULL)
+#endif /* LWIP_NETIF_HOSTNAME */
+
+#if LWIP_IGMP
+#define netif_set_igmp_mac_filter(netif, function) do { if((netif) != NULL) { (netif)->igmp_mac_filter = function; }}while(0)
+#define netif_get_igmp_mac_filter(netif) (((netif) != NULL) ? ((netif)->igmp_mac_filter) : NULL)
+#endif /* LWIP_IGMP */
+
+#if ENABLE_LOOPBACK
+err_t netif_loop_output(struct netif *netif, struct pbuf *p, ip_addr_t *dest_ip);
+void netif_poll(struct netif *netif);
+#if !LWIP_NETIF_LOOPBACK_MULTITHREADING
+void netif_poll_all(void);
+#endif /* !LWIP_NETIF_LOOPBACK_MULTITHREADING */
+#endif /* ENABLE_LOOPBACK */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_NETIF_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/netifapi.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/netifapi.h
new file mode 100644
index 0000000..33318ef
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/netifapi.h
@@ -0,0 +1,108 @@
+/*
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ */
+ 
+#ifndef __LWIP_NETIFAPI_H__
+#define __LWIP_NETIFAPI_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/sys.h"
+#include "lwip/netif.h"
+#include "lwip/dhcp.h"
+#include "lwip/autoip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef void (*netifapi_void_fn)(struct netif *netif);
+typedef err_t (*netifapi_errt_fn)(struct netif *netif);
+
+struct netifapi_msg_msg {
+#if !LWIP_TCPIP_CORE_LOCKING
+  sys_sem_t sem;
+#endif /* !LWIP_TCPIP_CORE_LOCKING */
+  err_t err;
+  struct netif *netif;
+  union {
+    struct {
+      ip_addr_t *ipaddr;
+      ip_addr_t *netmask;
+      ip_addr_t *gw;
+      void *state;
+      netif_init_fn init;
+      netif_input_fn input;
+    } add;
+    struct {
+      netifapi_void_fn voidfunc;
+      netifapi_errt_fn errtfunc;
+    } common;
+  } msg;
+};
+
+struct netifapi_msg {
+  void (* function)(struct netifapi_msg_msg *msg);
+  struct netifapi_msg_msg msg;
+};
+
+
+/* API for application */
+err_t netifapi_netif_add       ( struct netif *netif,
+                                 ip_addr_t *ipaddr,
+                                 ip_addr_t *netmask,
+                                 ip_addr_t *gw,
+                                 void *state,
+                                 netif_init_fn init,
+                                 netif_input_fn input);
+
+err_t netifapi_netif_set_addr  ( struct netif *netif,
+                                 ip_addr_t *ipaddr,
+                                 ip_addr_t *netmask,
+                                 ip_addr_t *gw );
+
+err_t netifapi_netif_common    ( struct netif *netif,
+                                 netifapi_void_fn voidfunc,
+                                 netifapi_errt_fn errtfunc);
+
+#define netifapi_netif_remove(n)      netifapi_netif_common(n, netif_remove, NULL)
+#define netifapi_netif_set_up(n)      netifapi_netif_common(n, netif_set_up, NULL)
+#define netifapi_netif_set_down(n)    netifapi_netif_common(n, netif_set_down, NULL)
+#define netifapi_netif_set_default(n) netifapi_netif_common(n, netif_set_default, NULL)
+#define netifapi_dhcp_start(n)        netifapi_netif_common(n, NULL, dhcp_start)
+#define netifapi_dhcp_stop(n)         netifapi_netif_common(n, dhcp_stop, NULL)
+#define netifapi_autoip_start(n)      netifapi_netif_common(n, NULL, autoip_start)
+#define netifapi_autoip_stop(n)       netifapi_netif_common(n, NULL, autoip_stop)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_NETIF_API */
+
+#endif /* __LWIP_NETIFAPI_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/opt.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/opt.h
new file mode 100644
index 0000000..a1b8765
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/opt.h
@@ -0,0 +1,2043 @@
+/**
+ * @file
+ *
+ * lwIP Options Configuration
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_OPT_H__
+#define __LWIP_OPT_H__
+
+/*
+ * Include user defined options first. Anything not defined in these files
+ * will be set to standard values. Override anything you dont like!
+ */
+#include "lwipopts.h"
+#include "lwip/debug.h"
+
+/*
+   -----------------------------------------------
+   ---------- Platform specific locking ----------
+   -----------------------------------------------
+*/
+
+/**
+ * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
+ * critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#ifndef SYS_LIGHTWEIGHT_PROT
+#define SYS_LIGHTWEIGHT_PROT            0
+#endif
+
+/** 
+ * NO_SYS==1: Provides VERY minimal functionality. Otherwise,
+ * use lwIP facilities.
+ */
+#ifndef NO_SYS
+#define NO_SYS                          0
+#endif
+
+/**
+ * NO_SYS_NO_TIMERS==1: Drop support for sys_timeout when NO_SYS==1
+ * Mainly for compatibility to old versions.
+ */
+#ifndef NO_SYS_NO_TIMERS
+#define NO_SYS_NO_TIMERS                0
+#endif
+
+/**
+ * MEMCPY: override this if you have a faster implementation at hand than the
+ * one included in your C library
+ */
+#ifndef MEMCPY
+#define MEMCPY(dst,src,len)             memcpy(dst,src,len)
+#endif
+
+/**
+ * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a
+ * call to memcpy() if the length is known at compile time and is small.
+ */
+#ifndef SMEMCPY
+#define SMEMCPY(dst,src,len)            memcpy(dst,src,len)
+#endif
+
+/*
+   ------------------------------------
+   ---------- Memory options ----------
+   ------------------------------------
+*/
+/**
+ * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library
+ * instead of the lwip internal allocator. Can save code size if you
+ * already use it.
+ */
+#ifndef MEM_LIBC_MALLOC
+#define MEM_LIBC_MALLOC                 0
+#endif
+
+/**
+* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator.
+* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution
+* speed and usage from interrupts!
+*/
+#ifndef MEMP_MEM_MALLOC
+#define MEMP_MEM_MALLOC                 0
+#endif
+
+/**
+ * MEM_ALIGNMENT: should be set to the alignment of the CPU
+ *    4 byte alignment -> #define MEM_ALIGNMENT 4
+ *    2 byte alignment -> #define MEM_ALIGNMENT 2
+ */
+#ifndef MEM_ALIGNMENT
+#define MEM_ALIGNMENT                   1
+#endif
+
+/**
+ * MEM_SIZE: the size of the heap memory. If the application will send
+ * a lot of data that needs to be copied, this should be set high.
+ */
+#ifndef MEM_SIZE
+#define MEM_SIZE                        1600
+#endif
+
+/**
+ * MEMP_SEPARATE_POOLS: if defined to 1, each pool is placed in its own array.
+ * This can be used to individually change the location of each pool.
+ * Default is one big array for all pools
+ */
+#ifndef MEMP_SEPARATE_POOLS
+#define MEMP_SEPARATE_POOLS             0
+#endif
+
+/**
+ * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable
+ * amount of bytes before and after each memp element in every pool and fills
+ * it with a prominent default value.
+ *    MEMP_OVERFLOW_CHECK == 0 no checking
+ *    MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed
+ *    MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time
+ *      memp_malloc() or memp_free() is called (useful but slow!)
+ */
+#ifndef MEMP_OVERFLOW_CHECK
+#define MEMP_OVERFLOW_CHECK             0
+#endif
+
+/**
+ * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make
+ * sure that there are no cycles in the linked lists.
+ */
+#ifndef MEMP_SANITY_CHECK
+#define MEMP_SANITY_CHECK               0
+#endif
+
+/**
+ * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set
+ * of memory pools of various sizes. When mem_malloc is called, an element of
+ * the smallest pool that can provide the length needed is returned.
+ * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled.
+ */
+#ifndef MEM_USE_POOLS
+#define MEM_USE_POOLS                   0
+#endif
+
+/**
+ * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next
+ * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more
+ * reliable. */
+#ifndef MEM_USE_POOLS_TRY_BIGGER_POOL
+#define MEM_USE_POOLS_TRY_BIGGER_POOL   0
+#endif
+
+/**
+ * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h
+ * that defines additional pools beyond the "standard" ones required
+ * by lwIP. If you set this to 1, you must have lwippools.h in your 
+ * inlude path somewhere. 
+ */
+#ifndef MEMP_USE_CUSTOM_POOLS
+#define MEMP_USE_CUSTOM_POOLS           0
+#endif
+
+/**
+ * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from
+ * interrupt context (or another context that doesn't allow waiting for a
+ * semaphore).
+ * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT,
+ * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs
+ * with each loop so that mem_free can run.
+ *
+ * ATTENTION: As you can see from the above description, this leads to dis-/
+ * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc
+ * can need longer.
+ *
+ * If you don't want that, at least for NO_SYS=0, you can still use the following
+ * functions to enqueue a deallocation call which then runs in the tcpip_thread
+ * context:
+ * - pbuf_free_callback(p);
+ * - mem_free_callback(m);
+ */
+#ifndef LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0
+#endif
+
+/*
+   ------------------------------------------------
+   ---------- Internal Memory Pool Sizes ----------
+   ------------------------------------------------
+*/
+/**
+ * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF).
+ * If the application sends a lot of data out of ROM (or other static memory),
+ * this should be set high.
+ */
+#ifndef MEMP_NUM_PBUF
+#define MEMP_NUM_PBUF                   16
+#endif
+
+/**
+ * MEMP_NUM_RAW_PCB: Number of raw connection PCBs
+ * (requires the LWIP_RAW option)
+ */
+#ifndef MEMP_NUM_RAW_PCB
+#define MEMP_NUM_RAW_PCB                4
+#endif
+
+/**
+ * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+ * per active UDP "connection".
+ * (requires the LWIP_UDP option)
+ */
+#ifndef MEMP_NUM_UDP_PCB
+#define MEMP_NUM_UDP_PCB                4
+#endif
+
+/**
+ * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections.
+ * (requires the LWIP_TCP option)
+ */
+#ifndef MEMP_NUM_TCP_PCB
+#define MEMP_NUM_TCP_PCB                5
+#endif
+
+/**
+ * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections.
+ * (requires the LWIP_TCP option)
+ */
+#ifndef MEMP_NUM_TCP_PCB_LISTEN
+#define MEMP_NUM_TCP_PCB_LISTEN         8
+#endif
+
+/**
+ * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments.
+ * (requires the LWIP_TCP option)
+ */
+#ifndef MEMP_NUM_TCP_SEG
+#define MEMP_NUM_TCP_SEG                16
+#endif
+
+/**
+ * MEMP_NUM_REASSDATA: the number of IP packets simultaneously queued for
+ * reassembly (whole packets, not fragments!)
+ */
+#ifndef MEMP_NUM_REASSDATA
+#define MEMP_NUM_REASSDATA              5
+#endif
+
+/**
+ * MEMP_NUM_FRAG_PBUF: the number of IP fragments simultaneously sent
+ * (fragments, not whole packets!).
+ * This is only used with IP_FRAG_USES_STATIC_BUF==0 and
+ * LWIP_NETIF_TX_SINGLE_PBUF==0 and only has to be > 1 with DMA-enabled MACs
+ * where the packet is not yet sent when netif->output returns.
+ */
+#ifndef MEMP_NUM_FRAG_PBUF
+#define MEMP_NUM_FRAG_PBUF              15
+#endif
+
+/**
+ * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing
+ * packets (pbufs) that are waiting for an ARP request (to resolve
+ * their destination address) to finish.
+ * (requires the ARP_QUEUEING option)
+ */
+#ifndef MEMP_NUM_ARP_QUEUE
+#define MEMP_NUM_ARP_QUEUE              30
+#endif
+
+/**
+ * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces
+ * can be members et the same time (one per netif - allsystems group -, plus one
+ * per netif membership).
+ * (requires the LWIP_IGMP option)
+ */
+#ifndef MEMP_NUM_IGMP_GROUP
+#define MEMP_NUM_IGMP_GROUP             8
+#endif
+
+/**
+ * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts.
+ * (requires NO_SYS==0)
+ */
+#ifndef MEMP_NUM_SYS_TIMEOUT
+#define MEMP_NUM_SYS_TIMEOUT            3
+#endif
+
+/**
+ * MEMP_NUM_NETBUF: the number of struct netbufs.
+ * (only needed if you use the sequential API, like api_lib.c)
+ */
+#ifndef MEMP_NUM_NETBUF
+#define MEMP_NUM_NETBUF                 2
+#endif
+
+/**
+ * MEMP_NUM_NETCONN: the number of struct netconns.
+ * (only needed if you use the sequential API, like api_lib.c)
+ */
+#ifndef MEMP_NUM_NETCONN
+#define MEMP_NUM_NETCONN                4
+#endif
+
+/**
+ * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used
+ * for callback/timeout API communication. 
+ * (only needed if you use tcpip.c)
+ */
+#ifndef MEMP_NUM_TCPIP_MSG_API
+#define MEMP_NUM_TCPIP_MSG_API          8
+#endif
+
+/**
+ * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used
+ * for incoming packets. 
+ * (only needed if you use tcpip.c)
+ */
+#ifndef MEMP_NUM_TCPIP_MSG_INPKT
+#define MEMP_NUM_TCPIP_MSG_INPKT        8
+#endif
+
+/**
+ * MEMP_NUM_SNMP_NODE: the number of leafs in the SNMP tree.
+ */
+#ifndef MEMP_NUM_SNMP_NODE
+#define MEMP_NUM_SNMP_NODE              50
+#endif
+
+/**
+ * MEMP_NUM_SNMP_ROOTNODE: the number of branches in the SNMP tree.
+ * Every branch has one leaf (MEMP_NUM_SNMP_NODE) at least!
+ */
+#ifndef MEMP_NUM_SNMP_ROOTNODE
+#define MEMP_NUM_SNMP_ROOTNODE          30
+#endif
+
+/**
+ * MEMP_NUM_SNMP_VARBIND: the number of concurrent requests (does not have to
+ * be changed normally) - 2 of these are used per request (1 for input,
+ * 1 for output)
+ */
+#ifndef MEMP_NUM_SNMP_VARBIND
+#define MEMP_NUM_SNMP_VARBIND           2
+#endif
+
+/**
+ * MEMP_NUM_SNMP_VALUE: the number of OID or values concurrently used
+ * (does not have to be changed normally) - 3 of these are used per request
+ * (1 for the value read and 2 for OIDs - input and output)
+ */
+#ifndef MEMP_NUM_SNMP_VALUE
+#define MEMP_NUM_SNMP_VALUE             3
+#endif
+
+/**
+ * MEMP_NUM_NETDB: the number of concurrently running lwip_addrinfo() calls
+ * (before freeing the corresponding memory using lwip_freeaddrinfo()).
+ */
+#ifndef MEMP_NUM_NETDB
+#define MEMP_NUM_NETDB                  1
+#endif
+
+/**
+ * MEMP_NUM_LOCALHOSTLIST: the number of host entries in the local host list
+ * if DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1.
+ */
+#ifndef MEMP_NUM_LOCALHOSTLIST
+#define MEMP_NUM_LOCALHOSTLIST          1
+#endif
+
+/**
+ * MEMP_NUM_PPPOE_INTERFACES: the number of concurrently active PPPoE
+ * interfaces (only used with PPPOE_SUPPORT==1)
+ */
+#ifndef MEMP_NUM_PPPOE_INTERFACES
+#define MEMP_NUM_PPPOE_INTERFACES       1
+#endif
+
+/**
+ * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. 
+ */
+#ifndef PBUF_POOL_SIZE
+#define PBUF_POOL_SIZE                  16
+#endif
+
+/*
+   ---------------------------------
+   ---------- ARP options ----------
+   ---------------------------------
+*/
+/**
+ * LWIP_ARP==1: Enable ARP functionality.
+ */
+#ifndef LWIP_ARP
+#define LWIP_ARP                        1
+#endif
+
+/**
+ * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached.
+ */
+#ifndef ARP_TABLE_SIZE
+#define ARP_TABLE_SIZE                  10
+#endif
+
+/**
+ * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address
+ * resolution. By default, only the most recent packet is queued per IP address.
+ * This is sufficient for most protocols and mainly reduces TCP connection
+ * startup time. Set this to 1 if you know your application sends more than one
+ * packet in a row to an IP address that is not in the ARP cache.
+ */
+#ifndef ARP_QUEUEING
+#define ARP_QUEUEING                    0
+#endif
+
+/**
+ * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be
+ * updated with the source MAC and IP addresses supplied in the packet.
+ * You may want to disable this if you do not trust LAN peers to have the
+ * correct addresses, or as a limited approach to attempt to handle
+ * spoofing. If disabled, lwIP will need to make a new ARP request if
+ * the peer is not already in the ARP table, adding a little latency.
+ * The peer *is* in the ARP table if it requested our address before.
+ * Also notice that this slows down input processing of every IP packet!
+ */
+#ifndef ETHARP_TRUST_IP_MAC
+#define ETHARP_TRUST_IP_MAC             0
+#endif
+
+/**
+ * ETHARP_SUPPORT_VLAN==1: support receiving ethernet packets with VLAN header.
+ * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check.
+ * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted.
+ * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted.
+ */
+#ifndef ETHARP_SUPPORT_VLAN
+#define ETHARP_SUPPORT_VLAN             0
+#endif
+
+/** LWIP_ETHERNET==1: enable ethernet support for PPPoE even though ARP
+ * might be disabled
+ */
+#ifndef LWIP_ETHERNET
+#define LWIP_ETHERNET                   (LWIP_ARP || PPPOE_SUPPORT)
+#endif
+
+/** ETH_PAD_SIZE: number of bytes added before the ethernet header to ensure
+ * alignment of payload after that header. Since the header is 14 bytes long,
+ * without this padding e.g. addresses in the IP header will not be aligned
+ * on a 32-bit boundary, so setting this to 2 can speed up 32-bit-platforms.
+ */
+#ifndef ETH_PAD_SIZE
+#define ETH_PAD_SIZE                    0
+#endif
+
+/** ETHARP_SUPPORT_STATIC_ENTRIES==1: enable code to support static ARP table
+ * entries (using etharp_add_static_entry/etharp_remove_static_entry).
+ */
+#ifndef ETHARP_SUPPORT_STATIC_ENTRIES
+#define ETHARP_SUPPORT_STATIC_ENTRIES   0
+#endif
+
+
+/*
+   --------------------------------
+   ---------- IP options ----------
+   --------------------------------
+*/
+/**
+ * IP_FORWARD==1: Enables the ability to forward IP packets across network
+ * interfaces. If you are going to run lwIP on a device with only one network
+ * interface, define this to 0.
+ */
+#ifndef IP_FORWARD
+#define IP_FORWARD                      0
+#endif
+
+/**
+ * IP_OPTIONS_ALLOWED: Defines the behavior for IP options.
+ *      IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped.
+ *      IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed).
+ */
+#ifndef IP_OPTIONS_ALLOWED
+#define IP_OPTIONS_ALLOWED              1
+#endif
+
+/**
+ * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that
+ * this option does not affect outgoing packet sizes, which can be controlled
+ * via IP_FRAG.
+ */
+#ifndef IP_REASSEMBLY
+#define IP_REASSEMBLY                   1
+#endif
+
+/**
+ * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note
+ * that this option does not affect incoming packet sizes, which can be
+ * controlled via IP_REASSEMBLY.
+ */
+#ifndef IP_FRAG
+#define IP_FRAG                         1
+#endif
+
+/**
+ * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally)
+ * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived
+ * in this time, the whole packet is discarded.
+ */
+#ifndef IP_REASS_MAXAGE
+#define IP_REASS_MAXAGE                 3
+#endif
+
+/**
+ * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled.
+ * Since the received pbufs are enqueued, be sure to configure
+ * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive
+ * packets even if the maximum amount of fragments is enqueued for reassembly!
+ */
+#ifndef IP_REASS_MAX_PBUFS
+#define IP_REASS_MAX_PBUFS              10
+#endif
+
+/**
+ * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP
+ * fragmentation. Otherwise pbufs are allocated and reference the original
+ * packet data to be fragmented (or with LWIP_NETIF_TX_SINGLE_PBUF==1,
+ * new PBUF_RAM pbufs are used for fragments).
+ * ATTENTION: IP_FRAG_USES_STATIC_BUF==1 may not be used for DMA-enabled MACs!
+ */
+#ifndef IP_FRAG_USES_STATIC_BUF
+#define IP_FRAG_USES_STATIC_BUF         0
+#endif
+
+/**
+ * IP_FRAG_MAX_MTU: Assumed max MTU on any interface for IP frag buffer
+ * (requires IP_FRAG_USES_STATIC_BUF==1)
+ */
+#if IP_FRAG_USES_STATIC_BUF && !defined(IP_FRAG_MAX_MTU)
+#define IP_FRAG_MAX_MTU                 1500
+#endif
+
+/**
+ * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers.
+ */
+#ifndef IP_DEFAULT_TTL
+#define IP_DEFAULT_TTL                  255
+#endif
+
+/**
+ * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast
+ * filter per pcb on udp and raw send operations. To enable broadcast filter
+ * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1.
+ */
+#ifndef IP_SOF_BROADCAST
+#define IP_SOF_BROADCAST                0
+#endif
+
+/**
+ * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast
+ * filter on recv operations.
+ */
+#ifndef IP_SOF_BROADCAST_RECV
+#define IP_SOF_BROADCAST_RECV           0
+#endif
+
+/*
+   ----------------------------------
+   ---------- ICMP options ----------
+   ----------------------------------
+*/
+/**
+ * LWIP_ICMP==1: Enable ICMP module inside the IP stack.
+ * Be careful, disable that make your product non-compliant to RFC1122
+ */
+#ifndef LWIP_ICMP
+#define LWIP_ICMP                       1
+#endif
+
+/**
+ * ICMP_TTL: Default value for Time-To-Live used by ICMP packets.
+ */
+#ifndef ICMP_TTL
+#define ICMP_TTL                       (IP_DEFAULT_TTL)
+#endif
+
+/**
+ * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only)
+ */
+#ifndef LWIP_BROADCAST_PING
+#define LWIP_BROADCAST_PING             0
+#endif
+
+/**
+ * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only)
+ */
+#ifndef LWIP_MULTICAST_PING
+#define LWIP_MULTICAST_PING             0
+#endif
+
+/*
+   ---------------------------------
+   ---------- RAW options ----------
+   ---------------------------------
+*/
+/**
+ * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
+ */
+#ifndef LWIP_RAW
+#define LWIP_RAW                        1
+#endif
+
+/**
+ * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
+ */
+#ifndef RAW_TTL
+#define RAW_TTL                        (IP_DEFAULT_TTL)
+#endif
+
+/*
+   ----------------------------------
+   ---------- DHCP options ----------
+   ----------------------------------
+*/
+/**
+ * LWIP_DHCP==1: Enable DHCP module.
+ */
+#ifndef LWIP_DHCP
+#define LWIP_DHCP                       0
+#endif
+
+/**
+ * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address.
+ */
+#ifndef DHCP_DOES_ARP_CHECK
+#define DHCP_DOES_ARP_CHECK             ((LWIP_DHCP) && (LWIP_ARP))
+#endif
+
+/*
+   ------------------------------------
+   ---------- AUTOIP options ----------
+   ------------------------------------
+*/
+/**
+ * LWIP_AUTOIP==1: Enable AUTOIP module.
+ */
+#ifndef LWIP_AUTOIP
+#define LWIP_AUTOIP                     0
+#endif
+
+/**
+ * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on
+ * the same interface at the same time.
+ */
+#ifndef LWIP_DHCP_AUTOIP_COOP
+#define LWIP_DHCP_AUTOIP_COOP           0
+#endif
+
+/**
+ * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes
+ * that should be sent before falling back on AUTOIP. This can be set
+ * as low as 1 to get an AutoIP address very quickly, but you should
+ * be prepared to handle a changing IP address when DHCP overrides
+ * AutoIP.
+ */
+#ifndef LWIP_DHCP_AUTOIP_COOP_TRIES
+#define LWIP_DHCP_AUTOIP_COOP_TRIES     9
+#endif
+
+/*
+   ----------------------------------
+   ---------- SNMP options ----------
+   ----------------------------------
+*/
+/**
+ * LWIP_SNMP==1: Turn on SNMP module. UDP must be available for SNMP
+ * transport.
+ */
+#ifndef LWIP_SNMP
+#define LWIP_SNMP                       0
+#endif
+
+/**
+ * SNMP_CONCURRENT_REQUESTS: Number of concurrent requests the module will
+ * allow. At least one request buffer is required.
+ * Does not have to be changed unless external MIBs answer request asynchronously
+ */
+#ifndef SNMP_CONCURRENT_REQUESTS
+#define SNMP_CONCURRENT_REQUESTS        1
+#endif
+
+/**
+ * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap
+ * destination is required
+ */
+#ifndef SNMP_TRAP_DESTINATIONS
+#define SNMP_TRAP_DESTINATIONS          1
+#endif
+
+/**
+ * SNMP_PRIVATE_MIB: 
+ * When using a private MIB, you have to create a file 'private_mib.h' that contains
+ * a 'struct mib_array_node mib_private' which contains your MIB.
+ */
+#ifndef SNMP_PRIVATE_MIB
+#define SNMP_PRIVATE_MIB                0
+#endif
+
+/**
+ * Only allow SNMP write actions that are 'safe' (e.g. disabeling netifs is not
+ * a safe action and disabled when SNMP_SAFE_REQUESTS = 1).
+ * Unsafe requests are disabled by default!
+ */
+#ifndef SNMP_SAFE_REQUESTS
+#define SNMP_SAFE_REQUESTS              1
+#endif
+
+/**
+ * The maximum length of strings used. This affects the size of
+ * MEMP_SNMP_VALUE elements.
+ */
+#ifndef SNMP_MAX_OCTET_STRING_LEN
+#define SNMP_MAX_OCTET_STRING_LEN       127
+#endif
+
+/**
+ * The maximum depth of the SNMP tree.
+ * With private MIBs enabled, this depends on your MIB!
+ * This affects the size of MEMP_SNMP_VALUE elements.
+ */
+#ifndef SNMP_MAX_TREE_DEPTH
+#define SNMP_MAX_TREE_DEPTH             15
+#endif
+
+/**
+ * The size of the MEMP_SNMP_VALUE elements, normally calculated from
+ * SNMP_MAX_OCTET_STRING_LEN and SNMP_MAX_TREE_DEPTH.
+ */
+#ifndef SNMP_MAX_VALUE_SIZE
+#define SNMP_MAX_VALUE_SIZE             LWIP_MAX((SNMP_MAX_OCTET_STRING_LEN)+1, sizeof(s32_t)*(SNMP_MAX_TREE_DEPTH))
+#endif
+
+/*
+   ----------------------------------
+   ---------- IGMP options ----------
+   ----------------------------------
+*/
+/**
+ * LWIP_IGMP==1: Turn on IGMP module. 
+ */
+#ifndef LWIP_IGMP
+#define LWIP_IGMP                       0
+#endif
+
+/*
+   ----------------------------------
+   ---------- DNS options -----------
+   ----------------------------------
+*/
+/**
+ * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS
+ * transport.
+ */
+#ifndef LWIP_DNS
+#define LWIP_DNS                        0
+#endif
+
+/** DNS maximum number of entries to maintain locally. */
+#ifndef DNS_TABLE_SIZE
+#define DNS_TABLE_SIZE                  4
+#endif
+
+/** DNS maximum host name length supported in the name table. */
+#ifndef DNS_MAX_NAME_LENGTH
+#define DNS_MAX_NAME_LENGTH             256
+#endif
+
+/** The maximum of DNS servers */
+#ifndef DNS_MAX_SERVERS
+#define DNS_MAX_SERVERS                 2
+#endif
+
+/** DNS do a name checking between the query and the response. */
+#ifndef DNS_DOES_NAME_CHECK
+#define DNS_DOES_NAME_CHECK             1
+#endif
+
+/** DNS message max. size. Default value is RFC compliant. */
+#ifndef DNS_MSG_SIZE
+#define DNS_MSG_SIZE                    512
+#endif
+
+/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled,
+ *  you have to define
+ *    #define DNS_LOCAL_HOSTLIST_INIT {{"host1", 0x123}, {"host2", 0x234}}
+ *  (an array of structs name/address, where address is an u32_t in network
+ *  byte order).
+ *
+ *  Instead, you can also use an external function:
+ *  #define DNS_LOOKUP_LOCAL_EXTERN(x) extern u32_t my_lookup_function(const char *name)
+ *  that returns the IP address or INADDR_NONE if not found.
+ */
+#ifndef DNS_LOCAL_HOSTLIST
+#define DNS_LOCAL_HOSTLIST              0
+#endif /* DNS_LOCAL_HOSTLIST */
+
+/** If this is turned on, the local host-list can be dynamically changed
+ *  at runtime. */
+#ifndef DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC   0
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+
+/*
+   ---------------------------------
+   ---------- UDP options ----------
+   ---------------------------------
+*/
+/**
+ * LWIP_UDP==1: Turn on UDP.
+ */
+#ifndef LWIP_UDP
+#define LWIP_UDP                        1
+#endif
+
+/**
+ * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP)
+ */
+#ifndef LWIP_UDPLITE
+#define LWIP_UDPLITE                    0
+#endif
+
+/**
+ * UDP_TTL: Default Time-To-Live value.
+ */
+#ifndef UDP_TTL
+#define UDP_TTL                         (IP_DEFAULT_TTL)
+#endif
+
+/**
+ * LWIP_NETBUF_RECVINFO==1: append destination addr and port to every netbuf.
+ */
+#ifndef LWIP_NETBUF_RECVINFO
+#define LWIP_NETBUF_RECVINFO            0
+#endif
+
+/*
+   ---------------------------------
+   ---------- TCP options ----------
+   ---------------------------------
+*/
+/**
+ * LWIP_TCP==1: Turn on TCP.
+ */
+#ifndef LWIP_TCP
+#define LWIP_TCP                        1
+#endif
+
+/**
+ * TCP_TTL: Default Time-To-Live value.
+ */
+#ifndef TCP_TTL
+#define TCP_TTL                         (IP_DEFAULT_TTL)
+#endif
+
+/**
+ * TCP_WND: The size of a TCP window.  This must be at least 
+ * (2 * TCP_MSS) for things to work well
+ */
+#ifndef TCP_WND
+#define TCP_WND                         (4 * TCP_MSS)
+#endif 
+
+/**
+ * TCP_MAXRTX: Maximum number of retransmissions of data segments.
+ */
+#ifndef TCP_MAXRTX
+#define TCP_MAXRTX                      12
+#endif
+
+/**
+ * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments.
+ */
+#ifndef TCP_SYNMAXRTX
+#define TCP_SYNMAXRTX                   6
+#endif
+
+/**
+ * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order.
+ * Define to 0 if your device is low on memory.
+ */
+#ifndef TCP_QUEUE_OOSEQ
+#define TCP_QUEUE_OOSEQ                 (LWIP_TCP)
+#endif
+
+/**
+ * TCP_MSS: TCP Maximum segment size. (default is 536, a conservative default,
+ * you might want to increase this.)
+ * For the receive side, this MSS is advertised to the remote side
+ * when opening a connection. For the transmit size, this MSS sets
+ * an upper limit on the MSS advertised by the remote host.
+ */
+#ifndef TCP_MSS
+#define TCP_MSS                         536
+#endif
+
+/**
+ * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really
+ * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which
+ * reflects the available reassembly buffer size at the remote host) and the
+ * largest size permitted by the IP layer" (RFC 1122)
+ * Setting this to 1 enables code that checks TCP_MSS against the MTU of the
+ * netif used for a connection and limits the MSS if it would be too big otherwise.
+ */
+#ifndef TCP_CALCULATE_EFF_SEND_MSS
+#define TCP_CALCULATE_EFF_SEND_MSS      1
+#endif
+
+
+/**
+ * TCP_SND_BUF: TCP sender buffer space (bytes). 
+ */
+#ifndef TCP_SND_BUF
+#define TCP_SND_BUF                     256
+#endif
+
+/**
+ * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least
+ * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work.
+ */
+#ifndef TCP_SND_QUEUELEN
+#define TCP_SND_QUEUELEN                ((4 * (TCP_SND_BUF) + (TCP_MSS - 1))/(TCP_MSS))
+#endif
+
+/**
+ * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than
+ * TCP_SND_BUF. It is the amount of space which must be available in the
+ * TCP snd_buf for select to return writable (combined with TCP_SNDQUEUELOWAT).
+ */
+#ifndef TCP_SNDLOWAT
+#define TCP_SNDLOWAT                    ((TCP_SND_BUF)/2)
+#endif
+
+/**
+ * TCP_SNDQUEUELOWAT: TCP writable bufs (pbuf count). This must be grater
+ * than TCP_SND_QUEUELEN. If the number of pbufs queued on a pcb drops below
+ * this number, select returns writable (combined with TCP_SNDLOWAT).
+ */
+#ifndef TCP_SNDQUEUELOWAT
+#define TCP_SNDQUEUELOWAT               ((TCP_SND_QUEUELEN)/2)
+#endif
+
+/**
+ * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb.
+ */
+#ifndef TCP_LISTEN_BACKLOG
+#define TCP_LISTEN_BACKLOG              0
+#endif
+
+/**
+ * The maximum allowed backlog for TCP listen netconns.
+ * This backlog is used unless another is explicitly specified.
+ * 0xff is the maximum (u8_t).
+ */
+#ifndef TCP_DEFAULT_LISTEN_BACKLOG
+#define TCP_DEFAULT_LISTEN_BACKLOG      0xff
+#endif
+
+/**
+ * TCP_OVERSIZE: The maximum number of bytes that tcp_write may
+ * allocate ahead of time in an attempt to create shorter pbuf chains
+ * for transmission. The meaningful range is 0 to TCP_MSS. Some
+ * suggested values are:
+ *
+ * 0:         Disable oversized allocation. Each tcp_write() allocates a new
+              pbuf (old behaviour).
+ * 1:         Allocate size-aligned pbufs with minimal excess. Use this if your
+ *            scatter-gather DMA requires aligned fragments.
+ * 128:       Limit the pbuf/memory overhead to 20%.
+ * TCP_MSS:   Try to create unfragmented TCP packets.
+ * TCP_MSS/4: Try to create 4 fragments or less per TCP packet.
+ */
+#ifndef TCP_OVERSIZE
+#define TCP_OVERSIZE                    TCP_MSS
+#endif
+
+/**
+ * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option.
+ */
+#ifndef LWIP_TCP_TIMESTAMPS
+#define LWIP_TCP_TIMESTAMPS             0
+#endif
+
+/**
+ * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an
+ * explicit window update
+ */
+#ifndef TCP_WND_UPDATE_THRESHOLD
+#define TCP_WND_UPDATE_THRESHOLD   (TCP_WND / 4)
+#endif
+
+/**
+ * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1.
+ *     LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all
+ *         events (accept, sent, etc) that happen in the system.
+ *     LWIP_CALLBACK_API==1: The PCB callback function is called directly
+ *         for the event.
+ */
+#ifndef LWIP_EVENT_API
+#define LWIP_EVENT_API                  0
+#define LWIP_CALLBACK_API               1
+#else 
+#define LWIP_EVENT_API                  1
+#define LWIP_CALLBACK_API               0
+#endif
+
+
+/*
+   ----------------------------------
+   ---------- Pbuf options ----------
+   ----------------------------------
+*/
+/**
+ * PBUF_LINK_HLEN: the number of bytes that should be allocated for a
+ * link level header. The default is 14, the standard value for
+ * Ethernet.
+ */
+#ifndef PBUF_LINK_HLEN
+#define PBUF_LINK_HLEN                  (14 + ETH_PAD_SIZE)
+#endif
+
+/**
+ * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is
+ * designed to accomodate single full size TCP frame in one pbuf, including
+ * TCP_MSS, IP header, and link header.
+ */
+#ifndef PBUF_POOL_BUFSIZE
+#define PBUF_POOL_BUFSIZE               LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN)
+#endif
+
+/*
+   ------------------------------------------------
+   ---------- Network Interfaces options ----------
+   ------------------------------------------------
+*/
+/**
+ * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname
+ * field.
+ */
+#ifndef LWIP_NETIF_HOSTNAME
+#define LWIP_NETIF_HOSTNAME             0
+#endif
+
+/**
+ * LWIP_NETIF_API==1: Support netif api (in netifapi.c)
+ */
+#ifndef LWIP_NETIF_API
+#define LWIP_NETIF_API                  0
+#endif
+
+/**
+ * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface
+ * changes its up/down status (i.e., due to DHCP IP acquistion)
+ */
+#ifndef LWIP_NETIF_STATUS_CALLBACK
+#define LWIP_NETIF_STATUS_CALLBACK      0
+#endif
+
+/**
+ * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface
+ * whenever the link changes (i.e., link down)
+ */
+#ifndef LWIP_NETIF_LINK_CALLBACK
+#define LWIP_NETIF_LINK_CALLBACK        0
+#endif
+
+/**
+ * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table
+ * indices) in struct netif. TCP and UDP can make use of this to prevent
+ * scanning the ARP table for every sent packet. While this is faster for big
+ * ARP tables or many concurrent connections, it might be counterproductive
+ * if you have a tiny ARP table or if there never are concurrent connections.
+ */
+#ifndef LWIP_NETIF_HWADDRHINT
+#define LWIP_NETIF_HWADDRHINT           0
+#endif
+
+/**
+ * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP
+ * address equal to the netif IP address, looping them back up the stack.
+ */
+#ifndef LWIP_NETIF_LOOPBACK
+#define LWIP_NETIF_LOOPBACK             0
+#endif
+
+/**
+ * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback
+ * sending for each netif (0 = disabled)
+ */
+#ifndef LWIP_LOOPBACK_MAX_PBUFS
+#define LWIP_LOOPBACK_MAX_PBUFS         0
+#endif
+
+/**
+ * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in
+ * the system, as netifs must change how they behave depending on this setting
+ * for the LWIP_NETIF_LOOPBACK option to work.
+ * Setting this is needed to avoid reentering non-reentrant functions like
+ * tcp_input().
+ *    LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a
+ *       multithreaded environment like tcpip.c. In this case, netif->input()
+ *       is called directly.
+ *    LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup.
+ *       The packets are put on a list and netif_poll() must be called in
+ *       the main application loop.
+ */
+#ifndef LWIP_NETIF_LOOPBACK_MULTITHREADING
+#define LWIP_NETIF_LOOPBACK_MULTITHREADING    (!NO_SYS)
+#endif
+
+/**
+ * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data
+ * to be sent into one single pbuf. This is for compatibility with DMA-enabled
+ * MACs that do not support scatter-gather.
+ * Beware that this might involve CPU-memcpy before transmitting that would not
+ * be needed without this flag! Use this only if you need to!
+ *
+ * @todo: TCP and IP-frag do not work with this, yet:
+ */
+#ifndef LWIP_NETIF_TX_SINGLE_PBUF
+#define LWIP_NETIF_TX_SINGLE_PBUF             0
+#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
+
+/*
+   ------------------------------------
+   ---------- LOOPIF options ----------
+   ------------------------------------
+*/
+/**
+ * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c
+ */
+#ifndef LWIP_HAVE_LOOPIF
+#define LWIP_HAVE_LOOPIF                0
+#endif
+
+/*
+   ------------------------------------
+   ---------- SLIPIF options ----------
+   ------------------------------------
+*/
+/**
+ * LWIP_HAVE_SLIPIF==1: Support slip interface and slipif.c
+ */
+#ifndef LWIP_HAVE_SLIPIF
+#define LWIP_HAVE_SLIPIF                0
+#endif
+
+/*
+   ------------------------------------
+   ---------- Thread options ----------
+   ------------------------------------
+*/
+/**
+ * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread.
+ */
+#ifndef TCPIP_THREAD_NAME
+#define TCPIP_THREAD_NAME              "tcpip_thread"
+#endif
+
+/**
+ * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef TCPIP_THREAD_STACKSIZE
+#define TCPIP_THREAD_STACKSIZE          0
+#endif
+
+/**
+ * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef TCPIP_THREAD_PRIO
+#define TCPIP_THREAD_PRIO               1
+#endif
+
+/**
+ * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages
+ * The queue size value itself is platform-dependent, but is passed to
+ * sys_mbox_new() when tcpip_init is called.
+ */
+#ifndef TCPIP_MBOX_SIZE
+#define TCPIP_MBOX_SIZE                 0
+#endif
+
+/**
+ * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread.
+ */
+#ifndef SLIPIF_THREAD_NAME
+#define SLIPIF_THREAD_NAME             "slipif_loop"
+#endif
+
+/**
+ * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef SLIPIF_THREAD_STACKSIZE
+#define SLIPIF_THREAD_STACKSIZE         0
+#endif
+
+/**
+ * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef SLIPIF_THREAD_PRIO
+#define SLIPIF_THREAD_PRIO              1
+#endif
+
+/**
+ * PPP_THREAD_NAME: The name assigned to the pppInputThread.
+ */
+#ifndef PPP_THREAD_NAME
+#define PPP_THREAD_NAME                "pppInputThread"
+#endif
+
+/**
+ * PPP_THREAD_STACKSIZE: The stack size used by the pppInputThread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef PPP_THREAD_STACKSIZE
+#define PPP_THREAD_STACKSIZE            0
+#endif
+
+/**
+ * PPP_THREAD_PRIO: The priority assigned to the pppInputThread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef PPP_THREAD_PRIO
+#define PPP_THREAD_PRIO                 1
+#endif
+
+/**
+ * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread.
+ */
+#ifndef DEFAULT_THREAD_NAME
+#define DEFAULT_THREAD_NAME            "lwIP"
+#endif
+
+/**
+ * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef DEFAULT_THREAD_STACKSIZE
+#define DEFAULT_THREAD_STACKSIZE        0
+#endif
+
+/**
+ * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef DEFAULT_THREAD_PRIO
+#define DEFAULT_THREAD_PRIO             1
+#endif
+
+/**
+ * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#ifndef DEFAULT_RAW_RECVMBOX_SIZE
+#define DEFAULT_RAW_RECVMBOX_SIZE       0
+#endif
+
+/**
+ * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#ifndef DEFAULT_UDP_RECVMBOX_SIZE
+#define DEFAULT_UDP_RECVMBOX_SIZE       0
+#endif
+
+/**
+ * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#ifndef DEFAULT_TCP_RECVMBOX_SIZE
+#define DEFAULT_TCP_RECVMBOX_SIZE       0
+#endif
+
+/**
+ * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections.
+ * The queue size value itself is platform-dependent, but is passed to
+ * sys_mbox_new() when the acceptmbox is created.
+ */
+#ifndef DEFAULT_ACCEPTMBOX_SIZE
+#define DEFAULT_ACCEPTMBOX_SIZE         0
+#endif
+
+/*
+   ----------------------------------------------
+   ---------- Sequential layer options ----------
+   ----------------------------------------------
+*/
+/**
+ * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!)
+ * Don't use it if you're not an active lwIP project member
+ */
+#ifndef LWIP_TCPIP_CORE_LOCKING
+#define LWIP_TCPIP_CORE_LOCKING         0
+#endif
+
+/**
+ * LWIP_TCPIP_CORE_LOCKING_INPUT: (EXPERIMENTAL!)
+ * Don't use it if you're not an active lwIP project member
+ */
+#ifndef LWIP_TCPIP_CORE_LOCKING_INPUT
+#define LWIP_TCPIP_CORE_LOCKING_INPUT   0
+#endif
+
+/**
+ * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c)
+ */
+#ifndef LWIP_NETCONN
+#define LWIP_NETCONN                    1
+#endif
+
+/** LWIP_TCPIP_TIMEOUT==1: Enable tcpip_timeout/tcpip_untimeout tod create
+ * timers running in tcpip_thread from another thread.
+ */
+#ifndef LWIP_TCPIP_TIMEOUT
+#define LWIP_TCPIP_TIMEOUT              1
+#endif
+
+/*
+   ------------------------------------
+   ---------- Socket options ----------
+   ------------------------------------
+*/
+/**
+ * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)
+ */
+#ifndef LWIP_SOCKET
+#define LWIP_SOCKET                     1
+#endif
+
+/**
+ * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names.
+ * (only used if you use sockets.c)
+ */
+#ifndef LWIP_COMPAT_SOCKETS
+#define LWIP_COMPAT_SOCKETS             1
+#endif
+
+/**
+ * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names.
+ * Disable this option if you use a POSIX operating system that uses the same
+ * names (read, write & close). (only used if you use sockets.c)
+ */
+#ifndef LWIP_POSIX_SOCKETS_IO_NAMES
+#define LWIP_POSIX_SOCKETS_IO_NAMES     1
+#endif
+
+/**
+ * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT
+ * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set
+ * in seconds. (does not require sockets.c, and will affect tcp.c)
+ */
+#ifndef LWIP_TCP_KEEPALIVE
+#define LWIP_TCP_KEEPALIVE              0
+#endif
+
+/**
+ * LWIP_SO_RCVTIMEO==1: Enable SO_RCVTIMEO processing.
+ */
+#ifndef LWIP_SO_RCVTIMEO
+#define LWIP_SO_RCVTIMEO                0
+#endif
+
+/**
+ * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing.
+ */
+#ifndef LWIP_SO_RCVBUF
+#define LWIP_SO_RCVBUF                  0
+#endif
+
+/**
+ * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize.
+ */
+#ifndef RECV_BUFSIZE_DEFAULT
+#define RECV_BUFSIZE_DEFAULT            INT_MAX
+#endif
+
+/**
+ * SO_REUSE==1: Enable SO_REUSEADDR option.
+ */
+#ifndef SO_REUSE
+#define SO_REUSE                        0
+#endif
+
+/**
+ * SO_REUSE_RXTOALL==1: Pass a copy of incoming broadcast/multicast packets
+ * to all local matches if SO_REUSEADDR is turned on.
+ * WARNING: Adds a memcpy for every packet if passing to more than one pcb!
+ */
+#ifndef SO_REUSE_RXTOALL
+#define SO_REUSE_RXTOALL                0
+#endif
+
+/*
+   ----------------------------------------
+   ---------- Statistics options ----------
+   ----------------------------------------
+*/
+/**
+ * LWIP_STATS==1: Enable statistics collection in lwip_stats.
+ */
+#ifndef LWIP_STATS
+#define LWIP_STATS                      1
+#endif
+
+#if LWIP_STATS
+
+/**
+ * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions.
+ */
+#ifndef LWIP_STATS_DISPLAY
+#define LWIP_STATS_DISPLAY              0
+#endif
+
+/**
+ * LINK_STATS==1: Enable link stats.
+ */
+#ifndef LINK_STATS
+#define LINK_STATS                      1
+#endif
+
+/**
+ * ETHARP_STATS==1: Enable etharp stats.
+ */
+#ifndef ETHARP_STATS
+#define ETHARP_STATS                    (LWIP_ARP)
+#endif
+
+/**
+ * IP_STATS==1: Enable IP stats.
+ */
+#ifndef IP_STATS
+#define IP_STATS                        1
+#endif
+
+/**
+ * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is
+ * on if using either frag or reass.
+ */
+#ifndef IPFRAG_STATS
+#define IPFRAG_STATS                    (IP_REASSEMBLY || IP_FRAG)
+#endif
+
+/**
+ * ICMP_STATS==1: Enable ICMP stats.
+ */
+#ifndef ICMP_STATS
+#define ICMP_STATS                      1
+#endif
+
+/**
+ * IGMP_STATS==1: Enable IGMP stats.
+ */
+#ifndef IGMP_STATS
+#define IGMP_STATS                      (LWIP_IGMP)
+#endif
+
+/**
+ * UDP_STATS==1: Enable UDP stats. Default is on if
+ * UDP enabled, otherwise off.
+ */
+#ifndef UDP_STATS
+#define UDP_STATS                       (LWIP_UDP)
+#endif
+
+/**
+ * TCP_STATS==1: Enable TCP stats. Default is on if TCP
+ * enabled, otherwise off.
+ */
+#ifndef TCP_STATS
+#define TCP_STATS                       (LWIP_TCP)
+#endif
+
+/**
+ * MEM_STATS==1: Enable mem.c stats.
+ */
+#ifndef MEM_STATS
+#define MEM_STATS                       ((MEM_LIBC_MALLOC == 0) && (MEM_USE_POOLS == 0))
+#endif
+
+/**
+ * MEMP_STATS==1: Enable memp.c pool stats.
+ */
+#ifndef MEMP_STATS
+#define MEMP_STATS                      (MEMP_MEM_MALLOC == 0)
+#endif
+
+/**
+ * SYS_STATS==1: Enable system stats (sem and mbox counts, etc).
+ */
+#ifndef SYS_STATS
+#define SYS_STATS                       (NO_SYS == 0)
+#endif
+
+#else
+
+#define LINK_STATS                      0
+#define IP_STATS                        0
+#define IPFRAG_STATS                    0
+#define ICMP_STATS                      0
+#define IGMP_STATS                      0
+#define UDP_STATS                       0
+#define TCP_STATS                       0
+#define MEM_STATS                       0
+#define MEMP_STATS                      0
+#define SYS_STATS                       0
+#define LWIP_STATS_DISPLAY              0
+
+#endif /* LWIP_STATS */
+
+/*
+   ---------------------------------
+   ---------- PPP options ----------
+   ---------------------------------
+*/
+/**
+ * PPP_SUPPORT==1: Enable PPP.
+ */
+#ifndef PPP_SUPPORT
+#define PPP_SUPPORT                     0
+#endif
+
+/**
+ * PPPOE_SUPPORT==1: Enable PPP Over Ethernet
+ */
+#ifndef PPPOE_SUPPORT
+#define PPPOE_SUPPORT                   0
+#endif
+
+/**
+ * PPPOS_SUPPORT==1: Enable PPP Over Serial
+ */
+#ifndef PPPOS_SUPPORT
+#define PPPOS_SUPPORT                   PPP_SUPPORT
+#endif
+
+#if PPP_SUPPORT
+
+/**
+ * NUM_PPP: Max PPP sessions.
+ */
+#ifndef NUM_PPP
+#define NUM_PPP                         1
+#endif
+
+/**
+ * PAP_SUPPORT==1: Support PAP.
+ */
+#ifndef PAP_SUPPORT
+#define PAP_SUPPORT                     0
+#endif
+
+/**
+ * CHAP_SUPPORT==1: Support CHAP.
+ */
+#ifndef CHAP_SUPPORT
+#define CHAP_SUPPORT                    0
+#endif
+
+/**
+ * MSCHAP_SUPPORT==1: Support MSCHAP. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef MSCHAP_SUPPORT
+#define MSCHAP_SUPPORT                  0
+#endif
+
+/**
+ * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef CBCP_SUPPORT
+#define CBCP_SUPPORT                    0
+#endif
+
+/**
+ * CCP_SUPPORT==1: Support CCP. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef CCP_SUPPORT
+#define CCP_SUPPORT                     0
+#endif
+
+/**
+ * VJ_SUPPORT==1: Support VJ header compression.
+ */
+#ifndef VJ_SUPPORT
+#define VJ_SUPPORT                      0
+#endif
+
+/**
+ * MD5_SUPPORT==1: Support MD5 (see also CHAP).
+ */
+#ifndef MD5_SUPPORT
+#define MD5_SUPPORT                     0
+#endif
+
+/*
+ * Timeouts
+ */
+#ifndef FSM_DEFTIMEOUT
+#define FSM_DEFTIMEOUT                  6       /* Timeout time in seconds */
+#endif
+
+#ifndef FSM_DEFMAXTERMREQS
+#define FSM_DEFMAXTERMREQS              2       /* Maximum Terminate-Request transmissions */
+#endif
+
+#ifndef FSM_DEFMAXCONFREQS
+#define FSM_DEFMAXCONFREQS              10      /* Maximum Configure-Request transmissions */
+#endif
+
+#ifndef FSM_DEFMAXNAKLOOPS
+#define FSM_DEFMAXNAKLOOPS              5       /* Maximum number of nak loops */
+#endif
+
+#ifndef UPAP_DEFTIMEOUT
+#define UPAP_DEFTIMEOUT                 6       /* Timeout (seconds) for retransmitting req */
+#endif
+
+#ifndef UPAP_DEFREQTIME
+#define UPAP_DEFREQTIME                 30      /* Time to wait for auth-req from peer */
+#endif
+
+#ifndef CHAP_DEFTIMEOUT
+#define CHAP_DEFTIMEOUT                 6       /* Timeout time in seconds */
+#endif
+
+#ifndef CHAP_DEFTRANSMITS
+#define CHAP_DEFTRANSMITS               10      /* max # times to send challenge */
+#endif
+
+/* Interval in seconds between keepalive echo requests, 0 to disable. */
+#ifndef LCP_ECHOINTERVAL
+#define LCP_ECHOINTERVAL                0
+#endif
+
+/* Number of unanswered echo requests before failure. */
+#ifndef LCP_MAXECHOFAILS
+#define LCP_MAXECHOFAILS                3
+#endif
+
+/* Max Xmit idle time (in jiffies) before resend flag char. */
+#ifndef PPP_MAXIDLEFLAG
+#define PPP_MAXIDLEFLAG                 100
+#endif
+
+/*
+ * Packet sizes
+ *
+ * Note - lcp shouldn't be allowed to negotiate stuff outside these
+ *    limits.  See lcp.h in the pppd directory.
+ * (XXX - these constants should simply be shared by lcp.c instead
+ *    of living in lcp.h)
+ */
+#define PPP_MTU                         1500     /* Default MTU (size of Info field) */
+#ifndef PPP_MAXMTU
+/* #define PPP_MAXMTU  65535 - (PPP_HDRLEN + PPP_FCSLEN) */
+#define PPP_MAXMTU                      1500 /* Largest MTU we allow */
+#endif
+#define PPP_MINMTU                      64
+#define PPP_MRU                         1500     /* default MRU = max length of info field */
+#define PPP_MAXMRU                      1500     /* Largest MRU we allow */
+#ifndef PPP_DEFMRU
+#define PPP_DEFMRU                      296             /* Try for this */
+#endif
+#define PPP_MINMRU                      128             /* No MRUs below this */
+
+#ifndef MAXNAMELEN
+#define MAXNAMELEN                      256     /* max length of hostname or name for auth */
+#endif
+#ifndef MAXSECRETLEN
+#define MAXSECRETLEN                    256     /* max length of password or secret */
+#endif
+
+#endif /* PPP_SUPPORT */
+
+/*
+   --------------------------------------
+   ---------- Checksum options ----------
+   --------------------------------------
+*/
+/**
+ * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.
+ */
+#ifndef CHECKSUM_GEN_IP
+#define CHECKSUM_GEN_IP                 1
+#endif
+ 
+/**
+ * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.
+ */
+#ifndef CHECKSUM_GEN_UDP
+#define CHECKSUM_GEN_UDP                1
+#endif
+ 
+/**
+ * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.
+ */
+#ifndef CHECKSUM_GEN_TCP
+#define CHECKSUM_GEN_TCP                1
+#endif
+ 
+/**
+ * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.
+ */
+#ifndef CHECKSUM_CHECK_IP
+#define CHECKSUM_CHECK_IP               1
+#endif
+ 
+/**
+ * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.
+ */
+#ifndef CHECKSUM_CHECK_UDP
+#define CHECKSUM_CHECK_UDP              1
+#endif
+
+/**
+ * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.
+ */
+#ifndef CHECKSUM_CHECK_TCP
+#define CHECKSUM_CHECK_TCP              1
+#endif
+
+/**
+ * LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from
+ * application buffers to pbufs.
+ */
+#ifndef LWIP_CHECKSUM_ON_COPY
+#define LWIP_CHECKSUM_ON_COPY           0
+#endif
+
+/*
+   ---------------------------------------
+   ---------- Debugging options ----------
+   ---------------------------------------
+*/
+/**
+ * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is
+ * compared against this value. If it is smaller, then debugging
+ * messages are written.
+ */
+#ifndef LWIP_DBG_MIN_LEVEL
+#define LWIP_DBG_MIN_LEVEL              LWIP_DBG_LEVEL_ALL
+#endif
+
+/**
+ * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable
+ * debug messages of certain types.
+ */
+#ifndef LWIP_DBG_TYPES_ON
+#define LWIP_DBG_TYPES_ON               LWIP_DBG_ON
+#endif
+
+/**
+ * ETHARP_DEBUG: Enable debugging in etharp.c.
+ */
+#ifndef ETHARP_DEBUG
+#define ETHARP_DEBUG                    LWIP_DBG_OFF
+#endif
+
+/**
+ * NETIF_DEBUG: Enable debugging in netif.c.
+ */
+#ifndef NETIF_DEBUG
+#define NETIF_DEBUG                     LWIP_DBG_OFF
+#endif
+
+/**
+ * PBUF_DEBUG: Enable debugging in pbuf.c.
+ */
+#ifndef PBUF_DEBUG
+#define PBUF_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * API_LIB_DEBUG: Enable debugging in api_lib.c.
+ */
+#ifndef API_LIB_DEBUG
+#define API_LIB_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * API_MSG_DEBUG: Enable debugging in api_msg.c.
+ */
+#ifndef API_MSG_DEBUG
+#define API_MSG_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * SOCKETS_DEBUG: Enable debugging in sockets.c.
+ */
+#ifndef SOCKETS_DEBUG
+#define SOCKETS_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * ICMP_DEBUG: Enable debugging in icmp.c.
+ */
+#ifndef ICMP_DEBUG
+#define ICMP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * IGMP_DEBUG: Enable debugging in igmp.c.
+ */
+#ifndef IGMP_DEBUG
+#define IGMP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * INET_DEBUG: Enable debugging in inet.c.
+ */
+#ifndef INET_DEBUG
+#define INET_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * IP_DEBUG: Enable debugging for IP.
+ */
+#ifndef IP_DEBUG
+#define IP_DEBUG                        LWIP_DBG_OFF
+#endif
+
+/**
+ * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass.
+ */
+#ifndef IP_REASS_DEBUG
+#define IP_REASS_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * RAW_DEBUG: Enable debugging in raw.c.
+ */
+#ifndef RAW_DEBUG
+#define RAW_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * MEM_DEBUG: Enable debugging in mem.c.
+ */
+#ifndef MEM_DEBUG
+#define MEM_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * MEMP_DEBUG: Enable debugging in memp.c.
+ */
+#ifndef MEMP_DEBUG
+#define MEMP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * SYS_DEBUG: Enable debugging in sys.c.
+ */
+#ifndef SYS_DEBUG
+#define SYS_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * TIMERS_DEBUG: Enable debugging in timers.c.
+ */
+#ifndef TIMERS_DEBUG
+#define TIMERS_DEBUG                    LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_DEBUG: Enable debugging for TCP.
+ */
+#ifndef TCP_DEBUG
+#define TCP_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug.
+ */
+#ifndef TCP_INPUT_DEBUG
+#define TCP_INPUT_DEBUG                 LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit.
+ */
+#ifndef TCP_FR_DEBUG
+#define TCP_FR_DEBUG                    LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit
+ * timeout.
+ */
+#ifndef TCP_RTO_DEBUG
+#define TCP_RTO_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_CWND_DEBUG: Enable debugging for TCP congestion window.
+ */
+#ifndef TCP_CWND_DEBUG
+#define TCP_CWND_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating.
+ */
+#ifndef TCP_WND_DEBUG
+#define TCP_WND_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions.
+ */
+#ifndef TCP_OUTPUT_DEBUG
+#define TCP_OUTPUT_DEBUG                LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_RST_DEBUG: Enable debugging for TCP with the RST message.
+ */
+#ifndef TCP_RST_DEBUG
+#define TCP_RST_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths.
+ */
+#ifndef TCP_QLEN_DEBUG
+#define TCP_QLEN_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * UDP_DEBUG: Enable debugging in UDP.
+ */
+#ifndef UDP_DEBUG
+#define UDP_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * TCPIP_DEBUG: Enable debugging in tcpip.c.
+ */
+#ifndef TCPIP_DEBUG
+#define TCPIP_DEBUG                     LWIP_DBG_OFF
+#endif
+
+/**
+ * PPP_DEBUG: Enable debugging for PPP.
+ */
+#ifndef PPP_DEBUG
+#define PPP_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * SLIP_DEBUG: Enable debugging in slipif.c.
+ */
+#ifndef SLIP_DEBUG
+#define SLIP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * DHCP_DEBUG: Enable debugging in dhcp.c.
+ */
+#ifndef DHCP_DEBUG
+#define DHCP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * AUTOIP_DEBUG: Enable debugging in autoip.c.
+ */
+#ifndef AUTOIP_DEBUG
+#define AUTOIP_DEBUG                    LWIP_DBG_OFF
+#endif
+
+/**
+ * SNMP_MSG_DEBUG: Enable debugging for SNMP messages.
+ */
+#ifndef SNMP_MSG_DEBUG
+#define SNMP_MSG_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs.
+ */
+#ifndef SNMP_MIB_DEBUG
+#define SNMP_MIB_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * DNS_DEBUG: Enable debugging for DNS.
+ */
+#ifndef DNS_DEBUG
+#define DNS_DEBUG                       LWIP_DBG_OFF
+#endif
+
+#endif /* __LWIP_OPT_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/pbuf.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/pbuf.h
new file mode 100644
index 0000000..3b1d608
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/pbuf.h
@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef __LWIP_PBUF_H__
+#define __LWIP_PBUF_H__
+
+#include "lwip/opt.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Currently, the pbuf_custom code is only needed for one specific configuration
+ * of IP_FRAG */
+#define LWIP_SUPPORT_CUSTOM_PBUF (IP_FRAG && !IP_FRAG_USES_STATIC_BUF && !LWIP_NETIF_TX_SINGLE_PBUF)
+
+#define PBUF_TRANSPORT_HLEN 20
+#define PBUF_IP_HLEN        20
+
+typedef enum {
+  PBUF_TRANSPORT,
+  PBUF_IP,
+  PBUF_LINK,
+  PBUF_RAW
+} pbuf_layer;
+
+typedef enum {
+  PBUF_RAM, /* pbuf data is stored in RAM */
+  PBUF_ROM, /* pbuf data is stored in ROM */
+  PBUF_REF, /* pbuf comes from the pbuf pool */
+  PBUF_POOL /* pbuf payload refers to RAM */
+} pbuf_type;
+
+
+/** indicates this packet's data should be immediately passed to the application */
+#define PBUF_FLAG_PUSH      0x01U
+/** indicates this is a custom pbuf: pbuf_free and pbuf_header handle such a
+    a pbuf differently */
+#define PBUF_FLAG_IS_CUSTOM 0x02U
+/** indicates this pbuf is UDP multicast to be looped back */
+#define PBUF_FLAG_MCASTLOOP 0x04U
+
+struct pbuf {
+  /** next pbuf in singly linked pbuf chain */
+  struct pbuf *next;
+
+  /** pointer to the actual data in the buffer */
+  void *payload;
+
+  /**
+   * total length of this buffer and all next buffers in chain
+   * belonging to the same packet.
+   *
+   * For non-queue packet chains this is the invariant:
+   * p->tot_len == p->len + (p->next? p->next->tot_len: 0)
+   */
+  u16_t tot_len;
+
+  /** length of this buffer */
+  u16_t len;
+
+  /** pbuf_type as u8_t instead of enum to save space */
+  u8_t /*pbuf_type*/ type;
+
+  /** misc flags */
+  u8_t flags;
+
+  /**
+   * the reference count always equals the number of pointers
+   * that refer to this pbuf. This can be pointers from an application,
+   * the stack itself, or pbuf->next pointers from a chain.
+   */
+  u16_t ref;
+};
+
+#if LWIP_SUPPORT_CUSTOM_PBUF
+/** Prototype for a function to free a custom pbuf */
+typedef void (*pbuf_free_custom_fn)(struct pbuf *p);
+
+/** A custom pbuf: like a pbuf, but following a function pointer to free it. */
+struct pbuf_custom {
+  /** The actual pbuf */
+  struct pbuf pbuf;
+  /** This function is called when pbuf_free deallocates this pbuf(_custom) */
+  pbuf_free_custom_fn custom_free_function;
+};
+#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
+
+/* Initializes the pbuf module. This call is empty for now, but may not be in future. */
+#define pbuf_init()
+
+struct pbuf *pbuf_alloc(pbuf_layer l, u16_t length, pbuf_type type);
+#if LWIP_SUPPORT_CUSTOM_PBUF
+struct pbuf *pbuf_alloced_custom(pbuf_layer l, u16_t length, pbuf_type type,
+                                 struct pbuf_custom *p, void *payload_mem,
+                                 u16_t payload_mem_len);
+#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
+void pbuf_realloc(struct pbuf *p, u16_t size); 
+u8_t pbuf_header(struct pbuf *p, s16_t header_size);
+void pbuf_ref(struct pbuf *p);
+u8_t pbuf_free(struct pbuf *p);
+u8_t pbuf_clen(struct pbuf *p);  
+void pbuf_cat(struct pbuf *head, struct pbuf *tail);
+void pbuf_chain(struct pbuf *head, struct pbuf *tail);
+struct pbuf *pbuf_dechain(struct pbuf *p);
+err_t pbuf_copy(struct pbuf *p_to, struct pbuf *p_from);
+u16_t pbuf_copy_partial(struct pbuf *p, void *dataptr, u16_t len, u16_t offset);
+err_t pbuf_take(struct pbuf *buf, const void *dataptr, u16_t len);
+struct pbuf *pbuf_coalesce(struct pbuf *p, pbuf_layer layer);
+#if LWIP_CHECKSUM_ON_COPY
+err_t pbuf_fill_chksum(struct pbuf *p, u16_t start_offset, const void *dataptr,
+                       u16_t len, u16_t *chksum);
+#endif /* LWIP_CHECKSUM_ON_COPY */
+
+u8_t pbuf_get_at(struct pbuf* p, u16_t offset);
+u16_t pbuf_memcmp(struct pbuf* p, u16_t offset, const void* s2, u16_t n);
+u16_t pbuf_memfind(struct pbuf* p, const void* mem, u16_t mem_len, u16_t start_offset);
+u16_t pbuf_strstr(struct pbuf* p, const char* substr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_PBUF_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/raw.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/raw.h
new file mode 100644
index 0000000..17d0a1c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/raw.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_RAW_H__
+#define __LWIP_RAW_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/def.h"
+#include "lwip/ip.h"
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct raw_pcb;
+
+/** Function prototype for raw pcb receive callback functions.
+ * @param arg user supplied argument (raw_pcb.recv_arg)
+ * @param pcb the raw_pcb which received data
+ * @param p the packet buffer that was received
+ * @param addr the remote IP address from which the packet was received
+ * @return 1 if the packet was 'eaten' (aka. deleted),
+ *         0 if the packet lives on
+ * If returning 1, the callback is responsible for freeing the pbuf
+ * if it's not used any more.
+ */
+typedef u8_t (*raw_recv_fn)(void *arg, struct raw_pcb *pcb, struct pbuf *p,
+    ip_addr_t *addr);
+
+struct raw_pcb {
+  /* Common members of all PCB types */
+  IP_PCB;
+
+  struct raw_pcb *next;
+
+  u8_t protocol;
+
+  /** receive callback function */
+  raw_recv_fn recv;
+  /* user-supplied argument for the recv callback */
+  void *recv_arg;
+};
+
+/* The following functions is the application layer interface to the
+   RAW code. */
+struct raw_pcb * raw_new        (u8_t proto);
+void             raw_remove     (struct raw_pcb *pcb);
+err_t            raw_bind       (struct raw_pcb *pcb, ip_addr_t *ipaddr);
+err_t            raw_connect    (struct raw_pcb *pcb, ip_addr_t *ipaddr);
+
+void             raw_recv       (struct raw_pcb *pcb, raw_recv_fn recv, void *recv_arg);
+err_t            raw_sendto     (struct raw_pcb *pcb, struct pbuf *p, ip_addr_t *ipaddr);
+err_t            raw_send       (struct raw_pcb *pcb, struct pbuf *p);
+
+/* The following functions are the lower layer interface to RAW. */
+u8_t             raw_input      (struct pbuf *p, struct netif *inp);
+#define raw_init() /* Compatibility define, not init needed. */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_RAW */
+
+#endif /* __LWIP_RAW_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/sio.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/sio.h
new file mode 100644
index 0000000..28ae2f2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/sio.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ */
+
+/*
+ * This is the interface to the platform specific serial IO module
+ * It needs to be implemented by those platforms which need SLIP or PPP
+ */
+
+#ifndef __SIO_H__
+#define __SIO_H__
+
+#include "lwip/arch.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* If you want to define sio_fd_t elsewhere or differently,
+   define this in your cc.h file. */
+#ifndef __sio_fd_t_defined
+typedef void * sio_fd_t;
+#endif
+
+/* The following functions can be defined to something else in your cc.h file
+   or be implemented in your custom sio.c file. */
+
+#ifndef sio_open
+/**
+ * Opens a serial device for communication.
+ * 
+ * @param devnum device number
+ * @return handle to serial device if successful, NULL otherwise
+ */
+sio_fd_t sio_open(u8_t devnum);
+#endif
+
+#ifndef sio_send
+/**
+ * Sends a single character to the serial device.
+ * 
+ * @param c character to send
+ * @param fd serial device handle
+ * 
+ * @note This function will block until the character can be sent.
+ */
+void sio_send(u8_t c, sio_fd_t fd);
+#endif
+
+#ifndef sio_recv
+/**
+ * Receives a single character from the serial device.
+ * 
+ * @param fd serial device handle
+ * 
+ * @note This function will block until a character is received.
+ */
+u8_t sio_recv(sio_fd_t fd);
+#endif
+
+#ifndef sio_read
+/**
+ * Reads from the serial device.
+ * 
+ * @param fd serial device handle
+ * @param data pointer to data buffer for receiving
+ * @param len maximum length (in bytes) of data to receive
+ * @return number of bytes actually received - may be 0 if aborted by sio_read_abort
+ * 
+ * @note This function will block until data can be received. The blocking
+ * can be cancelled by calling sio_read_abort().
+ */
+u32_t sio_read(sio_fd_t fd, u8_t *data, u32_t len);
+#endif
+
+#ifndef sio_tryread
+/**
+ * Tries to read from the serial device. Same as sio_read but returns
+ * immediately if no data is available and never blocks.
+ * 
+ * @param fd serial device handle
+ * @param data pointer to data buffer for receiving
+ * @param len maximum length (in bytes) of data to receive
+ * @return number of bytes actually received
+ */
+u32_t sio_tryread(sio_fd_t fd, u8_t *data, u32_t len);
+#endif
+
+#ifndef sio_write
+/**
+ * Writes to the serial device.
+ * 
+ * @param fd serial device handle
+ * @param data pointer to data to send
+ * @param len length (in bytes) of data to send
+ * @return number of bytes actually sent
+ * 
+ * @note This function will block until all data can be sent.
+ */
+u32_t sio_write(sio_fd_t fd, u8_t *data, u32_t len);
+#endif
+
+#ifndef sio_read_abort
+/**
+ * Aborts a blocking sio_read() call.
+ * 
+ * @param fd serial device handle
+ */
+void sio_read_abort(sio_fd_t fd);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SIO_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp.h
new file mode 100644
index 0000000..2ed043d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp.h
@@ -0,0 +1,367 @@
+/*
+ * Copyright (c) 2001, 2002 Leon Woestenberg 
+ * Copyright (c) 2001, 2002 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Leon Woestenberg 
+ *
+ */
+#ifndef __LWIP_SNMP_H__
+#define __LWIP_SNMP_H__
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lwip/ip_addr.h"
+
+struct udp_pcb;
+struct netif;
+
+/**
+ * @see RFC1213, "MIB-II, 6. Definitions"
+ */
+enum snmp_ifType {
+  snmp_ifType_other=1,                /* none of the following */
+  snmp_ifType_regular1822,
+  snmp_ifType_hdh1822,
+  snmp_ifType_ddn_x25,
+  snmp_ifType_rfc877_x25,
+  snmp_ifType_ethernet_csmacd,
+  snmp_ifType_iso88023_csmacd,
+  snmp_ifType_iso88024_tokenBus,
+  snmp_ifType_iso88025_tokenRing,
+  snmp_ifType_iso88026_man,
+  snmp_ifType_starLan,
+  snmp_ifType_proteon_10Mbit,
+  snmp_ifType_proteon_80Mbit,
+  snmp_ifType_hyperchannel,
+  snmp_ifType_fddi,
+  snmp_ifType_lapb,
+  snmp_ifType_sdlc,
+  snmp_ifType_ds1,                    /* T-1 */
+  snmp_ifType_e1,                     /* european equiv. of T-1 */
+  snmp_ifType_basicISDN,
+  snmp_ifType_primaryISDN,            /* proprietary serial */
+  snmp_ifType_propPointToPointSerial,
+  snmp_ifType_ppp,
+  snmp_ifType_softwareLoopback,
+  snmp_ifType_eon,                    /* CLNP over IP [11] */
+  snmp_ifType_ethernet_3Mbit,
+  snmp_ifType_nsip,                   /* XNS over IP */
+  snmp_ifType_slip,                   /* generic SLIP */
+  snmp_ifType_ultra,                  /* ULTRA technologies */
+  snmp_ifType_ds3,                    /* T-3 */
+  snmp_ifType_sip,                    /* SMDS */
+  snmp_ifType_frame_relay
+};
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+/** SNMP "sysuptime" Interval */
+#define SNMP_SYSUPTIME_INTERVAL 10
+
+/** fixed maximum length for object identifier type */
+#define LWIP_SNMP_OBJ_ID_LEN 32
+
+/** internal object identifier representation */
+struct snmp_obj_id
+{
+  u8_t len;
+  s32_t id[LWIP_SNMP_OBJ_ID_LEN];
+};
+
+/* system */
+void snmp_set_sysdesr(u8_t* str, u8_t* len);
+void snmp_set_sysobjid(struct snmp_obj_id *oid);
+void snmp_get_sysobjid_ptr(struct snmp_obj_id **oid);
+void snmp_inc_sysuptime(void);
+void snmp_add_sysuptime(u32_t value);
+void snmp_get_sysuptime(u32_t *value);
+void snmp_set_syscontact(u8_t *ocstr, u8_t *ocstrlen);
+void snmp_set_sysname(u8_t *ocstr, u8_t *ocstrlen);
+void snmp_set_syslocation(u8_t *ocstr, u8_t *ocstrlen);
+
+/* network interface */
+void snmp_add_ifinoctets(struct netif *ni, u32_t value); 
+void snmp_inc_ifinucastpkts(struct netif *ni);
+void snmp_inc_ifinnucastpkts(struct netif *ni);
+void snmp_inc_ifindiscards(struct netif *ni);
+void snmp_add_ifoutoctets(struct netif *ni, u32_t value);
+void snmp_inc_ifoutucastpkts(struct netif *ni);
+void snmp_inc_ifoutnucastpkts(struct netif *ni);
+void snmp_inc_ifoutdiscards(struct netif *ni);
+void snmp_inc_iflist(void);
+void snmp_dec_iflist(void);
+
+/* ARP (for atTable and ipNetToMediaTable) */
+void snmp_insert_arpidx_tree(struct netif *ni, ip_addr_t *ip);
+void snmp_delete_arpidx_tree(struct netif *ni, ip_addr_t *ip);
+
+/* IP */
+void snmp_inc_ipinreceives(void);
+void snmp_inc_ipinhdrerrors(void);
+void snmp_inc_ipinaddrerrors(void);
+void snmp_inc_ipforwdatagrams(void);
+void snmp_inc_ipinunknownprotos(void);
+void snmp_inc_ipindiscards(void);
+void snmp_inc_ipindelivers(void);
+void snmp_inc_ipoutrequests(void);
+void snmp_inc_ipoutdiscards(void);
+void snmp_inc_ipoutnoroutes(void);
+void snmp_inc_ipreasmreqds(void);
+void snmp_inc_ipreasmoks(void);
+void snmp_inc_ipreasmfails(void);
+void snmp_inc_ipfragoks(void);
+void snmp_inc_ipfragfails(void);
+void snmp_inc_ipfragcreates(void);
+void snmp_inc_iproutingdiscards(void);
+void snmp_insert_ipaddridx_tree(struct netif *ni);
+void snmp_delete_ipaddridx_tree(struct netif *ni);
+void snmp_insert_iprteidx_tree(u8_t dflt, struct netif *ni);
+void snmp_delete_iprteidx_tree(u8_t dflt, struct netif *ni);
+
+/* ICMP */
+void snmp_inc_icmpinmsgs(void);
+void snmp_inc_icmpinerrors(void);
+void snmp_inc_icmpindestunreachs(void);
+void snmp_inc_icmpintimeexcds(void);
+void snmp_inc_icmpinparmprobs(void);
+void snmp_inc_icmpinsrcquenchs(void);
+void snmp_inc_icmpinredirects(void);
+void snmp_inc_icmpinechos(void);
+void snmp_inc_icmpinechoreps(void);
+void snmp_inc_icmpintimestamps(void);
+void snmp_inc_icmpintimestampreps(void);
+void snmp_inc_icmpinaddrmasks(void);
+void snmp_inc_icmpinaddrmaskreps(void);
+void snmp_inc_icmpoutmsgs(void);
+void snmp_inc_icmpouterrors(void);
+void snmp_inc_icmpoutdestunreachs(void);
+void snmp_inc_icmpouttimeexcds(void);
+void snmp_inc_icmpoutparmprobs(void);
+void snmp_inc_icmpoutsrcquenchs(void);
+void snmp_inc_icmpoutredirects(void); 
+void snmp_inc_icmpoutechos(void);
+void snmp_inc_icmpoutechoreps(void);
+void snmp_inc_icmpouttimestamps(void);
+void snmp_inc_icmpouttimestampreps(void);
+void snmp_inc_icmpoutaddrmasks(void);
+void snmp_inc_icmpoutaddrmaskreps(void);
+
+/* TCP */
+void snmp_inc_tcpactiveopens(void);
+void snmp_inc_tcppassiveopens(void);
+void snmp_inc_tcpattemptfails(void);
+void snmp_inc_tcpestabresets(void);
+void snmp_inc_tcpinsegs(void);
+void snmp_inc_tcpoutsegs(void);
+void snmp_inc_tcpretranssegs(void);
+void snmp_inc_tcpinerrs(void);
+void snmp_inc_tcpoutrsts(void);
+
+/* UDP */
+void snmp_inc_udpindatagrams(void);
+void snmp_inc_udpnoports(void);
+void snmp_inc_udpinerrors(void);
+void snmp_inc_udpoutdatagrams(void);
+void snmp_insert_udpidx_tree(struct udp_pcb *pcb);
+void snmp_delete_udpidx_tree(struct udp_pcb *pcb);
+
+/* SNMP */
+void snmp_inc_snmpinpkts(void);
+void snmp_inc_snmpoutpkts(void);
+void snmp_inc_snmpinbadversions(void);
+void snmp_inc_snmpinbadcommunitynames(void);
+void snmp_inc_snmpinbadcommunityuses(void);
+void snmp_inc_snmpinasnparseerrs(void);
+void snmp_inc_snmpintoobigs(void);
+void snmp_inc_snmpinnosuchnames(void);
+void snmp_inc_snmpinbadvalues(void);
+void snmp_inc_snmpinreadonlys(void);
+void snmp_inc_snmpingenerrs(void);
+void snmp_add_snmpintotalreqvars(u8_t value);
+void snmp_add_snmpintotalsetvars(u8_t value);
+void snmp_inc_snmpingetrequests(void);
+void snmp_inc_snmpingetnexts(void);
+void snmp_inc_snmpinsetrequests(void);
+void snmp_inc_snmpingetresponses(void);
+void snmp_inc_snmpintraps(void);
+void snmp_inc_snmpouttoobigs(void);
+void snmp_inc_snmpoutnosuchnames(void);
+void snmp_inc_snmpoutbadvalues(void);
+void snmp_inc_snmpoutgenerrs(void);
+void snmp_inc_snmpoutgetrequests(void);
+void snmp_inc_snmpoutgetnexts(void);
+void snmp_inc_snmpoutsetrequests(void);
+void snmp_inc_snmpoutgetresponses(void);
+void snmp_inc_snmpouttraps(void);
+void snmp_get_snmpgrpid_ptr(struct snmp_obj_id **oid);
+void snmp_set_snmpenableauthentraps(u8_t *value);
+void snmp_get_snmpenableauthentraps(u8_t *value);
+
+/* LWIP_SNMP support not available */
+/* define everything to be empty */
+#else
+
+/* system */
+#define snmp_set_sysdesr(str, len)
+#define snmp_set_sysobjid(oid);
+#define snmp_get_sysobjid_ptr(oid)
+#define snmp_inc_sysuptime()
+#define snmp_add_sysuptime(value)
+#define snmp_get_sysuptime(value)
+#define snmp_set_syscontact(ocstr, ocstrlen);
+#define snmp_set_sysname(ocstr, ocstrlen);
+#define snmp_set_syslocation(ocstr, ocstrlen);
+
+/* network interface */
+#define snmp_add_ifinoctets(ni,value) 
+#define snmp_inc_ifinucastpkts(ni)
+#define snmp_inc_ifinnucastpkts(ni)
+#define snmp_inc_ifindiscards(ni)
+#define snmp_add_ifoutoctets(ni,value)
+#define snmp_inc_ifoutucastpkts(ni)
+#define snmp_inc_ifoutnucastpkts(ni)
+#define snmp_inc_ifoutdiscards(ni)
+#define snmp_inc_iflist()
+#define snmp_dec_iflist()
+
+/* ARP */
+#define snmp_insert_arpidx_tree(ni,ip)
+#define snmp_delete_arpidx_tree(ni,ip)
+
+/* IP */
+#define snmp_inc_ipinreceives()
+#define snmp_inc_ipinhdrerrors()
+#define snmp_inc_ipinaddrerrors()
+#define snmp_inc_ipforwdatagrams()
+#define snmp_inc_ipinunknownprotos()
+#define snmp_inc_ipindiscards()
+#define snmp_inc_ipindelivers()
+#define snmp_inc_ipoutrequests()
+#define snmp_inc_ipoutdiscards()
+#define snmp_inc_ipoutnoroutes()
+#define snmp_inc_ipreasmreqds()
+#define snmp_inc_ipreasmoks()
+#define snmp_inc_ipreasmfails()
+#define snmp_inc_ipfragoks()
+#define snmp_inc_ipfragfails()
+#define snmp_inc_ipfragcreates()
+#define snmp_inc_iproutingdiscards()
+#define snmp_insert_ipaddridx_tree(ni)
+#define snmp_delete_ipaddridx_tree(ni)
+#define snmp_insert_iprteidx_tree(dflt, ni)
+#define snmp_delete_iprteidx_tree(dflt, ni)
+
+/* ICMP */
+#define snmp_inc_icmpinmsgs()
+#define snmp_inc_icmpinerrors() 
+#define snmp_inc_icmpindestunreachs() 
+#define snmp_inc_icmpintimeexcds()
+#define snmp_inc_icmpinparmprobs() 
+#define snmp_inc_icmpinsrcquenchs() 
+#define snmp_inc_icmpinredirects() 
+#define snmp_inc_icmpinechos() 
+#define snmp_inc_icmpinechoreps()
+#define snmp_inc_icmpintimestamps() 
+#define snmp_inc_icmpintimestampreps()
+#define snmp_inc_icmpinaddrmasks()
+#define snmp_inc_icmpinaddrmaskreps()
+#define snmp_inc_icmpoutmsgs()
+#define snmp_inc_icmpouterrors()
+#define snmp_inc_icmpoutdestunreachs() 
+#define snmp_inc_icmpouttimeexcds() 
+#define snmp_inc_icmpoutparmprobs()
+#define snmp_inc_icmpoutsrcquenchs()
+#define snmp_inc_icmpoutredirects() 
+#define snmp_inc_icmpoutechos() 
+#define snmp_inc_icmpoutechoreps()
+#define snmp_inc_icmpouttimestamps()
+#define snmp_inc_icmpouttimestampreps()
+#define snmp_inc_icmpoutaddrmasks()
+#define snmp_inc_icmpoutaddrmaskreps()
+/* TCP */
+#define snmp_inc_tcpactiveopens()
+#define snmp_inc_tcppassiveopens()
+#define snmp_inc_tcpattemptfails()
+#define snmp_inc_tcpestabresets()
+#define snmp_inc_tcpinsegs()
+#define snmp_inc_tcpoutsegs()
+#define snmp_inc_tcpretranssegs()
+#define snmp_inc_tcpinerrs()
+#define snmp_inc_tcpoutrsts()
+
+/* UDP */
+#define snmp_inc_udpindatagrams()
+#define snmp_inc_udpnoports()
+#define snmp_inc_udpinerrors()
+#define snmp_inc_udpoutdatagrams()
+#define snmp_insert_udpidx_tree(pcb)
+#define snmp_delete_udpidx_tree(pcb)
+
+/* SNMP */
+#define snmp_inc_snmpinpkts()
+#define snmp_inc_snmpoutpkts()
+#define snmp_inc_snmpinbadversions()
+#define snmp_inc_snmpinbadcommunitynames()
+#define snmp_inc_snmpinbadcommunityuses()
+#define snmp_inc_snmpinasnparseerrs()
+#define snmp_inc_snmpintoobigs()
+#define snmp_inc_snmpinnosuchnames()
+#define snmp_inc_snmpinbadvalues()
+#define snmp_inc_snmpinreadonlys()
+#define snmp_inc_snmpingenerrs()
+#define snmp_add_snmpintotalreqvars(value)
+#define snmp_add_snmpintotalsetvars(value)
+#define snmp_inc_snmpingetrequests()
+#define snmp_inc_snmpingetnexts()
+#define snmp_inc_snmpinsetrequests()
+#define snmp_inc_snmpingetresponses()
+#define snmp_inc_snmpintraps()
+#define snmp_inc_snmpouttoobigs()
+#define snmp_inc_snmpoutnosuchnames()
+#define snmp_inc_snmpoutbadvalues()
+#define snmp_inc_snmpoutgenerrs()
+#define snmp_inc_snmpoutgetrequests()
+#define snmp_inc_snmpoutgetnexts()
+#define snmp_inc_snmpoutsetrequests()
+#define snmp_inc_snmpoutgetresponses()
+#define snmp_inc_snmpouttraps()
+#define snmp_get_snmpgrpid_ptr(oid)
+#define snmp_set_snmpenableauthentraps(value)
+#define snmp_get_snmpenableauthentraps(value)
+
+#endif /* LWIP_SNMP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_SNMP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp_asn1.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp_asn1.h
new file mode 100644
index 0000000..605fa3f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp_asn1.h
@@ -0,0 +1,101 @@
+/**
+ * @file
+ * Abstract Syntax Notation One (ISO 8824, 8825) codec.
+ */
+ 
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#ifndef __LWIP_SNMP_ASN1_H__
+#define __LWIP_SNMP_ASN1_H__
+
+#include "lwip/opt.h"
+#include "lwip/err.h"
+#include "lwip/pbuf.h"
+#include "lwip/snmp.h"
+
+#if LWIP_SNMP
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SNMP_ASN1_UNIV   (0)    /* (!0x80 | !0x40) */
+#define SNMP_ASN1_APPLIC (0x40) /* (!0x80 |  0x40) */
+#define SNMP_ASN1_CONTXT (0x80) /* ( 0x80 | !0x40) */
+
+#define SNMP_ASN1_CONSTR (0x20) /* ( 0x20) */
+#define SNMP_ASN1_PRIMIT (0)    /* (!0x20) */
+
+/* universal tags */
+#define SNMP_ASN1_INTEG  2
+#define SNMP_ASN1_OC_STR 4
+#define SNMP_ASN1_NUL    5
+#define SNMP_ASN1_OBJ_ID 6
+#define SNMP_ASN1_SEQ    16
+
+/* application specific (SNMP) tags */
+#define SNMP_ASN1_IPADDR 0    /* octet string size(4) */
+#define SNMP_ASN1_COUNTER 1   /* u32_t */
+#define SNMP_ASN1_GAUGE 2     /* u32_t */
+#define SNMP_ASN1_TIMETICKS 3 /* u32_t */
+#define SNMP_ASN1_OPAQUE 4    /* octet string */
+
+/* context specific (SNMP) tags */
+#define SNMP_ASN1_PDU_GET_REQ 0
+#define SNMP_ASN1_PDU_GET_NEXT_REQ 1
+#define SNMP_ASN1_PDU_GET_RESP 2
+#define SNMP_ASN1_PDU_SET_REQ 3
+#define SNMP_ASN1_PDU_TRAP 4
+
+err_t snmp_asn1_dec_type(struct pbuf *p, u16_t ofs, u8_t *type);
+err_t snmp_asn1_dec_length(struct pbuf *p, u16_t ofs, u8_t *octets_used, u16_t *length);
+err_t snmp_asn1_dec_u32t(struct pbuf *p, u16_t ofs, u16_t len, u32_t *value);
+err_t snmp_asn1_dec_s32t(struct pbuf *p, u16_t ofs, u16_t len, s32_t *value);
+err_t snmp_asn1_dec_oid(struct pbuf *p, u16_t ofs, u16_t len, struct snmp_obj_id *oid);
+err_t snmp_asn1_dec_raw(struct pbuf *p, u16_t ofs, u16_t len, u16_t raw_len, u8_t *raw);
+
+void snmp_asn1_enc_length_cnt(u16_t length, u8_t *octets_needed);
+void snmp_asn1_enc_u32t_cnt(u32_t value, u16_t *octets_needed);
+void snmp_asn1_enc_s32t_cnt(s32_t value, u16_t *octets_needed);
+void snmp_asn1_enc_oid_cnt(u8_t ident_len, s32_t *ident, u16_t *octets_needed);
+err_t snmp_asn1_enc_type(struct pbuf *p, u16_t ofs, u8_t type);
+err_t snmp_asn1_enc_length(struct pbuf *p, u16_t ofs, u16_t length);
+err_t snmp_asn1_enc_u32t(struct pbuf *p, u16_t ofs, u16_t octets_needed, u32_t value);
+err_t snmp_asn1_enc_s32t(struct pbuf *p, u16_t ofs, u16_t octets_needed, s32_t value);
+err_t snmp_asn1_enc_oid(struct pbuf *p, u16_t ofs, u8_t ident_len, s32_t *ident);
+err_t snmp_asn1_enc_raw(struct pbuf *p, u16_t ofs, u16_t raw_len, u8_t *raw);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_SNMP */
+
+#endif /* __LWIP_SNMP_ASN1_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp_msg.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp_msg.h
new file mode 100644
index 0000000..1183e3a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp_msg.h
@@ -0,0 +1,315 @@
+/**
+ * @file
+ * SNMP Agent message handling structures.
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#ifndef __LWIP_SNMP_MSG_H__
+#define __LWIP_SNMP_MSG_H__
+
+#include "lwip/opt.h"
+#include "lwip/snmp.h"
+#include "lwip/snmp_structs.h"
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+
+#if LWIP_SNMP
+
+#if SNMP_PRIVATE_MIB
+/* When using a private MIB, you have to create a file 'private_mib.h' that contains
+ * a 'struct mib_array_node mib_private' which contains your MIB. */
+#include "private_mib.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* The listen port of the SNMP agent. Clients have to make their requests to
+   this port. Most standard clients won't work if you change this! */
+#ifndef SNMP_IN_PORT
+#define SNMP_IN_PORT 161
+#endif
+/* The remote port the SNMP agent sends traps to. Most standard trap sinks won't
+   work if you change this! */
+#ifndef SNMP_TRAP_PORT
+#define SNMP_TRAP_PORT 162
+#endif
+
+#define SNMP_ES_NOERROR 0
+#define SNMP_ES_TOOBIG 1
+#define SNMP_ES_NOSUCHNAME 2
+#define SNMP_ES_BADVALUE 3
+#define SNMP_ES_READONLY 4
+#define SNMP_ES_GENERROR 5
+
+#define SNMP_GENTRAP_COLDSTART 0
+#define SNMP_GENTRAP_WARMSTART 1
+#define SNMP_GENTRAP_AUTHFAIL 4
+#define SNMP_GENTRAP_ENTERPRISESPC 6
+
+struct snmp_varbind
+{
+  /* next pointer, NULL for last in list */
+  struct snmp_varbind *next;
+  /* previous pointer, NULL for first in list */
+  struct snmp_varbind *prev;
+
+  /* object identifier length (in s32_t) */
+  u8_t ident_len;
+  /* object identifier array */
+  s32_t *ident;
+
+  /* object value ASN1 type */
+  u8_t value_type;
+  /* object value length (in u8_t) */
+  u8_t value_len;
+  /* object value */
+  void *value;
+
+  /* encoding varbind seq length length */
+  u8_t seqlenlen;
+  /* encoding object identifier length length */
+  u8_t olenlen;
+  /* encoding object value length length */
+  u8_t vlenlen;
+  /* encoding varbind seq length */
+  u16_t seqlen;
+  /* encoding object identifier length */
+  u16_t olen;
+  /* encoding object value length */
+  u16_t vlen;
+};
+
+struct snmp_varbind_root
+{
+  struct snmp_varbind *head;
+  struct snmp_varbind *tail;
+  /* number of variable bindings in list */
+  u8_t count;
+  /* encoding varbind-list seq length length */
+  u8_t seqlenlen;
+  /* encoding varbind-list seq length */
+  u16_t seqlen;
+};
+
+/** output response message header length fields */
+struct snmp_resp_header_lengths
+{
+  /* encoding error-index length length */
+  u8_t erridxlenlen;
+  /* encoding error-status length length */
+  u8_t errstatlenlen;
+  /* encoding request id length length */
+  u8_t ridlenlen;
+  /* encoding pdu length length */
+  u8_t pdulenlen;
+  /* encoding community length length */
+  u8_t comlenlen;
+  /* encoding version length length */
+  u8_t verlenlen;
+  /* encoding sequence length length */
+  u8_t seqlenlen;
+
+  /* encoding error-index length */
+  u16_t erridxlen;
+  /* encoding error-status length */
+  u16_t errstatlen;
+  /* encoding request id length */
+  u16_t ridlen;
+  /* encoding pdu length */
+  u16_t pdulen;
+  /* encoding community length */
+  u16_t comlen;
+  /* encoding version length */
+  u16_t verlen;
+  /* encoding sequence length */
+  u16_t seqlen;
+};
+
+/** output response message header length fields */
+struct snmp_trap_header_lengths
+{
+  /* encoding timestamp length length */
+  u8_t tslenlen;
+  /* encoding specific-trap length length */
+  u8_t strplenlen;
+  /* encoding generic-trap length length */
+  u8_t gtrplenlen;
+  /* encoding agent-addr length length */
+  u8_t aaddrlenlen;
+  /* encoding enterprise-id length length */
+  u8_t eidlenlen;
+  /* encoding pdu length length */
+  u8_t pdulenlen;
+  /* encoding community length length */
+  u8_t comlenlen;
+  /* encoding version length length */
+  u8_t verlenlen;
+  /* encoding sequence length length */
+  u8_t seqlenlen;
+
+  /* encoding timestamp length */
+  u16_t tslen;
+  /* encoding specific-trap length */
+  u16_t strplen;
+  /* encoding generic-trap length */
+  u16_t gtrplen;
+  /* encoding agent-addr length */
+  u16_t aaddrlen;
+  /* encoding enterprise-id length */
+  u16_t eidlen;
+  /* encoding pdu length */
+  u16_t pdulen;
+  /* encoding community length */
+  u16_t comlen;
+  /* encoding version length */
+  u16_t verlen;
+  /* encoding sequence length */
+  u16_t seqlen;
+};
+
+/* Accepting new SNMP messages. */
+#define SNMP_MSG_EMPTY                 0
+/* Search for matching object for variable binding. */
+#define SNMP_MSG_SEARCH_OBJ            1
+/* Perform SNMP operation on in-memory object.
+   Pass-through states, for symmetry only. */
+#define SNMP_MSG_INTERNAL_GET_OBJDEF   2
+#define SNMP_MSG_INTERNAL_GET_VALUE    3
+#define SNMP_MSG_INTERNAL_SET_TEST     4
+#define SNMP_MSG_INTERNAL_GET_OBJDEF_S 5
+#define SNMP_MSG_INTERNAL_SET_VALUE    6
+/* Perform SNMP operation on object located externally.
+   In theory this could be used for building a proxy agent.
+   Practical use is for an enterprise spc. app. gateway. */
+#define SNMP_MSG_EXTERNAL_GET_OBJDEF   7
+#define SNMP_MSG_EXTERNAL_GET_VALUE    8
+#define SNMP_MSG_EXTERNAL_SET_TEST     9
+#define SNMP_MSG_EXTERNAL_GET_OBJDEF_S 10
+#define SNMP_MSG_EXTERNAL_SET_VALUE    11
+
+#define SNMP_COMMUNITY_STR_LEN 64
+struct snmp_msg_pstat
+{
+  /* lwIP local port (161) binding */
+  struct udp_pcb *pcb;
+  /* source IP address */
+  ip_addr_t sip;
+  /* source UDP port */
+  u16_t sp;
+  /* request type */
+  u8_t rt;
+  /* request ID */
+  s32_t rid;
+  /* error status */
+  s32_t error_status;
+  /* error index */
+  s32_t error_index;
+  /* community name (zero terminated) */
+  u8_t community[SNMP_COMMUNITY_STR_LEN + 1];
+  /* community string length (exclusive zero term) */
+  u8_t com_strlen;
+  /* one out of MSG_EMPTY, MSG_DEMUX, MSG_INTERNAL, MSG_EXTERNAL_x */
+  u8_t state;
+  /* saved arguments for MSG_EXTERNAL_x */
+  struct mib_external_node *ext_mib_node;
+  struct snmp_name_ptr ext_name_ptr;
+  struct obj_def ext_object_def;
+  struct snmp_obj_id ext_oid;
+  /* index into input variable binding list */
+  u8_t vb_idx;
+  /* ptr into input variable binding list */
+  struct snmp_varbind *vb_ptr;
+  /* list of variable bindings from input */
+  struct snmp_varbind_root invb;
+  /* list of variable bindings to output */
+  struct snmp_varbind_root outvb;
+  /* output response lengths used in ASN encoding */
+  struct snmp_resp_header_lengths rhl;
+};
+
+struct snmp_msg_trap
+{
+  /* lwIP local port (161) binding */
+  struct udp_pcb *pcb;
+  /* destination IP address in network order */
+  ip_addr_t dip;
+
+  /* source enterprise ID (sysObjectID) */
+  struct snmp_obj_id *enterprise;
+  /* source IP address, raw network order format */
+  u8_t sip_raw[4];
+  /* generic trap code */
+  u32_t gen_trap;
+  /* specific trap code */
+  u32_t spc_trap;
+  /* timestamp */
+  u32_t ts;
+  /* list of variable bindings to output */
+  struct snmp_varbind_root outvb;
+  /* output trap lengths used in ASN encoding */
+  struct snmp_trap_header_lengths thl;
+};
+
+/** Agent Version constant, 0 = v1 oddity */
+extern const s32_t snmp_version;
+/** Agent default "public" community string */
+extern const char snmp_publiccommunity[7];
+
+extern struct snmp_msg_trap trap_msg;
+
+/** Agent setup, start listening to port 161. */
+void snmp_init(void);
+void snmp_trap_dst_enable(u8_t dst_idx, u8_t enable);
+void snmp_trap_dst_ip_set(u8_t dst_idx, ip_addr_t *dst);
+
+/** Varbind-list functions. */
+struct snmp_varbind* snmp_varbind_alloc(struct snmp_obj_id *oid, u8_t type, u8_t len);
+void snmp_varbind_free(struct snmp_varbind *vb);
+void snmp_varbind_list_free(struct snmp_varbind_root *root);
+void snmp_varbind_tail_add(struct snmp_varbind_root *root, struct snmp_varbind *vb);
+struct snmp_varbind* snmp_varbind_tail_remove(struct snmp_varbind_root *root);
+
+/** Handle an internal (recv) or external (private response) event. */
+void snmp_msg_event(u8_t request_id);
+err_t snmp_send_response(struct snmp_msg_pstat *m_stat);
+err_t snmp_send_trap(s8_t generic_trap, struct snmp_obj_id *eoid, s32_t specific_trap);
+void snmp_coldstart_trap(void);
+void snmp_authfail_trap(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_SNMP */
+
+#endif /* __LWIP_SNMP_MSG_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp_structs.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp_structs.h
new file mode 100644
index 0000000..0d3b46a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/snmp_structs.h
@@ -0,0 +1,268 @@
+/**
+ * @file
+ * Generic MIB tree structures.
+ *
+ * @todo namespace prefixes
+ */
+
+/*
+ * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christiaan Simons 
+ */
+
+#ifndef __LWIP_SNMP_STRUCTS_H__
+#define __LWIP_SNMP_STRUCTS_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/snmp.h"
+
+#if SNMP_PRIVATE_MIB
+/* When using a private MIB, you have to create a file 'private_mib.h' that contains
+ * a 'struct mib_array_node mib_private' which contains your MIB. */
+#include "private_mib.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* MIB object instance */
+#define MIB_OBJECT_NONE 0 
+#define MIB_OBJECT_SCALAR 1
+#define MIB_OBJECT_TAB 2
+
+/* MIB access types */
+#define MIB_ACCESS_READ   1
+#define MIB_ACCESS_WRITE  2
+
+/* MIB object access */
+#define MIB_OBJECT_READ_ONLY      MIB_ACCESS_READ
+#define MIB_OBJECT_READ_WRITE     (MIB_ACCESS_READ | MIB_ACCESS_WRITE)
+#define MIB_OBJECT_WRITE_ONLY     MIB_ACCESS_WRITE
+#define MIB_OBJECT_NOT_ACCESSIBLE 0
+
+/** object definition returned by (get_object_def)() */
+struct obj_def
+{
+  /* MIB_OBJECT_NONE (0), MIB_OBJECT_SCALAR (1), MIB_OBJECT_TAB (2) */
+  u8_t instance;
+  /* 0 read-only, 1 read-write, 2 write-only, 3 not-accessible */
+  u8_t access;
+  /* ASN type for this object */
+  u8_t asn_type;
+  /* value length (host length) */
+  u16_t v_len;
+  /* length of instance part of supplied object identifier */
+  u8_t  id_inst_len;
+  /* instance part of supplied object identifier */
+  s32_t *id_inst_ptr;
+};
+
+struct snmp_name_ptr
+{
+  u8_t ident_len;
+  s32_t *ident;
+};
+
+/** MIB const scalar (.0) node */
+#define MIB_NODE_SC 0x01
+/** MIB const array node */
+#define MIB_NODE_AR 0x02
+/** MIB array node (mem_malloced from RAM) */
+#define MIB_NODE_RA 0x03
+/** MIB list root node (mem_malloced from RAM) */
+#define MIB_NODE_LR 0x04
+/** MIB node for external objects */
+#define MIB_NODE_EX 0x05
+
+/** node "base class" layout, the mandatory fields for a node  */
+struct mib_node
+{
+  /** returns struct obj_def for the given object identifier */
+  void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od);
+  /** returns object value for the given object identifier,
+     @note the caller must allocate at least len bytes for the value */
+  void (*get_value)(struct obj_def *od, u16_t len, void *value);
+  /** tests length and/or range BEFORE setting */
+  u8_t (*set_test)(struct obj_def *od, u16_t len, void *value);
+  /** sets object value, only to be called when set_test()  */
+  void (*set_value)(struct obj_def *od, u16_t len, void *value);  
+  /** One out of MIB_NODE_AR, MIB_NODE_LR or MIB_NODE_EX */
+  u8_t node_type;
+  /* array or max list length */
+  u16_t maxlength;
+};
+
+/** derived node for scalars .0 index */
+typedef struct mib_node mib_scalar_node;
+
+/** derived node, points to a fixed size const array
+    of sub-identifiers plus a 'child' pointer */
+struct mib_array_node
+{
+  /* inherited "base class" members */
+  void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od);
+  void (*get_value)(struct obj_def *od, u16_t len, void *value);
+  u8_t (*set_test)(struct obj_def *od, u16_t len, void *value);
+  void (*set_value)(struct obj_def *od, u16_t len, void *value);
+
+  u8_t node_type;
+  u16_t maxlength;
+
+  /* additional struct members */
+  const s32_t *objid;
+  struct mib_node* const *nptr;
+};
+
+/** derived node, points to a fixed size mem_malloced array
+    of sub-identifiers plus a 'child' pointer */
+struct mib_ram_array_node
+{
+  /* inherited "base class" members */
+  void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od);
+  void (*get_value)(struct obj_def *od, u16_t len, void *value);
+  u8_t (*set_test)(struct obj_def *od, u16_t len, void *value);
+  void (*set_value)(struct obj_def *od, u16_t len, void *value);
+
+  u8_t node_type;
+  u16_t maxlength;
+
+  /* aditional struct members */
+  s32_t *objid;
+  struct mib_node **nptr;
+};
+
+struct mib_list_node
+{
+  struct mib_list_node *prev;  
+  struct mib_list_node *next;
+  s32_t objid;
+  struct mib_node *nptr;
+};
+
+/** derived node, points to a doubly linked list
+    of sub-identifiers plus a 'child' pointer */
+struct mib_list_rootnode
+{
+  /* inherited "base class" members */
+  void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od);
+  void (*get_value)(struct obj_def *od, u16_t len, void *value);
+  u8_t (*set_test)(struct obj_def *od, u16_t len, void *value);
+  void (*set_value)(struct obj_def *od, u16_t len, void *value);
+
+  u8_t node_type;
+  u16_t maxlength;
+
+  /* additional struct members */
+  struct mib_list_node *head;
+  struct mib_list_node *tail;
+  /* counts list nodes in list  */
+  u16_t count;
+};
+
+/** derived node, has access functions for mib object in external memory or device
+    using 'tree_level' and 'idx', with a range 0 .. (level_length() - 1) */
+struct mib_external_node
+{
+  /* inherited "base class" members */
+  void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od);
+  void (*get_value)(struct obj_def *od, u16_t len, void *value);
+  u8_t (*set_test)(struct obj_def *od, u16_t len, void *value);
+  void (*set_value)(struct obj_def *od, u16_t len, void *value);
+
+  u8_t node_type;
+  u16_t maxlength;
+
+  /* additional struct members */
+  /** points to an external (in memory) record of some sort of addressing
+      information, passed to and interpreted by the funtions below */
+  void* addr_inf;
+  /** tree levels under this node */
+  u8_t tree_levels;
+  /** number of objects at this level */
+  u16_t (*level_length)(void* addr_inf, u8_t level);
+  /** compares object sub identifier with external id
+      return zero when equal, nonzero when unequal */
+  s32_t (*ident_cmp)(void* addr_inf, u8_t level, u16_t idx, s32_t sub_id);
+  void (*get_objid)(void* addr_inf, u8_t level, u16_t idx, s32_t *sub_id);
+
+  /** async Questions */
+  void (*get_object_def_q)(void* addr_inf, u8_t rid, u8_t ident_len, s32_t *ident);
+  void (*get_value_q)(u8_t rid, struct obj_def *od);
+  void (*set_test_q)(u8_t rid, struct obj_def *od);
+  void (*set_value_q)(u8_t rid, struct obj_def *od, u16_t len, void *value);
+  /** async Answers */
+  void (*get_object_def_a)(u8_t rid, u8_t ident_len, s32_t *ident, struct obj_def *od);
+  void (*get_value_a)(u8_t rid, struct obj_def *od, u16_t len, void *value);
+  u8_t (*set_test_a)(u8_t rid, struct obj_def *od, u16_t len, void *value);
+  void (*set_value_a)(u8_t rid, struct obj_def *od, u16_t len, void *value);
+  /** async Panic Close (agent returns error reply, 
+      e.g. used for external transaction cleanup) */
+  void (*get_object_def_pc)(u8_t rid, u8_t ident_len, s32_t *ident);
+  void (*get_value_pc)(u8_t rid, struct obj_def *od);
+  void (*set_test_pc)(u8_t rid, struct obj_def *od);
+  void (*set_value_pc)(u8_t rid, struct obj_def *od);
+};
+
+/** export MIB tree from mib2.c */
+extern const struct mib_array_node internet;
+
+/** dummy function pointers for non-leaf MIB nodes from mib2.c */
+void noleafs_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od);
+void noleafs_get_value(struct obj_def *od, u16_t len, void *value);
+u8_t noleafs_set_test(struct obj_def *od, u16_t len, void *value);
+void noleafs_set_value(struct obj_def *od, u16_t len, void *value);
+
+void snmp_oidtoip(s32_t *ident, ip_addr_t *ip);
+void snmp_iptooid(ip_addr_t *ip, s32_t *ident);
+void snmp_ifindextonetif(s32_t ifindex, struct netif **netif);
+void snmp_netiftoifindex(struct netif *netif, s32_t *ifidx);
+
+struct mib_list_node* snmp_mib_ln_alloc(s32_t id);
+void snmp_mib_ln_free(struct mib_list_node *ln);
+struct mib_list_rootnode* snmp_mib_lrn_alloc(void);
+void snmp_mib_lrn_free(struct mib_list_rootnode *lrn);
+
+s8_t snmp_mib_node_insert(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **insn);
+s8_t snmp_mib_node_find(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **fn);
+struct mib_list_rootnode *snmp_mib_node_delete(struct mib_list_rootnode *rn, struct mib_list_node *n);
+
+struct mib_node* snmp_search_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_name_ptr *np);
+struct mib_node* snmp_expand_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret);
+u8_t snmp_iso_prefix_tst(u8_t ident_len, s32_t *ident);
+u8_t snmp_iso_prefix_expand(u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_SNMP */
+
+#endif /* __LWIP_SNMP_STRUCTS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/sockets.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/sockets.h
new file mode 100644
index 0000000..3c8fed2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/sockets.h
@@ -0,0 +1,376 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+#ifndef __LWIP_SOCKETS_H__
+#define __LWIP_SOCKETS_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+
+#include  /* for size_t */
+
+#include "lwip/ip_addr.h"
+#include "lwip/inet.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* members are in network byte order */
+struct sockaddr_in {
+  u8_t sin_len;
+  u8_t sin_family;
+  u16_t sin_port;
+  struct in_addr sin_addr;
+  char sin_zero[8];
+};
+
+struct sockaddr {
+  u8_t sa_len;
+  u8_t sa_family;
+  char sa_data[14];
+};
+
+#ifndef socklen_t
+#  define socklen_t u32_t
+#endif
+
+/* Socket protocol types (TCP/UDP/RAW) */
+#define SOCK_STREAM     1
+#define SOCK_DGRAM      2
+#define SOCK_RAW        3
+
+/*
+ * Option flags per-socket. These must match the SOF_ flags in ip.h (checked in init.c)
+ */
+#define  SO_DEBUG       0x0001 /* Unimplemented: turn on debugging info recording */
+#define  SO_ACCEPTCONN  0x0002 /* socket has had listen() */
+#define  SO_REUSEADDR   0x0004 /* Allow local address reuse */
+#define  SO_KEEPALIVE   0x0008 /* keep connections alive */
+#define  SO_DONTROUTE   0x0010 /* Unimplemented: just use interface addresses */
+#define  SO_BROADCAST   0x0020 /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */
+#define  SO_USELOOPBACK 0x0040 /* Unimplemented: bypass hardware when possible */
+#define  SO_LINGER      0x0080 /* linger on close if data present */
+#define  SO_OOBINLINE   0x0100 /* Unimplemented: leave received OOB data in line */
+#define  SO_REUSEPORT   0x0200 /* Unimplemented: allow local address & port reuse */
+
+#define SO_DONTLINGER   ((int)(~SO_LINGER))
+
+/*
+ * Additional options, not kept in so_options.
+ */
+#define SO_SNDBUF    0x1001    /* Unimplemented: send buffer size */
+#define SO_RCVBUF    0x1002    /* receive buffer size */
+#define SO_SNDLOWAT  0x1003    /* Unimplemented: send low-water mark */
+#define SO_RCVLOWAT  0x1004    /* Unimplemented: receive low-water mark */
+#define SO_SNDTIMEO  0x1005    /* Unimplemented: send timeout */
+#define SO_RCVTIMEO  0x1006    /* receive timeout */
+#define SO_ERROR     0x1007    /* get error status and clear */
+#define SO_TYPE      0x1008    /* get socket type */
+#define SO_CONTIMEO  0x1009    /* Unimplemented: connect timeout */
+#define SO_NO_CHECK  0x100a    /* don't create UDP checksum */
+
+
+/*
+ * Structure used for manipulating linger option.
+ */
+struct linger {
+       int l_onoff;                /* option on/off */
+       int l_linger;               /* linger time */
+};
+
+/*
+ * Level number for (get/set)sockopt() to apply to socket itself.
+ */
+#define  SOL_SOCKET  0xfff    /* options for socket level */
+
+
+#define AF_UNSPEC       0
+#define AF_INET         2
+#define PF_INET         AF_INET
+#define PF_UNSPEC       AF_UNSPEC
+
+#define IPPROTO_IP      0
+#define IPPROTO_TCP     6
+#define IPPROTO_UDP     17
+#define IPPROTO_UDPLITE 136
+
+/* Flags we can use with send and recv. */
+#define MSG_PEEK       0x01    /* Peeks at an incoming message */
+#define MSG_WAITALL    0x02    /* Unimplemented: Requests that the function block until the full amount of data requested can be returned */
+#define MSG_OOB        0x04    /* Unimplemented: Requests out-of-band data. The significance and semantics of out-of-band data are protocol-specific */
+#define MSG_DONTWAIT   0x08    /* Nonblocking i/o for this operation only */
+#define MSG_MORE       0x10    /* Sender will send more */
+
+
+/*
+ * Options for level IPPROTO_IP
+ */
+#define IP_TOS             1
+#define IP_TTL             2
+
+#if LWIP_TCP
+/*
+ * Options for level IPPROTO_TCP
+ */
+#define TCP_NODELAY    0x01    /* don't delay send to coalesce packets */
+#define TCP_KEEPALIVE  0x02    /* send KEEPALIVE probes when idle for pcb->keep_idle milliseconds */
+#define TCP_KEEPIDLE   0x03    /* set pcb->keep_idle  - Same as TCP_KEEPALIVE, but use seconds for get/setsockopt */
+#define TCP_KEEPINTVL  0x04    /* set pcb->keep_intvl - Use seconds for get/setsockopt */
+#define TCP_KEEPCNT    0x05    /* set pcb->keep_cnt   - Use number of probes sent for get/setsockopt */
+#endif /* LWIP_TCP */
+
+#if LWIP_UDP && LWIP_UDPLITE
+/*
+ * Options for level IPPROTO_UDPLITE
+ */
+#define UDPLITE_SEND_CSCOV 0x01 /* sender checksum coverage */
+#define UDPLITE_RECV_CSCOV 0x02 /* minimal receiver checksum coverage */
+#endif /* LWIP_UDP && LWIP_UDPLITE*/
+
+
+#if LWIP_IGMP
+/*
+ * Options and types for UDP multicast traffic handling
+ */
+#define IP_ADD_MEMBERSHIP  3
+#define IP_DROP_MEMBERSHIP 4
+#define IP_MULTICAST_TTL   5
+#define IP_MULTICAST_IF    6
+#define IP_MULTICAST_LOOP  7
+
+typedef struct ip_mreq {
+    struct in_addr imr_multiaddr; /* IP multicast address of group */
+    struct in_addr imr_interface; /* local IP address of interface */
+} ip_mreq;
+#endif /* LWIP_IGMP */
+
+/*
+ * The Type of Service provides an indication of the abstract
+ * parameters of the quality of service desired.  These parameters are
+ * to be used to guide the selection of the actual service parameters
+ * when transmitting a datagram through a particular network.  Several
+ * networks offer service precedence, which somehow treats high
+ * precedence traffic as more important than other traffic (generally
+ * by accepting only traffic above a certain precedence at time of high
+ * load).  The major choice is a three way tradeoff between low-delay,
+ * high-reliability, and high-throughput.
+ * The use of the Delay, Throughput, and Reliability indications may
+ * increase the cost (in some sense) of the service.  In many networks
+ * better performance for one of these parameters is coupled with worse
+ * performance on another.  Except for very unusual cases at most two
+ * of these three indications should be set.
+ */
+#define IPTOS_TOS_MASK          0x1E
+#define IPTOS_TOS(tos)          ((tos) & IPTOS_TOS_MASK)
+#define IPTOS_LOWDELAY          0x10
+#define IPTOS_THROUGHPUT        0x08
+#define IPTOS_RELIABILITY       0x04
+#define IPTOS_LOWCOST           0x02
+#define IPTOS_MINCOST           IPTOS_LOWCOST
+
+/*
+ * The Network Control precedence designation is intended to be used
+ * within a network only.  The actual use and control of that
+ * designation is up to each network. The Internetwork Control
+ * designation is intended for use by gateway control originators only.
+ * If the actual use of these precedence designations is of concern to
+ * a particular network, it is the responsibility of that network to
+ * control the access to, and use of, those precedence designations.
+ */
+#define IPTOS_PREC_MASK                 0xe0
+#define IPTOS_PREC(tos)                ((tos) & IPTOS_PREC_MASK)
+#define IPTOS_PREC_NETCONTROL           0xe0
+#define IPTOS_PREC_INTERNETCONTROL      0xc0
+#define IPTOS_PREC_CRITIC_ECP           0xa0
+#define IPTOS_PREC_FLASHOVERRIDE        0x80
+#define IPTOS_PREC_FLASH                0x60
+#define IPTOS_PREC_IMMEDIATE            0x40
+#define IPTOS_PREC_PRIORITY             0x20
+#define IPTOS_PREC_ROUTINE              0x00
+
+
+/*
+ * Commands for ioctlsocket(),  taken from the BSD file fcntl.h.
+ * lwip_ioctl only supports FIONREAD and FIONBIO, for now
+ *
+ * Ioctl's have the command encoded in the lower word,
+ * and the size of any in or out parameters in the upper
+ * word.  The high 2 bits of the upper word are used
+ * to encode the in/out status of the parameter; for now
+ * we restrict parameters to at most 128 bytes.
+ */
+#if !defined(FIONREAD) || !defined(FIONBIO)
+#define IOCPARM_MASK    0x7fU           /* parameters must be < 128 bytes */
+#define IOC_VOID        0x20000000UL    /* no parameters */
+#define IOC_OUT         0x40000000UL    /* copy out parameters */
+#define IOC_IN          0x80000000UL    /* copy in parameters */
+#define IOC_INOUT       (IOC_IN|IOC_OUT)
+                                        /* 0x20000000 distinguishes new &
+                                           old ioctl's */
+#define _IO(x,y)        (IOC_VOID|((x)<<8)|(y))
+
+#define _IOR(x,y,t)     (IOC_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
+
+#define _IOW(x,y,t)     (IOC_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
+#endif /* !defined(FIONREAD) || !defined(FIONBIO) */
+
+#ifndef FIONREAD
+#define FIONREAD    _IOR('f', 127, unsigned long) /* get # bytes to read */
+#endif
+#ifndef FIONBIO
+#define FIONBIO     _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */
+#endif
+
+/* Socket I/O Controls: unimplemented */
+#ifndef SIOCSHIWAT
+#define SIOCSHIWAT  _IOW('s',  0, unsigned long)  /* set high watermark */
+#define SIOCGHIWAT  _IOR('s',  1, unsigned long)  /* get high watermark */
+#define SIOCSLOWAT  _IOW('s',  2, unsigned long)  /* set low watermark */
+#define SIOCGLOWAT  _IOR('s',  3, unsigned long)  /* get low watermark */
+#define SIOCATMARK  _IOR('s',  7, unsigned long)  /* at oob mark? */
+#endif
+
+/* commands for fnctl */
+#ifndef F_GETFL
+#define F_GETFL 3
+#endif
+#ifndef F_SETFL
+#define F_SETFL 4
+#endif
+
+/* File status flags and file access modes for fnctl,
+   these are bits in an int. */
+#ifndef O_NONBLOCK
+#define O_NONBLOCK  1 /* nonblocking I/O */
+#endif
+#ifndef O_NDELAY
+#define O_NDELAY    1 /* same as O_NONBLOCK, for compatibility */
+#endif
+
+#ifndef SHUT_RD
+  #define SHUT_RD   0
+  #define SHUT_WR   1
+  #define SHUT_RDWR 2
+#endif
+
+/* FD_SET used for lwip_select */
+#ifndef FD_SET
+  #undef  FD_SETSIZE
+  /* Make FD_SETSIZE match NUM_SOCKETS in socket.c */
+  #define FD_SETSIZE    MEMP_NUM_NETCONN
+  #define FD_SET(n, p)  ((p)->fd_bits[(n)/8] |=  (1 << ((n) & 7)))
+  #define FD_CLR(n, p)  ((p)->fd_bits[(n)/8] &= ~(1 << ((n) & 7)))
+  #define FD_ISSET(n,p) ((p)->fd_bits[(n)/8] &   (1 << ((n) & 7)))
+  #define FD_ZERO(p)    memset((void*)(p),0,sizeof(*(p)))
+
+  typedef struct fd_set {
+          unsigned char fd_bits [(FD_SETSIZE+7)/8];
+        } fd_set;
+
+#endif /* FD_SET */
+
+/** LWIP_TIMEVAL_PRIVATE: if you want to use the struct timeval provided
+ * by your system, set this to 0 and include  in cc.h */ 
+#ifndef LWIP_TIMEVAL_PRIVATE
+#define LWIP_TIMEVAL_PRIVATE 1
+#endif
+
+#if LWIP_TIMEVAL_PRIVATE
+struct timeval {
+  long    tv_sec;         /* seconds */
+  long    tv_usec;        /* and microseconds */
+};
+#endif /* LWIP_TIMEVAL_PRIVATE */
+
+void lwip_socket_init(void);
+
+int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen);
+int lwip_bind(int s, const struct sockaddr *name, socklen_t namelen);
+int lwip_shutdown(int s, int how);
+int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen);
+int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen);
+int lwip_close(int s);
+int lwip_connect(int s, const struct sockaddr *name, socklen_t namelen);
+int lwip_listen(int s, int backlog);
+int lwip_recv(int s, void *mem, size_t len, int flags);
+int lwip_read(int s, void *mem, size_t len);
+int lwip_recvfrom(int s, void *mem, size_t len, int flags,
+      struct sockaddr *from, socklen_t *fromlen);
+int lwip_send(int s, const void *dataptr, size_t size, int flags);
+int lwip_sendto(int s, const void *dataptr, size_t size, int flags,
+    const struct sockaddr *to, socklen_t tolen);
+int lwip_socket(int domain, int type, int protocol);
+int lwip_write(int s, const void *dataptr, size_t size);
+int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
+                struct timeval *timeout);
+int lwip_ioctl(int s, long cmd, void *argp);
+int lwip_fcntl(int s, int cmd, int val);
+
+#if LWIP_COMPAT_SOCKETS
+#define accept(a,b,c)         lwip_accept(a,b,c)
+#define bind(a,b,c)           lwip_bind(a,b,c)
+#define shutdown(a,b)         lwip_shutdown(a,b)
+#define closesocket(s)        lwip_close(s)
+#define connect(a,b,c)        lwip_connect(a,b,c)
+#define getsockname(a,b,c)    lwip_getsockname(a,b,c)
+#define getpeername(a,b,c)    lwip_getpeername(a,b,c)
+#define setsockopt(a,b,c,d,e) lwip_setsockopt(a,b,c,d,e)
+#define getsockopt(a,b,c,d,e) lwip_getsockopt(a,b,c,d,e)
+#define listen(a,b)           lwip_listen(a,b)
+#define recv(a,b,c,d)         lwip_recv(a,b,c,d)
+#define recvfrom(a,b,c,d,e,f) lwip_recvfrom(a,b,c,d,e,f)
+#define send(a,b,c,d)         lwip_send(a,b,c,d)
+#define sendto(a,b,c,d,e,f)   lwip_sendto(a,b,c,d,e,f)
+#define socket(a,b,c)         lwip_socket(a,b,c)
+#define select(a,b,c,d,e)     lwip_select(a,b,c,d,e)
+#define ioctlsocket(a,b,c)    lwip_ioctl(a,b,c)
+
+#if LWIP_POSIX_SOCKETS_IO_NAMES
+#define read(a,b,c)           lwip_read(a,b,c)
+#define write(a,b,c)          lwip_write(a,b,c)
+#define close(s)              lwip_close(s)
+#endif /* LWIP_POSIX_SOCKETS_IO_NAMES */
+
+#endif /* LWIP_COMPAT_SOCKETS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_SOCKET */
+
+#endif /* __LWIP_SOCKETS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/stats.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/stats.h
new file mode 100644
index 0000000..015b7ce
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/stats.h
@@ -0,0 +1,292 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_STATS_H__
+#define __LWIP_STATS_H__
+
+#include "lwip/opt.h"
+
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_STATS
+
+#ifndef LWIP_STATS_LARGE
+#define LWIP_STATS_LARGE 0
+#endif
+
+#if LWIP_STATS_LARGE
+#define STAT_COUNTER     u32_t
+#define STAT_COUNTER_F   U32_F
+#else
+#define STAT_COUNTER     u16_t
+#define STAT_COUNTER_F   U16_F
+#endif 
+
+struct stats_proto {
+  STAT_COUNTER xmit;             /* Transmitted packets. */
+  STAT_COUNTER recv;             /* Received packets. */
+  STAT_COUNTER fw;               /* Forwarded packets. */
+  STAT_COUNTER drop;             /* Dropped packets. */
+  STAT_COUNTER chkerr;           /* Checksum error. */
+  STAT_COUNTER lenerr;           /* Invalid length error. */
+  STAT_COUNTER memerr;           /* Out of memory error. */
+  STAT_COUNTER rterr;            /* Routing error. */
+  STAT_COUNTER proterr;          /* Protocol error. */
+  STAT_COUNTER opterr;           /* Error in options. */
+  STAT_COUNTER err;              /* Misc error. */
+  STAT_COUNTER cachehit;
+};
+
+struct stats_igmp {
+  STAT_COUNTER xmit;             /* Transmitted packets. */
+  STAT_COUNTER recv;             /* Received packets. */
+  STAT_COUNTER drop;             /* Dropped packets. */
+  STAT_COUNTER chkerr;           /* Checksum error. */
+  STAT_COUNTER lenerr;           /* Invalid length error. */
+  STAT_COUNTER memerr;           /* Out of memory error. */
+  STAT_COUNTER proterr;          /* Protocol error. */
+  STAT_COUNTER rx_v1;            /* Received v1 frames. */
+  STAT_COUNTER rx_group;         /* Received group-specific queries. */
+  STAT_COUNTER rx_general;       /* Received general queries. */
+  STAT_COUNTER rx_report;        /* Received reports. */
+  STAT_COUNTER tx_join;          /* Sent joins. */
+  STAT_COUNTER tx_leave;         /* Sent leaves. */
+  STAT_COUNTER tx_report;        /* Sent reports. */
+};
+
+struct stats_mem {
+#ifdef LWIP_DEBUG
+  const char *name;
+#endif /* LWIP_DEBUG */
+  mem_size_t avail;
+  mem_size_t used;
+  mem_size_t max;
+  STAT_COUNTER err;
+  STAT_COUNTER illegal;
+};
+
+struct stats_syselem {
+  STAT_COUNTER used;
+  STAT_COUNTER max;
+  STAT_COUNTER err;
+};
+
+struct stats_sys {
+  struct stats_syselem sem;
+  struct stats_syselem mutex;
+  struct stats_syselem mbox;
+};
+
+struct stats_ {
+#if LINK_STATS
+  struct stats_proto link;
+#endif
+#if ETHARP_STATS
+  struct stats_proto etharp;
+#endif
+#if IPFRAG_STATS
+  struct stats_proto ip_frag;
+#endif
+#if IP_STATS
+  struct stats_proto ip;
+#endif
+#if ICMP_STATS
+  struct stats_proto icmp;
+#endif
+#if IGMP_STATS
+  struct stats_igmp igmp;
+#endif
+#if UDP_STATS
+  struct stats_proto udp;
+#endif
+#if TCP_STATS
+  struct stats_proto tcp;
+#endif
+#if MEM_STATS
+  struct stats_mem mem;
+#endif
+#if MEMP_STATS
+  struct stats_mem memp[MEMP_MAX];
+#endif
+#if SYS_STATS
+  struct stats_sys sys;
+#endif
+};
+
+extern struct stats_ lwip_stats;
+
+void stats_init(void);
+
+#define STATS_INC(x) ++lwip_stats.x
+#define STATS_DEC(x) --lwip_stats.x
+#define STATS_INC_USED(x, y) do { lwip_stats.x.used += y; \
+                                if (lwip_stats.x.max < lwip_stats.x.used) { \
+                                    lwip_stats.x.max = lwip_stats.x.used; \
+                                } \
+                             } while(0)
+#else /* LWIP_STATS */
+#define stats_init()
+#define STATS_INC(x)
+#define STATS_DEC(x)
+#define STATS_INC_USED(x)
+#endif /* LWIP_STATS */
+
+#if TCP_STATS
+#define TCP_STATS_INC(x) STATS_INC(x)
+#define TCP_STATS_DISPLAY() stats_display_proto(&lwip_stats.tcp, "TCP")
+#else
+#define TCP_STATS_INC(x)
+#define TCP_STATS_DISPLAY()
+#endif
+
+#if UDP_STATS
+#define UDP_STATS_INC(x) STATS_INC(x)
+#define UDP_STATS_DISPLAY() stats_display_proto(&lwip_stats.udp, "UDP")
+#else
+#define UDP_STATS_INC(x)
+#define UDP_STATS_DISPLAY()
+#endif
+
+#if ICMP_STATS
+#define ICMP_STATS_INC(x) STATS_INC(x)
+#define ICMP_STATS_DISPLAY() stats_display_proto(&lwip_stats.icmp, "ICMP")
+#else
+#define ICMP_STATS_INC(x)
+#define ICMP_STATS_DISPLAY()
+#endif
+
+#if IGMP_STATS
+#define IGMP_STATS_INC(x) STATS_INC(x)
+#define IGMP_STATS_DISPLAY() stats_display_igmp(&lwip_stats.igmp)
+#else
+#define IGMP_STATS_INC(x)
+#define IGMP_STATS_DISPLAY()
+#endif
+
+#if IP_STATS
+#define IP_STATS_INC(x) STATS_INC(x)
+#define IP_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip, "IP")
+#else
+#define IP_STATS_INC(x)
+#define IP_STATS_DISPLAY()
+#endif
+
+#if IPFRAG_STATS
+#define IPFRAG_STATS_INC(x) STATS_INC(x)
+#define IPFRAG_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG")
+#else
+#define IPFRAG_STATS_INC(x)
+#define IPFRAG_STATS_DISPLAY()
+#endif
+
+#if ETHARP_STATS
+#define ETHARP_STATS_INC(x) STATS_INC(x)
+#define ETHARP_STATS_DISPLAY() stats_display_proto(&lwip_stats.etharp, "ETHARP")
+#else
+#define ETHARP_STATS_INC(x)
+#define ETHARP_STATS_DISPLAY()
+#endif
+
+#if LINK_STATS
+#define LINK_STATS_INC(x) STATS_INC(x)
+#define LINK_STATS_DISPLAY() stats_display_proto(&lwip_stats.link, "LINK")
+#else
+#define LINK_STATS_INC(x)
+#define LINK_STATS_DISPLAY()
+#endif
+
+#if MEM_STATS
+#define MEM_STATS_AVAIL(x, y) lwip_stats.mem.x = y
+#define MEM_STATS_INC(x) STATS_INC(mem.x)
+#define MEM_STATS_INC_USED(x, y) STATS_INC_USED(mem, y)
+#define MEM_STATS_DEC_USED(x, y) lwip_stats.mem.x -= y
+#define MEM_STATS_DISPLAY() stats_display_mem(&lwip_stats.mem, "HEAP")
+#else
+#define MEM_STATS_AVAIL(x, y)
+#define MEM_STATS_INC(x)
+#define MEM_STATS_INC_USED(x, y)
+#define MEM_STATS_DEC_USED(x, y)
+#define MEM_STATS_DISPLAY()
+#endif
+
+#if MEMP_STATS
+#define MEMP_STATS_AVAIL(x, i, y) lwip_stats.memp[i].x = y
+#define MEMP_STATS_INC(x, i) STATS_INC(memp[i].x)
+#define MEMP_STATS_DEC(x, i) STATS_DEC(memp[i].x)
+#define MEMP_STATS_INC_USED(x, i) STATS_INC_USED(memp[i], 1)
+#define MEMP_STATS_DISPLAY(i) stats_display_memp(&lwip_stats.memp[i], i)
+#else
+#define MEMP_STATS_AVAIL(x, i, y)
+#define MEMP_STATS_INC(x, i)
+#define MEMP_STATS_DEC(x, i)
+#define MEMP_STATS_INC_USED(x, i)
+#define MEMP_STATS_DISPLAY(i)
+#endif
+
+#if SYS_STATS
+#define SYS_STATS_INC(x) STATS_INC(sys.x)
+#define SYS_STATS_DEC(x) STATS_DEC(sys.x)
+#define SYS_STATS_INC_USED(x) STATS_INC_USED(sys.x, 1)
+#define SYS_STATS_DISPLAY() stats_display_sys(&lwip_stats.sys)
+#else
+#define SYS_STATS_INC(x)
+#define SYS_STATS_DEC(x)
+#define SYS_STATS_INC_USED(x)
+#define SYS_STATS_DISPLAY()
+#endif
+
+/* Display of statistics */
+#if LWIP_STATS_DISPLAY
+void stats_display(void);
+void stats_display_proto(struct stats_proto *proto, char *name);
+void stats_display_igmp(struct stats_igmp *igmp);
+void stats_display_mem(struct stats_mem *mem, char *name);
+void stats_display_memp(struct stats_mem *mem, int index);
+void stats_display_sys(struct stats_sys *sys);
+#else /* LWIP_STATS_DISPLAY */
+#define stats_display()
+#define stats_display_proto(proto, name)
+#define stats_display_igmp(igmp)
+#define stats_display_mem(mem, name)
+#define stats_display_memp(mem, index)
+#define stats_display_sys(sys)
+#endif /* LWIP_STATS_DISPLAY */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_STATS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/sys.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/sys.h
new file mode 100644
index 0000000..9f62c75
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/sys.h
@@ -0,0 +1,331 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_SYS_H__
+#define __LWIP_SYS_H__
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if NO_SYS
+
+/* For a totally minimal and standalone system, we provide null
+   definitions of the sys_ functions. */
+typedef u8_t sys_sem_t;
+typedef u8_t sys_mutex_t;
+typedef u8_t sys_mbox_t;
+
+#define sys_sem_new(s, c) ERR_OK
+#define sys_sem_signal(s)
+#define sys_sem_wait(s)
+#define sys_arch_sem_wait(s,t)
+#define sys_sem_free(s)
+#define sys_mutex_new(mu) ERR_OK
+#define sys_mutex_lock(mu)
+#define sys_mutex_unlock(mu)
+#define sys_mutex_free(mu)
+#define sys_mbox_new(m, s) ERR_OK
+#define sys_mbox_fetch(m,d)
+#define sys_mbox_tryfetch(m,d)
+#define sys_mbox_post(m,d)
+#define sys_mbox_trypost(m,d)
+#define sys_mbox_free(m)
+
+#define sys_thread_new(n,t,a,s,p)
+
+#define sys_msleep(t)
+
+#else /* NO_SYS */
+
+/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */
+#define SYS_ARCH_TIMEOUT 0xffffffffUL
+
+/** sys_mbox_tryfetch() returns SYS_MBOX_EMPTY if appropriate.
+ * For now we use the same magic value, but we allow this to change in future.
+ */
+#define SYS_MBOX_EMPTY SYS_ARCH_TIMEOUT 
+
+#include "lwip/err.h"
+#include "arch/sys_arch.h"
+
+/** Function prototype for thread functions */
+typedef void (*lwip_thread_fn)(void *arg);
+
+/* Function prototypes for functions to be implemented by platform ports
+   (in sys_arch.c) */
+
+/* Mutex functions: */
+
+/** Define LWIP_COMPAT_MUTEX if the port has no mutexes and binary semaphores
+    should be used instead */
+#if LWIP_COMPAT_MUTEX
+/* for old ports that don't have mutexes: define them to binary semaphores */
+#define sys_mutex_t                   sys_sem_t
+#define sys_mutex_new(mutex)          sys_sem_new(mutex, 1)
+#define sys_mutex_lock(mutex)         sys_sem_wait(mutex)
+#define sys_mutex_unlock(mutex)       sys_sem_signal(mutex)
+#define sys_mutex_free(mutex)         sys_sem_free(mutex)
+#define sys_mutex_valid(mutex)        sys_sem_valid(mutex)
+#define sys_mutex_set_invalid(mutex)  sys_sem_set_invalid(mutex)
+
+#else /* LWIP_COMPAT_MUTEX */
+
+/** Create a new mutex
+ * @param mutex pointer to the mutex to create
+ * @return a new mutex */
+err_t sys_mutex_new(sys_mutex_t *mutex);
+/** Lock a mutex
+ * @param mutex the mutex to lock */
+void sys_mutex_lock(sys_mutex_t *mutex);
+/** Unlock a mutex
+ * @param mutex the mutex to unlock */
+void sys_mutex_unlock(sys_mutex_t *mutex);
+/** Delete a semaphore
+ * @param mutex the mutex to delete */
+void sys_mutex_free(sys_mutex_t *mutex); 
+#ifndef sys_mutex_valid
+/** Check if a mutex is valid/allocated: return 1 for valid, 0 for invalid */
+int sys_mutex_valid(sys_mutex_t *mutex);
+#endif
+#ifndef sys_mutex_set_invalid
+/** Set a mutex invalid so that sys_mutex_valid returns 0 */
+void sys_mutex_set_invalid(sys_mutex_t *mutex);
+#endif
+#endif /* LWIP_COMPAT_MUTEX */
+
+/* Semaphore functions: */
+
+/** Create a new semaphore
+ * @param sem pointer to the semaphore to create
+ * @param count initial count of the semaphore
+ * @return ERR_OK if successful, another err_t otherwise */
+err_t sys_sem_new(sys_sem_t *sem, u8_t count);
+/** Signals a semaphore
+ * @param sem the semaphore to signal */
+void sys_sem_signal(sys_sem_t *sem);
+/** Wait for a semaphore for the specified timeout
+ * @param sem the semaphore to wait for
+ * @param timeout timeout in milliseconds to wait (0 = wait forever)
+ * @return time (in milliseconds) waited for the semaphore
+ *         or SYS_ARCH_TIMEOUT on timeout */
+u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout);
+/** Delete a semaphore
+ * @param sem semaphore to delete */
+void sys_sem_free(sys_sem_t *sem);
+/** Wait for a semaphore - forever/no timeout */
+#define sys_sem_wait(sem)                  sys_arch_sem_wait(sem, 0)
+#ifndef sys_sem_valid
+/** Check if a sempahore is valid/allocated: return 1 for valid, 0 for invalid */
+int sys_sem_valid(sys_sem_t *sem);
+#endif
+#ifndef sys_sem_set_invalid
+/** Set a semaphore invalid so that sys_sem_valid returns 0 */
+void sys_sem_set_invalid(sys_sem_t *sem);
+#endif
+
+/* Time functions. */
+#ifndef sys_msleep
+void sys_msleep(u32_t ms); /* only has a (close to) 1 jiffy resolution. */
+#endif
+
+/* Mailbox functions. */
+
+/** Create a new mbox of specified size
+ * @param mbox pointer to the mbox to create
+ * @param size (miminum) number of messages in this mbox
+ * @return ERR_OK if successful, another err_t otherwise */
+err_t sys_mbox_new(sys_mbox_t *mbox, int size);
+/** Post a message to an mbox - may not fail
+ * -> blocks if full, only used from tasks not from ISR
+ * @param mbox mbox to posts the message
+ * @param msg message to post (ATTENTION: can be NULL) */
+void sys_mbox_post(sys_mbox_t *mbox, void *msg);
+/** Try to post a message to an mbox - may fail if full or ISR
+ * @param mbox mbox to posts the message
+ * @param msg message to post (ATTENTION: can be NULL) */
+err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg);
+/** Wait for a new message to arrive in the mbox
+ * @param mbox mbox to get a message from
+ * @param msg pointer where the message is stored
+ * @param timeout maximum time (in milliseconds) to wait for a message
+ * @return time (in milliseconds) waited for a message, may be 0 if not waited
+           or SYS_ARCH_TIMEOUT on timeout
+ *         The returned time has to be accurate to prevent timer jitter! */
+u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout);
+/* Allow port to override with a macro, e.g. special timout for sys_arch_mbox_fetch() */
+#ifndef sys_arch_mbox_tryfetch
+/** Wait for a new message to arrive in the mbox
+ * @param mbox mbox to get a message from
+ * @param msg pointer where the message is stored
+ * @param timeout maximum time (in milliseconds) to wait for a message
+ * @return 0 (milliseconds) if a message has been received
+ *         or SYS_MBOX_EMPTY if the mailbox is empty */
+u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg);
+#endif
+/** For now, we map straight to sys_arch implementation. */
+#define sys_mbox_tryfetch(mbox, msg) sys_arch_mbox_tryfetch(mbox, msg)
+/** Delete an mbox
+ * @param mbox mbox to delete */
+void sys_mbox_free(sys_mbox_t *mbox);
+#define sys_mbox_fetch(mbox, msg) sys_arch_mbox_fetch(mbox, msg, 0)
+#ifndef sys_mbox_valid
+/** Check if an mbox is valid/allocated: return 1 for valid, 0 for invalid */
+int sys_mbox_valid(sys_mbox_t *mbox);
+#endif
+#ifndef sys_mbox_set_invalid
+/** Set an mbox invalid so that sys_mbox_valid returns 0 */
+void sys_mbox_set_invalid(sys_mbox_t *mbox);
+#endif
+
+/** The only thread function:
+ * Creates a new thread
+ * @param name human-readable name for the thread (used for debugging purposes)
+ * @param thread thread-function
+ * @param arg parameter passed to 'thread'
+ * @param stacksize stack size in bytes for the new thread (may be ignored by ports)
+ * @param prio priority of the new thread (may be ignored by ports) */
+sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread, void *arg, int stacksize, int prio);
+
+#endif /* NO_SYS */
+
+/* sys_init() must be called before anthing else. */
+void sys_init(void);
+
+#ifndef sys_jiffies
+/** Ticks/jiffies since power up. */
+u32_t sys_jiffies(void);
+#endif
+
+/** Returns the current time in milliseconds,
+ * may be the same as sys_jiffies or at least based on it. */
+u32_t sys_now(void);
+
+/* Critical Region Protection */
+/* These functions must be implemented in the sys_arch.c file.
+   In some implementations they can provide a more light-weight protection
+   mechanism than using semaphores. Otherwise semaphores can be used for
+   implementation */
+#ifndef SYS_ARCH_PROTECT
+/** SYS_LIGHTWEIGHT_PROT
+ * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
+ * for certain critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#if SYS_LIGHTWEIGHT_PROT
+
+/** SYS_ARCH_DECL_PROTECT
+ * declare a protection variable. This macro will default to defining a variable of
+ * type sys_prot_t. If a particular port needs a different implementation, then
+ * this macro may be defined in sys_arch.h.
+ */
+#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev
+/** SYS_ARCH_PROTECT
+ * Perform a "fast" protect. This could be implemented by
+ * disabling interrupts for an embedded system or by using a semaphore or
+ * mutex. The implementation should allow calling SYS_ARCH_PROTECT when
+ * already protected. The old protection level is returned in the variable
+ * "lev". This macro will default to calling the sys_arch_protect() function
+ * which should be implemented in sys_arch.c. If a particular port needs a
+ * different implementation, then this macro may be defined in sys_arch.h
+ */
+#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect()
+/** SYS_ARCH_UNPROTECT
+ * Perform a "fast" set of the protection level to "lev". This could be
+ * implemented by setting the interrupt level to "lev" within the MACRO or by
+ * using a semaphore or mutex.  This macro will default to calling the
+ * sys_arch_unprotect() function which should be implemented in
+ * sys_arch.c. If a particular port needs a different implementation, then
+ * this macro may be defined in sys_arch.h
+ */
+#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev)
+sys_prot_t sys_arch_protect(void);
+void sys_arch_unprotect(sys_prot_t pval);
+
+#else
+
+#define SYS_ARCH_DECL_PROTECT(lev)
+#define SYS_ARCH_PROTECT(lev)
+#define SYS_ARCH_UNPROTECT(lev)
+
+#endif /* SYS_LIGHTWEIGHT_PROT */
+
+#endif /* SYS_ARCH_PROTECT */
+
+/*
+ * Macros to set/get and increase/decrease variables in a thread-safe way.
+ * Use these for accessing variable that are used from more than one thread.
+ */
+
+#ifndef SYS_ARCH_INC
+#define SYS_ARCH_INC(var, val) do { \
+                                SYS_ARCH_DECL_PROTECT(old_level); \
+                                SYS_ARCH_PROTECT(old_level); \
+                                var += val; \
+                                SYS_ARCH_UNPROTECT(old_level); \
+                              } while(0)
+#endif /* SYS_ARCH_INC */
+
+#ifndef SYS_ARCH_DEC
+#define SYS_ARCH_DEC(var, val) do { \
+                                SYS_ARCH_DECL_PROTECT(old_level); \
+                                SYS_ARCH_PROTECT(old_level); \
+                                var -= val; \
+                                SYS_ARCH_UNPROTECT(old_level); \
+                              } while(0)
+#endif /* SYS_ARCH_DEC */
+
+#ifndef SYS_ARCH_GET
+#define SYS_ARCH_GET(var, ret) do { \
+                                SYS_ARCH_DECL_PROTECT(old_level); \
+                                SYS_ARCH_PROTECT(old_level); \
+                                ret = var; \
+                                SYS_ARCH_UNPROTECT(old_level); \
+                              } while(0)
+#endif /* SYS_ARCH_GET */
+
+#ifndef SYS_ARCH_SET
+#define SYS_ARCH_SET(var, val) do { \
+                                SYS_ARCH_DECL_PROTECT(old_level); \
+                                SYS_ARCH_PROTECT(old_level); \
+                                var = val; \
+                                SYS_ARCH_UNPROTECT(old_level); \
+                              } while(0)
+#endif /* SYS_ARCH_SET */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_SYS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/tcp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/tcp.h
new file mode 100644
index 0000000..07dcd10
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/tcp.h
@@ -0,0 +1,377 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_TCP_H__
+#define __LWIP_TCP_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip.h"
+#include "lwip/icmp.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct tcp_pcb;
+
+/** Function prototype for tcp accept callback functions. Called when a new
+ * connection can be accepted on a listening pcb.
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param newpcb The new connection pcb
+ * @param err An error code if there has been an error accepting.
+ *            Only return ERR_ABRT if you have called tcp_abort from within the
+ *            callback function!
+ */
+typedef err_t (*tcp_accept_fn)(void *arg, struct tcp_pcb *newpcb, err_t err);
+
+/** Function prototype for tcp receive callback functions. Called when data has
+ * been received.
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param tpcb The connection pcb which received data
+ * @param p The received data (or NULL when the connection has been closed!)
+ * @param err An error code if there has been an error receiving
+ *            Only return ERR_ABRT if you have called tcp_abort from within the
+ *            callback function!
+ */
+typedef err_t (*tcp_recv_fn)(void *arg, struct tcp_pcb *tpcb,
+                             struct pbuf *p, err_t err);
+
+/** Function prototype for tcp sent callback functions. Called when sent data has
+ * been acknowledged by the remote side. Use it to free corresponding resources.
+ * This also means that the pcb has now space available to send new data.
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param tpcb The connection pcb for which data has been acknowledged
+ * @param len The amount of bytes acknowledged
+ * @return ERR_OK: try to send some data by calling tcp_output
+ *            Only return ERR_ABRT if you have called tcp_abort from within the
+ *            callback function!
+ */
+typedef err_t (*tcp_sent_fn)(void *arg, struct tcp_pcb *tpcb,
+                              u16_t len);
+
+/** Function prototype for tcp poll callback functions. Called periodically as
+ * specified by @see tcp_poll.
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param tpcb tcp pcb
+ * @return ERR_OK: try to send some data by calling tcp_output
+ *            Only return ERR_ABRT if you have called tcp_abort from within the
+ *            callback function!
+ */
+typedef err_t (*tcp_poll_fn)(void *arg, struct tcp_pcb *tpcb);
+
+/** Function prototype for tcp error callback functions. Called when the pcb
+ * receives a RST or is unexpectedly closed for any other reason.
+ *
+ * @note The corresponding pcb is already freed when this callback is called!
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param err Error code to indicate why the pcb has been closed
+ *            ERR_ABRT: aborted through tcp_abort or by a TCP timer
+ *            ERR_RST: the connection was reset by the remote host
+ */
+typedef void  (*tcp_err_fn)(void *arg, err_t err);
+
+/** Function prototype for tcp connected callback functions. Called when a pcb
+ * is connected to the remote side after initiating a connection attempt by
+ * calling tcp_connect().
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param tpcb The connection pcb which is connected
+ * @param err An unused error code, always ERR_OK currently ;-) TODO!
+ *            Only return ERR_ABRT if you have called tcp_abort from within the
+ *            callback function!
+ *
+ * @note When a connection attempt fails, the error callback is currently called!
+ */
+typedef err_t (*tcp_connected_fn)(void *arg, struct tcp_pcb *tpcb, err_t err);
+
+enum tcp_state {
+  CLOSED      = 0,
+  LISTEN      = 1,
+  SYN_SENT    = 2,
+  SYN_RCVD    = 3,
+  ESTABLISHED = 4,
+  FIN_WAIT_1  = 5,
+  FIN_WAIT_2  = 6,
+  CLOSE_WAIT  = 7,
+  CLOSING     = 8,
+  LAST_ACK    = 9,
+  TIME_WAIT   = 10
+};
+
+#if LWIP_CALLBACK_API
+  /* Function to call when a listener has been connected.
+   * @param arg user-supplied argument (tcp_pcb.callback_arg)
+   * @param pcb a new tcp_pcb that now is connected
+   * @param err an error argument (TODO: that is current always ERR_OK?)
+   * @return ERR_OK: accept the new connection,
+   *                 any other err_t abortsthe new connection
+   */
+#define DEF_ACCEPT_CALLBACK  tcp_accept_fn accept;
+#else /* LWIP_CALLBACK_API */
+#define DEF_ACCEPT_CALLBACK
+#endif /* LWIP_CALLBACK_API */
+
+/**
+ * members common to struct tcp_pcb and struct tcp_listen_pcb
+ */
+#define TCP_PCB_COMMON(type) \
+  type *next; /* for the linked list */ \
+  enum tcp_state state; /* TCP state */ \
+  u8_t prio; \
+  void *callback_arg; \
+  /* the accept callback for listen- and normal pcbs, if LWIP_CALLBACK_API */ \
+  DEF_ACCEPT_CALLBACK \
+  /* ports are in host byte order */ \
+  u16_t local_port
+
+
+/* the TCP protocol control block */
+struct tcp_pcb {
+/** common PCB members */
+  IP_PCB;
+/** protocol specific PCB members */
+  TCP_PCB_COMMON(struct tcp_pcb);
+
+  /* ports are in host byte order */
+  u16_t remote_port;
+  
+  u8_t flags;
+#define TF_ACK_DELAY   ((u8_t)0x01U)   /* Delayed ACK. */
+#define TF_ACK_NOW     ((u8_t)0x02U)   /* Immediate ACK. */
+#define TF_INFR        ((u8_t)0x04U)   /* In fast recovery. */
+#define TF_TIMESTAMP   ((u8_t)0x08U)   /* Timestamp option enabled */
+#define TF_RXCLOSED    ((u8_t)0x10U)   /* rx closed by tcp_shutdown */
+#define TF_FIN         ((u8_t)0x20U)   /* Connection was closed locally (FIN segment enqueued). */
+#define TF_NODELAY     ((u8_t)0x40U)   /* Disable Nagle algorithm */
+#define TF_NAGLEMEMERR ((u8_t)0x80U)   /* nagle enabled, memerr, try to output to prevent delayed ACK to happen */
+
+  /* the rest of the fields are in host byte order
+     as we have to do some math with them */
+  /* receiver variables */
+  u32_t rcv_nxt;   /* next seqno expected */
+  u16_t rcv_wnd;   /* receiver window available */
+  u16_t rcv_ann_wnd; /* receiver window to announce */
+  u32_t rcv_ann_right_edge; /* announced right edge of window */
+
+  /* Timers */
+  u32_t tmr;
+  u8_t polltmr, pollinterval;
+  
+  /* Retransmission timer. */
+  s16_t rtime;
+  
+  u16_t mss;   /* maximum segment size */
+  
+  /* RTT (round trip time) estimation variables */
+  u32_t rttest; /* RTT estimate in 500ms ticks */
+  u32_t rtseq;  /* sequence number being timed */
+  s16_t sa, sv; /* @todo document this */
+
+  s16_t rto;    /* retransmission time-out */
+  u8_t nrtx;    /* number of retransmissions */
+
+  /* fast retransmit/recovery */
+  u32_t lastack; /* Highest acknowledged seqno. */
+  u8_t dupacks;
+  
+  /* congestion avoidance/control variables */
+  u16_t cwnd;  
+  u16_t ssthresh;
+
+  /* sender variables */
+  u32_t snd_nxt;   /* next new seqno to be sent */
+  u16_t snd_wnd;   /* sender window */
+  u32_t snd_wl1, snd_wl2; /* Sequence and acknowledgement numbers of last
+                             window update. */
+  u32_t snd_lbb;       /* Sequence number of next byte to be buffered. */
+
+  u16_t acked;
+  
+  u16_t snd_buf;   /* Available buffer space for sending (in bytes). */
+#define TCP_SNDQUEUELEN_OVERFLOW (0xffffU-3)
+  u16_t snd_queuelen; /* Available buffer space for sending (in tcp_segs). */
+
+#if TCP_OVERSIZE
+  /* Extra bytes available at the end of the last pbuf in unsent. */
+  u16_t unsent_oversize;
+#endif /* TCP_OVERSIZE */ 
+
+  /* These are ordered by sequence number: */
+  struct tcp_seg *unsent;   /* Unsent (queued) segments. */
+  struct tcp_seg *unacked;  /* Sent but unacknowledged segments. */
+#if TCP_QUEUE_OOSEQ  
+  struct tcp_seg *ooseq;    /* Received out of sequence segments. */
+#endif /* TCP_QUEUE_OOSEQ */
+
+  struct pbuf *refused_data; /* Data previously received but not yet taken by upper layer */
+
+#if LWIP_CALLBACK_API
+  /* Function to be called when more send buffer space is available. */
+  tcp_sent_fn sent;
+  /* Function to be called when (in-sequence) data has arrived. */
+  tcp_recv_fn recv;
+  /* Function to be called when a connection has been set up. */
+  tcp_connected_fn connected;
+  /* Function which is called periodically. */
+  tcp_poll_fn poll;
+  /* Function to be called whenever a fatal error occurs. */
+  tcp_err_fn errf;
+#endif /* LWIP_CALLBACK_API */
+
+#if LWIP_TCP_TIMESTAMPS
+  u32_t ts_lastacksent;
+  u32_t ts_recent;
+#endif /* LWIP_TCP_TIMESTAMPS */
+
+  /* idle time before KEEPALIVE is sent */
+  u32_t keep_idle;
+#if LWIP_TCP_KEEPALIVE
+  u32_t keep_intvl;
+  u32_t keep_cnt;
+#endif /* LWIP_TCP_KEEPALIVE */
+  
+  /* Persist timer counter */
+  u32_t persist_cnt;
+  /* Persist timer back-off */
+  u8_t persist_backoff;
+
+  /* KEEPALIVE counter */
+  u8_t keep_cnt_sent;
+};
+
+struct tcp_pcb_listen {  
+/* Common members of all PCB types */
+  IP_PCB;
+/* Protocol specific PCB members */
+  TCP_PCB_COMMON(struct tcp_pcb_listen);
+
+#if TCP_LISTEN_BACKLOG
+  u8_t backlog;
+  u8_t accepts_pending;
+#endif /* TCP_LISTEN_BACKLOG */
+};
+
+#if LWIP_EVENT_API
+
+enum lwip_event {
+  LWIP_EVENT_ACCEPT,
+  LWIP_EVENT_SENT,
+  LWIP_EVENT_RECV,
+  LWIP_EVENT_CONNECTED,
+  LWIP_EVENT_POLL,
+  LWIP_EVENT_ERR
+};
+
+err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb,
+         enum lwip_event,
+         struct pbuf *p,
+         u16_t size,
+         err_t err);
+
+#endif /* LWIP_EVENT_API */
+
+/* Application program's interface: */
+struct tcp_pcb * tcp_new     (void);
+
+void             tcp_arg     (struct tcp_pcb *pcb, void *arg);
+void             tcp_accept  (struct tcp_pcb *pcb, tcp_accept_fn accept);
+void             tcp_recv    (struct tcp_pcb *pcb, tcp_recv_fn recv);
+void             tcp_sent    (struct tcp_pcb *pcb, tcp_sent_fn sent);
+void             tcp_poll    (struct tcp_pcb *pcb, tcp_poll_fn poll, u8_t interval);
+void             tcp_err     (struct tcp_pcb *pcb, tcp_err_fn err);
+
+#define          tcp_mss(pcb)             (((pcb)->flags & TF_TIMESTAMP) ? ((pcb)->mss - 12)  : (pcb)->mss)
+#define          tcp_sndbuf(pcb)          ((pcb)->snd_buf)
+#define          tcp_sndqueuelen(pcb)     ((pcb)->snd_queuelen)
+#define          tcp_nagle_disable(pcb)   ((pcb)->flags |= TF_NODELAY)
+#define          tcp_nagle_enable(pcb)    ((pcb)->flags &= ~TF_NODELAY)
+#define          tcp_nagle_disabled(pcb)  (((pcb)->flags & TF_NODELAY) != 0)
+
+#if TCP_LISTEN_BACKLOG
+#define          tcp_accepted(pcb) do { \
+  LWIP_ASSERT("pcb->state == LISTEN (called for wrong pcb?)", pcb->state == LISTEN); \
+  (((struct tcp_pcb_listen *)(pcb))->accepts_pending--); } while(0)
+#else  /* TCP_LISTEN_BACKLOG */
+#define          tcp_accepted(pcb) LWIP_ASSERT("pcb->state == LISTEN (called for wrong pcb?)", \
+                                               pcb->state == LISTEN)
+#endif /* TCP_LISTEN_BACKLOG */
+
+void             tcp_recved  (struct tcp_pcb *pcb, u16_t len);
+err_t            tcp_bind    (struct tcp_pcb *pcb, ip_addr_t *ipaddr,
+                              u16_t port);
+err_t            tcp_connect (struct tcp_pcb *pcb, ip_addr_t *ipaddr,
+                              u16_t port, tcp_connected_fn connected);
+
+struct tcp_pcb * tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog);
+#define          tcp_listen(pcb) tcp_listen_with_backlog(pcb, TCP_DEFAULT_LISTEN_BACKLOG)
+
+void             tcp_abort (struct tcp_pcb *pcb);
+err_t            tcp_close   (struct tcp_pcb *pcb);
+err_t            tcp_shutdown(struct tcp_pcb *pcb, int shut_rx, int shut_tx);
+
+/* Flags for "apiflags" parameter in tcp_write */
+#define TCP_WRITE_FLAG_COPY 0x01
+#define TCP_WRITE_FLAG_MORE 0x02
+
+err_t            tcp_write   (struct tcp_pcb *pcb, const void *dataptr, u16_t len,
+                              u8_t apiflags);
+
+void             tcp_setprio (struct tcp_pcb *pcb, u8_t prio);
+
+#define TCP_PRIO_MIN    1
+#define TCP_PRIO_NORMAL 64
+#define TCP_PRIO_MAX    127
+
+err_t            tcp_output  (struct tcp_pcb *pcb);
+
+
+const char* tcp_debug_state_str(enum tcp_state s);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_TCP */
+
+#endif /* __LWIP_TCP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/tcp_impl.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/tcp_impl.h
new file mode 100644
index 0000000..b4feec0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/tcp_impl.h
@@ -0,0 +1,471 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_TCP_IMPL_H__
+#define __LWIP_TCP_IMPL_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/tcp.h"
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip.h"
+#include "lwip/icmp.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Functions for interfacing with TCP: */
+
+/* Lower layer interface to TCP: */
+#define tcp_init() /* Compatibility define, no init needed. */
+void             tcp_tmr     (void);  /* Must be called every
+                                         TCP_TMR_INTERVAL
+                                         ms. (Typically 250 ms). */
+/* It is also possible to call these two functions at the right
+   intervals (instead of calling tcp_tmr()). */
+void             tcp_slowtmr (void);
+void             tcp_fasttmr (void);
+
+
+/* Only used by IP to pass a TCP segment to TCP: */
+void             tcp_input   (struct pbuf *p, struct netif *inp);
+/* Used within the TCP code only: */
+struct tcp_pcb * tcp_alloc   (u8_t prio);
+void             tcp_abandon (struct tcp_pcb *pcb, int reset);
+err_t            tcp_send_empty_ack(struct tcp_pcb *pcb);
+void             tcp_rexmit  (struct tcp_pcb *pcb);
+void             tcp_rexmit_rto  (struct tcp_pcb *pcb);
+void             tcp_rexmit_fast (struct tcp_pcb *pcb);
+u32_t            tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb);
+
+/**
+ * This is the Nagle algorithm: try to combine user data to send as few TCP
+ * segments as possible. Only send if
+ * - no previously transmitted data on the connection remains unacknowledged or
+ * - the TF_NODELAY flag is set (nagle algorithm turned off for this pcb) or
+ * - the only unsent segment is at least pcb->mss bytes long (or there is more
+ *   than one unsent segment - with lwIP, this can happen although unsent->len < mss)
+ * - or if we are in fast-retransmit (TF_INFR)
+ */
+#define tcp_do_output_nagle(tpcb) ((((tpcb)->unacked == NULL) || \
+                            ((tpcb)->flags & (TF_NODELAY | TF_INFR)) || \
+                            (((tpcb)->unsent != NULL) && (((tpcb)->unsent->next != NULL) || \
+                              ((tpcb)->unsent->len >= (tpcb)->mss))) \
+                            ) ? 1 : 0)
+#define tcp_output_nagle(tpcb) (tcp_do_output_nagle(tpcb) ? tcp_output(tpcb) : ERR_OK)
+
+
+#define TCP_SEQ_LT(a,b)     ((s32_t)((a)-(b)) < 0)
+#define TCP_SEQ_LEQ(a,b)    ((s32_t)((a)-(b)) <= 0)
+#define TCP_SEQ_GT(a,b)     ((s32_t)((a)-(b)) > 0)
+#define TCP_SEQ_GEQ(a,b)    ((s32_t)((a)-(b)) >= 0)
+/* is b<=a<=c? */
+#if 0 /* see bug #10548 */
+#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b))
+#endif
+#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c))
+#define TCP_FIN 0x01U
+#define TCP_SYN 0x02U
+#define TCP_RST 0x04U
+#define TCP_PSH 0x08U
+#define TCP_ACK 0x10U
+#define TCP_URG 0x20U
+#define TCP_ECE 0x40U
+#define TCP_CWR 0x80U
+
+#define TCP_FLAGS 0x3fU
+
+/* Length of the TCP header, excluding options. */
+#define TCP_HLEN 20
+
+#ifndef TCP_TMR_INTERVAL
+#define TCP_TMR_INTERVAL       250  /* The TCP timer interval in milliseconds. */
+#endif /* TCP_TMR_INTERVAL */
+
+#ifndef TCP_FAST_INTERVAL
+#define TCP_FAST_INTERVAL      TCP_TMR_INTERVAL /* the fine grained timeout in milliseconds */
+#endif /* TCP_FAST_INTERVAL */
+
+#ifndef TCP_SLOW_INTERVAL
+#define TCP_SLOW_INTERVAL      (2*TCP_TMR_INTERVAL)  /* the coarse grained timeout in milliseconds */
+#endif /* TCP_SLOW_INTERVAL */
+
+#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */
+#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */
+
+#define TCP_OOSEQ_TIMEOUT        6U /* x RTO */
+
+#ifndef TCP_MSL
+#define TCP_MSL 60000UL /* The maximum segment lifetime in milliseconds */
+#endif
+
+/* Keepalive values, compliant with RFC 1122. Don't change this unless you know what you're doing */
+#ifndef  TCP_KEEPIDLE_DEFAULT
+#define  TCP_KEEPIDLE_DEFAULT     7200000UL /* Default KEEPALIVE timer in milliseconds */
+#endif
+
+#ifndef  TCP_KEEPINTVL_DEFAULT
+#define  TCP_KEEPINTVL_DEFAULT    75000UL   /* Default Time between KEEPALIVE probes in milliseconds */
+#endif
+
+#ifndef  TCP_KEEPCNT_DEFAULT
+#define  TCP_KEEPCNT_DEFAULT      9U        /* Default Counter for KEEPALIVE probes */
+#endif
+
+#define  TCP_MAXIDLE              TCP_KEEPCNT_DEFAULT * TCP_KEEPINTVL_DEFAULT  /* Maximum KEEPALIVE probe time */
+
+/* Fields are (of course) in network byte order.
+ * Some fields are converted to host byte order in tcp_input().
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct tcp_hdr {
+  PACK_STRUCT_FIELD(u16_t src);
+  PACK_STRUCT_FIELD(u16_t dest);
+  PACK_STRUCT_FIELD(u32_t seqno);
+  PACK_STRUCT_FIELD(u32_t ackno);
+  PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags);
+  PACK_STRUCT_FIELD(u16_t wnd);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u16_t urgp);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define TCPH_OFFSET(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 8)
+#define TCPH_HDRLEN(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 12)
+#define TCPH_FLAGS(phdr)  (ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS)
+
+#define TCPH_OFFSET_SET(phdr, offset) (phdr)->_hdrlen_rsvd_flags = htons(((offset) << 8) | TCPH_FLAGS(phdr))
+#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | TCPH_FLAGS(phdr))
+#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = (((phdr)->_hdrlen_rsvd_flags & PP_HTONS((u16_t)(~(u16_t)(TCP_FLAGS)))) | htons(flags))
+#define TCPH_HDRLEN_FLAGS_SET(phdr, len, flags) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | (flags))
+
+#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = ((phdr)->_hdrlen_rsvd_flags | htons(flags))
+#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (TCPH_FLAGS(phdr) & ~(flags)) )
+
+#define TCP_TCPLEN(seg) ((seg)->len + ((TCPH_FLAGS((seg)->tcphdr) & (TCP_FIN | TCP_SYN)) != 0))
+
+/** Flags used on input processing, not on pcb->flags
+*/
+#define TF_RESET     (u8_t)0x08U   /* Connection was reset. */
+#define TF_CLOSED    (u8_t)0x10U   /* Connection was sucessfully closed. */
+#define TF_GOT_FIN   (u8_t)0x20U   /* Connection was closed by the remote end. */
+
+
+#if LWIP_EVENT_API
+
+#define TCP_EVENT_ACCEPT(pcb,err,ret)    ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_ACCEPT, NULL, 0, err)
+#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                   LWIP_EVENT_SENT, NULL, space, ERR_OK)
+#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_RECV, (p), 0, (err))
+#define TCP_EVENT_CLOSED(pcb,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_RECV, NULL, 0, ERR_OK)
+#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_CONNECTED, NULL, 0, (err))
+#define TCP_EVENT_POLL(pcb,ret)       ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_POLL, NULL, 0, ERR_OK)
+#define TCP_EVENT_ERR(errf,arg,err)  lwip_tcp_event((arg), NULL, \
+                LWIP_EVENT_ERR, NULL, 0, (err))
+
+#else /* LWIP_EVENT_API */
+
+#define TCP_EVENT_ACCEPT(pcb,err,ret)                          \
+  do {                                                         \
+    if((pcb)->accept != NULL)                                  \
+      (ret) = (pcb)->accept((pcb)->callback_arg,(pcb),(err));  \
+    else (ret) = ERR_ARG;                                      \
+  } while (0)
+
+#define TCP_EVENT_SENT(pcb,space,ret)                          \
+  do {                                                         \
+    if((pcb)->sent != NULL)                                    \
+      (ret) = (pcb)->sent((pcb)->callback_arg,(pcb),(space));  \
+    else (ret) = ERR_OK;                                       \
+  } while (0)
+
+#define TCP_EVENT_RECV(pcb,p,err,ret)                          \
+  do {                                                         \
+    if((pcb)->recv != NULL) {                                  \
+      (ret) = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err));\
+    } else {                                                   \
+      (ret) = tcp_recv_null(NULL, (pcb), (p), (err));          \
+    }                                                          \
+  } while (0)
+
+#define TCP_EVENT_CLOSED(pcb,ret)                                \
+  do {                                                           \
+    if(((pcb)->recv != NULL)) {                                  \
+      (ret) = (pcb)->recv((pcb)->callback_arg,(pcb),NULL,ERR_OK);\
+    } else {                                                     \
+      (ret) = ERR_OK;                                            \
+    }                                                            \
+  } while (0)
+
+#define TCP_EVENT_CONNECTED(pcb,err,ret)                         \
+  do {                                                           \
+    if((pcb)->connected != NULL)                                 \
+      (ret) = (pcb)->connected((pcb)->callback_arg,(pcb),(err)); \
+    else (ret) = ERR_OK;                                         \
+  } while (0)
+
+#define TCP_EVENT_POLL(pcb,ret)                                \
+  do {                                                         \
+    if((pcb)->poll != NULL)                                    \
+      (ret) = (pcb)->poll((pcb)->callback_arg,(pcb));          \
+    else (ret) = ERR_OK;                                       \
+  } while (0)
+
+#define TCP_EVENT_ERR(errf,arg,err)                            \
+  do {                                                         \
+    if((errf) != NULL)                                         \
+      (errf)((arg),(err));                                     \
+  } while (0)
+
+#endif /* LWIP_EVENT_API */
+
+/** Enabled extra-check for TCP_OVERSIZE if LWIP_DEBUG is enabled */
+#if TCP_OVERSIZE && defined(LWIP_DEBUG)
+#define TCP_OVERSIZE_DBGCHECK 1
+#else
+#define TCP_OVERSIZE_DBGCHECK 0
+#endif
+
+/** Don't generate checksum on copy if CHECKSUM_GEN_TCP is disabled */
+#define TCP_CHECKSUM_ON_COPY  (LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_TCP)
+
+/* This structure represents a TCP segment on the unsent, unacked and ooseq queues */
+struct tcp_seg {
+  struct tcp_seg *next;    /* used when putting segements on a queue */
+  struct pbuf *p;          /* buffer containing data + TCP header */
+  u16_t len;               /* the TCP length of this segment */
+#if TCP_OVERSIZE_DBGCHECK
+  u16_t oversize_left;     /* Extra bytes available at the end of the last
+                              pbuf in unsent (used for asserting vs.
+                              tcp_pcb.unsent_oversized only) */
+#endif /* TCP_OVERSIZE_DBGCHECK */ 
+#if TCP_CHECKSUM_ON_COPY
+  u16_t chksum;
+  u8_t  chksum_swapped;
+#endif /* TCP_CHECKSUM_ON_COPY */
+  u8_t  flags;
+#define TF_SEG_OPTS_MSS         (u8_t)0x01U /* Include MSS option. */
+#define TF_SEG_OPTS_TS          (u8_t)0x02U /* Include timestamp option. */
+#define TF_SEG_DATA_CHECKSUMMED (u8_t)0x04U /* ALL data (not the header) is
+                                               checksummed into 'chksum' */
+  struct tcp_hdr *tcphdr;  /* the TCP header */
+};
+
+#define LWIP_TCP_OPT_LENGTH(flags)              \
+  (flags & TF_SEG_OPTS_MSS ? 4  : 0) +          \
+  (flags & TF_SEG_OPTS_TS  ? 12 : 0)
+
+/** This returns a TCP header option for MSS in an u32_t */
+#define TCP_BUILD_MSS_OPTION(x) (x) = PP_HTONL(((u32_t)2 << 24) |          \
+                                               ((u32_t)4 << 16) |          \
+                                               (((u32_t)TCP_MSS / 256) << 8) | \
+                                               (TCP_MSS & 255))
+
+/* Global variables: */
+extern struct tcp_pcb *tcp_input_pcb;
+extern u32_t tcp_ticks;
+
+/* The TCP PCB lists. */
+union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */
+  struct tcp_pcb_listen *listen_pcbs; 
+  struct tcp_pcb *pcbs;
+};
+extern struct tcp_pcb *tcp_bound_pcbs;
+extern union tcp_listen_pcbs_t tcp_listen_pcbs;
+extern struct tcp_pcb *tcp_active_pcbs;  /* List of all TCP PCBs that are in a
+              state in which they accept or send
+              data. */
+extern struct tcp_pcb *tcp_tw_pcbs;      /* List of all TCP PCBs in TIME-WAIT. */
+
+extern struct tcp_pcb *tcp_tmp_pcb;      /* Only used for temporary storage. */
+
+/* Axioms about the above lists:   
+   1) Every TCP PCB that is not CLOSED is in one of the lists.
+   2) A PCB is only in one of the lists.
+   3) All PCBs in the tcp_listen_pcbs list is in LISTEN state.
+   4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state.
+*/
+/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB
+   with a PCB list or removes a PCB from a list, respectively. */
+#ifndef TCP_DEBUG_PCB_LISTS
+#define TCP_DEBUG_PCB_LISTS 0
+#endif
+#if TCP_DEBUG_PCB_LISTS
+#define TCP_REG(pcbs, npcb) do {\
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %d\n", (npcb), (npcb)->local_port)); \
+                            for(tcp_tmp_pcb = *(pcbs); \
+          tcp_tmp_pcb != NULL; \
+        tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+                                LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != (npcb)); \
+                            } \
+                            LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", ((pcbs) == &tcp_bound_pcbs) || ((npcb)->state != CLOSED)); \
+                            (npcb)->next = *(pcbs); \
+                            LWIP_ASSERT("TCP_REG: npcb->next != npcb", (npcb)->next != (npcb)); \
+                            *(pcbs) = (npcb); \
+                            LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
+              tcp_timer_needed(); \
+                            } while(0)
+#define TCP_RMV(pcbs, npcb) do { \
+                            LWIP_ASSERT("TCP_RMV: pcbs != NULL", *(pcbs) != NULL); \
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", (npcb), *(pcbs))); \
+                            if(*(pcbs) == (npcb)) { \
+                               *(pcbs) = (*pcbs)->next; \
+                            } else for(tcp_tmp_pcb = *(pcbs); tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+                               if(tcp_tmp_pcb->next == (npcb)) { \
+                                  tcp_tmp_pcb->next = (npcb)->next; \
+                                  break; \
+                               } \
+                            } \
+                            (npcb)->next = NULL; \
+                            LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", (npcb), *(pcbs))); \
+                            } while(0)
+
+#else /* LWIP_DEBUG */
+
+#define TCP_REG(pcbs, npcb)                        \
+  do {                                             \
+    (npcb)->next = *pcbs;                          \
+    *(pcbs) = (npcb);                              \
+    tcp_timer_needed();                            \
+  } while (0)
+
+#define TCP_RMV(pcbs, npcb)                        \
+  do {                                             \
+    if(*(pcbs) == (npcb)) {                        \
+      (*(pcbs)) = (*pcbs)->next;                   \
+    }                                              \
+    else {                                         \
+      for(tcp_tmp_pcb = *pcbs;                     \
+          tcp_tmp_pcb != NULL;                     \
+          tcp_tmp_pcb = tcp_tmp_pcb->next) {       \
+        if(tcp_tmp_pcb->next == (npcb)) {          \
+          tcp_tmp_pcb->next = (npcb)->next;        \
+          break;                                   \
+        }                                          \
+      }                                            \
+    }                                              \
+    (npcb)->next = NULL;                           \
+  } while(0)
+
+#endif /* LWIP_DEBUG */
+
+
+/* Internal functions: */
+struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb);
+void tcp_pcb_purge(struct tcp_pcb *pcb);
+void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb);
+
+void tcp_segs_free(struct tcp_seg *seg);
+void tcp_seg_free(struct tcp_seg *seg);
+struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg);
+
+#define tcp_ack(pcb)                               \
+  do {                                             \
+    if((pcb)->flags & TF_ACK_DELAY) {              \
+      (pcb)->flags &= ~TF_ACK_DELAY;               \
+      (pcb)->flags |= TF_ACK_NOW;                  \
+    }                                              \
+    else {                                         \
+      (pcb)->flags |= TF_ACK_DELAY;                \
+    }                                              \
+  } while (0)
+
+#define tcp_ack_now(pcb)                           \
+  do {                                             \
+    (pcb)->flags |= TF_ACK_NOW;                    \
+  } while (0)
+
+err_t tcp_send_fin(struct tcp_pcb *pcb);
+err_t tcp_enqueue_flags(struct tcp_pcb *pcb, u8_t flags);
+
+void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg);
+
+void tcp_rst(u32_t seqno, u32_t ackno,
+       ip_addr_t *local_ip, ip_addr_t *remote_ip,
+       u16_t local_port, u16_t remote_port);
+
+u32_t tcp_next_iss(void);
+
+void tcp_keepalive(struct tcp_pcb *pcb);
+void tcp_zero_window_probe(struct tcp_pcb *pcb);
+
+#if TCP_CALCULATE_EFF_SEND_MSS
+u16_t tcp_eff_send_mss(u16_t sendmss, ip_addr_t *addr);
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+
+#if LWIP_CALLBACK_API
+err_t tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err);
+#endif /* LWIP_CALLBACK_API */
+
+#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
+void tcp_debug_print(struct tcp_hdr *tcphdr);
+void tcp_debug_print_flags(u8_t flags);
+void tcp_debug_print_state(enum tcp_state s);
+void tcp_debug_print_pcbs(void);
+s16_t tcp_pcbs_sane(void);
+#else
+#  define tcp_debug_print(tcphdr)
+#  define tcp_debug_print_flags(flags)
+#  define tcp_debug_print_state(s)
+#  define tcp_debug_print_pcbs()
+#  define tcp_pcbs_sane() 1
+#endif /* TCP_DEBUG */
+
+/** External function (implemented in timers.c), called when TCP detects
+ * that a timer is needed (i.e. active- or time-wait-pcb found). */
+void tcp_timer_needed(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_TCP */
+
+#endif /* __LWIP_TCP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/tcpip.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/tcpip.h
new file mode 100644
index 0000000..995ba8a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/tcpip.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_TCPIP_H__
+#define __LWIP_TCPIP_H__
+
+#include "lwip/opt.h"
+
+#if !NO_SYS /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/api_msg.h"
+#include "lwip/netifapi.h"
+#include "lwip/pbuf.h"
+#include "lwip/api.h"
+#include "lwip/sys.h"
+#include "lwip/timers.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Define this to something that triggers a watchdog. This is called from
+ * tcpip_thread after processing a message. */
+#ifndef LWIP_TCPIP_THREAD_ALIVE
+#define LWIP_TCPIP_THREAD_ALIVE()
+#endif
+
+#if LWIP_TCPIP_CORE_LOCKING
+/** The global semaphore to lock the stack. */
+extern sys_mutex_t lock_tcpip_core;
+#define LOCK_TCPIP_CORE()     sys_mutex_lock(&lock_tcpip_core)
+#define UNLOCK_TCPIP_CORE()   sys_mutex_unlock(&lock_tcpip_core)
+#define TCPIP_APIMSG(m)       tcpip_apimsg_lock(m)
+#define TCPIP_APIMSG_ACK(m)
+#define TCPIP_NETIFAPI(m)     tcpip_netifapi_lock(m)
+#define TCPIP_NETIFAPI_ACK(m)
+#else /* LWIP_TCPIP_CORE_LOCKING */
+#define LOCK_TCPIP_CORE()
+#define UNLOCK_TCPIP_CORE()
+#define TCPIP_APIMSG(m)       tcpip_apimsg(m)
+#define TCPIP_APIMSG_ACK(m)   sys_sem_signal(&m->conn->op_completed)
+#define TCPIP_NETIFAPI(m)     tcpip_netifapi(m)
+#define TCPIP_NETIFAPI_ACK(m) sys_sem_signal(&m->sem)
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+
+/** Function prototype for the init_done function passed to tcpip_init */
+typedef void (*tcpip_init_done_fn)(void *arg);
+/** Function prototype for functions passed to tcpip_callback() */
+typedef void (*tcpip_callback_fn)(void *ctx);
+
+void tcpip_init(tcpip_init_done_fn tcpip_init_done, void *arg);
+
+#if LWIP_NETCONN
+err_t tcpip_apimsg(struct api_msg *apimsg);
+#if LWIP_TCPIP_CORE_LOCKING
+err_t tcpip_apimsg_lock(struct api_msg *apimsg);
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+#endif /* LWIP_NETCONN */
+
+err_t tcpip_input(struct pbuf *p, struct netif *inp);
+
+#if LWIP_NETIF_API
+err_t tcpip_netifapi(struct netifapi_msg *netifapimsg);
+#if LWIP_TCPIP_CORE_LOCKING
+err_t tcpip_netifapi_lock(struct netifapi_msg *netifapimsg);
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+#endif /* LWIP_NETIF_API */
+
+err_t tcpip_callback_with_block(tcpip_callback_fn function, void *ctx, u8_t block);
+#define tcpip_callback(f, ctx)              tcpip_callback_with_block(f, ctx, 1)
+
+/* free pbufs or heap memory from another context without blocking */
+err_t pbuf_free_callback(struct pbuf *p);
+err_t mem_free_callback(void *m);
+
+#if LWIP_TCPIP_TIMEOUT
+err_t tcpip_timeout(u32_t msecs, sys_timeout_handler h, void *arg);
+err_t tcpip_untimeout(sys_timeout_handler h, void *arg);
+#endif /* LWIP_TCPIP_TIMEOUT */
+
+enum tcpip_msg_type {
+#if LWIP_NETCONN
+  TCPIP_MSG_API,
+#endif /* LWIP_NETCONN */
+  TCPIP_MSG_INPKT,
+#if LWIP_NETIF_API
+  TCPIP_MSG_NETIFAPI,
+#endif /* LWIP_NETIF_API */
+#if LWIP_TCPIP_TIMEOUT
+  TCPIP_MSG_TIMEOUT,
+  TCPIP_MSG_UNTIMEOUT,
+#endif /* LWIP_TCPIP_TIMEOUT */
+  TCPIP_MSG_CALLBACK
+};
+
+struct tcpip_msg {
+  enum tcpip_msg_type type;
+  sys_sem_t *sem;
+  union {
+#if LWIP_NETCONN
+    struct api_msg *apimsg;
+#endif /* LWIP_NETCONN */
+#if LWIP_NETIF_API
+    struct netifapi_msg *netifapimsg;
+#endif /* LWIP_NETIF_API */
+    struct {
+      struct pbuf *p;
+      struct netif *netif;
+    } inp;
+    struct {
+      tcpip_callback_fn function;
+      void *ctx;
+    } cb;
+#if LWIP_TCPIP_TIMEOUT
+    struct {
+      u32_t msecs;
+      sys_timeout_handler h;
+      void *arg;
+    } tmo;
+#endif /* LWIP_TCPIP_TIMEOUT */
+  } msg;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !NO_SYS */
+
+#endif /* __LWIP_TCPIP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/timers.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/timers.h
new file mode 100644
index 0000000..fb92b4b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/timers.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *         Simon Goldschmidt
+ *
+ */
+#ifndef __LWIP_TIMERS_H__
+#define __LWIP_TIMERS_H__
+
+#include "lwip/opt.h"
+
+/* Timers are not supported when NO_SYS==1 and NO_SYS_NO_TIMERS==1 */
+#define LWIP_TIMERS (!NO_SYS || (NO_SYS && !NO_SYS_NO_TIMERS))
+
+#if LWIP_TIMERS
+
+#include "lwip/err.h"
+#include "lwip/sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef LWIP_DEBUG_TIMERNAMES
+#ifdef LWIP_DEBUG
+#define LWIP_DEBUG_TIMERNAMES SYS_DEBUG
+#else /* LWIP_DEBUG */
+#define LWIP_DEBUG_TIMERNAMES 0
+#endif /* LWIP_DEBUG*/
+#endif
+
+/** Function prototype for a timeout callback function. Register such a function
+ * using sys_timeout().
+ *
+ * @param arg Additional argument to pass to the function - set up by sys_timeout()
+ */
+typedef void (* sys_timeout_handler)(void *arg);
+
+struct sys_timeo {
+  struct sys_timeo *next;
+  u32_t time;
+  sys_timeout_handler h;
+  void *arg;
+#if LWIP_DEBUG_TIMERNAMES
+  const char* handler_name;
+#endif /* LWIP_DEBUG_TIMERNAMES */
+};
+
+void sys_timeouts_init(void);
+
+#if LWIP_DEBUG_TIMERNAMES
+void sys_timeout_debug(u32_t msecs, sys_timeout_handler handler, void *arg, const char* handler_name);
+#define sys_timeout(msecs, handler, arg) sys_timeout_debug(msecs, handler, arg, #handler)
+#else /* LWIP_DEBUG_TIMERNAMES */
+void sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg);
+#endif /* LWIP_DEBUG_TIMERNAMES */
+
+void sys_untimeout(sys_timeout_handler handler, void *arg);
+#if NO_SYS
+void sys_check_timeouts(void);
+void sys_restart_timeouts(void);
+#else /* NO_SYS */
+void sys_timeouts_mbox_fetch(sys_mbox_t *mbox, void **msg);
+#endif /* NO_SYS */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_TIMERS */
+#endif /* __LWIP_TIMERS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/udp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/udp.h
new file mode 100644
index 0000000..c98c1b3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/lwip/udp.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_UDP_H__
+#define __LWIP_UDP_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_UDP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/ip_addr.h"
+#include "lwip/ip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define UDP_HLEN 8
+
+/* Fields are (of course) in network byte order. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct udp_hdr {
+  PACK_STRUCT_FIELD(u16_t src);
+  PACK_STRUCT_FIELD(u16_t dest);  /* src/dest UDP ports */
+  PACK_STRUCT_FIELD(u16_t len);
+  PACK_STRUCT_FIELD(u16_t chksum);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define UDP_FLAGS_NOCHKSUM       0x01U
+#define UDP_FLAGS_UDPLITE        0x02U
+#define UDP_FLAGS_CONNECTED      0x04U
+#define UDP_FLAGS_MULTICAST_LOOP 0x08U
+
+struct udp_pcb;
+
+/** Function prototype for udp pcb receive callback functions
+ * addr and port are in same byte order as in the pcb
+ * The callback is responsible for freeing the pbuf
+ * if it's not used any more.
+ *
+ * ATTENTION: Be aware that 'addr' points into the pbuf 'p' so freeing this pbuf
+ *            makes 'addr' invalid, too.
+ *
+ * @param arg user supplied argument (udp_pcb.recv_arg)
+ * @param pcb the udp_pcb which received data
+ * @param p the packet buffer that was received
+ * @param addr the remote IP address from which the packet was received
+ * @param port the remote port from which the packet was received
+ */
+typedef void (*udp_recv_fn)(void *arg, struct udp_pcb *pcb, struct pbuf *p,
+    ip_addr_t *addr, u16_t port);
+
+
+struct udp_pcb {
+/* Common members of all PCB types */
+  IP_PCB;
+
+/* Protocol specific PCB members */
+
+  struct udp_pcb *next;
+
+  u8_t flags;
+  /** ports are in host byte order */
+  u16_t local_port, remote_port;
+
+#if LWIP_IGMP
+  /** outgoing network interface for multicast packets */
+  ip_addr_t multicast_ip;
+#endif /* LWIP_IGMP */
+
+#if LWIP_UDPLITE
+  /** used for UDP_LITE only */
+  u16_t chksum_len_rx, chksum_len_tx;
+#endif /* LWIP_UDPLITE */
+
+  /** receive callback function */
+  udp_recv_fn recv;
+  /** user-supplied argument for the recv callback */
+  void *recv_arg;  
+};
+/* udp_pcbs export for exernal reference (e.g. SNMP agent) */
+extern struct udp_pcb *udp_pcbs;
+
+/* The following functions is the application layer interface to the
+   UDP code. */
+struct udp_pcb * udp_new        (void);
+void             udp_remove     (struct udp_pcb *pcb);
+err_t            udp_bind       (struct udp_pcb *pcb, ip_addr_t *ipaddr,
+                                 u16_t port);
+err_t            udp_connect    (struct udp_pcb *pcb, ip_addr_t *ipaddr,
+                                 u16_t port);
+void             udp_disconnect (struct udp_pcb *pcb);
+void             udp_recv       (struct udp_pcb *pcb, udp_recv_fn recv,
+                                 void *recv_arg);
+err_t            udp_sendto_if  (struct udp_pcb *pcb, struct pbuf *p,
+                                 ip_addr_t *dst_ip, u16_t dst_port,
+                                 struct netif *netif);
+err_t            udp_sendto     (struct udp_pcb *pcb, struct pbuf *p,
+                                 ip_addr_t *dst_ip, u16_t dst_port);
+err_t            udp_send       (struct udp_pcb *pcb, struct pbuf *p);
+
+#if LWIP_CHECKSUM_ON_COPY
+err_t            udp_sendto_if_chksum(struct udp_pcb *pcb, struct pbuf *p,
+                                 ip_addr_t *dst_ip, u16_t dst_port,
+                                 struct netif *netif, u8_t have_chksum,
+                                 u16_t chksum);
+err_t            udp_sendto_chksum(struct udp_pcb *pcb, struct pbuf *p,
+                                 ip_addr_t *dst_ip, u16_t dst_port,
+                                 u8_t have_chksum, u16_t chksum);
+err_t            udp_send_chksum(struct udp_pcb *pcb, struct pbuf *p,
+                                 u8_t have_chksum, u16_t chksum);
+#endif /* LWIP_CHECKSUM_ON_COPY */
+
+#define          udp_flags(pcb) ((pcb)->flags)
+#define          udp_setflags(pcb, f)  ((pcb)->flags = (f))
+
+/* The following functions are the lower layer interface to UDP. */
+void             udp_input      (struct pbuf *p, struct netif *inp);
+
+#define udp_init() /* Compatibility define, not init needed. */
+
+#if UDP_DEBUG
+void udp_debug_print(struct udp_hdr *udphdr);
+#else
+#define udp_debug_print(udphdr)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_UDP */
+
+#endif /* __LWIP_UDP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/netif/etharp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/netif/etharp.h
new file mode 100644
index 0000000..691575f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/netif/etharp.h
@@ -0,0 +1,221 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (c) 2003-2004 Leon Woestenberg 
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef __NETIF_ETHARP_H__
+#define __NETIF_ETHARP_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_ARP || LWIP_ETHERNET /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/ip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef ETHARP_HWADDR_LEN
+#define ETHARP_HWADDR_LEN     6
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct eth_addr {
+  PACK_STRUCT_FIELD(u8_t addr[ETHARP_HWADDR_LEN]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** Ethernet header */
+struct eth_hdr {
+#if ETH_PAD_SIZE
+  PACK_STRUCT_FIELD(u8_t padding[ETH_PAD_SIZE]);
+#endif
+  PACK_STRUCT_FIELD(struct eth_addr dest);
+  PACK_STRUCT_FIELD(struct eth_addr src);
+  PACK_STRUCT_FIELD(u16_t type);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define SIZEOF_ETH_HDR (14 + ETH_PAD_SIZE)
+
+#if ETHARP_SUPPORT_VLAN
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** VLAN header inserted between ethernet header and payload
+ * if 'type' in ethernet header is ETHTYPE_VLAN.
+ * See IEEE802.Q */
+struct eth_vlan_hdr {
+  PACK_STRUCT_FIELD(u16_t prio_vid);
+  PACK_STRUCT_FIELD(u16_t tpid);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define SIZEOF_VLAN_HDR 4
+#define VLAN_ID(vlan_hdr) (htons((vlan_hdr)->prio_vid) & 0xFFF)
+
+#endif /* ETHARP_SUPPORT_VLAN */
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** the ARP message, see RFC 826 ("Packet format") */
+struct etharp_hdr {
+  PACK_STRUCT_FIELD(u16_t hwtype);
+  PACK_STRUCT_FIELD(u16_t proto);
+  PACK_STRUCT_FIELD(u8_t  hwlen);
+  PACK_STRUCT_FIELD(u8_t  protolen);
+  PACK_STRUCT_FIELD(u16_t opcode);
+  PACK_STRUCT_FIELD(struct eth_addr shwaddr);
+  PACK_STRUCT_FIELD(struct ip_addr2 sipaddr);
+  PACK_STRUCT_FIELD(struct eth_addr dhwaddr);
+  PACK_STRUCT_FIELD(struct ip_addr2 dipaddr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define SIZEOF_ETHARP_HDR 28
+#define SIZEOF_ETHARP_PACKET (SIZEOF_ETH_HDR + SIZEOF_ETHARP_HDR)
+
+/** 5 seconds period */
+#define ARP_TMR_INTERVAL 5000
+
+#define ETHTYPE_ARP       0x0806U
+#define ETHTYPE_IP        0x0800U
+#define ETHTYPE_VLAN      0x8100U
+#define ETHTYPE_PPPOEDISC 0x8863U  /* PPP Over Ethernet Discovery Stage */
+#define ETHTYPE_PPPOE     0x8864U  /* PPP Over Ethernet Session Stage */
+
+/** MEMCPY-like macro to copy to/from struct eth_addr's that are local variables
+ * or known to be 32-bit aligned within the protocol header. */
+#ifndef ETHADDR32_COPY
+#define ETHADDR32_COPY(src, dst)  SMEMCPY(src, dst, ETHARP_HWADDR_LEN)
+#endif
+
+/** MEMCPY-like macro to copy to/from struct eth_addr's that are no local
+ * variables and known to be 16-bit aligned within the protocol header. */
+#ifndef ETHADDR16_COPY
+#define ETHADDR16_COPY(src, dst)  SMEMCPY(src, dst, ETHARP_HWADDR_LEN)
+#endif
+
+#if LWIP_ARP /* don't build if not configured for use in lwipopts.h */
+
+/** ARP message types (opcodes) */
+#define ARP_REQUEST 1
+#define ARP_REPLY   2
+
+/** Define this to 1 and define LWIP_ARP_FILTER_NETIF_FN(pbuf, netif, type)
+ * to a filter function that returns the correct netif when using multiple
+ * netifs on one hardware interface where the netif's low-level receive
+ * routine cannot decide for the correct netif (e.g. when mapping multiple
+ * IP addresses to one hardware interface).
+ */
+#ifndef LWIP_ARP_FILTER_NETIF
+#define LWIP_ARP_FILTER_NETIF 0
+#endif
+
+#if ARP_QUEUEING
+/** struct for queueing outgoing packets for unknown address
+  * defined here to be accessed by memp.h
+  */
+struct etharp_q_entry {
+  struct etharp_q_entry *next;
+  struct pbuf *p;
+};
+#endif /* ARP_QUEUEING */
+
+#define etharp_init() /* Compatibility define, not init needed. */
+void etharp_tmr(void);
+s8_t etharp_find_addr(struct netif *netif, ip_addr_t *ipaddr,
+         struct eth_addr **eth_ret, ip_addr_t **ip_ret);
+err_t etharp_output(struct netif *netif, struct pbuf *q, ip_addr_t *ipaddr);
+err_t etharp_query(struct netif *netif, ip_addr_t *ipaddr, struct pbuf *q);
+err_t etharp_request(struct netif *netif, ip_addr_t *ipaddr);
+/** For Ethernet network interfaces, we might want to send "gratuitous ARP";
+ *  this is an ARP packet sent by a node in order to spontaneously cause other
+ *  nodes to update an entry in their ARP cache.
+ *  From RFC 3220 "IP Mobility Support for IPv4" section 4.6. */
+#define etharp_gratuitous(netif) etharp_request((netif), &(netif)->ip_addr)
+
+#if ETHARP_SUPPORT_STATIC_ENTRIES
+err_t etharp_add_static_entry(ip_addr_t *ipaddr, struct eth_addr *ethaddr);
+err_t etharp_remove_static_entry(ip_addr_t *ipaddr);
+#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
+
+#if LWIP_AUTOIP
+err_t etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr,
+                 const struct eth_addr *ethdst_addr,
+                 const struct eth_addr *hwsrc_addr, const ip_addr_t *ipsrc_addr,
+                 const struct eth_addr *hwdst_addr, const ip_addr_t *ipdst_addr,
+                 const u16_t opcode);
+#endif /* LWIP_AUTOIP */
+
+#endif /* LWIP_ARP */
+
+err_t ethernet_input(struct pbuf *p, struct netif *netif);
+
+#define eth_addr_cmp(addr1, addr2) (memcmp((addr1)->addr, (addr2)->addr, ETHARP_HWADDR_LEN) == 0)
+
+extern const struct eth_addr ethbroadcast, ethzero;
+
+#endif /* LWIP_ARP || LWIP_ETHERNET */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NETIF_ARP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/netif/ppp_oe.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/netif/ppp_oe.h
new file mode 100644
index 0000000..e1cdfa5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/netif/ppp_oe.h
@@ -0,0 +1,190 @@
+/*****************************************************************************
+* ppp_oe.h - PPP Over Ethernet implementation for lwIP.
+*
+* Copyright (c) 2006 by Marc Boucher, Services Informatiques (MBSI) inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 06-01-01 Marc Boucher 
+*   Ported to lwIP.
+*****************************************************************************/
+
+
+
+/* based on NetBSD: if_pppoe.c,v 1.64 2006/01/31 23:50:15 martin Exp */
+
+/*-
+ * Copyright (c) 2002 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Martin Husemann .
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef PPP_OE_H
+#define PPP_OE_H
+
+#include "lwip/opt.h"
+
+#if PPPOE_SUPPORT > 0
+
+#include "netif/etharp.h"
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct pppoehdr {
+  PACK_STRUCT_FIELD(u8_t vertype);
+  PACK_STRUCT_FIELD(u8_t code);
+  PACK_STRUCT_FIELD(u16_t session);
+  PACK_STRUCT_FIELD(u16_t plen);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct pppoetag {
+  PACK_STRUCT_FIELD(u16_t tag);
+  PACK_STRUCT_FIELD(u16_t len);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+
+#define PPPOE_STATE_INITIAL   0
+#define PPPOE_STATE_PADI_SENT 1
+#define PPPOE_STATE_PADR_SENT 2
+#define PPPOE_STATE_SESSION   3
+#define PPPOE_STATE_CLOSING   4
+/* passive */
+#define PPPOE_STATE_PADO_SENT 1
+
+#define PPPOE_HEADERLEN       sizeof(struct pppoehdr)
+#define PPPOE_VERTYPE         0x11    /* VER=1, TYPE = 1 */
+
+#define PPPOE_TAG_EOL         0x0000  /* end of list */
+#define PPPOE_TAG_SNAME       0x0101  /* service name */
+#define PPPOE_TAG_ACNAME      0x0102  /* access concentrator name */
+#define PPPOE_TAG_HUNIQUE     0x0103  /* host unique */
+#define PPPOE_TAG_ACCOOKIE    0x0104  /* AC cookie */
+#define PPPOE_TAG_VENDOR      0x0105  /* vendor specific */
+#define PPPOE_TAG_RELAYSID    0x0110  /* relay session id */
+#define PPPOE_TAG_SNAME_ERR   0x0201  /* service name error */
+#define PPPOE_TAG_ACSYS_ERR   0x0202  /* AC system error */
+#define PPPOE_TAG_GENERIC_ERR 0x0203  /* gerneric error */
+
+#define PPPOE_CODE_PADI       0x09    /* Active Discovery Initiation */
+#define PPPOE_CODE_PADO       0x07    /* Active Discovery Offer */
+#define PPPOE_CODE_PADR       0x19    /* Active Discovery Request */
+#define PPPOE_CODE_PADS       0x65    /* Active Discovery Session confirmation */
+#define PPPOE_CODE_PADT       0xA7    /* Active Discovery Terminate */
+
+#ifndef ETHERMTU
+#define ETHERMTU 1500
+#endif
+
+/* two byte PPP protocol discriminator, then IP data */
+#define PPPOE_MAXMTU          (ETHERMTU-PPPOE_HEADERLEN-2)
+
+#ifndef PPPOE_MAX_AC_COOKIE_LEN
+#define PPPOE_MAX_AC_COOKIE_LEN   64
+#endif
+
+struct pppoe_softc {
+  struct pppoe_softc *next;
+  struct netif *sc_ethif;      /* ethernet interface we are using */
+  int sc_pd;                   /* ppp unit number */
+  void (*sc_linkStatusCB)(int pd, int up);
+
+  int sc_state;                /* discovery phase or session connected */
+  struct eth_addr sc_dest;     /* hardware address of concentrator */
+  u16_t sc_session;            /* PPPoE session id */
+
+#ifdef PPPOE_TODO
+  char *sc_service_name;       /* if != NULL: requested name of service */
+  char *sc_concentrator_name;  /* if != NULL: requested concentrator id */
+#endif /* PPPOE_TODO */
+  u8_t sc_ac_cookie[PPPOE_MAX_AC_COOKIE_LEN]; /* content of AC cookie we must echo back */
+  size_t sc_ac_cookie_len;     /* length of cookie data */
+#ifdef PPPOE_SERVER
+  u8_t *sc_hunique;            /* content of host unique we must echo back */
+  size_t sc_hunique_len;       /* length of host unique */
+#endif
+  int sc_padi_retried;         /* number of PADI retries already done */
+  int sc_padr_retried;         /* number of PADR retries already done */
+};
+
+
+#define pppoe_init() /* compatibility define, no initialization needed */
+
+err_t pppoe_create(struct netif *ethif, int pd, void (*linkStatusCB)(int pd, int up), struct pppoe_softc **scptr);
+err_t pppoe_destroy(struct netif *ifp);
+
+int pppoe_connect(struct pppoe_softc *sc);
+void pppoe_disconnect(struct pppoe_softc *sc);
+
+void pppoe_disc_input(struct netif *netif, struct pbuf *p);
+void pppoe_data_input(struct netif *netif, struct pbuf *p);
+
+err_t pppoe_xmit(struct pppoe_softc *sc, struct pbuf *pb);
+
+/** used in ppp.c */
+#define PPPOE_HDRLEN (sizeof(struct eth_hdr) + PPPOE_HEADERLEN)
+
+#endif /* PPPOE_SUPPORT */
+
+#endif /* PPP_OE_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/netif/slipif.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/netif/slipif.h
new file mode 100644
index 0000000..ccd03c8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/include/netif/slipif.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __NETIF_SLIPIF_H__
+#define __NETIF_SLIPIF_H__
+
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+err_t slipif_init(struct netif * netif);
+void slipif_poll(struct netif *netif);
+
+#ifdef __cplusplus
+}
+#endif
+ 
+#endif 
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/FILES b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/FILES
new file mode 100644
index 0000000..099dbf3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/FILES
@@ -0,0 +1,29 @@
+This directory contains generic network interface device drivers that
+do not contain any hardware or architecture specific code. The files
+are:
+
+etharp.c
+          Implements the ARP (Address Resolution Protocol) over
+          Ethernet. The code in this file should be used together with
+          Ethernet device drivers. Note that this module has been
+          largely made Ethernet independent so you should be able to
+          adapt this for other link layers (such as Firewire).
+
+ethernetif.c
+          An example of how an Ethernet device driver could look. This
+          file can be used as a "skeleton" for developing new Ethernet
+          network device drivers. It uses the etharp.c ARP code.
+
+loopif.c
+          A "loopback" network interface driver. It requires configuration
+          through the define LWIP_LOOPIF_MULTITHREADING (see opt.h).
+
+slipif.c
+          A generic implementation of the SLIP (Serial Line IP)
+          protocol. It requires a sio (serial I/O) module to work.
+
+ppp/      Point-to-Point Protocol stack
+          The PPP stack has been ported from ucip (http://ucip.sourceforge.net).
+          It matches quite well to pppd 2.3.1 (http://ppp.samba.org), although
+          compared to that, it has some modifications for embedded systems and
+          the source code has been reordered a bit.
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/etharp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/etharp.c
new file mode 100644
index 0000000..b60dadd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/etharp.c
@@ -0,0 +1,1318 @@
+/**
+ * @file
+ * Address Resolution Protocol module for IP over Ethernet
+ *
+ * Functionally, ARP is divided into two parts. The first maps an IP address
+ * to a physical address when sending a packet, and the second part answers
+ * requests from other machines for our physical address.
+ *
+ * This implementation complies with RFC 826 (Ethernet ARP). It supports
+ * Gratuitious ARP from RFC3220 (IP Mobility Support for IPv4) section 4.6
+ * if an interface calls etharp_gratuitous(our_netif) upon address change.
+ */
+
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (c) 2003-2004 Leon Woestenberg 
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+ 
+#include "lwip/opt.h"
+
+#if LWIP_ARP || LWIP_ETHERNET
+
+#include "lwip/ip_addr.h"
+#include "lwip/def.h"
+#include "lwip/ip.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+#include "lwip/dhcp.h"
+#include "lwip/autoip.h"
+#include "netif/etharp.h"
+
+#if PPPOE_SUPPORT
+#include "netif/ppp_oe.h"
+#endif /* PPPOE_SUPPORT */
+
+#include 
+
+const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}};
+const struct eth_addr ethzero = {{0,0,0,0,0,0}};
+
+#if LWIP_ARP /* don't build if not configured for use in lwipopts.h */
+
+/** the time an ARP entry stays valid after its last update,
+ *  for ARP_TMR_INTERVAL = 5000, this is
+ *  (240 * 5) seconds = 20 minutes.
+ */
+#define ARP_MAXAGE 240
+/** the time an ARP entry stays pending after first request,
+ *  for ARP_TMR_INTERVAL = 5000, this is
+ *  (2 * 5) seconds = 10 seconds.
+ * 
+ *  @internal Keep this number at least 2, otherwise it might
+ *  run out instantly if the timeout occurs directly after a request.
+ */
+#define ARP_MAXPENDING 2
+
+#define HWTYPE_ETHERNET 1
+
+enum etharp_state {
+  ETHARP_STATE_EMPTY = 0,
+  ETHARP_STATE_PENDING,
+  ETHARP_STATE_STABLE
+};
+
+struct etharp_entry {
+#if ARP_QUEUEING
+  /** Pointer to queue of pending outgoing packets on this ARP entry. */
+  struct etharp_q_entry *q;
+#else /* ARP_QUEUEING */
+  /** Pointer to a single pending outgoing packet on this ARP entry. */
+  struct pbuf *q;
+#endif /* ARP_QUEUEING */
+  ip_addr_t ipaddr;
+  struct eth_addr ethaddr;
+#if LWIP_SNMP
+  struct netif *netif;
+#endif /* LWIP_SNMP */
+  u8_t state;
+  u8_t ctime;
+#if ETHARP_SUPPORT_STATIC_ENTRIES
+  u8_t static_entry;
+#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
+};
+
+static struct etharp_entry arp_table[ARP_TABLE_SIZE];
+
+#if !LWIP_NETIF_HWADDRHINT
+static u8_t etharp_cached_entry;
+#endif /* !LWIP_NETIF_HWADDRHINT */
+
+/** Try hard to create a new entry - we want the IP address to appear in
+    the cache (even if this means removing an active entry or so). */
+#define ETHARP_FLAG_TRY_HARD     1
+#define ETHARP_FLAG_FIND_ONLY    2
+#define ETHARP_FLAG_STATIC_ENTRY 4
+
+#if LWIP_NETIF_HWADDRHINT
+#define ETHARP_SET_HINT(netif, hint)  if (((netif) != NULL) && ((netif)->addr_hint != NULL))  \
+                                      *((netif)->addr_hint) = (hint);
+#else /* LWIP_NETIF_HWADDRHINT */
+#define ETHARP_SET_HINT(netif, hint)  (etharp_cached_entry = (hint))
+#endif /* LWIP_NETIF_HWADDRHINT */
+
+static err_t update_arp_entry(struct netif *netif, ip_addr_t *ipaddr, struct eth_addr *ethaddr, u8_t flags);
+
+
+/* Some checks, instead of etharp_init(): */
+#if (LWIP_ARP && (ARP_TABLE_SIZE > 0x7f))
+  #error "ARP_TABLE_SIZE must fit in an s8_t, you have to reduce it in your lwipopts.h"
+#endif
+
+
+#if ARP_QUEUEING
+/**
+ * Free a complete queue of etharp entries
+ *
+ * @param q a qeueue of etharp_q_entry's to free
+ */
+static void
+free_etharp_q(struct etharp_q_entry *q)
+{
+  struct etharp_q_entry *r;
+  LWIP_ASSERT("q != NULL", q != NULL);
+  LWIP_ASSERT("q->p != NULL", q->p != NULL);
+  while (q) {
+    r = q;
+    q = q->next;
+    LWIP_ASSERT("r->p != NULL", (r->p != NULL));
+    pbuf_free(r->p);
+    memp_free(MEMP_ARP_QUEUE, r);
+  }
+}
+#else /* ARP_QUEUEING */
+
+/** Compatibility define: free the queued pbuf */
+#define free_etharp_q(q) pbuf_free(q)
+
+#endif /* ARP_QUEUEING */
+
+/** Clean up ARP table entries */
+static void
+free_entry(int i)
+{
+  /* remove from SNMP ARP index tree */
+  snmp_delete_arpidx_tree(arp_table[i].netif, &arp_table[i].ipaddr);
+  /* and empty packet queue */
+  if (arp_table[i].q != NULL) {
+    /* remove all queued packets */
+    LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].q)));
+    free_etharp_q(arp_table[i].q);
+    arp_table[i].q = NULL;
+  }
+  /* recycle entry for re-use */      
+  arp_table[i].state = ETHARP_STATE_EMPTY;
+#if ETHARP_SUPPORT_STATIC_ENTRIES
+  arp_table[i].static_entry = 0;
+#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
+#ifdef LWIP_DEBUG
+  /* for debugging, clean out the complete entry */
+  arp_table[i].ctime = 0;
+#if LWIP_SNMP
+  arp_table[i].netif = NULL;
+#endif /* LWIP_SNMP */
+  ip_addr_set_zero(&arp_table[i].ipaddr);
+  arp_table[i].ethaddr = ethzero;
+#endif /* LWIP_DEBUG */
+}
+
+/**
+ * Clears expired entries in the ARP table.
+ *
+ * This function should be called every ETHARP_TMR_INTERVAL milliseconds (5 seconds),
+ * in order to expire entries in the ARP table.
+ */
+void
+etharp_tmr(void)
+{
+  u8_t i;
+
+  LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n"));
+  /* remove expired entries from the ARP table */
+  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
+    u8_t state = arp_table[i].state;
+    if (state != ETHARP_STATE_EMPTY
+#if ETHARP_SUPPORT_STATIC_ENTRIES
+      && (arp_table[i].static_entry == 0)
+#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
+      ) {
+      arp_table[i].ctime++;
+      if ((arp_table[i].ctime >= ARP_MAXAGE) ||
+          ((arp_table[i].state == ETHARP_STATE_PENDING)  &&
+           (arp_table[i].ctime >= ARP_MAXPENDING))) {
+        /* pending or stable entry has become old! */
+        LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired %s entry %"U16_F".\n",
+             arp_table[i].state == ETHARP_STATE_STABLE ? "stable" : "pending", (u16_t)i));
+        /* clean up entries that have just been expired */
+        free_entry(i);
+      }
+#if ARP_QUEUEING
+      /* still pending entry? (not expired) */
+      if (arp_table[i].state == ETHARP_STATE_PENDING) {
+        /* resend an ARP query here? */
+      }
+#endif /* ARP_QUEUEING */
+    }
+  }
+}
+
+/**
+ * Search the ARP table for a matching or new entry.
+ * 
+ * If an IP address is given, return a pending or stable ARP entry that matches
+ * the address. If no match is found, create a new entry with this address set,
+ * but in state ETHARP_EMPTY. The caller must check and possibly change the
+ * state of the returned entry.
+ * 
+ * If ipaddr is NULL, return a initialized new entry in state ETHARP_EMPTY.
+ * 
+ * In all cases, attempt to create new entries from an empty entry. If no
+ * empty entries are available and ETHARP_FLAG_TRY_HARD flag is set, recycle
+ * old entries. Heuristic choose the least important entry for recycling.
+ *
+ * @param ipaddr IP address to find in ARP cache, or to add if not found.
+ * @param flags @see definition of ETHARP_FLAG_*
+ * @param netif netif related to this address (used for NETIF_HWADDRHINT)
+ *  
+ * @return The ARP entry index that matched or is created, ERR_MEM if no
+ * entry is found or could be recycled.
+ */
+static s8_t
+find_entry(ip_addr_t *ipaddr, u8_t flags)
+{
+  s8_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE;
+  s8_t empty = ARP_TABLE_SIZE;
+  u8_t i = 0, age_pending = 0, age_stable = 0;
+  /* oldest entry with packets on queue */
+  s8_t old_queue = ARP_TABLE_SIZE;
+  /* its age */
+  u8_t age_queue = 0;
+
+  /**
+   * a) do a search through the cache, remember candidates
+   * b) select candidate entry
+   * c) create new entry
+   */
+
+  /* a) in a single search sweep, do all of this
+   * 1) remember the first empty entry (if any)
+   * 2) remember the oldest stable entry (if any)
+   * 3) remember the oldest pending entry without queued packets (if any)
+   * 4) remember the oldest pending entry with queued packets (if any)
+   * 5) search for a matching IP entry, either pending or stable
+   *    until 5 matches, or all entries are searched for.
+   */
+
+  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
+    u8_t state = arp_table[i].state;
+    /* no empty entry found yet and now we do find one? */
+    if ((empty == ARP_TABLE_SIZE) && (state == ETHARP_STATE_EMPTY)) {
+      LWIP_DEBUGF(ETHARP_DEBUG, ("find_entry: found empty entry %"U16_F"\n", (u16_t)i));
+      /* remember first empty entry */
+      empty = i;
+    } else if (state != ETHARP_STATE_EMPTY) {
+      LWIP_ASSERT("state == ETHARP_STATE_PENDING || state == ETHARP_STATE_STABLE",
+        state == ETHARP_STATE_PENDING || state == ETHARP_STATE_STABLE);
+      /* if given, does IP address match IP address in ARP entry? */
+      if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: found matching entry %"U16_F"\n", (u16_t)i));
+        /* found exact IP address match, simply bail out */
+        return i;
+      }
+      /* pending entry? */
+      if (state == ETHARP_STATE_PENDING) {
+        /* pending with queued packets? */
+        if (arp_table[i].q != NULL) {
+          if (arp_table[i].ctime >= age_queue) {
+            old_queue = i;
+            age_queue = arp_table[i].ctime;
+          }
+        } else
+        /* pending without queued packets? */
+        {
+          if (arp_table[i].ctime >= age_pending) {
+            old_pending = i;
+            age_pending = arp_table[i].ctime;
+          }
+        }
+      /* stable entry? */
+      } else if (state == ETHARP_STATE_STABLE) {
+#if ETHARP_SUPPORT_STATIC_ENTRIES
+        /* don't record old_stable for static entries since they never expire */
+        if (arp_table[i].static_entry == 0)
+#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
+        {
+          /* remember entry with oldest stable entry in oldest, its age in maxtime */
+          if (arp_table[i].ctime >= age_stable) {
+            old_stable = i;
+            age_stable = arp_table[i].ctime;
+          }
+        }
+      }
+    }
+  }
+  /* { we have no match } => try to create a new entry */
+   
+  /* don't create new entry, only search? */
+  if (((flags & ETHARP_FLAG_FIND_ONLY) != 0) ||
+      /* or no empty entry found and not allowed to recycle? */
+      ((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_FLAG_TRY_HARD) == 0))) {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: no empty entry found and not allowed to recycle\n"));
+    return (s8_t)ERR_MEM;
+  }
+  
+  /* b) choose the least destructive entry to recycle:
+   * 1) empty entry
+   * 2) oldest stable entry
+   * 3) oldest pending entry without queued packets
+   * 4) oldest pending entry with queued packets
+   * 
+   * { ETHARP_FLAG_TRY_HARD is set at this point }
+   */ 
+
+  /* 1) empty entry available? */
+  if (empty < ARP_TABLE_SIZE) {
+    i = empty;
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting empty entry %"U16_F"\n", (u16_t)i));
+  } else {
+    /* 2) found recyclable stable entry? */
+    if (old_stable < ARP_TABLE_SIZE) {
+      /* recycle oldest stable*/
+      i = old_stable;
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting oldest stable entry %"U16_F"\n", (u16_t)i));
+      /* no queued packets should exist on stable entries */
+      LWIP_ASSERT("arp_table[i].q == NULL", arp_table[i].q == NULL);
+    /* 3) found recyclable pending entry without queued packets? */
+    } else if (old_pending < ARP_TABLE_SIZE) {
+      /* recycle oldest pending */
+      i = old_pending;
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F" (without queue)\n", (u16_t)i));
+    /* 4) found recyclable pending entry with queued packets? */
+    } else if (old_queue < ARP_TABLE_SIZE) {
+      /* recycle oldest pending (queued packets are free in free_entry) */
+      i = old_queue;
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F", freeing packet queue %p\n", (u16_t)i, (void *)(arp_table[i].q)));
+      /* no empty or recyclable entries found */
+    } else {
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("find_entry: no empty or recyclable entries found\n"));
+      return (s8_t)ERR_MEM;
+    }
+
+    /* { empty or recyclable entry found } */
+    LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
+    free_entry(i);
+  }
+
+  LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
+  LWIP_ASSERT("arp_table[i].state == ETHARP_STATE_EMPTY",
+    arp_table[i].state == ETHARP_STATE_EMPTY);
+
+  /* IP address given? */
+  if (ipaddr != NULL) {
+    /* set IP address */
+    ip_addr_copy(arp_table[i].ipaddr, *ipaddr);
+  }
+  arp_table[i].ctime = 0;
+#if ETHARP_SUPPORT_STATIC_ENTRIES
+  arp_table[i].static_entry = 0;
+#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
+  return (err_t)i;
+}
+
+/**
+ * Send an IP packet on the network using netif->linkoutput
+ * The ethernet header is filled in before sending.
+ *
+ * @params netif the lwIP network interface on which to send the packet
+ * @params p the packet to send, p->payload pointing to the (uninitialized) ethernet header
+ * @params src the source MAC address to be copied into the ethernet header
+ * @params dst the destination MAC address to be copied into the ethernet header
+ * @return ERR_OK if the packet was sent, any other err_t on failure
+ */
+static err_t
+etharp_send_ip(struct netif *netif, struct pbuf *p, struct eth_addr *src, struct eth_addr *dst)
+{
+  struct eth_hdr *ethhdr = (struct eth_hdr *)p->payload;
+
+  LWIP_ASSERT("netif->hwaddr_len must be the same as ETHARP_HWADDR_LEN for etharp!",
+              (netif->hwaddr_len == ETHARP_HWADDR_LEN));
+  ETHADDR32_COPY(ðhdr->dest, dst);
+  ETHADDR16_COPY(ðhdr->src, src);
+  ethhdr->type = PP_HTONS(ETHTYPE_IP);
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_send_ip: sending packet %p\n", (void *)p));
+  /* send the packet */
+  return netif->linkoutput(netif, p);
+}
+
+/**
+ * Update (or insert) a IP/MAC address pair in the ARP cache.
+ *
+ * If a pending entry is resolved, any queued packets will be sent
+ * at this point.
+ * 
+ * @param netif netif related to this entry (used for NETIF_ADDRHINT)
+ * @param ipaddr IP address of the inserted ARP entry.
+ * @param ethaddr Ethernet address of the inserted ARP entry.
+ * @param flags @see definition of ETHARP_FLAG_*
+ *
+ * @return
+ * - ERR_OK Succesfully updated ARP cache.
+ * - ERR_MEM If we could not add a new ARP entry when ETHARP_FLAG_TRY_HARD was set.
+ * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
+ *
+ * @see pbuf_free()
+ */
+static err_t
+update_arp_entry(struct netif *netif, ip_addr_t *ipaddr, struct eth_addr *ethaddr, u8_t flags)
+{
+  s8_t i;
+  LWIP_ASSERT("netif->hwaddr_len == ETHARP_HWADDR_LEN", netif->hwaddr_len == ETHARP_HWADDR_LEN);
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n",
+    ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr),
+    ethaddr->addr[0], ethaddr->addr[1], ethaddr->addr[2],
+    ethaddr->addr[3], ethaddr->addr[4], ethaddr->addr[5]));
+  /* non-unicast address? */
+  if (ip_addr_isany(ipaddr) ||
+      ip_addr_isbroadcast(ipaddr, netif) ||
+      ip_addr_ismulticast(ipaddr)) {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("update_arp_entry: will not add non-unicast IP address to ARP cache\n"));
+    return ERR_ARG;
+  }
+  /* find or create ARP entry */
+  i = find_entry(ipaddr, flags);
+  /* bail out if no entry could be found */
+  if (i < 0) {
+    return (err_t)i;
+  }
+
+#if ETHARP_SUPPORT_STATIC_ENTRIES
+  if (flags & ETHARP_FLAG_STATIC_ENTRY) {
+    /* record static type */
+    arp_table[i].static_entry = 1;
+  }
+#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
+
+  /* mark it stable */
+  arp_table[i].state = ETHARP_STATE_STABLE;
+
+#if LWIP_SNMP
+  /* record network interface */
+  arp_table[i].netif = netif;
+#endif /* LWIP_SNMP */
+  /* insert in SNMP ARP index tree */
+  snmp_insert_arpidx_tree(netif, &arp_table[i].ipaddr);
+
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("update_arp_entry: updating stable entry %"S16_F"\n", (s16_t)i));
+  /* update address */
+  ETHADDR32_COPY(&arp_table[i].ethaddr, ethaddr);
+  /* reset time stamp */
+  arp_table[i].ctime = 0;
+  /* this is where we will send out queued packets! */
+#if ARP_QUEUEING
+  while (arp_table[i].q != NULL) {
+    struct pbuf *p;
+    /* remember remainder of queue */
+    struct etharp_q_entry *q = arp_table[i].q;
+    /* pop first item off the queue */
+    arp_table[i].q = q->next;
+    /* get the packet pointer */
+    p = q->p;
+    /* now queue entry can be freed */
+    memp_free(MEMP_ARP_QUEUE, q);
+#else /* ARP_QUEUEING */
+  if (arp_table[i].q != NULL) {
+    struct pbuf *p = arp_table[i].q;
+    arp_table[i].q = NULL;
+#endif /* ARP_QUEUEING */
+    /* send the queued IP packet */
+    etharp_send_ip(netif, p, (struct eth_addr*)(netif->hwaddr), ethaddr);
+    /* free the queued IP packet */
+    pbuf_free(p);
+  }
+  return ERR_OK;
+}
+
+#if ETHARP_SUPPORT_STATIC_ENTRIES
+/** Add a new static entry to the ARP table. If an entry exists for the
+ * specified IP address, this entry is overwritten.
+ * If packets are queued for the specified IP address, they are sent out.
+ *
+ * @param ipaddr IP address for the new static entry
+ * @param ethaddr ethernet address for the new static entry
+ * @return @see return values of etharp_add_static_entry
+ */
+err_t
+etharp_add_static_entry(ip_addr_t *ipaddr, struct eth_addr *ethaddr)
+{
+  struct netif *netif;
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_add_static_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n",
+    ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr),
+    ethaddr->addr[0], ethaddr->addr[1], ethaddr->addr[2],
+    ethaddr->addr[3], ethaddr->addr[4], ethaddr->addr[5]));
+
+  netif = ip_route(ipaddr);
+  if (netif == NULL) {
+    return ERR_RTE;
+  }
+
+  return update_arp_entry(netif, ipaddr, ethaddr, ETHARP_FLAG_TRY_HARD | ETHARP_FLAG_STATIC_ENTRY);
+}
+
+/** Remove a static entry from the ARP table previously added with a call to
+ * etharp_add_static_entry.
+ *
+ * @param ipaddr IP address of the static entry to remove
+ * @return ERR_OK: entry removed
+ *         ERR_MEM: entry wasn't found
+ *         ERR_ARG: entry wasn't a static entry but a dynamic one
+ */
+err_t
+etharp_remove_static_entry(ip_addr_t *ipaddr)
+{
+  s8_t i;
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_remove_static_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+    ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr)));
+
+  /* find or create ARP entry */
+  i = find_entry(ipaddr, ETHARP_FLAG_FIND_ONLY);
+  /* bail out if no entry could be found */
+  if (i < 0) {
+    return (err_t)i;
+  }
+
+  if ((arp_table[i].state != ETHARP_STATE_STABLE) ||
+    (arp_table[i].static_entry == 0)) {
+    /* entry wasn't a static entry, cannot remove it */
+    return ERR_ARG;
+  }
+  /* entry found, free it */
+  free_entry(i);
+  return ERR_OK;
+}
+#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
+
+/**
+ * Finds (stable) ethernet/IP address pair from ARP table
+ * using interface and IP address index.
+ * @note the addresses in the ARP table are in network order!
+ *
+ * @param netif points to interface index
+ * @param ipaddr points to the (network order) IP address index
+ * @param eth_ret points to return pointer
+ * @param ip_ret points to return pointer
+ * @return table index if found, -1 otherwise
+ */
+s8_t
+etharp_find_addr(struct netif *netif, ip_addr_t *ipaddr,
+         struct eth_addr **eth_ret, ip_addr_t **ip_ret)
+{
+  s8_t i;
+
+  LWIP_ASSERT("eth_ret != NULL && ip_ret != NULL",
+    eth_ret != NULL && ip_ret != NULL);
+
+  LWIP_UNUSED_ARG(netif);
+
+  i = find_entry(ipaddr, ETHARP_FLAG_FIND_ONLY);
+  if((i >= 0) && arp_table[i].state == ETHARP_STATE_STABLE) {
+      *eth_ret = &arp_table[i].ethaddr;
+      *ip_ret = &arp_table[i].ipaddr;
+      return i;
+  }
+  return -1;
+}
+
+#if ETHARP_TRUST_IP_MAC
+/**
+ * Updates the ARP table using the given IP packet.
+ *
+ * Uses the incoming IP packet's source address to update the
+ * ARP cache for the local network. The function does not alter
+ * or free the packet. This function must be called before the
+ * packet p is passed to the IP layer.
+ *
+ * @param netif The lwIP network interface on which the IP packet pbuf arrived.
+ * @param p The IP packet that arrived on netif.
+ *
+ * @return NULL
+ *
+ * @see pbuf_free()
+ */
+static void
+etharp_ip_input(struct netif *netif, struct pbuf *p)
+{
+  struct eth_hdr *ethhdr;
+  struct ip_hdr *iphdr;
+  ip_addr_t iphdr_src;
+  LWIP_ERROR("netif != NULL", (netif != NULL), return;);
+
+  /* Only insert an entry if the source IP address of the
+     incoming IP packet comes from a host on the local network. */
+  ethhdr = (struct eth_hdr *)p->payload;
+  iphdr = (struct ip_hdr *)((u8_t*)ethhdr + SIZEOF_ETH_HDR);
+#if ETHARP_SUPPORT_VLAN
+  if (ethhdr->type == PP_HTONS(ETHTYPE_VLAN)) {
+    iphdr = (struct ip_hdr *)((u8_t*)ethhdr + SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR);
+  }
+#endif /* ETHARP_SUPPORT_VLAN */
+
+  ip_addr_copy(iphdr_src, iphdr->src);
+
+  /* source is not on the local network? */
+  if (!ip_addr_netcmp(&iphdr_src, &(netif->ip_addr), &(netif->netmask))) {
+    /* do nothing */
+    return;
+  }
+
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_ip_input: updating ETHARP table.\n"));
+  /* update the source IP address in the cache, if present */
+  /* @todo We could use ETHARP_FLAG_TRY_HARD if we think we are going to talk
+   * back soon (for example, if the destination IP address is ours. */
+  update_arp_entry(netif, &iphdr_src, &(ethhdr->src), ETHARP_FLAG_FIND_ONLY);
+}
+#endif /* ETHARP_TRUST_IP_MAC */
+
+/**
+ * Responds to ARP requests to us. Upon ARP replies to us, add entry to cache  
+ * send out queued IP packets. Updates cache with snooped address pairs.
+ *
+ * Should be called for incoming ARP packets. The pbuf in the argument
+ * is freed by this function.
+ *
+ * @param netif The lwIP network interface on which the ARP packet pbuf arrived.
+ * @param ethaddr Ethernet address of netif.
+ * @param p The ARP packet that arrived on netif. Is freed by this function.
+ *
+ * @return NULL
+ *
+ * @see pbuf_free()
+ */
+static void
+etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, struct pbuf *p)
+{
+  struct etharp_hdr *hdr;
+  struct eth_hdr *ethhdr;
+  /* these are aligned properly, whereas the ARP header fields might not be */
+  ip_addr_t sipaddr, dipaddr;
+  u8_t for_us;
+#if LWIP_AUTOIP
+  const u8_t * ethdst_hwaddr;
+#endif /* LWIP_AUTOIP */
+
+  LWIP_ERROR("netif != NULL", (netif != NULL), return;);
+
+  /* drop short ARP packets: we have to check for p->len instead of p->tot_len here
+     since a struct etharp_hdr is pointed to p->payload, so it musn't be chained! */
+  if (p->len < SIZEOF_ETHARP_PACKET) {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
+      ("etharp_arp_input: packet dropped, too short (%"S16_F"/%"S16_F")\n", p->tot_len,
+      (s16_t)SIZEOF_ETHARP_PACKET));
+    ETHARP_STATS_INC(etharp.lenerr);
+    ETHARP_STATS_INC(etharp.drop);
+    pbuf_free(p);
+    return;
+  }
+
+  ethhdr = (struct eth_hdr *)p->payload;
+  hdr = (struct etharp_hdr *)((u8_t*)ethhdr + SIZEOF_ETH_HDR);
+#if ETHARP_SUPPORT_VLAN
+  if (ethhdr->type == PP_HTONS(ETHTYPE_VLAN)) {
+    hdr = (struct etharp_hdr *)(((u8_t*)ethhdr) + SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR);
+  }
+#endif /* ETHARP_SUPPORT_VLAN */
+
+  /* RFC 826 "Packet Reception": */
+  if ((hdr->hwtype != PP_HTONS(HWTYPE_ETHERNET)) ||
+      (hdr->hwlen != ETHARP_HWADDR_LEN) ||
+      (hdr->protolen != sizeof(ip_addr_t)) ||
+      (hdr->proto != PP_HTONS(ETHTYPE_IP)))  {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
+      ("etharp_arp_input: packet dropped, wrong hw type, hwlen, proto, protolen or ethernet type (%"U16_F"/%"U16_F"/%"U16_F"/%"U16_F")\n",
+      hdr->hwtype, hdr->hwlen, hdr->proto, hdr->protolen));
+    ETHARP_STATS_INC(etharp.proterr);
+    ETHARP_STATS_INC(etharp.drop);
+    pbuf_free(p);
+    return;
+  }
+  ETHARP_STATS_INC(etharp.recv);
+
+#if LWIP_AUTOIP
+  /* We have to check if a host already has configured our random
+   * created link local address and continously check if there is
+   * a host with this IP-address so we can detect collisions */
+  autoip_arp_reply(netif, hdr);
+#endif /* LWIP_AUTOIP */
+
+  /* Copy struct ip_addr2 to aligned ip_addr, to support compilers without
+   * structure packing (not using structure copy which breaks strict-aliasing rules). */
+  IPADDR2_COPY(&sipaddr, &hdr->sipaddr);
+  IPADDR2_COPY(&dipaddr, &hdr->dipaddr);
+
+  /* this interface is not configured? */
+  if (ip_addr_isany(&netif->ip_addr)) {
+    for_us = 0;
+  } else {
+    /* ARP packet directed to us? */
+    for_us = (u8_t)ip_addr_cmp(&dipaddr, &(netif->ip_addr));
+  }
+
+  /* ARP message directed to us?
+      -> add IP address in ARP cache; assume requester wants to talk to us,
+         can result in directly sending the queued packets for this host.
+     ARP message not directed to us?
+      ->  update the source IP address in the cache, if present */
+  update_arp_entry(netif, &sipaddr, &(hdr->shwaddr),
+                   for_us ? ETHARP_FLAG_TRY_HARD : ETHARP_FLAG_FIND_ONLY);
+
+  /* now act on the message itself */
+  switch (hdr->opcode) {
+  /* ARP request? */
+  case PP_HTONS(ARP_REQUEST):
+    /* ARP request. If it asked for our address, we send out a
+     * reply. In any case, we time-stamp any existing ARP entry,
+     * and possiby send out an IP packet that was queued on it. */
+
+    LWIP_DEBUGF (ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: incoming ARP request\n"));
+    /* ARP request for our address? */
+    if (for_us) {
+
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: replying to ARP request for our IP address\n"));
+      /* Re-use pbuf to send ARP reply.
+         Since we are re-using an existing pbuf, we can't call etharp_raw since
+         that would allocate a new pbuf. */
+      hdr->opcode = htons(ARP_REPLY);
+
+      IPADDR2_COPY(&hdr->dipaddr, &hdr->sipaddr);
+      IPADDR2_COPY(&hdr->sipaddr, &netif->ip_addr);
+
+      LWIP_ASSERT("netif->hwaddr_len must be the same as ETHARP_HWADDR_LEN for etharp!",
+                  (netif->hwaddr_len == ETHARP_HWADDR_LEN));
+#if LWIP_AUTOIP
+      /* If we are using Link-Local, all ARP packets that contain a Link-Local
+       * 'sender IP address' MUST be sent using link-layer broadcast instead of
+       * link-layer unicast. (See RFC3927 Section 2.5, last paragraph) */
+      ethdst_hwaddr = ip_addr_islinklocal(&netif->ip_addr) ? (u8_t*)(ethbroadcast.addr) : hdr->shwaddr.addr;
+#endif /* LWIP_AUTOIP */
+
+      ETHADDR16_COPY(&hdr->dhwaddr, &hdr->shwaddr);
+#if LWIP_AUTOIP
+      ETHADDR16_COPY(ðhdr->dest, ethdst_hwaddr);
+#else  /* LWIP_AUTOIP */
+      ETHADDR16_COPY(ðhdr->dest, &hdr->shwaddr);
+#endif /* LWIP_AUTOIP */
+      ETHADDR16_COPY(&hdr->shwaddr, ethaddr);
+      ETHADDR16_COPY(ðhdr->src, ethaddr);
+
+      /* hwtype, hwaddr_len, proto, protolen and the type in the ethernet header
+         are already correct, we tested that before */
+
+      /* return ARP reply */
+      netif->linkoutput(netif, p);
+    /* we are not configured? */
+    } else if (ip_addr_isany(&netif->ip_addr)) {
+      /* { for_us == 0 and netif->ip_addr.addr == 0 } */
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: we are unconfigured, ARP request ignored.\n"));
+    /* request was not directed to us */
+    } else {
+      /* { for_us == 0 and netif->ip_addr.addr != 0 } */
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: ARP request was not for us.\n"));
+    }
+    break;
+  case PP_HTONS(ARP_REPLY):
+    /* ARP reply. We already updated the ARP cache earlier. */
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: incoming ARP reply\n"));
+#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK)
+    /* DHCP wants to know about ARP replies from any host with an
+     * IP address also offered to us by the DHCP server. We do not
+     * want to take a duplicate IP address on a single network.
+     * @todo How should we handle redundant (fail-over) interfaces? */
+    dhcp_arp_reply(netif, &sipaddr);
+#endif /* (LWIP_DHCP && DHCP_DOES_ARP_CHECK) */
+    break;
+  default:
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_arp_input: ARP unknown opcode type %"S16_F"\n", htons(hdr->opcode)));
+    ETHARP_STATS_INC(etharp.err);
+    break;
+  }
+  /* free ARP packet */
+  pbuf_free(p);
+}
+
+/**
+ * Resolve and fill-in Ethernet address header for outgoing IP packet.
+ *
+ * For IP multicast and broadcast, corresponding Ethernet addresses
+ * are selected and the packet is transmitted on the link.
+ *
+ * For unicast addresses, the packet is submitted to etharp_query(). In
+ * case the IP address is outside the local network, the IP address of
+ * the gateway is used.
+ *
+ * @param netif The lwIP network interface which the IP packet will be sent on.
+ * @param q The pbuf(s) containing the IP packet to be sent.
+ * @param ipaddr The IP address of the packet destination.
+ *
+ * @return
+ * - ERR_RTE No route to destination (no gateway to external networks),
+ * or the return type of either etharp_query() or etharp_send_ip().
+ */
+err_t
+etharp_output(struct netif *netif, struct pbuf *q, ip_addr_t *ipaddr)
+{
+  struct eth_addr *dest, mcastaddr;
+
+  /* make room for Ethernet header - should not fail */
+  if (pbuf_header(q, sizeof(struct eth_hdr)) != 0) {
+    /* bail out */
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
+      ("etharp_output: could not allocate room for header.\n"));
+    LINK_STATS_INC(link.lenerr);
+    return ERR_BUF;
+  }
+
+  /* assume unresolved Ethernet address */
+  dest = NULL;
+  /* Determine on destination hardware address. Broadcasts and multicasts
+   * are special, other IP addresses are looked up in the ARP table. */
+
+  /* broadcast destination IP address? */
+  if (ip_addr_isbroadcast(ipaddr, netif)) {
+    /* broadcast on Ethernet also */
+    dest = (struct eth_addr *)ðbroadcast;
+  /* multicast destination IP address? */
+  } else if (ip_addr_ismulticast(ipaddr)) {
+    /* Hash IP multicast address to MAC address.*/
+    mcastaddr.addr[0] = 0x01;
+    mcastaddr.addr[1] = 0x00;
+    mcastaddr.addr[2] = 0x5e;
+    mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f;
+    mcastaddr.addr[4] = ip4_addr3(ipaddr);
+    mcastaddr.addr[5] = ip4_addr4(ipaddr);
+    /* destination Ethernet address is multicast */
+    dest = &mcastaddr;
+  /* unicast destination IP address? */
+  } else {
+    /* outside local network? */
+    if (!ip_addr_netcmp(ipaddr, &(netif->ip_addr), &(netif->netmask)) &&
+        !ip_addr_islinklocal(ipaddr)) {
+#if LWIP_AUTOIP
+      struct ip_hdr *iphdr = (struct ip_hdr*)((u8_t*)q->payload +
+        sizeof(struct eth_hdr));
+      /* According to RFC 3297, chapter 2.6.2 (Forwarding Rules), a packet with
+         a link-local source address must always be "directly to its destination
+         on the same physical link. The host MUST NOT send the packet to any
+         router for forwarding". */
+      if (!ip_addr_islinklocal(&iphdr->src))
+#endif /* LWIP_AUTOIP */
+      {
+        /* interface has default gateway? */
+        if (!ip_addr_isany(&netif->gw)) {
+          /* send to hardware address of default gateway IP address */
+          ipaddr = &(netif->gw);
+        /* no default gateway available */
+        } else {
+          /* no route to destination error (default gateway missing) */
+          return ERR_RTE;
+        }
+      }
+    }
+#if LWIP_NETIF_HWADDRHINT
+    if (netif->addr_hint != NULL) {
+      /* per-pcb cached entry was given */
+      u8_t etharp_cached_entry = *(netif->addr_hint);
+      if (etharp_cached_entry < ARP_TABLE_SIZE) {
+#endif /* LWIP_NETIF_HWADDRHINT */
+        if ((arp_table[etharp_cached_entry].state == ETHARP_STATE_STABLE) &&
+            (ip_addr_cmp(ipaddr, &arp_table[etharp_cached_entry].ipaddr))) {
+          /* the per-pcb-cached entry is stable and the right one! */
+          ETHARP_STATS_INC(etharp.cachehit);
+          return etharp_send_ip(netif, q, (struct eth_addr*)(netif->hwaddr),
+            &arp_table[etharp_cached_entry].ethaddr);
+        }
+#if LWIP_NETIF_HWADDRHINT
+      }
+    }
+#endif /* LWIP_NETIF_HWADDRHINT */
+    /* queue on destination Ethernet address belonging to ipaddr */
+    return etharp_query(netif, ipaddr, q);
+  }
+
+  /* continuation for multicast/broadcast destinations */
+  /* obtain source Ethernet address of the given interface */
+  /* send packet directly on the link */
+  return etharp_send_ip(netif, q, (struct eth_addr*)(netif->hwaddr), dest);
+}
+
+/**
+ * Send an ARP request for the given IP address and/or queue a packet.
+ *
+ * If the IP address was not yet in the cache, a pending ARP cache entry
+ * is added and an ARP request is sent for the given address. The packet
+ * is queued on this entry.
+ *
+ * If the IP address was already pending in the cache, a new ARP request
+ * is sent for the given address. The packet is queued on this entry.
+ *
+ * If the IP address was already stable in the cache, and a packet is
+ * given, it is directly sent and no ARP request is sent out. 
+ * 
+ * If the IP address was already stable in the cache, and no packet is
+ * given, an ARP request is sent out.
+ * 
+ * @param netif The lwIP network interface on which ipaddr
+ * must be queried for.
+ * @param ipaddr The IP address to be resolved.
+ * @param q If non-NULL, a pbuf that must be delivered to the IP address.
+ * q is not freed by this function.
+ *
+ * @note q must only be ONE packet, not a packet queue!
+ *
+ * @return
+ * - ERR_BUF Could not make room for Ethernet header.
+ * - ERR_MEM Hardware address unknown, and no more ARP entries available
+ *   to query for address or queue the packet.
+ * - ERR_MEM Could not queue packet due to memory shortage.
+ * - ERR_RTE No route to destination (no gateway to external networks).
+ * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
+ *
+ */
+err_t
+etharp_query(struct netif *netif, ip_addr_t *ipaddr, struct pbuf *q)
+{
+  struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr;
+  err_t result = ERR_MEM;
+  s8_t i; /* ARP entry index */
+
+  /* non-unicast address? */
+  if (ip_addr_isbroadcast(ipaddr, netif) ||
+      ip_addr_ismulticast(ipaddr) ||
+      ip_addr_isany(ipaddr)) {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n"));
+    return ERR_ARG;
+  }
+
+  /* find entry in ARP cache, ask to create entry if queueing packet */
+  i = find_entry(ipaddr, ETHARP_FLAG_TRY_HARD);
+
+  /* could not find or create entry? */
+  if (i < 0) {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not create ARP entry\n"));
+    if (q) {
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: packet dropped\n"));
+      ETHARP_STATS_INC(etharp.memerr);
+    }
+    return (err_t)i;
+  }
+
+  /* mark a fresh entry as pending (we just sent a request) */
+  if (arp_table[i].state == ETHARP_STATE_EMPTY) {
+    arp_table[i].state = ETHARP_STATE_PENDING;
+  }
+
+  /* { i is either a STABLE or (new or existing) PENDING entry } */
+  LWIP_ASSERT("arp_table[i].state == PENDING or STABLE",
+  ((arp_table[i].state == ETHARP_STATE_PENDING) ||
+   (arp_table[i].state == ETHARP_STATE_STABLE)));
+
+  /* do we have a pending entry? or an implicit query request? */
+  if ((arp_table[i].state == ETHARP_STATE_PENDING) || (q == NULL)) {
+    /* try to resolve it; send out ARP request */
+    result = etharp_request(netif, ipaddr);
+    if (result != ERR_OK) {
+      /* ARP request couldn't be sent */
+      /* We don't re-send arp request in etharp_tmr, but we still queue packets,
+         since this failure could be temporary, and the next packet calling
+         etharp_query again could lead to sending the queued packets. */
+    }
+    if (q == NULL) {
+      return result;
+    }
+  }
+
+  /* packet given? */
+  LWIP_ASSERT("q != NULL", q != NULL);
+  /* stable entry? */
+  if (arp_table[i].state == ETHARP_STATE_STABLE) {
+    /* we have a valid IP->Ethernet address mapping */
+    ETHARP_SET_HINT(netif, i);
+    /* send the packet */
+    result = etharp_send_ip(netif, q, srcaddr, &(arp_table[i].ethaddr));
+  /* pending entry? (either just created or already pending */
+  } else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+    /* entry is still pending, queue the given packet 'q' */
+    struct pbuf *p;
+    int copy_needed = 0;
+    /* IF q includes a PBUF_REF, PBUF_POOL or PBUF_RAM, we have no choice but
+     * to copy the whole queue into a new PBUF_RAM (see bug #11400) 
+     * PBUF_ROMs can be left as they are, since ROM must not get changed. */
+    p = q;
+    while (p) {
+      LWIP_ASSERT("no packet queues allowed!", (p->len != p->tot_len) || (p->next == 0));
+      if(p->type != PBUF_ROM) {
+        copy_needed = 1;
+        break;
+      }
+      p = p->next;
+    }
+    if(copy_needed) {
+      /* copy the whole packet into new pbufs */
+      p = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
+      if(p != NULL) {
+        if (pbuf_copy(p, q) != ERR_OK) {
+          pbuf_free(p);
+          p = NULL;
+        }
+      }
+    } else {
+      /* referencing the old pbuf is enough */
+      p = q;
+      pbuf_ref(p);
+    }
+    /* packet could be taken over? */
+    if (p != NULL) {
+      /* queue packet ... */
+#if ARP_QUEUEING
+      struct etharp_q_entry *new_entry;
+      /* allocate a new arp queue entry */
+      new_entry = (struct etharp_q_entry *)memp_malloc(MEMP_ARP_QUEUE);
+      if (new_entry != NULL) {
+        new_entry->next = 0;
+        new_entry->p = p;
+        if(arp_table[i].q != NULL) {
+          /* queue was already existent, append the new entry to the end */
+          struct etharp_q_entry *r;
+          r = arp_table[i].q;
+          while (r->next != NULL) {
+            r = r->next;
+          }
+          r->next = new_entry;
+        } else {
+          /* queue did not exist, first item in queue */
+          arp_table[i].q = new_entry;
+        }
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"S16_F"\n", (void *)q, (s16_t)i));
+        result = ERR_OK;
+      } else {
+        /* the pool MEMP_ARP_QUEUE is empty */
+        pbuf_free(p);
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
+        result = ERR_MEM;
+      }
+#else /* ARP_QUEUEING */
+      /* always queue one packet per ARP request only, freeing a previously queued packet */
+      if (arp_table[i].q != NULL) {
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: dropped previously queued packet %p for ARP entry %"S16_F"\n", (void *)q, (s16_t)i));
+        pbuf_free(arp_table[i].q);
+      }
+      arp_table[i].q = p;
+      result = ERR_OK;
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"S16_F"\n", (void *)q, (s16_t)i));
+#endif /* ARP_QUEUEING */
+    } else {
+      ETHARP_STATS_INC(etharp.memerr);
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
+      result = ERR_MEM;
+    }
+  }
+  return result;
+}
+
+/**
+ * Send a raw ARP packet (opcode and all addresses can be modified)
+ *
+ * @param netif the lwip network interface on which to send the ARP packet
+ * @param ethsrc_addr the source MAC address for the ethernet header
+ * @param ethdst_addr the destination MAC address for the ethernet header
+ * @param hwsrc_addr the source MAC address for the ARP protocol header
+ * @param ipsrc_addr the source IP address for the ARP protocol header
+ * @param hwdst_addr the destination MAC address for the ARP protocol header
+ * @param ipdst_addr the destination IP address for the ARP protocol header
+ * @param opcode the type of the ARP packet
+ * @return ERR_OK if the ARP packet has been sent
+ *         ERR_MEM if the ARP packet couldn't be allocated
+ *         any other err_t on failure
+ */
+#if !LWIP_AUTOIP
+static
+#endif /* LWIP_AUTOIP */
+err_t
+etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr,
+           const struct eth_addr *ethdst_addr,
+           const struct eth_addr *hwsrc_addr, const ip_addr_t *ipsrc_addr,
+           const struct eth_addr *hwdst_addr, const ip_addr_t *ipdst_addr,
+           const u16_t opcode)
+{
+  struct pbuf *p;
+  err_t result = ERR_OK;
+  struct eth_hdr *ethhdr;
+  struct etharp_hdr *hdr;
+#if LWIP_AUTOIP
+  const u8_t * ethdst_hwaddr;
+#endif /* LWIP_AUTOIP */
+
+  /* allocate a pbuf for the outgoing ARP request packet */
+  p = pbuf_alloc(PBUF_RAW, SIZEOF_ETHARP_PACKET, PBUF_RAM);
+  /* could allocate a pbuf for an ARP request? */
+  if (p == NULL) {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
+      ("etharp_raw: could not allocate pbuf for ARP request.\n"));
+    ETHARP_STATS_INC(etharp.memerr);
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("check that first pbuf can hold struct etharp_hdr",
+              (p->len >= SIZEOF_ETHARP_PACKET));
+
+  ethhdr = (struct eth_hdr *)p->payload;
+  hdr = (struct etharp_hdr *)((u8_t*)ethhdr + SIZEOF_ETH_HDR);
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_raw: sending raw ARP packet.\n"));
+  hdr->opcode = htons(opcode);
+
+  LWIP_ASSERT("netif->hwaddr_len must be the same as ETHARP_HWADDR_LEN for etharp!",
+              (netif->hwaddr_len == ETHARP_HWADDR_LEN));
+#if LWIP_AUTOIP
+  /* If we are using Link-Local, all ARP packets that contain a Link-Local
+   * 'sender IP address' MUST be sent using link-layer broadcast instead of
+   * link-layer unicast. (See RFC3927 Section 2.5, last paragraph) */
+  ethdst_hwaddr = ip_addr_islinklocal(ipsrc_addr) ? (u8_t*)(ethbroadcast.addr) : ethdst_addr->addr;
+#endif /* LWIP_AUTOIP */
+  /* Write the ARP MAC-Addresses */
+  ETHADDR16_COPY(&hdr->shwaddr, hwsrc_addr);
+  ETHADDR16_COPY(&hdr->dhwaddr, hwdst_addr);
+  /* Write the Ethernet MAC-Addresses */
+#if LWIP_AUTOIP
+  ETHADDR16_COPY(ðhdr->dest, ethdst_hwaddr);
+#else  /* LWIP_AUTOIP */
+  ETHADDR16_COPY(ðhdr->dest, ethdst_addr);
+#endif /* LWIP_AUTOIP */
+  ETHADDR16_COPY(ðhdr->src, ethsrc_addr);
+  /* Copy struct ip_addr2 to aligned ip_addr, to support compilers without
+   * structure packing. */ 
+  IPADDR2_COPY(&hdr->sipaddr, ipsrc_addr);
+  IPADDR2_COPY(&hdr->dipaddr, ipdst_addr);
+
+  hdr->hwtype = PP_HTONS(HWTYPE_ETHERNET);
+  hdr->proto = PP_HTONS(ETHTYPE_IP);
+  /* set hwlen and protolen */
+  hdr->hwlen = ETHARP_HWADDR_LEN;
+  hdr->protolen = sizeof(ip_addr_t);
+
+  ethhdr->type = PP_HTONS(ETHTYPE_ARP);
+  /* send ARP query */
+  result = netif->linkoutput(netif, p);
+  ETHARP_STATS_INC(etharp.xmit);
+  /* free ARP query packet */
+  pbuf_free(p);
+  p = NULL;
+  /* could not allocate pbuf for ARP request */
+
+  return result;
+}
+
+/**
+ * Send an ARP request packet asking for ipaddr.
+ *
+ * @param netif the lwip network interface on which to send the request
+ * @param ipaddr the IP address for which to ask
+ * @return ERR_OK if the request has been sent
+ *         ERR_MEM if the ARP packet couldn't be allocated
+ *         any other err_t on failure
+ */
+err_t
+etharp_request(struct netif *netif, ip_addr_t *ipaddr)
+{
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_request: sending ARP request.\n"));
+  return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, ðbroadcast,
+                    (struct eth_addr *)netif->hwaddr, &netif->ip_addr, ðzero,
+                    ipaddr, ARP_REQUEST);
+}
+#endif /* LWIP_ARP */
+
+/**
+ * Process received ethernet frames. Using this function instead of directly
+ * calling ip_input and passing ARP frames through etharp in ethernetif_input,
+ * the ARP cache is protected from concurrent access.
+ *
+ * @param p the recevied packet, p->payload pointing to the ethernet header
+ * @param netif the network interface on which the packet was received
+ */
+err_t
+ethernet_input(struct pbuf *p, struct netif *netif)
+{
+  struct eth_hdr* ethhdr;
+  u16_t type;
+  s16_t ip_hdr_offset = SIZEOF_ETH_HDR;
+
+  if (p->len <= SIZEOF_ETH_HDR) {
+    /* a packet with only an ethernet header (or less) is not valid for us */
+    ETHARP_STATS_INC(etharp.proterr);
+    ETHARP_STATS_INC(etharp.drop);
+    goto free_and_return;
+  }
+
+  /* points to packet payload, which starts with an Ethernet header */
+  ethhdr = (struct eth_hdr *)p->payload;
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE,
+    ("ethernet_input: dest:%"X8_F":%"X8_F":%"X8_F":%"X8_F":%"X8_F":%"X8_F", src:%"X8_F":%"X8_F":%"X8_F":%"X8_F":%"X8_F":%"X8_F", type:%"X16_F"\n",
+     (unsigned)ethhdr->dest.addr[0], (unsigned)ethhdr->dest.addr[1], (unsigned)ethhdr->dest.addr[2],
+     (unsigned)ethhdr->dest.addr[3], (unsigned)ethhdr->dest.addr[4], (unsigned)ethhdr->dest.addr[5],
+     (unsigned)ethhdr->src.addr[0], (unsigned)ethhdr->src.addr[1], (unsigned)ethhdr->src.addr[2],
+     (unsigned)ethhdr->src.addr[3], (unsigned)ethhdr->src.addr[4], (unsigned)ethhdr->src.addr[5],
+     (unsigned)htons(ethhdr->type)));
+
+  type = ethhdr->type;
+#if ETHARP_SUPPORT_VLAN
+  if (type == PP_HTONS(ETHTYPE_VLAN)) {
+    struct eth_vlan_hdr *vlan = (struct eth_vlan_hdr*)(((char*)ethhdr) + SIZEOF_ETH_HDR);
+    if (p->len <= SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR) {
+      /* a packet with only an ethernet/vlan header (or less) is not valid for us */
+      ETHARP_STATS_INC(etharp.proterr);
+      ETHARP_STATS_INC(etharp.drop);
+      goto free_and_return;
+    }
+#ifdef ETHARP_VLAN_CHECK /* if not, allow all VLANs */
+    if (VLAN_ID(vlan) != ETHARP_VLAN_CHECK) {
+      /* silently ignore this packet: not for our VLAN */
+      pbuf_free(p);
+      return ERR_OK;
+    }
+#endif /* ETHARP_VLAN_CHECK */
+    type = vlan->tpid;
+    ip_hdr_offset = SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR;
+  }
+#endif /* ETHARP_SUPPORT_VLAN */
+
+#if LWIP_ARP_FILTER_NETIF
+  netif = LWIP_ARP_FILTER_NETIF_FN(p, netif, htons(type));
+#endif /* LWIP_ARP_FILTER_NETIF*/
+
+  switch (type) {
+#if LWIP_ARP
+    /* IP packet? */
+    case PP_HTONS(ETHTYPE_IP):
+      if (!(netif->flags & NETIF_FLAG_ETHARP)) {
+        goto free_and_return;
+      }
+#if ETHARP_TRUST_IP_MAC
+      /* update ARP table */
+      etharp_ip_input(netif, p);
+#endif /* ETHARP_TRUST_IP_MAC */
+      /* skip Ethernet header */
+      if(pbuf_header(p, -ip_hdr_offset)) {
+        LWIP_ASSERT("Can't move over header in packet", 0);
+        goto free_and_return;
+      } else {
+        /* pass to IP layer */
+        ip_input(p, netif);
+      }
+      break;
+      
+    case PP_HTONS(ETHTYPE_ARP):
+      if (!(netif->flags & NETIF_FLAG_ETHARP)) {
+        goto free_and_return;
+      }
+      /* pass p to ARP module */
+      etharp_arp_input(netif, (struct eth_addr*)(netif->hwaddr), p);
+      break;
+#endif /* LWIP_ARP */
+#if PPPOE_SUPPORT
+    case PP_HTONS(ETHTYPE_PPPOEDISC): /* PPP Over Ethernet Discovery Stage */
+      pppoe_disc_input(netif, p);
+      break;
+
+    case PP_HTONS(ETHTYPE_PPPOE): /* PPP Over Ethernet Session Stage */
+      pppoe_data_input(netif, p);
+      break;
+#endif /* PPPOE_SUPPORT */
+
+    default:
+      ETHARP_STATS_INC(etharp.proterr);
+      ETHARP_STATS_INC(etharp.drop);
+      goto free_and_return;
+  }
+
+  /* This means the pbuf is freed or consumed,
+     so the caller doesn't have to free it again */
+  return ERR_OK;
+
+free_and_return:
+  pbuf_free(p);
+  return ERR_OK;
+}
+#endif /* LWIP_ARP || LWIP_ETHERNET */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ethernetif.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ethernetif.c
new file mode 100644
index 0000000..a5b7d99
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ethernetif.c
@@ -0,0 +1,318 @@
+/**
+ * @file
+ * Ethernet Interface Skeleton
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+/*
+ * This file is a skeleton for developing Ethernet network interface
+ * drivers for lwIP. Add code to the low_level functions and do a
+ * search-and-replace for the word "ethernetif" to replace it with
+ * something that better describes your network interface.
+ */
+
+#include "lwip/opt.h"
+
+#if 0 /* don't build, this is only a skeleton, see previous comment */
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include 
+#include 
+#include "netif/etharp.h"
+#include "netif/ppp_oe.h"
+
+/* Define those to better describe your network interface. */
+#define IFNAME0 'e'
+#define IFNAME1 'n'
+
+/**
+ * Helper struct to hold private data used to operate your ethernet interface.
+ * Keeping the ethernet address of the MAC in this struct is not necessary
+ * as it is already kept in the struct netif.
+ * But this is only an example, anyway...
+ */
+struct ethernetif {
+  struct eth_addr *ethaddr;
+  /* Add whatever per-interface state that is needed here. */
+};
+
+/* Forward declarations. */
+static void  ethernetif_input(struct netif *netif);
+
+/**
+ * In this function, the hardware should be initialized.
+ * Called from ethernetif_init().
+ *
+ * @param netif the already initialized lwip network interface structure
+ *        for this ethernetif
+ */
+static void
+low_level_init(struct netif *netif)
+{
+  struct ethernetif *ethernetif = netif->state;
+  
+  /* set MAC hardware address length */
+  netif->hwaddr_len = ETHARP_HWADDR_LEN;
+
+  /* set MAC hardware address */
+  netif->hwaddr[0] = ;
+  ...
+  netif->hwaddr[5] = ;
+
+  /* maximum transfer unit */
+  netif->mtu = 1500;
+  
+  /* device capabilities */
+  /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
+  netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
+ 
+  /* Do whatever else is needed to initialize interface. */  
+}
+
+/**
+ * This function should do the actual transmission of the packet. The packet is
+ * contained in the pbuf that is passed to the function. This pbuf
+ * might be chained.
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)
+ * @return ERR_OK if the packet could be sent
+ *         an err_t value if the packet couldn't be sent
+ *
+ * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to
+ *       strange results. You might consider waiting for space in the DMA queue
+ *       to become availale since the stack doesn't retry to send a packet
+ *       dropped because of memory failure (except for the TCP timers).
+ */
+
+static err_t
+low_level_output(struct netif *netif, struct pbuf *p)
+{
+  struct ethernetif *ethernetif = netif->state;
+  struct pbuf *q;
+
+  initiate transfer();
+  
+#if ETH_PAD_SIZE
+  pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
+#endif
+
+  for(q = p; q != NULL; q = q->next) {
+    /* Send the data from the pbuf to the interface, one pbuf at a
+       time. The size of the data in each pbuf is kept in the ->len
+       variable. */
+    send data from(q->payload, q->len);
+  }
+
+  signal that packet should be sent();
+
+#if ETH_PAD_SIZE
+  pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
+#endif
+  
+  LINK_STATS_INC(link.xmit);
+
+  return ERR_OK;
+}
+
+/**
+ * Should allocate a pbuf and transfer the bytes of the incoming
+ * packet from the interface into the pbuf.
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ * @return a pbuf filled with the received packet (including MAC header)
+ *         NULL on memory error
+ */
+static struct pbuf *
+low_level_input(struct netif *netif)
+{
+  struct ethernetif *ethernetif = netif->state;
+  struct pbuf *p, *q;
+  u16_t len;
+
+  /* Obtain the size of the packet and put it into the "len"
+     variable. */
+  len = ;
+
+#if ETH_PAD_SIZE
+  len += ETH_PAD_SIZE; /* allow room for Ethernet padding */
+#endif
+
+  /* We allocate a pbuf chain of pbufs from the pool. */
+  p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
+  
+  if (p != NULL) {
+
+#if ETH_PAD_SIZE
+    pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
+#endif
+
+    /* We iterate over the pbuf chain until we have read the entire
+     * packet into the pbuf. */
+    for(q = p; q != NULL; q = q->next) {
+      /* Read enough bytes to fill this pbuf in the chain. The
+       * available data in the pbuf is given by the q->len
+       * variable.
+       * This does not necessarily have to be a memcpy, you can also preallocate
+       * pbufs for a DMA-enabled MAC and after receiving truncate it to the
+       * actually received size. In this case, ensure the tot_len member of the
+       * pbuf is the sum of the chained pbuf len members.
+       */
+      read data into(q->payload, q->len);
+    }
+    acknowledge that packet has been read();
+
+#if ETH_PAD_SIZE
+    pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
+#endif
+
+    LINK_STATS_INC(link.recv);
+  } else {
+    drop packet();
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.drop);
+  }
+
+  return p;  
+}
+
+/**
+ * This function should be called when a packet is ready to be read
+ * from the interface. It uses the function low_level_input() that
+ * should handle the actual reception of bytes from the network
+ * interface. Then the type of the received packet is determined and
+ * the appropriate input function is called.
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ */
+static void
+ethernetif_input(struct netif *netif)
+{
+  struct ethernetif *ethernetif;
+  struct eth_hdr *ethhdr;
+  struct pbuf *p;
+
+  ethernetif = netif->state;
+
+  /* move received packet into a new pbuf */
+  p = low_level_input(netif);
+  /* no packet could be read, silently ignore this */
+  if (p == NULL) return;
+  /* points to packet payload, which starts with an Ethernet header */
+  ethhdr = p->payload;
+
+  switch (htons(ethhdr->type)) {
+  /* IP or ARP packet? */
+  case ETHTYPE_IP:
+  case ETHTYPE_ARP:
+#if PPPOE_SUPPORT
+  /* PPPoE packet? */
+  case ETHTYPE_PPPOEDISC:
+  case ETHTYPE_PPPOE:
+#endif /* PPPOE_SUPPORT */
+    /* full packet send to tcpip_thread to process */
+    if (netif->input(p, netif)!=ERR_OK)
+     { LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n"));
+       pbuf_free(p);
+       p = NULL;
+     }
+    break;
+
+  default:
+    pbuf_free(p);
+    p = NULL;
+    break;
+  }
+}
+
+/**
+ * Should be called at the beginning of the program to set up the
+ * network interface. It calls the function low_level_init() to do the
+ * actual setup of the hardware.
+ *
+ * This function should be passed as a parameter to netif_add().
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ * @return ERR_OK if the loopif is initialized
+ *         ERR_MEM if private data couldn't be allocated
+ *         any other err_t on error
+ */
+err_t
+ethernetif_init(struct netif *netif)
+{
+  struct ethernetif *ethernetif;
+
+  LWIP_ASSERT("netif != NULL", (netif != NULL));
+    
+  ethernetif = mem_malloc(sizeof(struct ethernetif));
+  if (ethernetif == NULL) {
+    LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n"));
+    return ERR_MEM;
+  }
+
+#if LWIP_NETIF_HOSTNAME
+  /* Initialize interface hostname */
+  netif->hostname = "lwip";
+#endif /* LWIP_NETIF_HOSTNAME */
+
+  /*
+   * Initialize the snmp variables and counters inside the struct netif.
+   * The last argument should be replaced with your link speed, in units
+   * of bits per second.
+   */
+  NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, LINK_SPEED_OF_YOUR_NETIF_IN_BPS);
+
+  netif->state = ethernetif;
+  netif->name[0] = IFNAME0;
+  netif->name[1] = IFNAME1;
+  /* We directly use etharp_output() here to save a function call.
+   * You can instead declare your own function an call etharp_output()
+   * from it if you have to do some checks before sending (e.g. if link
+   * is available...) */
+  netif->output = etharp_output;
+  netif->linkoutput = low_level_output;
+  
+  ethernetif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]);
+  
+  /* initialize the hardware */
+  low_level_init(netif);
+
+  return ERR_OK;
+}
+
+#endif /* 0 */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/auth.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/auth.c
new file mode 100644
index 0000000..c3c49d2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/auth.c
@@ -0,0 +1,1334 @@
+/*****************************************************************************
+* auth.c - Network Authentication and Phase Control program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 by Global Election Systems Inc.  All rights reserved.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-08 Guy Lancaster , Global Election Systems Inc.
+*   Ported from public pppd code.
+*****************************************************************************/
+/*
+ * auth.c - PPP authentication and phase control.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University.  The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "fsm.h"
+#include "lcp.h"
+#include "pap.h"
+#include "chap.h"
+#include "auth.h"
+#include "ipcp.h"
+
+#if CBCP_SUPPORT
+#include "cbcp.h"
+#endif /* CBCP_SUPPORT */
+
+#include "lwip/inet.h"
+
+#include 
+
+#if 0 /* UNUSED */
+/* Bits in scan_authfile return value */
+#define NONWILD_SERVER  1
+#define NONWILD_CLIENT  2
+
+#define ISWILD(word)  (word[0] == '*' && word[1] == 0)
+#endif /* UNUSED */
+
+#if PAP_SUPPORT || CHAP_SUPPORT
+/* The name by which the peer authenticated itself to us. */
+static char peer_authname[MAXNAMELEN];
+#endif /* PAP_SUPPORT || CHAP_SUPPORT */
+
+/* Records which authentication operations haven't completed yet. */
+static int auth_pending[NUM_PPP];
+
+/* Set if we have successfully called plogin() */
+static int logged_in;
+
+/* Set if we have run the /etc/ppp/auth-up script. */
+static int did_authup; /* @todo, we don't need this in lwip*/
+
+/* List of addresses which the peer may use. */
+static struct wordlist *addresses[NUM_PPP];
+
+#if 0 /* UNUSED */
+/* Wordlist giving addresses which the peer may use
+   without authenticating itself. */
+static struct wordlist *noauth_addrs;
+
+/* Extra options to apply, from the secrets file entry for the peer. */
+static struct wordlist *extra_options;
+#endif /* UNUSED */
+
+/* Number of network protocols which we have opened. */
+static int num_np_open;
+
+/* Number of network protocols which have come up. */
+static int num_np_up;
+
+#if PAP_SUPPORT || CHAP_SUPPORT
+/* Set if we got the contents of passwd[] from the pap-secrets file. */
+static int passwd_from_file;
+#endif /* PAP_SUPPORT || CHAP_SUPPORT */
+
+#if 0 /* UNUSED */
+/* Set if we require authentication only because we have a default route. */
+static bool default_auth;
+
+/* Hook to enable a plugin to control the idle time limit */
+int (*idle_time_hook) __P((struct ppp_idle *)) = NULL;
+
+/* Hook for a plugin to say whether we can possibly authenticate any peer */
+int (*pap_check_hook) __P((void)) = NULL;
+
+/* Hook for a plugin to check the PAP user and password */
+int (*pap_auth_hook) __P((char *user, char *passwd, char **msgp,
+        struct wordlist **paddrs,
+        struct wordlist **popts)) = NULL;
+
+/* Hook for a plugin to know about the PAP user logout */
+void (*pap_logout_hook) __P((void)) = NULL;
+
+/* Hook for a plugin to get the PAP password for authenticating us */
+int (*pap_passwd_hook) __P((char *user, char *passwd)) = NULL;
+
+/*
+ * This is used to ensure that we don't start an auth-up/down
+ * script while one is already running.
+ */
+enum script_state {
+    s_down,
+    s_up
+};
+
+static enum script_state auth_state = s_down;
+static enum script_state auth_script_state = s_down;
+static pid_t auth_script_pid = 0;
+
+/*
+ * Option variables.
+ * lwip: some of these are present in the ppp_settings structure
+ */
+bool uselogin = 0;            /* Use /etc/passwd for checking PAP */
+bool cryptpap = 0;            /* Passwords in pap-secrets are encrypted */
+bool refuse_pap = 0;          /* Don't wanna auth. ourselves with PAP */
+bool refuse_chap = 0;         /* Don't wanna auth. ourselves with CHAP */
+bool usehostname = 0;         /* Use hostname for our_name */
+bool auth_required = 0;       /* Always require authentication from peer */
+bool allow_any_ip = 0;        /* Allow peer to use any IP address */
+bool explicit_remote = 0;     /* User specified explicit remote name */
+char remote_name[MAXNAMELEN]; /* Peer's name for authentication */
+
+#endif /* UNUSED */
+
+/* Bits in auth_pending[] */
+#define PAP_WITHPEER    1
+#define PAP_PEER        2
+#define CHAP_WITHPEER   4
+#define CHAP_PEER       8
+
+/* @todo, move this somewhere */
+/* Used for storing a sequence of words.  Usually malloced. */
+struct wordlist {
+  struct wordlist *next;
+  char        word[1];
+};
+
+
+extern char *crypt (const char *, const char *);
+
+/* Prototypes for procedures local to this file. */
+
+static void network_phase (int);
+static void check_idle (void *);
+static void connect_time_expired (void *);
+#if 0
+static int  plogin (char *, char *, char **, int *);
+#endif
+static void plogout (void);
+static int  null_login (int);
+static int  get_pap_passwd (int, char *, char *);
+static int  have_pap_secret (void);
+static int  have_chap_secret (char *, char *, u32_t);
+static int  ip_addr_check (u32_t, struct wordlist *);
+
+#if 0 /* PAP_SUPPORT || CHAP_SUPPORT */
+static int  scan_authfile (FILE *, char *, char *, char *,
+             struct wordlist **, struct wordlist **,
+             char *);
+static void free_wordlist (struct wordlist *);
+static void auth_script (char *);
+static void auth_script_done (void *);
+static void set_allowed_addrs (int unit, struct wordlist *addrs);
+static int  some_ip_ok (struct wordlist *);
+static int  setupapfile (char **);
+static int  privgroup (char **);
+static int  set_noauth_addr (char **);
+static void check_access (FILE *, char *);
+#endif /* 0 */ /* PAP_SUPPORT || CHAP_SUPPORT */
+
+#if 0 /* UNUSED */
+/*
+ * Authentication-related options.
+ */
+option_t auth_options[] = {
+    { "require-pap", o_bool, &lcp_wantoptions[0].neg_upap,
+      "Require PAP authentication from peer", 1, &auth_required },
+    { "+pap", o_bool, &lcp_wantoptions[0].neg_upap,
+      "Require PAP authentication from peer", 1, &auth_required },
+    { "refuse-pap", o_bool, &refuse_pap,
+      "Don't agree to auth to peer with PAP", 1 },
+    { "-pap", o_bool, &refuse_pap,
+      "Don't allow PAP authentication with peer", 1 },
+    { "require-chap", o_bool, &lcp_wantoptions[0].neg_chap,
+      "Require CHAP authentication from peer", 1, &auth_required },
+    { "+chap", o_bool, &lcp_wantoptions[0].neg_chap,
+      "Require CHAP authentication from peer", 1, &auth_required },
+    { "refuse-chap", o_bool, &refuse_chap,
+      "Don't agree to auth to peer with CHAP", 1 },
+    { "-chap", o_bool, &refuse_chap,
+      "Don't allow CHAP authentication with peer", 1 },
+    { "name", o_string, our_name,
+      "Set local name for authentication",
+      OPT_PRIV|OPT_STATIC, NULL, MAXNAMELEN },
+    { "user", o_string, user,
+      "Set name for auth with peer", OPT_STATIC, NULL, MAXNAMELEN },
+    { "usehostname", o_bool, &usehostname,
+      "Must use hostname for authentication", 1 },
+    { "remotename", o_string, remote_name,
+      "Set remote name for authentication", OPT_STATIC,
+      &explicit_remote, MAXNAMELEN },
+    { "auth", o_bool, &auth_required,
+      "Require authentication from peer", 1 },
+    { "noauth", o_bool, &auth_required,
+      "Don't require peer to authenticate", OPT_PRIV, &allow_any_ip },
+    {  "login", o_bool, &uselogin,
+      "Use system password database for PAP", 1 },
+    { "papcrypt", o_bool, &cryptpap,
+      "PAP passwords are encrypted", 1 },
+    { "+ua", o_special, (void *)setupapfile,
+      "Get PAP user and password from file" },
+    { "password", o_string, passwd,
+      "Password for authenticating us to the peer", OPT_STATIC,
+      NULL, MAXSECRETLEN },
+    { "privgroup", o_special, (void *)privgroup,
+      "Allow group members to use privileged options", OPT_PRIV },
+    { "allow-ip", o_special, (void *)set_noauth_addr,
+      "Set IP address(es) which can be used without authentication",
+      OPT_PRIV },
+    { NULL }
+};
+#endif /* UNUSED */
+#if 0 /* UNUSED */
+/*
+ * setupapfile - specifies UPAP info for authenticating with peer.
+ */
+static int
+setupapfile(char **argv)
+{
+    FILE * ufile;
+    int l;
+
+    lcp_allowoptions[0].neg_upap = 1;
+
+    /* open user info file */
+    seteuid(getuid());
+    ufile = fopen(*argv, "r");
+    seteuid(0);
+    if (ufile == NULL) {
+      option_error("unable to open user login data file %s", *argv);
+      return 0;
+    }
+    check_access(ufile, *argv);
+
+    /* get username */
+    if (fgets(user, MAXNAMELEN - 1, ufile) == NULL
+        || fgets(passwd, MAXSECRETLEN - 1, ufile) == NULL){
+      option_error("unable to read user login data file %s", *argv);
+      return 0;
+    }
+    fclose(ufile);
+
+    /* get rid of newlines */
+    l = strlen(user);
+    if (l > 0 && user[l-1] == '\n')
+      user[l-1] = 0;
+    l = strlen(passwd);
+    if (l > 0 && passwd[l-1] == '\n')
+      passwd[l-1] = 0;
+
+    return (1);
+}
+#endif /* UNUSED */
+
+#if 0 /* UNUSED */
+/*
+ * privgroup - allow members of the group to have privileged access.
+ */
+static int
+privgroup(char **argv)
+{
+    struct group *g;
+    int i;
+
+    g = getgrnam(*argv);
+    if (g == 0) {
+      option_error("group %s is unknown", *argv);
+      return 0;
+    }
+    for (i = 0; i < ngroups; ++i) {
+      if (groups[i] == g->gr_gid) {
+        privileged = 1;
+        break;
+      }
+    }
+    return 1;
+}
+#endif
+
+#if 0 /* UNUSED */
+/*
+ * set_noauth_addr - set address(es) that can be used without authentication.
+ * Equivalent to specifying an entry like `"" * "" addr' in pap-secrets.
+ */
+static int
+set_noauth_addr(char **argv)
+{
+    char *addr = *argv;
+    int l = strlen(addr);
+    struct wordlist *wp;
+
+    wp = (struct wordlist *) malloc(sizeof(struct wordlist) + l + 1);
+    if (wp == NULL)
+      novm("allow-ip argument");
+    wp->word = (char *) (wp + 1);
+    wp->next = noauth_addrs;
+    BCOPY(addr, wp->word, l);
+    noauth_addrs = wp;
+    return 1;
+}
+#endif /* UNUSED */
+
+/*
+ * An Open on LCP has requested a change from Dead to Establish phase.
+ * Do what's necessary to bring the physical layer up.
+ */
+void
+link_required(int unit)
+{
+  LWIP_UNUSED_ARG(unit);
+
+  AUTHDEBUG(LOG_INFO, ("link_required: %d\n", unit));
+}
+
+/*
+ * LCP has terminated the link; go to the Dead phase and take the
+ * physical layer down.
+ */
+void
+link_terminated(int unit)
+{
+  AUTHDEBUG(LOG_INFO, ("link_terminated: %d\n", unit));
+  if (lcp_phase[unit] == PHASE_DEAD) {
+    return;
+  }
+  if (logged_in) {
+    plogout();
+  }
+  lcp_phase[unit] = PHASE_DEAD;
+  AUTHDEBUG(LOG_NOTICE, ("Connection terminated.\n"));
+  pppLinkTerminated(unit);
+}
+
+/*
+ * LCP has gone down; it will either die or try to re-establish.
+ */
+void
+link_down(int unit)
+{
+  int i;
+  struct protent *protp;
+
+  AUTHDEBUG(LOG_INFO, ("link_down: %d\n", unit));
+
+  if (did_authup) {
+    /* XXX Do link down processing. */
+    did_authup = 0;
+  }
+  for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+    if (!protp->enabled_flag) {
+      continue;
+    }
+    if (protp->protocol != PPP_LCP && protp->lowerdown != NULL) {
+      (*protp->lowerdown)(unit);
+    }
+    if (protp->protocol < 0xC000 && protp->close != NULL) {
+      (*protp->close)(unit, "LCP down");
+    }
+  }
+  num_np_open = 0;  /* number of network protocols we have opened */
+  num_np_up = 0;    /* Number of network protocols which have come up */
+
+  if (lcp_phase[unit] != PHASE_DEAD) {
+    lcp_phase[unit] = PHASE_TERMINATE;
+  }
+  pppLinkDown(unit);
+}
+
+/*
+ * The link is established.
+ * Proceed to the Dead, Authenticate or Network phase as appropriate.
+ */
+void
+link_established(int unit)
+{
+  int auth;
+  int i;
+  struct protent *protp;
+  lcp_options *wo = &lcp_wantoptions[unit];
+  lcp_options *go = &lcp_gotoptions[unit];
+#if PAP_SUPPORT || CHAP_SUPPORT
+  lcp_options *ho = &lcp_hisoptions[unit];
+#endif /* PAP_SUPPORT || CHAP_SUPPORT */
+
+  AUTHDEBUG(LOG_INFO, ("link_established: unit %d; Lowering up all protocols...\n", unit));
+  /*
+   * Tell higher-level protocols that LCP is up.
+   */
+  for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+    if (protp->protocol != PPP_LCP && protp->enabled_flag && protp->lowerup != NULL) {
+      (*protp->lowerup)(unit);
+    }
+  }
+  if (ppp_settings.auth_required && !(go->neg_chap || go->neg_upap)) {
+    /*
+     * We wanted the peer to authenticate itself, and it refused:
+     * treat it as though it authenticated with PAP using a username
+     * of "" and a password of "".  If that's not OK, boot it out.
+     */
+    if (!wo->neg_upap || !null_login(unit)) {
+      AUTHDEBUG(LOG_WARNING, ("peer refused to authenticate\n"));
+      lcp_close(unit, "peer refused to authenticate");
+      return;
+    }
+  }
+
+  lcp_phase[unit] = PHASE_AUTHENTICATE;
+  auth = 0;
+#if CHAP_SUPPORT
+  if (go->neg_chap) {
+    ChapAuthPeer(unit, ppp_settings.our_name, go->chap_mdtype);
+    auth |= CHAP_PEER;
+  } 
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT && CHAP_SUPPORT
+  else
+#endif /* PAP_SUPPORT && CHAP_SUPPORT */
+#if PAP_SUPPORT
+  if (go->neg_upap) {
+    upap_authpeer(unit);
+    auth |= PAP_PEER;
+  }
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+  if (ho->neg_chap) {
+    ChapAuthWithPeer(unit, ppp_settings.user, ho->chap_mdtype);
+    auth |= CHAP_WITHPEER;
+  }
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT && CHAP_SUPPORT
+  else
+#endif /* PAP_SUPPORT && CHAP_SUPPORT */
+#if PAP_SUPPORT
+  if (ho->neg_upap) {
+    if (ppp_settings.passwd[0] == 0) {
+      passwd_from_file = 1;
+      if (!get_pap_passwd(unit, ppp_settings.user, ppp_settings.passwd)) {
+        AUTHDEBUG(LOG_ERR, ("No secret found for PAP login\n"));
+      }
+    }
+    upap_authwithpeer(unit, ppp_settings.user, ppp_settings.passwd);
+    auth |= PAP_WITHPEER;
+  }
+#endif /* PAP_SUPPORT */
+  auth_pending[unit] = auth;
+
+  if (!auth) {
+    network_phase(unit);
+  }
+}
+
+/*
+ * Proceed to the network phase.
+ */
+static void
+network_phase(int unit)
+{
+  int i;
+  struct protent *protp;
+  lcp_options *go = &lcp_gotoptions[unit];
+
+  /*
+   * If the peer had to authenticate, run the auth-up script now.
+   */
+  if ((go->neg_chap || go->neg_upap) && !did_authup) {
+    /* XXX Do setup for peer authentication. */
+    did_authup = 1;
+  }
+
+#if CBCP_SUPPORT
+  /*
+   * If we negotiated callback, do it now.
+   */
+  if (go->neg_cbcp) {
+    lcp_phase[unit] = PHASE_CALLBACK;
+    (*cbcp_protent.open)(unit);
+    return;
+  }
+#endif /* CBCP_SUPPORT */
+
+  lcp_phase[unit] = PHASE_NETWORK;
+  for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+    if (protp->protocol < 0xC000 && protp->enabled_flag && protp->open != NULL) {
+      (*protp->open)(unit);
+      if (protp->protocol != PPP_CCP) {
+        ++num_np_open;
+      }
+    }
+  }
+
+  if (num_np_open == 0) {
+    /* nothing to do */
+    lcp_close(0, "No network protocols running");
+  }
+}
+/* @todo: add void start_networks(void) here (pppd 2.3.11) */
+
+/*
+ * The peer has failed to authenticate himself using `protocol'.
+ */
+void
+auth_peer_fail(int unit, u16_t protocol)
+{
+  LWIP_UNUSED_ARG(protocol);
+
+  AUTHDEBUG(LOG_INFO, ("auth_peer_fail: %d proto=%X\n", unit, protocol));
+  /*
+   * Authentication failure: take the link down
+   */
+  lcp_close(unit, "Authentication failed");
+}
+
+
+#if PAP_SUPPORT || CHAP_SUPPORT
+/*
+ * The peer has been successfully authenticated using `protocol'.
+ */
+void
+auth_peer_success(int unit, u16_t protocol, char *name, int namelen)
+{
+  int pbit;
+
+  AUTHDEBUG(LOG_INFO, ("auth_peer_success: %d proto=%X\n", unit, protocol));
+  switch (protocol) {
+    case PPP_CHAP:
+      pbit = CHAP_PEER;
+      break;
+    case PPP_PAP:
+      pbit = PAP_PEER;
+      break;
+    default:
+      AUTHDEBUG(LOG_WARNING, ("auth_peer_success: unknown protocol %x\n", protocol));
+      return;
+  }
+
+  /*
+   * Save the authenticated name of the peer for later.
+   */
+  if (namelen > (int)sizeof(peer_authname) - 1) {
+    namelen = sizeof(peer_authname) - 1;
+  }
+  BCOPY(name, peer_authname, namelen);
+  peer_authname[namelen] = 0;
+  
+  /*
+   * If there is no more authentication still to be done,
+   * proceed to the network (or callback) phase.
+   */
+  if ((auth_pending[unit] &= ~pbit) == 0) {
+    network_phase(unit);
+  }
+}
+
+/*
+ * We have failed to authenticate ourselves to the peer using `protocol'.
+ */
+void
+auth_withpeer_fail(int unit, u16_t protocol)
+{
+  int errCode = PPPERR_AUTHFAIL;
+
+  LWIP_UNUSED_ARG(protocol);
+
+  AUTHDEBUG(LOG_INFO, ("auth_withpeer_fail: %d proto=%X\n", unit, protocol));
+  if (passwd_from_file) {
+    BZERO(ppp_settings.passwd, MAXSECRETLEN);
+  }
+
+  /*
+   * We've failed to authenticate ourselves to our peer.
+   * He'll probably take the link down, and there's not much
+   * we can do except wait for that.
+   */
+  pppIOCtl(unit, PPPCTLS_ERRCODE, &errCode);
+  lcp_close(unit, "Failed to authenticate ourselves to peer");
+}
+
+/*
+ * We have successfully authenticated ourselves with the peer using `protocol'.
+ */
+void
+auth_withpeer_success(int unit, u16_t protocol)
+{
+  int pbit;
+
+  AUTHDEBUG(LOG_INFO, ("auth_withpeer_success: %d proto=%X\n", unit, protocol));
+  switch (protocol) {
+    case PPP_CHAP:
+      pbit = CHAP_WITHPEER;
+      break;
+    case PPP_PAP:
+      if (passwd_from_file) {
+        BZERO(ppp_settings.passwd, MAXSECRETLEN);
+      }
+      pbit = PAP_WITHPEER;
+      break;
+    default:
+      AUTHDEBUG(LOG_WARNING, ("auth_peer_success: unknown protocol %x\n", protocol));
+      pbit = 0;
+  }
+
+  /*
+   * If there is no more authentication still being done,
+   * proceed to the network (or callback) phase.
+   */
+  if ((auth_pending[unit] &= ~pbit) == 0) {
+    network_phase(unit);
+  }
+}
+#endif /* PAP_SUPPORT || CHAP_SUPPORT */
+
+
+/*
+ * np_up - a network protocol has come up.
+ */
+void
+np_up(int unit, u16_t proto)
+{
+  LWIP_UNUSED_ARG(unit);
+  LWIP_UNUSED_ARG(proto);
+
+  AUTHDEBUG(LOG_INFO, ("np_up: %d proto=%X\n", unit, proto));
+  if (num_np_up == 0) {
+    AUTHDEBUG(LOG_INFO, ("np_up: maxconnect=%d idle_time_limit=%d\n",ppp_settings.maxconnect,ppp_settings.idle_time_limit));
+    /*
+     * At this point we consider that the link has come up successfully.
+     */
+    if (ppp_settings.idle_time_limit > 0) {
+      TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit);
+    }
+
+    /*
+     * Set a timeout to close the connection once the maximum
+     * connect time has expired.
+     */
+    if (ppp_settings.maxconnect > 0) {
+      TIMEOUT(connect_time_expired, 0, ppp_settings.maxconnect);
+    }
+  }
+  ++num_np_up;
+}
+
+/*
+ * np_down - a network protocol has gone down.
+ */
+void
+np_down(int unit, u16_t proto)
+{
+  LWIP_UNUSED_ARG(unit);
+  LWIP_UNUSED_ARG(proto);
+
+  AUTHDEBUG(LOG_INFO, ("np_down: %d proto=%X\n", unit, proto));
+  if (--num_np_up == 0 && ppp_settings.idle_time_limit > 0) {
+    UNTIMEOUT(check_idle, NULL);
+  }
+}
+
+/*
+ * np_finished - a network protocol has finished using the link.
+ */
+void
+np_finished(int unit, u16_t proto)
+{
+  LWIP_UNUSED_ARG(unit);
+  LWIP_UNUSED_ARG(proto);
+
+  AUTHDEBUG(LOG_INFO, ("np_finished: %d proto=%X\n", unit, proto));
+  if (--num_np_open <= 0) {
+    /* no further use for the link: shut up shop. */
+    lcp_close(0, "No network protocols running");
+  }
+}
+
+/*
+ * check_idle - check whether the link has been idle for long
+ * enough that we can shut it down.
+ */
+static void
+check_idle(void *arg)
+{
+  struct ppp_idle idle;
+  u_short itime;
+  
+  LWIP_UNUSED_ARG(arg);
+  if (!get_idle_time(0, &idle)) {
+    return;
+  }
+  itime = LWIP_MIN(idle.xmit_idle, idle.recv_idle);
+  if (itime >= ppp_settings.idle_time_limit) {
+    /* link is idle: shut it down. */
+    AUTHDEBUG(LOG_INFO, ("Terminating connection due to lack of activity.\n"));
+    lcp_close(0, "Link inactive");
+  } else {
+    TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit - itime);
+  }
+}
+
+/*
+ * connect_time_expired - log a message and close the connection.
+ */
+static void
+connect_time_expired(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+
+  AUTHDEBUG(LOG_INFO, ("Connect time expired\n"));
+  lcp_close(0, "Connect time expired");   /* Close connection */
+}
+
+#if 0 /* UNUSED */
+/*
+ * auth_check_options - called to check authentication options.
+ */
+void
+auth_check_options(void)
+{
+  lcp_options *wo = &lcp_wantoptions[0];
+  int can_auth;
+  ipcp_options *ipwo = &ipcp_wantoptions[0];
+  u32_t remote;
+
+  /* Default our_name to hostname, and user to our_name */
+  if (ppp_settings.our_name[0] == 0 || ppp_settings.usehostname) {
+      strcpy(ppp_settings.our_name, ppp_settings.hostname);
+  }
+
+  if (ppp_settings.user[0] == 0) {
+    strcpy(ppp_settings.user, ppp_settings.our_name);
+  }
+
+  /* If authentication is required, ask peer for CHAP or PAP. */
+  if (ppp_settings.auth_required && !wo->neg_chap && !wo->neg_upap) {
+    wo->neg_chap = 1;
+    wo->neg_upap = 1;
+  }
+  
+  /*
+   * Check whether we have appropriate secrets to use
+   * to authenticate the peer.
+   */
+  can_auth = wo->neg_upap && have_pap_secret();
+  if (!can_auth && wo->neg_chap) {
+    remote = ipwo->accept_remote? 0: ipwo->hisaddr;
+    can_auth = have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote);
+  }
+
+  if (ppp_settings.auth_required && !can_auth) {
+    ppp_panic("No auth secret");
+  }
+}
+#endif /* UNUSED */
+
+/*
+ * auth_reset - called when LCP is starting negotiations to recheck
+ * authentication options, i.e. whether we have appropriate secrets
+ * to use for authenticating ourselves and/or the peer.
+ */
+void
+auth_reset(int unit)
+{
+  lcp_options *go = &lcp_gotoptions[unit];
+  lcp_options *ao = &lcp_allowoptions[0];
+  ipcp_options *ipwo = &ipcp_wantoptions[0];
+  u32_t remote;
+
+  AUTHDEBUG(LOG_INFO, ("auth_reset: %d\n", unit));
+  ao->neg_upap = !ppp_settings.refuse_pap && (ppp_settings.passwd[0] != 0 || get_pap_passwd(unit, NULL, NULL));
+  ao->neg_chap = !ppp_settings.refuse_chap && ppp_settings.passwd[0] != 0 /*have_chap_secret(ppp_settings.user, ppp_settings.remote_name, (u32_t)0)*/;
+
+  if (go->neg_upap && !have_pap_secret()) {
+    go->neg_upap = 0;
+  }
+  if (go->neg_chap) {
+    remote = ipwo->accept_remote? 0: ipwo->hisaddr;
+    if (!have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote)) {
+      go->neg_chap = 0;
+    }
+  }
+}
+
+#if PAP_SUPPORT
+/*
+ * check_passwd - Check the user name and passwd against the PAP secrets
+ * file.  If requested, also check against the system password database,
+ * and login the user if OK.
+ *
+ * returns:
+ *  UPAP_AUTHNAK: Authentication failed.
+ *  UPAP_AUTHACK: Authentication succeeded.
+ * In either case, msg points to an appropriate message.
+ */
+u_char
+check_passwd( int unit, char *auser, int userlen, char *apasswd, int passwdlen, char **msg, int *msglen)
+{
+#if 1 /* XXX Assume all entries OK. */
+  LWIP_UNUSED_ARG(unit);
+  LWIP_UNUSED_ARG(auser);
+  LWIP_UNUSED_ARG(userlen);
+  LWIP_UNUSED_ARG(apasswd);
+  LWIP_UNUSED_ARG(passwdlen);
+  LWIP_UNUSED_ARG(msglen);
+  *msg = (char *) 0;
+  return UPAP_AUTHACK;     /* XXX Assume all entries OK. */
+#else
+  u_char ret = 0;
+  struct wordlist *addrs = NULL;
+  char passwd[256], user[256];
+  char secret[MAXWORDLEN];
+  static u_short attempts = 0;
+  
+  /*
+   * Make copies of apasswd and auser, then null-terminate them.
+   */
+  BCOPY(apasswd, passwd, passwdlen);
+  passwd[passwdlen] = '\0';
+  BCOPY(auser, user, userlen);
+  user[userlen] = '\0';
+  *msg = (char *) 0;
+
+  /* XXX Validate user name and password. */
+  ret = UPAP_AUTHACK;     /* XXX Assume all entries OK. */
+      
+  if (ret == UPAP_AUTHNAK) {
+    if (*msg == (char *) 0) {
+      *msg = "Login incorrect";
+    }
+    *msglen = strlen(*msg);
+    /*
+     * Frustrate passwd stealer programs.
+     * Allow 10 tries, but start backing off after 3 (stolen from login).
+     * On 10'th, drop the connection.
+     */
+    if (attempts++ >= 10) {
+      AUTHDEBUG(LOG_WARNING, ("%d LOGIN FAILURES BY %s\n", attempts, user));
+      /*ppp_panic("Excess Bad Logins");*/
+    }
+    if (attempts > 3) {
+      /* @todo: this was sleep(), i.e. seconds, not milliseconds
+       * I don't think we really need this in lwIP - we would block tcpip_thread!
+       */
+      /*sys_msleep((attempts - 3) * 5);*/
+    }
+    if (addrs != NULL) {
+      free_wordlist(addrs);
+    }
+  } else {
+    attempts = 0; /* Reset count */
+    if (*msg == (char *) 0) {
+      *msg = "Login ok";
+    }
+    *msglen = strlen(*msg);
+    set_allowed_addrs(unit, addrs);
+  }
+
+  BZERO(passwd, sizeof(passwd));
+  BZERO(secret, sizeof(secret));
+
+  return ret;
+#endif
+}
+#endif /* PAP_SUPPORT */
+
+#if 0 /* UNUSED */
+/*
+ * This function is needed for PAM.
+ */
+
+#ifdef USE_PAM
+
+/* lwip does not support PAM*/
+
+#endif  /* USE_PAM */
+
+#endif /* UNUSED */
+
+
+#if 0 /* UNUSED */
+/*
+ * plogin - Check the user name and password against the system
+ * password database, and login the user if OK.
+ *
+ * returns:
+ *  UPAP_AUTHNAK: Login failed.
+ *  UPAP_AUTHACK: Login succeeded.
+ * In either case, msg points to an appropriate message.
+ */
+static int
+plogin(char *user, char *passwd, char **msg, int *msglen)
+{
+
+  LWIP_UNUSED_ARG(user);
+  LWIP_UNUSED_ARG(passwd);
+  LWIP_UNUSED_ARG(msg);
+  LWIP_UNUSED_ARG(msglen);
+
+
+ /* The new lines are here align the file when 
+  * compared against the pppd 2.3.11 code */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  /* XXX Fail until we decide that we want to support logins. */
+  return (UPAP_AUTHNAK);
+}
+#endif
+
+
+
+/*
+ * plogout - Logout the user.
+ */
+static void
+plogout(void)
+{
+  logged_in = 0;
+}
+
+/*
+ * null_login - Check if a username of "" and a password of "" are
+ * acceptable, and iff so, set the list of acceptable IP addresses
+ * and return 1.
+ */
+static int
+null_login(int unit)
+{
+  LWIP_UNUSED_ARG(unit);
+  /* XXX Fail until we decide that we want to support logins. */
+  return 0;
+}
+
+
+/*
+ * get_pap_passwd - get a password for authenticating ourselves with
+ * our peer using PAP.  Returns 1 on success, 0 if no suitable password
+ * could be found.
+ */
+static int
+get_pap_passwd(int unit, char *user, char *passwd)
+{
+  LWIP_UNUSED_ARG(unit);
+/* normally we would reject PAP if no password is provided,
+   but this causes problems with some providers (like CHT in Taiwan)
+   who incorrectly request PAP and expect a bogus/empty password, so
+   always provide a default user/passwd of "none"/"none"
+
+   @todo: This should be configured by the user, instead of being hardcoded here!
+*/
+  if(user) {
+    strcpy(user, "none");
+  }
+  if(passwd) {
+    strcpy(passwd, "none");
+  }
+  return 1;
+}
+
+/*
+ * have_pap_secret - check whether we have a PAP file with any
+ * secrets that we could possibly use for authenticating the peer.
+ */
+static int
+have_pap_secret(void)
+{
+  /* XXX Fail until we set up our passwords. */
+  return 0;
+}
+
+/*
+ * have_chap_secret - check whether we have a CHAP file with a
+ * secret that we could possibly use for authenticating `client'
+ * on `server'.  Either can be the null string, meaning we don't
+ * know the identity yet.
+ */
+static int
+have_chap_secret(char *client, char *server, u32_t remote)
+{
+  LWIP_UNUSED_ARG(client);
+  LWIP_UNUSED_ARG(server);
+  LWIP_UNUSED_ARG(remote);
+
+  /* XXX Fail until we set up our passwords. */
+  return 0;
+}
+#if CHAP_SUPPORT
+
+/*
+ * get_secret - open the CHAP secret file and return the secret
+ * for authenticating the given client on the given server.
+ * (We could be either client or server).
+ */
+int
+get_secret(int unit, char *client, char *server, char *secret, int *secret_len, int save_addrs)
+{
+#if 1
+  int len;
+  struct wordlist *addrs;
+
+  LWIP_UNUSED_ARG(unit);
+  LWIP_UNUSED_ARG(server);
+  LWIP_UNUSED_ARG(save_addrs);
+
+  addrs = NULL;
+
+  if(!client || !client[0] || strcmp(client, ppp_settings.user)) {
+    return 0;
+  }
+
+  len = (int)strlen(ppp_settings.passwd);
+  if (len > MAXSECRETLEN) {
+    AUTHDEBUG(LOG_ERR, ("Secret for %s on %s is too long\n", client, server));
+    len = MAXSECRETLEN;
+  }
+
+  BCOPY(ppp_settings.passwd, secret, len);
+  *secret_len = len;
+
+  return 1;
+#else
+  int ret = 0, len;
+  struct wordlist *addrs;
+  char secbuf[MAXWORDLEN];
+  
+  addrs = NULL;
+  secbuf[0] = 0;
+
+  /* XXX Find secret. */
+  if (ret < 0) {
+    return 0;
+  }
+
+  if (save_addrs) {
+    set_allowed_addrs(unit, addrs);
+  }
+
+  len = strlen(secbuf);
+  if (len > MAXSECRETLEN) {
+    AUTHDEBUG(LOG_ERR, ("Secret for %s on %s is too long\n", client, server));
+    len = MAXSECRETLEN;
+  }
+
+  BCOPY(secbuf, secret, len);
+  BZERO(secbuf, sizeof(secbuf));
+  *secret_len = len;
+
+  return 1;
+#endif
+}
+#endif /* CHAP_SUPPORT */
+
+
+#if 0 /* PAP_SUPPORT || CHAP_SUPPORT */
+/*
+ * set_allowed_addrs() - set the list of allowed addresses.
+ */
+static void
+set_allowed_addrs(int unit, struct wordlist *addrs)
+{
+  if (addresses[unit] != NULL) {
+    free_wordlist(addresses[unit]);
+  }
+  addresses[unit] = addrs;
+
+#if 0
+  /*
+   * If there's only one authorized address we might as well
+   * ask our peer for that one right away
+   */
+  if (addrs != NULL && addrs->next == NULL) {
+    char *p = addrs->word;
+    struct ipcp_options *wo = &ipcp_wantoptions[unit];
+    u32_t a;
+    struct hostent *hp;
+    
+    if (wo->hisaddr == 0 && *p != '!' && *p != '-' && strchr(p, '/') == NULL) {
+      hp = gethostbyname(p);
+      if (hp != NULL && hp->h_addrtype == AF_INET) {
+        a = *(u32_t *)hp->h_addr;
+      } else {
+        a = inet_addr(p);
+      }
+      if (a != (u32_t) -1) {
+        wo->hisaddr = a;
+      }
+    }
+  }
+#endif
+}
+#endif /* 0 */ /* PAP_SUPPORT || CHAP_SUPPORT */
+
+/*
+ * auth_ip_addr - check whether the peer is authorized to use
+ * a given IP address.  Returns 1 if authorized, 0 otherwise.
+ */
+int
+auth_ip_addr(int unit, u32_t addr)
+{
+  return ip_addr_check(addr, addresses[unit]);
+}
+
+static int /* @todo: integrate this funtion into auth_ip_addr()*/
+ip_addr_check(u32_t addr, struct wordlist *addrs)
+{
+  /* don't allow loopback or multicast address */
+  if (bad_ip_adrs(addr)) {
+    return 0;
+  }
+
+  if (addrs == NULL) {
+    return !ppp_settings.auth_required; /* no addresses authorized */
+  }
+
+  /* XXX All other addresses allowed. */
+  return 1;
+}
+
+/*
+ * bad_ip_adrs - return 1 if the IP address is one we don't want
+ * to use, such as an address in the loopback net or a multicast address.
+ * addr is in network byte order.
+ */
+int
+bad_ip_adrs(u32_t addr)
+{
+  addr = ntohl(addr);
+  return (addr >> IN_CLASSA_NSHIFT) == IN_LOOPBACKNET
+      || IN_MULTICAST(addr) || IN_BADCLASS(addr);
+}
+
+#if 0 /* UNUSED */ /* PAP_SUPPORT || CHAP_SUPPORT */
+/*
+ * some_ip_ok - check a wordlist to see if it authorizes any
+ * IP address(es).
+ */
+static int
+some_ip_ok(struct wordlist *addrs)
+{
+    for (; addrs != 0; addrs = addrs->next) {
+      if (addrs->word[0] == '-')
+        break;
+      if (addrs->word[0] != '!')
+        return 1; /* some IP address is allowed */
+    }
+    return 0;
+}
+
+/*
+ * check_access - complain if a secret file has too-liberal permissions.
+ */
+static void
+check_access(FILE *f, char *filename)
+{
+    struct stat sbuf;
+
+    if (fstat(fileno(f), &sbuf) < 0) {
+      warn("cannot stat secret file %s: %m", filename);
+    } else if ((sbuf.st_mode & (S_IRWXG | S_IRWXO)) != 0) {
+      warn("Warning - secret file %s has world and/or group access",
+            filename);
+    }
+}
+
+
+/*
+ * scan_authfile - Scan an authorization file for a secret suitable
+ * for authenticating `client' on `server'.  The return value is -1
+ * if no secret is found, otherwise >= 0.  The return value has
+ * NONWILD_CLIENT set if the secret didn't have "*" for the client, and
+ * NONWILD_SERVER set if the secret didn't have "*" for the server.
+ * Any following words on the line up to a "--" (i.e. address authorization
+ * info) are placed in a wordlist and returned in *addrs.  Any
+ * following words (extra options) are placed in a wordlist and
+ * returned in *opts.
+ * We assume secret is NULL or points to MAXWORDLEN bytes of space.
+ */
+static int
+scan_authfile(FILE *f, char *client, char *server, char *secret, struct wordlist **addrs, struct wordlist **opts, char *filename)
+{
+  /* We do not (currently) need this in lwip  */
+  return 0; /* dummy */
+}
+/*
+ * free_wordlist - release memory allocated for a wordlist.
+ */
+static void
+free_wordlist(struct wordlist *wp)
+{
+  struct wordlist *next;
+
+  while (wp != NULL) {
+    next = wp->next;
+    free(wp);
+    wp = next;
+  }
+}
+
+/*
+ * auth_script_done - called when the auth-up or auth-down script
+ * has finished.
+ */
+static void
+auth_script_done(void *arg)
+{
+    auth_script_pid = 0;
+    switch (auth_script_state) {
+    case s_up:
+      if (auth_state == s_down) {
+        auth_script_state = s_down;
+        auth_script(_PATH_AUTHDOWN);
+      }
+      break;
+    case s_down:
+      if (auth_state == s_up) {
+        auth_script_state = s_up;
+        auth_script(_PATH_AUTHUP);
+      }
+      break;
+    }
+}
+
+/*
+ * auth_script - execute a script with arguments
+ * interface-name peer-name real-user tty speed
+ */
+static void
+auth_script(char *script)
+{
+    char strspeed[32];
+    struct passwd *pw;
+    char struid[32];
+    char *user_name;
+    char *argv[8];
+
+    if ((pw = getpwuid(getuid())) != NULL && pw->pw_name != NULL)
+      user_name = pw->pw_name;
+    else {
+      slprintf(struid, sizeof(struid), "%d", getuid());
+      user_name = struid;
+    }
+    slprintf(strspeed, sizeof(strspeed), "%d", baud_rate);
+
+    argv[0] = script;
+    argv[1] = ifname;
+    argv[2] = peer_authname;
+    argv[3] = user_name;
+    argv[4] = devnam;
+    argv[5] = strspeed;
+    argv[6] = NULL;
+
+    auth_script_pid = run_program(script, argv, 0, auth_script_done, NULL);
+}
+#endif  /* 0 */ /* PAP_SUPPORT || CHAP_SUPPORT */
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/auth.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/auth.h
new file mode 100644
index 0000000..a8069ec
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/auth.h
@@ -0,0 +1,111 @@
+/*****************************************************************************
+* auth.h -  PPP Authentication and phase control header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD pppd.h.
+*****************************************************************************/
+/*
+ * pppd.h - PPP daemon global declarations.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ */
+
+#ifndef AUTH_H
+#define AUTH_H
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+/* we are starting to use the link */
+void link_required (int);
+
+/* we are finished with the link */
+void link_terminated (int);
+
+/* the LCP layer has left the Opened state */
+void link_down (int);
+
+/* the link is up; authenticate now */
+void link_established (int);
+
+/* a network protocol has come up */
+void np_up (int, u16_t);
+
+/* a network protocol has gone down */
+void np_down (int, u16_t);
+
+/* a network protocol no longer needs link */
+void np_finished (int, u16_t);
+
+/* peer failed to authenticate itself */
+void auth_peer_fail (int, u16_t);
+
+/* peer successfully authenticated itself */
+void auth_peer_success (int, u16_t, char *, int);
+
+/* we failed to authenticate ourselves */
+void auth_withpeer_fail (int, u16_t);
+
+/* we successfully authenticated ourselves */
+void auth_withpeer_success (int, u16_t);
+
+/* check authentication options supplied */
+void auth_check_options (void);
+
+/* check what secrets we have */
+void auth_reset (int);
+
+/* Check peer-supplied username/password */
+u_char check_passwd (int, char *, int, char *, int, char **, int *);
+
+/* get "secret" for chap */
+int  get_secret (int, char *, char *, char *, int *, int);
+
+/* check if IP address is authorized */
+int  auth_ip_addr (int, u32_t);
+
+/* check if IP address is unreasonable */
+int  bad_ip_adrs (u32_t);
+
+#endif /* AUTH_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/chap.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/chap.c
new file mode 100644
index 0000000..3a49ff8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/chap.c
@@ -0,0 +1,908 @@
+/*** WARNING - THIS HAS NEVER BEEN FINISHED ***/
+/*****************************************************************************
+* chap.c - Network Challenge Handshake Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*   Original based on BSD chap.c.
+*****************************************************************************/
+/*
+ * chap.c - Challenge Handshake Authentication Protocol.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University.  The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1991 Gregory M. Christy.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Gregory M. Christy.  The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#if CHAP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "magic.h"
+#include "randm.h"
+#include "auth.h"
+#include "md5.h"
+#include "chap.h"
+#include "chpms.h"
+
+#include 
+
+#if 0 /* UNUSED */
+/*
+ * Command-line options.
+ */
+static option_t chap_option_list[] = {
+    { "chap-restart", o_int, &chap[0].timeouttime,
+      "Set timeout for CHAP" },
+    { "chap-max-challenge", o_int, &chap[0].max_transmits,
+      "Set max #xmits for challenge" },
+    { "chap-interval", o_int, &chap[0].chal_interval,
+      "Set interval for rechallenge" },
+#ifdef MSLANMAN
+    { "ms-lanman", o_bool, &ms_lanman,
+      "Use LanMan passwd when using MS-CHAP", 1 },
+#endif
+    { NULL }
+};
+#endif /* UNUSED */
+
+/*
+ * Protocol entry points.
+ */
+static void ChapInit (int);
+static void ChapLowerUp (int);
+static void ChapLowerDown (int);
+static void ChapInput (int, u_char *, int);
+static void ChapProtocolReject (int);
+#if PPP_ADDITIONAL_CALLBACKS
+static int  ChapPrintPkt (u_char *, int, void (*) (void *, char *, ...), void *);
+#endif
+
+struct protent chap_protent = {
+  PPP_CHAP,
+  ChapInit,
+  ChapInput,
+  ChapProtocolReject,
+  ChapLowerUp,
+  ChapLowerDown,
+  NULL,
+  NULL,
+#if PPP_ADDITIONAL_CALLBACKS
+  ChapPrintPkt,
+  NULL,
+#endif /* PPP_ADDITIONAL_CALLBACKS */
+  1,
+  "CHAP",
+#if PPP_ADDITIONAL_CALLBACKS
+  NULL,
+  NULL,
+  NULL
+#endif /* PPP_ADDITIONAL_CALLBACKS */
+};
+
+chap_state chap[NUM_PPP]; /* CHAP state; one for each unit */
+
+static void ChapChallengeTimeout (void *);
+static void ChapResponseTimeout (void *);
+static void ChapReceiveChallenge (chap_state *, u_char *, u_char, int);
+static void ChapRechallenge (void *);
+static void ChapReceiveResponse (chap_state *, u_char *, int, int);
+static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len);
+static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len);
+static void ChapSendStatus (chap_state *, int);
+static void ChapSendChallenge (chap_state *);
+static void ChapSendResponse (chap_state *);
+static void ChapGenChallenge (chap_state *);
+
+/*
+ * ChapInit - Initialize a CHAP unit.
+ */
+static void
+ChapInit(int unit)
+{
+  chap_state *cstate = &chap[unit];
+
+  BZERO(cstate, sizeof(*cstate));
+  cstate->unit = unit;
+  cstate->clientstate = CHAPCS_INITIAL;
+  cstate->serverstate = CHAPSS_INITIAL;
+  cstate->timeouttime = CHAP_DEFTIMEOUT;
+  cstate->max_transmits = CHAP_DEFTRANSMITS;
+  /* random number generator is initialized in magic_init */
+}
+
+
+/*
+ * ChapAuthWithPeer - Authenticate us with our peer (start client).
+ *
+ */
+void
+ChapAuthWithPeer(int unit, char *our_name, u_char digest)
+{
+  chap_state *cstate = &chap[unit];
+
+  cstate->resp_name = our_name;
+  cstate->resp_type = digest;
+
+  if (cstate->clientstate == CHAPCS_INITIAL ||
+      cstate->clientstate == CHAPCS_PENDING) {
+    /* lower layer isn't up - wait until later */
+    cstate->clientstate = CHAPCS_PENDING;
+    return;
+  }
+
+  /*
+   * We get here as a result of LCP coming up.
+   * So even if CHAP was open before, we will 
+   * have to re-authenticate ourselves.
+   */
+  cstate->clientstate = CHAPCS_LISTEN;
+}
+
+
+/*
+ * ChapAuthPeer - Authenticate our peer (start server).
+ */
+void
+ChapAuthPeer(int unit, char *our_name, u_char digest)
+{
+  chap_state *cstate = &chap[unit];
+
+  cstate->chal_name = our_name;
+  cstate->chal_type = digest;
+  
+  if (cstate->serverstate == CHAPSS_INITIAL ||
+      cstate->serverstate == CHAPSS_PENDING) {
+    /* lower layer isn't up - wait until later */
+    cstate->serverstate = CHAPSS_PENDING;
+    return;
+  }
+
+  ChapGenChallenge(cstate);
+  ChapSendChallenge(cstate);    /* crank it up dude! */
+  cstate->serverstate = CHAPSS_INITIAL_CHAL;
+}
+
+
+/*
+ * ChapChallengeTimeout - Timeout expired on sending challenge.
+ */
+static void
+ChapChallengeTimeout(void *arg)
+{
+  chap_state *cstate = (chap_state *) arg;
+
+  /* if we aren't sending challenges, don't worry.  then again we */
+  /* probably shouldn't be here either */
+  if (cstate->serverstate != CHAPSS_INITIAL_CHAL &&
+      cstate->serverstate != CHAPSS_RECHALLENGE) {
+    return;
+  }
+
+  if (cstate->chal_transmits >= cstate->max_transmits) {
+    /* give up on peer */
+    CHAPDEBUG(LOG_ERR, ("Peer failed to respond to CHAP challenge\n"));
+    cstate->serverstate = CHAPSS_BADAUTH;
+    auth_peer_fail(cstate->unit, PPP_CHAP);
+    return;
+  }
+
+  ChapSendChallenge(cstate); /* Re-send challenge */
+}
+
+
+/*
+ * ChapResponseTimeout - Timeout expired on sending response.
+ */
+static void
+ChapResponseTimeout(void *arg)
+{
+  chap_state *cstate = (chap_state *) arg;
+
+  /* if we aren't sending a response, don't worry. */
+  if (cstate->clientstate != CHAPCS_RESPONSE) {
+    return;
+  }
+
+  ChapSendResponse(cstate);    /* re-send response */
+}
+
+
+/*
+ * ChapRechallenge - Time to challenge the peer again.
+ */
+static void
+ChapRechallenge(void *arg)
+{
+  chap_state *cstate = (chap_state *) arg;
+  
+  /* if we aren't sending a response, don't worry. */
+  if (cstate->serverstate != CHAPSS_OPEN) {
+    return;
+  }
+
+  ChapGenChallenge(cstate);
+  ChapSendChallenge(cstate);
+  cstate->serverstate = CHAPSS_RECHALLENGE;
+}
+
+
+/*
+ * ChapLowerUp - The lower layer is up.
+ *
+ * Start up if we have pending requests.
+ */
+static void
+ChapLowerUp(int unit)
+{
+  chap_state *cstate = &chap[unit];
+
+  if (cstate->clientstate == CHAPCS_INITIAL) {
+    cstate->clientstate = CHAPCS_CLOSED;
+  } else if (cstate->clientstate == CHAPCS_PENDING) {
+    cstate->clientstate = CHAPCS_LISTEN;
+  }
+
+  if (cstate->serverstate == CHAPSS_INITIAL) {
+    cstate->serverstate = CHAPSS_CLOSED;
+  } else if (cstate->serverstate == CHAPSS_PENDING) {
+    ChapGenChallenge(cstate);
+    ChapSendChallenge(cstate);
+    cstate->serverstate = CHAPSS_INITIAL_CHAL;
+  }
+}
+
+
+/*
+ * ChapLowerDown - The lower layer is down.
+ *
+ * Cancel all timeouts.
+ */
+static void
+ChapLowerDown(int unit)
+{
+  chap_state *cstate = &chap[unit];
+
+  /* Timeout(s) pending?  Cancel if so. */
+  if (cstate->serverstate == CHAPSS_INITIAL_CHAL ||
+      cstate->serverstate == CHAPSS_RECHALLENGE) {
+    UNTIMEOUT(ChapChallengeTimeout, cstate);
+  } else if (cstate->serverstate == CHAPSS_OPEN
+      && cstate->chal_interval != 0) {
+    UNTIMEOUT(ChapRechallenge, cstate);
+  }
+  if (cstate->clientstate == CHAPCS_RESPONSE) {
+    UNTIMEOUT(ChapResponseTimeout, cstate);
+  }
+  cstate->clientstate = CHAPCS_INITIAL;
+  cstate->serverstate = CHAPSS_INITIAL;
+}
+
+
+/*
+ * ChapProtocolReject - Peer doesn't grok CHAP.
+ */
+static void
+ChapProtocolReject(int unit)
+{
+  chap_state *cstate = &chap[unit];
+  
+  if (cstate->serverstate != CHAPSS_INITIAL &&
+      cstate->serverstate != CHAPSS_CLOSED) {
+    auth_peer_fail(unit, PPP_CHAP);
+  }
+  if (cstate->clientstate != CHAPCS_INITIAL &&
+      cstate->clientstate != CHAPCS_CLOSED) {
+    auth_withpeer_fail(unit, PPP_CHAP); /* lwip: just sets the PPP error code on this unit to PPPERR_AUTHFAIL */
+  }
+  ChapLowerDown(unit); /* shutdown chap */
+}
+
+
+/*
+ * ChapInput - Input CHAP packet.
+ */
+static void
+ChapInput(int unit, u_char *inpacket, int packet_len)
+{
+  chap_state *cstate = &chap[unit];
+  u_char *inp;
+  u_char code, id;
+  int len;
+  
+  /*
+   * Parse header (code, id and length).
+   * If packet too short, drop it.
+   */
+  inp = inpacket;
+  if (packet_len < CHAP_HEADERLEN) {
+    CHAPDEBUG(LOG_INFO, ("ChapInput: rcvd short header.\n"));
+    return;
+  }
+  GETCHAR(code, inp);
+  GETCHAR(id, inp);
+  GETSHORT(len, inp);
+  if (len < CHAP_HEADERLEN) {
+    CHAPDEBUG(LOG_INFO, ("ChapInput: rcvd illegal length.\n"));
+    return;
+  }
+  if (len > packet_len) {
+    CHAPDEBUG(LOG_INFO, ("ChapInput: rcvd short packet.\n"));
+    return;
+  }
+  len -= CHAP_HEADERLEN;
+  
+  /*
+   * Action depends on code (as in fact it usually does :-).
+   */
+  switch (code) {
+    case CHAP_CHALLENGE:
+      ChapReceiveChallenge(cstate, inp, id, len);
+      break;
+    
+    case CHAP_RESPONSE:
+      ChapReceiveResponse(cstate, inp, id, len);
+      break;
+    
+    case CHAP_FAILURE:
+      ChapReceiveFailure(cstate, inp, id, len);
+      break;
+    
+    case CHAP_SUCCESS:
+      ChapReceiveSuccess(cstate, inp, id, len);
+      break;
+    
+    default:        /* Need code reject? */
+      CHAPDEBUG(LOG_WARNING, ("Unknown CHAP code (%d) received.\n", code));
+      break;
+  }
+}
+
+
+/*
+ * ChapReceiveChallenge - Receive Challenge and send Response.
+ */
+static void
+ChapReceiveChallenge(chap_state *cstate, u_char *inp, u_char id, int len)
+{
+  int rchallenge_len;
+  u_char *rchallenge;
+  int secret_len;
+  char secret[MAXSECRETLEN];
+  char rhostname[256];
+  MD5_CTX mdContext;
+  u_char hash[MD5_SIGNATURE_SIZE];
+
+  CHAPDEBUG(LOG_INFO, ("ChapReceiveChallenge: Rcvd id %d.\n", id));
+  if (cstate->clientstate == CHAPCS_CLOSED ||
+    cstate->clientstate == CHAPCS_PENDING) {
+    CHAPDEBUG(LOG_INFO, ("ChapReceiveChallenge: in state %d\n",
+         cstate->clientstate));
+    return;
+  }
+
+  if (len < 2) {
+    CHAPDEBUG(LOG_INFO, ("ChapReceiveChallenge: rcvd short packet.\n"));
+    return;
+  }
+
+  GETCHAR(rchallenge_len, inp);
+  len -= sizeof (u_char) + rchallenge_len;  /* now name field length */
+  if (len < 0) {
+    CHAPDEBUG(LOG_INFO, ("ChapReceiveChallenge: rcvd short packet.\n"));
+    return;
+  }
+  rchallenge = inp;
+  INCPTR(rchallenge_len, inp);
+
+  if (len >= (int)sizeof(rhostname)) {
+    len = sizeof(rhostname) - 1;
+  }
+  BCOPY(inp, rhostname, len);
+  rhostname[len] = '\000';
+
+  CHAPDEBUG(LOG_INFO, ("ChapReceiveChallenge: received name field '%s'\n",
+             rhostname));
+
+  /* Microsoft doesn't send their name back in the PPP packet */
+  if (ppp_settings.remote_name[0] != 0 && (ppp_settings.explicit_remote || rhostname[0] == 0)) {
+    strncpy(rhostname, ppp_settings.remote_name, sizeof(rhostname));
+    rhostname[sizeof(rhostname) - 1] = 0;
+    CHAPDEBUG(LOG_INFO, ("ChapReceiveChallenge: using '%s' as remote name\n",
+               rhostname));
+  }
+
+  /* get secret for authenticating ourselves with the specified host */
+  if (!get_secret(cstate->unit, cstate->resp_name, rhostname,
+                  secret, &secret_len, 0)) {
+    secret_len = 0;    /* assume null secret if can't find one */
+    CHAPDEBUG(LOG_WARNING, ("No CHAP secret found for authenticating us to %s\n",
+               rhostname));
+  }
+
+  /* cancel response send timeout if necessary */
+  if (cstate->clientstate == CHAPCS_RESPONSE) {
+    UNTIMEOUT(ChapResponseTimeout, cstate);
+  }
+
+  cstate->resp_id = id;
+  cstate->resp_transmits = 0;
+
+  /*  generate MD based on negotiated type */
+  switch (cstate->resp_type) { 
+
+  case CHAP_DIGEST_MD5:
+    MD5Init(&mdContext);
+    MD5Update(&mdContext, &cstate->resp_id, 1);
+    MD5Update(&mdContext, (u_char*)secret, secret_len);
+    MD5Update(&mdContext, rchallenge, rchallenge_len);
+    MD5Final(hash, &mdContext);
+    BCOPY(hash, cstate->response, MD5_SIGNATURE_SIZE);
+    cstate->resp_length = MD5_SIGNATURE_SIZE;
+    break;
+  
+#if MSCHAP_SUPPORT
+  case CHAP_MICROSOFT:
+    ChapMS(cstate, rchallenge, rchallenge_len, secret, secret_len);
+    break;
+#endif
+
+  default:
+    CHAPDEBUG(LOG_INFO, ("unknown digest type %d\n", cstate->resp_type));
+    return;
+  }
+
+  BZERO(secret, sizeof(secret));
+  ChapSendResponse(cstate);
+}
+
+
+/*
+ * ChapReceiveResponse - Receive and process response.
+ */
+static void
+ChapReceiveResponse(chap_state *cstate, u_char *inp, int id, int len)
+{
+  u_char *remmd, remmd_len;
+  int secret_len, old_state;
+  int code;
+  char rhostname[256];
+  MD5_CTX mdContext;
+  char secret[MAXSECRETLEN];
+  u_char hash[MD5_SIGNATURE_SIZE];
+
+  CHAPDEBUG(LOG_INFO, ("ChapReceiveResponse: Rcvd id %d.\n", id));
+  
+  if (cstate->serverstate == CHAPSS_CLOSED ||
+      cstate->serverstate == CHAPSS_PENDING) {
+    CHAPDEBUG(LOG_INFO, ("ChapReceiveResponse: in state %d\n",
+    cstate->serverstate));
+    return;
+  }
+
+  if (id != cstate->chal_id) {
+    return;      /* doesn't match ID of last challenge */
+  }
+
+  /*
+  * If we have received a duplicate or bogus Response,
+  * we have to send the same answer (Success/Failure)
+  * as we did for the first Response we saw.
+  */
+  if (cstate->serverstate == CHAPSS_OPEN) {
+    ChapSendStatus(cstate, CHAP_SUCCESS);
+    return;
+  }
+  if (cstate->serverstate == CHAPSS_BADAUTH) {
+    ChapSendStatus(cstate, CHAP_FAILURE);
+    return;
+  }
+  
+  if (len < 2) {
+    CHAPDEBUG(LOG_INFO, ("ChapReceiveResponse: rcvd short packet.\n"));
+    return;
+  }
+  GETCHAR(remmd_len, inp); /* get length of MD */
+  remmd = inp;             /* get pointer to MD */
+  INCPTR(remmd_len, inp);
+  
+  len -= sizeof (u_char) + remmd_len;
+  if (len < 0) {
+    CHAPDEBUG(LOG_INFO, ("ChapReceiveResponse: rcvd short packet.\n"));
+    return;
+  }
+
+  UNTIMEOUT(ChapChallengeTimeout, cstate);
+  
+  if (len >= (int)sizeof(rhostname)) {
+    len = sizeof(rhostname) - 1;
+  }
+  BCOPY(inp, rhostname, len);
+  rhostname[len] = '\000';
+
+  CHAPDEBUG(LOG_INFO, ("ChapReceiveResponse: received name field: %s\n",
+             rhostname));
+
+  /*
+  * Get secret for authenticating them with us,
+  * do the hash ourselves, and compare the result.
+  */
+  code = CHAP_FAILURE;
+  if (!get_secret(cstate->unit, rhostname, cstate->chal_name,
+                  secret, &secret_len, 1)) {
+    CHAPDEBUG(LOG_WARNING, ("No CHAP secret found for authenticating %s\n",
+               rhostname));
+  } else {
+    /*  generate MD based on negotiated type */
+    switch (cstate->chal_type) {
+
+      case CHAP_DIGEST_MD5:    /* only MD5 is defined for now */
+        if (remmd_len != MD5_SIGNATURE_SIZE) {
+          break;      /* it's not even the right length */
+        }
+        MD5Init(&mdContext);
+        MD5Update(&mdContext, &cstate->chal_id, 1);
+        MD5Update(&mdContext, (u_char*)secret, secret_len);
+        MD5Update(&mdContext, cstate->challenge, cstate->chal_len);
+        MD5Final(hash, &mdContext); 
+        
+        /* compare local and remote MDs and send the appropriate status */
+        if (memcmp (hash, remmd, MD5_SIGNATURE_SIZE) == 0) {
+          code = CHAP_SUCCESS;  /* they are the same! */
+        }
+        break;
+      
+      default:
+        CHAPDEBUG(LOG_INFO, ("unknown digest type %d\n", cstate->chal_type));
+    }
+  }
+  
+  BZERO(secret, sizeof(secret));
+  ChapSendStatus(cstate, code);
+
+  if (code == CHAP_SUCCESS) {
+    old_state = cstate->serverstate;
+    cstate->serverstate = CHAPSS_OPEN;
+    if (old_state == CHAPSS_INITIAL_CHAL) {
+      auth_peer_success(cstate->unit, PPP_CHAP, rhostname, len);
+    }
+    if (cstate->chal_interval != 0) {
+      TIMEOUT(ChapRechallenge, cstate, cstate->chal_interval);
+    }
+  } else {
+    CHAPDEBUG(LOG_ERR, ("CHAP peer authentication failed\n"));
+    cstate->serverstate = CHAPSS_BADAUTH;
+    auth_peer_fail(cstate->unit, PPP_CHAP);
+  }
+}
+
+/*
+ * ChapReceiveSuccess - Receive Success
+ */
+static void
+ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len)
+{
+  LWIP_UNUSED_ARG(id);
+  LWIP_UNUSED_ARG(inp);
+
+  CHAPDEBUG(LOG_INFO, ("ChapReceiveSuccess: Rcvd id %d.\n", id));
+
+  if (cstate->clientstate == CHAPCS_OPEN) {
+    /* presumably an answer to a duplicate response */
+    return;
+  }
+
+  if (cstate->clientstate != CHAPCS_RESPONSE) {
+    /* don't know what this is */
+    CHAPDEBUG(LOG_INFO, ("ChapReceiveSuccess: in state %d\n",
+               cstate->clientstate));
+    return;
+  }
+  
+  UNTIMEOUT(ChapResponseTimeout, cstate);
+  
+  /*
+   * Print message.
+   */
+  if (len > 0) {
+    PRINTMSG(inp, len);
+  }
+
+  cstate->clientstate = CHAPCS_OPEN;
+
+  auth_withpeer_success(cstate->unit, PPP_CHAP);
+}
+
+
+/*
+ * ChapReceiveFailure - Receive failure.
+ */
+static void
+ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len)
+{
+  LWIP_UNUSED_ARG(id);
+  LWIP_UNUSED_ARG(inp);
+
+  CHAPDEBUG(LOG_INFO, ("ChapReceiveFailure: Rcvd id %d.\n", id));
+
+  if (cstate->clientstate != CHAPCS_RESPONSE) {
+    /* don't know what this is */
+    CHAPDEBUG(LOG_INFO, ("ChapReceiveFailure: in state %d\n",
+               cstate->clientstate));
+    return;
+  }
+
+  UNTIMEOUT(ChapResponseTimeout, cstate);
+
+  /*
+   * Print message.
+   */
+  if (len > 0) {
+    PRINTMSG(inp, len);
+  }
+
+  CHAPDEBUG(LOG_ERR, ("CHAP authentication failed\n"));
+  auth_withpeer_fail(cstate->unit, PPP_CHAP); /* lwip: just sets the PPP error code on this unit to PPPERR_AUTHFAIL */
+}
+
+
+/*
+ * ChapSendChallenge - Send an Authenticate challenge.
+ */
+static void
+ChapSendChallenge(chap_state *cstate)
+{
+  u_char *outp;
+  int chal_len, name_len;
+  int outlen;
+  
+  chal_len = cstate->chal_len;
+  name_len = (int)strlen(cstate->chal_name);
+  outlen = CHAP_HEADERLEN + sizeof (u_char) + chal_len + name_len;
+  outp = outpacket_buf[cstate->unit];
+
+  MAKEHEADER(outp, PPP_CHAP);    /* paste in a CHAP header */
+
+  PUTCHAR(CHAP_CHALLENGE, outp);
+  PUTCHAR(cstate->chal_id, outp);
+  PUTSHORT(outlen, outp);
+
+  PUTCHAR(chal_len, outp);    /* put length of challenge */
+  BCOPY(cstate->challenge, outp, chal_len);
+  INCPTR(chal_len, outp);
+
+  BCOPY(cstate->chal_name, outp, name_len);  /* append hostname */
+  
+  pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+
+  CHAPDEBUG(LOG_INFO, ("ChapSendChallenge: Sent id %d.\n", cstate->chal_id));
+  
+  TIMEOUT(ChapChallengeTimeout, cstate, cstate->timeouttime);
+  ++cstate->chal_transmits;
+}
+
+
+/*
+ * ChapSendStatus - Send a status response (ack or nak).
+ */
+static void
+ChapSendStatus(chap_state *cstate, int code)
+{
+  u_char *outp;
+  int outlen, msglen;
+  char msg[256]; /* @todo: this can be a char*, no strcpy needed */
+
+  if (code == CHAP_SUCCESS) {
+    strcpy(msg, "Welcome!");
+  } else {
+    strcpy(msg, "I don't like you.  Go 'way.");
+  }
+  msglen = (int)strlen(msg);
+
+  outlen = CHAP_HEADERLEN + msglen;
+  outp = outpacket_buf[cstate->unit];
+
+  MAKEHEADER(outp, PPP_CHAP);    /* paste in a header */
+  
+  PUTCHAR(code, outp);
+  PUTCHAR(cstate->chal_id, outp);
+  PUTSHORT(outlen, outp);
+  BCOPY(msg, outp, msglen);
+  pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+
+  CHAPDEBUG(LOG_INFO, ("ChapSendStatus: Sent code %d, id %d.\n", code,
+             cstate->chal_id));
+}
+
+/*
+ * ChapGenChallenge is used to generate a pseudo-random challenge string of
+ * a pseudo-random length between min_len and max_len.  The challenge
+ * string and its length are stored in *cstate, and various other fields of
+ * *cstate are initialized.
+ */
+
+static void
+ChapGenChallenge(chap_state *cstate)
+{
+  int chal_len;
+  u_char *ptr = cstate->challenge;
+  int i;
+
+  /* pick a random challenge length between MIN_CHALLENGE_LENGTH and 
+     MAX_CHALLENGE_LENGTH */  
+  chal_len = (unsigned)
+        ((((magic() >> 16) *
+              (MAX_CHALLENGE_LENGTH - MIN_CHALLENGE_LENGTH)) >> 16)
+           + MIN_CHALLENGE_LENGTH);
+  LWIP_ASSERT("chal_len <= 0xff", chal_len <= 0xffff);
+  cstate->chal_len = (u_char)chal_len;
+  cstate->chal_id = ++cstate->id;
+  cstate->chal_transmits = 0;
+
+  /* generate a random string */
+  for (i = 0; i < chal_len; i++ ) {
+    *ptr++ = (char) (magic() & 0xff);
+  }
+}
+
+/*
+ * ChapSendResponse - send a response packet with values as specified
+ * in *cstate.
+ */
+/* ARGSUSED */
+static void
+ChapSendResponse(chap_state *cstate)
+{
+  u_char *outp;
+  int outlen, md_len, name_len;
+
+  md_len = cstate->resp_length;
+  name_len = (int)strlen(cstate->resp_name);
+  outlen = CHAP_HEADERLEN + sizeof (u_char) + md_len + name_len;
+  outp = outpacket_buf[cstate->unit];
+
+  MAKEHEADER(outp, PPP_CHAP);
+  
+  PUTCHAR(CHAP_RESPONSE, outp);  /* we are a response */
+  PUTCHAR(cstate->resp_id, outp);  /* copy id from challenge packet */
+  PUTSHORT(outlen, outp);      /* packet length */
+  
+  PUTCHAR(md_len, outp);      /* length of MD */
+  BCOPY(cstate->response, outp, md_len);    /* copy MD to buffer */
+  INCPTR(md_len, outp);
+
+  BCOPY(cstate->resp_name, outp, name_len);  /* append our name */
+
+  /* send the packet */
+  pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+
+  cstate->clientstate = CHAPCS_RESPONSE;
+  TIMEOUT(ChapResponseTimeout, cstate, cstate->timeouttime);
+  ++cstate->resp_transmits;
+}
+
+#if PPP_ADDITIONAL_CALLBACKS
+static char *ChapCodenames[] = {
+  "Challenge", "Response", "Success", "Failure"
+};
+/*
+ * ChapPrintPkt - print the contents of a CHAP packet.
+ */
+static int
+ChapPrintPkt( u_char *p, int plen, void (*printer) (void *, char *, ...), void *arg)
+{
+  int code, id, len;
+  int clen, nlen;
+  u_char x;
+
+  if (plen < CHAP_HEADERLEN) {
+    return 0;
+  }
+  GETCHAR(code, p);
+  GETCHAR(id, p);
+  GETSHORT(len, p);
+  if (len < CHAP_HEADERLEN || len > plen) {
+    return 0;
+  }
+
+  if (code >= 1 && code <= sizeof(ChapCodenames) / sizeof(char *)) {
+    printer(arg, " %s", ChapCodenames[code-1]);
+  } else {
+    printer(arg, " code=0x%x", code);
+  }
+  printer(arg, " id=0x%x", id);
+  len -= CHAP_HEADERLEN;
+  switch (code) {
+    case CHAP_CHALLENGE:
+    case CHAP_RESPONSE:
+      if (len < 1) {
+        break;
+      }
+      clen = p[0];
+      if (len < clen + 1) {
+        break;
+      }
+      ++p;
+      nlen = len - clen - 1;
+      printer(arg, " <");
+      for (; clen > 0; --clen) {
+        GETCHAR(x, p);
+        printer(arg, "%.2x", x);
+      }
+      printer(arg, ">, name = %.*Z", nlen, p);
+      break;
+    case CHAP_FAILURE:
+    case CHAP_SUCCESS:
+      printer(arg, " %.*Z", len, p);
+      break;
+    default:
+      for (clen = len; clen > 0; --clen) {
+        GETCHAR(x, p);
+        printer(arg, " %.2x", x);
+      }
+  }
+
+  return len + CHAP_HEADERLEN;
+}
+#endif /* PPP_ADDITIONAL_CALLBACKS */
+
+#endif /* CHAP_SUPPORT */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/chap.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/chap.h
new file mode 100644
index 0000000..fedcab8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/chap.h
@@ -0,0 +1,150 @@
+/*****************************************************************************
+* chap.h - Network Challenge Handshake Authentication Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-03 Guy Lancaster , Global Election Systems Inc.
+*   Original built from BSD network code.
+******************************************************************************/
+/*
+ * chap.h - Challenge Handshake Authentication Protocol definitions.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University.  The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1991 Gregory M. Christy
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the author.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: chap.h,v 1.6 2010/01/24 13:19:34 goldsimon Exp $
+ */
+
+#ifndef CHAP_H
+#define CHAP_H
+
+/* Code + ID + length */
+#define CHAP_HEADERLEN 4
+
+/*
+ * CHAP codes.
+ */
+
+#define CHAP_DIGEST_MD5      5    /* use MD5 algorithm */
+#define MD5_SIGNATURE_SIZE   16   /* 16 bytes in a MD5 message digest */
+#define CHAP_MICROSOFT       0x80 /* use Microsoft-compatible alg. */
+#define MS_CHAP_RESPONSE_LEN 49   /* Response length for MS-CHAP */
+
+#define CHAP_CHALLENGE       1
+#define CHAP_RESPONSE        2
+#define CHAP_SUCCESS         3
+#define CHAP_FAILURE         4
+
+/*
+ *  Challenge lengths (for challenges we send) and other limits.
+ */
+#define MIN_CHALLENGE_LENGTH 32
+#define MAX_CHALLENGE_LENGTH 64
+#define MAX_RESPONSE_LENGTH  64 /* sufficient for MD5 or MS-CHAP */
+
+/*
+ * Each interface is described by a chap structure.
+ */
+
+typedef struct chap_state {
+  int unit;                               /* Interface unit number */
+  int clientstate;                        /* Client state */
+  int serverstate;                        /* Server state */
+  u_char challenge[MAX_CHALLENGE_LENGTH]; /* last challenge string sent */
+  u_char chal_len;                        /* challenge length */
+  u_char chal_id;                         /* ID of last challenge */
+  u_char chal_type;                       /* hash algorithm for challenges */
+  u_char id;                              /* Current id */
+  char *chal_name;                        /* Our name to use with challenge */
+  int chal_interval;                      /* Time until we challenge peer again */
+  int timeouttime;                        /* Timeout time in seconds */
+  int max_transmits;                      /* Maximum # of challenge transmissions */
+  int chal_transmits;                     /* Number of transmissions of challenge */
+  int resp_transmits;                     /* Number of transmissions of response */
+  u_char response[MAX_RESPONSE_LENGTH];   /* Response to send */
+  u_char resp_length;                     /* length of response */
+  u_char resp_id;                         /* ID for response messages */
+  u_char resp_type;                       /* hash algorithm for responses */
+  char *resp_name;                        /* Our name to send with response */
+} chap_state;
+
+
+/*
+ * Client (peer) states.
+ */
+#define CHAPCS_INITIAL       0 /* Lower layer down, not opened */
+#define CHAPCS_CLOSED        1 /* Lower layer up, not opened */
+#define CHAPCS_PENDING       2 /* Auth us to peer when lower up */
+#define CHAPCS_LISTEN        3 /* Listening for a challenge */
+#define CHAPCS_RESPONSE      4 /* Sent response, waiting for status */
+#define CHAPCS_OPEN          5 /* We've received Success */
+
+/*
+ * Server (authenticator) states.
+ */
+#define CHAPSS_INITIAL       0 /* Lower layer down, not opened */
+#define CHAPSS_CLOSED        1 /* Lower layer up, not opened */
+#define CHAPSS_PENDING       2 /* Auth peer when lower up */
+#define CHAPSS_INITIAL_CHAL  3 /* We've sent the first challenge */
+#define CHAPSS_OPEN          4 /* We've sent a Success msg */
+#define CHAPSS_RECHALLENGE   5 /* We've sent another challenge */
+#define CHAPSS_BADAUTH       6 /* We've sent a Failure msg */
+
+extern chap_state chap[];
+
+void ChapAuthWithPeer (int, char *, u_char);
+void ChapAuthPeer (int, char *, u_char);
+
+extern struct protent chap_protent;
+
+#endif /* CHAP_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/chpms.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/chpms.c
new file mode 100644
index 0000000..83acefc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/chpms.c
@@ -0,0 +1,396 @@
+/*** WARNING - THIS CODE HAS NOT BEEN FINISHED! ***/
+/*** The original PPPD code is written in a way to require either the UNIX DES
+     encryption functions encrypt(3) and setkey(3) or the DES library libdes.
+     Since both is not included in lwIP, MSCHAP currently does not work! */
+/*****************************************************************************
+* chpms.c - Network MicroSoft Challenge Handshake Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 by Global Election Systems Inc.  All rights reserved.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-08 Guy Lancaster , Global Election Systems Inc.
+*   Original based on BSD chap_ms.c.
+*****************************************************************************/
+/*
+ * chap_ms.c - Microsoft MS-CHAP compatible implementation.
+ *
+ * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited.
+ * http://www.strataware.com/
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Eric Rosenquist.  The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+/*
+ * Modifications by Lauri Pesonen / lpesonen@clinet.fi, april 1997
+ *
+ *   Implemented LANManager type password response to MS-CHAP challenges.
+ *   Now pppd provides both NT style and LANMan style blocks, and the
+ *   prefered is set by option "ms-lanman". Default is to use NT.
+ *   The hash text (StdText) was taken from Win95 RASAPI32.DLL.
+ *
+ *   You should also use DOMAIN\\USERNAME as described in README.MSCHAP80
+ */
+
+#define USE_CRYPT
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#if MSCHAP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "md4.h"
+#ifndef USE_CRYPT
+#include "des.h"
+#endif
+#include "chap.h"
+#include "chpms.h"
+
+#include 
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+typedef struct {
+    u_char LANManResp[24];
+    u_char NTResp[24];
+    u_char UseNT; /* If 1, ignore the LANMan response field */
+} MS_ChapResponse;
+/* We use MS_CHAP_RESPONSE_LEN, rather than sizeof(MS_ChapResponse),
+   in case this struct gets padded. */
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+
+/* XXX Don't know what to do with these. */
+extern void setkey(const char *);
+extern void encrypt(char *, int);
+
+static void DesEncrypt (u_char *, u_char *, u_char *);
+static void MakeKey (u_char *, u_char *);
+
+#ifdef USE_CRYPT
+static void Expand (u_char *, u_char *);
+static void Collapse (u_char *, u_char *);
+#endif
+
+static void ChallengeResponse(
+  u_char *challenge, /* IN   8 octets */
+  u_char *pwHash,    /* IN  16 octets */
+  u_char *response   /* OUT 24 octets */
+);
+static void ChapMS_NT(
+  char *rchallenge,
+  int rchallenge_len,
+  char *secret,
+  int secret_len,
+  MS_ChapResponse *response
+);
+static u_char Get7Bits(
+  u_char *input,
+  int startBit
+);
+
+static void
+ChallengeResponse( u_char *challenge, /* IN   8 octets */
+                   u_char *pwHash,    /* IN  16 octets */
+                   u_char *response   /* OUT 24 octets */)
+{
+  u_char    ZPasswordHash[21];
+
+  BZERO(ZPasswordHash, sizeof(ZPasswordHash));
+  BCOPY(pwHash, ZPasswordHash, 16);
+
+#if 0
+  log_packet(ZPasswordHash, sizeof(ZPasswordHash), "ChallengeResponse - ZPasswordHash", LOG_DEBUG);
+#endif
+
+  DesEncrypt(challenge, ZPasswordHash +  0, response + 0);
+  DesEncrypt(challenge, ZPasswordHash +  7, response + 8);
+  DesEncrypt(challenge, ZPasswordHash + 14, response + 16);
+
+#if 0
+  log_packet(response, 24, "ChallengeResponse - response", LOG_DEBUG);
+#endif
+}
+
+
+#ifdef USE_CRYPT
+static void
+DesEncrypt( u_char *clear, /* IN  8 octets */
+            u_char *key,   /* IN  7 octets */
+            u_char *cipher /* OUT 8 octets */)
+{
+  u_char des_key[8];
+  u_char crypt_key[66];
+  u_char des_input[66];
+
+  MakeKey(key, des_key);
+
+  Expand(des_key, crypt_key);
+  setkey((char*)crypt_key);
+
+#if 0
+  CHAPDEBUG(LOG_INFO, ("DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n",
+             clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7]));
+#endif
+
+  Expand(clear, des_input);
+  encrypt((char*)des_input, 0);
+  Collapse(des_input, cipher);
+
+#if 0
+  CHAPDEBUG(LOG_INFO, ("DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+             cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7]));
+#endif
+}
+
+#else /* USE_CRYPT */
+
+static void
+DesEncrypt( u_char *clear, /* IN  8 octets */
+            u_char *key,   /* IN  7 octets */
+            u_char *cipher /* OUT 8 octets */)
+{
+  des_cblock    des_key;
+  des_key_schedule  key_schedule;
+
+  MakeKey(key, des_key);
+
+  des_set_key(&des_key, key_schedule);
+
+#if 0
+  CHAPDEBUG(LOG_INFO, ("DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n",
+             clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7]));
+#endif
+
+  des_ecb_encrypt((des_cblock *)clear, (des_cblock *)cipher, key_schedule, 1);
+
+#if 0
+  CHAPDEBUG(LOG_INFO, ("DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+             cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7]));
+#endif
+}
+
+#endif /* USE_CRYPT */
+
+
+static u_char
+Get7Bits( u_char *input, int startBit)
+{
+  register unsigned int  word;
+
+  word  = (unsigned)input[startBit / 8] << 8;
+  word |= (unsigned)input[startBit / 8 + 1];
+
+  word >>= 15 - (startBit % 8 + 7);
+
+  return word & 0xFE;
+}
+
+#ifdef USE_CRYPT
+
+/* in == 8-byte string (expanded version of the 56-bit key)
+ * out == 64-byte string where each byte is either 1 or 0
+ * Note that the low-order "bit" is always ignored by by setkey()
+ */
+static void
+Expand(u_char *in, u_char *out)
+{
+  int j, c;
+  int i;
+
+  for(i = 0; i < 64; in++){
+    c = *in;
+    for(j = 7; j >= 0; j--) {
+      *out++ = (c >> j) & 01;
+    }
+    i += 8;
+  }
+}
+
+/* The inverse of Expand
+ */
+static void
+Collapse(u_char *in, u_char *out)
+{
+  int j;
+  int i;
+  unsigned int c;
+
+  for (i = 0; i < 64; i += 8, out++) {
+    c = 0;
+    for (j = 7; j >= 0; j--, in++) {
+      c |= *in << j;
+    }
+    *out = c & 0xff;
+  }
+}
+#endif
+
+static void
+MakeKey( u_char *key,    /* IN  56 bit DES key missing parity bits */
+         u_char *des_key /* OUT 64 bit DES key with parity bits added */)
+{
+  des_key[0] = Get7Bits(key,  0);
+  des_key[1] = Get7Bits(key,  7);
+  des_key[2] = Get7Bits(key, 14);
+  des_key[3] = Get7Bits(key, 21);
+  des_key[4] = Get7Bits(key, 28);
+  des_key[5] = Get7Bits(key, 35);
+  des_key[6] = Get7Bits(key, 42);
+  des_key[7] = Get7Bits(key, 49);
+  
+#ifndef USE_CRYPT
+  des_set_odd_parity((des_cblock *)des_key);
+#endif
+  
+#if 0
+  CHAPDEBUG(LOG_INFO, ("MakeKey: 56-bit input : %02X%02X%02X%02X%02X%02X%02X\n",
+             key[0], key[1], key[2], key[3], key[4], key[5], key[6]));
+  CHAPDEBUG(LOG_INFO, ("MakeKey: 64-bit output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+             des_key[0], des_key[1], des_key[2], des_key[3], des_key[4], des_key[5], des_key[6], des_key[7]));
+#endif
+}
+
+static void
+ChapMS_NT( char *rchallenge,
+           int rchallenge_len,
+           char *secret,
+           int secret_len,
+           MS_ChapResponse *response)
+{
+  int      i;
+  MDstruct  md4Context;
+  u_char    unicodePassword[MAX_NT_PASSWORD * 2];
+  static int  low_byte_first = -1;
+
+  LWIP_UNUSED_ARG(rchallenge_len);
+
+  /* Initialize the Unicode version of the secret (== password). */
+  /* This implicitly supports 8-bit ISO8859/1 characters. */
+  BZERO(unicodePassword, sizeof(unicodePassword));
+  for (i = 0; i < secret_len; i++) {
+    unicodePassword[i * 2] = (u_char)secret[i];
+  }
+  MDbegin(&md4Context);
+  MDupdate(&md4Context, unicodePassword, secret_len * 2 * 8);  /* Unicode is 2 bytes/char, *8 for bit count */
+
+  if (low_byte_first == -1) {
+    low_byte_first = (PP_HTONS((unsigned short int)1) != 1);
+  }
+  if (low_byte_first == 0) {
+    /* @todo: arg type - u_long* or u_int* ? */
+    MDreverse((unsigned int*)&md4Context);  /*  sfb 961105 */
+  }
+
+  MDupdate(&md4Context, NULL, 0);  /* Tell MD4 we're done */
+
+  ChallengeResponse((u_char*)rchallenge, (u_char*)md4Context.buffer, response->NTResp);
+}
+
+#ifdef MSLANMAN
+static u_char *StdText = (u_char *)"KGS!@#$%"; /* key from rasapi32.dll */
+
+static void
+ChapMS_LANMan( char *rchallenge,
+               int rchallenge_len,
+               char *secret,
+               int secret_len,
+               MS_ChapResponse  *response)
+{
+  int      i;
+  u_char    UcasePassword[MAX_NT_PASSWORD]; /* max is actually 14 */
+  u_char    PasswordHash[16];
+  
+  /* LANMan password is case insensitive */
+  BZERO(UcasePassword, sizeof(UcasePassword));
+  for (i = 0; i < secret_len; i++) {
+    UcasePassword[i] = (u_char)toupper(secret[i]);
+  }
+  DesEncrypt( StdText, UcasePassword + 0, PasswordHash + 0 );
+  DesEncrypt( StdText, UcasePassword + 7, PasswordHash + 8 );
+  ChallengeResponse(rchallenge, PasswordHash, response->LANManResp);
+}
+#endif
+
+void
+ChapMS( chap_state *cstate, char *rchallenge, int rchallenge_len, char *secret, int secret_len)
+{
+  MS_ChapResponse response;
+#ifdef MSLANMAN
+  extern int ms_lanman;
+#endif
+
+#if 0
+  CHAPDEBUG(LOG_INFO, ("ChapMS: secret is '%.*s'\n", secret_len, secret));
+#endif
+  BZERO(&response, sizeof(response));
+
+  /* Calculate both always */
+  ChapMS_NT(rchallenge, rchallenge_len, secret, secret_len, &response);
+
+#ifdef MSLANMAN
+  ChapMS_LANMan(rchallenge, rchallenge_len, secret, secret_len, &response);
+
+  /* prefered method is set by option  */
+  response.UseNT = !ms_lanman;
+#else
+  response.UseNT = 1;
+#endif
+
+  BCOPY(&response, cstate->response, MS_CHAP_RESPONSE_LEN);
+  cstate->resp_length = MS_CHAP_RESPONSE_LEN;
+}
+
+#endif /* MSCHAP_SUPPORT */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/chpms.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/chpms.h
new file mode 100644
index 0000000..df070fb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/chpms.h
@@ -0,0 +1,64 @@
+/*****************************************************************************
+* chpms.h - Network Microsoft Challenge Handshake Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-01-30 Guy Lancaster , Global Election Systems Inc.
+*   Original built from BSD network code.
+******************************************************************************/
+/*
+ * chap.h - Challenge Handshake Authentication Protocol definitions.
+ *
+ * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited.
+ * http://www.strataware.com/
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Eric Rosenquist.  The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: chpms.h,v 1.5 2007/12/19 20:47:23 fbernon Exp $
+ */
+
+#ifndef CHPMS_H
+#define CHPMS_H
+
+#define MAX_NT_PASSWORD 256 /* Maximum number of (Unicode) chars in an NT password */
+
+void ChapMS (chap_state *, char *, int, char *, int);
+
+#endif /* CHPMS_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/fsm.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/fsm.c
new file mode 100644
index 0000000..2e73c5a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/fsm.c
@@ -0,0 +1,890 @@
+/*****************************************************************************
+* fsm.c - Network Control Protocol Finite State Machine program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-01 Guy Lancaster , Global Election Systems Inc.
+*   Original based on BSD fsm.c.
+*****************************************************************************/
+/*
+ * fsm.c - {Link, IP} Control Protocol Finite State Machine.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+/*
+ * TODO:
+ * Randomize fsm id on link/init.
+ * Deal with variable outgoing MTU.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "fsm.h"
+
+#include 
+
+#if PPP_DEBUG
+static const char *ppperr_strerr[] = {
+           "LS_INITIAL",  /* LS_INITIAL  0 */
+           "LS_STARTING", /* LS_STARTING 1 */
+           "LS_CLOSED",   /* LS_CLOSED   2 */
+           "LS_STOPPED",  /* LS_STOPPED  3 */
+           "LS_CLOSING",  /* LS_CLOSING  4 */
+           "LS_STOPPING", /* LS_STOPPING 5 */
+           "LS_REQSENT",  /* LS_REQSENT  6 */
+           "LS_ACKRCVD",  /* LS_ACKRCVD  7 */
+           "LS_ACKSENT",  /* LS_ACKSENT  8 */
+           "LS_OPENED"    /* LS_OPENED   9 */
+};
+#endif /* PPP_DEBUG */
+
+static void fsm_timeout (void *);
+static void fsm_rconfreq (fsm *, u_char, u_char *, int);
+static void fsm_rconfack (fsm *, int, u_char *, int);
+static void fsm_rconfnakrej (fsm *, int, int, u_char *, int);
+static void fsm_rtermreq (fsm *, int, u_char *, int);
+static void fsm_rtermack (fsm *);
+static void fsm_rcoderej (fsm *, u_char *, int);
+static void fsm_sconfreq (fsm *, int);
+
+#define PROTO_NAME(f) ((f)->callbacks->proto_name)
+
+int peer_mru[NUM_PPP];
+
+
+/*
+ * fsm_init - Initialize fsm.
+ *
+ * Initialize fsm state.
+ */
+void
+fsm_init(fsm *f)
+{
+  f->state = LS_INITIAL;
+  f->flags = 0;
+  f->id = 0;        /* XXX Start with random id? */
+  f->timeouttime = FSM_DEFTIMEOUT;
+  f->maxconfreqtransmits = FSM_DEFMAXCONFREQS;
+  f->maxtermtransmits = FSM_DEFMAXTERMREQS;
+  f->maxnakloops = FSM_DEFMAXNAKLOOPS;
+  f->term_reason_len = 0;
+}
+
+
+/*
+ * fsm_lowerup - The lower layer is up.
+ */
+void
+fsm_lowerup(fsm *f)
+{
+  int oldState = f->state;
+
+  LWIP_UNUSED_ARG(oldState);
+
+  switch( f->state ) {
+    case LS_INITIAL:
+      f->state = LS_CLOSED;
+      break;
+
+    case LS_STARTING:
+      if( f->flags & OPT_SILENT ) {
+        f->state = LS_STOPPED;
+      } else {
+        /* Send an initial configure-request */
+        fsm_sconfreq(f, 0);
+        f->state = LS_REQSENT;
+      }
+    break;
+
+    default:
+      FSMDEBUG(LOG_INFO, ("%s: Up event in state %d (%s)!\n",
+          PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+  }
+
+  FSMDEBUG(LOG_INFO, ("%s: lowerup state %d (%s) -> %d (%s)\n",
+      PROTO_NAME(f), oldState, ppperr_strerr[oldState], f->state, ppperr_strerr[f->state]));
+}
+
+
+/*
+ * fsm_lowerdown - The lower layer is down.
+ *
+ * Cancel all timeouts and inform upper layers.
+ */
+void
+fsm_lowerdown(fsm *f)
+{
+  int oldState = f->state;
+
+  LWIP_UNUSED_ARG(oldState);
+
+  switch( f->state ) {
+    case LS_CLOSED:
+      f->state = LS_INITIAL;
+      break;
+
+    case LS_STOPPED:
+      f->state = LS_STARTING;
+      if( f->callbacks->starting ) {
+        (*f->callbacks->starting)(f);
+      }
+      break;
+
+    case LS_CLOSING:
+      f->state = LS_INITIAL;
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      break;
+
+    case LS_STOPPING:
+    case LS_REQSENT:
+    case LS_ACKRCVD:
+    case LS_ACKSENT:
+      f->state = LS_STARTING;
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      break;
+
+    case LS_OPENED:
+      if( f->callbacks->down ) {
+        (*f->callbacks->down)(f);
+      }
+      f->state = LS_STARTING;
+      break;
+
+    default:
+      FSMDEBUG(LOG_INFO, ("%s: Down event in state %d (%s)!\n",
+          PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+  }
+
+  FSMDEBUG(LOG_INFO, ("%s: lowerdown state %d (%s) -> %d (%s)\n",
+      PROTO_NAME(f), oldState, ppperr_strerr[oldState], f->state, ppperr_strerr[f->state]));
+}
+
+
+/*
+ * fsm_open - Link is allowed to come up.
+ */
+void
+fsm_open(fsm *f)
+{
+  int oldState = f->state;
+
+  LWIP_UNUSED_ARG(oldState);
+
+  switch( f->state ) {
+    case LS_INITIAL:
+      f->state = LS_STARTING;
+      if( f->callbacks->starting ) {
+        (*f->callbacks->starting)(f);
+      }
+      break;
+
+    case LS_CLOSED:
+      if( f->flags & OPT_SILENT ) {
+        f->state = LS_STOPPED;
+      } else {
+        /* Send an initial configure-request */
+        fsm_sconfreq(f, 0);
+        f->state = LS_REQSENT;
+      }
+      break;
+  
+    case LS_CLOSING:
+      f->state = LS_STOPPING;
+      /* fall through */
+    case LS_STOPPED:
+    case LS_OPENED:
+      if( f->flags & OPT_RESTART ) {
+        fsm_lowerdown(f);
+        fsm_lowerup(f);
+      }
+      break;
+  }
+
+  FSMDEBUG(LOG_INFO, ("%s: open state %d (%s) -> %d (%s)\n",
+      PROTO_NAME(f), oldState, ppperr_strerr[oldState], f->state, ppperr_strerr[f->state]));
+}
+
+#if 0 /* backport pppd 2.4.4b1; */
+/*
+ * terminate_layer - Start process of shutting down the FSM
+ *
+ * Cancel any timeout running, notify upper layers we're done, and
+ * send a terminate-request message as configured.
+ */
+static void
+terminate_layer(fsm *f, int nextstate)
+{
+  /* @todo */
+}
+#endif
+
+/*
+ * fsm_close - Start closing connection.
+ *
+ * Cancel timeouts and either initiate close or possibly go directly to
+ * the LS_CLOSED state.
+ */
+void
+fsm_close(fsm *f, char *reason)
+{
+  int oldState = f->state;
+
+  LWIP_UNUSED_ARG(oldState);
+
+  f->term_reason = reason;
+  f->term_reason_len = (reason == NULL ? 0 : (int)strlen(reason));
+  switch( f->state ) {
+    case LS_STARTING:
+      f->state = LS_INITIAL;
+      break;
+    case LS_STOPPED:
+      f->state = LS_CLOSED;
+      break;
+    case LS_STOPPING:
+      f->state = LS_CLOSING;
+      break;
+
+    case LS_REQSENT:
+    case LS_ACKRCVD:
+    case LS_ACKSENT:
+    case LS_OPENED:
+      if( f->state != LS_OPENED ) {
+        UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      } else if( f->callbacks->down ) {
+        (*f->callbacks->down)(f);  /* Inform upper layers we're down */
+      }
+      /* Init restart counter, send Terminate-Request */
+      f->retransmits = f->maxtermtransmits;
+      fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+            (u_char *) f->term_reason, f->term_reason_len);
+      TIMEOUT(fsm_timeout, f, f->timeouttime);
+      --f->retransmits;
+
+      f->state = LS_CLOSING;
+      break;
+  }
+
+  FSMDEBUG(LOG_INFO, ("%s: close reason=%s state %d (%s) -> %d (%s)\n",
+      PROTO_NAME(f), reason, oldState, ppperr_strerr[oldState], f->state, ppperr_strerr[f->state]));
+}
+
+
+/*
+ * fsm_timeout - Timeout expired.
+ */
+static void
+fsm_timeout(void *arg)
+{
+  fsm *f = (fsm *) arg;
+
+  switch (f->state) {
+    case LS_CLOSING:
+    case LS_STOPPING:
+      if( f->retransmits <= 0 ) {
+        FSMDEBUG(LOG_WARNING, ("%s: timeout sending Terminate-Request state=%d (%s)\n",
+             PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+        /*
+         * We've waited for an ack long enough.  Peer probably heard us.
+         */
+        f->state = (f->state == LS_CLOSING)? LS_CLOSED: LS_STOPPED;
+        if( f->callbacks->finished ) {
+          (*f->callbacks->finished)(f);
+        }
+      } else {
+        FSMDEBUG(LOG_WARNING, ("%s: timeout resending Terminate-Requests state=%d (%s)\n",
+             PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+        /* Send Terminate-Request */
+        fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+            (u_char *) f->term_reason, f->term_reason_len);
+        TIMEOUT(fsm_timeout, f, f->timeouttime);
+        --f->retransmits;
+      }
+      break;
+
+    case LS_REQSENT:
+    case LS_ACKRCVD:
+    case LS_ACKSENT:
+      if (f->retransmits <= 0) {
+        FSMDEBUG(LOG_WARNING, ("%s: timeout sending Config-Requests state=%d (%s)\n",
+         PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+        f->state = LS_STOPPED;
+        if( (f->flags & OPT_PASSIVE) == 0 && f->callbacks->finished ) {
+          (*f->callbacks->finished)(f);
+        }
+      } else {
+        FSMDEBUG(LOG_WARNING, ("%s: timeout resending Config-Request state=%d (%s)\n",
+         PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+        /* Retransmit the configure-request */
+        if (f->callbacks->retransmit) {
+          (*f->callbacks->retransmit)(f);
+        }
+        fsm_sconfreq(f, 1);    /* Re-send Configure-Request */
+        if( f->state == LS_ACKRCVD ) {
+          f->state = LS_REQSENT;
+        }
+      }
+      break;
+
+    default:
+      FSMDEBUG(LOG_INFO, ("%s: UNHANDLED timeout event in state %d (%s)!\n",
+          PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+  }
+}
+
+
+/*
+ * fsm_input - Input packet.
+ */
+void
+fsm_input(fsm *f, u_char *inpacket, int l)
+{
+  u_char *inp = inpacket;
+  u_char code, id;
+  int len;
+
+  /*
+  * Parse header (code, id and length).
+  * If packet too short, drop it.
+  */
+  if (l < HEADERLEN) {
+    FSMDEBUG(LOG_WARNING, ("fsm_input(%x): Rcvd short header.\n",
+          f->protocol));
+    return;
+  }
+  GETCHAR(code, inp);
+  GETCHAR(id, inp);
+  GETSHORT(len, inp);
+  if (len < HEADERLEN) {
+    FSMDEBUG(LOG_INFO, ("fsm_input(%x): Rcvd illegal length.\n",
+        f->protocol));
+    return;
+  }
+  if (len > l) {
+    FSMDEBUG(LOG_INFO, ("fsm_input(%x): Rcvd short packet.\n",
+        f->protocol));
+    return;
+  }
+  len -= HEADERLEN;    /* subtract header length */
+
+  if( f->state == LS_INITIAL || f->state == LS_STARTING ) {
+    FSMDEBUG(LOG_INFO, ("fsm_input(%x): Rcvd packet in state %d (%s).\n",
+        f->protocol, f->state, ppperr_strerr[f->state]));
+    return;
+  }
+  FSMDEBUG(LOG_INFO, ("fsm_input(%s):%d,%d,%d\n", PROTO_NAME(f), code, id, l));
+  /*
+   * Action depends on code.
+   */
+  switch (code) {
+    case CONFREQ:
+      fsm_rconfreq(f, id, inp, len);
+      break;
+    
+    case CONFACK:
+      fsm_rconfack(f, id, inp, len);
+      break;
+    
+    case CONFNAK:
+    case CONFREJ:
+      fsm_rconfnakrej(f, code, id, inp, len);
+      break;
+    
+    case TERMREQ:
+      fsm_rtermreq(f, id, inp, len);
+      break;
+    
+    case TERMACK:
+      fsm_rtermack(f);
+      break;
+    
+    case CODEREJ:
+      fsm_rcoderej(f, inp, len);
+      break;
+    
+    default:
+      FSMDEBUG(LOG_INFO, ("fsm_input(%s): default: \n", PROTO_NAME(f)));
+      if( !f->callbacks->extcode ||
+          !(*f->callbacks->extcode)(f, code, id, inp, len) ) {
+        fsm_sdata(f, CODEREJ, ++f->id, inpacket, len + HEADERLEN);
+      }
+      break;
+  }
+}
+
+
+/*
+ * fsm_rconfreq - Receive Configure-Request.
+ */
+static void
+fsm_rconfreq(fsm *f, u_char id, u_char *inp, int len)
+{
+  int code, reject_if_disagree;
+
+  FSMDEBUG(LOG_INFO, ("fsm_rconfreq(%s): Rcvd id %d state=%d (%s)\n", 
+        PROTO_NAME(f), id, f->state, ppperr_strerr[f->state]));
+  switch( f->state ) {
+    case LS_CLOSED:
+      /* Go away, we're closed */
+      fsm_sdata(f, TERMACK, id, NULL, 0);
+      return;
+    case LS_CLOSING:
+    case LS_STOPPING:
+      return;
+
+    case LS_OPENED:
+      /* Go down and restart negotiation */
+      if( f->callbacks->down ) {
+        (*f->callbacks->down)(f);  /* Inform upper layers */
+      }
+      fsm_sconfreq(f, 0);    /* Send initial Configure-Request */
+      break;
+
+    case LS_STOPPED:
+      /* Negotiation started by our peer */
+      fsm_sconfreq(f, 0);    /* Send initial Configure-Request */
+      f->state = LS_REQSENT;
+      break;
+  }
+  
+  /*
+  * Pass the requested configuration options
+  * to protocol-specific code for checking.
+  */
+  if (f->callbacks->reqci) {    /* Check CI */
+    reject_if_disagree = (f->nakloops >= f->maxnakloops);
+    code = (*f->callbacks->reqci)(f, inp, &len, reject_if_disagree);
+  } else if (len) {
+    code = CONFREJ;      /* Reject all CI */
+  } else {
+    code = CONFACK;
+  }
+  
+  /* send the Ack, Nak or Rej to the peer */
+  fsm_sdata(f, (u_char)code, id, inp, len);
+  
+  if (code == CONFACK) {
+    if (f->state == LS_ACKRCVD) {
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      f->state = LS_OPENED;
+      if (f->callbacks->up) {
+        (*f->callbacks->up)(f);  /* Inform upper layers */
+      }
+    } else {
+      f->state = LS_ACKSENT;
+    }
+    f->nakloops = 0;
+  } else {
+    /* we sent CONFACK or CONFREJ */
+    if (f->state != LS_ACKRCVD) {
+      f->state = LS_REQSENT;
+    }
+    if( code == CONFNAK ) {
+      ++f->nakloops;
+    }
+  }
+}
+
+
+/*
+ * fsm_rconfack - Receive Configure-Ack.
+ */
+static void
+fsm_rconfack(fsm *f, int id, u_char *inp, int len)
+{
+  FSMDEBUG(LOG_INFO, ("fsm_rconfack(%s): Rcvd id %d state=%d (%s)\n",
+        PROTO_NAME(f), id, f->state, ppperr_strerr[f->state]));
+  
+  if (id != f->reqid || f->seen_ack) {   /* Expected id? */
+    return; /* Nope, toss... */
+  }
+  if( !(f->callbacks->ackci? (*f->callbacks->ackci)(f, inp, len): (len == 0)) ) {
+    /* Ack is bad - ignore it */
+    FSMDEBUG(LOG_INFO, ("%s: received bad Ack (length %d)\n",
+          PROTO_NAME(f), len));
+    return;
+  }
+  f->seen_ack = 1;
+  
+  switch (f->state) {
+    case LS_CLOSED:
+    case LS_STOPPED:
+      fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+      break;
+    
+    case LS_REQSENT:
+      f->state = LS_ACKRCVD;
+      f->retransmits = f->maxconfreqtransmits;
+      break;
+    
+    case LS_ACKRCVD:
+      /* Huh? an extra valid Ack? oh well... */
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      fsm_sconfreq(f, 0);
+      f->state = LS_REQSENT;
+      break;
+    
+    case LS_ACKSENT:
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      f->state = LS_OPENED;
+      f->retransmits = f->maxconfreqtransmits;
+      if (f->callbacks->up) {
+        (*f->callbacks->up)(f);  /* Inform upper layers */
+      }
+      break;
+    
+    case LS_OPENED:
+      /* Go down and restart negotiation */
+      if (f->callbacks->down) {
+        (*f->callbacks->down)(f);  /* Inform upper layers */
+      }
+      fsm_sconfreq(f, 0);    /* Send initial Configure-Request */
+      f->state = LS_REQSENT;
+      break;
+  }
+}
+
+
+/*
+ * fsm_rconfnakrej - Receive Configure-Nak or Configure-Reject.
+ */
+static void
+fsm_rconfnakrej(fsm *f, int code, int id, u_char *inp, int len)
+{
+  int (*proc) (fsm *, u_char *, int);
+  int ret;
+
+  FSMDEBUG(LOG_INFO, ("fsm_rconfnakrej(%s): Rcvd id %d state=%d (%s)\n",
+        PROTO_NAME(f), id, f->state, ppperr_strerr[f->state]));
+
+  if (id != f->reqid || f->seen_ack) { /* Expected id? */
+    return;        /* Nope, toss... */
+  }
+  proc = (code == CONFNAK)? f->callbacks->nakci: f->callbacks->rejci;
+  if (!proc || !((ret = proc(f, inp, len)))) {
+    /* Nak/reject is bad - ignore it */
+    FSMDEBUG(LOG_INFO, ("%s: received bad %s (length %d)\n",
+          PROTO_NAME(f), (code==CONFNAK? "Nak": "reject"), len));
+    return;
+  }
+  f->seen_ack = 1;
+
+  switch (f->state) {
+    case LS_CLOSED:
+    case LS_STOPPED:
+      fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+      break;
+    
+    case LS_REQSENT:
+    case LS_ACKSENT:
+      /* They didn't agree to what we wanted - try another request */
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      if (ret < 0) {
+        f->state = LS_STOPPED;    /* kludge for stopping CCP */
+      } else {
+        fsm_sconfreq(f, 0);    /* Send Configure-Request */
+      }
+      break;
+    
+    case LS_ACKRCVD:
+      /* Got a Nak/reject when we had already had an Ack?? oh well... */
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      fsm_sconfreq(f, 0);
+      f->state = LS_REQSENT;
+      break;
+    
+    case LS_OPENED:
+      /* Go down and restart negotiation */
+      if (f->callbacks->down) {
+        (*f->callbacks->down)(f);  /* Inform upper layers */
+      }
+      fsm_sconfreq(f, 0);    /* Send initial Configure-Request */
+      f->state = LS_REQSENT;
+      break;
+  }
+}
+
+
+/*
+ * fsm_rtermreq - Receive Terminate-Req.
+ */
+static void
+fsm_rtermreq(fsm *f, int id, u_char *p, int len)
+{
+  LWIP_UNUSED_ARG(p);
+
+  FSMDEBUG(LOG_INFO, ("fsm_rtermreq(%s): Rcvd id %d state=%d (%s)\n",
+        PROTO_NAME(f), id, f->state, ppperr_strerr[f->state]));
+
+  switch (f->state) {
+    case LS_ACKRCVD:
+    case LS_ACKSENT:
+      f->state = LS_REQSENT;    /* Start over but keep trying */
+      break;
+
+    case LS_OPENED:
+      if (len > 0) {
+        FSMDEBUG(LOG_INFO, ("%s terminated by peer (%p)\n", PROTO_NAME(f), p));
+      } else {
+        FSMDEBUG(LOG_INFO, ("%s terminated by peer\n", PROTO_NAME(f)));
+      }
+      if (f->callbacks->down) {
+        (*f->callbacks->down)(f);  /* Inform upper layers */
+      }
+      f->retransmits = 0;
+      f->state = LS_STOPPING;
+      TIMEOUT(fsm_timeout, f, f->timeouttime);
+      break;
+  }
+
+  fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+}
+
+
+/*
+ * fsm_rtermack - Receive Terminate-Ack.
+ */
+static void
+fsm_rtermack(fsm *f)
+{
+  FSMDEBUG(LOG_INFO, ("fsm_rtermack(%s): state=%d (%s)\n", 
+        PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+  
+  switch (f->state) {
+    case LS_CLOSING:
+      UNTIMEOUT(fsm_timeout, f);
+      f->state = LS_CLOSED;
+      if( f->callbacks->finished ) {
+        (*f->callbacks->finished)(f);
+      }
+      break;
+
+    case LS_STOPPING:
+      UNTIMEOUT(fsm_timeout, f);
+      f->state = LS_STOPPED;
+      if( f->callbacks->finished ) {
+        (*f->callbacks->finished)(f);
+      }
+      break;
+    
+    case LS_ACKRCVD:
+      f->state = LS_REQSENT;
+      break;
+    
+    case LS_OPENED:
+      if (f->callbacks->down) {
+        (*f->callbacks->down)(f);  /* Inform upper layers */
+      }
+      fsm_sconfreq(f, 0);
+      break;
+    default:
+      FSMDEBUG(LOG_INFO, ("fsm_rtermack(%s): UNHANDLED state=%d (%s)!!!\n", 
+                PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+  }
+}
+
+
+/*
+ * fsm_rcoderej - Receive an Code-Reject.
+ */
+static void
+fsm_rcoderej(fsm *f, u_char *inp, int len)
+{
+  u_char code, id;
+  
+  FSMDEBUG(LOG_INFO, ("fsm_rcoderej(%s): state=%d (%s)\n", 
+        PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+  
+  if (len < HEADERLEN) {
+    FSMDEBUG(LOG_INFO, ("fsm_rcoderej: Rcvd short Code-Reject packet!\n"));
+    return;
+  }
+  GETCHAR(code, inp);
+  GETCHAR(id, inp);
+  FSMDEBUG(LOG_WARNING, ("%s: Rcvd Code-Reject for code %d, id %d\n",
+        PROTO_NAME(f), code, id));
+  
+  if( f->state == LS_ACKRCVD ) {
+    f->state = LS_REQSENT;
+  }
+}
+
+
+/*
+ * fsm_protreject - Peer doesn't speak this protocol.
+ *
+ * Treat this as a catastrophic error (RXJ-).
+ */
+void
+fsm_protreject(fsm *f)
+{
+  switch( f->state ) {
+    case LS_CLOSING:
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      /* fall through */
+    case LS_CLOSED:
+      f->state = LS_CLOSED;
+      if( f->callbacks->finished ) {
+        (*f->callbacks->finished)(f);
+      }
+      break;
+
+    case LS_STOPPING:
+    case LS_REQSENT:
+    case LS_ACKRCVD:
+    case LS_ACKSENT:
+      UNTIMEOUT(fsm_timeout, f);  /* Cancel timeout */
+      /* fall through */
+    case LS_STOPPED:
+      f->state = LS_STOPPED;
+      if( f->callbacks->finished ) {
+        (*f->callbacks->finished)(f);
+      }
+      break;
+    
+    case LS_OPENED:
+      if( f->callbacks->down ) {
+        (*f->callbacks->down)(f);
+      }
+      /* Init restart counter, send Terminate-Request */
+      f->retransmits = f->maxtermtransmits;
+      fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+            (u_char *) f->term_reason, f->term_reason_len);
+      TIMEOUT(fsm_timeout, f, f->timeouttime);
+      --f->retransmits;
+
+      f->state = LS_STOPPING;
+      break;
+    
+    default:
+      FSMDEBUG(LOG_INFO, ("%s: Protocol-reject event in state %d (%s)!\n",
+            PROTO_NAME(f), f->state, ppperr_strerr[f->state]));
+    }
+}
+
+
+/*
+ * fsm_sconfreq - Send a Configure-Request.
+ */
+static void
+fsm_sconfreq(fsm *f, int retransmit)
+{
+  u_char *outp;
+  int cilen;
+  
+  if( f->state != LS_REQSENT && f->state != LS_ACKRCVD && f->state != LS_ACKSENT ) {
+    /* Not currently negotiating - reset options */
+    if( f->callbacks->resetci ) {
+      (*f->callbacks->resetci)(f);
+    }
+    f->nakloops = 0;
+  }
+  
+  if( !retransmit ) {
+    /* New request - reset retransmission counter, use new ID */
+    f->retransmits = f->maxconfreqtransmits;
+    f->reqid = ++f->id;
+  }
+  
+  f->seen_ack = 0;
+  
+  /*
+   * Make up the request packet
+   */
+  outp = outpacket_buf[f->unit] + PPP_HDRLEN + HEADERLEN;
+  if( f->callbacks->cilen && f->callbacks->addci ) {
+    cilen = (*f->callbacks->cilen)(f);
+    if( cilen > peer_mru[f->unit] - (int)HEADERLEN ) {
+      cilen = peer_mru[f->unit] - HEADERLEN;
+    }
+    if (f->callbacks->addci) {
+      (*f->callbacks->addci)(f, outp, &cilen);
+    }
+  } else {
+    cilen = 0;
+  }
+
+  /* send the request to our peer */
+  fsm_sdata(f, CONFREQ, f->reqid, outp, cilen);
+  
+  /* start the retransmit timer */
+  --f->retransmits;
+  TIMEOUT(fsm_timeout, f, f->timeouttime);
+  
+  FSMDEBUG(LOG_INFO, ("%s: sending Configure-Request, id %d\n",
+        PROTO_NAME(f), f->reqid));
+}
+
+
+/*
+ * fsm_sdata - Send some data.
+ *
+ * Used for all packets sent to our peer by this module.
+ */
+void
+fsm_sdata( fsm *f, u_char code, u_char id, u_char *data, int datalen)
+{
+  u_char *outp;
+  int outlen;
+
+  /* Adjust length to be smaller than MTU */
+  outp = outpacket_buf[f->unit];
+  if (datalen > peer_mru[f->unit] - (int)HEADERLEN) {
+    datalen = peer_mru[f->unit] - HEADERLEN;
+  }
+  if (datalen && data != outp + PPP_HDRLEN + HEADERLEN) {
+    BCOPY(data, outp + PPP_HDRLEN + HEADERLEN, datalen);
+  }
+  outlen = datalen + HEADERLEN;
+  MAKEHEADER(outp, f->protocol);
+  PUTCHAR(code, outp);
+  PUTCHAR(id, outp);
+  PUTSHORT(outlen, outp);
+  pppWrite(f->unit, outpacket_buf[f->unit], outlen + PPP_HDRLEN);
+  FSMDEBUG(LOG_INFO, ("fsm_sdata(%s): Sent code %d,%d,%d.\n",
+        PROTO_NAME(f), code, id, outlen));
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/fsm.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/fsm.h
new file mode 100644
index 0000000..8d41b5f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/fsm.h
@@ -0,0 +1,157 @@
+/*****************************************************************************
+* fsm.h - Network Control Protocol Finite State Machine header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*   Original based on BSD code.
+*****************************************************************************/
+/*
+ * fsm.h - {Link, IP} Control Protocol Finite State Machine definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: fsm.h,v 1.5 2009/12/31 17:08:08 goldsimon Exp $
+ */
+
+#ifndef FSM_H
+#define FSM_H
+
+/*
+ * LCP Packet header = Code, id, length.
+ */
+#define HEADERLEN (sizeof (u_char) + sizeof (u_char) + sizeof (u_short))
+
+
+/*
+ *  CP (LCP, IPCP, etc.) codes.
+ */
+#define CONFREQ     1 /* Configuration Request */
+#define CONFACK     2 /* Configuration Ack */
+#define CONFNAK     3 /* Configuration Nak */
+#define CONFREJ     4 /* Configuration Reject */
+#define TERMREQ     5 /* Termination Request */
+#define TERMACK     6 /* Termination Ack */
+#define CODEREJ     7 /* Code Reject */
+
+
+/*
+ * Each FSM is described by an fsm structure and fsm callbacks.
+ */
+typedef struct fsm {
+  int unit;                        /* Interface unit number */
+  u_short protocol;                /* Data Link Layer Protocol field value */
+  int state;                       /* State */
+  int flags;                       /* Contains option bits */
+  u_char id;                       /* Current id */
+  u_char reqid;                    /* Current request id */
+  u_char seen_ack;                 /* Have received valid Ack/Nak/Rej to Req */
+  int timeouttime;                 /* Timeout time in milliseconds */
+  int maxconfreqtransmits;         /* Maximum Configure-Request transmissions */
+  int retransmits;                 /* Number of retransmissions left */
+  int maxtermtransmits;            /* Maximum Terminate-Request transmissions */
+  int nakloops;                    /* Number of nak loops since last ack */
+  int maxnakloops;                 /* Maximum number of nak loops tolerated */
+  struct fsm_callbacks* callbacks; /* Callback routines */
+  char* term_reason;               /* Reason for closing protocol */
+  int term_reason_len;             /* Length of term_reason */
+} fsm;
+
+
+typedef struct fsm_callbacks {
+  void (*resetci)(fsm*);                            /* Reset our Configuration Information */
+  int  (*cilen)(fsm*);                              /* Length of our Configuration Information */
+  void (*addci)(fsm*, u_char*, int*);               /* Add our Configuration Information */
+  int  (*ackci)(fsm*, u_char*, int);                /* ACK our Configuration Information */
+  int  (*nakci)(fsm*, u_char*, int);                /* NAK our Configuration Information */
+  int  (*rejci)(fsm*, u_char*, int);                /* Reject our Configuration Information */
+  int  (*reqci)(fsm*, u_char*, int*, int);          /* Request peer's Configuration Information */
+  void (*up)(fsm*);                                 /* Called when fsm reaches LS_OPENED state */
+  void (*down)(fsm*);                               /* Called when fsm leaves LS_OPENED state */
+  void (*starting)(fsm*);                           /* Called when we want the lower layer */
+  void (*finished)(fsm*);                           /* Called when we don't want the lower layer */
+  void (*protreject)(int);                          /* Called when Protocol-Reject received */
+  void (*retransmit)(fsm*);                         /* Retransmission is necessary */
+  int  (*extcode)(fsm*, int, u_char, u_char*, int); /* Called when unknown code received */
+  char *proto_name;                                 /* String name for protocol (for messages) */
+} fsm_callbacks;
+
+
+/*
+ * Link states.
+ */
+#define LS_INITIAL  0 /* Down, hasn't been opened */
+#define LS_STARTING 1 /* Down, been opened */
+#define LS_CLOSED   2 /* Up, hasn't been opened */
+#define LS_STOPPED  3 /* Open, waiting for down event */
+#define LS_CLOSING  4 /* Terminating the connection, not open */
+#define LS_STOPPING 5 /* Terminating, but open */
+#define LS_REQSENT  6 /* We've sent a Config Request */
+#define LS_ACKRCVD  7 /* We've received a Config Ack */
+#define LS_ACKSENT  8 /* We've sent a Config Ack */
+#define LS_OPENED   9 /* Connection available */
+
+/*
+ * Flags - indicate options controlling FSM operation
+ */
+#define OPT_PASSIVE 1 /* Don't die if we don't get a response */
+#define OPT_RESTART 2 /* Treat 2nd OPEN as DOWN, UP */
+#define OPT_SILENT  4 /* Wait for peer to speak first */
+
+
+/*
+ * Prototypes
+ */
+void fsm_init (fsm*);
+void fsm_lowerup (fsm*);
+void fsm_lowerdown (fsm*);
+void fsm_open (fsm*);
+void fsm_close (fsm*, char*);
+void fsm_input (fsm*, u_char*, int);
+void fsm_protreject (fsm*);
+void fsm_sdata (fsm*, u_char, u_char, u_char*, int);
+
+
+/*
+ * Variables
+ */
+extern int peer_mru[]; /* currently negotiated peer MRU (per unit) */
+
+#endif /* FSM_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/ipcp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/ipcp.c
new file mode 100644
index 0000000..461a600
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/ipcp.c
@@ -0,0 +1,1411 @@
+/** In contrast to pppd 2.3.1, DNS support has been added, proxy-ARP and
+    dial-on-demand has been stripped. */
+/*****************************************************************************
+* ipcp.c - Network PPP IP Control Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-08 Guy Lancaster , Global Election Systems Inc.
+*   Original.
+*****************************************************************************/
+/*
+ * ipcp.c - PPP IP Control Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "auth.h"
+#include "fsm.h"
+#include "vj.h"
+#include "ipcp.h"
+
+#include "lwip/inet.h"
+
+#include 
+
+/* #define OLD_CI_ADDRS 1 */ /* Support deprecated address negotiation. */
+
+/* global vars */
+ipcp_options ipcp_wantoptions[NUM_PPP];  /* Options that we want to request */
+ipcp_options ipcp_gotoptions[NUM_PPP];   /* Options that peer ack'd */
+ipcp_options ipcp_allowoptions[NUM_PPP]; /* Options we allow peer to request */
+ipcp_options ipcp_hisoptions[NUM_PPP];   /* Options that we ack'd */
+
+/* local vars */
+static int default_route_set[NUM_PPP]; /* Have set up a default route */
+static int cis_received[NUM_PPP];      /* # Conf-Reqs received */
+
+
+/*
+ * Callbacks for fsm code.  (CI = Configuration Information)
+ */
+static void ipcp_resetci (fsm *);                     /* Reset our CI */
+static int  ipcp_cilen (fsm *);                       /* Return length of our CI */
+static void ipcp_addci (fsm *, u_char *, int *);      /* Add our CI */
+static int  ipcp_ackci (fsm *, u_char *, int);        /* Peer ack'd our CI */
+static int  ipcp_nakci (fsm *, u_char *, int);        /* Peer nak'd our CI */
+static int  ipcp_rejci (fsm *, u_char *, int);        /* Peer rej'd our CI */
+static int  ipcp_reqci (fsm *, u_char *, int *, int); /* Rcv CI */
+static void ipcp_up (fsm *);                          /* We're UP */
+static void ipcp_down (fsm *);                        /* We're DOWN */
+#if PPP_ADDITIONAL_CALLBACKS
+static void ipcp_script (fsm *, char *); /* Run an up/down script */
+#endif
+static void ipcp_finished (fsm *);                    /* Don't need lower layer */
+
+
+fsm ipcp_fsm[NUM_PPP]; /* IPCP fsm structure */
+
+
+static fsm_callbacks ipcp_callbacks = { /* IPCP callback routines */
+  ipcp_resetci,  /* Reset our Configuration Information */
+  ipcp_cilen,    /* Length of our Configuration Information */
+  ipcp_addci,    /* Add our Configuration Information */
+  ipcp_ackci,    /* ACK our Configuration Information */
+  ipcp_nakci,    /* NAK our Configuration Information */
+  ipcp_rejci,    /* Reject our Configuration Information */
+  ipcp_reqci,    /* Request peer's Configuration Information */
+  ipcp_up,       /* Called when fsm reaches LS_OPENED state */
+  ipcp_down,     /* Called when fsm leaves LS_OPENED state */
+  NULL,          /* Called when we want the lower layer up */
+  ipcp_finished, /* Called when we want the lower layer down */
+  NULL,          /* Called when Protocol-Reject received */
+  NULL,          /* Retransmission is necessary */
+  NULL,          /* Called to handle protocol-specific codes */
+  "IPCP"         /* String name of protocol */
+};
+
+/*
+ * Protocol entry points from main code.
+ */
+static void ipcp_init (int);
+static void ipcp_open (int);
+static void ipcp_close (int, char *);
+static void ipcp_lowerup (int);
+static void ipcp_lowerdown (int);
+static void ipcp_input (int, u_char *, int);
+static void ipcp_protrej (int);
+
+
+struct protent ipcp_protent = {
+  PPP_IPCP,
+  ipcp_init,
+  ipcp_input,
+  ipcp_protrej,
+  ipcp_lowerup,
+  ipcp_lowerdown,
+  ipcp_open,
+  ipcp_close,
+#if PPP_ADDITIONAL_CALLBACKS
+  ipcp_printpkt,
+  NULL,
+#endif /* PPP_ADDITIONAL_CALLBACKS */
+  1,
+  "IPCP",
+#if PPP_ADDITIONAL_CALLBACKS
+  ip_check_options,
+  NULL,
+  ip_active_pkt
+#endif /* PPP_ADDITIONAL_CALLBACKS */
+};
+
+static void ipcp_clear_addrs (int);
+
+/*
+ * Lengths of configuration options.
+ */
+#define CILEN_VOID     2
+#define CILEN_COMPRESS 4  /* min length for compression protocol opt. */
+#define CILEN_VJ       6  /* length for RFC1332 Van-Jacobson opt. */
+#define CILEN_ADDR     6  /* new-style single address option */
+#define CILEN_ADDRS    10 /* old-style dual address option */
+
+
+#define CODENAME(x) ((x) == CONFACK ? "ACK" : \
+                     (x) == CONFNAK ? "NAK" : "REJ")
+
+
+/*
+ * ipcp_init - Initialize IPCP.
+ */
+static void
+ipcp_init(int unit)
+{
+  fsm           *f = &ipcp_fsm[unit];
+  ipcp_options *wo = &ipcp_wantoptions[unit];
+  ipcp_options *ao = &ipcp_allowoptions[unit];
+
+  f->unit      = unit;
+  f->protocol  = PPP_IPCP;
+  f->callbacks = &ipcp_callbacks;
+  fsm_init(&ipcp_fsm[unit]);
+
+  memset(wo, 0, sizeof(*wo));
+  memset(ao, 0, sizeof(*ao));
+
+  wo->neg_addr      = 1;
+  wo->ouraddr       = 0;
+#if VJ_SUPPORT
+  wo->neg_vj        = 1;
+#else  /* VJ_SUPPORT */
+  wo->neg_vj        = 0;
+#endif /* VJ_SUPPORT */
+  wo->vj_protocol   = IPCP_VJ_COMP;
+  wo->maxslotindex  = MAX_SLOTS - 1;
+  wo->cflag         = 0;
+  wo->default_route = 1;
+
+  ao->neg_addr      = 1;
+#if VJ_SUPPORT
+  ao->neg_vj        = 1;
+#else  /* VJ_SUPPORT */
+  ao->neg_vj        = 0;
+#endif /* VJ_SUPPORT */
+  ao->maxslotindex  = MAX_SLOTS - 1;
+  ao->cflag         = 1;
+  ao->default_route = 1;
+}
+
+
+/*
+ * ipcp_open - IPCP is allowed to come up.
+ */
+static void
+ipcp_open(int unit)
+{
+  fsm_open(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_close - Take IPCP down.
+ */
+static void
+ipcp_close(int unit, char *reason)
+{
+  fsm_close(&ipcp_fsm[unit], reason);
+}
+
+
+/*
+ * ipcp_lowerup - The lower layer is up.
+ */
+static void
+ipcp_lowerup(int unit)
+{
+  fsm_lowerup(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_lowerdown - The lower layer is down.
+ */
+static void
+ipcp_lowerdown(int unit)
+{
+  fsm_lowerdown(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_input - Input IPCP packet.
+ */
+static void
+ipcp_input(int unit, u_char *p, int len)
+{
+  fsm_input(&ipcp_fsm[unit], p, len);
+}
+
+
+/*
+ * ipcp_protrej - A Protocol-Reject was received for IPCP.
+ *
+ * Pretend the lower layer went down, so we shut up.
+ */
+static void
+ipcp_protrej(int unit)
+{
+  fsm_lowerdown(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_resetci - Reset our CI.
+ */
+static void
+ipcp_resetci(fsm *f)
+{
+  ipcp_options *wo = &ipcp_wantoptions[f->unit];
+  
+  wo->req_addr = wo->neg_addr && ipcp_allowoptions[f->unit].neg_addr;
+  if (wo->ouraddr == 0) {
+    wo->accept_local = 1;
+  }
+  if (wo->hisaddr == 0) {
+    wo->accept_remote = 1;
+  }
+  /* Request DNS addresses from the peer */
+  wo->req_dns1 = ppp_settings.usepeerdns;
+  wo->req_dns2 = ppp_settings.usepeerdns;
+  ipcp_gotoptions[f->unit] = *wo;
+  cis_received[f->unit] = 0;
+}
+
+
+/*
+ * ipcp_cilen - Return length of our CI.
+ */
+static int
+ipcp_cilen(fsm *f)
+{
+  ipcp_options *go = &ipcp_gotoptions[f->unit];
+  ipcp_options *wo = &ipcp_wantoptions[f->unit];
+  ipcp_options *ho = &ipcp_hisoptions[f->unit];
+
+#define LENCIVJ(neg, old)   (neg ? (old? CILEN_COMPRESS : CILEN_VJ) : 0)
+#define LENCIADDR(neg, old) (neg ? (old? CILEN_ADDRS : CILEN_ADDR) : 0)
+#define LENCIDNS(neg)       (neg ? (CILEN_ADDR) : 0)
+
+  /*
+   * First see if we want to change our options to the old
+   * forms because we have received old forms from the peer.
+   */
+  if (wo->neg_addr && !go->neg_addr && !go->old_addrs) {
+    /* use the old style of address negotiation */
+    go->neg_addr = 1;
+    go->old_addrs = 1;
+  }
+  if (wo->neg_vj && !go->neg_vj && !go->old_vj) {
+    /* try an older style of VJ negotiation */
+    if (cis_received[f->unit] == 0) {
+      /* keep trying the new style until we see some CI from the peer */
+      go->neg_vj = 1;
+    } else {
+      /* use the old style only if the peer did */
+      if (ho->neg_vj && ho->old_vj) {
+        go->neg_vj = 1;
+        go->old_vj = 1;
+        go->vj_protocol = ho->vj_protocol;
+      }
+    }
+  }
+
+  return (LENCIADDR(go->neg_addr, go->old_addrs) +
+          LENCIVJ(go->neg_vj, go->old_vj) +
+          LENCIDNS(go->req_dns1) +
+          LENCIDNS(go->req_dns2));
+}
+
+
+/*
+ * ipcp_addci - Add our desired CIs to a packet.
+ */
+static void
+ipcp_addci(fsm *f, u_char *ucp, int *lenp)
+{
+  ipcp_options *go = &ipcp_gotoptions[f->unit];
+  int len = *lenp;
+
+#define ADDCIVJ(opt, neg, val, old, maxslotindex, cflag) \
+  if (neg) { \
+    int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \
+    if (len >= vjlen) { \
+      PUTCHAR(opt, ucp); \
+      PUTCHAR(vjlen, ucp); \
+      PUTSHORT(val, ucp); \
+      if (!old) { \
+        PUTCHAR(maxslotindex, ucp); \
+        PUTCHAR(cflag, ucp); \
+      } \
+      len -= vjlen; \
+    } else { \
+      neg = 0; \
+    } \
+  }
+
+#define ADDCIADDR(opt, neg, old, val1, val2) \
+  if (neg) { \
+    int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \
+    if (len >= addrlen) { \
+      u32_t l; \
+      PUTCHAR(opt, ucp); \
+      PUTCHAR(addrlen, ucp); \
+      l = ntohl(val1); \
+      PUTLONG(l, ucp); \
+      if (old) { \
+        l = ntohl(val2); \
+        PUTLONG(l, ucp); \
+      } \
+      len -= addrlen; \
+    } else { \
+      neg = 0; \
+    } \
+  }
+
+#define ADDCIDNS(opt, neg, addr) \
+  if (neg) { \
+    if (len >= CILEN_ADDR) { \
+      u32_t l; \
+      PUTCHAR(opt, ucp); \
+      PUTCHAR(CILEN_ADDR, ucp); \
+      l = ntohl(addr); \
+      PUTLONG(l, ucp); \
+      len -= CILEN_ADDR; \
+    } else { \
+      neg = 0; \
+    } \
+  }
+
+  ADDCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr,
+      go->old_addrs, go->ouraddr, go->hisaddr);
+
+  ADDCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj,
+      go->maxslotindex, go->cflag);
+
+  ADDCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]);
+
+  ADDCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]);
+
+  *lenp -= len;
+}
+
+
+/*
+ * ipcp_ackci - Ack our CIs.
+ *
+ * Returns:
+ *  0 - Ack was bad.
+ *  1 - Ack was good.
+ */
+static int
+ipcp_ackci(fsm *f, u_char *p, int len)
+{
+  ipcp_options *go = &ipcp_gotoptions[f->unit];
+  u_short cilen, citype, cishort;
+  u32_t cilong;
+  u_char cimaxslotindex, cicflag;
+
+  /*
+   * CIs must be in exactly the same order that we sent...
+   * Check packet length and CI length at each step.
+   * If we find any deviations, then this packet is bad.
+   */
+
+#define ACKCIVJ(opt, neg, val, old, maxslotindex, cflag) \
+  if (neg) { \
+    int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \
+    if ((len -= vjlen) < 0) { \
+      goto bad; \
+    } \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != vjlen || \
+        citype != opt) { \
+      goto bad; \
+    } \
+    GETSHORT(cishort, p); \
+    if (cishort != val) { \
+      goto bad; \
+    } \
+    if (!old) { \
+      GETCHAR(cimaxslotindex, p); \
+      if (cimaxslotindex != maxslotindex) { \
+        goto bad; \
+      } \
+      GETCHAR(cicflag, p); \
+      if (cicflag != cflag) { \
+        goto bad; \
+      } \
+    } \
+  }
+  
+#define ACKCIADDR(opt, neg, old, val1, val2) \
+  if (neg) { \
+    int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \
+    u32_t l; \
+    if ((len -= addrlen) < 0) { \
+      goto bad; \
+    } \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != addrlen || \
+        citype != opt) { \
+      goto bad; \
+    } \
+    GETLONG(l, p); \
+    cilong = htonl(l); \
+    if (val1 != cilong) { \
+      goto bad; \
+    } \
+    if (old) { \
+      GETLONG(l, p); \
+      cilong = htonl(l); \
+      if (val2 != cilong) { \
+        goto bad; \
+      } \
+    } \
+  }
+
+#define ACKCIDNS(opt, neg, addr) \
+  if (neg) { \
+    u32_t l; \
+    if ((len -= CILEN_ADDR) < 0) { \
+      goto bad; \
+    } \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != CILEN_ADDR || \
+        citype != opt) { \
+      goto bad; \
+    } \
+    GETLONG(l, p); \
+    cilong = htonl(l); \
+    if (addr != cilong) { \
+      goto bad; \
+    } \
+  }
+
+  ACKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr,
+        go->old_addrs, go->ouraddr, go->hisaddr);
+
+  ACKCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj,
+      go->maxslotindex, go->cflag);
+
+  ACKCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]);
+
+  ACKCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]);
+
+  /*
+   * If there are any remaining CIs, then this packet is bad.
+   */
+  if (len != 0) {
+    goto bad;
+  }
+  return (1);
+
+bad:
+  IPCPDEBUG(LOG_INFO, ("ipcp_ackci: received bad Ack!\n"));
+  return (0);
+}
+
+/*
+ * ipcp_nakci - Peer has sent a NAK for some of our CIs.
+ * This should not modify any state if the Nak is bad
+ * or if IPCP is in the LS_OPENED state.
+ *
+ * Returns:
+ *  0 - Nak was bad.
+ *  1 - Nak was good.
+ */
+static int
+ipcp_nakci(fsm *f, u_char *p, int len)
+{
+  ipcp_options *go = &ipcp_gotoptions[f->unit];
+  u_char cimaxslotindex, cicflag;
+  u_char citype, cilen, *next;
+  u_short cishort;
+  u32_t ciaddr1, ciaddr2, l, cidnsaddr;
+  ipcp_options no;    /* options we've seen Naks for */
+  ipcp_options try;    /* options to request next time */
+
+  BZERO(&no, sizeof(no));
+  try = *go;
+
+  /*
+   * Any Nak'd CIs must be in exactly the same order that we sent.
+   * Check packet length and CI length at each step.
+   * If we find any deviations, then this packet is bad.
+   */
+#define NAKCIADDR(opt, neg, old, code) \
+  if (go->neg && \
+      len >= (cilen = (old? CILEN_ADDRS: CILEN_ADDR)) && \
+      p[1] == cilen && \
+      p[0] == opt) { \
+    len -= cilen; \
+    INCPTR(2, p); \
+    GETLONG(l, p); \
+    ciaddr1 = htonl(l); \
+    if (old) { \
+      GETLONG(l, p); \
+      ciaddr2 = htonl(l); \
+      no.old_addrs = 1; \
+    } else { \
+      ciaddr2 = 0; \
+    } \
+    no.neg = 1; \
+    code \
+  }
+
+#define NAKCIVJ(opt, neg, code) \
+  if (go->neg && \
+      ((cilen = p[1]) == CILEN_COMPRESS || cilen == CILEN_VJ) && \
+      len >= cilen && \
+      p[0] == opt) { \
+    len -= cilen; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    no.neg = 1; \
+    code \
+  }
+  
+#define NAKCIDNS(opt, neg, code) \
+  if (go->neg && \
+      ((cilen = p[1]) == CILEN_ADDR) && \
+      len >= cilen && \
+      p[0] == opt) { \
+    len -= cilen; \
+    INCPTR(2, p); \
+    GETLONG(l, p); \
+    cidnsaddr = htonl(l); \
+    no.neg = 1; \
+    code \
+  }
+
+  /*
+   * Accept the peer's idea of {our,his} address, if different
+   * from our idea, only if the accept_{local,remote} flag is set.
+   */
+  NAKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr, go->old_addrs,
+    if (go->accept_local && ciaddr1) { /* Do we know our address? */
+      try.ouraddr = ciaddr1;
+      IPCPDEBUG(LOG_INFO, ("local IP address %s\n",
+           inet_ntoa(ciaddr1)));
+    }
+    if (go->accept_remote && ciaddr2) { /* Does he know his? */
+      try.hisaddr = ciaddr2;
+      IPCPDEBUG(LOG_INFO, ("remote IP address %s\n",
+           inet_ntoa(ciaddr2)));
+    }
+  );
+
+  /*
+   * Accept the peer's value of maxslotindex provided that it
+   * is less than what we asked for.  Turn off slot-ID compression
+   * if the peer wants.  Send old-style compress-type option if
+   * the peer wants.
+   */
+  NAKCIVJ(CI_COMPRESSTYPE, neg_vj,
+    if (cilen == CILEN_VJ) {
+      GETCHAR(cimaxslotindex, p);
+      GETCHAR(cicflag, p);
+      if (cishort == IPCP_VJ_COMP) {
+        try.old_vj = 0;
+        if (cimaxslotindex < go->maxslotindex) {
+          try.maxslotindex = cimaxslotindex;
+        }
+        if (!cicflag) {
+          try.cflag = 0;
+        }
+      } else {
+        try.neg_vj = 0;
+      }
+    } else {
+      if (cishort == IPCP_VJ_COMP || cishort == IPCP_VJ_COMP_OLD) {
+        try.old_vj = 1;
+        try.vj_protocol = cishort;
+      } else {
+        try.neg_vj = 0;
+      }
+    }
+  );
+
+  NAKCIDNS(CI_MS_DNS1, req_dns1,
+      try.dnsaddr[0] = cidnsaddr;
+        IPCPDEBUG(LOG_INFO, ("primary DNS address %s\n", inet_ntoa(cidnsaddr)));
+      );
+
+  NAKCIDNS(CI_MS_DNS2, req_dns2,
+      try.dnsaddr[1] = cidnsaddr;
+        IPCPDEBUG(LOG_INFO, ("secondary DNS address %s\n", inet_ntoa(cidnsaddr)));
+      );
+
+  /*
+  * There may be remaining CIs, if the peer is requesting negotiation
+  * on an option that we didn't include in our request packet.
+  * If they want to negotiate about IP addresses, we comply.
+  * If they want us to ask for compression, we refuse.
+  */
+  while (len > CILEN_VOID) {
+    GETCHAR(citype, p);
+    GETCHAR(cilen, p);
+    if( (len -= cilen) < 0 ) {
+      goto bad;
+    }
+    next = p + cilen - 2;
+
+    switch (citype) {
+      case CI_COMPRESSTYPE:
+        if (go->neg_vj || no.neg_vj ||
+            (cilen != CILEN_VJ && cilen != CILEN_COMPRESS)) {
+          goto bad;
+        }
+        no.neg_vj = 1;
+        break;
+      case CI_ADDRS:
+        if ((go->neg_addr && go->old_addrs) || no.old_addrs
+            || cilen != CILEN_ADDRS) {
+          goto bad;
+        }
+        try.neg_addr = 1;
+        try.old_addrs = 1;
+        GETLONG(l, p);
+        ciaddr1 = htonl(l);
+        if (ciaddr1 && go->accept_local) {
+          try.ouraddr = ciaddr1;
+        }
+        GETLONG(l, p);
+        ciaddr2 = htonl(l);
+        if (ciaddr2 && go->accept_remote) {
+          try.hisaddr = ciaddr2;
+        }
+        no.old_addrs = 1;
+        break;
+      case CI_ADDR:
+        if (go->neg_addr || no.neg_addr || cilen != CILEN_ADDR) {
+          goto bad;
+        }
+        try.old_addrs = 0;
+        GETLONG(l, p);
+        ciaddr1 = htonl(l);
+        if (ciaddr1 && go->accept_local) {
+          try.ouraddr = ciaddr1;
+        }
+        if (try.ouraddr != 0) {
+          try.neg_addr = 1;
+        }
+        no.neg_addr = 1;
+        break;
+    }
+    p = next;
+  }
+
+  /* If there is still anything left, this packet is bad. */
+  if (len != 0) {
+    goto bad;
+  }
+
+  /*
+   * OK, the Nak is good.  Now we can update state.
+   */
+  if (f->state != LS_OPENED) {
+    *go = try;
+  }
+
+  return 1;
+
+bad:
+  IPCPDEBUG(LOG_INFO, ("ipcp_nakci: received bad Nak!\n"));
+  return 0;
+}
+
+
+/*
+ * ipcp_rejci - Reject some of our CIs.
+ */
+static int
+ipcp_rejci(fsm *f, u_char *p, int len)
+{
+  ipcp_options *go = &ipcp_gotoptions[f->unit];
+  u_char cimaxslotindex, ciflag, cilen;
+  u_short cishort;
+  u32_t cilong;
+  ipcp_options try;    /* options to request next time */
+
+  try = *go;
+  /*
+   * Any Rejected CIs must be in exactly the same order that we sent.
+   * Check packet length and CI length at each step.
+   * If we find any deviations, then this packet is bad.
+   */
+#define REJCIADDR(opt, neg, old, val1, val2) \
+  if (go->neg && \
+      len >= (cilen = old? CILEN_ADDRS: CILEN_ADDR) && \
+      p[1] == cilen && \
+      p[0] == opt) { \
+    u32_t l; \
+    len -= cilen; \
+    INCPTR(2, p); \
+    GETLONG(l, p); \
+    cilong = htonl(l); \
+    /* Check rejected value. */ \
+    if (cilong != val1) { \
+      goto bad; \
+    } \
+    if (old) { \
+      GETLONG(l, p); \
+      cilong = htonl(l); \
+      /* Check rejected value. */ \
+      if (cilong != val2) { \
+        goto bad; \
+      } \
+    } \
+    try.neg = 0; \
+  }
+
+#define REJCIVJ(opt, neg, val, old, maxslot, cflag) \
+  if (go->neg && \
+      p[1] == (old? CILEN_COMPRESS : CILEN_VJ) && \
+      len >= p[1] && \
+      p[0] == opt) { \
+    len -= p[1]; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    /* Check rejected value. */  \
+    if (cishort != val) { \
+      goto bad; \
+    } \
+    if (!old) { \
+      GETCHAR(cimaxslotindex, p); \
+      if (cimaxslotindex != maxslot) { \
+        goto bad; \
+      } \
+      GETCHAR(ciflag, p); \
+      if (ciflag != cflag) { \
+        goto bad; \
+      } \
+    } \
+    try.neg = 0; \
+  }
+
+#define REJCIDNS(opt, neg, dnsaddr) \
+  if (go->neg && \
+      ((cilen = p[1]) == CILEN_ADDR) && \
+      len >= cilen && \
+      p[0] == opt) { \
+    u32_t l; \
+    len -= cilen; \
+    INCPTR(2, p); \
+    GETLONG(l, p); \
+    cilong = htonl(l); \
+    /* Check rejected value. */ \
+    if (cilong != dnsaddr) { \
+      goto bad; \
+    } \
+    try.neg = 0; \
+  }
+
+  REJCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr,
+        go->old_addrs, go->ouraddr, go->hisaddr);
+
+  REJCIVJ(CI_COMPRESSTYPE, neg_vj, go->vj_protocol, go->old_vj,
+      go->maxslotindex, go->cflag);
+
+  REJCIDNS(CI_MS_DNS1, req_dns1, go->dnsaddr[0]);
+
+  REJCIDNS(CI_MS_DNS2, req_dns2, go->dnsaddr[1]);
+
+  /*
+   * If there are any remaining CIs, then this packet is bad.
+   */
+  if (len != 0) {
+    goto bad;
+  }
+  /*
+   * Now we can update state.
+   */
+  if (f->state != LS_OPENED) {
+    *go = try;
+  }
+  return 1;
+
+bad:
+  IPCPDEBUG(LOG_INFO, ("ipcp_rejci: received bad Reject!\n"));
+  return 0;
+}
+
+
+/*
+ * ipcp_reqci - Check the peer's requested CIs and send appropriate response.
+ *
+ * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified
+ * appropriately.  If reject_if_disagree is non-zero, doesn't return
+ * CONFNAK; returns CONFREJ if it can't return CONFACK.
+ */
+static int
+ipcp_reqci(fsm *f, u_char *inp/* Requested CIs */,int *len/* Length of requested CIs */,int reject_if_disagree)
+{
+  ipcp_options *wo = &ipcp_wantoptions[f->unit];
+  ipcp_options *ho = &ipcp_hisoptions[f->unit];
+  ipcp_options *ao = &ipcp_allowoptions[f->unit];
+#ifdef OLD_CI_ADDRS
+  ipcp_options *go = &ipcp_gotoptions[f->unit];
+#endif
+  u_char *cip, *next;     /* Pointer to current and next CIs */
+  u_short cilen, citype;  /* Parsed len, type */
+  u_short cishort;        /* Parsed short value */
+  u32_t tl, ciaddr1;      /* Parsed address values */
+#ifdef OLD_CI_ADDRS
+  u32_t ciaddr2;          /* Parsed address values */
+#endif
+  int rc = CONFACK;       /* Final packet return code */
+  int orc;                /* Individual option return code */
+  u_char *p;              /* Pointer to next char to parse */
+  u_char *ucp = inp;      /* Pointer to current output char */
+  int l = *len;           /* Length left */
+  u_char maxslotindex, cflag;
+  int d;
+
+  cis_received[f->unit] = 1;
+
+  /*
+   * Reset all his options.
+   */
+  BZERO(ho, sizeof(*ho));
+
+  /*
+   * Process all his options.
+   */
+  next = inp;
+  while (l) {
+    orc = CONFACK;       /* Assume success */
+    cip = p = next;      /* Remember begining of CI */
+    if (l < 2 ||         /* Not enough data for CI header or */
+        p[1] < 2 ||      /*  CI length too small or */
+        p[1] > l) {      /*  CI length too big? */
+      IPCPDEBUG(LOG_INFO, ("ipcp_reqci: bad CI length!\n"));
+      orc = CONFREJ;     /* Reject bad CI */
+      cilen = (u_short)l;/* Reject till end of packet */
+      l = 0;             /* Don't loop again */
+      goto endswitch;
+    }
+    GETCHAR(citype, p);  /* Parse CI type */
+    GETCHAR(cilen, p);   /* Parse CI length */
+    l -= cilen;          /* Adjust remaining length */
+    next += cilen;       /* Step to next CI */
+
+    switch (citype) {      /* Check CI type */
+#ifdef OLD_CI_ADDRS /* Need to save space... */
+      case CI_ADDRS:
+        IPCPDEBUG(LOG_INFO, ("ipcp_reqci: received ADDRS\n"));
+        if (!ao->neg_addr ||
+            cilen != CILEN_ADDRS) {  /* Check CI length */
+          orc = CONFREJ;    /* Reject CI */
+          break;
+        }
+
+        /*
+         * If he has no address, or if we both have his address but
+         * disagree about it, then NAK it with our idea.
+         * In particular, if we don't know his address, but he does,
+         * then accept it.
+         */
+        GETLONG(tl, p);    /* Parse source address (his) */
+        ciaddr1 = htonl(tl);
+        IPCPDEBUG(LOG_INFO, ("his addr %s\n", inet_ntoa(ciaddr1)));
+        if (ciaddr1 != wo->hisaddr
+            && (ciaddr1 == 0 || !wo->accept_remote)) {
+          orc = CONFNAK;
+          if (!reject_if_disagree) {
+            DECPTR(sizeof(u32_t), p);
+            tl = ntohl(wo->hisaddr);
+            PUTLONG(tl, p);
+          }
+        } else if (ciaddr1 == 0 && wo->hisaddr == 0) {
+          /*
+           * If neither we nor he knows his address, reject the option.
+           */
+          orc = CONFREJ;
+          wo->req_addr = 0;  /* don't NAK with 0.0.0.0 later */
+          break;
+        }
+
+        /*
+         * If he doesn't know our address, or if we both have our address
+         * but disagree about it, then NAK it with our idea.
+         */
+        GETLONG(tl, p);    /* Parse desination address (ours) */
+        ciaddr2 = htonl(tl);
+        IPCPDEBUG(LOG_INFO, ("our addr %s\n", inet_ntoa(ciaddr2)));
+        if (ciaddr2 != wo->ouraddr) {
+          if (ciaddr2 == 0 || !wo->accept_local) {
+            orc = CONFNAK;
+            if (!reject_if_disagree) {
+              DECPTR(sizeof(u32_t), p);
+              tl = ntohl(wo->ouraddr);
+              PUTLONG(tl, p);
+            }
+          } else {
+            go->ouraddr = ciaddr2;  /* accept peer's idea */
+          }
+        }
+
+        ho->neg_addr = 1;
+        ho->old_addrs = 1;
+        ho->hisaddr = ciaddr1;
+        ho->ouraddr = ciaddr2;
+        break;
+#endif
+
+      case CI_ADDR:
+        if (!ao->neg_addr) {
+          IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Reject ADDR not allowed\n"));
+          orc = CONFREJ;        /* Reject CI */
+          break;
+        } else if (cilen != CILEN_ADDR) {  /* Check CI length */
+          IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Reject ADDR bad len\n"));
+          orc = CONFREJ;        /* Reject CI */
+          break;
+        }
+
+        /*
+         * If he has no address, or if we both have his address but
+         * disagree about it, then NAK it with our idea.
+         * In particular, if we don't know his address, but he does,
+         * then accept it.
+         */
+        GETLONG(tl, p);  /* Parse source address (his) */
+        ciaddr1 = htonl(tl);
+        if (ciaddr1 != wo->hisaddr
+            && (ciaddr1 == 0 || !wo->accept_remote)) {
+          orc = CONFNAK;
+          if (!reject_if_disagree) {
+            DECPTR(sizeof(u32_t), p);
+            tl = ntohl(wo->hisaddr);
+            PUTLONG(tl, p);
+          }
+          IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Nak ADDR %s\n", inet_ntoa(ciaddr1)));
+        } else if (ciaddr1 == 0 && wo->hisaddr == 0) {
+          /*
+           * Don't ACK an address of 0.0.0.0 - reject it instead.
+           */
+          IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Reject ADDR %s\n", inet_ntoa(ciaddr1)));
+          orc = CONFREJ;
+          wo->req_addr = 0;  /* don't NAK with 0.0.0.0 later */
+          break;
+        }
+
+        ho->neg_addr = 1;
+        ho->hisaddr = ciaddr1;
+        IPCPDEBUG(LOG_INFO, ("ipcp_reqci: ADDR %s\n", inet_ntoa(ciaddr1)));
+        break;
+
+      case CI_MS_DNS1:
+      case CI_MS_DNS2:
+        /* Microsoft primary or secondary DNS request */
+        d = citype == CI_MS_DNS2;
+
+        /* If we do not have a DNS address then we cannot send it */
+        if (ao->dnsaddr[d] == 0 ||
+            cilen != CILEN_ADDR) {  /* Check CI length */
+          IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Rejecting DNS%d Request\n", d+1));
+          orc = CONFREJ;        /* Reject CI */
+          break;
+        }
+        GETLONG(tl, p);
+        if (htonl(tl) != ao->dnsaddr[d]) {
+          IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Naking DNS%d Request %s\n",
+                d+1, inet_ntoa(tl)));
+          DECPTR(sizeof(u32_t), p);
+          tl = ntohl(ao->dnsaddr[d]);
+          PUTLONG(tl, p);
+          orc = CONFNAK;
+        }
+        IPCPDEBUG(LOG_INFO, ("ipcp_reqci: received DNS%d Request\n", d+1));
+        break;
+
+      case CI_MS_WINS1:
+      case CI_MS_WINS2:
+        /* Microsoft primary or secondary WINS request */
+        d = citype == CI_MS_WINS2;
+        IPCPDEBUG(LOG_INFO, ("ipcp_reqci: received WINS%d Request\n", d+1));
+
+        /* If we do not have a DNS address then we cannot send it */
+        if (ao->winsaddr[d] == 0 ||
+          cilen != CILEN_ADDR) {  /* Check CI length */
+          orc = CONFREJ;      /* Reject CI */
+          break;
+        }
+        GETLONG(tl, p);
+        if (htonl(tl) != ao->winsaddr[d]) {
+          DECPTR(sizeof(u32_t), p);
+          tl = ntohl(ao->winsaddr[d]);
+          PUTLONG(tl, p);
+          orc = CONFNAK;
+        }
+        break;
+
+      case CI_COMPRESSTYPE:
+        if (!ao->neg_vj) {
+          IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Rejecting COMPRESSTYPE not allowed\n"));
+          orc = CONFREJ;
+          break;
+        } else if (cilen != CILEN_VJ && cilen != CILEN_COMPRESS) {
+          IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Rejecting COMPRESSTYPE len=%d\n", cilen));
+          orc = CONFREJ;
+          break;
+        }
+        GETSHORT(cishort, p);
+
+        if (!(cishort == IPCP_VJ_COMP ||
+            (cishort == IPCP_VJ_COMP_OLD && cilen == CILEN_COMPRESS))) {
+          IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Rejecting COMPRESSTYPE %d\n", cishort));
+          orc = CONFREJ;
+          break;
+        }
+
+        ho->neg_vj = 1;
+        ho->vj_protocol = cishort;
+        if (cilen == CILEN_VJ) {
+          GETCHAR(maxslotindex, p);
+          if (maxslotindex > ao->maxslotindex) { 
+            IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Naking VJ max slot %d\n", maxslotindex));
+            orc = CONFNAK;
+            if (!reject_if_disagree) {
+              DECPTR(1, p);
+              PUTCHAR(ao->maxslotindex, p);
+            }
+          }
+          GETCHAR(cflag, p);
+          if (cflag && !ao->cflag) {
+            IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Naking VJ cflag %d\n", cflag));
+            orc = CONFNAK;
+            if (!reject_if_disagree) {
+              DECPTR(1, p);
+              PUTCHAR(wo->cflag, p);
+            }
+          }
+          ho->maxslotindex = maxslotindex;
+          ho->cflag = cflag;
+        } else {
+          ho->old_vj = 1;
+          ho->maxslotindex = MAX_SLOTS - 1;
+          ho->cflag = 1;
+        }
+        IPCPDEBUG(LOG_INFO, (
+              "ipcp_reqci: received COMPRESSTYPE p=%d old=%d maxslot=%d cflag=%d\n",
+              ho->vj_protocol, ho->old_vj, ho->maxslotindex, ho->cflag));
+        break;
+
+      default:
+        IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Rejecting unknown CI type %d\n", citype));
+        orc = CONFREJ;
+        break;
+    }
+
+endswitch:
+    if (orc == CONFACK &&    /* Good CI */
+        rc != CONFACK) {     /*  but prior CI wasnt? */
+      continue;              /* Don't send this one */
+    }
+
+    if (orc == CONFNAK) {    /* Nak this CI? */
+      if (reject_if_disagree) {  /* Getting fed up with sending NAKs? */
+        IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Rejecting too many naks\n"));
+        orc = CONFREJ;       /* Get tough if so */
+      } else {
+        if (rc == CONFREJ) { /* Rejecting prior CI? */
+          continue;          /* Don't send this one */
+        }
+        if (rc == CONFACK) { /* Ack'd all prior CIs? */
+          rc = CONFNAK;      /* Not anymore... */
+          ucp = inp;         /* Backup */
+        }
+      }
+    }
+
+    if (orc == CONFREJ &&    /* Reject this CI */
+        rc != CONFREJ) {  /*  but no prior ones? */
+      rc = CONFREJ;
+      ucp = inp;        /* Backup */
+    }
+    
+    /* Need to move CI? */
+    if (ucp != cip) {
+      BCOPY(cip, ucp, cilen);  /* Move it */
+    }
+
+    /* Update output pointer */
+    INCPTR(cilen, ucp);
+  }
+
+  /*
+   * If we aren't rejecting this packet, and we want to negotiate
+   * their address, and they didn't send their address, then we
+   * send a NAK with a CI_ADDR option appended.  We assume the
+   * input buffer is long enough that we can append the extra
+   * option safely.
+   */
+  if (rc != CONFREJ && !ho->neg_addr &&
+      wo->req_addr && !reject_if_disagree) {
+    IPCPDEBUG(LOG_INFO, ("ipcp_reqci: Requesting peer address\n"));
+    if (rc == CONFACK) {
+      rc = CONFNAK;
+      ucp = inp;        /* reset pointer */
+      wo->req_addr = 0;    /* don't ask again */
+    }
+    PUTCHAR(CI_ADDR, ucp);
+    PUTCHAR(CILEN_ADDR, ucp);
+    tl = ntohl(wo->hisaddr);
+    PUTLONG(tl, ucp);
+  }
+
+  *len = (int)(ucp - inp);    /* Compute output length */
+  IPCPDEBUG(LOG_INFO, ("ipcp_reqci: returning Configure-%s\n", CODENAME(rc)));
+  return (rc);      /* Return final code */
+}
+
+
+#if 0
+/*
+ * ip_check_options - check that any IP-related options are OK,
+ * and assign appropriate defaults.
+ */
+static void
+ip_check_options(u_long localAddr)
+{
+  ipcp_options *wo = &ipcp_wantoptions[0];
+
+  /*
+   * Load our default IP address but allow the remote host to give us
+   * a new address.
+   */
+  if (wo->ouraddr == 0 && !ppp_settings.disable_defaultip) {
+    wo->accept_local = 1;  /* don't insist on this default value */
+    wo->ouraddr = htonl(localAddr);
+  }
+}
+#endif
+
+
+/*
+ * ipcp_up - IPCP has come UP.
+ *
+ * Configure the IP network interface appropriately and bring it up.
+ */
+static void
+ipcp_up(fsm *f)
+{
+  u32_t mask;
+  ipcp_options *ho = &ipcp_hisoptions[f->unit];
+  ipcp_options *go = &ipcp_gotoptions[f->unit];
+  ipcp_options *wo = &ipcp_wantoptions[f->unit];
+
+  np_up(f->unit, PPP_IP);
+  IPCPDEBUG(LOG_INFO, ("ipcp: up\n"));
+
+  /*
+   * We must have a non-zero IP address for both ends of the link.
+   */
+  if (!ho->neg_addr) {
+    ho->hisaddr = wo->hisaddr;
+  }
+
+  if (ho->hisaddr == 0) {
+    IPCPDEBUG(LOG_ERR, ("Could not determine remote IP address\n"));
+    ipcp_close(f->unit, "Could not determine remote IP address");
+    return;
+  }
+  if (go->ouraddr == 0) {
+    IPCPDEBUG(LOG_ERR, ("Could not determine local IP address\n"));
+    ipcp_close(f->unit, "Could not determine local IP address");
+    return;
+  }
+
+  if (ppp_settings.usepeerdns && (go->dnsaddr[0] || go->dnsaddr[1])) {
+    /*pppGotDNSAddrs(go->dnsaddr[0], go->dnsaddr[1]);*/
+  }
+
+  /*
+   * Check that the peer is allowed to use the IP address it wants.
+   */
+  if (!auth_ip_addr(f->unit, ho->hisaddr)) {
+    IPCPDEBUG(LOG_ERR, ("Peer is not authorized to use remote address %s\n",
+        inet_ntoa(ho->hisaddr)));
+    ipcp_close(f->unit, "Unauthorized remote IP address");
+    return;
+  }
+
+  /* set tcp compression */
+  sifvjcomp(f->unit, ho->neg_vj, ho->cflag, ho->maxslotindex);
+
+  /*
+   * Set IP addresses and (if specified) netmask.
+   */
+  mask = GetMask(go->ouraddr);
+
+  if (!sifaddr(f->unit, go->ouraddr, ho->hisaddr, mask, go->dnsaddr[0], go->dnsaddr[1])) {
+    IPCPDEBUG(LOG_WARNING, ("sifaddr failed\n"));
+    ipcp_close(f->unit, "Interface configuration failed");
+    return;
+  }
+
+  /* bring the interface up for IP */
+  if (!sifup(f->unit)) {
+    IPCPDEBUG(LOG_WARNING, ("sifup failed\n"));
+    ipcp_close(f->unit, "Interface configuration failed");
+    return;
+  }
+
+  sifnpmode(f->unit, PPP_IP, NPMODE_PASS);
+
+  /* assign a default route through the interface if required */
+  if (ipcp_wantoptions[f->unit].default_route) {
+    if (sifdefaultroute(f->unit, go->ouraddr, ho->hisaddr)) {
+      default_route_set[f->unit] = 1;
+    }
+  }
+
+  IPCPDEBUG(LOG_NOTICE, ("local  IP address %s\n", inet_ntoa(go->ouraddr)));
+  IPCPDEBUG(LOG_NOTICE, ("remote IP address %s\n", inet_ntoa(ho->hisaddr)));
+  if (go->dnsaddr[0]) {
+    IPCPDEBUG(LOG_NOTICE, ("primary   DNS address %s\n", inet_ntoa(go->dnsaddr[0])));
+  }
+  if (go->dnsaddr[1]) {
+    IPCPDEBUG(LOG_NOTICE, ("secondary DNS address %s\n", inet_ntoa(go->dnsaddr[1])));
+  }
+}
+
+
+/*
+ * ipcp_down - IPCP has gone DOWN.
+ *
+ * Take the IP network interface down, clear its addresses
+ * and delete routes through it.
+ */
+static void
+ipcp_down(fsm *f)
+{
+  IPCPDEBUG(LOG_INFO, ("ipcp: down\n"));
+  np_down(f->unit, PPP_IP);
+  sifvjcomp(f->unit, 0, 0, 0);
+
+  sifdown(f->unit);
+  ipcp_clear_addrs(f->unit);
+}
+
+
+/*
+ * ipcp_clear_addrs() - clear the interface addresses, routes, etc.
+ */
+static void
+ipcp_clear_addrs(int unit)
+{
+  u32_t ouraddr, hisaddr;
+
+  ouraddr = ipcp_gotoptions[unit].ouraddr;
+  hisaddr = ipcp_hisoptions[unit].hisaddr;
+  if (default_route_set[unit]) {
+    cifdefaultroute(unit, ouraddr, hisaddr);
+    default_route_set[unit] = 0;
+  }
+  cifaddr(unit, ouraddr, hisaddr);
+}
+
+
+/*
+ * ipcp_finished - possibly shut down the lower layers.
+ */
+static void
+ipcp_finished(fsm *f)
+{
+  np_finished(f->unit, PPP_IP);
+}
+
+#if PPP_ADDITIONAL_CALLBACKS
+static int
+ipcp_printpkt(u_char *p, int plen, void (*printer) (void *, char *, ...), void *arg)
+{
+  LWIP_UNUSED_ARG(p);
+  LWIP_UNUSED_ARG(plen);
+  LWIP_UNUSED_ARG(printer);
+  LWIP_UNUSED_ARG(arg);
+  return 0;
+}
+
+/*
+ * ip_active_pkt - see if this IP packet is worth bringing the link up for.
+ * We don't bring the link up for IP fragments or for TCP FIN packets
+ * with no data.
+ */
+#define IP_HDRLEN   20  /* bytes */
+#define IP_OFFMASK  0x1fff
+#define IPPROTO_TCP 6
+#define TCP_HDRLEN  20
+#define TH_FIN      0x01
+
+/*
+ * We use these macros because the IP header may be at an odd address,
+ * and some compilers might use word loads to get th_off or ip_hl.
+ */
+
+#define net_short(x)    (((x)[0] << 8) + (x)[1])
+#define get_iphl(x)     (((unsigned char *)(x))[0] & 0xF)
+#define get_ipoff(x)    net_short((unsigned char *)(x) + 6)
+#define get_ipproto(x)  (((unsigned char *)(x))[9])
+#define get_tcpoff(x)   (((unsigned char *)(x))[12] >> 4)
+#define get_tcpflags(x) (((unsigned char *)(x))[13])
+
+static int
+ip_active_pkt(u_char *pkt, int len)
+{
+  u_char *tcp;
+  int hlen;
+
+  len -= PPP_HDRLEN;
+  pkt += PPP_HDRLEN;
+  if (len < IP_HDRLEN) {
+    return 0;
+  }
+  if ((get_ipoff(pkt) & IP_OFFMASK) != 0) {
+    return 0;
+  }
+  if (get_ipproto(pkt) != IPPROTO_TCP) {
+    return 1;
+  }
+  hlen = get_iphl(pkt) * 4;
+  if (len < hlen + TCP_HDRLEN) {
+    return 0;
+  }
+  tcp = pkt + hlen;
+  if ((get_tcpflags(tcp) & TH_FIN) != 0 && len == hlen + get_tcpoff(tcp) * 4) {
+    return 0;
+  }
+  return 1;
+}
+#endif /* PPP_ADDITIONAL_CALLBACKS */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/ipcp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/ipcp.h
new file mode 100644
index 0000000..de03f46
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/ipcp.h
@@ -0,0 +1,106 @@
+/*****************************************************************************
+* ipcp.h -  PPP IP NCP: Internet Protocol Network Control Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * ipcp.h - IP Control Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: ipcp.h,v 1.4 2010/01/18 20:49:43 goldsimon Exp $
+ */
+
+#ifndef IPCP_H
+#define IPCP_H
+
+/*
+ * Options.
+ */
+#define CI_ADDRS            1      /* IP Addresses */
+#define CI_COMPRESSTYPE     2      /* Compression Type */
+#define CI_ADDR             3
+
+#define CI_MS_DNS1          129    /* Primary DNS value */
+#define CI_MS_WINS1         128    /* Primary WINS value */
+#define CI_MS_DNS2          131    /* Secondary DNS value */
+#define CI_MS_WINS2         130    /* Secondary WINS value */
+
+#define IPCP_VJMODE_OLD     1      /* "old" mode (option # = 0x0037) */
+#define IPCP_VJMODE_RFC1172 2      /* "old-rfc"mode (option # = 0x002d) */
+#define IPCP_VJMODE_RFC1332 3      /* "new-rfc"mode (option # = 0x002d, */
+                                   /*  maxslot and slot number compression) */
+
+#define IPCP_VJ_COMP        0x002d /* current value for VJ compression option */
+#define IPCP_VJ_COMP_OLD    0x0037 /* "old" (i.e, broken) value for VJ */
+                                   /* compression option */ 
+
+typedef struct ipcp_options {
+  u_int   neg_addr      : 1; /* Negotiate IP Address? */
+  u_int   old_addrs     : 1; /* Use old (IP-Addresses) option? */
+  u_int   req_addr      : 1; /* Ask peer to send IP address? */
+  u_int   default_route : 1; /* Assign default route through interface? */
+  u_int   proxy_arp     : 1; /* Make proxy ARP entry for peer? */
+  u_int   neg_vj        : 1; /* Van Jacobson Compression? */
+  u_int   old_vj        : 1; /* use old (short) form of VJ option? */
+  u_int   accept_local  : 1; /* accept peer's value for ouraddr */
+  u_int   accept_remote : 1; /* accept peer's value for hisaddr */
+  u_int   req_dns1      : 1; /* Ask peer to send primary DNS address? */
+  u_int   req_dns2      : 1; /* Ask peer to send secondary DNS address? */
+  u_short vj_protocol;       /* protocol value to use in VJ option */
+  u_char  maxslotindex;      /* VJ slots - 1. */
+  u_char  cflag;             /* VJ slot compression flag. */
+  u32_t   ouraddr, hisaddr;  /* Addresses in NETWORK BYTE ORDER */
+  u32_t   dnsaddr[2];        /* Primary and secondary MS DNS entries */
+  u32_t   winsaddr[2];       /* Primary and secondary MS WINS entries */
+} ipcp_options;
+
+extern fsm ipcp_fsm[];
+extern ipcp_options ipcp_wantoptions[];
+extern ipcp_options ipcp_gotoptions[];
+extern ipcp_options ipcp_allowoptions[];
+extern ipcp_options ipcp_hisoptions[];
+
+extern struct protent ipcp_protent;
+
+#endif /* IPCP_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/lcp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/lcp.c
new file mode 100644
index 0000000..21c83ac
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/lcp.c
@@ -0,0 +1,2066 @@
+/*****************************************************************************
+* lcp.c - Network Link Control Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-01 Guy Lancaster , Global Election Systems Inc.
+*   Original.
+*****************************************************************************/
+
+/*
+ * lcp.c - PPP Link Control Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+ 
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "fsm.h"
+#include "chap.h"
+#include "magic.h"
+#include "auth.h"
+#include "lcp.h"
+
+#include 
+
+#if PPPOE_SUPPORT
+#include "netif/ppp_oe.h"
+#else
+#define PPPOE_MAXMTU PPP_MAXMRU
+#endif
+
+#if 0 /* UNUSED */
+/*
+ * LCP-related command-line options.
+ */
+int lcp_echo_interval = 0;  /* Interval between LCP echo-requests */
+int lcp_echo_fails = 0;     /* Tolerance to unanswered echo-requests */
+bool  lax_recv = 0;         /* accept control chars in asyncmap */
+
+static int setescape (char **);
+
+static option_t lcp_option_list[] = {
+    /* LCP options */
+    /* list stripped for simplicity */
+    {NULL}
+};
+#endif /* UNUSED */
+
+/* options */
+LinkPhase lcp_phase[NUM_PPP];          /* Phase of link session (RFC 1661) */
+static u_int lcp_echo_interval      = LCP_ECHOINTERVAL; /* Interval between LCP echo-requests */
+static u_int lcp_echo_fails         = LCP_MAXECHOFAILS; /* Tolerance to unanswered echo-requests */
+
+/* global vars */
+static fsm lcp_fsm[NUM_PPP];                            /* LCP fsm structure (global)*/
+lcp_options lcp_wantoptions[NUM_PPP];  /* Options that we want to request */
+lcp_options lcp_gotoptions[NUM_PPP];   /* Options that peer ack'd */
+lcp_options lcp_allowoptions[NUM_PPP]; /* Options we allow peer to request */
+lcp_options lcp_hisoptions[NUM_PPP];   /* Options that we ack'd */
+ext_accm xmit_accm[NUM_PPP];           /* extended transmit ACCM */
+
+static u32_t lcp_echos_pending      = 0;                /* Number of outstanding echo msgs */
+static u32_t lcp_echo_number        = 0;                /* ID number of next echo frame */
+static u32_t lcp_echo_timer_running = 0;                /* TRUE if a timer is running */
+
+/* @todo: do we really need such a large buffer? The typical 1500 bytes seem too much. */
+static u_char nak_buffer[PPP_MRU]; /* where we construct a nak packet */ 
+
+/*
+ * Callbacks for fsm code.  (CI = Configuration Information)
+ */
+static void lcp_resetci (fsm*);                   /* Reset our CI */
+static int  lcp_cilen (fsm*);                     /* Return length of our CI */
+static void lcp_addci (fsm*, u_char*, int*);      /* Add our CI to pkt */
+static int  lcp_ackci (fsm*, u_char*, int);       /* Peer ack'd our CI */
+static int  lcp_nakci (fsm*, u_char*, int);       /* Peer nak'd our CI */
+static int  lcp_rejci (fsm*, u_char*, int);       /* Peer rej'd our CI */
+static int  lcp_reqci (fsm*, u_char*, int*, int); /* Rcv peer CI */
+static void lcp_up (fsm*);                        /* We're UP */
+static void lcp_down (fsm*);                      /* We're DOWN */
+static void lcp_starting (fsm*);                  /* We need lower layer up */
+static void lcp_finished (fsm*);                  /* We need lower layer down */
+static int  lcp_extcode (fsm*, int, u_char, u_char*, int);
+static void lcp_rprotrej (fsm*, u_char*, int);
+
+/*
+ * routines to send LCP echos to peer
+ */
+
+static void lcp_echo_lowerup (int);
+static void lcp_echo_lowerdown (int);
+static void LcpEchoTimeout (void*);
+static void lcp_received_echo_reply (fsm*, int, u_char*, int);
+static void LcpSendEchoRequest (fsm*);
+static void LcpLinkFailure (fsm*);
+static void LcpEchoCheck (fsm*);
+
+static fsm_callbacks lcp_callbacks = { /* LCP callback routines */
+  lcp_resetci,  /* Reset our Configuration Information */
+  lcp_cilen,    /* Length of our Configuration Information */
+  lcp_addci,    /* Add our Configuration Information */
+  lcp_ackci,    /* ACK our Configuration Information */
+  lcp_nakci,    /* NAK our Configuration Information */
+  lcp_rejci,    /* Reject our Configuration Information */
+  lcp_reqci,    /* Request peer's Configuration Information */
+  lcp_up,       /* Called when fsm reaches LS_OPENED state */
+  lcp_down,     /* Called when fsm leaves LS_OPENED state */
+  lcp_starting, /* Called when we want the lower layer up */
+  lcp_finished, /* Called when we want the lower layer down */
+  NULL,         /* Called when Protocol-Reject received */
+  NULL,         /* Retransmission is necessary */
+  lcp_extcode,  /* Called to handle LCP-specific codes */
+  "LCP"         /* String name of protocol */
+};
+
+/*
+ * Protocol entry points.
+ * Some of these are called directly.
+ */
+
+static void lcp_input (int, u_char *, int);
+static void lcp_protrej (int);
+
+struct protent lcp_protent = {
+    PPP_LCP,
+    lcp_init,
+    lcp_input,
+    lcp_protrej,
+    lcp_lowerup,
+    lcp_lowerdown,
+    lcp_open,
+    lcp_close,
+#if PPP_ADDITIONAL_CALLBACKS
+    lcp_printpkt,
+    NULL,
+#endif /* PPP_ADDITIONAL_CALLBACKS */
+    1,
+    "LCP",
+#if PPP_ADDITIONAL_CALLBACKS
+    NULL,
+    NULL,
+    NULL
+#endif /* PPP_ADDITIONAL_CALLBACKS */
+};
+
+int lcp_loopbackfail = DEFLOOPBACKFAIL;
+
+/*
+ * Length of each type of configuration option (in octets)
+ */
+#define CILEN_VOID  2
+#define CILEN_CHAR  3
+#define CILEN_SHORT 4 /* CILEN_VOID + sizeof(short) */
+#define CILEN_CHAP  5 /* CILEN_VOID + sizeof(short) + 1 */
+#define CILEN_LONG  6 /* CILEN_VOID + sizeof(long) */
+#define CILEN_LQR   8 /* CILEN_VOID + sizeof(short) + sizeof(long) */
+#define CILEN_CBCP  3
+
+#define CODENAME(x)  ((x) == CONFACK ? "ACK" : (x) == CONFNAK ? "NAK" : "REJ")
+
+#if 0 /* UNUSED */
+/*
+ * setescape - add chars to the set we escape on transmission.
+ */
+static int
+setescape(argv)
+    char **argv;
+{
+    int n, ret;
+    char *p, *endp;
+
+    p = *argv;
+    ret = 1;
+    while (*p) {
+      n = strtol(p, &endp, 16);
+      if (p == endp) {
+        option_error("escape parameter contains invalid hex number '%s'", p);
+        return 0;
+      }
+      p = endp;
+      if (n < 0 || n == 0x5E || n > 0xFF) {
+        option_error("can't escape character 0x%x", n);
+        ret = 0;
+      } else
+        xmit_accm[0][n >> 5] |= 1 << (n & 0x1F);
+      while (*p == ',' || *p == ' ')
+        ++p;
+    }
+    return ret;
+}
+#endif /* UNUSED */
+
+/*
+ * lcp_init - Initialize LCP.
+ */
+void
+lcp_init(int unit)
+{
+  fsm         *f  = &lcp_fsm[unit];
+  lcp_options *wo = &lcp_wantoptions[unit];
+  lcp_options *ao = &lcp_allowoptions[unit];
+
+  f->unit      = unit;
+  f->protocol  = PPP_LCP;
+  f->callbacks = &lcp_callbacks;
+
+  fsm_init(f);
+
+  wo->passive           = 0;
+  wo->silent            = 0;
+  wo->restart           = 0;               /* Set to 1 in kernels or multi-line implementations */
+  wo->neg_mru           = 1;
+  wo->mru               = PPP_DEFMRU;
+  wo->neg_asyncmap      = 1;
+  wo->asyncmap          = 0x00000000l;     /* Assume don't need to escape any ctl chars. */
+  wo->neg_chap          = 0;               /* Set to 1 on server */
+  wo->neg_upap          = 0;               /* Set to 1 on server */
+  wo->chap_mdtype       = CHAP_DIGEST_MD5;
+  wo->neg_magicnumber   = 1;
+  wo->neg_pcompression  = 1;
+  wo->neg_accompression = 1;
+  wo->neg_lqr           = 0;               /* no LQR implementation yet */
+  wo->neg_cbcp          = 0;
+
+  ao->neg_mru           = 1;
+  ao->mru               = PPP_MAXMRU;
+  ao->neg_asyncmap      = 1;
+  ao->asyncmap          = 0x00000000l;     /* Assume don't need to escape any ctl chars. */
+  ao->neg_chap          = (CHAP_SUPPORT != 0);
+  ao->chap_mdtype       = CHAP_DIGEST_MD5;
+  ao->neg_upap          = (PAP_SUPPORT != 0);
+  ao->neg_magicnumber   = 1;
+  ao->neg_pcompression  = 1;
+  ao->neg_accompression = 1;
+  ao->neg_lqr           = 0;               /* no LQR implementation yet */
+  ao->neg_cbcp          = (CBCP_SUPPORT != 0);
+
+  /* 
+   * Set transmit escape for the flag and escape characters plus anything
+   * set for the allowable options.
+   */
+  memset(xmit_accm[unit], 0, sizeof(xmit_accm[0]));
+  xmit_accm[unit][15] = 0x60;
+  xmit_accm[unit][0]  = (u_char)((ao->asyncmap        & 0xFF));
+  xmit_accm[unit][1]  = (u_char)((ao->asyncmap >> 8)  & 0xFF);
+  xmit_accm[unit][2]  = (u_char)((ao->asyncmap >> 16) & 0xFF);
+  xmit_accm[unit][3]  = (u_char)((ao->asyncmap >> 24) & 0xFF);
+  LCPDEBUG(LOG_INFO, ("lcp_init: xmit_accm=%X %X %X %X\n",
+        xmit_accm[unit][0],
+        xmit_accm[unit][1],
+        xmit_accm[unit][2],
+        xmit_accm[unit][3]));
+  
+  lcp_phase[unit] = PHASE_INITIALIZE;
+}
+
+
+/*
+ * lcp_open - LCP is allowed to come up.
+ */
+void
+lcp_open(int unit)
+{
+  fsm         *f  = &lcp_fsm[unit];
+  lcp_options *wo = &lcp_wantoptions[unit];
+
+  f->flags = 0;
+  if (wo->passive) {
+    f->flags |= OPT_PASSIVE;
+  }
+  if (wo->silent) {
+    f->flags |= OPT_SILENT;
+  }
+  fsm_open(f);
+
+  lcp_phase[unit] = PHASE_ESTABLISH;
+}
+
+
+/*
+ * lcp_close - Take LCP down.
+ */
+void
+lcp_close(int unit, char *reason)
+{
+  fsm *f = &lcp_fsm[unit];
+
+  if (lcp_phase[unit] != PHASE_DEAD) {
+    lcp_phase[unit] = PHASE_TERMINATE;
+  }
+  if (f->state == LS_STOPPED && f->flags & (OPT_PASSIVE|OPT_SILENT)) {
+    /*
+     * This action is not strictly according to the FSM in RFC1548,
+     * but it does mean that the program terminates if you do an
+     * lcp_close() in passive/silent mode when a connection hasn't
+     * been established.
+     */
+    f->state = LS_CLOSED;
+    lcp_finished(f);
+  } else {
+    fsm_close(f, reason);
+  }
+}
+
+
+/*
+ * lcp_lowerup - The lower layer is up.
+ */
+void
+lcp_lowerup(int unit)
+{
+  lcp_options *wo = &lcp_wantoptions[unit];
+
+  /*
+   * Don't use A/C or protocol compression on transmission,
+   * but accept A/C and protocol compressed packets
+   * if we are going to ask for A/C and protocol compression.
+   */
+  ppp_set_xaccm(unit, &xmit_accm[unit]);
+  ppp_send_config(unit, PPP_MRU, 0xffffffffl, 0, 0);
+  ppp_recv_config(unit, PPP_MRU, 0x00000000l,
+  wo->neg_pcompression, wo->neg_accompression);
+  peer_mru[unit] = PPP_MRU;
+  lcp_allowoptions[unit].asyncmap = (u_long)xmit_accm[unit][0]
+                                 | ((u_long)xmit_accm[unit][1] << 8)
+                                 | ((u_long)xmit_accm[unit][2] << 16)
+                                 | ((u_long)xmit_accm[unit][3] << 24);
+  LCPDEBUG(LOG_INFO, ("lcp_lowerup: asyncmap=%X %X %X %X\n",
+            xmit_accm[unit][3],
+            xmit_accm[unit][2],
+            xmit_accm[unit][1],
+            xmit_accm[unit][0]));
+
+  fsm_lowerup(&lcp_fsm[unit]);
+}
+
+
+/*
+ * lcp_lowerdown - The lower layer is down.
+ */
+void
+lcp_lowerdown(int unit)
+{
+  fsm_lowerdown(&lcp_fsm[unit]);
+}
+
+
+/*
+ * lcp_input - Input LCP packet.
+ */
+static void
+lcp_input(int unit, u_char *p, int len)
+{
+  fsm *f = &lcp_fsm[unit];
+
+  fsm_input(f, p, len);
+}
+
+
+/*
+ * lcp_extcode - Handle a LCP-specific code.
+ */
+static int
+lcp_extcode(fsm *f, int code, u_char id, u_char *inp, int len)
+{
+  u_char *magp;
+
+  switch( code ){
+    case PROTREJ:
+      lcp_rprotrej(f, inp, len);
+      break;
+  
+    case ECHOREQ:
+      if (f->state != LS_OPENED) {
+        break;
+      }
+      LCPDEBUG(LOG_INFO, ("lcp: Echo-Request, Rcvd id %d\n", id));
+      magp = inp;
+      PUTLONG(lcp_gotoptions[f->unit].magicnumber, magp);
+      fsm_sdata(f, ECHOREP, id, inp, len);
+      break;
+
+    case ECHOREP:
+      lcp_received_echo_reply(f, id, inp, len);
+      break;
+
+    case DISCREQ:
+      break;
+
+    default:
+      return 0;
+  }
+  return 1;
+}
+
+
+/*
+ * lcp_rprotrej - Receive an Protocol-Reject.
+ *
+ * Figure out which protocol is rejected and inform it.
+ */
+static void
+lcp_rprotrej(fsm *f, u_char *inp, int len)
+{
+  int i;
+  struct protent *protp;
+  u_short prot;
+
+  if (len < (int)sizeof (u_short)) {
+    LCPDEBUG(LOG_INFO, ("lcp_rprotrej: Rcvd short Protocol-Reject packet!\n"));
+    return;
+  }
+
+  GETSHORT(prot, inp);
+
+  LCPDEBUG(LOG_INFO, ("lcp_rprotrej: Rcvd Protocol-Reject packet for %x!\n", prot));
+
+  /*
+   * Protocol-Reject packets received in any state other than the LCP
+   * LS_OPENED state SHOULD be silently discarded.
+   */
+  if( f->state != LS_OPENED ) {
+    LCPDEBUG(LOG_INFO, ("Protocol-Reject discarded: LCP in state %d\n", f->state));
+    return;
+  }
+
+  /*
+   * Upcall the proper Protocol-Reject routine.
+   */
+  for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+    if (protp->protocol == prot && protp->enabled_flag) {
+      (*protp->protrej)(f->unit);
+      return;
+    }
+  }
+
+  LCPDEBUG(LOG_WARNING, ("Protocol-Reject for unsupported protocol 0x%x\n", prot));
+}
+
+
+/*
+ * lcp_protrej - A Protocol-Reject was received.
+ */
+static void
+lcp_protrej(int unit)
+{
+  LWIP_UNUSED_ARG(unit);
+  /*
+   * Can't reject LCP!
+   */
+  LCPDEBUG(LOG_WARNING, ("lcp_protrej: Received Protocol-Reject for LCP!\n"));
+  fsm_protreject(&lcp_fsm[unit]);
+}
+
+
+/*
+ * lcp_sprotrej - Send a Protocol-Reject for some protocol.
+ */
+void
+lcp_sprotrej(int unit, u_char *p, int len)
+{
+  /*
+   * Send back the protocol and the information field of the
+   * rejected packet.  We only get here if LCP is in the LS_OPENED state.
+   */
+
+  fsm_sdata(&lcp_fsm[unit], PROTREJ, ++lcp_fsm[unit].id, p, len);
+}
+
+
+/*
+ * lcp_resetci - Reset our CI.
+ */
+static void
+lcp_resetci(fsm *f)
+{
+  lcp_wantoptions[f->unit].magicnumber = magic();
+  lcp_wantoptions[f->unit].numloops = 0;
+  lcp_gotoptions[f->unit] = lcp_wantoptions[f->unit];
+  peer_mru[f->unit] = PPP_MRU;
+  auth_reset(f->unit);
+}
+
+
+/*
+ * lcp_cilen - Return length of our CI.
+ */
+static int
+lcp_cilen(fsm *f)
+{
+  lcp_options *go = &lcp_gotoptions[f->unit];
+
+#define LENCIVOID(neg)  ((neg) ? CILEN_VOID : 0)
+#define LENCICHAP(neg)  ((neg) ? CILEN_CHAP : 0)
+#define LENCISHORT(neg) ((neg) ? CILEN_SHORT : 0)
+#define LENCILONG(neg)  ((neg) ? CILEN_LONG : 0)
+#define LENCILQR(neg)   ((neg) ? CILEN_LQR: 0)
+#define LENCICBCP(neg)  ((neg) ? CILEN_CBCP: 0)
+  /*
+   * NB: we only ask for one of CHAP and UPAP, even if we will
+   * accept either.
+   */
+  return (LENCISHORT(go->neg_mru && go->mru != PPP_DEFMRU) +
+          LENCILONG(go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) +
+          LENCICHAP(go->neg_chap) +
+          LENCISHORT(!go->neg_chap && go->neg_upap) +
+          LENCILQR(go->neg_lqr) +
+          LENCICBCP(go->neg_cbcp) +
+          LENCILONG(go->neg_magicnumber) +
+          LENCIVOID(go->neg_pcompression) +
+          LENCIVOID(go->neg_accompression));
+}
+
+
+/*
+ * lcp_addci - Add our desired CIs to a packet.
+ */
+static void
+lcp_addci(fsm *f, u_char *ucp, int *lenp)
+{
+  lcp_options *go = &lcp_gotoptions[f->unit];
+  u_char *start_ucp = ucp;
+
+#define ADDCIVOID(opt, neg) \
+  if (neg) { \
+    LCPDEBUG(LOG_INFO, ("lcp_addci: opt=%d\n", opt)); \
+    PUTCHAR(opt, ucp); \
+    PUTCHAR(CILEN_VOID, ucp); \
+  }
+#define ADDCISHORT(opt, neg, val) \
+  if (neg) { \
+    LCPDEBUG(LOG_INFO, ("lcp_addci: INT opt=%d %X\n", opt, val)); \
+    PUTCHAR(opt, ucp); \
+    PUTCHAR(CILEN_SHORT, ucp); \
+    PUTSHORT(val, ucp); \
+  }
+#define ADDCICHAP(opt, neg, val, digest) \
+  if (neg) { \
+    LCPDEBUG(LOG_INFO, ("lcp_addci: CHAP opt=%d %X\n", opt, val)); \
+    PUTCHAR(opt, ucp); \
+    PUTCHAR(CILEN_CHAP, ucp); \
+    PUTSHORT(val, ucp); \
+    PUTCHAR(digest, ucp); \
+  }
+#define ADDCILONG(opt, neg, val) \
+  if (neg) { \
+    LCPDEBUG(LOG_INFO, ("lcp_addci: L opt=%d %lX\n", opt, val)); \
+    PUTCHAR(opt, ucp); \
+    PUTCHAR(CILEN_LONG, ucp); \
+    PUTLONG(val, ucp); \
+  }
+#define ADDCILQR(opt, neg, val) \
+  if (neg) { \
+    LCPDEBUG(LOG_INFO, ("lcp_addci: LQR opt=%d %lX\n", opt, val)); \
+    PUTCHAR(opt, ucp); \
+    PUTCHAR(CILEN_LQR, ucp); \
+    PUTSHORT(PPP_LQR, ucp); \
+    PUTLONG(val, ucp); \
+  }
+#define ADDCICHAR(opt, neg, val) \
+  if (neg) { \
+    LCPDEBUG(LOG_INFO, ("lcp_addci: CHAR opt=%d %X '%z'\n", opt, val, val)); \
+    PUTCHAR(opt, ucp); \
+    PUTCHAR(CILEN_CHAR, ucp); \
+    PUTCHAR(val, ucp); \
+  }
+
+  ADDCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru);
+  ADDCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl, go->asyncmap);
+  ADDCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype);
+  ADDCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP);
+  ADDCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period);
+  ADDCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT);
+  ADDCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber);
+  ADDCIVOID(CI_PCOMPRESSION, go->neg_pcompression);
+  ADDCIVOID(CI_ACCOMPRESSION, go->neg_accompression);
+
+  if (ucp - start_ucp != *lenp) {
+    /* this should never happen, because peer_mtu should be 1500 */
+    LCPDEBUG(LOG_ERR, ("Bug in lcp_addci: wrong length\n"));
+  }
+}
+
+
+/*
+ * lcp_ackci - Ack our CIs.
+ * This should not modify any state if the Ack is bad.
+ *
+ * Returns:
+ *  0 - Ack was bad.
+ *  1 - Ack was good.
+ */
+static int
+lcp_ackci(fsm *f, u_char *p, int len)
+{
+  lcp_options *go = &lcp_gotoptions[f->unit];
+  u_char cilen, citype, cichar;
+  u_short cishort;
+  u32_t cilong;
+
+  /*
+   * CIs must be in exactly the same order that we sent.
+   * Check packet length and CI length at each step.
+   * If we find any deviations, then this packet is bad.
+   */
+#define ACKCIVOID(opt, neg) \
+  if (neg) { \
+    if ((len -= CILEN_VOID) < 0) \
+      goto bad; \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != CILEN_VOID || citype != opt) \
+      goto bad; \
+  }
+#define ACKCISHORT(opt, neg, val) \
+  if (neg) { \
+    if ((len -= CILEN_SHORT) < 0) \
+      goto bad; \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != CILEN_SHORT || citype != opt) \
+      goto bad; \
+    GETSHORT(cishort, p); \
+    if (cishort != val) \
+      goto bad; \
+  }
+#define ACKCICHAR(opt, neg, val) \
+  if (neg) { \
+    if ((len -= CILEN_CHAR) < 0) \
+      goto bad; \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != CILEN_CHAR || citype != opt) \
+      goto bad; \
+    GETCHAR(cichar, p); \
+    if (cichar != val) \
+      goto bad; \
+  }
+#define ACKCICHAP(opt, neg, val, digest) \
+  if (neg) { \
+    if ((len -= CILEN_CHAP) < 0) \
+      goto bad; \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != CILEN_CHAP || citype != opt) \
+      goto bad; \
+    GETSHORT(cishort, p); \
+    if (cishort != val) \
+      goto bad; \
+    GETCHAR(cichar, p); \
+    if (cichar != digest) \
+      goto bad; \
+  }
+#define ACKCILONG(opt, neg, val) \
+  if (neg) { \
+    if ((len -= CILEN_LONG) < 0) \
+      goto bad; \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != CILEN_LONG ||  citype != opt) \
+      goto bad; \
+    GETLONG(cilong, p); \
+    if (cilong != val) \
+      goto bad; \
+  }
+#define ACKCILQR(opt, neg, val) \
+  if (neg) { \
+    if ((len -= CILEN_LQR) < 0) \
+      goto bad; \
+    GETCHAR(citype, p); \
+    GETCHAR(cilen, p); \
+    if (cilen != CILEN_LQR || citype != opt) \
+      goto bad; \
+    GETSHORT(cishort, p); \
+    if (cishort != PPP_LQR) \
+      goto bad; \
+    GETLONG(cilong, p); \
+    if (cilong != val) \
+      goto bad; \
+  }
+
+  ACKCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru);
+  ACKCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl, go->asyncmap);
+  ACKCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype);
+  ACKCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP);
+  ACKCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period);
+  ACKCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT);
+  ACKCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber);
+  ACKCIVOID(CI_PCOMPRESSION, go->neg_pcompression);
+  ACKCIVOID(CI_ACCOMPRESSION, go->neg_accompression);
+
+  /*
+   * If there are any remaining CIs, then this packet is bad.
+   */
+  if (len != 0) {
+    goto bad;
+  }
+  LCPDEBUG(LOG_INFO, ("lcp_acki: Ack\n"));
+  return (1);
+bad:
+  LCPDEBUG(LOG_WARNING, ("lcp_acki: received bad Ack!\n"));
+  return (0);
+}
+
+
+/*
+ * lcp_nakci - Peer has sent a NAK for some of our CIs.
+ * This should not modify any state if the Nak is bad
+ * or if LCP is in the LS_OPENED state.
+ *
+ * Returns:
+ *  0 - Nak was bad.
+ *  1 - Nak was good.
+ */
+static int
+lcp_nakci(fsm *f, u_char *p, int len)
+{
+  lcp_options *go = &lcp_gotoptions[f->unit];
+  lcp_options *wo = &lcp_wantoptions[f->unit];
+  u_char citype, cichar, *next;
+  u_short cishort;
+  u32_t cilong;
+  lcp_options no;     /* options we've seen Naks for */
+  lcp_options try;    /* options to request next time */
+  int looped_back = 0;
+  int cilen;
+
+  BZERO(&no, sizeof(no));
+  try = *go;
+
+  /*
+   * Any Nak'd CIs must be in exactly the same order that we sent.
+   * Check packet length and CI length at each step.
+   * If we find any deviations, then this packet is bad.
+   */
+#define NAKCIVOID(opt, neg, code) \
+  if (go->neg && \
+      len >= CILEN_VOID && \
+      p[1] == CILEN_VOID && \
+      p[0] == opt) { \
+    len -= CILEN_VOID; \
+    INCPTR(CILEN_VOID, p); \
+    no.neg = 1; \
+    code \
+  }
+#define NAKCICHAP(opt, neg, code) \
+  if (go->neg && \
+      len >= CILEN_CHAP && \
+      p[1] == CILEN_CHAP && \
+      p[0] == opt) { \
+    len -= CILEN_CHAP; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    GETCHAR(cichar, p); \
+    no.neg = 1; \
+    code \
+  }
+#define NAKCICHAR(opt, neg, code) \
+  if (go->neg && \
+      len >= CILEN_CHAR && \
+      p[1] == CILEN_CHAR && \
+      p[0] == opt) { \
+    len -= CILEN_CHAR; \
+    INCPTR(2, p); \
+    GETCHAR(cichar, p); \
+    no.neg = 1; \
+    code \
+  }
+#define NAKCISHORT(opt, neg, code) \
+  if (go->neg && \
+      len >= CILEN_SHORT && \
+      p[1] == CILEN_SHORT && \
+      p[0] == opt) { \
+    len -= CILEN_SHORT; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    no.neg = 1; \
+    code \
+  }
+#define NAKCILONG(opt, neg, code) \
+  if (go->neg && \
+      len >= CILEN_LONG && \
+      p[1] == CILEN_LONG && \
+      p[0] == opt) { \
+    len -= CILEN_LONG; \
+    INCPTR(2, p); \
+    GETLONG(cilong, p); \
+    no.neg = 1; \
+    code \
+  }
+#define NAKCILQR(opt, neg, code) \
+  if (go->neg && \
+      len >= CILEN_LQR && \
+      p[1] == CILEN_LQR && \
+      p[0] == opt) { \
+    len -= CILEN_LQR; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    GETLONG(cilong, p); \
+    no.neg = 1; \
+    code \
+  }
+
+  /*
+   * We don't care if they want to send us smaller packets than
+   * we want.  Therefore, accept any MRU less than what we asked for,
+   * but then ignore the new value when setting the MRU in the kernel.
+   * If they send us a bigger MRU than what we asked, accept it, up to
+   * the limit of the default MRU we'd get if we didn't negotiate.
+   */
+  if (go->neg_mru && go->mru != PPP_DEFMRU) {
+    NAKCISHORT(CI_MRU, neg_mru,
+      if (cishort <= wo->mru || cishort < PPP_DEFMRU) {
+        try.mru = cishort;
+      }
+    );
+  }
+
+  /*
+   * Add any characters they want to our (receive-side) asyncmap.
+   */
+  if (go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) {
+    NAKCILONG(CI_ASYNCMAP, neg_asyncmap,
+      try.asyncmap = go->asyncmap | cilong;
+    );
+  }
+
+  /*
+   * If they've nak'd our authentication-protocol, check whether
+   * they are proposing a different protocol, or a different
+   * hash algorithm for CHAP.
+   */
+  if ((go->neg_chap || go->neg_upap)
+      && len >= CILEN_SHORT
+      && p[0] == CI_AUTHTYPE && p[1] >= CILEN_SHORT && p[1] <= len) {
+    cilen = p[1];
+    len -= cilen;
+    no.neg_chap = go->neg_chap;
+    no.neg_upap = go->neg_upap;
+    INCPTR(2, p);
+    GETSHORT(cishort, p);
+    if (cishort == PPP_PAP && cilen == CILEN_SHORT) {
+      /*
+       * If we were asking for CHAP, they obviously don't want to do it.
+       * If we weren't asking for CHAP, then we were asking for PAP,
+       * in which case this Nak is bad.
+       */
+      if (!go->neg_chap) {
+        goto bad;
+      }
+      try.neg_chap = 0;
+    
+    } else if (cishort == PPP_CHAP && cilen == CILEN_CHAP) {
+      GETCHAR(cichar, p);
+      if (go->neg_chap) {
+        /*
+         * We were asking for CHAP/MD5; they must want a different
+         * algorithm.  If they can't do MD5, we'll have to stop
+         * asking for CHAP.
+         */
+        if (cichar != go->chap_mdtype) {
+          try.neg_chap = 0;
+        }
+      } else {
+        /*
+         * Stop asking for PAP if we were asking for it.
+         */
+        try.neg_upap = 0;
+      }
+    
+    } else {
+      /*
+       * We don't recognize what they're suggesting.
+       * Stop asking for what we were asking for.
+       */
+      if (go->neg_chap) {
+        try.neg_chap = 0;
+      } else {
+        try.neg_upap = 0;
+      }
+      p += cilen - CILEN_SHORT;
+    }
+  }
+
+  /*
+   * If they can't cope with our link quality protocol, we'll have
+   * to stop asking for LQR.  We haven't got any other protocol.
+   * If they Nak the reporting period, take their value XXX ?
+   */
+  NAKCILQR(CI_QUALITY, neg_lqr,
+    if (cishort != PPP_LQR) {
+      try.neg_lqr = 0;
+    } else {
+      try.lqr_period = cilong;
+    }
+  );
+
+  /*
+   * Only implementing CBCP...not the rest of the callback options
+   */
+  NAKCICHAR(CI_CALLBACK, neg_cbcp,
+    try.neg_cbcp = 0;
+  );
+
+  /*
+   * Check for a looped-back line.
+   */
+  NAKCILONG(CI_MAGICNUMBER, neg_magicnumber,
+    try.magicnumber = magic();
+    looped_back = 1;
+  );
+
+  /*
+   * Peer shouldn't send Nak for protocol compression or
+   * address/control compression requests; they should send
+   * a Reject instead.  If they send a Nak, treat it as a Reject.
+   */
+  NAKCIVOID(CI_PCOMPRESSION, neg_pcompression,
+    try.neg_pcompression = 0;
+  );
+  NAKCIVOID(CI_ACCOMPRESSION, neg_accompression,
+    try.neg_accompression = 0;
+  );
+
+  /*
+   * There may be remaining CIs, if the peer is requesting negotiation
+   * on an option that we didn't include in our request packet.
+   * If we see an option that we requested, or one we've already seen
+   * in this packet, then this packet is bad.
+   * If we wanted to respond by starting to negotiate on the requested
+   * option(s), we could, but we don't, because except for the
+   * authentication type and quality protocol, if we are not negotiating
+   * an option, it is because we were told not to.
+   * For the authentication type, the Nak from the peer means
+   * `let me authenticate myself with you' which is a bit pointless.
+   * For the quality protocol, the Nak means `ask me to send you quality
+   * reports', but if we didn't ask for them, we don't want them.
+   * An option we don't recognize represents the peer asking to
+   * negotiate some option we don't support, so ignore it.
+   */
+  while (len > CILEN_VOID) {
+    GETCHAR(citype, p);
+    GETCHAR(cilen, p);
+    if (cilen < CILEN_VOID || (len -= cilen) < 0) {
+      goto bad;
+    }
+    next = p + cilen - 2;
+
+    switch (citype) {
+      case CI_MRU:
+        if ((go->neg_mru && go->mru != PPP_DEFMRU)
+            || no.neg_mru || cilen != CILEN_SHORT) {
+          goto bad;
+        }
+        GETSHORT(cishort, p);
+        if (cishort < PPP_DEFMRU) {
+          try.mru = cishort;
+        }
+        break;
+      case CI_ASYNCMAP:
+        if ((go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl)
+            || no.neg_asyncmap || cilen != CILEN_LONG) {
+          goto bad;
+        }
+        break;
+      case CI_AUTHTYPE:
+        if (go->neg_chap || no.neg_chap || go->neg_upap || no.neg_upap) {
+          goto bad;
+        }
+        break;
+      case CI_MAGICNUMBER:
+        if (go->neg_magicnumber || no.neg_magicnumber ||
+            cilen != CILEN_LONG) {
+          goto bad;
+        }
+        break;
+      case CI_PCOMPRESSION:
+        if (go->neg_pcompression || no.neg_pcompression
+            || cilen != CILEN_VOID) {
+          goto bad;
+        }
+        break;
+      case CI_ACCOMPRESSION:
+        if (go->neg_accompression || no.neg_accompression
+            || cilen != CILEN_VOID) {
+          goto bad;
+        }
+        break;
+      case CI_QUALITY:
+        if (go->neg_lqr || no.neg_lqr || cilen != CILEN_LQR) {
+          goto bad;
+        }
+        break;
+    }
+    p = next;
+  }
+
+  /* If there is still anything left, this packet is bad. */
+  if (len != 0) {
+    goto bad;
+  }
+
+  /*
+  * OK, the Nak is good.  Now we can update state.
+  */
+  if (f->state != LS_OPENED) {
+    if (looped_back) {
+      if (++try.numloops >= lcp_loopbackfail) {
+        LCPDEBUG(LOG_NOTICE, ("Serial line is looped back.\n"));
+        lcp_close(f->unit, "Loopback detected");
+      }
+    } else {
+      try.numloops = 0;
+    }
+    *go = try;
+  }
+
+  return 1;
+
+bad:
+  LCPDEBUG(LOG_WARNING, ("lcp_nakci: received bad Nak!\n"));
+  return 0;
+}
+
+
+/*
+ * lcp_rejci - Peer has Rejected some of our CIs.
+ * This should not modify any state if the Reject is bad
+ * or if LCP is in the LS_OPENED state.
+ *
+ * Returns:
+ *  0 - Reject was bad.
+ *  1 - Reject was good.
+ */
+static int
+lcp_rejci(fsm *f, u_char *p, int len)
+{
+  lcp_options *go = &lcp_gotoptions[f->unit];
+  u_char cichar;
+  u_short cishort;
+  u32_t cilong;
+  lcp_options try; /* options to request next time */
+
+  try = *go;
+
+  /*
+   * Any Rejected CIs must be in exactly the same order that we sent.
+   * Check packet length and CI length at each step.
+   * If we find any deviations, then this packet is bad.
+   */
+#define REJCIVOID(opt, neg) \
+  if (go->neg && \
+      len >= CILEN_VOID && \
+      p[1] == CILEN_VOID && \
+      p[0] == opt) { \
+    len -= CILEN_VOID; \
+    INCPTR(CILEN_VOID, p); \
+    try.neg = 0; \
+    LCPDEBUG(LOG_INFO, ("lcp_rejci: void opt %d rejected\n", opt)); \
+  }
+#define REJCISHORT(opt, neg, val) \
+  if (go->neg && \
+      len >= CILEN_SHORT && \
+      p[1] == CILEN_SHORT && \
+      p[0] == opt) { \
+    len -= CILEN_SHORT; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    /* Check rejected value. */ \
+    if (cishort != val) { \
+      goto bad; \
+    } \
+    try.neg = 0; \
+    LCPDEBUG(LOG_INFO, ("lcp_rejci: short opt %d rejected\n", opt)); \
+  }
+#define REJCICHAP(opt, neg, val, digest) \
+  if (go->neg && \
+      len >= CILEN_CHAP && \
+      p[1] == CILEN_CHAP && \
+      p[0] == opt) { \
+    len -= CILEN_CHAP; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    GETCHAR(cichar, p); \
+    /* Check rejected value. */ \
+    if (cishort != val || cichar != digest) { \
+      goto bad; \
+    } \
+    try.neg = 0; \
+    try.neg_upap = 0; \
+    LCPDEBUG(LOG_INFO, ("lcp_rejci: chap opt %d rejected\n", opt)); \
+  }
+#define REJCILONG(opt, neg, val) \
+  if (go->neg && \
+      len >= CILEN_LONG && \
+      p[1] == CILEN_LONG && \
+      p[0] == opt) { \
+    len -= CILEN_LONG; \
+    INCPTR(2, p); \
+    GETLONG(cilong, p); \
+    /* Check rejected value. */ \
+    if (cilong != val) { \
+      goto bad; \
+    } \
+    try.neg = 0; \
+    LCPDEBUG(LOG_INFO, ("lcp_rejci: long opt %d rejected\n", opt)); \
+  }
+#define REJCILQR(opt, neg, val) \
+  if (go->neg && \
+      len >= CILEN_LQR && \
+      p[1] == CILEN_LQR && \
+      p[0] == opt) { \
+    len -= CILEN_LQR; \
+    INCPTR(2, p); \
+    GETSHORT(cishort, p); \
+    GETLONG(cilong, p); \
+    /* Check rejected value. */ \
+    if (cishort != PPP_LQR || cilong != val) { \
+      goto bad; \
+    } \
+    try.neg = 0; \
+    LCPDEBUG(LOG_INFO, ("lcp_rejci: LQR opt %d rejected\n", opt)); \
+  }
+#define REJCICBCP(opt, neg, val) \
+  if (go->neg && \
+      len >= CILEN_CBCP && \
+      p[1] == CILEN_CBCP && \
+      p[0] == opt) { \
+    len -= CILEN_CBCP; \
+    INCPTR(2, p); \
+    GETCHAR(cichar, p); \
+    /* Check rejected value. */ \
+    if (cichar != val) { \
+      goto bad; \
+    } \
+    try.neg = 0; \
+    LCPDEBUG(LOG_INFO, ("lcp_rejci: Callback opt %d rejected\n", opt)); \
+  }
+  
+  REJCISHORT(CI_MRU, neg_mru, go->mru);
+  REJCILONG(CI_ASYNCMAP, neg_asyncmap, go->asyncmap);
+  REJCICHAP(CI_AUTHTYPE, neg_chap, PPP_CHAP, go->chap_mdtype);
+  if (!go->neg_chap) {
+    REJCISHORT(CI_AUTHTYPE, neg_upap, PPP_PAP);
+  }
+  REJCILQR(CI_QUALITY, neg_lqr, go->lqr_period);
+  REJCICBCP(CI_CALLBACK, neg_cbcp, CBCP_OPT);
+  REJCILONG(CI_MAGICNUMBER, neg_magicnumber, go->magicnumber);
+  REJCIVOID(CI_PCOMPRESSION, neg_pcompression);
+  REJCIVOID(CI_ACCOMPRESSION, neg_accompression);
+  
+  /*
+   * If there are any remaining CIs, then this packet is bad.
+   */
+  if (len != 0) {
+    goto bad;
+  }
+  /*
+   * Now we can update state.
+   */
+  if (f->state != LS_OPENED) {
+    *go = try;
+  }
+  return 1;
+  
+bad:
+  LCPDEBUG(LOG_WARNING, ("lcp_rejci: received bad Reject!\n"));
+  return 0;
+}
+
+
+/*
+ * lcp_reqci - Check the peer's requested CIs and send appropriate response.
+ *
+ * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified
+ * appropriately.  If reject_if_disagree is non-zero, doesn't return
+ * CONFNAK; returns CONFREJ if it can't return CONFACK.
+ */
+static int
+lcp_reqci(fsm *f, 
+          u_char *inp,    /* Requested CIs */
+          int *lenp,      /* Length of requested CIs */
+          int reject_if_disagree)
+{
+  lcp_options *go = &lcp_gotoptions[f->unit];
+  lcp_options *ho = &lcp_hisoptions[f->unit];
+  lcp_options *ao = &lcp_allowoptions[f->unit];
+  u_char *cip, *next;         /* Pointer to current and next CIs */
+  int cilen, citype;          /* Parsed len, type */
+  u_char cichar;              /* Parsed char value */
+  u_short cishort;            /* Parsed short value */
+  u32_t cilong;               /* Parse long value */
+  int rc = CONFACK;           /* Final packet return code */
+  int orc;                    /* Individual option return code */
+  u_char *p;                  /* Pointer to next char to parse */
+  u_char *rejp;               /* Pointer to next char in reject frame */
+  u_char *nakp;               /* Pointer to next char in Nak frame */
+  int l = *lenp;              /* Length left */
+#if TRACELCP > 0
+  char traceBuf[80];
+  size_t traceNdx = 0;
+#endif
+
+  /*
+   * Reset all his options.
+   */
+  BZERO(ho, sizeof(*ho));
+
+  /*
+   * Process all his options.
+   */
+  next = inp;
+  nakp = nak_buffer;
+  rejp = inp;
+  while (l) {
+    orc = CONFACK;      /* Assume success */
+    cip = p = next;     /* Remember begining of CI */
+    if (l < 2 ||        /* Not enough data for CI header or */
+        p[1] < 2 ||     /*  CI length too small or */
+        p[1] > l) {     /*  CI length too big? */
+      LCPDEBUG(LOG_WARNING, ("lcp_reqci: bad CI length!\n"));
+      orc = CONFREJ;    /* Reject bad CI */
+      cilen = l;        /* Reject till end of packet */
+      l = 0;            /* Don't loop again */
+      citype = 0;
+      goto endswitch;
+    }
+    GETCHAR(citype, p); /* Parse CI type */
+    GETCHAR(cilen, p);  /* Parse CI length */
+    l -= cilen;         /* Adjust remaining length */
+    next += cilen;      /* Step to next CI */
+
+    switch (citype) {   /* Check CI type */
+      case CI_MRU:
+        if (!ao->neg_mru) {    /* Allow option? */
+          LCPDEBUG(LOG_INFO, ("lcp_reqci: Reject MRU - not allowed\n"));
+          orc = CONFREJ;    /* Reject CI */
+          break;
+        } else if (cilen != CILEN_SHORT) {  /* Check CI length */
+          LCPDEBUG(LOG_INFO, ("lcp_reqci: Reject MRU - bad length\n"));
+          orc = CONFREJ;    /* Reject CI */
+          break;
+        }
+        GETSHORT(cishort, p);  /* Parse MRU */
+
+        /*
+         * He must be able to receive at least our minimum.
+         * No need to check a maximum.  If he sends a large number,
+         * we'll just ignore it.
+         */
+        if (cishort < PPP_MINMRU) {
+          LCPDEBUG(LOG_INFO, ("lcp_reqci: Nak - MRU too small\n"));
+          orc = CONFNAK;    /* Nak CI */
+          PUTCHAR(CI_MRU, nakp);
+          PUTCHAR(CILEN_SHORT, nakp);
+          PUTSHORT(PPP_MINMRU, nakp);  /* Give him a hint */
+          break;
+        }
+        ho->neg_mru = 1;    /* Remember he sent MRU */
+        ho->mru = cishort;    /* And remember value */
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MRU %d", cishort);
+        traceNdx = strlen(traceBuf);
+#endif
+        break;
+
+      case CI_ASYNCMAP:
+        if (!ao->neg_asyncmap) {
+          LCPDEBUG(LOG_INFO, ("lcp_reqci: Reject ASYNCMAP not allowed\n"));
+          orc = CONFREJ;
+          break;
+        } else if (cilen != CILEN_LONG) {
+          LCPDEBUG(LOG_INFO, ("lcp_reqci: Reject ASYNCMAP bad length\n"));
+          orc = CONFREJ;
+          break;
+        }
+        GETLONG(cilong, p);
+        
+        /*
+         * Asyncmap must have set at least the bits
+         * which are set in lcp_allowoptions[unit].asyncmap.
+         */
+        if ((ao->asyncmap & ~cilong) != 0) {
+          LCPDEBUG(LOG_INFO, ("lcp_reqci: Nak ASYNCMAP %lX missing %lX\n", 
+                    cilong, ao->asyncmap));
+          orc = CONFNAK;
+          PUTCHAR(CI_ASYNCMAP, nakp);
+          PUTCHAR(CILEN_LONG, nakp);
+          PUTLONG(ao->asyncmap | cilong, nakp);
+          break;
+        }
+        ho->neg_asyncmap = 1;
+        ho->asyncmap = cilong;
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ASYNCMAP=%lX", cilong);
+        traceNdx = strlen(traceBuf);
+#endif
+        break;
+
+      case CI_AUTHTYPE:
+        if (cilen < CILEN_SHORT) {
+          LCPDEBUG(LOG_INFO, ("lcp_reqci: Reject AUTHTYPE missing arg\n"));
+          orc = CONFREJ;
+          break;
+        } else if (!(ao->neg_upap || ao->neg_chap)) {
+          /*
+           * Reject the option if we're not willing to authenticate.
+           */
+          LCPDEBUG(LOG_INFO, ("lcp_reqci: Reject AUTHTYPE not allowed\n"));
+          orc = CONFREJ;
+          break;
+        }
+        GETSHORT(cishort, p);
+        
+        /*
+         * Authtype must be UPAP or CHAP.
+         *
+         * Note: if both ao->neg_upap and ao->neg_chap are set,
+         * and the peer sends a Configure-Request with two
+         * authenticate-protocol requests, one for CHAP and one
+         * for UPAP, then we will reject the second request.
+         * Whether we end up doing CHAP or UPAP depends then on
+         * the ordering of the CIs in the peer's Configure-Request.
+         */
+        
+        if (cishort == PPP_PAP) {
+          if (ho->neg_chap) {  /* we've already accepted CHAP */
+            LCPDEBUG(LOG_WARNING, ("lcp_reqci: Reject AUTHTYPE PAP already accepted\n"));
+            orc = CONFREJ;
+            break;
+          } else if (cilen != CILEN_SHORT) {
+            LCPDEBUG(LOG_WARNING, ("lcp_reqci: Reject AUTHTYPE PAP bad len\n"));
+            orc = CONFREJ;
+            break;
+          }
+          if (!ao->neg_upap) {  /* we don't want to do PAP */
+            LCPDEBUG(LOG_WARNING, ("lcp_reqci: Nak AUTHTYPE PAP not allowed\n"));
+            orc = CONFNAK;  /* NAK it and suggest CHAP */
+            PUTCHAR(CI_AUTHTYPE, nakp);
+            PUTCHAR(CILEN_CHAP, nakp);
+            PUTSHORT(PPP_CHAP, nakp);
+            PUTCHAR(ao->chap_mdtype, nakp);
+            break;
+          }
+          ho->neg_upap = 1;
+#if TRACELCP > 0
+          snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PAP (%X)", cishort);
+          traceNdx = strlen(traceBuf);
+#endif
+          break;
+        }
+        if (cishort == PPP_CHAP) {
+          if (ho->neg_upap) {  /* we've already accepted PAP */
+            LCPDEBUG(LOG_WARNING, ("lcp_reqci: Reject AUTHTYPE CHAP accepted PAP\n"));
+            orc = CONFREJ;
+            break;
+          } else if (cilen != CILEN_CHAP) {
+            LCPDEBUG(LOG_WARNING, ("lcp_reqci: Reject AUTHTYPE CHAP bad len\n"));
+            orc = CONFREJ;
+            break;
+          }
+          if (!ao->neg_chap) {  /* we don't want to do CHAP */
+            LCPDEBUG(LOG_WARNING, ("lcp_reqci: Nak AUTHTYPE CHAP not allowed\n"));
+            orc = CONFNAK;  /* NAK it and suggest PAP */
+            PUTCHAR(CI_AUTHTYPE, nakp);
+            PUTCHAR(CILEN_SHORT, nakp);
+            PUTSHORT(PPP_PAP, nakp);
+            break;
+          }
+          GETCHAR(cichar, p);  /* get digest type*/
+          if (cichar != CHAP_DIGEST_MD5
+#if MSCHAP_SUPPORT
+              && cichar != CHAP_MICROSOFT
+#endif
+          ) {
+            LCPDEBUG(LOG_WARNING, ("lcp_reqci: Nak AUTHTYPE CHAP digest=%d\n", (int)cichar));
+            orc = CONFNAK;
+            PUTCHAR(CI_AUTHTYPE, nakp);
+            PUTCHAR(CILEN_CHAP, nakp);
+            PUTSHORT(PPP_CHAP, nakp);
+            PUTCHAR(ao->chap_mdtype, nakp);
+            break;
+          }
+#if TRACELCP > 0
+          snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CHAP %X,%d", cishort, (int)cichar);
+          traceNdx = strlen(traceBuf);
+#endif
+          ho->chap_mdtype = cichar; /* save md type */
+          ho->neg_chap = 1;
+          break;
+        }
+        
+        /*
+         * We don't recognize the protocol they're asking for.
+         * Nak it with something we're willing to do.
+         * (At this point we know ao->neg_upap || ao->neg_chap.)
+         */
+        orc = CONFNAK;
+        PUTCHAR(CI_AUTHTYPE, nakp);
+        if (ao->neg_chap) {
+          LCPDEBUG(LOG_WARNING, ("lcp_reqci: Nak AUTHTYPE %d req CHAP\n", cishort));
+          PUTCHAR(CILEN_CHAP, nakp);
+          PUTSHORT(PPP_CHAP, nakp);
+          PUTCHAR(ao->chap_mdtype, nakp);
+        } else {
+          LCPDEBUG(LOG_WARNING, ("lcp_reqci: Nak AUTHTYPE %d req PAP\n", cishort));
+          PUTCHAR(CILEN_SHORT, nakp);
+          PUTSHORT(PPP_PAP, nakp);
+        }
+        break;
+      
+      case CI_QUALITY:
+        GETSHORT(cishort, p);
+        GETLONG(cilong, p);
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " QUALITY (%x %x)", cishort, (unsigned int) cilong);
+        traceNdx = strlen(traceBuf);
+#endif
+
+        if (!ao->neg_lqr ||
+            cilen != CILEN_LQR) {
+          orc = CONFREJ;
+          break;
+        }
+        
+        /*
+         * Check the protocol and the reporting period.
+         * XXX When should we Nak this, and what with?
+         */
+        if (cishort != PPP_LQR) {
+          orc = CONFNAK;
+          PUTCHAR(CI_QUALITY, nakp);
+          PUTCHAR(CILEN_LQR, nakp);
+          PUTSHORT(PPP_LQR, nakp);
+          PUTLONG(ao->lqr_period, nakp);
+          break;
+        }
+        break;
+      
+      case CI_MAGICNUMBER:
+        if (!(ao->neg_magicnumber || go->neg_magicnumber) ||
+            cilen != CILEN_LONG) {
+          orc = CONFREJ;
+          break;
+        }
+        GETLONG(cilong, p);
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MAGICNUMBER (%lX)", cilong);
+        traceNdx = strlen(traceBuf);
+#endif
+
+        /*
+         * He must have a different magic number.
+         */
+        if (go->neg_magicnumber &&
+            cilong == go->magicnumber) {
+          cilong = magic();  /* Don't put magic() inside macro! */
+          orc = CONFNAK;
+          PUTCHAR(CI_MAGICNUMBER, nakp);
+          PUTCHAR(CILEN_LONG, nakp);
+          PUTLONG(cilong, nakp);
+          break;
+        }
+        ho->neg_magicnumber = 1;
+        ho->magicnumber = cilong;
+        break;
+      
+      
+      case CI_PCOMPRESSION:
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PCOMPRESSION");
+        traceNdx = strlen(traceBuf);
+#endif
+        if (!ao->neg_pcompression ||
+            cilen != CILEN_VOID) {
+          orc = CONFREJ;
+          break;
+        }
+        ho->neg_pcompression = 1;
+        break;
+      
+      case CI_ACCOMPRESSION:
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ACCOMPRESSION");
+        traceNdx = strlen(traceBuf);
+#endif
+        if (!ao->neg_accompression ||
+            cilen != CILEN_VOID) {
+          orc = CONFREJ;
+          break;
+        }
+        ho->neg_accompression = 1;
+        break;
+      
+      case CI_MRRU:
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_MRRU");
+        traceNdx = strlen(traceBuf);
+#endif
+        orc = CONFREJ;
+        break;
+      
+      case CI_SSNHF:
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_SSNHF");
+        traceNdx = strlen(traceBuf);
+#endif
+        orc = CONFREJ;
+        break;
+      
+      case CI_EPDISC:
+#if TRACELCP > 0
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_EPDISC");
+        traceNdx = strlen(traceBuf);
+#endif
+        orc = CONFREJ;
+        break;
+      
+      default:
+#if TRACELCP
+        snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " unknown %d", citype);
+        traceNdx = strlen(traceBuf);
+#endif
+        orc = CONFREJ;
+        break;
+    }
+
+  endswitch:
+#if TRACELCP
+    if (traceNdx >= 80 - 32) {
+      LCPDEBUG(LOG_INFO, ("lcp_reqci: rcvd%s\n", traceBuf));
+      traceNdx = 0;
+    }
+#endif
+    if (orc == CONFACK && /* Good CI */
+        rc != CONFACK) {  /*  but prior CI wasnt? */
+      continue;           /* Don't send this one */
+    }
+
+    if (orc == CONFNAK) {     /* Nak this CI? */
+      if (reject_if_disagree  /* Getting fed up with sending NAKs? */
+          && citype != CI_MAGICNUMBER) {
+        orc = CONFREJ;        /* Get tough if so */
+      } else {
+        if (rc == CONFREJ) {  /* Rejecting prior CI? */
+          continue;           /* Don't send this one */
+        }
+        rc = CONFNAK;
+      }
+    }
+    if (orc == CONFREJ) {        /* Reject this CI */
+      rc = CONFREJ;
+      if (cip != rejp) {         /* Need to move rejected CI? */
+        BCOPY(cip, rejp, cilen); /* Move it */
+      }
+      INCPTR(cilen, rejp);       /* Update output pointer */
+    }
+  }
+
+  /*
+   * If we wanted to send additional NAKs (for unsent CIs), the
+   * code would go here.  The extra NAKs would go at *nakp.
+   * At present there are no cases where we want to ask the
+   * peer to negotiate an option.
+   */
+
+  switch (rc) {
+    case CONFACK:
+      *lenp = (int)(next - inp);
+      break;
+    case CONFNAK:
+      /*
+       * Copy the Nak'd options from the nak_buffer to the caller's buffer.
+       */
+      *lenp = (int)(nakp - nak_buffer);
+      BCOPY(nak_buffer, inp, *lenp);
+      break;
+    case CONFREJ:
+      *lenp = (int)(rejp - inp);
+      break;
+  }
+
+#if TRACELCP > 0
+  if (traceNdx > 0) {
+    LCPDEBUG(LOG_INFO, ("lcp_reqci: %s\n", traceBuf));
+  }
+#endif
+  LCPDEBUG(LOG_INFO, ("lcp_reqci: returning CONF%s.\n", CODENAME(rc)));
+  return (rc);      /* Return final code */
+}
+
+
+/*
+ * lcp_up - LCP has come UP.
+ */
+static void
+lcp_up(fsm *f)
+{
+  lcp_options *wo = &lcp_wantoptions[f->unit];
+  lcp_options *ho = &lcp_hisoptions[f->unit];
+  lcp_options *go = &lcp_gotoptions[f->unit];
+  lcp_options *ao = &lcp_allowoptions[f->unit];
+
+  if (!go->neg_magicnumber) {
+    go->magicnumber = 0;
+  }
+  if (!ho->neg_magicnumber) {
+    ho->magicnumber = 0;
+  }
+
+  /*
+   * Set our MTU to the smaller of the MTU we wanted and
+   * the MRU our peer wanted.  If we negotiated an MRU,
+   * set our MRU to the larger of value we wanted and
+   * the value we got in the negotiation.
+   */
+  ppp_send_config(f->unit, LWIP_MIN(ao->mru, (ho->neg_mru? ho->mru: PPP_MRU)),
+                 (ho->neg_asyncmap? ho->asyncmap: 0xffffffffl),
+                  ho->neg_pcompression, ho->neg_accompression);
+  /*
+   * If the asyncmap hasn't been negotiated, we really should
+   * set the receive asyncmap to ffffffff, but we set it to 0
+   * for backwards contemptibility.
+   */
+  ppp_recv_config(f->unit, (go->neg_mru? LWIP_MAX(wo->mru, go->mru): PPP_MRU),
+                 (go->neg_asyncmap? go->asyncmap: 0x00000000),
+                  go->neg_pcompression, go->neg_accompression);
+
+  if (ho->neg_mru) {
+    peer_mru[f->unit] = ho->mru;
+  }
+
+  lcp_echo_lowerup(f->unit); /* Enable echo messages */
+
+  link_established(f->unit); /* The link is up; authenticate now */
+}
+
+
+/*
+ * lcp_down - LCP has gone DOWN.
+ *
+ * Alert other protocols.
+ */
+static void
+lcp_down(fsm *f)
+{
+  lcp_options *go = &lcp_gotoptions[f->unit];
+
+  lcp_echo_lowerdown(f->unit);
+
+  link_down(f->unit);
+
+  ppp_send_config(f->unit, PPP_MRU, 0xffffffffl, 0, 0);
+  ppp_recv_config(f->unit, PPP_MRU,
+                  (go->neg_asyncmap? go->asyncmap: 0x00000000),
+                   go->neg_pcompression, go->neg_accompression);
+  peer_mru[f->unit] = PPP_MRU;
+}
+
+
+/*
+ * lcp_starting - LCP needs the lower layer up.
+ */
+static void
+lcp_starting(fsm *f)
+{
+  link_required(f->unit); /* lwip: currently does nothing */
+}
+
+
+/*
+ * lcp_finished - LCP has finished with the lower layer.
+ */
+static void
+lcp_finished(fsm *f)
+{
+  link_terminated(f->unit); /* we are finished with the link */
+}
+
+
+#if PPP_ADDITIONAL_CALLBACKS
+/*
+ * print_string - print a readable representation of a string using
+ * printer.
+ */
+static void
+print_string( char *p, int len, void (*printer) (void *, char *, ...), void *arg)
+{
+  int c;
+  
+  printer(arg, "\"");
+  for (; len > 0; --len) {
+    c = *p++;
+    if (' ' <= c && c <= '~') {
+        if (c == '\\' || c == '"') {
+          printer(arg, "\\");
+        }
+        printer(arg, "%c", c);
+    } else {
+      switch (c) {
+        case '\n':
+          printer(arg, "\\n");
+          break;
+        case '\r':
+          printer(arg, "\\r");
+          break;
+        case '\t':
+          printer(arg, "\\t");
+          break;
+        default:
+          printer(arg, "\\%.3o", c);
+        }
+    }
+  }
+  printer(arg, "\"");
+}
+
+
+/*
+ * lcp_printpkt - print the contents of an LCP packet.
+ */
+static char *lcp_codenames[] = {
+  "ConfReq", "ConfAck", "ConfNak", "ConfRej",
+  "TermReq", "TermAck", "CodeRej", "ProtRej",
+  "EchoReq", "EchoRep", "DiscReq"
+};
+
+static int
+lcp_printpkt( u_char *p, int plen, void (*printer) (void *, char *, ...), void *arg)
+{
+  int code, id, len, olen;
+  u_char *pstart, *optend;
+  u_short cishort;
+  u32_t cilong;
+
+  if (plen < HEADERLEN) {
+    return 0;
+  }
+  pstart = p;
+  GETCHAR(code, p);
+  GETCHAR(id, p);
+  GETSHORT(len, p);
+  if (len < HEADERLEN || len > plen) {
+    return 0;
+  }
+
+  if (code >= 1 && code <= sizeof(lcp_codenames) / sizeof(char *)) {
+    printer(arg, " %s", lcp_codenames[code-1]);
+  } else {
+    printer(arg, " code=0x%x", code);
+  }
+  printer(arg, " id=0x%x", id);
+  len -= HEADERLEN;
+  switch (code) {
+    case CONFREQ:
+    case CONFACK:
+    case CONFNAK:
+    case CONFREJ:
+      /* print option list */
+      while (len >= 2) {
+        GETCHAR(code, p);
+        GETCHAR(olen, p);
+        p -= 2;
+        if (olen < 2 || olen > len) {
+          break;
+        }
+        printer(arg, " <");
+        len -= olen;
+        optend = p + olen;
+        switch (code) {
+          case CI_MRU:
+            if (olen == CILEN_SHORT) {
+              p += 2;
+              GETSHORT(cishort, p);
+              printer(arg, "mru %d", cishort);
+            }
+            break;
+          case CI_ASYNCMAP:
+            if (olen == CILEN_LONG) {
+              p += 2;
+              GETLONG(cilong, p);
+              printer(arg, "asyncmap 0x%lx", cilong);
+            }
+            break;
+          case CI_AUTHTYPE:
+            if (olen >= CILEN_SHORT) {
+              p += 2;
+              printer(arg, "auth ");
+              GETSHORT(cishort, p);
+              switch (cishort) {
+                case PPP_PAP:
+                  printer(arg, "pap");
+                  break;
+                case PPP_CHAP:
+                  printer(arg, "chap");
+                  break;
+                default:
+                  printer(arg, "0x%x", cishort);
+              }
+            }
+            break;
+          case CI_QUALITY:
+            if (olen >= CILEN_SHORT) {
+              p += 2;
+              printer(arg, "quality ");
+              GETSHORT(cishort, p);
+              switch (cishort) {
+                case PPP_LQR:
+                  printer(arg, "lqr");
+                  break;
+                default:
+                  printer(arg, "0x%x", cishort);
+              }
+            }
+            break;
+          case CI_CALLBACK:
+            if (olen >= CILEN_CHAR) {
+              p += 2;
+              printer(arg, "callback ");
+              GETSHORT(cishort, p);
+              switch (cishort) {
+                case CBCP_OPT:
+                  printer(arg, "CBCP");
+                  break;
+                default:
+                  printer(arg, "0x%x", cishort);
+              }
+            }
+            break;
+          case CI_MAGICNUMBER:
+            if (olen == CILEN_LONG) {
+              p += 2;
+              GETLONG(cilong, p);
+              printer(arg, "magic 0x%x", cilong);
+            }
+            break;
+          case CI_PCOMPRESSION:
+            if (olen == CILEN_VOID) {
+              p += 2;
+              printer(arg, "pcomp");
+            }
+            break;
+          case CI_ACCOMPRESSION:
+            if (olen == CILEN_VOID) {
+              p += 2;
+              printer(arg, "accomp");
+            }
+            break;
+        }
+        while (p < optend) {
+          GETCHAR(code, p);
+          printer(arg, " %.2x", code);
+        }
+        printer(arg, ">");
+      }
+      break;
+    
+    case TERMACK:
+    case TERMREQ:
+      if (len > 0 && *p >= ' ' && *p < 0x7f) {
+        printer(arg, " ");
+        print_string((char*)p, len, printer, arg);
+        p += len;
+        len = 0;
+      }
+      break;
+    
+    case ECHOREQ:
+    case ECHOREP:
+    case DISCREQ:
+      if (len >= 4) {
+        GETLONG(cilong, p);
+        printer(arg, " magic=0x%x", cilong);
+        p += 4;
+        len -= 4;
+      }
+      break;
+  }
+
+  /* print the rest of the bytes in the packet */
+  for (; len > 0; --len) {
+    GETCHAR(code, p);
+    printer(arg, " %.2x", code);
+  }
+
+  return (int)(p - pstart);
+}
+#endif /* PPP_ADDITIONAL_CALLBACKS */
+
+/*
+ * Time to shut down the link because there is nothing out there.
+ */
+static void
+LcpLinkFailure (fsm *f)
+{
+  if (f->state == LS_OPENED) {
+    LCPDEBUG(LOG_INFO, ("No response to %d echo-requests\n", lcp_echos_pending));
+    LCPDEBUG(LOG_NOTICE, ("Serial link appears to be disconnected.\n"));
+    lcp_close(f->unit, "Peer not responding");
+  }
+}
+
+/*
+ * Timer expired for the LCP echo requests from this process.
+ */
+static void
+LcpEchoCheck (fsm *f)
+{
+  LcpSendEchoRequest (f);
+
+  /*
+   * Start the timer for the next interval.
+   */
+  LWIP_ASSERT("lcp_echo_timer_running == 0", lcp_echo_timer_running == 0);
+
+  TIMEOUT (LcpEchoTimeout, f, lcp_echo_interval);
+  lcp_echo_timer_running = 1;
+}
+
+/*
+ * LcpEchoTimeout - Timer expired on the LCP echo
+ */
+static void
+LcpEchoTimeout (void *arg)
+{
+  if (lcp_echo_timer_running != 0) {
+    lcp_echo_timer_running = 0;
+    LcpEchoCheck ((fsm *) arg);
+  }
+}
+
+/*
+ * LcpEchoReply - LCP has received a reply to the echo
+ */
+static void
+lcp_received_echo_reply (fsm *f, int id, u_char *inp, int len)
+{
+  u32_t magic;
+
+  LWIP_UNUSED_ARG(id);
+
+  /* Check the magic number - don't count replies from ourselves. */
+  if (len < 4) {
+    LCPDEBUG(LOG_WARNING, ("lcp: received short Echo-Reply, length %d\n", len));
+    return;
+  }
+  GETLONG(magic, inp);
+  if (lcp_gotoptions[f->unit].neg_magicnumber && magic == lcp_gotoptions[f->unit].magicnumber) {
+    LCPDEBUG(LOG_WARNING, ("appear to have received our own echo-reply!\n"));
+    return;
+  }
+
+  /* Reset the number of outstanding echo frames */
+  lcp_echos_pending = 0;
+}
+
+/*
+ * LcpSendEchoRequest - Send an echo request frame to the peer
+ */
+static void
+LcpSendEchoRequest (fsm *f)
+{
+  u32_t lcp_magic;
+  u_char pkt[4], *pktp;
+
+  /*
+   * Detect the failure of the peer at this point.
+   */
+  if (lcp_echo_fails != 0) {
+    if (lcp_echos_pending >= lcp_echo_fails) {
+      LcpLinkFailure(f);
+      lcp_echos_pending = 0;
+    }
+  }
+
+  /*
+   * Make and send the echo request frame.
+   */
+  if (f->state == LS_OPENED) {
+    lcp_magic = lcp_gotoptions[f->unit].magicnumber;
+    pktp = pkt;
+    PUTLONG(lcp_magic, pktp);
+    fsm_sdata(f, ECHOREQ, (u_char)(lcp_echo_number++ & 0xFF), pkt, (int)(pktp - pkt));
+    ++lcp_echos_pending;
+  }
+}
+
+/*
+ * lcp_echo_lowerup - Start the timer for the LCP frame
+ */
+
+static void
+lcp_echo_lowerup (int unit)
+{
+  fsm *f = &lcp_fsm[unit];
+
+  /* Clear the parameters for generating echo frames */
+  lcp_echos_pending      = 0;
+  lcp_echo_number        = 0;
+  lcp_echo_timer_running = 0;
+
+  /* If a timeout interval is specified then start the timer */
+  if (lcp_echo_interval != 0) {
+    LcpEchoCheck (f);
+  }
+}
+
+/*
+ * lcp_echo_lowerdown - Stop the timer for the LCP frame
+ */
+
+static void
+lcp_echo_lowerdown (int unit)
+{
+  fsm *f = &lcp_fsm[unit];
+
+  if (lcp_echo_timer_running != 0) {
+    UNTIMEOUT (LcpEchoTimeout, f);
+    lcp_echo_timer_running = 0;
+  }
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/lcp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/lcp.h
new file mode 100644
index 0000000..b9201ee
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/lcp.h
@@ -0,0 +1,151 @@
+/*****************************************************************************
+* lcp.h - Network Link Control Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * lcp.h - Link Control Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: lcp.h,v 1.4 2010/01/18 20:49:43 goldsimon Exp $
+ */
+
+#ifndef LCP_H
+#define LCP_H
+/*
+ * Options.
+ */
+#define CI_MRU           1  /* Maximum Receive Unit */
+#define CI_ASYNCMAP      2  /* Async Control Character Map */
+#define CI_AUTHTYPE      3  /* Authentication Type */
+#define CI_QUALITY       4  /* Quality Protocol */
+#define CI_MAGICNUMBER   5  /* Magic Number */
+#define CI_PCOMPRESSION  7  /* Protocol Field Compression */
+#define CI_ACCOMPRESSION 8  /* Address/Control Field Compression */
+#define CI_CALLBACK      13 /* callback */
+#define CI_MRRU          17 /* max reconstructed receive unit; multilink */
+#define CI_SSNHF         18 /* short sequence numbers for multilink */
+#define CI_EPDISC        19 /* endpoint discriminator */
+
+/*
+ * LCP-specific packet types (code numbers).
+ */
+#define PROTREJ          8  /* Protocol Reject */
+#define ECHOREQ          9  /* Echo Request */
+#define ECHOREP          10 /* Echo Reply */
+#define DISCREQ          11 /* Discard Request */
+#define CBCP_OPT         6  /* Use callback control protocol */
+
+/*
+ * The state of options is described by an lcp_options structure.
+ */
+typedef struct lcp_options {
+    u_int passive           : 1; /* Don't die if we don't get a response */
+    u_int silent            : 1; /* Wait for the other end to start first */
+    u_int restart           : 1; /* Restart vs. exit after close */
+    u_int neg_mru           : 1; /* Negotiate the MRU? */
+    u_int neg_asyncmap      : 1; /* Negotiate the async map? */
+    u_int neg_upap          : 1; /* Ask for UPAP authentication? */
+    u_int neg_chap          : 1; /* Ask for CHAP authentication? */
+    u_int neg_magicnumber   : 1; /* Ask for magic number? */
+    u_int neg_pcompression  : 1; /* HDLC Protocol Field Compression? */
+    u_int neg_accompression : 1; /* HDLC Address/Control Field Compression? */
+    u_int neg_lqr           : 1; /* Negotiate use of Link Quality Reports */
+    u_int neg_cbcp          : 1; /* Negotiate use of CBCP */
+#ifdef PPP_MULTILINK
+    u_int neg_mrru          : 1; /* Negotiate multilink MRRU */
+    u_int neg_ssnhf         : 1; /* Negotiate short sequence numbers */
+    u_int neg_endpoint      : 1; /* Negotiate endpoint discriminator */
+#endif
+    u_short mru;                 /* Value of MRU */
+#ifdef PPP_MULTILINK
+    u_short mrru;                /* Value of MRRU, and multilink enable */
+#endif
+    u_char chap_mdtype;          /* which MD type (hashing algorithm) */
+    u32_t asyncmap;              /* Value of async map */
+    u32_t magicnumber;
+    int numloops;                /* Number of loops during magic number neg. */
+    u32_t lqr_period;            /* Reporting period for LQR 1/100ths second */
+#ifdef PPP_MULTILINK
+    struct epdisc endpoint;      /* endpoint discriminator */
+#endif
+} lcp_options;
+
+/*
+ * Values for phase from BSD pppd.h based on RFC 1661.
+ */
+typedef enum {
+  PHASE_DEAD = 0,
+  PHASE_INITIALIZE,
+  PHASE_ESTABLISH,
+  PHASE_AUTHENTICATE,
+  PHASE_CALLBACK,
+  PHASE_NETWORK,
+  PHASE_TERMINATE
+} LinkPhase;
+
+
+
+extern LinkPhase lcp_phase[NUM_PPP]; /* Phase of link session (RFC 1661) */
+extern lcp_options lcp_wantoptions[];
+extern lcp_options lcp_gotoptions[];
+extern lcp_options lcp_allowoptions[];
+extern lcp_options lcp_hisoptions[];
+extern ext_accm xmit_accm[];
+
+
+void lcp_init     (int);
+void lcp_open     (int);
+void lcp_close    (int, char *);
+void lcp_lowerup  (int);
+void lcp_lowerdown(int);
+void lcp_sprotrej (int, u_char *, int); /* send protocol reject */
+
+extern struct protent lcp_protent;
+
+/* Default number of times we receive our magic number from the peer
+   before deciding the link is looped-back. */
+#define DEFLOOPBACKFAIL 10
+
+#endif /* LCP_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/magic.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/magic.c
new file mode 100644
index 0000000..3901330
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/magic.c
@@ -0,0 +1,80 @@
+/*****************************************************************************
+* magic.c - Network Random Number Generator program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*   Original based on BSD magic.c.
+*****************************************************************************/
+/*
+ * magic.c - PPP Magic Number routines.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT
+
+#include "ppp.h"
+#include "randm.h"
+#include "magic.h"
+
+
+/*
+ * magicInit - Initialize the magic number generator.
+ *
+ * Since we use another random number generator that has its own
+ * initialization, we do nothing here.
+ */
+void magicInit()
+{
+  return;
+}
+
+/*
+ * magic - Returns the next magic number.
+ */
+u32_t magic()
+{
+  return avRandom();
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/magic.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/magic.h
new file mode 100644
index 0000000..eba70d2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/magic.h
@@ -0,0 +1,63 @@
+/*****************************************************************************
+* magic.h - Network Random Number Generator header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * magic.h - PPP Magic Number definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: magic.h,v 1.3 2010/01/18 20:49:43 goldsimon Exp $
+ */
+
+#ifndef MAGIC_H
+#define MAGIC_H
+
+/* Initialize the magic number generator */
+void  magicInit(void);
+
+/* Returns the next magic number */
+u32_t magic(void);
+
+#endif /* MAGIC_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/md5.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/md5.c
new file mode 100644
index 0000000..3cb69e2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/md5.c
@@ -0,0 +1,320 @@
+/*
+ ***********************************************************************
+ ** md5.c -- the source code for MD5 routines                         **
+ ** RSA Data Security, Inc. MD5 Message-Digest Algorithm              **
+ ** Created: 2/17/90 RLR                                              **
+ ** Revised: 1/91 SRD,AJ,BSK,JT Reference C ver., 7/10 constant corr. **
+ ***********************************************************************
+ */
+
+/*
+ ***********************************************************************
+ ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved.  **
+ **                                                                   **
+ ** License to copy and use this software is granted provided that    **
+ ** it is identified as the "RSA Data Security, Inc. MD5 Message-     **
+ ** Digest Algorithm" in all material mentioning or referencing this  **
+ ** software or this function.                                        **
+ **                                                                   **
+ ** License is also granted to make and use derivative works          **
+ ** provided that such works are identified as "derived from the RSA  **
+ ** Data Security, Inc. MD5 Message-Digest Algorithm" in all          **
+ ** material mentioning or referencing the derived work.              **
+ **                                                                   **
+ ** RSA Data Security, Inc. makes no representations concerning       **
+ ** either the merchantability of this software or the suitability    **
+ ** of this software for any particular purpose.  It is provided "as  **
+ ** is" without express or implied warranty of any kind.              **
+ **                                                                   **
+ ** These notices must be retained in any copies of any part of this  **
+ ** documentation and/or software.                                    **
+ ***********************************************************************
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#if CHAP_SUPPORT || MD5_SUPPORT
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "md5.h"
+
+#include 
+
+/*
+ ***********************************************************************
+ **  Message-digest routines:                                         **
+ **  To form the message digest for a message M                       **
+ **    (1) Initialize a context buffer mdContext using MD5Init        **
+ **    (2) Call MD5Update on mdContext and M                          **
+ **    (3) Call MD5Final on mdContext                                 **
+ **  The message digest is now in mdContext->digest[0...15]           **
+ ***********************************************************************
+ */
+
+/* forward declaration */
+static void Transform (u32_t *buf, u32_t *in);
+
+static unsigned char PADDING[64] = {
+  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+/* F, G, H and I are basic MD5 functions */
+#define F(x, y, z) (((x) & (y)) | ((~x) & (z)))
+#define G(x, y, z) (((x) & (z)) | ((y) & (~z)))
+#define H(x, y, z) ((x) ^ (y) ^ (z))
+#define I(x, y, z) ((y) ^ ((x) | (~z)))
+
+/* ROTATE_LEFT rotates x left n bits */
+#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n))))
+
+/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4 */
+/* Rotation is separate from addition to prevent recomputation */
+#define FF(a, b, c, d, x, s, ac) \
+  {(a) += F ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+#define GG(a, b, c, d, x, s, ac) \
+  {(a) += G ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+#define HH(a, b, c, d, x, s, ac) \
+  {(a) += H ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+#define II(a, b, c, d, x, s, ac) \
+  {(a) += I ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+
+#ifdef __STDC__
+#define UL(x) x##UL
+#else
+#ifdef WIN32
+#define UL(x) x##UL
+#else
+#define UL(x) x
+#endif
+#endif
+
+/* The routine MD5Init initializes the message-digest context
+   mdContext. All fields are set to zero.
+ */
+void
+MD5Init (MD5_CTX *mdContext)
+{
+  mdContext->i[0] = mdContext->i[1] = (u32_t)0;
+
+  /* Load magic initialization constants. */
+  mdContext->buf[0] = (u32_t)0x67452301UL;
+  mdContext->buf[1] = (u32_t)0xefcdab89UL;
+  mdContext->buf[2] = (u32_t)0x98badcfeUL;
+  mdContext->buf[3] = (u32_t)0x10325476UL;
+}
+
+/* The routine MD5Update updates the message-digest context to
+   account for the presence of each of the characters inBuf[0..inLen-1]
+   in the message whose digest is being computed.
+ */
+void
+MD5Update(MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen)
+{
+  u32_t in[16];
+  int mdi;
+  unsigned int i, ii;
+
+#if 0
+  PPPDEBUG(LOG_INFO, ("MD5Update: %u:%.*H\n", inLen, LWIP_MIN(inLen, 20) * 2, inBuf));
+  PPPDEBUG(LOG_INFO, ("MD5Update: %u:%s\n", inLen, inBuf));
+#endif
+  
+  /* compute number of bytes mod 64 */
+  mdi = (int)((mdContext->i[0] >> 3) & 0x3F);
+
+  /* update number of bits */
+  if ((mdContext->i[0] + ((u32_t)inLen << 3)) < mdContext->i[0]) {
+    mdContext->i[1]++;
+  }
+  mdContext->i[0] += ((u32_t)inLen << 3);
+  mdContext->i[1] += ((u32_t)inLen >> 29);
+
+  while (inLen--) {
+    /* add new character to buffer, increment mdi */
+    mdContext->in[mdi++] = *inBuf++;
+
+    /* transform if necessary */
+    if (mdi == 0x40) {
+      for (i = 0, ii = 0; i < 16; i++, ii += 4) {
+        in[i] = (((u32_t)mdContext->in[ii+3]) << 24) |
+                (((u32_t)mdContext->in[ii+2]) << 16) |
+                (((u32_t)mdContext->in[ii+1]) << 8)  |
+                ((u32_t)mdContext->in[ii]);
+      }
+      Transform (mdContext->buf, in);
+      mdi = 0;
+    }
+  }
+}
+
+/* The routine MD5Final terminates the message-digest computation and
+   ends with the desired message digest in mdContext->digest[0...15].
+ */
+void
+MD5Final (unsigned char hash[], MD5_CTX *mdContext)
+{
+  u32_t in[16];
+  int mdi;
+  unsigned int i, ii;
+  unsigned int padLen;
+
+  /* save number of bits */
+  in[14] = mdContext->i[0];
+  in[15] = mdContext->i[1];
+
+  /* compute number of bytes mod 64 */
+  mdi = (int)((mdContext->i[0] >> 3) & 0x3F);
+
+  /* pad out to 56 mod 64 */
+  padLen = (mdi < 56) ? (56 - mdi) : (120 - mdi);
+  MD5Update (mdContext, PADDING, padLen);
+
+  /* append length in bits and transform */
+  for (i = 0, ii = 0; i < 14; i++, ii += 4) {
+    in[i] = (((u32_t)mdContext->in[ii+3]) << 24) |
+            (((u32_t)mdContext->in[ii+2]) << 16) |
+            (((u32_t)mdContext->in[ii+1]) << 8)  |
+            ((u32_t)mdContext->in[ii]);
+  }
+  Transform (mdContext->buf, in);
+
+  /* store buffer in digest */
+  for (i = 0, ii = 0; i < 4; i++, ii += 4) {
+    mdContext->digest[ii]   = (unsigned char)(mdContext->buf[i] & 0xFF);
+    mdContext->digest[ii+1] =
+      (unsigned char)((mdContext->buf[i] >> 8)  & 0xFF);
+    mdContext->digest[ii+2] =
+      (unsigned char)((mdContext->buf[i] >> 16) & 0xFF);
+    mdContext->digest[ii+3] =
+      (unsigned char)((mdContext->buf[i] >> 24) & 0xFF);
+  }
+  SMEMCPY(hash, mdContext->digest, 16);
+}
+
+/* Basic MD5 step. Transforms buf based on in.
+ */
+static void
+Transform (u32_t *buf, u32_t *in)
+{
+  u32_t a = buf[0], b = buf[1], c = buf[2], d = buf[3];
+
+  /* Round 1 */
+#define S11 7
+#define S12 12
+#define S13 17
+#define S14 22
+  FF ( a, b, c, d, in[ 0], S11, UL(3614090360)); /* 1 */
+  FF ( d, a, b, c, in[ 1], S12, UL(3905402710)); /* 2 */
+  FF ( c, d, a, b, in[ 2], S13, UL( 606105819)); /* 3 */
+  FF ( b, c, d, a, in[ 3], S14, UL(3250441966)); /* 4 */
+  FF ( a, b, c, d, in[ 4], S11, UL(4118548399)); /* 5 */
+  FF ( d, a, b, c, in[ 5], S12, UL(1200080426)); /* 6 */
+  FF ( c, d, a, b, in[ 6], S13, UL(2821735955)); /* 7 */
+  FF ( b, c, d, a, in[ 7], S14, UL(4249261313)); /* 8 */
+  FF ( a, b, c, d, in[ 8], S11, UL(1770035416)); /* 9 */
+  FF ( d, a, b, c, in[ 9], S12, UL(2336552879)); /* 10 */
+  FF ( c, d, a, b, in[10], S13, UL(4294925233)); /* 11 */
+  FF ( b, c, d, a, in[11], S14, UL(2304563134)); /* 12 */
+  FF ( a, b, c, d, in[12], S11, UL(1804603682)); /* 13 */
+  FF ( d, a, b, c, in[13], S12, UL(4254626195)); /* 14 */
+  FF ( c, d, a, b, in[14], S13, UL(2792965006)); /* 15 */
+  FF ( b, c, d, a, in[15], S14, UL(1236535329)); /* 16 */
+
+  /* Round 2 */
+#define S21 5
+#define S22 9
+#define S23 14
+#define S24 20
+  GG ( a, b, c, d, in[ 1], S21, UL(4129170786)); /* 17 */
+  GG ( d, a, b, c, in[ 6], S22, UL(3225465664)); /* 18 */
+  GG ( c, d, a, b, in[11], S23, UL( 643717713)); /* 19 */
+  GG ( b, c, d, a, in[ 0], S24, UL(3921069994)); /* 20 */
+  GG ( a, b, c, d, in[ 5], S21, UL(3593408605)); /* 21 */
+  GG ( d, a, b, c, in[10], S22, UL(  38016083)); /* 22 */
+  GG ( c, d, a, b, in[15], S23, UL(3634488961)); /* 23 */
+  GG ( b, c, d, a, in[ 4], S24, UL(3889429448)); /* 24 */
+  GG ( a, b, c, d, in[ 9], S21, UL( 568446438)); /* 25 */
+  GG ( d, a, b, c, in[14], S22, UL(3275163606)); /* 26 */
+  GG ( c, d, a, b, in[ 3], S23, UL(4107603335)); /* 27 */
+  GG ( b, c, d, a, in[ 8], S24, UL(1163531501)); /* 28 */
+  GG ( a, b, c, d, in[13], S21, UL(2850285829)); /* 29 */
+  GG ( d, a, b, c, in[ 2], S22, UL(4243563512)); /* 30 */
+  GG ( c, d, a, b, in[ 7], S23, UL(1735328473)); /* 31 */
+  GG ( b, c, d, a, in[12], S24, UL(2368359562)); /* 32 */
+
+  /* Round 3 */
+#define S31 4
+#define S32 11
+#define S33 16
+#define S34 23
+  HH ( a, b, c, d, in[ 5], S31, UL(4294588738)); /* 33 */
+  HH ( d, a, b, c, in[ 8], S32, UL(2272392833)); /* 34 */
+  HH ( c, d, a, b, in[11], S33, UL(1839030562)); /* 35 */
+  HH ( b, c, d, a, in[14], S34, UL(4259657740)); /* 36 */
+  HH ( a, b, c, d, in[ 1], S31, UL(2763975236)); /* 37 */
+  HH ( d, a, b, c, in[ 4], S32, UL(1272893353)); /* 38 */
+  HH ( c, d, a, b, in[ 7], S33, UL(4139469664)); /* 39 */
+  HH ( b, c, d, a, in[10], S34, UL(3200236656)); /* 40 */
+  HH ( a, b, c, d, in[13], S31, UL( 681279174)); /* 41 */
+  HH ( d, a, b, c, in[ 0], S32, UL(3936430074)); /* 42 */
+  HH ( c, d, a, b, in[ 3], S33, UL(3572445317)); /* 43 */
+  HH ( b, c, d, a, in[ 6], S34, UL(  76029189)); /* 44 */
+  HH ( a, b, c, d, in[ 9], S31, UL(3654602809)); /* 45 */
+  HH ( d, a, b, c, in[12], S32, UL(3873151461)); /* 46 */
+  HH ( c, d, a, b, in[15], S33, UL( 530742520)); /* 47 */
+  HH ( b, c, d, a, in[ 2], S34, UL(3299628645)); /* 48 */
+
+  /* Round 4 */
+#define S41 6
+#define S42 10
+#define S43 15
+#define S44 21
+  II ( a, b, c, d, in[ 0], S41, UL(4096336452)); /* 49 */
+  II ( d, a, b, c, in[ 7], S42, UL(1126891415)); /* 50 */
+  II ( c, d, a, b, in[14], S43, UL(2878612391)); /* 51 */
+  II ( b, c, d, a, in[ 5], S44, UL(4237533241)); /* 52 */
+  II ( a, b, c, d, in[12], S41, UL(1700485571)); /* 53 */
+  II ( d, a, b, c, in[ 3], S42, UL(2399980690)); /* 54 */
+  II ( c, d, a, b, in[10], S43, UL(4293915773)); /* 55 */
+  II ( b, c, d, a, in[ 1], S44, UL(2240044497)); /* 56 */
+  II ( a, b, c, d, in[ 8], S41, UL(1873313359)); /* 57 */
+  II ( d, a, b, c, in[15], S42, UL(4264355552)); /* 58 */
+  II ( c, d, a, b, in[ 6], S43, UL(2734768916)); /* 59 */
+  II ( b, c, d, a, in[13], S44, UL(1309151649)); /* 60 */
+  II ( a, b, c, d, in[ 4], S41, UL(4149444226)); /* 61 */
+  II ( d, a, b, c, in[11], S42, UL(3174756917)); /* 62 */
+  II ( c, d, a, b, in[ 2], S43, UL( 718787259)); /* 63 */
+  II ( b, c, d, a, in[ 9], S44, UL(3951481745)); /* 64 */
+
+  buf[0] += a;
+  buf[1] += b;
+  buf[2] += c;
+  buf[3] += d;
+}
+
+#endif /* CHAP_SUPPORT || MD5_SUPPORT */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/md5.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/md5.h
new file mode 100644
index 0000000..e129533
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/md5.h
@@ -0,0 +1,55 @@
+/*
+ ***********************************************************************
+ ** md5.h -- header file for implementation of MD5                    **
+ ** RSA Data Security, Inc. MD5 Message-Digest Algorithm              **
+ ** Created: 2/17/90 RLR                                              **
+ ** Revised: 12/27/90 SRD,AJ,BSK,JT Reference C version               **
+ ** Revised (for MD5): RLR 4/27/91                                    **
+ **   -- G modified to have y&~z instead of y&z                       **
+ **   -- FF, GG, HH modified to add in last register done             **
+ **   -- Access pattern: round 2 works mod 5, round 3 works mod 3     **
+ **   -- distinct additive constant for each step                     **
+ **   -- round 4 added, working mod 7                                 **
+ ***********************************************************************
+ */
+
+/*
+ ***********************************************************************
+ ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved.  **
+ **                                                                   **
+ ** License to copy and use this software is granted provided that    **
+ ** it is identified as the "RSA Data Security, Inc. MD5 Message-     **
+ ** Digest Algorithm" in all material mentioning or referencing this  **
+ ** software or this function.                                        **
+ **                                                                   **
+ ** License is also granted to make and use derivative works          **
+ ** provided that such works are identified as "derived from the RSA  **
+ ** Data Security, Inc. MD5 Message-Digest Algorithm" in all          **
+ ** material mentioning or referencing the derived work.              **
+ **                                                                   **
+ ** RSA Data Security, Inc. makes no representations concerning       **
+ ** either the merchantability of this software or the suitability    **
+ ** of this software for any particular purpose.  It is provided "as  **
+ ** is" without express or implied warranty of any kind.              **
+ **                                                                   **
+ ** These notices must be retained in any copies of any part of this  **
+ ** documentation and/or software.                                    **
+ ***********************************************************************
+ */
+
+#ifndef MD5_H
+#define MD5_H
+
+/* Data structure for MD5 (Message-Digest) computation */
+typedef struct {
+  u32_t i[2];               /* number of _bits_ handled mod 2^64 */
+  u32_t buf[4];             /* scratch buffer */
+  unsigned char in[64];     /* input buffer */
+  unsigned char digest[16]; /* actual digest after MD5Final call */
+} MD5_CTX;
+
+void MD5Init  ( MD5_CTX *mdContext);
+void MD5Update( MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen);
+void MD5Final ( unsigned char hash[], MD5_CTX *mdContext);
+
+#endif /* MD5_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/pap.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/pap.c
new file mode 100644
index 0000000..ac44e64
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/pap.c
@@ -0,0 +1,628 @@
+/*****************************************************************************
+* pap.c - Network Password Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-12 Guy Lancaster , Global Election Systems Inc.
+*   Original.
+*****************************************************************************/
+/*
+ * upap.c - User/Password Authentication Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#if PAP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "auth.h"
+#include "pap.h"
+
+#include 
+
+#if 0 /* UNUSED */
+static bool hide_password = 1;
+
+/*
+ * Command-line options.
+ */
+static option_t pap_option_list[] = {
+    { "hide-password", o_bool, &hide_password,
+      "Don't output passwords to log", 1 },
+    { "show-password", o_bool, &hide_password,
+      "Show password string in debug log messages", 0 },
+    { "pap-restart", o_int, &upap[0].us_timeouttime,
+      "Set retransmit timeout for PAP" },
+    { "pap-max-authreq", o_int, &upap[0].us_maxtransmits,
+      "Set max number of transmissions for auth-reqs" },
+    { "pap-timeout", o_int, &upap[0].us_reqtimeout,
+      "Set time limit for peer PAP authentication" },
+    { NULL }
+};
+#endif
+
+/*
+ * Protocol entry points.
+ */
+static void upap_init      (int);
+static void upap_lowerup   (int);
+static void upap_lowerdown (int);
+static void upap_input     (int, u_char *, int);
+static void upap_protrej   (int);
+#if PPP_ADDITIONAL_CALLBACKS
+static int  upap_printpkt (u_char *, int, void (*)(void *, char *, ...), void *);
+#endif /* PPP_ADDITIONAL_CALLBACKS */
+
+struct protent pap_protent = {
+  PPP_PAP,
+  upap_init,
+  upap_input,
+  upap_protrej,
+  upap_lowerup,
+  upap_lowerdown,
+  NULL,
+  NULL,
+#if PPP_ADDITIONAL_CALLBACKS
+  upap_printpkt,
+  NULL,
+#endif /* PPP_ADDITIONAL_CALLBACKS */
+  1,
+  "PAP",
+#if PPP_ADDITIONAL_CALLBACKS
+  NULL,
+  NULL,
+  NULL
+#endif /* PPP_ADDITIONAL_CALLBACKS */
+};
+
+upap_state upap[NUM_PPP]; /* UPAP state; one for each unit */
+
+static void upap_timeout   (void *);
+static void upap_reqtimeout(void *);
+static void upap_rauthreq  (upap_state *, u_char *, u_char, int);
+static void upap_rauthack  (upap_state *, u_char *, int, int);
+static void upap_rauthnak  (upap_state *, u_char *, int, int);
+static void upap_sauthreq  (upap_state *);
+static void upap_sresp     (upap_state *, u_char, u_char, char *, int);
+
+
+/*
+ * upap_init - Initialize a UPAP unit.
+ */
+static void
+upap_init(int unit)
+{
+  upap_state *u = &upap[unit];
+
+  UPAPDEBUG(LOG_INFO, ("upap_init: %d\n", unit));
+  u->us_unit         = unit;
+  u->us_user         = NULL;
+  u->us_userlen      = 0;
+  u->us_passwd       = NULL;
+  u->us_passwdlen    = 0;
+  u->us_clientstate  = UPAPCS_INITIAL;
+  u->us_serverstate  = UPAPSS_INITIAL;
+  u->us_id           = 0;
+  u->us_timeouttime  = UPAP_DEFTIMEOUT;
+  u->us_maxtransmits = 10;
+  u->us_reqtimeout   = UPAP_DEFREQTIME;
+}
+
+/*
+ * upap_authwithpeer - Authenticate us with our peer (start client).
+ *
+ * Set new state and send authenticate's.
+ */
+void
+upap_authwithpeer(int unit, char *user, char *password)
+{
+  upap_state *u = &upap[unit];
+
+  UPAPDEBUG(LOG_INFO, ("upap_authwithpeer: %d user=%s password=%s s=%d\n",
+             unit, user, password, u->us_clientstate));
+
+  /* Save the username and password we're given */
+  u->us_user = user;
+  u->us_userlen = (int)strlen(user);
+  u->us_passwd = password;
+  u->us_passwdlen = (int)strlen(password);
+
+  u->us_transmits = 0;
+
+  /* Lower layer up yet? */
+  if (u->us_clientstate == UPAPCS_INITIAL ||
+      u->us_clientstate == UPAPCS_PENDING) {
+    u->us_clientstate = UPAPCS_PENDING;
+    return;
+  }
+
+  upap_sauthreq(u);      /* Start protocol */
+}
+
+
+/*
+ * upap_authpeer - Authenticate our peer (start server).
+ *
+ * Set new state.
+ */
+void
+upap_authpeer(int unit)
+{
+  upap_state *u = &upap[unit];
+
+  /* Lower layer up yet? */
+  if (u->us_serverstate == UPAPSS_INITIAL ||
+      u->us_serverstate == UPAPSS_PENDING) {
+    u->us_serverstate = UPAPSS_PENDING;
+    return;
+  }
+
+  u->us_serverstate = UPAPSS_LISTEN;
+  if (u->us_reqtimeout > 0) {
+    TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout);
+  }
+}
+
+/*
+ * upap_timeout - Retransmission timer for sending auth-reqs expired.
+ */
+static void
+upap_timeout(void *arg)
+{
+  upap_state *u = (upap_state *) arg;
+
+  UPAPDEBUG(LOG_INFO, ("upap_timeout: %d timeout %d expired s=%d\n", 
+        u->us_unit, u->us_timeouttime, u->us_clientstate));
+
+  if (u->us_clientstate != UPAPCS_AUTHREQ) {
+	UPAPDEBUG(LOG_INFO, ("upap_timeout: not in AUTHREQ state!\n"));
+    return;
+  }
+
+  if (u->us_transmits >= u->us_maxtransmits) {
+    /* give up in disgust */
+    UPAPDEBUG(LOG_ERR, ("No response to PAP authenticate-requests\n"));
+    u->us_clientstate = UPAPCS_BADAUTH;
+    auth_withpeer_fail(u->us_unit, PPP_PAP);
+    return;
+  }
+
+  upap_sauthreq(u);    /* Send Authenticate-Request and set upap timeout*/
+}
+
+
+/*
+ * upap_reqtimeout - Give up waiting for the peer to send an auth-req.
+ */
+static void
+upap_reqtimeout(void *arg)
+{
+  upap_state *u = (upap_state *) arg;
+
+  if (u->us_serverstate != UPAPSS_LISTEN) {
+    return; /* huh?? */
+  }
+
+  auth_peer_fail(u->us_unit, PPP_PAP);
+  u->us_serverstate = UPAPSS_BADAUTH;
+}
+
+
+/*
+ * upap_lowerup - The lower layer is up.
+ *
+ * Start authenticating if pending.
+ */
+static void
+upap_lowerup(int unit)
+{
+  upap_state *u = &upap[unit];
+
+  UPAPDEBUG(LOG_INFO, ("upap_lowerup: init %d clientstate s=%d\n", unit, u->us_clientstate));
+
+  if (u->us_clientstate == UPAPCS_INITIAL) {
+    u->us_clientstate = UPAPCS_CLOSED;
+  } else if (u->us_clientstate == UPAPCS_PENDING) {
+    upap_sauthreq(u);  /* send an auth-request */
+    /* now client state is UPAPCS__AUTHREQ */
+  }
+
+  if (u->us_serverstate == UPAPSS_INITIAL) {
+    u->us_serverstate = UPAPSS_CLOSED;
+  } else if (u->us_serverstate == UPAPSS_PENDING) {
+    u->us_serverstate = UPAPSS_LISTEN;
+    if (u->us_reqtimeout > 0) {
+      TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout);
+    }
+  }
+}
+
+
+/*
+ * upap_lowerdown - The lower layer is down.
+ *
+ * Cancel all timeouts.
+ */
+static void
+upap_lowerdown(int unit)
+{
+  upap_state *u = &upap[unit];
+
+  UPAPDEBUG(LOG_INFO, ("upap_lowerdown: %d s=%d\n", unit, u->us_clientstate));
+
+  if (u->us_clientstate == UPAPCS_AUTHREQ) { /* Timeout pending? */
+    UNTIMEOUT(upap_timeout, u);    /* Cancel timeout */
+  }
+  if (u->us_serverstate == UPAPSS_LISTEN && u->us_reqtimeout > 0) {
+    UNTIMEOUT(upap_reqtimeout, u);
+  }
+
+  u->us_clientstate = UPAPCS_INITIAL;
+  u->us_serverstate = UPAPSS_INITIAL;
+}
+
+
+/*
+ * upap_protrej - Peer doesn't speak this protocol.
+ *
+ * This shouldn't happen.  In any case, pretend lower layer went down.
+ */
+static void
+upap_protrej(int unit)
+{
+  upap_state *u = &upap[unit];
+
+  if (u->us_clientstate == UPAPCS_AUTHREQ) {
+    UPAPDEBUG(LOG_ERR, ("PAP authentication failed due to protocol-reject\n"));
+    auth_withpeer_fail(unit, PPP_PAP);
+  }
+  if (u->us_serverstate == UPAPSS_LISTEN) {
+    UPAPDEBUG(LOG_ERR, ("PAP authentication of peer failed (protocol-reject)\n"));
+    auth_peer_fail(unit, PPP_PAP);
+  }
+  upap_lowerdown(unit);
+}
+
+
+/*
+ * upap_input - Input UPAP packet.
+ */
+static void
+upap_input(int unit, u_char *inpacket, int l)
+{
+  upap_state *u = &upap[unit];
+  u_char *inp;
+  u_char code, id;
+  int len;
+
+  /*
+   * Parse header (code, id and length).
+   * If packet too short, drop it.
+   */
+  inp = inpacket;
+  if (l < (int)UPAP_HEADERLEN) {
+    UPAPDEBUG(LOG_INFO, ("pap_input: rcvd short header.\n"));
+    return;
+  }
+  GETCHAR(code, inp);
+  GETCHAR(id, inp);
+  GETSHORT(len, inp);
+  if (len < (int)UPAP_HEADERLEN) {
+    UPAPDEBUG(LOG_INFO, ("pap_input: rcvd illegal length.\n"));
+    return;
+  }
+  if (len > l) {
+    UPAPDEBUG(LOG_INFO, ("pap_input: rcvd short packet.\n"));
+    return;
+  }
+  len -= UPAP_HEADERLEN;
+
+  /*
+   * Action depends on code.
+   */
+  switch (code) {
+    case UPAP_AUTHREQ:
+      upap_rauthreq(u, inp, id, len);
+      break;
+
+    case UPAP_AUTHACK:
+      upap_rauthack(u, inp, id, len);
+      break;
+
+    case UPAP_AUTHNAK:
+      upap_rauthnak(u, inp, id, len);
+      break;
+
+    default:        /* XXX Need code reject */
+      UPAPDEBUG(LOG_INFO, ("pap_input: UNHANDLED default: code: %d, id: %d, len: %d.\n", code, id, len));
+      break;
+  }
+}
+
+
+/*
+ * upap_rauth - Receive Authenticate.
+ */
+static void
+upap_rauthreq(upap_state *u, u_char *inp, u_char id, int len)
+{
+  u_char ruserlen, rpasswdlen;
+  char *ruser, *rpasswd;
+  u_char retcode;
+  char *msg;
+  int msglen;
+
+  UPAPDEBUG(LOG_INFO, ("pap_rauth: Rcvd id %d.\n", id));
+
+  if (u->us_serverstate < UPAPSS_LISTEN) {
+    return;
+  }
+
+  /*
+   * If we receive a duplicate authenticate-request, we are
+   * supposed to return the same status as for the first request.
+   */
+  if (u->us_serverstate == UPAPSS_OPEN) {
+    upap_sresp(u, UPAP_AUTHACK, id, "", 0);  /* return auth-ack */
+    return;
+  }
+  if (u->us_serverstate == UPAPSS_BADAUTH) {
+    upap_sresp(u, UPAP_AUTHNAK, id, "", 0);  /* return auth-nak */
+    return;
+  }
+
+  /*
+   * Parse user/passwd.
+   */
+  if (len < (int)sizeof (u_char)) {
+    UPAPDEBUG(LOG_INFO, ("pap_rauth: rcvd short packet.\n"));
+    return;
+  }
+  GETCHAR(ruserlen, inp);
+  len -= sizeof (u_char) + ruserlen + sizeof (u_char);
+  if (len < 0) {
+    UPAPDEBUG(LOG_INFO, ("pap_rauth: rcvd short packet.\n"));
+    return;
+  }
+  ruser = (char *) inp;
+  INCPTR(ruserlen, inp);
+  GETCHAR(rpasswdlen, inp);
+  if (len < rpasswdlen) {
+    UPAPDEBUG(LOG_INFO, ("pap_rauth: rcvd short packet.\n"));
+    return;
+  }
+  rpasswd = (char *) inp;
+
+  /*
+   * Check the username and password given.
+   */
+  retcode = check_passwd(u->us_unit, ruser, ruserlen, rpasswd, rpasswdlen, &msg, &msglen);
+  /* lwip: currently retcode is always UPAP_AUTHACK */
+  BZERO(rpasswd, rpasswdlen);
+
+  upap_sresp(u, retcode, id, msg, msglen);
+
+  if (retcode == UPAP_AUTHACK) {
+    u->us_serverstate = UPAPSS_OPEN;
+    auth_peer_success(u->us_unit, PPP_PAP, ruser, ruserlen);
+  } else {
+    u->us_serverstate = UPAPSS_BADAUTH;
+    auth_peer_fail(u->us_unit, PPP_PAP);
+  }
+
+  if (u->us_reqtimeout > 0) {
+    UNTIMEOUT(upap_reqtimeout, u);
+  }
+}
+
+
+/*
+ * upap_rauthack - Receive Authenticate-Ack.
+ */
+static void
+upap_rauthack(upap_state *u, u_char *inp, int id, int len)
+{
+  u_char msglen;
+  char *msg;
+
+  LWIP_UNUSED_ARG(id);
+
+  UPAPDEBUG(LOG_INFO, ("pap_rauthack: Rcvd id %d s=%d\n", id, u->us_clientstate));
+
+  if (u->us_clientstate != UPAPCS_AUTHREQ) { /* XXX */
+    UPAPDEBUG(LOG_INFO, ("pap_rauthack: us_clientstate != UPAPCS_AUTHREQ\n"));
+    return;
+  }
+
+  /*
+   * Parse message.
+   */
+  if (len < (int)sizeof (u_char)) {
+    UPAPDEBUG(LOG_INFO, ("pap_rauthack: ignoring missing msg-length.\n"));
+  } else {
+    GETCHAR(msglen, inp);
+    if (msglen > 0) {
+      len -= sizeof (u_char);
+      if (len < msglen) {
+        UPAPDEBUG(LOG_INFO, ("pap_rauthack: rcvd short packet.\n"));
+        return;
+      }
+      msg = (char *) inp;
+      PRINTMSG(msg, msglen);
+    }
+  }
+  UNTIMEOUT(upap_timeout, u);    /* Cancel timeout */
+  u->us_clientstate = UPAPCS_OPEN;
+
+  auth_withpeer_success(u->us_unit, PPP_PAP);
+}
+
+
+/*
+ * upap_rauthnak - Receive Authenticate-Nak.
+ */
+static void
+upap_rauthnak(upap_state *u, u_char *inp, int id, int len)
+{
+  u_char msglen;
+  char *msg;
+
+  LWIP_UNUSED_ARG(id);
+
+  UPAPDEBUG(LOG_INFO, ("pap_rauthnak: Rcvd id %d s=%d\n", id, u->us_clientstate));
+
+  if (u->us_clientstate != UPAPCS_AUTHREQ) { /* XXX */
+    return;
+  }
+
+  /*
+   * Parse message.
+   */
+  if (len < sizeof (u_char)) {
+    UPAPDEBUG(LOG_INFO, ("pap_rauthnak: ignoring missing msg-length.\n"));
+  } else {
+    GETCHAR(msglen, inp);
+    if(msglen > 0) {
+      len -= sizeof (u_char);
+      if (len < msglen) {
+        UPAPDEBUG(LOG_INFO, ("pap_rauthnak: rcvd short packet.\n"));
+        return;
+      }
+      msg = (char *) inp;
+      PRINTMSG(msg, msglen);
+    }
+  }
+
+  u->us_clientstate = UPAPCS_BADAUTH;
+
+  UPAPDEBUG(LOG_ERR, ("PAP authentication failed\n"));
+  auth_withpeer_fail(u->us_unit, PPP_PAP);
+}
+
+
+/*
+ * upap_sauthreq - Send an Authenticate-Request.
+ */
+static void
+upap_sauthreq(upap_state *u)
+{
+  u_char *outp;
+  int outlen;
+
+  outlen = UPAP_HEADERLEN + 2 * sizeof (u_char) 
+         + u->us_userlen + u->us_passwdlen;
+  outp = outpacket_buf[u->us_unit];
+
+  MAKEHEADER(outp, PPP_PAP);
+
+  PUTCHAR(UPAP_AUTHREQ, outp);
+  PUTCHAR(++u->us_id, outp);
+  PUTSHORT(outlen, outp);
+  PUTCHAR(u->us_userlen, outp);
+  BCOPY(u->us_user, outp, u->us_userlen);
+  INCPTR(u->us_userlen, outp);
+  PUTCHAR(u->us_passwdlen, outp);
+  BCOPY(u->us_passwd, outp, u->us_passwdlen);
+
+  pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN);
+
+  UPAPDEBUG(LOG_INFO, ("pap_sauth: Sent id %d\n", u->us_id));
+
+  TIMEOUT(upap_timeout, u, u->us_timeouttime);
+  ++u->us_transmits;
+  u->us_clientstate = UPAPCS_AUTHREQ;
+}
+
+
+/*
+ * upap_sresp - Send a response (ack or nak).
+ */
+static void
+upap_sresp(upap_state *u, u_char code, u_char id, char *msg, int msglen)
+{
+  u_char *outp;
+  int outlen;
+
+  outlen = UPAP_HEADERLEN + sizeof (u_char) + msglen;
+  outp = outpacket_buf[u->us_unit];
+  MAKEHEADER(outp, PPP_PAP);
+
+  PUTCHAR(code, outp);
+  PUTCHAR(id, outp);
+  PUTSHORT(outlen, outp);
+  PUTCHAR(msglen, outp);
+  BCOPY(msg, outp, msglen);
+  pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN);
+
+  UPAPDEBUG(LOG_INFO, ("pap_sresp: Sent code %d, id %d s=%d\n", code, id, u->us_clientstate));
+}
+
+#if PPP_ADDITIONAL_CALLBACKS
+static char *upap_codenames[] = {
+    "AuthReq", "AuthAck", "AuthNak"
+};
+
+/*
+ * upap_printpkt - print the contents of a PAP packet.
+ */
+static int upap_printpkt(
+  u_char *p,
+  int plen,
+  void (*printer) (void *, char *, ...),
+  void *arg
+)
+{
+  LWIP_UNUSED_ARG(p);
+  LWIP_UNUSED_ARG(plen);
+  LWIP_UNUSED_ARG(printer);
+  LWIP_UNUSED_ARG(arg);
+  return 0;
+}
+#endif /* PPP_ADDITIONAL_CALLBACKS */
+
+#endif /* PAP_SUPPORT */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/pap.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/pap.h
new file mode 100644
index 0000000..c99a204
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/pap.h
@@ -0,0 +1,118 @@
+/*****************************************************************************
+* pap.h -  PPP Password Authentication Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * upap.h - User/Password Authentication Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef PAP_H
+#define PAP_H
+
+#if PAP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+/*
+ * Packet header = Code, id, length.
+ */
+#define UPAP_HEADERLEN (sizeof (u_char) + sizeof (u_char) + sizeof (u_short))
+
+
+/*
+ * UPAP codes.
+ */
+#define UPAP_AUTHREQ 1 /* Authenticate-Request */
+#define UPAP_AUTHACK 2 /* Authenticate-Ack */
+#define UPAP_AUTHNAK 3 /* Authenticate-Nak */
+
+/*
+ * Each interface is described by upap structure.
+ */
+typedef struct upap_state {
+  int us_unit;           /* Interface unit number */
+  const char *us_user;   /* User */
+  int us_userlen;        /* User length */
+  const char *us_passwd; /* Password */
+  int us_passwdlen;      /* Password length */
+  int us_clientstate;    /* Client state */
+  int us_serverstate;    /* Server state */
+  u_char us_id;          /* Current id */
+  int us_timeouttime;    /* Timeout (seconds) for auth-req retrans. */
+  int us_transmits;      /* Number of auth-reqs sent */
+  int us_maxtransmits;   /* Maximum number of auth-reqs to send */
+  int us_reqtimeout;     /* Time to wait for auth-req from peer */
+} upap_state;
+
+/*
+ * Client states.
+ */
+#define UPAPCS_INITIAL 0 /* Connection down */
+#define UPAPCS_CLOSED  1 /* Connection up, haven't requested auth */
+#define UPAPCS_PENDING 2 /* Connection down, have requested auth */
+#define UPAPCS_AUTHREQ 3 /* We've sent an Authenticate-Request */
+#define UPAPCS_OPEN    4 /* We've received an Ack */
+#define UPAPCS_BADAUTH 5 /* We've received a Nak */
+
+/*
+ * Server states.
+ */
+#define UPAPSS_INITIAL 0 /* Connection down */
+#define UPAPSS_CLOSED  1 /* Connection up, haven't requested auth */
+#define UPAPSS_PENDING 2 /* Connection down, have requested auth */
+#define UPAPSS_LISTEN  3 /* Listening for an Authenticate */
+#define UPAPSS_OPEN    4 /* We've sent an Ack */
+#define UPAPSS_BADAUTH 5 /* We've sent a Nak */
+
+
+extern upap_state upap[];
+
+void upap_authwithpeer  (int, char *, char *);
+void upap_authpeer      (int);
+
+extern struct protent pap_protent;
+
+#endif /* PAP_SUPPORT */
+
+#endif /* PAP_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/ppp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/ppp.c
new file mode 100644
index 0000000..e9b433b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/ppp.c
@@ -0,0 +1,2020 @@
+/*****************************************************************************
+* ppp.c - Network Point to Point Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*   Original.
+*****************************************************************************/
+
+/*
+ * ppp_defs.h - PPP definitions.
+ *
+ * if_pppvar.h - private structures and declarations for PPP.
+ *
+ * Copyright (c) 1994 The Australian National University.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, provided that the above copyright
+ * notice appears in all copies.  This software is provided without any
+ * warranty, express or implied. The Australian National University
+ * makes no representations about the suitability of this software for
+ * any purpose.
+ *
+ * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY
+ * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
+ * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
+ * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS,
+ * OR MODIFICATIONS.
+ */
+
+/*
+ * if_ppp.h - Point-to-Point Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/ip.h" /* for ip_input() */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "randm.h"
+#include "fsm.h"
+#if PAP_SUPPORT
+#include "pap.h"
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+#include "chap.h"
+#endif /* CHAP_SUPPORT */
+#include "ipcp.h"
+#include "lcp.h"
+#include "magic.h"
+#include "auth.h"
+#if VJ_SUPPORT
+#include "vj.h"
+#endif /* VJ_SUPPORT */
+#if PPPOE_SUPPORT
+#include "netif/ppp_oe.h"
+#endif /* PPPOE_SUPPORT */
+
+#include "lwip/tcpip.h"
+#include "lwip/api.h"
+#include "lwip/snmp.h"
+
+#include 
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+/** PPP_INPROC_MULTITHREADED==1 call pppInput using tcpip_callback().
+ * Set this to 0 if pppInProc is called inside tcpip_thread or with NO_SYS==1.
+ * Default is 1 for NO_SYS==0 (multithreaded) and 0 for NO_SYS==1 (single-threaded).
+ */
+#ifndef PPP_INPROC_MULTITHREADED
+#define PPP_INPROC_MULTITHREADED (NO_SYS==0)
+#endif
+
+/** PPP_INPROC_OWNTHREAD==1: start a dedicated RX thread per PPP session.
+ * Default is 0: call pppos_input() for received raw characters, charcater
+ * reception is up to the port */
+#ifndef PPP_INPROC_OWNTHREAD
+#define PPP_INPROC_OWNTHREAD      PPP_INPROC_MULTITHREADED
+#endif
+
+#if PPP_INPROC_OWNTHREAD && !PPP_INPROC_MULTITHREADED
+  #error "PPP_INPROC_OWNTHREAD needs PPP_INPROC_MULTITHREADED==1"
+#endif
+
+/*
+ * The basic PPP frame.
+ */
+#define PPP_ADDRESS(p)  (((u_char *)(p))[0])
+#define PPP_CONTROL(p)  (((u_char *)(p))[1])
+#define PPP_PROTOCOL(p) ((((u_char *)(p))[2] << 8) + ((u_char *)(p))[3])
+
+/* PPP packet parser states.  Current state indicates operation yet to be
+ * completed. */
+typedef enum {
+  PDIDLE = 0,  /* Idle state - waiting. */
+  PDSTART,     /* Process start flag. */
+  PDADDRESS,   /* Process address field. */
+  PDCONTROL,   /* Process control field. */
+  PDPROTOCOL1, /* Process protocol field 1. */
+  PDPROTOCOL2, /* Process protocol field 2. */
+  PDDATA       /* Process data byte. */
+} PPPDevStates;
+
+#define ESCAPE_P(accm, c) ((accm)[(c) >> 3] & pppACCMMask[c & 0x07])
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+
+/** RX buffer size: this may be configured smaller! */
+#ifndef PPPOS_RX_BUFSIZE
+#define PPPOS_RX_BUFSIZE    (PPP_MRU + PPP_HDRLEN)
+#endif
+
+typedef struct PPPControlRx_s {
+  /** unit number / ppp descriptor */
+  int pd;
+  /** the rx file descriptor */
+  sio_fd_t fd;
+  /** receive buffer - encoded data is stored here */
+  u_char rxbuf[PPPOS_RX_BUFSIZE];
+
+  /* The input packet. */
+  struct pbuf *inHead, *inTail;
+
+#if PPPOS_SUPPORT
+  u16_t inProtocol;             /* The input protocol code. */
+  u16_t inFCS;                  /* Input Frame Check Sequence value. */
+#endif /* PPPOS_SUPPORT */
+  PPPDevStates inState;         /* The input process state. */
+  char inEscaped;               /* Escape next character. */
+  ext_accm inACCM;              /* Async-Ctl-Char-Map for input. */
+} PPPControlRx;
+
+/*
+ * PPP interface control block.
+ */
+typedef struct PPPControl_s {
+  PPPControlRx rx;
+  char openFlag;                /* True when in use. */
+#if PPPOE_SUPPORT
+  struct netif *ethif;
+  struct pppoe_softc *pppoe_sc;
+#endif /* PPPOE_SUPPORT */
+  int  if_up;                   /* True when the interface is up. */
+  int  errCode;                 /* Code indicating why interface is down. */
+#if PPPOS_SUPPORT
+  sio_fd_t fd;                  /* File device ID of port. */
+#endif /* PPPOS_SUPPORT */
+  u16_t mtu;                    /* Peer's mru */
+  int  pcomp;                   /* Does peer accept protocol compression? */
+  int  accomp;                  /* Does peer accept addr/ctl compression? */
+  u_long lastXMit;              /* Time of last transmission. */
+  ext_accm outACCM;             /* Async-Ctl-Char-Map for output. */
+#if PPPOS_SUPPORT && VJ_SUPPORT
+  int  vjEnabled;               /* Flag indicating VJ compression enabled. */
+  struct vjcompress vjComp;     /* Van Jacobson compression header. */
+#endif /* PPPOS_SUPPORT && VJ_SUPPORT */
+
+  struct netif netif;
+
+  struct ppp_addrs addrs;
+
+  void (*linkStatusCB)(void *ctx, int errCode, void *arg);
+  void *linkStatusCtx;
+
+} PPPControl;
+
+
+/*
+ * Ioctl definitions.
+ */
+
+struct npioctl {
+  int         protocol; /* PPP procotol, e.g. PPP_IP */
+  enum NPmode mode;
+};
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+#if PPPOS_SUPPORT
+#if PPP_INPROC_OWNTHREAD
+static void pppInputThread(void *arg);
+#endif /* PPP_INPROC_OWNTHREAD */
+static void pppDrop(PPPControlRx *pcrx);
+static void pppInProc(PPPControlRx *pcrx, u_char *s, int l);
+#endif /* PPPOS_SUPPORT */
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+u_long subnetMask;
+
+static PPPControl pppControl[NUM_PPP]; /* The PPP interface control blocks. */
+
+/*
+ * PPP Data Link Layer "protocol" table.
+ * One entry per supported protocol.
+ * The last entry must be NULL.
+ */
+struct protent *ppp_protocols[] = {
+  &lcp_protent,
+#if PAP_SUPPORT
+  &pap_protent,
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+  &chap_protent,
+#endif /* CHAP_SUPPORT */
+#if CBCP_SUPPORT
+  &cbcp_protent,
+#endif /* CBCP_SUPPORT */
+  &ipcp_protent,
+#if CCP_SUPPORT
+  &ccp_protent,
+#endif /* CCP_SUPPORT */
+  NULL
+};
+
+
+/*
+ * Buffers for outgoing packets.  This must be accessed only from the appropriate
+ * PPP task so that it doesn't need to be protected to avoid collisions.
+ */
+u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN];
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+
+#if PPPOS_SUPPORT
+/*
+ * FCS lookup table as calculated by genfcstab.
+ * @todo: smaller, slower implementation for lower memory footprint?
+ */
+static const u_short fcstab[256] = {
+  0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
+  0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
+  0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
+  0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
+  0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
+  0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
+  0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
+  0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
+  0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
+  0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
+  0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
+  0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
+  0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
+  0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
+  0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
+  0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
+  0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
+  0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
+  0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
+  0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
+  0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
+  0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
+  0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
+  0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
+  0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
+  0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
+  0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
+  0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
+  0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
+  0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
+  0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
+  0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
+};
+
+/* PPP's Asynchronous-Control-Character-Map.  The mask array is used
+ * to select the specific bit for a character. */
+static u_char pppACCMMask[] = {
+  0x01,
+  0x02,
+  0x04,
+  0x08,
+  0x10,
+  0x20,
+  0x40,
+  0x80
+};
+
+/** Wake up the task blocked in reading from serial line (if any) */
+static void
+pppRecvWakeup(int pd)
+{
+  PPPDEBUG(LOG_DEBUG, ("pppRecvWakeup: unit %d\n", pd));
+  if (pppControl[pd].openFlag != 0) {
+    sio_read_abort(pppControl[pd].fd);
+  }
+}
+#endif /* PPPOS_SUPPORT */
+
+void
+pppLinkTerminated(int pd)
+{
+  PPPDEBUG(LOG_DEBUG, ("pppLinkTerminated: unit %d\n", pd));
+
+#if PPPOE_SUPPORT
+  if (pppControl[pd].ethif) {
+    pppoe_disconnect(pppControl[pd].pppoe_sc);
+  } else
+#endif /* PPPOE_SUPPORT */
+  {
+#if PPPOS_SUPPORT
+    PPPControl* pc;
+    pppRecvWakeup(pd);
+    pc = &pppControl[pd];
+
+    PPPDEBUG(LOG_DEBUG, ("pppLinkTerminated: unit %d: linkStatusCB=%p errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+    if (pc->linkStatusCB) {
+      pc->linkStatusCB(pc->linkStatusCtx, pc->errCode ? pc->errCode : PPPERR_PROTOCOL, NULL);
+    }
+
+    pc->openFlag = 0;/**/
+#endif /* PPPOS_SUPPORT */
+  }
+  PPPDEBUG(LOG_DEBUG, ("pppLinkTerminated: finished.\n"));
+}
+
+void
+pppLinkDown(int pd)
+{
+  PPPDEBUG(LOG_DEBUG, ("pppLinkDown: unit %d\n", pd));
+
+#if PPPOE_SUPPORT
+  if (pppControl[pd].ethif) {
+    pppoe_disconnect(pppControl[pd].pppoe_sc);
+  } else
+#endif /* PPPOE_SUPPORT */
+  {
+#if PPPOS_SUPPORT
+    pppRecvWakeup(pd);
+#endif /* PPPOS_SUPPORT */
+  }
+}
+
+/** Initiate LCP open request */
+static void
+pppStart(int pd)
+{
+  PPPDEBUG(LOG_DEBUG, ("pppStart: unit %d\n", pd));
+  lcp_lowerup(pd);
+  lcp_open(pd); /* Start protocol */
+  PPPDEBUG(LOG_DEBUG, ("pppStart: finished\n"));
+}
+
+/** LCP close request */
+static void
+pppStop(int pd)
+{
+  PPPDEBUG(LOG_DEBUG, ("pppStop: unit %d\n", pd));
+  lcp_close(pd, "User request");
+}
+
+/** Called when carrier/link is lost */
+static void
+pppHup(int pd)
+{
+  PPPDEBUG(LOG_DEBUG, ("pppHupCB: unit %d\n", pd));
+  lcp_lowerdown(pd);
+  link_terminated(pd);
+}
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/* Initialize the PPP subsystem. */
+
+struct ppp_settings ppp_settings;
+
+void
+pppInit(void)
+{
+  struct protent *protp;
+  int i, j;
+
+  memset(&ppp_settings, 0, sizeof(ppp_settings));
+  ppp_settings.usepeerdns = 1;
+  pppSetAuth(PPPAUTHTYPE_NONE, NULL, NULL);
+
+  magicInit();
+
+  subnetMask = PP_HTONL(0xffffff00UL);
+
+  for (i = 0; i < NUM_PPP; i++) {
+    /* Initialize each protocol to the standard option set. */
+    for (j = 0; (protp = ppp_protocols[j]) != NULL; ++j) {
+      (*protp->init)(i);
+    }
+  }
+}
+
+void
+pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd)
+{
+  switch(authType) {
+    case PPPAUTHTYPE_NONE:
+    default:
+#ifdef LWIP_PPP_STRICT_PAP_REJECT
+      ppp_settings.refuse_pap = 1;
+#else  /* LWIP_PPP_STRICT_PAP_REJECT */
+      /* some providers request pap and accept an empty login/pw */
+      ppp_settings.refuse_pap = 0;
+#endif /* LWIP_PPP_STRICT_PAP_REJECT */
+      ppp_settings.refuse_chap = 1;
+      break;
+
+    case PPPAUTHTYPE_ANY:
+      /* Warning: Using PPPAUTHTYPE_ANY might have security consequences.
+       * RFC 1994 says:
+       *
+       * In practice, within or associated with each PPP server, there is a
+       * database which associates "user" names with authentication
+       * information ("secrets").  It is not anticipated that a particular
+       * named user would be authenticated by multiple methods.  This would
+       * make the user vulnerable to attacks which negotiate the least secure
+       * method from among a set (such as PAP rather than CHAP).  If the same
+       * secret was used, PAP would reveal the secret to be used later with
+       * CHAP.
+       *
+       * Instead, for each user name there should be an indication of exactly
+       * one method used to authenticate that user name.  If a user needs to
+       * make use of different authentication methods under different
+       * circumstances, then distinct user names SHOULD be employed, each of
+       * which identifies exactly one authentication method.
+       *
+       */
+      ppp_settings.refuse_pap = 0;
+      ppp_settings.refuse_chap = 0;
+      break;
+
+    case PPPAUTHTYPE_PAP:
+      ppp_settings.refuse_pap = 0;
+      ppp_settings.refuse_chap = 1;
+      break;
+
+    case PPPAUTHTYPE_CHAP:
+      ppp_settings.refuse_pap = 1;
+      ppp_settings.refuse_chap = 0;
+      break;
+  }
+
+  if(user) {
+    strncpy(ppp_settings.user, user, sizeof(ppp_settings.user)-1);
+    ppp_settings.user[sizeof(ppp_settings.user)-1] = '\0';
+  } else {
+    ppp_settings.user[0] = '\0';
+  }
+
+  if(passwd) {
+    strncpy(ppp_settings.passwd, passwd, sizeof(ppp_settings.passwd)-1);
+    ppp_settings.passwd[sizeof(ppp_settings.passwd)-1] = '\0';
+  } else {
+    ppp_settings.passwd[0] = '\0';
+  }
+}
+
+#if PPPOS_SUPPORT
+/** Open a new PPP connection using the given I/O device.
+ * This initializes the PPP control block but does not
+ * attempt to negotiate the LCP session.  If this port
+ * connects to a modem, the modem connection must be
+ * established before calling this.
+ * Return a new PPP connection descriptor on success or
+ * an error code (negative) on failure.
+ *
+ * pppOpen() is directly defined to this function.
+ */
+int
+pppOverSerialOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx)
+{
+  PPPControl *pc;
+  int pd;
+
+  if (linkStatusCB == NULL) {
+    /* PPP is single-threaded: without a callback,
+     * there is no way to know when the link is up. */
+    return PPPERR_PARAM;
+  }
+
+  /* Find a free PPP session descriptor. */
+  for (pd = 0; pd < NUM_PPP && pppControl[pd].openFlag != 0; pd++);
+
+  if (pd >= NUM_PPP) {
+    pd = PPPERR_OPEN;
+  } else {
+    pc = &pppControl[pd];
+    /* @todo: is this correct or do I overwrite something? */
+    memset(pc, 0, sizeof(PPPControl));
+    pc->rx.pd = pd;
+    pc->rx.fd = fd;
+
+    pc->openFlag = 1;
+    pc->fd = fd;
+
+#if VJ_SUPPORT
+    vj_compress_init(&pc->vjComp);
+#endif /* VJ_SUPPORT */
+
+    /* 
+     * Default the in and out accm so that escape and flag characters
+     * are always escaped. 
+     */
+    pc->rx.inACCM[15] = 0x60; /* no need to protect since RX is not running */
+    pc->outACCM[15] = 0x60;
+
+    pc->linkStatusCB = linkStatusCB;
+    pc->linkStatusCtx = linkStatusCtx;
+
+    /*
+     * Start the connection and handle incoming events (packet or timeout).
+     */
+    PPPDEBUG(LOG_INFO, ("pppOverSerialOpen: unit %d: Connecting\n", pd));
+    pppStart(pd);
+#if PPP_INPROC_OWNTHREAD
+    sys_thread_new(PPP_THREAD_NAME, pppInputThread, (void*)&pc->rx, PPP_THREAD_STACKSIZE, PPP_THREAD_PRIO);
+#endif
+  }
+
+  return pd;
+}
+#endif /* PPPOS_SUPPORT */
+
+#if PPPOE_SUPPORT
+static void pppOverEthernetLinkStatusCB(int pd, int up);
+
+void
+pppOverEthernetClose(int pd)
+{
+  PPPControl* pc = &pppControl[pd];
+
+  /* *TJL* There's no lcp_deinit */
+  lcp_close(pd, NULL);
+
+  pppoe_destroy(&pc->netif);
+}
+
+int pppOverEthernetOpen(struct netif *ethif, const char *service_name, const char *concentrator_name, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx)
+{
+  PPPControl *pc;
+  int pd;
+
+  LWIP_UNUSED_ARG(service_name);
+  LWIP_UNUSED_ARG(concentrator_name);
+
+  if (linkStatusCB == NULL) {
+    /* PPP is single-threaded: without a callback,
+     * there is no way to know when the link is up. */
+    return PPPERR_PARAM;
+  }
+
+  /* Find a free PPP session descriptor. Critical region? */
+  for (pd = 0; pd < NUM_PPP && pppControl[pd].openFlag != 0; pd++);
+  if (pd >= NUM_PPP) {
+    pd = PPPERR_OPEN;
+  } else {
+    pc = &pppControl[pd];
+    memset(pc, 0, sizeof(PPPControl));
+    pc->openFlag = 1;
+    pc->ethif = ethif;
+
+    pc->linkStatusCB  = linkStatusCB;
+    pc->linkStatusCtx = linkStatusCtx;
+
+    lcp_wantoptions[pd].mru = PPPOE_MAXMTU;
+    lcp_wantoptions[pd].neg_asyncmap = 0;
+    lcp_wantoptions[pd].neg_pcompression = 0;
+    lcp_wantoptions[pd].neg_accompression = 0;
+
+    lcp_allowoptions[pd].mru = PPPOE_MAXMTU;
+    lcp_allowoptions[pd].neg_asyncmap = 0;
+    lcp_allowoptions[pd].neg_pcompression = 0;
+    lcp_allowoptions[pd].neg_accompression = 0;
+
+    if(pppoe_create(ethif, pd, pppOverEthernetLinkStatusCB, &pc->pppoe_sc) != ERR_OK) {
+      pc->openFlag = 0;
+      return PPPERR_OPEN;
+    }
+
+    pppoe_connect(pc->pppoe_sc);
+  }
+
+  return pd;
+}
+#endif /* PPPOE_SUPPORT */
+
+
+/* Close a PPP connection and release the descriptor. 
+ * Any outstanding packets in the queues are dropped.
+ * Return 0 on success, an error code on failure. */
+int
+pppClose(int pd)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 0;
+
+  PPPDEBUG(LOG_DEBUG, ("pppClose() called\n"));
+
+  /* Disconnect */
+#if PPPOE_SUPPORT
+  if(pc->ethif) {
+    PPPDEBUG(LOG_DEBUG, ("pppClose: unit %d kill_link -> pppStop\n", pd));
+    pc->errCode = PPPERR_USER;
+    /* This will leave us at PHASE_DEAD. */
+    pppStop(pd);
+  } else
+#endif /* PPPOE_SUPPORT */
+  {
+#if PPPOS_SUPPORT
+    PPPDEBUG(LOG_DEBUG, ("pppClose: unit %d kill_link -> pppStop\n", pd));
+    pc->errCode = PPPERR_USER;
+    /* This will leave us at PHASE_DEAD. */
+    pppStop(pd);
+    pppRecvWakeup(pd);
+#endif /* PPPOS_SUPPORT */
+  }
+
+  return st;
+}
+
+/* This function is called when carrier is lost on the PPP channel. */
+void
+pppSigHUP(int pd)
+{
+  PPPDEBUG(LOG_DEBUG, ("pppSigHUP: unit %d sig_hup -> pppHupCB\n", pd));
+  pppHup(pd);
+}
+
+#if PPPOS_SUPPORT
+static void
+nPut(PPPControl *pc, struct pbuf *nb)
+{
+  struct pbuf *b;
+  int c;
+
+  for(b = nb; b != NULL; b = b->next) {
+    if((c = sio_write(pc->fd, b->payload, b->len)) != b->len) {
+      PPPDEBUG(LOG_WARNING,
+               ("PPP nPut: incomplete sio_write(fd:%"SZT_F", len:%d, c: 0x%"X8_F") c = %d\n", (size_t)pc->fd, b->len, c, c));
+      LINK_STATS_INC(link.err);
+      pc->lastXMit = 0; /* prepend PPP_FLAG to next packet */
+      snmp_inc_ifoutdiscards(&pc->netif);
+      pbuf_free(nb);
+      return;
+    }
+  }
+
+  snmp_add_ifoutoctets(&pc->netif, nb->tot_len);
+  snmp_inc_ifoutucastpkts(&pc->netif);
+  pbuf_free(nb);
+  LINK_STATS_INC(link.xmit);
+}
+
+/* 
+ * pppAppend - append given character to end of given pbuf.  If outACCM
+ * is not NULL and the character needs to be escaped, do so.
+ * If pbuf is full, append another.
+ * Return the current pbuf.
+ */
+static struct pbuf *
+pppAppend(u_char c, struct pbuf *nb, ext_accm *outACCM)
+{
+  struct pbuf *tb = nb;
+  
+  /* Make sure there is room for the character and an escape code.
+   * Sure we don't quite fill the buffer if the character doesn't
+   * get escaped but is one character worth complicating this? */
+  /* Note: We assume no packet header. */
+  if (nb && (PBUF_POOL_BUFSIZE - nb->len) < 2) {
+    tb = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+    if (tb) {
+      nb->next = tb;
+    } else {
+      LINK_STATS_INC(link.memerr);
+    }
+    nb = tb;
+  }
+
+  if (nb) {
+    if (outACCM && ESCAPE_P(*outACCM, c)) {
+      *((u_char*)nb->payload + nb->len++) = PPP_ESCAPE;
+      *((u_char*)nb->payload + nb->len++) = c ^ PPP_TRANS;
+    } else {
+      *((u_char*)nb->payload + nb->len++) = c;
+    }
+  }
+
+  return tb;
+}
+#endif /* PPPOS_SUPPORT */
+
+#if PPPOE_SUPPORT
+static err_t
+pppifOutputOverEthernet(int pd, struct pbuf *p)
+{
+  PPPControl *pc = &pppControl[pd];
+  struct pbuf *pb;
+  u_short protocol = PPP_IP;
+  int i=0;
+  u16_t tot_len;
+
+  /* @todo: try to use pbuf_header() here! */
+  pb = pbuf_alloc(PBUF_LINK, PPPOE_HDRLEN + sizeof(protocol), PBUF_RAM);
+  if(!pb) {
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.proterr);
+    snmp_inc_ifoutdiscards(&pc->netif);
+    return ERR_MEM;
+  }
+
+  pbuf_header(pb, -(s16_t)PPPOE_HDRLEN);
+
+  pc->lastXMit = sys_jiffies();
+
+  if (!pc->pcomp || protocol > 0xFF) {
+    *((u_char*)pb->payload + i++) = (protocol >> 8) & 0xFF;
+  }
+  *((u_char*)pb->payload + i) = protocol & 0xFF;
+
+  pbuf_chain(pb, p);
+  tot_len = pb->tot_len;
+
+  if(pppoe_xmit(pc->pppoe_sc, pb) != ERR_OK) {
+    LINK_STATS_INC(link.err);
+    snmp_inc_ifoutdiscards(&pc->netif);
+    return PPPERR_DEVICE;
+  }
+
+  snmp_add_ifoutoctets(&pc->netif, tot_len);
+  snmp_inc_ifoutucastpkts(&pc->netif);
+  LINK_STATS_INC(link.xmit);
+  return ERR_OK;
+}
+#endif /* PPPOE_SUPPORT */
+
+/* Send a packet on the given connection. */
+static err_t
+pppifOutput(struct netif *netif, struct pbuf *pb, ip_addr_t *ipaddr)
+{
+  int pd = (int)(size_t)netif->state;
+  PPPControl *pc = &pppControl[pd];
+#if PPPOS_SUPPORT
+  u_short protocol = PPP_IP;
+  u_int fcsOut = PPP_INITFCS;
+  struct pbuf *headMB = NULL, *tailMB = NULL, *p;
+  u_char c;
+#endif /* PPPOS_SUPPORT */
+
+  LWIP_UNUSED_ARG(ipaddr);
+
+  /* Validate parameters. */
+  /* We let any protocol value go through - it can't hurt us
+   * and the peer will just drop it if it's not accepting it. */
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag || !pb) {
+    PPPDEBUG(LOG_WARNING, ("pppifOutput[%d]: bad parms prot=%d pb=%p\n",
+              pd, PPP_IP, pb));
+    LINK_STATS_INC(link.opterr);
+    LINK_STATS_INC(link.drop);
+    snmp_inc_ifoutdiscards(netif);
+    return ERR_ARG;
+  }
+
+  /* Check that the link is up. */
+  if (lcp_phase[pd] == PHASE_DEAD) {
+    PPPDEBUG(LOG_ERR, ("pppifOutput[%d]: link not up\n", pd));
+    LINK_STATS_INC(link.rterr);
+    LINK_STATS_INC(link.drop);
+    snmp_inc_ifoutdiscards(netif);
+    return ERR_RTE;
+  }
+
+#if PPPOE_SUPPORT
+  if(pc->ethif) {
+    return pppifOutputOverEthernet(pd, pb);
+  }
+#endif /* PPPOE_SUPPORT */
+
+#if PPPOS_SUPPORT
+  /* Grab an output buffer. */
+  headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+  if (headMB == NULL) {
+    PPPDEBUG(LOG_WARNING, ("pppifOutput[%d]: first alloc fail\n", pd));
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.drop);
+    snmp_inc_ifoutdiscards(netif);
+    return ERR_MEM;
+  }
+
+#if VJ_SUPPORT
+  /* 
+   * Attempt Van Jacobson header compression if VJ is configured and
+   * this is an IP packet. 
+   */
+  if (protocol == PPP_IP && pc->vjEnabled) {
+    switch (vj_compress_tcp(&pc->vjComp, pb)) {
+      case TYPE_IP:
+        /* No change...
+           protocol = PPP_IP_PROTOCOL; */
+        break;
+      case TYPE_COMPRESSED_TCP:
+        protocol = PPP_VJC_COMP;
+        break;
+      case TYPE_UNCOMPRESSED_TCP:
+        protocol = PPP_VJC_UNCOMP;
+        break;
+      default:
+        PPPDEBUG(LOG_WARNING, ("pppifOutput[%d]: bad IP packet\n", pd));
+        LINK_STATS_INC(link.proterr);
+        LINK_STATS_INC(link.drop);
+        snmp_inc_ifoutdiscards(netif);
+        pbuf_free(headMB);
+        return ERR_VAL;
+    }
+  }
+#endif /* VJ_SUPPORT */
+
+  tailMB = headMB;
+
+  /* Build the PPP header. */
+  if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG) {
+    tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+  }
+
+  pc->lastXMit = sys_jiffies();
+  if (!pc->accomp) {
+    fcsOut = PPP_FCS(fcsOut, PPP_ALLSTATIONS);
+    tailMB = pppAppend(PPP_ALLSTATIONS, tailMB, &pc->outACCM);
+    fcsOut = PPP_FCS(fcsOut, PPP_UI);
+    tailMB = pppAppend(PPP_UI, tailMB, &pc->outACCM);
+  }
+  if (!pc->pcomp || protocol > 0xFF) {
+    c = (protocol >> 8) & 0xFF;
+    fcsOut = PPP_FCS(fcsOut, c);
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+  }
+  c = protocol & 0xFF;
+  fcsOut = PPP_FCS(fcsOut, c);
+  tailMB = pppAppend(c, tailMB, &pc->outACCM);
+
+  /* Load packet. */
+  for(p = pb; p; p = p->next) {
+    int n;
+    u_char *sPtr;
+
+    sPtr = (u_char*)p->payload;
+    n = p->len;
+    while (n-- > 0) {
+      c = *sPtr++;
+
+      /* Update FCS before checking for special characters. */
+      fcsOut = PPP_FCS(fcsOut, c);
+      
+      /* Copy to output buffer escaping special characters. */
+      tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    }
+  }
+
+  /* Add FCS and trailing flag. */
+  c = ~fcsOut & 0xFF;
+  tailMB = pppAppend(c, tailMB, &pc->outACCM);
+  c = (~fcsOut >> 8) & 0xFF;
+  tailMB = pppAppend(c, tailMB, &pc->outACCM);
+  tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+
+  /* If we failed to complete the packet, throw it away. */
+  if (!tailMB) {
+    PPPDEBUG(LOG_WARNING,
+             ("pppifOutput[%d]: Alloc err - dropping proto=%d\n", 
+              pd, protocol));
+    pbuf_free(headMB);
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.drop);
+    snmp_inc_ifoutdiscards(netif);
+    return ERR_MEM;
+  }
+
+  /* Send it. */
+  PPPDEBUG(LOG_INFO, ("pppifOutput[%d]: proto=0x%"X16_F"\n", pd, protocol));
+
+  nPut(pc, headMB);
+#endif /* PPPOS_SUPPORT */
+
+  return ERR_OK;
+}
+
+/* Get and set parameters for the given connection.
+ * Return 0 on success, an error code on failure. */
+int
+pppIOCtl(int pd, int cmd, void *arg)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 0;
+
+  if (pd < 0 || pd >= NUM_PPP) {
+    st = PPPERR_PARAM;
+  } else {
+    switch(cmd) {
+    case PPPCTLG_UPSTATUS:      /* Get the PPP up status. */
+      if (arg) {
+        *(int *)arg = (int)(pc->if_up);
+      } else {
+        st = PPPERR_PARAM;
+      }
+      break;
+    case PPPCTLS_ERRCODE:       /* Set the PPP error code. */
+      if (arg) {
+        pc->errCode = *(int *)arg;
+      } else {
+        st = PPPERR_PARAM;
+      }
+      break;
+    case PPPCTLG_ERRCODE:       /* Get the PPP error code. */
+      if (arg) {
+        *(int *)arg = (int)(pc->errCode);
+      } else {
+        st = PPPERR_PARAM;
+      }
+      break;
+#if PPPOS_SUPPORT
+    case PPPCTLG_FD:            /* Get the fd associated with the ppp */
+      if (arg) {
+        *(sio_fd_t *)arg = pc->fd;
+      } else {
+        st = PPPERR_PARAM;
+      }
+      break;
+#endif /* PPPOS_SUPPORT */
+    default:
+      st = PPPERR_PARAM;
+      break;
+    }
+  }
+
+  return st;
+}
+
+/*
+ * Return the Maximum Transmission Unit for the given PPP connection.
+ */
+u_short
+pppMTU(int pd)
+{
+  PPPControl *pc = &pppControl[pd];
+  u_short st;
+
+  /* Validate parameters. */
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+    st = 0;
+  } else {
+    st = pc->mtu;
+  }
+
+  return st;
+}
+
+#if PPPOE_SUPPORT
+int
+pppWriteOverEthernet(int pd, const u_char *s, int n)
+{
+  PPPControl *pc = &pppControl[pd];
+  struct pbuf *pb;
+
+  /* skip address & flags */
+  s += 2;
+  n -= 2;
+
+  LWIP_ASSERT("PPPOE_HDRLEN + n <= 0xffff", PPPOE_HDRLEN + n <= 0xffff);
+  pb = pbuf_alloc(PBUF_LINK, (u16_t)(PPPOE_HDRLEN + n), PBUF_RAM);
+  if(!pb) {
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.proterr);
+    snmp_inc_ifoutdiscards(&pc->netif);
+    return PPPERR_ALLOC;
+  }
+
+  pbuf_header(pb, -(s16_t)PPPOE_HDRLEN);
+
+  pc->lastXMit = sys_jiffies();
+
+  MEMCPY(pb->payload, s, n);
+
+  if(pppoe_xmit(pc->pppoe_sc, pb) != ERR_OK) {
+    LINK_STATS_INC(link.err);
+    snmp_inc_ifoutdiscards(&pc->netif);
+    return PPPERR_DEVICE;
+  }
+
+  snmp_add_ifoutoctets(&pc->netif, (u16_t)n);
+  snmp_inc_ifoutucastpkts(&pc->netif);
+  LINK_STATS_INC(link.xmit);
+  return PPPERR_NONE;
+}
+#endif /* PPPOE_SUPPORT */
+
+/*
+ * Write n characters to a ppp link.
+ *  RETURN: >= 0 Number of characters written
+ *           -1 Failed to write to device
+ */
+int
+pppWrite(int pd, const u_char *s, int n)
+{
+  PPPControl *pc = &pppControl[pd];
+#if PPPOS_SUPPORT
+  u_char c;
+  u_int fcsOut;
+  struct pbuf *headMB, *tailMB;
+#endif /* PPPOS_SUPPORT */
+
+#if PPPOE_SUPPORT
+  if(pc->ethif) {
+    return pppWriteOverEthernet(pd, s, n);
+  }
+#endif /* PPPOE_SUPPORT */
+
+#if PPPOS_SUPPORT
+  headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+  if (headMB == NULL) {
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.proterr);
+    snmp_inc_ifoutdiscards(&pc->netif);
+    return PPPERR_ALLOC;
+  }
+
+  tailMB = headMB;
+
+  /* If the link has been idle, we'll send a fresh flag character to
+   * flush any noise. */
+  if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG) {
+    tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+  }
+  pc->lastXMit = sys_jiffies();
+
+  fcsOut = PPP_INITFCS;
+  /* Load output buffer. */
+  while (n-- > 0) {
+    c = *s++;
+
+    /* Update FCS before checking for special characters. */
+    fcsOut = PPP_FCS(fcsOut, c);
+
+    /* Copy to output buffer escaping special characters. */
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+  }
+    
+  /* Add FCS and trailing flag. */
+  c = ~fcsOut & 0xFF;
+  tailMB = pppAppend(c, tailMB, &pc->outACCM);
+  c = (~fcsOut >> 8) & 0xFF;
+  tailMB = pppAppend(c, tailMB, &pc->outACCM);
+  tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+
+  /* If we failed to complete the packet, throw it away.
+   * Otherwise send it. */
+  if (!tailMB) {
+    PPPDEBUG(LOG_WARNING,
+             ("pppWrite[%d]: Alloc err - dropping pbuf len=%d\n", pd, headMB->len));
+           /*"pppWrite[%d]: Alloc err - dropping %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */
+    pbuf_free(headMB);
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.proterr);
+    snmp_inc_ifoutdiscards(&pc->netif);
+    return PPPERR_ALLOC;
+  }
+
+  PPPDEBUG(LOG_INFO, ("pppWrite[%d]: len=%d\n", pd, headMB->len));
+                   /* "pppWrite[%d]: %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */
+  nPut(pc, headMB);
+#endif /* PPPOS_SUPPORT */
+
+  return PPPERR_NONE;
+}
+
+/*
+ * ppp_send_config - configure the transmit characteristics of
+ * the ppp interface.
+ */
+void
+ppp_send_config( int unit, u16_t mtu, u32_t asyncmap, int pcomp, int accomp)
+{
+  PPPControl *pc = &pppControl[unit];
+  int i;
+  
+  pc->mtu = mtu;
+  pc->pcomp = pcomp;
+  pc->accomp = accomp;
+  
+  /* Load the ACCM bits for the 32 control codes. */
+  for (i = 0; i < 32/8; i++) {
+    pc->outACCM[i] = (u_char)((asyncmap >> (8 * i)) & 0xFF);
+  }
+  PPPDEBUG(LOG_INFO, ("ppp_send_config[%d]: outACCM=%X %X %X %X\n",
+            unit,
+            pc->outACCM[0], pc->outACCM[1], pc->outACCM[2], pc->outACCM[3]));
+}
+
+
+/*
+ * ppp_set_xaccm - set the extended transmit ACCM for the interface.
+ */
+void
+ppp_set_xaccm(int unit, ext_accm *accm)
+{
+  SMEMCPY(pppControl[unit].outACCM, accm, sizeof(ext_accm));
+  PPPDEBUG(LOG_INFO, ("ppp_set_xaccm[%d]: outACCM=%X %X %X %X\n",
+            unit,
+            pppControl[unit].outACCM[0],
+            pppControl[unit].outACCM[1],
+            pppControl[unit].outACCM[2],
+            pppControl[unit].outACCM[3]));
+}
+
+
+/*
+ * ppp_recv_config - configure the receive-side characteristics of
+ * the ppp interface.
+ */
+void
+ppp_recv_config( int unit, int mru, u32_t asyncmap, int pcomp, int accomp)
+{
+  PPPControl *pc = &pppControl[unit];
+  int i;
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  LWIP_UNUSED_ARG(accomp);
+  LWIP_UNUSED_ARG(pcomp);
+  LWIP_UNUSED_ARG(mru);
+
+  /* Load the ACCM bits for the 32 control codes. */
+  SYS_ARCH_PROTECT(lev);
+  for (i = 0; i < 32 / 8; i++) {
+    /* @todo: does this work? ext_accm has been modified from pppd! */
+    pc->rx.inACCM[i] = (u_char)(asyncmap >> (i * 8));
+  }
+  SYS_ARCH_UNPROTECT(lev);
+  PPPDEBUG(LOG_INFO, ("ppp_recv_config[%d]: inACCM=%X %X %X %X\n",
+            unit,
+            pc->rx.inACCM[0], pc->rx.inACCM[1], pc->rx.inACCM[2], pc->rx.inACCM[3]));
+}
+
+#if 0
+/*
+ * ccp_test - ask kernel whether a given compression method
+ * is acceptable for use.  Returns 1 if the method and parameters
+ * are OK, 0 if the method is known but the parameters are not OK
+ * (e.g. code size should be reduced), or -1 if the method is unknown.
+ */
+int
+ccp_test( int unit, int opt_len,  int for_transmit, u_char *opt_ptr)
+{
+  return 0; /* XXX Currently no compression. */
+}
+
+/*
+ * ccp_flags_set - inform kernel about the current state of CCP.
+ */
+void
+ccp_flags_set(int unit, int isopen, int isup)
+{
+  /* XXX */
+}
+
+/*
+ * ccp_fatal_error - returns 1 if decompression was disabled as a
+ * result of an error detected after decompression of a packet,
+ * 0 otherwise.  This is necessary because of patent nonsense.
+ */
+int
+ccp_fatal_error(int unit)
+{
+  /* XXX */
+  return 0;
+}
+#endif
+
+/*
+ * get_idle_time - return how long the link has been idle.
+ */
+int
+get_idle_time(int u, struct ppp_idle *ip)
+{
+  /* XXX */
+  LWIP_UNUSED_ARG(u);
+  LWIP_UNUSED_ARG(ip);
+
+  return 0;
+}
+
+
+/*
+ * Return user specified netmask, modified by any mask we might determine
+ * for address `addr' (in network byte order).
+ * Here we scan through the system's list of interfaces, looking for
+ * any non-point-to-point interfaces which might appear to be on the same
+ * network as `addr'.  If we find any, we OR in their netmask to the
+ * user-specified netmask.
+ */
+u32_t
+GetMask(u32_t addr)
+{
+  u32_t mask, nmask;
+
+  htonl(addr);
+  if (IP_CLASSA(addr)) { /* determine network mask for address class */
+    nmask = IP_CLASSA_NET;
+  } else if (IP_CLASSB(addr)) {
+    nmask = IP_CLASSB_NET;
+  } else { 
+    nmask = IP_CLASSC_NET;
+  }
+
+  /* class D nets are disallowed by bad_ip_adrs */
+  mask = subnetMask | htonl(nmask);
+  
+  /* XXX
+   * Scan through the system's network interfaces.
+   * Get each netmask and OR them into our mask.
+   */
+
+  return mask;
+}
+
+/*
+ * sifvjcomp - config tcp header compression
+ */
+int
+sifvjcomp(int pd, int vjcomp, u8_t cidcomp, u8_t maxcid)
+{
+#if PPPOS_SUPPORT && VJ_SUPPORT
+  PPPControl *pc = &pppControl[pd];
+  
+  pc->vjEnabled = vjcomp;
+  pc->vjComp.compressSlot = cidcomp;
+  pc->vjComp.maxSlotIndex = maxcid;
+  PPPDEBUG(LOG_INFO, ("sifvjcomp: VJ compress enable=%d slot=%d max slot=%d\n",
+            vjcomp, cidcomp, maxcid));
+#else /* PPPOS_SUPPORT && VJ_SUPPORT */
+  LWIP_UNUSED_ARG(pd);
+  LWIP_UNUSED_ARG(vjcomp);
+  LWIP_UNUSED_ARG(cidcomp);
+  LWIP_UNUSED_ARG(maxcid);
+#endif /* PPPOS_SUPPORT && VJ_SUPPORT */
+
+  return 0;
+}
+
+/*
+ * pppifNetifInit - netif init callback
+ */
+static err_t
+pppifNetifInit(struct netif *netif)
+{
+  netif->name[0] = 'p';
+  netif->name[1] = 'p';
+  netif->output = pppifOutput;
+  netif->mtu = pppMTU((int)(size_t)netif->state);
+  netif->flags = NETIF_FLAG_POINTTOPOINT | NETIF_FLAG_LINK_UP;
+#if LWIP_NETIF_HOSTNAME
+  /* @todo: Initialize interface hostname */
+  /* netif_set_hostname(netif, "lwip"); */
+#endif /* LWIP_NETIF_HOSTNAME */
+  return ERR_OK;
+}
+
+
+/*
+ * sifup - Config the interface up and enable IP packets to pass.
+ */
+int
+sifup(int pd)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 1;
+  
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+    st = 0;
+    PPPDEBUG(LOG_WARNING, ("sifup[%d]: bad parms\n", pd));
+  } else {
+    netif_remove(&pc->netif);
+    if (netif_add(&pc->netif, &pc->addrs.our_ipaddr, &pc->addrs.netmask,
+                  &pc->addrs.his_ipaddr, (void *)(size_t)pd, pppifNetifInit, ip_input)) {
+      netif_set_up(&pc->netif);
+      pc->if_up = 1;
+      pc->errCode = PPPERR_NONE;
+
+      PPPDEBUG(LOG_DEBUG, ("sifup: unit %d: linkStatusCB=%p errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+      if (pc->linkStatusCB) {
+        pc->linkStatusCB(pc->linkStatusCtx, pc->errCode, &pc->addrs);
+      }
+    } else {
+      st = 0;
+      PPPDEBUG(LOG_ERR, ("sifup[%d]: netif_add failed\n", pd));
+    }
+  }
+
+  return st;
+}
+
+/*
+ * sifnpmode - Set the mode for handling packets for a given NP.
+ */
+int
+sifnpmode(int u, int proto, enum NPmode mode)
+{
+  LWIP_UNUSED_ARG(u);
+  LWIP_UNUSED_ARG(proto);
+  LWIP_UNUSED_ARG(mode);
+  return 0;
+}
+
+/*
+ * sifdown - Config the interface down and disable IP.
+ */
+int
+sifdown(int pd)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 1;
+  
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+    st = 0;
+    PPPDEBUG(LOG_WARNING, ("sifdown[%d]: bad parms\n", pd));
+  } else {
+    pc->if_up = 0;
+    /* make sure the netif status callback is called */
+    netif_set_down(&pc->netif);
+    netif_remove(&pc->netif);
+    PPPDEBUG(LOG_DEBUG, ("sifdown: unit %d: linkStatusCB=%p errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+    if (pc->linkStatusCB) {
+      pc->linkStatusCB(pc->linkStatusCtx, PPPERR_CONNECT, NULL);
+    }
+  }
+  return st;
+}
+
+/**
+ * sifaddr - Config the interface IP addresses and netmask.
+ * @param pd Interface unit ???
+ * @param o Our IP address ???
+ * @param h His IP address ???
+ * @param m IP subnet mask ???
+ * @param ns1 Primary DNS
+ * @param ns2 Secondary DNS
+ */
+int
+sifaddr( int pd, u32_t o, u32_t h, u32_t m, u32_t ns1, u32_t ns2)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 1;
+  
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+    st = 0;
+    PPPDEBUG(LOG_WARNING, ("sifup[%d]: bad parms\n", pd));
+  } else {
+    SMEMCPY(&pc->addrs.our_ipaddr, &o, sizeof(o));
+    SMEMCPY(&pc->addrs.his_ipaddr, &h, sizeof(h));
+    SMEMCPY(&pc->addrs.netmask, &m, sizeof(m));
+    SMEMCPY(&pc->addrs.dns1, &ns1, sizeof(ns1));
+    SMEMCPY(&pc->addrs.dns2, &ns2, sizeof(ns2));
+  }
+  return st;
+}
+
+/**
+ * cifaddr - Clear the interface IP addresses, and delete routes
+ * through the interface if possible.
+ * @param pd Interface unit ???
+ * @param o Our IP address ???
+ * @param h IP broadcast address ???
+ */
+int
+cifaddr( int pd, u32_t o, u32_t h)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 1;
+  
+  LWIP_UNUSED_ARG(o);
+  LWIP_UNUSED_ARG(h);
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+    st = 0;
+    PPPDEBUG(LOG_WARNING, ("sifup[%d]: bad parms\n", pd));
+  } else {
+    IP4_ADDR(&pc->addrs.our_ipaddr, 0,0,0,0);
+    IP4_ADDR(&pc->addrs.his_ipaddr, 0,0,0,0);
+    IP4_ADDR(&pc->addrs.netmask, 255,255,255,0);
+    IP4_ADDR(&pc->addrs.dns1, 0,0,0,0);
+    IP4_ADDR(&pc->addrs.dns2, 0,0,0,0);
+  }
+  return st;
+}
+
+/*
+ * sifdefaultroute - assign a default route through the address given.
+ */
+int
+sifdefaultroute(int pd, u32_t l, u32_t g)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 1;
+
+  LWIP_UNUSED_ARG(l);
+  LWIP_UNUSED_ARG(g);
+
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+    st = 0;
+    PPPDEBUG(LOG_WARNING, ("sifup[%d]: bad parms\n", pd));
+  } else {
+    netif_set_default(&pc->netif);
+  }
+
+  /* TODO: check how PPP handled the netMask, previously not set by ipSetDefault */
+
+  return st;
+}
+
+/*
+ * cifdefaultroute - delete a default route through the address given.
+ */
+int
+cifdefaultroute(int pd, u32_t l, u32_t g)
+{
+  PPPControl *pc = &pppControl[pd];
+  int st = 1;
+
+  LWIP_UNUSED_ARG(l);
+  LWIP_UNUSED_ARG(g);
+
+  if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+    st = 0;
+    PPPDEBUG(LOG_WARNING, ("sifup[%d]: bad parms\n", pd));
+  } else {
+    netif_set_default(NULL);
+  }
+
+  return st;
+}
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+
+#if PPPOS_SUPPORT && PPP_INPROC_OWNTHREAD
+/* The main PPP process function.  This implements the state machine according
+ * to section 4 of RFC 1661: The Point-To-Point Protocol. */
+static void
+pppInputThread(void *arg)
+{
+  int count;
+  PPPControlRx *pcrx = arg;
+
+  while (lcp_phase[pcrx->pd] != PHASE_DEAD) {
+    count = sio_read(pcrx->fd, pcrx->rxbuf, PPPOS_RX_BUFSIZE);
+    if(count > 0) {
+      pppInProc(pcrx, pcrx->rxbuf, count);
+    } else {
+      /* nothing received, give other tasks a chance to run */
+      sys_msleep(1);
+    }
+  }
+}
+#endif /* PPPOS_SUPPORT && PPP_INPROC_OWNTHREAD */
+
+#if PPPOE_SUPPORT
+
+void
+pppOverEthernetInitFailed(int pd)
+{
+  PPPControl* pc;
+
+  pppHup(pd);
+  pppStop(pd);
+
+  pc = &pppControl[pd];
+  pppoe_destroy(&pc->netif);
+  pc->openFlag = 0;
+
+  if(pc->linkStatusCB) {
+    pc->linkStatusCB(pc->linkStatusCtx, pc->errCode ? pc->errCode : PPPERR_PROTOCOL, NULL);
+  }
+}
+
+static void
+pppOverEthernetLinkStatusCB(int pd, int up)
+{
+  if(up) {
+    PPPDEBUG(LOG_INFO, ("pppOverEthernetLinkStatusCB: unit %d: Connecting\n", pd));
+    pppStart(pd);
+  } else {
+    pppOverEthernetInitFailed(pd);
+  }
+}
+#endif /* PPPOE_SUPPORT */
+
+struct pbuf *
+pppSingleBuf(struct pbuf *p)
+{
+  struct pbuf *q, *b;
+  u_char *pl;
+
+  if(p->tot_len == p->len) {
+    return p;
+  }
+
+  q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
+  if(!q) {
+    PPPDEBUG(LOG_ERR,
+             ("pppSingleBuf: unable to alloc new buf (%d)\n", p->tot_len));
+    return p; /* live dangerously */
+  }
+
+  for(b = p, pl = q->payload; b != NULL; b = b->next) {
+    MEMCPY(pl, b->payload, b->len);
+    pl += b->len;
+  }
+
+  pbuf_free(p);
+
+  return q;
+}
+
+struct pppInputHeader {
+  int unit;
+  u16_t proto;
+};
+
+/*
+ * Pass the processed input packet to the appropriate handler.
+ * This function and all handlers run in the context of the tcpip_thread
+ */
+static void
+pppInput(void *arg)
+{
+  struct pbuf *nb = (struct pbuf *)arg;
+  u16_t protocol;
+  int pd;
+
+  pd = ((struct pppInputHeader *)nb->payload)->unit;
+  protocol = ((struct pppInputHeader *)nb->payload)->proto;
+    
+  if(pbuf_header(nb, -(int)sizeof(struct pppInputHeader))) {
+    LWIP_ASSERT("pbuf_header failed\n", 0);
+    goto drop;
+  }
+
+  LINK_STATS_INC(link.recv);
+  snmp_inc_ifinucastpkts(&pppControl[pd].netif);
+  snmp_add_ifinoctets(&pppControl[pd].netif, nb->tot_len);
+
+  /*
+   * Toss all non-LCP packets unless LCP is OPEN.
+   * Until we get past the authentication phase, toss all packets
+   * except LCP, LQR and authentication packets.
+   */
+  if((lcp_phase[pd] <= PHASE_AUTHENTICATE) && (protocol != PPP_LCP)) {
+    if(!((protocol == PPP_LQR) || (protocol == PPP_PAP) || (protocol == PPP_CHAP)) ||
+        (lcp_phase[pd] != PHASE_AUTHENTICATE)) {
+      PPPDEBUG(LOG_INFO, ("pppInput: discarding proto 0x%"X16_F" in phase %d\n", protocol, lcp_phase[pd]));
+      goto drop;
+    }
+  }
+
+  switch(protocol) {
+    case PPP_VJC_COMP:      /* VJ compressed TCP */
+#if PPPOS_SUPPORT && VJ_SUPPORT
+      PPPDEBUG(LOG_INFO, ("pppInput[%d]: vj_comp in pbuf len=%d\n", pd, nb->len));
+      /*
+       * Clip off the VJ header and prepend the rebuilt TCP/IP header and
+       * pass the result to IP.
+       */
+      if ((vj_uncompress_tcp(&nb, &pppControl[pd].vjComp) >= 0) && (pppControl[pd].netif.input)) {
+        pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+        return;
+      }
+      /* Something's wrong so drop it. */
+      PPPDEBUG(LOG_WARNING, ("pppInput[%d]: Dropping VJ compressed\n", pd));
+#else  /* PPPOS_SUPPORT && VJ_SUPPORT */
+      /* No handler for this protocol so drop the packet. */
+      PPPDEBUG(LOG_INFO, ("pppInput[%d]: drop VJ Comp in %d:%s\n", pd, nb->len, nb->payload));
+#endif /* PPPOS_SUPPORT && VJ_SUPPORT */
+      break;
+
+    case PPP_VJC_UNCOMP:    /* VJ uncompressed TCP */
+#if PPPOS_SUPPORT && VJ_SUPPORT
+      PPPDEBUG(LOG_INFO, ("pppInput[%d]: vj_un in pbuf len=%d\n", pd, nb->len));
+      /*
+       * Process the TCP/IP header for VJ header compression and then pass
+       * the packet to IP.
+       */
+      if ((vj_uncompress_uncomp(nb, &pppControl[pd].vjComp) >= 0) && pppControl[pd].netif.input) {
+        pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+        return;
+      }
+      /* Something's wrong so drop it. */
+      PPPDEBUG(LOG_WARNING, ("pppInput[%d]: Dropping VJ uncompressed\n", pd));
+#else  /* PPPOS_SUPPORT && VJ_SUPPORT */
+      /* No handler for this protocol so drop the packet. */
+      PPPDEBUG(LOG_INFO,
+               ("pppInput[%d]: drop VJ UnComp in %d:.*H\n", 
+                pd, nb->len, LWIP_MIN(nb->len * 2, 40), nb->payload));
+#endif /* PPPOS_SUPPORT && VJ_SUPPORT */
+      break;
+
+    case PPP_IP:            /* Internet Protocol */
+      PPPDEBUG(LOG_INFO, ("pppInput[%d]: ip in pbuf len=%d\n", pd, nb->len));
+      if (pppControl[pd].netif.input) {
+        pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+        return;
+      }
+      break;
+
+    default: {
+      struct protent *protp;
+      int i;
+
+      /*
+       * Upcall the proper protocol input routine.
+       */
+      for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+        if (protp->protocol == protocol && protp->enabled_flag) {
+          PPPDEBUG(LOG_INFO, ("pppInput[%d]: %s len=%d\n", pd, protp->name, nb->len));
+          nb = pppSingleBuf(nb);
+          (*protp->input)(pd, nb->payload, nb->len);
+          PPPDEBUG(LOG_DETAIL, ("pppInput[%d]: packet processed\n", pd));
+          goto out;
+        }
+      }
+
+      /* No handler for this protocol so reject the packet. */
+      PPPDEBUG(LOG_INFO, ("pppInput[%d]: rejecting unsupported proto 0x%"X16_F" len=%d\n", pd, protocol, nb->len));
+      if (pbuf_header(nb, sizeof(protocol))) {
+        LWIP_ASSERT("pbuf_header failed\n", 0);
+        goto drop;
+      }
+#if BYTE_ORDER == LITTLE_ENDIAN
+      protocol = htons(protocol);
+#endif /* BYTE_ORDER == LITTLE_ENDIAN */
+      SMEMCPY(nb->payload, &protocol, sizeof(protocol));
+      lcp_sprotrej(pd, nb->payload, nb->len);
+    }
+    break;
+  }
+
+drop:
+  LINK_STATS_INC(link.drop);
+  snmp_inc_ifindiscards(&pppControl[pd].netif);
+
+out:
+  pbuf_free(nb);
+  return;
+}
+
+#if PPPOS_SUPPORT
+/*
+ * Drop the input packet.
+ */
+static void
+pppDrop(PPPControlRx *pcrx)
+{
+  if (pcrx->inHead != NULL) {
+#if 0
+    PPPDEBUG(LOG_INFO, ("pppDrop: %d:%.*H\n", pcrx->inHead->len, min(60, pcrx->inHead->len * 2), pcrx->inHead->payload));
+#endif
+    PPPDEBUG(LOG_INFO, ("pppDrop: pbuf len=%d, addr %p\n", pcrx->inHead->len, (void*)pcrx->inHead));
+    if (pcrx->inTail && (pcrx->inTail != pcrx->inHead)) {
+      pbuf_free(pcrx->inTail);
+    }
+    pbuf_free(pcrx->inHead);
+    pcrx->inHead = NULL;
+    pcrx->inTail = NULL;
+  }
+#if VJ_SUPPORT
+  vj_uncompress_err(&pppControl[pcrx->pd].vjComp);
+#endif /* VJ_SUPPORT */
+
+  LINK_STATS_INC(link.drop);
+  snmp_inc_ifindiscards(&pppControl[pcrx->pd].netif);
+}
+
+/** Pass received raw characters to PPPoS to be decoded. This function is
+ * thread-safe and can be called from a dedicated RX-thread or from a main-loop.
+ *
+ * @param pd PPP descriptor index, returned by pppOpen()
+ * @param data received data
+ * @param len length of received data
+ */
+void
+pppos_input(int pd, u_char* data, int len)
+{
+  pppInProc(&pppControl[pd].rx, data, len);
+}
+
+/**
+ * Process a received octet string.
+ */
+static void
+pppInProc(PPPControlRx *pcrx, u_char *s, int l)
+{
+  struct pbuf *nextNBuf;
+  u_char curChar;
+  u_char escaped;
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  PPPDEBUG(LOG_DEBUG, ("pppInProc[%d]: got %d bytes\n", pcrx->pd, l));
+  while (l-- > 0) {
+    curChar = *s++;
+
+    SYS_ARCH_PROTECT(lev);
+    escaped = ESCAPE_P(pcrx->inACCM, curChar);
+    SYS_ARCH_UNPROTECT(lev);
+    /* Handle special characters. */
+    if (escaped) {
+      /* Check for escape sequences. */
+      /* XXX Note that this does not handle an escaped 0x5d character which
+       * would appear as an escape character.  Since this is an ASCII ']'
+       * and there is no reason that I know of to escape it, I won't complicate
+       * the code to handle this case. GLL */
+      if (curChar == PPP_ESCAPE) {
+        pcrx->inEscaped = 1;
+      /* Check for the flag character. */
+      } else if (curChar == PPP_FLAG) {
+        /* If this is just an extra flag character, ignore it. */
+        if (pcrx->inState <= PDADDRESS) {
+          /* ignore it */;
+        /* If we haven't received the packet header, drop what has come in. */
+        } else if (pcrx->inState < PDDATA) {
+          PPPDEBUG(LOG_WARNING,
+                   ("pppInProc[%d]: Dropping incomplete packet %d\n", 
+                    pcrx->pd, pcrx->inState));
+          LINK_STATS_INC(link.lenerr);
+          pppDrop(pcrx);
+        /* If the fcs is invalid, drop the packet. */
+        } else if (pcrx->inFCS != PPP_GOODFCS) {
+          PPPDEBUG(LOG_INFO,
+                   ("pppInProc[%d]: Dropping bad fcs 0x%"X16_F" proto=0x%"X16_F"\n", 
+                    pcrx->pd, pcrx->inFCS, pcrx->inProtocol));
+          /* Note: If you get lots of these, check for UART frame errors or try different baud rate */
+          LINK_STATS_INC(link.chkerr);
+          pppDrop(pcrx);
+        /* Otherwise it's a good packet so pass it on. */
+        } else {
+          struct pbuf *inp;
+          /* Trim off the checksum. */
+          if(pcrx->inTail->len >= 2) {
+            pcrx->inTail->len -= 2;
+
+            pcrx->inTail->tot_len = pcrx->inTail->len;
+            if (pcrx->inTail != pcrx->inHead) {
+              pbuf_cat(pcrx->inHead, pcrx->inTail);
+            }
+          } else {
+            pcrx->inTail->tot_len = pcrx->inTail->len;
+            if (pcrx->inTail != pcrx->inHead) {
+              pbuf_cat(pcrx->inHead, pcrx->inTail);
+            }
+
+            pbuf_realloc(pcrx->inHead, pcrx->inHead->tot_len - 2);
+          }
+
+          /* Dispatch the packet thereby consuming it. */
+          inp = pcrx->inHead;
+          /* Packet consumed, release our references. */
+          pcrx->inHead = NULL;
+          pcrx->inTail = NULL;
+#if PPP_INPROC_MULTITHREADED
+          if(tcpip_callback_with_block(pppInput, inp, 0) != ERR_OK) {
+            PPPDEBUG(LOG_ERR, ("pppInProc[%d]: tcpip_callback() failed, dropping packet\n", pcrx->pd));
+            pbuf_free(inp);
+            LINK_STATS_INC(link.drop);
+            snmp_inc_ifindiscards(&pppControl[pcrx->pd].netif);
+          }
+#else /* PPP_INPROC_MULTITHREADED */
+          pppInput(inp);
+#endif /* PPP_INPROC_MULTITHREADED */
+        }
+
+        /* Prepare for a new packet. */
+        pcrx->inFCS = PPP_INITFCS;
+        pcrx->inState = PDADDRESS;
+        pcrx->inEscaped = 0;
+      /* Other characters are usually control characters that may have
+       * been inserted by the physical layer so here we just drop them. */
+      } else {
+        PPPDEBUG(LOG_WARNING,
+                 ("pppInProc[%d]: Dropping ACCM char <%d>\n", pcrx->pd, curChar));
+      }
+    /* Process other characters. */
+    } else {
+      /* Unencode escaped characters. */
+      if (pcrx->inEscaped) {
+        pcrx->inEscaped = 0;
+        curChar ^= PPP_TRANS;
+      }
+
+      /* Process character relative to current state. */
+      switch(pcrx->inState) {
+        case PDIDLE:                    /* Idle state - waiting. */
+          /* Drop the character if it's not 0xff
+           * we would have processed a flag character above. */
+          if (curChar != PPP_ALLSTATIONS) {
+            break;
+          }
+
+        /* Fall through */
+        case PDSTART:                   /* Process start flag. */
+          /* Prepare for a new packet. */
+          pcrx->inFCS = PPP_INITFCS;
+
+        /* Fall through */
+        case PDADDRESS:                 /* Process address field. */
+          if (curChar == PPP_ALLSTATIONS) {
+            pcrx->inState = PDCONTROL;
+            break;
+          }
+          /* Else assume compressed address and control fields so
+           * fall through to get the protocol... */
+        case PDCONTROL:                 /* Process control field. */
+          /* If we don't get a valid control code, restart. */
+          if (curChar == PPP_UI) {
+            pcrx->inState = PDPROTOCOL1;
+            break;
+          }
+#if 0
+          else {
+            PPPDEBUG(LOG_WARNING,
+                     ("pppInProc[%d]: Invalid control <%d>\n", pcrx->pd, curChar));
+            pcrx->inState = PDSTART;
+          }
+#endif
+        case PDPROTOCOL1:               /* Process protocol field 1. */
+          /* If the lower bit is set, this is the end of the protocol
+           * field. */
+          if (curChar & 1) {
+            pcrx->inProtocol = curChar;
+            pcrx->inState = PDDATA;
+          } else {
+            pcrx->inProtocol = (u_int)curChar << 8;
+            pcrx->inState = PDPROTOCOL2;
+          }
+          break;
+        case PDPROTOCOL2:               /* Process protocol field 2. */
+          pcrx->inProtocol |= curChar;
+          pcrx->inState = PDDATA;
+          break;
+        case PDDATA:                    /* Process data byte. */
+          /* Make space to receive processed data. */
+          if (pcrx->inTail == NULL || pcrx->inTail->len == PBUF_POOL_BUFSIZE) {
+            if (pcrx->inTail != NULL) {
+              pcrx->inTail->tot_len = pcrx->inTail->len;
+              if (pcrx->inTail != pcrx->inHead) {
+                pbuf_cat(pcrx->inHead, pcrx->inTail);
+                /* give up the inTail reference now */
+                pcrx->inTail = NULL;
+              }
+            }
+            /* If we haven't started a packet, we need a packet header. */
+            nextNBuf = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+            if (nextNBuf == NULL) {
+              /* No free buffers.  Drop the input packet and let the
+               * higher layers deal with it.  Continue processing
+               * the received pbuf chain in case a new packet starts. */
+              PPPDEBUG(LOG_ERR, ("pppInProc[%d]: NO FREE MBUFS!\n", pcrx->pd));
+              LINK_STATS_INC(link.memerr);
+              pppDrop(pcrx);
+              pcrx->inState = PDSTART;  /* Wait for flag sequence. */
+              break;
+            }
+            if (pcrx->inHead == NULL) {
+              struct pppInputHeader *pih = nextNBuf->payload;
+
+              pih->unit = pcrx->pd;
+              pih->proto = pcrx->inProtocol;
+
+              nextNBuf->len += sizeof(*pih);
+
+              pcrx->inHead = nextNBuf;
+            }
+            pcrx->inTail = nextNBuf;
+          }
+          /* Load character into buffer. */
+          ((u_char*)pcrx->inTail->payload)[pcrx->inTail->len++] = curChar;
+          break;
+      }
+
+      /* update the frame check sequence number. */
+      pcrx->inFCS = PPP_FCS(pcrx->inFCS, curChar);
+    }
+  } /* while (l-- > 0), all bytes processed */
+
+  avRandomize();
+}
+#endif /* PPPOS_SUPPORT */
+
+#if PPPOE_SUPPORT
+void
+pppInProcOverEthernet(int pd, struct pbuf *pb)
+{
+  struct pppInputHeader *pih;
+  u16_t inProtocol;
+
+  if(pb->len < sizeof(inProtocol)) {
+    PPPDEBUG(LOG_ERR, ("pppInProcOverEthernet: too small for protocol field\n"));
+    goto drop;
+  }
+
+  inProtocol = (((u8_t *)pb->payload)[0] << 8) | ((u8_t*)pb->payload)[1];
+
+  /* make room for pppInputHeader - should not fail */
+  if (pbuf_header(pb, sizeof(*pih) - sizeof(inProtocol)) != 0) {
+    PPPDEBUG(LOG_ERR, ("pppInProcOverEthernet: could not allocate room for header\n"));
+    goto drop;
+  }
+
+  pih = pb->payload;
+
+  pih->unit = pd;
+  pih->proto = inProtocol;
+
+  /* Dispatch the packet thereby consuming it. */
+  pppInput(pb);
+  return;
+
+drop:
+  LINK_STATS_INC(link.drop);
+  snmp_inc_ifindiscards(&pppControl[pd].netif);
+  pbuf_free(pb);
+  return;
+}
+#endif /* PPPOE_SUPPORT */
+
+#if LWIP_NETIF_STATUS_CALLBACK
+/** Set the status callback of a PPP's netif
+ *
+ * @param pd The PPP descriptor returned by pppOpen()
+ * @param status_callback pointer to the status callback function
+ *
+ * @see netif_set_status_callback
+ */
+void
+ppp_set_netif_statuscallback(int pd, netif_status_callback_fn status_callback)
+{
+  netif_set_status_callback(&pppControl[pd].netif, status_callback); 
+}
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+
+#if LWIP_NETIF_LINK_CALLBACK
+/** Set the link callback of a PPP's netif
+ *
+ * @param pd The PPP descriptor returned by pppOpen()
+ * @param link_callback pointer to the link callback function
+ *
+ * @see netif_set_link_callback
+ */
+void
+ppp_set_netif_linkcallback(int pd, netif_status_callback_fn link_callback)
+{
+  netif_set_link_callback(&pppControl[pd].netif, link_callback); 
+}
+#endif /* LWIP_NETIF_LINK_CALLBACK */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/ppp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/ppp.h
new file mode 100644
index 0000000..a72ac95
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/ppp.h
@@ -0,0 +1,483 @@
+/*****************************************************************************
+* ppp.h - Network Point to Point Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD codes.
+*****************************************************************************/
+
+#ifndef PPP_H
+#define PPP_H
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/def.h"
+#include "lwip/sio.h"
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+#include "lwip/netif.h"
+#include "lwip/sys.h"
+#include "lwip/timers.h"
+
+/** Some defines for code we skip compared to the original pppd.
+ *  These are just here to minimise the use of the ugly "#if 0". */
+#define PPP_ADDITIONAL_CALLBACKS  0
+
+/** Some error checks to test for unsupported code */
+#if CBCP_SUPPORT
+#error "CBCP is not supported in lwIP PPP"
+#endif
+#if CCP_SUPPORT
+#error "CCP is not supported in lwIP PPP"
+#endif
+
+/*
+ * pppd.h - PPP daemon global declarations.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ */
+/*
+ * ppp_defs.h - PPP definitions.
+ *
+ * Copyright (c) 1994 The Australian National University.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, provided that the above copyright
+ * notice appears in all copies.  This software is provided without any
+ * warranty, express or implied. The Australian National University
+ * makes no representations about the suitability of this software for
+ * any purpose.
+ *
+ * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY
+ * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
+ * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
+ * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS,
+ * OR MODIFICATIONS.
+ */
+
+#define TIMEOUT(f, a, t)    do { sys_untimeout((f), (a)); sys_timeout((t)*1000, (f), (a)); } while(0)
+#define UNTIMEOUT(f, a)     sys_untimeout((f), (a))
+
+
+#ifndef __u_char_defined
+
+/* Type definitions for BSD code. */
+typedef unsigned long  u_long;
+typedef unsigned int   u_int;
+typedef unsigned short u_short;
+typedef unsigned char  u_char;
+
+#endif
+
+/*
+ * Constants and structures defined by the internet system,
+ * Per RFC 790, September 1981, and numerous additions.
+ */
+
+/*
+ * The basic PPP frame.
+ */
+#define PPP_HDRLEN      4       /* octets for standard ppp header */
+#define PPP_FCSLEN      2       /* octets for FCS */
+
+
+/*
+ * Significant octet values.
+ */
+#define PPP_ALLSTATIONS 0xff    /* All-Stations broadcast address */
+#define PPP_UI          0x03    /* Unnumbered Information */
+#define PPP_FLAG        0x7e    /* Flag Sequence */
+#define PPP_ESCAPE      0x7d    /* Asynchronous Control Escape */
+#define PPP_TRANS       0x20    /* Asynchronous transparency modifier */
+
+/*
+ * Protocol field values.
+ */
+#define PPP_IP          0x21    /* Internet Protocol */
+#define PPP_AT          0x29    /* AppleTalk Protocol */
+#define PPP_VJC_COMP    0x2d    /* VJ compressed TCP */
+#define PPP_VJC_UNCOMP  0x2f    /* VJ uncompressed TCP */
+#define PPP_COMP        0xfd    /* compressed packet */
+#define PPP_IPCP        0x8021  /* IP Control Protocol */
+#define PPP_ATCP        0x8029  /* AppleTalk Control Protocol */
+#define PPP_CCP         0x80fd  /* Compression Control Protocol */
+#define PPP_LCP         0xc021  /* Link Control Protocol */
+#define PPP_PAP         0xc023  /* Password Authentication Protocol */
+#define PPP_LQR         0xc025  /* Link Quality Report protocol */
+#define PPP_CHAP        0xc223  /* Cryptographic Handshake Auth. Protocol */
+#define PPP_CBCP        0xc029  /* Callback Control Protocol */
+
+/*
+ * Values for FCS calculations.
+ */
+#define PPP_INITFCS     0xffff  /* Initial FCS value */
+#define PPP_GOODFCS     0xf0b8  /* Good final FCS value */
+#define PPP_FCS(fcs, c) (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff])
+
+/*
+ * Extended asyncmap - allows any character to be escaped.
+ */
+typedef u_char  ext_accm[32];
+
+/*
+ * What to do with network protocol (NP) packets.
+ */
+enum NPmode {
+  NPMODE_PASS,        /* pass the packet through */
+  NPMODE_DROP,        /* silently drop the packet */
+  NPMODE_ERROR,       /* return an error */
+  NPMODE_QUEUE        /* save it up for later. */
+};
+
+/*
+ * Inline versions of get/put char/short/long.
+ * Pointer is advanced; we assume that both arguments
+ * are lvalues and will already be in registers.
+ * cp MUST be u_char *.
+ */
+#define GETCHAR(c, cp) { \
+    (c) = *(cp)++; \
+}
+#define PUTCHAR(c, cp) { \
+    *(cp)++ = (u_char) (c); \
+}
+
+
+#define GETSHORT(s, cp) { \
+    (s) = *(cp); (cp)++; (s) <<= 8; \
+    (s) |= *(cp); (cp)++; \
+}
+#define PUTSHORT(s, cp) { \
+    *(cp)++ = (u_char) ((s) >> 8); \
+    *(cp)++ = (u_char) (s & 0xff); \
+}
+
+#define GETLONG(l, cp) { \
+    (l) = *(cp); (cp)++; (l) <<= 8; \
+    (l) |= *(cp); (cp)++; (l) <<= 8; \
+    (l) |= *(cp); (cp)++; (l) <<= 8; \
+    (l) |= *(cp); (cp)++; \
+}
+#define PUTLONG(l, cp) { \
+    *(cp)++ = (u_char) ((l) >> 24); \
+    *(cp)++ = (u_char) ((l) >> 16); \
+    *(cp)++ = (u_char) ((l) >> 8); \
+    *(cp)++ = (u_char) (l); \
+}
+
+
+#define INCPTR(n, cp)   ((cp) += (n))
+#define DECPTR(n, cp)   ((cp) -= (n))
+
+#define BCMP(s0, s1, l)     memcmp((u_char *)(s0), (u_char *)(s1), (l))
+#define BCOPY(s, d, l)      MEMCPY((d), (s), (l))
+#define BZERO(s, n)         memset(s, 0, n)
+
+#if PPP_DEBUG
+#define PRINTMSG(m, l)  { m[l] = '\0'; LWIP_DEBUGF(LOG_INFO, ("Remote message: %s\n", m)); }
+#else  /* PPP_DEBUG */
+#define PRINTMSG(m, l)
+#endif /* PPP_DEBUG */
+
+/*
+ * MAKEHEADER - Add PPP Header fields to a packet.
+ */
+#define MAKEHEADER(p, t) { \
+    PUTCHAR(PPP_ALLSTATIONS, p); \
+    PUTCHAR(PPP_UI, p); \
+    PUTSHORT(t, p); }
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+
+/* Error codes. */
+#define PPPERR_NONE      0 /* No error. */
+#define PPPERR_PARAM    -1 /* Invalid parameter. */
+#define PPPERR_OPEN     -2 /* Unable to open PPP session. */
+#define PPPERR_DEVICE   -3 /* Invalid I/O device for PPP. */
+#define PPPERR_ALLOC    -4 /* Unable to allocate resources. */
+#define PPPERR_USER     -5 /* User interrupt. */
+#define PPPERR_CONNECT  -6 /* Connection lost. */
+#define PPPERR_AUTHFAIL -7 /* Failed authentication challenge. */
+#define PPPERR_PROTOCOL -8 /* Failed to meet protocol. */
+
+/*
+ * PPP IOCTL commands.
+ */
+/*
+ * Get the up status - 0 for down, non-zero for up.  The argument must
+ * point to an int.
+ */
+#define PPPCTLG_UPSTATUS 100 /* Get the up status - 0 down else up */
+#define PPPCTLS_ERRCODE  101 /* Set the error code */
+#define PPPCTLG_ERRCODE  102 /* Get the error code */
+#define PPPCTLG_FD       103 /* Get the fd associated with the ppp */
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * The following struct gives the addresses of procedures to call
+ * for a particular protocol.
+ */
+struct protent {
+    u_short protocol;       /* PPP protocol number */
+    /* Initialization procedure */
+    void (*init) (int unit);
+    /* Process a received packet */
+    void (*input) (int unit, u_char *pkt, int len);
+    /* Process a received protocol-reject */
+    void (*protrej) (int unit);
+    /* Lower layer has come up */
+    void (*lowerup) (int unit);
+    /* Lower layer has gone down */
+    void (*lowerdown) (int unit);
+    /* Open the protocol */
+    void (*open) (int unit);
+    /* Close the protocol */
+    void (*close) (int unit, char *reason);
+#if PPP_ADDITIONAL_CALLBACKS
+    /* Print a packet in readable form */
+    int  (*printpkt) (u_char *pkt, int len,
+              void (*printer) (void *, char *, ...),
+              void *arg);
+    /* Process a received data packet */
+    void (*datainput) (int unit, u_char *pkt, int len);
+#endif /* PPP_ADDITIONAL_CALLBACKS */
+    int  enabled_flag;      /* 0 if protocol is disabled */
+    char *name;         /* Text name of protocol */
+#if PPP_ADDITIONAL_CALLBACKS
+    /* Check requested options, assign defaults */
+    void (*check_options) (u_long);
+    /* Configure interface for demand-dial */
+    int  (*demand_conf) (int unit);
+    /* Say whether to bring up link for this pkt */
+    int  (*active_pkt) (u_char *pkt, int len);
+#endif /* PPP_ADDITIONAL_CALLBACKS */
+};
+
+/*
+ * The following structure records the time in seconds since
+ * the last NP packet was sent or received.
+ */
+struct ppp_idle {
+  u_short xmit_idle;      /* seconds since last NP packet sent */
+  u_short recv_idle;      /* seconds since last NP packet received */
+};
+
+struct ppp_settings {
+
+  u_int  disable_defaultip : 1;       /* Don't use hostname for default IP addrs */
+  u_int  auth_required     : 1;       /* Peer is required to authenticate */
+  u_int  explicit_remote   : 1;       /* remote_name specified with remotename opt */
+  u_int  refuse_pap        : 1;       /* Don't wanna auth. ourselves with PAP */
+  u_int  refuse_chap       : 1;       /* Don't wanna auth. ourselves with CHAP */
+  u_int  usehostname       : 1;       /* Use hostname for our_name */
+  u_int  usepeerdns        : 1;       /* Ask peer for DNS adds */
+
+  u_short idle_time_limit;            /* Shut down link if idle for this long */
+  int  maxconnect;                    /* Maximum connect time (seconds) */
+
+  char user       [MAXNAMELEN   + 1]; /* Username for PAP */
+  char passwd     [MAXSECRETLEN + 1]; /* Password for PAP, secret for CHAP */
+  char our_name   [MAXNAMELEN   + 1]; /* Our name for authentication purposes */
+  char remote_name[MAXNAMELEN   + 1]; /* Peer's name for authentication */
+};
+
+struct ppp_addrs {
+  ip_addr_t our_ipaddr, his_ipaddr, netmask, dns1, dns2;
+};
+
+/*****************************
+*** PUBLIC DATA STRUCTURES ***
+*****************************/
+
+/* Buffers for outgoing packets. */
+extern u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN];
+
+extern struct ppp_settings ppp_settings;
+
+extern struct protent *ppp_protocols[]; /* Table of pointers to supported protocols */
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+/* Initialize the PPP subsystem. */
+void pppInit(void);
+
+/* Warning: Using PPPAUTHTYPE_ANY might have security consequences.
+ * RFC 1994 says:
+ *
+ * In practice, within or associated with each PPP server, there is a
+ * database which associates "user" names with authentication
+ * information ("secrets").  It is not anticipated that a particular
+ * named user would be authenticated by multiple methods.  This would
+ * make the user vulnerable to attacks which negotiate the least secure
+ * method from among a set (such as PAP rather than CHAP).  If the same
+ * secret was used, PAP would reveal the secret to be used later with
+ * CHAP.
+ *
+ * Instead, for each user name there should be an indication of exactly
+ * one method used to authenticate that user name.  If a user needs to
+ * make use of different authentication methods under different
+ * circumstances, then distinct user names SHOULD be employed, each of
+ * which identifies exactly one authentication method.
+ *
+ */
+enum pppAuthType {
+    PPPAUTHTYPE_NONE,
+    PPPAUTHTYPE_ANY,
+    PPPAUTHTYPE_PAP,
+    PPPAUTHTYPE_CHAP
+};
+
+void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd);
+
+/*
+ * Open a new PPP connection using the given serial I/O device.
+ * This initializes the PPP control block but does not
+ * attempt to negotiate the LCP session.
+ * Return a new PPP connection descriptor on success or
+ * an error code (negative) on failure. 
+ */
+int pppOverSerialOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx);
+
+/*
+ * Open a new PPP Over Ethernet (PPPOE) connection.
+ */
+int pppOverEthernetOpen(struct netif *ethif, const char *service_name, const char *concentrator_name, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx);
+
+/* for source code compatibility */
+#define pppOpen(fd,cb,ls) pppOverSerialOpen(fd,cb,ls)
+
+/*
+ * Close a PPP connection and release the descriptor. 
+ * Any outstanding packets in the queues are dropped.
+ * Return 0 on success, an error code on failure. 
+ */
+int pppClose(int pd);
+
+/*
+ * Indicate to the PPP process that the line has disconnected.
+ */
+void pppSigHUP(int pd);
+
+/*
+ * Get and set parameters for the given connection.
+ * Return 0 on success, an error code on failure. 
+ */
+int  pppIOCtl(int pd, int cmd, void *arg);
+
+/*
+ * Return the Maximum Transmission Unit for the given PPP connection.
+ */
+u_short pppMTU(int pd);
+
+/*
+ * Write n characters to a ppp link.
+ * RETURN: >= 0 Number of characters written, -1 Failed to write to device.
+ */
+int pppWrite(int pd, const u_char *s, int n);
+
+void pppInProcOverEthernet(int pd, struct pbuf *pb);
+
+struct pbuf *pppSingleBuf(struct pbuf *p);
+
+void pppLinkTerminated(int pd);
+
+void pppLinkDown(int pd);
+
+void pppos_input(int pd, u_char* data, int len);
+
+/* Configure i/f transmit parameters */
+void ppp_send_config (int, u16_t, u32_t, int, int);
+/* Set extended transmit ACCM */
+void ppp_set_xaccm (int, ext_accm *);
+/* Configure i/f receive parameters */
+void ppp_recv_config (int, int, u32_t, int, int);
+/* Find out how long link has been idle */
+int  get_idle_time (int, struct ppp_idle *);
+
+/* Configure VJ TCP header compression */
+int  sifvjcomp (int, int, u8_t, u8_t);
+/* Configure i/f down (for IP) */
+int  sifup (int);
+/* Set mode for handling packets for proto */
+int  sifnpmode (int u, int proto, enum NPmode mode);
+/* Configure i/f down (for IP) */
+int  sifdown (int);
+/* Configure IP addresses for i/f */
+int  sifaddr (int, u32_t, u32_t, u32_t, u32_t, u32_t);
+/* Reset i/f IP addresses */
+int  cifaddr (int, u32_t, u32_t);
+/* Create default route through i/f */
+int  sifdefaultroute (int, u32_t, u32_t);
+/* Delete default route through i/f */
+int  cifdefaultroute (int, u32_t, u32_t);
+
+/* Get appropriate netmask for address */
+u32_t GetMask (u32_t); 
+
+#if LWIP_NETIF_STATUS_CALLBACK
+void ppp_set_netif_statuscallback(int pd, netif_status_callback_fn status_callback);
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+#if LWIP_NETIF_LINK_CALLBACK
+void ppp_set_netif_linkcallback(int pd, netif_status_callback_fn link_callback);
+#endif /* LWIP_NETIF_LINK_CALLBACK */
+
+#endif /* PPP_SUPPORT */
+
+#endif /* PPP_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/ppp_oe.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/ppp_oe.c
new file mode 100644
index 0000000..040a0bc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/ppp_oe.c
@@ -0,0 +1,1132 @@
+/*****************************************************************************
+* ppp_oe.c - PPP Over Ethernet implementation for lwIP.
+*
+* Copyright (c) 2006 by Marc Boucher, Services Informatiques (MBSI) inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 06-01-01 Marc Boucher 
+*   Ported to lwIP.
+*****************************************************************************/
+
+
+
+/* based on NetBSD: if_pppoe.c,v 1.64 2006/01/31 23:50:15 martin Exp */
+
+/*-
+ * Copyright (c) 2002 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Martin Husemann .
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "lwip/opt.h"
+
+#if PPPOE_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "netif/ppp_oe.h"
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "lwip/timers.h"
+#include "lwip/memp.h"
+
+#include 
+#include 
+
+
+/* Add a 16 bit unsigned value to a buffer pointed to by PTR */
+#define PPPOE_ADD_16(PTR, VAL) \
+    *(PTR)++ = (u8_t)((VAL) / 256);    \
+    *(PTR)++ = (u8_t)((VAL) % 256)
+
+/* Add a complete PPPoE header to the buffer pointed to by PTR */
+#define PPPOE_ADD_HEADER(PTR, CODE, SESS, LEN)  \
+    *(PTR)++ = PPPOE_VERTYPE;  \
+    *(PTR)++ = (CODE);         \
+    PPPOE_ADD_16(PTR, SESS);   \
+    PPPOE_ADD_16(PTR, LEN)
+
+#define PPPOE_DISC_TIMEOUT (5*1000)  /* base for quick timeout calculation */
+#define PPPOE_SLOW_RETRY   (60*1000) /* persistent retry interval */
+#define PPPOE_DISC_MAXPADI  4        /* retry PADI four times (quickly) */
+#define PPPOE_DISC_MAXPADR  2        /* retry PADR twice */
+
+#ifdef PPPOE_SERVER
+#error "PPPOE_SERVER is not yet supported under lwIP!"
+/* from if_spppsubr.c */
+#define IFF_PASSIVE IFF_LINK0 /* wait passively for connection */
+#endif
+
+#ifndef PPPOE_ERRORSTRING_LEN
+#define PPPOE_ERRORSTRING_LEN     64
+#endif
+static char pppoe_error_tmp[PPPOE_ERRORSTRING_LEN];
+
+
+/* input routines */
+static void pppoe_dispatch_disc_pkt(struct netif *, struct pbuf *);
+
+/* management routines */
+static int pppoe_do_disconnect(struct pppoe_softc *);
+static void pppoe_abort_connect(struct pppoe_softc *);
+static void pppoe_clear_softc(struct pppoe_softc *, const char *);
+
+/* internal timeout handling */
+static void pppoe_timeout(void *);
+
+/* sending actual protocol controll packets */
+static err_t pppoe_send_padi(struct pppoe_softc *);
+static err_t pppoe_send_padr(struct pppoe_softc *);
+#ifdef PPPOE_SERVER
+static err_t pppoe_send_pado(struct pppoe_softc *);
+static err_t pppoe_send_pads(struct pppoe_softc *);
+#endif
+static err_t pppoe_send_padt(struct netif *, u_int, const u8_t *);
+
+/* internal helper functions */
+static struct pppoe_softc * pppoe_find_softc_by_session(u_int, struct netif *);
+static struct pppoe_softc * pppoe_find_softc_by_hunique(u8_t *, size_t, struct netif *);
+
+/** linked list of created pppoe interfaces */
+static struct pppoe_softc *pppoe_softc_list;
+
+err_t
+pppoe_create(struct netif *ethif, int pd, void (*linkStatusCB)(int pd, int up), struct pppoe_softc **scptr)
+{
+  struct pppoe_softc *sc;
+
+  sc = (struct pppoe_softc *)memp_malloc(MEMP_PPPOE_IF);
+  if (sc == NULL) {
+    *scptr = NULL;
+    return ERR_MEM;
+  }
+  memset(sc, 0, sizeof(struct pppoe_softc));
+
+  /* changed to real address later */
+  MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest));
+
+  sc->sc_pd = pd;
+  sc->sc_linkStatusCB = linkStatusCB;
+  sc->sc_ethif = ethif;
+
+  /* put the new interface at the head of the list */
+  sc->next = pppoe_softc_list;
+  pppoe_softc_list = sc;
+
+  *scptr = sc;
+
+  return ERR_OK;
+}
+
+err_t
+pppoe_destroy(struct netif *ifp)
+{
+  struct pppoe_softc *sc, *prev = NULL;
+
+  for (sc = pppoe_softc_list; sc != NULL; prev = sc, sc = sc->next) {
+    if (sc->sc_ethif == ifp) {
+      break;
+    }
+  }
+
+  if(!(sc && (sc->sc_ethif == ifp))) {
+    return ERR_IF;
+  }
+
+  sys_untimeout(pppoe_timeout, sc);
+  if (prev == NULL) {
+    /* remove sc from the head of the list */
+    pppoe_softc_list = sc->next;
+  } else {
+    /* remove sc from the list */
+    prev->next = sc->next;
+  }
+
+#ifdef PPPOE_TODO
+  if (sc->sc_concentrator_name) {
+    mem_free(sc->sc_concentrator_name);
+  }
+  if (sc->sc_service_name) {
+    mem_free(sc->sc_service_name);
+  }
+#endif /* PPPOE_TODO */
+  memp_free(MEMP_PPPOE_IF, sc);
+
+  return ERR_OK;
+}
+
+/*
+ * Find the interface handling the specified session.
+ * Note: O(number of sessions open), this is a client-side only, mean
+ * and lean implementation, so number of open sessions typically should
+ * be 1.
+ */
+static struct pppoe_softc *
+pppoe_find_softc_by_session(u_int session, struct netif *rcvif)
+{
+  struct pppoe_softc *sc;
+
+  if (session == 0) {
+    return NULL;
+  }
+
+  for (sc = pppoe_softc_list; sc != NULL; sc = sc->next) {
+    if (sc->sc_state == PPPOE_STATE_SESSION
+        && sc->sc_session == session) {
+      if (sc->sc_ethif == rcvif) {
+        return sc;
+      } else {
+        return NULL;
+      }
+    }
+  }
+  return NULL;
+}
+
+/* Check host unique token passed and return appropriate softc pointer,
+ * or NULL if token is bogus. */
+static struct pppoe_softc *
+pppoe_find_softc_by_hunique(u8_t *token, size_t len, struct netif *rcvif)
+{
+  struct pppoe_softc *sc, *t;
+
+  if (pppoe_softc_list == NULL) {
+    return NULL;
+  }
+
+  if (len != sizeof sc) {
+    return NULL;
+  }
+  MEMCPY(&t, token, len);
+
+  for (sc = pppoe_softc_list; sc != NULL; sc = sc->next) {
+    if (sc == t) {
+      break;
+    }
+  }
+
+  if (sc == NULL) {
+    PPPDEBUG(LOG_DEBUG, ("pppoe: alien host unique tag, no session found\n"));
+    return NULL;
+  }
+
+  /* should be safe to access *sc now */
+  if (sc->sc_state < PPPOE_STATE_PADI_SENT || sc->sc_state >= PPPOE_STATE_SESSION) {
+    printf("%c%c%"U16_F": host unique tag found, but it belongs to a connection in state %d\n",
+      sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, sc->sc_state);
+    return NULL;
+  }
+  if (sc->sc_ethif != rcvif) {
+    printf("%c%c%"U16_F": wrong interface, not accepting host unique\n",
+      sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num);
+    return NULL;
+  }
+  return sc;
+}
+
+static void
+pppoe_linkstatus_up(struct pppoe_softc *sc)
+{
+  sc->sc_linkStatusCB(sc->sc_pd, 1);
+}
+
+/* analyze and handle a single received packet while not in session state */
+static void
+pppoe_dispatch_disc_pkt(struct netif *netif, struct pbuf *pb)
+{
+  u16_t tag, len;
+  u16_t session, plen;
+  struct pppoe_softc *sc;
+  const char *err_msg;
+  char devname[6];
+  u8_t *ac_cookie;
+  u16_t ac_cookie_len;
+#ifdef PPPOE_SERVER
+  u8_t *hunique;
+  size_t hunique_len;
+#endif
+  struct pppoehdr *ph;
+  struct pppoetag pt;
+  int off, err, errortag;
+  struct eth_hdr *ethhdr;
+
+  pb = pppSingleBuf(pb);
+
+  strcpy(devname, "pppoe");  /* as long as we don't know which instance */
+  err_msg = NULL;
+  errortag = 0;
+  if (pb->len < sizeof(*ethhdr)) {
+    goto done;
+  }
+  ethhdr = (struct eth_hdr *)pb->payload;
+  off = sizeof(*ethhdr);
+
+  ac_cookie = NULL;
+  ac_cookie_len = 0;
+#ifdef PPPOE_SERVER
+  hunique = NULL;
+  hunique_len = 0;
+#endif
+  session = 0;
+  if (pb->len - off < PPPOE_HEADERLEN) {
+    printf("pppoe: packet too short: %d\n", pb->len);
+    goto done;
+  }
+
+  ph = (struct pppoehdr *) (ethhdr + 1);
+  if (ph->vertype != PPPOE_VERTYPE) {
+    printf("pppoe: unknown version/type packet: 0x%x\n", ph->vertype);
+    goto done;
+  }
+  session = ntohs(ph->session);
+  plen = ntohs(ph->plen);
+  off += sizeof(*ph);
+
+  if (plen + off > pb->len) {
+    printf("pppoe: packet content does not fit: data available = %d, packet size = %u\n",
+        pb->len - off, plen);
+    goto done;
+  }
+  if(pb->tot_len == pb->len) {
+    pb->tot_len = pb->len = (u16_t)off + plen; /* ignore trailing garbage */
+  }
+  tag = 0;
+  len = 0;
+  sc = NULL;
+  while (off + sizeof(pt) <= pb->len) {
+    MEMCPY(&pt, (u8_t*)pb->payload + off, sizeof(pt));
+    tag = ntohs(pt.tag);
+    len = ntohs(pt.len);
+    if (off + sizeof(pt) + len > pb->len) {
+      printf("pppoe: tag 0x%x len 0x%x is too long\n", tag, len);
+      goto done;
+    }
+    switch (tag) {
+      case PPPOE_TAG_EOL:
+        goto breakbreak;
+      case PPPOE_TAG_SNAME:
+        break;  /* ignored */
+      case PPPOE_TAG_ACNAME:
+        break;  /* ignored */
+      case PPPOE_TAG_HUNIQUE:
+        if (sc != NULL) {
+          break;
+        }
+#ifdef PPPOE_SERVER
+        hunique = (u8_t*)pb->payload + off + sizeof(pt);
+        hunique_len = len;
+#endif
+        sc = pppoe_find_softc_by_hunique((u8_t*)pb->payload + off + sizeof(pt), len, netif);
+        if (sc != NULL) {
+          snprintf(devname, sizeof(devname), "%c%c%"U16_F, sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num);
+        }
+        break;
+      case PPPOE_TAG_ACCOOKIE:
+        if (ac_cookie == NULL) {
+          ac_cookie = (u8_t*)pb->payload + off + sizeof(pt);
+          ac_cookie_len = len;
+        }
+        break;
+      case PPPOE_TAG_SNAME_ERR:
+        err_msg = "SERVICE NAME ERROR";
+        errortag = 1;
+        break;
+      case PPPOE_TAG_ACSYS_ERR:
+        err_msg = "AC SYSTEM ERROR";
+        errortag = 1;
+        break;
+      case PPPOE_TAG_GENERIC_ERR:
+        err_msg = "GENERIC ERROR";
+        errortag = 1;
+        break;
+    }
+    if (err_msg) {
+      if (errortag && len) {
+        u16_t error_len = LWIP_MIN(len, sizeof(pppoe_error_tmp)-1);
+        strncpy(pppoe_error_tmp, (char*)pb->payload + off + sizeof(pt), error_len);
+        pppoe_error_tmp[error_len-1] = '\0';
+        printf("%s: %s: %s\n", devname, err_msg, pppoe_error_tmp);
+      } else {
+        printf("%s: %s\n", devname, err_msg);
+      }
+      if (errortag) {
+        goto done;
+      }
+    }
+    off += sizeof(pt) + len;
+  }
+
+breakbreak:;
+  switch (ph->code) {
+    case PPPOE_CODE_PADI:
+#ifdef PPPOE_SERVER
+      /*
+       * got service name, concentrator name, and/or host unique.
+       * ignore if we have no interfaces with IFF_PASSIVE|IFF_UP.
+       */
+      if (LIST_EMPTY(&pppoe_softc_list)) {
+        goto done;
+      }
+      LIST_FOREACH(sc, &pppoe_softc_list, sc_list) {
+        if (!(sc->sc_sppp.pp_if.if_flags & IFF_UP)) {
+          continue;
+        }
+        if (!(sc->sc_sppp.pp_if.if_flags & IFF_PASSIVE)) {
+          continue;
+        }
+        if (sc->sc_state == PPPOE_STATE_INITIAL) {
+          break;
+        }
+      }
+      if (sc == NULL) {
+        /* printf("pppoe: free passive interface is not found\n"); */
+        goto done;
+      }
+      if (hunique) {
+        if (sc->sc_hunique) {
+          mem_free(sc->sc_hunique);
+        }
+        sc->sc_hunique = mem_malloc(hunique_len);
+        if (sc->sc_hunique == NULL) {
+          goto done;
+        }
+        sc->sc_hunique_len = hunique_len;
+        MEMCPY(sc->sc_hunique, hunique, hunique_len);
+      }
+      MEMCPY(&sc->sc_dest, eh->ether_shost, sizeof sc->sc_dest);
+      sc->sc_state = PPPOE_STATE_PADO_SENT;
+      pppoe_send_pado(sc);
+      break;
+#endif /* PPPOE_SERVER */
+    case PPPOE_CODE_PADR:
+#ifdef PPPOE_SERVER
+      /*
+       * get sc from ac_cookie if IFF_PASSIVE
+       */
+      if (ac_cookie == NULL) {
+        /* be quiet if there is not a single pppoe instance */
+        printf("pppoe: received PADR but not includes ac_cookie\n");
+        goto done;
+      }
+      sc = pppoe_find_softc_by_hunique(ac_cookie, ac_cookie_len, netif);
+      if (sc == NULL) {
+        /* be quiet if there is not a single pppoe instance */
+        if (!LIST_EMPTY(&pppoe_softc_list)) {
+          printf("pppoe: received PADR but could not find request for it\n");
+        }
+        goto done;
+      }
+      if (sc->sc_state != PPPOE_STATE_PADO_SENT) {
+        printf("%c%c%"U16_F": received unexpected PADR\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num);
+        goto done;
+      }
+      if (hunique) {
+        if (sc->sc_hunique) {
+          mem_free(sc->sc_hunique);
+        }
+        sc->sc_hunique = mem_malloc(hunique_len);
+        if (sc->sc_hunique == NULL) {
+          goto done;
+        }
+        sc->sc_hunique_len = hunique_len;
+        MEMCPY(sc->sc_hunique, hunique, hunique_len);
+      }
+      pppoe_send_pads(sc);
+      sc->sc_state = PPPOE_STATE_SESSION;
+      pppoe_linkstatus_up(sc); /* notify upper layers */
+      break;
+#else
+      /* ignore, we are no access concentrator */
+      goto done;
+#endif /* PPPOE_SERVER */
+    case PPPOE_CODE_PADO:
+      if (sc == NULL) {
+        /* be quiet if there is not a single pppoe instance */
+        if (pppoe_softc_list != NULL) {
+          printf("pppoe: received PADO but could not find request for it\n");
+        }
+        goto done;
+      }
+      if (sc->sc_state != PPPOE_STATE_PADI_SENT) {
+        printf("%c%c%"U16_F": received unexpected PADO\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num);
+        goto done;
+      }
+      if (ac_cookie) {
+        sc->sc_ac_cookie_len = ac_cookie_len;
+        MEMCPY(sc->sc_ac_cookie, ac_cookie, ac_cookie_len);
+      }
+      MEMCPY(&sc->sc_dest, ethhdr->src.addr, sizeof(sc->sc_dest.addr));
+      sys_untimeout(pppoe_timeout, sc);
+      sc->sc_padr_retried = 0;
+      sc->sc_state = PPPOE_STATE_PADR_SENT;
+      if ((err = pppoe_send_padr(sc)) != 0) {
+        PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": failed to send PADR, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err));
+      }
+      sys_timeout(PPPOE_DISC_TIMEOUT * (1 + sc->sc_padr_retried), pppoe_timeout, sc);
+      break;
+    case PPPOE_CODE_PADS:
+      if (sc == NULL) {
+        goto done;
+      }
+      sc->sc_session = session;
+      sys_untimeout(pppoe_timeout, sc);
+      PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": session 0x%x connected\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, session));
+      sc->sc_state = PPPOE_STATE_SESSION;
+      pppoe_linkstatus_up(sc); /* notify upper layers */
+      break;
+    case PPPOE_CODE_PADT:
+      if (sc == NULL) {
+        goto done;
+      }
+      pppoe_clear_softc(sc, "received PADT");
+      break;
+    default:
+      if(sc) {
+        printf("%c%c%"U16_F": unknown code (0x%"X16_F") session = 0x%"X16_F"\n",
+            sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num,
+            (u16_t)ph->code, session);
+      } else {
+        printf("pppoe: unknown code (0x%"X16_F") session = 0x%"X16_F"\n", (u16_t)ph->code, session);
+      }
+      break;
+  }
+
+done:
+  pbuf_free(pb);
+  return;
+}
+
+void
+pppoe_disc_input(struct netif *netif, struct pbuf *p)
+{
+  /* avoid error messages if there is not a single pppoe instance */
+  if (pppoe_softc_list != NULL) {
+    pppoe_dispatch_disc_pkt(netif, p);
+  } else {
+    pbuf_free(p);
+  }
+}
+
+void
+pppoe_data_input(struct netif *netif, struct pbuf *pb)
+{
+  u16_t session, plen;
+  struct pppoe_softc *sc;
+  struct pppoehdr *ph;
+#ifdef PPPOE_TERM_UNKNOWN_SESSIONS
+  u8_t shost[ETHER_ADDR_LEN];
+#endif
+
+#ifdef PPPOE_TERM_UNKNOWN_SESSIONS
+  MEMCPY(shost, ((struct eth_hdr *)pb->payload)->src.addr, sizeof(shost));
+#endif
+  if (pbuf_header(pb, -(int)sizeof(struct eth_hdr)) != 0) {
+    /* bail out */
+    PPPDEBUG(LOG_ERR, ("pppoe_data_input: pbuf_header failed\n"));
+    LINK_STATS_INC(link.lenerr);
+    goto drop;
+  } 
+
+  pb = pppSingleBuf (pb);
+
+  if (pb->len <= PPPOE_HEADERLEN) {
+    printf("pppoe (data): dropping too short packet: %d bytes\n", pb->len);
+    goto drop;
+  }
+
+  if (pb->len < sizeof(*ph)) {
+    printf("pppoe_data_input: could not get PPPoE header\n");
+    goto drop;
+  }
+  ph = (struct pppoehdr *)pb->payload;
+
+  if (ph->vertype != PPPOE_VERTYPE) {
+    printf("pppoe (data): unknown version/type packet: 0x%x\n", ph->vertype);
+    goto drop;
+  }
+  if (ph->code != 0) {
+    goto drop;
+  }
+
+  session = ntohs(ph->session);
+  sc = pppoe_find_softc_by_session(session, netif);
+  if (sc == NULL) {
+#ifdef PPPOE_TERM_UNKNOWN_SESSIONS
+    printf("pppoe: input for unknown session 0x%x, sending PADT\n", session);
+    pppoe_send_padt(netif, session, shost);
+#endif
+    goto drop;
+  }
+
+  plen = ntohs(ph->plen);
+
+  if (pbuf_header(pb, -(int)(PPPOE_HEADERLEN)) != 0) {
+    /* bail out */
+    PPPDEBUG(LOG_ERR, ("pppoe_data_input: pbuf_header PPPOE_HEADERLEN failed\n"));
+    LINK_STATS_INC(link.lenerr);
+    goto drop;
+  } 
+
+  PPPDEBUG(LOG_DEBUG, ("pppoe_data_input: %c%c%"U16_F": pkthdr.len=%d, pppoe.len=%d\n",
+        sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num,
+        pb->len, plen));
+
+  if (pb->len < plen) {
+    goto drop;
+  }
+
+  pppInProcOverEthernet(sc->sc_pd, pb);
+
+  return;
+
+drop:
+  pbuf_free(pb);
+}
+
+static err_t
+pppoe_output(struct pppoe_softc *sc, struct pbuf *pb)
+{
+  struct eth_hdr *ethhdr;
+  u16_t etype;
+  err_t res;
+
+  if (!sc->sc_ethif) {
+    pbuf_free(pb);
+    return ERR_IF;
+  }
+
+  ethhdr = (struct eth_hdr *)pb->payload;
+  etype = sc->sc_state == PPPOE_STATE_SESSION ? ETHTYPE_PPPOE : ETHTYPE_PPPOEDISC;
+  ethhdr->type = htons(etype);
+  MEMCPY(ethhdr->dest.addr, sc->sc_dest.addr, sizeof(ethhdr->dest.addr));
+  MEMCPY(ethhdr->src.addr, ((struct eth_addr *)sc->sc_ethif->hwaddr)->addr, sizeof(ethhdr->src.addr));
+
+  PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F" (%x) state=%d, session=0x%x output -> %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F", len=%d\n",
+      sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, etype,
+      sc->sc_state, sc->sc_session,
+      sc->sc_dest.addr[0], sc->sc_dest.addr[1], sc->sc_dest.addr[2], sc->sc_dest.addr[3], sc->sc_dest.addr[4], sc->sc_dest.addr[5],
+      pb->tot_len));
+
+  res = sc->sc_ethif->linkoutput(sc->sc_ethif, pb);
+
+  pbuf_free(pb);
+
+  return res;
+}
+
+static err_t
+pppoe_send_padi(struct pppoe_softc *sc)
+{
+  struct pbuf *pb;
+  u8_t *p;
+  int len;
+#ifdef PPPOE_TODO
+  int l1 = 0, l2 = 0; /* XXX: gcc */
+#endif /* PPPOE_TODO */
+
+  if (sc->sc_state >PPPOE_STATE_PADI_SENT) {
+    PPPDEBUG(LOG_ERR, ("ERROR: pppoe_send_padi in state %d", sc->sc_state));
+  }
+
+  /* calculate length of frame (excluding ethernet header + pppoe header) */
+  len = 2 + 2 + 2 + 2 + sizeof sc;  /* service name tag is required, host unique is send too */
+#ifdef PPPOE_TODO
+  if (sc->sc_service_name != NULL) {
+    l1 = (int)strlen(sc->sc_service_name);
+    len += l1;
+  }
+  if (sc->sc_concentrator_name != NULL) {
+    l2 = (int)strlen(sc->sc_concentrator_name);
+    len += 2 + 2 + l2;
+  }
+#endif /* PPPOE_TODO */
+  LWIP_ASSERT("sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len <= 0xffff",
+    sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len <= 0xffff);
+
+  /* allocate a buffer */
+  pb = pbuf_alloc(PBUF_LINK, (u16_t)(sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len), PBUF_RAM);
+  if (!pb) {
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len);
+
+  p = (u8_t*)pb->payload + sizeof (struct eth_hdr);
+  /* fill in pkt */
+  PPPOE_ADD_HEADER(p, PPPOE_CODE_PADI, 0, (u16_t)len);
+  PPPOE_ADD_16(p, PPPOE_TAG_SNAME);
+#ifdef PPPOE_TODO
+  if (sc->sc_service_name != NULL) {
+    PPPOE_ADD_16(p, l1);
+    MEMCPY(p, sc->sc_service_name, l1);
+    p += l1;
+  } else
+#endif /* PPPOE_TODO */
+  {
+    PPPOE_ADD_16(p, 0);
+  }
+#ifdef PPPOE_TODO
+  if (sc->sc_concentrator_name != NULL) {
+    PPPOE_ADD_16(p, PPPOE_TAG_ACNAME);
+    PPPOE_ADD_16(p, l2);
+    MEMCPY(p, sc->sc_concentrator_name, l2);
+    p += l2;
+  }
+#endif /* PPPOE_TODO */
+  PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE);
+  PPPOE_ADD_16(p, sizeof(sc));
+  MEMCPY(p, &sc, sizeof sc);
+
+  /* send pkt */
+  return pppoe_output(sc, pb);
+}
+
+static void
+pppoe_timeout(void *arg)
+{
+  int retry_wait, err;
+  struct pppoe_softc *sc = (struct pppoe_softc*)arg;
+
+  PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": timeout\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num));
+
+  switch (sc->sc_state) {
+    case PPPOE_STATE_PADI_SENT:
+      /*
+       * We have two basic ways of retrying:
+       *  - Quick retry mode: try a few times in short sequence
+       *  - Slow retry mode: we already had a connection successfully
+       *    established and will try infinitely (without user
+       *    intervention)
+       * We only enter slow retry mode if IFF_LINK1 (aka autodial)
+       * is not set.
+       */
+
+      /* initialize for quick retry mode */
+      retry_wait = PPPOE_DISC_TIMEOUT * (1 + sc->sc_padi_retried);
+
+      sc->sc_padi_retried++;
+      if (sc->sc_padi_retried >= PPPOE_DISC_MAXPADI) {
+#if 0
+        if ((sc->sc_sppp.pp_if.if_flags & IFF_LINK1) == 0) {
+          /* slow retry mode */
+          retry_wait = PPPOE_SLOW_RETRY;
+        } else
+#endif
+        {
+          pppoe_abort_connect(sc);
+          return;
+        }
+      }
+      if ((err = pppoe_send_padi(sc)) != 0) {
+        sc->sc_padi_retried--;
+        PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": failed to transmit PADI, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err));
+      }
+      sys_timeout(retry_wait, pppoe_timeout, sc);
+      break;
+
+    case PPPOE_STATE_PADR_SENT:
+      sc->sc_padr_retried++;
+      if (sc->sc_padr_retried >= PPPOE_DISC_MAXPADR) {
+        MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest));
+        sc->sc_state = PPPOE_STATE_PADI_SENT;
+        sc->sc_padr_retried = 0;
+        if ((err = pppoe_send_padi(sc)) != 0) {
+          PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": failed to send PADI, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err));
+        }
+        sys_timeout(PPPOE_DISC_TIMEOUT * (1 + sc->sc_padi_retried), pppoe_timeout, sc);
+        return;
+      }
+      if ((err = pppoe_send_padr(sc)) != 0) {
+        sc->sc_padr_retried--;
+        PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": failed to send PADR, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err));
+      }
+      sys_timeout(PPPOE_DISC_TIMEOUT * (1 + sc->sc_padr_retried), pppoe_timeout, sc);
+      break;
+    case PPPOE_STATE_CLOSING:
+      pppoe_do_disconnect(sc);
+      break;
+    default:
+      return;  /* all done, work in peace */
+  }
+}
+
+/* Start a connection (i.e. initiate discovery phase) */
+int
+pppoe_connect(struct pppoe_softc *sc)
+{
+  int err;
+
+  if (sc->sc_state != PPPOE_STATE_INITIAL) {
+    return EBUSY;
+  }
+
+#ifdef PPPOE_SERVER
+  /* wait PADI if IFF_PASSIVE */
+  if ((sc->sc_sppp.pp_if.if_flags & IFF_PASSIVE)) {
+    return 0;
+  }
+#endif
+  /* save state, in case we fail to send PADI */
+  sc->sc_state = PPPOE_STATE_PADI_SENT;
+  sc->sc_padr_retried = 0;
+  err = pppoe_send_padi(sc);
+  PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": failed to send PADI, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err));
+  sys_timeout(PPPOE_DISC_TIMEOUT, pppoe_timeout, sc);
+  return err;
+}
+
+/* disconnect */
+void
+pppoe_disconnect(struct pppoe_softc *sc)
+{
+  if (sc->sc_state < PPPOE_STATE_SESSION) {
+    return;
+  }
+  /*
+   * Do not call pppoe_disconnect here, the upper layer state
+   * machine gets confused by this. We must return from this
+   * function and defer disconnecting to the timeout handler.
+   */
+  sc->sc_state = PPPOE_STATE_CLOSING;
+  sys_timeout(20, pppoe_timeout, sc);
+}
+
+static int
+pppoe_do_disconnect(struct pppoe_softc *sc)
+{
+  int err;
+
+  if (sc->sc_state < PPPOE_STATE_SESSION) {
+    err = EBUSY;
+  } else {
+    PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": disconnecting\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num));
+    err = pppoe_send_padt(sc->sc_ethif, sc->sc_session, (const u8_t *)&sc->sc_dest);
+  }
+
+  /* cleanup softc */
+  sc->sc_state = PPPOE_STATE_INITIAL;
+  MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest));
+  sc->sc_ac_cookie_len = 0;
+#ifdef PPPOE_SERVER
+  if (sc->sc_hunique) {
+    mem_free(sc->sc_hunique);
+    sc->sc_hunique = NULL;
+  }
+  sc->sc_hunique_len = 0;
+#endif
+  sc->sc_session = 0;
+
+  sc->sc_linkStatusCB(sc->sc_pd, 0); /* notify upper layers */
+
+  return err;
+}
+
+/* Connection attempt aborted */
+static void
+pppoe_abort_connect(struct pppoe_softc *sc)
+{
+  printf("%c%c%"U16_F": could not establish connection\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num);
+  sc->sc_state = PPPOE_STATE_CLOSING;
+
+  sc->sc_linkStatusCB(sc->sc_pd, 0); /* notify upper layers */
+
+  /* clear connection state */
+  MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest));
+  sc->sc_state = PPPOE_STATE_INITIAL;
+}
+
+/* Send a PADR packet */
+static err_t
+pppoe_send_padr(struct pppoe_softc *sc)
+{
+  struct pbuf *pb;
+  u8_t *p;
+  size_t len;
+#ifdef PPPOE_TODO
+  size_t l1 = 0; /* XXX: gcc */
+#endif /* PPPOE_TODO */
+
+  if (sc->sc_state != PPPOE_STATE_PADR_SENT) {
+    return ERR_CONN;
+  }
+
+  len = 2 + 2 + 2 + 2 + sizeof(sc);    /* service name, host unique */
+#ifdef PPPOE_TODO
+  if (sc->sc_service_name != NULL) {    /* service name tag maybe empty */
+    l1 = strlen(sc->sc_service_name);
+    len += l1;
+  }
+#endif /* PPPOE_TODO */
+  if (sc->sc_ac_cookie_len > 0) {
+    len += 2 + 2 + sc->sc_ac_cookie_len;  /* AC cookie */
+  }
+  LWIP_ASSERT("sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len <= 0xffff",
+    sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len <= 0xffff);
+  pb = pbuf_alloc(PBUF_LINK, (u16_t)(sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len), PBUF_RAM);
+  if (!pb) {
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len);
+  p = (u8_t*)pb->payload + sizeof (struct eth_hdr);
+  PPPOE_ADD_HEADER(p, PPPOE_CODE_PADR, 0, len);
+  PPPOE_ADD_16(p, PPPOE_TAG_SNAME);
+#ifdef PPPOE_TODO
+  if (sc->sc_service_name != NULL) {
+    PPPOE_ADD_16(p, l1);
+    MEMCPY(p, sc->sc_service_name, l1);
+    p += l1;
+  } else
+#endif /* PPPOE_TODO */
+  {
+    PPPOE_ADD_16(p, 0);
+  }
+  if (sc->sc_ac_cookie_len > 0) {
+    PPPOE_ADD_16(p, PPPOE_TAG_ACCOOKIE);
+    PPPOE_ADD_16(p, sc->sc_ac_cookie_len);
+    MEMCPY(p, sc->sc_ac_cookie, sc->sc_ac_cookie_len);
+    p += sc->sc_ac_cookie_len;
+  }
+  PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE);
+  PPPOE_ADD_16(p, sizeof(sc));
+  MEMCPY(p, &sc, sizeof sc);
+
+  return pppoe_output(sc, pb);
+}
+
+/* send a PADT packet */
+static err_t
+pppoe_send_padt(struct netif *outgoing_if, u_int session, const u8_t *dest)
+{
+  struct pbuf *pb;
+  struct eth_hdr *ethhdr;
+  err_t res;
+  u8_t *p;
+
+  pb = pbuf_alloc(PBUF_LINK, sizeof(struct eth_hdr) + PPPOE_HEADERLEN, PBUF_RAM);
+  if (!pb) {
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len);
+
+  ethhdr = (struct eth_hdr *)pb->payload;
+  ethhdr->type = PP_HTONS(ETHTYPE_PPPOEDISC);
+  MEMCPY(ethhdr->dest.addr, dest, sizeof(ethhdr->dest.addr));
+  MEMCPY(ethhdr->src.addr, ((struct eth_addr *)outgoing_if->hwaddr)->addr, sizeof(ethhdr->src.addr));
+
+  p = (u8_t*)(ethhdr + 1);
+  PPPOE_ADD_HEADER(p, PPPOE_CODE_PADT, session, 0);
+
+  res = outgoing_if->linkoutput(outgoing_if, pb);
+
+  pbuf_free(pb);
+
+  return res;
+}
+
+#ifdef PPPOE_SERVER
+static err_t
+pppoe_send_pado(struct pppoe_softc *sc)
+{
+  struct pbuf *pb;
+  u8_t *p;
+  size_t len;
+
+  if (sc->sc_state != PPPOE_STATE_PADO_SENT) {
+    return ERR_CONN;
+  }
+
+  /* calc length */
+  len = 0;
+  /* include ac_cookie */
+  len += 2 + 2 + sizeof(sc);
+  /* include hunique */
+  len += 2 + 2 + sc->sc_hunique_len;
+  pb = pbuf_alloc(PBUF_LINK, sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len, PBUF_RAM);
+  if (!pb) {
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len);
+  p = (u8_t*)pb->payload + sizeof (struct eth_hdr);
+  PPPOE_ADD_HEADER(p, PPPOE_CODE_PADO, 0, len);
+  PPPOE_ADD_16(p, PPPOE_TAG_ACCOOKIE);
+  PPPOE_ADD_16(p, sizeof(sc));
+  MEMCPY(p, &sc, sizeof(sc));
+  p += sizeof(sc);
+  PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE);
+  PPPOE_ADD_16(p, sc->sc_hunique_len);
+  MEMCPY(p, sc->sc_hunique, sc->sc_hunique_len);
+  return pppoe_output(sc, pb);
+}
+
+static err_t
+pppoe_send_pads(struct pppoe_softc *sc)
+{
+  struct pbuf *pb;
+  u8_t *p;
+  size_t len, l1 = 0;  /* XXX: gcc */
+
+  if (sc->sc_state != PPPOE_STATE_PADO_SENT) {
+    return ERR_CONN;
+  }
+
+  sc->sc_session = mono_time.tv_sec % 0xff + 1;
+  /* calc length */
+  len = 0;
+  /* include hunique */
+  len += 2 + 2 + 2 + 2 + sc->sc_hunique_len;  /* service name, host unique*/
+  if (sc->sc_service_name != NULL) {    /* service name tag maybe empty */
+    l1 = strlen(sc->sc_service_name);
+    len += l1;
+  }
+  pb = pbuf_alloc(PBUF_LINK, sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len, PBUF_RAM);
+  if (!pb) {
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len);
+  p = (u8_t*)pb->payload + sizeof (struct eth_hdr);
+  PPPOE_ADD_HEADER(p, PPPOE_CODE_PADS, sc->sc_session, len);
+  PPPOE_ADD_16(p, PPPOE_TAG_SNAME);
+  if (sc->sc_service_name != NULL) {
+    PPPOE_ADD_16(p, l1);
+    MEMCPY(p, sc->sc_service_name, l1);
+    p += l1;
+  } else {
+    PPPOE_ADD_16(p, 0);
+  }
+  PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE);
+  PPPOE_ADD_16(p, sc->sc_hunique_len);
+  MEMCPY(p, sc->sc_hunique, sc->sc_hunique_len);
+  return pppoe_output(sc, pb);
+}
+#endif
+
+err_t
+pppoe_xmit(struct pppoe_softc *sc, struct pbuf *pb)
+{
+  u8_t *p;
+  size_t len;
+
+  /* are we ready to process data yet? */
+  if (sc->sc_state < PPPOE_STATE_SESSION) {
+    /*sppp_flush(&sc->sc_sppp.pp_if);*/
+    pbuf_free(pb);
+    return ERR_CONN;
+  }
+
+  len = pb->tot_len;
+
+  /* make room for Ethernet header - should not fail */
+  if (pbuf_header(pb, sizeof(struct eth_hdr) + PPPOE_HEADERLEN) != 0) {
+    /* bail out */
+    PPPDEBUG(LOG_ERR, ("pppoe: %c%c%"U16_F": pppoe_xmit: could not allocate room for header\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num));
+    LINK_STATS_INC(link.lenerr);
+    pbuf_free(pb);
+    return ERR_BUF;
+  } 
+
+  p = (u8_t*)pb->payload + sizeof(struct eth_hdr);
+  PPPOE_ADD_HEADER(p, 0, sc->sc_session, len);
+
+  return pppoe_output(sc, pb);
+}
+
+#if 0 /*def PFIL_HOOKS*/
+static int
+pppoe_ifattach_hook(void *arg, struct pbuf **mp, struct netif *ifp, int dir)
+{
+  struct pppoe_softc *sc;
+  int s;
+
+  if (mp != (struct pbuf **)PFIL_IFNET_DETACH) {
+    return 0;
+  }
+
+  LIST_FOREACH(sc, &pppoe_softc_list, sc_list) {
+    if (sc->sc_ethif != ifp) {
+      continue;
+    }
+    if (sc->sc_sppp.pp_if.if_flags & IFF_UP) {
+      sc->sc_sppp.pp_if.if_flags &= ~(IFF_UP|IFF_RUNNING);
+      printf("%c%c%"U16_F": ethernet interface detached, going down\n",
+          sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num);
+    }
+    sc->sc_ethif = NULL;
+    pppoe_clear_softc(sc, "ethernet interface detached");
+  }
+
+  return 0;
+}
+#endif
+
+static void
+pppoe_clear_softc(struct pppoe_softc *sc, const char *message)
+{
+  LWIP_UNUSED_ARG(message);
+
+  /* stop timer */
+  sys_untimeout(pppoe_timeout, sc);
+  PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": session 0x%x terminated, %s\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, sc->sc_session, message));
+
+  /* fix our state */
+  sc->sc_state = PPPOE_STATE_INITIAL;
+
+  /* notify upper layers */
+  sc->sc_linkStatusCB(sc->sc_pd, 0);
+
+  /* clean up softc */
+  MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest));
+  sc->sc_ac_cookie_len = 0;
+  sc->sc_session = 0;
+}
+
+#endif /* PPPOE_SUPPORT */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/pppdebug.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/pppdebug.h
new file mode 100644
index 0000000..8134997
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/pppdebug.h
@@ -0,0 +1,73 @@
+/*****************************************************************************
+* pppdebug.h - System debugging utilities.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+* portions Copyright (c) 2001 by Cognizant Pty Ltd.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY (please don't use tabs!)
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-07-29 Guy Lancaster , Global Election Systems Inc.
+*   Original.
+*
+*****************************************************************************
+*/
+#ifndef PPPDEBUG_H
+#define PPPDEBUG_H
+
+/* Trace levels. */
+#define LOG_CRITICAL  (PPP_DEBUG | LWIP_DBG_LEVEL_SEVERE)
+#define LOG_ERR       (PPP_DEBUG | LWIP_DBG_LEVEL_SEVERE)
+#define LOG_NOTICE    (PPP_DEBUG | LWIP_DBG_LEVEL_WARNING)
+#define LOG_WARNING   (PPP_DEBUG | LWIP_DBG_LEVEL_WARNING)
+#define LOG_INFO      (PPP_DEBUG)
+#define LOG_DETAIL    (PPP_DEBUG)
+#define LOG_DEBUG     (PPP_DEBUG)
+
+
+#define TRACELCP PPP_DEBUG
+
+#if PPP_DEBUG
+
+#define AUTHDEBUG(a, b) LWIP_DEBUGF(a, b)
+#define IPCPDEBUG(a, b) LWIP_DEBUGF(a, b)
+#define UPAPDEBUG(a, b) LWIP_DEBUGF(a, b)
+#define LCPDEBUG(a, b)  LWIP_DEBUGF(a, b)
+#define FSMDEBUG(a, b)  LWIP_DEBUGF(a, b)
+#define CHAPDEBUG(a, b) LWIP_DEBUGF(a, b)
+#define PPPDEBUG(a, b)  LWIP_DEBUGF(a, b)
+
+#else /* PPP_DEBUG */
+
+#define AUTHDEBUG(a, b)
+#define IPCPDEBUG(a, b)
+#define UPAPDEBUG(a, b)
+#define LCPDEBUG(a, b)
+#define FSMDEBUG(a, b)
+#define CHAPDEBUG(a, b)
+#define PPPDEBUG(a, b)
+
+#endif /* PPP_DEBUG */
+
+#endif /* PPPDEBUG_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/randm.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/randm.c
new file mode 100644
index 0000000..2f35caf
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/randm.c
@@ -0,0 +1,249 @@
+/*****************************************************************************
+* randm.c - Random number generator program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1998 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-06-03 Guy Lancaster , Global Election Systems Inc.
+*   Extracted from avos.
+*****************************************************************************/
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "md5.h"
+#include "randm.h"
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include 
+
+#if MD5_SUPPORT /* this module depends on MD5 */
+#define RANDPOOLSZ 16   /* Bytes stored in the pool of randomness. */
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static char randPool[RANDPOOLSZ];   /* Pool of randomness. */
+static long randCount = 0;      /* Pseudo-random incrementer */
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * Initialize the random number generator.
+ *
+ * Since this is to be called on power up, we don't have much
+ *  system randomess to work with.  Here all we use is the
+ *  real-time clock.  We'll accumulate more randomness as soon
+ *  as things start happening.
+ */
+void
+avRandomInit()
+{
+  avChurnRand(NULL, 0);
+}
+
+/*
+ * Churn the randomness pool on a random event.  Call this early and often
+ *  on random and semi-random system events to build randomness in time for
+ *  usage.  For randomly timed events, pass a null pointer and a zero length
+ *  and this will use the system timer and other sources to add randomness.
+ *  If new random data is available, pass a pointer to that and it will be
+ *  included.
+ *
+ * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427
+ */
+void
+avChurnRand(char *randData, u32_t randLen)
+{
+  MD5_CTX md5;
+
+  /* LWIP_DEBUGF(LOG_INFO, ("churnRand: %u@%P\n", randLen, randData)); */
+  MD5Init(&md5);
+  MD5Update(&md5, (u_char *)randPool, sizeof(randPool));
+  if (randData) {
+    MD5Update(&md5, (u_char *)randData, randLen);
+  } else {
+    struct {
+      /* INCLUDE fields for any system sources of randomness */
+      char foobar;
+    } sysData;
+
+    /* Load sysData fields here. */
+    MD5Update(&md5, (u_char *)&sysData, sizeof(sysData));
+  }
+  MD5Final((u_char *)randPool, &md5);
+/*  LWIP_DEBUGF(LOG_INFO, ("churnRand: -> 0\n")); */
+}
+
+/*
+ * Use the random pool to generate random data.  This degrades to pseudo
+ *  random when used faster than randomness is supplied using churnRand().
+ * Note: It's important that there be sufficient randomness in randPool
+ *  before this is called for otherwise the range of the result may be
+ *  narrow enough to make a search feasible.
+ *
+ * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427
+ *
+ * XXX Why does he not just call churnRand() for each block?  Probably
+ *  so that you don't ever publish the seed which could possibly help
+ *  predict future values.
+ * XXX Why don't we preserve md5 between blocks and just update it with
+ *  randCount each time?  Probably there is a weakness but I wish that
+ *  it was documented.
+ */
+void
+avGenRand(char *buf, u32_t bufLen)
+{
+  MD5_CTX md5;
+  u_char tmp[16];
+  u32_t n;
+
+  while (bufLen > 0) {
+    n = LWIP_MIN(bufLen, RANDPOOLSZ);
+    MD5Init(&md5);
+    MD5Update(&md5, (u_char *)randPool, sizeof(randPool));
+    MD5Update(&md5, (u_char *)&randCount, sizeof(randCount));
+    MD5Final(tmp, &md5);
+    randCount++;
+    MEMCPY(buf, tmp, n);
+    buf += n;
+    bufLen -= n;
+  }
+}
+
+/*
+ * Return a new random number.
+ */
+u32_t
+avRandom()
+{
+  u32_t newRand;
+
+  avGenRand((char *)&newRand, sizeof(newRand));
+
+  return newRand;
+}
+
+#else /* MD5_SUPPORT */
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static int  avRandomized = 0;       /* Set when truely randomized. */
+static u32_t avRandomSeed = 0;      /* Seed used for random number generation. */
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * Initialize the random number generator.
+ *
+ * Here we attempt to compute a random number seed but even if
+ * it isn't random, we'll randomize it later.
+ *
+ * The current method uses the fields from the real time clock,
+ * the idle process counter, the millisecond counter, and the
+ * hardware timer tick counter.  When this is invoked
+ * in startup(), then the idle counter and timer values may
+ * repeat after each boot and the real time clock may not be
+ * operational.  Thus we call it again on the first random
+ * event.
+ */
+void
+avRandomInit()
+{
+#if 0
+  /* Get a pointer into the last 4 bytes of clockBuf. */
+  u32_t *lptr1 = (u32_t *)((char *)&clockBuf[3]);
+
+  /*
+   * Initialize our seed using the real-time clock, the idle
+   * counter, the millisecond timer, and the hardware timer
+   * tick counter.  The real-time clock and the hardware
+   * tick counter are the best sources of randomness but
+   * since the tick counter is only 16 bit (and truncated
+   * at that), the idle counter and millisecond timer
+   * (which may be small values) are added to help
+   * randomize the lower 16 bits of the seed.
+   */
+  readClk();
+  avRandomSeed += *(u32_t *)clockBuf + *lptr1 + OSIdleCtr
+           + ppp_mtime() + ((u32_t)TM1 << 16) + TM1;
+#else
+  avRandomSeed += sys_jiffies(); /* XXX */
+#endif
+
+  /* Initialize the Borland random number generator. */
+  srand((unsigned)avRandomSeed);
+}
+
+/*
+ * Randomize our random seed value.  Here we use the fact that
+ * this function is called at *truely random* times by the polling
+ * and network functions.  Here we only get 16 bits of new random
+ * value but we use the previous value to randomize the other 16
+ * bits.
+ */
+void
+avRandomize(void)
+{
+  static u32_t last_jiffies;
+
+  if (!avRandomized) {
+    avRandomized = !0;
+    avRandomInit();
+    /* The initialization function also updates the seed. */
+  } else {
+    /* avRandomSeed += (avRandomSeed << 16) + TM1; */
+    avRandomSeed += (sys_jiffies() - last_jiffies); /* XXX */
+  }
+  last_jiffies = sys_jiffies();
+}
+
+/*
+ * Return a new random number.
+ * Here we use the Borland rand() function to supply a pseudo random
+ * number which we make truely random by combining it with our own
+ * seed which is randomized by truely random events. 
+ * Thus the numbers will be truely random unless there have been no
+ * operator or network events in which case it will be pseudo random
+ * seeded by the real time clock.
+ */
+u32_t
+avRandom()
+{
+  return ((((u32_t)rand() << 16) + rand()) + avRandomSeed);
+}
+
+#endif /* MD5_SUPPORT */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/randm.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/randm.h
new file mode 100644
index 0000000..a0984b0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/randm.h
@@ -0,0 +1,81 @@
+/*****************************************************************************
+* randm.h - Random number generator header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-05-29 Guy Lancaster , Global Election Systems Inc.
+*   Extracted from avos.
+*****************************************************************************/
+
+#ifndef RANDM_H
+#define RANDM_H
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+/*
+ * Initialize the random number generator.
+ */
+void avRandomInit(void);
+
+/*
+ * Churn the randomness pool on a random event.  Call this early and often
+ * on random and semi-random system events to build randomness in time for
+ * usage.  For randomly timed events, pass a null pointer and a zero length
+ * and this will use the system timer and other sources to add randomness.
+ * If new random data is available, pass a pointer to that and it will be
+ * included.
+ */
+void avChurnRand(char *randData, u32_t randLen);
+
+/*
+ * Randomize our random seed value.  To be called for truely random events
+ * such as user operations and network traffic.
+ */
+#if MD5_SUPPORT
+#define avRandomize() avChurnRand(NULL, 0)
+#else  /* MD5_SUPPORT */
+void avRandomize(void);
+#endif /* MD5_SUPPORT */
+
+/*
+ * Use the random pool to generate random data.  This degrades to pseudo
+ * random when used faster than randomness is supplied using churnRand().
+ * Thus it's important to make sure that the results of this are not
+ * published directly because one could predict the next result to at
+ * least some degree.  Also, it's important to get a good seed before
+ * the first use.
+ */
+void avGenRand(char *buf, u32_t bufLen);
+
+/*
+ * Return a new random number.
+ */
+u32_t avRandom(void);
+
+
+#endif /* RANDM_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/vj.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/vj.c
new file mode 100644
index 0000000..b7f2d54
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/vj.c
@@ -0,0 +1,652 @@
+/*
+ * Routines to compress and uncompess tcp packets (for transmission
+ * over low speed serial lines.
+ *
+ * Copyright (c) 1989 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Berkeley.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
+ *   Initial distribution.
+ *
+ * Modified June 1993 by Paul Mackerras, paulus@cs.anu.edu.au,
+ * so that the entire packet being decompressed doesn't have
+ * to be in contiguous memory (just the compressed header).
+ *
+ * Modified March 1998 by Guy Lancaster, glanca@gesn.com,
+ * for a 16 bit processor.
+ */
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#include "vj.h"
+
+#include 
+
+#if VJ_SUPPORT
+
+#if LINK_STATS
+#define INCR(counter) ++comp->stats.counter
+#else
+#define INCR(counter)
+#endif
+
+void
+vj_compress_init(struct vjcompress *comp)
+{
+  register u_char i;
+  register struct cstate *tstate = comp->tstate;
+  
+#if MAX_SLOTS == 0
+  memset((char *)comp, 0, sizeof(*comp));
+#endif
+  comp->maxSlotIndex = MAX_SLOTS - 1;
+  comp->compressSlot = 0;    /* Disable slot ID compression by default. */
+  for (i = MAX_SLOTS - 1; i > 0; --i) {
+    tstate[i].cs_id = i;
+    tstate[i].cs_next = &tstate[i - 1];
+  }
+  tstate[0].cs_next = &tstate[MAX_SLOTS - 1];
+  tstate[0].cs_id = 0;
+  comp->last_cs = &tstate[0];
+  comp->last_recv = 255;
+  comp->last_xmit = 255;
+  comp->flags = VJF_TOSS;
+}
+
+
+/* ENCODE encodes a number that is known to be non-zero.  ENCODEZ
+ * checks for zero (since zero has to be encoded in the long, 3 byte
+ * form).
+ */
+#define ENCODE(n) { \
+  if ((u_short)(n) >= 256) { \
+    *cp++ = 0; \
+    cp[1] = (u_char)(n); \
+    cp[0] = (u_char)((n) >> 8); \
+    cp += 2; \
+  } else { \
+    *cp++ = (u_char)(n); \
+  } \
+}
+#define ENCODEZ(n) { \
+  if ((u_short)(n) >= 256 || (u_short)(n) == 0) { \
+    *cp++ = 0; \
+    cp[1] = (u_char)(n); \
+    cp[0] = (u_char)((n) >> 8); \
+    cp += 2; \
+  } else { \
+    *cp++ = (u_char)(n); \
+  } \
+}
+
+#define DECODEL(f) { \
+  if (*cp == 0) {\
+    u32_t tmp = ntohl(f) + ((cp[1] << 8) | cp[2]); \
+    (f) = htonl(tmp); \
+    cp += 3; \
+  } else { \
+    u32_t tmp = ntohl(f) + (u32_t)*cp++; \
+    (f) = htonl(tmp); \
+  } \
+}
+
+#define DECODES(f) { \
+  if (*cp == 0) {\
+    u_short tmp = ntohs(f) + (((u_short)cp[1] << 8) | cp[2]); \
+    (f) = htons(tmp); \
+    cp += 3; \
+  } else { \
+    u_short tmp = ntohs(f) + (u_short)*cp++; \
+    (f) = htons(tmp); \
+  } \
+}
+
+#define DECODEU(f) { \
+  if (*cp == 0) {\
+    (f) = htons(((u_short)cp[1] << 8) | cp[2]); \
+    cp += 3; \
+  } else { \
+    (f) = htons((u_short)*cp++); \
+  } \
+}
+
+/*
+ * vj_compress_tcp - Attempt to do Van Jacobson header compression on a
+ * packet.  This assumes that nb and comp are not null and that the first
+ * buffer of the chain contains a valid IP header.
+ * Return the VJ type code indicating whether or not the packet was
+ * compressed.
+ */
+u_int
+vj_compress_tcp(struct vjcompress *comp, struct pbuf *pb)
+{
+  register struct ip_hdr *ip = (struct ip_hdr *)pb->payload;
+  register struct cstate *cs = comp->last_cs->cs_next;
+  register u_short hlen = IPH_HL(ip);
+  register struct tcp_hdr *oth;
+  register struct tcp_hdr *th;
+  register u_short deltaS, deltaA;
+  register u_long deltaL;
+  register u_int changes = 0;
+  u_char new_seq[16];
+  register u_char *cp = new_seq;
+
+  /*  
+   * Check that the packet is IP proto TCP.
+   */
+  if (IPH_PROTO(ip) != IP_PROTO_TCP) {
+    return (TYPE_IP);
+  }
+
+  /*
+   * Bail if this is an IP fragment or if the TCP packet isn't
+   * `compressible' (i.e., ACK isn't set or some other control bit is
+   * set).  
+   */
+  if ((IPH_OFFSET(ip) & PP_HTONS(0x3fff)) || pb->tot_len < 40) {
+    return (TYPE_IP);
+  }
+  th = (struct tcp_hdr *)&((long *)ip)[hlen];
+  if ((TCPH_FLAGS(th) & (TCP_SYN|TCP_FIN|TCP_RST|TCP_ACK)) != TCP_ACK) {
+    return (TYPE_IP);
+  }
+  /*
+   * Packet is compressible -- we're going to send either a
+   * COMPRESSED_TCP or UNCOMPRESSED_TCP packet.  Either way we need
+   * to locate (or create) the connection state.  Special case the
+   * most recently used connection since it's most likely to be used
+   * again & we don't have to do any reordering if it's used.
+   */
+  INCR(vjs_packets);
+  if (!ip_addr_cmp(&ip->src, &cs->cs_ip.src)
+      || !ip_addr_cmp(&ip->dest, &cs->cs_ip.dest)
+      || *(long *)th != ((long *)&cs->cs_ip)[IPH_HL(&cs->cs_ip)]) {
+    /*
+     * Wasn't the first -- search for it.
+     *
+     * States are kept in a circularly linked list with
+     * last_cs pointing to the end of the list.  The
+     * list is kept in lru order by moving a state to the
+     * head of the list whenever it is referenced.  Since
+     * the list is short and, empirically, the connection
+     * we want is almost always near the front, we locate
+     * states via linear search.  If we don't find a state
+     * for the datagram, the oldest state is (re-)used.
+     */
+    register struct cstate *lcs;
+    register struct cstate *lastcs = comp->last_cs;
+    
+    do {
+      lcs = cs; cs = cs->cs_next;
+      INCR(vjs_searches);
+      if (ip_addr_cmp(&ip->src, &cs->cs_ip.src)
+          && ip_addr_cmp(&ip->dest, &cs->cs_ip.dest)
+          && *(long *)th == ((long *)&cs->cs_ip)[IPH_HL(&cs->cs_ip)]) {
+        goto found;
+      }
+    } while (cs != lastcs);
+
+    /*
+     * Didn't find it -- re-use oldest cstate.  Send an
+     * uncompressed packet that tells the other side what
+     * connection number we're using for this conversation.
+     * Note that since the state list is circular, the oldest
+     * state points to the newest and we only need to set
+     * last_cs to update the lru linkage.
+     */
+    INCR(vjs_misses);
+    comp->last_cs = lcs;
+    hlen += TCPH_OFFSET(th);
+    hlen <<= 2;
+    /* Check that the IP/TCP headers are contained in the first buffer. */
+    if (hlen > pb->len) {
+      return (TYPE_IP);
+    }
+    goto uncompressed;
+
+    found:
+    /*
+     * Found it -- move to the front on the connection list.
+     */
+    if (cs == lastcs) {
+      comp->last_cs = lcs;
+    } else {
+      lcs->cs_next = cs->cs_next;
+      cs->cs_next = lastcs->cs_next;
+      lastcs->cs_next = cs;
+    }
+  }
+
+  oth = (struct tcp_hdr *)&((long *)&cs->cs_ip)[hlen];
+  deltaS = hlen;
+  hlen += TCPH_OFFSET(th);
+  hlen <<= 2;
+  /* Check that the IP/TCP headers are contained in the first buffer. */
+  if (hlen > pb->len) {
+    PPPDEBUG(LOG_INFO, ("vj_compress_tcp: header len %d spans buffers\n", hlen));
+    return (TYPE_IP);
+  }
+
+  /*
+   * Make sure that only what we expect to change changed. The first
+   * line of the `if' checks the IP protocol version, header length &
+   * type of service.  The 2nd line checks the "Don't fragment" bit.
+   * The 3rd line checks the time-to-live and protocol (the protocol
+   * check is unnecessary but costless).  The 4th line checks the TCP
+   * header length.  The 5th line checks IP options, if any.  The 6th
+   * line checks TCP options, if any.  If any of these things are
+   * different between the previous & current datagram, we send the
+   * current datagram `uncompressed'.
+   */
+  if (((u_short *)ip)[0] != ((u_short *)&cs->cs_ip)[0] 
+      || ((u_short *)ip)[3] != ((u_short *)&cs->cs_ip)[3] 
+      || ((u_short *)ip)[4] != ((u_short *)&cs->cs_ip)[4] 
+      || TCPH_OFFSET(th) != TCPH_OFFSET(oth) 
+      || (deltaS > 5 && BCMP(ip + 1, &cs->cs_ip + 1, (deltaS - 5) << 2)) 
+      || (TCPH_OFFSET(th) > 5 && BCMP(th + 1, oth + 1, (TCPH_OFFSET(th) - 5) << 2))) {
+    goto uncompressed;
+  }
+
+  /*
+   * Figure out which of the changing fields changed.  The
+   * receiver expects changes in the order: urgent, window,
+   * ack, seq (the order minimizes the number of temporaries
+   * needed in this section of code).
+   */
+  if (TCPH_FLAGS(th) & TCP_URG) {
+    deltaS = ntohs(th->urgp);
+    ENCODEZ(deltaS);
+    changes |= NEW_U;
+  } else if (th->urgp != oth->urgp) {
+    /* argh! URG not set but urp changed -- a sensible
+     * implementation should never do this but RFC793
+     * doesn't prohibit the change so we have to deal
+     * with it. */
+    goto uncompressed;
+  }
+
+  if ((deltaS = (u_short)(ntohs(th->wnd) - ntohs(oth->wnd))) != 0) {
+    ENCODE(deltaS);
+    changes |= NEW_W;
+  }
+
+  if ((deltaL = ntohl(th->ackno) - ntohl(oth->ackno)) != 0) {
+    if (deltaL > 0xffff) {
+      goto uncompressed;
+    }
+    deltaA = (u_short)deltaL;
+    ENCODE(deltaA);
+    changes |= NEW_A;
+  }
+
+  if ((deltaL = ntohl(th->seqno) - ntohl(oth->seqno)) != 0) {
+    if (deltaL > 0xffff) {
+      goto uncompressed;
+    }
+    deltaS = (u_short)deltaL;
+    ENCODE(deltaS);
+    changes |= NEW_S;
+  }
+
+  switch(changes) {
+  case 0:
+    /*
+     * Nothing changed. If this packet contains data and the
+     * last one didn't, this is probably a data packet following
+     * an ack (normal on an interactive connection) and we send
+     * it compressed.  Otherwise it's probably a retransmit,
+     * retransmitted ack or window probe.  Send it uncompressed
+     * in case the other side missed the compressed version.
+     */
+    if (IPH_LEN(ip) != IPH_LEN(&cs->cs_ip) &&
+      ntohs(IPH_LEN(&cs->cs_ip)) == hlen) {
+      break;
+    }
+
+  /* (fall through) */
+
+  case SPECIAL_I:
+  case SPECIAL_D:
+    /*
+     * actual changes match one of our special case encodings --
+     * send packet uncompressed.
+     */
+    goto uncompressed;
+
+  case NEW_S|NEW_A:
+    if (deltaS == deltaA && deltaS == ntohs(IPH_LEN(&cs->cs_ip)) - hlen) {
+      /* special case for echoed terminal traffic */
+      changes = SPECIAL_I;
+      cp = new_seq;
+    }
+    break;
+
+  case NEW_S:
+    if (deltaS == ntohs(IPH_LEN(&cs->cs_ip)) - hlen) {
+      /* special case for data xfer */
+      changes = SPECIAL_D;
+      cp = new_seq;
+    }
+    break;
+  }
+
+  deltaS = (u_short)(ntohs(IPH_ID(ip)) - ntohs(IPH_ID(&cs->cs_ip)));
+  if (deltaS != 1) {
+    ENCODEZ(deltaS);
+    changes |= NEW_I;
+  }
+  if (TCPH_FLAGS(th) & TCP_PSH) {
+    changes |= TCP_PUSH_BIT;
+  }
+  /*
+   * Grab the cksum before we overwrite it below.  Then update our
+   * state with this packet's header.
+   */
+  deltaA = ntohs(th->chksum);
+  BCOPY(ip, &cs->cs_ip, hlen);
+
+  /*
+   * We want to use the original packet as our compressed packet.
+   * (cp - new_seq) is the number of bytes we need for compressed
+   * sequence numbers.  In addition we need one byte for the change
+   * mask, one for the connection id and two for the tcp checksum.
+   * So, (cp - new_seq) + 4 bytes of header are needed.  hlen is how
+   * many bytes of the original packet to toss so subtract the two to
+   * get the new packet size.
+   */
+  deltaS = (u_short)(cp - new_seq);
+  if (!comp->compressSlot || comp->last_xmit != cs->cs_id) {
+    comp->last_xmit = cs->cs_id;
+    hlen -= deltaS + 4;
+    if(pbuf_header(pb, -hlen)){
+      /* Can we cope with this failing?  Just assert for now */
+      LWIP_ASSERT("pbuf_header failed\n", 0);
+    }
+    cp = (u_char *)pb->payload;
+    *cp++ = (u_char)(changes | NEW_C);
+    *cp++ = cs->cs_id;
+  } else {
+    hlen -= deltaS + 3;
+    if(pbuf_header(pb, -hlen)) {
+      /* Can we cope with this failing?  Just assert for now */
+      LWIP_ASSERT("pbuf_header failed\n", 0);
+    }
+    cp = (u_char *)pb->payload;
+    *cp++ = (u_char)changes;
+  }
+  *cp++ = (u_char)(deltaA >> 8);
+  *cp++ = (u_char)deltaA;
+  BCOPY(new_seq, cp, deltaS);
+  INCR(vjs_compressed);
+  return (TYPE_COMPRESSED_TCP);
+
+  /*
+   * Update connection state cs & send uncompressed packet (that is,
+   * a regular ip/tcp packet but with the 'conversation id' we hope
+   * to use on future compressed packets in the protocol field).
+   */
+uncompressed:
+  BCOPY(ip, &cs->cs_ip, hlen);
+  IPH_PROTO_SET(ip, cs->cs_id);
+  comp->last_xmit = cs->cs_id;
+  return (TYPE_UNCOMPRESSED_TCP);
+}
+
+/*
+ * Called when we may have missed a packet.
+ */
+void
+vj_uncompress_err(struct vjcompress *comp)
+{
+  comp->flags |= VJF_TOSS;
+  INCR(vjs_errorin);
+}
+
+/*
+ * "Uncompress" a packet of type TYPE_UNCOMPRESSED_TCP.
+ * Return 0 on success, -1 on failure.
+ */
+int
+vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp)
+{
+  register u_int hlen;
+  register struct cstate *cs;
+  register struct ip_hdr *ip;
+  
+  ip = (struct ip_hdr *)nb->payload;
+  hlen = IPH_HL(ip) << 2;
+  if (IPH_PROTO(ip) >= MAX_SLOTS
+      || hlen + sizeof(struct tcp_hdr) > nb->len
+      || (hlen += TCPH_OFFSET(((struct tcp_hdr *)&((char *)ip)[hlen])) << 2)
+          > nb->len
+      || hlen > MAX_HDR) {
+    PPPDEBUG(LOG_INFO, ("vj_uncompress_uncomp: bad cid=%d, hlen=%d buflen=%d\n", 
+      IPH_PROTO(ip), hlen, nb->len));
+    comp->flags |= VJF_TOSS;
+    INCR(vjs_errorin);
+    return -1;
+  }
+  cs = &comp->rstate[comp->last_recv = IPH_PROTO(ip)];
+  comp->flags &=~ VJF_TOSS;
+  IPH_PROTO_SET(ip, IP_PROTO_TCP);
+  BCOPY(ip, &cs->cs_ip, hlen);
+  cs->cs_hlen = (u_short)hlen;
+  INCR(vjs_uncompressedin);
+  return 0;
+}
+
+/*
+ * Uncompress a packet of type TYPE_COMPRESSED_TCP.
+ * The packet is composed of a buffer chain and the first buffer
+ * must contain an accurate chain length.
+ * The first buffer must include the entire compressed TCP/IP header. 
+ * This procedure replaces the compressed header with the uncompressed
+ * header and returns the length of the VJ header.
+ */
+int
+vj_uncompress_tcp(struct pbuf **nb, struct vjcompress *comp)
+{
+  u_char *cp;
+  struct tcp_hdr *th;
+  struct cstate *cs;
+  u_short *bp;
+  struct pbuf *n0 = *nb;
+  u32_t tmp;
+  u_int vjlen, hlen, changes;
+
+  INCR(vjs_compressedin);
+  cp = (u_char *)n0->payload;
+  changes = *cp++;
+  if (changes & NEW_C) {
+    /* 
+     * Make sure the state index is in range, then grab the state.
+     * If we have a good state index, clear the 'discard' flag. 
+     */
+    if (*cp >= MAX_SLOTS) {
+      PPPDEBUG(LOG_INFO, ("vj_uncompress_tcp: bad cid=%d\n", *cp));
+      goto bad;
+    }
+
+    comp->flags &=~ VJF_TOSS;
+    comp->last_recv = *cp++;
+  } else {
+    /* 
+     * this packet has an implicit state index.  If we've
+     * had a line error since the last time we got an
+     * explicit state index, we have to toss the packet. 
+     */
+    if (comp->flags & VJF_TOSS) {
+      PPPDEBUG(LOG_INFO, ("vj_uncompress_tcp: tossing\n"));
+      INCR(vjs_tossed);
+      return (-1);
+    }
+  }
+  cs = &comp->rstate[comp->last_recv];
+  hlen = IPH_HL(&cs->cs_ip) << 2;
+  th = (struct tcp_hdr *)&((u_char *)&cs->cs_ip)[hlen];
+  th->chksum = htons((*cp << 8) | cp[1]);
+  cp += 2;
+  if (changes & TCP_PUSH_BIT) {
+    TCPH_SET_FLAG(th, TCP_PSH);
+  } else {
+    TCPH_UNSET_FLAG(th, TCP_PSH);
+  }
+
+  switch (changes & SPECIALS_MASK) {
+  case SPECIAL_I:
+    {
+      register u32_t i = ntohs(IPH_LEN(&cs->cs_ip)) - cs->cs_hlen;
+      /* some compilers can't nest inline assembler.. */
+      tmp = ntohl(th->ackno) + i;
+      th->ackno = htonl(tmp);
+      tmp = ntohl(th->seqno) + i;
+      th->seqno = htonl(tmp);
+    }
+    break;
+
+  case SPECIAL_D:
+    /* some compilers can't nest inline assembler.. */
+    tmp = ntohl(th->seqno) + ntohs(IPH_LEN(&cs->cs_ip)) - cs->cs_hlen;
+    th->seqno = htonl(tmp);
+    break;
+
+  default:
+    if (changes & NEW_U) {
+      TCPH_SET_FLAG(th, TCP_URG);
+      DECODEU(th->urgp);
+    } else {
+      TCPH_UNSET_FLAG(th, TCP_URG);
+    }
+    if (changes & NEW_W) {
+      DECODES(th->wnd);
+    }
+    if (changes & NEW_A) {
+      DECODEL(th->ackno);
+    }
+    if (changes & NEW_S) {
+      DECODEL(th->seqno);
+    }
+    break;
+  }
+  if (changes & NEW_I) {
+    DECODES(cs->cs_ip._id);
+  } else {
+    IPH_ID_SET(&cs->cs_ip, ntohs(IPH_ID(&cs->cs_ip)) + 1);
+    IPH_ID_SET(&cs->cs_ip, htons(IPH_ID(&cs->cs_ip)));
+  }
+
+  /*
+   * At this point, cp points to the first byte of data in the
+   * packet.  Fill in the IP total length and update the IP
+   * header checksum.
+   */
+  vjlen = (u_short)(cp - (u_char*)n0->payload);
+  if (n0->len < vjlen) {
+    /* 
+     * We must have dropped some characters (crc should detect
+     * this but the old slip framing won't) 
+     */
+    PPPDEBUG(LOG_INFO, ("vj_uncompress_tcp: head buffer %d too short %d\n", 
+          n0->len, vjlen));
+    goto bad;
+  }
+
+#if BYTE_ORDER == LITTLE_ENDIAN
+  tmp = n0->tot_len - vjlen + cs->cs_hlen;
+  IPH_LEN_SET(&cs->cs_ip, htons((u_short)tmp));
+#else
+  IPH_LEN_SET(&cs->cs_ip, htons(n0->tot_len - vjlen + cs->cs_hlen));
+#endif
+
+  /* recompute the ip header checksum */
+  bp = (u_short *) &cs->cs_ip;
+  IPH_CHKSUM_SET(&cs->cs_ip, 0);
+  for (tmp = 0; hlen > 0; hlen -= 2) {
+    tmp += *bp++;
+  }
+  tmp = (tmp & 0xffff) + (tmp >> 16);
+  tmp = (tmp & 0xffff) + (tmp >> 16);
+  IPH_CHKSUM_SET(&cs->cs_ip,  (u_short)(~tmp));
+  
+  /* Remove the compressed header and prepend the uncompressed header. */
+  if(pbuf_header(n0, -((s16_t)(vjlen)))) {
+    /* Can we cope with this failing?  Just assert for now */
+    LWIP_ASSERT("pbuf_header failed\n", 0);
+    goto bad;
+  }
+
+  if(LWIP_MEM_ALIGN(n0->payload) != n0->payload) {
+    struct pbuf *np, *q;
+    u8_t *bufptr;
+
+    np = pbuf_alloc(PBUF_RAW, n0->len + cs->cs_hlen, PBUF_POOL);
+    if(!np) {
+      PPPDEBUG(LOG_WARNING, ("vj_uncompress_tcp: realign failed\n"));
+      goto bad;
+    }
+
+    if(pbuf_header(np, -cs->cs_hlen)) {
+      /* Can we cope with this failing?  Just assert for now */
+      LWIP_ASSERT("pbuf_header failed\n", 0);
+      goto bad;
+    }
+
+    bufptr = n0->payload;
+    for(q = np; q != NULL; q = q->next) {
+      MEMCPY(q->payload, bufptr, q->len);
+      bufptr += q->len;
+    }
+
+    if(n0->next) {
+      pbuf_chain(np, n0->next);
+      pbuf_dechain(n0);
+    }
+    pbuf_free(n0);
+    n0 = np;
+  }
+
+  if(pbuf_header(n0, cs->cs_hlen)) {
+    struct pbuf *np;
+
+    LWIP_ASSERT("vj_uncompress_tcp: cs->cs_hlen <= PBUF_POOL_BUFSIZE", cs->cs_hlen <= PBUF_POOL_BUFSIZE);
+    np = pbuf_alloc(PBUF_RAW, cs->cs_hlen, PBUF_POOL);
+    if(!np) {
+      PPPDEBUG(LOG_WARNING, ("vj_uncompress_tcp: prepend failed\n"));
+      goto bad;
+    }
+    pbuf_cat(np, n0);
+    n0 = np;
+  }
+  LWIP_ASSERT("n0->len >= cs->cs_hlen", n0->len >= cs->cs_hlen);
+  MEMCPY(n0->payload, &cs->cs_ip, cs->cs_hlen);
+
+  *nb = n0;
+
+  return vjlen;
+
+bad:
+  comp->flags |= VJF_TOSS;
+  INCR(vjs_errorin);
+  return (-1);
+}
+
+#endif /* VJ_SUPPORT */
+
+#endif /* PPP_SUPPORT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/vj.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/vj.h
new file mode 100644
index 0000000..fad1213
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/ppp/vj.h
@@ -0,0 +1,156 @@
+/*
+ * Definitions for tcp compression routines.
+ *
+ * $Id: vj.h,v 1.7 2010/02/22 17:52:09 goldsimon Exp $
+ *
+ * Copyright (c) 1989 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Berkeley.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
+ * - Initial distribution.
+ */
+
+#ifndef VJ_H
+#define VJ_H
+
+#include "lwip/ip.h"
+#include "lwip/tcp_impl.h"
+
+#define MAX_SLOTS 16 /* must be > 2 and < 256 */
+#define MAX_HDR   128
+
+/*
+ * Compressed packet format:
+ *
+ * The first octet contains the packet type (top 3 bits), TCP
+ * 'push' bit, and flags that indicate which of the 4 TCP sequence
+ * numbers have changed (bottom 5 bits).  The next octet is a
+ * conversation number that associates a saved IP/TCP header with
+ * the compressed packet.  The next two octets are the TCP checksum
+ * from the original datagram.  The next 0 to 15 octets are
+ * sequence number changes, one change per bit set in the header
+ * (there may be no changes and there are two special cases where
+ * the receiver implicitly knows what changed -- see below).
+ * 
+ * There are 5 numbers which can change (they are always inserted
+ * in the following order): TCP urgent pointer, window,
+ * acknowlegement, sequence number and IP ID.  (The urgent pointer
+ * is different from the others in that its value is sent, not the
+ * change in value.)  Since typical use of SLIP links is biased
+ * toward small packets (see comments on MTU/MSS below), changes
+ * use a variable length coding with one octet for numbers in the
+ * range 1 - 255 and 3 octets (0, MSB, LSB) for numbers in the
+ * range 256 - 65535 or 0.  (If the change in sequence number or
+ * ack is more than 65535, an uncompressed packet is sent.)
+ */
+
+/*
+ * Packet types (must not conflict with IP protocol version)
+ *
+ * The top nibble of the first octet is the packet type.  There are
+ * three possible types: IP (not proto TCP or tcp with one of the
+ * control flags set); uncompressed TCP (a normal IP/TCP packet but
+ * with the 8-bit protocol field replaced by an 8-bit connection id --
+ * this type of packet syncs the sender & receiver); and compressed
+ * TCP (described above).
+ *
+ * LSB of 4-bit field is TCP "PUSH" bit (a worthless anachronism) and
+ * is logically part of the 4-bit "changes" field that follows.  Top
+ * three bits are actual packet type.  For backward compatibility
+ * and in the interest of conserving bits, numbers are chosen so the
+ * IP protocol version number (4) which normally appears in this nibble
+ * means "IP packet".
+ */
+
+/* packet types */
+#define TYPE_IP               0x40
+#define TYPE_UNCOMPRESSED_TCP 0x70
+#define TYPE_COMPRESSED_TCP   0x80
+#define TYPE_ERROR            0x00
+
+/* Bits in first octet of compressed packet */
+#define NEW_C 0x40 /* flag bits for what changed in a packet */
+#define NEW_I 0x20
+#define NEW_S 0x08
+#define NEW_A 0x04
+#define NEW_W 0x02
+#define NEW_U 0x01
+
+/* reserved, special-case values of above */
+#define SPECIAL_I (NEW_S|NEW_W|NEW_U) /* echoed interactive traffic */
+#define SPECIAL_D (NEW_S|NEW_A|NEW_W|NEW_U) /* unidirectional data */
+#define SPECIALS_MASK (NEW_S|NEW_A|NEW_W|NEW_U)
+
+#define TCP_PUSH_BIT 0x10
+
+
+/*
+ * "state" data for each active tcp conversation on the wire.  This is
+ * basically a copy of the entire IP/TCP header from the last packet
+ * we saw from the conversation together with a small identifier
+ * the transmit & receive ends of the line use to locate saved header.
+ */
+struct cstate {
+  struct cstate *cs_next; /* next most recently used state (xmit only) */
+  u_short cs_hlen;        /* size of hdr (receive only) */
+  u_char cs_id;           /* connection # associated with this state */
+  u_char cs_filler;
+  union {
+    char csu_hdr[MAX_HDR];
+    struct ip_hdr csu_ip;     /* ip/tcp hdr from most recent packet */
+  } vjcs_u;
+};
+#define cs_ip vjcs_u.csu_ip
+#define cs_hdr vjcs_u.csu_hdr
+
+
+struct vjstat {
+  unsigned long vjs_packets;        /* outbound packets */
+  unsigned long vjs_compressed;     /* outbound compressed packets */
+  unsigned long vjs_searches;       /* searches for connection state */
+  unsigned long vjs_misses;         /* times couldn't find conn. state */
+  unsigned long vjs_uncompressedin; /* inbound uncompressed packets */
+  unsigned long vjs_compressedin;   /* inbound compressed packets */
+  unsigned long vjs_errorin;        /* inbound unknown type packets */
+  unsigned long vjs_tossed;         /* inbound packets tossed because of error */
+};
+
+/*
+ * all the state data for one serial line (we need one of these per line).
+ */
+struct vjcompress {
+  struct cstate *last_cs;          /* most recently used tstate */
+  u_char last_recv;                /* last rcvd conn. id */
+  u_char last_xmit;                /* last sent conn. id */
+  u_short flags;
+  u_char maxSlotIndex;
+  u_char compressSlot;             /* Flag indicating OK to compress slot ID. */
+#if LINK_STATS
+  struct vjstat stats;
+#endif
+  struct cstate tstate[MAX_SLOTS]; /* xmit connection states */
+  struct cstate rstate[MAX_SLOTS]; /* receive connection states */
+};
+
+/* flag values */
+#define VJF_TOSS 1U /* tossing rcvd frames because of input err */
+
+extern void  vj_compress_init    (struct vjcompress *comp);
+extern u_int vj_compress_tcp     (struct vjcompress *comp, struct pbuf *pb);
+extern void  vj_uncompress_err   (struct vjcompress *comp);
+extern int   vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp);
+extern int   vj_uncompress_tcp   (struct pbuf **nb, struct vjcompress *comp);
+
+#endif /* VJ_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/slipif.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/slipif.c
new file mode 100644
index 0000000..c19333d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0/src/netif/slipif.c
@@ -0,0 +1,367 @@
+/**
+ * @file
+ * SLIP Interface
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is built upon the file: src/arch/rtxc/netif/sioslip.c
+ *
+ * Author: Magnus Ivarsson  
+ */
+
+/* 
+ * This is an arch independent SLIP netif. The specific serial hooks must be
+ * provided by another file. They are sio_open, sio_read/sio_tryread and sio_send
+ */
+
+#include "netif/slipif.h"
+#include "lwip/opt.h"
+
+#if LWIP_HAVE_SLIPIF
+
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+#include "lwip/sio.h"
+
+#define SLIP_BLOCK     1
+#define SLIP_DONTBLOCK 0
+
+#define SLIP_END     0300 /* 0xC0 */
+#define SLIP_ESC     0333 /* 0xDB */
+#define SLIP_ESC_END 0334 /* 0xDC */
+#define SLIP_ESC_ESC 0335 /* 0xDD */
+
+#define SLIP_MAX_SIZE 1500
+
+enum slipif_recv_state {
+    SLIP_RECV_NORMAL,
+    SLIP_RECV_ESCAPE,
+};
+
+struct slipif_priv {
+  sio_fd_t sd;
+  /* q is the whole pbuf chain for a packet, p is the current pbuf in the chain */
+  struct pbuf *p, *q;
+  enum slipif_recv_state state;
+  u16_t i, recved;
+};
+
+/**
+ * Send a pbuf doing the necessary SLIP encapsulation
+ *
+ * Uses the serial layer's sio_send()
+ *
+ * @param netif the lwip network interface structure for this slipif
+ * @param p the pbuf chaing packet to send
+ * @param ipaddr the ip address to send the packet to (not used for slipif)
+ * @return always returns ERR_OK since the serial layer does not provide return values
+ */
+err_t
+slipif_output(struct netif *netif, struct pbuf *p, ip_addr_t *ipaddr)
+{
+  struct slipif_priv *priv;
+  struct pbuf *q;
+  u16_t i;
+  u8_t c;
+
+  LWIP_ASSERT("netif != NULL", (netif != NULL));
+  LWIP_ASSERT("netif->state != NULL", (netif->state != NULL));
+  LWIP_ASSERT("p != NULL", (p != NULL));
+
+  LWIP_UNUSED_ARG(ipaddr);
+
+  priv = netif->state;
+
+  /* Send pbuf out on the serial I/O device. */
+  sio_send(SLIP_END, priv->sd);
+
+  for (q = p; q != NULL; q = q->next) {
+    for (i = 0; i < q->len; i++) {
+      c = ((u8_t *)q->payload)[i];
+      switch (c) {
+      case SLIP_END:
+        sio_send(SLIP_ESC, priv->sd);
+        sio_send(SLIP_ESC_END, priv->sd);
+        break;
+      case SLIP_ESC:
+        sio_send(SLIP_ESC, priv->sd);
+        sio_send(SLIP_ESC_ESC, priv->sd);
+        break;
+      default:
+        sio_send(c, priv->sd);
+        break;
+      }
+    }
+  }
+  sio_send(SLIP_END, priv->sd);
+  return ERR_OK;
+}
+
+/**
+ * Static function for easy use of blockig or non-blocking
+ * sio_read
+ *
+ * @param fd serial device handle
+ * @param data pointer to data buffer for receiving
+ * @param len maximum length (in bytes) of data to receive
+ * @param block if 1, call sio_read; if 0, call sio_tryread
+ * @return return value of sio_read of sio_tryread
+ */
+static u32_t
+slip_sio_read(sio_fd_t fd, u8_t* data, u32_t len, u8_t block)
+{
+  if (block) {
+    return sio_read(fd, data, len);
+  } else {
+    return sio_tryread(fd, data, len);
+  }
+}
+
+/**
+ * Handle the incoming SLIP stream character by character
+ *
+ * Poll the serial layer by calling sio_read() or sio_tryread().
+ *
+ * @param netif the lwip network interface structure for this slipif
+ * @param block if 1, block until data is received; if 0, return when all data
+ *        from the buffer is received (multiple calls to this function will
+ *        return a complete packet, NULL is returned before - used for polling)
+ * @return The IP packet when SLIP_END is received
+ */
+static struct pbuf *
+slipif_input(struct netif *netif, u8_t block)
+{
+  struct slipif_priv *priv;
+  u8_t c;
+  struct pbuf *t;
+
+  LWIP_ASSERT("netif != NULL", (netif != NULL));
+  LWIP_ASSERT("netif->state != NULL", (netif->state != NULL));
+
+  priv = netif->state;
+
+  while (slip_sio_read(priv->sd, &c, 1, block) > 0) {
+    switch (priv->state) {
+    case SLIP_RECV_NORMAL:
+      switch (c) {
+      case SLIP_END:
+        if (priv->recved > 0) {
+          /* Received whole packet. */
+          /* Trim the pbuf to the size of the received packet. */
+          pbuf_realloc(priv->q, priv->recved);
+
+          LINK_STATS_INC(link.recv);
+
+          LWIP_DEBUGF(SLIP_DEBUG, ("slipif: Got packet\n"));
+          t = priv->q;
+          priv->p = priv->q = NULL;
+          priv->i = priv->recved = 0;
+          return t;
+        }
+        continue;
+      case SLIP_ESC:
+        priv->state = SLIP_RECV_ESCAPE;
+        continue;
+      }
+      break;
+    case SLIP_RECV_ESCAPE:
+      switch (c) {
+      case SLIP_ESC_END:
+        c = SLIP_END;
+        break;
+      case SLIP_ESC_ESC:
+        c = SLIP_ESC;
+        break;
+      }
+      priv->state = SLIP_RECV_NORMAL;
+      /* FALLTHROUGH */
+    }
+
+    /* byte received, packet not yet completely received */
+    if (priv->p == NULL) {
+      /* allocate a new pbuf */
+      LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: alloc\n"));
+      priv->p = pbuf_alloc(PBUF_LINK, (PBUF_POOL_BUFSIZE - PBUF_LINK_HLEN), PBUF_POOL);
+
+      if (priv->p == NULL) {
+        LINK_STATS_INC(link.drop);
+        LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: no new pbuf! (DROP)\n"));
+        /* don't process any further since we got no pbuf to receive to */
+        break;
+      }
+
+      if (priv->q != NULL) {
+        /* 'chain' the pbuf to the existing chain */
+        pbuf_cat(priv->q, priv->p);
+      } else {
+        /* p is the first pbuf in the chain */
+        priv->q = priv->p;
+      }
+    }
+
+    /* this automatically drops bytes if > SLIP_MAX_SIZE */
+    if ((priv->p != NULL) && (priv->recved <= SLIP_MAX_SIZE)) {
+      ((u8_t *)priv->p->payload)[priv->i] = c;
+      priv->recved++;
+      priv->i++;
+      if (priv->i >= priv->p->len) {
+        /* on to the next pbuf */
+        priv->i = 0;
+        if (priv->p->next != NULL && priv->p->next->len > 0) {
+          /* p is a chain, on to the next in the chain */
+            priv->p = priv->p->next;
+        } else {
+          /* p is a single pbuf, set it to NULL so next time a new
+           * pbuf is allocated */
+            priv->p = NULL;
+        }
+      }
+    }
+  }
+
+  return NULL;
+}
+
+#if !NO_SYS
+/**
+ * The SLIP input thread.
+ *
+ * Feed the IP layer with incoming packets
+ *
+ * @param nf the lwip network interface structure for this slipif
+ */
+static void
+slipif_loop_thread(void *nf)
+{
+  struct pbuf *p;
+  struct netif *netif = (struct netif *)nf;
+
+  while (1) {
+    p = slipif_input(netif, SLIP_BLOCK);
+    if (p != NULL) {
+      if (netif->input(p, netif) != ERR_OK) {
+        pbuf_free(p);
+        p = NULL;
+      }
+    }
+  }
+}
+#endif /* !NO_SYS */
+
+/**
+ * SLIP netif initialization
+ *
+ * Call the arch specific sio_open and remember
+ * the opened device in the state field of the netif.
+ *
+ * @param netif the lwip network interface structure for this slipif
+ * @return ERR_OK if serial line could be opened,
+ *         ERR_MEM if no memory could be allocated,
+ *         ERR_IF is serial line couldn't be opened
+ *
+ * @note netif->num must contain the number of the serial port to open
+ *       (0 by default)
+ */
+err_t
+slipif_init(struct netif *netif)
+{
+  struct slipif_priv *priv;
+
+  LWIP_DEBUGF(SLIP_DEBUG, ("slipif_init: netif->num=%"U16_F"\n", (u16_t)netif->num));
+
+  /* Allocate private data */
+  priv = mem_malloc(sizeof(struct slipif_priv));
+  if (!priv) {
+    return ERR_MEM;
+  }
+
+  netif->name[0] = 's';
+  netif->name[1] = 'l';
+  netif->output = slipif_output;
+  netif->mtu = SLIP_MAX_SIZE;
+  netif->flags |= NETIF_FLAG_POINTTOPOINT;
+
+  /* Try to open the serial port (netif->num contains the port number). */
+  priv->sd = sio_open(netif->num);
+  if (!priv->sd) {
+    /* Opening the serial port failed. */
+    mem_free(priv);
+    return ERR_IF;
+  }
+
+  /* Initialize private data */
+  priv->p = NULL;
+  priv->q = NULL;
+  priv->state = SLIP_RECV_NORMAL;
+  priv->i = 0;
+  priv->recved = 0;
+
+  netif->state = priv;
+
+  /* initialize the snmp variables and counters inside the struct netif
+   * ifSpeed: no assumption can be made without knowing more about the
+   * serial line!
+   */
+  NETIF_INIT_SNMP(netif, snmp_ifType_slip, 0);
+
+  /* Create a thread to poll the serial line. */
+  sys_thread_new(SLIPIF_THREAD_NAME, slipif_loop_thread, netif,
+    SLIPIF_THREAD_STACKSIZE, SLIPIF_THREAD_PRIO);
+  return ERR_OK;
+}
+
+/**
+ * Polls the serial device and feeds the IP layer with incoming packets.
+ *
+ * @param netif The lwip network interface structure for this slipif
+ */
+void
+slipif_poll(struct netif *netif)
+{
+  struct pbuf *p;
+  struct slipif_priv *priv;
+
+  LWIP_ASSERT("netif != NULL", (netif != NULL));
+  LWIP_ASSERT("netif->state != NULL", (netif->state != NULL));
+
+  priv = netif->state;
+
+  while ((p = slipif_input(netif, SLIP_DONTBLOCK)) != NULL) {
+    if (netif->input(p, netif) != ERR_OK) {
+      pbuf_free(p);
+    }
+  }
+}
+
+#endif /* LWIP_HAVE_SLIPIF */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/README b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/README
new file mode 100644
index 0000000..909f652
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/README
@@ -0,0 +1,13 @@
+uIP is a very small implementation of the TCP/IP stack that is written
+by Adam Dunkels . More information can be obtained 
+at the uIP homepage at http://www.sics.se/~adam/uip/.
+
+This is version $Name: uip-1-0 $.
+
+The directory structure look as follows:
+
+apps/  - Example applications
+doc/   - Documentation
+lib/   - Library code used by some applications
+uip/   - uIP TCP/IP stack code
+unix/  - uIP as a user space process under FreeBSD or Linux
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/README b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/README
new file mode 100644
index 0000000..f889209
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/README
@@ -0,0 +1,2 @@
+This directory contains a few example applications. They are not all
+heavily tested, however.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/Makefile.webserver b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/Makefile.webserver
new file mode 100644
index 0000000..f38c47a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/Makefile.webserver
@@ -0,0 +1 @@
+APP_SOURCES += httpd.c http-strings.c httpd-fs.c httpd-cgi.c
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings
new file mode 100644
index 0000000..0d3c30c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings
@@ -0,0 +1,35 @@
+http_http "http://"
+http_200 "200 "
+http_301 "301 "
+http_302 "302 "
+http_get "GET "
+http_10 "HTTP/1.0"
+http_11 "HTTP/1.1"
+http_content_type "content-type: "
+http_texthtml "text/html"
+http_location "location: "
+http_host "host: "
+http_crnl "\r\n"
+http_index_html "/index.html"
+http_404_html "/404.html"
+http_referer "Referer:"
+http_header_200 "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n"
+http_header_404 "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n"
+http_content_type_plain "Content-type: text/plain\r\n\r\n"
+http_content_type_html "Content-type: text/html\r\n\r\n"
+http_content_type_css  "Content-type: text/css\r\n\r\n"
+http_content_type_text "Content-type: text/text\r\n\r\n"
+http_content_type_png  "Content-type: image/png\r\n\r\n"
+http_content_type_gif  "Content-type: image/gif\r\n\r\n"
+http_content_type_jpg  "Content-type: image/jpeg\r\n\r\n"
+http_content_type_binary "Content-type: application/octet-stream\r\n\r\n"
+http_html ".html"
+http_shtml ".shtml"
+http_htm ".htm"
+http_css ".css"
+http_png ".png"
+http_gif ".gif"
+http_jpg ".jpg"
+http_text ".txt"
+http_txt ".txt"
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings.c
new file mode 100644
index 0000000..ef7a41c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings.c
@@ -0,0 +1,102 @@
+const char http_http[8] = 
+/* "http://" */
+{0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, };
+const char http_200[5] = 
+/* "200 " */
+{0x32, 0x30, 0x30, 0x20, };
+const char http_301[5] = 
+/* "301 " */
+{0x33, 0x30, 0x31, 0x20, };
+const char http_302[5] = 
+/* "302 " */
+{0x33, 0x30, 0x32, 0x20, };
+const char http_get[5] = 
+/* "GET " */
+{0x47, 0x45, 0x54, 0x20, };
+const char http_10[9] = 
+/* "HTTP/1.0" */
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, };
+const char http_11[9] = 
+/* "HTTP/1.1" */
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, };
+const char http_content_type[15] = 
+/* "content-type: " */
+{0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, };
+const char http_texthtml[10] = 
+/* "text/html" */
+{0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, };
+const char http_location[11] = 
+/* "location: " */
+{0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, };
+const char http_host[7] = 
+/* "host: " */
+{0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, };
+const char http_crnl[3] = 
+/* "\r\n" */
+{0xd, 0xa, };
+const char http_index_html[12] = 
+/* "/index.html" */
+{0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, };
+const char http_404_html[10] = 
+/* "/404.html" */
+{0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, };
+const char http_referer[9] = 
+/* "Referer:" */
+{0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, };
+const char http_header_200[84] = 
+/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, };
+const char http_header_404[91] = 
+/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 0x30, 0x34, 0x20, 0x4e, 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, };
+const char http_content_type_plain[29] = 
+/* "Content-type: text/plain\r\n\r\n" */
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xd, 0xa, 0xd, 0xa, };
+const char http_content_type_html[28] = 
+/* "Content-type: text/html\r\n\r\n" */
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 0xd, 0xa, };
+const char http_content_type_css [27] = 
+/* "Content-type: text/css\r\n\r\n" */
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 0xd, 0xa, 0xd, 0xa, };
+const char http_content_type_text[28] = 
+/* "Content-type: text/text\r\n\r\n" */
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x74, 0x65, 0x78, 0x74, 0xd, 0xa, 0xd, 0xa, };
+const char http_content_type_png [28] = 
+/* "Content-type: image/png\r\n\r\n" */
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x70, 0x6e, 0x67, 0xd, 0xa, 0xd, 0xa, };
+const char http_content_type_gif [28] = 
+/* "Content-type: image/gif\r\n\r\n" */
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0xd, 0xa, 0xd, 0xa, };
+const char http_content_type_jpg [29] = 
+/* "Content-type: image/jpeg\r\n\r\n" */
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x6a, 0x70, 0x65, 0x67, 0xd, 0xa, 0xd, 0xa, };
+const char http_content_type_binary[43] = 
+/* "Content-type: application/octet-stream\r\n\r\n" */
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x6f, 0x63, 0x74, 0x65, 0x74, 0x2d, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d, 0xd, 0xa, 0xd, 0xa, };
+const char http_html[6] = 
+/* ".html" */
+{0x2e, 0x68, 0x74, 0x6d, 0x6c, };
+const char http_shtml[7] = 
+/* ".shtml" */
+{0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, };
+const char http_htm[5] = 
+/* ".htm" */
+{0x2e, 0x68, 0x74, 0x6d, };
+const char http_css[5] = 
+/* ".css" */
+{0x2e, 0x63, 0x73, 0x73, };
+const char http_png[5] = 
+/* ".png" */
+{0x2e, 0x70, 0x6e, 0x67, };
+const char http_gif[5] = 
+/* ".gif" */
+{0x2e, 0x67, 0x69, 0x66, };
+const char http_jpg[5] = 
+/* ".jpg" */
+{0x2e, 0x6a, 0x70, 0x67, };
+const char http_text[5] = 
+/* ".txt" */
+{0x2e, 0x74, 0x78, 0x74, };
+const char http_txt[5] = 
+/* ".txt" */
+{0x2e, 0x74, 0x78, 0x74, };
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings.h
new file mode 100644
index 0000000..acbe7e1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings.h
@@ -0,0 +1,34 @@
+extern const char http_http[8];
+extern const char http_200[5];
+extern const char http_301[5];
+extern const char http_302[5];
+extern const char http_get[5];
+extern const char http_10[9];
+extern const char http_11[9];
+extern const char http_content_type[15];
+extern const char http_texthtml[10];
+extern const char http_location[11];
+extern const char http_host[7];
+extern const char http_crnl[3];
+extern const char http_index_html[12];
+extern const char http_404_html[10];
+extern const char http_referer[9];
+extern const char http_header_200[84];
+extern const char http_header_404[91];
+extern const char http_content_type_plain[29];
+extern const char http_content_type_html[28];
+extern const char http_content_type_css [27];
+extern const char http_content_type_text[28];
+extern const char http_content_type_png [28];
+extern const char http_content_type_gif [28];
+extern const char http_content_type_jpg [29];
+extern const char http_content_type_binary[43];
+extern const char http_html[6];
+extern const char http_shtml[7];
+extern const char http_htm[5];
+extern const char http_css[5];
+extern const char http_png[5];
+extern const char http_gif[5];
+extern const char http_jpg[5];
+extern const char http_text[5];
+extern const char http_txt[5];
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-cgi.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-cgi.c
new file mode 100644
index 0000000..f845c7a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-cgi.c
@@ -0,0 +1,203 @@
+/**
+ * \addtogroup httpd
+ * @{
+ */
+
+/**
+ * \file
+ *         Web server script interface
+ * \author
+ *         Adam Dunkels 
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2006, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $
+ *
+ */
+
+#include "uip.h"
+#include "psock.h"
+#include "httpd.h"
+#include "httpd-cgi.h"
+#include "httpd-fs.h"
+
+#include 
+#include 
+
+HTTPD_CGI_CALL(file, "file-stats", file_stats);
+HTTPD_CGI_CALL(tcp, "tcp-connections", tcp_stats);
+HTTPD_CGI_CALL(net, "net-stats", net_stats);
+
+static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, NULL };
+
+/*---------------------------------------------------------------------------*/
+static
+PT_THREAD(nullfunction(struct httpd_state *s, char *ptr))
+{
+  PSOCK_BEGIN(&s->sout);
+  PSOCK_END(&s->sout);
+}
+/*---------------------------------------------------------------------------*/
+httpd_cgifunction
+httpd_cgi(char *name)
+{
+  const struct httpd_cgi_call **f;
+
+  /* Find the matching name in the table, return the function. */
+  for(f = calls; *f != NULL; ++f) {
+    if(strncmp((*f)->name, name, strlen((*f)->name)) == 0) {
+      return (*f)->function;
+    }
+  }
+  return nullfunction;
+}
+/*---------------------------------------------------------------------------*/
+static unsigned short
+generate_file_stats(void *arg)
+{
+  char *f = (char *)arg;
+  return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f));
+}
+/*---------------------------------------------------------------------------*/
+static
+PT_THREAD(file_stats(struct httpd_state *s, char *ptr))
+{
+  PSOCK_BEGIN(&s->sout);
+
+  PSOCK_GENERATOR_SEND(&s->sout, generate_file_stats, strchr(ptr, ' ') + 1);
+  
+  PSOCK_END(&s->sout);
+}
+/*---------------------------------------------------------------------------*/
+static const char closed[] =   /*  "CLOSED",*/
+{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0};
+static const char syn_rcvd[] = /*  "SYN-RCVD",*/
+{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56,
+ 0x44,  0};
+static const char syn_sent[] = /*  "SYN-SENT",*/
+{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e,
+ 0x54,  0};
+static const char established[] = /*  "ESTABLISHED",*/
+{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48,
+ 0x45, 0x44, 0};
+static const char fin_wait_1[] = /*  "FIN-WAIT-1",*/
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,
+ 0x54, 0x2d, 0x31, 0};
+static const char fin_wait_2[] = /*  "FIN-WAIT-2",*/
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,
+ 0x54, 0x2d, 0x32, 0};
+static const char closing[] = /*  "CLOSING",*/
+{0x43, 0x4c, 0x4f, 0x53, 0x49,
+ 0x4e, 0x47, 0};
+static const char time_wait[] = /*  "TIME-WAIT,"*/
+{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41,
+ 0x49, 0x54, 0};
+static const char last_ack[] = /*  "LAST-ACK"*/
+{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43,
+ 0x4b, 0};
+
+static const char *states[] = {
+  closed,
+  syn_rcvd,
+  syn_sent,
+  established,
+  fin_wait_1,
+  fin_wait_2,
+  closing,
+  time_wait,
+  last_ack};
+  
+
+static unsigned short
+generate_tcp_stats(void *arg)
+{
+  struct uip_conn *conn;
+  struct httpd_state *s = (struct httpd_state *)arg;
+    
+  conn = &uip_conns[s->count];
+  return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE,
+		 "%d%u.%u.%u.%u:%u%s%u%u%c %c\r\n",
+		 htons(conn->lport),
+		 htons(conn->ripaddr[0]) >> 8,
+		 htons(conn->ripaddr[0]) & 0xff,
+		 htons(conn->ripaddr[1]) >> 8,
+		 htons(conn->ripaddr[1]) & 0xff,
+		 htons(conn->rport),
+		 states[conn->tcpstateflags & UIP_TS_MASK],
+		 conn->nrtx,
+		 conn->timer,
+		 (uip_outstanding(conn))? '*':' ',
+		 (uip_stopped(conn))? '!':' ');
+}
+/*---------------------------------------------------------------------------*/
+static
+PT_THREAD(tcp_stats(struct httpd_state *s, char *ptr))
+{
+  
+  PSOCK_BEGIN(&s->sout);
+
+  for(s->count = 0; s->count < UIP_CONNS; ++s->count) {
+    if((uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED) {
+      PSOCK_GENERATOR_SEND(&s->sout, generate_tcp_stats, s);
+    }
+  }
+
+  PSOCK_END(&s->sout);
+}
+/*---------------------------------------------------------------------------*/
+static unsigned short
+generate_net_stats(void *arg)
+{
+  struct httpd_state *s = (struct httpd_state *)arg;
+  return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE,
+		  "%5u\n", ((uip_stats_t *)&uip_stat)[s->count]);
+}
+
+static
+PT_THREAD(net_stats(struct httpd_state *s, char *ptr))
+{
+  PSOCK_BEGIN(&s->sout);
+
+#if UIP_STATISTICS
+
+  for(s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t);
+      ++s->count) {
+    PSOCK_GENERATOR_SEND(&s->sout, generate_net_stats, s);
+  }
+  
+#endif /* UIP_STATISTICS */
+  
+  PSOCK_END(&s->sout);
+}
+/*---------------------------------------------------------------------------*/
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-cgi.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-cgi.h
new file mode 100644
index 0000000..7ae9283
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-cgi.h
@@ -0,0 +1,84 @@
+/**
+ * \addtogroup httpd
+ * @{
+ */
+
+/**
+ * \file
+ *         Web server script interface header file
+ * \author
+ *         Adam Dunkels 
+ *
+ */
+
+
+
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $
+ *
+ */
+
+#ifndef __HTTPD_CGI_H__
+#define __HTTPD_CGI_H__
+
+#include "psock.h"
+#include "httpd.h"
+
+typedef PT_THREAD((* httpd_cgifunction)(struct httpd_state *, char *));
+
+httpd_cgifunction httpd_cgi(char *name);
+
+struct httpd_cgi_call {
+  const char *name;
+  const httpd_cgifunction function;
+};
+
+/**
+ * \brief      HTTPD CGI function declaration
+ * \param name The C variable name of the function
+ * \param str  The string name of the function, used in the script file
+ * \param function A pointer to the function that implements it
+ *
+ *             This macro is used for declaring a HTTPD CGI
+ *             function. This function is then added to the list of
+ *             HTTPD CGI functions with the httpd_cgi_add() function.
+ *
+ * \hideinitializer
+ */
+#define HTTPD_CGI_CALL(name, str, function) \
+static PT_THREAD(function(struct httpd_state *, char *)); \
+static const struct httpd_cgi_call name = {str, function}
+
+void httpd_cgi_init(void);
+#endif /* __HTTPD_CGI_H__ */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs.c
new file mode 100644
index 0000000..dc4aef0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $
+ */
+
+#include "httpd.h"
+#include "httpd-fs.h"
+#include "httpd-fsdata.h"
+
+#ifndef NULL
+#define NULL 0
+#endif /* NULL */
+
+#include "httpd-fsdata.c"
+
+#if HTTPD_FS_STATISTICS
+static u16_t count[HTTPD_FS_NUMFILES];
+#endif /* HTTPD_FS_STATISTICS */
+
+/*-----------------------------------------------------------------------------------*/
+static u8_t
+httpd_fs_strcmp(const char *str1, const char *str2)
+{
+  u8_t i;
+  i = 0;
+ loop:
+
+  if(str2[i] == 0 ||
+     str1[i] == '\r' ||
+     str1[i] == '\n') {
+    return 0;
+  }
+
+  if(str1[i] != str2[i]) {
+    return 1;
+  }
+
+
+  ++i;
+  goto loop;
+}
+/*-----------------------------------------------------------------------------------*/
+int
+httpd_fs_open(const char *name, struct httpd_fs_file *file)
+{
+#if HTTPD_FS_STATISTICS
+  u16_t i = 0;
+#endif /* HTTPD_FS_STATISTICS */
+  struct httpd_fsdata_file_noconst *f;
+
+  for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT;
+      f != NULL;
+      f = (struct httpd_fsdata_file_noconst *)f->next) {
+
+    if(httpd_fs_strcmp(name, f->name) == 0) {
+      file->data = f->data;
+      file->len = f->len;
+#if HTTPD_FS_STATISTICS
+      ++count[i];
+#endif /* HTTPD_FS_STATISTICS */
+      return 1;
+    }
+#if HTTPD_FS_STATISTICS
+    ++i;
+#endif /* HTTPD_FS_STATISTICS */
+
+  }
+  return 0;
+}
+/*-----------------------------------------------------------------------------------*/
+void
+httpd_fs_init(void)
+{
+#if HTTPD_FS_STATISTICS
+  u16_t i;
+  for(i = 0; i < HTTPD_FS_NUMFILES; i++) {
+    count[i] = 0;
+  }
+#endif /* HTTPD_FS_STATISTICS */
+}
+/*-----------------------------------------------------------------------------------*/
+#if HTTPD_FS_STATISTICS
+u16_t httpd_fs_count
+(char *name)
+{
+  struct httpd_fsdata_file_noconst *f;
+  u16_t i;
+
+  i = 0;
+  for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT;
+      f != NULL;
+      f = (struct httpd_fsdata_file_noconst *)f->next) {
+
+    if(httpd_fs_strcmp(name, f->name) == 0) {
+      return count[i];
+    }
+    ++i;
+  }
+  return 0;
+}
+#endif /* HTTPD_FS_STATISTICS */
+/*-----------------------------------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs.h
new file mode 100644
index 0000000..b594eea
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $
+ */
+#ifndef __HTTPD_FS_H__
+#define __HTTPD_FS_H__
+
+#define HTTPD_FS_STATISTICS 1
+
+struct httpd_fs_file {
+  char *data;
+  int len;
+};
+
+/* file must be allocated by caller and will be filled in
+   by the function. */
+int httpd_fs_open(const char *name, struct httpd_fs_file *file);
+
+#ifdef HTTPD_FS_STATISTICS
+#if HTTPD_FS_STATISTICS == 1
+u16_t httpd_fs_count(char *name);
+#endif /* HTTPD_FS_STATISTICS */
+#endif /* HTTPD_FS_STATISTICS */
+
+void httpd_fs_init(void);
+
+#endif /* __HTTPD_FS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/404.html b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/404.html
new file mode 100644
index 0000000..43e7f4c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/404.html
@@ -0,0 +1,8 @@
+
+  
+    

+      
404 - file not found

+      
Go here instead.

+    

+  
+
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/fade.png b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/fade.png
new file mode 100644
index 0000000..a9e69f7
Binary files /dev/null and b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/fade.png differ
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/files.shtml b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/files.shtml
new file mode 100644
index 0000000..361cc1d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/files.shtml
@@ -0,0 +1,35 @@
+%!: /header.html
+
File statistics

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
/index.html%! file-stats /index.html
+ 
/files.shtml%! file-stats /files.shtml
+ 
/tcp.shtml%! file-stats /tcp.shtml
+ 
/stats.shtml%! file-stats /stats.shtml
+ 
/style.css%! file-stats /style.css
+ 
/404.html%! file-stats /404.html
+ 
/fade.png%! file-stats /fade.png
+ 

+

+%!: /footer.html
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/footer.html b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/footer.html
new file mode 100644
index 0000000..290832d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/footer.html
@@ -0,0 +1,2 @@
+  
+
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/header.html b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/header.html
new file mode 100644
index 0000000..0c3c4ef
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/header.html
@@ -0,0 +1,18 @@
+
+
+  
+    Welcome to the uIP web server!
+      
+  
+  
+
+  

+  
Front page

+  
File statistics

+  
Network statistics

+  
Network
+  connections

+  

+  

+  
+  

diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/index.html b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/index.html
new file mode 100644
index 0000000..7af64c8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/index.html
@@ -0,0 +1,29 @@
+
+
+  
+    Welcome to the uIP web server!
+      
+  
+  
+
+  

+  
Front page

+  
File statistics

+  
Network statistics

+  
Network
+  connections

+  

+  

+
+  

+  

+  These web pages are served by a small web server running on top of
+  the uIP embedded TCP/IP
+  stack.
+  

+  

+  Click on the links above for web server statistics.
+  

+
+  
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/processes.shtml b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/processes.shtml
new file mode 100644
index 0000000..be857f9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/processes.shtml
@@ -0,0 +1,5 @@
+%!: /header.html
+
System processes


+
+%! processes
+%!: /footer.html
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/stats.shtml b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/stats.shtml
new file mode 100644
index 0000000..7eb381a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/stats.shtml
@@ -0,0 +1,31 @@
+%!: /header.html
+
Network statistics

+

+
IDNamePriorityPoll handlerEvent handlerProcstate

+
+IP           Packets received
+             Packets sent
+	     Packets dropped
+IP errors    IP version/header length
+             IP length, high byte
+             IP length, low byte
+             IP fragments
+             Header checksum
+             Wrong protocol
+ICMP	     Packets received
+             Packets sent
+             Packets dropped
+             Type errors
+TCP          Packets received
+             Packets sent
+             Packets dropped
+             Checksum errors
+             Data packets without ACKs
+             Resets
+             Retransmissions
+	     No connection avaliable
+	     Connection attempts to closed ports
+
%! net-stats
+

+
+%!: /footer.html
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/style.css b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/style.css
new file mode 100644
index 0000000..089fe84
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/style.css
@@ -0,0 +1,92 @@
+h1 
+{
+  text-align: center;
+  font-size:14pt;
+  font-family:arial,helvetica;
+  font-weight:bold;
+  padding:10px; 
+}
+
+body
+{
+
+  background-color: #fffeec;
+  color:black;
+
+  font-size:8pt;
+  font-family:arial,helvetica;
+}
+
+.menu
+{
+  margin: 4px;
+  width:60%;
+
+  padding:2px;
+	
+  border: solid 1px;
+  background-color: #fffcd2;
+  text-align:left;
+  
+  font-size:9pt;
+  font-family:arial,helvetica;  
+}
+
+div.menubox
+{
+  width: 25%;
+  border: 0;
+  float: left;
+text-align: center;
+}
+
+.contentblock
+{  
+  margin: 4px;
+  width:60%;
+
+  padding:2px;
+
+  border: 1px dotted;
+  background-color: white;
+
+  font-size:8pt;
+  font-family:arial,helvetica;  
+
+}
+
+p.intro
+{
+  margin-left:20px;
+  margin-right:20px;
+
+  font-size:10pt;
+/*  font-weight:bold; */
+  font-family:arial,helvetica;  
+}
+
+p.clink
+{
+  font-size:12pt;
+  font-family:courier,monospace;  
+  text-align:center;
+}
+
+p.clink9
+{
+  font-size:9pt;
+  font-family:courier,monospace;  
+  text-align:center;
+}
+
+
+p
+{
+  padding-left:10px;
+}
+
+p.right
+{
+  text-align:right; 
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/tcp.shtml b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/tcp.shtml
new file mode 100644
index 0000000..2404aed
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/tcp.shtml
@@ -0,0 +1,5 @@
+%!: /header.html
+
Current connections


+
+%! tcp-connections
+%!: /footer.html
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fsdata.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fsdata.c
new file mode 100644
index 0000000..29e5a1b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fsdata.c
@@ -0,0 +1,607 @@
+static const unsigned char data_processes_shtml[] = {
+	/* /processes.shtml */
+	0x2f, 0x70, 0x72, 0x6f, 0x63, 0x65, 0x73, 0x73, 0x65, 0x73, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0,
+	0x25, 0x21, 0x3a, 0x20, 0x2f, 0x68, 0x65, 0x61, 0x64, 0x65, 
+	0x72, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0xa, 0x3c, 0x68, 0x31, 
+	0x3e, 0x53, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x20, 0x70, 0x72, 
+	0x6f, 0x63, 0x65, 0x73, 0x73, 0x65, 0x73, 0x3c, 0x2f, 0x68, 
+	0x31, 0x3e, 0x3c, 0x62, 0x72, 0x3e, 0x3c, 0x74, 0x61, 0x62, 
+	0x6c, 0x65, 0x20, 0x77, 0x69, 0x64, 0x74, 0x68, 0x3d, 0x22, 
+	0x31, 0x30, 0x30, 0x25, 0x22, 0x3e, 0xa, 0x3c, 0x74, 0x72, 
+	0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x49, 0x44, 0x3c, 0x2f, 0x74, 
+	0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x4e, 0x61, 0x6d, 0x65, 
+	0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x50, 
+	0x72, 0x69, 0x6f, 0x72, 0x69, 0x74, 0x79, 0x3c, 0x2f, 0x74, 
+	0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x50, 0x6f, 0x6c, 0x6c, 
+	0x20, 0x68, 0x61, 0x6e, 0x64, 0x6c, 0x65, 0x72, 0x3c, 0x2f, 
+	0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x45, 0x76, 0x65, 
+	0x6e, 0x74, 0x20, 0x68, 0x61, 0x6e, 0x64, 0x6c, 0x65, 0x72, 
+	0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x50, 
+	0x72, 0x6f, 0x63, 0x73, 0x74, 0x61, 0x74, 0x65, 0x3c, 0x2f, 
+	0x74, 0x68, 0x3e, 0x3c, 0x2f, 0x74, 0x72, 0x3e, 0xa, 0x25, 
+	0x21, 0x20, 0x70, 0x72, 0x6f, 0x63, 0x65, 0x73, 0x73, 0x65, 
+	0x73, 0xa, 0x25, 0x21, 0x3a, 0x20, 0x2f, 0x66, 0x6f, 0x6f, 
+	0x74, 0x65, 0x72, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0};
+
+static const unsigned char data_404_html[] = {
+	/* /404.html */
+	0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0,
+	0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xa, 0x20, 0x20, 0x3c, 
+	0x62, 0x6f, 0x64, 0x79, 0x20, 0x62, 0x67, 0x63, 0x6f, 0x6c, 
+	0x6f, 0x72, 0x3d, 0x22, 0x77, 0x68, 0x69, 0x74, 0x65, 0x22, 
+	0x3e, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x63, 0x65, 0x6e, 
+	0x74, 0x65, 0x72, 0x3e, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 
+	0x20, 0x3c, 0x68, 0x31, 0x3e, 0x34, 0x30, 0x34, 0x20, 0x2d, 
+	0x20, 0x66, 0x69, 0x6c, 0x65, 0x20, 0x6e, 0x6f, 0x74, 0x20, 
+	0x66, 0x6f, 0x75, 0x6e, 0x64, 0x3c, 0x2f, 0x68, 0x31, 0x3e, 
+	0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x68, 0x33, 
+	0x3e, 0x47, 0x6f, 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 
+	0x66, 0x3d, 0x22, 0x2f, 0x22, 0x3e, 0x68, 0x65, 0x72, 0x65, 
+	0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x69, 0x6e, 0x73, 0x74, 0x65, 
+	0x61, 0x64, 0x2e, 0x3c, 0x2f, 0x68, 0x33, 0x3e, 0xa, 0x20, 
+	0x20, 0x20, 0x20, 0x3c, 0x2f, 0x63, 0x65, 0x6e, 0x74, 0x65, 
+	0x72, 0x3e, 0xa, 0x20, 0x20, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 
+	0x79, 0x3e, 0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 
+0};
+
+static const unsigned char data_files_shtml[] = {
+	/* /files.shtml */
+	0x2f, 0x66, 0x69, 0x6c, 0x65, 0x73, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0,
+	0x25, 0x21, 0x3a, 0x20, 0x2f, 0x68, 0x65, 0x61, 0x64, 0x65, 
+	0x72, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0xa, 0x3c, 0x68, 0x31, 
+	0x3e, 0x46, 0x69, 0x6c, 0x65, 0x20, 0x73, 0x74, 0x61, 0x74, 
+	0x69, 0x73, 0x74, 0x69, 0x63, 0x73, 0x3c, 0x2f, 0x68, 0x31, 
+	0x3e, 0xa, 0x3c, 0x63, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, 
+	0xa, 0x3c, 0x74, 0x61, 0x62, 0x6c, 0x65, 0x20, 0x77, 0x69, 
+	0x64, 0x74, 0x68, 0x3d, 0x22, 0x33, 0x30, 0x30, 0x22, 0x3e, 
+	0xa, 0x3c, 0x74, 0x72, 0x3e, 0x3c, 0x74, 0x64, 0x3e, 0x3c, 
+	0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x2f, 0x69, 
+	0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0x22, 
+	0x3e, 0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 
+	0x6d, 0x6c, 0x3c, 0x2f, 0x61, 0x3e, 0x3c, 0x2f, 0x74, 0x64, 
+	0x3e, 0xa, 0x3c, 0x74, 0x64, 0x3e, 0x25, 0x21, 0x20, 0x66, 
+	0x69, 0x6c, 0x65, 0x2d, 0x73, 0x74, 0x61, 0x74, 0x73, 0x20, 
+	0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 
+	0x6c, 0xa, 0x3c, 0x2f, 0x74, 0x64, 0x3e, 0x3c, 0x74, 0x64, 
+	0x3e, 0x3c, 0x69, 0x6d, 0x67, 0x20, 0x73, 0x72, 0x63, 0x3d, 
+	0x22, 0x2f, 0x66, 0x61, 0x64, 0x65, 0x2e, 0x70, 0x6e, 0x67, 
+	0x22, 0x20, 0x68, 0x65, 0x69, 0x67, 0x68, 0x74, 0x3d, 0x31, 
+	0x30, 0x20, 0x77, 0x69, 0x64, 0x74, 0x68, 0x3d, 0x25, 0x21, 
+	0x20, 0x66, 0x69, 0x6c, 0x65, 0x2d, 0x73, 0x74, 0x61, 0x74, 
+	0x73, 0x20, 0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 
+	0x74, 0x6d, 0x6c, 0xa, 0x3e, 0x20, 0x3c, 0x2f, 0x74, 0x64, 
+	0x3e, 0x3c, 0x2f, 0x74, 0x72, 0x3e, 0xa, 0x3c, 0x74, 0x72, 
+	0x3e, 0x3c, 0x74, 0x64, 0x3e, 0x3c, 0x61, 0x20, 0x68, 0x72, 
+	0x65, 0x66, 0x3d, 0x22, 0x2f, 0x66, 0x69, 0x6c, 0x65, 0x73, 
+	0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x2f, 0x66, 
+	0x69, 0x6c, 0x65, 0x73, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 
+	0x3c, 0x2f, 0x61, 0x3e, 0x3c, 0x2f, 0x74, 0x64, 0x3e, 0xa, 
+	0x3c, 0x74, 0x64, 0x3e, 0x25, 0x21, 0x20, 0x66, 0x69, 0x6c, 
+	0x65, 0x2d, 0x73, 0x74, 0x61, 0x74, 0x73, 0x20, 0x2f, 0x66, 
+	0x69, 0x6c, 0x65, 0x73, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 
+	0xa, 0x3c, 0x2f, 0x74, 0x64, 0x3e, 0x3c, 0x74, 0x64, 0x3e, 
+	0x3c, 0x69, 0x6d, 0x67, 0x20, 0x73, 0x72, 0x63, 0x3d, 0x22, 
+	0x2f, 0x66, 0x61, 0x64, 0x65, 0x2e, 0x70, 0x6e, 0x67, 0x22, 
+	0x20, 0x68, 0x65, 0x69, 0x67, 0x68, 0x74, 0x3d, 0x31, 0x30, 
+	0x20, 0x77, 0x69, 0x64, 0x74, 0x68, 0x3d, 0x25, 0x21, 0x20, 
+	0x66, 0x69, 0x6c, 0x65, 0x2d, 0x73, 0x74, 0x61, 0x74, 0x73, 
+	0x20, 0x2f, 0x66, 0x69, 0x6c, 0x65, 0x73, 0x2e, 0x73, 0x68, 
+	0x74, 0x6d, 0x6c, 0xa, 0x3e, 0x20, 0x3c, 0x2f, 0x74, 0x64, 
+	0x3e, 0x3c, 0x2f, 0x74, 0x72, 0x3e, 0xa, 0x3c, 0x74, 0x72, 
+	0x3e, 0x3c, 0x74, 0x64, 0x3e, 0x3c, 0x61, 0x20, 0x68, 0x72, 
+	0x65, 0x66, 0x3d, 0x22, 0x2f, 0x74, 0x63, 0x70, 0x2e, 0x73, 
+	0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x2f, 0x74, 0x63, 0x70, 
+	0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x3c, 0x2f, 0x61, 0x3e, 
+	0x3c, 0x2f, 0x74, 0x64, 0x3e, 0xa, 0x3c, 0x74, 0x64, 0x3e, 
+	0x25, 0x21, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x2d, 0x73, 0x74, 
+	0x61, 0x74, 0x73, 0x20, 0x2f, 0x74, 0x63, 0x70, 0x2e, 0x73, 
+	0x68, 0x74, 0x6d, 0x6c, 0xa, 0x3c, 0x2f, 0x74, 0x64, 0x3e, 
+	0x3c, 0x74, 0x64, 0x3e, 0x3c, 0x69, 0x6d, 0x67, 0x20, 0x73, 
+	0x72, 0x63, 0x3d, 0x22, 0x2f, 0x66, 0x61, 0x64, 0x65, 0x2e, 
+	0x70, 0x6e, 0x67, 0x22, 0x20, 0x68, 0x65, 0x69, 0x67, 0x68, 
+	0x74, 0x3d, 0x31, 0x30, 0x20, 0x77, 0x69, 0x64, 0x74, 0x68, 
+	0x3d, 0x25, 0x21, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x2d, 0x73, 
+	0x74, 0x61, 0x74, 0x73, 0x20, 0x2f, 0x74, 0x63, 0x70, 0x2e, 
+	0x73, 0x68, 0x74, 0x6d, 0x6c, 0xa, 0x3e, 0x20, 0x3c, 0x2f, 
+	0x74, 0x64, 0x3e, 0x3c, 0x2f, 0x74, 0x72, 0x3e, 0xa, 0x3c, 
+	0x74, 0x72, 0x3e, 0x3c, 0x74, 0x64, 0x3e, 0x3c, 0x61, 0x20, 
+	0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x2f, 0x73, 0x74, 0x61, 
+	0x74, 0x73, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 
+	0x2f, 0x73, 0x74, 0x61, 0x74, 0x73, 0x2e, 0x73, 0x68, 0x74, 
+	0x6d, 0x6c, 0x3c, 0x2f, 0x61, 0x3e, 0x3c, 0x2f, 0x74, 0x64, 
+	0x3e, 0xa, 0x3c, 0x74, 0x64, 0x3e, 0x25, 0x21, 0x20, 0x66, 
+	0x69, 0x6c, 0x65, 0x2d, 0x73, 0x74, 0x61, 0x74, 0x73, 0x20, 
+	0x2f, 0x73, 0x74, 0x61, 0x74, 0x73, 0x2e, 0x73, 0x68, 0x74, 
+	0x6d, 0x6c, 0xa, 0x3c, 0x2f, 0x74, 0x64, 0x3e, 0x3c, 0x74, 
+	0x64, 0x3e, 0x3c, 0x69, 0x6d, 0x67, 0x20, 0x73, 0x72, 0x63, 
+	0x3d, 0x22, 0x2f, 0x66, 0x61, 0x64, 0x65, 0x2e, 0x70, 0x6e, 
+	0x67, 0x22, 0x20, 0x68, 0x65, 0x69, 0x67, 0x68, 0x74, 0x3d, 
+	0x31, 0x30, 0x20, 0x77, 0x69, 0x64, 0x74, 0x68, 0x3d, 0x25, 
+	0x21, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x2d, 0x73, 0x74, 0x61, 
+	0x74, 0x73, 0x20, 0x2f, 0x73, 0x74, 0x61, 0x74, 0x73, 0x2e, 
+	0x73, 0x68, 0x74, 0x6d, 0x6c, 0xa, 0x3e, 0x20, 0x3c, 0x2f, 
+	0x74, 0x64, 0x3e, 0x3c, 0x2f, 0x74, 0x72, 0x3e, 0xa, 0x3c, 
+	0x74, 0x72, 0x3e, 0x3c, 0x74, 0x64, 0x3e, 0x3c, 0x61, 0x20, 
+	0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x2f, 0x73, 0x74, 0x79, 
+	0x6c, 0x65, 0x2e, 0x63, 0x73, 0x73, 0x22, 0x3e, 0x2f, 0x73, 
+	0x74, 0x79, 0x6c, 0x65, 0x2e, 0x63, 0x73, 0x73, 0x3c, 0x2f, 
+	0x61, 0x3e, 0x3c, 0x2f, 0x74, 0x64, 0x3e, 0xa, 0x3c, 0x74, 
+	0x64, 0x3e, 0x25, 0x21, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x2d, 
+	0x73, 0x74, 0x61, 0x74, 0x73, 0x20, 0x2f, 0x73, 0x74, 0x79, 
+	0x6c, 0x65, 0x2e, 0x63, 0x73, 0x73, 0xa, 0x3c, 0x2f, 0x74, 
+	0x64, 0x3e, 0x3c, 0x74, 0x64, 0x3e, 0x3c, 0x69, 0x6d, 0x67, 
+	0x20, 0x73, 0x72, 0x63, 0x3d, 0x22, 0x2f, 0x66, 0x61, 0x64, 
+	0x65, 0x2e, 0x70, 0x6e, 0x67, 0x22, 0x20, 0x68, 0x65, 0x69, 
+	0x67, 0x68, 0x74, 0x3d, 0x31, 0x30, 0x20, 0x77, 0x69, 0x64, 
+	0x74, 0x68, 0x3d, 0x25, 0x21, 0x20, 0x66, 0x69, 0x6c, 0x65, 
+	0x2d, 0x73, 0x74, 0x61, 0x74, 0x73, 0x20, 0x2f, 0x73, 0x74, 
+	0x79, 0x6c, 0x65, 0x2e, 0x63, 0x73, 0x73, 0xa, 0x3e, 0x20, 
+	0x3c, 0x2f, 0x74, 0x64, 0x3e, 0x3c, 0x2f, 0x74, 0x72, 0x3e, 
+	0xa, 0x3c, 0x74, 0x72, 0x3e, 0x3c, 0x74, 0x64, 0x3e, 0x3c, 
+	0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x2f, 0x34, 
+	0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x2f, 
+	0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0x3c, 0x2f, 
+	0x61, 0x3e, 0x3c, 0x2f, 0x74, 0x64, 0x3e, 0xa, 0x3c, 0x74, 
+	0x64, 0x3e, 0x25, 0x21, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x2d, 
+	0x73, 0x74, 0x61, 0x74, 0x73, 0x20, 0x2f, 0x34, 0x30, 0x34, 
+	0x2e, 0x68, 0x74, 0x6d, 0x6c, 0xa, 0x3c, 0x2f, 0x74, 0x64, 
+	0x3e, 0x3c, 0x74, 0x64, 0x3e, 0x3c, 0x69, 0x6d, 0x67, 0x20, 
+	0x73, 0x72, 0x63, 0x3d, 0x22, 0x2f, 0x66, 0x61, 0x64, 0x65, 
+	0x2e, 0x70, 0x6e, 0x67, 0x22, 0x20, 0x68, 0x65, 0x69, 0x67, 
+	0x68, 0x74, 0x3d, 0x31, 0x30, 0x20, 0x77, 0x69, 0x64, 0x74, 
+	0x68, 0x3d, 0x25, 0x21, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x2d, 
+	0x73, 0x74, 0x61, 0x74, 0x73, 0x20, 0x2f, 0x34, 0x30, 0x34, 
+	0x2e, 0x68, 0x74, 0x6d, 0x6c, 0xa, 0x3e, 0x20, 0x3c, 0x2f, 
+	0x74, 0x64, 0x3e, 0x3c, 0x2f, 0x74, 0x72, 0x3e, 0xa, 0x3c, 
+	0x74, 0x72, 0x3e, 0x3c, 0x74, 0x64, 0x3e, 0x3c, 0x61, 0x20, 
+	0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x2f, 0x66, 0x61, 0x64, 
+	0x65, 0x2e, 0x70, 0x6e, 0x67, 0x22, 0x3e, 0x2f, 0x66, 0x61, 
+	0x64, 0x65, 0x2e, 0x70, 0x6e, 0x67, 0x3c, 0x2f, 0x61, 0x3e, 
+	0x3c, 0x2f, 0x74, 0x64, 0x3e, 0xa, 0x3c, 0x74, 0x64, 0x3e, 
+	0x25, 0x21, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x2d, 0x73, 0x74, 
+	0x61, 0x74, 0x73, 0x20, 0x2f, 0x66, 0x61, 0x64, 0x65, 0x2e, 
+	0x70, 0x6e, 0x67, 0xa, 0x3c, 0x2f, 0x74, 0x64, 0x3e, 0x3c, 
+	0x74, 0x64, 0x3e, 0x3c, 0x69, 0x6d, 0x67, 0x20, 0x73, 0x72, 
+	0x63, 0x3d, 0x22, 0x2f, 0x66, 0x61, 0x64, 0x65, 0x2e, 0x70, 
+	0x6e, 0x67, 0x22, 0x20, 0x68, 0x65, 0x69, 0x67, 0x68, 0x74, 
+	0x3d, 0x31, 0x30, 0x20, 0x77, 0x69, 0x64, 0x74, 0x68, 0x3d, 
+	0x25, 0x21, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x2d, 0x73, 0x74, 
+	0x61, 0x74, 0x73, 0x20, 0x2f, 0x66, 0x61, 0x64, 0x65, 0x2e, 
+	0x70, 0x6e, 0x67, 0xa, 0x3e, 0x20, 0x3c, 0x2f, 0x74, 0x64, 
+	0x3e, 0x3c, 0x2f, 0x74, 0x72, 0x3e, 0xa, 0x3c, 0x2f, 0x74, 
+	0x61, 0x62, 0x6c, 0x65, 0x3e, 0xa, 0x3c, 0x2f, 0x63, 0x65, 
+	0x6e, 0x74, 0x65, 0x72, 0x3e, 0xa, 0x25, 0x21, 0x3a, 0x20, 
+	0x2f, 0x66, 0x6f, 0x6f, 0x74, 0x65, 0x72, 0x2e, 0x68, 0x74, 
+	0x6d, 0x6c, 0xa, 0};
+
+static const unsigned char data_footer_html[] = {
+	/* /footer.html */
+	0x2f, 0x66, 0x6f, 0x6f, 0x74, 0x65, 0x72, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0,
+	0x20, 0x20, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xa, 
+	0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0};
+
+static const unsigned char data_header_html[] = {
+	/* /header.html */
+	0x2f, 0x68, 0x65, 0x61, 0x64, 0x65, 0x72, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0,
+	0x3c, 0x21, 0x44, 0x4f, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, 
+	0x48, 0x54, 0x4d, 0x4c, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, 
+	0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f, 
+	0x2f, 0x44, 0x54, 0x44, 0x20, 0x48, 0x54, 0x4d, 0x4c, 0x20, 
+	0x34, 0x2e, 0x30, 0x31, 0x20, 0x54, 0x72, 0x61, 0x6e, 0x73, 
+	0x69, 0x74, 0x69, 0x6f, 0x6e, 0x61, 0x6c, 0x2f, 0x2f, 0x45, 
+	0x4e, 0x22, 0x20, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 
+	0x2f, 0x77, 0x77, 0x77, 0x2e, 0x77, 0x33, 0x2e, 0x6f, 0x72, 
+	0x67, 0x2f, 0x54, 0x52, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x34, 
+	0x2f, 0x6c, 0x6f, 0x6f, 0x73, 0x65, 0x2e, 0x64, 0x74, 0x64, 
+	0x22, 0x3e, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xa, 
+	0x20, 0x20, 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, 0xa, 0x20, 
+	0x20, 0x20, 0x20, 0x3c, 0x74, 0x69, 0x74, 0x6c, 0x65, 0x3e, 
+	0x57, 0x65, 0x6c, 0x63, 0x6f, 0x6d, 0x65, 0x20, 0x74, 0x6f, 
+	0x20, 0x74, 0x68, 0x65, 0x20, 0x75, 0x49, 0x50, 0x20, 0x77, 
+	0x65, 0x62, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, 0x72, 0x21, 
+	0x3c, 0x2f, 0x74, 0x69, 0x74, 0x6c, 0x65, 0x3e, 0xa, 0x20, 
+	0x20, 0x20, 0x20, 0x3c, 0x6c, 0x69, 0x6e, 0x6b, 0x20, 0x72, 
+	0x65, 0x6c, 0x3d, 0x22, 0x73, 0x74, 0x79, 0x6c, 0x65, 0x73, 
+	0x68, 0x65, 0x65, 0x74, 0x22, 0x20, 0x74, 0x79, 0x70, 0x65, 
+	0x3d, 0x22, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 
+	0x22, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x73, 0x74, 
+	0x79, 0x6c, 0x65, 0x2e, 0x63, 0x73, 0x73, 0x22, 0x3e, 0x20, 
+	0x20, 0xa, 0x20, 0x20, 0x3c, 0x2f, 0x68, 0x65, 0x61, 0x64, 
+	0x3e, 0xa, 0x20, 0x20, 0x3c, 0x62, 0x6f, 0x64, 0x79, 0x20, 
+	0x62, 0x67, 0x63, 0x6f, 0x6c, 0x6f, 0x72, 0x3d, 0x22, 0x23, 
+	0x66, 0x66, 0x66, 0x65, 0x65, 0x63, 0x22, 0x20, 0x74, 0x65, 
+	0x78, 0x74, 0x3d, 0x22, 0x62, 0x6c, 0x61, 0x63, 0x6b, 0x22, 
+	0x3e, 0xa, 0xa, 0x20, 0x20, 0x3c, 0x64, 0x69, 0x76, 0x20, 
+	0x63, 0x6c, 0x61, 0x73, 0x73, 0x3d, 0x22, 0x6d, 0x65, 0x6e, 
+	0x75, 0x22, 0x3e, 0xa, 0x20, 0x20, 0x3c, 0x64, 0x69, 0x76, 
+	0x20, 0x63, 0x6c, 0x61, 0x73, 0x73, 0x3d, 0x22, 0x6d, 0x65, 
+	0x6e, 0x75, 0x62, 0x6f, 0x78, 0x22, 0x3e, 0x3c, 0x61, 0x20, 
+	0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x2f, 0x22, 0x3e, 0x46, 
+	0x72, 0x6f, 0x6e, 0x74, 0x20, 0x70, 0x61, 0x67, 0x65, 0x3c, 
+	0x2f, 0x61, 0x3e, 0x3c, 0x2f, 0x64, 0x69, 0x76, 0x3e, 0xa, 
+	0x20, 0x20, 0x3c, 0x64, 0x69, 0x76, 0x20, 0x63, 0x6c, 0x61, 
+	0x73, 0x73, 0x3d, 0x22, 0x6d, 0x65, 0x6e, 0x75, 0x62, 0x6f, 
+	0x78, 0x22, 0x3e, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 
+	0x3d, 0x22, 0x66, 0x69, 0x6c, 0x65, 0x73, 0x2e, 0x73, 0x68, 
+	0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x46, 0x69, 0x6c, 0x65, 0x20, 
+	0x73, 0x74, 0x61, 0x74, 0x69, 0x73, 0x74, 0x69, 0x63, 0x73, 
+	0x3c, 0x2f, 0x61, 0x3e, 0x3c, 0x2f, 0x64, 0x69, 0x76, 0x3e, 
+	0xa, 0x20, 0x20, 0x3c, 0x64, 0x69, 0x76, 0x20, 0x63, 0x6c, 
+	0x61, 0x73, 0x73, 0x3d, 0x22, 0x6d, 0x65, 0x6e, 0x75, 0x62, 
+	0x6f, 0x78, 0x22, 0x3e, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 
+	0x66, 0x3d, 0x22, 0x73, 0x74, 0x61, 0x74, 0x73, 0x2e, 0x73, 
+	0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x4e, 0x65, 0x74, 0x77, 
+	0x6f, 0x72, 0x6b, 0x20, 0x73, 0x74, 0x61, 0x74, 0x69, 0x73, 
+	0x74, 0x69, 0x63, 0x73, 0x3c, 0x2f, 0x61, 0x3e, 0x3c, 0x2f, 
+	0x64, 0x69, 0x76, 0x3e, 0xa, 0x20, 0x20, 0x3c, 0x64, 0x69, 
+	0x76, 0x20, 0x63, 0x6c, 0x61, 0x73, 0x73, 0x3d, 0x22, 0x6d, 
+	0x65, 0x6e, 0x75, 0x62, 0x6f, 0x78, 0x22, 0x3e, 0x3c, 0x61, 
+	0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x74, 0x63, 0x70, 
+	0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x4e, 0x65, 
+	0x74, 0x77, 0x6f, 0x72, 0x6b, 0xa, 0x20, 0x20, 0x63, 0x6f, 
+	0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0x3c, 
+	0x2f, 0x61, 0x3e, 0x3c, 0x2f, 0x64, 0x69, 0x76, 0x3e, 0xa, 
+	0x20, 0x20, 0x3c, 0x62, 0x72, 0x3e, 0xa, 0x20, 0x20, 0x3c, 
+	0x2f, 0x64, 0x69, 0x76, 0x3e, 0xa, 0x20, 0x20, 0xa, 0x20, 
+	0x20, 0x3c, 0x64, 0x69, 0x76, 0x20, 0x63, 0x6c, 0x61, 0x73, 
+	0x73, 0x3d, 0x22, 0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 
+	0x62, 0x6c, 0x6f, 0x63, 0x6b, 0x22, 0x3e, 0xa, 0};
+
+static const unsigned char data_index_html[] = {
+	/* /index.html */
+	0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0,
+	0x3c, 0x21, 0x44, 0x4f, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, 
+	0x48, 0x54, 0x4d, 0x4c, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, 
+	0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f, 
+	0x2f, 0x44, 0x54, 0x44, 0x20, 0x48, 0x54, 0x4d, 0x4c, 0x20, 
+	0x34, 0x2e, 0x30, 0x31, 0x20, 0x54, 0x72, 0x61, 0x6e, 0x73, 
+	0x69, 0x74, 0x69, 0x6f, 0x6e, 0x61, 0x6c, 0x2f, 0x2f, 0x45, 
+	0x4e, 0x22, 0x20, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 
+	0x2f, 0x77, 0x77, 0x77, 0x2e, 0x77, 0x33, 0x2e, 0x6f, 0x72, 
+	0x67, 0x2f, 0x54, 0x52, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x34, 
+	0x2f, 0x6c, 0x6f, 0x6f, 0x73, 0x65, 0x2e, 0x64, 0x74, 0x64, 
+	0x22, 0x3e, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xa, 
+	0x20, 0x20, 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, 0xa, 0x20, 
+	0x20, 0x20, 0x20, 0x3c, 0x74, 0x69, 0x74, 0x6c, 0x65, 0x3e, 
+	0x57, 0x65, 0x6c, 0x63, 0x6f, 0x6d, 0x65, 0x20, 0x74, 0x6f, 
+	0x20, 0x74, 0x68, 0x65, 0x20, 0x75, 0x49, 0x50, 0x20, 0x77, 
+	0x65, 0x62, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, 0x72, 0x21, 
+	0x3c, 0x2f, 0x74, 0x69, 0x74, 0x6c, 0x65, 0x3e, 0xa, 0x20, 
+	0x20, 0x20, 0x20, 0x3c, 0x6c, 0x69, 0x6e, 0x6b, 0x20, 0x72, 
+	0x65, 0x6c, 0x3d, 0x22, 0x73, 0x74, 0x79, 0x6c, 0x65, 0x73, 
+	0x68, 0x65, 0x65, 0x74, 0x22, 0x20, 0x74, 0x79, 0x70, 0x65, 
+	0x3d, 0x22, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 
+	0x22, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x73, 0x74, 
+	0x79, 0x6c, 0x65, 0x2e, 0x63, 0x73, 0x73, 0x22, 0x3e, 0x20, 
+	0x20, 0xa, 0x20, 0x20, 0x3c, 0x2f, 0x68, 0x65, 0x61, 0x64, 
+	0x3e, 0xa, 0x20, 0x20, 0x3c, 0x62, 0x6f, 0x64, 0x79, 0x20, 
+	0x62, 0x67, 0x63, 0x6f, 0x6c, 0x6f, 0x72, 0x3d, 0x22, 0x23, 
+	0x66, 0x66, 0x66, 0x65, 0x65, 0x63, 0x22, 0x20, 0x74, 0x65, 
+	0x78, 0x74, 0x3d, 0x22, 0x62, 0x6c, 0x61, 0x63, 0x6b, 0x22, 
+	0x3e, 0xa, 0xa, 0x20, 0x20, 0x3c, 0x64, 0x69, 0x76, 0x20, 
+	0x63, 0x6c, 0x61, 0x73, 0x73, 0x3d, 0x22, 0x6d, 0x65, 0x6e, 
+	0x75, 0x22, 0x3e, 0xa, 0x20, 0x20, 0x3c, 0x64, 0x69, 0x76, 
+	0x20, 0x63, 0x6c, 0x61, 0x73, 0x73, 0x3d, 0x22, 0x6d, 0x65, 
+	0x6e, 0x75, 0x62, 0x6f, 0x78, 0x22, 0x3e, 0x3c, 0x61, 0x20, 
+	0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x2f, 0x22, 0x3e, 0x46, 
+	0x72, 0x6f, 0x6e, 0x74, 0x20, 0x70, 0x61, 0x67, 0x65, 0x3c, 
+	0x2f, 0x61, 0x3e, 0x3c, 0x2f, 0x64, 0x69, 0x76, 0x3e, 0xa, 
+	0x20, 0x20, 0x3c, 0x64, 0x69, 0x76, 0x20, 0x63, 0x6c, 0x61, 
+	0x73, 0x73, 0x3d, 0x22, 0x6d, 0x65, 0x6e, 0x75, 0x62, 0x6f, 
+	0x78, 0x22, 0x3e, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 
+	0x3d, 0x22, 0x66, 0x69, 0x6c, 0x65, 0x73, 0x2e, 0x73, 0x68, 
+	0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x46, 0x69, 0x6c, 0x65, 0x20, 
+	0x73, 0x74, 0x61, 0x74, 0x69, 0x73, 0x74, 0x69, 0x63, 0x73, 
+	0x3c, 0x2f, 0x61, 0x3e, 0x3c, 0x2f, 0x64, 0x69, 0x76, 0x3e, 
+	0xa, 0x20, 0x20, 0x3c, 0x64, 0x69, 0x76, 0x20, 0x63, 0x6c, 
+	0x61, 0x73, 0x73, 0x3d, 0x22, 0x6d, 0x65, 0x6e, 0x75, 0x62, 
+	0x6f, 0x78, 0x22, 0x3e, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 
+	0x66, 0x3d, 0x22, 0x73, 0x74, 0x61, 0x74, 0x73, 0x2e, 0x73, 
+	0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x4e, 0x65, 0x74, 0x77, 
+	0x6f, 0x72, 0x6b, 0x20, 0x73, 0x74, 0x61, 0x74, 0x69, 0x73, 
+	0x74, 0x69, 0x63, 0x73, 0x3c, 0x2f, 0x61, 0x3e, 0x3c, 0x2f, 
+	0x64, 0x69, 0x76, 0x3e, 0xa, 0x20, 0x20, 0x3c, 0x64, 0x69, 
+	0x76, 0x20, 0x63, 0x6c, 0x61, 0x73, 0x73, 0x3d, 0x22, 0x6d, 
+	0x65, 0x6e, 0x75, 0x62, 0x6f, 0x78, 0x22, 0x3e, 0x3c, 0x61, 
+	0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x74, 0x63, 0x70, 
+	0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x4e, 0x65, 
+	0x74, 0x77, 0x6f, 0x72, 0x6b, 0xa, 0x20, 0x20, 0x63, 0x6f, 
+	0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0x3c, 
+	0x2f, 0x61, 0x3e, 0x3c, 0x2f, 0x64, 0x69, 0x76, 0x3e, 0xa, 
+	0x20, 0x20, 0x3c, 0x62, 0x72, 0x3e, 0xa, 0x20, 0x20, 0x3c, 
+	0x2f, 0x64, 0x69, 0x76, 0x3e, 0xa, 0xa, 0x20, 0x20, 0x3c, 
+	0x64, 0x69, 0x76, 0x20, 0x63, 0x6c, 0x61, 0x73, 0x73, 0x3d, 
+	0x22, 0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x62, 0x6c, 
+	0x6f, 0x63, 0x6b, 0x22, 0x3e, 0xa, 0x20, 0x20, 0x3c, 0x70, 
+	0x3e, 0xa, 0x20, 0x20, 0x54, 0x68, 0x65, 0x73, 0x65, 0x20, 
+	0x77, 0x65, 0x62, 0x20, 0x70, 0x61, 0x67, 0x65, 0x73, 0x20, 
+	0x61, 0x72, 0x65, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, 0x64, 
+	0x20, 0x62, 0x79, 0x20, 0x61, 0x20, 0x73, 0x6d, 0x61, 0x6c, 
+	0x6c, 0x20, 0x77, 0x65, 0x62, 0x20, 0x73, 0x65, 0x72, 0x76, 
+	0x65, 0x72, 0x20, 0x72, 0x75, 0x6e, 0x6e, 0x69, 0x6e, 0x67, 
+	0x20, 0x6f, 0x6e, 0x20, 0x74, 0x6f, 0x70, 0x20, 0x6f, 0x66, 
+	0xa, 0x20, 0x20, 0x74, 0x68, 0x65, 0x20, 0x3c, 0x61, 0x20, 
+	0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x68, 0x74, 0x74, 0x70, 
+	0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 
+	0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 
+	0x2f, 0x75, 0x69, 0x70, 0x2f, 0x22, 0x3e, 0x75, 0x49, 0x50, 
+	0x20, 0x65, 0x6d, 0x62, 0x65, 0x64, 0x64, 0x65, 0x64, 0x20, 
+	0x54, 0x43, 0x50, 0x2f, 0x49, 0x50, 0xa, 0x20, 0x20, 0x73, 
+	0x74, 0x61, 0x63, 0x6b, 0x3c, 0x2f, 0x61, 0x3e, 0x2e, 0xa, 
+	0x20, 0x20, 0x3c, 0x2f, 0x70, 0x3e, 0xa, 0x20, 0x20, 0x3c, 
+	0x70, 0x3e, 0xa, 0x20, 0x20, 0x43, 0x6c, 0x69, 0x63, 0x6b, 
+	0x20, 0x6f, 0x6e, 0x20, 0x74, 0x68, 0x65, 0x20, 0x6c, 0x69, 
+	0x6e, 0x6b, 0x73, 0x20, 0x61, 0x62, 0x6f, 0x76, 0x65, 0x20, 
+	0x66, 0x6f, 0x72, 0x20, 0x77, 0x65, 0x62, 0x20, 0x73, 0x65, 
+	0x72, 0x76, 0x65, 0x72, 0x20, 0x73, 0x74, 0x61, 0x74, 0x69, 
+	0x73, 0x74, 0x69, 0x63, 0x73, 0x2e, 0xa, 0x20, 0x20, 0x3c, 
+	0x2f, 0x70, 0x3e, 0xa, 0xa, 0x20, 0x20, 0x3c, 0x2f, 0x62, 
+	0x6f, 0x64, 0x79, 0x3e, 0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 
+	0x6c, 0x3e, 0xa, 0};
+
+static const unsigned char data_style_css[] = {
+	/* /style.css */
+	0x2f, 0x73, 0x74, 0x79, 0x6c, 0x65, 0x2e, 0x63, 0x73, 0x73, 0,
+	0x68, 0x31, 0x20, 0xa, 0x7b, 0xa, 0x20, 0x20, 0x74, 0x65, 
+	0x78, 0x74, 0x2d, 0x61, 0x6c, 0x69, 0x67, 0x6e, 0x3a, 0x20, 
+	0x63, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3b, 0xa, 0x20, 0x20, 
+	0x66, 0x6f, 0x6e, 0x74, 0x2d, 0x73, 0x69, 0x7a, 0x65, 0x3a, 
+	0x31, 0x34, 0x70, 0x74, 0x3b, 0xa, 0x20, 0x20, 0x66, 0x6f, 
+	0x6e, 0x74, 0x2d, 0x66, 0x61, 0x6d, 0x69, 0x6c, 0x79, 0x3a, 
+	0x61, 0x72, 0x69, 0x61, 0x6c, 0x2c, 0x68, 0x65, 0x6c, 0x76, 
+	0x65, 0x74, 0x69, 0x63, 0x61, 0x3b, 0xa, 0x20, 0x20, 0x66, 
+	0x6f, 0x6e, 0x74, 0x2d, 0x77, 0x65, 0x69, 0x67, 0x68, 0x74, 
+	0x3a, 0x62, 0x6f, 0x6c, 0x64, 0x3b, 0xa, 0x20, 0x20, 0x70, 
+	0x61, 0x64, 0x64, 0x69, 0x6e, 0x67, 0x3a, 0x31, 0x30, 0x70, 
+	0x78, 0x3b, 0x20, 0xa, 0x7d, 0xa, 0xa, 0x62, 0x6f, 0x64, 
+	0x79, 0xa, 0x7b, 0xa, 0xa, 0x20, 0x20, 0x62, 0x61, 0x63, 
+	0x6b, 0x67, 0x72, 0x6f, 0x75, 0x6e, 0x64, 0x2d, 0x63, 0x6f, 
+	0x6c, 0x6f, 0x72, 0x3a, 0x20, 0x23, 0x66, 0x66, 0x66, 0x65, 
+	0x65, 0x63, 0x3b, 0xa, 0x20, 0x20, 0x63, 0x6f, 0x6c, 0x6f, 
+	0x72, 0x3a, 0x62, 0x6c, 0x61, 0x63, 0x6b, 0x3b, 0xa, 0xa, 
+	0x20, 0x20, 0x66, 0x6f, 0x6e, 0x74, 0x2d, 0x73, 0x69, 0x7a, 
+	0x65, 0x3a, 0x38, 0x70, 0x74, 0x3b, 0xa, 0x20, 0x20, 0x66, 
+	0x6f, 0x6e, 0x74, 0x2d, 0x66, 0x61, 0x6d, 0x69, 0x6c, 0x79, 
+	0x3a, 0x61, 0x72, 0x69, 0x61, 0x6c, 0x2c, 0x68, 0x65, 0x6c, 
+	0x76, 0x65, 0x74, 0x69, 0x63, 0x61, 0x3b, 0xa, 0x7d, 0xa, 
+	0xa, 0x2e, 0x6d, 0x65, 0x6e, 0x75, 0xa, 0x7b, 0xa, 0x20, 
+	0x20, 0x6d, 0x61, 0x72, 0x67, 0x69, 0x6e, 0x3a, 0x20, 0x34, 
+	0x70, 0x78, 0x3b, 0xa, 0x20, 0x20, 0x77, 0x69, 0x64, 0x74, 
+	0x68, 0x3a, 0x36, 0x30, 0x25, 0x3b, 0xa, 0xa, 0x20, 0x20, 
+	0x70, 0x61, 0x64, 0x64, 0x69, 0x6e, 0x67, 0x3a, 0x32, 0x70, 
+	0x78, 0x3b, 0xa, 0x9, 0xa, 0x20, 0x20, 0x62, 0x6f, 0x72, 
+	0x64, 0x65, 0x72, 0x3a, 0x20, 0x73, 0x6f, 0x6c, 0x69, 0x64, 
+	0x20, 0x31, 0x70, 0x78, 0x3b, 0xa, 0x20, 0x20, 0x62, 0x61, 
+	0x63, 0x6b, 0x67, 0x72, 0x6f, 0x75, 0x6e, 0x64, 0x2d, 0x63, 
+	0x6f, 0x6c, 0x6f, 0x72, 0x3a, 0x20, 0x23, 0x66, 0x66, 0x66, 
+	0x63, 0x64, 0x32, 0x3b, 0xa, 0x20, 0x20, 0x74, 0x65, 0x78, 
+	0x74, 0x2d, 0x61, 0x6c, 0x69, 0x67, 0x6e, 0x3a, 0x6c, 0x65, 
+	0x66, 0x74, 0x3b, 0xa, 0x20, 0x20, 0xa, 0x20, 0x20, 0x66, 
+	0x6f, 0x6e, 0x74, 0x2d, 0x73, 0x69, 0x7a, 0x65, 0x3a, 0x39, 
+	0x70, 0x74, 0x3b, 0xa, 0x20, 0x20, 0x66, 0x6f, 0x6e, 0x74, 
+	0x2d, 0x66, 0x61, 0x6d, 0x69, 0x6c, 0x79, 0x3a, 0x61, 0x72, 
+	0x69, 0x61, 0x6c, 0x2c, 0x68, 0x65, 0x6c, 0x76, 0x65, 0x74, 
+	0x69, 0x63, 0x61, 0x3b, 0x20, 0x20, 0xa, 0x7d, 0xa, 0xa, 
+	0x64, 0x69, 0x76, 0x2e, 0x6d, 0x65, 0x6e, 0x75, 0x62, 0x6f, 
+	0x78, 0xa, 0x7b, 0xa, 0x20, 0x20, 0x77, 0x69, 0x64, 0x74, 
+	0x68, 0x3a, 0x20, 0x32, 0x35, 0x25, 0x3b, 0xa, 0x20, 0x20, 
+	0x62, 0x6f, 0x72, 0x64, 0x65, 0x72, 0x3a, 0x20, 0x30, 0x3b, 
+	0xa, 0x20, 0x20, 0x66, 0x6c, 0x6f, 0x61, 0x74, 0x3a, 0x20, 
+	0x6c, 0x65, 0x66, 0x74, 0x3b, 0xa, 0x74, 0x65, 0x78, 0x74, 
+	0x2d, 0x61, 0x6c, 0x69, 0x67, 0x6e, 0x3a, 0x20, 0x63, 0x65, 
+	0x6e, 0x74, 0x65, 0x72, 0x3b, 0xa, 0x7d, 0xa, 0xa, 0x2e, 
+	0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x62, 0x6c, 0x6f, 
+	0x63, 0x6b, 0xa, 0x7b, 0x20, 0x20, 0xa, 0x20, 0x20, 0x6d, 
+	0x61, 0x72, 0x67, 0x69, 0x6e, 0x3a, 0x20, 0x34, 0x70, 0x78, 
+	0x3b, 0xa, 0x20, 0x20, 0x77, 0x69, 0x64, 0x74, 0x68, 0x3a, 
+	0x36, 0x30, 0x25, 0x3b, 0xa, 0xa, 0x20, 0x20, 0x70, 0x61, 
+	0x64, 0x64, 0x69, 0x6e, 0x67, 0x3a, 0x32, 0x70, 0x78, 0x3b, 
+	0xa, 0xa, 0x20, 0x20, 0x62, 0x6f, 0x72, 0x64, 0x65, 0x72, 
+	0x3a, 0x20, 0x31, 0x70, 0x78, 0x20, 0x64, 0x6f, 0x74, 0x74, 
+	0x65, 0x64, 0x3b, 0xa, 0x20, 0x20, 0x62, 0x61, 0x63, 0x6b, 
+	0x67, 0x72, 0x6f, 0x75, 0x6e, 0x64, 0x2d, 0x63, 0x6f, 0x6c, 
+	0x6f, 0x72, 0x3a, 0x20, 0x77, 0x68, 0x69, 0x74, 0x65, 0x3b, 
+	0xa, 0xa, 0x20, 0x20, 0x66, 0x6f, 0x6e, 0x74, 0x2d, 0x73, 
+	0x69, 0x7a, 0x65, 0x3a, 0x38, 0x70, 0x74, 0x3b, 0xa, 0x20, 
+	0x20, 0x66, 0x6f, 0x6e, 0x74, 0x2d, 0x66, 0x61, 0x6d, 0x69, 
+	0x6c, 0x79, 0x3a, 0x61, 0x72, 0x69, 0x61, 0x6c, 0x2c, 0x68, 
+	0x65, 0x6c, 0x76, 0x65, 0x74, 0x69, 0x63, 0x61, 0x3b, 0x20, 
+	0x20, 0xa, 0xa, 0x7d, 0xa, 0xa, 0x70, 0x2e, 0x69, 0x6e, 
+	0x74, 0x72, 0x6f, 0xa, 0x7b, 0xa, 0x20, 0x20, 0x6d, 0x61, 
+	0x72, 0x67, 0x69, 0x6e, 0x2d, 0x6c, 0x65, 0x66, 0x74, 0x3a, 
+	0x32, 0x30, 0x70, 0x78, 0x3b, 0xa, 0x20, 0x20, 0x6d, 0x61, 
+	0x72, 0x67, 0x69, 0x6e, 0x2d, 0x72, 0x69, 0x67, 0x68, 0x74, 
+	0x3a, 0x32, 0x30, 0x70, 0x78, 0x3b, 0xa, 0xa, 0x20, 0x20, 
+	0x66, 0x6f, 0x6e, 0x74, 0x2d, 0x73, 0x69, 0x7a, 0x65, 0x3a, 
+	0x31, 0x30, 0x70, 0x74, 0x3b, 0xa, 0x2f, 0x2a, 0x20, 0x20, 
+	0x66, 0x6f, 0x6e, 0x74, 0x2d, 0x77, 0x65, 0x69, 0x67, 0x68, 
+	0x74, 0x3a, 0x62, 0x6f, 0x6c, 0x64, 0x3b, 0x20, 0x2a, 0x2f, 
+	0xa, 0x20, 0x20, 0x66, 0x6f, 0x6e, 0x74, 0x2d, 0x66, 0x61, 
+	0x6d, 0x69, 0x6c, 0x79, 0x3a, 0x61, 0x72, 0x69, 0x61, 0x6c, 
+	0x2c, 0x68, 0x65, 0x6c, 0x76, 0x65, 0x74, 0x69, 0x63, 0x61, 
+	0x3b, 0x20, 0x20, 0xa, 0x7d, 0xa, 0xa, 0x70, 0x2e, 0x63, 
+	0x6c, 0x69, 0x6e, 0x6b, 0xa, 0x7b, 0xa, 0x20, 0x20, 0x66, 
+	0x6f, 0x6e, 0x74, 0x2d, 0x73, 0x69, 0x7a, 0x65, 0x3a, 0x31, 
+	0x32, 0x70, 0x74, 0x3b, 0xa, 0x20, 0x20, 0x66, 0x6f, 0x6e, 
+	0x74, 0x2d, 0x66, 0x61, 0x6d, 0x69, 0x6c, 0x79, 0x3a, 0x63, 
+	0x6f, 0x75, 0x72, 0x69, 0x65, 0x72, 0x2c, 0x6d, 0x6f, 0x6e, 
+	0x6f, 0x73, 0x70, 0x61, 0x63, 0x65, 0x3b, 0x20, 0x20, 0xa, 
+	0x20, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2d, 0x61, 0x6c, 0x69, 
+	0x67, 0x6e, 0x3a, 0x63, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3b, 
+	0xa, 0x7d, 0xa, 0xa, 0x70, 0x2e, 0x63, 0x6c, 0x69, 0x6e, 
+	0x6b, 0x39, 0xa, 0x7b, 0xa, 0x20, 0x20, 0x66, 0x6f, 0x6e, 
+	0x74, 0x2d, 0x73, 0x69, 0x7a, 0x65, 0x3a, 0x39, 0x70, 0x74, 
+	0x3b, 0xa, 0x20, 0x20, 0x66, 0x6f, 0x6e, 0x74, 0x2d, 0x66, 
+	0x61, 0x6d, 0x69, 0x6c, 0x79, 0x3a, 0x63, 0x6f, 0x75, 0x72, 
+	0x69, 0x65, 0x72, 0x2c, 0x6d, 0x6f, 0x6e, 0x6f, 0x73, 0x70, 
+	0x61, 0x63, 0x65, 0x3b, 0x20, 0x20, 0xa, 0x20, 0x20, 0x74, 
+	0x65, 0x78, 0x74, 0x2d, 0x61, 0x6c, 0x69, 0x67, 0x6e, 0x3a, 
+	0x63, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3b, 0xa, 0x7d, 0xa, 
+	0xa, 0xa, 0x70, 0xa, 0x7b, 0xa, 0x20, 0x20, 0x70, 0x61, 
+	0x64, 0x64, 0x69, 0x6e, 0x67, 0x2d, 0x6c, 0x65, 0x66, 0x74, 
+	0x3a, 0x31, 0x30, 0x70, 0x78, 0x3b, 0xa, 0x7d, 0xa, 0xa, 
+	0x70, 0x2e, 0x72, 0x69, 0x67, 0x68, 0x74, 0xa, 0x7b, 0xa, 
+	0x20, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2d, 0x61, 0x6c, 0x69, 
+	0x67, 0x6e, 0x3a, 0x72, 0x69, 0x67, 0x68, 0x74, 0x3b, 0x20, 
+	0xa, 0x7d, 0xa, 0xa, 0};
+
+static const unsigned char data_tcp_shtml[] = {
+	/* /tcp.shtml */
+	0x2f, 0x74, 0x63, 0x70, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0,
+	0x25, 0x21, 0x3a, 0x20, 0x2f, 0x68, 0x65, 0x61, 0x64, 0x65, 
+	0x72, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0xa, 0x3c, 0x68, 0x31, 
+	0x3e, 0x43, 0x75, 0x72, 0x72, 0x65, 0x6e, 0x74, 0x20, 0x63, 
+	0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 
+	0x3c, 0x2f, 0x68, 0x31, 0x3e, 0x3c, 0x62, 0x72, 0x3e, 0x3c, 
+	0x74, 0x61, 0x62, 0x6c, 0x65, 0x20, 0x77, 0x69, 0x64, 0x74, 
+	0x68, 0x3d, 0x22, 0x31, 0x30, 0x30, 0x25, 0x22, 0x3e, 0xa, 
+	0x3c, 0x74, 0x72, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x4c, 0x6f, 
+	0x63, 0x61, 0x6c, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 
+	0x68, 0x3e, 0x52, 0x65, 0x6d, 0x6f, 0x74, 0x65, 0x3c, 0x2f, 
+	0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x53, 0x74, 0x61, 
+	0x74, 0x65, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 
+	0x3e, 0x52, 0x65, 0x74, 0x72, 0x61, 0x6e, 0x73, 0x6d, 0x69, 
+	0x73, 0x73, 0x69, 0x6f, 0x6e, 0x73, 0x3c, 0x2f, 0x74, 0x68, 
+	0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x54, 0x69, 0x6d, 0x65, 0x72, 
+	0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x46, 
+	0x6c, 0x61, 0x67, 0x73, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 
+	0x2f, 0x74, 0x72, 0x3e, 0xa, 0x25, 0x21, 0x20, 0x74, 0x63, 
+	0x70, 0x2d, 0x63, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 
+	0x6f, 0x6e, 0x73, 0xa, 0x25, 0x21, 0x3a, 0x20, 0x2f, 0x66, 
+	0x6f, 0x6f, 0x74, 0x65, 0x72, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 
+0};
+
+static const unsigned char data_fade_png[] = {
+	/* /fade.png */
+	0x2f, 0x66, 0x61, 0x64, 0x65, 0x2e, 0x70, 0x6e, 0x67, 0,
+	0x89, 0x50, 0x4e, 0x47, 0xd, 0xa, 0x1a, 0xa, 00, 00, 
+	00, 0xd, 0x49, 0x48, 0x44, 0x52, 00, 00, 00, 0x4, 
+	00, 00, 00, 0xa, 0x8, 0x2, 00, 00, 00, 0x1c, 
+	0x99, 0x68, 0x59, 00, 00, 00, 0x9, 0x70, 0x48, 0x59, 
+	0x73, 00, 00, 0xb, 0x13, 00, 00, 0xb, 0x13, 0x1, 
+	00, 0x9a, 0x9c, 0x18, 00, 00, 00, 0x7, 0x74, 0x49, 
+	0x4d, 0x45, 0x7, 0xd6, 0x6, 0x8, 0x14, 0x1b, 0x39, 0xaf, 
+	0x5b, 0xc0, 0xe3, 00, 00, 00, 0x1d, 0x74, 0x45, 0x58, 
+	0x74, 0x43, 0x6f, 0x6d, 0x6d, 0x65, 0x6e, 0x74, 00, 0x43, 
+	0x72, 0x65, 0x61, 0x74, 0x65, 0x64, 0x20, 0x77, 0x69, 0x74, 
+	0x68, 0x20, 0x54, 0x68, 0x65, 0x20, 0x47, 0x49, 0x4d, 0x50, 
+	0xef, 0x64, 0x25, 0x6e, 00, 00, 00, 0x3a, 0x49, 0x44, 
+	0x41, 0x54, 0x8, 0xd7, 0x75, 0x8c, 0x31, 0x12, 00, 0x10, 
+	0x10, 0xc4, 0x2e, 0x37, 0x9e, 0x40, 0x65, 0xfd, 0xff, 0x83, 
+	0xf4, 0xa, 0x1c, 0x8d, 0x54, 0x9b, 0xc9, 0xcc, 0x9a, 0x3d, 
+	0x90, 0x73, 0x71, 0x67, 0x91, 0xd4, 0x74, 0x36, 0xa9, 0x55, 
+	0x1, 0xf8, 0x29, 0x58, 0xc8, 0xbf, 0x48, 0xc4, 0x81, 0x74, 
+	0xb, 0xa3, 0xf, 0x7c, 0xdb, 0x4, 0xe8, 0x40, 0x5, 0xdf, 
+	0xa1, 0xf3, 0xfc, 0x73, 00, 00, 00, 00, 0x49, 0x45, 
+	0x4e, 0x44, 0xae, 0x42, 0x60, 0x82, 0};
+
+static const unsigned char data_stats_shtml[] = {
+	/* /stats.shtml */
+	0x2f, 0x73, 0x74, 0x61, 0x74, 0x73, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0,
+	0x25, 0x21, 0x3a, 0x20, 0x2f, 0x68, 0x65, 0x61, 0x64, 0x65, 
+	0x72, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0xa, 0x3c, 0x68, 0x31, 
+	0x3e, 0x4e, 0x65, 0x74, 0x77, 0x6f, 0x72, 0x6b, 0x20, 0x73, 
+	0x74, 0x61, 0x74, 0x69, 0x73, 0x74, 0x69, 0x63, 0x73, 0x3c, 
+	0x2f, 0x68, 0x31, 0x3e, 0xa, 0x3c, 0x63, 0x65, 0x6e, 0x74, 
+	0x65, 0x72, 0x3e, 0xa, 0x3c, 0x74, 0x61, 0x62, 0x6c, 0x65, 
+	0x20, 0x77, 0x69, 0x64, 0x74, 0x68, 0x3d, 0x22, 0x33, 0x30, 
+	0x30, 0x22, 0x20, 0x62, 0x6f, 0x72, 0x64, 0x65, 0x72, 0x3d, 
+	0x22, 0x30, 0x22, 0x3e, 0xa, 0x3c, 0x74, 0x72, 0x3e, 0x3c, 
+	0x74, 0x64, 0x3e, 0x3c, 0x70, 0x72, 0x65, 0x3e, 0xa, 0x49, 
+	0x50, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 
+	0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, 0x74, 0x73, 0x20, 
+	0x72, 0x65, 0x63, 0x65, 0x69, 0x76, 0x65, 0x64, 0xa, 0x20, 
+	0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 
+	0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, 0x74, 0x73, 0x20, 
+	0x73, 0x65, 0x6e, 0x74, 0xa, 0x9, 0x20, 0x20, 0x20, 0x20, 
+	0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, 0x74, 0x73, 0x20, 0x64, 
+	0x72, 0x6f, 0x70, 0x70, 0x65, 0x64, 0xa, 0x49, 0x50, 0x20, 
+	0x65, 0x72, 0x72, 0x6f, 0x72, 0x73, 0x20, 0x20, 0x20, 0x20, 
+	0x49, 0x50, 0x20, 0x76, 0x65, 0x72, 0x73, 0x69, 0x6f, 0x6e, 
+	0x2f, 0x68, 0x65, 0x61, 0x64, 0x65, 0x72, 0x20, 0x6c, 0x65, 
+	0x6e, 0x67, 0x74, 0x68, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 
+	0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x49, 0x50, 
+	0x20, 0x6c, 0x65, 0x6e, 0x67, 0x74, 0x68, 0x2c, 0x20, 0x68, 
+	0x69, 0x67, 0x68, 0x20, 0x62, 0x79, 0x74, 0x65, 0xa, 0x20, 
+	0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 
+	0x20, 0x20, 0x49, 0x50, 0x20, 0x6c, 0x65, 0x6e, 0x67, 0x74, 
+	0x68, 0x2c, 0x20, 0x6c, 0x6f, 0x77, 0x20, 0x62, 0x79, 0x74, 
+	0x65, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 
+	0x20, 0x20, 0x20, 0x20, 0x20, 0x49, 0x50, 0x20, 0x66, 0x72, 
+	0x61, 0x67, 0x6d, 0x65, 0x6e, 0x74, 0x73, 0xa, 0x20, 0x20, 
+	0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 
+	0x20, 0x48, 0x65, 0x61, 0x64, 0x65, 0x72, 0x20, 0x63, 0x68, 
+	0x65, 0x63, 0x6b, 0x73, 0x75, 0x6d, 0xa, 0x20, 0x20, 0x20, 
+	0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 
+	0x57, 0x72, 0x6f, 0x6e, 0x67, 0x20, 0x70, 0x72, 0x6f, 0x74, 
+	0x6f, 0x63, 0x6f, 0x6c, 0xa, 0x49, 0x43, 0x4d, 0x50, 0x9, 
+	0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, 
+	0x74, 0x73, 0x20, 0x72, 0x65, 0x63, 0x65, 0x69, 0x76, 0x65, 
+	0x64, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 
+	0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, 
+	0x74, 0x73, 0x20, 0x73, 0x65, 0x6e, 0x74, 0xa, 0x20, 0x20, 
+	0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 
+	0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, 0x74, 0x73, 0x20, 0x64, 
+	0x72, 0x6f, 0x70, 0x70, 0x65, 0x64, 0xa, 0x20, 0x20, 0x20, 
+	0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 
+	0x54, 0x79, 0x70, 0x65, 0x20, 0x65, 0x72, 0x72, 0x6f, 0x72, 
+	0x73, 0xa, 0x54, 0x43, 0x50, 0x20, 0x20, 0x20, 0x20, 0x20, 
+	0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, 
+	0x74, 0x73, 0x20, 0x72, 0x65, 0x63, 0x65, 0x69, 0x76, 0x65, 
+	0x64, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 
+	0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, 
+	0x74, 0x73, 0x20, 0x73, 0x65, 0x6e, 0x74, 0xa, 0x20, 0x20, 
+	0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 
+	0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, 0x74, 0x73, 0x20, 0x64, 
+	0x72, 0x6f, 0x70, 0x70, 0x65, 0x64, 0xa, 0x20, 0x20, 0x20, 
+	0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 
+	0x43, 0x68, 0x65, 0x63, 0x6b, 0x73, 0x75, 0x6d, 0x20, 0x65, 
+	0x72, 0x72, 0x6f, 0x72, 0x73, 0xa, 0x20, 0x20, 0x20, 0x20, 
+	0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x44, 
+	0x61, 0x74, 0x61, 0x20, 0x70, 0x61, 0x63, 0x6b, 0x65, 0x74, 
+	0x73, 0x20, 0x77, 0x69, 0x74, 0x68, 0x6f, 0x75, 0x74, 0x20, 
+	0x41, 0x43, 0x4b, 0x73, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 
+	0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x52, 0x65, 
+	0x73, 0x65, 0x74, 0x73, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 
+	0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x52, 0x65, 
+	0x74, 0x72, 0x61, 0x6e, 0x73, 0x6d, 0x69, 0x73, 0x73, 0x69, 
+	0x6f, 0x6e, 0x73, 0xa, 0x9, 0x20, 0x20, 0x20, 0x20, 0x20, 
+	0x4e, 0x6f, 0x20, 0x63, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 
+	0x69, 0x6f, 0x6e, 0x20, 0x61, 0x76, 0x61, 0x6c, 0x69, 0x61, 
+	0x62, 0x6c, 0x65, 0xa, 0x9, 0x20, 0x20, 0x20, 0x20, 0x20, 
+	0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 
+	0x20, 0x61, 0x74, 0x74, 0x65, 0x6d, 0x70, 0x74, 0x73, 0x20, 
+	0x74, 0x6f, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0x64, 0x20, 
+	0x70, 0x6f, 0x72, 0x74, 0x73, 0xa, 0x3c, 0x2f, 0x70, 0x72, 
+	0x65, 0x3e, 0x3c, 0x2f, 0x74, 0x64, 0x3e, 0x3c, 0x74, 0x64, 
+	0x3e, 0x3c, 0x70, 0x72, 0x65, 0x3e, 0x25, 0x21, 0x20, 0x6e, 
+	0x65, 0x74, 0x2d, 0x73, 0x74, 0x61, 0x74, 0x73, 0xa, 0x3c, 
+	0x2f, 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x74, 0x61, 0x62, 
+	0x6c, 0x65, 0x3e, 0xa, 0x3c, 0x2f, 0x63, 0x65, 0x6e, 0x74, 
+	0x65, 0x72, 0x3e, 0xa, 0x25, 0x21, 0x3a, 0x20, 0x2f, 0x66, 
+	0x6f, 0x6f, 0x74, 0x65, 0x72, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 
+	0xa, 0};
+
+const struct httpd_fsdata_file file_processes_shtml[] = {{NULL, data_processes_shtml, data_processes_shtml + 17, sizeof(data_processes_shtml) - 17}};
+
+const struct httpd_fsdata_file file_404_html[] = {{file_processes_shtml, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}};
+
+const struct httpd_fsdata_file file_files_shtml[] = {{file_404_html, data_files_shtml, data_files_shtml + 13, sizeof(data_files_shtml) - 13}};
+
+const struct httpd_fsdata_file file_footer_html[] = {{file_files_shtml, data_footer_html, data_footer_html + 13, sizeof(data_footer_html) - 13}};
+
+const struct httpd_fsdata_file file_header_html[] = {{file_footer_html, data_header_html, data_header_html + 13, sizeof(data_header_html) - 13}};
+
+const struct httpd_fsdata_file file_index_html[] = {{file_header_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}};
+
+const struct httpd_fsdata_file file_style_css[] = {{file_index_html, data_style_css, data_style_css + 11, sizeof(data_style_css) - 11}};
+
+const struct httpd_fsdata_file file_tcp_shtml[] = {{file_style_css, data_tcp_shtml, data_tcp_shtml + 11, sizeof(data_tcp_shtml) - 11}};
+
+const struct httpd_fsdata_file file_fade_png[] = {{file_tcp_shtml, data_fade_png, data_fade_png + 10, sizeof(data_fade_png) - 10}};
+
+const struct httpd_fsdata_file file_stats_shtml[] = {{file_fade_png, data_stats_shtml, data_stats_shtml + 13, sizeof(data_stats_shtml) - 13}};
+
+#define HTTPD_FS_ROOT file_stats_shtml
+
+#define HTTPD_FS_NUMFILES 10
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fsdata.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fsdata.h
new file mode 100644
index 0000000..52d35c2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fsdata.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: httpd-fsdata.h,v 1.1 2006/06/07 09:13:08 adam Exp $
+ */
+#ifndef __HTTPD_FSDATA_H__
+#define __HTTPD_FSDATA_H__
+
+#include "uip.h"
+
+struct httpd_fsdata_file {
+  const struct httpd_fsdata_file *next;
+  const char *name;
+  const char *data;
+  const int len;
+#ifdef HTTPD_FS_STATISTICS
+#if HTTPD_FS_STATISTICS == 1
+  u16_t count;
+#endif /* HTTPD_FS_STATISTICS */
+#endif /* HTTPD_FS_STATISTICS */
+};
+
+struct httpd_fsdata_file_noconst {
+  struct httpd_fsdata_file *next;
+  char *name;
+  char *data;
+  int len;
+#ifdef HTTPD_FS_STATISTICS
+#if HTTPD_FS_STATISTICS == 1
+  u16_t count;
+#endif /* HTTPD_FS_STATISTICS */
+#endif /* HTTPD_FS_STATISTICS */
+};
+
+#endif /* __HTTPD_FSDATA_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd.c
new file mode 100644
index 0000000..e808688
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd.c
@@ -0,0 +1,338 @@
+/**
+ * \addtogroup apps
+ * @{
+ */
+
+/**
+ * \defgroup httpd Web server
+ * @{
+ * The uIP web server is a very simplistic implementation of an HTTP
+ * server. It can serve web pages and files from a read-only ROM
+ * filesystem, and provides a very small scripting language.
+
+ */
+
+/**
+ * \file
+ *         Web server
+ * \author
+ *         Adam Dunkels 
+ */
+
+
+/*
+ * Copyright (c) 2004, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $
+ */
+
+#include "uip.h"
+#include "httpd.h"
+#include "httpd-fs.h"
+#include "httpd-cgi.h"
+#include "http-strings.h"
+
+#include 
+
+#define STATE_WAITING 0
+#define STATE_OUTPUT  1
+
+#define ISO_nl      0x0a
+#define ISO_space   0x20
+#define ISO_bang    0x21
+#define ISO_percent 0x25
+#define ISO_period  0x2e
+#define ISO_slash   0x2f
+#define ISO_colon   0x3a
+
+
+/*---------------------------------------------------------------------------*/
+static unsigned short
+generate_part_of_file(void *state)
+{
+  struct httpd_state *s = (struct httpd_state *)state;
+
+  if(s->file.len > uip_mss()) {
+    s->len = uip_mss();
+  } else {
+    s->len = s->file.len;
+  }
+  memcpy(uip_appdata, s->file.data, s->len);
+  
+  return s->len;
+}
+/*---------------------------------------------------------------------------*/
+static
+PT_THREAD(send_file(struct httpd_state *s))
+{
+  PSOCK_BEGIN(&s->sout);
+  
+  do {
+    PSOCK_GENERATOR_SEND(&s->sout, generate_part_of_file, s);
+    s->file.len -= s->len;
+    s->file.data += s->len;
+  } while(s->file.len > 0);
+      
+  PSOCK_END(&s->sout);
+}
+/*---------------------------------------------------------------------------*/
+static
+PT_THREAD(send_part_of_file(struct httpd_state *s))
+{
+  PSOCK_BEGIN(&s->sout);
+
+  PSOCK_SEND(&s->sout, s->file.data, s->len);
+  
+  PSOCK_END(&s->sout);
+}
+/*---------------------------------------------------------------------------*/
+static void
+next_scriptstate(struct httpd_state *s)
+{
+  char *p;
+  p = strchr(s->scriptptr, ISO_nl) + 1;
+  s->scriptlen -= (unsigned short)(p - s->scriptptr);
+  s->scriptptr = p;
+}
+/*---------------------------------------------------------------------------*/
+static
+PT_THREAD(handle_script(struct httpd_state *s))
+{
+  char *ptr;
+  
+  PT_BEGIN(&s->scriptpt);
+
+
+  while(s->file.len > 0) {
+
+    /* Check if we should start executing a script. */
+    if(*s->file.data == ISO_percent &&
+       *(s->file.data + 1) == ISO_bang) {
+      s->scriptptr = s->file.data + 3;
+      s->scriptlen = s->file.len - 3;
+      if(*(s->scriptptr - 1) == ISO_colon) {
+	httpd_fs_open(s->scriptptr + 1, &s->file);
+	PT_WAIT_THREAD(&s->scriptpt, send_file(s));
+      } else {
+	PT_WAIT_THREAD(&s->scriptpt,
+		       httpd_cgi(s->scriptptr)(s, s->scriptptr));
+      }
+      next_scriptstate(s);
+      
+      /* The script is over, so we reset the pointers and continue
+	 sending the rest of the file. */
+      s->file.data = s->scriptptr;
+      s->file.len = s->scriptlen;
+    } else {
+      /* See if we find the start of script marker in the block of HTML
+	 to be sent. */
+
+      if(s->file.len > uip_mss()) {
+	s->len = uip_mss();
+      } else {
+	s->len = s->file.len;
+      }
+
+      if(*s->file.data == ISO_percent) {
+	ptr = strchr(s->file.data + 1, ISO_percent);
+      } else {
+	ptr = strchr(s->file.data, ISO_percent);
+      }
+      if(ptr != NULL &&
+	 ptr != s->file.data) {
+	s->len = (int)(ptr - s->file.data);
+	if(s->len >= uip_mss()) {
+	  s->len = uip_mss();
+	}
+      }
+      PT_WAIT_THREAD(&s->scriptpt, send_part_of_file(s));
+      s->file.data += s->len;
+      s->file.len -= s->len;
+      
+    }
+  }
+  
+  PT_END(&s->scriptpt);
+}
+/*---------------------------------------------------------------------------*/
+static
+PT_THREAD(send_headers(struct httpd_state *s, const char *statushdr))
+{
+  char *ptr;
+
+  PSOCK_BEGIN(&s->sout);
+
+  PSOCK_SEND_STR(&s->sout, statushdr);
+
+  ptr = strrchr(s->filename, ISO_period);
+  if(ptr == NULL) {
+    PSOCK_SEND_STR(&s->sout, http_content_type_binary);
+  } else if(strncmp(http_html, ptr, 5) == 0 ||
+	    strncmp(http_shtml, ptr, 6) == 0) {
+    PSOCK_SEND_STR(&s->sout, http_content_type_html);
+  } else if(strncmp(http_css, ptr, 4) == 0) {
+    PSOCK_SEND_STR(&s->sout, http_content_type_css);
+  } else if(strncmp(http_png, ptr, 4) == 0) {
+    PSOCK_SEND_STR(&s->sout, http_content_type_png);
+  } else if(strncmp(http_gif, ptr, 4) == 0) {
+    PSOCK_SEND_STR(&s->sout, http_content_type_gif);
+  } else if(strncmp(http_jpg, ptr, 4) == 0) {
+    PSOCK_SEND_STR(&s->sout, http_content_type_jpg);
+  } else {
+    PSOCK_SEND_STR(&s->sout, http_content_type_plain);
+  }
+  PSOCK_END(&s->sout);
+}
+/*---------------------------------------------------------------------------*/
+static
+PT_THREAD(handle_output(struct httpd_state *s))
+{
+  char *ptr;
+  
+  PT_BEGIN(&s->outputpt);
+ 
+  if(!httpd_fs_open(s->filename, &s->file)) {
+    httpd_fs_open(http_404_html, &s->file);
+    strcpy(s->filename, http_404_html);
+    PT_WAIT_THREAD(&s->outputpt,
+		   send_headers(s,
+		   http_header_404));
+    PT_WAIT_THREAD(&s->outputpt,
+		   send_file(s));
+  } else {
+    PT_WAIT_THREAD(&s->outputpt,
+		   send_headers(s,
+		   http_header_200));
+    ptr = strchr(s->filename, ISO_period);
+    if(ptr != NULL && strncmp(ptr, http_shtml, 6) == 0) {
+      PT_INIT(&s->scriptpt);
+      PT_WAIT_THREAD(&s->outputpt, handle_script(s));
+    } else {
+      PT_WAIT_THREAD(&s->outputpt,
+		     send_file(s));
+    }
+  }
+  PSOCK_CLOSE(&s->sout);
+  PT_END(&s->outputpt);
+}
+/*---------------------------------------------------------------------------*/
+static
+PT_THREAD(handle_input(struct httpd_state *s))
+{
+  PSOCK_BEGIN(&s->sin);
+
+  PSOCK_READTO(&s->sin, ISO_space);
+
+  
+  if(strncmp(s->inputbuf, http_get, 4) != 0) {
+    PSOCK_CLOSE_EXIT(&s->sin);
+  }
+  PSOCK_READTO(&s->sin, ISO_space);
+
+  if(s->inputbuf[0] != ISO_slash) {
+    PSOCK_CLOSE_EXIT(&s->sin);
+  }
+
+  if(s->inputbuf[1] == ISO_space) {
+    strncpy(s->filename, http_index_html, sizeof(s->filename));
+  } else {
+    s->inputbuf[PSOCK_DATALEN(&s->sin) - 1] = 0;
+    strncpy(s->filename, &s->inputbuf[0], sizeof(s->filename));
+  }
+
+  /*  httpd_log_file(uip_conn->ripaddr, s->filename);*/
+  
+  s->state = STATE_OUTPUT;
+
+  while(1) {
+    PSOCK_READTO(&s->sin, ISO_nl);
+
+    if(strncmp(s->inputbuf, http_referer, 8) == 0) {
+      s->inputbuf[PSOCK_DATALEN(&s->sin) - 2] = 0;
+      /*      httpd_log(&s->inputbuf[9]);*/
+    }
+  }
+  
+  PSOCK_END(&s->sin);
+}
+/*---------------------------------------------------------------------------*/
+static void
+handle_connection(struct httpd_state *s)
+{
+  handle_input(s);
+  if(s->state == STATE_OUTPUT) {
+    handle_output(s);
+  }
+}
+/*---------------------------------------------------------------------------*/
+void
+httpd_appcall(void)
+{
+  struct httpd_state *s = (struct httpd_state *)&(uip_conn->appstate);
+
+  if(uip_closed() || uip_aborted() || uip_timedout()) {
+  } else if(uip_connected()) {
+    PSOCK_INIT(&s->sin, s->inputbuf, sizeof(s->inputbuf) - 1);
+    PSOCK_INIT(&s->sout, s->inputbuf, sizeof(s->inputbuf) - 1);
+    PT_INIT(&s->outputpt);
+    s->state = STATE_WAITING;
+    /*    timer_set(&s->timer, CLOCK_SECOND * 100);*/
+    s->timer = 0;
+    handle_connection(s);
+  } else if(s != NULL) {
+    if(uip_poll()) {
+      ++s->timer;
+      if(s->timer >= 20) {
+	uip_abort();
+      }
+    } else {
+      s->timer = 0;
+    }
+    handle_connection(s);
+  } else {
+    uip_abort();
+  }
+}
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief      Initialize the web server
+ *
+ *             This function initializes the web server and should be
+ *             called at system boot-up.
+ */
+void
+httpd_init(void)
+{
+  uip_listen(HTONS(80));
+}
+/*---------------------------------------------------------------------------*/
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd.h
new file mode 100644
index 0000000..7f7a666
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2001-2005, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $
+ *
+ */
+
+#ifndef __HTTPD_H__
+#define __HTTPD_H__
+
+#include "psock.h"
+#include "httpd-fs.h"
+
+struct httpd_state {
+  unsigned char timer;
+  struct psock sin, sout;
+  struct pt outputpt, scriptpt;
+  char inputbuf[50];
+  char filename[20];
+  char state;
+  struct httpd_fs_file file;
+  int len;
+  char *scriptptr;
+  int scriptlen;
+  
+  unsigned short count;
+};
+
+void httpd_init(void);
+void httpd_appcall(void);
+
+void httpd_log(char *msg);
+void httpd_log_file(u16_t *requester, char *file);
+
+#endif /* __HTTPD_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/makefsdata b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/makefsdata
new file mode 100644
index 0000000..8d2715a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/makefsdata
@@ -0,0 +1,78 @@
+#!/usr/bin/perl
+
+open(OUTPUT, "> httpd-fsdata.c");
+
+chdir("httpd-fs");
+
+opendir(DIR, ".");
+@files =  grep { !/^\./ && !/(CVS|~)/ } readdir(DIR);
+closedir(DIR);
+
+foreach $file (@files) {  
+   
+    if(-d $file && $file !~ /^\./) {
+	print "Processing directory $file\n";
+	opendir(DIR, $file);
+	@newfiles =  grep { !/^\./ && !/(CVS|~)/ } readdir(DIR);
+	closedir(DIR);
+	printf "Adding files @newfiles\n";
+	@files = (@files, map { $_ = "$file/$_" } @newfiles);
+	next;
+    }
+}
+
+foreach $file (@files) {
+    if(-f $file) {
+	
+	print "Adding file $file\n";
+	
+	open(FILE, $file) || die "Could not open file $file\n";
+
+	$file =~ s-^-/-;
+	$fvar = $file;
+	$fvar =~ s-/-_-g;
+	$fvar =~ s-\.-_-g;
+	# for AVR, add PROGMEM here
+	print(OUTPUT "static const unsigned char data".$fvar."[] = {\n");
+	print(OUTPUT "\t/* $file */\n\t");
+	for($j = 0; $j < length($file); $j++) {
+	    printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1)));
+	}
+	printf(OUTPUT "0,\n");
+	
+	
+	$i = 0;        
+	while(read(FILE, $data, 1)) {
+	    if($i == 0) {
+		print(OUTPUT "\t");
+	    }
+	    printf(OUTPUT "%#02x, ", unpack("C", $data));
+	    $i++;
+	    if($i == 10) {
+		print(OUTPUT "\n");
+		$i = 0;
+	    }
+	}
+	print(OUTPUT "0};\n\n");
+	close(FILE);
+	push(@fvars, $fvar);
+	push(@pfiles, $file);
+    }
+}
+
+for($i = 0; $i < @fvars; $i++) {
+    $file = $pfiles[$i];
+    $fvar = $fvars[$i];
+
+    if($i == 0) {
+        $prevfile = "NULL";
+    } else {
+        $prevfile = "file" . $fvars[$i - 1];
+    }
+    print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, ");
+    print(OUTPUT "data$fvar + ". (length($file) + 1) .", ");
+    print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n");
+}
+
+print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n");
+print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n");
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/makestrings b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/makestrings
new file mode 100644
index 0000000..8a13c6d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/makestrings
@@ -0,0 +1,40 @@
+#!/usr/bin/perl
+
+
+sub stringify {
+  my $name = shift(@_);
+  open(OUTPUTC, "> $name.c");
+  open(OUTPUTH, "> $name.h");
+  
+  open(FILE, "$name");
+  
+  while() {
+    if(/(.+) "(.+)"/) {
+      $var = $1;
+      $data = $2;
+      
+      $datan = $data;
+      $datan =~ s/\\r/\r/g;
+      $datan =~ s/\\n/\n/g;
+      $datan =~ s/\\01/\01/g;      
+      $datan =~ s/\\0/\0/g;
+      
+      printf(OUTPUTC "const char $var\[%d] = \n", length($datan) + 1);
+      printf(OUTPUTC "/* \"$data\" */\n");
+      printf(OUTPUTC "{");
+      for($j = 0; $j < length($datan); $j++) {
+	printf(OUTPUTC "%#02x, ", unpack("C", substr($datan, $j, 1)));
+      }
+      printf(OUTPUTC "};\n");
+      
+      printf(OUTPUTH "extern const char $var\[%d];\n", length($datan) + 1);
+      
+    }
+  }
+  close(OUTPUTC);
+  close(OUTPUTH);
+}
+stringify("http-strings");
+
+exit 0;
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/webserver.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/webserver.h
new file mode 100644
index 0000000..1acb290
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/webserver.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2002, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $
+ *
+ */
+#ifndef __WEBSERVER_H__
+#define __WEBSERVER_H__
+
+#include "httpd.h"
+
+typedef struct httpd_state uip_tcp_appstate_t;
+/* UIP_APPCALL: the name of the application function. This function
+   must return void and take no arguments (i.e., C type "void
+   appfunc(void)"). */
+#ifndef UIP_APPCALL
+#define UIP_APPCALL     httpd_appcall
+#endif
+
+
+#endif /* __WEBSERVER_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip-1.0-changelog.txt b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip-1.0-changelog.txt
new file mode 100644
index 0000000..7a97704
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip-1.0-changelog.txt
@@ -0,0 +1,98 @@
+* A new API: protosockets that are similar to BSD sockets but does not
+  require any underlying multithreading system. 
+
+* Very rudimentary IPv6 support
+
+* New application: DHCP client. Web server rewritten with protosockets.
+
+* Removed uIP zero-copy functionality in order to simplify uIP device
+  driver coding: outbound packets are now *always* stored in full in
+  the uip_buf buffer.
+
+* Checksum computation is now part of uip.c, but it still is possible
+  to implement them in assembly code by specifying a configuration
+  option. Checksum code now runs on architectures with 2-byte alignment.
+  
+* Added TCP persistent timer.
+
+* Made all IP address representations use the new uip_ipaddr_ip
+  datatype for clarity.
+
+* Updated window behavior so that sending to a host with a small open
+  window works better now.
+
+* UDP API change: uip_udp_new() now takes port numbers in network byte
+  order like TCP functions.
+
+* Allow reception of packets when no IP address is configured to make
+  DHCP work.
+
+* Moved Ethernet address into main uIP module from ARP module.
+
+* Made constants explicit #defines and moved them out of the code
+  (header sizes, TCP options, TCP header length field). 
+
+* If uip_len is less than that reported by the IP header, the packet
+  is discarded. If uip_len is greater than the length reported by the
+  IP header, uip_len is adjusted.
+
+* Moved header size definitions into header file.
+
+* Added uIP call for polling an application without triggering any
+  timer events. Removed redundant assignments of uip_len and uip_slen.
+
+* Removed compiler warning about icmp_input label being defined when
+  UIP_PINGADDRCONF was not used.
+
+* Added UIP_APPDATA_SIZE macro that holds the available buffer size
+  for user data.
+
+* Added uip_udp_bind() call.
+
+* Moved checksum code into main uIP module.
+
+* Switched the TCP, UDP and IP header structures to be structs rather
+  than typedefs.
+
+* Prefixed TCP state names with UIP_ to avoid name space
+  contamination. 
+
+* Changed declarations of uip_appdatap and friends to void * to avoid
+  explicit typecasts. 
+
+* Bugfixes
+ 
+  o TCP: Fixed bug with high byte of peer window size.
+
+  o TCP: Fixed bug that in some cases prevented concurrent reception and
+    transmission of TCP data.
+
+  o TCP: uip_connect() didn't correctly calculate age of TIME_WAIT
+    connections.
+
+  o TCP: Array index for uip_conns[] array was out of bounds in
+    comparison. Comparison changed to make index within bounds.
+
+  o TCP: if the remote host crashes and tries to reestablish an old
+    connection, uIP should respond with an ACK with the correct
+    sequence and acknowledgment numbers, to which the remote host
+    should respond with an ACK. uIP did not respond with the correct
+    ACK.
+
+  o TCP: Fixed check for SYNACK segment: now checks only relevant TCP
+    control flags and discards flags reserved for future expansion.
+
+  o TCP: Fixed bug where uIP did not inform application that a connection
+    had been aborted during an active open.
+
+  o TCP: FIN segment was accepted even though application had stopped
+    incoming data with uip_stop().
+
+  o TCP: A FINACK segment would not always correctly acknowledge data.
+
+  o UDP: checksums are now calculated after all fields have been
+    filled in.
+
+  o UDP: network byte order on lastport in uip_udp_new().
+
+  o IP: memset() bugs in IP fragment reassembly code fixed.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/Makefile.include b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/Makefile.include
new file mode 100644
index 0000000..43ba247
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/Makefile.include
@@ -0,0 +1,47 @@
+
+
+ifdef APPS
+  APPDIRS = $(foreach APP, $(APPS), ../apps/$(APP))
+  -include $(foreach APP, $(APPS), ../apps/$(APP)/Makefile.$(APP))
+  CFLAGS += $(addprefix -I../apps/,$(APPS))
+endif
+
+ifndef CCDEP
+  CCDEP = $(CC)
+endif
+ifndef CCDEPCFLAGS
+  CCDEPCFLAGS = $(CFLAGS)
+endif
+ifndef OBJECTDIR
+  OBJECTDIR = obj
+endif
+
+ifeq (${wildcard $(OBJECTDIR)},)
+  DUMMY := ${shell mkdir $(OBJECTDIR)}
+endif
+
+
+vpath %.c . ../uip ../lib $(APPDIRS)
+
+$(OBJECTDIR)/%.o: %.c
+	$(CC) $(CFLAGS) -c $< -o $@
+
+$(OBJECTDIR)/%.d: %.c
+	@set -e; rm -f $@; \
+	$(CCDEP) -MM $(CCDEPCFLAGS) $< > $@.$$$$; \
+	sed 's,\($*\)\.o[ :]*,$(OBJECTDIR)/\1.o $@ : ,g' < $@.$$$$ > $@; \
+	rm -f $@.$$$$
+
+UIP_SOURCES=uip.c uip_arp.c uiplib.c psock.c timer.c uip-neighbor.c
+
+
+ifneq ($(MAKECMDGOALS),clean)
+-include $(addprefix $(OBJECTDIR)/,$(UIP_SOURCES:.c=.d) \
+                                   $(APP_SOURCES:.c=.d))
+endif
+
+uip.a: ${addprefix $(OBJECTDIR)/, $(UIP_SOURCES:.c=.o)}
+	$(AR) rcf $@ $^
+
+apps.a: ${addprefix $(OBJECTDIR)/, $(APP_SOURCES:.c=.o)}
+	$(AR) rcf $@ $^
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/clock.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/clock.h
new file mode 100644
index 0000000..dae6874
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/clock.h
@@ -0,0 +1,88 @@
+/**
+ * \defgroup clock Clock interface
+ *
+ * The clock interface is the interface between the \ref timer "timer library"
+ * and the platform specific clock functionality. The clock
+ * interface must be implemented for each platform that uses the \ref
+ * timer "timer library".
+ *
+ * The clock interface does only one this: it measures time. The clock
+ * interface provides a macro, CLOCK_SECOND, which corresponds to one
+ * second of system time.
+ *
+ * \sa \ref timer "Timer library"
+ *
+ * @{
+ */
+
+/*
+ * Copyright (c) 2004, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: clock.h,v 1.3 2006/06/11 21:46:39 adam Exp $
+ */
+#ifndef __CLOCK_H__
+#define __CLOCK_H__
+
+#include "clock-arch.h"
+
+/**
+ * Initialize the clock library.
+ *
+ * This function initializes the clock library and should be called
+ * from the main() function of the system.
+ *
+ */
+void clock_init(void);
+
+/**
+ * Get the current clock time.
+ *
+ * This function returns the current system clock time.
+ *
+ * \return The current clock time, measured in system ticks.
+ */
+clock_time_t clock_time(void);
+
+/**
+ * A second, measured in system clock time.
+ *
+ * \hideinitializer
+ */
+#ifdef CLOCK_CONF_SECOND
+#define CLOCK_SECOND CLOCK_CONF_SECOND
+#else
+#define CLOCK_SECOND (clock_time_t)32
+#endif
+
+#endif /* __CLOCK_H__ */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/lc-addrlabels.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/lc-addrlabels.h
new file mode 100644
index 0000000..9dff03d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/lc-addrlabels.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2004-2005, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: lc-addrlabels.h,v 1.3 2006/06/12 08:00:30 adam Exp $
+ */
+
+/**
+ * \addtogroup lc
+ * @{
+ */
+
+/**
+ * \file
+ * Implementation of local continuations based on the "Labels as
+ * values" feature of gcc
+ * \author
+ * Adam Dunkels 
+ *
+ * This implementation of local continuations is based on a special
+ * feature of the GCC C compiler called "labels as values". This
+ * feature allows assigning pointers with the address of the code
+ * corresponding to a particular C label.
+ *
+ * For more information, see the GCC documentation:
+ * http://gcc.gnu.org/onlinedocs/gcc/Labels-as-Values.html
+ *
+ * Thanks to dividuum for finding the nice local scope label
+ * implementation.
+ */
+
+#ifndef __LC_ADDRLABELS_H__
+#define __LC_ADDRLABELS_H__
+
+/** \hideinitializer */
+typedef void * lc_t;
+
+#define LC_INIT(s) s = NULL
+
+
+#define LC_RESUME(s)                            \
+  do {                                          \
+    if(s != NULL) {                             \
+      goto *s;                                  \
+    }                                           \
+  } while(0)
+
+#define LC_SET(s)                               \
+  do { ({ __label__ resume; resume: (s) = &&resume; }); }while(0)
+
+#define LC_END(s)
+
+#endif /* __LC_ADDRLABELS_H__ */
+
+/**  @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/lc-switch.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/lc-switch.h
new file mode 100644
index 0000000..17c8811
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/lc-switch.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2004-2005, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: lc-switch.h,v 1.2 2006/06/12 08:00:30 adam Exp $
+ */
+
+/**
+ * \addtogroup lc
+ * @{
+ */
+
+/**
+ * \file
+ * Implementation of local continuations based on switch() statment
+ * \author Adam Dunkels 
+ *
+ * This implementation of local continuations uses the C switch()
+ * statement to resume execution of a function somewhere inside the
+ * function's body. The implementation is based on the fact that
+ * switch() statements are able to jump directly into the bodies of
+ * control structures such as if() or while() statmenets.
+ *
+ * This implementation borrows heavily from Simon Tatham's coroutines
+ * implementation in C:
+ * http://www.chiark.greenend.org.uk/~sgtatham/coroutines.html
+ */
+
+#ifndef __LC_SWITCH_H__
+#define __LC_SWTICH_H__
+
+/* WARNING! lc implementation using switch() does not work if an
+   LC_SET() is done within another switch() statement! */
+
+/** \hideinitializer */
+typedef unsigned short lc_t;
+
+#define LC_INIT(s) s = 0;
+
+#define LC_RESUME(s) switch(s) { case 0:
+
+#define LC_SET(s) s = __LINE__; case __LINE__:
+
+#define LC_END(s) }
+
+#endif /* __LC_SWITCH_H__ */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/lc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/lc.h
new file mode 100644
index 0000000..3ad83cd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/lc.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2004-2005, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: lc.h,v 1.2 2006/06/12 08:00:30 adam Exp $
+ */
+
+/**
+ * \addtogroup pt
+ * @{
+ */
+
+/**
+ * \defgroup lc Local continuations
+ * @{
+ *
+ * Local continuations form the basis for implementing protothreads. A
+ * local continuation can be set in a specific function to
+ * capture the state of the function. After a local continuation has
+ * been set can be resumed in order to restore the state of the
+ * function at the point where the local continuation was set.
+ *
+ *
+ */
+
+/**
+ * \file lc.h
+ * Local continuations
+ * \author
+ * Adam Dunkels 
+ *
+ */
+
+#ifdef DOXYGEN
+/**
+ * Initialize a local continuation.
+ *
+ * This operation initializes the local continuation, thereby
+ * unsetting any previously set continuation state.
+ *
+ * \hideinitializer
+ */
+#define LC_INIT(lc)
+
+/**
+ * Set a local continuation.
+ *
+ * The set operation saves the state of the function at the point
+ * where the operation is executed. As far as the set operation is
+ * concerned, the state of the function does not include the
+ * call-stack or local (automatic) variables, but only the program
+ * counter and such CPU registers that needs to be saved.
+ *
+ * \hideinitializer
+ */
+#define LC_SET(lc)
+
+/**
+ * Resume a local continuation.
+ *
+ * The resume operation resumes a previously set local continuation, thus
+ * restoring the state in which the function was when the local
+ * continuation was set. If the local continuation has not been
+ * previously set, the resume operation does nothing.
+ *
+ * \hideinitializer
+ */
+#define LC_RESUME(lc)
+
+/**
+ * Mark the end of local continuation usage.
+ *
+ * The end operation signifies that local continuations should not be
+ * used any more in the function. This operation is not needed for
+ * most implementations of local continuation, but is required by a
+ * few implementations.
+ *
+ * \hideinitializer
+ */
+#define LC_END(lc)
+
+/**
+ * \var typedef lc_t;
+ *
+ * The local continuation type.
+ *
+ * \hideinitializer
+ */
+#endif /* DOXYGEN */
+
+#ifndef __LC_H__
+#define __LC_H__
+
+#ifdef LC_CONF_INCLUDE
+#include LC_CONF_INCLUDE
+#else
+#include "lc-switch.h"
+#endif /* LC_CONF_INCLUDE */
+
+#endif /* __LC_H__ */
+
+/** @} */
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/psock.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/psock.c
new file mode 100644
index 0000000..0c390d0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/psock.c
@@ -0,0 +1,339 @@
+/*
+ * Copyright (c) 2004, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: psock.c,v 1.2 2006/06/12 08:00:30 adam Exp $
+ */
+
+#include 
+#include 
+
+#include "uipopt.h"
+#include "psock.h"
+#include "uip.h"
+
+#define STATE_NONE 0
+#define STATE_ACKED 1
+#define STATE_READ 2
+#define STATE_BLOCKED_NEWDATA 3
+#define STATE_BLOCKED_CLOSE 4
+#define STATE_BLOCKED_SEND 5
+#define STATE_DATA_SENT 6
+
+/*
+ * Return value of the buffering functions that indicates that a
+ * buffer was not filled by incoming data.
+ *
+ */
+#define BUF_NOT_FULL 0
+#define BUF_NOT_FOUND 0
+
+/*
+ * Return value of the buffering functions that indicates that a
+ * buffer was completely filled by incoming data.
+ *
+ */
+#define BUF_FULL 1
+
+/*
+ * Return value of the buffering functions that indicates that an
+ * end-marker byte was found.
+ *
+ */
+#define BUF_FOUND 2
+
+/*---------------------------------------------------------------------------*/
+static void
+buf_setup(struct psock_buf *buf,
+	  u8_t *bufptr, u16_t bufsize)
+{
+  buf->ptr = bufptr;
+  buf->left = bufsize;
+}
+/*---------------------------------------------------------------------------*/
+static u8_t
+buf_bufdata(struct psock_buf *buf, u16_t len,
+	    u8_t **dataptr, u16_t *datalen)
+{
+  ( void ) len;
+  if(*datalen < buf->left) {
+    memcpy(buf->ptr, *dataptr, *datalen);
+    buf->ptr += *datalen;
+    buf->left -= *datalen;
+    *dataptr += *datalen;
+    *datalen = 0;
+    return BUF_NOT_FULL;
+  } else if(*datalen == buf->left) {
+    memcpy(buf->ptr, *dataptr, *datalen);
+    buf->ptr += *datalen;
+    buf->left = 0;
+    *dataptr += *datalen;
+    *datalen = 0;
+    return BUF_FULL;
+  } else {
+    memcpy(buf->ptr, *dataptr, buf->left);
+    buf->ptr += buf->left;
+    *datalen -= buf->left;
+    *dataptr += buf->left;
+    buf->left = 0;
+    return BUF_FULL;
+  }
+}
+/*---------------------------------------------------------------------------*/
+static u8_t
+buf_bufto(register struct psock_buf *buf, u8_t endmarker,
+	  register u8_t **dataptr, register u16_t *datalen)
+{
+  u8_t c;
+  while(buf->left > 0 && *datalen > 0) {
+    c = *buf->ptr = **dataptr;
+    ++*dataptr;
+    ++buf->ptr;
+    --*datalen;
+    --buf->left;
+    
+    if(c == endmarker) {
+      return BUF_FOUND;
+    }
+  }
+
+  if(*datalen == 0) {
+    return BUF_NOT_FOUND;
+  }
+
+  while(*datalen > 0) {
+    c = **dataptr;
+    --*datalen;
+    ++*dataptr;
+    
+    if(c == endmarker) {
+      return BUF_FOUND | BUF_FULL;
+    }
+  }
+  
+  return BUF_FULL;
+}
+/*---------------------------------------------------------------------------*/
+static char
+send_data(register struct psock *s)
+{
+  if(s->state != STATE_DATA_SENT || uip_rexmit()) {
+    if(s->sendlen > uip_mss()) {
+      uip_send(s->sendptr, uip_mss());
+    } else {
+      uip_send(s->sendptr, s->sendlen);
+    }
+    s->state = STATE_DATA_SENT;
+    return 1;
+  }
+  return 0;
+}
+/*---------------------------------------------------------------------------*/
+static char
+data_acked(register struct psock *s)
+{
+  if(s->state == STATE_DATA_SENT && uip_acked()) {
+    if(s->sendlen > uip_mss()) {
+      s->sendlen -= uip_mss();
+      s->sendptr += uip_mss();
+    } else {
+      s->sendptr += s->sendlen;
+      s->sendlen = 0;
+    }
+    s->state = STATE_ACKED;
+    return 1;
+  }
+  return 0;
+}
+/*---------------------------------------------------------------------------*/
+PT_THREAD(psock_send(register struct psock *s, const char *buf,
+		     unsigned int len))
+{
+  PT_BEGIN(&s->psockpt);
+
+  /* If there is no data to send, we exit immediately. */
+  if(len == 0) {
+    PT_EXIT(&s->psockpt);
+  }
+
+  /* Save the length of and a pointer to the data that is to be
+     sent. */
+  s->sendptr = (unsigned char*)buf;
+  s->sendlen = len;
+
+  s->state = STATE_NONE;
+
+  /* We loop here until all data is sent. The s->sendlen variable is
+     updated by the data_sent() function. */
+  while(s->sendlen > 0) {
+
+    /*
+     * The condition for this PT_WAIT_UNTIL is a little tricky: the
+     * protothread will wait here until all data has been acknowledged
+     * (data_acked() returns true) and until all data has been sent
+     * (send_data() returns true). The two functions data_acked() and
+     * send_data() must be called in succession to ensure that all
+     * data is sent. Therefore the & operator is used instead of the
+     * && operator, which would cause only the data_acked() function
+     * to be called when it returns false.
+     */
+    PT_WAIT_UNTIL(&s->psockpt, data_acked(s) & send_data(s));
+  }
+
+  s->state = STATE_NONE;
+  
+  PT_END(&s->psockpt);
+}
+/*---------------------------------------------------------------------------*/
+PT_THREAD(psock_generator_send(register struct psock *s,
+			       unsigned short (*generate)(void *), void *arg))
+{
+  PT_BEGIN(&s->psockpt);
+
+  /* Ensure that there is a generator function to call. */
+  if(generate == NULL) {
+    PT_EXIT(&s->psockpt);
+  }
+
+  /* Call the generator function to generate the data in the
+     uip_appdata buffer. */
+  s->sendlen = generate(arg);
+  s->sendptr = uip_appdata;
+
+  s->state = STATE_NONE;  
+  do {
+    /* Call the generator function again if we are called to perform a
+       retransmission. */
+    if(uip_rexmit()) {
+      generate(arg);
+    }
+    /* Wait until all data is sent and acknowledged. */
+    PT_WAIT_UNTIL(&s->psockpt, data_acked(s) & send_data(s));
+  } while(s->sendlen > 0);
+  
+  s->state = STATE_NONE;
+  
+  PT_END(&s->psockpt);
+}
+/*---------------------------------------------------------------------------*/
+u16_t
+psock_datalen(struct psock *psock)
+{
+  return psock->bufsize - psock->buf.left;
+}
+/*---------------------------------------------------------------------------*/
+char
+psock_newdata(struct psock *s)
+{
+  if(s->readlen > 0) {
+    /* There is data in the uip_appdata buffer that has not yet been
+       read with the PSOCK_READ functions. */
+    return 1;
+  } else if(s->state == STATE_READ) {
+    /* All data in uip_appdata buffer already consumed. */
+    s->state = STATE_BLOCKED_NEWDATA;
+    return 0;
+  } else if(uip_newdata()) {
+    /* There is new data that has not been consumed. */
+    return 1;
+  } else {
+    /* There is no new data. */
+    return 0;
+  }
+}
+/*---------------------------------------------------------------------------*/
+PT_THREAD(psock_readto(register struct psock *psock, unsigned char c))
+{
+  PT_BEGIN(&psock->psockpt);
+
+  buf_setup(&psock->buf, (unsigned char*)psock->bufptr, psock->bufsize);
+  
+  /* XXX: Should add buf_checkmarker() before do{} loop, if
+     incoming data has been handled while waiting for a write. */
+
+  do {
+    if(psock->readlen == 0) {
+      PT_WAIT_UNTIL(&psock->psockpt, psock_newdata(psock));
+      psock->state = STATE_READ;
+      psock->readptr = (u8_t *)uip_appdata;
+      psock->readlen = uip_datalen();
+    }
+  } while((buf_bufto(&psock->buf, c,
+		     &psock->readptr,
+		     &psock->readlen) & BUF_FOUND) == 0);
+  
+  if(psock_datalen(psock) == 0) {
+    psock->state = STATE_NONE;
+    PT_RESTART(&psock->psockpt);
+  }
+  PT_END(&psock->psockpt);
+}
+/*---------------------------------------------------------------------------*/
+PT_THREAD(psock_readbuf(register struct psock *psock))
+{
+  PT_BEGIN(&psock->psockpt);
+
+  buf_setup(&psock->buf, (unsigned char * ) psock->bufptr, psock->bufsize);
+  
+  /* XXX: Should add buf_checkmarker() before do{} loop, if
+     incoming data has been handled while waiting for a write. */
+
+  do {
+    if(psock->readlen == 0) {
+      PT_WAIT_UNTIL(&psock->psockpt, psock_newdata(psock));
+      printf("Waited for newdata\n");
+      psock->state = STATE_READ;
+      psock->readptr = (u8_t *)uip_appdata;
+      psock->readlen = uip_datalen();
+    }
+  } while(buf_bufdata(&psock->buf, psock->bufsize,
+			 &psock->readptr,
+			 &psock->readlen) != BUF_FULL);
+
+  if(psock_datalen(psock) == 0) {
+    psock->state = STATE_NONE;
+    PT_RESTART(&psock->psockpt);
+  }
+  PT_END(&psock->psockpt);
+}
+/*---------------------------------------------------------------------------*/
+void
+psock_init(register struct psock *psock, char *buffer, unsigned int buffersize)
+{
+  psock->state = STATE_NONE;
+  psock->readlen = 0;
+  psock->bufptr = buffer;
+  psock->bufsize = buffersize;
+  buf_setup(&psock->buf, (unsigned char*) buffer, buffersize);
+  PT_INIT(&psock->pt);
+  PT_INIT(&psock->psockpt);
+}
+/*---------------------------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/psock.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/psock.h
new file mode 100644
index 0000000..8d41258
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/psock.h
@@ -0,0 +1,380 @@
+/*
+ * Copyright (c) 2004, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: psock.h,v 1.3 2006/06/12 08:00:30 adam Exp $
+ */
+
+/**
+ * \defgroup psock Protosockets library
+ * @{
+ *
+ * The protosocket library provides an interface to the uIP stack that is
+ * similar to the traditional BSD socket interface. Unlike programs
+ * written for the ordinary uIP event-driven interface, programs
+ * written with the protosocket library are executed in a sequential
+ * fashion and does not have to be implemented as explicit state
+ * machines.
+ *
+ * Protosockets only work with TCP connections.
+ *
+ * The protosocket library uses \ref pt protothreads to provide
+ * sequential control flow. This makes the protosockets lightweight in
+ * terms of memory, but also means that protosockets inherits the
+ * functional limitations of protothreads. Each protosocket lives only
+ * within a single function. Automatic variables (stack variables) are
+ * not retained across a protosocket library function call.
+ *
+ * \note Because the protosocket library uses protothreads, local
+ * variables will not always be saved across a call to a protosocket
+ * library function. It is therefore advised that local variables are
+ * used with extreme care.
+ *
+ * The protosocket library provides functions for sending data without
+ * having to deal with retransmissions and acknowledgements, as well
+ * as functions for reading data without having to deal with data
+ * being split across more than one TCP segment.
+ *
+ * Because each protosocket runs as a protothread, the protosocket has to be
+ * started with a call to PSOCK_BEGIN() at the start of the function
+ * in which the protosocket is used. Similarly, the protosocket protothread can
+ * be terminated by a call to PSOCK_EXIT().
+ *
+ */
+
+/**
+ * \file
+ * Protosocket library header file
+ * \author
+ * Adam Dunkels 
+ *
+ */
+
+#ifndef __PSOCK_H__
+#define __PSOCK_H__
+
+#include "uipopt.h"
+#include "pt.h"
+
+ /*
+ * The structure that holds the state of a buffer.
+ *
+ * This structure holds the state of a uIP buffer. The structure has
+ * no user-visible elements, but is used through the functions
+ * provided by the library.
+ *
+ */
+struct psock_buf {
+  u8_t *ptr;
+  unsigned short left;
+};
+
+/**
+ * The representation of a protosocket.
+ *
+ * The protosocket structrure is an opaque structure with no user-visible
+ * elements.
+ */
+struct psock {
+  struct pt pt, psockpt; /* Protothreads - one that's using the psock
+			    functions, and one that runs inside the
+			    psock functions. */
+  const u8_t *sendptr;   /* Pointer to the next data to be sent. */
+  u8_t *readptr;         /* Pointer to the next data to be read. */
+  
+  char *bufptr;          /* Pointer to the buffer used for buffering
+			    incoming data. */
+  
+  u16_t sendlen;         /* The number of bytes left to be sent. */
+  u16_t readlen;         /* The number of bytes left to be read. */
+
+  struct psock_buf buf;  /* The structure holding the state of the
+			    input buffer. */
+  unsigned int bufsize;  /* The size of the input buffer. */
+  
+  unsigned char state;   /* The state of the protosocket. */
+};
+
+void psock_init(struct psock *psock, char *buffer, unsigned int buffersize);
+/**
+ * Initialize a protosocket.
+ *
+ * This macro initializes a protosocket and must be called before the
+ * protosocket is used. The initialization also specifies the input buffer
+ * for the protosocket.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket to be
+ * initialized
+ *
+ * \param buffer (char *) A pointer to the input buffer for the
+ * protosocket.
+ *
+ * \param buffersize (unsigned int) The size of the input buffer.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_INIT(psock, buffer, buffersize) \
+  psock_init(psock, buffer, buffersize)
+
+/**
+ * Start the protosocket protothread in a function.
+ *
+ * This macro starts the protothread associated with the protosocket and
+ * must come before other protosocket calls in the function it is used.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket to be
+ * started.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_BEGIN(psock) PT_BEGIN(&((psock)->pt))
+
+PT_THREAD(psock_send(struct psock *psock, const char *buf, unsigned int len));
+/**
+ * Send data.
+ *
+ * This macro sends data over a protosocket. The protosocket protothread blocks
+ * until all data has been sent and is known to have been received by
+ * the remote end of the TCP connection.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket over which
+ * data is to be sent.
+ *
+ * \param data (char *) A pointer to the data that is to be sent.
+ *
+ * \param datalen (unsigned int) The length of the data that is to be
+ * sent.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_SEND(psock, data, datalen)		\
+    PT_WAIT_THREAD(&((psock)->pt), psock_send(psock, data, datalen))
+
+/**
+ * \brief      Send a null-terminated string.
+ * \param psock Pointer to the protosocket.
+ * \param str  The string to be sent.
+ *
+ *             This function sends a null-terminated string over the
+ *             protosocket.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_SEND_STR(psock, str)      		\
+    PT_WAIT_THREAD(&((psock)->pt), psock_send(psock, str, strlen(str)))
+
+PT_THREAD(psock_generator_send(struct psock *psock,
+				unsigned short (*f)(void *), void *arg));
+
+/**
+ * \brief      Generate data with a function and send it
+ * \param psock Pointer to the protosocket.
+ * \param generator Pointer to the generator function
+ * \param arg   Argument to the generator function
+ *
+ *             This function generates data and sends it over the
+ *             protosocket. This can be used to dynamically generate
+ *             data for a transmission, instead of generating the data
+ *             in a buffer beforehand. This function reduces the need for
+ *             buffer memory. The generator function is implemented by
+ *             the application, and a pointer to the function is given
+ *             as an argument with the call to PSOCK_GENERATOR_SEND().
+ *
+ *             The generator function should place the generated data
+ *             directly in the uip_appdata buffer, and return the
+ *             length of the generated data. The generator function is
+ *             called by the protosocket layer when the data first is
+ *             sent, and once for every retransmission that is needed.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_GENERATOR_SEND(psock, generator, arg)     \
+    PT_WAIT_THREAD(&((psock)->pt),					\
+		   psock_generator_send(psock, generator, arg))
+
+
+/**
+ * Close a protosocket.
+ *
+ * This macro closes a protosocket and can only be called from within the
+ * protothread in which the protosocket lives.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket that is to
+ * be closed.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_CLOSE(psock) uip_close()
+
+PT_THREAD(psock_readbuf(struct psock *psock));
+/**
+ * Read data until the buffer is full.
+ *
+ * This macro will block waiting for data and read the data into the
+ * input buffer specified with the call to PSOCK_INIT(). Data is read
+ * until the buffer is full..
+ *
+ * \param psock (struct psock *) A pointer to the protosocket from which
+ * data should be read.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_READBUF(psock)				\
+  PT_WAIT_THREAD(&((psock)->pt), psock_readbuf(psock))
+
+PT_THREAD(psock_readto(struct psock *psock, unsigned char c));
+/**
+ * Read data up to a specified character.
+ *
+ * This macro will block waiting for data and read the data into the
+ * input buffer specified with the call to PSOCK_INIT(). Data is only
+ * read until the specifieed character appears in the data stream.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket from which
+ * data should be read.
+ *
+ * \param c (char) The character at which to stop reading.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_READTO(psock, c)				\
+  PT_WAIT_THREAD(&((psock)->pt), psock_readto(psock, c))
+
+/**
+ * The length of the data that was previously read.
+ *
+ * This macro returns the length of the data that was previously read
+ * using PSOCK_READTO() or PSOCK_READ().
+ *
+ * \param psock (struct psock *) A pointer to the protosocket holding the data.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_DATALEN(psock) psock_datalen(psock)
+
+u16_t psock_datalen(struct psock *psock);
+
+/**
+ * Exit the protosocket's protothread.
+ *
+ * This macro terminates the protothread of the protosocket and should
+ * almost always be used in conjunction with PSOCK_CLOSE().
+ *
+ * \sa PSOCK_CLOSE_EXIT()
+ *
+ * \param psock (struct psock *) A pointer to the protosocket.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_EXIT(psock) PT_EXIT(&((psock)->pt))
+
+/**
+ * Close a protosocket and exit the protosocket's protothread.
+ *
+ * This macro closes a protosocket and exits the protosocket's protothread.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_CLOSE_EXIT(psock)		\
+  do {						\
+    PSOCK_CLOSE(psock);			\
+    PSOCK_EXIT(psock);			\
+  } while(0)
+
+/**
+ * Declare the end of a protosocket's protothread.
+ *
+ * This macro is used for declaring that the protosocket's protothread
+ * ends. It must always be used together with a matching PSOCK_BEGIN()
+ * macro.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_END(psock) PT_END(&((psock)->pt))
+
+char psock_newdata(struct psock *s);
+
+/**
+ * Check if new data has arrived on a protosocket.
+ *
+ * This macro is used in conjunction with the PSOCK_WAIT_UNTIL()
+ * macro to check if data has arrived on a protosocket.
+ *
+ * \param psock (struct psock *) A pointer to the protosocket.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_NEWDATA(psock) psock_newdata(psock)
+
+/**
+ * Wait until a condition is true.
+ *
+ * This macro blocks the protothread until the specified condition is
+ * true. The macro PSOCK_NEWDATA() can be used to check if new data
+ * arrives when the protosocket is waiting.
+ *
+ * Typically, this macro is used as follows:
+ *
+ \code
+ PT_THREAD(thread(struct psock *s, struct timer *t))
+ {
+   PSOCK_BEGIN(s);
+
+   PSOCK_WAIT_UNTIL(s, PSOCK_NEWADATA(s) || timer_expired(t));
+   
+   if(PSOCK_NEWDATA(s)) {
+     PSOCK_READTO(s, '\n');
+   } else {
+     handle_timed_out(s);
+   }
+   
+   PSOCK_END(s);
+ }
+ \endcode
+ *
+ * \param psock (struct psock *) A pointer to the protosocket.
+ * \param condition The condition to wait for.
+ *
+ * \hideinitializer
+ */
+#define PSOCK_WAIT_UNTIL(psock, condition)    \
+  PT_WAIT_UNTIL(&((psock)->pt), (condition));
+
+#define PSOCK_WAIT_THREAD(psock, condition)   \
+  PT_WAIT_THREAD(&((psock)->pt), (condition))
+
+#endif /* __PSOCK_H__ */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/pt.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/pt.h
new file mode 100644
index 0000000..00ddd44
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/pt.h
@@ -0,0 +1,323 @@
+/*
+ * Copyright (c) 2004-2005, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: pt.h,v 1.2 2006/06/12 08:00:30 adam Exp $
+ */
+
+/**
+ * \addtogroup pt
+ * @{
+ */
+
+/**
+ * \file
+ * Protothreads implementation.
+ * \author
+ * Adam Dunkels 
+ *
+ */
+
+#ifndef __PT_H__
+#define __PT_H__
+
+#include "lc.h"
+
+struct pt {
+  lc_t lc;
+};
+
+#define PT_WAITING 0
+#define PT_EXITED  1
+#define PT_ENDED   2
+#define PT_YIELDED 3
+
+/**
+ * \name Initialization
+ * @{
+ */
+
+/**
+ * Initialize a protothread.
+ *
+ * Initializes a protothread. Initialization must be done prior to
+ * starting to execute the protothread.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \sa PT_SPAWN()
+ *
+ * \hideinitializer
+ */
+#define PT_INIT(pt)   LC_INIT((pt)->lc)
+
+/** @} */
+
+/**
+ * \name Declaration and definition
+ * @{
+ */
+
+/**
+ * Declaration of a protothread.
+ *
+ * This macro is used to declare a protothread. All protothreads must
+ * be declared with this macro.
+ *
+ * \param name_args The name and arguments of the C function
+ * implementing the protothread.
+ *
+ * \hideinitializer
+ */
+#define PT_THREAD(name_args) char name_args
+
+/**
+ * Declare the start of a protothread inside the C function
+ * implementing the protothread.
+ *
+ * This macro is used to declare the starting point of a
+ * protothread. It should be placed at the start of the function in
+ * which the protothread runs. All C statements above the PT_BEGIN()
+ * invokation will be executed each time the protothread is scheduled.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \hideinitializer
+ */
+#define PT_BEGIN(pt) { char PT_YIELD_FLAG = 1; LC_RESUME((pt)->lc)
+
+/**
+ * Declare the end of a protothread.
+ *
+ * This macro is used for declaring that a protothread ends. It must
+ * always be used together with a matching PT_BEGIN() macro.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \hideinitializer
+ */
+#define PT_END(pt) LC_END((pt)->lc); PT_YIELD_FLAG = 0; \
+                   PT_INIT(pt); return PT_ENDED; }
+
+/** @} */
+
+/**
+ * \name Blocked wait
+ * @{
+ */
+
+/**
+ * Block and wait until condition is true.
+ *
+ * This macro blocks the protothread until the specified condition is
+ * true.
+ *
+ * \param pt A pointer to the protothread control structure.
+ * \param condition The condition.
+ *
+ * \hideinitializer
+ */
+#define PT_WAIT_UNTIL(pt, condition)	        \
+  do {						\
+    LC_SET((pt)->lc);				\
+    if(!(condition)) {				\
+      return PT_WAITING;			\
+    }						\
+  } while(0)
+
+/**
+ * Block and wait while condition is true.
+ *
+ * This function blocks and waits while condition is true. See
+ * PT_WAIT_UNTIL().
+ *
+ * \param pt A pointer to the protothread control structure.
+ * \param cond The condition.
+ *
+ * \hideinitializer
+ */
+#define PT_WAIT_WHILE(pt, cond)  PT_WAIT_UNTIL((pt), !(cond))
+
+/** @} */
+
+/**
+ * \name Hierarchical protothreads
+ * @{
+ */
+
+/**
+ * Block and wait until a child protothread completes.
+ *
+ * This macro schedules a child protothread. The current protothread
+ * will block until the child protothread completes.
+ *
+ * \note The child protothread must be manually initialized with the
+ * PT_INIT() function before this function is used.
+ *
+ * \param pt A pointer to the protothread control structure.
+ * \param thread The child protothread with arguments
+ *
+ * \sa PT_SPAWN()
+ *
+ * \hideinitializer
+ */
+#define PT_WAIT_THREAD(pt, thread) PT_WAIT_WHILE((pt), PT_SCHEDULE(thread))
+
+/**
+ * Spawn a child protothread and wait until it exits.
+ *
+ * This macro spawns a child protothread and waits until it exits. The
+ * macro can only be used within a protothread.
+ *
+ * \param pt A pointer to the protothread control structure.
+ * \param child A pointer to the child protothread's control structure.
+ * \param thread The child protothread with arguments
+ *
+ * \hideinitializer
+ */
+#define PT_SPAWN(pt, child, thread)		\
+  do {						\
+    PT_INIT((child));				\
+    PT_WAIT_THREAD((pt), (thread));		\
+  } while(0)
+
+/** @} */
+
+/**
+ * \name Exiting and restarting
+ * @{
+ */
+
+/**
+ * Restart the protothread.
+ *
+ * This macro will block and cause the running protothread to restart
+ * its execution at the place of the PT_BEGIN() call.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \hideinitializer
+ */
+#define PT_RESTART(pt)				\
+  do {						\
+    PT_INIT(pt);				\
+    return PT_WAITING;			\
+  } while(0)
+
+/**
+ * Exit the protothread.
+ *
+ * This macro causes the protothread to exit. If the protothread was
+ * spawned by another protothread, the parent protothread will become
+ * unblocked and can continue to run.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \hideinitializer
+ */
+#define PT_EXIT(pt)				\
+  do {						\
+    PT_INIT(pt);				\
+    return PT_EXITED;			\
+  } while(0)
+
+/** @} */
+
+/**
+ * \name Calling a protothread
+ * @{
+ */
+
+/**
+ * Schedule a protothread.
+ *
+ * This function shedules a protothread. The return value of the
+ * function is non-zero if the protothread is running or zero if the
+ * protothread has exited.
+ *
+ * \param f The call to the C function implementing the protothread to
+ * be scheduled
+ *
+ * \hideinitializer
+ */
+#define PT_SCHEDULE(f) ((f) == PT_WAITING)
+
+/** @} */
+
+/**
+ * \name Yielding from a protothread
+ * @{
+ */
+
+/**
+ * Yield from the current protothread.
+ *
+ * This function will yield the protothread, thereby allowing other
+ * processing to take place in the system.
+ *
+ * \param pt A pointer to the protothread control structure.
+ *
+ * \hideinitializer
+ */
+#define PT_YIELD(pt)				\
+  do {						\
+    PT_YIELD_FLAG = 0;				\
+    LC_SET((pt)->lc);				\
+    if(PT_YIELD_FLAG == 0) {			\
+      return PT_YIELDED;			\
+    }						\
+  } while(0)
+
+/**
+ * \brief      Yield from the protothread until a condition occurs.
+ * \param pt   A pointer to the protothread control structure.
+ * \param cond The condition.
+ *
+ *             This function will yield the protothread, until the
+ *             specified condition evaluates to true.
+ *
+ *
+ * \hideinitializer
+ */
+#define PT_YIELD_UNTIL(pt, cond)		\
+  do {						\
+    PT_YIELD_FLAG = 0;				\
+    LC_SET((pt)->lc);				\
+    if((PT_YIELD_FLAG == 0) || !(cond)) {	\
+      return PT_YIELDED;			\
+    }						\
+  } while(0)
+
+/** @} */
+
+#endif /* __PT_H__ */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/timer.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/timer.c
new file mode 100644
index 0000000..8c270b2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/timer.c
@@ -0,0 +1,127 @@
+/**
+ * \addtogroup timer
+ * @{
+ */
+
+/**
+ * \file
+ * Timer library implementation.
+ * \author
+ * Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2004, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: timer.c,v 1.2 2006/06/12 08:00:30 adam Exp $
+ */
+
+#include "clock.h"
+#include "timer.h"
+
+/*---------------------------------------------------------------------------*/
+/**
+ * Set a timer.
+ *
+ * This function is used to set a timer for a time sometime in the
+ * future. The function timer_expired() will evaluate to true after
+ * the timer has expired.
+ *
+ * \param t A pointer to the timer
+ * \param interval The interval before the timer expires.
+ *
+ */
+void
+timer_set(struct timer *t, clock_time_t interval)
+{
+  t->interval = interval;
+  t->start = clock_time();
+}
+/*---------------------------------------------------------------------------*/
+/**
+ * Reset the timer with the same interval.
+ *
+ * This function resets the timer with the same interval that was
+ * given to the timer_set() function. The start point of the interval
+ * is the exact time that the timer last expired. Therefore, this
+ * function will cause the timer to be stable over time, unlike the
+ * timer_rester() function.
+ *
+ * \param t A pointer to the timer.
+ *
+ * \sa timer_restart()
+ */
+void
+timer_reset(struct timer *t)
+{
+  t->start += t->interval;
+}
+/*---------------------------------------------------------------------------*/
+/**
+ * Restart the timer from the current point in time
+ *
+ * This function restarts a timer with the same interval that was
+ * given to the timer_set() function. The timer will start at the
+ * current time.
+ *
+ * \note A periodic timer will drift if this function is used to reset
+ * it. For preioric timers, use the timer_reset() function instead.
+ *
+ * \param t A pointer to the timer.
+ *
+ * \sa timer_reset()
+ */
+void
+timer_restart(struct timer *t)
+{
+  t->start = clock_time();
+}
+/*---------------------------------------------------------------------------*/
+/**
+ * Check if a timer has expired.
+ *
+ * This function tests if a timer has expired and returns true or
+ * false depending on its status.
+ *
+ * \param t A pointer to the timer
+ *
+ * \return Non-zero if the timer has expired, zero otherwise.
+ *
+ */
+int
+timer_expired(struct timer *t)
+{
+  return (clock_time_t)(clock_time() - t->start) >= (clock_time_t)t->interval;
+}
+/*---------------------------------------------------------------------------*/
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/timer.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/timer.h
new file mode 100644
index 0000000..e28e3ca
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/timer.h
@@ -0,0 +1,86 @@
+/**
+ * \defgroup timer Timer library
+ *
+ * The timer library provides functions for setting, resetting and
+ * restarting timers, and for checking if a timer has expired. An
+ * application must "manually" check if its timers have expired; this
+ * is not done automatically.
+ *
+ * A timer is declared as a \c struct \c timer and all access to the
+ * timer is made by a pointer to the declared timer.
+ *
+ * \note The timer library uses the \ref clock "Clock library" to
+ * measure time. Intervals should be specified in the format used by
+ * the clock library.
+ *
+ * @{
+ */
+
+
+/**
+ * \file
+ * Timer library header file.
+ * \author
+ * Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2004, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: timer.h,v 1.3 2006/06/11 21:46:39 adam Exp $
+ */
+#ifndef __TIMER_H__
+#define __TIMER_H__
+
+#include "clock.h"
+
+/**
+ * A timer.
+ *
+ * This structure is used for declaring a timer. The timer must be set
+ * with timer_set() before it can be used.
+ *
+ * \hideinitializer
+ */
+struct timer {
+  clock_time_t start;
+  clock_time_t interval;
+};
+
+void timer_set(struct timer *t, clock_time_t interval);
+void timer_reset(struct timer *t);
+void timer_restart(struct timer *t);
+int timer_expired(struct timer *t);
+
+#endif /* __TIMER_H__ */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-fw.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-fw.c
new file mode 100644
index 0000000..2a85a6d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-fw.c
@@ -0,0 +1,532 @@
+/*
+ * Copyright (c) 2004, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: uip-fw.c,v 1.2 2006/06/12 08:00:30 adam Exp $
+ */
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \defgroup uipfw uIP packet forwarding
+ * @{
+ *
+ */
+
+/**
+ * \file
+ * uIP packet forwarding.
+ * \author Adam Dunkels 
+ *
+ * This file implements a number of simple functions which do packet
+ * forwarding over multiple network interfaces with uIP.
+ *
+ */
+
+#include "uip.h"
+#include "uip_arch.h"
+#include "uip-fw.h"
+
+#include  /* for memcpy() */
+
+/*
+ * The list of registered network interfaces.
+ */
+static struct uip_fw_netif *netifs = NULL;
+
+/*
+ * A pointer to the default network interface.
+ */
+static struct uip_fw_netif *defaultnetif = NULL;
+
+struct tcpip_hdr {
+  /* IP header. */
+  u8_t vhl,
+    tos;
+  u16_t len,
+    ipid,
+    ipoffset;
+  u8_t ttl,
+    proto;
+  u16_t ipchksum;
+  u16_t srcipaddr[2],
+    destipaddr[2];
+  
+  /* TCP header. */
+  u16_t srcport,
+    destport;
+  u8_t seqno[4],
+    ackno[4],
+    tcpoffset,
+    flags,
+    wnd[2];
+  u16_t tcpchksum;
+  u8_t urgp[2];
+  u8_t optdata[4];
+} PACK_STRUCT_END;
+
+struct icmpip_hdr {
+  /* IP header. */
+  u8_t vhl,
+    tos,
+    len[2],
+    ipid[2],
+    ipoffset[2],
+    ttl,
+    proto;
+  u16_t ipchksum;
+  u16_t srcipaddr[2],
+    destipaddr[2];
+  /* ICMP (echo) header. */
+  u8_t type, icode;
+  u16_t icmpchksum;
+  u16_t id, seqno;
+  u8_t payload[1];
+} PACK_STRUCT_END;
+
+/* ICMP ECHO. */
+#define ICMP_ECHO 8
+
+/* ICMP TIME-EXCEEDED. */
+#define ICMP_TE 11
+
+/*
+ * Pointer to the TCP/IP headers of the packet in the uip_buf buffer.
+ */
+#define BUF ((struct tcpip_hdr *)&uip_buf[UIP_LLH_LEN])
+
+/*
+ * Pointer to the ICMP/IP headers of the packet in the uip_buf buffer.
+ */
+#define ICMPBUF ((struct icmpip_hdr *)&uip_buf[UIP_LLH_LEN])
+
+/*
+ * Certain fields of an IP packet that are used for identifying
+ * duplicate packets.
+ */
+struct fwcache_entry {
+  u16_t timer;
+  
+  u16_t srcipaddr[2];
+  u16_t destipaddr[2];
+  u16_t ipid;
+  u8_t proto;
+  u8_t unused;
+
+#if notdef
+  u16_t payload[2];
+#endif
+
+#if UIP_REASSEMBLY > 0
+  u16_t len, offset;
+#endif
+};
+
+/*
+ * The number of packets to remember when looking for duplicates.
+ */
+#ifdef UIP_CONF_FWCACHE_SIZE
+#define FWCACHE_SIZE UIP_CONF_FWCACHE_SIZE
+#else
+#define FWCACHE_SIZE 2
+#endif
+
+
+/*
+ * A cache of packet header fields which are used for
+ * identifying duplicate packets.
+ */
+static struct fwcache_entry fwcache[FWCACHE_SIZE];
+
+/**
+ * \internal
+ * The time that a packet cache is active.
+ */
+#define FW_TIME 20
+
+/*------------------------------------------------------------------------------*/
+/**
+ * Initialize the uIP packet forwarding module.
+ */
+/*------------------------------------------------------------------------------*/
+void
+uip_fw_init(void)
+{
+  struct uip_fw_netif *t;
+  defaultnetif = NULL;
+  while(netifs != NULL) {
+    t = netifs;
+    netifs = netifs->next;
+    t->next = NULL;
+  }
+}
+/*------------------------------------------------------------------------------*/
+/**
+ * \internal
+ * Check if an IP address is within the network defined by an IP
+ * address and a netmask.
+ *
+ * \param ipaddr The IP address to be checked.
+ * \param netipaddr The IP address of the network.
+ * \param netmask The netmask of the network.
+ *
+ * \return Non-zero if IP address is in network, zero otherwise.
+ */
+/*------------------------------------------------------------------------------*/
+static unsigned char
+ipaddr_maskcmp(u16_t *ipaddr, u16_t *netipaddr, u16_t *netmask)
+{
+  return (ipaddr[0] & netmask [0]) == (netipaddr[0] & netmask[0]) &&
+    (ipaddr[1] & netmask[1]) == (netipaddr[1] & netmask[1]);
+}
+/*------------------------------------------------------------------------------*/
+/**
+ * \internal
+ * Send out an ICMP TIME-EXCEEDED message.
+ *
+ * This function replaces the packet in the uip_buf buffer with the
+ * ICMP packet.
+ */
+/*------------------------------------------------------------------------------*/
+static void
+time_exceeded(void)
+{
+  u16_t tmp16;
+
+  /* We don't send out ICMP errors for ICMP messages. */
+  if(ICMPBUF->proto == UIP_PROTO_ICMP) {
+    uip_len = 0;
+    return;
+  }
+  /* Copy fields from packet header into payload of this ICMP packet. */
+  memcpy(&(ICMPBUF->payload[0]), ICMPBUF, 28);
+
+  /* Set the ICMP type and code. */
+  ICMPBUF->type = ICMP_TE;
+  ICMPBUF->icode = 0;
+
+  /* Calculate the ICMP checksum. */
+  ICMPBUF->icmpchksum = 0;
+  ICMPBUF->icmpchksum = ~uip_chksum((u16_t *)&(ICMPBUF->type), 36);
+
+  /* Set the IP destination address to be the source address of the
+     original packet. */
+  tmp16= BUF->destipaddr[0];
+  BUF->destipaddr[0] = BUF->srcipaddr[0];
+  BUF->srcipaddr[0] = tmp16;
+  tmp16 = BUF->destipaddr[1];
+  BUF->destipaddr[1] = BUF->srcipaddr[1];
+  BUF->srcipaddr[1] = tmp16;
+
+  /* Set our IP address as the source address. */
+  BUF->srcipaddr[0] = uip_hostaddr[0];
+  BUF->srcipaddr[1] = uip_hostaddr[1];
+
+  /* The size of the ICMP time exceeded packet is 36 + the size of the
+     IP header (20) = 56. */
+  uip_len = 56;
+  ICMPBUF->len[0] = 0;
+  ICMPBUF->len[1] = uip_len;
+
+  /* Fill in the other fields in the IP header. */
+  ICMPBUF->vhl = 0x45;
+  ICMPBUF->tos = 0;
+  ICMPBUF->ipoffset[0] = ICMPBUF->ipoffset[1] = 0;
+  ICMPBUF->ttl  = UIP_TTL;
+  ICMPBUF->proto = UIP_PROTO_ICMP;
+  
+  /* Calculate IP checksum. */
+  ICMPBUF->ipchksum = 0;
+  ICMPBUF->ipchksum = ~(uip_ipchksum());
+
+
+}
+/*------------------------------------------------------------------------------*/
+/**
+ * \internal
+ * Register a packet in the forwarding cache so that it won't be
+ * forwarded again.
+ */
+/*------------------------------------------------------------------------------*/
+static void
+fwcache_register(void)
+{
+  struct fwcache_entry *fw;
+  int i, oldest;
+
+  oldest = FW_TIME;
+  fw = NULL;
+  
+  /* Find the oldest entry in the cache. */
+  for(i = 0; i < FWCACHE_SIZE; ++i) {
+    if(fwcache[i].timer == 0) {
+      fw = &fwcache[i];
+      break;
+    } else if(fwcache[i].timer <= oldest) {
+      fw = &fwcache[i];
+      oldest = fwcache[i].timer;
+    }
+  }
+
+  fw->timer = FW_TIME;
+  fw->ipid = BUF->ipid;
+  fw->srcipaddr[0] = BUF->srcipaddr[0];
+  fw->srcipaddr[1] = BUF->srcipaddr[1];
+  fw->destipaddr[0] = BUF->destipaddr[0];
+  fw->destipaddr[1] = BUF->destipaddr[1];
+  fw->proto = BUF->proto;
+#if notdef
+  fw->payload[0] = BUF->srcport;
+  fw->payload[1] = BUF->destport;
+#endif
+#if UIP_REASSEMBLY > 0
+  fw->len = BUF->len;
+  fw->offset = BUF->ipoffset;
+#endif
+}
+/*------------------------------------------------------------------------------*/
+/**
+ * \internal
+ * Find a network interface for the IP packet in uip_buf.
+ */
+/*------------------------------------------------------------------------------*/
+static struct uip_fw_netif *
+find_netif(void)
+{
+  struct uip_fw_netif *netif;
+  
+  /* Walk through every network interface to check for a match. */
+  for(netif = netifs; netif != NULL; netif = netif->next) {
+    if(ipaddr_maskcmp(BUF->destipaddr, netif->ipaddr,
+		      netif->netmask)) {
+      /* If there was a match, we break the loop. */
+      return netif;
+    }
+  }
+  
+  /* If no matching netif was found, we use default netif. */
+  return defaultnetif;
+}
+/*------------------------------------------------------------------------------*/
+/**
+ * Output an IP packet on the correct network interface.
+ *
+ * The IP packet should be present in the uip_buf buffer and its
+ * length in the global uip_len variable.
+ *
+ * \retval UIP_FW_ZEROLEN Indicates that a zero-length packet
+ * transmission was attempted and that no packet was sent.
+ *
+ * \retval UIP_FW_NOROUTE No suitable network interface could be found
+ * for the outbound packet, and the packet was not sent.
+ *
+ * \return The return value from the actual network interface output
+ * function is passed unmodified as a return value.
+ */
+/*------------------------------------------------------------------------------*/
+u8_t
+uip_fw_output(void)
+{
+  struct uip_fw_netif *netif;
+
+  if(uip_len == 0) {
+    return UIP_FW_ZEROLEN;
+  }
+
+  fwcache_register();
+
+#if UIP_BROADCAST
+  /* Link local broadcasts go out on all interfaces. */
+  if(/*BUF->proto == UIP_PROTO_UDP &&*/
+     BUF->destipaddr[0] == 0xffff &&
+     BUF->destipaddr[1] == 0xffff) {
+    if(defaultnetif != NULL) {
+      defaultnetif->output();
+    }
+    for(netif = netifs; netif != NULL; netif = netif->next) {
+      netif->output();
+    }
+    return UIP_FW_OK;
+  }
+#endif /* UIP_BROADCAST */
+  
+  netif = find_netif();
+  /*  printf("uip_fw_output: netif %p ->output %p len %d\n", netif,
+	 netif->output,
+	 uip_len);*/
+
+  if(netif == NULL) {
+    return UIP_FW_NOROUTE;
+  }
+  /* If we now have found a suitable network interface, we call its
+     output function to send out the packet. */
+  return netif->output();
+}
+/*------------------------------------------------------------------------------*/
+/**
+ * Forward an IP packet in the uip_buf buffer.
+ *
+ *
+ *
+ * \return UIP_FW_FORWARDED if the packet was forwarded, UIP_FW_LOCAL if
+ * the packet should be processed locally.
+ */
+/*------------------------------------------------------------------------------*/
+u8_t
+uip_fw_forward(void)
+{
+  struct fwcache_entry *fw;
+
+  /* First check if the packet is destined for ourselves and return 0
+     to indicate that the packet should be processed locally. */
+  if(BUF->destipaddr[0] == uip_hostaddr[0] &&
+     BUF->destipaddr[1] == uip_hostaddr[1]) {
+    return UIP_FW_LOCAL;
+  }
+
+  /* If we use ping IP address configuration, and our IP address is
+     not yet configured, we should intercept all ICMP echo packets. */
+#if UIP_PINGADDRCONF
+  if((uip_hostaddr[0] | uip_hostaddr[1]) == 0 &&
+     BUF->proto == UIP_PROTO_ICMP &&
+     ICMPBUF->type == ICMP_ECHO) {
+    return UIP_FW_LOCAL;
+  }
+#endif /* UIP_PINGADDRCONF */
+
+  /* Check if the packet is in the forwarding cache already, and if so
+     we drop it. */
+
+  for(fw = fwcache; fw < &fwcache[FWCACHE_SIZE]; ++fw) {
+    if(fw->timer != 0 &&
+#if UIP_REASSEMBLY > 0
+       fw->len == BUF->len &&
+       fw->offset == BUF->ipoffset &&
+#endif
+       fw->ipid == BUF->ipid &&
+       fw->srcipaddr[0] == BUF->srcipaddr[0] &&
+       fw->srcipaddr[1] == BUF->srcipaddr[1] &&
+       fw->destipaddr[0] == BUF->destipaddr[0] &&
+       fw->destipaddr[1] == BUF->destipaddr[1] &&
+#if notdef
+       fw->payload[0] == BUF->srcport &&
+       fw->payload[1] == BUF->destport &&
+#endif
+       fw->proto == BUF->proto) {
+      /* Drop packet. */
+      return UIP_FW_FORWARDED;
+    }
+  }
+
+  /* If the TTL reaches zero we produce an ICMP time exceeded message
+     in the uip_buf buffer and forward that packet back to the sender
+     of the packet. */
+  if(BUF->ttl <= 1) {
+    /* No time exceeded for broadcasts and multicasts! */
+    if(BUF->destipaddr[0] == 0xffff && BUF->destipaddr[1] == 0xffff) {
+      return UIP_FW_LOCAL;
+    }
+    time_exceeded();
+  }
+  
+  /* Decrement the TTL (time-to-live) value in the IP header */
+  BUF->ttl = BUF->ttl - 1;
+  
+  /* Update the IP checksum. */
+  if(BUF->ipchksum >= HTONS(0xffff - 0x0100)) {
+    BUF->ipchksum = BUF->ipchksum + HTONS(0x0100) + 1;
+  } else {
+    BUF->ipchksum = BUF->ipchksum + HTONS(0x0100);
+  }
+
+  if(uip_len > 0) {
+    uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_TCPIP_HLEN];
+    uip_fw_output();
+  }
+
+#if UIP_BROADCAST
+  if(BUF->destipaddr[0] == 0xffff && BUF->destipaddr[1] == 0xffff) {
+    return UIP_FW_LOCAL;
+  }
+#endif /* UIP_BROADCAST */
+
+  /* Return non-zero to indicate that the packet was forwarded and that no
+     other processing should be made. */
+  return UIP_FW_FORWARDED;
+}
+/*------------------------------------------------------------------------------*/
+/**
+ * Register a network interface with the forwarding module.
+ *
+ * \param netif A pointer to the network interface that is to be
+ * registered.
+ */
+/*------------------------------------------------------------------------------*/
+void
+uip_fw_register(struct uip_fw_netif *netif)
+{
+  netif->next = netifs;
+  netifs = netif;
+}
+/*------------------------------------------------------------------------------*/
+/**
+ * Register a default network interface.
+ *
+ * All packets that don't go out on any of the other interfaces will
+ * be routed to the default interface.
+ *
+ * \param netif A pointer to the network interface that is to be
+ * registered.
+ */
+/*------------------------------------------------------------------------------*/
+void
+uip_fw_default(struct uip_fw_netif *netif)
+{
+  defaultnetif = netif;
+}
+/*------------------------------------------------------------------------------*/
+/**
+ * Perform periodic processing.
+ */
+/*------------------------------------------------------------------------------*/
+void
+uip_fw_periodic(void)
+{
+  struct fwcache_entry *fw;
+  for(fw = fwcache; fw < &fwcache[FWCACHE_SIZE]; ++fw) {
+    if(fw->timer > 0) {
+      --fw->timer;
+    }
+  }
+}
+/*------------------------------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-fw.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-fw.h
new file mode 100644
index 0000000..e854ece
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-fw.h
@@ -0,0 +1,176 @@
+/**
+ * \addtogroup uipfw
+ * @{
+ */
+
+/**
+ * \file
+ * uIP packet forwarding header file.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2004, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: uip-fw.h,v 1.2 2006/06/12 08:00:30 adam Exp $
+ */
+#ifndef __UIP_FW_H__
+#define __UIP_FW_H__
+
+#include "uip.h"
+
+/**
+ * Representation of a uIP network interface.
+ */
+struct uip_fw_netif {
+  struct uip_fw_netif *next;  /**< Pointer to the next interface when
+				 linked in a list. */
+  u16_t ipaddr[2];            /**< The IP address of this interface. */
+  u16_t netmask[2];           /**< The netmask of the interface. */
+  u8_t (* output)(void);
+                              /**< A pointer to the function that
+				 sends a packet. */
+};
+
+/**
+ * Intantiating macro for a uIP network interface.
+ *
+ * Example:
+ \code
+ struct uip_fw_netif slipnetif =
+   {UIP_FW_NETIF(192,168,76,1, 255,255,255,0, slip_output)};
+ \endcode
+ * \param ip1,ip2,ip3,ip4 The IP address of the network interface.
+ *
+ * \param nm1,nm2,nm3,nm4 The netmask of the network interface.
+ *
+ * \param outputfunc A pointer to the output function of the network interface.
+ *
+ * \hideinitializer
+ */
+#define UIP_FW_NETIF(ip1,ip2,ip3,ip4, nm1,nm2,nm3,nm4, outputfunc) \
+        NULL, \
+	{HTONS((ip1 << 8) | ip2), HTONS((ip3 << 8) | ip4)}, \
+	{HTONS((nm1 << 8) | nm2), HTONS((nm3 << 8) | nm4)}, \
+        outputfunc
+
+/**
+ * Set the IP address of a network interface.
+ *
+ * \param netif A pointer to the uip_fw_netif structure for the network interface.
+ *
+ * \param addr A pointer to an IP address.
+ *
+ * \hideinitializer
+ */
+#define uip_fw_setipaddr(netif, addr) \
+        do { (netif)->ipaddr[0] = ((u16_t *)(addr))[0]; \
+             (netif)->ipaddr[1] = ((u16_t *)(addr))[1]; } while(0)
+/**
+ * Set the netmask of a network interface.
+ *
+ * \param netif A pointer to the uip_fw_netif structure for the network interface.
+ *
+ * \param addr A pointer to an IP address representing the netmask.
+ *
+ * \hideinitializer
+ */
+#define uip_fw_setnetmask(netif, addr) \
+        do { (netif)->netmask[0] = ((u16_t *)(addr))[0]; \
+             (netif)->netmask[1] = ((u16_t *)(addr))[1]; } while(0)
+
+void uip_fw_init(void);
+u8_t uip_fw_forward(void);
+u8_t uip_fw_output(void);
+void uip_fw_register(struct uip_fw_netif *netif);
+void uip_fw_default(struct uip_fw_netif *netif);
+void uip_fw_periodic(void);
+
+
+/**
+ * A non-error message that indicates that a packet should be
+ * processed locally.
+ *
+ * \hideinitializer
+ */
+#define UIP_FW_LOCAL     0
+
+/**
+ * A non-error message that indicates that something went OK.
+ *
+ * \hideinitializer
+ */
+#define UIP_FW_OK        0
+
+/**
+ * A non-error message that indicates that a packet was forwarded.
+ *
+ * \hideinitializer
+ */
+#define UIP_FW_FORWARDED 1
+
+/**
+ * A non-error message that indicates that a zero-length packet
+ * transmission was attempted, and that no packet was sent.
+ *
+ * \hideinitializer
+ */
+#define UIP_FW_ZEROLEN   2
+
+/**
+ * An error message that indicates that a packet that was too large
+ * for the outbound network interface was detected.
+ *
+ * \hideinitializer
+ */
+#define UIP_FW_TOOLARGE  3
+
+/**
+ * An error message that indicates that no suitable interface could be
+ * found for an outbound packet.
+ *
+ * \hideinitializer
+ */
+#define UIP_FW_NOROUTE   4
+
+/**
+ * An error message that indicates that a packet that should be
+ * forwarded or output was dropped.
+ *
+ * \hideinitializer
+ */
+#define UIP_FW_DROPPED   5
+
+
+#endif /* __UIP_FW_H__ */
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-neighbor.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-neighbor.c
new file mode 100644
index 0000000..6920960
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-neighbor.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2006, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * $Id: uip-neighbor.c,v 1.2 2006/06/12 08:00:30 adam Exp $
+ */
+
+/**
+ * \file
+ *         Database of link-local neighbors, used by IPv6 code and
+ *         to be used by a future ARP code rewrite.
+ * \author
+ *         Adam Dunkels 
+ */
+
+#include "uip-neighbor.h"
+
+#include 
+#include 
+
+#define MAX_TIME 128
+
+#ifdef UIP_NEIGHBOR_CONF_ENTRIES
+#define ENTRIES UIP_NEIGHBOR_CONF_ENTRIES
+#else /* UIP_NEIGHBOR_CONF_ENTRIES */
+#define ENTRIES 8
+#endif /* UIP_NEIGHBOR_CONF_ENTRIES */
+
+struct neighbor_entry {
+  uip_ipaddr_t ipaddr;
+  struct uip_neighbor_addr addr;
+  u8_t time;
+};
+static struct neighbor_entry entries[ENTRIES];
+
+/*---------------------------------------------------------------------------*/
+void
+uip_neighbor_init(void)
+{
+  int i;
+
+  for(i = 0; i < ENTRIES; ++i) {
+    entries[i].time = MAX_TIME;
+  }
+}
+/*---------------------------------------------------------------------------*/
+void
+uip_neighbor_periodic(void)
+{
+  int i;
+
+  for(i = 0; i < ENTRIES; ++i) {
+    if(entries[i].time < MAX_TIME) {
+      entries[i].time++;
+    }
+  }
+}
+/*---------------------------------------------------------------------------*/
+void
+uip_neighbor_add(uip_ipaddr_t ipaddr, struct uip_neighbor_addr *addr)
+{
+  int i, oldest;
+  u8_t oldest_time;
+
+  printf("Adding neighbor with link address %02x:%02x:%02x:%02x:%02x:%02x\n",
+	 addr->addr.addr[0], addr->addr.addr[1], addr->addr.addr[2], addr->addr.addr[3],
+	 addr->addr.addr[4], addr->addr.addr[5]);
+  
+  /* Find the first unused entry or the oldest used entry. */
+  oldest_time = 0;
+  oldest = 0;
+  for(i = 0; i < ENTRIES; ++i) {
+    if(entries[i].time == MAX_TIME) {
+      oldest = i;
+      break;
+    }
+    if(uip_ipaddr_cmp(entries[i].ipaddr, addr)) {
+      oldest = i;
+      break;
+    }
+    if(entries[i].time > oldest_time) {
+      oldest = i;
+      oldest_time = entries[i].time;
+    }
+  }
+
+  /* Use the oldest or first free entry (either pointed to by the
+     "oldest" variable). */
+  entries[oldest].time = 0;
+  uip_ipaddr_copy(entries[oldest].ipaddr, ipaddr);
+  memcpy(&entries[oldest].addr, addr, sizeof(struct uip_neighbor_addr));
+}
+/*---------------------------------------------------------------------------*/
+static struct neighbor_entry *
+find_entry(uip_ipaddr_t ipaddr)
+{
+  int i;
+  
+  for(i = 0; i < ENTRIES; ++i) {
+    if(uip_ipaddr_cmp(entries[i].ipaddr, ipaddr)) {
+      return &entries[i];
+    }
+  }
+  return NULL;
+}
+/*---------------------------------------------------------------------------*/
+void
+uip_neighbor_update(uip_ipaddr_t ipaddr)
+{
+  struct neighbor_entry *e;
+
+  e = find_entry(ipaddr);
+  if(e != NULL) {
+    e->time = 0;
+  }
+}
+/*---------------------------------------------------------------------------*/
+struct uip_neighbor_addr *
+uip_neighbor_lookup(uip_ipaddr_t ipaddr)
+{
+  struct neighbor_entry *e;
+
+  e = find_entry(ipaddr);
+  if(e != NULL) {
+    /*    printf("Lookup neighbor with link address %02x:%02x:%02x:%02x:%02x:%02x\n",
+	   e->addr.addr.addr[0], e->addr.addr.addr[1], e->addr.addr.addr[2], e->addr.addr.addr[3],
+	   e->addr.addr.addr[4], e->addr.addr.addr[5]);*/
+
+    return &e->addr;
+  }
+  return NULL;
+}
+/*---------------------------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-neighbor.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-neighbor.h
new file mode 100644
index 0000000..aca096f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-neighbor.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2006, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * $Id: uip-neighbor.h,v 1.2 2006/06/12 08:00:30 adam Exp $
+ */
+
+/**
+ * \file
+ *         Header file for database of link-local neighbors, used by
+ *         IPv6 code and to be used by future ARP code.
+ * \author
+ *         Adam Dunkels 
+ */
+
+#ifndef __UIP_NEIGHBOR_H__
+#define __UIP_NEIGHBOR_H__
+
+#include "uip.h"
+
+struct uip_neighbor_addr {
+#if UIP_NEIGHBOR_CONF_ADDRTYPE
+  UIP_NEIGHBOR_CONF_ADDRTYPE addr;
+#else
+  struct uip_eth_addr addr;
+#endif
+};
+
+void uip_neighbor_init(void);
+void uip_neighbor_add(uip_ipaddr_t ipaddr, struct uip_neighbor_addr *addr);
+void uip_neighbor_update(uip_ipaddr_t ipaddr);
+struct uip_neighbor_addr *uip_neighbor_lookup(uip_ipaddr_t ipaddr);
+void uip_neighbor_periodic(void);
+
+#endif /* __UIP-NEIGHBOR_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-split.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-split.c
new file mode 100644
index 0000000..639b9fc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-split.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2004, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: uip-split.c,v 1.2 2006/06/12 08:00:30 adam Exp $
+ */
+
+#include 
+
+#include "uip-split.h"
+#include "uip.h"
+#include "uip-fw.h"
+#include "uip_arch.h"
+
+
+
+#define BUF ((struct uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN])
+
+/*-----------------------------------------------------------------------------*/
+void
+uip_split_output(void)
+{
+  u16_t tcplen, len1, len2;
+
+  /* We only try to split maximum sized TCP segments. */
+  if(BUF->proto == UIP_PROTO_TCP &&
+     uip_len == UIP_BUFSIZE - UIP_LLH_LEN) {
+
+    tcplen = uip_len - UIP_TCPIP_HLEN;
+    /* Split the segment in two. If the original packet length was
+       odd, we make the second packet one byte larger. */
+    len1 = len2 = tcplen / 2;
+    if(len1 + len2 < tcplen) {
+      ++len2;
+    }
+
+    /* Create the first packet. This is done by altering the length
+       field of the IP header and updating the checksums. */
+    uip_len = len1 + UIP_TCPIP_HLEN;
+#if UIP_CONF_IPV6
+    /* For IPv6, the IP length field does not include the IPv6 IP header
+       length. */
+    BUF->len[0] = ((uip_len - UIP_IPH_LEN) >> 8);
+    BUF->len[1] = ((uip_len - UIP_IPH_LEN) & 0xff);
+#else /* UIP_CONF_IPV6 */
+    BUF->len[0] = uip_len >> 8;
+    BUF->len[1] = uip_len & 0xff;
+#endif /* UIP_CONF_IPV6 */
+    
+    /* Recalculate the TCP checksum. */
+    BUF->tcpchksum = 0;
+    BUF->tcpchksum = ~(uip_tcpchksum());
+
+#if !UIP_CONF_IPV6
+    /* Recalculate the IP checksum. */
+    BUF->ipchksum = 0;
+    BUF->ipchksum = ~(uip_ipchksum());
+#endif /* UIP_CONF_IPV6 */
+    
+    /* Transmit the first packet. */
+    /*    uip_fw_output();*/
+    tcpip_output();
+
+    /* Now, create the second packet. To do this, it is not enough to
+       just alter the length field, but we must also update the TCP
+       sequence number and point the uip_appdata to a new place in
+       memory. This place is detemined by the length of the first
+       packet (len1). */
+    uip_len = len2 + UIP_TCPIP_HLEN;
+#if UIP_CONF_IPV6
+    /* For IPv6, the IP length field does not include the IPv6 IP header
+       length. */
+    BUF->len[0] = ((uip_len - UIP_IPH_LEN) >> 8);
+    BUF->len[1] = ((uip_len - UIP_IPH_LEN) & 0xff);
+#else /* UIP_CONF_IPV6 */
+    BUF->len[0] = uip_len >> 8;
+    BUF->len[1] = uip_len & 0xff;
+#endif /* UIP_CONF_IPV6 */
+    
+    /*    uip_appdata += len1;*/
+    memcpy(uip_appdata, (u8_t *)uip_appdata + len1, len2);
+
+    uip_add32(BUF->seqno, len1);
+    BUF->seqno[0] = uip_acc32[0];
+    BUF->seqno[1] = uip_acc32[1];
+    BUF->seqno[2] = uip_acc32[2];
+    BUF->seqno[3] = uip_acc32[3];
+    
+    /* Recalculate the TCP checksum. */
+    BUF->tcpchksum = 0;
+    BUF->tcpchksum = ~(uip_tcpchksum());
+
+#if !UIP_CONF_IPV6
+    /* Recalculate the IP checksum. */
+    BUF->ipchksum = 0;
+    BUF->ipchksum = ~(uip_ipchksum());
+#endif /* UIP_CONF_IPV6 */
+
+    /* Transmit the second packet. */
+    /*    uip_fw_output();*/
+    tcpip_output();
+  } else {
+    /*    uip_fw_output();*/
+    tcpip_output();
+  }
+     
+}
+/*-----------------------------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-split.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-split.h
new file mode 100644
index 0000000..446e192
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-split.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2004, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * Author: Adam Dunkels 
+ *
+ * $Id: uip-split.h,v 1.2 2006/06/12 08:00:30 adam Exp $
+ */
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \defgroup uipsplit uIP TCP throughput booster hack
+ * @{
+ *
+ * The basic uIP TCP implementation only allows each TCP connection to
+ * have a single TCP segment in flight at any given time. Because of
+ * the delayed ACK algorithm employed by most TCP receivers, uIP's
+ * limit on the amount of in-flight TCP segments seriously reduces the
+ * maximum achievable throughput for sending data from uIP.
+ *
+ * The uip-split module is a hack which tries to remedy this
+ * situation. By splitting maximum sized outgoing TCP segments into
+ * two, the delayed ACK algorithm is not invoked at TCP
+ * receivers. This improves the throughput when sending data from uIP
+ * by orders of magnitude.
+ *
+ * The uip-split module uses the uip-fw module (uIP IP packet
+ * forwarding) for sending packets. Therefore, the uip-fw module must
+ * be set up with the appropriate network interfaces for this module
+ * to work.
+ */
+
+
+/**
+ * \file
+ * Module for splitting outbound TCP segments in two to avoid the
+ * delayed ACK throughput degradation.
+ * \author
+ * Adam Dunkels 
+ *
+ */
+
+#ifndef __UIP_SPLIT_H__
+#define __UIP_SPLIT_H__
+
+/**
+ * Handle outgoing packets.
+ *
+ * This function inspects an outgoing packet in the uip_buf buffer and
+ * sends it out using the uip_fw_output() function. If the packet is a
+ * full-sized TCP segment it will be split into two segments and
+ * transmitted separately. This function should be called instead of
+ * the actual device driver output function, or the uip_fw_output()
+ * function.
+ *
+ * The headers of the outgoing packet is assumed to be in the uip_buf
+ * buffer and the payload is assumed to be wherever uip_appdata
+ * points. The length of the outgoing packet is assumed to be in the
+ * uip_len variable.
+ *
+ */
+void uip_split_output(void);
+
+#endif /* __UIP_SPLIT_H__ */
+
+/** @} */
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip.c
new file mode 100644
index 0000000..bac2527
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip.c
@@ -0,0 +1,1908 @@
+#define DEBUG_PRINTF(...) /*printf(__VA_ARGS__)*/
+
+/**
+ * \defgroup uip The uIP TCP/IP stack
+ * @{
+ *
+ * uIP is an implementation of the TCP/IP protocol stack intended for
+ * small 8-bit and 16-bit microcontrollers.
+ *
+ * uIP provides the necessary protocols for Internet communication,
+ * with a very small code footprint and RAM requirements - the uIP
+ * code size is on the order of a few kilobytes and RAM usage is on
+ * the order of a few hundred bytes.
+ */
+
+/**
+ * \file
+ * The uIP TCP/IP stack code.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip.c,v 1.65 2006/06/11 21:46:39 adam Exp $
+ *
+ */
+
+/*
+ * uIP is a small implementation of the IP, UDP and TCP protocols (as
+ * well as some basic ICMP stuff). The implementation couples the IP,
+ * UDP, TCP and the application layers very tightly. To keep the size
+ * of the compiled code down, this code frequently uses the goto
+ * statement. While it would be possible to break the uip_process()
+ * function into many smaller functions, this would increase the code
+ * size because of the overhead of parameter passing and the fact that
+ * the optimier would not be as efficient.
+ *
+ * The principle is that we have a small buffer, called the uip_buf,
+ * in which the device driver puts an incoming packet. The TCP/IP
+ * stack parses the headers in the packet, and calls the
+ * application. If the remote host has sent data to the application,
+ * this data is present in the uip_buf and the application read the
+ * data from there. It is up to the application to put this data into
+ * a byte stream if needed. The application will not be fed with data
+ * that is out of sequence.
+ *
+ * If the application whishes to send data to the peer, it should put
+ * its data into the uip_buf. The uip_appdata pointer points to the
+ * first available byte. The TCP/IP stack will calculate the
+ * checksums, and fill in the necessary header fields and finally send
+ * the packet back to the peer.
+*/
+
+#include "uip.h"
+#include "uipopt.h"
+#include "uip_arch.h"
+
+#if UIP_CONF_IPV6
+#include "uip-neighbor.h"
+#endif /* UIP_CONF_IPV6 */
+
+#include 
+
+/*---------------------------------------------------------------------------*/
+/* Variable definitions. */
+
+
+/* The IP address of this host. If it is defined to be fixed (by
+   setting UIP_FIXEDADDR to 1 in uipopt.h), the address is set
+   here. Otherwise, the address */
+#if UIP_FIXEDADDR > 0
+const uip_ipaddr_t uip_hostaddr =
+  {HTONS((UIP_IPADDR0 << 8) | UIP_IPADDR1),
+   HTONS((UIP_IPADDR2 << 8) | UIP_IPADDR3)};
+const uip_ipaddr_t uip_draddr =
+  {HTONS((UIP_DRIPADDR0 << 8) | UIP_DRIPADDR1),
+   HTONS((UIP_DRIPADDR2 << 8) | UIP_DRIPADDR3)};
+const uip_ipaddr_t uip_netmask =
+  {HTONS((UIP_NETMASK0 << 8) | UIP_NETMASK1),
+   HTONS((UIP_NETMASK2 << 8) | UIP_NETMASK3)};
+#else
+uip_ipaddr_t uip_hostaddr, uip_draddr, uip_netmask;
+#endif /* UIP_FIXEDADDR */
+
+static const uip_ipaddr_t all_ones_addr =
+#if UIP_CONF_IPV6
+  {0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff};
+#else /* UIP_CONF_IPV6 */
+  {0xffff,0xffff};
+#endif /* UIP_CONF_IPV6 */
+static const uip_ipaddr_t all_zeroes_addr =
+#if UIP_CONF_IPV6
+  {0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000};
+#else /* UIP_CONF_IPV6 */
+  {0x0000,0x0000};
+#endif /* UIP_CONF_IPV6 */
+
+#if UIP_FIXEDETHADDR
+const struct uip_eth_addr uip_ethaddr = {{UIP_ETHADDR0,
+					  UIP_ETHADDR1,
+					  UIP_ETHADDR2,
+					  UIP_ETHADDR3,
+					  UIP_ETHADDR4,
+					  UIP_ETHADDR5}};
+#else
+struct uip_eth_addr uip_ethaddr = {{0,0,0,0,0,0}};
+#endif
+
+#ifndef UIP_CONF_EXTERNAL_BUFFER
+
+#ifdef __ICCARM__
+	#pragma data_alignment=4
+		u8_t uip_buf[UIP_BUFSIZE + 2]; /* The packet buffer that contains incoming packets. */
+#else
+	u8_t uip_buf[UIP_BUFSIZE + 2] ALIGN_STRUCT_END; /* The packet buffer that contains incoming packets. */
+#endif
+
+#endif /* UIP_CONF_EXTERNAL_BUFFER */
+
+void *uip_appdata;               /* The uip_appdata pointer points to
+				    application data. */
+void *uip_sappdata;              /* The uip_appdata pointer points to
+				    the application data which is to
+				    be sent. */
+#if UIP_URGDATA > 0
+void *uip_urgdata;               /* The uip_urgdata pointer points to
+   				    urgent data (out-of-band data), if
+   				    present. */
+u16_t uip_urglen, uip_surglen;
+#endif /* UIP_URGDATA > 0 */
+
+u16_t uip_len, uip_slen;
+                             /* The uip_len is either 8 or 16 bits,
+				depending on the maximum packet
+				size. */
+
+u8_t uip_flags;     /* The uip_flags variable is used for
+				communication between the TCP/IP stack
+				and the application program. */
+struct uip_conn *uip_conn;   /* uip_conn always points to the current
+				connection. */
+
+struct uip_conn uip_conns[UIP_CONNS];
+                             /* The uip_conns array holds all TCP
+				connections. */
+u16_t uip_listenports[UIP_LISTENPORTS];
+                             /* The uip_listenports list all currently
+				listning ports. */
+#if UIP_UDP
+struct uip_udp_conn *uip_udp_conn;
+struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS];
+#endif /* UIP_UDP */
+
+static u16_t ipid;           /* Ths ipid variable is an increasing
+				number that is used for the IP ID
+				field. */
+
+void uip_setipid(u16_t id) { ipid = id; }
+
+static u8_t iss[4];          /* The iss variable is used for the TCP
+				initial sequence number. */
+
+#if UIP_ACTIVE_OPEN
+static u16_t lastport;       /* Keeps track of the last port used for
+				a new connection. */
+#endif /* UIP_ACTIVE_OPEN */
+
+/* Temporary variables. */
+u8_t uip_acc32[4];
+static u8_t c, opt;
+static u16_t tmp16;
+
+/* Structures and definitions. */
+#define TCP_FIN 0x01
+#define TCP_SYN 0x02
+#define TCP_RST 0x04
+#define TCP_PSH 0x08
+#define TCP_ACK 0x10
+#define TCP_URG 0x20
+#define TCP_CTL 0x3f
+
+#define TCP_OPT_END     0   /* End of TCP options list */
+#define TCP_OPT_NOOP    1   /* "No-operation" TCP option */
+#define TCP_OPT_MSS     2   /* Maximum segment size TCP option */
+
+#define TCP_OPT_MSS_LEN 4   /* Length of TCP MSS option. */
+
+#define ICMP_ECHO_REPLY 0
+#define ICMP_ECHO       8
+
+#define ICMP6_ECHO_REPLY             129
+#define ICMP6_ECHO                   128
+#define ICMP6_NEIGHBOR_SOLICITATION  135
+#define ICMP6_NEIGHBOR_ADVERTISEMENT 136
+
+#define ICMP6_FLAG_S (1 << 6)
+
+#define ICMP6_OPTION_SOURCE_LINK_ADDRESS 1
+#define ICMP6_OPTION_TARGET_LINK_ADDRESS 2
+
+
+/* Macros. */
+#define BUF ((struct uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN])
+#define FBUF ((struct uip_tcpip_hdr *)&uip_reassbuf[0])
+#define ICMPBUF ((struct uip_icmpip_hdr *)&uip_buf[UIP_LLH_LEN])
+#define UDPBUF ((struct uip_udpip_hdr *)&uip_buf[UIP_LLH_LEN])
+
+
+#if UIP_STATISTICS == 1
+struct uip_stats uip_stat;
+#define UIP_STAT(s) s
+#else
+#define UIP_STAT(s)
+#endif /* UIP_STATISTICS == 1 */
+
+#if UIP_LOGGING == 1
+#include 
+void uip_log(char *msg);
+#define UIP_LOG(m) uip_log(m)
+#else
+#define UIP_LOG(m)
+#endif /* UIP_LOGGING == 1 */
+
+#if ! UIP_ARCH_ADD32
+void
+uip_add32(u8_t *op32, u16_t op16)
+{
+  uip_acc32[3] = op32[3] + (op16 & 0xff);
+  uip_acc32[2] = op32[2] + (op16 >> 8);
+  uip_acc32[1] = op32[1];
+  uip_acc32[0] = op32[0];
+
+  if(uip_acc32[2] < (op16 >> 8)) {
+    ++uip_acc32[1];
+    if(uip_acc32[1] == 0) {
+      ++uip_acc32[0];
+    }
+  }
+
+
+  if(uip_acc32[3] < (op16 & 0xff)) {
+    ++uip_acc32[2];
+    if(uip_acc32[2] == 0) {
+      ++uip_acc32[1];
+      if(uip_acc32[1] == 0) {
+	++uip_acc32[0];
+      }
+    }
+  }
+}
+
+#endif /* UIP_ARCH_ADD32 */
+
+#if ! UIP_ARCH_CHKSUM
+/*---------------------------------------------------------------------------*/
+static u16_t
+chksum(u16_t sum, const u8_t *data, u16_t len)
+{
+  u16_t t;
+  const u8_t *dataptr;
+  const u8_t *last_byte;
+
+  dataptr = data;
+  last_byte = data + len - 1;
+
+  while(dataptr < last_byte) {	/* At least two more bytes */
+    t = (dataptr[0] << 8) + dataptr[1];
+    sum += t;
+    if(sum < t) {
+      sum++;		/* carry */
+    }
+    dataptr += 2;
+  }
+
+  if(dataptr == last_byte) {
+    t = (dataptr[0] << 8) + 0;
+    sum += t;
+    if(sum < t) {
+      sum++;		/* carry */
+    }
+  }
+
+  /* Return sum in host byte order. */
+  return sum;
+}
+/*---------------------------------------------------------------------------*/
+u16_t
+uip_chksum(u16_t *data, u16_t len)
+{
+  return htons(chksum(0, (u8_t *)data, len));
+}
+/*---------------------------------------------------------------------------*/
+#ifndef UIP_ARCH_IPCHKSUM
+u16_t
+uip_ipchksum(void)
+{
+  u16_t sum;
+
+  sum = chksum(0, &uip_buf[UIP_LLH_LEN], UIP_IPH_LEN);
+  DEBUG_PRINTF("uip_ipchksum: sum 0x%04x\n", sum);
+  return (sum == 0) ? 0xffff : htons(sum);
+}
+#endif
+/*---------------------------------------------------------------------------*/
+static u16_t
+upper_layer_chksum(u8_t proto)
+{
+  u16_t upper_layer_len;
+  u16_t sum;
+
+#if UIP_CONF_IPV6
+  upper_layer_len = (((u16_t)(BUF->len[0]) << 8) + BUF->len[1]);
+#else /* UIP_CONF_IPV6 */
+  upper_layer_len = (((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - UIP_IPH_LEN;
+#endif /* UIP_CONF_IPV6 */
+
+  /* First sum pseudoheader. */
+
+  /* IP protocol and length fields. This addition cannot carry. */
+  sum = upper_layer_len + proto;
+  /* Sum IP source and destination addresses. */
+  sum = chksum(sum, (u8_t *)&BUF->srcipaddr[0], 2 * sizeof(uip_ipaddr_t));
+
+  /* Sum TCP header and data. */
+  sum = chksum(sum, &uip_buf[UIP_IPH_LEN + UIP_LLH_LEN],
+	       upper_layer_len);
+
+  return (sum == 0) ? 0xffff : htons(sum);
+}
+/*---------------------------------------------------------------------------*/
+#if UIP_CONF_IPV6
+u16_t
+uip_icmp6chksum(void)
+{
+  return upper_layer_chksum(UIP_PROTO_ICMP6);
+
+}
+#endif /* UIP_CONF_IPV6 */
+/*---------------------------------------------------------------------------*/
+u16_t
+uip_tcpchksum(void)
+{
+  return upper_layer_chksum(UIP_PROTO_TCP);
+}
+/*---------------------------------------------------------------------------*/
+#if UIP_UDP_CHECKSUMS
+u16_t
+uip_udpchksum(void)
+{
+  return upper_layer_chksum(UIP_PROTO_UDP);
+}
+#endif /* UIP_UDP_CHECKSUMS */
+#endif /* UIP_ARCH_CHKSUM */
+/*---------------------------------------------------------------------------*/
+void
+uip_init(void)
+{
+  for(c = 0; c < UIP_LISTENPORTS; ++c) {
+    uip_listenports[c] = 0;
+  }
+  for(c = 0; c < UIP_CONNS; ++c) {
+    uip_conns[c].tcpstateflags = UIP_CLOSED;
+  }
+#if UIP_ACTIVE_OPEN
+  lastport = 1024;
+#endif /* UIP_ACTIVE_OPEN */
+
+#if UIP_UDP
+  for(c = 0; c < UIP_UDP_CONNS; ++c) {
+    uip_udp_conns[c].lport = 0;
+  }
+#endif /* UIP_UDP */
+
+
+  /* IPv4 initialization. */
+#if UIP_FIXEDADDR == 0
+  /*  uip_hostaddr[0] = uip_hostaddr[1] = 0;*/
+#endif /* UIP_FIXEDADDR */
+
+}
+/*---------------------------------------------------------------------------*/
+#if UIP_ACTIVE_OPEN
+struct uip_conn *
+uip_connect(uip_ipaddr_t *ripaddr, u16_t rport)
+{
+  register struct uip_conn *conn, *cconn;
+
+  /* Find an unused local port. */
+ again:
+  ++lastport;
+
+  if(lastport >= 32000) {
+    lastport = 4096;
+  }
+
+  /* Check if this port is already in use, and if so try to find
+     another one. */
+  for(c = 0; c < UIP_CONNS; ++c) {
+    conn = &uip_conns[c];
+    if(conn->tcpstateflags != UIP_CLOSED &&
+       conn->lport == htons(lastport)) {
+      goto again;
+    }
+  }
+
+  conn = 0;
+  for(c = 0; c < UIP_CONNS; ++c) {
+    cconn = &uip_conns[c];
+    if(cconn->tcpstateflags == UIP_CLOSED) {
+      conn = cconn;
+      break;
+    }
+    if(cconn->tcpstateflags == UIP_TIME_WAIT) {
+      if(conn == 0 ||
+	 cconn->timer > conn->timer) {
+	conn = cconn;
+      }
+    }
+  }
+
+  if(conn == 0) {
+    return 0;
+  }
+
+  conn->tcpstateflags = UIP_SYN_SENT;
+
+  conn->snd_nxt[0] = iss[0];
+  conn->snd_nxt[1] = iss[1];
+  conn->snd_nxt[2] = iss[2];
+  conn->snd_nxt[3] = iss[3];
+
+  conn->initialmss = conn->mss = UIP_TCP_MSS;
+
+  conn->len = 1;   /* TCP length of the SYN is one. */
+  conn->nrtx = 0;
+  conn->timer = 1; /* Send the SYN next time around. */
+  conn->rto = UIP_RTO;
+  conn->sa = 0;
+  conn->sv = 16;   /* Initial value of the RTT variance. */
+  conn->lport = htons(lastport);
+  conn->rport = rport;
+  uip_ipaddr_copy(&conn->ripaddr, ripaddr);
+
+  return conn;
+}
+#endif /* UIP_ACTIVE_OPEN */
+/*---------------------------------------------------------------------------*/
+#if UIP_UDP
+struct uip_udp_conn *
+uip_udp_new(uip_ipaddr_t *ripaddr, u16_t rport)
+{
+  register struct uip_udp_conn *conn;
+
+  /* Find an unused local port. */
+ again:
+  ++lastport;
+
+  if(lastport >= 32000) {
+    lastport = 4096;
+  }
+
+  for(c = 0; c < UIP_UDP_CONNS; ++c) {
+    if(uip_udp_conns[c].lport == htons(lastport)) {
+      goto again;
+    }
+  }
+
+
+  conn = 0;
+  for(c = 0; c < UIP_UDP_CONNS; ++c) {
+    if(uip_udp_conns[c].lport == 0) {
+      conn = &uip_udp_conns[c];
+      break;
+    }
+  }
+
+  if(conn == 0) {
+    return 0;
+  }
+
+  conn->lport = HTONS(lastport);
+  conn->rport = rport;
+  if(ripaddr == NULL) {
+    memset(conn->ripaddr, 0, sizeof(uip_ipaddr_t));
+  } else {
+    uip_ipaddr_copy(&conn->ripaddr, ripaddr);
+  }
+  conn->ttl = UIP_TTL;
+
+  return conn;
+}
+#endif /* UIP_UDP */
+/*---------------------------------------------------------------------------*/
+void
+uip_unlisten(u16_t port)
+{
+  for(c = 0; c < UIP_LISTENPORTS; ++c) {
+    if(uip_listenports[c] == port) {
+      uip_listenports[c] = 0;
+      return;
+    }
+  }
+}
+/*---------------------------------------------------------------------------*/
+void
+uip_listen(u16_t port)
+{
+  for(c = 0; c < UIP_LISTENPORTS; ++c) {
+    if(uip_listenports[c] == 0) {
+      uip_listenports[c] = port;
+      return;
+    }
+  }
+}
+/*---------------------------------------------------------------------------*/
+/* XXX: IP fragment reassembly: not well-tested. */
+
+#if UIP_REASSEMBLY && !UIP_CONF_IPV6
+#define UIP_REASS_BUFSIZE (UIP_BUFSIZE - UIP_LLH_LEN)
+static u8_t uip_reassbuf[UIP_REASS_BUFSIZE];
+static u8_t uip_reassbitmap[UIP_REASS_BUFSIZE / (8 * 8)];
+static const u8_t bitmap_bits[8] = {0xff, 0x7f, 0x3f, 0x1f,
+				    0x0f, 0x07, 0x03, 0x01};
+static u16_t uip_reasslen;
+static u8_t uip_reassflags;
+#define UIP_REASS_FLAG_LASTFRAG 0x01
+static u8_t uip_reasstmr;
+
+#define IP_MF   0x20
+
+static u8_t
+uip_reass(void)
+{
+  u16_t offset, len;
+  u16_t i;
+
+  /* If ip_reasstmr is zero, no packet is present in the buffer, so we
+     write the IP header of the fragment into the reassembly
+     buffer. The timer is updated with the maximum age. */
+  if(uip_reasstmr == 0) {
+    memcpy(uip_reassbuf, &BUF->vhl, UIP_IPH_LEN);
+    uip_reasstmr = UIP_REASS_MAXAGE;
+    uip_reassflags = 0;
+    /* Clear the bitmap. */
+    memset(uip_reassbitmap, 0, sizeof(uip_reassbitmap));
+  }
+
+  /* Check if the incoming fragment matches the one currently present
+     in the reasembly buffer. If so, we proceed with copying the
+     fragment into the buffer. */
+  if(BUF->srcipaddr[0] == FBUF->srcipaddr[0] &&
+     BUF->srcipaddr[1] == FBUF->srcipaddr[1] &&
+     BUF->destipaddr[0] == FBUF->destipaddr[0] &&
+     BUF->destipaddr[1] == FBUF->destipaddr[1] &&
+     BUF->ipid[0] == FBUF->ipid[0] &&
+     BUF->ipid[1] == FBUF->ipid[1]) {
+
+    len = (BUF->len[0] << 8) + BUF->len[1] - (BUF->vhl & 0x0f) * 4;
+    offset = (((BUF->ipoffset[0] & 0x3f) << 8) + BUF->ipoffset[1]) * 8;
+
+    /* If the offset or the offset + fragment length overflows the
+       reassembly buffer, we discard the entire packet. */
+    if(offset > UIP_REASS_BUFSIZE ||
+       offset + len > UIP_REASS_BUFSIZE) {
+      uip_reasstmr = 0;
+      goto nullreturn;
+    }
+
+    /* Copy the fragment into the reassembly buffer, at the right
+       offset. */
+    memcpy(&uip_reassbuf[UIP_IPH_LEN + offset],
+	   (char *)BUF + (int)((BUF->vhl & 0x0f) * 4),
+	   len);
+
+    /* Update the bitmap. */
+    if(offset / (8 * 8) == (offset + len) / (8 * 8)) {
+      /* If the two endpoints are in the same byte, we only update
+	 that byte. */
+
+      uip_reassbitmap[offset / (8 * 8)] |=
+	     bitmap_bits[(offset / 8 ) & 7] &
+	     ~bitmap_bits[((offset + len) / 8 ) & 7];
+    } else {
+      /* If the two endpoints are in different bytes, we update the
+	 bytes in the endpoints and fill the stuff inbetween with
+	 0xff. */
+      uip_reassbitmap[offset / (8 * 8)] |=
+	bitmap_bits[(offset / 8 ) & 7];
+      for(i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) {
+	uip_reassbitmap[i] = 0xff;
+      }
+      uip_reassbitmap[(offset + len) / (8 * 8)] |=
+	~bitmap_bits[((offset + len) / 8 ) & 7];
+    }
+
+    /* If this fragment has the More Fragments flag set to zero, we
+       know that this is the last fragment, so we can calculate the
+       size of the entire packet. We also set the
+       IP_REASS_FLAG_LASTFRAG flag to indicate that we have received
+       the final fragment. */
+
+    if((BUF->ipoffset[0] & IP_MF) == 0) {
+      uip_reassflags |= UIP_REASS_FLAG_LASTFRAG;
+      uip_reasslen = offset + len;
+    }
+
+    /* Finally, we check if we have a full packet in the buffer. We do
+       this by checking if we have the last fragment and if all bits
+       in the bitmap are set. */
+    if(uip_reassflags & UIP_REASS_FLAG_LASTFRAG) {
+      /* Check all bytes up to and including all but the last byte in
+	 the bitmap. */
+      for(i = 0; i < uip_reasslen / (8 * 8) - 1; ++i) {
+	if(uip_reassbitmap[i] != 0xff) {
+	  goto nullreturn;
+	}
+      }
+      /* Check the last byte in the bitmap. It should contain just the
+	 right amount of bits. */
+      if(uip_reassbitmap[uip_reasslen / (8 * 8)] !=
+	 (u8_t)~bitmap_bits[uip_reasslen / 8 & 7]) {
+	goto nullreturn;
+      }
+
+      /* If we have come this far, we have a full packet in the
+	 buffer, so we allocate a pbuf and copy the packet into it. We
+	 also reset the timer. */
+      uip_reasstmr = 0;
+      memcpy(BUF, FBUF, uip_reasslen);
+
+      /* Pretend to be a "normal" (i.e., not fragmented) IP packet
+	 from now on. */
+      BUF->ipoffset[0] = BUF->ipoffset[1] = 0;
+      BUF->len[0] = uip_reasslen >> 8;
+      BUF->len[1] = uip_reasslen & 0xff;
+      BUF->ipchksum = 0;
+      BUF->ipchksum = ~(uip_ipchksum());
+
+      return uip_reasslen;
+    }
+  }
+
+ nullreturn:
+  return 0;
+}
+#endif /* UIP_REASSEMBLY */
+/*---------------------------------------------------------------------------*/
+static void
+uip_add_rcv_nxt(u16_t n)
+{
+  uip_add32(uip_conn->rcv_nxt, n);
+  uip_conn->rcv_nxt[0] = uip_acc32[0];
+  uip_conn->rcv_nxt[1] = uip_acc32[1];
+  uip_conn->rcv_nxt[2] = uip_acc32[2];
+  uip_conn->rcv_nxt[3] = uip_acc32[3];
+}
+/*---------------------------------------------------------------------------*/
+void
+uip_process(u8_t flag)
+{
+  register struct uip_conn *uip_connr = uip_conn;
+
+  ( void ) all_ones_addr;
+
+#if UIP_UDP
+  if(flag == UIP_UDP_SEND_CONN) {
+    goto udp_send;
+  }
+#endif /* UIP_UDP */
+
+  uip_sappdata = uip_appdata = &uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN];
+
+  /* Check if we were invoked because of a poll request for a
+     particular connection. */
+  if(flag == UIP_POLL_REQUEST) {
+    if((uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_ESTABLISHED &&
+       !uip_outstanding(uip_connr)) {
+	uip_flags = UIP_POLL;
+	UIP_APPCALL();
+	goto appsend;
+    }
+    goto drop;
+
+    /* Check if we were invoked because of the perodic timer fireing. */
+  } else if(flag == UIP_TIMER) {
+#if UIP_REASSEMBLY
+    if(uip_reasstmr != 0) {
+      --uip_reasstmr;
+    }
+#endif /* UIP_REASSEMBLY */
+    /* Increase the initial sequence number. */
+    if(++iss[3] == 0) {
+      if(++iss[2] == 0) {
+	if(++iss[1] == 0) {
+	  ++iss[0];
+	}
+      }
+    }
+
+    /* Reset the length variables. */
+    uip_len = 0;
+    uip_slen = 0;
+
+    /* Check if the connection is in a state in which we simply wait
+       for the connection to time out. If so, we increase the
+       connection's timer and remove the connection if it times
+       out. */
+    if(uip_connr->tcpstateflags == UIP_TIME_WAIT ||
+       uip_connr->tcpstateflags == UIP_FIN_WAIT_2) {
+      ++(uip_connr->timer);
+      if(uip_connr->timer == UIP_TIME_WAIT_TIMEOUT) {
+	uip_connr->tcpstateflags = UIP_CLOSED;
+      }
+    } else if(uip_connr->tcpstateflags != UIP_CLOSED) {
+      /* If the connection has outstanding data, we increase the
+	 connection's timer and see if it has reached the RTO value
+	 in which case we retransmit. */
+      if(uip_outstanding(uip_connr)) {
+	  uip_connr->timer = uip_connr->timer - 1;
+	if(uip_connr->timer == 0) {
+	  if(uip_connr->nrtx == UIP_MAXRTX ||
+	     ((uip_connr->tcpstateflags == UIP_SYN_SENT ||
+	       uip_connr->tcpstateflags == UIP_SYN_RCVD) &&
+	      uip_connr->nrtx == UIP_MAXSYNRTX)) {
+	    uip_connr->tcpstateflags = UIP_CLOSED;
+
+	    /* We call UIP_APPCALL() with uip_flags set to
+	       UIP_TIMEDOUT to inform the application that the
+	       connection has timed out. */
+	    uip_flags = UIP_TIMEDOUT;
+	    UIP_APPCALL();
+
+	    /* We also send a reset packet to the remote host. */
+	    BUF->flags = TCP_RST | TCP_ACK;
+	    goto tcp_send_nodata;
+	  }
+
+	  /* Exponential backoff. */
+	  uip_connr->timer = UIP_RTO << (uip_connr->nrtx > 4?
+					 4:
+					 uip_connr->nrtx);
+	  ++(uip_connr->nrtx);
+
+	  /* Ok, so we need to retransmit. We do this differently
+	     depending on which state we are in. In ESTABLISHED, we
+	     call upon the application so that it may prepare the
+	     data for the retransmit. In SYN_RCVD, we resend the
+	     SYNACK that we sent earlier and in LAST_ACK we have to
+	     retransmit our FINACK. */
+	  UIP_STAT(++uip_stat.tcp.rexmit);
+	  switch(uip_connr->tcpstateflags & UIP_TS_MASK) {
+	  case UIP_SYN_RCVD:
+	    /* In the SYN_RCVD state, we should retransmit our
+               SYNACK. */
+	    goto tcp_send_synack;
+
+#if UIP_ACTIVE_OPEN
+	  case UIP_SYN_SENT:
+	    /* In the SYN_SENT state, we retransmit out SYN. */
+	    BUF->flags = 0;
+	    goto tcp_send_syn;
+#endif /* UIP_ACTIVE_OPEN */
+
+	  case UIP_ESTABLISHED:
+	    /* In the ESTABLISHED state, we call upon the application
+               to do the actual retransmit after which we jump into
+               the code for sending out the packet (the apprexmit
+               label). */
+	    uip_flags = UIP_REXMIT;
+	    UIP_APPCALL();
+	    goto apprexmit;
+
+	  case UIP_FIN_WAIT_1:
+	  case UIP_CLOSING:
+	  case UIP_LAST_ACK:
+	    /* In all these states we should retransmit a FINACK. */
+	    goto tcp_send_finack;
+
+	  }
+	}
+      } else if((uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_ESTABLISHED) {
+	/* If there was no need for a retransmission, we poll the
+           application for new data. */
+	uip_flags = UIP_POLL;
+	UIP_APPCALL();
+	goto appsend;
+      }
+    }
+    goto drop;
+  }
+#if UIP_UDP
+  if(flag == UIP_UDP_TIMER) {
+    if(uip_udp_conn->lport != 0) {
+      uip_conn = NULL;
+      uip_sappdata = uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPUDPH_LEN];
+      uip_len = uip_slen = 0;
+      uip_flags = UIP_POLL;
+      UIP_UDP_APPCALL();
+      goto udp_send;
+    } else {
+      goto drop;
+    }
+  }
+#endif
+
+  /* This is where the input processing starts. */
+  UIP_STAT(++uip_stat.ip.recv);
+
+  /* Start of IP input header processing code. */
+
+#if UIP_CONF_IPV6
+  /* Check validity of the IP header. */
+  if((BUF->vtc & 0xf0) != 0x60)  { /* IP version and header length. */
+    UIP_STAT(++uip_stat.ip.drop);
+    UIP_STAT(++uip_stat.ip.vhlerr);
+    UIP_LOG("ipv6: invalid version.");
+    goto drop;
+  }
+#else /* UIP_CONF_IPV6 */
+  /* Check validity of the IP header. */
+  if(BUF->vhl != 0x45)  { /* IP version and header length. */
+    UIP_STAT(++uip_stat.ip.drop);
+    UIP_STAT(++uip_stat.ip.vhlerr);
+    UIP_LOG("ip: invalid version or header length.");
+    goto drop;
+  }
+#endif /* UIP_CONF_IPV6 */
+
+  /* Check the size of the packet. If the size reported to us in
+     uip_len is smaller the size reported in the IP header, we assume
+     that the packet has been corrupted in transit. If the size of
+     uip_len is larger than the size reported in the IP packet header,
+     the packet has been padded and we set uip_len to the correct
+     value.. */
+
+  if((BUF->len[0] << 8) + BUF->len[1] <= uip_len) {
+    uip_len = (BUF->len[0] << 8) + BUF->len[1];
+#if UIP_CONF_IPV6
+    uip_len += 40; /* The length reported in the IPv6 header is the
+		      length of the payload that follows the
+		      header. However, uIP uses the uip_len variable
+		      for holding the size of the entire packet,
+		      including the IP header. For IPv4 this is not a
+		      problem as the length field in the IPv4 header
+		      contains the length of the entire packet. But
+		      for IPv6 we need to add the size of the IPv6
+		      header (40 bytes). */
+#endif /* UIP_CONF_IPV6 */
+  } else {
+    UIP_LOG("ip: packet shorter than reported in IP header.");
+    goto drop;
+  }
+
+#if !UIP_CONF_IPV6
+  /* Check the fragment flag. */
+  if((BUF->ipoffset[0] & 0x3f) != 0 ||
+     BUF->ipoffset[1] != 0) {
+#if UIP_REASSEMBLY
+    uip_len = uip_reass();
+    if(uip_len == 0) {
+      goto drop;
+    }
+#else /* UIP_REASSEMBLY */
+    UIP_STAT(++uip_stat.ip.drop);
+    UIP_STAT(++uip_stat.ip.fragerr);
+    UIP_LOG("ip: fragment dropped.");
+    goto drop;
+#endif /* UIP_REASSEMBLY */
+  }
+#endif /* UIP_CONF_IPV6 */
+
+  if(uip_ipaddr_cmp(uip_hostaddr, all_zeroes_addr)) {
+    /* If we are configured to use ping IP address configuration and
+       hasn't been assigned an IP address yet, we accept all ICMP
+       packets. */
+#if UIP_PINGADDRCONF && !UIP_CONF_IPV6
+    if(BUF->proto == UIP_PROTO_ICMP) {
+      UIP_LOG("ip: possible ping config packet received.");
+      goto icmp_input;
+    } else {
+      UIP_LOG("ip: packet dropped since no address assigned.");
+      goto drop;
+    }
+#endif /* UIP_PINGADDRCONF */
+
+  } else {
+    /* If IP broadcast support is configured, we check for a broadcast
+       UDP packet, which may be destined to us. */
+#if UIP_BROADCAST
+    DEBUG_PRINTF("UDP IP checksum 0x%04x\n", uip_ipchksum());
+    if(BUF->proto == UIP_PROTO_UDP &&
+       uip_ipaddr_cmp(BUF->destipaddr, all_ones_addr)
+       /*&&
+	 uip_ipchksum() == 0xffff*/) {
+      goto udp_input;
+    }
+#endif /* UIP_BROADCAST */
+
+    /* Check if the packet is destined for our IP address. */
+#if !UIP_CONF_IPV6
+    if(!uip_ipaddr_cmp(BUF->destipaddr, uip_hostaddr)) {
+      UIP_STAT(++uip_stat.ip.drop);
+      goto drop;
+    }
+#else /* UIP_CONF_IPV6 */
+    /* For IPv6, packet reception is a little trickier as we need to
+       make sure that we listen to certain multicast addresses (all
+       hosts multicast address, and the solicited-node multicast
+       address) as well. However, we will cheat here and accept all
+       multicast packets that are sent to the ff02::/16 addresses. */
+    if(!uip_ipaddr_cmp(BUF->destipaddr, uip_hostaddr) &&
+       BUF->destipaddr[0] != HTONS(0xff02)) {
+      UIP_STAT(++uip_stat.ip.drop);
+      goto drop;
+    }
+#endif /* UIP_CONF_IPV6 */
+  }
+
+#if !UIP_CONF_IPV6
+  if(uip_ipchksum() != 0xffff) { /* Compute and check the IP header
+				    checksum. */
+    UIP_STAT(++uip_stat.ip.drop);
+    UIP_STAT(++uip_stat.ip.chkerr);
+    UIP_LOG("ip: bad checksum.");
+    goto drop;
+  }
+#endif /* UIP_CONF_IPV6 */
+
+  if(BUF->proto == UIP_PROTO_TCP) { /* Check for TCP packet. If so,
+				       proceed with TCP input
+				       processing. */
+    goto tcp_input;
+  }
+
+#if UIP_UDP
+  if(BUF->proto == UIP_PROTO_UDP) {
+    goto udp_input;
+  }
+#endif /* UIP_UDP */
+
+#if !UIP_CONF_IPV6
+  /* ICMPv4 processing code follows. */
+  if(BUF->proto != UIP_PROTO_ICMP) { /* We only allow ICMP packets from
+					here. */
+    UIP_STAT(++uip_stat.ip.drop);
+    UIP_STAT(++uip_stat.ip.protoerr);
+    UIP_LOG("ip: neither tcp nor icmp.");
+    goto drop;
+  }
+
+#if UIP_PINGADDRCONF
+ icmp_input:
+#endif /* UIP_PINGADDRCONF */
+  UIP_STAT(++uip_stat.icmp.recv);
+
+  /* ICMP echo (i.e., ping) processing. This is simple, we only change
+     the ICMP type from ECHO to ECHO_REPLY and adjust the ICMP
+     checksum before we return the packet. */
+  if(ICMPBUF->type != ICMP_ECHO) {
+    UIP_STAT(++uip_stat.icmp.drop);
+    UIP_STAT(++uip_stat.icmp.typeerr);
+    UIP_LOG("icmp: not icmp echo.");
+    goto drop;
+  }
+
+  /* If we are configured to use ping IP address assignment, we use
+     the destination IP address of this ping packet and assign it to
+     ourself. */
+#if UIP_PINGADDRCONF
+  if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) {
+    uip_hostaddr[0] = BUF->destipaddr[0];
+    uip_hostaddr[1] = BUF->destipaddr[1];
+  }
+#endif /* UIP_PINGADDRCONF */
+
+  ICMPBUF->type = ICMP_ECHO_REPLY;
+
+  if(ICMPBUF->icmpchksum >= HTONS(0xffff - (ICMP_ECHO << 8))) {
+    ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8) + 1;
+  } else {
+    ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8);
+  }
+
+  /* Swap IP addresses. */
+  uip_ipaddr_copy(BUF->destipaddr, BUF->srcipaddr);
+  uip_ipaddr_copy(BUF->srcipaddr, uip_hostaddr);
+
+  UIP_STAT(++uip_stat.icmp.sent);
+  goto send;
+
+  /* End of IPv4 input header processing code. */
+#else /* !UIP_CONF_IPV6 */
+
+  /* This is IPv6 ICMPv6 processing code. */
+  DEBUG_PRINTF("icmp6_input: length %d\n", uip_len);
+
+  if(BUF->proto != UIP_PROTO_ICMP6) { /* We only allow ICMPv6 packets from
+					 here. */
+    UIP_STAT(++uip_stat.ip.drop);
+    UIP_STAT(++uip_stat.ip.protoerr);
+    UIP_LOG("ip: neither tcp nor icmp6.");
+    goto drop;
+  }
+
+  UIP_STAT(++uip_stat.icmp.recv);
+
+  /* If we get a neighbor solicitation for our address we should send
+     a neighbor advertisement message back. */
+  if(ICMPBUF->type == ICMP6_NEIGHBOR_SOLICITATION) {
+    if(uip_ipaddr_cmp(ICMPBUF->icmp6data, uip_hostaddr)) {
+
+      if(ICMPBUF->options[0] == ICMP6_OPTION_SOURCE_LINK_ADDRESS) {
+	/* Save the sender's address in our neighbor list. */
+	uip_neighbor_add(ICMPBUF->srcipaddr, &(ICMPBUF->options[2]));
+      }
+
+      /* We should now send a neighbor advertisement back to where the
+	 neighbor solicication came from. */
+      ICMPBUF->type = ICMP6_NEIGHBOR_ADVERTISEMENT;
+      ICMPBUF->flags = ICMP6_FLAG_S; /* Solicited flag. */
+
+      ICMPBUF->reserved1 = ICMPBUF->reserved2 = ICMPBUF->reserved3 = 0;
+
+      uip_ipaddr_copy(ICMPBUF->destipaddr, ICMPBUF->srcipaddr);
+      uip_ipaddr_copy(ICMPBUF->srcipaddr, uip_hostaddr);
+      ICMPBUF->options[0] = ICMP6_OPTION_TARGET_LINK_ADDRESS;
+      ICMPBUF->options[1] = 1;  /* Options length, 1 = 8 bytes. */
+      memcpy(&(ICMPBUF->options[2]), &uip_ethaddr, sizeof(uip_ethaddr));
+      ICMPBUF->icmpchksum = 0;
+      ICMPBUF->icmpchksum = ~uip_icmp6chksum();
+      goto send;
+
+    }
+    goto drop;
+  } else if(ICMPBUF->type == ICMP6_ECHO) {
+    /* ICMP echo (i.e., ping) processing. This is simple, we only
+       change the ICMP type from ECHO to ECHO_REPLY and update the
+       ICMP checksum before we return the packet. */
+
+    ICMPBUF->type = ICMP6_ECHO_REPLY;
+
+    uip_ipaddr_copy(BUF->destipaddr, BUF->srcipaddr);
+    uip_ipaddr_copy(BUF->srcipaddr, uip_hostaddr);
+    ICMPBUF->icmpchksum = 0;
+    ICMPBUF->icmpchksum = ~uip_icmp6chksum();
+
+    UIP_STAT(++uip_stat.icmp.sent);
+    goto send;
+  } else {
+    DEBUG_PRINTF("Unknown icmp6 message type %d\n", ICMPBUF->type);
+    UIP_STAT(++uip_stat.icmp.drop);
+    UIP_STAT(++uip_stat.icmp.typeerr);
+    UIP_LOG("icmp: unknown ICMP message.");
+    goto drop;
+  }
+
+  /* End of IPv6 ICMP processing. */
+
+#endif /* !UIP_CONF_IPV6 */
+
+#if UIP_UDP
+  /* UDP input processing. */
+ udp_input:
+  /* UDP processing is really just a hack. We don't do anything to the
+     UDP/IP headers, but let the UDP application do all the hard
+     work. If the application sets uip_slen, it has a packet to
+     send. */
+#if UIP_UDP_CHECKSUMS
+  uip_len = uip_len - UIP_IPUDPH_LEN;
+  uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPUDPH_LEN];
+  if(UDPBUF->udpchksum != 0 && uip_udpchksum() != 0xffff) {
+    UIP_STAT(++uip_stat.udp.drop);
+    UIP_STAT(++uip_stat.udp.chkerr);
+    UIP_LOG("udp: bad checksum.");
+    goto drop;
+  }
+#else /* UIP_UDP_CHECKSUMS */
+  uip_len = uip_len - UIP_IPUDPH_LEN;
+#endif /* UIP_UDP_CHECKSUMS */
+
+  /* Demultiplex this UDP packet between the UDP "connections". */
+  for(uip_udp_conn = &uip_udp_conns[0];
+      uip_udp_conn < &uip_udp_conns[UIP_UDP_CONNS];
+      ++uip_udp_conn) {
+    /* If the local UDP port is non-zero, the connection is considered
+       to be used. If so, the local port number is checked against the
+       destination port number in the received packet. If the two port
+       numbers match, the remote port number is checked if the
+       connection is bound to a remote port. Finally, if the
+       connection is bound to a remote IP address, the source IP
+       address of the packet is checked. */
+    if(uip_udp_conn->lport != 0 &&
+       UDPBUF->destport == uip_udp_conn->lport &&
+       (uip_udp_conn->rport == 0 ||
+        UDPBUF->srcport == uip_udp_conn->rport) &&
+       (uip_ipaddr_cmp(uip_udp_conn->ripaddr, all_zeroes_addr) ||
+	uip_ipaddr_cmp(uip_udp_conn->ripaddr, all_ones_addr) ||
+	uip_ipaddr_cmp(BUF->srcipaddr, uip_udp_conn->ripaddr))) {
+      goto udp_found;
+    }
+  }
+  UIP_LOG("udp: no matching connection found");
+  goto drop;
+
+ udp_found:
+  UIP_STAT(++uip_stat.udp.recv);
+  uip_conn = NULL;
+  uip_flags = UIP_NEWDATA;
+  uip_sappdata = uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPUDPH_LEN];
+  uip_slen = 0;
+  UIP_UDP_APPCALL();
+ udp_send:
+  if(uip_slen == 0) {
+    goto drop;
+  }
+  uip_len = uip_slen + UIP_IPUDPH_LEN;
+
+#if UIP_CONF_IPV6
+  /* For IPv6, the IP length field does not include the IPv6 IP header
+     length. */
+  BUF->len[0] = ((uip_len - UIP_IPH_LEN) >> 8);
+  BUF->len[1] = ((uip_len - UIP_IPH_LEN) & 0xff);
+#else /* UIP_CONF_IPV6 */
+  BUF->len[0] = (uip_len >> 8);
+  BUF->len[1] = (uip_len & 0xff);
+#endif /* UIP_CONF_IPV6 */
+
+  BUF->ttl = uip_udp_conn->ttl;
+  BUF->proto = UIP_PROTO_UDP;
+
+  UDPBUF->udplen = HTONS(uip_slen + UIP_UDPH_LEN);
+  UDPBUF->udpchksum = 0;
+
+  BUF->srcport  = uip_udp_conn->lport;
+  BUF->destport = uip_udp_conn->rport;
+
+  uip_ipaddr_copy(BUF->srcipaddr, uip_hostaddr);
+  uip_ipaddr_copy(BUF->destipaddr, uip_udp_conn->ripaddr);
+
+  uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPTCPH_LEN];
+
+#if UIP_UDP_CHECKSUMS
+  /* Calculate UDP checksum. */
+  UDPBUF->udpchksum = ~(uip_udpchksum());
+  if(UDPBUF->udpchksum == 0) {
+    UDPBUF->udpchksum = 0xffff;
+  }
+#endif /* UIP_UDP_CHECKSUMS */
+  UIP_STAT(++uip_stat.udp.sent);
+  goto ip_send_nolen;
+#endif /* UIP_UDP */
+
+  /* TCP input processing. */
+ tcp_input:
+  UIP_STAT(++uip_stat.tcp.recv);
+
+  /* Start of TCP input header processing code. */
+
+  if(uip_tcpchksum() != 0xffff) {   /* Compute and check the TCP
+				       checksum. */
+    UIP_STAT(++uip_stat.tcp.drop);
+    UIP_STAT(++uip_stat.tcp.chkerr);
+    UIP_LOG("tcp: bad checksum.");
+    goto drop;
+  }
+
+
+  /* Demultiplex this segment. */
+  /* First check any active connections. */
+  for(uip_connr = &uip_conns[0]; uip_connr <= &uip_conns[UIP_CONNS - 1];
+      ++uip_connr) {
+    if(uip_connr->tcpstateflags != UIP_CLOSED &&
+       BUF->destport == uip_connr->lport &&
+       BUF->srcport == uip_connr->rport &&
+       uip_ipaddr_cmp(BUF->srcipaddr, uip_connr->ripaddr)) {
+      goto found;
+    }
+  }
+
+  /* If we didn't find and active connection that expected the packet,
+     either this packet is an old duplicate, or this is a SYN packet
+     destined for a connection in LISTEN. If the SYN flag isn't set,
+     it is an old packet and we send a RST. */
+  if((BUF->flags & TCP_CTL) != TCP_SYN) {
+    goto reset;
+  }
+
+  tmp16 = BUF->destport;
+  /* Next, check listening connections. */
+  for(c = 0; c < UIP_LISTENPORTS; ++c) {
+    if(tmp16 == uip_listenports[c])
+      goto found_listen;
+  }
+
+  /* No matching connection found, so we send a RST packet. */
+  UIP_STAT(++uip_stat.tcp.synrst);
+ reset:
+
+  /* We do not send resets in response to resets. */
+  if(BUF->flags & TCP_RST) {
+    goto drop;
+  }
+
+  UIP_STAT(++uip_stat.tcp.rst);
+
+  BUF->flags = TCP_RST | TCP_ACK;
+  uip_len = UIP_IPTCPH_LEN;
+  BUF->tcpoffset = 5 << 4;
+
+  /* Flip the seqno and ackno fields in the TCP header. */
+  c = BUF->seqno[3];
+  BUF->seqno[3] = BUF->ackno[3];
+  BUF->ackno[3] = c;
+
+  c = BUF->seqno[2];
+  BUF->seqno[2] = BUF->ackno[2];
+  BUF->ackno[2] = c;
+
+  c = BUF->seqno[1];
+  BUF->seqno[1] = BUF->ackno[1];
+  BUF->ackno[1] = c;
+
+  c = BUF->seqno[0];
+  BUF->seqno[0] = BUF->ackno[0];
+  BUF->ackno[0] = c;
+
+  /* We also have to increase the sequence number we are
+     acknowledging. If the least significant byte overflowed, we need
+     to propagate the carry to the other bytes as well. */
+  if(++BUF->ackno[3] == 0) {
+    if(++BUF->ackno[2] == 0) {
+      if(++BUF->ackno[1] == 0) {
+	++BUF->ackno[0];
+      }
+    }
+  }
+
+  /* Swap port numbers. */
+  tmp16 = BUF->srcport;
+  BUF->srcport = BUF->destport;
+  BUF->destport = tmp16;
+
+  /* Swap IP addresses. */
+  uip_ipaddr_copy(BUF->destipaddr, BUF->srcipaddr);
+  uip_ipaddr_copy(BUF->srcipaddr, uip_hostaddr);
+
+  /* And send out the RST packet! */
+  goto tcp_send_noconn;
+
+  /* This label will be jumped to if we matched the incoming packet
+     with a connection in LISTEN. In that case, we should create a new
+     connection and send a SYNACK in return. */
+ found_listen:
+  /* First we check if there are any connections avaliable. Unused
+     connections are kept in the same table as used connections, but
+     unused ones have the tcpstate set to CLOSED. Also, connections in
+     TIME_WAIT are kept track of and we'll use the oldest one if no
+     CLOSED connections are found. Thanks to Eddie C. Dost for a very
+     nice algorithm for the TIME_WAIT search. */
+  uip_connr = 0;
+  for(c = 0; c < UIP_CONNS; ++c) {
+    if(uip_conns[c].tcpstateflags == UIP_CLOSED) {
+      uip_connr = &uip_conns[c];
+      break;
+    }
+    if(uip_conns[c].tcpstateflags == UIP_TIME_WAIT) {
+      if(uip_connr == 0 ||
+	 uip_conns[c].timer > uip_connr->timer) {
+	uip_connr = &uip_conns[c];
+      }
+    }
+  }
+
+  if(uip_connr == 0) {
+    /* All connections are used already, we drop packet and hope that
+       the remote end will retransmit the packet at a time when we
+       have more spare connections. */
+    UIP_STAT(++uip_stat.tcp.syndrop);
+    UIP_LOG("tcp: found no unused connections.");
+    goto drop;
+  }
+  uip_conn = uip_connr;
+
+  /* Fill in the necessary fields for the new connection. */
+  uip_connr->rto = uip_connr->timer = UIP_RTO;
+  uip_connr->sa = 0;
+  uip_connr->sv = 4;
+  uip_connr->nrtx = 0;
+  uip_connr->lport = BUF->destport;
+  uip_connr->rport = BUF->srcport;
+  uip_ipaddr_copy(uip_connr->ripaddr, BUF->srcipaddr);
+  uip_connr->tcpstateflags = UIP_SYN_RCVD;
+
+  uip_connr->snd_nxt[0] = iss[0];
+  uip_connr->snd_nxt[1] = iss[1];
+  uip_connr->snd_nxt[2] = iss[2];
+  uip_connr->snd_nxt[3] = iss[3];
+  uip_connr->len = 1;
+
+  /* rcv_nxt should be the seqno from the incoming packet + 1. */
+  uip_connr->rcv_nxt[3] = BUF->seqno[3];
+  uip_connr->rcv_nxt[2] = BUF->seqno[2];
+  uip_connr->rcv_nxt[1] = BUF->seqno[1];
+  uip_connr->rcv_nxt[0] = BUF->seqno[0];
+  uip_add_rcv_nxt(1);
+
+  /* Parse the TCP MSS option, if present. */
+  if((BUF->tcpoffset & 0xf0) > 0x50) {
+    for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) {
+      opt = uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + c];
+      if(opt == TCP_OPT_END) {
+	/* End of options. */
+	break;
+      } else if(opt == TCP_OPT_NOOP) {
+	++c;
+	/* NOP option. */
+      } else if(opt == TCP_OPT_MSS &&
+		uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == TCP_OPT_MSS_LEN) {
+	/* An MSS option with the right option length. */
+	tmp16 = ((u16_t)uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) |
+	  (u16_t)uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN + 3 + c];
+	uip_connr->initialmss = uip_connr->mss =
+	  tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16;
+
+	/* And we are done processing options. */
+	break;
+      } else {
+	/* All other options have a length field, so that we easily
+	   can skip past them. */
+	if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) {
+	  /* If the length field is zero, the options are malformed
+	     and we don't process them further. */
+	  break;
+	}
+	c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c];
+      }
+    }
+  }
+
+  /* Our response will be a SYNACK. */
+#if UIP_ACTIVE_OPEN
+ tcp_send_synack:
+  BUF->flags = TCP_ACK;
+
+ tcp_send_syn:
+  BUF->flags |= TCP_SYN;
+#else /* UIP_ACTIVE_OPEN */
+ tcp_send_synack:
+  BUF->flags = TCP_SYN | TCP_ACK;
+#endif /* UIP_ACTIVE_OPEN */
+
+  /* We send out the TCP Maximum Segment Size option with our
+     SYNACK. */
+  BUF->optdata[0] = TCP_OPT_MSS;
+  BUF->optdata[1] = TCP_OPT_MSS_LEN;
+  BUF->optdata[2] = (UIP_TCP_MSS) / 256;
+  BUF->optdata[3] = (UIP_TCP_MSS) & 255;
+  uip_len = UIP_IPTCPH_LEN + TCP_OPT_MSS_LEN;
+  BUF->tcpoffset = ((UIP_TCPH_LEN + TCP_OPT_MSS_LEN) / 4) << 4;
+  goto tcp_send;
+
+  /* This label will be jumped to if we found an active connection. */
+ found:
+  uip_conn = uip_connr;
+  uip_flags = 0;
+  /* We do a very naive form of TCP reset processing; we just accept
+     any RST and kill our connection. We should in fact check if the
+     sequence number of this reset is wihtin our advertised window
+     before we accept the reset. */
+  if(BUF->flags & TCP_RST) {
+    uip_connr->tcpstateflags = UIP_CLOSED;
+    UIP_LOG("tcp: got reset, aborting connection.");
+    uip_flags = UIP_ABORT;
+    UIP_APPCALL();
+    goto drop;
+  }
+  /* Calculated the length of the data, if the application has sent
+     any data to us. */
+  c = (BUF->tcpoffset >> 4) << 2;
+  /* uip_len will contain the length of the actual TCP data. This is
+     calculated by subtracing the length of the TCP header (in
+     c) and the length of the IP header (20 bytes). */
+  uip_len = uip_len - c - UIP_IPH_LEN;
+
+  /* First, check if the sequence number of the incoming packet is
+     what we're expecting next. If not, we send out an ACK with the
+     correct numbers in. */
+  if(!(((uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_SYN_SENT) &&
+       ((BUF->flags & TCP_CTL) == (TCP_SYN | TCP_ACK)))) {
+    if((uip_len > 0 || ((BUF->flags & (TCP_SYN | TCP_FIN)) != 0)) &&
+       (BUF->seqno[0] != uip_connr->rcv_nxt[0] ||
+	BUF->seqno[1] != uip_connr->rcv_nxt[1] ||
+	BUF->seqno[2] != uip_connr->rcv_nxt[2] ||
+	BUF->seqno[3] != uip_connr->rcv_nxt[3])) {
+      goto tcp_send_ack;
+    }
+  }
+
+  /* Next, check if the incoming segment acknowledges any outstanding
+     data. If so, we update the sequence number, reset the length of
+     the outstanding data, calculate RTT estimations, and reset the
+     retransmission timer. */
+  if((BUF->flags & TCP_ACK) && uip_outstanding(uip_connr)) {
+    uip_add32(uip_connr->snd_nxt, uip_connr->len);
+
+    if(BUF->ackno[0] == uip_acc32[0] &&
+       BUF->ackno[1] == uip_acc32[1] &&
+       BUF->ackno[2] == uip_acc32[2] &&
+       BUF->ackno[3] == uip_acc32[3]) {
+      /* Update sequence number. */
+      uip_connr->snd_nxt[0] = uip_acc32[0];
+      uip_connr->snd_nxt[1] = uip_acc32[1];
+      uip_connr->snd_nxt[2] = uip_acc32[2];
+      uip_connr->snd_nxt[3] = uip_acc32[3];
+
+
+      /* Do RTT estimation, unless we have done retransmissions. */
+      if(uip_connr->nrtx == 0) {
+	signed char m;
+	m = uip_connr->rto - uip_connr->timer;
+	/* This is taken directly from VJs original code in his paper */
+	m = m - (uip_connr->sa >> 3);
+	uip_connr->sa += m;
+	if(m < 0) {
+	  m = -m;
+	}
+	m = m - (uip_connr->sv >> 2);
+	uip_connr->sv += m;
+	uip_connr->rto = (uip_connr->sa >> 3) + uip_connr->sv;
+
+      }
+      /* Set the acknowledged flag. */
+      uip_flags = UIP_ACKDATA;
+      /* Reset the retransmission timer. */
+      uip_connr->timer = uip_connr->rto;
+
+      /* Reset length of outstanding data. */
+      uip_connr->len = 0;
+    }
+
+  }
+
+  /* Do different things depending on in what state the connection is. */
+  switch(uip_connr->tcpstateflags & UIP_TS_MASK) {
+    /* CLOSED and LISTEN are not handled here. CLOSE_WAIT is not
+	implemented, since we force the application to close when the
+	peer sends a FIN (hence the application goes directly from
+	ESTABLISHED to LAST_ACK). */
+  case UIP_SYN_RCVD:
+    /* In SYN_RCVD we have sent out a SYNACK in response to a SYN, and
+       we are waiting for an ACK that acknowledges the data we sent
+       out the last time. Therefore, we want to have the UIP_ACKDATA
+       flag set. If so, we enter the ESTABLISHED state. */
+    if(uip_flags & UIP_ACKDATA) {
+      uip_connr->tcpstateflags = UIP_ESTABLISHED;
+      uip_flags = UIP_CONNECTED;
+      uip_connr->len = 0;
+      if(uip_len > 0) {
+        uip_flags |= UIP_NEWDATA;
+        uip_add_rcv_nxt(uip_len);
+      }
+      uip_slen = 0;
+      UIP_APPCALL();
+      goto appsend;
+    }
+    goto drop;
+#if UIP_ACTIVE_OPEN
+  case UIP_SYN_SENT:
+    /* In SYN_SENT, we wait for a SYNACK that is sent in response to
+       our SYN. The rcv_nxt is set to sequence number in the SYNACK
+       plus one, and we send an ACK. We move into the ESTABLISHED
+       state. */
+    if((uip_flags & UIP_ACKDATA) &&
+       (BUF->flags & TCP_CTL) == (TCP_SYN | TCP_ACK)) {
+
+      /* Parse the TCP MSS option, if present. */
+      if((BUF->tcpoffset & 0xf0) > 0x50) {
+	for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) {
+	  opt = uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN + c];
+	  if(opt == TCP_OPT_END) {
+	    /* End of options. */
+	    break;
+	  } else if(opt == TCP_OPT_NOOP) {
+	    ++c;
+	    /* NOP option. */
+	  } else if(opt == TCP_OPT_MSS &&
+		    uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == TCP_OPT_MSS_LEN) {
+	    /* An MSS option with the right option length. */
+	    tmp16 = (uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) |
+	      uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 3 + c];
+	    uip_connr->initialmss =
+	      uip_connr->mss = tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16;
+
+	    /* And we are done processing options. */
+	    break;
+	  } else {
+	    /* All other options have a length field, so that we easily
+	       can skip past them. */
+	    if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) {
+	      /* If the length field is zero, the options are malformed
+		 and we don't process them further. */
+	      break;
+	    }
+	    c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c];
+	  }
+	}
+      }
+      uip_connr->tcpstateflags = UIP_ESTABLISHED;
+      uip_connr->rcv_nxt[0] = BUF->seqno[0];
+      uip_connr->rcv_nxt[1] = BUF->seqno[1];
+      uip_connr->rcv_nxt[2] = BUF->seqno[2];
+      uip_connr->rcv_nxt[3] = BUF->seqno[3];
+      uip_add_rcv_nxt(1);
+      uip_flags = UIP_CONNECTED | UIP_NEWDATA;
+      uip_connr->len = 0;
+      uip_len = 0;
+      uip_slen = 0;
+      UIP_APPCALL();
+      goto appsend;
+    }
+    /* Inform the application that the connection failed */
+    uip_flags = UIP_ABORT;
+    UIP_APPCALL();
+    /* The connection is closed after we send the RST */
+    uip_conn->tcpstateflags = UIP_CLOSED;
+    goto reset;
+#endif /* UIP_ACTIVE_OPEN */
+
+  case UIP_ESTABLISHED:
+    /* In the ESTABLISHED state, we call upon the application to feed
+    data into the uip_buf. If the UIP_ACKDATA flag is set, the
+    application should put new data into the buffer, otherwise we are
+    retransmitting an old segment, and the application should put that
+    data into the buffer.
+
+    If the incoming packet is a FIN, we should close the connection on
+    this side as well, and we send out a FIN and enter the LAST_ACK
+    state. We require that there is no outstanding data; otherwise the
+    sequence numbers will be screwed up. */
+
+    if(BUF->flags & TCP_FIN && !(uip_connr->tcpstateflags & UIP_STOPPED)) {
+      if(uip_outstanding(uip_connr)) {
+	goto drop;
+      }
+      uip_add_rcv_nxt(1 + uip_len);
+      uip_flags |= UIP_CLOSE;
+      if(uip_len > 0) {
+	uip_flags |= UIP_NEWDATA;
+      }
+      UIP_APPCALL();
+      uip_connr->len = 1;
+      uip_connr->tcpstateflags = UIP_LAST_ACK;
+      uip_connr->nrtx = 0;
+    tcp_send_finack:
+      BUF->flags = TCP_FIN | TCP_ACK;
+      goto tcp_send_nodata;
+    }
+
+    /* Check the URG flag. If this is set, the segment carries urgent
+       data that we must pass to the application. */
+    if((BUF->flags & TCP_URG) != 0) {
+#if UIP_URGDATA > 0
+      uip_urglen = (BUF->urgp[0] << 8) | BUF->urgp[1];
+      if(uip_urglen > uip_len) {
+	/* There is more urgent data in the next segment to come. */
+	uip_urglen = uip_len;
+      }
+      uip_add_rcv_nxt(uip_urglen);
+      uip_len -= uip_urglen;
+      uip_urgdata = uip_appdata;
+      uip_appdata += uip_urglen;
+    } else {
+      uip_urglen = 0;
+#else /* UIP_URGDATA > 0 */
+      uip_appdata = ((char *)uip_appdata) + ((BUF->urgp[0] << 8) | BUF->urgp[1]);
+      uip_len -= (BUF->urgp[0] << 8) | BUF->urgp[1];
+#endif /* UIP_URGDATA > 0 */
+    }
+
+    /* If uip_len > 0 we have TCP data in the packet, and we flag this
+       by setting the UIP_NEWDATA flag and update the sequence number
+       we acknowledge. If the application has stopped the dataflow
+       using uip_stop(), we must not accept any data packets from the
+       remote host. */
+    if(uip_len > 0 && !(uip_connr->tcpstateflags & UIP_STOPPED)) {
+      uip_flags |= UIP_NEWDATA;
+      uip_add_rcv_nxt(uip_len);
+    }
+
+    /* Check if the available buffer space advertised by the other end
+       is smaller than the initial MSS for this connection. If so, we
+       set the current MSS to the window size to ensure that the
+       application does not send more data than the other end can
+       handle.
+
+       If the remote host advertises a zero window, we set the MSS to
+       the initial MSS so that the application will send an entire MSS
+       of data. This data will not be acknowledged by the receiver,
+       and the application will retransmit it. This is called the
+       "persistent timer" and uses the retransmission mechanim.
+    */
+    tmp16 = ((u16_t)BUF->wnd[0] << 8) + (u16_t)BUF->wnd[1];
+    if(tmp16 > uip_connr->initialmss ||
+       tmp16 == 0) {
+      tmp16 = uip_connr->initialmss;
+    }
+    uip_connr->mss = tmp16;
+
+    /* If this packet constitutes an ACK for outstanding data (flagged
+       by the UIP_ACKDATA flag, we should call the application since it
+       might want to send more data. If the incoming packet had data
+       from the peer (as flagged by the UIP_NEWDATA flag), the
+       application must also be notified.
+
+       When the application is called, the global variable uip_len
+       contains the length of the incoming data. The application can
+       access the incoming data through the global pointer
+       uip_appdata, which usually points UIP_IPTCPH_LEN + UIP_LLH_LEN
+       bytes into the uip_buf array.
+
+       If the application wishes to send any data, this data should be
+       put into the uip_appdata and the length of the data should be
+       put into uip_len. If the application don't have any data to
+       send, uip_len must be set to 0. */
+    if(uip_flags & (UIP_NEWDATA | UIP_ACKDATA)) {
+      uip_slen = 0;
+      UIP_APPCALL();
+
+    appsend:
+
+      if(uip_flags & UIP_ABORT) {
+	uip_slen = 0;
+	uip_connr->tcpstateflags = UIP_CLOSED;
+	BUF->flags = TCP_RST | TCP_ACK;
+	goto tcp_send_nodata;
+      }
+
+      if(uip_flags & UIP_CLOSE) {
+	uip_slen = 0;
+	uip_connr->len = 1;
+	uip_connr->tcpstateflags = UIP_FIN_WAIT_1;
+	uip_connr->nrtx = 0;
+	BUF->flags = TCP_FIN | TCP_ACK;
+	goto tcp_send_nodata;
+      }
+
+      /* If uip_slen > 0, the application has data to be sent. */
+      if(uip_slen > 0) {
+
+	/* If the connection has acknowledged data, the contents of
+	   the ->len variable should be discarded. */
+	if((uip_flags & UIP_ACKDATA) != 0) {
+	  uip_connr->len = 0;
+	}
+
+	/* If the ->len variable is non-zero the connection has
+	   already data in transit and cannot send anymore right
+	   now. */
+	if(uip_connr->len == 0) {
+
+	  /* The application cannot send more than what is allowed by
+	     the mss (the minumum of the MSS and the available
+	     window). */
+	  if(uip_slen > uip_connr->mss) {
+	    uip_slen = uip_connr->mss;
+	  }
+
+	  /* Remember how much data we send out now so that we know
+	     when everything has been acknowledged. */
+	  uip_connr->len = uip_slen;
+	} else {
+
+	  /* If the application already had unacknowledged data, we
+	     make sure that the application does not send (i.e.,
+	     retransmit) out more than it previously sent out. */
+	  uip_slen = uip_connr->len;
+	}
+      }
+      uip_connr->nrtx = 0;
+    apprexmit:
+      uip_appdata = uip_sappdata;
+
+      /* If the application has data to be sent, or if the incoming
+         packet had new data in it, we must send out a packet. */
+      if(uip_slen > 0 && uip_connr->len > 0) {
+	/* Add the length of the IP and TCP headers. */
+	uip_len = uip_connr->len + UIP_TCPIP_HLEN;
+	/* We always set the ACK flag in response packets. */
+	BUF->flags = TCP_ACK | TCP_PSH;
+	/* Send the packet. */
+	goto tcp_send_noopts;
+      }
+      /* If there is no data to send, just send out a pure ACK if
+	 there is newdata. */
+      if(uip_flags & UIP_NEWDATA) {
+	uip_len = UIP_TCPIP_HLEN;
+	BUF->flags = TCP_ACK;
+	goto tcp_send_noopts;
+      }
+    }
+    goto drop;
+  case UIP_LAST_ACK:
+    /* We can close this connection if the peer has acknowledged our
+       FIN. This is indicated by the UIP_ACKDATA flag. */
+    if(uip_flags & UIP_ACKDATA) {
+      uip_connr->tcpstateflags = UIP_CLOSED;
+      uip_flags = UIP_CLOSE;
+      UIP_APPCALL();
+    }
+    break;
+
+  case UIP_FIN_WAIT_1:
+    /* The application has closed the connection, but the remote host
+       hasn't closed its end yet. Thus we do nothing but wait for a
+       FIN from the other side. */
+    if(uip_len > 0) {
+      uip_add_rcv_nxt(uip_len);
+    }
+    if(BUF->flags & TCP_FIN) {
+      if(uip_flags & UIP_ACKDATA) {
+	uip_connr->tcpstateflags = UIP_TIME_WAIT;
+	uip_connr->timer = 0;
+	uip_connr->len = 0;
+      } else {
+	uip_connr->tcpstateflags = UIP_CLOSING;
+      }
+      uip_add_rcv_nxt(1);
+      uip_flags = UIP_CLOSE;
+      UIP_APPCALL();
+      goto tcp_send_ack;
+    } else if(uip_flags & UIP_ACKDATA) {
+      uip_connr->tcpstateflags = UIP_FIN_WAIT_2;
+      uip_connr->len = 0;
+      goto drop;
+    }
+    if(uip_len > 0) {
+      goto tcp_send_ack;
+    }
+    goto drop;
+
+  case UIP_FIN_WAIT_2:
+    if(uip_len > 0) {
+      uip_add_rcv_nxt(uip_len);
+    }
+    if(BUF->flags & TCP_FIN) {
+      uip_connr->tcpstateflags = UIP_TIME_WAIT;
+      uip_connr->timer = 0;
+      uip_add_rcv_nxt(1);
+      uip_flags = UIP_CLOSE;
+      UIP_APPCALL();
+      goto tcp_send_ack;
+    }
+    if(uip_len > 0) {
+      goto tcp_send_ack;
+    }
+    goto drop;
+
+  case UIP_TIME_WAIT:
+    goto tcp_send_ack;
+
+  case UIP_CLOSING:
+    if(uip_flags & UIP_ACKDATA) {
+      uip_connr->tcpstateflags = UIP_TIME_WAIT;
+      uip_connr->timer = 0;
+    }
+  }
+  goto drop;
+
+
+  /* We jump here when we are ready to send the packet, and just want
+     to set the appropriate TCP sequence numbers in the TCP header. */
+ tcp_send_ack:
+  BUF->flags = TCP_ACK;
+ tcp_send_nodata:
+  uip_len = UIP_IPTCPH_LEN;
+ tcp_send_noopts:
+  BUF->tcpoffset = (UIP_TCPH_LEN / 4) << 4;
+ tcp_send:
+  /* We're done with the input processing. We are now ready to send a
+     reply. Our job is to fill in all the fields of the TCP and IP
+     headers before calculating the checksum and finally send the
+     packet. */
+  BUF->ackno[0] = uip_connr->rcv_nxt[0];
+  BUF->ackno[1] = uip_connr->rcv_nxt[1];
+  BUF->ackno[2] = uip_connr->rcv_nxt[2];
+  BUF->ackno[3] = uip_connr->rcv_nxt[3];
+
+  BUF->seqno[0] = uip_connr->snd_nxt[0];
+  BUF->seqno[1] = uip_connr->snd_nxt[1];
+  BUF->seqno[2] = uip_connr->snd_nxt[2];
+  BUF->seqno[3] = uip_connr->snd_nxt[3];
+
+  BUF->proto = UIP_PROTO_TCP;
+
+  BUF->srcport  = uip_connr->lport;
+  BUF->destport = uip_connr->rport;
+
+  uip_ipaddr_copy(BUF->srcipaddr, uip_hostaddr);
+  uip_ipaddr_copy(BUF->destipaddr, uip_connr->ripaddr);
+
+  if(uip_connr->tcpstateflags & UIP_STOPPED) {
+    /* If the connection has issued uip_stop(), we advertise a zero
+       window so that the remote host will stop sending data. */
+    BUF->wnd[0] = BUF->wnd[1] = 0;
+  } else {
+    BUF->wnd[0] = ((UIP_RECEIVE_WINDOW) >> 8);
+    BUF->wnd[1] = ((UIP_RECEIVE_WINDOW) & 0xff);
+  }
+
+ tcp_send_noconn:
+  BUF->ttl = UIP_TTL;
+#if UIP_CONF_IPV6
+  /* For IPv6, the IP length field does not include the IPv6 IP header
+     length. */
+  BUF->len[0] = ((uip_len - UIP_IPH_LEN) >> 8);
+  BUF->len[1] = ((uip_len - UIP_IPH_LEN) & 0xff);
+#else /* UIP_CONF_IPV6 */
+  BUF->len[0] = (uip_len >> 8);
+  BUF->len[1] = (uip_len & 0xff);
+#endif /* UIP_CONF_IPV6 */
+
+  BUF->urgp[0] = BUF->urgp[1] = 0;
+
+  /* Calculate TCP checksum. */
+  BUF->tcpchksum = 0;
+  BUF->tcpchksum = ~(uip_tcpchksum());
+
+#if UIP_UDP
+ ip_send_nolen:
+#endif /* UIP_UDP */
+
+#if UIP_CONF_IPV6
+  BUF->vtc = 0x60;
+  BUF->tcflow = 0x00;
+  BUF->flow = 0x00;
+#else /* UIP_CONF_IPV6 */
+  BUF->vhl = 0x45;
+  BUF->tos = 0;
+  BUF->ipoffset[0] = BUF->ipoffset[1] = 0;
+  ++ipid;
+  BUF->ipid[0] = ipid >> 8;
+  BUF->ipid[1] = ipid & 0xff;
+  /* Calculate IP checksum. */
+  BUF->ipchksum = 0;
+  BUF->ipchksum = ~(uip_ipchksum());
+  DEBUG_PRINTF("uip ip_send_nolen: chkecum 0x%04x\n", uip_ipchksum());
+#endif /* UIP_CONF_IPV6 */
+
+  UIP_STAT(++uip_stat.tcp.sent);
+ send:
+  DEBUG_PRINTF("Sending packet with length %d (%d)\n", uip_len,
+	       (BUF->len[0] << 8) | BUF->len[1]);
+
+  UIP_STAT(++uip_stat.ip.sent);
+  /* Return and let the caller do the actual transmission. */
+  uip_flags = 0;
+  return;
+ drop:
+  uip_len = 0;
+  uip_flags = 0;
+  return;
+}
+/*---------------------------------------------------------------------------*/
+u16_t
+htons(u16_t val)
+{
+  return HTONS(val);
+}
+/*---------------------------------------------------------------------------*/
+void
+uip_send(const void *data, int len)
+{
+  if(len > 0) {
+    uip_slen = len;
+    if(data != uip_sappdata) {
+      memcpy(uip_sappdata, (data), uip_slen);
+    }
+  }
+}
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip.h
new file mode 100644
index 0000000..82da6fb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip.h
@@ -0,0 +1,1638 @@
+
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \file
+ * Header file for the uIP TCP/IP stack.
+ * \author Adam Dunkels 
+ *
+ * The uIP TCP/IP stack header file contains definitions for a number
+ * of C macros that are used by uIP programs as well as internal uIP
+ * structures, TCP/IP header structures and function declarations.
+ *
+ */
+
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip.h,v 1.40 2006/06/08 07:12:07 adam Exp $
+ *
+ */
+
+#ifndef __UIP_H__
+#define __UIP_H__
+
+#include "uipopt.h"
+
+/**
+ * Repressentation of an IP address.
+ *
+ */
+typedef u16_t uip_ip4addr_t[2];
+typedef u16_t uip_ip6addr_t[8];
+#if UIP_CONF_IPV6
+typedef uip_ip6addr_t uip_ipaddr_t;
+#else /* UIP_CONF_IPV6 */
+typedef uip_ip4addr_t uip_ipaddr_t;
+#endif /* UIP_CONF_IPV6 */
+
+/*---------------------------------------------------------------------------*/
+/* First, the functions that should be called from the
+ * system. Initialization, the periodic timer and incoming packets are
+ * handled by the following three functions.
+ */
+
+/**
+ * \defgroup uipconffunc uIP configuration functions
+ * @{
+ *
+ * The uIP configuration functions are used for setting run-time
+ * parameters in uIP such as IP addresses.
+ */
+
+/**
+ * Set the IP address of this host.
+ *
+ * The IP address is represented as a 4-byte array where the first
+ * octet of the IP address is put in the first member of the 4-byte
+ * array.
+ *
+ * Example:
+ \code
+
+ uip_ipaddr_t addr;
+
+ uip_ipaddr(&addr, 192,168,1,2);
+ uip_sethostaddr(&addr);
+
+ \endcode
+ * \param addr A pointer to an IP address of type uip_ipaddr_t;
+ *
+ * \sa uip_ipaddr()
+ *
+ * \hideinitializer
+ */
+#define uip_sethostaddr(addr) uip_ipaddr_copy(uip_hostaddr, (addr))
+
+/**
+ * Get the IP address of this host.
+ *
+ * The IP address is represented as a 4-byte array where the first
+ * octet of the IP address is put in the first member of the 4-byte
+ * array.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t hostaddr;
+
+ uip_gethostaddr(&hostaddr);
+ \endcode
+ * \param addr A pointer to a uip_ipaddr_t variable that will be
+ * filled in with the currently configured IP address.
+ *
+ * \hideinitializer
+ */
+#define uip_gethostaddr(addr) uip_ipaddr_copy((addr), uip_hostaddr)
+
+/**
+ * Set the default router's IP address.
+ *
+ * \param addr A pointer to a uip_ipaddr_t variable containing the IP
+ * address of the default router.
+ *
+ * \sa uip_ipaddr()
+ *
+ * \hideinitializer
+ */
+#define uip_setdraddr(addr) uip_ipaddr_copy(uip_draddr, (addr))
+
+/**
+ * Set the netmask.
+ *
+ * \param addr A pointer to a uip_ipaddr_t variable containing the IP
+ * address of the netmask.
+ *
+ * \sa uip_ipaddr()
+ *
+ * \hideinitializer
+ */
+#define uip_setnetmask(addr) uip_ipaddr_copy(uip_netmask, (addr))
+
+
+/**
+ * Get the default router's IP address.
+ *
+ * \param addr A pointer to a uip_ipaddr_t variable that will be
+ * filled in with the IP address of the default router.
+ *
+ * \hideinitializer
+ */
+#define uip_getdraddr(addr) uip_ipaddr_copy((addr), uip_draddr)
+
+/**
+ * Get the netmask.
+ *
+ * \param addr A pointer to a uip_ipaddr_t variable that will be
+ * filled in with the value of the netmask.
+ *
+ * \hideinitializer
+ */
+#define uip_getnetmask(addr) uip_ipaddr_copy((addr), uip_netmask)
+
+/** @} */
+
+/**
+ * \defgroup uipinit uIP initialization functions
+ * @{
+ *
+ * The uIP initialization functions are used for booting uIP.
+ */
+
+/**
+ * uIP initialization function.
+ *
+ * This function should be called at boot up to initilize the uIP
+ * TCP/IP stack.
+ */
+void uip_init(void);
+
+/**
+ * uIP initialization function.
+ *
+ * This function may be used at boot time to set the initial ip_id.
+ */
+void uip_setipid(u16_t id);
+
+/** @} */
+
+/**
+ * \defgroup uipdevfunc uIP device driver functions
+ * @{
+ *
+ * These functions are used by a network device driver for interacting
+ * with uIP.
+ */
+
+/**
+ * Process an incoming packet.
+ *
+ * This function should be called when the device driver has received
+ * a packet from the network. The packet from the device driver must
+ * be present in the uip_buf buffer, and the length of the packet
+ * should be placed in the uip_len variable.
+ *
+ * When the function returns, there may be an outbound packet placed
+ * in the uip_buf packet buffer. If so, the uip_len variable is set to
+ * the length of the packet. If no packet is to be sent out, the
+ * uip_len variable is set to 0.
+ *
+ * The usual way of calling the function is presented by the source
+ * code below.
+ \code
+  uip_len = devicedriver_poll();
+  if(uip_len > 0) {
+    uip_input();
+    if(uip_len > 0) {
+      devicedriver_send();
+    }
+  }
+ \endcode
+ *
+ * \note If you are writing a uIP device driver that needs ARP
+ * (Address Resolution Protocol), e.g., when running uIP over
+ * Ethernet, you will need to call the uIP ARP code before calling
+ * this function:
+ \code
+  #define BUF ((struct uip_eth_hdr *)&uip_buf[0])
+  uip_len = ethernet_devicedrver_poll();
+  if(uip_len > 0) {
+    if(BUF->type == HTONS(UIP_ETHTYPE_IP)) {
+      uip_arp_ipin();
+      uip_input();
+      if(uip_len > 0) {
+        uip_arp_out();
+	ethernet_devicedriver_send();
+      }
+    } else if(BUF->type == HTONS(UIP_ETHTYPE_ARP)) {
+      uip_arp_arpin();
+      if(uip_len > 0) {
+	ethernet_devicedriver_send();
+      }
+    }
+ \endcode
+ *
+ * \hideinitializer
+ */
+#define uip_input()        uip_process(UIP_DATA)
+
+/**
+ * Periodic processing for a connection identified by its number.
+ *
+ * This function does the necessary periodic processing (timers,
+ * polling) for a uIP TCP conneciton, and should be called when the
+ * periodic uIP timer goes off. It should be called for every
+ * connection, regardless of whether they are open of closed.
+ *
+ * When the function returns, it may have an outbound packet waiting
+ * for service in the uIP packet buffer, and if so the uip_len
+ * variable is set to a value larger than zero. The device driver
+ * should be called to send out the packet.
+ *
+ * The ususal way of calling the function is through a for() loop like
+ * this:
+ \code
+  for(i = 0; i < UIP_CONNS; ++i) {
+    uip_periodic(i);
+    if(uip_len > 0) {
+      devicedriver_send();
+    }
+  }
+ \endcode
+ *
+ * \note If you are writing a uIP device driver that needs ARP
+ * (Address Resolution Protocol), e.g., when running uIP over
+ * Ethernet, you will need to call the uip_arp_out() function before
+ * calling the device driver:
+ \code
+  for(i = 0; i < UIP_CONNS; ++i) {
+    uip_periodic(i);
+    if(uip_len > 0) {
+      uip_arp_out();
+      ethernet_devicedriver_send();
+    }
+  }
+ \endcode
+ *
+ * \param conn The number of the connection which is to be periodically polled.
+ *
+ * \hideinitializer
+ */
+#define uip_periodic(conn) do { uip_conn = &uip_conns[conn]; \
+                                uip_process(UIP_TIMER); } while (0)
+
+/**
+ *
+ *
+ */
+#define uip_conn_active(conn) (uip_conns[conn].tcpstateflags != UIP_CLOSED)
+
+/**
+ * Perform periodic processing for a connection identified by a pointer
+ * to its structure.
+ *
+ * Same as uip_periodic() but takes a pointer to the actual uip_conn
+ * struct instead of an integer as its argument. This function can be
+ * used to force periodic processing of a specific connection.
+ *
+ * \param conn A pointer to the uip_conn struct for the connection to
+ * be processed.
+ *
+ * \hideinitializer
+ */
+#define uip_periodic_conn(conn) do { uip_conn = conn; \
+                                     uip_process(UIP_TIMER); } while (0)
+
+/**
+ * Reuqest that a particular connection should be polled.
+ *
+ * Similar to uip_periodic_conn() but does not perform any timer
+ * processing. The application is polled for new data.
+ *
+ * \param conn A pointer to the uip_conn struct for the connection to
+ * be processed.
+ *
+ * \hideinitializer
+ */
+#define uip_poll_conn(conn) do { uip_conn = conn; \
+                                 uip_process(UIP_POLL_REQUEST); } while (0)
+
+
+#if UIP_UDP
+/**
+ * Periodic processing for a UDP connection identified by its number.
+ *
+ * This function is essentially the same as uip_periodic(), but for
+ * UDP connections. It is called in a similar fashion as the
+ * uip_periodic() function:
+ \code
+  for(i = 0; i < UIP_UDP_CONNS; i++) {
+    uip_udp_periodic(i);
+    if(uip_len > 0) {
+      devicedriver_send();
+    }
+  }
+ \endcode
+ *
+ * \note As for the uip_periodic() function, special care has to be
+ * taken when using uIP together with ARP and Ethernet:
+ \code
+  for(i = 0; i < UIP_UDP_CONNS; i++) {
+    uip_udp_periodic(i);
+    if(uip_len > 0) {
+      uip_arp_out();
+      ethernet_devicedriver_send();
+    }
+  }
+ \endcode
+ *
+ * \param conn The number of the UDP connection to be processed.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_periodic(conn) do { uip_udp_conn = &uip_udp_conns[conn]; \
+                                uip_process(UIP_UDP_TIMER); } while (0)
+
+/**
+ * Periodic processing for a UDP connection identified by a pointer to
+ * its structure.
+ *
+ * Same as uip_udp_periodic() but takes a pointer to the actual
+ * uip_conn struct instead of an integer as its argument. This
+ * function can be used to force periodic processing of a specific
+ * connection.
+ *
+ * \param conn A pointer to the uip_udp_conn struct for the connection
+ * to be processed.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_periodic_conn(conn) do { uip_udp_conn = conn; \
+                                         uip_process(UIP_UDP_TIMER); } while (0)
+
+
+#endif /* UIP_UDP */
+
+/**
+ * The uIP packet buffer.
+ *
+ * The uip_buf array is used to hold incoming and outgoing
+ * packets. The device driver should place incoming data into this
+ * buffer. When sending data, the device driver should read the link
+ * level headers and the TCP/IP headers from this buffer. The size of
+ * the link level headers is configured by the UIP_LLH_LEN define.
+ *
+ * \note The application data need not be placed in this buffer, so
+ * the device driver must read it from the place pointed to by the
+ * uip_appdata pointer as illustrated by the following example:
+ \code
+ void
+ devicedriver_send(void)
+ {
+    hwsend(&uip_buf[0], UIP_LLH_LEN);
+    if(uip_len <= UIP_LLH_LEN + UIP_TCPIP_HLEN) {
+      hwsend(&uip_buf[UIP_LLH_LEN], uip_len - UIP_LLH_LEN);
+    } else {
+      hwsend(&uip_buf[UIP_LLH_LEN], UIP_TCPIP_HLEN);
+      hwsend(uip_appdata, uip_len - UIP_TCPIP_HLEN - UIP_LLH_LEN);
+    }
+ }
+ \endcode
+ */
+#ifndef UIP_CONF_EXTERNAL_BUFFER
+	extern u8_t uip_buf[UIP_BUFSIZE+2];
+#else
+	extern unsigned char *uip_buf;
+#endif
+
+/** @} */
+
+/*---------------------------------------------------------------------------*/
+/* Functions that are used by the uIP application program. Opening and
+ * closing connections, sending and receiving data, etc. is all
+ * handled by the functions below.
+*/
+/**
+ * \defgroup uipappfunc uIP application functions
+ * @{
+ *
+ * Functions used by an application running of top of uIP.
+ */
+
+/**
+ * Start listening to the specified port.
+ *
+ * \note Since this function expects the port number in network byte
+ * order, a conversion using HTONS() or htons() is necessary.
+ *
+ \code
+ uip_listen(HTONS(80));
+ \endcode
+ *
+ * \param port A 16-bit port number in network byte order.
+ */
+void uip_listen(u16_t port);
+
+/**
+ * Stop listening to the specified port.
+ *
+ * \note Since this function expects the port number in network byte
+ * order, a conversion using HTONS() or htons() is necessary.
+ *
+ \code
+ uip_unlisten(HTONS(80));
+ \endcode
+ *
+ * \param port A 16-bit port number in network byte order.
+ */
+void uip_unlisten(u16_t port);
+
+/**
+ * Connect to a remote host using TCP.
+ *
+ * This function is used to start a new connection to the specified
+ * port on the specied host. It allocates a new connection identifier,
+ * sets the connection to the SYN_SENT state and sets the
+ * retransmission timer to 0. This will cause a TCP SYN segment to be
+ * sent out the next time this connection is periodically processed,
+ * which usually is done within 0.5 seconds after the call to
+ * uip_connect().
+ *
+ * \note This function is avaliable only if support for active open
+ * has been configured by defining UIP_ACTIVE_OPEN to 1 in uipopt.h.
+ *
+ * \note Since this function requires the port number to be in network
+ * byte order, a conversion using HTONS() or htons() is necessary.
+ *
+ \code
+ uip_ipaddr_t ipaddr;
+
+ uip_ipaddr(&ipaddr, 192,168,1,2);
+ uip_connect(&ipaddr, HTONS(80));
+ \endcode
+ *
+ * \param ripaddr The IP address of the remote hot.
+ *
+ * \param port A 16-bit port number in network byte order.
+ *
+ * \return A pointer to the uIP connection identifier for the new connection,
+ * or NULL if no connection could be allocated.
+ *
+ */
+struct uip_conn *uip_connect(uip_ipaddr_t *ripaddr, u16_t port);
+
+
+
+/**
+ * \internal
+ *
+ * Check if a connection has outstanding (i.e., unacknowledged) data.
+ *
+ * \param conn A pointer to the uip_conn structure for the connection.
+ *
+ * \hideinitializer
+ */
+#define uip_outstanding(conn) ((conn)->len)
+
+/**
+ * Send data on the current connection.
+ *
+ * This function is used to send out a single segment of TCP
+ * data. Only applications that have been invoked by uIP for event
+ * processing can send data.
+ *
+ * The amount of data that actually is sent out after a call to this
+ * funcion is determined by the maximum amount of data TCP allows. uIP
+ * will automatically crop the data so that only the appropriate
+ * amount of data is sent. The function uip_mss() can be used to query
+ * uIP for the amount of data that actually will be sent.
+ *
+ * \note This function does not guarantee that the sent data will
+ * arrive at the destination. If the data is lost in the network, the
+ * application will be invoked with the uip_rexmit() event being
+ * set. The application will then have to resend the data using this
+ * function.
+ *
+ * \param data A pointer to the data which is to be sent.
+ *
+ * \param len The maximum amount of data bytes to be sent.
+ *
+ * \hideinitializer
+ */
+void uip_send(const void *data, int len);
+
+/**
+ * The length of any incoming data that is currently avaliable (if avaliable)
+ * in the uip_appdata buffer.
+ *
+ * The test function uip_data() must first be used to check if there
+ * is any data available at all.
+ *
+ * \hideinitializer
+ */
+/*void uip_datalen(void);*/
+#define uip_datalen()       uip_len
+
+/**
+ * The length of any out-of-band data (urgent data) that has arrived
+ * on the connection.
+ *
+ * \note The configuration parameter UIP_URGDATA must be set for this
+ * function to be enabled.
+ *
+ * \hideinitializer
+ */
+#define uip_urgdatalen()    uip_urglen
+
+/**
+ * Close the current connection.
+ *
+ * This function will close the current connection in a nice way.
+ *
+ * \hideinitializer
+ */
+#define uip_close()         (uip_flags = UIP_CLOSE)
+
+/**
+ * Abort the current connection.
+ *
+ * This function will abort (reset) the current connection, and is
+ * usually used when an error has occured that prevents using the
+ * uip_close() function.
+ *
+ * \hideinitializer
+ */
+#define uip_abort()         (uip_flags = UIP_ABORT)
+
+/**
+ * Tell the sending host to stop sending data.
+ *
+ * This function will close our receiver's window so that we stop
+ * receiving data for the current connection.
+ *
+ * \hideinitializer
+ */
+#define uip_stop()          (uip_conn->tcpstateflags |= UIP_STOPPED)
+
+/**
+ * Find out if the current connection has been previously stopped with
+ * uip_stop().
+ *
+ * \hideinitializer
+ */
+#define uip_stopped(conn)   ((conn)->tcpstateflags & UIP_STOPPED)
+
+/**
+ * Restart the current connection, if is has previously been stopped
+ * with uip_stop().
+ *
+ * This function will open the receiver's window again so that we
+ * start receiving data for the current connection.
+ *
+ * \hideinitializer
+ */
+#define uip_restart()         do { uip_flags |= UIP_NEWDATA; \
+                                   uip_conn->tcpstateflags &= ~UIP_STOPPED; \
+                              } while(0)
+
+
+/* uIP tests that can be made to determine in what state the current
+   connection is, and what the application function should do. */
+
+/**
+ * Is the current connection a UDP connection?
+ *
+ * This function checks whether the current connection is a UDP connection.
+ *
+ * \hideinitializer
+ *
+ */
+#define uip_udpconnection() (uip_conn == NULL)
+
+/**
+ * Is new incoming data available?
+ *
+ * Will reduce to non-zero if there is new data for the application
+ * present at the uip_appdata pointer. The size of the data is
+ * avaliable through the uip_len variable.
+ *
+ * \hideinitializer
+ */
+#define uip_newdata()   (uip_flags & UIP_NEWDATA)
+
+/**
+ * Has previously sent data been acknowledged?
+ *
+ * Will reduce to non-zero if the previously sent data has been
+ * acknowledged by the remote host. This means that the application
+ * can send new data.
+ *
+ * \hideinitializer
+ */
+#define uip_acked()   (uip_flags & UIP_ACKDATA)
+
+/**
+ * Has the connection just been connected?
+ *
+ * Reduces to non-zero if the current connection has been connected to
+ * a remote host. This will happen both if the connection has been
+ * actively opened (with uip_connect()) or passively opened (with
+ * uip_listen()).
+ *
+ * \hideinitializer
+ */
+#define uip_connected() (uip_flags & UIP_CONNECTED)
+
+/**
+ * Has the connection been closed by the other end?
+ *
+ * Is non-zero if the connection has been closed by the remote
+ * host. The application may then do the necessary clean-ups.
+ *
+ * \hideinitializer
+ */
+#define uip_closed()    (uip_flags & UIP_CLOSE)
+
+/**
+ * Has the connection been aborted by the other end?
+ *
+ * Non-zero if the current connection has been aborted (reset) by the
+ * remote host.
+ *
+ * \hideinitializer
+ */
+#define uip_aborted()    (uip_flags & UIP_ABORT)
+
+/**
+ * Has the connection timed out?
+ *
+ * Non-zero if the current connection has been aborted due to too many
+ * retransmissions.
+ *
+ * \hideinitializer
+ */
+#define uip_timedout()    (uip_flags & UIP_TIMEDOUT)
+
+/**
+ * Do we need to retransmit previously data?
+ *
+ * Reduces to non-zero if the previously sent data has been lost in
+ * the network, and the application should retransmit it. The
+ * application should send the exact same data as it did the last
+ * time, using the uip_send() function.
+ *
+ * \hideinitializer
+ */
+#define uip_rexmit()     (uip_flags & UIP_REXMIT)
+
+/**
+ * Is the connection being polled by uIP?
+ *
+ * Is non-zero if the reason the application is invoked is that the
+ * current connection has been idle for a while and should be
+ * polled.
+ *
+ * The polling event can be used for sending data without having to
+ * wait for the remote host to send data.
+ *
+ * \hideinitializer
+ */
+#define uip_poll()       (uip_flags & UIP_POLL)
+
+/**
+ * Get the initial maxium segment size (MSS) of the current
+ * connection.
+ *
+ * \hideinitializer
+ */
+#define uip_initialmss()             (uip_conn->initialmss)
+
+/**
+ * Get the current maxium segment size that can be sent on the current
+ * connection.
+ *
+ * The current maxiumum segment size that can be sent on the
+ * connection is computed from the receiver's window and the MSS of
+ * the connection (which also is available by calling
+ * uip_initialmss()).
+ *
+ * \hideinitializer
+ */
+#define uip_mss()             (uip_conn->mss)
+
+/**
+ * Set up a new UDP connection.
+ *
+ * This function sets up a new UDP connection. The function will
+ * automatically allocate an unused local port for the new
+ * connection. However, another port can be chosen by using the
+ * uip_udp_bind() call, after the uip_udp_new() function has been
+ * called.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t addr;
+ struct uip_udp_conn *c;
+
+ uip_ipaddr(&addr, 192,168,2,1);
+ c = uip_udp_new(&addr, HTONS(12345));
+ if(c != NULL) {
+   uip_udp_bind(c, HTONS(12344));
+ }
+ \endcode
+ * \param ripaddr The IP address of the remote host.
+ *
+ * \param rport The remote port number in network byte order.
+ *
+ * \return The uip_udp_conn structure for the new connection or NULL
+ * if no connection could be allocated.
+ */
+struct uip_udp_conn *uip_udp_new(uip_ipaddr_t *ripaddr, u16_t rport);
+
+/**
+ * Removed a UDP connection.
+ *
+ * \param conn A pointer to the uip_udp_conn structure for the connection.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_remove(conn) (conn)->lport = 0
+
+/**
+ * Bind a UDP connection to a local port.
+ *
+ * \param conn A pointer to the uip_udp_conn structure for the
+ * connection.
+ *
+ * \param port The local port number, in network byte order.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_bind(conn, port) (conn)->lport = port
+
+/**
+ * Send a UDP datagram of length len on the current connection.
+ *
+ * This function can only be called in response to a UDP event (poll
+ * or newdata). The data must be present in the uip_buf buffer, at the
+ * place pointed to by the uip_appdata pointer.
+ *
+ * \param len The length of the data in the uip_buf buffer.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_send(len) uip_send((char *)uip_appdata, len)
+
+/** @} */
+
+/* uIP convenience and converting functions. */
+
+/**
+ * \defgroup uipconvfunc uIP conversion functions
+ * @{
+ *
+ * These functions can be used for converting between different data
+ * formats used by uIP.
+ */
+
+/**
+ * Construct an IP address from four bytes.
+ *
+ * This function constructs an IP address of the type that uIP handles
+ * internally from four bytes. The function is handy for specifying IP
+ * addresses to use with e.g. the uip_connect() function.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr;
+ struct uip_conn *c;
+
+ uip_ipaddr(&ipaddr, 192,168,1,2);
+ c = uip_connect(&ipaddr, HTONS(80));
+ \endcode
+ *
+ * \param addr A pointer to a uip_ipaddr_t variable that will be
+ * filled in with the IP address.
+ *
+ * \param addr0 The first octet of the IP address.
+ * \param addr1 The second octet of the IP address.
+ * \param addr2 The third octet of the IP address.
+ * \param addr3 The forth octet of the IP address.
+ *
+ * \hideinitializer
+ */
+#define uip_ipaddr(addr, addr0,addr1,addr2,addr3) do { \
+                     ((u16_t *)(addr))[0] = HTONS(((addr0) << 8) | (addr1)); \
+                     ((u16_t *)(addr))[1] = HTONS(((addr2) << 8) | (addr3)); \
+                  } while(0)
+
+/**
+ * Construct an IPv6 address from eight 16-bit words.
+ *
+ * This function constructs an IPv6 address.
+ *
+ * \hideinitializer
+ */
+#define uip_ip6addr(addr, addr0,addr1,addr2,addr3,addr4,addr5,addr6,addr7) do { \
+                     ((u16_t *)(addr))[0] = HTONS((addr0)); \
+                     ((u16_t *)(addr))[1] = HTONS((addr1)); \
+                     ((u16_t *)(addr))[2] = HTONS((addr2)); \
+                     ((u16_t *)(addr))[3] = HTONS((addr3)); \
+                     ((u16_t *)(addr))[4] = HTONS((addr4)); \
+                     ((u16_t *)(addr))[5] = HTONS((addr5)); \
+                     ((u16_t *)(addr))[6] = HTONS((addr6)); \
+                     ((u16_t *)(addr))[7] = HTONS((addr7)); \
+                  } while(0)
+
+/**
+ * Copy an IP address to another IP address.
+ *
+ * Copies an IP address from one place to another.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr1, ipaddr2;
+
+ uip_ipaddr(&ipaddr1, 192,16,1,2);
+ uip_ipaddr_copy(&ipaddr2, &ipaddr1);
+ \endcode
+ *
+ * \param dest The destination for the copy.
+ * \param src The source from where to copy.
+ *
+ * \hideinitializer
+ */
+#if !UIP_CONF_IPV6
+#define uip_ipaddr_copy(dest, src) do { \
+                     ((u16_t *)dest)[0] = ((u16_t *)src)[0]; \
+                     ((u16_t *)dest)[1] = ((u16_t *)src)[1]; \
+                  } while(0)
+#else /* !UIP_CONF_IPV6 */
+#define uip_ipaddr_copy(dest, src) memcpy(dest, src, sizeof(uip_ip6addr_t))
+#endif /* !UIP_CONF_IPV6 */
+
+/**
+ * Compare two IP addresses
+ *
+ * Compares two IP addresses.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr1, ipaddr2;
+
+ uip_ipaddr(&ipaddr1, 192,16,1,2);
+ if(uip_ipaddr_cmp(&ipaddr2, &ipaddr1)) {
+    printf("They are the same");
+ }
+ \endcode
+ *
+ * \param addr1 The first IP address.
+ * \param addr2 The second IP address.
+ *
+ * \hideinitializer
+ */
+#if !UIP_CONF_IPV6
+#define uip_ipaddr_cmp(addr1, addr2) (((u16_t *)addr1)[0] == ((u16_t *)addr2)[0] && \
+				      ((u16_t *)addr1)[1] == ((u16_t *)addr2)[1])
+#else /* !UIP_CONF_IPV6 */
+#define uip_ipaddr_cmp(addr1, addr2) (memcmp(addr1, addr2, sizeof(uip_ip6addr_t)) == 0)
+#endif /* !UIP_CONF_IPV6 */
+
+/**
+ * Compare two IP addresses with netmasks
+ *
+ * Compares two IP addresses with netmasks. The masks are used to mask
+ * out the bits that are to be compared.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr1, ipaddr2, mask;
+
+ uip_ipaddr(&mask, 255,255,255,0);
+ uip_ipaddr(&ipaddr1, 192,16,1,2);
+ uip_ipaddr(&ipaddr2, 192,16,1,3);
+ if(uip_ipaddr_maskcmp(&ipaddr1, &ipaddr2, &mask)) {
+    printf("They are the same");
+ }
+ \endcode
+ *
+ * \param addr1 The first IP address.
+ * \param addr2 The second IP address.
+ * \param mask The netmask.
+ *
+ * \hideinitializer
+ */
+#define uip_ipaddr_maskcmp(addr1, addr2, mask) \
+                          (((((u16_t *)addr1)[0] & ((u16_t *)mask)[0]) == \
+                            (((u16_t *)addr2)[0] & ((u16_t *)mask)[0])) && \
+                           ((((u16_t *)addr1)[1] & ((u16_t *)mask)[1]) == \
+                            (((u16_t *)addr2)[1] & ((u16_t *)mask)[1])))
+
+
+/**
+ * Mask out the network part of an IP address.
+ *
+ * Masks out the network part of an IP address, given the address and
+ * the netmask.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr1, ipaddr2, netmask;
+
+ uip_ipaddr(&ipaddr1, 192,16,1,2);
+ uip_ipaddr(&netmask, 255,255,255,0);
+ uip_ipaddr_mask(&ipaddr2, &ipaddr1, &netmask);
+ \endcode
+ *
+ * In the example above, the variable "ipaddr2" will contain the IP
+ * address 192.168.1.0.
+ *
+ * \param dest Where the result is to be placed.
+ * \param src The IP address.
+ * \param mask The netmask.
+ *
+ * \hideinitializer
+ */
+#define uip_ipaddr_mask(dest, src, mask) do { \
+                     ((u16_t *)dest)[0] = ((u16_t *)src)[0] & ((u16_t *)mask)[0]; \
+                     ((u16_t *)dest)[1] = ((u16_t *)src)[1] & ((u16_t *)mask)[1]; \
+                  } while(0)
+
+/**
+ * Pick the first octet of an IP address.
+ *
+ * Picks out the first octet of an IP address.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr;
+ u8_t octet;
+
+ uip_ipaddr(&ipaddr, 1,2,3,4);
+ octet = uip_ipaddr1(&ipaddr);
+ \endcode
+ *
+ * In the example above, the variable "octet" will contain the value 1.
+ *
+ * \hideinitializer
+ */
+#define uip_ipaddr1(addr) (htons(((u16_t *)(addr))[0]) >> 8)
+
+/**
+ * Pick the second octet of an IP address.
+ *
+ * Picks out the second octet of an IP address.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr;
+ u8_t octet;
+
+ uip_ipaddr(&ipaddr, 1,2,3,4);
+ octet = uip_ipaddr2(&ipaddr);
+ \endcode
+ *
+ * In the example above, the variable "octet" will contain the value 2.
+ *
+ * \hideinitializer
+ */
+#define uip_ipaddr2(addr) (htons(((u16_t *)(addr))[0]) & 0xff)
+
+/**
+ * Pick the third octet of an IP address.
+ *
+ * Picks out the third octet of an IP address.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr;
+ u8_t octet;
+
+ uip_ipaddr(&ipaddr, 1,2,3,4);
+ octet = uip_ipaddr3(&ipaddr);
+ \endcode
+ *
+ * In the example above, the variable "octet" will contain the value 3.
+ *
+ * \hideinitializer
+ */
+#define uip_ipaddr3(addr) (htons(((u16_t *)(addr))[1]) >> 8)
+
+/**
+ * Pick the fourth octet of an IP address.
+ *
+ * Picks out the fourth octet of an IP address.
+ *
+ * Example:
+ \code
+ uip_ipaddr_t ipaddr;
+ u8_t octet;
+
+ uip_ipaddr(&ipaddr, 1,2,3,4);
+ octet = uip_ipaddr4(&ipaddr);
+ \endcode
+ *
+ * In the example above, the variable "octet" will contain the value 4.
+ *
+ * \hideinitializer
+ */
+#define uip_ipaddr4(addr) (htons(((u16_t *)(addr))[1]) & 0xff)
+
+/**
+ * Convert 16-bit quantity from host byte order to network byte order.
+ *
+ * This macro is primarily used for converting constants from host
+ * byte order to network byte order. For converting variables to
+ * network byte order, use the htons() function instead.
+ *
+ * \hideinitializer
+ */
+#ifndef HTONS
+#   if UIP_BYTE_ORDER == UIP_BIG_ENDIAN
+#      define HTONS(n) (n)
+#   else /* UIP_BYTE_ORDER == UIP_BIG_ENDIAN */
+#      define HTONS(n) (u16_t)((((u16_t) (n)) << 8) | (((u16_t) (n)) >> 8))
+#   endif /* UIP_BYTE_ORDER == UIP_BIG_ENDIAN */
+#else
+#error "HTONS already defined!"
+#endif /* HTONS */
+
+/**
+ * Convert 16-bit quantity from host byte order to network byte order.
+ *
+ * This function is primarily used for converting variables from host
+ * byte order to network byte order. For converting constants to
+ * network byte order, use the HTONS() macro instead.
+ */
+#ifndef htons
+u16_t htons(u16_t val);
+#endif /* htons */
+#ifndef ntohs
+#define ntohs htons
+#endif
+
+/** @} */
+
+/**
+ * Pointer to the application data in the packet buffer.
+ *
+ * This pointer points to the application data when the application is
+ * called. If the application wishes to send data, the application may
+ * use this space to write the data into before calling uip_send().
+ */
+extern void *uip_appdata;
+
+#if UIP_URGDATA > 0
+/* u8_t *uip_urgdata:
+ *
+ * This pointer points to any urgent data that has been received. Only
+ * present if compiled with support for urgent data (UIP_URGDATA).
+ */
+extern void *uip_urgdata;
+#endif /* UIP_URGDATA > 0 */
+
+
+/**
+ * \defgroup uipdrivervars Variables used in uIP device drivers
+ * @{
+ *
+ * uIP has a few global variables that are used in device drivers for
+ * uIP.
+ */
+
+/**
+ * The length of the packet in the uip_buf buffer.
+ *
+ * The global variable uip_len holds the length of the packet in the
+ * uip_buf buffer.
+ *
+ * When the network device driver calls the uIP input function,
+ * uip_len should be set to the length of the packet in the uip_buf
+ * buffer.
+ *
+ * When sending packets, the device driver should use the contents of
+ * the uip_len variable to determine the length of the outgoing
+ * packet.
+ *
+ */
+extern u16_t uip_len;
+
+/** @} */
+
+#if UIP_URGDATA > 0
+extern u16_t uip_urglen, uip_surglen;
+#endif /* UIP_URGDATA > 0 */
+
+
+/**
+ * Representation of a uIP TCP connection.
+ *
+ * The uip_conn structure is used for identifying a connection. All
+ * but one field in the structure are to be considered read-only by an
+ * application. The only exception is the appstate field whos purpose
+ * is to let the application store application-specific state (e.g.,
+ * file pointers) for the connection. The type of this field is
+ * configured in the "uipopt.h" header file.
+ */
+struct uip_conn {
+  uip_ipaddr_t ripaddr;   /**< The IP address of the remote host. */
+
+  u16_t lport;        /**< The local TCP port, in network byte order. */
+  u16_t rport;        /**< The local remote TCP port, in network byte
+			 order. */
+
+  u8_t rcv_nxt[4];    /**< The sequence number that we expect to
+			 receive next. */
+  u8_t snd_nxt[4];    /**< The sequence number that was last sent by
+                         us. */
+  u16_t len;          /**< Length of the data that was previously sent. */
+  u16_t mss;          /**< Current maximum segment size for the
+			 connection. */
+  u16_t initialmss;   /**< Initial maximum segment size for the
+			 connection. */
+  u8_t sa;            /**< Retransmission time-out calculation state
+			 variable. */
+  u8_t sv;            /**< Retransmission time-out calculation state
+			 variable. */
+  u8_t rto;           /**< Retransmission time-out. */
+  u8_t tcpstateflags; /**< TCP state and flags. */
+  u8_t timer;         /**< The retransmission timer. */
+  u8_t nrtx;          /**< The number of retransmissions for the last
+			 segment sent. */
+
+  /** The application state. */
+  uip_tcp_appstate_t appstate;
+};
+
+
+/**
+ * Pointer to the current TCP connection.
+ *
+ * The uip_conn pointer can be used to access the current TCP
+ * connection.
+ */
+extern struct uip_conn *uip_conn;
+/* The array containing all uIP connections. */
+extern struct uip_conn uip_conns[UIP_CONNS];
+/**
+ * \addtogroup uiparch
+ * @{
+ */
+
+/**
+ * 4-byte array used for the 32-bit sequence number calculations.
+ */
+extern u8_t uip_acc32[4];
+
+/** @} */
+
+
+#if UIP_UDP
+/**
+ * Representation of a uIP UDP connection.
+ */
+struct uip_udp_conn {
+  uip_ipaddr_t ripaddr;   /**< The IP address of the remote peer. */
+  u16_t lport;        /**< The local port number in network byte order. */
+  u16_t rport;        /**< The remote port number in network byte order. */
+  u8_t  ttl;          /**< Default time-to-live. */
+
+  /** The application state. */
+  uip_udp_appstate_t appstate;
+};
+
+/**
+ * The current UDP connection.
+ */
+extern struct uip_udp_conn *uip_udp_conn;
+extern struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS];
+#endif /* UIP_UDP */
+
+/**
+ * The structure holding the TCP/IP statistics that are gathered if
+ * UIP_STATISTICS is set to 1.
+ *
+ */
+struct uip_stats {
+  struct {
+    uip_stats_t drop;     /**< Number of dropped packets at the IP
+			     layer. */
+    uip_stats_t recv;     /**< Number of received packets at the IP
+			     layer. */
+    uip_stats_t sent;     /**< Number of sent packets at the IP
+			     layer. */
+    uip_stats_t vhlerr;   /**< Number of packets dropped due to wrong
+			     IP version or header length. */
+    uip_stats_t hblenerr; /**< Number of packets dropped due to wrong
+			     IP length, high byte. */
+    uip_stats_t lblenerr; /**< Number of packets dropped due to wrong
+			     IP length, low byte. */
+    uip_stats_t fragerr;  /**< Number of packets dropped since they
+			     were IP fragments. */
+    uip_stats_t chkerr;   /**< Number of packets dropped due to IP
+			     checksum errors. */
+    uip_stats_t protoerr; /**< Number of packets dropped since they
+			     were neither ICMP, UDP nor TCP. */
+  } ip;                   /**< IP statistics. */
+  struct {
+    uip_stats_t drop;     /**< Number of dropped ICMP packets. */
+    uip_stats_t recv;     /**< Number of received ICMP packets. */
+    uip_stats_t sent;     /**< Number of sent ICMP packets. */
+    uip_stats_t typeerr;  /**< Number of ICMP packets with a wrong
+			     type. */
+  } icmp;                 /**< ICMP statistics. */
+  struct {
+    uip_stats_t drop;     /**< Number of dropped TCP segments. */
+    uip_stats_t recv;     /**< Number of recived TCP segments. */
+    uip_stats_t sent;     /**< Number of sent TCP segments. */
+    uip_stats_t chkerr;   /**< Number of TCP segments with a bad
+			     checksum. */
+    uip_stats_t ackerr;   /**< Number of TCP segments with a bad ACK
+			     number. */
+    uip_stats_t rst;      /**< Number of recevied TCP RST (reset) segments. */
+    uip_stats_t rexmit;   /**< Number of retransmitted TCP segments. */
+    uip_stats_t syndrop;  /**< Number of dropped SYNs due to too few
+			     connections was avaliable. */
+    uip_stats_t synrst;   /**< Number of SYNs for closed ports,
+			     triggering a RST. */
+  } tcp;                  /**< TCP statistics. */
+#if UIP_UDP
+  struct {
+    uip_stats_t drop;     /**< Number of dropped UDP segments. */
+    uip_stats_t recv;     /**< Number of recived UDP segments. */
+    uip_stats_t sent;     /**< Number of sent UDP segments. */
+    uip_stats_t chkerr;   /**< Number of UDP segments with a bad
+			     checksum. */
+  } udp;                  /**< UDP statistics. */
+#endif /* UIP_UDP */
+};
+
+/**
+ * The uIP TCP/IP statistics.
+ *
+ * This is the variable in which the uIP TCP/IP statistics are gathered.
+ */
+extern struct uip_stats uip_stat;
+
+
+/*---------------------------------------------------------------------------*/
+/* All the stuff below this point is internal to uIP and should not be
+ * used directly by an application or by a device driver.
+ */
+/*---------------------------------------------------------------------------*/
+/* u8_t uip_flags:
+ *
+ * When the application is called, uip_flags will contain the flags
+ * that are defined in this file. Please read below for more
+ * infomation.
+ */
+extern u8_t uip_flags;
+
+/* The following flags may be set in the global variable uip_flags
+   before calling the application callback. The UIP_ACKDATA,
+   UIP_NEWDATA, and UIP_CLOSE flags may both be set at the same time,
+   whereas the others are mutualy exclusive. Note that these flags
+   should *NOT* be accessed directly, but only through the uIP
+   functions/macros. */
+
+#define UIP_ACKDATA   1     /* Signifies that the outstanding data was
+			       acked and the application should send
+			       out new data instead of retransmitting
+			       the last data. */
+#define UIP_NEWDATA   2     /* Flags the fact that the peer has sent
+			       us new data. */
+#define UIP_REXMIT    4     /* Tells the application to retransmit the
+			       data that was last sent. */
+#define UIP_POLL      8     /* Used for polling the application, to
+			       check if the application has data that
+			       it wants to send. */
+#define UIP_CLOSE     16    /* The remote host has closed the
+			       connection, thus the connection has
+			       gone away. Or the application signals
+			       that it wants to close the
+			       connection. */
+#define UIP_ABORT     32    /* The remote host has aborted the
+			       connection, thus the connection has
+			       gone away. Or the application signals
+			       that it wants to abort the
+			       connection. */
+#define UIP_CONNECTED 64    /* We have got a connection from a remote
+                               host and have set up a new connection
+                               for it, or an active connection has
+                               been successfully established. */
+
+#define UIP_TIMEDOUT  128   /* The connection has been aborted due to
+			       too many retransmissions. */
+
+/* uip_process(flag):
+ *
+ * The actual uIP function which does all the work.
+ */
+void uip_process(u8_t flag);
+
+/* The following flags are passed as an argument to the uip_process()
+   function. They are used to distinguish between the two cases where
+   uip_process() is called. It can be called either because we have
+   incoming data that should be processed, or because the periodic
+   timer has fired. These values are never used directly, but only in
+   the macrose defined in this file. */
+
+#define UIP_DATA          1     /* Tells uIP that there is incoming
+				   data in the uip_buf buffer. The
+				   length of the data is stored in the
+				   global variable uip_len. */
+#define UIP_TIMER         2     /* Tells uIP that the periodic timer
+				   has fired. */
+#define UIP_POLL_REQUEST  3     /* Tells uIP that a connection should
+				   be polled. */
+#define UIP_UDP_SEND_CONN 4     /* Tells uIP that a UDP datagram
+				   should be constructed in the
+				   uip_buf buffer. */
+#if UIP_UDP
+#define UIP_UDP_TIMER     5
+#endif /* UIP_UDP */
+
+/* The TCP states used in the uip_conn->tcpstateflags. */
+#define UIP_CLOSED      0
+#define UIP_SYN_RCVD    1
+#define UIP_SYN_SENT    2
+#define UIP_ESTABLISHED 3
+#define UIP_FIN_WAIT_1  4
+#define UIP_FIN_WAIT_2  5
+#define UIP_CLOSING     6
+#define UIP_TIME_WAIT   7
+#define UIP_LAST_ACK    8
+#define UIP_TS_MASK     15
+
+#define UIP_STOPPED      16
+
+/* The TCP and IP headers. */
+
+#ifdef __ICCARM__
+	#pragma pack(1)
+#endif
+
+struct uip_tcpip_hdr {
+#if UIP_CONF_IPV6
+  /* IPv6 header. */
+  u8_t vtc,
+    tcflow;
+  u16_t flow;
+  u8_t len[2];
+  u8_t proto, ttl;
+  uip_ip6addr_t srcipaddr, destipaddr;
+#else /* UIP_CONF_IPV6 */
+  /* IPv4 header. */
+  u8_t vhl,
+    tos,
+    len[2],
+    ipid[2],
+    ipoffset[2],
+    ttl,
+    proto;
+  u16_t ipchksum;
+  u16_t srcipaddr[2],
+    destipaddr[2];
+#endif /* UIP_CONF_IPV6 */
+
+  /* TCP header. */
+  u16_t srcport,
+    destport;
+  u8_t seqno[4],
+    ackno[4],
+    tcpoffset,
+    flags,
+    wnd[2];
+  u16_t tcpchksum;
+  u8_t urgp[2];
+  u8_t optdata[4];
+} PACK_STRUCT_END;
+
+#ifdef __ICCARM__
+	#pragma pack()
+#endif
+
+/* The ICMP and IP headers. */
+#ifdef __ICCARM__
+	#pragma pack(1)
+#endif
+
+struct uip_icmpip_hdr {
+#if UIP_CONF_IPV6
+  /* IPv6 header. */
+  u8_t vtc,
+    tcf;
+  u16_t flow;
+  u8_t len[2];
+  u8_t proto, ttl;
+  uip_ip6addr_t srcipaddr, destipaddr;
+#else /* UIP_CONF_IPV6 */
+  /* IPv4 header. */
+  u8_t vhl,
+    tos,
+    len[2],
+    ipid[2],
+    ipoffset[2],
+    ttl,
+    proto;
+  u16_t ipchksum;
+  u16_t srcipaddr[2],
+    destipaddr[2];
+#endif /* UIP_CONF_IPV6 */
+
+  /* ICMP (echo) header. */
+  u8_t type, icode;
+  u16_t icmpchksum;
+#if !UIP_CONF_IPV6
+  u16_t id, seqno;
+#else /* !UIP_CONF_IPV6 */
+  u8_t flags, reserved1, reserved2, reserved3;
+  u8_t icmp6data[16];
+  u8_t options[1];
+#endif /* !UIP_CONF_IPV6 */
+} PACK_STRUCT_END;
+
+#ifdef __ICCARM__
+	#pragma pack()
+#endif
+
+
+/* The UDP and IP headers. */
+#ifdef __ICCARM__
+	#pragma pack(1)
+#endif
+
+struct uip_udpip_hdr {
+#if UIP_CONF_IPV6
+  /* IPv6 header. */
+  u8_t vtc,
+    tcf;
+  u16_t flow;
+  u8_t len[2];
+  u8_t proto, ttl;
+  uip_ip6addr_t srcipaddr, destipaddr;
+#else /* UIP_CONF_IPV6 */
+  /* IP header. */
+  u8_t vhl,
+    tos,
+    len[2],
+    ipid[2],
+    ipoffset[2],
+    ttl,
+    proto;
+  u16_t ipchksum;
+  u16_t srcipaddr[2],
+    destipaddr[2];
+#endif /* UIP_CONF_IPV6 */
+
+  /* UDP header. */
+  u16_t srcport,
+    destport;
+  u16_t udplen;
+  u16_t udpchksum;
+} PACK_STRUCT_END;
+
+#ifdef __ICCARM__
+	#pragma pack()
+#endif
+
+
+
+/**
+ * The buffer size available for user data in the \ref uip_buf buffer.
+ *
+ * This macro holds the available size for user data in the \ref
+ * uip_buf buffer. The macro is intended to be used for checking
+ * bounds of available user data.
+ *
+ * Example:
+ \code
+ snprintf(uip_appdata, UIP_APPDATA_SIZE, "%u\n", i);
+ \endcode
+ *
+ * \hideinitializer
+ */
+#define UIP_APPDATA_SIZE (UIP_BUFSIZE - UIP_LLH_LEN - UIP_TCPIP_HLEN)
+
+
+#define UIP_PROTO_ICMP  1
+#define UIP_PROTO_TCP   6
+#define UIP_PROTO_UDP   17
+#define UIP_PROTO_ICMP6 58
+
+/* Header sizes. */
+#if UIP_CONF_IPV6
+#define UIP_IPH_LEN    40
+#else /* UIP_CONF_IPV6 */
+#define UIP_IPH_LEN    20    /* Size of IP header */
+#endif /* UIP_CONF_IPV6 */
+#define UIP_UDPH_LEN    8    /* Size of UDP header */
+#define UIP_TCPH_LEN   20    /* Size of TCP header */
+#define UIP_IPUDPH_LEN (UIP_UDPH_LEN + UIP_IPH_LEN)    /* Size of IP +
+							  UDP
+							  header */
+#define UIP_IPTCPH_LEN (UIP_TCPH_LEN + UIP_IPH_LEN)    /* Size of IP +
+							  TCP
+							  header */
+#define UIP_TCPIP_HLEN UIP_IPTCPH_LEN
+
+
+#if UIP_FIXEDADDR
+extern const uip_ipaddr_t uip_hostaddr, uip_netmask, uip_draddr;
+#else /* UIP_FIXEDADDR */
+extern uip_ipaddr_t uip_hostaddr, uip_netmask, uip_draddr;
+#endif /* UIP_FIXEDADDR */
+
+
+
+/**
+ * Representation of a 48-bit Ethernet address.
+ */
+#ifdef __ICCARM__
+	#pragma pack(1)
+#endif
+
+struct uip_eth_addr {
+  u8_t addr[6];
+} PACK_STRUCT_END;
+
+#ifdef __ICCARM__
+	#pragma pack()
+#endif
+
+/**
+ * Calculate the Internet checksum over a buffer.
+ *
+ * The Internet checksum is the one's complement of the one's
+ * complement sum of all 16-bit words in the buffer.
+ *
+ * See RFC1071.
+ *
+ * \param buf A pointer to the buffer over which the checksum is to be
+ * computed.
+ *
+ * \param len The length of the buffer over which the checksum is to
+ * be computed.
+ *
+ * \return The Internet checksum of the buffer.
+ */
+u16_t uip_chksum(u16_t *buf, u16_t len);
+
+/**
+ * Calculate the IP header checksum of the packet header in uip_buf.
+ *
+ * The IP header checksum is the Internet checksum of the 20 bytes of
+ * the IP header.
+ *
+ * \return The IP header checksum of the IP header in the uip_buf
+ * buffer.
+ */
+u16_t uip_ipchksum(void);
+
+/**
+ * Calculate the TCP checksum of the packet in uip_buf and uip_appdata.
+ *
+ * The TCP checksum is the Internet checksum of data contents of the
+ * TCP segment, and a pseudo-header as defined in RFC793.
+ *
+ * \return The TCP checksum of the TCP segment in uip_buf and pointed
+ * to by uip_appdata.
+ */
+u16_t uip_tcpchksum(void);
+
+/**
+ * Calculate the UDP checksum of the packet in uip_buf and uip_appdata.
+ *
+ * The UDP checksum is the Internet checksum of data contents of the
+ * UDP segment, and a pseudo-header as defined in RFC768.
+ *
+ * \return The UDP checksum of the UDP segment in uip_buf and pointed
+ * to by uip_appdata.
+ */
+u16_t uip_udpchksum(void);
+
+
+#endif /* __UIP_H__ */
+
+
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arch.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arch.h
new file mode 100644
index 0000000..5ea4578
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arch.h
@@ -0,0 +1,138 @@
+/**
+ * \addtogroup uip
+ * {@
+ */
+
+/**
+ * \defgroup uiparch Architecture specific uIP functions
+ * @{
+ *
+ * The functions in the architecture specific module implement the IP
+ * check sum and 32-bit additions.
+ *
+ * The IP checksum calculation is the most computationally expensive
+ * operation in the TCP/IP stack and it therefore pays off to
+ * implement this in efficient assembler. The purpose of the uip-arch
+ * module is to let the checksum functions to be implemented in
+ * architecture specific assembler.
+ *
+ */
+
+/**
+ * \file
+ * Declarations of architecture specific functions.
+ * \author Adam Dunkels 
+ */
+
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip_arch.h,v 1.2 2006/06/07 09:15:19 adam Exp $
+ *
+ */
+
+#ifndef __UIP_ARCH_H__
+#define __UIP_ARCH_H__
+
+#include "uip.h"
+
+/**
+ * Carry out a 32-bit addition.
+ *
+ * Because not all architectures for which uIP is intended has native
+ * 32-bit arithmetic, uIP uses an external C function for doing the
+ * required 32-bit additions in the TCP protocol processing. This
+ * function should add the two arguments and place the result in the
+ * global variable uip_acc32.
+ *
+ * \note The 32-bit integer pointed to by the op32 parameter and the
+ * result in the uip_acc32 variable are in network byte order (big
+ * endian).
+ *
+ * \param op32 A pointer to a 4-byte array representing a 32-bit
+ * integer in network byte order (big endian).
+ *
+ * \param op16 A 16-bit integer in host byte order.
+ */
+void uip_add32(u8_t *op32, u16_t op16);
+
+/**
+ * Calculate the Internet checksum over a buffer.
+ *
+ * The Internet checksum is the one's complement of the one's
+ * complement sum of all 16-bit words in the buffer.
+ *
+ * See RFC1071.
+ *
+ * \note This function is not called in the current version of uIP,
+ * but future versions might make use of it.
+ *
+ * \param buf A pointer to the buffer over which the checksum is to be
+ * computed.
+ *
+ * \param len The length of the buffer over which the checksum is to
+ * be computed.
+ *
+ * \return The Internet checksum of the buffer.
+ */
+u16_t uip_chksum(u16_t *buf, u16_t len);
+
+/**
+ * Calculate the IP header checksum of the packet header in uip_buf.
+ *
+ * The IP header checksum is the Internet checksum of the 20 bytes of
+ * the IP header.
+ *
+ * \return The IP header checksum of the IP header in the uip_buf
+ * buffer.
+ */
+u16_t uip_ipchksum(void);
+
+/**
+ * Calculate the TCP checksum of the packet in uip_buf and uip_appdata.
+ *
+ * The TCP checksum is the Internet checksum of data contents of the
+ * TCP segment, and a pseudo-header as defined in RFC793.
+ *
+ * \note The uip_appdata pointer that points to the packet data may
+ * point anywhere in memory, so it is not possible to simply calculate
+ * the Internet checksum of the contents of the uip_buf buffer.
+ *
+ * \return The TCP checksum of the TCP segment in uip_buf and pointed
+ * to by uip_appdata.
+ */
+u16_t uip_tcpchksum(void);
+
+u16_t uip_udpchksum(void);
+
+/** @} */
+/** @} */
+
+#endif /* __UIP_ARCH_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arp.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arp.c
new file mode 100644
index 0000000..44c7975
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arp.c
@@ -0,0 +1,439 @@
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \defgroup uiparp uIP Address Resolution Protocol
+ * @{
+ *
+ * The Address Resolution Protocol ARP is used for mapping between IP
+ * addresses and link level addresses such as the Ethernet MAC
+ * addresses. ARP uses broadcast queries to ask for the link level
+ * address of a known IP address and the host which is configured with
+ * the IP address for which the query was meant, will respond with its
+ * link level address.
+ *
+ * \note This ARP implementation only supports Ethernet.
+ */
+
+/**
+ * \file
+ * Implementation of the ARP Address Resolution Protocol.
+ * \author Adam Dunkels 
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip_arp.c,v 1.8 2006/06/02 23:36:21 adam Exp $
+ *
+ */
+
+
+#include "uip_arp.h"
+
+#include 
+
+#ifdef __ICCARM__
+	#pragma pack(1)
+#endif
+
+struct arp_hdr {
+  struct uip_eth_hdr ethhdr;
+  u16_t hwtype;
+  u16_t protocol;
+  u8_t hwlen;
+  u8_t protolen;
+  u16_t opcode;
+  struct uip_eth_addr shwaddr;
+  u16_t sipaddr[2];
+  struct uip_eth_addr dhwaddr;
+  u16_t dipaddr[2];
+} PACK_STRUCT_END;
+
+#ifdef __ICCARM__
+	#pragma pack()
+#endif
+
+#ifdef __ICCARM__
+	#pragma pack(1)
+#endif
+
+struct ethip_hdr {
+  struct uip_eth_hdr ethhdr;
+  /* IP header. */
+  u8_t vhl,
+    tos,
+    len[2],
+    ipid[2],
+    ipoffset[2],
+    ttl,
+    proto;
+  u16_t ipchksum;
+  u16_t srcipaddr[2],
+    destipaddr[2];
+} PACK_STRUCT_END;
+
+#ifdef __ICCARM__
+	#pragma pack()
+#endif
+
+#define ARP_REQUEST 1
+#define ARP_REPLY   2
+
+#define ARP_HWTYPE_ETH 1
+
+struct arp_entry {
+  u16_t ipaddr[2];
+  struct uip_eth_addr ethaddr;
+  u8_t time;
+};
+
+static const struct uip_eth_addr broadcast_ethaddr =
+  {{0xff,0xff,0xff,0xff,0xff,0xff}};
+static const u16_t broadcast_ipaddr[2] = {0xffff,0xffff};
+
+static struct arp_entry arp_table[UIP_ARPTAB_SIZE];
+static u16_t ipaddr[2];
+static u8_t i, c;
+
+static u8_t arptime;
+static u8_t tmpage;
+
+#define BUF   ((struct arp_hdr *)&uip_buf[0])
+#define IPBUF ((struct ethip_hdr *)&uip_buf[0])
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Initialize the ARP module.
+ *
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+uip_arp_init(void)
+{
+  for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+    memset(arp_table[i].ipaddr, 0, 4);
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Periodic ARP processing function.
+ *
+ * This function performs periodic timer processing in the ARP module
+ * and should be called at regular intervals. The recommended interval
+ * is 10 seconds between the calls.
+ *
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+uip_arp_timer(void)
+{
+  struct arp_entry *tabptr;
+
+  ++arptime;
+  for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+    tabptr = &arp_table[i];
+    if((tabptr->ipaddr[0] | tabptr->ipaddr[1]) != 0 &&
+       arptime - tabptr->time >= UIP_ARP_MAXAGE) {
+      memset(tabptr->ipaddr, 0, 4);
+    }
+  }
+
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+uip_arp_update(u16_t *ipaddr, struct uip_eth_addr *ethaddr)
+{
+  register struct arp_entry *tabptr;
+  /* Walk through the ARP mapping table and try to find an entry to
+     update. If none is found, the IP -> MAC address mapping is
+     inserted in the ARP table. */
+  for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+
+    tabptr = &arp_table[i];
+    /* Only check those entries that are actually in use. */
+    if(tabptr->ipaddr[0] != 0 &&
+       tabptr->ipaddr[1] != 0) {
+
+      /* Check if the source IP address of the incoming packet matches
+         the IP address in this ARP table entry. */
+      if(ipaddr[0] == tabptr->ipaddr[0] &&
+	 ipaddr[1] == tabptr->ipaddr[1]) {
+	
+	/* An old entry found, update this and return. */
+	memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6);
+	tabptr->time = arptime;
+
+	return;
+      }
+    }
+  }
+
+  /* If we get here, no existing ARP table entry was found, so we
+     create one. */
+
+  /* First, we try to find an unused entry in the ARP table. */
+  for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+    tabptr = &arp_table[i];
+    if(tabptr->ipaddr[0] == 0 &&
+       tabptr->ipaddr[1] == 0) {
+      break;
+    }
+  }
+
+  /* If no unused entry is found, we try to find the oldest entry and
+     throw it away. */
+  if(i == UIP_ARPTAB_SIZE) {
+    tmpage = 0;
+    c = 0;
+    for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+      tabptr = &arp_table[i];
+      if(arptime - tabptr->time > tmpage) {
+	tmpage = arptime - tabptr->time;
+	c = i;
+      }
+    }
+    i = c;
+    tabptr = &arp_table[i];
+  }
+
+  /* Now, i is the ARP table entry which we will fill with the new
+     information. */
+  memcpy(tabptr->ipaddr, ipaddr, 4);
+  memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6);
+  tabptr->time = arptime;
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * ARP processing for incoming IP packets
+ *
+ * This function should be called by the device driver when an IP
+ * packet has been received. The function will check if the address is
+ * in the ARP cache, and if so the ARP cache entry will be
+ * refreshed. If no ARP cache entry was found, a new one is created.
+ *
+ * This function expects an IP packet with a prepended Ethernet header
+ * in the uip_buf[] buffer, and the length of the packet in the global
+ * variable uip_len.
+ */
+/*-----------------------------------------------------------------------------------*/
+#if 1
+void
+uip_arp_ipin(void)
+{
+  uip_len -= sizeof(struct uip_eth_hdr);
+	
+  /* Only insert/update an entry if the source IP address of the
+     incoming IP packet comes from a host on the local network. */
+  if((IPBUF->srcipaddr[0] & uip_netmask[0]) !=
+     (uip_hostaddr[0] & uip_netmask[0])) {
+    return;
+  }
+  if((IPBUF->srcipaddr[1] & uip_netmask[1]) !=
+     (uip_hostaddr[1] & uip_netmask[1])) {
+    return;
+  }
+  uip_arp_update(IPBUF->srcipaddr, &(IPBUF->ethhdr.src));
+
+  return;
+}
+#endif /* 0 */
+/*-----------------------------------------------------------------------------------*/
+/**
+ * ARP processing for incoming ARP packets.
+ *
+ * This function should be called by the device driver when an ARP
+ * packet has been received. The function will act differently
+ * depending on the ARP packet type: if it is a reply for a request
+ * that we previously sent out, the ARP cache will be filled in with
+ * the values from the ARP reply. If the incoming ARP packet is an ARP
+ * request for our IP address, an ARP reply packet is created and put
+ * into the uip_buf[] buffer.
+ *
+ * When the function returns, the value of the global variable uip_len
+ * indicates whether the device driver should send out a packet or
+ * not. If uip_len is zero, no packet should be sent. If uip_len is
+ * non-zero, it contains the length of the outbound packet that is
+ * present in the uip_buf[] buffer.
+ *
+ * This function expects an ARP packet with a prepended Ethernet
+ * header in the uip_buf[] buffer, and the length of the packet in the
+ * global variable uip_len.
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+uip_arp_arpin(void)
+{
+
+  if(uip_len < sizeof(struct arp_hdr)) {
+    uip_len = 0;
+    return;
+  }
+  uip_len = 0;
+
+  switch(BUF->opcode) {
+  case HTONS(ARP_REQUEST):
+    /* ARP request. If it asked for our address, we send out a
+       reply. */
+    if(uip_ipaddr_cmp(BUF->dipaddr, uip_hostaddr)) {
+      /* First, we register the one who made the request in our ARP
+	 table, since it is likely that we will do more communication
+	 with this host in the future. */
+      uip_arp_update(BUF->sipaddr, &BUF->shwaddr);
+
+      /* The reply opcode is 2. */
+      BUF->opcode = HTONS(2);
+
+      memcpy(BUF->dhwaddr.addr, BUF->shwaddr.addr, 6);
+      memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6);
+      memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6);
+      memcpy(BUF->ethhdr.dest.addr, BUF->dhwaddr.addr, 6);
+
+      BUF->dipaddr[0] = BUF->sipaddr[0];
+      BUF->dipaddr[1] = BUF->sipaddr[1];
+      BUF->sipaddr[0] = uip_hostaddr[0];
+      BUF->sipaddr[1] = uip_hostaddr[1];
+
+      BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP);
+      uip_len = sizeof(struct arp_hdr);
+    }
+    break;
+  case HTONS(ARP_REPLY):
+    /* ARP reply. We insert or update the ARP table if it was meant
+       for us. */
+    if(uip_ipaddr_cmp(BUF->dipaddr, uip_hostaddr)) {
+      uip_arp_update(BUF->sipaddr, &BUF->shwaddr);
+    }
+    break;
+  }
+
+  return;
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Prepend Ethernet header to an outbound IP packet and see if we need
+ * to send out an ARP request.
+ *
+ * This function should be called before sending out an IP packet. The
+ * function checks the destination IP address of the IP packet to see
+ * what Ethernet MAC address that should be used as a destination MAC
+ * address on the Ethernet.
+ *
+ * If the destination IP address is in the local network (determined
+ * by logical ANDing of netmask and our IP address), the function
+ * checks the ARP cache to see if an entry for the destination IP
+ * address is found. If so, an Ethernet header is prepended and the
+ * function returns. If no ARP cache entry is found for the
+ * destination IP address, the packet in the uip_buf[] is replaced by
+ * an ARP request packet for the IP address. The IP packet is dropped
+ * and it is assumed that they higher level protocols (e.g., TCP)
+ * eventually will retransmit the dropped packet.
+ *
+ * If the destination IP address is not on the local network, the IP
+ * address of the default router is used instead.
+ *
+ * When the function returns, a packet is present in the uip_buf[]
+ * buffer, and the length of the packet is in the global variable
+ * uip_len.
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+uip_arp_out(void)
+{
+  struct arp_entry *tabptr;
+
+  /* Find the destination IP address in the ARP table and construct
+     the Ethernet header. If the destination IP addres isn't on the
+     local network, we use the default router's IP address instead.
+
+     If not ARP table entry is found, we overwrite the original IP
+     packet with an ARP request for the IP address. */
+
+  /* First check if destination is a local broadcast. */
+  if(uip_ipaddr_cmp(IPBUF->destipaddr, broadcast_ipaddr)) {
+    memcpy(IPBUF->ethhdr.dest.addr, broadcast_ethaddr.addr, 6);
+  } else {
+    /* Check if the destination address is on the local network. */
+    if(!uip_ipaddr_maskcmp(IPBUF->destipaddr, uip_hostaddr, uip_netmask)) {
+      /* Destination address was not on the local network, so we need to
+	 use the default router's IP address instead of the destination
+	 address when determining the MAC address. */
+      uip_ipaddr_copy(ipaddr, uip_draddr);
+    } else {
+      /* Else, we use the destination IP address. */
+      uip_ipaddr_copy(ipaddr, IPBUF->destipaddr);
+    }
+
+    for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+      tabptr = &arp_table[i];
+      if(uip_ipaddr_cmp(ipaddr, tabptr->ipaddr)) {
+	break;
+      }
+    }
+
+    if(i == UIP_ARPTAB_SIZE) {
+      /* The destination address was not in our ARP table, so we
+	 overwrite the IP packet with an ARP request. */
+
+      memset(BUF->ethhdr.dest.addr, 0xff, 6);
+      memset(BUF->dhwaddr.addr, 0x00, 6);
+      memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6);
+      memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6);
+
+      uip_ipaddr_copy(BUF->dipaddr, ipaddr);
+      uip_ipaddr_copy(BUF->sipaddr, uip_hostaddr);
+      BUF->opcode = HTONS(ARP_REQUEST); /* ARP request. */
+      BUF->hwtype = HTONS(ARP_HWTYPE_ETH);
+      BUF->protocol = HTONS(UIP_ETHTYPE_IP);
+      BUF->hwlen = 6;
+      BUF->protolen = 4;
+      BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP);
+
+      uip_appdata = &uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN];
+
+      uip_len = sizeof(struct arp_hdr);
+      return;
+    }
+
+    /* Build an ethernet header. */
+    memcpy(IPBUF->ethhdr.dest.addr, tabptr->ethaddr.addr, 6);
+  }
+  memcpy(IPBUF->ethhdr.src.addr, uip_ethaddr.addr, 6);
+
+  IPBUF->ethhdr.type = HTONS(UIP_ETHTYPE_IP);
+
+  uip_len += sizeof(struct uip_eth_hdr);
+}
+/*-----------------------------------------------------------------------------------*/
+
+/** @} */
+/** @} */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arp.h
new file mode 100644
index 0000000..b6b2b66
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arp.h
@@ -0,0 +1,152 @@
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \addtogroup uiparp
+ * @{
+ */
+
+/**
+ * \file
+ * Macros and definitions for the ARP module.
+ * \author Adam Dunkels 
+ */
+
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip_arp.h,v 1.5 2006/06/11 21:46:39 adam Exp $
+ *
+ */
+
+#ifndef __UIP_ARP_H__
+#define __UIP_ARP_H__
+
+#include "uip.h"
+
+
+extern struct uip_eth_addr uip_ethaddr;
+
+/**
+ * The Ethernet header.
+ */
+#ifdef __ICCARM__
+	#pragma pack(1)
+#endif
+
+struct uip_eth_hdr {
+  struct uip_eth_addr dest;
+  struct uip_eth_addr src;
+  u16_t type;
+}PACK_STRUCT_END;
+
+#ifdef __ICCARM__
+	#pragma pack()
+#endif
+
+#define UIP_ETHTYPE_ARP 0x0806
+#define UIP_ETHTYPE_IP  0x0800
+#define UIP_ETHTYPE_IP6 0x86dd
+
+
+/* The uip_arp_init() function must be called before any of the other
+   ARP functions. */
+void uip_arp_init(void);
+
+/* The uip_arp_ipin() function should be called whenever an IP packet
+   arrives from the Ethernet. This function refreshes the ARP table or
+   inserts a new mapping if none exists. The function assumes that an
+   IP packet with an Ethernet header is present in the uip_buf buffer
+   and that the length of the packet is in the uip_len variable. */
+void uip_arp_ipin(void);
+//#define uip_arp_ipin()
+
+/* The uip_arp_arpin() should be called when an ARP packet is received
+   by the Ethernet driver. This function also assumes that the
+   Ethernet frame is present in the uip_buf buffer. When the
+   uip_arp_arpin() function returns, the contents of the uip_buf
+   buffer should be sent out on the Ethernet if the uip_len variable
+   is > 0. */
+void uip_arp_arpin(void);
+
+/* The uip_arp_out() function should be called when an IP packet
+   should be sent out on the Ethernet. This function creates an
+   Ethernet header before the IP header in the uip_buf buffer. The
+   Ethernet header will have the correct Ethernet MAC destination
+   address filled in if an ARP table entry for the destination IP
+   address (or the IP address of the default router) is present. If no
+   such table entry is found, the IP packet is overwritten with an ARP
+   request and we rely on TCP to retransmit the packet that was
+   overwritten. In any case, the uip_len variable holds the length of
+   the Ethernet frame that should be transmitted. */
+void uip_arp_out(void);
+
+/* The uip_arp_timer() function should be called every ten seconds. It
+   is responsible for flushing old entries in the ARP table. */
+void uip_arp_timer(void);
+
+/** @} */
+
+/**
+ * \addtogroup uipconffunc
+ * @{
+ */
+
+
+/**
+ * Specifiy the Ethernet MAC address.
+ *
+ * The ARP code needs to know the MAC address of the Ethernet card in
+ * order to be able to respond to ARP queries and to generate working
+ * Ethernet headers.
+ *
+ * \note This macro only specifies the Ethernet MAC address to the ARP
+ * code. It cannot be used to change the MAC address of the Ethernet
+ * card.
+ *
+ * \param eaddr A pointer to a struct uip_eth_addr containing the
+ * Ethernet MAC address of the Ethernet card.
+ *
+ * \hideinitializer
+ */
+#define uip_setethaddr(eaddr) do {uip_ethaddr.addr[0] = eaddr.addr[0]; \
+                              uip_ethaddr.addr[1] = eaddr.addr[1];\
+                              uip_ethaddr.addr[2] = eaddr.addr[2];\
+                              uip_ethaddr.addr[3] = eaddr.addr[3];\
+                              uip_ethaddr.addr[4] = eaddr.addr[4];\
+                              uip_ethaddr.addr[5] = eaddr.addr[5];} while(0)
+
+/** @} */
+/** @} */
+
+#endif /* __UIP_ARP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uiplib.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uiplib.c
new file mode 100644
index 0000000..647b0b2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uiplib.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2004, Adam Dunkels and the Swedish Institute of
+ * Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * $Id: uiplib.c,v 1.2 2006/06/12 08:00:31 adam Exp $
+ *
+ */
+
+
+#include "uip.h"
+#include "uiplib.h"
+
+
+/*-----------------------------------------------------------------------------------*/
+unsigned char
+uiplib_ipaddrconv(char *addrstr, unsigned char *ipaddr)
+{
+  unsigned char tmp;
+  char c;
+  unsigned char i, j;
+
+  tmp = 0;
+  
+  for(i = 0; i < 4; ++i) {
+    j = 0;
+    do {
+      c = *addrstr;
+      ++j;
+      if(j > 4) {
+	return 0;
+      }
+      if(c == '.' || c == 0) {
+	*ipaddr = tmp;
+	++ipaddr;
+	tmp = 0;
+      } else if(c >= '0' && c <= '9') {
+	tmp = (tmp * 10) + (c - '0');
+      } else {
+	return 0;
+      }
+      ++addrstr;
+    } while(c != '.' && c != 0);
+  }
+  return 1;
+}
+
+/*-----------------------------------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uiplib.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uiplib.h
new file mode 100644
index 0000000..6eb0c66
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uiplib.h
@@ -0,0 +1,71 @@
+/**
+ * \file
+ * Various uIP library functions.
+ * \author
+ * Adam Dunkels 
+ *
+ */
+
+/*
+ * Copyright (c) 2002, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack
+ *
+ * $Id: uiplib.h,v 1.1 2006/06/07 09:15:19 adam Exp $
+ *
+ */
+#ifndef __UIPLIB_H__
+#define __UIPLIB_H__
+
+/**
+ * \addtogroup uipconvfunc
+ * @{
+ */
+
+/**
+ * Convert a textual representation of an IP address to a numerical representation.
+ *
+ * This function takes a textual representation of an IP address in
+ * the form a.b.c.d and converts it into a 4-byte array that can be
+ * used by other uIP functions.
+ *
+ * \param addrstr A pointer to a string containing the IP address in
+ * textual form.
+ *
+ * \param addr A pointer to a 4-byte array that will be filled in with
+ * the numerical representation of the address.
+ *
+ * \retval 0 If the IP address could not be parsed.
+ * \retval Non-zero If the IP address was parsed.
+ */
+unsigned char uiplib_ipaddrconv(char *addrstr, unsigned char *addr);
+
+/** @} */
+
+#endif /* __UIPLIB_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uipopt.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uipopt.h
new file mode 100644
index 0000000..f7c3e0f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/ethernet/uIP/uip-1.0/uip/uipopt.h
@@ -0,0 +1,539 @@
+/**
+ * \defgroup uipopt Configuration options for uIP
+ * @{
+ *
+ * uIP is configured using the per-project configuration file
+ * uipopt.h. This file contains all compile-time options for uIP and
+ * should be tweaked to match each specific project. The uIP
+ * distribution contains a documented example "uipopt.h" that can be
+ * copied and modified for each project.
+ *
+ * \note Most of the configuration options in the uipopt.h should not
+ * be changed, but rather the per-project uip-conf.h file.
+ */
+
+/**
+ * \file
+ * Configuration options for uIP.
+ * \author Adam Dunkels 
+ *
+ * This file is used for tweaking various configuration options for
+ * uIP. You should make a copy of this file into one of your project's
+ * directories instead of editing this example "uipopt.h" file that
+ * comes with the uIP distribution.
+ */
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uipopt.h,v 1.4 2006/06/12 08:00:31 adam Exp $
+ *
+ */
+
+#ifndef __UIPOPT_H__
+#define __UIPOPT_H__
+
+#ifndef UIP_LITTLE_ENDIAN
+#define UIP_LITTLE_ENDIAN  3412
+#endif /* UIP_LITTLE_ENDIAN */
+#ifndef UIP_BIG_ENDIAN
+#define UIP_BIG_ENDIAN     1234
+#endif /* UIP_BIG_ENDIAN */
+
+#include "uip-conf.h"
+
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \name Static configuration options
+ * @{
+ *
+ * These configuration options can be used for setting the IP address
+ * settings statically, but only if UIP_FIXEDADDR is set to 1. The
+ * configuration options for a specific node includes IP address,
+ * netmask and default router as well as the Ethernet address. The
+ * netmask, default router and Ethernet address are appliciable only
+ * if uIP should be run over Ethernet.
+ *
+ * All of these should be changed to suit your project.
+*/
+
+/**
+ * Determines if uIP should use a fixed IP address or not.
+ *
+ * If uIP should use a fixed IP address, the settings are set in the
+ * uipopt.h file. If not, the macros uip_sethostaddr(),
+ * uip_setdraddr() and uip_setnetmask() should be used instead.
+ *
+ * \hideinitializer
+ */
+#define UIP_FIXEDADDR    0
+
+/**
+ * Ping IP address asignment.
+ *
+ * uIP uses a "ping" packets for setting its own IP address if this
+ * option is set. If so, uIP will start with an empty IP address and
+ * the destination IP address of the first incoming "ping" (ICMP echo)
+ * packet will be used for setting the hosts IP address.
+ *
+ * \note This works only if UIP_FIXEDADDR is 0.
+ *
+ * \hideinitializer
+ */
+#ifdef UIP_CONF_PINGADDRCONF
+#define UIP_PINGADDRCONF UIP_CONF_PINGADDRCONF
+#else /* UIP_CONF_PINGADDRCONF */
+#define UIP_PINGADDRCONF 0
+#endif /* UIP_CONF_PINGADDRCONF */
+
+
+/**
+ * Specifies if the uIP ARP module should be compiled with a fixed
+ * Ethernet MAC address or not.
+ *
+ * If this configuration option is 0, the macro uip_setethaddr() can
+ * be used to specify the Ethernet address at run-time.
+ *
+ * \hideinitializer
+ */
+#define UIP_FIXEDETHADDR 0
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+/**
+ * \name IP configuration options
+ * @{
+ *
+ */
+/**
+ * The IP TTL (time to live) of IP packets sent by uIP.
+ *
+ * This should normally not be changed.
+ */
+#define UIP_TTL         64
+
+/**
+ * Turn on support for IP packet reassembly.
+ *
+ * uIP supports reassembly of fragmented IP packets. This features
+ * requires an additonal amount of RAM to hold the reassembly buffer
+ * and the reassembly code size is approximately 700 bytes.  The
+ * reassembly buffer is of the same size as the uip_buf buffer
+ * (configured by UIP_BUFSIZE).
+ *
+ * \note IP packet reassembly is not heavily tested.
+ *
+ * \hideinitializer
+ */
+#define UIP_REASSEMBLY 0
+
+/**
+ * The maximum time an IP fragment should wait in the reassembly
+ * buffer before it is dropped.
+ *
+ */
+#define UIP_REASS_MAXAGE 40
+
+/** @} */
+
+/*------------------------------------------------------------------------------*/
+/**
+ * \name UDP configuration options
+ * @{
+ */
+
+/**
+ * Toggles wether UDP support should be compiled in or not.
+ *
+ * \hideinitializer
+ */
+#ifdef UIP_CONF_UDP
+#define UIP_UDP UIP_CONF_UDP
+#else /* UIP_CONF_UDP */
+#define UIP_UDP           0
+#endif /* UIP_CONF_UDP */
+
+/**
+ * Toggles if UDP checksums should be used or not.
+ *
+ * \note Support for UDP checksums is currently not included in uIP,
+ * so this option has no function.
+ *
+ * \hideinitializer
+ */
+#ifdef UIP_CONF_UDP_CHECKSUMS
+#define UIP_UDP_CHECKSUMS UIP_CONF_UDP_CHECKSUMS
+#else
+#define UIP_UDP_CHECKSUMS 0
+#endif
+
+/**
+ * The maximum amount of concurrent UDP connections.
+ *
+ * \hideinitializer
+ */
+#ifdef UIP_CONF_UDP_CONNS
+#define UIP_UDP_CONNS UIP_CONF_UDP_CONNS
+#else /* UIP_CONF_UDP_CONNS */
+#define UIP_UDP_CONNS    10
+#endif /* UIP_CONF_UDP_CONNS */
+
+/**
+ * The name of the function that should be called when UDP datagrams arrive.
+ *
+ * \hideinitializer
+ */
+
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+/**
+ * \name TCP configuration options
+ * @{
+ */
+
+/**
+ * Determines if support for opening connections from uIP should be
+ * compiled in.
+ *
+ * If the applications that are running on top of uIP for this project
+ * do not need to open outgoing TCP connections, this configration
+ * option can be turned off to reduce the code size of uIP.
+ *
+ * \hideinitializer
+ */
+#define UIP_ACTIVE_OPEN 1
+
+/**
+ * The maximum number of simultaneously open TCP connections.
+ *
+ * Since the TCP connections are statically allocated, turning this
+ * configuration knob down results in less RAM used. Each TCP
+ * connection requires approximatly 30 bytes of memory.
+ *
+ * \hideinitializer
+ */
+#ifndef UIP_CONF_MAX_CONNECTIONS
+#define UIP_CONNS       10
+#else /* UIP_CONF_MAX_CONNECTIONS */
+#define UIP_CONNS UIP_CONF_MAX_CONNECTIONS
+#endif /* UIP_CONF_MAX_CONNECTIONS */
+
+
+/**
+ * The maximum number of simultaneously listening TCP ports.
+ *
+ * Each listening TCP port requires 2 bytes of memory.
+ *
+ * \hideinitializer
+ */
+#ifndef UIP_CONF_MAX_LISTENPORTS
+#define UIP_LISTENPORTS 20
+#else /* UIP_CONF_MAX_LISTENPORTS */
+#define UIP_LISTENPORTS UIP_CONF_MAX_LISTENPORTS
+#endif /* UIP_CONF_MAX_LISTENPORTS */
+
+/**
+ * Determines if support for TCP urgent data notification should be
+ * compiled in.
+ *
+ * Urgent data (out-of-band data) is a rarely used TCP feature that
+ * very seldom would be required.
+ *
+ * \hideinitializer
+ */
+#define UIP_URGDATA      0
+
+/**
+ * The initial retransmission timeout counted in timer pulses.
+ *
+ * This should not be changed.
+ */
+#define UIP_RTO         3
+
+/**
+ * The maximum number of times a segment should be retransmitted
+ * before the connection should be aborted.
+ *
+ * This should not be changed.
+ */
+#define UIP_MAXRTX      8
+
+/**
+ * The maximum number of times a SYN segment should be retransmitted
+ * before a connection request should be deemed to have been
+ * unsuccessful.
+ *
+ * This should not need to be changed.
+ */
+#define UIP_MAXSYNRTX      5
+
+/**
+ * The TCP maximum segment size.
+ *
+ * This is should not be to set to more than
+ * UIP_BUFSIZE - UIP_LLH_LEN - UIP_TCPIP_HLEN.
+ */
+#define UIP_TCP_MSS     (UIP_BUFSIZE - UIP_LLH_LEN - UIP_TCPIP_HLEN)
+
+/**
+ * The size of the advertised receiver's window.
+ *
+ * Should be set low (i.e., to the size of the uip_buf buffer) is the
+ * application is slow to process incoming data, or high (32768 bytes)
+ * if the application processes data quickly.
+ *
+ * \hideinitializer
+ */
+#ifndef UIP_CONF_RECEIVE_WINDOW
+#define UIP_RECEIVE_WINDOW UIP_TCP_MSS
+#else
+#define UIP_RECEIVE_WINDOW UIP_CONF_RECEIVE_WINDOW
+#endif
+
+/**
+ * How long a connection should stay in the TIME_WAIT state.
+ *
+ * This configiration option has no real implication, and it should be
+ * left untouched.
+ */
+#define UIP_TIME_WAIT_TIMEOUT 120
+
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+/**
+ * \name ARP configuration options
+ * @{
+ */
+
+/**
+ * The size of the ARP table.
+ *
+ * This option should be set to a larger value if this uIP node will
+ * have many connections from the local network.
+ *
+ * \hideinitializer
+ */
+#ifdef UIP_CONF_ARPTAB_SIZE
+#define UIP_ARPTAB_SIZE UIP_CONF_ARPTAB_SIZE
+#else
+#define UIP_ARPTAB_SIZE 8
+#endif
+
+/**
+ * The maxium age of ARP table entries measured in 10ths of seconds.
+ *
+ * An UIP_ARP_MAXAGE of 120 corresponds to 20 minutes (BSD
+ * default).
+ */
+#define UIP_ARP_MAXAGE 120
+
+/** @} */
+
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \name General configuration options
+ * @{
+ */
+
+/**
+ * The size of the uIP packet buffer.
+ *
+ * The uIP packet buffer should not be smaller than 60 bytes, and does
+ * not need to be larger than 1500 bytes. Lower size results in lower
+ * TCP throughput, larger size results in higher TCP throughput.
+ *
+ * \hideinitializer
+ */
+#ifndef UIP_CONF_BUFFER_SIZE
+#define UIP_BUFSIZE     1500
+#else /* UIP_CONF_BUFFER_SIZE */
+#define UIP_BUFSIZE UIP_CONF_BUFFER_SIZE
+#endif /* UIP_CONF_BUFFER_SIZE */
+
+
+/**
+ * Determines if statistics support should be compiled in.
+ *
+ * The statistics is useful for debugging and to show the user.
+ *
+ * \hideinitializer
+ */
+#ifndef UIP_CONF_STATISTICS
+#define UIP_STATISTICS  0
+#else /* UIP_CONF_STATISTICS */
+#define UIP_STATISTICS UIP_CONF_STATISTICS
+#endif /* UIP_CONF_STATISTICS */
+
+/**
+ * Determines if logging of certain events should be compiled in.
+ *
+ * This is useful mostly for debugging. The function uip_log()
+ * must be implemented to suit the architecture of the project, if
+ * logging is turned on.
+ *
+ * \hideinitializer
+ */
+#ifndef UIP_CONF_LOGGING
+#define UIP_LOGGING     0
+#else /* UIP_CONF_LOGGING */
+#define UIP_LOGGING     UIP_CONF_LOGGING
+#endif /* UIP_CONF_LOGGING */
+
+/**
+ * Broadcast support.
+ *
+ * This flag configures IP broadcast support. This is useful only
+ * together with UDP.
+ *
+ * \hideinitializer
+ *
+ */
+#ifndef UIP_CONF_BROADCAST
+#define UIP_BROADCAST 0
+#else /* UIP_CONF_BROADCAST */
+#define UIP_BROADCAST UIP_CONF_BROADCAST
+#endif /* UIP_CONF_BROADCAST */
+
+/**
+ * Print out a uIP log message.
+ *
+ * This function must be implemented by the module that uses uIP, and
+ * is called by uIP whenever a log message is generated.
+ */
+void uip_log(char *msg);
+
+/**
+ * The link level header length.
+ *
+ * This is the offset into the uip_buf where the IP header can be
+ * found. For Ethernet, this should be set to 14. For SLIP, this
+ * should be set to 0.
+ *
+ * \hideinitializer
+ */
+#ifdef UIP_CONF_LLH_LEN
+#define UIP_LLH_LEN UIP_CONF_LLH_LEN
+#else /* UIP_CONF_LLH_LEN */
+#define UIP_LLH_LEN     14
+#endif /* UIP_CONF_LLH_LEN */
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+/**
+ * \name CPU architecture configuration
+ * @{
+ *
+ * The CPU architecture configuration is where the endianess of the
+ * CPU on which uIP is to be run is specified. Most CPUs today are
+ * little endian, and the most notable exception are the Motorolas
+ * which are big endian. The BYTE_ORDER macro should be changed to
+ * reflect the CPU architecture on which uIP is to be run.
+ */
+
+/**
+ * The byte order of the CPU architecture on which uIP is to be run.
+ *
+ * This option can be either BIG_ENDIAN (Motorola byte order) or
+ * LITTLE_ENDIAN (Intel byte order).
+ *
+ * \hideinitializer
+ */
+#ifdef UIP_CONF_BYTE_ORDER
+#define UIP_BYTE_ORDER     UIP_CONF_BYTE_ORDER
+#else /* UIP_CONF_BYTE_ORDER */
+#define UIP_BYTE_ORDER     UIP_LITTLE_ENDIAN
+#endif /* UIP_CONF_BYTE_ORDER */
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \name Appication specific configurations
+ * @{
+ *
+ * An uIP application is implemented using a single application
+ * function that is called by uIP whenever a TCP/IP event occurs. The
+ * name of this function must be registered with uIP at compile time
+ * using the UIP_APPCALL definition.
+ *
+ * uIP applications can store the application state within the
+ * uip_conn structure by specifying the type of the application
+ * structure by typedef:ing the type uip_tcp_appstate_t and uip_udp_appstate_t.
+ *
+ * The file containing the definitions must be included in the
+ * uipopt.h file.
+ *
+ * The following example illustrates how this can look.
+ \code
+
+void httpd_appcall(void);
+#define UIP_APPCALL     httpd_appcall
+
+struct httpd_state {
+  u8_t state;
+  u16_t count;
+  char *dataptr;
+  char *script;
+};
+typedef struct httpd_state uip_tcp_appstate_t
+ \endcode
+ */
+
+/**
+ * \var #define UIP_APPCALL
+ *
+ * The name of the application function that uIP should call in
+ * response to TCP/IP events.
+ *
+ */
+
+/**
+ * \var typedef uip_tcp_appstate_t
+ *
+ * The type of the application state that is to be stored in the
+ * uip_conn structure. This usually is typedef:ed to a struct holding
+ * application state information.
+ */
+
+/**
+ * \var typedef uip_udp_appstate_t
+ *
+ * The type of the application state that is to be stored in the
+ * uip_conn structure. This usually is typedef:ed to a struct holding
+ * application state information.
+ */
+/** @} */
+/** @} */
+
+#endif /* __UIPOPT_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/AbortDelay.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/AbortDelay.h
new file mode 100644
index 0000000..30792a7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/AbortDelay.h
@@ -0,0 +1,36 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef ABORT_DELAY_H
+#define ABORT_DELAY_H
+
+void vCreateAbortDelayTasks( void );
+BaseType_t xAreAbortDelayTestTasksStillRunning( void );
+
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/BlockQ.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/BlockQ.h
new file mode 100644
index 0000000..18265ef
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/BlockQ.h
@@ -0,0 +1,36 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef BLOCK_Q_H
+#define BLOCK_Q_H
+
+void vStartBlockingQueueTasks( UBaseType_t uxPriority );
+BaseType_t xAreBlockingQueuesStillRunning( void );
+
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/EventGroupsDemo.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/EventGroupsDemo.h
new file mode 100644
index 0000000..4080e99
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/EventGroupsDemo.h
@@ -0,0 +1,44 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+
+/*
+ * This file contains fairly comprehensive checks on the behaviour of event
+ * groups.  It is not intended to be a user friendly demonstration of the event
+ * groups API.
+ */
+
+#ifndef EVENT_GROUPS_DEMO_H
+#define EVENT_GROUPS_DEMO_H
+
+void vStartEventGroupTasks( void );
+BaseType_t xAreEventGroupTasksStillRunning( void );
+void vPeriodicEventGroupsProcessing( void );
+
+#endif /* EVENT_GROUPS_DEMO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/GenQTest.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/GenQTest.h
new file mode 100644
index 0000000..9429707
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/GenQTest.h
@@ -0,0 +1,38 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef GEN_Q_TEST_H
+#define GEN_Q_TEST_H
+
+void vStartGenericQueueTasks( UBaseType_t uxPriority );
+BaseType_t xAreGenericQueueTasksStillRunning( void );
+void vMutexISRInteractionTest( void );
+
+#endif /* GEN_Q_TEST_H */
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/IntQueue.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/IntQueue.h
new file mode 100644
index 0000000..3b532a6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/IntQueue.h
@@ -0,0 +1,42 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef QUEUE_ACCESS_TEST
+#define QUEUE_ACCESS_TEST
+
+void vStartInterruptQueueTasks( void );
+BaseType_t xAreIntQueueTasksStillRunning( void );
+BaseType_t xFirstTimerHandler( void );
+BaseType_t xSecondTimerHandler( void );
+
+#endif /* QUEUE_ACCESS_TEST */
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/IntSemTest.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/IntSemTest.h
new file mode 100644
index 0000000..2005825
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/IntSemTest.h
@@ -0,0 +1,38 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef INT_SEM_TEST_H
+#define INT_SEM_TEST_H
+
+void vStartInterruptSemaphoreTasks( void );
+BaseType_t xAreInterruptSemaphoreTasksStillRunning( void );
+void vInterruptSemaphorePeriodicTest( void );
+
+#endif /* INT_SEM_TEST_H */
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/MessageBufferAMP.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/MessageBufferAMP.h
new file mode 100644
index 0000000..89a7c55
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/MessageBufferAMP.h
@@ -0,0 +1,35 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef MESSAGE_BUFFER_AMP_H
+#define MESSAGE_BUFFER_AMP_H
+
+void vStartMessageBufferAMPTasks( configSTACK_DEPTH_TYPE xStackSize );
+BaseType_t xAreMessageBufferAMPTasksStillRunning( void );
+void vGenerateCoreBInterrupt( void * xUpdatedMessageBuffer );
+
+#endif /* MESSAGE_BUFFER_AMP_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/MessageBufferDemo.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/MessageBufferDemo.h
new file mode 100644
index 0000000..b18ee55
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/MessageBufferDemo.h
@@ -0,0 +1,37 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef MESSAGE_BUFFER_TEST_H
+#define MESSAGE_BUFFER_TEST_H
+
+void vStartMessageBufferTasks( configSTACK_DEPTH_TYPE xStackSize  );
+BaseType_t xAreMessageBufferTasksStillRunning( void );
+
+#endif /* MESSAGE_BUFFER_TEST_H */
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/PollQ.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/PollQ.h
new file mode 100644
index 0000000..5d2e3fd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/PollQ.h
@@ -0,0 +1,36 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef POLLED_Q_H
+#define POLLED_Q_H
+
+void vStartPolledQueueTasks( UBaseType_t uxPriority );
+BaseType_t xArePollingQueuesStillRunning( void );
+
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/QPeek.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/QPeek.h
new file mode 100644
index 0000000..a628063
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/QPeek.h
@@ -0,0 +1,37 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef Q_PEEK_TEST_H
+#define Q_PEEK_TEST_H
+
+void vStartQueuePeekTasks( void );
+BaseType_t xAreQueuePeekTasksStillRunning( void );
+
+#endif /* Q_PEEK_TEST_H */
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/QueueOverwrite.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/QueueOverwrite.h
new file mode 100644
index 0000000..cbdd186
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/QueueOverwrite.h
@@ -0,0 +1,37 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef QUEUE_OVERWRITE_H
+#define QUEUE_OVERWRITE_H
+
+void vStartQueueOverwriteTask( UBaseType_t uxPriority );
+BaseType_t xIsQueueOverwriteTaskStillRunning( void );
+void vQueueOverwritePeriodicISRDemo( void );
+
+#endif /* QUEUE_OVERWRITE_H */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/QueueSet.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/QueueSet.h
new file mode 100644
index 0000000..4f1090c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/QueueSet.h
@@ -0,0 +1,37 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef QUEUE_WAIT_MULTIPLE_H
+#define QUEUE_WAIT_MULTIPLE_H
+
+void vStartQueueSetTasks( void );
+BaseType_t xAreQueueSetTasksStillRunning( void );
+void vQueueSetAccessQueueSetFromISR( void );
+
+#endif /* QUEUE_WAIT_MULTIPLE_H */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/QueueSetPolling.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/QueueSetPolling.h
new file mode 100644
index 0000000..775eb7b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/QueueSetPolling.h
@@ -0,0 +1,37 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef QUEUE_SET_POLLING_H
+#define QUEUE_SET_POLLING_H
+
+void vStartQueueSetPollingTask( void );
+BaseType_t xAreQueueSetPollTasksStillRunning( void );
+void vQueueSetPollingInterruptAccess( void );
+
+#endif /* QUEUE_SET_POLLING_H */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/StaticAllocation.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/StaticAllocation.h
new file mode 100644
index 0000000..130a13f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/StaticAllocation.h
@@ -0,0 +1,37 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef STATIC_ALLOCATION_H
+#define STATIC_ALLOCATION_H
+
+void vStartStaticallyAllocatedTasks( void  );
+BaseType_t xAreStaticAllocationTasksStillRunning( void );
+
+#endif /* STATIC_ALLOCATION_H */
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/StreamBufferDemo.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/StreamBufferDemo.h
new file mode 100644
index 0000000..9327872
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/StreamBufferDemo.h
@@ -0,0 +1,38 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef STREAM_BUFFER_TEST_H
+#define STREAM_BUFFER_TEST_H
+
+void vStartStreamBufferTasks( void );
+BaseType_t xAreStreamBufferTasksStillRunning( void );
+void vPeriodicStreamBufferProcessing( void );
+
+#endif /* STREAM_BUFFER_TEST_H */
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/StreamBufferInterrupt.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/StreamBufferInterrupt.h
new file mode 100644
index 0000000..24914fc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/StreamBufferInterrupt.h
@@ -0,0 +1,35 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef STREAM_BUFFER_INTERRUPT_H
+#define STREAM_BUFFER_INTERRUPT_H
+
+void vStartStreamBufferInterruptDemo( void );
+void vBasicStreamBufferSendFromISR( void );
+BaseType_t xIsInterruptStreamBufferDemoStillRunning( void );
+
+#endif /* STREAM_BUFFER_INTERRUPT_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/TaskNotify.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/TaskNotify.h
new file mode 100644
index 0000000..9ad8d5e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/TaskNotify.h
@@ -0,0 +1,38 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef TASK_NOTIFY_H
+#define TASK_NOTIFY_H
+
+void vStartTaskNotifyTask( void  );
+BaseType_t xAreTaskNotificationTasksStillRunning( void );
+void xNotifyTaskFromISR( void );
+
+#endif /* TASK_NOTIFY_H */
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/TimerDemo.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/TimerDemo.h
new file mode 100644
index 0000000..f3101e7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/TimerDemo.h
@@ -0,0 +1,38 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef TIMER_DEMO_H
+#define TIMER_DEMO_H
+
+void vStartTimerDemoTask( TickType_t xBaseFrequencyIn );
+BaseType_t xAreTimerDemoTasksStillRunning( TickType_t xCycleFrequency );
+void vTimerPeriodicISRTests( void );
+
+#endif /* TIMER_DEMO_H */
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/blocktim.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/blocktim.h
new file mode 100644
index 0000000..76223b7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/blocktim.h
@@ -0,0 +1,36 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef BLOCK_TIME_TEST_H
+#define BLOCK_TIME_TEST_H
+
+void vCreateBlockTimeTasks( void );
+BaseType_t xAreBlockTimeTestTasksStillRunning( void );
+
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/comtest.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/comtest.h
new file mode 100644
index 0000000..0607f2b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/comtest.h
@@ -0,0 +1,37 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef COMTEST_H
+#define COMTEST_H
+
+void vAltStartComTestTasks( UBaseType_t uxPriority, uint32_t ulBaudRate, UBaseType_t uxLED );
+void vStartComTestTasks( UBaseType_t uxPriority, eCOMPort ePort, eBaud eBaudRate );
+BaseType_t xAreComTestTasksStillRunning( void );
+void vComTestUnsuspendTask( void );
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/comtest2.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/comtest2.h
new file mode 100644
index 0000000..3972361
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/comtest2.h
@@ -0,0 +1,35 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef COMTEST_H
+#define COMTEST_H
+
+void vAltStartComTestTasks( UBaseType_t uxPriority, uint32_t ulBaudRate, UBaseType_t uxLED );
+BaseType_t xAreComTestTasksStillRunning( void );
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/comtest_strings.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/comtest_strings.h
new file mode 100644
index 0000000..f9291b6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/comtest_strings.h
@@ -0,0 +1,35 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef COMTEST_STRINGS_H
+#define COMTEST_STRINGS_H
+
+void vStartComTestStringsTasks( UBaseType_t uxPriority, uint32_t ulBaudRate, UBaseType_t uxLED );
+BaseType_t xAreComTestTasksStillRunning( void );
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/countsem.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/countsem.h
new file mode 100644
index 0000000..644faae
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/countsem.h
@@ -0,0 +1,35 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef COUNT_SEMAPHORE_TEST_H
+#define COUNT_SEMAPHORE_TEST_H
+
+void vStartCountingSemaphoreTasks( void );
+BaseType_t xAreCountingSemaphoreTasksStillRunning( void );
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/crflash.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/crflash.h
new file mode 100644
index 0000000..f4b8988
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/crflash.h
@@ -0,0 +1,47 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef CRFLASH_LED_H
+#define CRFLASH_LED_H
+
+/*
+ * Create the co-routines used to flash the LED's at different rates.
+ *
+ * @param uxPriority The number of 'fixed delay' co-routines to create.  This
+ *		  also effects the number of LED's that will be utilised.  For example,
+ *		  passing in 3 will cause LED's 0 to 2 to be utilised.
+ */
+void vStartFlashCoRoutines( UBaseType_t uxPriority );
+
+/*
+ * Return pdPASS or pdFAIL depending on whether an error has been detected
+ * or not.
+ */
+BaseType_t xAreFlashCoRoutinesStillRunning( void );
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/crhook.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/crhook.h
new file mode 100644
index 0000000..85209fc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/crhook.h
@@ -0,0 +1,43 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef CRHOOK_H
+#define CRHOOK_H
+
+/*
+ * Create the co-routines used to communicate wit the tick hook.
+ */
+void vStartHookCoRoutines( void );
+
+/*
+ * Return pdPASS or pdFAIL depending on whether an error has been detected
+ * or not.
+ */
+BaseType_t xAreHookCoRoutinesStillRunning( void );
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/death.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/death.h
new file mode 100644
index 0000000..c6213c6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/death.h
@@ -0,0 +1,36 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef SUICIDE_TASK_H
+#define SUICIDE_TASK_H
+
+void vCreateSuicidalTasks( UBaseType_t uxPriority );
+BaseType_t xIsCreateTaskStillRunning( void );
+
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/dynamic.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/dynamic.h
new file mode 100644
index 0000000..b90ce40
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/dynamic.h
@@ -0,0 +1,36 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef DYNAMIC_MANIPULATION_H
+#define DYNAMIC_MANIPULATION_H
+
+void vStartDynamicPriorityTasks( void );
+BaseType_t xAreDynamicPriorityTasksStillRunning( void );
+
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/fileIO.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/fileIO.h
new file mode 100644
index 0000000..747a564
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/fileIO.h
@@ -0,0 +1,36 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef FILE_IO_H
+#define FILE_IO_H
+
+void vDisplayMessage( const char * const pcMessageToPrint );
+void vWriteMessageToDisk( const char * const pcMessage );
+void vWriteBufferToDisk( const char * const pcBuffer, uint32_t ulBufferLength );
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/flash.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/flash.h
new file mode 100644
index 0000000..88a1efe
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/flash.h
@@ -0,0 +1,34 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef FLASH_LED_H
+#define FLASH_LED_H
+
+void vStartLEDFlashTasks( UBaseType_t uxPriority );
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/flash_timer.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/flash_timer.h
new file mode 100644
index 0000000..a61e5a5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/flash_timer.h
@@ -0,0 +1,41 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef FLASH_TIMER_H
+#define FLASH_TIMER_H
+
+/*
+ * Creates the LED flashing timers.  xNumberOfLEDs specifies how many timers to
+ * create, with each timer toggling a different LED.  The first LED to be 
+ * toggled is LED 0, with subsequent LEDs following on in numerical order.  Each
+ * timer uses the exact same callback function, with the timer ID being used
+ * within the callback function to determine which timer has actually expired
+ * (and therefore which LED to toggle).
+ */
+void vStartLEDFlashTimers( UBaseType_t uxNumberOfLEDs );
+
+#endif /* FLASH_TIMER_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/flop.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/flop.h
new file mode 100644
index 0000000..7e7f436
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/flop.h
@@ -0,0 +1,36 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef FLOP_TASKS_H
+#define FLOP_TASKS_H
+
+void vStartMathTasks( UBaseType_t uxPriority );
+BaseType_t xAreMathsTaskStillRunning( void );
+
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/integer.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/integer.h
new file mode 100644
index 0000000..c1c5362
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/integer.h
@@ -0,0 +1,36 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef INTEGER_TASKS_H
+#define INTEGER_TASKS_H
+
+void vStartIntegerMathTasks( UBaseType_t uxPriority );
+BaseType_t xAreIntegerMathsTaskStillRunning( void );
+
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/mevents.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/mevents.h
new file mode 100644
index 0000000..4d5f852
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/mevents.h
@@ -0,0 +1,36 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef EVENTS_TEST_H
+#define EVENTS_TEST_H
+
+void vStartMultiEventTasks( void );
+BaseType_t xAreMultiEventTasksStillRunning( void );
+
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/partest.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/partest.h
new file mode 100644
index 0000000..cbe3e67
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/partest.h
@@ -0,0 +1,38 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PARTEST_H
+#define PARTEST_H
+
+#define partstDEFAULT_PORT_ADDRESS		( ( uint16_t ) 0x378 )
+
+void vParTestInitialise( void );
+void vParTestSetLED( UBaseType_t uxLED, BaseType_t xValue );
+void vParTestToggleLED( UBaseType_t uxLED );
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/print.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/print.h
new file mode 100644
index 0000000..29088b9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/print.h
@@ -0,0 +1,37 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PRINT_H
+#define PRINT_H
+
+void vPrintInitialise( void );
+void vPrintDisplayMessage( const char * const * pcMessageToSend );
+const char *pcPrintGetNextMessage( TickType_t xPrintRate );
+
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/recmutex.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/recmutex.h
new file mode 100644
index 0000000..679c379
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/recmutex.h
@@ -0,0 +1,35 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef RECURSIVE_MUTEX_TEST_H
+#define RECURSIVE_MUTEX_TEST_H
+
+void vStartRecursiveMutexTasks( void );
+BaseType_t xAreRecursiveMutexTasksStillRunning( void );
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/semtest.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/semtest.h
new file mode 100644
index 0000000..b7a5bb0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/semtest.h
@@ -0,0 +1,35 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef SEMAPHORE_TEST_H
+#define SEMAPHORE_TEST_H
+
+void vStartSemaphoreTasks( UBaseType_t uxPriority );
+BaseType_t xAreSemaphoreTasksStillRunning( void );
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/serial.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/serial.h
new file mode 100644
index 0000000..9c4fbcd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/Common/include/serial.h
@@ -0,0 +1,98 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef SERIAL_COMMS_H
+#define SERIAL_COMMS_H
+
+typedef void * xComPortHandle;
+
+typedef enum
+{ 
+	serCOM1, 
+	serCOM2, 
+	serCOM3, 
+	serCOM4, 
+	serCOM5, 
+	serCOM6, 
+	serCOM7, 
+	serCOM8 
+} eCOMPort;
+
+typedef enum 
+{ 
+	serNO_PARITY, 
+	serODD_PARITY, 
+	serEVEN_PARITY, 
+	serMARK_PARITY, 
+	serSPACE_PARITY 
+} eParity;
+
+typedef enum 
+{ 
+	serSTOP_1, 
+	serSTOP_2 
+} eStopBits;
+
+typedef enum 
+{ 
+	serBITS_5, 
+	serBITS_6, 
+	serBITS_7, 
+	serBITS_8 
+} eDataBits;
+
+typedef enum 
+{ 
+	ser50,		
+	ser75,		
+	ser110,		
+	ser134,		
+	ser150,    
+	ser200,
+	ser300,		
+	ser600,		
+	ser1200,	
+	ser1800,	
+	ser2400,   
+	ser4800,
+	ser9600,		
+	ser19200,	
+	ser38400,	
+	ser57600,	
+	ser115200
+} eBaud;
+
+xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength );
+xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength );
+void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength );
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime );
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime );
+portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort );
+void vSerialClose( xComPortHandle xPort );
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/.cproject b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/.cproject
new file mode 100644
index 0000000..2f9dbd5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/.cproject
@@ -0,0 +1,227 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+					
+						
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+	
+	
+		
+			
+		
+		
+			
+		
+	
+	
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/.project b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/.project
new file mode 100644
index 0000000..2db3617
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/.project
@@ -0,0 +1,155 @@
+
+
+	RTOSDemo
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		org.eclipse.cdt.core.cnature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			FreeRTOS_Source
+			2
+			virtual:/virtual
+		
+		
+			FreeRTOS_Source/event_groups.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Source/event_groups.c
+		
+		
+			FreeRTOS_Source/include
+			2
+			FREERTOS_ROOT/FreeRTOS/Source/include
+		
+		
+			FreeRTOS_Source/list.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Source/list.c
+		
+		
+			FreeRTOS_Source/portable
+			2
+			virtual:/virtual
+		
+		
+			FreeRTOS_Source/queue.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Source/queue.c
+		
+		
+			FreeRTOS_Source/stream_buffer.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Source/stream_buffer.c
+		
+		
+			FreeRTOS_Source/tasks.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Source/tasks.c
+		
+		
+			FreeRTOS_Source/timers.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Source/timers.c
+		
+		
+			full_demo/common_demo_tasks
+			2
+			virtual:/virtual
+		
+		
+			FreeRTOS_Source/portable/GCC
+			2
+			virtual:/virtual
+		
+		
+			FreeRTOS_Source/portable/MemMang
+			2
+			virtual:/virtual
+		
+		
+			full_demo/common_demo_tasks/EventGroupsDemo.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/EventGroupsDemo.c
+		
+		
+			full_demo/common_demo_tasks/GenQTest.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/GenQTest.c
+		
+		
+			full_demo/common_demo_tasks/TaskNotify.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/TaskNotify.c
+		
+		
+			full_demo/common_demo_tasks/TimerDemo.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/TimerDemo.c
+		
+		
+			full_demo/common_demo_tasks/blocktim.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/blocktim.c
+		
+		
+			full_demo/common_demo_tasks/dynamic.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/dynamic.c
+		
+		
+			full_demo/common_demo_tasks/include
+			2
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/include
+		
+		
+			full_demo/common_demo_tasks/recmutex.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/recmutex.c
+		
+		
+			FreeRTOS_Source/portable/GCC/RISC-V
+			2
+			FREERTOS_ROOT/FreeRTOS/Source/portable/GCC/RISC-V
+		
+		
+			FreeRTOS_Source/portable/MemMang/heap_4.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Source/portable/MemMang/heap_4.c
+		
+	
+	
+		
+			1546280186727
+			FreeRTOS_Source/portable/GCC/RISC-V/chip_specific_extensions
+			9
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-RV32I_CLINT_no_extensions
+			
+		
+	
+	
+		
+			FREERTOS_ROOT
+			$%7BPARENT-3-PROJECT_LOC%7D
+		
+	
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/.settings/language.settings.xml b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/.settings/language.settings.xml
new file mode 100644
index 0000000..3fd0e8c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+
+
+	
+		
+			
+			
+			
+			
+				
+				
+			
+		
+	
+	
+		
+			
+			
+			
+			
+				
+				
+			
+		
+	
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/BuildEnvironment.mk b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/BuildEnvironment.mk
new file mode 100644
index 0000000..9d92d9f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/BuildEnvironment.mk
@@ -0,0 +1,53 @@
+#
+# File: BuildEnvironment.mk
+# Copyright (c) 2019, Dornerworks Ltd.
+#
+
+BUILD_DIR = ./build
+CROSS_COMPILE_PREFIX = riscv32-unknown-elf
+
+SDK_DIR = ./freedom-e-sdk
+
+LINKER_SCRIPT = $(SDK_DIR)/env/freedom-e300-hifive1/flash.lds
+#-----------------------------------------------------------
+GCC     = $(CROSS_COMPILE_PREFIX)-gcc
+OBJCOPY = $(CROSS_COMPILE_PREFIX)-objcopy
+OBJDUMP = $(CROSS_COMPILE_PREFIX)-objdump
+AR      = $(CROSS_COMPILE_PREFIX)-ar
+RANLIB  = $(CROSS_COMPILE_PREFIX)-ranlib
+GDB     = $(CROSS_COMPILE_PREFIX)-gdb
+
+# if using the multi-arch (riscv64-unknown-elf-gcc):
+ARCH_FLAGS = -march=rv32imac -mabi=ilp32 -mcmodel=medany
+# Basic CFLAGS:
+CFLAGS  = -Wall -Wextra -O0 -g3 -msmall-data-limit=8 -std=gnu11
+CFLAGS += -ffunction-sections -fdata-sections -fno-builtin-printf
+CFLAGS += -DDONT_USE_PLIC -DDONT_USE_M_TIME
+CFLAGS += -include sys/cdefs.h
+CFLAGS += $(ARCH_FLAGS)
+# These flags are for outputing *.d dependency files for make
+CFLAGS += -MT"$@" -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)"
+
+ASMFLAGS =  -O0 -g3
+ASMFLAGS += $(ARCH_FLAGS)
+ASMFLAGS += -DportasmHANDLE_INTERRUPT=handle_trap
+ASMFLAGS += -msmall-data-limit=8
+ASMFLAGS += -ffunction-sections -fdata-sections
+ASMFLAGS += -x assembler-with-cpp
+ASMFLAGS += -MT"$@" -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)"
+
+# Linker arguments __________________________________________
+LDFLAGS :=  -Xlinker --gc-sections -Xlinker --defsym=__stack_size=1K
+LDFLAGS += -O0 -g3
+LDFLAGS += -ffunction-sections -fdata-sections --specs=nano.specs
+LDFLAGS += -nostartfiles
+LDFLAGS += -T $(LINKER_SCRIPT)
+LDFLAGS += -L../
+LDFLAGS += -Wl,--start-group -Wl,--end-group
+LDFLAGS += -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=open -Wl,--wrap=lseek -Wl,--wrap=read -Wl,--wrap=write
+LDFLAGS += -Wl,--wrap=fstat -Wl,--wrap=stat -Wl,--wrap=close -Wl,--wrap=link -Wl,--wrap=unlink -Wl,--wrap=execve
+LDFLAGS += -Wl,--wrap=fork -Wl,--wrap=getpid -Wl,--wrap=kill -Wl,--wrap=wait -Wl,--wrap=isatty -Wl,--wrap=times
+LDFLAGS += -Wl,--wrap=sbrk -Wl,--wrap=_exit -Wl,--wrap=puts -Wl,--wrap=_malloc -Wl,--wrap=_free -Wl,--wrap=_open
+LDFLAGS += -Wl,--wrap=_lseek -Wl,--wrap=_read -Wl,--wrap=_write -Wl,--wrap=_fstat -Wl,--wrap=_stat -Wl,--wrap=_close
+LDFLAGS += -Wl,--wrap=_link -Wl,--wrap=_unlink -Wl,--wrap=_execve -Wl,--wrap=_fork -Wl,--wrap=_getpid -Wl,--wrap=_kill
+LDFLAGS += -Wl,--wrap=_wait -Wl,--wrap=_isatty -Wl,--wrap=_times -Wl,--wrap=_sbrk -Wl,--wrap=__exit -Wl,--wrap=_puts
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/Demo Documentation.url b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/Demo Documentation.url
new file mode 100644
index 0000000..e2478fb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/Demo Documentation.url	
@@ -0,0 +1,5 @@
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,11
+[InternetShortcut]
+IDList=
+URL=https://freertos.org/RTOS-RISC-V-FreedomStudio-QMEU.html
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/FreeRTOS.mk b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/FreeRTOS.mk
new file mode 100644
index 0000000..4a87a2a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/FreeRTOS.mk
@@ -0,0 +1,32 @@
+#
+# File: FreeRTOS.mk
+# Copyright (c) 2019, Dornerworks Ltd.
+#
+
+-include BuildEnvironment.mk
+
+FREERTOS_DIR = ../..
+FREERTOS_SOURCE_DIR = $(FREERTOS_DIR)/Source
+
+FREERTOS_SRC = \
+	$(FREERTOS_SOURCE_DIR)/croutine.c \
+	$(FREERTOS_SOURCE_DIR)/list.c \
+	$(FREERTOS_SOURCE_DIR)/queue.c \
+	$(FREERTOS_SOURCE_DIR)/tasks.c \
+	$(FREERTOS_SOURCE_DIR)/timers.c \
+	$(FREERTOS_SOURCE_DIR)/event_groups.c \
+	$(FREERTOS_SOURCE_DIR)/stream_buffer.c \
+	$(FREERTOS_SOURCE_DIR)/portable/MemMang/heap_4.c
+
+FREERTOS_INC = $(FREERTOS_SOURCE_DIR)/include
+
+FREERTOS_INCLUDES := \
+	-I $(FREERTOS_INC)
+
+INTERRUPT_HANDLER = main_blinky
+
+FREERTOS_BUILD_DIR = $(BUILD_DIR)/FreeRTOS
+FREERTOS_OBJS = $(patsubst %.c,$(FREERTOS_BUILD_DIR)/%.o,$(notdir $(FREERTOS_SRC)))
+VPATH += \
+	$(FREERTOS_SOURCE_DIR) \
+	$(FREERTOS_SOURCE_DIR)/portable/MemMang
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/FreeRTOSConfig.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/FreeRTOSConfig.h
new file mode 100644
index 0000000..f239c1c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+    FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include "platform.h"
+
+/*
+ * For some reason the standard demo timer demo/test tasks fail when executing
+ * in QEMU, although they pass on other RISC-V platforms.  This requires
+ * further investigation, but for now, defining _WINDOWS_ has the effect of
+ * using the wider timer test thresholds that are normally only used when the
+ * tests are used with the FreeRTOS Windows port (which is not deterministic
+ * and therefore requires wider margins).
+ */
+#define _WINDOWS_
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configCLINT_BASE_ADDRESS		CLINT_CTRL_ADDR
+#define configUSE_PREEMPTION			1
+#define configUSE_IDLE_HOOK				0
+#define configUSE_TICK_HOOK				1
+#define configCPU_CLOCK_HZ				( 10000000 ) /*QEMU*/
+#define configTICK_RATE_HZ				( ( TickType_t ) 1000 )
+#define configMAX_PRIORITIES			( 7 )
+#define configMINIMAL_STACK_SIZE		( ( unsigned short ) 70 )
+#define configTOTAL_HEAP_SIZE			( ( size_t ) 14100 )
+#define configMAX_TASK_NAME_LEN			( 16 )
+#define configUSE_TRACE_FACILITY		0
+#define configUSE_16_BIT_TICKS			0
+#define configIDLE_SHOULD_YIELD			0
+#define configUSE_MUTEXES				1
+#define configQUEUE_REGISTRY_SIZE		8
+#define configCHECK_FOR_STACK_OVERFLOW	2
+#define configUSE_RECURSIVE_MUTEXES		1
+#define configUSE_MALLOC_FAILED_HOOK	1
+#define configUSE_APPLICATION_TASK_TAG	0
+#define configUSE_COUNTING_SEMAPHORES	1
+#define configGENERATE_RUN_TIME_STATS	0
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 			0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Software timer definitions. */
+#define configUSE_TIMERS				1
+#define configTIMER_TASK_PRIORITY		( configMAX_PRIORITIES - 1 )
+#define configTIMER_QUEUE_LENGTH		4
+#define configTIMER_TASK_STACK_DEPTH	( 100 )
+
+/* Task priorities.  Allow these to be overridden. */
+#ifndef uartPRIMARY_PRIORITY
+	#define uartPRIMARY_PRIORITY		( configMAX_PRIORITIES - 3 )
+#endif
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet		1
+#define INCLUDE_uxTaskPriorityGet		1
+#define INCLUDE_vTaskDelete				1
+#define INCLUDE_vTaskCleanUpResources	1
+#define INCLUDE_vTaskSuspend			1
+#define INCLUDE_vTaskDelayUntil			1
+#define INCLUDE_vTaskDelay				1
+#define INCLUDE_eTaskGetState			1
+#define INCLUDE_xTimerPendFunctionCall	1
+
+/* Normal assert() semantics without relying on the provision of an assert.h
+header file. */
+void vAssertCalled( void );
+#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled()
+
+/* Overwrite some of the stack sizes allocated to various test and demo tasks.
+Like all task stack sizes, the value is the number of words, not bytes. */
+#define bktBLOCK_TIME_TASK_STACK_SIZE 100
+#define notifyNOTIFIED_TASK_STACK_SIZE 120
+#define priSUSPENDED_RX_TASK_STACK_SIZE 90
+#define tmrTIMER_TEST_TASK_STACK_SIZE 100
+#define ebRENDESVOUS_TEST_TASK_STACK_SIZE 100
+#define ebEVENT_GROUP_SET_BITS_TEST_TASK_STACK_SIZE 115
+#define genqMUTEX_TEST_TASK_STACK_SIZE 90
+#define genqGENERIC_QUEUE_TEST_TASK_STACK_SIZE 100
+#define recmuRECURSIVE_MUTEX_TEST_TASK_STACK_SIZE 90
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/Hardware_Qemu.launch b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/Hardware_Qemu.launch
new file mode 100644
index 0000000..ad57bf5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/Hardware_Qemu.launch
@@ -0,0 +1,44 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/Makefile b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/Makefile
new file mode 100644
index 0000000..0e07695
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/Makefile
@@ -0,0 +1,197 @@
+#
+# File: Makefile
+# Copyright (c) 2019, Dornerworks Ltd.
+#
+
+PROJ_NAME ?= simple
+
+include BuildEnvironment.mk
+include FreeRTOS.mk
+-include $(wildcard $(OUTDIR)/*.d)
+# Platform spcific settings for this application _____________________________________________
+
+ARCH = RISC-V
+ARCH_PORTABLE_INC = $(FREERTOS_SOURCE_DIR)/portable/GCC/$(ARCH)/
+ARCH_PORTABLE_SRC = $(FREERTOS_SOURCE_DIR)/portable/GCC/$(ARCH)/port.c
+ARCH_PORTABLE_ASM = $(FREERTOS_SOURCE_DIR)/portable/GCC/$(ARCH)/portASM.S
+
+SDK_SRC := \
+	$(SDK_DIR)/libwrap/sys/_exit.c \
+	$(SDK_DIR)/libwrap/sys/close.c \
+	$(SDK_DIR)/libwrap/sys/execve.c \
+	$(SDK_DIR)/libwrap/sys/fork.c \
+	$(SDK_DIR)/libwrap/sys/fstat.c \
+	$(SDK_DIR)/libwrap/sys/getpid.c \
+	$(SDK_DIR)/libwrap/sys/isatty.c \
+	$(SDK_DIR)/libwrap/sys/kill.c \
+	$(SDK_DIR)/libwrap/sys/link.c \
+	$(SDK_DIR)/libwrap/sys/lseek.c \
+	$(SDK_DIR)/libwrap/sys/openat.c \
+	$(SDK_DIR)/libwrap/sys/puts.c \
+	$(SDK_DIR)/libwrap/sys/read.c \
+	$(SDK_DIR)/libwrap/sys/sbrk.c \
+	$(SDK_DIR)/libwrap/sys/stat.c \
+	$(SDK_DIR)/libwrap/sys/times.c \
+	$(SDK_DIR)/libwrap/sys/unlink.c \
+	$(SDK_DIR)/libwrap/sys/wait.c \
+	$(SDK_DIR)/libwrap/sys/write.c \
+	$(SDK_DIR)/libwrap/stdlib/malloc.c \
+	$(SDK_DIR)/libwrap/misc/write_hex.c \
+	$(SDK_DIR)/env/freedom-e300-hifive1/init.c \
+	$(SDK_DIR)/drivers/plic/plic_driver.c \
+	$(SDK_DIR)/drivers/fe300prci/fe300prci_driver.c
+
+SDK_ASM := \
+	$(SDK_DIR)/env/entry.S \
+	$(SDK_DIR)/env/start.S
+SDK_OBJS := $(patsubst %.c,$(FREERTOS_BUILD_DIR)/%.o,$(notdir $(SDK_SRC)))
+SDK_OBJS += $(patsubst %.S,$(FREERTOS_BUILD_DIR)/%.o,$(notdir $(SDK_ASM)))
+VPATH += \
+	$(SDK_DIR)/env \
+	$(SDK_DIR)/env/freedom-e300-hifive1 \
+	$(SDK_DIR)/libwrap/sys \
+	$(SDK_DIR)/libwrap/misc \
+	$(SDK_DIR)/libwrap/stdlib \
+	$(SDK_DIR)/drivers/plic \
+	$(SDK_DIR)/drivers/fe300prci
+
+PORT_OBJS := $(patsubst %.c,$(FREERTOS_BUILD_DIR)/%.o,$(notdir $(ARCH_PORTABLE_SRC)))
+PORT_OBJS += $(patsubst %.S,$(FREERTOS_BUILD_DIR)/%.o,$(notdir $(ARCH_PORTABLE_ASM)))
+FREERTOS_OBJS += $(PORT_OBJS) $(SDK_OBJS)
+VPATH += $(FREERTOS_SOURCE_DIR)/portable/GCC/$(ARCH)
+
+
+CFLAGS += -DportasmHANDLE_INTERRUPT=$(INTERRUPT_HANDLER)
+
+# Set up application source, include, and object files for compilation: ______________________
+APP_SRC_DIR = .
+APP_SRC = \
+	$(APP_SRC_DIR)/main.c \
+	$(APP_SRC_DIR)/blinky_demo/main_blinky.c \
+	$(APP_SRC_DIR)/full_demo/main_full.c
+
+APP_ASM = \
+	$(APP_SRC_DIR)/full_demo/RegTest.S
+
+APP_INCLUDES = \
+	-I ./ \
+	-I $(SDK_DIR)/include \
+	-I $(SDK_DIR)/env/freedom-e300-hifive1 \
+	-I $(SDK_DIR)/env \
+	-I $(FREERTOS_INC) \
+	-I $(ARCH_PORTABLE_INC) \
+	-I $(FREERTOS_DIR)/Demo/Common/include
+
+APP_BUILD_DIR = $(BUILD_DIR)/app
+APP_OBJS := $(patsubst %.c,$(APP_BUILD_DIR)/%.o,$(notdir $(APP_SRC)))
+APP_OBJS += $(patsubst %.S,$(APP_BUILD_DIR)/%.o,$(notdir $(APP_ASM)))
+VPATH += \
+	$(APP_SRC_DIR)/blinky_demo \
+	$(APP_SRC_DIR)/full_demo \
+	$(APP_SRC_DIR)
+
+DEMO_COMMON_SRC =  \
+	$(FREERTOS_DIR)/Demo/Common/Minimal/EventGroupsDemo.c \
+	$(FREERTOS_DIR)/Demo/Common/Minimal/TimerDemo.c \
+	$(FREERTOS_DIR)/Demo/Common/Minimal/TaskNotify.c \
+	$(FREERTOS_DIR)/Demo/Common/Minimal/GenQTest.c \
+	$(FREERTOS_DIR)/Demo/Common/Minimal/blocktim.c \
+	$(FREERTOS_DIR)/Demo/Common/Minimal/dynamic.c \
+	$(FREERTOS_DIR)/Demo/Common/Minimal/recmutex.c
+
+DEMO_COMMON_OBJS := $(patsubst %.c,$(APP_BUILD_DIR)/%.o,$(notdir $(DEMO_COMMON_SRC)))
+VPATH += $(FREERTOS_DIR)/Demo/Common/Minimal
+
+OUT_ELF = $(BUILD_DIR)/FreeRTOS-$(PROJ_NAME).elf
+
+# Need to tell FreeRTOS where to find the FreeRTOSConfig.h __________________________________
+FREERTOS_INCLUDES += \
+	-I ./ \
+	-I $(ARCH_PORTABLE_INC) \
+	-I $(SDK_DIR)/include \
+	-I $(SDK_DIR)/env/freedom-e300-hifive1 \
+	-I $(SDK_DIR)/env \
+	-I $(SDK_DIR)/drivers \
+	-I $(FREERTOS_DIR)/Demo/Common/include \
+	-I $(FREERTOS_SOURCE_DIR)/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions
+
+# List of object files to compile for the system:
+OUT_OBJS = \
+	$(APP_OBJS) \
+	$(DEMO_COMMON_OBJS) \
+	$(FREERTOS_OBJS)
+
+BUILD_DIRECTORIES = \
+	$(APP_BUILD_DIR) \
+	$(FREERTOS_BUILD_DIR)
+
+LDFLAGS += -Wl,-Map,"$(BUILD_DIR)/$(PROJ_NAME).map"
+
+.PHONY: debug clean app_compile debug-app frtos_compile print-info out_elf sim-qemu gdb
+all: directories $(OUT_OBJS) $(OUT_ELF)
+directories: $(BUILD_DIRECTORIES)
+app_compile: directories $(APP_OBJS)
+frtos_compile: directories $(FREERTOS_OBJS)
+out_elf: directories $(OUT_ELF)
+
+# Notes
+# Each "Module" needs
+#  - Lists of source files
+#  - Source Directory(ies)
+#  - Include Directory List (with -I prepending each entry)
+#  - Build Directory
+#  - Object list
+#    - OBJS = $(patsubst %.c,$(MODULE_BUILD_DIR)/%.o,$(notdir $(MODULE_SRC)))
+#  - Add source direcories to VPATH
+# In the master make file
+#  - Module build directory must be created
+#  - Object Rules can be done with
+#    - $(MODULE_BUILD_DIR)/%.o : %.c
+
+# Compile Object Files ____________________________________________________________________
+$(APP_BUILD_DIR)/%.o : %.c
+	@echo "[APP Objects] : $@ ______________________________________________________________"
+	@echo "Building: $<"
+	$(GCC) $(CFLAGS) $(APP_INCLUDES) -o $@ -c $<
+	@echo "Finished Building: $<"
+
+$(APP_BUILD_DIR)/%.o : %.S
+	@echo "[APP Objects] : $@ ______________________________________________________________"
+	@echo "Building: $<"
+	$(GCC) $(ASMFLAGS) $(APP_INCLUDES) $(FREERTOS_INCLUDES) -o $@ -c $<
+	@echo "Finished Building: $<"
+
+$(FREERTOS_BUILD_DIR)/%.o : %.c
+	@echo "[FreeRTOS Objects] : $@ __________________________________________________________"
+	@echo "Building: $<"
+	$(GCC) $(CFLAGS) $(FREERTOS_INCLUDES) -o $@ -c $<
+	@echo "Finished Building: $<"
+
+$(FREERTOS_BUILD_DIR)/%.o : %.S
+	@echo "[FreeRTOS Objects] : $@ __________________________________________________________"
+	@echo "Building: $<"
+	$(GCC) $(ASMFLAGS) $(FREERTOS_INCLUDES) -o $@ -c $<
+	@echo "Finished Building: $<"
+
+# Generate ELF ___________________________________________________________________________
+$(OUT_ELF): $(OUT_OBJS)
+	@echo '___________________________________________________________________________________'
+	@echo 'Building target: $@'
+	@echo '_______________________________'
+	$(GCC) $(LDFLAGS) $(LDOPTS) -o $@ $(OUT_OBJS) $(LIB_FLAGS)
+	@echo 'Finished building target: $@'
+	@echo ' '
+
+.PHONY:  build_lib
+
+$(BUILD_DIRECTORIES):
+	mkdir -p $@
+
+clean:
+	rm -rv $(BUILD_DIR)
+
+sim-qemu: $(OUT_ELF)
+	qemu-system-riscv32 -kernel $^  -S -s -machine sifive_e
+
+gdb: $(OUT_ELF)
+	$(GDB) -iex "set mem inaccessible-by-default off" -iex "set arch riscv:rv32" -iex "set riscv use_compressed_breakpoint off"
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/blinky_demo/main_blinky.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/blinky_demo/main_blinky.c
new file mode 100644
index 0000000..78b3747
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/blinky_demo/main_blinky.c
@@ -0,0 +1,203 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/******************************************************************************
+ * NOTE 1:  This project provides two demo applications.  A simple blinky
+ * style project, and a more comprehensive test and demo application.  The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
+ * between the two.  See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
+ * in main.c.  This file implements the simply blinky style version.
+ *
+ * NOTE 2:  This file only contains the source code that is specific to the
+ * basic demo.  Generic functions, such FreeRTOS hook functions, and functions
+ * required to configure the hardware are defined in main.c.
+ ******************************************************************************
+ *
+ * main_blinky() creates one queue, and two tasks.  It then starts the
+ * scheduler.
+ *
+ * The Queue Send Task:
+ * The queue send task is implemented by the prvQueueSendTask() function in
+ * this file.  prvQueueSendTask() sits in a loop that causes it to repeatedly
+ * block for 1000 milliseconds, before sending the value 100 to the queue that
+ * was created within main_blinky().  Once the value is sent, the task loops
+ * back around to block for another 1000 milliseconds...and so on.
+ *
+ * The Queue Receive Task:
+ * The queue receive task is implemented by the prvQueueReceiveTask() function
+ * in this file.  prvQueueReceiveTask() sits in a loop where it repeatedly
+ * blocks on attempts to read data from the queue that was created within
+ * main_blinky().  When data is received, the task checks the value of the
+ * data, and if the value equals the expected 100, writes 'Blink' to the UART
+ * (the UART is used in place of the LED to allow easy execution in QEMU).  The
+ * 'block time' parameter passed to the queue receive function specifies that
+ * the task should be held in the Blocked state indefinitely to wait for data to
+ * be available on the queue.  The queue receive task will only leave the
+ * Blocked state when the queue send task writes to the queue.  As the queue
+ * send task writes to the queue every 1000 milliseconds, the queue receive
+ * task leaves the Blocked state every 1000 milliseconds, and therefore toggles
+ * the LED every 200 milliseconds.
+ */
+
+/* Standard includes. */
+#include 
+#include 
+#include 
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* Priorities used by the tasks. */
+#define mainQUEUE_RECEIVE_TASK_PRIORITY		( tskIDLE_PRIORITY + 2 )
+#define	mainQUEUE_SEND_TASK_PRIORITY		( tskIDLE_PRIORITY + 1 )
+
+/* The rate at which data is sent to the queue.  The 200ms value is converted
+to ticks using the pdMS_TO_TICKS() macro. */
+#define mainQUEUE_SEND_FREQUENCY_MS			pdMS_TO_TICKS( 1000 )
+
+/* The maximum number items the queue can hold.  The priority of the receiving
+task is above the priority of the sending task, so the receiving task will
+preempt the sending task and remove the queue items each time the sending task
+writes to the queue.  Therefore the queue will never have more than one item in
+it at any time, and even with a queue length of 1, the sending task will never
+find the queue full. */
+#define mainQUEUE_LENGTH					( 1 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in
+ * main.c.
+ */
+void main_blinky( void );
+
+/*
+ * The tasks as described in the comments at the top of this file.
+ */
+static void prvQueueReceiveTask( void *pvParameters );
+static void prvQueueSendTask( void *pvParameters );
+
+/*-----------------------------------------------------------*/
+
+/* The queue used by both tasks. */
+static QueueHandle_t xQueue = NULL;
+
+/*-----------------------------------------------------------*/
+
+void main_blinky( void )
+{
+	/* Create the queue. */
+	xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );
+
+	if( xQueue != NULL )
+	{
+		/* Start the two tasks as described in the comments at the top of this
+		file. */
+		xTaskCreate( prvQueueReceiveTask,				/* The function that implements the task. */
+					"Rx", 								/* The text name assigned to the task - for debug only as it is not used by the kernel. */
+					configMINIMAL_STACK_SIZE * 2U, 			/* The size of the stack to allocate to the task. */
+					NULL, 								/* The parameter passed to the task - not used in this case. */
+					mainQUEUE_RECEIVE_TASK_PRIORITY, 	/* The priority assigned to the task. */
+					NULL );								/* The task handle is not required, so NULL is passed. */
+
+		xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE * 2U, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
+
+		/* Start the tasks and timer running. */
+		vTaskStartScheduler();
+	}
+
+	/* If all is well, the scheduler will now be running, and the following
+	line will never be reached.  If the following line does execute, then
+	there was insufficient FreeRTOS heap memory available for the Idle and/or
+	timer tasks to be created.  See the memory management section on the
+	FreeRTOS web site for more details on the FreeRTOS heap
+	http://www.freertos.org/a00111.html. */
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueSendTask( void *pvParameters )
+{
+TickType_t xNextWakeTime;
+const unsigned long ulValueToSend = 100UL;
+BaseType_t xReturned;
+
+	/* Remove compiler warning about unused parameter. */
+	( void ) pvParameters;
+
+	/* Initialise xNextWakeTime - this only needs to be done once. */
+	xNextWakeTime = xTaskGetTickCount();
+
+	for( ;; )
+	{
+		/* Place this task in the blocked state until it is time to run again. */
+		vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
+
+		/* Send to the queue - causing the queue receive task to unblock and
+		toggle the LED.  0 is used as the block time so the sending operation
+		will not block - it shouldn't need to block as the queue should always
+		be empty at this point in the code. */
+		xReturned = xQueueSend( xQueue, &ulValueToSend, 0U );
+		configASSERT( xReturned == pdPASS );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueReceiveTask( void *pvParameters )
+{
+unsigned long ulReceivedValue;
+const unsigned long ulExpectedValue = 100UL;
+const char * const pcPassMessage = "Blink\r\n";
+const char * const pcFailMessage = "Unexpected value received\r\n";
+
+	/* Remove compiler warning about unused parameter. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		/* Wait until something arrives in the queue - this task will block
+		indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
+		FreeRTOSConfig.h. */
+		xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
+
+		/*  To get here something must have been received from the queue, but
+		is it the expected value?  If it is, toggle the LED. */
+		if( ulReceivedValue == ulExpectedValue )
+		{
+			write( STDOUT_FILENO, pcPassMessage, strlen( pcPassMessage ) );
+			ulReceivedValue = 0U;
+		}
+		else
+		{
+			write( STDOUT_FILENO, pcFailMessage, strlen( pcFailMessage ) );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/fe310-xsvd.json b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/fe310-xsvd.json
new file mode 100644
index 0000000..d1767fa
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/fe310-xsvd.json
@@ -0,0 +1,2325 @@
+{
+  "schemaVersion": "0.2.4",
+  "contentVersion": "0.2.0",
+  "headerVersion": "0.2.0",
+  "device": {
+    "fe310": {
+      "displayName": "Freedom E310-G000",
+      "description": "The FE310-G000 is the first Freedom E300 SoC, and is the industry's first commercially available RISC-V SoC. The FE310-G000 is built around the E31 Core Complex instantiated in the Freedom E300 platform.",
+      "supplier": {
+        "name": "sifive",
+        "id": "1",
+        "displayName": "SiFive",
+        "fullName": "SiFive, Inc.",
+        "contact": "info@sifive.com"
+      },
+      "busWidth": "32",
+      "resetMask": "all",
+      "resetValue": "0x00000000",
+      "access": "rw",
+      "headerGuardPrefix": "SIFIVE_DEVICES_FE310_",
+      "headerTypePrefix": "sifive_fe310_",
+      "headerInterruptPrefix": "sifive_fe310_interrupt_global_",
+      "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+      "revision": "r0p0",
+      "numInterrupts": "51",
+      "priorityBits": "3",
+      "regWidth": "32",
+      "cores": {
+        "e31": {
+          "harts": "1",
+          "isa": "RV32IMAC",
+          "isaVersion": "2.2",
+          "mpu": "pmp",
+          "mmu": "none",
+          "localInterrupts": {
+            "machine_software": {
+              "description": "Machine Software Interrupt",
+              "value": "3"
+            },
+            "machine_timer": {
+              "description": "Machine Timer Interrupt",
+              "value": "7"
+            },
+            "machine_ext": {
+              "description": "Machine External Interrupt",
+              "value": "11"
+            }
+          },
+          "numLocalInterrupts": "0"
+        }
+      },
+      "peripherals": {
+        "clint": {
+          "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+          "baseAddress": "0x02000000",
+          "size": "0x10000",
+          "registers": {
+            "msip": {
+              "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+              "addressOffset": "0x0000",
+              "arraySize": "1"
+            }
+          },
+          "clusters": {
+            "mtimecmp": {
+              "description": "Machine Time Compare Registers per Hart",
+              "addressOffset": "0x4000",
+              "arraySize": "1",
+              "registers": {
+                "low": {
+                  "description": "Machine Compare Register Low",
+                  "addressOffset": "0x0000"
+                },
+                "high": {
+                  "description": "Machine Compare Register High",
+                  "addressOffset": "0x0004"
+                }
+              }
+            },
+            "mtime": {
+              "description": "Machine Time Register",
+              "addressOffset": "0xBFF8",
+              "access": "r",
+              "registers": {
+                "low": {
+                  "description": "Machine Time Register Low",
+                  "addressOffset": "0x0000"
+                },
+                "high": {
+                  "description": "Machine Time Register High",
+                  "addressOffset": "0x0004"
+                }
+              }
+            }
+          }
+        },
+        "plic": {
+          "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+          "baseAddress": "0x0C000000",
+          "size": "0x4000000",
+          "registers": {
+            "priorities": {
+              "arraySize": "52",
+              "description": "Interrupt Priorities Registers; 0 is reserved.",
+              "addressOffset": "0x0000",
+              "fields": {
+                "value": {
+                  "description": "The priority for a given global interrupt",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "pendings": {
+              "arraySize": "2",
+              "description": "Interrupt Pending Bits Registers",
+              "addressOffset": "0x1000",
+              "access": "r"
+            }
+          },
+          "clusters": {
+            "enablestarget0": {
+              "description": "Hart 0 Interrupt Enable Bits",
+              "addressOffset": "0x00002000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-mode Interrupt Enable Bits",
+                  "registers": {
+                    "enables": {
+                      "arraySize": "2",
+                      "description": "Interrupt Enable Bits Registers",
+                      "addressOffset": "0x0000"
+                    }
+                  }
+                }
+              }
+            },
+            "target0": {
+              "description": "Hart 0 Interrupt Thresholds",
+              "addressOffset": "0x00200000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-Mode Interrupt Threshold",
+                  "registers": {
+                    "threshold": {
+                      "description": "The Priority Threshold Register",
+                      "addressOffset": "0x0000",
+                      "fields": {
+                        "value": {
+                          "description": "The priority threshold value",
+                          "bitOffset": "0",
+                          "bitWidth": "3",
+                          "resetMask": "all",
+                          "resetValue": "0x0"
+                        }
+                      }
+                    },
+                    "claimcomplete": {
+                      "description": "The Interrupt Claim/Completion Register",
+                      "addressOffset": "0x0004"
+                    }
+                  }
+                }
+              }
+            }
+          }
+        },
+        "wdog": {
+          "description": "Watchdog Timer (WDT), part of Always-On Domain",
+          "baseAddress": "0x10000000",
+          "size": "0x0040",
+          "resetMask": "none",
+          "registers": {
+            "cfg": {
+              "description": "Watchdog Configuration Register",
+              "addressOffset": "0x0000",
+              "fields": {
+                "scale": {
+                  "description": "Watchdog counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "rsten": {
+                  "description": "Watchdog full reset enable",
+                  "bitOffset": "8",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "zerocmp": {
+                  "description": "Watchdog zero on comparator",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Watchdog enable counter always",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "encoreawake": {
+                  "description": "Watchdog counter only when awake",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmpip": {
+                  "description": "Watchdog interrupt pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Watchdog Count Register",
+              "addressOffset": "0x0008"
+            },
+            "scale": {
+              "description": "Watchdog Scale Register",
+              "addressOffset": "0x0010",
+              "fields": {
+                "value": {
+                  "description": "Watchdog scale value",
+                  "bitOffset": "0",
+                  "bitWidth": "16"
+                }
+              }
+            },
+            "feed": {
+              "description": "Watchdog Feed Address Register",
+              "addressOffset": "0x0018"
+            },
+            "key": {
+              "description": "Watchdog Key Register",
+              "addressOffset": "0x001C"
+            },
+            "cmp": {
+              "description": "Watchdog Compare Register",
+              "addressOffset": "0x0020",
+              "fields": {
+                "value": {
+                  "description": "Watchdog compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "16"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "wdogcmp": {
+              "description": "Watchdog Compare Interrupt",
+              "value": "1"
+            }
+          }
+        },
+        "rtc": {
+          "description": "Real-Time Clock (RTC), part of Always-On Domain",
+          "baseAddress": "0x10000040",
+          "size": "0x0030",
+          "resetMask": "none",
+          "registers": {
+            "cfg": {
+              "description": "RTC Configuration Register",
+              "addressOffset": "0x0000",
+              "fields": {
+                "scale": {
+                  "description": "RTC clock rate scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "enalways": {
+                  "description": "RTC counter enable",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmpip": {
+                  "description": "RTC comparator interrupt pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "low": {
+              "description": "RTC Counter Register Low",
+              "addressOffset": "0x0008"
+            },
+            "high": {
+              "description": "RTC Counter Register High",
+              "addressOffset": "0x000C",
+              "fields": {
+                "value": {
+                  "description": "RTC counter register, high bits",
+                  "bitOffset": "0",
+                  "bitWidth": "16"
+                }
+              }
+            },
+            "scale": {
+              "description": "RTC Scale Register",
+              "addressOffset": "0x0010"
+            },
+            "cmp": {
+              "description": "RTC Compare Register",
+              "addressOffset": "0x0020"
+            }
+          },
+          "interrupts": {
+            "rtccmp": {
+              "description": "RTC Compare Interrupt",
+              "value": "2"
+            }
+          }
+        },
+        "pmu": {
+          "description": "Power-Management Unit (PMU), part of Always-On Domain",
+          "baseAddress": "0x10000100",
+          "size": "0x0050",
+          "resetMask": "none",
+          "registers": {
+            "wakeupi": {
+              "description": "Wakeup program instruction Registers",
+              "addressOffset": "0x0000",
+              "arraySize": "8"
+            },
+            "sleepi": {
+              "description": "Sleep Program Instruction Registers",
+              "addressOffset": "0x0020",
+              "arraySize": "8"
+            },
+            "ie": {
+              "description": "PMU Interrupt Enables Register",
+              "addressOffset": "0x0040",
+              "fields": {
+                "rtc": {
+                  "description": "RTC Comparator active",
+                  "bitOffset": "1",
+                  "bitWidth": "1"
+                },
+                "dwakeup": {
+                  "description": "dwakeup_n pin active",
+                  "bitOffset": "2",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "cause": {
+              "description": "PMU Wakeup Cause Register",
+              "addressOffset": "0x0044",
+              "fields": {
+                "wakeupcause": {
+                  "description": "Wakeup cause",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "access": "r",
+                  "enumerations": {
+                    "wakeupcause-enum": {
+                      "description": "Wakeup Cause Values Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "reset",
+                          "description": "Reset Wakeup"
+                        },
+                        "1": {
+                          "displayName": "rtc",
+                          "description": "RTC Wakeup"
+                        },
+                        "2": {
+                          "displayName": "dwakeup",
+                          "description": "Digital input Wakeup"
+                        },
+                        "*": {
+                          "displayName": "undefined"
+                        }
+                      }
+                    }
+                  }
+                },
+                "resetcause": {
+                  "description": "Reset cause",
+                  "bitOffset": "8",
+                  "bitWidth": "2",
+                  "access": "r",
+                  "enumerations": {
+                    "resetcause-enum": {
+                      "description": "Reset Cause Values Enumeration",
+                      "values": {
+                        "1": {
+                          "displayName": "external",
+                          "description": "External reset"
+                        },
+                        "2": {
+                          "displayName": "watchdog",
+                          "description": "Watchdog timer reset"
+                        },
+                        "*": {
+                          "displayName": "undefined"
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "sleep": {
+              "description": "PMU Initiate Sleep Sequence Register",
+              "addressOffset": "0x0048"
+            },
+            "key": {
+              "description": "PMU Key Register",
+              "addressOffset": "0x004C"
+            }
+          }
+        },
+        "aon": {
+          "description": "Always-On (AON) Domain",
+          "baseAddress": "0x10000070",
+          "size": "0x0090",
+          "resetMask": "none",
+          "registers": {
+            "lfrosccfg": {
+              "description": "Internal Programmable Low-Frequency Ring Oscillator Register",
+              "addressOffset": "0x0000",
+              "fields": {
+                "div": {
+                  "description": "LFROSC divider",
+                  "bitOffset": "0",
+                  "bitWidth": "6",
+                  "resetMask": "all",
+                  "resetValue": "0x04"
+                },
+                "trim": {
+                  "description": "LFROSC trim value",
+                  "bitOffset": "16",
+                  "bitWidth": "5",
+                  "resetMask": "all",
+                  "resetValue": "0x10"
+                },
+                "en": {
+                  "description": "LFROSC enable",
+                  "bitOffset": "30",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "rdy": {
+                  "description": "LFROSC ready",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "backup": {
+              "description": "Backup Registers",
+              "addressOffset": "0x0010",
+              "arraySize": "32"
+            }
+          }
+        },
+        "prci": {
+          "description": "Power, Reset, Clock, Interrupt (PRCI) Peripheral",
+          "baseAddress": "0x10008000",
+          "size": "0x8000",
+          "registers": {
+            "hfrosccfg": {
+              "description": "Internal Trimmable Programmable 72 MHz Oscillator Register",
+              "addressOffset": "0x0000",
+              "fields": {
+                "div": {
+                  "description": "HFROSC divider",
+                  "bitOffset": "0",
+                  "bitWidth": "6",
+                  "resetMask": "all",
+                  "resetValue": "0x04"
+                },
+                "trim": {
+                  "description": "HFROSC trim value",
+                  "bitOffset": "16",
+                  "bitWidth": "5",
+                  "resetMask": "all",
+                  "resetValue": "0x10"
+                },
+                "en": {
+                  "description": "HFROSC enable",
+                  "bitOffset": "30",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "rdy": {
+                  "description": "HFROSC ready",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "hfxosccfg": {
+              "description": "External 16 MHz Crystal Oscillator Register",
+              "addressOffset": "0x0004",
+              "fields": {
+                "en": {
+                  "description": "HFXOSC enable",
+                  "bitOffset": "30",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "rdy": {
+                  "description": "HFXOSC ready",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "pllcfg": {
+              "description": "Internal High-Frequency PLL (HFPLL) Register",
+              "addressOffset": "0x0008",
+              "fields": {
+                "r": {
+                  "description": "PLL R input divider value",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x1",
+                  "enumerations": {
+                    "pllr-enum": {
+                      "description": "Reference Clock R Divide Ratio Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "/1",
+                          "headerName": "div1",
+                          "description": "Unchanged"
+                        },
+                        "1": {
+                          "displayName": "/2",
+                          "headerName": "div2",
+                          "description": "Divided by 2"
+                        },
+                        "2": {
+                          "displayName": "/3",
+                          "headerName": "div3",
+                          "description": "Divided by 3"
+                        },
+                        "3": {
+                          "displayName": "/4",
+                          "headerName": "div4",
+                          "description": "Divided by 4"
+                        }
+                      }
+                    }
+                  }
+                },
+                "f": {
+                  "description": "PLL F multiplier value",
+                  "bitOffset": "4",
+                  "bitWidth": "6",
+                  "resetMask": "all",
+                  "resetValue": "0x1F",
+                  "enumerations": {
+                    "pllf-enum": {
+                      "description": "Reference Clock F Multiplier Ratio Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "*2",
+                          "headerName": "mul2",
+                          "description": "Multiplied by 2"
+                        },
+                        "1": {
+                          "displayName": "*4",
+                          "headerName": "mul4",
+                          "description": "Multiplied by 4"
+                        },
+                        "2": {
+                          "displayName": "*6",
+                          "headerName": "mul6",
+                          "description": "Multiplied by 6"
+                        },
+                        "3": {
+                          "displayName": "*8",
+                          "headerName": "mul8",
+                          "description": "Multiplied by 8"
+                        },
+                        "4": {
+                          "displayName": "*10",
+                          "headerName": "mul10",
+                          "description": "Multiplied by 10"
+                        },
+                        "5": {
+                          "displayName": "*12",
+                          "headerName": "mul12",
+                          "description": "Multiplied by 12"
+                        },
+                        "6": {
+                          "displayName": "*14",
+                          "headerName": "mul14",
+                          "description": "Multiplied by 14"
+                        },
+                        "7": {
+                          "displayName": "*16",
+                          "headerName": "mul16",
+                          "description": "Multiplied by 16"
+                        },
+                        "8": {
+                          "displayName": "*18",
+                          "headerName": "mul18",
+                          "description": "Multiplied by 18"
+                        },
+                        "9": {
+                          "displayName": "*20",
+                          "headerName": "mul20",
+                          "description": "Multiplied by 20"
+                        },
+                        "10": {
+                          "displayName": "*22",
+                          "headerName": "mul22",
+                          "description": "Multiplied by 22"
+                        },
+                        "11": {
+                          "displayName": "*24",
+                          "headerName": "mul24",
+                          "description": "Multiplied by 24"
+                        },
+                        "12": {
+                          "displayName": "*26",
+                          "headerName": "mul26",
+                          "description": "Multiplied by 26"
+                        },
+                        "13": {
+                          "displayName": "*28",
+                          "headerName": "mul28",
+                          "description": "Multiplied by 28"
+                        },
+                        "14": {
+                          "displayName": "*30",
+                          "headerName": "mul30",
+                          "description": "Multiplied by 30"
+                        },
+                        "15": {
+                          "displayName": "*32",
+                          "headerName": "mul32",
+                          "description": "Multiplied by 32"
+                        },
+                        "16": {
+                          "displayName": "*34",
+                          "headerName": "mul34",
+                          "description": "Multiplied by 34"
+                        },
+                        "17": {
+                          "displayName": "*36",
+                          "headerName": "mul36",
+                          "description": "Multiplied by 36"
+                        },
+                        "18": {
+                          "displayName": "*38",
+                          "headerName": "mul38",
+                          "description": "Multiplied by 38"
+                        },
+                        "19": {
+                          "displayName": "*40",
+                          "headerName": "mul40",
+                          "description": "Multiplied by 40"
+                        },
+                        "20": {
+                          "displayName": "*42",
+                          "headerName": "mul42",
+                          "description": "Multiplied by 42"
+                        },
+                        "21": {
+                          "displayName": "*44",
+                          "headerName": "mul44",
+                          "description": "Multiplied by 44"
+                        },
+                        "22": {
+                          "displayName": "*46",
+                          "headerName": "mul46",
+                          "description": "Multiplied by 46"
+                        },
+                        "23": {
+                          "displayName": "*48",
+                          "headerName": "mul48",
+                          "description": "Multiplied by 48"
+                        },
+                        "24": {
+                          "displayName": "*50",
+                          "headerName": "mul50",
+                          "description": "Multiplied by 50"
+                        },
+                        "25": {
+                          "displayName": "*52",
+                          "headerName": "mul52",
+                          "description": "Multiplied by 52"
+                        },
+                        "26": {
+                          "displayName": "*54",
+                          "headerName": "mul54",
+                          "description": "Multiplied by 54"
+                        },
+                        "27": {
+                          "displayName": "*56",
+                          "headerName": "mul56",
+                          "description": "Multiplied by 56"
+                        },
+                        "28": {
+                          "displayName": "*58",
+                          "headerName": "mul58",
+                          "description": "Multiplied by 58"
+                        },
+                        "29": {
+                          "displayName": "*60",
+                          "headerName": "mul60",
+                          "description": "Multiplied by 60"
+                        },
+                        "30": {
+                          "displayName": "*62",
+                          "headerName": "mul62",
+                          "description": "Multiplied by 62"
+                        },
+                        "31": {
+                          "displayName": "*64",
+                          "headerName": "mul64",
+                          "description": "Multiplied by 64"
+                        },
+                        "32": {
+                          "displayName": "*66",
+                          "headerName": "mul66",
+                          "description": "Multiplied by 66"
+                        },
+                        "33": {
+                          "displayName": "*68",
+                          "headerName": "mul68",
+                          "description": "Multiplied by 68"
+                        },
+                        "34": {
+                          "displayName": "*70",
+                          "headerName": "mul70",
+                          "description": "Multiplied by 70"
+                        },
+                        "35": {
+                          "displayName": "*72",
+                          "headerName": "mul72",
+                          "description": "Multiplied by 72"
+                        },
+                        "36": {
+                          "displayName": "*74",
+                          "headerName": "mul74",
+                          "description": "Multiplied by 74"
+                        },
+                        "37": {
+                          "displayName": "*76",
+                          "headerName": "mul76",
+                          "description": "Multiplied by 76"
+                        },
+                        "38": {
+                          "displayName": "*78",
+                          "headerName": "mul78",
+                          "description": "Multiplied by 78"
+                        },
+                        "39": {
+                          "displayName": "*80",
+                          "headerName": "mul80",
+                          "description": "Multiplied by 80"
+                        },
+                        "40": {
+                          "displayName": "*82",
+                          "headerName": "mul82",
+                          "description": "Multiplied by 82"
+                        },
+                        "41": {
+                          "displayName": "*84",
+                          "headerName": "mul84",
+                          "description": "Multiplied by 84"
+                        },
+                        "42": {
+                          "displayName": "*86",
+                          "headerName": "mul86",
+                          "description": "Multiplied by 86"
+                        },
+                        "43": {
+                          "displayName": "*88",
+                          "headerName": "mul88",
+                          "description": "Multiplied by 88"
+                        },
+                        "44": {
+                          "displayName": "*90",
+                          "headerName": "mul90",
+                          "description": "Multiplied by 90"
+                        },
+                        "45": {
+                          "displayName": "*92",
+                          "headerName": "mul92",
+                          "description": "Multiplied by 92"
+                        },
+                        "46": {
+                          "displayName": "*94",
+                          "headerName": "mul94",
+                          "description": "Multiplied by 94"
+                        },
+                        "47": {
+                          "displayName": "*96",
+                          "headerName": "mul96",
+                          "description": "Multiplied by 96"
+                        },
+                        "48": {
+                          "displayName": "*98",
+                          "headerName": "mul98",
+                          "description": "Multiplied by 98"
+                        },
+                        "49": {
+                          "displayName": "*100",
+                          "headerName": "mul100",
+                          "description": "Multiplied by 100"
+                        },
+                        "50": {
+                          "displayName": "*102",
+                          "headerName": "mul102",
+                          "description": "Multiplied by 102"
+                        },
+                        "51": {
+                          "displayName": "*104",
+                          "headerName": "mul104",
+                          "description": "Multiplied by 104"
+                        },
+                        "52": {
+                          "displayName": "*106",
+                          "headerName": "mul106",
+                          "description": "Multiplied by 106"
+                        },
+                        "53": {
+                          "displayName": "*108",
+                          "headerName": "mul108",
+                          "description": "Multiplied by 108"
+                        },
+                        "54": {
+                          "displayName": "*110",
+                          "headerName": "mul110",
+                          "description": "Multiplied by 110"
+                        },
+                        "55": {
+                          "displayName": "*112",
+                          "headerName": "mul112",
+                          "description": "Multiplied by 112"
+                        },
+                        "56": {
+                          "displayName": "*114",
+                          "headerName": "mul114",
+                          "description": "Multiplied by 114"
+                        },
+                        "57": {
+                          "displayName": "*116",
+                          "headerName": "mul116",
+                          "description": "Multiplied by 116"
+                        },
+                        "58": {
+                          "displayName": "*118",
+                          "headerName": "mul118",
+                          "description": "Multiplied by 118"
+                        },
+                        "59": {
+                          "displayName": "*120",
+                          "headerName": "mul120",
+                          "description": "Multiplied by 120"
+                        },
+                        "60": {
+                          "displayName": "*122",
+                          "headerName": "mul122",
+                          "description": "Multiplied by 122"
+                        },
+                        "61": {
+                          "displayName": "*124",
+                          "headerName": "mul124",
+                          "description": "Multiplied by 124"
+                        },
+                        "62": {
+                          "displayName": "*126",
+                          "headerName": "mul126",
+                          "description": "Multiplied by 126"
+                        },
+                        "63": {
+                          "displayName": "*128",
+                          "headerName": "mul128",
+                          "description": "Multiplied by 128"
+                        }
+                      }
+                    }
+                  }
+                },
+                "q": {
+                  "description": "PLL Q output divider value",
+                  "bitOffset": "10",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x3",
+                  "enumerations": {
+                    "pllq-enum": {
+                      "description": "Reference Clock Q Divide Ratio Enumeration",
+                      "values": {
+                        "*": {
+                          "displayName": "n/a",
+                          "description": "Not supported"
+                        },
+                        "1": {
+                          "displayName": "/2",
+                          "headerName": "div2",
+                          "description": "Divided by 2"
+                        },
+                        "2": {
+                          "displayName": "/4",
+                          "headerName": "div4",
+                          "description": "Divided by 4"
+                        },
+                        "3": {
+                          "displayName": "/8",
+                          "headerName": "div8",
+                          "description": "Divided by 8"
+                        }
+                      }
+                    }
+                  }
+                },
+                "sel": {
+                  "description": "PLL select",
+                  "bitOffset": "16",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "refsel": {
+                  "description": "PLL reference select",
+                  "bitOffset": "17",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "bypass": {
+                  "description": "PLL bypass",
+                  "bitOffset": "18",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "lock": {
+                  "description": "PLL lock indicator",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "plloutdiv": {
+              "description": "PLL Output Divider",
+              "addressOffset": "0x000C"
+            }
+          }
+        },
+        "otp": {
+          "description": "One-Time Programmable Memory (OTP) Peripheral",
+          "baseAddress": "0x10010000",
+          "size": "0x1000",
+          "registers": {
+            "lock": {
+              "description": "Programmed-I/O Lock Register",
+              "addressOffset": "0x0000"
+            },
+            "ck": {
+              "description": "Device Clock Signal Register",
+              "addressOffset": "0x0004"
+            },
+            "oe": {
+              "description": "Device Output-Enable Signal Register",
+              "addressOffset": "0x0008"
+            },
+            "sel": {
+              "description": "Device Chip-Select Signal Register",
+              "addressOffset": "0x000C"
+            },
+            "we": {
+              "description": "Device Write-Enable Signal Register",
+              "addressOffset": "0x0010"
+            },
+            "mr": {
+              "description": "Device Mode Register",
+              "addressOffset": "0x0014"
+            },
+            "mrr": {
+              "description": "Read-Voltage Regulator Control Register",
+              "addressOffset": "0x0018"
+            },
+            "mpp": {
+              "description": "Write-Voltage Charge Pump Control Register",
+              "addressOffset": "0x001C"
+            },
+            "vrren": {
+              "description": "Read-Voltage Enable Register",
+              "addressOffset": "0x0020"
+            },
+            "vppen": {
+              "description": "Write-Voltage Enable Register",
+              "addressOffset": "0x0024"
+            },
+            "a": {
+              "description": "Device Address Register",
+              "addressOffset": "0x0028"
+            },
+            "d": {
+              "description": "Device Data Input Register",
+              "addressOffset": "0x002C"
+            },
+            "q": {
+              "description": "Device Data Output Register",
+              "addressOffset": "0x0030"
+            },
+            "rsctrl": {
+              "description": "Read Sequencer Control Register",
+              "addressOffset": "0x0034",
+              "fields": {
+                "scale": {
+                  "description": "OTP timescale",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "tas": {
+                  "description": "Address setup time",
+                  "bitOffset": "3",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "trp": {
+                  "description": "Read pulse time",
+                  "bitOffset": "4",
+                  "bitWidth": "1"
+                },
+                "tracc": {
+                  "description": "Read access time",
+                  "bitOffset": "5",
+                  "bitWidth": "1"
+                }
+              }
+            }
+          }
+        },
+        "gpio": {
+          "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+          "baseAddress": "0x10012000",
+          "size": "0x1000",
+          "registers": {
+            "value": {
+              "description": "Pin Value Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "inputen": {
+              "description": "Pin Input Enable Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Input Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outputen": {
+              "description": "Pin Output Enable Register",
+              "addressOffset": "0x008",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Output Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "port": {
+              "description": "Output Port Value Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output Port Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "pue": {
+              "description": "Internal Pull-up Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Internal Pull-up Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "ds": {
+              "description": "Pin Drive Strength Register",
+              "addressOffset": "0x014",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Drive Strength Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseie": {
+              "description": "Rise Interrupt Enable Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseip": {
+              "description": "Rise Interrupt Pending Register",
+              "addressOffset": "0x01C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallie": {
+              "description": "Fall Interrupt Enable Register",
+              "addressOffset": "0x020",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallip": {
+              "description": "Fall Interrupt Pending Register",
+              "addressOffset": "0x024",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highie": {
+              "description": "High Interrupt Enable Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highip": {
+              "description": "High Interrupt Pending Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowie": {
+              "description": "Low Interrupt Enable Register",
+              "addressOffset": "0x030",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowip": {
+              "description": "Low Interrupt Pending Register",
+              "addressOffset": "0x034",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofen": {
+              "description": "HW I/O Function Enable Register",
+              "addressOffset": "0x038",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofsel": {
+              "description": "HW I/O Function Select Register",
+              "addressOffset": "0x03C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Select Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outxor": {
+              "description": "Output XOR (invert) Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output XOR Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "gpio0": {
+              "description": "GPIO0 Interrupt",
+              "value": "8"
+            },
+            "gpio1": {
+              "description": "GPIO1 Interrupt",
+              "value": "9"
+            },
+            "gpio2": {
+              "description": "GPIO2 Interrupt",
+              "value": "10"
+            },
+            "gpio3": {
+              "description": "GPIO3 Interrupt",
+              "value": "11"
+            },
+            "gpio4": {
+              "description": "GPIO4 Interrupt",
+              "value": "12"
+            },
+            "gpio5": {
+              "description": "GPIO5 Interrupt",
+              "value": "13"
+            },
+            "gpio6": {
+              "description": "GPIO6 Interrupt",
+              "value": "14"
+            },
+            "gpio7": {
+              "description": "GPIO7 Interrupt",
+              "value": "15"
+            },
+            "gpio8": {
+              "description": "GPIO8 Interrupt",
+              "value": "16"
+            },
+            "gpio9": {
+              "description": "GPIO9 Interrupt",
+              "value": "17"
+            },
+            "gpio10": {
+              "description": "GPIO10 Interrupt",
+              "value": "18"
+            },
+            "gpio11": {
+              "description": "GPIO11 Interrupt",
+              "value": "19"
+            },
+            "gpio12": {
+              "description": "GPIO12 Interrupt",
+              "value": "20"
+            },
+            "gpio13": {
+              "description": "GPIO13 Interrupt",
+              "value": "21"
+            },
+            "gpio14": {
+              "description": "GPIO14 Interrupt",
+              "value": "22"
+            },
+            "gpio15": {
+              "description": "GPIO15 Interrupt",
+              "value": "23"
+            },
+            "gpio16": {
+              "description": "GPIO16 Interrupt",
+              "value": "24"
+            },
+            "gpio17": {
+              "description": "GPIO17 Interrupt",
+              "value": "25"
+            },
+            "gpio18": {
+              "description": "GPIO18 Interrupt",
+              "value": "26"
+            },
+            "gpio19": {
+              "description": "GPIO19 Interrupt",
+              "value": "27"
+            },
+            "gpio20": {
+              "description": "GPIO20 Interrupt",
+              "value": "28"
+            },
+            "gpio21": {
+              "description": "GPIO21 Interrupt",
+              "value": "29"
+            },
+            "gpio22": {
+              "description": "GPIO22 Interrupt",
+              "value": "30"
+            },
+            "gpio23": {
+              "description": "GPIO23 Interrupt",
+              "value": "31"
+            },
+            "gpio24": {
+              "description": "GPIO24 Interrupt",
+              "value": "32"
+            },
+            "gpio25": {
+              "description": "GPIO25 Interrupt",
+              "value": "33"
+            },
+            "gpio26": {
+              "description": "GPIO26 Interrupt",
+              "value": "34"
+            },
+            "gpio27": {
+              "description": "GPIO27 Interrupt",
+              "value": "35"
+            },
+            "gpio28": {
+              "description": "GPIO28 Interrupt",
+              "value": "36"
+            },
+            "gpio29": {
+              "description": "GPIO29 Interrupt",
+              "value": "37"
+            },
+            "gpio30": {
+              "description": "GPIO30 Interrupt",
+              "value": "38"
+            },
+            "gpio31": {
+              "description": "GPIO31 Interrupt",
+              "value": "39"
+            }
+          }
+        },
+        "uart0": {
+          "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+          "baseAddress": "0x10013000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "uart",
+          "registers": {
+            "txdata": {
+              "description": "Transmit Data Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "full": {
+                  "description": "Transmit FIFO full",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Receive Data Register",
+              "addressOffset": "0x004",
+              "resetMask": "none",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "access": "r"
+                },
+                "empty": {
+                  "description": "Receive FIFO empty",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txctrl": {
+              "description": "Transmit Control Register ",
+              "addressOffset": "0x008",
+              "fields": {
+                "txen": {
+                  "description": "Transmit enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "nstop": {
+                  "description": "Number of stop bits",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "txcnt": {
+                  "description": "Transmit watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "rxctrl": {
+              "description": "Receive Control Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "rxen": {
+                  "description": "Receive enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxcnt": {
+                  "description": "Receive watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x014",
+              "access": "r",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "div": {
+              "description": "Baud Rate Divisor Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "value": {
+                  "description": "Baud rate divisor",
+                  "bitOffset": "0",
+                  "bitWidth": "16",
+                  "resetMask": "all",
+                  "resetValue": "0x0000FFFF"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "uart0": {
+              "description": "UART0 Interrupt",
+              "value": "3"
+            }
+          }
+        },
+        "spi0": {
+          "description": "Serial Peripheral Interface (SPI) Peripheral",
+          "baseAddress": "0x10014000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "spi",
+          "registers": {
+            "sckdiv": {
+              "description": "Serial clock divisor Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Divisor for serial clock",
+                  "bitOffset": "0",
+                  "bitWidth": "12",
+                  "resetMask": "all",
+                  "resetValue": "0x003"
+                }
+              }
+            },
+            "sckmode": {
+              "description": "Serial Clock Mode Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "pha": {
+                  "description": "Serial clock phase",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "pol": {
+                  "description": "Serial clock polarity",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "csid": {
+              "description": "Chip Select ID Register",
+              "addressOffset": "0x010",
+              "resetMask": "all",
+              "resetValue": "0x00000000"
+            },
+            "csdef": {
+              "description": "Chip Select Default Register",
+              "addressOffset": "0x014",
+              "resetMask": "all",
+              "resetValue": "0x00000001"
+            },
+            "csmode": {
+              "description": "Chip Select Mode Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "mode": {
+                  "description": "Chip select mode",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "csmode-enum": {
+                      "description": "Chip Select Modes Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "auto",
+                          "description": "Assert/de-assert CS at the beginning/end of each frame"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        },
+                        "2": {
+                          "displayName": "hold",
+                          "description": "Keep CS continuously asserted after the initial frame"
+                        },
+                        "3": {
+                          "displayName": "off",
+                          "description": "Disable hardware control of the CS pin"
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "delay0": {
+              "description": "Delay Control 0 Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "cssck": {
+                  "description": "CS to SCK Delay",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "sckcs": {
+                  "description": "SCK to CS Delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "delay1": {
+              "description": "Delay Control 1 Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "intercs": {
+                  "description": "Minimum CS inactive time",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "interxfr": {
+                  "description": "Maximum interframe delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "fmt": {
+              "description": "Frame Format Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "proto": {
+                  "description": "SPI Protocol",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "proto-enum": {
+                      "description": "SPI Protocol Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "single",
+                          "description": "DQ0 (MOSI), DQ1 (MISO)"
+                        },
+                        "1": {
+                          "displayName": "dual",
+                          "description": "DQ0, DQ1"
+                        },
+                        "2": {
+                          "displayName": "quad",
+                          "description": "DQ0, DQ1, DQ2, DQ3"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        }
+                      }
+                    }
+                  }
+                },
+                "endian": {
+                  "description": "SPI endianness",
+                  "bitOffset": "2",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "endian-enum": {
+                      "description": "SPI Endianness Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "msb",
+                          "description": "Transmit most-significant bit (MSB) first"
+                        },
+                        "1": {
+                          "displayName": "lsb",
+                          "description": "Transmit least-significant bit (LSB) first"
+                        }
+                      }
+                    }
+                  }
+                },
+                "dir": {
+                  "description": "SPI I/O Direction",
+                  "bitOffset": "3",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1",
+                  "enumerations": {
+                    "dir-enum": {
+                      "description": "SPI I/O Direction Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "rx",
+                          "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+                        },
+                        "1": {
+                          "displayName": "tx",
+                          "description": "The receive FIFO is not populated."
+                        }
+                      }
+                    }
+                  }
+                },
+                "len": {
+                  "description": "Number of bits per frame",
+                  "bitOffset": "16",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x8"
+                }
+              }
+            },
+            "txdata": {
+              "description": "Tx FIFO Data Register",
+              "addressOffset": "0x048",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x00"
+                },
+                "full": {
+                  "description": "FIFO full flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Rx FIFO Data Register",
+              "addressOffset": "0x04C",
+              "resetMask": "none",
+              "access": "r",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "empty": {
+                  "description": "FIFO empty flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txmark": {
+              "description": "Tx FIFO Watermark Register",
+              "addressOffset": "0x050",
+              "fields": {
+                "value": {
+                  "description": "Transmit watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "rxmark": {
+              "description": "Rx FIFO Watermark Register",
+              "addressOffset": "0x054",
+              "fields": {
+                "value": {
+                  "description": "Receive watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "fctrl": {
+              "description": "Flash Interface Control Register",
+              "addressOffset": "0x060",
+              "fields": {
+                "en": {
+                  "description": "SPI Flash Mode Select",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "ffmt": {
+              "description": "Flash Instruction Format Register",
+              "addressOffset": "0x064",
+              "fields": {
+                "cmden": {
+                  "description": "Enable sending of command",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "addrlen": {
+                  "description": "Number of address bytes(0 to 4)",
+                  "bitOffset": "1",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x3"
+                },
+                "padcnt": {
+                  "description": "Number of dummy cycles",
+                  "bitOffset": "4",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdproto": {
+                  "description": "Protocol for transmitting command",
+                  "bitOffset": "8",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "addrproto": {
+                  "description": "Protocol for transmitting address and padding",
+                  "bitOffset": "10",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "dataproto": {
+                  "description": "Protocol for receiving data bytes",
+                  "bitOffset": "12",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdcode": {
+                  "description": "Value of command byte",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x03"
+                },
+                "padcode": {
+                  "description": "First 8 bits to transmit during dummy cycles",
+                  "bitOffset": "24",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x070",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x074",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r"
+                },
+                "rxwm": {
+                  "description": "Receive watermark pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "spi0": {
+              "description": "SPI0 Interrupt",
+              "value": "5"
+            }
+          }
+        },
+        "pwm0": {
+          "description": "Pulse-Width Modulation (PWM) Peripheral",
+          "baseAddress": "0x10015000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "registers": {
+            "cfg": {
+              "description": "Configuration Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "sticky": {
+                  "description": "Sticky - disallow clearing pwmcmpXip bits",
+                  "bitOffset": "8",
+                  "bitWidth": "1"
+                },
+                "zerocmp": {
+                  "description": "Zero - counter resets to zero after match",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "deglitch": {
+                  "description": "Deglitch - latch pwmcmpXip within same cycle",
+                  "bitOffset": "10",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Enable always - run continuously",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "enoneshot": {
+                  "description": "enable one shot - run one cycle",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmp0center": {
+                  "description": "PWM0 Compare Center",
+                  "bitOffset": "16",
+                  "bitWidth": "1"
+                },
+                "cmp1center": {
+                  "description": "PWM1 Compare Center",
+                  "bitOffset": "17",
+                  "bitWidth": "1"
+                },
+                "cmp2center": {
+                  "description": "PWM2 Compare Center",
+                  "bitOffset": "18",
+                  "bitWidth": "1"
+                },
+                "cmp3center": {
+                  "description": "PWM3 Compare Center",
+                  "bitOffset": "19",
+                  "bitWidth": "1"
+                },
+                "cmp0gang": {
+                  "description": "PWM0/PWM1 Compare Gang",
+                  "bitOffset": "24",
+                  "bitWidth": "1"
+                },
+                "cmp1gang": {
+                  "description": "PWM1/PWM2 Compare Gang",
+                  "bitOffset": "25",
+                  "bitWidth": "1"
+                },
+                "cmp2gang": {
+                  "description": "PWM2/PWM3 Compare Gang",
+                  "bitOffset": "26",
+                  "bitWidth": "1"
+                },
+                "cmp3gang": {
+                  "description": "PWM3/PWM0 Compare Gang",
+                  "bitOffset": "27",
+                  "bitWidth": "1"
+                },
+                "cmp0ip": {
+                  "description": "PWM0 Interrupt Pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                },
+                "cmp1ip": {
+                  "description": "PWM1 Interrupt Pending",
+                  "bitOffset": "29",
+                  "bitWidth": "1"
+                },
+                "cmp2ip": {
+                  "description": "PWM2 Interrupt Pending",
+                  "bitOffset": "30",
+                  "bitWidth": "1"
+                },
+                "cmp3ip": {
+                  "description": "PWM3 Interrupt Pending",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Configuration Register",
+              "addressOffset": "0x008"
+            },
+            "scale": {
+              "description": "Scale Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            },
+            "cmp": {
+              "arraySize": "4",
+              "description": "Compare Registers",
+              "addressOffset": "0x020",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "pwm0cmp0": {
+              "description": "PWM0 Compare 0 Interrupt",
+              "value": "40"
+            },
+            "pwm0cmp1": {
+              "description": "PWM0 Compare 1 Interrupt",
+              "value": "41"
+            },
+            "pwm0cmp2": {
+              "description": "PWM0 Compare 2 Interrupt",
+              "value": "42"
+            },
+            "pwm0cmp3": {
+              "description": "PWM0 Compare 3 Interrupt",
+              "value": "43"
+            }
+          }
+        },
+        "uart1": {
+          "baseAddress": "0x10023000",
+          "derivedFrom": "uart0",
+          "groupName": "uart",
+          "interrupts": {
+            "uart1": {
+              "description": "UART1 Interrupt",
+              "value": "4"
+            }
+          }
+        },
+        "spi1": {
+          "baseAddress": "0x10024000",
+          "derivedFrom": "spi0",
+          "groupName": "spi",
+          "interrupts": {
+            "spi1": {
+              "description": "SPI1 Interrupt",
+              "value": "6"
+            }
+          }
+        },
+        "pwm1": {
+          "description": "Pulse-Width Modulation (PWM) Peripheral",
+          "baseAddress": "0x10025000",
+          "groupName": "pwm",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "pwm",
+          "registers": {
+            "cfg": {
+              "description": "Configuration Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "sticky": {
+                  "description": "Sticky - disallow clearing pwmcmpXip bits",
+                  "bitOffset": "8",
+                  "bitWidth": "1"
+                },
+                "zerocmp": {
+                  "description": "Zero - counter resets to zero after match",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "deglitch": {
+                  "description": "Deglitch - latch pwmcmpXip within same cycle",
+                  "bitOffset": "10",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Enable always - run continuously",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "enoneshot": {
+                  "description": "enable one shot - run one cycle",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmp0center": {
+                  "description": "PWM0 Compare Center",
+                  "bitOffset": "16",
+                  "bitWidth": "1"
+                },
+                "cmp1center": {
+                  "description": "PWM1 Compare Center",
+                  "bitOffset": "17",
+                  "bitWidth": "1"
+                },
+                "cmp2center": {
+                  "description": "PWM2 Compare Center",
+                  "bitOffset": "18",
+                  "bitWidth": "1"
+                },
+                "cmp3center": {
+                  "description": "PWM3 Compare Center",
+                  "bitOffset": "19",
+                  "bitWidth": "1"
+                },
+                "cmp0gang": {
+                  "description": "PWM0/PWM1 Compare Gang",
+                  "bitOffset": "24",
+                  "bitWidth": "1"
+                },
+                "cmp1gang": {
+                  "description": "PWM1/PWM2 Compare Gang",
+                  "bitOffset": "25",
+                  "bitWidth": "1"
+                },
+                "cmp2gang": {
+                  "description": "PWM2/PWM3 Compare Gang",
+                  "bitOffset": "26",
+                  "bitWidth": "1"
+                },
+                "cmp3gang": {
+                  "description": "PWM3/PWM0 Compare Gang",
+                  "bitOffset": "27",
+                  "bitWidth": "1"
+                },
+                "cmp0ip": {
+                  "description": "PWM0 Interrupt Pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                },
+                "cmp1ip": {
+                  "description": "PWM1 Interrupt Pending",
+                  "bitOffset": "29",
+                  "bitWidth": "1"
+                },
+                "cmp2ip": {
+                  "description": "PWM2 Interrupt Pending",
+                  "bitOffset": "30",
+                  "bitWidth": "1"
+                },
+                "cmp3ip": {
+                  "description": "PWM3 Interrupt Pending",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Configuration Register",
+              "addressOffset": "0x008"
+            },
+            "scale": {
+              "description": "Scale Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "16"
+                }
+              }
+            },
+            "cmp": {
+              "arraySize": "4",
+              "description": "Compare Registers",
+              "addressOffset": "0x020",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "16"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "pwm1cmp0": {
+              "description": "PWM1 Compare 0 Interrupt",
+              "value": "44"
+            },
+            "pwm1cmp1": {
+              "description": "PWM1 Compare 1 Interrupt",
+              "value": "45"
+            },
+            "pwm1cmp2": {
+              "description": "PWM1 Compare 2 Interrupt",
+              "value": "46"
+            },
+            "pwm1cmp3": {
+              "description": "PWM1 Compare 3 Interrupt",
+              "value": "47"
+            }
+          }
+        },
+        "spi2": {
+          "baseAddress": "0x10034000",
+          "derivedFrom": "spi0",
+          "groupName": "spi",
+          "interrupts": {
+            "spi2": {
+              "description": "SPI2 Interrupt",
+              "value": "7"
+            }
+          }
+        },
+        "pwm2": {
+          "baseAddress": "0x10035000",
+          "derivedFrom": "pwm1",
+          "groupName": "pwm",
+          "interrupts": {
+            "pwm2cmp0": {
+              "description": "PWM2 Compare 0 Interrupt",
+              "value": "48"
+            },
+            "pwm2cmp1": {
+              "description": "PWM2 Compare 1 Interrupt",
+              "value": "49"
+            },
+            "pwm2cmp2": {
+              "description": "PWM2 Compare 2 Interrupt",
+              "value": "50"
+            },
+            "pwm2cmp3": {
+              "description": "PWM2 Compare 3 Interrupt",
+              "value": "51"
+            }
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/LICENSE(Freedom-e-SDK) b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/LICENSE(Freedom-e-SDK)
new file mode 100644
index 0000000..0b0b6c8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/LICENSE(Freedom-e-SDK)
@@ -0,0 +1,206 @@
+
+This software, except as otherwise noted in subrepositories, 
+is licensed under the Apache 2 license, quoted below.
+
+
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+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
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+
+   Unless required by applicable law or agreed to in writing, software
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diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/drivers/fe300prci/fe300prci_driver.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/drivers/fe300prci/fe300prci_driver.c
new file mode 100644
index 0000000..214b1d5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/drivers/fe300prci/fe300prci_driver.c
@@ -0,0 +1,252 @@
+// See LICENSE file for license details
+
+#include "platform.h"
+
+#ifdef PRCI_CTRL_ADDR
+#include "fe300prci/fe300prci_driver.h"
+#include 
+
+#define rdmcycle(x)  {				       \
+    uint32_t lo, hi, hi2;			       \
+    __asm__ __volatile__ ("1:\n\t"		       \
+			  "csrr %0, mcycleh\n\t"       \
+			  "csrr %1, mcycle\n\t"	       \
+			  "csrr %2, mcycleh\n\t"		\
+			  "bne  %0, %2, 1b\n\t"			\
+			  : "=r" (hi), "=r" (lo), "=r" (hi2)) ;	\
+    *(x) = lo | ((uint64_t) hi << 32); 				\
+  }
+
+uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq)
+{
+
+  uint32_t start_mtime = CLINT_REG(CLINT_MTIME);
+  uint32_t end_mtime = start_mtime + mtime_ticks + 1;
+
+  // Make sure we won't get rollover.
+  while (end_mtime < start_mtime){
+    start_mtime = CLINT_REG(CLINT_MTIME);
+    end_mtime = start_mtime + mtime_ticks + 1;
+  }
+
+  // Don't start measuring until mtime edge.
+  uint32_t tmp = start_mtime;
+  do {
+    start_mtime = CLINT_REG(CLINT_MTIME);
+  } while (start_mtime == tmp);
+  
+  uint64_t start_mcycle;
+  rdmcycle(&start_mcycle);
+  
+  while (CLINT_REG(CLINT_MTIME) < end_mtime) ;
+  
+  uint64_t end_mcycle;
+  rdmcycle(&end_mcycle);
+  uint32_t difference = (uint32_t) (end_mcycle - start_mcycle);
+
+  uint64_t freq = ((uint64_t) difference * mtime_freq) / mtime_ticks;
+  return (uint32_t) freq & 0xFFFFFFFF;
+  
+}
+ 
+
+void PRCI_use_hfrosc(int div, int trim)
+{
+  // Make sure the HFROSC is running at its default setting
+  // It is OK to change this even if we are running off of it.
+  
+  PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1));
+
+  while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0);
+  
+  PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1);
+}
+
+void PRCI_use_pll(int refsel, int bypass,
+			 int r, int f, int q, int finaldiv,
+			 int hfroscdiv, int hfrosctrim)
+{
+  // Ensure that we aren't running off the PLL before we mess with it.
+  if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {
+    // Make sure the HFROSC is running at its default setting
+    PRCI_use_hfrosc(4, 16);
+  }
+  
+  // Set PLL Source to be HFXOSC if desired.
+  uint32_t config_value = 0;
+
+  config_value |= PLL_REFSEL(refsel);
+  
+  if (bypass) {
+    // Bypass
+    config_value |= PLL_BYPASS(1);
+
+    PRCI_REG(PRCI_PLLCFG) = config_value;
+
+    // If we don't have an HFXTAL, this doesn't really matter.
+    // Set our Final output divide to divide-by-1:
+    PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
+  } else {
+  
+    // To overclock, use the hfrosc
+    if (hfrosctrim >= 0 && hfroscdiv >= 0) {
+      PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
+    }
+    
+    // Set DIV Settings for PLL
+    
+    // (Legal values of f_REF are 6-48MHz)
+
+    // Set DIVR to divide-by-2 to get 8MHz frequency
+    // (legal values of f_R are 6-12 MHz)
+
+    config_value |= PLL_BYPASS(1);
+    config_value |= PLL_R(r);
+
+    // Set DIVF to get 512Mhz frequncy
+    // There is an implied multiply-by-2, 16Mhz.
+    // So need to write 32-1
+    // (legal values of f_F are 384-768 MHz)
+    config_value |= PLL_F(f);
+
+    // Set DIVQ to divide-by-2 to get 256 MHz frequency
+    // (legal values of f_Q are 50-400Mhz)
+    config_value |= PLL_Q(q);
+
+    // Set our Final output divide to divide-by-1:
+    if (finaldiv == 1){
+      PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
+    } else {
+      PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV(finaldiv-1));
+    }
+
+    PRCI_REG(PRCI_PLLCFG) = config_value;
+
+    // Un-Bypass the PLL.
+    PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
+
+    // Wait for PLL Lock
+    // Note that the Lock signal can be glitchy.
+    // Need to wait 100 us
+    // RTC is running at 32kHz.
+    // So wait 4 ticks of RTC.
+    uint32_t now = CLINT_REG(CLINT_MTIME);
+    while (CLINT_REG(CLINT_MTIME) - now < 4) ;
+    
+    // Now it is safe to check for PLL Lock
+    while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0);
+
+  }
+
+  // Switch over to PLL Clock source
+  PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);
+
+  // If we're running off HFXOSC, turn off the HFROSC to
+  // save power.
+  if (refsel) {
+    PRCI_REG(PRCI_HFROSCCFG) &= ~ROSC_EN(1);
+  }
+  
+}
+
+void PRCI_use_default_clocks()
+{
+  // Turn off the LFROSC
+  AON_REG(AON_LFROSC) &= ~ROSC_EN(1);
+
+  // Use HFROSC
+  PRCI_use_hfrosc(4, 16);
+}
+
+void PRCI_use_hfxosc(uint32_t finaldiv)
+{
+  
+  PRCI_use_pll(1, // Use HFXTAL
+	       1, // Bypass = 1
+	       0, // PLL settings don't matter
+	       0, // PLL settings don't matter
+	       0, // PLL settings don't matter
+	       finaldiv,
+	       -1,
+	       -1);
+}
+
+// This is a generic function, which
+// doesn't span the entire range of HFROSC settings.
+// It only adjusts the trim, which can span a hundred MHz or so.
+// This function does not check the legality of the PLL settings
+// at all, and it is quite possible to configure invalid PLL settings
+// this way.
+// It returns the actual measured CPU frequency.
+
+uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target )
+{
+
+  uint32_t hfrosctrim = 0;
+  uint32_t hfroscdiv = 4;
+  uint32_t prev_trim = 0;
+
+  // In this function we use PLL settings which
+  // will give us a 32x multiplier from the output
+  // of the HFROSC source to the output of the
+  // PLL. We first measure our HFROSC to get the
+  // right trim, then finally use it as the PLL source.
+  // We should really check here that the f_cpu
+  // requested is something in the limit of the PLL. For
+  // now that is up to the user.
+
+  // This will undershoot for frequencies not divisible by 16.
+  uint32_t desired_hfrosc_freq = (f_cpu/ 16);
+
+  PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
+  
+  // Ignore the first run (for icache reasons)
+  uint32_t cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
+
+  cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
+  uint32_t prev_freq = cpu_freq;
+  
+  while ((cpu_freq < desired_hfrosc_freq) && (hfrosctrim < 0x1F)){
+    prev_trim = hfrosctrim;
+    prev_freq = cpu_freq;
+    hfrosctrim ++;
+    PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
+    cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
+  } 
+
+  // We couldn't go low enough
+  if (prev_freq > desired_hfrosc_freq){
+    PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
+    cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ);
+    return cpu_freq;
+  }
+  
+  // We couldn't go high enough
+  if (cpu_freq < desired_hfrosc_freq){
+    PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
+    cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ);
+    return cpu_freq;
+  }
+
+  // Check for over/undershoot
+  switch(target) {
+  case(PRCI_FREQ_CLOSEST):
+    if ((desired_hfrosc_freq - prev_freq) < (cpu_freq - desired_hfrosc_freq)) {
+      PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
+    } else {
+      PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim);
+    }
+    break;
+  case(PRCI_FREQ_UNDERSHOOT):
+    PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
+    break;
+  default:
+    PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim);
+  }
+
+  cpu_freq =  PRCI_measure_mcycle_freq(1000, RTC_FREQ);
+  return cpu_freq;
+
+}
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/drivers/fe300prci/fe300prci_driver.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/drivers/fe300prci/fe300prci_driver.h
new file mode 100644
index 0000000..5ad9c0c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/drivers/fe300prci/fe300prci_driver.h
@@ -0,0 +1,79 @@
+// See LICENSE file for license details
+
+#ifndef _FE300PRCI_DRIVER_H_
+#define _FE300PRCI_DRIVER_H_
+
+__BEGIN_DECLS
+
+#include 
+
+typedef enum prci_freq_target {
+  
+  PRCI_FREQ_OVERSHOOT,
+  PRCI_FREQ_CLOSEST,
+  PRCI_FREQ_UNDERSHOOT
+
+} PRCI_freq_target;
+
+/* Measure and return the approximate frequency of the 
+ * CPU, as given by measuring the mcycle counter against 
+ * the mtime ticks.
+ */
+uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq);
+
+/* Safely switch over to the HFROSC using the given div
+ * and trim settings.
+ */
+void PRCI_use_hfrosc(int div, int trim);
+
+/* Safely switch over to the 16MHz HFXOSC,
+ * applying the finaldiv clock divider (1 is the lowest
+ * legal value).
+ */
+void PRCI_use_hfxosc(uint32_t finaldiv);
+
+/* Safely switch over to the PLL using the given
+ * settings.
+ * 
+ * Note that not all combinations of the inputs are actually
+ * legal, and this function does not check for their
+ * legality ("safely" means that this function won't turn off
+ * or glitch the clock the CPU is actually running off, but
+ * doesn't protect against you making it too fast or slow.)
+ */
+
+void PRCI_use_pll(int refsel, int bypass,
+			 int r, int f, int q, int finaldiv,
+			 int hfroscdiv, int hfrosctrim);
+
+/* Use the default clocks configured at reset.
+ * This is ~16Mhz HFROSC and turns off the LFROSC
+ * (on the current FE310 Dev Platforms, an external LFROSC is 
+ * used as it is more power efficient).
+ */
+void PRCI_use_default_clocks();
+
+/* This routine will adjust the HFROSC trim
+ * while using HFROSC as the clock source, 
+ * measure the resulting frequency, then
+ * use it as the PLL clock source, 
+ * in an attempt to get over, under, or close to the 
+ * requested frequency. It returns the actual measured 
+ * frequency. 
+ *
+ * Note that the requested frequency must be within the 
+ * range supported by the PLL so not all values are 
+ * achievable with this function, and not all 
+ * are guaranteed to actually work. The PLL
+ * is rated higher than the hardware.
+ * 
+ * There is no check on the desired f_cpu frequency, it
+ * is up to the user to specify something reasonable.
+ */
+
+uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target);
+
+__END_DECLS
+
+#endif
+  
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/drivers/plic/plic_driver.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/drivers/plic/plic_driver.c
new file mode 100644
index 0000000..4f0e495
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/drivers/plic/plic_driver.c
@@ -0,0 +1,127 @@
+// See LICENSE for license details.
+
+#include "sifive/devices/plic.h"
+#include "plic/plic_driver.h"
+#include "platform.h"
+#include "encoding.h"
+#include 
+
+
+// Note that there are no assertions or bounds checking on these
+// parameter values.
+
+void volatile_memzero(uint8_t * base, unsigned int size)
+{
+  volatile uint8_t * ptr;
+  for (ptr = base; ptr < (base + size); ptr++){
+    *ptr = 0;
+  }
+}
+
+void PLIC_init (
+                plic_instance_t * this_plic,
+                uintptr_t         base_addr,
+                uint32_t num_sources,
+                uint32_t num_priorities
+                )
+{
+  
+  this_plic->base_addr = base_addr;
+  this_plic->num_sources = num_sources;
+  this_plic->num_priorities = num_priorities;
+  
+  // Disable all interrupts (don't assume that these registers are reset).
+  unsigned long hart_id = read_csr(mhartid);
+  volatile_memzero((uint8_t*) (this_plic->base_addr +
+                               PLIC_ENABLE_OFFSET +
+                               (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET)),
+                   (num_sources + 8) / 8);
+  
+  // Set all priorities to 0 (equal priority -- don't assume that these are reset).
+  volatile_memzero ((uint8_t *)(this_plic->base_addr +
+                                PLIC_PRIORITY_OFFSET),
+                    (num_sources + 1) << PLIC_PRIORITY_SHIFT_PER_SOURCE);
+
+  // Set the threshold to 0.
+  volatile plic_threshold* threshold = (plic_threshold*)
+    (this_plic->base_addr +
+     PLIC_THRESHOLD_OFFSET +
+     (hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET));
+
+  *threshold = 0;
+  
+}
+
+void PLIC_set_threshold (plic_instance_t * this_plic,
+			 plic_threshold threshold){
+
+  unsigned long hart_id = read_csr(mhartid);  
+  volatile plic_threshold* threshold_ptr = (plic_threshold*) (this_plic->base_addr +
+                                                              PLIC_THRESHOLD_OFFSET +
+                                                              (hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET));
+
+  *threshold_ptr = threshold;
+
+}
+  
+
+void PLIC_enable_interrupt (plic_instance_t * this_plic, plic_source source){
+
+  unsigned long hart_id = read_csr(mhartid);
+  volatile uint8_t * current_ptr = (volatile uint8_t *)(this_plic->base_addr +
+                                                        PLIC_ENABLE_OFFSET +
+                                                        (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) +
+                                                        (source >> 3));
+  uint8_t current = *current_ptr;
+  current = current | ( 1 << (source & 0x7));
+  *current_ptr = current;
+
+}
+
+void PLIC_disable_interrupt (plic_instance_t * this_plic, plic_source source){
+  
+  unsigned long hart_id = read_csr(mhartid);
+  volatile uint8_t * current_ptr = (volatile uint8_t *) (this_plic->base_addr +
+                                                         PLIC_ENABLE_OFFSET +
+                                                         (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) +
+                                                         (source >> 3));
+  uint8_t current = *current_ptr;
+  current = current & ~(( 1 << (source & 0x7)));
+  *current_ptr = current;
+  
+}
+
+void PLIC_set_priority (plic_instance_t * this_plic, plic_source source, plic_priority priority){
+
+  if (this_plic->num_priorities > 0) {
+    volatile plic_priority * priority_ptr = (volatile plic_priority *)
+      (this_plic->base_addr +
+       PLIC_PRIORITY_OFFSET +
+       (source << PLIC_PRIORITY_SHIFT_PER_SOURCE));
+    *priority_ptr = priority;
+  }
+}
+
+plic_source PLIC_claim_interrupt(plic_instance_t * this_plic){
+  
+  unsigned long hart_id = read_csr(mhartid);
+
+  volatile plic_source * claim_addr = (volatile plic_source * )
+    (this_plic->base_addr +
+     PLIC_CLAIM_OFFSET +
+     (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET));
+
+  return  *claim_addr;
+  
+}
+
+void PLIC_complete_interrupt(plic_instance_t * this_plic, plic_source source){
+  
+  unsigned long hart_id = read_csr(mhartid);
+  volatile plic_source * claim_addr = (volatile plic_source *) (this_plic->base_addr +
+                                                                PLIC_CLAIM_OFFSET +
+                                                                (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET));
+  *claim_addr = source;
+  
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/drivers/plic/plic_driver.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/drivers/plic/plic_driver.h
new file mode 100644
index 0000000..8ce8e51
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/drivers/plic/plic_driver.h
@@ -0,0 +1,51 @@
+// See LICENSE file for licence details
+
+#ifndef PLIC_DRIVER_H
+#define PLIC_DRIVER_H
+
+
+__BEGIN_DECLS
+
+#include "platform.h"
+
+typedef struct __plic_instance_t
+{
+  uintptr_t base_addr;
+
+  uint32_t num_sources;
+  uint32_t num_priorities;
+  
+} plic_instance_t;
+
+typedef uint32_t plic_source;
+typedef uint32_t plic_priority;
+typedef uint32_t plic_threshold;
+
+void PLIC_init (
+                plic_instance_t * this_plic,
+                uintptr_t         base_addr,
+                uint32_t num_sources,
+                uint32_t num_priorities
+                );
+
+void PLIC_set_threshold (plic_instance_t * this_plic,
+			 plic_threshold threshold);
+  
+void PLIC_enable_interrupt (plic_instance_t * this_plic,
+			    plic_source source);
+
+void PLIC_disable_interrupt (plic_instance_t * this_plic,
+			     plic_source source);
+  
+void PLIC_set_priority (plic_instance_t * this_plic,
+			plic_source source,
+			plic_priority priority);
+
+plic_source PLIC_claim_interrupt(plic_instance_t * this_plic);
+
+void PLIC_complete_interrupt(plic_instance_t * this_plic,
+			     plic_source source);
+
+__END_DECLS
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/encoding.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/encoding.h
new file mode 100644
index 0000000..417e751
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/encoding.h
@@ -0,0 +1,1313 @@
+// See LICENSE for license details.
+
+#ifndef RISCV_CSR_ENCODING_H
+#define RISCV_CSR_ENCODING_H
+
+#define MSTATUS_UIE         0x00000001
+#define MSTATUS_SIE         0x00000002
+#define MSTATUS_HIE         0x00000004
+#define MSTATUS_MIE         0x00000008
+#define MSTATUS_UPIE        0x00000010
+#define MSTATUS_SPIE        0x00000020
+#define MSTATUS_HPIE        0x00000040
+#define MSTATUS_MPIE        0x00000080
+#define MSTATUS_SPP         0x00000100
+#define MSTATUS_HPP         0x00000600
+#define MSTATUS_MPP         0x00001800
+#define MSTATUS_FS          0x00006000
+#define MSTATUS_XS          0x00018000
+#define MSTATUS_MPRV        0x00020000
+#define MSTATUS_PUM         0x00040000
+#define MSTATUS_MXR         0x00080000
+#define MSTATUS_VM          0x1F000000
+#define MSTATUS32_SD        0x80000000
+#define MSTATUS64_SD        0x8000000000000000
+
+#define SSTATUS_UIE         0x00000001
+#define SSTATUS_SIE         0x00000002
+#define SSTATUS_UPIE        0x00000010
+#define SSTATUS_SPIE        0x00000020
+#define SSTATUS_SPP         0x00000100
+#define SSTATUS_FS          0x00006000
+#define SSTATUS_XS          0x00018000
+#define SSTATUS_PUM         0x00040000
+#define SSTATUS32_SD        0x80000000
+#define SSTATUS64_SD        0x8000000000000000
+
+#define DCSR_XDEBUGVER      (3U<<30)
+#define DCSR_NDRESET        (1<<29)
+#define DCSR_FULLRESET      (1<<28)
+#define DCSR_EBREAKM        (1<<15)
+#define DCSR_EBREAKH        (1<<14)
+#define DCSR_EBREAKS        (1<<13)
+#define DCSR_EBREAKU        (1<<12)
+#define DCSR_STOPCYCLE      (1<<10)
+#define DCSR_STOPTIME       (1<<9)
+#define DCSR_CAUSE          (7<<6)
+#define DCSR_DEBUGINT       (1<<5)
+#define DCSR_HALT           (1<<3)
+#define DCSR_STEP           (1<<2)
+#define DCSR_PRV            (3<<0)
+
+#define DCSR_CAUSE_NONE     0
+#define DCSR_CAUSE_SWBP     1
+#define DCSR_CAUSE_HWBP     2
+#define DCSR_CAUSE_DEBUGINT 3
+#define DCSR_CAUSE_STEP     4
+#define DCSR_CAUSE_HALT     5
+
+#define MCONTROL_TYPE(xlen)    (0xfULL<<((xlen)-4))
+#define MCONTROL_DMODE(xlen)   (1ULL<<((xlen)-5))
+#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
+
+#define MCONTROL_SELECT     (1<<19)
+#define MCONTROL_TIMING     (1<<18)
+#define MCONTROL_ACTION     (0x3f<<12)
+#define MCONTROL_CHAIN      (1<<11)
+#define MCONTROL_MATCH      (0xf<<7)
+#define MCONTROL_M          (1<<6)
+#define MCONTROL_H          (1<<5)
+#define MCONTROL_S          (1<<4)
+#define MCONTROL_U          (1<<3)
+#define MCONTROL_EXECUTE    (1<<2)
+#define MCONTROL_STORE      (1<<1)
+#define MCONTROL_LOAD       (1<<0)
+
+#define MCONTROL_TYPE_NONE      0
+#define MCONTROL_TYPE_MATCH     2
+
+#define MCONTROL_ACTION_DEBUG_EXCEPTION   0
+#define MCONTROL_ACTION_DEBUG_MODE        1
+#define MCONTROL_ACTION_TRACE_START       2
+#define MCONTROL_ACTION_TRACE_STOP        3
+#define MCONTROL_ACTION_TRACE_EMIT        4
+
+#define MCONTROL_MATCH_EQUAL     0
+#define MCONTROL_MATCH_NAPOT     1
+#define MCONTROL_MATCH_GE        2
+#define MCONTROL_MATCH_LT        3
+#define MCONTROL_MATCH_MASK_LOW  4
+#define MCONTROL_MATCH_MASK_HIGH 5
+
+#define MIP_SSIP            (1 << IRQ_S_SOFT)
+#define MIP_HSIP            (1 << IRQ_H_SOFT)
+#define MIP_MSIP            (1 << IRQ_M_SOFT)
+#define MIP_STIP            (1 << IRQ_S_TIMER)
+#define MIP_HTIP            (1 << IRQ_H_TIMER)
+#define MIP_MTIP            (1 << IRQ_M_TIMER)
+#define MIP_SEIP            (1 << IRQ_S_EXT)
+#define MIP_HEIP            (1 << IRQ_H_EXT)
+#define MIP_MEIP            (1 << IRQ_M_EXT)
+
+#define SIP_SSIP MIP_SSIP
+#define SIP_STIP MIP_STIP
+
+#define PRV_U 0
+#define PRV_S 1
+#define PRV_H 2
+#define PRV_M 3
+
+#define VM_MBARE 0
+#define VM_MBB   1
+#define VM_MBBID 2
+#define VM_SV32  8
+#define VM_SV39  9
+#define VM_SV48  10
+
+#define IRQ_S_SOFT   1
+#define IRQ_H_SOFT   2
+#define IRQ_M_SOFT   3
+#define IRQ_S_TIMER  5
+#define IRQ_H_TIMER  6
+#define IRQ_M_TIMER  7
+#define IRQ_S_EXT    9
+#define IRQ_H_EXT    10
+#define IRQ_M_EXT    11
+#define IRQ_COP      12
+#define IRQ_HOST     13
+
+#define DEFAULT_RSTVEC     0x00001000
+#define DEFAULT_NMIVEC     0x00001004
+#define DEFAULT_MTVEC      0x00001010
+#define CONFIG_STRING_ADDR 0x0000100C
+#define EXT_IO_BASE        0x40000000
+#define DRAM_BASE          0x80000000
+
+// page table entry (PTE) fields
+#define PTE_V     0x001 // Valid
+#define PTE_R     0x002 // Read
+#define PTE_W     0x004 // Write
+#define PTE_X     0x008 // Execute
+#define PTE_U     0x010 // User
+#define PTE_G     0x020 // Global
+#define PTE_A     0x040 // Accessed
+#define PTE_D     0x080 // Dirty
+#define PTE_SOFT  0x300 // Reserved for Software
+
+#define PTE_PPN_SHIFT 10
+
+#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
+
+#ifdef __riscv
+
+#ifdef __riscv64
+# define MSTATUS_SD MSTATUS64_SD
+# define SSTATUS_SD SSTATUS64_SD
+# define RISCV_PGLEVEL_BITS 9
+#else
+# define MSTATUS_SD MSTATUS32_SD
+# define SSTATUS_SD SSTATUS32_SD
+# define RISCV_PGLEVEL_BITS 10
+#endif
+#define RISCV_PGSHIFT 12
+#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
+
+#ifndef __ASSEMBLER__
+
+#ifdef __GNUC__
+
+#define read_csr(reg) ({ unsigned long __tmp; \
+  asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+  __tmp; })
+
+#define write_csr(reg, val) ({ \
+  if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+    asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
+  else \
+    asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
+
+#define swap_csr(reg, val) ({ unsigned long __tmp; \
+  if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+    asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
+  else \
+    asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
+  __tmp; })
+
+#define set_csr(reg, bit) ({ unsigned long __tmp; \
+  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+    asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+  else \
+    asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+  __tmp; })
+
+#define clear_csr(reg, bit) ({ unsigned long __tmp; \
+  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+    asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+  else \
+    asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+  __tmp; })
+
+#define rdtime() read_csr(time)
+#define rdcycle() read_csr(cycle)
+#define rdinstret() read_csr(instret)
+
+#endif
+
+#endif
+
+#endif
+
+#endif
+/* Automatically generated by parse-opcodes */
+#ifndef RISCV_ENCODING_H
+#define RISCV_ENCODING_H
+#define MATCH_BEQ 0x63
+#define MASK_BEQ  0x707f
+#define MATCH_BNE 0x1063
+#define MASK_BNE  0x707f
+#define MATCH_BLT 0x4063
+#define MASK_BLT  0x707f
+#define MATCH_BGE 0x5063
+#define MASK_BGE  0x707f
+#define MATCH_BLTU 0x6063
+#define MASK_BLTU  0x707f
+#define MATCH_BGEU 0x7063
+#define MASK_BGEU  0x707f
+#define MATCH_JALR 0x67
+#define MASK_JALR  0x707f
+#define MATCH_JAL 0x6f
+#define MASK_JAL  0x7f
+#define MATCH_LUI 0x37
+#define MASK_LUI  0x7f
+#define MATCH_AUIPC 0x17
+#define MASK_AUIPC  0x7f
+#define MATCH_ADDI 0x13
+#define MASK_ADDI  0x707f
+#define MATCH_SLLI 0x1013
+#define MASK_SLLI  0xfc00707f
+#define MATCH_SLTI 0x2013
+#define MASK_SLTI  0x707f
+#define MATCH_SLTIU 0x3013
+#define MASK_SLTIU  0x707f
+#define MATCH_XORI 0x4013
+#define MASK_XORI  0x707f
+#define MATCH_SRLI 0x5013
+#define MASK_SRLI  0xfc00707f
+#define MATCH_SRAI 0x40005013
+#define MASK_SRAI  0xfc00707f
+#define MATCH_ORI 0x6013
+#define MASK_ORI  0x707f
+#define MATCH_ANDI 0x7013
+#define MASK_ANDI  0x707f
+#define MATCH_ADD 0x33
+#define MASK_ADD  0xfe00707f
+#define MATCH_SUB 0x40000033
+#define MASK_SUB  0xfe00707f
+#define MATCH_SLL 0x1033
+#define MASK_SLL  0xfe00707f
+#define MATCH_SLT 0x2033
+#define MASK_SLT  0xfe00707f
+#define MATCH_SLTU 0x3033
+#define MASK_SLTU  0xfe00707f
+#define MATCH_XOR 0x4033
+#define MASK_XOR  0xfe00707f
+#define MATCH_SRL 0x5033
+#define MASK_SRL  0xfe00707f
+#define MATCH_SRA 0x40005033
+#define MASK_SRA  0xfe00707f
+#define MATCH_OR 0x6033
+#define MASK_OR  0xfe00707f
+#define MATCH_AND 0x7033
+#define MASK_AND  0xfe00707f
+#define MATCH_ADDIW 0x1b
+#define MASK_ADDIW  0x707f
+#define MATCH_SLLIW 0x101b
+#define MASK_SLLIW  0xfe00707f
+#define MATCH_SRLIW 0x501b
+#define MASK_SRLIW  0xfe00707f
+#define MATCH_SRAIW 0x4000501b
+#define MASK_SRAIW  0xfe00707f
+#define MATCH_ADDW 0x3b
+#define MASK_ADDW  0xfe00707f
+#define MATCH_SUBW 0x4000003b
+#define MASK_SUBW  0xfe00707f
+#define MATCH_SLLW 0x103b
+#define MASK_SLLW  0xfe00707f
+#define MATCH_SRLW 0x503b
+#define MASK_SRLW  0xfe00707f
+#define MATCH_SRAW 0x4000503b
+#define MASK_SRAW  0xfe00707f
+#define MATCH_LB 0x3
+#define MASK_LB  0x707f
+#define MATCH_LH 0x1003
+#define MASK_LH  0x707f
+#define MATCH_LW 0x2003
+#define MASK_LW  0x707f
+#define MATCH_LD 0x3003
+#define MASK_LD  0x707f
+#define MATCH_LBU 0x4003
+#define MASK_LBU  0x707f
+#define MATCH_LHU 0x5003
+#define MASK_LHU  0x707f
+#define MATCH_LWU 0x6003
+#define MASK_LWU  0x707f
+#define MATCH_SB 0x23
+#define MASK_SB  0x707f
+#define MATCH_SH 0x1023
+#define MASK_SH  0x707f
+#define MATCH_SW 0x2023
+#define MASK_SW  0x707f
+#define MATCH_SD 0x3023
+#define MASK_SD  0x707f
+#define MATCH_FENCE 0xf
+#define MASK_FENCE  0x707f
+#define MATCH_FENCE_I 0x100f
+#define MASK_FENCE_I  0x707f
+#define MATCH_MUL 0x2000033
+#define MASK_MUL  0xfe00707f
+#define MATCH_MULH 0x2001033
+#define MASK_MULH  0xfe00707f
+#define MATCH_MULHSU 0x2002033
+#define MASK_MULHSU  0xfe00707f
+#define MATCH_MULHU 0x2003033
+#define MASK_MULHU  0xfe00707f
+#define MATCH_DIV 0x2004033
+#define MASK_DIV  0xfe00707f
+#define MATCH_DIVU 0x2005033
+#define MASK_DIVU  0xfe00707f
+#define MATCH_REM 0x2006033
+#define MASK_REM  0xfe00707f
+#define MATCH_REMU 0x2007033
+#define MASK_REMU  0xfe00707f
+#define MATCH_MULW 0x200003b
+#define MASK_MULW  0xfe00707f
+#define MATCH_DIVW 0x200403b
+#define MASK_DIVW  0xfe00707f
+#define MATCH_DIVUW 0x200503b
+#define MASK_DIVUW  0xfe00707f
+#define MATCH_REMW 0x200603b
+#define MASK_REMW  0xfe00707f
+#define MATCH_REMUW 0x200703b
+#define MASK_REMUW  0xfe00707f
+#define MATCH_AMOADD_W 0x202f
+#define MASK_AMOADD_W  0xf800707f
+#define MATCH_AMOXOR_W 0x2000202f
+#define MASK_AMOXOR_W  0xf800707f
+#define MATCH_AMOOR_W 0x4000202f
+#define MASK_AMOOR_W  0xf800707f
+#define MATCH_AMOAND_W 0x6000202f
+#define MASK_AMOAND_W  0xf800707f
+#define MATCH_AMOMIN_W 0x8000202f
+#define MASK_AMOMIN_W  0xf800707f
+#define MATCH_AMOMAX_W 0xa000202f
+#define MASK_AMOMAX_W  0xf800707f
+#define MATCH_AMOMINU_W 0xc000202f
+#define MASK_AMOMINU_W  0xf800707f
+#define MATCH_AMOMAXU_W 0xe000202f
+#define MASK_AMOMAXU_W  0xf800707f
+#define MATCH_AMOSWAP_W 0x800202f
+#define MASK_AMOSWAP_W  0xf800707f
+#define MATCH_LR_W 0x1000202f
+#define MASK_LR_W  0xf9f0707f
+#define MATCH_SC_W 0x1800202f
+#define MASK_SC_W  0xf800707f
+#define MATCH_AMOADD_D 0x302f
+#define MASK_AMOADD_D  0xf800707f
+#define MATCH_AMOXOR_D 0x2000302f
+#define MASK_AMOXOR_D  0xf800707f
+#define MATCH_AMOOR_D 0x4000302f
+#define MASK_AMOOR_D  0xf800707f
+#define MATCH_AMOAND_D 0x6000302f
+#define MASK_AMOAND_D  0xf800707f
+#define MATCH_AMOMIN_D 0x8000302f
+#define MASK_AMOMIN_D  0xf800707f
+#define MATCH_AMOMAX_D 0xa000302f
+#define MASK_AMOMAX_D  0xf800707f
+#define MATCH_AMOMINU_D 0xc000302f
+#define MASK_AMOMINU_D  0xf800707f
+#define MATCH_AMOMAXU_D 0xe000302f
+#define MASK_AMOMAXU_D  0xf800707f
+#define MATCH_AMOSWAP_D 0x800302f
+#define MASK_AMOSWAP_D  0xf800707f
+#define MATCH_LR_D 0x1000302f
+#define MASK_LR_D  0xf9f0707f
+#define MATCH_SC_D 0x1800302f
+#define MASK_SC_D  0xf800707f
+#define MATCH_ECALL 0x73
+#define MASK_ECALL  0xffffffff
+#define MATCH_EBREAK 0x100073
+#define MASK_EBREAK  0xffffffff
+#define MATCH_URET 0x200073
+#define MASK_URET  0xffffffff
+#define MATCH_SRET 0x10200073
+#define MASK_SRET  0xffffffff
+#define MATCH_HRET 0x20200073
+#define MASK_HRET  0xffffffff
+#define MATCH_MRET 0x30200073
+#define MASK_MRET  0xffffffff
+#define MATCH_DRET 0x7b200073
+#define MASK_DRET  0xffffffff
+#define MATCH_SFENCE_VM 0x10400073
+#define MASK_SFENCE_VM  0xfff07fff
+#define MATCH_WFI 0x10500073
+#define MASK_WFI  0xffffffff
+#define MATCH_CSRRW 0x1073
+#define MASK_CSRRW  0x707f
+#define MATCH_CSRRS 0x2073
+#define MASK_CSRRS  0x707f
+#define MATCH_CSRRC 0x3073
+#define MASK_CSRRC  0x707f
+#define MATCH_CSRRWI 0x5073
+#define MASK_CSRRWI  0x707f
+#define MATCH_CSRRSI 0x6073
+#define MASK_CSRRSI  0x707f
+#define MATCH_CSRRCI 0x7073
+#define MASK_CSRRCI  0x707f
+#define MATCH_FADD_S 0x53
+#define MASK_FADD_S  0xfe00007f
+#define MATCH_FSUB_S 0x8000053
+#define MASK_FSUB_S  0xfe00007f
+#define MATCH_FMUL_S 0x10000053
+#define MASK_FMUL_S  0xfe00007f
+#define MATCH_FDIV_S 0x18000053
+#define MASK_FDIV_S  0xfe00007f
+#define MATCH_FSGNJ_S 0x20000053
+#define MASK_FSGNJ_S  0xfe00707f
+#define MATCH_FSGNJN_S 0x20001053
+#define MASK_FSGNJN_S  0xfe00707f
+#define MATCH_FSGNJX_S 0x20002053
+#define MASK_FSGNJX_S  0xfe00707f
+#define MATCH_FMIN_S 0x28000053
+#define MASK_FMIN_S  0xfe00707f
+#define MATCH_FMAX_S 0x28001053
+#define MASK_FMAX_S  0xfe00707f
+#define MATCH_FSQRT_S 0x58000053
+#define MASK_FSQRT_S  0xfff0007f
+#define MATCH_FADD_D 0x2000053
+#define MASK_FADD_D  0xfe00007f
+#define MATCH_FSUB_D 0xa000053
+#define MASK_FSUB_D  0xfe00007f
+#define MATCH_FMUL_D 0x12000053
+#define MASK_FMUL_D  0xfe00007f
+#define MATCH_FDIV_D 0x1a000053
+#define MASK_FDIV_D  0xfe00007f
+#define MATCH_FSGNJ_D 0x22000053
+#define MASK_FSGNJ_D  0xfe00707f
+#define MATCH_FSGNJN_D 0x22001053
+#define MASK_FSGNJN_D  0xfe00707f
+#define MATCH_FSGNJX_D 0x22002053
+#define MASK_FSGNJX_D  0xfe00707f
+#define MATCH_FMIN_D 0x2a000053
+#define MASK_FMIN_D  0xfe00707f
+#define MATCH_FMAX_D 0x2a001053
+#define MASK_FMAX_D  0xfe00707f
+#define MATCH_FCVT_S_D 0x40100053
+#define MASK_FCVT_S_D  0xfff0007f
+#define MATCH_FCVT_D_S 0x42000053
+#define MASK_FCVT_D_S  0xfff0007f
+#define MATCH_FSQRT_D 0x5a000053
+#define MASK_FSQRT_D  0xfff0007f
+#define MATCH_FLE_S 0xa0000053
+#define MASK_FLE_S  0xfe00707f
+#define MATCH_FLT_S 0xa0001053
+#define MASK_FLT_S  0xfe00707f
+#define MATCH_FEQ_S 0xa0002053
+#define MASK_FEQ_S  0xfe00707f
+#define MATCH_FLE_D 0xa2000053
+#define MASK_FLE_D  0xfe00707f
+#define MATCH_FLT_D 0xa2001053
+#define MASK_FLT_D  0xfe00707f
+#define MATCH_FEQ_D 0xa2002053
+#define MASK_FEQ_D  0xfe00707f
+#define MATCH_FCVT_W_S 0xc0000053
+#define MASK_FCVT_W_S  0xfff0007f
+#define MATCH_FCVT_WU_S 0xc0100053
+#define MASK_FCVT_WU_S  0xfff0007f
+#define MATCH_FCVT_L_S 0xc0200053
+#define MASK_FCVT_L_S  0xfff0007f
+#define MATCH_FCVT_LU_S 0xc0300053
+#define MASK_FCVT_LU_S  0xfff0007f
+#define MATCH_FMV_X_S 0xe0000053
+#define MASK_FMV_X_S  0xfff0707f
+#define MATCH_FCLASS_S 0xe0001053
+#define MASK_FCLASS_S  0xfff0707f
+#define MATCH_FCVT_W_D 0xc2000053
+#define MASK_FCVT_W_D  0xfff0007f
+#define MATCH_FCVT_WU_D 0xc2100053
+#define MASK_FCVT_WU_D  0xfff0007f
+#define MATCH_FCVT_L_D 0xc2200053
+#define MASK_FCVT_L_D  0xfff0007f
+#define MATCH_FCVT_LU_D 0xc2300053
+#define MASK_FCVT_LU_D  0xfff0007f
+#define MATCH_FMV_X_D 0xe2000053
+#define MASK_FMV_X_D  0xfff0707f
+#define MATCH_FCLASS_D 0xe2001053
+#define MASK_FCLASS_D  0xfff0707f
+#define MATCH_FCVT_S_W 0xd0000053
+#define MASK_FCVT_S_W  0xfff0007f
+#define MATCH_FCVT_S_WU 0xd0100053
+#define MASK_FCVT_S_WU  0xfff0007f
+#define MATCH_FCVT_S_L 0xd0200053
+#define MASK_FCVT_S_L  0xfff0007f
+#define MATCH_FCVT_S_LU 0xd0300053
+#define MASK_FCVT_S_LU  0xfff0007f
+#define MATCH_FMV_S_X 0xf0000053
+#define MASK_FMV_S_X  0xfff0707f
+#define MATCH_FCVT_D_W 0xd2000053
+#define MASK_FCVT_D_W  0xfff0007f
+#define MATCH_FCVT_D_WU 0xd2100053
+#define MASK_FCVT_D_WU  0xfff0007f
+#define MATCH_FCVT_D_L 0xd2200053
+#define MASK_FCVT_D_L  0xfff0007f
+#define MATCH_FCVT_D_LU 0xd2300053
+#define MASK_FCVT_D_LU  0xfff0007f
+#define MATCH_FMV_D_X 0xf2000053
+#define MASK_FMV_D_X  0xfff0707f
+#define MATCH_FLW 0x2007
+#define MASK_FLW  0x707f
+#define MATCH_FLD 0x3007
+#define MASK_FLD  0x707f
+#define MATCH_FSW 0x2027
+#define MASK_FSW  0x707f
+#define MATCH_FSD 0x3027
+#define MASK_FSD  0x707f
+#define MATCH_FMADD_S 0x43
+#define MASK_FMADD_S  0x600007f
+#define MATCH_FMSUB_S 0x47
+#define MASK_FMSUB_S  0x600007f
+#define MATCH_FNMSUB_S 0x4b
+#define MASK_FNMSUB_S  0x600007f
+#define MATCH_FNMADD_S 0x4f
+#define MASK_FNMADD_S  0x600007f
+#define MATCH_FMADD_D 0x2000043
+#define MASK_FMADD_D  0x600007f
+#define MATCH_FMSUB_D 0x2000047
+#define MASK_FMSUB_D  0x600007f
+#define MATCH_FNMSUB_D 0x200004b
+#define MASK_FNMSUB_D  0x600007f
+#define MATCH_FNMADD_D 0x200004f
+#define MASK_FNMADD_D  0x600007f
+#define MATCH_C_NOP 0x1
+#define MASK_C_NOP  0xffff
+#define MATCH_C_ADDI16SP 0x6101
+#define MASK_C_ADDI16SP  0xef83
+#define MATCH_C_JR 0x8002
+#define MASK_C_JR  0xf07f
+#define MATCH_C_JALR 0x9002
+#define MASK_C_JALR  0xf07f
+#define MATCH_C_EBREAK 0x9002
+#define MASK_C_EBREAK  0xffff
+#define MATCH_C_LD 0x6000
+#define MASK_C_LD  0xe003
+#define MATCH_C_SD 0xe000
+#define MASK_C_SD  0xe003
+#define MATCH_C_ADDIW 0x2001
+#define MASK_C_ADDIW  0xe003
+#define MATCH_C_LDSP 0x6002
+#define MASK_C_LDSP  0xe003
+#define MATCH_C_SDSP 0xe002
+#define MASK_C_SDSP  0xe003
+#define MATCH_C_ADDI4SPN 0x0
+#define MASK_C_ADDI4SPN  0xe003
+#define MATCH_C_FLD 0x2000
+#define MASK_C_FLD  0xe003
+#define MATCH_C_LW 0x4000
+#define MASK_C_LW  0xe003
+#define MATCH_C_FLW 0x6000
+#define MASK_C_FLW  0xe003
+#define MATCH_C_FSD 0xa000
+#define MASK_C_FSD  0xe003
+#define MATCH_C_SW 0xc000
+#define MASK_C_SW  0xe003
+#define MATCH_C_FSW 0xe000
+#define MASK_C_FSW  0xe003
+#define MATCH_C_ADDI 0x1
+#define MASK_C_ADDI  0xe003
+#define MATCH_C_JAL 0x2001
+#define MASK_C_JAL  0xe003
+#define MATCH_C_LI 0x4001
+#define MASK_C_LI  0xe003
+#define MATCH_C_LUI 0x6001
+#define MASK_C_LUI  0xe003
+#define MATCH_C_SRLI 0x8001
+#define MASK_C_SRLI  0xec03
+#define MATCH_C_SRAI 0x8401
+#define MASK_C_SRAI  0xec03
+#define MATCH_C_ANDI 0x8801
+#define MASK_C_ANDI  0xec03
+#define MATCH_C_SUB 0x8c01
+#define MASK_C_SUB  0xfc63
+#define MATCH_C_XOR 0x8c21
+#define MASK_C_XOR  0xfc63
+#define MATCH_C_OR 0x8c41
+#define MASK_C_OR  0xfc63
+#define MATCH_C_AND 0x8c61
+#define MASK_C_AND  0xfc63
+#define MATCH_C_SUBW 0x9c01
+#define MASK_C_SUBW  0xfc63
+#define MATCH_C_ADDW 0x9c21
+#define MASK_C_ADDW  0xfc63
+#define MATCH_C_J 0xa001
+#define MASK_C_J  0xe003
+#define MATCH_C_BEQZ 0xc001
+#define MASK_C_BEQZ  0xe003
+#define MATCH_C_BNEZ 0xe001
+#define MASK_C_BNEZ  0xe003
+#define MATCH_C_SLLI 0x2
+#define MASK_C_SLLI  0xe003
+#define MATCH_C_FLDSP 0x2002
+#define MASK_C_FLDSP  0xe003
+#define MATCH_C_LWSP 0x4002
+#define MASK_C_LWSP  0xe003
+#define MATCH_C_FLWSP 0x6002
+#define MASK_C_FLWSP  0xe003
+#define MATCH_C_MV 0x8002
+#define MASK_C_MV  0xf003
+#define MATCH_C_ADD 0x9002
+#define MASK_C_ADD  0xf003
+#define MATCH_C_FSDSP 0xa002
+#define MASK_C_FSDSP  0xe003
+#define MATCH_C_SWSP 0xc002
+#define MASK_C_SWSP  0xe003
+#define MATCH_C_FSWSP 0xe002
+#define MASK_C_FSWSP  0xe003
+#define MATCH_CUSTOM0 0xb
+#define MASK_CUSTOM0  0x707f
+#define MATCH_CUSTOM0_RS1 0x200b
+#define MASK_CUSTOM0_RS1  0x707f
+#define MATCH_CUSTOM0_RS1_RS2 0x300b
+#define MASK_CUSTOM0_RS1_RS2  0x707f
+#define MATCH_CUSTOM0_RD 0x400b
+#define MASK_CUSTOM0_RD  0x707f
+#define MATCH_CUSTOM0_RD_RS1 0x600b
+#define MASK_CUSTOM0_RD_RS1  0x707f
+#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
+#define MASK_CUSTOM0_RD_RS1_RS2  0x707f
+#define MATCH_CUSTOM1 0x2b
+#define MASK_CUSTOM1  0x707f
+#define MATCH_CUSTOM1_RS1 0x202b
+#define MASK_CUSTOM1_RS1  0x707f
+#define MATCH_CUSTOM1_RS1_RS2 0x302b
+#define MASK_CUSTOM1_RS1_RS2  0x707f
+#define MATCH_CUSTOM1_RD 0x402b
+#define MASK_CUSTOM1_RD  0x707f
+#define MATCH_CUSTOM1_RD_RS1 0x602b
+#define MASK_CUSTOM1_RD_RS1  0x707f
+#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
+#define MASK_CUSTOM1_RD_RS1_RS2  0x707f
+#define MATCH_CUSTOM2 0x5b
+#define MASK_CUSTOM2  0x707f
+#define MATCH_CUSTOM2_RS1 0x205b
+#define MASK_CUSTOM2_RS1  0x707f
+#define MATCH_CUSTOM2_RS1_RS2 0x305b
+#define MASK_CUSTOM2_RS1_RS2  0x707f
+#define MATCH_CUSTOM2_RD 0x405b
+#define MASK_CUSTOM2_RD  0x707f
+#define MATCH_CUSTOM2_RD_RS1 0x605b
+#define MASK_CUSTOM2_RD_RS1  0x707f
+#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
+#define MASK_CUSTOM2_RD_RS1_RS2  0x707f
+#define MATCH_CUSTOM3 0x7b
+#define MASK_CUSTOM3  0x707f
+#define MATCH_CUSTOM3_RS1 0x207b
+#define MASK_CUSTOM3_RS1  0x707f
+#define MATCH_CUSTOM3_RS1_RS2 0x307b
+#define MASK_CUSTOM3_RS1_RS2  0x707f
+#define MATCH_CUSTOM3_RD 0x407b
+#define MASK_CUSTOM3_RD  0x707f
+#define MATCH_CUSTOM3_RD_RS1 0x607b
+#define MASK_CUSTOM3_RD_RS1  0x707f
+#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
+#define MASK_CUSTOM3_RD_RS1_RS2  0x707f
+#define CSR_FFLAGS 0x1
+#define CSR_FRM 0x2
+#define CSR_FCSR 0x3
+#define CSR_CYCLE 0xc00
+#define CSR_TIME 0xc01
+#define CSR_INSTRET 0xc02
+#define CSR_HPMCOUNTER3 0xc03
+#define CSR_HPMCOUNTER4 0xc04
+#define CSR_HPMCOUNTER5 0xc05
+#define CSR_HPMCOUNTER6 0xc06
+#define CSR_HPMCOUNTER7 0xc07
+#define CSR_HPMCOUNTER8 0xc08
+#define CSR_HPMCOUNTER9 0xc09
+#define CSR_HPMCOUNTER10 0xc0a
+#define CSR_HPMCOUNTER11 0xc0b
+#define CSR_HPMCOUNTER12 0xc0c
+#define CSR_HPMCOUNTER13 0xc0d
+#define CSR_HPMCOUNTER14 0xc0e
+#define CSR_HPMCOUNTER15 0xc0f
+#define CSR_HPMCOUNTER16 0xc10
+#define CSR_HPMCOUNTER17 0xc11
+#define CSR_HPMCOUNTER18 0xc12
+#define CSR_HPMCOUNTER19 0xc13
+#define CSR_HPMCOUNTER20 0xc14
+#define CSR_HPMCOUNTER21 0xc15
+#define CSR_HPMCOUNTER22 0xc16
+#define CSR_HPMCOUNTER23 0xc17
+#define CSR_HPMCOUNTER24 0xc18
+#define CSR_HPMCOUNTER25 0xc19
+#define CSR_HPMCOUNTER26 0xc1a
+#define CSR_HPMCOUNTER27 0xc1b
+#define CSR_HPMCOUNTER28 0xc1c
+#define CSR_HPMCOUNTER29 0xc1d
+#define CSR_HPMCOUNTER30 0xc1e
+#define CSR_HPMCOUNTER31 0xc1f
+#define CSR_SSTATUS 0x100
+#define CSR_SIE 0x104
+#define CSR_STVEC 0x105
+#define CSR_SSCRATCH 0x140
+#define CSR_SEPC 0x141
+#define CSR_SCAUSE 0x142
+#define CSR_SBADADDR 0x143
+#define CSR_SIP 0x144
+#define CSR_SPTBR 0x180
+#define CSR_MSTATUS 0x300
+#define CSR_MISA 0x301
+#define CSR_MEDELEG 0x302
+#define CSR_MIDELEG 0x303
+#define CSR_MIE 0x304
+#define CSR_MTVEC 0x305
+#define CSR_MSCRATCH 0x340
+#define CSR_MEPC 0x341
+#define CSR_MCAUSE 0x342
+#define CSR_MBADADDR 0x343
+#define CSR_MIP 0x344
+#define CSR_TSELECT 0x7a0
+#define CSR_TDATA1 0x7a1
+#define CSR_TDATA2 0x7a2
+#define CSR_TDATA3 0x7a3
+#define CSR_DCSR 0x7b0
+#define CSR_DPC 0x7b1
+#define CSR_DSCRATCH 0x7b2
+#define CSR_MCYCLE 0xb00
+#define CSR_MINSTRET 0xb02
+#define CSR_MHPMCOUNTER3 0xb03
+#define CSR_MHPMCOUNTER4 0xb04
+#define CSR_MHPMCOUNTER5 0xb05
+#define CSR_MHPMCOUNTER6 0xb06
+#define CSR_MHPMCOUNTER7 0xb07
+#define CSR_MHPMCOUNTER8 0xb08
+#define CSR_MHPMCOUNTER9 0xb09
+#define CSR_MHPMCOUNTER10 0xb0a
+#define CSR_MHPMCOUNTER11 0xb0b
+#define CSR_MHPMCOUNTER12 0xb0c
+#define CSR_MHPMCOUNTER13 0xb0d
+#define CSR_MHPMCOUNTER14 0xb0e
+#define CSR_MHPMCOUNTER15 0xb0f
+#define CSR_MHPMCOUNTER16 0xb10
+#define CSR_MHPMCOUNTER17 0xb11
+#define CSR_MHPMCOUNTER18 0xb12
+#define CSR_MHPMCOUNTER19 0xb13
+#define CSR_MHPMCOUNTER20 0xb14
+#define CSR_MHPMCOUNTER21 0xb15
+#define CSR_MHPMCOUNTER22 0xb16
+#define CSR_MHPMCOUNTER23 0xb17
+#define CSR_MHPMCOUNTER24 0xb18
+#define CSR_MHPMCOUNTER25 0xb19
+#define CSR_MHPMCOUNTER26 0xb1a
+#define CSR_MHPMCOUNTER27 0xb1b
+#define CSR_MHPMCOUNTER28 0xb1c
+#define CSR_MHPMCOUNTER29 0xb1d
+#define CSR_MHPMCOUNTER30 0xb1e
+#define CSR_MHPMCOUNTER31 0xb1f
+#define CSR_MUCOUNTEREN 0x320
+#define CSR_MSCOUNTEREN 0x321
+#define CSR_MHPMEVENT3 0x323
+#define CSR_MHPMEVENT4 0x324
+#define CSR_MHPMEVENT5 0x325
+#define CSR_MHPMEVENT6 0x326
+#define CSR_MHPMEVENT7 0x327
+#define CSR_MHPMEVENT8 0x328
+#define CSR_MHPMEVENT9 0x329
+#define CSR_MHPMEVENT10 0x32a
+#define CSR_MHPMEVENT11 0x32b
+#define CSR_MHPMEVENT12 0x32c
+#define CSR_MHPMEVENT13 0x32d
+#define CSR_MHPMEVENT14 0x32e
+#define CSR_MHPMEVENT15 0x32f
+#define CSR_MHPMEVENT16 0x330
+#define CSR_MHPMEVENT17 0x331
+#define CSR_MHPMEVENT18 0x332
+#define CSR_MHPMEVENT19 0x333
+#define CSR_MHPMEVENT20 0x334
+#define CSR_MHPMEVENT21 0x335
+#define CSR_MHPMEVENT22 0x336
+#define CSR_MHPMEVENT23 0x337
+#define CSR_MHPMEVENT24 0x338
+#define CSR_MHPMEVENT25 0x339
+#define CSR_MHPMEVENT26 0x33a
+#define CSR_MHPMEVENT27 0x33b
+#define CSR_MHPMEVENT28 0x33c
+#define CSR_MHPMEVENT29 0x33d
+#define CSR_MHPMEVENT30 0x33e
+#define CSR_MHPMEVENT31 0x33f
+#define CSR_MVENDORID 0xf11
+#define CSR_MARCHID 0xf12
+#define CSR_MIMPID 0xf13
+#define CSR_MHARTID 0xf14
+#define CSR_CYCLEH 0xc80
+#define CSR_TIMEH 0xc81
+#define CSR_INSTRETH 0xc82
+#define CSR_HPMCOUNTER3H 0xc83
+#define CSR_HPMCOUNTER4H 0xc84
+#define CSR_HPMCOUNTER5H 0xc85
+#define CSR_HPMCOUNTER6H 0xc86
+#define CSR_HPMCOUNTER7H 0xc87
+#define CSR_HPMCOUNTER8H 0xc88
+#define CSR_HPMCOUNTER9H 0xc89
+#define CSR_HPMCOUNTER10H 0xc8a
+#define CSR_HPMCOUNTER11H 0xc8b
+#define CSR_HPMCOUNTER12H 0xc8c
+#define CSR_HPMCOUNTER13H 0xc8d
+#define CSR_HPMCOUNTER14H 0xc8e
+#define CSR_HPMCOUNTER15H 0xc8f
+#define CSR_HPMCOUNTER16H 0xc90
+#define CSR_HPMCOUNTER17H 0xc91
+#define CSR_HPMCOUNTER18H 0xc92
+#define CSR_HPMCOUNTER19H 0xc93
+#define CSR_HPMCOUNTER20H 0xc94
+#define CSR_HPMCOUNTER21H 0xc95
+#define CSR_HPMCOUNTER22H 0xc96
+#define CSR_HPMCOUNTER23H 0xc97
+#define CSR_HPMCOUNTER24H 0xc98
+#define CSR_HPMCOUNTER25H 0xc99
+#define CSR_HPMCOUNTER26H 0xc9a
+#define CSR_HPMCOUNTER27H 0xc9b
+#define CSR_HPMCOUNTER28H 0xc9c
+#define CSR_HPMCOUNTER29H 0xc9d
+#define CSR_HPMCOUNTER30H 0xc9e
+#define CSR_HPMCOUNTER31H 0xc9f
+#define CSR_MCYCLEH 0xb80
+#define CSR_MINSTRETH 0xb82
+#define CSR_MHPMCOUNTER3H 0xb83
+#define CSR_MHPMCOUNTER4H 0xb84
+#define CSR_MHPMCOUNTER5H 0xb85
+#define CSR_MHPMCOUNTER6H 0xb86
+#define CSR_MHPMCOUNTER7H 0xb87
+#define CSR_MHPMCOUNTER8H 0xb88
+#define CSR_MHPMCOUNTER9H 0xb89
+#define CSR_MHPMCOUNTER10H 0xb8a
+#define CSR_MHPMCOUNTER11H 0xb8b
+#define CSR_MHPMCOUNTER12H 0xb8c
+#define CSR_MHPMCOUNTER13H 0xb8d
+#define CSR_MHPMCOUNTER14H 0xb8e
+#define CSR_MHPMCOUNTER15H 0xb8f
+#define CSR_MHPMCOUNTER16H 0xb90
+#define CSR_MHPMCOUNTER17H 0xb91
+#define CSR_MHPMCOUNTER18H 0xb92
+#define CSR_MHPMCOUNTER19H 0xb93
+#define CSR_MHPMCOUNTER20H 0xb94
+#define CSR_MHPMCOUNTER21H 0xb95
+#define CSR_MHPMCOUNTER22H 0xb96
+#define CSR_MHPMCOUNTER23H 0xb97
+#define CSR_MHPMCOUNTER24H 0xb98
+#define CSR_MHPMCOUNTER25H 0xb99
+#define CSR_MHPMCOUNTER26H 0xb9a
+#define CSR_MHPMCOUNTER27H 0xb9b
+#define CSR_MHPMCOUNTER28H 0xb9c
+#define CSR_MHPMCOUNTER29H 0xb9d
+#define CSR_MHPMCOUNTER30H 0xb9e
+#define CSR_MHPMCOUNTER31H 0xb9f
+#define CAUSE_MISALIGNED_FETCH 0x0
+#define CAUSE_FAULT_FETCH 0x1
+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
+#define CAUSE_BREAKPOINT 0x3
+#define CAUSE_MISALIGNED_LOAD 0x4
+#define CAUSE_FAULT_LOAD 0x5
+#define CAUSE_MISALIGNED_STORE 0x6
+#define CAUSE_FAULT_STORE 0x7
+#define CAUSE_USER_ECALL 0x8
+#define CAUSE_SUPERVISOR_ECALL 0x9
+#define CAUSE_HYPERVISOR_ECALL 0xa
+#define CAUSE_MACHINE_ECALL 0xb
+#endif
+#ifdef DECLARE_INSN
+DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
+DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
+DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
+DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
+DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
+DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
+DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
+DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
+DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
+DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
+DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
+DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
+DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
+DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
+DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
+DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
+DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
+DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
+DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
+DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
+DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
+DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
+DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
+DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
+DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
+DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
+DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
+DECLARE_INSN(or, MATCH_OR, MASK_OR)
+DECLARE_INSN(and, MATCH_AND, MASK_AND)
+DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
+DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
+DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
+DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
+DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
+DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
+DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
+DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
+DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
+DECLARE_INSN(lb, MATCH_LB, MASK_LB)
+DECLARE_INSN(lh, MATCH_LH, MASK_LH)
+DECLARE_INSN(lw, MATCH_LW, MASK_LW)
+DECLARE_INSN(ld, MATCH_LD, MASK_LD)
+DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
+DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
+DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
+DECLARE_INSN(sb, MATCH_SB, MASK_SB)
+DECLARE_INSN(sh, MATCH_SH, MASK_SH)
+DECLARE_INSN(sw, MATCH_SW, MASK_SW)
+DECLARE_INSN(sd, MATCH_SD, MASK_SD)
+DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
+DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
+DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
+DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
+DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
+DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
+DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
+DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
+DECLARE_INSN(rem, MATCH_REM, MASK_REM)
+DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
+DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
+DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
+DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
+DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
+DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
+DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
+DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
+DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
+DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
+DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
+DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
+DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
+DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
+DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
+DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
+DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
+DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
+DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
+DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
+DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
+DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
+DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
+DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
+DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
+DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
+DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
+DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
+DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
+DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
+DECLARE_INSN(uret, MATCH_URET, MASK_URET)
+DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
+DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
+DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
+DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
+DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
+DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
+DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
+DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
+DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
+DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
+DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
+DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
+DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
+DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
+DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
+DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
+DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
+DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
+DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
+DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
+DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
+DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
+DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
+DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
+DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
+DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
+DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
+DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
+DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
+DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
+DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
+DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
+DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
+DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
+DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
+DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
+DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
+DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
+DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
+DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
+DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
+DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
+DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
+DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
+DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
+DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
+DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
+DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
+DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
+DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
+DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
+DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
+DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
+DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
+DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
+DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
+DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
+DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
+DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
+DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
+DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
+DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
+DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
+DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
+DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
+DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
+DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
+DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
+DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
+DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
+DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
+DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
+DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
+DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
+DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
+DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
+DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
+DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
+DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
+DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
+DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
+DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
+DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
+DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
+DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
+DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
+DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
+DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
+DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
+DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
+DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
+DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
+DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
+DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
+DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
+DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
+DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
+DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
+DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
+DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
+DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
+DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
+DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
+DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
+DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
+DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
+DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
+DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
+DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
+DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
+DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
+DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
+DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
+DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
+DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
+DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
+DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
+DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
+DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
+DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
+DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
+DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
+DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
+DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
+DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
+DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
+DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
+DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
+DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
+DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
+DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
+DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
+DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
+DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
+DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
+DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
+DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
+DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
+DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
+#endif
+#ifdef DECLARE_CSR
+DECLARE_CSR(fflags, CSR_FFLAGS)
+DECLARE_CSR(frm, CSR_FRM)
+DECLARE_CSR(fcsr, CSR_FCSR)
+DECLARE_CSR(cycle, CSR_CYCLE)
+DECLARE_CSR(time, CSR_TIME)
+DECLARE_CSR(instret, CSR_INSTRET)
+DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
+DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
+DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
+DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
+DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
+DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
+DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
+DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
+DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
+DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
+DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
+DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
+DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
+DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
+DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
+DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
+DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
+DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
+DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
+DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
+DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
+DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
+DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
+DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
+DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
+DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
+DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
+DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
+DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
+DECLARE_CSR(sstatus, CSR_SSTATUS)
+DECLARE_CSR(sie, CSR_SIE)
+DECLARE_CSR(stvec, CSR_STVEC)
+DECLARE_CSR(sscratch, CSR_SSCRATCH)
+DECLARE_CSR(sepc, CSR_SEPC)
+DECLARE_CSR(scause, CSR_SCAUSE)
+DECLARE_CSR(sbadaddr, CSR_SBADADDR)
+DECLARE_CSR(sip, CSR_SIP)
+DECLARE_CSR(sptbr, CSR_SPTBR)
+DECLARE_CSR(mstatus, CSR_MSTATUS)
+DECLARE_CSR(misa, CSR_MISA)
+DECLARE_CSR(medeleg, CSR_MEDELEG)
+DECLARE_CSR(mideleg, CSR_MIDELEG)
+DECLARE_CSR(mie, CSR_MIE)
+DECLARE_CSR(mtvec, CSR_MTVEC)
+DECLARE_CSR(mscratch, CSR_MSCRATCH)
+DECLARE_CSR(mepc, CSR_MEPC)
+DECLARE_CSR(mcause, CSR_MCAUSE)
+DECLARE_CSR(mbadaddr, CSR_MBADADDR)
+DECLARE_CSR(mip, CSR_MIP)
+DECLARE_CSR(tselect, CSR_TSELECT)
+DECLARE_CSR(tdata1, CSR_TDATA1)
+DECLARE_CSR(tdata2, CSR_TDATA2)
+DECLARE_CSR(tdata3, CSR_TDATA3)
+DECLARE_CSR(dcsr, CSR_DCSR)
+DECLARE_CSR(dpc, CSR_DPC)
+DECLARE_CSR(dscratch, CSR_DSCRATCH)
+DECLARE_CSR(mcycle, CSR_MCYCLE)
+DECLARE_CSR(minstret, CSR_MINSTRET)
+DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
+DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
+DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
+DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
+DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
+DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
+DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
+DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
+DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
+DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
+DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
+DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
+DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
+DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
+DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
+DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
+DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
+DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
+DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
+DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
+DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
+DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
+DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
+DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
+DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
+DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
+DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
+DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
+DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
+DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
+DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
+DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
+DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
+DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
+DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
+DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
+DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
+DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
+DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
+DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
+DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
+DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
+DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
+DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
+DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
+DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
+DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
+DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
+DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
+DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
+DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
+DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
+DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
+DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
+DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
+DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
+DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
+DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
+DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
+DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
+DECLARE_CSR(mvendorid, CSR_MVENDORID)
+DECLARE_CSR(marchid, CSR_MARCHID)
+DECLARE_CSR(mimpid, CSR_MIMPID)
+DECLARE_CSR(mhartid, CSR_MHARTID)
+DECLARE_CSR(cycleh, CSR_CYCLEH)
+DECLARE_CSR(timeh, CSR_TIMEH)
+DECLARE_CSR(instreth, CSR_INSTRETH)
+DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
+DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
+DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
+DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
+DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
+DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
+DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
+DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
+DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
+DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
+DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
+DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
+DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
+DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
+DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
+DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
+DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
+DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
+DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
+DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
+DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
+DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
+DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
+DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
+DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
+DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
+DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
+DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
+DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
+DECLARE_CSR(mcycleh, CSR_MCYCLEH)
+DECLARE_CSR(minstreth, CSR_MINSTRETH)
+DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
+DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
+DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
+DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
+DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
+DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
+DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
+DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
+DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
+DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
+DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
+DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
+DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
+DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
+DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
+DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
+DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
+DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
+DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
+DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
+DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
+DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
+DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
+DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
+DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
+DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
+DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
+DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
+DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
+#endif
+#ifdef DECLARE_CAUSE
+DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
+DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
+DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
+DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
+DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
+DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)
+DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
+DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)
+DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
+DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
+DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
+DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/entry.S b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/entry.S
new file mode 100644
index 0000000..ce44f48
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/entry.S
@@ -0,0 +1,98 @@
+// See LICENSE for license details
+
+#ifndef ENTRY_S
+#define ENTRY_S
+
+#include "encoding.h"
+#include "sifive/bits.h"
+
+  .section      .text.entry	
+  .align 2
+  .weak trap_entry
+  .global trap_entry
+trap_entry:
+  addi sp, sp, -32*REGBYTES
+
+  STORE x1, 1*REGBYTES(sp)
+  STORE x2, 2*REGBYTES(sp)
+  STORE x3, 3*REGBYTES(sp)
+  STORE x4, 4*REGBYTES(sp)
+  STORE x5, 5*REGBYTES(sp)
+  STORE x6, 6*REGBYTES(sp)
+  STORE x7, 7*REGBYTES(sp)
+  STORE x8, 8*REGBYTES(sp)
+  STORE x9, 9*REGBYTES(sp)
+  STORE x10, 10*REGBYTES(sp)
+  STORE x11, 11*REGBYTES(sp)
+  STORE x12, 12*REGBYTES(sp)
+  STORE x13, 13*REGBYTES(sp)
+  STORE x14, 14*REGBYTES(sp)
+  STORE x15, 15*REGBYTES(sp)
+  STORE x16, 16*REGBYTES(sp)
+  STORE x17, 17*REGBYTES(sp)
+  STORE x18, 18*REGBYTES(sp)
+  STORE x19, 19*REGBYTES(sp)
+  STORE x20, 20*REGBYTES(sp)
+  STORE x21, 21*REGBYTES(sp)
+  STORE x22, 22*REGBYTES(sp)
+  STORE x23, 23*REGBYTES(sp)
+  STORE x24, 24*REGBYTES(sp)
+  STORE x25, 25*REGBYTES(sp)
+  STORE x26, 26*REGBYTES(sp)
+  STORE x27, 27*REGBYTES(sp)
+  STORE x28, 28*REGBYTES(sp)
+  STORE x29, 29*REGBYTES(sp)
+  STORE x30, 30*REGBYTES(sp)
+  STORE x31, 31*REGBYTES(sp)
+
+  csrr a0, mcause
+  csrr a1, mepc
+  mv a2, sp
+  call handle_trap
+  csrw mepc, a0
+
+  # Remain in M-mode after mret
+  li t0, MSTATUS_MPP
+  csrs mstatus, t0
+
+  LOAD x1, 1*REGBYTES(sp)
+  LOAD x2, 2*REGBYTES(sp)
+  LOAD x3, 3*REGBYTES(sp)
+  LOAD x4, 4*REGBYTES(sp)
+  LOAD x5, 5*REGBYTES(sp)
+  LOAD x6, 6*REGBYTES(sp)
+  LOAD x7, 7*REGBYTES(sp)
+  LOAD x8, 8*REGBYTES(sp)
+  LOAD x9, 9*REGBYTES(sp)
+  LOAD x10, 10*REGBYTES(sp)
+  LOAD x11, 11*REGBYTES(sp)
+  LOAD x12, 12*REGBYTES(sp)
+  LOAD x13, 13*REGBYTES(sp)
+  LOAD x14, 14*REGBYTES(sp)
+  LOAD x15, 15*REGBYTES(sp)
+  LOAD x16, 16*REGBYTES(sp)
+  LOAD x17, 17*REGBYTES(sp)
+  LOAD x18, 18*REGBYTES(sp)
+  LOAD x19, 19*REGBYTES(sp)
+  LOAD x20, 20*REGBYTES(sp)
+  LOAD x21, 21*REGBYTES(sp)
+  LOAD x22, 22*REGBYTES(sp)
+  LOAD x23, 23*REGBYTES(sp)
+  LOAD x24, 24*REGBYTES(sp)
+  LOAD x25, 25*REGBYTES(sp)
+  LOAD x26, 26*REGBYTES(sp)
+  LOAD x27, 27*REGBYTES(sp)
+  LOAD x28, 28*REGBYTES(sp)
+  LOAD x29, 29*REGBYTES(sp)
+  LOAD x30, 30*REGBYTES(sp)
+  LOAD x31, 31*REGBYTES(sp)
+
+  addi sp, sp, 32*REGBYTES
+  mret
+
+.weak handle_trap
+handle_trap:
+1:
+  j 1b
+	
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/dhrystone.lds b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/dhrystone.lds
new file mode 100644
index 0000000..302bf74
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/dhrystone.lds
@@ -0,0 +1,157 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{
+  flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M
+  ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
+}
+
+PHDRS
+{
+  flash PT_LOAD;
+  ram_init PT_LOAD;
+  ram PT_NULL;
+}
+
+SECTIONS
+{
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
+
+  .init           :
+  {
+    KEEP (*(SORT_NONE(.init)))
+  } >flash AT>flash :flash
+
+  .text           :
+  {
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >flash AT>flash :flash
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >flash AT>flash :flash
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+
+  . = ALIGN(4);
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >flash AT>flash :flash
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >flash AT>flash :flash
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >flash AT>flash :flash
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >flash AT>flash :flash
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >flash AT>flash :flash
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >flash AT>flash :flash
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>flash :ram_init
+
+  .data          :
+  {
+    *(.rdata)
+    *(.rodata .rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+    . = ALIGN(8);
+    PROVIDE( __global_pointer$ = . + 0x800 );
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+    . = ALIGN(8);
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >ram AT>flash :ram_init
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . );
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram :ram
+
+  . = ALIGN(8);
+  PROVIDE( _end = . );
+  PROVIDE( end = . );
+
+  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+  {
+    PROVIDE( _heap_end = . );
+    . = __stack_size;
+    PROVIDE( _sp = . );
+  } >ram AT>ram :ram
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/flash.lds b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/flash.lds
new file mode 100644
index 0000000..0b7e754
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/flash.lds
@@ -0,0 +1,162 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{
+  flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M
+  ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
+}
+
+PHDRS
+{
+  flash PT_LOAD;
+  ram_init PT_LOAD;
+  ram PT_NULL;
+}
+
+SECTIONS
+{
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
+
+  .init           :
+  {
+    KEEP (*(SORT_NONE(.init)))
+  } >flash AT>flash :flash
+
+  .text           :
+  {
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >flash AT>flash :flash
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >flash AT>flash :flash
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+
+  .rodata         :
+  {
+    *(.rdata)
+    *(.rodata .rodata.*)
+    *(.gnu.linkonce.r.*)
+  } >flash AT>flash :flash
+
+  . = ALIGN(4);
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >flash AT>flash :flash
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >flash AT>flash :flash
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >flash AT>flash :flash
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >flash AT>flash :flash
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >flash AT>flash :flash
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >flash AT>flash :flash
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>flash :ram_init
+
+  .data          :
+  {
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+    . = ALIGN(8);
+    PROVIDE( __global_pointer$ = . + 0x800 );
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+    . = ALIGN(8);
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >ram AT>flash :ram_init
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . );
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram :ram
+
+  . = ALIGN(8);
+  PROVIDE( _end = . );
+  PROVIDE( end = . );
+
+  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+  {
+    PROVIDE( _heap_end = . );
+    . = __stack_size;
+    PROVIDE( _sp = . );
+    __freertos_irq_stack_top = .;
+  } >ram AT>ram :ram
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/init.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/init.c
new file mode 100644
index 0000000..a0800e8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/init.c
@@ -0,0 +1,238 @@
+#include 
+#include 
+#include 
+
+#include "platform.h"
+#include "encoding.h"
+
+extern int main(int argc, char** argv);
+extern void trap_entry();
+
+static unsigned long mtime_lo(void)
+{
+  return *(volatile unsigned long *)(CLINT_CTRL_ADDR + CLINT_MTIME);
+}
+
+#ifdef __riscv32
+
+static uint32_t mtime_hi(void)
+{
+  return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4);
+}
+
+uint64_t get_timer_value()
+{
+  while (1) {
+    uint32_t hi = mtime_hi();
+    uint32_t lo = mtime_lo();
+    if (hi == mtime_hi())
+      return ((uint64_t)hi << 32) | lo;
+  }
+}
+
+#else /* __riscv32 */
+
+uint64_t get_timer_value()
+{
+  return mtime_lo();
+}
+
+#endif
+
+unsigned long get_timer_freq()
+{
+  return 32768;
+}
+
+static void use_hfrosc(int div, int trim)
+{
+  // Make sure the HFROSC is running at its default setting
+  PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1));
+  while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ;
+  PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1);
+}
+
+static void use_pll(int refsel, int bypass, int r, int f, int q)
+{
+  // Ensure that we aren't running off the PLL before we mess with it.
+  if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {
+    // Make sure the HFROSC is running at its default setting
+    use_hfrosc(4, 16);
+  }
+
+  // Set PLL Source to be HFXOSC if available.
+  uint32_t config_value = 0;
+
+  config_value |= PLL_REFSEL(refsel);
+
+  if (bypass) {
+    // Bypass
+    config_value |= PLL_BYPASS(1);
+
+    PRCI_REG(PRCI_PLLCFG) = config_value;
+
+    // If we don't have an HFXTAL, this doesn't really matter.
+    // Set our Final output divide to divide-by-1:
+    PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
+  } else {
+    // In case we are executing from QSPI,
+    // (which is quite likely) we need to
+    // set the QSPI clock divider appropriately
+    // before boosting the clock frequency.
+
+    // Div = f_sck/2
+    SPI0_REG(SPI_REG_SCKDIV) = 8;
+
+    // Set DIV Settings for PLL
+    // Both HFROSC and HFXOSC are modeled as ideal
+    // 16MHz sources (assuming dividers are set properly for
+    // HFROSC).
+    // (Legal values of f_REF are 6-48MHz)
+
+    // Set DIVR to divide-by-2 to get 8MHz frequency
+    // (legal values of f_R are 6-12 MHz)
+
+    config_value |= PLL_BYPASS(1);
+    config_value |= PLL_R(r);
+
+    // Set DIVF to get 512Mhz frequncy
+    // There is an implied multiply-by-2, 16Mhz.
+    // So need to write 32-1
+    // (legal values of f_F are 384-768 MHz)
+    config_value |= PLL_F(f);
+
+    // Set DIVQ to divide-by-2 to get 256 MHz frequency
+    // (legal values of f_Q are 50-400Mhz)
+    config_value |= PLL_Q(q);
+
+    // Set our Final output divide to divide-by-1:
+    PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
+
+    PRCI_REG(PRCI_PLLCFG) = config_value;
+
+    // Un-Bypass the PLL.
+    PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
+
+    // Wait for PLL Lock
+    // Note that the Lock signal can be glitchy.
+    // Need to wait 100 us
+    // RTC is running at 32kHz.
+    // So wait 4 ticks of RTC.
+    uint32_t now = mtime_lo();
+    while (mtime_lo() - now < 4) ;
+
+    // Now it is safe to check for PLL Lock
+    while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ;
+  }
+
+  // Switch over to PLL Clock source
+  PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);
+}
+
+static void use_default_clocks()
+{
+  // Turn off the LFROSC
+  AON_REG(AON_LFROSC) &= ~ROSC_EN(1);
+
+  // Use HFROSC
+  use_hfrosc(4, 16);
+}
+
+static unsigned long __attribute__((noinline)) measure_cpu_freq(size_t n)
+{
+  unsigned long start_mtime, delta_mtime;
+  unsigned long mtime_freq = get_timer_freq();
+
+  // Don't start measuruing until we see an mtime tick
+  unsigned long tmp = mtime_lo();
+  do {
+    start_mtime = mtime_lo();
+  } while (start_mtime == tmp);
+
+  unsigned long start_mcycle = read_csr(mcycle);
+
+  do {
+    delta_mtime = mtime_lo() - start_mtime;
+  } while (delta_mtime < n);
+
+  unsigned long delta_mcycle = read_csr(mcycle) - start_mcycle;
+
+  return (delta_mcycle / delta_mtime) * mtime_freq
+         + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime;
+}
+
+unsigned long get_cpu_freq()
+{
+  static uint32_t cpu_freq;
+
+  if (!cpu_freq) {
+    // warm up I$
+    measure_cpu_freq(1);
+    // measure for real
+    cpu_freq = measure_cpu_freq(10);
+  }
+
+  return cpu_freq;
+}
+
+static void uart_init(size_t baud_rate)
+{
+  GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
+  GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
+  UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1;
+  UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
+}
+
+
+
+#ifdef USE_PLIC
+extern void handle_m_ext_interrupt();
+#endif
+
+#ifdef USE_M_TIME
+extern void handle_m_time_interrupt();
+#endif
+
+uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
+{
+  if (0){
+#ifdef USE_PLIC
+    // External Machine-Level interrupt from PLIC
+  } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
+    handle_m_ext_interrupt();
+#endif
+#ifdef USE_M_TIME
+    // External Machine-Level interrupt from PLIC
+  } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
+    handle_m_time_interrupt();
+#endif
+  }
+  else {
+    write(1, "trap\n", 5);
+    _exit(1 + mcause);
+  }
+  return epc;
+}
+
+void _init()
+{
+  
+  #ifndef NO_INIT
+  use_default_clocks();
+  use_pll(0, 0, 1, 31, 1);
+  uart_init(115200);
+
+  printf("core freq at %d Hz\n", (int)get_cpu_freq());
+
+  write_csr(mtvec, &trap_entry);
+  if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
+    write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
+    write_csr(fcsr, 0); // initialize rounding mode, undefined at reset
+  }
+  #endif
+  
+}
+
+void _fini()
+{
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/openocd.cfg b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/openocd.cfg
new file mode 100644
index 0000000..08b7611
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/openocd.cfg
@@ -0,0 +1,34 @@
+adapter_khz     10000
+
+interface ftdi
+ftdi_device_desc "Dual RS232-HS"
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0008 0x001b
+ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
+
+#Reset Stretcher logic on FE310 is ~1 second long
+#This doesn't apply if you use
+# ftdi_set_signal, but still good to document
+#adapter_nsrst_delay 1500
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
+init
+#reset -- This type of reset is not implemented yet
+if {[ info exists pulse_srst]} {
+  ftdi_set_signal nSRST 0
+  ftdi_set_signal nSRST z
+  #Wait for the reset stretcher
+  #It will work without this, but
+  #will incur lots of delays for later commands.
+  sleep 1500
+}	
+halt
+#flash protect 0 64 last off
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/platform.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/platform.h
new file mode 100644
index 0000000..75d31e0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/platform.h
@@ -0,0 +1,133 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_PLATFORM_H
+#define _SIFIVE_PLATFORM_H
+
+// Some things missing from the official encoding.h
+#define MCAUSE_INT         0x80000000
+#define MCAUSE_CAUSE       0x7FFFFFFF
+
+#include "sifive/const.h"
+#include "sifive/devices/aon.h"
+#include "sifive/devices/clint.h"
+#include "sifive/devices/gpio.h"
+#include "sifive/devices/otp.h"
+#include "sifive/devices/plic.h"
+#include "sifive/devices/prci.h"
+#include "sifive/devices/pwm.h"
+#include "sifive/devices/spi.h"
+#include "sifive/devices/uart.h"
+
+/****************************************************************************
+ * Platform definitions
+ *****************************************************************************/
+
+// Memory map
+#define MASKROM_MEM_ADDR _AC(0x00001000,UL)
+#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
+#define OTP_MEM_ADDR _AC(0x00020000,UL)
+#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
+#define PLIC_CTRL_ADDR _AC(0x0C000000,UL)
+#define AON_CTRL_ADDR _AC(0x10000000,UL)
+#define PRCI_CTRL_ADDR _AC(0x10008000,UL)
+#define OTP_CTRL_ADDR _AC(0x10010000,UL)
+#define GPIO_CTRL_ADDR _AC(0x10012000,UL)
+#define UART0_CTRL_ADDR _AC(0x10013000,UL)
+#define SPI0_CTRL_ADDR _AC(0x10014000,UL)
+#define PWM0_CTRL_ADDR _AC(0x10015000,UL)
+#define UART1_CTRL_ADDR _AC(0x10023000,UL)
+#define SPI1_CTRL_ADDR _AC(0x10024000,UL)
+#define PWM1_CTRL_ADDR _AC(0x10025000,UL)
+#define SPI2_CTRL_ADDR _AC(0x10034000,UL)
+#define PWM2_CTRL_ADDR _AC(0x10035000,UL)
+#define SPI0_MEM_ADDR _AC(0x20000000,UL)
+#define MEM_CTRL_ADDR _AC(0x80000000,UL)
+
+// IOF masks
+#define IOF0_SPI1_MASK          _AC(0x000007FC,UL)
+#define SPI11_NUM_SS     (4)
+#define IOF_SPI1_SS0          (2u)
+#define IOF_SPI1_SS1          (8u)
+#define IOF_SPI1_SS2          (9u)
+#define IOF_SPI1_SS3          (10u)
+#define IOF_SPI1_MOSI         (3u)
+#define IOF_SPI1_MISO         (4u)
+#define IOF_SPI1_SCK          (5u)
+#define IOF_SPI1_DQ0          (3u)
+#define IOF_SPI1_DQ1          (4u)
+#define IOF_SPI1_DQ2          (6u)
+#define IOF_SPI1_DQ3          (7u)
+
+#define IOF0_SPI2_MASK          _AC(0xFC000000,UL)
+#define SPI2_NUM_SS       (1)
+#define IOF_SPI2_SS0          (26u)
+#define IOF_SPI2_MOSI         (27u)
+#define IOF_SPI2_MISO         (28u)
+#define IOF_SPI2_SCK          (29u)
+#define IOF_SPI2_DQ0          (27u)
+#define IOF_SPI2_DQ1          (28u)
+#define IOF_SPI2_DQ2          (30u)
+#define IOF_SPI2_DQ3          (31u)
+
+//#define IOF0_I2C_MASK          _AC(0x00003000,UL)
+
+#define IOF0_UART0_MASK         _AC(0x00030000, UL)
+#define IOF_UART0_RX   (16u)
+#define IOF_UART0_TX   (17u)
+
+#define IOF0_UART1_MASK         _AC(0x03000000, UL)
+#define IOF_UART1_RX (24u)
+#define IOF_UART1_TX (25u)
+
+#define IOF1_PWM0_MASK          _AC(0x0000000F, UL)
+#define IOF1_PWM1_MASK          _AC(0x00780000, UL)
+#define IOF1_PWM2_MASK          _AC(0x00003C00, UL)
+
+// Interrupt numbers
+#define INT_RESERVED 0
+#define INT_WDOGCMP 1
+#define INT_RTCCMP 2
+#define INT_UART0_BASE 3
+#define INT_UART1_BASE 4
+#define INT_SPI0_BASE 5
+#define INT_SPI1_BASE 6
+#define INT_SPI2_BASE 7
+#define INT_GPIO_BASE 8
+#define INT_PWM0_BASE 40
+#define INT_PWM1_BASE 44
+#define INT_PWM2_BASE 48
+
+// Helper functions
+#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
+#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
+#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset)
+#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
+#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
+#define OTP_REG(offset)  _REG32(OTP_CTRL_ADDR, offset)
+#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
+#define PRCI_REG(offset) _REG32(PRCI_CTRL_ADDR, offset)
+#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
+#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset)
+#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset)
+#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
+#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset)
+#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset)
+#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
+#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset)
+
+// Misc
+
+#include 
+
+#define NUM_GPIO 32
+
+#define PLIC_NUM_INTERRUPTS 52
+#define PLIC_NUM_PRIORITIES 7
+
+#include "hifive1.h"
+
+unsigned long get_cpu_freq(void);
+unsigned long get_timer_freq(void);
+uint64_t get_timer_value(void);
+
+#endif /* _SIFIVE_PLATFORM_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/hifive1.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/hifive1.h
new file mode 100644
index 0000000..d8fa4c9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/hifive1.h
@@ -0,0 +1,81 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_HIFIVE1_H
+#define _SIFIVE_HIFIVE1_H
+
+#include 
+
+/****************************************************************************
+ * GPIO Connections
+ *****************************************************************************/
+
+// These are the GPIO bit offsets for the RGB LED on HiFive1 Board.
+// These are also mapped to RGB LEDs on the Freedom E300 Arty
+// FPGA
+// Dev Kit.
+
+#define RED_LED_OFFSET   22
+#define GREEN_LED_OFFSET 19
+#define BLUE_LED_OFFSET  21
+
+// These are the GPIO bit offsets for the differen digital pins
+// on the headers for both the HiFive1 Board and the Freedom E300 Arty FPGA Dev Kit.
+#define PIN_0_OFFSET 16
+#define PIN_1_OFFSET 17
+#define PIN_2_OFFSET 18
+#define PIN_3_OFFSET 19
+#define PIN_4_OFFSET 20
+#define PIN_5_OFFSET 21
+#define PIN_6_OFFSET 22
+#define PIN_7_OFFSET 23
+#define PIN_8_OFFSET 0
+#define PIN_9_OFFSET 1
+#define PIN_10_OFFSET 2
+#define PIN_11_OFFSET 3
+#define PIN_12_OFFSET 4
+#define PIN_13_OFFSET 5
+//#define PIN_14_OFFSET 8 //This pin is not connected on either board.
+#define PIN_15_OFFSET 9
+#define PIN_16_OFFSET 10
+#define PIN_17_OFFSET 11
+#define PIN_18_OFFSET 12
+#define PIN_19_OFFSET 13
+
+// These are *PIN* numbers, not
+// GPIO Offset Numbers.
+#define PIN_SPI1_SCK    (13u)
+#define PIN_SPI1_MISO   (12u)
+#define PIN_SPI1_MOSI   (11u)
+#define PIN_SPI1_SS0    (10u)
+#define PIN_SPI1_SS1    (14u) 
+#define PIN_SPI1_SS2    (15u)
+#define PIN_SPI1_SS3    (16u)
+
+#define SS_PIN_TO_CS_ID(x) \
+  ((x==PIN_SPI1_SS0 ? 0 :		 \
+    (x==PIN_SPI1_SS1 ? 1 :		 \
+     (x==PIN_SPI1_SS2 ? 2 :		 \
+      (x==PIN_SPI1_SS3 ? 3 :		 \
+       -1))))) 
+
+
+// These buttons are present only on the Freedom E300 Arty Dev Kit.
+#ifdef HAS_BOARD_BUTTONS
+#define BUTTON_0_OFFSET 15
+#define BUTTON_1_OFFSET 30
+#define BUTTON_2_OFFSET 31
+
+#define INT_DEVICE_BUTTON_0 (INT_GPIO_BASE + BUTTON_0_OFFSET)
+#define INT_DEVICE_BUTTON_1 (INT_GPIO_BASE + BUTTON_1_OFFSET)
+#define INT_DEVICE_BUTTON_2 (INT_GPIO_BASE + BUTTON_2_OFFSET)
+
+#endif
+
+#define HAS_HFXOSC 1
+#define HAS_LFROSC_BYPASS 1
+
+#define RTC_FREQ 32768
+
+void write_hex(int fd, unsigned long int hex);
+
+#endif /* _SIFIVE_HIFIVE1_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/start.S b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/start.S
new file mode 100644
index 0000000..ac24d51
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/env/start.S
@@ -0,0 +1,110 @@
+// See LICENSE for license details.
+
+/* This is defined in sifive/platform.h, but that can't be included from
+ * assembly. */
+#define CLINT_CTRL_ADDR 0x02000000
+
+	.section .init
+	.globl _start
+	.type _start,@function
+
+_start:
+	.cfi_startproc
+	.cfi_undefined ra
+.option push
+.option norelax
+	la gp, __global_pointer$
+.option pop
+	la sp, _sp
+
+#if defined(ENABLE_SMP)
+	smp_pause(t0, t1)
+#endif
+
+	/* Load data section */
+	la a0, _data_lma
+	la a1, _data
+	la a2, _edata
+	bgeu a1, a2, 2f
+1:
+	lw t0, (a0)
+	sw t0, (a1)
+	addi a0, a0, 4
+	addi a1, a1, 4
+	bltu a1, a2, 1b
+2:
+
+	/* Clear bss section */
+	la a0, __bss_start
+	la a1, _end
+	bgeu a0, a1, 2f
+1:
+	sw zero, (a0)
+	addi a0, a0, 4
+	bltu a0, a1, 1b
+2:
+
+	/* Call global constructors */
+	la a0, __libc_fini_array
+	call atexit
+	call __libc_init_array
+
+#ifndef __riscv_float_abi_soft
+	/* Enable FPU */
+	li t0, MSTATUS_FS
+	csrs mstatus, t0
+	csrr t1, mstatus
+	and t1, t1, t0
+	beqz t1, 1f
+	fssr x0
+1:
+#endif
+
+#if defined(ENABLE_SMP)
+	smp_resume(t0, t1)
+
+	csrr a0, mhartid
+	bnez a0, 2f
+#endif
+
+	auipc ra, 0
+	addi sp, sp, -16
+#if __riscv_xlen == 32
+	sw ra, 8(sp)
+#else
+	sd ra, 8(sp)
+#endif
+
+	/* argc = argv = 0 */
+	li a0, 0
+	li a1, 0
+	call main
+	tail exit
+1:
+	j 1b
+
+#if defined(ENABLE_SMP)
+2:
+	la t0, trap_entry
+	csrw mtvec, t0
+
+	csrr a0, mhartid
+	la t1, _sp
+	slli t0, a0, 10
+	sub sp, t1, t0
+
+	auipc ra, 0
+	addi sp, sp, -16
+#if __riscv_xlen == 32
+	sw ra, 8(sp)
+#else
+	sd ra, 8(sp)
+#endif
+
+	call secondary_main
+	tail exit
+
+1:
+	j 1b
+#endif
+	.cfi_endproc
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/bits.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/bits.h
new file mode 100644
index 0000000..54ea8a4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/bits.h
@@ -0,0 +1,36 @@
+// See LICENSE for license details.
+#ifndef _RISCV_BITS_H
+#define _RISCV_BITS_H
+
+#define likely(x) __builtin_expect((x), 1)
+#define unlikely(x) __builtin_expect((x), 0)
+
+#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b))
+#define ROUNDDOWN(a, b) ((a)/(b)*(b))
+
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
+
+#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
+#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
+
+#define STR(x) XSTR(x)
+#define XSTR(x) #x
+
+#if __riscv_xlen == 64
+# define SLL32    sllw
+# define STORE    sd
+# define LOAD     ld
+# define LWU      lwu
+# define LOG_REGBYTES 3
+#else
+# define SLL32    sll
+# define STORE    sw
+# define LOAD     lw
+# define LWU      lw
+# define LOG_REGBYTES 2
+#endif
+#define REGBYTES (1 << LOG_REGBYTES)
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/const.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/const.h
new file mode 100644
index 0000000..fdd6fca
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/const.h
@@ -0,0 +1,18 @@
+// See LICENSE for license details.
+/* Derived from  */
+
+#ifndef _SIFIVE_CONST_H
+#define _SIFIVE_CONST_H
+
+#ifdef __ASSEMBLER__
+#define _AC(X,Y)        X
+#define _AT(T,X)        X
+#else
+#define _AC(X,Y)        (X##Y)
+#define _AT(T,X)        ((T)(X))
+#endif /* !__ASSEMBLER__*/
+
+#define _BITUL(x)       (_AC(1,UL) << (x))
+#define _BITULL(x)      (_AC(1,ULL) << (x))
+
+#endif /* _SIFIVE_CONST_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/aon.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/aon.h
new file mode 100644
index 0000000..7841537
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/aon.h
@@ -0,0 +1,88 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_AON_H
+#define _SIFIVE_AON_H
+
+/* Register offsets */
+
+#define AON_WDOGCFG     0x000
+#define AON_WDOGCOUNT   0x008
+#define AON_WDOGS       0x010
+#define AON_WDOGFEED    0x018
+#define AON_WDOGKEY     0x01C
+#define AON_WDOGCMP     0x020
+
+#define AON_RTCCFG      0x040
+#define AON_RTCLO       0x048
+#define AON_RTCHI       0x04C
+#define AON_RTCS        0x050
+#define AON_RTCCMP      0x060
+
+#define AON_BACKUP0     0x080
+#define AON_BACKUP1     0x084
+#define AON_BACKUP2     0x088
+#define AON_BACKUP3     0x08C
+#define AON_BACKUP4     0x090
+#define AON_BACKUP5     0x094
+#define AON_BACKUP6     0x098
+#define AON_BACKUP7     0x09C
+#define AON_BACKUP8     0x0A0
+#define AON_BACKUP9     0x0A4
+#define AON_BACKUP10    0x0A8
+#define AON_BACKUP11    0x0AC
+#define AON_BACKUP12    0x0B0
+#define AON_BACKUP13    0x0B4
+#define AON_BACKUP14    0x0B8
+#define AON_BACKUP15    0x0BC
+
+#define AON_PMUWAKEUPI0 0x100
+#define AON_PMUWAKEUPI1 0x104
+#define AON_PMUWAKEUPI2 0x108
+#define AON_PMUWAKEUPI3 0x10C
+#define AON_PMUWAKEUPI4 0x110
+#define AON_PMUWAKEUPI5 0x114
+#define AON_PMUWAKEUPI6 0x118
+#define AON_PMUWAKEUPI7 0x11C
+#define AON_PMUSLEEPI0  0x120
+#define AON_PMUSLEEPI1  0x124
+#define AON_PMUSLEEPI2  0x128
+#define AON_PMUSLEEPI3  0x12C
+#define AON_PMUSLEEPI4  0x130
+#define AON_PMUSLEEPI5  0x134
+#define AON_PMUSLEEPI6  0x138
+#define AON_PMUSLEEPI7  0x13C
+#define AON_PMUIE       0x140
+#define AON_PMUCAUSE    0x144
+#define AON_PMUSLEEP    0x148
+#define AON_PMUKEY      0x14C
+
+#define AON_LFROSC      0x070
+/* Constants */
+
+#define AON_WDOGKEY_VALUE  0x51F15E
+#define AON_WDOGFEED_VALUE 0xD09F00D
+
+#define AON_WDOGCFG_SCALE       0x0000000F
+#define AON_WDOGCFG_RSTEN       0x00000100
+#define AON_WDOGCFG_ZEROCMP     0x00000200
+#define AON_WDOGCFG_ENALWAYS    0x00001000
+#define AON_WDOGCFG_ENCOREAWAKE 0x00002000
+#define AON_WDOGCFG_CMPIP       0x10000000
+
+#define AON_RTCCFG_SCALE     0x0000000F
+#define AON_RTCCFG_ENALWAYS  0x00001000
+#define AON_RTCCFG_CMPIP     0x10000000
+
+#define AON_WAKEUPCAUSE_RESET   0x00
+#define AON_WAKEUPCAUSE_RTC     0x01
+#define AON_WAKEUPCAUSE_DWAKEUP 0x02
+#define AON_WAKEUPCAUSE_AWAKEUP 0x03
+
+#define AON_RESETCAUSE_POWERON  0x0000
+#define AON_RESETCAUSE_EXTERNAL 0x0100
+#define AON_RESETCAUSE_WATCHDOG 0x0200
+
+#define AON_PMUCAUSE_WAKEUPCAUSE 0x00FF
+#define AON_PMUCAUSE_RESETCAUSE  0xFF00
+
+#endif /* _SIFIVE_AON_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/clint.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/clint.h
new file mode 100644
index 0000000..057ba02
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/clint.h
@@ -0,0 +1,14 @@
+// See LICENSE for license details
+
+#ifndef _SIFIVE_CLINT_H
+#define _SIFIVE_CLINT_H
+
+
+#define CLINT_MSIP 0x0000
+#define CLINT_MSIP_size   0x4
+#define CLINT_MTIMECMP 0x4000
+#define CLINT_MTIMECMP_size 0x8
+#define CLINT_MTIME 0xBFF8
+#define CLINT_MTIME_size 0x8
+
+#endif /* _SIFIVE_CLINT_H */ 
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/gpio.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/gpio.h
new file mode 100644
index 0000000..69239de
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/gpio.h
@@ -0,0 +1,24 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_GPIO_H
+#define _SIFIVE_GPIO_H
+
+#define GPIO_INPUT_VAL  (0x00)
+#define GPIO_INPUT_EN   (0x04)
+#define GPIO_OUTPUT_EN  (0x08)
+#define GPIO_OUTPUT_VAL (0x0C)
+#define GPIO_PULLUP_EN  (0x10)
+#define GPIO_DRIVE      (0x14)
+#define GPIO_RISE_IE    (0x18)
+#define GPIO_RISE_IP    (0x1C)
+#define GPIO_FALL_IE    (0x20)
+#define GPIO_FALL_IP    (0x24)
+#define GPIO_HIGH_IE    (0x28)
+#define GPIO_HIGH_IP    (0x2C)
+#define GPIO_LOW_IE     (0x30)
+#define GPIO_LOW_IP     (0x34)
+#define GPIO_IOF_EN     (0x38)
+#define GPIO_IOF_SEL    (0x3C)
+#define GPIO_OUTPUT_XOR    (0x40)
+
+#endif /* _SIFIVE_GPIO_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/otp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/otp.h
new file mode 100644
index 0000000..2482518
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/otp.h
@@ -0,0 +1,23 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_OTP_H
+#define _SIFIVE_OTP_H
+
+/* Register offsets */
+
+#define OTP_LOCK         0x00
+#define OTP_CK           0x04
+#define OTP_OE           0x08
+#define OTP_SEL          0x0C
+#define OTP_WE           0x10
+#define OTP_MR           0x14
+#define OTP_MRR          0x18
+#define OTP_MPP          0x1C
+#define OTP_VRREN        0x20
+#define OTP_VPPEN        0x24
+#define OTP_A            0x28
+#define OTP_D            0x2C
+#define OTP_Q            0x30
+#define OTP_READ_TIMINGS 0x34
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/plic.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/plic.h
new file mode 100644
index 0000000..494e04e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/plic.h
@@ -0,0 +1,31 @@
+// See LICENSE for license details.
+
+#ifndef PLIC_H
+#define PLIC_H
+
+#include 
+
+// 32 bits per source
+#define PLIC_PRIORITY_OFFSET            _AC(0x0000,UL)
+#define PLIC_PRIORITY_SHIFT_PER_SOURCE  2
+// 1 bit per source (1 address)
+#define PLIC_PENDING_OFFSET             _AC(0x1000,UL)
+#define PLIC_PENDING_SHIFT_PER_SOURCE   0
+
+//0x80 per target
+#define PLIC_ENABLE_OFFSET              _AC(0x2000,UL)
+#define PLIC_ENABLE_SHIFT_PER_TARGET    7
+
+
+#define PLIC_THRESHOLD_OFFSET           _AC(0x200000,UL)
+#define PLIC_CLAIM_OFFSET               _AC(0x200004,UL)
+#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12
+#define PLIC_CLAIM_SHIFT_PER_TARGET     12
+
+#define PLIC_MAX_SOURCE                 1023
+#define PLIC_SOURCE_MASK                0x3FF
+
+#define PLIC_MAX_TARGET                 15871
+#define PLIC_TARGET_MASK                0x3FFF
+
+#endif /* PLIC_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/prci.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/prci.h
new file mode 100644
index 0000000..582863c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/prci.h
@@ -0,0 +1,56 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_PRCI_H
+#define _SIFIVE_PRCI_H
+
+/* Register offsets */
+
+#define PRCI_HFROSCCFG   (0x0000)
+#define PRCI_HFXOSCCFG   (0x0004)
+#define PRCI_PLLCFG      (0x0008)
+#define PRCI_PLLDIV      (0x000C)
+#define PRCI_PROCMONCFG  (0x00F0)
+
+/* Fields */
+#define ROSC_DIV(x)    (((x) & 0x2F) << 0 ) 
+#define ROSC_TRIM(x)   (((x) & 0x1F) << 16)
+#define ROSC_EN(x)     (((x) & 0x1 ) << 30) 
+#define ROSC_RDY(x)    (((x) & 0x1 ) << 31)
+
+#define XOSC_EN(x)     (((x) & 0x1) << 30)
+#define XOSC_RDY(x)    (((x) & 0x1) << 31)
+
+#define PLL_R(x)       (((x) & 0x7)  << 0)
+// single reserved bit for F LSB.
+#define PLL_F(x)       (((x) & 0x3F) << 4)
+#define PLL_Q(x)       (((x) & 0x3)  << 10)
+#define PLL_SEL(x)     (((x) & 0x1)  << 16)
+#define PLL_REFSEL(x)  (((x) & 0x1)  << 17)
+#define PLL_BYPASS(x)  (((x) & 0x1)  << 18)
+#define PLL_LOCK(x)    (((x) & 0x1)  << 31)
+
+#define PLL_R_default 0x1
+#define PLL_F_default 0x1F
+#define PLL_Q_default 0x3
+
+#define PLL_REFSEL_HFROSC 0x0
+#define PLL_REFSEL_HFXOSC 0x1
+
+#define PLL_SEL_HFROSC 0x0
+#define PLL_SEL_PLL    0x1
+
+#define PLL_FINAL_DIV(x)      (((x) & 0x3F) << 0)
+#define PLL_FINAL_DIV_BY_1(x) (((x) & 0x1 ) << 8)
+
+#define PROCMON_DIV(x)   (((x) & 0x1F) << 0)
+#define PROCMON_TRIM(x)  (((x) & 0x1F) << 8)
+#define PROCMON_EN(x)    (((x) & 0x1)  << 16)
+#define PROCMON_SEL(x)   (((x) & 0x3)  << 24)
+#define PROCMON_NT_EN(x) (((x) & 0x1)  << 28)
+
+#define PROCMON_SEL_HFCLK     0
+#define PROCMON_SEL_HFXOSCIN  1
+#define PROCMON_SEL_PLLOUTDIV 2
+#define PROCMON_SEL_PROCMON   3
+
+#endif // _SIFIVE_PRCI_H
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/pwm.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/pwm.h
new file mode 100644
index 0000000..3c5f704
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/pwm.h
@@ -0,0 +1,37 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_PWM_H
+#define _SIFIVE_PWM_H
+
+/* Register offsets */
+
+#define PWM_CFG   0x00
+#define PWM_COUNT 0x08
+#define PWM_S     0x10
+#define PWM_CMP0  0x20
+#define PWM_CMP1  0x24
+#define PWM_CMP2  0x28
+#define PWM_CMP3  0x2C
+
+/* Constants */
+
+#define PWM_CFG_SCALE       0x0000000F
+#define PWM_CFG_STICKY      0x00000100
+#define PWM_CFG_ZEROCMP     0x00000200
+#define PWM_CFG_DEGLITCH    0x00000400
+#define PWM_CFG_ENALWAYS    0x00001000
+#define PWM_CFG_ONESHOT     0x00002000
+#define PWM_CFG_CMP0CENTER  0x00010000
+#define PWM_CFG_CMP1CENTER  0x00020000
+#define PWM_CFG_CMP2CENTER  0x00040000
+#define PWM_CFG_CMP3CENTER  0x00080000
+#define PWM_CFG_CMP0GANG    0x01000000
+#define PWM_CFG_CMP1GANG    0x02000000
+#define PWM_CFG_CMP2GANG    0x04000000
+#define PWM_CFG_CMP3GANG    0x08000000
+#define PWM_CFG_CMP0IP      0x10000000
+#define PWM_CFG_CMP1IP      0x20000000
+#define PWM_CFG_CMP2IP      0x40000000
+#define PWM_CFG_CMP3IP      0x80000000
+
+#endif /* _SIFIVE_PWM_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/spi.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/spi.h
new file mode 100644
index 0000000..e3c1d35
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/spi.h
@@ -0,0 +1,80 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_SPI_H
+#define _SIFIVE_SPI_H
+
+/* Register offsets */
+
+#define SPI_REG_SCKDIV          0x00
+#define SPI_REG_SCKMODE         0x04
+#define SPI_REG_CSID            0x10
+#define SPI_REG_CSDEF           0x14
+#define SPI_REG_CSMODE          0x18
+
+#define SPI_REG_DCSSCK          0x28
+#define SPI_REG_DSCKCS          0x2a
+#define SPI_REG_DINTERCS        0x2c
+#define SPI_REG_DINTERXFR       0x2e
+
+#define SPI_REG_FMT             0x40
+#define SPI_REG_TXFIFO          0x48
+#define SPI_REG_RXFIFO          0x4c
+#define SPI_REG_TXCTRL          0x50
+#define SPI_REG_RXCTRL          0x54
+
+#define SPI_REG_FCTRL           0x60
+#define SPI_REG_FFMT            0x64
+
+#define SPI_REG_IE              0x70
+#define SPI_REG_IP              0x74
+
+/* Fields */
+
+#define SPI_SCK_PHA             0x1
+#define SPI_SCK_POL             0x2
+
+#define SPI_FMT_PROTO(x)        ((x) & 0x3)
+#define SPI_FMT_ENDIAN(x)       (((x) & 0x1) << 2)
+#define SPI_FMT_DIR(x)          (((x) & 0x1) << 3)
+#define SPI_FMT_LEN(x)          (((x) & 0xf) << 16)
+
+/* TXCTRL register */
+#define SPI_TXWM(x)             ((x) & 0xffff)
+/* RXCTRL register */
+#define SPI_RXWM(x)             ((x) & 0xffff)
+
+#define SPI_IP_TXWM             0x1
+#define SPI_IP_RXWM             0x2
+
+#define SPI_FCTRL_EN            0x1
+
+#define SPI_INSN_CMD_EN         0x1
+#define SPI_INSN_ADDR_LEN(x)    (((x) & 0x7) << 1)
+#define SPI_INSN_PAD_CNT(x)     (((x) & 0xf) << 4)
+#define SPI_INSN_CMD_PROTO(x)   (((x) & 0x3) << 8)
+#define SPI_INSN_ADDR_PROTO(x)  (((x) & 0x3) << 10)
+#define SPI_INSN_DATA_PROTO(x)  (((x) & 0x3) << 12)
+#define SPI_INSN_CMD_CODE(x)    (((x) & 0xff) << 16)
+#define SPI_INSN_PAD_CODE(x)    (((x) & 0xff) << 24)
+
+#define SPI_TXFIFO_FULL  (1 << 31)   
+#define SPI_RXFIFO_EMPTY (1 << 31)   
+
+/* Values */
+
+#define SPI_CSMODE_AUTO         0
+#define SPI_CSMODE_HOLD         2
+#define SPI_CSMODE_OFF          3
+
+#define SPI_DIR_RX              0
+#define SPI_DIR_TX              1
+
+#define SPI_PROTO_S             0
+#define SPI_PROTO_D             1
+#define SPI_PROTO_Q             2
+
+#define SPI_ENDIAN_MSB          0
+#define SPI_ENDIAN_LSB          1
+
+
+#endif /* _SIFIVE_SPI_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/uart.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/uart.h
new file mode 100644
index 0000000..ce9fd01
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/uart.h
@@ -0,0 +1,27 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_UART_H
+#define _SIFIVE_UART_H
+
+/* Register offsets */
+#define UART_REG_TXFIFO         0x00
+#define UART_REG_RXFIFO         0x04
+#define UART_REG_TXCTRL         0x08
+#define UART_REG_RXCTRL         0x0c
+#define UART_REG_IE             0x10
+#define UART_REG_IP             0x14
+#define UART_REG_DIV            0x18
+
+/* TXCTRL register */
+#define UART_TXEN               0x1
+#define UART_TXWM(x)            (((x) & 0xffff) << 16)
+
+/* RXCTRL register */
+#define UART_RXEN               0x1
+#define UART_RXWM(x)            (((x) & 0xffff) << 16)
+
+/* IP register */
+#define UART_IP_TXWM            0x1
+#define UART_IP_RXWM            0x2
+
+#endif /* _SIFIVE_UART_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/sections.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/sections.h
new file mode 100644
index 0000000..bcbf9f8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/sections.h
@@ -0,0 +1,17 @@
+// See LICENSE for license details.
+#ifndef _SECTIONS_H
+#define _SECTIONS_H
+
+extern unsigned char _rom[];
+extern unsigned char _rom_end[];
+
+extern unsigned char _ram[];
+extern unsigned char _ram_end[];
+
+extern unsigned char _ftext[];
+extern unsigned char _etext[];
+extern unsigned char _fbss[];
+extern unsigned char _ebss[];
+extern unsigned char _end[];
+
+#endif /* _SECTIONS_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/smp.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/smp.h
new file mode 100644
index 0000000..8e7d485
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/include/sifive/smp.h
@@ -0,0 +1,65 @@
+#ifndef SIFIVE_SMP
+#define SIFIVE_SMP
+
+// The maximum number of HARTs this code supports
+#ifndef MAX_HARTS
+#define MAX_HARTS 32
+#endif
+#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4)
+
+// The hart that non-SMP tests should run on
+#ifndef NONSMP_HART
+#define NONSMP_HART 0
+#endif
+
+/* If your test cannot handle multiple-threads, use this: 
+ *   smp_disable(reg1)
+ */
+#define smp_disable(reg1, reg2)			 \
+  csrr reg1, mhartid				;\
+  li   reg2, NONSMP_HART			;\
+  beq  reg1, reg2, hart0_entry			;\
+42:						;\
+  wfi    					;\
+  j 42b						;\
+hart0_entry:
+
+/* If your test needs to temporarily block multiple-threads, do this:
+ *    smp_pause(reg1, reg2)
+ *    ... single-threaded work ...
+ *    smp_resume(reg1, reg2)
+ *    ... multi-threaded work ...
+ */
+
+#define smp_pause(reg1, reg2)	 \
+  li reg2, 0x8			;\
+  csrw mie, reg2		;\
+  csrr reg2, mhartid		;\
+  bnez reg2, 42f
+
+#define smp_resume(reg1, reg2)	 \
+  li reg1, CLINT_CTRL_ADDR	;\
+41:				;\
+  li reg2, 1			;\
+  sw reg2, 0(reg1)		;\
+  addi reg1, reg1, 4		;\
+  li reg2, CLINT_END_HART_IPI	;\
+  blt reg1, reg2, 41b		;\
+42:				;\
+  wfi    			;\
+  csrr reg2, mip		;\
+  andi reg2, reg2, 0x8		;\
+  beqz reg2, 42b		;\
+  li reg1, CLINT_CTRL_ADDR	;\
+  csrr reg2, mhartid		;\
+  slli reg2, reg2, 2		;\
+  add reg2, reg2, reg1		;\
+  sw zero, 0(reg2)		;\
+41:				;\
+  lw reg2, 0(reg1)		;\
+  bnez reg2, 41b		;\
+  addi reg1, reg1, 4		;\
+  li reg2, CLINT_END_HART_IPI	;\
+  blt reg1, reg2, 41b
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/misc/write_hex.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/misc/write_hex.c
new file mode 100644
index 0000000..4d25241
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/misc/write_hex.c
@@ -0,0 +1,19 @@
+/* See LICENSE of license details. */
+
+#include 
+#include 
+#include "platform.h"
+
+void write_hex(int fd, unsigned long int hex)
+{
+  uint8_t ii;
+  uint8_t jj;
+  char towrite;
+  write(fd , "0x", 2);
+  for (ii = sizeof(unsigned long int) * 2 ; ii > 0; ii--) {
+    jj = ii - 1;
+    uint8_t digit = ((hex & (0xF << (jj*4))) >> (jj*4));
+    towrite = digit < 0xA ? ('0' + digit) : ('A' +  (digit - 0xA));
+    write(fd, &towrite, 1);
+  }
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/stdlib/malloc.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/stdlib/malloc.c
new file mode 100644
index 0000000..871766f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/stdlib/malloc.c
@@ -0,0 +1,17 @@
+/* See LICENSE for license details. */
+
+/* These functions are intended for embedded RV32 systems and are
+   obviously incorrect in general. */
+
+void* __wrap_malloc(unsigned long sz)
+{
+  extern void* sbrk(long);
+  void* res = sbrk(sz);
+  if ((long)res == -1)
+    return 0;
+  return res;
+}
+
+void __wrap_free(void* ptr)
+{
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/_exit.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/_exit.c
new file mode 100644
index 0000000..89b0b3d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/_exit.c
@@ -0,0 +1,17 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "platform.h"
+#include "weak_under_alias.h"
+
+void __wrap_exit(int code)
+{
+  const char message[] = "\nProgam has exited with code:";
+
+  write(STDERR_FILENO, message, sizeof(message) - 1);
+  write_hex(STDERR_FILENO, code);
+  write(STDERR_FILENO, "\n", 1);
+
+  for (;;);
+}
+weak_under_alias(exit);
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/close.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/close.c
new file mode 100644
index 0000000..fe2dd77
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/close.c
@@ -0,0 +1,11 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_close(int fd)
+{
+  return _stub(EBADF);
+}
+weak_under_alias(close);
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/execve.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/execve.c
new file mode 100644
index 0000000..508ae21
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/execve.c
@@ -0,0 +1,11 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_execve(const char* name, char* const argv[], char* const env[])
+{
+  return _stub(ENOMEM);
+}
+weak_under_alias(execve);
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/fork.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/fork.c
new file mode 100644
index 0000000..3f05a67
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/fork.c
@@ -0,0 +1,9 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "stub.h"
+
+int fork(void)
+{
+  return _stub(EAGAIN);
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/fstat.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/fstat.c
new file mode 100644
index 0000000..8de6b8c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/fstat.c
@@ -0,0 +1,18 @@
+/* See LICENSE of license details. */
+
+#include 
+#include 
+#include 
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_fstat(int fd, struct stat* st)
+{
+  if (isatty(fd)) {
+    st->st_mode = S_IFCHR;
+    return 0;
+  }
+
+  return _stub(EBADF);
+}
+weak_under_alias(fstat);
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/getpid.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/getpid.c
new file mode 100644
index 0000000..8b2a7c7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/getpid.c
@@ -0,0 +1,8 @@
+/* See LICENSE of license details. */
+#include "weak_under_alias.h"
+
+int __wrap_getpid(void)
+{
+  return 1;
+}
+weak_under_alias(getpid);
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/isatty.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/isatty.c
new file mode 100644
index 0000000..d65f932
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/isatty.c
@@ -0,0 +1,13 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "weak_under_alias.h"
+
+int __wrap_isatty(int fd)
+{
+  if (fd == STDOUT_FILENO || fd == STDERR_FILENO)
+    return 1;
+
+  return 0;
+}
+weak_under_alias(isatty);
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/kill.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/kill.c
new file mode 100644
index 0000000..fe1fa62
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/kill.c
@@ -0,0 +1,11 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_kill(int pid, int sig)
+{
+  return _stub(EINVAL);
+}
+weak_under_alias(kill);
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/link.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/link.c
new file mode 100644
index 0000000..eeac5b9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/link.c
@@ -0,0 +1,11 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_link(const char *old_name, const char *new_name)
+{
+  return _stub(EMLINK);
+}
+weak_under_alias(link);
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/lseek.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/lseek.c
new file mode 100644
index 0000000..81b2b78
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/lseek.c
@@ -0,0 +1,16 @@
+/* See LICENSE of license details. */
+
+#include 
+#include 
+#include 
+#include "stub.h"
+#include "weak_under_alias.h"
+
+off_t __wrap_lseek(int fd, off_t ptr, int dir)
+{
+  if (isatty(fd))
+    return 0;
+
+  return _stub(EBADF);
+}
+weak_under_alias(lseek);
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/open.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/open.c
new file mode 100644
index 0000000..8b74f2a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/open.c
@@ -0,0 +1,11 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_open(const char* name, int flags, int mode)
+{
+  return _stub(ENOENT);
+}
+weak_under_alias(open);
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/openat.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/openat.c
new file mode 100644
index 0000000..687e0e2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/openat.c
@@ -0,0 +1,11 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_openat(int dirfd, const char* name, int flags, int mode)
+{
+  return _stub(ENOENT);
+}
+weak_under_alias(openat);
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/puts.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/puts.c
new file mode 100644
index 0000000..45c05c0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/puts.c
@@ -0,0 +1,28 @@
+/* See LICENSE of license details. */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "platform.h"
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_puts(const char *s)
+{
+  while (*s != '\0') {
+    while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
+    UART0_REG(UART_REG_TXFIFO) = *s;
+
+    if (*s == '\n') {
+      while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
+      UART0_REG(UART_REG_TXFIFO) = '\r';
+    }
+
+    ++s;
+  }
+
+  return 0;
+}
+weak_under_alias(puts);
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/read.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/read.c
new file mode 100644
index 0000000..08d0ab5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/read.c
@@ -0,0 +1,32 @@
+/* See LICENSE of license details. */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "platform.h"
+#include "stub.h"
+#include "weak_under_alias.h"
+
+ssize_t __wrap_read(int fd, void* ptr, size_t len)
+{
+  uint8_t * current = (uint8_t *)ptr;
+  volatile uint32_t * uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO);
+  volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_CTRL_ADDR + UART_REG_RXCTRL + 2);
+
+  ssize_t result = 0;
+
+  if (isatty(fd)) {
+    for (current = (uint8_t *)ptr;
+        (current < ((uint8_t *)ptr) + len) && (*uart_rx_cnt > 0);
+        current ++) {
+      *current = *uart_rx;
+      result++;
+    }
+    return result;
+  }
+
+  return _stub(EBADF);
+}
+weak_under_alias(read);
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/sbrk.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/sbrk.c
new file mode 100644
index 0000000..451bc27
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/sbrk.c
@@ -0,0 +1,18 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "weak_under_alias.h"
+
+void *__wrap_sbrk(ptrdiff_t incr)
+{
+  extern char _end[];
+  extern char _heap_end[];
+  static char *curbrk = _end;
+
+  if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
+    return NULL - 1;
+
+  curbrk += incr;
+  return curbrk - incr;
+}
+weak_under_alias(sbrk);
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/stat.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/stat.c
new file mode 100644
index 0000000..b950590
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/stat.c
@@ -0,0 +1,12 @@
+/* See LICENSE of license details. */
+
+#include 
+#include 
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_stat(const char* file, struct stat* st)
+{
+  return _stub(EACCES);
+}
+weak_under_alias(stat);
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/stub.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/stub.h
new file mode 100644
index 0000000..cebddda
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/stub.h
@@ -0,0 +1,10 @@
+/* See LICENSE of license details. */
+#ifndef _SIFIVE_SYS_STUB_H
+#define _SIFIVE_SYS_STUB_H
+
+static inline int _stub(int err)
+{
+  return -1;
+}
+
+#endif /* _SIFIVE_SYS_STUB_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/times.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/times.c
new file mode 100644
index 0000000..26e1737
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/times.c
@@ -0,0 +1,12 @@
+/* See LICENSE of license details. */
+
+#include 
+#include 
+#include "stub.h"
+#include "weak_under_alias.h"
+
+clock_t __wrap_times(struct tms* buf)
+{
+  return _stub(EACCES);
+}
+weak_under_alias(times);
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/unlink.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/unlink.c
new file mode 100644
index 0000000..8e23464
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/unlink.c
@@ -0,0 +1,11 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_unlink(const char* name)
+{
+  return _stub(ENOENT);
+}
+weak_under_alias(unlink);
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/wait.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/wait.c
new file mode 100644
index 0000000..bb566e6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/wait.c
@@ -0,0 +1,9 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "stub.h"
+
+int wait(int* status)
+{
+  return _stub(ECHILD);
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/weak_under_alias.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/weak_under_alias.h
new file mode 100644
index 0000000..402a223
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/weak_under_alias.h
@@ -0,0 +1,7 @@
+#ifndef _BSP_LIBWRAP_WEAK_UNDER_ALIAS_H
+#define _BSP_LIBWRAP_WEAK_UNDER_ALIAS_H
+
+#define weak_under_alias(name) \
+  extern __typeof (__wrap_##name) __wrap__##name __attribute__ ((weak, alias ("__wrap_"#name)))
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/write.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/write.c
new file mode 100644
index 0000000..c6ec5b4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/freedom-e-sdk/libwrap/sys/write.c
@@ -0,0 +1,31 @@
+/* See LICENSE of license details. */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "platform.h"
+#include "stub.h"
+#include "weak_under_alias.h"
+
+ssize_t __wrap_write(int fd, const void* ptr, size_t len)
+{
+  const uint8_t * current = (const uint8_t *)ptr;
+
+  if (isatty(fd)) {
+    for (size_t jj = 0; jj < len; jj++) {
+      while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
+      UART0_REG(UART_REG_TXFIFO) = current[jj];
+
+      if (current[jj] == '\n') {
+        while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
+        UART0_REG(UART_REG_TXFIFO) = '\r';
+      }
+    }
+    return len;
+  }
+
+  return _stub(EBADF);
+}
+weak_under_alias(write);
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/full_demo/RegTest.S b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/full_demo/RegTest.S
new file mode 100644
index 0000000..0a5e544
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/full_demo/RegTest.S
@@ -0,0 +1,262 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	.extern ulRegTest1LoopCounter
+	.extern ulRegTest2LoopCounter
+
+	.global vRegTest1Implementation
+	.global vRegTest2Implementation
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The register check tasks are described in the comments at the top of
+ * main_full.c.
+ */
+
+vRegTest1Implementation:
+
+	/* Fill the core registers with known values. */
+	li x5, 0x5
+	li x6, 0x6
+	li x7, 0x7
+	li x8, 0x8
+	li x9, 0x9
+	li x10, 0xa
+	li x11, 0xb
+	li x12, 0xc
+	li x13, 0xd
+	li x14, 0xe
+	li x15, 0xf
+	li x16, 0x10
+	li x17, 0x11
+	li x18, 0x12
+	li x19, 0x13
+	li x20, 0x14
+	li x21, 0x15
+	li x22, 0x16
+	li x23, 0x17
+	li x24, 0x18
+	li x25, 0x19
+	li x26, 0x1a
+	li x27, 0x1b
+	li x28, 0x1c
+	li x29, 0x1d
+	li x30, 0x1e
+
+reg1_loop:
+
+	/* Check each register still contains the expected known value.
+	vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation
+	uses x5 as the temporary. */
+	li x31, 0x5
+	bne x31, x5, reg1_error_loop
+	li x31, 0x6
+	bne x31, x6, reg1_error_loop
+	li x31, 0x7
+	bne x31, x7, reg1_error_loop
+	li x31, 0x8
+	bne x31, x8, reg1_error_loop
+	li x31, 0x9
+	bne x31, x9, reg1_error_loop
+	li x31, 0xa
+	bne x31, x10, reg1_error_loop
+	li x31, 0xb
+	bne x31, x11, reg1_error_loop
+	li x31, 0xc
+	bne x31, x12, reg1_error_loop
+	li x31, 0xd
+	bne x31, x13, reg1_error_loop
+	li x31, 0xe
+	bne x31, x14, reg1_error_loop
+	li x31, 0xf
+	bne x31, x15, reg1_error_loop
+	li x31, 0x10
+	bne x31, x16, reg1_error_loop
+	li x31, 0x11
+	bne x31, x17, reg1_error_loop
+	li x31, 0x12
+	bne x31, x18, reg1_error_loop
+	li x31, 0x13
+	bne x31, x19, reg1_error_loop
+	li x31, 0x14
+	bne x31, x20, reg1_error_loop
+	li x31, 0x15
+	bne x31, x21, reg1_error_loop
+	li x31, 0x16
+	bne x31, x22, reg1_error_loop
+	li x31, 0x17
+	bne x31, x23, reg1_error_loop
+	li x31, 0x18
+	bne x31, x24, reg1_error_loop
+	li x31, 0x19
+	bne x31, x25, reg1_error_loop
+	li x31, 0x1a
+	bne x31, x26, reg1_error_loop
+	li x31, 0x1b
+	bne x31, x27, reg1_error_loop
+	li x31, 0x1c
+	bne x31, x28, reg1_error_loop
+	li x31, 0x1d
+	bne x31, x29, reg1_error_loop
+	li x31, 0x1e
+	bne x31, x30, reg1_error_loop
+
+	/* Everything passed, increment the loop counter. */
+	lw x31, ulRegTest1LoopCounterConst
+	lw x30, 0(x31)
+	addi x30, x30, 1
+	sw x30, 0(x31)
+
+	/* Restore clobbered register reading for next loop. */
+	li x30, 0x1e
+
+	/* Yield to increase code coverage. */
+	ecall
+
+	/* Start again. */
+	jal reg1_loop
+
+reg1_error_loop:
+	/* Jump here if a register contains an uxpected value.  This stops the loop
+	counter being incremented so the check task knows an error was found. */
+//	ebreak
+	jal reg1_error_loop
+
+ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter
+
+/*-----------------------------------------------------------*/
+
+vRegTest2Implementation:
+
+	/* Fill the core registers with known values. */
+	li x6, 0x61
+	li x7, 0x71
+	li x8, 0x81
+	li x9, 0x91
+	li x10, 0xa1
+	li x11, 0xb1
+	li x12, 0xc1
+	li x13, 0xd1
+	li x14, 0xe1
+	li x15, 0xf1
+	li x16, 0x20
+	li x17, 0x21
+	li x18, 0x22
+	li x19, 0x23
+	li x20, 0x24
+	li x21, 0x25
+	li x22, 0x26
+	li x23, 0x27
+	li x24, 0x28
+	li x25, 0x29
+	li x26, 0x2a
+	li x27, 0x2b
+	li x28, 0x2c
+	li x29, 0x2d
+	li x30, 0x2e
+	li x31, 0x2f
+
+Reg2_loop:
+
+	/* Check each register still contains the expected known value.
+	vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation
+	uses x31 as the temporary. */
+	li x5, 0x61
+	bne x5, x6, reg2_error_loop
+	li x5, 0x71
+	bne x5, x7, reg2_error_loop
+	li x5, 0x81
+	bne x5, x8, reg2_error_loop
+	li x5, 0x91
+	bne x5, x9, reg2_error_loop
+	li x5, 0xa1
+	bne x5, x10, reg2_error_loop
+	li x5, 0xb1
+	bne x5, x11, reg2_error_loop
+	li x5, 0xc1
+	bne x5, x12, reg2_error_loop
+	li x5, 0xd1
+	bne x5, x13, reg2_error_loop
+	li x5, 0xe1
+	bne x5, x14, reg2_error_loop
+	li x5, 0xf1
+	bne x5, x15, reg2_error_loop
+	li x5, 0x20
+	bne x5, x16, reg2_error_loop
+	li x5, 0x21
+	bne x5, x17, reg2_error_loop
+	li x5, 0x22
+	bne x5, x18, reg2_error_loop
+	li x5, 0x23
+	bne x5, x19, reg2_error_loop
+	li x5, 0x24
+	bne x5, x20, reg2_error_loop
+	li x5, 0x25
+	bne x5, x21, reg2_error_loop
+	li x5, 0x26
+	bne x5, x22, reg2_error_loop
+	li x5, 0x27
+	bne x5, x23, reg2_error_loop
+	li x5, 0x28
+	bne x5, x24, reg2_error_loop
+	li x5, 0x29
+	bne x5, x25, reg2_error_loop
+	li x5, 0x2a
+	bne x5, x26, reg2_error_loop
+	li x5, 0x2b
+	bne x5, x27, reg2_error_loop
+	li x5, 0x2c
+	bne x5, x28, reg2_error_loop
+	li x5, 0x2d
+	bne x5, x29, reg2_error_loop
+	li x5, 0x2e
+	bne x5, x30, reg2_error_loop
+	li x5, 0x2f
+	bne x5, x31, reg2_error_loop
+
+	/* Everything passed, increment the loop counter. */
+	lw x5, ulRegTest2LoopCounterConst
+	lw x6, 0(x5)
+	addi x6, x6, 1
+	sw x6, 0(x5)
+
+	/* Restore clobbered register reading for next loop. */
+	li x6, 0x61
+
+	/* Start again. */
+	jal Reg2_loop
+
+reg2_error_loop:
+	/* Jump here if a register contains an uxpected value.  This stops the loop
+	counter being incremented so the check task knows an error was found. */
+//	ebreak
+	jal reg2_error_loop
+
+ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/full_demo/main_full.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/full_demo/main_full.c
new file mode 100644
index 0000000..bd79bcb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/full_demo/main_full.c
@@ -0,0 +1,320 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/******************************************************************************
+ * NOTE 1:  This project provides two demo applications.  A simple blinky style
+ * project, and a more comprehensive test and demo application.  The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
+ * between the two.  See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
+ * in main.c.  This file implements the comprehensive test and demo version.
+ *
+ * NOTE 2:  This file only contains the source code that is specific to the
+ * full demo.  Generic functions, such FreeRTOS hook functions, and functions
+ * required to configure the hardware, are defined in main.c.
+ *
+ ******************************************************************************
+ *
+ * main_full() creates all the demo application tasks and software timers, then
+ * starts the scheduler.  The web documentation provides more details of the
+ * standard demo application tasks, which provide no particular functionality,
+ * but do provide a good example of how to use the FreeRTOS API.
+ *
+ * In addition to the standard demo tasks, the following tasks and tests are
+ * defined and/or created within this file:
+ *
+ * "Reg test" tasks - These fill both the core registers with known values, then
+ * check that each register maintains its expected value for the lifetime of the
+ * task.  Each task uses a different set of values.  The reg test tasks execute
+ * with a very low priority, so get preempted very frequently.  A register
+ * containing an unexpected value is indicative of an error in the context
+ * switching mechanism.
+ *
+ * "Check" task - The check executes every five seconds.  It checks that all
+ * the standard demo tasks, and the register check tasks, are not only still
+ * executing, but are executing without reporting any errors.  If the check task
+ * discovers that a task has either stalled, or reported an error, then it
+ * prints an error message to the UART, otherwise it prints "Pass" followed
+ * by an additional period (".") after each successful loop of its implementing
+ * function.
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "semphr.h"
+
+/* Standard demo application includes. */
+#include "dynamic.h"
+#include "blocktim.h"
+#include "GenQTest.h"
+#include "recmutex.h"
+#include "TimerDemo.h"
+#include "EventGroupsDemo.h"
+#include "TaskNotify.h"
+
+/* SiFive includes. */
+#include "platform.h"
+#include "encoding.h"
+#include "unistd.h"
+
+/* Priorities for the demo application tasks. */
+#define mainCHECK_TASK_PRIORITY				( configMAX_PRIORITIES - 1 )
+
+/* The period of the check task, in ms, converted to ticks using the
+pdMS_TO_TICKS() macro. */
+#define mainNO_ERROR_CHECK_TASK_PERIOD		pdMS_TO_TICKS( 5000UL )
+
+/* Parameters that are passed into the register check tasks solely for the
+purpose of ensuring parameters are passed into tasks correctl5. */
+#define mainREG_TEST_TASK_1_PARAMETER		( ( void * ) 0x12345678 )
+#define mainREG_TEST_TASK_2_PARAMETER		( ( void * ) 0x87654321 )
+
+/* The base period used by the timer test tasks. */
+#define mainTIMER_TEST_PERIOD				( 50 )
+
+/* The size of the stack allocated to the check task (as described in the
+comments at the top of this file. */
+#define mainCHECK_TASK_STACK_SIZE_WORDS 85
+
+/* Size of the stacks to allocated for the register check tasks. */
+#define mainREG_TEST_STACK_SIZE_WORDS 50
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by main() to run the full demo (as opposed to the blinky demo) when
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
+ */
+void main_full( void );
+
+/*
+ * The check task, as described at the top of this file.
+ */
+static void prvCheckTask( void *pvParameters );
+
+/*
+ * Register check tasks as described at the top of this file.  The nature of
+ * these files necessitates that they are written in an assembly file, but the
+ * entry points are kept in the C file for the convenience of checking the task
+ * parameter.
+ */
+static void prvRegTestTaskEntry1( void *pvParameters );
+extern void vRegTest1Implementation( void );
+static void prvRegTestTaskEntry2( void *pvParameters );
+extern void vRegTest2Implementation( void );
+
+/*
+ * Tick hook used by the full demo, which includes code that interacts with
+ * some of the tests.
+ */
+void vFullDemoTickHook( void );
+
+/*-----------------------------------------------------------*/
+
+/* The following two variables are used to communicate the status of the
+register check tasks to the check task.  If the variables keep incrementing,
+then the register check tasks have not discovered any errors.  If a variable
+stops incrementing, then an error has been found. */
+volatile uint32_t ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
+
+/*-----------------------------------------------------------*/
+
+void main_full( void )
+{
+	/* Create the register check tasks, as described at the top of this	file.
+	Use xTaskCreateStatic() to create a task using only statically allocated
+	memory. */
+	xTaskCreate( prvRegTestTaskEntry1, 			/* The function that implements the task. */
+				 "Reg1", 						/* The name of the task. */
+				 mainREG_TEST_STACK_SIZE_WORDS, /* Size of stack to allocate for the task - in words not bytes!. */
+				 mainREG_TEST_TASK_1_PARAMETER, /* Parameter passed into the task. */
+				 tskIDLE_PRIORITY, 				/* Priority of the task. */
+				 NULL );						/* Can be used to pass out a handle to the created task. */
+	xTaskCreate( prvRegTestTaskEntry2, "Reg2", mainREG_TEST_STACK_SIZE_WORDS, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL );
+
+	/* Start all the other standard demo/test tasks.  They have no particular
+	functionality, but do demonstrate how to use the FreeRTOS API and test the
+	kernel port. */
+	vStartDynamicPriorityTasks();
+	vCreateBlockTimeTasks();
+	vStartGenericQueueTasks( tskIDLE_PRIORITY );
+	vStartRecursiveMutexTasks();
+	vStartTimerDemoTask( mainTIMER_TEST_PERIOD );
+	vStartEventGroupTasks();
+	vStartTaskNotifyTask();
+
+	/* Create the task that performs the 'check' functionality,	as described at
+	the top of this file. */
+	xTaskCreate( prvCheckTask, "Check", mainCHECK_TASK_STACK_SIZE_WORDS, NULL, mainCHECK_TASK_PRIORITY, NULL );
+
+	/* Start the scheduler. */
+	vTaskStartScheduler();
+
+	/* If all is well, the scheduler will now be running, and the following
+	line will never be reached.  If the following line does execute, then
+	there was insufficient FreeRTOS heap memory available for the Idle and/or
+	timer tasks to be created.  See the memory management section on the
+	FreeRTOS web site for more details on the FreeRTOS heap
+	http://www.freertos.org/a00111.html. */
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTask( void *pvParameters )
+{
+const TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;
+TickType_t xLastExecutionTime;
+static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
+const char * const pcPassMessage = "Pass";
+const char * pcStatusMessage = ".";
+
+	/* Just to stop compiler warnings. */
+	( void ) pvParameters;
+
+	write( STDOUT_FILENO, pcPassMessage, strlen( pcPassMessage ) );
+
+	/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
+	works correctly. */
+	xLastExecutionTime = xTaskGetTickCount();
+
+	/* Cycle for ever, delaying then checking all the other tasks are still
+	operating without error.  The onboard LED is toggled on each iteration.
+	If an error is detected then the delay period is decreased from
+	mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD.  This has the
+	effect of increasing the rate at which the onboard LED toggles, and in so
+	doing gives visual feedback of the system status. */
+	for( ;; )
+	{
+		/* Delay until it is time to execute again. */
+		vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );
+
+		/* Check all the demo tasks (other than the flash tasks) to ensure
+		that they are all still running, and that none have detected an error. */
+		if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
+		{
+			pcStatusMessage = "ERROR: Dynamic priority demo/tests.\r\n";
+		}
+
+		if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
+		{
+			pcStatusMessage = "ERROR: Block time demo/tests.\r\n";
+		}
+
+		if ( xAreGenericQueueTasksStillRunning() != pdTRUE )
+		{
+			pcStatusMessage = "ERROR: Generic queue demo/tests.\r\n";
+		}
+
+		if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
+		{
+			pcStatusMessage = "ERROR: Recursive mutex demo/tests.\r\n";
+		}
+
+		if( xAreTimerDemoTasksStillRunning( ( TickType_t ) xDelayPeriod ) != pdPASS )
+		{
+			pcStatusMessage = "ERROR: Timer demo/tests.\r\n";
+		}
+
+		if( xAreEventGroupTasksStillRunning() != pdPASS )
+		{
+			pcStatusMessage = "ERROR: Event group demo/tests.\r\n";
+		}
+
+		if( xAreTaskNotificationTasksStillRunning() != pdPASS )
+		{
+			pcStatusMessage = "ERROR: Task notification demo/tests.\r\n";
+		}
+
+		/* Check that the register test 1 task is still running. */
+		if( ulLastRegTest1Value == ulRegTest1LoopCounter )
+		{
+			pcStatusMessage = "ERROR: Register test 1.\r\n";
+		}
+		ulLastRegTest1Value = ulRegTest1LoopCounter;
+
+		/* Check that the register test 2 task is still running. */
+		if( ulLastRegTest2Value == ulRegTest2LoopCounter )
+		{
+			pcStatusMessage = "ERROR: Register test 2.\r\n";
+		}
+		ulLastRegTest2Value = ulRegTest2LoopCounter;
+
+		/* Write the status message to the UART. */
+		write( STDOUT_FILENO, pcStatusMessage, strlen( pcStatusMessage ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTestTaskEntry1( void *pvParameters )
+{
+	/* Although the regtest task is written in assembler, its entry point is
+	written in C for convenience of checking the task parameter is being passed
+	in correctly. */
+	if( pvParameters == mainREG_TEST_TASK_1_PARAMETER )
+	{
+		/* Start the part of the test that is written in assembler. */
+		vRegTest1Implementation();
+	}
+
+	/* The following line will only execute if the task parameter is found to
+	be incorrect.  The check task will detect that the regtest loop counter is
+	not being incremented and flag an error. */
+	vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTestTaskEntry2( void *pvParameters )
+{
+	/* Although the regtest task is written in assembler, its entry point is
+	written in C for convenience of checking the task parameter is being passed
+	in correctly. */
+	if( pvParameters == mainREG_TEST_TASK_2_PARAMETER )
+	{
+		/* Start the part of the test that is written in assembler. */
+		vRegTest2Implementation();
+	}
+
+	/* The following line will only execute if the task parameter is found to
+	be incorrect.  The check task will detect that the regtest loop counter is
+	not being incremented and flag an error. */
+	vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+void vFullDemoTickHook( void )
+{
+	/* Called from vApplicationTickHook() when the project is configured to
+	build the full demo. */
+	vTimerPeriodicISRTests();
+	vPeriodicEventGroupsProcessing();
+	xNotifyTaskFromISR();
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/main.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/main.c
new file mode 100644
index 0000000..5c82039
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/main.c
@@ -0,0 +1,178 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* FreeRTOS kernel includes. */
+#include 
+#include 
+
+/******************************************************************************
+ * This project provides two demo applications.  A simple blinky style project,
+ * and a more comprehensive test and demo application.  The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to
+ * select between the two.  The simply blinky demo is implemented and described
+ * in main_blinky.c.  The more comprehensive test and demo application is
+ * implemented and described in main_full.c.
+ *
+ * This file implements the code that is not demo specific, including the
+ * hardware setup and standard FreeRTOS hook functions.
+ *
+ * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON
+ * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO
+ * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!
+ *
+ *
+ * NOTE 1:
+ *
+ * This project has only been tested in the QEMU emulation of the HiFive board
+ * from SiFive.
+ *
+ * Start QEMU using the following command line:
+ *
+ * [your_path_1]\qemu-system-riscv32 -kernel [your_path_2]\FreeRTOS\Demo\RISC-V-Qemu-sifive_e-FreedomStudio\Debug\RTOSDemo.elf -S -s -machine sifive_e
+ *
+ * Where [your_path_1] must be replaced with the correct path to your QEMU
+ * installation and the elf file generated by this project respectively.
+ *
+ *
+ * NOTE 2:
+ *
+ * Start GDB using the following command line (this can be entered in the
+ * Eclipse Debug Launch Configuration dialogue):
+ *
+ * riscv64-unknown-elf-gdb.exe -iex "set mem inaccessible-by-default off" -iex "set arch riscv:rv32" -iex "set riscv use_compressed_breakpoint off"
+ *
+ *
+ * Note 3:
+ *
+ * Status information is sent to the QEMU serial console.
+ */
+
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
+or 0 to run the more comprehensive test and demo application. */
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY	1
+
+/*
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
+ */
+#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1
+	extern void main_blinky( void );
+#else
+	extern void main_full( void );
+#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */
+
+/* Prototypes for the standard FreeRTOS callback/hook functions implemented
+within this file.  See https://www.freertos.org/a00016.html */
+void vApplicationMallocFailedHook( void );
+void vApplicationIdleHook( void );
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );
+void vApplicationTickHook( void );
+
+/*-----------------------------------------------------------*/
+
+int main( void )
+{
+	/* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top
+	of this file. */
+	#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )
+	{
+		main_blinky();
+	}
+	#else
+	{
+		main_full();
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationMallocFailedHook( void )
+{
+	/* vApplicationMallocFailedHook() will only be called if
+	configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h.  It is a hook
+	function that will get called if a call to pvPortMalloc() fails.
+	pvPortMalloc() is called internally by the kernel whenever a task, queue,
+	timer or semaphore is created.  It is also called by various parts of the
+	demo application.  If heap_1.c or heap_2.c are used, then the size of the
+	heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
+	FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
+	to query the size of free heap space that remains (although it does not
+	provide information on how the remaining heap might be fragmented). */
+	taskDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+	/* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
+	to 1 in FreeRTOSConfig.h.  It will be called on each iteration of the idle
+	task.  It is essential that code added to this hook function never attempts
+	to block in any way (for example, call xQueueReceive() with a block time
+	specified, or call vTaskDelay()).  If the application makes use of the
+	vTaskDelete() API function (as this demo application does) then it is also
+	important that vApplicationIdleHook() is permitted to return to its calling
+	function, because it is the responsibility of the idle task to clean up
+	memory allocated by the kernel to any task that has since been deleted. */
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
+{
+	( void ) pcTaskName;
+	( void ) pxTask;
+
+	/* Run time stack overflow checking is performed if
+	configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2.  This hook
+	function is called if a stack overflow is detected. */
+	taskDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationTickHook( void )
+{
+	/* The tests in the full demo expect some interaction with interrupts. */
+	#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 )
+	{
+		extern void vFullDemoTickHook( void );
+		vFullDemoTickHook();
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+void vAssertCalled( void )
+{
+volatile uint32_t ulSetTo1ToExitFunction = 0;
+
+	taskDISABLE_INTERRUPTS();
+	while( ulSetTo1ToExitFunction != 1 )
+	{
+		__asm volatile( "NOP" );
+	}
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/sifive-freedom-e300-hifive1.cfg b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/sifive-freedom-e300-hifive1.cfg
new file mode 100644
index 0000000..d0af4dd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/sifive-freedom-e300-hifive1.cfg
@@ -0,0 +1,34 @@
+adapter_khz     10000
+
+interface ftdi
+ftdi_device_desc "Dual RS232-HS"
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0008 0x001b
+ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
+
+#Reset Stretcher logic on FE310 is ~1 second long
+#This doesn't apply if you use
+# ftdi_set_signal, but still good to document
+#adapter_nsrst_delay 1500
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
+init
+#reset -- This type of reset is not implemented yet
+if {[ info exists pulse_srst]} {
+  ftdi_set_signal nSRST 0
+  ftdi_set_signal nSRST z
+  #Wait for the reset stretcher
+  #It will work without this, but
+  #will incur lots of delays for later commands.
+  sleep 1500
+}	
+halt
+flash protect 0 64 last off
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/pin_mux.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/pin_mux.c
new file mode 100644
index 0000000..9c3335d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/pin_mux.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v3.0
+processor: RV32M1
+package_id: RV32M1
+mcu_data: ksdk2_0
+processor_version: 0.0.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_port.h"
+#include "pin_mux.h"
+
+/*FUNCTION**********************************************************************
+ * 
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ * 
+ *END**************************************************************************/
+void BOARD_InitBootPins(void) {
+    BOARD_InitPins();
+}
+
+#define PIN7_IDX                         7u   /*!< Pin number for pin 7 in a port */
+#define PIN8_IDX                         8u   /*!< Pin number for pin 8 in a port */
+#define PIN24_IDX                       24u   /*!< Pin number for pin 24 in a port */
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm4, enableClock: 'true'}
+- pin_list:
+  - {pin_num: D6, peripheral: GPIOA, signal: 'GPIO, 24', pin_signal: PTA24/LPSPI2_PCS0/LPSPI1_SCK/LPI2C2_SCL/FB_OE_b/TPM2_CH0}
+  - {pin_num: N2, peripheral: LPUART0, signal: RX, pin_signal: LPCMP0_IN0/PTC7/LLWU_P15/LPSPI0_PCS3/LPUART0_RX/LPI2C1_HREQ/TPM0_CH0/LPTMR1_ALT1}
+  - {pin_num: P3, peripheral: LPUART0, signal: TX, pin_signal: LPCMP0_IN1/PTC8/LPSPI0_SCK/LPUART0_TX/LPI2C0_HREQ/TPM0_CH1}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ *END**************************************************************************/
+void BOARD_InitPins(void) {
+  CLOCK_EnableClock(kCLOCK_PortA);                           /* Clock Gate Control: 0x01u */
+  CLOCK_EnableClock(kCLOCK_PortC);                           /* Clock Gate Control: 0x01u */
+
+  PORT_SetPinMux(PORTA, PIN24_IDX, kPORT_MuxAsGpio);         /* PORTA24 (pin D6) is configured as PTA24 */
+  PORT_SetPinMux(PORTC, PIN7_IDX, kPORT_MuxAlt3);            /* PORTC7 (pin N2) is configured as LPUART0_RX */
+  PORT_SetPinMux(PORTC, PIN8_IDX, kPORT_MuxAlt3);            /* PORTC8 (pin P3) is configured as LPUART0_TX */
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/pin_mux.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/pin_mux.h
new file mode 100644
index 0000000..eb4b69e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/pin_mux.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Direction type  */
+typedef enum _pin_mux_direction
+{
+  kPIN_MUX_DirectionInput = 0U,         /* Input direction */
+  kPIN_MUX_DirectionOutput = 1U,        /* Output direction */
+  kPIN_MUX_DirectionInputOrOutput = 2U  /* Input or output direction */
+} pin_mux_direction_t;
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_ri5cy.cfg b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_ri5cy.cfg
new file mode 100644
index 0000000..05ce1bd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_ri5cy.cfg
@@ -0,0 +1,150 @@
+set _WORKAREASIZE 0x2000
+
+adapter_khz 1000
+
+interface jlink
+transport select jtag
+
+set _WORKAREASIZE 0x1000
+
+set _CHIPNAME rv32m1
+
+reset_config srst_only
+
+# OpenCores Mohor JTAG TAP ID
+set _CPUTAPID  0x249511C3
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME rv32m1 -endian little -chain-position $_TARGETNAME
+
+# Select the TAP core we are using
+tap_select mohor
+
+# Select the debug unit core we are using. This debug unit as an option.
+
+set ADBG_USE_HISPEED		1
+
+# If ADBG_USE_HISPEED is set (options bit 1), status bits will be skipped
+# on burst reads and writes to improve download speeds.
+# This option must match the RTL configured option.
+
+du_select adv [expr $ADBG_USE_HISPEED]
+
+# Select core 0
+core_select 0
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+$_TARGETNAME configure -event gdb-detach {
+    resume
+}
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_CHIPNAME.flash0 rv32m1 0 0 0 0 $_TARGETNAME # For core 0
+flash bank $_CHIPNAME.flash1 rv32m1 0x01000000 0 0 0 $_TARGETNAME # For core 1
+
+proc ri5cy_boot { } {
+
+    # Erase all blok unsecure
+    mwb 0x40023000 0x70
+    mww 0x40023004 0x49000000
+    mwb 0x40023000 0x80
+
+    sleep 1000
+
+    mwb 0x40023000 0x70
+    mww 0x40023008 0xFFFF03FF
+    mww 0x40023004 0x43840000
+    mwb 0x40023000 0x80
+
+    sleep 2
+}
+
+proc cm4_boot { } {
+
+    # Erase all blok unsecure
+    mwb 0x40023000 0x70
+    mww 0x40023004 0x49000000
+    mwb 0x40023000 0x80
+
+    sleep 1000
+
+    mwb 0x40023000 0x70
+    mww 0x40023008 0xFFFFFFFF
+    mww 0x40023004 0x43840000
+    mwb 0x40023000 0x80
+
+    sleep 2
+}
+
+proc zero_boot { } {
+
+    # Erase all blok unsecure
+    mwb 0x40023000 0x70
+    mww 0x40023004 0x49000000
+    mwb 0x40023000 0x80
+
+    sleep 1000
+
+    mwb 0x40023000 0x70
+    mww 0x40023008 0xFFFF03BF
+    mww 0x40023004 0x43840000
+    mwb 0x40023000 0x80
+
+    sleep 2
+}
+
+proc cm0_boot { } {
+
+    # Erase all blok unsecure
+    mwb 0x40023000 0x70
+    mww 0x40023004 0x49000000
+    mwb 0x40023000 0x80
+
+    sleep 1000
+
+    mwb 0x40023000 0x70
+    mww 0x40023008 0xFFFFFFBF
+    mww 0x40023004 0x43840000
+    mwb 0x40023000 0x80
+
+    sleep 2
+}
+
+# All cores are available, CM4 & RI5CY boot first
+proc core0_boot { } {
+
+    # Erase all blok unsecure
+    mwb 0x40023000 0x70
+    mww 0x40023004 0x49000000
+    mwb 0x40023000 0x80
+
+    sleep 1000
+
+    mwb 0x40023000 0x70
+    mww 0x40023008 0xFFFFA3FF
+    mww 0x40023004 0x43840000
+    mwb 0x40023000 0x80
+
+    sleep 2
+}
+
+# All cores are available, CM0 & ZERO_RISCY boot first
+proc core1_boot { } {
+
+    # Erase all blok unsecure
+    mwb 0x40023000 0x70
+    mww 0x40023004 0x49000000
+    mwb 0x40023000 0x80
+
+    sleep 1000
+
+    mwb 0x40023000 0x70
+    mww 0x40023008 0xFFFFA3BF
+    mww 0x40023004 0x43840000
+    mwb 0x40023000 0x80
+
+    sleep 2
+}
+
+init
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/RISCV/core_riscv32.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/RISCV/core_riscv32.h
new file mode 100644
index 0000000..fa0e9ee
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/RISCV/core_riscv32.h
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+#ifndef __CORE_RISCV32_H__
+#define __CORE_RISCV32_H__
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define RISCV32
+
+#if defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
+  #define __STATIC_INLINE  static inline
+
+#else
+  #error Unknown compiler
+#endif
+
+#if defined ( __GNUC__ )
+
+#define __BKPT(x) __ASM("ebreak")
+
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("nop");
+}
+
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("nop");
+}
+
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+{
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("csrsi mstatus, 8");
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("csrci mstatus, 8");
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+  return __builtin_bswap32(value);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  return __builtin_bswap16(value);
+}
+
+#else
+  #error Unknown compiler
+#endif
+
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_RISCV32_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/board.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/board.c
new file mode 100644
index 0000000..bd7d9f6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/board.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include 
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+    CLOCK_SetIpSrc(kCLOCK_Lpuart0, kCLOCK_IpSrcFircAsync);
+
+    uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+
+    DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/board.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/board.h
new file mode 100644
index 0000000..4523b03
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/board.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "clock_config.h"
+#include "fsl_gpio.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "RV32M1-VEGA"
+
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_LPUART
+#define BOARD_DEBUG_UART_BAUDRATE 115200U
+#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART0
+#define BOARD_DEBUG_UART_INSTANCE    0U
+#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(kCLOCK_Lpuart0)
+#define BOARD_UART_IRQ LPUART0_IRQn
+#define BOARD_UART_IRQ_HANDLER LPUART0_IRQHandler
+
+/* Definitions for eRPC MU transport layer */
+#if defined(FSL_FEATURE_MU_SIDE_A)
+#define MU_BASE MUA
+#define MU_IRQ MUA_IRQn
+#define MU_IRQ_HANDLER MUA_IRQHandler
+#endif
+#if defined(FSL_FEATURE_MU_SIDE_B)
+#define MU_BASE MUB
+#define MU_IRQ MUB_IRQn
+#define MU_IRQ_HANDLER MUB_IRQHandler
+#endif
+#define MU_IRQ_PRIORITY (2)
+
+/*! @brief Define the port interrupt number for the board switches */
+#define BOARD_SW2_GPIO GPIOA
+#define BOARD_SW2_PORT PORTA
+#define BOARD_SW2_GPIO_PIN 0U
+#define BOARD_SW2_IRQ PORTA_IRQn
+#define BOARD_SW2_IRQ_HANDLER PORTA_IRQHandler
+#define BOARD_SW2_NAME "SW2"
+
+/* Board led color mapping */
+#define BOARD_LED_RED_GPIO GPIOA
+#define BOARD_LED_RED_GPIO_PIN 24U
+
+/*! @brief The TPM channel used for board */
+#define BOARD_TPM_CHANNEL 0U
+
+#define LOGIC_LED_ON 1U
+#define LOGIC_LED_OFF 0U
+#define BOARD_LED1_GPIO GPIOA
+#define BOARD_LED1_GPIO_PIN 24U
+#define BOARD_LED2_GPIO GPIOA
+#define BOARD_LED2_GPIO_PIN 23U
+#define BOARD_LED3_GPIO GPIOA
+#define BOARD_LED3_GPIO_PIN 22U
+
+#define LED1_INIT(output)                                              \
+    GPIO_WritePinOutput(BOARD_LED1_GPIO, BOARD_LED1_GPIO_PIN, output); \
+    BOARD_LED1_GPIO->PDDR |= (1U << BOARD_LED1_GPIO_PIN)                                /*!< Enable target LED1 */
+#define LED1_ON() GPIO_SetPinsOutput(BOARD_LED1_GPIO, 1U << BOARD_LED1_GPIO_PIN)        /*!< Turn on target LED1 */
+#define LED1_OFF() GPIO_ClearPinsOutput(BOARD_LED1_GPIO, 1U << BOARD_LED1_GPIO_PIN)     /*!< Turn off target LED1 */
+#define LED1_TOGGLE() GPIO_TogglePinsOutput(BOARD_LED1_GPIO, 1U << BOARD_LED1_GPIO_PIN) /*!< Toggle on target LED1 */
+
+#define LED2_INIT(output)                                              \
+    GPIO_WritePinOutput(BOARD_LED2_GPIO, BOARD_LED2_GPIO_PIN, output); \
+    BOARD_LED2_GPIO->PDDR |= (1U << BOARD_LED2_GPIO_PIN)                                /*!< Enable target LED2 */
+#define LED2_ON() GPIO_SetPinsOutput(BOARD_LED2_GPIO, 1U << BOARD_LED2_GPIO_PIN)        /*!< Turn on target LED2 */
+#define LED2_OFF() GPIO_ClearPinsOutput(BOARD_LED2_GPIO, 1U << BOARD_LED2_GPIO_PIN)     /*!< Turn off target LED2 */
+#define LED2_TOGGLE() GPIO_TogglePinsOutput(BOARD_LED2_GPIO, 1U << BOARD_LED2_GPIO_PIN) /*!< Toggle on target LED2 */
+
+#define LED3_INIT(output)                                              \
+    GPIO_WritePinOutput(BOARD_LED3_GPIO, BOARD_LED3_GPIO_PIN, output); \
+    BOARD_LED3_GPIO->PDDR |= (1U << BOARD_LED3_GPIO_PIN)                                /*!< Enable target LED3 */
+#define LED3_ON() GPIO_SetPinsOutput(BOARD_LED3_GPIO, 1U << BOARD_LED3_GPIO_PIN)        /*!< Turn on target LED3 */
+#define LED3_OFF() GPIO_ClearPinsOutput(BOARD_LED3_GPIO, 1U << BOARD_LED3_GPIO_PIN)     /*!< Turn off target LED3 */
+#define LED3_TOGGLE() GPIO_TogglePinsOutput(BOARD_LED3_GPIO, 1U << BOARD_LED3_GPIO_PIN) /*!< Toggle on target LED3 */
+
+#define BOARD_USDHC0_BASEADDR USDHC0
+#define BOARD_USDHC_CD_PORT_BASE PORTC
+#define BOARD_USDHC_CD_GPIO_BASE GPIOC
+#define BOARD_USDHC_CD_GPIO_PIN 27
+#define BOARD_USDHC_CD_PORT_IRQ PORTC_IRQn
+#define BOARD_USDHC_CD_PORT_IRQ_HANDLER PORTC_IRQHandler
+
+#define BOARD_USDHC_CD_GPIO_INIT()                                                                                \
+    {                                                                                                             \
+        gpio_pin_config_t sw_config = {kGPIO_DigitalInput, 0};                                                    \
+        GPIO_PinInit(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN, &sw_config);                              \
+        PORT_SetPinInterruptConfig(BOARD_USDHC_CD_PORT_BASE, BOARD_USDHC_CD_GPIO_PIN, kPORT_InterruptRisingEdge); \
+    }
+
+#define BOARD_USDHC_CD_STATUS() (GPIO_ReadPinInput(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN))
+
+#define BOARD_USDHC_CD_INTERRUPT_STATUS() (GPIO_GetPinsInterruptFlags(BOARD_USDHC_CD_GPIO_BASE))
+#define BOARD_USDHC_CD_CLEAR_INTERRUPT(flag) (GPIO_ClearPinsInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, flag))
+#define BOARD_USDHC_CARD_INSERT_CD_LEVEL (1U)
+#define BOARD_USDHC0_CLK_FREQ (CLOCK_GetIpFreq(kCLOCK_Sdhc0))
+
+#define BOARD_SD_HOST_BASEADDR BOARD_USDHC0_BASEADDR
+#define BOARD_SD_HOST_CLK_FREQ BOARD_USDHC0_CLK_FREQ
+#define BOARD_SD_HOST_IRQ USDHC0_IRQn
+#define BOARD_SD_SUPPORT_180V (0U)
+#define BOARD_MMC_HOST_BASEADDR BOARD_USDHC0_BASEADDR
+#define BOARD_MMC_HOST_CLK_FREQ BOARD_USDHC0_CLK_FREQ
+#define BOARD_MMC_HOST_IRQ USDHC0_IRQn
+#define BOARD_MMC_VCCQ_SUPPLY kMMC_VoltageWindows270to360
+#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360
+#define BOARD_MMC_PIN_CONFIG(speed, strength)
+
+/* this define not implement, due to EVK board have no power reset circuit */
+#define BOARD_SD_POWER_RESET_GPIO ()
+#define BOARD_SD_POWER_RESET_GPIO_PIN ()
+#define BOARD_USDHC_SDCARD_POWER_CONTROL_INIT()
+#define BOARD_USDHC_SDCARD_POWER_CONTROL(state)
+#define BOARD_SD_PIN_CONFIG(speed, strength)
+#define BOARD_USDHC_MMCCARD_POWER_CONTROL(enable)
+#define BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT()
+
+#define LLWU_SW_GPIO BOARD_SW2_GPIO
+#define LLWU_SW_PORT BOARD_SW2_PORT
+#define LLWU_SW_GPIO_PIN BOARD_SW2_GPIO_PIN
+#define LLWU_SW_IRQ BOARD_SW2_IRQ
+#define LLWU_SW_IRQ_HANDLER BOARD_SW2_IRQ_HANDLER
+#define LLWU_SW_NAME BOARD_SW2_NAME
+
+#define NMI_PIN                0U
+#define JTAG_TCLK_PIN          1U
+#define JTAG_TDI_PIN           2U
+#define JTAG_TDO_PIN           3U
+#define JTAG_TMS_PIN           4U
+
+#define NMI_PORT               PORTA
+#define JTAG_TCLK_PORT         PORTA
+#define JTAG_TDI_PORT          PORTA
+#define JTAG_TDO_PORT          PORTA
+#define JTAG_TMS_PORT          PORTA 
+
+#define NMI_GPIO               GPIOA
+#define JTAG_TCLK_GPIO         GPIOA
+#define JTAG_TDI_GPIO          GPIOA
+#define JTAG_TDO_GPIO          GPIOA
+#define JTAG_TMS_GPIO          GPIOA
+
+#define BOARD_SPI_FLASH_SCLK_PORT       PORTB
+#define BOARD_SPI_FLASH_SCLK_GPIO       GPIOB
+#define BOARD_SPI_FLASH_SCLK_GPIO_PIN   20U
+
+#define BOARD_SPI_FLASH_SI_PORT         PORTB
+#define BOARD_SPI_FLASH_SI_GPIO         GPIOB
+#define BOARD_SPI_FLASH_SI_GPIO_PIN     21U
+
+#define BOARD_SPI_FLASH_CS_PORT         PORTB
+#define BOARD_SPI_FLASH_CS_GPIO         GPIOB
+#define BOARD_SPI_FLASH_CS_GPIO_PIN     22U
+
+#define BOARD_SPI_FLASH_SO_PORT         PORTB
+#define BOARD_SPI_FLASH_SO_GPIO         GPIOB
+#define BOARD_SPI_FLASH_SO_GPIO_PIN     24U
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/clock_config.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/clock_config.c
new file mode 100644
index 0000000..09fcc5b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/clock_config.c
@@ -0,0 +1,436 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
+ *    Note: The clock could not be set when it is being used as system clock.
+ *    In default out of reset, the CPU is clocked from FIRC(IRC48M),
+ *    so before setting FIRC, change to use another avaliable clock source.
+ *
+ * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
+ *
+ * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
+ *    Wait until the system clock source is changed to target source.
+ *
+ * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
+ *    corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
+ *    Supported run mode and clock restrictions could be found in Reference Manual.
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v3.0
+processor: RV32M1
+package_id: RV32M1
+mcu_data: ksdk2_0
+processor_version: 0.0.0
+board: RV32M1_VEGA
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "fsl_msmc.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define SCG_LPFLL_DISABLE                                 0U  /*!< LPFLL clock disabled */
+#define SCG_SOSC_DISABLE                                  0U  /*!< System OSC disabled */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#ifndef SDK_SECONDARY_CORE
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_CONFIG_FircSafeConfig
+ * Description   : This function is used to safely configure FIRC clock.
+ *                 In default out of reset, the CPU is clocked from FIRC(IRC48M).
+ *                 Before setting FIRC, change to use SIRC as system clock,
+ *                 then configure FIRC. 
+ * Param fircConfig  : FIRC configuration.
+ *
+ *END**************************************************************************/
+static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
+{
+    scg_sys_clk_config_t curConfig;
+    const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
+                                             .div1 = kSCG_AsyncClkDisable,
+                                             .div2 = kSCG_AsyncClkDivBy2,
+                                             .range = kSCG_SircRangeHigh};
+    scg_sys_clk_config_t sysClkSafeConfigSource = {
+         .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider. */
+         .divCore = kSCG_SysClkDivBy1, /* Core clock divider. */
+         .src = kSCG_SysClkSrcSirc     /* System clock source. */
+    };
+    /* Init Sirc */
+    CLOCK_InitSirc(&scgSircConfig);
+    /* Change to use SIRC as system clock source to prepare to change FIRCCFG register */
+    CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
+    /* Wait for clock source switch finished */
+    do
+    {
+        CLOCK_GetCurSysClkConfig(&curConfig);
+    } while (curConfig.src != sysClkSafeConfigSource.src);
+
+    /* Init Firc */
+    CLOCK_InitFirc(fircConfig);
+}
+#endif
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: Bus_clock.outFreq, value: 48 MHz}
+- {id: Core_clock.outFreq, value: 48 MHz}
+- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
+- {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
+- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
+- {id: LPO_CLK.outFreq, value: 1 kHz}
+- {id: Platform_clock.outFreq, value: 48 MHz}
+- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
+- {id: Slow_clock.outFreq, value: 24 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
+- {id: SCG.FIRCDIV2.scale, value: '1', locked: true}
+- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
+- {id: SCG.LPFLLDIV1.scale, value: '1', locked: true}
+- {id: SCG.LPFLLDIV3.scale, value: '0', locked: true}
+- {id: SCG.SIRCDIV1.scale, value: '0', locked: true}
+- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
+    {
+        .divSlow = kSCG_SysClkDivBy2,             /* Slow Clock Divider: divided by 2 */
+        .divBus = kSCG_SysClkDivBy1,              /* Bus Clock Divider: divided by 1 */
+        .divExt = kSCG_SysClkDivBy1,              /* External Clock Divider: divided by 1 */
+        .divCore = kSCG_SysClkDivBy1,             /* Core Clock Divider: divided by 1 */
+        .src = kSCG_SysClkSrcFirc,                /* Fast IRC is selected as System Clock Source */
+    };
+const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN =
+    {
+        .freq = 0U,                               /* System Oscillator frequency: 0Hz */
+        .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
+        .enableMode = SCG_SOSC_DISABLE,           /* System OSC disabled */
+        .div1 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 1: Clock output is disabled */
+        .div2 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 2: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 3: Clock output is disabled */
+    };
+const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
+    {
+        .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
+        .div1 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 1: Clock output is disabled */
+        .div2 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 2: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDivBy1,              /* Slow IRC Clock Divider 3: divided by 1 */
+        .range = kSCG_SircRangeHigh,              /* Slow IRC high range clock (8 MHz) */
+    };
+const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
+    {
+        .enableMode = kSCG_FircEnable,            /* Enable FIRC clock */
+        .div1 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 1: divided by 1 */
+        .div2 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 2: divided by 1 */
+        .div3 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 3: divided by 1 */
+        .range = kSCG_FircRange48M,               /* Fast IRC is trimmed to 48MHz */
+        .trimConfig = NULL,
+    };
+const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockRUN =
+    {
+        .enableMode = SCG_LPFLL_DISABLE,          /* LPFLL clock disabled */
+        .div1 = kSCG_AsyncClkDivBy1,              /* Low Power FLL Clock Divider 1: divided by 1 */
+        .div2 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 2: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 3: Clock output is disabled */
+        .range = kSCG_LpFllRange48M,              /* LPFLL is trimmed to 48MHz */
+        .trimConfig = NULL,
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    scg_sys_clk_config_t curConfig;
+
+    /* Init FIRC */
+    CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
+    /* Set SCG to FIRC mode. */
+    CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
+    /* Wait for clock source switch finished */
+    do
+    {
+        CLOCK_GetCurSysClkConfig(&curConfig);
+    } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
+    /* Init SIRC */
+    CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
+    /* Init LPFLL */
+    CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockHSRUN **********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockHSRUN
+outputs:
+- {id: Bus_clock.outFreq, value: 72 MHz}
+- {id: Core_clock.outFreq, value: 72 MHz}
+- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
+- {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
+- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
+- {id: LPO_CLK.outFreq, value: 1 kHz}
+- {id: Platform_clock.outFreq, value: 72 MHz}
+- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
+- {id: Slow_clock.outFreq, value: 8 MHz}
+- {id: System_clock.outFreq, value: 72 MHz}
+settings:
+- {id: SCGMode, value: LPFLL}
+- {id: powerMode, value: HSRUN}
+- {id: SCG.DIVCORE.scale, value: '1', locked: true}
+- {id: SCG.DIVSLOW.scale, value: '9'}
+- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
+- {id: SCG.FIRCDIV2.scale, value: '1', locked: true}
+- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
+- {id: SCG.LPFLLDIV1.scale, value: '0', locked: true}
+- {id: SCG.LPFLL_mul.scale, value: '36', locked: true}
+- {id: SCG.SCSSEL.sel, value: SCG.LPFLL}
+- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
+- {id: SCG.TRIMDIV.scale, value: '24'}
+- {id: SCG.TRIMSRCSEL.sel, value: SCG.FIRC}
+- {id: 'SCG::RCCR[SCS].bitField', value: '5'}
+- {id: SCG_LPFLLCSR_LPFLLEN_CFG, value: Enabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockHSRUN configuration
+ ******************************************************************************/
+const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN =
+    {
+        .divSlow = kSCG_SysClkDivBy9,             /* Slow Clock Divider: divided by 9 */
+        .divBus = kSCG_SysClkDivBy1,              /* Bus Clock Divider: divided by 1 */
+        .divExt = kSCG_SysClkDivBy1,              /* External Clock Divider: divided by 1 */
+        .divCore = kSCG_SysClkDivBy1,             /* Core Clock Divider: divided by 1 */
+        .src = kSCG_SysClkSrcLpFll,               /* Low power FLL is selected as System Clock Source */
+    };
+const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN =
+    {
+        .freq = 0U,                               /* System Oscillator frequency: 0Hz */
+        .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
+        .enableMode = SCG_SOSC_DISABLE,           /* System OSC disabled */
+        .div1 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 1: Clock output is disabled */
+        .div2 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 2: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 3: Clock output is disabled */
+    };
+const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN =
+    {
+        .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
+        .div1 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 1: Clock output is disabled */
+        .div2 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 2: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDivBy1,              /* Slow IRC Clock Divider 3: divided by 1 */
+        .range = kSCG_SircRangeHigh,              /* Slow IRC high range clock (8 MHz) */
+    };
+const scg_firc_config_t g_scgFircConfig_BOARD_BootClockHSRUN =
+    {
+        .enableMode = kSCG_FircEnable,            /* Enable FIRC clock */
+        .div1 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 1: divided by 1 */
+        .div2 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 2: divided by 1 */
+        .div3 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 3: divided by 1 */
+        .range = kSCG_FircRange48M,               /* Fast IRC is trimmed to 48MHz */
+        .trimConfig = NULL,
+    };
+const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockHSRUN =
+    {
+        .enableMode = kSCG_LpFllEnable,           /* Enable LPFLL clock */
+        .div1 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 1: Clock output is disabled */
+        .div2 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 2: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 3: Clock output is disabled */
+        .range = kSCG_LpFllRange72M,              /* LPFLL is trimmed to 72MHz */
+        .trimConfig = NULL,
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockHSRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockHSRUN(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    scg_sys_clk_config_t curConfig;
+
+    /* Init FIRC */
+    CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockHSRUN);
+    /* Init LPFLL */
+    CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockHSRUN);
+#if defined(CPU_RV32M1_cm4) || defined(CPU_RV32M1_ri5cy)
+    /* Set HSRUN power mode */
+    SMC_SetPowerModeProtection(SMC0, kSMC_AllowPowerModeAll);
+    SMC_SetPowerModeHsrun(SMC0);
+    while (SMC_GetPowerModeState(SMC0) != kSMC_PowerStateHsrun)
+    {
+    }
+#elif defined(CPU_RV32M1_cm0plus) || defined(CPU_RV32M1_zero_riscy)
+    SMC_SetPowerModeProtection(SMC1, kSMC_AllowPowerModeAll);
+    SMC_SetPowerModeHsrun(SMC1);
+    while (SMC_GetPowerModeState(SMC1) != kSMC_PowerStateHsrun)
+    {
+    }
+#endif
+    /* Set SCG to LPFLL mode. */
+    CLOCK_SetHsrunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockHSRUN);
+    /* Wait for clock source switch finished */
+    do
+    {
+        CLOCK_GetCurSysClkConfig(&curConfig);
+    } while (curConfig.src != g_sysClkConfig_BOARD_BootClockHSRUN.src);
+    /* Init SIRC */
+    CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockHSRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockVLPR
+outputs:
+- {id: Bus_clock.outFreq, value: 2 MHz}
+- {id: Core_clock.outFreq, value: 4 MHz}
+- {id: LPO_CLK.outFreq, value: 1 kHz}
+- {id: Platform_clock.outFreq, value: 4 MHz}
+- {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
+- {id: SIRCDIV2_CLK.outFreq, value: 8 MHz}
+- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
+- {id: Slow_clock.outFreq, value: 4000/9 kHz}
+- {id: System_clock.outFreq, value: 4 MHz}
+settings:
+- {id: SCGMode, value: SIRC}
+- {id: powerMode, value: VLPR}
+- {id: SCG.DIVBUS.scale, value: '2', locked: true}
+- {id: SCG.DIVCORE.scale, value: '2', locked: true}
+- {id: SCG.DIVSLOW.scale, value: '9'}
+- {id: SCG.FIRCDIV1.scale, value: '1'}
+- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
+- {id: SCG.SIRCDIV1.scale, value: '1', locked: true}
+- {id: SCG.SIRCDIV2.scale, value: '1', locked: true}
+- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR =
+    {
+        .divSlow = kSCG_SysClkDivBy9,             /* Slow Clock Divider: divided by 9 */
+        .divBus = kSCG_SysClkDivBy2,              /* Bus Clock Divider: divided by 2 */
+        .divExt = kSCG_SysClkDivBy1,              /* External Clock Divider: divided by 1 */
+        .divCore = kSCG_SysClkDivBy2,             /* Core Clock Divider: divided by 2 */
+        .src = kSCG_SysClkSrcSirc,                /* Slow IRC is selected as System Clock Source */
+    };
+const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR =
+    {
+        .freq = 0U,                               /* System Oscillator frequency: 0Hz */
+        .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
+        .enableMode = SCG_SOSC_DISABLE,           /* System OSC disabled */
+        .div1 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 1: Clock output is disabled */
+        .div2 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 2: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 3: Clock output is disabled */
+    };
+const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
+    {
+        .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
+        .div1 = kSCG_AsyncClkDivBy1,              /* Slow IRC Clock Divider 1: divided by 1 */
+        .div2 = kSCG_AsyncClkDivBy1,              /* Slow IRC Clock Divider 2: divided by 1 */
+        .div3 = kSCG_AsyncClkDivBy1,              /* Slow IRC Clock Divider 3: divided by 1 */
+        .range = kSCG_SircRangeHigh,              /* Slow IRC high range clock (8 MHz) */
+    };
+const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR =
+    {
+        .enableMode = kSCG_FircEnable,            /* Enable FIRC clock */
+        .div1 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 1: divided by 1 */
+        .div2 = kSCG_AsyncClkDisable,             /* Fast IRC Clock Divider 2: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDisable,             /* Fast IRC Clock Divider 3: Clock output is disabled */
+        .range = kSCG_FircRange48M,               /* Fast IRC is trimmed to 48MHz */
+        .trimConfig = NULL,
+    };
+const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockVLPR =
+    {
+        .enableMode = SCG_LPFLL_DISABLE,          /* LPFLL clock disabled */
+        .div1 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 1: Clock output is disabled */
+        .div2 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 2: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 3: Clock output is disabled */
+        .range = kSCG_LpFllRange48M,              /* LPFLL is trimmed to 48MHz */
+        .trimConfig = NULL,
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+void BOARD_BootClockVLPR(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    scg_sys_clk_config_t curConfig;
+
+    /* Init SIRC */
+    CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockVLPR);
+    /* Set SCG to SIRC mode. */
+    CLOCK_SetVlprModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockVLPR);
+    /* Init FIRC */
+    CLOCK_InitFirc(&g_scgFircConfig_BOARD_BootClockVLPR);
+    /* Init LPFLL */
+    CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockVLPR);
+#if defined(CPU_RV32M1_cm4) || defined(CPU_RV32M1_ri5cy)
+    /* Set VLPR power mode. */
+    SMC_SetPowerModeProtection(SMC0, kSMC_AllowPowerModeAll);
+    SMC_SetPowerModeVlpr(SMC0);
+    while (SMC_GetPowerModeState(SMC0) != kSMC_PowerStateVlpr)
+    {
+    }
+#elif defined(CPU_RV32M1_cm0plus) || defined(CPU_RV32M1_zero_riscy)
+    /* Set VLPR power mode. */
+    SMC_SetPowerModeProtection(SMC1, kSMC_AllowPowerModeAll);
+    SMC_SetPowerModeVlpr(SMC1);
+    while (SMC_GetPowerModeState(SMC1) != kSMC_PowerStateVlpr)
+    {
+    }
+#endif
+    /* Wait for clock source switch finished */
+    do
+    {
+        CLOCK_GetCurSysClkConfig(&curConfig);
+    } while (curConfig.src != g_sysClkConfig_BOARD_BootClockVLPR.src);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
+#endif
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/clock_config.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/clock_config.h
new file mode 100644
index 0000000..75fd7d6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/clock_config.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+ 
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK              48000000U  /*!< Core clock frequency: 48000000Hz */
+
+/*! @brief SCG set for BOARD_BootClockRUN configuration.
+ */
+extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN;
+/*! @brief System OSC set for BOARD_BootClockRUN configuration.
+ */
+extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN;
+/*! @brief SIRC set for BOARD_BootClockRUN configuration.
+ */
+extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN;
+/*! @brief FIRC set for BOARD_BootClockRUN configuration.
+ */
+extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockRUN;
+/*! @brief Low Power FLL set for BOARD_BootClockRUN configuration.
+ */
+extern const scg_lpfll_config_t g_scgLpFllConfigBOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockHSRUN **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockHSRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK            72000000U  /*!< Core clock frequency: 72000000Hz */
+
+/*! @brief SCG set for BOARD_BootClockHSRUN configuration.
+ */
+extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN;
+/*! @brief System OSC set for BOARD_BootClockHSRUN configuration.
+ */
+extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN;
+/*! @brief SIRC set for BOARD_BootClockHSRUN configuration.
+ */
+extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN;
+/*! @brief FIRC set for BOARD_BootClockHSRUN configuration.
+ */
+extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockHSRUN;
+/*! @brief Low Power FLL set for BOARD_BootClockHSRUN configuration.
+ */
+extern const scg_lpfll_config_t g_scgLpFllConfigBOARD_BootClockHSRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockHSRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockHSRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK              4000000U  /*!< Core clock frequency: 4000000Hz */
+
+/*! @brief SCG set for BOARD_BootClockVLPR configuration.
+ */
+extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR;
+/*! @brief System OSC set for BOARD_BootClockVLPR configuration.
+ */
+extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR;
+/*! @brief SIRC set for BOARD_BootClockVLPR configuration.
+ */
+extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR;
+/*! @brief FIRC set for BOARD_BootClockVLPR configuration.
+ */
+extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockVLPR;
+/*! @brief Low Power FLL set for BOARD_BootClockVLPR configuration.
+ */
+extern const scg_lpfll_config_t g_scgLpFllConfigBOARD_BootClockVLPR;
+
+/*******************************************************************************
+ * API for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockVLPR(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/readme.txt b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/readme.txt
new file mode 100644
index 0000000..391b4a9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/readme.txt
@@ -0,0 +1,48 @@
+Overview
+========
+The Hello World demo application provides a sanity check for the new SDK build environments and board bring up. The Hello
+World demo prints the "Hello World" string to the terminal using the SDK UART drivers. The purpose of this demo is to
+show how to use the UART, and to provide a simple project for debugging and further development.
+
+Toolchain supported
+===================
+- GCC RISC-V Embedded 7.1.1
+- RISC-V Eclipse IDE 4.7.2
+
+Hardware requirements
+=====================
+- Mini/micro USB cable
+- RV32M1-VEGA board
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+If download M0+ core project, need to let MCU boot from M0+ core, please follow below steps:
+1. Download blhost.exe from www.nxp.com/kboot.
+2. Connect J8 on board to PC using USB cable.
+3. After PC recognize the USB HID device, go to blhost.exe folder, open command line.
+4. Run command "blhost.exe -u -- flash-erase-all-unsecure", it will erase the flash on chip.
+5. Run command "blhost.exe -u -- flash-program-once 0x84 4 ffffffbf", set FOPT3 to boot from M0+ core.
+
+Prepare the Demo
+================
+1.  Connect a USB cable between the host PC and the OpenSDA USB port on the target board. 
+2.  Open a serial terminal with the following settings:
+    - 115200 baud rate
+    - 8 data bits
+    - No parity
+    - One stop bit
+    - No flow control
+3.  Download the program to the target board.
+4.  Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+The log below shows the output of the hello world demo in the terminal window:
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+hello world.
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Customization options
+=====================
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/RV32M1_ri5cy.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/RV32M1_ri5cy.h
new file mode 100644
index 0000000..0264b6f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/RV32M1_ri5cy.h
@@ -0,0 +1,24026 @@
+/*
+** ###################################################################
+**     Processors:          RV32M1_ri5cy
+**                          RV32M1_ri5cy
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
+**     Version:             rev. 1.0, 2018-10-02
+**     Build:               b180926
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for RV32M1_ri5cy
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2018-10-02)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file RV32M1_ri5cy.h
+ * @version 1.0
+ * @date 2018-10-02
+ * @brief CMSIS Peripheral Access Layer for RV32M1_ri5cy
+ *
+ * CMSIS Peripheral Access Layer for RV32M1_ri5cy
+ */
+
+#ifndef _RV32M1_RI5CY_H_
+#define _RV32M1_RI5CY_H_                    /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
+
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 82                 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Device specific interrupts */
+  DMA0_0_4_8_12_IRQn           = 0,                /**< DMA0 channel 0/4/8/12 transfer complete */
+  DMA0_1_5_9_13_IRQn           = 1,                /**< DMA0 channel 1/5/9/13 transfer complete */
+  DMA0_2_6_10_14_IRQn          = 2,                /**< DMA0 channel 2/6/10/14 transfer complete */
+  DMA0_3_7_11_15_IRQn          = 3,                /**< DMA0 channel 3/7/11/15 transfer complete */
+  DMA0_Error_IRQn              = 4,                /**< DMA0 channel 0-15 error interrupt */
+  CMC0_IRQn                    = 5,                /**< Core Mode Controller 0 */
+  MUA_IRQn                     = 6,                /**< MU Side A interrupt */
+  USB0_IRQn                    = 7,                /**< USB0 interrupt */
+  USDHC0_IRQn                  = 8,                /**< SDHC0 interrupt */
+  I2S0_IRQn                    = 9,                /**< I2S0 interrupt */
+  FLEXIO0_IRQn                 = 10,               /**< FLEXIO0 */
+  EMVSIM0_IRQn                 = 11,               /**< EMVSIM0 interrupt */
+  LPIT0_IRQn                   = 12,               /**< LPIT0 interrupt */
+  LPSPI0_IRQn                  = 13,               /**< LPSPI0 single interrupt vector for all sources */
+  LPSPI1_IRQn                  = 14,               /**< LPSPI1 single interrupt vector for all sources */
+  LPI2C0_IRQn                  = 15,               /**< LPI2C0 interrupt */
+  LPI2C1_IRQn                  = 16,               /**< LPI2C1 interrupt */
+  LPUART0_IRQn                 = 17,               /**< LPUART0 status and error */
+  PORTA_IRQn                   = 18,               /**< PORTA Pin detect */
+  TPM0_IRQn                    = 19,               /**< TPM0 single interrupt vector for all sources */
+  ADC0_IRQn                    = 21,               /**< LPADC0 interrupt */
+  LPDAC0_IRQn                  = 20,               /**< DAC0 interrupt */
+  LPCMP0_IRQn                  = 22,               /**< LPCMP0 interrupt */
+  RTC_IRQn                     = 23,               /**< RTC Alarm interrupt */
+  INTMUX0_0_IRQn               = 24,               /**< INTMUX0 channel0 interrupt */
+  INTMUX0_1_IRQn               = 25,               /**< INTMUX0 channel1 interrupt */
+  INTMUX0_2_IRQn               = 26,               /**< INTMUX0 channel2 interrupt */
+  INTMUX0_3_IRQn               = 27,               /**< INTMUX0 channel3 interrupt */
+  INTMUX0_4_IRQn               = 28,               /**< INTMUX0 channel4 interrupt */
+  INTMUX0_5_IRQn               = 29,               /**< INTMUX0 channel5 interrupt */
+  INTMUX0_6_IRQn               = 30,               /**< INTMUX0 channel6 interrupt */
+  INTMUX0_7_IRQn               = 31,               /**< INTMUX0 channel7 interrupt */
+  EWM_IRQn                     = 32,               /**< EWM interrupt */
+  FTFE_Command_Complete_IRQn   = 33,               /**< FTFE interrupt */
+  FTFE_Read_Collision_IRQn     = 34,               /**< FTFE interrupt */
+  LLWU0_IRQn                   = 35,               /**< Low leakage wakeup 0 */
+  SPM_IRQn                     = 36,               /**< SPM */
+  WDOG0_IRQn                   = 37,               /**< WDOG0 interrupt */
+  SCG_IRQn                     = 38,               /**< SCG interrupt */
+  LPTMR0_IRQn                  = 39,               /**< LPTMR0 interrupt */
+  LPTMR1_IRQn                  = 40,               /**< LPTMR1 interrupt */
+  TPM1_IRQn                    = 41,               /**< TPM1 single interrupt vector for all sources */
+  TPM2_IRQn                    = 42,               /**< TPM2 single interrupt vector for all sources */
+  LPI2C2_IRQn                  = 43,               /**< LPI2C2 interrupt */
+  LPSPI2_IRQn                  = 44,               /**< LPSPI2 single interrupt vector for all sources */
+  LPUART1_IRQn                 = 45,               /**< LPUART1 status and error */
+  LPUART2_IRQn                 = 46,               /**< LPUART2 status and error */
+  PORTB_IRQn                   = 47,               /**< PORTB Pin detect */
+  PORTC_IRQn                   = 48,               /**< PORTC Pin detect */
+  PORTD_IRQn                   = 49,               /**< PORTD Pin detect */
+  CAU3_Task_Complete_IRQn      = 50,               /**< Cryptographic Acceleration Unit version 3 Task Complete */
+  CAU3_Security_Violation_IRQn = 51,               /**< Cryptographic Acceleration Unit version 3 Security Violation */
+  TRNG_IRQn                    = 52,               /**< TRNG interrupt */
+  LPIT1_IRQn                   = 53,               /**< LPIT1 interrupt */
+  LPTMR2_IRQn                  = 54,               /**< LPTMR2 interrupt */
+  TPM3_IRQn                    = 55,               /**< TPM3 single interrupt vector for all sources */
+  LPI2C3_IRQn                  = 56,               /**< LPI2C3 interrupt */
+  LPSPI3_IRQn                  = 57,               /**< LPSPI3 single interrupt vector for all sources */
+  LPUART3_IRQn                 = 58,               /**< LPUART3 status and error */
+  PORTE_IRQn                   = 59,               /**< PORTE Pin detect */
+  LPCMP1_IRQn                  = 60,               /**< LPCMP1 interrupt */
+  RF0_0_IRQn                   = 61,               /**< RF0 interrupt 0 */
+  RF0_1_IRQn                   = 62,               /**< RF0 interrupt 1 */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M4 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               3         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
+
+#include "core_riscv32.h"              /* Core Peripheral Access Layer */
+#include "system_RV32M1_ri5cy.h"  /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup edma_request
+ * @{ */
+
+/*******************************************************************************
+ * Definitions
+*******************************************************************************/
+
+/*!
+ * @brief Enumeration for the DMA hardware request
+ *
+ * Defines the enumeration for the DMA hardware request collections.
+ */
+typedef enum _dma_request_source
+{
+    kDmaRequestMux0LLWU0            = 0|0x100U,    /**< LLWU0 Wakeup */
+    kDmaRequestMux0LPTMR0           = 1|0x100U,    /**< LPTMR0 Trigger */
+    kDmaRequestMux0LPTMR1           = 2|0x100U,    /**< LPTMR1 Trigger */
+    kDmaRequestMux0TPM0Channel0     = 3|0x100U,    /**< TPM0 Channel 0 */
+    kDmaRequestMux0TPM0Channel1     = 4|0x100U,    /**< TPM0 Channel 1 */
+    kDmaRequestMux0TPM0Channel2     = 5|0x100U,    /**< TPM0 Channel 2 */
+    kDmaRequestMux0TPM0Channel3     = 6|0x100U,    /**< TPM0 Channel 3 */
+    kDmaRequestMux0TPM0Channel4     = 7|0x100U,    /**< TPM0 Channel 4 */
+    kDmaRequestMux0TPM0Channel5     = 8|0x100U,    /**< TPM0 Channel 5 */
+    kDmaRequestMux0TPM0Overflow     = 9|0x100U,    /**< TPM0 Overflow */
+    kDmaRequestMux0TPM1Channel0     = 10|0x100U,   /**< TPM1 Channel 0 */
+    kDmaRequestMux0TPM1Channel1     = 11|0x100U,   /**< TPM1 Channel 1 */
+    kDmaRequestMux0TPM1Overflow     = 12|0x100U,   /**< TPM1 Overflow */
+    kDmaRequestMux0TPM2Channel0     = 13|0x100U,   /**< TPM2 Channel 0 */
+    kDmaRequestMux0TPM2Channel1     = 14|0x100U,   /**< TPM2 Channel 1 */
+    kDmaRequestMux0TPM2Channel2     = 15|0x100U,   /**< TPM2 Channel 2 */
+    kDmaRequestMux0TPM2Channel3     = 16|0x100U,   /**< TPM2 Channel 3 */
+    kDmaRequestMux0TPM2Channel4     = 17|0x100U,   /**< TPM2 Channel 4 */
+    kDmaRequestMux0TPM2Channel5     = 18|0x100U,   /**< TPM2 Channel 5 */
+    kDmaRequestMux0TPM2Overflow     = 19|0x100U,   /**< TPM2 Overflow */
+    kDmaRequestMux0EMVSIM0Rx        = 20|0x100U,   /**< EMVSIM0 Receive */
+    kDmaRequestMux0EMVSIM0Tx        = 21|0x100U,   /**< EMVSIM0 Transmit */
+    kDmaRequestMux0FLEXIO0Channel0  = 22|0x100U,   /**< FLEXIO0 Channel 0 */
+    kDmaRequestMux0FLEXIO0Channel1  = 23|0x100U,   /**< FLEXIO0 Channel 1 */
+    kDmaRequestMux0FLEXIO0Channel2  = 24|0x100U,   /**< FLEXIO0 Channel 2 */
+    kDmaRequestMux0FLEXIO0Channel3  = 25|0x100U,   /**< FLEXIO0 Channel 3 */
+    kDmaRequestMux0FLEXIO0Channel4  = 26|0x100U,   /**< FLEXIO0 Channel 4 */
+    kDmaRequestMux0FLEXIO0Channel5  = 27|0x100U,   /**< FLEXIO0 Channel 5 */
+    kDmaRequestMux0FLEXIO0Channel6  = 28|0x100U,   /**< FLEXIO0 Channel 6 */
+    kDmaRequestMux0FLEXIO0Channel7  = 29|0x100U,   /**< FLEXIO0 Channel 7 */
+    kDmaRequestMux0LPI2C0Rx         = 30|0x100U,   /**< LPI2C0 Receive */
+    kDmaRequestMux0LPI2C0Tx         = 31|0x100U,   /**< LPI2C0 Transmit */
+    kDmaRequestMux0LPI2C1Rx         = 32|0x100U,   /**< LPI2C1 Receive */
+    kDmaRequestMux0LPI2C1Tx         = 33|0x100U,   /**< LPI2C1 Transmit */
+    kDmaRequestMux0LPI2C2Rx         = 34|0x100U,   /**< LPI2C2 Receive */
+    kDmaRequestMux0LPI2C2Tx         = 35|0x100U,   /**< LPI2C2 Transmit */
+    kDmaRequestMux0I2S0Rx           = 36|0x100U,   /**< I2S0 Receive */
+    kDmaRequestMux0I2S0Tx           = 37|0x100U,   /**< I2S0 Transmit */
+    kDmaRequestMux0LPSPI0Rx         = 38|0x100U,   /**< LPSPI0 Receive */
+    kDmaRequestMux0LPSPI0Tx         = 39|0x100U,   /**< LPSPI0 Transmit */
+    kDmaRequestMux0LPSPI1Rx         = 40|0x100U,   /**< LPSPI1 Receive */
+    kDmaRequestMux0LPSPI1Tx         = 41|0x100U,   /**< LPSPI1 Transmit */
+    kDmaRequestMux0LPSPI2Rx         = 42|0x100U,   /**< LPSPI2 Receive */
+    kDmaRequestMux0LPSPI2Tx         = 43|0x100U,   /**< LPSPI2 Transmit */
+    kDmaRequestMux0LPUART0Rx        = 44|0x100U,   /**< LPUART0 Receive */
+    kDmaRequestMux0LPUART0Tx        = 45|0x100U,   /**< LPUART0 Transmit */
+    kDmaRequestMux0LPUART1Rx        = 46|0x100U,   /**< LPUART1 Receive */
+    kDmaRequestMux0LPUART1Tx        = 47|0x100U,   /**< LPUART1 Transmit */
+    kDmaRequestMux0LPUART2Rx        = 48|0x100U,   /**< LPUART2 Receive */
+    kDmaRequestMux0LPUART2Tx        = 49|0x100U,   /**< LPUART2 Transmit */
+    kDmaRequestMux0PORTA            = 50|0x100U,   /**< PORTA Pin Request */
+    kDmaRequestMux0PORTB            = 51|0x100U,   /**< PORTB Pin Request */
+    kDmaRequestMux0PORTC            = 52|0x100U,   /**< PORTC Pin Request */
+    kDmaRequestMux0PORTD            = 53|0x100U,   /**< PORTD Pin Request */
+    kDmaRequestMux0LPADC0           = 54|0x100U,   /**< LPADC0 Conversion Complete */
+    kDmaRequestMux0LPCMP0           = 55|0x100U,   /**< LPCMP0 Comparator Trigger */
+    kDmaRequestMux0DAC0             = 56|0x100U,   /**< DAC0 Conversion Complete */
+    kDmaRequestMux0CAUv3            = 57|0x100U,   /**< CAUv3 Data Request */
+    kDmaRequestMux0LPTMR2           = 58|0x100U,   /**< LPTMR2 Trigger */
+    kDmaRequestMux0LPSPI3Rx         = 59|0x100U,   /**< LPSPI3 Receive */
+    kDmaRequestMux0LPSPI3Tx         = 60|0x100U,   /**< LPSPI3 Transmit */
+    kDmaRequestMux0LPUART3Rx        = 61|0x100U,   /**< LPUART3 Receive */
+    kDmaRequestMux0LPUART3Tx        = 62|0x100U,   /**< LPUART3 Transmit */
+    kDmaRequestMux0PORTE            = 63|0x100U,   /**< PORTE Pin Request */
+} dma_request_source_t;
+
+/* @} */
+
+/*!
+ * @addtogroup trgmux_source
+ * @{ */
+
+/*******************************************************************************
+ * Definitions
+*******************************************************************************/
+
+/*!
+ * @brief Enumeration for the TRGMUX source
+ *
+ * Defines the enumeration for the TRGMUX source collections.
+ */
+typedef enum _trgmux_source
+{
+    kTRGMUX_Source0Disabled         = 0U,          /**< Trigger function is disabled */
+    kTRGMUX_Source1Disabled         = 0U,          /**< Trigger function is disabled */
+    kTRGMUX_Source0Llwu0            = 1U,          /**< LLWU0 trigger is selected */
+    kTRGMUX_Source1Llwu1            = 1U,          /**< LLWU1 trigger is selected */
+    kTRGMUX_Source0Lpit0Channel0    = 2U,          /**< LPIT0 Channel 0 is selected */
+    kTRGMUX_Source1Lpit1Channel0    = 2U,          /**< LPIT1 Channel 0 is selected */
+    kTRGMUX_Source0Lpit0Channel1    = 3U,          /**< LPIT0 Channel 1 is selected */
+    kTRGMUX_Source1Lpit1Channel1    = 3U,          /**< LPIT1 Channel 1 is selected */
+    kTRGMUX_Source0Lpit0Channel2    = 4U,          /**< LPIT0 Channel 2 is selected */
+    kTRGMUX_Source1Lpit1Channel2    = 4U,          /**< LPIT1 Channel 2 is selected */
+    kTRGMUX_Source0Lpit0Channel3    = 5U,          /**< LPIT0 Channel 3 is selected */
+    kTRGMUX_Source1Lpit1Channel3    = 5U,          /**< LPIT1 Channel 3 is selected */
+    kTRGMUX_Source0RtcAlarm         = 6U,          /**< RTC Alarm is selected */
+    kTRGMUX_Source1Lptmr2Trigger    = 6U,          /**< LPTMR2 Trigger is selected */
+    kTRGMUX_Source0RtcSeconds       = 7U,          /**< RTC Seconds is selected */
+    kTRGMUX_Source1Tpm3ChannelEven  = 7U,          /**< TPM3 Channel Even is selected */
+    kTRGMUX_Source0Lptmr0Trigger    = 8U,          /**< LPTMR0 Trigger is selected */
+    kTRGMUX_Source1Tpm3ChannelOdd   = 8U,          /**< TPM3 Channel Odd is selected */
+    kTRGMUX_Source0Lptmr1Trigger    = 9U,          /**< LPTMR1 Trigger is selected */
+    kTRGMUX_Source1Tpm3Overflow     = 9U,          /**< TPM3 Overflow is selected */
+    kTRGMUX_Source0Tpm0ChannelEven  = 10U,         /**< TPM0 Channel Even is selected */
+    kTRGMUX_Source1Lpi2c3MasterStop = 10U,         /**< LPI2C3 Master Stop is selected */
+    kTRGMUX_Source0Tpm0ChannelOdd   = 11U,         /**< TPM0 Channel Odd is selected */
+    kTRGMUX_Source1Lpi2c3SlaveStop  = 11U,         /**< LPI2C3 Slave Stop is selected */
+    kTRGMUX_Source0Tpm0Overflow     = 12U,         /**< TPM0 Overflow is selected */
+    kTRGMUX_Source1Lpspi3Frame      = 12U,         /**< LPSPI3 Frame is selected */
+    kTRGMUX_Source0Tpm1ChannelEven  = 13U,         /**< TPM1 Channel Even is selected */
+    kTRGMUX_Source1Lpspi3RX         = 13U,         /**< LPSPI3 Rx is selected */
+    kTRGMUX_Source0Tpm1ChannelOdd   = 14U,         /**< TPM1 Channel Odd is selected */
+    kTRGMUX_Source1Lpuart3RxData    = 14U,         /**< LPUART3 Rx Data is selected */
+    kTRGMUX_Source0Tpm1Overflow     = 15U,         /**< TPM1 Overflow is selected */
+    kTRGMUX_Source1Lpuart3RxIdle    = 15U,         /**< LPUART3 Rx Idle is selected */
+    kTRGMUX_Source0Tpm2ChannelEven  = 16U,         /**< TPM2 Channel Even is selected */
+    kTRGMUX_Source1Lpuart3TxData    = 16U,         /**< LPUART3 Tx Data is selected */
+    kTRGMUX_Source0Tpm2ChannelOdd   = 17U,         /**< TPM2 Channel Odd is selected */
+    kTRGMUX_Source1PortEPinTrigger  = 17U,         /**< PORTE Pin Trigger is selected */
+    kTRGMUX_Source0Tpm2Overflow     = 18U,         /**< TPM2 Overflow is selected */
+    kTRGMUX_Source1Lpcmp1Output     = 18U,         /**< LPCMP1 Output is selected */
+    kTRGMUX_Source0FlexIO0Timer0    = 19U,         /**< FlexIO0 Timer 0 is selected */
+    kTRGMUX_Source1RtcAlarm         = 19U,         /**< RTC Alarm is selected */
+    kTRGMUX_Source0FlexIO0Timer1    = 20U,         /**< FlexIO0 Timer 1 is selected */
+    kTRGMUX_Source1RtcSeconds       = 20U,         /**< RTC Seconds is selected */
+    kTRGMUX_Source0FlexIO0Timer2    = 21U,         /**< FlexIO0 Timer 2 is selected */
+    kTRGMUX_Source1Lptmr0Trigger    = 21U,         /**< LPTMR0 Trigger is selected */
+    kTRGMUX_Source0FlexIO0Timer3    = 22U,         /**< FlexIO0 Timer 3 is selected */
+    kTRGMUX_Source1Lptmr1Trigger    = 22U,         /**< LPTMR1 Trigger is selected */
+    kTRGMUX_Source0FlexIO0Timer4    = 23U,         /**< FLexIO0 Timer 4 is selected */
+    kTRGMUX_Source1Tpm1ChannelEven  = 23U,         /**< TPM1 Channel Even is selected */
+    kTRGMUX_Source0FlexIO0Timer5    = 24U,         /**< FlexIO0 Timer 5 is selected */
+    kTRGMUX_Source1Tpm1ChannelOdd   = 24U,         /**< TPM1 Channel Odd is selected */
+    kTRGMUX_Source0FlexIO0Timer6    = 25U,         /**< FlexIO0 Timer 6 is selected */
+    kTRGMUX_Source1Tpm1Overflow     = 25U,         /**< TPM1 Overflow is selected */
+    kTRGMUX_Source0FlexIO0Timer7    = 26U,         /**< FlexIO0 Timer 7 is selected */
+    kTRGMUX_Source1Tpm2ChannelEven  = 26U,         /**< TPM2 Channel Even is selected */
+    kTRGMUX_Source0Lpi2c0MasterStop = 27U,         /**< LPI2C0 Master Stop is selected */
+    kTRGMUX_Source1Tpm2ChannelOdd   = 27U,         /**< TPM2 Channel Odd is selected */
+    kTRGMUX_Source0Lpi2c0SlaveStop  = 28U,         /**< LPI2C0 Slave Stop is selected */
+    kTRGMUX_Source1Tpm2Overflow     = 28U,         /**< TPM2 Overflow is selected */
+    kTRGMUX_Source0Lpi2c1MasterStop = 29U,         /**< LPI2C1 Master Stop is selected */
+    kTRGMUX_Source1FlexIO0Timer0    = 29U,         /**< FlexIO0 Timer 0 is selected */
+    kTRGMUX_Source0Lpi2c1SlaveStop  = 30U,         /**< LPI2C1 Slave Stop is selected */
+    kTRGMUX_Source1FlexIO0Timer1    = 30U,         /**< FlexIO0 Timer 1 is selected */
+    kTRGMUX_Source0Lpi2c2MasterStop = 31U,         /**< LPI2C2 Master Stop is selected */
+    kTRGMUX_Source1FlexIO0Timer2    = 31U,         /**< FlexIO0 Timer 2 is selected */
+    kTRGMUX_Source0Lpi2c2SlaveStop  = 32U,         /**< LPI2C2 Slave Stop is selected */
+    kTRGMUX_Source1FlexIO0Timer3    = 32U,         /**< FlexIO0 Timer 3 is selected */
+    kTRGMUX_Source0Sai0Rx           = 33U,         /**< SAI0 Rx Frame Sync is selected */
+    kTRGMUX_Source1FlexIO0Timer4    = 33U,         /**< FLexIO0 Timer 4 is selected */
+    kTRGMUX_Source0Sai0Tx           = 34U,         /**< SAI0 Tx Frame Sync is selected */
+    kTRGMUX_Source1FlexIO0Timer5    = 34U,         /**< FlexIO0 Timer 5 is selected */
+    kTRGMUX_Source0Lpspi0Frame      = 35U,         /**< LPSPI0 Frame is selected */
+    kTRGMUX_Source1FlexIO0Timer6    = 35U,         /**< FlexIO0 Timer 6 is selected */
+    kTRGMUX_Source0Lpspi0Rx         = 36U,         /**< LPSPI0 Rx is selected */
+    kTRGMUX_Source1FlexIO0Timer7    = 36U,         /**< FlexIO0 Timer 7 is selected */
+    kTRGMUX_Source0Lpspi1Frame      = 37U,         /**< LPSPI1 Frame is selected */
+    kTRGMUX_Source1Lpi2c0MasterStop = 37U,         /**< LPI2C0 Master Stop is selected */
+    kTRGMUX_Source0Lpspi1Rx         = 38U,         /**< LPSPI1 Rx is selected */
+    kTRGMUX_Source1Lpi2c0SlaveStop  = 38U,         /**< LPI2C0 Slave Stop is selected */
+    kTRGMUX_Source0Lpspi2Frame      = 39U,         /**< LPSPI2 Frame is selected */
+    kTRGMUX_Source1Lpi2c1MasterStop = 39U,         /**< LPI2C1 Master Stop is selected */
+    kTRGMUX_Source0Lpspi2RX         = 40U,         /**< LPSPI2 Rx is selected */
+    kTRGMUX_Source1Lpi2c1SlaveStop  = 40U,         /**< LPI2C1 Slave Stop is selected */
+    kTRGMUX_Source0Lpuart0RxData    = 41U,         /**< LPUART0 Rx Data is selected */
+    kTRGMUX_Source1Lpi2c2MasterStop = 41U,         /**< LPI2C2 Master Stop is selected */
+    kTRGMUX_Source0Lpuart0RxIdle    = 42U,         /**< LPUART0 Rx Idle is selected */
+    kTRGMUX_Source1Lpi2c2SlaveStop  = 42U,         /**< LPI2C2 Slave Stop is selected */
+    kTRGMUX_Source0Lpuart0TxData    = 43U,         /**< LPUART0 Tx Data is selected */
+    kTRGMUX_Source1Sai0Rx           = 43U,         /**< SAI0 Rx Frame Sync is selected */
+    kTRGMUX_Source0Lpuart1RxData    = 44U,         /**< LPUART1 Rx Data is selected */
+    kTRGMUX_Source1Sai0Tx           = 44U,         /**< SAI0 Tx Frame Sync is selected */
+    kTRGMUX_Source0Lpuart1RxIdle    = 45U,         /**< LPUART1 Rx Idle is selected */
+    kTRGMUX_Source1Lpspi0Frame      = 45U,         /**< LPSPI0 Frame is selected */
+    kTRGMUX_Source0Lpuart1TxData    = 46U,         /**< LPUART1 TX Data is selected */
+    kTRGMUX_Source1Lpspi0Rx         = 46U,         /**< LPSPI0 Rx is selected */
+    kTRGMUX_Source0Lpuart2RxData    = 47U,         /**< LPUART2 RX Data is selected */
+    kTRGMUX_Source1Lpspi1Frame      = 47U,         /**< LPSPI1 Frame is selected */
+    kTRGMUX_Source0Lpuart2RxIdle    = 48U,         /**< LPUART2 RX Idle is selected */
+    kTRGMUX_Source1Lpspi1Rx         = 48U,         /**< LPSPI1 Rx is selected */
+    kTRGMUX_Source0Lpuart2TxData    = 49U,         /**< LPUART2 TX Data is selected */
+    kTRGMUX_Source1Lpspi2Frame      = 49U,         /**< LPSPI2 Frame is selected */
+    kTRGMUX_Source0Usb0Frame        = 50U,         /**< USB0 Start of Frame is selected */
+    kTRGMUX_Source1Lpspi2RX         = 50U,         /**< LPSPI2 Rx is selected */
+    kTRGMUX_Source0PortAPinTrigger  = 51U,         /**< PORTA Pin Trigger is selected */
+    kTRGMUX_Source1Lpuart0RxData    = 51U,         /**< LPUART0 Rx Data is selected */
+    kTRGMUX_Source0PortBPinTrigger  = 52U,         /**< PORTB Pin Trigger is selected */
+    kTRGMUX_Source1Lpuart0RxIdle    = 52U,         /**< LPUART0 Rx Idle is selected */
+    kTRGMUX_Source0PortCPinTrigger  = 53U,         /**< PORTC Pin Trigger is selected */
+    kTRGMUX_Source1Lpuart0TxData    = 53U,         /**< LPUART0 Tx Data is selected */
+    kTRGMUX_Source0PortDPinTrigger  = 54U,         /**< PORTD Pin Trigger is selected */
+    kTRGMUX_Source1Lpuart1RxData    = 54U,         /**< LPUART1 Rx Data is selected */
+    kTRGMUX_Source0Lpcmp0Output     = 55U,         /**< LPCMP0 Output is selected */
+    kTRGMUX_Source1Lpuart1RxIdle    = 55U,         /**< LPUART1 Rx Idle is selected */
+    kTRGMUX_Source0Lpi2c3MasterStop = 56U,         /**< LPI2C3 Master Stop is selected */
+    kTRGMUX_Source1Lpuart1TxData    = 56U,         /**< LPUART1 TX Data is selected */
+    kTRGMUX_Source0Lpi2c3SlaveStop  = 57U,         /**< LPI2C3 Slave Stop is selected */
+    kTRGMUX_Source1Lpuart2RxData    = 57U,         /**< LPUART2 RX Data is selected */
+    kTRGMUX_Source0Lpspi3Frame      = 58U,         /**< LPSPI3 Frame is selected */
+    kTRGMUX_Source1Lpuart2RxIdle    = 58U,         /**< LPUART2 RX Idle is selected */
+    kTRGMUX_Source0Lpspi3Rx         = 59U,         /**< LPSPI3 Rx Data is selected */
+    kTRGMUX_Source1Lpuart2TxData    = 59U,         /**< LPUART2 TX Data is selected */
+    kTRGMUX_Source0Lpuart3RxData    = 60U,         /**< LPUART3 Rx Data is selected */
+    kTRGMUX_Source1PortAPinTrigger  = 60U,         /**< PORTA Pin Trigger is selected */
+    kTRGMUX_Source0Lpuart3RxIdle    = 61U,         /**< LPUART3 Rx Idle is selected */
+    kTRGMUX_Source1PortBPinTrigger  = 61U,         /**< PORTB Pin Trigger is selected */
+    kTRGMUX_Source0Lpuart3TxData    = 62U,         /**< LPUART3 Tx Data is selected */
+    kTRGMUX_Source1PortCPinTrigger  = 62U,         /**< PORTC Pin Trigger is selected */
+    kTRGMUX_Source0PortEPinTrigger  = 63U,         /**< PORTE Pin Trigger is selected */
+    kTRGMUX_Source1PortDPinTrigger  = 63U,         /**< PORTD Pin Trigger is selected */
+} trgmux_source_t;
+
+/* @} */
+
+/*!
+ * @brief Enumeration for the TRGMUX device
+ *
+ * Defines the enumeration for the TRGMUX device collections.
+ */
+typedef enum _trgmux_device
+{
+    kTRGMUX_Trgmux0Dmamux0          = 0U,          /**< DMAMUX0 device trigger input */
+    kTRGMUX_Trgmux1Dmamux1          = 0U,          /**< DMAMUX1 device trigger input */
+    kTRGMUX_Trgmux0Lpit0            = 1U,          /**< LPIT0 device trigger input */
+    kTRGMUX_Trgmux1Lpit1            = 1U,          /**< LPIT1 device trigger input */
+    kTRGMUX_Trgmux0Tpm0             = 2U,          /**< TPM0 device trigger input */
+    kTRGMUX_Trgmux1Tpm3             = 2U,          /**< TPM3 device trigger input */
+    kTRGMUX_Trgmux0Tpm1             = 3U,          /**< TPM1 device trigger input */
+    kTRGMUX_Trgmux1Lpi2c3           = 3U,          /**< LPI2C3 device trigger input */
+    kTRGMUX_Trgmux0Tpm2             = 4U,          /**< TPM2 device trigger input */
+    kTRGMUX_Trgmux1Lpspi3           = 4U,          /**< LPSPI3 device trigger input */
+    kTRGMUX_Trgmux0Flexio0          = 5U,          /**< FLEXIO0 device trigger input */
+    kTRGMUX_Trgmux1Lpuart3          = 5U,          /**< LPUART3 device trigger input */
+    kTRGMUX_Trgmux0Lpi2c0           = 6U,          /**< LPI2C0 device trigger input */
+    kTRGMUX_Trgmux1Lpcmp1           = 6U,          /**< LPCMP1 device trigger input */
+    kTRGMUX_Trgmux0Lpi2c1           = 7U,          /**< LPI2C1 device trigger input */
+    kTRGMUX_Trgmux1Dmamux0          = 7U,          /**< DMAMUX0 device trigger input */
+    kTRGMUX_Trgmux0Lpi2c2           = 8U,          /**< LPI2C2 device trigger input */
+    kTRGMUX_Trgmux1Lpit0            = 8U,          /**< LPIT0 device trigger input */
+    kTRGMUX_Trgmux0Lpspi0           = 9U,          /**< LPSPI0 device trigger input */
+    kTRGMUX_Trgmux1Tpm0             = 9U,          /**< TPM0 device trigger input */
+    kTRGMUX_Trgmux0Lpspi1           = 10U,         /**< LPSPI1 device trigger input */
+    kTRGMUX_Trgmux1Tpm1             = 10U,         /**< TPM1 device trigger input */
+    kTRGMUX_Trgmux0Lpspi2           = 11U,         /**< LPSPI2 device trigger input */
+    kTRGMUX_Trgmux1Tpm2             = 11U,         /**< TPM2 device trigger input */
+    kTRGMUX_Trgmux0Lpuart0          = 12U,         /**< LPUART0 device trigger input */
+    kTRGMUX_Trgmux1Flexio0          = 12U,         /**< FLEXIO0 device trigger input */
+    kTRGMUX_Trgmux0Lpuart1          = 13U,         /**< LPUART1 device trigger input */
+    kTRGMUX_Trgmux1Lpi2c0           = 13U,         /**< LPI2C0 device trigger input */
+    kTRGMUX_Trgmux0Lpuart2          = 14U,         /**< LPUART2 device trigger input */
+    kTRGMUX_Trgmux1Lpi2c1           = 14U,         /**< LPI2C1 device trigger input */
+    kTRGMUX_Trgmux0Adc0             = 15U,         /**< ADC0 device trigger input */
+    kTRGMUX_Trgmux1Lpi2c2           = 15U,         /**< LPI2C2 device trigger input */
+    kTRGMUX_Trgmux0Lpcmp0           = 16U,         /**< LPCMP0 device trigger input */
+    kTRGMUX_Trgmux1Lpspi0           = 16U,         /**< LPSPI0 device trigger input */
+    kTRGMUX_Trgmux0Dac0             = 17U,         /**< DAC0 device trigger input */
+    kTRGMUX_Trgmux1Lpspi1           = 17U,         /**< LPSPI1 device trigger input */
+    kTRGMUX_Trgmux0Dmamux1          = 18U,         /**< DMAMUX1 device trigger input */
+    kTRGMUX_Trgmux1Lpspi2           = 18U,         /**< LPSPI2 device trigger input */
+    kTRGMUX_Trgmux0Lpit1            = 19U,         /**< LPIT1 device trigger input */
+    kTRGMUX_Trgmux1Lpuart0          = 19U,         /**< LPUART0 device trigger input */
+    kTRGMUX_Trgmux0Tpm3             = 20U,         /**< TPM3 device trigger input */
+    kTRGMUX_Trgmux1Lpuart1          = 20U,         /**< LPUART1 device trigger input */
+    kTRGMUX_Trgmux0Lpi2c3           = 21U,         /**< LPI2C3 device trigger input */
+    kTRGMUX_Trgmux1Lpuart2          = 21U,         /**< LPUART2 device trigger input */
+    kTRGMUX_Trgmux0Lpspi3           = 22U,         /**< LPSPI3 device trigger input */
+    kTRGMUX_Trgmux1Adc0             = 22U,         /**< ADC0 device trigger input */
+    kTRGMUX_Trgmux0Lpuart3          = 23U,         /**< LPUART3 device trigger input */
+    kTRGMUX_Trgmux1Lpcmp0           = 23U,         /**< LPCMP0 device trigger input */
+    kTRGMUX_Trgmux0Lpcmp1           = 24U,         /**< LPCMP1 device trigger input */
+    kTRGMUX_Trgmux1Lpdac0           = 24U,         /**< LPDAC0 device trigger input */
+} trgmux_device_t;
+
+/* @} */
+
+/*!
+ * @addtogroup xrdc_mapping
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the XRDC mapping
+ *
+ * Defines the structure for the XRDC resource collections.
+ */
+
+typedef enum _xrdc_master
+{
+    kXRDC_MasterCM4CodeBus          = 0U,          /**< CM4 C-BUS */
+    kXRDC_MasterCM4SystemBus        = 1U,          /**< CM4 S-BUS */
+    kXRDC_MasterRI5CYCodeBus        = 16U,         /**< RI5CY C-BUS */
+    kXRDC_MasterRI5CYSystemBus      = 17U,         /**< RI5CY S-BUS */
+    kXRDC_MasterEdma0               = 2U,          /**< EDMA0 */
+    kXRDC_MasterUsdhc               = 3U,          /**< USDHC */
+    kXRDC_MasterUsb                 = 4U,          /**< USB */
+    kXRDC_MasterCM0P                = 32U,         /**< CM0P */
+    kXRDC_MasterEdma1               = 33U,         /**< EDMA1 */
+    kXRDC_MasterCau3                = 34U,         /**< CAU3 */
+    kXRDC_MasterZERORISCYCodeBus    = 35U,         /**<  ZERO RISCY C-BUS */
+    kXRDC_MasterZERORISCYSystemBus  = 36U,         /**< ZERO RISCY S-BUS */
+} xrdc_master_t;
+
+/* @} */
+
+typedef enum _xrdc_mem
+{
+    kXRDC_MemMrc0_0                 = 0U,          /**< MRC0 Memory 0 */
+    kXRDC_MemMrc0_1                 = 1U,          /**< MRC0 Memory 1 */
+    kXRDC_MemMrc0_2                 = 2U,          /**< MRC0 Memory 2 */
+    kXRDC_MemMrc0_3                 = 3U,          /**< MRC0 Memory 3 */
+    kXRDC_MemMrc0_4                 = 4U,          /**< MRC0 Memory 4 */
+    kXRDC_MemMrc0_5                 = 5U,          /**< MRC0 Memory 5 */
+    kXRDC_MemMrc0_6                 = 6U,          /**< MRC0 Memory 6 */
+    kXRDC_MemMrc0_7                 = 7U,          /**< MRC0 Memory 7 */
+    kXRDC_MemMrc1_0                 = 16U,         /**< MRC1 Memory 0 */
+    kXRDC_MemMrc1_1                 = 17U,         /**< MRC1 Memory 1 */
+    kXRDC_MemMrc1_2                 = 18U,         /**< MRC1 Memory 2 */
+    kXRDC_MemMrc1_3                 = 19U,         /**< MRC1 Memory 3 */
+    kXRDC_MemMrc1_4                 = 20U,         /**< MRC1 Memory 4 */
+    kXRDC_MemMrc1_5                 = 21U,         /**< MRC1 Memory 5 */
+    kXRDC_MemMrc1_6                 = 22U,         /**< MRC1 Memory 6 */
+    kXRDC_MemMrc1_7                 = 23U,         /**< MRC1 Memory 7 */
+} xrdc_mem_t;
+
+typedef enum _xrdc_periph
+{
+    kXRDC_PeriphMscm                = 1U,          /**< Miscellaneous System Control Module (MSCM) */
+    kXRDC_PeriphDma0                = 8U,          /**< Direct Memory Access 0 (DMA0) controller */
+    kXRDC_PeriphDma0Tcd             = 9U,          /**< Direct Memory Access 0 (DMA0) controller transfer control descriptors */
+    kXRDC_PeriphFlexBus             = 12U,         /**< External Bus Interface(FlexBus) */
+    kXRDC_PeriphXrdcMgr             = 20U,         /**< Extended Resource Domain Controller (XRDC) MGR */
+    kXRDC_PeriphXrdcMdac            = 21U,         /**< Extended Resource Domain Controller (XRDC) MDAC */
+    kXRDC_PeriphXrdcPac             = 22U,         /**< Extended Resource Domain Controller (XRDC) PAC */
+    kXRDC_PeriphXrdcMrc             = 23U,         /**< Extended Resource Domain Controller (XRDC) MRC */
+    kXRDC_PeriphSema420             = 27U,         /**< Semaphore Unit 0 (SEMA420) */
+    kXRDC_PeriphCmc0                = 32U,         /**< Core Mode Controller (CMC) */
+    kXRDC_PeriphDmamux0             = 33U,         /**< Direct Memory Access Multiplexer 0 (DMAMUX0) */
+    kXRDC_PeriphEwm                 = 34U,         /**< External Watchdog Monitor (EWM) */
+    kXRDC_PeriphFtfe                = 35U,         /**< Flash Memory Module (FTFE) */
+    kXRDC_PeriphLlwu0               = 36U,         /**< Low Leakage Wake-up Unit 0 (LLWU0) */
+    kXRDC_PeriphMua                 = 37U,         /**< Message Unit Side A (MU-A) */
+    kXRDC_PeriphSim                 = 38U,         /**< System Integration Module (SIM) */
+    kXRDC_PeriphSimdgo              = 39U,         /**< System Integration Module - DGO (SIM-DGO) */
+    kXRDC_PeriphSpm                 = 40U,         /**< System Power Management (SPM) */
+    kXRDC_PeriphTrgmux0             = 41U,         /**< Tirgger Multiplexer 0 (TRGMUX0) */
+    kXRDC_PeriphWdog0               = 42U,         /**< Watchdog 0 (WDOG0) */
+    kXRDC_PeriphPcc0                = 43U,         /**< Peripheral Clock Controller 0 (PCC0) */
+    kXRDC_PeriphScg                 = 44U,         /**< System Clock Generator (SCG) */
+    kXRDC_PeriphSrf                 = 45U,         /**< System Register File */
+    kXRDC_PeriphVbat                = 46U,         /**< VBAT Register File */
+    kXRDC_PeriphCrc0                = 47U,         /**< Cyclic Redundancy Check 0 (CRC0) */
+    kXRDC_PeriphLpit0               = 48U,         /**< Low-Power Periodic Interrupt Timer 0 (LPIT0) */
+    kXRDC_PeriphRtc                 = 49U,         /**< Real Time Clock (RTC) */
+    kXRDC_PeriphLptmr0              = 50U,         /**< Low-Power Timer 0 (LPTMR0) */
+    kXRDC_PeriphLptmr1              = 51U,         /**< Low-Power Timer 1 (LPTMR1) */
+    kXRDC_PeriphTstmr0              = 52U,         /**< Time Stamp Timer 0 (TSTMR0) */
+    kXRDC_PeriphTpm0                = 53U,         /**< Timer / Pulse Width Modulator Module 0 (TPM0) - 6 channel */
+    kXRDC_PeriphTpm1                = 54U,         /**< Timer / Pulse Width Modulator Module 1 (TPM1) - 2 channel */
+    kXRDC_PeriphTpm2                = 55U,         /**< Timer / Pulse Width Modulator Module 2 (TPM2) - 6 channel */
+    kXRDC_PeriphEmvsim0             = 56U,         /**< Euro Mastercard Visa Secure Identity Module 0 (EMVSIM0) */
+    kXRDC_PeriphFlexio0             = 57U,         /**< Flexible Input / Output 0 (FlexIO0) */
+    kXRDC_PeriphLpi2c0              = 58U,         /**< Low-Power Inter-Integrated Circuit 0 (LPI2C0) */
+    kXRDC_PeriphLpi2c1              = 59U,         /**< Low-Power Inter-Integrated Circuit 1 (LPI2C1) */
+    kXRDC_PeriphLpi2c2              = 60U,         /**< Low-Power Inter-Integrated Circuit 2 (LPI2C2) */
+    kXRDC_PeriphSai0                = 61U,         /**< Serial Audio Interface 0 (SAI0) */
+    kXRDC_PeriphSdhc0               = 62U,         /**< Secure Digital Host Controller 0 (SDHC0) */
+    kXRDC_PeriphLpspi0              = 63U,         /**< Low-Power Serial Peripheral Interface 0 (LPSPI0) */
+    kXRDC_PeriphLpspi1              = 64U,         /**< Low-Power Serial Peripheral Interface 1 (LPSPI1) */
+    kXRDC_PeriphLpspi2              = 65U,         /**< Low-Power Serial Peripheral Interface 2 (LPSPI2) */
+    kXRDC_PeriphLpuart0             = 66U,         /**< Low-Power Universal Asynchronous Receive / Transmit 0 (LPUART0) */
+    kXRDC_PeriphLpuart1             = 67U,         /**< Low-Power Universal Asynchronous Receive / Transmit 1 (LPUART1) */
+    kXRDC_PeriphLpuart2             = 68U,         /**< Low-Power Universal Asynchronous Receive / Transmit 2 (LPUART2) */
+    kXRDC_PeriphUsb0                = 69U,         /**< Universal Serial Bus 0 (USB0) - Full Speed, Device Only */
+    kXRDC_PeriphPortA               = 70U,         /**< PORTA Multiplex Control */
+    kXRDC_PeriphPortB               = 71U,         /**< PORTB Multiplex Control */
+    kXRDC_PeriphPortC               = 72U,         /**< PORTC Multiplex Control */
+    kXRDC_PeriphPortD               = 73U,         /**< PORTD Multiplex Control */
+    kXRDC_PeriphLpadc0              = 74U,         /**< Low-Power Analog-to-Digital Converter 0 (LPADC0) */
+    kXRDC_PeriphLpcmp0              = 75U,         /**< Low-Power Comparator 0 (LPCMP0) */
+    kXRDC_PeriphDac0                = 76U,         /**< Digital-to-Analog Converter 0 (DAC0) */
+    kXRDC_PeriphVref                = 77U,         /**< Voltage Reference (VREF) */
+    kXRDC_PeriphDma1                = 136U,        /**< Direct Memory Access 1 (DMA1) controller */
+    kXRDC_PeriphDma1Tcd             = 137U,        /**< Direct Memory Access 1 (DMA1) controller trasfer control descriptors */
+    kXRDC_PeriphFgpio1              = 143U,        /**< IO Port Alias */
+    kXRDC_PeriphSema421             = 155U,        /**< Semaphore Unit 1 (SEMA421) */
+    kXRDC_PeriphCmc1                = 160U,        /**< Core Mode Controller (CMC) */
+    kXRDC_PeriphDmamux1             = 161U,        /**< Direct Memory Access Mutiplexer 1 (DMAMUX1) */
+    kXRDC_PeriphIntmux0             = 162U,        /**< Interrupt Multiplexer 0 (INTMUX0) */
+    kXRDC_Periphllwu1               = 163U,        /**< Low Leakage Wake-up Unit 1 (LLWU1) */
+    kXRDC_PeriphMub                 = 164U,        /**< Messaging Unit - Side B (MU-B) */
+    kXRDC_PeriphTrgmux1             = 165U,        /**< Trigger Multiplexer 1 (TRGMUX1) */
+    kXRDC_PeriphWdog1               = 166U,        /**< Watchdog 1 (WDOG1) */
+    kXRDC_PeriphPcc1                = 167U,        /**< Peripheral Clock Controller 1 (PCC1) */
+    kXRDC_PeriphCau3                = 168U,        /**< Cryptographic Acceleration Unit (CAU3) */
+    kXRDC_PeriphTrng                = 169U,        /**< True Random Number Generator (TRNG) */
+    kXRDC_PeriphLpit1               = 170U,        /**< Low-Power Periodic Interrupt Timer 1 (LPIT1) */
+    kXRDC_PeriphLptmr2              = 171U,        /**< Low-Power Timer 2 (LPTMR2) */
+    kXRDC_PeriphTstmr1              = 172U,        /**< Time Stamp Timer 1 (TSTMR1) */
+    kXRDC_PeriphTpm3                = 173U,        /**< Timer / Pulse Width Modulation Module 3 (TPM3) - 2 channel */
+    kXRDC_PeriphLpi2c3              = 174U,        /**< Low-Power Inter-Integrated Circuit 3 (LPI2C3) */
+    kXRDC_PeriphRsim                = 175U,        /**< 2.4GHz Radio (RF2.4G) - RSIM */
+    kXRDC_PeriphXcvr                = 176U,        /**< 2.4GHz Radio (RF2.4G) - XCVR */
+    kXRDC_PeriphAnt                 = 177U,        /**< 2.4GHz Radio (RF2.4G) - ANT+ Link Layer */
+    kXRDC_PeriphBle                 = 178U,        /**< 2.4GHz Radio (RF2.4G) - Bluetooth Link layer */
+    kXRDC_PeriphGfsk                = 179U,        /**< 2.4GHz Radio (RF2.4G) - Generic Link layer */
+    kXRDC_PeriphIeee                = 180U,        /**< 2.4GHz Radio (RF2.4G) - IEEE 802.15.4 Link Layer */
+    kXRDC_PeriphLpspi3              = 181U,        /**< Low-Power Serial Peripheral Interface 3 (LPSPI3) */
+    kXRDC_PeriphLpuart3             = 182U,        /**< Low-Power Universal Asynchronous Receive / Transmit 3 (LPUART3) */
+    kXRDC_PeriphPortE               = 183U,        /**< PORTE Multiplex Control */
+    kXRDC_PeriphLpcmp1              = 214U,        /**< Low-Power Comparator 1 (LPCMP1) */
+} xrdc_periph_t;
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t CTRL;                              /**< ADC Control Register, offset: 0x10 */
+  __IO uint32_t STAT;                              /**< ADC Status Register, offset: 0x14 */
+  __IO uint32_t IE;                                /**< Interrupt Enable Register, offset: 0x18 */
+  __IO uint32_t DE;                                /**< DMA Enable Register, offset: 0x1C */
+  __IO uint32_t CFG;                               /**< ADC Configuration Register, offset: 0x20 */
+  __IO uint32_t PAUSE;                             /**< ADC Pause Register, offset: 0x24 */
+       uint8_t RESERVED_1[8];
+  __IO uint32_t FCTRL;                             /**< ADC FIFO Control Register, offset: 0x30 */
+  __O  uint32_t SWTRIG;                            /**< Software Trigger Register, offset: 0x34 */
+       uint8_t RESERVED_2[8];
+  __IO uint32_t OFSTRIM;                           /**< ADC Offset Trim Register, offset: 0x40 */
+       uint8_t RESERVED_3[124];
+  __IO uint32_t TCTRL[4];                          /**< Trigger Control Register, array offset: 0xC0, array step: 0x4 */
+       uint8_t RESERVED_4[48];
+  struct {                                         /* offset: 0x100, array step: 0x8 */
+    __IO uint32_t CMDL;                              /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
+    __IO uint32_t CMDH;                              /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
+  } CMD[15];
+       uint8_t RESERVED_5[136];
+  __IO uint32_t CV[4];                             /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
+       uint8_t RESERVED_6[240];
+  __I  uint32_t RESFIFO;                           /**< ADC Data Result FIFO Register, offset: 0x300 */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define ADC_VERID_RES_MASK                       (0x1U)
+#define ADC_VERID_RES_SHIFT                      (0U)
+/*! RES - Resolution
+ *  0b0..Up to 13-bit differential/12-bit single ended resolution supported.
+ *  0b1..Up to 16-bit differential/15-bit single ended resolution supported.
+ */
+#define ADC_VERID_RES(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
+#define ADC_VERID_DIFFEN_MASK                    (0x2U)
+#define ADC_VERID_DIFFEN_SHIFT                   (1U)
+/*! DIFFEN - Differential Supported
+ *  0b0..Differential operation not supported.
+ *  0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented.
+ */
+#define ADC_VERID_DIFFEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
+#define ADC_VERID_MVI_MASK                       (0x8U)
+#define ADC_VERID_MVI_SHIFT                      (3U)
+/*! MVI - Multi Vref Implemented
+ *  0b0..Single voltage reference high (VREFH) input supported.
+ *  0b1..Multiple voltage reference high (VREFH) inputs supported.
+ */
+#define ADC_VERID_MVI(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
+#define ADC_VERID_CSW_MASK                       (0x70U)
+#define ADC_VERID_CSW_SHIFT                      (4U)
+/*! CSW - Channel Scale Width
+ *  0b000..Channel scaling not supported.
+ *  0b001..Channel scaling supported. 1-bit CSCALE control field.
+ *  0b110..Channel scaling supported. 6-bit CSCALE control field.
+ */
+#define ADC_VERID_CSW(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
+#define ADC_VERID_VR1RNGI_MASK                   (0x100U)
+#define ADC_VERID_VR1RNGI_SHIFT                  (8U)
+/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
+ *  0b0..Range control not required. CFG[VREF1RNG] is not implemented.
+ *  0b1..Range control required. CFG[VREF1RNG] is implemented.
+ */
+#define ADC_VERID_VR1RNGI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
+#define ADC_VERID_IADCKI_MASK                    (0x200U)
+#define ADC_VERID_IADCKI_SHIFT                   (9U)
+/*! IADCKI - Internal ADC Clock implemented
+ *  0b0..Internal clock source not implemented.
+ *  0b1..Internal clock source (and CFG[ADCKEN]) implemented.
+ */
+#define ADC_VERID_IADCKI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
+#define ADC_VERID_CALOFSI_MASK                   (0x400U)
+#define ADC_VERID_CALOFSI_SHIFT                  (10U)
+/*! CALOFSI - Calibration Offset Function Implemented
+ *  0b0..Offset calibration and offset trimming not implemented.
+ *  0b1..Offset calibration and offset trimming implemented.
+ */
+#define ADC_VERID_CALOFSI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
+#define ADC_VERID_MINOR_MASK                     (0xFF0000U)
+#define ADC_VERID_MINOR_SHIFT                    (16U)
+#define ADC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
+#define ADC_VERID_MAJOR_MASK                     (0xFF000000U)
+#define ADC_VERID_MAJOR_SHIFT                    (24U)
+#define ADC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define ADC_PARAM_TRIG_NUM_MASK                  (0xFFU)
+#define ADC_PARAM_TRIG_NUM_SHIFT                 (0U)
+#define ADC_PARAM_TRIG_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
+#define ADC_PARAM_FIFOSIZE_MASK                  (0xFF00U)
+#define ADC_PARAM_FIFOSIZE_SHIFT                 (8U)
+/*! FIFOSIZE - Result FIFO Depth
+ *  0b00000001..Result FIFO depth = 1 dataword.
+ *  0b00000100..Result FIFO depth = 4 datawords.
+ *  0b00001000..Result FIFO depth = 8 datawords.
+ *  0b00010000..Result FIFO depth = 16 datawords.
+ *  0b00100000..Result FIFO depth = 32 datawords.
+ *  0b01000000..Result FIFO depth = 64 datawords.
+ */
+#define ADC_PARAM_FIFOSIZE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
+#define ADC_PARAM_CV_NUM_MASK                    (0xFF0000U)
+#define ADC_PARAM_CV_NUM_SHIFT                   (16U)
+#define ADC_PARAM_CV_NUM(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
+#define ADC_PARAM_CMD_NUM_MASK                   (0xFF000000U)
+#define ADC_PARAM_CMD_NUM_SHIFT                  (24U)
+#define ADC_PARAM_CMD_NUM(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
+/*! @} */
+
+/*! @name CTRL - ADC Control Register */
+/*! @{ */
+#define ADC_CTRL_ADCEN_MASK                      (0x1U)
+#define ADC_CTRL_ADCEN_SHIFT                     (0U)
+/*! ADCEN - ADC Enable
+ *  0b0..ADC is disabled.
+ *  0b1..ADC is enabled.
+ */
+#define ADC_CTRL_ADCEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
+#define ADC_CTRL_RST_MASK                        (0x2U)
+#define ADC_CTRL_RST_SHIFT                       (1U)
+/*! RST - Software Reset
+ *  0b0..ADC logic is not reset.
+ *  0b1..ADC logic is reset.
+ */
+#define ADC_CTRL_RST(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
+#define ADC_CTRL_DOZEN_MASK                      (0x4U)
+#define ADC_CTRL_DOZEN_SHIFT                     (2U)
+/*! DOZEN - Doze Enable
+ *  0b0..ADC is enabled in Doze mode.
+ *  0b1..ADC is disabled in Doze mode.
+ */
+#define ADC_CTRL_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
+#define ADC_CTRL_RSTFIFO_MASK                    (0x100U)
+#define ADC_CTRL_RSTFIFO_SHIFT                   (8U)
+/*! RSTFIFO - Reset FIFO
+ *  0b0..No effect.
+ *  0b1..FIFO is reset.
+ */
+#define ADC_CTRL_RSTFIFO(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK)
+/*! @} */
+
+/*! @name STAT - ADC Status Register */
+/*! @{ */
+#define ADC_STAT_RDY_MASK                        (0x1U)
+#define ADC_STAT_RDY_SHIFT                       (0U)
+/*! RDY - Result FIFO Ready Flag
+ *  0b0..Result FIFO data level not above watermark level.
+ *  0b1..Result FIFO holding data above watermark level.
+ */
+#define ADC_STAT_RDY(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK)
+#define ADC_STAT_FOF_MASK                        (0x2U)
+#define ADC_STAT_FOF_SHIFT                       (1U)
+/*! FOF - Result FIFO Overflow Flag
+ *  0b0..No result FIFO overflow has occurred since the last time the flag was cleared.
+ *  0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared.
+ */
+#define ADC_STAT_FOF(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK)
+#define ADC_STAT_TRGACT_MASK                     (0x30000U)
+#define ADC_STAT_TRGACT_SHIFT                    (16U)
+/*! TRGACT - Trigger Active
+ *  0b00..Command (sequence) associated with Trigger 0 currently being executed.
+ *  0b01..Command (sequence) associated with Trigger 1 currently being executed.
+ *  0b10..Command (sequence) associated with Trigger 2 currently being executed.
+ *  0b11..Command (sequence) associated with Trigger 3 currently being executed.
+ */
+#define ADC_STAT_TRGACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
+#define ADC_STAT_CMDACT_MASK                     (0xF000000U)
+#define ADC_STAT_CMDACT_SHIFT                    (24U)
+/*! CMDACT - Command Active
+ *  0b0000..No command is currently in progress.
+ *  0b0001..Command 1 currently being executed.
+ *  0b0010..Command 2 currently being executed.
+ *  0b0011-0b1111..Associated command number is currently being executed.
+ */
+#define ADC_STAT_CMDACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
+/*! @} */
+
+/*! @name IE - Interrupt Enable Register */
+/*! @{ */
+#define ADC_IE_FWMIE_MASK                        (0x1U)
+#define ADC_IE_FWMIE_SHIFT                       (0U)
+/*! FWMIE - FIFO Watermark Interrupt Enable
+ *  0b0..FIFO watermark interrupts are not enabled.
+ *  0b1..FIFO watermark interrupts are enabled.
+ */
+#define ADC_IE_FWMIE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK)
+#define ADC_IE_FOFIE_MASK                        (0x2U)
+#define ADC_IE_FOFIE_SHIFT                       (1U)
+/*! FOFIE - Result FIFO Overflow Interrupt Enable
+ *  0b0..FIFO overflow interrupts are not enabled.
+ *  0b1..FIFO overflow interrupts are enabled.
+ */
+#define ADC_IE_FOFIE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK)
+/*! @} */
+
+/*! @name DE - DMA Enable Register */
+/*! @{ */
+#define ADC_DE_FWMDE_MASK                        (0x1U)
+#define ADC_DE_FWMDE_SHIFT                       (0U)
+/*! FWMDE - FIFO Watermark DMA Enable
+ *  0b0..DMA request disabled.
+ *  0b1..DMA request enabled.
+ */
+#define ADC_DE_FWMDE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK)
+/*! @} */
+
+/*! @name CFG - ADC Configuration Register */
+/*! @{ */
+#define ADC_CFG_TPRICTRL_MASK                    (0x1U)
+#define ADC_CFG_TPRICTRL_SHIFT                   (0U)
+/*! TPRICTRL - ADC trigger priority control
+ *  0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started.
+ *  0b1..If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true conversion.
+ */
+#define ADC_CFG_TPRICTRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
+#define ADC_CFG_PWRSEL_MASK                      (0x30U)
+#define ADC_CFG_PWRSEL_SHIFT                     (4U)
+/*! PWRSEL - Power Configuration Select
+ *  0b00..Level 1 (Lowest power setting)
+ *  0b01..Level 2
+ *  0b10..Level 3
+ *  0b11..Level 4 (Highest power setting)
+ */
+#define ADC_CFG_PWRSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
+#define ADC_CFG_REFSEL_MASK                      (0xC0U)
+#define ADC_CFG_REFSEL_SHIFT                     (6U)
+/*! REFSEL - Voltage Reference Selection
+ *  0b00..(Default) Option 1 setting.
+ *  0b01..Option 2 setting.
+ *  0b10..Option 3 setting.
+ *  0b11..Reserved
+ */
+#define ADC_CFG_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
+#define ADC_CFG_CALOFS_MASK                      (0x8000U)
+#define ADC_CFG_CALOFS_SHIFT                     (15U)
+/*! CALOFS - Configure for offset calibration function
+ *  0b0..Calibration function disabled
+ *  0b1..Configure for offset calibration function
+ */
+#define ADC_CFG_CALOFS(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_CALOFS_SHIFT)) & ADC_CFG_CALOFS_MASK)
+#define ADC_CFG_PUDLY_MASK                       (0xFF0000U)
+#define ADC_CFG_PUDLY_SHIFT                      (16U)
+#define ADC_CFG_PUDLY(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
+#define ADC_CFG_PWREN_MASK                       (0x10000000U)
+#define ADC_CFG_PWREN_SHIFT                      (28U)
+/*! PWREN - ADC Analog Pre-Enable
+ *  0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
+ *  0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any detected trigger does not begin ADC operation until the power up delay time has passed.
+ */
+#define ADC_CFG_PWREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
+#define ADC_CFG_VREF1RNG_MASK                    (0x20000000U)
+#define ADC_CFG_VREF1RNG_SHIFT                   (29U)
+/*! VREF1RNG - Enable support for low voltage reference on Option 1 Reference
+ *  0b0..Configuration required when Voltage Reference Option 1 input is in high voltage range
+ *  0b1..Configuration required when Voltage Reference Option 1 input is in low voltage range
+ */
+#define ADC_CFG_VREF1RNG(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_VREF1RNG_SHIFT)) & ADC_CFG_VREF1RNG_MASK)
+#define ADC_CFG_ADCKEN_MASK                      (0x80000000U)
+#define ADC_CFG_ADCKEN_SHIFT                     (31U)
+/*! ADCKEN - ADC asynchronous clock enable
+ *  0b0..ADC internal clock is disabled
+ *  0b1..ADC internal clock is enabled
+ */
+#define ADC_CFG_ADCKEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADCKEN_SHIFT)) & ADC_CFG_ADCKEN_MASK)
+/*! @} */
+
+/*! @name PAUSE - ADC Pause Register */
+/*! @{ */
+#define ADC_PAUSE_PAUSEDLY_MASK                  (0x1FFU)
+#define ADC_PAUSE_PAUSEDLY_SHIFT                 (0U)
+#define ADC_PAUSE_PAUSEDLY(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
+#define ADC_PAUSE_PAUSEEN_MASK                   (0x80000000U)
+#define ADC_PAUSE_PAUSEEN_SHIFT                  (31U)
+/*! PAUSEEN - PAUSE Option Enable
+ *  0b0..Pause operation disabled
+ *  0b1..Pause operation enabled
+ */
+#define ADC_PAUSE_PAUSEEN(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
+/*! @} */
+
+/*! @name FCTRL - ADC FIFO Control Register */
+/*! @{ */
+#define ADC_FCTRL_FCOUNT_MASK                    (0x1FU)
+#define ADC_FCTRL_FCOUNT_SHIFT                   (0U)
+#define ADC_FCTRL_FCOUNT(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
+#define ADC_FCTRL_FWMARK_MASK                    (0xF0000U)
+#define ADC_FCTRL_FWMARK_SHIFT                   (16U)
+#define ADC_FCTRL_FWMARK(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
+/*! @} */
+
+/*! @name SWTRIG - Software Trigger Register */
+/*! @{ */
+#define ADC_SWTRIG_SWT0_MASK                     (0x1U)
+#define ADC_SWTRIG_SWT0_SHIFT                    (0U)
+/*! SWT0 - Software trigger 0 event
+ *  0b0..No trigger 0 event generated.
+ *  0b1..Trigger 0 event generated.
+ */
+#define ADC_SWTRIG_SWT0(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
+#define ADC_SWTRIG_SWT1_MASK                     (0x2U)
+#define ADC_SWTRIG_SWT1_SHIFT                    (1U)
+/*! SWT1 - Software trigger 1 event
+ *  0b0..No trigger 1 event generated.
+ *  0b1..Trigger 1 event generated.
+ */
+#define ADC_SWTRIG_SWT1(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
+#define ADC_SWTRIG_SWT2_MASK                     (0x4U)
+#define ADC_SWTRIG_SWT2_SHIFT                    (2U)
+/*! SWT2 - Software trigger 2 event
+ *  0b0..No trigger 2 event generated.
+ *  0b1..Trigger 2 event generated.
+ */
+#define ADC_SWTRIG_SWT2(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
+#define ADC_SWTRIG_SWT3_MASK                     (0x8U)
+#define ADC_SWTRIG_SWT3_SHIFT                    (3U)
+/*! SWT3 - Software trigger 3 event
+ *  0b0..No trigger 3 event generated.
+ *  0b1..Trigger 3 event generated.
+ */
+#define ADC_SWTRIG_SWT3(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
+/*! @} */
+
+/*! @name OFSTRIM - ADC Offset Trim Register */
+/*! @{ */
+#define ADC_OFSTRIM_OFSTRIM_MASK                 (0x3FU)
+#define ADC_OFSTRIM_OFSTRIM_SHIFT                (0U)
+#define ADC_OFSTRIM_OFSTRIM(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_SHIFT)) & ADC_OFSTRIM_OFSTRIM_MASK)
+/*! @} */
+
+/*! @name TCTRL - Trigger Control Register */
+/*! @{ */
+#define ADC_TCTRL_HTEN_MASK                      (0x1U)
+#define ADC_TCTRL_HTEN_SHIFT                     (0U)
+/*! HTEN - Trigger enable
+ *  0b0..Hardware trigger source disabled
+ *  0b1..Hardware trigger source enabled
+ */
+#define ADC_TCTRL_HTEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
+#define ADC_TCTRL_TPRI_MASK                      (0x300U)
+#define ADC_TCTRL_TPRI_SHIFT                     (8U)
+/*! TPRI - Trigger priority setting
+ *  0b00..Set to highest priority, Level 1
+ *  0b01-0b10..Set to corresponding priority level
+ *  0b11..Set to lowest priority, Level 4
+ */
+#define ADC_TCTRL_TPRI(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
+#define ADC_TCTRL_TDLY_MASK                      (0xF0000U)
+#define ADC_TCTRL_TDLY_SHIFT                     (16U)
+#define ADC_TCTRL_TDLY(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
+#define ADC_TCTRL_TCMD_MASK                      (0xF000000U)
+#define ADC_TCTRL_TCMD_SHIFT                     (24U)
+/*! TCMD - Trigger command select
+ *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
+ *  0b0001..CMD1 is executed
+ *  0b0010-0b1110..Corresponding CMD is executed
+ *  0b1111..CMD15 is executed
+ */
+#define ADC_TCTRL_TCMD(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
+/*! @} */
+
+/* The count of ADC_TCTRL */
+#define ADC_TCTRL_COUNT                          (4U)
+
+/*! @name CMDL - ADC Command Low Buffer Register */
+/*! @{ */
+#define ADC_CMDL_ADCH_MASK                       (0x1FU)
+#define ADC_CMDL_ADCH_SHIFT                      (0U)
+/*! ADCH - Input channel select
+ *  0b00000..Select CH0A or CH0B
+ *  0b00001..Select CH1A or CH1B
+ *  0b00010..Select CH2A or CH2B
+ *  0b00011..Select CH3A or CH3B
+ *  0b00100-0b11101..Select corresponding channel CHnA or CHnB
+ *  0b11110..Select CH30A or CH30B
+ *  0b11111..Select CH31A or CH31B
+ */
+#define ADC_CMDL_ADCH(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
+#define ADC_CMDL_ABSEL_MASK                      (0x20U)
+#define ADC_CMDL_ABSEL_SHIFT                     (5U)
+/*! ABSEL - A-side vs. B-side Select
+ *  0b0..The associated A-side channel is converted.
+ *  0b1..The associated B-side channel is converted.
+ */
+#define ADC_CMDL_ABSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)
+/*! @} */
+
+/* The count of ADC_CMDL */
+#define ADC_CMDL_COUNT                           (15U)
+
+/*! @name CMDH - ADC Command High Buffer Register */
+/*! @{ */
+#define ADC_CMDH_CMPEN_MASK                      (0x3U)
+#define ADC_CMDH_CMPEN_SHIFT                     (0U)
+/*! CMPEN - Compare Function Enable
+ *  0b00..Compare disabled.
+ *  0b01..Reserved
+ *  0b10..Compare enabled. Store on true.
+ *  0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
+ */
+#define ADC_CMDH_CMPEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
+#define ADC_CMDH_LWI_MASK                        (0x80U)
+#define ADC_CMDH_LWI_SHIFT                       (7U)
+/*! LWI - Loop with Increment
+ *  0b0..Auto channel increment disabled
+ *  0b1..Auto channel increment enabled
+ */
+#define ADC_CMDH_LWI(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
+#define ADC_CMDH_STS_MASK                        (0x700U)
+#define ADC_CMDH_STS_SHIFT                       (8U)
+/*! STS - Sample Time Select
+ *  0b000..Minimum sample time of 3 ADCK cycles.
+ *  0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
+ *  0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
+ *  0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
+ *  0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
+ *  0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
+ *  0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
+ *  0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
+ */
+#define ADC_CMDH_STS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
+#define ADC_CMDH_AVGS_MASK                       (0x7000U)
+#define ADC_CMDH_AVGS_SHIFT                      (12U)
+/*! AVGS - Hardware Average Select
+ *  0b000..Single conversion.
+ *  0b001..2 conversions averaged.
+ *  0b010..4 conversions averaged.
+ *  0b011..8 conversions averaged.
+ *  0b100..16 conversions averaged.
+ *  0b101..32 conversions averaged.
+ *  0b110..64 conversions averaged.
+ *  0b111..128 conversions averaged.
+ */
+#define ADC_CMDH_AVGS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
+#define ADC_CMDH_LOOP_MASK                       (0xF0000U)
+#define ADC_CMDH_LOOP_SHIFT                      (16U)
+/*! LOOP - Loop Count Select
+ *  0b0000..Looping not enabled. Command executes 1 time.
+ *  0b0001..Loop 1 time. Command executes 2 times.
+ *  0b0010..Loop 2 times. Command executes 3 times.
+ *  0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
+ *  0b1111..Loop 15 times. Command executes 16 times.
+ */
+#define ADC_CMDH_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
+#define ADC_CMDH_NEXT_MASK                       (0xF000000U)
+#define ADC_CMDH_NEXT_SHIFT                      (24U)
+/*! NEXT - Next Command Select
+ *  0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
+ *  0b0001..Select CMD1 command buffer register as next command.
+ *  0b0010-0b1110..Select corresponding CMD command buffer register as next command
+ *  0b1111..Select CMD15 command buffer register as next command.
+ */
+#define ADC_CMDH_NEXT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
+/*! @} */
+
+/* The count of ADC_CMDH */
+#define ADC_CMDH_COUNT                           (15U)
+
+/*! @name CV - Compare Value Register */
+/*! @{ */
+#define ADC_CV_CVL_MASK                          (0xFFFFU)
+#define ADC_CV_CVL_SHIFT                         (0U)
+#define ADC_CV_CVL(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
+#define ADC_CV_CVH_MASK                          (0xFFFF0000U)
+#define ADC_CV_CVH_SHIFT                         (16U)
+#define ADC_CV_CVH(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
+/*! @} */
+
+/* The count of ADC_CV */
+#define ADC_CV_COUNT                             (4U)
+
+/*! @name RESFIFO - ADC Data Result FIFO Register */
+/*! @{ */
+#define ADC_RESFIFO_D_MASK                       (0xFFFFU)
+#define ADC_RESFIFO_D_SHIFT                      (0U)
+#define ADC_RESFIFO_D(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
+#define ADC_RESFIFO_TSRC_MASK                    (0x30000U)
+#define ADC_RESFIFO_TSRC_SHIFT                   (16U)
+/*! TSRC - Trigger Source
+ *  0b00..Trigger source 0 initiated this conversion.
+ *  0b01..Trigger source 1 initiated this conversion.
+ *  0b10..Trigger source 2 initiated this conversion.
+ *  0b11..Trigger source 3 initiated this conversion.
+ */
+#define ADC_RESFIFO_TSRC(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
+#define ADC_RESFIFO_LOOPCNT_MASK                 (0xF00000U)
+#define ADC_RESFIFO_LOOPCNT_SHIFT                (20U)
+/*! LOOPCNT - Loop count value
+ *  0b0000..Result is from initial conversion in command.
+ *  0b0001..Result is from second conversion in command.
+ *  0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
+ *  0b1111..Result is from 16th conversion in command.
+ */
+#define ADC_RESFIFO_LOOPCNT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
+#define ADC_RESFIFO_CMDSRC_MASK                  (0xF000000U)
+#define ADC_RESFIFO_CMDSRC_SHIFT                 (24U)
+/*! CMDSRC - Command Buffer Source
+ *  0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
+ *  0b0001..CMD1 buffer used as control settings for this conversion.
+ *  0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
+ *  0b1111..CMD15 buffer used as control settings for this conversion.
+ */
+#define ADC_RESFIFO_CMDSRC(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
+#define ADC_RESFIFO_VALID_MASK                   (0x80000000U)
+#define ADC_RESFIFO_VALID_SHIFT                  (31U)
+/*! VALID - FIFO entry is valid
+ *  0b0..FIFO is empty. Discard any read from RESFIFO.
+ *  0b1..FIFO record read from RESFIFO is valid.
+ */
+#define ADC_RESFIFO_VALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x4004A000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS                           { ADC0_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS                            { ADC0 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS                                 { ADC0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AXBS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
+ * @{
+ */
+
+/** AXBS - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x100 */
+    __IO uint32_t PRS;                               /**< Priority Slave Registers, array offset: 0x0, array step: 0x100 */
+         uint8_t RESERVED_0[12];
+    __IO uint32_t CRS;                               /**< Control Register, array offset: 0x10, array step: 0x100 */
+         uint8_t RESERVED_1[236];
+  } SLAVE[5];
+       uint8_t RESERVED_0[768];
+  __IO uint32_t MGPCR0;                            /**< Master General Purpose Control Register, offset: 0x800 */
+       uint8_t RESERVED_1[252];
+  __IO uint32_t MGPCR1;                            /**< Master General Purpose Control Register, offset: 0x900 */
+       uint8_t RESERVED_2[252];
+  __IO uint32_t MGPCR2;                            /**< Master General Purpose Control Register, offset: 0xA00 */
+       uint8_t RESERVED_3[252];
+  __IO uint32_t MGPCR3;                            /**< Master General Purpose Control Register, offset: 0xB00 */
+       uint8_t RESERVED_4[252];
+  __IO uint32_t MGPCR4;                            /**< Master General Purpose Control Register, offset: 0xC00 */
+       uint8_t RESERVED_5[252];
+  __IO uint32_t MGPCR5;                            /**< Master General Purpose Control Register, offset: 0xD00 */
+} AXBS_Type;
+
+/* ----------------------------------------------------------------------------
+   -- AXBS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Masks AXBS Register Masks
+ * @{
+ */
+
+/*! @name PRS - Priority Slave Registers */
+/*! @{ */
+#define AXBS_PRS_M0_MASK                         (0x7U)
+#define AXBS_PRS_M0_SHIFT                        (0U)
+/*! M0 - Master 0 Priority. Sets the arbitration priority for this port on the associated slave port.
+ *  0b000..This master has level 1, or highest, priority when accessing the slave port.
+ *  0b001..This master has level 2 priority when accessing the slave port.
+ *  0b010..This master has level 3 priority when accessing the slave port.
+ *  0b011..This master has level 4 priority when accessing the slave port.
+ *  0b100..This master has level 5 priority when accessing the slave port.
+ *  0b101..This master has level 6 priority when accessing the slave port.
+ *  0b110..This master has level 7 priority when accessing the slave port.
+ *  0b111..This master has level 8, or lowest, priority when accessing the slave port.
+ */
+#define AXBS_PRS_M0(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
+#define AXBS_PRS_M1_MASK                         (0x70U)
+#define AXBS_PRS_M1_SHIFT                        (4U)
+/*! M1 - Master 1 Priority. Sets the arbitration priority for this port on the associated slave port.
+ *  0b000..This master has level 1, or highest, priority when accessing the slave port.
+ *  0b001..This master has level 2 priority when accessing the slave port.
+ *  0b010..This master has level 3 priority when accessing the slave port.
+ *  0b011..This master has level 4 priority when accessing the slave port.
+ *  0b100..This master has level 5 priority when accessing the slave port.
+ *  0b101..This master has level 6 priority when accessing the slave port.
+ *  0b110..This master has level 7 priority when accessing the slave port.
+ *  0b111..This master has level 8, or lowest, priority when accessing the slave port.
+ */
+#define AXBS_PRS_M1(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
+#define AXBS_PRS_M2_MASK                         (0x700U)
+#define AXBS_PRS_M2_SHIFT                        (8U)
+/*! M2 - Master 2 Priority. Sets the arbitration priority for this port on the associated slave port.
+ *  0b000..This master has level 1, or highest, priority when accessing the slave port.
+ *  0b001..This master has level 2 priority when accessing the slave port.
+ *  0b010..This master has level 3 priority when accessing the slave port.
+ *  0b011..This master has level 4 priority when accessing the slave port.
+ *  0b100..This master has level 5 priority when accessing the slave port.
+ *  0b101..This master has level 6 priority when accessing the slave port.
+ *  0b110..This master has level 7 priority when accessing the slave port.
+ *  0b111..This master has level 8, or lowest, priority when accessing the slave port.
+ */
+#define AXBS_PRS_M2(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
+#define AXBS_PRS_M3_MASK                         (0x7000U)
+#define AXBS_PRS_M3_SHIFT                        (12U)
+/*! M3 - Master 3 Priority. Sets the arbitration priority for this port on the associated slave port.
+ *  0b000..This master has level 1, or highest, priority when accessing the slave port.
+ *  0b001..This master has level 2 priority when accessing the slave port.
+ *  0b010..This master has level 3 priority when accessing the slave port.
+ *  0b011..This master has level 4 priority when accessing the slave port.
+ *  0b100..This master has level 5 priority when accessing the slave port.
+ *  0b101..This master has level 6 priority when accessing the slave port.
+ *  0b110..This master has level 7 priority when accessing the slave port.
+ *  0b111..This master has level 8, or lowest, priority when accessing the slave port.
+ */
+#define AXBS_PRS_M3(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
+#define AXBS_PRS_M4_MASK                         (0x70000U)
+#define AXBS_PRS_M4_SHIFT                        (16U)
+/*! M4 - Master 4 Priority. Sets the arbitration priority for this port on the associated slave port.
+ *  0b000..This master has level 1, or highest, priority when accessing the slave port.
+ *  0b001..This master has level 2 priority when accessing the slave port.
+ *  0b010..This master has level 3 priority when accessing the slave port.
+ *  0b011..This master has level 4 priority when accessing the slave port.
+ *  0b100..This master has level 5 priority when accessing the slave port.
+ *  0b101..This master has level 6 priority when accessing the slave port.
+ *  0b110..This master has level 7 priority when accessing the slave port.
+ *  0b111..This master has level 8, or lowest, priority when accessing the slave port.
+ */
+#define AXBS_PRS_M4(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
+#define AXBS_PRS_M5_MASK                         (0x700000U)
+#define AXBS_PRS_M5_SHIFT                        (20U)
+/*! M5 - Master 5 Priority. Sets the arbitration priority for this port on the associated slave port.
+ *  0b000..This master has level 1, or highest, priority when accessing the slave port.
+ *  0b001..This master has level 2 priority when accessing the slave port.
+ *  0b010..This master has level 3 priority when accessing the slave port.
+ *  0b011..This master has level 4 priority when accessing the slave port.
+ *  0b100..This master has level 5 priority when accessing the slave port.
+ *  0b101..This master has level 6 priority when accessing the slave port.
+ *  0b110..This master has level 7 priority when accessing the slave port.
+ *  0b111..This master has level 8, or lowest, priority when accessing the slave port.
+ */
+#define AXBS_PRS_M5(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
+/*! @} */
+
+/* The count of AXBS_PRS */
+#define AXBS_PRS_COUNT                           (5U)
+
+/*! @name CRS - Control Register */
+/*! @{ */
+#define AXBS_CRS_PARK_MASK                       (0x7U)
+#define AXBS_CRS_PARK_SHIFT                      (0U)
+/*! PARK - Park
+ *  0b000..Park on master port M0
+ *  0b001..Park on master port M1
+ *  0b010..Park on master port M2
+ *  0b011..Park on master port M3
+ *  0b100..Park on master port M4
+ *  0b101..Park on master port M5
+ *  0b110..Park on master port M6
+ *  0b111..Park on master port M7
+ */
+#define AXBS_CRS_PARK(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
+#define AXBS_CRS_PCTL_MASK                       (0x30U)
+#define AXBS_CRS_PCTL_SHIFT                      (4U)
+/*! PCTL - Parking Control
+ *  0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field
+ *  0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port
+ *  0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state
+ *  0b11..Reserved
+ */
+#define AXBS_CRS_PCTL(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
+#define AXBS_CRS_ARB_MASK                        (0x300U)
+#define AXBS_CRS_ARB_SHIFT                       (8U)
+/*! ARB - Arbitration Mode
+ *  0b00..Fixed priority
+ *  0b01..Round-robin, or rotating, priority
+ *  0b10..Reserved
+ *  0b11..Reserved
+ */
+#define AXBS_CRS_ARB(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
+#define AXBS_CRS_HLP_MASK                        (0x40000000U)
+#define AXBS_CRS_HLP_SHIFT                       (30U)
+/*! HLP - Halt Low Priority
+ *  0b0..The low power mode request has the highest priority for arbitration on this slave port
+ *  0b1..The low power mode request has the lowest initial priority for arbitration on this slave port
+ */
+#define AXBS_CRS_HLP(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
+#define AXBS_CRS_RO_MASK                         (0x80000000U)
+#define AXBS_CRS_RO_SHIFT                        (31U)
+/*! RO - Read Only
+ *  0b0..The slave port's registers are writeable
+ *  0b1..The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response.
+ */
+#define AXBS_CRS_RO(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
+/*! @} */
+
+/* The count of AXBS_CRS */
+#define AXBS_CRS_COUNT                           (5U)
+
+/*! @name MGPCR0 - Master General Purpose Control Register */
+/*! @{ */
+#define AXBS_MGPCR0_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR0_AULB_SHIFT                   (0U)
+/*! AULB - Arbitrates On Undefined Length Bursts
+ *  0b000..No arbitration is allowed during an undefined length burst
+ *  0b001..Arbitration is allowed at any time during an undefined length burst
+ *  0b010..Arbitration is allowed after four beats of an undefined length burst
+ *  0b011..Arbitration is allowed after eight beats of an undefined length burst
+ *  0b100..Arbitration is allowed after 16 beats of an undefined length burst
+ *  0b101..Reserved
+ *  0b110..Reserved
+ *  0b111..Reserved
+ */
+#define AXBS_MGPCR0_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
+/*! @} */
+
+/*! @name MGPCR1 - Master General Purpose Control Register */
+/*! @{ */
+#define AXBS_MGPCR1_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR1_AULB_SHIFT                   (0U)
+/*! AULB - Arbitrates On Undefined Length Bursts
+ *  0b000..No arbitration is allowed during an undefined length burst
+ *  0b001..Arbitration is allowed at any time during an undefined length burst
+ *  0b010..Arbitration is allowed after four beats of an undefined length burst
+ *  0b011..Arbitration is allowed after eight beats of an undefined length burst
+ *  0b100..Arbitration is allowed after 16 beats of an undefined length burst
+ *  0b101..Reserved
+ *  0b110..Reserved
+ *  0b111..Reserved
+ */
+#define AXBS_MGPCR1_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
+/*! @} */
+
+/*! @name MGPCR2 - Master General Purpose Control Register */
+/*! @{ */
+#define AXBS_MGPCR2_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR2_AULB_SHIFT                   (0U)
+/*! AULB - Arbitrates On Undefined Length Bursts
+ *  0b000..No arbitration is allowed during an undefined length burst
+ *  0b001..Arbitration is allowed at any time during an undefined length burst
+ *  0b010..Arbitration is allowed after four beats of an undefined length burst
+ *  0b011..Arbitration is allowed after eight beats of an undefined length burst
+ *  0b100..Arbitration is allowed after 16 beats of an undefined length burst
+ *  0b101..Reserved
+ *  0b110..Reserved
+ *  0b111..Reserved
+ */
+#define AXBS_MGPCR2_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
+/*! @} */
+
+/*! @name MGPCR3 - Master General Purpose Control Register */
+/*! @{ */
+#define AXBS_MGPCR3_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR3_AULB_SHIFT                   (0U)
+/*! AULB - Arbitrates On Undefined Length Bursts
+ *  0b000..No arbitration is allowed during an undefined length burst
+ *  0b001..Arbitration is allowed at any time during an undefined length burst
+ *  0b010..Arbitration is allowed after four beats of an undefined length burst
+ *  0b011..Arbitration is allowed after eight beats of an undefined length burst
+ *  0b100..Arbitration is allowed after 16 beats of an undefined length burst
+ *  0b101..Reserved
+ *  0b110..Reserved
+ *  0b111..Reserved
+ */
+#define AXBS_MGPCR3_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
+/*! @} */
+
+/*! @name MGPCR4 - Master General Purpose Control Register */
+/*! @{ */
+#define AXBS_MGPCR4_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR4_AULB_SHIFT                   (0U)
+/*! AULB - Arbitrates On Undefined Length Bursts
+ *  0b000..No arbitration is allowed during an undefined length burst
+ *  0b001..Arbitration is allowed at any time during an undefined length burst
+ *  0b010..Arbitration is allowed after four beats of an undefined length burst
+ *  0b011..Arbitration is allowed after eight beats of an undefined length burst
+ *  0b100..Arbitration is allowed after 16 beats of an undefined length burst
+ *  0b101..Reserved
+ *  0b110..Reserved
+ *  0b111..Reserved
+ */
+#define AXBS_MGPCR4_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
+/*! @} */
+
+/*! @name MGPCR5 - Master General Purpose Control Register */
+/*! @{ */
+#define AXBS_MGPCR5_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR5_AULB_SHIFT                   (0U)
+/*! AULB - Arbitrates On Undefined Length Bursts
+ *  0b000..No arbitration is allowed during an undefined length burst
+ *  0b001..Arbitration is allowed at any time during an undefined length burst
+ *  0b010..Arbitration is allowed after four beats of an undefined length burst
+ *  0b011..Arbitration is allowed after eight beats of an undefined length burst
+ *  0b100..Arbitration is allowed after 16 beats of an undefined length burst
+ *  0b101..Reserved
+ *  0b110..Reserved
+ *  0b111..Reserved
+ */
+#define AXBS_MGPCR5_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Masks */
+
+
+/* AXBS - Peripheral instance base addresses */
+/** Peripheral AXBS0 base address */
+#define AXBS0_BASE                               (0x40004000u)
+/** Peripheral AXBS0 base pointer */
+#define AXBS0                                    ((AXBS_Type *)AXBS0_BASE)
+/** Array initializer of AXBS peripheral base addresses */
+#define AXBS_BASE_ADDRS                          { AXBS0_BASE }
+/** Array initializer of AXBS peripheral base pointers */
+#define AXBS_BASE_PTRS                           { AXBS0 }
+
+/*!
+ * @}
+ */ /* end of group AXBS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAU3 Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU3_Peripheral_Access_Layer CAU3 Peripheral Access Layer
+ * @{
+ */
+
+/** CAU3 - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t PCT;                               /**< Processor Core Type, offset: 0x0 */
+  __I  uint32_t MCFG;                              /**< Memory Configuration, offset: 0x4 */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t CR;                                /**< Control Register, offset: 0x10 */
+  __IO uint32_t SR;                                /**< Status Register, offset: 0x14 */
+       uint8_t RESERVED_1[8];
+  __IO uint32_t DBGCSR;                            /**< Debug Control/Status Register, offset: 0x20 */
+  __IO uint32_t DBGPBR;                            /**< Debug PC Breakpoint Register, offset: 0x24 */
+       uint8_t RESERVED_2[8];
+  __IO uint32_t DBGMCMD;                           /**< Debug Memory Command Register, offset: 0x30 */
+  __IO uint32_t DBGMADR;                           /**< Debug Memory Address Register, offset: 0x34 */
+  __IO uint32_t DBGMDR;                            /**< Debug Memory Data Register, offset: 0x38 */
+       uint8_t RESERVED_3[180];
+  __IO uint32_t SEMA4;                             /**< Semaphore Register, offset: 0xF0 */
+  __I  uint32_t SMOWNR;                            /**< Semaphore Ownership Register, offset: 0xF4 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t ARR;                               /**< Address Remap Register, offset: 0xFC */
+       uint8_t RESERVED_5[128];
+  __IO uint32_t CC_R[30];                          /**< CryptoCore General Purpose Registers, array offset: 0x180, array step: 0x4 */
+  __IO uint32_t CC_R30;                            /**< General Purpose R30, offset: 0x1F8 */
+  __IO uint32_t CC_R31;                            /**< General Purpose R31, offset: 0x1FC */
+  __IO uint32_t CC_PC;                             /**< Program Counter, offset: 0x200 */
+  __O  uint32_t CC_CMD;                            /**< Start Command Register, offset: 0x204 */
+  __I  uint32_t CC_CF;                             /**< Condition Flag, offset: 0x208 */
+       uint8_t RESERVED_6[500];
+  __IO uint32_t MDPK;                              /**< Mode Register (PublicKey), offset: 0x400 */
+       uint8_t RESERVED_7[44];
+  __O  uint32_t COM;                               /**< Command Register, offset: 0x430 */
+  __IO uint32_t CTL;                               /**< Control Register, offset: 0x434 */
+       uint8_t RESERVED_8[8];
+  __O  uint32_t CW;                                /**< Clear Written Register, offset: 0x440 */
+       uint8_t RESERVED_9[4];
+  __IO uint32_t STA;                               /**< Status Register, offset: 0x448 */
+  __I  uint32_t ESTA;                              /**< Error Status Register, offset: 0x44C */
+       uint8_t RESERVED_10[48];
+  __IO uint32_t PKASZ;                             /**< PKHA A Size Register, offset: 0x480 */
+       uint8_t RESERVED_11[4];
+  __IO uint32_t PKBSZ;                             /**< PKHA B Size Register, offset: 0x488 */
+       uint8_t RESERVED_12[4];
+  __IO uint32_t PKNSZ;                             /**< PKHA N Size Register, offset: 0x490 */
+       uint8_t RESERVED_13[4];
+  __IO uint32_t PKESZ;                             /**< PKHA E Size Register, offset: 0x498 */
+       uint8_t RESERVED_14[84];
+  __I  uint32_t PKHA_VID1;                         /**< PKHA Revision ID 1, offset: 0x4F0 */
+  __I  uint32_t PKHA_VID2;                         /**< PKHA Revision ID 2, offset: 0x4F4 */
+  __I  uint32_t CHA_VID;                           /**< CHA Revision ID, offset: 0x4F8 */
+       uint8_t RESERVED_15[260];
+  __IO uint32_t PKHA_CCR;                          /**< PKHA Clock Control Register, offset: 0x600 */
+  __I  uint32_t GSR;                               /**< Global Status Register, offset: 0x604 */
+  __IO uint32_t CKLFSR;                            /**< Clock Linear Feedback Shift Register, offset: 0x608 */
+       uint8_t RESERVED_16[500];
+  __IO uint32_t PKA0[32];                          /**< PKHA A0 Register, array offset: 0x800, array step: 0x4 */
+  __IO uint32_t PKA1[32];                          /**< PKHA A1 Register, array offset: 0x880, array step: 0x4 */
+  __IO uint32_t PKA2[32];                          /**< PKHA A2 Register, array offset: 0x900, array step: 0x4 */
+  __IO uint32_t PKA3[32];                          /**< PKHA A3 Register, array offset: 0x980, array step: 0x4 */
+  __IO uint32_t PKB0[32];                          /**< PKHA B0 Register, array offset: 0xA00, array step: 0x4 */
+  __IO uint32_t PKB1[32];                          /**< PKHA B1 Register, array offset: 0xA80, array step: 0x4 */
+  __IO uint32_t PKB2[32];                          /**< PKHA B2 Register, array offset: 0xB00, array step: 0x4 */
+  __IO uint32_t PKB3[32];                          /**< PKHA B3 Register, array offset: 0xB80, array step: 0x4 */
+  __IO uint32_t PKN0[32];                          /**< PKHA N0 Register, array offset: 0xC00, array step: 0x4 */
+  __IO uint32_t PKN1[32];                          /**< PKHA N1 Register, array offset: 0xC80, array step: 0x4 */
+  __IO uint32_t PKN2[32];                          /**< PKHA N2 Register, array offset: 0xD00, array step: 0x4 */
+  __IO uint32_t PKN3[32];                          /**< PKHA N3 Register, array offset: 0xD80, array step: 0x4 */
+  __O  uint32_t PKE[128];                          /**< PKHA E Register, array offset: 0xE00, array step: 0x4 */
+} CAU3_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CAU3 Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU3_Register_Masks CAU3 Register Masks
+ * @{
+ */
+
+/*! @name PCT - Processor Core Type */
+/*! @{ */
+#define CAU3_PCT_Y_MASK                          (0xFU)
+#define CAU3_PCT_Y_SHIFT                         (0U)
+/*! Y - Minor version number
+ *  0b0000..Minor version number
+ */
+#define CAU3_PCT_Y(x)                            (((uint32_t)(((uint32_t)(x)) << CAU3_PCT_Y_SHIFT)) & CAU3_PCT_Y_MASK)
+#define CAU3_PCT_X_MASK                          (0xF0U)
+#define CAU3_PCT_X_SHIFT                         (4U)
+/*! X - Major version number
+ *  0b0000..Major version number
+ */
+#define CAU3_PCT_X(x)                            (((uint32_t)(((uint32_t)(x)) << CAU3_PCT_X_SHIFT)) & CAU3_PCT_X_MASK)
+#define CAU3_PCT_ID_MASK                         (0xFFFFFF00U)
+#define CAU3_PCT_ID_SHIFT                        (8U)
+/*! ID - Module ID number
+ *  0b010010110100000101100000..ID number for basic configuration
+ *  0b010010110100000101100001..ID number for PKHA configuration
+ */
+#define CAU3_PCT_ID(x)                           (((uint32_t)(((uint32_t)(x)) << CAU3_PCT_ID_SHIFT)) & CAU3_PCT_ID_MASK)
+/*! @} */
+
+/*! @name MCFG - Memory Configuration */
+/*! @{ */
+#define CAU3_MCFG_DRAM_SZ_MASK                   (0xF00U)
+#define CAU3_MCFG_DRAM_SZ_SHIFT                  (8U)
+/*! DRAM_SZ - Data RAM Size
+ *  0b0000..No memory module
+ *  0b0100..2K bytes
+ *  0b0101..3K bytes
+ *  0b0110..4K bytes
+ *  0b0111..6K bytes
+ *  0b1000..8K bytes
+ *  0b1001..12K bytes
+ *  0b1010..16K bytes
+ *  0b1011..24K bytes
+ *  0b1100..32K bytes
+ *  0b1101..48K bytes
+ *  0b1110..64K bytes
+ *  0b1111..96K bytes
+ */
+#define CAU3_MCFG_DRAM_SZ(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_MCFG_DRAM_SZ_SHIFT)) & CAU3_MCFG_DRAM_SZ_MASK)
+#define CAU3_MCFG_IROM_SZ_MASK                   (0xF0000U)
+#define CAU3_MCFG_IROM_SZ_SHIFT                  (16U)
+/*! IROM_SZ - Instruction ROM Size
+ *  0b0000..No memory module
+ *  0b0100..2K bytes
+ *  0b0101..3K bytes
+ *  0b0110..4K bytes
+ *  0b0111..6K bytes
+ *  0b1000..8K bytes
+ *  0b1001..12K bytes
+ *  0b1010..16K bytes
+ *  0b1011..24K bytes
+ *  0b1100..32K bytes
+ *  0b1101..48K bytes
+ *  0b1110..64K bytes
+ *  0b1111..96K bytes
+ */
+#define CAU3_MCFG_IROM_SZ(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_MCFG_IROM_SZ_SHIFT)) & CAU3_MCFG_IROM_SZ_MASK)
+#define CAU3_MCFG_IRAM_SZ_MASK                   (0xF000000U)
+#define CAU3_MCFG_IRAM_SZ_SHIFT                  (24U)
+/*! IRAM_SZ - Instruction RAM Size
+ *  0b0000..No memory module
+ *  0b0100..2K bytes
+ *  0b0101..3K bytes
+ *  0b0110..4K bytes
+ *  0b0111..6K bytes
+ *  0b1000..8K bytes
+ *  0b1001..12K bytes
+ *  0b1010..16K bytes
+ *  0b1011..24K bytes
+ *  0b1100..32K bytes
+ *  0b1101..48K bytes
+ *  0b1110..64K bytes
+ *  0b1111..96K bytes
+ */
+#define CAU3_MCFG_IRAM_SZ(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_MCFG_IRAM_SZ_SHIFT)) & CAU3_MCFG_IRAM_SZ_MASK)
+/*! @} */
+
+/*! @name CR - Control Register */
+/*! @{ */
+#define CAU3_CR_TCSEIE_MASK                      (0x1U)
+#define CAU3_CR_TCSEIE_SHIFT                     (0U)
+/*! TCSEIE - Task completion with software error interrupt enable
+ *  0b0..Disables task completion with software error to generate an interrupt request
+ *  0b1..Enables task completion with software error to generate an interrupt request
+ */
+#define CAU3_CR_TCSEIE(x)                        (((uint32_t)(((uint32_t)(x)) << CAU3_CR_TCSEIE_SHIFT)) & CAU3_CR_TCSEIE_MASK)
+#define CAU3_CR_ILLIE_MASK                       (0x2U)
+#define CAU3_CR_ILLIE_SHIFT                      (1U)
+/*! ILLIE - Illegal Instruction Interrupt Enable
+ *  0b0..Illegal instruction interrupt requests are disabled
+ *  0b1..illegal Instruction interrupt requests are enabled
+ */
+#define CAU3_CR_ILLIE(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_CR_ILLIE_SHIFT)) & CAU3_CR_ILLIE_MASK)
+#define CAU3_CR_ASREIE_MASK                      (0x8U)
+#define CAU3_CR_ASREIE_SHIFT                     (3U)
+/*! ASREIE - AHB Slave Response Error Interrupt Enable
+ *  0b0..AHB slave response error interruption is not enabled
+ *  0b1..AHB slave response error interruption is enabled
+ */
+#define CAU3_CR_ASREIE(x)                        (((uint32_t)(((uint32_t)(x)) << CAU3_CR_ASREIE_SHIFT)) & CAU3_CR_ASREIE_MASK)
+#define CAU3_CR_IIADIE_MASK                      (0x10U)
+#define CAU3_CR_IIADIE_SHIFT                     (4U)
+/*! IIADIE - IMEM Illegal Address Interrupt Enable
+ *  0b0..IMEM illegal address interruption is not enabled
+ *  0b1..IMEM illegal address interruption is enabled
+ */
+#define CAU3_CR_IIADIE(x)                        (((uint32_t)(((uint32_t)(x)) << CAU3_CR_IIADIE_SHIFT)) & CAU3_CR_IIADIE_MASK)
+#define CAU3_CR_DIADIE_MASK                      (0x20U)
+#define CAU3_CR_DIADIE_SHIFT                     (5U)
+/*! DIADIE - DMEM Illegal Address Interrupt Enable
+ *  0b0..DMEM illegal address interruption is not enabled
+ *  0b1..DMEM illegal address interruption is enabled
+ */
+#define CAU3_CR_DIADIE(x)                        (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DIADIE_SHIFT)) & CAU3_CR_DIADIE_MASK)
+#define CAU3_CR_SVIE_MASK                        (0x40U)
+#define CAU3_CR_SVIE_SHIFT                       (6U)
+/*! SVIE - Security Violation Interrupt Enable
+ *  0b0..Security violation interruption is not enabled
+ *  0b1..Security violation interruption is enabled
+ */
+#define CAU3_CR_SVIE(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CR_SVIE_SHIFT)) & CAU3_CR_SVIE_MASK)
+#define CAU3_CR_TCIE_MASK                        (0x80U)
+#define CAU3_CR_TCIE_SHIFT                       (7U)
+/*! TCIE - Task completion with no error interrupt enable
+ *  0b0..Disables task completion with no error to generate an interrupt request
+ *  0b1..Enables task completion with no error to generate an interrupt request
+ */
+#define CAU3_CR_TCIE(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CR_TCIE_SHIFT)) & CAU3_CR_TCIE_MASK)
+#define CAU3_CR_RSTSM4_MASK                      (0x3000U)
+#define CAU3_CR_RSTSM4_SHIFT                     (12U)
+/*! RSTSM4 - Reset Semaphore
+ *  0b00..Idle state
+ *  0b01..Wait for second write
+ *  0b10..Clears semaphore if previous state was "01"
+ *  0b11..Reserved
+ */
+#define CAU3_CR_RSTSM4(x)                        (((uint32_t)(((uint32_t)(x)) << CAU3_CR_RSTSM4_SHIFT)) & CAU3_CR_RSTSM4_MASK)
+#define CAU3_CR_MRST_MASK                        (0x8000U)
+#define CAU3_CR_MRST_SHIFT                       (15U)
+/*! MRST - Module Reset
+ *  0b0..no action
+ *  0b1..reset
+ */
+#define CAU3_CR_MRST(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CR_MRST_SHIFT)) & CAU3_CR_MRST_MASK)
+#define CAU3_CR_FSV_MASK                         (0x10000U)
+#define CAU3_CR_FSV_SHIFT                        (16U)
+/*! FSV - Force Security Violation Test
+ *  0b0..no violation is forced
+ *  0b1..force security violation
+ */
+#define CAU3_CR_FSV(x)                           (((uint32_t)(((uint32_t)(x)) << CAU3_CR_FSV_SHIFT)) & CAU3_CR_FSV_MASK)
+#define CAU3_CR_DTCCFG_MASK                      (0x7000000U)
+#define CAU3_CR_DTCCFG_SHIFT                     (24U)
+/*! DTCCFG - Default Task Completion Configuration
+ *  0b100..Issue a DMA request
+ *  0b010..Assert Event Completion Signal
+ *  0b001..Issue an Interrupt Request
+ *  0b000..no explicit action
+ */
+#define CAU3_CR_DTCCFG(x)                        (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DTCCFG_SHIFT)) & CAU3_CR_DTCCFG_MASK)
+#define CAU3_CR_DSHFI_MASK                       (0x10000000U)
+#define CAU3_CR_DSHFI_SHIFT                      (28U)
+/*! DSHFI - Disable Secure Hash Function Instructions
+ *  0b0..Secure Hash Functions are enabled
+ *  0b1..Secure Hash Functions are disabled
+ */
+#define CAU3_CR_DSHFI(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DSHFI_SHIFT)) & CAU3_CR_DSHFI_MASK)
+#define CAU3_CR_DDESI_MASK                       (0x20000000U)
+#define CAU3_CR_DDESI_SHIFT                      (29U)
+/*! DDESI - Disable DES Instructions
+ *  0b0..DES instructions are enabled
+ *  0b1..DES instructions are disabled
+ */
+#define CAU3_CR_DDESI(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DDESI_SHIFT)) & CAU3_CR_DDESI_MASK)
+#define CAU3_CR_DAESI_MASK                       (0x40000000U)
+#define CAU3_CR_DAESI_SHIFT                      (30U)
+/*! DAESI - Disable AES Instructions
+ *  0b0..AES instructions are enabled
+ *  0b1..AES instructions are disabled
+ */
+#define CAU3_CR_DAESI(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DAESI_SHIFT)) & CAU3_CR_DAESI_MASK)
+#define CAU3_CR_MDIS_MASK                        (0x80000000U)
+#define CAU3_CR_MDIS_SHIFT                       (31U)
+/*! MDIS - Module Disable
+ *  0b0..CAU3 exits from low power mode
+ *  0b1..CAU3 enters low power mode
+ */
+#define CAU3_CR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CR_MDIS_SHIFT)) & CAU3_CR_MDIS_MASK)
+/*! @} */
+
+/*! @name SR - Status Register */
+/*! @{ */
+#define CAU3_SR_TCSEIRQ_MASK                     (0x1U)
+#define CAU3_SR_TCSEIRQ_SHIFT                    (0U)
+/*! TCSEIRQ - Task completion with software error interrupt request
+ *  0b0..Task not finished or finished with no software error
+ *  0b1..Task execution finished with software error
+ */
+#define CAU3_SR_TCSEIRQ(x)                       (((uint32_t)(((uint32_t)(x)) << CAU3_SR_TCSEIRQ_SHIFT)) & CAU3_SR_TCSEIRQ_MASK)
+#define CAU3_SR_ILLIRQ_MASK                      (0x2U)
+#define CAU3_SR_ILLIRQ_SHIFT                     (1U)
+/*! ILLIRQ - Illegal instruction interrupt request
+ *  0b0..no error
+ *  0b1..illegal instruction detected
+ */
+#define CAU3_SR_ILLIRQ(x)                        (((uint32_t)(((uint32_t)(x)) << CAU3_SR_ILLIRQ_SHIFT)) & CAU3_SR_ILLIRQ_MASK)
+#define CAU3_SR_ASREIRQ_MASK                     (0x8U)
+#define CAU3_SR_ASREIRQ_SHIFT                    (3U)
+/*! ASREIRQ - AHB slave response error interrupt Request
+ *  0b0..no error
+ *  0b1..AHB slave response error detected
+ */
+#define CAU3_SR_ASREIRQ(x)                       (((uint32_t)(((uint32_t)(x)) << CAU3_SR_ASREIRQ_SHIFT)) & CAU3_SR_ASREIRQ_MASK)
+#define CAU3_SR_IIADIRQ_MASK                     (0x10U)
+#define CAU3_SR_IIADIRQ_SHIFT                    (4U)
+/*! IIADIRQ - IMEM Illegal address interrupt request
+ *  0b0..no error
+ *  0b1..illegal IMEM address detected
+ */
+#define CAU3_SR_IIADIRQ(x)                       (((uint32_t)(((uint32_t)(x)) << CAU3_SR_IIADIRQ_SHIFT)) & CAU3_SR_IIADIRQ_MASK)
+#define CAU3_SR_DIADIRQ_MASK                     (0x20U)
+#define CAU3_SR_DIADIRQ_SHIFT                    (5U)
+/*! DIADIRQ - DMEM illegal access interrupt request
+ *  0b0..no illegal address
+ *  0b1..illegal address
+ */
+#define CAU3_SR_DIADIRQ(x)                       (((uint32_t)(((uint32_t)(x)) << CAU3_SR_DIADIRQ_SHIFT)) & CAU3_SR_DIADIRQ_MASK)
+#define CAU3_SR_SVIRQ_MASK                       (0x40U)
+#define CAU3_SR_SVIRQ_SHIFT                      (6U)
+/*! SVIRQ - Security violation interrupt request
+ *  0b0..No security violation
+ *  0b1..Security violation
+ */
+#define CAU3_SR_SVIRQ(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_SR_SVIRQ_SHIFT)) & CAU3_SR_SVIRQ_MASK)
+#define CAU3_SR_TCIRQ_MASK                       (0x80U)
+#define CAU3_SR_TCIRQ_SHIFT                      (7U)
+/*! TCIRQ - Task completion with no error interrupt request
+ *  0b0..Task not finished or finished with error
+ *  0b1..Task execution finished with no error
+ */
+#define CAU3_SR_TCIRQ(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_SR_TCIRQ_SHIFT)) & CAU3_SR_TCIRQ_MASK)
+#define CAU3_SR_TKCS_MASK                        (0xF00U)
+#define CAU3_SR_TKCS_SHIFT                       (8U)
+/*! TKCS - Task completion status
+ *  0b0000..Initialization RUN
+ *  0b0001..Running
+ *  0b0010..Debug Halted
+ *  0b1001..Stop - Error Free
+ *  0b1010..Stop - Error
+ *  0b1110..Stop - Security Violation, assert security violation output signal and set SVIRQ
+ *  0b1111..Stop - Security Violation and set SVIRQ
+ */
+#define CAU3_SR_TKCS(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_SR_TKCS_SHIFT)) & CAU3_SR_TKCS_MASK)
+#define CAU3_SR_SVF_MASK                         (0x10000U)
+#define CAU3_SR_SVF_SHIFT                        (16U)
+/*! SVF - Security violation flag
+ *  0b0..SoC security violation is not asserted
+ *  0b1..SoC security violation was asserted
+ */
+#define CAU3_SR_SVF(x)                           (((uint32_t)(((uint32_t)(x)) << CAU3_SR_SVF_SHIFT)) & CAU3_SR_SVF_MASK)
+#define CAU3_SR_DBG_MASK                         (0x20000U)
+#define CAU3_SR_DBG_SHIFT                        (17U)
+/*! DBG - Debug mode
+ *  0b0..CAU3 is not in debug mode
+ *  0b1..CAU3 is in debug mode
+ */
+#define CAU3_SR_DBG(x)                           (((uint32_t)(((uint32_t)(x)) << CAU3_SR_DBG_SHIFT)) & CAU3_SR_DBG_MASK)
+#define CAU3_SR_TCCFG_MASK                       (0x7000000U)
+#define CAU3_SR_TCCFG_SHIFT                      (24U)
+/*! TCCFG - Task completion configuration
+ *  0b100..Issue a DMA request
+ *  0b010..Assert the Event Completion Signal
+ *  0b001..Assert an interrupt request
+ *  0b000..No action
+ */
+#define CAU3_SR_TCCFG(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_SR_TCCFG_SHIFT)) & CAU3_SR_TCCFG_MASK)
+#define CAU3_SR_MDISF_MASK                       (0x80000000U)
+#define CAU3_SR_MDISF_SHIFT                      (31U)
+/*! MDISF - Module disable flag
+ *  0b0..CCore is not in low power mode
+ *  0b1..CCore is in low power mode
+ */
+#define CAU3_SR_MDISF(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_SR_MDISF_SHIFT)) & CAU3_SR_MDISF_MASK)
+/*! @} */
+
+/*! @name DBGCSR - Debug Control/Status Register */
+/*! @{ */
+#define CAU3_DBGCSR_DDBG_MASK                    (0x1U)
+#define CAU3_DBGCSR_DDBG_SHIFT                   (0U)
+/*! DDBG - Debug Disable
+ *  0b0..debug is enabled
+ *  0b1..debug is disabled
+ */
+#define CAU3_DBGCSR_DDBG(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_DDBG_SHIFT)) & CAU3_DBGCSR_DDBG_MASK)
+#define CAU3_DBGCSR_DDBGMC_MASK                  (0x2U)
+#define CAU3_DBGCSR_DDBGMC_SHIFT                 (1U)
+/*! DDBGMC - Disable Debug Memory Commands
+ *  0b0..IPS access to IMEM and DMEM are enabled
+ *  0b1..IPS access to IMEM and DMEM are disabled
+ */
+#define CAU3_DBGCSR_DDBGMC(x)                    (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_DDBGMC_SHIFT)) & CAU3_DBGCSR_DDBGMC_MASK)
+#define CAU3_DBGCSR_PBREN_MASK                   (0x10U)
+#define CAU3_DBGCSR_PBREN_SHIFT                  (4U)
+/*! PBREN - PC Breakpoint Register Enable
+ *  0b0..PC breakpoint register (DBGPBR) is disabled
+ *  0b1..PC breakpoint register (DBGPBR) is enabled
+ */
+#define CAU3_DBGCSR_PBREN(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_PBREN_SHIFT)) & CAU3_DBGCSR_PBREN_MASK)
+#define CAU3_DBGCSR_SIM_MASK                     (0x20U)
+#define CAU3_DBGCSR_SIM_SHIFT                    (5U)
+/*! SIM - Single Instruction Mode
+ *  0b0..Single instruction mode is disabled
+ *  0b1..Single instruction mode is enabled
+ */
+#define CAU3_DBGCSR_SIM(x)                       (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_SIM_SHIFT)) & CAU3_DBGCSR_SIM_MASK)
+#define CAU3_DBGCSR_FRCH_MASK                    (0x100U)
+#define CAU3_DBGCSR_FRCH_SHIFT                   (8U)
+/*! FRCH - Force Debug Halt
+ *  0b0..Halt state not forced
+ *  0b1..Force halt state
+ */
+#define CAU3_DBGCSR_FRCH(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_FRCH_SHIFT)) & CAU3_DBGCSR_FRCH_MASK)
+#define CAU3_DBGCSR_DBGGO_MASK                   (0x1000U)
+#define CAU3_DBGCSR_DBGGO_SHIFT                  (12U)
+/*! DBGGO - Debug Go
+ *  0b0..No action
+ *  0b1..Resume program execution
+ */
+#define CAU3_DBGCSR_DBGGO(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_DBGGO_SHIFT)) & CAU3_DBGCSR_DBGGO_MASK)
+#define CAU3_DBGCSR_PCBHF_MASK                   (0x10000U)
+#define CAU3_DBGCSR_PCBHF_SHIFT                  (16U)
+/*! PCBHF - CryptoCore is Halted due to Hardware Breakpoint
+ *  0b0..CryptoCore is not halted due to a hardware breakpoint
+ *  0b1..CryptoCore is halted due to a hardware breakpoint
+ */
+#define CAU3_DBGCSR_PCBHF(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_PCBHF_SHIFT)) & CAU3_DBGCSR_PCBHF_MASK)
+#define CAU3_DBGCSR_SIMHF_MASK                   (0x20000U)
+#define CAU3_DBGCSR_SIMHF_SHIFT                  (17U)
+/*! SIMHF - CryptoCore is Halted due to Single Instruction Step
+ *  0b0..CryptoCore is not in a single step halt
+ *  0b1..CryptoCore is in a single step halt
+ */
+#define CAU3_DBGCSR_SIMHF(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_SIMHF_SHIFT)) & CAU3_DBGCSR_SIMHF_MASK)
+#define CAU3_DBGCSR_HLTIF_MASK                   (0x40000U)
+#define CAU3_DBGCSR_HLTIF_SHIFT                  (18U)
+/*! HLTIF - CryptoCore is Halted due to HALT Instruction
+ *  0b0..CryptoCore is not in software breakpoint
+ *  0b1..CryptoCore is in software breakpoint
+ */
+#define CAU3_DBGCSR_HLTIF(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_HLTIF_SHIFT)) & CAU3_DBGCSR_HLTIF_MASK)
+#define CAU3_DBGCSR_CSTPF_MASK                   (0x40000000U)
+#define CAU3_DBGCSR_CSTPF_SHIFT                  (30U)
+/*! CSTPF - CryptoCore is Stopped Status Flag
+ *  0b0..CryptoCore is not stopped
+ *  0b1..CryptoCore is stopped
+ */
+#define CAU3_DBGCSR_CSTPF(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_CSTPF_SHIFT)) & CAU3_DBGCSR_CSTPF_MASK)
+#define CAU3_DBGCSR_CHLTF_MASK                   (0x80000000U)
+#define CAU3_DBGCSR_CHLTF_SHIFT                  (31U)
+/*! CHLTF - CryptoCore is Halted Status Flag
+ *  0b0..CryptoCore is not halted
+ *  0b1..CryptoCore is halted
+ */
+#define CAU3_DBGCSR_CHLTF(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_CHLTF_SHIFT)) & CAU3_DBGCSR_CHLTF_MASK)
+/*! @} */
+
+/*! @name DBGPBR - Debug PC Breakpoint Register */
+/*! @{ */
+#define CAU3_DBGPBR_PCBKPT_MASK                  (0xFFFFCU)
+#define CAU3_DBGPBR_PCBKPT_SHIFT                 (2U)
+#define CAU3_DBGPBR_PCBKPT(x)                    (((uint32_t)(((uint32_t)(x)) << CAU3_DBGPBR_PCBKPT_SHIFT)) & CAU3_DBGPBR_PCBKPT_MASK)
+/*! @} */
+
+/*! @name DBGMCMD - Debug Memory Command Register */
+/*! @{ */
+#define CAU3_DBGMCMD_DM_MASK                     (0x1000000U)
+#define CAU3_DBGMCMD_DM_SHIFT                    (24U)
+/*! DM - Instruction/Data Memory Selection
+ *  0b0..IMEM is selected
+ *  0b1..DMEM is selected
+ */
+#define CAU3_DBGMCMD_DM(x)                       (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_DM_SHIFT)) & CAU3_DBGMCMD_DM_MASK)
+#define CAU3_DBGMCMD_IA_MASK                     (0x4000000U)
+#define CAU3_DBGMCMD_IA_SHIFT                    (26U)
+/*! IA - Increment Address
+ *  0b0..Address is not incremented
+ *  0b1..Address is incremented after the access
+ */
+#define CAU3_DBGMCMD_IA(x)                       (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_IA_SHIFT)) & CAU3_DBGMCMD_IA_MASK)
+#define CAU3_DBGMCMD_Rb_1_MASK                   (0x8000000U)
+#define CAU3_DBGMCMD_Rb_1_SHIFT                  (27U)
+#define CAU3_DBGMCMD_Rb_1(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_Rb_1_SHIFT)) & CAU3_DBGMCMD_Rb_1_MASK)
+#define CAU3_DBGMCMD_BV_MASK                     (0x10000000U)
+#define CAU3_DBGMCMD_BV_SHIFT                    (28U)
+/*! BV - Byte Reversal Control
+ *  0b0..DMEM bytes are not reversed
+ *  0b1..DMEM bytes are reversed
+ */
+#define CAU3_DBGMCMD_BV(x)                       (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_BV_SHIFT)) & CAU3_DBGMCMD_BV_MASK)
+#define CAU3_DBGMCMD_R_0_MASK                    (0x40000000U)
+#define CAU3_DBGMCMD_R_0_SHIFT                   (30U)
+#define CAU3_DBGMCMD_R_0(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_R_0_SHIFT)) & CAU3_DBGMCMD_R_0_MASK)
+#define CAU3_DBGMCMD_R_1_MASK                    (0x80000000U)
+#define CAU3_DBGMCMD_R_1_SHIFT                   (31U)
+#define CAU3_DBGMCMD_R_1(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_R_1_SHIFT)) & CAU3_DBGMCMD_R_1_MASK)
+/*! @} */
+
+/*! @name DBGMADR - Debug Memory Address Register */
+/*! @{ */
+#define CAU3_DBGMADR_DMADDR_MASK                 (0xFFFFFFFCU)
+#define CAU3_DBGMADR_DMADDR_SHIFT                (2U)
+#define CAU3_DBGMADR_DMADDR(x)                   (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMADR_DMADDR_SHIFT)) & CAU3_DBGMADR_DMADDR_MASK)
+/*! @} */
+
+/*! @name DBGMDR - Debug Memory Data Register */
+/*! @{ */
+#define CAU3_DBGMDR_DMDATA_MASK                  (0xFFFFFFFFU)
+#define CAU3_DBGMDR_DMDATA_SHIFT                 (0U)
+#define CAU3_DBGMDR_DMDATA(x)                    (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMDR_DMDATA_SHIFT)) & CAU3_DBGMDR_DMDATA_MASK)
+/*! @} */
+
+/*! @name SEMA4 - Semaphore Register */
+/*! @{ */
+#define CAU3_SEMA4_DID_MASK                      (0xFU)
+#define CAU3_SEMA4_DID_SHIFT                     (0U)
+#define CAU3_SEMA4_DID(x)                        (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_DID_SHIFT)) & CAU3_SEMA4_DID_MASK)
+#define CAU3_SEMA4_PR_MASK                       (0x40U)
+#define CAU3_SEMA4_PR_SHIFT                      (6U)
+/*! PR - Privilege Attribute of Locked Semaphore Owner
+ *  0b0..If semaphore is locked, then owner is operating in user mode
+ *  0b1..If semaphore is locked, then owner is operating in privileged mode
+ */
+#define CAU3_SEMA4_PR(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_PR_SHIFT)) & CAU3_SEMA4_PR_MASK)
+#define CAU3_SEMA4_NS_MASK                       (0x80U)
+#define CAU3_SEMA4_NS_SHIFT                      (7U)
+/*! NS - Non Secure Attribute of the Locked Semaphore Owner
+ *  0b0..If semaphore is locked, owner is operating in secure mode
+ *  0b1..If semaphore is locked, owner is operating in nonsecure mode
+ */
+#define CAU3_SEMA4_NS(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_NS_SHIFT)) & CAU3_SEMA4_NS_MASK)
+#define CAU3_SEMA4_MSTRN_MASK                    (0x3F00U)
+#define CAU3_SEMA4_MSTRN_SHIFT                   (8U)
+#define CAU3_SEMA4_MSTRN(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_MSTRN_SHIFT)) & CAU3_SEMA4_MSTRN_MASK)
+#define CAU3_SEMA4_LK_MASK                       (0x80000000U)
+#define CAU3_SEMA4_LK_SHIFT                      (31U)
+/*! LK - Semaphore Lock and Release Control
+ *  0b0..Semaphore release
+ *  0b1..Semaphore lock
+ */
+#define CAU3_SEMA4_LK(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_LK_SHIFT)) & CAU3_SEMA4_LK_MASK)
+/*! @} */
+
+/*! @name SMOWNR - Semaphore Ownership Register */
+/*! @{ */
+#define CAU3_SMOWNR_LOCK_MASK                    (0x1U)
+#define CAU3_SMOWNR_LOCK_SHIFT                   (0U)
+/*! LOCK - Semaphore Locked
+ *  0b0..Semaphore not locked
+ *  0b1..Semaphore locked
+ */
+#define CAU3_SMOWNR_LOCK(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_SMOWNR_LOCK_SHIFT)) & CAU3_SMOWNR_LOCK_MASK)
+#define CAU3_SMOWNR_NOWNER_MASK                  (0x80000000U)
+#define CAU3_SMOWNR_NOWNER_SHIFT                 (31U)
+/*! NOWNER - Semaphore Ownership
+ *  0b0..The host making the current read access is the semaphore owner
+ *  0b1..The host making the current read access is NOT the semaphore owner
+ */
+#define CAU3_SMOWNR_NOWNER(x)                    (((uint32_t)(((uint32_t)(x)) << CAU3_SMOWNR_NOWNER_SHIFT)) & CAU3_SMOWNR_NOWNER_MASK)
+/*! @} */
+
+/*! @name ARR - Address Remap Register */
+/*! @{ */
+#define CAU3_ARR_ARRL_MASK                       (0xFFFFFFFFU)
+#define CAU3_ARR_ARRL_SHIFT                      (0U)
+#define CAU3_ARR_ARRL(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_ARR_ARRL_SHIFT)) & CAU3_ARR_ARRL_MASK)
+/*! @} */
+
+/*! @name CC_R - CryptoCore General Purpose Registers */
+/*! @{ */
+#define CAU3_CC_R_R_MASK                         (0xFFFFFFFFU)
+#define CAU3_CC_R_R_SHIFT                        (0U)
+#define CAU3_CC_R_R(x)                           (((uint32_t)(((uint32_t)(x)) << CAU3_CC_R_R_SHIFT)) & CAU3_CC_R_R_MASK)
+/*! @} */
+
+/* The count of CAU3_CC_R */
+#define CAU3_CC_R_COUNT                          (30U)
+
+/*! @name CC_R30 - General Purpose R30 */
+/*! @{ */
+#define CAU3_CC_R30_SP_MASK                      (0xFFFFFFFFU)
+#define CAU3_CC_R30_SP_SHIFT                     (0U)
+#define CAU3_CC_R30_SP(x)                        (((uint32_t)(((uint32_t)(x)) << CAU3_CC_R30_SP_SHIFT)) & CAU3_CC_R30_SP_MASK)
+/*! @} */
+
+/*! @name CC_R31 - General Purpose R31 */
+/*! @{ */
+#define CAU3_CC_R31_LR_MASK                      (0xFFFFFFFFU)
+#define CAU3_CC_R31_LR_SHIFT                     (0U)
+#define CAU3_CC_R31_LR(x)                        (((uint32_t)(((uint32_t)(x)) << CAU3_CC_R31_LR_SHIFT)) & CAU3_CC_R31_LR_MASK)
+/*! @} */
+
+/*! @name CC_PC - Program Counter */
+/*! @{ */
+#define CAU3_CC_PC_PC_MASK                       (0xFFFFFU)
+#define CAU3_CC_PC_PC_SHIFT                      (0U)
+#define CAU3_CC_PC_PC(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_CC_PC_PC_SHIFT)) & CAU3_CC_PC_PC_MASK)
+/*! @} */
+
+/*! @name CC_CMD - Start Command Register */
+/*! @{ */
+#define CAU3_CC_CMD_CMD_MASK                     (0x70000U)
+#define CAU3_CC_CMD_CMD_SHIFT                    (16U)
+/*! CMD - Command
+ *  0b000..Use CR[DTCCFG] for task completion configuration
+ *  0b100..Issue a DMA request
+ *  0b010..Assert Event Completion Signal
+ *  0b001..Issue an interrupt request
+ */
+#define CAU3_CC_CMD_CMD(x)                       (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CMD_CMD_SHIFT)) & CAU3_CC_CMD_CMD_MASK)
+/*! @} */
+
+/*! @name CC_CF - Condition Flag */
+/*! @{ */
+#define CAU3_CC_CF_C_MASK                        (0x1U)
+#define CAU3_CC_CF_C_SHIFT                       (0U)
+#define CAU3_CC_CF_C(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CF_C_SHIFT)) & CAU3_CC_CF_C_MASK)
+#define CAU3_CC_CF_V_MASK                        (0x2U)
+#define CAU3_CC_CF_V_SHIFT                       (1U)
+#define CAU3_CC_CF_V(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CF_V_SHIFT)) & CAU3_CC_CF_V_MASK)
+#define CAU3_CC_CF_Z_MASK                        (0x4U)
+#define CAU3_CC_CF_Z_SHIFT                       (2U)
+#define CAU3_CC_CF_Z(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CF_Z_SHIFT)) & CAU3_CC_CF_Z_MASK)
+#define CAU3_CC_CF_N_MASK                        (0x8U)
+#define CAU3_CC_CF_N_SHIFT                       (3U)
+#define CAU3_CC_CF_N(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CF_N_SHIFT)) & CAU3_CC_CF_N_MASK)
+/*! @} */
+
+/*! @name MDPK - Mode Register (PublicKey) */
+/*! @{ */
+#define CAU3_MDPK_PKHA_MODE_LS_MASK              (0xFFFU)
+#define CAU3_MDPK_PKHA_MODE_LS_SHIFT             (0U)
+#define CAU3_MDPK_PKHA_MODE_LS(x)                (((uint32_t)(((uint32_t)(x)) << CAU3_MDPK_PKHA_MODE_LS_SHIFT)) & CAU3_MDPK_PKHA_MODE_LS_MASK)
+#define CAU3_MDPK_PKHA_MODE_MS_MASK              (0xF0000U)
+#define CAU3_MDPK_PKHA_MODE_MS_SHIFT             (16U)
+#define CAU3_MDPK_PKHA_MODE_MS(x)                (((uint32_t)(((uint32_t)(x)) << CAU3_MDPK_PKHA_MODE_MS_SHIFT)) & CAU3_MDPK_PKHA_MODE_MS_MASK)
+#define CAU3_MDPK_ALG_MASK                       (0xF00000U)
+#define CAU3_MDPK_ALG_SHIFT                      (20U)
+/*! ALG - Algorithm
+ *  0b1000..PKHA
+ */
+#define CAU3_MDPK_ALG(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_MDPK_ALG_SHIFT)) & CAU3_MDPK_ALG_MASK)
+/*! @} */
+
+/*! @name COM - Command Register */
+/*! @{ */
+#define CAU3_COM_ALL_MASK                        (0x1U)
+#define CAU3_COM_ALL_SHIFT                       (0U)
+/*! ALL - Reset All Internal Logic
+ *  0b0..Do Not Reset
+ *  0b1..Reset PKHA engine and registers
+ */
+#define CAU3_COM_ALL(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_COM_ALL_SHIFT)) & CAU3_COM_ALL_MASK)
+#define CAU3_COM_PK_MASK                         (0x40U)
+#define CAU3_COM_PK_SHIFT                        (6U)
+/*! PK - Reset PKHA
+ *  0b0..Do Not Reset
+ *  0b1..Reset Public Key Hardware Accelerator
+ */
+#define CAU3_COM_PK(x)                           (((uint32_t)(((uint32_t)(x)) << CAU3_COM_PK_SHIFT)) & CAU3_COM_PK_MASK)
+/*! @} */
+
+/*! @name CTL - Control Register */
+/*! @{ */
+#define CAU3_CTL_IM_MASK                         (0x1U)
+#define CAU3_CTL_IM_SHIFT                        (0U)
+/*! IM - Interrupt Mask
+ *  0b0..Interrupt not masked.
+ *  0b1..Interrupt masked
+ */
+#define CAU3_CTL_IM(x)                           (((uint32_t)(((uint32_t)(x)) << CAU3_CTL_IM_SHIFT)) & CAU3_CTL_IM_MASK)
+#define CAU3_CTL_PDE_MASK                        (0x10U)
+#define CAU3_CTL_PDE_SHIFT                       (4U)
+/*! PDE - PKHA Register DMA Enable
+ *  0b0..DMA Request and Done signals disabled for the PKHA Registers.
+ *  0b1..DMA Request and Done signals enabled for the PKHA Registers.
+ */
+#define CAU3_CTL_PDE(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CTL_PDE_SHIFT)) & CAU3_CTL_PDE_MASK)
+/*! @} */
+
+/*! @name CW - Clear Written Register */
+/*! @{ */
+#define CAU3_CW_CM_MASK                          (0x1U)
+#define CAU3_CW_CM_SHIFT                         (0U)
+#define CAU3_CW_CM(x)                            (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CM_SHIFT)) & CAU3_CW_CM_MASK)
+#define CAU3_CW_CPKA_MASK                        (0x1000U)
+#define CAU3_CW_CPKA_SHIFT                       (12U)
+#define CAU3_CW_CPKA(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CPKA_SHIFT)) & CAU3_CW_CPKA_MASK)
+#define CAU3_CW_CPKB_MASK                        (0x2000U)
+#define CAU3_CW_CPKB_SHIFT                       (13U)
+#define CAU3_CW_CPKB(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CPKB_SHIFT)) & CAU3_CW_CPKB_MASK)
+#define CAU3_CW_CPKN_MASK                        (0x4000U)
+#define CAU3_CW_CPKN_SHIFT                       (14U)
+#define CAU3_CW_CPKN(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CPKN_SHIFT)) & CAU3_CW_CPKN_MASK)
+#define CAU3_CW_CPKE_MASK                        (0x8000U)
+#define CAU3_CW_CPKE_SHIFT                       (15U)
+#define CAU3_CW_CPKE(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CPKE_SHIFT)) & CAU3_CW_CPKE_MASK)
+/*! @} */
+
+/*! @name STA - Status Register */
+/*! @{ */
+#define CAU3_STA_PB_MASK                         (0x40U)
+#define CAU3_STA_PB_SHIFT                        (6U)
+/*! PB - PKHA Busy
+ *  0b0..PKHA Idle
+ *  0b1..PKHA Busy.
+ */
+#define CAU3_STA_PB(x)                           (((uint32_t)(((uint32_t)(x)) << CAU3_STA_PB_SHIFT)) & CAU3_STA_PB_MASK)
+#define CAU3_STA_DI_MASK                         (0x10000U)
+#define CAU3_STA_DI_SHIFT                        (16U)
+#define CAU3_STA_DI(x)                           (((uint32_t)(((uint32_t)(x)) << CAU3_STA_DI_SHIFT)) & CAU3_STA_DI_MASK)
+#define CAU3_STA_EI_MASK                         (0x100000U)
+#define CAU3_STA_EI_SHIFT                        (20U)
+/*! EI - Error Interrupt
+ *  0b0..Not Error.
+ *  0b1..Error Interrupt.
+ */
+#define CAU3_STA_EI(x)                           (((uint32_t)(((uint32_t)(x)) << CAU3_STA_EI_SHIFT)) & CAU3_STA_EI_MASK)
+#define CAU3_STA_PKP_MASK                        (0x10000000U)
+#define CAU3_STA_PKP_SHIFT                       (28U)
+#define CAU3_STA_PKP(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_STA_PKP_SHIFT)) & CAU3_STA_PKP_MASK)
+#define CAU3_STA_PKO_MASK                        (0x20000000U)
+#define CAU3_STA_PKO_SHIFT                       (29U)
+#define CAU3_STA_PKO(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_STA_PKO_SHIFT)) & CAU3_STA_PKO_MASK)
+#define CAU3_STA_PKZ_MASK                        (0x40000000U)
+#define CAU3_STA_PKZ_SHIFT                       (30U)
+#define CAU3_STA_PKZ(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_STA_PKZ_SHIFT)) & CAU3_STA_PKZ_MASK)
+/*! @} */
+
+/*! @name ESTA - Error Status Register */
+/*! @{ */
+#define CAU3_ESTA_ERRID1_MASK                    (0xFU)
+#define CAU3_ESTA_ERRID1_SHIFT                   (0U)
+/*! ERRID1 - Error ID 1
+ *  0b0001..Mode Error
+ *  0b0010..PKHA N Register Size Error
+ *  0b0011..PKHA E Register Size Error
+ *  0b0100..PKHA A Register Size Error
+ *  0b0101..PKHA B Register Size Error
+ *  0b0110..PKHA C input (as contained in the PKHA B0 quadrant) is Zero
+ *  0b0111..PKHA Divide by Zero Error
+ *  0b1000..PKHA Modulus Even Error
+ *  0b1111..Invalid Crypto Engine Selected
+ */
+#define CAU3_ESTA_ERRID1(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_ESTA_ERRID1_SHIFT)) & CAU3_ESTA_ERRID1_MASK)
+#define CAU3_ESTA_CL1_MASK                       (0xF00U)
+#define CAU3_ESTA_CL1_SHIFT                      (8U)
+/*! CL1 - algorithms
+ *  0b0000..General Error
+ *  0b1000..Public Key
+ */
+#define CAU3_ESTA_CL1(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_ESTA_CL1_SHIFT)) & CAU3_ESTA_CL1_MASK)
+/*! @} */
+
+/*! @name PKASZ - PKHA A Size Register */
+/*! @{ */
+#define CAU3_PKASZ_PKASZ_MASK                    (0x1FFU)
+#define CAU3_PKASZ_PKASZ_SHIFT                   (0U)
+#define CAU3_PKASZ_PKASZ(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_PKASZ_PKASZ_SHIFT)) & CAU3_PKASZ_PKASZ_MASK)
+/*! @} */
+
+/*! @name PKBSZ - PKHA B Size Register */
+/*! @{ */
+#define CAU3_PKBSZ_PKBSZ_MASK                    (0x1FFU)
+#define CAU3_PKBSZ_PKBSZ_SHIFT                   (0U)
+#define CAU3_PKBSZ_PKBSZ(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_PKBSZ_PKBSZ_SHIFT)) & CAU3_PKBSZ_PKBSZ_MASK)
+/*! @} */
+
+/*! @name PKNSZ - PKHA N Size Register */
+/*! @{ */
+#define CAU3_PKNSZ_PKNSZ_MASK                    (0x1FFU)
+#define CAU3_PKNSZ_PKNSZ_SHIFT                   (0U)
+#define CAU3_PKNSZ_PKNSZ(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_PKNSZ_PKNSZ_SHIFT)) & CAU3_PKNSZ_PKNSZ_MASK)
+/*! @} */
+
+/*! @name PKESZ - PKHA E Size Register */
+/*! @{ */
+#define CAU3_PKESZ_PKESZ_MASK                    (0x1FFU)
+#define CAU3_PKESZ_PKESZ_SHIFT                   (0U)
+#define CAU3_PKESZ_PKESZ(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_PKESZ_PKESZ_SHIFT)) & CAU3_PKESZ_PKESZ_MASK)
+/*! @} */
+
+/*! @name PKHA_VID1 - PKHA Revision ID 1 */
+/*! @{ */
+#define CAU3_PKHA_VID1_MIN_REV_MASK              (0xFFU)
+#define CAU3_PKHA_VID1_MIN_REV_SHIFT             (0U)
+#define CAU3_PKHA_VID1_MIN_REV(x)                (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID1_MIN_REV_SHIFT)) & CAU3_PKHA_VID1_MIN_REV_MASK)
+#define CAU3_PKHA_VID1_MAJ_REV_MASK              (0xFF00U)
+#define CAU3_PKHA_VID1_MAJ_REV_SHIFT             (8U)
+#define CAU3_PKHA_VID1_MAJ_REV(x)                (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID1_MAJ_REV_SHIFT)) & CAU3_PKHA_VID1_MAJ_REV_MASK)
+#define CAU3_PKHA_VID1_IP_ID_MASK                (0xFFFF0000U)
+#define CAU3_PKHA_VID1_IP_ID_SHIFT               (16U)
+#define CAU3_PKHA_VID1_IP_ID(x)                  (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID1_IP_ID_SHIFT)) & CAU3_PKHA_VID1_IP_ID_MASK)
+/*! @} */
+
+/*! @name PKHA_VID2 - PKHA Revision ID 2 */
+/*! @{ */
+#define CAU3_PKHA_VID2_ECO_REV_MASK              (0xFFU)
+#define CAU3_PKHA_VID2_ECO_REV_SHIFT             (0U)
+#define CAU3_PKHA_VID2_ECO_REV(x)                (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID2_ECO_REV_SHIFT)) & CAU3_PKHA_VID2_ECO_REV_MASK)
+#define CAU3_PKHA_VID2_ARCH_ERA_MASK             (0xFF00U)
+#define CAU3_PKHA_VID2_ARCH_ERA_SHIFT            (8U)
+#define CAU3_PKHA_VID2_ARCH_ERA(x)               (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID2_ARCH_ERA_SHIFT)) & CAU3_PKHA_VID2_ARCH_ERA_MASK)
+/*! @} */
+
+/*! @name CHA_VID - CHA Revision ID */
+/*! @{ */
+#define CAU3_CHA_VID_PKHAREV_MASK                (0xF0000U)
+#define CAU3_CHA_VID_PKHAREV_SHIFT               (16U)
+#define CAU3_CHA_VID_PKHAREV(x)                  (((uint32_t)(((uint32_t)(x)) << CAU3_CHA_VID_PKHAREV_SHIFT)) & CAU3_CHA_VID_PKHAREV_MASK)
+#define CAU3_CHA_VID_PKHAVID_MASK                (0xF00000U)
+#define CAU3_CHA_VID_PKHAVID_SHIFT               (20U)
+#define CAU3_CHA_VID_PKHAVID(x)                  (((uint32_t)(((uint32_t)(x)) << CAU3_CHA_VID_PKHAVID_SHIFT)) & CAU3_CHA_VID_PKHAVID_MASK)
+/*! @} */
+
+/*! @name PKHA_CCR - PKHA Clock Control Register */
+/*! @{ */
+#define CAU3_PKHA_CCR_CKTHRT_MASK                (0x7U)
+#define CAU3_PKHA_CCR_CKTHRT_SHIFT               (0U)
+/*! CKTHRT - Clock Throttle selection
+ *  0b000..PKHA clock division rate is 8/8 - full speed
+ *  0b001..PKHA clock division rate is 1/8
+ *  0b010..PKHA clock division rate is 2/8
+ *  0b011..PKHA clock division rate is 3/8
+ *  0b100..PKHA clock division rate is 4/8
+ *  0b101..PKHA clock division rate is 5/8
+ *  0b110..PKHA clock division rate is 6/8
+ *  0b111..PKHA clock division rate is 7/8
+ */
+#define CAU3_PKHA_CCR_CKTHRT(x)                  (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_CKTHRT_SHIFT)) & CAU3_PKHA_CCR_CKTHRT_MASK)
+#define CAU3_PKHA_CCR_LK_MASK                    (0x1000000U)
+#define CAU3_PKHA_CCR_LK_SHIFT                   (24U)
+/*! LK - Register Lock
+ *  0b0..Register is unlocked
+ *  0b1..Register is locked
+ */
+#define CAU3_PKHA_CCR_LK(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_LK_SHIFT)) & CAU3_PKHA_CCR_LK_MASK)
+#define CAU3_PKHA_CCR_ELFR_MASK                  (0x20000000U)
+#define CAU3_PKHA_CCR_ELFR_SHIFT                 (29U)
+/*! ELFR - Enable Linear Feedback Shift Register
+ *  0b0..LFSR is only enabled if ECT = 1 and ECJ = 1
+ *  0b1..LFSR is enabled independently of ECT and ECJ
+ */
+#define CAU3_PKHA_CCR_ELFR(x)                    (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_ELFR_SHIFT)) & CAU3_PKHA_CCR_ELFR_MASK)
+#define CAU3_PKHA_CCR_ECJ_MASK                   (0x40000000U)
+#define CAU3_PKHA_CCR_ECJ_SHIFT                  (30U)
+/*! ECJ - Enable Clock Jitter
+ *  0b0..Clock Jitter is disabled
+ *  0b1..Clock jitter is enabled
+ */
+#define CAU3_PKHA_CCR_ECJ(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_ECJ_SHIFT)) & CAU3_PKHA_CCR_ECJ_MASK)
+#define CAU3_PKHA_CCR_ECT_MASK                   (0x80000000U)
+#define CAU3_PKHA_CCR_ECT_SHIFT                  (31U)
+/*! ECT - Enable Clock Throttle
+ *  0b0..PKHA clock throttle disabled meaning that PKHA is operatiing at full speed
+ *  0b1..PKHA clock throttle enabled
+ */
+#define CAU3_PKHA_CCR_ECT(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_ECT_SHIFT)) & CAU3_PKHA_CCR_ECT_MASK)
+/*! @} */
+
+/*! @name GSR - Global Status Register */
+/*! @{ */
+#define CAU3_GSR_CDI_MASK                        (0x400U)
+#define CAU3_GSR_CDI_SHIFT                       (10U)
+/*! CDI - CAU3 Done Interrupt occurred
+ *  0b0..CAU3 Done Interrupt did not occur
+ *  0b1..CAU3 Done Interrupt occurred
+ */
+#define CAU3_GSR_CDI(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_GSR_CDI_SHIFT)) & CAU3_GSR_CDI_MASK)
+#define CAU3_GSR_CEI_MASK                        (0x4000U)
+#define CAU3_GSR_CEI_SHIFT                       (14U)
+/*! CEI - CAU3 Error Interrupt
+ *  0b0..CAU3 Error Interrupt did not occur
+ *  0b1..CAU3 Error Interrupt occurred
+ */
+#define CAU3_GSR_CEI(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_GSR_CEI_SHIFT)) & CAU3_GSR_CEI_MASK)
+#define CAU3_GSR_PEI_MASK                        (0x8000U)
+#define CAU3_GSR_PEI_SHIFT                       (15U)
+/*! PEI - PKHA Done or Error Interrupt
+ *  0b0..PKHA interrupt did not occur
+ *  0b1..PKHA interrupt had occurred
+ */
+#define CAU3_GSR_PEI(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_GSR_PEI_SHIFT)) & CAU3_GSR_PEI_MASK)
+#define CAU3_GSR_PBSY_MASK                       (0x80000000U)
+#define CAU3_GSR_PBSY_SHIFT                      (31U)
+/*! PBSY - PKHA Busy
+ *  0b0..PKHA not busy
+ *  0b1..PKHA busy
+ */
+#define CAU3_GSR_PBSY(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_GSR_PBSY_SHIFT)) & CAU3_GSR_PBSY_MASK)
+/*! @} */
+
+/*! @name CKLFSR - Clock Linear Feedback Shift Register */
+/*! @{ */
+#define CAU3_CKLFSR_LFSR_MASK                    (0xFFFFFFFFU)
+#define CAU3_CKLFSR_LFSR_SHIFT                   (0U)
+#define CAU3_CKLFSR_LFSR(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_CKLFSR_LFSR_SHIFT)) & CAU3_CKLFSR_LFSR_MASK)
+/*! @} */
+
+/*! @name PKA0 - PKHA A0 Register */
+/*! @{ */
+#define CAU3_PKA0_PKHA_A0_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKA0_PKHA_A0_SHIFT                  (0U)
+#define CAU3_PKA0_PKHA_A0(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKA0_PKHA_A0_SHIFT)) & CAU3_PKA0_PKHA_A0_MASK)
+/*! @} */
+
+/* The count of CAU3_PKA0 */
+#define CAU3_PKA0_COUNT                          (32U)
+
+/*! @name PKA1 - PKHA A1 Register */
+/*! @{ */
+#define CAU3_PKA1_PKHA_A1_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKA1_PKHA_A1_SHIFT                  (0U)
+#define CAU3_PKA1_PKHA_A1(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKA1_PKHA_A1_SHIFT)) & CAU3_PKA1_PKHA_A1_MASK)
+/*! @} */
+
+/* The count of CAU3_PKA1 */
+#define CAU3_PKA1_COUNT                          (32U)
+
+/*! @name PKA2 - PKHA A2 Register */
+/*! @{ */
+#define CAU3_PKA2_PKHA_A2_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKA2_PKHA_A2_SHIFT                  (0U)
+#define CAU3_PKA2_PKHA_A2(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKA2_PKHA_A2_SHIFT)) & CAU3_PKA2_PKHA_A2_MASK)
+/*! @} */
+
+/* The count of CAU3_PKA2 */
+#define CAU3_PKA2_COUNT                          (32U)
+
+/*! @name PKA3 - PKHA A3 Register */
+/*! @{ */
+#define CAU3_PKA3_PKHA_A3_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKA3_PKHA_A3_SHIFT                  (0U)
+#define CAU3_PKA3_PKHA_A3(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKA3_PKHA_A3_SHIFT)) & CAU3_PKA3_PKHA_A3_MASK)
+/*! @} */
+
+/* The count of CAU3_PKA3 */
+#define CAU3_PKA3_COUNT                          (32U)
+
+/*! @name PKB0 - PKHA B0 Register */
+/*! @{ */
+#define CAU3_PKB0_PKHA_B0_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKB0_PKHA_B0_SHIFT                  (0U)
+#define CAU3_PKB0_PKHA_B0(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKB0_PKHA_B0_SHIFT)) & CAU3_PKB0_PKHA_B0_MASK)
+/*! @} */
+
+/* The count of CAU3_PKB0 */
+#define CAU3_PKB0_COUNT                          (32U)
+
+/*! @name PKB1 - PKHA B1 Register */
+/*! @{ */
+#define CAU3_PKB1_PKHA_B1_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKB1_PKHA_B1_SHIFT                  (0U)
+#define CAU3_PKB1_PKHA_B1(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKB1_PKHA_B1_SHIFT)) & CAU3_PKB1_PKHA_B1_MASK)
+/*! @} */
+
+/* The count of CAU3_PKB1 */
+#define CAU3_PKB1_COUNT                          (32U)
+
+/*! @name PKB2 - PKHA B2 Register */
+/*! @{ */
+#define CAU3_PKB2_PKHA_B2_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKB2_PKHA_B2_SHIFT                  (0U)
+#define CAU3_PKB2_PKHA_B2(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKB2_PKHA_B2_SHIFT)) & CAU3_PKB2_PKHA_B2_MASK)
+/*! @} */
+
+/* The count of CAU3_PKB2 */
+#define CAU3_PKB2_COUNT                          (32U)
+
+/*! @name PKB3 - PKHA B3 Register */
+/*! @{ */
+#define CAU3_PKB3_PKHA_B3_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKB3_PKHA_B3_SHIFT                  (0U)
+#define CAU3_PKB3_PKHA_B3(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKB3_PKHA_B3_SHIFT)) & CAU3_PKB3_PKHA_B3_MASK)
+/*! @} */
+
+/* The count of CAU3_PKB3 */
+#define CAU3_PKB3_COUNT                          (32U)
+
+/*! @name PKN0 - PKHA N0 Register */
+/*! @{ */
+#define CAU3_PKN0_PKHA_N0_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKN0_PKHA_N0_SHIFT                  (0U)
+#define CAU3_PKN0_PKHA_N0(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKN0_PKHA_N0_SHIFT)) & CAU3_PKN0_PKHA_N0_MASK)
+/*! @} */
+
+/* The count of CAU3_PKN0 */
+#define CAU3_PKN0_COUNT                          (32U)
+
+/*! @name PKN1 - PKHA N1 Register */
+/*! @{ */
+#define CAU3_PKN1_PKHA_N1_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKN1_PKHA_N1_SHIFT                  (0U)
+#define CAU3_PKN1_PKHA_N1(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKN1_PKHA_N1_SHIFT)) & CAU3_PKN1_PKHA_N1_MASK)
+/*! @} */
+
+/* The count of CAU3_PKN1 */
+#define CAU3_PKN1_COUNT                          (32U)
+
+/*! @name PKN2 - PKHA N2 Register */
+/*! @{ */
+#define CAU3_PKN2_PKHA_N2_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKN2_PKHA_N2_SHIFT                  (0U)
+#define CAU3_PKN2_PKHA_N2(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKN2_PKHA_N2_SHIFT)) & CAU3_PKN2_PKHA_N2_MASK)
+/*! @} */
+
+/* The count of CAU3_PKN2 */
+#define CAU3_PKN2_COUNT                          (32U)
+
+/*! @name PKN3 - PKHA N3 Register */
+/*! @{ */
+#define CAU3_PKN3_PKHA_N3_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKN3_PKHA_N3_SHIFT                  (0U)
+#define CAU3_PKN3_PKHA_N3(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKN3_PKHA_N3_SHIFT)) & CAU3_PKN3_PKHA_N3_MASK)
+/*! @} */
+
+/* The count of CAU3_PKN3 */
+#define CAU3_PKN3_COUNT                          (32U)
+
+/*! @name PKE - PKHA E Register */
+/*! @{ */
+#define CAU3_PKE_PKHA_E_MASK                     (0xFFFFFFFFU)
+#define CAU3_PKE_PKHA_E_SHIFT                    (0U)
+#define CAU3_PKE_PKHA_E(x)                       (((uint32_t)(((uint32_t)(x)) << CAU3_PKE_PKHA_E_SHIFT)) & CAU3_PKE_PKHA_E_MASK)
+/*! @} */
+
+/* The count of CAU3_PKE */
+#define CAU3_PKE_COUNT                           (128U)
+
+
+/*!
+ * @}
+ */ /* end of group CAU3_Register_Masks */
+
+
+/* CAU3 - Peripheral instance base addresses */
+/** Peripheral CAU3 base address */
+#define CAU3_BASE                                (0x41028000u)
+/** Peripheral CAU3 base pointer */
+#define CAU3                                     ((CAU3_Type *)CAU3_BASE)
+/** Array initializer of CAU3 peripheral base addresses */
+#define CAU3_BASE_ADDRS                          { CAU3_BASE }
+/** Array initializer of CAU3 peripheral base pointers */
+#define CAU3_BASE_PTRS                           { CAU3 }
+/** Interrupt vectors for the CAU3 peripheral type */
+#define CAU3_TASK_COMPLETE_IRQS                  { CAU3_Task_Complete_IRQn }
+#define CAU3_SECURITY_VIOLATION_IRQS             { CAU3_Security_Violation_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CAU3_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    __IO uint32_t DATA;                              /**< CRC Data register, offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint8_t DATALL;                             /**< CRC_DATALL register, offset: 0x0 */
+      __IO uint8_t DATALU;                             /**< CRC_DATALU register, offset: 0x1 */
+      __IO uint8_t DATAHL;                             /**< CRC_DATAHL register, offset: 0x2 */
+      __IO uint8_t DATAHU;                             /**< CRC_DATAHU register, offset: 0x3 */
+    } ACCESS8BIT;
+    struct {                                         /* offset: 0x0 */
+      __IO uint16_t DATAL;                             /**< CRC_DATAL register, offset: 0x0 */
+      __IO uint16_t DATAH;                             /**< CRC_DATAH register, offset: 0x2 */
+    } ACCESS16BIT;
+  };
+  union {                                          /* offset: 0x4 */
+    __IO uint32_t GPOLY;                             /**< CRC Polynomial register, offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint8_t GPOLYLL;                            /**< CRC_GPOLYLL register, offset: 0x4 */
+      __IO uint8_t GPOLYLU;                            /**< CRC_GPOLYLU register, offset: 0x5 */
+      __IO uint8_t GPOLYHL;                            /**< CRC_GPOLYHL register, offset: 0x6 */
+      __IO uint8_t GPOLYHU;                            /**< CRC_GPOLYHU register, offset: 0x7 */
+    } GPOLY_ACCESS8BIT;
+    struct {                                         /* offset: 0x4 */
+      __IO uint16_t GPOLYL;                            /**< CRC_GPOLYL register, offset: 0x4 */
+      __IO uint16_t GPOLYH;                            /**< CRC_GPOLYH register, offset: 0x6 */
+    } GPOLY_ACCESS16BIT;
+  };
+  union {                                          /* offset: 0x8 */
+    __IO uint32_t CTRL;                              /**< CRC Control register, offset: 0x8 */
+    struct {                                         /* offset: 0x8 */
+           uint8_t RESERVED_0[3];
+      __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register, offset: 0xB */
+    } CTRL_ACCESS8BIT;
+  };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/*! @name DATA - CRC Data register */
+/*! @{ */
+#define CRC_DATA_LL_MASK                         (0xFFU)
+#define CRC_DATA_LL_SHIFT                        (0U)
+#define CRC_DATA_LL(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
+#define CRC_DATA_LU_MASK                         (0xFF00U)
+#define CRC_DATA_LU_SHIFT                        (8U)
+#define CRC_DATA_LU(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
+#define CRC_DATA_HL_MASK                         (0xFF0000U)
+#define CRC_DATA_HL_SHIFT                        (16U)
+#define CRC_DATA_HL(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
+#define CRC_DATA_HU_MASK                         (0xFF000000U)
+#define CRC_DATA_HU_SHIFT                        (24U)
+#define CRC_DATA_HU(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
+/*! @} */
+
+/*! @name DATALL - CRC_DATALL register */
+/*! @{ */
+#define CRC_DATALL_DATALL_MASK                   (0xFFU)
+#define CRC_DATALL_DATALL_SHIFT                  (0U)
+#define CRC_DATALL_DATALL(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
+/*! @} */
+
+/*! @name DATALU - CRC_DATALU register */
+/*! @{ */
+#define CRC_DATALU_DATALU_MASK                   (0xFFU)
+#define CRC_DATALU_DATALU_SHIFT                  (0U)
+#define CRC_DATALU_DATALU(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
+/*! @} */
+
+/*! @name DATAHL - CRC_DATAHL register */
+/*! @{ */
+#define CRC_DATAHL_DATAHL_MASK                   (0xFFU)
+#define CRC_DATAHL_DATAHL_SHIFT                  (0U)
+#define CRC_DATAHL_DATAHL(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
+/*! @} */
+
+/*! @name DATAHU - CRC_DATAHU register */
+/*! @{ */
+#define CRC_DATAHU_DATAHU_MASK                   (0xFFU)
+#define CRC_DATAHU_DATAHU_SHIFT                  (0U)
+#define CRC_DATAHU_DATAHU(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
+/*! @} */
+
+/*! @name DATAL - CRC_DATAL register */
+/*! @{ */
+#define CRC_DATAL_DATAL_MASK                     (0xFFFFU)
+#define CRC_DATAL_DATAL_SHIFT                    (0U)
+#define CRC_DATAL_DATAL(x)                       (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
+/*! @} */
+
+/*! @name DATAH - CRC_DATAH register */
+/*! @{ */
+#define CRC_DATAH_DATAH_MASK                     (0xFFFFU)
+#define CRC_DATAH_DATAH_SHIFT                    (0U)
+#define CRC_DATAH_DATAH(x)                       (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
+/*! @} */
+
+/*! @name GPOLY - CRC Polynomial register */
+/*! @{ */
+#define CRC_GPOLY_LOW_MASK                       (0xFFFFU)
+#define CRC_GPOLY_LOW_SHIFT                      (0U)
+#define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK                      (0xFFFF0000U)
+#define CRC_GPOLY_HIGH_SHIFT                     (16U)
+#define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
+/*! @} */
+
+/*! @name GPOLYLL - CRC_GPOLYLL register */
+/*! @{ */
+#define CRC_GPOLYLL_GPOLYLL_MASK                 (0xFFU)
+#define CRC_GPOLYLL_GPOLYLL_SHIFT                (0U)
+#define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
+/*! @} */
+
+/*! @name GPOLYLU - CRC_GPOLYLU register */
+/*! @{ */
+#define CRC_GPOLYLU_GPOLYLU_MASK                 (0xFFU)
+#define CRC_GPOLYLU_GPOLYLU_SHIFT                (0U)
+#define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
+/*! @} */
+
+/*! @name GPOLYHL - CRC_GPOLYHL register */
+/*! @{ */
+#define CRC_GPOLYHL_GPOLYHL_MASK                 (0xFFU)
+#define CRC_GPOLYHL_GPOLYHL_SHIFT                (0U)
+#define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
+/*! @} */
+
+/*! @name GPOLYHU - CRC_GPOLYHU register */
+/*! @{ */
+#define CRC_GPOLYHU_GPOLYHU_MASK                 (0xFFU)
+#define CRC_GPOLYHU_GPOLYHU_SHIFT                (0U)
+#define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
+/*! @} */
+
+/*! @name GPOLYL - CRC_GPOLYL register */
+/*! @{ */
+#define CRC_GPOLYL_GPOLYL_MASK                   (0xFFFFU)
+#define CRC_GPOLYL_GPOLYL_SHIFT                  (0U)
+#define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
+/*! @} */
+
+/*! @name GPOLYH - CRC_GPOLYH register */
+/*! @{ */
+#define CRC_GPOLYH_GPOLYH_MASK                   (0xFFFFU)
+#define CRC_GPOLYH_GPOLYH_SHIFT                  (0U)
+#define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
+/*! @} */
+
+/*! @name CTRL - CRC Control register */
+/*! @{ */
+#define CRC_CTRL_TCRC_MASK                       (0x1000000U)
+#define CRC_CTRL_TCRC_SHIFT                      (24U)
+/*! TCRC - TCRC
+ *  0b0..16-bit CRC protocol.
+ *  0b1..32-bit CRC protocol.
+ */
+#define CRC_CTRL_TCRC(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
+#define CRC_CTRL_WAS_MASK                        (0x2000000U)
+#define CRC_CTRL_WAS_SHIFT                       (25U)
+/*! WAS - Write CRC Data Register As Seed
+ *  0b0..Writes to the CRC data register are data values.
+ *  0b1..Writes to the CRC data register are seed values.
+ */
+#define CRC_CTRL_WAS(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
+#define CRC_CTRL_FXOR_MASK                       (0x4000000U)
+#define CRC_CTRL_FXOR_SHIFT                      (26U)
+/*! FXOR - Complement Read Of CRC Data Register
+ *  0b0..No XOR on reading.
+ *  0b1..Invert or complement the read value of the CRC Data register.
+ */
+#define CRC_CTRL_FXOR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
+#define CRC_CTRL_TOTR_MASK                       (0x30000000U)
+#define CRC_CTRL_TOTR_SHIFT                      (28U)
+/*! TOTR - Type Of Transpose For Read
+ *  0b00..No transposition.
+ *  0b01..Bits in bytes are transposed; bytes are not transposed.
+ *  0b10..Both bits in bytes and bytes are transposed.
+ *  0b11..Only bytes are transposed; no bits in a byte are transposed.
+ */
+#define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK                        (0xC0000000U)
+#define CRC_CTRL_TOT_SHIFT                       (30U)
+/*! TOT - Type Of Transpose For Writes
+ *  0b00..No transposition.
+ *  0b01..Bits in bytes are transposed; bytes are not transposed.
+ *  0b10..Both bits in bytes and bytes are transposed.
+ *  0b11..Only bytes are transposed; no bits in a byte are transposed.
+ */
+#define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
+/*! @} */
+
+/*! @name CTRLHU - CRC_CTRLHU register */
+/*! @{ */
+#define CRC_CTRLHU_TCRC_MASK                     (0x1U)
+#define CRC_CTRLHU_TCRC_SHIFT                    (0U)
+/*! TCRC
+ *  0b0..16-bit CRC protocol.
+ *  0b1..32-bit CRC protocol.
+ */
+#define CRC_CTRLHU_TCRC(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
+#define CRC_CTRLHU_WAS_MASK                      (0x2U)
+#define CRC_CTRLHU_WAS_SHIFT                     (1U)
+/*! WAS
+ *  0b0..Writes to the CRC data register are data values.
+ *  0b1..Writes to the CRC data register are seed values.
+ */
+#define CRC_CTRLHU_WAS(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
+#define CRC_CTRLHU_FXOR_MASK                     (0x4U)
+#define CRC_CTRLHU_FXOR_SHIFT                    (2U)
+/*! FXOR
+ *  0b0..No XOR on reading.
+ *  0b1..Invert or complement the read value of the CRC Data register.
+ */
+#define CRC_CTRLHU_FXOR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
+#define CRC_CTRLHU_TOTR_MASK                     (0x30U)
+#define CRC_CTRLHU_TOTR_SHIFT                    (4U)
+/*! TOTR
+ *  0b00..No transposition.
+ *  0b01..Bits in bytes are transposed; bytes are not transposed.
+ *  0b10..Both bits in bytes and bytes are transposed.
+ *  0b11..Only bytes are transposed; no bits in a byte are transposed.
+ */
+#define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK                      (0xC0U)
+#define CRC_CTRLHU_TOT_SHIFT                     (6U)
+/*! TOT
+ *  0b00..No transposition.
+ *  0b01..Bits in bytes are transposed; bytes are not transposed.
+ *  0b10..Both bits in bytes and bytes are transposed.
+ *  0b11..Only bytes are transposed; no bits in a byte are transposed.
+ */
+#define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE                                 (0x4002F000u)
+/** Peripheral CRC base pointer */
+#define CRC0                                     ((CRC_Type *)CRC_BASE)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS                           { CRC_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS                            { CRC0 }
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /**< Control Register, offset: 0x0 */
+  __I  uint32_t ES;                                /**< Error Status Register, offset: 0x4 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t ERQ;                               /**< Enable Request Register, offset: 0xC */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t EEI;                               /**< Enable Error Interrupt Register, offset: 0x14 */
+  __O  uint8_t CEEI;                               /**< Clear Enable Error Interrupt Register, offset: 0x18 */
+  __O  uint8_t SEEI;                               /**< Set Enable Error Interrupt Register, offset: 0x19 */
+  __O  uint8_t CERQ;                               /**< Clear Enable Request Register, offset: 0x1A */
+  __O  uint8_t SERQ;                               /**< Set Enable Request Register, offset: 0x1B */
+  __O  uint8_t CDNE;                               /**< Clear DONE Status Bit Register, offset: 0x1C */
+  __O  uint8_t SSRT;                               /**< Set START Bit Register, offset: 0x1D */
+  __O  uint8_t CERR;                               /**< Clear Error Register, offset: 0x1E */
+  __O  uint8_t CINT;                               /**< Clear Interrupt Request Register, offset: 0x1F */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t INT;                               /**< Interrupt Request Register, offset: 0x24 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t ERR;                               /**< Error Register, offset: 0x2C */
+       uint8_t RESERVED_4[4];
+  __I  uint32_t HRS;                               /**< Hardware Request Status Register, offset: 0x34 */
+       uint8_t RESERVED_5[12];
+  __IO uint32_t EARS;                              /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
+       uint8_t RESERVED_6[184];
+  __IO uint8_t DCHPRI3;                            /**< Channel Priority Register, offset: 0x100 */
+  __IO uint8_t DCHPRI2;                            /**< Channel Priority Register, offset: 0x101 */
+  __IO uint8_t DCHPRI1;                            /**< Channel Priority Register, offset: 0x102 */
+  __IO uint8_t DCHPRI0;                            /**< Channel Priority Register, offset: 0x103 */
+  __IO uint8_t DCHPRI7;                            /**< Channel Priority Register, offset: 0x104 */
+  __IO uint8_t DCHPRI6;                            /**< Channel Priority Register, offset: 0x105 */
+  __IO uint8_t DCHPRI5;                            /**< Channel Priority Register, offset: 0x106 */
+  __IO uint8_t DCHPRI4;                            /**< Channel Priority Register, offset: 0x107 */
+  __IO uint8_t DCHPRI11;                           /**< Channel Priority Register, offset: 0x108 */
+  __IO uint8_t DCHPRI10;                           /**< Channel Priority Register, offset: 0x109 */
+  __IO uint8_t DCHPRI9;                            /**< Channel Priority Register, offset: 0x10A */
+  __IO uint8_t DCHPRI8;                            /**< Channel Priority Register, offset: 0x10B */
+  __IO uint8_t DCHPRI15;                           /**< Channel Priority Register, offset: 0x10C */
+  __IO uint8_t DCHPRI14;                           /**< Channel Priority Register, offset: 0x10D */
+  __IO uint8_t DCHPRI13;                           /**< Channel Priority Register, offset: 0x10E */
+  __IO uint8_t DCHPRI12;                           /**< Channel Priority Register, offset: 0x10F */
+       uint8_t RESERVED_7[3824];
+  struct {                                         /* offset: 0x1000, array step: 0x20 */
+    __IO uint32_t SADDR;                             /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+    __IO uint16_t SOFF;                              /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+    __IO uint16_t ATTR;                              /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+    union {                                          /* offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLNO;                       /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFNO;                    /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFYES;                   /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+    };
+    __IO uint32_t SLAST;                             /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+    __IO uint32_t DADDR;                             /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+    __IO uint16_t DOFF;                              /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+    union {                                          /* offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKNO;                     /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKYES;                    /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+    };
+    __IO uint32_t DLAST_SGA;                         /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+    __IO uint16_t CSR;                               /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+    union {                                          /* offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKNO;                     /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKYES;                    /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+    };
+  } TCD[16];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/*! @name CR - Control Register */
+/*! @{ */
+#define DMA_CR_EDBG_MASK                         (0x2U)
+#define DMA_CR_EDBG_SHIFT                        (1U)
+/*! EDBG - Enable Debug
+ *  0b0..When in debug mode, the DMA continues to operate.
+ *  0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
+ */
+#define DMA_CR_EDBG(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
+#define DMA_CR_ERCA_MASK                         (0x4U)
+#define DMA_CR_ERCA_SHIFT                        (2U)
+/*! ERCA - Enable Round Robin Channel Arbitration
+ *  0b0..Fixed priority arbitration is used for channel selection .
+ *  0b1..Round robin arbitration is used for channel selection .
+ */
+#define DMA_CR_ERCA(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
+#define DMA_CR_HOE_MASK                          (0x10U)
+#define DMA_CR_HOE_SHIFT                         (4U)
+/*! HOE - Halt On Error
+ *  0b0..Normal operation
+ *  0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
+ */
+#define DMA_CR_HOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
+#define DMA_CR_HALT_MASK                         (0x20U)
+#define DMA_CR_HALT_SHIFT                        (5U)
+/*! HALT - Halt DMA Operations
+ *  0b0..Normal operation
+ *  0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.
+ */
+#define DMA_CR_HALT(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
+#define DMA_CR_CLM_MASK                          (0x40U)
+#define DMA_CR_CLM_SHIFT                         (6U)
+/*! CLM - Continuous Link Mode
+ *  0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again.
+ *  0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.
+ */
+#define DMA_CR_CLM(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
+#define DMA_CR_EMLM_MASK                         (0x80U)
+#define DMA_CR_EMLM_SHIFT                        (7U)
+/*! EMLM - Enable Minor Loop Mapping
+ *  0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
+ *  0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.
+ */
+#define DMA_CR_EMLM(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
+#define DMA_CR_ECX_MASK                          (0x10000U)
+#define DMA_CR_ECX_SHIFT                         (16U)
+/*! ECX - Error Cancel Transfer
+ *  0b0..Normal operation
+ *  0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.
+ */
+#define DMA_CR_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
+#define DMA_CR_CX_MASK                           (0x20000U)
+#define DMA_CR_CX_SHIFT                          (17U)
+/*! CX - Cancel Transfer
+ *  0b0..Normal operation
+ *  0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
+ */
+#define DMA_CR_CX(x)                             (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
+#define DMA_CR_ACTIVE_MASK                       (0x80000000U)
+#define DMA_CR_ACTIVE_SHIFT                      (31U)
+/*! ACTIVE - DMA Active Status
+ *  0b0..eDMA is idle.
+ *  0b1..eDMA is executing a channel.
+ */
+#define DMA_CR_ACTIVE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
+/*! @} */
+
+/*! @name ES - Error Status Register */
+/*! @{ */
+#define DMA_ES_DBE_MASK                          (0x1U)
+#define DMA_ES_DBE_SHIFT                         (0U)
+/*! DBE - Destination Bus Error
+ *  0b0..No destination bus error
+ *  0b1..The last recorded error was a bus error on a destination write
+ */
+#define DMA_ES_DBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
+#define DMA_ES_SBE_MASK                          (0x2U)
+#define DMA_ES_SBE_SHIFT                         (1U)
+/*! SBE - Source Bus Error
+ *  0b0..No source bus error
+ *  0b1..The last recorded error was a bus error on a source read
+ */
+#define DMA_ES_SBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
+#define DMA_ES_SGE_MASK                          (0x4U)
+#define DMA_ES_SGE_SHIFT                         (2U)
+/*! SGE - Scatter/Gather Configuration Error
+ *  0b0..No scatter/gather configuration error
+ *  0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
+ */
+#define DMA_ES_SGE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
+#define DMA_ES_NCE_MASK                          (0x8U)
+#define DMA_ES_NCE_SHIFT                         (3U)
+/*! NCE - NBYTES/CITER Configuration Error
+ *  0b0..No NBYTES/CITER configuration error
+ *  0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
+ */
+#define DMA_ES_NCE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
+#define DMA_ES_DOE_MASK                          (0x10U)
+#define DMA_ES_DOE_SHIFT                         (4U)
+/*! DOE - Destination Offset Error
+ *  0b0..No destination offset configuration error
+ *  0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
+ */
+#define DMA_ES_DOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
+#define DMA_ES_DAE_MASK                          (0x20U)
+#define DMA_ES_DAE_SHIFT                         (5U)
+/*! DAE - Destination Address Error
+ *  0b0..No destination address configuration error
+ *  0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
+ */
+#define DMA_ES_DAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
+#define DMA_ES_SOE_MASK                          (0x40U)
+#define DMA_ES_SOE_SHIFT                         (6U)
+/*! SOE - Source Offset Error
+ *  0b0..No source offset configuration error
+ *  0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
+ */
+#define DMA_ES_SOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
+#define DMA_ES_SAE_MASK                          (0x80U)
+#define DMA_ES_SAE_SHIFT                         (7U)
+/*! SAE - Source Address Error
+ *  0b0..No source address configuration error.
+ *  0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
+ */
+#define DMA_ES_SAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
+#define DMA_ES_ERRCHN_MASK                       (0xF00U)
+#define DMA_ES_ERRCHN_SHIFT                      (8U)
+#define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK                          (0x4000U)
+#define DMA_ES_CPE_SHIFT                         (14U)
+/*! CPE - Channel Priority Error
+ *  0b0..No channel priority error
+ *  0b1..The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique.
+ */
+#define DMA_ES_CPE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
+#define DMA_ES_ECX_MASK                          (0x10000U)
+#define DMA_ES_ECX_SHIFT                         (16U)
+/*! ECX - Transfer Canceled
+ *  0b0..No canceled transfers
+ *  0b1..The last recorded entry was a canceled transfer by the error cancel transfer input
+ */
+#define DMA_ES_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
+#define DMA_ES_VLD_MASK                          (0x80000000U)
+#define DMA_ES_VLD_SHIFT                         (31U)
+/*! VLD - VLD
+ *  0b0..No ERR bits are set.
+ *  0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.
+ */
+#define DMA_ES_VLD(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
+/*! @} */
+
+/*! @name ERQ - Enable Request Register */
+/*! @{ */
+#define DMA_ERQ_ERQ0_MASK                        (0x1U)
+#define DMA_ERQ_ERQ0_SHIFT                       (0U)
+/*! ERQ0 - Enable DMA Request 0
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
+#define DMA_ERQ_ERQ1_MASK                        (0x2U)
+#define DMA_ERQ_ERQ1_SHIFT                       (1U)
+/*! ERQ1 - Enable DMA Request 1
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
+#define DMA_ERQ_ERQ2_MASK                        (0x4U)
+#define DMA_ERQ_ERQ2_SHIFT                       (2U)
+/*! ERQ2 - Enable DMA Request 2
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
+#define DMA_ERQ_ERQ3_MASK                        (0x8U)
+#define DMA_ERQ_ERQ3_SHIFT                       (3U)
+/*! ERQ3 - Enable DMA Request 3
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
+#define DMA_ERQ_ERQ4_MASK                        (0x10U)
+#define DMA_ERQ_ERQ4_SHIFT                       (4U)
+/*! ERQ4 - Enable DMA Request 4
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
+#define DMA_ERQ_ERQ5_MASK                        (0x20U)
+#define DMA_ERQ_ERQ5_SHIFT                       (5U)
+/*! ERQ5 - Enable DMA Request 5
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
+#define DMA_ERQ_ERQ6_MASK                        (0x40U)
+#define DMA_ERQ_ERQ6_SHIFT                       (6U)
+/*! ERQ6 - Enable DMA Request 6
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
+#define DMA_ERQ_ERQ7_MASK                        (0x80U)
+#define DMA_ERQ_ERQ7_SHIFT                       (7U)
+/*! ERQ7 - Enable DMA Request 7
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
+#define DMA_ERQ_ERQ8_MASK                        (0x100U)
+#define DMA_ERQ_ERQ8_SHIFT                       (8U)
+/*! ERQ8 - Enable DMA Request 8
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
+#define DMA_ERQ_ERQ9_MASK                        (0x200U)
+#define DMA_ERQ_ERQ9_SHIFT                       (9U)
+/*! ERQ9 - Enable DMA Request 9
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
+#define DMA_ERQ_ERQ10_MASK                       (0x400U)
+#define DMA_ERQ_ERQ10_SHIFT                      (10U)
+/*! ERQ10 - Enable DMA Request 10
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
+#define DMA_ERQ_ERQ11_MASK                       (0x800U)
+#define DMA_ERQ_ERQ11_SHIFT                      (11U)
+/*! ERQ11 - Enable DMA Request 11
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
+#define DMA_ERQ_ERQ12_MASK                       (0x1000U)
+#define DMA_ERQ_ERQ12_SHIFT                      (12U)
+/*! ERQ12 - Enable DMA Request 12
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
+#define DMA_ERQ_ERQ13_MASK                       (0x2000U)
+#define DMA_ERQ_ERQ13_SHIFT                      (13U)
+/*! ERQ13 - Enable DMA Request 13
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
+#define DMA_ERQ_ERQ14_MASK                       (0x4000U)
+#define DMA_ERQ_ERQ14_SHIFT                      (14U)
+/*! ERQ14 - Enable DMA Request 14
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
+#define DMA_ERQ_ERQ15_MASK                       (0x8000U)
+#define DMA_ERQ_ERQ15_SHIFT                      (15U)
+/*! ERQ15 - Enable DMA Request 15
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
+/*! @} */
+
+/*! @name EEI - Enable Error Interrupt Register */
+/*! @{ */
+#define DMA_EEI_EEI0_MASK                        (0x1U)
+#define DMA_EEI_EEI0_SHIFT                       (0U)
+/*! EEI0 - Enable Error Interrupt 0
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
+#define DMA_EEI_EEI1_MASK                        (0x2U)
+#define DMA_EEI_EEI1_SHIFT                       (1U)
+/*! EEI1 - Enable Error Interrupt 1
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
+#define DMA_EEI_EEI2_MASK                        (0x4U)
+#define DMA_EEI_EEI2_SHIFT                       (2U)
+/*! EEI2 - Enable Error Interrupt 2
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
+#define DMA_EEI_EEI3_MASK                        (0x8U)
+#define DMA_EEI_EEI3_SHIFT                       (3U)
+/*! EEI3 - Enable Error Interrupt 3
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
+#define DMA_EEI_EEI4_MASK                        (0x10U)
+#define DMA_EEI_EEI4_SHIFT                       (4U)
+/*! EEI4 - Enable Error Interrupt 4
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
+#define DMA_EEI_EEI5_MASK                        (0x20U)
+#define DMA_EEI_EEI5_SHIFT                       (5U)
+/*! EEI5 - Enable Error Interrupt 5
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
+#define DMA_EEI_EEI6_MASK                        (0x40U)
+#define DMA_EEI_EEI6_SHIFT                       (6U)
+/*! EEI6 - Enable Error Interrupt 6
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
+#define DMA_EEI_EEI7_MASK                        (0x80U)
+#define DMA_EEI_EEI7_SHIFT                       (7U)
+/*! EEI7 - Enable Error Interrupt 7
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
+#define DMA_EEI_EEI8_MASK                        (0x100U)
+#define DMA_EEI_EEI8_SHIFT                       (8U)
+/*! EEI8 - Enable Error Interrupt 8
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
+#define DMA_EEI_EEI9_MASK                        (0x200U)
+#define DMA_EEI_EEI9_SHIFT                       (9U)
+/*! EEI9 - Enable Error Interrupt 9
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
+#define DMA_EEI_EEI10_MASK                       (0x400U)
+#define DMA_EEI_EEI10_SHIFT                      (10U)
+/*! EEI10 - Enable Error Interrupt 10
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
+#define DMA_EEI_EEI11_MASK                       (0x800U)
+#define DMA_EEI_EEI11_SHIFT                      (11U)
+/*! EEI11 - Enable Error Interrupt 11
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
+#define DMA_EEI_EEI12_MASK                       (0x1000U)
+#define DMA_EEI_EEI12_SHIFT                      (12U)
+/*! EEI12 - Enable Error Interrupt 12
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
+#define DMA_EEI_EEI13_MASK                       (0x2000U)
+#define DMA_EEI_EEI13_SHIFT                      (13U)
+/*! EEI13 - Enable Error Interrupt 13
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
+#define DMA_EEI_EEI14_MASK                       (0x4000U)
+#define DMA_EEI_EEI14_SHIFT                      (14U)
+/*! EEI14 - Enable Error Interrupt 14
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
+#define DMA_EEI_EEI15_MASK                       (0x8000U)
+#define DMA_EEI_EEI15_SHIFT                      (15U)
+/*! EEI15 - Enable Error Interrupt 15
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
+/*! @} */
+
+/*! @name CEEI - Clear Enable Error Interrupt Register */
+/*! @{ */
+#define DMA_CEEI_CEEI_MASK                       (0xFU)
+#define DMA_CEEI_CEEI_SHIFT                      (0U)
+#define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK                       (0x40U)
+#define DMA_CEEI_CAEE_SHIFT                      (6U)
+/*! CAEE - Clear All Enable Error Interrupts
+ *  0b0..Clear only the EEI bit specified in the CEEI field
+ *  0b1..Clear all bits in EEI
+ */
+#define DMA_CEEI_CAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
+#define DMA_CEEI_NOP_MASK                        (0x80U)
+#define DMA_CEEI_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_CEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
+/*! @} */
+
+/*! @name SEEI - Set Enable Error Interrupt Register */
+/*! @{ */
+#define DMA_SEEI_SEEI_MASK                       (0xFU)
+#define DMA_SEEI_SEEI_SHIFT                      (0U)
+#define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK                       (0x40U)
+#define DMA_SEEI_SAEE_SHIFT                      (6U)
+/*! SAEE - Sets All Enable Error Interrupts
+ *  0b0..Set only the EEI bit specified in the SEEI field.
+ *  0b1..Sets all bits in EEI
+ */
+#define DMA_SEEI_SAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
+#define DMA_SEEI_NOP_MASK                        (0x80U)
+#define DMA_SEEI_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_SEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
+/*! @} */
+
+/*! @name CERQ - Clear Enable Request Register */
+/*! @{ */
+#define DMA_CERQ_CERQ_MASK                       (0xFU)
+#define DMA_CERQ_CERQ_SHIFT                      (0U)
+#define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK                       (0x40U)
+#define DMA_CERQ_CAER_SHIFT                      (6U)
+/*! CAER - Clear All Enable Requests
+ *  0b0..Clear only the ERQ bit specified in the CERQ field
+ *  0b1..Clear all bits in ERQ
+ */
+#define DMA_CERQ_CAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
+#define DMA_CERQ_NOP_MASK                        (0x80U)
+#define DMA_CERQ_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_CERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
+/*! @} */
+
+/*! @name SERQ - Set Enable Request Register */
+/*! @{ */
+#define DMA_SERQ_SERQ_MASK                       (0xFU)
+#define DMA_SERQ_SERQ_SHIFT                      (0U)
+#define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK                       (0x40U)
+#define DMA_SERQ_SAER_SHIFT                      (6U)
+/*! SAER - Set All Enable Requests
+ *  0b0..Set only the ERQ bit specified in the SERQ field
+ *  0b1..Set all bits in ERQ
+ */
+#define DMA_SERQ_SAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
+#define DMA_SERQ_NOP_MASK                        (0x80U)
+#define DMA_SERQ_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_SERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
+/*! @} */
+
+/*! @name CDNE - Clear DONE Status Bit Register */
+/*! @{ */
+#define DMA_CDNE_CDNE_MASK                       (0xFU)
+#define DMA_CDNE_CDNE_SHIFT                      (0U)
+#define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK                       (0x40U)
+#define DMA_CDNE_CADN_SHIFT                      (6U)
+/*! CADN - Clears All DONE Bits
+ *  0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
+ *  0b1..Clears all bits in TCDn_CSR[DONE]
+ */
+#define DMA_CDNE_CADN(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
+#define DMA_CDNE_NOP_MASK                        (0x80U)
+#define DMA_CDNE_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_CDNE_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
+/*! @} */
+
+/*! @name SSRT - Set START Bit Register */
+/*! @{ */
+#define DMA_SSRT_SSRT_MASK                       (0xFU)
+#define DMA_SSRT_SSRT_SHIFT                      (0U)
+#define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK                       (0x40U)
+#define DMA_SSRT_SAST_SHIFT                      (6U)
+/*! SAST - Set All START Bits (activates all channels)
+ *  0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field
+ *  0b1..Set all bits in TCDn_CSR[START]
+ */
+#define DMA_SSRT_SAST(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
+#define DMA_SSRT_NOP_MASK                        (0x80U)
+#define DMA_SSRT_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_SSRT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
+/*! @} */
+
+/*! @name CERR - Clear Error Register */
+/*! @{ */
+#define DMA_CERR_CERR_MASK                       (0xFU)
+#define DMA_CERR_CERR_SHIFT                      (0U)
+#define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK                       (0x40U)
+#define DMA_CERR_CAEI_SHIFT                      (6U)
+/*! CAEI - Clear All Error Indicators
+ *  0b0..Clear only the ERR bit specified in the CERR field
+ *  0b1..Clear all bits in ERR
+ */
+#define DMA_CERR_CAEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
+#define DMA_CERR_NOP_MASK                        (0x80U)
+#define DMA_CERR_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_CERR_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
+/*! @} */
+
+/*! @name CINT - Clear Interrupt Request Register */
+/*! @{ */
+#define DMA_CINT_CINT_MASK                       (0xFU)
+#define DMA_CINT_CINT_SHIFT                      (0U)
+#define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK                       (0x40U)
+#define DMA_CINT_CAIR_SHIFT                      (6U)
+/*! CAIR - Clear All Interrupt Requests
+ *  0b0..Clear only the INT bit specified in the CINT field
+ *  0b1..Clear all bits in INT
+ */
+#define DMA_CINT_CAIR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
+#define DMA_CINT_NOP_MASK                        (0x80U)
+#define DMA_CINT_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_CINT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
+/*! @} */
+
+/*! @name INT - Interrupt Request Register */
+/*! @{ */
+#define DMA_INT_INT0_MASK                        (0x1U)
+#define DMA_INT_INT0_SHIFT                       (0U)
+/*! INT0 - Interrupt Request 0
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
+#define DMA_INT_INT1_MASK                        (0x2U)
+#define DMA_INT_INT1_SHIFT                       (1U)
+/*! INT1 - Interrupt Request 1
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
+#define DMA_INT_INT2_MASK                        (0x4U)
+#define DMA_INT_INT2_SHIFT                       (2U)
+/*! INT2 - Interrupt Request 2
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
+#define DMA_INT_INT3_MASK                        (0x8U)
+#define DMA_INT_INT3_SHIFT                       (3U)
+/*! INT3 - Interrupt Request 3
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
+#define DMA_INT_INT4_MASK                        (0x10U)
+#define DMA_INT_INT4_SHIFT                       (4U)
+/*! INT4 - Interrupt Request 4
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
+#define DMA_INT_INT5_MASK                        (0x20U)
+#define DMA_INT_INT5_SHIFT                       (5U)
+/*! INT5 - Interrupt Request 5
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
+#define DMA_INT_INT6_MASK                        (0x40U)
+#define DMA_INT_INT6_SHIFT                       (6U)
+/*! INT6 - Interrupt Request 6
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
+#define DMA_INT_INT7_MASK                        (0x80U)
+#define DMA_INT_INT7_SHIFT                       (7U)
+/*! INT7 - Interrupt Request 7
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
+#define DMA_INT_INT8_MASK                        (0x100U)
+#define DMA_INT_INT8_SHIFT                       (8U)
+/*! INT8 - Interrupt Request 8
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
+#define DMA_INT_INT9_MASK                        (0x200U)
+#define DMA_INT_INT9_SHIFT                       (9U)
+/*! INT9 - Interrupt Request 9
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
+#define DMA_INT_INT10_MASK                       (0x400U)
+#define DMA_INT_INT10_SHIFT                      (10U)
+/*! INT10 - Interrupt Request 10
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
+#define DMA_INT_INT11_MASK                       (0x800U)
+#define DMA_INT_INT11_SHIFT                      (11U)
+/*! INT11 - Interrupt Request 11
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
+#define DMA_INT_INT12_MASK                       (0x1000U)
+#define DMA_INT_INT12_SHIFT                      (12U)
+/*! INT12 - Interrupt Request 12
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
+#define DMA_INT_INT13_MASK                       (0x2000U)
+#define DMA_INT_INT13_SHIFT                      (13U)
+/*! INT13 - Interrupt Request 13
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
+#define DMA_INT_INT14_MASK                       (0x4000U)
+#define DMA_INT_INT14_SHIFT                      (14U)
+/*! INT14 - Interrupt Request 14
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
+#define DMA_INT_INT15_MASK                       (0x8000U)
+#define DMA_INT_INT15_SHIFT                      (15U)
+/*! INT15 - Interrupt Request 15
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
+/*! @} */
+
+/*! @name ERR - Error Register */
+/*! @{ */
+#define DMA_ERR_ERR0_MASK                        (0x1U)
+#define DMA_ERR_ERR0_SHIFT                       (0U)
+/*! ERR0 - Error In Channel 0
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
+#define DMA_ERR_ERR1_MASK                        (0x2U)
+#define DMA_ERR_ERR1_SHIFT                       (1U)
+/*! ERR1 - Error In Channel 1
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
+#define DMA_ERR_ERR2_MASK                        (0x4U)
+#define DMA_ERR_ERR2_SHIFT                       (2U)
+/*! ERR2 - Error In Channel 2
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
+#define DMA_ERR_ERR3_MASK                        (0x8U)
+#define DMA_ERR_ERR3_SHIFT                       (3U)
+/*! ERR3 - Error In Channel 3
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
+#define DMA_ERR_ERR4_MASK                        (0x10U)
+#define DMA_ERR_ERR4_SHIFT                       (4U)
+/*! ERR4 - Error In Channel 4
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
+#define DMA_ERR_ERR5_MASK                        (0x20U)
+#define DMA_ERR_ERR5_SHIFT                       (5U)
+/*! ERR5 - Error In Channel 5
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
+#define DMA_ERR_ERR6_MASK                        (0x40U)
+#define DMA_ERR_ERR6_SHIFT                       (6U)
+/*! ERR6 - Error In Channel 6
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
+#define DMA_ERR_ERR7_MASK                        (0x80U)
+#define DMA_ERR_ERR7_SHIFT                       (7U)
+/*! ERR7 - Error In Channel 7
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
+#define DMA_ERR_ERR8_MASK                        (0x100U)
+#define DMA_ERR_ERR8_SHIFT                       (8U)
+/*! ERR8 - Error In Channel 8
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
+#define DMA_ERR_ERR9_MASK                        (0x200U)
+#define DMA_ERR_ERR9_SHIFT                       (9U)
+/*! ERR9 - Error In Channel 9
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
+#define DMA_ERR_ERR10_MASK                       (0x400U)
+#define DMA_ERR_ERR10_SHIFT                      (10U)
+/*! ERR10 - Error In Channel 10
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
+#define DMA_ERR_ERR11_MASK                       (0x800U)
+#define DMA_ERR_ERR11_SHIFT                      (11U)
+/*! ERR11 - Error In Channel 11
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
+#define DMA_ERR_ERR12_MASK                       (0x1000U)
+#define DMA_ERR_ERR12_SHIFT                      (12U)
+/*! ERR12 - Error In Channel 12
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
+#define DMA_ERR_ERR13_MASK                       (0x2000U)
+#define DMA_ERR_ERR13_SHIFT                      (13U)
+/*! ERR13 - Error In Channel 13
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
+#define DMA_ERR_ERR14_MASK                       (0x4000U)
+#define DMA_ERR_ERR14_SHIFT                      (14U)
+/*! ERR14 - Error In Channel 14
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
+#define DMA_ERR_ERR15_MASK                       (0x8000U)
+#define DMA_ERR_ERR15_SHIFT                      (15U)
+/*! ERR15 - Error In Channel 15
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
+/*! @} */
+
+/*! @name HRS - Hardware Request Status Register */
+/*! @{ */
+#define DMA_HRS_HRS0_MASK                        (0x1U)
+#define DMA_HRS_HRS0_SHIFT                       (0U)
+/*! HRS0 - Hardware Request Status Channel 0
+ *  0b0..A hardware service request for channel 0 is not present
+ *  0b1..A hardware service request for channel 0 is present
+ */
+#define DMA_HRS_HRS0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
+#define DMA_HRS_HRS1_MASK                        (0x2U)
+#define DMA_HRS_HRS1_SHIFT                       (1U)
+/*! HRS1 - Hardware Request Status Channel 1
+ *  0b0..A hardware service request for channel 1 is not present
+ *  0b1..A hardware service request for channel 1 is present
+ */
+#define DMA_HRS_HRS1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
+#define DMA_HRS_HRS2_MASK                        (0x4U)
+#define DMA_HRS_HRS2_SHIFT                       (2U)
+/*! HRS2 - Hardware Request Status Channel 2
+ *  0b0..A hardware service request for channel 2 is not present
+ *  0b1..A hardware service request for channel 2 is present
+ */
+#define DMA_HRS_HRS2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
+#define DMA_HRS_HRS3_MASK                        (0x8U)
+#define DMA_HRS_HRS3_SHIFT                       (3U)
+/*! HRS3 - Hardware Request Status Channel 3
+ *  0b0..A hardware service request for channel 3 is not present
+ *  0b1..A hardware service request for channel 3 is present
+ */
+#define DMA_HRS_HRS3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
+#define DMA_HRS_HRS4_MASK                        (0x10U)
+#define DMA_HRS_HRS4_SHIFT                       (4U)
+/*! HRS4 - Hardware Request Status Channel 4
+ *  0b0..A hardware service request for channel 4 is not present
+ *  0b1..A hardware service request for channel 4 is present
+ */
+#define DMA_HRS_HRS4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
+#define DMA_HRS_HRS5_MASK                        (0x20U)
+#define DMA_HRS_HRS5_SHIFT                       (5U)
+/*! HRS5 - Hardware Request Status Channel 5
+ *  0b0..A hardware service request for channel 5 is not present
+ *  0b1..A hardware service request for channel 5 is present
+ */
+#define DMA_HRS_HRS5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
+#define DMA_HRS_HRS6_MASK                        (0x40U)
+#define DMA_HRS_HRS6_SHIFT                       (6U)
+/*! HRS6 - Hardware Request Status Channel 6
+ *  0b0..A hardware service request for channel 6 is not present
+ *  0b1..A hardware service request for channel 6 is present
+ */
+#define DMA_HRS_HRS6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
+#define DMA_HRS_HRS7_MASK                        (0x80U)
+#define DMA_HRS_HRS7_SHIFT                       (7U)
+/*! HRS7 - Hardware Request Status Channel 7
+ *  0b0..A hardware service request for channel 7 is not present
+ *  0b1..A hardware service request for channel 7 is present
+ */
+#define DMA_HRS_HRS7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
+#define DMA_HRS_HRS8_MASK                        (0x100U)
+#define DMA_HRS_HRS8_SHIFT                       (8U)
+/*! HRS8 - Hardware Request Status Channel 8
+ *  0b0..A hardware service request for channel 8 is not present
+ *  0b1..A hardware service request for channel 8 is present
+ */
+#define DMA_HRS_HRS8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
+#define DMA_HRS_HRS9_MASK                        (0x200U)
+#define DMA_HRS_HRS9_SHIFT                       (9U)
+/*! HRS9 - Hardware Request Status Channel 9
+ *  0b0..A hardware service request for channel 9 is not present
+ *  0b1..A hardware service request for channel 9 is present
+ */
+#define DMA_HRS_HRS9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
+#define DMA_HRS_HRS10_MASK                       (0x400U)
+#define DMA_HRS_HRS10_SHIFT                      (10U)
+/*! HRS10 - Hardware Request Status Channel 10
+ *  0b0..A hardware service request for channel 10 is not present
+ *  0b1..A hardware service request for channel 10 is present
+ */
+#define DMA_HRS_HRS10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
+#define DMA_HRS_HRS11_MASK                       (0x800U)
+#define DMA_HRS_HRS11_SHIFT                      (11U)
+/*! HRS11 - Hardware Request Status Channel 11
+ *  0b0..A hardware service request for channel 11 is not present
+ *  0b1..A hardware service request for channel 11 is present
+ */
+#define DMA_HRS_HRS11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
+#define DMA_HRS_HRS12_MASK                       (0x1000U)
+#define DMA_HRS_HRS12_SHIFT                      (12U)
+/*! HRS12 - Hardware Request Status Channel 12
+ *  0b0..A hardware service request for channel 12 is not present
+ *  0b1..A hardware service request for channel 12 is present
+ */
+#define DMA_HRS_HRS12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
+#define DMA_HRS_HRS13_MASK                       (0x2000U)
+#define DMA_HRS_HRS13_SHIFT                      (13U)
+/*! HRS13 - Hardware Request Status Channel 13
+ *  0b0..A hardware service request for channel 13 is not present
+ *  0b1..A hardware service request for channel 13 is present
+ */
+#define DMA_HRS_HRS13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
+#define DMA_HRS_HRS14_MASK                       (0x4000U)
+#define DMA_HRS_HRS14_SHIFT                      (14U)
+/*! HRS14 - Hardware Request Status Channel 14
+ *  0b0..A hardware service request for channel 14 is not present
+ *  0b1..A hardware service request for channel 14 is present
+ */
+#define DMA_HRS_HRS14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
+#define DMA_HRS_HRS15_MASK                       (0x8000U)
+#define DMA_HRS_HRS15_SHIFT                      (15U)
+/*! HRS15 - Hardware Request Status Channel 15
+ *  0b0..A hardware service request for channel 15 is not present
+ *  0b1..A hardware service request for channel 15 is present
+ */
+#define DMA_HRS_HRS15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
+/*! @} */
+
+/*! @name EARS - Enable Asynchronous Request in Stop Register */
+/*! @{ */
+#define DMA_EARS_EDREQ_0_MASK                    (0x1U)
+#define DMA_EARS_EDREQ_0_SHIFT                   (0U)
+/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0.
+ *  0b0..Disable asynchronous DMA request for channel 0.
+ *  0b1..Enable asynchronous DMA request for channel 0.
+ */
+#define DMA_EARS_EDREQ_0(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
+#define DMA_EARS_EDREQ_1_MASK                    (0x2U)
+#define DMA_EARS_EDREQ_1_SHIFT                   (1U)
+/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1.
+ *  0b0..Disable asynchronous DMA request for channel 1
+ *  0b1..Enable asynchronous DMA request for channel 1.
+ */
+#define DMA_EARS_EDREQ_1(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
+#define DMA_EARS_EDREQ_2_MASK                    (0x4U)
+#define DMA_EARS_EDREQ_2_SHIFT                   (2U)
+/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2.
+ *  0b0..Disable asynchronous DMA request for channel 2.
+ *  0b1..Enable asynchronous DMA request for channel 2.
+ */
+#define DMA_EARS_EDREQ_2(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
+#define DMA_EARS_EDREQ_3_MASK                    (0x8U)
+#define DMA_EARS_EDREQ_3_SHIFT                   (3U)
+/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3.
+ *  0b0..Disable asynchronous DMA request for channel 3.
+ *  0b1..Enable asynchronous DMA request for channel 3.
+ */
+#define DMA_EARS_EDREQ_3(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
+#define DMA_EARS_EDREQ_4_MASK                    (0x10U)
+#define DMA_EARS_EDREQ_4_SHIFT                   (4U)
+/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4
+ *  0b0..Disable asynchronous DMA request for channel 4.
+ *  0b1..Enable asynchronous DMA request for channel 4.
+ */
+#define DMA_EARS_EDREQ_4(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
+#define DMA_EARS_EDREQ_5_MASK                    (0x20U)
+#define DMA_EARS_EDREQ_5_SHIFT                   (5U)
+/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5
+ *  0b0..Disable asynchronous DMA request for channel 5.
+ *  0b1..Enable asynchronous DMA request for channel 5.
+ */
+#define DMA_EARS_EDREQ_5(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
+#define DMA_EARS_EDREQ_6_MASK                    (0x40U)
+#define DMA_EARS_EDREQ_6_SHIFT                   (6U)
+/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6
+ *  0b0..Disable asynchronous DMA request for channel 6.
+ *  0b1..Enable asynchronous DMA request for channel 6.
+ */
+#define DMA_EARS_EDREQ_6(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
+#define DMA_EARS_EDREQ_7_MASK                    (0x80U)
+#define DMA_EARS_EDREQ_7_SHIFT                   (7U)
+/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7
+ *  0b0..Disable asynchronous DMA request for channel 7.
+ *  0b1..Enable asynchronous DMA request for channel 7.
+ */
+#define DMA_EARS_EDREQ_7(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
+#define DMA_EARS_EDREQ_8_MASK                    (0x100U)
+#define DMA_EARS_EDREQ_8_SHIFT                   (8U)
+/*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8
+ *  0b0..Disable asynchronous DMA request for channel 8.
+ *  0b1..Enable asynchronous DMA request for channel 8.
+ */
+#define DMA_EARS_EDREQ_8(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
+#define DMA_EARS_EDREQ_9_MASK                    (0x200U)
+#define DMA_EARS_EDREQ_9_SHIFT                   (9U)
+/*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9
+ *  0b0..Disable asynchronous DMA request for channel 9.
+ *  0b1..Enable asynchronous DMA request for channel 9.
+ */
+#define DMA_EARS_EDREQ_9(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
+#define DMA_EARS_EDREQ_10_MASK                   (0x400U)
+#define DMA_EARS_EDREQ_10_SHIFT                  (10U)
+/*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10
+ *  0b0..Disable asynchronous DMA request for channel 10.
+ *  0b1..Enable asynchronous DMA request for channel 10.
+ */
+#define DMA_EARS_EDREQ_10(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
+#define DMA_EARS_EDREQ_11_MASK                   (0x800U)
+#define DMA_EARS_EDREQ_11_SHIFT                  (11U)
+/*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11
+ *  0b0..Disable asynchronous DMA request for channel 11.
+ *  0b1..Enable asynchronous DMA request for channel 11.
+ */
+#define DMA_EARS_EDREQ_11(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
+#define DMA_EARS_EDREQ_12_MASK                   (0x1000U)
+#define DMA_EARS_EDREQ_12_SHIFT                  (12U)
+/*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12
+ *  0b0..Disable asynchronous DMA request for channel 12.
+ *  0b1..Enable asynchronous DMA request for channel 12.
+ */
+#define DMA_EARS_EDREQ_12(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
+#define DMA_EARS_EDREQ_13_MASK                   (0x2000U)
+#define DMA_EARS_EDREQ_13_SHIFT                  (13U)
+/*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13
+ *  0b0..Disable asynchronous DMA request for channel 13.
+ *  0b1..Enable asynchronous DMA request for channel 13.
+ */
+#define DMA_EARS_EDREQ_13(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
+#define DMA_EARS_EDREQ_14_MASK                   (0x4000U)
+#define DMA_EARS_EDREQ_14_SHIFT                  (14U)
+/*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14
+ *  0b0..Disable asynchronous DMA request for channel 14.
+ *  0b1..Enable asynchronous DMA request for channel 14.
+ */
+#define DMA_EARS_EDREQ_14(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
+#define DMA_EARS_EDREQ_15_MASK                   (0x8000U)
+#define DMA_EARS_EDREQ_15_SHIFT                  (15U)
+/*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15
+ *  0b0..Disable asynchronous DMA request for channel 15.
+ *  0b1..Enable asynchronous DMA request for channel 15.
+ */
+#define DMA_EARS_EDREQ_15(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
+/*! @} */
+
+/*! @name DCHPRI3 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI3_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI3_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI3_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI3_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
+#define DMA_DCHPRI3_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI3_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI3_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI2 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI2_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI2_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI2_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI2_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI2_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
+#define DMA_DCHPRI2_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI2_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI2_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI1 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI1_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI1_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI1_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI1_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI1_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
+#define DMA_DCHPRI1_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI1_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI1_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI0 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI0_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI0_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI0_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI0_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI0_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
+#define DMA_DCHPRI0_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI0_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI0_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI7 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI7_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI7_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI7_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
+#define DMA_DCHPRI7_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI7_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI7_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
+#define DMA_DCHPRI7_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI7_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI7_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI6 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI6_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI6_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI6_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
+#define DMA_DCHPRI6_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI6_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI6_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
+#define DMA_DCHPRI6_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI6_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI6_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI5 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI5_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI5_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI5_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
+#define DMA_DCHPRI5_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI5_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI5_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
+#define DMA_DCHPRI5_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI5_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI5_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI4 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI4_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI4_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI4_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
+#define DMA_DCHPRI4_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI4_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI4_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
+#define DMA_DCHPRI4_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI4_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI4_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI11 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI11_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI11_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI11_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
+#define DMA_DCHPRI11_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI11_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI11_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
+#define DMA_DCHPRI11_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI11_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI11_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI10 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI10_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI10_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI10_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
+#define DMA_DCHPRI10_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI10_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI10_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
+#define DMA_DCHPRI10_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI10_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI10_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI9 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI9_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI9_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI9_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
+#define DMA_DCHPRI9_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI9_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI9_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
+#define DMA_DCHPRI9_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI9_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI9_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI8 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI8_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI8_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI8_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
+#define DMA_DCHPRI8_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI8_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI8_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
+#define DMA_DCHPRI8_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI8_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI8_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI15 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI15_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI15_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI15_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
+#define DMA_DCHPRI15_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI15_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI15_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
+#define DMA_DCHPRI15_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI15_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI15_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI14 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI14_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI14_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI14_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
+#define DMA_DCHPRI14_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI14_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI14_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
+#define DMA_DCHPRI14_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI14_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI14_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI13 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI13_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI13_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI13_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
+#define DMA_DCHPRI13_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI13_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI13_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
+#define DMA_DCHPRI13_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI13_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI13_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI12 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI12_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI12_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI12_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
+#define DMA_DCHPRI12_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI12_DPA_SHIFT                   (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI12_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
+#define DMA_DCHPRI12_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI12_ECP_SHIFT                   (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI12_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
+/*! @} */
+
+/*! @name SADDR - TCD Source Address */
+/*! @{ */
+#define DMA_SADDR_SADDR_MASK                     (0xFFFFFFFFU)
+#define DMA_SADDR_SADDR_SHIFT                    (0U)
+#define DMA_SADDR_SADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
+/*! @} */
+
+/* The count of DMA_SADDR */
+#define DMA_SADDR_COUNT                          (16U)
+
+/*! @name SOFF - TCD Signed Source Address Offset */
+/*! @{ */
+#define DMA_SOFF_SOFF_MASK                       (0xFFFFU)
+#define DMA_SOFF_SOFF_SHIFT                      (0U)
+#define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
+/*! @} */
+
+/* The count of DMA_SOFF */
+#define DMA_SOFF_COUNT                           (16U)
+
+/*! @name ATTR - TCD Transfer Attributes */
+/*! @{ */
+#define DMA_ATTR_DSIZE_MASK                      (0x7U)
+#define DMA_ATTR_DSIZE_SHIFT                     (0U)
+#define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK                       (0xF8U)
+#define DMA_ATTR_DMOD_SHIFT                      (3U)
+#define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK                      (0x700U)
+#define DMA_ATTR_SSIZE_SHIFT                     (8U)
+/*! SSIZE - Source data transfer size
+ *  0b000..8-bit
+ *  0b001..16-bit
+ *  0b010..32-bit
+ *  0b011..Reserved
+ *  0b100..16-byte burst
+ *  0b101..32-byte burst
+ *  0b110..Reserved
+ *  0b111..Reserved
+ */
+#define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK                       (0xF800U)
+#define DMA_ATTR_SMOD_SHIFT                      (11U)
+/*! SMOD - Source Address Modulo
+ *  0b00000..Source address modulo feature is disabled
+ *  0b00001-0b11111..This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
+ */
+#define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
+/*! @} */
+
+/* The count of DMA_ATTR */
+#define DMA_ATTR_COUNT                           (16U)
+
+/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
+/*! @{ */
+#define DMA_NBYTES_MLNO_NBYTES_MASK              (0xFFFFFFFFU)
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT             (0U)
+#define DMA_NBYTES_MLNO_NBYTES(x)                (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
+/*! @} */
+
+/* The count of DMA_NBYTES_MLNO */
+#define DMA_NBYTES_MLNO_COUNT                    (16U)
+
+/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
+/*! @{ */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK           (0x3FFFFFFFU)
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT          (0U)
+#define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK            (0x40000000U)
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           (30U)
+/*! DMLOE - Destination Minor Loop Offset enable
+ *  0b0..The minor loop offset is not applied to the DADDR
+ *  0b1..The minor loop offset is applied to the DADDR
+ */
+#define DMA_NBYTES_MLOFFNO_DMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK            (0x80000000U)
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           (31U)
+/*! SMLOE - Source Minor Loop Offset Enable
+ *  0b0..The minor loop offset is not applied to the SADDR
+ *  0b1..The minor loop offset is applied to the SADDR
+ */
+#define DMA_NBYTES_MLOFFNO_SMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
+/*! @} */
+
+/* The count of DMA_NBYTES_MLOFFNO */
+#define DMA_NBYTES_MLOFFNO_COUNT                 (16U)
+
+/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
+/*! @{ */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK          (0x3FFU)
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT         (0U)
+#define DMA_NBYTES_MLOFFYES_NBYTES(x)            (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK           (0x3FFFFC00U)
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          (10U)
+#define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK           (0x40000000U)
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          (30U)
+/*! DMLOE - Destination Minor Loop Offset enable
+ *  0b0..The minor loop offset is not applied to the DADDR
+ *  0b1..The minor loop offset is applied to the DADDR
+ */
+#define DMA_NBYTES_MLOFFYES_DMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK           (0x80000000U)
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          (31U)
+/*! SMLOE - Source Minor Loop Offset Enable
+ *  0b0..The minor loop offset is not applied to the SADDR
+ *  0b1..The minor loop offset is applied to the SADDR
+ */
+#define DMA_NBYTES_MLOFFYES_SMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
+/*! @} */
+
+/* The count of DMA_NBYTES_MLOFFYES */
+#define DMA_NBYTES_MLOFFYES_COUNT                (16U)
+
+/*! @name SLAST - TCD Last Source Address Adjustment */
+/*! @{ */
+#define DMA_SLAST_SLAST_MASK                     (0xFFFFFFFFU)
+#define DMA_SLAST_SLAST_SHIFT                    (0U)
+#define DMA_SLAST_SLAST(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
+/*! @} */
+
+/* The count of DMA_SLAST */
+#define DMA_SLAST_COUNT                          (16U)
+
+/*! @name DADDR - TCD Destination Address */
+/*! @{ */
+#define DMA_DADDR_DADDR_MASK                     (0xFFFFFFFFU)
+#define DMA_DADDR_DADDR_SHIFT                    (0U)
+#define DMA_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
+/*! @} */
+
+/* The count of DMA_DADDR */
+#define DMA_DADDR_COUNT                          (16U)
+
+/*! @name DOFF - TCD Signed Destination Address Offset */
+/*! @{ */
+#define DMA_DOFF_DOFF_MASK                       (0xFFFFU)
+#define DMA_DOFF_DOFF_SHIFT                      (0U)
+#define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
+/*! @} */
+
+/* The count of DMA_DOFF */
+#define DMA_DOFF_COUNT                           (16U)
+
+/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
+/*! @{ */
+#define DMA_CITER_ELINKNO_CITER_MASK             (0x7FFFU)
+#define DMA_CITER_ELINKNO_CITER_SHIFT            (0U)
+#define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK             (0x8000U)
+#define DMA_CITER_ELINKNO_ELINK_SHIFT            (15U)
+/*! ELINK - Enable channel-to-channel linking on minor-loop complete
+ *  0b0..The channel-to-channel linking is disabled
+ *  0b1..The channel-to-channel linking is enabled
+ */
+#define DMA_CITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
+/*! @} */
+
+/* The count of DMA_CITER_ELINKNO */
+#define DMA_CITER_ELINKNO_COUNT                  (16U)
+
+/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
+/*! @{ */
+#define DMA_CITER_ELINKYES_CITER_MASK            (0x1FFU)
+#define DMA_CITER_ELINKYES_CITER_SHIFT           (0U)
+#define DMA_CITER_ELINKYES_CITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK           (0x1E00U)
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT          (9U)
+#define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK            (0x8000U)
+#define DMA_CITER_ELINKYES_ELINK_SHIFT           (15U)
+/*! ELINK - Enable channel-to-channel linking on minor-loop complete
+ *  0b0..The channel-to-channel linking is disabled
+ *  0b1..The channel-to-channel linking is enabled
+ */
+#define DMA_CITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
+/*! @} */
+
+/* The count of DMA_CITER_ELINKYES */
+#define DMA_CITER_ELINKYES_COUNT                 (16U)
+
+/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
+/*! @{ */
+#define DMA_DLAST_SGA_DLASTSGA_MASK              (0xFFFFFFFFU)
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT             (0U)
+#define DMA_DLAST_SGA_DLASTSGA(x)                (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
+/*! @} */
+
+/* The count of DMA_DLAST_SGA */
+#define DMA_DLAST_SGA_COUNT                      (16U)
+
+/*! @name CSR - TCD Control and Status */
+/*! @{ */
+#define DMA_CSR_START_MASK                       (0x1U)
+#define DMA_CSR_START_SHIFT                      (0U)
+/*! START - Channel Start
+ *  0b0..The channel is not explicitly started.
+ *  0b1..The channel is explicitly started via a software initiated service request.
+ */
+#define DMA_CSR_START(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
+#define DMA_CSR_INTMAJOR_MASK                    (0x2U)
+#define DMA_CSR_INTMAJOR_SHIFT                   (1U)
+/*! INTMAJOR - Enable an interrupt when major iteration count completes.
+ *  0b0..The end-of-major loop interrupt is disabled.
+ *  0b1..The end-of-major loop interrupt is enabled.
+ */
+#define DMA_CSR_INTMAJOR(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
+#define DMA_CSR_INTHALF_MASK                     (0x4U)
+#define DMA_CSR_INTHALF_SHIFT                    (2U)
+/*! INTHALF - Enable an interrupt when major counter is half complete.
+ *  0b0..The half-point interrupt is disabled.
+ *  0b1..The half-point interrupt is enabled.
+ */
+#define DMA_CSR_INTHALF(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
+#define DMA_CSR_DREQ_MASK                        (0x8U)
+#define DMA_CSR_DREQ_SHIFT                       (3U)
+/*! DREQ - Disable Request
+ *  0b0..The channel's ERQ bit is not affected.
+ *  0b1..The channel's ERQ bit is cleared when the major loop is complete.
+ */
+#define DMA_CSR_DREQ(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
+#define DMA_CSR_ESG_MASK                         (0x10U)
+#define DMA_CSR_ESG_SHIFT                        (4U)
+/*! ESG - Enable Scatter/Gather Processing
+ *  0b0..The current channel's TCD is normal format.
+ *  0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
+ */
+#define DMA_CSR_ESG(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
+#define DMA_CSR_MAJORELINK_MASK                  (0x20U)
+#define DMA_CSR_MAJORELINK_SHIFT                 (5U)
+/*! MAJORELINK - Enable channel-to-channel linking on major loop complete
+ *  0b0..The channel-to-channel linking is disabled.
+ *  0b1..The channel-to-channel linking is enabled.
+ */
+#define DMA_CSR_MAJORELINK(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
+#define DMA_CSR_ACTIVE_MASK                      (0x40U)
+#define DMA_CSR_ACTIVE_SHIFT                     (6U)
+#define DMA_CSR_ACTIVE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
+#define DMA_CSR_DONE_MASK                        (0x80U)
+#define DMA_CSR_DONE_SHIFT                       (7U)
+#define DMA_CSR_DONE(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
+#define DMA_CSR_MAJORLINKCH_MASK                 (0xF00U)
+#define DMA_CSR_MAJORLINKCH_SHIFT                (8U)
+#define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK                         (0xC000U)
+#define DMA_CSR_BWC_SHIFT                        (14U)
+/*! BWC - Bandwidth Control
+ *  0b00..No eDMA engine stalls.
+ *  0b01..Reserved
+ *  0b10..eDMA engine stalls for 4 cycles after each R/W.
+ *  0b11..eDMA engine stalls for 8 cycles after each R/W.
+ */
+#define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
+/*! @} */
+
+/* The count of DMA_CSR */
+#define DMA_CSR_COUNT                            (16U)
+
+/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
+/*! @{ */
+#define DMA_BITER_ELINKNO_BITER_MASK             (0x7FFFU)
+#define DMA_BITER_ELINKNO_BITER_SHIFT            (0U)
+#define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK             (0x8000U)
+#define DMA_BITER_ELINKNO_ELINK_SHIFT            (15U)
+/*! ELINK - Enables channel-to-channel linking on minor loop complete
+ *  0b0..The channel-to-channel linking is disabled
+ *  0b1..The channel-to-channel linking is enabled
+ */
+#define DMA_BITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
+/*! @} */
+
+/* The count of DMA_BITER_ELINKNO */
+#define DMA_BITER_ELINKNO_COUNT                  (16U)
+
+/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
+/*! @{ */
+#define DMA_BITER_ELINKYES_BITER_MASK            (0x1FFU)
+#define DMA_BITER_ELINKYES_BITER_SHIFT           (0U)
+#define DMA_BITER_ELINKYES_BITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK           (0x1E00U)
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT          (9U)
+#define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK            (0x8000U)
+#define DMA_BITER_ELINKYES_ELINK_SHIFT           (15U)
+/*! ELINK - Enables channel-to-channel linking on minor loop complete
+ *  0b0..The channel-to-channel linking is disabled
+ *  0b1..The channel-to-channel linking is enabled
+ */
+#define DMA_BITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
+/*! @} */
+
+/* The count of DMA_BITER_ELINKYES */
+#define DMA_BITER_ELINKYES_COUNT                 (16U)
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA0 base address */
+#define DMA0_BASE                                (0x40008000u)
+/** Peripheral DMA0 base pointer */
+#define DMA0                                     ((DMA_Type *)DMA0_BASE)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS                           { DMA0_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS                            { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS                             { {DMA0_0_4_8_12_IRQn, DMA0_1_5_9_13_IRQn, DMA0_2_6_10_14_IRQn, DMA0_3_7_11_15_IRQn} }
+#define DMA_ERROR_IRQS                           { DMA0_Error_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CHCFG[16];                         /**< Channel 0 Configuration Register..Channel 15 Configuration Register, array offset: 0x0, array step: 0x4 */
+} DMAMUX_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/*! @name CHCFG - Channel 0 Configuration Register..Channel 15 Configuration Register */
+/*! @{ */
+#define DMAMUX_CHCFG_SOURCE_MASK                 (0x3FU)
+#define DMAMUX_CHCFG_SOURCE_SHIFT                (0U)
+#define DMAMUX_CHCFG_SOURCE(x)                   (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_A_ON_MASK                   (0x20000000U)
+#define DMAMUX_CHCFG_A_ON_SHIFT                  (29U)
+/*! A_ON - DMA Channel Always Enable
+ *  0b0..DMA Channel Always ON function is disabled
+ *  0b1..DMA Channel Always ON function is enabled
+ */
+#define DMAMUX_CHCFG_A_ON(x)                     (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK                   (0x40000000U)
+#define DMAMUX_CHCFG_TRIG_SHIFT                  (30U)
+/*! TRIG - DMA Channel Trigger Enable
+ *  0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
+ *  0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
+ */
+#define DMAMUX_CHCFG_TRIG(x)                     (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
+#define DMAMUX_CHCFG_ENBL_MASK                   (0x80000000U)
+#define DMAMUX_CHCFG_ENBL_SHIFT                  (31U)
+/*! ENBL - DMA Mux Channel Enable
+ *  0b0..DMA Mux channel is disabled
+ *  0b1..DMA Mux channel is enabled
+ */
+#define DMAMUX_CHCFG_ENBL(x)                     (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
+/*! @} */
+
+/* The count of DMAMUX_CHCFG */
+#define DMAMUX_CHCFG_COUNT                       (16U)
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX0 base address */
+#define DMAMUX0_BASE                             (0x40021000u)
+/** Peripheral DMAMUX0 base pointer */
+#define DMAMUX0                                  ((DMAMUX_Type *)DMAMUX0_BASE)
+/** Array initializer of DMAMUX peripheral base addresses */
+#define DMAMUX_BASE_ADDRS                        { DMAMUX0_BASE }
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASE_PTRS                         { DMAMUX0 }
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EMVSIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer
+ * @{
+ */
+
+/** EMVSIM - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VER_ID;                            /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __IO uint32_t CLKCFG;                            /**< Clock Configuration Register, offset: 0x8 */
+  __IO uint32_t DIVISOR;                           /**< Baud Rate Divisor Register, offset: 0xC */
+  __IO uint32_t CTRL;                              /**< Control Register, offset: 0x10 */
+  __IO uint32_t INT_MASK;                          /**< Interrupt Mask Register, offset: 0x14 */
+  __IO uint32_t RX_THD;                            /**< Receiver Threshold Register, offset: 0x18 */
+  __IO uint32_t TX_THD;                            /**< Transmitter Threshold Register, offset: 0x1C */
+  __IO uint32_t RX_STATUS;                         /**< Receive Status Register, offset: 0x20 */
+  __IO uint32_t TX_STATUS;                         /**< Transmitter Status Register, offset: 0x24 */
+  __IO uint32_t PCSR;                              /**< Port Control and Status Register, offset: 0x28 */
+  __I  uint32_t RX_BUF;                            /**< Receive Data Read Buffer, offset: 0x2C */
+  __O  uint32_t TX_BUF;                            /**< Transmit Data Buffer, offset: 0x30 */
+  __IO uint32_t TX_GETU;                           /**< Transmitter Guard ETU Value Register, offset: 0x34 */
+  __IO uint32_t CWT_VAL;                           /**< Character Wait Time Value Register, offset: 0x38 */
+  __IO uint32_t BWT_VAL;                           /**< Block Wait Time Value Register, offset: 0x3C */
+  __IO uint32_t BGT_VAL;                           /**< Block Guard Time Value Register, offset: 0x40 */
+  __IO uint32_t GPCNT0_VAL;                        /**< General Purpose Counter 0 Timeout Value Register, offset: 0x44 */
+  __IO uint32_t GPCNT1_VAL;                        /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */
+} EMVSIM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- EMVSIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks
+ * @{
+ */
+
+/*! @name VER_ID - Version ID Register */
+/*! @{ */
+#define EMVSIM_VER_ID_VER_MASK                   (0xFFFFFFFFU)
+#define EMVSIM_VER_ID_VER_SHIFT                  (0U)
+#define EMVSIM_VER_ID_VER(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK          (0xFFU)
+#define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT         (0U)
+#define EMVSIM_PARAM_RX_FIFO_DEPTH(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)
+#define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK          (0xFF00U)
+#define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT         (8U)
+#define EMVSIM_PARAM_TX_FIFO_DEPTH(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)
+/*! @} */
+
+/*! @name CLKCFG - Clock Configuration Register */
+/*! @{ */
+#define EMVSIM_CLKCFG_CLK_PRSC_MASK              (0xFFU)
+#define EMVSIM_CLKCFG_CLK_PRSC_SHIFT             (0U)
+/*! CLK_PRSC - Clock Prescaler Value
+ *  0b00000010..Divide by 2
+ */
+#define EMVSIM_CLKCFG_CLK_PRSC(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK)
+#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK        (0x300U)
+#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT       (8U)
+/*! GPCNT1_CLK_SEL - General Purpose Counter 1 Clock Select
+ *  0b00..Disabled / Reset (default)
+ *  0b01..Card Clock
+ *  0b10..Receive Clock
+ *  0b11..ETU Clock (transmit clock)
+ */
+#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK)
+#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK        (0xC00U)
+#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT       (10U)
+/*! GPCNT0_CLK_SEL - General Purpose Counter 0 Clock Select
+ *  0b00..Disabled / Reset (default)
+ *  0b01..Card Clock
+ *  0b10..Receive Clock
+ *  0b11..ETU Clock (transmit clock)
+ */
+#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK)
+/*! @} */
+
+/*! @name DIVISOR - Baud Rate Divisor Register */
+/*! @{ */
+#define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK        (0x1FFU)
+#define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT       (0U)
+/*! DIVISOR_VALUE - Divisor (F/D) Value
+ *  0b000000000-0b000000100..Invalid. As per ISO 7816 specification, minimum value of F/D is 5
+ *  0b101110100..Divisor value for F = 372 and D = 1 (default)
+ */
+#define EMVSIM_DIVISOR_DIVISOR_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK)
+/*! @} */
+
+/*! @name CTRL - Control Register */
+/*! @{ */
+#define EMVSIM_CTRL_IC_MASK                      (0x1U)
+#define EMVSIM_CTRL_IC_SHIFT                     (0U)
+/*! IC - Inverse Convention
+ *  0b0..Direction convention transfers enabled (default)
+ *  0b1..Inverse convention transfers enabled
+ */
+#define EMVSIM_CTRL_IC(x)                        (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK)
+#define EMVSIM_CTRL_ICM_MASK                     (0x2U)
+#define EMVSIM_CTRL_ICM_SHIFT                    (1U)
+/*! ICM - Initial Character Mode
+ *  0b0..Initial Character Mode disabled
+ *  0b1..Initial Character Mode enabled (default)
+ */
+#define EMVSIM_CTRL_ICM(x)                       (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK)
+#define EMVSIM_CTRL_ANACK_MASK                   (0x4U)
+#define EMVSIM_CTRL_ANACK_SHIFT                  (2U)
+/*! ANACK - Auto NACK Enable
+ *  0b0..NACK generation on errors disabled
+ *  0b1..NACK generation on errors enabled (default)
+ */
+#define EMVSIM_CTRL_ANACK(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK)
+#define EMVSIM_CTRL_ONACK_MASK                   (0x8U)
+#define EMVSIM_CTRL_ONACK_SHIFT                  (3U)
+/*! ONACK - Overrun NACK Enable
+ *  0b0..NACK generation on overrun is disabled (default)
+ *  0b1..NACK generation on overrun is enabled
+ */
+#define EMVSIM_CTRL_ONACK(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK)
+#define EMVSIM_CTRL_FLSH_RX_MASK                 (0x100U)
+#define EMVSIM_CTRL_FLSH_RX_SHIFT                (8U)
+/*! FLSH_RX - Flush Receiver Bit
+ *  0b0..EMV SIM Receiver normal operation (default)
+ *  0b1..EMV SIM Receiver held in Reset
+ */
+#define EMVSIM_CTRL_FLSH_RX(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK)
+#define EMVSIM_CTRL_FLSH_TX_MASK                 (0x200U)
+#define EMVSIM_CTRL_FLSH_TX_SHIFT                (9U)
+/*! FLSH_TX - Flush Transmitter Bit
+ *  0b0..EMV SIM Transmitter normal operation (default)
+ *  0b1..EMV SIM Transmitter held in Reset
+ */
+#define EMVSIM_CTRL_FLSH_TX(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK)
+#define EMVSIM_CTRL_SW_RST_MASK                  (0x400U)
+#define EMVSIM_CTRL_SW_RST_SHIFT                 (10U)
+/*! SW_RST - Software Reset Bit
+ *  0b0..EMV SIM Normal operation (default)
+ *  0b1..EMV SIM held in Reset
+ */
+#define EMVSIM_CTRL_SW_RST(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK)
+#define EMVSIM_CTRL_KILL_CLOCKS_MASK             (0x800U)
+#define EMVSIM_CTRL_KILL_CLOCKS_SHIFT            (11U)
+/*! KILL_CLOCKS - Kill all internal clocks
+ *  0b0..EMV SIM input clock enabled (default)
+ *  0b1..EMV SIM input clock is disabled
+ */
+#define EMVSIM_CTRL_KILL_CLOCKS(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK)
+#define EMVSIM_CTRL_DOZE_EN_MASK                 (0x1000U)
+#define EMVSIM_CTRL_DOZE_EN_SHIFT                (12U)
+/*! DOZE_EN - Doze Enable
+ *  0b0..DOZE instruction will gate all internal EMV SIM clocks as well as the Smart Card clock when the transmit FIFO is empty (default)
+ *  0b1..DOZE instruction has no effect on EMV SIM module
+ */
+#define EMVSIM_CTRL_DOZE_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK)
+#define EMVSIM_CTRL_STOP_EN_MASK                 (0x2000U)
+#define EMVSIM_CTRL_STOP_EN_SHIFT                (13U)
+/*! STOP_EN - STOP Enable
+ *  0b0..STOP instruction shuts down all EMV SIM clocks (default)
+ *  0b1..STOP instruction shuts down all clocks except for the Smart Card Clock (SCK) (clock provided to Smart Card)
+ */
+#define EMVSIM_CTRL_STOP_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK)
+#define EMVSIM_CTRL_RCV_EN_MASK                  (0x10000U)
+#define EMVSIM_CTRL_RCV_EN_SHIFT                 (16U)
+/*! RCV_EN - Receiver Enable
+ *  0b0..EMV SIM Receiver disabled (default)
+ *  0b1..EMV SIM Receiver enabled
+ */
+#define EMVSIM_CTRL_RCV_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK)
+#define EMVSIM_CTRL_XMT_EN_MASK                  (0x20000U)
+#define EMVSIM_CTRL_XMT_EN_SHIFT                 (17U)
+/*! XMT_EN - Transmitter Enable
+ *  0b0..EMV SIM Transmitter disabled (default)
+ *  0b1..EMV SIM Transmitter enabled
+ */
+#define EMVSIM_CTRL_XMT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK)
+#define EMVSIM_CTRL_RCVR_11_MASK                 (0x40000U)
+#define EMVSIM_CTRL_RCVR_11_SHIFT                (18U)
+/*! RCVR_11 - Receiver 11 ETU Mode Enable
+ *  0b0..Receiver configured for 12 ETU operation mode (default)
+ *  0b1..Receiver configured for 11 ETU operation mode
+ */
+#define EMVSIM_CTRL_RCVR_11(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
+#define EMVSIM_CTRL_RX_DMA_EN_MASK               (0x80000U)
+#define EMVSIM_CTRL_RX_DMA_EN_SHIFT              (19U)
+/*! RX_DMA_EN - Receive DMA Enable
+ *  0b0..No DMA Read Request asserted for Receiver (default)
+ *  0b1..DMA Read Request asserted for Receiver
+ */
+#define EMVSIM_CTRL_RX_DMA_EN(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK)
+#define EMVSIM_CTRL_TX_DMA_EN_MASK               (0x100000U)
+#define EMVSIM_CTRL_TX_DMA_EN_SHIFT              (20U)
+/*! TX_DMA_EN - Transmit DMA Enable
+ *  0b0..No DMA Write Request asserted for Transmitter (default)
+ *  0b1..DMA Write Request asserted for Transmitter
+ */
+#define EMVSIM_CTRL_TX_DMA_EN(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK)
+#define EMVSIM_CTRL_INV_CRC_VAL_MASK             (0x1000000U)
+#define EMVSIM_CTRL_INV_CRC_VAL_SHIFT            (24U)
+/*! INV_CRC_VAL - Invert bits in the CRC Output Value
+ *  0b0..Bits in CRC Output value will not be inverted.
+ *  0b1..Bits in CRC Output value will be inverted. (default)
+ */
+#define EMVSIM_CTRL_INV_CRC_VAL(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK)
+#define EMVSIM_CTRL_CRC_OUT_FLIP_MASK            (0x2000000U)
+#define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT           (25U)
+/*! CRC_OUT_FLIP - CRC Output Value Bit Reversal or Flip
+ *  0b0..Bits within the CRC output bytes will not be reversed i.e. 15:0 will remain 15:0 (default)
+ *  0b1..Bits within the CRC output bytes will be reversed i.e. 15:0 will become {8:15,0:7}
+ */
+#define EMVSIM_CTRL_CRC_OUT_FLIP(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK)
+#define EMVSIM_CTRL_CRC_IN_FLIP_MASK             (0x4000000U)
+#define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT            (26U)
+/*! CRC_IN_FLIP - CRC Input Byte's Bit Reversal or Flip Control
+ *  0b0..Bits in the input byte will not be reversed (i.e. 7:0 will remain 7:0) before the CRC calculation (default)
+ *  0b1..Bits in the input byte will be reversed (i.e. 7:0 will become 0:7) before CRC calculation
+ */
+#define EMVSIM_CTRL_CRC_IN_FLIP(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK)
+#define EMVSIM_CTRL_CWT_EN_MASK                  (0x8000000U)
+#define EMVSIM_CTRL_CWT_EN_SHIFT                 (27U)
+/*! CWT_EN - Character Wait Time Counter Enable
+ *  0b0..Character Wait time Counter is disabled (default)
+ *  0b1..Character Wait time counter is enabled
+ */
+#define EMVSIM_CTRL_CWT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK)
+#define EMVSIM_CTRL_LRC_EN_MASK                  (0x10000000U)
+#define EMVSIM_CTRL_LRC_EN_SHIFT                 (28U)
+/*! LRC_EN - LRC Enable
+ *  0b0..8-bit Linear Redundancy Checking disabled (default)
+ *  0b1..8-bit Linear Redundancy Checking enabled
+ */
+#define EMVSIM_CTRL_LRC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK)
+#define EMVSIM_CTRL_CRC_EN_MASK                  (0x20000000U)
+#define EMVSIM_CTRL_CRC_EN_SHIFT                 (29U)
+/*! CRC_EN - CRC Enable
+ *  0b0..16-bit Cyclic Redundancy Checking disabled (default)
+ *  0b1..16-bit Cyclic Redundancy Checking enabled
+ */
+#define EMVSIM_CTRL_CRC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK)
+#define EMVSIM_CTRL_XMT_CRC_LRC_MASK             (0x40000000U)
+#define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT            (30U)
+/*! XMT_CRC_LRC - Transmit CRC or LRC Enable
+ *  0b0..No CRC or LRC value is transmitted (default)
+ *  0b1..Transmit LRC or CRC info when FIFO empties (whichever is enabled)
+ */
+#define EMVSIM_CTRL_XMT_CRC_LRC(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK)
+#define EMVSIM_CTRL_BWT_EN_MASK                  (0x80000000U)
+#define EMVSIM_CTRL_BWT_EN_SHIFT                 (31U)
+/*! BWT_EN - Block Wait Time Counter Enable
+ *  0b0..Disable BWT, BGT Counters (default)
+ *  0b1..Enable BWT, BGT Counters
+ */
+#define EMVSIM_CTRL_BWT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK)
+/*! @} */
+
+/*! @name INT_MASK - Interrupt Mask Register */
+/*! @{ */
+#define EMVSIM_INT_MASK_RDT_IM_MASK              (0x1U)
+#define EMVSIM_INT_MASK_RDT_IM_SHIFT             (0U)
+/*! RDT_IM - Receive Data Threshold Interrupt Mask
+ *  0b0..RDTF interrupt enabled
+ *  0b1..RDTF interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_RDT_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK)
+#define EMVSIM_INT_MASK_TC_IM_MASK               (0x2U)
+#define EMVSIM_INT_MASK_TC_IM_SHIFT              (1U)
+/*! TC_IM - Transmit Complete Interrupt Mask
+ *  0b0..TCF interrupt enabled
+ *  0b1..TCF interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_TC_IM(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK)
+#define EMVSIM_INT_MASK_RFO_IM_MASK              (0x4U)
+#define EMVSIM_INT_MASK_RFO_IM_SHIFT             (2U)
+/*! RFO_IM - Receive FIFO Overflow Interrupt Mask
+ *  0b0..RFO interrupt enabled
+ *  0b1..RFO interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_RFO_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK)
+#define EMVSIM_INT_MASK_ETC_IM_MASK              (0x8U)
+#define EMVSIM_INT_MASK_ETC_IM_SHIFT             (3U)
+/*! ETC_IM - Early Transmit Complete Interrupt Mask
+ *  0b0..ETC interrupt enabled
+ *  0b1..ETC interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_ETC_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK)
+#define EMVSIM_INT_MASK_TFE_IM_MASK              (0x10U)
+#define EMVSIM_INT_MASK_TFE_IM_SHIFT             (4U)
+/*! TFE_IM - Transmit FIFO Empty Interrupt Mask
+ *  0b0..TFE interrupt enabled
+ *  0b1..TFE interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_TFE_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK)
+#define EMVSIM_INT_MASK_TNACK_IM_MASK            (0x20U)
+#define EMVSIM_INT_MASK_TNACK_IM_SHIFT           (5U)
+/*! TNACK_IM - Transmit NACK Threshold Interrupt Mask
+ *  0b0..TNTE interrupt enabled
+ *  0b1..TNTE interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_TNACK_IM(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK)
+#define EMVSIM_INT_MASK_TFF_IM_MASK              (0x40U)
+#define EMVSIM_INT_MASK_TFF_IM_SHIFT             (6U)
+/*! TFF_IM - Transmit FIFO Full Interrupt Mask
+ *  0b0..TFF interrupt enabled
+ *  0b1..TFF interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_TFF_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK)
+#define EMVSIM_INT_MASK_TDT_IM_MASK              (0x80U)
+#define EMVSIM_INT_MASK_TDT_IM_SHIFT             (7U)
+/*! TDT_IM - Transmit Data Threshold Interrupt Mask
+ *  0b0..TDTF interrupt enabled
+ *  0b1..TDTF interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_TDT_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK)
+#define EMVSIM_INT_MASK_GPCNT0_IM_MASK           (0x100U)
+#define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT          (8U)
+/*! GPCNT0_IM - General Purpose Timer 0 Timeout Interrupt Mask
+ *  0b0..GPCNT0_TO interrupt enabled
+ *  0b1..GPCNT0_TO interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_GPCNT0_IM(x)             (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK)
+#define EMVSIM_INT_MASK_CWT_ERR_IM_MASK          (0x200U)
+#define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT         (9U)
+/*! CWT_ERR_IM - Character Wait Time Error Interrupt Mask
+ *  0b0..CWT_ERR interrupt enabled
+ *  0b1..CWT_ERR interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_CWT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK)
+#define EMVSIM_INT_MASK_RNACK_IM_MASK            (0x400U)
+#define EMVSIM_INT_MASK_RNACK_IM_SHIFT           (10U)
+/*! RNACK_IM - Receiver NACK Threshold Interrupt Mask
+ *  0b0..RTE interrupt enabled
+ *  0b1..RTE interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_RNACK_IM(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK)
+#define EMVSIM_INT_MASK_BWT_ERR_IM_MASK          (0x800U)
+#define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT         (11U)
+/*! BWT_ERR_IM - Block Wait Time Error Interrupt Mask
+ *  0b0..BWT_ERR interrupt enabled
+ *  0b1..BWT_ERR interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_BWT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK)
+#define EMVSIM_INT_MASK_BGT_ERR_IM_MASK          (0x1000U)
+#define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT         (12U)
+/*! BGT_ERR_IM - Block Guard Time Error Interrupt
+ *  0b0..BGT_ERR interrupt enabled
+ *  0b1..BGT_ERR interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_BGT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK)
+#define EMVSIM_INT_MASK_GPCNT1_IM_MASK           (0x2000U)
+#define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT          (13U)
+/*! GPCNT1_IM - General Purpose Counter 1 Timeout Interrupt Mask
+ *  0b0..GPCNT1_TO interrupt enabled
+ *  0b1..GPCNT1_TO interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_GPCNT1_IM(x)             (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK)
+#define EMVSIM_INT_MASK_RX_DATA_IM_MASK          (0x4000U)
+#define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT         (14U)
+/*! RX_DATA_IM - Receive Data Interrupt Mask
+ *  0b0..RX_DATA interrupt enabled
+ *  0b1..RX_DATA interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_RX_DATA_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK)
+#define EMVSIM_INT_MASK_PEF_IM_MASK              (0x8000U)
+#define EMVSIM_INT_MASK_PEF_IM_SHIFT             (15U)
+/*! PEF_IM - Parity Error Interrupt Mask
+ *  0b0..PEF interrupt enabled
+ *  0b1..PEF interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_PEF_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
+/*! @} */
+
+/*! @name RX_THD - Receiver Threshold Register */
+/*! @{ */
+#define EMVSIM_RX_THD_RDT_MASK                   (0xFU)
+#define EMVSIM_RX_THD_RDT_SHIFT                  (0U)
+#define EMVSIM_RX_THD_RDT(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
+#define EMVSIM_RX_THD_RNCK_THD_MASK              (0xF00U)
+#define EMVSIM_RX_THD_RNCK_THD_SHIFT             (8U)
+/*! RNCK_THD - Receiver NACK Threshold Value
+ *  0b0000..Zero Threshold. RTE will not be set
+ */
+#define EMVSIM_RX_THD_RNCK_THD(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK)
+/*! @} */
+
+/*! @name TX_THD - Transmitter Threshold Register */
+/*! @{ */
+#define EMVSIM_TX_THD_TDT_MASK                   (0xFU)
+#define EMVSIM_TX_THD_TDT_SHIFT                  (0U)
+#define EMVSIM_TX_THD_TDT(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK)
+#define EMVSIM_TX_THD_TNCK_THD_MASK              (0xF00U)
+#define EMVSIM_TX_THD_TNCK_THD_SHIFT             (8U)
+/*! TNCK_THD - Transmitter NACK Threshold Value
+ *  0b0000..TNTE will never be set; retransmission after NACK reception is disabled.
+ *  0b0001..TNTE will be set after 1 nack is received; 0 retransmissions occurs.
+ *  0b0010..TNTE will be set after 2 nacks are received; at most 1 retransmission occurs.
+ *  0b0011..TNTE will be set after 3 nacks are received; at most 2 retransmissions occurs.
+ *  0b1111..TNTE will be set after 15 nacks are received; at most 14 retransmissions occurs.
+ */
+#define EMVSIM_TX_THD_TNCK_THD(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK)
+/*! @} */
+
+/*! @name RX_STATUS - Receive Status Register */
+/*! @{ */
+#define EMVSIM_RX_STATUS_RFO_MASK                (0x1U)
+#define EMVSIM_RX_STATUS_RFO_SHIFT               (0U)
+/*! RFO - Receive FIFO Overflow Flag
+ *  0b0..No overrun error has occurred (default)
+ *  0b1..A byte was received when the received FIFO was already full
+ */
+#define EMVSIM_RX_STATUS_RFO(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK)
+#define EMVSIM_RX_STATUS_RX_DATA_MASK            (0x10U)
+#define EMVSIM_RX_STATUS_RX_DATA_SHIFT           (4U)
+/*! RX_DATA - Receive Data Interrupt Flag
+ *  0b0..No new byte is received
+ *  0b1..New byte is received ans stored in Receive FIFO
+ */
+#define EMVSIM_RX_STATUS_RX_DATA(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK)
+#define EMVSIM_RX_STATUS_RDTF_MASK               (0x20U)
+#define EMVSIM_RX_STATUS_RDTF_SHIFT              (5U)
+/*! RDTF - Receive Data Threshold Interrupt Flag
+ *  0b0..Number of unread bytes in receive FIFO less than the value set by RDT[3:0] (default).
+ *  0b1..Number of unread bytes in receive FIFO greater or than equal to value set by RDT[3:0].
+ */
+#define EMVSIM_RX_STATUS_RDTF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK)
+#define EMVSIM_RX_STATUS_LRC_OK_MASK             (0x40U)
+#define EMVSIM_RX_STATUS_LRC_OK_SHIFT            (6U)
+/*! LRC_OK - LRC Check OK Flag
+ *  0b0..Current LRC value does not match remainder.
+ *  0b1..Current calculated LRC value matches the expected result (i.e. zero).
+ */
+#define EMVSIM_RX_STATUS_LRC_OK(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK)
+#define EMVSIM_RX_STATUS_CRC_OK_MASK             (0x80U)
+#define EMVSIM_RX_STATUS_CRC_OK_SHIFT            (7U)
+/*! CRC_OK - CRC Check OK Flag
+ *  0b0..Current CRC value does not match remainder.
+ *  0b1..Current calculated CRC value matches the expected result.
+ */
+#define EMVSIM_RX_STATUS_CRC_OK(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK)
+#define EMVSIM_RX_STATUS_CWT_ERR_MASK            (0x100U)
+#define EMVSIM_RX_STATUS_CWT_ERR_SHIFT           (8U)
+/*! CWT_ERR - Character Wait Time Error Flag
+ *  0b0..No CWT violation has occurred (default).
+ *  0b1..Time between two consecutive characters has exceeded the value in CHAR_WAIT.
+ */
+#define EMVSIM_RX_STATUS_CWT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK)
+#define EMVSIM_RX_STATUS_RTE_MASK                (0x200U)
+#define EMVSIM_RX_STATUS_RTE_SHIFT               (9U)
+/*! RTE - Received NACK Threshold Error Flag
+ *  0b0..Number of NACKs generated by the receiver is less than the value programmed in RTH[3:0]
+ *  0b1..Number of NACKs generated by the receiver is equal to the value programmed in RTH[3:0]
+ */
+#define EMVSIM_RX_STATUS_RTE(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK)
+#define EMVSIM_RX_STATUS_BWT_ERR_MASK            (0x400U)
+#define EMVSIM_RX_STATUS_BWT_ERR_SHIFT           (10U)
+/*! BWT_ERR - Block Wait Time Error Flag
+ *  0b0..Block wait time not exceeded
+ *  0b1..Block wait time was exceeded
+ */
+#define EMVSIM_RX_STATUS_BWT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK)
+#define EMVSIM_RX_STATUS_BGT_ERR_MASK            (0x800U)
+#define EMVSIM_RX_STATUS_BGT_ERR_SHIFT           (11U)
+/*! BGT_ERR - Block Guard Time Error Flag
+ *  0b0..Block guard time was sufficient
+ *  0b1..Block guard time was too small
+ */
+#define EMVSIM_RX_STATUS_BGT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK)
+#define EMVSIM_RX_STATUS_PEF_MASK                (0x1000U)
+#define EMVSIM_RX_STATUS_PEF_SHIFT               (12U)
+/*! PEF - Parity Error Flag
+ *  0b0..No parity error detected
+ *  0b1..Parity error detected
+ */
+#define EMVSIM_RX_STATUS_PEF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK)
+#define EMVSIM_RX_STATUS_FEF_MASK                (0x2000U)
+#define EMVSIM_RX_STATUS_FEF_SHIFT               (13U)
+/*! FEF - Frame Error Flag
+ *  0b0..No frame error detected
+ *  0b1..Frame error detected
+ */
+#define EMVSIM_RX_STATUS_FEF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK)
+#define EMVSIM_RX_STATUS_RX_WPTR_MASK            (0xF0000U)
+#define EMVSIM_RX_STATUS_RX_WPTR_SHIFT           (16U)
+#define EMVSIM_RX_STATUS_RX_WPTR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK)
+#define EMVSIM_RX_STATUS_RX_CNT_MASK             (0xF000000U)
+#define EMVSIM_RX_STATUS_RX_CNT_SHIFT            (24U)
+/*! RX_CNT - Receive FIFO Byte Count
+ *  0b0000..FIFO is emtpy
+ */
+#define EMVSIM_RX_STATUS_RX_CNT(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK)
+/*! @} */
+
+/*! @name TX_STATUS - Transmitter Status Register */
+/*! @{ */
+#define EMVSIM_TX_STATUS_TNTE_MASK               (0x1U)
+#define EMVSIM_TX_STATUS_TNTE_SHIFT              (0U)
+/*! TNTE - Transmit NACK Threshold Error Flag
+ *  0b0..Transmit NACK threshold has not been reached (default)
+ *  0b1..Transmit NACK threshold reached; transmitter frozen
+ */
+#define EMVSIM_TX_STATUS_TNTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK)
+#define EMVSIM_TX_STATUS_TFE_MASK                (0x8U)
+#define EMVSIM_TX_STATUS_TFE_SHIFT               (3U)
+/*! TFE - Transmit FIFO Empty Flag
+ *  0b0..Transmit FIFO is not empty
+ *  0b1..Transmit FIFO is empty (default)
+ */
+#define EMVSIM_TX_STATUS_TFE(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK)
+#define EMVSIM_TX_STATUS_ETCF_MASK               (0x10U)
+#define EMVSIM_TX_STATUS_ETCF_SHIFT              (4U)
+/*! ETCF - Early Transmit Complete Flag
+ *  0b0..Transmit pending or in progress
+ *  0b1..Transmit complete (default)
+ */
+#define EMVSIM_TX_STATUS_ETCF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK)
+#define EMVSIM_TX_STATUS_TCF_MASK                (0x20U)
+#define EMVSIM_TX_STATUS_TCF_SHIFT               (5U)
+/*! TCF - Transmit Complete Flag
+ *  0b0..Transmit pending or in progress
+ *  0b1..Transmit complete (default)
+ */
+#define EMVSIM_TX_STATUS_TCF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK)
+#define EMVSIM_TX_STATUS_TFF_MASK                (0x40U)
+#define EMVSIM_TX_STATUS_TFF_SHIFT               (6U)
+/*! TFF - Transmit FIFO Full Flag
+ *  0b0..Transmit FIFO Full condition has not occurred (default)
+ *  0b1..A Transmit FIFO Full condition has occurred
+ */
+#define EMVSIM_TX_STATUS_TFF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK)
+#define EMVSIM_TX_STATUS_TDTF_MASK               (0x80U)
+#define EMVSIM_TX_STATUS_TDTF_SHIFT              (7U)
+/*! TDTF - Transmit Data Threshold Flag
+ *  0b0..Number of bytes in FIFO is greater than TDT[3:0], or bit has been cleared
+ *  0b1..Number of bytes in FIFO is less than or equal to TDT[3:0] (default)
+ */
+#define EMVSIM_TX_STATUS_TDTF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK)
+#define EMVSIM_TX_STATUS_GPCNT0_TO_MASK          (0x100U)
+#define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT         (8U)
+/*! GPCNT0_TO - General Purpose Counter 0 Timeout Flag
+ *  0b0..GPCNT0_VAL time not reached, or bit has been cleared. (default)
+ *  0b1..General Purpose counter has reached the GPCNT0_VAL value
+ */
+#define EMVSIM_TX_STATUS_GPCNT0_TO(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK)
+#define EMVSIM_TX_STATUS_GPCNT1_TO_MASK          (0x200U)
+#define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT         (9U)
+/*! GPCNT1_TO - General Purpose Counter 1 Timeout Flag
+ *  0b0..GPCNT1_VAL time not reached, or bit has been cleared. (default)
+ *  0b1..General Purpose counter has reached the GPCNT1_VAL value
+ */
+#define EMVSIM_TX_STATUS_GPCNT1_TO(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK)
+#define EMVSIM_TX_STATUS_TX_RPTR_MASK            (0xF0000U)
+#define EMVSIM_TX_STATUS_TX_RPTR_SHIFT           (16U)
+#define EMVSIM_TX_STATUS_TX_RPTR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK)
+#define EMVSIM_TX_STATUS_TX_CNT_MASK             (0xF000000U)
+#define EMVSIM_TX_STATUS_TX_CNT_SHIFT            (24U)
+/*! TX_CNT - Transmit FIFO Byte Count
+ *  0b0000..FIFO is emtpy
+ */
+#define EMVSIM_TX_STATUS_TX_CNT(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK)
+/*! @} */
+
+/*! @name PCSR - Port Control and Status Register */
+/*! @{ */
+#define EMVSIM_PCSR_SAPD_MASK                    (0x1U)
+#define EMVSIM_PCSR_SAPD_SHIFT                   (0U)
+/*! SAPD - Auto Power Down Enable
+ *  0b0..Auto power down disabled (default)
+ *  0b1..Auto power down enabled
+ */
+#define EMVSIM_PCSR_SAPD(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK)
+#define EMVSIM_PCSR_SVCC_EN_MASK                 (0x2U)
+#define EMVSIM_PCSR_SVCC_EN_SHIFT                (1U)
+/*! SVCC_EN - Vcc Enable for Smart Card
+ *  0b0..Smart Card Voltage disabled (default)
+ *  0b1..Smart Card Voltage enabled
+ */
+#define EMVSIM_PCSR_SVCC_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK)
+#define EMVSIM_PCSR_VCCENP_MASK                  (0x4U)
+#define EMVSIM_PCSR_VCCENP_SHIFT                 (2U)
+/*! VCCENP - VCC Enable Polarity Control
+ *  0b0..VCC_EN is active high. Polarity of SVCC_EN is unchanged.
+ *  0b1..VCC_EN is active low. Polarity of SVCC_EN is inverted.
+ */
+#define EMVSIM_PCSR_VCCENP(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK)
+#define EMVSIM_PCSR_SRST_MASK                    (0x8U)
+#define EMVSIM_PCSR_SRST_SHIFT                   (3U)
+/*! SRST - Reset to Smart Card
+ *  0b0..Smart Card Reset is asserted (default)
+ *  0b1..Smart Card Reset is de-asserted
+ */
+#define EMVSIM_PCSR_SRST(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK)
+#define EMVSIM_PCSR_SCEN_MASK                    (0x10U)
+#define EMVSIM_PCSR_SCEN_SHIFT                   (4U)
+/*! SCEN - Clock Enable for Smart Card
+ *  0b0..Smart Card Clock Disabled
+ *  0b1..Smart Card Clock Enabled
+ */
+#define EMVSIM_PCSR_SCEN(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK)
+#define EMVSIM_PCSR_SCSP_MASK                    (0x20U)
+#define EMVSIM_PCSR_SCSP_SHIFT                   (5U)
+/*! SCSP - Smart Card Clock Stop Polarity
+ *  0b0..Clock is logic 0 when stopped by SCEN
+ *  0b1..Clock is logic 1 when stopped by SCEN
+ */
+#define EMVSIM_PCSR_SCSP(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK)
+#define EMVSIM_PCSR_SPD_MASK                     (0x80U)
+#define EMVSIM_PCSR_SPD_SHIFT                    (7U)
+/*! SPD - Auto Power Down Control
+ *  0b0..No effect (default)
+ *  0b1..Start Auto Powerdown or Power Down is in progress
+ */
+#define EMVSIM_PCSR_SPD(x)                       (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK)
+#define EMVSIM_PCSR_SPDIM_MASK                   (0x1000000U)
+#define EMVSIM_PCSR_SPDIM_SHIFT                  (24U)
+/*! SPDIM - Smart Card Presence Detect Interrupt Mask
+ *  0b0..SIM presence detect interrupt is enabled
+ *  0b1..SIM presence detect interrupt is masked (default)
+ */
+#define EMVSIM_PCSR_SPDIM(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK)
+#define EMVSIM_PCSR_SPDIF_MASK                   (0x2000000U)
+#define EMVSIM_PCSR_SPDIF_SHIFT                  (25U)
+/*! SPDIF - Smart Card Presence Detect Interrupt Flag
+ *  0b0..No insertion or removal of Smart Card detected on Port (default)
+ *  0b1..Insertion or removal of Smart Card detected on Port
+ */
+#define EMVSIM_PCSR_SPDIF(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK)
+#define EMVSIM_PCSR_SPDP_MASK                    (0x4000000U)
+#define EMVSIM_PCSR_SPDP_SHIFT                   (26U)
+/*! SPDP - Smart Card Presence Detect Pin Status
+ *  0b0..SIM Presence Detect pin is logic low
+ *  0b1..SIM Presence Detectpin is logic high
+ */
+#define EMVSIM_PCSR_SPDP(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK)
+#define EMVSIM_PCSR_SPDES_MASK                   (0x8000000U)
+#define EMVSIM_PCSR_SPDES_SHIFT                  (27U)
+/*! SPDES - SIM Presence Detect Edge Select
+ *  0b0..Falling edge on the pin (default)
+ *  0b1..Rising edge on the pin
+ */
+#define EMVSIM_PCSR_SPDES(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK)
+/*! @} */
+
+/*! @name RX_BUF - Receive Data Read Buffer */
+/*! @{ */
+#define EMVSIM_RX_BUF_RX_BYTE_MASK               (0xFFU)
+#define EMVSIM_RX_BUF_RX_BYTE_SHIFT              (0U)
+#define EMVSIM_RX_BUF_RX_BYTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK)
+/*! @} */
+
+/*! @name TX_BUF - Transmit Data Buffer */
+/*! @{ */
+#define EMVSIM_TX_BUF_TX_BYTE_MASK               (0xFFU)
+#define EMVSIM_TX_BUF_TX_BYTE_SHIFT              (0U)
+#define EMVSIM_TX_BUF_TX_BYTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK)
+/*! @} */
+
+/*! @name TX_GETU - Transmitter Guard ETU Value Register */
+/*! @{ */
+#define EMVSIM_TX_GETU_GETU_MASK                 (0xFFU)
+#define EMVSIM_TX_GETU_GETU_SHIFT                (0U)
+/*! GETU - Transmitter Guard Time Value in ETU
+ *  0b00000000..no additional ETUs inserted (default)
+ *  0b00000001..1 additional ETU inserted
+ *  0b11111110..254 additional ETUs inserted
+ *  0b11111111..Subtracts one ETU by reducing the number of STOP bits from two to one
+ */
+#define EMVSIM_TX_GETU_GETU(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
+/*! @} */
+
+/*! @name CWT_VAL - Character Wait Time Value Register */
+/*! @{ */
+#define EMVSIM_CWT_VAL_CWT_MASK                  (0xFFFFU)
+#define EMVSIM_CWT_VAL_CWT_SHIFT                 (0U)
+#define EMVSIM_CWT_VAL_CWT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK)
+/*! @} */
+
+/*! @name BWT_VAL - Block Wait Time Value Register */
+/*! @{ */
+#define EMVSIM_BWT_VAL_BWT_MASK                  (0xFFFFFFFFU)
+#define EMVSIM_BWT_VAL_BWT_SHIFT                 (0U)
+#define EMVSIM_BWT_VAL_BWT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK)
+/*! @} */
+
+/*! @name BGT_VAL - Block Guard Time Value Register */
+/*! @{ */
+#define EMVSIM_BGT_VAL_BGT_MASK                  (0xFFFFU)
+#define EMVSIM_BGT_VAL_BGT_SHIFT                 (0U)
+#define EMVSIM_BGT_VAL_BGT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK)
+/*! @} */
+
+/*! @name GPCNT0_VAL - General Purpose Counter 0 Timeout Value Register */
+/*! @{ */
+#define EMVSIM_GPCNT0_VAL_GPCNT0_MASK            (0xFFFFU)
+#define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT           (0U)
+#define EMVSIM_GPCNT0_VAL_GPCNT0(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK)
+/*! @} */
+
+/*! @name GPCNT1_VAL - General Purpose Counter 1 Timeout Value */
+/*! @{ */
+#define EMVSIM_GPCNT1_VAL_GPCNT1_MASK            (0xFFFFU)
+#define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT           (0U)
+#define EMVSIM_GPCNT1_VAL_GPCNT1(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group EMVSIM_Register_Masks */
+
+
+/* EMVSIM - Peripheral instance base addresses */
+/** Peripheral EMVSIM0 base address */
+#define EMVSIM0_BASE                             (0x40038000u)
+/** Peripheral EMVSIM0 base pointer */
+#define EMVSIM0                                  ((EMVSIM_Type *)EMVSIM0_BASE)
+/** Array initializer of EMVSIM peripheral base addresses */
+#define EMVSIM_BASE_ADDRS                        { EMVSIM0_BASE }
+/** Array initializer of EMVSIM peripheral base pointers */
+#define EMVSIM_BASE_PTRS                         { EMVSIM0 }
+/** Interrupt vectors for the EMVSIM peripheral type */
+#define EMVSIM_IRQS                              { EMVSIM0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group EMVSIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EVENT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EVENT_Peripheral_Access_Layer EVENT Peripheral Access Layer
+ * @{
+ */
+
+/** EVENT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t INTPTEN;                           /**< Interrupt Enable Register, offset: 0x0 */
+  __IO uint32_t INTPTPEND;                         /**< Interrupt Pengding Register, offset: 0x4 */
+  __IO uint32_t INTPTPENDSET;                      /**< Set Interrupt Pengding Register, offset: 0x8 */
+  __IO uint32_t INTPTPENDCLEAR;                    /**< Clear Interrupt Pengding Register, offset: 0xC */
+  __IO uint32_t INTPTSECURE;                       /**< Interrupt Secure Register, offset: 0x10 */
+  __IO uint32_t INTPTPRI[4];                       /**< Interrupt Priority 0 Register..Interrupt Priority 3 Register, array offset: 0x14, array step: 0x4 */
+  __IO uint32_t INTPRIBASE;                        /**< Interrupt Priority Base, offset: 0x24 */
+  __I  uint32_t INTPTENACTIVE;                     /**< Interrupt Active Register, offset: 0x28 */
+  __I  uint32_t INTACTPRI[4];                      /**< Interrupt Active Priority 0 Register..Interrupt Active Priority 3 Register, array offset: 0x2C, array step: 0x4 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t EVENTEN;                           /**< Event Enable Register, offset: 0x40 */
+  __IO uint32_t EVENTPEND;                         /**< Event Pengding Register, offset: 0x44 */
+  __IO uint32_t EVTPENDSET;                        /**< Set Event Pengding Register, offset: 0x48 */
+  __IO uint32_t EVTPENDCLEAR;                      /**< Clear Event Pengding Register, offset: 0x4C */
+       uint8_t RESERVED_1[48];
+  __IO uint32_t SLPCTRL;                           /**< Sleep Control Register, offset: 0x80 */
+  __IO uint32_t SLPSTATUS;                         /**< Sleep Status Register, offset: 0x84 */
+} EVENT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- EVENT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EVENT_Register_Masks EVENT Register Masks
+ * @{
+ */
+
+/*! @name INTPTEN - Interrupt Enable Register */
+/*! @{ */
+#define EVENT_INTPTEN_IEN_MASK                   (0xFFFFFFFFU)
+#define EVENT_INTPTEN_IEN_SHIFT                  (0U)
+/*! IEN - Interrupt n Enable
+ *  0b00000000000000000000000000000000..Interrupt n is disabled.
+ *  0b00000000000000000000000000000001..Interrupt n is enabled.
+ */
+#define EVENT_INTPTEN_IEN(x)                     (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTEN_IEN_SHIFT)) & EVENT_INTPTEN_IEN_MASK)
+/*! @} */
+
+/*! @name INTPTPEND - Interrupt Pengding Register */
+/*! @{ */
+#define EVENT_INTPTPEND_IPEND_MASK               (0xFFFFFFFFU)
+#define EVENT_INTPTPEND_IPEND_SHIFT              (0U)
+/*! IPEND - Interrupt n Pending
+ *  0b00000000000000000000000000000000..Interrupt n is not pending.
+ *  0b00000000000000000000000000000001..Interrupt n is pending.
+ */
+#define EVENT_INTPTPEND_IPEND(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPEND_IPEND_SHIFT)) & EVENT_INTPTPEND_IPEND_MASK)
+/*! @} */
+
+/*! @name INTPTPENDSET - Set Interrupt Pengding Register */
+/*! @{ */
+#define EVENT_INTPTPENDSET_IPENDSET_MASK         (0xFFFFFFFFU)
+#define EVENT_INTPTPENDSET_IPENDSET_SHIFT        (0U)
+/*! IPENDSET - Set Interrupt n Pending
+ *  0b00000000000000000000000000000000..Not set interrupt n in pending status
+ *  0b00000000000000000000000000000001..Set interrupt n in pending status.
+ */
+#define EVENT_INTPTPENDSET_IPENDSET(x)           (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPENDSET_IPENDSET_SHIFT)) & EVENT_INTPTPENDSET_IPENDSET_MASK)
+/*! @} */
+
+/*! @name INTPTPENDCLEAR - Clear Interrupt Pengding Register */
+/*! @{ */
+#define EVENT_INTPTPENDCLEAR_IPENDCLEAR_MASK     (0xFFFFFFFFU)
+#define EVENT_INTPTPENDCLEAR_IPENDCLEAR_SHIFT    (0U)
+/*! IPENDCLEAR - Clear Interrupt n out of Pending
+ *  0b00000000000000000000000000000000..Not clear interrupt n out of pending status
+ *  0b00000000000000000000000000000001..Clear interrupt n out of pending status.
+ */
+#define EVENT_INTPTPENDCLEAR_IPENDCLEAR(x)       (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPENDCLEAR_IPENDCLEAR_SHIFT)) & EVENT_INTPTPENDCLEAR_IPENDCLEAR_MASK)
+/*! @} */
+
+/*! @name INTPTSECURE - Interrupt Secure Register */
+/*! @{ */
+#define EVENT_INTPTSECURE_ISECURE_MASK           (0xFFFFFFFFU)
+#define EVENT_INTPTSECURE_ISECURE_SHIFT          (0U)
+/*! ISECURE - Set secure feature of Interrupt n
+ *  0b00000000000000000000000000000000..Set interrupt n out of security
+ *  0b00000000000000000000000000000001..Set interrupt n in secruity.
+ */
+#define EVENT_INTPTSECURE_ISECURE(x)             (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTSECURE_ISECURE_SHIFT)) & EVENT_INTPTSECURE_ISECURE_MASK)
+/*! @} */
+
+/*! @name INTPTPRI - Interrupt Priority 0 Register..Interrupt Priority 3 Register */
+/*! @{ */
+#define EVENT_INTPTPRI_IPRI0_MASK                (0x7U)
+#define EVENT_INTPTPRI_IPRI0_SHIFT               (0U)
+#define EVENT_INTPTPRI_IPRI0(x)                  (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI0_SHIFT)) & EVENT_INTPTPRI_IPRI0_MASK)
+#define EVENT_INTPTPRI_IPRI8_MASK                (0x7U)
+#define EVENT_INTPTPRI_IPRI8_SHIFT               (0U)
+#define EVENT_INTPTPRI_IPRI8(x)                  (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI8_SHIFT)) & EVENT_INTPTPRI_IPRI8_MASK)
+#define EVENT_INTPTPRI_IPRI16_MASK               (0x7U)
+#define EVENT_INTPTPRI_IPRI16_SHIFT              (0U)
+#define EVENT_INTPTPRI_IPRI16(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI16_SHIFT)) & EVENT_INTPTPRI_IPRI16_MASK)
+#define EVENT_INTPTPRI_IPRI24_MASK               (0x7U)
+#define EVENT_INTPTPRI_IPRI24_SHIFT              (0U)
+#define EVENT_INTPTPRI_IPRI24(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI24_SHIFT)) & EVENT_INTPTPRI_IPRI24_MASK)
+#define EVENT_INTPTPRI_IPRI1_MASK                (0x70U)
+#define EVENT_INTPTPRI_IPRI1_SHIFT               (4U)
+#define EVENT_INTPTPRI_IPRI1(x)                  (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI1_SHIFT)) & EVENT_INTPTPRI_IPRI1_MASK)
+#define EVENT_INTPTPRI_IPRI9_MASK                (0x70U)
+#define EVENT_INTPTPRI_IPRI9_SHIFT               (4U)
+#define EVENT_INTPTPRI_IPRI9(x)                  (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI9_SHIFT)) & EVENT_INTPTPRI_IPRI9_MASK)
+#define EVENT_INTPTPRI_IPRI17_MASK               (0x70U)
+#define EVENT_INTPTPRI_IPRI17_SHIFT              (4U)
+#define EVENT_INTPTPRI_IPRI17(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI17_SHIFT)) & EVENT_INTPTPRI_IPRI17_MASK)
+#define EVENT_INTPTPRI_IPRI25_MASK               (0x70U)
+#define EVENT_INTPTPRI_IPRI25_SHIFT              (4U)
+#define EVENT_INTPTPRI_IPRI25(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI25_SHIFT)) & EVENT_INTPTPRI_IPRI25_MASK)
+#define EVENT_INTPTPRI_IPRI2_MASK                (0x700U)
+#define EVENT_INTPTPRI_IPRI2_SHIFT               (8U)
+#define EVENT_INTPTPRI_IPRI2(x)                  (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI2_SHIFT)) & EVENT_INTPTPRI_IPRI2_MASK)
+#define EVENT_INTPTPRI_IPRI10_MASK               (0x700U)
+#define EVENT_INTPTPRI_IPRI10_SHIFT              (8U)
+#define EVENT_INTPTPRI_IPRI10(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI10_SHIFT)) & EVENT_INTPTPRI_IPRI10_MASK)
+#define EVENT_INTPTPRI_IPRI18_MASK               (0x700U)
+#define EVENT_INTPTPRI_IPRI18_SHIFT              (8U)
+#define EVENT_INTPTPRI_IPRI18(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI18_SHIFT)) & EVENT_INTPTPRI_IPRI18_MASK)
+#define EVENT_INTPTPRI_IPRI26_MASK               (0x700U)
+#define EVENT_INTPTPRI_IPRI26_SHIFT              (8U)
+#define EVENT_INTPTPRI_IPRI26(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI26_SHIFT)) & EVENT_INTPTPRI_IPRI26_MASK)
+#define EVENT_INTPTPRI_IPRI3_MASK                (0x7000U)
+#define EVENT_INTPTPRI_IPRI3_SHIFT               (12U)
+#define EVENT_INTPTPRI_IPRI3(x)                  (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI3_SHIFT)) & EVENT_INTPTPRI_IPRI3_MASK)
+#define EVENT_INTPTPRI_IPRI11_MASK               (0x7000U)
+#define EVENT_INTPTPRI_IPRI11_SHIFT              (12U)
+#define EVENT_INTPTPRI_IPRI11(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI11_SHIFT)) & EVENT_INTPTPRI_IPRI11_MASK)
+#define EVENT_INTPTPRI_IPRI19_MASK               (0x7000U)
+#define EVENT_INTPTPRI_IPRI19_SHIFT              (12U)
+#define EVENT_INTPTPRI_IPRI19(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI19_SHIFT)) & EVENT_INTPTPRI_IPRI19_MASK)
+#define EVENT_INTPTPRI_IPRI27_MASK               (0x7000U)
+#define EVENT_INTPTPRI_IPRI27_SHIFT              (12U)
+#define EVENT_INTPTPRI_IPRI27(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI27_SHIFT)) & EVENT_INTPTPRI_IPRI27_MASK)
+#define EVENT_INTPTPRI_IPRI4_MASK                (0x70000U)
+#define EVENT_INTPTPRI_IPRI4_SHIFT               (16U)
+#define EVENT_INTPTPRI_IPRI4(x)                  (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI4_SHIFT)) & EVENT_INTPTPRI_IPRI4_MASK)
+#define EVENT_INTPTPRI_IPRI12_MASK               (0x70000U)
+#define EVENT_INTPTPRI_IPRI12_SHIFT              (16U)
+#define EVENT_INTPTPRI_IPRI12(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI12_SHIFT)) & EVENT_INTPTPRI_IPRI12_MASK)
+#define EVENT_INTPTPRI_IPRI20_MASK               (0x70000U)
+#define EVENT_INTPTPRI_IPRI20_SHIFT              (16U)
+#define EVENT_INTPTPRI_IPRI20(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI20_SHIFT)) & EVENT_INTPTPRI_IPRI20_MASK)
+#define EVENT_INTPTPRI_IPRI28_MASK               (0x70000U)
+#define EVENT_INTPTPRI_IPRI28_SHIFT              (16U)
+#define EVENT_INTPTPRI_IPRI28(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI28_SHIFT)) & EVENT_INTPTPRI_IPRI28_MASK)
+#define EVENT_INTPTPRI_IPRI5_MASK                (0x700000U)
+#define EVENT_INTPTPRI_IPRI5_SHIFT               (20U)
+#define EVENT_INTPTPRI_IPRI5(x)                  (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI5_SHIFT)) & EVENT_INTPTPRI_IPRI5_MASK)
+#define EVENT_INTPTPRI_IPRI13_MASK               (0x700000U)
+#define EVENT_INTPTPRI_IPRI13_SHIFT              (20U)
+#define EVENT_INTPTPRI_IPRI13(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI13_SHIFT)) & EVENT_INTPTPRI_IPRI13_MASK)
+#define EVENT_INTPTPRI_IPRI21_MASK               (0x700000U)
+#define EVENT_INTPTPRI_IPRI21_SHIFT              (20U)
+#define EVENT_INTPTPRI_IPRI21(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI21_SHIFT)) & EVENT_INTPTPRI_IPRI21_MASK)
+#define EVENT_INTPTPRI_IPRI29_MASK               (0x700000U)
+#define EVENT_INTPTPRI_IPRI29_SHIFT              (20U)
+#define EVENT_INTPTPRI_IPRI29(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI29_SHIFT)) & EVENT_INTPTPRI_IPRI29_MASK)
+#define EVENT_INTPTPRI_IPRI6_MASK                (0x7000000U)
+#define EVENT_INTPTPRI_IPRI6_SHIFT               (24U)
+#define EVENT_INTPTPRI_IPRI6(x)                  (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI6_SHIFT)) & EVENT_INTPTPRI_IPRI6_MASK)
+#define EVENT_INTPTPRI_IPRI14_MASK               (0x7000000U)
+#define EVENT_INTPTPRI_IPRI14_SHIFT              (24U)
+#define EVENT_INTPTPRI_IPRI14(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI14_SHIFT)) & EVENT_INTPTPRI_IPRI14_MASK)
+#define EVENT_INTPTPRI_IPRI22_MASK               (0x7000000U)
+#define EVENT_INTPTPRI_IPRI22_SHIFT              (24U)
+#define EVENT_INTPTPRI_IPRI22(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI22_SHIFT)) & EVENT_INTPTPRI_IPRI22_MASK)
+#define EVENT_INTPTPRI_IPRI30_MASK               (0x7000000U)
+#define EVENT_INTPTPRI_IPRI30_SHIFT              (24U)
+#define EVENT_INTPTPRI_IPRI30(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI30_SHIFT)) & EVENT_INTPTPRI_IPRI30_MASK)
+#define EVENT_INTPTPRI_IPRI7_MASK                (0x70000000U)
+#define EVENT_INTPTPRI_IPRI7_SHIFT               (28U)
+#define EVENT_INTPTPRI_IPRI7(x)                  (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI7_SHIFT)) & EVENT_INTPTPRI_IPRI7_MASK)
+#define EVENT_INTPTPRI_IPRI15_MASK               (0x70000000U)
+#define EVENT_INTPTPRI_IPRI15_SHIFT              (28U)
+#define EVENT_INTPTPRI_IPRI15(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI15_SHIFT)) & EVENT_INTPTPRI_IPRI15_MASK)
+#define EVENT_INTPTPRI_IPRI23_MASK               (0x70000000U)
+#define EVENT_INTPTPRI_IPRI23_SHIFT              (28U)
+#define EVENT_INTPTPRI_IPRI23(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI23_SHIFT)) & EVENT_INTPTPRI_IPRI23_MASK)
+#define EVENT_INTPTPRI_IPRI31_MASK               (0x70000000U)
+#define EVENT_INTPTPRI_IPRI31_SHIFT              (28U)
+#define EVENT_INTPTPRI_IPRI31(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI31_SHIFT)) & EVENT_INTPTPRI_IPRI31_MASK)
+/*! @} */
+
+/* The count of EVENT_INTPTPRI */
+#define EVENT_INTPTPRI_COUNT                     (4U)
+
+/*! @name INTPRIBASE - Interrupt Priority Base */
+/*! @{ */
+#define EVENT_INTPRIBASE_IPBASE_MASK             (0xFU)
+#define EVENT_INTPRIBASE_IPBASE_SHIFT            (0U)
+#define EVENT_INTPRIBASE_IPBASE(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTPRIBASE_IPBASE_SHIFT)) & EVENT_INTPRIBASE_IPBASE_MASK)
+/*! @} */
+
+/*! @name INTPTENACTIVE - Interrupt Active Register */
+/*! @{ */
+#define EVENT_INTPTENACTIVE_IACTIVE_MASK         (0xFFFFFFFFU)
+#define EVENT_INTPTENACTIVE_IACTIVE_SHIFT        (0U)
+/*! IACTIVE - Interrupt n Enable
+ *  0b00000000000000000000000000000000..Interrupt n is not active.
+ *  0b00000000000000000000000000000001..Interrupt n is active..
+ */
+#define EVENT_INTPTENACTIVE_IACTIVE(x)           (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTENACTIVE_IACTIVE_SHIFT)) & EVENT_INTPTENACTIVE_IACTIVE_MASK)
+/*! @} */
+
+/*! @name INTACTPRI - Interrupt Active Priority 0 Register..Interrupt Active Priority 3 Register */
+/*! @{ */
+#define EVENT_INTACTPRI_IAPRI0_MASK              (0x7U)
+#define EVENT_INTACTPRI_IAPRI0_SHIFT             (0U)
+#define EVENT_INTACTPRI_IAPRI0(x)                (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI0_SHIFT)) & EVENT_INTACTPRI_IAPRI0_MASK)
+#define EVENT_INTACTPRI_IAPRI8_MASK              (0x7U)
+#define EVENT_INTACTPRI_IAPRI8_SHIFT             (0U)
+#define EVENT_INTACTPRI_IAPRI8(x)                (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI8_SHIFT)) & EVENT_INTACTPRI_IAPRI8_MASK)
+#define EVENT_INTACTPRI_IAPRI16_MASK             (0x7U)
+#define EVENT_INTACTPRI_IAPRI16_SHIFT            (0U)
+#define EVENT_INTACTPRI_IAPRI16(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI16_SHIFT)) & EVENT_INTACTPRI_IAPRI16_MASK)
+#define EVENT_INTACTPRI_IAPRI24_MASK             (0x7U)
+#define EVENT_INTACTPRI_IAPRI24_SHIFT            (0U)
+#define EVENT_INTACTPRI_IAPRI24(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI24_SHIFT)) & EVENT_INTACTPRI_IAPRI24_MASK)
+#define EVENT_INTACTPRI_IAPRI1_MASK              (0x70U)
+#define EVENT_INTACTPRI_IAPRI1_SHIFT             (4U)
+#define EVENT_INTACTPRI_IAPRI1(x)                (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI1_SHIFT)) & EVENT_INTACTPRI_IAPRI1_MASK)
+#define EVENT_INTACTPRI_IAPRI9_MASK              (0x70U)
+#define EVENT_INTACTPRI_IAPRI9_SHIFT             (4U)
+#define EVENT_INTACTPRI_IAPRI9(x)                (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI9_SHIFT)) & EVENT_INTACTPRI_IAPRI9_MASK)
+#define EVENT_INTACTPRI_IAPRI17_MASK             (0x70U)
+#define EVENT_INTACTPRI_IAPRI17_SHIFT            (4U)
+#define EVENT_INTACTPRI_IAPRI17(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI17_SHIFT)) & EVENT_INTACTPRI_IAPRI17_MASK)
+#define EVENT_INTACTPRI_IAPRI25_MASK             (0x70U)
+#define EVENT_INTACTPRI_IAPRI25_SHIFT            (4U)
+#define EVENT_INTACTPRI_IAPRI25(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI25_SHIFT)) & EVENT_INTACTPRI_IAPRI25_MASK)
+#define EVENT_INTACTPRI_IAPRI2_MASK              (0x700U)
+#define EVENT_INTACTPRI_IAPRI2_SHIFT             (8U)
+#define EVENT_INTACTPRI_IAPRI2(x)                (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI2_SHIFT)) & EVENT_INTACTPRI_IAPRI2_MASK)
+#define EVENT_INTACTPRI_IAPRI10_MASK             (0x700U)
+#define EVENT_INTACTPRI_IAPRI10_SHIFT            (8U)
+#define EVENT_INTACTPRI_IAPRI10(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI10_SHIFT)) & EVENT_INTACTPRI_IAPRI10_MASK)
+#define EVENT_INTACTPRI_IAPRI18_MASK             (0x700U)
+#define EVENT_INTACTPRI_IAPRI18_SHIFT            (8U)
+#define EVENT_INTACTPRI_IAPRI18(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI18_SHIFT)) & EVENT_INTACTPRI_IAPRI18_MASK)
+#define EVENT_INTACTPRI_IAPRI26_MASK             (0x700U)
+#define EVENT_INTACTPRI_IAPRI26_SHIFT            (8U)
+#define EVENT_INTACTPRI_IAPRI26(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI26_SHIFT)) & EVENT_INTACTPRI_IAPRI26_MASK)
+#define EVENT_INTACTPRI_IAPRI3_MASK              (0x7000U)
+#define EVENT_INTACTPRI_IAPRI3_SHIFT             (12U)
+#define EVENT_INTACTPRI_IAPRI3(x)                (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI3_SHIFT)) & EVENT_INTACTPRI_IAPRI3_MASK)
+#define EVENT_INTACTPRI_IAPRI11_MASK             (0x7000U)
+#define EVENT_INTACTPRI_IAPRI11_SHIFT            (12U)
+#define EVENT_INTACTPRI_IAPRI11(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI11_SHIFT)) & EVENT_INTACTPRI_IAPRI11_MASK)
+#define EVENT_INTACTPRI_IAPRI19_MASK             (0x7000U)
+#define EVENT_INTACTPRI_IAPRI19_SHIFT            (12U)
+#define EVENT_INTACTPRI_IAPRI19(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI19_SHIFT)) & EVENT_INTACTPRI_IAPRI19_MASK)
+#define EVENT_INTACTPRI_IAPRI27_MASK             (0x7000U)
+#define EVENT_INTACTPRI_IAPRI27_SHIFT            (12U)
+#define EVENT_INTACTPRI_IAPRI27(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI27_SHIFT)) & EVENT_INTACTPRI_IAPRI27_MASK)
+#define EVENT_INTACTPRI_IAPRI4_MASK              (0x70000U)
+#define EVENT_INTACTPRI_IAPRI4_SHIFT             (16U)
+#define EVENT_INTACTPRI_IAPRI4(x)                (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI4_SHIFT)) & EVENT_INTACTPRI_IAPRI4_MASK)
+#define EVENT_INTACTPRI_IAPRI12_MASK             (0x70000U)
+#define EVENT_INTACTPRI_IAPRI12_SHIFT            (16U)
+#define EVENT_INTACTPRI_IAPRI12(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI12_SHIFT)) & EVENT_INTACTPRI_IAPRI12_MASK)
+#define EVENT_INTACTPRI_IAPRI20_MASK             (0x70000U)
+#define EVENT_INTACTPRI_IAPRI20_SHIFT            (16U)
+#define EVENT_INTACTPRI_IAPRI20(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI20_SHIFT)) & EVENT_INTACTPRI_IAPRI20_MASK)
+#define EVENT_INTACTPRI_IAPRI28_MASK             (0x70000U)
+#define EVENT_INTACTPRI_IAPRI28_SHIFT            (16U)
+#define EVENT_INTACTPRI_IAPRI28(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI28_SHIFT)) & EVENT_INTACTPRI_IAPRI28_MASK)
+#define EVENT_INTACTPRI_IAPRI5_MASK              (0x700000U)
+#define EVENT_INTACTPRI_IAPRI5_SHIFT             (20U)
+#define EVENT_INTACTPRI_IAPRI5(x)                (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI5_SHIFT)) & EVENT_INTACTPRI_IAPRI5_MASK)
+#define EVENT_INTACTPRI_IAPRI13_MASK             (0x700000U)
+#define EVENT_INTACTPRI_IAPRI13_SHIFT            (20U)
+#define EVENT_INTACTPRI_IAPRI13(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI13_SHIFT)) & EVENT_INTACTPRI_IAPRI13_MASK)
+#define EVENT_INTACTPRI_IAPRI21_MASK             (0x700000U)
+#define EVENT_INTACTPRI_IAPRI21_SHIFT            (20U)
+#define EVENT_INTACTPRI_IAPRI21(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI21_SHIFT)) & EVENT_INTACTPRI_IAPRI21_MASK)
+#define EVENT_INTACTPRI_IAPRI29_MASK             (0x700000U)
+#define EVENT_INTACTPRI_IAPRI29_SHIFT            (20U)
+#define EVENT_INTACTPRI_IAPRI29(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI29_SHIFT)) & EVENT_INTACTPRI_IAPRI29_MASK)
+#define EVENT_INTACTPRI_IAPRI6_MASK              (0x7000000U)
+#define EVENT_INTACTPRI_IAPRI6_SHIFT             (24U)
+#define EVENT_INTACTPRI_IAPRI6(x)                (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI6_SHIFT)) & EVENT_INTACTPRI_IAPRI6_MASK)
+#define EVENT_INTACTPRI_IAPRI14_MASK             (0x7000000U)
+#define EVENT_INTACTPRI_IAPRI14_SHIFT            (24U)
+#define EVENT_INTACTPRI_IAPRI14(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI14_SHIFT)) & EVENT_INTACTPRI_IAPRI14_MASK)
+#define EVENT_INTACTPRI_IAPRI22_MASK             (0x7000000U)
+#define EVENT_INTACTPRI_IAPRI22_SHIFT            (24U)
+#define EVENT_INTACTPRI_IAPRI22(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI22_SHIFT)) & EVENT_INTACTPRI_IAPRI22_MASK)
+#define EVENT_INTACTPRI_IAPRI30_MASK             (0x7000000U)
+#define EVENT_INTACTPRI_IAPRI30_SHIFT            (24U)
+#define EVENT_INTACTPRI_IAPRI30(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI30_SHIFT)) & EVENT_INTACTPRI_IAPRI30_MASK)
+#define EVENT_INTACTPRI_IAPRI7_MASK              (0x70000000U)
+#define EVENT_INTACTPRI_IAPRI7_SHIFT             (28U)
+#define EVENT_INTACTPRI_IAPRI7(x)                (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI7_SHIFT)) & EVENT_INTACTPRI_IAPRI7_MASK)
+#define EVENT_INTACTPRI_IAPRI15_MASK             (0x70000000U)
+#define EVENT_INTACTPRI_IAPRI15_SHIFT            (28U)
+#define EVENT_INTACTPRI_IAPRI15(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI15_SHIFT)) & EVENT_INTACTPRI_IAPRI15_MASK)
+#define EVENT_INTACTPRI_IAPRI23_MASK             (0x70000000U)
+#define EVENT_INTACTPRI_IAPRI23_SHIFT            (28U)
+#define EVENT_INTACTPRI_IAPRI23(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI23_SHIFT)) & EVENT_INTACTPRI_IAPRI23_MASK)
+#define EVENT_INTACTPRI_IAPRI31_MASK             (0x70000000U)
+#define EVENT_INTACTPRI_IAPRI31_SHIFT            (28U)
+#define EVENT_INTACTPRI_IAPRI31(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI31_SHIFT)) & EVENT_INTACTPRI_IAPRI31_MASK)
+/*! @} */
+
+/* The count of EVENT_INTACTPRI */
+#define EVENT_INTACTPRI_COUNT                    (4U)
+
+/*! @name EVENTEN - Event Enable Register */
+/*! @{ */
+#define EVENT_EVENTEN_EEN_MASK                   (0xFFFFFFFFU)
+#define EVENT_EVENTEN_EEN_SHIFT                  (0U)
+/*! EEN - Event n Enable
+ *  0b00000000000000000000000000000000..Event n is disabled.
+ *  0b00000000000000000000000000000001..Event n is enabled.
+ */
+#define EVENT_EVENTEN_EEN(x)                     (((uint32_t)(((uint32_t)(x)) << EVENT_EVENTEN_EEN_SHIFT)) & EVENT_EVENTEN_EEN_MASK)
+/*! @} */
+
+/*! @name EVENTPEND - Event Pengding Register */
+/*! @{ */
+#define EVENT_EVENTPEND_EPEND_MASK               (0xFFFFFFFFU)
+#define EVENT_EVENTPEND_EPEND_SHIFT              (0U)
+/*! EPEND - Event n Pending
+ *  0b00000000000000000000000000000000..Event n is not pending.
+ *  0b00000000000000000000000000000001..Event n is pending.
+ */
+#define EVENT_EVENTPEND_EPEND(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_EVENTPEND_EPEND_SHIFT)) & EVENT_EVENTPEND_EPEND_MASK)
+/*! @} */
+
+/*! @name EVTPENDSET - Set Event Pengding Register */
+/*! @{ */
+#define EVENT_EVTPENDSET_EPENDSET_MASK           (0xFFFFFFFFU)
+#define EVENT_EVTPENDSET_EPENDSET_SHIFT          (0U)
+/*! EPENDSET - Set Event n Pending
+ *  0b00000000000000000000000000000000..Not set event n in pending status
+ *  0b00000000000000000000000000000001..Set event n in pending status.
+ */
+#define EVENT_EVTPENDSET_EPENDSET(x)             (((uint32_t)(((uint32_t)(x)) << EVENT_EVTPENDSET_EPENDSET_SHIFT)) & EVENT_EVTPENDSET_EPENDSET_MASK)
+/*! @} */
+
+/*! @name EVTPENDCLEAR - Clear Event Pengding Register */
+/*! @{ */
+#define EVENT_EVTPENDCLEAR_EPENDCLEAR_MASK       (0xFFFFFFFFU)
+#define EVENT_EVTPENDCLEAR_EPENDCLEAR_SHIFT      (0U)
+/*! EPENDCLEAR - Clear Event n out of Pending
+ *  0b00000000000000000000000000000000..Not clear event n out of pending status
+ *  0b00000000000000000000000000000001..Clear event n out of pending status.
+ */
+#define EVENT_EVTPENDCLEAR_EPENDCLEAR(x)         (((uint32_t)(((uint32_t)(x)) << EVENT_EVTPENDCLEAR_EPENDCLEAR_SHIFT)) & EVENT_EVTPENDCLEAR_EPENDCLEAR_MASK)
+/*! @} */
+
+/*! @name SLPCTRL - Sleep Control Register */
+/*! @{ */
+#define EVENT_SLPCTRL_SLPCTRL_MASK               (0x3U)
+#define EVENT_SLPCTRL_SLPCTRL_SHIFT              (0U)
+/*! SLPCTRL - Sleep Mode Control
+ *  0b01..Sleep enable
+ *  0b10..Deep sleep enable
+ */
+#define EVENT_SLPCTRL_SLPCTRL(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_SLPCTRL_SLPCTRL_SHIFT)) & EVENT_SLPCTRL_SLPCTRL_MASK)
+#define EVENT_SLPCTRL_SYSRSTREQST_MASK           (0x80000000U)
+#define EVENT_SLPCTRL_SYSRSTREQST_SHIFT          (31U)
+/*! SYSRSTREQST - System Reset Request
+ *  0b0..Do not send system reset request.
+ *  0b1..Send system reset request
+ */
+#define EVENT_SLPCTRL_SYSRSTREQST(x)             (((uint32_t)(((uint32_t)(x)) << EVENT_SLPCTRL_SYSRSTREQST_SHIFT)) & EVENT_SLPCTRL_SYSRSTREQST_MASK)
+/*! @} */
+
+/*! @name SLPSTATUS - Sleep Status Register */
+/*! @{ */
+#define EVENT_SLPSTATUS_SLPSTAT_MASK             (0x3U)
+#define EVENT_SLPSTATUS_SLPSTAT_SHIFT            (0U)
+/*! SLPSTAT - Sleep Status
+ *  0b01..In sleep mode
+ *  0b10..In deep sleep mode
+ */
+#define EVENT_SLPSTATUS_SLPSTAT(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_SLPSTATUS_SLPSTAT_SHIFT)) & EVENT_SLPSTATUS_SLPSTAT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group EVENT_Register_Masks */
+
+
+/* EVENT - Peripheral instance base addresses */
+/** Peripheral EVENT0 base address */
+#define EVENT0_BASE                              (0xE0041000u)
+/** Peripheral EVENT0 base pointer */
+#define EVENT0                                   ((EVENT_Type *)EVENT0_BASE)
+/** Array initializer of EVENT peripheral base addresses */
+#define EVENT_BASE_ADDRS                         { EVENT0_BASE }
+/** Array initializer of EVENT peripheral base pointers */
+#define EVENT_BASE_PTRS                          { EVENT0 }
+
+/*!
+ * @}
+ */ /* end of group EVENT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EWM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
+ * @{
+ */
+
+/** EWM - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CTRL;                               /**< Control Register, offset: 0x0 */
+  __O  uint8_t SERV;                               /**< Service Register, offset: 0x1 */
+  __IO uint8_t CMPL;                               /**< Compare Low Register, offset: 0x2 */
+  __IO uint8_t CMPH;                               /**< Compare High Register, offset: 0x3 */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t CLKPRESCALER;                       /**< Clock Prescaler Register, offset: 0x5 */
+} EWM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- EWM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control Register */
+/*! @{ */
+#define EWM_CTRL_EWMEN_MASK                      (0x1U)
+#define EWM_CTRL_EWMEN_SHIFT                     (0U)
+#define EWM_CTRL_EWMEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
+#define EWM_CTRL_ASSIN_MASK                      (0x2U)
+#define EWM_CTRL_ASSIN_SHIFT                     (1U)
+#define EWM_CTRL_ASSIN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
+#define EWM_CTRL_INEN_MASK                       (0x4U)
+#define EWM_CTRL_INEN_SHIFT                      (2U)
+#define EWM_CTRL_INEN(x)                         (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
+#define EWM_CTRL_INTEN_MASK                      (0x8U)
+#define EWM_CTRL_INTEN_SHIFT                     (3U)
+#define EWM_CTRL_INTEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
+/*! @} */
+
+/*! @name SERV - Service Register */
+/*! @{ */
+#define EWM_SERV_SERVICE_MASK                    (0xFFU)
+#define EWM_SERV_SERVICE_SHIFT                   (0U)
+#define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
+/*! @} */
+
+/*! @name CMPL - Compare Low Register */
+/*! @{ */
+#define EWM_CMPL_COMPAREL_MASK                   (0xFFU)
+#define EWM_CMPL_COMPAREL_SHIFT                  (0U)
+#define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
+/*! @} */
+
+/*! @name CMPH - Compare High Register */
+/*! @{ */
+#define EWM_CMPH_COMPAREH_MASK                   (0xFFU)
+#define EWM_CMPH_COMPAREH_SHIFT                  (0U)
+#define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
+/*! @} */
+
+/*! @name CLKPRESCALER - Clock Prescaler Register */
+/*! @{ */
+#define EWM_CLKPRESCALER_CLK_DIV_MASK            (0xFFU)
+#define EWM_CLKPRESCALER_CLK_DIV_SHIFT           (0U)
+#define EWM_CLKPRESCALER_CLK_DIV(x)              (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Masks */
+
+
+/* EWM - Peripheral instance base addresses */
+/** Peripheral EWM base address */
+#define EWM_BASE                                 (0x40022000u)
+/** Peripheral EWM base pointer */
+#define EWM                                      ((EWM_Type *)EWM_BASE)
+/** Array initializer of EWM peripheral base addresses */
+#define EWM_BASE_ADDRS                           { EWM_BASE }
+/** Array initializer of EWM peripheral base pointers */
+#define EWM_BASE_PTRS                            { EWM }
+/** Interrupt vectors for the EWM peripheral type */
+#define EWM_IRQS                                 { EWM_IRQn }
+
+/*!
+ * @}
+ */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
+ * @{
+ */
+
+/** FB - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0xC */
+    __IO uint32_t CSAR;                              /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
+    __IO uint32_t CSMR;                              /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
+    __IO uint32_t CSCR;                              /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
+  } CS[6];
+       uint8_t RESERVED_0[24];
+  __IO uint32_t CSPMCR;                            /**< Chip Select Port Multiplexing Control Register, offset: 0x60 */
+} FB_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Masks FB Register Masks
+ * @{
+ */
+
+/*! @name CSAR - Chip Select Address Register */
+/*! @{ */
+#define FB_CSAR_BA_MASK                          (0xFFFF0000U)
+#define FB_CSAR_BA_SHIFT                         (16U)
+#define FB_CSAR_BA(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
+/*! @} */
+
+/* The count of FB_CSAR */
+#define FB_CSAR_COUNT                            (6U)
+
+/*! @name CSMR - Chip Select Mask Register */
+/*! @{ */
+#define FB_CSMR_V_MASK                           (0x1U)
+#define FB_CSMR_V_SHIFT                          (0U)
+/*! V - Valid
+ *  0b0..Chip-select is invalid.
+ *  0b1..Chip-select is valid.
+ */
+#define FB_CSMR_V(x)                             (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
+#define FB_CSMR_WP_MASK                          (0x100U)
+#define FB_CSMR_WP_SHIFT                         (8U)
+/*! WP - Write Protect
+ *  0b0..Write accesses are allowed.
+ *  0b1..Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle.
+ */
+#define FB_CSMR_WP(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
+#define FB_CSMR_BAM_MASK                         (0xFFFF0000U)
+#define FB_CSMR_BAM_SHIFT                        (16U)
+/*! BAM - Base Address Mask
+ *  0b0000000000000000..The corresponding address bit in CSAR is used in the chip-select decode.
+ *  0b0000000000000001..The corresponding address bit in CSAR is a don't care in the chip-select decode.
+ */
+#define FB_CSMR_BAM(x)                           (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
+/*! @} */
+
+/* The count of FB_CSMR */
+#define FB_CSMR_COUNT                            (6U)
+
+/*! @name CSCR - Chip Select Control Register */
+/*! @{ */
+#define FB_CSCR_BSTW_MASK                        (0x8U)
+#define FB_CSCR_BSTW_SHIFT                       (3U)
+/*! BSTW - Burst-Write Enable
+ *  0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes.
+ *  0b1..Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
+ */
+#define FB_CSCR_BSTW(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
+#define FB_CSCR_BSTR_MASK                        (0x10U)
+#define FB_CSCR_BSTR_SHIFT                       (4U)
+/*! BSTR - Burst-Read Enable
+ *  0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads.
+ *  0b1..Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
+ */
+#define FB_CSCR_BSTR(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
+#define FB_CSCR_BEM_MASK                         (0x20U)
+#define FB_CSCR_BEM_SHIFT                        (5U)
+/*! BEM - Byte-Enable Mode
+ *  0b0..FB_BE_B is asserted for data write only.
+ *  0b1..FB_BE_B is asserted for data read and write accesses.
+ */
+#define FB_CSCR_BEM(x)                           (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
+#define FB_CSCR_PS_MASK                          (0xC0U)
+#define FB_CSCR_PS_SHIFT                         (6U)
+/*! PS - Port Size
+ *  0b00..32-bit port size. Valid data is sampled and driven on FB_D[31:0].
+ *  0b01..8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b.
+ *  0b1x..16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b.
+ */
+#define FB_CSCR_PS(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
+#define FB_CSCR_AA_MASK                          (0x100U)
+#define FB_CSCR_AA_SHIFT                         (8U)
+/*! AA - Auto-Acknowledge Enable
+ *  0b0..Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally.
+ *  0b1..Enabled. Internal transfer acknowledge is asserted as specified by WS.
+ */
+#define FB_CSCR_AA(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
+#define FB_CSCR_BLS_MASK                         (0x200U)
+#define FB_CSCR_BLS_SHIFT                        (9U)
+/*! BLS - Byte-Lane Shift
+ *  0b0..Not shifted. Data is left-aligned on FB_AD.
+ *  0b1..Shifted. Data is right-aligned on FB_AD.
+ */
+#define FB_CSCR_BLS(x)                           (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
+#define FB_CSCR_WS_MASK                          (0xFC00U)
+#define FB_CSCR_WS_SHIFT                         (10U)
+#define FB_CSCR_WS(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
+#define FB_CSCR_WRAH_MASK                        (0x30000U)
+#define FB_CSCR_WRAH_SHIFT                       (16U)
+/*! WRAH - Write Address Hold or Deselect
+ *  0b00..1 cycle (default for all but FB_CS0_B)
+ *  0b01..2 cycles
+ *  0b10..3 cycles
+ *  0b11..4 cycles (default for FB_CS0_B)
+ */
+#define FB_CSCR_WRAH(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
+#define FB_CSCR_RDAH_MASK                        (0xC0000U)
+#define FB_CSCR_RDAH_SHIFT                       (18U)
+/*! RDAH - Read Address Hold or Deselect
+ *  0b00..When AA is 1b, 1 cycle. When AA is 0b, 0 cycles.
+ *  0b01..When AA is 1b, 2 cycles. When AA is 0b, 1 cycle.
+ *  0b10..When AA is 1b, 3 cycles. When AA is 0b, 2 cycles.
+ *  0b11..When AA is 1b, 4 cycles. When AA is 0b, 3 cycles.
+ */
+#define FB_CSCR_RDAH(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
+#define FB_CSCR_ASET_MASK                        (0x300000U)
+#define FB_CSCR_ASET_SHIFT                       (20U)
+/*! ASET - Address Setup
+ *  0b00..Assert FB_CSn_B on the first rising clock edge after the address is asserted (default for all but FB_CS0_B).
+ *  0b01..Assert FB_CSn_B on the second rising clock edge after the address is asserted.
+ *  0b10..Assert FB_CSn_B on the third rising clock edge after the address is asserted.
+ *  0b11..Assert FB_CSn_B on the fourth rising clock edge after the address is asserted (default for FB_CS0_B ).
+ */
+#define FB_CSCR_ASET(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
+#define FB_CSCR_EXTS_MASK                        (0x400000U)
+#define FB_CSCR_EXTS_SHIFT                       (22U)
+/*! EXTS - EXTS
+ *  0b0..Disabled. FB_TS_B/FB_ALE asserts for one bus clock cycle.
+ *  0b1..Enabled. FB_TS_B/FB_ALE remains asserted until the first positive clock edge after FB_CSn_B asserts.
+ */
+#define FB_CSCR_EXTS(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
+#define FB_CSCR_SWSEN_MASK                       (0x800000U)
+#define FB_CSCR_SWSEN_SHIFT                      (23U)
+/*! SWSEN - Secondary Wait State Enable
+ *  0b0..Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers.
+ *  0b1..Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations.
+ */
+#define FB_CSCR_SWSEN(x)                         (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
+#define FB_CSCR_SWS_MASK                         (0xFC000000U)
+#define FB_CSCR_SWS_SHIFT                        (26U)
+#define FB_CSCR_SWS(x)                           (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
+/*! @} */
+
+/* The count of FB_CSCR */
+#define FB_CSCR_COUNT                            (6U)
+
+/*! @name CSPMCR - Chip Select Port Multiplexing Control Register */
+/*! @{ */
+#define FB_CSPMCR_GROUP5_MASK                    (0xF000U)
+#define FB_CSPMCR_GROUP5_SHIFT                   (12U)
+/*! GROUP5 - FlexBus Signal Group 5 Multiplex control
+ *  0b0000..FB_TA_B
+ *  0b0001..FB_CS3_B. You must also write 1b to CSCR[AA].
+ *  0b0010..FB_BE_7_0_B. You must also write 1b to CSCR[AA].
+ */
+#define FB_CSPMCR_GROUP5(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
+#define FB_CSPMCR_GROUP4_MASK                    (0xF0000U)
+#define FB_CSPMCR_GROUP4_SHIFT                   (16U)
+/*! GROUP4 - FlexBus Signal Group 4 Multiplex control
+ *  0b0000..FB_TBST_B
+ *  0b0001..FB_CS2_B
+ *  0b0010..FB_BE_15_8_B
+ */
+#define FB_CSPMCR_GROUP4(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
+#define FB_CSPMCR_GROUP3_MASK                    (0xF00000U)
+#define FB_CSPMCR_GROUP3_SHIFT                   (20U)
+/*! GROUP3 - FlexBus Signal Group 3 Multiplex control
+ *  0b0000..FB_CS5_B
+ *  0b0001..FB_TSIZ1
+ *  0b0010..FB_BE_23_16_B
+ */
+#define FB_CSPMCR_GROUP3(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
+#define FB_CSPMCR_GROUP2_MASK                    (0xF000000U)
+#define FB_CSPMCR_GROUP2_SHIFT                   (24U)
+/*! GROUP2 - FlexBus Signal Group 2 Multiplex control
+ *  0b0000..FB_CS4_B
+ *  0b0001..FB_TSIZ0
+ *  0b0010..FB_BE_31_24_B
+ */
+#define FB_CSPMCR_GROUP2(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
+#define FB_CSPMCR_GROUP1_MASK                    (0xF0000000U)
+#define FB_CSPMCR_GROUP1_SHIFT                   (28U)
+/*! GROUP1 - FlexBus Signal Group 1 Multiplex control
+ *  0b0000..FB_ALE
+ *  0b0001..FB_CS1_B
+ *  0b0010..FB_TS_B
+ */
+#define FB_CSPMCR_GROUP1(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Masks */
+
+
+/* FB - Peripheral instance base addresses */
+/** Peripheral FB base address */
+#define FB_BASE                                  (0x4000C000u)
+/** Peripheral FB base pointer */
+#define FB                                       ((FB_Type *)FB_BASE)
+/** Array initializer of FB peripheral base addresses */
+#define FB_BASE_ADDRS                            { FB_BASE }
+/** Array initializer of FB peripheral base pointers */
+#define FB_BASE_PTRS                             { FB }
+
+/*!
+ * @}
+ */ /* end of group FB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FLEXIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
+ * @{
+ */
+
+/** FLEXIO - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __IO uint32_t CTRL;                              /**< FlexIO Control Register, offset: 0x8 */
+  __I  uint32_t PIN;                               /**< Pin State Register, offset: 0xC */
+  __IO uint32_t SHIFTSTAT;                         /**< Shifter Status Register, offset: 0x10 */
+  __IO uint32_t SHIFTERR;                          /**< Shifter Error Register, offset: 0x14 */
+  __IO uint32_t TIMSTAT;                           /**< Timer Status Register, offset: 0x18 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t SHIFTSIEN;                         /**< Shifter Status Interrupt Enable, offset: 0x20 */
+  __IO uint32_t SHIFTEIEN;                         /**< Shifter Error Interrupt Enable, offset: 0x24 */
+  __IO uint32_t TIMIEN;                            /**< Timer Interrupt Enable Register, offset: 0x28 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t SHIFTSDEN;                         /**< Shifter Status DMA Enable, offset: 0x30 */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t SHIFTSTATE;                        /**< Shifter State Register, offset: 0x40 */
+       uint8_t RESERVED_3[60];
+  __IO uint32_t SHIFTCTL[8];                       /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
+       uint8_t RESERVED_4[96];
+  __IO uint32_t SHIFTCFG[8];                       /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
+       uint8_t RESERVED_5[224];
+  __IO uint32_t SHIFTBUF[8];                       /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
+       uint8_t RESERVED_6[96];
+  __IO uint32_t SHIFTBUFBIS[8];                    /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
+       uint8_t RESERVED_7[96];
+  __IO uint32_t SHIFTBUFBYS[8];                    /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
+       uint8_t RESERVED_8[96];
+  __IO uint32_t SHIFTBUFBBS[8];                    /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
+       uint8_t RESERVED_9[96];
+  __IO uint32_t TIMCTL[8];                         /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
+       uint8_t RESERVED_10[96];
+  __IO uint32_t TIMCFG[8];                         /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
+       uint8_t RESERVED_11[96];
+  __IO uint32_t TIMCMP[8];                         /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
+       uint8_t RESERVED_12[352];
+  __IO uint32_t SHIFTBUFNBS[8];                    /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */
+       uint8_t RESERVED_13[96];
+  __IO uint32_t SHIFTBUFHWS[8];                    /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */
+       uint8_t RESERVED_14[96];
+  __IO uint32_t SHIFTBUFNIS[8];                    /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */
+} FLEXIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FLEXIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define FLEXIO_VERID_FEATURE_MASK                (0xFFFFU)
+#define FLEXIO_VERID_FEATURE_SHIFT               (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000000000000..Standard features implemented.
+ *  0b0000000000000001..Supports state, logic and parallel modes.
+ */
+#define FLEXIO_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
+#define FLEXIO_VERID_MINOR_MASK                  (0xFF0000U)
+#define FLEXIO_VERID_MINOR_SHIFT                 (16U)
+#define FLEXIO_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
+#define FLEXIO_VERID_MAJOR_MASK                  (0xFF000000U)
+#define FLEXIO_VERID_MAJOR_SHIFT                 (24U)
+#define FLEXIO_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define FLEXIO_PARAM_SHIFTER_MASK                (0xFFU)
+#define FLEXIO_PARAM_SHIFTER_SHIFT               (0U)
+#define FLEXIO_PARAM_SHIFTER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
+#define FLEXIO_PARAM_TIMER_MASK                  (0xFF00U)
+#define FLEXIO_PARAM_TIMER_SHIFT                 (8U)
+#define FLEXIO_PARAM_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
+#define FLEXIO_PARAM_PIN_MASK                    (0xFF0000U)
+#define FLEXIO_PARAM_PIN_SHIFT                   (16U)
+#define FLEXIO_PARAM_PIN(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
+#define FLEXIO_PARAM_TRIGGER_MASK                (0xFF000000U)
+#define FLEXIO_PARAM_TRIGGER_SHIFT               (24U)
+#define FLEXIO_PARAM_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
+/*! @} */
+
+/*! @name CTRL - FlexIO Control Register */
+/*! @{ */
+#define FLEXIO_CTRL_FLEXEN_MASK                  (0x1U)
+#define FLEXIO_CTRL_FLEXEN_SHIFT                 (0U)
+/*! FLEXEN - FlexIO Enable
+ *  0b0..FlexIO module is disabled.
+ *  0b1..FlexIO module is enabled.
+ */
+#define FLEXIO_CTRL_FLEXEN(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
+#define FLEXIO_CTRL_SWRST_MASK                   (0x2U)
+#define FLEXIO_CTRL_SWRST_SHIFT                  (1U)
+/*! SWRST - Software Reset
+ *  0b0..Software reset is disabled
+ *  0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.
+ */
+#define FLEXIO_CTRL_SWRST(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
+#define FLEXIO_CTRL_FASTACC_MASK                 (0x4U)
+#define FLEXIO_CTRL_FASTACC_SHIFT                (2U)
+/*! FASTACC - Fast Access
+ *  0b0..Configures for normal register accesses to FlexIO
+ *  0b1..Configures for fast register accesses to FlexIO
+ */
+#define FLEXIO_CTRL_FASTACC(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
+#define FLEXIO_CTRL_DBGE_MASK                    (0x40000000U)
+#define FLEXIO_CTRL_DBGE_SHIFT                   (30U)
+/*! DBGE - Debug Enable
+ *  0b0..FlexIO is disabled in debug modes.
+ *  0b1..FlexIO is enabled in debug modes
+ */
+#define FLEXIO_CTRL_DBGE(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
+#define FLEXIO_CTRL_DOZEN_MASK                   (0x80000000U)
+#define FLEXIO_CTRL_DOZEN_SHIFT                  (31U)
+/*! DOZEN - Doze Enable
+ *  0b0..FlexIO enabled in Doze modes.
+ *  0b1..FlexIO disabled in Doze modes.
+ */
+#define FLEXIO_CTRL_DOZEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
+/*! @} */
+
+/*! @name PIN - Pin State Register */
+/*! @{ */
+#define FLEXIO_PIN_PDI_MASK                      (0xFFFFFFFFU)
+#define FLEXIO_PIN_PDI_SHIFT                     (0U)
+#define FLEXIO_PIN_PDI(x)                        (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
+/*! @} */
+
+/*! @name SHIFTSTAT - Shifter Status Register */
+/*! @{ */
+#define FLEXIO_SHIFTSTAT_SSF_MASK                (0xFFU)
+#define FLEXIO_SHIFTSTAT_SSF_SHIFT               (0U)
+#define FLEXIO_SHIFTSTAT_SSF(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
+/*! @} */
+
+/*! @name SHIFTERR - Shifter Error Register */
+/*! @{ */
+#define FLEXIO_SHIFTERR_SEF_MASK                 (0xFFU)
+#define FLEXIO_SHIFTERR_SEF_SHIFT                (0U)
+#define FLEXIO_SHIFTERR_SEF(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
+/*! @} */
+
+/*! @name TIMSTAT - Timer Status Register */
+/*! @{ */
+#define FLEXIO_TIMSTAT_TSF_MASK                  (0xFFU)
+#define FLEXIO_TIMSTAT_TSF_SHIFT                 (0U)
+#define FLEXIO_TIMSTAT_TSF(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
+/*! @} */
+
+/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
+/*! @{ */
+#define FLEXIO_SHIFTSIEN_SSIE_MASK               (0xFFU)
+#define FLEXIO_SHIFTSIEN_SSIE_SHIFT              (0U)
+#define FLEXIO_SHIFTSIEN_SSIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
+/*! @} */
+
+/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
+/*! @{ */
+#define FLEXIO_SHIFTEIEN_SEIE_MASK               (0xFFU)
+#define FLEXIO_SHIFTEIEN_SEIE_SHIFT              (0U)
+#define FLEXIO_SHIFTEIEN_SEIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
+/*! @} */
+
+/*! @name TIMIEN - Timer Interrupt Enable Register */
+/*! @{ */
+#define FLEXIO_TIMIEN_TEIE_MASK                  (0xFFU)
+#define FLEXIO_TIMIEN_TEIE_SHIFT                 (0U)
+#define FLEXIO_TIMIEN_TEIE(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
+/*! @} */
+
+/*! @name SHIFTSDEN - Shifter Status DMA Enable */
+/*! @{ */
+#define FLEXIO_SHIFTSDEN_SSDE_MASK               (0xFFU)
+#define FLEXIO_SHIFTSDEN_SSDE_SHIFT              (0U)
+#define FLEXIO_SHIFTSDEN_SSDE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
+/*! @} */
+
+/*! @name SHIFTSTATE - Shifter State Register */
+/*! @{ */
+#define FLEXIO_SHIFTSTATE_STATE_MASK             (0x7U)
+#define FLEXIO_SHIFTSTATE_STATE_SHIFT            (0U)
+#define FLEXIO_SHIFTSTATE_STATE(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
+/*! @} */
+
+/*! @name SHIFTCTL - Shifter Control N Register */
+/*! @{ */
+#define FLEXIO_SHIFTCTL_SMOD_MASK                (0x7U)
+#define FLEXIO_SHIFTCTL_SMOD_SHIFT               (0U)
+/*! SMOD - Shifter Mode
+ *  0b000..Disabled.
+ *  0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
+ *  0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
+ *  0b011..Reserved.
+ *  0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
+ *  0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
+ *  0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes.
+ *  0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
+ */
+#define FLEXIO_SHIFTCTL_SMOD(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
+#define FLEXIO_SHIFTCTL_PINPOL_MASK              (0x80U)
+#define FLEXIO_SHIFTCTL_PINPOL_SHIFT             (7U)
+/*! PINPOL - Shifter Pin Polarity
+ *  0b0..Pin is active high
+ *  0b1..Pin is active low
+ */
+#define FLEXIO_SHIFTCTL_PINPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
+#define FLEXIO_SHIFTCTL_PINSEL_MASK              (0x1F00U)
+#define FLEXIO_SHIFTCTL_PINSEL_SHIFT             (8U)
+#define FLEXIO_SHIFTCTL_PINSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
+#define FLEXIO_SHIFTCTL_PINCFG_MASK              (0x30000U)
+#define FLEXIO_SHIFTCTL_PINCFG_SHIFT             (16U)
+/*! PINCFG - Shifter Pin Configuration
+ *  0b00..Shifter pin output disabled
+ *  0b01..Shifter pin open drain or bidirectional output enable
+ *  0b10..Shifter pin bidirectional output data
+ *  0b11..Shifter pin output
+ */
+#define FLEXIO_SHIFTCTL_PINCFG(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
+#define FLEXIO_SHIFTCTL_TIMPOL_MASK              (0x800000U)
+#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT             (23U)
+/*! TIMPOL - Timer Polarity
+ *  0b0..Shift on posedge of Shift clock
+ *  0b1..Shift on negedge of Shift clock
+ */
+#define FLEXIO_SHIFTCTL_TIMPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
+#define FLEXIO_SHIFTCTL_TIMSEL_MASK              (0x7000000U)
+#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT             (24U)
+#define FLEXIO_SHIFTCTL_TIMSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTCTL */
+#define FLEXIO_SHIFTCTL_COUNT                    (8U)
+
+/*! @name SHIFTCFG - Shifter Configuration N Register */
+/*! @{ */
+#define FLEXIO_SHIFTCFG_SSTART_MASK              (0x3U)
+#define FLEXIO_SHIFTCFG_SSTART_SHIFT             (0U)
+/*! SSTART - Shifter Start bit
+ *  0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
+ *  0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
+ *  0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
+ *  0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
+ */
+#define FLEXIO_SHIFTCFG_SSTART(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
+#define FLEXIO_SHIFTCFG_SSTOP_MASK               (0x30U)
+#define FLEXIO_SHIFTCFG_SSTOP_SHIFT              (4U)
+/*! SSTOP - Shifter Stop bit
+ *  0b00..Stop bit disabled for transmitter/receiver/match store
+ *  0b01..Reserved for transmitter/receiver/match store
+ *  0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
+ *  0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
+ */
+#define FLEXIO_SHIFTCFG_SSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
+#define FLEXIO_SHIFTCFG_INSRC_MASK               (0x100U)
+#define FLEXIO_SHIFTCFG_INSRC_SHIFT              (8U)
+/*! INSRC - Input Source
+ *  0b0..Pin
+ *  0b1..Shifter N+1 Output
+ */
+#define FLEXIO_SHIFTCFG_INSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
+#define FLEXIO_SHIFTCFG_PWIDTH_MASK              (0x1F0000U)
+#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT             (16U)
+#define FLEXIO_SHIFTCFG_PWIDTH(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTCFG */
+#define FLEXIO_SHIFTCFG_COUNT                    (8U)
+
+/*! @name SHIFTBUF - Shifter Buffer N Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK            (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT           (0U)
+#define FLEXIO_SHIFTBUF_SHIFTBUF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUF */
+#define FLEXIO_SHIFTBUF_COUNT                    (8U)
+
+/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK      (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT     (0U)
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFBIS */
+#define FLEXIO_SHIFTBUFBIS_COUNT                 (8U)
+
+/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK      (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT     (0U)
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFBYS */
+#define FLEXIO_SHIFTBUFBYS_COUNT                 (8U)
+
+/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK      (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT     (0U)
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFBBS */
+#define FLEXIO_SHIFTBUFBBS_COUNT                 (8U)
+
+/*! @name TIMCTL - Timer Control N Register */
+/*! @{ */
+#define FLEXIO_TIMCTL_TIMOD_MASK                 (0x3U)
+#define FLEXIO_TIMCTL_TIMOD_SHIFT                (0U)
+/*! TIMOD - Timer Mode
+ *  0b00..Timer Disabled.
+ *  0b01..Dual 8-bit counters baud mode.
+ *  0b10..Dual 8-bit counters PWM high mode.
+ *  0b11..Single 16-bit counter mode.
+ */
+#define FLEXIO_TIMCTL_TIMOD(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
+#define FLEXIO_TIMCTL_PINPOL_MASK                (0x80U)
+#define FLEXIO_TIMCTL_PINPOL_SHIFT               (7U)
+/*! PINPOL - Timer Pin Polarity
+ *  0b0..Pin is active high
+ *  0b1..Pin is active low
+ */
+#define FLEXIO_TIMCTL_PINPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
+#define FLEXIO_TIMCTL_PINSEL_MASK                (0x1F00U)
+#define FLEXIO_TIMCTL_PINSEL_SHIFT               (8U)
+#define FLEXIO_TIMCTL_PINSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
+#define FLEXIO_TIMCTL_PINCFG_MASK                (0x30000U)
+#define FLEXIO_TIMCTL_PINCFG_SHIFT               (16U)
+/*! PINCFG - Timer Pin Configuration
+ *  0b00..Timer pin output disabled
+ *  0b01..Timer pin open drain or bidirectional output enable
+ *  0b10..Timer pin bidirectional output data
+ *  0b11..Timer pin output
+ */
+#define FLEXIO_TIMCTL_PINCFG(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
+#define FLEXIO_TIMCTL_TRGSRC_MASK                (0x400000U)
+#define FLEXIO_TIMCTL_TRGSRC_SHIFT               (22U)
+/*! TRGSRC - Trigger Source
+ *  0b0..External trigger selected
+ *  0b1..Internal trigger selected
+ */
+#define FLEXIO_TIMCTL_TRGSRC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
+#define FLEXIO_TIMCTL_TRGPOL_MASK                (0x800000U)
+#define FLEXIO_TIMCTL_TRGPOL_SHIFT               (23U)
+/*! TRGPOL - Trigger Polarity
+ *  0b0..Trigger active high
+ *  0b1..Trigger active low
+ */
+#define FLEXIO_TIMCTL_TRGPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
+#define FLEXIO_TIMCTL_TRGSEL_MASK                (0x3F000000U)
+#define FLEXIO_TIMCTL_TRGSEL_SHIFT               (24U)
+#define FLEXIO_TIMCTL_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
+/*! @} */
+
+/* The count of FLEXIO_TIMCTL */
+#define FLEXIO_TIMCTL_COUNT                      (8U)
+
+/*! @name TIMCFG - Timer Configuration N Register */
+/*! @{ */
+#define FLEXIO_TIMCFG_TSTART_MASK                (0x2U)
+#define FLEXIO_TIMCFG_TSTART_SHIFT               (1U)
+/*! TSTART - Timer Start Bit
+ *  0b0..Start bit disabled
+ *  0b1..Start bit enabled
+ */
+#define FLEXIO_TIMCFG_TSTART(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
+#define FLEXIO_TIMCFG_TSTOP_MASK                 (0x30U)
+#define FLEXIO_TIMCFG_TSTOP_SHIFT                (4U)
+/*! TSTOP - Timer Stop Bit
+ *  0b00..Stop bit disabled
+ *  0b01..Stop bit is enabled on timer compare
+ *  0b10..Stop bit is enabled on timer disable
+ *  0b11..Stop bit is enabled on timer compare and timer disable
+ */
+#define FLEXIO_TIMCFG_TSTOP(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
+#define FLEXIO_TIMCFG_TIMENA_MASK                (0x700U)
+#define FLEXIO_TIMCFG_TIMENA_SHIFT               (8U)
+/*! TIMENA - Timer Enable
+ *  0b000..Timer always enabled
+ *  0b001..Timer enabled on Timer N-1 enable
+ *  0b010..Timer enabled on Trigger high
+ *  0b011..Timer enabled on Trigger high and Pin high
+ *  0b100..Timer enabled on Pin rising edge
+ *  0b101..Timer enabled on Pin rising edge and Trigger high
+ *  0b110..Timer enabled on Trigger rising edge
+ *  0b111..Timer enabled on Trigger rising or falling edge
+ */
+#define FLEXIO_TIMCFG_TIMENA(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
+#define FLEXIO_TIMCFG_TIMDIS_MASK                (0x7000U)
+#define FLEXIO_TIMCFG_TIMDIS_SHIFT               (12U)
+/*! TIMDIS - Timer Disable
+ *  0b000..Timer never disabled
+ *  0b001..Timer disabled on Timer N-1 disable
+ *  0b010..Timer disabled on Timer compare (upper 8-bits match and decrement)
+ *  0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
+ *  0b100..Timer disabled on Pin rising or falling edge
+ *  0b101..Timer disabled on Pin rising or falling edge provided Trigger is high
+ *  0b110..Timer disabled on Trigger falling edge
+ *  0b111..Reserved
+ */
+#define FLEXIO_TIMCFG_TIMDIS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
+#define FLEXIO_TIMCFG_TIMRST_MASK                (0x70000U)
+#define FLEXIO_TIMCFG_TIMRST_SHIFT               (16U)
+/*! TIMRST - Timer Reset
+ *  0b000..Timer never reset
+ *  0b001..Reserved
+ *  0b010..Timer reset on Timer Pin equal to Timer Output
+ *  0b011..Timer reset on Timer Trigger equal to Timer Output
+ *  0b100..Timer reset on Timer Pin rising edge
+ *  0b101..Reserved
+ *  0b110..Timer reset on Trigger rising edge
+ *  0b111..Timer reset on Trigger rising or falling edge
+ */
+#define FLEXIO_TIMCFG_TIMRST(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
+#define FLEXIO_TIMCFG_TIMDEC_MASK                (0x300000U)
+#define FLEXIO_TIMCFG_TIMDEC_SHIFT               (20U)
+/*! TIMDEC - Timer Decrement
+ *  0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output.
+ *  0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
+ *  0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input.
+ *  0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
+ */
+#define FLEXIO_TIMCFG_TIMDEC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
+#define FLEXIO_TIMCFG_TIMOUT_MASK                (0x3000000U)
+#define FLEXIO_TIMCFG_TIMOUT_SHIFT               (24U)
+/*! TIMOUT - Timer Output
+ *  0b00..Timer output is logic one when enabled and is not affected by timer reset
+ *  0b01..Timer output is logic zero when enabled and is not affected by timer reset
+ *  0b10..Timer output is logic one when enabled and on timer reset
+ *  0b11..Timer output is logic zero when enabled and on timer reset
+ */
+#define FLEXIO_TIMCFG_TIMOUT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
+/*! @} */
+
+/* The count of FLEXIO_TIMCFG */
+#define FLEXIO_TIMCFG_COUNT                      (8U)
+
+/*! @name TIMCMP - Timer Compare N Register */
+/*! @{ */
+#define FLEXIO_TIMCMP_CMP_MASK                   (0xFFFFU)
+#define FLEXIO_TIMCMP_CMP_SHIFT                  (0U)
+#define FLEXIO_TIMCMP_CMP(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
+/*! @} */
+
+/* The count of FLEXIO_TIMCMP */
+#define FLEXIO_TIMCMP_COUNT                      (8U)
+
+/*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK      (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT     (0U)
+#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFNBS */
+#define FLEXIO_SHIFTBUFNBS_COUNT                 (8U)
+
+/*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK      (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT     (0U)
+#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFHWS */
+#define FLEXIO_SHIFTBUFHWS_COUNT                 (8U)
+
+/*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK      (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT     (0U)
+#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFNIS */
+#define FLEXIO_SHIFTBUFNIS_COUNT                 (8U)
+
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Register_Masks */
+
+
+/* FLEXIO - Peripheral instance base addresses */
+/** Peripheral FLEXIO0 base address */
+#define FLEXIO0_BASE                             (0x40039000u)
+/** Peripheral FLEXIO0 base pointer */
+#define FLEXIO0                                  ((FLEXIO_Type *)FLEXIO0_BASE)
+/** Array initializer of FLEXIO peripheral base addresses */
+#define FLEXIO_BASE_ADDRS                        { FLEXIO0_BASE }
+/** Array initializer of FLEXIO peripheral base pointers */
+#define FLEXIO_BASE_PTRS                         { FLEXIO0 }
+/** Interrupt vectors for the FLEXIO peripheral type */
+#define FLEXIO_IRQS                              { FLEXIO0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFE Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
+ * @{
+ */
+
+/** FTFE - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t FSTAT;                              /**< Flash Status Register, offset: 0x0 */
+  __IO uint8_t FCNFG;                              /**< Flash Configuration Register, offset: 0x1 */
+  __I  uint8_t FSEC;                               /**< Flash Security Register, offset: 0x2 */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t FCCOB3;                             /**< Flash Common Command Object Registers, offset: 0x4 */
+  __IO uint8_t FCCOB2;                             /**< Flash Common Command Object Registers, offset: 0x5 */
+  __IO uint8_t FCCOB1;                             /**< Flash Common Command Object Registers, offset: 0x6 */
+  __IO uint8_t FCCOB0;                             /**< Flash Common Command Object Registers, offset: 0x7 */
+  __IO uint8_t FCCOB7;                             /**< Flash Common Command Object Registers, offset: 0x8 */
+  __IO uint8_t FCCOB6;                             /**< Flash Common Command Object Registers, offset: 0x9 */
+  __IO uint8_t FCCOB5;                             /**< Flash Common Command Object Registers, offset: 0xA */
+  __IO uint8_t FCCOB4;                             /**< Flash Common Command Object Registers, offset: 0xB */
+  __IO uint8_t FCCOBB;                             /**< Flash Common Command Object Registers, offset: 0xC */
+  __IO uint8_t FCCOBA;                             /**< Flash Common Command Object Registers, offset: 0xD */
+  __IO uint8_t FCCOB9;                             /**< Flash Common Command Object Registers, offset: 0xE */
+  __IO uint8_t FCCOB8;                             /**< Flash Common Command Object Registers, offset: 0xF */
+  __I  uint8_t FOPT3;                              /**< Flash Option Registers, offset: 0x10 */
+  __I  uint8_t FOPT2;                              /**< Flash Option Registers, offset: 0x11 */
+  __I  uint8_t FOPT1;                              /**< Flash Option Registers, offset: 0x12 */
+  __I  uint8_t FOPT0;                              /**< Flash Option Registers, offset: 0x13 */
+       uint8_t RESERVED_1[4];
+  __IO uint8_t FPROTH3;                            /**< Primary Program Flash Protection Registers, offset: 0x18 */
+  __IO uint8_t FPROTH2;                            /**< Primary Program Flash Protection Registers, offset: 0x19 */
+  __IO uint8_t FPROTH1;                            /**< Primary Program Flash Protection Registers, offset: 0x1A */
+  __IO uint8_t FPROTH0;                            /**< Primary Program Flash Protection Registers, offset: 0x1B */
+  __IO uint8_t FPROTL3;                            /**< Primary Program Flash Protection Registers, offset: 0x1C */
+  __IO uint8_t FPROTL2;                            /**< Primary Program Flash Protection Registers, offset: 0x1D */
+  __IO uint8_t FPROTL1;                            /**< Primary Program Flash Protection Registers, offset: 0x1E */
+  __IO uint8_t FPROTL0;                            /**< Primary Program Flash Protection Registers, offset: 0x1F */
+       uint8_t RESERVED_2[4];
+  __IO uint8_t FPROTSL;                            /**< Secondary Program Flash Protection Registers, offset: 0x24 */
+  __IO uint8_t FPROTSH;                            /**< Secondary Program Flash Protection Registers, offset: 0x25 */
+       uint8_t RESERVED_3[6];
+  __I  uint8_t FACSS;                              /**< Primary Flash Access Segment Size Register, offset: 0x2C */
+  __I  uint8_t FACSN;                              /**< Primary Flash Access Segment Number Register, offset: 0x2D */
+  __I  uint8_t FACSSS;                             /**< Secondary Flash Access Segment Size Register, offset: 0x2E */
+  __I  uint8_t FACSNS;                             /**< Secondary Flash Access Segment Number Register, offset: 0x2F */
+  __I  uint8_t XACCH3;                             /**< Primary Execute-only Access Registers, offset: 0x30 */
+  __I  uint8_t XACCH2;                             /**< Primary Execute-only Access Registers, offset: 0x31 */
+  __I  uint8_t XACCH1;                             /**< Primary Execute-only Access Registers, offset: 0x32 */
+  __I  uint8_t XACCH0;                             /**< Primary Execute-only Access Registers, offset: 0x33 */
+  __I  uint8_t XACCL3;                             /**< Primary Execute-only Access Registers, offset: 0x34 */
+  __I  uint8_t XACCL2;                             /**< Primary Execute-only Access Registers, offset: 0x35 */
+  __I  uint8_t XACCL1;                             /**< Primary Execute-only Access Registers, offset: 0x36 */
+  __I  uint8_t XACCL0;                             /**< Primary Execute-only Access Registers, offset: 0x37 */
+  __I  uint8_t SACCH3;                             /**< Primary Supervisor-only Access Registers, offset: 0x38 */
+  __I  uint8_t SACCH2;                             /**< Primary Supervisor-only Access Registers, offset: 0x39 */
+  __I  uint8_t SACCH1;                             /**< Primary Supervisor-only Access Registers, offset: 0x3A */
+  __I  uint8_t SACCH0;                             /**< Primary Supervisor-only Access Registers, offset: 0x3B */
+  __I  uint8_t SACCL3;                             /**< Primary Supervisor-only Access Registers, offset: 0x3C */
+  __I  uint8_t SACCL2;                             /**< Primary Supervisor-only Access Registers, offset: 0x3D */
+  __I  uint8_t SACCL1;                             /**< Primary Supervisor-only Access Registers, offset: 0x3E */
+  __I  uint8_t SACCL0;                             /**< Primary Supervisor-only Access Registers, offset: 0x3F */
+       uint8_t RESERVED_4[4];
+  __I  uint8_t XACCSL;                             /**< Secondary Execute-only Access Registers, offset: 0x44 */
+  __I  uint8_t XACCSH;                             /**< Secondary Execute-only Access Registers, offset: 0x45 */
+       uint8_t RESERVED_5[6];
+  __I  uint8_t SACCSL;                             /**< Secondary Supervisor-only Access Registers, offset: 0x4C */
+  __I  uint8_t SACCSH;                             /**< Secondary Supervisor-only Access Registers, offset: 0x4D */
+       uint8_t RESERVED_6[4];
+  __I  uint8_t FSTDBYCTL;                          /**< Flash Standby Control Register, offset: 0x52 */
+  __IO uint8_t FSTDBY;                             /**< Flash Standby Register, offset: 0x53 */
+} FTFE_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FTFE Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Masks FTFE Register Masks
+ * @{
+ */
+
+/*! @name FSTAT - Flash Status Register */
+/*! @{ */
+#define FTFE_FSTAT_MGSTAT0_MASK                  (0x1U)
+#define FTFE_FSTAT_MGSTAT0_SHIFT                 (0U)
+#define FTFE_FSTAT_MGSTAT0(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK)
+#define FTFE_FSTAT_FPVIOL_MASK                   (0x10U)
+#define FTFE_FSTAT_FPVIOL_SHIFT                  (4U)
+/*! FPVIOL - Flash Protection Violation Flag
+ *  0b0..No protection violation detected
+ *  0b1..Protection violation detected
+ */
+#define FTFE_FSTAT_FPVIOL(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)
+#define FTFE_FSTAT_ACCERR_MASK                   (0x20U)
+#define FTFE_FSTAT_ACCERR_SHIFT                  (5U)
+/*! ACCERR - Flash Access Error Flag
+ *  0b0..No access error detected
+ *  0b1..Access error detected
+ */
+#define FTFE_FSTAT_ACCERR(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)
+#define FTFE_FSTAT_RDCOLERR_MASK                 (0x40U)
+#define FTFE_FSTAT_RDCOLERR_SHIFT                (6U)
+/*! RDCOLERR - Flash Read Collision Error Flag
+ *  0b0..No collision error detected
+ *  0b1..Collision error detected
+ */
+#define FTFE_FSTAT_RDCOLERR(x)                   (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)
+#define FTFE_FSTAT_CCIF_MASK                     (0x80U)
+#define FTFE_FSTAT_CCIF_SHIFT                    (7U)
+/*! CCIF - Command Complete Interrupt Flag
+ *  0b0..Flash command in progress
+ *  0b1..Flash command has completed
+ */
+#define FTFE_FSTAT_CCIF(x)                       (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)
+/*! @} */
+
+/*! @name FCNFG - Flash Configuration Register */
+/*! @{ */
+#define FTFE_FCNFG_RAMRDY_MASK                   (0x2U)
+#define FTFE_FCNFG_RAMRDY_SHIFT                  (1U)
+/*! RAMRDY - RAM Ready
+ *  0b0..Programming acceleration RAM is not available
+ *  0b1..Programming acceleration RAM is available
+ */
+#define FTFE_FCNFG_RAMRDY(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)
+#define FTFE_FCNFG_CRCRDY_MASK                   (0x4U)
+#define FTFE_FCNFG_CRCRDY_SHIFT                  (2U)
+/*! CRCRDY - CRC Ready
+ *  0b0..Programming acceleration RAM is not available for CRC operations
+ *  0b1..Programming acceleration RAM is available for CRC operations
+ */
+#define FTFE_FCNFG_CRCRDY(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CRCRDY_SHIFT)) & FTFE_FCNFG_CRCRDY_MASK)
+#define FTFE_FCNFG_SWAP_MASK                     (0x8U)
+#define FTFE_FCNFG_SWAP_SHIFT                    (3U)
+/*! SWAP - Swap
+ *  0b0..Program flash 0 block is located at relative address 0x0000
+ *  0b1..Program flash 1 block is located at relative address 0x0000
+ */
+#define FTFE_FCNFG_SWAP(x)                       (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK)
+#define FTFE_FCNFG_ERSSUSP_MASK                  (0x10U)
+#define FTFE_FCNFG_ERSSUSP_SHIFT                 (4U)
+/*! ERSSUSP - Erase Suspend
+ *  0b0..No suspend requested
+ *  0b1..Suspend the current Erase Flash Sector command execution
+ */
+#define FTFE_FCNFG_ERSSUSP(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)
+#define FTFE_FCNFG_ERSAREQ_MASK                  (0x20U)
+#define FTFE_FCNFG_ERSAREQ_SHIFT                 (5U)
+/*! ERSAREQ - Erase All Request
+ *  0b0..No request or request complete
+ *  0b1..Request to: (1) run the Erase All Blocks command, (2) verify the erased state, (3) program the security byte in the Flash Configuration Field to the unsecure state, and (4) release MCU security by setting the FSEC[SEC] field to the unsecure state.
+ */
+#define FTFE_FCNFG_ERSAREQ(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)
+#define FTFE_FCNFG_RDCOLLIE_MASK                 (0x40U)
+#define FTFE_FCNFG_RDCOLLIE_SHIFT                (6U)
+/*! RDCOLLIE - Read Collision Error Interrupt Enable
+ *  0b0..Read collision error interrupt disabled
+ *  0b1..Read collision error interrupt enabled. An interrupt request is generated whenever a flash read collision error is detected (see the description of FSTAT[RDCOLERR]).
+ */
+#define FTFE_FCNFG_RDCOLLIE(x)                   (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)
+#define FTFE_FCNFG_CCIE_MASK                     (0x80U)
+#define FTFE_FCNFG_CCIE_SHIFT                    (7U)
+/*! CCIE - Command Complete Interrupt Enable
+ *  0b0..Command complete interrupt disabled
+ *  0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.
+ */
+#define FTFE_FCNFG_CCIE(x)                       (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)
+/*! @} */
+
+/*! @name FSEC - Flash Security Register */
+/*! @{ */
+#define FTFE_FSEC_SEC_MASK                       (0x3U)
+#define FTFE_FSEC_SEC_SHIFT                      (0U)
+/*! SEC - Flash Security
+ *  0b00..MCU security status is secure
+ *  0b01..MCU security status is secure
+ *  0b10..MCU security status is unsecure (The standard shipping condition of the flash module is unsecure.)
+ *  0b11..MCU security status is secure
+ */
+#define FTFE_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)
+#define FTFE_FSEC_FSLACC_MASK                    (0xCU)
+#define FTFE_FSEC_FSLACC_SHIFT                   (2U)
+/*! FSLACC - Factory Security Level Access Code
+ *  0b00..Factory access granted
+ *  0b01..Factory access denied
+ *  0b10..Factory access denied
+ *  0b11..Factory access granted
+ */
+#define FTFE_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)
+#define FTFE_FSEC_MEEN_MASK                      (0x30U)
+#define FTFE_FSEC_MEEN_SHIFT                     (4U)
+/*! MEEN - Mass Erase Enable Bits
+ *  0b00..Mass erase is enabled
+ *  0b01..Mass erase is enabled
+ *  0b10..Mass erase is disabled
+ *  0b11..Mass erase is enabled
+ */
+#define FTFE_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)
+#define FTFE_FSEC_KEYEN_MASK                     (0xC0U)
+#define FTFE_FSEC_KEYEN_SHIFT                    (6U)
+/*! KEYEN - Backdoor Key Security Enable
+ *  0b00..Backdoor key access disabled
+ *  0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
+ *  0b10..Backdoor key access enabled
+ *  0b11..Backdoor key access disabled
+ */
+#define FTFE_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)
+/*! @} */
+
+/*! @name FCCOB3 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB3_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB3_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB2 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB2_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB2_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB1 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB1_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB1_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB0 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB0_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB0_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB7 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB7_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB7_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB6 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB6_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB6_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB5 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB5_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB5_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB4 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB4_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB4_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOBB - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOBB_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOBB_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOBA - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOBA_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOBA_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB9 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB9_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB9_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB8 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB8_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB8_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK)
+/*! @} */
+
+/*! @name FOPT3 - Flash Option Registers */
+/*! @{ */
+#define FTFE_FOPT3_OPT_MASK                      (0xFFU)
+#define FTFE_FOPT3_OPT_SHIFT                     (0U)
+#define FTFE_FOPT3_OPT(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT3_OPT_SHIFT)) & FTFE_FOPT3_OPT_MASK)
+/*! @} */
+
+/*! @name FOPT2 - Flash Option Registers */
+/*! @{ */
+#define FTFE_FOPT2_OPT_MASK                      (0xFFU)
+#define FTFE_FOPT2_OPT_SHIFT                     (0U)
+#define FTFE_FOPT2_OPT(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT2_OPT_SHIFT)) & FTFE_FOPT2_OPT_MASK)
+/*! @} */
+
+/*! @name FOPT1 - Flash Option Registers */
+/*! @{ */
+#define FTFE_FOPT1_OPT_MASK                      (0xFFU)
+#define FTFE_FOPT1_OPT_SHIFT                     (0U)
+#define FTFE_FOPT1_OPT(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT1_OPT_SHIFT)) & FTFE_FOPT1_OPT_MASK)
+/*! @} */
+
+/*! @name FOPT0 - Flash Option Registers */
+/*! @{ */
+#define FTFE_FOPT0_OPT_MASK                      (0xFFU)
+#define FTFE_FOPT0_OPT_SHIFT                     (0U)
+#define FTFE_FOPT0_OPT(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT0_OPT_SHIFT)) & FTFE_FOPT0_OPT_MASK)
+/*! @} */
+
+/*! @name FPROTH3 - Primary Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROTH3_PROT_MASK                   (0xFFU)
+#define FTFE_FPROTH3_PROT_SHIFT                  (0U)
+#define FTFE_FPROTH3_PROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTH3_PROT_SHIFT)) & FTFE_FPROTH3_PROT_MASK)
+/*! @} */
+
+/*! @name FPROTH2 - Primary Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROTH2_PROT_MASK                   (0xFFU)
+#define FTFE_FPROTH2_PROT_SHIFT                  (0U)
+#define FTFE_FPROTH2_PROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTH2_PROT_SHIFT)) & FTFE_FPROTH2_PROT_MASK)
+/*! @} */
+
+/*! @name FPROTH1 - Primary Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROTH1_PROT_MASK                   (0xFFU)
+#define FTFE_FPROTH1_PROT_SHIFT                  (0U)
+#define FTFE_FPROTH1_PROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTH1_PROT_SHIFT)) & FTFE_FPROTH1_PROT_MASK)
+/*! @} */
+
+/*! @name FPROTH0 - Primary Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROTH0_PROT_MASK                   (0xFFU)
+#define FTFE_FPROTH0_PROT_SHIFT                  (0U)
+#define FTFE_FPROTH0_PROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTH0_PROT_SHIFT)) & FTFE_FPROTH0_PROT_MASK)
+/*! @} */
+
+/*! @name FPROTL3 - Primary Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROTL3_PROT_MASK                   (0xFFU)
+#define FTFE_FPROTL3_PROT_SHIFT                  (0U)
+#define FTFE_FPROTL3_PROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTL3_PROT_SHIFT)) & FTFE_FPROTL3_PROT_MASK)
+/*! @} */
+
+/*! @name FPROTL2 - Primary Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROTL2_PROT_MASK                   (0xFFU)
+#define FTFE_FPROTL2_PROT_SHIFT                  (0U)
+#define FTFE_FPROTL2_PROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTL2_PROT_SHIFT)) & FTFE_FPROTL2_PROT_MASK)
+/*! @} */
+
+/*! @name FPROTL1 - Primary Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROTL1_PROT_MASK                   (0xFFU)
+#define FTFE_FPROTL1_PROT_SHIFT                  (0U)
+#define FTFE_FPROTL1_PROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTL1_PROT_SHIFT)) & FTFE_FPROTL1_PROT_MASK)
+/*! @} */
+
+/*! @name FPROTL0 - Primary Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROTL0_PROT_MASK                   (0xFFU)
+#define FTFE_FPROTL0_PROT_SHIFT                  (0U)
+#define FTFE_FPROTL0_PROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTL0_PROT_SHIFT)) & FTFE_FPROTL0_PROT_MASK)
+/*! @} */
+
+/*! @name FPROTSL - Secondary Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROTSL_PROTS_MASK                  (0xFFU)
+#define FTFE_FPROTSL_PROTS_SHIFT                 (0U)
+#define FTFE_FPROTSL_PROTS(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTSL_PROTS_SHIFT)) & FTFE_FPROTSL_PROTS_MASK)
+/*! @} */
+
+/*! @name FPROTSH - Secondary Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROTSH_PROTS_MASK                  (0xFFU)
+#define FTFE_FPROTSH_PROTS_SHIFT                 (0U)
+#define FTFE_FPROTSH_PROTS(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTSH_PROTS_SHIFT)) & FTFE_FPROTSH_PROTS_MASK)
+/*! @} */
+
+/*! @name FACSS - Primary Flash Access Segment Size Register */
+/*! @{ */
+#define FTFE_FACSS_SGSIZE_MASK                   (0xFFU)
+#define FTFE_FACSS_SGSIZE_SHIFT                  (0U)
+#define FTFE_FACSS_SGSIZE(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FACSS_SGSIZE_SHIFT)) & FTFE_FACSS_SGSIZE_MASK)
+/*! @} */
+
+/*! @name FACSN - Primary Flash Access Segment Number Register */
+/*! @{ */
+#define FTFE_FACSN_NUMSG_MASK                    (0xFFU)
+#define FTFE_FACSN_NUMSG_SHIFT                   (0U)
+/*! NUMSG - Number of Segments Indicator
+ *  0b00110000..Primary Program flash memory is divided into 48 segments (768 Kbytes, 1.5 Mbytes)
+ *  0b01000000..Primary Program flash memory is divided into 64 segments (512 Kbytes, 1 Mbyte, 2 Mbytes)
+ */
+#define FTFE_FACSN_NUMSG(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FACSN_NUMSG_SHIFT)) & FTFE_FACSN_NUMSG_MASK)
+/*! @} */
+
+/*! @name FACSSS - Secondary Flash Access Segment Size Register */
+/*! @{ */
+#define FTFE_FACSSS_SGSIZE_S_MASK                (0xFFU)
+#define FTFE_FACSSS_SGSIZE_S_SHIFT               (0U)
+#define FTFE_FACSSS_SGSIZE_S(x)                  (((uint8_t)(((uint8_t)(x)) << FTFE_FACSSS_SGSIZE_S_SHIFT)) & FTFE_FACSSS_SGSIZE_S_MASK)
+/*! @} */
+
+/*! @name FACSNS - Secondary Flash Access Segment Number Register */
+/*! @{ */
+#define FTFE_FACSNS_NUMSG_S_MASK                 (0xFFU)
+#define FTFE_FACSNS_NUMSG_S_SHIFT                (0U)
+/*! NUMSG_S - Number of Segments Indicator
+ *  0b00010000..Secondary Program flash memory is divided into 16 segments
+ */
+#define FTFE_FACSNS_NUMSG_S(x)                   (((uint8_t)(((uint8_t)(x)) << FTFE_FACSNS_NUMSG_S_SHIFT)) & FTFE_FACSNS_NUMSG_S_MASK)
+/*! @} */
+
+/*! @name XACCH3 - Primary Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCH3_XA_MASK                      (0xFFU)
+#define FTFE_XACCH3_XA_SHIFT                     (0U)
+#define FTFE_XACCH3_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH3_XA_SHIFT)) & FTFE_XACCH3_XA_MASK)
+/*! @} */
+
+/*! @name XACCH2 - Primary Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCH2_XA_MASK                      (0xFFU)
+#define FTFE_XACCH2_XA_SHIFT                     (0U)
+#define FTFE_XACCH2_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH2_XA_SHIFT)) & FTFE_XACCH2_XA_MASK)
+/*! @} */
+
+/*! @name XACCH1 - Primary Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCH1_XA_MASK                      (0xFFU)
+#define FTFE_XACCH1_XA_SHIFT                     (0U)
+#define FTFE_XACCH1_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH1_XA_SHIFT)) & FTFE_XACCH1_XA_MASK)
+/*! @} */
+
+/*! @name XACCH0 - Primary Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCH0_XA_MASK                      (0xFFU)
+#define FTFE_XACCH0_XA_SHIFT                     (0U)
+#define FTFE_XACCH0_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH0_XA_SHIFT)) & FTFE_XACCH0_XA_MASK)
+/*! @} */
+
+/*! @name XACCL3 - Primary Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCL3_XA_MASK                      (0xFFU)
+#define FTFE_XACCL3_XA_SHIFT                     (0U)
+#define FTFE_XACCL3_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL3_XA_SHIFT)) & FTFE_XACCL3_XA_MASK)
+/*! @} */
+
+/*! @name XACCL2 - Primary Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCL2_XA_MASK                      (0xFFU)
+#define FTFE_XACCL2_XA_SHIFT                     (0U)
+#define FTFE_XACCL2_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL2_XA_SHIFT)) & FTFE_XACCL2_XA_MASK)
+/*! @} */
+
+/*! @name XACCL1 - Primary Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCL1_XA_MASK                      (0xFFU)
+#define FTFE_XACCL1_XA_SHIFT                     (0U)
+#define FTFE_XACCL1_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL1_XA_SHIFT)) & FTFE_XACCL1_XA_MASK)
+/*! @} */
+
+/*! @name XACCL0 - Primary Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCL0_XA_MASK                      (0xFFU)
+#define FTFE_XACCL0_XA_SHIFT                     (0U)
+#define FTFE_XACCL0_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL0_XA_SHIFT)) & FTFE_XACCL0_XA_MASK)
+/*! @} */
+
+/*! @name SACCH3 - Primary Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCH3_SA_MASK                      (0xFFU)
+#define FTFE_SACCH3_SA_SHIFT                     (0U)
+#define FTFE_SACCH3_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH3_SA_SHIFT)) & FTFE_SACCH3_SA_MASK)
+/*! @} */
+
+/*! @name SACCH2 - Primary Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCH2_SA_MASK                      (0xFFU)
+#define FTFE_SACCH2_SA_SHIFT                     (0U)
+#define FTFE_SACCH2_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH2_SA_SHIFT)) & FTFE_SACCH2_SA_MASK)
+/*! @} */
+
+/*! @name SACCH1 - Primary Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCH1_SA_MASK                      (0xFFU)
+#define FTFE_SACCH1_SA_SHIFT                     (0U)
+#define FTFE_SACCH1_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH1_SA_SHIFT)) & FTFE_SACCH1_SA_MASK)
+/*! @} */
+
+/*! @name SACCH0 - Primary Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCH0_SA_MASK                      (0xFFU)
+#define FTFE_SACCH0_SA_SHIFT                     (0U)
+#define FTFE_SACCH0_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH0_SA_SHIFT)) & FTFE_SACCH0_SA_MASK)
+/*! @} */
+
+/*! @name SACCL3 - Primary Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCL3_SA_MASK                      (0xFFU)
+#define FTFE_SACCL3_SA_SHIFT                     (0U)
+#define FTFE_SACCL3_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL3_SA_SHIFT)) & FTFE_SACCL3_SA_MASK)
+/*! @} */
+
+/*! @name SACCL2 - Primary Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCL2_SA_MASK                      (0xFFU)
+#define FTFE_SACCL2_SA_SHIFT                     (0U)
+#define FTFE_SACCL2_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL2_SA_SHIFT)) & FTFE_SACCL2_SA_MASK)
+/*! @} */
+
+/*! @name SACCL1 - Primary Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCL1_SA_MASK                      (0xFFU)
+#define FTFE_SACCL1_SA_SHIFT                     (0U)
+#define FTFE_SACCL1_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL1_SA_SHIFT)) & FTFE_SACCL1_SA_MASK)
+/*! @} */
+
+/*! @name SACCL0 - Primary Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCL0_SA_MASK                      (0xFFU)
+#define FTFE_SACCL0_SA_SHIFT                     (0U)
+#define FTFE_SACCL0_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL0_SA_SHIFT)) & FTFE_SACCL0_SA_MASK)
+/*! @} */
+
+/*! @name XACCSL - Secondary Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCSL_XA_S_MASK                    (0xFFU)
+#define FTFE_XACCSL_XA_S_SHIFT                   (0U)
+#define FTFE_XACCSL_XA_S(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_XACCSL_XA_S_SHIFT)) & FTFE_XACCSL_XA_S_MASK)
+/*! @} */
+
+/*! @name XACCSH - Secondary Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCSH_XA_S_MASK                    (0xFFU)
+#define FTFE_XACCSH_XA_S_SHIFT                   (0U)
+#define FTFE_XACCSH_XA_S(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_XACCSH_XA_S_SHIFT)) & FTFE_XACCSH_XA_S_MASK)
+/*! @} */
+
+/*! @name SACCSL - Secondary Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCSL_SA_S_MASK                    (0xFFU)
+#define FTFE_SACCSL_SA_S_SHIFT                   (0U)
+#define FTFE_SACCSL_SA_S(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_SACCSL_SA_S_SHIFT)) & FTFE_SACCSL_SA_S_MASK)
+/*! @} */
+
+/*! @name SACCSH - Secondary Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCSH_SA_S_MASK                    (0xFFU)
+#define FTFE_SACCSH_SA_S_SHIFT                   (0U)
+#define FTFE_SACCSH_SA_S(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_SACCSH_SA_S_SHIFT)) & FTFE_SACCSH_SA_S_MASK)
+/*! @} */
+
+/*! @name FSTDBYCTL - Flash Standby Control Register */
+/*! @{ */
+#define FTFE_FSTDBYCTL_STDBYDIS_MASK             (0x1U)
+#define FTFE_FSTDBYCTL_STDBYDIS_SHIFT            (0U)
+/*! STDBYDIS - Standy Mode Disable
+ *  0b0..Standby mode enabled for flash blocks selected by STDBYx
+ *  0b1..Standby mode disabled (STDBYx ignored)
+ */
+#define FTFE_FSTDBYCTL_STDBYDIS(x)               (((uint8_t)(((uint8_t)(x)) << FTFE_FSTDBYCTL_STDBYDIS_SHIFT)) & FTFE_FSTDBYCTL_STDBYDIS_MASK)
+/*! @} */
+
+/*! @name FSTDBY - Flash Standby Register */
+/*! @{ */
+#define FTFE_FSTDBY_STDBY0_MASK                  (0x1U)
+#define FTFE_FSTDBY_STDBY0_SHIFT                 (0U)
+/*! STDBY0 - Standy Mode for Flash Block 0
+ *  0b0..Standby mode not enabled for flash block 0
+ *  0b1..If STDBYDIS is clear, standby mode is enabled for flash block 0 (when SWAP=0/1, flash block 1/0 is the inactive block)
+ */
+#define FTFE_FSTDBY_STDBY0(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_FSTDBY_STDBY0_SHIFT)) & FTFE_FSTDBY_STDBY0_MASK)
+#define FTFE_FSTDBY_STDBY1_MASK                  (0x2U)
+#define FTFE_FSTDBY_STDBY1_SHIFT                 (1U)
+/*! STDBY1 - Standy Mode for Flash Block 1
+ *  0b0..Standby mode not enabled for flash block 1
+ *  0b1..If STDBYDIS is clear, standby mode is enabled for flash block 1 (when SWAP=0/1, flash block 1/0 is the inactive block)
+ */
+#define FTFE_FSTDBY_STDBY1(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_FSTDBY_STDBY1_SHIFT)) & FTFE_FSTDBY_STDBY1_MASK)
+#define FTFE_FSTDBY_STDBY2_MASK                  (0x4U)
+#define FTFE_FSTDBY_STDBY2_SHIFT                 (2U)
+/*! STDBY2 - Standy Mode for Flash Block 2
+ *  0b0..Standby mode not enabled for flash block 2
+ *  0b1..If STDBYDIS is clear, standby mode is enabled for flash block 2
+ */
+#define FTFE_FSTDBY_STDBY2(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_FSTDBY_STDBY2_SHIFT)) & FTFE_FSTDBY_STDBY2_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Masks */
+
+
+/* FTFE - Peripheral instance base addresses */
+/** Peripheral FTFE base address */
+#define FTFE_BASE                                (0x40023000u)
+/** Peripheral FTFE base pointer */
+#define FTFE                                     ((FTFE_Type *)FTFE_BASE)
+/** Array initializer of FTFE peripheral base addresses */
+#define FTFE_BASE_ADDRS                          { FTFE_BASE }
+/** Array initializer of FTFE peripheral base pointers */
+#define FTFE_BASE_PTRS                           { FTFE }
+/** Interrupt vectors for the FTFE peripheral type */
+#define FTFE_COMMAND_COMPLETE_IRQS               { FTFE_Command_Complete_IRQn }
+#define FTFE_READ_COLLISION_IRQS                 { FTFE_Read_Collision_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FTFE_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/*! @name PDOR - Port Data Output Register */
+/*! @{ */
+#define GPIO_PDOR_PDO_MASK                       (0xFFFFFFFFU)
+#define GPIO_PDOR_PDO_SHIFT                      (0U)
+#define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
+/*! @} */
+
+/*! @name PSOR - Port Set Output Register */
+/*! @{ */
+#define GPIO_PSOR_PTSO_MASK                      (0xFFFFFFFFU)
+#define GPIO_PSOR_PTSO_SHIFT                     (0U)
+#define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
+/*! @} */
+
+/*! @name PCOR - Port Clear Output Register */
+/*! @{ */
+#define GPIO_PCOR_PTCO_MASK                      (0xFFFFFFFFU)
+#define GPIO_PCOR_PTCO_SHIFT                     (0U)
+#define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
+/*! @} */
+
+/*! @name PTOR - Port Toggle Output Register */
+/*! @{ */
+#define GPIO_PTOR_PTTO_MASK                      (0xFFFFFFFFU)
+#define GPIO_PTOR_PTTO_SHIFT                     (0U)
+#define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
+/*! @} */
+
+/*! @name PDIR - Port Data Input Register */
+/*! @{ */
+#define GPIO_PDIR_PDI_MASK                       (0xFFFFFFFFU)
+#define GPIO_PDIR_PDI_SHIFT                      (0U)
+#define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
+/*! @} */
+
+/*! @name PDDR - Port Data Direction Register */
+/*! @{ */
+#define GPIO_PDDR_PDD_MASK                       (0xFFFFFFFFU)
+#define GPIO_PDDR_PDD_SHIFT                      (0U)
+#define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIOA base address */
+#define GPIOA_BASE                               (0x48020000u)
+/** Peripheral GPIOA base pointer */
+#define GPIOA                                    ((GPIO_Type *)GPIOA_BASE)
+/** Peripheral GPIOB base address */
+#define GPIOB_BASE                               (0x48020040u)
+/** Peripheral GPIOB base pointer */
+#define GPIOB                                    ((GPIO_Type *)GPIOB_BASE)
+/** Peripheral GPIOC base address */
+#define GPIOC_BASE                               (0x48020080u)
+/** Peripheral GPIOC base pointer */
+#define GPIOC                                    ((GPIO_Type *)GPIOC_BASE)
+/** Peripheral GPIOD base address */
+#define GPIOD_BASE                               (0x480200C0u)
+/** Peripheral GPIOD base pointer */
+#define GPIOD                                    ((GPIO_Type *)GPIOD_BASE)
+/** Peripheral GPIOE base address */
+#define GPIOE_BASE                               (0x4100F000u)
+/** Peripheral GPIOE base pointer */
+#define GPIOE                                    ((GPIO_Type *)GPIOE_BASE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS                          { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS                           { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __IO uint32_t TCSR;                              /**< SAI Transmit Control Register, offset: 0x8 */
+  __IO uint32_t TCR1;                              /**< SAI Transmit Configuration 1 Register, offset: 0xC */
+  __IO uint32_t TCR2;                              /**< SAI Transmit Configuration 2 Register, offset: 0x10 */
+  __IO uint32_t TCR3;                              /**< SAI Transmit Configuration 3 Register, offset: 0x14 */
+  __IO uint32_t TCR4;                              /**< SAI Transmit Configuration 4 Register, offset: 0x18 */
+  __IO uint32_t TCR5;                              /**< SAI Transmit Configuration 5 Register, offset: 0x1C */
+  __O  uint32_t TDR[2];                            /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+       uint8_t RESERVED_0[24];
+  __I  uint32_t TFR[2];                            /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
+       uint8_t RESERVED_1[24];
+  __IO uint32_t TMR;                               /**< SAI Transmit Mask Register, offset: 0x60 */
+       uint8_t RESERVED_2[36];
+  __IO uint32_t RCSR;                              /**< SAI Receive Control Register, offset: 0x88 */
+  __IO uint32_t RCR1;                              /**< SAI Receive Configuration 1 Register, offset: 0x8C */
+  __IO uint32_t RCR2;                              /**< SAI Receive Configuration 2 Register, offset: 0x90 */
+  __IO uint32_t RCR3;                              /**< SAI Receive Configuration 3 Register, offset: 0x94 */
+  __IO uint32_t RCR4;                              /**< SAI Receive Configuration 4 Register, offset: 0x98 */
+  __IO uint32_t RCR5;                              /**< SAI Receive Configuration 5 Register, offset: 0x9C */
+  __I  uint32_t RDR[2];                            /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+       uint8_t RESERVED_3[24];
+  __I  uint32_t RFR[2];                            /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
+       uint8_t RESERVED_4[24];
+  __IO uint32_t RMR;                               /**< SAI Receive Mask Register, offset: 0xE0 */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2S Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define I2S_VERID_FEATURE_MASK                   (0xFFFFU)
+#define I2S_VERID_FEATURE_SHIFT                  (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000000000000..Standard feature set.
+ */
+#define I2S_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
+#define I2S_VERID_MINOR_MASK                     (0xFF0000U)
+#define I2S_VERID_MINOR_SHIFT                    (16U)
+#define I2S_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
+#define I2S_VERID_MAJOR_MASK                     (0xFF000000U)
+#define I2S_VERID_MAJOR_SHIFT                    (24U)
+#define I2S_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define I2S_PARAM_DATALINE_MASK                  (0xFU)
+#define I2S_PARAM_DATALINE_SHIFT                 (0U)
+#define I2S_PARAM_DATALINE(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
+#define I2S_PARAM_FIFO_MASK                      (0xF00U)
+#define I2S_PARAM_FIFO_SHIFT                     (8U)
+#define I2S_PARAM_FIFO(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
+#define I2S_PARAM_FRAME_MASK                     (0xF0000U)
+#define I2S_PARAM_FRAME_SHIFT                    (16U)
+#define I2S_PARAM_FRAME(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
+/*! @} */
+
+/*! @name TCSR - SAI Transmit Control Register */
+/*! @{ */
+#define I2S_TCSR_FRDE_MASK                       (0x1U)
+#define I2S_TCSR_FRDE_SHIFT                      (0U)
+/*! FRDE - FIFO Request DMA Enable
+ *  0b0..Disables the DMA request.
+ *  0b1..Enables the DMA request.
+ */
+#define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
+#define I2S_TCSR_FWDE_MASK                       (0x2U)
+#define I2S_TCSR_FWDE_SHIFT                      (1U)
+/*! FWDE - FIFO Warning DMA Enable
+ *  0b0..Disables the DMA request.
+ *  0b1..Enables the DMA request.
+ */
+#define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
+#define I2S_TCSR_FRIE_MASK                       (0x100U)
+#define I2S_TCSR_FRIE_SHIFT                      (8U)
+/*! FRIE - FIFO Request Interrupt Enable
+ *  0b0..Disables the interrupt.
+ *  0b1..Enables the interrupt.
+ */
+#define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
+#define I2S_TCSR_FWIE_MASK                       (0x200U)
+#define I2S_TCSR_FWIE_SHIFT                      (9U)
+/*! FWIE - FIFO Warning Interrupt Enable
+ *  0b0..Disables the interrupt.
+ *  0b1..Enables the interrupt.
+ */
+#define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
+#define I2S_TCSR_FEIE_MASK                       (0x400U)
+#define I2S_TCSR_FEIE_SHIFT                      (10U)
+/*! FEIE - FIFO Error Interrupt Enable
+ *  0b0..Disables the interrupt.
+ *  0b1..Enables the interrupt.
+ */
+#define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
+#define I2S_TCSR_SEIE_MASK                       (0x800U)
+#define I2S_TCSR_SEIE_SHIFT                      (11U)
+/*! SEIE - Sync Error Interrupt Enable
+ *  0b0..Disables interrupt.
+ *  0b1..Enables interrupt.
+ */
+#define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
+#define I2S_TCSR_WSIE_MASK                       (0x1000U)
+#define I2S_TCSR_WSIE_SHIFT                      (12U)
+/*! WSIE - Word Start Interrupt Enable
+ *  0b0..Disables interrupt.
+ *  0b1..Enables interrupt.
+ */
+#define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
+#define I2S_TCSR_FRF_MASK                        (0x10000U)
+#define I2S_TCSR_FRF_SHIFT                       (16U)
+/*! FRF - FIFO Request Flag
+ *  0b0..Transmit FIFO watermark has not been reached.
+ *  0b1..Transmit FIFO watermark has been reached.
+ */
+#define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
+#define I2S_TCSR_FWF_MASK                        (0x20000U)
+#define I2S_TCSR_FWF_SHIFT                       (17U)
+/*! FWF - FIFO Warning Flag
+ *  0b0..No enabled transmit FIFO is empty.
+ *  0b1..Enabled transmit FIFO is empty.
+ */
+#define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
+#define I2S_TCSR_FEF_MASK                        (0x40000U)
+#define I2S_TCSR_FEF_SHIFT                       (18U)
+/*! FEF - FIFO Error Flag
+ *  0b0..Transmit underrun not detected.
+ *  0b1..Transmit underrun detected.
+ */
+#define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
+#define I2S_TCSR_SEF_MASK                        (0x80000U)
+#define I2S_TCSR_SEF_SHIFT                       (19U)
+/*! SEF - Sync Error Flag
+ *  0b0..Sync error not detected.
+ *  0b1..Frame sync error detected.
+ */
+#define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
+#define I2S_TCSR_WSF_MASK                        (0x100000U)
+#define I2S_TCSR_WSF_SHIFT                       (20U)
+/*! WSF - Word Start Flag
+ *  0b0..Start of word not detected.
+ *  0b1..Start of word detected.
+ */
+#define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
+#define I2S_TCSR_SR_MASK                         (0x1000000U)
+#define I2S_TCSR_SR_SHIFT                        (24U)
+/*! SR - Software Reset
+ *  0b0..No effect.
+ *  0b1..Software reset.
+ */
+#define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
+#define I2S_TCSR_FR_MASK                         (0x2000000U)
+#define I2S_TCSR_FR_SHIFT                        (25U)
+/*! FR - FIFO Reset
+ *  0b0..No effect.
+ *  0b1..FIFO reset.
+ */
+#define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
+#define I2S_TCSR_BCE_MASK                        (0x10000000U)
+#define I2S_TCSR_BCE_SHIFT                       (28U)
+/*! BCE - Bit Clock Enable
+ *  0b0..Transmit bit clock is disabled.
+ *  0b1..Transmit bit clock is enabled.
+ */
+#define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
+#define I2S_TCSR_DBGE_MASK                       (0x20000000U)
+#define I2S_TCSR_DBGE_SHIFT                      (29U)
+/*! DBGE - Debug Enable
+ *  0b0..Transmitter is disabled in Debug mode, after completing the current frame.
+ *  0b1..Transmitter is enabled in Debug mode.
+ */
+#define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
+#define I2S_TCSR_STOPE_MASK                      (0x40000000U)
+#define I2S_TCSR_STOPE_SHIFT                     (30U)
+/*! STOPE - Stop Enable
+ *  0b0..Transmitter disabled in Stop mode.
+ *  0b1..Transmitter enabled in Stop mode.
+ */
+#define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
+#define I2S_TCSR_TE_MASK                         (0x80000000U)
+#define I2S_TCSR_TE_SHIFT                        (31U)
+/*! TE - Transmitter Enable
+ *  0b0..Transmitter is disabled.
+ *  0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
+ */
+#define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
+/*! @} */
+
+/*! @name TCR1 - SAI Transmit Configuration 1 Register */
+/*! @{ */
+#define I2S_TCR1_TFW_MASK                        (0x7U)
+#define I2S_TCR1_TFW_SHIFT                       (0U)
+#define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
+/*! @} */
+
+/*! @name TCR2 - SAI Transmit Configuration 2 Register */
+/*! @{ */
+#define I2S_TCR2_DIV_MASK                        (0xFFU)
+#define I2S_TCR2_DIV_SHIFT                       (0U)
+#define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK                        (0x1000000U)
+#define I2S_TCR2_BCD_SHIFT                       (24U)
+/*! BCD - Bit Clock Direction
+ *  0b0..Bit clock is generated externally in Slave mode.
+ *  0b1..Bit clock is generated internally in Master mode.
+ */
+#define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
+#define I2S_TCR2_BCP_MASK                        (0x2000000U)
+#define I2S_TCR2_BCP_SHIFT                       (25U)
+/*! BCP - Bit Clock Polarity
+ *  0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
+ *  0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
+ */
+#define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
+#define I2S_TCR2_MSEL_MASK                       (0xC000000U)
+#define I2S_TCR2_MSEL_SHIFT                      (26U)
+/*! MSEL - MCLK Select
+ *  0b00..Bus Clock selected.
+ *  0b01..Master Clock (MCLK) 1 option selected.
+ *  0b10..Master Clock (MCLK) 2 option selected.
+ *  0b11..Master Clock (MCLK) 3 option selected.
+ */
+#define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK                        (0x10000000U)
+#define I2S_TCR2_BCI_SHIFT                       (28U)
+/*! BCI - Bit Clock Input
+ *  0b0..No effect.
+ *  0b1..Internal logic is clocked as if bit clock was externally generated.
+ */
+#define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
+#define I2S_TCR2_BCS_MASK                        (0x20000000U)
+#define I2S_TCR2_BCS_SHIFT                       (29U)
+/*! BCS - Bit Clock Swap
+ *  0b0..Use the normal bit clock source.
+ *  0b1..Swap the bit clock source.
+ */
+#define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
+#define I2S_TCR2_SYNC_MASK                       (0xC0000000U)
+#define I2S_TCR2_SYNC_SHIFT                      (30U)
+/*! SYNC - Synchronous Mode
+ *  0b00..Asynchronous mode.
+ *  0b01..Synchronous with receiver.
+ *  0b10..Synchronous with another SAI transmitter.
+ *  0b11..Synchronous with another SAI receiver.
+ */
+#define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
+/*! @} */
+
+/*! @name TCR3 - SAI Transmit Configuration 3 Register */
+/*! @{ */
+#define I2S_TCR3_WDFL_MASK                       (0x1FU)
+#define I2S_TCR3_WDFL_SHIFT                      (0U)
+#define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK                        (0x30000U)
+#define I2S_TCR3_TCE_SHIFT                       (16U)
+#define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
+#define I2S_TCR3_CFR_MASK                        (0x3000000U)
+#define I2S_TCR3_CFR_SHIFT                       (24U)
+#define I2S_TCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
+/*! @} */
+
+/*! @name TCR4 - SAI Transmit Configuration 4 Register */
+/*! @{ */
+#define I2S_TCR4_FSD_MASK                        (0x1U)
+#define I2S_TCR4_FSD_SHIFT                       (0U)
+/*! FSD - Frame Sync Direction
+ *  0b0..Frame sync is generated externally in Slave mode.
+ *  0b1..Frame sync is generated internally in Master mode.
+ */
+#define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
+#define I2S_TCR4_FSP_MASK                        (0x2U)
+#define I2S_TCR4_FSP_SHIFT                       (1U)
+/*! FSP - Frame Sync Polarity
+ *  0b0..Frame sync is active high.
+ *  0b1..Frame sync is active low.
+ */
+#define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
+#define I2S_TCR4_ONDEM_MASK                      (0x4U)
+#define I2S_TCR4_ONDEM_SHIFT                     (2U)
+/*! ONDEM - On Demand Mode
+ *  0b0..Internal frame sync is generated continuously.
+ *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
+ */
+#define I2S_TCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
+#define I2S_TCR4_FSE_MASK                        (0x8U)
+#define I2S_TCR4_FSE_SHIFT                       (3U)
+/*! FSE - Frame Sync Early
+ *  0b0..Frame sync asserts with the first bit of the frame.
+ *  0b1..Frame sync asserts one bit before the first bit of the frame.
+ */
+#define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
+#define I2S_TCR4_MF_MASK                         (0x10U)
+#define I2S_TCR4_MF_SHIFT                        (4U)
+/*! MF - MSB First
+ *  0b0..LSB is transmitted first.
+ *  0b1..MSB is transmitted first.
+ */
+#define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
+#define I2S_TCR4_CHMOD_MASK                      (0x20U)
+#define I2S_TCR4_CHMOD_SHIFT                     (5U)
+/*! CHMOD - Channel Mode
+ *  0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled.
+ *  0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled.
+ */
+#define I2S_TCR4_CHMOD(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
+#define I2S_TCR4_SYWD_MASK                       (0x1F00U)
+#define I2S_TCR4_SYWD_SHIFT                      (8U)
+#define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK                       (0x1F0000U)
+#define I2S_TCR4_FRSZ_SHIFT                      (16U)
+#define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
+#define I2S_TCR4_FPACK_MASK                      (0x3000000U)
+#define I2S_TCR4_FPACK_SHIFT                     (24U)
+/*! FPACK - FIFO Packing Mode
+ *  0b00..FIFO packing is disabled
+ *  0b01..Reserved
+ *  0b10..8-bit FIFO packing is enabled
+ *  0b11..16-bit FIFO packing is enabled
+ */
+#define I2S_TCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
+#define I2S_TCR4_FCOMB_MASK                      (0xC000000U)
+#define I2S_TCR4_FCOMB_SHIFT                     (26U)
+/*! FCOMB - FIFO Combine Mode
+ *  0b00..FIFO combine mode disabled.
+ *  0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers).
+ *  0b10..FIFO combine mode enabled on FIFO writes (by software).
+ *  0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
+ */
+#define I2S_TCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
+#define I2S_TCR4_FCONT_MASK                      (0x10000000U)
+#define I2S_TCR4_FCONT_SHIFT                     (28U)
+/*! FCONT - FIFO Continue on Error
+ *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
+ *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
+ */
+#define I2S_TCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
+/*! @} */
+
+/*! @name TCR5 - SAI Transmit Configuration 5 Register */
+/*! @{ */
+#define I2S_TCR5_FBT_MASK                        (0x1F00U)
+#define I2S_TCR5_FBT_SHIFT                       (8U)
+#define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK                        (0x1F0000U)
+#define I2S_TCR5_W0W_SHIFT                       (16U)
+#define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK                        (0x1F000000U)
+#define I2S_TCR5_WNW_SHIFT                       (24U)
+#define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
+/*! @} */
+
+/*! @name TDR - SAI Transmit Data Register */
+/*! @{ */
+#define I2S_TDR_TDR_MASK                         (0xFFFFFFFFU)
+#define I2S_TDR_TDR_SHIFT                        (0U)
+#define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
+/*! @} */
+
+/* The count of I2S_TDR */
+#define I2S_TDR_COUNT                            (2U)
+
+/*! @name TFR - SAI Transmit FIFO Register */
+/*! @{ */
+#define I2S_TFR_RFP_MASK                         (0xFU)
+#define I2S_TFR_RFP_SHIFT                        (0U)
+#define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK                         (0xF0000U)
+#define I2S_TFR_WFP_SHIFT                        (16U)
+#define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
+#define I2S_TFR_WCP_MASK                         (0x80000000U)
+#define I2S_TFR_WCP_SHIFT                        (31U)
+/*! WCP - Write Channel Pointer
+ *  0b0..No effect.
+ *  0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
+ */
+#define I2S_TFR_WCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
+/*! @} */
+
+/* The count of I2S_TFR */
+#define I2S_TFR_COUNT                            (2U)
+
+/*! @name TMR - SAI Transmit Mask Register */
+/*! @{ */
+#define I2S_TMR_TWM_MASK                         (0xFFFFFFFFU)
+#define I2S_TMR_TWM_SHIFT                        (0U)
+/*! TWM - Transmit Word Mask
+ *  0b00000000000000000000000000000000..Word N is enabled.
+ *  0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked.
+ */
+#define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
+/*! @} */
+
+/*! @name RCSR - SAI Receive Control Register */
+/*! @{ */
+#define I2S_RCSR_FRDE_MASK                       (0x1U)
+#define I2S_RCSR_FRDE_SHIFT                      (0U)
+/*! FRDE - FIFO Request DMA Enable
+ *  0b0..Disables the DMA request.
+ *  0b1..Enables the DMA request.
+ */
+#define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
+#define I2S_RCSR_FWDE_MASK                       (0x2U)
+#define I2S_RCSR_FWDE_SHIFT                      (1U)
+/*! FWDE - FIFO Warning DMA Enable
+ *  0b0..Disables the DMA request.
+ *  0b1..Enables the DMA request.
+ */
+#define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
+#define I2S_RCSR_FRIE_MASK                       (0x100U)
+#define I2S_RCSR_FRIE_SHIFT                      (8U)
+/*! FRIE - FIFO Request Interrupt Enable
+ *  0b0..Disables the interrupt.
+ *  0b1..Enables the interrupt.
+ */
+#define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
+#define I2S_RCSR_FWIE_MASK                       (0x200U)
+#define I2S_RCSR_FWIE_SHIFT                      (9U)
+/*! FWIE - FIFO Warning Interrupt Enable
+ *  0b0..Disables the interrupt.
+ *  0b1..Enables the interrupt.
+ */
+#define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
+#define I2S_RCSR_FEIE_MASK                       (0x400U)
+#define I2S_RCSR_FEIE_SHIFT                      (10U)
+/*! FEIE - FIFO Error Interrupt Enable
+ *  0b0..Disables the interrupt.
+ *  0b1..Enables the interrupt.
+ */
+#define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
+#define I2S_RCSR_SEIE_MASK                       (0x800U)
+#define I2S_RCSR_SEIE_SHIFT                      (11U)
+/*! SEIE - Sync Error Interrupt Enable
+ *  0b0..Disables interrupt.
+ *  0b1..Enables interrupt.
+ */
+#define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
+#define I2S_RCSR_WSIE_MASK                       (0x1000U)
+#define I2S_RCSR_WSIE_SHIFT                      (12U)
+/*! WSIE - Word Start Interrupt Enable
+ *  0b0..Disables interrupt.
+ *  0b1..Enables interrupt.
+ */
+#define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
+#define I2S_RCSR_FRF_MASK                        (0x10000U)
+#define I2S_RCSR_FRF_SHIFT                       (16U)
+/*! FRF - FIFO Request Flag
+ *  0b0..Receive FIFO watermark not reached.
+ *  0b1..Receive FIFO watermark has been reached.
+ */
+#define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
+#define I2S_RCSR_FWF_MASK                        (0x20000U)
+#define I2S_RCSR_FWF_SHIFT                       (17U)
+/*! FWF - FIFO Warning Flag
+ *  0b0..No enabled receive FIFO is full.
+ *  0b1..Enabled receive FIFO is full.
+ */
+#define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
+#define I2S_RCSR_FEF_MASK                        (0x40000U)
+#define I2S_RCSR_FEF_SHIFT                       (18U)
+/*! FEF - FIFO Error Flag
+ *  0b0..Receive overflow not detected.
+ *  0b1..Receive overflow detected.
+ */
+#define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
+#define I2S_RCSR_SEF_MASK                        (0x80000U)
+#define I2S_RCSR_SEF_SHIFT                       (19U)
+/*! SEF - Sync Error Flag
+ *  0b0..Sync error not detected.
+ *  0b1..Frame sync error detected.
+ */
+#define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
+#define I2S_RCSR_WSF_MASK                        (0x100000U)
+#define I2S_RCSR_WSF_SHIFT                       (20U)
+/*! WSF - Word Start Flag
+ *  0b0..Start of word not detected.
+ *  0b1..Start of word detected.
+ */
+#define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
+#define I2S_RCSR_SR_MASK                         (0x1000000U)
+#define I2S_RCSR_SR_SHIFT                        (24U)
+/*! SR - Software Reset
+ *  0b0..No effect.
+ *  0b1..Software reset.
+ */
+#define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
+#define I2S_RCSR_FR_MASK                         (0x2000000U)
+#define I2S_RCSR_FR_SHIFT                        (25U)
+/*! FR - FIFO Reset
+ *  0b0..No effect.
+ *  0b1..FIFO reset.
+ */
+#define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
+#define I2S_RCSR_BCE_MASK                        (0x10000000U)
+#define I2S_RCSR_BCE_SHIFT                       (28U)
+/*! BCE - Bit Clock Enable
+ *  0b0..Receive bit clock is disabled.
+ *  0b1..Receive bit clock is enabled.
+ */
+#define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
+#define I2S_RCSR_DBGE_MASK                       (0x20000000U)
+#define I2S_RCSR_DBGE_SHIFT                      (29U)
+/*! DBGE - Debug Enable
+ *  0b0..Receiver is disabled in Debug mode, after completing the current frame.
+ *  0b1..Receiver is enabled in Debug mode.
+ */
+#define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
+#define I2S_RCSR_STOPE_MASK                      (0x40000000U)
+#define I2S_RCSR_STOPE_SHIFT                     (30U)
+/*! STOPE - Stop Enable
+ *  0b0..Receiver disabled in Stop mode.
+ *  0b1..Receiver enabled in Stop mode.
+ */
+#define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
+#define I2S_RCSR_RE_MASK                         (0x80000000U)
+#define I2S_RCSR_RE_SHIFT                        (31U)
+/*! RE - Receiver Enable
+ *  0b0..Receiver is disabled.
+ *  0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
+ */
+#define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
+/*! @} */
+
+/*! @name RCR1 - SAI Receive Configuration 1 Register */
+/*! @{ */
+#define I2S_RCR1_RFW_MASK                        (0x7U)
+#define I2S_RCR1_RFW_SHIFT                       (0U)
+#define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
+/*! @} */
+
+/*! @name RCR2 - SAI Receive Configuration 2 Register */
+/*! @{ */
+#define I2S_RCR2_DIV_MASK                        (0xFFU)
+#define I2S_RCR2_DIV_SHIFT                       (0U)
+#define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK                        (0x1000000U)
+#define I2S_RCR2_BCD_SHIFT                       (24U)
+/*! BCD - Bit Clock Direction
+ *  0b0..Bit clock is generated externally in Slave mode.
+ *  0b1..Bit clock is generated internally in Master mode.
+ */
+#define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
+#define I2S_RCR2_BCP_MASK                        (0x2000000U)
+#define I2S_RCR2_BCP_SHIFT                       (25U)
+/*! BCP - Bit Clock Polarity
+ *  0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
+ *  0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
+ */
+#define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
+#define I2S_RCR2_MSEL_MASK                       (0xC000000U)
+#define I2S_RCR2_MSEL_SHIFT                      (26U)
+/*! MSEL - MCLK Select
+ *  0b00..Bus Clock selected.
+ *  0b01..Master Clock (MCLK) 1 option selected.
+ *  0b10..Master Clock (MCLK) 2 option selected.
+ *  0b11..Master Clock (MCLK) 3 option selected.
+ */
+#define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK                        (0x10000000U)
+#define I2S_RCR2_BCI_SHIFT                       (28U)
+/*! BCI - Bit Clock Input
+ *  0b0..No effect.
+ *  0b1..Internal logic is clocked as if bit clock was externally generated.
+ */
+#define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
+#define I2S_RCR2_BCS_MASK                        (0x20000000U)
+#define I2S_RCR2_BCS_SHIFT                       (29U)
+/*! BCS - Bit Clock Swap
+ *  0b0..Use the normal bit clock source.
+ *  0b1..Swap the bit clock source.
+ */
+#define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
+#define I2S_RCR2_SYNC_MASK                       (0xC0000000U)
+#define I2S_RCR2_SYNC_SHIFT                      (30U)
+/*! SYNC - Synchronous Mode
+ *  0b00..Asynchronous mode.
+ *  0b01..Synchronous with transmitter.
+ *  0b10..Synchronous with another SAI receiver.
+ *  0b11..Synchronous with another SAI transmitter.
+ */
+#define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
+/*! @} */
+
+/*! @name RCR3 - SAI Receive Configuration 3 Register */
+/*! @{ */
+#define I2S_RCR3_WDFL_MASK                       (0x1FU)
+#define I2S_RCR3_WDFL_SHIFT                      (0U)
+#define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK                        (0x30000U)
+#define I2S_RCR3_RCE_SHIFT                       (16U)
+#define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
+#define I2S_RCR3_CFR_MASK                        (0x3000000U)
+#define I2S_RCR3_CFR_SHIFT                       (24U)
+#define I2S_RCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
+/*! @} */
+
+/*! @name RCR4 - SAI Receive Configuration 4 Register */
+/*! @{ */
+#define I2S_RCR4_FSD_MASK                        (0x1U)
+#define I2S_RCR4_FSD_SHIFT                       (0U)
+/*! FSD - Frame Sync Direction
+ *  0b0..Frame Sync is generated externally in Slave mode.
+ *  0b1..Frame Sync is generated internally in Master mode.
+ */
+#define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
+#define I2S_RCR4_FSP_MASK                        (0x2U)
+#define I2S_RCR4_FSP_SHIFT                       (1U)
+/*! FSP - Frame Sync Polarity
+ *  0b0..Frame sync is active high.
+ *  0b1..Frame sync is active low.
+ */
+#define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
+#define I2S_RCR4_ONDEM_MASK                      (0x4U)
+#define I2S_RCR4_ONDEM_SHIFT                     (2U)
+/*! ONDEM - On Demand Mode
+ *  0b0..Internal frame sync is generated continuously.
+ *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
+ */
+#define I2S_RCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
+#define I2S_RCR4_FSE_MASK                        (0x8U)
+#define I2S_RCR4_FSE_SHIFT                       (3U)
+/*! FSE - Frame Sync Early
+ *  0b0..Frame sync asserts with the first bit of the frame.
+ *  0b1..Frame sync asserts one bit before the first bit of the frame.
+ */
+#define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
+#define I2S_RCR4_MF_MASK                         (0x10U)
+#define I2S_RCR4_MF_SHIFT                        (4U)
+/*! MF - MSB First
+ *  0b0..LSB is received first.
+ *  0b1..MSB is received first.
+ */
+#define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
+#define I2S_RCR4_SYWD_MASK                       (0x1F00U)
+#define I2S_RCR4_SYWD_SHIFT                      (8U)
+#define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK                       (0x1F0000U)
+#define I2S_RCR4_FRSZ_SHIFT                      (16U)
+#define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
+#define I2S_RCR4_FPACK_MASK                      (0x3000000U)
+#define I2S_RCR4_FPACK_SHIFT                     (24U)
+/*! FPACK - FIFO Packing Mode
+ *  0b00..FIFO packing is disabled
+ *  0b01..Reserved.
+ *  0b10..8-bit FIFO packing is enabled
+ *  0b11..16-bit FIFO packing is enabled
+ */
+#define I2S_RCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
+#define I2S_RCR4_FCOMB_MASK                      (0xC000000U)
+#define I2S_RCR4_FCOMB_SHIFT                     (26U)
+/*! FCOMB - FIFO Combine Mode
+ *  0b00..FIFO combine mode disabled.
+ *  0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers).
+ *  0b10..FIFO combine mode enabled on FIFO reads (by software).
+ *  0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
+ */
+#define I2S_RCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
+#define I2S_RCR4_FCONT_MASK                      (0x10000000U)
+#define I2S_RCR4_FCONT_SHIFT                     (28U)
+/*! FCONT - FIFO Continue on Error
+ *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
+ *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
+ */
+#define I2S_RCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
+/*! @} */
+
+/*! @name RCR5 - SAI Receive Configuration 5 Register */
+/*! @{ */
+#define I2S_RCR5_FBT_MASK                        (0x1F00U)
+#define I2S_RCR5_FBT_SHIFT                       (8U)
+#define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK                        (0x1F0000U)
+#define I2S_RCR5_W0W_SHIFT                       (16U)
+#define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK                        (0x1F000000U)
+#define I2S_RCR5_WNW_SHIFT                       (24U)
+#define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
+/*! @} */
+
+/*! @name RDR - SAI Receive Data Register */
+/*! @{ */
+#define I2S_RDR_RDR_MASK                         (0xFFFFFFFFU)
+#define I2S_RDR_RDR_SHIFT                        (0U)
+#define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
+/*! @} */
+
+/* The count of I2S_RDR */
+#define I2S_RDR_COUNT                            (2U)
+
+/*! @name RFR - SAI Receive FIFO Register */
+/*! @{ */
+#define I2S_RFR_RFP_MASK                         (0xFU)
+#define I2S_RFR_RFP_SHIFT                        (0U)
+#define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
+#define I2S_RFR_RCP_MASK                         (0x8000U)
+#define I2S_RFR_RCP_SHIFT                        (15U)
+/*! RCP - Receive Channel Pointer
+ *  0b0..No effect.
+ *  0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
+ */
+#define I2S_RFR_RCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
+#define I2S_RFR_WFP_MASK                         (0xF0000U)
+#define I2S_RFR_WFP_SHIFT                        (16U)
+#define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
+/*! @} */
+
+/* The count of I2S_RFR */
+#define I2S_RFR_COUNT                            (2U)
+
+/*! @name RMR - SAI Receive Mask Register */
+/*! @{ */
+#define I2S_RMR_RWM_MASK                         (0xFFFFFFFFU)
+#define I2S_RMR_RWM_SHIFT                        (0U)
+/*! RWM - Receive Word Mask
+ *  0b00000000000000000000000000000000..Word N is enabled.
+ *  0b00000000000000000000000000000001..Word N is masked.
+ */
+#define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE                                (0x4003D000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0                                     ((I2S_Type *)I2S0_BASE)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS                           { I2S0_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS                            { I2S0 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_RX_IRQS                              { I2S0_IRQn }
+#define I2S_TX_IRQS                              { I2S0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- INTMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INTMUX_Peripheral_Access_Layer INTMUX Peripheral Access Layer
+ * @{
+ */
+
+/** INTMUX - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x40 */
+    __IO uint32_t CHn_CSR;                           /**< Channel n Control Status Register, array offset: 0x0, array step: 0x40 */
+    __I  uint32_t CHn_VEC;                           /**< Channel n Vector Number Register, array offset: 0x4, array step: 0x40 */
+         uint8_t RESERVED_0[8];
+    __IO uint32_t CHn_IER_31_0;                      /**< Channel n Interrupt Enable Register, array offset: 0x10, array step: 0x40 */
+         uint8_t RESERVED_1[12];
+    __I  uint32_t CHn_IPR_31_0;                      /**< Channel n Interrupt Pending Register, array offset: 0x20, array step: 0x40 */
+         uint8_t RESERVED_2[28];
+  } CHANNEL[8];
+} INTMUX_Type;
+
+/* ----------------------------------------------------------------------------
+   -- INTMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INTMUX_Register_Masks INTMUX Register Masks
+ * @{
+ */
+
+/*! @name CHn_CSR - Channel n Control Status Register */
+/*! @{ */
+#define INTMUX_CHn_CSR_RST_MASK                  (0x1U)
+#define INTMUX_CHn_CSR_RST_SHIFT                 (0U)
+/*! RST - Software Reset
+ *  0b0..No operation.
+ *  0b1..Perform a software reset on this channel.
+ */
+#define INTMUX_CHn_CSR_RST(x)                    (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_RST_SHIFT)) & INTMUX_CHn_CSR_RST_MASK)
+#define INTMUX_CHn_CSR_AND_MASK                  (0x2U)
+#define INTMUX_CHn_CSR_AND_SHIFT                 (1U)
+/*! AND - Logic AND
+ *  0b0..Logic OR all enabled interrupt inputs.
+ *  0b1..Logic AND all enabled interrupt inputs.
+ */
+#define INTMUX_CHn_CSR_AND(x)                    (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_AND_SHIFT)) & INTMUX_CHn_CSR_AND_MASK)
+#define INTMUX_CHn_CSR_IRQN_MASK                 (0x30U)
+#define INTMUX_CHn_CSR_IRQN_SHIFT                (4U)
+/*! IRQN - Channel Input Number
+ *  0b00..32 interrupt inputs
+ *  0b01..Reserved
+ *  0b10..Reserved
+ *  0b11..Reserved
+ */
+#define INTMUX_CHn_CSR_IRQN(x)                   (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQN_SHIFT)) & INTMUX_CHn_CSR_IRQN_MASK)
+#define INTMUX_CHn_CSR_CHIN_MASK                 (0xF00U)
+#define INTMUX_CHn_CSR_CHIN_SHIFT                (8U)
+#define INTMUX_CHn_CSR_CHIN(x)                   (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_CHIN_SHIFT)) & INTMUX_CHn_CSR_CHIN_MASK)
+#define INTMUX_CHn_CSR_IRQP_MASK                 (0x80000000U)
+#define INTMUX_CHn_CSR_IRQP_SHIFT                (31U)
+/*! IRQP - Channel Interrupt Request Pending
+ *  0b0..No interrupt is pending.
+ *  0b1..The interrupt output of this channel is pending.
+ */
+#define INTMUX_CHn_CSR_IRQP(x)                   (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQP_SHIFT)) & INTMUX_CHn_CSR_IRQP_MASK)
+/*! @} */
+
+/* The count of INTMUX_CHn_CSR */
+#define INTMUX_CHn_CSR_COUNT                     (8U)
+
+/*! @name CHn_VEC - Channel n Vector Number Register */
+/*! @{ */
+#define INTMUX_CHn_VEC_VECN_MASK                 (0x3FFCU)
+#define INTMUX_CHn_VEC_VECN_SHIFT                (2U)
+#define INTMUX_CHn_VEC_VECN(x)                   (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_VEC_VECN_SHIFT)) & INTMUX_CHn_VEC_VECN_MASK)
+/*! @} */
+
+/* The count of INTMUX_CHn_VEC */
+#define INTMUX_CHn_VEC_COUNT                     (8U)
+
+/*! @name CHn_IER_31_0 - Channel n Interrupt Enable Register */
+/*! @{ */
+#define INTMUX_CHn_IER_31_0_INTE_MASK            (0xFFFFFFFFU)
+#define INTMUX_CHn_IER_31_0_INTE_SHIFT           (0U)
+#define INTMUX_CHn_IER_31_0_INTE(x)              (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IER_31_0_INTE_SHIFT)) & INTMUX_CHn_IER_31_0_INTE_MASK)
+/*! @} */
+
+/* The count of INTMUX_CHn_IER_31_0 */
+#define INTMUX_CHn_IER_31_0_COUNT                (8U)
+
+/*! @name CHn_IPR_31_0 - Channel n Interrupt Pending Register */
+/*! @{ */
+#define INTMUX_CHn_IPR_31_0_INTP_MASK            (0xFFFFFFFFU)
+#define INTMUX_CHn_IPR_31_0_INTP_SHIFT           (0U)
+#define INTMUX_CHn_IPR_31_0_INTP(x)              (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IPR_31_0_INTP_SHIFT)) & INTMUX_CHn_IPR_31_0_INTP_MASK)
+/*! @} */
+
+/* The count of INTMUX_CHn_IPR_31_0 */
+#define INTMUX_CHn_IPR_31_0_COUNT                (8U)
+
+
+/*!
+ * @}
+ */ /* end of group INTMUX_Register_Masks */
+
+
+/* INTMUX - Peripheral instance base addresses */
+/** Peripheral INTMUX0 base address */
+#define INTMUX0_BASE                             (0x4004F000u)
+/** Peripheral INTMUX0 base pointer */
+#define INTMUX0                                  ((INTMUX_Type *)INTMUX0_BASE)
+/** Array initializer of INTMUX peripheral base addresses */
+#define INTMUX_BASE_ADDRS                        { INTMUX0_BASE }
+/** Array initializer of INTMUX peripheral base pointers */
+#define INTMUX_BASE_PTRS                         { INTMUX0 }
+/** Interrupt vectors for the INTMUX peripheral type */
+#define INTMUX_IRQS                              { { INTMUX0_0_IRQn, INTMUX0_1_IRQn, INTMUX0_2_IRQn, INTMUX0_3_IRQn, INTMUX0_4_IRQn, INTMUX0_5_IRQn, INTMUX0_6_IRQn, INTMUX0_7_IRQn },  }
+
+/*!
+ * @}
+ */ /* end of group INTMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __IO uint32_t PE1;                               /**< Pin Enable 1 register, offset: 0x8 */
+  __IO uint32_t PE2;                               /**< Pin Enable 2 register, offset: 0xC */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t ME;                                /**< Module Interrupt Enable register, offset: 0x18 */
+  __IO uint32_t DE;                                /**< Module DMA/Trigger Enable register, offset: 0x1C */
+  __IO uint32_t PF;                                /**< Pin Flag register, offset: 0x20 */
+       uint8_t RESERVED_1[12];
+  __IO uint32_t FILT;                              /**< Pin Filter register, offset: 0x30 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t PDC1;                              /**< Pin DMA/Trigger Configuration 1 register, offset: 0x38 */
+  __IO uint32_t PDC2;                              /**< Pin DMA/Trigger Configuration 2 register, offset: 0x3C */
+       uint8_t RESERVED_3[8];
+  __IO uint32_t FDC;                               /**< Pin Filter DMA/Trigger Configuration register, offset: 0x48 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t PMC;                               /**< Pin Mode Configuration register, offset: 0x50 */
+       uint8_t RESERVED_5[4];
+  __IO uint32_t FMC;                               /**< Pin Filter Mode Configuration register, offset: 0x58 */
+} LLWU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define LLWU_VERID_FEATURE_MASK                  (0xFFFFU)
+#define LLWU_VERID_FEATURE_SHIFT                 (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000000000000..Standard features implemented
+ *  0b0000000000000001..Support for DMA/Trigger generation from wakeup pins and filters enabled. Support for external pin/filter detection during all power modes enabled.
+ */
+#define LLWU_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_FEATURE_SHIFT)) & LLWU_VERID_FEATURE_MASK)
+#define LLWU_VERID_MINOR_MASK                    (0xFF0000U)
+#define LLWU_VERID_MINOR_SHIFT                   (16U)
+#define LLWU_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_MINOR_SHIFT)) & LLWU_VERID_MINOR_MASK)
+#define LLWU_VERID_MAJOR_MASK                    (0xFF000000U)
+#define LLWU_VERID_MAJOR_SHIFT                   (24U)
+#define LLWU_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_MAJOR_SHIFT)) & LLWU_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define LLWU_PARAM_FILTERS_MASK                  (0xFFU)
+#define LLWU_PARAM_FILTERS_SHIFT                 (0U)
+#define LLWU_PARAM_FILTERS(x)                    (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_FILTERS_SHIFT)) & LLWU_PARAM_FILTERS_MASK)
+#define LLWU_PARAM_DMAS_MASK                     (0xFF00U)
+#define LLWU_PARAM_DMAS_SHIFT                    (8U)
+#define LLWU_PARAM_DMAS(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_DMAS_SHIFT)) & LLWU_PARAM_DMAS_MASK)
+#define LLWU_PARAM_MODULES_MASK                  (0xFF0000U)
+#define LLWU_PARAM_MODULES_SHIFT                 (16U)
+#define LLWU_PARAM_MODULES(x)                    (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_MODULES_SHIFT)) & LLWU_PARAM_MODULES_MASK)
+#define LLWU_PARAM_PINS_MASK                     (0xFF000000U)
+#define LLWU_PARAM_PINS_SHIFT                    (24U)
+#define LLWU_PARAM_PINS(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_PINS_SHIFT)) & LLWU_PARAM_PINS_MASK)
+/*! @} */
+
+/*! @name PE1 - Pin Enable 1 register */
+/*! @{ */
+#define LLWU_PE1_WUPE0_MASK                      (0x3U)
+#define LLWU_PE1_WUPE0_SHIFT                     (0U)
+/*! WUPE0 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE0(x)                        (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK                      (0xCU)
+#define LLWU_PE1_WUPE1_SHIFT                     (2U)
+/*! WUPE1 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE1(x)                        (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK                      (0x30U)
+#define LLWU_PE1_WUPE2_SHIFT                     (4U)
+/*! WUPE2 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE2(x)                        (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK                      (0xC0U)
+#define LLWU_PE1_WUPE3_SHIFT                     (6U)
+/*! WUPE3 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE3(x)                        (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
+#define LLWU_PE1_WUPE4_MASK                      (0x300U)
+#define LLWU_PE1_WUPE4_SHIFT                     (8U)
+/*! WUPE4 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE4(x)                        (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE4_SHIFT)) & LLWU_PE1_WUPE4_MASK)
+#define LLWU_PE1_WUPE5_MASK                      (0xC00U)
+#define LLWU_PE1_WUPE5_SHIFT                     (10U)
+/*! WUPE5 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE5(x)                        (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE5_SHIFT)) & LLWU_PE1_WUPE5_MASK)
+#define LLWU_PE1_WUPE6_MASK                      (0x3000U)
+#define LLWU_PE1_WUPE6_SHIFT                     (12U)
+/*! WUPE6 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE6(x)                        (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE6_SHIFT)) & LLWU_PE1_WUPE6_MASK)
+#define LLWU_PE1_WUPE7_MASK                      (0xC000U)
+#define LLWU_PE1_WUPE7_SHIFT                     (14U)
+/*! WUPE7 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE7(x)                        (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE7_SHIFT)) & LLWU_PE1_WUPE7_MASK)
+#define LLWU_PE1_WUPE8_MASK                      (0x30000U)
+#define LLWU_PE1_WUPE8_SHIFT                     (16U)
+/*! WUPE8 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE8(x)                        (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE8_SHIFT)) & LLWU_PE1_WUPE8_MASK)
+#define LLWU_PE1_WUPE9_MASK                      (0xC0000U)
+#define LLWU_PE1_WUPE9_SHIFT                     (18U)
+/*! WUPE9 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE9(x)                        (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE9_SHIFT)) & LLWU_PE1_WUPE9_MASK)
+#define LLWU_PE1_WUPE10_MASK                     (0x300000U)
+#define LLWU_PE1_WUPE10_SHIFT                    (20U)
+/*! WUPE10 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE10(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE10_SHIFT)) & LLWU_PE1_WUPE10_MASK)
+#define LLWU_PE1_WUPE11_MASK                     (0xC00000U)
+#define LLWU_PE1_WUPE11_SHIFT                    (22U)
+/*! WUPE11 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE11(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE11_SHIFT)) & LLWU_PE1_WUPE11_MASK)
+#define LLWU_PE1_WUPE12_MASK                     (0x3000000U)
+#define LLWU_PE1_WUPE12_SHIFT                    (24U)
+/*! WUPE12 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE12(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE12_SHIFT)) & LLWU_PE1_WUPE12_MASK)
+#define LLWU_PE1_WUPE13_MASK                     (0xC000000U)
+#define LLWU_PE1_WUPE13_SHIFT                    (26U)
+/*! WUPE13 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE13(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE13_SHIFT)) & LLWU_PE1_WUPE13_MASK)
+#define LLWU_PE1_WUPE14_MASK                     (0x30000000U)
+#define LLWU_PE1_WUPE14_SHIFT                    (28U)
+/*! WUPE14 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE14(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE14_SHIFT)) & LLWU_PE1_WUPE14_MASK)
+#define LLWU_PE1_WUPE15_MASK                     (0xC0000000U)
+#define LLWU_PE1_WUPE15_SHIFT                    (30U)
+/*! WUPE15 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE15(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE15_SHIFT)) & LLWU_PE1_WUPE15_MASK)
+/*! @} */
+
+/*! @name PE2 - Pin Enable 2 register */
+/*! @{ */
+#define LLWU_PE2_WUPE16_MASK                     (0x3U)
+#define LLWU_PE2_WUPE16_SHIFT                    (0U)
+/*! WUPE16 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE16(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE16_SHIFT)) & LLWU_PE2_WUPE16_MASK)
+#define LLWU_PE2_WUPE17_MASK                     (0xCU)
+#define LLWU_PE2_WUPE17_SHIFT                    (2U)
+/*! WUPE17 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE17(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE17_SHIFT)) & LLWU_PE2_WUPE17_MASK)
+#define LLWU_PE2_WUPE18_MASK                     (0x30U)
+#define LLWU_PE2_WUPE18_SHIFT                    (4U)
+/*! WUPE18 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE18(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE18_SHIFT)) & LLWU_PE2_WUPE18_MASK)
+#define LLWU_PE2_WUPE19_MASK                     (0xC0U)
+#define LLWU_PE2_WUPE19_SHIFT                    (6U)
+/*! WUPE19 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE19(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE19_SHIFT)) & LLWU_PE2_WUPE19_MASK)
+#define LLWU_PE2_WUPE20_MASK                     (0x300U)
+#define LLWU_PE2_WUPE20_SHIFT                    (8U)
+/*! WUPE20 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE20(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE20_SHIFT)) & LLWU_PE2_WUPE20_MASK)
+#define LLWU_PE2_WUPE21_MASK                     (0xC00U)
+#define LLWU_PE2_WUPE21_SHIFT                    (10U)
+/*! WUPE21 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE21(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE21_SHIFT)) & LLWU_PE2_WUPE21_MASK)
+#define LLWU_PE2_WUPE22_MASK                     (0x3000U)
+#define LLWU_PE2_WUPE22_SHIFT                    (12U)
+/*! WUPE22 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE22(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE22_SHIFT)) & LLWU_PE2_WUPE22_MASK)
+#define LLWU_PE2_WUPE23_MASK                     (0xC000U)
+#define LLWU_PE2_WUPE23_SHIFT                    (14U)
+/*! WUPE23 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE23(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE23_SHIFT)) & LLWU_PE2_WUPE23_MASK)
+#define LLWU_PE2_WUPE24_MASK                     (0x30000U)
+#define LLWU_PE2_WUPE24_SHIFT                    (16U)
+/*! WUPE24 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE24(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE24_SHIFT)) & LLWU_PE2_WUPE24_MASK)
+#define LLWU_PE2_WUPE25_MASK                     (0xC0000U)
+#define LLWU_PE2_WUPE25_SHIFT                    (18U)
+/*! WUPE25 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE25(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE25_SHIFT)) & LLWU_PE2_WUPE25_MASK)
+#define LLWU_PE2_WUPE26_MASK                     (0x300000U)
+#define LLWU_PE2_WUPE26_SHIFT                    (20U)
+/*! WUPE26 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE26(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE26_SHIFT)) & LLWU_PE2_WUPE26_MASK)
+#define LLWU_PE2_Reserved27_MASK                 (0xC00000U)
+#define LLWU_PE2_Reserved27_SHIFT                (22U)
+/*! Reserved27 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_Reserved27(x)                   (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved27_SHIFT)) & LLWU_PE2_Reserved27_MASK)
+#define LLWU_PE2_Reserved28_MASK                 (0x3000000U)
+#define LLWU_PE2_Reserved28_SHIFT                (24U)
+/*! Reserved28 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_Reserved28(x)                   (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved28_SHIFT)) & LLWU_PE2_Reserved28_MASK)
+#define LLWU_PE2_WUPE29_MASK                     (0xC000000U)
+#define LLWU_PE2_WUPE29_SHIFT                    (26U)
+/*! WUPE29 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE29(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE29_SHIFT)) & LLWU_PE2_WUPE29_MASK)
+#define LLWU_PE2_WUPE30_MASK                     (0x30000000U)
+#define LLWU_PE2_WUPE30_SHIFT                    (28U)
+/*! WUPE30 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE30(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE30_SHIFT)) & LLWU_PE2_WUPE30_MASK)
+#define LLWU_PE2_WUPE31_MASK                     (0xC0000000U)
+#define LLWU_PE2_WUPE31_SHIFT                    (30U)
+/*! WUPE31 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE31(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE31_SHIFT)) & LLWU_PE2_WUPE31_MASK)
+/*! @} */
+
+/*! @name ME - Module Interrupt Enable register */
+/*! @{ */
+#define LLWU_ME_WUME0_MASK                       (0x1U)
+#define LLWU_ME_WUME0_SHIFT                      (0U)
+/*! WUME0 - Wakeup module enable for module n
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME0(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
+#define LLWU_ME_WUME1_MASK                       (0x2U)
+#define LLWU_ME_WUME1_SHIFT                      (1U)
+/*! WUME1 - Wakeup module enable for module n
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME1(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
+#define LLWU_ME_WUME2_MASK                       (0x4U)
+#define LLWU_ME_WUME2_SHIFT                      (2U)
+/*! WUME2 - Wakeup module enable for module n
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME2(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
+#define LLWU_ME_Reserved3_MASK                   (0x8U)
+#define LLWU_ME_Reserved3_SHIFT                  (3U)
+/*! Reserved3 - Wakeup module enable for module n
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_Reserved3(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_ME_Reserved3_SHIFT)) & LLWU_ME_Reserved3_MASK)
+#define LLWU_ME_WUME3_MASK                       (0x8U)
+#define LLWU_ME_WUME3_SHIFT                      (3U)
+/*! WUME3 - Wakeup module enable for module n
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME3(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
+#define LLWU_ME_Reserved4_MASK                   (0x10U)
+#define LLWU_ME_Reserved4_SHIFT                  (4U)
+/*! Reserved4 - Wakeup module enable for module n
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_Reserved4(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_ME_Reserved4_SHIFT)) & LLWU_ME_Reserved4_MASK)
+#define LLWU_ME_WUME5_MASK                       (0x20U)
+#define LLWU_ME_WUME5_SHIFT                      (5U)
+/*! WUME5 - Wakeup module enable for module n
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME5(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
+#define LLWU_ME_WUME6_MASK                       (0x40U)
+#define LLWU_ME_WUME6_SHIFT                      (6U)
+/*! WUME6 - Wakeup module enable for module n
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME6(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
+#define LLWU_ME_WUME7_MASK                       (0x80U)
+#define LLWU_ME_WUME7_SHIFT                      (7U)
+/*! WUME7 - Wakeup module enable for module n
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME7(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
+/*! @} */
+
+/*! @name DE - Module DMA/Trigger Enable register */
+/*! @{ */
+#define LLWU_DE_WUDE0_MASK                       (0x1U)
+#define LLWU_DE_WUDE0_SHIFT                      (0U)
+/*! WUDE0 - DMA/Trigger wakeup enable for module n
+ *  0b0..Internal module request not enabled as a DMA/Trigger wakeup source
+ *  0b1..Internal module request enabled as a DMA/Trigger wakeup source
+ */
+#define LLWU_DE_WUDE0(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE0_SHIFT)) & LLWU_DE_WUDE0_MASK)
+#define LLWU_DE_WUDE1_MASK                       (0x2U)
+#define LLWU_DE_WUDE1_SHIFT                      (1U)
+/*! WUDE1 - DMA/Trigger wakeup enable for module n
+ *  0b0..Internal module request not enabled as a DMA/Trigger wakeup source
+ *  0b1..Internal module request enabled as a DMA/Trigger wakeup source
+ */
+#define LLWU_DE_WUDE1(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE1_SHIFT)) & LLWU_DE_WUDE1_MASK)
+#define LLWU_DE_WUDE2_MASK                       (0x4U)
+#define LLWU_DE_WUDE2_SHIFT                      (2U)
+/*! WUDE2 - DMA/Trigger wakeup enable for module n
+ *  0b0..Internal module request not enabled as a DMA/Trigger wakeup source
+ *  0b1..Internal module request enabled as a DMA/Trigger wakeup source
+ */
+#define LLWU_DE_WUDE2(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE2_SHIFT)) & LLWU_DE_WUDE2_MASK)
+#define LLWU_DE_Reserved3_MASK                   (0x8U)
+#define LLWU_DE_Reserved3_SHIFT                  (3U)
+/*! Reserved3 - DMA/Trigger wakeup enable for module n
+ *  0b0..Internal module request not enabled as a DMA/Trigger wakeup source
+ *  0b1..Internal module request enabled as a DMA/Trigger wakeup source
+ */
+#define LLWU_DE_Reserved3(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_DE_Reserved3_SHIFT)) & LLWU_DE_Reserved3_MASK)
+#define LLWU_DE_WUDE4_MASK                       (0x10U)
+#define LLWU_DE_WUDE4_SHIFT                      (4U)
+/*! WUDE4 - DMA/Trigger wakeup enable for module n
+ *  0b0..Internal module request not enabled as a DMA/Trigger wakeup source
+ *  0b1..Internal module request enabled as a DMA/Trigger wakeup source
+ */
+#define LLWU_DE_WUDE4(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE4_SHIFT)) & LLWU_DE_WUDE4_MASK)
+#define LLWU_DE_WUDE5_MASK                       (0x20U)
+#define LLWU_DE_WUDE5_SHIFT                      (5U)
+/*! WUDE5 - DMA/Trigger wakeup enable for module n
+ *  0b0..Internal module request not enabled as a DMA/Trigger wakeup source
+ *  0b1..Internal module request enabled as a DMA/Trigger wakeup source
+ */
+#define LLWU_DE_WUDE5(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE5_SHIFT)) & LLWU_DE_WUDE5_MASK)
+#define LLWU_DE_WUDE6_MASK                       (0x40U)
+#define LLWU_DE_WUDE6_SHIFT                      (6U)
+/*! WUDE6 - DMA/Trigger wakeup enable for module n
+ *  0b0..Internal module request not enabled as a DMA/Trigger wakeup source
+ *  0b1..Internal module request enabled as a DMA/Trigger wakeup source
+ */
+#define LLWU_DE_WUDE6(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE6_SHIFT)) & LLWU_DE_WUDE6_MASK)
+#define LLWU_DE_Reserved7_MASK                   (0x80U)
+#define LLWU_DE_Reserved7_SHIFT                  (7U)
+/*! Reserved7 - DMA/Trigger wakeup enable for module n
+ *  0b0..Internal module request not enabled as a DMA/Trigger wakeup source
+ *  0b1..Internal module request enabled as a DMA/Trigger wakeup source
+ */
+#define LLWU_DE_Reserved7(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_DE_Reserved7_SHIFT)) & LLWU_DE_Reserved7_MASK)
+/*! @} */
+
+/*! @name PF - Pin Flag register */
+/*! @{ */
+#define LLWU_PF_WUF0_MASK                        (0x1U)
+#define LLWU_PF_WUF0_SHIFT                       (0U)
+/*! WUF0 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF0(x)                          (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF0_SHIFT)) & LLWU_PF_WUF0_MASK)
+#define LLWU_PF_WUF1_MASK                        (0x2U)
+#define LLWU_PF_WUF1_SHIFT                       (1U)
+/*! WUF1 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF1(x)                          (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF1_SHIFT)) & LLWU_PF_WUF1_MASK)
+#define LLWU_PF_WUF2_MASK                        (0x4U)
+#define LLWU_PF_WUF2_SHIFT                       (2U)
+/*! WUF2 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF2(x)                          (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF2_SHIFT)) & LLWU_PF_WUF2_MASK)
+#define LLWU_PF_WUF3_MASK                        (0x8U)
+#define LLWU_PF_WUF3_SHIFT                       (3U)
+/*! WUF3 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF3(x)                          (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF3_SHIFT)) & LLWU_PF_WUF3_MASK)
+#define LLWU_PF_WUF4_MASK                        (0x10U)
+#define LLWU_PF_WUF4_SHIFT                       (4U)
+/*! WUF4 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF4(x)                          (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF4_SHIFT)) & LLWU_PF_WUF4_MASK)
+#define LLWU_PF_WUF5_MASK                        (0x20U)
+#define LLWU_PF_WUF5_SHIFT                       (5U)
+/*! WUF5 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF5(x)                          (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF5_SHIFT)) & LLWU_PF_WUF5_MASK)
+#define LLWU_PF_WUF6_MASK                        (0x40U)
+#define LLWU_PF_WUF6_SHIFT                       (6U)
+/*! WUF6 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF6(x)                          (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF6_SHIFT)) & LLWU_PF_WUF6_MASK)
+#define LLWU_PF_WUF7_MASK                        (0x80U)
+#define LLWU_PF_WUF7_SHIFT                       (7U)
+/*! WUF7 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF7(x)                          (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF7_SHIFT)) & LLWU_PF_WUF7_MASK)
+#define LLWU_PF_WUF8_MASK                        (0x100U)
+#define LLWU_PF_WUF8_SHIFT                       (8U)
+/*! WUF8 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF8(x)                          (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF8_SHIFT)) & LLWU_PF_WUF8_MASK)
+#define LLWU_PF_WUF9_MASK                        (0x200U)
+#define LLWU_PF_WUF9_SHIFT                       (9U)
+/*! WUF9 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF9(x)                          (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF9_SHIFT)) & LLWU_PF_WUF9_MASK)
+#define LLWU_PF_WUF10_MASK                       (0x400U)
+#define LLWU_PF_WUF10_SHIFT                      (10U)
+/*! WUF10 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF10(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF10_SHIFT)) & LLWU_PF_WUF10_MASK)
+#define LLWU_PF_WUF11_MASK                       (0x800U)
+#define LLWU_PF_WUF11_SHIFT                      (11U)
+/*! WUF11 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF11(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF11_SHIFT)) & LLWU_PF_WUF11_MASK)
+#define LLWU_PF_WUF12_MASK                       (0x1000U)
+#define LLWU_PF_WUF12_SHIFT                      (12U)
+/*! WUF12 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF12(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF12_SHIFT)) & LLWU_PF_WUF12_MASK)
+#define LLWU_PF_WUF13_MASK                       (0x2000U)
+#define LLWU_PF_WUF13_SHIFT                      (13U)
+/*! WUF13 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF13(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF13_SHIFT)) & LLWU_PF_WUF13_MASK)
+#define LLWU_PF_WUF14_MASK                       (0x4000U)
+#define LLWU_PF_WUF14_SHIFT                      (14U)
+/*! WUF14 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF14(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF14_SHIFT)) & LLWU_PF_WUF14_MASK)
+#define LLWU_PF_WUF15_MASK                       (0x8000U)
+#define LLWU_PF_WUF15_SHIFT                      (15U)
+/*! WUF15 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF15(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF15_SHIFT)) & LLWU_PF_WUF15_MASK)
+#define LLWU_PF_WUF16_MASK                       (0x10000U)
+#define LLWU_PF_WUF16_SHIFT                      (16U)
+/*! WUF16 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF16(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF16_SHIFT)) & LLWU_PF_WUF16_MASK)
+#define LLWU_PF_WUF17_MASK                       (0x20000U)
+#define LLWU_PF_WUF17_SHIFT                      (17U)
+/*! WUF17 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF17(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF17_SHIFT)) & LLWU_PF_WUF17_MASK)
+#define LLWU_PF_WUF18_MASK                       (0x40000U)
+#define LLWU_PF_WUF18_SHIFT                      (18U)
+/*! WUF18 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF18(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF18_SHIFT)) & LLWU_PF_WUF18_MASK)
+#define LLWU_PF_WUF19_MASK                       (0x80000U)
+#define LLWU_PF_WUF19_SHIFT                      (19U)
+/*! WUF19 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF19(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF19_SHIFT)) & LLWU_PF_WUF19_MASK)
+#define LLWU_PF_WUF20_MASK                       (0x100000U)
+#define LLWU_PF_WUF20_SHIFT                      (20U)
+/*! WUF20 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF20(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF20_SHIFT)) & LLWU_PF_WUF20_MASK)
+#define LLWU_PF_WUF21_MASK                       (0x200000U)
+#define LLWU_PF_WUF21_SHIFT                      (21U)
+/*! WUF21 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF21(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF21_SHIFT)) & LLWU_PF_WUF21_MASK)
+#define LLWU_PF_WUF22_MASK                       (0x400000U)
+#define LLWU_PF_WUF22_SHIFT                      (22U)
+/*! WUF22 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF22(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF22_SHIFT)) & LLWU_PF_WUF22_MASK)
+#define LLWU_PF_WUF23_MASK                       (0x800000U)
+#define LLWU_PF_WUF23_SHIFT                      (23U)
+/*! WUF23 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF23(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF23_SHIFT)) & LLWU_PF_WUF23_MASK)
+#define LLWU_PF_WUF24_MASK                       (0x1000000U)
+#define LLWU_PF_WUF24_SHIFT                      (24U)
+/*! WUF24 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF24(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF24_SHIFT)) & LLWU_PF_WUF24_MASK)
+#define LLWU_PF_WUF25_MASK                       (0x2000000U)
+#define LLWU_PF_WUF25_SHIFT                      (25U)
+/*! WUF25 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF25(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF25_SHIFT)) & LLWU_PF_WUF25_MASK)
+#define LLWU_PF_WUF26_MASK                       (0x4000000U)
+#define LLWU_PF_WUF26_SHIFT                      (26U)
+/*! WUF26 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF26(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF26_SHIFT)) & LLWU_PF_WUF26_MASK)
+#define LLWU_PF_Reserved27_MASK                  (0x8000000U)
+#define LLWU_PF_Reserved27_SHIFT                 (27U)
+/*! Reserved27 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_Reserved27(x)                    (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved27_SHIFT)) & LLWU_PF_Reserved27_MASK)
+#define LLWU_PF_Reserved28_MASK                  (0x10000000U)
+#define LLWU_PF_Reserved28_SHIFT                 (28U)
+/*! Reserved28 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_Reserved28(x)                    (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved28_SHIFT)) & LLWU_PF_Reserved28_MASK)
+#define LLWU_PF_WUF29_MASK                       (0x20000000U)
+#define LLWU_PF_WUF29_SHIFT                      (29U)
+/*! WUF29 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF29(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF29_SHIFT)) & LLWU_PF_WUF29_MASK)
+#define LLWU_PF_WUF30_MASK                       (0x40000000U)
+#define LLWU_PF_WUF30_SHIFT                      (30U)
+/*! WUF30 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF30(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF30_SHIFT)) & LLWU_PF_WUF30_MASK)
+#define LLWU_PF_WUF31_MASK                       (0x80000000U)
+#define LLWU_PF_WUF31_SHIFT                      (31U)
+/*! WUF31 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF31(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF31_SHIFT)) & LLWU_PF_WUF31_MASK)
+/*! @} */
+
+/*! @name FILT - Pin Filter register */
+/*! @{ */
+#define LLWU_FILT_FILTSEL1_MASK                  (0x1FU)
+#define LLWU_FILT_FILTSEL1_SHIFT                 (0U)
+/*! FILTSEL1 - Filter 1 Pin Select
+ *  0b00000..Select LLWU_P0 for filter
+ *  0b11111..Select LLWU_P31 for filter
+ */
+#define LLWU_FILT_FILTSEL1(x)                    (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTSEL1_SHIFT)) & LLWU_FILT_FILTSEL1_MASK)
+#define LLWU_FILT_FILTE1_MASK                    (0x60U)
+#define LLWU_FILT_FILTE1_SHIFT                   (5U)
+/*! FILTE1 - Filter 1 Enable
+ *  0b00..Filter disabled
+ *  0b01..Filter posedge detect enabled when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..Filter negedge detect enabled when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..Filter any edge detect enabled when configured as interrupt/DMA request
+ */
+#define LLWU_FILT_FILTE1(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTE1_SHIFT)) & LLWU_FILT_FILTE1_MASK)
+#define LLWU_FILT_FILTF1_MASK                    (0x80U)
+#define LLWU_FILT_FILTF1_SHIFT                   (7U)
+/*! FILTF1 - Filter 1 Flag
+ *  0b0..Pin Filter 1 was not a wakeup source
+ *  0b1..Pin Filter 1 was a wakeup source
+ */
+#define LLWU_FILT_FILTF1(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTF1_SHIFT)) & LLWU_FILT_FILTF1_MASK)
+#define LLWU_FILT_FILTSEL2_MASK                  (0x1F00U)
+#define LLWU_FILT_FILTSEL2_SHIFT                 (8U)
+/*! FILTSEL2 - Filter 2 Pin Select
+ *  0b00000..Select LLWU_P0 for filter
+ *  0b11111..Select LLWU_P31 for filter
+ */
+#define LLWU_FILT_FILTSEL2(x)                    (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTSEL2_SHIFT)) & LLWU_FILT_FILTSEL2_MASK)
+#define LLWU_FILT_FILTE2_MASK                    (0x6000U)
+#define LLWU_FILT_FILTE2_SHIFT                   (13U)
+/*! FILTE2 - Filter 2 Enable
+ *  0b00..Filter disabled
+ *  0b01..Filter posedge detect enabled when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..Filter negedge detect enabled when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..Filter any edge detect enabled when configured as interrupt/DMA request
+ */
+#define LLWU_FILT_FILTE2(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTE2_SHIFT)) & LLWU_FILT_FILTE2_MASK)
+#define LLWU_FILT_FILTF2_MASK                    (0x8000U)
+#define LLWU_FILT_FILTF2_SHIFT                   (15U)
+/*! FILTF2 - Filter 2 Flag
+ *  0b0..Pin Filter 2 was not a wakeup source
+ *  0b1..Pin Filter 2 was a wakeup source
+ */
+#define LLWU_FILT_FILTF2(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTF2_SHIFT)) & LLWU_FILT_FILTF2_MASK)
+/*! @} */
+
+/*! @name PDC1 - Pin DMA/Trigger Configuration 1 register */
+/*! @{ */
+#define LLWU_PDC1_WUPDC0_MASK                    (0x3U)
+#define LLWU_PDC1_WUPDC0_SHIFT                   (0U)
+/*! WUPDC0 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC0(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC0_SHIFT)) & LLWU_PDC1_WUPDC0_MASK)
+#define LLWU_PDC1_WUPDC1_MASK                    (0xCU)
+#define LLWU_PDC1_WUPDC1_SHIFT                   (2U)
+/*! WUPDC1 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC1(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC1_SHIFT)) & LLWU_PDC1_WUPDC1_MASK)
+#define LLWU_PDC1_WUPDC2_MASK                    (0x30U)
+#define LLWU_PDC1_WUPDC2_SHIFT                   (4U)
+/*! WUPDC2 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC2(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC2_SHIFT)) & LLWU_PDC1_WUPDC2_MASK)
+#define LLWU_PDC1_WUPDC3_MASK                    (0xC0U)
+#define LLWU_PDC1_WUPDC3_SHIFT                   (6U)
+/*! WUPDC3 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC3(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC3_SHIFT)) & LLWU_PDC1_WUPDC3_MASK)
+#define LLWU_PDC1_WUPDC4_MASK                    (0x300U)
+#define LLWU_PDC1_WUPDC4_SHIFT                   (8U)
+/*! WUPDC4 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC4(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC4_SHIFT)) & LLWU_PDC1_WUPDC4_MASK)
+#define LLWU_PDC1_WUPDC5_MASK                    (0xC00U)
+#define LLWU_PDC1_WUPDC5_SHIFT                   (10U)
+/*! WUPDC5 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC5(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC5_SHIFT)) & LLWU_PDC1_WUPDC5_MASK)
+#define LLWU_PDC1_WUPDC6_MASK                    (0x3000U)
+#define LLWU_PDC1_WUPDC6_SHIFT                   (12U)
+/*! WUPDC6 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC6(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC6_SHIFT)) & LLWU_PDC1_WUPDC6_MASK)
+#define LLWU_PDC1_WUPDC7_MASK                    (0xC000U)
+#define LLWU_PDC1_WUPDC7_SHIFT                   (14U)
+/*! WUPDC7 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC7(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC7_SHIFT)) & LLWU_PDC1_WUPDC7_MASK)
+#define LLWU_PDC1_WUPDC8_MASK                    (0x30000U)
+#define LLWU_PDC1_WUPDC8_SHIFT                   (16U)
+/*! WUPDC8 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC8(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC8_SHIFT)) & LLWU_PDC1_WUPDC8_MASK)
+#define LLWU_PDC1_WUPDC9_MASK                    (0xC0000U)
+#define LLWU_PDC1_WUPDC9_SHIFT                   (18U)
+/*! WUPDC9 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC9(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC9_SHIFT)) & LLWU_PDC1_WUPDC9_MASK)
+#define LLWU_PDC1_WUPDC10_MASK                   (0x300000U)
+#define LLWU_PDC1_WUPDC10_SHIFT                  (20U)
+/*! WUPDC10 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC10(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC10_SHIFT)) & LLWU_PDC1_WUPDC10_MASK)
+#define LLWU_PDC1_WUPDC11_MASK                   (0xC00000U)
+#define LLWU_PDC1_WUPDC11_SHIFT                  (22U)
+/*! WUPDC11 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC11(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC11_SHIFT)) & LLWU_PDC1_WUPDC11_MASK)
+#define LLWU_PDC1_WUPDC12_MASK                   (0x3000000U)
+#define LLWU_PDC1_WUPDC12_SHIFT                  (24U)
+/*! WUPDC12 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC12(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC12_SHIFT)) & LLWU_PDC1_WUPDC12_MASK)
+#define LLWU_PDC1_WUPDC13_MASK                   (0xC000000U)
+#define LLWU_PDC1_WUPDC13_SHIFT                  (26U)
+/*! WUPDC13 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC13(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC13_SHIFT)) & LLWU_PDC1_WUPDC13_MASK)
+#define LLWU_PDC1_WUPDC14_MASK                   (0x30000000U)
+#define LLWU_PDC1_WUPDC14_SHIFT                  (28U)
+/*! WUPDC14 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC14(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC14_SHIFT)) & LLWU_PDC1_WUPDC14_MASK)
+#define LLWU_PDC1_WUPDC15_MASK                   (0xC0000000U)
+#define LLWU_PDC1_WUPDC15_SHIFT                  (30U)
+/*! WUPDC15 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC15(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC15_SHIFT)) & LLWU_PDC1_WUPDC15_MASK)
+/*! @} */
+
+/*! @name PDC2 - Pin DMA/Trigger Configuration 2 register */
+/*! @{ */
+#define LLWU_PDC2_WUPDC16_MASK                   (0x3U)
+#define LLWU_PDC2_WUPDC16_SHIFT                  (0U)
+/*! WUPDC16 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC16(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC16_SHIFT)) & LLWU_PDC2_WUPDC16_MASK)
+#define LLWU_PDC2_WUPDC17_MASK                   (0xCU)
+#define LLWU_PDC2_WUPDC17_SHIFT                  (2U)
+/*! WUPDC17 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC17(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC17_SHIFT)) & LLWU_PDC2_WUPDC17_MASK)
+#define LLWU_PDC2_WUPDC18_MASK                   (0x30U)
+#define LLWU_PDC2_WUPDC18_SHIFT                  (4U)
+/*! WUPDC18 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC18(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC18_SHIFT)) & LLWU_PDC2_WUPDC18_MASK)
+#define LLWU_PDC2_WUPDC19_MASK                   (0xC0U)
+#define LLWU_PDC2_WUPDC19_SHIFT                  (6U)
+/*! WUPDC19 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC19(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC19_SHIFT)) & LLWU_PDC2_WUPDC19_MASK)
+#define LLWU_PDC2_WUPDC20_MASK                   (0x300U)
+#define LLWU_PDC2_WUPDC20_SHIFT                  (8U)
+/*! WUPDC20 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC20(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC20_SHIFT)) & LLWU_PDC2_WUPDC20_MASK)
+#define LLWU_PDC2_WUPDC21_MASK                   (0xC00U)
+#define LLWU_PDC2_WUPDC21_SHIFT                  (10U)
+/*! WUPDC21 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC21(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC21_SHIFT)) & LLWU_PDC2_WUPDC21_MASK)
+#define LLWU_PDC2_WUPDC22_MASK                   (0x3000U)
+#define LLWU_PDC2_WUPDC22_SHIFT                  (12U)
+/*! WUPDC22 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC22(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC22_SHIFT)) & LLWU_PDC2_WUPDC22_MASK)
+#define LLWU_PDC2_WUPDC23_MASK                   (0xC000U)
+#define LLWU_PDC2_WUPDC23_SHIFT                  (14U)
+/*! WUPDC23 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC23(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC23_SHIFT)) & LLWU_PDC2_WUPDC23_MASK)
+#define LLWU_PDC2_WUPDC24_MASK                   (0x30000U)
+#define LLWU_PDC2_WUPDC24_SHIFT                  (16U)
+/*! WUPDC24 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC24(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC24_SHIFT)) & LLWU_PDC2_WUPDC24_MASK)
+#define LLWU_PDC2_WUPDC25_MASK                   (0xC0000U)
+#define LLWU_PDC2_WUPDC25_SHIFT                  (18U)
+/*! WUPDC25 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC25(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC25_SHIFT)) & LLWU_PDC2_WUPDC25_MASK)
+#define LLWU_PDC2_WUPDC26_MASK                   (0x300000U)
+#define LLWU_PDC2_WUPDC26_SHIFT                  (20U)
+/*! WUPDC26 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC26(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC26_SHIFT)) & LLWU_PDC2_WUPDC26_MASK)
+#define LLWU_PDC2_Reserved27_MASK                (0xC00000U)
+#define LLWU_PDC2_Reserved27_SHIFT               (22U)
+/*! Reserved27 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_Reserved27(x)                  (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_Reserved27_SHIFT)) & LLWU_PDC2_Reserved27_MASK)
+#define LLWU_PDC2_Reserved28_MASK                (0x3000000U)
+#define LLWU_PDC2_Reserved28_SHIFT               (24U)
+/*! Reserved28 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_Reserved28(x)                  (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_Reserved28_SHIFT)) & LLWU_PDC2_Reserved28_MASK)
+#define LLWU_PDC2_WUPDC29_MASK                   (0xC000000U)
+#define LLWU_PDC2_WUPDC29_SHIFT                  (26U)
+/*! WUPDC29 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC29(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC29_SHIFT)) & LLWU_PDC2_WUPDC29_MASK)
+#define LLWU_PDC2_WUPDC30_MASK                   (0x30000000U)
+#define LLWU_PDC2_WUPDC30_SHIFT                  (28U)
+/*! WUPDC30 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC30(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC30_SHIFT)) & LLWU_PDC2_WUPDC30_MASK)
+#define LLWU_PDC2_WUPDC31_MASK                   (0xC0000000U)
+#define LLWU_PDC2_WUPDC31_SHIFT                  (30U)
+/*! WUPDC31 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC31(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC31_SHIFT)) & LLWU_PDC2_WUPDC31_MASK)
+/*! @} */
+
+/*! @name FDC - Pin Filter DMA/Trigger Configuration register */
+/*! @{ */
+#define LLWU_FDC_FILTC1_MASK                     (0x3U)
+#define LLWU_FDC_FILTC1_SHIFT                    (0U)
+/*! FILTC1 - Filter configuration for FILT1
+ *  0b00..Filter output configured as interrupt
+ *  0b01..Filter output configured as DMA request
+ *  0b10..Filter output configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_FDC_FILTC1(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_FDC_FILTC1_SHIFT)) & LLWU_FDC_FILTC1_MASK)
+#define LLWU_FDC_FILTC2_MASK                     (0xCU)
+#define LLWU_FDC_FILTC2_SHIFT                    (2U)
+/*! FILTC2 - Filter configuration for FILT2
+ *  0b00..Filter output configured as interrupt
+ *  0b01..Filter output configured as DMA request
+ *  0b10..Filter output configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_FDC_FILTC2(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_FDC_FILTC2_SHIFT)) & LLWU_FDC_FILTC2_MASK)
+/*! @} */
+
+/*! @name PMC - Pin Mode Configuration register */
+/*! @{ */
+#define LLWU_PMC_WUPMC0_MASK                     (0x1U)
+#define LLWU_PMC_WUPMC0_SHIFT                    (0U)
+/*! WUPMC0 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC0(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC0_SHIFT)) & LLWU_PMC_WUPMC0_MASK)
+#define LLWU_PMC_WUPMC1_MASK                     (0x2U)
+#define LLWU_PMC_WUPMC1_SHIFT                    (1U)
+/*! WUPMC1 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC1(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC1_SHIFT)) & LLWU_PMC_WUPMC1_MASK)
+#define LLWU_PMC_WUPMC2_MASK                     (0x4U)
+#define LLWU_PMC_WUPMC2_SHIFT                    (2U)
+/*! WUPMC2 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC2(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC2_SHIFT)) & LLWU_PMC_WUPMC2_MASK)
+#define LLWU_PMC_WUPMC3_MASK                     (0x8U)
+#define LLWU_PMC_WUPMC3_SHIFT                    (3U)
+/*! WUPMC3 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC3(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC3_SHIFT)) & LLWU_PMC_WUPMC3_MASK)
+#define LLWU_PMC_WUPMC4_MASK                     (0x10U)
+#define LLWU_PMC_WUPMC4_SHIFT                    (4U)
+/*! WUPMC4 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC4(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC4_SHIFT)) & LLWU_PMC_WUPMC4_MASK)
+#define LLWU_PMC_WUPMC5_MASK                     (0x20U)
+#define LLWU_PMC_WUPMC5_SHIFT                    (5U)
+/*! WUPMC5 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC5(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC5_SHIFT)) & LLWU_PMC_WUPMC5_MASK)
+#define LLWU_PMC_WUPMC6_MASK                     (0x40U)
+#define LLWU_PMC_WUPMC6_SHIFT                    (6U)
+/*! WUPMC6 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC6(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC6_SHIFT)) & LLWU_PMC_WUPMC6_MASK)
+#define LLWU_PMC_WUPMC7_MASK                     (0x80U)
+#define LLWU_PMC_WUPMC7_SHIFT                    (7U)
+/*! WUPMC7 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC7(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC7_SHIFT)) & LLWU_PMC_WUPMC7_MASK)
+#define LLWU_PMC_WUPMC8_MASK                     (0x100U)
+#define LLWU_PMC_WUPMC8_SHIFT                    (8U)
+/*! WUPMC8 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC8(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC8_SHIFT)) & LLWU_PMC_WUPMC8_MASK)
+#define LLWU_PMC_WUPMC9_MASK                     (0x200U)
+#define LLWU_PMC_WUPMC9_SHIFT                    (9U)
+/*! WUPMC9 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC9(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC9_SHIFT)) & LLWU_PMC_WUPMC9_MASK)
+#define LLWU_PMC_WUPMC10_MASK                    (0x400U)
+#define LLWU_PMC_WUPMC10_SHIFT                   (10U)
+/*! WUPMC10 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC10(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC10_SHIFT)) & LLWU_PMC_WUPMC10_MASK)
+#define LLWU_PMC_WUPMC11_MASK                    (0x800U)
+#define LLWU_PMC_WUPMC11_SHIFT                   (11U)
+/*! WUPMC11 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC11(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC11_SHIFT)) & LLWU_PMC_WUPMC11_MASK)
+#define LLWU_PMC_WUPMC12_MASK                    (0x1000U)
+#define LLWU_PMC_WUPMC12_SHIFT                   (12U)
+/*! WUPMC12 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC12(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC12_SHIFT)) & LLWU_PMC_WUPMC12_MASK)
+#define LLWU_PMC_WUPMC13_MASK                    (0x2000U)
+#define LLWU_PMC_WUPMC13_SHIFT                   (13U)
+/*! WUPMC13 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC13(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC13_SHIFT)) & LLWU_PMC_WUPMC13_MASK)
+#define LLWU_PMC_WUPMC14_MASK                    (0x4000U)
+#define LLWU_PMC_WUPMC14_SHIFT                   (14U)
+/*! WUPMC14 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC14(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC14_SHIFT)) & LLWU_PMC_WUPMC14_MASK)
+#define LLWU_PMC_WUPMC15_MASK                    (0x8000U)
+#define LLWU_PMC_WUPMC15_SHIFT                   (15U)
+/*! WUPMC15 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC15(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC15_SHIFT)) & LLWU_PMC_WUPMC15_MASK)
+#define LLWU_PMC_WUPMC16_MASK                    (0x10000U)
+#define LLWU_PMC_WUPMC16_SHIFT                   (16U)
+/*! WUPMC16 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC16(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC16_SHIFT)) & LLWU_PMC_WUPMC16_MASK)
+#define LLWU_PMC_WUPMC17_MASK                    (0x20000U)
+#define LLWU_PMC_WUPMC17_SHIFT                   (17U)
+/*! WUPMC17 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC17(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC17_SHIFT)) & LLWU_PMC_WUPMC17_MASK)
+#define LLWU_PMC_WUPMC18_MASK                    (0x40000U)
+#define LLWU_PMC_WUPMC18_SHIFT                   (18U)
+/*! WUPMC18 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC18(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC18_SHIFT)) & LLWU_PMC_WUPMC18_MASK)
+#define LLWU_PMC_WUPMC19_MASK                    (0x80000U)
+#define LLWU_PMC_WUPMC19_SHIFT                   (19U)
+/*! WUPMC19 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC19(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC19_SHIFT)) & LLWU_PMC_WUPMC19_MASK)
+#define LLWU_PMC_WUPMC20_MASK                    (0x100000U)
+#define LLWU_PMC_WUPMC20_SHIFT                   (20U)
+/*! WUPMC20 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC20(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC20_SHIFT)) & LLWU_PMC_WUPMC20_MASK)
+#define LLWU_PMC_WUPMC21_MASK                    (0x200000U)
+#define LLWU_PMC_WUPMC21_SHIFT                   (21U)
+/*! WUPMC21 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC21(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC21_SHIFT)) & LLWU_PMC_WUPMC21_MASK)
+#define LLWU_PMC_WUPMC22_MASK                    (0x400000U)
+#define LLWU_PMC_WUPMC22_SHIFT                   (22U)
+/*! WUPMC22 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC22(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC22_SHIFT)) & LLWU_PMC_WUPMC22_MASK)
+#define LLWU_PMC_WUPMC23_MASK                    (0x800000U)
+#define LLWU_PMC_WUPMC23_SHIFT                   (23U)
+/*! WUPMC23 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC23(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC23_SHIFT)) & LLWU_PMC_WUPMC23_MASK)
+#define LLWU_PMC_WUPMC24_MASK                    (0x1000000U)
+#define LLWU_PMC_WUPMC24_SHIFT                   (24U)
+/*! WUPMC24 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC24(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC24_SHIFT)) & LLWU_PMC_WUPMC24_MASK)
+#define LLWU_PMC_WUPMC25_MASK                    (0x2000000U)
+#define LLWU_PMC_WUPMC25_SHIFT                   (25U)
+/*! WUPMC25 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC25(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC25_SHIFT)) & LLWU_PMC_WUPMC25_MASK)
+#define LLWU_PMC_WUPMC26_MASK                    (0x4000000U)
+#define LLWU_PMC_WUPMC26_SHIFT                   (26U)
+/*! WUPMC26 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC26(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC26_SHIFT)) & LLWU_PMC_WUPMC26_MASK)
+#define LLWU_PMC_Reserved27_MASK                 (0x8000000U)
+#define LLWU_PMC_Reserved27_SHIFT                (27U)
+/*! Reserved27 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_Reserved27(x)                   (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_Reserved27_SHIFT)) & LLWU_PMC_Reserved27_MASK)
+#define LLWU_PMC_Reserved28_MASK                 (0x10000000U)
+#define LLWU_PMC_Reserved28_SHIFT                (28U)
+/*! Reserved28 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_Reserved28(x)                   (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_Reserved28_SHIFT)) & LLWU_PMC_Reserved28_MASK)
+#define LLWU_PMC_WUPMC29_MASK                    (0x20000000U)
+#define LLWU_PMC_WUPMC29_SHIFT                   (29U)
+/*! WUPMC29 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC29(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC29_SHIFT)) & LLWU_PMC_WUPMC29_MASK)
+#define LLWU_PMC_WUPMC30_MASK                    (0x40000000U)
+#define LLWU_PMC_WUPMC30_SHIFT                   (30U)
+/*! WUPMC30 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC30(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC30_SHIFT)) & LLWU_PMC_WUPMC30_MASK)
+#define LLWU_PMC_WUPMC31_MASK                    (0x80000000U)
+#define LLWU_PMC_WUPMC31_SHIFT                   (31U)
+/*! WUPMC31 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC31(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC31_SHIFT)) & LLWU_PMC_WUPMC31_MASK)
+/*! @} */
+
+/*! @name FMC - Pin Filter Mode Configuration register */
+/*! @{ */
+#define LLWU_FMC_FILTM1_MASK                     (0x1U)
+#define LLWU_FMC_FILTM1_SHIFT                    (0U)
+/*! FILTM1 - Filter Mode for FILT1
+ *  0b0..External input pin filter detection active only during LLS/VLLS mode
+ *  0b1..External input pin filter detection active during all power modes
+ */
+#define LLWU_FMC_FILTM1(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_FMC_FILTM1_SHIFT)) & LLWU_FMC_FILTM1_MASK)
+#define LLWU_FMC_FILTM2_MASK                     (0x2U)
+#define LLWU_FMC_FILTM2_SHIFT                    (1U)
+/*! FILTM2 - Filter Mode for FILT2
+ *  0b0..External input pin filter detection active only during LLS/VLLS mode
+ *  0b1..External input pin filter detection active during all power modes
+ */
+#define LLWU_FMC_FILTM2(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_FMC_FILTM2_SHIFT)) & LLWU_FMC_FILTM2_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU0 base address */
+#define LLWU0_BASE                               (0x40024000u)
+/** Peripheral LLWU0 base pointer */
+#define LLWU0                                    ((LLWU_Type *)LLWU0_BASE)
+/** Peripheral LLWU1 base address */
+#define LLWU1_BASE                               (0x41023000u)
+/** Peripheral LLWU1 base pointer */
+#define LLWU1                                    ((LLWU_Type *)LLWU1_BASE)
+/** Array initializer of LLWU peripheral base addresses */
+#define LLWU_BASE_ADDRS                          { LLWU0_BASE, LLWU1_BASE }
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASE_PTRS                           { LLWU0, LLWU1 }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS                                { LLWU0_IRQn, NotAvail_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPCMP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPCMP_Peripheral_Access_Layer LPCMP Peripheral Access Layer
+ * @{
+ */
+
+/** LPCMP - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __IO uint32_t CCR0;                              /**< Comparator Control Register 0, offset: 0x8 */
+  __IO uint32_t CCR1;                              /**< Comparator Control Register 1, offset: 0xC */
+  __IO uint32_t CCR2;                              /**< Comparator Control Register 2, offset: 0x10 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t DCR;                               /**< DAC Control Register, offset: 0x18 */
+  __IO uint32_t IER;                               /**< Interrupt Enable Register, offset: 0x1C */
+  __IO uint32_t CSR;                               /**< Comparator Status Register, offset: 0x20 */
+} LPCMP_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPCMP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPCMP_Register_Masks LPCMP Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define LPCMP_VERID_FEATURE_MASK                 (0xFFFFU)
+#define LPCMP_VERID_FEATURE_SHIFT                (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000000000001..Round robin feature
+ */
+#define LPCMP_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_FEATURE_SHIFT)) & LPCMP_VERID_FEATURE_MASK)
+#define LPCMP_VERID_MINOR_MASK                   (0xFF0000U)
+#define LPCMP_VERID_MINOR_SHIFT                  (16U)
+#define LPCMP_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MINOR_SHIFT)) & LPCMP_VERID_MINOR_MASK)
+#define LPCMP_VERID_MAJOR_MASK                   (0xFF000000U)
+#define LPCMP_VERID_MAJOR_SHIFT                  (24U)
+#define LPCMP_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MAJOR_SHIFT)) & LPCMP_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define LPCMP_PARAM_DAC_RES_MASK                 (0xFU)
+#define LPCMP_PARAM_DAC_RES_SHIFT                (0U)
+/*! DAC_RES - DAC resolution
+ *  0b0000..4 bit DAC
+ *  0b0001..6 bit DAC
+ *  0b0010..8 bit DAC
+ *  0b0011..10 bit DAC
+ *  0b0100..12 bit DAC
+ *  0b0101..14 bit DAC
+ *  0b0110..16 bit DAC
+ */
+#define LPCMP_PARAM_DAC_RES(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_PARAM_DAC_RES_SHIFT)) & LPCMP_PARAM_DAC_RES_MASK)
+/*! @} */
+
+/*! @name CCR0 - Comparator Control Register 0 */
+/*! @{ */
+#define LPCMP_CCR0_CMP_EN_MASK                   (0x1U)
+#define LPCMP_CCR0_CMP_EN_SHIFT                  (0U)
+/*! CMP_EN - Comparator Module Enable
+ *  0b0..Analog Comparator is disabled.
+ *  0b1..Analog Comparator is enabled.
+ */
+#define LPCMP_CCR0_CMP_EN(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_EN_SHIFT)) & LPCMP_CCR0_CMP_EN_MASK)
+#define LPCMP_CCR0_CMP_STOP_EN_MASK              (0x2U)
+#define LPCMP_CCR0_CMP_STOP_EN_SHIFT             (1U)
+/*! CMP_STOP_EN - Comparator Module STOP Mode Enable
+ *  0b0..Comparator is disabled in STOP modes regardless of CMP_EN.
+ *  0b1..Comparator is enabled in STOP mode if CMP_EN is active
+ */
+#define LPCMP_CCR0_CMP_STOP_EN(x)                (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_STOP_EN_SHIFT)) & LPCMP_CCR0_CMP_STOP_EN_MASK)
+/*! @} */
+
+/*! @name CCR1 - Comparator Control Register 1 */
+/*! @{ */
+#define LPCMP_CCR1_WINDOW_EN_MASK                (0x1U)
+#define LPCMP_CCR1_WINDOW_EN_SHIFT               (0U)
+/*! WINDOW_EN - Windowing Enable
+ *  0b0..Windowing mode is not selected.
+ *  0b1..Windowing mode is selected.
+ */
+#define LPCMP_CCR1_WINDOW_EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_EN_SHIFT)) & LPCMP_CCR1_WINDOW_EN_MASK)
+#define LPCMP_CCR1_SAMPLE_EN_MASK                (0x2U)
+#define LPCMP_CCR1_SAMPLE_EN_SHIFT               (1U)
+/*! SAMPLE_EN - Sample Enable
+ *  0b0..Sampling mode is not selected.
+ *  0b1..Sampling mode is selected.
+ */
+#define LPCMP_CCR1_SAMPLE_EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_SAMPLE_EN_SHIFT)) & LPCMP_CCR1_SAMPLE_EN_MASK)
+#define LPCMP_CCR1_DMA_EN_MASK                   (0x4U)
+#define LPCMP_CCR1_DMA_EN_SHIFT                  (2U)
+/*! DMA_EN - DMA Enable
+ *  0b0..DMA is disabled.
+ *  0b1..DMA is enabled.
+ */
+#define LPCMP_CCR1_DMA_EN(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_DMA_EN_SHIFT)) & LPCMP_CCR1_DMA_EN_MASK)
+#define LPCMP_CCR1_COUT_INV_MASK                 (0x8U)
+#define LPCMP_CCR1_COUT_INV_SHIFT                (3U)
+/*! COUT_INV - Comparator invert
+ *  0b0..Does not invert the comparator output.
+ *  0b1..Inverts the comparator output.
+ */
+#define LPCMP_CCR1_COUT_INV(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_INV_SHIFT)) & LPCMP_CCR1_COUT_INV_MASK)
+#define LPCMP_CCR1_COUT_SEL_MASK                 (0x10U)
+#define LPCMP_CCR1_COUT_SEL_SHIFT                (4U)
+/*! COUT_SEL - Comparator Output Select
+ *  0b0..Set CMPO to equal COUT (filtered comparator output).
+ *  0b1..Set CMPO to equal COUTA (unfiltered comparator output).
+ */
+#define LPCMP_CCR1_COUT_SEL(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_SEL_SHIFT)) & LPCMP_CCR1_COUT_SEL_MASK)
+#define LPCMP_CCR1_COUT_PEN_MASK                 (0x20U)
+#define LPCMP_CCR1_COUT_PEN_SHIFT                (5U)
+/*! COUT_PEN - Comparator Output Pin Enable
+ *  0b0..When COUT_PEN is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin.
+ *  0b1..When COUT_PEN is 1, and if the software has configured the comparator to own a packaged pin, the comparator output is available in a packaged pin.
+ */
+#define LPCMP_CCR1_COUT_PEN(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_PEN_SHIFT)) & LPCMP_CCR1_COUT_PEN_MASK)
+#define LPCMP_CCR1_FILT_CNT_MASK                 (0x70000U)
+#define LPCMP_CCR1_FILT_CNT_SHIFT                (16U)
+/*! FILT_CNT - Filter Sample Count
+ *  0b000..Filter is disabled. If SAMPLE_EN = 1, then COUT is a logic zero (this is not a legal state in , and is not recommended). If SAMPLE_EN = 0, COUT = COUTA.
+ *  0b001..1 consecutive sample must agree (comparator output is simply sampled).
+ *  0b010..2 consecutive samples must agree.
+ *  0b011..3 consecutive samples must agree.
+ *  0b100..4 consecutive samples must agree.
+ *  0b101..5 consecutive samples must agree.
+ *  0b110..6 consecutive samples must agree.
+ *  0b111..7 consecutive samples must agree.
+ */
+#define LPCMP_CCR1_FILT_CNT(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_CNT_SHIFT)) & LPCMP_CCR1_FILT_CNT_MASK)
+#define LPCMP_CCR1_FILT_PER_MASK                 (0xFF000000U)
+#define LPCMP_CCR1_FILT_PER_SHIFT                (24U)
+#define LPCMP_CCR1_FILT_PER(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_PER_SHIFT)) & LPCMP_CCR1_FILT_PER_MASK)
+/*! @} */
+
+/*! @name CCR2 - Comparator Control Register 2 */
+/*! @{ */
+#define LPCMP_CCR2_CMP_HPMD_MASK                 (0x1U)
+#define LPCMP_CCR2_CMP_HPMD_SHIFT                (0U)
+/*! CMP_HPMD - CMP High Power Mode Select
+ *  0b0..Low speed comparison mode is selected.(when CMP_NPMD is 0)
+ *  0b1..High speed comparison mode is selected.(when CMP_NPMD is 0)
+ */
+#define LPCMP_CCR2_CMP_HPMD(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_HPMD_SHIFT)) & LPCMP_CCR2_CMP_HPMD_MASK)
+#define LPCMP_CCR2_CMP_NPMD_MASK                 (0x2U)
+#define LPCMP_CCR2_CMP_NPMD_SHIFT                (1U)
+/*! CMP_NPMD - CMP Nano Power Mode Select
+ *  0b0..Nano Power Comparator is not enabled (mode is determined by CMP_HPMD)
+ *  0b1..Nano Power Comparator is enabled
+ */
+#define LPCMP_CCR2_CMP_NPMD(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_NPMD_SHIFT)) & LPCMP_CCR2_CMP_NPMD_MASK)
+#define LPCMP_CCR2_HYSTCTR_MASK                  (0x30U)
+#define LPCMP_CCR2_HYSTCTR_SHIFT                 (4U)
+/*! HYSTCTR - Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level
+ *  0b00..The hard block output has level 0 hysteresis internally.
+ *  0b01..The hard block output has level 1 hysteresis internally.
+ *  0b10..The hard block output has level 2 hysteresis internally.
+ *  0b11..The hard block output has level 3 hysteresis internally.
+ */
+#define LPCMP_CCR2_HYSTCTR(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_HYSTCTR_SHIFT)) & LPCMP_CCR2_HYSTCTR_MASK)
+#define LPCMP_CCR2_PSEL_MASK                     (0x70000U)
+#define LPCMP_CCR2_PSEL_SHIFT                    (16U)
+/*! PSEL - Plus Input MUX Control
+ *  0b000..Input 0
+ *  0b001..Input 1
+ *  0b010..Input 2
+ *  0b011..Input 3
+ *  0b100..Input 4
+ *  0b101..Input 5
+ *  0b110..Input 6
+ *  0b111..Internal DAC output
+ */
+#define LPCMP_CCR2_PSEL(x)                       (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_PSEL_SHIFT)) & LPCMP_CCR2_PSEL_MASK)
+#define LPCMP_CCR2_MSEL_MASK                     (0x700000U)
+#define LPCMP_CCR2_MSEL_SHIFT                    (20U)
+/*! MSEL - Minus Input MUX Control
+ *  0b000..Input 0
+ *  0b001..Input 1
+ *  0b010..Input 2
+ *  0b011..Input 3
+ *  0b100..Input 4
+ *  0b101..Input 5
+ *  0b110..Input 6
+ *  0b111..Internal DAC output
+ */
+#define LPCMP_CCR2_MSEL(x)                       (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_MSEL_SHIFT)) & LPCMP_CCR2_MSEL_MASK)
+/*! @} */
+
+/*! @name DCR - DAC Control Register */
+/*! @{ */
+#define LPCMP_DCR_DAC_EN_MASK                    (0x1U)
+#define LPCMP_DCR_DAC_EN_SHIFT                   (0U)
+/*! DAC_EN - DAC Enable
+ *  0b0..DAC is disabled.
+ *  0b1..DAC is enabled.
+ */
+#define LPCMP_DCR_DAC_EN(x)                      (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_EN_SHIFT)) & LPCMP_DCR_DAC_EN_MASK)
+#define LPCMP_DCR_DAC_HPMD_MASK                  (0x2U)
+#define LPCMP_DCR_DAC_HPMD_SHIFT                 (1U)
+/*! DAC_HPMD - DAC High Power Mode Select
+ *  0b0..DAC high power mode is not enabled.
+ *  0b1..DAC high power mode is enabled.
+ */
+#define LPCMP_DCR_DAC_HPMD(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_HPMD_SHIFT)) & LPCMP_DCR_DAC_HPMD_MASK)
+#define LPCMP_DCR_VRSEL_MASK                     (0x100U)
+#define LPCMP_DCR_VRSEL_SHIFT                    (8U)
+/*! VRSEL - Supply Voltage Reference Source Select
+ *  0b0..vrefh_int is selected as resistor ladder network supply reference Vin.
+ *  0b1..vrefh_ext is selected as resistor ladder network supply reference Vin.
+ */
+#define LPCMP_DCR_VRSEL(x)                       (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_VRSEL_SHIFT)) & LPCMP_DCR_VRSEL_MASK)
+#define LPCMP_DCR_DAC_DATA_MASK                  (0x3F0000U)
+#define LPCMP_DCR_DAC_DATA_SHIFT                 (16U)
+#define LPCMP_DCR_DAC_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_DATA_SHIFT)) & LPCMP_DCR_DAC_DATA_MASK)
+/*! @} */
+
+/*! @name IER - Interrupt Enable Register */
+/*! @{ */
+#define LPCMP_IER_CFR_IE_MASK                    (0x1U)
+#define LPCMP_IER_CFR_IE_SHIFT                   (0U)
+/*! CFR_IE - Comparator Flag Rising Interrupt Enable
+ *  0b0..CFR interrupt is disabled.
+ *  0b1..CFR interrupt is enabled.
+ */
+#define LPCMP_IER_CFR_IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFR_IE_SHIFT)) & LPCMP_IER_CFR_IE_MASK)
+#define LPCMP_IER_CFF_IE_MASK                    (0x2U)
+#define LPCMP_IER_CFF_IE_SHIFT                   (1U)
+/*! CFF_IE - Comparator Flag Falling Interrupt Enable
+ *  0b0..CFF interrupt is disabled.
+ *  0b1..CFF interrupt is enabled.
+ */
+#define LPCMP_IER_CFF_IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFF_IE_SHIFT)) & LPCMP_IER_CFF_IE_MASK)
+/*! @} */
+
+/*! @name CSR - Comparator Status Register */
+/*! @{ */
+#define LPCMP_CSR_CFR_MASK                       (0x1U)
+#define LPCMP_CSR_CFR_SHIFT                      (0U)
+/*! CFR - Analog Comparator Flag Rising
+ *  0b0..A rising edge has not been detected on COUT.
+ *  0b1..A rising edge on COUT has occurred.
+ */
+#define LPCMP_CSR_CFR(x)                         (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFR_SHIFT)) & LPCMP_CSR_CFR_MASK)
+#define LPCMP_CSR_CFF_MASK                       (0x2U)
+#define LPCMP_CSR_CFF_SHIFT                      (1U)
+/*! CFF - Analog Comparator Flag Falling
+ *  0b0..A falling edge has not been detected on COUT.
+ *  0b1..A falling edge on COUT has occurred.
+ */
+#define LPCMP_CSR_CFF(x)                         (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFF_SHIFT)) & LPCMP_CSR_CFF_MASK)
+#define LPCMP_CSR_COUT_MASK                      (0x100U)
+#define LPCMP_CSR_COUT_SHIFT                     (8U)
+#define LPCMP_CSR_COUT(x)                        (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_COUT_SHIFT)) & LPCMP_CSR_COUT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LPCMP_Register_Masks */
+
+
+/* LPCMP - Peripheral instance base addresses */
+/** Peripheral LPCMP0 base address */
+#define LPCMP0_BASE                              (0x4004B000u)
+/** Peripheral LPCMP0 base pointer */
+#define LPCMP0                                   ((LPCMP_Type *)LPCMP0_BASE)
+/** Peripheral LPCMP1 base address */
+#define LPCMP1_BASE                              (0x41038000u)
+/** Peripheral LPCMP1 base pointer */
+#define LPCMP1                                   ((LPCMP_Type *)LPCMP1_BASE)
+/** Array initializer of LPCMP peripheral base addresses */
+#define LPCMP_BASE_ADDRS                         { LPCMP0_BASE, LPCMP1_BASE }
+/** Array initializer of LPCMP peripheral base pointers */
+#define LPCMP_BASE_PTRS                          { LPCMP0, LPCMP1 }
+/** Interrupt vectors for the LPCMP peripheral type */
+#define LPCMP_IRQS                               { LPCMP0_IRQn, LPCMP1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPCMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPDAC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPDAC_Peripheral_Access_Layer LPDAC Peripheral Access Layer
+ * @{
+ */
+
+/** LPDAC - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version Identifier Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __O  uint32_t DATA;                              /**< DAC Data Register, offset: 0x8 */
+  __IO uint32_t GCR;                               /**< DAC Global Control Register, offset: 0xC */
+  __IO uint32_t FCR;                               /**< DAC FIFO Control Register, offset: 0x10 */
+  __I  uint32_t FPR;                               /**< DAC FIFO Pointer Register, offset: 0x14 */
+  __IO uint32_t FSR;                               /**< FIFO Status Register, offset: 0x18 */
+  __IO uint32_t IER;                               /**< DAC Interrupt Enable Register, offset: 0x1C */
+  __IO uint32_t DER;                               /**< DAC DMA Enable Register, offset: 0x20 */
+  __IO uint32_t RCR;                               /**< DAC Reset Control Register, offset: 0x24 */
+  __O  uint32_t TCR;                               /**< DAC Trigger Control Register, offset: 0x28 */
+} LPDAC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPDAC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPDAC_Register_Masks LPDAC Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version Identifier Register */
+/*! @{ */
+#define LPDAC_VERID_FEATURE_MASK                 (0xFFFFU)
+#define LPDAC_VERID_FEATURE_SHIFT                (0U)
+#define LPDAC_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_FEATURE_SHIFT)) & LPDAC_VERID_FEATURE_MASK)
+#define LPDAC_VERID_MINOR_MASK                   (0xFF0000U)
+#define LPDAC_VERID_MINOR_SHIFT                  (16U)
+#define LPDAC_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_MINOR_SHIFT)) & LPDAC_VERID_MINOR_MASK)
+#define LPDAC_VERID_MAJOR_MASK                   (0xFF000000U)
+#define LPDAC_VERID_MAJOR_SHIFT                  (24U)
+#define LPDAC_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_MAJOR_SHIFT)) & LPDAC_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define LPDAC_PARAM_FIFOSZ_MASK                  (0x7U)
+#define LPDAC_PARAM_FIFOSZ_SHIFT                 (0U)
+/*! FIFOSZ - FIFO size
+ *  0b000..Reserved
+ *  0b001..FIFO depth is 4
+ *  0b010..FIFO depth is 8
+ *  0b011..FIFO depth is 16
+ *  0b100..FIFO depth is 32
+ *  0b101..FIFO depth is 64
+ *  0b110..FIFO depth is 128
+ *  0b111..FIFO depth is 256
+ */
+#define LPDAC_PARAM_FIFOSZ(x)                    (((uint32_t)(((uint32_t)(x)) << LPDAC_PARAM_FIFOSZ_SHIFT)) & LPDAC_PARAM_FIFOSZ_MASK)
+/*! @} */
+
+/*! @name DATA - DAC Data Register */
+/*! @{ */
+#define LPDAC_DATA_DATA_MASK                     (0xFFFU)
+#define LPDAC_DATA_DATA_SHIFT                    (0U)
+#define LPDAC_DATA_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_DATA_DATA_SHIFT)) & LPDAC_DATA_DATA_MASK)
+/*! @} */
+
+/*! @name GCR - DAC Global Control Register */
+/*! @{ */
+#define LPDAC_GCR_DACEN_MASK                     (0x1U)
+#define LPDAC_GCR_DACEN_SHIFT                    (0U)
+/*! DACEN - DAC Enable
+ *  0b0..The DAC system is disabled.
+ *  0b1..The DAC system is enabled.
+ */
+#define LPDAC_GCR_DACEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACEN_SHIFT)) & LPDAC_GCR_DACEN_MASK)
+#define LPDAC_GCR_DACRFS_MASK                    (0x2U)
+#define LPDAC_GCR_DACRFS_SHIFT                   (1U)
+/*! DACRFS - DAC Reference Select
+ *  0b0..The DAC selects VREFH_INT as the reference voltage.
+ *  0b1..The DAC selects VREFH_EXT as the reference voltage.
+ */
+#define LPDAC_GCR_DACRFS(x)                      (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACRFS_SHIFT)) & LPDAC_GCR_DACRFS_MASK)
+#define LPDAC_GCR_LPEN_MASK                      (0x4U)
+#define LPDAC_GCR_LPEN_SHIFT                     (2U)
+/*! LPEN - Low Power Enable
+ *  0b0..High-Power mode
+ *  0b1..Low-Power mode
+ */
+#define LPDAC_GCR_LPEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_LPEN_SHIFT)) & LPDAC_GCR_LPEN_MASK)
+#define LPDAC_GCR_FIFOEN_MASK                    (0x8U)
+#define LPDAC_GCR_FIFOEN_SHIFT                   (3U)
+/*! FIFOEN - FIFO Enable
+ *  0b0..FIFO mode is disabled and buffer mode is enabled. Any data written to DATA[DATA] goes to buffer then goes to conversion.
+ *  0b1..FIFO mode is enabled. Data will be first read from FIFO to buffer then goes to conversion
+ */
+#define LPDAC_GCR_FIFOEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_FIFOEN_SHIFT)) & LPDAC_GCR_FIFOEN_MASK)
+#define LPDAC_GCR_SWMD_MASK                      (0x10U)
+#define LPDAC_GCR_SWMD_SHIFT                     (4U)
+/*! SWMD - Swing Back Mode
+ *  0b0..Swing back mode disable
+ *  0b1..Swing back mode enable
+ */
+#define LPDAC_GCR_SWMD(x)                        (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_SWMD_SHIFT)) & LPDAC_GCR_SWMD_MASK)
+#define LPDAC_GCR_TRGSEL_MASK                    (0x20U)
+#define LPDAC_GCR_TRGSEL_SHIFT                   (5U)
+/*! TRGSEL - DAC Trigger Select
+ *  0b0..The DAC hardware trigger is selected.
+ *  0b1..The DAC software trigger is selected.
+ */
+#define LPDAC_GCR_TRGSEL(x)                      (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_TRGSEL_SHIFT)) & LPDAC_GCR_TRGSEL_MASK)
+/*! @} */
+
+/*! @name FCR - DAC FIFO Control Register */
+/*! @{ */
+#define LPDAC_FCR_WML_MASK                       (0xFU)
+#define LPDAC_FCR_WML_SHIFT                      (0U)
+#define LPDAC_FCR_WML(x)                         (((uint32_t)(((uint32_t)(x)) << LPDAC_FCR_WML_SHIFT)) & LPDAC_FCR_WML_MASK)
+/*! @} */
+
+/*! @name FPR - DAC FIFO Pointer Register */
+/*! @{ */
+#define LPDAC_FPR_FIFO_RPT_MASK                  (0xFU)
+#define LPDAC_FPR_FIFO_RPT_SHIFT                 (0U)
+#define LPDAC_FPR_FIFO_RPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPDAC_FPR_FIFO_RPT_SHIFT)) & LPDAC_FPR_FIFO_RPT_MASK)
+#define LPDAC_FPR_FIFO_WPT_MASK                  (0xF0000U)
+#define LPDAC_FPR_FIFO_WPT_SHIFT                 (16U)
+#define LPDAC_FPR_FIFO_WPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPDAC_FPR_FIFO_WPT_SHIFT)) & LPDAC_FPR_FIFO_WPT_MASK)
+/*! @} */
+
+/*! @name FSR - FIFO Status Register */
+/*! @{ */
+#define LPDAC_FSR_FULL_MASK                      (0x1U)
+#define LPDAC_FSR_FULL_SHIFT                     (0U)
+/*! FULL - FIFO Full Flag
+ *  0b0..FIFO is not full
+ *  0b1..FIFO is full
+ */
+#define LPDAC_FSR_FULL(x)                        (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_FULL_SHIFT)) & LPDAC_FSR_FULL_MASK)
+#define LPDAC_FSR_EMPTY_MASK                     (0x2U)
+#define LPDAC_FSR_EMPTY_SHIFT                    (1U)
+/*! EMPTY - FIFO Empty Flag
+ *  0b0..FIFO is not empty
+ *  0b1..FIFO is empty
+ */
+#define LPDAC_FSR_EMPTY(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_EMPTY_SHIFT)) & LPDAC_FSR_EMPTY_MASK)
+#define LPDAC_FSR_WM_MASK                        (0x4U)
+#define LPDAC_FSR_WM_SHIFT                       (2U)
+/*! WM - FIFO Watermark Status Flag
+ *  0b0..Data in FIFO is more than watermark level
+ *  0b1..Data in FIFO is less than or equal to watermark level
+ */
+#define LPDAC_FSR_WM(x)                          (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_WM_SHIFT)) & LPDAC_FSR_WM_MASK)
+#define LPDAC_FSR_SWBK_MASK                      (0x8U)
+#define LPDAC_FSR_SWBK_SHIFT                     (3U)
+/*! SWBK - Swing Back One Cycle Complete Flag
+ *  0b0..No swing back cycle has completed since the last time the flag was cleared.
+ *  0b1..At least one swing back cycle has occurred since the last time the flag was cleared.
+ */
+#define LPDAC_FSR_SWBK(x)                        (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_SWBK_SHIFT)) & LPDAC_FSR_SWBK_MASK)
+#define LPDAC_FSR_OF_MASK                        (0x40U)
+#define LPDAC_FSR_OF_SHIFT                       (6U)
+/*! OF - FIFO Overflow Flag
+ *  0b0..No overflow has occurred since the last time the flag was cleared.
+ *  0b1..At least one FIFO overflow has occurred since the last time the flag was cleared.
+ */
+#define LPDAC_FSR_OF(x)                          (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_OF_SHIFT)) & LPDAC_FSR_OF_MASK)
+#define LPDAC_FSR_UF_MASK                        (0x80U)
+#define LPDAC_FSR_UF_SHIFT                       (7U)
+/*! UF - FIFO Underflow Flag
+ *  0b0..No underflow has occurred since the last time the flag was cleared.
+ *  0b1..At least one trigger underflow has occurred since the last time the flag was cleared.
+ */
+#define LPDAC_FSR_UF(x)                          (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_UF_SHIFT)) & LPDAC_FSR_UF_MASK)
+/*! @} */
+
+/*! @name IER - DAC Interrupt Enable Register */
+/*! @{ */
+#define LPDAC_IER_FULL_IE_MASK                   (0x1U)
+#define LPDAC_IER_FULL_IE_SHIFT                  (0U)
+/*! FULL_IE - FIFO Full Interrupt Enable
+ *  0b0..FIFO Full interrupt is disabled.
+ *  0b1..FIFO Full interrupt is enabled.
+ */
+#define LPDAC_IER_FULL_IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_FULL_IE_SHIFT)) & LPDAC_IER_FULL_IE_MASK)
+#define LPDAC_IER_EMPTY_IE_MASK                  (0x2U)
+#define LPDAC_IER_EMPTY_IE_SHIFT                 (1U)
+/*! EMPTY_IE - FIFO Empty Interrupt Enable
+ *  0b0..FIFO Empty interrupt is disabled.
+ *  0b1..FIFO Empty interrupt is enabled.
+ */
+#define LPDAC_IER_EMPTY_IE(x)                    (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_EMPTY_IE_SHIFT)) & LPDAC_IER_EMPTY_IE_MASK)
+#define LPDAC_IER_WM_IE_MASK                     (0x4U)
+#define LPDAC_IER_WM_IE_SHIFT                    (2U)
+/*! WM_IE - FIFO Watermark Interrupt Enable
+ *  0b0..Watermark interrupt is disabled.
+ *  0b1..Watermark interrupt is enabled.
+ */
+#define LPDAC_IER_WM_IE(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_WM_IE_SHIFT)) & LPDAC_IER_WM_IE_MASK)
+#define LPDAC_IER_SWBK_IE_MASK                   (0x8U)
+#define LPDAC_IER_SWBK_IE_SHIFT                  (3U)
+/*! SWBK_IE - Swing back One Cycle Complete Interrupt Enable
+ *  0b0..Swing back one time complete interrupt is disabled.
+ *  0b1..Swing back one time complete interrupt is enabled.
+ */
+#define LPDAC_IER_SWBK_IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_SWBK_IE_SHIFT)) & LPDAC_IER_SWBK_IE_MASK)
+#define LPDAC_IER_OF_IE_MASK                     (0x40U)
+#define LPDAC_IER_OF_IE_SHIFT                    (6U)
+/*! OF_IE - FIFO Overflow Interrupt Enable
+ *  0b0..Overflow interrupt is disabled
+ *  0b1..Overflow interrupt is enabled.
+ */
+#define LPDAC_IER_OF_IE(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_OF_IE_SHIFT)) & LPDAC_IER_OF_IE_MASK)
+#define LPDAC_IER_UF_IE_MASK                     (0x80U)
+#define LPDAC_IER_UF_IE_SHIFT                    (7U)
+/*! UF_IE - FIFO Underflow Interrupt Enable
+ *  0b0..Underflow interrupt is disabled.
+ *  0b1..Underflow interrupt is enabled.
+ */
+#define LPDAC_IER_UF_IE(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_UF_IE_SHIFT)) & LPDAC_IER_UF_IE_MASK)
+/*! @} */
+
+/*! @name DER - DAC DMA Enable Register */
+/*! @{ */
+#define LPDAC_DER_EMPTY_DMAEN_MASK               (0x2U)
+#define LPDAC_DER_EMPTY_DMAEN_SHIFT              (1U)
+/*! EMPTY_DMAEN - FIFO Empty DMA Enable
+ *  0b0..FIFO Empty DMA request is disabled.
+ *  0b1..FIFO Empty DMA request is enabled.
+ */
+#define LPDAC_DER_EMPTY_DMAEN(x)                 (((uint32_t)(((uint32_t)(x)) << LPDAC_DER_EMPTY_DMAEN_SHIFT)) & LPDAC_DER_EMPTY_DMAEN_MASK)
+#define LPDAC_DER_WM_DMAEN_MASK                  (0x4U)
+#define LPDAC_DER_WM_DMAEN_SHIFT                 (2U)
+/*! WM_DMAEN - FIFO Watermark DMA Enable
+ *  0b0..Watermark DMA request is disabled.
+ *  0b1..Watermark DMA request is enabled.
+ */
+#define LPDAC_DER_WM_DMAEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPDAC_DER_WM_DMAEN_SHIFT)) & LPDAC_DER_WM_DMAEN_MASK)
+/*! @} */
+
+/*! @name RCR - DAC Reset Control Register */
+/*! @{ */
+#define LPDAC_RCR_SWRST_MASK                     (0x1U)
+#define LPDAC_RCR_SWRST_SHIFT                    (0U)
+/*! SWRST - Software Reset
+ *  0b0..No effect
+ *  0b1..Software reset
+ */
+#define LPDAC_RCR_SWRST(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_RCR_SWRST_SHIFT)) & LPDAC_RCR_SWRST_MASK)
+#define LPDAC_RCR_FIFORST_MASK                   (0x2U)
+#define LPDAC_RCR_FIFORST_SHIFT                  (1U)
+/*! FIFORST - FIFO Reset
+ *  0b0..No effect
+ *  0b1..FIFO reset
+ */
+#define LPDAC_RCR_FIFORST(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_RCR_FIFORST_SHIFT)) & LPDAC_RCR_FIFORST_MASK)
+/*! @} */
+
+/*! @name TCR - DAC Trigger Control Register */
+/*! @{ */
+#define LPDAC_TCR_SWTRG_MASK                     (0x1U)
+#define LPDAC_TCR_SWTRG_SHIFT                    (0U)
+/*! SWTRG - Software Trigger
+ *  0b0..The DAC soft trigger is not valid.
+ *  0b1..The DAC soft trigger is valid.
+ */
+#define LPDAC_TCR_SWTRG(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_TCR_SWTRG_SHIFT)) & LPDAC_TCR_SWTRG_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LPDAC_Register_Masks */
+
+
+/* LPDAC - Peripheral instance base addresses */
+/** Peripheral LPDAC0 base address */
+#define LPDAC0_BASE                              (0x4004C000u)
+/** Peripheral LPDAC0 base pointer */
+#define LPDAC0                                   ((LPDAC_Type *)LPDAC0_BASE)
+/** Array initializer of LPDAC peripheral base addresses */
+#define LPDAC_BASE_ADDRS                         { LPDAC0_BASE }
+/** Array initializer of LPDAC peripheral base pointers */
+#define LPDAC_BASE_PTRS                          { LPDAC0 }
+/** Interrupt vectors for the LPDAC peripheral type */
+#define LPDAC_IRQS                               { LPDAC0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPDAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPI2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
+ * @{
+ */
+
+/** LPI2C - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t MCR;                               /**< Master Control Register, offset: 0x10 */
+  __IO uint32_t MSR;                               /**< Master Status Register, offset: 0x14 */
+  __IO uint32_t MIER;                              /**< Master Interrupt Enable Register, offset: 0x18 */
+  __IO uint32_t MDER;                              /**< Master DMA Enable Register, offset: 0x1C */
+  __IO uint32_t MCFGR0;                            /**< Master Configuration Register 0, offset: 0x20 */
+  __IO uint32_t MCFGR1;                            /**< Master Configuration Register 1, offset: 0x24 */
+  __IO uint32_t MCFGR2;                            /**< Master Configuration Register 2, offset: 0x28 */
+  __IO uint32_t MCFGR3;                            /**< Master Configuration Register 3, offset: 0x2C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t MDMR;                              /**< Master Data Match Register, offset: 0x40 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t MCCR0;                             /**< Master Clock Configuration Register 0, offset: 0x48 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t MCCR1;                             /**< Master Clock Configuration Register 1, offset: 0x50 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t MFCR;                              /**< Master FIFO Control Register, offset: 0x58 */
+  __I  uint32_t MFSR;                              /**< Master FIFO Status Register, offset: 0x5C */
+  __O  uint32_t MTDR;                              /**< Master Transmit Data Register, offset: 0x60 */
+       uint8_t RESERVED_5[12];
+  __I  uint32_t MRDR;                              /**< Master Receive Data Register, offset: 0x70 */
+       uint8_t RESERVED_6[156];
+  __IO uint32_t SCR;                               /**< Slave Control Register, offset: 0x110 */
+  __IO uint32_t SSR;                               /**< Slave Status Register, offset: 0x114 */
+  __IO uint32_t SIER;                              /**< Slave Interrupt Enable Register, offset: 0x118 */
+  __IO uint32_t SDER;                              /**< Slave DMA Enable Register, offset: 0x11C */
+       uint8_t RESERVED_7[4];
+  __IO uint32_t SCFGR1;                            /**< Slave Configuration Register 1, offset: 0x124 */
+  __IO uint32_t SCFGR2;                            /**< Slave Configuration Register 2, offset: 0x128 */
+       uint8_t RESERVED_8[20];
+  __IO uint32_t SAMR;                              /**< Slave Address Match Register, offset: 0x140 */
+       uint8_t RESERVED_9[12];
+  __I  uint32_t SASR;                              /**< Slave Address Status Register, offset: 0x150 */
+  __IO uint32_t STAR;                              /**< Slave Transmit ACK Register, offset: 0x154 */
+       uint8_t RESERVED_10[8];
+  __O  uint32_t STDR;                              /**< Slave Transmit Data Register, offset: 0x160 */
+       uint8_t RESERVED_11[12];
+  __I  uint32_t SRDR;                              /**< Slave Receive Data Register, offset: 0x170 */
+} LPI2C_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPI2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define LPI2C_VERID_FEATURE_MASK                 (0xFFFFU)
+#define LPI2C_VERID_FEATURE_SHIFT                (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000000000010..Master only, with standard feature set
+ *  0b0000000000000011..Master and slave, with standard feature set
+ */
+#define LPI2C_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
+#define LPI2C_VERID_MINOR_MASK                   (0xFF0000U)
+#define LPI2C_VERID_MINOR_SHIFT                  (16U)
+#define LPI2C_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
+#define LPI2C_VERID_MAJOR_MASK                   (0xFF000000U)
+#define LPI2C_VERID_MAJOR_SHIFT                  (24U)
+#define LPI2C_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define LPI2C_PARAM_MTXFIFO_MASK                 (0xFU)
+#define LPI2C_PARAM_MTXFIFO_SHIFT                (0U)
+#define LPI2C_PARAM_MTXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
+#define LPI2C_PARAM_MRXFIFO_MASK                 (0xF00U)
+#define LPI2C_PARAM_MRXFIFO_SHIFT                (8U)
+#define LPI2C_PARAM_MRXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
+/*! @} */
+
+/*! @name MCR - Master Control Register */
+/*! @{ */
+#define LPI2C_MCR_MEN_MASK                       (0x1U)
+#define LPI2C_MCR_MEN_SHIFT                      (0U)
+/*! MEN - Master Enable
+ *  0b0..Master logic is disabled
+ *  0b1..Master logic is enabled
+ */
+#define LPI2C_MCR_MEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
+#define LPI2C_MCR_RST_MASK                       (0x2U)
+#define LPI2C_MCR_RST_SHIFT                      (1U)
+/*! RST - Software Reset
+ *  0b0..Master logic is not reset
+ *  0b1..Master logic is reset
+ */
+#define LPI2C_MCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
+#define LPI2C_MCR_DOZEN_MASK                     (0x4U)
+#define LPI2C_MCR_DOZEN_SHIFT                    (2U)
+/*! DOZEN - Doze mode enable
+ *  0b0..Master is enabled in Doze mode
+ *  0b1..Master is disabled in Doze mode
+ */
+#define LPI2C_MCR_DOZEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
+#define LPI2C_MCR_DBGEN_MASK                     (0x8U)
+#define LPI2C_MCR_DBGEN_SHIFT                    (3U)
+/*! DBGEN - Debug Enable
+ *  0b0..Master is disabled in debug mode
+ *  0b1..Master is enabled in debug mode
+ */
+#define LPI2C_MCR_DBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
+#define LPI2C_MCR_RTF_MASK                       (0x100U)
+#define LPI2C_MCR_RTF_SHIFT                      (8U)
+/*! RTF - Reset Transmit FIFO
+ *  0b0..No effect
+ *  0b1..Transmit FIFO is reset
+ */
+#define LPI2C_MCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
+#define LPI2C_MCR_RRF_MASK                       (0x200U)
+#define LPI2C_MCR_RRF_SHIFT                      (9U)
+/*! RRF - Reset Receive FIFO
+ *  0b0..No effect
+ *  0b1..Receive FIFO is reset
+ */
+#define LPI2C_MCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
+/*! @} */
+
+/*! @name MSR - Master Status Register */
+/*! @{ */
+#define LPI2C_MSR_TDF_MASK                       (0x1U)
+#define LPI2C_MSR_TDF_SHIFT                      (0U)
+/*! TDF - Transmit Data Flag
+ *  0b0..Transmit data is not requested
+ *  0b1..Transmit data is requested
+ */
+#define LPI2C_MSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
+#define LPI2C_MSR_RDF_MASK                       (0x2U)
+#define LPI2C_MSR_RDF_SHIFT                      (1U)
+/*! RDF - Receive Data Flag
+ *  0b0..Receive Data is not ready
+ *  0b1..Receive data is ready
+ */
+#define LPI2C_MSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
+#define LPI2C_MSR_EPF_MASK                       (0x100U)
+#define LPI2C_MSR_EPF_SHIFT                      (8U)
+/*! EPF - End Packet Flag
+ *  0b0..Master has not generated a STOP or Repeated START condition
+ *  0b1..Master has generated a STOP or Repeated START condition
+ */
+#define LPI2C_MSR_EPF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
+#define LPI2C_MSR_SDF_MASK                       (0x200U)
+#define LPI2C_MSR_SDF_SHIFT                      (9U)
+/*! SDF - STOP Detect Flag
+ *  0b0..Master has not generated a STOP condition
+ *  0b1..Master has generated a STOP condition
+ */
+#define LPI2C_MSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
+#define LPI2C_MSR_NDF_MASK                       (0x400U)
+#define LPI2C_MSR_NDF_SHIFT                      (10U)
+/*! NDF - NACK Detect Flag
+ *  0b0..Unexpected NACK was not detected
+ *  0b1..Unexpected NACK was detected
+ */
+#define LPI2C_MSR_NDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
+#define LPI2C_MSR_ALF_MASK                       (0x800U)
+#define LPI2C_MSR_ALF_SHIFT                      (11U)
+/*! ALF - Arbitration Lost Flag
+ *  0b0..Master has not lost arbitration
+ *  0b1..Master has lost arbitration
+ */
+#define LPI2C_MSR_ALF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
+#define LPI2C_MSR_FEF_MASK                       (0x1000U)
+#define LPI2C_MSR_FEF_SHIFT                      (12U)
+/*! FEF - FIFO Error Flag
+ *  0b0..No error
+ *  0b1..Master sending or receiving data without a START condition
+ */
+#define LPI2C_MSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
+#define LPI2C_MSR_PLTF_MASK                      (0x2000U)
+#define LPI2C_MSR_PLTF_SHIFT                     (13U)
+/*! PLTF - Pin Low Timeout Flag
+ *  0b0..Pin low timeout has not occurred or is disabled
+ *  0b1..Pin low timeout has occurred
+ */
+#define LPI2C_MSR_PLTF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
+#define LPI2C_MSR_DMF_MASK                       (0x4000U)
+#define LPI2C_MSR_DMF_SHIFT                      (14U)
+/*! DMF - Data Match Flag
+ *  0b0..Have not received matching data
+ *  0b1..Have received matching data
+ */
+#define LPI2C_MSR_DMF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
+#define LPI2C_MSR_MBF_MASK                       (0x1000000U)
+#define LPI2C_MSR_MBF_SHIFT                      (24U)
+/*! MBF - Master Busy Flag
+ *  0b0..I2C Master is idle
+ *  0b1..I2C Master is busy
+ */
+#define LPI2C_MSR_MBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
+#define LPI2C_MSR_BBF_MASK                       (0x2000000U)
+#define LPI2C_MSR_BBF_SHIFT                      (25U)
+/*! BBF - Bus Busy Flag
+ *  0b0..I2C Bus is idle
+ *  0b1..I2C Bus is busy
+ */
+#define LPI2C_MSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
+/*! @} */
+
+/*! @name MIER - Master Interrupt Enable Register */
+/*! @{ */
+#define LPI2C_MIER_TDIE_MASK                     (0x1U)
+#define LPI2C_MIER_TDIE_SHIFT                    (0U)
+/*! TDIE - Transmit Data Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_MIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
+#define LPI2C_MIER_RDIE_MASK                     (0x2U)
+#define LPI2C_MIER_RDIE_SHIFT                    (1U)
+/*! RDIE - Receive Data Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_MIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
+#define LPI2C_MIER_EPIE_MASK                     (0x100U)
+#define LPI2C_MIER_EPIE_SHIFT                    (8U)
+/*! EPIE - End Packet Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_MIER_EPIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
+#define LPI2C_MIER_SDIE_MASK                     (0x200U)
+#define LPI2C_MIER_SDIE_SHIFT                    (9U)
+/*! SDIE - STOP Detect Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_MIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
+#define LPI2C_MIER_NDIE_MASK                     (0x400U)
+#define LPI2C_MIER_NDIE_SHIFT                    (10U)
+/*! NDIE - NACK Detect Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_MIER_NDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
+#define LPI2C_MIER_ALIE_MASK                     (0x800U)
+#define LPI2C_MIER_ALIE_SHIFT                    (11U)
+/*! ALIE - Arbitration Lost Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_MIER_ALIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
+#define LPI2C_MIER_FEIE_MASK                     (0x1000U)
+#define LPI2C_MIER_FEIE_SHIFT                    (12U)
+/*! FEIE - FIFO Error Interrupt Enable
+ *  0b0..Enabled
+ *  0b1..Disabled
+ */
+#define LPI2C_MIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
+#define LPI2C_MIER_PLTIE_MASK                    (0x2000U)
+#define LPI2C_MIER_PLTIE_SHIFT                   (13U)
+/*! PLTIE - Pin Low Timeout Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_MIER_PLTIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
+#define LPI2C_MIER_DMIE_MASK                     (0x4000U)
+#define LPI2C_MIER_DMIE_SHIFT                    (14U)
+/*! DMIE - Data Match Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_MIER_DMIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
+/*! @} */
+
+/*! @name MDER - Master DMA Enable Register */
+/*! @{ */
+#define LPI2C_MDER_TDDE_MASK                     (0x1U)
+#define LPI2C_MDER_TDDE_SHIFT                    (0U)
+/*! TDDE - Transmit Data DMA Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
+#define LPI2C_MDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
+#define LPI2C_MDER_RDDE_MASK                     (0x2U)
+#define LPI2C_MDER_RDDE_SHIFT                    (1U)
+/*! RDDE - Receive Data DMA Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
+#define LPI2C_MDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
+/*! @} */
+
+/*! @name MCFGR0 - Master Configuration Register 0 */
+/*! @{ */
+#define LPI2C_MCFGR0_HREN_MASK                   (0x1U)
+#define LPI2C_MCFGR0_HREN_SHIFT                  (0U)
+/*! HREN - Host Request Enable
+ *  0b0..Host request input is disabled
+ *  0b1..Host request input is enabled
+ */
+#define LPI2C_MCFGR0_HREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
+#define LPI2C_MCFGR0_HRPOL_MASK                  (0x2U)
+#define LPI2C_MCFGR0_HRPOL_SHIFT                 (1U)
+/*! HRPOL - Host Request Polarity
+ *  0b0..Active low
+ *  0b1..Active high
+ */
+#define LPI2C_MCFGR0_HRPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
+#define LPI2C_MCFGR0_HRSEL_MASK                  (0x4U)
+#define LPI2C_MCFGR0_HRSEL_SHIFT                 (2U)
+/*! HRSEL - Host Request Select
+ *  0b0..Host request input is pin HREQ
+ *  0b1..Host request input is input trigger
+ */
+#define LPI2C_MCFGR0_HRSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
+#define LPI2C_MCFGR0_CIRFIFO_MASK                (0x100U)
+#define LPI2C_MCFGR0_CIRFIFO_SHIFT               (8U)
+/*! CIRFIFO - Circular FIFO Enable
+ *  0b0..Circular FIFO is disabled
+ *  0b1..Circular FIFO is enabled
+ */
+#define LPI2C_MCFGR0_CIRFIFO(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
+#define LPI2C_MCFGR0_RDMO_MASK                   (0x200U)
+#define LPI2C_MCFGR0_RDMO_SHIFT                  (9U)
+/*! RDMO - Receive Data Match Only
+ *  0b0..Received data is stored in the receive FIFO
+ *  0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set
+ */
+#define LPI2C_MCFGR0_RDMO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
+/*! @} */
+
+/*! @name MCFGR1 - Master Configuration Register 1 */
+/*! @{ */
+#define LPI2C_MCFGR1_PRESCALE_MASK               (0x7U)
+#define LPI2C_MCFGR1_PRESCALE_SHIFT              (0U)
+/*! PRESCALE - Prescaler
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 4
+ *  0b011..Divide by 8
+ *  0b100..Divide by 16
+ *  0b101..Divide by 32
+ *  0b110..Divide by 64
+ *  0b111..Divide by 128
+ */
+#define LPI2C_MCFGR1_PRESCALE(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
+#define LPI2C_MCFGR1_AUTOSTOP_MASK               (0x100U)
+#define LPI2C_MCFGR1_AUTOSTOP_SHIFT              (8U)
+/*! AUTOSTOP - Automatic STOP Generation
+ *  0b0..No effect
+ *  0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy
+ */
+#define LPI2C_MCFGR1_AUTOSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
+#define LPI2C_MCFGR1_IGNACK_MASK                 (0x200U)
+#define LPI2C_MCFGR1_IGNACK_SHIFT                (9U)
+/*! IGNACK - IGNACK
+ *  0b0..LPI2C Master will receive ACK and NACK normally
+ *  0b1..LPI2C Master will treat a received NACK as if it (NACK) was an ACK
+ */
+#define LPI2C_MCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
+#define LPI2C_MCFGR1_TIMECFG_MASK                (0x400U)
+#define LPI2C_MCFGR1_TIMECFG_SHIFT               (10U)
+/*! TIMECFG - Timeout Configuration
+ *  0b0..Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout
+ *  0b1..Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout
+ */
+#define LPI2C_MCFGR1_TIMECFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
+#define LPI2C_MCFGR1_MATCFG_MASK                 (0x70000U)
+#define LPI2C_MCFGR1_MATCFG_SHIFT                (16U)
+/*! MATCFG - Match Configuration
+ *  0b000..Match is disabled
+ *  0b001..Reserved
+ *  0b010..Match is enabled (1st data word equals MATCH0 OR MATCH1)
+ *  0b011..Match is enabled (any data word equals MATCH0 OR MATCH1)
+ *  0b100..Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1)
+ *  0b101..Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1)
+ *  0b110..Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1)
+ *  0b111..Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1)
+ */
+#define LPI2C_MCFGR1_MATCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
+#define LPI2C_MCFGR1_PINCFG_MASK                 (0x7000000U)
+#define LPI2C_MCFGR1_PINCFG_SHIFT                (24U)
+/*! PINCFG - Pin Configuration
+ *  0b000..2-pin open drain mode
+ *  0b001..2-pin output only mode (ultra-fast mode)
+ *  0b010..2-pin push-pull mode
+ *  0b011..4-pin push-pull mode
+ *  0b100..2-pin open drain mode with separate LPI2C slave
+ *  0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave
+ *  0b110..2-pin push-pull mode with separate LPI2C slave
+ *  0b111..4-pin push-pull mode (inverted outputs)
+ */
+#define LPI2C_MCFGR1_PINCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
+/*! @} */
+
+/*! @name MCFGR2 - Master Configuration Register 2 */
+/*! @{ */
+#define LPI2C_MCFGR2_BUSIDLE_MASK                (0xFFFU)
+#define LPI2C_MCFGR2_BUSIDLE_SHIFT               (0U)
+#define LPI2C_MCFGR2_BUSIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
+#define LPI2C_MCFGR2_FILTSCL_MASK                (0xF0000U)
+#define LPI2C_MCFGR2_FILTSCL_SHIFT               (16U)
+#define LPI2C_MCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
+#define LPI2C_MCFGR2_FILTSDA_MASK                (0xF000000U)
+#define LPI2C_MCFGR2_FILTSDA_SHIFT               (24U)
+#define LPI2C_MCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
+/*! @} */
+
+/*! @name MCFGR3 - Master Configuration Register 3 */
+/*! @{ */
+#define LPI2C_MCFGR3_PINLOW_MASK                 (0xFFF00U)
+#define LPI2C_MCFGR3_PINLOW_SHIFT                (8U)
+#define LPI2C_MCFGR3_PINLOW(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
+/*! @} */
+
+/*! @name MDMR - Master Data Match Register */
+/*! @{ */
+#define LPI2C_MDMR_MATCH0_MASK                   (0xFFU)
+#define LPI2C_MDMR_MATCH0_SHIFT                  (0U)
+#define LPI2C_MDMR_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
+#define LPI2C_MDMR_MATCH1_MASK                   (0xFF0000U)
+#define LPI2C_MDMR_MATCH1_SHIFT                  (16U)
+#define LPI2C_MDMR_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
+/*! @} */
+
+/*! @name MCCR0 - Master Clock Configuration Register 0 */
+/*! @{ */
+#define LPI2C_MCCR0_CLKLO_MASK                   (0x3FU)
+#define LPI2C_MCCR0_CLKLO_SHIFT                  (0U)
+#define LPI2C_MCCR0_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
+#define LPI2C_MCCR0_CLKHI_MASK                   (0x3F00U)
+#define LPI2C_MCCR0_CLKHI_SHIFT                  (8U)
+#define LPI2C_MCCR0_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
+#define LPI2C_MCCR0_SETHOLD_MASK                 (0x3F0000U)
+#define LPI2C_MCCR0_SETHOLD_SHIFT                (16U)
+#define LPI2C_MCCR0_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
+#define LPI2C_MCCR0_DATAVD_MASK                  (0x3F000000U)
+#define LPI2C_MCCR0_DATAVD_SHIFT                 (24U)
+#define LPI2C_MCCR0_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
+/*! @} */
+
+/*! @name MCCR1 - Master Clock Configuration Register 1 */
+/*! @{ */
+#define LPI2C_MCCR1_CLKLO_MASK                   (0x3FU)
+#define LPI2C_MCCR1_CLKLO_SHIFT                  (0U)
+#define LPI2C_MCCR1_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
+#define LPI2C_MCCR1_CLKHI_MASK                   (0x3F00U)
+#define LPI2C_MCCR1_CLKHI_SHIFT                  (8U)
+#define LPI2C_MCCR1_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
+#define LPI2C_MCCR1_SETHOLD_MASK                 (0x3F0000U)
+#define LPI2C_MCCR1_SETHOLD_SHIFT                (16U)
+#define LPI2C_MCCR1_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
+#define LPI2C_MCCR1_DATAVD_MASK                  (0x3F000000U)
+#define LPI2C_MCCR1_DATAVD_SHIFT                 (24U)
+#define LPI2C_MCCR1_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
+/*! @} */
+
+/*! @name MFCR - Master FIFO Control Register */
+/*! @{ */
+#define LPI2C_MFCR_TXWATER_MASK                  (0x3U)
+#define LPI2C_MFCR_TXWATER_SHIFT                 (0U)
+#define LPI2C_MFCR_TXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
+#define LPI2C_MFCR_RXWATER_MASK                  (0x30000U)
+#define LPI2C_MFCR_RXWATER_SHIFT                 (16U)
+#define LPI2C_MFCR_RXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
+/*! @} */
+
+/*! @name MFSR - Master FIFO Status Register */
+/*! @{ */
+#define LPI2C_MFSR_TXCOUNT_MASK                  (0x7U)
+#define LPI2C_MFSR_TXCOUNT_SHIFT                 (0U)
+#define LPI2C_MFSR_TXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
+#define LPI2C_MFSR_RXCOUNT_MASK                  (0x70000U)
+#define LPI2C_MFSR_RXCOUNT_SHIFT                 (16U)
+#define LPI2C_MFSR_RXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
+/*! @} */
+
+/*! @name MTDR - Master Transmit Data Register */
+/*! @{ */
+#define LPI2C_MTDR_DATA_MASK                     (0xFFU)
+#define LPI2C_MTDR_DATA_SHIFT                    (0U)
+#define LPI2C_MTDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
+#define LPI2C_MTDR_CMD_MASK                      (0x700U)
+#define LPI2C_MTDR_CMD_SHIFT                     (8U)
+/*! CMD - Command Data
+ *  0b000..Transmit DATA[7:0]
+ *  0b001..Receive (DATA[7:0] + 1) bytes
+ *  0b010..Generate STOP condition
+ *  0b011..Receive and discard (DATA[7:0] + 1) bytes
+ *  0b100..Generate (repeated) START and transmit address in DATA[7:0]
+ *  0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned.
+ *  0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode
+ *  0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.
+ */
+#define LPI2C_MTDR_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
+/*! @} */
+
+/*! @name MRDR - Master Receive Data Register */
+/*! @{ */
+#define LPI2C_MRDR_DATA_MASK                     (0xFFU)
+#define LPI2C_MRDR_DATA_SHIFT                    (0U)
+#define LPI2C_MRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
+#define LPI2C_MRDR_RXEMPTY_MASK                  (0x4000U)
+#define LPI2C_MRDR_RXEMPTY_SHIFT                 (14U)
+/*! RXEMPTY - RX Empty
+ *  0b0..Receive FIFO is not empty
+ *  0b1..Receive FIFO is empty
+ */
+#define LPI2C_MRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
+/*! @} */
+
+/*! @name SCR - Slave Control Register */
+/*! @{ */
+#define LPI2C_SCR_SEN_MASK                       (0x1U)
+#define LPI2C_SCR_SEN_SHIFT                      (0U)
+/*! SEN - Slave Enable
+ *  0b0..I2C Slave mode is disabled
+ *  0b1..I2C Slave mode is enabled
+ */
+#define LPI2C_SCR_SEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
+#define LPI2C_SCR_RST_MASK                       (0x2U)
+#define LPI2C_SCR_RST_SHIFT                      (1U)
+/*! RST - Software Reset
+ *  0b0..Slave mode logic is not reset
+ *  0b1..Slave mode logic is reset
+ */
+#define LPI2C_SCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
+#define LPI2C_SCR_FILTEN_MASK                    (0x10U)
+#define LPI2C_SCR_FILTEN_SHIFT                   (4U)
+/*! FILTEN - Filter Enable
+ *  0b0..Disable digital filter and output delay counter for slave mode
+ *  0b1..Enable digital filter and output delay counter for slave mode
+ */
+#define LPI2C_SCR_FILTEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
+#define LPI2C_SCR_FILTDZ_MASK                    (0x20U)
+#define LPI2C_SCR_FILTDZ_SHIFT                   (5U)
+/*! FILTDZ - Filter Doze Enable
+ *  0b0..Filter remains enabled in Doze mode
+ *  0b1..Filter is disabled in Doze mode
+ */
+#define LPI2C_SCR_FILTDZ(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
+#define LPI2C_SCR_RTF_MASK                       (0x100U)
+#define LPI2C_SCR_RTF_SHIFT                      (8U)
+/*! RTF - Reset Transmit FIFO
+ *  0b0..No effect
+ *  0b1..Transmit Data Register is now empty
+ */
+#define LPI2C_SCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
+#define LPI2C_SCR_RRF_MASK                       (0x200U)
+#define LPI2C_SCR_RRF_SHIFT                      (9U)
+/*! RRF - Reset Receive FIFO
+ *  0b0..No effect
+ *  0b1..Receive Data Register is now empty
+ */
+#define LPI2C_SCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
+/*! @} */
+
+/*! @name SSR - Slave Status Register */
+/*! @{ */
+#define LPI2C_SSR_TDF_MASK                       (0x1U)
+#define LPI2C_SSR_TDF_SHIFT                      (0U)
+/*! TDF - Transmit Data Flag
+ *  0b0..Transmit data not requested
+ *  0b1..Transmit data is requested
+ */
+#define LPI2C_SSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
+#define LPI2C_SSR_RDF_MASK                       (0x2U)
+#define LPI2C_SSR_RDF_SHIFT                      (1U)
+/*! RDF - Receive Data Flag
+ *  0b0..Receive data is not ready
+ *  0b1..Receive data is ready
+ */
+#define LPI2C_SSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
+#define LPI2C_SSR_AVF_MASK                       (0x4U)
+#define LPI2C_SSR_AVF_SHIFT                      (2U)
+/*! AVF - Address Valid Flag
+ *  0b0..Address Status Register is not valid
+ *  0b1..Address Status Register is valid
+ */
+#define LPI2C_SSR_AVF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
+#define LPI2C_SSR_TAF_MASK                       (0x8U)
+#define LPI2C_SSR_TAF_SHIFT                      (3U)
+/*! TAF - Transmit ACK Flag
+ *  0b0..Transmit ACK/NACK is not required
+ *  0b1..Transmit ACK/NACK is required
+ */
+#define LPI2C_SSR_TAF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
+#define LPI2C_SSR_RSF_MASK                       (0x100U)
+#define LPI2C_SSR_RSF_SHIFT                      (8U)
+/*! RSF - Repeated Start Flag
+ *  0b0..Slave has not detected a Repeated START condition
+ *  0b1..Slave has detected a Repeated START condition
+ */
+#define LPI2C_SSR_RSF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
+#define LPI2C_SSR_SDF_MASK                       (0x200U)
+#define LPI2C_SSR_SDF_SHIFT                      (9U)
+/*! SDF - STOP Detect Flag
+ *  0b0..Slave has not detected a STOP condition
+ *  0b1..Slave has detected a STOP condition
+ */
+#define LPI2C_SSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
+#define LPI2C_SSR_BEF_MASK                       (0x400U)
+#define LPI2C_SSR_BEF_SHIFT                      (10U)
+/*! BEF - Bit Error Flag
+ *  0b0..Slave has not detected a bit error
+ *  0b1..Slave has detected a bit error
+ */
+#define LPI2C_SSR_BEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
+#define LPI2C_SSR_FEF_MASK                       (0x800U)
+#define LPI2C_SSR_FEF_SHIFT                      (11U)
+/*! FEF - FIFO Error Flag
+ *  0b0..FIFO underflow or overflow was not detected
+ *  0b1..FIFO underflow or overflow was detected
+ */
+#define LPI2C_SSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
+#define LPI2C_SSR_AM0F_MASK                      (0x1000U)
+#define LPI2C_SSR_AM0F_SHIFT                     (12U)
+/*! AM0F - Address Match 0 Flag
+ *  0b0..Have not received an ADDR0 matching address
+ *  0b1..Have received an ADDR0 matching address
+ */
+#define LPI2C_SSR_AM0F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
+#define LPI2C_SSR_AM1F_MASK                      (0x2000U)
+#define LPI2C_SSR_AM1F_SHIFT                     (13U)
+/*! AM1F - Address Match 1 Flag
+ *  0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address
+ *  0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address
+ */
+#define LPI2C_SSR_AM1F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
+#define LPI2C_SSR_GCF_MASK                       (0x4000U)
+#define LPI2C_SSR_GCF_SHIFT                      (14U)
+/*! GCF - General Call Flag
+ *  0b0..Slave has not detected the General Call Address or the General Call Address is disabled
+ *  0b1..Slave has detected the General Call Address
+ */
+#define LPI2C_SSR_GCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
+#define LPI2C_SSR_SARF_MASK                      (0x8000U)
+#define LPI2C_SSR_SARF_SHIFT                     (15U)
+/*! SARF - SMBus Alert Response Flag
+ *  0b0..SMBus Alert Response is disabled or not detected
+ *  0b1..SMBus Alert Response is enabled and detected
+ */
+#define LPI2C_SSR_SARF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
+#define LPI2C_SSR_SBF_MASK                       (0x1000000U)
+#define LPI2C_SSR_SBF_SHIFT                      (24U)
+/*! SBF - Slave Busy Flag
+ *  0b0..I2C Slave is idle
+ *  0b1..I2C Slave is busy
+ */
+#define LPI2C_SSR_SBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
+#define LPI2C_SSR_BBF_MASK                       (0x2000000U)
+#define LPI2C_SSR_BBF_SHIFT                      (25U)
+/*! BBF - Bus Busy Flag
+ *  0b0..I2C Bus is idle
+ *  0b1..I2C Bus is busy
+ */
+#define LPI2C_SSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
+/*! @} */
+
+/*! @name SIER - Slave Interrupt Enable Register */
+/*! @{ */
+#define LPI2C_SIER_TDIE_MASK                     (0x1U)
+#define LPI2C_SIER_TDIE_SHIFT                    (0U)
+/*! TDIE - Transmit Data Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_SIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
+#define LPI2C_SIER_RDIE_MASK                     (0x2U)
+#define LPI2C_SIER_RDIE_SHIFT                    (1U)
+/*! RDIE - Receive Data Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_SIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
+#define LPI2C_SIER_AVIE_MASK                     (0x4U)
+#define LPI2C_SIER_AVIE_SHIFT                    (2U)
+/*! AVIE - Address Valid Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_SIER_AVIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
+#define LPI2C_SIER_TAIE_MASK                     (0x8U)
+#define LPI2C_SIER_TAIE_SHIFT                    (3U)
+/*! TAIE - Transmit ACK Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_SIER_TAIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
+#define LPI2C_SIER_RSIE_MASK                     (0x100U)
+#define LPI2C_SIER_RSIE_SHIFT                    (8U)
+/*! RSIE - Repeated Start Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_SIER_RSIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
+#define LPI2C_SIER_SDIE_MASK                     (0x200U)
+#define LPI2C_SIER_SDIE_SHIFT                    (9U)
+/*! SDIE - STOP Detect Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_SIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
+#define LPI2C_SIER_BEIE_MASK                     (0x400U)
+#define LPI2C_SIER_BEIE_SHIFT                    (10U)
+/*! BEIE - Bit Error Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_SIER_BEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
+#define LPI2C_SIER_FEIE_MASK                     (0x800U)
+#define LPI2C_SIER_FEIE_SHIFT                    (11U)
+/*! FEIE - FIFO Error Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_SIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
+#define LPI2C_SIER_AM0IE_MASK                    (0x1000U)
+#define LPI2C_SIER_AM0IE_SHIFT                   (12U)
+/*! AM0IE - Address Match 0 Interrupt Enable
+ *  0b0..Enabled
+ *  0b1..Disabled
+ */
+#define LPI2C_SIER_AM0IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
+#define LPI2C_SIER_AM1F_MASK                     (0x2000U)
+#define LPI2C_SIER_AM1F_SHIFT                    (13U)
+/*! AM1F - Address Match 1 Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_SIER_AM1F(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)
+#define LPI2C_SIER_GCIE_MASK                     (0x4000U)
+#define LPI2C_SIER_GCIE_SHIFT                    (14U)
+/*! GCIE - General Call Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_SIER_GCIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
+#define LPI2C_SIER_SARIE_MASK                    (0x8000U)
+#define LPI2C_SIER_SARIE_SHIFT                   (15U)
+/*! SARIE - SMBus Alert Response Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_SIER_SARIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
+/*! @} */
+
+/*! @name SDER - Slave DMA Enable Register */
+/*! @{ */
+#define LPI2C_SDER_TDDE_MASK                     (0x1U)
+#define LPI2C_SDER_TDDE_SHIFT                    (0U)
+/*! TDDE - Transmit Data DMA Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
+#define LPI2C_SDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
+#define LPI2C_SDER_RDDE_MASK                     (0x2U)
+#define LPI2C_SDER_RDDE_SHIFT                    (1U)
+/*! RDDE - Receive Data DMA Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
+#define LPI2C_SDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
+#define LPI2C_SDER_AVDE_MASK                     (0x4U)
+#define LPI2C_SDER_AVDE_SHIFT                    (2U)
+/*! AVDE - Address Valid DMA Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
+#define LPI2C_SDER_AVDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
+/*! @} */
+
+/*! @name SCFGR1 - Slave Configuration Register 1 */
+/*! @{ */
+#define LPI2C_SCFGR1_ADRSTALL_MASK               (0x1U)
+#define LPI2C_SCFGR1_ADRSTALL_SHIFT              (0U)
+/*! ADRSTALL - Address SCL Stall
+ *  0b0..Clock stretching is disabled
+ *  0b1..Clock stretching is enabled
+ */
+#define LPI2C_SCFGR1_ADRSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
+#define LPI2C_SCFGR1_RXSTALL_MASK                (0x2U)
+#define LPI2C_SCFGR1_RXSTALL_SHIFT               (1U)
+/*! RXSTALL - RX SCL Stall
+ *  0b0..Clock stretching is disabled
+ *  0b1..Clock stretching is enabled
+ */
+#define LPI2C_SCFGR1_RXSTALL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
+#define LPI2C_SCFGR1_TXDSTALL_MASK               (0x4U)
+#define LPI2C_SCFGR1_TXDSTALL_SHIFT              (2U)
+/*! TXDSTALL - TX Data SCL Stall
+ *  0b0..Clock stretching is disabled
+ *  0b1..Clock stretching is enabled
+ */
+#define LPI2C_SCFGR1_TXDSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
+#define LPI2C_SCFGR1_ACKSTALL_MASK               (0x8U)
+#define LPI2C_SCFGR1_ACKSTALL_SHIFT              (3U)
+/*! ACKSTALL - ACK SCL Stall
+ *  0b0..Clock stretching is disabled
+ *  0b1..Clock stretching is enabled
+ */
+#define LPI2C_SCFGR1_ACKSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
+#define LPI2C_SCFGR1_GCEN_MASK                   (0x100U)
+#define LPI2C_SCFGR1_GCEN_SHIFT                  (8U)
+/*! GCEN - General Call Enable
+ *  0b0..General Call address is disabled
+ *  0b1..General Call address is enabled
+ */
+#define LPI2C_SCFGR1_GCEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
+#define LPI2C_SCFGR1_SAEN_MASK                   (0x200U)
+#define LPI2C_SCFGR1_SAEN_SHIFT                  (9U)
+/*! SAEN - SMBus Alert Enable
+ *  0b0..Disables match on SMBus Alert
+ *  0b1..Enables match on SMBus Alert
+ */
+#define LPI2C_SCFGR1_SAEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
+#define LPI2C_SCFGR1_TXCFG_MASK                  (0x400U)
+#define LPI2C_SCFGR1_TXCFG_SHIFT                 (10U)
+/*! TXCFG - Transmit Flag Configuration
+ *  0b0..Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty
+ *  0b1..Transmit Data Flag will assert whenever the Transmit Data register is empty
+ */
+#define LPI2C_SCFGR1_TXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
+#define LPI2C_SCFGR1_RXCFG_MASK                  (0x800U)
+#define LPI2C_SCFGR1_RXCFG_SHIFT                 (11U)
+/*! RXCFG - Receive Data Configuration
+ *  0b0..Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]).
+ *  0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]).
+ */
+#define LPI2C_SCFGR1_RXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
+#define LPI2C_SCFGR1_IGNACK_MASK                 (0x1000U)
+#define LPI2C_SCFGR1_IGNACK_SHIFT                (12U)
+/*! IGNACK - Ignore NACK
+ *  0b0..Slave will end transfer when NACK is detected
+ *  0b1..Slave will not end transfer when NACK detected
+ */
+#define LPI2C_SCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
+#define LPI2C_SCFGR1_HSMEN_MASK                  (0x2000U)
+#define LPI2C_SCFGR1_HSMEN_SHIFT                 (13U)
+/*! HSMEN - High Speed Mode Enable
+ *  0b0..Disables detection of HS-mode master code
+ *  0b1..Enables detection of HS-mode master code
+ */
+#define LPI2C_SCFGR1_HSMEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
+#define LPI2C_SCFGR1_ADDRCFG_MASK                (0x70000U)
+#define LPI2C_SCFGR1_ADDRCFG_SHIFT               (16U)
+/*! ADDRCFG - Address Configuration
+ *  0b000..Address match 0 (7-bit)
+ *  0b001..Address match 0 (10-bit)
+ *  0b010..Address match 0 (7-bit) or Address match 1 (7-bit)
+ *  0b011..Address match 0 (10-bit) or Address match 1 (10-bit)
+ *  0b100..Address match 0 (7-bit) or Address match 1 (10-bit)
+ *  0b101..Address match 0 (10-bit) or Address match 1 (7-bit)
+ *  0b110..From Address match 0 (7-bit) to Address match 1 (7-bit)
+ *  0b111..From Address match 0 (10-bit) to Address match 1 (10-bit)
+ */
+#define LPI2C_SCFGR1_ADDRCFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
+/*! @} */
+
+/*! @name SCFGR2 - Slave Configuration Register 2 */
+/*! @{ */
+#define LPI2C_SCFGR2_CLKHOLD_MASK                (0xFU)
+#define LPI2C_SCFGR2_CLKHOLD_SHIFT               (0U)
+#define LPI2C_SCFGR2_CLKHOLD(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
+#define LPI2C_SCFGR2_DATAVD_MASK                 (0x3F00U)
+#define LPI2C_SCFGR2_DATAVD_SHIFT                (8U)
+#define LPI2C_SCFGR2_DATAVD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
+#define LPI2C_SCFGR2_FILTSCL_MASK                (0xF0000U)
+#define LPI2C_SCFGR2_FILTSCL_SHIFT               (16U)
+#define LPI2C_SCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
+#define LPI2C_SCFGR2_FILTSDA_MASK                (0xF000000U)
+#define LPI2C_SCFGR2_FILTSDA_SHIFT               (24U)
+#define LPI2C_SCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
+/*! @} */
+
+/*! @name SAMR - Slave Address Match Register */
+/*! @{ */
+#define LPI2C_SAMR_ADDR0_MASK                    (0x7FEU)
+#define LPI2C_SAMR_ADDR0_SHIFT                   (1U)
+#define LPI2C_SAMR_ADDR0(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
+#define LPI2C_SAMR_ADDR1_MASK                    (0x7FE0000U)
+#define LPI2C_SAMR_ADDR1_SHIFT                   (17U)
+#define LPI2C_SAMR_ADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
+/*! @} */
+
+/*! @name SASR - Slave Address Status Register */
+/*! @{ */
+#define LPI2C_SASR_RADDR_MASK                    (0x7FFU)
+#define LPI2C_SASR_RADDR_SHIFT                   (0U)
+#define LPI2C_SASR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
+#define LPI2C_SASR_ANV_MASK                      (0x4000U)
+#define LPI2C_SASR_ANV_SHIFT                     (14U)
+/*! ANV - Address Not Valid
+ *  0b0..Received Address (RADDR) is valid
+ *  0b1..Received Address (RADDR) is not valid
+ */
+#define LPI2C_SASR_ANV(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
+/*! @} */
+
+/*! @name STAR - Slave Transmit ACK Register */
+/*! @{ */
+#define LPI2C_STAR_TXNACK_MASK                   (0x1U)
+#define LPI2C_STAR_TXNACK_SHIFT                  (0U)
+/*! TXNACK - Transmit NACK
+ *  0b0..Write a Transmit ACK for each received word
+ *  0b1..Write a Transmit NACK for each received word
+ */
+#define LPI2C_STAR_TXNACK(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
+/*! @} */
+
+/*! @name STDR - Slave Transmit Data Register */
+/*! @{ */
+#define LPI2C_STDR_DATA_MASK                     (0xFFU)
+#define LPI2C_STDR_DATA_SHIFT                    (0U)
+#define LPI2C_STDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
+/*! @} */
+
+/*! @name SRDR - Slave Receive Data Register */
+/*! @{ */
+#define LPI2C_SRDR_DATA_MASK                     (0xFFU)
+#define LPI2C_SRDR_DATA_SHIFT                    (0U)
+#define LPI2C_SRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
+#define LPI2C_SRDR_RXEMPTY_MASK                  (0x4000U)
+#define LPI2C_SRDR_RXEMPTY_SHIFT                 (14U)
+/*! RXEMPTY - RX Empty
+ *  0b0..The Receive Data Register is not empty
+ *  0b1..The Receive Data Register is empty
+ */
+#define LPI2C_SRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
+#define LPI2C_SRDR_SOF_MASK                      (0x8000U)
+#define LPI2C_SRDR_SOF_SHIFT                     (15U)
+/*! SOF - Start Of Frame
+ *  0b0..Indicates this is not the first data word since a (repeated) START or STOP condition
+ *  0b1..Indicates this is the first data word since a (repeated) START or STOP condition
+ */
+#define LPI2C_SRDR_SOF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LPI2C_Register_Masks */
+
+
+/* LPI2C - Peripheral instance base addresses */
+/** Peripheral LPI2C0 base address */
+#define LPI2C0_BASE                              (0x4003A000u)
+/** Peripheral LPI2C0 base pointer */
+#define LPI2C0                                   ((LPI2C_Type *)LPI2C0_BASE)
+/** Peripheral LPI2C1 base address */
+#define LPI2C1_BASE                              (0x4003B000u)
+/** Peripheral LPI2C1 base pointer */
+#define LPI2C1                                   ((LPI2C_Type *)LPI2C1_BASE)
+/** Peripheral LPI2C2 base address */
+#define LPI2C2_BASE                              (0x4003C000u)
+/** Peripheral LPI2C2 base pointer */
+#define LPI2C2                                   ((LPI2C_Type *)LPI2C2_BASE)
+/** Peripheral LPI2C3 base address */
+#define LPI2C3_BASE                              (0x4102E000u)
+/** Peripheral LPI2C3 base pointer */
+#define LPI2C3                                   ((LPI2C_Type *)LPI2C3_BASE)
+/** Array initializer of LPI2C peripheral base addresses */
+#define LPI2C_BASE_ADDRS                         { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE }
+/** Array initializer of LPI2C peripheral base pointers */
+#define LPI2C_BASE_PTRS                          { LPI2C0, LPI2C1, LPI2C2, LPI2C3 }
+/** Interrupt vectors for the LPI2C peripheral type */
+#define LPI2C_IRQS                               { LPI2C0_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPI2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPIT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPIT_Peripheral_Access_Layer LPIT Peripheral Access Layer
+ * @{
+ */
+
+/** LPIT - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __IO uint32_t MCR;                               /**< Module Control Register, offset: 0x8 */
+  __IO uint32_t MSR;                               /**< Module Status Register, offset: 0xC */
+  __IO uint32_t MIER;                              /**< Module Interrupt Enable Register, offset: 0x10 */
+  __IO uint32_t SETTEN;                            /**< Set Timer Enable Register, offset: 0x14 */
+  __O  uint32_t CLRTEN;                            /**< Clear Timer Enable Register, offset: 0x18 */
+       uint8_t RESERVED_0[4];
+  struct {                                         /* offset: 0x20, array step: 0x10 */
+    __IO uint32_t TVAL;                              /**< Timer Value Register, array offset: 0x20, array step: 0x10 */
+    __I  uint32_t CVAL;                              /**< Current Timer Value, array offset: 0x24, array step: 0x10 */
+    __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x28, array step: 0x10 */
+         uint8_t RESERVED_0[4];
+  } CHANNEL[4];
+} LPIT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPIT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPIT_Register_Masks LPIT Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define LPIT_VERID_FEATURE_MASK                  (0xFFFFU)
+#define LPIT_VERID_FEATURE_SHIFT                 (0U)
+#define LPIT_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_FEATURE_SHIFT)) & LPIT_VERID_FEATURE_MASK)
+#define LPIT_VERID_MINOR_MASK                    (0xFF0000U)
+#define LPIT_VERID_MINOR_SHIFT                   (16U)
+#define LPIT_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MINOR_SHIFT)) & LPIT_VERID_MINOR_MASK)
+#define LPIT_VERID_MAJOR_MASK                    (0xFF000000U)
+#define LPIT_VERID_MAJOR_SHIFT                   (24U)
+#define LPIT_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MAJOR_SHIFT)) & LPIT_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define LPIT_PARAM_CHANNEL_MASK                  (0xFFU)
+#define LPIT_PARAM_CHANNEL_SHIFT                 (0U)
+#define LPIT_PARAM_CHANNEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_CHANNEL_SHIFT)) & LPIT_PARAM_CHANNEL_MASK)
+#define LPIT_PARAM_EXT_TRIG_MASK                 (0xFF00U)
+#define LPIT_PARAM_EXT_TRIG_SHIFT                (8U)
+#define LPIT_PARAM_EXT_TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_EXT_TRIG_SHIFT)) & LPIT_PARAM_EXT_TRIG_MASK)
+/*! @} */
+
+/*! @name MCR - Module Control Register */
+/*! @{ */
+#define LPIT_MCR_M_CEN_MASK                      (0x1U)
+#define LPIT_MCR_M_CEN_SHIFT                     (0U)
+/*! M_CEN - Module Clock Enable
+ *  0b0..Disable peripheral clock to timers
+ *  0b1..Enable peripheral clock to timers
+ */
+#define LPIT_MCR_M_CEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_M_CEN_SHIFT)) & LPIT_MCR_M_CEN_MASK)
+#define LPIT_MCR_SW_RST_MASK                     (0x2U)
+#define LPIT_MCR_SW_RST_SHIFT                    (1U)
+/*! SW_RST - Software Reset Bit
+ *  0b0..Timer channels and registers are not reset
+ *  0b1..Reset timer channels and registers
+ */
+#define LPIT_MCR_SW_RST(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_SW_RST_SHIFT)) & LPIT_MCR_SW_RST_MASK)
+#define LPIT_MCR_DOZE_EN_MASK                    (0x4U)
+#define LPIT_MCR_DOZE_EN_SHIFT                   (2U)
+/*! DOZE_EN - DOZE Mode Enable Bit
+ *  0b0..Stop timer channels in DOZE mode
+ *  0b1..Allow timer channels to continue to run in DOZE mode
+ */
+#define LPIT_MCR_DOZE_EN(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DOZE_EN_SHIFT)) & LPIT_MCR_DOZE_EN_MASK)
+#define LPIT_MCR_DBG_EN_MASK                     (0x8U)
+#define LPIT_MCR_DBG_EN_SHIFT                    (3U)
+/*! DBG_EN - Debug Enable Bit
+ *  0b0..Stop timer channels in Debug mode
+ *  0b1..Allow timer channels to continue to run in Debug mode
+ */
+#define LPIT_MCR_DBG_EN(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DBG_EN_SHIFT)) & LPIT_MCR_DBG_EN_MASK)
+/*! @} */
+
+/*! @name MSR - Module Status Register */
+/*! @{ */
+#define LPIT_MSR_TIF0_MASK                       (0x1U)
+#define LPIT_MSR_TIF0_SHIFT                      (0U)
+/*! TIF0 - Channel 0 Timer Interrupt Flag
+ *  0b0..Timer has not timed out
+ *  0b1..Timeout has occurred (timer has timed out)
+ */
+#define LPIT_MSR_TIF0(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF0_SHIFT)) & LPIT_MSR_TIF0_MASK)
+#define LPIT_MSR_TIF1_MASK                       (0x2U)
+#define LPIT_MSR_TIF1_SHIFT                      (1U)
+/*! TIF1 - Channel 1 Timer Interrupt Flag
+ *  0b0..Timer has not timed out
+ *  0b1..Timeout has occurred (timer has timed out)
+ */
+#define LPIT_MSR_TIF1(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF1_SHIFT)) & LPIT_MSR_TIF1_MASK)
+#define LPIT_MSR_TIF2_MASK                       (0x4U)
+#define LPIT_MSR_TIF2_SHIFT                      (2U)
+/*! TIF2 - Channel 2 Timer Interrupt Flag
+ *  0b0..Timer has not timed out
+ *  0b1..Timeout has occurred (timer has timed out)
+ */
+#define LPIT_MSR_TIF2(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF2_SHIFT)) & LPIT_MSR_TIF2_MASK)
+#define LPIT_MSR_TIF3_MASK                       (0x8U)
+#define LPIT_MSR_TIF3_SHIFT                      (3U)
+/*! TIF3 - Channel 3 Timer Interrupt Flag
+ *  0b0..Timer has not timed out
+ *  0b1..Timeout has occurred (timer has timed out)
+ */
+#define LPIT_MSR_TIF3(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF3_SHIFT)) & LPIT_MSR_TIF3_MASK)
+/*! @} */
+
+/*! @name MIER - Module Interrupt Enable Register */
+/*! @{ */
+#define LPIT_MIER_TIE0_MASK                      (0x1U)
+#define LPIT_MIER_TIE0_SHIFT                     (0U)
+/*! TIE0 - Channel 0 Timer Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPIT_MIER_TIE0(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE0_SHIFT)) & LPIT_MIER_TIE0_MASK)
+#define LPIT_MIER_TIE1_MASK                      (0x2U)
+#define LPIT_MIER_TIE1_SHIFT                     (1U)
+/*! TIE1 - Channel 1 Timer Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPIT_MIER_TIE1(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE1_SHIFT)) & LPIT_MIER_TIE1_MASK)
+#define LPIT_MIER_TIE2_MASK                      (0x4U)
+#define LPIT_MIER_TIE2_SHIFT                     (2U)
+/*! TIE2 - Channel 2 Timer Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPIT_MIER_TIE2(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE2_SHIFT)) & LPIT_MIER_TIE2_MASK)
+#define LPIT_MIER_TIE3_MASK                      (0x8U)
+#define LPIT_MIER_TIE3_SHIFT                     (3U)
+/*! TIE3 - Channel 3 Timer Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPIT_MIER_TIE3(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE3_SHIFT)) & LPIT_MIER_TIE3_MASK)
+/*! @} */
+
+/*! @name SETTEN - Set Timer Enable Register */
+/*! @{ */
+#define LPIT_SETTEN_SET_T_EN_0_MASK              (0x1U)
+#define LPIT_SETTEN_SET_T_EN_0_SHIFT             (0U)
+/*! SET_T_EN_0 - Set Timer 0 Enable
+ *  0b0..No effect
+ *  0b1..Enables Timer Channel 0
+ */
+#define LPIT_SETTEN_SET_T_EN_0(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_0_SHIFT)) & LPIT_SETTEN_SET_T_EN_0_MASK)
+#define LPIT_SETTEN_SET_T_EN_1_MASK              (0x2U)
+#define LPIT_SETTEN_SET_T_EN_1_SHIFT             (1U)
+/*! SET_T_EN_1 - Set Timer 1 Enable
+ *  0b0..No Effect
+ *  0b1..Enables Timer Channel 1
+ */
+#define LPIT_SETTEN_SET_T_EN_1(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_1_SHIFT)) & LPIT_SETTEN_SET_T_EN_1_MASK)
+#define LPIT_SETTEN_SET_T_EN_2_MASK              (0x4U)
+#define LPIT_SETTEN_SET_T_EN_2_SHIFT             (2U)
+/*! SET_T_EN_2 - Set Timer 2 Enable
+ *  0b0..No Effect
+ *  0b1..Enables Timer Channel 2
+ */
+#define LPIT_SETTEN_SET_T_EN_2(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_2_SHIFT)) & LPIT_SETTEN_SET_T_EN_2_MASK)
+#define LPIT_SETTEN_SET_T_EN_3_MASK              (0x8U)
+#define LPIT_SETTEN_SET_T_EN_3_SHIFT             (3U)
+/*! SET_T_EN_3 - Set Timer 3 Enable
+ *  0b0..No effect
+ *  0b1..Enables Timer Channel 3
+ */
+#define LPIT_SETTEN_SET_T_EN_3(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_3_SHIFT)) & LPIT_SETTEN_SET_T_EN_3_MASK)
+/*! @} */
+
+/*! @name CLRTEN - Clear Timer Enable Register */
+/*! @{ */
+#define LPIT_CLRTEN_CLR_T_EN_0_MASK              (0x1U)
+#define LPIT_CLRTEN_CLR_T_EN_0_SHIFT             (0U)
+/*! CLR_T_EN_0 - Clear Timer 0 Enable
+ *  0b0..No action
+ *  0b1..Clear the Timer Enable bit (TCTRL0[T_EN]) for Timer Channel 0
+ */
+#define LPIT_CLRTEN_CLR_T_EN_0(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_0_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_0_MASK)
+#define LPIT_CLRTEN_CLR_T_EN_1_MASK              (0x2U)
+#define LPIT_CLRTEN_CLR_T_EN_1_SHIFT             (1U)
+/*! CLR_T_EN_1 - Clear Timer 1 Enable
+ *  0b0..No Action
+ *  0b1..Clear the Timer Enable bit (TCTRL1[T_EN]) for Timer Channel 1
+ */
+#define LPIT_CLRTEN_CLR_T_EN_1(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_1_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_1_MASK)
+#define LPIT_CLRTEN_CLR_T_EN_2_MASK              (0x4U)
+#define LPIT_CLRTEN_CLR_T_EN_2_SHIFT             (2U)
+/*! CLR_T_EN_2 - Clear Timer 2 Enable
+ *  0b0..No Action
+ *  0b1..Clear the Timer Enable bit (TCTRL2[T_EN]) for Timer Channel 2
+ */
+#define LPIT_CLRTEN_CLR_T_EN_2(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_2_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_2_MASK)
+#define LPIT_CLRTEN_CLR_T_EN_3_MASK              (0x8U)
+#define LPIT_CLRTEN_CLR_T_EN_3_SHIFT             (3U)
+/*! CLR_T_EN_3 - Clear Timer 3 Enable
+ *  0b0..No Action
+ *  0b1..Clear the Timer Enable bit (TCTRL3[T_EN]) for Timer Channel 3
+ */
+#define LPIT_CLRTEN_CLR_T_EN_3(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_3_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_3_MASK)
+/*! @} */
+
+/*! @name TVAL - Timer Value Register */
+/*! @{ */
+#define LPIT_TVAL_TMR_VAL_MASK                   (0xFFFFFFFFU)
+#define LPIT_TVAL_TMR_VAL_SHIFT                  (0U)
+/*! TMR_VAL - Timer Value
+ *  0b00000000000000000000000000000000..Invalid load value in compare mode
+ *  0b00000000000000000000000000000001..Invalid load value in compare mode
+ *  0b00000000000000000000000000000010-0b11111111111111111111111111111111..In compare mode: the value to be loaded; in capture mode, the value of the timer
+ */
+#define LPIT_TVAL_TMR_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << LPIT_TVAL_TMR_VAL_SHIFT)) & LPIT_TVAL_TMR_VAL_MASK)
+/*! @} */
+
+/* The count of LPIT_TVAL */
+#define LPIT_TVAL_COUNT                          (4U)
+
+/*! @name CVAL - Current Timer Value */
+/*! @{ */
+#define LPIT_CVAL_TMR_CUR_VAL_MASK               (0xFFFFFFFFU)
+#define LPIT_CVAL_TMR_CUR_VAL_SHIFT              (0U)
+#define LPIT_CVAL_TMR_CUR_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
+/*! @} */
+
+/* The count of LPIT_CVAL */
+#define LPIT_CVAL_COUNT                          (4U)
+
+/*! @name TCTRL - Timer Control Register */
+/*! @{ */
+#define LPIT_TCTRL_T_EN_MASK                     (0x1U)
+#define LPIT_TCTRL_T_EN_SHIFT                    (0U)
+/*! T_EN - Timer Enable
+ *  0b0..Timer Channel is disabled
+ *  0b1..Timer Channel is enabled
+ */
+#define LPIT_TCTRL_T_EN(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_T_EN_SHIFT)) & LPIT_TCTRL_T_EN_MASK)
+#define LPIT_TCTRL_CHAIN_MASK                    (0x2U)
+#define LPIT_TCTRL_CHAIN_SHIFT                   (1U)
+/*! CHAIN - Chain Channel
+ *  0b0..Channel Chaining is disabled. The channel timer runs independently.
+ *  0b1..Channel Chaining is enabled. The timer decrements on the previous channel's timeout.
+ */
+#define LPIT_TCTRL_CHAIN(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_CHAIN_SHIFT)) & LPIT_TCTRL_CHAIN_MASK)
+#define LPIT_TCTRL_MODE_MASK                     (0xCU)
+#define LPIT_TCTRL_MODE_SHIFT                    (2U)
+/*! MODE - Timer Operation Mode
+ *  0b00..32-bit Periodic Counter
+ *  0b01..Dual 16-bit Periodic Counter
+ *  0b10..32-bit Trigger Accumulator
+ *  0b11..32-bit Trigger Input Capture
+ */
+#define LPIT_TCTRL_MODE(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_MODE_SHIFT)) & LPIT_TCTRL_MODE_MASK)
+#define LPIT_TCTRL_TSOT_MASK                     (0x10000U)
+#define LPIT_TCTRL_TSOT_SHIFT                    (16U)
+/*! TSOT - Timer Start On Trigger
+ *  0b0..Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI))
+ *  0b1..Timer starts to decrement when a rising edge on a selected trigger is detected
+ */
+#define LPIT_TCTRL_TSOT(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOT_SHIFT)) & LPIT_TCTRL_TSOT_MASK)
+#define LPIT_TCTRL_TSOI_MASK                     (0x20000U)
+#define LPIT_TCTRL_TSOI_SHIFT                    (17U)
+/*! TSOI - Timer Stop On Interrupt
+ *  0b0..The channel timer does not stop after timeout
+ *  0b1..The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected.
+ */
+#define LPIT_TCTRL_TSOI(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOI_SHIFT)) & LPIT_TCTRL_TSOI_MASK)
+#define LPIT_TCTRL_TROT_MASK                     (0x40000U)
+#define LPIT_TCTRL_TROT_SHIFT                    (18U)
+/*! TROT - Timer Reload On Trigger
+ *  0b0..Timer will not reload on the selected trigger
+ *  0b1..Timer will reload on the selected trigger
+ */
+#define LPIT_TCTRL_TROT(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TROT_SHIFT)) & LPIT_TCTRL_TROT_MASK)
+#define LPIT_TCTRL_TRG_SRC_MASK                  (0x800000U)
+#define LPIT_TCTRL_TRG_SRC_SHIFT                 (23U)
+/*! TRG_SRC - Trigger Source
+ *  0b0..Selects external triggers
+ *  0b1..Selects internal triggers
+ */
+#define LPIT_TCTRL_TRG_SRC(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SRC_SHIFT)) & LPIT_TCTRL_TRG_SRC_MASK)
+#define LPIT_TCTRL_TRG_SEL_MASK                  (0xF000000U)
+#define LPIT_TCTRL_TRG_SEL_SHIFT                 (24U)
+/*! TRG_SEL - Trigger Select
+ *  0b0000-0b0011..Timer channel 0 - 3 trigger source is selected
+ *  0b0100-0b1111..Reserved
+ */
+#define LPIT_TCTRL_TRG_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SEL_SHIFT)) & LPIT_TCTRL_TRG_SEL_MASK)
+/*! @} */
+
+/* The count of LPIT_TCTRL */
+#define LPIT_TCTRL_COUNT                         (4U)
+
+
+/*!
+ * @}
+ */ /* end of group LPIT_Register_Masks */
+
+
+/* LPIT - Peripheral instance base addresses */
+/** Peripheral LPIT0 base address */
+#define LPIT0_BASE                               (0x40030000u)
+/** Peripheral LPIT0 base pointer */
+#define LPIT0                                    ((LPIT_Type *)LPIT0_BASE)
+/** Peripheral LPIT1 base address */
+#define LPIT1_BASE                               (0x4102A000u)
+/** Peripheral LPIT1 base pointer */
+#define LPIT1                                    ((LPIT_Type *)LPIT1_BASE)
+/** Array initializer of LPIT peripheral base addresses */
+#define LPIT_BASE_ADDRS                          { LPIT0_BASE, LPIT1_BASE }
+/** Array initializer of LPIT peripheral base pointers */
+#define LPIT_BASE_PTRS                           { LPIT0, LPIT1 }
+/** Interrupt vectors for the LPIT peripheral type */
+#define LPIT_IRQS                                { { LPIT0_IRQn, LPIT0_IRQn, LPIT0_IRQn, LPIT0_IRQn }, { LPIT1_IRQn, LPIT1_IRQn, LPIT1_IRQn, LPIT1_IRQn } }
+
+/*!
+ * @}
+ */ /* end of group LPIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPSPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
+ * @{
+ */
+
+/** LPSPI - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t CR;                                /**< Control Register, offset: 0x10 */
+  __IO uint32_t SR;                                /**< Status Register, offset: 0x14 */
+  __IO uint32_t IER;                               /**< Interrupt Enable Register, offset: 0x18 */
+  __IO uint32_t DER;                               /**< DMA Enable Register, offset: 0x1C */
+  __IO uint32_t CFGR0;                             /**< Configuration Register 0, offset: 0x20 */
+  __IO uint32_t CFGR1;                             /**< Configuration Register 1, offset: 0x24 */
+       uint8_t RESERVED_1[8];
+  __IO uint32_t DMR0;                              /**< Data Match Register 0, offset: 0x30 */
+  __IO uint32_t DMR1;                              /**< Data Match Register 1, offset: 0x34 */
+       uint8_t RESERVED_2[8];
+  __IO uint32_t CCR;                               /**< Clock Configuration Register, offset: 0x40 */
+       uint8_t RESERVED_3[20];
+  __IO uint32_t FCR;                               /**< FIFO Control Register, offset: 0x58 */
+  __I  uint32_t FSR;                               /**< FIFO Status Register, offset: 0x5C */
+  __IO uint32_t TCR;                               /**< Transmit Command Register, offset: 0x60 */
+  __O  uint32_t TDR;                               /**< Transmit Data Register, offset: 0x64 */
+       uint8_t RESERVED_4[8];
+  __I  uint32_t RSR;                               /**< Receive Status Register, offset: 0x70 */
+  __I  uint32_t RDR;                               /**< Receive Data Register, offset: 0x74 */
+} LPSPI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPSPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPSPI_Register_Masks LPSPI Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define LPSPI_VERID_FEATURE_MASK                 (0xFFFFU)
+#define LPSPI_VERID_FEATURE_SHIFT                (0U)
+/*! FEATURE - Module Identification Number
+ *  0b0000000000000100..Standard feature set supporting a 32-bit shift register.
+ */
+#define LPSPI_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
+#define LPSPI_VERID_MINOR_MASK                   (0xFF0000U)
+#define LPSPI_VERID_MINOR_SHIFT                  (16U)
+#define LPSPI_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
+#define LPSPI_VERID_MAJOR_MASK                   (0xFF000000U)
+#define LPSPI_VERID_MAJOR_SHIFT                  (24U)
+#define LPSPI_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define LPSPI_PARAM_TXFIFO_MASK                  (0xFFU)
+#define LPSPI_PARAM_TXFIFO_SHIFT                 (0U)
+#define LPSPI_PARAM_TXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
+#define LPSPI_PARAM_RXFIFO_MASK                  (0xFF00U)
+#define LPSPI_PARAM_RXFIFO_SHIFT                 (8U)
+#define LPSPI_PARAM_RXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
+/*! @} */
+
+/*! @name CR - Control Register */
+/*! @{ */
+#define LPSPI_CR_MEN_MASK                        (0x1U)
+#define LPSPI_CR_MEN_SHIFT                       (0U)
+/*! MEN - Module Enable
+ *  0b0..Module is disabled
+ *  0b1..Module is enabled
+ */
+#define LPSPI_CR_MEN(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
+#define LPSPI_CR_RST_MASK                        (0x2U)
+#define LPSPI_CR_RST_SHIFT                       (1U)
+/*! RST - Software Reset
+ *  0b0..Master logic is not reset
+ *  0b1..Master logic is reset
+ */
+#define LPSPI_CR_RST(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
+#define LPSPI_CR_DOZEN_MASK                      (0x4U)
+#define LPSPI_CR_DOZEN_SHIFT                     (2U)
+/*! DOZEN - Doze mode enable
+ *  0b0..Module is enabled in Doze mode
+ *  0b1..Module is disabled in Doze mode
+ */
+#define LPSPI_CR_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
+#define LPSPI_CR_DBGEN_MASK                      (0x8U)
+#define LPSPI_CR_DBGEN_SHIFT                     (3U)
+/*! DBGEN - Debug Enable
+ *  0b0..Module is disabled in debug mode
+ *  0b1..Module is enabled in debug mode
+ */
+#define LPSPI_CR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
+#define LPSPI_CR_RTF_MASK                        (0x100U)
+#define LPSPI_CR_RTF_SHIFT                       (8U)
+/*! RTF - Reset Transmit FIFO
+ *  0b0..No effect
+ *  0b1..Transmit FIFO is reset
+ */
+#define LPSPI_CR_RTF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
+#define LPSPI_CR_RRF_MASK                        (0x200U)
+#define LPSPI_CR_RRF_SHIFT                       (9U)
+/*! RRF - Reset Receive FIFO
+ *  0b0..No effect
+ *  0b1..Receive FIFO is reset
+ */
+#define LPSPI_CR_RRF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
+/*! @} */
+
+/*! @name SR - Status Register */
+/*! @{ */
+#define LPSPI_SR_TDF_MASK                        (0x1U)
+#define LPSPI_SR_TDF_SHIFT                       (0U)
+/*! TDF - Transmit Data Flag
+ *  0b0..Transmit data not requested
+ *  0b1..Transmit data is requested
+ */
+#define LPSPI_SR_TDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
+#define LPSPI_SR_RDF_MASK                        (0x2U)
+#define LPSPI_SR_RDF_SHIFT                       (1U)
+/*! RDF - Receive Data Flag
+ *  0b0..Receive Data is not ready
+ *  0b1..Receive data is ready
+ */
+#define LPSPI_SR_RDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
+#define LPSPI_SR_WCF_MASK                        (0x100U)
+#define LPSPI_SR_WCF_SHIFT                       (8U)
+/*! WCF - Word Complete Flag
+ *  0b0..Transfer of a received word has not yet completed
+ *  0b1..Transfer of a received word has completed
+ */
+#define LPSPI_SR_WCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
+#define LPSPI_SR_FCF_MASK                        (0x200U)
+#define LPSPI_SR_FCF_SHIFT                       (9U)
+/*! FCF - Frame Complete Flag
+ *  0b0..Frame transfer has not completed
+ *  0b1..Frame transfer has completed
+ */
+#define LPSPI_SR_FCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
+#define LPSPI_SR_TCF_MASK                        (0x400U)
+#define LPSPI_SR_TCF_SHIFT                       (10U)
+/*! TCF - Transfer Complete Flag
+ *  0b0..All transfers have not completed
+ *  0b1..All transfers have completed
+ */
+#define LPSPI_SR_TCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
+#define LPSPI_SR_TEF_MASK                        (0x800U)
+#define LPSPI_SR_TEF_SHIFT                       (11U)
+/*! TEF - Transmit Error Flag
+ *  0b0..Transmit FIFO underrun has not occurred
+ *  0b1..Transmit FIFO underrun has occurred
+ */
+#define LPSPI_SR_TEF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
+#define LPSPI_SR_REF_MASK                        (0x1000U)
+#define LPSPI_SR_REF_SHIFT                       (12U)
+/*! REF - Receive Error Flag
+ *  0b0..Receive FIFO has not overflowed
+ *  0b1..Receive FIFO has overflowed
+ */
+#define LPSPI_SR_REF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
+#define LPSPI_SR_DMF_MASK                        (0x2000U)
+#define LPSPI_SR_DMF_SHIFT                       (13U)
+/*! DMF - Data Match Flag
+ *  0b0..Have not received matching data
+ *  0b1..Have received matching data
+ */
+#define LPSPI_SR_DMF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
+#define LPSPI_SR_MBF_MASK                        (0x1000000U)
+#define LPSPI_SR_MBF_SHIFT                       (24U)
+/*! MBF - Module Busy Flag
+ *  0b0..LPSPI is idle
+ *  0b1..LPSPI is busy
+ */
+#define LPSPI_SR_MBF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
+/*! @} */
+
+/*! @name IER - Interrupt Enable Register */
+/*! @{ */
+#define LPSPI_IER_TDIE_MASK                      (0x1U)
+#define LPSPI_IER_TDIE_SHIFT                     (0U)
+/*! TDIE - Transmit Data Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_TDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
+#define LPSPI_IER_RDIE_MASK                      (0x2U)
+#define LPSPI_IER_RDIE_SHIFT                     (1U)
+/*! RDIE - Receive Data Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_RDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
+#define LPSPI_IER_WCIE_MASK                      (0x100U)
+#define LPSPI_IER_WCIE_SHIFT                     (8U)
+/*! WCIE - Word Complete Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_WCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
+#define LPSPI_IER_FCIE_MASK                      (0x200U)
+#define LPSPI_IER_FCIE_SHIFT                     (9U)
+/*! FCIE - Frame Complete Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_FCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
+#define LPSPI_IER_TCIE_MASK                      (0x400U)
+#define LPSPI_IER_TCIE_SHIFT                     (10U)
+/*! TCIE - Transfer Complete Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_TCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
+#define LPSPI_IER_TEIE_MASK                      (0x800U)
+#define LPSPI_IER_TEIE_SHIFT                     (11U)
+/*! TEIE - Transmit Error Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_TEIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
+#define LPSPI_IER_REIE_MASK                      (0x1000U)
+#define LPSPI_IER_REIE_SHIFT                     (12U)
+/*! REIE - Receive Error Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_REIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
+#define LPSPI_IER_DMIE_MASK                      (0x2000U)
+#define LPSPI_IER_DMIE_SHIFT                     (13U)
+/*! DMIE - Data Match Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_DMIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
+/*! @} */
+
+/*! @name DER - DMA Enable Register */
+/*! @{ */
+#define LPSPI_DER_TDDE_MASK                      (0x1U)
+#define LPSPI_DER_TDDE_SHIFT                     (0U)
+/*! TDDE - Transmit Data DMA Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
+#define LPSPI_DER_TDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
+#define LPSPI_DER_RDDE_MASK                      (0x2U)
+#define LPSPI_DER_RDDE_SHIFT                     (1U)
+/*! RDDE - Receive Data DMA Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
+#define LPSPI_DER_RDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
+/*! @} */
+
+/*! @name CFGR0 - Configuration Register 0 */
+/*! @{ */
+#define LPSPI_CFGR0_HREN_MASK                    (0x1U)
+#define LPSPI_CFGR0_HREN_SHIFT                   (0U)
+/*! HREN - Host Request Enable
+ *  0b0..Host request is disabled
+ *  0b1..Host request is enabled
+ */
+#define LPSPI_CFGR0_HREN(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
+#define LPSPI_CFGR0_HRPOL_MASK                   (0x2U)
+#define LPSPI_CFGR0_HRPOL_SHIFT                  (1U)
+/*! HRPOL - Host Request Polarity
+ *  0b0..Active low
+ *  0b1..Active high
+ */
+#define LPSPI_CFGR0_HRPOL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
+#define LPSPI_CFGR0_HRSEL_MASK                   (0x4U)
+#define LPSPI_CFGR0_HRSEL_SHIFT                  (2U)
+/*! HRSEL - Host Request Select
+ *  0b0..Host request input is the LPSPI_HREQ pin
+ *  0b1..Host request input is the input trigger
+ */
+#define LPSPI_CFGR0_HRSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
+#define LPSPI_CFGR0_CIRFIFO_MASK                 (0x100U)
+#define LPSPI_CFGR0_CIRFIFO_SHIFT                (8U)
+/*! CIRFIFO - Circular FIFO Enable
+ *  0b0..Circular FIFO is disabled
+ *  0b1..Circular FIFO is enabled
+ */
+#define LPSPI_CFGR0_CIRFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
+#define LPSPI_CFGR0_RDMO_MASK                    (0x200U)
+#define LPSPI_CFGR0_RDMO_SHIFT                   (9U)
+/*! RDMO - Receive Data Match Only
+ *  0b0..Received data is stored in the receive FIFO as in normal operations
+ *  0b1..Received data is discarded unless the Data Match Flag (DMF) is set
+ */
+#define LPSPI_CFGR0_RDMO(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
+/*! @} */
+
+/*! @name CFGR1 - Configuration Register 1 */
+/*! @{ */
+#define LPSPI_CFGR1_MASTER_MASK                  (0x1U)
+#define LPSPI_CFGR1_MASTER_SHIFT                 (0U)
+/*! MASTER - Master Mode
+ *  0b0..Slave mode
+ *  0b1..Master mode
+ */
+#define LPSPI_CFGR1_MASTER(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
+#define LPSPI_CFGR1_SAMPLE_MASK                  (0x2U)
+#define LPSPI_CFGR1_SAMPLE_SHIFT                 (1U)
+/*! SAMPLE - Sample Point
+ *  0b0..Input data is sampled on SCK edge
+ *  0b1..Input data is sampled on delayed SCK edge
+ */
+#define LPSPI_CFGR1_SAMPLE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
+#define LPSPI_CFGR1_AUTOPCS_MASK                 (0x4U)
+#define LPSPI_CFGR1_AUTOPCS_SHIFT                (2U)
+/*! AUTOPCS - Automatic PCS
+ *  0b0..Automatic PCS generation is disabled
+ *  0b1..Automatic PCS generation is enabled
+ */
+#define LPSPI_CFGR1_AUTOPCS(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
+#define LPSPI_CFGR1_NOSTALL_MASK                 (0x8U)
+#define LPSPI_CFGR1_NOSTALL_SHIFT                (3U)
+/*! NOSTALL - No Stall
+ *  0b0..Transfers will stall when the transmit FIFO is empty or the receive FIFO is full
+ *  0b1..Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur
+ */
+#define LPSPI_CFGR1_NOSTALL(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
+#define LPSPI_CFGR1_PCSPOL_MASK                  (0xF00U)
+#define LPSPI_CFGR1_PCSPOL_SHIFT                 (8U)
+/*! PCSPOL - Peripheral Chip Select Polarity
+ *  0b0000..The Peripheral Chip Select pin PCSx is active low
+ *  0b0001..The Peripheral Chip Select pin PCSx is active high
+ */
+#define LPSPI_CFGR1_PCSPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
+#define LPSPI_CFGR1_MATCFG_MASK                  (0x70000U)
+#define LPSPI_CFGR1_MATCFG_SHIFT                 (16U)
+/*! MATCFG - Match Configuration
+ *  0b000..Match is disabled
+ *  0b001..Reserved
+ *  0b010..010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1)
+ *  0b011..011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)
+ *  0b100..100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)]
+ *  0b101..101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)]
+ *  0b110..110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)]
+ *  0b111..111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)]
+ */
+#define LPSPI_CFGR1_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
+#define LPSPI_CFGR1_PINCFG_MASK                  (0x3000000U)
+#define LPSPI_CFGR1_PINCFG_SHIFT                 (24U)
+/*! PINCFG - Pin Configuration
+ *  0b00..SIN is used for input data and SOUT is used for output data
+ *  0b01..SIN is used for both input and output data
+ *  0b10..SOUT is used for both input and output data
+ *  0b11..SOUT is used for input data and SIN is used for output data
+ */
+#define LPSPI_CFGR1_PINCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
+#define LPSPI_CFGR1_OUTCFG_MASK                  (0x4000000U)
+#define LPSPI_CFGR1_OUTCFG_SHIFT                 (26U)
+/*! OUTCFG - Output Config
+ *  0b0..Output data retains last value when chip select is negated
+ *  0b1..Output data is tristated when chip select is negated
+ */
+#define LPSPI_CFGR1_OUTCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
+#define LPSPI_CFGR1_PCSCFG_MASK                  (0x8000000U)
+#define LPSPI_CFGR1_PCSCFG_SHIFT                 (27U)
+/*! PCSCFG - Peripheral Chip Select Configuration
+ *  0b0..PCS[3:2] are enabled
+ *  0b1..PCS[3:2] are disabled
+ */
+#define LPSPI_CFGR1_PCSCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
+/*! @} */
+
+/*! @name DMR0 - Data Match Register 0 */
+/*! @{ */
+#define LPSPI_DMR0_MATCH0_MASK                   (0xFFFFFFFFU)
+#define LPSPI_DMR0_MATCH0_SHIFT                  (0U)
+#define LPSPI_DMR0_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
+/*! @} */
+
+/*! @name DMR1 - Data Match Register 1 */
+/*! @{ */
+#define LPSPI_DMR1_MATCH1_MASK                   (0xFFFFFFFFU)
+#define LPSPI_DMR1_MATCH1_SHIFT                  (0U)
+#define LPSPI_DMR1_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
+/*! @} */
+
+/*! @name CCR - Clock Configuration Register */
+/*! @{ */
+#define LPSPI_CCR_SCKDIV_MASK                    (0xFFU)
+#define LPSPI_CCR_SCKDIV_SHIFT                   (0U)
+#define LPSPI_CCR_SCKDIV(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
+#define LPSPI_CCR_DBT_MASK                       (0xFF00U)
+#define LPSPI_CCR_DBT_SHIFT                      (8U)
+#define LPSPI_CCR_DBT(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
+#define LPSPI_CCR_PCSSCK_MASK                    (0xFF0000U)
+#define LPSPI_CCR_PCSSCK_SHIFT                   (16U)
+#define LPSPI_CCR_PCSSCK(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
+#define LPSPI_CCR_SCKPCS_MASK                    (0xFF000000U)
+#define LPSPI_CCR_SCKPCS_SHIFT                   (24U)
+#define LPSPI_CCR_SCKPCS(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
+/*! @} */
+
+/*! @name FCR - FIFO Control Register */
+/*! @{ */
+#define LPSPI_FCR_TXWATER_MASK                   (0x3U)
+#define LPSPI_FCR_TXWATER_SHIFT                  (0U)
+#define LPSPI_FCR_TXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
+#define LPSPI_FCR_RXWATER_MASK                   (0x30000U)
+#define LPSPI_FCR_RXWATER_SHIFT                  (16U)
+#define LPSPI_FCR_RXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
+/*! @} */
+
+/*! @name FSR - FIFO Status Register */
+/*! @{ */
+#define LPSPI_FSR_TXCOUNT_MASK                   (0x7U)
+#define LPSPI_FSR_TXCOUNT_SHIFT                  (0U)
+#define LPSPI_FSR_TXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
+#define LPSPI_FSR_RXCOUNT_MASK                   (0x70000U)
+#define LPSPI_FSR_RXCOUNT_SHIFT                  (16U)
+#define LPSPI_FSR_RXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
+/*! @} */
+
+/*! @name TCR - Transmit Command Register */
+/*! @{ */
+#define LPSPI_TCR_FRAMESZ_MASK                   (0xFFFU)
+#define LPSPI_TCR_FRAMESZ_SHIFT                  (0U)
+#define LPSPI_TCR_FRAMESZ(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
+#define LPSPI_TCR_WIDTH_MASK                     (0x30000U)
+#define LPSPI_TCR_WIDTH_SHIFT                    (16U)
+/*! WIDTH - Transfer Width
+ *  0b00..1 bit transfer
+ *  0b01..2 bit transfer
+ *  0b10..4 bit transfer
+ *  0b11..Reserved
+ */
+#define LPSPI_TCR_WIDTH(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
+#define LPSPI_TCR_TXMSK_MASK                     (0x40000U)
+#define LPSPI_TCR_TXMSK_SHIFT                    (18U)
+/*! TXMSK - Transmit Data Mask
+ *  0b0..Normal transfer
+ *  0b1..Mask transmit data
+ */
+#define LPSPI_TCR_TXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
+#define LPSPI_TCR_RXMSK_MASK                     (0x80000U)
+#define LPSPI_TCR_RXMSK_SHIFT                    (19U)
+/*! RXMSK - Receive Data Mask
+ *  0b0..Normal transfer
+ *  0b1..Receive data is masked
+ */
+#define LPSPI_TCR_RXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
+#define LPSPI_TCR_CONTC_MASK                     (0x100000U)
+#define LPSPI_TCR_CONTC_SHIFT                    (20U)
+/*! CONTC - Continuing Command
+ *  0b0..Command word for start of new transfer
+ *  0b1..Command word for continuing transfer
+ */
+#define LPSPI_TCR_CONTC(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
+#define LPSPI_TCR_CONT_MASK                      (0x200000U)
+#define LPSPI_TCR_CONT_SHIFT                     (21U)
+/*! CONT - Continuous Transfer
+ *  0b0..Continuous transfer is disabled
+ *  0b1..Continuous transfer is enabled
+ */
+#define LPSPI_TCR_CONT(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
+#define LPSPI_TCR_BYSW_MASK                      (0x400000U)
+#define LPSPI_TCR_BYSW_SHIFT                     (22U)
+/*! BYSW - Byte Swap
+ *  0b0..Byte swap is disabled
+ *  0b1..Byte swap is enabled
+ */
+#define LPSPI_TCR_BYSW(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
+#define LPSPI_TCR_LSBF_MASK                      (0x800000U)
+#define LPSPI_TCR_LSBF_SHIFT                     (23U)
+/*! LSBF - LSB First
+ *  0b0..Data is transferred MSB first
+ *  0b1..Data is transferred LSB first
+ */
+#define LPSPI_TCR_LSBF(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
+#define LPSPI_TCR_PCS_MASK                       (0x3000000U)
+#define LPSPI_TCR_PCS_SHIFT                      (24U)
+/*! PCS - Peripheral Chip Select
+ *  0b00..Transfer using LPSPI_PCS[0]
+ *  0b01..Transfer using LPSPI_PCS[1]
+ *  0b10..Transfer using LPSPI_PCS[2]
+ *  0b11..Transfer using LPSPI_PCS[3]
+ */
+#define LPSPI_TCR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
+#define LPSPI_TCR_PRESCALE_MASK                  (0x38000000U)
+#define LPSPI_TCR_PRESCALE_SHIFT                 (27U)
+/*! PRESCALE - Prescaler Value
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 4
+ *  0b011..Divide by 8
+ *  0b100..Divide by 16
+ *  0b101..Divide by 32
+ *  0b110..Divide by 64
+ *  0b111..Divide by 128
+ */
+#define LPSPI_TCR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
+#define LPSPI_TCR_CPHA_MASK                      (0x40000000U)
+#define LPSPI_TCR_CPHA_SHIFT                     (30U)
+/*! CPHA - Clock Phase
+ *  0b0..Data is captured on the leading edge of SCK and changed on the following edge of SCK
+ *  0b1..Data is changed on the leading edge of SCK and captured on the following edge of SCK
+ */
+#define LPSPI_TCR_CPHA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
+#define LPSPI_TCR_CPOL_MASK                      (0x80000000U)
+#define LPSPI_TCR_CPOL_SHIFT                     (31U)
+/*! CPOL - Clock Polarity
+ *  0b0..The inactive state value of SCK is low
+ *  0b1..The inactive state value of SCK is high
+ */
+#define LPSPI_TCR_CPOL(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
+/*! @} */
+
+/*! @name TDR - Transmit Data Register */
+/*! @{ */
+#define LPSPI_TDR_DATA_MASK                      (0xFFFFFFFFU)
+#define LPSPI_TDR_DATA_SHIFT                     (0U)
+#define LPSPI_TDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
+/*! @} */
+
+/*! @name RSR - Receive Status Register */
+/*! @{ */
+#define LPSPI_RSR_SOF_MASK                       (0x1U)
+#define LPSPI_RSR_SOF_SHIFT                      (0U)
+/*! SOF - Start Of Frame
+ *  0b0..Subsequent data word received after LPSPI_PCS assertion
+ *  0b1..First data word received after LPSPI_PCS assertion
+ */
+#define LPSPI_RSR_SOF(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
+#define LPSPI_RSR_RXEMPTY_MASK                   (0x2U)
+#define LPSPI_RSR_RXEMPTY_SHIFT                  (1U)
+/*! RXEMPTY - RX FIFO Empty
+ *  0b0..RX FIFO is not empty
+ *  0b1..RX FIFO is empty
+ */
+#define LPSPI_RSR_RXEMPTY(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
+/*! @} */
+
+/*! @name RDR - Receive Data Register */
+/*! @{ */
+#define LPSPI_RDR_DATA_MASK                      (0xFFFFFFFFU)
+#define LPSPI_RDR_DATA_SHIFT                     (0U)
+#define LPSPI_RDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LPSPI_Register_Masks */
+
+
+/* LPSPI - Peripheral instance base addresses */
+/** Peripheral LPSPI0 base address */
+#define LPSPI0_BASE                              (0x4003F000u)
+/** Peripheral LPSPI0 base pointer */
+#define LPSPI0                                   ((LPSPI_Type *)LPSPI0_BASE)
+/** Peripheral LPSPI1 base address */
+#define LPSPI1_BASE                              (0x40040000u)
+/** Peripheral LPSPI1 base pointer */
+#define LPSPI1                                   ((LPSPI_Type *)LPSPI1_BASE)
+/** Peripheral LPSPI2 base address */
+#define LPSPI2_BASE                              (0x40041000u)
+/** Peripheral LPSPI2 base pointer */
+#define LPSPI2                                   ((LPSPI_Type *)LPSPI2_BASE)
+/** Peripheral LPSPI3 base address */
+#define LPSPI3_BASE                              (0x41035000u)
+/** Peripheral LPSPI3 base pointer */
+#define LPSPI3                                   ((LPSPI_Type *)LPSPI3_BASE)
+/** Array initializer of LPSPI peripheral base addresses */
+#define LPSPI_BASE_ADDRS                         { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE }
+/** Array initializer of LPSPI peripheral base pointers */
+#define LPSPI_BASE_PTRS                          { LPSPI0, LPSPI1, LPSPI2, LPSPI3 }
+/** Interrupt vectors for the LPSPI peripheral type */
+#define LPSPI_IRQS                               { LPSPI0_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPSPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CSR;                               /**< Low Power Timer Control Status Register, offset: 0x0 */
+  __IO uint32_t PSR;                               /**< Low Power Timer Prescale Register, offset: 0x4 */
+  __IO uint32_t CMR;                               /**< Low Power Timer Compare Register, offset: 0x8 */
+  __IO uint32_t CNR;                               /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/*! @name CSR - Low Power Timer Control Status Register */
+/*! @{ */
+#define LPTMR_CSR_TEN_MASK                       (0x1U)
+#define LPTMR_CSR_TEN_SHIFT                      (0U)
+/*! TEN - Timer Enable
+ *  0b0..LPTMR is disabled and internal logic is reset.
+ *  0b1..LPTMR is enabled.
+ */
+#define LPTMR_CSR_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
+#define LPTMR_CSR_TMS_MASK                       (0x2U)
+#define LPTMR_CSR_TMS_SHIFT                      (1U)
+/*! TMS - Timer Mode Select
+ *  0b0..Time Counter mode.
+ *  0b1..Pulse Counter mode.
+ */
+#define LPTMR_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
+#define LPTMR_CSR_TFC_MASK                       (0x4U)
+#define LPTMR_CSR_TFC_SHIFT                      (2U)
+/*! TFC - Timer Free-Running Counter
+ *  0b0..CNR is reset whenever TCF is set.
+ *  0b1..CNR is reset on overflow.
+ */
+#define LPTMR_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
+#define LPTMR_CSR_TPP_MASK                       (0x8U)
+#define LPTMR_CSR_TPP_SHIFT                      (3U)
+/*! TPP - Timer Pin Polarity
+ *  0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.
+ *  0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.
+ */
+#define LPTMR_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
+#define LPTMR_CSR_TPS_MASK                       (0x30U)
+#define LPTMR_CSR_TPS_SHIFT                      (4U)
+/*! TPS - Timer Pin Select
+ *  0b00..Pulse counter input 0 is selected.
+ *  0b01..Pulse counter input 1 is selected.
+ *  0b10..Pulse counter input 2 is selected.
+ *  0b11..Pulse counter input 3 is selected.
+ */
+#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK                       (0x40U)
+#define LPTMR_CSR_TIE_SHIFT                      (6U)
+/*! TIE - Timer Interrupt Enable
+ *  0b0..Timer interrupt disabled.
+ *  0b1..Timer interrupt enabled.
+ */
+#define LPTMR_CSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
+#define LPTMR_CSR_TCF_MASK                       (0x80U)
+#define LPTMR_CSR_TCF_SHIFT                      (7U)
+/*! TCF - Timer Compare Flag
+ *  0b0..The value of CNR is not equal to CMR and increments.
+ *  0b1..The value of CNR is equal to CMR and increments.
+ */
+#define LPTMR_CSR_TCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
+#define LPTMR_CSR_TDRE_MASK                      (0x100U)
+#define LPTMR_CSR_TDRE_SHIFT                     (8U)
+/*! TDRE - Timer DMA Request Enable
+ *  0b0..Timer DMA Request disabled.
+ *  0b1..Timer DMA Request enabled.
+ */
+#define LPTMR_CSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK)
+/*! @} */
+
+/*! @name PSR - Low Power Timer Prescale Register */
+/*! @{ */
+#define LPTMR_PSR_PCS_MASK                       (0x3U)
+#define LPTMR_PSR_PCS_SHIFT                      (0U)
+/*! PCS - Prescaler Clock Select
+ *  0b00..Prescaler/glitch filter clock 0 selected.
+ *  0b01..Prescaler/glitch filter clock 1 selected.
+ *  0b10..Prescaler/glitch filter clock 2 selected.
+ *  0b11..Prescaler/glitch filter clock 3 selected.
+ */
+#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK                      (0x4U)
+#define LPTMR_PSR_PBYP_SHIFT                     (2U)
+/*! PBYP - Prescaler Bypass
+ *  0b0..Prescaler/glitch filter is enabled.
+ *  0b1..Prescaler/glitch filter is bypassed.
+ */
+#define LPTMR_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
+#define LPTMR_PSR_PRESCALE_MASK                  (0x78U)
+#define LPTMR_PSR_PRESCALE_SHIFT                 (3U)
+/*! PRESCALE - Prescale Value
+ *  0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.
+ *  0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.
+ *  0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.
+ *  0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.
+ *  0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.
+ *  0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.
+ *  0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.
+ *  0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.
+ *  0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.
+ *  0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.
+ *  0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.
+ *  0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.
+ *  0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.
+ *  0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.
+ *  0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.
+ *  0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.
+ */
+#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
+/*! @} */
+
+/*! @name CMR - Low Power Timer Compare Register */
+/*! @{ */
+#define LPTMR_CMR_COMPARE_MASK                   (0xFFFFFFFFU)
+#define LPTMR_CMR_COMPARE_SHIFT                  (0U)
+#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
+/*! @} */
+
+/*! @name CNR - Low Power Timer Counter Register */
+/*! @{ */
+#define LPTMR_CNR_COUNTER_MASK                   (0xFFFFFFFFU)
+#define LPTMR_CNR_COUNTER_SHIFT                  (0U)
+#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE                              (0x40032000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
+/** Peripheral LPTMR1 base address */
+#define LPTMR1_BASE                              (0x40033000u)
+/** Peripheral LPTMR1 base pointer */
+#define LPTMR1                                   ((LPTMR_Type *)LPTMR1_BASE)
+/** Peripheral LPTMR2 base address */
+#define LPTMR2_BASE                              (0x4102B000u)
+/** Peripheral LPTMR2 base pointer */
+#define LPTMR2                                   ((LPTMR_Type *)LPTMR2_BASE)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS                         { LPTMR0_BASE, LPTMR1_BASE, LPTMR2_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS                          { LPTMR0, LPTMR1, LPTMR2 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS                               { LPTMR0_IRQn, LPTMR1_IRQn, LPTMR2_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPUART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
+ * @{
+ */
+
+/** LPUART - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __IO uint32_t GLOBAL;                            /**< LPUART Global Register, offset: 0x8 */
+  __IO uint32_t PINCFG;                            /**< LPUART Pin Configuration Register, offset: 0xC */
+  __IO uint32_t BAUD;                              /**< LPUART Baud Rate Register, offset: 0x10 */
+  __IO uint32_t STAT;                              /**< LPUART Status Register, offset: 0x14 */
+  __IO uint32_t CTRL;                              /**< LPUART Control Register, offset: 0x18 */
+  __IO uint32_t DATA;                              /**< LPUART Data Register, offset: 0x1C */
+  __IO uint32_t MATCH;                             /**< LPUART Match Address Register, offset: 0x20 */
+  __IO uint32_t MODIR;                             /**< LPUART Modem IrDA Register, offset: 0x24 */
+  __IO uint32_t FIFO;                              /**< LPUART FIFO Register, offset: 0x28 */
+  __IO uint32_t WATER;                             /**< LPUART Watermark Register, offset: 0x2C */
+} LPUART_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPUART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Register_Masks LPUART Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define LPUART_VERID_FEATURE_MASK                (0xFFFFU)
+#define LPUART_VERID_FEATURE_SHIFT               (0U)
+/*! FEATURE - Feature Identification Number
+ *  0b0000000000000001..Standard feature set.
+ *  0b0000000000000011..Standard feature set with MODEM/IrDA support.
+ */
+#define LPUART_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
+#define LPUART_VERID_MINOR_MASK                  (0xFF0000U)
+#define LPUART_VERID_MINOR_SHIFT                 (16U)
+#define LPUART_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
+#define LPUART_VERID_MAJOR_MASK                  (0xFF000000U)
+#define LPUART_VERID_MAJOR_SHIFT                 (24U)
+#define LPUART_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define LPUART_PARAM_TXFIFO_MASK                 (0xFFU)
+#define LPUART_PARAM_TXFIFO_SHIFT                (0U)
+#define LPUART_PARAM_TXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
+#define LPUART_PARAM_RXFIFO_MASK                 (0xFF00U)
+#define LPUART_PARAM_RXFIFO_SHIFT                (8U)
+#define LPUART_PARAM_RXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
+/*! @} */
+
+/*! @name GLOBAL - LPUART Global Register */
+/*! @{ */
+#define LPUART_GLOBAL_RST_MASK                   (0x2U)
+#define LPUART_GLOBAL_RST_SHIFT                  (1U)
+/*! RST - Software Reset
+ *  0b0..Module is not reset.
+ *  0b1..Module is reset.
+ */
+#define LPUART_GLOBAL_RST(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
+/*! @} */
+
+/*! @name PINCFG - LPUART Pin Configuration Register */
+/*! @{ */
+#define LPUART_PINCFG_TRGSEL_MASK                (0x3U)
+#define LPUART_PINCFG_TRGSEL_SHIFT               (0U)
+/*! TRGSEL - Trigger Select
+ *  0b00..Input trigger is disabled.
+ *  0b01..Input trigger is used instead of RXD pin input.
+ *  0b10..Input trigger is used instead of CTS_B pin input.
+ *  0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger.
+ */
+#define LPUART_PINCFG_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
+/*! @} */
+
+/*! @name BAUD - LPUART Baud Rate Register */
+/*! @{ */
+#define LPUART_BAUD_SBR_MASK                     (0x1FFFU)
+#define LPUART_BAUD_SBR_SHIFT                    (0U)
+#define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
+#define LPUART_BAUD_SBNS_MASK                    (0x2000U)
+#define LPUART_BAUD_SBNS_SHIFT                   (13U)
+/*! SBNS - Stop Bit Number Select
+ *  0b0..One stop bit.
+ *  0b1..Two stop bits.
+ */
+#define LPUART_BAUD_SBNS(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
+#define LPUART_BAUD_RXEDGIE_MASK                 (0x4000U)
+#define LPUART_BAUD_RXEDGIE_SHIFT                (14U)
+/*! RXEDGIE - RX Input Active Edge Interrupt Enable
+ *  0b0..Hardware interrupts from LPUART_STAT[RXEDGIF] disabled.
+ *  0b1..Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1.
+ */
+#define LPUART_BAUD_RXEDGIE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
+#define LPUART_BAUD_LBKDIE_MASK                  (0x8000U)
+#define LPUART_BAUD_LBKDIE_SHIFT                 (15U)
+/*! LBKDIE - LIN Break Detect Interrupt Enable
+ *  0b0..Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling).
+ *  0b1..Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1.
+ */
+#define LPUART_BAUD_LBKDIE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
+#define LPUART_BAUD_RESYNCDIS_MASK               (0x10000U)
+#define LPUART_BAUD_RESYNCDIS_SHIFT              (16U)
+/*! RESYNCDIS - Resynchronization Disable
+ *  0b0..Resynchronization during received data word is supported
+ *  0b1..Resynchronization during received data word is disabled
+ */
+#define LPUART_BAUD_RESYNCDIS(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
+#define LPUART_BAUD_BOTHEDGE_MASK                (0x20000U)
+#define LPUART_BAUD_BOTHEDGE_SHIFT               (17U)
+/*! BOTHEDGE - Both Edge Sampling
+ *  0b0..Receiver samples input data using the rising edge of the baud rate clock.
+ *  0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.
+ */
+#define LPUART_BAUD_BOTHEDGE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
+#define LPUART_BAUD_MATCFG_MASK                  (0xC0000U)
+#define LPUART_BAUD_MATCFG_SHIFT                 (18U)
+/*! MATCFG - Match Configuration
+ *  0b00..Address Match Wakeup
+ *  0b01..Idle Match Wakeup
+ *  0b10..Match On and Match Off
+ *  0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input
+ */
+#define LPUART_BAUD_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
+#define LPUART_BAUD_RIDMAE_MASK                  (0x100000U)
+#define LPUART_BAUD_RIDMAE_SHIFT                 (20U)
+/*! RIDMAE - Receiver Idle DMA Enable
+ *  0b0..DMA request disabled.
+ *  0b1..DMA request enabled.
+ */
+#define LPUART_BAUD_RIDMAE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)
+#define LPUART_BAUD_RDMAE_MASK                   (0x200000U)
+#define LPUART_BAUD_RDMAE_SHIFT                  (21U)
+/*! RDMAE - Receiver Full DMA Enable
+ *  0b0..DMA request disabled.
+ *  0b1..DMA request enabled.
+ */
+#define LPUART_BAUD_RDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
+#define LPUART_BAUD_TDMAE_MASK                   (0x800000U)
+#define LPUART_BAUD_TDMAE_SHIFT                  (23U)
+/*! TDMAE - Transmitter DMA Enable
+ *  0b0..DMA request disabled.
+ *  0b1..DMA request enabled.
+ */
+#define LPUART_BAUD_TDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
+#define LPUART_BAUD_OSR_MASK                     (0x1F000000U)
+#define LPUART_BAUD_OSR_SHIFT                    (24U)
+/*! OSR - Oversampling Ratio
+ *  0b00000..Writing 0 to this field will result in an oversampling ratio of 16
+ *  0b00001..Reserved
+ *  0b00010..Reserved
+ *  0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set.
+ *  0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set.
+ *  0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set.
+ *  0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set.
+ *  0b00111..Oversampling ratio of 8.
+ *  0b01000..Oversampling ratio of 9.
+ *  0b01001..Oversampling ratio of 10.
+ *  0b01010..Oversampling ratio of 11.
+ *  0b01011..Oversampling ratio of 12.
+ *  0b01100..Oversampling ratio of 13.
+ *  0b01101..Oversampling ratio of 14.
+ *  0b01110..Oversampling ratio of 15.
+ *  0b01111..Oversampling ratio of 16.
+ *  0b10000..Oversampling ratio of 17.
+ *  0b10001..Oversampling ratio of 18.
+ *  0b10010..Oversampling ratio of 19.
+ *  0b10011..Oversampling ratio of 20.
+ *  0b10100..Oversampling ratio of 21.
+ *  0b10101..Oversampling ratio of 22.
+ *  0b10110..Oversampling ratio of 23.
+ *  0b10111..Oversampling ratio of 24.
+ *  0b11000..Oversampling ratio of 25.
+ *  0b11001..Oversampling ratio of 26.
+ *  0b11010..Oversampling ratio of 27.
+ *  0b11011..Oversampling ratio of 28.
+ *  0b11100..Oversampling ratio of 29.
+ *  0b11101..Oversampling ratio of 30.
+ *  0b11110..Oversampling ratio of 31.
+ *  0b11111..Oversampling ratio of 32.
+ */
+#define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
+#define LPUART_BAUD_M10_MASK                     (0x20000000U)
+#define LPUART_BAUD_M10_SHIFT                    (29U)
+/*! M10 - 10-bit Mode select
+ *  0b0..Receiver and transmitter use 7-bit to 9-bit data characters.
+ *  0b1..Receiver and transmitter use 10-bit data characters.
+ */
+#define LPUART_BAUD_M10(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
+#define LPUART_BAUD_MAEN2_MASK                   (0x40000000U)
+#define LPUART_BAUD_MAEN2_SHIFT                  (30U)
+/*! MAEN2 - Match Address Mode Enable 2
+ *  0b0..Normal operation.
+ *  0b1..Enables automatic address matching or data matching mode for MATCH[MA2].
+ */
+#define LPUART_BAUD_MAEN2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
+#define LPUART_BAUD_MAEN1_MASK                   (0x80000000U)
+#define LPUART_BAUD_MAEN1_SHIFT                  (31U)
+/*! MAEN1 - Match Address Mode Enable 1
+ *  0b0..Normal operation.
+ *  0b1..Enables automatic address matching or data matching mode for MATCH[MA1].
+ */
+#define LPUART_BAUD_MAEN1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
+/*! @} */
+
+/*! @name STAT - LPUART Status Register */
+/*! @{ */
+#define LPUART_STAT_MA2F_MASK                    (0x4000U)
+#define LPUART_STAT_MA2F_SHIFT                   (14U)
+/*! MA2F - Match 2 Flag
+ *  0b0..Received data is not equal to MA2
+ *  0b1..Received data is equal to MA2
+ */
+#define LPUART_STAT_MA2F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
+#define LPUART_STAT_MA1F_MASK                    (0x8000U)
+#define LPUART_STAT_MA1F_SHIFT                   (15U)
+/*! MA1F - Match 1 Flag
+ *  0b0..Received data is not equal to MA1
+ *  0b1..Received data is equal to MA1
+ */
+#define LPUART_STAT_MA1F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
+#define LPUART_STAT_PF_MASK                      (0x10000U)
+#define LPUART_STAT_PF_SHIFT                     (16U)
+/*! PF - Parity Error Flag
+ *  0b0..No parity error.
+ *  0b1..Parity error.
+ */
+#define LPUART_STAT_PF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
+#define LPUART_STAT_FE_MASK                      (0x20000U)
+#define LPUART_STAT_FE_SHIFT                     (17U)
+/*! FE - Framing Error Flag
+ *  0b0..No framing error detected. This does not guarantee the framing is correct.
+ *  0b1..Framing error.
+ */
+#define LPUART_STAT_FE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
+#define LPUART_STAT_NF_MASK                      (0x40000U)
+#define LPUART_STAT_NF_SHIFT                     (18U)
+/*! NF - Noise Flag
+ *  0b0..No noise detected.
+ *  0b1..Noise detected in the received character in LPUART_DATA.
+ */
+#define LPUART_STAT_NF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
+#define LPUART_STAT_OR_MASK                      (0x80000U)
+#define LPUART_STAT_OR_SHIFT                     (19U)
+/*! OR - Receiver Overrun Flag
+ *  0b0..No overrun.
+ *  0b1..Receive overrun (new LPUART data lost).
+ */
+#define LPUART_STAT_OR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
+#define LPUART_STAT_IDLE_MASK                    (0x100000U)
+#define LPUART_STAT_IDLE_SHIFT                   (20U)
+/*! IDLE - Idle Line Flag
+ *  0b0..No idle line detected.
+ *  0b1..Idle line was detected.
+ */
+#define LPUART_STAT_IDLE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
+#define LPUART_STAT_RDRF_MASK                    (0x200000U)
+#define LPUART_STAT_RDRF_SHIFT                   (21U)
+/*! RDRF - Receive Data Register Full Flag
+ *  0b0..Receive data buffer empty.
+ *  0b1..Receive data buffer full.
+ */
+#define LPUART_STAT_RDRF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
+#define LPUART_STAT_TC_MASK                      (0x400000U)
+#define LPUART_STAT_TC_SHIFT                     (22U)
+/*! TC - Transmission Complete Flag
+ *  0b0..Transmitter active (sending data, a preamble, or a break).
+ *  0b1..Transmitter idle (transmission activity complete).
+ */
+#define LPUART_STAT_TC(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
+#define LPUART_STAT_TDRE_MASK                    (0x800000U)
+#define LPUART_STAT_TDRE_SHIFT                   (23U)
+/*! TDRE - Transmit Data Register Empty Flag
+ *  0b0..Transmit data buffer full.
+ *  0b1..Transmit data buffer empty.
+ */
+#define LPUART_STAT_TDRE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
+#define LPUART_STAT_RAF_MASK                     (0x1000000U)
+#define LPUART_STAT_RAF_SHIFT                    (24U)
+/*! RAF - Receiver Active Flag
+ *  0b0..LPUART receiver idle waiting for a start bit.
+ *  0b1..LPUART receiver active (RXD input not idle).
+ */
+#define LPUART_STAT_RAF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
+#define LPUART_STAT_LBKDE_MASK                   (0x2000000U)
+#define LPUART_STAT_LBKDE_SHIFT                  (25U)
+/*! LBKDE - LIN Break Detection Enable
+ *  0b0..LIN break detect is disabled, normal break character can be detected.
+ *  0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1).
+ */
+#define LPUART_STAT_LBKDE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
+#define LPUART_STAT_BRK13_MASK                   (0x4000000U)
+#define LPUART_STAT_BRK13_SHIFT                  (26U)
+/*! BRK13 - Break Character Generation Length
+ *  0b0..Break character is transmitted with length of 9 to 13 bit times.
+ *  0b1..Break character is transmitted with length of 12 to 15 bit times.
+ */
+#define LPUART_STAT_BRK13(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
+#define LPUART_STAT_RWUID_MASK                   (0x8000000U)
+#define LPUART_STAT_RWUID_SHIFT                  (27U)
+/*! RWUID - Receive Wake Up Idle Detect
+ *  0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match.
+ *  0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match.
+ */
+#define LPUART_STAT_RWUID(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
+#define LPUART_STAT_RXINV_MASK                   (0x10000000U)
+#define LPUART_STAT_RXINV_SHIFT                  (28U)
+/*! RXINV - Receive Data Inversion
+ *  0b0..Receive data not inverted.
+ *  0b1..Receive data inverted.
+ */
+#define LPUART_STAT_RXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
+#define LPUART_STAT_MSBF_MASK                    (0x20000000U)
+#define LPUART_STAT_MSBF_SHIFT                   (29U)
+/*! MSBF - MSB First
+ *  0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
+ *  0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].
+ */
+#define LPUART_STAT_MSBF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
+#define LPUART_STAT_RXEDGIF_MASK                 (0x40000000U)
+#define LPUART_STAT_RXEDGIF_SHIFT                (30U)
+/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag
+ *  0b0..No active edge on the receive pin has occurred.
+ *  0b1..An active edge on the receive pin has occurred.
+ */
+#define LPUART_STAT_RXEDGIF(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
+#define LPUART_STAT_LBKDIF_MASK                  (0x80000000U)
+#define LPUART_STAT_LBKDIF_SHIFT                 (31U)
+/*! LBKDIF - LIN Break Detect Interrupt Flag
+ *  0b0..No LIN break character has been detected.
+ *  0b1..LIN break character has been detected.
+ */
+#define LPUART_STAT_LBKDIF(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
+/*! @} */
+
+/*! @name CTRL - LPUART Control Register */
+/*! @{ */
+#define LPUART_CTRL_PT_MASK                      (0x1U)
+#define LPUART_CTRL_PT_SHIFT                     (0U)
+/*! PT - Parity Type
+ *  0b0..Even parity.
+ *  0b1..Odd parity.
+ */
+#define LPUART_CTRL_PT(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
+#define LPUART_CTRL_PE_MASK                      (0x2U)
+#define LPUART_CTRL_PE_SHIFT                     (1U)
+/*! PE - Parity Enable
+ *  0b0..No hardware parity generation or checking.
+ *  0b1..Parity enabled.
+ */
+#define LPUART_CTRL_PE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
+#define LPUART_CTRL_ILT_MASK                     (0x4U)
+#define LPUART_CTRL_ILT_SHIFT                    (2U)
+/*! ILT - Idle Line Type Select
+ *  0b0..Idle character bit count starts after start bit.
+ *  0b1..Idle character bit count starts after stop bit.
+ */
+#define LPUART_CTRL_ILT(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
+#define LPUART_CTRL_WAKE_MASK                    (0x8U)
+#define LPUART_CTRL_WAKE_SHIFT                   (3U)
+/*! WAKE - Receiver Wakeup Method Select
+ *  0b0..Configures RWU for idle-line wakeup.
+ *  0b1..Configures RWU with address-mark wakeup.
+ */
+#define LPUART_CTRL_WAKE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
+#define LPUART_CTRL_M_MASK                       (0x10U)
+#define LPUART_CTRL_M_SHIFT                      (4U)
+/*! M - 9-Bit or 8-Bit Mode Select
+ *  0b0..Receiver and transmitter use 8-bit data characters.
+ *  0b1..Receiver and transmitter use 9-bit data characters.
+ */
+#define LPUART_CTRL_M(x)                         (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
+#define LPUART_CTRL_RSRC_MASK                    (0x20U)
+#define LPUART_CTRL_RSRC_SHIFT                   (5U)
+/*! RSRC - Receiver Source Select
+ *  0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin.
+ *  0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input.
+ */
+#define LPUART_CTRL_RSRC(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
+#define LPUART_CTRL_DOZEEN_MASK                  (0x40U)
+#define LPUART_CTRL_DOZEEN_SHIFT                 (6U)
+/*! DOZEEN - Doze Enable
+ *  0b0..LPUART is enabled in Doze mode.
+ *  0b1..LPUART is disabled in Doze mode.
+ */
+#define LPUART_CTRL_DOZEEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
+#define LPUART_CTRL_LOOPS_MASK                   (0x80U)
+#define LPUART_CTRL_LOOPS_SHIFT                  (7U)
+/*! LOOPS - Loop Mode Select
+ *  0b0..Normal operation - RXD and TXD use separate pins.
+ *  0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
+ */
+#define LPUART_CTRL_LOOPS(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
+#define LPUART_CTRL_IDLECFG_MASK                 (0x700U)
+#define LPUART_CTRL_IDLECFG_SHIFT                (8U)
+/*! IDLECFG - Idle Configuration
+ *  0b000..1 idle character
+ *  0b001..2 idle characters
+ *  0b010..4 idle characters
+ *  0b011..8 idle characters
+ *  0b100..16 idle characters
+ *  0b101..32 idle characters
+ *  0b110..64 idle characters
+ *  0b111..128 idle characters
+ */
+#define LPUART_CTRL_IDLECFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
+#define LPUART_CTRL_M7_MASK                      (0x800U)
+#define LPUART_CTRL_M7_SHIFT                     (11U)
+/*! M7 - 7-Bit Mode Select
+ *  0b0..Receiver and transmitter use 8-bit to 10-bit data characters.
+ *  0b1..Receiver and transmitter use 7-bit data characters.
+ */
+#define LPUART_CTRL_M7(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)
+#define LPUART_CTRL_MA2IE_MASK                   (0x4000U)
+#define LPUART_CTRL_MA2IE_SHIFT                  (14U)
+/*! MA2IE - Match 2 Interrupt Enable
+ *  0b0..MA2F interrupt disabled
+ *  0b1..MA2F interrupt enabled
+ */
+#define LPUART_CTRL_MA2IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
+#define LPUART_CTRL_MA1IE_MASK                   (0x8000U)
+#define LPUART_CTRL_MA1IE_SHIFT                  (15U)
+/*! MA1IE - Match 1 Interrupt Enable
+ *  0b0..MA1F interrupt disabled
+ *  0b1..MA1F interrupt enabled
+ */
+#define LPUART_CTRL_MA1IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
+#define LPUART_CTRL_SBK_MASK                     (0x10000U)
+#define LPUART_CTRL_SBK_SHIFT                    (16U)
+/*! SBK - Send Break
+ *  0b0..Normal transmitter operation.
+ *  0b1..Queue break character(s) to be sent.
+ */
+#define LPUART_CTRL_SBK(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
+#define LPUART_CTRL_RWU_MASK                     (0x20000U)
+#define LPUART_CTRL_RWU_SHIFT                    (17U)
+/*! RWU - Receiver Wakeup Control
+ *  0b0..Normal receiver operation.
+ *  0b1..LPUART receiver in standby waiting for wakeup condition.
+ */
+#define LPUART_CTRL_RWU(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
+#define LPUART_CTRL_RE_MASK                      (0x40000U)
+#define LPUART_CTRL_RE_SHIFT                     (18U)
+/*! RE - Receiver Enable
+ *  0b0..Receiver disabled.
+ *  0b1..Receiver enabled.
+ */
+#define LPUART_CTRL_RE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
+#define LPUART_CTRL_TE_MASK                      (0x80000U)
+#define LPUART_CTRL_TE_SHIFT                     (19U)
+/*! TE - Transmitter Enable
+ *  0b0..Transmitter disabled.
+ *  0b1..Transmitter enabled.
+ */
+#define LPUART_CTRL_TE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
+#define LPUART_CTRL_ILIE_MASK                    (0x100000U)
+#define LPUART_CTRL_ILIE_SHIFT                   (20U)
+/*! ILIE - Idle Line Interrupt Enable
+ *  0b0..Hardware interrupts from IDLE disabled; use polling.
+ *  0b1..Hardware interrupt requested when IDLE flag is 1.
+ */
+#define LPUART_CTRL_ILIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
+#define LPUART_CTRL_RIE_MASK                     (0x200000U)
+#define LPUART_CTRL_RIE_SHIFT                    (21U)
+/*! RIE - Receiver Interrupt Enable
+ *  0b0..Hardware interrupts from RDRF disabled; use polling.
+ *  0b1..Hardware interrupt requested when RDRF flag is 1.
+ */
+#define LPUART_CTRL_RIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
+#define LPUART_CTRL_TCIE_MASK                    (0x400000U)
+#define LPUART_CTRL_TCIE_SHIFT                   (22U)
+/*! TCIE - Transmission Complete Interrupt Enable for
+ *  0b0..Hardware interrupts from TC disabled; use polling.
+ *  0b1..Hardware interrupt requested when TC flag is 1.
+ */
+#define LPUART_CTRL_TCIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
+#define LPUART_CTRL_TIE_MASK                     (0x800000U)
+#define LPUART_CTRL_TIE_SHIFT                    (23U)
+/*! TIE - Transmit Interrupt Enable
+ *  0b0..Hardware interrupts from TDRE disabled; use polling.
+ *  0b1..Hardware interrupt requested when TDRE flag is 1.
+ */
+#define LPUART_CTRL_TIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
+#define LPUART_CTRL_PEIE_MASK                    (0x1000000U)
+#define LPUART_CTRL_PEIE_SHIFT                   (24U)
+/*! PEIE - Parity Error Interrupt Enable
+ *  0b0..PF interrupts disabled; use polling).
+ *  0b1..Hardware interrupt requested when PF is set.
+ */
+#define LPUART_CTRL_PEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
+#define LPUART_CTRL_FEIE_MASK                    (0x2000000U)
+#define LPUART_CTRL_FEIE_SHIFT                   (25U)
+/*! FEIE - Framing Error Interrupt Enable
+ *  0b0..FE interrupts disabled; use polling.
+ *  0b1..Hardware interrupt requested when FE is set.
+ */
+#define LPUART_CTRL_FEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
+#define LPUART_CTRL_NEIE_MASK                    (0x4000000U)
+#define LPUART_CTRL_NEIE_SHIFT                   (26U)
+/*! NEIE - Noise Error Interrupt Enable
+ *  0b0..NF interrupts disabled; use polling.
+ *  0b1..Hardware interrupt requested when NF is set.
+ */
+#define LPUART_CTRL_NEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
+#define LPUART_CTRL_ORIE_MASK                    (0x8000000U)
+#define LPUART_CTRL_ORIE_SHIFT                   (27U)
+/*! ORIE - Overrun Interrupt Enable
+ *  0b0..OR interrupts disabled; use polling.
+ *  0b1..Hardware interrupt requested when OR is set.
+ */
+#define LPUART_CTRL_ORIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
+#define LPUART_CTRL_TXINV_MASK                   (0x10000000U)
+#define LPUART_CTRL_TXINV_SHIFT                  (28U)
+/*! TXINV - Transmit Data Inversion
+ *  0b0..Transmit data not inverted.
+ *  0b1..Transmit data inverted.
+ */
+#define LPUART_CTRL_TXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
+#define LPUART_CTRL_TXDIR_MASK                   (0x20000000U)
+#define LPUART_CTRL_TXDIR_SHIFT                  (29U)
+/*! TXDIR - TXD Pin Direction in Single-Wire Mode
+ *  0b0..TXD pin is an input in single-wire mode.
+ *  0b1..TXD pin is an output in single-wire mode.
+ */
+#define LPUART_CTRL_TXDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
+#define LPUART_CTRL_R9T8_MASK                    (0x40000000U)
+#define LPUART_CTRL_R9T8_SHIFT                   (30U)
+#define LPUART_CTRL_R9T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
+#define LPUART_CTRL_R8T9_MASK                    (0x80000000U)
+#define LPUART_CTRL_R8T9_SHIFT                   (31U)
+#define LPUART_CTRL_R8T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
+/*! @} */
+
+/*! @name DATA - LPUART Data Register */
+/*! @{ */
+#define LPUART_DATA_R0T0_MASK                    (0x1U)
+#define LPUART_DATA_R0T0_SHIFT                   (0U)
+#define LPUART_DATA_R0T0(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
+#define LPUART_DATA_R1T1_MASK                    (0x2U)
+#define LPUART_DATA_R1T1_SHIFT                   (1U)
+#define LPUART_DATA_R1T1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
+#define LPUART_DATA_R2T2_MASK                    (0x4U)
+#define LPUART_DATA_R2T2_SHIFT                   (2U)
+#define LPUART_DATA_R2T2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
+#define LPUART_DATA_R3T3_MASK                    (0x8U)
+#define LPUART_DATA_R3T3_SHIFT                   (3U)
+#define LPUART_DATA_R3T3(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
+#define LPUART_DATA_R4T4_MASK                    (0x10U)
+#define LPUART_DATA_R4T4_SHIFT                   (4U)
+#define LPUART_DATA_R4T4(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
+#define LPUART_DATA_R5T5_MASK                    (0x20U)
+#define LPUART_DATA_R5T5_SHIFT                   (5U)
+#define LPUART_DATA_R5T5(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
+#define LPUART_DATA_R6T6_MASK                    (0x40U)
+#define LPUART_DATA_R6T6_SHIFT                   (6U)
+#define LPUART_DATA_R6T6(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
+#define LPUART_DATA_R7T7_MASK                    (0x80U)
+#define LPUART_DATA_R7T7_SHIFT                   (7U)
+#define LPUART_DATA_R7T7(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
+#define LPUART_DATA_R8T8_MASK                    (0x100U)
+#define LPUART_DATA_R8T8_SHIFT                   (8U)
+#define LPUART_DATA_R8T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
+#define LPUART_DATA_R9T9_MASK                    (0x200U)
+#define LPUART_DATA_R9T9_SHIFT                   (9U)
+#define LPUART_DATA_R9T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
+#define LPUART_DATA_IDLINE_MASK                  (0x800U)
+#define LPUART_DATA_IDLINE_SHIFT                 (11U)
+/*! IDLINE - Idle Line
+ *  0b0..Receiver was not idle before receiving this character.
+ *  0b1..Receiver was idle before receiving this character.
+ */
+#define LPUART_DATA_IDLINE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
+#define LPUART_DATA_RXEMPT_MASK                  (0x1000U)
+#define LPUART_DATA_RXEMPT_SHIFT                 (12U)
+/*! RXEMPT - Receive Buffer Empty
+ *  0b0..Receive buffer contains valid data.
+ *  0b1..Receive buffer is empty, data returned on read is not valid.
+ */
+#define LPUART_DATA_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
+#define LPUART_DATA_FRETSC_MASK                  (0x2000U)
+#define LPUART_DATA_FRETSC_SHIFT                 (13U)
+/*! FRETSC - Frame Error / Transmit Special Character
+ *  0b0..The dataword was received without a frame error on read, or transmit a normal character on write.
+ *  0b1..The dataword was received with a frame error, or transmit an idle or break character on transmit.
+ */
+#define LPUART_DATA_FRETSC(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
+#define LPUART_DATA_PARITYE_MASK                 (0x4000U)
+#define LPUART_DATA_PARITYE_SHIFT                (14U)
+/*! PARITYE - PARITYE
+ *  0b0..The dataword was received without a parity error.
+ *  0b1..The dataword was received with a parity error.
+ */
+#define LPUART_DATA_PARITYE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
+#define LPUART_DATA_NOISY_MASK                   (0x8000U)
+#define LPUART_DATA_NOISY_SHIFT                  (15U)
+/*! NOISY - NOISY
+ *  0b0..The dataword was received without noise.
+ *  0b1..The data was received with noise.
+ */
+#define LPUART_DATA_NOISY(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
+/*! @} */
+
+/*! @name MATCH - LPUART Match Address Register */
+/*! @{ */
+#define LPUART_MATCH_MA1_MASK                    (0x3FFU)
+#define LPUART_MATCH_MA1_SHIFT                   (0U)
+#define LPUART_MATCH_MA1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
+#define LPUART_MATCH_MA2_MASK                    (0x3FF0000U)
+#define LPUART_MATCH_MA2_SHIFT                   (16U)
+#define LPUART_MATCH_MA2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
+/*! @} */
+
+/*! @name MODIR - LPUART Modem IrDA Register */
+/*! @{ */
+#define LPUART_MODIR_TXCTSE_MASK                 (0x1U)
+#define LPUART_MODIR_TXCTSE_SHIFT                (0U)
+/*! TXCTSE - Transmitter clear-to-send enable
+ *  0b0..CTS has no effect on the transmitter.
+ *  0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
+ */
+#define LPUART_MODIR_TXCTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
+#define LPUART_MODIR_TXRTSE_MASK                 (0x2U)
+#define LPUART_MODIR_TXRTSE_SHIFT                (1U)
+/*! TXRTSE - Transmitter request-to-send enable
+ *  0b0..The transmitter has no effect on RTS.
+ *  0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit.
+ */
+#define LPUART_MODIR_TXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
+#define LPUART_MODIR_TXRTSPOL_MASK               (0x4U)
+#define LPUART_MODIR_TXRTSPOL_SHIFT              (2U)
+/*! TXRTSPOL - Transmitter request-to-send polarity
+ *  0b0..Transmitter RTS is active low.
+ *  0b1..Transmitter RTS is active high.
+ */
+#define LPUART_MODIR_TXRTSPOL(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
+#define LPUART_MODIR_RXRTSE_MASK                 (0x8U)
+#define LPUART_MODIR_RXRTSE_SHIFT                (3U)
+/*! RXRTSE - Receiver request-to-send enable
+ *  0b0..The receiver has no effect on RTS.
+ *  0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full.
+ */
+#define LPUART_MODIR_RXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
+#define LPUART_MODIR_TXCTSC_MASK                 (0x10U)
+#define LPUART_MODIR_TXCTSC_SHIFT                (4U)
+/*! TXCTSC - Transmit CTS Configuration
+ *  0b0..CTS input is sampled at the start of each character.
+ *  0b1..CTS input is sampled when the transmitter is idle.
+ */
+#define LPUART_MODIR_TXCTSC(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
+#define LPUART_MODIR_TXCTSSRC_MASK               (0x20U)
+#define LPUART_MODIR_TXCTSSRC_SHIFT              (5U)
+/*! TXCTSSRC - Transmit CTS Source
+ *  0b0..CTS input is the CTS_B pin.
+ *  0b1..CTS input is the inverted Receiver Match result.
+ */
+#define LPUART_MODIR_TXCTSSRC(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
+#define LPUART_MODIR_RTSWATER_MASK               (0x700U)
+#define LPUART_MODIR_RTSWATER_SHIFT              (8U)
+#define LPUART_MODIR_RTSWATER(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
+#define LPUART_MODIR_TNP_MASK                    (0x30000U)
+#define LPUART_MODIR_TNP_SHIFT                   (16U)
+/*! TNP - Transmitter narrow pulse
+ *  0b00..1/OSR.
+ *  0b01..2/OSR.
+ *  0b10..3/OSR.
+ *  0b11..4/OSR.
+ */
+#define LPUART_MODIR_TNP(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
+#define LPUART_MODIR_IREN_MASK                   (0x40000U)
+#define LPUART_MODIR_IREN_SHIFT                  (18U)
+/*! IREN - Infrared enable
+ *  0b0..IR disabled.
+ *  0b1..IR enabled.
+ */
+#define LPUART_MODIR_IREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
+/*! @} */
+
+/*! @name FIFO - LPUART FIFO Register */
+/*! @{ */
+#define LPUART_FIFO_RXFIFOSIZE_MASK              (0x7U)
+#define LPUART_FIFO_RXFIFOSIZE_SHIFT             (0U)
+/*! RXFIFOSIZE - Receive FIFO. Buffer Depth
+ *  0b000..Receive FIFO/Buffer depth = 1 dataword.
+ *  0b001..Receive FIFO/Buffer depth = 4 datawords.
+ *  0b010..Receive FIFO/Buffer depth = 8 datawords.
+ *  0b011..Receive FIFO/Buffer depth = 16 datawords.
+ *  0b100..Receive FIFO/Buffer depth = 32 datawords.
+ *  0b101..Receive FIFO/Buffer depth = 64 datawords.
+ *  0b110..Receive FIFO/Buffer depth = 128 datawords.
+ *  0b111..Receive FIFO/Buffer depth = 256 datawords.
+ */
+#define LPUART_FIFO_RXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
+#define LPUART_FIFO_RXFE_MASK                    (0x8U)
+#define LPUART_FIFO_RXFE_SHIFT                   (3U)
+/*! RXFE - Receive FIFO Enable
+ *  0b0..Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
+ *  0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
+ */
+#define LPUART_FIFO_RXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
+#define LPUART_FIFO_TXFIFOSIZE_MASK              (0x70U)
+#define LPUART_FIFO_TXFIFOSIZE_SHIFT             (4U)
+/*! TXFIFOSIZE - Transmit FIFO. Buffer Depth
+ *  0b000..Transmit FIFO/Buffer depth = 1 dataword.
+ *  0b001..Transmit FIFO/Buffer depth = 4 datawords.
+ *  0b010..Transmit FIFO/Buffer depth = 8 datawords.
+ *  0b011..Transmit FIFO/Buffer depth = 16 datawords.
+ *  0b100..Transmit FIFO/Buffer depth = 32 datawords.
+ *  0b101..Transmit FIFO/Buffer depth = 64 datawords.
+ *  0b110..Transmit FIFO/Buffer depth = 128 datawords.
+ *  0b111..Transmit FIFO/Buffer depth = 256 datawords
+ */
+#define LPUART_FIFO_TXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
+#define LPUART_FIFO_TXFE_MASK                    (0x80U)
+#define LPUART_FIFO_TXFE_SHIFT                   (7U)
+/*! TXFE - Transmit FIFO Enable
+ *  0b0..Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
+ *  0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
+ */
+#define LPUART_FIFO_TXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
+#define LPUART_FIFO_RXUFE_MASK                   (0x100U)
+#define LPUART_FIFO_RXUFE_SHIFT                  (8U)
+/*! RXUFE - Receive FIFO Underflow Interrupt Enable
+ *  0b0..RXUF flag does not generate an interrupt to the host.
+ *  0b1..RXUF flag generates an interrupt to the host.
+ */
+#define LPUART_FIFO_RXUFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
+#define LPUART_FIFO_TXOFE_MASK                   (0x200U)
+#define LPUART_FIFO_TXOFE_SHIFT                  (9U)
+/*! TXOFE - Transmit FIFO Overflow Interrupt Enable
+ *  0b0..TXOF flag does not generate an interrupt to the host.
+ *  0b1..TXOF flag generates an interrupt to the host.
+ */
+#define LPUART_FIFO_TXOFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
+#define LPUART_FIFO_RXIDEN_MASK                  (0x1C00U)
+#define LPUART_FIFO_RXIDEN_SHIFT                 (10U)
+/*! RXIDEN - Receiver Idle Empty Enable
+ *  0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle.
+ *  0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character.
+ *  0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters.
+ *  0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters.
+ *  0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters.
+ *  0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters.
+ *  0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters.
+ *  0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.
+ */
+#define LPUART_FIFO_RXIDEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
+#define LPUART_FIFO_RXFLUSH_MASK                 (0x4000U)
+#define LPUART_FIFO_RXFLUSH_SHIFT                (14U)
+/*! RXFLUSH - Receive FIFO/Buffer Flush
+ *  0b0..No flush operation occurs.
+ *  0b1..All data in the receive FIFO/buffer is cleared out.
+ */
+#define LPUART_FIFO_RXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
+#define LPUART_FIFO_TXFLUSH_MASK                 (0x8000U)
+#define LPUART_FIFO_TXFLUSH_SHIFT                (15U)
+/*! TXFLUSH - Transmit FIFO/Buffer Flush
+ *  0b0..No flush operation occurs.
+ *  0b1..All data in the transmit FIFO/Buffer is cleared out.
+ */
+#define LPUART_FIFO_TXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
+#define LPUART_FIFO_RXUF_MASK                    (0x10000U)
+#define LPUART_FIFO_RXUF_SHIFT                   (16U)
+/*! RXUF - Receiver Buffer Underflow Flag
+ *  0b0..No receive buffer underflow has occurred since the last time the flag was cleared.
+ *  0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared.
+ */
+#define LPUART_FIFO_RXUF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
+#define LPUART_FIFO_TXOF_MASK                    (0x20000U)
+#define LPUART_FIFO_TXOF_SHIFT                   (17U)
+/*! TXOF - Transmitter Buffer Overflow Flag
+ *  0b0..No transmit buffer overflow has occurred since the last time the flag was cleared.
+ *  0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared.
+ */
+#define LPUART_FIFO_TXOF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
+#define LPUART_FIFO_RXEMPT_MASK                  (0x400000U)
+#define LPUART_FIFO_RXEMPT_SHIFT                 (22U)
+/*! RXEMPT - Receive Buffer/FIFO Empty
+ *  0b0..Receive buffer is not empty.
+ *  0b1..Receive buffer is empty.
+ */
+#define LPUART_FIFO_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
+#define LPUART_FIFO_TXEMPT_MASK                  (0x800000U)
+#define LPUART_FIFO_TXEMPT_SHIFT                 (23U)
+/*! TXEMPT - Transmit Buffer/FIFO Empty
+ *  0b0..Transmit buffer is not empty.
+ *  0b1..Transmit buffer is empty.
+ */
+#define LPUART_FIFO_TXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
+/*! @} */
+
+/*! @name WATER - LPUART Watermark Register */
+/*! @{ */
+#define LPUART_WATER_TXWATER_MASK                (0x7U)
+#define LPUART_WATER_TXWATER_SHIFT               (0U)
+#define LPUART_WATER_TXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
+#define LPUART_WATER_TXCOUNT_MASK                (0xF00U)
+#define LPUART_WATER_TXCOUNT_SHIFT               (8U)
+#define LPUART_WATER_TXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
+#define LPUART_WATER_RXWATER_MASK                (0x70000U)
+#define LPUART_WATER_RXWATER_SHIFT               (16U)
+#define LPUART_WATER_RXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
+#define LPUART_WATER_RXCOUNT_MASK                (0xF000000U)
+#define LPUART_WATER_RXCOUNT_SHIFT               (24U)
+#define LPUART_WATER_RXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LPUART_Register_Masks */
+
+
+/* LPUART - Peripheral instance base addresses */
+/** Peripheral LPUART0 base address */
+#define LPUART0_BASE                             (0x40042000u)
+/** Peripheral LPUART0 base pointer */
+#define LPUART0                                  ((LPUART_Type *)LPUART0_BASE)
+/** Peripheral LPUART1 base address */
+#define LPUART1_BASE                             (0x40043000u)
+/** Peripheral LPUART1 base pointer */
+#define LPUART1                                  ((LPUART_Type *)LPUART1_BASE)
+/** Peripheral LPUART2 base address */
+#define LPUART2_BASE                             (0x40044000u)
+/** Peripheral LPUART2 base pointer */
+#define LPUART2                                  ((LPUART_Type *)LPUART2_BASE)
+/** Peripheral LPUART3 base address */
+#define LPUART3_BASE                             (0x41036000u)
+/** Peripheral LPUART3 base pointer */
+#define LPUART3                                  ((LPUART_Type *)LPUART3_BASE)
+/** Array initializer of LPUART peripheral base addresses */
+#define LPUART_BASE_ADDRS                        { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE }
+/** Array initializer of LPUART peripheral base pointers */
+#define LPUART_BASE_PTRS                         { LPUART0, LPUART1, LPUART2, LPUART3 }
+/** Interrupt vectors for the LPUART peripheral type */
+#define LPUART_RX_TX_IRQS                        { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn }
+#define LPUART_ERR_IRQS                          { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPUART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[8];
+  __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+  __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+  __IO uint32_t CPCR;                              /**< Core Platform Control Register, offset: 0xC */
+  __IO uint32_t ISCR;                              /**< Interrupt Status and Control Register, offset: 0x10 */
+       uint8_t RESERVED_1[32];
+  __IO uint32_t CPCR2;                             /**< Core Platform Control Register 2, offset: 0x34 */
+       uint8_t RESERVED_2[8];
+  __IO uint32_t CPO;                               /**< Compute Operation Control Register, offset: 0x40 */
+} MCM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
+/*! @{ */
+#define MCM_PLASC_ASC_MASK                       (0xFFU)
+#define MCM_PLASC_ASC_SHIFT                      (0U)
+#define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
+/*! @} */
+
+/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
+/*! @{ */
+#define MCM_PLAMC_AMC_MASK                       (0xFFU)
+#define MCM_PLAMC_AMC_SHIFT                      (0U)
+#define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
+/*! @} */
+
+/*! @name CPCR - Core Platform Control Register */
+/*! @{ */
+#define MCM_CPCR_CBRR_MASK                       (0x200U)
+#define MCM_CPCR_CBRR_SHIFT                      (9U)
+/*! CBRR - Crossbar round-robin arbitration enable
+ *  0b0..Fixed-priority arbitration
+ *  0b1..Round-robin arbitration
+ */
+#define MCM_CPCR_CBRR(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_CPCR_CBRR_SHIFT)) & MCM_CPCR_CBRR_MASK)
+/*! @} */
+
+/*! @name ISCR - Interrupt Status and Control Register */
+/*! @{ */
+#define MCM_ISCR_FIOC_MASK                       (0x100U)
+#define MCM_ISCR_FIOC_SHIFT                      (8U)
+/*! FIOC - FPU invalid operation interrupt status
+ *  0b0..No interrupt
+ *  0b1..Interrupt occurred
+ */
+#define MCM_ISCR_FIOC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
+#define MCM_ISCR_FDZC_MASK                       (0x200U)
+#define MCM_ISCR_FDZC_SHIFT                      (9U)
+/*! FDZC - FPU divide-by-zero interrupt status
+ *  0b0..No interrupt
+ *  0b1..Interrupt occurred
+ */
+#define MCM_ISCR_FDZC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
+#define MCM_ISCR_FOFC_MASK                       (0x400U)
+#define MCM_ISCR_FOFC_SHIFT                      (10U)
+/*! FOFC - FPU overflow interrupt status
+ *  0b0..No interrupt
+ *  0b1..Interrupt occurred
+ */
+#define MCM_ISCR_FOFC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
+#define MCM_ISCR_FUFC_MASK                       (0x800U)
+#define MCM_ISCR_FUFC_SHIFT                      (11U)
+/*! FUFC - FPU underflow interrupt status
+ *  0b0..No interrupt
+ *  0b1..Interrupt occurred
+ */
+#define MCM_ISCR_FUFC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
+#define MCM_ISCR_FIXC_MASK                       (0x1000U)
+#define MCM_ISCR_FIXC_SHIFT                      (12U)
+/*! FIXC - FPU inexact interrupt status
+ *  0b0..No interrupt
+ *  0b1..Interrupt occurred
+ */
+#define MCM_ISCR_FIXC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
+#define MCM_ISCR_FIDC_MASK                       (0x8000U)
+#define MCM_ISCR_FIDC_SHIFT                      (15U)
+/*! FIDC - FPU input denormal interrupt status
+ *  0b0..No interrupt
+ *  0b1..Interrupt occurred
+ */
+#define MCM_ISCR_FIDC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
+#define MCM_ISCR_FIOCE_MASK                      (0x1000000U)
+#define MCM_ISCR_FIOCE_SHIFT                     (24U)
+/*! FIOCE - FPU invalid operation interrupt enable
+ *  0b0..Disable interrupt
+ *  0b1..Enable interrupt
+ */
+#define MCM_ISCR_FIOCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
+#define MCM_ISCR_FDZCE_MASK                      (0x2000000U)
+#define MCM_ISCR_FDZCE_SHIFT                     (25U)
+/*! FDZCE - FPU divide-by-zero interrupt enable
+ *  0b0..Disable interrupt
+ *  0b1..Enable interrupt
+ */
+#define MCM_ISCR_FDZCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
+#define MCM_ISCR_FOFCE_MASK                      (0x4000000U)
+#define MCM_ISCR_FOFCE_SHIFT                     (26U)
+/*! FOFCE - FPU overflow interrupt enable
+ *  0b0..Disable interrupt
+ *  0b1..Enable interrupt
+ */
+#define MCM_ISCR_FOFCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
+#define MCM_ISCR_FUFCE_MASK                      (0x8000000U)
+#define MCM_ISCR_FUFCE_SHIFT                     (27U)
+/*! FUFCE - FPU underflow interrupt enable
+ *  0b0..Disable interrupt
+ *  0b1..Enable interrupt
+ */
+#define MCM_ISCR_FUFCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
+#define MCM_ISCR_FIXCE_MASK                      (0x10000000U)
+#define MCM_ISCR_FIXCE_SHIFT                     (28U)
+/*! FIXCE - FPU inexact interrupt enable
+ *  0b0..Disable interrupt
+ *  0b1..Enable interrupt
+ */
+#define MCM_ISCR_FIXCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
+#define MCM_ISCR_FIDCE_MASK                      (0x80000000U)
+#define MCM_ISCR_FIDCE_SHIFT                     (31U)
+/*! FIDCE - FPU input denormal interrupt enable
+ *  0b0..Disable interrupt
+ *  0b1..Enable interrupt
+ */
+#define MCM_ISCR_FIDCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
+/*! @} */
+
+/*! @name CPCR2 - Core Platform Control Register 2 */
+/*! @{ */
+#define MCM_CPCR2_CCBC_MASK                      (0x1U)
+#define MCM_CPCR2_CCBC_SHIFT                     (0U)
+/*! CCBC - Clear code bus cache, this field always reads as 0.
+ *  0b0..No effect
+ *  0b1..Clear code bus cache
+ */
+#define MCM_CPCR2_CCBC(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_CCBC_SHIFT)) & MCM_CPCR2_CCBC_MASK)
+#define MCM_CPCR2_DCBC_MASK                      (0x8U)
+#define MCM_CPCR2_DCBC_SHIFT                     (3U)
+/*! DCBC - Disable code bus cache
+ *  0b0..Enable code bus cache
+ *  0b1..Disable code bus cache
+ */
+#define MCM_CPCR2_DCBC(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_DCBC_SHIFT)) & MCM_CPCR2_DCBC_MASK)
+#define MCM_CPCR2_CBCS_MASK                      (0xF0U)
+#define MCM_CPCR2_CBCS_SHIFT                     (4U)
+/*! CBCS - Code Bus Cache Size
+ *  0b0000..0 KB
+ *  0b0001..1 KB
+ *  0b0010..2 KB
+ *  0b0011..4 KB
+ *  0b0100..8 KB
+ *  0b0101..16 KB
+ *  0b0110..32 KB
+ */
+#define MCM_CPCR2_CBCS(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_CBCS_SHIFT)) & MCM_CPCR2_CBCS_MASK)
+#define MCM_CPCR2_PCCMCTRL_MASK                  (0x10000U)
+#define MCM_CPCR2_PCCMCTRL_SHIFT                 (16U)
+/*! PCCMCTRL - Bypass fixed code cache map
+ *  0b0..The fixed code cache map is not bypassed
+ *  0b1..The fixed code cache map is bypassed
+ */
+#define MCM_CPCR2_PCCMCTRL(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_PCCMCTRL_SHIFT)) & MCM_CPCR2_PCCMCTRL_MASK)
+#define MCM_CPCR2_LCCPWB_MASK                    (0x20000U)
+#define MCM_CPCR2_LCCPWB_SHIFT                   (17U)
+/*! LCCPWB - Limit code cache peripheral write buffering
+ *  0b0..Code cache peripheral write buffering is not limited
+ *  0b1..Code cache peripheral write buffering is limited
+ */
+#define MCM_CPCR2_LCCPWB(x)                      (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_LCCPWB_SHIFT)) & MCM_CPCR2_LCCPWB_MASK)
+/*! @} */
+
+/*! @name CPO - Compute Operation Control Register */
+/*! @{ */
+#define MCM_CPO_CPOREQ_MASK                      (0x1U)
+#define MCM_CPO_CPOREQ_SHIFT                     (0U)
+/*! CPOREQ - Compute Operation request
+ *  0b0..Request is cleared.
+ *  0b1..Request Compute Operation.
+ */
+#define MCM_CPO_CPOREQ(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
+#define MCM_CPO_CPOACK_MASK                      (0x2U)
+#define MCM_CPO_CPOACK_SHIFT                     (1U)
+/*! CPOACK - Compute Operation acknowledge
+ *  0b0..Compute operation entry has not completed or compute operation exit has completed.
+ *  0b1..Compute operation entry has completed or compute operation exit has not completed.
+ */
+#define MCM_CPO_CPOACK(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
+#define MCM_CPO_CPOWOI_MASK                      (0x4U)
+#define MCM_CPO_CPOWOI_SHIFT                     (2U)
+/*! CPOWOI - Compute Operation wakeup on interrupt
+ *  0b0..No effect.
+ *  0b1..When set, the CPOREQ is cleared on any interrupt or exception vector fetch.
+ */
+#define MCM_CPO_CPOWOI(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM0 base address */
+#define MCM0_BASE                                (0xE0080000u)
+/** Peripheral MCM0 base pointer */
+#define MCM0                                     ((MCM_Type *)MCM0_BASE)
+/** Array initializer of MCM peripheral base addresses */
+#define MCM_BASE_ADDRS                           { MCM0_BASE }
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASE_PTRS                            { MCM0 }
+/** Interrupt vectors for the MCM peripheral type */
+#define MCM_IRQS                                 { CTI0_MCM0_IRQn }
+/* MCM compatibility definitions */
+#define MCM_BASE                  MCM0_BASE
+#define MCM                       MCM0
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MSCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MSCM_Peripheral_Access_Layer MSCM Peripheral Access Layer
+ * @{
+ */
+
+/** MSCM - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t CPXTYPE;                           /**< Processor X Type Register, offset: 0x0 */
+  __I  uint32_t CPXNUM;                            /**< Processor X Number Register, offset: 0x4 */
+  __I  uint32_t CPXMASTER;                         /**< Processor X Master Register, offset: 0x8 */
+  __I  uint32_t CPXCOUNT;                          /**< Processor X Count Register, offset: 0xC */
+  __I  uint32_t CPXCFG0;                           /**< Processor X Configuration Register 0, offset: 0x10 */
+  __I  uint32_t CPXCFG1;                           /**< Processor X Configuration Register 1, offset: 0x14 */
+  __I  uint32_t CPXCFG2;                           /**< Processor X Configuration Register 2, offset: 0x18 */
+  __I  uint32_t CPXCFG3;                           /**< Processor X Configuration Register 3, offset: 0x1C */
+  struct {                                         /* offset: 0x20, array step: 0x20 */
+    __I  uint32_t TYPE;                              /**< Processor 0 Type Register..Processor 1 Type Register, array offset: 0x20, array step: 0x20 */
+    __I  uint32_t NUM;                               /**< Processor 0 Number Register..Processor 1 Number Register, array offset: 0x24, array step: 0x20 */
+    __I  uint32_t MASTER;                            /**< Processor 0 Master Register..Processor 1 Master Register, array offset: 0x28, array step: 0x20 */
+    __I  uint32_t COUNT;                             /**< Processor 0 Count Register..Processor 1 Count Register, array offset: 0x2C, array step: 0x20 */
+    __I  uint32_t CFG0;                              /**< Processor 0 Configuration Register 0..Processor 1 Configuration Register 0, array offset: 0x30, array step: 0x20 */
+    __I  uint32_t CFG1;                              /**< Processor 0 Configuration Register 1..Processor 1 Configuration Register 1, array offset: 0x34, array step: 0x20 */
+    __I  uint32_t CFG2;                              /**< Processor 0 Configuration Register 2..Processor 1 Configuration Register 2, array offset: 0x38, array step: 0x20 */
+    __I  uint32_t CFG3;                              /**< Processor 0 Configuration Register 3..Processor 1 Configuration Register 3, array offset: 0x3C, array step: 0x20 */
+  } CP[2];
+       uint8_t RESERVED_0[928];
+  __IO uint32_t OCMDR0;                            /**< On-Chip Memory Descriptor Register, offset: 0x400 */
+  __IO uint32_t OCMDR1;                            /**< On-Chip Memory Descriptor Register, offset: 0x404 */
+  __IO uint32_t OCMDR2;                            /**< On-Chip Memory Descriptor Register, offset: 0x408 */
+  __IO uint32_t OCMDR3;                            /**< On-Chip Memory Descriptor Register, offset: 0x40C */
+} MSCM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MSCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MSCM_Register_Masks MSCM Register Masks
+ * @{
+ */
+
+/*! @name CPXTYPE - Processor X Type Register */
+/*! @{ */
+#define MSCM_CPXTYPE_RYPZ_MASK                   (0xFFU)
+#define MSCM_CPXTYPE_RYPZ_SHIFT                  (0U)
+#define MSCM_CPXTYPE_RYPZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXTYPE_RYPZ_SHIFT)) & MSCM_CPXTYPE_RYPZ_MASK)
+#define MSCM_CPXTYPE_PERSONALITY_MASK            (0xFFFFFF00U)
+#define MSCM_CPXTYPE_PERSONALITY_SHIFT           (8U)
+#define MSCM_CPXTYPE_PERSONALITY(x)              (((uint32_t)(((uint32_t)(x)) << MSCM_CPXTYPE_PERSONALITY_SHIFT)) & MSCM_CPXTYPE_PERSONALITY_MASK)
+/*! @} */
+
+/*! @name CPXNUM - Processor X Number Register */
+/*! @{ */
+#define MSCM_CPXNUM_CPN_MASK                     (0x1U)
+#define MSCM_CPXNUM_CPN_SHIFT                    (0U)
+#define MSCM_CPXNUM_CPN(x)                       (((uint32_t)(((uint32_t)(x)) << MSCM_CPXNUM_CPN_SHIFT)) & MSCM_CPXNUM_CPN_MASK)
+/*! @} */
+
+/*! @name CPXMASTER - Processor X Master Register */
+/*! @{ */
+#define MSCM_CPXMASTER_PPMN_MASK                 (0x3FU)
+#define MSCM_CPXMASTER_PPMN_SHIFT                (0U)
+#define MSCM_CPXMASTER_PPMN(x)                   (((uint32_t)(((uint32_t)(x)) << MSCM_CPXMASTER_PPMN_SHIFT)) & MSCM_CPXMASTER_PPMN_MASK)
+/*! @} */
+
+/*! @name CPXCOUNT - Processor X Count Register */
+/*! @{ */
+#define MSCM_CPXCOUNT_PCNT_MASK                  (0x3U)
+#define MSCM_CPXCOUNT_PCNT_SHIFT                 (0U)
+#define MSCM_CPXCOUNT_PCNT(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCOUNT_PCNT_SHIFT)) & MSCM_CPXCOUNT_PCNT_MASK)
+/*! @} */
+
+/*! @name CPXCFG0 - Processor X Configuration Register 0 */
+/*! @{ */
+#define MSCM_CPXCFG0_DCWY_MASK                   (0xFFU)
+#define MSCM_CPXCFG0_DCWY_SHIFT                  (0U)
+#define MSCM_CPXCFG0_DCWY(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_DCWY_SHIFT)) & MSCM_CPXCFG0_DCWY_MASK)
+#define MSCM_CPXCFG0_DCSZ_MASK                   (0xFF00U)
+#define MSCM_CPXCFG0_DCSZ_SHIFT                  (8U)
+#define MSCM_CPXCFG0_DCSZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_DCSZ_SHIFT)) & MSCM_CPXCFG0_DCSZ_MASK)
+#define MSCM_CPXCFG0_ICWY_MASK                   (0xFF0000U)
+#define MSCM_CPXCFG0_ICWY_SHIFT                  (16U)
+#define MSCM_CPXCFG0_ICWY(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_ICWY_SHIFT)) & MSCM_CPXCFG0_ICWY_MASK)
+#define MSCM_CPXCFG0_ICSZ_MASK                   (0xFF000000U)
+#define MSCM_CPXCFG0_ICSZ_SHIFT                  (24U)
+#define MSCM_CPXCFG0_ICSZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_ICSZ_SHIFT)) & MSCM_CPXCFG0_ICSZ_MASK)
+/*! @} */
+
+/*! @name CPXCFG1 - Processor X Configuration Register 1 */
+/*! @{ */
+#define MSCM_CPXCFG1_L2WY_MASK                   (0xFF0000U)
+#define MSCM_CPXCFG1_L2WY_SHIFT                  (16U)
+#define MSCM_CPXCFG1_L2WY(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG1_L2WY_SHIFT)) & MSCM_CPXCFG1_L2WY_MASK)
+#define MSCM_CPXCFG1_L2SZ_MASK                   (0xFF000000U)
+#define MSCM_CPXCFG1_L2SZ_SHIFT                  (24U)
+#define MSCM_CPXCFG1_L2SZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG1_L2SZ_SHIFT)) & MSCM_CPXCFG1_L2SZ_MASK)
+/*! @} */
+
+/*! @name CPXCFG2 - Processor X Configuration Register 2 */
+/*! @{ */
+#define MSCM_CPXCFG2_TMUSZ_MASK                  (0xFF00U)
+#define MSCM_CPXCFG2_TMUSZ_SHIFT                 (8U)
+#define MSCM_CPXCFG2_TMUSZ(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG2_TMUSZ_SHIFT)) & MSCM_CPXCFG2_TMUSZ_MASK)
+#define MSCM_CPXCFG2_TMLSZ_MASK                  (0xFF000000U)
+#define MSCM_CPXCFG2_TMLSZ_SHIFT                 (24U)
+#define MSCM_CPXCFG2_TMLSZ(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG2_TMLSZ_SHIFT)) & MSCM_CPXCFG2_TMLSZ_MASK)
+/*! @} */
+
+/*! @name CPXCFG3 - Processor X Configuration Register 3 */
+/*! @{ */
+#define MSCM_CPXCFG3_FPU_MASK                    (0x1U)
+#define MSCM_CPXCFG3_FPU_SHIFT                   (0U)
+/*! FPU - Floating Point Unit
+ *  0b0..FPU support is not included.
+ *  0b1..FPU support is included.
+ */
+#define MSCM_CPXCFG3_FPU(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_FPU_SHIFT)) & MSCM_CPXCFG3_FPU_MASK)
+#define MSCM_CPXCFG3_SIMD_MASK                   (0x2U)
+#define MSCM_CPXCFG3_SIMD_SHIFT                  (1U)
+/*! SIMD - SIMD/NEON instruction support
+ *  0b0..SIMD/NEON support is not included.
+ *  0b1..SIMD/NEON support is included.
+ */
+#define MSCM_CPXCFG3_SIMD(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_SIMD_SHIFT)) & MSCM_CPXCFG3_SIMD_MASK)
+#define MSCM_CPXCFG3_JAZ_MASK                    (0x4U)
+#define MSCM_CPXCFG3_JAZ_SHIFT                   (2U)
+/*! JAZ - Jazelle support
+ *  0b0..Jazelle support is not included.
+ *  0b1..Jazelle support is included.
+ */
+#define MSCM_CPXCFG3_JAZ(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_JAZ_SHIFT)) & MSCM_CPXCFG3_JAZ_MASK)
+#define MSCM_CPXCFG3_MMU_MASK                    (0x8U)
+#define MSCM_CPXCFG3_MMU_SHIFT                   (3U)
+/*! MMU - Memory Management Unit
+ *  0b0..MMU support is not included.
+ *  0b1..MMU support is included.
+ */
+#define MSCM_CPXCFG3_MMU(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_MMU_SHIFT)) & MSCM_CPXCFG3_MMU_MASK)
+#define MSCM_CPXCFG3_TZ_MASK                     (0x10U)
+#define MSCM_CPXCFG3_TZ_SHIFT                    (4U)
+/*! TZ - Trust Zone
+ *  0b0..Trust Zone support is not included.
+ *  0b1..Trust Zone support is included.
+ */
+#define MSCM_CPXCFG3_TZ(x)                       (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_TZ_SHIFT)) & MSCM_CPXCFG3_TZ_MASK)
+#define MSCM_CPXCFG3_CMP_MASK                    (0x20U)
+#define MSCM_CPXCFG3_CMP_SHIFT                   (5U)
+/*! CMP - Core Memory Protection unit
+ *  0b0..Core Memory Protection is not included.
+ *  0b1..Core Memory Protection is included.
+ */
+#define MSCM_CPXCFG3_CMP(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_CMP_SHIFT)) & MSCM_CPXCFG3_CMP_MASK)
+#define MSCM_CPXCFG3_BB_MASK                     (0x40U)
+#define MSCM_CPXCFG3_BB_SHIFT                    (6U)
+/*! BB - Bit Banding
+ *  0b0..Bit Banding is not supported.
+ *  0b1..Bit Banding is supported.
+ */
+#define MSCM_CPXCFG3_BB(x)                       (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_BB_SHIFT)) & MSCM_CPXCFG3_BB_MASK)
+#define MSCM_CPXCFG3_SBP_MASK                    (0x300U)
+#define MSCM_CPXCFG3_SBP_SHIFT                   (8U)
+#define MSCM_CPXCFG3_SBP(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_SBP_SHIFT)) & MSCM_CPXCFG3_SBP_MASK)
+/*! @} */
+
+/*! @name TYPE - Processor 0 Type Register..Processor 1 Type Register */
+/*! @{ */
+#define MSCM_TYPE_RYPZ_MASK                      (0xFFU)
+#define MSCM_TYPE_RYPZ_SHIFT                     (0U)
+#define MSCM_TYPE_RYPZ(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_TYPE_RYPZ_SHIFT)) & MSCM_TYPE_RYPZ_MASK)
+#define MSCM_TYPE_PERSONALITY_MASK               (0xFFFFFF00U)
+#define MSCM_TYPE_PERSONALITY_SHIFT              (8U)
+#define MSCM_TYPE_PERSONALITY(x)                 (((uint32_t)(((uint32_t)(x)) << MSCM_TYPE_PERSONALITY_SHIFT)) & MSCM_TYPE_PERSONALITY_MASK)
+/*! @} */
+
+/* The count of MSCM_TYPE */
+#define MSCM_TYPE_COUNT                          (2U)
+
+/*! @name NUM - Processor 0 Number Register..Processor 1 Number Register */
+/*! @{ */
+#define MSCM_NUM_CPN_MASK                        (0x1U)
+#define MSCM_NUM_CPN_SHIFT                       (0U)
+#define MSCM_NUM_CPN(x)                          (((uint32_t)(((uint32_t)(x)) << MSCM_NUM_CPN_SHIFT)) & MSCM_NUM_CPN_MASK)
+/*! @} */
+
+/* The count of MSCM_NUM */
+#define MSCM_NUM_COUNT                           (2U)
+
+/*! @name MASTER - Processor 0 Master Register..Processor 1 Master Register */
+/*! @{ */
+#define MSCM_MASTER_PPMN_MASK                    (0x3FU)
+#define MSCM_MASTER_PPMN_SHIFT                   (0U)
+#define MSCM_MASTER_PPMN(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_MASTER_PPMN_SHIFT)) & MSCM_MASTER_PPMN_MASK)
+/*! @} */
+
+/* The count of MSCM_MASTER */
+#define MSCM_MASTER_COUNT                        (2U)
+
+/*! @name COUNT - Processor 0 Count Register..Processor 1 Count Register */
+/*! @{ */
+#define MSCM_COUNT_PCNT_MASK                     (0x3U)
+#define MSCM_COUNT_PCNT_SHIFT                    (0U)
+#define MSCM_COUNT_PCNT(x)                       (((uint32_t)(((uint32_t)(x)) << MSCM_COUNT_PCNT_SHIFT)) & MSCM_COUNT_PCNT_MASK)
+/*! @} */
+
+/* The count of MSCM_COUNT */
+#define MSCM_COUNT_COUNT                         (2U)
+
+/*! @name CFG0 - Processor 0 Configuration Register 0..Processor 1 Configuration Register 0 */
+/*! @{ */
+#define MSCM_CFG0_DCWY_MASK                      (0xFFU)
+#define MSCM_CFG0_DCWY_SHIFT                     (0U)
+#define MSCM_CFG0_DCWY(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_CFG0_DCWY_SHIFT)) & MSCM_CFG0_DCWY_MASK)
+#define MSCM_CFG0_DCSZ_MASK                      (0xFF00U)
+#define MSCM_CFG0_DCSZ_SHIFT                     (8U)
+#define MSCM_CFG0_DCSZ(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_CFG0_DCSZ_SHIFT)) & MSCM_CFG0_DCSZ_MASK)
+#define MSCM_CFG0_ICWY_MASK                      (0xFF0000U)
+#define MSCM_CFG0_ICWY_SHIFT                     (16U)
+#define MSCM_CFG0_ICWY(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_CFG0_ICWY_SHIFT)) & MSCM_CFG0_ICWY_MASK)
+#define MSCM_CFG0_ICSZ_MASK                      (0xFF000000U)
+#define MSCM_CFG0_ICSZ_SHIFT                     (24U)
+#define MSCM_CFG0_ICSZ(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_CFG0_ICSZ_SHIFT)) & MSCM_CFG0_ICSZ_MASK)
+/*! @} */
+
+/* The count of MSCM_CFG0 */
+#define MSCM_CFG0_COUNT                          (2U)
+
+/*! @name CFG1 - Processor 0 Configuration Register 1..Processor 1 Configuration Register 1 */
+/*! @{ */
+#define MSCM_CFG1_L2WY_MASK                      (0xFF0000U)
+#define MSCM_CFG1_L2WY_SHIFT                     (16U)
+#define MSCM_CFG1_L2WY(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_CFG1_L2WY_SHIFT)) & MSCM_CFG1_L2WY_MASK)
+#define MSCM_CFG1_L2SZ_MASK                      (0xFF000000U)
+#define MSCM_CFG1_L2SZ_SHIFT                     (24U)
+#define MSCM_CFG1_L2SZ(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_CFG1_L2SZ_SHIFT)) & MSCM_CFG1_L2SZ_MASK)
+/*! @} */
+
+/* The count of MSCM_CFG1 */
+#define MSCM_CFG1_COUNT                          (2U)
+
+/*! @name CFG2 - Processor 0 Configuration Register 2..Processor 1 Configuration Register 2 */
+/*! @{ */
+#define MSCM_CFG2_TMUSZ_MASK                     (0xFF00U)
+#define MSCM_CFG2_TMUSZ_SHIFT                    (8U)
+#define MSCM_CFG2_TMUSZ(x)                       (((uint32_t)(((uint32_t)(x)) << MSCM_CFG2_TMUSZ_SHIFT)) & MSCM_CFG2_TMUSZ_MASK)
+#define MSCM_CFG2_TMLSZ_MASK                     (0xFF000000U)
+#define MSCM_CFG2_TMLSZ_SHIFT                    (24U)
+#define MSCM_CFG2_TMLSZ(x)                       (((uint32_t)(((uint32_t)(x)) << MSCM_CFG2_TMLSZ_SHIFT)) & MSCM_CFG2_TMLSZ_MASK)
+/*! @} */
+
+/* The count of MSCM_CFG2 */
+#define MSCM_CFG2_COUNT                          (2U)
+
+/*! @name CFG3 - Processor 0 Configuration Register 3..Processor 1 Configuration Register 3 */
+/*! @{ */
+#define MSCM_CFG3_FPU_MASK                       (0x1U)
+#define MSCM_CFG3_FPU_SHIFT                      (0U)
+/*! FPU - Floating Point Unit
+ *  0b0..FPU support is not included.
+ *  0b1..FPU support is included.
+ */
+#define MSCM_CFG3_FPU(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_FPU_SHIFT)) & MSCM_CFG3_FPU_MASK)
+#define MSCM_CFG3_SIMD_MASK                      (0x2U)
+#define MSCM_CFG3_SIMD_SHIFT                     (1U)
+/*! SIMD - SIMD/NEON instruction support
+ *  0b0..SIMD/NEON support is not included.
+ *  0b1..SIMD/NEON support is included.
+ */
+#define MSCM_CFG3_SIMD(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_SIMD_SHIFT)) & MSCM_CFG3_SIMD_MASK)
+#define MSCM_CFG3_JAZ_MASK                       (0x4U)
+#define MSCM_CFG3_JAZ_SHIFT                      (2U)
+/*! JAZ - Jazelle support
+ *  0b0..Jazelle support is not included.
+ *  0b1..Jazelle support is included.
+ */
+#define MSCM_CFG3_JAZ(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_JAZ_SHIFT)) & MSCM_CFG3_JAZ_MASK)
+#define MSCM_CFG3_MMU_MASK                       (0x8U)
+#define MSCM_CFG3_MMU_SHIFT                      (3U)
+/*! MMU - Memory Management Unit
+ *  0b0..MMU support is not included.
+ *  0b1..MMU support is included.
+ */
+#define MSCM_CFG3_MMU(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_MMU_SHIFT)) & MSCM_CFG3_MMU_MASK)
+#define MSCM_CFG3_TZ_MASK                        (0x10U)
+#define MSCM_CFG3_TZ_SHIFT                       (4U)
+/*! TZ - Trust Zone
+ *  0b0..Trust Zone support is not included.
+ *  0b1..Trust Zone support is included.
+ */
+#define MSCM_CFG3_TZ(x)                          (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_TZ_SHIFT)) & MSCM_CFG3_TZ_MASK)
+#define MSCM_CFG3_CMP_MASK                       (0x20U)
+#define MSCM_CFG3_CMP_SHIFT                      (5U)
+/*! CMP - Core Memory Protection unit
+ *  0b0..Core Memory Protection is not included.
+ *  0b1..Core Memory Protection is included.
+ */
+#define MSCM_CFG3_CMP(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_CMP_SHIFT)) & MSCM_CFG3_CMP_MASK)
+#define MSCM_CFG3_BB_MASK                        (0x40U)
+#define MSCM_CFG3_BB_SHIFT                       (6U)
+/*! BB - Bit Banding
+ *  0b0..Bit Banding is not supported.
+ *  0b1..Bit Banding is supported.
+ */
+#define MSCM_CFG3_BB(x)                          (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_BB_SHIFT)) & MSCM_CFG3_BB_MASK)
+#define MSCM_CFG3_SBP_MASK                       (0x300U)
+#define MSCM_CFG3_SBP_SHIFT                      (8U)
+#define MSCM_CFG3_SBP(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_SBP_SHIFT)) & MSCM_CFG3_SBP_MASK)
+/*! @} */
+
+/* The count of MSCM_CFG3 */
+#define MSCM_CFG3_COUNT                          (2U)
+
+/*! @name OCMDR0 - On-Chip Memory Descriptor Register */
+/*! @{ */
+#define MSCM_OCMDR0_OCM1_MASK                    (0x30U)
+#define MSCM_OCMDR0_OCM1_SHIFT                   (4U)
+#define MSCM_OCMDR0_OCM1(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCM1_SHIFT)) & MSCM_OCMDR0_OCM1_MASK)
+#define MSCM_OCMDR0_OCMPU_MASK                   (0x1000U)
+#define MSCM_OCMDR0_OCMPU_SHIFT                  (12U)
+#define MSCM_OCMDR0_OCMPU(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMPU_SHIFT)) & MSCM_OCMDR0_OCMPU_MASK)
+#define MSCM_OCMDR0_OCMT_MASK                    (0xE000U)
+#define MSCM_OCMDR0_OCMT_SHIFT                   (13U)
+/*! OCMT - OCMT
+ *  0b000..Reserved
+ *  0b001..Reserved
+ *  0b010..Reserved
+ *  0b011..OCMEMn is a ROM.
+ *  0b100..OCMEMn is a Program Flash.
+ *  0b101..Reserved
+ *  0b110..OCMEMn is an EEE.
+ *  0b111..Reserved
+ */
+#define MSCM_OCMDR0_OCMT(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMT_SHIFT)) & MSCM_OCMDR0_OCMT_MASK)
+#define MSCM_OCMDR0_RO_MASK                      (0x10000U)
+#define MSCM_OCMDR0_RO_SHIFT                     (16U)
+/*! RO - RO
+ *  0b0..Writes to the OCMDRn[11:0] are allowed
+ *  0b1..Writes to the OCMDRn[11:0] are ignored
+ */
+#define MSCM_OCMDR0_RO(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_RO_SHIFT)) & MSCM_OCMDR0_RO_MASK)
+#define MSCM_OCMDR0_OCMW_MASK                    (0xE0000U)
+#define MSCM_OCMDR0_OCMW_SHIFT                   (17U)
+/*! OCMW - OCMW
+ *  0b000-0b001..Reserved
+ *  0b010..OCMEMn 32-bits wide
+ *  0b011..OCMEMn 64-bits wide
+ *  0b100..OCMEMn 128-bits wide
+ *  0b101..OCMEMn 256-bits wide
+ *  0b110-0b111..Reserved
+ */
+#define MSCM_OCMDR0_OCMW(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMW_SHIFT)) & MSCM_OCMDR0_OCMW_MASK)
+#define MSCM_OCMDR0_OCMSZ_MASK                   (0xF000000U)
+#define MSCM_OCMDR0_OCMSZ_SHIFT                  (24U)
+/*! OCMSZ - OCMSZ
+ *  0b0000..no OCMEMn
+ *  0b0001..1KB OCMEMn
+ *  0b0010..2KB OCMEMn
+ *  0b0011..4KB OCMEMn
+ *  0b0100..8KB OCMEMn
+ *  0b0101..16KB OCMEMn
+ *  0b0110..32KB OCMEMn
+ *  0b0111..64KB OCMEMn
+ *  0b1000..128KB OCMEMn
+ *  0b1001..256KB OCMEMn
+ *  0b1010..512KB OCMEMn
+ *  0b1011..1MB OCMEMn
+ *  0b1100..2MB OCMEMn
+ *  0b1101..4MB OCMEMn
+ *  0b1110..8MB OCMEMn
+ *  0b1111..16MB OCMEMn
+ */
+#define MSCM_OCMDR0_OCMSZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMSZ_SHIFT)) & MSCM_OCMDR0_OCMSZ_MASK)
+#define MSCM_OCMDR0_OCMSZH_MASK                  (0x10000000U)
+#define MSCM_OCMDR0_OCMSZH_SHIFT                 (28U)
+/*! OCMSZH - OCMSZH
+ *  0b0..OCMEMn is a power-of-2 capacity.
+ *  0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
+ */
+#define MSCM_OCMDR0_OCMSZH(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMSZH_SHIFT)) & MSCM_OCMDR0_OCMSZH_MASK)
+#define MSCM_OCMDR0_V_MASK                       (0x80000000U)
+#define MSCM_OCMDR0_V_SHIFT                      (31U)
+/*! V - V
+ *  0b0..OCMEMn is not present.
+ *  0b1..OCMEMn is present.
+ */
+#define MSCM_OCMDR0_V(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_V_SHIFT)) & MSCM_OCMDR0_V_MASK)
+/*! @} */
+
+/*! @name OCMDR1 - On-Chip Memory Descriptor Register */
+/*! @{ */
+#define MSCM_OCMDR1_OCM1_MASK                    (0x30U)
+#define MSCM_OCMDR1_OCM1_SHIFT                   (4U)
+#define MSCM_OCMDR1_OCM1(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCM1_SHIFT)) & MSCM_OCMDR1_OCM1_MASK)
+#define MSCM_OCMDR1_OCMPU_MASK                   (0x1000U)
+#define MSCM_OCMDR1_OCMPU_SHIFT                  (12U)
+#define MSCM_OCMDR1_OCMPU(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMPU_SHIFT)) & MSCM_OCMDR1_OCMPU_MASK)
+#define MSCM_OCMDR1_OCMT_MASK                    (0xE000U)
+#define MSCM_OCMDR1_OCMT_SHIFT                   (13U)
+/*! OCMT - OCMT
+ *  0b000..Reserved
+ *  0b001..Reserved
+ *  0b010..Reserved
+ *  0b011..OCMEMn is a ROM.
+ *  0b100..OCMEMn is a Program Flash.
+ *  0b101..Reserved
+ *  0b110..OCMEMn is an EEE.
+ *  0b111..Reserved
+ */
+#define MSCM_OCMDR1_OCMT(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMT_SHIFT)) & MSCM_OCMDR1_OCMT_MASK)
+#define MSCM_OCMDR1_RO_MASK                      (0x10000U)
+#define MSCM_OCMDR1_RO_SHIFT                     (16U)
+/*! RO - RO
+ *  0b0..Writes to the OCMDRn[11:0] are allowed
+ *  0b1..Writes to the OCMDRn[11:0] are ignored
+ */
+#define MSCM_OCMDR1_RO(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_RO_SHIFT)) & MSCM_OCMDR1_RO_MASK)
+#define MSCM_OCMDR1_OCMW_MASK                    (0xE0000U)
+#define MSCM_OCMDR1_OCMW_SHIFT                   (17U)
+/*! OCMW - OCMW
+ *  0b000-0b001..Reserved
+ *  0b010..OCMEMn 32-bits wide
+ *  0b011..OCMEMn 64-bits wide
+ *  0b100..OCMEMn 128-bits wide
+ *  0b101..OCMEMn 256-bits wide
+ *  0b110-0b111..Reserved
+ */
+#define MSCM_OCMDR1_OCMW(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMW_SHIFT)) & MSCM_OCMDR1_OCMW_MASK)
+#define MSCM_OCMDR1_OCMSZ_MASK                   (0xF000000U)
+#define MSCM_OCMDR1_OCMSZ_SHIFT                  (24U)
+/*! OCMSZ - OCMSZ
+ *  0b0000..no OCMEMn
+ *  0b0001..1KB OCMEMn
+ *  0b0010..2KB OCMEMn
+ *  0b0011..4KB OCMEMn
+ *  0b0100..8KB OCMEMn
+ *  0b0101..16KB OCMEMn
+ *  0b0110..32KB OCMEMn
+ *  0b0111..64KB OCMEMn
+ *  0b1000..128KB OCMEMn
+ *  0b1001..256KB OCMEMn
+ *  0b1010..512KB OCMEMn
+ *  0b1011..1MB OCMEMn
+ *  0b1100..2MB OCMEMn
+ *  0b1101..4MB OCMEMn
+ *  0b1110..8MB OCMEMn
+ *  0b1111..16MB OCMEMn
+ */
+#define MSCM_OCMDR1_OCMSZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMSZ_SHIFT)) & MSCM_OCMDR1_OCMSZ_MASK)
+#define MSCM_OCMDR1_OCMSZH_MASK                  (0x10000000U)
+#define MSCM_OCMDR1_OCMSZH_SHIFT                 (28U)
+/*! OCMSZH - OCMSZH
+ *  0b0..OCMEMn is a power-of-2 capacity.
+ *  0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
+ */
+#define MSCM_OCMDR1_OCMSZH(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMSZH_SHIFT)) & MSCM_OCMDR1_OCMSZH_MASK)
+#define MSCM_OCMDR1_V_MASK                       (0x80000000U)
+#define MSCM_OCMDR1_V_SHIFT                      (31U)
+/*! V - V
+ *  0b0..OCMEMn is not present.
+ *  0b1..OCMEMn is present.
+ */
+#define MSCM_OCMDR1_V(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_V_SHIFT)) & MSCM_OCMDR1_V_MASK)
+/*! @} */
+
+/*! @name OCMDR2 - On-Chip Memory Descriptor Register */
+/*! @{ */
+#define MSCM_OCMDR2_OCMPU_MASK                   (0x1000U)
+#define MSCM_OCMDR2_OCMPU_SHIFT                  (12U)
+#define MSCM_OCMDR2_OCMPU(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMPU_SHIFT)) & MSCM_OCMDR2_OCMPU_MASK)
+#define MSCM_OCMDR2_OCMT_MASK                    (0xE000U)
+#define MSCM_OCMDR2_OCMT_SHIFT                   (13U)
+/*! OCMT - OCMT
+ *  0b000..Reserved
+ *  0b001..Reserved
+ *  0b010..Reserved
+ *  0b011..OCMEMn is a ROM.
+ *  0b100..OCMEMn is a Program Flash.
+ *  0b101..Reserved
+ *  0b110..OCMEMn is an EEE.
+ *  0b111..Reserved
+ */
+#define MSCM_OCMDR2_OCMT(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMT_SHIFT)) & MSCM_OCMDR2_OCMT_MASK)
+#define MSCM_OCMDR2_RO_MASK                      (0x10000U)
+#define MSCM_OCMDR2_RO_SHIFT                     (16U)
+/*! RO - RO
+ *  0b0..Writes to the OCMDRn[11:0] are allowed
+ *  0b1..Writes to the OCMDRn[11:0] are ignored
+ */
+#define MSCM_OCMDR2_RO(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_RO_SHIFT)) & MSCM_OCMDR2_RO_MASK)
+#define MSCM_OCMDR2_OCMW_MASK                    (0xE0000U)
+#define MSCM_OCMDR2_OCMW_SHIFT                   (17U)
+/*! OCMW - OCMW
+ *  0b000-0b001..Reserved
+ *  0b010..OCMEMn 32-bits wide
+ *  0b011..OCMEMn 64-bits wide
+ *  0b100..OCMEMn 128-bits wide
+ *  0b101..OCMEMn 256-bits wide
+ *  0b110-0b111..Reserved
+ */
+#define MSCM_OCMDR2_OCMW(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMW_SHIFT)) & MSCM_OCMDR2_OCMW_MASK)
+#define MSCM_OCMDR2_OCMSZ_MASK                   (0xF000000U)
+#define MSCM_OCMDR2_OCMSZ_SHIFT                  (24U)
+/*! OCMSZ - OCMSZ
+ *  0b0000..no OCMEMn
+ *  0b0001..1KB OCMEMn
+ *  0b0010..2KB OCMEMn
+ *  0b0011..4KB OCMEMn
+ *  0b0100..8KB OCMEMn
+ *  0b0101..16KB OCMEMn
+ *  0b0110..32KB OCMEMn
+ *  0b0111..64KB OCMEMn
+ *  0b1000..128KB OCMEMn
+ *  0b1001..256KB OCMEMn
+ *  0b1010..512KB OCMEMn
+ *  0b1011..1MB OCMEMn
+ *  0b1100..2MB OCMEMn
+ *  0b1101..4MB OCMEMn
+ *  0b1110..8MB OCMEMn
+ *  0b1111..16MB OCMEMn
+ */
+#define MSCM_OCMDR2_OCMSZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMSZ_SHIFT)) & MSCM_OCMDR2_OCMSZ_MASK)
+#define MSCM_OCMDR2_OCMSZH_MASK                  (0x10000000U)
+#define MSCM_OCMDR2_OCMSZH_SHIFT                 (28U)
+/*! OCMSZH - OCMSZH
+ *  0b0..OCMEMn is a power-of-2 capacity.
+ *  0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
+ */
+#define MSCM_OCMDR2_OCMSZH(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMSZH_SHIFT)) & MSCM_OCMDR2_OCMSZH_MASK)
+#define MSCM_OCMDR2_V_MASK                       (0x80000000U)
+#define MSCM_OCMDR2_V_SHIFT                      (31U)
+/*! V - V
+ *  0b0..OCMEMn is not present.
+ *  0b1..OCMEMn is present.
+ */
+#define MSCM_OCMDR2_V(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_V_SHIFT)) & MSCM_OCMDR2_V_MASK)
+/*! @} */
+
+/*! @name OCMDR3 - On-Chip Memory Descriptor Register */
+/*! @{ */
+#define MSCM_OCMDR3_OCMPU_MASK                   (0x1000U)
+#define MSCM_OCMDR3_OCMPU_SHIFT                  (12U)
+#define MSCM_OCMDR3_OCMPU(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMPU_SHIFT)) & MSCM_OCMDR3_OCMPU_MASK)
+#define MSCM_OCMDR3_OCMT_MASK                    (0xE000U)
+#define MSCM_OCMDR3_OCMT_SHIFT                   (13U)
+/*! OCMT - OCMT
+ *  0b000..Reserved
+ *  0b001..Reserved
+ *  0b010..Reserved
+ *  0b011..OCMEMn is a ROM.
+ *  0b100..OCMEMn is a Program Flash.
+ *  0b101..Reserved
+ *  0b110..OCMEMn is an EEE.
+ *  0b111..Reserved
+ */
+#define MSCM_OCMDR3_OCMT(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMT_SHIFT)) & MSCM_OCMDR3_OCMT_MASK)
+#define MSCM_OCMDR3_RO_MASK                      (0x10000U)
+#define MSCM_OCMDR3_RO_SHIFT                     (16U)
+/*! RO - RO
+ *  0b0..Writes to the OCMDRn[11:0] are allowed
+ *  0b1..Writes to the OCMDRn[11:0] are ignored
+ */
+#define MSCM_OCMDR3_RO(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_RO_SHIFT)) & MSCM_OCMDR3_RO_MASK)
+#define MSCM_OCMDR3_OCMW_MASK                    (0xE0000U)
+#define MSCM_OCMDR3_OCMW_SHIFT                   (17U)
+/*! OCMW - OCMW
+ *  0b000-0b001..Reserved
+ *  0b010..OCMEMn 32-bits wide
+ *  0b011..OCMEMn 64-bits wide
+ *  0b100..OCMEMn 128-bits wide
+ *  0b101..OCMEMn 256-bits wide
+ *  0b110-0b111..Reserved
+ */
+#define MSCM_OCMDR3_OCMW(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMW_SHIFT)) & MSCM_OCMDR3_OCMW_MASK)
+#define MSCM_OCMDR3_OCMSZ_MASK                   (0xF000000U)
+#define MSCM_OCMDR3_OCMSZ_SHIFT                  (24U)
+/*! OCMSZ - OCMSZ
+ *  0b0000..no OCMEMn
+ *  0b0001..1KB OCMEMn
+ *  0b0010..2KB OCMEMn
+ *  0b0011..4KB OCMEMn
+ *  0b0100..8KB OCMEMn
+ *  0b0101..16KB OCMEMn
+ *  0b0110..32KB OCMEMn
+ *  0b0111..64KB OCMEMn
+ *  0b1000..128KB OCMEMn
+ *  0b1001..256KB OCMEMn
+ *  0b1010..512KB OCMEMn
+ *  0b1011..1MB OCMEMn
+ *  0b1100..2MB OCMEMn
+ *  0b1101..4MB OCMEMn
+ *  0b1110..8MB OCMEMn
+ *  0b1111..16MB OCMEMn
+ */
+#define MSCM_OCMDR3_OCMSZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMSZ_SHIFT)) & MSCM_OCMDR3_OCMSZ_MASK)
+#define MSCM_OCMDR3_OCMSZH_MASK                  (0x10000000U)
+#define MSCM_OCMDR3_OCMSZH_SHIFT                 (28U)
+/*! OCMSZH - OCMSZH
+ *  0b0..OCMEMn is a power-of-2 capacity.
+ *  0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
+ */
+#define MSCM_OCMDR3_OCMSZH(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMSZH_SHIFT)) & MSCM_OCMDR3_OCMSZH_MASK)
+#define MSCM_OCMDR3_V_MASK                       (0x80000000U)
+#define MSCM_OCMDR3_V_SHIFT                      (31U)
+/*! V - V
+ *  0b0..OCMEMn is not present.
+ *  0b1..OCMEMn is present.
+ */
+#define MSCM_OCMDR3_V(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_V_SHIFT)) & MSCM_OCMDR3_V_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group MSCM_Register_Masks */
+
+
+/* MSCM - Peripheral instance base addresses */
+/** Peripheral MSCM base address */
+#define MSCM_BASE                                (0x40001000u)
+/** Peripheral MSCM base pointer */
+#define MSCM                                     ((MSCM_Type *)MSCM_BASE)
+/** Array initializer of MSCM peripheral base addresses */
+#define MSCM_BASE_ADDRS                          { MSCM_BASE }
+/** Array initializer of MSCM peripheral base pointers */
+#define MSCM_BASE_PTRS                           { MSCM }
+
+/*!
+ * @}
+ */ /* end of group MSCM_Peripheral_Access_Layer */
+
+/*!
+ * @brief Core boot mode.
+ */
+typedef enum _mu_core_boot_mode
+{
+    kMU_CoreBootFromDflashBase = 0x00U, /*!< Boot from Dflash base.  */
+    kMU_CoreBootFromCore1RamBase = 0x02U, /*!< Boot from ZERO RISCY RAM base. */
+} mu_core_boot_mode_t;
+/*!
+ * @brief Power mode on the other side definition.
+ */
+typedef enum _mu_power_mode
+{
+    kMU_PowerModeRun = 0x00U,  /*!< Run mode.           */
+    kMU_PowerModeCoo = 0x01U,  /*!< COO mode.           */
+    kMU_PowerModeWait = 0x02U, /*!< WAIT mode.          */
+    kMU_PowerModeStop = 0x03U, /*!< STOP/VLPS mode.     */
+    kMU_PowerModeDsm = 0x04U   /*!< DSM: LLS/VLLS mode. */
+} mu_power_mode_t;
+
+
+/* ----------------------------------------------------------------------------
+   -- MU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer
+ * @{
+ */
+
+/** MU - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VER;                               /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PAR;                               /**< Parameter Register, offset: 0x4 */
+       uint8_t RESERVED_0[24];
+  __IO uint32_t TR[4];                             /**< Transmit Register, array offset: 0x20, array step: 0x4 */
+       uint8_t RESERVED_1[16];
+  __I  uint32_t RR[4];                             /**< Receive Register, array offset: 0x40, array step: 0x4 */
+       uint8_t RESERVED_2[16];
+  __IO uint32_t SR;                                /**< Status Register, offset: 0x60 */
+  __IO uint32_t CR;                                /**< Control Register, offset: 0x64 */
+  __IO uint32_t CCR;                               /**< Core Control Register, offset: 0x68 */
+} MU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MU_Register_Masks MU Register Masks
+ * @{
+ */
+
+/*! @name VER - Version ID Register */
+/*! @{ */
+#define MU_VER_FEATURE_MASK                      (0xFFFFU)
+#define MU_VER_FEATURE_SHIFT                     (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b000000000000x1xx..Core Control and Status Registers are implemented in both MUA and MUB.
+ *  0b000000000000xx1x..RAIP/RAIE register bits are implemented.
+ *  0b000000000000xxx0..Standard features implemented
+ */
+#define MU_VER_FEATURE(x)                        (((uint32_t)(((uint32_t)(x)) << MU_VER_FEATURE_SHIFT)) & MU_VER_FEATURE_MASK)
+#define MU_VER_MINOR_MASK                        (0xFF0000U)
+#define MU_VER_MINOR_SHIFT                       (16U)
+#define MU_VER_MINOR(x)                          (((uint32_t)(((uint32_t)(x)) << MU_VER_MINOR_SHIFT)) & MU_VER_MINOR_MASK)
+#define MU_VER_MAJOR_MASK                        (0xFF000000U)
+#define MU_VER_MAJOR_SHIFT                       (24U)
+#define MU_VER_MAJOR(x)                          (((uint32_t)(((uint32_t)(x)) << MU_VER_MAJOR_SHIFT)) & MU_VER_MAJOR_MASK)
+/*! @} */
+
+/*! @name PAR - Parameter Register */
+/*! @{ */
+#define MU_PAR_PARAMETER_MASK                    (0xFFFFFFFFU)
+#define MU_PAR_PARAMETER_SHIFT                   (0U)
+#define MU_PAR_PARAMETER(x)                      (((uint32_t)(((uint32_t)(x)) << MU_PAR_PARAMETER_SHIFT)) & MU_PAR_PARAMETER_MASK)
+/*! @} */
+
+/*! @name TR - Transmit Register */
+/*! @{ */
+#define MU_TR_DATA_MASK                          (0xFFFFFFFFU)
+#define MU_TR_DATA_SHIFT                         (0U)
+#define MU_TR_DATA(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TR_DATA_SHIFT)) & MU_TR_DATA_MASK)
+/*! @} */
+
+/* The count of MU_TR */
+#define MU_TR_COUNT                              (4U)
+
+/*! @name RR - Receive Register */
+/*! @{ */
+#define MU_RR_DATA_MASK                          (0xFFFFFFFFU)
+#define MU_RR_DATA_SHIFT                         (0U)
+#define MU_RR_DATA(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RR_DATA_SHIFT)) & MU_RR_DATA_MASK)
+/*! @} */
+
+/* The count of MU_RR */
+#define MU_RR_COUNT                              (4U)
+
+/*! @name SR - Status Register */
+/*! @{ */
+#define MU_SR_Fn_MASK                            (0x7U)
+#define MU_SR_Fn_SHIFT                           (0U)
+/*! Fn - Fn
+ *  0b000..Fn bit in the MUB CR register is written 0 (default).
+ *  0b001..Fn bit in the MUB CR register is written 1.
+ */
+#define MU_SR_Fn(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK)
+#define MU_SR_NMIC_MASK                          (0x8U)
+#define MU_SR_NMIC_SHIFT                         (3U)
+/*! NMIC - NMIC
+ *  0b0..Default
+ *  0b1..Writing "1" clears the NMI bit in the MUB CR register.
+ */
+#define MU_SR_NMIC(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_NMIC_SHIFT)) & MU_SR_NMIC_MASK)
+#define MU_SR_EP_MASK                            (0x10U)
+#define MU_SR_EP_SHIFT                           (4U)
+/*! EP - EP
+ *  0b0..The MUA side event is not pending (default).
+ *  0b1..The MUA side event is pending.
+ */
+#define MU_SR_EP(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK)
+#define MU_SR_HRIP_MASK                          (0x80U)
+#define MU_SR_HRIP_SHIFT                         (7U)
+/*! HRIP - HRIP
+ *  0b0..MUB didn't issue hardware reset to Processor A
+ *  0b1..MUB had initiated a hardware reset to Processor A through HR bit.
+ */
+#define MU_SR_HRIP(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_HRIP_SHIFT)) & MU_SR_HRIP_MASK)
+#define MU_SR_FUP_MASK                           (0x100U)
+#define MU_SR_FUP_SHIFT                          (8U)
+/*! FUP - FUP
+ *  0b0..No flags updated, initiated by the MUA, in progress (default)
+ *  0b1..MUA initiated flags update, processing
+ */
+#define MU_SR_FUP(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK)
+#define MU_SR_RDIP_MASK                          (0x200U)
+#define MU_SR_RDIP_SHIFT                         (9U)
+/*! RDIP - RDIP
+ *  0b0..Processor B did not exit reset
+ *  0b1..Processor B exited from reset
+ */
+#define MU_SR_RDIP(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_RDIP_SHIFT)) & MU_SR_RDIP_MASK)
+#define MU_SR_RAIP_MASK                          (0x400U)
+#define MU_SR_RAIP_SHIFT                         (10U)
+/*! RAIP - RAIP
+ *  0b0..Processor B did not enter reset
+ *  0b1..Processor B entered reset
+ */
+#define MU_SR_RAIP(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_RAIP_SHIFT)) & MU_SR_RAIP_MASK)
+#define MU_SR_MURIP_MASK                         (0x800U)
+#define MU_SR_MURIP_SHIFT                        (11U)
+/*! MURIP - MURIP
+ *  0b0..Processor B did not issue MU reset
+ *  0b1..Processor B issued MU reset
+ */
+#define MU_SR_MURIP(x)                           (((uint32_t)(((uint32_t)(x)) << MU_SR_MURIP_SHIFT)) & MU_SR_MURIP_MASK)
+#define MU_SR_PM_MASK                            (0x7000U)
+#define MU_SR_PM_SHIFT                           (12U)
+/*! PM - PM
+ *  0b000..The MUB processor is in Run Mode.
+ *  0b001..The MUB processor is in COO Mode.
+ *  0b010..The MUB processor is in WAIT Mode.
+ *  0b011..The MUB processor is in STOP/VLPS Mode.
+ *  0b100..The MUB processor is in LLS/VLLS Mode.
+ */
+#define MU_SR_PM(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_PM_SHIFT)) & MU_SR_PM_MASK)
+#define MU_SR_TEn_MASK                           (0xF00000U)
+#define MU_SR_TEn_SHIFT                          (20U)
+/*! TEn - TEn
+ *  0b0000..MUA TRn register is not empty.
+ *  0b0001..MUA TRn register is empty (default).
+ */
+#define MU_SR_TEn(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK)
+#define MU_SR_RFn_MASK                           (0xF000000U)
+#define MU_SR_RFn_SHIFT                          (24U)
+/*! RFn - RFn
+ *  0b0000..MUA RRn register is not full (default).
+ *  0b0001..MUA RRn register has received data from MUB TRn register and is ready to be read by the MUA.
+ */
+#define MU_SR_RFn(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK)
+#define MU_SR_GIPn_MASK                          (0xF0000000U)
+#define MU_SR_GIPn_SHIFT                         (28U)
+/*! GIPn - GIPn
+ *  0b0000..MUA general purpose interrupt n is not pending. (default)
+ *  0b0001..MUA general purpose interrupt n is pending.
+ */
+#define MU_SR_GIPn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK)
+/*! @} */
+
+/*! @name CR - Control Register */
+/*! @{ */
+#define MU_CR_Fn_MASK                            (0x7U)
+#define MU_CR_Fn_SHIFT                           (0U)
+/*! Fn - Fn
+ *  0b000..Clears the Fn bit in the SR register.
+ *  0b001..Sets the Fn bit in the SR register.
+ */
+#define MU_CR_Fn(x)                              (((uint32_t)(((uint32_t)(x)) << MU_CR_Fn_SHIFT)) & MU_CR_Fn_MASK)
+#define MU_CR_NMI_MASK                           (0x8U)
+#define MU_CR_NMI_SHIFT                          (3U)
+/*! NMI - NMI
+ *  0b0..Non-maskable interrupt is not issued to the Processor B by the Processor A (default).
+ *  0b1..Non-maskable interrupt is issued to the Processor B by the Processor A.
+ */
+#define MU_CR_NMI(x)                             (((uint32_t)(((uint32_t)(x)) << MU_CR_NMI_SHIFT)) & MU_CR_NMI_MASK)
+#define MU_CR_MUR_MASK                           (0x20U)
+#define MU_CR_MUR_SHIFT                          (5U)
+/*! MUR - MUR
+ *  0b0..N/A. Self clearing bit (default).
+ *  0b1..Asserts the MU reset.
+ */
+#define MU_CR_MUR(x)                             (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
+#define MU_CR_RDIE_MASK                          (0x40U)
+#define MU_CR_RDIE_SHIFT                         (6U)
+/*! RDIE - RDIE
+ *  0b0..Disables Processor A General Purpose Interrupt 3 request due to Processor B reset de-assertion.
+ *  0b1..Enables Processor A General Purpose Interrupt 3 request due to Processor B reset de-assertion.
+ */
+#define MU_CR_RDIE(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_RDIE_SHIFT)) & MU_CR_RDIE_MASK)
+#define MU_CR_HRIE_MASK                          (0x80U)
+#define MU_CR_HRIE_SHIFT                         (7U)
+/*! HRIE - Processor A hardware reset interrupt enable
+ *  0b0..Disables Processor A General Purpose Interrupt 3 request due to Processor B issued HR to Processor A.
+ *  0b1..Enables Processor A General Purpose Interrupt 3 request due to Processor B issued HR to Processor A.
+ */
+#define MU_CR_HRIE(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_HRIE_SHIFT)) & MU_CR_HRIE_MASK)
+#define MU_CR_MURIE_MASK                         (0x800U)
+#define MU_CR_MURIE_SHIFT                        (11U)
+/*! MURIE - MURIE
+ *  0b0..Disables Processor A-side General Purpose Interrupt 3 request due to MU reset issued by MUB.
+ *  0b1..Enables Processor A-side General Purpose Interrupt 3 request due to MU reset issued by MUB.
+ */
+#define MU_CR_MURIE(x)                           (((uint32_t)(((uint32_t)(x)) << MU_CR_MURIE_SHIFT)) & MU_CR_MURIE_MASK)
+#define MU_CR_RAIE_MASK                          (0x1000U)
+#define MU_CR_RAIE_SHIFT                         (12U)
+/*! RAIE - RAIE
+ *  0b0..Disables Processor A-side General Purpose Interrupt 3 request due to Processor B reset assertion.
+ *  0b1..Enables Processor A-side General Purpose Interrupt 3 request due to Processor B reset assertion.
+ */
+#define MU_CR_RAIE(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_RAIE_SHIFT)) & MU_CR_RAIE_MASK)
+#define MU_CR_GIRn_MASK                          (0xF0000U)
+#define MU_CR_GIRn_SHIFT                         (16U)
+/*! GIRn - GIRn
+ *  0b0000..MUA General Interrupt n is not requested to the MUB (default).
+ *  0b0001..MUA General Interrupt n is requested to the MUB.
+ */
+#define MU_CR_GIRn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)
+#define MU_CR_TIEn_MASK                          (0xF00000U)
+#define MU_CR_TIEn_SHIFT                         (20U)
+/*! TIEn - TIEn
+ *  0b0000..Disables MUA Transmit Interrupt n. (default)
+ *  0b0001..Enables MUA Transmit Interrupt n.
+ */
+#define MU_CR_TIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK)
+#define MU_CR_RIEn_MASK                          (0xF000000U)
+#define MU_CR_RIEn_SHIFT                         (24U)
+/*! RIEn - RIEn
+ *  0b0000..Disables MUA Receive Interrupt n. (default)
+ *  0b0001..Enables MUA Receive Interrupt n.
+ */
+#define MU_CR_RIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK)
+#define MU_CR_GIEn_MASK                          (0xF0000000U)
+#define MU_CR_GIEn_SHIFT                         (28U)
+/*! GIEn - GIEn
+ *  0b0000..Disables MUA General Interrupt n. (default)
+ *  0b0001..Enables MUA General Interrupt n.
+ */
+#define MU_CR_GIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK)
+/*! @} */
+
+/*! @name CCR - Core Control Register */
+/*! @{ */
+#define MU_CCR_HR_MASK                           (0x1U)
+#define MU_CCR_HR_SHIFT                          (0U)
+/*! HR - HR
+ *  0b0..De-assert Hardware reset to the Processor B. (default)
+ *  0b1..Assert Hardware reset to the Processor B.
+ */
+#define MU_CCR_HR(x)                             (((uint32_t)(((uint32_t)(x)) << MU_CCR_HR_SHIFT)) & MU_CCR_HR_MASK)
+#define MU_CCR_HRM_MASK                          (0x2U)
+#define MU_CCR_HRM_SHIFT                         (1U)
+/*! HRM - When set, HR bit in MUB CCR has no effect
+ *  0b0..HR bit in MUB CCR is not masked, enables the hardware reset to the Processor A (default after hardware reset).
+ *  0b1..HR bit in MUB CCR is masked, disables the hardware reset request to the Processor A.
+ */
+#define MU_CCR_HRM(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CCR_HRM_SHIFT)) & MU_CCR_HRM_MASK)
+#define MU_CCR_RSTH_MASK                         (0x4U)
+#define MU_CCR_RSTH_SHIFT                        (2U)
+/*! RSTH - Processor B Reset Hold
+ *  0b0..Release Processor B from reset
+ *  0b1..Hold Processor B in reset
+ */
+#define MU_CCR_RSTH(x)                           (((uint32_t)(((uint32_t)(x)) << MU_CCR_RSTH_SHIFT)) & MU_CCR_RSTH_MASK)
+#define MU_CCR_CLKE_MASK                         (0x8U)
+#define MU_CCR_CLKE_SHIFT                        (3U)
+/*! CLKE - MUB clock enable
+ *  0b0..MUB platform clock gated when MUB-side enters a stop mode.
+ *  0b1..MUB platform clock kept running after MUB-side enters a stop mode, until MUA also enters a stop mode.
+ */
+#define MU_CCR_CLKE(x)                           (((uint32_t)(((uint32_t)(x)) << MU_CCR_CLKE_SHIFT)) & MU_CCR_CLKE_MASK)
+#define MU_CCR_BOOT_MASK                         (0x30U)
+#define MU_CCR_BOOT_SHIFT                        (4U)
+/*! BOOT - Slave Processor B Boot Config.
+ *  0b00..Boot from Dflash base
+ *  0b01..Reserved
+ *  0b10..Boot from CM0+ RAM base
+ *  0b11..Reserved
+ */
+#define MU_CCR_BOOT(x)                           (((uint32_t)(((uint32_t)(x)) << MU_CCR_BOOT_SHIFT)) & MU_CCR_BOOT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group MU_Register_Masks */
+
+
+/* MU - Peripheral instance base addresses */
+/** Peripheral MUA base address */
+#define MUA_BASE                                 (0x40025000u)
+/** Peripheral MUA base pointer */
+#define MUA                                      ((MU_Type *)MUA_BASE)
+/** Array initializer of MU peripheral base addresses */
+#define MU_BASE_ADDRS                            { MUA_BASE }
+/** Array initializer of MU peripheral base pointers */
+#define MU_BASE_PTRS                             { MUA }
+/** Interrupt vectors for the MU peripheral type */
+#define MU_IRQS                                  { MUA_IRQn }
+
+/*!
+ * @}
+ */ /* end of group MU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PCC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PCC_Peripheral_Access_Layer PCC Peripheral Access Layer
+ * @{
+ */
+
+/** PCC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CLKCFG[130];                       /**< PCC MSCM Register..PCC EXT_CLK Register, array offset: 0x0, array step: 0x4 */
+} PCC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PCC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PCC_Register_Masks PCC Register Masks
+ * @{
+ */
+
+/*! @name CLKCFG - PCC MSCM Register..PCC EXT_CLK Register */
+/*! @{ */
+#define PCC_CLKCFG_PCD_MASK                      (0x7U)
+#define PCC_CLKCFG_PCD_SHIFT                     (0U)
+/*! PCD - Peripheral Clock Divider Select
+ *  0b000..Divide by 1.
+ *  0b001..Divide by 2.
+ *  0b010..Divide by 3.
+ *  0b011..Divide by 4.
+ *  0b100..Divide by 5.
+ *  0b101..Divide by 6.
+ *  0b110..Divide by 7.
+ *  0b111..Divide by 8.
+ */
+#define PCC_CLKCFG_PCD(x)                        (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PCD_SHIFT)) & PCC_CLKCFG_PCD_MASK)
+#define PCC_CLKCFG_FRAC_MASK                     (0x8U)
+#define PCC_CLKCFG_FRAC_SHIFT                    (3U)
+/*! FRAC - Peripheral Clock Divider Fraction
+ *  0b0..Fractional value is 0.
+ *  0b1..Fractional value is 1.
+ */
+#define PCC_CLKCFG_FRAC(x)                       (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_FRAC_SHIFT)) & PCC_CLKCFG_FRAC_MASK)
+#define PCC_CLKCFG_PCS_MASK                      (0x7000000U)
+#define PCC_CLKCFG_PCS_SHIFT                     (24U)
+/*! PCS - Peripheral Clock Source Select
+ *  0b000..Clock is off. An external clock can be enabled for this peripheral.
+ *  0b001..Clock option 1
+ *  0b010..Clock option 2
+ *  0b011..Clock option 3
+ *  0b100..Clock option 4
+ *  0b101..Clock option 5
+ *  0b110..Clock option 6
+ *  0b111..Clock option 7
+ */
+#define PCC_CLKCFG_PCS(x)                        (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PCS_SHIFT)) & PCC_CLKCFG_PCS_MASK)
+#define PCC_CLKCFG_INUSE_MASK                    (0x20000000U)
+#define PCC_CLKCFG_INUSE_SHIFT                   (29U)
+/*! INUSE - In use flag
+ *  0b0..Peripheral is not being used.
+ *  0b1..Peripheral is being used. Software cannot modify the existing clocking configuration.
+ */
+#define PCC_CLKCFG_INUSE(x)                      (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_INUSE_SHIFT)) & PCC_CLKCFG_INUSE_MASK)
+#define PCC_CLKCFG_CGC_MASK                      (0x40000000U)
+#define PCC_CLKCFG_CGC_SHIFT                     (30U)
+/*! CGC - Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled. The current clock selection and divider options are locked.
+ */
+#define PCC_CLKCFG_CGC(x)                        (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_CGC_SHIFT)) & PCC_CLKCFG_CGC_MASK)
+#define PCC_CLKCFG_PR_MASK                       (0x80000000U)
+#define PCC_CLKCFG_PR_SHIFT                      (31U)
+/*! PR - Present
+ *  0b0..Peripheral is not present.
+ *  0b1..Peripheral is present.
+ */
+#define PCC_CLKCFG_PR(x)                         (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PR_SHIFT)) & PCC_CLKCFG_PR_MASK)
+/*! @} */
+
+/* The count of PCC_CLKCFG */
+#define PCC_CLKCFG_COUNT                         (130U)
+
+
+/*!
+ * @}
+ */ /* end of group PCC_Register_Masks */
+
+
+/* PCC - Peripheral instance base addresses */
+/** Peripheral PCC0 base address */
+#define PCC0_BASE                                (0x4002B000u)
+/** Peripheral PCC0 base pointer */
+#define PCC0                                     ((PCC_Type *)PCC0_BASE)
+/** Peripheral PCC1 base address */
+#define PCC1_BASE                                (0x41027000u)
+/** Peripheral PCC1 base pointer */
+#define PCC1                                     ((PCC_Type *)PCC1_BASE)
+/** Array initializer of PCC peripheral base addresses */
+#define PCC_BASE_ADDRS                           { PCC0_BASE, PCC1_BASE }
+/** Array initializer of PCC peripheral base pointers */
+#define PCC_BASE_PTRS                            { PCC0, PCC1 }
+#define    PCC_INSTANCE_MASK            (0xFu)
+#define    PCC_INSTANCE_SHIFT           (12u)
+#define    PCC_PERIPHERAL_MASK          (0xFFFu)
+#define    PCC_PERIPHERAL_SHIFT         (0u)
+#define    PCC_INSTANCE_0               (0u)
+#define    PCC_INSTANCE_1               (1u)
+
+#define    PCC_MSCM_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 1U)
+#define    PCC_AXBS0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 4U)
+#define    PCC_DMA0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 8U)
+#define    PCC_FLEXBUS_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 12U)
+#define    PCC_XRDC_MGR_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 20U)
+#define    PCC0_XRDC_PAC_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 22U)
+#define    PCC0_XRDC_MRC_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 23U)
+#define    PCC_SEMA42_0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 27U)
+#define    PCC_DMAMUX0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 33U)
+#define    PCC_EWM_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 34U)
+#define    PCC_MUA_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 37U)
+#define    PCC_CRC0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 47U)
+#define    PCC_LPIT0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 48U)
+#define    PCC_TPM0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 53U)
+#define    PCC_TPM1_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 54U)
+#define    PCC_TPM2_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 55U)
+#define    PCC_EMVSIM0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 56U)
+#define    PCC_FLEXIO0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 57U)
+#define    PCC_LPI2C0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 58U)
+#define    PCC_LPI2C1_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 59U)
+#define    PCC_LPI2C2_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 60U)
+#define    PCC_I2S0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 61U)
+#define    PCC_USDHC0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 62U)
+#define    PCC_LPSPI0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 63U)
+#define    PCC_LPSPI1_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 64U)
+#define    PCC_LPSPI2_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 65U)
+#define    PCC_LPUART0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 66U)
+#define    PCC_LPUART1_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 67U)
+#define    PCC_LPUART2_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 68U)
+#define    PCC_USB0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 69U)
+#define    PCC_PORTA_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 70U)
+#define    PCC_PORTB_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 71U)
+#define    PCC_PORTC_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 72U)
+#define    PCC_PORTD_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 73U)
+#define    PCC_ADC0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 74U)
+#define    PCC_LPDAC0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 76U)
+#define    PCC_VREF_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 77U)
+#define    PCC_TRACE_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 128U)
+#define    PCC_DMA1_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 8U)
+#define    PCC_GPIOE_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 15U)
+#define    PCC1_XRDC_PAC_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 22U)
+#define    PCC1_XRDC_MRC_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 23U)
+#define    PCC_SEMA42_1_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 27U)
+#define    PCC_DMAMUX1_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 33U)
+#define    PCC_INTMUX1_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 34U)
+#define    PCC_MUB_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 36U)
+#define    PCC_CAU3_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 40U)
+#define    PCC_TRNG_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 41U)
+#define    PCC_LPIT1_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 42U)
+#define    PCC_TPM3_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 45U)
+#define    PCC_LPI2C3_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 46U)
+#define    PCC_LPSPI3_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 53U)
+#define    PCC_LPUART3_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 54U)
+#define    PCC_PORTE_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 55U)
+#define    PCC_MTB_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 128U)
+#define    PCC_EXT_CLK_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 129U)
+#define    PCC_MSCM              (PCC0->CLKCFG[1])
+#define    PCC_AXBS0              (PCC0->CLKCFG[4])
+#define    PCC_DMA0              (PCC0->CLKCFG[8])
+#define    PCC_FLEXBUS              (PCC0->CLKCFG[12])
+#define    PCC_XRDC_MGR              (PCC0->CLKCFG[20])
+#define    PCC0_XRDC_PAC              (PCC0->CLKCFG[22])
+#define    PCC0_XRDC_MRC              (PCC0->CLKCFG[23])
+#define    PCC_SEMA42_0              (PCC0->CLKCFG[27])
+#define    PCC_DMAMUX0              (PCC0->CLKCFG[33])
+#define    PCC_EWM              (PCC0->CLKCFG[34])
+#define    PCC_MUA              (PCC0->CLKCFG[37])
+#define    PCC_CRC0              (PCC0->CLKCFG[47])
+#define    PCC_LPIT0              (PCC0->CLKCFG[48])
+#define    PCC_TPM0              (PCC0->CLKCFG[53])
+#define    PCC_TPM1              (PCC0->CLKCFG[54])
+#define    PCC_TPM2              (PCC0->CLKCFG[55])
+#define    PCC_EMVSIM0              (PCC0->CLKCFG[56])
+#define    PCC_FLEXIO0              (PCC0->CLKCFG[57])
+#define    PCC_LPI2C0              (PCC0->CLKCFG[58])
+#define    PCC_LPI2C1              (PCC0->CLKCFG[59])
+#define    PCC_LPI2C2              (PCC0->CLKCFG[60])
+#define    PCC_I2S0              (PCC0->CLKCFG[61])
+#define    PCC_USDHC0              (PCC0->CLKCFG[62])
+#define    PCC_LPSPI0              (PCC0->CLKCFG[63])
+#define    PCC_LPSPI1              (PCC0->CLKCFG[64])
+#define    PCC_LPSPI2              (PCC0->CLKCFG[65])
+#define    PCC_LPUART0              (PCC0->CLKCFG[66])
+#define    PCC_LPUART1              (PCC0->CLKCFG[67])
+#define    PCC_LPUART2              (PCC0->CLKCFG[68])
+#define    PCC_USB0              (PCC0->CLKCFG[69])
+#define    PCC_PORTA              (PCC0->CLKCFG[70])
+#define    PCC_PORTB              (PCC0->CLKCFG[71])
+#define    PCC_PORTC              (PCC0->CLKCFG[72])
+#define    PCC_PORTD              (PCC0->CLKCFG[73])
+#define    PCC_ADC0              (PCC0->CLKCFG[74])
+#define    PCC_LPDAC0              (PCC0->CLKCFG[76])
+#define    PCC_VREF              (PCC0->CLKCFG[77])
+#define    PCC_TRACE              (PCC0->CLKCFG[128])
+#define    PCC_DMA1              (PCC1->CLKCFG[8])
+#define    PCC_GPIOE              (PCC1->CLKCFG[15])
+#define    PCC1_XRDC_PAC              (PCC1->CLKCFG[22])
+#define    PCC1_XRDC_MRC              (PCC1->CLKCFG[23])
+#define    PCC_SEMA42_1              (PCC1->CLKCFG[27])
+#define    PCC_DMAMUX1              (PCC1->CLKCFG[33])
+#define    PCC_INTMUX1              (PCC1->CLKCFG[34])
+#define    PCC_MUB              (PCC1->CLKCFG[36])
+#define    PCC_CAU3              (PCC1->CLKCFG[40])
+#define    PCC_TRNG              (PCC1->CLKCFG[41])
+#define    PCC_LPIT1              (PCC1->CLKCFG[42])
+#define    PCC_TPM3              (PCC1->CLKCFG[45])
+#define    PCC_LPI2C3              (PCC1->CLKCFG[46])
+#define    PCC_LPSPI3              (PCC1->CLKCFG[53])
+#define    PCC_LPUART3              (PCC1->CLKCFG[54])
+#define    PCC_PORTE              (PCC1->CLKCFG[55])
+#define    PCC_MTB              (PCC1->CLKCFG[128])
+#define    PCC_EXT_CLK              (PCC1->CLKCFG[129])
+
+
+/*!
+ * @}
+ */ /* end of group PCC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PCR[32];                           /**< Pin Control Register 0..Pin Control Register 30, array offset: 0x0, array step: 0x4 */
+  __O  uint32_t GPCLR;                             /**< Global Pin Control Low Register, offset: 0x80 */
+  __O  uint32_t GPCHR;                             /**< Global Pin Control High Register, offset: 0x84 */
+  __O  uint32_t GICLR;                             /**< Global Interrupt Control Low Register, offset: 0x88 */
+  __O  uint32_t GICHR;                             /**< Global Interrupt Control High Register, offset: 0x8C */
+       uint8_t RESERVED_0[16];
+  __IO uint32_t ISFR;                              /**< Interrupt Status Flag Register, offset: 0xA0 */
+       uint8_t RESERVED_1[28];
+  __IO uint32_t DFER;                              /**< Digital Filter Enable Register, offset: 0xC0 */
+  __IO uint32_t DFCR;                              /**< Digital Filter Clock Register, offset: 0xC4 */
+  __IO uint32_t DFWR;                              /**< Digital Filter Width Register, offset: 0xC8 */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PORT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/*! @name PCR - Pin Control Register 0..Pin Control Register 30 */
+/*! @{ */
+#define PORT_PCR_PS_MASK                         (0x1U)
+#define PORT_PCR_PS_SHIFT                        (0U)
+/*! PS - Pull Select
+ *  0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
+ *  0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
+ */
+#define PORT_PCR_PS(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
+#define PORT_PCR_PE_MASK                         (0x2U)
+#define PORT_PCR_PE_SHIFT                        (1U)
+/*! PE - Pull Enable
+ *  0b0..Internal pull resistor is not enabled on the corresponding pin.
+ *  0b1..Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
+ */
+#define PORT_PCR_PE(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
+#define PORT_PCR_SRE_MASK                        (0x4U)
+#define PORT_PCR_SRE_SHIFT                       (2U)
+/*! SRE - Slew Rate Enable
+ *  0b0..Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
+ *  0b1..Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
+ */
+#define PORT_PCR_SRE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
+#define PORT_PCR_PFE_MASK                        (0x10U)
+#define PORT_PCR_PFE_SHIFT                       (4U)
+/*! PFE - Passive Filter Enable
+ *  0b0..Passive input filter is disabled on the corresponding pin.
+ *  0b1..Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
+ */
+#define PORT_PCR_PFE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
+#define PORT_PCR_ODE_MASK                        (0x20U)
+#define PORT_PCR_ODE_SHIFT                       (5U)
+/*! ODE - Open Drain Enable
+ *  0b0..Open drain output is disabled on the corresponding pin.
+ *  0b1..Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
+ */
+#define PORT_PCR_ODE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
+#define PORT_PCR_DSE_MASK                        (0x40U)
+#define PORT_PCR_DSE_SHIFT                       (6U)
+/*! DSE - Drive Strength Enable
+ *  0b0..Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
+ *  0b1..High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
+ */
+#define PORT_PCR_DSE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
+#define PORT_PCR_MUX_MASK                        (0x700U)
+#define PORT_PCR_MUX_SHIFT                       (8U)
+/*! MUX - Pin Mux Control
+ *  0b000..Pin disabled (Alternative 0) (analog).
+ *  0b001..Alternative 1 (GPIO).
+ *  0b010..Alternative 2 (chip-specific).
+ *  0b011..Alternative 3 (chip-specific).
+ *  0b100..Alternative 4 (chip-specific).
+ *  0b101..Alternative 5 (chip-specific).
+ *  0b110..Alternative 6 (chip-specific).
+ *  0b111..Alternative 7 (chip-specific).
+ */
+#define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK                         (0x8000U)
+#define PORT_PCR_LK_SHIFT                        (15U)
+/*! LK - Lock Register
+ *  0b0..Pin Control Register is not locked.
+ *  0b1..Pin Control Register is locked and cannot be updated until the next system reset.
+ */
+#define PORT_PCR_LK(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
+#define PORT_PCR_IRQC_MASK                       (0xF0000U)
+#define PORT_PCR_IRQC_SHIFT                      (16U)
+/*! IRQC - Interrupt Configuration
+ *  0b0000..Interrupt Status Flag (ISF) is disabled.
+ *  0b0001..ISF flag and DMA request on rising edge.
+ *  0b0010..ISF flag and DMA request on falling edge.
+ *  0b0011..ISF flag and DMA request on either edge.
+ *  0b0100..Reserved.
+ *  0b0101..Flag sets on rising edge.
+ *  0b0110..Flag sets on falling edge.
+ *  0b0111..Flag sets on either edge.
+ *  0b1000..ISF flag and Interrupt when logic 0.
+ *  0b1001..ISF flag and Interrupt on rising-edge.
+ *  0b1010..ISF flag and Interrupt on falling-edge.
+ *  0b1011..ISF flag and Interrupt on either edge.
+ *  0b1100..ISF flag and Interrupt when logic 1.
+ *  0b1101..Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]
+ *  0b1110..Enable active low trigger output, flag is disabled.
+ *  0b1111..Reserved.
+ */
+#define PORT_PCR_IRQC(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK                        (0x1000000U)
+#define PORT_PCR_ISF_SHIFT                       (24U)
+/*! ISF - Interrupt Status Flag
+ *  0b0..Configured interrupt is not detected.
+ *  0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
+ */
+#define PORT_PCR_ISF(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
+/*! @} */
+
+/* The count of PORT_PCR */
+#define PORT_PCR_COUNT                           (32U)
+
+/*! @name GPCLR - Global Pin Control Low Register */
+/*! @{ */
+#define PORT_GPCLR_GPWD_MASK                     (0xFFFFU)
+#define PORT_GPCLR_GPWD_SHIFT                    (0U)
+#define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK                     (0xFFFF0000U)
+#define PORT_GPCLR_GPWE_SHIFT                    (16U)
+#define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
+/*! @} */
+
+/*! @name GPCHR - Global Pin Control High Register */
+/*! @{ */
+#define PORT_GPCHR_GPWD_MASK                     (0xFFFFU)
+#define PORT_GPCHR_GPWD_SHIFT                    (0U)
+#define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK                     (0xFFFF0000U)
+#define PORT_GPCHR_GPWE_SHIFT                    (16U)
+#define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
+/*! @} */
+
+/*! @name GICLR - Global Interrupt Control Low Register */
+/*! @{ */
+#define PORT_GICLR_GIWE_MASK                     (0xFFFFU)
+#define PORT_GICLR_GIWE_SHIFT                    (0U)
+#define PORT_GICLR_GIWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GICLR_GIWE_SHIFT)) & PORT_GICLR_GIWE_MASK)
+#define PORT_GICLR_GIWD_MASK                     (0xFFFF0000U)
+#define PORT_GICLR_GIWD_SHIFT                    (16U)
+#define PORT_GICLR_GIWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GICLR_GIWD_SHIFT)) & PORT_GICLR_GIWD_MASK)
+/*! @} */
+
+/*! @name GICHR - Global Interrupt Control High Register */
+/*! @{ */
+#define PORT_GICHR_GIWE_MASK                     (0xFFFFU)
+#define PORT_GICHR_GIWE_SHIFT                    (0U)
+#define PORT_GICHR_GIWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GICHR_GIWE_SHIFT)) & PORT_GICHR_GIWE_MASK)
+#define PORT_GICHR_GIWD_MASK                     (0xFFFF0000U)
+#define PORT_GICHR_GIWD_SHIFT                    (16U)
+#define PORT_GICHR_GIWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GICHR_GIWD_SHIFT)) & PORT_GICHR_GIWD_MASK)
+/*! @} */
+
+/*! @name ISFR - Interrupt Status Flag Register */
+/*! @{ */
+#define PORT_ISFR_ISF_MASK                       (0xFFFFFFFFU)
+#define PORT_ISFR_ISF_SHIFT                      (0U)
+#define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
+/*! @} */
+
+/*! @name DFER - Digital Filter Enable Register */
+/*! @{ */
+#define PORT_DFER_DFE_MASK                       (0xFFFFFFFFU)
+#define PORT_DFER_DFE_SHIFT                      (0U)
+#define PORT_DFER_DFE(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
+/*! @} */
+
+/*! @name DFCR - Digital Filter Clock Register */
+/*! @{ */
+#define PORT_DFCR_CS_MASK                        (0x1U)
+#define PORT_DFCR_CS_SHIFT                       (0U)
+/*! CS - Clock Source
+ *  0b0..Digital filters are clocked by the bus clock.
+ *  0b1..Digital filters are clocked by the 8 clock.
+ */
+#define PORT_DFCR_CS(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
+/*! @} */
+
+/*! @name DFWR - Digital Filter Width Register */
+/*! @{ */
+#define PORT_DFWR_FILT_MASK                      (0x1FU)
+#define PORT_DFWR_FILT_SHIFT                     (0U)
+#define PORT_DFWR_FILT(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE                               (0x40046000u)
+/** Peripheral PORTA base pointer */
+#define PORTA                                    ((PORT_Type *)PORTA_BASE)
+/** Peripheral PORTB base address */
+#define PORTB_BASE                               (0x40047000u)
+/** Peripheral PORTB base pointer */
+#define PORTB                                    ((PORT_Type *)PORTB_BASE)
+/** Peripheral PORTC base address */
+#define PORTC_BASE                               (0x40048000u)
+/** Peripheral PORTC base pointer */
+#define PORTC                                    ((PORT_Type *)PORTC_BASE)
+/** Peripheral PORTD base address */
+#define PORTD_BASE                               (0x40049000u)
+/** Peripheral PORTD base pointer */
+#define PORTD                                    ((PORT_Type *)PORTD_BASE)
+/** Peripheral PORTE base address */
+#define PORTE_BASE                               (0x41037000u)
+/** Peripheral PORTE base pointer */
+#define PORTE                                    ((PORT_Type *)PORTE_BASE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS                          { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS                           { PORTA, PORTB, PORTC, PORTD, PORTE }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS                                { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RSIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RSIM_Peripheral_Access_Layer RSIM Peripheral Access Layer
+ * @{
+ */
+
+/** RSIM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONTROL;                           /**< Radio System Control, offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  __IO uint32_t MISC;                              /**< Radio Miscellaneous, offset: 0x10 */
+  __IO uint32_t POWER;                             /**< RSIM Power Control, offset: 0x14 */
+  __IO uint32_t SW_CONFIG;                         /**< Radio Software Configuration, offset: 0x18 */
+       uint8_t RESERVED_1[228];
+  __I  uint32_t DSM_TIMER;                         /**< Deep Sleep Timer, offset: 0x100 */
+  __IO uint32_t DSM_CONTROL;                       /**< Deep Sleep Timer Control, offset: 0x104 */
+  __IO uint32_t DSM_WAKEUP;                        /**< Deep Sleep Wakeup Sequence, offset: 0x108 */
+  __I  uint32_t WOR_DURATION;                      /**< WOR Deep Sleep Duration, offset: 0x10C */
+  __IO uint32_t WOR_WAKE;                          /**< WOR Deep Sleep Wake Time, offset: 0x110 */
+       uint8_t RESERVED_2[8];
+  __IO uint32_t MAN_SLEEP;                         /**< MAN Deep Sleep Time, offset: 0x11C */
+  __IO uint32_t MAN_WAKE;                          /**< MAN Deep Sleep Wake Time, offset: 0x120 */
+  __IO uint32_t RF_OSC_CTRL;                       /**< Radio Oscillator Control, offset: 0x124 */
+  __IO uint32_t ANA_TEST;                          /**< Radio Analog Test Registers, offset: 0x128 */
+  __IO uint32_t ANA_TRIM;                          /**< Radio Analog Trim Registers, offset: 0x12C */
+} RSIM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RSIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RSIM_Register_Masks RSIM Register Masks
+ * @{
+ */
+
+/*! @name CONTROL - Radio System Control */
+/*! @{ */
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_EN_MASK    (0x1U)
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_EN_SHIFT   (0U)
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_POWER_REQ_EN_SHIFT)) & RSIM_CONTROL_BLE_RF_POWER_REQ_EN_MASK)
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_STAT_MASK  (0x2U)
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_STAT_SHIFT (1U)
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_STAT(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_POWER_REQ_STAT_SHIFT)) & RSIM_CONTROL_BLE_RF_POWER_REQ_STAT_MASK)
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT_EN_MASK (0x10U)
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT_EN_SHIFT (4U)
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT_EN(x)  (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_POWER_REQ_INT_EN_SHIFT)) & RSIM_CONTROL_BLE_RF_POWER_REQ_INT_EN_MASK)
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT_MASK   (0x20U)
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT_SHIFT  (5U)
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT(x)     (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_POWER_REQ_INT_SHIFT)) & RSIM_CONTROL_BLE_RF_POWER_REQ_INT_MASK)
+#define RSIM_CONTROL_RF_OSC_EN_MASK              (0x100U)
+#define RSIM_CONTROL_RF_OSC_EN_SHIFT             (8U)
+#define RSIM_CONTROL_RF_OSC_EN(x)                (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_EN_SHIFT)) & RSIM_CONTROL_RF_OSC_EN_MASK)
+#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_MASK (0x1000U)
+#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_SHIFT (12U)
+#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_SHIFT)) & RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_MASK)
+#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_MASK (0x2000U)
+#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_SHIFT (13U)
+/*! RADIO_GASKET_BYPASS_OVRD - Radio Gasket Bypass Override
+ *  0b0..XCVR and Link Layer Register Clock is the RF Ref Osc Clock
+ *  0b1..XCVR and Link Layer Register Clock is the SoC IPG Clock
+ */
+#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_SHIFT)) & RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_MASK)
+#define RSIM_CONTROL_IPP_OBE_BLE_EARLY_WARNING_MASK (0x4000U)
+#define RSIM_CONTROL_IPP_OBE_BLE_EARLY_WARNING_SHIFT (14U)
+#define RSIM_CONTROL_IPP_OBE_BLE_EARLY_WARNING(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_BLE_EARLY_WARNING_SHIFT)) & RSIM_CONTROL_IPP_OBE_BLE_EARLY_WARNING_MASK)
+#define RSIM_CONTROL_IPP_OBE_RF_ACTIVE_MASK      (0x8000U)
+#define RSIM_CONTROL_IPP_OBE_RF_ACTIVE_SHIFT     (15U)
+#define RSIM_CONTROL_IPP_OBE_RF_ACTIVE(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_RF_ACTIVE_SHIFT)) & RSIM_CONTROL_IPP_OBE_RF_ACTIVE_MASK)
+#define RSIM_CONTROL_IPP_OBE_RF_OSC_EN_MASK      (0x10000U)
+#define RSIM_CONTROL_IPP_OBE_RF_OSC_EN_SHIFT     (16U)
+#define RSIM_CONTROL_IPP_OBE_RF_OSC_EN(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_RF_OSC_EN_SHIFT)) & RSIM_CONTROL_IPP_OBE_RF_OSC_EN_MASK)
+#define RSIM_CONTROL_IPP_OBE_RF_STATUS_MASK      (0x40000U)
+#define RSIM_CONTROL_IPP_OBE_RF_STATUS_SHIFT     (18U)
+#define RSIM_CONTROL_IPP_OBE_RF_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_RF_STATUS_SHIFT)) & RSIM_CONTROL_IPP_OBE_RF_STATUS_MASK)
+#define RSIM_CONTROL_IPP_OBE_RF_PRIORITY_MASK    (0x80000U)
+#define RSIM_CONTROL_IPP_OBE_RF_PRIORITY_SHIFT   (19U)
+#define RSIM_CONTROL_IPP_OBE_RF_PRIORITY(x)      (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_RF_PRIORITY_SHIFT)) & RSIM_CONTROL_IPP_OBE_RF_PRIORITY_MASK)
+#define RSIM_CONTROL_BLE_DSM_EXIT_MASK           (0x100000U)
+#define RSIM_CONTROL_BLE_DSM_EXIT_SHIFT          (20U)
+#define RSIM_CONTROL_BLE_DSM_EXIT(x)             (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_DSM_EXIT_SHIFT)) & RSIM_CONTROL_BLE_DSM_EXIT_MASK)
+#define RSIM_CONTROL_WOR_DSM_EXIT_MASK           (0x200000U)
+#define RSIM_CONTROL_WOR_DSM_EXIT_SHIFT          (21U)
+#define RSIM_CONTROL_WOR_DSM_EXIT(x)             (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_WOR_DSM_EXIT_SHIFT)) & RSIM_CONTROL_WOR_DSM_EXIT_MASK)
+#define RSIM_CONTROL_RF_OSC_READY_MASK           (0x1000000U)
+#define RSIM_CONTROL_RF_OSC_READY_SHIFT          (24U)
+#define RSIM_CONTROL_RF_OSC_READY(x)             (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_READY_SHIFT)) & RSIM_CONTROL_RF_OSC_READY_MASK)
+#define RSIM_CONTROL_RF_OSC_READY_OVRD_EN_MASK   (0x2000000U)
+#define RSIM_CONTROL_RF_OSC_READY_OVRD_EN_SHIFT  (25U)
+#define RSIM_CONTROL_RF_OSC_READY_OVRD_EN(x)     (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_READY_OVRD_EN_SHIFT)) & RSIM_CONTROL_RF_OSC_READY_OVRD_EN_MASK)
+#define RSIM_CONTROL_RF_OSC_READY_OVRD_MASK      (0x4000000U)
+#define RSIM_CONTROL_RF_OSC_READY_OVRD_SHIFT     (26U)
+#define RSIM_CONTROL_RF_OSC_READY_OVRD(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_READY_OVRD_SHIFT)) & RSIM_CONTROL_RF_OSC_READY_OVRD_MASK)
+#define RSIM_CONTROL_RSIM_CGC_BLE_EN_MASK        (0x8000000U)
+#define RSIM_CONTROL_RSIM_CGC_BLE_EN_SHIFT       (27U)
+/*! RSIM_CGC_BLE_EN - BLE Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define RSIM_CONTROL_RSIM_CGC_BLE_EN(x)          (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_CGC_BLE_EN_SHIFT)) & RSIM_CONTROL_RSIM_CGC_BLE_EN_MASK)
+#define RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK       (0x10000000U)
+#define RSIM_CONTROL_RSIM_CGC_XCVR_EN_SHIFT      (28U)
+/*! RSIM_CGC_XCVR_EN - XCVR Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define RSIM_CONTROL_RSIM_CGC_XCVR_EN(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_CGC_XCVR_EN_SHIFT)) & RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK)
+#define RSIM_CONTROL_RSIM_CGC_ZIG_EN_MASK        (0x20000000U)
+#define RSIM_CONTROL_RSIM_CGC_ZIG_EN_SHIFT       (29U)
+/*! RSIM_CGC_ZIG_EN - ZIG Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define RSIM_CONTROL_RSIM_CGC_ZIG_EN(x)          (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_CGC_ZIG_EN_SHIFT)) & RSIM_CONTROL_RSIM_CGC_ZIG_EN_MASK)
+#define RSIM_CONTROL_RSIM_CGC_GEN_EN_MASK        (0x80000000U)
+#define RSIM_CONTROL_RSIM_CGC_GEN_EN_SHIFT       (31U)
+/*! RSIM_CGC_GEN_EN - GEN Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define RSIM_CONTROL_RSIM_CGC_GEN_EN(x)          (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_CGC_GEN_EN_SHIFT)) & RSIM_CONTROL_RSIM_CGC_GEN_EN_MASK)
+/*! @} */
+
+/*! @name MISC - Radio Miscellaneous */
+/*! @{ */
+#define RSIM_MISC_RADIO_VERSION_MASK             (0xFF000000U)
+#define RSIM_MISC_RADIO_VERSION_SHIFT            (24U)
+#define RSIM_MISC_RADIO_VERSION(x)               (((uint32_t)(((uint32_t)(x)) << RSIM_MISC_RADIO_VERSION_SHIFT)) & RSIM_MISC_RADIO_VERSION_MASK)
+/*! @} */
+
+/*! @name POWER - RSIM Power Control */
+/*! @{ */
+#define RSIM_POWER_RADIO_STOP_MODE_STAT_MASK     (0x7U)
+#define RSIM_POWER_RADIO_STOP_MODE_STAT_SHIFT    (0U)
+#define RSIM_POWER_RADIO_STOP_MODE_STAT(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_STOP_MODE_STAT_SHIFT)) & RSIM_POWER_RADIO_STOP_MODE_STAT_MASK)
+#define RSIM_POWER_SPM_STOP_ACK_STAT_MASK        (0x8U)
+#define RSIM_POWER_SPM_STOP_ACK_STAT_SHIFT       (3U)
+#define RSIM_POWER_SPM_STOP_ACK_STAT(x)          (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_STOP_ACK_STAT_SHIFT)) & RSIM_POWER_SPM_STOP_ACK_STAT_MASK)
+#define RSIM_POWER_RADIO_STOP_MODE_OVRD_MASK     (0x70U)
+#define RSIM_POWER_RADIO_STOP_MODE_OVRD_SHIFT    (4U)
+#define RSIM_POWER_RADIO_STOP_MODE_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_STOP_MODE_OVRD_SHIFT)) & RSIM_POWER_RADIO_STOP_MODE_OVRD_MASK)
+#define RSIM_POWER_RADIO_STOP_MODE_OVRD_EN_MASK  (0x80U)
+#define RSIM_POWER_RADIO_STOP_MODE_OVRD_EN_SHIFT (7U)
+#define RSIM_POWER_RADIO_STOP_MODE_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_STOP_MODE_OVRD_EN_SHIFT)) & RSIM_POWER_RADIO_STOP_MODE_OVRD_EN_MASK)
+#define RSIM_POWER_RADIO_STOP_ACK_STAT_MASK      (0x100U)
+#define RSIM_POWER_RADIO_STOP_ACK_STAT_SHIFT     (8U)
+#define RSIM_POWER_RADIO_STOP_ACK_STAT(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_STOP_ACK_STAT_SHIFT)) & RSIM_POWER_RADIO_STOP_ACK_STAT_MASK)
+#define RSIM_POWER_RADIO_STOP_REQ_STAT_MASK      (0x200U)
+#define RSIM_POWER_RADIO_STOP_REQ_STAT_SHIFT     (9U)
+#define RSIM_POWER_RADIO_STOP_REQ_STAT(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_STOP_REQ_STAT_SHIFT)) & RSIM_POWER_RADIO_STOP_REQ_STAT_MASK)
+#define RSIM_POWER_RSIM_STOP_REQ_OVRD_MASK       (0x400U)
+#define RSIM_POWER_RSIM_STOP_REQ_OVRD_SHIFT      (10U)
+#define RSIM_POWER_RSIM_STOP_REQ_OVRD(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_STOP_REQ_OVRD_SHIFT)) & RSIM_POWER_RSIM_STOP_REQ_OVRD_MASK)
+#define RSIM_POWER_RSIM_STOP_REQ_OVRD_EN_MASK    (0x800U)
+#define RSIM_POWER_RSIM_STOP_REQ_OVRD_EN_SHIFT   (11U)
+#define RSIM_POWER_RSIM_STOP_REQ_OVRD_EN(x)      (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_STOP_REQ_OVRD_EN_SHIFT)) & RSIM_POWER_RSIM_STOP_REQ_OVRD_EN_MASK)
+#define RSIM_POWER_RF_OSC_EN_OVRD_MASK           (0x1000U)
+#define RSIM_POWER_RF_OSC_EN_OVRD_SHIFT          (12U)
+#define RSIM_POWER_RF_OSC_EN_OVRD(x)             (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RF_OSC_EN_OVRD_SHIFT)) & RSIM_POWER_RF_OSC_EN_OVRD_MASK)
+#define RSIM_POWER_RF_OSC_EN_OVRD_EN_MASK        (0x2000U)
+#define RSIM_POWER_RF_OSC_EN_OVRD_EN_SHIFT       (13U)
+#define RSIM_POWER_RF_OSC_EN_OVRD_EN(x)          (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RF_OSC_EN_OVRD_EN_SHIFT)) & RSIM_POWER_RF_OSC_EN_OVRD_EN_MASK)
+#define RSIM_POWER_RF_POWER_EN_OVRD_MASK         (0x4000U)
+#define RSIM_POWER_RF_POWER_EN_OVRD_SHIFT        (14U)
+#define RSIM_POWER_RF_POWER_EN_OVRD(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RF_POWER_EN_OVRD_SHIFT)) & RSIM_POWER_RF_POWER_EN_OVRD_MASK)
+#define RSIM_POWER_RF_POWER_EN_OVRD_EN_MASK      (0x8000U)
+#define RSIM_POWER_RF_POWER_EN_OVRD_EN_SHIFT     (15U)
+#define RSIM_POWER_RF_POWER_EN_OVRD_EN(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RF_POWER_EN_OVRD_EN_SHIFT)) & RSIM_POWER_RF_POWER_EN_OVRD_EN_MASK)
+#define RSIM_POWER_SPM_ISO_STAT_MASK             (0x10000U)
+#define RSIM_POWER_SPM_ISO_STAT_SHIFT            (16U)
+#define RSIM_POWER_SPM_ISO_STAT(x)               (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_ISO_STAT_SHIFT)) & RSIM_POWER_SPM_ISO_STAT_MASK)
+#define RSIM_POWER_RADIO_ISO_STAT_MASK           (0x20000U)
+#define RSIM_POWER_RADIO_ISO_STAT_SHIFT          (17U)
+#define RSIM_POWER_RADIO_ISO_STAT(x)             (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_ISO_STAT_SHIFT)) & RSIM_POWER_RADIO_ISO_STAT_MASK)
+#define RSIM_POWER_RSIM_ISO_OVRD_MASK            (0x40000U)
+#define RSIM_POWER_RSIM_ISO_OVRD_SHIFT           (18U)
+#define RSIM_POWER_RSIM_ISO_OVRD(x)              (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_ISO_OVRD_SHIFT)) & RSIM_POWER_RSIM_ISO_OVRD_MASK)
+#define RSIM_POWER_RSIM_ISO_OVRD_EN_MASK         (0x80000U)
+#define RSIM_POWER_RSIM_ISO_OVRD_EN_SHIFT        (19U)
+#define RSIM_POWER_RSIM_ISO_OVRD_EN(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_ISO_OVRD_EN_SHIFT)) & RSIM_POWER_RSIM_ISO_OVRD_EN_MASK)
+#define RSIM_POWER_SPM_RUN_ACK_STAT_MASK         (0x100000U)
+#define RSIM_POWER_SPM_RUN_ACK_STAT_SHIFT        (20U)
+#define RSIM_POWER_SPM_RUN_ACK_STAT(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_RUN_ACK_STAT_SHIFT)) & RSIM_POWER_SPM_RUN_ACK_STAT_MASK)
+#define RSIM_POWER_RADIO_RUN_REQ_STAT_MASK       (0x200000U)
+#define RSIM_POWER_RADIO_RUN_REQ_STAT_SHIFT      (21U)
+#define RSIM_POWER_RADIO_RUN_REQ_STAT(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_RUN_REQ_STAT_SHIFT)) & RSIM_POWER_RADIO_RUN_REQ_STAT_MASK)
+#define RSIM_POWER_RSIM_RUN_REQ_OVRD_MASK        (0x400000U)
+#define RSIM_POWER_RSIM_RUN_REQ_OVRD_SHIFT       (22U)
+#define RSIM_POWER_RSIM_RUN_REQ_OVRD(x)          (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_RUN_REQ_OVRD_SHIFT)) & RSIM_POWER_RSIM_RUN_REQ_OVRD_MASK)
+#define RSIM_POWER_RSIM_RUN_REQ_OVRD_EN_MASK     (0x800000U)
+#define RSIM_POWER_RSIM_RUN_REQ_OVRD_EN_SHIFT    (23U)
+#define RSIM_POWER_RSIM_RUN_REQ_OVRD_EN(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_RUN_REQ_OVRD_EN_SHIFT)) & RSIM_POWER_RSIM_RUN_REQ_OVRD_EN_MASK)
+#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_MASK    (0x1000000U)
+#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_SHIFT   (24U)
+#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD(x)      (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_SHIFT)) & RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_MASK)
+#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_EN_MASK (0x2000000U)
+#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_EN_SHIFT (25U)
+#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_EN(x)   (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_EN_SHIFT)) & RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_EN_MASK)
+#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_MASK     (0x4000000U)
+#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_SHIFT    (26U)
+#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_SHIFT)) & RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_MASK)
+#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_EN_MASK  (0x8000000U)
+#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_EN_SHIFT (27U)
+#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_EN_SHIFT)) & RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_EN_MASK)
+#define RSIM_POWER_RSIM_STOP_MODE_MASK           (0x70000000U)
+#define RSIM_POWER_RSIM_STOP_MODE_SHIFT          (28U)
+/*! RSIM_STOP_MODE - RSIM lowest allowed Stop Mode
+ *  0b000..Reserved
+ *  0b001..Reserved
+ *  0b011..RLLS mode (Radio State Retention mode)
+ *  0b111..RVLLS mode (This is the POR setting)
+ */
+#define RSIM_POWER_RSIM_STOP_MODE(x)             (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_STOP_MODE_SHIFT)) & RSIM_POWER_RSIM_STOP_MODE_MASK)
+#define RSIM_POWER_RSIM_RUN_REQUEST_MASK         (0x80000000U)
+#define RSIM_POWER_RSIM_RUN_REQUEST_SHIFT        (31U)
+#define RSIM_POWER_RSIM_RUN_REQUEST(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_RUN_REQUEST_SHIFT)) & RSIM_POWER_RSIM_RUN_REQUEST_MASK)
+/*! @} */
+
+/*! @name SW_CONFIG - Radio Software Configuration */
+/*! @{ */
+#define RSIM_SW_CONFIG_RADIO_CONFIGURED_POR_RESET_MASK (0x1U)
+#define RSIM_SW_CONFIG_RADIO_CONFIGURED_POR_RESET_SHIFT (0U)
+#define RSIM_SW_CONFIG_RADIO_CONFIGURED_POR_RESET(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO_CONFIGURED_POR_RESET_SHIFT)) & RSIM_SW_CONFIG_RADIO_CONFIGURED_POR_RESET_MASK)
+#define RSIM_SW_CONFIG_RADIO_CONFIGURED_SYS_RESET_MASK (0x2U)
+#define RSIM_SW_CONFIG_RADIO_CONFIGURED_SYS_RESET_SHIFT (1U)
+#define RSIM_SW_CONFIG_RADIO_CONFIGURED_SYS_RESET(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO_CONFIGURED_SYS_RESET_SHIFT)) & RSIM_SW_CONFIG_RADIO_CONFIGURED_SYS_RESET_MASK)
+#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_MASK  (0x10U)
+#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_SHIFT (4U)
+#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_SHIFT)) & RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_MASK)
+#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_EN_MASK (0x20U)
+#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_EN_SHIFT (5U)
+#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_EN_SHIFT)) & RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_EN_MASK)
+#define RSIM_SW_CONFIG_RADIO_POR_BIT_MASK        (0x100U)
+#define RSIM_SW_CONFIG_RADIO_POR_BIT_SHIFT       (8U)
+#define RSIM_SW_CONFIG_RADIO_POR_BIT(x)          (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO_POR_BIT_SHIFT)) & RSIM_SW_CONFIG_RADIO_POR_BIT_MASK)
+#define RSIM_SW_CONFIG_RSIM_RADIO_ISO_POR_OVRD_MASK (0x1000U)
+#define RSIM_SW_CONFIG_RSIM_RADIO_ISO_POR_OVRD_SHIFT (12U)
+#define RSIM_SW_CONFIG_RSIM_RADIO_ISO_POR_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RSIM_RADIO_ISO_POR_OVRD_SHIFT)) & RSIM_SW_CONFIG_RSIM_RADIO_ISO_POR_OVRD_MASK)
+#define RSIM_SW_CONFIG_RADIO_RESET_BIT_MASK      (0x10000U)
+#define RSIM_SW_CONFIG_RADIO_RESET_BIT_SHIFT     (16U)
+#define RSIM_SW_CONFIG_RADIO_RESET_BIT(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO_RESET_BIT_SHIFT)) & RSIM_SW_CONFIG_RADIO_RESET_BIT_MASK)
+#define RSIM_SW_CONFIG_WAKEUP_INTERRUPT_SOURCE_MASK (0x300000U)
+#define RSIM_SW_CONFIG_WAKEUP_INTERRUPT_SOURCE_SHIFT (20U)
+/*! WAKEUP_INTERRUPT_SOURCE - RSIM Wakeup Interrupt Source Selector
+ *  0b00..No Radio Power-On Sequence interrupt will be generated.
+ *  0b01..A Power-On Sequence interrupt will be generated when the RF Power Request occurs, including unblocked requests from an external source to use the RF OSC.
+ *  0b10..A Power-On Sequence interrupt will be generated when the RF OSC Request occurs, but not if the RF OSC request was from an external source.
+ *  0b11..A Power-On Sequence interrupt will be generated when the RSIM RF Active Warning occurs
+ */
+#define RSIM_SW_CONFIG_WAKEUP_INTERRUPT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_WAKEUP_INTERRUPT_SOURCE_SHIFT)) & RSIM_SW_CONFIG_WAKEUP_INTERRUPT_SOURCE_MASK)
+#define RSIM_SW_CONFIG_RADIO0_INTERRUPT_EN_MASK  (0x1000000U)
+#define RSIM_SW_CONFIG_RADIO0_INTERRUPT_EN_SHIFT (24U)
+#define RSIM_SW_CONFIG_RADIO0_INTERRUPT_EN(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO0_INTERRUPT_EN_SHIFT)) & RSIM_SW_CONFIG_RADIO0_INTERRUPT_EN_MASK)
+#define RSIM_SW_CONFIG_RADIO1_INTERRUPT_EN_MASK  (0x2000000U)
+#define RSIM_SW_CONFIG_RADIO1_INTERRUPT_EN_SHIFT (25U)
+#define RSIM_SW_CONFIG_RADIO1_INTERRUPT_EN(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO1_INTERRUPT_EN_SHIFT)) & RSIM_SW_CONFIG_RADIO1_INTERRUPT_EN_MASK)
+#define RSIM_SW_CONFIG_BLOCK_SOC_RESETS_MASK     (0x10000000U)
+#define RSIM_SW_CONFIG_BLOCK_SOC_RESETS_SHIFT    (28U)
+#define RSIM_SW_CONFIG_BLOCK_SOC_RESETS(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_BLOCK_SOC_RESETS_SHIFT)) & RSIM_SW_CONFIG_BLOCK_SOC_RESETS_MASK)
+#define RSIM_SW_CONFIG_BLOCK_RADIO_OUTPUTS_MASK  (0x20000000U)
+#define RSIM_SW_CONFIG_BLOCK_RADIO_OUTPUTS_SHIFT (29U)
+#define RSIM_SW_CONFIG_BLOCK_RADIO_OUTPUTS(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_BLOCK_RADIO_OUTPUTS_SHIFT)) & RSIM_SW_CONFIG_BLOCK_RADIO_OUTPUTS_MASK)
+#define RSIM_SW_CONFIG_ALLOW_DFT_RESETS_MASK     (0x40000000U)
+#define RSIM_SW_CONFIG_ALLOW_DFT_RESETS_SHIFT    (30U)
+#define RSIM_SW_CONFIG_ALLOW_DFT_RESETS(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_ALLOW_DFT_RESETS_SHIFT)) & RSIM_SW_CONFIG_ALLOW_DFT_RESETS_MASK)
+#define RSIM_SW_CONFIG_BLOCK_EXT_OSC_PWR_REQ_MASK (0x80000000U)
+#define RSIM_SW_CONFIG_BLOCK_EXT_OSC_PWR_REQ_SHIFT (31U)
+#define RSIM_SW_CONFIG_BLOCK_EXT_OSC_PWR_REQ(x)  (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_BLOCK_EXT_OSC_PWR_REQ_SHIFT)) & RSIM_SW_CONFIG_BLOCK_EXT_OSC_PWR_REQ_MASK)
+/*! @} */
+
+/*! @name DSM_TIMER - Deep Sleep Timer */
+/*! @{ */
+#define RSIM_DSM_TIMER_DSM_TIMER_MASK            (0xFFFFFFU)
+#define RSIM_DSM_TIMER_DSM_TIMER_SHIFT           (0U)
+#define RSIM_DSM_TIMER_DSM_TIMER(x)              (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_TIMER_DSM_TIMER_SHIFT)) & RSIM_DSM_TIMER_DSM_TIMER_MASK)
+/*! @} */
+
+/*! @name DSM_CONTROL - Deep Sleep Timer Control */
+/*! @{ */
+#define RSIM_DSM_CONTROL_DSM_WOR_READY_MASK      (0x1U)
+#define RSIM_DSM_CONTROL_DSM_WOR_READY_SHIFT     (0U)
+#define RSIM_DSM_CONTROL_DSM_WOR_READY(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_WOR_READY_SHIFT)) & RSIM_DSM_CONTROL_DSM_WOR_READY_MASK)
+#define RSIM_DSM_CONTROL_WOR_DEEP_SLEEP_STATUS_MASK (0x2U)
+#define RSIM_DSM_CONTROL_WOR_DEEP_SLEEP_STATUS_SHIFT (1U)
+#define RSIM_DSM_CONTROL_WOR_DEEP_SLEEP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_DEEP_SLEEP_STATUS_SHIFT)) & RSIM_DSM_CONTROL_WOR_DEEP_SLEEP_STATUS_MASK)
+#define RSIM_DSM_CONTROL_DSM_WOR_FINISHED_MASK   (0x4U)
+#define RSIM_DSM_CONTROL_DSM_WOR_FINISHED_SHIFT  (2U)
+#define RSIM_DSM_CONTROL_DSM_WOR_FINISHED(x)     (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_WOR_FINISHED_SHIFT)) & RSIM_DSM_CONTROL_DSM_WOR_FINISHED_MASK)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQUEST_EN_MASK (0x8U)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQUEST_EN_SHIFT (3U)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQUEST_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_WAKEUP_REQUEST_EN_SHIFT)) & RSIM_DSM_CONTROL_WOR_WAKEUP_REQUEST_EN_MASK)
+#define RSIM_DSM_CONTROL_WOR_SLEEP_REQUEST_MASK  (0x10U)
+#define RSIM_DSM_CONTROL_WOR_SLEEP_REQUEST_SHIFT (4U)
+#define RSIM_DSM_CONTROL_WOR_SLEEP_REQUEST(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_SLEEP_REQUEST_SHIFT)) & RSIM_DSM_CONTROL_WOR_SLEEP_REQUEST_MASK)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_MASK     (0x20U)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_SHIFT    (5U)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_SHIFT)) & RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_MASK)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_INTERRUPT_EN_MASK (0x40U)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_INTERRUPT_EN_SHIFT (6U)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_INTERRUPT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_WAKEUP_INTERRUPT_EN_SHIFT)) & RSIM_DSM_CONTROL_WOR_WAKEUP_INTERRUPT_EN_MASK)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_INT_MASK (0x80U)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_INT_SHIFT (7U)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_INT(x)   (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_INT_SHIFT)) & RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_INT_MASK)
+#define RSIM_DSM_CONTROL_DSM_MAN_READY_MASK      (0x100U)
+#define RSIM_DSM_CONTROL_DSM_MAN_READY_SHIFT     (8U)
+#define RSIM_DSM_CONTROL_DSM_MAN_READY(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_MAN_READY_SHIFT)) & RSIM_DSM_CONTROL_DSM_MAN_READY_MASK)
+#define RSIM_DSM_CONTROL_MAN_DEEP_SLEEP_STATUS_MASK (0x200U)
+#define RSIM_DSM_CONTROL_MAN_DEEP_SLEEP_STATUS_SHIFT (9U)
+#define RSIM_DSM_CONTROL_MAN_DEEP_SLEEP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_DEEP_SLEEP_STATUS_SHIFT)) & RSIM_DSM_CONTROL_MAN_DEEP_SLEEP_STATUS_MASK)
+#define RSIM_DSM_CONTROL_DSM_MAN_FINISHED_MASK   (0x400U)
+#define RSIM_DSM_CONTROL_DSM_MAN_FINISHED_SHIFT  (10U)
+#define RSIM_DSM_CONTROL_DSM_MAN_FINISHED(x)     (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_MAN_FINISHED_SHIFT)) & RSIM_DSM_CONTROL_DSM_MAN_FINISHED_MASK)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQUEST_EN_MASK (0x800U)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQUEST_EN_SHIFT (11U)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQUEST_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_WAKEUP_REQUEST_EN_SHIFT)) & RSIM_DSM_CONTROL_MAN_WAKEUP_REQUEST_EN_MASK)
+#define RSIM_DSM_CONTROL_MAN_SLEEP_REQUEST_MASK  (0x1000U)
+#define RSIM_DSM_CONTROL_MAN_SLEEP_REQUEST_SHIFT (12U)
+#define RSIM_DSM_CONTROL_MAN_SLEEP_REQUEST(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_SLEEP_REQUEST_SHIFT)) & RSIM_DSM_CONTROL_MAN_SLEEP_REQUEST_MASK)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_MASK     (0x2000U)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_SHIFT    (13U)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_SHIFT)) & RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_MASK)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_INTERRUPT_EN_MASK (0x4000U)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_INTERRUPT_EN_SHIFT (14U)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_INTERRUPT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_WAKEUP_INTERRUPT_EN_SHIFT)) & RSIM_DSM_CONTROL_MAN_WAKEUP_INTERRUPT_EN_MASK)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_INT_MASK (0x8000U)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_INT_SHIFT (15U)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_INT(x)   (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_INT_SHIFT)) & RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_INT_MASK)
+#define RSIM_DSM_CONTROL_WIFI_COEXIST_1_MASK     (0x10000U)
+#define RSIM_DSM_CONTROL_WIFI_COEXIST_1_SHIFT    (16U)
+#define RSIM_DSM_CONTROL_WIFI_COEXIST_1(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WIFI_COEXIST_1_SHIFT)) & RSIM_DSM_CONTROL_WIFI_COEXIST_1_MASK)
+#define RSIM_DSM_CONTROL_WIFI_COEXIST_2_MASK     (0x20000U)
+#define RSIM_DSM_CONTROL_WIFI_COEXIST_2_SHIFT    (17U)
+#define RSIM_DSM_CONTROL_WIFI_COEXIST_2(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WIFI_COEXIST_2_SHIFT)) & RSIM_DSM_CONTROL_WIFI_COEXIST_2_MASK)
+#define RSIM_DSM_CONTROL_WIFI_COEXIST_3_MASK     (0x40000U)
+#define RSIM_DSM_CONTROL_WIFI_COEXIST_3_SHIFT    (18U)
+#define RSIM_DSM_CONTROL_WIFI_COEXIST_3(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WIFI_COEXIST_3_SHIFT)) & RSIM_DSM_CONTROL_WIFI_COEXIST_3_MASK)
+#define RSIM_DSM_CONTROL_RF_ACTIVE_ENDS_WITH_TSM_MASK (0x100000U)
+#define RSIM_DSM_CONTROL_RF_ACTIVE_ENDS_WITH_TSM_SHIFT (20U)
+#define RSIM_DSM_CONTROL_RF_ACTIVE_ENDS_WITH_TSM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_RF_ACTIVE_ENDS_WITH_TSM_SHIFT)) & RSIM_DSM_CONTROL_RF_ACTIVE_ENDS_WITH_TSM_MASK)
+#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_ENDS_WITH_TSM_MASK (0x200000U)
+#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_ENDS_WITH_TSM_SHIFT (21U)
+#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_ENDS_WITH_TSM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_SW_RF_ACTIVE_ENDS_WITH_TSM_SHIFT)) & RSIM_DSM_CONTROL_SW_RF_ACTIVE_ENDS_WITH_TSM_MASK)
+#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_BIT_MASK   (0x400000U)
+#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_BIT_SHIFT  (22U)
+#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_BIT(x)     (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_SW_RF_ACTIVE_BIT_SHIFT)) & RSIM_DSM_CONTROL_SW_RF_ACTIVE_BIT_MASK)
+#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_EN_MASK    (0x800000U)
+#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_EN_SHIFT   (23U)
+#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_EN(x)      (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_SW_RF_ACTIVE_EN_SHIFT)) & RSIM_DSM_CONTROL_SW_RF_ACTIVE_EN_MASK)
+#define RSIM_DSM_CONTROL_DSM_TIMER_CLR_MASK      (0x8000000U)
+#define RSIM_DSM_CONTROL_DSM_TIMER_CLR_SHIFT     (27U)
+#define RSIM_DSM_CONTROL_DSM_TIMER_CLR(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_TIMER_CLR_SHIFT)) & RSIM_DSM_CONTROL_DSM_TIMER_CLR_MASK)
+#define RSIM_DSM_CONTROL_DSM_TIMER_EN_MASK       (0x80000000U)
+#define RSIM_DSM_CONTROL_DSM_TIMER_EN_SHIFT      (31U)
+#define RSIM_DSM_CONTROL_DSM_TIMER_EN(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_TIMER_EN_SHIFT)) & RSIM_DSM_CONTROL_DSM_TIMER_EN_MASK)
+/*! @} */
+
+/*! @name DSM_WAKEUP - Deep Sleep Wakeup Sequence */
+/*! @{ */
+#define RSIM_DSM_WAKEUP_DSM_POWER_OFFSET_TIME_MASK (0x3FFU)
+#define RSIM_DSM_WAKEUP_DSM_POWER_OFFSET_TIME_SHIFT (0U)
+#define RSIM_DSM_WAKEUP_DSM_POWER_OFFSET_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_WAKEUP_DSM_POWER_OFFSET_TIME_SHIFT)) & RSIM_DSM_WAKEUP_DSM_POWER_OFFSET_TIME_MASK)
+#define RSIM_DSM_WAKEUP_ACTIVE_WARNING_MASK      (0x3F000U)
+#define RSIM_DSM_WAKEUP_ACTIVE_WARNING_SHIFT     (12U)
+#define RSIM_DSM_WAKEUP_ACTIVE_WARNING(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_WAKEUP_ACTIVE_WARNING_SHIFT)) & RSIM_DSM_WAKEUP_ACTIVE_WARNING_MASK)
+#define RSIM_DSM_WAKEUP_FINE_DELAY_MASK          (0x3F00000U)
+#define RSIM_DSM_WAKEUP_FINE_DELAY_SHIFT         (20U)
+#define RSIM_DSM_WAKEUP_FINE_DELAY(x)            (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_WAKEUP_FINE_DELAY_SHIFT)) & RSIM_DSM_WAKEUP_FINE_DELAY_MASK)
+#define RSIM_DSM_WAKEUP_COARSE_DELAY_MASK        (0xF0000000U)
+#define RSIM_DSM_WAKEUP_COARSE_DELAY_SHIFT       (28U)
+#define RSIM_DSM_WAKEUP_COARSE_DELAY(x)          (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_WAKEUP_COARSE_DELAY_SHIFT)) & RSIM_DSM_WAKEUP_COARSE_DELAY_MASK)
+/*! @} */
+
+/*! @name WOR_DURATION - WOR Deep Sleep Duration */
+/*! @{ */
+#define RSIM_WOR_DURATION_WOR_DSM_DURATION_MASK  (0xFFFFFFU)
+#define RSIM_WOR_DURATION_WOR_DSM_DURATION_SHIFT (0U)
+#define RSIM_WOR_DURATION_WOR_DSM_DURATION(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_WOR_DURATION_WOR_DSM_DURATION_SHIFT)) & RSIM_WOR_DURATION_WOR_DSM_DURATION_MASK)
+/*! @} */
+
+/*! @name WOR_WAKE - WOR Deep Sleep Wake Time */
+/*! @{ */
+#define RSIM_WOR_WAKE_WOR_WAKE_TIME_MASK         (0xFFFFFFU)
+#define RSIM_WOR_WAKE_WOR_WAKE_TIME_SHIFT        (0U)
+#define RSIM_WOR_WAKE_WOR_WAKE_TIME(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_WOR_WAKE_WOR_WAKE_TIME_SHIFT)) & RSIM_WOR_WAKE_WOR_WAKE_TIME_MASK)
+#define RSIM_WOR_WAKE_WOR_FSM_STATE_MASK         (0x70000000U)
+#define RSIM_WOR_WAKE_WOR_FSM_STATE_SHIFT        (28U)
+#define RSIM_WOR_WAKE_WOR_FSM_STATE(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_WOR_WAKE_WOR_FSM_STATE_SHIFT)) & RSIM_WOR_WAKE_WOR_FSM_STATE_MASK)
+/*! @} */
+
+/*! @name MAN_SLEEP - MAN Deep Sleep Time */
+/*! @{ */
+#define RSIM_MAN_SLEEP_MAN_SLEEP_TIME_MASK       (0xFFFFFFU)
+#define RSIM_MAN_SLEEP_MAN_SLEEP_TIME_SHIFT      (0U)
+#define RSIM_MAN_SLEEP_MAN_SLEEP_TIME(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_MAN_SLEEP_MAN_SLEEP_TIME_SHIFT)) & RSIM_MAN_SLEEP_MAN_SLEEP_TIME_MASK)
+/*! @} */
+
+/*! @name MAN_WAKE - MAN Deep Sleep Wake Time */
+/*! @{ */
+#define RSIM_MAN_WAKE_MAN_WAKE_TIME_MASK         (0xFFFFFFU)
+#define RSIM_MAN_WAKE_MAN_WAKE_TIME_SHIFT        (0U)
+#define RSIM_MAN_WAKE_MAN_WAKE_TIME(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_MAN_WAKE_MAN_WAKE_TIME_SHIFT)) & RSIM_MAN_WAKE_MAN_WAKE_TIME_MASK)
+#define RSIM_MAN_WAKE_MAN_FSM_STATE_MASK         (0x70000000U)
+#define RSIM_MAN_WAKE_MAN_FSM_STATE_SHIFT        (28U)
+#define RSIM_MAN_WAKE_MAN_FSM_STATE(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_MAN_WAKE_MAN_FSM_STATE_SHIFT)) & RSIM_MAN_WAKE_MAN_FSM_STATE_MASK)
+/*! @} */
+
+/*! @name RF_OSC_CTRL - Radio Oscillator Control */
+/*! @{ */
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_MASK (0x3U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_SHIFT (0U)
+/*! BB_XTAL_ALC_COUNT_SEL - rmap_bb_xtal_alc_count_sel_hv[1:0]
+ *  0b00..2048 (64 us @ 32 MHz)
+ *  0b01..4096 (128 us @ 32 MHz)
+ *  0b10..8192 (256 us @ 32 MHz)
+ *  0b11..16384 (512 us @ 32 MHz)
+ */
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_MASK)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_MASK     (0x4U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_SHIFT    (2U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_MASK)
+#define RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_MASK   (0x8U)
+#define RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_SHIFT  (3U)
+#define RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN(x)     (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_SHIFT)) & RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_MASK)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_MASK  (0x1F0U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_SHIFT (4U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_MASK)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_MASK (0x200U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_SHIFT (9U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_MASK)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_MASK    (0x400U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_SHIFT   (10U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL(x)      (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_MASK)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_MASK (0x800U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_SHIFT (11U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON(x)   (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_MASK)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_GM_MASK         (0x1F000U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_GM_SHIFT        (12U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_GM(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_GM_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_GM_MASK)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_MASK    (0x20000U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_SHIFT   (17U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD(x)      (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_MASK)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_MASK (0x40000U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_SHIFT (18U)
+/*! BB_XTAL_ON_OVRD_ON - rmap_bb_xtal_on_ovrd_on_hv
+ *  0b0..rfctrl_bb_xtal_on_hv is asserted
+ *  0b1..rfctrl_bb_xtal_on_ovrd_hv is asserted
+ */
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON(x)   (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_MASK)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_MASK (0x300000U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_SHIFT (20U)
+/*! BB_XTAL_READY_COUNT_SEL - rmap_bb_xtal_ready_count_sel_hv[1:0]
+ *  0b00..1024 counts (32 us @ 32 MHz)
+ *  0b01..2048 (64 us @ 32 MHz)
+ *  0b10..4096 (128 us @ 32 MHz)
+ *  0b11..8192 (256 us @ 32 MHz)
+ */
+#define RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_MASK)
+#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_MASK (0x8000000U)
+#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_SHIFT (27U)
+#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_MASK)
+#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK (0x10000000U)
+#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_SHIFT (28U)
+#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD(x)   (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK)
+#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK (0x20000000U)
+#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_SHIFT (29U)
+#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK)
+#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_MASK (0x40000000U)
+#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_SHIFT (30U)
+#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD(x)  (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_SHIFT)) & RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_MASK)
+#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_EN_MASK (0x80000000U)
+#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_EN_SHIFT (31U)
+#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_EN_SHIFT)) & RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_EN_MASK)
+/*! @} */
+
+/*! @name ANA_TEST - Radio Analog Test Registers */
+/*! @{ */
+#define RSIM_ANA_TEST_XTAL_OUT_BUF_EN_MASK       (0x10U)
+#define RSIM_ANA_TEST_XTAL_OUT_BUF_EN_SHIFT      (4U)
+#define RSIM_ANA_TEST_XTAL_OUT_BUF_EN(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_XTAL_OUT_BUF_EN_SHIFT)) & RSIM_ANA_TEST_XTAL_OUT_BUF_EN_MASK)
+/*! @} */
+
+/*! @name ANA_TRIM - Radio Analog Trim Registers */
+/*! @{ */
+#define RSIM_ANA_TRIM_BB_LDO_LS_SPARE_MASK       (0x3U)
+#define RSIM_ANA_TRIM_BB_LDO_LS_SPARE_SHIFT      (0U)
+#define RSIM_ANA_TRIM_BB_LDO_LS_SPARE(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_LS_SPARE_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_LS_SPARE_MASK)
+#define RSIM_ANA_TRIM_BB_LDO_LS_TRIM_MASK        (0x38U)
+#define RSIM_ANA_TRIM_BB_LDO_LS_TRIM_SHIFT       (3U)
+/*! BB_LDO_LS_TRIM - rmap_bb_ldo_ls_trim_hv[2:0]
+ *  0b000..1.20 V (Default)
+ *  0b001..1.25 V
+ *  0b010..1.28 V
+ *  0b011..1.33 V
+ *  0b100..1.40 V
+ *  0b101..1.44 V
+ *  0b110..1.50 V
+ *  0b111..1.66 V
+ */
+#define RSIM_ANA_TRIM_BB_LDO_LS_TRIM(x)          (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_LS_TRIM_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_LS_TRIM_MASK)
+#define RSIM_ANA_TRIM_BB_LDO_XO_SPARE_MASK       (0xC0U)
+#define RSIM_ANA_TRIM_BB_LDO_XO_SPARE_SHIFT      (6U)
+#define RSIM_ANA_TRIM_BB_LDO_XO_SPARE(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_XO_SPARE_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_XO_SPARE_MASK)
+#define RSIM_ANA_TRIM_BB_LDO_XO_TRIM_MASK        (0x700U)
+#define RSIM_ANA_TRIM_BB_LDO_XO_TRIM_SHIFT       (8U)
+/*! BB_LDO_XO_TRIM - rmap_bb_ldo_xo_trim_hv[2:0]
+ *  0b000..1.20 V (Default)
+ *  0b001..1.25 V
+ *  0b010..1.28 V
+ *  0b011..1.33 V
+ *  0b100..1.40 V
+ *  0b101..1.44 V
+ *  0b110..1.50 V
+ *  0b111..1.66 V
+ */
+#define RSIM_ANA_TRIM_BB_LDO_XO_TRIM(x)          (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_XO_TRIM_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_XO_TRIM_MASK)
+#define RSIM_ANA_TRIM_BB_XTAL_SPARE_MASK         (0xF800U)
+#define RSIM_ANA_TRIM_BB_XTAL_SPARE_SHIFT        (11U)
+#define RSIM_ANA_TRIM_BB_XTAL_SPARE(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_XTAL_SPARE_SHIFT)) & RSIM_ANA_TRIM_BB_XTAL_SPARE_MASK)
+#define RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK          (0xFF0000U)
+#define RSIM_ANA_TRIM_BB_XTAL_TRIM_SHIFT         (16U)
+#define RSIM_ANA_TRIM_BB_XTAL_TRIM(x)            (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_XTAL_TRIM_SHIFT)) & RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK)
+#define RSIM_ANA_TRIM_BG_1V_TRIM_MASK            (0xF000000U)
+#define RSIM_ANA_TRIM_BG_1V_TRIM_SHIFT           (24U)
+/*! BG_1V_TRIM - rmap_bg_1v_trim_hv[3:0]
+ *  0b0000..954.14 mV
+ *  0b0001..959.26 mV
+ *  0b0010..964.38 mV
+ *  0b0011..969.5 mV
+ *  0b0100..974.6 mV
+ *  0b0101..979.7 mV
+ *  0b0110..984.8 mV
+ *  0b0111..989.9 mV
+ *  0b1000..995 mV (Default)
+ *  0b1001..1 V
+ *  0b1010..1.005 V
+ *  0b1011..1.01 V
+ *  0b1100..1.015 V
+ *  0b1101..1.02 V
+ *  0b1110..1.025 V
+ *  0b1111..1.031 V
+ */
+#define RSIM_ANA_TRIM_BG_1V_TRIM(x)              (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BG_1V_TRIM_SHIFT)) & RSIM_ANA_TRIM_BG_1V_TRIM_MASK)
+#define RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_MASK      (0xF0000000U)
+#define RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_SHIFT     (28U)
+/*! BG_IBIAS_5U_TRIM - rmap_bg_ibias_5u_trim_hv[3:0]
+ *  0b0000..3.55 uA
+ *  0b0001..3.73 uA
+ *  0b0010..4.04 uA
+ *  0b0011..4.22 uA
+ *  0b0100..4.39 uA
+ *  0b0101..4.57 uA
+ *  0b0110..4.89 uA
+ *  0b0111..5.06 (Default)
+ *  0b1000..5.23 uA
+ *  0b1001..5.41 uA
+ *  0b1010..5.72 uA
+ *  0b1011..5.9 uA
+ *  0b1100..6.07 uA
+ *  0b1101..6.25 uA
+ *  0b1110..6.56 uA
+ *  0b1111..6.74 uA
+ */
+#define RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_SHIFT)) & RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group RSIM_Register_Masks */
+
+
+/* RSIM - Peripheral instance base addresses */
+/** Peripheral RSIM base address */
+#define RSIM_BASE                                (0x4102F000u)
+/** Peripheral RSIM base pointer */
+#define RSIM                                     ((RSIM_Type *)RSIM_BASE)
+/** Array initializer of RSIM peripheral base addresses */
+#define RSIM_BASE_ADDRS                          { RSIM_BASE }
+/** Array initializer of RSIM peripheral base pointers */
+#define RSIM_BASE_PTRS                           { RSIM }
+
+/*!
+ * @}
+ */ /* end of group RSIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TSR;                               /**< RTC Time Seconds Register, offset: 0x0 */
+  __IO uint32_t TPR;                               /**< RTC Time Prescaler Register, offset: 0x4 */
+  __IO uint32_t TAR;                               /**< RTC Time Alarm Register, offset: 0x8 */
+  __IO uint32_t TCR;                               /**< RTC Time Compensation Register, offset: 0xC */
+  __IO uint32_t CR;                                /**< RTC Control Register, offset: 0x10 */
+  __IO uint32_t SR;                                /**< RTC Status Register, offset: 0x14 */
+  __IO uint32_t LR;                                /**< RTC Lock Register, offset: 0x18 */
+  __IO uint32_t IER;                               /**< RTC Interrupt Enable Register, offset: 0x1C */
+  __I  uint32_t TTSR;                              /**< RTC Tamper Time Seconds Register, offset: 0x20 */
+  __IO uint32_t MER;                               /**< RTC Monotonic Enable Register, offset: 0x24 */
+  __IO uint32_t MCLR;                              /**< RTC Monotonic Counter Low Register, offset: 0x28 */
+  __IO uint32_t MCHR;                              /**< RTC Monotonic Counter High Register, offset: 0x2C */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TDR;                               /**< RTC Tamper Detect Register, offset: 0x34 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t TIR;                               /**< RTC Tamper Interrupt Register, offset: 0x3C */
+  __IO uint32_t PCR[4];                            /**< RTC Pin Configuration Register, array offset: 0x40, array step: 0x4 */
+       uint8_t RESERVED_2[1968];
+  __IO uint32_t WAR;                               /**< RTC Write Access Register, offset: 0x800 */
+  __IO uint32_t RAR;                               /**< RTC Read Access Register, offset: 0x804 */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/*! @name TSR - RTC Time Seconds Register */
+/*! @{ */
+#define RTC_TSR_TSR_MASK                         (0xFFFFFFFFU)
+#define RTC_TSR_TSR_SHIFT                        (0U)
+#define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
+/*! @} */
+
+/*! @name TPR - RTC Time Prescaler Register */
+/*! @{ */
+#define RTC_TPR_TPR_MASK                         (0xFFFFU)
+#define RTC_TPR_TPR_SHIFT                        (0U)
+#define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
+/*! @} */
+
+/*! @name TAR - RTC Time Alarm Register */
+/*! @{ */
+#define RTC_TAR_TAR_MASK                         (0xFFFFFFFFU)
+#define RTC_TAR_TAR_SHIFT                        (0U)
+#define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
+/*! @} */
+
+/*! @name TCR - RTC Time Compensation Register */
+/*! @{ */
+#define RTC_TCR_TCR_MASK                         (0xFFU)
+#define RTC_TCR_TCR_SHIFT                        (0U)
+/*! TCR - Time Compensation Register
+ *  0b10000000..Time Prescaler Register overflows every 32896 clock cycles.
+ *  0b10000001..Time Prescaler Register overflows every 32895 clock cycles.
+ *  0b11111111..Time Prescaler Register overflows every 32769 clock cycles.
+ *  0b00000000..Time Prescaler Register overflows every 32768 clock cycles.
+ *  0b00000001..Time Prescaler Register overflows every 32767 clock cycles.
+ *  0b01111110..Time Prescaler Register overflows every 32642 clock cycles.
+ *  0b01111111..Time Prescaler Register overflows every 32641 clock cycles.
+ */
+#define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK                         (0xFF00U)
+#define RTC_TCR_CIR_SHIFT                        (8U)
+#define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK                         (0xFF0000U)
+#define RTC_TCR_TCV_SHIFT                        (16U)
+#define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK                         (0xFF000000U)
+#define RTC_TCR_CIC_SHIFT                        (24U)
+#define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
+/*! @} */
+
+/*! @name CR - RTC Control Register */
+/*! @{ */
+#define RTC_CR_SWR_MASK                          (0x1U)
+#define RTC_CR_SWR_SHIFT                         (0U)
+/*! SWR - Software Reset
+ *  0b0..No effect.
+ *  0b1..Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software explicitly clearing it.
+ */
+#define RTC_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
+#define RTC_CR_WPE_MASK                          (0x2U)
+#define RTC_CR_WPE_SHIFT                         (1U)
+/*! WPE - Wakeup Pin Enable
+ *  0b0..RTC_WAKEUP pin is disabled.
+ *  0b1..RTC_WAKEUP pin is enabled and asserts if the RTC interrupt asserts or if the wakeup pin is forced on.
+ */
+#define RTC_CR_WPE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
+#define RTC_CR_SUP_MASK                          (0x4U)
+#define RTC_CR_SUP_SHIFT                         (2U)
+/*! SUP - Supervisor Access
+ *  0b0..Non-supervisor mode write accesses are not supported and generate a bus error.
+ *  0b1..Non-supervisor mode write accesses are supported.
+ */
+#define RTC_CR_SUP(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
+#define RTC_CR_UM_MASK                           (0x8U)
+#define RTC_CR_UM_SHIFT                          (3U)
+/*! UM - Update Mode
+ *  0b0..Registers cannot be written when locked.
+ *  0b1..Registers can be written when locked under limited conditions.
+ */
+#define RTC_CR_UM(x)                             (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
+#define RTC_CR_WPS_MASK                          (0x10U)
+#define RTC_CR_WPS_SHIFT                         (4U)
+/*! WPS - Wakeup Pin Select
+ *  0b0..RTC_WAKEUP pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on.
+ *  0b1..RTC_WAKEUP pin outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals.
+ */
+#define RTC_CR_WPS(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
+#define RTC_CR_CPS_MASK                          (0x20U)
+#define RTC_CR_CPS_SHIFT                         (5U)
+/*! CPS - Clock Pin Select
+ *  0b0..The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT.
+ *  0b1..The RTC 32.768 kHz clock is output on RTC_CLKOUT, provided it is output to other peripherals.
+ */
+#define RTC_CR_CPS(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_CPS_SHIFT)) & RTC_CR_CPS_MASK)
+#define RTC_CR_LPOS_MASK                         (0x80U)
+#define RTC_CR_LPOS_SHIFT                        (7U)
+/*! LPOS - LPO Select
+ *  0b0..RTC prescaler increments using 32.768 kHz clock.
+ *  0b1..RTC prescaler increments using 1 kHz LPO, bits [4:0] of the prescaler are ignored.
+ */
+#define RTC_CR_LPOS(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_LPOS_SHIFT)) & RTC_CR_LPOS_MASK)
+#define RTC_CR_OSCE_MASK                         (0x100U)
+#define RTC_CR_OSCE_SHIFT                        (8U)
+/*! OSCE - Oscillator Enable
+ *  0b0..32.768 kHz oscillator is disabled.
+ *  0b1..32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.
+ */
+#define RTC_CR_OSCE(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
+#define RTC_CR_CLKO_MASK                         (0x200U)
+#define RTC_CR_CLKO_SHIFT                        (9U)
+/*! CLKO - Clock Output
+ *  0b0..The 32 kHz clock is output to other peripherals.
+ *  0b1..The 32 kHz clock is not output to other peripherals.
+ */
+#define RTC_CR_CLKO(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
+#define RTC_CR_SC16P_MASK                        (0x400U)
+#define RTC_CR_SC16P_SHIFT                       (10U)
+/*! SC16P - Oscillator 16pF Load Configure
+ *  0b0..Disable the load.
+ *  0b1..Enable the additional load.
+ */
+#define RTC_CR_SC16P(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
+#define RTC_CR_SC8P_MASK                         (0x800U)
+#define RTC_CR_SC8P_SHIFT                        (11U)
+/*! SC8P - Oscillator 8pF Load Configure
+ *  0b0..Disable the load.
+ *  0b1..Enable the additional load.
+ */
+#define RTC_CR_SC8P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
+#define RTC_CR_SC4P_MASK                         (0x1000U)
+#define RTC_CR_SC4P_SHIFT                        (12U)
+/*! SC4P - Oscillator 4pF Load Configure
+ *  0b0..Disable the load.
+ *  0b1..Enable the additional load.
+ */
+#define RTC_CR_SC4P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
+#define RTC_CR_SC2P_MASK                         (0x2000U)
+#define RTC_CR_SC2P_SHIFT                        (13U)
+/*! SC2P - Oscillator 2pF Load Configure
+ *  0b0..Disable the load.
+ *  0b1..Enable the additional load.
+ */
+#define RTC_CR_SC2P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
+#define RTC_CR_OSCM_MASK                         (0x8000U)
+#define RTC_CR_OSCM_SHIFT                        (15U)
+/*! OSCM - Oscillator Mode Select
+ *  0b0..Configures the 32.768kHz crystal oscillator for robust operation supporting a wide range of crystals.
+ *  0b1..Configures the 32.768kHz crystal oscillator for low power operation supporting a more limited range of crystals.
+ */
+#define RTC_CR_OSCM(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCM_SHIFT)) & RTC_CR_OSCM_MASK)
+#define RTC_CR_PORS_MASK                         (0x30000U)
+#define RTC_CR_PORS_SHIFT                        (16U)
+/*! PORS - POR Select
+ *  0b00..POR brownout enabled for 120us every 128ms.
+ *  0b01..POR brownout enabled for 120us every 64ms.
+ *  0b10..POR brownout enabled for 120us every 32ms.
+ *  0b11..POR brownout always enabled.
+ */
+#define RTC_CR_PORS(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_PORS_SHIFT)) & RTC_CR_PORS_MASK)
+#define RTC_CR_CPE_MASK                          (0x3000000U)
+#define RTC_CR_CPE_SHIFT                         (24U)
+/*! CPE - Clock Pin Enable
+ *  0b00..The RTC_CLKOUT function is disabled.
+ *  0b01..Enable RTC_CLKOUT pin on pin 1.
+ *  0b10..Enable RTC_CLKOUT pin on pin 2.
+ *  0b11..Enable RTC_CLKOUT pin on pin 3.
+ */
+#define RTC_CR_CPE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_CPE_SHIFT)) & RTC_CR_CPE_MASK)
+/*! @} */
+
+/*! @name SR - RTC Status Register */
+/*! @{ */
+#define RTC_SR_TIF_MASK                          (0x1U)
+#define RTC_SR_TIF_SHIFT                         (0U)
+/*! TIF - Time Invalid Flag
+ *  0b0..Time is valid.
+ *  0b1..Time is invalid and time counter is read as zero.
+ */
+#define RTC_SR_TIF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
+#define RTC_SR_TOF_MASK                          (0x2U)
+#define RTC_SR_TOF_SHIFT                         (1U)
+/*! TOF - Time Overflow Flag
+ *  0b0..Time overflow has not occurred.
+ *  0b1..Time overflow has occurred and time counter is read as zero.
+ */
+#define RTC_SR_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
+#define RTC_SR_TAF_MASK                          (0x4U)
+#define RTC_SR_TAF_SHIFT                         (2U)
+/*! TAF - Time Alarm Flag
+ *  0b0..Time alarm has not occurred.
+ *  0b1..Time alarm has occurred.
+ */
+#define RTC_SR_TAF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
+#define RTC_SR_MOF_MASK                          (0x8U)
+#define RTC_SR_MOF_SHIFT                         (3U)
+/*! MOF - Monotonic Overflow Flag
+ *  0b0..Monotonic counter overflow has not occurred.
+ *  0b1..Monotonic counter overflow has occurred and monotonic counter is read as zero.
+ */
+#define RTC_SR_MOF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_MOF_SHIFT)) & RTC_SR_MOF_MASK)
+#define RTC_SR_TCE_MASK                          (0x10U)
+#define RTC_SR_TCE_SHIFT                         (4U)
+/*! TCE - Time Counter Enable
+ *  0b0..Time counter is disabled.
+ *  0b1..Time counter is enabled.
+ */
+#define RTC_SR_TCE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
+#define RTC_SR_TIDF_MASK                         (0x80U)
+#define RTC_SR_TIDF_SHIFT                        (7U)
+/*! TIDF - Tamper Interrupt Detect Flag
+ *  0b0..Tamper interrupt has not asserted.
+ *  0b1..Tamper interrupt has asserted.
+ */
+#define RTC_SR_TIDF(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIDF_SHIFT)) & RTC_SR_TIDF_MASK)
+/*! @} */
+
+/*! @name LR - RTC Lock Register */
+/*! @{ */
+#define RTC_LR_TCL_MASK                          (0x8U)
+#define RTC_LR_TCL_SHIFT                         (3U)
+/*! TCL - Time Compensation Lock
+ *  0b0..Time Compensation Register is locked and writes are ignored.
+ *  0b1..Time Compensation Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_TCL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
+#define RTC_LR_CRL_MASK                          (0x10U)
+#define RTC_LR_CRL_SHIFT                         (4U)
+/*! CRL - Control Register Lock
+ *  0b0..Control Register is locked and writes are ignored.
+ *  0b1..Control Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_CRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
+#define RTC_LR_SRL_MASK                          (0x20U)
+#define RTC_LR_SRL_SHIFT                         (5U)
+/*! SRL - Status Register Lock
+ *  0b0..Status Register is locked and writes are ignored.
+ *  0b1..Status Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_SRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
+#define RTC_LR_LRL_MASK                          (0x40U)
+#define RTC_LR_LRL_SHIFT                         (6U)
+/*! LRL - Lock Register Lock
+ *  0b0..Lock Register is locked and writes are ignored.
+ *  0b1..Lock Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_LRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
+#define RTC_LR_TTSL_MASK                         (0x100U)
+#define RTC_LR_TTSL_SHIFT                        (8U)
+/*! TTSL - Tamper Time Seconds Lock
+ *  0b0..Tamper Time Seconds Register is locked and writes are ignored.
+ *  0b1..Tamper Time Seconds Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_TTSL(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_LR_TTSL_SHIFT)) & RTC_LR_TTSL_MASK)
+#define RTC_LR_MEL_MASK                          (0x200U)
+#define RTC_LR_MEL_SHIFT                         (9U)
+/*! MEL - Monotonic Enable Lock
+ *  0b0..Monotonic Enable Register is locked and writes are ignored.
+ *  0b1..Monotonic Enable Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_MEL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_MEL_SHIFT)) & RTC_LR_MEL_MASK)
+#define RTC_LR_MCLL_MASK                         (0x400U)
+#define RTC_LR_MCLL_SHIFT                        (10U)
+/*! MCLL - Monotonic Counter Low Lock
+ *  0b0..Monotonic Counter Low Register is locked and writes are ignored.
+ *  0b1..Monotonic Counter Low Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_MCLL(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCLL_SHIFT)) & RTC_LR_MCLL_MASK)
+#define RTC_LR_MCHL_MASK                         (0x800U)
+#define RTC_LR_MCHL_SHIFT                        (11U)
+/*! MCHL - Monotonic Counter High Lock
+ *  0b0..Monotonic Counter High Register is locked and writes are ignored.
+ *  0b1..Monotonic Counter High Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_MCHL(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCHL_SHIFT)) & RTC_LR_MCHL_MASK)
+#define RTC_LR_TDL_MASK                          (0x2000U)
+#define RTC_LR_TDL_SHIFT                         (13U)
+/*! TDL - Tamper Detect Lock
+ *  0b0..Tamper Detect Register is locked and writes are ignored.
+ *  0b1..Tamper Detect Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_TDL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_TDL_SHIFT)) & RTC_LR_TDL_MASK)
+#define RTC_LR_TIL_MASK                          (0x8000U)
+#define RTC_LR_TIL_SHIFT                         (15U)
+/*! TIL - Tamper Interrupt Lock
+ *  0b0..Tamper Interrupt Register is locked and writes are ignored.
+ *  0b1..Tamper Interrupt Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_TIL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_TIL_SHIFT)) & RTC_LR_TIL_MASK)
+#define RTC_LR_PCL_MASK                          (0xF0000U)
+#define RTC_LR_PCL_SHIFT                         (16U)
+#define RTC_LR_PCL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_PCL_SHIFT)) & RTC_LR_PCL_MASK)
+/*! @} */
+
+/*! @name IER - RTC Interrupt Enable Register */
+/*! @{ */
+#define RTC_IER_TIIE_MASK                        (0x1U)
+#define RTC_IER_TIIE_SHIFT                       (0U)
+/*! TIIE - Time Invalid Interrupt Enable
+ *  0b0..Time invalid flag does not generate an interrupt.
+ *  0b1..Time invalid flag does generate an interrupt.
+ */
+#define RTC_IER_TIIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
+#define RTC_IER_TOIE_MASK                        (0x2U)
+#define RTC_IER_TOIE_SHIFT                       (1U)
+/*! TOIE - Time Overflow Interrupt Enable
+ *  0b0..Time overflow flag does not generate an interrupt.
+ *  0b1..Time overflow flag does generate an interrupt.
+ */
+#define RTC_IER_TOIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
+#define RTC_IER_TAIE_MASK                        (0x4U)
+#define RTC_IER_TAIE_SHIFT                       (2U)
+/*! TAIE - Time Alarm Interrupt Enable
+ *  0b0..Time alarm flag does not generate an interrupt.
+ *  0b1..Time alarm flag does generate an interrupt.
+ */
+#define RTC_IER_TAIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
+#define RTC_IER_MOIE_MASK                        (0x8U)
+#define RTC_IER_MOIE_SHIFT                       (3U)
+/*! MOIE - Monotonic Overflow Interrupt Enable
+ *  0b0..Monotonic overflow flag does not generate an interrupt.
+ *  0b1..Monotonic overflow flag does generate an interrupt.
+ */
+#define RTC_IER_MOIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_MOIE_SHIFT)) & RTC_IER_MOIE_MASK)
+#define RTC_IER_TSIE_MASK                        (0x10U)
+#define RTC_IER_TSIE_SHIFT                       (4U)
+/*! TSIE - Time Seconds Interrupt Enable
+ *  0b0..Seconds interrupt is disabled.
+ *  0b1..Seconds interrupt is enabled.
+ */
+#define RTC_IER_TSIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
+#define RTC_IER_WPON_MASK                        (0x80U)
+#define RTC_IER_WPON_SHIFT                       (7U)
+/*! WPON - Wakeup Pin On
+ *  0b0..No effect.
+ *  0b1..If the RTC_WAKEUP pin is enabled, then the pin will assert.
+ */
+#define RTC_IER_WPON(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
+#define RTC_IER_TSIC_MASK                        (0x70000U)
+#define RTC_IER_TSIC_SHIFT                       (16U)
+/*! TSIC - Timer Seconds Interrupt Configuration
+ *  0b000..1 Hz.
+ *  0b001..2 Hz.
+ *  0b010..4 Hz.
+ *  0b011..8 Hz.
+ *  0b100..16 Hz.
+ *  0b101..32 Hz.
+ *  0b110..64 Hz.
+ *  0b111..128 Hz.
+ */
+#define RTC_IER_TSIC(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIC_SHIFT)) & RTC_IER_TSIC_MASK)
+/*! @} */
+
+/*! @name TTSR - RTC Tamper Time Seconds Register */
+/*! @{ */
+#define RTC_TTSR_TTS_MASK                        (0xFFFFFFFFU)
+#define RTC_TTSR_TTS_SHIFT                       (0U)
+#define RTC_TTSR_TTS(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_TTSR_TTS_SHIFT)) & RTC_TTSR_TTS_MASK)
+/*! @} */
+
+/*! @name MER - RTC Monotonic Enable Register */
+/*! @{ */
+#define RTC_MER_MCE_MASK                         (0x10U)
+#define RTC_MER_MCE_SHIFT                        (4U)
+/*! MCE - Monotonic Counter Enable
+ *  0b0..Writes to the monotonic counter load the counter with the value written.
+ *  0b1..Writes to the monotonic counter increment the counter.
+ */
+#define RTC_MER_MCE(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_MER_MCE_SHIFT)) & RTC_MER_MCE_MASK)
+/*! @} */
+
+/*! @name MCLR - RTC Monotonic Counter Low Register */
+/*! @{ */
+#define RTC_MCLR_MCL_MASK                        (0xFFFFFFFFU)
+#define RTC_MCLR_MCL_SHIFT                       (0U)
+#define RTC_MCLR_MCL(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_MCLR_MCL_SHIFT)) & RTC_MCLR_MCL_MASK)
+/*! @} */
+
+/*! @name MCHR - RTC Monotonic Counter High Register */
+/*! @{ */
+#define RTC_MCHR_MCH_MASK                        (0xFFFFFFFFU)
+#define RTC_MCHR_MCH_SHIFT                       (0U)
+#define RTC_MCHR_MCH(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_MCHR_MCH_SHIFT)) & RTC_MCHR_MCH_MASK)
+/*! @} */
+
+/*! @name TDR - RTC Tamper Detect Register */
+/*! @{ */
+#define RTC_TDR_LCTF_MASK                        (0x10U)
+#define RTC_TDR_LCTF_SHIFT                       (4U)
+/*! LCTF - Loss of Clock Tamper Flag
+ *  0b0..Tamper not detected.
+ *  0b1..Loss of Clock tamper detected.
+ */
+#define RTC_TDR_LCTF(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_TDR_LCTF_SHIFT)) & RTC_TDR_LCTF_MASK)
+#define RTC_TDR_STF_MASK                         (0x20U)
+#define RTC_TDR_STF_SHIFT                        (5U)
+/*! STF - Security Tamper Flag
+ *  0b0..Tamper not detected.
+ *  0b1..Security module tamper detected.
+ */
+#define RTC_TDR_STF(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TDR_STF_SHIFT)) & RTC_TDR_STF_MASK)
+#define RTC_TDR_FSF_MASK                         (0x40U)
+#define RTC_TDR_FSF_SHIFT                        (6U)
+/*! FSF - Flash Security Flag
+ *  0b0..Tamper not detected.
+ *  0b1..Flash security tamper detected.
+ */
+#define RTC_TDR_FSF(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TDR_FSF_SHIFT)) & RTC_TDR_FSF_MASK)
+#define RTC_TDR_TMF_MASK                         (0x80U)
+#define RTC_TDR_TMF_SHIFT                        (7U)
+/*! TMF - Test Mode Flag
+ *  0b0..Tamper not detected.
+ *  0b1..Test mode tamper detected.
+ */
+#define RTC_TDR_TMF(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TDR_TMF_SHIFT)) & RTC_TDR_TMF_MASK)
+#define RTC_TDR_TPF_MASK                         (0xF0000U)
+#define RTC_TDR_TPF_SHIFT                        (16U)
+#define RTC_TDR_TPF(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TDR_TPF_SHIFT)) & RTC_TDR_TPF_MASK)
+/*! @} */
+
+/*! @name TIR - RTC Tamper Interrupt Register */
+/*! @{ */
+#define RTC_TIR_LCIE_MASK                        (0x10U)
+#define RTC_TIR_LCIE_SHIFT                       (4U)
+/*! LCIE - Loss of Clock Interrupt Enable
+ *  0b0..Interupt disabled.
+ *  0b1..An interrupt is generated when the loss of clock flag is set.
+ */
+#define RTC_TIR_LCIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_TIR_LCIE_SHIFT)) & RTC_TIR_LCIE_MASK)
+#define RTC_TIR_SIE_MASK                         (0x20U)
+#define RTC_TIR_SIE_SHIFT                        (5U)
+/*! SIE - Security Module Interrupt Enable
+ *  0b0..Interupt disabled.
+ *  0b1..An interrupt is generated when the security module flag is set.
+ */
+#define RTC_TIR_SIE(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TIR_SIE_SHIFT)) & RTC_TIR_SIE_MASK)
+#define RTC_TIR_FSIE_MASK                        (0x40U)
+#define RTC_TIR_FSIE_SHIFT                       (6U)
+/*! FSIE - Flash Security Interrupt Enable
+ *  0b0..Interupt disabled.
+ *  0b1..An interrupt is generated when the flash security flag is set.
+ */
+#define RTC_TIR_FSIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_TIR_FSIE_SHIFT)) & RTC_TIR_FSIE_MASK)
+#define RTC_TIR_TMIE_MASK                        (0x80U)
+#define RTC_TIR_TMIE_SHIFT                       (7U)
+/*! TMIE - Test Mode Interrupt Enable
+ *  0b0..Interupt disabled.
+ *  0b1..An interrupt is generated when the test mode flag is set.
+ */
+#define RTC_TIR_TMIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_TIR_TMIE_SHIFT)) & RTC_TIR_TMIE_MASK)
+#define RTC_TIR_TPIE_MASK                        (0xF0000U)
+#define RTC_TIR_TPIE_SHIFT                       (16U)
+#define RTC_TIR_TPIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_TIR_TPIE_SHIFT)) & RTC_TIR_TPIE_MASK)
+/*! @} */
+
+/*! @name PCR - RTC Pin Configuration Register */
+/*! @{ */
+#define RTC_PCR_TPE_MASK                         (0x1000000U)
+#define RTC_PCR_TPE_SHIFT                        (24U)
+/*! TPE - Tamper Pull Enable
+ *  0b0..Pull resistor is disabled on tamper pin.
+ *  0b1..Pull resistor is enabled on tamper pin.
+ */
+#define RTC_PCR_TPE(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TPE_SHIFT)) & RTC_PCR_TPE_MASK)
+#define RTC_PCR_TPS_MASK                         (0x2000000U)
+#define RTC_PCR_TPS_SHIFT                        (25U)
+/*! TPS - Tamper Pull Select
+ *  0b0..Tamper pin pull resistor direction will assert the tamper pin.
+ *  0b1..Tamper pin pull resistor direction will negate the tamper pin.
+ */
+#define RTC_PCR_TPS(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TPS_SHIFT)) & RTC_PCR_TPS_MASK)
+#define RTC_PCR_TFE_MASK                         (0x4000000U)
+#define RTC_PCR_TFE_SHIFT                        (26U)
+/*! TFE - Tamper Filter Enable
+ *  0b0..Input filter is disabled on the tamper pin.
+ *  0b1..Input filter is enabled on the tamper pin.
+ */
+#define RTC_PCR_TFE(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TFE_SHIFT)) & RTC_PCR_TFE_MASK)
+#define RTC_PCR_TPP_MASK                         (0x8000000U)
+#define RTC_PCR_TPP_SHIFT                        (27U)
+/*! TPP - Tamper Pin Polarity
+ *  0b0..Tamper pin is active high.
+ *  0b1..Tamper pin is active low.
+ */
+#define RTC_PCR_TPP(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TPP_SHIFT)) & RTC_PCR_TPP_MASK)
+#define RTC_PCR_TPID_MASK                        (0x80000000U)
+#define RTC_PCR_TPID_SHIFT                       (31U)
+/*! TPID - Tamper Pin Input Data
+ *  0b0..Tamper pin input data is logic zero.
+ *  0b1..Tamper pin input data is logic one.
+ */
+#define RTC_PCR_TPID(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TPID_SHIFT)) & RTC_PCR_TPID_MASK)
+/*! @} */
+
+/* The count of RTC_PCR */
+#define RTC_PCR_COUNT                            (4U)
+
+/*! @name WAR - RTC Write Access Register */
+/*! @{ */
+#define RTC_WAR_TSRW_MASK                        (0x1U)
+#define RTC_WAR_TSRW_SHIFT                       (0U)
+/*! TSRW - Time Seconds Register Write
+ *  0b0..Writes to the Time Seconds Register are ignored.
+ *  0b1..Writes to the Time Seconds Register complete as normal.
+ */
+#define RTC_WAR_TSRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
+#define RTC_WAR_TPRW_MASK                        (0x2U)
+#define RTC_WAR_TPRW_SHIFT                       (1U)
+/*! TPRW - Time Prescaler Register Write
+ *  0b0..Writes to the Time Prescaler Register are ignored.
+ *  0b1..Writes to the Time Prescaler Register complete as normal.
+ */
+#define RTC_WAR_TPRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
+#define RTC_WAR_TARW_MASK                        (0x4U)
+#define RTC_WAR_TARW_SHIFT                       (2U)
+/*! TARW - Time Alarm Register Write
+ *  0b0..Writes to the Time Alarm Register are ignored.
+ *  0b1..Writes to the Time Alarm Register complete as normal.
+ */
+#define RTC_WAR_TARW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
+#define RTC_WAR_TCRW_MASK                        (0x8U)
+#define RTC_WAR_TCRW_SHIFT                       (3U)
+/*! TCRW - Time Compensation Register Write
+ *  0b0..Writes to the Time Compensation Register are ignored.
+ *  0b1..Writes to the Time Compensation Register complete as normal.
+ */
+#define RTC_WAR_TCRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
+#define RTC_WAR_CRW_MASK                         (0x10U)
+#define RTC_WAR_CRW_SHIFT                        (4U)
+/*! CRW - Control Register Write
+ *  0b0..Writes to the Control Register are ignored.
+ *  0b1..Writes to the Control Register complete as normal.
+ */
+#define RTC_WAR_CRW(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
+#define RTC_WAR_SRW_MASK                         (0x20U)
+#define RTC_WAR_SRW_SHIFT                        (5U)
+/*! SRW - Status Register Write
+ *  0b0..Writes to the Status Register are ignored.
+ *  0b1..Writes to the Status Register complete as normal.
+ */
+#define RTC_WAR_SRW(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
+#define RTC_WAR_LRW_MASK                         (0x40U)
+#define RTC_WAR_LRW_SHIFT                        (6U)
+/*! LRW - Lock Register Write
+ *  0b0..Writes to the Lock Register are ignored.
+ *  0b1..Writes to the Lock Register complete as normal.
+ */
+#define RTC_WAR_LRW(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
+#define RTC_WAR_IERW_MASK                        (0x80U)
+#define RTC_WAR_IERW_SHIFT                       (7U)
+/*! IERW - Interrupt Enable Register Write
+ *  0b0..Writes to the Interupt Enable Register are ignored.
+ *  0b1..Writes to the Interrupt Enable Register complete as normal.
+ */
+#define RTC_WAR_IERW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
+#define RTC_WAR_TTSW_MASK                        (0x100U)
+#define RTC_WAR_TTSW_SHIFT                       (8U)
+/*! TTSW - Tamper Time Seconds Write
+ *  0b0..Writes to the Tamper Time Seconds Register are ignored.
+ *  0b1..Writes to the Tamper Time Seconds Register complete as normal.
+ */
+#define RTC_WAR_TTSW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TTSW_SHIFT)) & RTC_WAR_TTSW_MASK)
+#define RTC_WAR_MERW_MASK                        (0x200U)
+#define RTC_WAR_MERW_SHIFT                       (9U)
+/*! MERW - Monotonic Enable Register Write
+ *  0b0..Writes to the Monotonic Enable Register are ignored.
+ *  0b1..Writes to the Monotonic Enable Register complete as normal.
+ */
+#define RTC_WAR_MERW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MERW_SHIFT)) & RTC_WAR_MERW_MASK)
+#define RTC_WAR_MCLW_MASK                        (0x400U)
+#define RTC_WAR_MCLW_SHIFT                       (10U)
+/*! MCLW - Monotonic Counter Low Write
+ *  0b0..Writes to the Monotonic Counter Low Register are ignored.
+ *  0b1..Writes to the Monotonic Counter Low Register complete as normal.
+ */
+#define RTC_WAR_MCLW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCLW_SHIFT)) & RTC_WAR_MCLW_MASK)
+#define RTC_WAR_MCHW_MASK                        (0x800U)
+#define RTC_WAR_MCHW_SHIFT                       (11U)
+/*! MCHW - Monotonic Counter High Write
+ *  0b0..Writes to the Monotonic Counter High Register are ignored.
+ *  0b1..Writes to the Monotonic Counter High Register complete as normal.
+ */
+#define RTC_WAR_MCHW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCHW_SHIFT)) & RTC_WAR_MCHW_MASK)
+#define RTC_WAR_TDRW_MASK                        (0x2000U)
+#define RTC_WAR_TDRW_SHIFT                       (13U)
+/*! TDRW - Tamper Detect Register Write
+ *  0b0..Writes to the Tamper Detect Register are ignored.
+ *  0b1..Writes to the Tamper Detect Register complete as normal.
+ */
+#define RTC_WAR_TDRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TDRW_SHIFT)) & RTC_WAR_TDRW_MASK)
+#define RTC_WAR_TIRW_MASK                        (0x8000U)
+#define RTC_WAR_TIRW_SHIFT                       (15U)
+/*! TIRW - Tamper Interrupt Register Write
+ *  0b0..Writes to the Tamper Interrupt Register are ignored.
+ *  0b1..Writes to the Tamper Interrupt Register complete as normal.
+ */
+#define RTC_WAR_TIRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TIRW_SHIFT)) & RTC_WAR_TIRW_MASK)
+#define RTC_WAR_PCRW_MASK                        (0xF0000U)
+#define RTC_WAR_PCRW_SHIFT                       (16U)
+#define RTC_WAR_PCRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_PCRW_SHIFT)) & RTC_WAR_PCRW_MASK)
+/*! @} */
+
+/*! @name RAR - RTC Read Access Register */
+/*! @{ */
+#define RTC_RAR_TSRR_MASK                        (0x1U)
+#define RTC_RAR_TSRR_SHIFT                       (0U)
+/*! TSRR - Time Seconds Register Read
+ *  0b0..Reads to the Time Seconds Register are ignored.
+ *  0b1..Reads to the Time Seconds Register complete as normal.
+ */
+#define RTC_RAR_TSRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
+#define RTC_RAR_TPRR_MASK                        (0x2U)
+#define RTC_RAR_TPRR_SHIFT                       (1U)
+/*! TPRR - Time Prescaler Register Read
+ *  0b0..Reads to the Time Pprescaler Register are ignored.
+ *  0b1..Reads to the Time Prescaler Register complete as normal.
+ */
+#define RTC_RAR_TPRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
+#define RTC_RAR_TARR_MASK                        (0x4U)
+#define RTC_RAR_TARR_SHIFT                       (2U)
+/*! TARR - Time Alarm Register Read
+ *  0b0..Reads to the Time Alarm Register are ignored.
+ *  0b1..Reads to the Time Alarm Register complete as normal.
+ */
+#define RTC_RAR_TARR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
+#define RTC_RAR_TCRR_MASK                        (0x8U)
+#define RTC_RAR_TCRR_SHIFT                       (3U)
+/*! TCRR - Time Compensation Register Read
+ *  0b0..Reads to the Time Compensation Register are ignored.
+ *  0b1..Reads to the Time Compensation Register complete as normal.
+ */
+#define RTC_RAR_TCRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
+#define RTC_RAR_CRR_MASK                         (0x10U)
+#define RTC_RAR_CRR_SHIFT                        (4U)
+/*! CRR - Control Register Read
+ *  0b0..Reads to the Control Register are ignored.
+ *  0b1..Reads to the Control Register complete as normal.
+ */
+#define RTC_RAR_CRR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
+#define RTC_RAR_SRR_MASK                         (0x20U)
+#define RTC_RAR_SRR_SHIFT                        (5U)
+/*! SRR - Status Register Read
+ *  0b0..Reads to the Status Register are ignored.
+ *  0b1..Reads to the Status Register complete as normal.
+ */
+#define RTC_RAR_SRR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
+#define RTC_RAR_LRR_MASK                         (0x40U)
+#define RTC_RAR_LRR_SHIFT                        (6U)
+/*! LRR - Lock Register Read
+ *  0b0..Reads to the Lock Register are ignored.
+ *  0b1..Reads to the Lock Register complete as normal.
+ */
+#define RTC_RAR_LRR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
+#define RTC_RAR_IERR_MASK                        (0x80U)
+#define RTC_RAR_IERR_SHIFT                       (7U)
+/*! IERR - Interrupt Enable Register Read
+ *  0b0..Reads to the Interrupt Enable Register are ignored.
+ *  0b1..Reads to the Interrupt Enable Register complete as normal.
+ */
+#define RTC_RAR_IERR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
+#define RTC_RAR_TTSR_MASK                        (0x100U)
+#define RTC_RAR_TTSR_SHIFT                       (8U)
+/*! TTSR - Tamper Time Seconds Read
+ *  0b0..Reads to the Tamper Time Seconds Register are ignored.
+ *  0b1..Reads to the Tamper Time Seconds Register complete as normal.
+ */
+#define RTC_RAR_TTSR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TTSR_SHIFT)) & RTC_RAR_TTSR_MASK)
+#define RTC_RAR_MERR_MASK                        (0x200U)
+#define RTC_RAR_MERR_SHIFT                       (9U)
+/*! MERR - Monotonic Enable Register Read
+ *  0b0..Reads to the Monotonic Enable Register are ignored.
+ *  0b1..Reads to the Monotonic Enable Register complete as normal.
+ */
+#define RTC_RAR_MERR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MERR_SHIFT)) & RTC_RAR_MERR_MASK)
+#define RTC_RAR_MCLR_MASK                        (0x400U)
+#define RTC_RAR_MCLR_SHIFT                       (10U)
+/*! MCLR - Monotonic Counter Low Read
+ *  0b0..Reads to the Monotonic Counter Low Register are ignored.
+ *  0b1..Reads to the Monotonic Counter Low Register complete as normal.
+ */
+#define RTC_RAR_MCLR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCLR_SHIFT)) & RTC_RAR_MCLR_MASK)
+#define RTC_RAR_MCHR_MASK                        (0x800U)
+#define RTC_RAR_MCHR_SHIFT                       (11U)
+/*! MCHR - Monotonic Counter High Read
+ *  0b0..Reads to the Monotonic Counter High Register are ignored.
+ *  0b1..Reads to the Monotonic Counter High Register complete as normal.
+ */
+#define RTC_RAR_MCHR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCHR_SHIFT)) & RTC_RAR_MCHR_MASK)
+#define RTC_RAR_TDRR_MASK                        (0x2000U)
+#define RTC_RAR_TDRR_SHIFT                       (13U)
+/*! TDRR - Tamper Detect Register Read
+ *  0b0..Reads to the Tamper Detect Register are ignored.
+ *  0b1..Reads to the Tamper Detect Register complete as normal.
+ */
+#define RTC_RAR_TDRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TDRR_SHIFT)) & RTC_RAR_TDRR_MASK)
+#define RTC_RAR_TIRR_MASK                        (0x8000U)
+#define RTC_RAR_TIRR_SHIFT                       (15U)
+/*! TIRR - Tamper Interrupt Register Read
+ *  0b0..Reads to the Tamper Interrupt Register are ignored.
+ *  0b1..Reads to the Tamper Interrupt Register complete as normal.
+ */
+#define RTC_RAR_TIRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TIRR_SHIFT)) & RTC_RAR_TIRR_MASK)
+#define RTC_RAR_PCRR_MASK                        (0xF0000U)
+#define RTC_RAR_PCRR_SHIFT                       (16U)
+#define RTC_RAR_PCRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_PCRR_SHIFT)) & RTC_RAR_PCRR_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE                                 (0x40031000u)
+/** Peripheral RTC base pointer */
+#define RTC                                      ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS                           { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS                            { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS                                 { RTC_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SCG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SCG_Peripheral_Access_Layer SCG Peripheral Access Layer
+ * @{
+ */
+
+/** SCG - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+       uint8_t RESERVED_0[8];
+  __I  uint32_t CSR;                               /**< Clock Status Register, offset: 0x10 */
+  __IO uint32_t RCCR;                              /**< Run Clock Control Register, offset: 0x14 */
+  __IO uint32_t VCCR;                              /**< VLPR Clock Control Register, offset: 0x18 */
+  __IO uint32_t HCCR;                              /**< HSRUN Clock Control Register, offset: 0x1C */
+  __IO uint32_t CLKOUTCNFG;                        /**< SCG CLKOUT Configuration Register, offset: 0x20 */
+       uint8_t RESERVED_1[220];
+  __IO uint32_t SOSCCSR;                           /**< System OSC Control Status Register, offset: 0x100 */
+  __IO uint32_t SOSCDIV;                           /**< System OSC Divide Register, offset: 0x104 */
+       uint8_t RESERVED_2[248];
+  __IO uint32_t SIRCCSR;                           /**< Slow IRC Control Status Register, offset: 0x200 */
+  __IO uint32_t SIRCDIV;                           /**< Slow IRC Divide Register, offset: 0x204 */
+  __IO uint32_t SIRCCFG;                           /**< Slow IRC Configuration Register, offset: 0x208 */
+       uint8_t RESERVED_3[244];
+  __IO uint32_t FIRCCSR;                           /**< Fast IRC Control Status Register, offset: 0x300 */
+  __IO uint32_t FIRCDIV;                           /**< Fast IRC Divide Register, offset: 0x304 */
+  __IO uint32_t FIRCCFG;                           /**< Fast IRC Configuration Register, offset: 0x308 */
+  __IO uint32_t FIRCTCFG;                          /**< Fast IRC Trim Configuration Register, offset: 0x30C */
+       uint8_t RESERVED_4[8];
+  __IO uint32_t FIRCSTAT;                          /**< Fast IRC Status Register, offset: 0x318 */
+       uint8_t RESERVED_5[228];
+  __IO uint32_t ROSCCSR;                           /**< RTC OSC Control Status Register, offset: 0x400 */
+       uint8_t RESERVED_6[252];
+  __IO uint32_t LPFLLCSR;                          /**< Low Power FLL Control Status Register, offset: 0x500 */
+  __IO uint32_t LPFLLDIV;                          /**< Low Power FLL Divide Register, offset: 0x504 */
+  __IO uint32_t LPFLLCFG;                          /**< Low Power FLL Configuration Register, offset: 0x508 */
+  __IO uint32_t LPFLLTCFG;                         /**< Low Power FLL Trim Configuration Register, offset: 0x50C */
+       uint8_t RESERVED_7[4];
+  __IO uint32_t LPFLLSTAT;                         /**< Low Power FLL Status Register, offset: 0x514 */
+} SCG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SCG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SCG_Register_Masks SCG Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define SCG_VERID_VERSION_MASK                   (0xFFFFFFFFU)
+#define SCG_VERID_VERSION_SHIFT                  (0U)
+#define SCG_VERID_VERSION(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_VERID_VERSION_SHIFT)) & SCG_VERID_VERSION_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define SCG_PARAM_CLKPRES_MASK                   (0xFFU)
+#define SCG_PARAM_CLKPRES_SHIFT                  (0U)
+/*! CLKPRES - Clock Present
+ *  0b00000000-0b00000001..Reserved.
+ *  0bxxxxxx1x..System OSC (SOSC) is present.
+ *  0bxxxxx1xx..Slow IRC (SIRC) is present.
+ *  0bxxxx1xxx..Fast IRC (FIRC) is present.
+ *  0bxxx1xxxx..RTC OSC (ROSC) is present.
+ *  0bxx1xxxxx..Low Power FLL (LPFLL) is present.
+ */
+#define SCG_PARAM_CLKPRES(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_CLKPRES_SHIFT)) & SCG_PARAM_CLKPRES_MASK)
+#define SCG_PARAM_DIVPRES_MASK                   (0xF8000000U)
+#define SCG_PARAM_DIVPRES_SHIFT                  (27U)
+/*! DIVPRES - Divider Present
+ *  0bxxxx1..System DIVSLOW is present.
+ *  0bxxx1x..System DIVBUS is present.
+ *  0bxx1xx..System DIVEXT is present.
+ *  0b1xxxx..System DIVCORE is present.
+ */
+#define SCG_PARAM_DIVPRES(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_DIVPRES_SHIFT)) & SCG_PARAM_DIVPRES_MASK)
+/*! @} */
+
+/*! @name CSR - Clock Status Register */
+/*! @{ */
+#define SCG_CSR_DIVSLOW_MASK                     (0xFU)
+#define SCG_CSR_DIVSLOW_SHIFT                    (0U)
+/*! DIVSLOW - Slow Clock Divide Ratio
+ *  0b0000..Reserved
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_CSR_DIVSLOW(x)                       (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
+#define SCG_CSR_DIVBUS_MASK                      (0xF0U)
+#define SCG_CSR_DIVBUS_SHIFT                     (4U)
+/*! DIVBUS - Bus Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_CSR_DIVBUS(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVBUS_SHIFT)) & SCG_CSR_DIVBUS_MASK)
+#define SCG_CSR_DIVEXT_MASK                      (0xF00U)
+#define SCG_CSR_DIVEXT_SHIFT                     (8U)
+/*! DIVEXT - External Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_CSR_DIVEXT(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVEXT_SHIFT)) & SCG_CSR_DIVEXT_MASK)
+#define SCG_CSR_DIVCORE_MASK                     (0xF0000U)
+#define SCG_CSR_DIVCORE_SHIFT                    (16U)
+/*! DIVCORE - Core Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_CSR_DIVCORE(x)                       (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVCORE_SHIFT)) & SCG_CSR_DIVCORE_MASK)
+#define SCG_CSR_SCS_MASK                         (0xF000000U)
+#define SCG_CSR_SCS_SHIFT                        (24U)
+/*! SCS - System Clock Source
+ *  0b0000..Reserved
+ *  0b0001..System OSC (SOSC_CLK)
+ *  0b0010..Slow IRC (SIRC_CLK)
+ *  0b0011..Fast IRC (FIRC_CLK)
+ *  0b0100..RTC OSC (ROSC_CLK)
+ *  0b0101..Low Power FLL (LPFLL_CLK)
+ *  0b0110..Reserved
+ *  0b0111..Reserved
+ */
+#define SCG_CSR_SCS(x)                           (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK)
+/*! @} */
+
+/*! @name RCCR - Run Clock Control Register */
+/*! @{ */
+#define SCG_RCCR_DIVSLOW_MASK                    (0xFU)
+#define SCG_RCCR_DIVSLOW_SHIFT                   (0U)
+/*! DIVSLOW - Slow Clock Divide Ratio
+ *  0b0000..Reserved
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_RCCR_DIVSLOW(x)                      (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVSLOW_SHIFT)) & SCG_RCCR_DIVSLOW_MASK)
+#define SCG_RCCR_DIVBUS_MASK                     (0xF0U)
+#define SCG_RCCR_DIVBUS_SHIFT                    (4U)
+/*! DIVBUS - Bus Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_RCCR_DIVBUS(x)                       (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVBUS_SHIFT)) & SCG_RCCR_DIVBUS_MASK)
+#define SCG_RCCR_DIVEXT_MASK                     (0xF00U)
+#define SCG_RCCR_DIVEXT_SHIFT                    (8U)
+/*! DIVEXT - External Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_RCCR_DIVEXT(x)                       (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVEXT_SHIFT)) & SCG_RCCR_DIVEXT_MASK)
+#define SCG_RCCR_DIVCORE_MASK                    (0xF0000U)
+#define SCG_RCCR_DIVCORE_SHIFT                   (16U)
+/*! DIVCORE - Core Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_RCCR_DIVCORE(x)                      (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVCORE_SHIFT)) & SCG_RCCR_DIVCORE_MASK)
+#define SCG_RCCR_SCS_MASK                        (0x7000000U)
+#define SCG_RCCR_SCS_SHIFT                       (24U)
+/*! SCS - System Clock Source
+ *  0b000..Reserved
+ *  0b001..System OSC (SOSC_CLK)
+ *  0b010..Slow IRC (SIRC_CLK)
+ *  0b011..Fast IRC (FIRC_CLK)
+ *  0b100..RTC OSC (ROSC_CLK)
+ *  0b101..Low Power FLL (LPFLL_CLK)
+ *  0b110..Reserved
+ *  0b111..Reserved
+ */
+#define SCG_RCCR_SCS(x)                          (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK)
+/*! @} */
+
+/*! @name VCCR - VLPR Clock Control Register */
+/*! @{ */
+#define SCG_VCCR_DIVSLOW_MASK                    (0xFU)
+#define SCG_VCCR_DIVSLOW_SHIFT                   (0U)
+/*! DIVSLOW - Slow Clock Divide Ratio
+ *  0b0000..Reserved
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_VCCR_DIVSLOW(x)                      (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVSLOW_SHIFT)) & SCG_VCCR_DIVSLOW_MASK)
+#define SCG_VCCR_DIVBUS_MASK                     (0xF0U)
+#define SCG_VCCR_DIVBUS_SHIFT                    (4U)
+/*! DIVBUS - Bus Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_VCCR_DIVBUS(x)                       (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVBUS_SHIFT)) & SCG_VCCR_DIVBUS_MASK)
+#define SCG_VCCR_DIVEXT_MASK                     (0xF00U)
+#define SCG_VCCR_DIVEXT_SHIFT                    (8U)
+/*! DIVEXT - External Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_VCCR_DIVEXT(x)                       (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVEXT_SHIFT)) & SCG_VCCR_DIVEXT_MASK)
+#define SCG_VCCR_DIVCORE_MASK                    (0xF0000U)
+#define SCG_VCCR_DIVCORE_SHIFT                   (16U)
+/*! DIVCORE - Core Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_VCCR_DIVCORE(x)                      (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)
+#define SCG_VCCR_SCS_MASK                        (0xF000000U)
+#define SCG_VCCR_SCS_SHIFT                       (24U)
+/*! SCS - System Clock Source
+ *  0b0000..Reserved
+ *  0b0001..System OSC (SOSC_CLK)
+ *  0b0010..Slow IRC (SIRC_CLK)
+ *  0b0011..Reserved
+ *  0b0100..RTC OSC (ROSC_CLK)
+ *  0b0101..Reserved
+ *  0b0110..Reserved
+ *  0b0111..Reserved
+ */
+#define SCG_VCCR_SCS(x)                          (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_SCS_SHIFT)) & SCG_VCCR_SCS_MASK)
+/*! @} */
+
+/*! @name HCCR - HSRUN Clock Control Register */
+/*! @{ */
+#define SCG_HCCR_DIVSLOW_MASK                    (0xFU)
+#define SCG_HCCR_DIVSLOW_SHIFT                   (0U)
+/*! DIVSLOW - Slow Clock Divide Ratio
+ *  0b0000..Reserved
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_HCCR_DIVSLOW(x)                      (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVSLOW_SHIFT)) & SCG_HCCR_DIVSLOW_MASK)
+#define SCG_HCCR_DIVBUS_MASK                     (0xF0U)
+#define SCG_HCCR_DIVBUS_SHIFT                    (4U)
+/*! DIVBUS - Bus Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_HCCR_DIVBUS(x)                       (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVBUS_SHIFT)) & SCG_HCCR_DIVBUS_MASK)
+#define SCG_HCCR_DIVEXT_MASK                     (0xF00U)
+#define SCG_HCCR_DIVEXT_SHIFT                    (8U)
+/*! DIVEXT - External Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_HCCR_DIVEXT(x)                       (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVEXT_SHIFT)) & SCG_HCCR_DIVEXT_MASK)
+#define SCG_HCCR_DIVCORE_MASK                    (0xF0000U)
+#define SCG_HCCR_DIVCORE_SHIFT                   (16U)
+/*! DIVCORE - Core Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_HCCR_DIVCORE(x)                      (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVCORE_SHIFT)) & SCG_HCCR_DIVCORE_MASK)
+#define SCG_HCCR_SCS_MASK                        (0xF000000U)
+#define SCG_HCCR_SCS_SHIFT                       (24U)
+/*! SCS - System Clock Source
+ *  0b0000..Reserved
+ *  0b0001..System OSC (SOSC_CLK)
+ *  0b0010..Slow IRC (SIRC_CLK)
+ *  0b0011..Fast IRC (FIRC_CLK)
+ *  0b0100..RTC OSC (ROSC_CLK)
+ *  0b0101..Low Power FLL (LPFLL_CLK)
+ *  0b0110..Reserved
+ *  0b0111..Reserved
+ */
+#define SCG_HCCR_SCS(x)                          (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_SCS_SHIFT)) & SCG_HCCR_SCS_MASK)
+/*! @} */
+
+/*! @name CLKOUTCNFG - SCG CLKOUT Configuration Register */
+/*! @{ */
+#define SCG_CLKOUTCNFG_CLKOUTSEL_MASK            (0xF000000U)
+#define SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT           (24U)
+/*! CLKOUTSEL - SCG Clkout Select
+ *  0b0000..SCG EXTERNAL Clock
+ *  0b0001..System OSC (SOSC_CLK)
+ *  0b0010..Slow IRC (SIRC_CLK)
+ *  0b0011..Fast IRC (FIRC_CLK)
+ *  0b0100..RTC OSC (ROSC_CLK)
+ *  0b0101..Low Power FLL (LPFLL_CLK)
+ *  0b0110..Reserved
+ *  0b0111..Reserved
+ *  0b1111..Reserved
+ */
+#define SCG_CLKOUTCNFG_CLKOUTSEL(x)              (((uint32_t)(((uint32_t)(x)) << SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT)) & SCG_CLKOUTCNFG_CLKOUTSEL_MASK)
+/*! @} */
+
+/*! @name SOSCCSR - System OSC Control Status Register */
+/*! @{ */
+#define SCG_SOSCCSR_SOSCEN_MASK                  (0x1U)
+#define SCG_SOSCCSR_SOSCEN_SHIFT                 (0U)
+/*! SOSCEN - System OSC Enable
+ *  0b0..System OSC is disabled
+ *  0b1..System OSC is enabled
+ */
+#define SCG_SOSCCSR_SOSCEN(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK)
+#define SCG_SOSCCSR_SOSCSTEN_MASK                (0x2U)
+#define SCG_SOSCCSR_SOSCSTEN_SHIFT               (1U)
+/*! SOSCSTEN - System OSC Stop Enable
+ *  0b0..System OSC is disabled in Stop modes
+ *  0b1..System OSC is enabled in Stop modes if SOSCEN=1. In VLLS0, system oscillator is disabled even if SOSCSTEN=1 and SOSCEN=1.
+ */
+#define SCG_SOSCCSR_SOSCSTEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSTEN_SHIFT)) & SCG_SOSCCSR_SOSCSTEN_MASK)
+#define SCG_SOSCCSR_SOSCLPEN_MASK                (0x4U)
+#define SCG_SOSCCSR_SOSCLPEN_SHIFT               (2U)
+/*! SOSCLPEN - System OSC Low Power Enable
+ *  0b0..System OSC is disabled in VLP modes
+ *  0b1..System OSC is enabled in VLP modes
+ */
+#define SCG_SOSCCSR_SOSCLPEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCLPEN_SHIFT)) & SCG_SOSCCSR_SOSCLPEN_MASK)
+#define SCG_SOSCCSR_SOSCCM_MASK                  (0x10000U)
+#define SCG_SOSCCSR_SOSCCM_SHIFT                 (16U)
+/*! SOSCCM - System OSC Clock Monitor
+ *  0b0..System OSC Clock Monitor is disabled
+ *  0b1..System OSC Clock Monitor is enabled
+ */
+#define SCG_SOSCCSR_SOSCCM(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCM_SHIFT)) & SCG_SOSCCSR_SOSCCM_MASK)
+#define SCG_SOSCCSR_SOSCCMRE_MASK                (0x20000U)
+#define SCG_SOSCCSR_SOSCCMRE_SHIFT               (17U)
+/*! SOSCCMRE - System OSC Clock Monitor Reset Enable
+ *  0b0..Clock Monitor generates interrupt when error detected
+ *  0b1..Clock Monitor generates reset when error detected
+ */
+#define SCG_SOSCCSR_SOSCCMRE(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCMRE_SHIFT)) & SCG_SOSCCSR_SOSCCMRE_MASK)
+#define SCG_SOSCCSR_LK_MASK                      (0x800000U)
+#define SCG_SOSCCSR_LK_SHIFT                     (23U)
+/*! LK - Lock Register
+ *  0b0..This Control Status Register can be written.
+ *  0b1..This Control Status Register cannot be written.
+ */
+#define SCG_SOSCCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_LK_SHIFT)) & SCG_SOSCCSR_LK_MASK)
+#define SCG_SOSCCSR_SOSCVLD_MASK                 (0x1000000U)
+#define SCG_SOSCCSR_SOSCVLD_SHIFT                (24U)
+/*! SOSCVLD - System OSC Valid
+ *  0b0..System OSC is not enabled or clock is not valid
+ *  0b1..System OSC is enabled and output clock is valid
+ */
+#define SCG_SOSCCSR_SOSCVLD(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK)
+#define SCG_SOSCCSR_SOSCSEL_MASK                 (0x2000000U)
+#define SCG_SOSCCSR_SOSCSEL_SHIFT                (25U)
+/*! SOSCSEL - System OSC Selected
+ *  0b0..System OSC is not the system clock source
+ *  0b1..System OSC is the system clock source
+ */
+#define SCG_SOSCCSR_SOSCSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSEL_SHIFT)) & SCG_SOSCCSR_SOSCSEL_MASK)
+#define SCG_SOSCCSR_SOSCERR_MASK                 (0x4000000U)
+#define SCG_SOSCCSR_SOSCERR_SHIFT                (26U)
+/*! SOSCERR - System OSC Clock Error
+ *  0b0..System OSC Clock Monitor is disabled or has not detected an error
+ *  0b1..System OSC Clock Monitor is enabled and detected an error
+ */
+#define SCG_SOSCCSR_SOSCERR(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERR_SHIFT)) & SCG_SOSCCSR_SOSCERR_MASK)
+/*! @} */
+
+/*! @name SOSCDIV - System OSC Divide Register */
+/*! @{ */
+#define SCG_SOSCDIV_SOSCDIV1_MASK                (0x7U)
+#define SCG_SOSCDIV_SOSCDIV1_SHIFT               (0U)
+/*! SOSCDIV1 - System OSC Clock Divide 1
+ *  0b000..Output disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_SOSCDIV_SOSCDIV1(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV1_SHIFT)) & SCG_SOSCDIV_SOSCDIV1_MASK)
+#define SCG_SOSCDIV_SOSCDIV2_MASK                (0x700U)
+#define SCG_SOSCDIV_SOSCDIV2_SHIFT               (8U)
+/*! SOSCDIV2 - System OSC Clock Divide 2
+ *  0b000..Output disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_SOSCDIV_SOSCDIV2(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV2_SHIFT)) & SCG_SOSCDIV_SOSCDIV2_MASK)
+#define SCG_SOSCDIV_SOSCDIV3_MASK                (0x70000U)
+#define SCG_SOSCDIV_SOSCDIV3_SHIFT               (16U)
+/*! SOSCDIV3 - System OSC Clock Divide 3
+ *  0b000..Output disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_SOSCDIV_SOSCDIV3(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV3_SHIFT)) & SCG_SOSCDIV_SOSCDIV3_MASK)
+/*! @} */
+
+/*! @name SIRCCSR - Slow IRC Control Status Register */
+/*! @{ */
+#define SCG_SIRCCSR_SIRCEN_MASK                  (0x1U)
+#define SCG_SIRCCSR_SIRCEN_SHIFT                 (0U)
+/*! SIRCEN - Slow IRC Enable
+ *  0b0..Slow IRC is disabled
+ *  0b1..Slow IRC is enabled
+ */
+#define SCG_SIRCCSR_SIRCEN(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCEN_SHIFT)) & SCG_SIRCCSR_SIRCEN_MASK)
+#define SCG_SIRCCSR_SIRCSTEN_MASK                (0x2U)
+#define SCG_SIRCCSR_SIRCSTEN_SHIFT               (1U)
+/*! SIRCSTEN - Slow IRC Stop Enable
+ *  0b0..Slow IRC is disabled in Stop modes
+ *  0b1..Slow IRC is enabled in Stop modes
+ */
+#define SCG_SIRCCSR_SIRCSTEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSTEN_SHIFT)) & SCG_SIRCCSR_SIRCSTEN_MASK)
+#define SCG_SIRCCSR_SIRCLPEN_MASK                (0x4U)
+#define SCG_SIRCCSR_SIRCLPEN_SHIFT               (2U)
+/*! SIRCLPEN - Slow IRC Low Power Enable
+ *  0b0..Slow IRC is disabled in VLP modes
+ *  0b1..Slow IRC is enabled in VLP modes
+ */
+#define SCG_SIRCCSR_SIRCLPEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCLPEN_SHIFT)) & SCG_SIRCCSR_SIRCLPEN_MASK)
+#define SCG_SIRCCSR_LK_MASK                      (0x800000U)
+#define SCG_SIRCCSR_LK_SHIFT                     (23U)
+/*! LK - Lock Register
+ *  0b0..Control Status Register can be written.
+ *  0b1..Control Status Register cannot be written.
+ */
+#define SCG_SIRCCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_LK_SHIFT)) & SCG_SIRCCSR_LK_MASK)
+#define SCG_SIRCCSR_SIRCVLD_MASK                 (0x1000000U)
+#define SCG_SIRCCSR_SIRCVLD_SHIFT                (24U)
+/*! SIRCVLD - Slow IRC Valid
+ *  0b0..Slow IRC is not enabled or clock is not valid
+ *  0b1..Slow IRC is enabled and output clock is valid
+ */
+#define SCG_SIRCCSR_SIRCVLD(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK)
+#define SCG_SIRCCSR_SIRCSEL_MASK                 (0x2000000U)
+#define SCG_SIRCCSR_SIRCSEL_SHIFT                (25U)
+/*! SIRCSEL - Slow IRC Selected
+ *  0b0..Slow IRC is not the system clock source
+ *  0b1..Slow IRC is the system clock source
+ */
+#define SCG_SIRCCSR_SIRCSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSEL_SHIFT)) & SCG_SIRCCSR_SIRCSEL_MASK)
+/*! @} */
+
+/*! @name SIRCDIV - Slow IRC Divide Register */
+/*! @{ */
+#define SCG_SIRCDIV_SIRCDIV1_MASK                (0x7U)
+#define SCG_SIRCDIV_SIRCDIV1_SHIFT               (0U)
+/*! SIRCDIV1 - Slow IRC Clock Divide 1
+ *  0b000..Output disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_SIRCDIV_SIRCDIV1(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV1_SHIFT)) & SCG_SIRCDIV_SIRCDIV1_MASK)
+#define SCG_SIRCDIV_SIRCDIV2_MASK                (0x700U)
+#define SCG_SIRCDIV_SIRCDIV2_SHIFT               (8U)
+/*! SIRCDIV2 - Slow IRC Clock Divide 2
+ *  0b000..Output disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_SIRCDIV_SIRCDIV2(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV2_SHIFT)) & SCG_SIRCDIV_SIRCDIV2_MASK)
+#define SCG_SIRCDIV_SIRCDIV3_MASK                (0x70000U)
+#define SCG_SIRCDIV_SIRCDIV3_SHIFT               (16U)
+/*! SIRCDIV3 - Slow IRC Clock Divider 3
+ *  0b000..Output disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_SIRCDIV_SIRCDIV3(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV3_SHIFT)) & SCG_SIRCDIV_SIRCDIV3_MASK)
+/*! @} */
+
+/*! @name SIRCCFG - Slow IRC Configuration Register */
+/*! @{ */
+#define SCG_SIRCCFG_RANGE_MASK                   (0x1U)
+#define SCG_SIRCCFG_RANGE_SHIFT                  (0U)
+/*! RANGE - Frequency Range
+ *  0b0..Slow IRC low range clock (2MHz)
+ *  0b1..Slow IRC high range clock (8 MHz)
+ */
+#define SCG_SIRCCFG_RANGE(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCFG_RANGE_SHIFT)) & SCG_SIRCCFG_RANGE_MASK)
+/*! @} */
+
+/*! @name FIRCCSR - Fast IRC Control Status Register */
+/*! @{ */
+#define SCG_FIRCCSR_FIRCEN_MASK                  (0x1U)
+#define SCG_FIRCCSR_FIRCEN_SHIFT                 (0U)
+/*! FIRCEN - Fast IRC Enable
+ *  0b0..Fast IRC is disabled
+ *  0b1..Fast IRC is enabled
+ */
+#define SCG_FIRCCSR_FIRCEN(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK)
+#define SCG_FIRCCSR_FIRCSTEN_MASK                (0x2U)
+#define SCG_FIRCCSR_FIRCSTEN_SHIFT               (1U)
+/*! FIRCSTEN - Fast IRC Stop Enable
+ *  0b0..Fast IRC is disabled in Stop modes.
+ *  0b1..Fast IRC is enabled in Stop modes
+ */
+#define SCG_FIRCCSR_FIRCSTEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSTEN_SHIFT)) & SCG_FIRCCSR_FIRCSTEN_MASK)
+#define SCG_FIRCCSR_FIRCLPEN_MASK                (0x4U)
+#define SCG_FIRCCSR_FIRCLPEN_SHIFT               (2U)
+/*! FIRCLPEN - Fast IRC Low Power Enable
+ *  0b0..Fast IRC is disabled in VLP modes
+ *  0b1..Fast IRC is enabled in VLP modes
+ */
+#define SCG_FIRCCSR_FIRCLPEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCLPEN_SHIFT)) & SCG_FIRCCSR_FIRCLPEN_MASK)
+#define SCG_FIRCCSR_FIRCREGOFF_MASK              (0x8U)
+#define SCG_FIRCCSR_FIRCREGOFF_SHIFT             (3U)
+/*! FIRCREGOFF - Fast IRC Regulator Enable
+ *  0b0..Fast IRC Regulator is enabled.
+ *  0b1..Fast IRC Regulator is disabled.
+ */
+#define SCG_FIRCCSR_FIRCREGOFF(x)                (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCREGOFF_SHIFT)) & SCG_FIRCCSR_FIRCREGOFF_MASK)
+#define SCG_FIRCCSR_FIRCTREN_MASK                (0x100U)
+#define SCG_FIRCCSR_FIRCTREN_SHIFT               (8U)
+/*! FIRCTREN - Fast IRC Trim Enable
+ *  0b0..Disable trimming Fast IRC to an external clock source
+ *  0b1..Enable trimming Fast IRC to an external clock source
+ */
+#define SCG_FIRCCSR_FIRCTREN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTREN_SHIFT)) & SCG_FIRCCSR_FIRCTREN_MASK)
+#define SCG_FIRCCSR_FIRCTRUP_MASK                (0x200U)
+#define SCG_FIRCCSR_FIRCTRUP_SHIFT               (9U)
+/*! FIRCTRUP - Fast IRC Trim Update
+ *  0b0..Disable Fast IRC trimming updates
+ *  0b1..Enable Fast IRC trimming updates
+ */
+#define SCG_FIRCCSR_FIRCTRUP(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTRUP_SHIFT)) & SCG_FIRCCSR_FIRCTRUP_MASK)
+#define SCG_FIRCCSR_LK_MASK                      (0x800000U)
+#define SCG_FIRCCSR_LK_SHIFT                     (23U)
+/*! LK - Lock Register
+ *  0b0..Control Status Register can be written.
+ *  0b1..Control Status Register cannot be written.
+ */
+#define SCG_FIRCCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_LK_SHIFT)) & SCG_FIRCCSR_LK_MASK)
+#define SCG_FIRCCSR_FIRCVLD_MASK                 (0x1000000U)
+#define SCG_FIRCCSR_FIRCVLD_SHIFT                (24U)
+/*! FIRCVLD - Fast IRC Valid status
+ *  0b0..Fast IRC is not enabled or clock is not valid.
+ *  0b1..Fast IRC is enabled and output clock is valid. The clock is valid once there is an output clock from the FIRC analog.
+ */
+#define SCG_FIRCCSR_FIRCVLD(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCVLD_SHIFT)) & SCG_FIRCCSR_FIRCVLD_MASK)
+#define SCG_FIRCCSR_FIRCSEL_MASK                 (0x2000000U)
+#define SCG_FIRCCSR_FIRCSEL_SHIFT                (25U)
+/*! FIRCSEL - Fast IRC Selected status
+ *  0b0..Fast IRC is not the system clock source
+ *  0b1..Fast IRC is the system clock source
+ */
+#define SCG_FIRCCSR_FIRCSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK)
+#define SCG_FIRCCSR_FIRCERR_MASK                 (0x4000000U)
+#define SCG_FIRCCSR_FIRCERR_SHIFT                (26U)
+/*! FIRCERR - Fast IRC Clock Error
+ *  0b0..Error not detected with the Fast IRC trimming.
+ *  0b1..Error detected with the Fast IRC trimming.
+ */
+#define SCG_FIRCCSR_FIRCERR(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_SHIFT)) & SCG_FIRCCSR_FIRCERR_MASK)
+/*! @} */
+
+/*! @name FIRCDIV - Fast IRC Divide Register */
+/*! @{ */
+#define SCG_FIRCDIV_FIRCDIV1_MASK                (0x7U)
+#define SCG_FIRCDIV_FIRCDIV1_SHIFT               (0U)
+/*! FIRCDIV1 - Fast IRC Clock Divide 1
+ *  0b000..Output disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_FIRCDIV_FIRCDIV1(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV1_SHIFT)) & SCG_FIRCDIV_FIRCDIV1_MASK)
+#define SCG_FIRCDIV_FIRCDIV2_MASK                (0x700U)
+#define SCG_FIRCDIV_FIRCDIV2_SHIFT               (8U)
+/*! FIRCDIV2 - Fast IRC Clock Divide 2
+ *  0b000..Output disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_FIRCDIV_FIRCDIV2(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV2_SHIFT)) & SCG_FIRCDIV_FIRCDIV2_MASK)
+#define SCG_FIRCDIV_FIRCDIV3_MASK                (0x70000U)
+#define SCG_FIRCDIV_FIRCDIV3_SHIFT               (16U)
+/*! FIRCDIV3 - Fast IRC Clock Divider 3
+ *  0b000..Clock disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_FIRCDIV_FIRCDIV3(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV3_SHIFT)) & SCG_FIRCDIV_FIRCDIV3_MASK)
+/*! @} */
+
+/*! @name FIRCCFG - Fast IRC Configuration Register */
+/*! @{ */
+#define SCG_FIRCCFG_RANGE_MASK                   (0x3U)
+#define SCG_FIRCCFG_RANGE_SHIFT                  (0U)
+/*! RANGE - Frequency Range
+ *  0b00..Fast IRC is trimmed to 48 MHz
+ *  0b01..Fast IRC is trimmed to 52 MHz
+ *  0b10..Fast IRC is trimmed to 56 MHz
+ *  0b11..Fast IRC is trimmed to 60 MHz
+ */
+#define SCG_FIRCCFG_RANGE(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCFG_RANGE_SHIFT)) & SCG_FIRCCFG_RANGE_MASK)
+/*! @} */
+
+/*! @name FIRCTCFG - Fast IRC Trim Configuration Register */
+/*! @{ */
+#define SCG_FIRCTCFG_TRIMSRC_MASK                (0x3U)
+#define SCG_FIRCTCFG_TRIMSRC_SHIFT               (0U)
+/*! TRIMSRC - Trim Source
+ *  0b00..Reserved
+ *  0b01..Reserved
+ *  0b10..System OSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency slower than 32kHz.
+ *  0b11..RTC OSC (32.768 kHz)
+ */
+#define SCG_FIRCTCFG_TRIMSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMSRC_SHIFT)) & SCG_FIRCTCFG_TRIMSRC_MASK)
+#define SCG_FIRCTCFG_TRIMDIV_MASK                (0x700U)
+#define SCG_FIRCTCFG_TRIMDIV_SHIFT               (8U)
+/*! TRIMDIV - Fast IRC Trim Predivide
+ *  0b000..Divide by 1
+ *  0b001..Divide by 128
+ *  0b010..Divide by 256
+ *  0b011..Divide by 512
+ *  0b100..Divide by 1024
+ *  0b101..Divide by 2048
+ *  0b110..Reserved. Writing this value will result in Divide by 1.
+ *  0b111..Reserved. Writing this value will result in a Divide by 1.
+ */
+#define SCG_FIRCTCFG_TRIMDIV(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMDIV_SHIFT)) & SCG_FIRCTCFG_TRIMDIV_MASK)
+/*! @} */
+
+/*! @name FIRCSTAT - Fast IRC Status Register */
+/*! @{ */
+#define SCG_FIRCSTAT_TRIMFINE_MASK               (0x7FU)
+#define SCG_FIRCSTAT_TRIMFINE_SHIFT              (0U)
+#define SCG_FIRCSTAT_TRIMFINE(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMFINE_SHIFT)) & SCG_FIRCSTAT_TRIMFINE_MASK)
+#define SCG_FIRCSTAT_TRIMCOAR_MASK               (0x3F00U)
+#define SCG_FIRCSTAT_TRIMCOAR_SHIFT              (8U)
+#define SCG_FIRCSTAT_TRIMCOAR(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMCOAR_SHIFT)) & SCG_FIRCSTAT_TRIMCOAR_MASK)
+/*! @} */
+
+/*! @name ROSCCSR - RTC OSC Control Status Register */
+/*! @{ */
+#define SCG_ROSCCSR_ROSCCM_MASK                  (0x10000U)
+#define SCG_ROSCCSR_ROSCCM_SHIFT                 (16U)
+/*! ROSCCM - RTC OSC Clock Monitor
+ *  0b0..RTC OSC Clock Monitor is disabled
+ *  0b1..RTC OSC Clock Monitor is enabled
+ */
+#define SCG_ROSCCSR_ROSCCM(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCCM_SHIFT)) & SCG_ROSCCSR_ROSCCM_MASK)
+#define SCG_ROSCCSR_ROSCCMRE_MASK                (0x20000U)
+#define SCG_ROSCCSR_ROSCCMRE_SHIFT               (17U)
+/*! ROSCCMRE - RTC OSC Clock Monitor Reset Enable
+ *  0b0..Clock Monitor generates interrupt when error detected
+ *  0b1..Clock Monitor generates reset when error detected
+ */
+#define SCG_ROSCCSR_ROSCCMRE(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCCMRE_SHIFT)) & SCG_ROSCCSR_ROSCCMRE_MASK)
+#define SCG_ROSCCSR_LK_MASK                      (0x800000U)
+#define SCG_ROSCCSR_LK_SHIFT                     (23U)
+/*! LK - Lock Register
+ *  0b0..Control Status Register can be written.
+ *  0b1..Control Status Register cannot be written.
+ */
+#define SCG_ROSCCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_LK_SHIFT)) & SCG_ROSCCSR_LK_MASK)
+#define SCG_ROSCCSR_ROSCVLD_MASK                 (0x1000000U)
+#define SCG_ROSCCSR_ROSCVLD_SHIFT                (24U)
+/*! ROSCVLD - RTC OSC Valid
+ *  0b0..RTC OSC is not enabled or clock is not valid
+ *  0b1..RTC OSC is enabled and output clock is valid
+ */
+#define SCG_ROSCCSR_ROSCVLD(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCVLD_SHIFT)) & SCG_ROSCCSR_ROSCVLD_MASK)
+#define SCG_ROSCCSR_ROSCSEL_MASK                 (0x2000000U)
+#define SCG_ROSCCSR_ROSCSEL_SHIFT                (25U)
+/*! ROSCSEL - RTC OSC Selected
+ *  0b0..RTC OSC is not the system clock source
+ *  0b1..RTC OSC is the system clock source
+ */
+#define SCG_ROSCCSR_ROSCSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCSEL_SHIFT)) & SCG_ROSCCSR_ROSCSEL_MASK)
+#define SCG_ROSCCSR_ROSCERR_MASK                 (0x4000000U)
+#define SCG_ROSCCSR_ROSCERR_SHIFT                (26U)
+/*! ROSCERR - RTC OSC Clock Error
+ *  0b0..RTC OSC Clock Monitor is disabled or has not detected an error
+ *  0b1..RTC OSC Clock Monitor is enabled and detected an RTC loss of clock error
+ */
+#define SCG_ROSCCSR_ROSCERR(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCERR_SHIFT)) & SCG_ROSCCSR_ROSCERR_MASK)
+/*! @} */
+
+/*! @name LPFLLCSR - Low Power FLL Control Status Register */
+/*! @{ */
+#define SCG_LPFLLCSR_LPFLLEN_MASK                (0x1U)
+#define SCG_LPFLLCSR_LPFLLEN_SHIFT               (0U)
+/*! LPFLLEN - LPFLL Enable
+ *  0b0..LPFLL is disabled
+ *  0b1..LPFLL is enabled
+ */
+#define SCG_LPFLLCSR_LPFLLEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLEN_SHIFT)) & SCG_LPFLLCSR_LPFLLEN_MASK)
+#define SCG_LPFLLCSR_LPFLLSTEN_MASK              (0x2U)
+#define SCG_LPFLLCSR_LPFLLSTEN_SHIFT             (1U)
+/*! LPFLLSTEN - LPFLL Stop Enable
+ *  0b0..LPFLL is disabled in Stop modes.
+ *  0b1..LPFLL is enabled in Stop modes
+ */
+#define SCG_LPFLLCSR_LPFLLSTEN(x)                (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLSTEN_SHIFT)) & SCG_LPFLLCSR_LPFLLSTEN_MASK)
+#define SCG_LPFLLCSR_LPFLLTREN_MASK              (0x100U)
+#define SCG_LPFLLCSR_LPFLLTREN_SHIFT             (8U)
+/*! LPFLLTREN - LPFLL Trim Enable
+ *  0b0..Disable trimming LPFLL to an reference clock source
+ *  0b1..Enable trimming LPFLL to an reference clock source
+ */
+#define SCG_LPFLLCSR_LPFLLTREN(x)                (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLTREN_SHIFT)) & SCG_LPFLLCSR_LPFLLTREN_MASK)
+#define SCG_LPFLLCSR_LPFLLTRUP_MASK              (0x200U)
+#define SCG_LPFLLCSR_LPFLLTRUP_SHIFT             (9U)
+/*! LPFLLTRUP - LPFLL Trim Update
+ *  0b0..Disable LPFLL trimming updates. LPFLL frequency determined by AUTOTRIM written value.
+ *  0b1..Enable LPFLL trimming updates. LPFLL frequency determined by reference clock multiplication
+ */
+#define SCG_LPFLLCSR_LPFLLTRUP(x)                (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLTRUP_SHIFT)) & SCG_LPFLLCSR_LPFLLTRUP_MASK)
+#define SCG_LPFLLCSR_LPFLLTRMLOCK_MASK           (0x400U)
+#define SCG_LPFLLCSR_LPFLLTRMLOCK_SHIFT          (10U)
+/*! LPFLLTRMLOCK - LPFLL Trim LOCK
+ *  0b0..LPFLL not Locked
+ *  0b1..LPFLL trimmed and Locked
+ */
+#define SCG_LPFLLCSR_LPFLLTRMLOCK(x)             (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLTRMLOCK_SHIFT)) & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK)
+#define SCG_LPFLLCSR_LPFLLCM_MASK                (0x10000U)
+#define SCG_LPFLLCSR_LPFLLCM_SHIFT               (16U)
+/*! LPFLLCM - LPFLL Clock Monitor
+ *  0b0..LPFLL Clock Monitor is disabled
+ *  0b1..LPFLL Clock Monitor is enabled
+ */
+#define SCG_LPFLLCSR_LPFLLCM(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLCM_SHIFT)) & SCG_LPFLLCSR_LPFLLCM_MASK)
+#define SCG_LPFLLCSR_LPFLLCMRE_MASK              (0x20000U)
+#define SCG_LPFLLCSR_LPFLLCMRE_SHIFT             (17U)
+/*! LPFLLCMRE - LPFLL Clock Monitor Reset Enable
+ *  0b0..Clock Monitor generates interrupt when error detected
+ *  0b1..Clock Monitor generates reset when error detected
+ */
+#define SCG_LPFLLCSR_LPFLLCMRE(x)                (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLCMRE_SHIFT)) & SCG_LPFLLCSR_LPFLLCMRE_MASK)
+#define SCG_LPFLLCSR_LK_MASK                     (0x800000U)
+#define SCG_LPFLLCSR_LK_SHIFT                    (23U)
+/*! LK - Lock Register
+ *  0b0..Control Status Register can be written.
+ *  0b1..Control Status Register cannot be written.
+ */
+#define SCG_LPFLLCSR_LK(x)                       (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LK_SHIFT)) & SCG_LPFLLCSR_LK_MASK)
+#define SCG_LPFLLCSR_LPFLLVLD_MASK               (0x1000000U)
+#define SCG_LPFLLCSR_LPFLLVLD_SHIFT              (24U)
+/*! LPFLLVLD - LPFLL Valid
+ *  0b0..LPFLL is not enabled or clock is not valid.
+ *  0b1..LPFLL is enabled and output clock is valid.
+ */
+#define SCG_LPFLLCSR_LPFLLVLD(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLVLD_SHIFT)) & SCG_LPFLLCSR_LPFLLVLD_MASK)
+#define SCG_LPFLLCSR_LPFLLSEL_MASK               (0x2000000U)
+#define SCG_LPFLLCSR_LPFLLSEL_SHIFT              (25U)
+/*! LPFLLSEL - LPFLL Selected
+ *  0b0..LPFLL is not the system clock source
+ *  0b1..LPFLL is the system clock source
+ */
+#define SCG_LPFLLCSR_LPFLLSEL(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLSEL_SHIFT)) & SCG_LPFLLCSR_LPFLLSEL_MASK)
+#define SCG_LPFLLCSR_LPFLLERR_MASK               (0x4000000U)
+#define SCG_LPFLLCSR_LPFLLERR_SHIFT              (26U)
+/*! LPFLLERR - LPFLL Clock Error
+ *  0b0..Error not detected with the LPFLL trimming.
+ *  0b1..Error detected with the LPFLL trimming.
+ */
+#define SCG_LPFLLCSR_LPFLLERR(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLERR_SHIFT)) & SCG_LPFLLCSR_LPFLLERR_MASK)
+/*! @} */
+
+/*! @name LPFLLDIV - Low Power FLL Divide Register */
+/*! @{ */
+#define SCG_LPFLLDIV_LPFLLDIV1_MASK              (0x7U)
+#define SCG_LPFLLDIV_LPFLLDIV1_SHIFT             (0U)
+/*! LPFLLDIV1 - LPFLL Clock Divide 1
+ *  0b000..Output disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_LPFLLDIV_LPFLLDIV1(x)                (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLDIV_LPFLLDIV1_SHIFT)) & SCG_LPFLLDIV_LPFLLDIV1_MASK)
+#define SCG_LPFLLDIV_LPFLLDIV2_MASK              (0x700U)
+#define SCG_LPFLLDIV_LPFLLDIV2_SHIFT             (8U)
+/*! LPFLLDIV2 - LPFLL Clock Divide 2
+ *  0b000..Output disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_LPFLLDIV_LPFLLDIV2(x)                (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLDIV_LPFLLDIV2_SHIFT)) & SCG_LPFLLDIV_LPFLLDIV2_MASK)
+#define SCG_LPFLLDIV_LPFLLDIV3_MASK              (0x70000U)
+#define SCG_LPFLLDIV_LPFLLDIV3_SHIFT             (16U)
+/*! LPFLLDIV3 - LPFLL Clock Divide 3
+ *  0b000..Clock disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_LPFLLDIV_LPFLLDIV3(x)                (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLDIV_LPFLLDIV3_SHIFT)) & SCG_LPFLLDIV_LPFLLDIV3_MASK)
+/*! @} */
+
+/*! @name LPFLLCFG - Low Power FLL Configuration Register */
+/*! @{ */
+#define SCG_LPFLLCFG_FSEL_MASK                   (0x3U)
+#define SCG_LPFLLCFG_FSEL_SHIFT                  (0U)
+/*! FSEL - Frequency Select
+ *  0b00..LPFLL is trimmed to 48 MHz.
+ *  0b01..LPFLL is trimmed to 72 MHz.
+ *  0b10..Reserved
+ *  0b11..Reserved
+ */
+#define SCG_LPFLLCFG_FSEL(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCFG_FSEL_SHIFT)) & SCG_LPFLLCFG_FSEL_MASK)
+/*! @} */
+
+/*! @name LPFLLTCFG - Low Power FLL Trim Configuration Register */
+/*! @{ */
+#define SCG_LPFLLTCFG_TRIMSRC_MASK               (0x3U)
+#define SCG_LPFLLTCFG_TRIMSRC_SHIFT              (0U)
+/*! TRIMSRC - Trim Source
+ *  0b00..SIRC
+ *  0b01..FIRC
+ *  0b10..System OSC
+ *  0b11..RTC OSC
+ */
+#define SCG_LPFLLTCFG_TRIMSRC(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLTCFG_TRIMSRC_SHIFT)) & SCG_LPFLLTCFG_TRIMSRC_MASK)
+#define SCG_LPFLLTCFG_TRIMDIV_MASK               (0x1F00U)
+#define SCG_LPFLLTCFG_TRIMDIV_SHIFT              (8U)
+#define SCG_LPFLLTCFG_TRIMDIV(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLTCFG_TRIMDIV_SHIFT)) & SCG_LPFLLTCFG_TRIMDIV_MASK)
+#define SCG_LPFLLTCFG_LOCKW2LSB_MASK             (0x10000U)
+#define SCG_LPFLLTCFG_LOCKW2LSB_SHIFT            (16U)
+/*! LOCKW2LSB - Lock LPFLL with 2 LSBS
+ *  0b0..LPFLL locks within 1LSB (0.4%)
+ *  0b1..LPFLL locks within 2LSB (0.8%)
+ */
+#define SCG_LPFLLTCFG_LOCKW2LSB(x)               (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLTCFG_LOCKW2LSB_SHIFT)) & SCG_LPFLLTCFG_LOCKW2LSB_MASK)
+/*! @} */
+
+/*! @name LPFLLSTAT - Low Power FLL Status Register */
+/*! @{ */
+#define SCG_LPFLLSTAT_AUTOTRIM_MASK              (0xFFU)
+#define SCG_LPFLLSTAT_AUTOTRIM_SHIFT             (0U)
+#define SCG_LPFLLSTAT_AUTOTRIM(x)                (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLSTAT_AUTOTRIM_SHIFT)) & SCG_LPFLLSTAT_AUTOTRIM_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SCG_Register_Masks */
+
+
+/* SCG - Peripheral instance base addresses */
+/** Peripheral SCG base address */
+#define SCG_BASE                                 (0x4002C000u)
+/** Peripheral SCG base pointer */
+#define SCG                                      ((SCG_Type *)SCG_BASE)
+/** Array initializer of SCG peripheral base addresses */
+#define SCG_BASE_ADDRS                           { SCG_BASE }
+/** Array initializer of SCG peripheral base pointers */
+#define SCG_BASE_PTRS                            { SCG }
+/** Interrupt vectors for the SCG peripheral type */
+#define SCG_IRQS                                 { SCG_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SEMA42 Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SEMA42_Peripheral_Access_Layer SEMA42 Peripheral Access Layer
+ * @{
+ */
+
+/** SEMA42 - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t GATE3;                              /**< Gate Register, offset: 0x0 */
+  __IO uint8_t GATE2;                              /**< Gate Register, offset: 0x1 */
+  __IO uint8_t GATE1;                              /**< Gate Register, offset: 0x2 */
+  __IO uint8_t GATE0;                              /**< Gate Register, offset: 0x3 */
+  __IO uint8_t GATE7;                              /**< Gate Register, offset: 0x4 */
+  __IO uint8_t GATE6;                              /**< Gate Register, offset: 0x5 */
+  __IO uint8_t GATE5;                              /**< Gate Register, offset: 0x6 */
+  __IO uint8_t GATE4;                              /**< Gate Register, offset: 0x7 */
+  __IO uint8_t GATE11;                             /**< Gate Register, offset: 0x8 */
+  __IO uint8_t GATE10;                             /**< Gate Register, offset: 0x9 */
+  __IO uint8_t GATE9;                              /**< Gate Register, offset: 0xA */
+  __IO uint8_t GATE8;                              /**< Gate Register, offset: 0xB */
+  __IO uint8_t GATE15;                             /**< Gate Register, offset: 0xC */
+  __IO uint8_t GATE14;                             /**< Gate Register, offset: 0xD */
+  __IO uint8_t GATE13;                             /**< Gate Register, offset: 0xE */
+  __IO uint8_t GATE12;                             /**< Gate Register, offset: 0xF */
+       uint8_t RESERVED_0[50];
+  union {                                          /* offset: 0x42 */
+    __I  uint16_t RSTGT_R;                           /**< Reset Gate Read, offset: 0x42 */
+    __O  uint16_t RSTGT_W;                           /**< Reset Gate Write, offset: 0x42 */
+  };
+} SEMA42_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SEMA42 Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SEMA42_Register_Masks SEMA42 Register Masks
+ * @{
+ */
+
+/*! @name GATE3 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE3_GTFSM_MASK                  (0xFU)
+#define SEMA42_GATE3_GTFSM_SHIFT                 (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE3_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE3_GTFSM_SHIFT)) & SEMA42_GATE3_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE2 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE2_GTFSM_MASK                  (0xFU)
+#define SEMA42_GATE2_GTFSM_SHIFT                 (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE2_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE2_GTFSM_SHIFT)) & SEMA42_GATE2_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE1 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE1_GTFSM_MASK                  (0xFU)
+#define SEMA42_GATE1_GTFSM_SHIFT                 (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE1_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE1_GTFSM_SHIFT)) & SEMA42_GATE1_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE0 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE0_GTFSM_MASK                  (0xFU)
+#define SEMA42_GATE0_GTFSM_SHIFT                 (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE0_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE0_GTFSM_SHIFT)) & SEMA42_GATE0_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE7 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE7_GTFSM_MASK                  (0xFU)
+#define SEMA42_GATE7_GTFSM_SHIFT                 (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE7_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE7_GTFSM_SHIFT)) & SEMA42_GATE7_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE6 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE6_GTFSM_MASK                  (0xFU)
+#define SEMA42_GATE6_GTFSM_SHIFT                 (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE6_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE6_GTFSM_SHIFT)) & SEMA42_GATE6_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE5 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE5_GTFSM_MASK                  (0xFU)
+#define SEMA42_GATE5_GTFSM_SHIFT                 (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE5_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE5_GTFSM_SHIFT)) & SEMA42_GATE5_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE4 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE4_GTFSM_MASK                  (0xFU)
+#define SEMA42_GATE4_GTFSM_SHIFT                 (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE4_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE4_GTFSM_SHIFT)) & SEMA42_GATE4_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE11 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE11_GTFSM_MASK                 (0xFU)
+#define SEMA42_GATE11_GTFSM_SHIFT                (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE11_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE11_GTFSM_SHIFT)) & SEMA42_GATE11_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE10 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE10_GTFSM_MASK                 (0xFU)
+#define SEMA42_GATE10_GTFSM_SHIFT                (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE10_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE10_GTFSM_SHIFT)) & SEMA42_GATE10_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE9 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE9_GTFSM_MASK                  (0xFU)
+#define SEMA42_GATE9_GTFSM_SHIFT                 (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE9_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE9_GTFSM_SHIFT)) & SEMA42_GATE9_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE8 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE8_GTFSM_MASK                  (0xFU)
+#define SEMA42_GATE8_GTFSM_SHIFT                 (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE8_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE8_GTFSM_SHIFT)) & SEMA42_GATE8_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE15 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE15_GTFSM_MASK                 (0xFU)
+#define SEMA42_GATE15_GTFSM_SHIFT                (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE15_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE15_GTFSM_SHIFT)) & SEMA42_GATE15_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE14 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE14_GTFSM_MASK                 (0xFU)
+#define SEMA42_GATE14_GTFSM_SHIFT                (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE14_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE14_GTFSM_SHIFT)) & SEMA42_GATE14_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE13 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE13_GTFSM_MASK                 (0xFU)
+#define SEMA42_GATE13_GTFSM_SHIFT                (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE13_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE13_GTFSM_SHIFT)) & SEMA42_GATE13_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE12 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE12_GTFSM_MASK                 (0xFU)
+#define SEMA42_GATE12_GTFSM_SHIFT                (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE12_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE12_GTFSM_SHIFT)) & SEMA42_GATE12_GTFSM_MASK)
+/*! @} */
+
+/*! @name RSTGT_R - Reset Gate Read */
+/*! @{ */
+#define SEMA42_RSTGT_R_RSTGTN_MASK               (0xFFU)
+#define SEMA42_RSTGT_R_RSTGTN_SHIFT              (0U)
+#define SEMA42_RSTGT_R_RSTGTN(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGTN_SHIFT)) & SEMA42_RSTGT_R_RSTGTN_MASK)
+#define SEMA42_RSTGT_R_RSTGMS_MASK               (0xF00U)
+#define SEMA42_RSTGT_R_RSTGMS_SHIFT              (8U)
+#define SEMA42_RSTGT_R_RSTGMS(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK)
+#define SEMA42_RSTGT_R_RSTGSM_MASK               (0x3000U)
+#define SEMA42_RSTGT_R_RSTGSM_SHIFT              (12U)
+/*! RSTGSM - RSTGSM
+ *  0b00..Idle, waiting for the first data pattern write.
+ *  0b01..Waiting for the second data pattern write.
+ *  0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, this machine returns to the idle (waiting for first data pattern write) state. The "01" state persists for only one clock cycle. Software cannot observe this state.
+ *  0b11..This state encoding is never used and therefore reserved.
+ */
+#define SEMA42_RSTGT_R_RSTGSM(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGSM_SHIFT)) & SEMA42_RSTGT_R_RSTGSM_MASK)
+#define SEMA42_RSTGT_R_ROZ_MASK                  (0xC000U)
+#define SEMA42_RSTGT_R_ROZ_SHIFT                 (14U)
+#define SEMA42_RSTGT_R_ROZ(x)                    (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_ROZ_SHIFT)) & SEMA42_RSTGT_R_ROZ_MASK)
+/*! @} */
+
+/*! @name RSTGT_W - Reset Gate Write */
+/*! @{ */
+#define SEMA42_RSTGT_W_RSTGTN_MASK               (0xFFU)
+#define SEMA42_RSTGT_W_RSTGTN_SHIFT              (0U)
+#define SEMA42_RSTGT_W_RSTGTN(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGTN_SHIFT)) & SEMA42_RSTGT_W_RSTGTN_MASK)
+#define SEMA42_RSTGT_W_RSTGDP_MASK               (0xFF00U)
+#define SEMA42_RSTGT_W_RSTGDP_SHIFT              (8U)
+#define SEMA42_RSTGT_W_RSTGDP(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGDP_SHIFT)) & SEMA42_RSTGT_W_RSTGDP_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SEMA42_Register_Masks */
+
+
+/* SEMA42 - Peripheral instance base addresses */
+/** Peripheral SEMA420 base address */
+#define SEMA420_BASE                             (0x4001B000u)
+/** Peripheral SEMA420 base pointer */
+#define SEMA420                                  ((SEMA42_Type *)SEMA420_BASE)
+/** Peripheral SEMA421 base address */
+#define SEMA421_BASE                             (0x4101B000u)
+/** Peripheral SEMA421 base pointer */
+#define SEMA421                                  ((SEMA42_Type *)SEMA421_BASE)
+/** Array initializer of SEMA42 peripheral base addresses */
+#define SEMA42_BASE_ADDRS                        { SEMA420_BASE, SEMA421_BASE }
+/** Array initializer of SEMA42 peripheral base pointers */
+#define SEMA42_BASE_PTRS                         { SEMA420, SEMA421 }
+
+/*!
+ * @}
+ */ /* end of group SEMA42_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[4];
+  __IO uint32_t CHIPCTRL;                          /**< Chip Control Register, offset: 0x4 */
+       uint8_t RESERVED_1[28];
+  __I  uint32_t SDID;                              /**< System Device Identification Register, offset: 0x24 */
+       uint8_t RESERVED_2[36];
+  __IO uint32_t FCFG1;                             /**< Flash Configuration Register 1, offset: 0x4C */
+  __I  uint32_t FCFG2;                             /**< Flash Configuration Register 2, offset: 0x50 */
+       uint8_t RESERVED_3[4];
+  __I  uint32_t UIDH;                              /**< Unique Identification Register High, offset: 0x58 */
+  __I  uint32_t UIDM;                              /**< Unique Identification Register Mid Middle, offset: 0x5C */
+  __I  uint32_t UIDL;                              /**< Unique Identification Register Mid Low, offset: 0x60 */
+  __I  uint32_t RFADDRL;                           /**< RF Mac Address Low, offset: 0x64 */
+  __I  uint32_t RFADDRH;                           /**< RF MAC Address High, offset: 0x68 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t MISC2;                             /**< MISC2 Register, offset: 0x70 */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/*! @name CHIPCTRL - Chip Control Register */
+/*! @{ */
+#define SIM_CHIPCTRL_FBSL_MASK                   (0x300U)
+#define SIM_CHIPCTRL_FBSL_SHIFT                  (8U)
+/*! FBSL - FLEXBUS security level
+ *  0b00..All off-chip access(instruction and data) via the Flexbus or sdram are disallowed
+ *  0b01..All off-chip access(instruction and data) via the Flexbus or sdram are disallowed
+ *  0b10..off-chip instruction access are disallowed, data access are allowed
+ *  0b11..off-chip instruction access and data access are allowed
+ */
+#define SIM_CHIPCTRL_FBSL(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTRL_FBSL_SHIFT)) & SIM_CHIPCTRL_FBSL_MASK)
+/*! @} */
+
+/*! @name SDID - System Device Identification Register */
+/*! @{ */
+#define SIM_SDID_PINID_MASK                      (0xFU)
+#define SIM_SDID_PINID_SHIFT                     (0U)
+/*! PINID - PINID
+ *  0b1000..176-pin
+ *  0b1101..191-pin
+ */
+#define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
+#define SIM_SDID_DIEID_MASK                      (0xF80U)
+#define SIM_SDID_DIEID_SHIFT                     (7U)
+#define SIM_SDID_DIEID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK                      (0xF000U)
+#define SIM_SDID_REVID_SHIFT                     (12U)
+#define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
+#define SIM_SDID_SERIESID_MASK                   (0xF00000U)
+#define SIM_SDID_SERIESID_SHIFT                  (20U)
+#define SIM_SDID_SERIESID(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK                   (0xF000000U)
+#define SIM_SDID_SUBFAMID_SHIFT                  (24U)
+/*! SUBFAMID - SUBFAMID
+ *  0b0010..02
+ *  0b0011..03
+ *  0b0100..04
+ */
+#define SIM_SDID_SUBFAMID(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMID_MASK                      (0xF0000000U)
+#define SIM_SDID_FAMID_SHIFT                     (28U)
+/*! FAMID - FAMID
+ *  0b0000..RV32M1
+ */
+#define SIM_SDID_FAMID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
+/*! @} */
+
+/*! @name FCFG1 - Flash Configuration Register 1 */
+/*! @{ */
+#define SIM_FCFG1_FLASHDIS_MASK                  (0x1U)
+#define SIM_FCFG1_FLASHDIS_SHIFT                 (0U)
+/*! FLASHDIS - Flash disable
+ *  0b0..Flash is enabled
+ *  0b1..Flash is disabled
+ */
+#define SIM_FCFG1_FLASHDIS(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
+#define SIM_FCFG1_FLASHDOZE_MASK                 (0x2U)
+#define SIM_FCFG1_FLASHDOZE_SHIFT                (1U)
+/*! FLASHDOZE - Flash Doze
+ *  0b0..Flash remains enabled during Doze mode
+ *  0b1..Flash is disabled for the duration of Doze mode
+ */
+#define SIM_FCFG1_FLASHDOZE(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
+#define SIM_FCFG1_FLSAUTODISEN_MASK              (0x4U)
+#define SIM_FCFG1_FLSAUTODISEN_SHIFT             (2U)
+/*! FLSAUTODISEN - Flash auto disable enabled.
+ *  0b0..Disable flash auto disable function
+ *  0b1..Enable flash auto disable function
+ */
+#define SIM_FCFG1_FLSAUTODISEN(x)                (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLSAUTODISEN_SHIFT)) & SIM_FCFG1_FLSAUTODISEN_MASK)
+#define SIM_FCFG1_FLSAUTODISWD_MASK              (0x3FF8U)
+#define SIM_FCFG1_FLSAUTODISWD_SHIFT             (3U)
+#define SIM_FCFG1_FLSAUTODISWD(x)                (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLSAUTODISWD_SHIFT)) & SIM_FCFG1_FLSAUTODISWD_MASK)
+#define SIM_FCFG1_CORE1_SRAMSIZE_MASK            (0xF0000U)
+#define SIM_FCFG1_CORE1_SRAMSIZE_SHIFT           (16U)
+/*! CORE1_SRAMSIZE
+ *  0b1001..CM0+ has 128 KB SRAM
+ */
+#define SIM_FCFG1_CORE1_SRAMSIZE(x)              (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_CORE1_SRAMSIZE_SHIFT)) & SIM_FCFG1_CORE1_SRAMSIZE_MASK)
+#define SIM_FCFG1_CORE0_SRAMSIZE_MASK            (0xF00000U)
+#define SIM_FCFG1_CORE0_SRAMSIZE_SHIFT           (20U)
+/*! CORE0_SRAMSIZE
+ *  0b1010..CM4 has 256 KB SRAM
+ */
+#define SIM_FCFG1_CORE0_SRAMSIZE(x)              (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_CORE0_SRAMSIZE_SHIFT)) & SIM_FCFG1_CORE0_SRAMSIZE_MASK)
+#define SIM_FCFG1_CORE1_PFSIZE_MASK              (0xF000000U)
+#define SIM_FCFG1_CORE1_PFSIZE_SHIFT             (24U)
+/*! CORE1_PFSIZE
+ *  0b1010..CM0+ has 256 KB flash size.
+ */
+#define SIM_FCFG1_CORE1_PFSIZE(x)                (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_CORE1_PFSIZE_SHIFT)) & SIM_FCFG1_CORE1_PFSIZE_MASK)
+#define SIM_FCFG1_CORE0_PFSIZE_MASK              (0xF0000000U)
+#define SIM_FCFG1_CORE0_PFSIZE_SHIFT             (28U)
+/*! CORE0_PFSIZE
+ *  0b1100..CM4 has 1 MB flash size.
+ */
+#define SIM_FCFG1_CORE0_PFSIZE(x)                (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_CORE0_PFSIZE_SHIFT)) & SIM_FCFG1_CORE0_PFSIZE_MASK)
+/*! @} */
+
+/*! @name FCFG2 - Flash Configuration Register 2 */
+/*! @{ */
+#define SIM_FCFG2_MAXADDR2_MASK                  (0x3F0000U)
+#define SIM_FCFG2_MAXADDR2_SHIFT                 (16U)
+#define SIM_FCFG2_MAXADDR2(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR2_SHIFT)) & SIM_FCFG2_MAXADDR2_MASK)
+#define SIM_FCFG2_MAXADDR01_MASK                 (0x7F000000U)
+#define SIM_FCFG2_MAXADDR01_SHIFT                (24U)
+#define SIM_FCFG2_MAXADDR01(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR01_SHIFT)) & SIM_FCFG2_MAXADDR01_MASK)
+#define SIM_FCFG2_SWAP_MASK                      (0x80000000U)
+#define SIM_FCFG2_SWAP_SHIFT                     (31U)
+/*! SWAP - SWAP
+ *  0b0..Logical P-flash Block 0 is located at relative address 0x0000
+ *  0b1..Logical P-flash Block 1 is located at relative address 0x0000
+ */
+#define SIM_FCFG2_SWAP(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_SWAP_SHIFT)) & SIM_FCFG2_SWAP_MASK)
+/*! @} */
+
+/*! @name UIDH - Unique Identification Register High */
+/*! @{ */
+#define SIM_UIDH_UID_MASK                        (0xFFFFU)
+#define SIM_UIDH_UID_SHIFT                       (0U)
+#define SIM_UIDH_UID(x)                          (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
+/*! @} */
+
+/*! @name UIDM - Unique Identification Register Mid Middle */
+/*! @{ */
+#define SIM_UIDM_UID_MASK                        (0xFFFFFFFFU)
+#define SIM_UIDM_UID_SHIFT                       (0U)
+#define SIM_UIDM_UID(x)                          (((uint32_t)(((uint32_t)(x)) << SIM_UIDM_UID_SHIFT)) & SIM_UIDM_UID_MASK)
+/*! @} */
+
+/*! @name UIDL - Unique Identification Register Mid Low */
+/*! @{ */
+#define SIM_UIDL_UID_MASK                        (0xFFFFFFFFU)
+#define SIM_UIDL_UID_SHIFT                       (0U)
+#define SIM_UIDL_UID(x)                          (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
+/*! @} */
+
+/*! @name RFADDRL - RF Mac Address Low */
+/*! @{ */
+#define SIM_RFADDRL_MACADDR0_MASK                (0xFFU)
+#define SIM_RFADDRL_MACADDR0_SHIFT               (0U)
+#define SIM_RFADDRL_MACADDR0(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_RFADDRL_MACADDR0_SHIFT)) & SIM_RFADDRL_MACADDR0_MASK)
+#define SIM_RFADDRL_MACADDR1_MASK                (0xFF00U)
+#define SIM_RFADDRL_MACADDR1_SHIFT               (8U)
+#define SIM_RFADDRL_MACADDR1(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_RFADDRL_MACADDR1_SHIFT)) & SIM_RFADDRL_MACADDR1_MASK)
+#define SIM_RFADDRL_MACADDR2_MASK                (0xFF0000U)
+#define SIM_RFADDRL_MACADDR2_SHIFT               (16U)
+#define SIM_RFADDRL_MACADDR2(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_RFADDRL_MACADDR2_SHIFT)) & SIM_RFADDRL_MACADDR2_MASK)
+#define SIM_RFADDRL_MACADDR3_MASK                (0xFF000000U)
+#define SIM_RFADDRL_MACADDR3_SHIFT               (24U)
+#define SIM_RFADDRL_MACADDR3(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_RFADDRL_MACADDR3_SHIFT)) & SIM_RFADDRL_MACADDR3_MASK)
+/*! @} */
+
+/*! @name RFADDRH - RF MAC Address High */
+/*! @{ */
+#define SIM_RFADDRH_MACADDR4_MASK                (0xFFU)
+#define SIM_RFADDRH_MACADDR4_SHIFT               (0U)
+#define SIM_RFADDRH_MACADDR4(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_RFADDRH_MACADDR4_SHIFT)) & SIM_RFADDRH_MACADDR4_MASK)
+/*! @} */
+
+/*! @name MISC2 - MISC2 Register */
+/*! @{ */
+#define SIM_MISC2_SYSTICK_CLK_EN_MASK            (0x1U)
+#define SIM_MISC2_SYSTICK_CLK_EN_SHIFT           (0U)
+/*! systick_clk_en - Systick clock enable
+ *  0b0..Systick clock is disabled
+ *  0b1..Systick clock is enabled
+ */
+#define SIM_MISC2_SYSTICK_CLK_EN(x)              (((uint32_t)(((uint32_t)(x)) << SIM_MISC2_SYSTICK_CLK_EN_SHIFT)) & SIM_MISC2_SYSTICK_CLK_EN_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE                                 (0x40026000u)
+/** Peripheral SIM base pointer */
+#define SIM                                      ((SIM_Type *)SIM_BASE)
+/** Array initializer of SIM peripheral base addresses */
+#define SIM_BASE_ADDRS                           { SIM_BASE }
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASE_PTRS                            { SIM }
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __IO uint32_t PMPROT;                            /**< Power Mode Protection register, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t PMCTRL;                            /**< Power Mode Control register, offset: 0x10 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t PMSTAT;                            /**< Power Mode Status register, offset: 0x18 */
+       uint8_t RESERVED_2[4];
+  __I  uint32_t SRS;                               /**< System Reset Status, offset: 0x20 */
+  __IO uint32_t RPC;                               /**< Reset Pin Control, offset: 0x24 */
+  __IO uint32_t SSRS;                              /**< Sticky System Reset Status, offset: 0x28 */
+  __IO uint32_t SRIE;                              /**< System Reset Interrupt Enable, offset: 0x2C */
+  __IO uint32_t SRIF;                              /**< System Reset Interrupt Flag, offset: 0x30 */
+       uint8_t RESERVED_3[12];
+  __IO uint32_t MR;                                /**< Mode Register, offset: 0x40 */
+       uint8_t RESERVED_4[12];
+  __IO uint32_t FM;                                /**< Force Mode Register, offset: 0x50 */
+       uint8_t RESERVED_5[12];
+  __IO uint32_t SRAMLPR;                           /**< SRAM Low Power Register, offset: 0x60 */
+  __IO uint32_t SRAMDSR;                           /**< SRAM Deep Sleep Register, offset: 0x64 */
+} SMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define SMC_VERID_FEATURE_MASK                   (0xFFFFU)
+#define SMC_VERID_FEATURE_SHIFT                  (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000010101011..Default features supported
+ */
+#define SMC_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << SMC_VERID_FEATURE_SHIFT)) & SMC_VERID_FEATURE_MASK)
+#define SMC_VERID_MINOR_MASK                     (0xFF0000U)
+#define SMC_VERID_MINOR_SHIFT                    (16U)
+#define SMC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_VERID_MINOR_SHIFT)) & SMC_VERID_MINOR_MASK)
+#define SMC_VERID_MAJOR_MASK                     (0xFF000000U)
+#define SMC_VERID_MAJOR_SHIFT                    (24U)
+#define SMC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_VERID_MAJOR_SHIFT)) & SMC_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define SMC_PARAM_PWRD_INDPT_MASK                (0x1U)
+#define SMC_PARAM_PWRD_INDPT_SHIFT               (0U)
+#define SMC_PARAM_PWRD_INDPT(x)                  (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_PWRD_INDPT_SHIFT)) & SMC_PARAM_PWRD_INDPT_MASK)
+/*! @} */
+
+/*! @name PMPROT - Power Mode Protection register */
+/*! @{ */
+#define SMC_PMPROT_AVLLS_MASK                    (0x3U)
+#define SMC_PMPROT_AVLLS_SHIFT                   (0U)
+/*! AVLLS - Allow Very-Low-Leakage Stop Mode
+ *  0b00..VLLS mode is not allowed
+ *  0b01..VLLS0/1 mode is allowed
+ *  0b10..VLLS2/3 mode is allowed
+ *  0b11..VLLS0/1/2/3 mode is allowed
+ */
+#define SMC_PMPROT_AVLLS(x)                      (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
+#define SMC_PMPROT_ALLS_MASK                     (0x8U)
+#define SMC_PMPROT_ALLS_SHIFT                    (3U)
+/*! ALLS - Allow Low-Leakage Stop Mode
+ *  0b0..LLS is not allowed
+ *  0b1..LLS is allowed
+ */
+#define SMC_PMPROT_ALLS(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
+#define SMC_PMPROT_AVLP_MASK                     (0x20U)
+#define SMC_PMPROT_AVLP_SHIFT                    (5U)
+/*! AVLP - Allow Very-Low-Power Modes
+ *  0b0..VLPR, VLPW, and VLPS are not allowed.
+ *  0b1..VLPR, VLPW, and VLPS are allowed.
+ */
+#define SMC_PMPROT_AVLP(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
+#define SMC_PMPROT_AHSRUN_MASK                   (0x80U)
+#define SMC_PMPROT_AHSRUN_SHIFT                  (7U)
+/*! AHSRUN - Allow High Speed Run mode
+ *  0b0..HSRUN is not allowed
+ *  0b1..HSRUN is allowed
+ */
+#define SMC_PMPROT_AHSRUN(x)                     (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK)
+/*! @} */
+
+/*! @name PMCTRL - Power Mode Control register */
+/*! @{ */
+#define SMC_PMCTRL_STOPM_MASK                    (0x7U)
+#define SMC_PMCTRL_STOPM_SHIFT                   (0U)
+/*! STOPM - Stop Mode Control
+ *  0b000..Normal Stop (STOP)
+ *  0b001..Reserved
+ *  0b010..Very-Low-Power Stop (VLPS)
+ *  0b011..Low-Leakage Stop (LLS)
+ *  0b100..Very-Low-Leakage Stop with SRAM retention(VLLS2/3)
+ *  0b101..Reserved
+ *  0b110..Very-Low-Leakage Stop without SRAM retention (VLLS0/1)
+ *  0b111..Reserved
+ */
+#define SMC_PMCTRL_STOPM(x)                      (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_RUNM_MASK                     (0x300U)
+#define SMC_PMCTRL_RUNM_SHIFT                    (8U)
+/*! RUNM - Run Mode Control
+ *  0b00..Normal Run mode (RUN)
+ *  0b01..Reserved
+ *  0b10..Very-Low-Power Run mode (VLPR)
+ *  0b11..High Speed Run mode (HSRUN)
+ */
+#define SMC_PMCTRL_RUNM(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
+#define SMC_PMCTRL_PSTOPO_MASK                   (0x30000U)
+#define SMC_PMCTRL_PSTOPO_SHIFT                  (16U)
+/*! PSTOPO - Partial Stop Option
+ *  0b00..STOP - Normal Stop mode
+ *  0b01..PSTOP1 - Partial Stop with system and bus clock disabled
+ *  0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
+ *  0b11..PSTOP3 - Partial Stop with system clock enabled and bus clock enabled
+ */
+#define SMC_PMCTRL_PSTOPO(x)                     (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_PSTOPO_SHIFT)) & SMC_PMCTRL_PSTOPO_MASK)
+/*! @} */
+
+/*! @name PMSTAT - Power Mode Status register */
+/*! @{ */
+#define SMC_PMSTAT_PMSTAT_MASK                   (0xFFU)
+#define SMC_PMSTAT_PMSTAT_SHIFT                  (0U)
+/*! PMSTAT - Power Mode Status
+ *  0b00000001..Current power mode is RUN.
+ *  0b00000010..Current power mode is any STOP mode.
+ *  0b00000100..Current power mode is VLPR.
+ *  0b10000000..Current power mode is HSRUN
+ */
+#define SMC_PMSTAT_PMSTAT(x)                     (((uint32_t)(((uint32_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
+#define SMC_PMSTAT_STOPSTAT_MASK                 (0xFF000000U)
+#define SMC_PMSTAT_STOPSTAT_SHIFT                (24U)
+#define SMC_PMSTAT_STOPSTAT(x)                   (((uint32_t)(((uint32_t)(x)) << SMC_PMSTAT_STOPSTAT_SHIFT)) & SMC_PMSTAT_STOPSTAT_MASK)
+/*! @} */
+
+/*! @name SRS - System Reset Status */
+/*! @{ */
+#define SMC_SRS_WAKEUP_MASK                      (0x1U)
+#define SMC_SRS_WAKEUP_SHIFT                     (0U)
+/*! WAKEUP - Wakeup Reset
+ *  0b0..Reset not generated by wakeup from VLLS mode.
+ *  0b1..Reset generated by wakeup from VLLS mode.
+ */
+#define SMC_SRS_WAKEUP(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_SRS_WAKEUP_SHIFT)) & SMC_SRS_WAKEUP_MASK)
+#define SMC_SRS_POR_MASK                         (0x2U)
+#define SMC_SRS_POR_SHIFT                        (1U)
+/*! POR - POR Reset
+ *  0b0..Reset not generated by POR.
+ *  0b1..Reset generated by POR.
+ */
+#define SMC_SRS_POR(x)                           (((uint32_t)(((uint32_t)(x)) << SMC_SRS_POR_SHIFT)) & SMC_SRS_POR_MASK)
+#define SMC_SRS_LVD_MASK                         (0x4U)
+#define SMC_SRS_LVD_SHIFT                        (2U)
+/*! LVD - LVD Reset
+ *  0b0..Reset not generated by LVD.
+ *  0b1..Reset generated by LVD.
+ */
+#define SMC_SRS_LVD(x)                           (((uint32_t)(((uint32_t)(x)) << SMC_SRS_LVD_SHIFT)) & SMC_SRS_LVD_MASK)
+#define SMC_SRS_HVD_MASK                         (0x8U)
+#define SMC_SRS_HVD_SHIFT                        (3U)
+/*! HVD - HVD Reset
+ *  0b0..Reset not generated by HVD.
+ *  0b1..Reset generated by HVD.
+ */
+#define SMC_SRS_HVD(x)                           (((uint32_t)(((uint32_t)(x)) << SMC_SRS_HVD_SHIFT)) & SMC_SRS_HVD_MASK)
+#define SMC_SRS_WARM_MASK                        (0x10U)
+#define SMC_SRS_WARM_SHIFT                       (4U)
+/*! WARM - Warm Reset
+ *  0b0..Reset not generated by Warm Reset source.
+ *  0b1..Reset generated by Warm Reset source.
+ */
+#define SMC_SRS_WARM(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SRS_WARM_SHIFT)) & SMC_SRS_WARM_MASK)
+#define SMC_SRS_FATAL_MASK                       (0x20U)
+#define SMC_SRS_FATAL_SHIFT                      (5U)
+/*! FATAL - Fatal Reset
+ *  0b0..Reset was not generated by a fatal reset source.
+ *  0b1..Reset was generated by a fatal reset source.
+ */
+#define SMC_SRS_FATAL(x)                         (((uint32_t)(((uint32_t)(x)) << SMC_SRS_FATAL_SHIFT)) & SMC_SRS_FATAL_MASK)
+#define SMC_SRS_CORE_MASK                        (0x80U)
+#define SMC_SRS_CORE_SHIFT                       (7U)
+/*! CORE - Core Reset
+ *  0b0..Reset source was not core only reset.
+ *  0b1..Reset source was core reset and reset the core only.
+ */
+#define SMC_SRS_CORE(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SRS_CORE_SHIFT)) & SMC_SRS_CORE_MASK)
+#define SMC_SRS_PIN_MASK                         (0x100U)
+#define SMC_SRS_PIN_SHIFT                        (8U)
+/*! PIN - Pin Reset
+ *  0b0..Reset was not generated from the assertion of RESET_B pin.
+ *  0b1..Reset was generated from the assertion of RESET_B pin.
+ */
+#define SMC_SRS_PIN(x)                           (((uint32_t)(((uint32_t)(x)) << SMC_SRS_PIN_SHIFT)) & SMC_SRS_PIN_MASK)
+#define SMC_SRS_MDM_MASK                         (0x200U)
+#define SMC_SRS_MDM_SHIFT                        (9U)
+/*! MDM - MDM Reset
+ *  0b0..Reset was not generated from the MDM reset request.
+ *  0b1..Reset was generated from the MDM reset request.
+ */
+#define SMC_SRS_MDM(x)                           (((uint32_t)(((uint32_t)(x)) << SMC_SRS_MDM_SHIFT)) & SMC_SRS_MDM_MASK)
+#define SMC_SRS_RSTACK_MASK                      (0x400U)
+#define SMC_SRS_RSTACK_SHIFT                     (10U)
+/*! RSTACK - Reset Timeout
+ *  0b0..Reset not generated from Reset Controller Timeout.
+ *  0b1..Reset generated from Reset Controller Timeout.
+ */
+#define SMC_SRS_RSTACK(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_SRS_RSTACK_SHIFT)) & SMC_SRS_RSTACK_MASK)
+#define SMC_SRS_STOPACK_MASK                     (0x800U)
+#define SMC_SRS_STOPACK_SHIFT                    (11U)
+/*! STOPACK - Stop Timeout Reset
+ *  0b0..Reset not generated by Stop Controller Timeout.
+ *  0b1..Reset generated by Stop Controller Timeout.
+ */
+#define SMC_SRS_STOPACK(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_SRS_STOPACK_SHIFT)) & SMC_SRS_STOPACK_MASK)
+#define SMC_SRS_SCG_MASK                         (0x1000U)
+#define SMC_SRS_SCG_SHIFT                        (12U)
+/*! SCG - SCG Reset
+ *  0b0..Reset is not generated from an SCG loss of lock or loss of clock.
+ *  0b1..Reset is generated from an SCG loss of lock or loss of clock.
+ */
+#define SMC_SRS_SCG(x)                           (((uint32_t)(((uint32_t)(x)) << SMC_SRS_SCG_SHIFT)) & SMC_SRS_SCG_MASK)
+#define SMC_SRS_WDOG_MASK                        (0x2000U)
+#define SMC_SRS_WDOG_SHIFT                       (13U)
+/*! WDOG - Watchdog Reset
+ *  0b0..Reset is not generated from the WatchDog timeout.
+ *  0b1..Reset is generated from the WatchDog timeout.
+ */
+#define SMC_SRS_WDOG(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SRS_WDOG_SHIFT)) & SMC_SRS_WDOG_MASK)
+#define SMC_SRS_SW_MASK                          (0x4000U)
+#define SMC_SRS_SW_SHIFT                         (14U)
+/*! SW - Software Reset
+ *  0b0..Reset not generated by software request from core.
+ *  0b1..Reset generated by software request from core.
+ */
+#define SMC_SRS_SW(x)                            (((uint32_t)(((uint32_t)(x)) << SMC_SRS_SW_SHIFT)) & SMC_SRS_SW_MASK)
+#define SMC_SRS_LOCKUP_MASK                      (0x8000U)
+#define SMC_SRS_LOCKUP_SHIFT                     (15U)
+/*! LOCKUP - Lockup Reset
+ *  0b0..Reset not generated by core lockup or exception.
+ *  0b1..Reset generated by core lockup or exception.
+ */
+#define SMC_SRS_LOCKUP(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_SRS_LOCKUP_SHIFT)) & SMC_SRS_LOCKUP_MASK)
+#define SMC_SRS_CORE0_MASK                       (0x10000U)
+#define SMC_SRS_CORE0_SHIFT                      (16U)
+/*! CORE0 - Core0 System Reset
+ *  0b0..Reset not generated from Core0 system reset source.
+ *  0b1..Reset generated from Core0 system reset source.
+ */
+#define SMC_SRS_CORE0(x)                         (((uint32_t)(((uint32_t)(x)) << SMC_SRS_CORE0_SHIFT)) & SMC_SRS_CORE0_MASK)
+#define SMC_SRS_CORE1_MASK                       (0x20000U)
+#define SMC_SRS_CORE1_SHIFT                      (17U)
+/*! CORE1 - Core1 System Reset
+ *  0b0..Reset not generated from Core1 system reset source.
+ *  0b1..Reset generated from Core1 system reset source.
+ */
+#define SMC_SRS_CORE1(x)                         (((uint32_t)(((uint32_t)(x)) << SMC_SRS_CORE1_SHIFT)) & SMC_SRS_CORE1_MASK)
+#define SMC_SRS_JTAG_MASK                        (0x10000000U)
+#define SMC_SRS_JTAG_SHIFT                       (28U)
+/*! JTAG - JTAG System Reset
+ *  0b0..Reset not generated by JTAG system reset.
+ *  0b1..Reset generated by JTAG system reset.
+ */
+#define SMC_SRS_JTAG(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SRS_JTAG_SHIFT)) & SMC_SRS_JTAG_MASK)
+/*! @} */
+
+/*! @name RPC - Reset Pin Control */
+/*! @{ */
+#define SMC_RPC_FILTCFG_MASK                     (0x1FU)
+#define SMC_RPC_FILTCFG_SHIFT                    (0U)
+#define SMC_RPC_FILTCFG(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_RPC_FILTCFG_SHIFT)) & SMC_RPC_FILTCFG_MASK)
+#define SMC_RPC_FILTEN_MASK                      (0x100U)
+#define SMC_RPC_FILTEN_SHIFT                     (8U)
+/*! FILTEN - Filter Enable
+ *  0b0..Slow clock reset pin filter disabled.
+ *  0b1..Slow clock reset pin filter enabled in Run modes.
+ */
+#define SMC_RPC_FILTEN(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_RPC_FILTEN_SHIFT)) & SMC_RPC_FILTEN_MASK)
+#define SMC_RPC_LPOFEN_MASK                      (0x200U)
+#define SMC_RPC_LPOFEN_SHIFT                     (9U)
+/*! LPOFEN - LPO Filter Enable
+ *  0b0..LPO clock reset pin filter disabled.
+ *  0b1..LPO clock reset pin filter enabled in all modes.
+ */
+#define SMC_RPC_LPOFEN(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_RPC_LPOFEN_SHIFT)) & SMC_RPC_LPOFEN_MASK)
+/*! @} */
+
+/*! @name SSRS - Sticky System Reset Status */
+/*! @{ */
+#define SMC_SSRS_WAKEUP_MASK                     (0x1U)
+#define SMC_SSRS_WAKEUP_SHIFT                    (0U)
+/*! WAKEUP - Wakeup Reset
+ *  0b0..Reset not generated by wakeup from VLLS mode.
+ *  0b1..Reset generated by wakeup from VLLS mode.
+ */
+#define SMC_SSRS_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_WAKEUP_SHIFT)) & SMC_SSRS_WAKEUP_MASK)
+#define SMC_SSRS_POR_MASK                        (0x2U)
+#define SMC_SSRS_POR_SHIFT                       (1U)
+/*! POR - POR Reset
+ *  0b0..Reset not generated by POR.
+ *  0b1..Reset generated by POR.
+ */
+#define SMC_SSRS_POR(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_POR_SHIFT)) & SMC_SSRS_POR_MASK)
+#define SMC_SSRS_LVD_MASK                        (0x4U)
+#define SMC_SSRS_LVD_SHIFT                       (2U)
+/*! LVD - LVD Reset
+ *  0b0..Reset not generated by LVD.
+ *  0b1..Reset generated by LVD.
+ */
+#define SMC_SSRS_LVD(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_LVD_SHIFT)) & SMC_SSRS_LVD_MASK)
+#define SMC_SSRS_HVD_MASK                        (0x8U)
+#define SMC_SSRS_HVD_SHIFT                       (3U)
+/*! HVD - HVD Reset
+ *  0b0..Reset not generated by HVD.
+ *  0b1..Reset generated by HVD.
+ */
+#define SMC_SSRS_HVD(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_HVD_SHIFT)) & SMC_SSRS_HVD_MASK)
+#define SMC_SSRS_WARM_MASK                       (0x10U)
+#define SMC_SSRS_WARM_SHIFT                      (4U)
+/*! WARM - Warm Reset
+ *  0b0..Reset not generated by system reset source.
+ *  0b1..Reset generated by system reset source.
+ */
+#define SMC_SSRS_WARM(x)                         (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_WARM_SHIFT)) & SMC_SSRS_WARM_MASK)
+#define SMC_SSRS_FATAL_MASK                      (0x20U)
+#define SMC_SSRS_FATAL_SHIFT                     (5U)
+/*! FATAL - Fatal Reset
+ *  0b0..Reset was not generated by a fatal reset source.
+ *  0b1..Reset was generated by a fatal reset source.
+ */
+#define SMC_SSRS_FATAL(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_FATAL_SHIFT)) & SMC_SSRS_FATAL_MASK)
+#define SMC_SSRS_PIN_MASK                        (0x100U)
+#define SMC_SSRS_PIN_SHIFT                       (8U)
+/*! PIN - Pin Reset
+ *  0b0..Reset was not generated from the RESET_B pin.
+ *  0b1..Reset was generated from the RESET_B pin.
+ */
+#define SMC_SSRS_PIN(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_PIN_SHIFT)) & SMC_SSRS_PIN_MASK)
+#define SMC_SSRS_MDM_MASK                        (0x200U)
+#define SMC_SSRS_MDM_SHIFT                       (9U)
+/*! MDM - MDM Reset
+ *  0b0..Reset was not generated from the MDM reset request.
+ *  0b1..Reset was generated from the MDM reset request.
+ */
+#define SMC_SSRS_MDM(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_MDM_SHIFT)) & SMC_SSRS_MDM_MASK)
+#define SMC_SSRS_RSTACK_MASK                     (0x400U)
+#define SMC_SSRS_RSTACK_SHIFT                    (10U)
+/*! RSTACK - Reset Timeout
+ *  0b0..Reset not generated from Reset Controller Timeout.
+ *  0b1..Reset generated from Reset Controller Timeout.
+ */
+#define SMC_SSRS_RSTACK(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_RSTACK_SHIFT)) & SMC_SSRS_RSTACK_MASK)
+#define SMC_SSRS_STOPACK_MASK                    (0x800U)
+#define SMC_SSRS_STOPACK_SHIFT                   (11U)
+/*! STOPACK - Stop Timeout Reset
+ *  0b0..Reset not generated by Stop Controller Timeout.
+ *  0b1..Reset generated by Stop Controller Timeout.
+ */
+#define SMC_SSRS_STOPACK(x)                      (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_STOPACK_SHIFT)) & SMC_SSRS_STOPACK_MASK)
+#define SMC_SSRS_SCG_MASK                        (0x1000U)
+#define SMC_SSRS_SCG_SHIFT                       (12U)
+/*! SCG - SCG Reset
+ *  0b0..Reset is not generated from an SCG loss of lock or loss of clock.
+ *  0b1..Reset is generated from an SCG loss of lock or loss of clock.
+ */
+#define SMC_SSRS_SCG(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_SCG_SHIFT)) & SMC_SSRS_SCG_MASK)
+#define SMC_SSRS_WDOG_MASK                       (0x2000U)
+#define SMC_SSRS_WDOG_SHIFT                      (13U)
+/*! WDOG - Watchdog Reset
+ *  0b0..Reset is not generated from the WatchDog timeout.
+ *  0b1..Reset is generated from the WatchDog timeout.
+ */
+#define SMC_SSRS_WDOG(x)                         (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_WDOG_SHIFT)) & SMC_SSRS_WDOG_MASK)
+#define SMC_SSRS_SW_MASK                         (0x4000U)
+#define SMC_SSRS_SW_SHIFT                        (14U)
+/*! SW - Software Reset
+ *  0b0..Reset not generated by software request from core.
+ *  0b1..Reset generated by software request from core.
+ */
+#define SMC_SSRS_SW(x)                           (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_SW_SHIFT)) & SMC_SSRS_SW_MASK)
+#define SMC_SSRS_LOCKUP_MASK                     (0x8000U)
+#define SMC_SSRS_LOCKUP_SHIFT                    (15U)
+/*! LOCKUP - Lockup Reset
+ *  0b0..Reset not generated by core lockup.
+ *  0b1..Reset generated by core lockup.
+ */
+#define SMC_SSRS_LOCKUP(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_LOCKUP_SHIFT)) & SMC_SSRS_LOCKUP_MASK)
+#define SMC_SSRS_CORE0_MASK                      (0x10000U)
+#define SMC_SSRS_CORE0_SHIFT                     (16U)
+/*! CORE0 - Core0 Reset
+ *  0b0..Reset not generated from Core0 reset source.
+ *  0b1..Reset generated from Core0 reset source.
+ */
+#define SMC_SSRS_CORE0(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_CORE0_SHIFT)) & SMC_SSRS_CORE0_MASK)
+#define SMC_SSRS_CORE1_MASK                      (0x20000U)
+#define SMC_SSRS_CORE1_SHIFT                     (17U)
+/*! CORE1 - Core1 Reset
+ *  0b0..Reset not generated from Core1 reset source.
+ *  0b1..Reset generated from Core1 reset source.
+ */
+#define SMC_SSRS_CORE1(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_CORE1_SHIFT)) & SMC_SSRS_CORE1_MASK)
+#define SMC_SSRS_JTAG_MASK                       (0x10000000U)
+#define SMC_SSRS_JTAG_SHIFT                      (28U)
+/*! JTAG - JTAG System Reset
+ *  0b0..Reset not generated by JTAG system reset.
+ *  0b1..Reset generated by JTAG system reset.
+ */
+#define SMC_SSRS_JTAG(x)                         (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_JTAG_SHIFT)) & SMC_SSRS_JTAG_MASK)
+/*! @} */
+
+/*! @name SRIE - System Reset Interrupt Enable */
+/*! @{ */
+#define SMC_SRIE_PIN_MASK                        (0x100U)
+#define SMC_SRIE_PIN_SHIFT                       (8U)
+/*! PIN - Pin Reset
+ *  0b0..Interrupt disabled.
+ *  0b1..Interrupt enabled.
+ */
+#define SMC_SRIE_PIN(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_PIN_SHIFT)) & SMC_SRIE_PIN_MASK)
+#define SMC_SRIE_MDM_MASK                        (0x200U)
+#define SMC_SRIE_MDM_SHIFT                       (9U)
+/*! MDM - MDM Reset
+ *  0b0..Interrupt disabled.
+ *  0b1..Interrupt enabled.
+ */
+#define SMC_SRIE_MDM(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_MDM_SHIFT)) & SMC_SRIE_MDM_MASK)
+#define SMC_SRIE_STOPACK_MASK                    (0x800U)
+#define SMC_SRIE_STOPACK_SHIFT                   (11U)
+/*! STOPACK - Stop Timeout Reset
+ *  0b0..Interrupt disabled.
+ *  0b1..Interrupt enabled.
+ */
+#define SMC_SRIE_STOPACK(x)                      (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_STOPACK_SHIFT)) & SMC_SRIE_STOPACK_MASK)
+#define SMC_SRIE_WDOG_MASK                       (0x2000U)
+#define SMC_SRIE_WDOG_SHIFT                      (13U)
+/*! WDOG - Watchdog Reset
+ *  0b0..Interrupt disabled.
+ *  0b1..Interrupt enabled.
+ */
+#define SMC_SRIE_WDOG(x)                         (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_WDOG_SHIFT)) & SMC_SRIE_WDOG_MASK)
+#define SMC_SRIE_SW_MASK                         (0x4000U)
+#define SMC_SRIE_SW_SHIFT                        (14U)
+/*! SW - Software Reset
+ *  0b0..Interrupt disabled.
+ *  0b1..Interrupt enabled.
+ */
+#define SMC_SRIE_SW(x)                           (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_SW_SHIFT)) & SMC_SRIE_SW_MASK)
+#define SMC_SRIE_LOCKUP_MASK                     (0x8000U)
+#define SMC_SRIE_LOCKUP_SHIFT                    (15U)
+/*! LOCKUP - Lockup Reset
+ *  0b0..Interrupt disabled.
+ *  0b1..Interrupt enabled.
+ */
+#define SMC_SRIE_LOCKUP(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_LOCKUP_SHIFT)) & SMC_SRIE_LOCKUP_MASK)
+#define SMC_SRIE_CORE0_MASK                      (0x10000U)
+#define SMC_SRIE_CORE0_SHIFT                     (16U)
+/*! CORE0 - Core0 Reset
+ *  0b0..Interrupt disabled.
+ *  0b1..Interrupt enabled.
+ */
+#define SMC_SRIE_CORE0(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_CORE0_SHIFT)) & SMC_SRIE_CORE0_MASK)
+#define SMC_SRIE_CORE1_MASK                      (0x20000U)
+#define SMC_SRIE_CORE1_SHIFT                     (17U)
+/*! CORE1 - Core1 Reset
+ *  0b0..Interrupt disabled.
+ *  0b1..Interrupt enabled.
+ */
+#define SMC_SRIE_CORE1(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_CORE1_SHIFT)) & SMC_SRIE_CORE1_MASK)
+/*! @} */
+
+/*! @name SRIF - System Reset Interrupt Flag */
+/*! @{ */
+#define SMC_SRIF_PIN_MASK                        (0x100U)
+#define SMC_SRIF_PIN_SHIFT                       (8U)
+/*! PIN - Pin Reset
+ *  0b0..Reset source not pending.
+ *  0b1..Reset source pending.
+ */
+#define SMC_SRIF_PIN(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_PIN_SHIFT)) & SMC_SRIF_PIN_MASK)
+#define SMC_SRIF_MDM_MASK                        (0x200U)
+#define SMC_SRIF_MDM_SHIFT                       (9U)
+/*! MDM - MDM Reset
+ *  0b0..Reset source not pending.
+ *  0b1..Reset source pending.
+ */
+#define SMC_SRIF_MDM(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_MDM_SHIFT)) & SMC_SRIF_MDM_MASK)
+#define SMC_SRIF_STOPACK_MASK                    (0x800U)
+#define SMC_SRIF_STOPACK_SHIFT                   (11U)
+/*! STOPACK - Stop Timeout Reset
+ *  0b0..Reset source not pending.
+ *  0b1..Reset source pending.
+ */
+#define SMC_SRIF_STOPACK(x)                      (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_STOPACK_SHIFT)) & SMC_SRIF_STOPACK_MASK)
+#define SMC_SRIF_WDOG_MASK                       (0x2000U)
+#define SMC_SRIF_WDOG_SHIFT                      (13U)
+/*! WDOG - Watchdog Reset
+ *  0b0..Reset source not pending.
+ *  0b1..Reset source pending.
+ */
+#define SMC_SRIF_WDOG(x)                         (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_WDOG_SHIFT)) & SMC_SRIF_WDOG_MASK)
+#define SMC_SRIF_SW_MASK                         (0x4000U)
+#define SMC_SRIF_SW_SHIFT                        (14U)
+/*! SW - Software Reset
+ *  0b0..Reset source not pending.
+ *  0b1..Reset source pending.
+ */
+#define SMC_SRIF_SW(x)                           (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_SW_SHIFT)) & SMC_SRIF_SW_MASK)
+#define SMC_SRIF_LOCKUP_MASK                     (0x8000U)
+#define SMC_SRIF_LOCKUP_SHIFT                    (15U)
+/*! LOCKUP - Lockup Reset
+ *  0b0..Reset source not pending.
+ *  0b1..Reset source pending.
+ */
+#define SMC_SRIF_LOCKUP(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_LOCKUP_SHIFT)) & SMC_SRIF_LOCKUP_MASK)
+#define SMC_SRIF_CORE0_MASK                      (0x10000U)
+#define SMC_SRIF_CORE0_SHIFT                     (16U)
+/*! CORE0 - Core0 Reset
+ *  0b0..Reset source not pending.
+ *  0b1..Reset source pending.
+ */
+#define SMC_SRIF_CORE0(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_CORE0_SHIFT)) & SMC_SRIF_CORE0_MASK)
+#define SMC_SRIF_CORE1_MASK                      (0x20000U)
+#define SMC_SRIF_CORE1_SHIFT                     (17U)
+/*! CORE1 - Core1 Reset
+ *  0b0..Reset source not pending.
+ *  0b1..Reset source pending.
+ */
+#define SMC_SRIF_CORE1(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_CORE1_SHIFT)) & SMC_SRIF_CORE1_MASK)
+/*! @} */
+
+/*! @name MR - Mode Register */
+/*! @{ */
+#define SMC_MR_BOOTCFG_MASK                      (0x3U)
+#define SMC_MR_BOOTCFG_SHIFT                     (0U)
+/*! BOOTCFG - Boot Configuration
+ *  0b00..Boot from Flash.
+ *  0b01..Boot from ROM due to BOOTCFG0 pin assertion.
+ *  0b10..Boot from ROM due to FOPT configuration.
+ *  0b11..Boot from ROM due to both BOOTCFG0 pin assertion and FOPT configuration.
+ */
+#define SMC_MR_BOOTCFG(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_MR_BOOTCFG_SHIFT)) & SMC_MR_BOOTCFG_MASK)
+/*! @} */
+
+/*! @name FM - Force Mode Register */
+/*! @{ */
+#define SMC_FM_FORCECFG_MASK                     (0x3U)
+#define SMC_FM_FORCECFG_SHIFT                    (0U)
+/*! FORCECFG - Boot Configuration
+ *  0b00..No effect.
+ *  0b01..Assert corresponding bit in Mode Register on next system reset.
+ */
+#define SMC_FM_FORCECFG(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_FM_FORCECFG_SHIFT)) & SMC_FM_FORCECFG_MASK)
+/*! @} */
+
+/*! @name SRAMLPR - SRAM Low Power Register */
+/*! @{ */
+#define SMC_SRAMLPR_LPE_MASK                     (0xFFFFFFFFU)
+#define SMC_SRAMLPR_LPE_SHIFT                    (0U)
+#define SMC_SRAMLPR_LPE(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_SRAMLPR_LPE_SHIFT)) & SMC_SRAMLPR_LPE_MASK)
+/*! @} */
+
+/*! @name SRAMDSR - SRAM Deep Sleep Register */
+/*! @{ */
+#define SMC_SRAMDSR_DSE_MASK                     (0xFFFFFFFFU)
+#define SMC_SRAMDSR_DSE_SHIFT                    (0U)
+#define SMC_SRAMDSR_DSE(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_SRAMDSR_DSE_SHIFT)) & SMC_SRAMDSR_DSE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC0 base address */
+#define SMC0_BASE                                (0x40020000u)
+/** Peripheral SMC0 base pointer */
+#define SMC0                                     ((SMC_Type *)SMC0_BASE)
+/** Peripheral SMC1 base address */
+#define SMC1_BASE                                (0x41020000u)
+/** Peripheral SMC1 base pointer */
+#define SMC1                                     ((SMC_Type *)SMC1_BASE)
+/** Array initializer of SMC peripheral base addresses */
+#define SMC_BASE_ADDRS                           { SMC0_BASE, SMC1_BASE }
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASE_PTRS                            { SMC0, SMC1 }
+/** Interrupt vectors for the SMC peripheral type */
+#define SMC_IRQS                                 { CMC0_IRQn, NotAvail_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPM_Peripheral_Access_Layer SPM Peripheral Access Layer
+ * @{
+ */
+
+/** SPM - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+       uint8_t RESERVED_0[4];
+  __I  uint32_t RSR;                               /**< Regulator Status Register, offset: 0x8 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t RCTRL;                             /**< Run Control Register, offset: 0x10 */
+  __IO uint32_t LPCTRL;                            /**< Low Power Control Register, offset: 0x14 */
+       uint8_t RESERVED_2[232];
+  __IO uint32_t CORERCNFG;                         /**< CORE LDO RUN Configuration Register, offset: 0x100 */
+  __IO uint32_t CORELPCNFG;                        /**< CORE LDO Low Power Configuration register, offset: 0x104 */
+  __IO uint32_t CORESC;                            /**< Core LDO Status And Control register, offset: 0x108 */
+  __IO uint32_t LVDSC1;                            /**< Low Voltage Detect Status and Control 1 register, offset: 0x10C */
+  __IO uint32_t LVDSC2;                            /**< Low Voltage Detect Status and Control 2 register, offset: 0x110 */
+  __IO uint32_t HVDSC1;                            /**< High Voltage Detect Status And Control 1 register, offset: 0x114 */
+       uint8_t RESERVED_3[232];
+  __IO uint32_t RFLDOLPCNFG;                       /**< RF LDO Low Power Configuration register, offset: 0x200 */
+  __IO uint32_t RFLDOSC;                           /**< RF LDO Status And Control register, offset: 0x204 */
+       uint8_t RESERVED_4[252];
+  __IO uint32_t DCDCSC;                            /**< DCDC Status Control Register, offset: 0x304 */
+       uint8_t RESERVED_5[4];
+  __IO uint32_t DCDCC1;                            /**< DCDC Control Register 1, offset: 0x30C */
+  __IO uint32_t DCDCC2;                            /**< DCDC Control Register 2, offset: 0x310 */
+  __IO uint32_t DCDCC3;                            /**< DCDC Control Register 3, offset: 0x314 */
+  __IO uint32_t DCDCC4;                            /**< DCDC Control Register 4, offset: 0x318 */
+       uint8_t RESERVED_6[4];
+  __IO uint32_t DCDCC6;                            /**< DCDC Control Register 6, offset: 0x320 */
+       uint8_t RESERVED_7[232];
+  __IO uint32_t LPREQPINCNTRL;                     /**< LP Request Pin Control Register, offset: 0x40C */
+} SPM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SPM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPM_Register_Masks SPM Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define SPM_VERID_FEATURE_MASK                   (0xFFFFU)
+#define SPM_VERID_FEATURE_SHIFT                  (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000000000000..Standard features implemented.
+ */
+#define SPM_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << SPM_VERID_FEATURE_SHIFT)) & SPM_VERID_FEATURE_MASK)
+#define SPM_VERID_MINOR_MASK                     (0xFF0000U)
+#define SPM_VERID_MINOR_SHIFT                    (16U)
+#define SPM_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << SPM_VERID_MINOR_SHIFT)) & SPM_VERID_MINOR_MASK)
+#define SPM_VERID_MAJOR_MASK                     (0xFF000000U)
+#define SPM_VERID_MAJOR_SHIFT                    (24U)
+#define SPM_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << SPM_VERID_MAJOR_SHIFT)) & SPM_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name RSR - Regulator Status Register */
+/*! @{ */
+#define SPM_RSR_REGSEL_MASK                      (0x7U)
+#define SPM_RSR_REGSEL_SHIFT                     (0U)
+#define SPM_RSR_REGSEL(x)                        (((uint32_t)(((uint32_t)(x)) << SPM_RSR_REGSEL_SHIFT)) & SPM_RSR_REGSEL_MASK)
+#define SPM_RSR_MCUPMSTAT_MASK                   (0x1F0000U)
+#define SPM_RSR_MCUPMSTAT_SHIFT                  (16U)
+/*! MCUPMSTAT - MCU Power Mode Status
+ *  0b00000..Reserved
+ *  0b00001..Last Low Power mode is STOP.
+ *  0b00010..Last Low Power mode is VLPS.
+ *  0b00100..Last Low Power mode is LLS.
+ *  0b01000..Last Low Power mode is VLLS23.
+ *  0b10000..Last Low Power mode is VLLS01.
+ */
+#define SPM_RSR_MCUPMSTAT(x)                     (((uint32_t)(((uint32_t)(x)) << SPM_RSR_MCUPMSTAT_SHIFT)) & SPM_RSR_MCUPMSTAT_MASK)
+#define SPM_RSR_RFPMSTAT_MASK                    (0x7000000U)
+#define SPM_RSR_RFPMSTAT_SHIFT                   (24U)
+/*! RFPMSTAT - RADIO Power Mode Status
+ *  0b000..Reserved
+ *  0b001..Current Power mode is VLPS.
+ *  0b010..Current Power mode is LLS.
+ *  0b100..Current Power mode is VLLS.
+ */
+#define SPM_RSR_RFPMSTAT(x)                      (((uint32_t)(((uint32_t)(x)) << SPM_RSR_RFPMSTAT_SHIFT)) & SPM_RSR_RFPMSTAT_MASK)
+#define SPM_RSR_RFRUNFORCE_MASK                  (0x8000000U)
+#define SPM_RSR_RFRUNFORCE_SHIFT                 (27U)
+/*! RFRUNFORCE - RADIO Run Force Power Mode Status
+ *  0b0..Radio Run Force Regulator Off
+ *  0b1..Radio Run Force Regulator On.
+ */
+#define SPM_RSR_RFRUNFORCE(x)                    (((uint32_t)(((uint32_t)(x)) << SPM_RSR_RFRUNFORCE_SHIFT)) & SPM_RSR_RFRUNFORCE_MASK)
+/*! @} */
+
+/*! @name RCTRL - Run Control Register */
+/*! @{ */
+#define SPM_RCTRL_REGSEL_MASK                    (0x7U)
+#define SPM_RCTRL_REGSEL_SHIFT                   (0U)
+#define SPM_RCTRL_REGSEL(x)                      (((uint32_t)(((uint32_t)(x)) << SPM_RCTRL_REGSEL_SHIFT)) & SPM_RCTRL_REGSEL_MASK)
+/*! @} */
+
+/*! @name LPCTRL - Low Power Control Register */
+/*! @{ */
+#define SPM_LPCTRL_REGSEL_MASK                   (0x7U)
+#define SPM_LPCTRL_REGSEL_SHIFT                  (0U)
+#define SPM_LPCTRL_REGSEL(x)                     (((uint32_t)(((uint32_t)(x)) << SPM_LPCTRL_REGSEL_SHIFT)) & SPM_LPCTRL_REGSEL_MASK)
+/*! @} */
+
+/*! @name CORERCNFG - CORE LDO RUN Configuration Register */
+/*! @{ */
+#define SPM_CORERCNFG_VDDIOVDDMEN_MASK           (0x10000U)
+#define SPM_CORERCNFG_VDDIOVDDMEN_SHIFT          (16U)
+/*! VDDIOVDDMEN - VDDIOVDDMEN
+ *  0b0..VDDIO voltage monitor disabled in run modes.
+ *  0b1..VDDIO voltage monitor enabled in run modes.
+ */
+#define SPM_CORERCNFG_VDDIOVDDMEN(x)             (((uint32_t)(((uint32_t)(x)) << SPM_CORERCNFG_VDDIOVDDMEN_SHIFT)) & SPM_CORERCNFG_VDDIOVDDMEN_MASK)
+#define SPM_CORERCNFG_USBVDDMEN_MASK             (0x20000U)
+#define SPM_CORERCNFG_USBVDDMEN_SHIFT            (17U)
+/*! USBVDDMEN - USBVDDMEN
+ *  0b0..USB voltage monitor disabled in run modes.
+ *  0b1..USB voltage monitor enabled in run modes.
+ */
+#define SPM_CORERCNFG_USBVDDMEN(x)               (((uint32_t)(((uint32_t)(x)) << SPM_CORERCNFG_USBVDDMEN_SHIFT)) & SPM_CORERCNFG_USBVDDMEN_MASK)
+#define SPM_CORERCNFG_RTCVDDMEN_MASK             (0x40000U)
+#define SPM_CORERCNFG_RTCVDDMEN_SHIFT            (18U)
+/*! RTCVDDMEN - RTCVDDMEN
+ *  0b0..RTC voltage monitor disabled in run modes.
+ *  0b1..RTC voltage monitor enabled in run modes.
+ */
+#define SPM_CORERCNFG_RTCVDDMEN(x)               (((uint32_t)(((uint32_t)(x)) << SPM_CORERCNFG_RTCVDDMEN_SHIFT)) & SPM_CORERCNFG_RTCVDDMEN_MASK)
+/*! @} */
+
+/*! @name CORELPCNFG - CORE LDO Low Power Configuration register */
+/*! @{ */
+#define SPM_CORELPCNFG_LPSEL_MASK                (0x2U)
+#define SPM_CORELPCNFG_LPSEL_SHIFT               (1U)
+/*! LPSEL - LPSEL
+ *  0b0..Core LDO enters low power state in VLP/Stop modes.
+ *  0b1..Core LDO remains in high power state in VLP/Stop modes. If LPSEL = 1 in a low power mode then BGEN must also be set to 1.
+ */
+#define SPM_CORELPCNFG_LPSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_LPSEL_SHIFT)) & SPM_CORELPCNFG_LPSEL_MASK)
+#define SPM_CORELPCNFG_BGEN_MASK                 (0x4U)
+#define SPM_CORELPCNFG_BGEN_SHIFT                (2U)
+/*! BGEN - Bandgap Enable In Low Power Mode Operation
+ *  0b0..Bandgap is disabled in STOP/VLP/LLS and VLLS modes.
+ *  0b1..Bandgap remains enabled in STOP/VLP/LLS and VLLS modes.
+ */
+#define SPM_CORELPCNFG_BGEN(x)                   (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_BGEN_SHIFT)) & SPM_CORELPCNFG_BGEN_MASK)
+#define SPM_CORELPCNFG_BGBEN_MASK                (0x8U)
+#define SPM_CORELPCNFG_BGBEN_SHIFT               (3U)
+/*! BGBEN - Bandgap Buffer Enable
+ *  0b0..Bandgap buffer not enabled
+ *  0b1..Bandgap buffer enabled BGEN must be set when this bit is also set.
+ */
+#define SPM_CORELPCNFG_BGBEN(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_BGBEN_SHIFT)) & SPM_CORELPCNFG_BGBEN_MASK)
+#define SPM_CORELPCNFG_BGBDS_MASK                (0x10U)
+#define SPM_CORELPCNFG_BGBDS_SHIFT               (4U)
+/*! BGBDS - Bandgap Buffer Drive Select
+ *  0b0..Low Drive
+ *  0b1..High Drive
+ */
+#define SPM_CORELPCNFG_BGBDS(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_BGBDS_SHIFT)) & SPM_CORELPCNFG_BGBDS_MASK)
+#define SPM_CORELPCNFG_LPOEN_MASK                (0x80U)
+#define SPM_CORELPCNFG_LPOEN_SHIFT               (7U)
+/*! LPOEN - LPO Enabled
+ *  0b0..LPO is disabled in VLLS modes.
+ *  0b1..LPO remains enabled in VLLS modes.
+ */
+#define SPM_CORELPCNFG_LPOEN(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_LPOEN_SHIFT)) & SPM_CORELPCNFG_LPOEN_MASK)
+#define SPM_CORELPCNFG_POREN_MASK                (0x100U)
+#define SPM_CORELPCNFG_POREN_SHIFT               (8U)
+/*! POREN - POR Enabled
+ *  0b0..POR brownout is disabled in VLLS0/1 mode.
+ *  0b1..POR brownout remains enabled in VLLS0/1 mode.
+ */
+#define SPM_CORELPCNFG_POREN(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_POREN_SHIFT)) & SPM_CORELPCNFG_POREN_MASK)
+#define SPM_CORELPCNFG_LVDEN_MASK                (0x200U)
+#define SPM_CORELPCNFG_LVDEN_SHIFT               (9U)
+/*! LVDEN - LVD Enabled
+ *  0b0..LVD/HVD is disabled in low power modes.
+ *  0b1..LVD/HVD remains enabled in low power modes. BGEN must be set when this bit is also set.
+ */
+#define SPM_CORELPCNFG_LVDEN(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_LVDEN_SHIFT)) & SPM_CORELPCNFG_LVDEN_MASK)
+#define SPM_CORELPCNFG_LPHIDRIVE_MASK            (0x4000U)
+#define SPM_CORELPCNFG_LPHIDRIVE_SHIFT           (14U)
+/*! LPHIDRIVE - LPHIDRIVE
+ *  0b0..High Drive disabled.
+ *  0b1..High Drive enabled.
+ */
+#define SPM_CORELPCNFG_LPHIDRIVE(x)              (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_LPHIDRIVE_SHIFT)) & SPM_CORELPCNFG_LPHIDRIVE_MASK)
+#define SPM_CORELPCNFG_ALLREFEN_MASK             (0x8000U)
+#define SPM_CORELPCNFG_ALLREFEN_SHIFT            (15U)
+/*! ALLREFEN - All Reference Enable. This bit only has an affect in VLLS0/1.
+ *  0b0..All references are disabled in VLLS.
+ *  0b1..All references are enabled in VLLS0/1.
+ */
+#define SPM_CORELPCNFG_ALLREFEN(x)               (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_ALLREFEN_SHIFT)) & SPM_CORELPCNFG_ALLREFEN_MASK)
+#define SPM_CORELPCNFG_VDDIOVDDMEN_MASK          (0x10000U)
+#define SPM_CORELPCNFG_VDDIOVDDMEN_SHIFT         (16U)
+/*! VDDIOVDDMEN - VDDIOVDDMEN
+ *  0b0..VDDIO voltage monitor disabled in lp modes.
+ *  0b1..VDDIO voltage monitor enabled in lp modes. Note: voltage monitor is always disabled in VLLS0/1 modes.
+ */
+#define SPM_CORELPCNFG_VDDIOVDDMEN(x)            (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_VDDIOVDDMEN_SHIFT)) & SPM_CORELPCNFG_VDDIOVDDMEN_MASK)
+#define SPM_CORELPCNFG_USBVDDMEN_MASK            (0x20000U)
+#define SPM_CORELPCNFG_USBVDDMEN_SHIFT           (17U)
+/*! USBVDDMEN - USBVDDMEN
+ *  0b0..USB voltage monitor disabled in lp modes.
+ *  0b1..USB voltage monitor enabled in lp modes. Note: voltage monitor is always disabled in VLLS0/1 modes.
+ */
+#define SPM_CORELPCNFG_USBVDDMEN(x)              (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_USBVDDMEN_SHIFT)) & SPM_CORELPCNFG_USBVDDMEN_MASK)
+#define SPM_CORELPCNFG_RTCVDDMEN_MASK            (0x40000U)
+#define SPM_CORELPCNFG_RTCVDDMEN_SHIFT           (18U)
+/*! RTCVDDMEN - RTCVDDMEN
+ *  0b0..RTC voltage monitor disabled in lp modes.
+ *  0b1..RTC voltage monitor enabled in lp modes. Note: voltage monitor is always disabled in VLLS0/1 modes.
+ */
+#define SPM_CORELPCNFG_RTCVDDMEN(x)              (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_RTCVDDMEN_SHIFT)) & SPM_CORELPCNFG_RTCVDDMEN_MASK)
+/*! @} */
+
+/*! @name CORESC - Core LDO Status And Control register */
+/*! @{ */
+#define SPM_CORESC_REGONS_MASK                   (0x4U)
+#define SPM_CORESC_REGONS_SHIFT                  (2U)
+/*! REGONS - CORE LDO Regulator in Run Regulation Status
+ *  0b0..Regulator is in low power state or in transition to/from it.
+ *  0b1..Regulator is in high power state.
+ */
+#define SPM_CORESC_REGONS(x)                     (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_REGONS_SHIFT)) & SPM_CORESC_REGONS_MASK)
+#define SPM_CORESC_ACKISO_MASK                   (0x8U)
+#define SPM_CORESC_ACKISO_SHIFT                  (3U)
+/*! ACKISO - Acknowledge Isolation
+ *  0b0..Peripherals and I/O pads are in normal run state.
+ *  0b1..Certain peripherals and I/O pads are in a isolated and latched state.
+ */
+#define SPM_CORESC_ACKISO(x)                     (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_ACKISO_SHIFT)) & SPM_CORESC_ACKISO_MASK)
+#define SPM_CORESC_TRIM_MASK                     (0x3F00U)
+#define SPM_CORESC_TRIM_SHIFT                    (8U)
+#define SPM_CORESC_TRIM(x)                       (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_TRIM_SHIFT)) & SPM_CORESC_TRIM_MASK)
+#define SPM_CORESC_VDDIOOVRIDE_MASK              (0x10000U)
+#define SPM_CORESC_VDDIOOVRIDE_SHIFT             (16U)
+/*! VDDIOOVRIDE - VDDIOOVRIDE
+ *  0b0..VDDIOOK status set to 1'b0.
+ *  0b1..VDDIOOK status set to 1'b1.
+ */
+#define SPM_CORESC_VDDIOOVRIDE(x)                (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_VDDIOOVRIDE_SHIFT)) & SPM_CORESC_VDDIOOVRIDE_MASK)
+#define SPM_CORESC_USBOVRIDE_MASK                (0x20000U)
+#define SPM_CORESC_USBOVRIDE_SHIFT               (17U)
+/*! USBOVRIDE - USBOVRIDE
+ *  0b0..USBVDDOK status set to 1'b0.
+ *  0b1..USBVDDOK status set to 1'b1.
+ */
+#define SPM_CORESC_USBOVRIDE(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_USBOVRIDE_SHIFT)) & SPM_CORESC_USBOVRIDE_MASK)
+#define SPM_CORESC_RTCOVRIDE_MASK                (0x40000U)
+#define SPM_CORESC_RTCOVRIDE_SHIFT               (18U)
+/*! RTCOVRIDE - RTCOVRIDE
+ *  0b0..RTCVDDOK status set to 1'b0.
+ *  0b1..RTCVDDOK status set to 1'b1.
+ */
+#define SPM_CORESC_RTCOVRIDE(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_RTCOVRIDE_SHIFT)) & SPM_CORESC_RTCOVRIDE_MASK)
+#define SPM_CORESC_VDDIOOK_MASK                  (0x1000000U)
+#define SPM_CORESC_VDDIOOK_SHIFT                 (24U)
+#define SPM_CORESC_VDDIOOK(x)                    (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_VDDIOOK_SHIFT)) & SPM_CORESC_VDDIOOK_MASK)
+#define SPM_CORESC_USBVDDOK_MASK                 (0x2000000U)
+#define SPM_CORESC_USBVDDOK_SHIFT                (25U)
+#define SPM_CORESC_USBVDDOK(x)                   (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_USBVDDOK_SHIFT)) & SPM_CORESC_USBVDDOK_MASK)
+#define SPM_CORESC_RTCVDDOK_MASK                 (0x4000000U)
+#define SPM_CORESC_RTCVDDOK_SHIFT                (26U)
+#define SPM_CORESC_RTCVDDOK(x)                   (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_RTCVDDOK_SHIFT)) & SPM_CORESC_RTCVDDOK_MASK)
+/*! @} */
+
+/*! @name LVDSC1 - Low Voltage Detect Status and Control 1 register */
+/*! @{ */
+#define SPM_LVDSC1_COREVDD_LVDRE_MASK            (0x10U)
+#define SPM_LVDSC1_COREVDD_LVDRE_SHIFT           (4U)
+/*! COREVDD_LVDRE - Core Low-Voltage Detect Reset Enable
+ *  0b0..COREVDD_LVDF does not generate hardware resets
+ *  0b1..Force an MCU reset when CORE_LVDF = 1
+ */
+#define SPM_LVDSC1_COREVDD_LVDRE(x)              (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_COREVDD_LVDRE_SHIFT)) & SPM_LVDSC1_COREVDD_LVDRE_MASK)
+#define SPM_LVDSC1_COREVDD_LVDIE_MASK            (0x20U)
+#define SPM_LVDSC1_COREVDD_LVDIE_SHIFT           (5U)
+/*! COREVDD_LVDIE - Low-Voltage Detect Interrupt Enable
+ *  0b0..Hardware interrupt disabled (use polling)
+ *  0b1..Request a hardware interrupt when LVDF = 1
+ */
+#define SPM_LVDSC1_COREVDD_LVDIE(x)              (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_COREVDD_LVDIE_SHIFT)) & SPM_LVDSC1_COREVDD_LVDIE_MASK)
+#define SPM_LVDSC1_COREVDD_LVDACK_MASK           (0x40U)
+#define SPM_LVDSC1_COREVDD_LVDACK_SHIFT          (6U)
+#define SPM_LVDSC1_COREVDD_LVDACK(x)             (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_COREVDD_LVDACK_SHIFT)) & SPM_LVDSC1_COREVDD_LVDACK_MASK)
+#define SPM_LVDSC1_COREVDD_LVDF_MASK             (0x80U)
+#define SPM_LVDSC1_COREVDD_LVDF_SHIFT            (7U)
+/*! COREVDD_LVDF - Low-Voltage Detect Flag
+ *  0b0..Low-voltage event not detected
+ *  0b1..Low-voltage event detected
+ */
+#define SPM_LVDSC1_COREVDD_LVDF(x)               (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_COREVDD_LVDF_SHIFT)) & SPM_LVDSC1_COREVDD_LVDF_MASK)
+#define SPM_LVDSC1_VDD_LVDV_MASK                 (0x30000U)
+#define SPM_LVDSC1_VDD_LVDV_SHIFT                (16U)
+/*! VDD_LVDV - VDD Low-Voltage Detect Voltage Select
+ *  0b00..Low trip point selected (V LVD = V LVDL )
+ *  0b01..High trip point selected (V LVD = V LVDH )
+ *  0b10..Reserved
+ *  0b11..Reserved
+ */
+#define SPM_LVDSC1_VDD_LVDV(x)                   (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_VDD_LVDV_SHIFT)) & SPM_LVDSC1_VDD_LVDV_MASK)
+#define SPM_LVDSC1_VDD_LVDRE_MASK                (0x100000U)
+#define SPM_LVDSC1_VDD_LVDRE_SHIFT               (20U)
+/*! VDD_LVDRE - VDD Low-Voltage Detect Reset Enable
+ *  0b0..VDD_LVDF does not generate hardware resets
+ *  0b1..Force an MCU reset when VDD_LVDF = 1
+ */
+#define SPM_LVDSC1_VDD_LVDRE(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_VDD_LVDRE_SHIFT)) & SPM_LVDSC1_VDD_LVDRE_MASK)
+#define SPM_LVDSC1_VDD_LVDIE_MASK                (0x200000U)
+#define SPM_LVDSC1_VDD_LVDIE_SHIFT               (21U)
+/*! VDD_LVDIE - VDD Low-Voltage Detect Interrupt Enable
+ *  0b0..Hardware interrupt disabled (use polling)
+ *  0b1..Request a hardware interrupt when VDD_LVDF = 1
+ */
+#define SPM_LVDSC1_VDD_LVDIE(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_VDD_LVDIE_SHIFT)) & SPM_LVDSC1_VDD_LVDIE_MASK)
+#define SPM_LVDSC1_VDD_LVDACK_MASK               (0x400000U)
+#define SPM_LVDSC1_VDD_LVDACK_SHIFT              (22U)
+#define SPM_LVDSC1_VDD_LVDACK(x)                 (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_VDD_LVDACK_SHIFT)) & SPM_LVDSC1_VDD_LVDACK_MASK)
+#define SPM_LVDSC1_VDD_LVDF_MASK                 (0x800000U)
+#define SPM_LVDSC1_VDD_LVDF_SHIFT                (23U)
+/*! VDD_LVDF - VDD Low-Voltage Detect Flag
+ *  0b0..Low-voltage event not detected
+ *  0b1..Low-voltage event detected
+ */
+#define SPM_LVDSC1_VDD_LVDF(x)                   (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_VDD_LVDF_SHIFT)) & SPM_LVDSC1_VDD_LVDF_MASK)
+/*! @} */
+
+/*! @name LVDSC2 - Low Voltage Detect Status and Control 2 register */
+/*! @{ */
+#define SPM_LVDSC2_VDD_LVWV_MASK                 (0x30000U)
+#define SPM_LVDSC2_VDD_LVWV_SHIFT                (16U)
+/*! VDD_LVWV - VDD Low-Voltage Warning Voltage Select
+ *  0b00..Low trip point selected (V LVW = VLVW1)
+ *  0b01..Mid 1 trip point selected (V LVW = VLVW2)
+ *  0b10..Mid 2 trip point selected (V LVW = VLVW3)
+ *  0b11..High trip point selected (V LVW = VLVW4)
+ */
+#define SPM_LVDSC2_VDD_LVWV(x)                   (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC2_VDD_LVWV_SHIFT)) & SPM_LVDSC2_VDD_LVWV_MASK)
+#define SPM_LVDSC2_VDD_LVWIE_MASK                (0x200000U)
+#define SPM_LVDSC2_VDD_LVWIE_SHIFT               (21U)
+/*! VDD_LVWIE - VDD Low-Voltage Warning Interrupt Enable
+ *  0b0..Hardware interrupt disabled (use polling)
+ *  0b1..Request a hardware interrupt when VDD_LVWF = 1
+ */
+#define SPM_LVDSC2_VDD_LVWIE(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC2_VDD_LVWIE_SHIFT)) & SPM_LVDSC2_VDD_LVWIE_MASK)
+#define SPM_LVDSC2_VDD_LVWACK_MASK               (0x400000U)
+#define SPM_LVDSC2_VDD_LVWACK_SHIFT              (22U)
+#define SPM_LVDSC2_VDD_LVWACK(x)                 (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC2_VDD_LVWACK_SHIFT)) & SPM_LVDSC2_VDD_LVWACK_MASK)
+#define SPM_LVDSC2_VDD_LVWF_MASK                 (0x800000U)
+#define SPM_LVDSC2_VDD_LVWF_SHIFT                (23U)
+/*! VDD_LVWF - VDD Low-Voltage Warning Flag
+ *  0b0..Low-voltage warning event not detected
+ *  0b1..Low-voltage warning event detected
+ */
+#define SPM_LVDSC2_VDD_LVWF(x)                   (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC2_VDD_LVWF_SHIFT)) & SPM_LVDSC2_VDD_LVWF_MASK)
+/*! @} */
+
+/*! @name HVDSC1 - High Voltage Detect Status And Control 1 register */
+/*! @{ */
+#define SPM_HVDSC1_VDD_HVDV_MASK                 (0x10000U)
+#define SPM_HVDSC1_VDD_HVDV_SHIFT                (16U)
+/*! VDD_HVDV - VDD High-Voltage Detect Voltage Select
+ *  0b0..Low trip point selected (V VDD = V VDD_HVDL )
+ *  0b1..High trip point selected (V VDD = V VDD_HVDH )
+ */
+#define SPM_HVDSC1_VDD_HVDV(x)                   (((uint32_t)(((uint32_t)(x)) << SPM_HVDSC1_VDD_HVDV_SHIFT)) & SPM_HVDSC1_VDD_HVDV_MASK)
+#define SPM_HVDSC1_VDD_HVDRE_MASK                (0x100000U)
+#define SPM_HVDSC1_VDD_HVDRE_SHIFT               (20U)
+/*! VDD_HVDRE - VDD High-Voltage Detect Reset Enable
+ *  0b0..VDD HVDF does not generate hardware resets
+ *  0b1..Force an MCU reset when VDD_HVDF = 1
+ */
+#define SPM_HVDSC1_VDD_HVDRE(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_HVDSC1_VDD_HVDRE_SHIFT)) & SPM_HVDSC1_VDD_HVDRE_MASK)
+#define SPM_HVDSC1_VDD_HVDIE_MASK                (0x200000U)
+#define SPM_HVDSC1_VDD_HVDIE_SHIFT               (21U)
+/*! VDD_HVDIE - VDD High-Voltage Detect Interrupt Enable
+ *  0b0..Hardware interrupt disabled (use polling)
+ *  0b1..Request a hardware interrupt when HVDF = 1
+ */
+#define SPM_HVDSC1_VDD_HVDIE(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_HVDSC1_VDD_HVDIE_SHIFT)) & SPM_HVDSC1_VDD_HVDIE_MASK)
+#define SPM_HVDSC1_VDD_HVDACK_MASK               (0x400000U)
+#define SPM_HVDSC1_VDD_HVDACK_SHIFT              (22U)
+#define SPM_HVDSC1_VDD_HVDACK(x)                 (((uint32_t)(((uint32_t)(x)) << SPM_HVDSC1_VDD_HVDACK_SHIFT)) & SPM_HVDSC1_VDD_HVDACK_MASK)
+#define SPM_HVDSC1_VDD_HVDF_MASK                 (0x800000U)
+#define SPM_HVDSC1_VDD_HVDF_SHIFT                (23U)
+/*! VDD_HVDF - VDD High-Voltage Detect Flag
+ *  0b0..Vdd High-voltage event not detected
+ *  0b1..Vdd High-voltage event detected
+ */
+#define SPM_HVDSC1_VDD_HVDF(x)                   (((uint32_t)(((uint32_t)(x)) << SPM_HVDSC1_VDD_HVDF_SHIFT)) & SPM_HVDSC1_VDD_HVDF_MASK)
+/*! @} */
+
+/*! @name RFLDOLPCNFG - RF LDO Low Power Configuration register */
+/*! @{ */
+#define SPM_RFLDOLPCNFG_LPSEL_MASK               (0x2U)
+#define SPM_RFLDOLPCNFG_LPSEL_SHIFT              (1U)
+/*! LPSEL - LPSEL
+ *  0b0..RF LDO regulator enters low power state in VLP/Stop modes.
+ *  0b1..RF LDO regulator remains in high power state in VLP/Stop modes.
+ */
+#define SPM_RFLDOLPCNFG_LPSEL(x)                 (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOLPCNFG_LPSEL_SHIFT)) & SPM_RFLDOLPCNFG_LPSEL_MASK)
+/*! @} */
+
+/*! @name RFLDOSC - RF LDO Status And Control register */
+/*! @{ */
+#define SPM_RFLDOSC_IOREGVSEL_MASK               (0x1U)
+#define SPM_RFLDOSC_IOREGVSEL_SHIFT              (0U)
+/*! IOREGVSEL - IO Regulator Voltage Select
+ *  0b0..Regulate to 1.8V.
+ *  0b1..Regulate to 1.5V.
+ */
+#define SPM_RFLDOSC_IOREGVSEL(x)                 (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_IOREGVSEL_SHIFT)) & SPM_RFLDOSC_IOREGVSEL_MASK)
+#define SPM_RFLDOSC_VDD1P8SEL_MASK               (0x10U)
+#define SPM_RFLDOSC_VDD1P8SEL_SHIFT              (4U)
+/*! VDD1P8SEL - VDD 1p8 SNS Pin Select
+ *  0b0..VDD1p8_SNS0 selected.
+ *  0b1..VDD1p8_SNS1 selected.
+ */
+#define SPM_RFLDOSC_VDD1P8SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_VDD1P8SEL_SHIFT)) & SPM_RFLDOSC_VDD1P8SEL_MASK)
+#define SPM_RFLDOSC_ISINKEN_MASK                 (0x20U)
+#define SPM_RFLDOSC_ISINKEN_SHIFT                (5U)
+/*! ISINKEN - ISINKEN
+ *  0b0..Disable current sink feature of low power regulator.
+ *  0b1..Enable current sink feature of low power regulator.
+ */
+#define SPM_RFLDOSC_ISINKEN(x)                   (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_ISINKEN_SHIFT)) & SPM_RFLDOSC_ISINKEN_MASK)
+#define SPM_RFLDOSC_IOTRIM_MASK                  (0x1F00U)
+#define SPM_RFLDOSC_IOTRIM_SHIFT                 (8U)
+#define SPM_RFLDOSC_IOTRIM(x)                    (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_IOTRIM_SHIFT)) & SPM_RFLDOSC_IOTRIM_MASK)
+#define SPM_RFLDOSC_IOSSSEL_MASK                 (0x70000U)
+#define SPM_RFLDOSC_IOSSSEL_SHIFT                (16U)
+/*! IOSSSEL - IO 1.8 Reg Soft Start Select
+ *  0b000..Soft Start duration set to 110us.
+ *  0b001..Soft Start duration set to 95us.
+ *  0b010..Soft Start duration set to 60us.
+ *  0b011..Soft Start duration set to 48us.
+ *  0b100..Soft Start duration set to 38us.
+ *  0b101..Soft Start duration set to 30us.
+ *  0b110..Soft Start duration set to 24us.
+ *  0b111..Soft Start duration set to 17us.
+ */
+#define SPM_RFLDOSC_IOSSSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_IOSSSEL_SHIFT)) & SPM_RFLDOSC_IOSSSEL_MASK)
+#define SPM_RFLDOSC_SSDONE_MASK                  (0x1000000U)
+#define SPM_RFLDOSC_SSDONE_SHIFT                 (24U)
+#define SPM_RFLDOSC_SSDONE(x)                    (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_SSDONE_SHIFT)) & SPM_RFLDOSC_SSDONE_MASK)
+#define SPM_RFLDOSC_IOSPARE_OUT_MASK             (0xC000000U)
+#define SPM_RFLDOSC_IOSPARE_OUT_SHIFT            (26U)
+#define SPM_RFLDOSC_IOSPARE_OUT(x)               (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_IOSPARE_OUT_SHIFT)) & SPM_RFLDOSC_IOSPARE_OUT_MASK)
+/*! @} */
+
+/*! @name DCDCSC - DCDC Status Control Register */
+/*! @{ */
+#define SPM_DCDCSC_DCDC_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U)
+#define SPM_DCDCSC_DCDC_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U)
+#define SPM_DCDCSC_DCDC_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & SPM_DCDCSC_DCDC_DISABLE_AUTO_CLK_SWITCH_MASK)
+#define SPM_DCDCSC_DCDC_SEL_CLK_MASK             (0x4U)
+#define SPM_DCDCSC_DCDC_SEL_CLK_SHIFT            (2U)
+#define SPM_DCDCSC_DCDC_SEL_CLK(x)               (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_SEL_CLK_SHIFT)) & SPM_DCDCSC_DCDC_SEL_CLK_MASK)
+#define SPM_DCDCSC_DCDC_PWD_OSC_INT_MASK         (0x8U)
+#define SPM_DCDCSC_DCDC_PWD_OSC_INT_SHIFT        (3U)
+#define SPM_DCDCSC_DCDC_PWD_OSC_INT(x)           (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_PWD_OSC_INT_SHIFT)) & SPM_DCDCSC_DCDC_PWD_OSC_INT_MASK)
+#define SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_MASK       (0xC00U)
+#define SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_SHIFT      (10U)
+/*! DCDC_VBAT_DIV_CTRL - DCDC_VBAT_DIV_CTRL
+ *  0b00..OFF
+ *  0b01..VBAT
+ *  0b10..VBAT / 2
+ *  0b11..VBAT / 4
+ */
+#define SPM_DCDCSC_DCDC_VBAT_DIV_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_SHIFT)) & SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_MASK)
+#define SPM_DCDCSC_DCDC_LESS_I_MASK              (0x2000000U)
+#define SPM_DCDCSC_DCDC_LESS_I_SHIFT             (25U)
+#define SPM_DCDCSC_DCDC_LESS_I(x)                (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_LESS_I_SHIFT)) & SPM_DCDCSC_DCDC_LESS_I_MASK)
+#define SPM_DCDCSC_PWD_CMP_OFFSET_MASK           (0x4000000U)
+#define SPM_DCDCSC_PWD_CMP_OFFSET_SHIFT          (26U)
+#define SPM_DCDCSC_PWD_CMP_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_PWD_CMP_OFFSET_SHIFT)) & SPM_DCDCSC_PWD_CMP_OFFSET_MASK)
+#define SPM_DCDCSC_CLKFLT_FAULT_MASK             (0x40000000U)
+#define SPM_DCDCSC_CLKFLT_FAULT_SHIFT            (30U)
+#define SPM_DCDCSC_CLKFLT_FAULT(x)               (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_CLKFLT_FAULT_SHIFT)) & SPM_DCDCSC_CLKFLT_FAULT_MASK)
+#define SPM_DCDCSC_DCDC_STS_DC_OK_MASK           (0x80000000U)
+#define SPM_DCDCSC_DCDC_STS_DC_OK_SHIFT          (31U)
+#define SPM_DCDCSC_DCDC_STS_DC_OK(x)             (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_STS_DC_OK_SHIFT)) & SPM_DCDCSC_DCDC_STS_DC_OK_MASK)
+/*! @} */
+
+/*! @name DCDCC1 - DCDC Control Register 1 */
+/*! @{ */
+#define SPM_DCDCC1_POSLIMIT_BUCK_IN_MASK         (0x7FU)
+#define SPM_DCDCC1_POSLIMIT_BUCK_IN_SHIFT        (0U)
+#define SPM_DCDCC1_POSLIMIT_BUCK_IN(x)           (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC1_POSLIMIT_BUCK_IN_SHIFT)) & SPM_DCDCC1_POSLIMIT_BUCK_IN_MASK)
+#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_CM_HYST_MASK (0x4000000U)
+#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_CM_HYST_SHIFT (26U)
+#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_CM_HYST(x)   (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC1_DCDC_LOOPCTRL_EN_CM_HYST_SHIFT)) & SPM_DCDCC1_DCDC_LOOPCTRL_EN_CM_HYST_MASK)
+#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_DF_HYST_MASK (0x8000000U)
+#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_DF_HYST_SHIFT (27U)
+#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_DF_HYST(x)   (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC1_DCDC_LOOPCTRL_EN_DF_HYST_SHIFT)) & SPM_DCDCC1_DCDC_LOOPCTRL_EN_DF_HYST_MASK)
+/*! @} */
+
+/*! @name DCDCC2 - DCDC Control Register 2 */
+/*! @{ */
+#define SPM_DCDCC2_DCDC_LOOPCTRL_HYST_SIGN_MASK  (0x2000U)
+#define SPM_DCDCC2_DCDC_LOOPCTRL_HYST_SIGN_SHIFT (13U)
+#define SPM_DCDCC2_DCDC_LOOPCTRL_HYST_SIGN(x)    (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC2_DCDC_LOOPCTRL_HYST_SIGN_SHIFT)) & SPM_DCDCC2_DCDC_LOOPCTRL_HYST_SIGN_MASK)
+#define SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_MASK (0x8000U)
+#define SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_SHIFT (15U)
+#define SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_SHIFT)) & SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_MASK)
+#define SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL_MASK (0x3FF0000U)
+#define SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL_SHIFT (16U)
+#define SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL(x)  (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL_SHIFT)) & SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL_MASK)
+/*! @} */
+
+/*! @name DCDCC3 - DCDC Control Register 3 */
+/*! @{ */
+#define SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS_MASK     (0x1U)
+#define SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS_SHIFT    (0U)
+#define SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS(x)       (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS_SHIFT)) & SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS_MASK)
+#define SPM_DCDCC3_DCDC_VBAT_VALUE_MASK          (0x1CU)
+#define SPM_DCDCC3_DCDC_VBAT_VALUE_SHIFT         (2U)
+#define SPM_DCDCC3_DCDC_VBAT_VALUE(x)            (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_VBAT_VALUE_SHIFT)) & SPM_DCDCC3_DCDC_VBAT_VALUE_MASK)
+#define SPM_DCDCC3_DCDC_VDD1P2CTRL_ADJTN_MASK    (0xF0000U)
+#define SPM_DCDCC3_DCDC_VDD1P2CTRL_ADJTN_SHIFT   (16U)
+#define SPM_DCDCC3_DCDC_VDD1P2CTRL_ADJTN(x)      (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_VDD1P2CTRL_ADJTN_SHIFT)) & SPM_DCDCC3_DCDC_VDD1P2CTRL_ADJTN_MASK)
+#define SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_MASK   (0x1000000U)
+#define SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_SHIFT  (24U)
+#define SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK(x)     (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_SHIFT)) & SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_MASK)
+#define SPM_DCDCC3_DCDC_MINPWR_EXTRA_DOUBLE_FETS_MASK (0x2000000U)
+#define SPM_DCDCC3_DCDC_MINPWR_EXTRA_DOUBLE_FETS_SHIFT (25U)
+#define SPM_DCDCC3_DCDC_MINPWR_EXTRA_DOUBLE_FETS(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_MINPWR_EXTRA_DOUBLE_FETS_SHIFT)) & SPM_DCDCC3_DCDC_MINPWR_EXTRA_DOUBLE_FETS_MASK)
+#define SPM_DCDCC3_DCDC_MINPWR_DOUBLE_FETS_MASK  (0x4000000U)
+#define SPM_DCDCC3_DCDC_MINPWR_DOUBLE_FETS_SHIFT (26U)
+#define SPM_DCDCC3_DCDC_MINPWR_DOUBLE_FETS(x)    (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_MINPWR_DOUBLE_FETS_SHIFT)) & SPM_DCDCC3_DCDC_MINPWR_DOUBLE_FETS_MASK)
+#define SPM_DCDCC3_DCDC_MINPWR_HALF_FETS_MASK    (0x8000000U)
+#define SPM_DCDCC3_DCDC_MINPWR_HALF_FETS_SHIFT   (27U)
+#define SPM_DCDCC3_DCDC_MINPWR_HALF_FETS(x)      (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_MINPWR_HALF_FETS_SHIFT)) & SPM_DCDCC3_DCDC_MINPWR_HALF_FETS_MASK)
+#define SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABLE_STEP_MASK (0x40000000U)
+#define SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABLE_STEP_SHIFT (30U)
+#define SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABLE_STEP_SHIFT)) & SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABLE_STEP_MASK)
+#define SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP_MASK (0x80000000U)
+#define SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP_SHIFT (31U)
+#define SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP_SHIFT)) & SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP_MASK)
+/*! @} */
+
+/*! @name DCDCC4 - DCDC Control Register 4 */
+/*! @{ */
+#define SPM_DCDCC4_INTEGRATOR_VALUE_MASK         (0x7FFFFU)
+#define SPM_DCDCC4_INTEGRATOR_VALUE_SHIFT        (0U)
+#define SPM_DCDCC4_INTEGRATOR_VALUE(x)           (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC4_INTEGRATOR_VALUE_SHIFT)) & SPM_DCDCC4_INTEGRATOR_VALUE_MASK)
+#define SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_MASK  (0x80000U)
+#define SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_SHIFT (19U)
+/*! INTEGRATOR_VALUE_SELECT - INTEGRATOR VALUE SELECT
+ *  0b0..Select the saved value in hardware
+ *  0b1..Select the integrator value in this register
+ */
+#define SPM_DCDCC4_INTEGRATOR_VALUE_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_SHIFT)) & SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_MASK)
+#define SPM_DCDCC4_PULSE_RUN_SPEEDUP_MASK        (0x100000U)
+#define SPM_DCDCC4_PULSE_RUN_SPEEDUP_SHIFT       (20U)
+#define SPM_DCDCC4_PULSE_RUN_SPEEDUP(x)          (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC4_PULSE_RUN_SPEEDUP_SHIFT)) & SPM_DCDCC4_PULSE_RUN_SPEEDUP_MASK)
+/*! @} */
+
+/*! @name DCDCC6 - DCDC Control Register 6 */
+/*! @{ */
+#define SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG_MASK      (0x1FU)
+#define SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG_SHIFT     (0U)
+#define SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG(x)        (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG_SHIFT)) & SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG_MASK)
+#define SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK_MASK (0xF00U)
+#define SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK_SHIFT (8U)
+#define SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK(x)   (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK_SHIFT)) & SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK_MASK)
+#define SPM_DCDCC6_DCDC_HSVDD_TRIM_MASK          (0xF000000U)
+#define SPM_DCDCC6_DCDC_HSVDD_TRIM_SHIFT         (24U)
+#define SPM_DCDCC6_DCDC_HSVDD_TRIM(x)            (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC6_DCDC_HSVDD_TRIM_SHIFT)) & SPM_DCDCC6_DCDC_HSVDD_TRIM_MASK)
+/*! @} */
+
+/*! @name LPREQPINCNTRL - LP Request Pin Control Register */
+/*! @{ */
+#define SPM_LPREQPINCNTRL_LPREQOE_MASK           (0x1U)
+#define SPM_LPREQPINCNTRL_LPREQOE_SHIFT          (0U)
+/*! LPREQOE - Low Power Request Output Enable Register
+ *  0b0..Low Power request output pin not enabled.
+ *  0b1..Low Power request output pin enabled.
+ */
+#define SPM_LPREQPINCNTRL_LPREQOE(x)             (((uint32_t)(((uint32_t)(x)) << SPM_LPREQPINCNTRL_LPREQOE_SHIFT)) & SPM_LPREQPINCNTRL_LPREQOE_MASK)
+#define SPM_LPREQPINCNTRL_POLARITY_MASK          (0x2U)
+#define SPM_LPREQPINCNTRL_POLARITY_SHIFT         (1U)
+/*! POLARITY - Low Power Request Output Pin Polarity Control Register
+ *  0b0..High true polarity.
+ *  0b1..Low true polarity.
+ */
+#define SPM_LPREQPINCNTRL_POLARITY(x)            (((uint32_t)(((uint32_t)(x)) << SPM_LPREQPINCNTRL_POLARITY_SHIFT)) & SPM_LPREQPINCNTRL_POLARITY_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SPM_Register_Masks */
+
+
+/* SPM - Peripheral instance base addresses */
+/** Peripheral SPM base address */
+#define SPM_BASE                                 (0x40028000u)
+/** Peripheral SPM base pointer */
+#define SPM                                      ((SPM_Type *)SPM_BASE)
+/** Array initializer of SPM peripheral base addresses */
+#define SPM_BASE_ADDRS                           { SPM_BASE }
+/** Array initializer of SPM peripheral base pointers */
+#define SPM_BASE_PTRS                            { SPM }
+/** Interrupt vectors for the SPM peripheral type */
+#define SPM_IRQS                                 { SPM_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- TPM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
+ * @{
+ */
+
+/** TPM - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __IO uint32_t GLOBAL;                            /**< TPM Global Register, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t SC;                                /**< Status and Control, offset: 0x10 */
+  __IO uint32_t CNT;                               /**< Counter, offset: 0x14 */
+  __IO uint32_t MOD;                               /**< Modulo, offset: 0x18 */
+  __IO uint32_t STATUS;                            /**< Capture and Compare Status, offset: 0x1C */
+  struct {                                         /* offset: 0x20, array step: 0x8 */
+    __IO uint32_t CnSC;                              /**< Channel (n) Status and Control, array offset: 0x20, array step: 0x8 */
+    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x24, array step: 0x8 */
+  } CONTROLS[6];
+       uint8_t RESERVED_1[20];
+  __IO uint32_t COMBINE;                           /**< Combine Channel Register, offset: 0x64 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t TRIG;                              /**< Channel Trigger, offset: 0x6C */
+  __IO uint32_t POL;                               /**< Channel Polarity, offset: 0x70 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t FILTER;                            /**< Filter Control, offset: 0x78 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control and Status, offset: 0x80 */
+  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
+} TPM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- TPM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Register_Masks TPM Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define TPM_VERID_FEATURE_MASK                   (0xFFFFU)
+#define TPM_VERID_FEATURE_SHIFT                  (0U)
+/*! FEATURE - Feature Identification Number
+ *  0b0000000000000001..Standard feature set.
+ *  0b0000000000000011..Standard feature set with Filter and Combine registers implemented.
+ *  0b0000000000000111..Standard feature set with Filter, Combine and Quadrature registers implemented.
+ */
+#define TPM_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_VERID_FEATURE_SHIFT)) & TPM_VERID_FEATURE_MASK)
+#define TPM_VERID_MINOR_MASK                     (0xFF0000U)
+#define TPM_VERID_MINOR_SHIFT                    (16U)
+#define TPM_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MINOR_SHIFT)) & TPM_VERID_MINOR_MASK)
+#define TPM_VERID_MAJOR_MASK                     (0xFF000000U)
+#define TPM_VERID_MAJOR_SHIFT                    (24U)
+#define TPM_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MAJOR_SHIFT)) & TPM_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define TPM_PARAM_CHAN_MASK                      (0xFFU)
+#define TPM_PARAM_CHAN_SHIFT                     (0U)
+#define TPM_PARAM_CHAN(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_CHAN_SHIFT)) & TPM_PARAM_CHAN_MASK)
+#define TPM_PARAM_TRIG_MASK                      (0xFF00U)
+#define TPM_PARAM_TRIG_SHIFT                     (8U)
+#define TPM_PARAM_TRIG(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_TRIG_SHIFT)) & TPM_PARAM_TRIG_MASK)
+#define TPM_PARAM_WIDTH_MASK                     (0xFF0000U)
+#define TPM_PARAM_WIDTH_SHIFT                    (16U)
+#define TPM_PARAM_WIDTH(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_WIDTH_SHIFT)) & TPM_PARAM_WIDTH_MASK)
+/*! @} */
+
+/*! @name GLOBAL - TPM Global Register */
+/*! @{ */
+#define TPM_GLOBAL_NOUPDATE_MASK                 (0x1U)
+#define TPM_GLOBAL_NOUPDATE_SHIFT                (0U)
+/*! NOUPDATE - No Update
+ *  0b0..Internal double buffered registers update as normal.
+ *  0b1..Internal double buffered registers do not update.
+ */
+#define TPM_GLOBAL_NOUPDATE(x)                   (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_NOUPDATE_SHIFT)) & TPM_GLOBAL_NOUPDATE_MASK)
+#define TPM_GLOBAL_RST_MASK                      (0x2U)
+#define TPM_GLOBAL_RST_SHIFT                     (1U)
+/*! RST - Software Reset
+ *  0b0..Module is not reset.
+ *  0b1..Module is reset.
+ */
+#define TPM_GLOBAL_RST(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_RST_SHIFT)) & TPM_GLOBAL_RST_MASK)
+/*! @} */
+
+/*! @name SC - Status and Control */
+/*! @{ */
+#define TPM_SC_PS_MASK                           (0x7U)
+#define TPM_SC_PS_SHIFT                          (0U)
+/*! PS - Prescale Factor Selection
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 4
+ *  0b011..Divide by 8
+ *  0b100..Divide by 16
+ *  0b101..Divide by 32
+ *  0b110..Divide by 64
+ *  0b111..Divide by 128
+ */
+#define TPM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
+#define TPM_SC_CMOD_MASK                         (0x18U)
+#define TPM_SC_CMOD_SHIFT                        (3U)
+/*! CMOD - Clock Mode Selection
+ *  0b00..TPM counter is disabled
+ *  0b01..TPM counter increments on every TPM counter clock
+ *  0b10..TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock
+ *  0b11..TPM counter increments on rising edge of the selected external input trigger.
+ */
+#define TPM_SC_CMOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
+#define TPM_SC_CPWMS_MASK                        (0x20U)
+#define TPM_SC_CPWMS_SHIFT                       (5U)
+/*! CPWMS - Center-Aligned PWM Select
+ *  0b0..TPM counter operates in up counting mode.
+ *  0b1..TPM counter operates in up-down counting mode.
+ */
+#define TPM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
+#define TPM_SC_TOIE_MASK                         (0x40U)
+#define TPM_SC_TOIE_SHIFT                        (6U)
+/*! TOIE - Timer Overflow Interrupt Enable
+ *  0b0..Disable TOF interrupts. Use software polling or DMA request.
+ *  0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.
+ */
+#define TPM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
+#define TPM_SC_TOF_MASK                          (0x80U)
+#define TPM_SC_TOF_SHIFT                         (7U)
+/*! TOF - Timer Overflow Flag
+ *  0b0..TPM counter has not overflowed.
+ *  0b1..TPM counter has overflowed.
+ */
+#define TPM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
+#define TPM_SC_DMA_MASK                          (0x100U)
+#define TPM_SC_DMA_SHIFT                         (8U)
+/*! DMA - DMA Enable
+ *  0b0..Disables DMA transfers.
+ *  0b1..Enables DMA transfers.
+ */
+#define TPM_SC_DMA(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
+/*! @} */
+
+/*! @name CNT - Counter */
+/*! @{ */
+#define TPM_CNT_COUNT_MASK                       (0xFFFFU)
+#define TPM_CNT_COUNT_SHIFT                      (0U)
+#define TPM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
+/*! @} */
+
+/*! @name MOD - Modulo */
+/*! @{ */
+#define TPM_MOD_MOD_MASK                         (0xFFFFU)
+#define TPM_MOD_MOD_SHIFT                        (0U)
+#define TPM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
+/*! @} */
+
+/*! @name STATUS - Capture and Compare Status */
+/*! @{ */
+#define TPM_STATUS_CH0F_MASK                     (0x1U)
+#define TPM_STATUS_CH0F_SHIFT                    (0U)
+/*! CH0F - Channel 0 Flag
+ *  0b0..No channel event has occurred.
+ *  0b1..A channel event has occurred.
+ */
+#define TPM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
+#define TPM_STATUS_CH1F_MASK                     (0x2U)
+#define TPM_STATUS_CH1F_SHIFT                    (1U)
+/*! CH1F - Channel 1 Flag
+ *  0b0..No channel event has occurred.
+ *  0b1..A channel event has occurred.
+ */
+#define TPM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
+#define TPM_STATUS_CH2F_MASK                     (0x4U)
+#define TPM_STATUS_CH2F_SHIFT                    (2U)
+/*! CH2F - Channel 2 Flag
+ *  0b0..No channel event has occurred.
+ *  0b1..A channel event has occurred.
+ */
+#define TPM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK)
+#define TPM_STATUS_CH3F_MASK                     (0x8U)
+#define TPM_STATUS_CH3F_SHIFT                    (3U)
+/*! CH3F - Channel 3 Flag
+ *  0b0..No channel event has occurred.
+ *  0b1..A channel event has occurred.
+ */
+#define TPM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK)
+#define TPM_STATUS_CH4F_MASK                     (0x10U)
+#define TPM_STATUS_CH4F_SHIFT                    (4U)
+/*! CH4F - Channel 4 Flag
+ *  0b0..No channel event has occurred.
+ *  0b1..A channel event has occurred.
+ */
+#define TPM_STATUS_CH4F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK)
+#define TPM_STATUS_CH5F_MASK                     (0x20U)
+#define TPM_STATUS_CH5F_SHIFT                    (5U)
+/*! CH5F - Channel 5 Flag
+ *  0b0..No channel event has occurred.
+ *  0b1..A channel event has occurred.
+ */
+#define TPM_STATUS_CH5F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK)
+#define TPM_STATUS_TOF_MASK                      (0x100U)
+#define TPM_STATUS_TOF_SHIFT                     (8U)
+/*! TOF - Timer Overflow Flag
+ *  0b0..TPM counter has not overflowed.
+ *  0b1..TPM counter has overflowed.
+ */
+#define TPM_STATUS_TOF(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
+/*! @} */
+
+/*! @name CnSC - Channel (n) Status and Control */
+/*! @{ */
+#define TPM_CnSC_DMA_MASK                        (0x1U)
+#define TPM_CnSC_DMA_SHIFT                       (0U)
+/*! DMA - DMA Enable
+ *  0b0..Disable DMA transfers.
+ *  0b1..Enable DMA transfers.
+ */
+#define TPM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
+#define TPM_CnSC_ELSA_MASK                       (0x4U)
+#define TPM_CnSC_ELSA_SHIFT                      (2U)
+#define TPM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
+#define TPM_CnSC_ELSB_MASK                       (0x8U)
+#define TPM_CnSC_ELSB_SHIFT                      (3U)
+#define TPM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
+#define TPM_CnSC_MSA_MASK                        (0x10U)
+#define TPM_CnSC_MSA_SHIFT                       (4U)
+#define TPM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
+#define TPM_CnSC_MSB_MASK                        (0x20U)
+#define TPM_CnSC_MSB_SHIFT                       (5U)
+#define TPM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
+#define TPM_CnSC_CHIE_MASK                       (0x40U)
+#define TPM_CnSC_CHIE_SHIFT                      (6U)
+/*! CHIE - Channel Interrupt Enable
+ *  0b0..Disable channel interrupts.
+ *  0b1..Enable channel interrupts.
+ */
+#define TPM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
+#define TPM_CnSC_CHF_MASK                        (0x80U)
+#define TPM_CnSC_CHF_SHIFT                       (7U)
+/*! CHF - Channel Flag
+ *  0b0..No channel event has occurred.
+ *  0b1..A channel event has occurred.
+ */
+#define TPM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
+/*! @} */
+
+/* The count of TPM_CnSC */
+#define TPM_CnSC_COUNT                           (6U)
+
+/*! @name CnV - Channel (n) Value */
+/*! @{ */
+#define TPM_CnV_VAL_MASK                         (0xFFFFU)
+#define TPM_CnV_VAL_SHIFT                        (0U)
+#define TPM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
+/*! @} */
+
+/* The count of TPM_CnV */
+#define TPM_CnV_COUNT                            (6U)
+
+/*! @name COMBINE - Combine Channel Register */
+/*! @{ */
+#define TPM_COMBINE_COMBINE0_MASK                (0x1U)
+#define TPM_COMBINE_COMBINE0_SHIFT               (0U)
+/*! COMBINE0 - Combine Channels 0 and 1
+ *  0b0..Channels 0 and 1 are independent.
+ *  0b1..Channels 0 and 1 are combined.
+ */
+#define TPM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)
+#define TPM_COMBINE_COMSWAP0_MASK                (0x2U)
+#define TPM_COMBINE_COMSWAP0_SHIFT               (1U)
+/*! COMSWAP0 - Combine Channel 0 and 1 Swap
+ *  0b0..Even channel is used for input capture and 1st compare.
+ *  0b1..Odd channel is used for input capture and 1st compare.
+ */
+#define TPM_COMBINE_COMSWAP0(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)
+#define TPM_COMBINE_COMBINE1_MASK                (0x100U)
+#define TPM_COMBINE_COMBINE1_SHIFT               (8U)
+/*! COMBINE1 - Combine Channels 2 and 3
+ *  0b0..Channels 2 and 3 are independent.
+ *  0b1..Channels 2 and 3 are combined.
+ */
+#define TPM_COMBINE_COMBINE1(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE1_SHIFT)) & TPM_COMBINE_COMBINE1_MASK)
+#define TPM_COMBINE_COMSWAP1_MASK                (0x200U)
+#define TPM_COMBINE_COMSWAP1_SHIFT               (9U)
+/*! COMSWAP1 - Combine Channels 2 and 3 Swap
+ *  0b0..Even channel is used for input capture and 1st compare.
+ *  0b1..Odd channel is used for input capture and 1st compare.
+ */
+#define TPM_COMBINE_COMSWAP1(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP1_SHIFT)) & TPM_COMBINE_COMSWAP1_MASK)
+#define TPM_COMBINE_COMBINE2_MASK                (0x10000U)
+#define TPM_COMBINE_COMBINE2_SHIFT               (16U)
+/*! COMBINE2 - Combine Channels 4 and 5
+ *  0b0..Channels 4 and 5 are independent.
+ *  0b1..Channels 4 and 5 are combined.
+ */
+#define TPM_COMBINE_COMBINE2(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE2_SHIFT)) & TPM_COMBINE_COMBINE2_MASK)
+#define TPM_COMBINE_COMSWAP2_MASK                (0x20000U)
+#define TPM_COMBINE_COMSWAP2_SHIFT               (17U)
+/*! COMSWAP2 - Combine Channels 4 and 5 Swap
+ *  0b0..Even channel is used for input capture and 1st compare.
+ *  0b1..Odd channel is used for input capture and 1st compare.
+ */
+#define TPM_COMBINE_COMSWAP2(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP2_SHIFT)) & TPM_COMBINE_COMSWAP2_MASK)
+/*! @} */
+
+/*! @name TRIG - Channel Trigger */
+/*! @{ */
+#define TPM_TRIG_TRIG0_MASK                      (0x1U)
+#define TPM_TRIG_TRIG0_SHIFT                     (0U)
+/*! TRIG0 - Channel 0 Trigger
+ *  0b0..No effect.
+ *  0b1..Configures trigger input 0 to be used by channel 0.
+ */
+#define TPM_TRIG_TRIG0(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG0_SHIFT)) & TPM_TRIG_TRIG0_MASK)
+#define TPM_TRIG_TRIG1_MASK                      (0x2U)
+#define TPM_TRIG_TRIG1_SHIFT                     (1U)
+/*! TRIG1 - Channel 1 Trigger
+ *  0b0..No effect.
+ *  0b1..Configures trigger input 1 to be used by channel 1.
+ */
+#define TPM_TRIG_TRIG1(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG1_SHIFT)) & TPM_TRIG_TRIG1_MASK)
+#define TPM_TRIG_TRIG2_MASK                      (0x4U)
+#define TPM_TRIG_TRIG2_SHIFT                     (2U)
+/*! TRIG2 - Channel 2 Trigger
+ *  0b0..No effect.
+ *  0b1..Configures trigger input 0 to be used by channel 2.
+ */
+#define TPM_TRIG_TRIG2(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG2_SHIFT)) & TPM_TRIG_TRIG2_MASK)
+#define TPM_TRIG_TRIG3_MASK                      (0x8U)
+#define TPM_TRIG_TRIG3_SHIFT                     (3U)
+/*! TRIG3 - Channel 3 Trigger
+ *  0b0..No effect.
+ *  0b1..Configures trigger input 1 to be used by channel 3.
+ */
+#define TPM_TRIG_TRIG3(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG3_SHIFT)) & TPM_TRIG_TRIG3_MASK)
+#define TPM_TRIG_TRIG4_MASK                      (0x10U)
+#define TPM_TRIG_TRIG4_SHIFT                     (4U)
+/*! TRIG4 - Channel 4 Trigger
+ *  0b0..No effect.
+ *  0b1..Configures trigger input 0 to be used by channel 4.
+ */
+#define TPM_TRIG_TRIG4(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG4_SHIFT)) & TPM_TRIG_TRIG4_MASK)
+#define TPM_TRIG_TRIG5_MASK                      (0x20U)
+#define TPM_TRIG_TRIG5_SHIFT                     (5U)
+/*! TRIG5 - Channel 5 Trigger
+ *  0b0..No effect.
+ *  0b1..Configures trigger input 1 to be used by channel 5.
+ */
+#define TPM_TRIG_TRIG5(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG5_SHIFT)) & TPM_TRIG_TRIG5_MASK)
+/*! @} */
+
+/*! @name POL - Channel Polarity */
+/*! @{ */
+#define TPM_POL_POL0_MASK                        (0x1U)
+#define TPM_POL_POL0_SHIFT                       (0U)
+/*! POL0 - Channel 0 Polarity
+ *  0b0..The channel polarity is active high.
+ *  0b1..The channel polarity is active low.
+ */
+#define TPM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)
+#define TPM_POL_POL1_MASK                        (0x2U)
+#define TPM_POL_POL1_SHIFT                       (1U)
+/*! POL1 - Channel 1 Polarity
+ *  0b0..The channel polarity is active high.
+ *  0b1..The channel polarity is active low.
+ */
+#define TPM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)
+#define TPM_POL_POL2_MASK                        (0x4U)
+#define TPM_POL_POL2_SHIFT                       (2U)
+/*! POL2 - Channel 2 Polarity
+ *  0b0..The channel polarity is active high.
+ *  0b1..The channel polarity is active low.
+ */
+#define TPM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK)
+#define TPM_POL_POL3_MASK                        (0x8U)
+#define TPM_POL_POL3_SHIFT                       (3U)
+/*! POL3 - Channel 3 Polarity
+ *  0b0..The channel polarity is active high.
+ *  0b1..The channel polarity is active low.
+ */
+#define TPM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK)
+#define TPM_POL_POL4_MASK                        (0x10U)
+#define TPM_POL_POL4_SHIFT                       (4U)
+/*! POL4 - Channel 4 Polarity
+ *  0b0..The channel polarity is active high
+ *  0b1..The channel polarity is active low.
+ */
+#define TPM_POL_POL4(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL4_SHIFT)) & TPM_POL_POL4_MASK)
+#define TPM_POL_POL5_MASK                        (0x20U)
+#define TPM_POL_POL5_SHIFT                       (5U)
+/*! POL5 - Channel 5 Polarity
+ *  0b0..The channel polarity is active high.
+ *  0b1..The channel polarity is active low.
+ */
+#define TPM_POL_POL5(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL5_SHIFT)) & TPM_POL_POL5_MASK)
+/*! @} */
+
+/*! @name FILTER - Filter Control */
+/*! @{ */
+#define TPM_FILTER_CH0FVAL_MASK                  (0xFU)
+#define TPM_FILTER_CH0FVAL_SHIFT                 (0U)
+#define TPM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)
+#define TPM_FILTER_CH1FVAL_MASK                  (0xF0U)
+#define TPM_FILTER_CH1FVAL_SHIFT                 (4U)
+#define TPM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)
+#define TPM_FILTER_CH2FVAL_MASK                  (0xF00U)
+#define TPM_FILTER_CH2FVAL_SHIFT                 (8U)
+#define TPM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH2FVAL_SHIFT)) & TPM_FILTER_CH2FVAL_MASK)
+#define TPM_FILTER_CH3FVAL_MASK                  (0xF000U)
+#define TPM_FILTER_CH3FVAL_SHIFT                 (12U)
+#define TPM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH3FVAL_SHIFT)) & TPM_FILTER_CH3FVAL_MASK)
+#define TPM_FILTER_CH4FVAL_MASK                  (0xF0000U)
+#define TPM_FILTER_CH4FVAL_SHIFT                 (16U)
+#define TPM_FILTER_CH4FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH4FVAL_SHIFT)) & TPM_FILTER_CH4FVAL_MASK)
+#define TPM_FILTER_CH5FVAL_MASK                  (0xF00000U)
+#define TPM_FILTER_CH5FVAL_SHIFT                 (20U)
+#define TPM_FILTER_CH5FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH5FVAL_SHIFT)) & TPM_FILTER_CH5FVAL_MASK)
+/*! @} */
+
+/*! @name QDCTRL - Quadrature Decoder Control and Status */
+/*! @{ */
+#define TPM_QDCTRL_QUADEN_MASK                   (0x1U)
+#define TPM_QDCTRL_QUADEN_SHIFT                  (0U)
+/*! QUADEN - QUADEN
+ *  0b0..Quadrature decoder mode is disabled.
+ *  0b1..Quadrature decoder mode is enabled.
+ */
+#define TPM_QDCTRL_QUADEN(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)
+#define TPM_QDCTRL_TOFDIR_MASK                   (0x2U)
+#define TPM_QDCTRL_TOFDIR_SHIFT                  (1U)
+/*! TOFDIR - TOFDIR
+ *  0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register).
+ *  0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero).
+ */
+#define TPM_QDCTRL_TOFDIR(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)
+#define TPM_QDCTRL_QUADIR_MASK                   (0x4U)
+#define TPM_QDCTRL_QUADIR_SHIFT                  (2U)
+/*! QUADIR - Counter Direction in Quadrature Decode Mode
+ *  0b0..Counter direction is decreasing (counter decrement).
+ *  0b1..Counter direction is increasing (counter increment).
+ */
+#define TPM_QDCTRL_QUADIR(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)
+#define TPM_QDCTRL_QUADMODE_MASK                 (0x8U)
+#define TPM_QDCTRL_QUADMODE_SHIFT                (3U)
+/*! QUADMODE - Quadrature Decoder Mode
+ *  0b0..Phase encoding mode.
+ *  0b1..Count and direction encoding mode.
+ */
+#define TPM_QDCTRL_QUADMODE(x)                   (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)
+/*! @} */
+
+/*! @name CONF - Configuration */
+/*! @{ */
+#define TPM_CONF_DOZEEN_MASK                     (0x20U)
+#define TPM_CONF_DOZEEN_SHIFT                    (5U)
+/*! DOZEEN - Doze Enable
+ *  0b0..Internal TPM counter continues in Doze mode.
+ *  0b1..Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are ignored, and PWM outputs are forced to their default state.
+ */
+#define TPM_CONF_DOZEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
+#define TPM_CONF_DBGMODE_MASK                    (0xC0U)
+#define TPM_CONF_DBGMODE_SHIFT                   (6U)
+/*! DBGMODE - Debug Mode
+ *  0b00..TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are ignored, and PWM outputs are forced to their default state.
+ *  0b11..TPM counter continues in debug mode.
+ */
+#define TPM_CONF_DBGMODE(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
+#define TPM_CONF_GTBSYNC_MASK                    (0x100U)
+#define TPM_CONF_GTBSYNC_SHIFT                   (8U)
+/*! GTBSYNC - Global Time Base Synchronization
+ *  0b0..Global timebase synchronization disabled.
+ *  0b1..Global timebase synchronization enabled.
+ */
+#define TPM_CONF_GTBSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)
+#define TPM_CONF_GTBEEN_MASK                     (0x200U)
+#define TPM_CONF_GTBEEN_SHIFT                    (9U)
+/*! GTBEEN - Global time base enable
+ *  0b0..All channels use the internally generated TPM counter as their timebase
+ *  0b1..All channels use an externally generated global timebase as their timebase
+ */
+#define TPM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
+#define TPM_CONF_CSOT_MASK                       (0x10000U)
+#define TPM_CONF_CSOT_SHIFT                      (16U)
+/*! CSOT - Counter Start on Trigger
+ *  0b0..TPM counter starts to increment immediately, once it is enabled.
+ *  0b1..TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.
+ */
+#define TPM_CONF_CSOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
+#define TPM_CONF_CSOO_MASK                       (0x20000U)
+#define TPM_CONF_CSOO_SHIFT                      (17U)
+/*! CSOO - Counter Stop On Overflow
+ *  0b0..TPM counter continues incrementing or decrementing after overflow
+ *  0b1..TPM counter stops incrementing or decrementing after overflow.
+ */
+#define TPM_CONF_CSOO(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
+#define TPM_CONF_CROT_MASK                       (0x40000U)
+#define TPM_CONF_CROT_SHIFT                      (18U)
+/*! CROT - Counter Reload On Trigger
+ *  0b0..Counter is not reloaded due to a rising edge on the selected input trigger
+ *  0b1..Counter is reloaded when a rising edge is detected on the selected input trigger
+ */
+#define TPM_CONF_CROT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
+#define TPM_CONF_CPOT_MASK                       (0x80000U)
+#define TPM_CONF_CPOT_SHIFT                      (19U)
+#define TPM_CONF_CPOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)
+#define TPM_CONF_TRGPOL_MASK                     (0x400000U)
+#define TPM_CONF_TRGPOL_SHIFT                    (22U)
+/*! TRGPOL - Trigger Polarity
+ *  0b0..Trigger is active high.
+ *  0b1..Trigger is active low.
+ */
+#define TPM_CONF_TRGPOL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)
+#define TPM_CONF_TRGSRC_MASK                     (0x800000U)
+#define TPM_CONF_TRGSRC_SHIFT                    (23U)
+/*! TRGSRC - Trigger Source
+ *  0b0..Trigger source selected by TRGSEL is external.
+ *  0b1..Trigger source selected by TRGSEL is internal (channel pin input capture).
+ */
+#define TPM_CONF_TRGSRC(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)
+#define TPM_CONF_TRGSEL_MASK                     (0x3000000U)
+#define TPM_CONF_TRGSEL_SHIFT                    (24U)
+/*! TRGSEL - Trigger Select
+ *  0b01..Channel 0 pin input capture
+ *  0b10..Channel 1 pin input capture
+ *  0b11..Channel 0 or Channel 1 pin input capture
+ */
+#define TPM_CONF_TRGSEL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group TPM_Register_Masks */
+
+
+/* TPM - Peripheral instance base addresses */
+/** Peripheral TPM0 base address */
+#define TPM0_BASE                                (0x40035000u)
+/** Peripheral TPM0 base pointer */
+#define TPM0                                     ((TPM_Type *)TPM0_BASE)
+/** Peripheral TPM1 base address */
+#define TPM1_BASE                                (0x40036000u)
+/** Peripheral TPM1 base pointer */
+#define TPM1                                     ((TPM_Type *)TPM1_BASE)
+/** Peripheral TPM2 base address */
+#define TPM2_BASE                                (0x40037000u)
+/** Peripheral TPM2 base pointer */
+#define TPM2                                     ((TPM_Type *)TPM2_BASE)
+/** Peripheral TPM3 base address */
+#define TPM3_BASE                                (0x4102D000u)
+/** Peripheral TPM3 base pointer */
+#define TPM3                                     ((TPM_Type *)TPM3_BASE)
+/** Array initializer of TPM peripheral base addresses */
+#define TPM_BASE_ADDRS                           { TPM0_BASE, TPM1_BASE, TPM2_BASE, TPM3_BASE }
+/** Array initializer of TPM peripheral base pointers */
+#define TPM_BASE_PTRS                            { TPM0, TPM1, TPM2, TPM3 }
+/** Interrupt vectors for the TPM peripheral type */
+#define TPM_IRQS                                 { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn, TPM3_IRQn }
+
+/*!
+ * @}
+ */ /* end of group TPM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- TRGMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TRGMUX_Peripheral_Access_Layer TRGMUX Peripheral Access Layer
+ * @{
+ */
+
+/** TRGMUX - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TRGCFG[25];                        /**< TRGMUX TRGMUX_DMAMUX0 Register..TRGMUX TRGMUX_LPDAC0 Register, array offset: 0x0, array step: 0x4 */
+} TRGMUX_Type;
+
+/* ----------------------------------------------------------------------------
+   -- TRGMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TRGMUX_Register_Masks TRGMUX Register Masks
+ * @{
+ */
+
+/*! @name TRGCFG - TRGMUX TRGMUX_DMAMUX0 Register..TRGMUX TRGMUX_LPDAC0 Register */
+/*! @{ */
+#define TRGMUX_TRGCFG_SEL0_MASK                  (0x3FU)
+#define TRGMUX_TRGCFG_SEL0_SHIFT                 (0U)
+#define TRGMUX_TRGCFG_SEL0(x)                    (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL0_SHIFT)) & TRGMUX_TRGCFG_SEL0_MASK)
+#define TRGMUX_TRGCFG_SEL1_MASK                  (0x3F00U)
+#define TRGMUX_TRGCFG_SEL1_SHIFT                 (8U)
+#define TRGMUX_TRGCFG_SEL1(x)                    (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL1_SHIFT)) & TRGMUX_TRGCFG_SEL1_MASK)
+#define TRGMUX_TRGCFG_SEL2_MASK                  (0x3F0000U)
+#define TRGMUX_TRGCFG_SEL2_SHIFT                 (16U)
+#define TRGMUX_TRGCFG_SEL2(x)                    (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL2_SHIFT)) & TRGMUX_TRGCFG_SEL2_MASK)
+#define TRGMUX_TRGCFG_SEL3_MASK                  (0x3F000000U)
+#define TRGMUX_TRGCFG_SEL3_SHIFT                 (24U)
+#define TRGMUX_TRGCFG_SEL3(x)                    (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL3_SHIFT)) & TRGMUX_TRGCFG_SEL3_MASK)
+#define TRGMUX_TRGCFG_LK_MASK                    (0x80000000U)
+#define TRGMUX_TRGCFG_LK_SHIFT                   (31U)
+/*! LK - TRGMUX register lock.
+ *  0b0..Register can be written.
+ *  0b1..Register cannot be written until the next system Reset.
+ */
+#define TRGMUX_TRGCFG_LK(x)                      (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_LK_SHIFT)) & TRGMUX_TRGCFG_LK_MASK)
+/*! @} */
+
+/* The count of TRGMUX_TRGCFG */
+#define TRGMUX_TRGCFG_COUNT                      (25U)
+
+
+/*!
+ * @}
+ */ /* end of group TRGMUX_Register_Masks */
+
+
+/* TRGMUX - Peripheral instance base addresses */
+/** Peripheral TRGMUX0 base address */
+#define TRGMUX0_BASE                             (0x40029000u)
+/** Peripheral TRGMUX0 base pointer */
+#define TRGMUX0                                  ((TRGMUX_Type *)TRGMUX0_BASE)
+/** Peripheral TRGMUX1 base address */
+#define TRGMUX1_BASE                             (0x41025000u)
+/** Peripheral TRGMUX1 base pointer */
+#define TRGMUX1                                  ((TRGMUX_Type *)TRGMUX1_BASE)
+/** Array initializer of TRGMUX peripheral base addresses */
+#define TRGMUX_BASE_ADDRS                        { TRGMUX0_BASE, TRGMUX1_BASE }
+/** Array initializer of TRGMUX peripheral base pointers */
+#define TRGMUX_BASE_PTRS                         { TRGMUX0, TRGMUX1 }
+
+/*!
+ * @}
+ */ /* end of group TRGMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- TRNG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer
+ * @{
+ */
+
+/** TRNG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCTL;                              /**< Miscellaneous Control Register, offset: 0x0 */
+  __IO uint32_t SCMISC;                            /**< Statistical Check Miscellaneous Register, offset: 0x4 */
+  __IO uint32_t PKRRNG;                            /**< Poker Range Register, offset: 0x8 */
+  union {                                          /* offset: 0xC */
+    __IO uint32_t PKRMAX;                            /**< Poker Maximum Limit Register, offset: 0xC */
+    __I  uint32_t PKRSQ;                             /**< Poker Square Calculation Result Register, offset: 0xC */
+  };
+  __IO uint32_t SDCTL;                             /**< Seed Control Register, offset: 0x10 */
+  union {                                          /* offset: 0x14 */
+    __IO uint32_t SBLIM;                             /**< Sparse Bit Limit Register, offset: 0x14 */
+    __I  uint32_t TOTSAM;                            /**< Total Samples Register, offset: 0x14 */
+  };
+  __IO uint32_t FRQMIN;                            /**< Frequency Count Minimum Limit Register, offset: 0x18 */
+  union {                                          /* offset: 0x1C */
+    __I  uint32_t FRQCNT;                            /**< Frequency Count Register, offset: 0x1C */
+    __IO uint32_t FRQMAX;                            /**< Frequency Count Maximum Limit Register, offset: 0x1C */
+  };
+  union {                                          /* offset: 0x20 */
+    __I  uint32_t SCMC;                              /**< Statistical Check Monobit Count Register, offset: 0x20 */
+    __IO uint32_t SCML;                              /**< Statistical Check Monobit Limit Register, offset: 0x20 */
+  };
+  union {                                          /* offset: 0x24 */
+    __I  uint32_t SCR1C;                             /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */
+    __IO uint32_t SCR1L;                             /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */
+  };
+  union {                                          /* offset: 0x28 */
+    __I  uint32_t SCR2C;                             /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */
+    __IO uint32_t SCR2L;                             /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */
+  };
+  union {                                          /* offset: 0x2C */
+    __I  uint32_t SCR3C;                             /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */
+    __IO uint32_t SCR3L;                             /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */
+  };
+  union {                                          /* offset: 0x30 */
+    __I  uint32_t SCR4C;                             /**< Statistical Check Run Length 4 Count Register, offset: 0x30 */
+    __IO uint32_t SCR4L;                             /**< Statistical Check Run Length 4 Limit Register, offset: 0x30 */
+  };
+  union {                                          /* offset: 0x34 */
+    __I  uint32_t SCR5C;                             /**< Statistical Check Run Length 5 Count Register, offset: 0x34 */
+    __IO uint32_t SCR5L;                             /**< Statistical Check Run Length 5 Limit Register, offset: 0x34 */
+  };
+  union {                                          /* offset: 0x38 */
+    __I  uint32_t SCR6PC;                            /**< Statistical Check Run Length 6+ Count Register, offset: 0x38 */
+    __IO uint32_t SCR6PL;                            /**< Statistical Check Run Length 6+ Limit Register, offset: 0x38 */
+  };
+  __I  uint32_t STATUS;                            /**< Status Register, offset: 0x3C */
+  __I  uint32_t ENT[16];                           /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */
+  __I  uint32_t PKRCNT10;                          /**< Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */
+  __I  uint32_t PKRCNT32;                          /**< Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */
+  __I  uint32_t PKRCNT54;                          /**< Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */
+  __I  uint32_t PKRCNT76;                          /**< Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */
+  __I  uint32_t PKRCNT98;                          /**< Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */
+  __I  uint32_t PKRCNTBA;                          /**< Statistical Check Poker Count B and A Register, offset: 0x94 */
+  __I  uint32_t PKRCNTDC;                          /**< Statistical Check Poker Count D and C Register, offset: 0x98 */
+  __I  uint32_t PKRCNTFE;                          /**< Statistical Check Poker Count F and E Register, offset: 0x9C */
+  __IO uint32_t SEC_CFG;                           /**< Security Configuration Register, offset: 0xA0 */
+  __IO uint32_t INT_CTRL;                          /**< Interrupt Control Register, offset: 0xA4 */
+  __IO uint32_t INT_MASK;                          /**< Mask Register, offset: 0xA8 */
+  __I  uint32_t INT_STATUS;                        /**< Interrupt Status Register, offset: 0xAC */
+       uint8_t RESERVED_0[64];
+  __I  uint32_t VID1;                              /**< Version ID Register (MS), offset: 0xF0 */
+  __I  uint32_t VID2;                              /**< Version ID Register (LS), offset: 0xF4 */
+} TRNG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- TRNG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TRNG_Register_Masks TRNG Register Masks
+ * @{
+ */
+
+/*! @name MCTL - Miscellaneous Control Register */
+/*! @{ */
+#define TRNG_MCTL_SAMP_MODE_MASK                 (0x3U)
+#define TRNG_MCTL_SAMP_MODE_SHIFT                (0U)
+/*! SAMP_MODE
+ *  0b00..use Von Neumann data into both Entropy shifter and Statistical Checker
+ *  0b01..use raw data into both Entropy shifter and Statistical Checker
+ *  0b10..use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker
+ *  0b11..undefined/reserved.
+ */
+#define TRNG_MCTL_SAMP_MODE(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)
+#define TRNG_MCTL_OSC_DIV_MASK                   (0xCU)
+#define TRNG_MCTL_OSC_DIV_SHIFT                  (2U)
+/*! OSC_DIV
+ *  0b00..use ring oscillator with no divide
+ *  0b01..use ring oscillator divided-by-2
+ *  0b10..use ring oscillator divided-by-4
+ *  0b11..use ring oscillator divided-by-8
+ */
+#define TRNG_MCTL_OSC_DIV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
+#define TRNG_MCTL_UNUSED4_MASK                   (0x10U)
+#define TRNG_MCTL_UNUSED4_SHIFT                  (4U)
+#define TRNG_MCTL_UNUSED4(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK)
+#define TRNG_MCTL_TRNG_ACC_MASK                  (0x20U)
+#define TRNG_MCTL_TRNG_ACC_SHIFT                 (5U)
+#define TRNG_MCTL_TRNG_ACC(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK)
+#define TRNG_MCTL_RST_DEF_MASK                   (0x40U)
+#define TRNG_MCTL_RST_DEF_SHIFT                  (6U)
+#define TRNG_MCTL_RST_DEF(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)
+#define TRNG_MCTL_FOR_SCLK_MASK                  (0x80U)
+#define TRNG_MCTL_FOR_SCLK_SHIFT                 (7U)
+#define TRNG_MCTL_FOR_SCLK(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)
+#define TRNG_MCTL_FCT_FAIL_MASK                  (0x100U)
+#define TRNG_MCTL_FCT_FAIL_SHIFT                 (8U)
+#define TRNG_MCTL_FCT_FAIL(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)
+#define TRNG_MCTL_FCT_VAL_MASK                   (0x200U)
+#define TRNG_MCTL_FCT_VAL_SHIFT                  (9U)
+#define TRNG_MCTL_FCT_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)
+#define TRNG_MCTL_ENT_VAL_MASK                   (0x400U)
+#define TRNG_MCTL_ENT_VAL_SHIFT                  (10U)
+#define TRNG_MCTL_ENT_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)
+#define TRNG_MCTL_TST_OUT_MASK                   (0x800U)
+#define TRNG_MCTL_TST_OUT_SHIFT                  (11U)
+#define TRNG_MCTL_TST_OUT(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)
+#define TRNG_MCTL_ERR_MASK                       (0x1000U)
+#define TRNG_MCTL_ERR_SHIFT                      (12U)
+#define TRNG_MCTL_ERR(x)                         (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)
+#define TRNG_MCTL_TSTOP_OK_MASK                  (0x2000U)
+#define TRNG_MCTL_TSTOP_OK_SHIFT                 (13U)
+#define TRNG_MCTL_TSTOP_OK(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)
+#define TRNG_MCTL_PRGM_MASK                      (0x10000U)
+#define TRNG_MCTL_PRGM_SHIFT                     (16U)
+#define TRNG_MCTL_PRGM(x)                        (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
+/*! @} */
+
+/*! @name SCMISC - Statistical Check Miscellaneous Register */
+/*! @{ */
+#define TRNG_SCMISC_LRUN_MAX_MASK                (0xFFU)
+#define TRNG_SCMISC_LRUN_MAX_SHIFT               (0U)
+#define TRNG_SCMISC_LRUN_MAX(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)
+#define TRNG_SCMISC_RTY_CT_MASK                  (0xF0000U)
+#define TRNG_SCMISC_RTY_CT_SHIFT                 (16U)
+#define TRNG_SCMISC_RTY_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
+/*! @} */
+
+/*! @name PKRRNG - Poker Range Register */
+/*! @{ */
+#define TRNG_PKRRNG_PKR_RNG_MASK                 (0xFFFFU)
+#define TRNG_PKRRNG_PKR_RNG_SHIFT                (0U)
+#define TRNG_PKRRNG_PKR_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)
+/*! @} */
+
+/*! @name PKRMAX - Poker Maximum Limit Register */
+/*! @{ */
+#define TRNG_PKRMAX_PKR_MAX_MASK                 (0xFFFFFFU)
+#define TRNG_PKRMAX_PKR_MAX_SHIFT                (0U)
+#define TRNG_PKRMAX_PKR_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)
+/*! @} */
+
+/*! @name PKRSQ - Poker Square Calculation Result Register */
+/*! @{ */
+#define TRNG_PKRSQ_PKR_SQ_MASK                   (0xFFFFFFU)
+#define TRNG_PKRSQ_PKR_SQ_SHIFT                  (0U)
+#define TRNG_PKRSQ_PKR_SQ(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)
+/*! @} */
+
+/*! @name SDCTL - Seed Control Register */
+/*! @{ */
+#define TRNG_SDCTL_SAMP_SIZE_MASK                (0xFFFFU)
+#define TRNG_SDCTL_SAMP_SIZE_SHIFT               (0U)
+#define TRNG_SDCTL_SAMP_SIZE(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)
+#define TRNG_SDCTL_ENT_DLY_MASK                  (0xFFFF0000U)
+#define TRNG_SDCTL_ENT_DLY_SHIFT                 (16U)
+#define TRNG_SDCTL_ENT_DLY(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
+/*! @} */
+
+/*! @name SBLIM - Sparse Bit Limit Register */
+/*! @{ */
+#define TRNG_SBLIM_SB_LIM_MASK                   (0x3FFU)
+#define TRNG_SBLIM_SB_LIM_SHIFT                  (0U)
+#define TRNG_SBLIM_SB_LIM(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)
+/*! @} */
+
+/*! @name TOTSAM - Total Samples Register */
+/*! @{ */
+#define TRNG_TOTSAM_TOT_SAM_MASK                 (0xFFFFFU)
+#define TRNG_TOTSAM_TOT_SAM_SHIFT                (0U)
+#define TRNG_TOTSAM_TOT_SAM(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)
+/*! @} */
+
+/*! @name FRQMIN - Frequency Count Minimum Limit Register */
+/*! @{ */
+#define TRNG_FRQMIN_FRQ_MIN_MASK                 (0x3FFFFFU)
+#define TRNG_FRQMIN_FRQ_MIN_SHIFT                (0U)
+#define TRNG_FRQMIN_FRQ_MIN(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
+/*! @} */
+
+/*! @name FRQCNT - Frequency Count Register */
+/*! @{ */
+#define TRNG_FRQCNT_FRQ_CT_MASK                  (0x3FFFFFU)
+#define TRNG_FRQCNT_FRQ_CT_SHIFT                 (0U)
+#define TRNG_FRQCNT_FRQ_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
+/*! @} */
+
+/*! @name FRQMAX - Frequency Count Maximum Limit Register */
+/*! @{ */
+#define TRNG_FRQMAX_FRQ_MAX_MASK                 (0x3FFFFFU)
+#define TRNG_FRQMAX_FRQ_MAX_SHIFT                (0U)
+#define TRNG_FRQMAX_FRQ_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
+/*! @} */
+
+/*! @name SCMC - Statistical Check Monobit Count Register */
+/*! @{ */
+#define TRNG_SCMC_MONO_CT_MASK                   (0xFFFFU)
+#define TRNG_SCMC_MONO_CT_SHIFT                  (0U)
+#define TRNG_SCMC_MONO_CT(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
+/*! @} */
+
+/*! @name SCML - Statistical Check Monobit Limit Register */
+/*! @{ */
+#define TRNG_SCML_MONO_MAX_MASK                  (0xFFFFU)
+#define TRNG_SCML_MONO_MAX_SHIFT                 (0U)
+#define TRNG_SCML_MONO_MAX(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)
+#define TRNG_SCML_MONO_RNG_MASK                  (0xFFFF0000U)
+#define TRNG_SCML_MONO_RNG_SHIFT                 (16U)
+#define TRNG_SCML_MONO_RNG(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
+/*! @} */
+
+/*! @name SCR1C - Statistical Check Run Length 1 Count Register */
+/*! @{ */
+#define TRNG_SCR1C_R1_0_CT_MASK                  (0x7FFFU)
+#define TRNG_SCR1C_R1_0_CT_SHIFT                 (0U)
+#define TRNG_SCR1C_R1_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)
+#define TRNG_SCR1C_R1_1_CT_MASK                  (0x7FFF0000U)
+#define TRNG_SCR1C_R1_1_CT_SHIFT                 (16U)
+#define TRNG_SCR1C_R1_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
+/*! @} */
+
+/*! @name SCR1L - Statistical Check Run Length 1 Limit Register */
+/*! @{ */
+#define TRNG_SCR1L_RUN1_MAX_MASK                 (0x7FFFU)
+#define TRNG_SCR1L_RUN1_MAX_SHIFT                (0U)
+#define TRNG_SCR1L_RUN1_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)
+#define TRNG_SCR1L_RUN1_RNG_MASK                 (0x7FFF0000U)
+#define TRNG_SCR1L_RUN1_RNG_SHIFT                (16U)
+#define TRNG_SCR1L_RUN1_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
+/*! @} */
+
+/*! @name SCR2C - Statistical Check Run Length 2 Count Register */
+/*! @{ */
+#define TRNG_SCR2C_R2_0_CT_MASK                  (0x3FFFU)
+#define TRNG_SCR2C_R2_0_CT_SHIFT                 (0U)
+#define TRNG_SCR2C_R2_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)
+#define TRNG_SCR2C_R2_1_CT_MASK                  (0x3FFF0000U)
+#define TRNG_SCR2C_R2_1_CT_SHIFT                 (16U)
+#define TRNG_SCR2C_R2_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
+/*! @} */
+
+/*! @name SCR2L - Statistical Check Run Length 2 Limit Register */
+/*! @{ */
+#define TRNG_SCR2L_RUN2_MAX_MASK                 (0x3FFFU)
+#define TRNG_SCR2L_RUN2_MAX_SHIFT                (0U)
+#define TRNG_SCR2L_RUN2_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)
+#define TRNG_SCR2L_RUN2_RNG_MASK                 (0x3FFF0000U)
+#define TRNG_SCR2L_RUN2_RNG_SHIFT                (16U)
+#define TRNG_SCR2L_RUN2_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
+/*! @} */
+
+/*! @name SCR3C - Statistical Check Run Length 3 Count Register */
+/*! @{ */
+#define TRNG_SCR3C_R3_0_CT_MASK                  (0x1FFFU)
+#define TRNG_SCR3C_R3_0_CT_SHIFT                 (0U)
+#define TRNG_SCR3C_R3_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)
+#define TRNG_SCR3C_R3_1_CT_MASK                  (0x1FFF0000U)
+#define TRNG_SCR3C_R3_1_CT_SHIFT                 (16U)
+#define TRNG_SCR3C_R3_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
+/*! @} */
+
+/*! @name SCR3L - Statistical Check Run Length 3 Limit Register */
+/*! @{ */
+#define TRNG_SCR3L_RUN3_MAX_MASK                 (0x1FFFU)
+#define TRNG_SCR3L_RUN3_MAX_SHIFT                (0U)
+#define TRNG_SCR3L_RUN3_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)
+#define TRNG_SCR3L_RUN3_RNG_MASK                 (0x1FFF0000U)
+#define TRNG_SCR3L_RUN3_RNG_SHIFT                (16U)
+#define TRNG_SCR3L_RUN3_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
+/*! @} */
+
+/*! @name SCR4C - Statistical Check Run Length 4 Count Register */
+/*! @{ */
+#define TRNG_SCR4C_R4_0_CT_MASK                  (0xFFFU)
+#define TRNG_SCR4C_R4_0_CT_SHIFT                 (0U)
+#define TRNG_SCR4C_R4_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)
+#define TRNG_SCR4C_R4_1_CT_MASK                  (0xFFF0000U)
+#define TRNG_SCR4C_R4_1_CT_SHIFT                 (16U)
+#define TRNG_SCR4C_R4_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)
+/*! @} */
+
+/*! @name SCR4L - Statistical Check Run Length 4 Limit Register */
+/*! @{ */
+#define TRNG_SCR4L_RUN4_MAX_MASK                 (0xFFFU)
+#define TRNG_SCR4L_RUN4_MAX_SHIFT                (0U)
+#define TRNG_SCR4L_RUN4_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)
+#define TRNG_SCR4L_RUN4_RNG_MASK                 (0xFFF0000U)
+#define TRNG_SCR4L_RUN4_RNG_SHIFT                (16U)
+#define TRNG_SCR4L_RUN4_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)
+/*! @} */
+
+/*! @name SCR5C - Statistical Check Run Length 5 Count Register */
+/*! @{ */
+#define TRNG_SCR5C_R5_0_CT_MASK                  (0x7FFU)
+#define TRNG_SCR5C_R5_0_CT_SHIFT                 (0U)
+#define TRNG_SCR5C_R5_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)
+#define TRNG_SCR5C_R5_1_CT_MASK                  (0x7FF0000U)
+#define TRNG_SCR5C_R5_1_CT_SHIFT                 (16U)
+#define TRNG_SCR5C_R5_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)
+/*! @} */
+
+/*! @name SCR5L - Statistical Check Run Length 5 Limit Register */
+/*! @{ */
+#define TRNG_SCR5L_RUN5_MAX_MASK                 (0x7FFU)
+#define TRNG_SCR5L_RUN5_MAX_SHIFT                (0U)
+#define TRNG_SCR5L_RUN5_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)
+#define TRNG_SCR5L_RUN5_RNG_MASK                 (0x7FF0000U)
+#define TRNG_SCR5L_RUN5_RNG_SHIFT                (16U)
+#define TRNG_SCR5L_RUN5_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)
+/*! @} */
+
+/*! @name SCR6PC - Statistical Check Run Length 6+ Count Register */
+/*! @{ */
+#define TRNG_SCR6PC_R6P_0_CT_MASK                (0x7FFU)
+#define TRNG_SCR6PC_R6P_0_CT_SHIFT               (0U)
+#define TRNG_SCR6PC_R6P_0_CT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)
+#define TRNG_SCR6PC_R6P_1_CT_MASK                (0x7FF0000U)
+#define TRNG_SCR6PC_R6P_1_CT_SHIFT               (16U)
+#define TRNG_SCR6PC_R6P_1_CT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)
+/*! @} */
+
+/*! @name SCR6PL - Statistical Check Run Length 6+ Limit Register */
+/*! @{ */
+#define TRNG_SCR6PL_RUN6P_MAX_MASK               (0x7FFU)
+#define TRNG_SCR6PL_RUN6P_MAX_SHIFT              (0U)
+#define TRNG_SCR6PL_RUN6P_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)
+#define TRNG_SCR6PL_RUN6P_RNG_MASK               (0x7FF0000U)
+#define TRNG_SCR6PL_RUN6P_RNG_SHIFT              (16U)
+#define TRNG_SCR6PL_RUN6P_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)
+/*! @} */
+
+/*! @name STATUS - Status Register */
+/*! @{ */
+#define TRNG_STATUS_TF1BR0_MASK                  (0x1U)
+#define TRNG_STATUS_TF1BR0_SHIFT                 (0U)
+#define TRNG_STATUS_TF1BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
+#define TRNG_STATUS_TF1BR1_MASK                  (0x2U)
+#define TRNG_STATUS_TF1BR1_SHIFT                 (1U)
+#define TRNG_STATUS_TF1BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
+#define TRNG_STATUS_TF2BR0_MASK                  (0x4U)
+#define TRNG_STATUS_TF2BR0_SHIFT                 (2U)
+#define TRNG_STATUS_TF2BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
+#define TRNG_STATUS_TF2BR1_MASK                  (0x8U)
+#define TRNG_STATUS_TF2BR1_SHIFT                 (3U)
+#define TRNG_STATUS_TF2BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
+#define TRNG_STATUS_TF3BR0_MASK                  (0x10U)
+#define TRNG_STATUS_TF3BR0_SHIFT                 (4U)
+#define TRNG_STATUS_TF3BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
+#define TRNG_STATUS_TF3BR1_MASK                  (0x20U)
+#define TRNG_STATUS_TF3BR1_SHIFT                 (5U)
+#define TRNG_STATUS_TF3BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
+#define TRNG_STATUS_TF4BR0_MASK                  (0x40U)
+#define TRNG_STATUS_TF4BR0_SHIFT                 (6U)
+#define TRNG_STATUS_TF4BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)
+#define TRNG_STATUS_TF4BR1_MASK                  (0x80U)
+#define TRNG_STATUS_TF4BR1_SHIFT                 (7U)
+#define TRNG_STATUS_TF4BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)
+#define TRNG_STATUS_TF5BR0_MASK                  (0x100U)
+#define TRNG_STATUS_TF5BR0_SHIFT                 (8U)
+#define TRNG_STATUS_TF5BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)
+#define TRNG_STATUS_TF5BR1_MASK                  (0x200U)
+#define TRNG_STATUS_TF5BR1_SHIFT                 (9U)
+#define TRNG_STATUS_TF5BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)
+#define TRNG_STATUS_TF6PBR0_MASK                 (0x400U)
+#define TRNG_STATUS_TF6PBR0_SHIFT                (10U)
+#define TRNG_STATUS_TF6PBR0(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)
+#define TRNG_STATUS_TF6PBR1_MASK                 (0x800U)
+#define TRNG_STATUS_TF6PBR1_SHIFT                (11U)
+#define TRNG_STATUS_TF6PBR1(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)
+#define TRNG_STATUS_TFSB_MASK                    (0x1000U)
+#define TRNG_STATUS_TFSB_SHIFT                   (12U)
+#define TRNG_STATUS_TFSB(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)
+#define TRNG_STATUS_TFLR_MASK                    (0x2000U)
+#define TRNG_STATUS_TFLR_SHIFT                   (13U)
+#define TRNG_STATUS_TFLR(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
+#define TRNG_STATUS_TFP_MASK                     (0x4000U)
+#define TRNG_STATUS_TFP_SHIFT                    (14U)
+#define TRNG_STATUS_TFP(x)                       (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)
+#define TRNG_STATUS_TFMB_MASK                    (0x8000U)
+#define TRNG_STATUS_TFMB_SHIFT                   (15U)
+#define TRNG_STATUS_TFMB(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
+#define TRNG_STATUS_RETRY_CT_MASK                (0xF0000U)
+#define TRNG_STATUS_RETRY_CT_SHIFT               (16U)
+#define TRNG_STATUS_RETRY_CT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
+/*! @} */
+
+/*! @name ENT - Entropy Read Register */
+/*! @{ */
+#define TRNG_ENT_ENT_MASK                        (0xFFFFFFFFU)
+#define TRNG_ENT_ENT_SHIFT                       (0U)
+#define TRNG_ENT_ENT(x)                          (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
+/*! @} */
+
+/* The count of TRNG_ENT */
+#define TRNG_ENT_COUNT                           (16U)
+
+/*! @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */
+/*! @{ */
+#define TRNG_PKRCNT10_PKR_0_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNT10_PKR_0_CT_SHIFT             (0U)
+#define TRNG_PKRCNT10_PKR_0_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)
+#define TRNG_PKRCNT10_PKR_1_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNT10_PKR_1_CT_SHIFT             (16U)
+#define TRNG_PKRCNT10_PKR_1_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)
+/*! @} */
+
+/*! @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */
+/*! @{ */
+#define TRNG_PKRCNT32_PKR_2_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNT32_PKR_2_CT_SHIFT             (0U)
+#define TRNG_PKRCNT32_PKR_2_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)
+#define TRNG_PKRCNT32_PKR_3_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNT32_PKR_3_CT_SHIFT             (16U)
+#define TRNG_PKRCNT32_PKR_3_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)
+/*! @} */
+
+/*! @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */
+/*! @{ */
+#define TRNG_PKRCNT54_PKR_4_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNT54_PKR_4_CT_SHIFT             (0U)
+#define TRNG_PKRCNT54_PKR_4_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)
+#define TRNG_PKRCNT54_PKR_5_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNT54_PKR_5_CT_SHIFT             (16U)
+#define TRNG_PKRCNT54_PKR_5_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)
+/*! @} */
+
+/*! @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */
+/*! @{ */
+#define TRNG_PKRCNT76_PKR_6_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNT76_PKR_6_CT_SHIFT             (0U)
+#define TRNG_PKRCNT76_PKR_6_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)
+#define TRNG_PKRCNT76_PKR_7_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNT76_PKR_7_CT_SHIFT             (16U)
+#define TRNG_PKRCNT76_PKR_7_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)
+/*! @} */
+
+/*! @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */
+/*! @{ */
+#define TRNG_PKRCNT98_PKR_8_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNT98_PKR_8_CT_SHIFT             (0U)
+#define TRNG_PKRCNT98_PKR_8_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)
+#define TRNG_PKRCNT98_PKR_9_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNT98_PKR_9_CT_SHIFT             (16U)
+#define TRNG_PKRCNT98_PKR_9_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)
+/*! @} */
+
+/*! @name PKRCNTBA - Statistical Check Poker Count B and A Register */
+/*! @{ */
+#define TRNG_PKRCNTBA_PKR_A_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNTBA_PKR_A_CT_SHIFT             (0U)
+#define TRNG_PKRCNTBA_PKR_A_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)
+#define TRNG_PKRCNTBA_PKR_B_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNTBA_PKR_B_CT_SHIFT             (16U)
+#define TRNG_PKRCNTBA_PKR_B_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)
+/*! @} */
+
+/*! @name PKRCNTDC - Statistical Check Poker Count D and C Register */
+/*! @{ */
+#define TRNG_PKRCNTDC_PKR_C_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNTDC_PKR_C_CT_SHIFT             (0U)
+#define TRNG_PKRCNTDC_PKR_C_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)
+#define TRNG_PKRCNTDC_PKR_D_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNTDC_PKR_D_CT_SHIFT             (16U)
+#define TRNG_PKRCNTDC_PKR_D_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)
+/*! @} */
+
+/*! @name PKRCNTFE - Statistical Check Poker Count F and E Register */
+/*! @{ */
+#define TRNG_PKRCNTFE_PKR_E_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNTFE_PKR_E_CT_SHIFT             (0U)
+#define TRNG_PKRCNTFE_PKR_E_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)
+#define TRNG_PKRCNTFE_PKR_F_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNTFE_PKR_F_CT_SHIFT             (16U)
+#define TRNG_PKRCNTFE_PKR_F_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)
+/*! @} */
+
+/*! @name SEC_CFG - Security Configuration Register */
+/*! @{ */
+#define TRNG_SEC_CFG_UNUSED0_MASK                (0x1U)
+#define TRNG_SEC_CFG_UNUSED0_SHIFT               (0U)
+#define TRNG_SEC_CFG_UNUSED0(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK)
+#define TRNG_SEC_CFG_NO_PRGM_MASK                (0x2U)
+#define TRNG_SEC_CFG_NO_PRGM_SHIFT               (1U)
+/*! NO_PRGM
+ *  0b0..Programability of registers controlled only by the Miscellaneous Control Register's access mode bit.
+ *  0b1..Overides Miscellaneous Control Register access mode and prevents TRNG register programming.
+ */
+#define TRNG_SEC_CFG_NO_PRGM(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
+#define TRNG_SEC_CFG_UNUSED2_MASK                (0x4U)
+#define TRNG_SEC_CFG_UNUSED2_SHIFT               (2U)
+#define TRNG_SEC_CFG_UNUSED2(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK)
+/*! @} */
+
+/*! @name INT_CTRL - Interrupt Control Register */
+/*! @{ */
+#define TRNG_INT_CTRL_HW_ERR_MASK                (0x1U)
+#define TRNG_INT_CTRL_HW_ERR_SHIFT               (0U)
+/*! HW_ERR
+ *  0b0..Corresponding bit of INT_STATUS register cleared.
+ *  0b1..Corresponding bit of INT_STATUS register active.
+ */
+#define TRNG_INT_CTRL_HW_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
+#define TRNG_INT_CTRL_ENT_VAL_MASK               (0x2U)
+#define TRNG_INT_CTRL_ENT_VAL_SHIFT              (1U)
+/*! ENT_VAL
+ *  0b0..Same behavior as bit 0 of this register.
+ *  0b1..Same behavior as bit 0 of this register.
+ */
+#define TRNG_INT_CTRL_ENT_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
+#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK           (0x4U)
+#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT          (2U)
+/*! FRQ_CT_FAIL
+ *  0b0..Same behavior as bit 0 of this register.
+ *  0b1..Same behavior as bit 0 of this register.
+ */
+#define TRNG_INT_CTRL_FRQ_CT_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
+#define TRNG_INT_CTRL_UNUSED_MASK                (0xFFFFFFF8U)
+#define TRNG_INT_CTRL_UNUSED_SHIFT               (3U)
+#define TRNG_INT_CTRL_UNUSED(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)
+/*! @} */
+
+/*! @name INT_MASK - Mask Register */
+/*! @{ */
+#define TRNG_INT_MASK_HW_ERR_MASK                (0x1U)
+#define TRNG_INT_MASK_HW_ERR_SHIFT               (0U)
+/*! HW_ERR
+ *  0b0..Corresponding interrupt of INT_STATUS is masked.
+ *  0b1..Corresponding bit of INT_STATUS is active.
+ */
+#define TRNG_INT_MASK_HW_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
+#define TRNG_INT_MASK_ENT_VAL_MASK               (0x2U)
+#define TRNG_INT_MASK_ENT_VAL_SHIFT              (1U)
+/*! ENT_VAL
+ *  0b0..Same behavior as bit 0 of this register.
+ *  0b1..Same behavior as bit 0 of this register.
+ */
+#define TRNG_INT_MASK_ENT_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
+#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK           (0x4U)
+#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT          (2U)
+/*! FRQ_CT_FAIL
+ *  0b0..Same behavior as bit 0 of this register.
+ *  0b1..Same behavior as bit 0 of this register.
+ */
+#define TRNG_INT_MASK_FRQ_CT_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
+/*! @} */
+
+/*! @name INT_STATUS - Interrupt Status Register */
+/*! @{ */
+#define TRNG_INT_STATUS_HW_ERR_MASK              (0x1U)
+#define TRNG_INT_STATUS_HW_ERR_SHIFT             (0U)
+/*! HW_ERR
+ *  0b0..no error
+ *  0b1..error detected.
+ */
+#define TRNG_INT_STATUS_HW_ERR(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
+#define TRNG_INT_STATUS_ENT_VAL_MASK             (0x2U)
+#define TRNG_INT_STATUS_ENT_VAL_SHIFT            (1U)
+/*! ENT_VAL
+ *  0b0..Busy generation entropy. Any value read is invalid.
+ *  0b1..TRNG can be stopped and entropy is valid if read.
+ */
+#define TRNG_INT_STATUS_ENT_VAL(x)               (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
+#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK         (0x4U)
+#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT        (2U)
+/*! FRQ_CT_FAIL
+ *  0b0..No hardware nor self test frequency errors.
+ *  0b1..The frequency counter has detected a failure.
+ */
+#define TRNG_INT_STATUS_FRQ_CT_FAIL(x)           (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
+/*! @} */
+
+/*! @name VID1 - Version ID Register (MS) */
+/*! @{ */
+#define TRNG_VID1_MIN_REV_MASK                   (0xFFU)
+#define TRNG_VID1_MIN_REV_SHIFT                  (0U)
+/*! MIN_REV
+ *  0b00000000..Minor revision number for TRNG.
+ */
+#define TRNG_VID1_MIN_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)
+#define TRNG_VID1_MAJ_REV_MASK                   (0xFF00U)
+#define TRNG_VID1_MAJ_REV_SHIFT                  (8U)
+/*! MAJ_REV
+ *  0b00000001..Major revision number for TRNG.
+ */
+#define TRNG_VID1_MAJ_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)
+#define TRNG_VID1_IP_ID_MASK                     (0xFFFF0000U)
+#define TRNG_VID1_IP_ID_SHIFT                    (16U)
+/*! IP_ID
+ *  0b0000000000110000..ID for TRNG.
+ */
+#define TRNG_VID1_IP_ID(x)                       (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)
+/*! @} */
+
+/*! @name VID2 - Version ID Register (LS) */
+/*! @{ */
+#define TRNG_VID2_CONFIG_OPT_MASK                (0xFFU)
+#define TRNG_VID2_CONFIG_OPT_SHIFT               (0U)
+/*! CONFIG_OPT
+ *  0b00000000..TRNG_CONFIG_OPT for TRNG.
+ */
+#define TRNG_VID2_CONFIG_OPT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)
+#define TRNG_VID2_ECO_REV_MASK                   (0xFF00U)
+#define TRNG_VID2_ECO_REV_SHIFT                  (8U)
+/*! ECO_REV
+ *  0b00000000..TRNG_ECO_REV for TRNG.
+ */
+#define TRNG_VID2_ECO_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)
+#define TRNG_VID2_INTG_OPT_MASK                  (0xFF0000U)
+#define TRNG_VID2_INTG_OPT_SHIFT                 (16U)
+/*! INTG_OPT
+ *  0b00000000..INTG_OPT for TRNG.
+ */
+#define TRNG_VID2_INTG_OPT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)
+#define TRNG_VID2_ERA_MASK                       (0xFF000000U)
+#define TRNG_VID2_ERA_SHIFT                      (24U)
+/*! ERA
+ *  0b00000000..COMPILE_OPT for TRNG.
+ */
+#define TRNG_VID2_ERA(x)                         (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group TRNG_Register_Masks */
+
+
+/* TRNG - Peripheral instance base addresses */
+/** Peripheral TRNG base address */
+#define TRNG_BASE                                (0x41029000u)
+/** Peripheral TRNG base pointer */
+#define TRNG                                     ((TRNG_Type *)TRNG_BASE)
+/** Array initializer of TRNG peripheral base addresses */
+#define TRNG_BASE_ADDRS                          { TRNG_BASE }
+/** Array initializer of TRNG peripheral base pointers */
+#define TRNG_BASE_PTRS                           { TRNG }
+/** Interrupt vectors for the TRNG peripheral type */
+#define TRNG_IRQS                                { TRNG_IRQn }
+/** Backward compatibility macros */
+#define TRNG0                                    TRNG
+
+
+/*!
+ * @}
+ */ /* end of group TRNG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- TSTMR Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TSTMR_Peripheral_Access_Layer TSTMR Peripheral Access Layer
+ * @{
+ */
+
+/** TSTMR - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t L;                                 /**< Time Stamp Timer Register Low, offset: 0x0 */
+  __I  uint32_t H;                                 /**< Time Stamp Timer Register High, offset: 0x4 */
+} TSTMR_Type;
+
+/* ----------------------------------------------------------------------------
+   -- TSTMR Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TSTMR_Register_Masks TSTMR Register Masks
+ * @{
+ */
+
+/*! @name L - Time Stamp Timer Register Low */
+/*! @{ */
+#define TSTMR_L_VALUE_MASK                       (0xFFFFFFFFU)
+#define TSTMR_L_VALUE_SHIFT                      (0U)
+#define TSTMR_L_VALUE(x)                         (((uint32_t)(((uint32_t)(x)) << TSTMR_L_VALUE_SHIFT)) & TSTMR_L_VALUE_MASK)
+/*! @} */
+
+/*! @name H - Time Stamp Timer Register High */
+/*! @{ */
+#define TSTMR_H_VALUE_MASK                       (0xFFFFFFU)
+#define TSTMR_H_VALUE_SHIFT                      (0U)
+#define TSTMR_H_VALUE(x)                         (((uint32_t)(((uint32_t)(x)) << TSTMR_H_VALUE_SHIFT)) & TSTMR_H_VALUE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group TSTMR_Register_Masks */
+
+
+/* TSTMR - Peripheral instance base addresses */
+/** Peripheral TSTMRA base address */
+#define TSTMRA_BASE                              (0x40034000u)
+/** Peripheral TSTMRA base pointer */
+#define TSTMRA                                   ((TSTMR_Type *)TSTMRA_BASE)
+/** Array initializer of TSTMR peripheral base addresses */
+#define TSTMR_BASE_ADDRS                         { TSTMRA_BASE }
+/** Array initializer of TSTMR peripheral base pointers */
+#define TSTMR_BASE_PTRS                          { TSTMRA }
+
+/*!
+ * @}
+ */ /* end of group TSTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t PERID;                              /**< Peripheral ID register, offset: 0x0 */
+       uint8_t RESERVED_0[3];
+  __I  uint8_t IDCOMP;                             /**< Peripheral ID Complement register, offset: 0x4 */
+       uint8_t RESERVED_1[3];
+  __I  uint8_t REV;                                /**< Peripheral Revision register, offset: 0x8 */
+       uint8_t RESERVED_2[3];
+  __I  uint8_t ADDINFO;                            /**< Peripheral Additional Info register, offset: 0xC */
+       uint8_t RESERVED_3[15];
+  __IO uint8_t OTGCTL;                             /**< OTG Control register, offset: 0x1C */
+       uint8_t RESERVED_4[99];
+  __IO uint8_t ISTAT;                              /**< Interrupt Status register, offset: 0x80 */
+       uint8_t RESERVED_5[3];
+  __IO uint8_t INTEN;                              /**< Interrupt Enable register, offset: 0x84 */
+       uint8_t RESERVED_6[3];
+  __IO uint8_t ERRSTAT;                            /**< Error Interrupt Status register, offset: 0x88 */
+       uint8_t RESERVED_7[3];
+  __IO uint8_t ERREN;                              /**< Error Interrupt Enable register, offset: 0x8C */
+       uint8_t RESERVED_8[3];
+  __I  uint8_t STAT;                               /**< Status register, offset: 0x90 */
+       uint8_t RESERVED_9[3];
+  __IO uint8_t CTL;                                /**< Control register, offset: 0x94 */
+       uint8_t RESERVED_10[3];
+  __IO uint8_t ADDR;                               /**< Address register, offset: 0x98 */
+       uint8_t RESERVED_11[3];
+  __IO uint8_t BDTPAGE1;                           /**< BDT Page register 1, offset: 0x9C */
+       uint8_t RESERVED_12[3];
+  __IO uint8_t FRMNUML;                            /**< Frame Number register Low, offset: 0xA0 */
+       uint8_t RESERVED_13[3];
+  __IO uint8_t FRMNUMH;                            /**< Frame Number register High, offset: 0xA4 */
+       uint8_t RESERVED_14[11];
+  __IO uint8_t BDTPAGE2;                           /**< BDT Page Register 2, offset: 0xB0 */
+       uint8_t RESERVED_15[3];
+  __IO uint8_t BDTPAGE3;                           /**< BDT Page Register 3, offset: 0xB4 */
+       uint8_t RESERVED_16[11];
+  struct {                                         /* offset: 0xC0, array step: 0x4 */
+    __IO uint8_t ENDPT;                              /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+         uint8_t RESERVED_0[3];
+  } ENDPOINT[16];
+  __IO uint8_t USBCTRL;                            /**< USB Control register, offset: 0x100 */
+       uint8_t RESERVED_17[3];
+  __I  uint8_t OBSERVE;                            /**< USB OTG Observe register, offset: 0x104 */
+       uint8_t RESERVED_18[3];
+  __IO uint8_t CONTROL;                            /**< USB OTG Control register, offset: 0x108 */
+       uint8_t RESERVED_19[3];
+  __IO uint8_t USBTRC0;                            /**< USB Transceiver Control register 0, offset: 0x10C */
+       uint8_t RESERVED_20[23];
+  __IO uint8_t KEEP_ALIVE_CTRL;                    /**< Keep Alive mode control, offset: 0x124 */
+       uint8_t RESERVED_21[3];
+  __IO uint8_t KEEP_ALIVE_WKCTRL;                  /**< Keep Alive mode wakeup control, offset: 0x128 */
+       uint8_t RESERVED_22[3];
+  __IO uint8_t MISCCTRL;                           /**< Miscellaneous Control register, offset: 0x12C */
+       uint8_t RESERVED_23[3];
+  __IO uint8_t STALL_IL_DIS;                       /**< Peripheral mode stall disable for endpoints 7 to 0 in IN direction, offset: 0x130 */
+       uint8_t RESERVED_24[3];
+  __IO uint8_t STALL_IH_DIS;                       /**< Peripheral mode stall disable for endpoints 15 to 8 in IN direction, offset: 0x134 */
+       uint8_t RESERVED_25[3];
+  __IO uint8_t STALL_OL_DIS;                       /**< Peripheral mode stall disable for endpoints 7 to 0 in OUT direction, offset: 0x138 */
+       uint8_t RESERVED_26[3];
+  __IO uint8_t STALL_OH_DIS;                       /**< Peripheral mode stall disable for endpoints 15 to 8 in OUT direction, offset: 0x13C */
+       uint8_t RESERVED_27[3];
+  __IO uint8_t CLK_RECOVER_CTRL;                   /**< USB Clock recovery control, offset: 0x140 */
+       uint8_t RESERVED_28[3];
+  __IO uint8_t CLK_RECOVER_IRC_EN;                 /**< IRC48MFIRC oscillator enable register, offset: 0x144 */
+       uint8_t RESERVED_29[15];
+  __IO uint8_t CLK_RECOVER_INT_EN;                 /**< Clock recovery combined interrupt enable, offset: 0x154 */
+       uint8_t RESERVED_30[7];
+  __IO uint8_t CLK_RECOVER_INT_STATUS;             /**< Clock recovery separated interrupt status, offset: 0x15C */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/*! @name PERID - Peripheral ID register */
+/*! @{ */
+#define USB_PERID_ID_MASK                        (0x3FU)
+#define USB_PERID_ID_SHIFT                       (0U)
+#define USB_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
+/*! @} */
+
+/*! @name IDCOMP - Peripheral ID Complement register */
+/*! @{ */
+#define USB_IDCOMP_NID_MASK                      (0x3FU)
+#define USB_IDCOMP_NID_SHIFT                     (0U)
+#define USB_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
+/*! @} */
+
+/*! @name REV - Peripheral Revision register */
+/*! @{ */
+#define USB_REV_REV_MASK                         (0xFFU)
+#define USB_REV_REV_SHIFT                        (0U)
+#define USB_REV_REV(x)                           (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
+/*! @} */
+
+/*! @name ADDINFO - Peripheral Additional Info register */
+/*! @{ */
+#define USB_ADDINFO_IEHOST_MASK                  (0x1U)
+#define USB_ADDINFO_IEHOST_SHIFT                 (0U)
+#define USB_ADDINFO_IEHOST(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
+/*! @} */
+
+/*! @name OTGCTL - OTG Control register */
+/*! @{ */
+#define USB_OTGCTL_DPHIGH_MASK                   (0x80U)
+#define USB_OTGCTL_DPHIGH_SHIFT                  (7U)
+/*! DPHIGH - D+ Data Line pullup resistor enable
+ *  0b0..D+ pullup resistor is not enabled
+ *  0b1..D+ pullup resistor is enabled
+ */
+#define USB_OTGCTL_DPHIGH(x)                     (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
+/*! @} */
+
+/*! @name ISTAT - Interrupt Status register */
+/*! @{ */
+#define USB_ISTAT_USBRST_MASK                    (0x1U)
+#define USB_ISTAT_USBRST_SHIFT                   (0U)
+#define USB_ISTAT_USBRST(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
+#define USB_ISTAT_ERROR_MASK                     (0x2U)
+#define USB_ISTAT_ERROR_SHIFT                    (1U)
+#define USB_ISTAT_ERROR(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
+#define USB_ISTAT_SOFTOK_MASK                    (0x4U)
+#define USB_ISTAT_SOFTOK_SHIFT                   (2U)
+#define USB_ISTAT_SOFTOK(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
+#define USB_ISTAT_TOKDNE_MASK                    (0x8U)
+#define USB_ISTAT_TOKDNE_SHIFT                   (3U)
+#define USB_ISTAT_TOKDNE(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
+#define USB_ISTAT_SLEEP_MASK                     (0x10U)
+#define USB_ISTAT_SLEEP_SHIFT                    (4U)
+#define USB_ISTAT_SLEEP(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
+#define USB_ISTAT_RESUME_MASK                    (0x20U)
+#define USB_ISTAT_RESUME_SHIFT                   (5U)
+#define USB_ISTAT_RESUME(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
+#define USB_ISTAT_STALL_MASK                     (0x80U)
+#define USB_ISTAT_STALL_SHIFT                    (7U)
+#define USB_ISTAT_STALL(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
+/*! @} */
+
+/*! @name INTEN - Interrupt Enable register */
+/*! @{ */
+#define USB_INTEN_USBRSTEN_MASK                  (0x1U)
+#define USB_INTEN_USBRSTEN_SHIFT                 (0U)
+/*! USBRSTEN - USBRST Interrupt Enable
+ *  0b0..Disables the USBRST interrupt.
+ *  0b1..Enables the USBRST interrupt.
+ */
+#define USB_INTEN_USBRSTEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
+#define USB_INTEN_ERROREN_MASK                   (0x2U)
+#define USB_INTEN_ERROREN_SHIFT                  (1U)
+/*! ERROREN - ERROR Interrupt Enable
+ *  0b0..Disables the ERROR interrupt.
+ *  0b1..Enables the ERROR interrupt.
+ */
+#define USB_INTEN_ERROREN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
+#define USB_INTEN_SOFTOKEN_MASK                  (0x4U)
+#define USB_INTEN_SOFTOKEN_SHIFT                 (2U)
+/*! SOFTOKEN - SOFTOK Interrupt Enable
+ *  0b0..Disbles the SOFTOK interrupt.
+ *  0b1..Enables the SOFTOK interrupt.
+ */
+#define USB_INTEN_SOFTOKEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
+#define USB_INTEN_TOKDNEEN_MASK                  (0x8U)
+#define USB_INTEN_TOKDNEEN_SHIFT                 (3U)
+/*! TOKDNEEN - TOKDNE Interrupt Enable
+ *  0b0..Disables the TOKDNE interrupt.
+ *  0b1..Enables the TOKDNE interrupt.
+ */
+#define USB_INTEN_TOKDNEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
+#define USB_INTEN_SLEEPEN_MASK                   (0x10U)
+#define USB_INTEN_SLEEPEN_SHIFT                  (4U)
+/*! SLEEPEN - SLEEP Interrupt Enable
+ *  0b0..Disables the SLEEP interrupt.
+ *  0b1..Enables the SLEEP interrupt.
+ */
+#define USB_INTEN_SLEEPEN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
+#define USB_INTEN_RESUMEEN_MASK                  (0x20U)
+#define USB_INTEN_RESUMEEN_SHIFT                 (5U)
+/*! RESUMEEN - RESUME Interrupt Enable
+ *  0b0..Disables the RESUME interrupt.
+ *  0b1..Enables the RESUME interrupt.
+ */
+#define USB_INTEN_RESUMEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
+#define USB_INTEN_STALLEN_MASK                   (0x80U)
+#define USB_INTEN_STALLEN_SHIFT                  (7U)
+/*! STALLEN - STALL Interrupt Enable
+ *  0b0..Diasbles the STALL interrupt.
+ *  0b1..Enables the STALL interrupt.
+ */
+#define USB_INTEN_STALLEN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
+/*! @} */
+
+/*! @name ERRSTAT - Error Interrupt Status register */
+/*! @{ */
+#define USB_ERRSTAT_PIDERR_MASK                  (0x1U)
+#define USB_ERRSTAT_PIDERR_SHIFT                 (0U)
+#define USB_ERRSTAT_PIDERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
+#define USB_ERRSTAT_CRC5EOF_MASK                 (0x2U)
+#define USB_ERRSTAT_CRC5EOF_SHIFT                (1U)
+#define USB_ERRSTAT_CRC5EOF(x)                   (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
+#define USB_ERRSTAT_CRC16_MASK                   (0x4U)
+#define USB_ERRSTAT_CRC16_SHIFT                  (2U)
+#define USB_ERRSTAT_CRC16(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
+#define USB_ERRSTAT_DFN8_MASK                    (0x8U)
+#define USB_ERRSTAT_DFN8_SHIFT                   (3U)
+#define USB_ERRSTAT_DFN8(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
+#define USB_ERRSTAT_BTOERR_MASK                  (0x10U)
+#define USB_ERRSTAT_BTOERR_SHIFT                 (4U)
+#define USB_ERRSTAT_BTOERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
+#define USB_ERRSTAT_DMAERR_MASK                  (0x20U)
+#define USB_ERRSTAT_DMAERR_SHIFT                 (5U)
+#define USB_ERRSTAT_DMAERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
+#define USB_ERRSTAT_OWNERR_MASK                  (0x40U)
+#define USB_ERRSTAT_OWNERR_SHIFT                 (6U)
+#define USB_ERRSTAT_OWNERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK)
+#define USB_ERRSTAT_BTSERR_MASK                  (0x80U)
+#define USB_ERRSTAT_BTSERR_SHIFT                 (7U)
+#define USB_ERRSTAT_BTSERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
+/*! @} */
+
+/*! @name ERREN - Error Interrupt Enable register */
+/*! @{ */
+#define USB_ERREN_PIDERREN_MASK                  (0x1U)
+#define USB_ERREN_PIDERREN_SHIFT                 (0U)
+/*! PIDERREN - PIDERR Interrupt Enable
+ *  0b0..Disables the PIDERR interrupt.
+ *  0b1..Enters the PIDERR interrupt.
+ */
+#define USB_ERREN_PIDERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
+#define USB_ERREN_CRC5EOFEN_MASK                 (0x2U)
+#define USB_ERREN_CRC5EOFEN_SHIFT                (1U)
+/*! CRC5EOFEN - CRC5/EOF Interrupt Enable
+ *  0b0..Disables the CRC5/EOF interrupt.
+ *  0b1..Enables the CRC5/EOF interrupt.
+ */
+#define USB_ERREN_CRC5EOFEN(x)                   (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
+#define USB_ERREN_CRC16EN_MASK                   (0x4U)
+#define USB_ERREN_CRC16EN_SHIFT                  (2U)
+/*! CRC16EN - CRC16 Interrupt Enable
+ *  0b0..Disables the CRC16 interrupt.
+ *  0b1..Enables the CRC16 interrupt.
+ */
+#define USB_ERREN_CRC16EN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
+#define USB_ERREN_DFN8EN_MASK                    (0x8U)
+#define USB_ERREN_DFN8EN_SHIFT                   (3U)
+/*! DFN8EN - DFN8 Interrupt Enable
+ *  0b0..Disables the DFN8 interrupt.
+ *  0b1..Enables the DFN8 interrupt.
+ */
+#define USB_ERREN_DFN8EN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
+#define USB_ERREN_BTOERREN_MASK                  (0x10U)
+#define USB_ERREN_BTOERREN_SHIFT                 (4U)
+/*! BTOERREN - BTOERR Interrupt Enable
+ *  0b0..Disables the BTOERR interrupt.
+ *  0b1..Enables the BTOERR interrupt.
+ */
+#define USB_ERREN_BTOERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
+#define USB_ERREN_DMAERREN_MASK                  (0x20U)
+#define USB_ERREN_DMAERREN_SHIFT                 (5U)
+/*! DMAERREN - DMAERR Interrupt Enable
+ *  0b0..Disables the DMAERR interrupt.
+ *  0b1..Enables the DMAERR interrupt.
+ */
+#define USB_ERREN_DMAERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
+#define USB_ERREN_OWNERREN_MASK                  (0x40U)
+#define USB_ERREN_OWNERREN_SHIFT                 (6U)
+/*! OWNERREN - OWNERR Interrupt Enable
+ *  0b0..Disables the OWNERR interrupt.
+ *  0b1..Enables the OWNERR interrupt.
+ */
+#define USB_ERREN_OWNERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK)
+#define USB_ERREN_BTSERREN_MASK                  (0x80U)
+#define USB_ERREN_BTSERREN_SHIFT                 (7U)
+/*! BTSERREN - BTSERR Interrupt Enable
+ *  0b0..Disables the BTSERR interrupt.
+ *  0b1..Enables the BTSERR interrupt.
+ */
+#define USB_ERREN_BTSERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
+/*! @} */
+
+/*! @name STAT - Status register */
+/*! @{ */
+#define USB_STAT_ODD_MASK                        (0x4U)
+#define USB_STAT_ODD_SHIFT                       (2U)
+#define USB_STAT_ODD(x)                          (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
+#define USB_STAT_TX_MASK                         (0x8U)
+#define USB_STAT_TX_SHIFT                        (3U)
+/*! TX - Transmit Indicator
+ *  0b0..The most recent transaction was a receive operation.
+ *  0b1..The most recent transaction was a transmit operation.
+ */
+#define USB_STAT_TX(x)                           (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
+#define USB_STAT_ENDP_MASK                       (0xF0U)
+#define USB_STAT_ENDP_SHIFT                      (4U)
+#define USB_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
+/*! @} */
+
+/*! @name CTL - Control register */
+/*! @{ */
+#define USB_CTL_USBENSOFEN_MASK                  (0x1U)
+#define USB_CTL_USBENSOFEN_SHIFT                 (0U)
+/*! USBENSOFEN - USB Enable
+ *  0b0..Disables the USB Module.
+ *  0b1..Enables the USB Module.
+ */
+#define USB_CTL_USBENSOFEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
+#define USB_CTL_ODDRST_MASK                      (0x2U)
+#define USB_CTL_ODDRST_SHIFT                     (1U)
+#define USB_CTL_ODDRST(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
+#define USB_CTL_RESUME_MASK                      (0x4U)
+#define USB_CTL_RESUME_SHIFT                     (2U)
+#define USB_CTL_RESUME(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
+#define USB_CTL_HOSTMODEEN_MASK                  (0x8U)
+#define USB_CTL_HOSTMODEEN_SHIFT                 (3U)
+/*! HOSTMODEEN - Host mode enable
+ *  0b0..USB Module operates in Device mode.
+ *  0b1..USB Module operates in Host mode. In Host mode, the USB module performs USB transactions under the programmed control of the host processor.
+ */
+#define USB_CTL_HOSTMODEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK          (0x20U)
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT         (5U)
+#define USB_CTL_TXSUSPENDTOKENBUSY(x)            (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
+#define USB_CTL_SE0_MASK                         (0x40U)
+#define USB_CTL_SE0_SHIFT                        (6U)
+#define USB_CTL_SE0(x)                           (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
+#define USB_CTL_JSTATE_MASK                      (0x80U)
+#define USB_CTL_JSTATE_SHIFT                     (7U)
+#define USB_CTL_JSTATE(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
+/*! @} */
+
+/*! @name ADDR - Address register */
+/*! @{ */
+#define USB_ADDR_ADDR_MASK                       (0x7FU)
+#define USB_ADDR_ADDR_SHIFT                      (0U)
+#define USB_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
+/*! @} */
+
+/*! @name BDTPAGE1 - BDT Page register 1 */
+/*! @{ */
+#define USB_BDTPAGE1_BDTBA_MASK                  (0xFEU)
+#define USB_BDTPAGE1_BDTBA_SHIFT                 (1U)
+#define USB_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
+/*! @} */
+
+/*! @name FRMNUML - Frame Number register Low */
+/*! @{ */
+#define USB_FRMNUML_FRM_MASK                     (0xFFU)
+#define USB_FRMNUML_FRM_SHIFT                    (0U)
+#define USB_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
+/*! @} */
+
+/*! @name FRMNUMH - Frame Number register High */
+/*! @{ */
+#define USB_FRMNUMH_FRM_MASK                     (0x7U)
+#define USB_FRMNUMH_FRM_SHIFT                    (0U)
+#define USB_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
+/*! @} */
+
+/*! @name BDTPAGE2 - BDT Page Register 2 */
+/*! @{ */
+#define USB_BDTPAGE2_BDTBA_MASK                  (0xFFU)
+#define USB_BDTPAGE2_BDTBA_SHIFT                 (0U)
+#define USB_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
+/*! @} */
+
+/*! @name BDTPAGE3 - BDT Page Register 3 */
+/*! @{ */
+#define USB_BDTPAGE3_BDTBA_MASK                  (0xFFU)
+#define USB_BDTPAGE3_BDTBA_SHIFT                 (0U)
+#define USB_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
+/*! @} */
+
+/*! @name ENDPT - Endpoint Control register */
+/*! @{ */
+#define USB_ENDPT_EPHSHK_MASK                    (0x1U)
+#define USB_ENDPT_EPHSHK_SHIFT                   (0U)
+#define USB_ENDPT_EPHSHK(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
+#define USB_ENDPT_EPSTALL_MASK                   (0x2U)
+#define USB_ENDPT_EPSTALL_SHIFT                  (1U)
+#define USB_ENDPT_EPSTALL(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
+#define USB_ENDPT_EPTXEN_MASK                    (0x4U)
+#define USB_ENDPT_EPTXEN_SHIFT                   (2U)
+#define USB_ENDPT_EPTXEN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
+#define USB_ENDPT_EPRXEN_MASK                    (0x8U)
+#define USB_ENDPT_EPRXEN_SHIFT                   (3U)
+#define USB_ENDPT_EPRXEN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
+#define USB_ENDPT_EPCTLDIS_MASK                  (0x10U)
+#define USB_ENDPT_EPCTLDIS_SHIFT                 (4U)
+#define USB_ENDPT_EPCTLDIS(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
+/*! @} */
+
+/* The count of USB_ENDPT */
+#define USB_ENDPT_COUNT                          (16U)
+
+/*! @name USBCTRL - USB Control register */
+/*! @{ */
+#define USB_USBCTRL_UARTSEL_MASK                 (0x10U)
+#define USB_USBCTRL_UARTSEL_SHIFT                (4U)
+/*! UARTSEL - UART Select
+ *  0b0..USB signals are not used as UART signals.
+ *  0b1..USB signals are used as UART signals.
+ */
+#define USB_USBCTRL_UARTSEL(x)                   (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK)
+#define USB_USBCTRL_UARTCHLS_MASK                (0x20U)
+#define USB_USBCTRL_UARTCHLS_SHIFT               (5U)
+/*! UARTCHLS - UART Signal Channel Select
+ *  0b0..USB DP/DM signals are used as UART TX/RX.
+ *  0b1..USB DP/DM signals are used as UART RX/TX.
+ */
+#define USB_USBCTRL_UARTCHLS(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK)
+#define USB_USBCTRL_PDE_MASK                     (0x40U)
+#define USB_USBCTRL_PDE_SHIFT                    (6U)
+/*! PDE - Pulldown enable
+ *  0b0..Weak pulldowns are disabled on D+ and D-.
+ *  0b1..Weak pulldowns are enabled on D+ and D-.
+ */
+#define USB_USBCTRL_PDE(x)                       (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
+#define USB_USBCTRL_SUSP_MASK                    (0x80U)
+#define USB_USBCTRL_SUSP_SHIFT                   (7U)
+/*! SUSP - Suspend
+ *  0b0..USB transceiver is not in the Suspend state.
+ *  0b1..USB transceiver is in the Suspend state.
+ */
+#define USB_USBCTRL_SUSP(x)                      (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
+/*! @} */
+
+/*! @name OBSERVE - USB OTG Observe register */
+/*! @{ */
+#define USB_OBSERVE_DMPD_MASK                    (0x10U)
+#define USB_OBSERVE_DMPD_SHIFT                   (4U)
+/*! DMPD - DMPD
+ *  0b0..D- pulldown is disabled.
+ *  0b1..D- pulldown is enabled.
+ */
+#define USB_OBSERVE_DMPD(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
+#define USB_OBSERVE_DPPD_MASK                    (0x40U)
+#define USB_OBSERVE_DPPD_SHIFT                   (6U)
+/*! DPPD - DPPD
+ *  0b0..D+ pulldown is disabled.
+ *  0b1..D+ pulldown is enabled.
+ */
+#define USB_OBSERVE_DPPD(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
+#define USB_OBSERVE_DPPU_MASK                    (0x80U)
+#define USB_OBSERVE_DPPU_SHIFT                   (7U)
+/*! DPPU - DPPU
+ *  0b0..D+ pullup disabled.
+ *  0b1..D+ pullup enabled.
+ */
+#define USB_OBSERVE_DPPU(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
+/*! @} */
+
+/*! @name CONTROL - USB OTG Control register */
+/*! @{ */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK          (0x10U)
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT         (4U)
+/*! DPPULLUPNONOTG - DPPULLUPNONOTG
+ *  0b0..DP Pullup in non-OTG Device mode is not enabled.
+ *  0b1..DP Pullup in non-OTG Device mode is enabled.
+ */
+#define USB_CONTROL_DPPULLUPNONOTG(x)            (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
+/*! @} */
+
+/*! @name USBTRC0 - USB Transceiver Control register 0 */
+/*! @{ */
+#define USB_USBTRC0_USB_RESUME_INT_MASK          (0x1U)
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT         (0U)
+/*! USB_RESUME_INT - USB Asynchronous Interrupt
+ *  0b0..No interrupt was generated.
+ *  0b1..Interrupt was generated because of the USB asynchronous interrupt.
+ */
+#define USB_USBTRC0_USB_RESUME_INT(x)            (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
+#define USB_USBTRC0_SYNC_DET_MASK                (0x2U)
+#define USB_USBTRC0_SYNC_DET_SHIFT               (1U)
+/*! SYNC_DET - Synchronous USB Interrupt Detect
+ *  0b0..Synchronous interrupt has not been detected.
+ *  0b1..Synchronous interrupt has been detected.
+ */
+#define USB_USBTRC0_SYNC_DET(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK    (0x4U)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT   (2U)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x)      (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
+#define USB_USBTRC0_VREDG_DET_MASK               (0x8U)
+#define USB_USBTRC0_VREDG_DET_SHIFT              (3U)
+/*! VREDG_DET - VREGIN Rising Edge Interrupt Detect
+ *  0b0..VREGIN rising edge interrupt has not been detected.
+ *  0b1..VREGIN rising edge interrupt has been detected.
+ */
+#define USB_USBTRC0_VREDG_DET(x)                 (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK)
+#define USB_USBTRC0_VFEDG_DET_MASK               (0x10U)
+#define USB_USBTRC0_VFEDG_DET_SHIFT              (4U)
+/*! VFEDG_DET - VREGIN Falling Edge Interrupt Detect
+ *  0b0..VREGIN falling edge interrupt has not been detected.
+ *  0b1..VREGIN falling edge interrupt has been detected.
+ */
+#define USB_USBTRC0_VFEDG_DET(x)                 (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK)
+#define USB_USBTRC0_USBRESMEN_MASK               (0x20U)
+#define USB_USBTRC0_USBRESMEN_SHIFT              (5U)
+/*! USBRESMEN - Asynchronous Resume Interrupt Enable
+ *  0b0..USB asynchronous wakeup from Suspend mode is disabled.
+ *  0b1..USB asynchronous wakeup from Suspend mode is enabled.
+ */
+#define USB_USBTRC0_USBRESMEN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
+#define USB_USBTRC0_VREGIN_STS_MASK              (0x40U)
+#define USB_USBTRC0_VREGIN_STS_SHIFT             (6U)
+#define USB_USBTRC0_VREGIN_STS(x)                (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREGIN_STS_SHIFT)) & USB_USBTRC0_VREGIN_STS_MASK)
+#define USB_USBTRC0_USBRESET_MASK                (0x80U)
+#define USB_USBTRC0_USBRESET_SHIFT               (7U)
+/*! USBRESET - USB Reset
+ *  0b0..Normal USB module operation.
+ *  0b1..Returns the USB module to its reset state.
+ */
+#define USB_USBTRC0_USBRESET(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
+/*! @} */
+
+/*! @name KEEP_ALIVE_CTRL - Keep Alive mode control */
+/*! @{ */
+#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK   (0x1U)
+#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT  (0U)
+#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN(x)     (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK)
+#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK   (0x2U)
+#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT  (1U)
+#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN(x)     (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK)
+#define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK (0x4U)
+#define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT (2U)
+/*! STOP_ACK_DLY_EN - STOP_ACK_DLY_EN
+ *  0b0..Enter KEEP_ALIVE mode until the USB core is idle and there is no USB AHB transfer.
+ *  0b1..Enter KEEP_ALIVE mode immediately when there is no USB AHB transfer.
+ */
+#define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN(x)   (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK)
+#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK     (0x8U)
+#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT    (3U)
+/*! WAKE_REQ_EN - WAKE_REQ_EN
+ *  0b0..USB bus wakeup request is disabled
+ *  0b1..USB bus wakeup request is enabled
+ */
+#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN(x)       (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK)
+#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK     (0x10U)
+#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT    (4U)
+#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN(x)       (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK)
+#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_MASK  (0x40U)
+#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_SHIFT (6U)
+/*! KEEP_ALIVE_STS - Keep Alive Status
+ *  0b0..USB is not in Keep Alive mode.
+ *  0b1..USB is in Keep Alive mode.
+ */
+#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS(x)    (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_MASK)
+#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK    (0x80U)
+#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT   (7U)
+#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS(x)      (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK)
+/*! @} */
+
+/*! @name KEEP_ALIVE_WKCTRL - Keep Alive mode wakeup control */
+/*! @{ */
+#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK  (0xFU)
+#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT (0U)
+/*! WAKE_ON_THIS - WAKE_ON_THIS
+ *  0b0001..Wake up after receiving OUT/SETUP token packet.
+ *  0b1101..Wake up after receiving SETUP token packet. All other values are reserved.
+ */
+#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS(x)    (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK)
+#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK    (0xF0U)
+#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT   (4U)
+#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT(x)      (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK)
+/*! @} */
+
+/*! @name MISCCTRL - Miscellaneous Control register */
+/*! @{ */
+#define USB_MISCCTRL_SOFDYNTHLD_MASK             (0x1U)
+#define USB_MISCCTRL_SOFDYNTHLD_SHIFT            (0U)
+/*! SOFDYNTHLD - Dynamic SOF Threshold Compare mode
+ *  0b0..SOF_TOK interrupt is set when byte times SOF threshold is reached.
+ *  0b1..SOF_TOK interrupt is set when 8 byte times SOF threshold is reached or overstepped.
+ */
+#define USB_MISCCTRL_SOFDYNTHLD(x)               (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFDYNTHLD_SHIFT)) & USB_MISCCTRL_SOFDYNTHLD_MASK)
+#define USB_MISCCTRL_SOFBUSSET_MASK              (0x2U)
+#define USB_MISCCTRL_SOFBUSSET_SHIFT             (1U)
+/*! SOFBUSSET - SOF_TOK Interrupt Generation Mode Select
+ *  0b0..SOF_TOK interrupt is set according to SOF threshold value.
+ *  0b1..SOF_TOK interrupt is set when SOF counter reaches 0.
+ */
+#define USB_MISCCTRL_SOFBUSSET(x)                (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFBUSSET_SHIFT)) & USB_MISCCTRL_SOFBUSSET_MASK)
+#define USB_MISCCTRL_OWNERRISODIS_MASK           (0x4U)
+#define USB_MISCCTRL_OWNERRISODIS_SHIFT          (2U)
+/*! OWNERRISODIS - OWN Error Detect for ISO IN / ISO OUT Disable
+ *  0b0..OWN error detect for ISO IN / ISO OUT is not disabled.
+ *  0b1..OWN error detect for ISO IN / ISO OUT is disabled.
+ */
+#define USB_MISCCTRL_OWNERRISODIS(x)             (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK)
+#define USB_MISCCTRL_VREDG_EN_MASK               (0x8U)
+#define USB_MISCCTRL_VREDG_EN_SHIFT              (3U)
+/*! VREDG_EN - VREGIN Rising Edge Interrupt Enable
+ *  0b0..VREGIN rising edge interrupt disabled.
+ *  0b1..VREGIN rising edge interrupt enabled.
+ */
+#define USB_MISCCTRL_VREDG_EN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK)
+#define USB_MISCCTRL_VFEDG_EN_MASK               (0x10U)
+#define USB_MISCCTRL_VFEDG_EN_SHIFT              (4U)
+/*! VFEDG_EN - VREGIN Falling Edge Interrupt Enable
+ *  0b0..VREGIN falling edge interrupt disabled.
+ *  0b1..VREGIN falling edge interrupt enabled.
+ */
+#define USB_MISCCTRL_VFEDG_EN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK)
+#define USB_MISCCTRL_STL_ADJ_EN_MASK             (0x80U)
+#define USB_MISCCTRL_STL_ADJ_EN_SHIFT            (7U)
+/*! STL_ADJ_EN - USB Peripheral mode Stall Adjust Enable
+ *  0b0..If USB_ENDPTn[END_STALL] = 1, both IN and OUT directions for the associated endpoint will be stalled
+ *  0b1..If USB_ENDPTn[END_STALL] = 1, the USB_STALL_xx_DIS registers control which directions for the associated endpoint will be stalled.
+ */
+#define USB_MISCCTRL_STL_ADJ_EN(x)               (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_STL_ADJ_EN_SHIFT)) & USB_MISCCTRL_STL_ADJ_EN_MASK)
+/*! @} */
+
+/*! @name STALL_IL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in IN direction */
+/*! @{ */
+#define USB_STALL_IL_DIS_STALL_I_DIS0_MASK       (0x1U)
+#define USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT      (0U)
+/*! STALL_I_DIS0 - STALL_I_DIS0
+ *  0b0..Endpoint 0 IN direction stall is enabled.
+ *  0b1..Endpoint 0 IN direction stall is disabled.
+ */
+#define USB_STALL_IL_DIS_STALL_I_DIS0(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS0_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS1_MASK       (0x2U)
+#define USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT      (1U)
+/*! STALL_I_DIS1 - STALL_I_DIS1
+ *  0b0..Endpoint 1 IN direction stall is enabled.
+ *  0b1..Endpoint 1 IN direction stall is disabled.
+ */
+#define USB_STALL_IL_DIS_STALL_I_DIS1(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS1_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS2_MASK       (0x4U)
+#define USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT      (2U)
+/*! STALL_I_DIS2 - STALL_I_DIS2
+ *  0b0..Endpoint 2 IN direction stall is enabled.
+ *  0b1..Endpoint 2 IN direction stall is disabled.
+ */
+#define USB_STALL_IL_DIS_STALL_I_DIS2(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS2_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS3_MASK       (0x8U)
+#define USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT      (3U)
+/*! STALL_I_DIS3 - STALL_I_DIS3
+ *  0b0..Endpoint 3 IN direction stall is enabled.
+ *  0b1..Endpoint 3 IN direction stall is disabled.
+ */
+#define USB_STALL_IL_DIS_STALL_I_DIS3(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS3_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS4_MASK       (0x10U)
+#define USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT      (4U)
+/*! STALL_I_DIS4 - STALL_I_DIS4
+ *  0b0..Endpoint 4 IN direction stall is enabled.
+ *  0b1..Endpoint 4 IN direction stall is disabled.
+ */
+#define USB_STALL_IL_DIS_STALL_I_DIS4(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS4_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS5_MASK       (0x20U)
+#define USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT      (5U)
+/*! STALL_I_DIS5 - STALL_I_DIS5
+ *  0b0..Endpoint 5 IN direction stall is enabled.
+ *  0b1..Endpoint 5 IN direction stall is disabled.
+ */
+#define USB_STALL_IL_DIS_STALL_I_DIS5(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS5_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS6_MASK       (0x40U)
+#define USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT      (6U)
+/*! STALL_I_DIS6 - STALL_I_DIS6
+ *  0b0..Endpoint 6 IN direction stall is enabled.
+ *  0b1..Endpoint 6 IN direction stall is disabled.
+ */
+#define USB_STALL_IL_DIS_STALL_I_DIS6(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS6_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS7_MASK       (0x80U)
+#define USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT      (7U)
+/*! STALL_I_DIS7 - STALL_I_DIS7
+ *  0b0..Endpoint 7 IN direction stall is enabled.
+ *  0b1..Endpoint 7 IN direction stall is disabled.
+ */
+#define USB_STALL_IL_DIS_STALL_I_DIS7(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS7_MASK)
+/*! @} */
+
+/*! @name STALL_IH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in IN direction */
+/*! @{ */
+#define USB_STALL_IH_DIS_STALL_I_DIS8_MASK       (0x1U)
+#define USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT      (0U)
+/*! STALL_I_DIS8 - STALL_I_DIS8
+ *  0b0..Endpoint 8 IN direction stall is enabled.
+ *  0b1..Endpoint 8 IN direction stall is disabled.
+ */
+#define USB_STALL_IH_DIS_STALL_I_DIS8(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS8_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS9_MASK       (0x2U)
+#define USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT      (1U)
+/*! STALL_I_DIS9 - STALL_I_DIS9
+ *  0b0..Endpoint 9 IN direction stall is enabled.
+ *  0b1..Endpoint 9 IN direction stall is disabled.
+ */
+#define USB_STALL_IH_DIS_STALL_I_DIS9(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS9_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS10_MASK      (0x4U)
+#define USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT     (2U)
+/*! STALL_I_DIS10 - STALL_I_DIS10
+ *  0b0..Endpoint 10 IN direction stall is enabled.
+ *  0b1..Endpoint 10 IN direction stall is disabled.
+ */
+#define USB_STALL_IH_DIS_STALL_I_DIS10(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS10_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS11_MASK      (0x8U)
+#define USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT     (3U)
+/*! STALL_I_DIS11 - STALL_I_DIS11
+ *  0b0..Endpoint 11 IN direction stall is enabled.
+ *  0b1..Endpoint 11 IN direction stall is disabled.
+ */
+#define USB_STALL_IH_DIS_STALL_I_DIS11(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS11_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS12_MASK      (0x10U)
+#define USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT     (4U)
+/*! STALL_I_DIS12 - STALL_I_DIS12
+ *  0b0..Endpoint 12 IN direction stall is enabled.
+ *  0b1..Endpoint 12 IN direction stall is disabled.
+ */
+#define USB_STALL_IH_DIS_STALL_I_DIS12(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS12_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS13_MASK      (0x20U)
+#define USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT     (5U)
+/*! STALL_I_DIS13 - STALL_I_DIS13
+ *  0b0..Endpoint 13 IN direction stall is enabled.
+ *  0b1..Endpoint 13 IN direction stall is disabled.
+ */
+#define USB_STALL_IH_DIS_STALL_I_DIS13(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS13_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS14_MASK      (0x40U)
+#define USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT     (6U)
+/*! STALL_I_DIS14 - STALL_I_DIS14
+ *  0b0..Endpoint 14 IN direction stall is enabled.
+ *  0b1..Endpoint 14 IN direction stall is disabled.
+ */
+#define USB_STALL_IH_DIS_STALL_I_DIS14(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS14_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS15_MASK      (0x80U)
+#define USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT     (7U)
+/*! STALL_I_DIS15 - STALL_I_DIS15
+ *  0b0..Endpoint 15 IN direction stall is enabled.
+ *  0b1..Endpoint 15 IN direction stall is disabled.
+ */
+#define USB_STALL_IH_DIS_STALL_I_DIS15(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS15_MASK)
+/*! @} */
+
+/*! @name STALL_OL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in OUT direction */
+/*! @{ */
+#define USB_STALL_OL_DIS_STALL_O_DIS0_MASK       (0x1U)
+#define USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT      (0U)
+/*! STALL_O_DIS0 - STALL_O_DIS0
+ *  0b0..Endpoint 0 OUT direction stall is enabled.
+ *  0b1..Endpoint 0 OUT direction stall is disabled.
+ */
+#define USB_STALL_OL_DIS_STALL_O_DIS0(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS0_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS1_MASK       (0x2U)
+#define USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT      (1U)
+/*! STALL_O_DIS1 - STALL_O_DIS1
+ *  0b0..Endpoint 1 OUT direction stall is enabled.
+ *  0b1..Endpoint 1 OUT direction stall is disabled.
+ */
+#define USB_STALL_OL_DIS_STALL_O_DIS1(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS1_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS2_MASK       (0x4U)
+#define USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT      (2U)
+/*! STALL_O_DIS2 - STALL_O_DIS2
+ *  0b0..Endpoint 2 OUT direction stall is enabled.
+ *  0b1..Endpoint 2 OUT direction stall is disabled.
+ */
+#define USB_STALL_OL_DIS_STALL_O_DIS2(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS2_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS3_MASK       (0x8U)
+#define USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT      (3U)
+/*! STALL_O_DIS3 - STALL_O_DIS3
+ *  0b0..Endpoint 3 OUT direction stall is enabled.
+ *  0b1..Endpoint 3 OUT direction stall is disabled.
+ */
+#define USB_STALL_OL_DIS_STALL_O_DIS3(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS3_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS4_MASK       (0x10U)
+#define USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT      (4U)
+/*! STALL_O_DIS4 - STALL_O_DIS4
+ *  0b0..Endpoint 4 OUT direction stall is enabled.
+ *  0b1..Endpoint 4 OUT direction stall is disabled.
+ */
+#define USB_STALL_OL_DIS_STALL_O_DIS4(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS4_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS5_MASK       (0x20U)
+#define USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT      (5U)
+/*! STALL_O_DIS5 - STALL_O_DIS5
+ *  0b0..Endpoint 5 OUT direction stall is enabled.
+ *  0b1..Endpoint 5 OUT direction stall is disabled.
+ */
+#define USB_STALL_OL_DIS_STALL_O_DIS5(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS5_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS6_MASK       (0x40U)
+#define USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT      (6U)
+/*! STALL_O_DIS6 - STALL_O_DIS6
+ *  0b0..Endpoint 6 OUT direction stall is enabled.
+ *  0b1..Endpoint 6 OUT direction stall is disabled.
+ */
+#define USB_STALL_OL_DIS_STALL_O_DIS6(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS6_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS7_MASK       (0x80U)
+#define USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT      (7U)
+/*! STALL_O_DIS7 - STALL_O_DIS7
+ *  0b0..Endpoint 7 OUT direction stall is enabled.
+ *  0b1..Endpoint 7 OUT direction stall is disabled.
+ */
+#define USB_STALL_OL_DIS_STALL_O_DIS7(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS7_MASK)
+/*! @} */
+
+/*! @name STALL_OH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in OUT direction */
+/*! @{ */
+#define USB_STALL_OH_DIS_STALL_O_DIS8_MASK       (0x1U)
+#define USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT      (0U)
+/*! STALL_O_DIS8 - STALL_O_DIS8
+ *  0b0..Endpoint 8 OUT direction stall is enabled.
+ *  0b1..Endpoint 8 OUT direction stall is disabled.
+ */
+#define USB_STALL_OH_DIS_STALL_O_DIS8(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS8_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS9_MASK       (0x2U)
+#define USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT      (1U)
+/*! STALL_O_DIS9 - STALL_O_DIS9
+ *  0b0..Endpoint 9 OUT direction stall is enabled.
+ *  0b1..Endpoint 9 OUT direction stall is disabled.
+ */
+#define USB_STALL_OH_DIS_STALL_O_DIS9(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS9_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS10_MASK      (0x4U)
+#define USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT     (2U)
+/*! STALL_O_DIS10 - STALL_O_DIS10
+ *  0b0..Endpoint 10 OUT direction stall is enabled.
+ *  0b1..Endpoint 10 OUT direction stall is disabled.
+ */
+#define USB_STALL_OH_DIS_STALL_O_DIS10(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS10_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS11_MASK      (0x8U)
+#define USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT     (3U)
+/*! STALL_O_DIS11 - STALL_O_DIS11
+ *  0b0..Endpoint 11 OUT direction stall is enabled.
+ *  0b1..Endpoint 11 OUT direction stall is disabled.
+ */
+#define USB_STALL_OH_DIS_STALL_O_DIS11(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS11_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS12_MASK      (0x10U)
+#define USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT     (4U)
+/*! STALL_O_DIS12 - STALL_O_DIS12
+ *  0b0..Endpoint 12 OUT direction stall is enabled.
+ *  0b1..Endpoint 12 OUT direction stall is disabled.
+ */
+#define USB_STALL_OH_DIS_STALL_O_DIS12(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS12_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS13_MASK      (0x20U)
+#define USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT     (5U)
+/*! STALL_O_DIS13 - STALL_O_DIS13
+ *  0b0..Endpoint 13 OUT direction stall is enabled.
+ *  0b1..Endpoint 13 OUT direction stall is disabled.
+ */
+#define USB_STALL_OH_DIS_STALL_O_DIS13(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS13_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS14_MASK      (0x40U)
+#define USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT     (6U)
+/*! STALL_O_DIS14 - STALL_O_DIS14
+ *  0b0..Endpoint 14 OUT direction stall is enabled.
+ *  0b1..Endpoint 14 OUT direction stall is disabled.
+ */
+#define USB_STALL_OH_DIS_STALL_O_DIS14(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS14_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS15_MASK      (0x80U)
+#define USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT     (7U)
+/*! STALL_O_DIS15 - STALL_O_DIS15
+ *  0b0..Endpoint 15 OUT direction stall is enabled.
+ *  0b1..Endpoint 15 OUT direction stall is disabled.
+ */
+#define USB_STALL_OH_DIS_STALL_O_DIS15(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS15_MASK)
+/*! @} */
+
+/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
+/*! @{ */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
+/*! RESTART_IFRTRIM_EN - Restart from IFR trim value
+ *  0b0..Trim fine adjustment always works based on the previous updated trim fine value (default).
+ *  0b1..Trim fine restarts from the IFR trim value, whenever bus_reset/bus_resume is detected or module enable is desasserted.
+ */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
+/*! RESET_RESUME_ROUGH_EN - Reset/resume to rough phase enable
+ *  0b0..Always works in tracking phase after the first time rough phase, to track transition (default).
+ *  0b1..Go back to rough stage whenever a bus reset or bus resume occurs.
+ */
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
+/*! CLOCK_RECOVER_EN - Crystal-less USB enable
+ *  0b0..Disable clock recovery block (default)
+ *  0b1..Enable clock recovery block
+ */
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
+/*! @} */
+
+/*! @name CLK_RECOVER_IRC_EN - IRC48MFIRC oscillator enable register */
+/*! @{ */
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK       (0x1U)
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT      (0U)
+/*! REG_EN - Regulator enable
+ *  0b0..IRC48M local regulator is disabled
+ *  0b1..IRC48M local regulator is enabled (default)
+ */
+#define USB_CLK_RECOVER_IRC_EN_REG_EN(x)         (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK       (0x2U)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT      (1U)
+/*! IRC_EN - IRC_EN
+ *  0b0..Disable the IRC48M module (default)
+ *  0b1..Enable the IRC48M module
+ */
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x)         (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
+/*! @} */
+
+/*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */
+/*! @{ */
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U)
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U)
+/*! OVF_ERROR_EN - OVF_ERROR_EN
+ *  0b0..The interrupt will be masked
+ *  0b1..The interrupt will be enabled (default)
+ */
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x)   (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
+/*! @} */
+
+/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
+/*! @{ */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
+/*! OVF_ERROR - OVF_ERROR
+ *  0b0..No interrupt is reported
+ *  0b1..Unmasked interrupt has been generated
+ */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x)  (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE                                (0x40045000u)
+/** Peripheral USB0 base pointer */
+#define USB0                                     ((USB_Type *)USB0_BASE)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS                           { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS                            { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS                                 { USB0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBVREG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBVREG_Peripheral_Access_Layer USBVREG Peripheral Access Layer
+ * @{
+ */
+
+/** USBVREG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< USB VREG Control Register, offset: 0x0 */
+  __IO uint32_t CFGCTRL;                           /**< USB VREG Configuration Control Register, offset: 0x4 */
+} USBVREG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USBVREG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBVREG_Register_Masks USBVREG Register Masks
+ * @{
+ */
+
+/*! @name CTRL - USB VREG Control Register */
+/*! @{ */
+#define USBVREG_CTRL_VSTBY_MASK                  (0x20000000U)
+#define USBVREG_CTRL_VSTBY_SHIFT                 (29U)
+/*! VSTBY - USB Voltage Regulator in Standby Mode during VLPR and VLPW modes
+ *  0b0..USB voltage regulator is not in standby during VLPR and VLPW modes.
+ *  0b1..USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+#define USBVREG_CTRL_VSTBY(x)                    (((uint32_t)(((uint32_t)(x)) << USBVREG_CTRL_VSTBY_SHIFT)) & USBVREG_CTRL_VSTBY_MASK)
+#define USBVREG_CTRL_SSTBY_MASK                  (0x40000000U)
+#define USBVREG_CTRL_SSTBY_SHIFT                 (30U)
+/*! SSTBY - USB Voltage Regulator in Standby Mode during Stop, VLPS, LLS and VLLS Modes
+ *  0b0..USB voltage regulator is not in standby during Stop,VLPS,LLS and VLLS modes.
+ *  0b1..USB voltage regulator is in standby during Stop,VLPS,LLS and VLLS modes.
+ */
+#define USBVREG_CTRL_SSTBY(x)                    (((uint32_t)(((uint32_t)(x)) << USBVREG_CTRL_SSTBY_SHIFT)) & USBVREG_CTRL_SSTBY_MASK)
+#define USBVREG_CTRL_EN_MASK                     (0x80000000U)
+#define USBVREG_CTRL_EN_SHIFT                    (31U)
+/*! EN - USB Voltage Regulator Enable
+ *  0b0..USB voltage regulator is disabled.
+ *  0b1..USB voltage regulator is enabled.
+ */
+#define USBVREG_CTRL_EN(x)                       (((uint32_t)(((uint32_t)(x)) << USBVREG_CTRL_EN_SHIFT)) & USBVREG_CTRL_EN_MASK)
+/*! @} */
+
+/*! @name CFGCTRL - USB VREG Configuration Control Register */
+/*! @{ */
+#define USBVREG_CFGCTRL_URWE_MASK                (0x1000000U)
+#define USBVREG_CFGCTRL_URWE_SHIFT               (24U)
+/*! URWE - USB Voltage Regulator Enable Write Enable
+ *  0b0..CTRL[EN] can not be written.
+ *  0b1..CTRL[EN] can be written.
+ */
+#define USBVREG_CFGCTRL_URWE(x)                  (((uint32_t)(((uint32_t)(x)) << USBVREG_CFGCTRL_URWE_SHIFT)) & USBVREG_CFGCTRL_URWE_MASK)
+#define USBVREG_CFGCTRL_UVSWE_MASK               (0x2000000U)
+#define USBVREG_CFGCTRL_UVSWE_SHIFT              (25U)
+/*! UVSWE - USB Voltage Regulator VLP Standby Write Enable
+ *  0b0..CTRL[VSTBY] cannot be written.
+ *  0b1..CTRL[VSTBY] can be written.
+ */
+#define USBVREG_CFGCTRL_UVSWE(x)                 (((uint32_t)(((uint32_t)(x)) << USBVREG_CFGCTRL_UVSWE_SHIFT)) & USBVREG_CFGCTRL_UVSWE_MASK)
+#define USBVREG_CFGCTRL_USSWE_MASK               (0x4000000U)
+#define USBVREG_CFGCTRL_USSWE_SHIFT              (26U)
+/*! USSWE - USB Voltage Rregulator Stop Standby Write Enable
+ *  0b0..CTRL[SSTBY] field cannot be written.
+ *  0b1..CTRL[SSTBY] can be written.
+ */
+#define USBVREG_CFGCTRL_USSWE(x)                 (((uint32_t)(((uint32_t)(x)) << USBVREG_CFGCTRL_USSWE_SHIFT)) & USBVREG_CFGCTRL_USSWE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USBVREG_Register_Masks */
+
+
+/* USBVREG - Peripheral instance base addresses */
+/** Peripheral USBVREG base address */
+#define USBVREG_BASE                             (0x40027000u)
+/** Peripheral USBVREG base pointer */
+#define USBVREG                                  ((USBVREG_Type *)USBVREG_BASE)
+/** Array initializer of USBVREG peripheral base addresses */
+#define USBVREG_BASE_ADDRS                       { USBVREG_BASE }
+/** Array initializer of USBVREG peripheral base pointers */
+#define USBVREG_BASE_PTRS                        { USBVREG }
+
+/*!
+ * @}
+ */ /* end of group USBVREG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USDHC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer
+ * @{
+ */
+
+/** USDHC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t DS_ADDR;                           /**< DMA System Address, offset: 0x0 */
+  __IO uint32_t BLK_ATT;                           /**< Block Attributes, offset: 0x4 */
+  __IO uint32_t CMD_ARG;                           /**< Command Argument, offset: 0x8 */
+  __IO uint32_t CMD_XFR_TYP;                       /**< Command Transfer Type, offset: 0xC */
+  __I  uint32_t CMD_RSP0;                          /**< Command Response0, offset: 0x10 */
+  __I  uint32_t CMD_RSP1;                          /**< Command Response1, offset: 0x14 */
+  __I  uint32_t CMD_RSP2;                          /**< Command Response2, offset: 0x18 */
+  __I  uint32_t CMD_RSP3;                          /**< Command Response3, offset: 0x1C */
+  __IO uint32_t DATA_BUFF_ACC_PORT;                /**< Data Buffer Access Port, offset: 0x20 */
+  __I  uint32_t PRES_STATE;                        /**< Present State, offset: 0x24 */
+  __IO uint32_t PROT_CTRL;                         /**< Protocol Control, offset: 0x28 */
+  __IO uint32_t SYS_CTRL;                          /**< System Control, offset: 0x2C */
+  __IO uint32_t INT_STATUS;                        /**< Interrupt Status, offset: 0x30 */
+  __IO uint32_t INT_STATUS_EN;                     /**< Interrupt Status Enable, offset: 0x34 */
+  __IO uint32_t INT_SIGNAL_EN;                     /**< Interrupt Signal Enable, offset: 0x38 */
+  __I  uint32_t AUTOCMD12_ERR_STATUS;              /**< Auto CMD12 Error Status, offset: 0x3C */
+  __I  uint32_t HOST_CTRL_CAP;                     /**< Host Controller Capabilities, offset: 0x40 */
+  __IO uint32_t WTMK_LVL;                          /**< Watermark Level, offset: 0x44 */
+  __IO uint32_t MIX_CTRL;                          /**< Mixer Control, offset: 0x48 */
+       uint8_t RESERVED_0[4];
+  __O  uint32_t FORCE_EVENT;                       /**< Force Event, offset: 0x50 */
+  __I  uint32_t ADMA_ERR_STATUS;                   /**< ADMA Error Status Register, offset: 0x54 */
+  __IO uint32_t ADMA_SYS_ADDR;                     /**< ADMA System Address, offset: 0x58 */
+       uint8_t RESERVED_1[100];
+  __IO uint32_t VEND_SPEC;                         /**< Vendor Specific Register, offset: 0xC0 */
+  __IO uint32_t MMC_BOOT;                          /**< MMC Boot Register, offset: 0xC4 */
+  __IO uint32_t VEND_SPEC2;                        /**< Vendor Specific 2 Register, offset: 0xC8 */
+} USDHC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USDHC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USDHC_Register_Masks USDHC Register Masks
+ * @{
+ */
+
+/*! @name DS_ADDR - DMA System Address */
+/*! @{ */
+#define USDHC_DS_ADDR_DS_ADDR_MASK               (0xFFFFFFFFU)
+#define USDHC_DS_ADDR_DS_ADDR_SHIFT              (0U)
+#define USDHC_DS_ADDR_DS_ADDR(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
+/*! @} */
+
+/*! @name BLK_ATT - Block Attributes */
+/*! @{ */
+#define USDHC_BLK_ATT_BLKSIZE_MASK               (0x1FFFU)
+#define USDHC_BLK_ATT_BLKSIZE_SHIFT              (0U)
+/*! BLKSIZE - Block Size
+ *  0b1000000000000..4096 Bytes
+ *  0b0100000000000..2048 Bytes
+ *  0b0001000000000..512 Bytes
+ *  0b0000111111111..511 Bytes
+ *  0b0000000000100..4 Bytes
+ *  0b0000000000011..3 Bytes
+ *  0b0000000000010..2 Bytes
+ *  0b0000000000001..1 Byte
+ *  0b0000000000000..No data transfer
+ */
+#define USDHC_BLK_ATT_BLKSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
+#define USDHC_BLK_ATT_BLKCNT_MASK                (0xFFFF0000U)
+#define USDHC_BLK_ATT_BLKCNT_SHIFT               (16U)
+/*! BLKCNT - Block Count
+ *  0b1111111111111111..65535 blocks
+ *  0b0000000000000010..2 blocks
+ *  0b0000000000000001..1 block
+ *  0b0000000000000000..Stop Count
+ */
+#define USDHC_BLK_ATT_BLKCNT(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
+/*! @} */
+
+/*! @name CMD_ARG - Command Argument */
+/*! @{ */
+#define USDHC_CMD_ARG_CMDARG_MASK                (0xFFFFFFFFU)
+#define USDHC_CMD_ARG_CMDARG_SHIFT               (0U)
+#define USDHC_CMD_ARG_CMDARG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
+/*! @} */
+
+/*! @name CMD_XFR_TYP - Command Transfer Type */
+/*! @{ */
+#define USDHC_CMD_XFR_TYP_RSPTYP_MASK            (0x30000U)
+#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT           (16U)
+/*! RSPTYP - Response Type Select
+ *  0b00..No Response
+ *  0b01..Response Length 136
+ *  0b10..Response Length 48
+ *  0b11..Response Length 48, check Busy after response
+ */
+#define USDHC_CMD_XFR_TYP_RSPTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
+#define USDHC_CMD_XFR_TYP_CCCEN_MASK             (0x80000U)
+#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT            (19U)
+/*! CCCEN - Command CRC Check Enable
+ *  0b1..Enable
+ *  0b0..Disable
+ */
+#define USDHC_CMD_XFR_TYP_CCCEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
+#define USDHC_CMD_XFR_TYP_CICEN_MASK             (0x100000U)
+#define USDHC_CMD_XFR_TYP_CICEN_SHIFT            (20U)
+/*! CICEN - Command Index Check Enable
+ *  0b1..Enable
+ *  0b0..Disable
+ */
+#define USDHC_CMD_XFR_TYP_CICEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
+#define USDHC_CMD_XFR_TYP_DPSEL_MASK             (0x200000U)
+#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT            (21U)
+/*! DPSEL - Data Present Select
+ *  0b1..Data Present
+ *  0b0..No Data Present
+ */
+#define USDHC_CMD_XFR_TYP_DPSEL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
+#define USDHC_CMD_XFR_TYP_CMDTYP_MASK            (0xC00000U)
+#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT           (22U)
+/*! CMDTYP - Command Type
+ *  0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR
+ *  0b10..Resume CMD52 for writing Function Select in CCCR
+ *  0b01..Suspend CMD52 for writing Bus Suspend in CCCR
+ *  0b00..Normal Other commands
+ */
+#define USDHC_CMD_XFR_TYP_CMDTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
+#define USDHC_CMD_XFR_TYP_CMDINX_MASK            (0x3F000000U)
+#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT           (24U)
+#define USDHC_CMD_XFR_TYP_CMDINX(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
+/*! @} */
+
+/*! @name CMD_RSP0 - Command Response0 */
+/*! @{ */
+#define USDHC_CMD_RSP0_CMDRSP0_MASK              (0xFFFFFFFFU)
+#define USDHC_CMD_RSP0_CMDRSP0_SHIFT             (0U)
+#define USDHC_CMD_RSP0_CMDRSP0(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
+/*! @} */
+
+/*! @name CMD_RSP1 - Command Response1 */
+/*! @{ */
+#define USDHC_CMD_RSP1_CMDRSP1_MASK              (0xFFFFFFFFU)
+#define USDHC_CMD_RSP1_CMDRSP1_SHIFT             (0U)
+#define USDHC_CMD_RSP1_CMDRSP1(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
+/*! @} */
+
+/*! @name CMD_RSP2 - Command Response2 */
+/*! @{ */
+#define USDHC_CMD_RSP2_CMDRSP2_MASK              (0xFFFFFFFFU)
+#define USDHC_CMD_RSP2_CMDRSP2_SHIFT             (0U)
+#define USDHC_CMD_RSP2_CMDRSP2(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
+/*! @} */
+
+/*! @name CMD_RSP3 - Command Response3 */
+/*! @{ */
+#define USDHC_CMD_RSP3_CMDRSP3_MASK              (0xFFFFFFFFU)
+#define USDHC_CMD_RSP3_CMDRSP3_SHIFT             (0U)
+#define USDHC_CMD_RSP3_CMDRSP3(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
+/*! @} */
+
+/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */
+/*! @{ */
+#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK    (0xFFFFFFFFU)
+#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT   (0U)
+#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
+/*! @} */
+
+/*! @name PRES_STATE - Present State */
+/*! @{ */
+#define USDHC_PRES_STATE_CIHB_MASK               (0x1U)
+#define USDHC_PRES_STATE_CIHB_SHIFT              (0U)
+/*! CIHB - Command Inhibit (CMD)
+ *  0b1..Cannot issue command
+ *  0b0..Can issue command using only CMD line
+ */
+#define USDHC_PRES_STATE_CIHB(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
+#define USDHC_PRES_STATE_CDIHB_MASK              (0x2U)
+#define USDHC_PRES_STATE_CDIHB_SHIFT             (1U)
+/*! CDIHB - Command Inhibit (DATA)
+ *  0b1..Cannot issue command which uses the DATA line
+ *  0b0..Can issue command which uses the DATA line
+ */
+#define USDHC_PRES_STATE_CDIHB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
+#define USDHC_PRES_STATE_DLA_MASK                (0x4U)
+#define USDHC_PRES_STATE_DLA_SHIFT               (2U)
+/*! DLA - Data Line Active
+ *  0b1..DATA Line Active
+ *  0b0..DATA Line Inactive
+ */
+#define USDHC_PRES_STATE_DLA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
+#define USDHC_PRES_STATE_SDSTB_MASK              (0x8U)
+#define USDHC_PRES_STATE_SDSTB_SHIFT             (3U)
+/*! SDSTB - SD Clock Stable
+ *  0b1..Clock is stable.
+ *  0b0..Clock is changing frequency and not stable.
+ */
+#define USDHC_PRES_STATE_SDSTB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
+#define USDHC_PRES_STATE_IPGOFF_MASK             (0x10U)
+#define USDHC_PRES_STATE_IPGOFF_SHIFT            (4U)
+/*! IPGOFF - IPG_CLK Gated Off Internally
+ *  0b1..IPG_CLK is gated off.
+ *  0b0..IPG_CLK is active.
+ */
+#define USDHC_PRES_STATE_IPGOFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
+#define USDHC_PRES_STATE_HCKOFF_MASK             (0x20U)
+#define USDHC_PRES_STATE_HCKOFF_SHIFT            (5U)
+/*! HCKOFF - HCLK Gated Off Internally
+ *  0b1..HCLK is gated off.
+ *  0b0..HCLK is active.
+ */
+#define USDHC_PRES_STATE_HCKOFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
+#define USDHC_PRES_STATE_PEROFF_MASK             (0x40U)
+#define USDHC_PRES_STATE_PEROFF_SHIFT            (6U)
+/*! PEROFF - IPG_PERCLK Gated Off Internally
+ *  0b1..IPG_PERCLK is gated off.
+ *  0b0..IPG_PERCLK is active.
+ */
+#define USDHC_PRES_STATE_PEROFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
+#define USDHC_PRES_STATE_SDOFF_MASK              (0x80U)
+#define USDHC_PRES_STATE_SDOFF_SHIFT             (7U)
+/*! SDOFF - SD Clock Gated Off Internally
+ *  0b1..SD Clock is gated off.
+ *  0b0..SD Clock is active.
+ */
+#define USDHC_PRES_STATE_SDOFF(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
+#define USDHC_PRES_STATE_WTA_MASK                (0x100U)
+#define USDHC_PRES_STATE_WTA_SHIFT               (8U)
+/*! WTA - Write Transfer Active
+ *  0b1..Transferring data
+ *  0b0..No valid data
+ */
+#define USDHC_PRES_STATE_WTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
+#define USDHC_PRES_STATE_RTA_MASK                (0x200U)
+#define USDHC_PRES_STATE_RTA_SHIFT               (9U)
+/*! RTA - Read Transfer Active
+ *  0b1..Transferring data
+ *  0b0..No valid data
+ */
+#define USDHC_PRES_STATE_RTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
+#define USDHC_PRES_STATE_BWEN_MASK               (0x400U)
+#define USDHC_PRES_STATE_BWEN_SHIFT              (10U)
+/*! BWEN - Buffer Write Enable
+ *  0b1..Write enable
+ *  0b0..Write disable
+ */
+#define USDHC_PRES_STATE_BWEN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
+#define USDHC_PRES_STATE_BREN_MASK               (0x800U)
+#define USDHC_PRES_STATE_BREN_SHIFT              (11U)
+/*! BREN - Buffer Read Enable
+ *  0b1..Read enable
+ *  0b0..Read disable
+ */
+#define USDHC_PRES_STATE_BREN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
+#define USDHC_PRES_STATE_CINST_MASK              (0x10000U)
+#define USDHC_PRES_STATE_CINST_SHIFT             (16U)
+/*! CINST - Card Inserted
+ *  0b1..Card Inserted
+ *  0b0..Power on Reset or No Card
+ */
+#define USDHC_PRES_STATE_CINST(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
+#define USDHC_PRES_STATE_CDPL_MASK               (0x40000U)
+#define USDHC_PRES_STATE_CDPL_SHIFT              (18U)
+/*! CDPL - Card Detect Pin Level
+ *  0b1..Card present (CD_B = 0)
+ *  0b0..No card present (CD_B = 1)
+ */
+#define USDHC_PRES_STATE_CDPL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
+#define USDHC_PRES_STATE_WPSPL_MASK              (0x80000U)
+#define USDHC_PRES_STATE_WPSPL_SHIFT             (19U)
+/*! WPSPL - Write Protect Switch Pin Level
+ *  0b1..Write enabled (WP = 0)
+ *  0b0..Write protected (WP = 1)
+ */
+#define USDHC_PRES_STATE_WPSPL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
+#define USDHC_PRES_STATE_CLSL_MASK               (0x800000U)
+#define USDHC_PRES_STATE_CLSL_SHIFT              (23U)
+#define USDHC_PRES_STATE_CLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
+#define USDHC_PRES_STATE_DLSL_MASK               (0xFF000000U)
+#define USDHC_PRES_STATE_DLSL_SHIFT              (24U)
+/*! DLSL - DATA[7:0] Line Signal Level
+ *  0b00000111..Data 7 line signal level
+ *  0b00000110..Data 6 line signal level
+ *  0b00000101..Data 5 line signal level
+ *  0b00000100..Data 4 line signal level
+ *  0b00000011..Data 3 line signal level
+ *  0b00000010..Data 2 line signal level
+ *  0b00000001..Data 1 line signal level
+ *  0b00000000..Data 0 line signal level
+ */
+#define USDHC_PRES_STATE_DLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
+/*! @} */
+
+/*! @name PROT_CTRL - Protocol Control */
+/*! @{ */
+#define USDHC_PROT_CTRL_LCTL_MASK                (0x1U)
+#define USDHC_PROT_CTRL_LCTL_SHIFT               (0U)
+/*! LCTL - LED Control
+ *  0b1..LED on
+ *  0b0..LED off
+ */
+#define USDHC_PROT_CTRL_LCTL(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)
+#define USDHC_PROT_CTRL_DTW_MASK                 (0x6U)
+#define USDHC_PROT_CTRL_DTW_SHIFT                (1U)
+/*! DTW - Data Transfer Width
+ *  0b10..8-bit mode
+ *  0b01..4-bit mode
+ *  0b00..1-bit mode
+ *  0b11..Reserved
+ */
+#define USDHC_PROT_CTRL_DTW(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
+#define USDHC_PROT_CTRL_D3CD_MASK                (0x8U)
+#define USDHC_PROT_CTRL_D3CD_SHIFT               (3U)
+/*! D3CD - DATA3 as Card Detection Pin
+ *  0b1..DATA3 as Card Detection Pin
+ *  0b0..DATA3 does not monitor Card Insertion
+ */
+#define USDHC_PROT_CTRL_D3CD(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
+#define USDHC_PROT_CTRL_EMODE_MASK               (0x30U)
+#define USDHC_PROT_CTRL_EMODE_SHIFT              (4U)
+/*! EMODE - Endian Mode
+ *  0b00..Big Endian Mode
+ *  0b01..Half Word Big Endian Mode
+ *  0b10..Little Endian Mode
+ *  0b11..Reserved
+ */
+#define USDHC_PROT_CTRL_EMODE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
+#define USDHC_PROT_CTRL_CDTL_MASK                (0x40U)
+#define USDHC_PROT_CTRL_CDTL_SHIFT               (6U)
+/*! CDTL - Card Detect Test Level
+ *  0b1..Card Detect Test Level is 1, card inserted
+ *  0b0..Card Detect Test Level is 0, no card inserted
+ */
+#define USDHC_PROT_CTRL_CDTL(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
+#define USDHC_PROT_CTRL_CDSS_MASK                (0x80U)
+#define USDHC_PROT_CTRL_CDSS_SHIFT               (7U)
+/*! CDSS - Card Detect Signal Selection
+ *  0b1..Card Detection Test Level is selected (for test purpose).
+ *  0b0..Card Detection Level is selected (for normal purpose).
+ */
+#define USDHC_PROT_CTRL_CDSS(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
+#define USDHC_PROT_CTRL_DMASEL_MASK              (0x300U)
+#define USDHC_PROT_CTRL_DMASEL_SHIFT             (8U)
+/*! DMASEL - DMA Select
+ *  0b00..No DMA or Simple DMA is selected
+ *  0b01..ADMA1 is selected
+ *  0b10..ADMA2 is selected
+ *  0b11..reserved
+ */
+#define USDHC_PROT_CTRL_DMASEL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
+#define USDHC_PROT_CTRL_SABGREQ_MASK             (0x10000U)
+#define USDHC_PROT_CTRL_SABGREQ_SHIFT            (16U)
+/*! SABGREQ - Stop At Block Gap Request
+ *  0b1..Stop
+ *  0b0..Transfer
+ */
+#define USDHC_PROT_CTRL_SABGREQ(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
+#define USDHC_PROT_CTRL_CREQ_MASK                (0x20000U)
+#define USDHC_PROT_CTRL_CREQ_SHIFT               (17U)
+/*! CREQ - Continue Request
+ *  0b1..Restart
+ *  0b0..No effect
+ */
+#define USDHC_PROT_CTRL_CREQ(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
+#define USDHC_PROT_CTRL_RWCTL_MASK               (0x40000U)
+#define USDHC_PROT_CTRL_RWCTL_SHIFT              (18U)
+/*! RWCTL - Read Wait Control
+ *  0b1..Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set
+ *  0b0..Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set
+ */
+#define USDHC_PROT_CTRL_RWCTL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
+#define USDHC_PROT_CTRL_IABG_MASK                (0x80000U)
+#define USDHC_PROT_CTRL_IABG_SHIFT               (19U)
+/*! IABG - Interrupt At Block Gap
+ *  0b1..Enabled
+ *  0b0..Disabled
+ */
+#define USDHC_PROT_CTRL_IABG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
+#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK     (0x100000U)
+#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT    (20U)
+#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
+#define USDHC_PROT_CTRL_WECINT_MASK              (0x1000000U)
+#define USDHC_PROT_CTRL_WECINT_SHIFT             (24U)
+/*! WECINT - Wakeup Event Enable On Card Interrupt
+ *  0b1..Enable
+ *  0b0..Disable
+ */
+#define USDHC_PROT_CTRL_WECINT(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
+#define USDHC_PROT_CTRL_WECINS_MASK              (0x2000000U)
+#define USDHC_PROT_CTRL_WECINS_SHIFT             (25U)
+/*! WECINS - Wakeup Event Enable On SD Card Insertion
+ *  0b1..Enable
+ *  0b0..Disable
+ */
+#define USDHC_PROT_CTRL_WECINS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
+#define USDHC_PROT_CTRL_WECRM_MASK               (0x4000000U)
+#define USDHC_PROT_CTRL_WECRM_SHIFT              (26U)
+/*! WECRM - Wakeup Event Enable On SD Card Removal
+ *  0b1..Enable
+ *  0b0..Disable
+ */
+#define USDHC_PROT_CTRL_WECRM(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
+#define USDHC_PROT_CTRL_BURST_LEN_EN_MASK        (0x38000000U)
+#define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT       (27U)
+/*! BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP
+ *  0bxx1..Burst length is enabled for INCR
+ *  0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16
+ *  0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP
+ */
+#define USDHC_PROT_CTRL_BURST_LEN_EN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)
+#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK    (0x40000000U)
+#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT   (30U)
+/*! NON_EXACT_BLK_RD - NON_EXACT_BLK_RD
+ *  0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.
+ *  0b0..The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read.
+ */
+#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
+/*! @} */
+
+/*! @name SYS_CTRL - System Control */
+/*! @{ */
+#define USDHC_SYS_CTRL_DVS_MASK                  (0xF0U)
+#define USDHC_SYS_CTRL_DVS_SHIFT                 (4U)
+/*! DVS - Divisor
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define USDHC_SYS_CTRL_DVS(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
+#define USDHC_SYS_CTRL_SDCLKFS_MASK              (0xFF00U)
+#define USDHC_SYS_CTRL_SDCLKFS_SHIFT             (8U)
+#define USDHC_SYS_CTRL_SDCLKFS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
+#define USDHC_SYS_CTRL_DTOCV_MASK                (0xF0000U)
+#define USDHC_SYS_CTRL_DTOCV_SHIFT               (16U)
+/*! DTOCV - Data Timeout Counter Value
+ *  0b1111..SDCLK x 2 29
+ *  0b1110..SDCLK x 2 28
+ *  0b1101..SDCLK x 2 27
+ *  0b0001..SDCLK x 2 15
+ *  0b0000..SDCLK x 2 14
+ */
+#define USDHC_SYS_CTRL_DTOCV(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
+#define USDHC_SYS_CTRL_IPP_RST_N_MASK            (0x800000U)
+#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT           (23U)
+#define USDHC_SYS_CTRL_IPP_RST_N(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
+#define USDHC_SYS_CTRL_RSTA_MASK                 (0x1000000U)
+#define USDHC_SYS_CTRL_RSTA_SHIFT                (24U)
+/*! RSTA - Software Reset For ALL
+ *  0b1..Reset
+ *  0b0..No Reset
+ */
+#define USDHC_SYS_CTRL_RSTA(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
+#define USDHC_SYS_CTRL_RSTC_MASK                 (0x2000000U)
+#define USDHC_SYS_CTRL_RSTC_SHIFT                (25U)
+/*! RSTC - Software Reset For CMD Line
+ *  0b1..Reset
+ *  0b0..No Reset
+ */
+#define USDHC_SYS_CTRL_RSTC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
+#define USDHC_SYS_CTRL_RSTD_MASK                 (0x4000000U)
+#define USDHC_SYS_CTRL_RSTD_SHIFT                (26U)
+/*! RSTD - Software Reset For DATA Line
+ *  0b1..Reset
+ *  0b0..No Reset
+ */
+#define USDHC_SYS_CTRL_RSTD(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
+#define USDHC_SYS_CTRL_INITA_MASK                (0x8000000U)
+#define USDHC_SYS_CTRL_INITA_SHIFT               (27U)
+#define USDHC_SYS_CTRL_INITA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
+/*! @} */
+
+/*! @name INT_STATUS - Interrupt Status */
+/*! @{ */
+#define USDHC_INT_STATUS_CC_MASK                 (0x1U)
+#define USDHC_INT_STATUS_CC_SHIFT                (0U)
+/*! CC - Command Complete
+ *  0b1..Command complete
+ *  0b0..Command not complete
+ */
+#define USDHC_INT_STATUS_CC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
+#define USDHC_INT_STATUS_TC_MASK                 (0x2U)
+#define USDHC_INT_STATUS_TC_SHIFT                (1U)
+/*! TC - Transfer Complete
+ *  0b1..Transfer complete
+ *  0b0..Transfer not complete
+ */
+#define USDHC_INT_STATUS_TC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
+#define USDHC_INT_STATUS_BGE_MASK                (0x4U)
+#define USDHC_INT_STATUS_BGE_SHIFT               (2U)
+/*! BGE - Block Gap Event
+ *  0b1..Transaction stopped at block gap
+ *  0b0..No block gap event
+ */
+#define USDHC_INT_STATUS_BGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
+#define USDHC_INT_STATUS_DINT_MASK               (0x8U)
+#define USDHC_INT_STATUS_DINT_SHIFT              (3U)
+/*! DINT - DMA Interrupt
+ *  0b1..DMA Interrupt is generated
+ *  0b0..No DMA Interrupt
+ */
+#define USDHC_INT_STATUS_DINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
+#define USDHC_INT_STATUS_BWR_MASK                (0x10U)
+#define USDHC_INT_STATUS_BWR_SHIFT               (4U)
+/*! BWR - Buffer Write Ready
+ *  0b1..Ready to write buffer:
+ *  0b0..Not ready to write buffer
+ */
+#define USDHC_INT_STATUS_BWR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
+#define USDHC_INT_STATUS_BRR_MASK                (0x20U)
+#define USDHC_INT_STATUS_BRR_SHIFT               (5U)
+/*! BRR - Buffer Read Ready
+ *  0b1..Ready to read buffer
+ *  0b0..Not ready to read buffer
+ */
+#define USDHC_INT_STATUS_BRR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
+#define USDHC_INT_STATUS_CINS_MASK               (0x40U)
+#define USDHC_INT_STATUS_CINS_SHIFT              (6U)
+/*! CINS - Card Insertion
+ *  0b1..Card inserted
+ *  0b0..Card state unstable or removed
+ */
+#define USDHC_INT_STATUS_CINS(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
+#define USDHC_INT_STATUS_CRM_MASK                (0x80U)
+#define USDHC_INT_STATUS_CRM_SHIFT               (7U)
+/*! CRM - Card Removal
+ *  0b1..Card removed
+ *  0b0..Card state unstable or inserted
+ */
+#define USDHC_INT_STATUS_CRM(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
+#define USDHC_INT_STATUS_CINT_MASK               (0x100U)
+#define USDHC_INT_STATUS_CINT_SHIFT              (8U)
+/*! CINT - Card Interrupt
+ *  0b1..Generate Card Interrupt
+ *  0b0..No Card Interrupt
+ */
+#define USDHC_INT_STATUS_CINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
+#define USDHC_INT_STATUS_CTOE_MASK               (0x10000U)
+#define USDHC_INT_STATUS_CTOE_SHIFT              (16U)
+/*! CTOE - Command Timeout Error
+ *  0b1..Time out
+ *  0b0..No Error
+ */
+#define USDHC_INT_STATUS_CTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
+#define USDHC_INT_STATUS_CCE_MASK                (0x20000U)
+#define USDHC_INT_STATUS_CCE_SHIFT               (17U)
+/*! CCE - Command CRC Error
+ *  0b1..CRC Error Generated.
+ *  0b0..No Error
+ */
+#define USDHC_INT_STATUS_CCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
+#define USDHC_INT_STATUS_CEBE_MASK               (0x40000U)
+#define USDHC_INT_STATUS_CEBE_SHIFT              (18U)
+/*! CEBE - Command End Bit Error
+ *  0b1..End Bit Error Generated
+ *  0b0..No Error
+ */
+#define USDHC_INT_STATUS_CEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
+#define USDHC_INT_STATUS_CIE_MASK                (0x80000U)
+#define USDHC_INT_STATUS_CIE_SHIFT               (19U)
+/*! CIE - Command Index Error
+ *  0b1..Error
+ *  0b0..No Error
+ */
+#define USDHC_INT_STATUS_CIE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
+#define USDHC_INT_STATUS_DTOE_MASK               (0x100000U)
+#define USDHC_INT_STATUS_DTOE_SHIFT              (20U)
+/*! DTOE - Data Timeout Error
+ *  0b1..Time out
+ *  0b0..No Error
+ */
+#define USDHC_INT_STATUS_DTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
+#define USDHC_INT_STATUS_DCE_MASK                (0x200000U)
+#define USDHC_INT_STATUS_DCE_SHIFT               (21U)
+/*! DCE - Data CRC Error
+ *  0b1..Error
+ *  0b0..No Error
+ */
+#define USDHC_INT_STATUS_DCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
+#define USDHC_INT_STATUS_DEBE_MASK               (0x400000U)
+#define USDHC_INT_STATUS_DEBE_SHIFT              (22U)
+/*! DEBE - Data End Bit Error
+ *  0b1..Error
+ *  0b0..No Error
+ */
+#define USDHC_INT_STATUS_DEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
+#define USDHC_INT_STATUS_AC12E_MASK              (0x1000000U)
+#define USDHC_INT_STATUS_AC12E_SHIFT             (24U)
+/*! AC12E - Auto CMD12 Error
+ *  0b1..Error
+ *  0b0..No Error
+ */
+#define USDHC_INT_STATUS_AC12E(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
+#define USDHC_INT_STATUS_DMAE_MASK               (0x10000000U)
+#define USDHC_INT_STATUS_DMAE_SHIFT              (28U)
+/*! DMAE - DMA Error
+ *  0b1..Error
+ *  0b0..No Error
+ */
+#define USDHC_INT_STATUS_DMAE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
+/*! @} */
+
+/*! @name INT_STATUS_EN - Interrupt Status Enable */
+/*! @{ */
+#define USDHC_INT_STATUS_EN_CCSEN_MASK           (0x1U)
+#define USDHC_INT_STATUS_EN_CCSEN_SHIFT          (0U)
+/*! CCSEN - Command Complete Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
+#define USDHC_INT_STATUS_EN_TCSEN_MASK           (0x2U)
+#define USDHC_INT_STATUS_EN_TCSEN_SHIFT          (1U)
+/*! TCSEN - Transfer Complete Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_TCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
+#define USDHC_INT_STATUS_EN_BGESEN_MASK          (0x4U)
+#define USDHC_INT_STATUS_EN_BGESEN_SHIFT         (2U)
+/*! BGESEN - Block Gap Event Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_BGESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
+#define USDHC_INT_STATUS_EN_DINTSEN_MASK         (0x8U)
+#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT        (3U)
+/*! DINTSEN - DMA Interrupt Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_DINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
+#define USDHC_INT_STATUS_EN_BWRSEN_MASK          (0x10U)
+#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT         (4U)
+/*! BWRSEN - Buffer Write Ready Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_BWRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
+#define USDHC_INT_STATUS_EN_BRRSEN_MASK          (0x20U)
+#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT         (5U)
+/*! BRRSEN - Buffer Read Ready Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_BRRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
+#define USDHC_INT_STATUS_EN_CINSSEN_MASK         (0x40U)
+#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT        (6U)
+/*! CINSSEN - Card Insertion Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CINSSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
+#define USDHC_INT_STATUS_EN_CRMSEN_MASK          (0x80U)
+#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT         (7U)
+/*! CRMSEN - Card Removal Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CRMSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
+#define USDHC_INT_STATUS_EN_CINTSEN_MASK         (0x100U)
+#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT        (8U)
+/*! CINTSEN - Card Interrupt Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
+#define USDHC_INT_STATUS_EN_CTOESEN_MASK         (0x10000U)
+#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT        (16U)
+/*! CTOESEN - Command Timeout Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
+#define USDHC_INT_STATUS_EN_CCESEN_MASK          (0x20000U)
+#define USDHC_INT_STATUS_EN_CCESEN_SHIFT         (17U)
+/*! CCESEN - Command CRC Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
+#define USDHC_INT_STATUS_EN_CEBESEN_MASK         (0x40000U)
+#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT        (18U)
+/*! CEBESEN - Command End Bit Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
+#define USDHC_INT_STATUS_EN_CIESEN_MASK          (0x80000U)
+#define USDHC_INT_STATUS_EN_CIESEN_SHIFT         (19U)
+/*! CIESEN - Command Index Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CIESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
+#define USDHC_INT_STATUS_EN_DTOESEN_MASK         (0x100000U)
+#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT        (20U)
+/*! DTOESEN - Data Timeout Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_DTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
+#define USDHC_INT_STATUS_EN_DCESEN_MASK          (0x200000U)
+#define USDHC_INT_STATUS_EN_DCESEN_SHIFT         (21U)
+/*! DCESEN - Data CRC Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_DCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
+#define USDHC_INT_STATUS_EN_DEBESEN_MASK         (0x400000U)
+#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT        (22U)
+/*! DEBESEN - Data End Bit Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_DEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
+#define USDHC_INT_STATUS_EN_AC12ESEN_MASK        (0x1000000U)
+#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT       (24U)
+/*! AC12ESEN - Auto CMD12 Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_AC12ESEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
+#define USDHC_INT_STATUS_EN_DMAESEN_MASK         (0x10000000U)
+#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT        (28U)
+/*! DMAESEN - DMA Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_DMAESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
+/*! @} */
+
+/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */
+/*! @{ */
+#define USDHC_INT_SIGNAL_EN_CCIEN_MASK           (0x1U)
+#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT          (0U)
+/*! CCIEN - Command Complete Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_TCIEN_MASK           (0x2U)
+#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT          (1U)
+/*! TCIEN - Transfer Complete Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_TCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK          (0x4U)
+#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT         (2U)
+/*! BGEIEN - Block Gap Event Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_BGEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK         (0x8U)
+#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT        (3U)
+/*! DINTIEN - DMA Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_DINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK          (0x10U)
+#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT         (4U)
+/*! BWRIEN - Buffer Write Ready Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_BWRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK          (0x20U)
+#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT         (5U)
+/*! BRRIEN - Buffer Read Ready Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_BRRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK         (0x40U)
+#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT        (6U)
+/*! CINSIEN - Card Insertion Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CINSIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK          (0x80U)
+#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT         (7U)
+/*! CRMIEN - Card Removal Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CRMIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK         (0x100U)
+#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT        (8U)
+/*! CINTIEN - Card Interrupt Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK         (0x10000U)
+#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT        (16U)
+/*! CTOEIEN - Command Timeout Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK          (0x20000U)
+#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT         (17U)
+/*! CCEIEN - Command CRC Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK         (0x40000U)
+#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT        (18U)
+/*! CEBEIEN - Command End Bit Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK          (0x80000U)
+#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT         (19U)
+/*! CIEIEN - Command Index Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CIEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK         (0x100000U)
+#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT        (20U)
+/*! DTOEIEN - Data Timeout Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_DTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK          (0x200000U)
+#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT         (21U)
+/*! DCEIEN - Data CRC Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_DCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK         (0x400000U)
+#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT        (22U)
+/*! DEBEIEN - Data End Bit Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_DEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK        (0x1000000U)
+#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT       (24U)
+/*! AC12EIEN - Auto CMD12 Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_AC12EIEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK         (0x10000000U)
+#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT        (28U)
+/*! DMAEIEN - DMA Error Interrupt Enable
+ *  0b1..Enable
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_DMAEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
+/*! @} */
+
+/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */
+/*! @{ */
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK   (0x1U)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT  (0U)
+/*! AC12NE - Auto CMD12 Not Executed
+ *  0b1..Not executed
+ *  0b0..Executed
+ */
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK  (0x2U)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
+/*! AC12TOE - Auto CMD12 / 23 Timeout Error
+ *  0b1..Time out
+ *  0b0..No error
+ */
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK  (0x4U)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
+/*! AC12EBE - Auto CMD12 / 23 End Bit Error
+ *  0b1..End Bit Error Generated
+ *  0b0..No error
+ */
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK   (0x8U)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT  (3U)
+/*! AC12CE - Auto CMD12 / 23 CRC Error
+ *  0b1..CRC Error Met in Auto CMD12/23 Response
+ *  0b0..No CRC error
+ */
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK   (0x10U)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT  (4U)
+/*! AC12IE - Auto CMD12 / 23 Index Error
+ *  0b1..Error, the CMD index in response is not CMD12/23
+ *  0b0..No error
+ */
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
+#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
+#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
+/*! CNIBAC12E - Command Not Issued By Auto CMD12 Error
+ *  0b1..Not Issued
+ *  0b0..No error
+ */
+#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
+/*! @} */
+
+/*! @name HOST_CTRL_CAP - Host Controller Capabilities */
+/*! @{ */
+#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK   (0x4U)
+#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT  (2U)
+#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
+#define USDHC_HOST_CTRL_CAP_MBL_MASK             (0x70000U)
+#define USDHC_HOST_CTRL_CAP_MBL_SHIFT            (16U)
+/*! MBL - Max Block Length
+ *  0b000..512 bytes
+ *  0b001..1024 bytes
+ *  0b010..2048 bytes
+ *  0b011..4096 bytes
+ */
+#define USDHC_HOST_CTRL_CAP_MBL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
+#define USDHC_HOST_CTRL_CAP_ADMAS_MASK           (0x100000U)
+#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT          (20U)
+/*! ADMAS - ADMA Support
+ *  0b1..Advanced DMA Supported
+ *  0b0..Advanced DMA Not supported
+ */
+#define USDHC_HOST_CTRL_CAP_ADMAS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
+#define USDHC_HOST_CTRL_CAP_HSS_MASK             (0x200000U)
+#define USDHC_HOST_CTRL_CAP_HSS_SHIFT            (21U)
+/*! HSS - High Speed Support
+ *  0b1..High Speed Supported
+ *  0b0..High Speed Not Supported
+ */
+#define USDHC_HOST_CTRL_CAP_HSS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
+#define USDHC_HOST_CTRL_CAP_DMAS_MASK            (0x400000U)
+#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT           (22U)
+/*! DMAS - DMA Support
+ *  0b1..DMA Supported
+ *  0b0..DMA not supported
+ */
+#define USDHC_HOST_CTRL_CAP_DMAS(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
+#define USDHC_HOST_CTRL_CAP_SRS_MASK             (0x800000U)
+#define USDHC_HOST_CTRL_CAP_SRS_SHIFT            (23U)
+/*! SRS - Suspend / Resume Support
+ *  0b1..Supported
+ *  0b0..Not supported
+ */
+#define USDHC_HOST_CTRL_CAP_SRS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
+#define USDHC_HOST_CTRL_CAP_VS33_MASK            (0x1000000U)
+#define USDHC_HOST_CTRL_CAP_VS33_SHIFT           (24U)
+/*! VS33 - Voltage Support 3.3V
+ *  0b1..3.3V supported
+ *  0b0..3.3V not supported
+ */
+#define USDHC_HOST_CTRL_CAP_VS33(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
+#define USDHC_HOST_CTRL_CAP_VS30_MASK            (0x2000000U)
+#define USDHC_HOST_CTRL_CAP_VS30_SHIFT           (25U)
+/*! VS30 - Voltage Support 3.0 V
+ *  0b1..3.0V supported
+ *  0b0..3.0V not supported
+ */
+#define USDHC_HOST_CTRL_CAP_VS30(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
+#define USDHC_HOST_CTRL_CAP_VS18_MASK            (0x4000000U)
+#define USDHC_HOST_CTRL_CAP_VS18_SHIFT           (26U)
+/*! VS18 - Voltage Support 1.8 V
+ *  0b1..1.8V supported
+ *  0b0..1.8V not supported
+ */
+#define USDHC_HOST_CTRL_CAP_VS18(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
+/*! @} */
+
+/*! @name WTMK_LVL - Watermark Level */
+/*! @{ */
+#define USDHC_WTMK_LVL_RD_WML_MASK               (0xFFU)
+#define USDHC_WTMK_LVL_RD_WML_SHIFT              (0U)
+#define USDHC_WTMK_LVL_RD_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
+#define USDHC_WTMK_LVL_RD_BRST_LEN_MASK          (0x1F00U)
+#define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT         (8U)
+#define USDHC_WTMK_LVL_RD_BRST_LEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)
+#define USDHC_WTMK_LVL_WR_WML_MASK               (0xFF0000U)
+#define USDHC_WTMK_LVL_WR_WML_SHIFT              (16U)
+#define USDHC_WTMK_LVL_WR_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
+#define USDHC_WTMK_LVL_WR_BRST_LEN_MASK          (0x1F000000U)
+#define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT         (24U)
+#define USDHC_WTMK_LVL_WR_BRST_LEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)
+/*! @} */
+
+/*! @name MIX_CTRL - Mixer Control */
+/*! @{ */
+#define USDHC_MIX_CTRL_DMAEN_MASK                (0x1U)
+#define USDHC_MIX_CTRL_DMAEN_SHIFT               (0U)
+/*! DMAEN - DMA Enable
+ *  0b1..Enable
+ *  0b0..Disable
+ */
+#define USDHC_MIX_CTRL_DMAEN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
+#define USDHC_MIX_CTRL_BCEN_MASK                 (0x2U)
+#define USDHC_MIX_CTRL_BCEN_SHIFT                (1U)
+/*! BCEN - Block Count Enable
+ *  0b1..Enable
+ *  0b0..Disable
+ */
+#define USDHC_MIX_CTRL_BCEN(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
+#define USDHC_MIX_CTRL_AC12EN_MASK               (0x4U)
+#define USDHC_MIX_CTRL_AC12EN_SHIFT              (2U)
+/*! AC12EN - Auto CMD12 Enable
+ *  0b1..Enable
+ *  0b0..Disable
+ */
+#define USDHC_MIX_CTRL_AC12EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
+#define USDHC_MIX_CTRL_DDR_EN_MASK               (0x8U)
+#define USDHC_MIX_CTRL_DDR_EN_SHIFT              (3U)
+#define USDHC_MIX_CTRL_DDR_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
+#define USDHC_MIX_CTRL_DTDSEL_MASK               (0x10U)
+#define USDHC_MIX_CTRL_DTDSEL_SHIFT              (4U)
+/*! DTDSEL - Data Transfer Direction Select
+ *  0b1..Read (Card to Host)
+ *  0b0..Write (Host to Card)
+ */
+#define USDHC_MIX_CTRL_DTDSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
+#define USDHC_MIX_CTRL_MSBSEL_MASK               (0x20U)
+#define USDHC_MIX_CTRL_MSBSEL_SHIFT              (5U)
+/*! MSBSEL - Multi / Single Block Select
+ *  0b1..Multiple Blocks
+ *  0b0..Single Block
+ */
+#define USDHC_MIX_CTRL_MSBSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
+#define USDHC_MIX_CTRL_NIBBLE_POS_MASK           (0x40U)
+#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT          (6U)
+#define USDHC_MIX_CTRL_NIBBLE_POS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
+#define USDHC_MIX_CTRL_AC23EN_MASK               (0x80U)
+#define USDHC_MIX_CTRL_AC23EN_SHIFT              (7U)
+#define USDHC_MIX_CTRL_AC23EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
+/*! @} */
+
+/*! @name FORCE_EVENT - Force Event */
+/*! @{ */
+#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK        (0x1U)
+#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT       (0U)
+#define USDHC_FORCE_EVENT_FEVTAC12NE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
+#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK       (0x2U)
+#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT      (1U)
+#define USDHC_FORCE_EVENT_FEVTAC12TOE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
+#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK        (0x4U)
+#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT       (2U)
+#define USDHC_FORCE_EVENT_FEVTAC12CE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
+#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK       (0x8U)
+#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT      (3U)
+#define USDHC_FORCE_EVENT_FEVTAC12EBE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
+#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK        (0x10U)
+#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT       (4U)
+#define USDHC_FORCE_EVENT_FEVTAC12IE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
+#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK     (0x80U)
+#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT    (7U)
+#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
+#define USDHC_FORCE_EVENT_FEVTCTOE_MASK          (0x10000U)
+#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT         (16U)
+#define USDHC_FORCE_EVENT_FEVTCTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
+#define USDHC_FORCE_EVENT_FEVTCCE_MASK           (0x20000U)
+#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT          (17U)
+#define USDHC_FORCE_EVENT_FEVTCCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
+#define USDHC_FORCE_EVENT_FEVTCEBE_MASK          (0x40000U)
+#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT         (18U)
+#define USDHC_FORCE_EVENT_FEVTCEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
+#define USDHC_FORCE_EVENT_FEVTCIE_MASK           (0x80000U)
+#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT          (19U)
+#define USDHC_FORCE_EVENT_FEVTCIE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
+#define USDHC_FORCE_EVENT_FEVTDTOE_MASK          (0x100000U)
+#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT         (20U)
+#define USDHC_FORCE_EVENT_FEVTDTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
+#define USDHC_FORCE_EVENT_FEVTDCE_MASK           (0x200000U)
+#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT          (21U)
+#define USDHC_FORCE_EVENT_FEVTDCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
+#define USDHC_FORCE_EVENT_FEVTDEBE_MASK          (0x400000U)
+#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT         (22U)
+#define USDHC_FORCE_EVENT_FEVTDEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
+#define USDHC_FORCE_EVENT_FEVTAC12E_MASK         (0x1000000U)
+#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT        (24U)
+#define USDHC_FORCE_EVENT_FEVTAC12E(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
+#define USDHC_FORCE_EVENT_FEVTDMAE_MASK          (0x10000000U)
+#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT         (28U)
+#define USDHC_FORCE_EVENT_FEVTDMAE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
+#define USDHC_FORCE_EVENT_FEVTCINT_MASK          (0x80000000U)
+#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT         (31U)
+#define USDHC_FORCE_EVENT_FEVTCINT(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
+/*! @} */
+
+/*! @name ADMA_ERR_STATUS - ADMA Error Status Register */
+/*! @{ */
+#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK        (0x3U)
+#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT       (0U)
+#define USDHC_ADMA_ERR_STATUS_ADMAES(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
+#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK       (0x4U)
+#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT      (2U)
+/*! ADMALME - ADMA Length Mismatch Error
+ *  0b1..Error
+ *  0b0..No Error
+ */
+#define USDHC_ADMA_ERR_STATUS_ADMALME(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
+#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK       (0x8U)
+#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT      (3U)
+/*! ADMADCE - ADMA Descriptor Error
+ *  0b1..Error
+ *  0b0..No Error
+ */
+#define USDHC_ADMA_ERR_STATUS_ADMADCE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
+/*! @} */
+
+/*! @name ADMA_SYS_ADDR - ADMA System Address */
+/*! @{ */
+#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK        (0xFFFFFFFCU)
+#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT       (2U)
+#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
+/*! @} */
+
+/*! @name VEND_SPEC - Vendor Specific Register */
+/*! @{ */
+#define USDHC_VEND_SPEC_VSELECT_MASK             (0x2U)
+#define USDHC_VEND_SPEC_VSELECT_SHIFT            (1U)
+/*! VSELECT - Voltage Selection
+ *  0b1..Change the voltage to low voltage range, around 1.8 V
+ *  0b0..Change the voltage to high voltage range, around 3.0 V
+ */
+#define USDHC_VEND_SPEC_VSELECT(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
+#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK     (0x4U)
+#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT    (2U)
+/*! CONFLICT_CHK_EN - Conflict check enable.
+ *  0b0..Conflict check disable
+ *  0b1..Conflict check enable
+ */
+#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
+#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK  (0x8U)
+#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
+/*! AC12_WR_CHKBUSY_EN - AC12_WR_CHKBUSY_EN
+ *  0b0..Do not check busy after auto CMD12 for write data packet
+ *  0b1..Check busy after auto CMD12 for write data packet
+ */
+#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
+#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK        (0x100U)
+#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT       (8U)
+/*! FRC_SDCLK_ON - FRC_SDCLK_ON
+ *  0b0..CLK active or inactive is fully controlled by the hardware.
+ *  0b1..Force CLK active.
+ */
+#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
+#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK         (0x8000U)
+#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT        (15U)
+/*! CRC_CHK_DIS - CRC Check Disable
+ *  0b0..Check CRC16 for every read data packet and check CRC bits for every write data packet
+ *  0b1..Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet
+ */
+#define USDHC_VEND_SPEC_CRC_CHK_DIS(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
+#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK         (0x80000000U)
+#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT        (31U)
+/*! CMD_BYTE_EN - CMD_BYTE_EN
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define USDHC_VEND_SPEC_CMD_BYTE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
+/*! @} */
+
+/*! @name MMC_BOOT - MMC Boot Register */
+/*! @{ */
+#define USDHC_MMC_BOOT_DTOCV_ACK_MASK            (0xFU)
+#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT           (0U)
+/*! DTOCV_ACK - DTOCV_ACK
+ *  0b0000..SDCLK x 2^14
+ *  0b0001..SDCLK x 2^15
+ *  0b0010..SDCLK x 2^16
+ *  0b0011..SDCLK x 2^17
+ *  0b0100..SDCLK x 2^18
+ *  0b0101..SDCLK x 2^19
+ *  0b0110..SDCLK x 2^20
+ *  0b0111..SDCLK x 2^21
+ *  0b1110..SDCLK x 2^28
+ *  0b1111..SDCLK x 2^29
+ */
+#define USDHC_MMC_BOOT_DTOCV_ACK(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
+#define USDHC_MMC_BOOT_BOOT_ACK_MASK             (0x10U)
+#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT            (4U)
+/*! BOOT_ACK - BOOT_ACK
+ *  0b0..No ack
+ *  0b1..Ack
+ */
+#define USDHC_MMC_BOOT_BOOT_ACK(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
+#define USDHC_MMC_BOOT_BOOT_MODE_MASK            (0x20U)
+#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT           (5U)
+/*! BOOT_MODE - BOOT_MODE
+ *  0b0..Normal boot
+ *  0b1..Alternative boot
+ */
+#define USDHC_MMC_BOOT_BOOT_MODE(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
+#define USDHC_MMC_BOOT_BOOT_EN_MASK              (0x40U)
+#define USDHC_MMC_BOOT_BOOT_EN_SHIFT             (6U)
+/*! BOOT_EN - BOOT_EN
+ *  0b0..Fast boot disable
+ *  0b1..Fast boot enable
+ */
+#define USDHC_MMC_BOOT_BOOT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
+#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK         (0x80U)
+#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT        (7U)
+#define USDHC_MMC_BOOT_AUTO_SABG_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
+#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK     (0x100U)
+#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT    (8U)
+/*! DISABLE_TIME_OUT - Disable Time Out
+ *  0b0..Enable time out
+ *  0b1..Disable time out
+ */
+#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
+#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK         (0xFFFF0000U)
+#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT        (16U)
+#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
+/*! @} */
+
+/*! @name VEND_SPEC2 - Vendor Specific 2 Register */
+/*! @{ */
+#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK   (0x8U)
+#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT  (3U)
+/*! CARD_INT_D3_TEST - Card Interrupt Detection Test
+ *  0b0..Check the card interrupt only when DATA3 is high.
+ *  0b1..Check the card interrupt by ignoring the status of DATA3.
+ */
+#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
+#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK    (0x1000U)
+#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT   (12U)
+/*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23
+ *  0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enable.
+ *  0b0..Disable
+ */
+#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
+#define USDHC_VEND_SPEC2_AHB_RST_MASK            (0x4000U)
+#define USDHC_VEND_SPEC2_AHB_RST_SHIFT           (14U)
+#define USDHC_VEND_SPEC2_AHB_RST(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_AHB_RST_SHIFT)) & USDHC_VEND_SPEC2_AHB_RST_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USDHC_Register_Masks */
+
+
+/* USDHC - Peripheral instance base addresses */
+/** Peripheral USDHC0 base address */
+#define USDHC0_BASE                              (0x4003E000u)
+/** Peripheral USDHC0 base pointer */
+#define USDHC0                                   ((USDHC_Type *)USDHC0_BASE)
+/** Array initializer of USDHC peripheral base addresses */
+#define USDHC_BASE_ADDRS                         { USDHC0_BASE }
+/** Array initializer of USDHC peripheral base pointers */
+#define USDHC_BASE_PTRS                          { USDHC0 }
+/** Interrupt vectors for the USDHC peripheral type */
+#define USDHC_IRQS                               { USDHC0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USDHC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- VREF Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t TRM;                                /**< VREF Trim Register, offset: 0x0 */
+  __IO uint8_t SC;                                 /**< VREF Status and Control Register, offset: 0x1 */
+       uint8_t RESERVED_0[3];
+  __IO uint8_t TRM4;                               /**< VREF Trim 2.1V Register, offset: 0x5 */
+} VREF_Type;
+
+/* ----------------------------------------------------------------------------
+   -- VREF Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/*! @name TRM - VREF Trim Register */
+/*! @{ */
+#define VREF_TRM_TRIM_MASK                       (0x3FU)
+#define VREF_TRM_TRIM_SHIFT                      (0U)
+/*! TRIM - Trim bits
+ *  0b000000..Min
+ *  0b111111..Max
+ */
+#define VREF_TRM_TRIM(x)                         (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK                     (0x40U)
+#define VREF_TRM_CHOPEN_SHIFT                    (6U)
+/*! CHOPEN - Chop oscillator enable. When set, the internal chopping operation is enabled and the internal analog offset will be minimized.
+ *  0b0..Chop oscillator is disabled.
+ *  0b1..Chop oscillator is enabled.
+ */
+#define VREF_TRM_CHOPEN(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
+/*! @} */
+
+/*! @name SC - VREF Status and Control Register */
+/*! @{ */
+#define VREF_SC_MODE_LV_MASK                     (0x3U)
+#define VREF_SC_MODE_LV_SHIFT                    (0U)
+/*! MODE_LV - Buffer Mode selection
+ *  0b00..Bandgap on only, for stabilization and startup
+ *  0b01..High power buffer mode enabled
+ *  0b10..Low-power buffer mode enabled
+ *  0b11..Reserved
+ */
+#define VREF_SC_MODE_LV(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK                      (0x4U)
+#define VREF_SC_VREFST_SHIFT                     (2U)
+/*! VREFST - Internal Voltage Reference stable
+ *  0b0..The module is disabled or not stable.
+ *  0b1..The module is stable.
+ */
+#define VREF_SC_VREFST(x)                        (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
+#define VREF_SC_ICOMPEN_MASK                     (0x20U)
+#define VREF_SC_ICOMPEN_SHIFT                    (5U)
+/*! ICOMPEN - Second order curvature compensation enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define VREF_SC_ICOMPEN(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
+#define VREF_SC_REGEN_MASK                       (0x40U)
+#define VREF_SC_REGEN_SHIFT                      (6U)
+/*! REGEN - Regulator enable
+ *  0b0..Internal 1.75 V regulator is disabled.
+ *  0b1..Internal 1.75 V regulator is enabled.
+ */
+#define VREF_SC_REGEN(x)                         (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
+#define VREF_SC_VREFEN_MASK                      (0x80U)
+#define VREF_SC_VREFEN_SHIFT                     (7U)
+/*! VREFEN - Internal Voltage Reference enable
+ *  0b0..The module is disabled.
+ *  0b1..The module is enabled.
+ */
+#define VREF_SC_VREFEN(x)                        (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
+/*! @} */
+
+/*! @name TRM4 - VREF Trim 2.1V Register */
+/*! @{ */
+#define VREF_TRM4_TRIM2V1_MASK                   (0x3FU)
+#define VREF_TRM4_TRIM2V1_SHIFT                  (0U)
+/*! TRIM2V1 - VREF 2.1V Trim Bits
+ *  0b000000..Max
+ *  0b111111..Min
+ */
+#define VREF_TRM4_TRIM2V1(x)                     (((uint8_t)(((uint8_t)(x)) << VREF_TRM4_TRIM2V1_SHIFT)) & VREF_TRM4_TRIM2V1_MASK)
+#define VREF_TRM4_VREF2V1_EN_MASK                (0x80U)
+#define VREF_TRM4_VREF2V1_EN_SHIFT               (7U)
+/*! VREF2V1_EN - Internal Voltage Reference (2.1V) Enable
+ *  0b0..VREF 2.1V is enabled
+ *  0b1..VREF 2.1V is disabled
+ */
+#define VREF_TRM4_VREF2V1_EN(x)                  (((uint8_t)(((uint8_t)(x)) << VREF_TRM4_VREF2V1_EN_SHIFT)) & VREF_TRM4_VREF2V1_EN_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE                                (0x4004D000u)
+/** Peripheral VREF base pointer */
+#define VREF                                     ((VREF_Type *)VREF_BASE)
+/** Array initializer of VREF peripheral base addresses */
+#define VREF_BASE_ADDRS                          { VREF_BASE }
+/** Array initializer of VREF peripheral base pointers */
+#define VREF_BASE_PTRS                           { VREF }
+
+/*!
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CS;                                /**< Watchdog Control and Status Register, offset: 0x0 */
+  __IO uint32_t CNT;                               /**< Watchdog Counter Register, offset: 0x4 */
+  __IO uint32_t TOVAL;                             /**< Watchdog Timeout Value Register, offset: 0x8 */
+  __IO uint32_t WIN;                               /**< Watchdog Window Register, offset: 0xC */
+} WDOG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/*! @name CS - Watchdog Control and Status Register */
+/*! @{ */
+#define WDOG_CS_STOP_MASK                        (0x1U)
+#define WDOG_CS_STOP_SHIFT                       (0U)
+/*! STOP - Stop Enable
+ *  0b0..Watchdog disabled in chip stop mode.
+ *  0b1..Watchdog enabled in chip stop mode.
+ */
+#define WDOG_CS_STOP(x)                          (((uint32_t)(((uint32_t)(x)) << WDOG_CS_STOP_SHIFT)) & WDOG_CS_STOP_MASK)
+#define WDOG_CS_WAIT_MASK                        (0x2U)
+#define WDOG_CS_WAIT_SHIFT                       (1U)
+/*! WAIT - Wait Enable
+ *  0b0..Watchdog disabled in chip wait mode.
+ *  0b1..Watchdog enabled in chip wait mode.
+ */
+#define WDOG_CS_WAIT(x)                          (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WAIT_SHIFT)) & WDOG_CS_WAIT_MASK)
+#define WDOG_CS_DBG_MASK                         (0x4U)
+#define WDOG_CS_DBG_SHIFT                        (2U)
+/*! DBG - Debug Enable
+ *  0b0..Watchdog disabled in chip debug mode.
+ *  0b1..Watchdog enabled in chip debug mode.
+ */
+#define WDOG_CS_DBG(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_DBG_SHIFT)) & WDOG_CS_DBG_MASK)
+#define WDOG_CS_TST_MASK                         (0x18U)
+#define WDOG_CS_TST_SHIFT                        (3U)
+/*! TST - Watchdog Test
+ *  0b00..Watchdog test mode disabled.
+ *  0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode.
+ *  0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW].
+ *  0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].
+ */
+#define WDOG_CS_TST(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_TST_SHIFT)) & WDOG_CS_TST_MASK)
+#define WDOG_CS_UPDATE_MASK                      (0x20U)
+#define WDOG_CS_UPDATE_SHIFT                     (5U)
+/*! UPDATE - Allow updates
+ *  0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset.
+ *  0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence.
+ */
+#define WDOG_CS_UPDATE(x)                        (((uint32_t)(((uint32_t)(x)) << WDOG_CS_UPDATE_SHIFT)) & WDOG_CS_UPDATE_MASK)
+#define WDOG_CS_INT_MASK                         (0x40U)
+#define WDOG_CS_INT_SHIFT                        (6U)
+/*! INT - Watchdog Interrupt
+ *  0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed.
+ *  0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch.
+ */
+#define WDOG_CS_INT(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_INT_SHIFT)) & WDOG_CS_INT_MASK)
+#define WDOG_CS_EN_MASK                          (0x80U)
+#define WDOG_CS_EN_SHIFT                         (7U)
+/*! EN - Watchdog Enable
+ *  0b0..Watchdog disabled.
+ *  0b1..Watchdog enabled.
+ */
+#define WDOG_CS_EN(x)                            (((uint32_t)(((uint32_t)(x)) << WDOG_CS_EN_SHIFT)) & WDOG_CS_EN_MASK)
+#define WDOG_CS_CLK_MASK                         (0x300U)
+#define WDOG_CS_CLK_SHIFT                        (8U)
+/*! CLK - Watchdog Clock
+ *  0b00..Bus clock
+ *  0b01..LPO clock
+ *  0b10..INTCLK (internal clock)
+ *  0b11..ERCLK (external reference clock)
+ */
+#define WDOG_CS_CLK(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CLK_SHIFT)) & WDOG_CS_CLK_MASK)
+#define WDOG_CS_RCS_MASK                         (0x400U)
+#define WDOG_CS_RCS_SHIFT                        (10U)
+/*! RCS - Reconfiguration Success
+ *  0b0..Reconfiguring WDOG.
+ *  0b1..Reconfiguration is successful.
+ */
+#define WDOG_CS_RCS(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_RCS_SHIFT)) & WDOG_CS_RCS_MASK)
+#define WDOG_CS_ULK_MASK                         (0x800U)
+#define WDOG_CS_ULK_SHIFT                        (11U)
+/*! ULK - Unlock status
+ *  0b0..WDOG is locked.
+ *  0b1..WDOG is unlocked.
+ */
+#define WDOG_CS_ULK(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_ULK_SHIFT)) & WDOG_CS_ULK_MASK)
+#define WDOG_CS_PRES_MASK                        (0x1000U)
+#define WDOG_CS_PRES_SHIFT                       (12U)
+/*! PRES - Watchdog prescaler
+ *  0b0..256 prescaler disabled.
+ *  0b1..256 prescaler enabled.
+ */
+#define WDOG_CS_PRES(x)                          (((uint32_t)(((uint32_t)(x)) << WDOG_CS_PRES_SHIFT)) & WDOG_CS_PRES_MASK)
+#define WDOG_CS_CMD32EN_MASK                     (0x2000U)
+#define WDOG_CS_CMD32EN_SHIFT                    (13U)
+/*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words
+ *  0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported.
+ *  0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported.
+ */
+#define WDOG_CS_CMD32EN(x)                       (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CMD32EN_SHIFT)) & WDOG_CS_CMD32EN_MASK)
+#define WDOG_CS_FLG_MASK                         (0x4000U)
+#define WDOG_CS_FLG_SHIFT                        (14U)
+/*! FLG - Watchdog Interrupt Flag
+ *  0b0..No interrupt occurred.
+ *  0b1..An interrupt occurred.
+ */
+#define WDOG_CS_FLG(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_FLG_SHIFT)) & WDOG_CS_FLG_MASK)
+#define WDOG_CS_WIN_MASK                         (0x8000U)
+#define WDOG_CS_WIN_SHIFT                        (15U)
+/*! WIN - Watchdog Window
+ *  0b0..Window mode disabled.
+ *  0b1..Window mode enabled.
+ */
+#define WDOG_CS_WIN(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WIN_SHIFT)) & WDOG_CS_WIN_MASK)
+/*! @} */
+
+/*! @name CNT - Watchdog Counter Register */
+/*! @{ */
+#define WDOG_CNT_CNTLOW_MASK                     (0xFFU)
+#define WDOG_CNT_CNTLOW_SHIFT                    (0U)
+#define WDOG_CNT_CNTLOW(x)                       (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTLOW_SHIFT)) & WDOG_CNT_CNTLOW_MASK)
+#define WDOG_CNT_CNTHIGH_MASK                    (0xFF00U)
+#define WDOG_CNT_CNTHIGH_SHIFT                   (8U)
+#define WDOG_CNT_CNTHIGH(x)                      (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTHIGH_SHIFT)) & WDOG_CNT_CNTHIGH_MASK)
+/*! @} */
+
+/*! @name TOVAL - Watchdog Timeout Value Register */
+/*! @{ */
+#define WDOG_TOVAL_TOVALLOW_MASK                 (0xFFU)
+#define WDOG_TOVAL_TOVALLOW_SHIFT                (0U)
+#define WDOG_TOVAL_TOVALLOW(x)                   (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALLOW_SHIFT)) & WDOG_TOVAL_TOVALLOW_MASK)
+#define WDOG_TOVAL_TOVALHIGH_MASK                (0xFF00U)
+#define WDOG_TOVAL_TOVALHIGH_SHIFT               (8U)
+#define WDOG_TOVAL_TOVALHIGH(x)                  (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALHIGH_SHIFT)) & WDOG_TOVAL_TOVALHIGH_MASK)
+/*! @} */
+
+/*! @name WIN - Watchdog Window Register */
+/*! @{ */
+#define WDOG_WIN_WINLOW_MASK                     (0xFFU)
+#define WDOG_WIN_WINLOW_SHIFT                    (0U)
+#define WDOG_WIN_WINLOW(x)                       (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINLOW_SHIFT)) & WDOG_WIN_WINLOW_MASK)
+#define WDOG_WIN_WINHIGH_MASK                    (0xFF00U)
+#define WDOG_WIN_WINHIGH_SHIFT                   (8U)
+#define WDOG_WIN_WINHIGH(x)                      (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINHIGH_SHIFT)) & WDOG_WIN_WINHIGH_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG0 base address */
+#define WDOG0_BASE                               (0x4002A000u)
+/** Peripheral WDOG0 base pointer */
+#define WDOG0                                    ((WDOG_Type *)WDOG0_BASE)
+/** Peripheral WDOG1 base address */
+#define WDOG1_BASE                               (0x41026000u)
+/** Peripheral WDOG1 base pointer */
+#define WDOG1                                    ((WDOG_Type *)WDOG1_BASE)
+/** Array initializer of WDOG peripheral base addresses */
+#define WDOG_BASE_ADDRS                          { WDOG0_BASE, WDOG1_BASE }
+/** Array initializer of WDOG peripheral base pointers */
+#define WDOG_BASE_PTRS                           { WDOG0, WDOG1 }
+/** Interrupt vectors for the WDOG peripheral type */
+#define WDOG_IRQS                                { WDOG0_IRQn, NotAvail_IRQn }
+/* Extra definition */
+#define WDOG_UPDATE_KEY                          (0xD928C520U)
+#define WDOG_REFRESH_KEY                         (0xB480A602U)
+
+
+/*!
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- XRDC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XRDC_Peripheral_Access_Layer XRDC Peripheral Access Layer
+ * @{
+ */
+
+/** XRDC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /**< Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[236];
+  __I  uint32_t HWCFG0;                            /**< Hardware Configuration Register 0, offset: 0xF0 */
+  __I  uint32_t HWCFG1;                            /**< Hardware Configuration Register 1, offset: 0xF4 */
+  __I  uint32_t HWCFG2;                            /**< Hardware Configuration Register 2, offset: 0xF8 */
+  __I  uint32_t HWCFG3;                            /**< Hardware Configuration Register 3, offset: 0xFC */
+  __I  uint8_t MDACFG[37];                         /**< Master Domain Assignment Configuration Register, array offset: 0x100, array step: 0x1 */
+       uint8_t RESERVED_1[27];
+  __I  uint8_t MRCFG[2];                           /**< Memory Region Configuration Register, array offset: 0x140, array step: 0x1 */
+       uint8_t RESERVED_2[186];
+  __IO uint32_t FDID;                              /**< Fault Domain ID, offset: 0x1FC */
+  __I  uint32_t DERRLOC[3];                        /**< Domain Error Location Register, array offset: 0x200, array step: 0x4 */
+       uint8_t RESERVED_3[500];
+  __IO uint32_t DERR_W[19][4];                     /**< Domain Error Word0 Register..Domain Error Word3 Register, array offset: 0x400, array step: index*0x10, index2*0x4 */
+       uint8_t RESERVED_4[464];
+  __IO uint32_t PID[37];                           /**< Process Identifier, array offset: 0x700, array step: 0x4 */
+       uint8_t RESERVED_5[108];
+  struct {                                         /* offset: 0x800, array step: 0x20 */
+    __IO uint32_t MDA_W[2];                          /**< Master Domain Assignment, array offset: 0x800, array step: index*0x20, index2*0x4 */
+         uint8_t RESERVED_0[24];
+  } MDA[37];
+       uint8_t RESERVED_6[864];
+  __IO uint32_t PDAC_W[289][2];                    /**< Peripheral Domain Access Control, array offset: 0x1000, array step: index*0x8, index2*0x4 */
+       uint8_t RESERVED_7[1784];
+  struct {                                         /* offset: 0x2000, array step: 0x20 */
+    __IO uint32_t MRGD_W[5];                         /**< Memory Region Descriptor, array offset: 0x2000, array step: index*0x20, index2*0x4 */
+         uint8_t RESERVED_0[12];
+  } MRGD[24];
+} XRDC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- XRDC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XRDC_Register_Masks XRDC Register Masks
+ * @{
+ */
+
+/*! @name CR - Control Register */
+/*! @{ */
+#define XRDC_CR_GVLDM_MASK                       (0x1U)
+#define XRDC_CR_GVLDM_SHIFT                      (0U)
+/*! GVLDM - Global Valid MDACs(XRDC global enable/disable).
+ *  0b0..XRDC MDACs are disabled.
+ *  0b1..XRDC MDACs are enabled.
+ */
+#define XRDC_CR_GVLDM(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC_CR_GVLDM_SHIFT)) & XRDC_CR_GVLDM_MASK)
+#define XRDC_CR_HRL_MASK                         (0x1EU)
+#define XRDC_CR_HRL_SHIFT                        (1U)
+#define XRDC_CR_HRL(x)                           (((uint32_t)(((uint32_t)(x)) << XRDC_CR_HRL_SHIFT)) & XRDC_CR_HRL_MASK)
+#define XRDC_CR_VAW_MASK                         (0x100U)
+#define XRDC_CR_VAW_SHIFT                        (8U)
+/*! VAW - Virtualization aware
+ *  0b0..Implementation is not virtualization aware.
+ *  0b1..Implementation is virtualization aware.
+ */
+#define XRDC_CR_VAW(x)                           (((uint32_t)(((uint32_t)(x)) << XRDC_CR_VAW_SHIFT)) & XRDC_CR_VAW_MASK)
+#define XRDC_CR_GVLDP_MASK                       (0x4000U)
+#define XRDC_CR_GVLDP_SHIFT                      (14U)
+/*! GVLDP - Global Valid for PACs/MSCs
+ *  0b0..XRDC PACs/MSCs are disabled.
+ *  0b1..XRDC PACs/MSCs are enabled.
+ */
+#define XRDC_CR_GVLDP(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC_CR_GVLDP_SHIFT)) & XRDC_CR_GVLDP_MASK)
+#define XRDC_CR_GVLDC_MASK                       (0x8000U)
+#define XRDC_CR_GVLDC_SHIFT                      (15U)
+/*! GVLDC - Global Valid for MRCs
+ *  0b0..XRDC MRCs are disabled.
+ *  0b1..XRDC MRCs are enabled.
+ */
+#define XRDC_CR_GVLDC(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC_CR_GVLDC_SHIFT)) & XRDC_CR_GVLDC_MASK)
+#define XRDC_CR_LK1_MASK                         (0x40000000U)
+#define XRDC_CR_LK1_SHIFT                        (30U)
+/*! LK1 - 1-bit Lock
+ *  0b0..Register can be written by any secure privileged write.
+ *  0b1..Register is locked (read-only) until the next reset.
+ */
+#define XRDC_CR_LK1(x)                           (((uint32_t)(((uint32_t)(x)) << XRDC_CR_LK1_SHIFT)) & XRDC_CR_LK1_MASK)
+/*! @} */
+
+/*! @name HWCFG0 - Hardware Configuration Register 0 */
+/*! @{ */
+#define XRDC_HWCFG0_NDID_MASK                    (0xFFU)
+#define XRDC_HWCFG0_NDID_SHIFT                   (0U)
+#define XRDC_HWCFG0_NDID(x)                      (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NDID_SHIFT)) & XRDC_HWCFG0_NDID_MASK)
+#define XRDC_HWCFG0_NMSTR_MASK                   (0xFF00U)
+#define XRDC_HWCFG0_NMSTR_SHIFT                  (8U)
+#define XRDC_HWCFG0_NMSTR(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NMSTR_SHIFT)) & XRDC_HWCFG0_NMSTR_MASK)
+#define XRDC_HWCFG0_NMRC_MASK                    (0xFF0000U)
+#define XRDC_HWCFG0_NMRC_SHIFT                   (16U)
+#define XRDC_HWCFG0_NMRC(x)                      (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NMRC_SHIFT)) & XRDC_HWCFG0_NMRC_MASK)
+#define XRDC_HWCFG0_NPAC_MASK                    (0xF000000U)
+#define XRDC_HWCFG0_NPAC_SHIFT                   (24U)
+#define XRDC_HWCFG0_NPAC(x)                      (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NPAC_SHIFT)) & XRDC_HWCFG0_NPAC_MASK)
+#define XRDC_HWCFG0_MID_MASK                     (0xF0000000U)
+#define XRDC_HWCFG0_MID_SHIFT                    (28U)
+#define XRDC_HWCFG0_MID(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_MID_SHIFT)) & XRDC_HWCFG0_MID_MASK)
+/*! @} */
+
+/*! @name HWCFG1 - Hardware Configuration Register 1 */
+/*! @{ */
+#define XRDC_HWCFG1_DID_MASK                     (0xFU)
+#define XRDC_HWCFG1_DID_SHIFT                    (0U)
+#define XRDC_HWCFG1_DID(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG1_DID_SHIFT)) & XRDC_HWCFG1_DID_MASK)
+/*! @} */
+
+/*! @name HWCFG2 - Hardware Configuration Register 2 */
+/*! @{ */
+#define XRDC_HWCFG2_PIDP0_MASK                   (0x1U)
+#define XRDC_HWCFG2_PIDP0_SHIFT                  (0U)
+/*! PIDP0 - Process identifier
+ *  0b0..Bus master 0 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 0 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP0(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP0_SHIFT)) & XRDC_HWCFG2_PIDP0_MASK)
+#define XRDC_HWCFG2_PIDP1_MASK                   (0x2U)
+#define XRDC_HWCFG2_PIDP1_SHIFT                  (1U)
+/*! PIDP1 - Process identifier
+ *  0b0..Bus master 1 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 1 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP1(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP1_SHIFT)) & XRDC_HWCFG2_PIDP1_MASK)
+#define XRDC_HWCFG2_PIDP2_MASK                   (0x4U)
+#define XRDC_HWCFG2_PIDP2_SHIFT                  (2U)
+/*! PIDP2 - Process identifier
+ *  0b0..Bus master 2 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 2 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP2(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP2_SHIFT)) & XRDC_HWCFG2_PIDP2_MASK)
+#define XRDC_HWCFG2_PIDP3_MASK                   (0x8U)
+#define XRDC_HWCFG2_PIDP3_SHIFT                  (3U)
+/*! PIDP3 - Process identifier
+ *  0b0..Bus master 3 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 3 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP3(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP3_SHIFT)) & XRDC_HWCFG2_PIDP3_MASK)
+#define XRDC_HWCFG2_PIDP4_MASK                   (0x10U)
+#define XRDC_HWCFG2_PIDP4_SHIFT                  (4U)
+/*! PIDP4 - Process identifier
+ *  0b0..Bus master 4 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 4 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP4(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP4_SHIFT)) & XRDC_HWCFG2_PIDP4_MASK)
+#define XRDC_HWCFG2_PIDP5_MASK                   (0x20U)
+#define XRDC_HWCFG2_PIDP5_SHIFT                  (5U)
+/*! PIDP5 - Process identifier
+ *  0b0..Bus master 5 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 5 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP5(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP5_SHIFT)) & XRDC_HWCFG2_PIDP5_MASK)
+#define XRDC_HWCFG2_PIDP6_MASK                   (0x40U)
+#define XRDC_HWCFG2_PIDP6_SHIFT                  (6U)
+/*! PIDP6 - Process identifier
+ *  0b0..Bus master 6 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 6 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP6(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP6_SHIFT)) & XRDC_HWCFG2_PIDP6_MASK)
+#define XRDC_HWCFG2_PIDP7_MASK                   (0x80U)
+#define XRDC_HWCFG2_PIDP7_SHIFT                  (7U)
+/*! PIDP7 - Process identifier
+ *  0b0..Bus master 7 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 7 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP7(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP7_SHIFT)) & XRDC_HWCFG2_PIDP7_MASK)
+#define XRDC_HWCFG2_PIDP8_MASK                   (0x100U)
+#define XRDC_HWCFG2_PIDP8_SHIFT                  (8U)
+/*! PIDP8 - Process identifier
+ *  0b0..Bus master 8 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 8 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP8(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP8_SHIFT)) & XRDC_HWCFG2_PIDP8_MASK)
+#define XRDC_HWCFG2_PIDP9_MASK                   (0x200U)
+#define XRDC_HWCFG2_PIDP9_SHIFT                  (9U)
+/*! PIDP9 - Process identifier
+ *  0b0..Bus master 9 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 9 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP9(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP9_SHIFT)) & XRDC_HWCFG2_PIDP9_MASK)
+#define XRDC_HWCFG2_PIDP10_MASK                  (0x400U)
+#define XRDC_HWCFG2_PIDP10_SHIFT                 (10U)
+/*! PIDP10 - Process identifier
+ *  0b0..Bus master 10 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 10 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP10(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP10_SHIFT)) & XRDC_HWCFG2_PIDP10_MASK)
+#define XRDC_HWCFG2_PIDP11_MASK                  (0x800U)
+#define XRDC_HWCFG2_PIDP11_SHIFT                 (11U)
+/*! PIDP11 - Process identifier
+ *  0b0..Bus master 11 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 11 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP11(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP11_SHIFT)) & XRDC_HWCFG2_PIDP11_MASK)
+#define XRDC_HWCFG2_PIDP12_MASK                  (0x1000U)
+#define XRDC_HWCFG2_PIDP12_SHIFT                 (12U)
+/*! PIDP12 - Process identifier
+ *  0b0..Bus master 12 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 12 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP12(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP12_SHIFT)) & XRDC_HWCFG2_PIDP12_MASK)
+#define XRDC_HWCFG2_PIDP13_MASK                  (0x2000U)
+#define XRDC_HWCFG2_PIDP13_SHIFT                 (13U)
+/*! PIDP13 - Process identifier
+ *  0b0..Bus master 13 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 13 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP13(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP13_SHIFT)) & XRDC_HWCFG2_PIDP13_MASK)
+#define XRDC_HWCFG2_PIDP14_MASK                  (0x4000U)
+#define XRDC_HWCFG2_PIDP14_SHIFT                 (14U)
+/*! PIDP14 - Process identifier
+ *  0b0..Bus master 14 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 14 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP14(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP14_SHIFT)) & XRDC_HWCFG2_PIDP14_MASK)
+#define XRDC_HWCFG2_PIDP15_MASK                  (0x8000U)
+#define XRDC_HWCFG2_PIDP15_SHIFT                 (15U)
+/*! PIDP15 - Process identifier
+ *  0b0..Bus master 15 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 15 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP15(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP15_SHIFT)) & XRDC_HWCFG2_PIDP15_MASK)
+#define XRDC_HWCFG2_PIDP16_MASK                  (0x10000U)
+#define XRDC_HWCFG2_PIDP16_SHIFT                 (16U)
+/*! PIDP16 - Process identifier
+ *  0b0..Bus master 16 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 16 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP16(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP16_SHIFT)) & XRDC_HWCFG2_PIDP16_MASK)
+#define XRDC_HWCFG2_PIDP17_MASK                  (0x20000U)
+#define XRDC_HWCFG2_PIDP17_SHIFT                 (17U)
+/*! PIDP17 - Process identifier
+ *  0b0..Bus master 17 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 17 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP17(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP17_SHIFT)) & XRDC_HWCFG2_PIDP17_MASK)
+#define XRDC_HWCFG2_PIDP18_MASK                  (0x40000U)
+#define XRDC_HWCFG2_PIDP18_SHIFT                 (18U)
+/*! PIDP18 - Process identifier
+ *  0b0..Bus master 18 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 18 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP18(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP18_SHIFT)) & XRDC_HWCFG2_PIDP18_MASK)
+#define XRDC_HWCFG2_PIDP19_MASK                  (0x80000U)
+#define XRDC_HWCFG2_PIDP19_SHIFT                 (19U)
+/*! PIDP19 - Process identifier
+ *  0b0..Bus master 19 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 19 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP19(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP19_SHIFT)) & XRDC_HWCFG2_PIDP19_MASK)
+#define XRDC_HWCFG2_PIDP20_MASK                  (0x100000U)
+#define XRDC_HWCFG2_PIDP20_SHIFT                 (20U)
+/*! PIDP20 - Process identifier
+ *  0b0..Bus master 20 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 20 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP20(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP20_SHIFT)) & XRDC_HWCFG2_PIDP20_MASK)
+#define XRDC_HWCFG2_PIDP21_MASK                  (0x200000U)
+#define XRDC_HWCFG2_PIDP21_SHIFT                 (21U)
+/*! PIDP21 - Process identifier
+ *  0b0..Bus master 21 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 21 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP21(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP21_SHIFT)) & XRDC_HWCFG2_PIDP21_MASK)
+#define XRDC_HWCFG2_PIDP22_MASK                  (0x400000U)
+#define XRDC_HWCFG2_PIDP22_SHIFT                 (22U)
+/*! PIDP22 - Process identifier
+ *  0b0..Bus master 22 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 22 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP22(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP22_SHIFT)) & XRDC_HWCFG2_PIDP22_MASK)
+#define XRDC_HWCFG2_PIDP23_MASK                  (0x800000U)
+#define XRDC_HWCFG2_PIDP23_SHIFT                 (23U)
+/*! PIDP23 - Process identifier
+ *  0b0..Bus master 23 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 23 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP23(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP23_SHIFT)) & XRDC_HWCFG2_PIDP23_MASK)
+#define XRDC_HWCFG2_PIDP24_MASK                  (0x1000000U)
+#define XRDC_HWCFG2_PIDP24_SHIFT                 (24U)
+/*! PIDP24 - Process identifier
+ *  0b0..Bus master 24 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 24 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP24(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP24_SHIFT)) & XRDC_HWCFG2_PIDP24_MASK)
+#define XRDC_HWCFG2_PIDP25_MASK                  (0x2000000U)
+#define XRDC_HWCFG2_PIDP25_SHIFT                 (25U)
+/*! PIDP25 - Process identifier
+ *  0b0..Bus master 25 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 25 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP25(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP25_SHIFT)) & XRDC_HWCFG2_PIDP25_MASK)
+#define XRDC_HWCFG2_PIDP26_MASK                  (0x4000000U)
+#define XRDC_HWCFG2_PIDP26_SHIFT                 (26U)
+/*! PIDP26 - Process identifier
+ *  0b0..Bus master 26 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 26 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP26(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP26_SHIFT)) & XRDC_HWCFG2_PIDP26_MASK)
+#define XRDC_HWCFG2_PIDP27_MASK                  (0x8000000U)
+#define XRDC_HWCFG2_PIDP27_SHIFT                 (27U)
+/*! PIDP27 - Process identifier
+ *  0b0..Bus master 27 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 27 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP27(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP27_SHIFT)) & XRDC_HWCFG2_PIDP27_MASK)
+#define XRDC_HWCFG2_PIDP28_MASK                  (0x10000000U)
+#define XRDC_HWCFG2_PIDP28_SHIFT                 (28U)
+/*! PIDP28 - Process identifier
+ *  0b0..Bus master 28 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 28 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP28(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP28_SHIFT)) & XRDC_HWCFG2_PIDP28_MASK)
+#define XRDC_HWCFG2_PIDP29_MASK                  (0x20000000U)
+#define XRDC_HWCFG2_PIDP29_SHIFT                 (29U)
+/*! PIDP29 - Process identifier
+ *  0b0..Bus master 29 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 29 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP29(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP29_SHIFT)) & XRDC_HWCFG2_PIDP29_MASK)
+#define XRDC_HWCFG2_PIDP30_MASK                  (0x40000000U)
+#define XRDC_HWCFG2_PIDP30_SHIFT                 (30U)
+/*! PIDP30 - Process identifier
+ *  0b0..Bus master 30 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 30 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP30(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP30_SHIFT)) & XRDC_HWCFG2_PIDP30_MASK)
+#define XRDC_HWCFG2_PIDP31_MASK                  (0x80000000U)
+#define XRDC_HWCFG2_PIDP31_SHIFT                 (31U)
+/*! PIDP31 - Process identifier
+ *  0b0..Bus master 31 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 31 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP31(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP31_SHIFT)) & XRDC_HWCFG2_PIDP31_MASK)
+/*! @} */
+
+/*! @name HWCFG3 - Hardware Configuration Register 3 */
+/*! @{ */
+#define XRDC_HWCFG3_PIDPn_MASK                   (0xFFFFFFFFU)
+#define XRDC_HWCFG3_PIDPn_SHIFT                  (0U)
+#define XRDC_HWCFG3_PIDPn(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDPn_SHIFT)) & XRDC_HWCFG3_PIDPn_MASK)
+/*! @} */
+
+/*! @name MDACFG - Master Domain Assignment Configuration Register */
+/*! @{ */
+#define XRDC_MDACFG_NMDAR_MASK                   (0xFU)
+#define XRDC_MDACFG_NMDAR_SHIFT                  (0U)
+#define XRDC_MDACFG_NMDAR(x)                     (((uint8_t)(((uint8_t)(x)) << XRDC_MDACFG_NMDAR_SHIFT)) & XRDC_MDACFG_NMDAR_MASK)
+#define XRDC_MDACFG_NCM_MASK                     (0x80U)
+#define XRDC_MDACFG_NCM_SHIFT                    (7U)
+/*! NCM - Non-CPU Master
+ *  0b0..Bus master is a processor.
+ *  0b1..Bus master is a non-processor.
+ */
+#define XRDC_MDACFG_NCM(x)                       (((uint8_t)(((uint8_t)(x)) << XRDC_MDACFG_NCM_SHIFT)) & XRDC_MDACFG_NCM_MASK)
+/*! @} */
+
+/* The count of XRDC_MDACFG */
+#define XRDC_MDACFG_COUNT                        (37U)
+
+/*! @name MRCFG - Memory Region Configuration Register */
+/*! @{ */
+#define XRDC_MRCFG_NMRGD_MASK                    (0x1FU)
+#define XRDC_MRCFG_NMRGD_SHIFT                   (0U)
+#define XRDC_MRCFG_NMRGD(x)                      (((uint8_t)(((uint8_t)(x)) << XRDC_MRCFG_NMRGD_SHIFT)) & XRDC_MRCFG_NMRGD_MASK)
+/*! @} */
+
+/* The count of XRDC_MRCFG */
+#define XRDC_MRCFG_COUNT                         (2U)
+
+/*! @name FDID - Fault Domain ID */
+/*! @{ */
+#define XRDC_FDID_FDID_MASK                      (0xFU)
+#define XRDC_FDID_FDID_SHIFT                     (0U)
+#define XRDC_FDID_FDID(x)                        (((uint32_t)(((uint32_t)(x)) << XRDC_FDID_FDID_SHIFT)) & XRDC_FDID_FDID_MASK)
+/*! @} */
+
+/*! @name DERRLOC - Domain Error Location Register */
+/*! @{ */
+#define XRDC_DERRLOC_MRCINST_MASK                (0xFFFFU)
+#define XRDC_DERRLOC_MRCINST_SHIFT               (0U)
+#define XRDC_DERRLOC_MRCINST(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERRLOC_MRCINST_SHIFT)) & XRDC_DERRLOC_MRCINST_MASK)
+#define XRDC_DERRLOC_PACINST_MASK                (0xF0000U)
+#define XRDC_DERRLOC_PACINST_SHIFT               (16U)
+#define XRDC_DERRLOC_PACINST(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERRLOC_PACINST_SHIFT)) & XRDC_DERRLOC_PACINST_MASK)
+/*! @} */
+
+/* The count of XRDC_DERRLOC */
+#define XRDC_DERRLOC_COUNT                       (3U)
+
+/*! @name DERR_W - Domain Error Word0 Register..Domain Error Word3 Register */
+/*! @{ */
+#define XRDC_DERR_W_EADDR_MASK                   (0xFFFFFFFFU)
+#define XRDC_DERR_W_EADDR_SHIFT                  (0U)
+#define XRDC_DERR_W_EADDR(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EADDR_SHIFT)) & XRDC_DERR_W_EADDR_MASK)
+#define XRDC_DERR_W_EDID_MASK                    (0xFU)
+#define XRDC_DERR_W_EDID_SHIFT                   (0U)
+#define XRDC_DERR_W_EDID(x)                      (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EDID_SHIFT)) & XRDC_DERR_W_EDID_MASK)
+#define XRDC_DERR_W_EATR_MASK                    (0x700U)
+#define XRDC_DERR_W_EATR_SHIFT                   (8U)
+/*! EATR - Error attributes
+ *  0b000..Secure user mode, instruction fetch access.
+ *  0b001..Secure user mode, data access.
+ *  0b010..Secure privileged mode, instruction fetch access.
+ *  0b011..Secure privileged mode, data access.
+ *  0b100..Nonsecure user mode, instruction fetch access.
+ *  0b101..Nonsecure user mode, data access.
+ *  0b110..Nonsecure privileged mode, instruction fetch access.
+ *  0b111..Nonsecure privileged mode, data access.
+ */
+#define XRDC_DERR_W_EATR(x)                      (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EATR_SHIFT)) & XRDC_DERR_W_EATR_MASK)
+#define XRDC_DERR_W_ERW_MASK                     (0x800U)
+#define XRDC_DERR_W_ERW_SHIFT                    (11U)
+/*! ERW - Error read/write
+ *  0b0..Read access
+ *  0b1..Write access
+ */
+#define XRDC_DERR_W_ERW(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_ERW_SHIFT)) & XRDC_DERR_W_ERW_MASK)
+#define XRDC_DERR_W_EPORT_MASK                   (0x7000000U)
+#define XRDC_DERR_W_EPORT_SHIFT                  (24U)
+#define XRDC_DERR_W_EPORT(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EPORT_SHIFT)) & XRDC_DERR_W_EPORT_MASK)
+#define XRDC_DERR_W_EST_MASK                     (0xC0000000U)
+#define XRDC_DERR_W_EST_SHIFT                    (30U)
+/*! EST - Error state
+ *  0b00..No access violation has been detected.
+ *  0b01..No access violation has been detected.
+ *  0b10..A single access violation has been detected.
+ *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
+ */
+#define XRDC_DERR_W_EST(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EST_SHIFT)) & XRDC_DERR_W_EST_MASK)
+#define XRDC_DERR_W_RECR_MASK                    (0xC0000000U)
+#define XRDC_DERR_W_RECR_SHIFT                   (30U)
+#define XRDC_DERR_W_RECR(x)                      (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_RECR_SHIFT)) & XRDC_DERR_W_RECR_MASK)
+/*! @} */
+
+/* The count of XRDC_DERR_W */
+#define XRDC_DERR_W_COUNT                        (19U)
+
+/* The count of XRDC_DERR_W */
+#define XRDC_DERR_W_COUNT2                       (4U)
+
+/*! @name PID - Process Identifier */
+/*! @{ */
+#define XRDC_PID_PID_MASK                        (0x3FU)
+#define XRDC_PID_PID_SHIFT                       (0U)
+#define XRDC_PID_PID(x)                          (((uint32_t)(((uint32_t)(x)) << XRDC_PID_PID_SHIFT)) & XRDC_PID_PID_MASK)
+#define XRDC_PID_SP4SM_MASK                      (0x8000000U)
+#define XRDC_PID_SP4SM_SHIFT                     (27U)
+#define XRDC_PID_SP4SM(x)                        (((uint32_t)(((uint32_t)(x)) << XRDC_PID_SP4SM_SHIFT)) & XRDC_PID_SP4SM_MASK)
+#define XRDC_PID_TSM_MASK                        (0x10000000U)
+#define XRDC_PID_TSM_SHIFT                       (28U)
+#define XRDC_PID_TSM(x)                          (((uint32_t)(((uint32_t)(x)) << XRDC_PID_TSM_SHIFT)) & XRDC_PID_TSM_MASK)
+#define XRDC_PID_LK2_MASK                        (0x60000000U)
+#define XRDC_PID_LK2_SHIFT                       (29U)
+/*! LK2 - Lock
+ *  0b00..Register can be written by any secure privileged write.
+ *  0b01..Register can be written by any secure privileged write.
+ *  0b10..Register can only be written by a secure privileged write from bus master m.
+ *  0b11..Register is locked (read-only) until the next reset.
+ */
+#define XRDC_PID_LK2(x)                          (((uint32_t)(((uint32_t)(x)) << XRDC_PID_LK2_SHIFT)) & XRDC_PID_LK2_MASK)
+/*! @} */
+
+/* The count of XRDC_PID */
+#define XRDC_PID_COUNT                           (37U)
+
+/*! @name MDA_W - Master Domain Assignment */
+/*! @{ */
+#define XRDC_MDA_W_DID_MASK                      (0xFU)
+#define XRDC_MDA_W_DID_SHIFT                     (0U)
+#define XRDC_MDA_W_DID(x)                        (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_DID_SHIFT)) & XRDC_MDA_W_DID_MASK)
+#define XRDC_MDA_W_DIDS_MASK                     (0x30U)
+#define XRDC_MDA_W_DIDS_SHIFT                    (4U)
+/*! DIDS - DID Select
+ *  0b00..Use MDAm[3:0] as the domain identifier.
+ *  0b01..Use the input DID as the domain identifier.
+ *  0b10..Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier.
+ *  0b11..Reserved for future use.
+ */
+#define XRDC_MDA_W_DIDS(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_DIDS_SHIFT)) & XRDC_MDA_W_DIDS_MASK)
+#define XRDC_MDA_W_PA_MASK                       (0x30U)
+#define XRDC_MDA_W_PA_SHIFT                      (4U)
+/*! PA - Privileged attribute
+ *  0b00..Force the bus attribute for this master to user.
+ *  0b01..Force the bus attribute for this master to privileged.
+ *  0b10..Use the bus master's privileged/user attribute directly.
+ *  0b11..Use the bus master's privileged/user attribute directly.
+ */
+#define XRDC_MDA_W_PA(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_PA_SHIFT)) & XRDC_MDA_W_PA_MASK)
+#define XRDC_MDA_W_PE_MASK                       (0xC0U)
+#define XRDC_MDA_W_PE_SHIFT                      (6U)
+/*! PE - Process identifier enable
+ *  0b00..No process identifier is included in the domain hit evaluation.
+ *  0b01..No process identifier is included in the domain hit evaluation.
+ *  0b10..The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM))
+ *  0b11..The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ~((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM))
+ */
+#define XRDC_MDA_W_PE(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_PE_SHIFT)) & XRDC_MDA_W_PE_MASK)
+#define XRDC_MDA_W_SA_MASK                       (0xC0U)
+#define XRDC_MDA_W_SA_SHIFT                      (6U)
+/*! SA - Secure attribute
+ *  0b00..Force the bus attribute for this master to secure.
+ *  0b01..Force the bus attribute for this master to nonsecure.
+ *  0b10..Use the bus master's secure/nonsecure attribute directly.
+ *  0b11..Use the bus master's secure/nonsecure attribute directly.
+ */
+#define XRDC_MDA_W_SA(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_SA_SHIFT)) & XRDC_MDA_W_SA_MASK)
+#define XRDC_MDA_W_DIDB_MASK                     (0x100U)
+#define XRDC_MDA_W_DIDB_SHIFT                    (8U)
+/*! DIDB - DID Bypass
+ *  0b0..Use MDAn[3:0] as the domain identifier.
+ *  0b1..Use the DID input as the domain identifier.
+ */
+#define XRDC_MDA_W_DIDB(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_DIDB_SHIFT)) & XRDC_MDA_W_DIDB_MASK)
+#define XRDC_MDA_W_PIDM_MASK                     (0x3F00U)
+#define XRDC_MDA_W_PIDM_SHIFT                    (8U)
+#define XRDC_MDA_W_PIDM(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_PIDM_SHIFT)) & XRDC_MDA_W_PIDM_MASK)
+#define XRDC_MDA_W_PID_MASK                      (0x3F0000U)
+#define XRDC_MDA_W_PID_SHIFT                     (16U)
+#define XRDC_MDA_W_PID(x)                        (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_PID_SHIFT)) & XRDC_MDA_W_PID_MASK)
+#define XRDC_MDA_W_DFMT_MASK                     (0x20000000U)
+#define XRDC_MDA_W_DFMT_SHIFT                    (29U)
+/*! DFMT - Domain format
+ *  0b0..Processor-core domain assignment
+ *  0b1..Non-processor domain assignment
+ */
+#define XRDC_MDA_W_DFMT(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_DFMT_SHIFT)) & XRDC_MDA_W_DFMT_MASK)
+#define XRDC_MDA_W_LK1_MASK                      (0x40000000U)
+#define XRDC_MDA_W_LK1_SHIFT                     (30U)
+/*! LK1 - 1-bit Lock
+ *  0b0..Register can be written by any secure privileged write.
+ *  0b1..Register is locked (read-only) until the next reset.
+ */
+#define XRDC_MDA_W_LK1(x)                        (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_LK1_SHIFT)) & XRDC_MDA_W_LK1_MASK)
+#define XRDC_MDA_W_VLD_MASK                      (0x80000000U)
+#define XRDC_MDA_W_VLD_SHIFT                     (31U)
+/*! VLD - Valid
+ *  0b0..The Wr domain assignment is invalid.
+ *  0b1..The Wr domain assignment is valid.
+ */
+#define XRDC_MDA_W_VLD(x)                        (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_VLD_SHIFT)) & XRDC_MDA_W_VLD_MASK)
+/*! @} */
+
+/* The count of XRDC_MDA_W */
+#define XRDC_MDA_W_COUNT                         (37U)
+
+/* The count of XRDC_MDA_W */
+#define XRDC_MDA_W_COUNT2                        (2U)
+
+/*! @name PDAC_W - Peripheral Domain Access Control */
+/*! @{ */
+#define XRDC_PDAC_W_D0ACP_MASK                   (0x7U)
+#define XRDC_PDAC_W_D0ACP_SHIFT                  (0U)
+#define XRDC_PDAC_W_D0ACP(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D0ACP_SHIFT)) & XRDC_PDAC_W_D0ACP_MASK)
+#define XRDC_PDAC_W_D1ACP_MASK                   (0x38U)
+#define XRDC_PDAC_W_D1ACP_SHIFT                  (3U)
+#define XRDC_PDAC_W_D1ACP(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D1ACP_SHIFT)) & XRDC_PDAC_W_D1ACP_MASK)
+#define XRDC_PDAC_W_D2ACP_MASK                   (0x1C0U)
+#define XRDC_PDAC_W_D2ACP_SHIFT                  (6U)
+#define XRDC_PDAC_W_D2ACP(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D2ACP_SHIFT)) & XRDC_PDAC_W_D2ACP_MASK)
+#define XRDC_PDAC_W_EAL_MASK                     (0x3000000U)
+#define XRDC_PDAC_W_EAL_SHIFT                    (24U)
+/*! EAL - Exclusive Access Lock
+ *  0b00..Lock disabled
+ *  0b01..Lock disabled until next reset
+ *  0b10..Lock enabled, lock state = available
+ *  0b11..Lock enabled, lock state = not available
+ */
+#define XRDC_PDAC_W_EAL(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_EAL_SHIFT)) & XRDC_PDAC_W_EAL_MASK)
+#define XRDC_PDAC_W_EALO_MASK                    (0xF000000U)
+#define XRDC_PDAC_W_EALO_SHIFT                   (24U)
+#define XRDC_PDAC_W_EALO(x)                      (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_EALO_SHIFT)) & XRDC_PDAC_W_EALO_MASK)
+#define XRDC_PDAC_W_LK2_MASK                     (0x60000000U)
+#define XRDC_PDAC_W_LK2_SHIFT                    (29U)
+/*! LK2 - Lock
+ *  0b00..Entire PDACs can be written.
+ *  0b01..Entire PDACs can be written.
+ *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
+ *  0b11..PDACs is locked (read-only) until the next reset.
+ */
+#define XRDC_PDAC_W_LK2(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_LK2_SHIFT)) & XRDC_PDAC_W_LK2_MASK)
+#define XRDC_PDAC_W_VLD_MASK                     (0x80000000U)
+#define XRDC_PDAC_W_VLD_SHIFT                    (31U)
+/*! VLD - Valid
+ *  0b0..The PDACs assignment is invalid.
+ *  0b1..The PDACs assignment is valid.
+ */
+#define XRDC_PDAC_W_VLD(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_VLD_SHIFT)) & XRDC_PDAC_W_VLD_MASK)
+/*! @} */
+
+/* The count of XRDC_PDAC_W */
+#define XRDC_PDAC_W_COUNT                        (289U)
+
+/* The count of XRDC_PDAC_W */
+#define XRDC_PDAC_W_COUNT2                       (2U)
+
+/*! @name MRGD_W - Memory Region Descriptor */
+/*! @{ */
+#define XRDC_MRGD_W_ACCSET1_MASK                 (0xFFFU)
+#define XRDC_MRGD_W_ACCSET1_SHIFT                (0U)
+#define XRDC_MRGD_W_ACCSET1(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_ACCSET1_SHIFT)) & XRDC_MRGD_W_ACCSET1_MASK)
+#define XRDC_MRGD_W_D0SEL_MASK                   (0x7U)
+#define XRDC_MRGD_W_D0SEL_SHIFT                  (0U)
+#define XRDC_MRGD_W_D0SEL(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D0SEL_SHIFT)) & XRDC_MRGD_W_D0SEL_MASK)
+#define XRDC_MRGD_W_D1SEL_MASK                   (0x38U)
+#define XRDC_MRGD_W_D1SEL_SHIFT                  (3U)
+#define XRDC_MRGD_W_D1SEL(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D1SEL_SHIFT)) & XRDC_MRGD_W_D1SEL_MASK)
+#define XRDC_MRGD_W_ENDADDR_MASK                 (0xFFFFFFE0U)
+#define XRDC_MRGD_W_ENDADDR_SHIFT                (5U)
+#define XRDC_MRGD_W_ENDADDR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_ENDADDR_SHIFT)) & XRDC_MRGD_W_ENDADDR_MASK)
+#define XRDC_MRGD_W_SRTADDR_MASK                 (0xFFFFFFE0U)
+#define XRDC_MRGD_W_SRTADDR_SHIFT                (5U)
+#define XRDC_MRGD_W_SRTADDR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_SRTADDR_SHIFT)) & XRDC_MRGD_W_SRTADDR_MASK)
+#define XRDC_MRGD_W_D2SEL_MASK                   (0x1C0U)
+#define XRDC_MRGD_W_D2SEL_SHIFT                  (6U)
+#define XRDC_MRGD_W_D2SEL(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D2SEL_SHIFT)) & XRDC_MRGD_W_D2SEL_MASK)
+#define XRDC_MRGD_W_LKAS1_MASK                   (0x1000U)
+#define XRDC_MRGD_W_LKAS1_SHIFT                  (12U)
+/*! LKAS1 - Lock ACCSET1
+ *  0b0..Writes to ACCSET1 affect lesser modes
+ *  0b1..ACCSET1 cannot be modified
+ */
+#define XRDC_MRGD_W_LKAS1(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_LKAS1_SHIFT)) & XRDC_MRGD_W_LKAS1_MASK)
+#define XRDC_MRGD_W_ACCSET2_MASK                 (0xFFF0000U)
+#define XRDC_MRGD_W_ACCSET2_SHIFT                (16U)
+#define XRDC_MRGD_W_ACCSET2(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_ACCSET2_SHIFT)) & XRDC_MRGD_W_ACCSET2_MASK)
+#define XRDC_MRGD_W_EAL_MASK                     (0x3000000U)
+#define XRDC_MRGD_W_EAL_SHIFT                    (24U)
+/*! EAL - Exclusive Access Lock
+ *  0b00..Lock disabled
+ *  0b01..Lock disabled until next reset
+ *  0b10..Lock enabled, lock state = available
+ *  0b11..Lock enabled, lock state = not available
+ */
+#define XRDC_MRGD_W_EAL(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_EAL_SHIFT)) & XRDC_MRGD_W_EAL_MASK)
+#define XRDC_MRGD_W_EALO_MASK                    (0xF000000U)
+#define XRDC_MRGD_W_EALO_SHIFT                   (24U)
+#define XRDC_MRGD_W_EALO(x)                      (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_EALO_SHIFT)) & XRDC_MRGD_W_EALO_MASK)
+#define XRDC_MRGD_W_LKAS2_MASK                   (0x10000000U)
+#define XRDC_MRGD_W_LKAS2_SHIFT                  (28U)
+/*! LKAS2 - Lock ACCSET2
+ *  0b0..Writes to ACCSET2 affect lesser modes
+ *  0b1..ACCSET2 cannot be modified
+ */
+#define XRDC_MRGD_W_LKAS2(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_LKAS2_SHIFT)) & XRDC_MRGD_W_LKAS2_MASK)
+#define XRDC_MRGD_W_LK2_MASK                     (0x60000000U)
+#define XRDC_MRGD_W_LK2_SHIFT                    (29U)
+/*! LK2 - Lock
+ *  0b00..Entire MRGDn can be written.
+ *  0b01..Entire MRGDn can be written.
+ *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
+ *  0b11..MRGDn is locked (read-only) until the next reset.
+ */
+#define XRDC_MRGD_W_LK2(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_LK2_SHIFT)) & XRDC_MRGD_W_LK2_MASK)
+#define XRDC_MRGD_W_CR_MASK                      (0x80000000U)
+#define XRDC_MRGD_W_CR_SHIFT                     (31U)
+#define XRDC_MRGD_W_CR(x)                        (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_CR_SHIFT)) & XRDC_MRGD_W_CR_MASK)
+#define XRDC_MRGD_W_VLD_MASK                     (0x80000000U)
+#define XRDC_MRGD_W_VLD_SHIFT                    (31U)
+/*! VLD - Valid
+ *  0b0..The MRGDn assignment is invalid.
+ *  0b1..The MRGDn assignment is valid.
+ */
+#define XRDC_MRGD_W_VLD(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_VLD_SHIFT)) & XRDC_MRGD_W_VLD_MASK)
+/*! @} */
+
+/* The count of XRDC_MRGD_W */
+#define XRDC_MRGD_W_COUNT                        (24U)
+
+/* The count of XRDC_MRGD_W */
+#define XRDC_MRGD_W_COUNT2                       (5U)
+
+
+/*!
+ * @}
+ */ /* end of group XRDC_Register_Masks */
+
+
+/* XRDC - Peripheral instance base addresses */
+/** Peripheral XRDC base address */
+#define XRDC_BASE                                (0x40014000u)
+/** Peripheral XRDC base pointer */
+#define XRDC                                     ((XRDC_Type *)XRDC_BASE)
+/** Array initializer of XRDC peripheral base addresses */
+#define XRDC_BASE_ADDRS                          { XRDC_BASE }
+/** Array initializer of XRDC peripheral base pointers */
+#define XRDC_BASE_PTRS                           { XRDC }
+
+/*!
+ * @}
+ */ /* end of group XRDC_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang system_header
+  #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDK Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
+ * @{
+ */
+
+#define EVENT_UNIT EVENT0
+#define INTMUX INTMUX0
+
+/*!
+ * @}
+ */ /* end of group SDK_Compatibility_Symbols */
+
+
+#endif  /* _RV32M1_RI5CY_H_ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/RV32M1_ri5cy_features.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/RV32M1_ri5cy_features.h
new file mode 100644
index 0000000..6e68f8a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/RV32M1_ri5cy_features.h
@@ -0,0 +1,1561 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.0, 2018-10-02
+**     Build:               b180815
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2018-10-02)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+#ifndef _RV32M1_ri5cy_FEATURES_H_
+#define _RV32M1_ri5cy_FEATURES_H_
+
+/* SOC module features */
+
+/* @brief AXBS availability on the SoC. */
+#define FSL_FEATURE_SOC_AXBS_COUNT (1)
+/* @brief CAU3 availability on the SoC. */
+#define FSL_FEATURE_SOC_CAU3_COUNT (1)
+/* @brief CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_CRC_COUNT (1)
+/* @brief DMAMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
+/* @brief EDMA availability on the SoC. */
+#define FSL_FEATURE_SOC_EDMA_COUNT (1)
+/* @brief EMVSIM availability on the SoC. */
+#define FSL_FEATURE_SOC_EMVSIM_COUNT (1)
+/* @brief EVENT availability on the SoC. */
+#define FSL_FEATURE_SOC_EVENT_COUNT (1)
+/* @brief EWM availability on the SoC. */
+#define FSL_FEATURE_SOC_EWM_COUNT (1)
+/* @brief FB availability on the SoC. */
+#define FSL_FEATURE_SOC_FB_COUNT (1)
+/* @brief FLASH availability on the SoC. */
+#define FSL_FEATURE_SOC_FLASH_COUNT (1)
+/* @brief FLEXIO availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXIO_COUNT (1)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (5)
+/* @brief I2S availability on the SoC. */
+#define FSL_FEATURE_SOC_I2S_COUNT (1)
+/* @brief INTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INTMUX_COUNT (1)
+/* @brief LLWU availability on the SoC. */
+#define FSL_FEATURE_SOC_LLWU_COUNT (2)
+/* @brief LPADC availability on the SoC. */
+#define FSL_FEATURE_SOC_LPADC_COUNT (1)
+/* @brief LPCMP availability on the SoC. */
+#define FSL_FEATURE_SOC_LPCMP_COUNT (2)
+/* @brief LPDAC availability on the SoC. */
+#define FSL_FEATURE_SOC_LPDAC_COUNT (1)
+/* @brief LPI2C availability on the SoC. */
+#define FSL_FEATURE_SOC_LPI2C_COUNT (4)
+/* @brief LPIT availability on the SoC. */
+#define FSL_FEATURE_SOC_LPIT_COUNT (2)
+/* @brief LPSPI availability on the SoC. */
+#define FSL_FEATURE_SOC_LPSPI_COUNT (4)
+/* @brief LPTMR availability on the SoC. */
+#define FSL_FEATURE_SOC_LPTMR_COUNT (3)
+/* @brief LPUART availability on the SoC. */
+#define FSL_FEATURE_SOC_LPUART_COUNT (4)
+/* @brief MCM availability on the SoC. */
+#define FSL_FEATURE_SOC_MCM_COUNT (1)
+/* @brief MSCM availability on the SoC. */
+#define FSL_FEATURE_SOC_MSCM_COUNT (1)
+/* @brief MU availability on the SoC. */
+#define FSL_FEATURE_SOC_MU_COUNT (1)
+/* @brief PCC availability on the SoC. */
+#define FSL_FEATURE_SOC_PCC_COUNT (2)
+/* @brief PORT availability on the SoC. */
+#define FSL_FEATURE_SOC_PORT_COUNT (5)
+/* @brief RSIM availability on the SoC. */
+#define FSL_FEATURE_SOC_RSIM_COUNT (1)
+/* @brief RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_RTC_COUNT (1)
+/* @brief SCG availability on the SoC. */
+#define FSL_FEATURE_SOC_SCG_COUNT (1)
+/* @brief SEMA42 availability on the SoC. */
+#define FSL_FEATURE_SOC_SEMA42_COUNT (2)
+/* @brief SIM availability on the SoC. */
+#define FSL_FEATURE_SOC_SIM_COUNT (1)
+/* @brief SMC availability on the SoC. */
+#define FSL_FEATURE_SOC_SMC_COUNT (2)
+/* @brief SPM availability on the SoC. */
+#define FSL_FEATURE_SOC_SPM_COUNT (1)
+/* @brief TPM availability on the SoC. */
+#define FSL_FEATURE_SOC_TPM_COUNT (4)
+/* @brief TRGMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_TRGMUX_COUNT (2)
+/* @brief TRNG availability on the SoC. */
+#define FSL_FEATURE_SOC_TRNG_COUNT (1)
+/* @brief TSTMR availability on the SoC. */
+#define FSL_FEATURE_SOC_TSTMR_COUNT (1)
+/* @brief USB availability on the SoC. */
+#define FSL_FEATURE_SOC_USB_COUNT (1)
+/* @brief USBVREG availability on the SoC. */
+#define FSL_FEATURE_SOC_USBVREG_COUNT (1)
+/* @brief USDHC availability on the SoC. */
+#define FSL_FEATURE_SOC_USDHC_COUNT (1)
+/* @brief VREF availability on the SoC. */
+#define FSL_FEATURE_SOC_VREF_COUNT (1)
+/* @brief WDOG availability on the SoC. */
+#define FSL_FEATURE_SOC_WDOG_COUNT (2)
+/* @brief XRDC availability on the SoC. */
+#define FSL_FEATURE_SOC_XRDC_COUNT (1)
+
+/* LPADC module features */
+
+/* @brief Has differential mode (bitfield CMDLn[DIFF]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0)
+/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0)
+/* @brief Has internal clock (bitfield CFG[ADCKEN]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (1)
+/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (1)
+/* @brief Has calibration (bitfield CFG[CALOFS]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (1)
+/* @brief Has offset trim (register OFSTRIM). */
+#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
+
+/* AXBS module features */
+
+/* No feature definitions */
+
+/* CRC module features */
+
+/* @brief Has data register with name CRC */
+#define FSL_FEATURE_CRC_HAS_CRC_REG (0)
+
+/* EDMA module features */
+
+/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (16)
+/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
+/* @brief Has DMA_Error interrupt vector. */
+#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0)
+/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16)
+
+/* DMAMUX module features */
+
+/* @brief Number of DMA channels (related to number of register CHCFGn). */
+#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 16)
+/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
+#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
+/* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */
+#define FSL_FEATURE_DMAMUX_HAS_A_ON (1)
+
+/* EWM module features */
+
+/* @brief Has clock select (register CLKCTRL). */
+#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT  (0)
+/* @brief Has clock prescaler (register CLKPRESCALER). */
+#define FSL_FEATURE_EWM_HAS_PRESCALER  (1)
+
+/* FB module features */
+
+/* No feature definitions */
+
+/* FLEXIO module features */
+
+/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
+#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
+/* @brief Has Pin Data Input Register (FLEXIO_PIN) */
+#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1)
+/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
+#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1)
+/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
+#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1)
+/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */
+#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1)
+/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */
+#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1)
+/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */
+#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1)
+/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */
+#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1)
+/* @brief Reset value of the FLEXIO_VERID register */
+#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001)
+/* @brief Reset value of the FLEXIO_PARAM register */
+#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200808)
+
+/* FLASH module features */
+
+/* @brief Current core ID. */
+#define FSL_FEATURE_FLASH_CURRENT_CORE_ID (0)
+/* @brief Is of type FTFA. */
+#define FSL_FEATURE_FLASH_IS_FTFA (0)
+/* @brief Is of type FTFE. */
+#define FSL_FEATURE_FLASH_IS_FTFE (1)
+/* @brief Is of type FTFL. */
+#define FSL_FEATURE_FLASH_IS_FTFL (0)
+/* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+#define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
+/* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+#define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
+/* @brief Has EEPROM region protection (register FEPROT). */
+#define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
+/* @brief Has data flash region protection (register FDPROT). */
+#define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
+/* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+#define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1)
+/* @brief Has flash cache control in FMC module. */
+#define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
+/* @brief Has flash cache control in MCM module. */
+#define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
+/* @brief Has flash cache control in MSCM module. */
+#define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (1)
+/* @brief Has prefetch speculation control in flash, such as kv5x. */
+#define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
+/* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for RV32M1. */
+#define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (1)
+/* @brief P-Flash start address. */
+#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+/* @brief P-Flash block count. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
+/* @brief P-Flash block size. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288)
+/* @brief P-Flash sector size. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096)
+/* @brief P-Flash write unit size. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
+/* @brief P-Flash data path width. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
+/* @brief P-Flash block swap feature. */
+#define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1)
+/* @brief P-Flash protection region count. */
+#define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (64)
+/* @brief Has multiple flash. */
+#define FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH (1)
+/* @brief Flash memory count. */
+#define FSL_FEATURE_FLASH_MEMORY_COUNT (2)
+/* @brief P-Flash start address. */
+#define FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS (0x01000000)
+/* @brief P-Flash block count. */
+#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT (1)
+/* @brief P-Flash block size. */
+#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE (262144)
+/* @brief P-Flash sector size. */
+#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE (2048)
+/* @brief P-Flash write unit size. */
+#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE (8)
+/* @brief P-Flash data path width. */
+#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_DATA_PATH_WIDTH (8)
+/* @brief P-Flash protection region count. */
+#define FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT (16)
+/* @brief P-Flash block swap feature. */
+#define FSL_FEATURE_FLASH_HAS_1_PFLASH_BLOCK_SWAP (0)
+/* @brief Has FlexNVM memory. */
+#define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
+/* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+#define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
+/* @brief FlexNVM block count. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
+/* @brief FlexNVM block size. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
+/* @brief FlexNVM sector size. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
+/* @brief FlexNVM write unit size. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
+/* @brief FlexNVM data path width. */
+#define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
+/* @brief Has FlexRAM memory. */
+#define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
+/* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+#define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x48000000)
+/* @brief FlexRAM size. */
+#define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
+/* @brief Has 0x00 Read 1s Block command. */
+#define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
+/* @brief Flash 1 has 0x00 Read 1s Block command. */
+#define FSL_FEATURE_FLASH_HAS_1_READ_1S_BLOCK_CMD (0)
+/* @brief Has 0x01 Read 1s Section command. */
+#define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+/* @brief Has 0x02 Program Check command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+/* @brief Has 0x03 Read Resource command. */
+#define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (0)
+/* @brief Has 0x06 Program Longword command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
+/* @brief Has 0x07 Program Phrase command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
+/* @brief Has 0x08 Erase Flash Block command. */
+#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
+/* @brief Flash 1 has 0x08 Erase Flash Block command. */
+#define FSL_FEATURE_FLASH_HAS_1_ERASE_FLASH_BLOCK_CMD (0)
+/* @brief Has 0x09 Erase Flash Sector command. */
+#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+/* @brief Has 0x0B Program Section command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
+/* @brief Has 0x0C Generate CRC signature for selected program flash sectors. */
+#define FSL_FEATURE_FLASH_HAS_GENERATE_CRC_CMD (1)
+/* @brief Has 0x40 Read 1s All Blocks command. */
+#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
+/* @brief Has 0x41 Read Once command. */
+#define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+/* @brief Has 0x43 Program Once command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+/* @brief Has 0x44 Erase All Blocks command. */
+#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
+/* @brief Has 0x45 Verify Backdoor Access Key command. */
+#define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+/* @brief Has 0x46 Swap Control command. */
+#define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1)
+/* @brief Flash 1 has 0x46 Swap Control command. */
+#define FSL_FEATURE_FLASH_HAS_1_SWAP_CONTROL_CMD (0)
+/* @brief Has 0x49 Erase All Blocks Unsecure command. */
+#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1)
+/* @brief Has 0x4A Read 1s All Execute-only Segments command. */
+#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
+/* @brief Has 0x4B Erase All Execute-only Segments command. */
+#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
+/* @brief Has 0x80 Program Partition command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
+/* @brief Has 0x81 Set FlexRAM Function command. */
+#define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
+/* @brief P-Flash Erase/Read 1st all block command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
+/* @brief P-Flash Erase sector command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16)
+/* @brief P-Flash Erase sector command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT (8)
+/* @brief P-Flash Program/Verify section command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16)
+/* @brief P-Flash Program/Verify section command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT (8)
+/* @brief P-Flash Read resource command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
+/* @brief P-Flash Program check command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+/* @brief P-Flash Program check command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16)
+/* @brief P-Flash 1 Program check command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_1_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
+/* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
+/* @brief FlexNVM Erase sector command address alignment. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
+/* @brief FlexNVM Rrogram/Verify section command address alignment. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
+/* @brief FlexNVM Read resource command address alignment. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
+/* @brief FlexNVM Program check command address alignment. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
+/* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
+/* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+/* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+/* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
+/* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
+/* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
+/* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
+/* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
+/* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
+/* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
+/* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
+/* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+/* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+/* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+/* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+/* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+/* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
+
+/* GPIO module features */
+
+/* @brief Has fast (single cycle) access capability via a dedicated memory region. */
+#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1)
+/* @brief Has port input disable register (PIDR). */
+#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1)
+
+/* SAI module features */
+
+/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
+#define FSL_FEATURE_SAI_FIFO_COUNT (8)
+/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
+#define FSL_FEATURE_SAI_CHANNEL_COUNT (2)
+/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
+#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
+/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1)
+/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1)
+/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1)
+/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
+#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1)
+/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
+#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
+/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
+#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0)
+/* @brief Interrupt source number */
+#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1)
+/* @brief Has register of MCR. */
+#define FSL_FEATURE_SAI_HAS_MCR (0)
+/* @brief Has bit field MICS of the MCR register. */
+#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1)
+/* @brief Has register of MDR */
+#define FSL_FEATURE_SAI_HAS_MDR (0)
+/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */
+#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0)
+
+/* INTMUX module features */
+
+/* @brief Number of INTMUX channels (related to number of register CHn_CSR). */
+#define FSL_FEATURE_INTMUX_CHANNEL_COUNT (8)
+/* @brief Number of INTMUX IRQ source. */
+#define FSL_FEATURE_INTMUX_IRQ_COUNT (32)
+/* @brief The start IRQ index of first INTMUX source IRQ. */
+#define FSL_FEATURE_INTMUX_IRQ_START_INDEX (32)
+/* @brief The direction of INTMUX. OUT, route the CM4 subsystem IRQ to System. */
+#define FSL_FEATURE_INTMUX_DIRECTION_OUT (0)
+/* @brief The total number of level1 interrupt vectors. */
+#define FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS (32)
+
+/* LLWU module features */
+
+/* @brief Maximum number of pins connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (32)
+/* @brief Maximum number of internal modules connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
+/* @brief Number of digital filters. */
+#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
+/* @brief Has MF register. */
+#define FSL_FEATURE_LLWU_HAS_MF (0)
+/* @brief Has PF register. */
+#define FSL_FEATURE_LLWU_HAS_PF (1)
+/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
+#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
+/* @brief Has no internal module wakeup flag register. */
+#define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (1)
+/* @brief Has external pin 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
+/* @brief Has external pin 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
+/* @brief Has external pin 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (22)
+/* @brief Has external pin 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (30)
+/* @brief Has external pin 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (1)
+/* @brief Has external pin 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (2)
+/* @brief Has external pin 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (4)
+/* @brief Has external pin 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (6)
+/* @brief Has external pin 8 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (7)
+/* @brief Has external pin 9 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (8)
+/* @brief Has external pin 10 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (16)
+/* @brief Has external pin 11 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (20)
+/* @brief Has external pin 12 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (22)
+/* @brief Has external pin 13 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (25)
+/* @brief Has external pin 14 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (28)
+/* @brief Has external pin 15 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7)
+/* @brief Has external pin 16 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (9)
+/* @brief Has external pin 17 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (11)
+/* @brief Has external pin 18 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (12)
+/* @brief Has external pin 19 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (8)
+/* @brief Has external pin 20 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (10)
+/* @brief Has external pin 21 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (1)
+/* @brief Has external pin 22 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (3)
+/* @brief Has external pin 23 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (8)
+/* @brief Has external pin 24 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (9)
+/* @brief Has external pin 25 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (10)
+/* @brief Has external pin 26 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (12)
+/* @brief Has external pin 27 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
+/* @brief Has external pin 28 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
+/* @brief Has external pin 29 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
+/* @brief Has external pin 30 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
+/* @brief Has external pin 31 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
+/* @brief Has internal module 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
+/* @brief Has internal module 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
+/* @brief Has internal module 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
+/* @brief Has internal module 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
+/* @brief Has internal module 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
+/* @brief Has internal module 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
+/* @brief Has internal module 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (1)
+/* @brief Has internal module 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
+/* @brief Has LLWU_VERID. */
+#define FSL_FEATURE_LLWU_HAS_VERID (1)
+/* @brief Has LLWU_PARAM. */
+#define FSL_FEATURE_LLWU_HAS_PARAM (1)
+/* @brief LLWU register bit width. */
+#define FSL_FEATURE_LLWU_REG_BITWIDTH (32)
+/* @brief Has DMA Enable register LLWU_DE. */
+#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (1)
+
+/* LPDAC module features */
+
+/* @brief FIFO size. */
+#define FSL_FEATURE_LPDAC_FIFO_SIZE (16)
+
+/* LPI2C module features */
+
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4)
+
+/* LPIT module features */
+
+/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
+#define FSL_FEATURE_LPIT_TIMER_COUNT (4)
+/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
+#define FSL_FEATURE_LPIT_HAS_LIFETIME_TIMER (0)
+/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
+#define FSL_FEATURE_LPIT_HAS_CHAIN_MODE (0)
+/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
+#define FSL_FEATURE_LPIT_HAS_SHARED_IRQ_HANDLER (0)
+
+/* LPSPI module features */
+
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+
+/* LPTMR module features */
+
+/* @brief Has shared interrupt handler with another LPTMR module. */
+#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
+/* @brief Whether LPTMR counter is 32 bits width. */
+#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1)
+/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
+#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1)
+
+/* LPUART module features */
+
+/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
+#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
+/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
+/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPUART_HAS_FIFO (1)
+/* @brief Has 32-bit register MODIR */
+#define FSL_FEATURE_LPUART_HAS_MODIR (1)
+/* @brief Hardware flow control (RTS, CTS) is supported. */
+#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
+/* @brief Infrared (modulation) is supported. */
+#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
+/* @brief 2 bits long stop bit is available. */
+#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
+/* @brief If 10-bit mode is supported. */
+#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
+/* @brief If 7-bit mode is supported. */
+#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1)
+/* @brief Baud rate fine adjustment is available. */
+#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
+/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
+/* @brief Peripheral type. */
+#define FSL_FEATURE_LPUART_IS_SCI (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8)
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
+/* @brief Maximal data width with parity bit. */
+#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
+/* @brief Supports two match addresses to filter incoming frames. */
+#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
+/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
+/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
+#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
+/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
+/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
+#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
+/* @brief Has improved smart card (ISO7816 protocol) support. */
+#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
+/* @brief Has local operation network (CEA709.1-B protocol) support. */
+#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
+/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
+#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
+/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
+#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
+/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
+#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+/* @brief Has separate RX and TX interrupts. */
+#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
+/* @brief Has LPAURT_PARAM. */
+#define FSL_FEATURE_LPUART_HAS_PARAM (1)
+/* @brief Has LPUART_VERID. */
+#define FSL_FEATURE_LPUART_HAS_VERID (1)
+/* @brief Has LPUART_GLOBAL. */
+#define FSL_FEATURE_LPUART_HAS_GLOBAL (1)
+/* @brief Has LPUART_PINCFG. */
+#define FSL_FEATURE_LPUART_HAS_PINCFG (1)
+
+/* MCM module features */
+
+/* @brief Has L1 cache. */
+#define FSL_FEATURE_HAS_L1CACHE (1)
+
+/* MSCM module features */
+
+/* @brief Number of configuration information for processors. */
+#define FSL_FEATURE_MSCM_HAS_CP_COUNT (2)
+/* @brief Has data cache. */
+#define FSL_FEATURE_MSCM_HAS_DATACACHE (0)
+
+/* MU module features */
+
+/* @brief MU side for current core */
+#define FSL_FEATURE_MU_SIDE_A (1)
+/* @brief MU Has register CCR */
+#define FSL_FEATURE_MU_HAS_CCR (1)
+/* @brief MU Has register SR[RS], BSR[ARS] */
+#define FSL_FEATURE_MU_HAS_SR_RS (0)
+/* @brief MU Has register CR[RDIE], CR[RAIE], SR[RDIP], SR[RAIP] */
+#define FSL_FEATURE_MU_HAS_RESET_INT (1)
+/* @brief MU Has register SR[MURIP] */
+#define FSL_FEATURE_MU_HAS_SR_MURIP (1)
+/* @brief brief MU Has register SR[HRIP] */
+#define FSL_FEATURE_MU_HAS_SR_HRIP (1)
+/* @brief brief MU does not support enable clock of the other core, CR[CLKE] or CCR[CLKE]. */
+#define FSL_FEATURE_MU_NO_CLKE (0)
+/* @brief brief MU does not support NMI, CR[NMI]. */
+#define FSL_FEATURE_MU_NO_NMI (0)
+/* @brief brief MU does not support hold the other core reset. CR[RSTH] or CCR[RSTH]. */
+#define FSL_FEATURE_MU_NO_RSTH (0)
+/* @brief brief MU does not supports MU reset, CR[MUR]. */
+#define FSL_FEATURE_MU_NO_MUR (0)
+/* @brief brief MU does not supports hardware reset, CR[HR] or CCR[HR]. */
+#define FSL_FEATURE_MU_NO_HR (0)
+/* @brief brief MU supports mask the hardware reset. CR[HRM] or CCR[HRM]. */
+#define FSL_FEATURE_MU_HAS_HRM (1)
+
+/* interrupt module features */
+
+/* @brief Lowest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
+/* @brief Highest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31)
+
+/* PCC module features */
+
+/* @brief Has CLOCK GATE CONTROL bit (e.g PCC_CGC) */
+#define FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL (1)
+
+/* PORT module features */
+
+/* @brief Has control lock (register bit PCR[LK]). */
+#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
+/* @brief Has open drain control (register bit PCR[ODE]). */
+#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
+/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
+#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
+/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */
+#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
+/* @brief Has pull resistor selection available. */
+#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
+/* @brief Has pull resistor enable (register bit PCR[PE]). */
+#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
+/* @brief Has slew rate control (register bit PCR[SRE]). */
+#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
+/* @brief Has passive filter (register bit field PCR[PFE]). */
+#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
+/* @brief Has drive strength control (register bit PCR[DSE]). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
+/* @brief Defines width of PCR[MUX] field. */
+#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
+/* @brief Has independent interrupt control(register ICR). */
+#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0)
+/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
+#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (1)
+/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (1)
+/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (1)
+
+/* RTC module features */
+
+/* @brief Has wakeup pin. */
+#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
+/* @brief Has wakeup pin selection (bit field CR[WPS]). */
+#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
+/* @brief Has low power features (registers MER, MCLR and MCHR). */
+#define FSL_FEATURE_RTC_HAS_MONOTONIC (1)
+/* @brief Has read/write access control (registers WAR and RAR). */
+#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
+/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+#define FSL_FEATURE_RTC_HAS_SECURITY (1)
+/* @brief Has RTC_CLKIN available. */
+#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
+/* @brief Has prescaler adjust for LPO. */
+#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1)
+/* @brief Has Clock Pin Enable field. */
+#define FSL_FEATURE_RTC_HAS_CPE (1)
+/* @brief Has Timer Seconds Interrupt Configuration field. */
+#define FSL_FEATURE_RTC_HAS_TSIC (1)
+/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
+#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
+/* @brief Has Tamper Interrupt Register (register TIR). */
+#define FSL_FEATURE_RTC_HAS_TIR (1)
+/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */
+#define FSL_FEATURE_RTC_HAS_TIR_TPIE (1)
+/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */
+#define FSL_FEATURE_RTC_HAS_TIR_SIE (1)
+/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */
+#define FSL_FEATURE_RTC_HAS_TIR_LCIE (1)
+/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */
+#define FSL_FEATURE_RTC_HAS_SR_TIDF (1)
+/* @brief Has Tamper Detect Register (register TDR). */
+#define FSL_FEATURE_RTC_HAS_TDR (1)
+/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */
+#define FSL_FEATURE_RTC_HAS_TDR_TPF (1)
+/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */
+#define FSL_FEATURE_RTC_HAS_TDR_STF (1)
+/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */
+#define FSL_FEATURE_RTC_HAS_TDR_LCTF (1)
+/* @brief Has Tamper Time Seconds Register (register TTSR). */
+#define FSL_FEATURE_RTC_HAS_TTSR (1)
+/* @brief Has Pin Configuration Register (register PCR). */
+#define FSL_FEATURE_RTC_HAS_PCR (1)
+/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */
+#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0)
+
+/* SCG module features */
+
+/* @brief Has platform clock divider SCG_CSR[DIVPLAT]. */
+#define FSL_FEATURE_SCG_HAS_DIVPLAT (0)
+/* @brief Has bus clock divider SCG_CSR[DIVBUS]. */
+#define FSL_FEATURE_SCG_HAS_DIVBUS (1)
+/* @brief Has external clock divide ratio SCG_CSR[DIVEXT]. */
+#define FSL_FEATURE_SCG_HAS_DIVEXT (1)
+/* @brief Has OSC capacitor setting SOSCCFG[SC2P ~ SC16P]. */
+#define FSL_FEATURE_SCG_HAS_OSC_SCXP (0)
+/* @brief Has SOSCCSR[SOSCERCLKEN]. */
+#define FSL_FEATURE_SCG_HAS_OSC_ERCLK (0)
+/* @brief Has OSC freq range SOSCCFG[RANGE]. */
+#define FSL_FEATURE_SCG_HAS_SOSC_RANGE (0)
+/* @brief Has CLKOUT configure register SCG_CLKOUTCNFG. */
+#define FSL_FEATURE_SCG_HAS_CLKOUTCNFG (1)
+/* @brief Has SCG_SOSCDIV[SOSCDIV3]. */
+#define FSL_FEATURE_SCG_HAS_SOSCDIV3 (1)
+/* @brief Has SCG_SIRCDIV[SIRCDIV3]. */
+#define FSL_FEATURE_SCG_HAS_SIRCDIV3 (1)
+/* @brief Has SCG_SIRCCSR[LPOPO]. */
+#define FSL_FEATURE_SCG_HAS_SIRC_LPOPO (0)
+/* @brief Has SCG_FIRCDIV[FIRCDIV3]. */
+#define FSL_FEATURE_SCG_HAS_FIRCDIV3 (1)
+/* @brief Has SCG_FIRCCSR[FIRCLPEN]. */
+#define FSL_FEATURE_SCG_HAS_FIRCLPEN (1)
+/* @brief Has SCG_FIRCCSR[FIRCREGOFF]. */
+#define FSL_FEATURE_SCG_HAS_FIRCREGOFF (1)
+/* @brief Has SCG_SPLLDIV[SPLLDIV3]. */
+#define FSL_FEATURE_SCG_HAS_SPLLDIV3 (0)
+/* @brief Has SCG_SPLLCFG[PLLPOSTDIV1]. */
+#define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV1 (0)
+/* @brief Has SCG_SPLLCFG[PLLPOSTDIV2]. */
+#define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV2 (0)
+/* @brief Has SCG_SPLLCFG[PLLS]. */
+#define FSL_FEATURE_SCG_HAS_SPLL_PLLS (0)
+/* @brief Has SCG_SPLLCFG[BYPASS]. */
+#define FSL_FEATURE_SCG_HAS_SPLL_BYPASS (0)
+/* @brief Has SCG_SPLLCFG[PFDSEL]. */
+#define FSL_FEATURE_SCG_HAS_SPLL_PFDSEL (0)
+/* @brief Has SCG_SPLLCSR[SPLLCM]. */
+#define FSL_FEATURE_SCG_HAS_SPLL_MONITOR (0)
+/* @brief Has SCG_LPFLLDIV[FLLDIV3]. */
+#define FSL_FEATURE_SCG_HAS_FLLDIV3 (1)
+/* @brief Has low power FLL, SCG_LPFLLCSR. */
+#define FSL_FEATURE_SCG_HAS_LPFLL (1)
+/* @brief Has system PLL, SCG_SPLLCSR. */
+#define FSL_FEATURE_SCG_HAS_SPLL (0)
+/* @brief Has system PLL PFD, SCG_SPLLPFD. */
+#define FSL_FEATURE_SCG_HAS_SPLLPFD (0)
+/* @brief Has auxiliary PLL, SCG_APLLCSR. */
+#define FSL_FEATURE_SCG_HAS_APLL (0)
+/* @brief Has RTC OSC control, SCG_ROSCCSR. */
+#define FSL_FEATURE_SCG_HAS_ROSC (1)
+/* @brief Has RTC OSC clock source. */
+#define FSL_FEATURE_SCG_HAS_ROSC_SYS_CLK_SRC (1)
+/* @brief Has RTC OSC clock out select. */
+#define FSL_FEATURE_SCG_HAS_ROSC_CLKOUT (1)
+/* @brief Has EXTERNAL clock out select. */
+#define FSL_FEATURE_SCG_HAS_EXT_CLKOUT (1)
+/* @brief Has no System OSC configuration register, SCG_SOSCCFG. */
+#define FSL_FEATURE_SCG_HAS_NO_SOSCCFG (1)
+/* @brief Has no SCG_SOSCCSR[SOSCEN]. */
+#define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCEN (0)
+/* @brief Has no SCG_SOSCCSR[SOSCSTEN]. */
+#define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCSTEN (0)
+/* @brief Has no SCG_SOSCCSR[SOSCLPEN]. */
+#define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCLPEN (0)
+/* @brief Has no FIRC trim configuration register, SCG_FIRCTCFG. */
+#define FSL_FEATURE_SCG_HAS_NO_FIRCTCFG (0)
+/* @brief Has FIRC trim source USB0 Start of Frame. */
+#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB0 (0)
+/* @brief Has FIRC trim source USB1 Start of Frame. */
+#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB1 (0)
+/* @brief Has FIRC trim source system OSC. */
+#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_SOSC (1)
+/* @brief Has FIRC trim source RTC OSC. */
+#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_RTCOSC (1)
+
+/* SEMA42 module features */
+
+/* @brief Gate counts */
+#define FSL_FEATURE_SEMA42_GATE_COUNT (16)
+
+/* SIM module features */
+
+/* @brief Has USB FS divider. */
+#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
+#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
+/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0)
+/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
+/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (0)
+/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (0)
+/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0)
+/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
+/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
+/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
+/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
+/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
+/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
+/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
+#define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
+/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
+#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
+/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
+#define FSL_FEATURE_SIM_OPT_UART_COUNT (0)
+/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
+/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
+/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
+/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
+/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
+/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
+/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
+/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
+/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
+/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
+/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0)
+/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0)
+/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0)
+/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0)
+/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0)
+/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0)
+/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0)
+/* @brief Has FTM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
+/* @brief Number of FTM modules. */
+#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
+/* @brief Number of FTM triggers with selectable source. */
+#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
+/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
+/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
+/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
+/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
+/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
+/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
+/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
+/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
+/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
+/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
+/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
+/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
+/* @brief Has TPM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
+/* @brief The highest TPM module index. */
+#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
+/* @brief Has TPM module with index 0. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
+/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
+/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
+/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
+/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
+/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
+/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
+/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
+/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0)
+/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0)
+/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
+/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
+/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
+/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
+/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
+/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
+/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0)
+/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
+/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
+/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
+/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
+/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
+/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
+/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
+/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
+/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
+/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_ADC_COUNT (0)
+/* @brief ADC module has alternate trigger (register bit SOPT7[ADC0ALTTRGEN]). */
+#define FSL_FEATURE_SIM_OPT_ADC_HAS_ALTERNATE_TRIGGER (0)
+/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (0)
+/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0)
+/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
+/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
+/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
+/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
+/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
+/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
+/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
+/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
+/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0)
+/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
+/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (0)
+/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (0)
+/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
+/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
+/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
+/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
+/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
+/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
+/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
+/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
+/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
+/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
+/* @brief Has device die ID (register bit field SDID[DIEID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
+/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
+/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
+/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
+/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
+/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
+/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
+/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
+/* @brief Has flash for core0(CM4) (register bit field FCFG1[CORE0_PFSIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_CORE0_PFSIZE (1)
+/* @brief Has flash for core1(CM0) (register bit field FCFG1[CORE1_PFSIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_CORE1_PFSIZE (1)
+/* @brief Has sram for core0(CM4) (register bit field FCFG1[CORE0_SRAMSIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_CORE0_SRAMSIZE (1)
+/* @brief Has sram for core1(CM0) (register bit field FCFG1[CORE1_SRAMSIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_CORE1_SRAMSIZE (1)
+/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (0)
+/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0)
+/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (1)
+/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
+/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
+/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
+/* @brief Has miscellanious control register (register MCR). */
+#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
+/* @brief Has COP watchdog (registers COPC and SRVCOP). */
+#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
+/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
+#define FSL_FEATURE_SIM_HAS_COP_STOP (0)
+/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
+#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
+/* @brief Has MISCCTRL reg. */
+#define FSL_FEATURE_SIM_HAS_MISCCTRL (0)
+/* @brief Has LTCEN bit (e.g SIM_MISCCTRL). */
+#define FSL_FEATURE_SIM_HAS_MISCCTRL_LTCEN (0)
+/* @brief Has DMAINTSEL0 bit (e.g SIM_MISCCTRL). */
+#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL0 (0)
+/* @brief Has DMAINTSEL1 bit (e.g SIM_MISCCTRL). */
+#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL1 (0)
+/* @brief Has DMAINTSEL2 bit (e.g SIM_MISCCTRL). */
+#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL2 (0)
+/* @brief Has DMAINTSEL3 bit (e.g SIM_MISCCTRL). */
+#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL3 (0)
+/* @brief Has SECKEY0 reg. */
+#define FSL_FEATURE_SIM_HAS_SECKEY0 (0)
+/* @brief Has SECKEY bit (e.g SIM_SECKEY0). */
+#define FSL_FEATURE_SIM_HAS_SECKEY0_SECKEY (0)
+/* @brief Has SECKEY1 reg. */
+#define FSL_FEATURE_SIM_HAS_SECKEY1 (0)
+/* @brief Has SECKEY bit (e.g SIM_SECKEY1). */
+#define FSL_FEATURE_SIM_HAS_SECKEY1_SECKEY (0)
+/* @brief Has SECKEY2 reg. */
+#define FSL_FEATURE_SIM_HAS_SECKEY2 (0)
+/* @brief Has SECKEY bit (e.g SIM_SECKEY2). */
+#define FSL_FEATURE_SIM_HAS_SECKEY2_SECKEY (0)
+/* @brief Has SECKEY3 reg. */
+#define FSL_FEATURE_SIM_HAS_SECKEY3 (0)
+/* @brief Has SECKEY bit (e.g SIM_SECKEY3). */
+#define FSL_FEATURE_SIM_HAS_SECKEY3_SECKEY (0)
+/* @brief Has no SDID reg. */
+#define FSL_FEATURE_SIM_HAS_NO_SDID (0)
+/* @brief Has no UID reg. */
+#define FSL_FEATURE_SIM_HAS_NO_UID (0)
+/* @brief Has RFADDRL and RFADDRH registers. */
+#define FSL_FEATURE_SIM_HAS_RF_MAC_ADDR (1)
+/* @brief Has SYSTICK_CLK_EN bit in SIM_MISC2 register. */
+#define FSL_FEATURE_SIM_MISC2_HAS_SYSTICK_CLK_EN (1)
+/* @brief Has UIDM registers. */
+#define FSL_FEATURE_SIM_HAS_UIDM (1)
+
+/* SMC module features */
+
+/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
+#define FSL_FEATURE_SMC_HAS_PSTOPO (0)
+/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
+#define FSL_FEATURE_SMC_HAS_LPOPO (0)
+/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
+#define FSL_FEATURE_SMC_HAS_PORPO (0)
+/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
+#define FSL_FEATURE_SMC_HAS_LPWUI (0)
+/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
+#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
+/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
+#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
+/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
+/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
+/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
+#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1)
+/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
+#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
+/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
+#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
+/* @brief Has stop submode. */
+#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
+/* @brief Has stop submode 0(VLLS0). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
+/* @brief Has stop submode 2(VLLS2). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
+/* @brief Has SMC_PARAM. */
+#define FSL_FEATURE_SMC_HAS_PARAM (1)
+/* @brief Has SMC_VERID. */
+#define FSL_FEATURE_SMC_HAS_VERID (1)
+/* @brief Has SMC_CSRE. */
+#define FSL_FEATURE_SMC_HAS_CSRE (0)
+/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */
+#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (0)
+/* @brief Has tamper reset (register bit SRS[TAMPER]). */
+#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0)
+/* @brief Has security violation reset (register bit SRS[SECVIO]). */
+#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0)
+/* @brief Has security violation reset (register bit SRS[VBAT]). */
+#define FSL_FEATURE_SMC_HAS_SRS_VBAT (0)
+/* @brief Has security violation reset (register bit SRS[CORE0]). */
+#define FSL_FEATURE_SMC_HAS_SRS_CORE0 (1)
+/* @brief Has security violation reset (register bit SRS[CORE1]). */
+#define FSL_FEATURE_SMC_HAS_SRS_CORE1 (1)
+/* @brief Has security violation reset (register bit SRIE[VBAT]). */
+#define FSL_FEATURE_SMC_HAS_SRIE_VBAT (0)
+/* @brief Has security violation reset (register bit SRIE[CORE0]). */
+#define FSL_FEATURE_SMC_HAS_SRIE_CORE0 (1)
+/* @brief Has security violation reset (register bit SRIE[CORE1]). */
+#define FSL_FEATURE_SMC_HAS_SRIE_CORE1 (1)
+
+/* SysTick module features */
+
+/* @brief Systick has external reference clock. */
+#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1)
+/* @brief Systick external reference clock is core clock divided by this value. */
+#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16)
+
+/* TPM module features */
+
+/* @brief Number of channels. */
+#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \
+    ((x) == TPM0 ? (6) : \
+    ((x) == TPM1 ? (2) : \
+    ((x) == TPM2 ? (6) : \
+    ((x) == TPM3 ? (2) : (-1)))))
+/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
+#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
+/* @brief Has TPM_PARAM. */
+#define FSL_FEATURE_TPM_HAS_PARAM (1)
+/* @brief Has TPM_VERID. */
+#define FSL_FEATURE_TPM_HAS_VERID (1)
+/* @brief Has TPM_GLOBAL. */
+#define FSL_FEATURE_TPM_HAS_GLOBAL (1)
+/* @brief Has TPM_TRIG. */
+#define FSL_FEATURE_TPM_HAS_TRIG (1)
+/* @brief Has counter pause on trigger. */
+#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
+/* @brief Has external trigger selection. */
+#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1)
+/* @brief Has TPM_COMBINE register. */
+#define FSL_FEATURE_TPM_HAS_COMBINE (1)
+/* @brief Whether COMBINE register has effect. */
+#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1)
+/* @brief Has TPM_POL. */
+#define FSL_FEATURE_TPM_HAS_POL (1)
+/* @brief Has TPM_FILTER register. */
+#define FSL_FEATURE_TPM_HAS_FILTER (1)
+/* @brief Whether FILTER register has effect. */
+#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1)
+/* @brief Has TPM_QDCTRL register. */
+#define FSL_FEATURE_TPM_HAS_QDCTRL (1)
+/* @brief Whether QDCTRL register has effect. */
+#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1)
+
+/* TRGMUX module features */
+
+/* No feature definitions */
+
+/* TRNG module features */
+
+/* No feature definitions */
+
+/* TSTMR module features */
+
+/* @brief TSTMR clock frequency is 1MHZ. */
+#define FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_1MHZ (1)
+
+/* USB module features */
+
+/* @brief KHCI module instance count */
+#define FSL_FEATURE_USB_KHCI_COUNT (1)
+/* @brief HOST mode enabled */
+#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (0)
+/* @brief OTG mode enabled */
+#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (0)
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USB_KHCI_USB_RAM (2048)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS (1208025088)
+/* @brief Has KEEP_ALIVE_CTRL register */
+#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (1)
+/* @brief Mode control of the USB Keep Alive */
+#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_MODE_CONTROL (USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK)
+/* @brief Has the Dynamic SOF threshold compare support */
+#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1)
+/* @brief Has the VBUS detect support */
+#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (1)
+/* @brief Has the IRC48M module clock support */
+#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
+/* @brief Number of endpoints supported */
+#define FSL_FEATURE_USB_ENDPT_COUNT (16)
+/* @brief Has STALL_IL/OL_DIS registers */
+#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (1)
+/* @brief Has STALL_IH/OH_DIS registers */
+#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (1)
+
+/* USDHC module features */
+
+/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */
+#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0)
+/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */
+#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0)
+/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */
+#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (0)
+/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */
+#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (0)
+
+/* VREF module features */
+
+/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
+#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
+/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
+#define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
+/* @brief If high/low buffer mode supported */
+#define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
+/* @brief Module has also low reference (registers VREFL/VREFH) */
+#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
+/* @brief Has VREF_TRM4. */
+#define FSL_FEATURE_VREF_HAS_TRM4 (1)
+
+/* WDOG module features */
+
+/* @brief Watchdog is available. */
+#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
+/* @brief WDOG_CNT can be 32-bit written. */
+#define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1)
+
+/* XRDC module features */
+
+/* @brief Does not have global valid (register bit CR[GVLD]). */
+#define FSL_FEATURE_XRDC_HAS_NO_CR_GVLD (1)
+/* @brief Has domain ID of faulted access (register bit FDID[FDID]). */
+#define FSL_FEATURE_XRDC_HAS_FDID (1)
+/* @brief Has special 4-state model option (register bit PID[SP4SM]). */
+#define FSL_FEATURE_XRDC_PID_SP4SM (1)
+/* @brief Does not have logical partition identifier (register bit MDA_W[LPID]). */
+#define FSL_FEATURE_XRDC_NO_MDA_LPID (1)
+/* @brief Does not have logical partition enable option (register bit MDA_W[LPE]). */
+#define FSL_FEATURE_XRDC_NO_MDA_LPE (1)
+/* @brief Does not have peripheral semaphore enable option (register bit PDAC_W0[SE]). */
+#define FSL_FEATURE_XRDC_NO_PDAC_SE (1)
+/* @brief Does not have peripheral semaphore number (register bit PDAC_W0[SNUM]). */
+#define FSL_FEATURE_XRDC_NO_PDAC_SNUM (1)
+/* @brief Has peripheral excessive access lock owner (register bit PDAC_W0[EALO]). */
+#define FSL_FEATURE_XRDC_HAS_PDAC_EALO (1)
+/* @brief Has peripheral excessive access lock option (register bit PDAC_W1[EAL]). */
+#define FSL_FEATURE_XRDC_HAS_PDAC_EAL (1)
+/* @brief Has memory region end address (register bit MRGD_W1[ENDADDR]). */
+#define FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR (1)
+/* @brief Does not have memory region semaphore enable option (register bit MRGD_W2[SE]). */
+#define FSL_FEATURE_XRDC_NO_MRGD_SE (1)
+/* @brief Does not have memory region semaphore number (register bit MRGD_W2[SNUM]). */
+#define FSL_FEATURE_XRDC_NO_MRGD_SNUM (1)
+/* @brief Does not domain x access control policy option (register bit MRGD_W2[DxACP]). */
+#define FSL_FEATURE_XRDC_NO_MRGD_DXACP (1)
+/* @brief Does not have region size configuration (register bit MRGD_W2[SZ]). */
+#define FSL_FEATURE_XRDC_NO_MRGD_SZ (1)
+/* @brief Does not have subregion disable option (register bit MRGD_W2[SRD]). */
+#define FSL_FEATURE_XRDC_NO_MRGD_SRD (1)
+/* @brief Has memory region excessive access lock owner (register bit MRGD_W2[EALO]). */
+#define FSL_FEATURE_XRDC_HAS_MRGD_EALO (1)
+/* @brief Has domain x access policy select option (register bit MRGD_W2[DxSEL]). */
+#define FSL_FEATURE_XRDC_HAS_MRGD_DXSEL (1)
+/* @brief Has memory region excessive access lock option (register bit MRGD_W3[EAL]). */
+#define FSL_FEATURE_XRDC_HAS_MRGD_EAL (1)
+/* @brief Does not have lock option in MRGD_W3 register (register bit MRGD_W3[LK2]). */
+#define FSL_FEATURE_XRDC_NO_MRGD_W3_LK2 (1)
+/* @brief Does not have valid option in MRGD_W3 register (register bit MRGD_W3[VLD]). */
+#define FSL_FEATURE_XRDC_NO_MRGD_W3_VLD (1)
+/* @brief Has code region indicator select option (register bit MRGD_W3[CR]). */
+#define FSL_FEATURE_XRDC_HAS_MRGD_CR (1)
+/* @brief Has ASSSET lock option (register bit MRGD_W4[LKAS1]/[LKAS2]). */
+#define FSL_FEATURE_XRDC_HAS_MRGD_LKAS (1)
+/* @brief Has programmable access flags (register bit MRGD_W4[ACCSET1]/[ACCSET2]). */
+#define FSL_FEATURE_XRDC_HAS_MRGD_ACCSET (1)
+/* @brief Has lock option in MRGD_W4 register (register bit MRGD_W4[LK2]). */
+#define FSL_FEATURE_XRDC_HAS_MRGD_W4_LK2 (1)
+/* @brief Has valid option in MRGD_W4 register (register bit MRGD_W4[VLD]). */
+#define FSL_FEATURE_XRDC_HAS_MRGD_W4_VLD (1)
+/* @brief XRDC domain number (reset value of HWCFG0[NDID] plus 1). */
+#define FSL_FEATURE_XRDC_DOMAIN_COUNT (3)
+
+#endif /* _RV32M1_ri5cy_FEATURES_H_ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/RV32M1_zero_riscy.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/RV32M1_zero_riscy.h
new file mode 100644
index 0000000..55b369a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/RV32M1_zero_riscy.h
@@ -0,0 +1,32675 @@
+/*
+** ###################################################################
+**     Processors:          RV32M1_zero_riscy
+**                          RV32M1_zero_riscy
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
+**     Version:             rev. 1.0, 2018-10-02
+**     Build:               b180926
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for RV32M1_zero_riscy
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2018-10-02)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file RV32M1_zero_riscy.h
+ * @version 1.0
+ * @date 2018-10-02
+ * @brief CMSIS Peripheral Access Layer for RV32M1_zero_riscy
+ *
+ * CMSIS Peripheral Access Layer for RV32M1_zero_riscy
+ */
+
+#ifndef _RV32M1_CM0PLUS_H_
+#define _RV32M1_CM0PLUS_H_                  /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
+
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 80                 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Device specific interrupts */
+  CTI1_IRQn                    = 0,                /**< Cross Trigger Interface 1 */
+  DMA1_04_IRQn                 = 1,                /**< DMA1 channel 0/4 transfer complete */
+  DMA1_15_IRQn                 = 2,                /**< DMA1 channel 1/5 transfer complete */
+  DMA1_26_IRQn                 = 3,                /**< DMA1 channel 2/6 transfer complete */
+  DMA1_37_IRQn                 = 4,                /**< DMA1 channel 3/7 transfer complete */
+  DMA1_Error_IRQn              = 5,                /**< DMA1 channel 0-7 error interrupt */
+  CMC1_IRQn                    = 6,                /**< Core Mode Controller 1 */
+  LLWU1_IRQn                   = 7,                /**< Low leakage wakeup 1 */
+  MUB_IRQn                     = 8,                /**< MU Side B interrupt */
+  WDOG1_IRQn                   = 9,                /**< WDOG1 interrupt */
+  CAU3_Task_Complete_IRQn      = 10,               /**< Cryptographic Acceleration Unit version 3 Task Complete */
+  CAU3_Security_Violation_IRQn = 11,               /**< Cryptographic Acceleration Unit version 3 Security Violation */
+  TRNG_IRQn                    = 12,               /**< TRNG interrupt */
+  LPIT1_IRQn                   = 13,               /**< LPIT1 interrupt */
+  LPTMR2_IRQn                  = 14,               /**< LPTMR2 interrupt */
+  TPM3_IRQn                    = 15,               /**< TPM3 single interrupt vector for all sources */
+  LPI2C3_IRQn                  = 16,               /**< LPI2C3 interrupt */
+  RF0_0_IRQn                   = 17,               /**< RF0 interrupt 0 */
+  RF0_1_IRQn                   = 18,               /**< RF0 interrupt 1 */
+  LPSPI3_IRQn                  = 19,               /**< LPSPI3 single interrupt vector for all sources */
+  LPUART3_IRQn                 = 20,               /**< LPUART3 status and error */
+  PORTE_IRQn                   = 21,               /**< PORTE Pin detect */
+  LPCMP1_IRQn                  = 22,               /**< LPCMP1 interrupt */
+  RTC_IRQn                     = 23,               /**< RTC */
+  INTMUX1_0_IRQn               = 24,               /**< INTMUX1 channel0 interrupt */
+  INTMUX1_1_IRQn               = 25,               /**< INTMUX1 channel1 interrupt */
+  INTMUX1_2_IRQn               = 26,               /**< INTMUX1 channel2 interrupt */
+  INTMUX1_3_IRQn               = 27,               /**< INTMUX1 channel3 interrupt */
+  INTMUX1_4_IRQn               = 28,               /**< INTMUX1 channel4 interrupt */
+  INTMUX1_5_IRQn               = 29,               /**< INTMUX1 channel5 interrupt */
+  INTMUX1_6_IRQn               = 30,               /**< INTMUX1 channel6 interrupt */
+  INTMUX1_7_IRQn               = 31,               /**< INTMUX1 channel7 interrupt */
+  EWM_IRQn                     = 32,               /**< EWM interrupt  (INTMUX1 source IRQ0) */
+  FTFE_Command_Complete_IRQn   = 33,               /**< FTFE interrupt  (INTMUX1 source IRQ1) */
+  FTFE_Read_Collision_IRQn     = 34,               /**< FTFE interrupt  (INTMUX1 source IRQ2) */
+  SPM_IRQn                     = 35,               /**< SPM (INTMUX1 source IRQ3) */
+  SCG_IRQn                     = 36,               /**< SCG interrupt (INTMUX1 source IRQ4) */
+  LPIT0_IRQn                   = 37,               /**< LPIT0 interrupt (INTMUX1 source IRQ5) */
+  LPTMR0_IRQn                  = 38,               /**< LPTMR0 interrupt (INTMUX1 source IRQ6) */
+  LPTMR1_IRQn                  = 39,               /**< LPTMR1 interrupt (INTMUX1 source IRQ7) */
+  TPM0_IRQn                    = 40,               /**< TPM0 single interrupt vector for all sources (INTMUX1 source IRQ8) */
+  TPM1_IRQn                    = 41,               /**< TPM1 single interrupt vector for all sources (INTMUX1 source IRQ9) */
+  TPM2_IRQn                    = 42,               /**< TPM2 single interrupt vector for all sources (INTMUX1 source IRQ10) */
+  EMVSIM0_IRQn                 = 43,               /**< EMVSIM0 interrupt (INTMUX1 source IRQ11) */
+  FLEXIO0_IRQn                 = 44,               /**< FLEXIO0 (INTMUX1 source IRQ12) */
+  LPI2C0_IRQn                  = 45,               /**< LPI2C0 interrupt (INTMUX1 source IRQ13) */
+  LPI2C1_IRQn                  = 46,               /**< LPI2C1 interrupt (INTMUX1 source IRQ14) */
+  LPI2C2_IRQn                  = 47,               /**< LPI2C2 interrupt (INTMUX1 source IRQ15) */
+  I2S0_IRQn                    = 48,               /**< I2S0 interrupt (INTMUX1 source IRQ16) */
+  USDHC0_IRQn                  = 49,               /**< SDHC0 interrupt (INTMUX1 source IRQ17) */
+  LPSPI0_IRQn                  = 50,               /**< LPSPI0 single interrupt vector for all sources (INTMUX1 source IRQ18) */
+  LPSPI1_IRQn                  = 51,               /**< LPSPI1 single interrupt vector for all sources (INTMUX1 source IRQ19) */
+  LPSPI2_IRQn                  = 52,               /**< LPSPI2 single interrupt vector for all sources (INTMUX1 source IRQ20) */
+  LPUART0_IRQn                 = 53,               /**< LPUART0 status and error (INTMUX1 source IRQ21) */
+  LPUART1_IRQn                 = 54,               /**< LPUART1 status and error (INTMUX1 source IRQ22) */
+  LPUART2_IRQn                 = 55,               /**< LPUART2 status and error (INTMUX1 source IRQ23) */
+  USB0_IRQn                    = 56,               /**< USB0 interrupt (INTMUX1 source IRQ24) */
+  PORTA_IRQn                   = 57,               /**< PORTA Pin detect (INTMUX1 source IRQ25) */
+  PORTB_IRQn                   = 58,               /**< PORTB Pin detect (INTMUX1 source IRQ26) */
+  PORTC_IRQn                   = 59,               /**< PORTC Pin detect (INTMUX1 source IRQ27) */
+  PORTD_IRQn                   = 60,               /**< PORTD Pin detect (INTMUX1 source IRQ28) */
+  ADC0_IRQn                    = 61,               /**< LPADC0 interrupt (INTMUX1 source IRQ29) */
+  LPCMP0_IRQn                  = 62,               /**< LPCMP0 interrupt (INTMUX1 source IRQ30) */
+  LPDAC0_IRQn                  = 63                /**< DAC0 interrupt (INTMUX1 source IRQ31) */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M0 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
+ * @{
+ */
+
+#define __CM0PLUS_REV                  0x0000    /**< Core revision r0p0 */
+#define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
+#define __VTOR_PRESENT                 1         /**< Defines if VTOR is present or not */
+#define __NVIC_PRIO_BITS               2         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_riscv32.h"              /* Core Peripheral Access Layer */
+#include "system_RV32M1_zero_riscy.h" /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup edma_request
+ * @{ */
+
+/*******************************************************************************
+ * Definitions
+*******************************************************************************/
+
+/*!
+ * @brief Enumeration for the DMA hardware request
+ *
+ * Defines the enumeration for the DMA hardware request collections.
+ */
+typedef enum _dma_request_source
+{
+    kDmaRequestMux1LLWU1            = 0|0x200U,    /**< LLWU1 Wakeup */
+    kDmaRequestMux1CAEv3            = 1|0x200U,    /**< CAEv3 Data Request */
+    kDmaRequestMux1LPTMR2           = 2|0x200U,    /**< LPTMR2 Trigger */
+    kDmaRequestMux1TPM3Channel0     = 3|0x200U,    /**< TPM3 Channel 0 */
+    kDmaRequestMux1TPM3Channel1     = 4|0x200U,    /**< TPM3 Channel 1 */
+    kDmaRequestMux1TPM3Overflow     = 5|0x200U,    /**< TPM3 Overflow */
+    kDmaRequestMux1LPI2C3Rx         = 6|0x200U,    /**< LPI2C3 Receive */
+    kDmaRequestMux1LPI2C3Tx         = 7|0x200U,    /**< LPI2C3 Transmit */
+    kDmaRequestMux1RF0Rx            = 8|0x200U,    /**< 2.4GHz Radio 0 Receive */
+    kDmaRequestMux1LPSPI3Rx         = 9|0x200U,    /**< LPSPI3 Receive */
+    kDmaRequestMux1LPSPI3Tx         = 10|0x200U,   /**< LPSPI3 Transmit */
+    kDmaRequestMux1LPUART3Rx        = 11|0x200U,   /**< LPUART3 Receive */
+    kDmaRequestMux1LPUART3Tx        = 12|0x200U,   /**< LPUART3 Transmit */
+    kDmaRequestMux1PORTE            = 13|0x200U,   /**< PORTE Pin Request */
+    kDmaRequestMux1LPCMP1           = 14|0x200U,   /**< LPCMP1 Comparator Trigger */
+    kDmaRequestMux1LPTMR1           = 15|0x200U,   /**< LPTMR1 Trigger */
+    kDmaRequestMux1FLEXIO0Channel0  = 16|0x200U,   /**< FLEXIO0 Channel 0 */
+    kDmaRequestMux1FLEXIO0Channel1  = 17|0x200U,   /**< FLEXIO0 Channel 1 */
+    kDmaRequestMux1FLEXIO0Channel2  = 18|0x200U,   /**< FLEXIO0 Channel 2 */
+    kDmaRequestMux1FLEXIO0Channel3  = 19|0x200U,   /**< FLEXIO0 Channel 3 */
+    kDmaRequestMux1FLEXIO0Channel4  = 20|0x200U,   /**< FLEXIO0 Channel 4 */
+    kDmaRequestMux1FLEXIO0Channel5  = 21|0x200U,   /**< FLEXIO0 Channel 5 */
+    kDmaRequestMux1FLEXIO0Channel6  = 22|0x200U,   /**< FLEXIO0 Channel 6 */
+    kDmaRequestMux1FLEXIO0Channel7  = 23|0x200U,   /**< FLEXIO0 Channel 7 */
+    kDmaRequestMux1I2S0Rx           = 24|0x200U,   /**< I2S0 Receive */
+    kDmaRequestMux1I2S0Tx           = 25|0x200U,   /**< I2S0 Transmit */
+    kDmaRequestMux1PORTA            = 26|0x200U,   /**< PORTA Pin Request */
+    kDmaRequestMux1PORTB            = 27|0x200U,   /**< PORTB Pin Request */
+    kDmaRequestMux1PORTC            = 28|0x200U,   /**< PORTC Pin Request */
+    kDmaRequestMux1PORTD            = 29|0x200U,   /**< PORTD Pin Request */
+    kDmaRequestMux1LPADC0           = 30|0x200U,   /**< LPADC0 Conversion Complete */
+    kDmaRequestMux1DAC0             = 31|0x200U,   /**< DAC0 Conversion Complete */
+} dma_request_source_t;
+
+/* @} */
+
+/*!
+ * @addtogroup trgmux_source
+ * @{ */
+
+/*******************************************************************************
+ * Definitions
+*******************************************************************************/
+
+/*!
+ * @brief Enumeration for the TRGMUX source
+ *
+ * Defines the enumeration for the TRGMUX source collections.
+ */
+typedef enum _trgmux_source
+{
+    kTRGMUX_Source0Disabled         = 0U,          /**< Trigger function is disabled */
+    kTRGMUX_Source1Disabled         = 0U,          /**< Trigger function is disabled */
+    kTRGMUX_Source0Llwu0            = 1U,          /**< LLWU0 trigger is selected */
+    kTRGMUX_Source1Llwu1            = 1U,          /**< LLWU1 trigger is selected */
+    kTRGMUX_Source0Lpit0Channel0    = 2U,          /**< LPIT0 Channel 0 is selected */
+    kTRGMUX_Source1Lpit1Channel0    = 2U,          /**< LPIT1 Channel 0 is selected */
+    kTRGMUX_Source0Lpit0Channel1    = 3U,          /**< LPIT0 Channel 1 is selected */
+    kTRGMUX_Source1Lpit1Channel1    = 3U,          /**< LPIT1 Channel 1 is selected */
+    kTRGMUX_Source0Lpit0Channel2    = 4U,          /**< LPIT0 Channel 2 is selected */
+    kTRGMUX_Source1Lpit1Channel2    = 4U,          /**< LPIT1 Channel 2 is selected */
+    kTRGMUX_Source0Lpit0Channel3    = 5U,          /**< LPIT0 Channel 3 is selected */
+    kTRGMUX_Source1Lpit1Channel3    = 5U,          /**< LPIT1 Channel 3 is selected */
+    kTRGMUX_Source0RtcAlarm         = 6U,          /**< RTC Alarm is selected */
+    kTRGMUX_Source1Lptmr2Trigger    = 6U,          /**< LPTMR2 Trigger is selected */
+    kTRGMUX_Source0RtcSeconds       = 7U,          /**< RTC Seconds is selected */
+    kTRGMUX_Source1Tpm3ChannelEven  = 7U,          /**< TPM3 Channel Even is selected */
+    kTRGMUX_Source0Lptmr0Trigger    = 8U,          /**< LPTMR0 Trigger is selected */
+    kTRGMUX_Source1Tpm3ChannelOdd   = 8U,          /**< TPM3 Channel Odd is selected */
+    kTRGMUX_Source0Lptmr1Trigger    = 9U,          /**< LPTMR1 Trigger is selected */
+    kTRGMUX_Source1Tpm3Overflow     = 9U,          /**< TPM3 Overflow is selected */
+    kTRGMUX_Source0Tpm0ChannelEven  = 10U,         /**< TPM0 Channel Even is selected */
+    kTRGMUX_Source1Lpi2c3MasterStop = 10U,         /**< LPI2C3 Master Stop is selected */
+    kTRGMUX_Source0Tpm0ChannelOdd   = 11U,         /**< TPM0 Channel Odd is selected */
+    kTRGMUX_Source1Lpi2c3SlaveStop  = 11U,         /**< LPI2C3 Slave Stop is selected */
+    kTRGMUX_Source0Tpm0Overflow     = 12U,         /**< TPM0 Overflow is selected */
+    kTRGMUX_Source1Lpspi3Frame      = 12U,         /**< LPSPI3 Frame is selected */
+    kTRGMUX_Source0Tpm1ChannelEven  = 13U,         /**< TPM1 Channel Even is selected */
+    kTRGMUX_Source1Lpspi3RX         = 13U,         /**< LPSPI3 Rx is selected */
+    kTRGMUX_Source0Tpm1ChannelOdd   = 14U,         /**< TPM1 Channel Odd is selected */
+    kTRGMUX_Source1Lpuart3RxData    = 14U,         /**< LPUART3 Rx Data is selected */
+    kTRGMUX_Source0Tpm1Overflow     = 15U,         /**< TPM1 Overflow is selected */
+    kTRGMUX_Source1Lpuart3RxIdle    = 15U,         /**< LPUART3 Rx Idle is selected */
+    kTRGMUX_Source0Tpm2ChannelEven  = 16U,         /**< TPM2 Channel Even is selected */
+    kTRGMUX_Source1Lpuart3TxData    = 16U,         /**< LPUART3 Tx Data is selected */
+    kTRGMUX_Source0Tpm2ChannelOdd   = 17U,         /**< TPM2 Channel Odd is selected */
+    kTRGMUX_Source1PortEPinTrigger  = 17U,         /**< PORTE Pin Trigger is selected */
+    kTRGMUX_Source0Tpm2Overflow     = 18U,         /**< TPM2 Overflow is selected */
+    kTRGMUX_Source1Lpcmp1Output     = 18U,         /**< LPCMP1 Output is selected */
+    kTRGMUX_Source0FlexIO0Timer0    = 19U,         /**< FlexIO0 Timer 0 is selected */
+    kTRGMUX_Source1RtcAlarm         = 19U,         /**< RTC Alarm is selected */
+    kTRGMUX_Source0FlexIO0Timer1    = 20U,         /**< FlexIO0 Timer 1 is selected */
+    kTRGMUX_Source1RtcSeconds       = 20U,         /**< RTC Seconds is selected */
+    kTRGMUX_Source0FlexIO0Timer2    = 21U,         /**< FlexIO0 Timer 2 is selected */
+    kTRGMUX_Source1Lptmr0Trigger    = 21U,         /**< LPTMR0 Trigger is selected */
+    kTRGMUX_Source0FlexIO0Timer3    = 22U,         /**< FlexIO0 Timer 3 is selected */
+    kTRGMUX_Source1Lptmr1Trigger    = 22U,         /**< LPTMR1 Trigger is selected */
+    kTRGMUX_Source0FlexIO0Timer4    = 23U,         /**< FLexIO0 Timer 4 is selected */
+    kTRGMUX_Source1Tpm1ChannelEven  = 23U,         /**< TPM1 Channel Even is selected */
+    kTRGMUX_Source0FlexIO0Timer5    = 24U,         /**< FlexIO0 Timer 5 is selected */
+    kTRGMUX_Source1Tpm1ChannelOdd   = 24U,         /**< TPM1 Channel Odd is selected */
+    kTRGMUX_Source0FlexIO0Timer6    = 25U,         /**< FlexIO0 Timer 6 is selected */
+    kTRGMUX_Source1Tpm1Overflow     = 25U,         /**< TPM1 Overflow is selected */
+    kTRGMUX_Source0FlexIO0Timer7    = 26U,         /**< FlexIO0 Timer 7 is selected */
+    kTRGMUX_Source1Tpm2ChannelEven  = 26U,         /**< TPM2 Channel Even is selected */
+    kTRGMUX_Source0Lpi2c0MasterStop = 27U,         /**< LPI2C0 Master Stop is selected */
+    kTRGMUX_Source1Tpm2ChannelOdd   = 27U,         /**< TPM2 Channel Odd is selected */
+    kTRGMUX_Source0Lpi2c0SlaveStop  = 28U,         /**< LPI2C0 Slave Stop is selected */
+    kTRGMUX_Source1Tpm2Overflow     = 28U,         /**< TPM2 Overflow is selected */
+    kTRGMUX_Source0Lpi2c1MasterStop = 29U,         /**< LPI2C1 Master Stop is selected */
+    kTRGMUX_Source1FlexIO0Timer0    = 29U,         /**< FlexIO0 Timer 0 is selected */
+    kTRGMUX_Source0Lpi2c1SlaveStop  = 30U,         /**< LPI2C1 Slave Stop is selected */
+    kTRGMUX_Source1FlexIO0Timer1    = 30U,         /**< FlexIO0 Timer 1 is selected */
+    kTRGMUX_Source0Lpi2c2MasterStop = 31U,         /**< LPI2C2 Master Stop is selected */
+    kTRGMUX_Source1FlexIO0Timer2    = 31U,         /**< FlexIO0 Timer 2 is selected */
+    kTRGMUX_Source0Lpi2c2SlaveStop  = 32U,         /**< LPI2C2 Slave Stop is selected */
+    kTRGMUX_Source1FlexIO0Timer3    = 32U,         /**< FlexIO0 Timer 3 is selected */
+    kTRGMUX_Source0Sai0Rx           = 33U,         /**< SAI0 Rx Frame Sync is selected */
+    kTRGMUX_Source1FlexIO0Timer4    = 33U,         /**< FLexIO0 Timer 4 is selected */
+    kTRGMUX_Source0Sai0Tx           = 34U,         /**< SAI0 Tx Frame Sync is selected */
+    kTRGMUX_Source1FlexIO0Timer5    = 34U,         /**< FlexIO0 Timer 5 is selected */
+    kTRGMUX_Source0Lpspi0Frame      = 35U,         /**< LPSPI0 Frame is selected */
+    kTRGMUX_Source1FlexIO0Timer6    = 35U,         /**< FlexIO0 Timer 6 is selected */
+    kTRGMUX_Source0Lpspi0Rx         = 36U,         /**< LPSPI0 Rx is selected */
+    kTRGMUX_Source1FlexIO0Timer7    = 36U,         /**< FlexIO0 Timer 7 is selected */
+    kTRGMUX_Source0Lpspi1Frame      = 37U,         /**< LPSPI1 Frame is selected */
+    kTRGMUX_Source1Lpi2c0MasterStop = 37U,         /**< LPI2C0 Master Stop is selected */
+    kTRGMUX_Source0Lpspi1Rx         = 38U,         /**< LPSPI1 Rx is selected */
+    kTRGMUX_Source1Lpi2c0SlaveStop  = 38U,         /**< LPI2C0 Slave Stop is selected */
+    kTRGMUX_Source0Lpspi2Frame      = 39U,         /**< LPSPI2 Frame is selected */
+    kTRGMUX_Source1Lpi2c1MasterStop = 39U,         /**< LPI2C1 Master Stop is selected */
+    kTRGMUX_Source0Lpspi2RX         = 40U,         /**< LPSPI2 Rx is selected */
+    kTRGMUX_Source1Lpi2c1SlaveStop  = 40U,         /**< LPI2C1 Slave Stop is selected */
+    kTRGMUX_Source0Lpuart0RxData    = 41U,         /**< LPUART0 Rx Data is selected */
+    kTRGMUX_Source1Lpi2c2MasterStop = 41U,         /**< LPI2C2 Master Stop is selected */
+    kTRGMUX_Source0Lpuart0RxIdle    = 42U,         /**< LPUART0 Rx Idle is selected */
+    kTRGMUX_Source1Lpi2c2SlaveStop  = 42U,         /**< LPI2C2 Slave Stop is selected */
+    kTRGMUX_Source0Lpuart0TxData    = 43U,         /**< LPUART0 Tx Data is selected */
+    kTRGMUX_Source1Sai0Rx           = 43U,         /**< SAI0 Rx Frame Sync is selected */
+    kTRGMUX_Source0Lpuart1RxData    = 44U,         /**< LPUART1 Rx Data is selected */
+    kTRGMUX_Source1Sai0Tx           = 44U,         /**< SAI0 Tx Frame Sync is selected */
+    kTRGMUX_Source0Lpuart1RxIdle    = 45U,         /**< LPUART1 Rx Idle is selected */
+    kTRGMUX_Source1Lpspi0Frame      = 45U,         /**< LPSPI0 Frame is selected */
+    kTRGMUX_Source0Lpuart1TxData    = 46U,         /**< LPUART1 TX Data is selected */
+    kTRGMUX_Source1Lpspi0Rx         = 46U,         /**< LPSPI0 Rx is selected */
+    kTRGMUX_Source0Lpuart2RxData    = 47U,         /**< LPUART2 RX Data is selected */
+    kTRGMUX_Source1Lpspi1Frame      = 47U,         /**< LPSPI1 Frame is selected */
+    kTRGMUX_Source0Lpuart2RxIdle    = 48U,         /**< LPUART2 RX Idle is selected */
+    kTRGMUX_Source1Lpspi1Rx         = 48U,         /**< LPSPI1 Rx is selected */
+    kTRGMUX_Source0Lpuart2TxData    = 49U,         /**< LPUART2 TX Data is selected */
+    kTRGMUX_Source1Lpspi2Frame      = 49U,         /**< LPSPI2 Frame is selected */
+    kTRGMUX_Source0Usb0Frame        = 50U,         /**< USB0 Start of Frame is selected */
+    kTRGMUX_Source1Lpspi2RX         = 50U,         /**< LPSPI2 Rx is selected */
+    kTRGMUX_Source0PortAPinTrigger  = 51U,         /**< PORTA Pin Trigger is selected */
+    kTRGMUX_Source1Lpuart0RxData    = 51U,         /**< LPUART0 Rx Data is selected */
+    kTRGMUX_Source0PortBPinTrigger  = 52U,         /**< PORTB Pin Trigger is selected */
+    kTRGMUX_Source1Lpuart0RxIdle    = 52U,         /**< LPUART0 Rx Idle is selected */
+    kTRGMUX_Source0PortCPinTrigger  = 53U,         /**< PORTC Pin Trigger is selected */
+    kTRGMUX_Source1Lpuart0TxData    = 53U,         /**< LPUART0 Tx Data is selected */
+    kTRGMUX_Source0PortDPinTrigger  = 54U,         /**< PORTD Pin Trigger is selected */
+    kTRGMUX_Source1Lpuart1RxData    = 54U,         /**< LPUART1 Rx Data is selected */
+    kTRGMUX_Source0Lpcmp0Output     = 55U,         /**< LPCMP0 Output is selected */
+    kTRGMUX_Source1Lpuart1RxIdle    = 55U,         /**< LPUART1 Rx Idle is selected */
+    kTRGMUX_Source0Lpi2c3MasterStop = 56U,         /**< LPI2C3 Master Stop is selected */
+    kTRGMUX_Source1Lpuart1TxData    = 56U,         /**< LPUART1 TX Data is selected */
+    kTRGMUX_Source0Lpi2c3SlaveStop  = 57U,         /**< LPI2C3 Slave Stop is selected */
+    kTRGMUX_Source1Lpuart2RxData    = 57U,         /**< LPUART2 RX Data is selected */
+    kTRGMUX_Source0Lpspi3Frame      = 58U,         /**< LPSPI3 Frame is selected */
+    kTRGMUX_Source1Lpuart2RxIdle    = 58U,         /**< LPUART2 RX Idle is selected */
+    kTRGMUX_Source0Lpspi3Rx         = 59U,         /**< LPSPI3 Rx Data is selected */
+    kTRGMUX_Source1Lpuart2TxData    = 59U,         /**< LPUART2 TX Data is selected */
+    kTRGMUX_Source0Lpuart3RxData    = 60U,         /**< LPUART3 Rx Data is selected */
+    kTRGMUX_Source1PortAPinTrigger  = 60U,         /**< PORTA Pin Trigger is selected */
+    kTRGMUX_Source0Lpuart3RxIdle    = 61U,         /**< LPUART3 Rx Idle is selected */
+    kTRGMUX_Source1PortBPinTrigger  = 61U,         /**< PORTB Pin Trigger is selected */
+    kTRGMUX_Source0Lpuart3TxData    = 62U,         /**< LPUART3 Tx Data is selected */
+    kTRGMUX_Source1PortCPinTrigger  = 62U,         /**< PORTC Pin Trigger is selected */
+    kTRGMUX_Source0PortEPinTrigger  = 63U,         /**< PORTE Pin Trigger is selected */
+    kTRGMUX_Source1PortDPinTrigger  = 63U,         /**< PORTD Pin Trigger is selected */
+} trgmux_source_t;
+
+/* @} */
+
+/*!
+ * @brief Enumeration for the TRGMUX device
+ *
+ * Defines the enumeration for the TRGMUX device collections.
+ */
+typedef enum _trgmux_device
+{
+    kTRGMUX_Trgmux0Dmamux0          = 0U,          /**< DMAMUX0 device trigger input */
+    kTRGMUX_Trgmux1Dmamux1          = 0U,          /**< DMAMUX1 device trigger input */
+    kTRGMUX_Trgmux0Lpit0            = 1U,          /**< LPIT0 device trigger input */
+    kTRGMUX_Trgmux1Lpit1            = 1U,          /**< LPIT1 device trigger input */
+    kTRGMUX_Trgmux0Tpm0             = 2U,          /**< TPM0 device trigger input */
+    kTRGMUX_Trgmux1Tpm3             = 2U,          /**< TPM3 device trigger input */
+    kTRGMUX_Trgmux0Tpm1             = 3U,          /**< TPM1 device trigger input */
+    kTRGMUX_Trgmux1Lpi2c3           = 3U,          /**< LPI2C3 device trigger input */
+    kTRGMUX_Trgmux0Tpm2             = 4U,          /**< TPM2 device trigger input */
+    kTRGMUX_Trgmux1Lpspi3           = 4U,          /**< LPSPI3 device trigger input */
+    kTRGMUX_Trgmux0Flexio0          = 5U,          /**< FLEXIO0 device trigger input */
+    kTRGMUX_Trgmux1Lpuart3          = 5U,          /**< LPUART3 device trigger input */
+    kTRGMUX_Trgmux0Lpi2c0           = 6U,          /**< LPI2C0 device trigger input */
+    kTRGMUX_Trgmux1Lpcmp1           = 6U,          /**< LPCMP1 device trigger input */
+    kTRGMUX_Trgmux0Lpi2c1           = 7U,          /**< LPI2C1 device trigger input */
+    kTRGMUX_Trgmux1Dmamux0          = 7U,          /**< DMAMUX0 device trigger input */
+    kTRGMUX_Trgmux0Lpi2c2           = 8U,          /**< LPI2C2 device trigger input */
+    kTRGMUX_Trgmux1Lpit0            = 8U,          /**< LPIT0 device trigger input */
+    kTRGMUX_Trgmux0Lpspi0           = 9U,          /**< LPSPI0 device trigger input */
+    kTRGMUX_Trgmux1Tpm0             = 9U,          /**< TPM0 device trigger input */
+    kTRGMUX_Trgmux0Lpspi1           = 10U,         /**< LPSPI1 device trigger input */
+    kTRGMUX_Trgmux1Tpm1             = 10U,         /**< TPM1 device trigger input */
+    kTRGMUX_Trgmux0Lpspi2           = 11U,         /**< LPSPI2 device trigger input */
+    kTRGMUX_Trgmux1Tpm2             = 11U,         /**< TPM2 device trigger input */
+    kTRGMUX_Trgmux0Lpuart0          = 12U,         /**< LPUART0 device trigger input */
+    kTRGMUX_Trgmux1Flexio0          = 12U,         /**< FLEXIO0 device trigger input */
+    kTRGMUX_Trgmux0Lpuart1          = 13U,         /**< LPUART1 device trigger input */
+    kTRGMUX_Trgmux1Lpi2c0           = 13U,         /**< LPI2C0 device trigger input */
+    kTRGMUX_Trgmux0Lpuart2          = 14U,         /**< LPUART2 device trigger input */
+    kTRGMUX_Trgmux1Lpi2c1           = 14U,         /**< LPI2C1 device trigger input */
+    kTRGMUX_Trgmux0Adc0             = 15U,         /**< ADC0 device trigger input */
+    kTRGMUX_Trgmux1Lpi2c2           = 15U,         /**< LPI2C2 device trigger input */
+    kTRGMUX_Trgmux0Lpcmp0           = 16U,         /**< LPCMP0 device trigger input */
+    kTRGMUX_Trgmux1Lpspi0           = 16U,         /**< LPSPI0 device trigger input */
+    kTRGMUX_Trgmux0Dac0             = 17U,         /**< DAC0 device trigger input */
+    kTRGMUX_Trgmux1Lpspi1           = 17U,         /**< LPSPI1 device trigger input */
+    kTRGMUX_Trgmux0Dmamux1          = 18U,         /**< DMAMUX1 device trigger input */
+    kTRGMUX_Trgmux1Lpspi2           = 18U,         /**< LPSPI2 device trigger input */
+    kTRGMUX_Trgmux0Lpit1            = 19U,         /**< LPIT1 device trigger input */
+    kTRGMUX_Trgmux1Lpuart0          = 19U,         /**< LPUART0 device trigger input */
+    kTRGMUX_Trgmux0Tpm3             = 20U,         /**< TPM3 device trigger input */
+    kTRGMUX_Trgmux1Lpuart1          = 20U,         /**< LPUART1 device trigger input */
+    kTRGMUX_Trgmux0Lpi2c3           = 21U,         /**< LPI2C3 device trigger input */
+    kTRGMUX_Trgmux1Lpuart2          = 21U,         /**< LPUART2 device trigger input */
+    kTRGMUX_Trgmux0Lpspi3           = 22U,         /**< LPSPI3 device trigger input */
+    kTRGMUX_Trgmux1Adc0             = 22U,         /**< ADC0 device trigger input */
+    kTRGMUX_Trgmux0Lpuart3          = 23U,         /**< LPUART3 device trigger input */
+    kTRGMUX_Trgmux1Lpcmp0           = 23U,         /**< LPCMP0 device trigger input */
+    kTRGMUX_Trgmux0Lpcmp1           = 24U,         /**< LPCMP1 device trigger input */
+    kTRGMUX_Trgmux1Lpdac0           = 24U,         /**< LPDAC0 device trigger input */
+} trgmux_device_t;
+
+/* @} */
+
+/*!
+ * @addtogroup xrdc_mapping
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the XRDC mapping
+ *
+ * Defines the structure for the XRDC resource collections.
+ */
+
+typedef enum _xrdc_master
+{
+    kXRDC_MasterCM4CodeBus          = 0U,          /**< CM4 C-BUS */
+    kXRDC_MasterCM4SystemBus        = 1U,          /**< CM4 S-BUS */
+    kXRDC_MasterRI5CYCodeBus        = 16U,         /**< RI5CY C-BUS */
+    kXRDC_MasterRI5CYSystemBus      = 17U,         /**< RI5CY S-BUS */
+    kXRDC_MasterEdma0               = 2U,          /**< EDMA0 */
+    kXRDC_MasterUsdhc               = 3U,          /**< USDHC */
+    kXRDC_MasterUsb                 = 4U,          /**< USB */
+    kXRDC_MasterCM0P                = 32U,         /**< CM0P */
+    kXRDC_MasterEdma1               = 33U,         /**< EDMA1 */
+    kXRDC_MasterCau3                = 34U,         /**< CAU3 */
+    kXRDC_MasterZERORISCYCodeBus    = 35U,         /**<  ZERO RISCY C-BUS */
+    kXRDC_MasterZERORISCYSystemBus  = 36U,         /**< ZERO RISCY S-BUS */
+} xrdc_master_t;
+
+/* @} */
+
+typedef enum _xrdc_mem
+{
+    kXRDC_MemMrc0_0                 = 0U,          /**< MRC0 Memory 0 */
+    kXRDC_MemMrc0_1                 = 1U,          /**< MRC0 Memory 1 */
+    kXRDC_MemMrc0_2                 = 2U,          /**< MRC0 Memory 2 */
+    kXRDC_MemMrc0_3                 = 3U,          /**< MRC0 Memory 3 */
+    kXRDC_MemMrc0_4                 = 4U,          /**< MRC0 Memory 4 */
+    kXRDC_MemMrc0_5                 = 5U,          /**< MRC0 Memory 5 */
+    kXRDC_MemMrc0_6                 = 6U,          /**< MRC0 Memory 6 */
+    kXRDC_MemMrc0_7                 = 7U,          /**< MRC0 Memory 7 */
+    kXRDC_MemMrc1_0                 = 16U,         /**< MRC1 Memory 0 */
+    kXRDC_MemMrc1_1                 = 17U,         /**< MRC1 Memory 1 */
+    kXRDC_MemMrc1_2                 = 18U,         /**< MRC1 Memory 2 */
+    kXRDC_MemMrc1_3                 = 19U,         /**< MRC1 Memory 3 */
+    kXRDC_MemMrc1_4                 = 20U,         /**< MRC1 Memory 4 */
+    kXRDC_MemMrc1_5                 = 21U,         /**< MRC1 Memory 5 */
+    kXRDC_MemMrc1_6                 = 22U,         /**< MRC1 Memory 6 */
+    kXRDC_MemMrc1_7                 = 23U,         /**< MRC1 Memory 7 */
+} xrdc_mem_t;
+
+typedef enum _xrdc_periph
+{
+    kXRDC_PeriphMscm                = 1U,          /**< Miscellaneous System Control Module (MSCM) */
+    kXRDC_PeriphDma0                = 8U,          /**< Direct Memory Access 0 (DMA0) controller */
+    kXRDC_PeriphDma0Tcd             = 9U,          /**< Direct Memory Access 0 (DMA0) controller transfer control descriptors */
+    kXRDC_PeriphFlexBus             = 12U,         /**< External Bus Interface(FlexBus) */
+    kXRDC_PeriphXrdcMgr             = 20U,         /**< Extended Resource Domain Controller (XRDC) MGR */
+    kXRDC_PeriphXrdcMdac            = 21U,         /**< Extended Resource Domain Controller (XRDC) MDAC */
+    kXRDC_PeriphXrdcPac             = 22U,         /**< Extended Resource Domain Controller (XRDC) PAC */
+    kXRDC_PeriphXrdcMrc             = 23U,         /**< Extended Resource Domain Controller (XRDC) MRC */
+    kXRDC_PeriphSema420             = 27U,         /**< Semaphore Unit 0 (SEMA420) */
+    kXRDC_PeriphCmc0                = 32U,         /**< Core Mode Controller (CMC) */
+    kXRDC_PeriphDmamux0             = 33U,         /**< Direct Memory Access Multiplexer 0 (DMAMUX0) */
+    kXRDC_PeriphEwm                 = 34U,         /**< External Watchdog Monitor (EWM) */
+    kXRDC_PeriphFtfe                = 35U,         /**< Flash Memory Module (FTFE) */
+    kXRDC_PeriphLlwu0               = 36U,         /**< Low Leakage Wake-up Unit 0 (LLWU0) */
+    kXRDC_PeriphMua                 = 37U,         /**< Message Unit Side A (MU-A) */
+    kXRDC_PeriphSim                 = 38U,         /**< System Integration Module (SIM) */
+    kXRDC_PeriphSimdgo              = 39U,         /**< System Integration Module - DGO (SIM-DGO) */
+    kXRDC_PeriphSpm                 = 40U,         /**< System Power Management (SPM) */
+    kXRDC_PeriphTrgmux0             = 41U,         /**< Tirgger Multiplexer 0 (TRGMUX0) */
+    kXRDC_PeriphWdog0               = 42U,         /**< Watchdog 0 (WDOG0) */
+    kXRDC_PeriphPcc0                = 43U,         /**< Peripheral Clock Controller 0 (PCC0) */
+    kXRDC_PeriphScg                 = 44U,         /**< System Clock Generator (SCG) */
+    kXRDC_PeriphSrf                 = 45U,         /**< System Register File */
+    kXRDC_PeriphVbat                = 46U,         /**< VBAT Register File */
+    kXRDC_PeriphCrc0                = 47U,         /**< Cyclic Redundancy Check 0 (CRC0) */
+    kXRDC_PeriphLpit0               = 48U,         /**< Low-Power Periodic Interrupt Timer 0 (LPIT0) */
+    kXRDC_PeriphRtc                 = 49U,         /**< Real Time Clock (RTC) */
+    kXRDC_PeriphLptmr0              = 50U,         /**< Low-Power Timer 0 (LPTMR0) */
+    kXRDC_PeriphLptmr1              = 51U,         /**< Low-Power Timer 1 (LPTMR1) */
+    kXRDC_PeriphTstmr0              = 52U,         /**< Time Stamp Timer 0 (TSTMR0) */
+    kXRDC_PeriphTpm0                = 53U,         /**< Timer / Pulse Width Modulator Module 0 (TPM0) - 6 channel */
+    kXRDC_PeriphTpm1                = 54U,         /**< Timer / Pulse Width Modulator Module 1 (TPM1) - 2 channel */
+    kXRDC_PeriphTpm2                = 55U,         /**< Timer / Pulse Width Modulator Module 2 (TPM2) - 6 channel */
+    kXRDC_PeriphEmvsim0             = 56U,         /**< Euro Mastercard Visa Secure Identity Module 0 (EMVSIM0) */
+    kXRDC_PeriphFlexio0             = 57U,         /**< Flexible Input / Output 0 (FlexIO0) */
+    kXRDC_PeriphLpi2c0              = 58U,         /**< Low-Power Inter-Integrated Circuit 0 (LPI2C0) */
+    kXRDC_PeriphLpi2c1              = 59U,         /**< Low-Power Inter-Integrated Circuit 1 (LPI2C1) */
+    kXRDC_PeriphLpi2c2              = 60U,         /**< Low-Power Inter-Integrated Circuit 2 (LPI2C2) */
+    kXRDC_PeriphSai0                = 61U,         /**< Serial Audio Interface 0 (SAI0) */
+    kXRDC_PeriphSdhc0               = 62U,         /**< Secure Digital Host Controller 0 (SDHC0) */
+    kXRDC_PeriphLpspi0              = 63U,         /**< Low-Power Serial Peripheral Interface 0 (LPSPI0) */
+    kXRDC_PeriphLpspi1              = 64U,         /**< Low-Power Serial Peripheral Interface 1 (LPSPI1) */
+    kXRDC_PeriphLpspi2              = 65U,         /**< Low-Power Serial Peripheral Interface 2 (LPSPI2) */
+    kXRDC_PeriphLpuart0             = 66U,         /**< Low-Power Universal Asynchronous Receive / Transmit 0 (LPUART0) */
+    kXRDC_PeriphLpuart1             = 67U,         /**< Low-Power Universal Asynchronous Receive / Transmit 1 (LPUART1) */
+    kXRDC_PeriphLpuart2             = 68U,         /**< Low-Power Universal Asynchronous Receive / Transmit 2 (LPUART2) */
+    kXRDC_PeriphUsb0                = 69U,         /**< Universal Serial Bus 0 (USB0) - Full Speed, Device Only */
+    kXRDC_PeriphPortA               = 70U,         /**< PORTA Multiplex Control */
+    kXRDC_PeriphPortB               = 71U,         /**< PORTB Multiplex Control */
+    kXRDC_PeriphPortC               = 72U,         /**< PORTC Multiplex Control */
+    kXRDC_PeriphPortD               = 73U,         /**< PORTD Multiplex Control */
+    kXRDC_PeriphLpadc0              = 74U,         /**< Low-Power Analog-to-Digital Converter 0 (LPADC0) */
+    kXRDC_PeriphLpcmp0              = 75U,         /**< Low-Power Comparator 0 (LPCMP0) */
+    kXRDC_PeriphDac0                = 76U,         /**< Digital-to-Analog Converter 0 (DAC0) */
+    kXRDC_PeriphVref                = 77U,         /**< Voltage Reference (VREF) */
+    kXRDC_PeriphDma1                = 136U,        /**< Direct Memory Access 1 (DMA1) controller */
+    kXRDC_PeriphDma1Tcd             = 137U,        /**< Direct Memory Access 1 (DMA1) controller trasfer control descriptors */
+    kXRDC_PeriphFgpio1              = 143U,        /**< IO Port Alias */
+    kXRDC_PeriphSema421             = 155U,        /**< Semaphore Unit 1 (SEMA421) */
+    kXRDC_PeriphCmc1                = 160U,        /**< Core Mode Controller (CMC) */
+    kXRDC_PeriphDmamux1             = 161U,        /**< Direct Memory Access Mutiplexer 1 (DMAMUX1) */
+    kXRDC_PeriphIntmux0             = 162U,        /**< Interrupt Multiplexer 0 (INTMUX0) */
+    kXRDC_Periphllwu1               = 163U,        /**< Low Leakage Wake-up Unit 1 (LLWU1) */
+    kXRDC_PeriphMub                 = 164U,        /**< Messaging Unit - Side B (MU-B) */
+    kXRDC_PeriphTrgmux1             = 165U,        /**< Trigger Multiplexer 1 (TRGMUX1) */
+    kXRDC_PeriphWdog1               = 166U,        /**< Watchdog 1 (WDOG1) */
+    kXRDC_PeriphPcc1                = 167U,        /**< Peripheral Clock Controller 1 (PCC1) */
+    kXRDC_PeriphCau3                = 168U,        /**< Cryptographic Acceleration Unit (CAU3) */
+    kXRDC_PeriphTrng                = 169U,        /**< True Random Number Generator (TRNG) */
+    kXRDC_PeriphLpit1               = 170U,        /**< Low-Power Periodic Interrupt Timer 1 (LPIT1) */
+    kXRDC_PeriphLptmr2              = 171U,        /**< Low-Power Timer 2 (LPTMR2) */
+    kXRDC_PeriphTstmr1              = 172U,        /**< Time Stamp Timer 1 (TSTMR1) */
+    kXRDC_PeriphTpm3                = 173U,        /**< Timer / Pulse Width Modulation Module 3 (TPM3) - 2 channel */
+    kXRDC_PeriphLpi2c3              = 174U,        /**< Low-Power Inter-Integrated Circuit 3 (LPI2C3) */
+    kXRDC_PeriphRsim                = 175U,        /**< 2.4GHz Radio (RF2.4G) - RSIM */
+    kXRDC_PeriphXcvr                = 176U,        /**< 2.4GHz Radio (RF2.4G) - XCVR */
+    kXRDC_PeriphAnt                 = 177U,        /**< 2.4GHz Radio (RF2.4G) - ANT+ Link Layer */
+    kXRDC_PeriphBle                 = 178U,        /**< 2.4GHz Radio (RF2.4G) - Bluetooth Link layer */
+    kXRDC_PeriphGfsk                = 179U,        /**< 2.4GHz Radio (RF2.4G) - Generic Link layer */
+    kXRDC_PeriphIeee                = 180U,        /**< 2.4GHz Radio (RF2.4G) - IEEE 802.15.4 Link Layer */
+    kXRDC_PeriphLpspi3              = 181U,        /**< Low-Power Serial Peripheral Interface 3 (LPSPI3) */
+    kXRDC_PeriphLpuart3             = 182U,        /**< Low-Power Universal Asynchronous Receive / Transmit 3 (LPUART3) */
+    kXRDC_PeriphPortE               = 183U,        /**< PORTE Multiplex Control */
+    kXRDC_PeriphLpcmp1              = 214U,        /**< Low-Power Comparator 1 (LPCMP1) */
+} xrdc_periph_t;
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t CTRL;                              /**< ADC Control Register, offset: 0x10 */
+  __IO uint32_t STAT;                              /**< ADC Status Register, offset: 0x14 */
+  __IO uint32_t IE;                                /**< Interrupt Enable Register, offset: 0x18 */
+  __IO uint32_t DE;                                /**< DMA Enable Register, offset: 0x1C */
+  __IO uint32_t CFG;                               /**< ADC Configuration Register, offset: 0x20 */
+  __IO uint32_t PAUSE;                             /**< ADC Pause Register, offset: 0x24 */
+       uint8_t RESERVED_1[8];
+  __IO uint32_t FCTRL;                             /**< ADC FIFO Control Register, offset: 0x30 */
+  __O  uint32_t SWTRIG;                            /**< Software Trigger Register, offset: 0x34 */
+       uint8_t RESERVED_2[8];
+  __IO uint32_t OFSTRIM;                           /**< ADC Offset Trim Register, offset: 0x40 */
+       uint8_t RESERVED_3[124];
+  __IO uint32_t TCTRL[4];                          /**< Trigger Control Register, array offset: 0xC0, array step: 0x4 */
+       uint8_t RESERVED_4[48];
+  struct {                                         /* offset: 0x100, array step: 0x8 */
+    __IO uint32_t CMDL;                              /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
+    __IO uint32_t CMDH;                              /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
+  } CMD[15];
+       uint8_t RESERVED_5[136];
+  __IO uint32_t CV[4];                             /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
+       uint8_t RESERVED_6[240];
+  __I  uint32_t RESFIFO;                           /**< ADC Data Result FIFO Register, offset: 0x300 */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define ADC_VERID_RES_MASK                       (0x1U)
+#define ADC_VERID_RES_SHIFT                      (0U)
+/*! RES - Resolution
+ *  0b0..Up to 13-bit differential/12-bit single ended resolution supported.
+ *  0b1..Up to 16-bit differential/15-bit single ended resolution supported.
+ */
+#define ADC_VERID_RES(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
+#define ADC_VERID_DIFFEN_MASK                    (0x2U)
+#define ADC_VERID_DIFFEN_SHIFT                   (1U)
+/*! DIFFEN - Differential Supported
+ *  0b0..Differential operation not supported.
+ *  0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented.
+ */
+#define ADC_VERID_DIFFEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
+#define ADC_VERID_MVI_MASK                       (0x8U)
+#define ADC_VERID_MVI_SHIFT                      (3U)
+/*! MVI - Multi Vref Implemented
+ *  0b0..Single voltage reference high (VREFH) input supported.
+ *  0b1..Multiple voltage reference high (VREFH) inputs supported.
+ */
+#define ADC_VERID_MVI(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
+#define ADC_VERID_CSW_MASK                       (0x70U)
+#define ADC_VERID_CSW_SHIFT                      (4U)
+/*! CSW - Channel Scale Width
+ *  0b000..Channel scaling not supported.
+ *  0b001..Channel scaling supported. 1-bit CSCALE control field.
+ *  0b110..Channel scaling supported. 6-bit CSCALE control field.
+ */
+#define ADC_VERID_CSW(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
+#define ADC_VERID_VR1RNGI_MASK                   (0x100U)
+#define ADC_VERID_VR1RNGI_SHIFT                  (8U)
+/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
+ *  0b0..Range control not required. CFG[VREF1RNG] is not implemented.
+ *  0b1..Range control required. CFG[VREF1RNG] is implemented.
+ */
+#define ADC_VERID_VR1RNGI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
+#define ADC_VERID_IADCKI_MASK                    (0x200U)
+#define ADC_VERID_IADCKI_SHIFT                   (9U)
+/*! IADCKI - Internal ADC Clock implemented
+ *  0b0..Internal clock source not implemented.
+ *  0b1..Internal clock source (and CFG[ADCKEN]) implemented.
+ */
+#define ADC_VERID_IADCKI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
+#define ADC_VERID_CALOFSI_MASK                   (0x400U)
+#define ADC_VERID_CALOFSI_SHIFT                  (10U)
+/*! CALOFSI - Calibration Offset Function Implemented
+ *  0b0..Offset calibration and offset trimming not implemented.
+ *  0b1..Offset calibration and offset trimming implemented.
+ */
+#define ADC_VERID_CALOFSI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
+#define ADC_VERID_MINOR_MASK                     (0xFF0000U)
+#define ADC_VERID_MINOR_SHIFT                    (16U)
+#define ADC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
+#define ADC_VERID_MAJOR_MASK                     (0xFF000000U)
+#define ADC_VERID_MAJOR_SHIFT                    (24U)
+#define ADC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define ADC_PARAM_TRIG_NUM_MASK                  (0xFFU)
+#define ADC_PARAM_TRIG_NUM_SHIFT                 (0U)
+#define ADC_PARAM_TRIG_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
+#define ADC_PARAM_FIFOSIZE_MASK                  (0xFF00U)
+#define ADC_PARAM_FIFOSIZE_SHIFT                 (8U)
+/*! FIFOSIZE - Result FIFO Depth
+ *  0b00000001..Result FIFO depth = 1 dataword.
+ *  0b00000100..Result FIFO depth = 4 datawords.
+ *  0b00001000..Result FIFO depth = 8 datawords.
+ *  0b00010000..Result FIFO depth = 16 datawords.
+ *  0b00100000..Result FIFO depth = 32 datawords.
+ *  0b01000000..Result FIFO depth = 64 datawords.
+ */
+#define ADC_PARAM_FIFOSIZE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
+#define ADC_PARAM_CV_NUM_MASK                    (0xFF0000U)
+#define ADC_PARAM_CV_NUM_SHIFT                   (16U)
+#define ADC_PARAM_CV_NUM(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
+#define ADC_PARAM_CMD_NUM_MASK                   (0xFF000000U)
+#define ADC_PARAM_CMD_NUM_SHIFT                  (24U)
+#define ADC_PARAM_CMD_NUM(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
+/*! @} */
+
+/*! @name CTRL - ADC Control Register */
+/*! @{ */
+#define ADC_CTRL_ADCEN_MASK                      (0x1U)
+#define ADC_CTRL_ADCEN_SHIFT                     (0U)
+/*! ADCEN - ADC Enable
+ *  0b0..ADC is disabled.
+ *  0b1..ADC is enabled.
+ */
+#define ADC_CTRL_ADCEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
+#define ADC_CTRL_RST_MASK                        (0x2U)
+#define ADC_CTRL_RST_SHIFT                       (1U)
+/*! RST - Software Reset
+ *  0b0..ADC logic is not reset.
+ *  0b1..ADC logic is reset.
+ */
+#define ADC_CTRL_RST(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
+#define ADC_CTRL_DOZEN_MASK                      (0x4U)
+#define ADC_CTRL_DOZEN_SHIFT                     (2U)
+/*! DOZEN - Doze Enable
+ *  0b0..ADC is enabled in Doze mode.
+ *  0b1..ADC is disabled in Doze mode.
+ */
+#define ADC_CTRL_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
+#define ADC_CTRL_RSTFIFO_MASK                    (0x100U)
+#define ADC_CTRL_RSTFIFO_SHIFT                   (8U)
+/*! RSTFIFO - Reset FIFO
+ *  0b0..No effect.
+ *  0b1..FIFO is reset.
+ */
+#define ADC_CTRL_RSTFIFO(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK)
+/*! @} */
+
+/*! @name STAT - ADC Status Register */
+/*! @{ */
+#define ADC_STAT_RDY_MASK                        (0x1U)
+#define ADC_STAT_RDY_SHIFT                       (0U)
+/*! RDY - Result FIFO Ready Flag
+ *  0b0..Result FIFO data level not above watermark level.
+ *  0b1..Result FIFO holding data above watermark level.
+ */
+#define ADC_STAT_RDY(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK)
+#define ADC_STAT_FOF_MASK                        (0x2U)
+#define ADC_STAT_FOF_SHIFT                       (1U)
+/*! FOF - Result FIFO Overflow Flag
+ *  0b0..No result FIFO overflow has occurred since the last time the flag was cleared.
+ *  0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared.
+ */
+#define ADC_STAT_FOF(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK)
+#define ADC_STAT_TRGACT_MASK                     (0x30000U)
+#define ADC_STAT_TRGACT_SHIFT                    (16U)
+/*! TRGACT - Trigger Active
+ *  0b00..Command (sequence) associated with Trigger 0 currently being executed.
+ *  0b01..Command (sequence) associated with Trigger 1 currently being executed.
+ *  0b10..Command (sequence) associated with Trigger 2 currently being executed.
+ *  0b11..Command (sequence) associated with Trigger 3 currently being executed.
+ */
+#define ADC_STAT_TRGACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
+#define ADC_STAT_CMDACT_MASK                     (0xF000000U)
+#define ADC_STAT_CMDACT_SHIFT                    (24U)
+/*! CMDACT - Command Active
+ *  0b0000..No command is currently in progress.
+ *  0b0001..Command 1 currently being executed.
+ *  0b0010..Command 2 currently being executed.
+ *  0b0011-0b1111..Associated command number is currently being executed.
+ */
+#define ADC_STAT_CMDACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
+/*! @} */
+
+/*! @name IE - Interrupt Enable Register */
+/*! @{ */
+#define ADC_IE_FWMIE_MASK                        (0x1U)
+#define ADC_IE_FWMIE_SHIFT                       (0U)
+/*! FWMIE - FIFO Watermark Interrupt Enable
+ *  0b0..FIFO watermark interrupts are not enabled.
+ *  0b1..FIFO watermark interrupts are enabled.
+ */
+#define ADC_IE_FWMIE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK)
+#define ADC_IE_FOFIE_MASK                        (0x2U)
+#define ADC_IE_FOFIE_SHIFT                       (1U)
+/*! FOFIE - Result FIFO Overflow Interrupt Enable
+ *  0b0..FIFO overflow interrupts are not enabled.
+ *  0b1..FIFO overflow interrupts are enabled.
+ */
+#define ADC_IE_FOFIE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK)
+/*! @} */
+
+/*! @name DE - DMA Enable Register */
+/*! @{ */
+#define ADC_DE_FWMDE_MASK                        (0x1U)
+#define ADC_DE_FWMDE_SHIFT                       (0U)
+/*! FWMDE - FIFO Watermark DMA Enable
+ *  0b0..DMA request disabled.
+ *  0b1..DMA request enabled.
+ */
+#define ADC_DE_FWMDE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK)
+/*! @} */
+
+/*! @name CFG - ADC Configuration Register */
+/*! @{ */
+#define ADC_CFG_TPRICTRL_MASK                    (0x1U)
+#define ADC_CFG_TPRICTRL_SHIFT                   (0U)
+/*! TPRICTRL - ADC trigger priority control
+ *  0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started.
+ *  0b1..If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true conversion.
+ */
+#define ADC_CFG_TPRICTRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
+#define ADC_CFG_PWRSEL_MASK                      (0x30U)
+#define ADC_CFG_PWRSEL_SHIFT                     (4U)
+/*! PWRSEL - Power Configuration Select
+ *  0b00..Level 1 (Lowest power setting)
+ *  0b01..Level 2
+ *  0b10..Level 3
+ *  0b11..Level 4 (Highest power setting)
+ */
+#define ADC_CFG_PWRSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
+#define ADC_CFG_REFSEL_MASK                      (0xC0U)
+#define ADC_CFG_REFSEL_SHIFT                     (6U)
+/*! REFSEL - Voltage Reference Selection
+ *  0b00..(Default) Option 1 setting.
+ *  0b01..Option 2 setting.
+ *  0b10..Option 3 setting.
+ *  0b11..Reserved
+ */
+#define ADC_CFG_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
+#define ADC_CFG_CALOFS_MASK                      (0x8000U)
+#define ADC_CFG_CALOFS_SHIFT                     (15U)
+/*! CALOFS - Configure for offset calibration function
+ *  0b0..Calibration function disabled
+ *  0b1..Configure for offset calibration function
+ */
+#define ADC_CFG_CALOFS(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_CALOFS_SHIFT)) & ADC_CFG_CALOFS_MASK)
+#define ADC_CFG_PUDLY_MASK                       (0xFF0000U)
+#define ADC_CFG_PUDLY_SHIFT                      (16U)
+#define ADC_CFG_PUDLY(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
+#define ADC_CFG_PWREN_MASK                       (0x10000000U)
+#define ADC_CFG_PWREN_SHIFT                      (28U)
+/*! PWREN - ADC Analog Pre-Enable
+ *  0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
+ *  0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any detected trigger does not begin ADC operation until the power up delay time has passed.
+ */
+#define ADC_CFG_PWREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
+#define ADC_CFG_VREF1RNG_MASK                    (0x20000000U)
+#define ADC_CFG_VREF1RNG_SHIFT                   (29U)
+/*! VREF1RNG - Enable support for low voltage reference on Option 1 Reference
+ *  0b0..Configuration required when Voltage Reference Option 1 input is in high voltage range
+ *  0b1..Configuration required when Voltage Reference Option 1 input is in low voltage range
+ */
+#define ADC_CFG_VREF1RNG(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_VREF1RNG_SHIFT)) & ADC_CFG_VREF1RNG_MASK)
+#define ADC_CFG_ADCKEN_MASK                      (0x80000000U)
+#define ADC_CFG_ADCKEN_SHIFT                     (31U)
+/*! ADCKEN - ADC asynchronous clock enable
+ *  0b0..ADC internal clock is disabled
+ *  0b1..ADC internal clock is enabled
+ */
+#define ADC_CFG_ADCKEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADCKEN_SHIFT)) & ADC_CFG_ADCKEN_MASK)
+/*! @} */
+
+/*! @name PAUSE - ADC Pause Register */
+/*! @{ */
+#define ADC_PAUSE_PAUSEDLY_MASK                  (0x1FFU)
+#define ADC_PAUSE_PAUSEDLY_SHIFT                 (0U)
+#define ADC_PAUSE_PAUSEDLY(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
+#define ADC_PAUSE_PAUSEEN_MASK                   (0x80000000U)
+#define ADC_PAUSE_PAUSEEN_SHIFT                  (31U)
+/*! PAUSEEN - PAUSE Option Enable
+ *  0b0..Pause operation disabled
+ *  0b1..Pause operation enabled
+ */
+#define ADC_PAUSE_PAUSEEN(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
+/*! @} */
+
+/*! @name FCTRL - ADC FIFO Control Register */
+/*! @{ */
+#define ADC_FCTRL_FCOUNT_MASK                    (0x1FU)
+#define ADC_FCTRL_FCOUNT_SHIFT                   (0U)
+#define ADC_FCTRL_FCOUNT(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
+#define ADC_FCTRL_FWMARK_MASK                    (0xF0000U)
+#define ADC_FCTRL_FWMARK_SHIFT                   (16U)
+#define ADC_FCTRL_FWMARK(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
+/*! @} */
+
+/*! @name SWTRIG - Software Trigger Register */
+/*! @{ */
+#define ADC_SWTRIG_SWT0_MASK                     (0x1U)
+#define ADC_SWTRIG_SWT0_SHIFT                    (0U)
+/*! SWT0 - Software trigger 0 event
+ *  0b0..No trigger 0 event generated.
+ *  0b1..Trigger 0 event generated.
+ */
+#define ADC_SWTRIG_SWT0(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
+#define ADC_SWTRIG_SWT1_MASK                     (0x2U)
+#define ADC_SWTRIG_SWT1_SHIFT                    (1U)
+/*! SWT1 - Software trigger 1 event
+ *  0b0..No trigger 1 event generated.
+ *  0b1..Trigger 1 event generated.
+ */
+#define ADC_SWTRIG_SWT1(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
+#define ADC_SWTRIG_SWT2_MASK                     (0x4U)
+#define ADC_SWTRIG_SWT2_SHIFT                    (2U)
+/*! SWT2 - Software trigger 2 event
+ *  0b0..No trigger 2 event generated.
+ *  0b1..Trigger 2 event generated.
+ */
+#define ADC_SWTRIG_SWT2(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
+#define ADC_SWTRIG_SWT3_MASK                     (0x8U)
+#define ADC_SWTRIG_SWT3_SHIFT                    (3U)
+/*! SWT3 - Software trigger 3 event
+ *  0b0..No trigger 3 event generated.
+ *  0b1..Trigger 3 event generated.
+ */
+#define ADC_SWTRIG_SWT3(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
+/*! @} */
+
+/*! @name OFSTRIM - ADC Offset Trim Register */
+/*! @{ */
+#define ADC_OFSTRIM_OFSTRIM_MASK                 (0x3FU)
+#define ADC_OFSTRIM_OFSTRIM_SHIFT                (0U)
+#define ADC_OFSTRIM_OFSTRIM(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_SHIFT)) & ADC_OFSTRIM_OFSTRIM_MASK)
+/*! @} */
+
+/*! @name TCTRL - Trigger Control Register */
+/*! @{ */
+#define ADC_TCTRL_HTEN_MASK                      (0x1U)
+#define ADC_TCTRL_HTEN_SHIFT                     (0U)
+/*! HTEN - Trigger enable
+ *  0b0..Hardware trigger source disabled
+ *  0b1..Hardware trigger source enabled
+ */
+#define ADC_TCTRL_HTEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
+#define ADC_TCTRL_TPRI_MASK                      (0x300U)
+#define ADC_TCTRL_TPRI_SHIFT                     (8U)
+/*! TPRI - Trigger priority setting
+ *  0b00..Set to highest priority, Level 1
+ *  0b01-0b10..Set to corresponding priority level
+ *  0b11..Set to lowest priority, Level 4
+ */
+#define ADC_TCTRL_TPRI(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
+#define ADC_TCTRL_TDLY_MASK                      (0xF0000U)
+#define ADC_TCTRL_TDLY_SHIFT                     (16U)
+#define ADC_TCTRL_TDLY(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
+#define ADC_TCTRL_TCMD_MASK                      (0xF000000U)
+#define ADC_TCTRL_TCMD_SHIFT                     (24U)
+/*! TCMD - Trigger command select
+ *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
+ *  0b0001..CMD1 is executed
+ *  0b0010-0b1110..Corresponding CMD is executed
+ *  0b1111..CMD15 is executed
+ */
+#define ADC_TCTRL_TCMD(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
+/*! @} */
+
+/* The count of ADC_TCTRL */
+#define ADC_TCTRL_COUNT                          (4U)
+
+/*! @name CMDL - ADC Command Low Buffer Register */
+/*! @{ */
+#define ADC_CMDL_ADCH_MASK                       (0x1FU)
+#define ADC_CMDL_ADCH_SHIFT                      (0U)
+/*! ADCH - Input channel select
+ *  0b00000..Select CH0A or CH0B
+ *  0b00001..Select CH1A or CH1B
+ *  0b00010..Select CH2A or CH2B
+ *  0b00011..Select CH3A or CH3B
+ *  0b00100-0b11101..Select corresponding channel CHnA or CHnB
+ *  0b11110..Select CH30A or CH30B
+ *  0b11111..Select CH31A or CH31B
+ */
+#define ADC_CMDL_ADCH(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
+#define ADC_CMDL_ABSEL_MASK                      (0x20U)
+#define ADC_CMDL_ABSEL_SHIFT                     (5U)
+/*! ABSEL - A-side vs. B-side Select
+ *  0b0..The associated A-side channel is converted.
+ *  0b1..The associated B-side channel is converted.
+ */
+#define ADC_CMDL_ABSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)
+/*! @} */
+
+/* The count of ADC_CMDL */
+#define ADC_CMDL_COUNT                           (15U)
+
+/*! @name CMDH - ADC Command High Buffer Register */
+/*! @{ */
+#define ADC_CMDH_CMPEN_MASK                      (0x3U)
+#define ADC_CMDH_CMPEN_SHIFT                     (0U)
+/*! CMPEN - Compare Function Enable
+ *  0b00..Compare disabled.
+ *  0b01..Reserved
+ *  0b10..Compare enabled. Store on true.
+ *  0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
+ */
+#define ADC_CMDH_CMPEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
+#define ADC_CMDH_LWI_MASK                        (0x80U)
+#define ADC_CMDH_LWI_SHIFT                       (7U)
+/*! LWI - Loop with Increment
+ *  0b0..Auto channel increment disabled
+ *  0b1..Auto channel increment enabled
+ */
+#define ADC_CMDH_LWI(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
+#define ADC_CMDH_STS_MASK                        (0x700U)
+#define ADC_CMDH_STS_SHIFT                       (8U)
+/*! STS - Sample Time Select
+ *  0b000..Minimum sample time of 3 ADCK cycles.
+ *  0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
+ *  0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
+ *  0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
+ *  0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
+ *  0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
+ *  0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
+ *  0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
+ */
+#define ADC_CMDH_STS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
+#define ADC_CMDH_AVGS_MASK                       (0x7000U)
+#define ADC_CMDH_AVGS_SHIFT                      (12U)
+/*! AVGS - Hardware Average Select
+ *  0b000..Single conversion.
+ *  0b001..2 conversions averaged.
+ *  0b010..4 conversions averaged.
+ *  0b011..8 conversions averaged.
+ *  0b100..16 conversions averaged.
+ *  0b101..32 conversions averaged.
+ *  0b110..64 conversions averaged.
+ *  0b111..128 conversions averaged.
+ */
+#define ADC_CMDH_AVGS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
+#define ADC_CMDH_LOOP_MASK                       (0xF0000U)
+#define ADC_CMDH_LOOP_SHIFT                      (16U)
+/*! LOOP - Loop Count Select
+ *  0b0000..Looping not enabled. Command executes 1 time.
+ *  0b0001..Loop 1 time. Command executes 2 times.
+ *  0b0010..Loop 2 times. Command executes 3 times.
+ *  0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
+ *  0b1111..Loop 15 times. Command executes 16 times.
+ */
+#define ADC_CMDH_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
+#define ADC_CMDH_NEXT_MASK                       (0xF000000U)
+#define ADC_CMDH_NEXT_SHIFT                      (24U)
+/*! NEXT - Next Command Select
+ *  0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
+ *  0b0001..Select CMD1 command buffer register as next command.
+ *  0b0010-0b1110..Select corresponding CMD command buffer register as next command
+ *  0b1111..Select CMD15 command buffer register as next command.
+ */
+#define ADC_CMDH_NEXT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
+/*! @} */
+
+/* The count of ADC_CMDH */
+#define ADC_CMDH_COUNT                           (15U)
+
+/*! @name CV - Compare Value Register */
+/*! @{ */
+#define ADC_CV_CVL_MASK                          (0xFFFFU)
+#define ADC_CV_CVL_SHIFT                         (0U)
+#define ADC_CV_CVL(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
+#define ADC_CV_CVH_MASK                          (0xFFFF0000U)
+#define ADC_CV_CVH_SHIFT                         (16U)
+#define ADC_CV_CVH(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
+/*! @} */
+
+/* The count of ADC_CV */
+#define ADC_CV_COUNT                             (4U)
+
+/*! @name RESFIFO - ADC Data Result FIFO Register */
+/*! @{ */
+#define ADC_RESFIFO_D_MASK                       (0xFFFFU)
+#define ADC_RESFIFO_D_SHIFT                      (0U)
+#define ADC_RESFIFO_D(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
+#define ADC_RESFIFO_TSRC_MASK                    (0x30000U)
+#define ADC_RESFIFO_TSRC_SHIFT                   (16U)
+/*! TSRC - Trigger Source
+ *  0b00..Trigger source 0 initiated this conversion.
+ *  0b01..Trigger source 1 initiated this conversion.
+ *  0b10..Trigger source 2 initiated this conversion.
+ *  0b11..Trigger source 3 initiated this conversion.
+ */
+#define ADC_RESFIFO_TSRC(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
+#define ADC_RESFIFO_LOOPCNT_MASK                 (0xF00000U)
+#define ADC_RESFIFO_LOOPCNT_SHIFT                (20U)
+/*! LOOPCNT - Loop count value
+ *  0b0000..Result is from initial conversion in command.
+ *  0b0001..Result is from second conversion in command.
+ *  0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
+ *  0b1111..Result is from 16th conversion in command.
+ */
+#define ADC_RESFIFO_LOOPCNT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
+#define ADC_RESFIFO_CMDSRC_MASK                  (0xF000000U)
+#define ADC_RESFIFO_CMDSRC_SHIFT                 (24U)
+/*! CMDSRC - Command Buffer Source
+ *  0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
+ *  0b0001..CMD1 buffer used as control settings for this conversion.
+ *  0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
+ *  0b1111..CMD15 buffer used as control settings for this conversion.
+ */
+#define ADC_RESFIFO_CMDSRC(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
+#define ADC_RESFIFO_VALID_MASK                   (0x80000000U)
+#define ADC_RESFIFO_VALID_SHIFT                  (31U)
+/*! VALID - FIFO entry is valid
+ *  0b0..FIFO is empty. Discard any read from RESFIFO.
+ *  0b1..FIFO record read from RESFIFO is valid.
+ */
+#define ADC_RESFIFO_VALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x4004A000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS                           { ADC0_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS                            { ADC0 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS                                 { ADC0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- BTLE_RF Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup BTLE_RF_Peripheral_Access_Layer BTLE_RF Peripheral Access Layer
+ * @{
+ */
+
+/** BTLE_RF - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[1536];
+  __I  uint16_t BLE_PART_ID;                       /**< BLUETOOTH LOW ENERGY PART ID, offset: 0x600 */
+       uint8_t RESERVED_1[2];
+  __I  uint16_t DSM_STATUS;                        /**< BLE DSM STATUS, offset: 0x604 */
+       uint8_t RESERVED_2[2];
+  __IO uint16_t MISC_CTRL;                         /**< BLE MISCELLANEOUS CONTROL, offset: 0x608 */
+       uint8_t RESERVED_3[2];
+  __I  uint16_t BLE_FSM;                           /**< BLE STATE MACHINE STATUS, offset: 0x60C */
+} BTLE_RF_Type;
+
+/* ----------------------------------------------------------------------------
+   -- BTLE_RF Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup BTLE_RF_Register_Masks BTLE_RF Register Masks
+ * @{
+ */
+
+/*! @name BLE_PART_ID - BLUETOOTH LOW ENERGY PART ID */
+/*! @{ */
+#define BTLE_RF_BLE_PART_ID_BLE_PART_ID_MASK     (0xFFFFU)
+#define BTLE_RF_BLE_PART_ID_BLE_PART_ID_SHIFT    (0U)
+/*! BLE_PART_ID - BLE Part ID
+ *  0b0000000000000000..Pre-production
+ *  0b0000000000000001..Pre-production
+ *  0b0000000000000010..KW40
+ *  0b0000000000000011..KW41
+ *  0b0000000000000100..RV32M1
+ *  0b0000000000000101..KW35/KW36
+ */
+#define BTLE_RF_BLE_PART_ID_BLE_PART_ID(x)       (((uint16_t)(((uint16_t)(x)) << BTLE_RF_BLE_PART_ID_BLE_PART_ID_SHIFT)) & BTLE_RF_BLE_PART_ID_BLE_PART_ID_MASK)
+/*! @} */
+
+/*! @name DSM_STATUS - BLE DSM STATUS */
+/*! @{ */
+#define BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_MASK   (0x1U)
+#define BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_SHIFT  (0U)
+#define BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ(x)     (((uint16_t)(((uint16_t)(x)) << BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_SHIFT)) & BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_MASK)
+#define BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_MASK    (0x2U)
+#define BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_SHIFT   (1U)
+#define BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE(x)      (((uint16_t)(((uint16_t)(x)) << BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_SHIFT)) & BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_MASK)
+#define BTLE_RF_DSM_STATUS_XCVR_BUSY_MASK        (0x4U)
+#define BTLE_RF_DSM_STATUS_XCVR_BUSY_SHIFT       (2U)
+/*! XCVR_BUSY - Transceiver Busy Status Bit
+ *  0b0..RF Channel in available (TSM is idle)
+ *  0b1..RF Channel in use (TSM is busy)
+ */
+#define BTLE_RF_DSM_STATUS_XCVR_BUSY(x)          (((uint16_t)(((uint16_t)(x)) << BTLE_RF_DSM_STATUS_XCVR_BUSY_SHIFT)) & BTLE_RF_DSM_STATUS_XCVR_BUSY_MASK)
+/*! @} */
+
+/*! @name MISC_CTRL - BLE MISCELLANEOUS CONTROL */
+/*! @{ */
+#define BTLE_RF_MISC_CTRL_TSM_INTR_EN_MASK       (0x2U)
+#define BTLE_RF_MISC_CTRL_TSM_INTR_EN_SHIFT      (1U)
+#define BTLE_RF_MISC_CTRL_TSM_INTR_EN(x)         (((uint16_t)(((uint16_t)(x)) << BTLE_RF_MISC_CTRL_TSM_INTR_EN_SHIFT)) & BTLE_RF_MISC_CTRL_TSM_INTR_EN_MASK)
+#define BTLE_RF_MISC_CTRL_BLE_FSM_SEL_MASK       (0x1CU)
+#define BTLE_RF_MISC_CTRL_BLE_FSM_SEL_SHIFT      (2U)
+#define BTLE_RF_MISC_CTRL_BLE_FSM_SEL(x)         (((uint16_t)(((uint16_t)(x)) << BTLE_RF_MISC_CTRL_BLE_FSM_SEL_SHIFT)) & BTLE_RF_MISC_CTRL_BLE_FSM_SEL_MASK)
+/*! @} */
+
+/*! @name BLE_FSM - BLE STATE MACHINE STATUS */
+/*! @{ */
+#define BTLE_RF_BLE_FSM_VAR_CS_MASK              (0x1FU)
+#define BTLE_RF_BLE_FSM_VAR_CS_SHIFT             (0U)
+#define BTLE_RF_BLE_FSM_VAR_CS(x)                (((uint16_t)(((uint16_t)(x)) << BTLE_RF_BLE_FSM_VAR_CS_SHIFT)) & BTLE_RF_BLE_FSM_VAR_CS_MASK)
+#define BTLE_RF_BLE_FSM_BTLE_TX_EN_MASK          (0x20U)
+#define BTLE_RF_BLE_FSM_BTLE_TX_EN_SHIFT         (5U)
+#define BTLE_RF_BLE_FSM_BTLE_TX_EN(x)            (((uint16_t)(((uint16_t)(x)) << BTLE_RF_BLE_FSM_BTLE_TX_EN_SHIFT)) & BTLE_RF_BLE_FSM_BTLE_TX_EN_MASK)
+#define BTLE_RF_BLE_FSM_BTLE_RX_EN_MASK          (0x40U)
+#define BTLE_RF_BLE_FSM_BTLE_RX_EN_SHIFT         (6U)
+#define BTLE_RF_BLE_FSM_BTLE_RX_EN(x)            (((uint16_t)(((uint16_t)(x)) << BTLE_RF_BLE_FSM_BTLE_RX_EN_SHIFT)) & BTLE_RF_BLE_FSM_BTLE_RX_EN_MASK)
+#define BTLE_RF_BLE_FSM_TX_CS_MASK               (0xF80U)
+#define BTLE_RF_BLE_FSM_TX_CS_SHIFT              (7U)
+#define BTLE_RF_BLE_FSM_TX_CS(x)                 (((uint16_t)(((uint16_t)(x)) << BTLE_RF_BLE_FSM_TX_CS_SHIFT)) & BTLE_RF_BLE_FSM_TX_CS_MASK)
+#define BTLE_RF_BLE_FSM_RX_CS_MASK               (0xF000U)
+#define BTLE_RF_BLE_FSM_RX_CS_SHIFT              (12U)
+#define BTLE_RF_BLE_FSM_RX_CS(x)                 (((uint16_t)(((uint16_t)(x)) << BTLE_RF_BLE_FSM_RX_CS_SHIFT)) & BTLE_RF_BLE_FSM_RX_CS_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group BTLE_RF_Register_Masks */
+
+
+/* BTLE_RF - Peripheral instance base addresses */
+/** Peripheral BTLE_RF base address */
+#define BTLE_RF_BASE                             (0x41032000u)
+/** Peripheral BTLE_RF base pointer */
+#define BTLE_RF                                  ((BTLE_RF_Type *)BTLE_RF_BASE)
+/** Array initializer of BTLE_RF peripheral base addresses */
+#define BTLE_RF_BASE_ADDRS                       { BTLE_RF_BASE }
+/** Array initializer of BTLE_RF peripheral base pointers */
+#define BTLE_RF_BASE_PTRS                        { BTLE_RF }
+
+/*!
+ * @}
+ */ /* end of group BTLE_RF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAU3 Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU3_Peripheral_Access_Layer CAU3 Peripheral Access Layer
+ * @{
+ */
+
+/** CAU3 - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t PCT;                               /**< Processor Core Type, offset: 0x0 */
+  __I  uint32_t MCFG;                              /**< Memory Configuration, offset: 0x4 */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t CR;                                /**< Control Register, offset: 0x10 */
+  __IO uint32_t SR;                                /**< Status Register, offset: 0x14 */
+       uint8_t RESERVED_1[8];
+  __IO uint32_t DBGCSR;                            /**< Debug Control/Status Register, offset: 0x20 */
+  __IO uint32_t DBGPBR;                            /**< Debug PC Breakpoint Register, offset: 0x24 */
+       uint8_t RESERVED_2[8];
+  __IO uint32_t DBGMCMD;                           /**< Debug Memory Command Register, offset: 0x30 */
+  __IO uint32_t DBGMADR;                           /**< Debug Memory Address Register, offset: 0x34 */
+  __IO uint32_t DBGMDR;                            /**< Debug Memory Data Register, offset: 0x38 */
+       uint8_t RESERVED_3[180];
+  __IO uint32_t SEMA4;                             /**< Semaphore Register, offset: 0xF0 */
+  __I  uint32_t SMOWNR;                            /**< Semaphore Ownership Register, offset: 0xF4 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t ARR;                               /**< Address Remap Register, offset: 0xFC */
+       uint8_t RESERVED_5[128];
+  __IO uint32_t CC_R[30];                          /**< CryptoCore General Purpose Registers, array offset: 0x180, array step: 0x4 */
+  __IO uint32_t CC_R30;                            /**< General Purpose R30, offset: 0x1F8 */
+  __IO uint32_t CC_R31;                            /**< General Purpose R31, offset: 0x1FC */
+  __IO uint32_t CC_PC;                             /**< Program Counter, offset: 0x200 */
+  __O  uint32_t CC_CMD;                            /**< Start Command Register, offset: 0x204 */
+  __I  uint32_t CC_CF;                             /**< Condition Flag, offset: 0x208 */
+       uint8_t RESERVED_6[500];
+  __IO uint32_t MDPK;                              /**< Mode Register (PublicKey), offset: 0x400 */
+       uint8_t RESERVED_7[44];
+  __O  uint32_t COM;                               /**< Command Register, offset: 0x430 */
+  __IO uint32_t CTL;                               /**< Control Register, offset: 0x434 */
+       uint8_t RESERVED_8[8];
+  __O  uint32_t CW;                                /**< Clear Written Register, offset: 0x440 */
+       uint8_t RESERVED_9[4];
+  __IO uint32_t STA;                               /**< Status Register, offset: 0x448 */
+  __I  uint32_t ESTA;                              /**< Error Status Register, offset: 0x44C */
+       uint8_t RESERVED_10[48];
+  __IO uint32_t PKASZ;                             /**< PKHA A Size Register, offset: 0x480 */
+       uint8_t RESERVED_11[4];
+  __IO uint32_t PKBSZ;                             /**< PKHA B Size Register, offset: 0x488 */
+       uint8_t RESERVED_12[4];
+  __IO uint32_t PKNSZ;                             /**< PKHA N Size Register, offset: 0x490 */
+       uint8_t RESERVED_13[4];
+  __IO uint32_t PKESZ;                             /**< PKHA E Size Register, offset: 0x498 */
+       uint8_t RESERVED_14[84];
+  __I  uint32_t PKHA_VID1;                         /**< PKHA Revision ID 1, offset: 0x4F0 */
+  __I  uint32_t PKHA_VID2;                         /**< PKHA Revision ID 2, offset: 0x4F4 */
+  __I  uint32_t CHA_VID;                           /**< CHA Revision ID, offset: 0x4F8 */
+       uint8_t RESERVED_15[260];
+  __IO uint32_t PKHA_CCR;                          /**< PKHA Clock Control Register, offset: 0x600 */
+  __I  uint32_t GSR;                               /**< Global Status Register, offset: 0x604 */
+  __IO uint32_t CKLFSR;                            /**< Clock Linear Feedback Shift Register, offset: 0x608 */
+       uint8_t RESERVED_16[500];
+  __IO uint32_t PKA0[32];                          /**< PKHA A0 Register, array offset: 0x800, array step: 0x4 */
+  __IO uint32_t PKA1[32];                          /**< PKHA A1 Register, array offset: 0x880, array step: 0x4 */
+  __IO uint32_t PKA2[32];                          /**< PKHA A2 Register, array offset: 0x900, array step: 0x4 */
+  __IO uint32_t PKA3[32];                          /**< PKHA A3 Register, array offset: 0x980, array step: 0x4 */
+  __IO uint32_t PKB0[32];                          /**< PKHA B0 Register, array offset: 0xA00, array step: 0x4 */
+  __IO uint32_t PKB1[32];                          /**< PKHA B1 Register, array offset: 0xA80, array step: 0x4 */
+  __IO uint32_t PKB2[32];                          /**< PKHA B2 Register, array offset: 0xB00, array step: 0x4 */
+  __IO uint32_t PKB3[32];                          /**< PKHA B3 Register, array offset: 0xB80, array step: 0x4 */
+  __IO uint32_t PKN0[32];                          /**< PKHA N0 Register, array offset: 0xC00, array step: 0x4 */
+  __IO uint32_t PKN1[32];                          /**< PKHA N1 Register, array offset: 0xC80, array step: 0x4 */
+  __IO uint32_t PKN2[32];                          /**< PKHA N2 Register, array offset: 0xD00, array step: 0x4 */
+  __IO uint32_t PKN3[32];                          /**< PKHA N3 Register, array offset: 0xD80, array step: 0x4 */
+  __O  uint32_t PKE[128];                          /**< PKHA E Register, array offset: 0xE00, array step: 0x4 */
+} CAU3_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CAU3 Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU3_Register_Masks CAU3 Register Masks
+ * @{
+ */
+
+/*! @name PCT - Processor Core Type */
+/*! @{ */
+#define CAU3_PCT_Y_MASK                          (0xFU)
+#define CAU3_PCT_Y_SHIFT                         (0U)
+/*! Y - Minor version number
+ *  0b0000..Minor version number
+ */
+#define CAU3_PCT_Y(x)                            (((uint32_t)(((uint32_t)(x)) << CAU3_PCT_Y_SHIFT)) & CAU3_PCT_Y_MASK)
+#define CAU3_PCT_X_MASK                          (0xF0U)
+#define CAU3_PCT_X_SHIFT                         (4U)
+/*! X - Major version number
+ *  0b0000..Major version number
+ */
+#define CAU3_PCT_X(x)                            (((uint32_t)(((uint32_t)(x)) << CAU3_PCT_X_SHIFT)) & CAU3_PCT_X_MASK)
+#define CAU3_PCT_ID_MASK                         (0xFFFFFF00U)
+#define CAU3_PCT_ID_SHIFT                        (8U)
+/*! ID - Module ID number
+ *  0b010010110100000101100000..ID number for basic configuration
+ *  0b010010110100000101100001..ID number for PKHA configuration
+ */
+#define CAU3_PCT_ID(x)                           (((uint32_t)(((uint32_t)(x)) << CAU3_PCT_ID_SHIFT)) & CAU3_PCT_ID_MASK)
+/*! @} */
+
+/*! @name MCFG - Memory Configuration */
+/*! @{ */
+#define CAU3_MCFG_DRAM_SZ_MASK                   (0xF00U)
+#define CAU3_MCFG_DRAM_SZ_SHIFT                  (8U)
+/*! DRAM_SZ - Data RAM Size
+ *  0b0000..No memory module
+ *  0b0100..2K bytes
+ *  0b0101..3K bytes
+ *  0b0110..4K bytes
+ *  0b0111..6K bytes
+ *  0b1000..8K bytes
+ *  0b1001..12K bytes
+ *  0b1010..16K bytes
+ *  0b1011..24K bytes
+ *  0b1100..32K bytes
+ *  0b1101..48K bytes
+ *  0b1110..64K bytes
+ *  0b1111..96K bytes
+ */
+#define CAU3_MCFG_DRAM_SZ(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_MCFG_DRAM_SZ_SHIFT)) & CAU3_MCFG_DRAM_SZ_MASK)
+#define CAU3_MCFG_IROM_SZ_MASK                   (0xF0000U)
+#define CAU3_MCFG_IROM_SZ_SHIFT                  (16U)
+/*! IROM_SZ - Instruction ROM Size
+ *  0b0000..No memory module
+ *  0b0100..2K bytes
+ *  0b0101..3K bytes
+ *  0b0110..4K bytes
+ *  0b0111..6K bytes
+ *  0b1000..8K bytes
+ *  0b1001..12K bytes
+ *  0b1010..16K bytes
+ *  0b1011..24K bytes
+ *  0b1100..32K bytes
+ *  0b1101..48K bytes
+ *  0b1110..64K bytes
+ *  0b1111..96K bytes
+ */
+#define CAU3_MCFG_IROM_SZ(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_MCFG_IROM_SZ_SHIFT)) & CAU3_MCFG_IROM_SZ_MASK)
+#define CAU3_MCFG_IRAM_SZ_MASK                   (0xF000000U)
+#define CAU3_MCFG_IRAM_SZ_SHIFT                  (24U)
+/*! IRAM_SZ - Instruction RAM Size
+ *  0b0000..No memory module
+ *  0b0100..2K bytes
+ *  0b0101..3K bytes
+ *  0b0110..4K bytes
+ *  0b0111..6K bytes
+ *  0b1000..8K bytes
+ *  0b1001..12K bytes
+ *  0b1010..16K bytes
+ *  0b1011..24K bytes
+ *  0b1100..32K bytes
+ *  0b1101..48K bytes
+ *  0b1110..64K bytes
+ *  0b1111..96K bytes
+ */
+#define CAU3_MCFG_IRAM_SZ(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_MCFG_IRAM_SZ_SHIFT)) & CAU3_MCFG_IRAM_SZ_MASK)
+/*! @} */
+
+/*! @name CR - Control Register */
+/*! @{ */
+#define CAU3_CR_TCSEIE_MASK                      (0x1U)
+#define CAU3_CR_TCSEIE_SHIFT                     (0U)
+/*! TCSEIE - Task completion with software error interrupt enable
+ *  0b0..Disables task completion with software error to generate an interrupt request
+ *  0b1..Enables task completion with software error to generate an interrupt request
+ */
+#define CAU3_CR_TCSEIE(x)                        (((uint32_t)(((uint32_t)(x)) << CAU3_CR_TCSEIE_SHIFT)) & CAU3_CR_TCSEIE_MASK)
+#define CAU3_CR_ILLIE_MASK                       (0x2U)
+#define CAU3_CR_ILLIE_SHIFT                      (1U)
+/*! ILLIE - Illegal Instruction Interrupt Enable
+ *  0b0..Illegal instruction interrupt requests are disabled
+ *  0b1..illegal Instruction interrupt requests are enabled
+ */
+#define CAU3_CR_ILLIE(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_CR_ILLIE_SHIFT)) & CAU3_CR_ILLIE_MASK)
+#define CAU3_CR_ASREIE_MASK                      (0x8U)
+#define CAU3_CR_ASREIE_SHIFT                     (3U)
+/*! ASREIE - AHB Slave Response Error Interrupt Enable
+ *  0b0..AHB slave response error interruption is not enabled
+ *  0b1..AHB slave response error interruption is enabled
+ */
+#define CAU3_CR_ASREIE(x)                        (((uint32_t)(((uint32_t)(x)) << CAU3_CR_ASREIE_SHIFT)) & CAU3_CR_ASREIE_MASK)
+#define CAU3_CR_IIADIE_MASK                      (0x10U)
+#define CAU3_CR_IIADIE_SHIFT                     (4U)
+/*! IIADIE - IMEM Illegal Address Interrupt Enable
+ *  0b0..IMEM illegal address interruption is not enabled
+ *  0b1..IMEM illegal address interruption is enabled
+ */
+#define CAU3_CR_IIADIE(x)                        (((uint32_t)(((uint32_t)(x)) << CAU3_CR_IIADIE_SHIFT)) & CAU3_CR_IIADIE_MASK)
+#define CAU3_CR_DIADIE_MASK                      (0x20U)
+#define CAU3_CR_DIADIE_SHIFT                     (5U)
+/*! DIADIE - DMEM Illegal Address Interrupt Enable
+ *  0b0..DMEM illegal address interruption is not enabled
+ *  0b1..DMEM illegal address interruption is enabled
+ */
+#define CAU3_CR_DIADIE(x)                        (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DIADIE_SHIFT)) & CAU3_CR_DIADIE_MASK)
+#define CAU3_CR_SVIE_MASK                        (0x40U)
+#define CAU3_CR_SVIE_SHIFT                       (6U)
+/*! SVIE - Security Violation Interrupt Enable
+ *  0b0..Security violation interruption is not enabled
+ *  0b1..Security violation interruption is enabled
+ */
+#define CAU3_CR_SVIE(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CR_SVIE_SHIFT)) & CAU3_CR_SVIE_MASK)
+#define CAU3_CR_TCIE_MASK                        (0x80U)
+#define CAU3_CR_TCIE_SHIFT                       (7U)
+/*! TCIE - Task completion with no error interrupt enable
+ *  0b0..Disables task completion with no error to generate an interrupt request
+ *  0b1..Enables task completion with no error to generate an interrupt request
+ */
+#define CAU3_CR_TCIE(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CR_TCIE_SHIFT)) & CAU3_CR_TCIE_MASK)
+#define CAU3_CR_RSTSM4_MASK                      (0x3000U)
+#define CAU3_CR_RSTSM4_SHIFT                     (12U)
+/*! RSTSM4 - Reset Semaphore
+ *  0b00..Idle state
+ *  0b01..Wait for second write
+ *  0b10..Clears semaphore if previous state was "01"
+ *  0b11..Reserved
+ */
+#define CAU3_CR_RSTSM4(x)                        (((uint32_t)(((uint32_t)(x)) << CAU3_CR_RSTSM4_SHIFT)) & CAU3_CR_RSTSM4_MASK)
+#define CAU3_CR_MRST_MASK                        (0x8000U)
+#define CAU3_CR_MRST_SHIFT                       (15U)
+/*! MRST - Module Reset
+ *  0b0..no action
+ *  0b1..reset
+ */
+#define CAU3_CR_MRST(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CR_MRST_SHIFT)) & CAU3_CR_MRST_MASK)
+#define CAU3_CR_FSV_MASK                         (0x10000U)
+#define CAU3_CR_FSV_SHIFT                        (16U)
+/*! FSV - Force Security Violation Test
+ *  0b0..no violation is forced
+ *  0b1..force security violation
+ */
+#define CAU3_CR_FSV(x)                           (((uint32_t)(((uint32_t)(x)) << CAU3_CR_FSV_SHIFT)) & CAU3_CR_FSV_MASK)
+#define CAU3_CR_DTCCFG_MASK                      (0x7000000U)
+#define CAU3_CR_DTCCFG_SHIFT                     (24U)
+/*! DTCCFG - Default Task Completion Configuration
+ *  0b100..Issue a DMA request
+ *  0b010..Assert Event Completion Signal
+ *  0b001..Issue an Interrupt Request
+ *  0b000..no explicit action
+ */
+#define CAU3_CR_DTCCFG(x)                        (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DTCCFG_SHIFT)) & CAU3_CR_DTCCFG_MASK)
+#define CAU3_CR_DSHFI_MASK                       (0x10000000U)
+#define CAU3_CR_DSHFI_SHIFT                      (28U)
+/*! DSHFI - Disable Secure Hash Function Instructions
+ *  0b0..Secure Hash Functions are enabled
+ *  0b1..Secure Hash Functions are disabled
+ */
+#define CAU3_CR_DSHFI(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DSHFI_SHIFT)) & CAU3_CR_DSHFI_MASK)
+#define CAU3_CR_DDESI_MASK                       (0x20000000U)
+#define CAU3_CR_DDESI_SHIFT                      (29U)
+/*! DDESI - Disable DES Instructions
+ *  0b0..DES instructions are enabled
+ *  0b1..DES instructions are disabled
+ */
+#define CAU3_CR_DDESI(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DDESI_SHIFT)) & CAU3_CR_DDESI_MASK)
+#define CAU3_CR_DAESI_MASK                       (0x40000000U)
+#define CAU3_CR_DAESI_SHIFT                      (30U)
+/*! DAESI - Disable AES Instructions
+ *  0b0..AES instructions are enabled
+ *  0b1..AES instructions are disabled
+ */
+#define CAU3_CR_DAESI(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_CR_DAESI_SHIFT)) & CAU3_CR_DAESI_MASK)
+#define CAU3_CR_MDIS_MASK                        (0x80000000U)
+#define CAU3_CR_MDIS_SHIFT                       (31U)
+/*! MDIS - Module Disable
+ *  0b0..CAU3 exits from low power mode
+ *  0b1..CAU3 enters low power mode
+ */
+#define CAU3_CR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CR_MDIS_SHIFT)) & CAU3_CR_MDIS_MASK)
+/*! @} */
+
+/*! @name SR - Status Register */
+/*! @{ */
+#define CAU3_SR_TCSEIRQ_MASK                     (0x1U)
+#define CAU3_SR_TCSEIRQ_SHIFT                    (0U)
+/*! TCSEIRQ - Task completion with software error interrupt request
+ *  0b0..Task not finished or finished with no software error
+ *  0b1..Task execution finished with software error
+ */
+#define CAU3_SR_TCSEIRQ(x)                       (((uint32_t)(((uint32_t)(x)) << CAU3_SR_TCSEIRQ_SHIFT)) & CAU3_SR_TCSEIRQ_MASK)
+#define CAU3_SR_ILLIRQ_MASK                      (0x2U)
+#define CAU3_SR_ILLIRQ_SHIFT                     (1U)
+/*! ILLIRQ - Illegal instruction interrupt request
+ *  0b0..no error
+ *  0b1..illegal instruction detected
+ */
+#define CAU3_SR_ILLIRQ(x)                        (((uint32_t)(((uint32_t)(x)) << CAU3_SR_ILLIRQ_SHIFT)) & CAU3_SR_ILLIRQ_MASK)
+#define CAU3_SR_ASREIRQ_MASK                     (0x8U)
+#define CAU3_SR_ASREIRQ_SHIFT                    (3U)
+/*! ASREIRQ - AHB slave response error interrupt Request
+ *  0b0..no error
+ *  0b1..AHB slave response error detected
+ */
+#define CAU3_SR_ASREIRQ(x)                       (((uint32_t)(((uint32_t)(x)) << CAU3_SR_ASREIRQ_SHIFT)) & CAU3_SR_ASREIRQ_MASK)
+#define CAU3_SR_IIADIRQ_MASK                     (0x10U)
+#define CAU3_SR_IIADIRQ_SHIFT                    (4U)
+/*! IIADIRQ - IMEM Illegal address interrupt request
+ *  0b0..no error
+ *  0b1..illegal IMEM address detected
+ */
+#define CAU3_SR_IIADIRQ(x)                       (((uint32_t)(((uint32_t)(x)) << CAU3_SR_IIADIRQ_SHIFT)) & CAU3_SR_IIADIRQ_MASK)
+#define CAU3_SR_DIADIRQ_MASK                     (0x20U)
+#define CAU3_SR_DIADIRQ_SHIFT                    (5U)
+/*! DIADIRQ - DMEM illegal access interrupt request
+ *  0b0..no illegal address
+ *  0b1..illegal address
+ */
+#define CAU3_SR_DIADIRQ(x)                       (((uint32_t)(((uint32_t)(x)) << CAU3_SR_DIADIRQ_SHIFT)) & CAU3_SR_DIADIRQ_MASK)
+#define CAU3_SR_SVIRQ_MASK                       (0x40U)
+#define CAU3_SR_SVIRQ_SHIFT                      (6U)
+/*! SVIRQ - Security violation interrupt request
+ *  0b0..No security violation
+ *  0b1..Security violation
+ */
+#define CAU3_SR_SVIRQ(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_SR_SVIRQ_SHIFT)) & CAU3_SR_SVIRQ_MASK)
+#define CAU3_SR_TCIRQ_MASK                       (0x80U)
+#define CAU3_SR_TCIRQ_SHIFT                      (7U)
+/*! TCIRQ - Task completion with no error interrupt request
+ *  0b0..Task not finished or finished with error
+ *  0b1..Task execution finished with no error
+ */
+#define CAU3_SR_TCIRQ(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_SR_TCIRQ_SHIFT)) & CAU3_SR_TCIRQ_MASK)
+#define CAU3_SR_TKCS_MASK                        (0xF00U)
+#define CAU3_SR_TKCS_SHIFT                       (8U)
+/*! TKCS - Task completion status
+ *  0b0000..Initialization RUN
+ *  0b0001..Running
+ *  0b0010..Debug Halted
+ *  0b1001..Stop - Error Free
+ *  0b1010..Stop - Error
+ *  0b1110..Stop - Security Violation, assert security violation output signal and set SVIRQ
+ *  0b1111..Stop - Security Violation and set SVIRQ
+ */
+#define CAU3_SR_TKCS(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_SR_TKCS_SHIFT)) & CAU3_SR_TKCS_MASK)
+#define CAU3_SR_SVF_MASK                         (0x10000U)
+#define CAU3_SR_SVF_SHIFT                        (16U)
+/*! SVF - Security violation flag
+ *  0b0..SoC security violation is not asserted
+ *  0b1..SoC security violation was asserted
+ */
+#define CAU3_SR_SVF(x)                           (((uint32_t)(((uint32_t)(x)) << CAU3_SR_SVF_SHIFT)) & CAU3_SR_SVF_MASK)
+#define CAU3_SR_DBG_MASK                         (0x20000U)
+#define CAU3_SR_DBG_SHIFT                        (17U)
+/*! DBG - Debug mode
+ *  0b0..CAU3 is not in debug mode
+ *  0b1..CAU3 is in debug mode
+ */
+#define CAU3_SR_DBG(x)                           (((uint32_t)(((uint32_t)(x)) << CAU3_SR_DBG_SHIFT)) & CAU3_SR_DBG_MASK)
+#define CAU3_SR_TCCFG_MASK                       (0x7000000U)
+#define CAU3_SR_TCCFG_SHIFT                      (24U)
+/*! TCCFG - Task completion configuration
+ *  0b100..Issue a DMA request
+ *  0b010..Assert the Event Completion Signal
+ *  0b001..Assert an interrupt request
+ *  0b000..No action
+ */
+#define CAU3_SR_TCCFG(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_SR_TCCFG_SHIFT)) & CAU3_SR_TCCFG_MASK)
+#define CAU3_SR_MDISF_MASK                       (0x80000000U)
+#define CAU3_SR_MDISF_SHIFT                      (31U)
+/*! MDISF - Module disable flag
+ *  0b0..CCore is not in low power mode
+ *  0b1..CCore is in low power mode
+ */
+#define CAU3_SR_MDISF(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_SR_MDISF_SHIFT)) & CAU3_SR_MDISF_MASK)
+/*! @} */
+
+/*! @name DBGCSR - Debug Control/Status Register */
+/*! @{ */
+#define CAU3_DBGCSR_DDBG_MASK                    (0x1U)
+#define CAU3_DBGCSR_DDBG_SHIFT                   (0U)
+/*! DDBG - Debug Disable
+ *  0b0..debug is enabled
+ *  0b1..debug is disabled
+ */
+#define CAU3_DBGCSR_DDBG(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_DDBG_SHIFT)) & CAU3_DBGCSR_DDBG_MASK)
+#define CAU3_DBGCSR_DDBGMC_MASK                  (0x2U)
+#define CAU3_DBGCSR_DDBGMC_SHIFT                 (1U)
+/*! DDBGMC - Disable Debug Memory Commands
+ *  0b0..IPS access to IMEM and DMEM are enabled
+ *  0b1..IPS access to IMEM and DMEM are disabled
+ */
+#define CAU3_DBGCSR_DDBGMC(x)                    (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_DDBGMC_SHIFT)) & CAU3_DBGCSR_DDBGMC_MASK)
+#define CAU3_DBGCSR_PBREN_MASK                   (0x10U)
+#define CAU3_DBGCSR_PBREN_SHIFT                  (4U)
+/*! PBREN - PC Breakpoint Register Enable
+ *  0b0..PC breakpoint register (DBGPBR) is disabled
+ *  0b1..PC breakpoint register (DBGPBR) is enabled
+ */
+#define CAU3_DBGCSR_PBREN(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_PBREN_SHIFT)) & CAU3_DBGCSR_PBREN_MASK)
+#define CAU3_DBGCSR_SIM_MASK                     (0x20U)
+#define CAU3_DBGCSR_SIM_SHIFT                    (5U)
+/*! SIM - Single Instruction Mode
+ *  0b0..Single instruction mode is disabled
+ *  0b1..Single instruction mode is enabled
+ */
+#define CAU3_DBGCSR_SIM(x)                       (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_SIM_SHIFT)) & CAU3_DBGCSR_SIM_MASK)
+#define CAU3_DBGCSR_FRCH_MASK                    (0x100U)
+#define CAU3_DBGCSR_FRCH_SHIFT                   (8U)
+/*! FRCH - Force Debug Halt
+ *  0b0..Halt state not forced
+ *  0b1..Force halt state
+ */
+#define CAU3_DBGCSR_FRCH(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_FRCH_SHIFT)) & CAU3_DBGCSR_FRCH_MASK)
+#define CAU3_DBGCSR_DBGGO_MASK                   (0x1000U)
+#define CAU3_DBGCSR_DBGGO_SHIFT                  (12U)
+/*! DBGGO - Debug Go
+ *  0b0..No action
+ *  0b1..Resume program execution
+ */
+#define CAU3_DBGCSR_DBGGO(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_DBGGO_SHIFT)) & CAU3_DBGCSR_DBGGO_MASK)
+#define CAU3_DBGCSR_PCBHF_MASK                   (0x10000U)
+#define CAU3_DBGCSR_PCBHF_SHIFT                  (16U)
+/*! PCBHF - CryptoCore is Halted due to Hardware Breakpoint
+ *  0b0..CryptoCore is not halted due to a hardware breakpoint
+ *  0b1..CryptoCore is halted due to a hardware breakpoint
+ */
+#define CAU3_DBGCSR_PCBHF(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_PCBHF_SHIFT)) & CAU3_DBGCSR_PCBHF_MASK)
+#define CAU3_DBGCSR_SIMHF_MASK                   (0x20000U)
+#define CAU3_DBGCSR_SIMHF_SHIFT                  (17U)
+/*! SIMHF - CryptoCore is Halted due to Single Instruction Step
+ *  0b0..CryptoCore is not in a single step halt
+ *  0b1..CryptoCore is in a single step halt
+ */
+#define CAU3_DBGCSR_SIMHF(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_SIMHF_SHIFT)) & CAU3_DBGCSR_SIMHF_MASK)
+#define CAU3_DBGCSR_HLTIF_MASK                   (0x40000U)
+#define CAU3_DBGCSR_HLTIF_SHIFT                  (18U)
+/*! HLTIF - CryptoCore is Halted due to HALT Instruction
+ *  0b0..CryptoCore is not in software breakpoint
+ *  0b1..CryptoCore is in software breakpoint
+ */
+#define CAU3_DBGCSR_HLTIF(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_HLTIF_SHIFT)) & CAU3_DBGCSR_HLTIF_MASK)
+#define CAU3_DBGCSR_CSTPF_MASK                   (0x40000000U)
+#define CAU3_DBGCSR_CSTPF_SHIFT                  (30U)
+/*! CSTPF - CryptoCore is Stopped Status Flag
+ *  0b0..CryptoCore is not stopped
+ *  0b1..CryptoCore is stopped
+ */
+#define CAU3_DBGCSR_CSTPF(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_CSTPF_SHIFT)) & CAU3_DBGCSR_CSTPF_MASK)
+#define CAU3_DBGCSR_CHLTF_MASK                   (0x80000000U)
+#define CAU3_DBGCSR_CHLTF_SHIFT                  (31U)
+/*! CHLTF - CryptoCore is Halted Status Flag
+ *  0b0..CryptoCore is not halted
+ *  0b1..CryptoCore is halted
+ */
+#define CAU3_DBGCSR_CHLTF(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_DBGCSR_CHLTF_SHIFT)) & CAU3_DBGCSR_CHLTF_MASK)
+/*! @} */
+
+/*! @name DBGPBR - Debug PC Breakpoint Register */
+/*! @{ */
+#define CAU3_DBGPBR_PCBKPT_MASK                  (0xFFFFCU)
+#define CAU3_DBGPBR_PCBKPT_SHIFT                 (2U)
+#define CAU3_DBGPBR_PCBKPT(x)                    (((uint32_t)(((uint32_t)(x)) << CAU3_DBGPBR_PCBKPT_SHIFT)) & CAU3_DBGPBR_PCBKPT_MASK)
+/*! @} */
+
+/*! @name DBGMCMD - Debug Memory Command Register */
+/*! @{ */
+#define CAU3_DBGMCMD_DM_MASK                     (0x1000000U)
+#define CAU3_DBGMCMD_DM_SHIFT                    (24U)
+/*! DM - Instruction/Data Memory Selection
+ *  0b0..IMEM is selected
+ *  0b1..DMEM is selected
+ */
+#define CAU3_DBGMCMD_DM(x)                       (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_DM_SHIFT)) & CAU3_DBGMCMD_DM_MASK)
+#define CAU3_DBGMCMD_IA_MASK                     (0x4000000U)
+#define CAU3_DBGMCMD_IA_SHIFT                    (26U)
+/*! IA - Increment Address
+ *  0b0..Address is not incremented
+ *  0b1..Address is incremented after the access
+ */
+#define CAU3_DBGMCMD_IA(x)                       (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_IA_SHIFT)) & CAU3_DBGMCMD_IA_MASK)
+#define CAU3_DBGMCMD_Rb_1_MASK                   (0x8000000U)
+#define CAU3_DBGMCMD_Rb_1_SHIFT                  (27U)
+#define CAU3_DBGMCMD_Rb_1(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_Rb_1_SHIFT)) & CAU3_DBGMCMD_Rb_1_MASK)
+#define CAU3_DBGMCMD_BV_MASK                     (0x10000000U)
+#define CAU3_DBGMCMD_BV_SHIFT                    (28U)
+/*! BV - Byte Reversal Control
+ *  0b0..DMEM bytes are not reversed
+ *  0b1..DMEM bytes are reversed
+ */
+#define CAU3_DBGMCMD_BV(x)                       (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_BV_SHIFT)) & CAU3_DBGMCMD_BV_MASK)
+#define CAU3_DBGMCMD_R_0_MASK                    (0x40000000U)
+#define CAU3_DBGMCMD_R_0_SHIFT                   (30U)
+#define CAU3_DBGMCMD_R_0(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_R_0_SHIFT)) & CAU3_DBGMCMD_R_0_MASK)
+#define CAU3_DBGMCMD_R_1_MASK                    (0x80000000U)
+#define CAU3_DBGMCMD_R_1_SHIFT                   (31U)
+#define CAU3_DBGMCMD_R_1(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMCMD_R_1_SHIFT)) & CAU3_DBGMCMD_R_1_MASK)
+/*! @} */
+
+/*! @name DBGMADR - Debug Memory Address Register */
+/*! @{ */
+#define CAU3_DBGMADR_DMADDR_MASK                 (0xFFFFFFFCU)
+#define CAU3_DBGMADR_DMADDR_SHIFT                (2U)
+#define CAU3_DBGMADR_DMADDR(x)                   (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMADR_DMADDR_SHIFT)) & CAU3_DBGMADR_DMADDR_MASK)
+/*! @} */
+
+/*! @name DBGMDR - Debug Memory Data Register */
+/*! @{ */
+#define CAU3_DBGMDR_DMDATA_MASK                  (0xFFFFFFFFU)
+#define CAU3_DBGMDR_DMDATA_SHIFT                 (0U)
+#define CAU3_DBGMDR_DMDATA(x)                    (((uint32_t)(((uint32_t)(x)) << CAU3_DBGMDR_DMDATA_SHIFT)) & CAU3_DBGMDR_DMDATA_MASK)
+/*! @} */
+
+/*! @name SEMA4 - Semaphore Register */
+/*! @{ */
+#define CAU3_SEMA4_DID_MASK                      (0xFU)
+#define CAU3_SEMA4_DID_SHIFT                     (0U)
+#define CAU3_SEMA4_DID(x)                        (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_DID_SHIFT)) & CAU3_SEMA4_DID_MASK)
+#define CAU3_SEMA4_PR_MASK                       (0x40U)
+#define CAU3_SEMA4_PR_SHIFT                      (6U)
+/*! PR - Privilege Attribute of Locked Semaphore Owner
+ *  0b0..If semaphore is locked, then owner is operating in user mode
+ *  0b1..If semaphore is locked, then owner is operating in privileged mode
+ */
+#define CAU3_SEMA4_PR(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_PR_SHIFT)) & CAU3_SEMA4_PR_MASK)
+#define CAU3_SEMA4_NS_MASK                       (0x80U)
+#define CAU3_SEMA4_NS_SHIFT                      (7U)
+/*! NS - Non Secure Attribute of the Locked Semaphore Owner
+ *  0b0..If semaphore is locked, owner is operating in secure mode
+ *  0b1..If semaphore is locked, owner is operating in nonsecure mode
+ */
+#define CAU3_SEMA4_NS(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_NS_SHIFT)) & CAU3_SEMA4_NS_MASK)
+#define CAU3_SEMA4_MSTRN_MASK                    (0x3F00U)
+#define CAU3_SEMA4_MSTRN_SHIFT                   (8U)
+#define CAU3_SEMA4_MSTRN(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_MSTRN_SHIFT)) & CAU3_SEMA4_MSTRN_MASK)
+#define CAU3_SEMA4_LK_MASK                       (0x80000000U)
+#define CAU3_SEMA4_LK_SHIFT                      (31U)
+/*! LK - Semaphore Lock and Release Control
+ *  0b0..Semaphore release
+ *  0b1..Semaphore lock
+ */
+#define CAU3_SEMA4_LK(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_SEMA4_LK_SHIFT)) & CAU3_SEMA4_LK_MASK)
+/*! @} */
+
+/*! @name SMOWNR - Semaphore Ownership Register */
+/*! @{ */
+#define CAU3_SMOWNR_LOCK_MASK                    (0x1U)
+#define CAU3_SMOWNR_LOCK_SHIFT                   (0U)
+/*! LOCK - Semaphore Locked
+ *  0b0..Semaphore not locked
+ *  0b1..Semaphore locked
+ */
+#define CAU3_SMOWNR_LOCK(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_SMOWNR_LOCK_SHIFT)) & CAU3_SMOWNR_LOCK_MASK)
+#define CAU3_SMOWNR_NOWNER_MASK                  (0x80000000U)
+#define CAU3_SMOWNR_NOWNER_SHIFT                 (31U)
+/*! NOWNER - Semaphore Ownership
+ *  0b0..The host making the current read access is the semaphore owner
+ *  0b1..The host making the current read access is NOT the semaphore owner
+ */
+#define CAU3_SMOWNR_NOWNER(x)                    (((uint32_t)(((uint32_t)(x)) << CAU3_SMOWNR_NOWNER_SHIFT)) & CAU3_SMOWNR_NOWNER_MASK)
+/*! @} */
+
+/*! @name ARR - Address Remap Register */
+/*! @{ */
+#define CAU3_ARR_ARRL_MASK                       (0xFFFFFFFFU)
+#define CAU3_ARR_ARRL_SHIFT                      (0U)
+#define CAU3_ARR_ARRL(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_ARR_ARRL_SHIFT)) & CAU3_ARR_ARRL_MASK)
+/*! @} */
+
+/*! @name CC_R - CryptoCore General Purpose Registers */
+/*! @{ */
+#define CAU3_CC_R_R_MASK                         (0xFFFFFFFFU)
+#define CAU3_CC_R_R_SHIFT                        (0U)
+#define CAU3_CC_R_R(x)                           (((uint32_t)(((uint32_t)(x)) << CAU3_CC_R_R_SHIFT)) & CAU3_CC_R_R_MASK)
+/*! @} */
+
+/* The count of CAU3_CC_R */
+#define CAU3_CC_R_COUNT                          (30U)
+
+/*! @name CC_R30 - General Purpose R30 */
+/*! @{ */
+#define CAU3_CC_R30_SP_MASK                      (0xFFFFFFFFU)
+#define CAU3_CC_R30_SP_SHIFT                     (0U)
+#define CAU3_CC_R30_SP(x)                        (((uint32_t)(((uint32_t)(x)) << CAU3_CC_R30_SP_SHIFT)) & CAU3_CC_R30_SP_MASK)
+/*! @} */
+
+/*! @name CC_R31 - General Purpose R31 */
+/*! @{ */
+#define CAU3_CC_R31_LR_MASK                      (0xFFFFFFFFU)
+#define CAU3_CC_R31_LR_SHIFT                     (0U)
+#define CAU3_CC_R31_LR(x)                        (((uint32_t)(((uint32_t)(x)) << CAU3_CC_R31_LR_SHIFT)) & CAU3_CC_R31_LR_MASK)
+/*! @} */
+
+/*! @name CC_PC - Program Counter */
+/*! @{ */
+#define CAU3_CC_PC_PC_MASK                       (0xFFFFFU)
+#define CAU3_CC_PC_PC_SHIFT                      (0U)
+#define CAU3_CC_PC_PC(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_CC_PC_PC_SHIFT)) & CAU3_CC_PC_PC_MASK)
+/*! @} */
+
+/*! @name CC_CMD - Start Command Register */
+/*! @{ */
+#define CAU3_CC_CMD_CMD_MASK                     (0x70000U)
+#define CAU3_CC_CMD_CMD_SHIFT                    (16U)
+/*! CMD - Command
+ *  0b000..Use CR[DTCCFG] for task completion configuration
+ *  0b100..Issue a DMA request
+ *  0b010..Assert Event Completion Signal
+ *  0b001..Issue an interrupt request
+ */
+#define CAU3_CC_CMD_CMD(x)                       (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CMD_CMD_SHIFT)) & CAU3_CC_CMD_CMD_MASK)
+/*! @} */
+
+/*! @name CC_CF - Condition Flag */
+/*! @{ */
+#define CAU3_CC_CF_C_MASK                        (0x1U)
+#define CAU3_CC_CF_C_SHIFT                       (0U)
+#define CAU3_CC_CF_C(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CF_C_SHIFT)) & CAU3_CC_CF_C_MASK)
+#define CAU3_CC_CF_V_MASK                        (0x2U)
+#define CAU3_CC_CF_V_SHIFT                       (1U)
+#define CAU3_CC_CF_V(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CF_V_SHIFT)) & CAU3_CC_CF_V_MASK)
+#define CAU3_CC_CF_Z_MASK                        (0x4U)
+#define CAU3_CC_CF_Z_SHIFT                       (2U)
+#define CAU3_CC_CF_Z(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CF_Z_SHIFT)) & CAU3_CC_CF_Z_MASK)
+#define CAU3_CC_CF_N_MASK                        (0x8U)
+#define CAU3_CC_CF_N_SHIFT                       (3U)
+#define CAU3_CC_CF_N(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CC_CF_N_SHIFT)) & CAU3_CC_CF_N_MASK)
+/*! @} */
+
+/*! @name MDPK - Mode Register (PublicKey) */
+/*! @{ */
+#define CAU3_MDPK_PKHA_MODE_LS_MASK              (0xFFFU)
+#define CAU3_MDPK_PKHA_MODE_LS_SHIFT             (0U)
+#define CAU3_MDPK_PKHA_MODE_LS(x)                (((uint32_t)(((uint32_t)(x)) << CAU3_MDPK_PKHA_MODE_LS_SHIFT)) & CAU3_MDPK_PKHA_MODE_LS_MASK)
+#define CAU3_MDPK_PKHA_MODE_MS_MASK              (0xF0000U)
+#define CAU3_MDPK_PKHA_MODE_MS_SHIFT             (16U)
+#define CAU3_MDPK_PKHA_MODE_MS(x)                (((uint32_t)(((uint32_t)(x)) << CAU3_MDPK_PKHA_MODE_MS_SHIFT)) & CAU3_MDPK_PKHA_MODE_MS_MASK)
+#define CAU3_MDPK_ALG_MASK                       (0xF00000U)
+#define CAU3_MDPK_ALG_SHIFT                      (20U)
+/*! ALG - Algorithm
+ *  0b1000..PKHA
+ */
+#define CAU3_MDPK_ALG(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_MDPK_ALG_SHIFT)) & CAU3_MDPK_ALG_MASK)
+/*! @} */
+
+/*! @name COM - Command Register */
+/*! @{ */
+#define CAU3_COM_ALL_MASK                        (0x1U)
+#define CAU3_COM_ALL_SHIFT                       (0U)
+/*! ALL - Reset All Internal Logic
+ *  0b0..Do Not Reset
+ *  0b1..Reset PKHA engine and registers
+ */
+#define CAU3_COM_ALL(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_COM_ALL_SHIFT)) & CAU3_COM_ALL_MASK)
+#define CAU3_COM_PK_MASK                         (0x40U)
+#define CAU3_COM_PK_SHIFT                        (6U)
+/*! PK - Reset PKHA
+ *  0b0..Do Not Reset
+ *  0b1..Reset Public Key Hardware Accelerator
+ */
+#define CAU3_COM_PK(x)                           (((uint32_t)(((uint32_t)(x)) << CAU3_COM_PK_SHIFT)) & CAU3_COM_PK_MASK)
+/*! @} */
+
+/*! @name CTL - Control Register */
+/*! @{ */
+#define CAU3_CTL_IM_MASK                         (0x1U)
+#define CAU3_CTL_IM_SHIFT                        (0U)
+/*! IM - Interrupt Mask
+ *  0b0..Interrupt not masked.
+ *  0b1..Interrupt masked
+ */
+#define CAU3_CTL_IM(x)                           (((uint32_t)(((uint32_t)(x)) << CAU3_CTL_IM_SHIFT)) & CAU3_CTL_IM_MASK)
+#define CAU3_CTL_PDE_MASK                        (0x10U)
+#define CAU3_CTL_PDE_SHIFT                       (4U)
+/*! PDE - PKHA Register DMA Enable
+ *  0b0..DMA Request and Done signals disabled for the PKHA Registers.
+ *  0b1..DMA Request and Done signals enabled for the PKHA Registers.
+ */
+#define CAU3_CTL_PDE(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CTL_PDE_SHIFT)) & CAU3_CTL_PDE_MASK)
+/*! @} */
+
+/*! @name CW - Clear Written Register */
+/*! @{ */
+#define CAU3_CW_CM_MASK                          (0x1U)
+#define CAU3_CW_CM_SHIFT                         (0U)
+#define CAU3_CW_CM(x)                            (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CM_SHIFT)) & CAU3_CW_CM_MASK)
+#define CAU3_CW_CPKA_MASK                        (0x1000U)
+#define CAU3_CW_CPKA_SHIFT                       (12U)
+#define CAU3_CW_CPKA(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CPKA_SHIFT)) & CAU3_CW_CPKA_MASK)
+#define CAU3_CW_CPKB_MASK                        (0x2000U)
+#define CAU3_CW_CPKB_SHIFT                       (13U)
+#define CAU3_CW_CPKB(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CPKB_SHIFT)) & CAU3_CW_CPKB_MASK)
+#define CAU3_CW_CPKN_MASK                        (0x4000U)
+#define CAU3_CW_CPKN_SHIFT                       (14U)
+#define CAU3_CW_CPKN(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CPKN_SHIFT)) & CAU3_CW_CPKN_MASK)
+#define CAU3_CW_CPKE_MASK                        (0x8000U)
+#define CAU3_CW_CPKE_SHIFT                       (15U)
+#define CAU3_CW_CPKE(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_CW_CPKE_SHIFT)) & CAU3_CW_CPKE_MASK)
+/*! @} */
+
+/*! @name STA - Status Register */
+/*! @{ */
+#define CAU3_STA_PB_MASK                         (0x40U)
+#define CAU3_STA_PB_SHIFT                        (6U)
+/*! PB - PKHA Busy
+ *  0b0..PKHA Idle
+ *  0b1..PKHA Busy.
+ */
+#define CAU3_STA_PB(x)                           (((uint32_t)(((uint32_t)(x)) << CAU3_STA_PB_SHIFT)) & CAU3_STA_PB_MASK)
+#define CAU3_STA_DI_MASK                         (0x10000U)
+#define CAU3_STA_DI_SHIFT                        (16U)
+#define CAU3_STA_DI(x)                           (((uint32_t)(((uint32_t)(x)) << CAU3_STA_DI_SHIFT)) & CAU3_STA_DI_MASK)
+#define CAU3_STA_EI_MASK                         (0x100000U)
+#define CAU3_STA_EI_SHIFT                        (20U)
+/*! EI - Error Interrupt
+ *  0b0..Not Error.
+ *  0b1..Error Interrupt.
+ */
+#define CAU3_STA_EI(x)                           (((uint32_t)(((uint32_t)(x)) << CAU3_STA_EI_SHIFT)) & CAU3_STA_EI_MASK)
+#define CAU3_STA_PKP_MASK                        (0x10000000U)
+#define CAU3_STA_PKP_SHIFT                       (28U)
+#define CAU3_STA_PKP(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_STA_PKP_SHIFT)) & CAU3_STA_PKP_MASK)
+#define CAU3_STA_PKO_MASK                        (0x20000000U)
+#define CAU3_STA_PKO_SHIFT                       (29U)
+#define CAU3_STA_PKO(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_STA_PKO_SHIFT)) & CAU3_STA_PKO_MASK)
+#define CAU3_STA_PKZ_MASK                        (0x40000000U)
+#define CAU3_STA_PKZ_SHIFT                       (30U)
+#define CAU3_STA_PKZ(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_STA_PKZ_SHIFT)) & CAU3_STA_PKZ_MASK)
+/*! @} */
+
+/*! @name ESTA - Error Status Register */
+/*! @{ */
+#define CAU3_ESTA_ERRID1_MASK                    (0xFU)
+#define CAU3_ESTA_ERRID1_SHIFT                   (0U)
+/*! ERRID1 - Error ID 1
+ *  0b0001..Mode Error
+ *  0b0010..PKHA N Register Size Error
+ *  0b0011..PKHA E Register Size Error
+ *  0b0100..PKHA A Register Size Error
+ *  0b0101..PKHA B Register Size Error
+ *  0b0110..PKHA C input (as contained in the PKHA B0 quadrant) is Zero
+ *  0b0111..PKHA Divide by Zero Error
+ *  0b1000..PKHA Modulus Even Error
+ *  0b1111..Invalid Crypto Engine Selected
+ */
+#define CAU3_ESTA_ERRID1(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_ESTA_ERRID1_SHIFT)) & CAU3_ESTA_ERRID1_MASK)
+#define CAU3_ESTA_CL1_MASK                       (0xF00U)
+#define CAU3_ESTA_CL1_SHIFT                      (8U)
+/*! CL1 - algorithms
+ *  0b0000..General Error
+ *  0b1000..Public Key
+ */
+#define CAU3_ESTA_CL1(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_ESTA_CL1_SHIFT)) & CAU3_ESTA_CL1_MASK)
+/*! @} */
+
+/*! @name PKASZ - PKHA A Size Register */
+/*! @{ */
+#define CAU3_PKASZ_PKASZ_MASK                    (0x1FFU)
+#define CAU3_PKASZ_PKASZ_SHIFT                   (0U)
+#define CAU3_PKASZ_PKASZ(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_PKASZ_PKASZ_SHIFT)) & CAU3_PKASZ_PKASZ_MASK)
+/*! @} */
+
+/*! @name PKBSZ - PKHA B Size Register */
+/*! @{ */
+#define CAU3_PKBSZ_PKBSZ_MASK                    (0x1FFU)
+#define CAU3_PKBSZ_PKBSZ_SHIFT                   (0U)
+#define CAU3_PKBSZ_PKBSZ(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_PKBSZ_PKBSZ_SHIFT)) & CAU3_PKBSZ_PKBSZ_MASK)
+/*! @} */
+
+/*! @name PKNSZ - PKHA N Size Register */
+/*! @{ */
+#define CAU3_PKNSZ_PKNSZ_MASK                    (0x1FFU)
+#define CAU3_PKNSZ_PKNSZ_SHIFT                   (0U)
+#define CAU3_PKNSZ_PKNSZ(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_PKNSZ_PKNSZ_SHIFT)) & CAU3_PKNSZ_PKNSZ_MASK)
+/*! @} */
+
+/*! @name PKESZ - PKHA E Size Register */
+/*! @{ */
+#define CAU3_PKESZ_PKESZ_MASK                    (0x1FFU)
+#define CAU3_PKESZ_PKESZ_SHIFT                   (0U)
+#define CAU3_PKESZ_PKESZ(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_PKESZ_PKESZ_SHIFT)) & CAU3_PKESZ_PKESZ_MASK)
+/*! @} */
+
+/*! @name PKHA_VID1 - PKHA Revision ID 1 */
+/*! @{ */
+#define CAU3_PKHA_VID1_MIN_REV_MASK              (0xFFU)
+#define CAU3_PKHA_VID1_MIN_REV_SHIFT             (0U)
+#define CAU3_PKHA_VID1_MIN_REV(x)                (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID1_MIN_REV_SHIFT)) & CAU3_PKHA_VID1_MIN_REV_MASK)
+#define CAU3_PKHA_VID1_MAJ_REV_MASK              (0xFF00U)
+#define CAU3_PKHA_VID1_MAJ_REV_SHIFT             (8U)
+#define CAU3_PKHA_VID1_MAJ_REV(x)                (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID1_MAJ_REV_SHIFT)) & CAU3_PKHA_VID1_MAJ_REV_MASK)
+#define CAU3_PKHA_VID1_IP_ID_MASK                (0xFFFF0000U)
+#define CAU3_PKHA_VID1_IP_ID_SHIFT               (16U)
+#define CAU3_PKHA_VID1_IP_ID(x)                  (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID1_IP_ID_SHIFT)) & CAU3_PKHA_VID1_IP_ID_MASK)
+/*! @} */
+
+/*! @name PKHA_VID2 - PKHA Revision ID 2 */
+/*! @{ */
+#define CAU3_PKHA_VID2_ECO_REV_MASK              (0xFFU)
+#define CAU3_PKHA_VID2_ECO_REV_SHIFT             (0U)
+#define CAU3_PKHA_VID2_ECO_REV(x)                (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID2_ECO_REV_SHIFT)) & CAU3_PKHA_VID2_ECO_REV_MASK)
+#define CAU3_PKHA_VID2_ARCH_ERA_MASK             (0xFF00U)
+#define CAU3_PKHA_VID2_ARCH_ERA_SHIFT            (8U)
+#define CAU3_PKHA_VID2_ARCH_ERA(x)               (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_VID2_ARCH_ERA_SHIFT)) & CAU3_PKHA_VID2_ARCH_ERA_MASK)
+/*! @} */
+
+/*! @name CHA_VID - CHA Revision ID */
+/*! @{ */
+#define CAU3_CHA_VID_PKHAREV_MASK                (0xF0000U)
+#define CAU3_CHA_VID_PKHAREV_SHIFT               (16U)
+#define CAU3_CHA_VID_PKHAREV(x)                  (((uint32_t)(((uint32_t)(x)) << CAU3_CHA_VID_PKHAREV_SHIFT)) & CAU3_CHA_VID_PKHAREV_MASK)
+#define CAU3_CHA_VID_PKHAVID_MASK                (0xF00000U)
+#define CAU3_CHA_VID_PKHAVID_SHIFT               (20U)
+#define CAU3_CHA_VID_PKHAVID(x)                  (((uint32_t)(((uint32_t)(x)) << CAU3_CHA_VID_PKHAVID_SHIFT)) & CAU3_CHA_VID_PKHAVID_MASK)
+/*! @} */
+
+/*! @name PKHA_CCR - PKHA Clock Control Register */
+/*! @{ */
+#define CAU3_PKHA_CCR_CKTHRT_MASK                (0x7U)
+#define CAU3_PKHA_CCR_CKTHRT_SHIFT               (0U)
+/*! CKTHRT - Clock Throttle selection
+ *  0b000..PKHA clock division rate is 8/8 - full speed
+ *  0b001..PKHA clock division rate is 1/8
+ *  0b010..PKHA clock division rate is 2/8
+ *  0b011..PKHA clock division rate is 3/8
+ *  0b100..PKHA clock division rate is 4/8
+ *  0b101..PKHA clock division rate is 5/8
+ *  0b110..PKHA clock division rate is 6/8
+ *  0b111..PKHA clock division rate is 7/8
+ */
+#define CAU3_PKHA_CCR_CKTHRT(x)                  (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_CKTHRT_SHIFT)) & CAU3_PKHA_CCR_CKTHRT_MASK)
+#define CAU3_PKHA_CCR_LK_MASK                    (0x1000000U)
+#define CAU3_PKHA_CCR_LK_SHIFT                   (24U)
+/*! LK - Register Lock
+ *  0b0..Register is unlocked
+ *  0b1..Register is locked
+ */
+#define CAU3_PKHA_CCR_LK(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_LK_SHIFT)) & CAU3_PKHA_CCR_LK_MASK)
+#define CAU3_PKHA_CCR_ELFR_MASK                  (0x20000000U)
+#define CAU3_PKHA_CCR_ELFR_SHIFT                 (29U)
+/*! ELFR - Enable Linear Feedback Shift Register
+ *  0b0..LFSR is only enabled if ECT = 1 and ECJ = 1
+ *  0b1..LFSR is enabled independently of ECT and ECJ
+ */
+#define CAU3_PKHA_CCR_ELFR(x)                    (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_ELFR_SHIFT)) & CAU3_PKHA_CCR_ELFR_MASK)
+#define CAU3_PKHA_CCR_ECJ_MASK                   (0x40000000U)
+#define CAU3_PKHA_CCR_ECJ_SHIFT                  (30U)
+/*! ECJ - Enable Clock Jitter
+ *  0b0..Clock Jitter is disabled
+ *  0b1..Clock jitter is enabled
+ */
+#define CAU3_PKHA_CCR_ECJ(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_ECJ_SHIFT)) & CAU3_PKHA_CCR_ECJ_MASK)
+#define CAU3_PKHA_CCR_ECT_MASK                   (0x80000000U)
+#define CAU3_PKHA_CCR_ECT_SHIFT                  (31U)
+/*! ECT - Enable Clock Throttle
+ *  0b0..PKHA clock throttle disabled meaning that PKHA is operatiing at full speed
+ *  0b1..PKHA clock throttle enabled
+ */
+#define CAU3_PKHA_CCR_ECT(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKHA_CCR_ECT_SHIFT)) & CAU3_PKHA_CCR_ECT_MASK)
+/*! @} */
+
+/*! @name GSR - Global Status Register */
+/*! @{ */
+#define CAU3_GSR_CDI_MASK                        (0x400U)
+#define CAU3_GSR_CDI_SHIFT                       (10U)
+/*! CDI - CAU3 Done Interrupt occurred
+ *  0b0..CAU3 Done Interrupt did not occur
+ *  0b1..CAU3 Done Interrupt occurred
+ */
+#define CAU3_GSR_CDI(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_GSR_CDI_SHIFT)) & CAU3_GSR_CDI_MASK)
+#define CAU3_GSR_CEI_MASK                        (0x4000U)
+#define CAU3_GSR_CEI_SHIFT                       (14U)
+/*! CEI - CAU3 Error Interrupt
+ *  0b0..CAU3 Error Interrupt did not occur
+ *  0b1..CAU3 Error Interrupt occurred
+ */
+#define CAU3_GSR_CEI(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_GSR_CEI_SHIFT)) & CAU3_GSR_CEI_MASK)
+#define CAU3_GSR_PEI_MASK                        (0x8000U)
+#define CAU3_GSR_PEI_SHIFT                       (15U)
+/*! PEI - PKHA Done or Error Interrupt
+ *  0b0..PKHA interrupt did not occur
+ *  0b1..PKHA interrupt had occurred
+ */
+#define CAU3_GSR_PEI(x)                          (((uint32_t)(((uint32_t)(x)) << CAU3_GSR_PEI_SHIFT)) & CAU3_GSR_PEI_MASK)
+#define CAU3_GSR_PBSY_MASK                       (0x80000000U)
+#define CAU3_GSR_PBSY_SHIFT                      (31U)
+/*! PBSY - PKHA Busy
+ *  0b0..PKHA not busy
+ *  0b1..PKHA busy
+ */
+#define CAU3_GSR_PBSY(x)                         (((uint32_t)(((uint32_t)(x)) << CAU3_GSR_PBSY_SHIFT)) & CAU3_GSR_PBSY_MASK)
+/*! @} */
+
+/*! @name CKLFSR - Clock Linear Feedback Shift Register */
+/*! @{ */
+#define CAU3_CKLFSR_LFSR_MASK                    (0xFFFFFFFFU)
+#define CAU3_CKLFSR_LFSR_SHIFT                   (0U)
+#define CAU3_CKLFSR_LFSR(x)                      (((uint32_t)(((uint32_t)(x)) << CAU3_CKLFSR_LFSR_SHIFT)) & CAU3_CKLFSR_LFSR_MASK)
+/*! @} */
+
+/*! @name PKA0 - PKHA A0 Register */
+/*! @{ */
+#define CAU3_PKA0_PKHA_A0_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKA0_PKHA_A0_SHIFT                  (0U)
+#define CAU3_PKA0_PKHA_A0(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKA0_PKHA_A0_SHIFT)) & CAU3_PKA0_PKHA_A0_MASK)
+/*! @} */
+
+/* The count of CAU3_PKA0 */
+#define CAU3_PKA0_COUNT                          (32U)
+
+/*! @name PKA1 - PKHA A1 Register */
+/*! @{ */
+#define CAU3_PKA1_PKHA_A1_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKA1_PKHA_A1_SHIFT                  (0U)
+#define CAU3_PKA1_PKHA_A1(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKA1_PKHA_A1_SHIFT)) & CAU3_PKA1_PKHA_A1_MASK)
+/*! @} */
+
+/* The count of CAU3_PKA1 */
+#define CAU3_PKA1_COUNT                          (32U)
+
+/*! @name PKA2 - PKHA A2 Register */
+/*! @{ */
+#define CAU3_PKA2_PKHA_A2_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKA2_PKHA_A2_SHIFT                  (0U)
+#define CAU3_PKA2_PKHA_A2(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKA2_PKHA_A2_SHIFT)) & CAU3_PKA2_PKHA_A2_MASK)
+/*! @} */
+
+/* The count of CAU3_PKA2 */
+#define CAU3_PKA2_COUNT                          (32U)
+
+/*! @name PKA3 - PKHA A3 Register */
+/*! @{ */
+#define CAU3_PKA3_PKHA_A3_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKA3_PKHA_A3_SHIFT                  (0U)
+#define CAU3_PKA3_PKHA_A3(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKA3_PKHA_A3_SHIFT)) & CAU3_PKA3_PKHA_A3_MASK)
+/*! @} */
+
+/* The count of CAU3_PKA3 */
+#define CAU3_PKA3_COUNT                          (32U)
+
+/*! @name PKB0 - PKHA B0 Register */
+/*! @{ */
+#define CAU3_PKB0_PKHA_B0_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKB0_PKHA_B0_SHIFT                  (0U)
+#define CAU3_PKB0_PKHA_B0(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKB0_PKHA_B0_SHIFT)) & CAU3_PKB0_PKHA_B0_MASK)
+/*! @} */
+
+/* The count of CAU3_PKB0 */
+#define CAU3_PKB0_COUNT                          (32U)
+
+/*! @name PKB1 - PKHA B1 Register */
+/*! @{ */
+#define CAU3_PKB1_PKHA_B1_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKB1_PKHA_B1_SHIFT                  (0U)
+#define CAU3_PKB1_PKHA_B1(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKB1_PKHA_B1_SHIFT)) & CAU3_PKB1_PKHA_B1_MASK)
+/*! @} */
+
+/* The count of CAU3_PKB1 */
+#define CAU3_PKB1_COUNT                          (32U)
+
+/*! @name PKB2 - PKHA B2 Register */
+/*! @{ */
+#define CAU3_PKB2_PKHA_B2_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKB2_PKHA_B2_SHIFT                  (0U)
+#define CAU3_PKB2_PKHA_B2(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKB2_PKHA_B2_SHIFT)) & CAU3_PKB2_PKHA_B2_MASK)
+/*! @} */
+
+/* The count of CAU3_PKB2 */
+#define CAU3_PKB2_COUNT                          (32U)
+
+/*! @name PKB3 - PKHA B3 Register */
+/*! @{ */
+#define CAU3_PKB3_PKHA_B3_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKB3_PKHA_B3_SHIFT                  (0U)
+#define CAU3_PKB3_PKHA_B3(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKB3_PKHA_B3_SHIFT)) & CAU3_PKB3_PKHA_B3_MASK)
+/*! @} */
+
+/* The count of CAU3_PKB3 */
+#define CAU3_PKB3_COUNT                          (32U)
+
+/*! @name PKN0 - PKHA N0 Register */
+/*! @{ */
+#define CAU3_PKN0_PKHA_N0_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKN0_PKHA_N0_SHIFT                  (0U)
+#define CAU3_PKN0_PKHA_N0(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKN0_PKHA_N0_SHIFT)) & CAU3_PKN0_PKHA_N0_MASK)
+/*! @} */
+
+/* The count of CAU3_PKN0 */
+#define CAU3_PKN0_COUNT                          (32U)
+
+/*! @name PKN1 - PKHA N1 Register */
+/*! @{ */
+#define CAU3_PKN1_PKHA_N1_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKN1_PKHA_N1_SHIFT                  (0U)
+#define CAU3_PKN1_PKHA_N1(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKN1_PKHA_N1_SHIFT)) & CAU3_PKN1_PKHA_N1_MASK)
+/*! @} */
+
+/* The count of CAU3_PKN1 */
+#define CAU3_PKN1_COUNT                          (32U)
+
+/*! @name PKN2 - PKHA N2 Register */
+/*! @{ */
+#define CAU3_PKN2_PKHA_N2_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKN2_PKHA_N2_SHIFT                  (0U)
+#define CAU3_PKN2_PKHA_N2(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKN2_PKHA_N2_SHIFT)) & CAU3_PKN2_PKHA_N2_MASK)
+/*! @} */
+
+/* The count of CAU3_PKN2 */
+#define CAU3_PKN2_COUNT                          (32U)
+
+/*! @name PKN3 - PKHA N3 Register */
+/*! @{ */
+#define CAU3_PKN3_PKHA_N3_MASK                   (0xFFFFFFFFU)
+#define CAU3_PKN3_PKHA_N3_SHIFT                  (0U)
+#define CAU3_PKN3_PKHA_N3(x)                     (((uint32_t)(((uint32_t)(x)) << CAU3_PKN3_PKHA_N3_SHIFT)) & CAU3_PKN3_PKHA_N3_MASK)
+/*! @} */
+
+/* The count of CAU3_PKN3 */
+#define CAU3_PKN3_COUNT                          (32U)
+
+/*! @name PKE - PKHA E Register */
+/*! @{ */
+#define CAU3_PKE_PKHA_E_MASK                     (0xFFFFFFFFU)
+#define CAU3_PKE_PKHA_E_SHIFT                    (0U)
+#define CAU3_PKE_PKHA_E(x)                       (((uint32_t)(((uint32_t)(x)) << CAU3_PKE_PKHA_E_SHIFT)) & CAU3_PKE_PKHA_E_MASK)
+/*! @} */
+
+/* The count of CAU3_PKE */
+#define CAU3_PKE_COUNT                           (128U)
+
+
+/*!
+ * @}
+ */ /* end of group CAU3_Register_Masks */
+
+
+/* CAU3 - Peripheral instance base addresses */
+/** Peripheral CAU3 base address */
+#define CAU3_BASE                                (0x41028000u)
+/** Peripheral CAU3 base pointer */
+#define CAU3                                     ((CAU3_Type *)CAU3_BASE)
+/** Array initializer of CAU3 peripheral base addresses */
+#define CAU3_BASE_ADDRS                          { CAU3_BASE }
+/** Array initializer of CAU3 peripheral base pointers */
+#define CAU3_BASE_PTRS                           { CAU3 }
+/** Interrupt vectors for the CAU3 peripheral type */
+#define CAU3_TASK_COMPLETE_IRQS                  { CAU3_Task_Complete_IRQn }
+#define CAU3_SECURITY_VIOLATION_IRQS             { CAU3_Security_Violation_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CAU3_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    __IO uint32_t DATA;                              /**< CRC Data register, offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint8_t DATALL;                             /**< CRC_DATALL register, offset: 0x0 */
+      __IO uint8_t DATALU;                             /**< CRC_DATALU register, offset: 0x1 */
+      __IO uint8_t DATAHL;                             /**< CRC_DATAHL register, offset: 0x2 */
+      __IO uint8_t DATAHU;                             /**< CRC_DATAHU register, offset: 0x3 */
+    } ACCESS8BIT;
+    struct {                                         /* offset: 0x0 */
+      __IO uint16_t DATAL;                             /**< CRC_DATAL register, offset: 0x0 */
+      __IO uint16_t DATAH;                             /**< CRC_DATAH register, offset: 0x2 */
+    } ACCESS16BIT;
+  };
+  union {                                          /* offset: 0x4 */
+    __IO uint32_t GPOLY;                             /**< CRC Polynomial register, offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint8_t GPOLYLL;                            /**< CRC_GPOLYLL register, offset: 0x4 */
+      __IO uint8_t GPOLYLU;                            /**< CRC_GPOLYLU register, offset: 0x5 */
+      __IO uint8_t GPOLYHL;                            /**< CRC_GPOLYHL register, offset: 0x6 */
+      __IO uint8_t GPOLYHU;                            /**< CRC_GPOLYHU register, offset: 0x7 */
+    } GPOLY_ACCESS8BIT;
+    struct {                                         /* offset: 0x4 */
+      __IO uint16_t GPOLYL;                            /**< CRC_GPOLYL register, offset: 0x4 */
+      __IO uint16_t GPOLYH;                            /**< CRC_GPOLYH register, offset: 0x6 */
+    } GPOLY_ACCESS16BIT;
+  };
+  union {                                          /* offset: 0x8 */
+    __IO uint32_t CTRL;                              /**< CRC Control register, offset: 0x8 */
+    struct {                                         /* offset: 0x8 */
+           uint8_t RESERVED_0[3];
+      __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register, offset: 0xB */
+    } CTRL_ACCESS8BIT;
+  };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/*! @name DATA - CRC Data register */
+/*! @{ */
+#define CRC_DATA_LL_MASK                         (0xFFU)
+#define CRC_DATA_LL_SHIFT                        (0U)
+#define CRC_DATA_LL(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
+#define CRC_DATA_LU_MASK                         (0xFF00U)
+#define CRC_DATA_LU_SHIFT                        (8U)
+#define CRC_DATA_LU(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
+#define CRC_DATA_HL_MASK                         (0xFF0000U)
+#define CRC_DATA_HL_SHIFT                        (16U)
+#define CRC_DATA_HL(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
+#define CRC_DATA_HU_MASK                         (0xFF000000U)
+#define CRC_DATA_HU_SHIFT                        (24U)
+#define CRC_DATA_HU(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
+/*! @} */
+
+/*! @name DATALL - CRC_DATALL register */
+/*! @{ */
+#define CRC_DATALL_DATALL_MASK                   (0xFFU)
+#define CRC_DATALL_DATALL_SHIFT                  (0U)
+#define CRC_DATALL_DATALL(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
+/*! @} */
+
+/*! @name DATALU - CRC_DATALU register */
+/*! @{ */
+#define CRC_DATALU_DATALU_MASK                   (0xFFU)
+#define CRC_DATALU_DATALU_SHIFT                  (0U)
+#define CRC_DATALU_DATALU(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
+/*! @} */
+
+/*! @name DATAHL - CRC_DATAHL register */
+/*! @{ */
+#define CRC_DATAHL_DATAHL_MASK                   (0xFFU)
+#define CRC_DATAHL_DATAHL_SHIFT                  (0U)
+#define CRC_DATAHL_DATAHL(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
+/*! @} */
+
+/*! @name DATAHU - CRC_DATAHU register */
+/*! @{ */
+#define CRC_DATAHU_DATAHU_MASK                   (0xFFU)
+#define CRC_DATAHU_DATAHU_SHIFT                  (0U)
+#define CRC_DATAHU_DATAHU(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
+/*! @} */
+
+/*! @name DATAL - CRC_DATAL register */
+/*! @{ */
+#define CRC_DATAL_DATAL_MASK                     (0xFFFFU)
+#define CRC_DATAL_DATAL_SHIFT                    (0U)
+#define CRC_DATAL_DATAL(x)                       (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
+/*! @} */
+
+/*! @name DATAH - CRC_DATAH register */
+/*! @{ */
+#define CRC_DATAH_DATAH_MASK                     (0xFFFFU)
+#define CRC_DATAH_DATAH_SHIFT                    (0U)
+#define CRC_DATAH_DATAH(x)                       (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
+/*! @} */
+
+/*! @name GPOLY - CRC Polynomial register */
+/*! @{ */
+#define CRC_GPOLY_LOW_MASK                       (0xFFFFU)
+#define CRC_GPOLY_LOW_SHIFT                      (0U)
+#define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK                      (0xFFFF0000U)
+#define CRC_GPOLY_HIGH_SHIFT                     (16U)
+#define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
+/*! @} */
+
+/*! @name GPOLYLL - CRC_GPOLYLL register */
+/*! @{ */
+#define CRC_GPOLYLL_GPOLYLL_MASK                 (0xFFU)
+#define CRC_GPOLYLL_GPOLYLL_SHIFT                (0U)
+#define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
+/*! @} */
+
+/*! @name GPOLYLU - CRC_GPOLYLU register */
+/*! @{ */
+#define CRC_GPOLYLU_GPOLYLU_MASK                 (0xFFU)
+#define CRC_GPOLYLU_GPOLYLU_SHIFT                (0U)
+#define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
+/*! @} */
+
+/*! @name GPOLYHL - CRC_GPOLYHL register */
+/*! @{ */
+#define CRC_GPOLYHL_GPOLYHL_MASK                 (0xFFU)
+#define CRC_GPOLYHL_GPOLYHL_SHIFT                (0U)
+#define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
+/*! @} */
+
+/*! @name GPOLYHU - CRC_GPOLYHU register */
+/*! @{ */
+#define CRC_GPOLYHU_GPOLYHU_MASK                 (0xFFU)
+#define CRC_GPOLYHU_GPOLYHU_SHIFT                (0U)
+#define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
+/*! @} */
+
+/*! @name GPOLYL - CRC_GPOLYL register */
+/*! @{ */
+#define CRC_GPOLYL_GPOLYL_MASK                   (0xFFFFU)
+#define CRC_GPOLYL_GPOLYL_SHIFT                  (0U)
+#define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
+/*! @} */
+
+/*! @name GPOLYH - CRC_GPOLYH register */
+/*! @{ */
+#define CRC_GPOLYH_GPOLYH_MASK                   (0xFFFFU)
+#define CRC_GPOLYH_GPOLYH_SHIFT                  (0U)
+#define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
+/*! @} */
+
+/*! @name CTRL - CRC Control register */
+/*! @{ */
+#define CRC_CTRL_TCRC_MASK                       (0x1000000U)
+#define CRC_CTRL_TCRC_SHIFT                      (24U)
+/*! TCRC - TCRC
+ *  0b0..16-bit CRC protocol.
+ *  0b1..32-bit CRC protocol.
+ */
+#define CRC_CTRL_TCRC(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
+#define CRC_CTRL_WAS_MASK                        (0x2000000U)
+#define CRC_CTRL_WAS_SHIFT                       (25U)
+/*! WAS - Write CRC Data Register As Seed
+ *  0b0..Writes to the CRC data register are data values.
+ *  0b1..Writes to the CRC data register are seed values.
+ */
+#define CRC_CTRL_WAS(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
+#define CRC_CTRL_FXOR_MASK                       (0x4000000U)
+#define CRC_CTRL_FXOR_SHIFT                      (26U)
+/*! FXOR - Complement Read Of CRC Data Register
+ *  0b0..No XOR on reading.
+ *  0b1..Invert or complement the read value of the CRC Data register.
+ */
+#define CRC_CTRL_FXOR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
+#define CRC_CTRL_TOTR_MASK                       (0x30000000U)
+#define CRC_CTRL_TOTR_SHIFT                      (28U)
+/*! TOTR - Type Of Transpose For Read
+ *  0b00..No transposition.
+ *  0b01..Bits in bytes are transposed; bytes are not transposed.
+ *  0b10..Both bits in bytes and bytes are transposed.
+ *  0b11..Only bytes are transposed; no bits in a byte are transposed.
+ */
+#define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK                        (0xC0000000U)
+#define CRC_CTRL_TOT_SHIFT                       (30U)
+/*! TOT - Type Of Transpose For Writes
+ *  0b00..No transposition.
+ *  0b01..Bits in bytes are transposed; bytes are not transposed.
+ *  0b10..Both bits in bytes and bytes are transposed.
+ *  0b11..Only bytes are transposed; no bits in a byte are transposed.
+ */
+#define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
+/*! @} */
+
+/*! @name CTRLHU - CRC_CTRLHU register */
+/*! @{ */
+#define CRC_CTRLHU_TCRC_MASK                     (0x1U)
+#define CRC_CTRLHU_TCRC_SHIFT                    (0U)
+/*! TCRC
+ *  0b0..16-bit CRC protocol.
+ *  0b1..32-bit CRC protocol.
+ */
+#define CRC_CTRLHU_TCRC(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
+#define CRC_CTRLHU_WAS_MASK                      (0x2U)
+#define CRC_CTRLHU_WAS_SHIFT                     (1U)
+/*! WAS
+ *  0b0..Writes to the CRC data register are data values.
+ *  0b1..Writes to the CRC data register are seed values.
+ */
+#define CRC_CTRLHU_WAS(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
+#define CRC_CTRLHU_FXOR_MASK                     (0x4U)
+#define CRC_CTRLHU_FXOR_SHIFT                    (2U)
+/*! FXOR
+ *  0b0..No XOR on reading.
+ *  0b1..Invert or complement the read value of the CRC Data register.
+ */
+#define CRC_CTRLHU_FXOR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
+#define CRC_CTRLHU_TOTR_MASK                     (0x30U)
+#define CRC_CTRLHU_TOTR_SHIFT                    (4U)
+/*! TOTR
+ *  0b00..No transposition.
+ *  0b01..Bits in bytes are transposed; bytes are not transposed.
+ *  0b10..Both bits in bytes and bytes are transposed.
+ *  0b11..Only bytes are transposed; no bits in a byte are transposed.
+ */
+#define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK                      (0xC0U)
+#define CRC_CTRLHU_TOT_SHIFT                     (6U)
+/*! TOT
+ *  0b00..No transposition.
+ *  0b01..Bits in bytes are transposed; bytes are not transposed.
+ *  0b10..Both bits in bytes and bytes are transposed.
+ *  0b11..Only bytes are transposed; no bits in a byte are transposed.
+ */
+#define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE                                 (0x4002F000u)
+/** Peripheral CRC base pointer */
+#define CRC0                                     ((CRC_Type *)CRC_BASE)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS                           { CRC_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS                            { CRC0 }
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /**< Control Register, offset: 0x0 */
+  __I  uint32_t ES;                                /**< Error Status Register, offset: 0x4 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t ERQ;                               /**< Enable Request Register, offset: 0xC */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t EEI;                               /**< Enable Error Interrupt Register, offset: 0x14 */
+  __O  uint8_t CEEI;                               /**< Clear Enable Error Interrupt Register, offset: 0x18 */
+  __O  uint8_t SEEI;                               /**< Set Enable Error Interrupt Register, offset: 0x19 */
+  __O  uint8_t CERQ;                               /**< Clear Enable Request Register, offset: 0x1A */
+  __O  uint8_t SERQ;                               /**< Set Enable Request Register, offset: 0x1B */
+  __O  uint8_t CDNE;                               /**< Clear DONE Status Bit Register, offset: 0x1C */
+  __O  uint8_t SSRT;                               /**< Set START Bit Register, offset: 0x1D */
+  __O  uint8_t CERR;                               /**< Clear Error Register, offset: 0x1E */
+  __O  uint8_t CINT;                               /**< Clear Interrupt Request Register, offset: 0x1F */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t INT;                               /**< Interrupt Request Register, offset: 0x24 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t ERR;                               /**< Error Register, offset: 0x2C */
+       uint8_t RESERVED_4[4];
+  __I  uint32_t HRS;                               /**< Hardware Request Status Register, offset: 0x34 */
+       uint8_t RESERVED_5[12];
+  __IO uint32_t EARS;                              /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
+       uint8_t RESERVED_6[184];
+  __IO uint8_t DCHPRI3;                            /**< Channel Priority Register, offset: 0x100 */
+  __IO uint8_t DCHPRI2;                            /**< Channel Priority Register, offset: 0x101 */
+  __IO uint8_t DCHPRI1;                            /**< Channel Priority Register, offset: 0x102 */
+  __IO uint8_t DCHPRI0;                            /**< Channel Priority Register, offset: 0x103 */
+  __IO uint8_t DCHPRI7;                            /**< Channel Priority Register, offset: 0x104 */
+  __IO uint8_t DCHPRI6;                            /**< Channel Priority Register, offset: 0x105 */
+  __IO uint8_t DCHPRI5;                            /**< Channel Priority Register, offset: 0x106 */
+  __IO uint8_t DCHPRI4;                            /**< Channel Priority Register, offset: 0x107 */
+       uint8_t RESERVED_7[3832];
+  struct {                                         /* offset: 0x1000, array step: 0x20 */
+    __IO uint32_t SADDR;                             /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+    __IO uint16_t SOFF;                              /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+    __IO uint16_t ATTR;                              /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+    union {                                          /* offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLNO;                       /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFNO;                    /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFYES;                   /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+    };
+    __IO uint32_t SLAST;                             /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+    __IO uint32_t DADDR;                             /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+    __IO uint16_t DOFF;                              /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+    union {                                          /* offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKNO;                     /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKYES;                    /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+    };
+    __IO uint32_t DLAST_SGA;                         /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+    __IO uint16_t CSR;                               /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+    union {                                          /* offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKNO;                     /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKYES;                    /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+    };
+  } TCD[8];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/*! @name CR - Control Register */
+/*! @{ */
+#define DMA_CR_EDBG_MASK                         (0x2U)
+#define DMA_CR_EDBG_SHIFT                        (1U)
+/*! EDBG - Enable Debug
+ *  0b0..When in debug mode, the DMA continues to operate.
+ *  0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
+ */
+#define DMA_CR_EDBG(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
+#define DMA_CR_ERCA_MASK                         (0x4U)
+#define DMA_CR_ERCA_SHIFT                        (2U)
+/*! ERCA - Enable Round Robin Channel Arbitration
+ *  0b0..Fixed priority arbitration is used for channel selection .
+ *  0b1..Round robin arbitration is used for channel selection .
+ */
+#define DMA_CR_ERCA(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
+#define DMA_CR_HOE_MASK                          (0x10U)
+#define DMA_CR_HOE_SHIFT                         (4U)
+/*! HOE - Halt On Error
+ *  0b0..Normal operation
+ *  0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
+ */
+#define DMA_CR_HOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
+#define DMA_CR_HALT_MASK                         (0x20U)
+#define DMA_CR_HALT_SHIFT                        (5U)
+/*! HALT - Halt DMA Operations
+ *  0b0..Normal operation
+ *  0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.
+ */
+#define DMA_CR_HALT(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
+#define DMA_CR_CLM_MASK                          (0x40U)
+#define DMA_CR_CLM_SHIFT                         (6U)
+/*! CLM - Continuous Link Mode
+ *  0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again.
+ *  0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.
+ */
+#define DMA_CR_CLM(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
+#define DMA_CR_EMLM_MASK                         (0x80U)
+#define DMA_CR_EMLM_SHIFT                        (7U)
+/*! EMLM - Enable Minor Loop Mapping
+ *  0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
+ *  0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.
+ */
+#define DMA_CR_EMLM(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
+#define DMA_CR_ECX_MASK                          (0x10000U)
+#define DMA_CR_ECX_SHIFT                         (16U)
+/*! ECX - Error Cancel Transfer
+ *  0b0..Normal operation
+ *  0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.
+ */
+#define DMA_CR_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
+#define DMA_CR_CX_MASK                           (0x20000U)
+#define DMA_CR_CX_SHIFT                          (17U)
+/*! CX - Cancel Transfer
+ *  0b0..Normal operation
+ *  0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
+ */
+#define DMA_CR_CX(x)                             (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
+#define DMA_CR_ACTIVE_MASK                       (0x80000000U)
+#define DMA_CR_ACTIVE_SHIFT                      (31U)
+/*! ACTIVE - DMA Active Status
+ *  0b0..eDMA is idle.
+ *  0b1..eDMA is executing a channel.
+ */
+#define DMA_CR_ACTIVE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
+/*! @} */
+
+/*! @name ES - Error Status Register */
+/*! @{ */
+#define DMA_ES_DBE_MASK                          (0x1U)
+#define DMA_ES_DBE_SHIFT                         (0U)
+/*! DBE - Destination Bus Error
+ *  0b0..No destination bus error
+ *  0b1..The last recorded error was a bus error on a destination write
+ */
+#define DMA_ES_DBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
+#define DMA_ES_SBE_MASK                          (0x2U)
+#define DMA_ES_SBE_SHIFT                         (1U)
+/*! SBE - Source Bus Error
+ *  0b0..No source bus error
+ *  0b1..The last recorded error was a bus error on a source read
+ */
+#define DMA_ES_SBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
+#define DMA_ES_SGE_MASK                          (0x4U)
+#define DMA_ES_SGE_SHIFT                         (2U)
+/*! SGE - Scatter/Gather Configuration Error
+ *  0b0..No scatter/gather configuration error
+ *  0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
+ */
+#define DMA_ES_SGE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
+#define DMA_ES_NCE_MASK                          (0x8U)
+#define DMA_ES_NCE_SHIFT                         (3U)
+/*! NCE - NBYTES/CITER Configuration Error
+ *  0b0..No NBYTES/CITER configuration error
+ *  0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
+ */
+#define DMA_ES_NCE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
+#define DMA_ES_DOE_MASK                          (0x10U)
+#define DMA_ES_DOE_SHIFT                         (4U)
+/*! DOE - Destination Offset Error
+ *  0b0..No destination offset configuration error
+ *  0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
+ */
+#define DMA_ES_DOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
+#define DMA_ES_DAE_MASK                          (0x20U)
+#define DMA_ES_DAE_SHIFT                         (5U)
+/*! DAE - Destination Address Error
+ *  0b0..No destination address configuration error
+ *  0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
+ */
+#define DMA_ES_DAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
+#define DMA_ES_SOE_MASK                          (0x40U)
+#define DMA_ES_SOE_SHIFT                         (6U)
+/*! SOE - Source Offset Error
+ *  0b0..No source offset configuration error
+ *  0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
+ */
+#define DMA_ES_SOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
+#define DMA_ES_SAE_MASK                          (0x80U)
+#define DMA_ES_SAE_SHIFT                         (7U)
+/*! SAE - Source Address Error
+ *  0b0..No source address configuration error.
+ *  0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
+ */
+#define DMA_ES_SAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
+#define DMA_ES_ERRCHN_MASK                       (0x700U)
+#define DMA_ES_ERRCHN_SHIFT                      (8U)
+#define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK                          (0x4000U)
+#define DMA_ES_CPE_SHIFT                         (14U)
+/*! CPE - Channel Priority Error
+ *  0b0..No channel priority error
+ *  0b1..The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique.
+ */
+#define DMA_ES_CPE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
+#define DMA_ES_ECX_MASK                          (0x10000U)
+#define DMA_ES_ECX_SHIFT                         (16U)
+/*! ECX - Transfer Canceled
+ *  0b0..No canceled transfers
+ *  0b1..The last recorded entry was a canceled transfer by the error cancel transfer input
+ */
+#define DMA_ES_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
+#define DMA_ES_VLD_MASK                          (0x80000000U)
+#define DMA_ES_VLD_SHIFT                         (31U)
+/*! VLD - VLD
+ *  0b0..No ERR bits are set.
+ *  0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.
+ */
+#define DMA_ES_VLD(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
+/*! @} */
+
+/*! @name ERQ - Enable Request Register */
+/*! @{ */
+#define DMA_ERQ_ERQ0_MASK                        (0x1U)
+#define DMA_ERQ_ERQ0_SHIFT                       (0U)
+/*! ERQ0 - Enable DMA Request 0
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
+#define DMA_ERQ_ERQ1_MASK                        (0x2U)
+#define DMA_ERQ_ERQ1_SHIFT                       (1U)
+/*! ERQ1 - Enable DMA Request 1
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
+#define DMA_ERQ_ERQ2_MASK                        (0x4U)
+#define DMA_ERQ_ERQ2_SHIFT                       (2U)
+/*! ERQ2 - Enable DMA Request 2
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
+#define DMA_ERQ_ERQ3_MASK                        (0x8U)
+#define DMA_ERQ_ERQ3_SHIFT                       (3U)
+/*! ERQ3 - Enable DMA Request 3
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
+#define DMA_ERQ_ERQ4_MASK                        (0x10U)
+#define DMA_ERQ_ERQ4_SHIFT                       (4U)
+/*! ERQ4 - Enable DMA Request 4
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
+#define DMA_ERQ_ERQ5_MASK                        (0x20U)
+#define DMA_ERQ_ERQ5_SHIFT                       (5U)
+/*! ERQ5 - Enable DMA Request 5
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
+#define DMA_ERQ_ERQ6_MASK                        (0x40U)
+#define DMA_ERQ_ERQ6_SHIFT                       (6U)
+/*! ERQ6 - Enable DMA Request 6
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
+#define DMA_ERQ_ERQ7_MASK                        (0x80U)
+#define DMA_ERQ_ERQ7_SHIFT                       (7U)
+/*! ERQ7 - Enable DMA Request 7
+ *  0b0..The DMA request signal for the corresponding channel is disabled
+ *  0b1..The DMA request signal for the corresponding channel is enabled
+ */
+#define DMA_ERQ_ERQ7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
+/*! @} */
+
+/*! @name EEI - Enable Error Interrupt Register */
+/*! @{ */
+#define DMA_EEI_EEI0_MASK                        (0x1U)
+#define DMA_EEI_EEI0_SHIFT                       (0U)
+/*! EEI0 - Enable Error Interrupt 0
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
+#define DMA_EEI_EEI1_MASK                        (0x2U)
+#define DMA_EEI_EEI1_SHIFT                       (1U)
+/*! EEI1 - Enable Error Interrupt 1
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
+#define DMA_EEI_EEI2_MASK                        (0x4U)
+#define DMA_EEI_EEI2_SHIFT                       (2U)
+/*! EEI2 - Enable Error Interrupt 2
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
+#define DMA_EEI_EEI3_MASK                        (0x8U)
+#define DMA_EEI_EEI3_SHIFT                       (3U)
+/*! EEI3 - Enable Error Interrupt 3
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
+#define DMA_EEI_EEI4_MASK                        (0x10U)
+#define DMA_EEI_EEI4_SHIFT                       (4U)
+/*! EEI4 - Enable Error Interrupt 4
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
+#define DMA_EEI_EEI5_MASK                        (0x20U)
+#define DMA_EEI_EEI5_SHIFT                       (5U)
+/*! EEI5 - Enable Error Interrupt 5
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
+#define DMA_EEI_EEI6_MASK                        (0x40U)
+#define DMA_EEI_EEI6_SHIFT                       (6U)
+/*! EEI6 - Enable Error Interrupt 6
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
+#define DMA_EEI_EEI7_MASK                        (0x80U)
+#define DMA_EEI_EEI7_SHIFT                       (7U)
+/*! EEI7 - Enable Error Interrupt 7
+ *  0b0..The error signal for corresponding channel does not generate an error interrupt
+ *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
+ */
+#define DMA_EEI_EEI7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
+/*! @} */
+
+/*! @name CEEI - Clear Enable Error Interrupt Register */
+/*! @{ */
+#define DMA_CEEI_CEEI_MASK                       (0x7U)
+#define DMA_CEEI_CEEI_SHIFT                      (0U)
+#define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK                       (0x40U)
+#define DMA_CEEI_CAEE_SHIFT                      (6U)
+/*! CAEE - Clear All Enable Error Interrupts
+ *  0b0..Clear only the EEI bit specified in the CEEI field
+ *  0b1..Clear all bits in EEI
+ */
+#define DMA_CEEI_CAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
+#define DMA_CEEI_NOP_MASK                        (0x80U)
+#define DMA_CEEI_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_CEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
+/*! @} */
+
+/*! @name SEEI - Set Enable Error Interrupt Register */
+/*! @{ */
+#define DMA_SEEI_SEEI_MASK                       (0x7U)
+#define DMA_SEEI_SEEI_SHIFT                      (0U)
+#define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK                       (0x40U)
+#define DMA_SEEI_SAEE_SHIFT                      (6U)
+/*! SAEE - Sets All Enable Error Interrupts
+ *  0b0..Set only the EEI bit specified in the SEEI field.
+ *  0b1..Sets all bits in EEI
+ */
+#define DMA_SEEI_SAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
+#define DMA_SEEI_NOP_MASK                        (0x80U)
+#define DMA_SEEI_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_SEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
+/*! @} */
+
+/*! @name CERQ - Clear Enable Request Register */
+/*! @{ */
+#define DMA_CERQ_CERQ_MASK                       (0x7U)
+#define DMA_CERQ_CERQ_SHIFT                      (0U)
+#define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK                       (0x40U)
+#define DMA_CERQ_CAER_SHIFT                      (6U)
+/*! CAER - Clear All Enable Requests
+ *  0b0..Clear only the ERQ bit specified in the CERQ field
+ *  0b1..Clear all bits in ERQ
+ */
+#define DMA_CERQ_CAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
+#define DMA_CERQ_NOP_MASK                        (0x80U)
+#define DMA_CERQ_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_CERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
+/*! @} */
+
+/*! @name SERQ - Set Enable Request Register */
+/*! @{ */
+#define DMA_SERQ_SERQ_MASK                       (0x7U)
+#define DMA_SERQ_SERQ_SHIFT                      (0U)
+#define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK                       (0x40U)
+#define DMA_SERQ_SAER_SHIFT                      (6U)
+/*! SAER - Set All Enable Requests
+ *  0b0..Set only the ERQ bit specified in the SERQ field
+ *  0b1..Set all bits in ERQ
+ */
+#define DMA_SERQ_SAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
+#define DMA_SERQ_NOP_MASK                        (0x80U)
+#define DMA_SERQ_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_SERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
+/*! @} */
+
+/*! @name CDNE - Clear DONE Status Bit Register */
+/*! @{ */
+#define DMA_CDNE_CDNE_MASK                       (0x7U)
+#define DMA_CDNE_CDNE_SHIFT                      (0U)
+#define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK                       (0x40U)
+#define DMA_CDNE_CADN_SHIFT                      (6U)
+/*! CADN - Clears All DONE Bits
+ *  0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
+ *  0b1..Clears all bits in TCDn_CSR[DONE]
+ */
+#define DMA_CDNE_CADN(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
+#define DMA_CDNE_NOP_MASK                        (0x80U)
+#define DMA_CDNE_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_CDNE_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
+/*! @} */
+
+/*! @name SSRT - Set START Bit Register */
+/*! @{ */
+#define DMA_SSRT_SSRT_MASK                       (0x7U)
+#define DMA_SSRT_SSRT_SHIFT                      (0U)
+#define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK                       (0x40U)
+#define DMA_SSRT_SAST_SHIFT                      (6U)
+/*! SAST - Set All START Bits (activates all channels)
+ *  0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field
+ *  0b1..Set all bits in TCDn_CSR[START]
+ */
+#define DMA_SSRT_SAST(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
+#define DMA_SSRT_NOP_MASK                        (0x80U)
+#define DMA_SSRT_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_SSRT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
+/*! @} */
+
+/*! @name CERR - Clear Error Register */
+/*! @{ */
+#define DMA_CERR_CERR_MASK                       (0x7U)
+#define DMA_CERR_CERR_SHIFT                      (0U)
+#define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK                       (0x40U)
+#define DMA_CERR_CAEI_SHIFT                      (6U)
+/*! CAEI - Clear All Error Indicators
+ *  0b0..Clear only the ERR bit specified in the CERR field
+ *  0b1..Clear all bits in ERR
+ */
+#define DMA_CERR_CAEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
+#define DMA_CERR_NOP_MASK                        (0x80U)
+#define DMA_CERR_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_CERR_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
+/*! @} */
+
+/*! @name CINT - Clear Interrupt Request Register */
+/*! @{ */
+#define DMA_CINT_CINT_MASK                       (0x7U)
+#define DMA_CINT_CINT_SHIFT                      (0U)
+#define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK                       (0x40U)
+#define DMA_CINT_CAIR_SHIFT                      (6U)
+/*! CAIR - Clear All Interrupt Requests
+ *  0b0..Clear only the INT bit specified in the CINT field
+ *  0b1..Clear all bits in INT
+ */
+#define DMA_CINT_CAIR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
+#define DMA_CINT_NOP_MASK                        (0x80U)
+#define DMA_CINT_NOP_SHIFT                       (7U)
+/*! NOP - No Op enable
+ *  0b0..Normal operation
+ *  0b1..No operation, ignore the other bits in this register
+ */
+#define DMA_CINT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
+/*! @} */
+
+/*! @name INT - Interrupt Request Register */
+/*! @{ */
+#define DMA_INT_INT0_MASK                        (0x1U)
+#define DMA_INT_INT0_SHIFT                       (0U)
+/*! INT0 - Interrupt Request 0
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
+#define DMA_INT_INT1_MASK                        (0x2U)
+#define DMA_INT_INT1_SHIFT                       (1U)
+/*! INT1 - Interrupt Request 1
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
+#define DMA_INT_INT2_MASK                        (0x4U)
+#define DMA_INT_INT2_SHIFT                       (2U)
+/*! INT2 - Interrupt Request 2
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
+#define DMA_INT_INT3_MASK                        (0x8U)
+#define DMA_INT_INT3_SHIFT                       (3U)
+/*! INT3 - Interrupt Request 3
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
+#define DMA_INT_INT4_MASK                        (0x10U)
+#define DMA_INT_INT4_SHIFT                       (4U)
+/*! INT4 - Interrupt Request 4
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
+#define DMA_INT_INT5_MASK                        (0x20U)
+#define DMA_INT_INT5_SHIFT                       (5U)
+/*! INT5 - Interrupt Request 5
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
+#define DMA_INT_INT6_MASK                        (0x40U)
+#define DMA_INT_INT6_SHIFT                       (6U)
+/*! INT6 - Interrupt Request 6
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
+#define DMA_INT_INT7_MASK                        (0x80U)
+#define DMA_INT_INT7_SHIFT                       (7U)
+/*! INT7 - Interrupt Request 7
+ *  0b0..The interrupt request for corresponding channel is cleared
+ *  0b1..The interrupt request for corresponding channel is active
+ */
+#define DMA_INT_INT7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
+/*! @} */
+
+/*! @name ERR - Error Register */
+/*! @{ */
+#define DMA_ERR_ERR0_MASK                        (0x1U)
+#define DMA_ERR_ERR0_SHIFT                       (0U)
+/*! ERR0 - Error In Channel 0
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
+#define DMA_ERR_ERR1_MASK                        (0x2U)
+#define DMA_ERR_ERR1_SHIFT                       (1U)
+/*! ERR1 - Error In Channel 1
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
+#define DMA_ERR_ERR2_MASK                        (0x4U)
+#define DMA_ERR_ERR2_SHIFT                       (2U)
+/*! ERR2 - Error In Channel 2
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
+#define DMA_ERR_ERR3_MASK                        (0x8U)
+#define DMA_ERR_ERR3_SHIFT                       (3U)
+/*! ERR3 - Error In Channel 3
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
+#define DMA_ERR_ERR4_MASK                        (0x10U)
+#define DMA_ERR_ERR4_SHIFT                       (4U)
+/*! ERR4 - Error In Channel 4
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
+#define DMA_ERR_ERR5_MASK                        (0x20U)
+#define DMA_ERR_ERR5_SHIFT                       (5U)
+/*! ERR5 - Error In Channel 5
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
+#define DMA_ERR_ERR6_MASK                        (0x40U)
+#define DMA_ERR_ERR6_SHIFT                       (6U)
+/*! ERR6 - Error In Channel 6
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
+#define DMA_ERR_ERR7_MASK                        (0x80U)
+#define DMA_ERR_ERR7_SHIFT                       (7U)
+/*! ERR7 - Error In Channel 7
+ *  0b0..An error in this channel has not occurred
+ *  0b1..An error in this channel has occurred
+ */
+#define DMA_ERR_ERR7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
+/*! @} */
+
+/*! @name HRS - Hardware Request Status Register */
+/*! @{ */
+#define DMA_HRS_HRS0_MASK                        (0x1U)
+#define DMA_HRS_HRS0_SHIFT                       (0U)
+/*! HRS0 - Hardware Request Status Channel 0
+ *  0b0..A hardware service request for channel 0 is not present
+ *  0b1..A hardware service request for channel 0 is present
+ */
+#define DMA_HRS_HRS0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
+#define DMA_HRS_HRS1_MASK                        (0x2U)
+#define DMA_HRS_HRS1_SHIFT                       (1U)
+/*! HRS1 - Hardware Request Status Channel 1
+ *  0b0..A hardware service request for channel 1 is not present
+ *  0b1..A hardware service request for channel 1 is present
+ */
+#define DMA_HRS_HRS1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
+#define DMA_HRS_HRS2_MASK                        (0x4U)
+#define DMA_HRS_HRS2_SHIFT                       (2U)
+/*! HRS2 - Hardware Request Status Channel 2
+ *  0b0..A hardware service request for channel 2 is not present
+ *  0b1..A hardware service request for channel 2 is present
+ */
+#define DMA_HRS_HRS2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
+#define DMA_HRS_HRS3_MASK                        (0x8U)
+#define DMA_HRS_HRS3_SHIFT                       (3U)
+/*! HRS3 - Hardware Request Status Channel 3
+ *  0b0..A hardware service request for channel 3 is not present
+ *  0b1..A hardware service request for channel 3 is present
+ */
+#define DMA_HRS_HRS3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
+#define DMA_HRS_HRS4_MASK                        (0x10U)
+#define DMA_HRS_HRS4_SHIFT                       (4U)
+/*! HRS4 - Hardware Request Status Channel 4
+ *  0b0..A hardware service request for channel 4 is not present
+ *  0b1..A hardware service request for channel 4 is present
+ */
+#define DMA_HRS_HRS4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
+#define DMA_HRS_HRS5_MASK                        (0x20U)
+#define DMA_HRS_HRS5_SHIFT                       (5U)
+/*! HRS5 - Hardware Request Status Channel 5
+ *  0b0..A hardware service request for channel 5 is not present
+ *  0b1..A hardware service request for channel 5 is present
+ */
+#define DMA_HRS_HRS5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
+#define DMA_HRS_HRS6_MASK                        (0x40U)
+#define DMA_HRS_HRS6_SHIFT                       (6U)
+/*! HRS6 - Hardware Request Status Channel 6
+ *  0b0..A hardware service request for channel 6 is not present
+ *  0b1..A hardware service request for channel 6 is present
+ */
+#define DMA_HRS_HRS6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
+#define DMA_HRS_HRS7_MASK                        (0x80U)
+#define DMA_HRS_HRS7_SHIFT                       (7U)
+/*! HRS7 - Hardware Request Status Channel 7
+ *  0b0..A hardware service request for channel 7 is not present
+ *  0b1..A hardware service request for channel 7 is present
+ */
+#define DMA_HRS_HRS7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
+/*! @} */
+
+/*! @name EARS - Enable Asynchronous Request in Stop Register */
+/*! @{ */
+#define DMA_EARS_EDREQ_0_MASK                    (0x1U)
+#define DMA_EARS_EDREQ_0_SHIFT                   (0U)
+/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0.
+ *  0b0..Disable asynchronous DMA request for channel 0.
+ *  0b1..Enable asynchronous DMA request for channel 0.
+ */
+#define DMA_EARS_EDREQ_0(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
+#define DMA_EARS_EDREQ_1_MASK                    (0x2U)
+#define DMA_EARS_EDREQ_1_SHIFT                   (1U)
+/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1.
+ *  0b0..Disable asynchronous DMA request for channel 1
+ *  0b1..Enable asynchronous DMA request for channel 1.
+ */
+#define DMA_EARS_EDREQ_1(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
+#define DMA_EARS_EDREQ_2_MASK                    (0x4U)
+#define DMA_EARS_EDREQ_2_SHIFT                   (2U)
+/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2.
+ *  0b0..Disable asynchronous DMA request for channel 2.
+ *  0b1..Enable asynchronous DMA request for channel 2.
+ */
+#define DMA_EARS_EDREQ_2(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
+#define DMA_EARS_EDREQ_3_MASK                    (0x8U)
+#define DMA_EARS_EDREQ_3_SHIFT                   (3U)
+/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3.
+ *  0b0..Disable asynchronous DMA request for channel 3.
+ *  0b1..Enable asynchronous DMA request for channel 3.
+ */
+#define DMA_EARS_EDREQ_3(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
+#define DMA_EARS_EDREQ_4_MASK                    (0x10U)
+#define DMA_EARS_EDREQ_4_SHIFT                   (4U)
+/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4
+ *  0b0..Disable asynchronous DMA request for channel 4.
+ *  0b1..Enable asynchronous DMA request for channel 4.
+ */
+#define DMA_EARS_EDREQ_4(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
+#define DMA_EARS_EDREQ_5_MASK                    (0x20U)
+#define DMA_EARS_EDREQ_5_SHIFT                   (5U)
+/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5
+ *  0b0..Disable asynchronous DMA request for channel 5.
+ *  0b1..Enable asynchronous DMA request for channel 5.
+ */
+#define DMA_EARS_EDREQ_5(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
+#define DMA_EARS_EDREQ_6_MASK                    (0x40U)
+#define DMA_EARS_EDREQ_6_SHIFT                   (6U)
+/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6
+ *  0b0..Disable asynchronous DMA request for channel 6.
+ *  0b1..Enable asynchronous DMA request for channel 6.
+ */
+#define DMA_EARS_EDREQ_6(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
+#define DMA_EARS_EDREQ_7_MASK                    (0x80U)
+#define DMA_EARS_EDREQ_7_SHIFT                   (7U)
+/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7
+ *  0b0..Disable asynchronous DMA request for channel 7.
+ *  0b1..Enable asynchronous DMA request for channel 7.
+ */
+#define DMA_EARS_EDREQ_7(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
+/*! @} */
+
+/*! @name DCHPRI3 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI3_CHPRI_MASK                   (0x7U)
+#define DMA_DCHPRI3_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI3_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI3_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
+#define DMA_DCHPRI3_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI3_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI3_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI2 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI2_CHPRI_MASK                   (0x7U)
+#define DMA_DCHPRI2_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI2_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI2_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI2_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
+#define DMA_DCHPRI2_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI2_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI2_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI1 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI1_CHPRI_MASK                   (0x7U)
+#define DMA_DCHPRI1_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI1_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI1_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI1_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
+#define DMA_DCHPRI1_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI1_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI1_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI0 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI0_CHPRI_MASK                   (0x7U)
+#define DMA_DCHPRI0_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI0_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI0_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI0_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
+#define DMA_DCHPRI0_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI0_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI0_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI7 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI7_CHPRI_MASK                   (0x7U)
+#define DMA_DCHPRI7_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI7_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
+#define DMA_DCHPRI7_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI7_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI7_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
+#define DMA_DCHPRI7_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI7_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI7_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI6 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI6_CHPRI_MASK                   (0x7U)
+#define DMA_DCHPRI6_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI6_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
+#define DMA_DCHPRI6_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI6_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI6_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
+#define DMA_DCHPRI6_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI6_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI6_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI5 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI5_CHPRI_MASK                   (0x7U)
+#define DMA_DCHPRI5_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI5_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
+#define DMA_DCHPRI5_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI5_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI5_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
+#define DMA_DCHPRI5_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI5_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI5_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
+/*! @} */
+
+/*! @name DCHPRI4 - Channel Priority Register */
+/*! @{ */
+#define DMA_DCHPRI4_CHPRI_MASK                   (0x7U)
+#define DMA_DCHPRI4_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI4_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
+#define DMA_DCHPRI4_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI4_DPA_SHIFT                    (6U)
+/*! DPA - Disable Preempt Ability. This field resets to 0.
+ *  0b0..Channel n can suspend a lower priority channel.
+ *  0b1..Channel n cannot suspend any channel, regardless of channel priority.
+ */
+#define DMA_DCHPRI4_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
+#define DMA_DCHPRI4_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI4_ECP_SHIFT                    (7U)
+/*! ECP - Enable Channel Preemption. This field resets to 0.
+ *  0b0..Channel n cannot be suspended by a higher priority channel's service request.
+ *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
+ */
+#define DMA_DCHPRI4_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
+/*! @} */
+
+/*! @name SADDR - TCD Source Address */
+/*! @{ */
+#define DMA_SADDR_SADDR_MASK                     (0xFFFFFFFFU)
+#define DMA_SADDR_SADDR_SHIFT                    (0U)
+#define DMA_SADDR_SADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
+/*! @} */
+
+/* The count of DMA_SADDR */
+#define DMA_SADDR_COUNT                          (8U)
+
+/*! @name SOFF - TCD Signed Source Address Offset */
+/*! @{ */
+#define DMA_SOFF_SOFF_MASK                       (0xFFFFU)
+#define DMA_SOFF_SOFF_SHIFT                      (0U)
+#define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
+/*! @} */
+
+/* The count of DMA_SOFF */
+#define DMA_SOFF_COUNT                           (8U)
+
+/*! @name ATTR - TCD Transfer Attributes */
+/*! @{ */
+#define DMA_ATTR_DSIZE_MASK                      (0x7U)
+#define DMA_ATTR_DSIZE_SHIFT                     (0U)
+#define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK                       (0xF8U)
+#define DMA_ATTR_DMOD_SHIFT                      (3U)
+#define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK                      (0x700U)
+#define DMA_ATTR_SSIZE_SHIFT                     (8U)
+/*! SSIZE - Source data transfer size
+ *  0b000..8-bit
+ *  0b001..16-bit
+ *  0b010..32-bit
+ *  0b011..Reserved
+ *  0b100..16-byte
+ *  0b101..32-byte
+ *  0b110..Reserved
+ *  0b111..Reserved
+ */
+#define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK                       (0xF800U)
+#define DMA_ATTR_SMOD_SHIFT                      (11U)
+/*! SMOD - Source Address Modulo
+ *  0b00000..Source address modulo feature is disabled
+ *  0b00001-0b11111..This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
+ */
+#define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
+/*! @} */
+
+/* The count of DMA_ATTR */
+#define DMA_ATTR_COUNT                           (8U)
+
+/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
+/*! @{ */
+#define DMA_NBYTES_MLNO_NBYTES_MASK              (0xFFFFFFFFU)
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT             (0U)
+#define DMA_NBYTES_MLNO_NBYTES(x)                (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
+/*! @} */
+
+/* The count of DMA_NBYTES_MLNO */
+#define DMA_NBYTES_MLNO_COUNT                    (8U)
+
+/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
+/*! @{ */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK           (0x3FFFFFFFU)
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT          (0U)
+#define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK            (0x40000000U)
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           (30U)
+/*! DMLOE - Destination Minor Loop Offset enable
+ *  0b0..The minor loop offset is not applied to the DADDR
+ *  0b1..The minor loop offset is applied to the DADDR
+ */
+#define DMA_NBYTES_MLOFFNO_DMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK            (0x80000000U)
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           (31U)
+/*! SMLOE - Source Minor Loop Offset Enable
+ *  0b0..The minor loop offset is not applied to the SADDR
+ *  0b1..The minor loop offset is applied to the SADDR
+ */
+#define DMA_NBYTES_MLOFFNO_SMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
+/*! @} */
+
+/* The count of DMA_NBYTES_MLOFFNO */
+#define DMA_NBYTES_MLOFFNO_COUNT                 (8U)
+
+/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
+/*! @{ */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK          (0x3FFU)
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT         (0U)
+#define DMA_NBYTES_MLOFFYES_NBYTES(x)            (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK           (0x3FFFFC00U)
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          (10U)
+#define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK           (0x40000000U)
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          (30U)
+/*! DMLOE - Destination Minor Loop Offset enable
+ *  0b0..The minor loop offset is not applied to the DADDR
+ *  0b1..The minor loop offset is applied to the DADDR
+ */
+#define DMA_NBYTES_MLOFFYES_DMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK           (0x80000000U)
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          (31U)
+/*! SMLOE - Source Minor Loop Offset Enable
+ *  0b0..The minor loop offset is not applied to the SADDR
+ *  0b1..The minor loop offset is applied to the SADDR
+ */
+#define DMA_NBYTES_MLOFFYES_SMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
+/*! @} */
+
+/* The count of DMA_NBYTES_MLOFFYES */
+#define DMA_NBYTES_MLOFFYES_COUNT                (8U)
+
+/*! @name SLAST - TCD Last Source Address Adjustment */
+/*! @{ */
+#define DMA_SLAST_SLAST_MASK                     (0xFFFFFFFFU)
+#define DMA_SLAST_SLAST_SHIFT                    (0U)
+#define DMA_SLAST_SLAST(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
+/*! @} */
+
+/* The count of DMA_SLAST */
+#define DMA_SLAST_COUNT                          (8U)
+
+/*! @name DADDR - TCD Destination Address */
+/*! @{ */
+#define DMA_DADDR_DADDR_MASK                     (0xFFFFFFFFU)
+#define DMA_DADDR_DADDR_SHIFT                    (0U)
+#define DMA_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
+/*! @} */
+
+/* The count of DMA_DADDR */
+#define DMA_DADDR_COUNT                          (8U)
+
+/*! @name DOFF - TCD Signed Destination Address Offset */
+/*! @{ */
+#define DMA_DOFF_DOFF_MASK                       (0xFFFFU)
+#define DMA_DOFF_DOFF_SHIFT                      (0U)
+#define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
+/*! @} */
+
+/* The count of DMA_DOFF */
+#define DMA_DOFF_COUNT                           (8U)
+
+/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
+/*! @{ */
+#define DMA_CITER_ELINKNO_CITER_MASK             (0x7FFFU)
+#define DMA_CITER_ELINKNO_CITER_SHIFT            (0U)
+#define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK             (0x8000U)
+#define DMA_CITER_ELINKNO_ELINK_SHIFT            (15U)
+/*! ELINK - Enable channel-to-channel linking on minor-loop complete
+ *  0b0..The channel-to-channel linking is disabled
+ *  0b1..The channel-to-channel linking is enabled
+ */
+#define DMA_CITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
+/*! @} */
+
+/* The count of DMA_CITER_ELINKNO */
+#define DMA_CITER_ELINKNO_COUNT                  (8U)
+
+/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
+/*! @{ */
+#define DMA_CITER_ELINKYES_CITER_MASK            (0x1FFU)
+#define DMA_CITER_ELINKYES_CITER_SHIFT           (0U)
+#define DMA_CITER_ELINKYES_CITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK           (0xE00U)
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT          (9U)
+#define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK            (0x8000U)
+#define DMA_CITER_ELINKYES_ELINK_SHIFT           (15U)
+/*! ELINK - Enable channel-to-channel linking on minor-loop complete
+ *  0b0..The channel-to-channel linking is disabled
+ *  0b1..The channel-to-channel linking is enabled
+ */
+#define DMA_CITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
+/*! @} */
+
+/* The count of DMA_CITER_ELINKYES */
+#define DMA_CITER_ELINKYES_COUNT                 (8U)
+
+/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
+/*! @{ */
+#define DMA_DLAST_SGA_DLASTSGA_MASK              (0xFFFFFFFFU)
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT             (0U)
+#define DMA_DLAST_SGA_DLASTSGA(x)                (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
+/*! @} */
+
+/* The count of DMA_DLAST_SGA */
+#define DMA_DLAST_SGA_COUNT                      (8U)
+
+/*! @name CSR - TCD Control and Status */
+/*! @{ */
+#define DMA_CSR_START_MASK                       (0x1U)
+#define DMA_CSR_START_SHIFT                      (0U)
+/*! START - Channel Start
+ *  0b0..The channel is not explicitly started.
+ *  0b1..The channel is explicitly started via a software initiated service request.
+ */
+#define DMA_CSR_START(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
+#define DMA_CSR_INTMAJOR_MASK                    (0x2U)
+#define DMA_CSR_INTMAJOR_SHIFT                   (1U)
+/*! INTMAJOR - Enable an interrupt when major iteration count completes.
+ *  0b0..The end-of-major loop interrupt is disabled.
+ *  0b1..The end-of-major loop interrupt is enabled.
+ */
+#define DMA_CSR_INTMAJOR(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
+#define DMA_CSR_INTHALF_MASK                     (0x4U)
+#define DMA_CSR_INTHALF_SHIFT                    (2U)
+/*! INTHALF - Enable an interrupt when major counter is half complete.
+ *  0b0..The half-point interrupt is disabled.
+ *  0b1..The half-point interrupt is enabled.
+ */
+#define DMA_CSR_INTHALF(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
+#define DMA_CSR_DREQ_MASK                        (0x8U)
+#define DMA_CSR_DREQ_SHIFT                       (3U)
+/*! DREQ - Disable Request
+ *  0b0..The channel's ERQ bit is not affected.
+ *  0b1..The channel's ERQ bit is cleared when the major loop is complete.
+ */
+#define DMA_CSR_DREQ(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
+#define DMA_CSR_ESG_MASK                         (0x10U)
+#define DMA_CSR_ESG_SHIFT                        (4U)
+/*! ESG - Enable Scatter/Gather Processing
+ *  0b0..The current channel's TCD is normal format.
+ *  0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
+ */
+#define DMA_CSR_ESG(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
+#define DMA_CSR_MAJORELINK_MASK                  (0x20U)
+#define DMA_CSR_MAJORELINK_SHIFT                 (5U)
+/*! MAJORELINK - Enable channel-to-channel linking on major loop complete
+ *  0b0..The channel-to-channel linking is disabled.
+ *  0b1..The channel-to-channel linking is enabled.
+ */
+#define DMA_CSR_MAJORELINK(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
+#define DMA_CSR_ACTIVE_MASK                      (0x40U)
+#define DMA_CSR_ACTIVE_SHIFT                     (6U)
+#define DMA_CSR_ACTIVE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
+#define DMA_CSR_DONE_MASK                        (0x80U)
+#define DMA_CSR_DONE_SHIFT                       (7U)
+#define DMA_CSR_DONE(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
+#define DMA_CSR_MAJORLINKCH_MASK                 (0x700U)
+#define DMA_CSR_MAJORLINKCH_SHIFT                (8U)
+#define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK                         (0xC000U)
+#define DMA_CSR_BWC_SHIFT                        (14U)
+/*! BWC - Bandwidth Control
+ *  0b00..No eDMA engine stalls.
+ *  0b01..Reserved
+ *  0b10..eDMA engine stalls for 4 cycles after each R/W.
+ *  0b11..eDMA engine stalls for 8 cycles after each R/W.
+ */
+#define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
+/*! @} */
+
+/* The count of DMA_CSR */
+#define DMA_CSR_COUNT                            (8U)
+
+/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
+/*! @{ */
+#define DMA_BITER_ELINKNO_BITER_MASK             (0x7FFFU)
+#define DMA_BITER_ELINKNO_BITER_SHIFT            (0U)
+#define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK             (0x8000U)
+#define DMA_BITER_ELINKNO_ELINK_SHIFT            (15U)
+/*! ELINK - Enables channel-to-channel linking on minor loop complete
+ *  0b0..The channel-to-channel linking is disabled
+ *  0b1..The channel-to-channel linking is enabled
+ */
+#define DMA_BITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
+/*! @} */
+
+/* The count of DMA_BITER_ELINKNO */
+#define DMA_BITER_ELINKNO_COUNT                  (8U)
+
+/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
+/*! @{ */
+#define DMA_BITER_ELINKYES_BITER_MASK            (0x1FFU)
+#define DMA_BITER_ELINKYES_BITER_SHIFT           (0U)
+#define DMA_BITER_ELINKYES_BITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK           (0xE00U)
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT          (9U)
+#define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK            (0x8000U)
+#define DMA_BITER_ELINKYES_ELINK_SHIFT           (15U)
+/*! ELINK - Enables channel-to-channel linking on minor loop complete
+ *  0b0..The channel-to-channel linking is disabled
+ *  0b1..The channel-to-channel linking is enabled
+ */
+#define DMA_BITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
+/*! @} */
+
+/* The count of DMA_BITER_ELINKYES */
+#define DMA_BITER_ELINKYES_COUNT                 (8U)
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA1 base address */
+#define DMA1_BASE                                (0x41008000u)
+/** Peripheral DMA1 base pointer */
+#define DMA1                                     ((DMA_Type *)DMA1_BASE)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS                           { 0u, DMA1_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS                            { (DMA_Type *)0u, DMA1 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS                             { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { DMA1_04_IRQn, DMA1_15_IRQn, DMA1_26_IRQn, DMA1_37_IRQn, DMA1_04_IRQn, DMA1_15_IRQn, DMA1_26_IRQn, DMA1_37_IRQn } }
+#define DMA_ERROR_IRQS                           { NotAvail_IRQn, DMA1_Error_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CHCFG[8];                          /**< Channel 0 Configuration Register..Channel 7 Configuration Register, array offset: 0x0, array step: 0x4 */
+} DMAMUX_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/*! @name CHCFG - Channel 0 Configuration Register..Channel 7 Configuration Register */
+/*! @{ */
+#define DMAMUX_CHCFG_SOURCE_MASK                 (0x1FU)
+#define DMAMUX_CHCFG_SOURCE_SHIFT                (0U)
+#define DMAMUX_CHCFG_SOURCE(x)                   (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_A_ON_MASK                   (0x20000000U)
+#define DMAMUX_CHCFG_A_ON_SHIFT                  (29U)
+/*! A_ON - DMA Channel Always Enable
+ *  0b0..DMA Channel Always ON function is disabled
+ *  0b1..DMA Channel Always ON function is enabled
+ */
+#define DMAMUX_CHCFG_A_ON(x)                     (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK                   (0x40000000U)
+#define DMAMUX_CHCFG_TRIG_SHIFT                  (30U)
+/*! TRIG - DMA Channel Trigger Enable
+ *  0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
+ *  0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
+ */
+#define DMAMUX_CHCFG_TRIG(x)                     (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
+#define DMAMUX_CHCFG_ENBL_MASK                   (0x80000000U)
+#define DMAMUX_CHCFG_ENBL_SHIFT                  (31U)
+/*! ENBL - DMA Mux Channel Enable
+ *  0b0..DMA Mux channel is disabled
+ *  0b1..DMA Mux channel is enabled
+ */
+#define DMAMUX_CHCFG_ENBL(x)                     (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
+/*! @} */
+
+/* The count of DMAMUX_CHCFG */
+#define DMAMUX_CHCFG_COUNT                       (8U)
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX1 base address */
+#define DMAMUX1_BASE                             (0x41021000u)
+/** Peripheral DMAMUX1 base pointer */
+#define DMAMUX1                                  ((DMAMUX_Type *)DMAMUX1_BASE)
+/** Array initializer of DMAMUX peripheral base addresses */
+#define DMAMUX_BASE_ADDRS                        { 0u, DMAMUX1_BASE }
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASE_PTRS                         { (DMAMUX_Type *)0u, DMAMUX1 }
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EMVSIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer
+ * @{
+ */
+
+/** EMVSIM - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VER_ID;                            /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __IO uint32_t CLKCFG;                            /**< Clock Configuration Register, offset: 0x8 */
+  __IO uint32_t DIVISOR;                           /**< Baud Rate Divisor Register, offset: 0xC */
+  __IO uint32_t CTRL;                              /**< Control Register, offset: 0x10 */
+  __IO uint32_t INT_MASK;                          /**< Interrupt Mask Register, offset: 0x14 */
+  __IO uint32_t RX_THD;                            /**< Receiver Threshold Register, offset: 0x18 */
+  __IO uint32_t TX_THD;                            /**< Transmitter Threshold Register, offset: 0x1C */
+  __IO uint32_t RX_STATUS;                         /**< Receive Status Register, offset: 0x20 */
+  __IO uint32_t TX_STATUS;                         /**< Transmitter Status Register, offset: 0x24 */
+  __IO uint32_t PCSR;                              /**< Port Control and Status Register, offset: 0x28 */
+  __I  uint32_t RX_BUF;                            /**< Receive Data Read Buffer, offset: 0x2C */
+  __O  uint32_t TX_BUF;                            /**< Transmit Data Buffer, offset: 0x30 */
+  __IO uint32_t TX_GETU;                           /**< Transmitter Guard ETU Value Register, offset: 0x34 */
+  __IO uint32_t CWT_VAL;                           /**< Character Wait Time Value Register, offset: 0x38 */
+  __IO uint32_t BWT_VAL;                           /**< Block Wait Time Value Register, offset: 0x3C */
+  __IO uint32_t BGT_VAL;                           /**< Block Guard Time Value Register, offset: 0x40 */
+  __IO uint32_t GPCNT0_VAL;                        /**< General Purpose Counter 0 Timeout Value Register, offset: 0x44 */
+  __IO uint32_t GPCNT1_VAL;                        /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */
+} EMVSIM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- EMVSIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks
+ * @{
+ */
+
+/*! @name VER_ID - Version ID Register */
+/*! @{ */
+#define EMVSIM_VER_ID_VER_MASK                   (0xFFFFFFFFU)
+#define EMVSIM_VER_ID_VER_SHIFT                  (0U)
+#define EMVSIM_VER_ID_VER(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK          (0xFFU)
+#define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT         (0U)
+#define EMVSIM_PARAM_RX_FIFO_DEPTH(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)
+#define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK          (0xFF00U)
+#define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT         (8U)
+#define EMVSIM_PARAM_TX_FIFO_DEPTH(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)
+/*! @} */
+
+/*! @name CLKCFG - Clock Configuration Register */
+/*! @{ */
+#define EMVSIM_CLKCFG_CLK_PRSC_MASK              (0xFFU)
+#define EMVSIM_CLKCFG_CLK_PRSC_SHIFT             (0U)
+/*! CLK_PRSC - Clock Prescaler Value
+ *  0b00000010..Divide by 2
+ */
+#define EMVSIM_CLKCFG_CLK_PRSC(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK)
+#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK        (0x300U)
+#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT       (8U)
+/*! GPCNT1_CLK_SEL - General Purpose Counter 1 Clock Select
+ *  0b00..Disabled / Reset (default)
+ *  0b01..Card Clock
+ *  0b10..Receive Clock
+ *  0b11..ETU Clock (transmit clock)
+ */
+#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK)
+#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK        (0xC00U)
+#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT       (10U)
+/*! GPCNT0_CLK_SEL - General Purpose Counter 0 Clock Select
+ *  0b00..Disabled / Reset (default)
+ *  0b01..Card Clock
+ *  0b10..Receive Clock
+ *  0b11..ETU Clock (transmit clock)
+ */
+#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK)
+/*! @} */
+
+/*! @name DIVISOR - Baud Rate Divisor Register */
+/*! @{ */
+#define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK        (0x1FFU)
+#define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT       (0U)
+/*! DIVISOR_VALUE - Divisor (F/D) Value
+ *  0b000000000-0b000000100..Invalid. As per ISO 7816 specification, minimum value of F/D is 5
+ *  0b101110100..Divisor value for F = 372 and D = 1 (default)
+ */
+#define EMVSIM_DIVISOR_DIVISOR_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK)
+/*! @} */
+
+/*! @name CTRL - Control Register */
+/*! @{ */
+#define EMVSIM_CTRL_IC_MASK                      (0x1U)
+#define EMVSIM_CTRL_IC_SHIFT                     (0U)
+/*! IC - Inverse Convention
+ *  0b0..Direction convention transfers enabled (default)
+ *  0b1..Inverse convention transfers enabled
+ */
+#define EMVSIM_CTRL_IC(x)                        (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK)
+#define EMVSIM_CTRL_ICM_MASK                     (0x2U)
+#define EMVSIM_CTRL_ICM_SHIFT                    (1U)
+/*! ICM - Initial Character Mode
+ *  0b0..Initial Character Mode disabled
+ *  0b1..Initial Character Mode enabled (default)
+ */
+#define EMVSIM_CTRL_ICM(x)                       (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK)
+#define EMVSIM_CTRL_ANACK_MASK                   (0x4U)
+#define EMVSIM_CTRL_ANACK_SHIFT                  (2U)
+/*! ANACK - Auto NACK Enable
+ *  0b0..NACK generation on errors disabled
+ *  0b1..NACK generation on errors enabled (default)
+ */
+#define EMVSIM_CTRL_ANACK(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK)
+#define EMVSIM_CTRL_ONACK_MASK                   (0x8U)
+#define EMVSIM_CTRL_ONACK_SHIFT                  (3U)
+/*! ONACK - Overrun NACK Enable
+ *  0b0..NACK generation on overrun is disabled (default)
+ *  0b1..NACK generation on overrun is enabled
+ */
+#define EMVSIM_CTRL_ONACK(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK)
+#define EMVSIM_CTRL_FLSH_RX_MASK                 (0x100U)
+#define EMVSIM_CTRL_FLSH_RX_SHIFT                (8U)
+/*! FLSH_RX - Flush Receiver Bit
+ *  0b0..EMV SIM Receiver normal operation (default)
+ *  0b1..EMV SIM Receiver held in Reset
+ */
+#define EMVSIM_CTRL_FLSH_RX(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK)
+#define EMVSIM_CTRL_FLSH_TX_MASK                 (0x200U)
+#define EMVSIM_CTRL_FLSH_TX_SHIFT                (9U)
+/*! FLSH_TX - Flush Transmitter Bit
+ *  0b0..EMV SIM Transmitter normal operation (default)
+ *  0b1..EMV SIM Transmitter held in Reset
+ */
+#define EMVSIM_CTRL_FLSH_TX(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK)
+#define EMVSIM_CTRL_SW_RST_MASK                  (0x400U)
+#define EMVSIM_CTRL_SW_RST_SHIFT                 (10U)
+/*! SW_RST - Software Reset Bit
+ *  0b0..EMV SIM Normal operation (default)
+ *  0b1..EMV SIM held in Reset
+ */
+#define EMVSIM_CTRL_SW_RST(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK)
+#define EMVSIM_CTRL_KILL_CLOCKS_MASK             (0x800U)
+#define EMVSIM_CTRL_KILL_CLOCKS_SHIFT            (11U)
+/*! KILL_CLOCKS - Kill all internal clocks
+ *  0b0..EMV SIM input clock enabled (default)
+ *  0b1..EMV SIM input clock is disabled
+ */
+#define EMVSIM_CTRL_KILL_CLOCKS(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK)
+#define EMVSIM_CTRL_DOZE_EN_MASK                 (0x1000U)
+#define EMVSIM_CTRL_DOZE_EN_SHIFT                (12U)
+/*! DOZE_EN - Doze Enable
+ *  0b0..DOZE instruction will gate all internal EMV SIM clocks as well as the Smart Card clock when the transmit FIFO is empty (default)
+ *  0b1..DOZE instruction has no effect on EMV SIM module
+ */
+#define EMVSIM_CTRL_DOZE_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK)
+#define EMVSIM_CTRL_STOP_EN_MASK                 (0x2000U)
+#define EMVSIM_CTRL_STOP_EN_SHIFT                (13U)
+/*! STOP_EN - STOP Enable
+ *  0b0..STOP instruction shuts down all EMV SIM clocks (default)
+ *  0b1..STOP instruction shuts down all clocks except for the Smart Card Clock (SCK) (clock provided to Smart Card)
+ */
+#define EMVSIM_CTRL_STOP_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK)
+#define EMVSIM_CTRL_RCV_EN_MASK                  (0x10000U)
+#define EMVSIM_CTRL_RCV_EN_SHIFT                 (16U)
+/*! RCV_EN - Receiver Enable
+ *  0b0..EMV SIM Receiver disabled (default)
+ *  0b1..EMV SIM Receiver enabled
+ */
+#define EMVSIM_CTRL_RCV_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK)
+#define EMVSIM_CTRL_XMT_EN_MASK                  (0x20000U)
+#define EMVSIM_CTRL_XMT_EN_SHIFT                 (17U)
+/*! XMT_EN - Transmitter Enable
+ *  0b0..EMV SIM Transmitter disabled (default)
+ *  0b1..EMV SIM Transmitter enabled
+ */
+#define EMVSIM_CTRL_XMT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK)
+#define EMVSIM_CTRL_RCVR_11_MASK                 (0x40000U)
+#define EMVSIM_CTRL_RCVR_11_SHIFT                (18U)
+/*! RCVR_11 - Receiver 11 ETU Mode Enable
+ *  0b0..Receiver configured for 12 ETU operation mode (default)
+ *  0b1..Receiver configured for 11 ETU operation mode
+ */
+#define EMVSIM_CTRL_RCVR_11(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
+#define EMVSIM_CTRL_RX_DMA_EN_MASK               (0x80000U)
+#define EMVSIM_CTRL_RX_DMA_EN_SHIFT              (19U)
+/*! RX_DMA_EN - Receive DMA Enable
+ *  0b0..No DMA Read Request asserted for Receiver (default)
+ *  0b1..DMA Read Request asserted for Receiver
+ */
+#define EMVSIM_CTRL_RX_DMA_EN(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK)
+#define EMVSIM_CTRL_TX_DMA_EN_MASK               (0x100000U)
+#define EMVSIM_CTRL_TX_DMA_EN_SHIFT              (20U)
+/*! TX_DMA_EN - Transmit DMA Enable
+ *  0b0..No DMA Write Request asserted for Transmitter (default)
+ *  0b1..DMA Write Request asserted for Transmitter
+ */
+#define EMVSIM_CTRL_TX_DMA_EN(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK)
+#define EMVSIM_CTRL_INV_CRC_VAL_MASK             (0x1000000U)
+#define EMVSIM_CTRL_INV_CRC_VAL_SHIFT            (24U)
+/*! INV_CRC_VAL - Invert bits in the CRC Output Value
+ *  0b0..Bits in CRC Output value will not be inverted.
+ *  0b1..Bits in CRC Output value will be inverted. (default)
+ */
+#define EMVSIM_CTRL_INV_CRC_VAL(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK)
+#define EMVSIM_CTRL_CRC_OUT_FLIP_MASK            (0x2000000U)
+#define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT           (25U)
+/*! CRC_OUT_FLIP - CRC Output Value Bit Reversal or Flip
+ *  0b0..Bits within the CRC output bytes will not be reversed i.e. 15:0 will remain 15:0 (default)
+ *  0b1..Bits within the CRC output bytes will be reversed i.e. 15:0 will become {8:15,0:7}
+ */
+#define EMVSIM_CTRL_CRC_OUT_FLIP(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK)
+#define EMVSIM_CTRL_CRC_IN_FLIP_MASK             (0x4000000U)
+#define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT            (26U)
+/*! CRC_IN_FLIP - CRC Input Byte's Bit Reversal or Flip Control
+ *  0b0..Bits in the input byte will not be reversed (i.e. 7:0 will remain 7:0) before the CRC calculation (default)
+ *  0b1..Bits in the input byte will be reversed (i.e. 7:0 will become 0:7) before CRC calculation
+ */
+#define EMVSIM_CTRL_CRC_IN_FLIP(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK)
+#define EMVSIM_CTRL_CWT_EN_MASK                  (0x8000000U)
+#define EMVSIM_CTRL_CWT_EN_SHIFT                 (27U)
+/*! CWT_EN - Character Wait Time Counter Enable
+ *  0b0..Character Wait time Counter is disabled (default)
+ *  0b1..Character Wait time counter is enabled
+ */
+#define EMVSIM_CTRL_CWT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK)
+#define EMVSIM_CTRL_LRC_EN_MASK                  (0x10000000U)
+#define EMVSIM_CTRL_LRC_EN_SHIFT                 (28U)
+/*! LRC_EN - LRC Enable
+ *  0b0..8-bit Linear Redundancy Checking disabled (default)
+ *  0b1..8-bit Linear Redundancy Checking enabled
+ */
+#define EMVSIM_CTRL_LRC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK)
+#define EMVSIM_CTRL_CRC_EN_MASK                  (0x20000000U)
+#define EMVSIM_CTRL_CRC_EN_SHIFT                 (29U)
+/*! CRC_EN - CRC Enable
+ *  0b0..16-bit Cyclic Redundancy Checking disabled (default)
+ *  0b1..16-bit Cyclic Redundancy Checking enabled
+ */
+#define EMVSIM_CTRL_CRC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK)
+#define EMVSIM_CTRL_XMT_CRC_LRC_MASK             (0x40000000U)
+#define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT            (30U)
+/*! XMT_CRC_LRC - Transmit CRC or LRC Enable
+ *  0b0..No CRC or LRC value is transmitted (default)
+ *  0b1..Transmit LRC or CRC info when FIFO empties (whichever is enabled)
+ */
+#define EMVSIM_CTRL_XMT_CRC_LRC(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK)
+#define EMVSIM_CTRL_BWT_EN_MASK                  (0x80000000U)
+#define EMVSIM_CTRL_BWT_EN_SHIFT                 (31U)
+/*! BWT_EN - Block Wait Time Counter Enable
+ *  0b0..Disable BWT, BGT Counters (default)
+ *  0b1..Enable BWT, BGT Counters
+ */
+#define EMVSIM_CTRL_BWT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK)
+/*! @} */
+
+/*! @name INT_MASK - Interrupt Mask Register */
+/*! @{ */
+#define EMVSIM_INT_MASK_RDT_IM_MASK              (0x1U)
+#define EMVSIM_INT_MASK_RDT_IM_SHIFT             (0U)
+/*! RDT_IM - Receive Data Threshold Interrupt Mask
+ *  0b0..RDTF interrupt enabled
+ *  0b1..RDTF interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_RDT_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK)
+#define EMVSIM_INT_MASK_TC_IM_MASK               (0x2U)
+#define EMVSIM_INT_MASK_TC_IM_SHIFT              (1U)
+/*! TC_IM - Transmit Complete Interrupt Mask
+ *  0b0..TCF interrupt enabled
+ *  0b1..TCF interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_TC_IM(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK)
+#define EMVSIM_INT_MASK_RFO_IM_MASK              (0x4U)
+#define EMVSIM_INT_MASK_RFO_IM_SHIFT             (2U)
+/*! RFO_IM - Receive FIFO Overflow Interrupt Mask
+ *  0b0..RFO interrupt enabled
+ *  0b1..RFO interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_RFO_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK)
+#define EMVSIM_INT_MASK_ETC_IM_MASK              (0x8U)
+#define EMVSIM_INT_MASK_ETC_IM_SHIFT             (3U)
+/*! ETC_IM - Early Transmit Complete Interrupt Mask
+ *  0b0..ETC interrupt enabled
+ *  0b1..ETC interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_ETC_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK)
+#define EMVSIM_INT_MASK_TFE_IM_MASK              (0x10U)
+#define EMVSIM_INT_MASK_TFE_IM_SHIFT             (4U)
+/*! TFE_IM - Transmit FIFO Empty Interrupt Mask
+ *  0b0..TFE interrupt enabled
+ *  0b1..TFE interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_TFE_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK)
+#define EMVSIM_INT_MASK_TNACK_IM_MASK            (0x20U)
+#define EMVSIM_INT_MASK_TNACK_IM_SHIFT           (5U)
+/*! TNACK_IM - Transmit NACK Threshold Interrupt Mask
+ *  0b0..TNTE interrupt enabled
+ *  0b1..TNTE interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_TNACK_IM(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK)
+#define EMVSIM_INT_MASK_TFF_IM_MASK              (0x40U)
+#define EMVSIM_INT_MASK_TFF_IM_SHIFT             (6U)
+/*! TFF_IM - Transmit FIFO Full Interrupt Mask
+ *  0b0..TFF interrupt enabled
+ *  0b1..TFF interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_TFF_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK)
+#define EMVSIM_INT_MASK_TDT_IM_MASK              (0x80U)
+#define EMVSIM_INT_MASK_TDT_IM_SHIFT             (7U)
+/*! TDT_IM - Transmit Data Threshold Interrupt Mask
+ *  0b0..TDTF interrupt enabled
+ *  0b1..TDTF interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_TDT_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK)
+#define EMVSIM_INT_MASK_GPCNT0_IM_MASK           (0x100U)
+#define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT          (8U)
+/*! GPCNT0_IM - General Purpose Timer 0 Timeout Interrupt Mask
+ *  0b0..GPCNT0_TO interrupt enabled
+ *  0b1..GPCNT0_TO interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_GPCNT0_IM(x)             (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK)
+#define EMVSIM_INT_MASK_CWT_ERR_IM_MASK          (0x200U)
+#define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT         (9U)
+/*! CWT_ERR_IM - Character Wait Time Error Interrupt Mask
+ *  0b0..CWT_ERR interrupt enabled
+ *  0b1..CWT_ERR interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_CWT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK)
+#define EMVSIM_INT_MASK_RNACK_IM_MASK            (0x400U)
+#define EMVSIM_INT_MASK_RNACK_IM_SHIFT           (10U)
+/*! RNACK_IM - Receiver NACK Threshold Interrupt Mask
+ *  0b0..RTE interrupt enabled
+ *  0b1..RTE interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_RNACK_IM(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK)
+#define EMVSIM_INT_MASK_BWT_ERR_IM_MASK          (0x800U)
+#define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT         (11U)
+/*! BWT_ERR_IM - Block Wait Time Error Interrupt Mask
+ *  0b0..BWT_ERR interrupt enabled
+ *  0b1..BWT_ERR interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_BWT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK)
+#define EMVSIM_INT_MASK_BGT_ERR_IM_MASK          (0x1000U)
+#define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT         (12U)
+/*! BGT_ERR_IM - Block Guard Time Error Interrupt
+ *  0b0..BGT_ERR interrupt enabled
+ *  0b1..BGT_ERR interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_BGT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK)
+#define EMVSIM_INT_MASK_GPCNT1_IM_MASK           (0x2000U)
+#define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT          (13U)
+/*! GPCNT1_IM - General Purpose Counter 1 Timeout Interrupt Mask
+ *  0b0..GPCNT1_TO interrupt enabled
+ *  0b1..GPCNT1_TO interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_GPCNT1_IM(x)             (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK)
+#define EMVSIM_INT_MASK_RX_DATA_IM_MASK          (0x4000U)
+#define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT         (14U)
+/*! RX_DATA_IM - Receive Data Interrupt Mask
+ *  0b0..RX_DATA interrupt enabled
+ *  0b1..RX_DATA interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_RX_DATA_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK)
+#define EMVSIM_INT_MASK_PEF_IM_MASK              (0x8000U)
+#define EMVSIM_INT_MASK_PEF_IM_SHIFT             (15U)
+/*! PEF_IM - Parity Error Interrupt Mask
+ *  0b0..PEF interrupt enabled
+ *  0b1..PEF interrupt masked (default)
+ */
+#define EMVSIM_INT_MASK_PEF_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
+/*! @} */
+
+/*! @name RX_THD - Receiver Threshold Register */
+/*! @{ */
+#define EMVSIM_RX_THD_RDT_MASK                   (0xFU)
+#define EMVSIM_RX_THD_RDT_SHIFT                  (0U)
+#define EMVSIM_RX_THD_RDT(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
+#define EMVSIM_RX_THD_RNCK_THD_MASK              (0xF00U)
+#define EMVSIM_RX_THD_RNCK_THD_SHIFT             (8U)
+/*! RNCK_THD - Receiver NACK Threshold Value
+ *  0b0000..Zero Threshold. RTE will not be set
+ */
+#define EMVSIM_RX_THD_RNCK_THD(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK)
+/*! @} */
+
+/*! @name TX_THD - Transmitter Threshold Register */
+/*! @{ */
+#define EMVSIM_TX_THD_TDT_MASK                   (0xFU)
+#define EMVSIM_TX_THD_TDT_SHIFT                  (0U)
+#define EMVSIM_TX_THD_TDT(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK)
+#define EMVSIM_TX_THD_TNCK_THD_MASK              (0xF00U)
+#define EMVSIM_TX_THD_TNCK_THD_SHIFT             (8U)
+/*! TNCK_THD - Transmitter NACK Threshold Value
+ *  0b0000..TNTE will never be set; retransmission after NACK reception is disabled.
+ *  0b0001..TNTE will be set after 1 nack is received; 0 retransmissions occurs.
+ *  0b0010..TNTE will be set after 2 nacks are received; at most 1 retransmission occurs.
+ *  0b0011..TNTE will be set after 3 nacks are received; at most 2 retransmissions occurs.
+ *  0b1111..TNTE will be set after 15 nacks are received; at most 14 retransmissions occurs.
+ */
+#define EMVSIM_TX_THD_TNCK_THD(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK)
+/*! @} */
+
+/*! @name RX_STATUS - Receive Status Register */
+/*! @{ */
+#define EMVSIM_RX_STATUS_RFO_MASK                (0x1U)
+#define EMVSIM_RX_STATUS_RFO_SHIFT               (0U)
+/*! RFO - Receive FIFO Overflow Flag
+ *  0b0..No overrun error has occurred (default)
+ *  0b1..A byte was received when the received FIFO was already full
+ */
+#define EMVSIM_RX_STATUS_RFO(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK)
+#define EMVSIM_RX_STATUS_RX_DATA_MASK            (0x10U)
+#define EMVSIM_RX_STATUS_RX_DATA_SHIFT           (4U)
+/*! RX_DATA - Receive Data Interrupt Flag
+ *  0b0..No new byte is received
+ *  0b1..New byte is received ans stored in Receive FIFO
+ */
+#define EMVSIM_RX_STATUS_RX_DATA(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK)
+#define EMVSIM_RX_STATUS_RDTF_MASK               (0x20U)
+#define EMVSIM_RX_STATUS_RDTF_SHIFT              (5U)
+/*! RDTF - Receive Data Threshold Interrupt Flag
+ *  0b0..Number of unread bytes in receive FIFO less than the value set by RDT[3:0] (default).
+ *  0b1..Number of unread bytes in receive FIFO greater or than equal to value set by RDT[3:0].
+ */
+#define EMVSIM_RX_STATUS_RDTF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK)
+#define EMVSIM_RX_STATUS_LRC_OK_MASK             (0x40U)
+#define EMVSIM_RX_STATUS_LRC_OK_SHIFT            (6U)
+/*! LRC_OK - LRC Check OK Flag
+ *  0b0..Current LRC value does not match remainder.
+ *  0b1..Current calculated LRC value matches the expected result (i.e. zero).
+ */
+#define EMVSIM_RX_STATUS_LRC_OK(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK)
+#define EMVSIM_RX_STATUS_CRC_OK_MASK             (0x80U)
+#define EMVSIM_RX_STATUS_CRC_OK_SHIFT            (7U)
+/*! CRC_OK - CRC Check OK Flag
+ *  0b0..Current CRC value does not match remainder.
+ *  0b1..Current calculated CRC value matches the expected result.
+ */
+#define EMVSIM_RX_STATUS_CRC_OK(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK)
+#define EMVSIM_RX_STATUS_CWT_ERR_MASK            (0x100U)
+#define EMVSIM_RX_STATUS_CWT_ERR_SHIFT           (8U)
+/*! CWT_ERR - Character Wait Time Error Flag
+ *  0b0..No CWT violation has occurred (default).
+ *  0b1..Time between two consecutive characters has exceeded the value in CHAR_WAIT.
+ */
+#define EMVSIM_RX_STATUS_CWT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK)
+#define EMVSIM_RX_STATUS_RTE_MASK                (0x200U)
+#define EMVSIM_RX_STATUS_RTE_SHIFT               (9U)
+/*! RTE - Received NACK Threshold Error Flag
+ *  0b0..Number of NACKs generated by the receiver is less than the value programmed in RTH[3:0]
+ *  0b1..Number of NACKs generated by the receiver is equal to the value programmed in RTH[3:0]
+ */
+#define EMVSIM_RX_STATUS_RTE(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK)
+#define EMVSIM_RX_STATUS_BWT_ERR_MASK            (0x400U)
+#define EMVSIM_RX_STATUS_BWT_ERR_SHIFT           (10U)
+/*! BWT_ERR - Block Wait Time Error Flag
+ *  0b0..Block wait time not exceeded
+ *  0b1..Block wait time was exceeded
+ */
+#define EMVSIM_RX_STATUS_BWT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK)
+#define EMVSIM_RX_STATUS_BGT_ERR_MASK            (0x800U)
+#define EMVSIM_RX_STATUS_BGT_ERR_SHIFT           (11U)
+/*! BGT_ERR - Block Guard Time Error Flag
+ *  0b0..Block guard time was sufficient
+ *  0b1..Block guard time was too small
+ */
+#define EMVSIM_RX_STATUS_BGT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK)
+#define EMVSIM_RX_STATUS_PEF_MASK                (0x1000U)
+#define EMVSIM_RX_STATUS_PEF_SHIFT               (12U)
+/*! PEF - Parity Error Flag
+ *  0b0..No parity error detected
+ *  0b1..Parity error detected
+ */
+#define EMVSIM_RX_STATUS_PEF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK)
+#define EMVSIM_RX_STATUS_FEF_MASK                (0x2000U)
+#define EMVSIM_RX_STATUS_FEF_SHIFT               (13U)
+/*! FEF - Frame Error Flag
+ *  0b0..No frame error detected
+ *  0b1..Frame error detected
+ */
+#define EMVSIM_RX_STATUS_FEF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK)
+#define EMVSIM_RX_STATUS_RX_WPTR_MASK            (0xF0000U)
+#define EMVSIM_RX_STATUS_RX_WPTR_SHIFT           (16U)
+#define EMVSIM_RX_STATUS_RX_WPTR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK)
+#define EMVSIM_RX_STATUS_RX_CNT_MASK             (0xF000000U)
+#define EMVSIM_RX_STATUS_RX_CNT_SHIFT            (24U)
+/*! RX_CNT - Receive FIFO Byte Count
+ *  0b0000..FIFO is emtpy
+ */
+#define EMVSIM_RX_STATUS_RX_CNT(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK)
+/*! @} */
+
+/*! @name TX_STATUS - Transmitter Status Register */
+/*! @{ */
+#define EMVSIM_TX_STATUS_TNTE_MASK               (0x1U)
+#define EMVSIM_TX_STATUS_TNTE_SHIFT              (0U)
+/*! TNTE - Transmit NACK Threshold Error Flag
+ *  0b0..Transmit NACK threshold has not been reached (default)
+ *  0b1..Transmit NACK threshold reached; transmitter frozen
+ */
+#define EMVSIM_TX_STATUS_TNTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK)
+#define EMVSIM_TX_STATUS_TFE_MASK                (0x8U)
+#define EMVSIM_TX_STATUS_TFE_SHIFT               (3U)
+/*! TFE - Transmit FIFO Empty Flag
+ *  0b0..Transmit FIFO is not empty
+ *  0b1..Transmit FIFO is empty (default)
+ */
+#define EMVSIM_TX_STATUS_TFE(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK)
+#define EMVSIM_TX_STATUS_ETCF_MASK               (0x10U)
+#define EMVSIM_TX_STATUS_ETCF_SHIFT              (4U)
+/*! ETCF - Early Transmit Complete Flag
+ *  0b0..Transmit pending or in progress
+ *  0b1..Transmit complete (default)
+ */
+#define EMVSIM_TX_STATUS_ETCF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK)
+#define EMVSIM_TX_STATUS_TCF_MASK                (0x20U)
+#define EMVSIM_TX_STATUS_TCF_SHIFT               (5U)
+/*! TCF - Transmit Complete Flag
+ *  0b0..Transmit pending or in progress
+ *  0b1..Transmit complete (default)
+ */
+#define EMVSIM_TX_STATUS_TCF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK)
+#define EMVSIM_TX_STATUS_TFF_MASK                (0x40U)
+#define EMVSIM_TX_STATUS_TFF_SHIFT               (6U)
+/*! TFF - Transmit FIFO Full Flag
+ *  0b0..Transmit FIFO Full condition has not occurred (default)
+ *  0b1..A Transmit FIFO Full condition has occurred
+ */
+#define EMVSIM_TX_STATUS_TFF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK)
+#define EMVSIM_TX_STATUS_TDTF_MASK               (0x80U)
+#define EMVSIM_TX_STATUS_TDTF_SHIFT              (7U)
+/*! TDTF - Transmit Data Threshold Flag
+ *  0b0..Number of bytes in FIFO is greater than TDT[3:0], or bit has been cleared
+ *  0b1..Number of bytes in FIFO is less than or equal to TDT[3:0] (default)
+ */
+#define EMVSIM_TX_STATUS_TDTF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK)
+#define EMVSIM_TX_STATUS_GPCNT0_TO_MASK          (0x100U)
+#define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT         (8U)
+/*! GPCNT0_TO - General Purpose Counter 0 Timeout Flag
+ *  0b0..GPCNT0_VAL time not reached, or bit has been cleared. (default)
+ *  0b1..General Purpose counter has reached the GPCNT0_VAL value
+ */
+#define EMVSIM_TX_STATUS_GPCNT0_TO(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK)
+#define EMVSIM_TX_STATUS_GPCNT1_TO_MASK          (0x200U)
+#define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT         (9U)
+/*! GPCNT1_TO - General Purpose Counter 1 Timeout Flag
+ *  0b0..GPCNT1_VAL time not reached, or bit has been cleared. (default)
+ *  0b1..General Purpose counter has reached the GPCNT1_VAL value
+ */
+#define EMVSIM_TX_STATUS_GPCNT1_TO(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK)
+#define EMVSIM_TX_STATUS_TX_RPTR_MASK            (0xF0000U)
+#define EMVSIM_TX_STATUS_TX_RPTR_SHIFT           (16U)
+#define EMVSIM_TX_STATUS_TX_RPTR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK)
+#define EMVSIM_TX_STATUS_TX_CNT_MASK             (0xF000000U)
+#define EMVSIM_TX_STATUS_TX_CNT_SHIFT            (24U)
+/*! TX_CNT - Transmit FIFO Byte Count
+ *  0b0000..FIFO is emtpy
+ */
+#define EMVSIM_TX_STATUS_TX_CNT(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK)
+/*! @} */
+
+/*! @name PCSR - Port Control and Status Register */
+/*! @{ */
+#define EMVSIM_PCSR_SAPD_MASK                    (0x1U)
+#define EMVSIM_PCSR_SAPD_SHIFT                   (0U)
+/*! SAPD - Auto Power Down Enable
+ *  0b0..Auto power down disabled (default)
+ *  0b1..Auto power down enabled
+ */
+#define EMVSIM_PCSR_SAPD(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK)
+#define EMVSIM_PCSR_SVCC_EN_MASK                 (0x2U)
+#define EMVSIM_PCSR_SVCC_EN_SHIFT                (1U)
+/*! SVCC_EN - Vcc Enable for Smart Card
+ *  0b0..Smart Card Voltage disabled (default)
+ *  0b1..Smart Card Voltage enabled
+ */
+#define EMVSIM_PCSR_SVCC_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK)
+#define EMVSIM_PCSR_VCCENP_MASK                  (0x4U)
+#define EMVSIM_PCSR_VCCENP_SHIFT                 (2U)
+/*! VCCENP - VCC Enable Polarity Control
+ *  0b0..VCC_EN is active high. Polarity of SVCC_EN is unchanged.
+ *  0b1..VCC_EN is active low. Polarity of SVCC_EN is inverted.
+ */
+#define EMVSIM_PCSR_VCCENP(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK)
+#define EMVSIM_PCSR_SRST_MASK                    (0x8U)
+#define EMVSIM_PCSR_SRST_SHIFT                   (3U)
+/*! SRST - Reset to Smart Card
+ *  0b0..Smart Card Reset is asserted (default)
+ *  0b1..Smart Card Reset is de-asserted
+ */
+#define EMVSIM_PCSR_SRST(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK)
+#define EMVSIM_PCSR_SCEN_MASK                    (0x10U)
+#define EMVSIM_PCSR_SCEN_SHIFT                   (4U)
+/*! SCEN - Clock Enable for Smart Card
+ *  0b0..Smart Card Clock Disabled
+ *  0b1..Smart Card Clock Enabled
+ */
+#define EMVSIM_PCSR_SCEN(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK)
+#define EMVSIM_PCSR_SCSP_MASK                    (0x20U)
+#define EMVSIM_PCSR_SCSP_SHIFT                   (5U)
+/*! SCSP - Smart Card Clock Stop Polarity
+ *  0b0..Clock is logic 0 when stopped by SCEN
+ *  0b1..Clock is logic 1 when stopped by SCEN
+ */
+#define EMVSIM_PCSR_SCSP(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK)
+#define EMVSIM_PCSR_SPD_MASK                     (0x80U)
+#define EMVSIM_PCSR_SPD_SHIFT                    (7U)
+/*! SPD - Auto Power Down Control
+ *  0b0..No effect (default)
+ *  0b1..Start Auto Powerdown or Power Down is in progress
+ */
+#define EMVSIM_PCSR_SPD(x)                       (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK)
+#define EMVSIM_PCSR_SPDIM_MASK                   (0x1000000U)
+#define EMVSIM_PCSR_SPDIM_SHIFT                  (24U)
+/*! SPDIM - Smart Card Presence Detect Interrupt Mask
+ *  0b0..SIM presence detect interrupt is enabled
+ *  0b1..SIM presence detect interrupt is masked (default)
+ */
+#define EMVSIM_PCSR_SPDIM(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK)
+#define EMVSIM_PCSR_SPDIF_MASK                   (0x2000000U)
+#define EMVSIM_PCSR_SPDIF_SHIFT                  (25U)
+/*! SPDIF - Smart Card Presence Detect Interrupt Flag
+ *  0b0..No insertion or removal of Smart Card detected on Port (default)
+ *  0b1..Insertion or removal of Smart Card detected on Port
+ */
+#define EMVSIM_PCSR_SPDIF(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK)
+#define EMVSIM_PCSR_SPDP_MASK                    (0x4000000U)
+#define EMVSIM_PCSR_SPDP_SHIFT                   (26U)
+/*! SPDP - Smart Card Presence Detect Pin Status
+ *  0b0..SIM Presence Detect pin is logic low
+ *  0b1..SIM Presence Detectpin is logic high
+ */
+#define EMVSIM_PCSR_SPDP(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK)
+#define EMVSIM_PCSR_SPDES_MASK                   (0x8000000U)
+#define EMVSIM_PCSR_SPDES_SHIFT                  (27U)
+/*! SPDES - SIM Presence Detect Edge Select
+ *  0b0..Falling edge on the pin (default)
+ *  0b1..Rising edge on the pin
+ */
+#define EMVSIM_PCSR_SPDES(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK)
+/*! @} */
+
+/*! @name RX_BUF - Receive Data Read Buffer */
+/*! @{ */
+#define EMVSIM_RX_BUF_RX_BYTE_MASK               (0xFFU)
+#define EMVSIM_RX_BUF_RX_BYTE_SHIFT              (0U)
+#define EMVSIM_RX_BUF_RX_BYTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK)
+/*! @} */
+
+/*! @name TX_BUF - Transmit Data Buffer */
+/*! @{ */
+#define EMVSIM_TX_BUF_TX_BYTE_MASK               (0xFFU)
+#define EMVSIM_TX_BUF_TX_BYTE_SHIFT              (0U)
+#define EMVSIM_TX_BUF_TX_BYTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK)
+/*! @} */
+
+/*! @name TX_GETU - Transmitter Guard ETU Value Register */
+/*! @{ */
+#define EMVSIM_TX_GETU_GETU_MASK                 (0xFFU)
+#define EMVSIM_TX_GETU_GETU_SHIFT                (0U)
+/*! GETU - Transmitter Guard Time Value in ETU
+ *  0b00000000..no additional ETUs inserted (default)
+ *  0b00000001..1 additional ETU inserted
+ *  0b11111110..254 additional ETUs inserted
+ *  0b11111111..Subtracts one ETU by reducing the number of STOP bits from two to one
+ */
+#define EMVSIM_TX_GETU_GETU(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
+/*! @} */
+
+/*! @name CWT_VAL - Character Wait Time Value Register */
+/*! @{ */
+#define EMVSIM_CWT_VAL_CWT_MASK                  (0xFFFFU)
+#define EMVSIM_CWT_VAL_CWT_SHIFT                 (0U)
+#define EMVSIM_CWT_VAL_CWT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK)
+/*! @} */
+
+/*! @name BWT_VAL - Block Wait Time Value Register */
+/*! @{ */
+#define EMVSIM_BWT_VAL_BWT_MASK                  (0xFFFFFFFFU)
+#define EMVSIM_BWT_VAL_BWT_SHIFT                 (0U)
+#define EMVSIM_BWT_VAL_BWT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK)
+/*! @} */
+
+/*! @name BGT_VAL - Block Guard Time Value Register */
+/*! @{ */
+#define EMVSIM_BGT_VAL_BGT_MASK                  (0xFFFFU)
+#define EMVSIM_BGT_VAL_BGT_SHIFT                 (0U)
+#define EMVSIM_BGT_VAL_BGT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK)
+/*! @} */
+
+/*! @name GPCNT0_VAL - General Purpose Counter 0 Timeout Value Register */
+/*! @{ */
+#define EMVSIM_GPCNT0_VAL_GPCNT0_MASK            (0xFFFFU)
+#define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT           (0U)
+#define EMVSIM_GPCNT0_VAL_GPCNT0(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK)
+/*! @} */
+
+/*! @name GPCNT1_VAL - General Purpose Counter 1 Timeout Value */
+/*! @{ */
+#define EMVSIM_GPCNT1_VAL_GPCNT1_MASK            (0xFFFFU)
+#define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT           (0U)
+#define EMVSIM_GPCNT1_VAL_GPCNT1(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group EMVSIM_Register_Masks */
+
+
+/* EMVSIM - Peripheral instance base addresses */
+/** Peripheral EMVSIM0 base address */
+#define EMVSIM0_BASE                             (0x40038000u)
+/** Peripheral EMVSIM0 base pointer */
+#define EMVSIM0                                  ((EMVSIM_Type *)EMVSIM0_BASE)
+/** Array initializer of EMVSIM peripheral base addresses */
+#define EMVSIM_BASE_ADDRS                        { EMVSIM0_BASE }
+/** Array initializer of EMVSIM peripheral base pointers */
+#define EMVSIM_BASE_PTRS                         { EMVSIM0 }
+/** Interrupt vectors for the EMVSIM peripheral type */
+#define EMVSIM_IRQS                              { EMVSIM0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group EMVSIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EVENT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EVENT_Peripheral_Access_Layer EVENT Peripheral Access Layer
+ * @{
+ */
+
+/** EVENT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t INTPTEN;                           /**< Interrupt Enable Register, offset: 0x0 */
+  __IO uint32_t INTPTPEND;                         /**< Interrupt Pengding Register, offset: 0x4 */
+  __IO uint32_t INTPTPENDSET;                      /**< Set Interrupt Pengding Register, offset: 0x8 */
+  __IO uint32_t INTPTPENDCLEAR;                    /**< Clear Interrupt Pengding Register, offset: 0xC */
+  __IO uint32_t INTPTSECURE;                       /**< Interrupt Secure Register, offset: 0x10 */
+  __IO uint32_t INTPTPRI[4];                       /**< Interrupt Priority 0 Register..Interrupt Priority 3 Register, array offset: 0x14, array step: 0x4 */
+  __IO uint32_t INTPRIBASE;                        /**< Interrupt Priority Base, offset: 0x24 */
+  __I  uint32_t INTPTENACTIVE;                     /**< Interrupt Active Register, offset: 0x28 */
+  __I  uint32_t INTACTPRI[4];                      /**< Interrupt Active Priority 0 Register..Interrupt Active Priority 3 Register, array offset: 0x2C, array step: 0x4 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t EVENTEN;                           /**< Event Enable Register, offset: 0x40 */
+  __IO uint32_t EVENTPEND;                         /**< Event Pengding Register, offset: 0x44 */
+  __IO uint32_t EVTPENDSET;                        /**< Set Event Pengding Register, offset: 0x48 */
+  __IO uint32_t EVTPENDCLEAR;                      /**< Clear Event Pengding Register, offset: 0x4C */
+       uint8_t RESERVED_1[48];
+  __IO uint32_t SLPCTRL;                           /**< Sleep Control Register, offset: 0x80 */
+  __IO uint32_t SLPSTATUS;                         /**< Sleep Status Register, offset: 0x84 */
+} EVENT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- EVENT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EVENT_Register_Masks EVENT Register Masks
+ * @{
+ */
+
+/*! @name INTPTEN - Interrupt Enable Register */
+/*! @{ */
+#define EVENT_INTPTEN_IEN_MASK                   (0xFFFFFFFFU)
+#define EVENT_INTPTEN_IEN_SHIFT                  (0U)
+/*! IEN - Interrupt n Enable
+ *  0b00000000000000000000000000000000..Interrupt n is disabled.
+ *  0b00000000000000000000000000000001..Interrupt n is enabled.
+ */
+#define EVENT_INTPTEN_IEN(x)                     (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTEN_IEN_SHIFT)) & EVENT_INTPTEN_IEN_MASK)
+/*! @} */
+
+/*! @name INTPTPEND - Interrupt Pengding Register */
+/*! @{ */
+#define EVENT_INTPTPEND_IPEND_MASK               (0xFFFFFFFFU)
+#define EVENT_INTPTPEND_IPEND_SHIFT              (0U)
+/*! IPEND - Interrupt n Pending
+ *  0b00000000000000000000000000000000..Interrupt n is not pending.
+ *  0b00000000000000000000000000000001..Interrupt n is pending.
+ */
+#define EVENT_INTPTPEND_IPEND(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPEND_IPEND_SHIFT)) & EVENT_INTPTPEND_IPEND_MASK)
+/*! @} */
+
+/*! @name INTPTPENDSET - Set Interrupt Pengding Register */
+/*! @{ */
+#define EVENT_INTPTPENDSET_IPENDSET_MASK         (0xFFFFFFFFU)
+#define EVENT_INTPTPENDSET_IPENDSET_SHIFT        (0U)
+/*! IPENDSET - Set Interrupt n Pending
+ *  0b00000000000000000000000000000000..Not set interrupt n in pending status
+ *  0b00000000000000000000000000000001..Set interrupt n in pending status.
+ */
+#define EVENT_INTPTPENDSET_IPENDSET(x)           (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPENDSET_IPENDSET_SHIFT)) & EVENT_INTPTPENDSET_IPENDSET_MASK)
+/*! @} */
+
+/*! @name INTPTPENDCLEAR - Clear Interrupt Pengding Register */
+/*! @{ */
+#define EVENT_INTPTPENDCLEAR_IPENDCLEAR_MASK     (0xFFFFFFFFU)
+#define EVENT_INTPTPENDCLEAR_IPENDCLEAR_SHIFT    (0U)
+/*! IPENDCLEAR - Clear Interrupt n out of Pending
+ *  0b00000000000000000000000000000000..Not clear interrupt n out of pending status
+ *  0b00000000000000000000000000000001..Clear interrupt n out of pending status.
+ */
+#define EVENT_INTPTPENDCLEAR_IPENDCLEAR(x)       (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPENDCLEAR_IPENDCLEAR_SHIFT)) & EVENT_INTPTPENDCLEAR_IPENDCLEAR_MASK)
+/*! @} */
+
+/*! @name INTPTSECURE - Interrupt Secure Register */
+/*! @{ */
+#define EVENT_INTPTSECURE_ISECURE_MASK           (0xFFFFFFFFU)
+#define EVENT_INTPTSECURE_ISECURE_SHIFT          (0U)
+/*! ISECURE - Set secure feature of Interrupt n
+ *  0b00000000000000000000000000000000..Set interrupt n out of security
+ *  0b00000000000000000000000000000001..Set interrupt n in secruity.
+ */
+#define EVENT_INTPTSECURE_ISECURE(x)             (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTSECURE_ISECURE_SHIFT)) & EVENT_INTPTSECURE_ISECURE_MASK)
+/*! @} */
+
+/*! @name INTPTPRI - Interrupt Priority 0 Register..Interrupt Priority 3 Register */
+/*! @{ */
+#define EVENT_INTPTPRI_IPRI0_MASK                (0x7U)
+#define EVENT_INTPTPRI_IPRI0_SHIFT               (0U)
+#define EVENT_INTPTPRI_IPRI0(x)                  (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI0_SHIFT)) & EVENT_INTPTPRI_IPRI0_MASK)
+#define EVENT_INTPTPRI_IPRI8_MASK                (0x7U)
+#define EVENT_INTPTPRI_IPRI8_SHIFT               (0U)
+#define EVENT_INTPTPRI_IPRI8(x)                  (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI8_SHIFT)) & EVENT_INTPTPRI_IPRI8_MASK)
+#define EVENT_INTPTPRI_IPRI16_MASK               (0x7U)
+#define EVENT_INTPTPRI_IPRI16_SHIFT              (0U)
+#define EVENT_INTPTPRI_IPRI16(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI16_SHIFT)) & EVENT_INTPTPRI_IPRI16_MASK)
+#define EVENT_INTPTPRI_IPRI24_MASK               (0x7U)
+#define EVENT_INTPTPRI_IPRI24_SHIFT              (0U)
+#define EVENT_INTPTPRI_IPRI24(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI24_SHIFT)) & EVENT_INTPTPRI_IPRI24_MASK)
+#define EVENT_INTPTPRI_IPRI1_MASK                (0x70U)
+#define EVENT_INTPTPRI_IPRI1_SHIFT               (4U)
+#define EVENT_INTPTPRI_IPRI1(x)                  (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI1_SHIFT)) & EVENT_INTPTPRI_IPRI1_MASK)
+#define EVENT_INTPTPRI_IPRI9_MASK                (0x70U)
+#define EVENT_INTPTPRI_IPRI9_SHIFT               (4U)
+#define EVENT_INTPTPRI_IPRI9(x)                  (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI9_SHIFT)) & EVENT_INTPTPRI_IPRI9_MASK)
+#define EVENT_INTPTPRI_IPRI17_MASK               (0x70U)
+#define EVENT_INTPTPRI_IPRI17_SHIFT              (4U)
+#define EVENT_INTPTPRI_IPRI17(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI17_SHIFT)) & EVENT_INTPTPRI_IPRI17_MASK)
+#define EVENT_INTPTPRI_IPRI25_MASK               (0x70U)
+#define EVENT_INTPTPRI_IPRI25_SHIFT              (4U)
+#define EVENT_INTPTPRI_IPRI25(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI25_SHIFT)) & EVENT_INTPTPRI_IPRI25_MASK)
+#define EVENT_INTPTPRI_IPRI2_MASK                (0x700U)
+#define EVENT_INTPTPRI_IPRI2_SHIFT               (8U)
+#define EVENT_INTPTPRI_IPRI2(x)                  (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI2_SHIFT)) & EVENT_INTPTPRI_IPRI2_MASK)
+#define EVENT_INTPTPRI_IPRI10_MASK               (0x700U)
+#define EVENT_INTPTPRI_IPRI10_SHIFT              (8U)
+#define EVENT_INTPTPRI_IPRI10(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI10_SHIFT)) & EVENT_INTPTPRI_IPRI10_MASK)
+#define EVENT_INTPTPRI_IPRI18_MASK               (0x700U)
+#define EVENT_INTPTPRI_IPRI18_SHIFT              (8U)
+#define EVENT_INTPTPRI_IPRI18(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI18_SHIFT)) & EVENT_INTPTPRI_IPRI18_MASK)
+#define EVENT_INTPTPRI_IPRI26_MASK               (0x700U)
+#define EVENT_INTPTPRI_IPRI26_SHIFT              (8U)
+#define EVENT_INTPTPRI_IPRI26(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI26_SHIFT)) & EVENT_INTPTPRI_IPRI26_MASK)
+#define EVENT_INTPTPRI_IPRI3_MASK                (0x7000U)
+#define EVENT_INTPTPRI_IPRI3_SHIFT               (12U)
+#define EVENT_INTPTPRI_IPRI3(x)                  (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI3_SHIFT)) & EVENT_INTPTPRI_IPRI3_MASK)
+#define EVENT_INTPTPRI_IPRI11_MASK               (0x7000U)
+#define EVENT_INTPTPRI_IPRI11_SHIFT              (12U)
+#define EVENT_INTPTPRI_IPRI11(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI11_SHIFT)) & EVENT_INTPTPRI_IPRI11_MASK)
+#define EVENT_INTPTPRI_IPRI19_MASK               (0x7000U)
+#define EVENT_INTPTPRI_IPRI19_SHIFT              (12U)
+#define EVENT_INTPTPRI_IPRI19(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI19_SHIFT)) & EVENT_INTPTPRI_IPRI19_MASK)
+#define EVENT_INTPTPRI_IPRI27_MASK               (0x7000U)
+#define EVENT_INTPTPRI_IPRI27_SHIFT              (12U)
+#define EVENT_INTPTPRI_IPRI27(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI27_SHIFT)) & EVENT_INTPTPRI_IPRI27_MASK)
+#define EVENT_INTPTPRI_IPRI4_MASK                (0x70000U)
+#define EVENT_INTPTPRI_IPRI4_SHIFT               (16U)
+#define EVENT_INTPTPRI_IPRI4(x)                  (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI4_SHIFT)) & EVENT_INTPTPRI_IPRI4_MASK)
+#define EVENT_INTPTPRI_IPRI12_MASK               (0x70000U)
+#define EVENT_INTPTPRI_IPRI12_SHIFT              (16U)
+#define EVENT_INTPTPRI_IPRI12(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI12_SHIFT)) & EVENT_INTPTPRI_IPRI12_MASK)
+#define EVENT_INTPTPRI_IPRI20_MASK               (0x70000U)
+#define EVENT_INTPTPRI_IPRI20_SHIFT              (16U)
+#define EVENT_INTPTPRI_IPRI20(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI20_SHIFT)) & EVENT_INTPTPRI_IPRI20_MASK)
+#define EVENT_INTPTPRI_IPRI28_MASK               (0x70000U)
+#define EVENT_INTPTPRI_IPRI28_SHIFT              (16U)
+#define EVENT_INTPTPRI_IPRI28(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI28_SHIFT)) & EVENT_INTPTPRI_IPRI28_MASK)
+#define EVENT_INTPTPRI_IPRI5_MASK                (0x700000U)
+#define EVENT_INTPTPRI_IPRI5_SHIFT               (20U)
+#define EVENT_INTPTPRI_IPRI5(x)                  (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI5_SHIFT)) & EVENT_INTPTPRI_IPRI5_MASK)
+#define EVENT_INTPTPRI_IPRI13_MASK               (0x700000U)
+#define EVENT_INTPTPRI_IPRI13_SHIFT              (20U)
+#define EVENT_INTPTPRI_IPRI13(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI13_SHIFT)) & EVENT_INTPTPRI_IPRI13_MASK)
+#define EVENT_INTPTPRI_IPRI21_MASK               (0x700000U)
+#define EVENT_INTPTPRI_IPRI21_SHIFT              (20U)
+#define EVENT_INTPTPRI_IPRI21(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI21_SHIFT)) & EVENT_INTPTPRI_IPRI21_MASK)
+#define EVENT_INTPTPRI_IPRI29_MASK               (0x700000U)
+#define EVENT_INTPTPRI_IPRI29_SHIFT              (20U)
+#define EVENT_INTPTPRI_IPRI29(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI29_SHIFT)) & EVENT_INTPTPRI_IPRI29_MASK)
+#define EVENT_INTPTPRI_IPRI6_MASK                (0x7000000U)
+#define EVENT_INTPTPRI_IPRI6_SHIFT               (24U)
+#define EVENT_INTPTPRI_IPRI6(x)                  (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI6_SHIFT)) & EVENT_INTPTPRI_IPRI6_MASK)
+#define EVENT_INTPTPRI_IPRI14_MASK               (0x7000000U)
+#define EVENT_INTPTPRI_IPRI14_SHIFT              (24U)
+#define EVENT_INTPTPRI_IPRI14(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI14_SHIFT)) & EVENT_INTPTPRI_IPRI14_MASK)
+#define EVENT_INTPTPRI_IPRI22_MASK               (0x7000000U)
+#define EVENT_INTPTPRI_IPRI22_SHIFT              (24U)
+#define EVENT_INTPTPRI_IPRI22(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI22_SHIFT)) & EVENT_INTPTPRI_IPRI22_MASK)
+#define EVENT_INTPTPRI_IPRI30_MASK               (0x7000000U)
+#define EVENT_INTPTPRI_IPRI30_SHIFT              (24U)
+#define EVENT_INTPTPRI_IPRI30(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI30_SHIFT)) & EVENT_INTPTPRI_IPRI30_MASK)
+#define EVENT_INTPTPRI_IPRI7_MASK                (0x70000000U)
+#define EVENT_INTPTPRI_IPRI7_SHIFT               (28U)
+#define EVENT_INTPTPRI_IPRI7(x)                  (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI7_SHIFT)) & EVENT_INTPTPRI_IPRI7_MASK)
+#define EVENT_INTPTPRI_IPRI15_MASK               (0x70000000U)
+#define EVENT_INTPTPRI_IPRI15_SHIFT              (28U)
+#define EVENT_INTPTPRI_IPRI15(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI15_SHIFT)) & EVENT_INTPTPRI_IPRI15_MASK)
+#define EVENT_INTPTPRI_IPRI23_MASK               (0x70000000U)
+#define EVENT_INTPTPRI_IPRI23_SHIFT              (28U)
+#define EVENT_INTPTPRI_IPRI23(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI23_SHIFT)) & EVENT_INTPTPRI_IPRI23_MASK)
+#define EVENT_INTPTPRI_IPRI31_MASK               (0x70000000U)
+#define EVENT_INTPTPRI_IPRI31_SHIFT              (28U)
+#define EVENT_INTPTPRI_IPRI31(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTPRI_IPRI31_SHIFT)) & EVENT_INTPTPRI_IPRI31_MASK)
+/*! @} */
+
+/* The count of EVENT_INTPTPRI */
+#define EVENT_INTPTPRI_COUNT                     (4U)
+
+/*! @name INTPRIBASE - Interrupt Priority Base */
+/*! @{ */
+#define EVENT_INTPRIBASE_IPBASE_MASK             (0xFU)
+#define EVENT_INTPRIBASE_IPBASE_SHIFT            (0U)
+#define EVENT_INTPRIBASE_IPBASE(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTPRIBASE_IPBASE_SHIFT)) & EVENT_INTPRIBASE_IPBASE_MASK)
+/*! @} */
+
+/*! @name INTPTENACTIVE - Interrupt Active Register */
+/*! @{ */
+#define EVENT_INTPTENACTIVE_IACTIVE_MASK         (0xFFFFFFFFU)
+#define EVENT_INTPTENACTIVE_IACTIVE_SHIFT        (0U)
+/*! IACTIVE - Interrupt n Enable
+ *  0b00000000000000000000000000000000..Interrupt n is not active.
+ *  0b00000000000000000000000000000001..Interrupt n is active..
+ */
+#define EVENT_INTPTENACTIVE_IACTIVE(x)           (((uint32_t)(((uint32_t)(x)) << EVENT_INTPTENACTIVE_IACTIVE_SHIFT)) & EVENT_INTPTENACTIVE_IACTIVE_MASK)
+/*! @} */
+
+/*! @name INTACTPRI - Interrupt Active Priority 0 Register..Interrupt Active Priority 3 Register */
+/*! @{ */
+#define EVENT_INTACTPRI_IAPRI0_MASK              (0x7U)
+#define EVENT_INTACTPRI_IAPRI0_SHIFT             (0U)
+#define EVENT_INTACTPRI_IAPRI0(x)                (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI0_SHIFT)) & EVENT_INTACTPRI_IAPRI0_MASK)
+#define EVENT_INTACTPRI_IAPRI8_MASK              (0x7U)
+#define EVENT_INTACTPRI_IAPRI8_SHIFT             (0U)
+#define EVENT_INTACTPRI_IAPRI8(x)                (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI8_SHIFT)) & EVENT_INTACTPRI_IAPRI8_MASK)
+#define EVENT_INTACTPRI_IAPRI16_MASK             (0x7U)
+#define EVENT_INTACTPRI_IAPRI16_SHIFT            (0U)
+#define EVENT_INTACTPRI_IAPRI16(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI16_SHIFT)) & EVENT_INTACTPRI_IAPRI16_MASK)
+#define EVENT_INTACTPRI_IAPRI24_MASK             (0x7U)
+#define EVENT_INTACTPRI_IAPRI24_SHIFT            (0U)
+#define EVENT_INTACTPRI_IAPRI24(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI24_SHIFT)) & EVENT_INTACTPRI_IAPRI24_MASK)
+#define EVENT_INTACTPRI_IAPRI1_MASK              (0x70U)
+#define EVENT_INTACTPRI_IAPRI1_SHIFT             (4U)
+#define EVENT_INTACTPRI_IAPRI1(x)                (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI1_SHIFT)) & EVENT_INTACTPRI_IAPRI1_MASK)
+#define EVENT_INTACTPRI_IAPRI9_MASK              (0x70U)
+#define EVENT_INTACTPRI_IAPRI9_SHIFT             (4U)
+#define EVENT_INTACTPRI_IAPRI9(x)                (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI9_SHIFT)) & EVENT_INTACTPRI_IAPRI9_MASK)
+#define EVENT_INTACTPRI_IAPRI17_MASK             (0x70U)
+#define EVENT_INTACTPRI_IAPRI17_SHIFT            (4U)
+#define EVENT_INTACTPRI_IAPRI17(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI17_SHIFT)) & EVENT_INTACTPRI_IAPRI17_MASK)
+#define EVENT_INTACTPRI_IAPRI25_MASK             (0x70U)
+#define EVENT_INTACTPRI_IAPRI25_SHIFT            (4U)
+#define EVENT_INTACTPRI_IAPRI25(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI25_SHIFT)) & EVENT_INTACTPRI_IAPRI25_MASK)
+#define EVENT_INTACTPRI_IAPRI2_MASK              (0x700U)
+#define EVENT_INTACTPRI_IAPRI2_SHIFT             (8U)
+#define EVENT_INTACTPRI_IAPRI2(x)                (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI2_SHIFT)) & EVENT_INTACTPRI_IAPRI2_MASK)
+#define EVENT_INTACTPRI_IAPRI10_MASK             (0x700U)
+#define EVENT_INTACTPRI_IAPRI10_SHIFT            (8U)
+#define EVENT_INTACTPRI_IAPRI10(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI10_SHIFT)) & EVENT_INTACTPRI_IAPRI10_MASK)
+#define EVENT_INTACTPRI_IAPRI18_MASK             (0x700U)
+#define EVENT_INTACTPRI_IAPRI18_SHIFT            (8U)
+#define EVENT_INTACTPRI_IAPRI18(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI18_SHIFT)) & EVENT_INTACTPRI_IAPRI18_MASK)
+#define EVENT_INTACTPRI_IAPRI26_MASK             (0x700U)
+#define EVENT_INTACTPRI_IAPRI26_SHIFT            (8U)
+#define EVENT_INTACTPRI_IAPRI26(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI26_SHIFT)) & EVENT_INTACTPRI_IAPRI26_MASK)
+#define EVENT_INTACTPRI_IAPRI3_MASK              (0x7000U)
+#define EVENT_INTACTPRI_IAPRI3_SHIFT             (12U)
+#define EVENT_INTACTPRI_IAPRI3(x)                (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI3_SHIFT)) & EVENT_INTACTPRI_IAPRI3_MASK)
+#define EVENT_INTACTPRI_IAPRI11_MASK             (0x7000U)
+#define EVENT_INTACTPRI_IAPRI11_SHIFT            (12U)
+#define EVENT_INTACTPRI_IAPRI11(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI11_SHIFT)) & EVENT_INTACTPRI_IAPRI11_MASK)
+#define EVENT_INTACTPRI_IAPRI19_MASK             (0x7000U)
+#define EVENT_INTACTPRI_IAPRI19_SHIFT            (12U)
+#define EVENT_INTACTPRI_IAPRI19(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI19_SHIFT)) & EVENT_INTACTPRI_IAPRI19_MASK)
+#define EVENT_INTACTPRI_IAPRI27_MASK             (0x7000U)
+#define EVENT_INTACTPRI_IAPRI27_SHIFT            (12U)
+#define EVENT_INTACTPRI_IAPRI27(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI27_SHIFT)) & EVENT_INTACTPRI_IAPRI27_MASK)
+#define EVENT_INTACTPRI_IAPRI4_MASK              (0x70000U)
+#define EVENT_INTACTPRI_IAPRI4_SHIFT             (16U)
+#define EVENT_INTACTPRI_IAPRI4(x)                (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI4_SHIFT)) & EVENT_INTACTPRI_IAPRI4_MASK)
+#define EVENT_INTACTPRI_IAPRI12_MASK             (0x70000U)
+#define EVENT_INTACTPRI_IAPRI12_SHIFT            (16U)
+#define EVENT_INTACTPRI_IAPRI12(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI12_SHIFT)) & EVENT_INTACTPRI_IAPRI12_MASK)
+#define EVENT_INTACTPRI_IAPRI20_MASK             (0x70000U)
+#define EVENT_INTACTPRI_IAPRI20_SHIFT            (16U)
+#define EVENT_INTACTPRI_IAPRI20(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI20_SHIFT)) & EVENT_INTACTPRI_IAPRI20_MASK)
+#define EVENT_INTACTPRI_IAPRI28_MASK             (0x70000U)
+#define EVENT_INTACTPRI_IAPRI28_SHIFT            (16U)
+#define EVENT_INTACTPRI_IAPRI28(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI28_SHIFT)) & EVENT_INTACTPRI_IAPRI28_MASK)
+#define EVENT_INTACTPRI_IAPRI5_MASK              (0x700000U)
+#define EVENT_INTACTPRI_IAPRI5_SHIFT             (20U)
+#define EVENT_INTACTPRI_IAPRI5(x)                (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI5_SHIFT)) & EVENT_INTACTPRI_IAPRI5_MASK)
+#define EVENT_INTACTPRI_IAPRI13_MASK             (0x700000U)
+#define EVENT_INTACTPRI_IAPRI13_SHIFT            (20U)
+#define EVENT_INTACTPRI_IAPRI13(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI13_SHIFT)) & EVENT_INTACTPRI_IAPRI13_MASK)
+#define EVENT_INTACTPRI_IAPRI21_MASK             (0x700000U)
+#define EVENT_INTACTPRI_IAPRI21_SHIFT            (20U)
+#define EVENT_INTACTPRI_IAPRI21(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI21_SHIFT)) & EVENT_INTACTPRI_IAPRI21_MASK)
+#define EVENT_INTACTPRI_IAPRI29_MASK             (0x700000U)
+#define EVENT_INTACTPRI_IAPRI29_SHIFT            (20U)
+#define EVENT_INTACTPRI_IAPRI29(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI29_SHIFT)) & EVENT_INTACTPRI_IAPRI29_MASK)
+#define EVENT_INTACTPRI_IAPRI6_MASK              (0x7000000U)
+#define EVENT_INTACTPRI_IAPRI6_SHIFT             (24U)
+#define EVENT_INTACTPRI_IAPRI6(x)                (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI6_SHIFT)) & EVENT_INTACTPRI_IAPRI6_MASK)
+#define EVENT_INTACTPRI_IAPRI14_MASK             (0x7000000U)
+#define EVENT_INTACTPRI_IAPRI14_SHIFT            (24U)
+#define EVENT_INTACTPRI_IAPRI14(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI14_SHIFT)) & EVENT_INTACTPRI_IAPRI14_MASK)
+#define EVENT_INTACTPRI_IAPRI22_MASK             (0x7000000U)
+#define EVENT_INTACTPRI_IAPRI22_SHIFT            (24U)
+#define EVENT_INTACTPRI_IAPRI22(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI22_SHIFT)) & EVENT_INTACTPRI_IAPRI22_MASK)
+#define EVENT_INTACTPRI_IAPRI30_MASK             (0x7000000U)
+#define EVENT_INTACTPRI_IAPRI30_SHIFT            (24U)
+#define EVENT_INTACTPRI_IAPRI30(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI30_SHIFT)) & EVENT_INTACTPRI_IAPRI30_MASK)
+#define EVENT_INTACTPRI_IAPRI7_MASK              (0x70000000U)
+#define EVENT_INTACTPRI_IAPRI7_SHIFT             (28U)
+#define EVENT_INTACTPRI_IAPRI7(x)                (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI7_SHIFT)) & EVENT_INTACTPRI_IAPRI7_MASK)
+#define EVENT_INTACTPRI_IAPRI15_MASK             (0x70000000U)
+#define EVENT_INTACTPRI_IAPRI15_SHIFT            (28U)
+#define EVENT_INTACTPRI_IAPRI15(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI15_SHIFT)) & EVENT_INTACTPRI_IAPRI15_MASK)
+#define EVENT_INTACTPRI_IAPRI23_MASK             (0x70000000U)
+#define EVENT_INTACTPRI_IAPRI23_SHIFT            (28U)
+#define EVENT_INTACTPRI_IAPRI23(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI23_SHIFT)) & EVENT_INTACTPRI_IAPRI23_MASK)
+#define EVENT_INTACTPRI_IAPRI31_MASK             (0x70000000U)
+#define EVENT_INTACTPRI_IAPRI31_SHIFT            (28U)
+#define EVENT_INTACTPRI_IAPRI31(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_INTACTPRI_IAPRI31_SHIFT)) & EVENT_INTACTPRI_IAPRI31_MASK)
+/*! @} */
+
+/* The count of EVENT_INTACTPRI */
+#define EVENT_INTACTPRI_COUNT                    (4U)
+
+/*! @name EVENTEN - Event Enable Register */
+/*! @{ */
+#define EVENT_EVENTEN_EEN_MASK                   (0xFFFFFFFFU)
+#define EVENT_EVENTEN_EEN_SHIFT                  (0U)
+/*! EEN - Event n Enable
+ *  0b00000000000000000000000000000000..Event n is disabled.
+ *  0b00000000000000000000000000000001..Event n is enabled.
+ */
+#define EVENT_EVENTEN_EEN(x)                     (((uint32_t)(((uint32_t)(x)) << EVENT_EVENTEN_EEN_SHIFT)) & EVENT_EVENTEN_EEN_MASK)
+/*! @} */
+
+/*! @name EVENTPEND - Event Pengding Register */
+/*! @{ */
+#define EVENT_EVENTPEND_EPEND_MASK               (0xFFFFFFFFU)
+#define EVENT_EVENTPEND_EPEND_SHIFT              (0U)
+/*! EPEND - Event n Pending
+ *  0b00000000000000000000000000000000..Event n is not pending.
+ *  0b00000000000000000000000000000001..Event n is pending.
+ */
+#define EVENT_EVENTPEND_EPEND(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_EVENTPEND_EPEND_SHIFT)) & EVENT_EVENTPEND_EPEND_MASK)
+/*! @} */
+
+/*! @name EVTPENDSET - Set Event Pengding Register */
+/*! @{ */
+#define EVENT_EVTPENDSET_EPENDSET_MASK           (0xFFFFFFFFU)
+#define EVENT_EVTPENDSET_EPENDSET_SHIFT          (0U)
+/*! EPENDSET - Set Event n Pending
+ *  0b00000000000000000000000000000000..Not set event n in pending status
+ *  0b00000000000000000000000000000001..Set event n in pending status.
+ */
+#define EVENT_EVTPENDSET_EPENDSET(x)             (((uint32_t)(((uint32_t)(x)) << EVENT_EVTPENDSET_EPENDSET_SHIFT)) & EVENT_EVTPENDSET_EPENDSET_MASK)
+/*! @} */
+
+/*! @name EVTPENDCLEAR - Clear Event Pengding Register */
+/*! @{ */
+#define EVENT_EVTPENDCLEAR_EPENDCLEAR_MASK       (0xFFFFFFFFU)
+#define EVENT_EVTPENDCLEAR_EPENDCLEAR_SHIFT      (0U)
+/*! EPENDCLEAR - Clear Event n out of Pending
+ *  0b00000000000000000000000000000000..Not clear event n out of pending status
+ *  0b00000000000000000000000000000001..Clear event n out of pending status.
+ */
+#define EVENT_EVTPENDCLEAR_EPENDCLEAR(x)         (((uint32_t)(((uint32_t)(x)) << EVENT_EVTPENDCLEAR_EPENDCLEAR_SHIFT)) & EVENT_EVTPENDCLEAR_EPENDCLEAR_MASK)
+/*! @} */
+
+/*! @name SLPCTRL - Sleep Control Register */
+/*! @{ */
+#define EVENT_SLPCTRL_SLPCTRL_MASK               (0x3U)
+#define EVENT_SLPCTRL_SLPCTRL_SHIFT              (0U)
+/*! SLPCTRL - Sleep Mode Control
+ *  0b01..Sleep enable
+ *  0b10..Deep sleep enable
+ */
+#define EVENT_SLPCTRL_SLPCTRL(x)                 (((uint32_t)(((uint32_t)(x)) << EVENT_SLPCTRL_SLPCTRL_SHIFT)) & EVENT_SLPCTRL_SLPCTRL_MASK)
+#define EVENT_SLPCTRL_SYSRSTREQST_MASK           (0x80000000U)
+#define EVENT_SLPCTRL_SYSRSTREQST_SHIFT          (31U)
+/*! SYSRSTREQST - System Reset Request
+ *  0b0..Do not send system reset request.
+ *  0b1..Send system reset request
+ */
+#define EVENT_SLPCTRL_SYSRSTREQST(x)             (((uint32_t)(((uint32_t)(x)) << EVENT_SLPCTRL_SYSRSTREQST_SHIFT)) & EVENT_SLPCTRL_SYSRSTREQST_MASK)
+/*! @} */
+
+/*! @name SLPSTATUS - Sleep Status Register */
+/*! @{ */
+#define EVENT_SLPSTATUS_SLPSTAT_MASK             (0x3U)
+#define EVENT_SLPSTATUS_SLPSTAT_SHIFT            (0U)
+/*! SLPSTAT - Sleep Status
+ *  0b01..In sleep mode
+ *  0b10..In deep sleep mode
+ */
+#define EVENT_SLPSTATUS_SLPSTAT(x)               (((uint32_t)(((uint32_t)(x)) << EVENT_SLPSTATUS_SLPSTAT_SHIFT)) & EVENT_SLPSTATUS_SLPSTAT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group EVENT_Register_Masks */
+
+
+/* EVENT - Peripheral instance base addresses */
+/** Peripheral EVENT1 base address */
+#define EVENT1_BASE                              (0x4101F000u)
+/** Peripheral EVENT1 base pointer */
+#define EVENT1                                   ((EVENT_Type *)EVENT1_BASE)
+/** Array initializer of EVENT peripheral base addresses */
+#define EVENT_BASE_ADDRS                         { EVENT1_BASE }
+/** Array initializer of EVENT peripheral base pointers */
+#define EVENT_BASE_PTRS                          { EVENT1 }
+
+/*!
+ * @}
+ */ /* end of group EVENT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EWM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
+ * @{
+ */
+
+/** EWM - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CTRL;                               /**< Control Register, offset: 0x0 */
+  __O  uint8_t SERV;                               /**< Service Register, offset: 0x1 */
+  __IO uint8_t CMPL;                               /**< Compare Low Register, offset: 0x2 */
+  __IO uint8_t CMPH;                               /**< Compare High Register, offset: 0x3 */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t CLKPRESCALER;                       /**< Clock Prescaler Register, offset: 0x5 */
+} EWM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- EWM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control Register */
+/*! @{ */
+#define EWM_CTRL_EWMEN_MASK                      (0x1U)
+#define EWM_CTRL_EWMEN_SHIFT                     (0U)
+#define EWM_CTRL_EWMEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
+#define EWM_CTRL_ASSIN_MASK                      (0x2U)
+#define EWM_CTRL_ASSIN_SHIFT                     (1U)
+#define EWM_CTRL_ASSIN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
+#define EWM_CTRL_INEN_MASK                       (0x4U)
+#define EWM_CTRL_INEN_SHIFT                      (2U)
+#define EWM_CTRL_INEN(x)                         (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
+#define EWM_CTRL_INTEN_MASK                      (0x8U)
+#define EWM_CTRL_INTEN_SHIFT                     (3U)
+#define EWM_CTRL_INTEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
+/*! @} */
+
+/*! @name SERV - Service Register */
+/*! @{ */
+#define EWM_SERV_SERVICE_MASK                    (0xFFU)
+#define EWM_SERV_SERVICE_SHIFT                   (0U)
+#define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
+/*! @} */
+
+/*! @name CMPL - Compare Low Register */
+/*! @{ */
+#define EWM_CMPL_COMPAREL_MASK                   (0xFFU)
+#define EWM_CMPL_COMPAREL_SHIFT                  (0U)
+#define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
+/*! @} */
+
+/*! @name CMPH - Compare High Register */
+/*! @{ */
+#define EWM_CMPH_COMPAREH_MASK                   (0xFFU)
+#define EWM_CMPH_COMPAREH_SHIFT                  (0U)
+#define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
+/*! @} */
+
+/*! @name CLKPRESCALER - Clock Prescaler Register */
+/*! @{ */
+#define EWM_CLKPRESCALER_CLK_DIV_MASK            (0xFFU)
+#define EWM_CLKPRESCALER_CLK_DIV_SHIFT           (0U)
+#define EWM_CLKPRESCALER_CLK_DIV(x)              (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Masks */
+
+
+/* EWM - Peripheral instance base addresses */
+/** Peripheral EWM base address */
+#define EWM_BASE                                 (0x40022000u)
+/** Peripheral EWM base pointer */
+#define EWM                                      ((EWM_Type *)EWM_BASE)
+/** Array initializer of EWM peripheral base addresses */
+#define EWM_BASE_ADDRS                           { EWM_BASE }
+/** Array initializer of EWM peripheral base pointers */
+#define EWM_BASE_PTRS                            { EWM }
+/** Interrupt vectors for the EWM peripheral type */
+#define EWM_IRQS                                 { EWM_IRQn }
+
+/*!
+ * @}
+ */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
+ * @{
+ */
+
+/** FB - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0xC */
+    __IO uint32_t CSAR;                              /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
+    __IO uint32_t CSMR;                              /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
+    __IO uint32_t CSCR;                              /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
+  } CS[6];
+       uint8_t RESERVED_0[24];
+  __IO uint32_t CSPMCR;                            /**< Chip Select Port Multiplexing Control Register, offset: 0x60 */
+} FB_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Masks FB Register Masks
+ * @{
+ */
+
+/*! @name CSAR - Chip Select Address Register */
+/*! @{ */
+#define FB_CSAR_BA_MASK                          (0xFFFF0000U)
+#define FB_CSAR_BA_SHIFT                         (16U)
+#define FB_CSAR_BA(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
+/*! @} */
+
+/* The count of FB_CSAR */
+#define FB_CSAR_COUNT                            (6U)
+
+/*! @name CSMR - Chip Select Mask Register */
+/*! @{ */
+#define FB_CSMR_V_MASK                           (0x1U)
+#define FB_CSMR_V_SHIFT                          (0U)
+/*! V - Valid
+ *  0b0..Chip-select is invalid.
+ *  0b1..Chip-select is valid.
+ */
+#define FB_CSMR_V(x)                             (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
+#define FB_CSMR_WP_MASK                          (0x100U)
+#define FB_CSMR_WP_SHIFT                         (8U)
+/*! WP - Write Protect
+ *  0b0..Write accesses are allowed.
+ *  0b1..Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle.
+ */
+#define FB_CSMR_WP(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
+#define FB_CSMR_BAM_MASK                         (0xFFFF0000U)
+#define FB_CSMR_BAM_SHIFT                        (16U)
+/*! BAM - Base Address Mask
+ *  0b0000000000000000..The corresponding address bit in CSAR is used in the chip-select decode.
+ *  0b0000000000000001..The corresponding address bit in CSAR is a don't care in the chip-select decode.
+ */
+#define FB_CSMR_BAM(x)                           (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
+/*! @} */
+
+/* The count of FB_CSMR */
+#define FB_CSMR_COUNT                            (6U)
+
+/*! @name CSCR - Chip Select Control Register */
+/*! @{ */
+#define FB_CSCR_BSTW_MASK                        (0x8U)
+#define FB_CSCR_BSTW_SHIFT                       (3U)
+/*! BSTW - Burst-Write Enable
+ *  0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes.
+ *  0b1..Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
+ */
+#define FB_CSCR_BSTW(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
+#define FB_CSCR_BSTR_MASK                        (0x10U)
+#define FB_CSCR_BSTR_SHIFT                       (4U)
+/*! BSTR - Burst-Read Enable
+ *  0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads.
+ *  0b1..Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
+ */
+#define FB_CSCR_BSTR(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
+#define FB_CSCR_BEM_MASK                         (0x20U)
+#define FB_CSCR_BEM_SHIFT                        (5U)
+/*! BEM - Byte-Enable Mode
+ *  0b0..FB_BE_B is asserted for data write only.
+ *  0b1..FB_BE_B is asserted for data read and write accesses.
+ */
+#define FB_CSCR_BEM(x)                           (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
+#define FB_CSCR_PS_MASK                          (0xC0U)
+#define FB_CSCR_PS_SHIFT                         (6U)
+/*! PS - Port Size
+ *  0b00..32-bit port size. Valid data is sampled and driven on FB_D[31:0].
+ *  0b01..8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b.
+ *  0b1x..16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b.
+ */
+#define FB_CSCR_PS(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
+#define FB_CSCR_AA_MASK                          (0x100U)
+#define FB_CSCR_AA_SHIFT                         (8U)
+/*! AA - Auto-Acknowledge Enable
+ *  0b0..Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally.
+ *  0b1..Enabled. Internal transfer acknowledge is asserted as specified by WS.
+ */
+#define FB_CSCR_AA(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
+#define FB_CSCR_BLS_MASK                         (0x200U)
+#define FB_CSCR_BLS_SHIFT                        (9U)
+/*! BLS - Byte-Lane Shift
+ *  0b0..Not shifted. Data is left-aligned on FB_AD.
+ *  0b1..Shifted. Data is right-aligned on FB_AD.
+ */
+#define FB_CSCR_BLS(x)                           (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
+#define FB_CSCR_WS_MASK                          (0xFC00U)
+#define FB_CSCR_WS_SHIFT                         (10U)
+#define FB_CSCR_WS(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
+#define FB_CSCR_WRAH_MASK                        (0x30000U)
+#define FB_CSCR_WRAH_SHIFT                       (16U)
+/*! WRAH - Write Address Hold or Deselect
+ *  0b00..1 cycle (default for all but FB_CS0_B)
+ *  0b01..2 cycles
+ *  0b10..3 cycles
+ *  0b11..4 cycles (default for FB_CS0_B)
+ */
+#define FB_CSCR_WRAH(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
+#define FB_CSCR_RDAH_MASK                        (0xC0000U)
+#define FB_CSCR_RDAH_SHIFT                       (18U)
+/*! RDAH - Read Address Hold or Deselect
+ *  0b00..When AA is 1b, 1 cycle. When AA is 0b, 0 cycles.
+ *  0b01..When AA is 1b, 2 cycles. When AA is 0b, 1 cycle.
+ *  0b10..When AA is 1b, 3 cycles. When AA is 0b, 2 cycles.
+ *  0b11..When AA is 1b, 4 cycles. When AA is 0b, 3 cycles.
+ */
+#define FB_CSCR_RDAH(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
+#define FB_CSCR_ASET_MASK                        (0x300000U)
+#define FB_CSCR_ASET_SHIFT                       (20U)
+/*! ASET - Address Setup
+ *  0b00..Assert FB_CSn_B on the first rising clock edge after the address is asserted (default for all but FB_CS0_B).
+ *  0b01..Assert FB_CSn_B on the second rising clock edge after the address is asserted.
+ *  0b10..Assert FB_CSn_B on the third rising clock edge after the address is asserted.
+ *  0b11..Assert FB_CSn_B on the fourth rising clock edge after the address is asserted (default for FB_CS0_B ).
+ */
+#define FB_CSCR_ASET(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
+#define FB_CSCR_EXTS_MASK                        (0x400000U)
+#define FB_CSCR_EXTS_SHIFT                       (22U)
+/*! EXTS - EXTS
+ *  0b0..Disabled. FB_TS_B/FB_ALE asserts for one bus clock cycle.
+ *  0b1..Enabled. FB_TS_B/FB_ALE remains asserted until the first positive clock edge after FB_CSn_B asserts.
+ */
+#define FB_CSCR_EXTS(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
+#define FB_CSCR_SWSEN_MASK                       (0x800000U)
+#define FB_CSCR_SWSEN_SHIFT                      (23U)
+/*! SWSEN - Secondary Wait State Enable
+ *  0b0..Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers.
+ *  0b1..Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations.
+ */
+#define FB_CSCR_SWSEN(x)                         (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
+#define FB_CSCR_SWS_MASK                         (0xFC000000U)
+#define FB_CSCR_SWS_SHIFT                        (26U)
+#define FB_CSCR_SWS(x)                           (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
+/*! @} */
+
+/* The count of FB_CSCR */
+#define FB_CSCR_COUNT                            (6U)
+
+/*! @name CSPMCR - Chip Select Port Multiplexing Control Register */
+/*! @{ */
+#define FB_CSPMCR_GROUP5_MASK                    (0xF000U)
+#define FB_CSPMCR_GROUP5_SHIFT                   (12U)
+/*! GROUP5 - FlexBus Signal Group 5 Multiplex control
+ *  0b0000..FB_TA_B
+ *  0b0001..FB_CS3_B. You must also write 1b to CSCR[AA].
+ *  0b0010..FB_BE_7_0_B. You must also write 1b to CSCR[AA].
+ */
+#define FB_CSPMCR_GROUP5(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
+#define FB_CSPMCR_GROUP4_MASK                    (0xF0000U)
+#define FB_CSPMCR_GROUP4_SHIFT                   (16U)
+/*! GROUP4 - FlexBus Signal Group 4 Multiplex control
+ *  0b0000..FB_TBST_B
+ *  0b0001..FB_CS2_B
+ *  0b0010..FB_BE_15_8_B
+ */
+#define FB_CSPMCR_GROUP4(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
+#define FB_CSPMCR_GROUP3_MASK                    (0xF00000U)
+#define FB_CSPMCR_GROUP3_SHIFT                   (20U)
+/*! GROUP3 - FlexBus Signal Group 3 Multiplex control
+ *  0b0000..FB_CS5_B
+ *  0b0001..FB_TSIZ1
+ *  0b0010..FB_BE_23_16_B
+ */
+#define FB_CSPMCR_GROUP3(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
+#define FB_CSPMCR_GROUP2_MASK                    (0xF000000U)
+#define FB_CSPMCR_GROUP2_SHIFT                   (24U)
+/*! GROUP2 - FlexBus Signal Group 2 Multiplex control
+ *  0b0000..FB_CS4_B
+ *  0b0001..FB_TSIZ0
+ *  0b0010..FB_BE_31_24_B
+ */
+#define FB_CSPMCR_GROUP2(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
+#define FB_CSPMCR_GROUP1_MASK                    (0xF0000000U)
+#define FB_CSPMCR_GROUP1_SHIFT                   (28U)
+/*! GROUP1 - FlexBus Signal Group 1 Multiplex control
+ *  0b0000..FB_ALE
+ *  0b0001..FB_CS1_B
+ *  0b0010..FB_TS_B
+ */
+#define FB_CSPMCR_GROUP1(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Masks */
+
+
+/* FB - Peripheral instance base addresses */
+/** Peripheral FB base address */
+#define FB_BASE                                  (0x4000C000u)
+/** Peripheral FB base pointer */
+#define FB                                       ((FB_Type *)FB_BASE)
+/** Array initializer of FB peripheral base addresses */
+#define FB_BASE_ADDRS                            { FB_BASE }
+/** Array initializer of FB peripheral base pointers */
+#define FB_BASE_PTRS                             { FB }
+
+/*!
+ * @}
+ */ /* end of group FB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FGPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
+ * @{
+ */
+
+/** FGPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
+} FGPIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FGPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
+ * @{
+ */
+
+/*! @name PDOR - Port Data Output Register */
+/*! @{ */
+#define FGPIO_PDOR_PDO_MASK                      (0xFFFFFFFFU)
+#define FGPIO_PDOR_PDO_SHIFT                     (0U)
+#define FGPIO_PDOR_PDO(x)                        (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK)
+/*! @} */
+
+/*! @name PSOR - Port Set Output Register */
+/*! @{ */
+#define FGPIO_PSOR_PTSO_MASK                     (0xFFFFFFFFU)
+#define FGPIO_PSOR_PTSO_SHIFT                    (0U)
+#define FGPIO_PSOR_PTSO(x)                       (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK)
+/*! @} */
+
+/*! @name PCOR - Port Clear Output Register */
+/*! @{ */
+#define FGPIO_PCOR_PTCO_MASK                     (0xFFFFFFFFU)
+#define FGPIO_PCOR_PTCO_SHIFT                    (0U)
+#define FGPIO_PCOR_PTCO(x)                       (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK)
+/*! @} */
+
+/*! @name PTOR - Port Toggle Output Register */
+/*! @{ */
+#define FGPIO_PTOR_PTTO_MASK                     (0xFFFFFFFFU)
+#define FGPIO_PTOR_PTTO_SHIFT                    (0U)
+#define FGPIO_PTOR_PTTO(x)                       (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK)
+/*! @} */
+
+/*! @name PDIR - Port Data Input Register */
+/*! @{ */
+#define FGPIO_PDIR_PDI_MASK                      (0xFFFFFFFFU)
+#define FGPIO_PDIR_PDI_SHIFT                     (0U)
+#define FGPIO_PDIR_PDI(x)                        (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK)
+/*! @} */
+
+/*! @name PDDR - Port Data Direction Register */
+/*! @{ */
+#define FGPIO_PDDR_PDD_MASK                      (0xFFFFFFFFU)
+#define FGPIO_PDDR_PDD_SHIFT                     (0U)
+#define FGPIO_PDDR_PDD(x)                        (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group FGPIO_Register_Masks */
+
+
+/* FGPIO - Peripheral instance base addresses */
+/** Peripheral FGPIOE base address */
+#define FGPIOE_BASE                              (0xF8000000u)
+/** Peripheral FGPIOE base pointer */
+#define FGPIOE                                   ((FGPIO_Type *)FGPIOE_BASE)
+/** Array initializer of FGPIO peripheral base addresses */
+#define FGPIO_BASE_ADDRS                         { 0u, 0u, 0u, 0u, FGPIOE_BASE }
+/** Array initializer of FGPIO peripheral base pointers */
+#define FGPIO_BASE_PTRS                          { (FGPIO_Type *)0u, (FGPIO_Type *)0u, (FGPIO_Type *)0u, (FGPIO_Type *)0u, FGPIOE }
+
+/*!
+ * @}
+ */ /* end of group FGPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FLEXIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
+ * @{
+ */
+
+/** FLEXIO - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __IO uint32_t CTRL;                              /**< FlexIO Control Register, offset: 0x8 */
+  __I  uint32_t PIN;                               /**< Pin State Register, offset: 0xC */
+  __IO uint32_t SHIFTSTAT;                         /**< Shifter Status Register, offset: 0x10 */
+  __IO uint32_t SHIFTERR;                          /**< Shifter Error Register, offset: 0x14 */
+  __IO uint32_t TIMSTAT;                           /**< Timer Status Register, offset: 0x18 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t SHIFTSIEN;                         /**< Shifter Status Interrupt Enable, offset: 0x20 */
+  __IO uint32_t SHIFTEIEN;                         /**< Shifter Error Interrupt Enable, offset: 0x24 */
+  __IO uint32_t TIMIEN;                            /**< Timer Interrupt Enable Register, offset: 0x28 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t SHIFTSDEN;                         /**< Shifter Status DMA Enable, offset: 0x30 */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t SHIFTSTATE;                        /**< Shifter State Register, offset: 0x40 */
+       uint8_t RESERVED_3[60];
+  __IO uint32_t SHIFTCTL[8];                       /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
+       uint8_t RESERVED_4[96];
+  __IO uint32_t SHIFTCFG[8];                       /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
+       uint8_t RESERVED_5[224];
+  __IO uint32_t SHIFTBUF[8];                       /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
+       uint8_t RESERVED_6[96];
+  __IO uint32_t SHIFTBUFBIS[8];                    /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
+       uint8_t RESERVED_7[96];
+  __IO uint32_t SHIFTBUFBYS[8];                    /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
+       uint8_t RESERVED_8[96];
+  __IO uint32_t SHIFTBUFBBS[8];                    /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
+       uint8_t RESERVED_9[96];
+  __IO uint32_t TIMCTL[8];                         /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
+       uint8_t RESERVED_10[96];
+  __IO uint32_t TIMCFG[8];                         /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
+       uint8_t RESERVED_11[96];
+  __IO uint32_t TIMCMP[8];                         /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
+       uint8_t RESERVED_12[352];
+  __IO uint32_t SHIFTBUFNBS[8];                    /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */
+       uint8_t RESERVED_13[96];
+  __IO uint32_t SHIFTBUFHWS[8];                    /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */
+       uint8_t RESERVED_14[96];
+  __IO uint32_t SHIFTBUFNIS[8];                    /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */
+} FLEXIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FLEXIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define FLEXIO_VERID_FEATURE_MASK                (0xFFFFU)
+#define FLEXIO_VERID_FEATURE_SHIFT               (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000000000000..Standard features implemented.
+ *  0b0000000000000001..Supports state, logic and parallel modes.
+ */
+#define FLEXIO_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
+#define FLEXIO_VERID_MINOR_MASK                  (0xFF0000U)
+#define FLEXIO_VERID_MINOR_SHIFT                 (16U)
+#define FLEXIO_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
+#define FLEXIO_VERID_MAJOR_MASK                  (0xFF000000U)
+#define FLEXIO_VERID_MAJOR_SHIFT                 (24U)
+#define FLEXIO_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define FLEXIO_PARAM_SHIFTER_MASK                (0xFFU)
+#define FLEXIO_PARAM_SHIFTER_SHIFT               (0U)
+#define FLEXIO_PARAM_SHIFTER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
+#define FLEXIO_PARAM_TIMER_MASK                  (0xFF00U)
+#define FLEXIO_PARAM_TIMER_SHIFT                 (8U)
+#define FLEXIO_PARAM_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
+#define FLEXIO_PARAM_PIN_MASK                    (0xFF0000U)
+#define FLEXIO_PARAM_PIN_SHIFT                   (16U)
+#define FLEXIO_PARAM_PIN(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
+#define FLEXIO_PARAM_TRIGGER_MASK                (0xFF000000U)
+#define FLEXIO_PARAM_TRIGGER_SHIFT               (24U)
+#define FLEXIO_PARAM_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
+/*! @} */
+
+/*! @name CTRL - FlexIO Control Register */
+/*! @{ */
+#define FLEXIO_CTRL_FLEXEN_MASK                  (0x1U)
+#define FLEXIO_CTRL_FLEXEN_SHIFT                 (0U)
+/*! FLEXEN - FlexIO Enable
+ *  0b0..FlexIO module is disabled.
+ *  0b1..FlexIO module is enabled.
+ */
+#define FLEXIO_CTRL_FLEXEN(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
+#define FLEXIO_CTRL_SWRST_MASK                   (0x2U)
+#define FLEXIO_CTRL_SWRST_SHIFT                  (1U)
+/*! SWRST - Software Reset
+ *  0b0..Software reset is disabled
+ *  0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.
+ */
+#define FLEXIO_CTRL_SWRST(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
+#define FLEXIO_CTRL_FASTACC_MASK                 (0x4U)
+#define FLEXIO_CTRL_FASTACC_SHIFT                (2U)
+/*! FASTACC - Fast Access
+ *  0b0..Configures for normal register accesses to FlexIO
+ *  0b1..Configures for fast register accesses to FlexIO
+ */
+#define FLEXIO_CTRL_FASTACC(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
+#define FLEXIO_CTRL_DBGE_MASK                    (0x40000000U)
+#define FLEXIO_CTRL_DBGE_SHIFT                   (30U)
+/*! DBGE - Debug Enable
+ *  0b0..FlexIO is disabled in debug modes.
+ *  0b1..FlexIO is enabled in debug modes
+ */
+#define FLEXIO_CTRL_DBGE(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
+#define FLEXIO_CTRL_DOZEN_MASK                   (0x80000000U)
+#define FLEXIO_CTRL_DOZEN_SHIFT                  (31U)
+/*! DOZEN - Doze Enable
+ *  0b0..FlexIO enabled in Doze modes.
+ *  0b1..FlexIO disabled in Doze modes.
+ */
+#define FLEXIO_CTRL_DOZEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
+/*! @} */
+
+/*! @name PIN - Pin State Register */
+/*! @{ */
+#define FLEXIO_PIN_PDI_MASK                      (0xFFFFFFFFU)
+#define FLEXIO_PIN_PDI_SHIFT                     (0U)
+#define FLEXIO_PIN_PDI(x)                        (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
+/*! @} */
+
+/*! @name SHIFTSTAT - Shifter Status Register */
+/*! @{ */
+#define FLEXIO_SHIFTSTAT_SSF_MASK                (0xFFU)
+#define FLEXIO_SHIFTSTAT_SSF_SHIFT               (0U)
+#define FLEXIO_SHIFTSTAT_SSF(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
+/*! @} */
+
+/*! @name SHIFTERR - Shifter Error Register */
+/*! @{ */
+#define FLEXIO_SHIFTERR_SEF_MASK                 (0xFFU)
+#define FLEXIO_SHIFTERR_SEF_SHIFT                (0U)
+#define FLEXIO_SHIFTERR_SEF(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
+/*! @} */
+
+/*! @name TIMSTAT - Timer Status Register */
+/*! @{ */
+#define FLEXIO_TIMSTAT_TSF_MASK                  (0xFFU)
+#define FLEXIO_TIMSTAT_TSF_SHIFT                 (0U)
+#define FLEXIO_TIMSTAT_TSF(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
+/*! @} */
+
+/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
+/*! @{ */
+#define FLEXIO_SHIFTSIEN_SSIE_MASK               (0xFFU)
+#define FLEXIO_SHIFTSIEN_SSIE_SHIFT              (0U)
+#define FLEXIO_SHIFTSIEN_SSIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
+/*! @} */
+
+/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
+/*! @{ */
+#define FLEXIO_SHIFTEIEN_SEIE_MASK               (0xFFU)
+#define FLEXIO_SHIFTEIEN_SEIE_SHIFT              (0U)
+#define FLEXIO_SHIFTEIEN_SEIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
+/*! @} */
+
+/*! @name TIMIEN - Timer Interrupt Enable Register */
+/*! @{ */
+#define FLEXIO_TIMIEN_TEIE_MASK                  (0xFFU)
+#define FLEXIO_TIMIEN_TEIE_SHIFT                 (0U)
+#define FLEXIO_TIMIEN_TEIE(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
+/*! @} */
+
+/*! @name SHIFTSDEN - Shifter Status DMA Enable */
+/*! @{ */
+#define FLEXIO_SHIFTSDEN_SSDE_MASK               (0xFFU)
+#define FLEXIO_SHIFTSDEN_SSDE_SHIFT              (0U)
+#define FLEXIO_SHIFTSDEN_SSDE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
+/*! @} */
+
+/*! @name SHIFTSTATE - Shifter State Register */
+/*! @{ */
+#define FLEXIO_SHIFTSTATE_STATE_MASK             (0x7U)
+#define FLEXIO_SHIFTSTATE_STATE_SHIFT            (0U)
+#define FLEXIO_SHIFTSTATE_STATE(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
+/*! @} */
+
+/*! @name SHIFTCTL - Shifter Control N Register */
+/*! @{ */
+#define FLEXIO_SHIFTCTL_SMOD_MASK                (0x7U)
+#define FLEXIO_SHIFTCTL_SMOD_SHIFT               (0U)
+/*! SMOD - Shifter Mode
+ *  0b000..Disabled.
+ *  0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
+ *  0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
+ *  0b011..Reserved.
+ *  0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
+ *  0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
+ *  0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes.
+ *  0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
+ */
+#define FLEXIO_SHIFTCTL_SMOD(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
+#define FLEXIO_SHIFTCTL_PINPOL_MASK              (0x80U)
+#define FLEXIO_SHIFTCTL_PINPOL_SHIFT             (7U)
+/*! PINPOL - Shifter Pin Polarity
+ *  0b0..Pin is active high
+ *  0b1..Pin is active low
+ */
+#define FLEXIO_SHIFTCTL_PINPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
+#define FLEXIO_SHIFTCTL_PINSEL_MASK              (0x1F00U)
+#define FLEXIO_SHIFTCTL_PINSEL_SHIFT             (8U)
+#define FLEXIO_SHIFTCTL_PINSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
+#define FLEXIO_SHIFTCTL_PINCFG_MASK              (0x30000U)
+#define FLEXIO_SHIFTCTL_PINCFG_SHIFT             (16U)
+/*! PINCFG - Shifter Pin Configuration
+ *  0b00..Shifter pin output disabled
+ *  0b01..Shifter pin open drain or bidirectional output enable
+ *  0b10..Shifter pin bidirectional output data
+ *  0b11..Shifter pin output
+ */
+#define FLEXIO_SHIFTCTL_PINCFG(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
+#define FLEXIO_SHIFTCTL_TIMPOL_MASK              (0x800000U)
+#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT             (23U)
+/*! TIMPOL - Timer Polarity
+ *  0b0..Shift on posedge of Shift clock
+ *  0b1..Shift on negedge of Shift clock
+ */
+#define FLEXIO_SHIFTCTL_TIMPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
+#define FLEXIO_SHIFTCTL_TIMSEL_MASK              (0x7000000U)
+#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT             (24U)
+#define FLEXIO_SHIFTCTL_TIMSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTCTL */
+#define FLEXIO_SHIFTCTL_COUNT                    (8U)
+
+/*! @name SHIFTCFG - Shifter Configuration N Register */
+/*! @{ */
+#define FLEXIO_SHIFTCFG_SSTART_MASK              (0x3U)
+#define FLEXIO_SHIFTCFG_SSTART_SHIFT             (0U)
+/*! SSTART - Shifter Start bit
+ *  0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
+ *  0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
+ *  0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
+ *  0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
+ */
+#define FLEXIO_SHIFTCFG_SSTART(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
+#define FLEXIO_SHIFTCFG_SSTOP_MASK               (0x30U)
+#define FLEXIO_SHIFTCFG_SSTOP_SHIFT              (4U)
+/*! SSTOP - Shifter Stop bit
+ *  0b00..Stop bit disabled for transmitter/receiver/match store
+ *  0b01..Reserved for transmitter/receiver/match store
+ *  0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
+ *  0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
+ */
+#define FLEXIO_SHIFTCFG_SSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
+#define FLEXIO_SHIFTCFG_INSRC_MASK               (0x100U)
+#define FLEXIO_SHIFTCFG_INSRC_SHIFT              (8U)
+/*! INSRC - Input Source
+ *  0b0..Pin
+ *  0b1..Shifter N+1 Output
+ */
+#define FLEXIO_SHIFTCFG_INSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
+#define FLEXIO_SHIFTCFG_PWIDTH_MASK              (0x1F0000U)
+#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT             (16U)
+#define FLEXIO_SHIFTCFG_PWIDTH(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTCFG */
+#define FLEXIO_SHIFTCFG_COUNT                    (8U)
+
+/*! @name SHIFTBUF - Shifter Buffer N Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK            (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT           (0U)
+#define FLEXIO_SHIFTBUF_SHIFTBUF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUF */
+#define FLEXIO_SHIFTBUF_COUNT                    (8U)
+
+/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK      (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT     (0U)
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFBIS */
+#define FLEXIO_SHIFTBUFBIS_COUNT                 (8U)
+
+/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK      (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT     (0U)
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFBYS */
+#define FLEXIO_SHIFTBUFBYS_COUNT                 (8U)
+
+/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK      (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT     (0U)
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFBBS */
+#define FLEXIO_SHIFTBUFBBS_COUNT                 (8U)
+
+/*! @name TIMCTL - Timer Control N Register */
+/*! @{ */
+#define FLEXIO_TIMCTL_TIMOD_MASK                 (0x3U)
+#define FLEXIO_TIMCTL_TIMOD_SHIFT                (0U)
+/*! TIMOD - Timer Mode
+ *  0b00..Timer Disabled.
+ *  0b01..Dual 8-bit counters baud mode.
+ *  0b10..Dual 8-bit counters PWM high mode.
+ *  0b11..Single 16-bit counter mode.
+ */
+#define FLEXIO_TIMCTL_TIMOD(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
+#define FLEXIO_TIMCTL_PINPOL_MASK                (0x80U)
+#define FLEXIO_TIMCTL_PINPOL_SHIFT               (7U)
+/*! PINPOL - Timer Pin Polarity
+ *  0b0..Pin is active high
+ *  0b1..Pin is active low
+ */
+#define FLEXIO_TIMCTL_PINPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
+#define FLEXIO_TIMCTL_PINSEL_MASK                (0x1F00U)
+#define FLEXIO_TIMCTL_PINSEL_SHIFT               (8U)
+#define FLEXIO_TIMCTL_PINSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
+#define FLEXIO_TIMCTL_PINCFG_MASK                (0x30000U)
+#define FLEXIO_TIMCTL_PINCFG_SHIFT               (16U)
+/*! PINCFG - Timer Pin Configuration
+ *  0b00..Timer pin output disabled
+ *  0b01..Timer pin open drain or bidirectional output enable
+ *  0b10..Timer pin bidirectional output data
+ *  0b11..Timer pin output
+ */
+#define FLEXIO_TIMCTL_PINCFG(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
+#define FLEXIO_TIMCTL_TRGSRC_MASK                (0x400000U)
+#define FLEXIO_TIMCTL_TRGSRC_SHIFT               (22U)
+/*! TRGSRC - Trigger Source
+ *  0b0..External trigger selected
+ *  0b1..Internal trigger selected
+ */
+#define FLEXIO_TIMCTL_TRGSRC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
+#define FLEXIO_TIMCTL_TRGPOL_MASK                (0x800000U)
+#define FLEXIO_TIMCTL_TRGPOL_SHIFT               (23U)
+/*! TRGPOL - Trigger Polarity
+ *  0b0..Trigger active high
+ *  0b1..Trigger active low
+ */
+#define FLEXIO_TIMCTL_TRGPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
+#define FLEXIO_TIMCTL_TRGSEL_MASK                (0x3F000000U)
+#define FLEXIO_TIMCTL_TRGSEL_SHIFT               (24U)
+#define FLEXIO_TIMCTL_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
+/*! @} */
+
+/* The count of FLEXIO_TIMCTL */
+#define FLEXIO_TIMCTL_COUNT                      (8U)
+
+/*! @name TIMCFG - Timer Configuration N Register */
+/*! @{ */
+#define FLEXIO_TIMCFG_TSTART_MASK                (0x2U)
+#define FLEXIO_TIMCFG_TSTART_SHIFT               (1U)
+/*! TSTART - Timer Start Bit
+ *  0b0..Start bit disabled
+ *  0b1..Start bit enabled
+ */
+#define FLEXIO_TIMCFG_TSTART(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
+#define FLEXIO_TIMCFG_TSTOP_MASK                 (0x30U)
+#define FLEXIO_TIMCFG_TSTOP_SHIFT                (4U)
+/*! TSTOP - Timer Stop Bit
+ *  0b00..Stop bit disabled
+ *  0b01..Stop bit is enabled on timer compare
+ *  0b10..Stop bit is enabled on timer disable
+ *  0b11..Stop bit is enabled on timer compare and timer disable
+ */
+#define FLEXIO_TIMCFG_TSTOP(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
+#define FLEXIO_TIMCFG_TIMENA_MASK                (0x700U)
+#define FLEXIO_TIMCFG_TIMENA_SHIFT               (8U)
+/*! TIMENA - Timer Enable
+ *  0b000..Timer always enabled
+ *  0b001..Timer enabled on Timer N-1 enable
+ *  0b010..Timer enabled on Trigger high
+ *  0b011..Timer enabled on Trigger high and Pin high
+ *  0b100..Timer enabled on Pin rising edge
+ *  0b101..Timer enabled on Pin rising edge and Trigger high
+ *  0b110..Timer enabled on Trigger rising edge
+ *  0b111..Timer enabled on Trigger rising or falling edge
+ */
+#define FLEXIO_TIMCFG_TIMENA(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
+#define FLEXIO_TIMCFG_TIMDIS_MASK                (0x7000U)
+#define FLEXIO_TIMCFG_TIMDIS_SHIFT               (12U)
+/*! TIMDIS - Timer Disable
+ *  0b000..Timer never disabled
+ *  0b001..Timer disabled on Timer N-1 disable
+ *  0b010..Timer disabled on Timer compare (upper 8-bits match and decrement)
+ *  0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
+ *  0b100..Timer disabled on Pin rising or falling edge
+ *  0b101..Timer disabled on Pin rising or falling edge provided Trigger is high
+ *  0b110..Timer disabled on Trigger falling edge
+ *  0b111..Reserved
+ */
+#define FLEXIO_TIMCFG_TIMDIS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
+#define FLEXIO_TIMCFG_TIMRST_MASK                (0x70000U)
+#define FLEXIO_TIMCFG_TIMRST_SHIFT               (16U)
+/*! TIMRST - Timer Reset
+ *  0b000..Timer never reset
+ *  0b001..Reserved
+ *  0b010..Timer reset on Timer Pin equal to Timer Output
+ *  0b011..Timer reset on Timer Trigger equal to Timer Output
+ *  0b100..Timer reset on Timer Pin rising edge
+ *  0b101..Reserved
+ *  0b110..Timer reset on Trigger rising edge
+ *  0b111..Timer reset on Trigger rising or falling edge
+ */
+#define FLEXIO_TIMCFG_TIMRST(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
+#define FLEXIO_TIMCFG_TIMDEC_MASK                (0x300000U)
+#define FLEXIO_TIMCFG_TIMDEC_SHIFT               (20U)
+/*! TIMDEC - Timer Decrement
+ *  0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output.
+ *  0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
+ *  0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input.
+ *  0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
+ */
+#define FLEXIO_TIMCFG_TIMDEC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
+#define FLEXIO_TIMCFG_TIMOUT_MASK                (0x3000000U)
+#define FLEXIO_TIMCFG_TIMOUT_SHIFT               (24U)
+/*! TIMOUT - Timer Output
+ *  0b00..Timer output is logic one when enabled and is not affected by timer reset
+ *  0b01..Timer output is logic zero when enabled and is not affected by timer reset
+ *  0b10..Timer output is logic one when enabled and on timer reset
+ *  0b11..Timer output is logic zero when enabled and on timer reset
+ */
+#define FLEXIO_TIMCFG_TIMOUT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
+/*! @} */
+
+/* The count of FLEXIO_TIMCFG */
+#define FLEXIO_TIMCFG_COUNT                      (8U)
+
+/*! @name TIMCMP - Timer Compare N Register */
+/*! @{ */
+#define FLEXIO_TIMCMP_CMP_MASK                   (0xFFFFU)
+#define FLEXIO_TIMCMP_CMP_SHIFT                  (0U)
+#define FLEXIO_TIMCMP_CMP(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
+/*! @} */
+
+/* The count of FLEXIO_TIMCMP */
+#define FLEXIO_TIMCMP_COUNT                      (8U)
+
+/*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK      (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT     (0U)
+#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFNBS */
+#define FLEXIO_SHIFTBUFNBS_COUNT                 (8U)
+
+/*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK      (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT     (0U)
+#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFHWS */
+#define FLEXIO_SHIFTBUFHWS_COUNT                 (8U)
+
+/*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */
+/*! @{ */
+#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK      (0xFFFFFFFFU)
+#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT     (0U)
+#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
+/*! @} */
+
+/* The count of FLEXIO_SHIFTBUFNIS */
+#define FLEXIO_SHIFTBUFNIS_COUNT                 (8U)
+
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Register_Masks */
+
+
+/* FLEXIO - Peripheral instance base addresses */
+/** Peripheral FLEXIO0 base address */
+#define FLEXIO0_BASE                             (0x40039000u)
+/** Peripheral FLEXIO0 base pointer */
+#define FLEXIO0                                  ((FLEXIO_Type *)FLEXIO0_BASE)
+/** Array initializer of FLEXIO peripheral base addresses */
+#define FLEXIO_BASE_ADDRS                        { FLEXIO0_BASE }
+/** Array initializer of FLEXIO peripheral base pointers */
+#define FLEXIO_BASE_PTRS                         { FLEXIO0 }
+/** Interrupt vectors for the FLEXIO peripheral type */
+#define FLEXIO_IRQS                              { FLEXIO0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFE Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
+ * @{
+ */
+
+/** FTFE - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t FSTAT;                              /**< Flash Status Register, offset: 0x0 */
+  __IO uint8_t FCNFG;                              /**< Flash Configuration Register, offset: 0x1 */
+  __I  uint8_t FSEC;                               /**< Flash Security Register, offset: 0x2 */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t FCCOB3;                             /**< Flash Common Command Object Registers, offset: 0x4 */
+  __IO uint8_t FCCOB2;                             /**< Flash Common Command Object Registers, offset: 0x5 */
+  __IO uint8_t FCCOB1;                             /**< Flash Common Command Object Registers, offset: 0x6 */
+  __IO uint8_t FCCOB0;                             /**< Flash Common Command Object Registers, offset: 0x7 */
+  __IO uint8_t FCCOB7;                             /**< Flash Common Command Object Registers, offset: 0x8 */
+  __IO uint8_t FCCOB6;                             /**< Flash Common Command Object Registers, offset: 0x9 */
+  __IO uint8_t FCCOB5;                             /**< Flash Common Command Object Registers, offset: 0xA */
+  __IO uint8_t FCCOB4;                             /**< Flash Common Command Object Registers, offset: 0xB */
+  __IO uint8_t FCCOBB;                             /**< Flash Common Command Object Registers, offset: 0xC */
+  __IO uint8_t FCCOBA;                             /**< Flash Common Command Object Registers, offset: 0xD */
+  __IO uint8_t FCCOB9;                             /**< Flash Common Command Object Registers, offset: 0xE */
+  __IO uint8_t FCCOB8;                             /**< Flash Common Command Object Registers, offset: 0xF */
+  __I  uint8_t FOPT3;                              /**< Flash Option Registers, offset: 0x10 */
+  __I  uint8_t FOPT2;                              /**< Flash Option Registers, offset: 0x11 */
+  __I  uint8_t FOPT1;                              /**< Flash Option Registers, offset: 0x12 */
+  __I  uint8_t FOPT0;                              /**< Flash Option Registers, offset: 0x13 */
+       uint8_t RESERVED_1[4];
+  __IO uint8_t FPROTH3;                            /**< Primary Program Flash Protection Registers, offset: 0x18 */
+  __IO uint8_t FPROTH2;                            /**< Primary Program Flash Protection Registers, offset: 0x19 */
+  __IO uint8_t FPROTH1;                            /**< Primary Program Flash Protection Registers, offset: 0x1A */
+  __IO uint8_t FPROTH0;                            /**< Primary Program Flash Protection Registers, offset: 0x1B */
+  __IO uint8_t FPROTL3;                            /**< Primary Program Flash Protection Registers, offset: 0x1C */
+  __IO uint8_t FPROTL2;                            /**< Primary Program Flash Protection Registers, offset: 0x1D */
+  __IO uint8_t FPROTL1;                            /**< Primary Program Flash Protection Registers, offset: 0x1E */
+  __IO uint8_t FPROTL0;                            /**< Primary Program Flash Protection Registers, offset: 0x1F */
+       uint8_t RESERVED_2[4];
+  __IO uint8_t FPROTSL;                            /**< Secondary Program Flash Protection Registers, offset: 0x24 */
+  __IO uint8_t FPROTSH;                            /**< Secondary Program Flash Protection Registers, offset: 0x25 */
+       uint8_t RESERVED_3[6];
+  __I  uint8_t FACSS;                              /**< Primary Flash Access Segment Size Register, offset: 0x2C */
+  __I  uint8_t FACSN;                              /**< Primary Flash Access Segment Number Register, offset: 0x2D */
+  __I  uint8_t FACSSS;                             /**< Secondary Flash Access Segment Size Register, offset: 0x2E */
+  __I  uint8_t FACSNS;                             /**< Secondary Flash Access Segment Number Register, offset: 0x2F */
+  __I  uint8_t XACCH3;                             /**< Primary Execute-only Access Registers, offset: 0x30 */
+  __I  uint8_t XACCH2;                             /**< Primary Execute-only Access Registers, offset: 0x31 */
+  __I  uint8_t XACCH1;                             /**< Primary Execute-only Access Registers, offset: 0x32 */
+  __I  uint8_t XACCH0;                             /**< Primary Execute-only Access Registers, offset: 0x33 */
+  __I  uint8_t XACCL3;                             /**< Primary Execute-only Access Registers, offset: 0x34 */
+  __I  uint8_t XACCL2;                             /**< Primary Execute-only Access Registers, offset: 0x35 */
+  __I  uint8_t XACCL1;                             /**< Primary Execute-only Access Registers, offset: 0x36 */
+  __I  uint8_t XACCL0;                             /**< Primary Execute-only Access Registers, offset: 0x37 */
+  __I  uint8_t SACCH3;                             /**< Primary Supervisor-only Access Registers, offset: 0x38 */
+  __I  uint8_t SACCH2;                             /**< Primary Supervisor-only Access Registers, offset: 0x39 */
+  __I  uint8_t SACCH1;                             /**< Primary Supervisor-only Access Registers, offset: 0x3A */
+  __I  uint8_t SACCH0;                             /**< Primary Supervisor-only Access Registers, offset: 0x3B */
+  __I  uint8_t SACCL3;                             /**< Primary Supervisor-only Access Registers, offset: 0x3C */
+  __I  uint8_t SACCL2;                             /**< Primary Supervisor-only Access Registers, offset: 0x3D */
+  __I  uint8_t SACCL1;                             /**< Primary Supervisor-only Access Registers, offset: 0x3E */
+  __I  uint8_t SACCL0;                             /**< Primary Supervisor-only Access Registers, offset: 0x3F */
+       uint8_t RESERVED_4[4];
+  __I  uint8_t XACCSL;                             /**< Secondary Execute-only Access Registers, offset: 0x44 */
+  __I  uint8_t XACCSH;                             /**< Secondary Execute-only Access Registers, offset: 0x45 */
+       uint8_t RESERVED_5[6];
+  __I  uint8_t SACCSL;                             /**< Secondary Supervisor-only Access Registers, offset: 0x4C */
+  __I  uint8_t SACCSH;                             /**< Secondary Supervisor-only Access Registers, offset: 0x4D */
+       uint8_t RESERVED_6[4];
+  __I  uint8_t FSTDBYCTL;                          /**< Flash Standby Control Register, offset: 0x52 */
+  __IO uint8_t FSTDBY;                             /**< Flash Standby Register, offset: 0x53 */
+} FTFE_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FTFE Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Masks FTFE Register Masks
+ * @{
+ */
+
+/*! @name FSTAT - Flash Status Register */
+/*! @{ */
+#define FTFE_FSTAT_MGSTAT0_MASK                  (0x1U)
+#define FTFE_FSTAT_MGSTAT0_SHIFT                 (0U)
+#define FTFE_FSTAT_MGSTAT0(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK)
+#define FTFE_FSTAT_FPVIOL_MASK                   (0x10U)
+#define FTFE_FSTAT_FPVIOL_SHIFT                  (4U)
+/*! FPVIOL - Flash Protection Violation Flag
+ *  0b0..No protection violation detected
+ *  0b1..Protection violation detected
+ */
+#define FTFE_FSTAT_FPVIOL(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)
+#define FTFE_FSTAT_ACCERR_MASK                   (0x20U)
+#define FTFE_FSTAT_ACCERR_SHIFT                  (5U)
+/*! ACCERR - Flash Access Error Flag
+ *  0b0..No access error detected
+ *  0b1..Access error detected
+ */
+#define FTFE_FSTAT_ACCERR(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)
+#define FTFE_FSTAT_RDCOLERR_MASK                 (0x40U)
+#define FTFE_FSTAT_RDCOLERR_SHIFT                (6U)
+/*! RDCOLERR - Flash Read Collision Error Flag
+ *  0b0..No collision error detected
+ *  0b1..Collision error detected
+ */
+#define FTFE_FSTAT_RDCOLERR(x)                   (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)
+#define FTFE_FSTAT_CCIF_MASK                     (0x80U)
+#define FTFE_FSTAT_CCIF_SHIFT                    (7U)
+/*! CCIF - Command Complete Interrupt Flag
+ *  0b0..Flash command in progress
+ *  0b1..Flash command has completed
+ */
+#define FTFE_FSTAT_CCIF(x)                       (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)
+/*! @} */
+
+/*! @name FCNFG - Flash Configuration Register */
+/*! @{ */
+#define FTFE_FCNFG_RAMRDY_MASK                   (0x2U)
+#define FTFE_FCNFG_RAMRDY_SHIFT                  (1U)
+/*! RAMRDY - RAM Ready
+ *  0b0..Programming acceleration RAM is not available
+ *  0b1..Programming acceleration RAM is available
+ */
+#define FTFE_FCNFG_RAMRDY(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)
+#define FTFE_FCNFG_CRCRDY_MASK                   (0x4U)
+#define FTFE_FCNFG_CRCRDY_SHIFT                  (2U)
+/*! CRCRDY - CRC Ready
+ *  0b0..Programming acceleration RAM is not available for CRC operations
+ *  0b1..Programming acceleration RAM is available for CRC operations
+ */
+#define FTFE_FCNFG_CRCRDY(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CRCRDY_SHIFT)) & FTFE_FCNFG_CRCRDY_MASK)
+#define FTFE_FCNFG_SWAP_MASK                     (0x8U)
+#define FTFE_FCNFG_SWAP_SHIFT                    (3U)
+/*! SWAP - Swap
+ *  0b0..Program flash 0 block is located at relative address 0x0000
+ *  0b1..Program flash 1 block is located at relative address 0x0000
+ */
+#define FTFE_FCNFG_SWAP(x)                       (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK)
+#define FTFE_FCNFG_ERSSUSP_MASK                  (0x10U)
+#define FTFE_FCNFG_ERSSUSP_SHIFT                 (4U)
+/*! ERSSUSP - Erase Suspend
+ *  0b0..No suspend requested
+ *  0b1..Suspend the current Erase Flash Sector command execution
+ */
+#define FTFE_FCNFG_ERSSUSP(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)
+#define FTFE_FCNFG_ERSAREQ_MASK                  (0x20U)
+#define FTFE_FCNFG_ERSAREQ_SHIFT                 (5U)
+/*! ERSAREQ - Erase All Request
+ *  0b0..No request or request complete
+ *  0b1..Request to: (1) run the Erase All Blocks command, (2) verify the erased state, (3) program the security byte in the Flash Configuration Field to the unsecure state, and (4) release MCU security by setting the FSEC[SEC] field to the unsecure state.
+ */
+#define FTFE_FCNFG_ERSAREQ(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)
+#define FTFE_FCNFG_RDCOLLIE_MASK                 (0x40U)
+#define FTFE_FCNFG_RDCOLLIE_SHIFT                (6U)
+/*! RDCOLLIE - Read Collision Error Interrupt Enable
+ *  0b0..Read collision error interrupt disabled
+ *  0b1..Read collision error interrupt enabled. An interrupt request is generated whenever a flash read collision error is detected (see the description of FSTAT[RDCOLERR]).
+ */
+#define FTFE_FCNFG_RDCOLLIE(x)                   (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)
+#define FTFE_FCNFG_CCIE_MASK                     (0x80U)
+#define FTFE_FCNFG_CCIE_SHIFT                    (7U)
+/*! CCIE - Command Complete Interrupt Enable
+ *  0b0..Command complete interrupt disabled
+ *  0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.
+ */
+#define FTFE_FCNFG_CCIE(x)                       (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)
+/*! @} */
+
+/*! @name FSEC - Flash Security Register */
+/*! @{ */
+#define FTFE_FSEC_SEC_MASK                       (0x3U)
+#define FTFE_FSEC_SEC_SHIFT                      (0U)
+/*! SEC - Flash Security
+ *  0b00..MCU security status is secure
+ *  0b01..MCU security status is secure
+ *  0b10..MCU security status is unsecure (The standard shipping condition of the flash module is unsecure.)
+ *  0b11..MCU security status is secure
+ */
+#define FTFE_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)
+#define FTFE_FSEC_FSLACC_MASK                    (0xCU)
+#define FTFE_FSEC_FSLACC_SHIFT                   (2U)
+/*! FSLACC - Factory Security Level Access Code
+ *  0b00..Factory access granted
+ *  0b01..Factory access denied
+ *  0b10..Factory access denied
+ *  0b11..Factory access granted
+ */
+#define FTFE_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)
+#define FTFE_FSEC_MEEN_MASK                      (0x30U)
+#define FTFE_FSEC_MEEN_SHIFT                     (4U)
+/*! MEEN - Mass Erase Enable Bits
+ *  0b00..Mass erase is enabled
+ *  0b01..Mass erase is enabled
+ *  0b10..Mass erase is disabled
+ *  0b11..Mass erase is enabled
+ */
+#define FTFE_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)
+#define FTFE_FSEC_KEYEN_MASK                     (0xC0U)
+#define FTFE_FSEC_KEYEN_SHIFT                    (6U)
+/*! KEYEN - Backdoor Key Security Enable
+ *  0b00..Backdoor key access disabled
+ *  0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
+ *  0b10..Backdoor key access enabled
+ *  0b11..Backdoor key access disabled
+ */
+#define FTFE_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)
+/*! @} */
+
+/*! @name FCCOB3 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB3_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB3_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB2 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB2_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB2_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB1 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB1_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB1_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB0 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB0_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB0_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB7 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB7_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB7_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB6 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB6_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB6_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB5 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB5_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB5_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB4 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB4_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB4_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOBB - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOBB_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOBB_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOBA - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOBA_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOBA_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB9 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB9_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB9_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK)
+/*! @} */
+
+/*! @name FCCOB8 - Flash Common Command Object Registers */
+/*! @{ */
+#define FTFE_FCCOB8_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB8_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK)
+/*! @} */
+
+/*! @name FOPT3 - Flash Option Registers */
+/*! @{ */
+#define FTFE_FOPT3_OPT_MASK                      (0xFFU)
+#define FTFE_FOPT3_OPT_SHIFT                     (0U)
+#define FTFE_FOPT3_OPT(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT3_OPT_SHIFT)) & FTFE_FOPT3_OPT_MASK)
+/*! @} */
+
+/*! @name FOPT2 - Flash Option Registers */
+/*! @{ */
+#define FTFE_FOPT2_OPT_MASK                      (0xFFU)
+#define FTFE_FOPT2_OPT_SHIFT                     (0U)
+#define FTFE_FOPT2_OPT(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT2_OPT_SHIFT)) & FTFE_FOPT2_OPT_MASK)
+/*! @} */
+
+/*! @name FOPT1 - Flash Option Registers */
+/*! @{ */
+#define FTFE_FOPT1_OPT_MASK                      (0xFFU)
+#define FTFE_FOPT1_OPT_SHIFT                     (0U)
+#define FTFE_FOPT1_OPT(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT1_OPT_SHIFT)) & FTFE_FOPT1_OPT_MASK)
+/*! @} */
+
+/*! @name FOPT0 - Flash Option Registers */
+/*! @{ */
+#define FTFE_FOPT0_OPT_MASK                      (0xFFU)
+#define FTFE_FOPT0_OPT_SHIFT                     (0U)
+#define FTFE_FOPT0_OPT(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT0_OPT_SHIFT)) & FTFE_FOPT0_OPT_MASK)
+/*! @} */
+
+/*! @name FPROTH3 - Primary Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROTH3_PROT_MASK                   (0xFFU)
+#define FTFE_FPROTH3_PROT_SHIFT                  (0U)
+#define FTFE_FPROTH3_PROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTH3_PROT_SHIFT)) & FTFE_FPROTH3_PROT_MASK)
+/*! @} */
+
+/*! @name FPROTH2 - Primary Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROTH2_PROT_MASK                   (0xFFU)
+#define FTFE_FPROTH2_PROT_SHIFT                  (0U)
+#define FTFE_FPROTH2_PROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTH2_PROT_SHIFT)) & FTFE_FPROTH2_PROT_MASK)
+/*! @} */
+
+/*! @name FPROTH1 - Primary Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROTH1_PROT_MASK                   (0xFFU)
+#define FTFE_FPROTH1_PROT_SHIFT                  (0U)
+#define FTFE_FPROTH1_PROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTH1_PROT_SHIFT)) & FTFE_FPROTH1_PROT_MASK)
+/*! @} */
+
+/*! @name FPROTH0 - Primary Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROTH0_PROT_MASK                   (0xFFU)
+#define FTFE_FPROTH0_PROT_SHIFT                  (0U)
+#define FTFE_FPROTH0_PROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTH0_PROT_SHIFT)) & FTFE_FPROTH0_PROT_MASK)
+/*! @} */
+
+/*! @name FPROTL3 - Primary Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROTL3_PROT_MASK                   (0xFFU)
+#define FTFE_FPROTL3_PROT_SHIFT                  (0U)
+#define FTFE_FPROTL3_PROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTL3_PROT_SHIFT)) & FTFE_FPROTL3_PROT_MASK)
+/*! @} */
+
+/*! @name FPROTL2 - Primary Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROTL2_PROT_MASK                   (0xFFU)
+#define FTFE_FPROTL2_PROT_SHIFT                  (0U)
+#define FTFE_FPROTL2_PROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTL2_PROT_SHIFT)) & FTFE_FPROTL2_PROT_MASK)
+/*! @} */
+
+/*! @name FPROTL1 - Primary Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROTL1_PROT_MASK                   (0xFFU)
+#define FTFE_FPROTL1_PROT_SHIFT                  (0U)
+#define FTFE_FPROTL1_PROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTL1_PROT_SHIFT)) & FTFE_FPROTL1_PROT_MASK)
+/*! @} */
+
+/*! @name FPROTL0 - Primary Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROTL0_PROT_MASK                   (0xFFU)
+#define FTFE_FPROTL0_PROT_SHIFT                  (0U)
+#define FTFE_FPROTL0_PROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTL0_PROT_SHIFT)) & FTFE_FPROTL0_PROT_MASK)
+/*! @} */
+
+/*! @name FPROTSL - Secondary Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROTSL_PROTS_MASK                  (0xFFU)
+#define FTFE_FPROTSL_PROTS_SHIFT                 (0U)
+#define FTFE_FPROTSL_PROTS(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTSL_PROTS_SHIFT)) & FTFE_FPROTSL_PROTS_MASK)
+/*! @} */
+
+/*! @name FPROTSH - Secondary Program Flash Protection Registers */
+/*! @{ */
+#define FTFE_FPROTSH_PROTS_MASK                  (0xFFU)
+#define FTFE_FPROTSH_PROTS_SHIFT                 (0U)
+#define FTFE_FPROTSH_PROTS(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_FPROTSH_PROTS_SHIFT)) & FTFE_FPROTSH_PROTS_MASK)
+/*! @} */
+
+/*! @name FACSS - Primary Flash Access Segment Size Register */
+/*! @{ */
+#define FTFE_FACSS_SGSIZE_MASK                   (0xFFU)
+#define FTFE_FACSS_SGSIZE_SHIFT                  (0U)
+#define FTFE_FACSS_SGSIZE(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FACSS_SGSIZE_SHIFT)) & FTFE_FACSS_SGSIZE_MASK)
+/*! @} */
+
+/*! @name FACSN - Primary Flash Access Segment Number Register */
+/*! @{ */
+#define FTFE_FACSN_NUMSG_MASK                    (0xFFU)
+#define FTFE_FACSN_NUMSG_SHIFT                   (0U)
+/*! NUMSG - Number of Segments Indicator
+ *  0b00110000..Primary Program flash memory is divided into 48 segments (768 Kbytes, 1.5 Mbytes)
+ *  0b01000000..Primary Program flash memory is divided into 64 segments (512 Kbytes, 1 Mbyte, 2 Mbytes)
+ */
+#define FTFE_FACSN_NUMSG(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FACSN_NUMSG_SHIFT)) & FTFE_FACSN_NUMSG_MASK)
+/*! @} */
+
+/*! @name FACSSS - Secondary Flash Access Segment Size Register */
+/*! @{ */
+#define FTFE_FACSSS_SGSIZE_S_MASK                (0xFFU)
+#define FTFE_FACSSS_SGSIZE_S_SHIFT               (0U)
+#define FTFE_FACSSS_SGSIZE_S(x)                  (((uint8_t)(((uint8_t)(x)) << FTFE_FACSSS_SGSIZE_S_SHIFT)) & FTFE_FACSSS_SGSIZE_S_MASK)
+/*! @} */
+
+/*! @name FACSNS - Secondary Flash Access Segment Number Register */
+/*! @{ */
+#define FTFE_FACSNS_NUMSG_S_MASK                 (0xFFU)
+#define FTFE_FACSNS_NUMSG_S_SHIFT                (0U)
+/*! NUMSG_S - Number of Segments Indicator
+ *  0b00010000..Secondary Program flash memory is divided into 16 segments
+ */
+#define FTFE_FACSNS_NUMSG_S(x)                   (((uint8_t)(((uint8_t)(x)) << FTFE_FACSNS_NUMSG_S_SHIFT)) & FTFE_FACSNS_NUMSG_S_MASK)
+/*! @} */
+
+/*! @name XACCH3 - Primary Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCH3_XA_MASK                      (0xFFU)
+#define FTFE_XACCH3_XA_SHIFT                     (0U)
+#define FTFE_XACCH3_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH3_XA_SHIFT)) & FTFE_XACCH3_XA_MASK)
+/*! @} */
+
+/*! @name XACCH2 - Primary Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCH2_XA_MASK                      (0xFFU)
+#define FTFE_XACCH2_XA_SHIFT                     (0U)
+#define FTFE_XACCH2_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH2_XA_SHIFT)) & FTFE_XACCH2_XA_MASK)
+/*! @} */
+
+/*! @name XACCH1 - Primary Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCH1_XA_MASK                      (0xFFU)
+#define FTFE_XACCH1_XA_SHIFT                     (0U)
+#define FTFE_XACCH1_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH1_XA_SHIFT)) & FTFE_XACCH1_XA_MASK)
+/*! @} */
+
+/*! @name XACCH0 - Primary Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCH0_XA_MASK                      (0xFFU)
+#define FTFE_XACCH0_XA_SHIFT                     (0U)
+#define FTFE_XACCH0_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH0_XA_SHIFT)) & FTFE_XACCH0_XA_MASK)
+/*! @} */
+
+/*! @name XACCL3 - Primary Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCL3_XA_MASK                      (0xFFU)
+#define FTFE_XACCL3_XA_SHIFT                     (0U)
+#define FTFE_XACCL3_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL3_XA_SHIFT)) & FTFE_XACCL3_XA_MASK)
+/*! @} */
+
+/*! @name XACCL2 - Primary Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCL2_XA_MASK                      (0xFFU)
+#define FTFE_XACCL2_XA_SHIFT                     (0U)
+#define FTFE_XACCL2_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL2_XA_SHIFT)) & FTFE_XACCL2_XA_MASK)
+/*! @} */
+
+/*! @name XACCL1 - Primary Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCL1_XA_MASK                      (0xFFU)
+#define FTFE_XACCL1_XA_SHIFT                     (0U)
+#define FTFE_XACCL1_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL1_XA_SHIFT)) & FTFE_XACCL1_XA_MASK)
+/*! @} */
+
+/*! @name XACCL0 - Primary Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCL0_XA_MASK                      (0xFFU)
+#define FTFE_XACCL0_XA_SHIFT                     (0U)
+#define FTFE_XACCL0_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL0_XA_SHIFT)) & FTFE_XACCL0_XA_MASK)
+/*! @} */
+
+/*! @name SACCH3 - Primary Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCH3_SA_MASK                      (0xFFU)
+#define FTFE_SACCH3_SA_SHIFT                     (0U)
+#define FTFE_SACCH3_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH3_SA_SHIFT)) & FTFE_SACCH3_SA_MASK)
+/*! @} */
+
+/*! @name SACCH2 - Primary Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCH2_SA_MASK                      (0xFFU)
+#define FTFE_SACCH2_SA_SHIFT                     (0U)
+#define FTFE_SACCH2_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH2_SA_SHIFT)) & FTFE_SACCH2_SA_MASK)
+/*! @} */
+
+/*! @name SACCH1 - Primary Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCH1_SA_MASK                      (0xFFU)
+#define FTFE_SACCH1_SA_SHIFT                     (0U)
+#define FTFE_SACCH1_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH1_SA_SHIFT)) & FTFE_SACCH1_SA_MASK)
+/*! @} */
+
+/*! @name SACCH0 - Primary Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCH0_SA_MASK                      (0xFFU)
+#define FTFE_SACCH0_SA_SHIFT                     (0U)
+#define FTFE_SACCH0_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH0_SA_SHIFT)) & FTFE_SACCH0_SA_MASK)
+/*! @} */
+
+/*! @name SACCL3 - Primary Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCL3_SA_MASK                      (0xFFU)
+#define FTFE_SACCL3_SA_SHIFT                     (0U)
+#define FTFE_SACCL3_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL3_SA_SHIFT)) & FTFE_SACCL3_SA_MASK)
+/*! @} */
+
+/*! @name SACCL2 - Primary Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCL2_SA_MASK                      (0xFFU)
+#define FTFE_SACCL2_SA_SHIFT                     (0U)
+#define FTFE_SACCL2_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL2_SA_SHIFT)) & FTFE_SACCL2_SA_MASK)
+/*! @} */
+
+/*! @name SACCL1 - Primary Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCL1_SA_MASK                      (0xFFU)
+#define FTFE_SACCL1_SA_SHIFT                     (0U)
+#define FTFE_SACCL1_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL1_SA_SHIFT)) & FTFE_SACCL1_SA_MASK)
+/*! @} */
+
+/*! @name SACCL0 - Primary Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCL0_SA_MASK                      (0xFFU)
+#define FTFE_SACCL0_SA_SHIFT                     (0U)
+#define FTFE_SACCL0_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL0_SA_SHIFT)) & FTFE_SACCL0_SA_MASK)
+/*! @} */
+
+/*! @name XACCSL - Secondary Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCSL_XA_S_MASK                    (0xFFU)
+#define FTFE_XACCSL_XA_S_SHIFT                   (0U)
+#define FTFE_XACCSL_XA_S(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_XACCSL_XA_S_SHIFT)) & FTFE_XACCSL_XA_S_MASK)
+/*! @} */
+
+/*! @name XACCSH - Secondary Execute-only Access Registers */
+/*! @{ */
+#define FTFE_XACCSH_XA_S_MASK                    (0xFFU)
+#define FTFE_XACCSH_XA_S_SHIFT                   (0U)
+#define FTFE_XACCSH_XA_S(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_XACCSH_XA_S_SHIFT)) & FTFE_XACCSH_XA_S_MASK)
+/*! @} */
+
+/*! @name SACCSL - Secondary Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCSL_SA_S_MASK                    (0xFFU)
+#define FTFE_SACCSL_SA_S_SHIFT                   (0U)
+#define FTFE_SACCSL_SA_S(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_SACCSL_SA_S_SHIFT)) & FTFE_SACCSL_SA_S_MASK)
+/*! @} */
+
+/*! @name SACCSH - Secondary Supervisor-only Access Registers */
+/*! @{ */
+#define FTFE_SACCSH_SA_S_MASK                    (0xFFU)
+#define FTFE_SACCSH_SA_S_SHIFT                   (0U)
+#define FTFE_SACCSH_SA_S(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_SACCSH_SA_S_SHIFT)) & FTFE_SACCSH_SA_S_MASK)
+/*! @} */
+
+/*! @name FSTDBYCTL - Flash Standby Control Register */
+/*! @{ */
+#define FTFE_FSTDBYCTL_STDBYDIS_MASK             (0x1U)
+#define FTFE_FSTDBYCTL_STDBYDIS_SHIFT            (0U)
+/*! STDBYDIS - Standy Mode Disable
+ *  0b0..Standby mode enabled for flash blocks selected by STDBYx
+ *  0b1..Standby mode disabled (STDBYx ignored)
+ */
+#define FTFE_FSTDBYCTL_STDBYDIS(x)               (((uint8_t)(((uint8_t)(x)) << FTFE_FSTDBYCTL_STDBYDIS_SHIFT)) & FTFE_FSTDBYCTL_STDBYDIS_MASK)
+/*! @} */
+
+/*! @name FSTDBY - Flash Standby Register */
+/*! @{ */
+#define FTFE_FSTDBY_STDBY0_MASK                  (0x1U)
+#define FTFE_FSTDBY_STDBY0_SHIFT                 (0U)
+/*! STDBY0 - Standy Mode for Flash Block 0
+ *  0b0..Standby mode not enabled for flash block 0
+ *  0b1..If STDBYDIS is clear, standby mode is enabled for flash block 0 (when SWAP=0/1, flash block 1/0 is the inactive block)
+ */
+#define FTFE_FSTDBY_STDBY0(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_FSTDBY_STDBY0_SHIFT)) & FTFE_FSTDBY_STDBY0_MASK)
+#define FTFE_FSTDBY_STDBY1_MASK                  (0x2U)
+#define FTFE_FSTDBY_STDBY1_SHIFT                 (1U)
+/*! STDBY1 - Standy Mode for Flash Block 1
+ *  0b0..Standby mode not enabled for flash block 1
+ *  0b1..If STDBYDIS is clear, standby mode is enabled for flash block 1 (when SWAP=0/1, flash block 1/0 is the inactive block)
+ */
+#define FTFE_FSTDBY_STDBY1(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_FSTDBY_STDBY1_SHIFT)) & FTFE_FSTDBY_STDBY1_MASK)
+#define FTFE_FSTDBY_STDBY2_MASK                  (0x4U)
+#define FTFE_FSTDBY_STDBY2_SHIFT                 (2U)
+/*! STDBY2 - Standy Mode for Flash Block 2
+ *  0b0..Standby mode not enabled for flash block 2
+ *  0b1..If STDBYDIS is clear, standby mode is enabled for flash block 2
+ */
+#define FTFE_FSTDBY_STDBY2(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_FSTDBY_STDBY2_SHIFT)) & FTFE_FSTDBY_STDBY2_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Masks */
+
+
+/* FTFE - Peripheral instance base addresses */
+/** Peripheral FTFE base address */
+#define FTFE_BASE                                (0x40023000u)
+/** Peripheral FTFE base pointer */
+#define FTFE                                     ((FTFE_Type *)FTFE_BASE)
+/** Array initializer of FTFE peripheral base addresses */
+#define FTFE_BASE_ADDRS                          { FTFE_BASE }
+/** Array initializer of FTFE peripheral base pointers */
+#define FTFE_BASE_PTRS                           { FTFE }
+/** Interrupt vectors for the FTFE peripheral type */
+#define FTFE_COMMAND_COMPLETE_IRQS               { FTFE_Command_Complete_IRQn }
+#define FTFE_READ_COLLISION_IRQS                 { FTFE_Read_Collision_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FTFE_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GENFSK Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GENFSK_Peripheral_Access_Layer GENFSK Peripheral Access Layer
+ * @{
+ */
+
+/** GENFSK - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t IRQ_CTRL;                          /**< IRQ CONTROL, offset: 0x0 */
+  __IO uint32_t EVENT_TMR;                         /**< EVENT TIMER, offset: 0x4 */
+  __IO uint32_t T1_CMP;                            /**< T1 COMPARE, offset: 0x8 */
+  __IO uint32_t T2_CMP;                            /**< T2 COMPARE, offset: 0xC */
+  __I  uint32_t TIMESTAMP;                         /**< TIMESTAMP, offset: 0x10 */
+  __IO uint32_t XCVR_CTRL;                         /**< TRANSCEIVER CONTROL, offset: 0x14 */
+  __I  uint32_t XCVR_STS;                          /**< TRANSCEIVER STATUS, offset: 0x18 */
+  __IO uint32_t XCVR_CFG;                          /**< TRANSCEIVER CONFIGURATION, offset: 0x1C */
+  __IO uint32_t CHANNEL_NUM;                       /**< CHANNEL NUMBER, offset: 0x20 */
+  __IO uint32_t TX_POWER;                          /**< TRANSMIT POWER, offset: 0x24 */
+  __IO uint32_t NTW_ADR_CTRL;                      /**< NETWORK ADDRESS CONTROL, offset: 0x28 */
+  __IO uint32_t NTW_ADR_0;                         /**< NETWORK ADDRESS 0, offset: 0x2C */
+  __IO uint32_t NTW_ADR_1;                         /**< NETWORK ADDRESS 1, offset: 0x30 */
+  __IO uint32_t NTW_ADR_2;                         /**< NETWORK ADDRESS 2, offset: 0x34 */
+  __IO uint32_t NTW_ADR_3;                         /**< NETWORK ADDRESS 3, offset: 0x38 */
+  __IO uint32_t RX_WATERMARK;                      /**< RECEIVE WATERMARK, offset: 0x3C */
+  __IO uint32_t DSM_CTRL;                          /**< DSM CONTROL, offset: 0x40 */
+  __I  uint32_t PART_ID;                           /**< PART ID, offset: 0x44 */
+       uint8_t RESERVED_0[24];
+  __IO uint32_t PACKET_CFG;                        /**< PACKET CONFIGURATION, offset: 0x60 */
+  __IO uint32_t H0_CFG;                            /**< H0 CONFIGURATION, offset: 0x64 */
+  __IO uint32_t H1_CFG;                            /**< H1 CONFIGURATION, offset: 0x68 */
+  __IO uint32_t CRC_CFG;                           /**< CRC CONFIGURATION, offset: 0x6C */
+  __IO uint32_t CRC_INIT;                          /**< CRC INITIALIZATION, offset: 0x70 */
+  __IO uint32_t CRC_POLY;                          /**< CRC POLYNOMIAL, offset: 0x74 */
+  __IO uint32_t CRC_XOR_OUT;                       /**< CRC XOR OUT, offset: 0x78 */
+  __IO uint32_t WHITEN_CFG;                        /**< WHITENER CONFIGURATION, offset: 0x7C */
+  __IO uint32_t WHITEN_POLY;                       /**< WHITENER POLYNOMIAL, offset: 0x80 */
+  __IO uint32_t WHITEN_SZ_THR;                     /**< WHITENER SIZE THRESHOLD, offset: 0x84 */
+  __IO uint32_t BITRATE;                           /**< BIT RATE, offset: 0x88 */
+  __IO uint32_t PB_PARTITION;                      /**< PACKET BUFFER PARTITION POINT, offset: 0x8C */
+       uint8_t RESERVED_1[1648];
+  __IO uint16_t PACKET_BUFFER[1088];               /**< PACKET BUFFER, array offset: 0x700, array step: 0x2 */
+} GENFSK_Type;
+
+/* ----------------------------------------------------------------------------
+   -- GENFSK Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GENFSK_Register_Masks GENFSK Register Masks
+ * @{
+ */
+
+/*! @name IRQ_CTRL - IRQ CONTROL */
+/*! @{ */
+#define GENFSK_IRQ_CTRL_SEQ_END_IRQ_MASK         (0x1U)
+#define GENFSK_IRQ_CTRL_SEQ_END_IRQ_SHIFT        (0U)
+/*! SEQ_END_IRQ - Sequence End Interrupt
+ *  0b0..Sequence End Interrupt is not asserted.
+ *  0b1..Sequence End Interrupt is asserted.
+ */
+#define GENFSK_IRQ_CTRL_SEQ_END_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_SEQ_END_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_SEQ_END_IRQ_MASK)
+#define GENFSK_IRQ_CTRL_TX_IRQ_MASK              (0x2U)
+#define GENFSK_IRQ_CTRL_TX_IRQ_SHIFT             (1U)
+/*! TX_IRQ - TX Interrupt
+ *  0b0..TX Interrupt is not asserted.
+ *  0b1..TX Interrupt is asserted.
+ */
+#define GENFSK_IRQ_CTRL_TX_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TX_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_TX_IRQ_MASK)
+#define GENFSK_IRQ_CTRL_RX_IRQ_MASK              (0x4U)
+#define GENFSK_IRQ_CTRL_RX_IRQ_SHIFT             (2U)
+/*! RX_IRQ - RX Interrupt
+ *  0b0..RX Interrupt is not asserted.
+ *  0b1..RX Interrupt is asserted.
+ */
+#define GENFSK_IRQ_CTRL_RX_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_RX_IRQ_MASK)
+#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_MASK         (0x8U)
+#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_SHIFT        (3U)
+/*! NTW_ADR_IRQ - Network Address Match Interrupt
+ *  0b0..Network Address Match Interrupt is not asserted.
+ *  0b1..Network Address Match Interrupt is asserted.
+ */
+#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_NTW_ADR_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_NTW_ADR_IRQ_MASK)
+#define GENFSK_IRQ_CTRL_T1_IRQ_MASK              (0x10U)
+#define GENFSK_IRQ_CTRL_T1_IRQ_SHIFT             (4U)
+/*! T1_IRQ - Timer1 (T1) Compare Interrupt
+ *  0b0..Timer1 (T1) Compare Interrupt is not asserted.
+ *  0b1..Timer1 (T1) Compare Interrupt is asserted.
+ */
+#define GENFSK_IRQ_CTRL_T1_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T1_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_T1_IRQ_MASK)
+#define GENFSK_IRQ_CTRL_T2_IRQ_MASK              (0x20U)
+#define GENFSK_IRQ_CTRL_T2_IRQ_SHIFT             (5U)
+/*! T2_IRQ - Timer2 (T2) Compare Interrupt
+ *  0b0..Timer2 (T2) Compare Interrupt is not asserted.
+ *  0b1..Timer2 (T2) Compare Interrupt is asserted.
+ */
+#define GENFSK_IRQ_CTRL_T2_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T2_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_T2_IRQ_MASK)
+#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_MASK      (0x40U)
+#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_SHIFT     (6U)
+/*! PLL_UNLOCK_IRQ - PLL Unlock Interrupt
+ *  0b0..PLL Unlock Interrupt is not asserted.
+ *  0b1..PLL Unlock Interrupt is asserted.
+ */
+#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_MASK)
+#define GENFSK_IRQ_CTRL_WAKE_IRQ_MASK            (0x80U)
+#define GENFSK_IRQ_CTRL_WAKE_IRQ_SHIFT           (7U)
+/*! WAKE_IRQ - Wake Interrrupt
+ *  0b0..Wake Interrupt is not asserted.
+ *  0b1..Wake Interrupt is asserted.
+ */
+#define GENFSK_IRQ_CTRL_WAKE_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_WAKE_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_WAKE_IRQ_MASK)
+#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_MASK    (0x100U)
+#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_SHIFT   (8U)
+/*! RX_WATERMARK_IRQ - RX Watermark Interrupt
+ *  0b0..RX Watermark Interrupt is not asserted.
+ *  0b1..RX Watermark Interrupt is asserted.
+ */
+#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_MASK)
+#define GENFSK_IRQ_CTRL_TSM_IRQ_MASK             (0x200U)
+#define GENFSK_IRQ_CTRL_TSM_IRQ_SHIFT            (9U)
+/*! TSM_IRQ - TSM Interrupt
+ *  0b0..TSM0_IRQ and TSM1_IRQ are both clear.
+ *  0b1..Indicates TSM0_IRQ or TSM1_IRQ is set in XCVR_STATUS.
+ */
+#define GENFSK_IRQ_CTRL_TSM_IRQ(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TSM_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_TSM_IRQ_MASK)
+#define GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_MASK      (0x10000U)
+#define GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_SHIFT     (16U)
+/*! SEQ_END_IRQ_EN - SEQ_END_IRQ Enable
+ *  0b0..Sequence End Interrupt is not enabled.
+ *  0b1..Sequence End Interrupt is enabled.
+ */
+#define GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_MASK)
+#define GENFSK_IRQ_CTRL_TX_IRQ_EN_MASK           (0x20000U)
+#define GENFSK_IRQ_CTRL_TX_IRQ_EN_SHIFT          (17U)
+/*! TX_IRQ_EN - TX_IRQ Enable
+ *  0b0..TX Interrupt is not enabled.
+ *  0b1..TX Interrupt is enabled.
+ */
+#define GENFSK_IRQ_CTRL_TX_IRQ_EN(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TX_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_TX_IRQ_EN_MASK)
+#define GENFSK_IRQ_CTRL_RX_IRQ_EN_MASK           (0x40000U)
+#define GENFSK_IRQ_CTRL_RX_IRQ_EN_SHIFT          (18U)
+/*! RX_IRQ_EN - RX_IRQ Enable
+ *  0b0..RX Interrupt is not enabled.
+ *  0b1..RX Interrupt is enabled.
+ */
+#define GENFSK_IRQ_CTRL_RX_IRQ_EN(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_RX_IRQ_EN_MASK)
+#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_MASK      (0x80000U)
+#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_SHIFT     (19U)
+/*! NTW_ADR_IRQ_EN - NTW_ADR_IRQ Enable
+ *  0b0..Network Address Match Interrupt is not enabled.
+ *  0b1..Network Address Match Interrupt is enabled.
+ */
+#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_MASK)
+#define GENFSK_IRQ_CTRL_T1_IRQ_EN_MASK           (0x100000U)
+#define GENFSK_IRQ_CTRL_T1_IRQ_EN_SHIFT          (20U)
+/*! T1_IRQ_EN - T1_IRQ Enable
+ *  0b0..Timer1 (T1) Compare Interrupt is not enabled.
+ *  0b1..Timer1 (T1) Compare Interrupt is enabled.
+ */
+#define GENFSK_IRQ_CTRL_T1_IRQ_EN(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T1_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_T1_IRQ_EN_MASK)
+#define GENFSK_IRQ_CTRL_T2_IRQ_EN_MASK           (0x200000U)
+#define GENFSK_IRQ_CTRL_T2_IRQ_EN_SHIFT          (21U)
+/*! T2_IRQ_EN - T2_IRQ Enable
+ *  0b0..Timer1 (T2) Compare Interrupt is not enabled.
+ *  0b1..Timer1 (T2) Compare Interrupt is enabled.
+ */
+#define GENFSK_IRQ_CTRL_T2_IRQ_EN(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T2_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_T2_IRQ_EN_MASK)
+#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_MASK   (0x400000U)
+#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_SHIFT  (22U)
+/*! PLL_UNLOCK_IRQ_EN - PLL_UNLOCK_IRQ Enable
+ *  0b0..PLL Unlock Interrupt is not enabled.
+ *  0b1..PLL Unlock Interrupt is enabled.
+ */
+#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_MASK)
+#define GENFSK_IRQ_CTRL_WAKE_IRQ_EN_MASK         (0x800000U)
+#define GENFSK_IRQ_CTRL_WAKE_IRQ_EN_SHIFT        (23U)
+/*! WAKE_IRQ_EN - WAKE_IRQ Enable
+ *  0b0..Wake Interrupt is not enabled.
+ *  0b1..Wake Interrupt is enabled.
+ */
+#define GENFSK_IRQ_CTRL_WAKE_IRQ_EN(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_WAKE_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_WAKE_IRQ_EN_MASK)
+#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_MASK (0x1000000U)
+#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_SHIFT (24U)
+/*! RX_WATERMARK_IRQ_EN - RX_WATERMARK_IRQ Enable
+ *  0b0..RX Watermark Interrupt is not enabled.
+ *  0b1..RX Watermark Interrupt is enabled.
+ */
+#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_MASK)
+#define GENFSK_IRQ_CTRL_TSM_IRQ_EN_MASK          (0x2000000U)
+#define GENFSK_IRQ_CTRL_TSM_IRQ_EN_SHIFT         (25U)
+/*! TSM_IRQ_EN - TSM_IRQ Enable
+ *  0b0..TSM Interrupt is not enabled.
+ *  0b1..TSM Interrupt is enabled.
+ */
+#define GENFSK_IRQ_CTRL_TSM_IRQ_EN(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TSM_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_TSM_IRQ_EN_MASK)
+#define GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_MASK  (0x4000000U)
+#define GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_SHIFT (26U)
+/*! GENERIC_FSK_IRQ_EN - GENERIC_FSK_IRQ Master Enable
+ *  0b0..All GENERIC_FSK Interrupts are disabled.
+ *  0b1..All GENERIC_FSK Interrupts can be enabled.
+ */
+#define GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_MASK)
+#define GENFSK_IRQ_CTRL_CRC_IGNORE_MASK          (0x8000000U)
+#define GENFSK_IRQ_CTRL_CRC_IGNORE_SHIFT         (27U)
+/*! CRC_IGNORE - CRC Ignore
+ *  0b0..RX_IRQ will not be asserted for a received packet which fails CRC verification.
+ *  0b1..RX_IRQ will be asserted even for a received packet which fails CRC verification.
+ */
+#define GENFSK_IRQ_CTRL_CRC_IGNORE(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_CRC_IGNORE_SHIFT)) & GENFSK_IRQ_CTRL_CRC_IGNORE_MASK)
+#define GENFSK_IRQ_CTRL_CRC_VALID_MASK           (0x80000000U)
+#define GENFSK_IRQ_CTRL_CRC_VALID_SHIFT          (31U)
+/*! CRC_VALID - CRC Valid
+ *  0b0..CRC of RX packet is not valid.
+ *  0b1..CRC of RX packet is valid.
+ */
+#define GENFSK_IRQ_CTRL_CRC_VALID(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_CRC_VALID_SHIFT)) & GENFSK_IRQ_CTRL_CRC_VALID_MASK)
+/*! @} */
+
+/*! @name EVENT_TMR - EVENT TIMER */
+/*! @{ */
+#define GENFSK_EVENT_TMR_EVENT_TMR_MASK          (0xFFFFFFU)
+#define GENFSK_EVENT_TMR_EVENT_TMR_SHIFT         (0U)
+#define GENFSK_EVENT_TMR_EVENT_TMR(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_EVENT_TMR_EVENT_TMR_SHIFT)) & GENFSK_EVENT_TMR_EVENT_TMR_MASK)
+#define GENFSK_EVENT_TMR_EVENT_TMR_LD_MASK       (0x1000000U)
+#define GENFSK_EVENT_TMR_EVENT_TMR_LD_SHIFT      (24U)
+#define GENFSK_EVENT_TMR_EVENT_TMR_LD(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_EVENT_TMR_EVENT_TMR_LD_SHIFT)) & GENFSK_EVENT_TMR_EVENT_TMR_LD_MASK)
+#define GENFSK_EVENT_TMR_EVENT_TMR_ADD_MASK      (0x2000000U)
+#define GENFSK_EVENT_TMR_EVENT_TMR_ADD_SHIFT     (25U)
+#define GENFSK_EVENT_TMR_EVENT_TMR_ADD(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_EVENT_TMR_EVENT_TMR_ADD_SHIFT)) & GENFSK_EVENT_TMR_EVENT_TMR_ADD_MASK)
+/*! @} */
+
+/*! @name T1_CMP - T1 COMPARE */
+/*! @{ */
+#define GENFSK_T1_CMP_T1_CMP_MASK                (0xFFFFFFU)
+#define GENFSK_T1_CMP_T1_CMP_SHIFT               (0U)
+#define GENFSK_T1_CMP_T1_CMP(x)                  (((uint32_t)(((uint32_t)(x)) << GENFSK_T1_CMP_T1_CMP_SHIFT)) & GENFSK_T1_CMP_T1_CMP_MASK)
+#define GENFSK_T1_CMP_T1_CMP_EN_MASK             (0x1000000U)
+#define GENFSK_T1_CMP_T1_CMP_EN_SHIFT            (24U)
+#define GENFSK_T1_CMP_T1_CMP_EN(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_T1_CMP_T1_CMP_EN_SHIFT)) & GENFSK_T1_CMP_T1_CMP_EN_MASK)
+/*! @} */
+
+/*! @name T2_CMP - T2 COMPARE */
+/*! @{ */
+#define GENFSK_T2_CMP_T2_CMP_MASK                (0xFFFFFFU)
+#define GENFSK_T2_CMP_T2_CMP_SHIFT               (0U)
+#define GENFSK_T2_CMP_T2_CMP(x)                  (((uint32_t)(((uint32_t)(x)) << GENFSK_T2_CMP_T2_CMP_SHIFT)) & GENFSK_T2_CMP_T2_CMP_MASK)
+#define GENFSK_T2_CMP_T2_CMP_EN_MASK             (0x1000000U)
+#define GENFSK_T2_CMP_T2_CMP_EN_SHIFT            (24U)
+#define GENFSK_T2_CMP_T2_CMP_EN(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_T2_CMP_T2_CMP_EN_SHIFT)) & GENFSK_T2_CMP_T2_CMP_EN_MASK)
+/*! @} */
+
+/*! @name TIMESTAMP - TIMESTAMP */
+/*! @{ */
+#define GENFSK_TIMESTAMP_TIMESTAMP_MASK          (0xFFFFFFU)
+#define GENFSK_TIMESTAMP_TIMESTAMP_SHIFT         (0U)
+#define GENFSK_TIMESTAMP_TIMESTAMP(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_TIMESTAMP_TIMESTAMP_SHIFT)) & GENFSK_TIMESTAMP_TIMESTAMP_MASK)
+/*! @} */
+
+/*! @name XCVR_CTRL - TRANSCEIVER CONTROL */
+/*! @{ */
+#define GENFSK_XCVR_CTRL_SEQCMD_MASK             (0xFU)
+#define GENFSK_XCVR_CTRL_SEQCMD_SHIFT            (0U)
+/*! SEQCMD - Sequence Commands
+ *  0b0000..No Action
+ *  0b0001..TX Start Now
+ *  0b0010..TX Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP)
+ *  0b0011..TX Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP)
+ *  0b0100..TX Cancel -- Cancels pending TX events but do not abort a TX-in-progress
+ *  0b0101..RX Start Now
+ *  0b0110..RX Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP)
+ *  0b0111..RX Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP)
+ *  0b1000..RX Stop @ T1 Timer Compare Match (EVENT_TMR = T1_CMP)
+ *  0b1001..RX Stop @ T2 Timer Compare Match (EVENT_TMR = T2_CMP)
+ *  0b1010..RX Cancel -- Cancels pending RX events but do not abort a RX-in-progress
+ *  0b1011..Abort All - Cancels all pending events and abort any sequence-in-progress
+ *  0b1100..Reserved
+ *  0b1101..Reserved
+ *  0b1110..Reserved
+ *  0b1111..Reserved
+ */
+#define GENFSK_XCVR_CTRL_SEQCMD(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CTRL_SEQCMD_SHIFT)) & GENFSK_XCVR_CTRL_SEQCMD_MASK)
+#define GENFSK_XCVR_CTRL_LENGTH_EXT_MASK         (0x7FF00U)
+#define GENFSK_XCVR_CTRL_LENGTH_EXT_SHIFT        (8U)
+#define GENFSK_XCVR_CTRL_LENGTH_EXT(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CTRL_LENGTH_EXT_SHIFT)) & GENFSK_XCVR_CTRL_LENGTH_EXT_MASK)
+#define GENFSK_XCVR_CTRL_CMDDEC_CS_MASK          (0x7000000U)
+#define GENFSK_XCVR_CTRL_CMDDEC_CS_SHIFT         (24U)
+#define GENFSK_XCVR_CTRL_CMDDEC_CS(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CTRL_CMDDEC_CS_SHIFT)) & GENFSK_XCVR_CTRL_CMDDEC_CS_MASK)
+#define GENFSK_XCVR_CTRL_XCVR_BUSY_MASK          (0x80000000U)
+#define GENFSK_XCVR_CTRL_XCVR_BUSY_SHIFT         (31U)
+/*! XCVR_BUSY - Transceiver Busy
+ *  0b0..IDLE
+ *  0b1..BUSY
+ */
+#define GENFSK_XCVR_CTRL_XCVR_BUSY(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CTRL_XCVR_BUSY_SHIFT)) & GENFSK_XCVR_CTRL_XCVR_BUSY_MASK)
+/*! @} */
+
+/*! @name XCVR_STS - TRANSCEIVER STATUS */
+/*! @{ */
+#define GENFSK_XCVR_STS_TX_START_T1_PEND_MASK    (0x1U)
+#define GENFSK_XCVR_STS_TX_START_T1_PEND_SHIFT   (0U)
+#define GENFSK_XCVR_STS_TX_START_T1_PEND(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_START_T1_PEND_SHIFT)) & GENFSK_XCVR_STS_TX_START_T1_PEND_MASK)
+#define GENFSK_XCVR_STS_TX_START_T2_PEND_MASK    (0x2U)
+#define GENFSK_XCVR_STS_TX_START_T2_PEND_SHIFT   (1U)
+#define GENFSK_XCVR_STS_TX_START_T2_PEND(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_START_T2_PEND_SHIFT)) & GENFSK_XCVR_STS_TX_START_T2_PEND_MASK)
+#define GENFSK_XCVR_STS_TX_IN_WARMUP_MASK        (0x4U)
+#define GENFSK_XCVR_STS_TX_IN_WARMUP_SHIFT       (2U)
+#define GENFSK_XCVR_STS_TX_IN_WARMUP(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_IN_WARMUP_SHIFT)) & GENFSK_XCVR_STS_TX_IN_WARMUP_MASK)
+#define GENFSK_XCVR_STS_TX_IN_PROGRESS_MASK      (0x8U)
+#define GENFSK_XCVR_STS_TX_IN_PROGRESS_SHIFT     (3U)
+#define GENFSK_XCVR_STS_TX_IN_PROGRESS(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_IN_PROGRESS_SHIFT)) & GENFSK_XCVR_STS_TX_IN_PROGRESS_MASK)
+#define GENFSK_XCVR_STS_TX_IN_WARMDN_MASK        (0x10U)
+#define GENFSK_XCVR_STS_TX_IN_WARMDN_SHIFT       (4U)
+#define GENFSK_XCVR_STS_TX_IN_WARMDN(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_IN_WARMDN_SHIFT)) & GENFSK_XCVR_STS_TX_IN_WARMDN_MASK)
+#define GENFSK_XCVR_STS_RX_START_T1_PEND_MASK    (0x20U)
+#define GENFSK_XCVR_STS_RX_START_T1_PEND_SHIFT   (5U)
+#define GENFSK_XCVR_STS_RX_START_T1_PEND(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_START_T1_PEND_SHIFT)) & GENFSK_XCVR_STS_RX_START_T1_PEND_MASK)
+#define GENFSK_XCVR_STS_RX_START_T2_PEND_MASK    (0x40U)
+#define GENFSK_XCVR_STS_RX_START_T2_PEND_SHIFT   (6U)
+#define GENFSK_XCVR_STS_RX_START_T2_PEND(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_START_T2_PEND_SHIFT)) & GENFSK_XCVR_STS_RX_START_T2_PEND_MASK)
+#define GENFSK_XCVR_STS_RX_STOP_T1_PEND_MASK     (0x80U)
+#define GENFSK_XCVR_STS_RX_STOP_T1_PEND_SHIFT    (7U)
+#define GENFSK_XCVR_STS_RX_STOP_T1_PEND(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_STOP_T1_PEND_SHIFT)) & GENFSK_XCVR_STS_RX_STOP_T1_PEND_MASK)
+#define GENFSK_XCVR_STS_RX_STOP_T2_PEND_MASK     (0x100U)
+#define GENFSK_XCVR_STS_RX_STOP_T2_PEND_SHIFT    (8U)
+#define GENFSK_XCVR_STS_RX_STOP_T2_PEND(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_STOP_T2_PEND_SHIFT)) & GENFSK_XCVR_STS_RX_STOP_T2_PEND_MASK)
+#define GENFSK_XCVR_STS_RX_IN_WARMUP_MASK        (0x200U)
+#define GENFSK_XCVR_STS_RX_IN_WARMUP_SHIFT       (9U)
+#define GENFSK_XCVR_STS_RX_IN_WARMUP(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_IN_WARMUP_SHIFT)) & GENFSK_XCVR_STS_RX_IN_WARMUP_MASK)
+#define GENFSK_XCVR_STS_RX_IN_SEARCH_MASK        (0x400U)
+#define GENFSK_XCVR_STS_RX_IN_SEARCH_SHIFT       (10U)
+#define GENFSK_XCVR_STS_RX_IN_SEARCH(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_IN_SEARCH_SHIFT)) & GENFSK_XCVR_STS_RX_IN_SEARCH_MASK)
+#define GENFSK_XCVR_STS_RX_IN_PROGRESS_MASK      (0x800U)
+#define GENFSK_XCVR_STS_RX_IN_PROGRESS_SHIFT     (11U)
+#define GENFSK_XCVR_STS_RX_IN_PROGRESS(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_IN_PROGRESS_SHIFT)) & GENFSK_XCVR_STS_RX_IN_PROGRESS_MASK)
+#define GENFSK_XCVR_STS_RX_IN_WARMDN_MASK        (0x1000U)
+#define GENFSK_XCVR_STS_RX_IN_WARMDN_SHIFT       (12U)
+#define GENFSK_XCVR_STS_RX_IN_WARMDN(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_IN_WARMDN_SHIFT)) & GENFSK_XCVR_STS_RX_IN_WARMDN_MASK)
+#define GENFSK_XCVR_STS_LQI_VALID_MASK           (0x4000U)
+#define GENFSK_XCVR_STS_LQI_VALID_SHIFT          (14U)
+/*! LQI_VALID - LQI Valid Indicator
+ *  0b0..LQI is not yet valid for RX packet.
+ *  0b1..LQI is valid for RX packet.
+ */
+#define GENFSK_XCVR_STS_LQI_VALID(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_LQI_VALID_SHIFT)) & GENFSK_XCVR_STS_LQI_VALID_MASK)
+#define GENFSK_XCVR_STS_CRC_VALID_MASK           (0x8000U)
+#define GENFSK_XCVR_STS_CRC_VALID_SHIFT          (15U)
+/*! CRC_VALID - CRC Valid Indicator
+ *  0b0..CRC is not valid for RX packet.
+ *  0b1..CRC is valid for RX packet.
+ */
+#define GENFSK_XCVR_STS_CRC_VALID(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_CRC_VALID_SHIFT)) & GENFSK_XCVR_STS_CRC_VALID_MASK)
+#define GENFSK_XCVR_STS_RSSI_MASK                (0xFF0000U)
+#define GENFSK_XCVR_STS_RSSI_SHIFT               (16U)
+#define GENFSK_XCVR_STS_RSSI(x)                  (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RSSI_SHIFT)) & GENFSK_XCVR_STS_RSSI_MASK)
+#define GENFSK_XCVR_STS_LQI_MASK                 (0xFF000000U)
+#define GENFSK_XCVR_STS_LQI_SHIFT                (24U)
+#define GENFSK_XCVR_STS_LQI(x)                   (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_LQI_SHIFT)) & GENFSK_XCVR_STS_LQI_MASK)
+/*! @} */
+
+/*! @name XCVR_CFG - TRANSCEIVER CONFIGURATION */
+/*! @{ */
+#define GENFSK_XCVR_CFG_TX_WHITEN_DIS_MASK       (0x1U)
+#define GENFSK_XCVR_CFG_TX_WHITEN_DIS_SHIFT      (0U)
+#define GENFSK_XCVR_CFG_TX_WHITEN_DIS(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_TX_WHITEN_DIS_SHIFT)) & GENFSK_XCVR_CFG_TX_WHITEN_DIS_MASK)
+#define GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_MASK     (0x2U)
+#define GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_SHIFT    (1U)
+#define GENFSK_XCVR_CFG_RX_DEWHITEN_DIS(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_SHIFT)) & GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_MASK)
+#define GENFSK_XCVR_CFG_SW_CRC_EN_MASK           (0x4U)
+#define GENFSK_XCVR_CFG_SW_CRC_EN_SHIFT          (2U)
+#define GENFSK_XCVR_CFG_SW_CRC_EN(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_SW_CRC_EN_SHIFT)) & GENFSK_XCVR_CFG_SW_CRC_EN_MASK)
+#define GENFSK_XCVR_CFG_STOP_POSTPONE_ON_AA_MASK (0x8U)
+#define GENFSK_XCVR_CFG_STOP_POSTPONE_ON_AA_SHIFT (3U)
+/*! STOP_POSTPONE_ON_AA - Postpone Stop Command Timeout On Access Address Match Enable
+ *  0b0..STOP Abort will occur on RX_STOP_T1 or RX_STOP_T1 Event Timer match, regardless of ntw_adr_matched
+ *  0b1..STOP Abort will be deferred on RX_STOP_T1 or RX_STOP_T1 Event Timer match, if ntw_adr_matched is asserted; otherwise the RX_STOP Abort will occur immediately
+ */
+#define GENFSK_XCVR_CFG_STOP_POSTPONE_ON_AA(x)   (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_STOP_POSTPONE_ON_AA_SHIFT)) & GENFSK_XCVR_CFG_STOP_POSTPONE_ON_AA_MASK)
+#define GENFSK_XCVR_CFG_PREAMBLE_SZ_MASK         (0x70U)
+#define GENFSK_XCVR_CFG_PREAMBLE_SZ_SHIFT        (4U)
+#define GENFSK_XCVR_CFG_PREAMBLE_SZ(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_PREAMBLE_SZ_SHIFT)) & GENFSK_XCVR_CFG_PREAMBLE_SZ_MASK)
+#define GENFSK_XCVR_CFG_TX_WARMUP_MASK           (0xFF00U)
+#define GENFSK_XCVR_CFG_TX_WARMUP_SHIFT          (8U)
+#define GENFSK_XCVR_CFG_TX_WARMUP(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_TX_WARMUP_SHIFT)) & GENFSK_XCVR_CFG_TX_WARMUP_MASK)
+#define GENFSK_XCVR_CFG_RX_WARMUP_MASK           (0xFF0000U)
+#define GENFSK_XCVR_CFG_RX_WARMUP_SHIFT          (16U)
+#define GENFSK_XCVR_CFG_RX_WARMUP(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_RX_WARMUP_SHIFT)) & GENFSK_XCVR_CFG_RX_WARMUP_MASK)
+/*! @} */
+
+/*! @name CHANNEL_NUM - CHANNEL NUMBER */
+/*! @{ */
+#define GENFSK_CHANNEL_NUM_CHANNEL_NUM_MASK      (0x7FU)
+#define GENFSK_CHANNEL_NUM_CHANNEL_NUM_SHIFT     (0U)
+#define GENFSK_CHANNEL_NUM_CHANNEL_NUM(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_CHANNEL_NUM_CHANNEL_NUM_SHIFT)) & GENFSK_CHANNEL_NUM_CHANNEL_NUM_MASK)
+/*! @} */
+
+/*! @name TX_POWER - TRANSMIT POWER */
+/*! @{ */
+#define GENFSK_TX_POWER_TX_POWER_MASK            (0x3FU)
+#define GENFSK_TX_POWER_TX_POWER_SHIFT           (0U)
+#define GENFSK_TX_POWER_TX_POWER(x)              (((uint32_t)(((uint32_t)(x)) << GENFSK_TX_POWER_TX_POWER_SHIFT)) & GENFSK_TX_POWER_TX_POWER_MASK)
+/*! @} */
+
+/*! @name NTW_ADR_CTRL - NETWORK ADDRESS CONTROL */
+/*! @{ */
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_MASK      (0xFU)
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_SHIFT     (0U)
+/*! NTW_ADR_EN - Network Address Enable
+ *  0b0001..Enable Network Address 0 for correlation
+ *  0b0010..Enable Network Address 1 for correlation
+ *  0b0100..Enable Network Address 2 for correlation
+ *  0b1000..Enable Network Address 3 for correlation
+ */
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR_EN(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_MASK)
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_MASK     (0xF0U)
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_SHIFT    (4U)
+/*! NTW_ADR_MCH - Network Address Match
+ *  0b0001..Network Address 0 has matched
+ *  0b0010..Network Address 1 has matched
+ *  0b0100..Network Address 2 has matched
+ *  0b1000..Network Address 3 has matched
+ */
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_MASK)
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ_MASK     (0x300U)
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ_SHIFT    (8U)
+/*! NTW_ADR0_SZ - Network Address 0 Size
+ *  0b00..Network Address 0 requires a 8-bit correlation
+ *  0b01..Network Address 0 requires a 16-bit correlation
+ *  0b10..Network Address 0 requires a 24-bit correlation
+ *  0b11..Network Address 0 requires a 32-bit correlation
+ */
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ_MASK)
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ_MASK     (0xC00U)
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ_SHIFT    (10U)
+/*! NTW_ADR1_SZ - Network Address 1 Size
+ *  0b00..Network Address 1 requires a 8-bit correlation
+ *  0b01..Network Address 1 requires a 16-bit correlation
+ *  0b10..Network Address 1 requires a 24-bit correlation
+ *  0b11..Network Address 1 requires a 32-bit correlation
+ */
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ_MASK)
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ_MASK     (0x3000U)
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ_SHIFT    (12U)
+/*! NTW_ADR2_SZ - Network Address 2 Size
+ *  0b00..Network Address 2 requires a 8-bit correlation
+ *  0b01..Network Address 2 requires a 16-bit correlation
+ *  0b10..Network Address 2 requires a 24-bit correlation
+ *  0b11..Network Address 2 requires a 32-bit correlation
+ */
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ_MASK)
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ_MASK     (0xC000U)
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ_SHIFT    (14U)
+/*! NTW_ADR3_SZ - Network Address 3 Size
+ *  0b00..Network Address 3 requires a 8-bit correlation
+ *  0b01..Network Address 3 requires a 16-bit correlation
+ *  0b10..Network Address 3 requires a 24-bit correlation
+ *  0b11..Network Address 3 requires a 32-bit correlation
+ */
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ_MASK)
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0_MASK    (0x70000U)
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0_SHIFT   (16U)
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0_MASK)
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1_MASK    (0x700000U)
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1_SHIFT   (20U)
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1_MASK)
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2_MASK    (0x7000000U)
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2_SHIFT   (24U)
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2_MASK)
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3_MASK    (0x70000000U)
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3_SHIFT   (28U)
+#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3_MASK)
+/*! @} */
+
+/*! @name NTW_ADR_0 - NETWORK ADDRESS 0 */
+/*! @{ */
+#define GENFSK_NTW_ADR_0_NTW_ADR_0_MASK          (0xFFFFFFFFU)
+#define GENFSK_NTW_ADR_0_NTW_ADR_0_SHIFT         (0U)
+#define GENFSK_NTW_ADR_0_NTW_ADR_0(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_0_NTW_ADR_0_SHIFT)) & GENFSK_NTW_ADR_0_NTW_ADR_0_MASK)
+/*! @} */
+
+/*! @name NTW_ADR_1 - NETWORK ADDRESS 1 */
+/*! @{ */
+#define GENFSK_NTW_ADR_1_NTW_ADR_1_MASK          (0xFFFFFFFFU)
+#define GENFSK_NTW_ADR_1_NTW_ADR_1_SHIFT         (0U)
+#define GENFSK_NTW_ADR_1_NTW_ADR_1(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_1_NTW_ADR_1_SHIFT)) & GENFSK_NTW_ADR_1_NTW_ADR_1_MASK)
+/*! @} */
+
+/*! @name NTW_ADR_2 - NETWORK ADDRESS 2 */
+/*! @{ */
+#define GENFSK_NTW_ADR_2_NTW_ADR_2_MASK          (0xFFFFFFFFU)
+#define GENFSK_NTW_ADR_2_NTW_ADR_2_SHIFT         (0U)
+#define GENFSK_NTW_ADR_2_NTW_ADR_2(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_2_NTW_ADR_2_SHIFT)) & GENFSK_NTW_ADR_2_NTW_ADR_2_MASK)
+/*! @} */
+
+/*! @name NTW_ADR_3 - NETWORK ADDRESS 3 */
+/*! @{ */
+#define GENFSK_NTW_ADR_3_NTW_ADR_3_MASK          (0xFFFFFFFFU)
+#define GENFSK_NTW_ADR_3_NTW_ADR_3_SHIFT         (0U)
+#define GENFSK_NTW_ADR_3_NTW_ADR_3(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_3_NTW_ADR_3_SHIFT)) & GENFSK_NTW_ADR_3_NTW_ADR_3_MASK)
+/*! @} */
+
+/*! @name RX_WATERMARK - RECEIVE WATERMARK */
+/*! @{ */
+#define GENFSK_RX_WATERMARK_RX_WATERMARK_MASK    (0x1FFFU)
+#define GENFSK_RX_WATERMARK_RX_WATERMARK_SHIFT   (0U)
+#define GENFSK_RX_WATERMARK_RX_WATERMARK(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_WATERMARK_RX_WATERMARK_SHIFT)) & GENFSK_RX_WATERMARK_RX_WATERMARK_MASK)
+#define GENFSK_RX_WATERMARK_BYTE_COUNTER_MASK    (0x1FFF0000U)
+#define GENFSK_RX_WATERMARK_BYTE_COUNTER_SHIFT   (16U)
+#define GENFSK_RX_WATERMARK_BYTE_COUNTER(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_WATERMARK_BYTE_COUNTER_SHIFT)) & GENFSK_RX_WATERMARK_BYTE_COUNTER_MASK)
+/*! @} */
+
+/*! @name DSM_CTRL - DSM CONTROL */
+/*! @{ */
+#define GENFSK_DSM_CTRL_GEN_SLEEP_REQUEST_MASK   (0x1U)
+#define GENFSK_DSM_CTRL_GEN_SLEEP_REQUEST_SHIFT  (0U)
+#define GENFSK_DSM_CTRL_GEN_SLEEP_REQUEST(x)     (((uint32_t)(((uint32_t)(x)) << GENFSK_DSM_CTRL_GEN_SLEEP_REQUEST_SHIFT)) & GENFSK_DSM_CTRL_GEN_SLEEP_REQUEST_MASK)
+/*! @} */
+
+/*! @name PART_ID - PART ID */
+/*! @{ */
+#define GENFSK_PART_ID_PART_ID_MASK              (0xFFU)
+#define GENFSK_PART_ID_PART_ID_SHIFT             (0U)
+#define GENFSK_PART_ID_PART_ID(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_PART_ID_PART_ID_SHIFT)) & GENFSK_PART_ID_PART_ID_MASK)
+/*! @} */
+
+/*! @name PACKET_CFG - PACKET CONFIGURATION */
+/*! @{ */
+#define GENFSK_PACKET_CFG_LENGTH_SZ_MASK         (0x1FU)
+#define GENFSK_PACKET_CFG_LENGTH_SZ_SHIFT        (0U)
+#define GENFSK_PACKET_CFG_LENGTH_SZ(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_SZ_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_SZ_MASK)
+#define GENFSK_PACKET_CFG_LENGTH_BIT_ORD_MASK    (0x20U)
+#define GENFSK_PACKET_CFG_LENGTH_BIT_ORD_SHIFT   (5U)
+/*! LENGTH_BIT_ORD - LENGTH Bit Order
+ *  0b0..LS Bit First
+ *  0b1..MS Bit First
+ */
+#define GENFSK_PACKET_CFG_LENGTH_BIT_ORD(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_BIT_ORD_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_BIT_ORD_MASK)
+#define GENFSK_PACKET_CFG_SYNC_ADDR_SZ_MASK      (0xC0U)
+#define GENFSK_PACKET_CFG_SYNC_ADDR_SZ_SHIFT     (6U)
+#define GENFSK_PACKET_CFG_SYNC_ADDR_SZ(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_SYNC_ADDR_SZ_SHIFT)) & GENFSK_PACKET_CFG_SYNC_ADDR_SZ_MASK)
+#define GENFSK_PACKET_CFG_LENGTH_ADJ_MASK        (0xFF00U)
+#define GENFSK_PACKET_CFG_LENGTH_ADJ_SHIFT       (8U)
+#define GENFSK_PACKET_CFG_LENGTH_ADJ(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_ADJ_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_ADJ_MASK)
+#define GENFSK_PACKET_CFG_H0_SZ_MASK             (0x1F0000U)
+#define GENFSK_PACKET_CFG_H0_SZ_SHIFT            (16U)
+#define GENFSK_PACKET_CFG_H0_SZ(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H0_SZ_SHIFT)) & GENFSK_PACKET_CFG_H0_SZ_MASK)
+#define GENFSK_PACKET_CFG_LENGTH_ADJ_UNSIGNED_MASK (0x200000U)
+#define GENFSK_PACKET_CFG_LENGTH_ADJ_UNSIGNED_SHIFT (21U)
+/*! LENGTH_ADJ_UNSIGNED - Length Adjustment Unsigned Enabled
+ *  0b0..Hardware interprets LENGTH_ADJ as a signed integer (default)
+ *  0b1..Hardware interprets LENGTH_ADJ as a unsigned integer
+ */
+#define GENFSK_PACKET_CFG_LENGTH_ADJ_UNSIGNED(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_ADJ_UNSIGNED_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_ADJ_UNSIGNED_MASK)
+#define GENFSK_PACKET_CFG_H1_SZ_MASK             (0x1F000000U)
+#define GENFSK_PACKET_CFG_H1_SZ_SHIFT            (24U)
+#define GENFSK_PACKET_CFG_H1_SZ(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H1_SZ_SHIFT)) & GENFSK_PACKET_CFG_H1_SZ_MASK)
+#define GENFSK_PACKET_CFG_H1_FAIL_MASK           (0x20000000U)
+#define GENFSK_PACKET_CFG_H1_FAIL_SHIFT          (29U)
+#define GENFSK_PACKET_CFG_H1_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H1_FAIL_SHIFT)) & GENFSK_PACKET_CFG_H1_FAIL_MASK)
+#define GENFSK_PACKET_CFG_H0_FAIL_MASK           (0x40000000U)
+#define GENFSK_PACKET_CFG_H0_FAIL_SHIFT          (30U)
+#define GENFSK_PACKET_CFG_H0_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H0_FAIL_SHIFT)) & GENFSK_PACKET_CFG_H0_FAIL_MASK)
+#define GENFSK_PACKET_CFG_LENGTH_FAIL_MASK       (0x80000000U)
+#define GENFSK_PACKET_CFG_LENGTH_FAIL_SHIFT      (31U)
+#define GENFSK_PACKET_CFG_LENGTH_FAIL(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_FAIL_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_FAIL_MASK)
+/*! @} */
+
+/*! @name H0_CFG - H0 CONFIGURATION */
+/*! @{ */
+#define GENFSK_H0_CFG_H0_MATCH_MASK              (0xFFFFU)
+#define GENFSK_H0_CFG_H0_MATCH_SHIFT             (0U)
+#define GENFSK_H0_CFG_H0_MATCH(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_H0_CFG_H0_MATCH_SHIFT)) & GENFSK_H0_CFG_H0_MATCH_MASK)
+#define GENFSK_H0_CFG_H0_MASK_MASK               (0xFFFF0000U)
+#define GENFSK_H0_CFG_H0_MASK_SHIFT              (16U)
+#define GENFSK_H0_CFG_H0_MASK(x)                 (((uint32_t)(((uint32_t)(x)) << GENFSK_H0_CFG_H0_MASK_SHIFT)) & GENFSK_H0_CFG_H0_MASK_MASK)
+/*! @} */
+
+/*! @name H1_CFG - H1 CONFIGURATION */
+/*! @{ */
+#define GENFSK_H1_CFG_H1_MATCH_MASK              (0xFFFFU)
+#define GENFSK_H1_CFG_H1_MATCH_SHIFT             (0U)
+#define GENFSK_H1_CFG_H1_MATCH(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_H1_CFG_H1_MATCH_SHIFT)) & GENFSK_H1_CFG_H1_MATCH_MASK)
+#define GENFSK_H1_CFG_H1_MASK_MASK               (0xFFFF0000U)
+#define GENFSK_H1_CFG_H1_MASK_SHIFT              (16U)
+#define GENFSK_H1_CFG_H1_MASK(x)                 (((uint32_t)(((uint32_t)(x)) << GENFSK_H1_CFG_H1_MASK_SHIFT)) & GENFSK_H1_CFG_H1_MASK_MASK)
+/*! @} */
+
+/*! @name CRC_CFG - CRC CONFIGURATION */
+/*! @{ */
+#define GENFSK_CRC_CFG_CRC_SZ_MASK               (0x7U)
+#define GENFSK_CRC_CFG_CRC_SZ_SHIFT              (0U)
+#define GENFSK_CRC_CFG_CRC_SZ(x)                 (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_SZ_SHIFT)) & GENFSK_CRC_CFG_CRC_SZ_MASK)
+#define GENFSK_CRC_CFG_CRC_START_BYTE_MASK       (0xF00U)
+#define GENFSK_CRC_CFG_CRC_START_BYTE_SHIFT      (8U)
+#define GENFSK_CRC_CFG_CRC_START_BYTE(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_START_BYTE_SHIFT)) & GENFSK_CRC_CFG_CRC_START_BYTE_MASK)
+#define GENFSK_CRC_CFG_CRC_REF_IN_MASK           (0x10000U)
+#define GENFSK_CRC_CFG_CRC_REF_IN_SHIFT          (16U)
+/*! CRC_REF_IN - CRC Reflect In
+ *  0b0..do not manipulate input data stream
+ *  0b1..reflect each byte in the input stream bitwise
+ */
+#define GENFSK_CRC_CFG_CRC_REF_IN(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_REF_IN_SHIFT)) & GENFSK_CRC_CFG_CRC_REF_IN_MASK)
+#define GENFSK_CRC_CFG_CRC_REF_OUT_MASK          (0x20000U)
+#define GENFSK_CRC_CFG_CRC_REF_OUT_SHIFT         (17U)
+/*! CRC_REF_OUT - CRC Reflect Out
+ *  0b0..do not manipulate CRC result
+ *  0b1..CRC result is to be reflected bitwise (operated on entire word)
+ */
+#define GENFSK_CRC_CFG_CRC_REF_OUT(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_REF_OUT_SHIFT)) & GENFSK_CRC_CFG_CRC_REF_OUT_MASK)
+#define GENFSK_CRC_CFG_CRC_BYTE_ORD_MASK         (0x40000U)
+#define GENFSK_CRC_CFG_CRC_BYTE_ORD_SHIFT        (18U)
+/*! CRC_BYTE_ORD - CRC Byte Order
+ *  0b0..LS Byte First
+ *  0b1..MS Byte First
+ */
+#define GENFSK_CRC_CFG_CRC_BYTE_ORD(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_BYTE_ORD_SHIFT)) & GENFSK_CRC_CFG_CRC_BYTE_ORD_MASK)
+/*! @} */
+
+/*! @name CRC_INIT - CRC INITIALIZATION */
+/*! @{ */
+#define GENFSK_CRC_INIT_CRC_SEED_MASK            (0xFFFFFFFFU)
+#define GENFSK_CRC_INIT_CRC_SEED_SHIFT           (0U)
+#define GENFSK_CRC_INIT_CRC_SEED(x)              (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_INIT_CRC_SEED_SHIFT)) & GENFSK_CRC_INIT_CRC_SEED_MASK)
+/*! @} */
+
+/*! @name CRC_POLY - CRC POLYNOMIAL */
+/*! @{ */
+#define GENFSK_CRC_POLY_CRC_POLY_MASK            (0xFFFFFFFFU)
+#define GENFSK_CRC_POLY_CRC_POLY_SHIFT           (0U)
+#define GENFSK_CRC_POLY_CRC_POLY(x)              (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_POLY_CRC_POLY_SHIFT)) & GENFSK_CRC_POLY_CRC_POLY_MASK)
+/*! @} */
+
+/*! @name CRC_XOR_OUT - CRC XOR OUT */
+/*! @{ */
+#define GENFSK_CRC_XOR_OUT_CRC_XOR_OUT_MASK      (0xFFFFFFFFU)
+#define GENFSK_CRC_XOR_OUT_CRC_XOR_OUT_SHIFT     (0U)
+#define GENFSK_CRC_XOR_OUT_CRC_XOR_OUT(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_XOR_OUT_CRC_XOR_OUT_SHIFT)) & GENFSK_CRC_XOR_OUT_CRC_XOR_OUT_MASK)
+/*! @} */
+
+/*! @name WHITEN_CFG - WHITENER CONFIGURATION */
+/*! @{ */
+#define GENFSK_WHITEN_CFG_WHITEN_START_MASK      (0x3U)
+#define GENFSK_WHITEN_CFG_WHITEN_START_SHIFT     (0U)
+/*! WHITEN_START - Configure Whitener Start Point
+ *  0b00..no whitening
+ *  0b01..start whitening at start-of-H0
+ *  0b10..start whitening at start-of-H1 but only if LENGTH > WHITEN_SZ_THR
+ *  0b11..start whitening at start-of-payload but only if LENGTH > WHITEN_SZ_THR
+ */
+#define GENFSK_WHITEN_CFG_WHITEN_START(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_START_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_START_MASK)
+#define GENFSK_WHITEN_CFG_WHITEN_END_MASK        (0x4U)
+#define GENFSK_WHITEN_CFG_WHITEN_END_SHIFT       (2U)
+/*! WHITEN_END - Configure end-of-whitening
+ *  0b0..end whiten at end-of-payload
+ *  0b1..end whiten at end-of-crc
+ */
+#define GENFSK_WHITEN_CFG_WHITEN_END(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_END_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_END_MASK)
+#define GENFSK_WHITEN_CFG_WHITEN_B4_CRC_MASK     (0x8U)
+#define GENFSK_WHITEN_CFG_WHITEN_B4_CRC_SHIFT    (3U)
+/*! WHITEN_B4_CRC - Congifure for Whitening-before-CRC
+ *  0b0..CRC before whiten/de-whiten
+ *  0b1..Whiten/de-whiten before CRC
+ */
+#define GENFSK_WHITEN_CFG_WHITEN_B4_CRC(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_B4_CRC_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_B4_CRC_MASK)
+#define GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE_MASK  (0x10U)
+#define GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE_SHIFT (4U)
+#define GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE_MASK)
+#define GENFSK_WHITEN_CFG_WHITEN_REF_IN_MASK     (0x20U)
+#define GENFSK_WHITEN_CFG_WHITEN_REF_IN_SHIFT    (5U)
+#define GENFSK_WHITEN_CFG_WHITEN_REF_IN(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_REF_IN_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_REF_IN_MASK)
+#define GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_MASK (0x40U)
+#define GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_SHIFT (6U)
+/*! WHITEN_PAYLOAD_REINIT - Configure for Whitener re-initialization
+ *  0b0..Don't re-initialize Whitener LFSR at start-of-payload
+ *  0b1..Re-initialize Whitener LFSR at start-of-payload
+ */
+#define GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_MASK)
+#define GENFSK_WHITEN_CFG_WHITEN_SIZE_MASK       (0xF00U)
+#define GENFSK_WHITEN_CFG_WHITEN_SIZE_SHIFT      (8U)
+#define GENFSK_WHITEN_CFG_WHITEN_SIZE(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_SIZE_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_SIZE_MASK)
+#define GENFSK_WHITEN_CFG_MANCHESTER_EN_MASK     (0x1000U)
+#define GENFSK_WHITEN_CFG_MANCHESTER_EN_SHIFT    (12U)
+/*! MANCHESTER_EN - Configure for Manchester Encoding/Decoding
+ *  0b0..Disable Manchester encoding (TX) and decoding (RX)
+ *  0b1..Enable Manchester encoding (TX) and decoding (RX)
+ */
+#define GENFSK_WHITEN_CFG_MANCHESTER_EN(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_MANCHESTER_EN_SHIFT)) & GENFSK_WHITEN_CFG_MANCHESTER_EN_MASK)
+#define GENFSK_WHITEN_CFG_MANCHESTER_INV_MASK    (0x2000U)
+#define GENFSK_WHITEN_CFG_MANCHESTER_INV_SHIFT   (13U)
+/*! MANCHESTER_INV - Configure for Inverted Manchester Encoding
+ *  0b0..Manchester coding as per 802.3
+ *  0b1..Manchester coding as per 802.3 but with the encoding signal inverted
+ */
+#define GENFSK_WHITEN_CFG_MANCHESTER_INV(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_MANCHESTER_INV_SHIFT)) & GENFSK_WHITEN_CFG_MANCHESTER_INV_MASK)
+#define GENFSK_WHITEN_CFG_MANCHESTER_START_MASK  (0x4000U)
+#define GENFSK_WHITEN_CFG_MANCHESTER_START_SHIFT (14U)
+/*! MANCHESTER_START - Configure Manchester Encoding Start Point
+ *  0b0..Start Manchester coding at start-of-payload
+ *  0b1..Start Manchester coding at start-of-header
+ */
+#define GENFSK_WHITEN_CFG_MANCHESTER_START(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_MANCHESTER_START_SHIFT)) & GENFSK_WHITEN_CFG_MANCHESTER_START_MASK)
+#define GENFSK_WHITEN_CFG_WHITEN_INIT_MASK       (0x1FF0000U)
+#define GENFSK_WHITEN_CFG_WHITEN_INIT_SHIFT      (16U)
+#define GENFSK_WHITEN_CFG_WHITEN_INIT(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_INIT_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_INIT_MASK)
+/*! @} */
+
+/*! @name WHITEN_POLY - WHITENER POLYNOMIAL */
+/*! @{ */
+#define GENFSK_WHITEN_POLY_WHITEN_POLY_MASK      (0x1FFU)
+#define GENFSK_WHITEN_POLY_WHITEN_POLY_SHIFT     (0U)
+#define GENFSK_WHITEN_POLY_WHITEN_POLY(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_POLY_WHITEN_POLY_SHIFT)) & GENFSK_WHITEN_POLY_WHITEN_POLY_MASK)
+/*! @} */
+
+/*! @name WHITEN_SZ_THR - WHITENER SIZE THRESHOLD */
+/*! @{ */
+#define GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR_MASK  (0xFFFU)
+#define GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR_SHIFT (0U)
+#define GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR_SHIFT)) & GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR_MASK)
+#define GENFSK_WHITEN_SZ_THR_LENGTH_MAX_MASK     (0x7F0000U)
+#define GENFSK_WHITEN_SZ_THR_LENGTH_MAX_SHIFT    (16U)
+#define GENFSK_WHITEN_SZ_THR_LENGTH_MAX(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_SZ_THR_LENGTH_MAX_SHIFT)) & GENFSK_WHITEN_SZ_THR_LENGTH_MAX_MASK)
+#define GENFSK_WHITEN_SZ_THR_REC_BAD_PKT_MASK    (0x800000U)
+#define GENFSK_WHITEN_SZ_THR_REC_BAD_PKT_SHIFT   (23U)
+/*! REC_BAD_PKT - Receive Bad Packets
+ *  0b0..packets which fail H0, H1, or LENGTH_MAX result in an automatic recycle after the header is received and parsed
+ *  0b1..packets which fail H0, H1, or LENGTH_MAX are received in their entirety
+ */
+#define GENFSK_WHITEN_SZ_THR_REC_BAD_PKT(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_SZ_THR_REC_BAD_PKT_SHIFT)) & GENFSK_WHITEN_SZ_THR_REC_BAD_PKT_MASK)
+/*! @} */
+
+/*! @name BITRATE - BIT RATE */
+/*! @{ */
+#define GENFSK_BITRATE_BITRATE_MASK              (0x3U)
+#define GENFSK_BITRATE_BITRATE_SHIFT             (0U)
+/*! BITRATE - Bit Rate
+ *  0b00..1Mbit/sec
+ *  0b01..500Kbit/sec
+ *  0b10..250Kbit/sec (not supported if WHITEN_CFG[MANCHESTER_EN]=1)
+ *  0b11..2Mbit/sec (not supported if WHITEN_CFG[MANCHESTER_EN]=1)
+ */
+#define GENFSK_BITRATE_BITRATE(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_BITRATE_BITRATE_SHIFT)) & GENFSK_BITRATE_BITRATE_MASK)
+/*! @} */
+
+/*! @name PB_PARTITION - PACKET BUFFER PARTITION POINT */
+/*! @{ */
+#define GENFSK_PB_PARTITION_PB_PARTITION_MASK    (0x7FFU)
+#define GENFSK_PB_PARTITION_PB_PARTITION_SHIFT   (0U)
+#define GENFSK_PB_PARTITION_PB_PARTITION(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_PB_PARTITION_PB_PARTITION_SHIFT)) & GENFSK_PB_PARTITION_PB_PARTITION_MASK)
+/*! @} */
+
+/*! @name PACKET_BUFFER - PACKET BUFFER */
+/*! @{ */
+#define GENFSK_PACKET_BUFFER_PACKET_BUFFER_MASK  (0xFFFFU)
+#define GENFSK_PACKET_BUFFER_PACKET_BUFFER_SHIFT (0U)
+#define GENFSK_PACKET_BUFFER_PACKET_BUFFER(x)    (((uint16_t)(((uint16_t)(x)) << GENFSK_PACKET_BUFFER_PACKET_BUFFER_SHIFT)) & GENFSK_PACKET_BUFFER_PACKET_BUFFER_MASK)
+/*! @} */
+
+/* The count of GENFSK_PACKET_BUFFER */
+#define GENFSK_PACKET_BUFFER_COUNT               (1088U)
+
+
+/*!
+ * @}
+ */ /* end of group GENFSK_Register_Masks */
+
+
+/* GENFSK - Peripheral instance base addresses */
+/** Peripheral GENFSK base address */
+#define GENFSK_BASE                              (0x41033000u)
+/** Peripheral GENFSK base pointer */
+#define GENFSK                                   ((GENFSK_Type *)GENFSK_BASE)
+/** Array initializer of GENFSK peripheral base addresses */
+#define GENFSK_BASE_ADDRS                        { GENFSK_BASE }
+/** Array initializer of GENFSK peripheral base pointers */
+#define GENFSK_BASE_PTRS                         { GENFSK }
+
+/*!
+ * @}
+ */ /* end of group GENFSK_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/*! @name PDOR - Port Data Output Register */
+/*! @{ */
+#define GPIO_PDOR_PDO_MASK                       (0xFFFFFFFFU)
+#define GPIO_PDOR_PDO_SHIFT                      (0U)
+#define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
+/*! @} */
+
+/*! @name PSOR - Port Set Output Register */
+/*! @{ */
+#define GPIO_PSOR_PTSO_MASK                      (0xFFFFFFFFU)
+#define GPIO_PSOR_PTSO_SHIFT                     (0U)
+#define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
+/*! @} */
+
+/*! @name PCOR - Port Clear Output Register */
+/*! @{ */
+#define GPIO_PCOR_PTCO_MASK                      (0xFFFFFFFFU)
+#define GPIO_PCOR_PTCO_SHIFT                     (0U)
+#define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
+/*! @} */
+
+/*! @name PTOR - Port Toggle Output Register */
+/*! @{ */
+#define GPIO_PTOR_PTTO_MASK                      (0xFFFFFFFFU)
+#define GPIO_PTOR_PTTO_SHIFT                     (0U)
+#define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
+/*! @} */
+
+/*! @name PDIR - Port Data Input Register */
+/*! @{ */
+#define GPIO_PDIR_PDI_MASK                       (0xFFFFFFFFU)
+#define GPIO_PDIR_PDI_SHIFT                      (0U)
+#define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
+/*! @} */
+
+/*! @name PDDR - Port Data Direction Register */
+/*! @{ */
+#define GPIO_PDDR_PDD_MASK                       (0xFFFFFFFFU)
+#define GPIO_PDDR_PDD_SHIFT                      (0U)
+#define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIOA base address */
+#define GPIOA_BASE                               (0x48020000u)
+/** Peripheral GPIOA base pointer */
+#define GPIOA                                    ((GPIO_Type *)GPIOA_BASE)
+/** Peripheral GPIOB base address */
+#define GPIOB_BASE                               (0x48020040u)
+/** Peripheral GPIOB base pointer */
+#define GPIOB                                    ((GPIO_Type *)GPIOB_BASE)
+/** Peripheral GPIOC base address */
+#define GPIOC_BASE                               (0x48020080u)
+/** Peripheral GPIOC base pointer */
+#define GPIOC                                    ((GPIO_Type *)GPIOC_BASE)
+/** Peripheral GPIOD base address */
+#define GPIOD_BASE                               (0x480200C0u)
+/** Peripheral GPIOD base pointer */
+#define GPIOD                                    ((GPIO_Type *)GPIOD_BASE)
+/** Peripheral GPIOE base address */
+#define GPIOE_BASE                               (0x4100F000u)
+/** Peripheral GPIOE base pointer */
+#define GPIOE                                    ((GPIO_Type *)GPIOE_BASE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS                          { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS                           { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __IO uint32_t TCSR;                              /**< SAI Transmit Control Register, offset: 0x8 */
+  __IO uint32_t TCR1;                              /**< SAI Transmit Configuration 1 Register, offset: 0xC */
+  __IO uint32_t TCR2;                              /**< SAI Transmit Configuration 2 Register, offset: 0x10 */
+  __IO uint32_t TCR3;                              /**< SAI Transmit Configuration 3 Register, offset: 0x14 */
+  __IO uint32_t TCR4;                              /**< SAI Transmit Configuration 4 Register, offset: 0x18 */
+  __IO uint32_t TCR5;                              /**< SAI Transmit Configuration 5 Register, offset: 0x1C */
+  __O  uint32_t TDR[2];                            /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+       uint8_t RESERVED_0[24];
+  __I  uint32_t TFR[2];                            /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
+       uint8_t RESERVED_1[24];
+  __IO uint32_t TMR;                               /**< SAI Transmit Mask Register, offset: 0x60 */
+       uint8_t RESERVED_2[36];
+  __IO uint32_t RCSR;                              /**< SAI Receive Control Register, offset: 0x88 */
+  __IO uint32_t RCR1;                              /**< SAI Receive Configuration 1 Register, offset: 0x8C */
+  __IO uint32_t RCR2;                              /**< SAI Receive Configuration 2 Register, offset: 0x90 */
+  __IO uint32_t RCR3;                              /**< SAI Receive Configuration 3 Register, offset: 0x94 */
+  __IO uint32_t RCR4;                              /**< SAI Receive Configuration 4 Register, offset: 0x98 */
+  __IO uint32_t RCR5;                              /**< SAI Receive Configuration 5 Register, offset: 0x9C */
+  __I  uint32_t RDR[2];                            /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+       uint8_t RESERVED_3[24];
+  __I  uint32_t RFR[2];                            /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
+       uint8_t RESERVED_4[24];
+  __IO uint32_t RMR;                               /**< SAI Receive Mask Register, offset: 0xE0 */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2S Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define I2S_VERID_FEATURE_MASK                   (0xFFFFU)
+#define I2S_VERID_FEATURE_SHIFT                  (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000000000000..Standard feature set.
+ */
+#define I2S_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
+#define I2S_VERID_MINOR_MASK                     (0xFF0000U)
+#define I2S_VERID_MINOR_SHIFT                    (16U)
+#define I2S_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
+#define I2S_VERID_MAJOR_MASK                     (0xFF000000U)
+#define I2S_VERID_MAJOR_SHIFT                    (24U)
+#define I2S_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define I2S_PARAM_DATALINE_MASK                  (0xFU)
+#define I2S_PARAM_DATALINE_SHIFT                 (0U)
+#define I2S_PARAM_DATALINE(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
+#define I2S_PARAM_FIFO_MASK                      (0xF00U)
+#define I2S_PARAM_FIFO_SHIFT                     (8U)
+#define I2S_PARAM_FIFO(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
+#define I2S_PARAM_FRAME_MASK                     (0xF0000U)
+#define I2S_PARAM_FRAME_SHIFT                    (16U)
+#define I2S_PARAM_FRAME(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
+/*! @} */
+
+/*! @name TCSR - SAI Transmit Control Register */
+/*! @{ */
+#define I2S_TCSR_FRDE_MASK                       (0x1U)
+#define I2S_TCSR_FRDE_SHIFT                      (0U)
+/*! FRDE - FIFO Request DMA Enable
+ *  0b0..Disables the DMA request.
+ *  0b1..Enables the DMA request.
+ */
+#define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
+#define I2S_TCSR_FWDE_MASK                       (0x2U)
+#define I2S_TCSR_FWDE_SHIFT                      (1U)
+/*! FWDE - FIFO Warning DMA Enable
+ *  0b0..Disables the DMA request.
+ *  0b1..Enables the DMA request.
+ */
+#define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
+#define I2S_TCSR_FRIE_MASK                       (0x100U)
+#define I2S_TCSR_FRIE_SHIFT                      (8U)
+/*! FRIE - FIFO Request Interrupt Enable
+ *  0b0..Disables the interrupt.
+ *  0b1..Enables the interrupt.
+ */
+#define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
+#define I2S_TCSR_FWIE_MASK                       (0x200U)
+#define I2S_TCSR_FWIE_SHIFT                      (9U)
+/*! FWIE - FIFO Warning Interrupt Enable
+ *  0b0..Disables the interrupt.
+ *  0b1..Enables the interrupt.
+ */
+#define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
+#define I2S_TCSR_FEIE_MASK                       (0x400U)
+#define I2S_TCSR_FEIE_SHIFT                      (10U)
+/*! FEIE - FIFO Error Interrupt Enable
+ *  0b0..Disables the interrupt.
+ *  0b1..Enables the interrupt.
+ */
+#define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
+#define I2S_TCSR_SEIE_MASK                       (0x800U)
+#define I2S_TCSR_SEIE_SHIFT                      (11U)
+/*! SEIE - Sync Error Interrupt Enable
+ *  0b0..Disables interrupt.
+ *  0b1..Enables interrupt.
+ */
+#define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
+#define I2S_TCSR_WSIE_MASK                       (0x1000U)
+#define I2S_TCSR_WSIE_SHIFT                      (12U)
+/*! WSIE - Word Start Interrupt Enable
+ *  0b0..Disables interrupt.
+ *  0b1..Enables interrupt.
+ */
+#define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
+#define I2S_TCSR_FRF_MASK                        (0x10000U)
+#define I2S_TCSR_FRF_SHIFT                       (16U)
+/*! FRF - FIFO Request Flag
+ *  0b0..Transmit FIFO watermark has not been reached.
+ *  0b1..Transmit FIFO watermark has been reached.
+ */
+#define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
+#define I2S_TCSR_FWF_MASK                        (0x20000U)
+#define I2S_TCSR_FWF_SHIFT                       (17U)
+/*! FWF - FIFO Warning Flag
+ *  0b0..No enabled transmit FIFO is empty.
+ *  0b1..Enabled transmit FIFO is empty.
+ */
+#define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
+#define I2S_TCSR_FEF_MASK                        (0x40000U)
+#define I2S_TCSR_FEF_SHIFT                       (18U)
+/*! FEF - FIFO Error Flag
+ *  0b0..Transmit underrun not detected.
+ *  0b1..Transmit underrun detected.
+ */
+#define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
+#define I2S_TCSR_SEF_MASK                        (0x80000U)
+#define I2S_TCSR_SEF_SHIFT                       (19U)
+/*! SEF - Sync Error Flag
+ *  0b0..Sync error not detected.
+ *  0b1..Frame sync error detected.
+ */
+#define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
+#define I2S_TCSR_WSF_MASK                        (0x100000U)
+#define I2S_TCSR_WSF_SHIFT                       (20U)
+/*! WSF - Word Start Flag
+ *  0b0..Start of word not detected.
+ *  0b1..Start of word detected.
+ */
+#define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
+#define I2S_TCSR_SR_MASK                         (0x1000000U)
+#define I2S_TCSR_SR_SHIFT                        (24U)
+/*! SR - Software Reset
+ *  0b0..No effect.
+ *  0b1..Software reset.
+ */
+#define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
+#define I2S_TCSR_FR_MASK                         (0x2000000U)
+#define I2S_TCSR_FR_SHIFT                        (25U)
+/*! FR - FIFO Reset
+ *  0b0..No effect.
+ *  0b1..FIFO reset.
+ */
+#define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
+#define I2S_TCSR_BCE_MASK                        (0x10000000U)
+#define I2S_TCSR_BCE_SHIFT                       (28U)
+/*! BCE - Bit Clock Enable
+ *  0b0..Transmit bit clock is disabled.
+ *  0b1..Transmit bit clock is enabled.
+ */
+#define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
+#define I2S_TCSR_DBGE_MASK                       (0x20000000U)
+#define I2S_TCSR_DBGE_SHIFT                      (29U)
+/*! DBGE - Debug Enable
+ *  0b0..Transmitter is disabled in Debug mode, after completing the current frame.
+ *  0b1..Transmitter is enabled in Debug mode.
+ */
+#define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
+#define I2S_TCSR_STOPE_MASK                      (0x40000000U)
+#define I2S_TCSR_STOPE_SHIFT                     (30U)
+/*! STOPE - Stop Enable
+ *  0b0..Transmitter disabled in Stop mode.
+ *  0b1..Transmitter enabled in Stop mode.
+ */
+#define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
+#define I2S_TCSR_TE_MASK                         (0x80000000U)
+#define I2S_TCSR_TE_SHIFT                        (31U)
+/*! TE - Transmitter Enable
+ *  0b0..Transmitter is disabled.
+ *  0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
+ */
+#define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
+/*! @} */
+
+/*! @name TCR1 - SAI Transmit Configuration 1 Register */
+/*! @{ */
+#define I2S_TCR1_TFW_MASK                        (0x7U)
+#define I2S_TCR1_TFW_SHIFT                       (0U)
+#define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
+/*! @} */
+
+/*! @name TCR2 - SAI Transmit Configuration 2 Register */
+/*! @{ */
+#define I2S_TCR2_DIV_MASK                        (0xFFU)
+#define I2S_TCR2_DIV_SHIFT                       (0U)
+#define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK                        (0x1000000U)
+#define I2S_TCR2_BCD_SHIFT                       (24U)
+/*! BCD - Bit Clock Direction
+ *  0b0..Bit clock is generated externally in Slave mode.
+ *  0b1..Bit clock is generated internally in Master mode.
+ */
+#define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
+#define I2S_TCR2_BCP_MASK                        (0x2000000U)
+#define I2S_TCR2_BCP_SHIFT                       (25U)
+/*! BCP - Bit Clock Polarity
+ *  0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
+ *  0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
+ */
+#define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
+#define I2S_TCR2_MSEL_MASK                       (0xC000000U)
+#define I2S_TCR2_MSEL_SHIFT                      (26U)
+/*! MSEL - MCLK Select
+ *  0b00..Bus Clock selected.
+ *  0b01..Master Clock (MCLK) 1 option selected.
+ *  0b10..Master Clock (MCLK) 2 option selected.
+ *  0b11..Master Clock (MCLK) 3 option selected.
+ */
+#define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK                        (0x10000000U)
+#define I2S_TCR2_BCI_SHIFT                       (28U)
+/*! BCI - Bit Clock Input
+ *  0b0..No effect.
+ *  0b1..Internal logic is clocked as if bit clock was externally generated.
+ */
+#define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
+#define I2S_TCR2_BCS_MASK                        (0x20000000U)
+#define I2S_TCR2_BCS_SHIFT                       (29U)
+/*! BCS - Bit Clock Swap
+ *  0b0..Use the normal bit clock source.
+ *  0b1..Swap the bit clock source.
+ */
+#define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
+#define I2S_TCR2_SYNC_MASK                       (0xC0000000U)
+#define I2S_TCR2_SYNC_SHIFT                      (30U)
+/*! SYNC - Synchronous Mode
+ *  0b00..Asynchronous mode.
+ *  0b01..Synchronous with receiver.
+ *  0b10..Synchronous with another SAI transmitter.
+ *  0b11..Synchronous with another SAI receiver.
+ */
+#define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
+/*! @} */
+
+/*! @name TCR3 - SAI Transmit Configuration 3 Register */
+/*! @{ */
+#define I2S_TCR3_WDFL_MASK                       (0x1FU)
+#define I2S_TCR3_WDFL_SHIFT                      (0U)
+#define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK                        (0x30000U)
+#define I2S_TCR3_TCE_SHIFT                       (16U)
+#define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
+#define I2S_TCR3_CFR_MASK                        (0x3000000U)
+#define I2S_TCR3_CFR_SHIFT                       (24U)
+#define I2S_TCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
+/*! @} */
+
+/*! @name TCR4 - SAI Transmit Configuration 4 Register */
+/*! @{ */
+#define I2S_TCR4_FSD_MASK                        (0x1U)
+#define I2S_TCR4_FSD_SHIFT                       (0U)
+/*! FSD - Frame Sync Direction
+ *  0b0..Frame sync is generated externally in Slave mode.
+ *  0b1..Frame sync is generated internally in Master mode.
+ */
+#define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
+#define I2S_TCR4_FSP_MASK                        (0x2U)
+#define I2S_TCR4_FSP_SHIFT                       (1U)
+/*! FSP - Frame Sync Polarity
+ *  0b0..Frame sync is active high.
+ *  0b1..Frame sync is active low.
+ */
+#define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
+#define I2S_TCR4_ONDEM_MASK                      (0x4U)
+#define I2S_TCR4_ONDEM_SHIFT                     (2U)
+/*! ONDEM - On Demand Mode
+ *  0b0..Internal frame sync is generated continuously.
+ *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
+ */
+#define I2S_TCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
+#define I2S_TCR4_FSE_MASK                        (0x8U)
+#define I2S_TCR4_FSE_SHIFT                       (3U)
+/*! FSE - Frame Sync Early
+ *  0b0..Frame sync asserts with the first bit of the frame.
+ *  0b1..Frame sync asserts one bit before the first bit of the frame.
+ */
+#define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
+#define I2S_TCR4_MF_MASK                         (0x10U)
+#define I2S_TCR4_MF_SHIFT                        (4U)
+/*! MF - MSB First
+ *  0b0..LSB is transmitted first.
+ *  0b1..MSB is transmitted first.
+ */
+#define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
+#define I2S_TCR4_CHMOD_MASK                      (0x20U)
+#define I2S_TCR4_CHMOD_SHIFT                     (5U)
+/*! CHMOD - Channel Mode
+ *  0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled.
+ *  0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled.
+ */
+#define I2S_TCR4_CHMOD(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
+#define I2S_TCR4_SYWD_MASK                       (0x1F00U)
+#define I2S_TCR4_SYWD_SHIFT                      (8U)
+#define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK                       (0x1F0000U)
+#define I2S_TCR4_FRSZ_SHIFT                      (16U)
+#define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
+#define I2S_TCR4_FPACK_MASK                      (0x3000000U)
+#define I2S_TCR4_FPACK_SHIFT                     (24U)
+/*! FPACK - FIFO Packing Mode
+ *  0b00..FIFO packing is disabled
+ *  0b01..Reserved
+ *  0b10..8-bit FIFO packing is enabled
+ *  0b11..16-bit FIFO packing is enabled
+ */
+#define I2S_TCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
+#define I2S_TCR4_FCOMB_MASK                      (0xC000000U)
+#define I2S_TCR4_FCOMB_SHIFT                     (26U)
+/*! FCOMB - FIFO Combine Mode
+ *  0b00..FIFO combine mode disabled.
+ *  0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers).
+ *  0b10..FIFO combine mode enabled on FIFO writes (by software).
+ *  0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
+ */
+#define I2S_TCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
+#define I2S_TCR4_FCONT_MASK                      (0x10000000U)
+#define I2S_TCR4_FCONT_SHIFT                     (28U)
+/*! FCONT - FIFO Continue on Error
+ *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
+ *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
+ */
+#define I2S_TCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
+/*! @} */
+
+/*! @name TCR5 - SAI Transmit Configuration 5 Register */
+/*! @{ */
+#define I2S_TCR5_FBT_MASK                        (0x1F00U)
+#define I2S_TCR5_FBT_SHIFT                       (8U)
+#define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK                        (0x1F0000U)
+#define I2S_TCR5_W0W_SHIFT                       (16U)
+#define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK                        (0x1F000000U)
+#define I2S_TCR5_WNW_SHIFT                       (24U)
+#define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
+/*! @} */
+
+/*! @name TDR - SAI Transmit Data Register */
+/*! @{ */
+#define I2S_TDR_TDR_MASK                         (0xFFFFFFFFU)
+#define I2S_TDR_TDR_SHIFT                        (0U)
+#define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
+/*! @} */
+
+/* The count of I2S_TDR */
+#define I2S_TDR_COUNT                            (2U)
+
+/*! @name TFR - SAI Transmit FIFO Register */
+/*! @{ */
+#define I2S_TFR_RFP_MASK                         (0xFU)
+#define I2S_TFR_RFP_SHIFT                        (0U)
+#define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK                         (0xF0000U)
+#define I2S_TFR_WFP_SHIFT                        (16U)
+#define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
+#define I2S_TFR_WCP_MASK                         (0x80000000U)
+#define I2S_TFR_WCP_SHIFT                        (31U)
+/*! WCP - Write Channel Pointer
+ *  0b0..No effect.
+ *  0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
+ */
+#define I2S_TFR_WCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
+/*! @} */
+
+/* The count of I2S_TFR */
+#define I2S_TFR_COUNT                            (2U)
+
+/*! @name TMR - SAI Transmit Mask Register */
+/*! @{ */
+#define I2S_TMR_TWM_MASK                         (0xFFFFFFFFU)
+#define I2S_TMR_TWM_SHIFT                        (0U)
+/*! TWM - Transmit Word Mask
+ *  0b00000000000000000000000000000000..Word N is enabled.
+ *  0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked.
+ */
+#define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
+/*! @} */
+
+/*! @name RCSR - SAI Receive Control Register */
+/*! @{ */
+#define I2S_RCSR_FRDE_MASK                       (0x1U)
+#define I2S_RCSR_FRDE_SHIFT                      (0U)
+/*! FRDE - FIFO Request DMA Enable
+ *  0b0..Disables the DMA request.
+ *  0b1..Enables the DMA request.
+ */
+#define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
+#define I2S_RCSR_FWDE_MASK                       (0x2U)
+#define I2S_RCSR_FWDE_SHIFT                      (1U)
+/*! FWDE - FIFO Warning DMA Enable
+ *  0b0..Disables the DMA request.
+ *  0b1..Enables the DMA request.
+ */
+#define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
+#define I2S_RCSR_FRIE_MASK                       (0x100U)
+#define I2S_RCSR_FRIE_SHIFT                      (8U)
+/*! FRIE - FIFO Request Interrupt Enable
+ *  0b0..Disables the interrupt.
+ *  0b1..Enables the interrupt.
+ */
+#define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
+#define I2S_RCSR_FWIE_MASK                       (0x200U)
+#define I2S_RCSR_FWIE_SHIFT                      (9U)
+/*! FWIE - FIFO Warning Interrupt Enable
+ *  0b0..Disables the interrupt.
+ *  0b1..Enables the interrupt.
+ */
+#define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
+#define I2S_RCSR_FEIE_MASK                       (0x400U)
+#define I2S_RCSR_FEIE_SHIFT                      (10U)
+/*! FEIE - FIFO Error Interrupt Enable
+ *  0b0..Disables the interrupt.
+ *  0b1..Enables the interrupt.
+ */
+#define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
+#define I2S_RCSR_SEIE_MASK                       (0x800U)
+#define I2S_RCSR_SEIE_SHIFT                      (11U)
+/*! SEIE - Sync Error Interrupt Enable
+ *  0b0..Disables interrupt.
+ *  0b1..Enables interrupt.
+ */
+#define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
+#define I2S_RCSR_WSIE_MASK                       (0x1000U)
+#define I2S_RCSR_WSIE_SHIFT                      (12U)
+/*! WSIE - Word Start Interrupt Enable
+ *  0b0..Disables interrupt.
+ *  0b1..Enables interrupt.
+ */
+#define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
+#define I2S_RCSR_FRF_MASK                        (0x10000U)
+#define I2S_RCSR_FRF_SHIFT                       (16U)
+/*! FRF - FIFO Request Flag
+ *  0b0..Receive FIFO watermark not reached.
+ *  0b1..Receive FIFO watermark has been reached.
+ */
+#define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
+#define I2S_RCSR_FWF_MASK                        (0x20000U)
+#define I2S_RCSR_FWF_SHIFT                       (17U)
+/*! FWF - FIFO Warning Flag
+ *  0b0..No enabled receive FIFO is full.
+ *  0b1..Enabled receive FIFO is full.
+ */
+#define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
+#define I2S_RCSR_FEF_MASK                        (0x40000U)
+#define I2S_RCSR_FEF_SHIFT                       (18U)
+/*! FEF - FIFO Error Flag
+ *  0b0..Receive overflow not detected.
+ *  0b1..Receive overflow detected.
+ */
+#define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
+#define I2S_RCSR_SEF_MASK                        (0x80000U)
+#define I2S_RCSR_SEF_SHIFT                       (19U)
+/*! SEF - Sync Error Flag
+ *  0b0..Sync error not detected.
+ *  0b1..Frame sync error detected.
+ */
+#define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
+#define I2S_RCSR_WSF_MASK                        (0x100000U)
+#define I2S_RCSR_WSF_SHIFT                       (20U)
+/*! WSF - Word Start Flag
+ *  0b0..Start of word not detected.
+ *  0b1..Start of word detected.
+ */
+#define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
+#define I2S_RCSR_SR_MASK                         (0x1000000U)
+#define I2S_RCSR_SR_SHIFT                        (24U)
+/*! SR - Software Reset
+ *  0b0..No effect.
+ *  0b1..Software reset.
+ */
+#define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
+#define I2S_RCSR_FR_MASK                         (0x2000000U)
+#define I2S_RCSR_FR_SHIFT                        (25U)
+/*! FR - FIFO Reset
+ *  0b0..No effect.
+ *  0b1..FIFO reset.
+ */
+#define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
+#define I2S_RCSR_BCE_MASK                        (0x10000000U)
+#define I2S_RCSR_BCE_SHIFT                       (28U)
+/*! BCE - Bit Clock Enable
+ *  0b0..Receive bit clock is disabled.
+ *  0b1..Receive bit clock is enabled.
+ */
+#define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
+#define I2S_RCSR_DBGE_MASK                       (0x20000000U)
+#define I2S_RCSR_DBGE_SHIFT                      (29U)
+/*! DBGE - Debug Enable
+ *  0b0..Receiver is disabled in Debug mode, after completing the current frame.
+ *  0b1..Receiver is enabled in Debug mode.
+ */
+#define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
+#define I2S_RCSR_STOPE_MASK                      (0x40000000U)
+#define I2S_RCSR_STOPE_SHIFT                     (30U)
+/*! STOPE - Stop Enable
+ *  0b0..Receiver disabled in Stop mode.
+ *  0b1..Receiver enabled in Stop mode.
+ */
+#define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
+#define I2S_RCSR_RE_MASK                         (0x80000000U)
+#define I2S_RCSR_RE_SHIFT                        (31U)
+/*! RE - Receiver Enable
+ *  0b0..Receiver is disabled.
+ *  0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
+ */
+#define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
+/*! @} */
+
+/*! @name RCR1 - SAI Receive Configuration 1 Register */
+/*! @{ */
+#define I2S_RCR1_RFW_MASK                        (0x7U)
+#define I2S_RCR1_RFW_SHIFT                       (0U)
+#define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
+/*! @} */
+
+/*! @name RCR2 - SAI Receive Configuration 2 Register */
+/*! @{ */
+#define I2S_RCR2_DIV_MASK                        (0xFFU)
+#define I2S_RCR2_DIV_SHIFT                       (0U)
+#define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK                        (0x1000000U)
+#define I2S_RCR2_BCD_SHIFT                       (24U)
+/*! BCD - Bit Clock Direction
+ *  0b0..Bit clock is generated externally in Slave mode.
+ *  0b1..Bit clock is generated internally in Master mode.
+ */
+#define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
+#define I2S_RCR2_BCP_MASK                        (0x2000000U)
+#define I2S_RCR2_BCP_SHIFT                       (25U)
+/*! BCP - Bit Clock Polarity
+ *  0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
+ *  0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
+ */
+#define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
+#define I2S_RCR2_MSEL_MASK                       (0xC000000U)
+#define I2S_RCR2_MSEL_SHIFT                      (26U)
+/*! MSEL - MCLK Select
+ *  0b00..Bus Clock selected.
+ *  0b01..Master Clock (MCLK) 1 option selected.
+ *  0b10..Master Clock (MCLK) 2 option selected.
+ *  0b11..Master Clock (MCLK) 3 option selected.
+ */
+#define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK                        (0x10000000U)
+#define I2S_RCR2_BCI_SHIFT                       (28U)
+/*! BCI - Bit Clock Input
+ *  0b0..No effect.
+ *  0b1..Internal logic is clocked as if bit clock was externally generated.
+ */
+#define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
+#define I2S_RCR2_BCS_MASK                        (0x20000000U)
+#define I2S_RCR2_BCS_SHIFT                       (29U)
+/*! BCS - Bit Clock Swap
+ *  0b0..Use the normal bit clock source.
+ *  0b1..Swap the bit clock source.
+ */
+#define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
+#define I2S_RCR2_SYNC_MASK                       (0xC0000000U)
+#define I2S_RCR2_SYNC_SHIFT                      (30U)
+/*! SYNC - Synchronous Mode
+ *  0b00..Asynchronous mode.
+ *  0b01..Synchronous with transmitter.
+ *  0b10..Synchronous with another SAI receiver.
+ *  0b11..Synchronous with another SAI transmitter.
+ */
+#define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
+/*! @} */
+
+/*! @name RCR3 - SAI Receive Configuration 3 Register */
+/*! @{ */
+#define I2S_RCR3_WDFL_MASK                       (0x1FU)
+#define I2S_RCR3_WDFL_SHIFT                      (0U)
+#define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK                        (0x30000U)
+#define I2S_RCR3_RCE_SHIFT                       (16U)
+#define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
+#define I2S_RCR3_CFR_MASK                        (0x3000000U)
+#define I2S_RCR3_CFR_SHIFT                       (24U)
+#define I2S_RCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
+/*! @} */
+
+/*! @name RCR4 - SAI Receive Configuration 4 Register */
+/*! @{ */
+#define I2S_RCR4_FSD_MASK                        (0x1U)
+#define I2S_RCR4_FSD_SHIFT                       (0U)
+/*! FSD - Frame Sync Direction
+ *  0b0..Frame Sync is generated externally in Slave mode.
+ *  0b1..Frame Sync is generated internally in Master mode.
+ */
+#define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
+#define I2S_RCR4_FSP_MASK                        (0x2U)
+#define I2S_RCR4_FSP_SHIFT                       (1U)
+/*! FSP - Frame Sync Polarity
+ *  0b0..Frame sync is active high.
+ *  0b1..Frame sync is active low.
+ */
+#define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
+#define I2S_RCR4_ONDEM_MASK                      (0x4U)
+#define I2S_RCR4_ONDEM_SHIFT                     (2U)
+/*! ONDEM - On Demand Mode
+ *  0b0..Internal frame sync is generated continuously.
+ *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
+ */
+#define I2S_RCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
+#define I2S_RCR4_FSE_MASK                        (0x8U)
+#define I2S_RCR4_FSE_SHIFT                       (3U)
+/*! FSE - Frame Sync Early
+ *  0b0..Frame sync asserts with the first bit of the frame.
+ *  0b1..Frame sync asserts one bit before the first bit of the frame.
+ */
+#define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
+#define I2S_RCR4_MF_MASK                         (0x10U)
+#define I2S_RCR4_MF_SHIFT                        (4U)
+/*! MF - MSB First
+ *  0b0..LSB is received first.
+ *  0b1..MSB is received first.
+ */
+#define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
+#define I2S_RCR4_SYWD_MASK                       (0x1F00U)
+#define I2S_RCR4_SYWD_SHIFT                      (8U)
+#define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK                       (0x1F0000U)
+#define I2S_RCR4_FRSZ_SHIFT                      (16U)
+#define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
+#define I2S_RCR4_FPACK_MASK                      (0x3000000U)
+#define I2S_RCR4_FPACK_SHIFT                     (24U)
+/*! FPACK - FIFO Packing Mode
+ *  0b00..FIFO packing is disabled
+ *  0b01..Reserved.
+ *  0b10..8-bit FIFO packing is enabled
+ *  0b11..16-bit FIFO packing is enabled
+ */
+#define I2S_RCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
+#define I2S_RCR4_FCOMB_MASK                      (0xC000000U)
+#define I2S_RCR4_FCOMB_SHIFT                     (26U)
+/*! FCOMB - FIFO Combine Mode
+ *  0b00..FIFO combine mode disabled.
+ *  0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers).
+ *  0b10..FIFO combine mode enabled on FIFO reads (by software).
+ *  0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
+ */
+#define I2S_RCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
+#define I2S_RCR4_FCONT_MASK                      (0x10000000U)
+#define I2S_RCR4_FCONT_SHIFT                     (28U)
+/*! FCONT - FIFO Continue on Error
+ *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
+ *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
+ */
+#define I2S_RCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
+/*! @} */
+
+/*! @name RCR5 - SAI Receive Configuration 5 Register */
+/*! @{ */
+#define I2S_RCR5_FBT_MASK                        (0x1F00U)
+#define I2S_RCR5_FBT_SHIFT                       (8U)
+#define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK                        (0x1F0000U)
+#define I2S_RCR5_W0W_SHIFT                       (16U)
+#define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK                        (0x1F000000U)
+#define I2S_RCR5_WNW_SHIFT                       (24U)
+#define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
+/*! @} */
+
+/*! @name RDR - SAI Receive Data Register */
+/*! @{ */
+#define I2S_RDR_RDR_MASK                         (0xFFFFFFFFU)
+#define I2S_RDR_RDR_SHIFT                        (0U)
+#define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
+/*! @} */
+
+/* The count of I2S_RDR */
+#define I2S_RDR_COUNT                            (2U)
+
+/*! @name RFR - SAI Receive FIFO Register */
+/*! @{ */
+#define I2S_RFR_RFP_MASK                         (0xFU)
+#define I2S_RFR_RFP_SHIFT                        (0U)
+#define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
+#define I2S_RFR_RCP_MASK                         (0x8000U)
+#define I2S_RFR_RCP_SHIFT                        (15U)
+/*! RCP - Receive Channel Pointer
+ *  0b0..No effect.
+ *  0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
+ */
+#define I2S_RFR_RCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
+#define I2S_RFR_WFP_MASK                         (0xF0000U)
+#define I2S_RFR_WFP_SHIFT                        (16U)
+#define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
+/*! @} */
+
+/* The count of I2S_RFR */
+#define I2S_RFR_COUNT                            (2U)
+
+/*! @name RMR - SAI Receive Mask Register */
+/*! @{ */
+#define I2S_RMR_RWM_MASK                         (0xFFFFFFFFU)
+#define I2S_RMR_RWM_SHIFT                        (0U)
+/*! RWM - Receive Word Mask
+ *  0b00000000000000000000000000000000..Word N is enabled.
+ *  0b00000000000000000000000000000001..Word N is masked.
+ */
+#define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE                                (0x4003D000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0                                     ((I2S_Type *)I2S0_BASE)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS                           { I2S0_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS                            { I2S0 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_RX_IRQS                              { I2S0_IRQn }
+#define I2S_TX_IRQS                              { I2S0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- INTMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INTMUX_Peripheral_Access_Layer INTMUX Peripheral Access Layer
+ * @{
+ */
+
+/** INTMUX - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x40 */
+    __IO uint32_t CHn_CSR;                           /**< Channel n Control Status Register, array offset: 0x0, array step: 0x40 */
+    __I  uint32_t CHn_VEC;                           /**< Channel n Vector Number Register, array offset: 0x4, array step: 0x40 */
+         uint8_t RESERVED_0[8];
+    __IO uint32_t CHn_IER_31_0;                      /**< Channel n Interrupt Enable Register, array offset: 0x10, array step: 0x40 */
+         uint8_t RESERVED_1[12];
+    __I  uint32_t CHn_IPR_31_0;                      /**< Channel n Interrupt Pending Register, array offset: 0x20, array step: 0x40 */
+         uint8_t RESERVED_2[28];
+  } CHANNEL[8];
+} INTMUX_Type;
+
+/* ----------------------------------------------------------------------------
+   -- INTMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INTMUX_Register_Masks INTMUX Register Masks
+ * @{
+ */
+
+/*! @name CHn_CSR - Channel n Control Status Register */
+/*! @{ */
+#define INTMUX_CHn_CSR_RST_MASK                  (0x1U)
+#define INTMUX_CHn_CSR_RST_SHIFT                 (0U)
+/*! RST - Software Reset
+ *  0b0..No operation.
+ *  0b1..Perform a software reset on this channel.
+ */
+#define INTMUX_CHn_CSR_RST(x)                    (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_RST_SHIFT)) & INTMUX_CHn_CSR_RST_MASK)
+#define INTMUX_CHn_CSR_AND_MASK                  (0x2U)
+#define INTMUX_CHn_CSR_AND_SHIFT                 (1U)
+/*! AND - Logic AND
+ *  0b0..Logic OR all enabled interrupt inputs.
+ *  0b1..Logic AND all enabled interrupt inputs.
+ */
+#define INTMUX_CHn_CSR_AND(x)                    (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_AND_SHIFT)) & INTMUX_CHn_CSR_AND_MASK)
+#define INTMUX_CHn_CSR_IRQN_MASK                 (0x30U)
+#define INTMUX_CHn_CSR_IRQN_SHIFT                (4U)
+/*! IRQN - Channel Input Number
+ *  0b00..32 interrupt inputs
+ *  0b01..Reserved
+ *  0b10..Reserved
+ *  0b11..Reserved
+ */
+#define INTMUX_CHn_CSR_IRQN(x)                   (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQN_SHIFT)) & INTMUX_CHn_CSR_IRQN_MASK)
+#define INTMUX_CHn_CSR_CHIN_MASK                 (0xF00U)
+#define INTMUX_CHn_CSR_CHIN_SHIFT                (8U)
+#define INTMUX_CHn_CSR_CHIN(x)                   (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_CHIN_SHIFT)) & INTMUX_CHn_CSR_CHIN_MASK)
+#define INTMUX_CHn_CSR_IRQP_MASK                 (0x80000000U)
+#define INTMUX_CHn_CSR_IRQP_SHIFT                (31U)
+/*! IRQP - Channel Interrupt Request Pending
+ *  0b0..No interrupt is pending.
+ *  0b1..The interrupt output of this channel is pending.
+ */
+#define INTMUX_CHn_CSR_IRQP(x)                   (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQP_SHIFT)) & INTMUX_CHn_CSR_IRQP_MASK)
+/*! @} */
+
+/* The count of INTMUX_CHn_CSR */
+#define INTMUX_CHn_CSR_COUNT                     (8U)
+
+/*! @name CHn_VEC - Channel n Vector Number Register */
+/*! @{ */
+#define INTMUX_CHn_VEC_VECN_MASK                 (0x3FFCU)
+#define INTMUX_CHn_VEC_VECN_SHIFT                (2U)
+#define INTMUX_CHn_VEC_VECN(x)                   (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_VEC_VECN_SHIFT)) & INTMUX_CHn_VEC_VECN_MASK)
+/*! @} */
+
+/* The count of INTMUX_CHn_VEC */
+#define INTMUX_CHn_VEC_COUNT                     (8U)
+
+/*! @name CHn_IER_31_0 - Channel n Interrupt Enable Register */
+/*! @{ */
+#define INTMUX_CHn_IER_31_0_INTE_MASK            (0xFFFFFFFFU)
+#define INTMUX_CHn_IER_31_0_INTE_SHIFT           (0U)
+#define INTMUX_CHn_IER_31_0_INTE(x)              (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IER_31_0_INTE_SHIFT)) & INTMUX_CHn_IER_31_0_INTE_MASK)
+/*! @} */
+
+/* The count of INTMUX_CHn_IER_31_0 */
+#define INTMUX_CHn_IER_31_0_COUNT                (8U)
+
+/*! @name CHn_IPR_31_0 - Channel n Interrupt Pending Register */
+/*! @{ */
+#define INTMUX_CHn_IPR_31_0_INTP_MASK            (0xFFFFFFFFU)
+#define INTMUX_CHn_IPR_31_0_INTP_SHIFT           (0U)
+#define INTMUX_CHn_IPR_31_0_INTP(x)              (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IPR_31_0_INTP_SHIFT)) & INTMUX_CHn_IPR_31_0_INTP_MASK)
+/*! @} */
+
+/* The count of INTMUX_CHn_IPR_31_0 */
+#define INTMUX_CHn_IPR_31_0_COUNT                (8U)
+
+
+/*!
+ * @}
+ */ /* end of group INTMUX_Register_Masks */
+
+
+/* INTMUX - Peripheral instance base addresses */
+/** Peripheral INTMUX1 base address */
+#define INTMUX1_BASE                             (0x41022000u)
+/** Peripheral INTMUX1 base pointer */
+#define INTMUX1                                  ((INTMUX_Type *)INTMUX1_BASE)
+/** Array initializer of INTMUX peripheral base addresses */
+#define INTMUX_BASE_ADDRS                        { 0u, INTMUX1_BASE }
+/** Array initializer of INTMUX peripheral base pointers */
+#define INTMUX_BASE_PTRS                         { (INTMUX_Type *)0u, INTMUX1 }
+/** Interrupt vectors for the INTMUX peripheral type */
+#define INTMUX_IRQS                              { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { INTMUX1_0_IRQn, INTMUX1_1_IRQn, INTMUX1_2_IRQn, INTMUX1_3_IRQn, INTMUX1_4_IRQn, INTMUX1_5_IRQn, INTMUX1_6_IRQn, INTMUX1_7_IRQn } }
+
+/*!
+ * @}
+ */ /* end of group INTMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __IO uint32_t PE1;                               /**< Pin Enable 1 register, offset: 0x8 */
+  __IO uint32_t PE2;                               /**< Pin Enable 2 register, offset: 0xC */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t ME;                                /**< Module Interrupt Enable register, offset: 0x18 */
+  __IO uint32_t DE;                                /**< Module DMA/Trigger Enable register, offset: 0x1C */
+  __IO uint32_t PF;                                /**< Pin Flag register, offset: 0x20 */
+       uint8_t RESERVED_1[12];
+  __IO uint32_t FILT;                              /**< Pin Filter register, offset: 0x30 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t PDC1;                              /**< Pin DMA/Trigger Configuration 1 register, offset: 0x38 */
+  __IO uint32_t PDC2;                              /**< Pin DMA/Trigger Configuration 2 register, offset: 0x3C */
+       uint8_t RESERVED_3[8];
+  __IO uint32_t FDC;                               /**< Pin Filter DMA/Trigger Configuration register, offset: 0x48 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t PMC;                               /**< Pin Mode Configuration register, offset: 0x50 */
+       uint8_t RESERVED_5[4];
+  __IO uint32_t FMC;                               /**< Pin Filter Mode Configuration register, offset: 0x58 */
+} LLWU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define LLWU_VERID_FEATURE_MASK                  (0xFFFFU)
+#define LLWU_VERID_FEATURE_SHIFT                 (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000000000000..Standard features implemented
+ *  0b0000000000000001..Support for DMA/Trigger generation from wakeup pins and filters enabled. Support for external pin/filter detection during all power modes enabled.
+ */
+#define LLWU_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_FEATURE_SHIFT)) & LLWU_VERID_FEATURE_MASK)
+#define LLWU_VERID_MINOR_MASK                    (0xFF0000U)
+#define LLWU_VERID_MINOR_SHIFT                   (16U)
+#define LLWU_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_MINOR_SHIFT)) & LLWU_VERID_MINOR_MASK)
+#define LLWU_VERID_MAJOR_MASK                    (0xFF000000U)
+#define LLWU_VERID_MAJOR_SHIFT                   (24U)
+#define LLWU_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_VERID_MAJOR_SHIFT)) & LLWU_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define LLWU_PARAM_FILTERS_MASK                  (0xFFU)
+#define LLWU_PARAM_FILTERS_SHIFT                 (0U)
+#define LLWU_PARAM_FILTERS(x)                    (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_FILTERS_SHIFT)) & LLWU_PARAM_FILTERS_MASK)
+#define LLWU_PARAM_DMAS_MASK                     (0xFF00U)
+#define LLWU_PARAM_DMAS_SHIFT                    (8U)
+#define LLWU_PARAM_DMAS(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_DMAS_SHIFT)) & LLWU_PARAM_DMAS_MASK)
+#define LLWU_PARAM_MODULES_MASK                  (0xFF0000U)
+#define LLWU_PARAM_MODULES_SHIFT                 (16U)
+#define LLWU_PARAM_MODULES(x)                    (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_MODULES_SHIFT)) & LLWU_PARAM_MODULES_MASK)
+#define LLWU_PARAM_PINS_MASK                     (0xFF000000U)
+#define LLWU_PARAM_PINS_SHIFT                    (24U)
+#define LLWU_PARAM_PINS(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PARAM_PINS_SHIFT)) & LLWU_PARAM_PINS_MASK)
+/*! @} */
+
+/*! @name PE1 - Pin Enable 1 register */
+/*! @{ */
+#define LLWU_PE1_WUPE0_MASK                      (0x3U)
+#define LLWU_PE1_WUPE0_SHIFT                     (0U)
+/*! WUPE0 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE0(x)                        (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK                      (0xCU)
+#define LLWU_PE1_WUPE1_SHIFT                     (2U)
+/*! WUPE1 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE1(x)                        (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK                      (0x30U)
+#define LLWU_PE1_WUPE2_SHIFT                     (4U)
+/*! WUPE2 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE2(x)                        (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK                      (0xC0U)
+#define LLWU_PE1_WUPE3_SHIFT                     (6U)
+/*! WUPE3 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE3(x)                        (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
+#define LLWU_PE1_WUPE4_MASK                      (0x300U)
+#define LLWU_PE1_WUPE4_SHIFT                     (8U)
+/*! WUPE4 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE4(x)                        (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE4_SHIFT)) & LLWU_PE1_WUPE4_MASK)
+#define LLWU_PE1_WUPE5_MASK                      (0xC00U)
+#define LLWU_PE1_WUPE5_SHIFT                     (10U)
+/*! WUPE5 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE5(x)                        (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE5_SHIFT)) & LLWU_PE1_WUPE5_MASK)
+#define LLWU_PE1_WUPE6_MASK                      (0x3000U)
+#define LLWU_PE1_WUPE6_SHIFT                     (12U)
+/*! WUPE6 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE6(x)                        (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE6_SHIFT)) & LLWU_PE1_WUPE6_MASK)
+#define LLWU_PE1_WUPE7_MASK                      (0xC000U)
+#define LLWU_PE1_WUPE7_SHIFT                     (14U)
+/*! WUPE7 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE7(x)                        (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE7_SHIFT)) & LLWU_PE1_WUPE7_MASK)
+#define LLWU_PE1_WUPE8_MASK                      (0x30000U)
+#define LLWU_PE1_WUPE8_SHIFT                     (16U)
+/*! WUPE8 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE8(x)                        (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE8_SHIFT)) & LLWU_PE1_WUPE8_MASK)
+#define LLWU_PE1_WUPE9_MASK                      (0xC0000U)
+#define LLWU_PE1_WUPE9_SHIFT                     (18U)
+/*! WUPE9 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE9(x)                        (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE9_SHIFT)) & LLWU_PE1_WUPE9_MASK)
+#define LLWU_PE1_WUPE10_MASK                     (0x300000U)
+#define LLWU_PE1_WUPE10_SHIFT                    (20U)
+/*! WUPE10 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE10(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE10_SHIFT)) & LLWU_PE1_WUPE10_MASK)
+#define LLWU_PE1_WUPE11_MASK                     (0xC00000U)
+#define LLWU_PE1_WUPE11_SHIFT                    (22U)
+/*! WUPE11 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE11(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE11_SHIFT)) & LLWU_PE1_WUPE11_MASK)
+#define LLWU_PE1_WUPE12_MASK                     (0x3000000U)
+#define LLWU_PE1_WUPE12_SHIFT                    (24U)
+/*! WUPE12 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE12(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE12_SHIFT)) & LLWU_PE1_WUPE12_MASK)
+#define LLWU_PE1_WUPE13_MASK                     (0xC000000U)
+#define LLWU_PE1_WUPE13_SHIFT                    (26U)
+/*! WUPE13 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE13(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE13_SHIFT)) & LLWU_PE1_WUPE13_MASK)
+#define LLWU_PE1_WUPE14_MASK                     (0x30000000U)
+#define LLWU_PE1_WUPE14_SHIFT                    (28U)
+/*! WUPE14 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE14(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE14_SHIFT)) & LLWU_PE1_WUPE14_MASK)
+#define LLWU_PE1_WUPE15_MASK                     (0xC0000000U)
+#define LLWU_PE1_WUPE15_SHIFT                    (30U)
+/*! WUPE15 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE1_WUPE15(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE1_WUPE15_SHIFT)) & LLWU_PE1_WUPE15_MASK)
+/*! @} */
+
+/*! @name PE2 - Pin Enable 2 register */
+/*! @{ */
+#define LLWU_PE2_WUPE16_MASK                     (0x3U)
+#define LLWU_PE2_WUPE16_SHIFT                    (0U)
+/*! WUPE16 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE16(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE16_SHIFT)) & LLWU_PE2_WUPE16_MASK)
+#define LLWU_PE2_WUPE17_MASK                     (0xCU)
+#define LLWU_PE2_WUPE17_SHIFT                    (2U)
+/*! WUPE17 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE17(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE17_SHIFT)) & LLWU_PE2_WUPE17_MASK)
+#define LLWU_PE2_WUPE18_MASK                     (0x30U)
+#define LLWU_PE2_WUPE18_SHIFT                    (4U)
+/*! WUPE18 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE18(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE18_SHIFT)) & LLWU_PE2_WUPE18_MASK)
+#define LLWU_PE2_WUPE19_MASK                     (0xC0U)
+#define LLWU_PE2_WUPE19_SHIFT                    (6U)
+/*! WUPE19 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE19(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE19_SHIFT)) & LLWU_PE2_WUPE19_MASK)
+#define LLWU_PE2_WUPE20_MASK                     (0x300U)
+#define LLWU_PE2_WUPE20_SHIFT                    (8U)
+/*! WUPE20 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE20(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE20_SHIFT)) & LLWU_PE2_WUPE20_MASK)
+#define LLWU_PE2_WUPE21_MASK                     (0xC00U)
+#define LLWU_PE2_WUPE21_SHIFT                    (10U)
+/*! WUPE21 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE21(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE21_SHIFT)) & LLWU_PE2_WUPE21_MASK)
+#define LLWU_PE2_WUPE22_MASK                     (0x3000U)
+#define LLWU_PE2_WUPE22_SHIFT                    (12U)
+/*! WUPE22 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE22(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE22_SHIFT)) & LLWU_PE2_WUPE22_MASK)
+#define LLWU_PE2_WUPE23_MASK                     (0xC000U)
+#define LLWU_PE2_WUPE23_SHIFT                    (14U)
+/*! WUPE23 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE23(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE23_SHIFT)) & LLWU_PE2_WUPE23_MASK)
+#define LLWU_PE2_WUPE24_MASK                     (0x30000U)
+#define LLWU_PE2_WUPE24_SHIFT                    (16U)
+/*! WUPE24 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE24(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE24_SHIFT)) & LLWU_PE2_WUPE24_MASK)
+#define LLWU_PE2_WUPE25_MASK                     (0xC0000U)
+#define LLWU_PE2_WUPE25_SHIFT                    (18U)
+/*! WUPE25 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE25(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE25_SHIFT)) & LLWU_PE2_WUPE25_MASK)
+#define LLWU_PE2_WUPE26_MASK                     (0x300000U)
+#define LLWU_PE2_WUPE26_SHIFT                    (20U)
+/*! WUPE26 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE26(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE26_SHIFT)) & LLWU_PE2_WUPE26_MASK)
+#define LLWU_PE2_Reserved27_MASK                 (0xC00000U)
+#define LLWU_PE2_Reserved27_SHIFT                (22U)
+/*! Reserved27 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_Reserved27(x)                   (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved27_SHIFT)) & LLWU_PE2_Reserved27_MASK)
+#define LLWU_PE2_Reserved28_MASK                 (0x3000000U)
+#define LLWU_PE2_Reserved28_SHIFT                (24U)
+/*! Reserved28 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_Reserved28(x)                   (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_Reserved28_SHIFT)) & LLWU_PE2_Reserved28_MASK)
+#define LLWU_PE2_WUPE29_MASK                     (0xC000000U)
+#define LLWU_PE2_WUPE29_SHIFT                    (26U)
+/*! WUPE29 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE29(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE29_SHIFT)) & LLWU_PE2_WUPE29_MASK)
+#define LLWU_PE2_WUPE30_MASK                     (0x30000000U)
+#define LLWU_PE2_WUPE30_SHIFT                    (28U)
+/*! WUPE30 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE30(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE30_SHIFT)) & LLWU_PE2_WUPE30_MASK)
+#define LLWU_PE2_WUPE31_MASK                     (0xC0000000U)
+#define LLWU_PE2_WUPE31_SHIFT                    (30U)
+/*! WUPE31 - Wakeup pin enable for LLWU_Pn
+ *  0b00..External input pin disabled as wakeup input
+ *  0b01..External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..External input pin enabled with any change detection when configured as interrupt/DMA request
+ */
+#define LLWU_PE2_WUPE31(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PE2_WUPE31_SHIFT)) & LLWU_PE2_WUPE31_MASK)
+/*! @} */
+
+/*! @name ME - Module Interrupt Enable register */
+/*! @{ */
+#define LLWU_ME_WUME0_MASK                       (0x1U)
+#define LLWU_ME_WUME0_SHIFT                      (0U)
+/*! WUME0 - Wakeup module enable for module n
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME0(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
+#define LLWU_ME_WUME1_MASK                       (0x2U)
+#define LLWU_ME_WUME1_SHIFT                      (1U)
+/*! WUME1 - Wakeup module enable for module n
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME1(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
+#define LLWU_ME_WUME2_MASK                       (0x4U)
+#define LLWU_ME_WUME2_SHIFT                      (2U)
+/*! WUME2 - Wakeup module enable for module n
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME2(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
+#define LLWU_ME_Reserved3_MASK                   (0x8U)
+#define LLWU_ME_Reserved3_SHIFT                  (3U)
+/*! Reserved3 - Wakeup module enable for module n
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_Reserved3(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_ME_Reserved3_SHIFT)) & LLWU_ME_Reserved3_MASK)
+#define LLWU_ME_WUME3_MASK                       (0x8U)
+#define LLWU_ME_WUME3_SHIFT                      (3U)
+/*! WUME3 - Wakeup module enable for module n
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME3(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
+#define LLWU_ME_Reserved4_MASK                   (0x10U)
+#define LLWU_ME_Reserved4_SHIFT                  (4U)
+/*! Reserved4 - Wakeup module enable for module n
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_Reserved4(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_ME_Reserved4_SHIFT)) & LLWU_ME_Reserved4_MASK)
+#define LLWU_ME_WUME5_MASK                       (0x20U)
+#define LLWU_ME_WUME5_SHIFT                      (5U)
+/*! WUME5 - Wakeup module enable for module n
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME5(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
+#define LLWU_ME_WUME6_MASK                       (0x40U)
+#define LLWU_ME_WUME6_SHIFT                      (6U)
+/*! WUME6 - Wakeup module enable for module n
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME6(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
+#define LLWU_ME_WUME7_MASK                       (0x80U)
+#define LLWU_ME_WUME7_SHIFT                      (7U)
+/*! WUME7 - Wakeup module enable for module n
+ *  0b0..Internal module flag not used as wakeup source
+ *  0b1..Internal module flag used as wakeup source
+ */
+#define LLWU_ME_WUME7(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
+/*! @} */
+
+/*! @name DE - Module DMA/Trigger Enable register */
+/*! @{ */
+#define LLWU_DE_WUDE0_MASK                       (0x1U)
+#define LLWU_DE_WUDE0_SHIFT                      (0U)
+/*! WUDE0 - DMA/Trigger wakeup enable for module n
+ *  0b0..Internal module request not enabled as a DMA/Trigger wakeup source
+ *  0b1..Internal module request enabled as a DMA/Trigger wakeup source
+ */
+#define LLWU_DE_WUDE0(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE0_SHIFT)) & LLWU_DE_WUDE0_MASK)
+#define LLWU_DE_WUDE1_MASK                       (0x2U)
+#define LLWU_DE_WUDE1_SHIFT                      (1U)
+/*! WUDE1 - DMA/Trigger wakeup enable for module n
+ *  0b0..Internal module request not enabled as a DMA/Trigger wakeup source
+ *  0b1..Internal module request enabled as a DMA/Trigger wakeup source
+ */
+#define LLWU_DE_WUDE1(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE1_SHIFT)) & LLWU_DE_WUDE1_MASK)
+#define LLWU_DE_WUDE2_MASK                       (0x4U)
+#define LLWU_DE_WUDE2_SHIFT                      (2U)
+/*! WUDE2 - DMA/Trigger wakeup enable for module n
+ *  0b0..Internal module request not enabled as a DMA/Trigger wakeup source
+ *  0b1..Internal module request enabled as a DMA/Trigger wakeup source
+ */
+#define LLWU_DE_WUDE2(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE2_SHIFT)) & LLWU_DE_WUDE2_MASK)
+#define LLWU_DE_Reserved3_MASK                   (0x8U)
+#define LLWU_DE_Reserved3_SHIFT                  (3U)
+/*! Reserved3 - DMA/Trigger wakeup enable for module n
+ *  0b0..Internal module request not enabled as a DMA/Trigger wakeup source
+ *  0b1..Internal module request enabled as a DMA/Trigger wakeup source
+ */
+#define LLWU_DE_Reserved3(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_DE_Reserved3_SHIFT)) & LLWU_DE_Reserved3_MASK)
+#define LLWU_DE_WUDE4_MASK                       (0x10U)
+#define LLWU_DE_WUDE4_SHIFT                      (4U)
+/*! WUDE4 - DMA/Trigger wakeup enable for module n
+ *  0b0..Internal module request not enabled as a DMA/Trigger wakeup source
+ *  0b1..Internal module request enabled as a DMA/Trigger wakeup source
+ */
+#define LLWU_DE_WUDE4(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE4_SHIFT)) & LLWU_DE_WUDE4_MASK)
+#define LLWU_DE_WUDE5_MASK                       (0x20U)
+#define LLWU_DE_WUDE5_SHIFT                      (5U)
+/*! WUDE5 - DMA/Trigger wakeup enable for module n
+ *  0b0..Internal module request not enabled as a DMA/Trigger wakeup source
+ *  0b1..Internal module request enabled as a DMA/Trigger wakeup source
+ */
+#define LLWU_DE_WUDE5(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE5_SHIFT)) & LLWU_DE_WUDE5_MASK)
+#define LLWU_DE_WUDE6_MASK                       (0x40U)
+#define LLWU_DE_WUDE6_SHIFT                      (6U)
+/*! WUDE6 - DMA/Trigger wakeup enable for module n
+ *  0b0..Internal module request not enabled as a DMA/Trigger wakeup source
+ *  0b1..Internal module request enabled as a DMA/Trigger wakeup source
+ */
+#define LLWU_DE_WUDE6(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_DE_WUDE6_SHIFT)) & LLWU_DE_WUDE6_MASK)
+#define LLWU_DE_Reserved7_MASK                   (0x80U)
+#define LLWU_DE_Reserved7_SHIFT                  (7U)
+/*! Reserved7 - DMA/Trigger wakeup enable for module n
+ *  0b0..Internal module request not enabled as a DMA/Trigger wakeup source
+ *  0b1..Internal module request enabled as a DMA/Trigger wakeup source
+ */
+#define LLWU_DE_Reserved7(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_DE_Reserved7_SHIFT)) & LLWU_DE_Reserved7_MASK)
+/*! @} */
+
+/*! @name PF - Pin Flag register */
+/*! @{ */
+#define LLWU_PF_WUF0_MASK                        (0x1U)
+#define LLWU_PF_WUF0_SHIFT                       (0U)
+/*! WUF0 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF0(x)                          (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF0_SHIFT)) & LLWU_PF_WUF0_MASK)
+#define LLWU_PF_WUF1_MASK                        (0x2U)
+#define LLWU_PF_WUF1_SHIFT                       (1U)
+/*! WUF1 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF1(x)                          (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF1_SHIFT)) & LLWU_PF_WUF1_MASK)
+#define LLWU_PF_WUF2_MASK                        (0x4U)
+#define LLWU_PF_WUF2_SHIFT                       (2U)
+/*! WUF2 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF2(x)                          (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF2_SHIFT)) & LLWU_PF_WUF2_MASK)
+#define LLWU_PF_WUF3_MASK                        (0x8U)
+#define LLWU_PF_WUF3_SHIFT                       (3U)
+/*! WUF3 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF3(x)                          (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF3_SHIFT)) & LLWU_PF_WUF3_MASK)
+#define LLWU_PF_WUF4_MASK                        (0x10U)
+#define LLWU_PF_WUF4_SHIFT                       (4U)
+/*! WUF4 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF4(x)                          (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF4_SHIFT)) & LLWU_PF_WUF4_MASK)
+#define LLWU_PF_WUF5_MASK                        (0x20U)
+#define LLWU_PF_WUF5_SHIFT                       (5U)
+/*! WUF5 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF5(x)                          (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF5_SHIFT)) & LLWU_PF_WUF5_MASK)
+#define LLWU_PF_WUF6_MASK                        (0x40U)
+#define LLWU_PF_WUF6_SHIFT                       (6U)
+/*! WUF6 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF6(x)                          (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF6_SHIFT)) & LLWU_PF_WUF6_MASK)
+#define LLWU_PF_WUF7_MASK                        (0x80U)
+#define LLWU_PF_WUF7_SHIFT                       (7U)
+/*! WUF7 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF7(x)                          (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF7_SHIFT)) & LLWU_PF_WUF7_MASK)
+#define LLWU_PF_WUF8_MASK                        (0x100U)
+#define LLWU_PF_WUF8_SHIFT                       (8U)
+/*! WUF8 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF8(x)                          (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF8_SHIFT)) & LLWU_PF_WUF8_MASK)
+#define LLWU_PF_WUF9_MASK                        (0x200U)
+#define LLWU_PF_WUF9_SHIFT                       (9U)
+/*! WUF9 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF9(x)                          (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF9_SHIFT)) & LLWU_PF_WUF9_MASK)
+#define LLWU_PF_WUF10_MASK                       (0x400U)
+#define LLWU_PF_WUF10_SHIFT                      (10U)
+/*! WUF10 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF10(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF10_SHIFT)) & LLWU_PF_WUF10_MASK)
+#define LLWU_PF_WUF11_MASK                       (0x800U)
+#define LLWU_PF_WUF11_SHIFT                      (11U)
+/*! WUF11 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF11(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF11_SHIFT)) & LLWU_PF_WUF11_MASK)
+#define LLWU_PF_WUF12_MASK                       (0x1000U)
+#define LLWU_PF_WUF12_SHIFT                      (12U)
+/*! WUF12 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF12(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF12_SHIFT)) & LLWU_PF_WUF12_MASK)
+#define LLWU_PF_WUF13_MASK                       (0x2000U)
+#define LLWU_PF_WUF13_SHIFT                      (13U)
+/*! WUF13 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF13(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF13_SHIFT)) & LLWU_PF_WUF13_MASK)
+#define LLWU_PF_WUF14_MASK                       (0x4000U)
+#define LLWU_PF_WUF14_SHIFT                      (14U)
+/*! WUF14 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF14(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF14_SHIFT)) & LLWU_PF_WUF14_MASK)
+#define LLWU_PF_WUF15_MASK                       (0x8000U)
+#define LLWU_PF_WUF15_SHIFT                      (15U)
+/*! WUF15 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF15(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF15_SHIFT)) & LLWU_PF_WUF15_MASK)
+#define LLWU_PF_WUF16_MASK                       (0x10000U)
+#define LLWU_PF_WUF16_SHIFT                      (16U)
+/*! WUF16 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF16(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF16_SHIFT)) & LLWU_PF_WUF16_MASK)
+#define LLWU_PF_WUF17_MASK                       (0x20000U)
+#define LLWU_PF_WUF17_SHIFT                      (17U)
+/*! WUF17 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF17(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF17_SHIFT)) & LLWU_PF_WUF17_MASK)
+#define LLWU_PF_WUF18_MASK                       (0x40000U)
+#define LLWU_PF_WUF18_SHIFT                      (18U)
+/*! WUF18 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF18(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF18_SHIFT)) & LLWU_PF_WUF18_MASK)
+#define LLWU_PF_WUF19_MASK                       (0x80000U)
+#define LLWU_PF_WUF19_SHIFT                      (19U)
+/*! WUF19 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF19(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF19_SHIFT)) & LLWU_PF_WUF19_MASK)
+#define LLWU_PF_WUF20_MASK                       (0x100000U)
+#define LLWU_PF_WUF20_SHIFT                      (20U)
+/*! WUF20 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF20(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF20_SHIFT)) & LLWU_PF_WUF20_MASK)
+#define LLWU_PF_WUF21_MASK                       (0x200000U)
+#define LLWU_PF_WUF21_SHIFT                      (21U)
+/*! WUF21 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF21(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF21_SHIFT)) & LLWU_PF_WUF21_MASK)
+#define LLWU_PF_WUF22_MASK                       (0x400000U)
+#define LLWU_PF_WUF22_SHIFT                      (22U)
+/*! WUF22 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF22(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF22_SHIFT)) & LLWU_PF_WUF22_MASK)
+#define LLWU_PF_WUF23_MASK                       (0x800000U)
+#define LLWU_PF_WUF23_SHIFT                      (23U)
+/*! WUF23 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF23(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF23_SHIFT)) & LLWU_PF_WUF23_MASK)
+#define LLWU_PF_WUF24_MASK                       (0x1000000U)
+#define LLWU_PF_WUF24_SHIFT                      (24U)
+/*! WUF24 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF24(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF24_SHIFT)) & LLWU_PF_WUF24_MASK)
+#define LLWU_PF_WUF25_MASK                       (0x2000000U)
+#define LLWU_PF_WUF25_SHIFT                      (25U)
+/*! WUF25 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF25(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF25_SHIFT)) & LLWU_PF_WUF25_MASK)
+#define LLWU_PF_WUF26_MASK                       (0x4000000U)
+#define LLWU_PF_WUF26_SHIFT                      (26U)
+/*! WUF26 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF26(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF26_SHIFT)) & LLWU_PF_WUF26_MASK)
+#define LLWU_PF_Reserved27_MASK                  (0x8000000U)
+#define LLWU_PF_Reserved27_SHIFT                 (27U)
+/*! Reserved27 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_Reserved27(x)                    (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved27_SHIFT)) & LLWU_PF_Reserved27_MASK)
+#define LLWU_PF_Reserved28_MASK                  (0x10000000U)
+#define LLWU_PF_Reserved28_SHIFT                 (28U)
+/*! Reserved28 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_Reserved28(x)                    (((uint32_t)(((uint32_t)(x)) << LLWU_PF_Reserved28_SHIFT)) & LLWU_PF_Reserved28_MASK)
+#define LLWU_PF_WUF29_MASK                       (0x20000000U)
+#define LLWU_PF_WUF29_SHIFT                      (29U)
+/*! WUF29 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF29(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF29_SHIFT)) & LLWU_PF_WUF29_MASK)
+#define LLWU_PF_WUF30_MASK                       (0x40000000U)
+#define LLWU_PF_WUF30_SHIFT                      (30U)
+/*! WUF30 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF30(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF30_SHIFT)) & LLWU_PF_WUF30_MASK)
+#define LLWU_PF_WUF31_MASK                       (0x80000000U)
+#define LLWU_PF_WUF31_SHIFT                      (31U)
+/*! WUF31 - Wakeup flag for LLWU_Pn
+ *  0b0..LLWU_Pn input was not a wakeup source
+ *  0b1..LLWU_Pn input was a wakeup source
+ */
+#define LLWU_PF_WUF31(x)                         (((uint32_t)(((uint32_t)(x)) << LLWU_PF_WUF31_SHIFT)) & LLWU_PF_WUF31_MASK)
+/*! @} */
+
+/*! @name FILT - Pin Filter register */
+/*! @{ */
+#define LLWU_FILT_FILTSEL1_MASK                  (0x1FU)
+#define LLWU_FILT_FILTSEL1_SHIFT                 (0U)
+/*! FILTSEL1 - Filter 1 Pin Select
+ *  0b00000..Select LLWU_P0 for filter
+ *  0b11111..Select LLWU_P31 for filter
+ */
+#define LLWU_FILT_FILTSEL1(x)                    (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTSEL1_SHIFT)) & LLWU_FILT_FILTSEL1_MASK)
+#define LLWU_FILT_FILTE1_MASK                    (0x60U)
+#define LLWU_FILT_FILTE1_SHIFT                   (5U)
+/*! FILTE1 - Filter 1 Enable
+ *  0b00..Filter disabled
+ *  0b01..Filter posedge detect enabled when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..Filter negedge detect enabled when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..Filter any edge detect enabled when configured as interrupt/DMA request
+ */
+#define LLWU_FILT_FILTE1(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTE1_SHIFT)) & LLWU_FILT_FILTE1_MASK)
+#define LLWU_FILT_FILTF1_MASK                    (0x80U)
+#define LLWU_FILT_FILTF1_SHIFT                   (7U)
+/*! FILTF1 - Filter 1 Flag
+ *  0b0..Pin Filter 1 was not a wakeup source
+ *  0b1..Pin Filter 1 was a wakeup source
+ */
+#define LLWU_FILT_FILTF1(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTF1_SHIFT)) & LLWU_FILT_FILTF1_MASK)
+#define LLWU_FILT_FILTSEL2_MASK                  (0x1F00U)
+#define LLWU_FILT_FILTSEL2_SHIFT                 (8U)
+/*! FILTSEL2 - Filter 2 Pin Select
+ *  0b00000..Select LLWU_P0 for filter
+ *  0b11111..Select LLWU_P31 for filter
+ */
+#define LLWU_FILT_FILTSEL2(x)                    (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTSEL2_SHIFT)) & LLWU_FILT_FILTSEL2_MASK)
+#define LLWU_FILT_FILTE2_MASK                    (0x6000U)
+#define LLWU_FILT_FILTE2_SHIFT                   (13U)
+/*! FILTE2 - Filter 2 Enable
+ *  0b00..Filter disabled
+ *  0b01..Filter posedge detect enabled when configured as interrupt/DMA request or high level detection when configured as trigger request
+ *  0b10..Filter negedge detect enabled when configured as interrupt/DMA request or low level detection when configured as trigger request
+ *  0b11..Filter any edge detect enabled when configured as interrupt/DMA request
+ */
+#define LLWU_FILT_FILTE2(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTE2_SHIFT)) & LLWU_FILT_FILTE2_MASK)
+#define LLWU_FILT_FILTF2_MASK                    (0x8000U)
+#define LLWU_FILT_FILTF2_SHIFT                   (15U)
+/*! FILTF2 - Filter 2 Flag
+ *  0b0..Pin Filter 2 was not a wakeup source
+ *  0b1..Pin Filter 2 was a wakeup source
+ */
+#define LLWU_FILT_FILTF2(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_FILT_FILTF2_SHIFT)) & LLWU_FILT_FILTF2_MASK)
+/*! @} */
+
+/*! @name PDC1 - Pin DMA/Trigger Configuration 1 register */
+/*! @{ */
+#define LLWU_PDC1_WUPDC0_MASK                    (0x3U)
+#define LLWU_PDC1_WUPDC0_SHIFT                   (0U)
+/*! WUPDC0 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC0(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC0_SHIFT)) & LLWU_PDC1_WUPDC0_MASK)
+#define LLWU_PDC1_WUPDC1_MASK                    (0xCU)
+#define LLWU_PDC1_WUPDC1_SHIFT                   (2U)
+/*! WUPDC1 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC1(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC1_SHIFT)) & LLWU_PDC1_WUPDC1_MASK)
+#define LLWU_PDC1_WUPDC2_MASK                    (0x30U)
+#define LLWU_PDC1_WUPDC2_SHIFT                   (4U)
+/*! WUPDC2 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC2(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC2_SHIFT)) & LLWU_PDC1_WUPDC2_MASK)
+#define LLWU_PDC1_WUPDC3_MASK                    (0xC0U)
+#define LLWU_PDC1_WUPDC3_SHIFT                   (6U)
+/*! WUPDC3 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC3(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC3_SHIFT)) & LLWU_PDC1_WUPDC3_MASK)
+#define LLWU_PDC1_WUPDC4_MASK                    (0x300U)
+#define LLWU_PDC1_WUPDC4_SHIFT                   (8U)
+/*! WUPDC4 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC4(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC4_SHIFT)) & LLWU_PDC1_WUPDC4_MASK)
+#define LLWU_PDC1_WUPDC5_MASK                    (0xC00U)
+#define LLWU_PDC1_WUPDC5_SHIFT                   (10U)
+/*! WUPDC5 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC5(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC5_SHIFT)) & LLWU_PDC1_WUPDC5_MASK)
+#define LLWU_PDC1_WUPDC6_MASK                    (0x3000U)
+#define LLWU_PDC1_WUPDC6_SHIFT                   (12U)
+/*! WUPDC6 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC6(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC6_SHIFT)) & LLWU_PDC1_WUPDC6_MASK)
+#define LLWU_PDC1_WUPDC7_MASK                    (0xC000U)
+#define LLWU_PDC1_WUPDC7_SHIFT                   (14U)
+/*! WUPDC7 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC7(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC7_SHIFT)) & LLWU_PDC1_WUPDC7_MASK)
+#define LLWU_PDC1_WUPDC8_MASK                    (0x30000U)
+#define LLWU_PDC1_WUPDC8_SHIFT                   (16U)
+/*! WUPDC8 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC8(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC8_SHIFT)) & LLWU_PDC1_WUPDC8_MASK)
+#define LLWU_PDC1_WUPDC9_MASK                    (0xC0000U)
+#define LLWU_PDC1_WUPDC9_SHIFT                   (18U)
+/*! WUPDC9 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC9(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC9_SHIFT)) & LLWU_PDC1_WUPDC9_MASK)
+#define LLWU_PDC1_WUPDC10_MASK                   (0x300000U)
+#define LLWU_PDC1_WUPDC10_SHIFT                  (20U)
+/*! WUPDC10 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC10(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC10_SHIFT)) & LLWU_PDC1_WUPDC10_MASK)
+#define LLWU_PDC1_WUPDC11_MASK                   (0xC00000U)
+#define LLWU_PDC1_WUPDC11_SHIFT                  (22U)
+/*! WUPDC11 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC11(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC11_SHIFT)) & LLWU_PDC1_WUPDC11_MASK)
+#define LLWU_PDC1_WUPDC12_MASK                   (0x3000000U)
+#define LLWU_PDC1_WUPDC12_SHIFT                  (24U)
+/*! WUPDC12 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC12(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC12_SHIFT)) & LLWU_PDC1_WUPDC12_MASK)
+#define LLWU_PDC1_WUPDC13_MASK                   (0xC000000U)
+#define LLWU_PDC1_WUPDC13_SHIFT                  (26U)
+/*! WUPDC13 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC13(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC13_SHIFT)) & LLWU_PDC1_WUPDC13_MASK)
+#define LLWU_PDC1_WUPDC14_MASK                   (0x30000000U)
+#define LLWU_PDC1_WUPDC14_SHIFT                  (28U)
+/*! WUPDC14 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC14(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC14_SHIFT)) & LLWU_PDC1_WUPDC14_MASK)
+#define LLWU_PDC1_WUPDC15_MASK                   (0xC0000000U)
+#define LLWU_PDC1_WUPDC15_SHIFT                  (30U)
+/*! WUPDC15 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC1_WUPDC15(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC1_WUPDC15_SHIFT)) & LLWU_PDC1_WUPDC15_MASK)
+/*! @} */
+
+/*! @name PDC2 - Pin DMA/Trigger Configuration 2 register */
+/*! @{ */
+#define LLWU_PDC2_WUPDC16_MASK                   (0x3U)
+#define LLWU_PDC2_WUPDC16_SHIFT                  (0U)
+/*! WUPDC16 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC16(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC16_SHIFT)) & LLWU_PDC2_WUPDC16_MASK)
+#define LLWU_PDC2_WUPDC17_MASK                   (0xCU)
+#define LLWU_PDC2_WUPDC17_SHIFT                  (2U)
+/*! WUPDC17 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC17(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC17_SHIFT)) & LLWU_PDC2_WUPDC17_MASK)
+#define LLWU_PDC2_WUPDC18_MASK                   (0x30U)
+#define LLWU_PDC2_WUPDC18_SHIFT                  (4U)
+/*! WUPDC18 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC18(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC18_SHIFT)) & LLWU_PDC2_WUPDC18_MASK)
+#define LLWU_PDC2_WUPDC19_MASK                   (0xC0U)
+#define LLWU_PDC2_WUPDC19_SHIFT                  (6U)
+/*! WUPDC19 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC19(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC19_SHIFT)) & LLWU_PDC2_WUPDC19_MASK)
+#define LLWU_PDC2_WUPDC20_MASK                   (0x300U)
+#define LLWU_PDC2_WUPDC20_SHIFT                  (8U)
+/*! WUPDC20 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC20(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC20_SHIFT)) & LLWU_PDC2_WUPDC20_MASK)
+#define LLWU_PDC2_WUPDC21_MASK                   (0xC00U)
+#define LLWU_PDC2_WUPDC21_SHIFT                  (10U)
+/*! WUPDC21 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC21(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC21_SHIFT)) & LLWU_PDC2_WUPDC21_MASK)
+#define LLWU_PDC2_WUPDC22_MASK                   (0x3000U)
+#define LLWU_PDC2_WUPDC22_SHIFT                  (12U)
+/*! WUPDC22 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC22(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC22_SHIFT)) & LLWU_PDC2_WUPDC22_MASK)
+#define LLWU_PDC2_WUPDC23_MASK                   (0xC000U)
+#define LLWU_PDC2_WUPDC23_SHIFT                  (14U)
+/*! WUPDC23 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC23(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC23_SHIFT)) & LLWU_PDC2_WUPDC23_MASK)
+#define LLWU_PDC2_WUPDC24_MASK                   (0x30000U)
+#define LLWU_PDC2_WUPDC24_SHIFT                  (16U)
+/*! WUPDC24 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC24(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC24_SHIFT)) & LLWU_PDC2_WUPDC24_MASK)
+#define LLWU_PDC2_WUPDC25_MASK                   (0xC0000U)
+#define LLWU_PDC2_WUPDC25_SHIFT                  (18U)
+/*! WUPDC25 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC25(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC25_SHIFT)) & LLWU_PDC2_WUPDC25_MASK)
+#define LLWU_PDC2_WUPDC26_MASK                   (0x300000U)
+#define LLWU_PDC2_WUPDC26_SHIFT                  (20U)
+/*! WUPDC26 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC26(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC26_SHIFT)) & LLWU_PDC2_WUPDC26_MASK)
+#define LLWU_PDC2_Reserved27_MASK                (0xC00000U)
+#define LLWU_PDC2_Reserved27_SHIFT               (22U)
+/*! Reserved27 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_Reserved27(x)                  (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_Reserved27_SHIFT)) & LLWU_PDC2_Reserved27_MASK)
+#define LLWU_PDC2_Reserved28_MASK                (0x3000000U)
+#define LLWU_PDC2_Reserved28_SHIFT               (24U)
+/*! Reserved28 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_Reserved28(x)                  (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_Reserved28_SHIFT)) & LLWU_PDC2_Reserved28_MASK)
+#define LLWU_PDC2_WUPDC29_MASK                   (0xC000000U)
+#define LLWU_PDC2_WUPDC29_SHIFT                  (26U)
+/*! WUPDC29 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC29(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC29_SHIFT)) & LLWU_PDC2_WUPDC29_MASK)
+#define LLWU_PDC2_WUPDC30_MASK                   (0x30000000U)
+#define LLWU_PDC2_WUPDC30_SHIFT                  (28U)
+/*! WUPDC30 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC30(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC30_SHIFT)) & LLWU_PDC2_WUPDC30_MASK)
+#define LLWU_PDC2_WUPDC31_MASK                   (0xC0000000U)
+#define LLWU_PDC2_WUPDC31_SHIFT                  (30U)
+/*! WUPDC31 - Wakeup pin configuration for LLWU_Pn
+ *  0b00..External input pin configured as interrupt
+ *  0b01..External input pin configured as DMA request
+ *  0b10..External input pin configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_PDC2_WUPDC31(x)                     (((uint32_t)(((uint32_t)(x)) << LLWU_PDC2_WUPDC31_SHIFT)) & LLWU_PDC2_WUPDC31_MASK)
+/*! @} */
+
+/*! @name FDC - Pin Filter DMA/Trigger Configuration register */
+/*! @{ */
+#define LLWU_FDC_FILTC1_MASK                     (0x3U)
+#define LLWU_FDC_FILTC1_SHIFT                    (0U)
+/*! FILTC1 - Filter configuration for FILT1
+ *  0b00..Filter output configured as interrupt
+ *  0b01..Filter output configured as DMA request
+ *  0b10..Filter output configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_FDC_FILTC1(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_FDC_FILTC1_SHIFT)) & LLWU_FDC_FILTC1_MASK)
+#define LLWU_FDC_FILTC2_MASK                     (0xCU)
+#define LLWU_FDC_FILTC2_SHIFT                    (2U)
+/*! FILTC2 - Filter configuration for FILT2
+ *  0b00..Filter output configured as interrupt
+ *  0b01..Filter output configured as DMA request
+ *  0b10..Filter output configured as trigger event
+ *  0b11..Reserved
+ */
+#define LLWU_FDC_FILTC2(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_FDC_FILTC2_SHIFT)) & LLWU_FDC_FILTC2_MASK)
+/*! @} */
+
+/*! @name PMC - Pin Mode Configuration register */
+/*! @{ */
+#define LLWU_PMC_WUPMC0_MASK                     (0x1U)
+#define LLWU_PMC_WUPMC0_SHIFT                    (0U)
+/*! WUPMC0 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC0(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC0_SHIFT)) & LLWU_PMC_WUPMC0_MASK)
+#define LLWU_PMC_WUPMC1_MASK                     (0x2U)
+#define LLWU_PMC_WUPMC1_SHIFT                    (1U)
+/*! WUPMC1 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC1(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC1_SHIFT)) & LLWU_PMC_WUPMC1_MASK)
+#define LLWU_PMC_WUPMC2_MASK                     (0x4U)
+#define LLWU_PMC_WUPMC2_SHIFT                    (2U)
+/*! WUPMC2 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC2(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC2_SHIFT)) & LLWU_PMC_WUPMC2_MASK)
+#define LLWU_PMC_WUPMC3_MASK                     (0x8U)
+#define LLWU_PMC_WUPMC3_SHIFT                    (3U)
+/*! WUPMC3 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC3(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC3_SHIFT)) & LLWU_PMC_WUPMC3_MASK)
+#define LLWU_PMC_WUPMC4_MASK                     (0x10U)
+#define LLWU_PMC_WUPMC4_SHIFT                    (4U)
+/*! WUPMC4 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC4(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC4_SHIFT)) & LLWU_PMC_WUPMC4_MASK)
+#define LLWU_PMC_WUPMC5_MASK                     (0x20U)
+#define LLWU_PMC_WUPMC5_SHIFT                    (5U)
+/*! WUPMC5 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC5(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC5_SHIFT)) & LLWU_PMC_WUPMC5_MASK)
+#define LLWU_PMC_WUPMC6_MASK                     (0x40U)
+#define LLWU_PMC_WUPMC6_SHIFT                    (6U)
+/*! WUPMC6 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC6(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC6_SHIFT)) & LLWU_PMC_WUPMC6_MASK)
+#define LLWU_PMC_WUPMC7_MASK                     (0x80U)
+#define LLWU_PMC_WUPMC7_SHIFT                    (7U)
+/*! WUPMC7 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC7(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC7_SHIFT)) & LLWU_PMC_WUPMC7_MASK)
+#define LLWU_PMC_WUPMC8_MASK                     (0x100U)
+#define LLWU_PMC_WUPMC8_SHIFT                    (8U)
+/*! WUPMC8 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC8(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC8_SHIFT)) & LLWU_PMC_WUPMC8_MASK)
+#define LLWU_PMC_WUPMC9_MASK                     (0x200U)
+#define LLWU_PMC_WUPMC9_SHIFT                    (9U)
+/*! WUPMC9 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC9(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC9_SHIFT)) & LLWU_PMC_WUPMC9_MASK)
+#define LLWU_PMC_WUPMC10_MASK                    (0x400U)
+#define LLWU_PMC_WUPMC10_SHIFT                   (10U)
+/*! WUPMC10 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC10(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC10_SHIFT)) & LLWU_PMC_WUPMC10_MASK)
+#define LLWU_PMC_WUPMC11_MASK                    (0x800U)
+#define LLWU_PMC_WUPMC11_SHIFT                   (11U)
+/*! WUPMC11 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC11(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC11_SHIFT)) & LLWU_PMC_WUPMC11_MASK)
+#define LLWU_PMC_WUPMC12_MASK                    (0x1000U)
+#define LLWU_PMC_WUPMC12_SHIFT                   (12U)
+/*! WUPMC12 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC12(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC12_SHIFT)) & LLWU_PMC_WUPMC12_MASK)
+#define LLWU_PMC_WUPMC13_MASK                    (0x2000U)
+#define LLWU_PMC_WUPMC13_SHIFT                   (13U)
+/*! WUPMC13 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC13(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC13_SHIFT)) & LLWU_PMC_WUPMC13_MASK)
+#define LLWU_PMC_WUPMC14_MASK                    (0x4000U)
+#define LLWU_PMC_WUPMC14_SHIFT                   (14U)
+/*! WUPMC14 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC14(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC14_SHIFT)) & LLWU_PMC_WUPMC14_MASK)
+#define LLWU_PMC_WUPMC15_MASK                    (0x8000U)
+#define LLWU_PMC_WUPMC15_SHIFT                   (15U)
+/*! WUPMC15 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC15(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC15_SHIFT)) & LLWU_PMC_WUPMC15_MASK)
+#define LLWU_PMC_WUPMC16_MASK                    (0x10000U)
+#define LLWU_PMC_WUPMC16_SHIFT                   (16U)
+/*! WUPMC16 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC16(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC16_SHIFT)) & LLWU_PMC_WUPMC16_MASK)
+#define LLWU_PMC_WUPMC17_MASK                    (0x20000U)
+#define LLWU_PMC_WUPMC17_SHIFT                   (17U)
+/*! WUPMC17 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC17(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC17_SHIFT)) & LLWU_PMC_WUPMC17_MASK)
+#define LLWU_PMC_WUPMC18_MASK                    (0x40000U)
+#define LLWU_PMC_WUPMC18_SHIFT                   (18U)
+/*! WUPMC18 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC18(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC18_SHIFT)) & LLWU_PMC_WUPMC18_MASK)
+#define LLWU_PMC_WUPMC19_MASK                    (0x80000U)
+#define LLWU_PMC_WUPMC19_SHIFT                   (19U)
+/*! WUPMC19 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC19(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC19_SHIFT)) & LLWU_PMC_WUPMC19_MASK)
+#define LLWU_PMC_WUPMC20_MASK                    (0x100000U)
+#define LLWU_PMC_WUPMC20_SHIFT                   (20U)
+/*! WUPMC20 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC20(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC20_SHIFT)) & LLWU_PMC_WUPMC20_MASK)
+#define LLWU_PMC_WUPMC21_MASK                    (0x200000U)
+#define LLWU_PMC_WUPMC21_SHIFT                   (21U)
+/*! WUPMC21 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC21(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC21_SHIFT)) & LLWU_PMC_WUPMC21_MASK)
+#define LLWU_PMC_WUPMC22_MASK                    (0x400000U)
+#define LLWU_PMC_WUPMC22_SHIFT                   (22U)
+/*! WUPMC22 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC22(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC22_SHIFT)) & LLWU_PMC_WUPMC22_MASK)
+#define LLWU_PMC_WUPMC23_MASK                    (0x800000U)
+#define LLWU_PMC_WUPMC23_SHIFT                   (23U)
+/*! WUPMC23 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC23(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC23_SHIFT)) & LLWU_PMC_WUPMC23_MASK)
+#define LLWU_PMC_WUPMC24_MASK                    (0x1000000U)
+#define LLWU_PMC_WUPMC24_SHIFT                   (24U)
+/*! WUPMC24 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC24(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC24_SHIFT)) & LLWU_PMC_WUPMC24_MASK)
+#define LLWU_PMC_WUPMC25_MASK                    (0x2000000U)
+#define LLWU_PMC_WUPMC25_SHIFT                   (25U)
+/*! WUPMC25 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC25(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC25_SHIFT)) & LLWU_PMC_WUPMC25_MASK)
+#define LLWU_PMC_WUPMC26_MASK                    (0x4000000U)
+#define LLWU_PMC_WUPMC26_SHIFT                   (26U)
+/*! WUPMC26 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC26(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC26_SHIFT)) & LLWU_PMC_WUPMC26_MASK)
+#define LLWU_PMC_Reserved27_MASK                 (0x8000000U)
+#define LLWU_PMC_Reserved27_SHIFT                (27U)
+/*! Reserved27 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_Reserved27(x)                   (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_Reserved27_SHIFT)) & LLWU_PMC_Reserved27_MASK)
+#define LLWU_PMC_Reserved28_MASK                 (0x10000000U)
+#define LLWU_PMC_Reserved28_SHIFT                (28U)
+/*! Reserved28 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_Reserved28(x)                   (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_Reserved28_SHIFT)) & LLWU_PMC_Reserved28_MASK)
+#define LLWU_PMC_WUPMC29_MASK                    (0x20000000U)
+#define LLWU_PMC_WUPMC29_SHIFT                   (29U)
+/*! WUPMC29 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC29(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC29_SHIFT)) & LLWU_PMC_WUPMC29_MASK)
+#define LLWU_PMC_WUPMC30_MASK                    (0x40000000U)
+#define LLWU_PMC_WUPMC30_SHIFT                   (30U)
+/*! WUPMC30 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC30(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC30_SHIFT)) & LLWU_PMC_WUPMC30_MASK)
+#define LLWU_PMC_WUPMC31_MASK                    (0x80000000U)
+#define LLWU_PMC_WUPMC31_SHIFT                   (31U)
+/*! WUPMC31 - Wakeup pin mode for LLWU_Pn
+ *  0b0..External input pin detection active only during LLS/VLLS mode
+ *  0b1..External input pin detection active during all power modes
+ */
+#define LLWU_PMC_WUPMC31(x)                      (((uint32_t)(((uint32_t)(x)) << LLWU_PMC_WUPMC31_SHIFT)) & LLWU_PMC_WUPMC31_MASK)
+/*! @} */
+
+/*! @name FMC - Pin Filter Mode Configuration register */
+/*! @{ */
+#define LLWU_FMC_FILTM1_MASK                     (0x1U)
+#define LLWU_FMC_FILTM1_SHIFT                    (0U)
+/*! FILTM1 - Filter Mode for FILT1
+ *  0b0..External input pin filter detection active only during LLS/VLLS mode
+ *  0b1..External input pin filter detection active during all power modes
+ */
+#define LLWU_FMC_FILTM1(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_FMC_FILTM1_SHIFT)) & LLWU_FMC_FILTM1_MASK)
+#define LLWU_FMC_FILTM2_MASK                     (0x2U)
+#define LLWU_FMC_FILTM2_SHIFT                    (1U)
+/*! FILTM2 - Filter Mode for FILT2
+ *  0b0..External input pin filter detection active only during LLS/VLLS mode
+ *  0b1..External input pin filter detection active during all power modes
+ */
+#define LLWU_FMC_FILTM2(x)                       (((uint32_t)(((uint32_t)(x)) << LLWU_FMC_FILTM2_SHIFT)) & LLWU_FMC_FILTM2_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU0 base address */
+#define LLWU0_BASE                               (0x40024000u)
+/** Peripheral LLWU0 base pointer */
+#define LLWU0                                    ((LLWU_Type *)LLWU0_BASE)
+/** Peripheral LLWU1 base address */
+#define LLWU1_BASE                               (0x41023000u)
+/** Peripheral LLWU1 base pointer */
+#define LLWU1                                    ((LLWU_Type *)LLWU1_BASE)
+/** Array initializer of LLWU peripheral base addresses */
+#define LLWU_BASE_ADDRS                          { LLWU0_BASE, LLWU1_BASE }
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASE_PTRS                           { LLWU0, LLWU1 }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS                                { NotAvail_IRQn, LLWU1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPCMP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPCMP_Peripheral_Access_Layer LPCMP Peripheral Access Layer
+ * @{
+ */
+
+/** LPCMP - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __IO uint32_t CCR0;                              /**< Comparator Control Register 0, offset: 0x8 */
+  __IO uint32_t CCR1;                              /**< Comparator Control Register 1, offset: 0xC */
+  __IO uint32_t CCR2;                              /**< Comparator Control Register 2, offset: 0x10 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t DCR;                               /**< DAC Control Register, offset: 0x18 */
+  __IO uint32_t IER;                               /**< Interrupt Enable Register, offset: 0x1C */
+  __IO uint32_t CSR;                               /**< Comparator Status Register, offset: 0x20 */
+} LPCMP_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPCMP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPCMP_Register_Masks LPCMP Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define LPCMP_VERID_FEATURE_MASK                 (0xFFFFU)
+#define LPCMP_VERID_FEATURE_SHIFT                (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000000000001..Round robin feature
+ */
+#define LPCMP_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_FEATURE_SHIFT)) & LPCMP_VERID_FEATURE_MASK)
+#define LPCMP_VERID_MINOR_MASK                   (0xFF0000U)
+#define LPCMP_VERID_MINOR_SHIFT                  (16U)
+#define LPCMP_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MINOR_SHIFT)) & LPCMP_VERID_MINOR_MASK)
+#define LPCMP_VERID_MAJOR_MASK                   (0xFF000000U)
+#define LPCMP_VERID_MAJOR_SHIFT                  (24U)
+#define LPCMP_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MAJOR_SHIFT)) & LPCMP_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define LPCMP_PARAM_DAC_RES_MASK                 (0xFU)
+#define LPCMP_PARAM_DAC_RES_SHIFT                (0U)
+/*! DAC_RES - DAC resolution
+ *  0b0000..4 bit DAC
+ *  0b0001..6 bit DAC
+ *  0b0010..8 bit DAC
+ *  0b0011..10 bit DAC
+ *  0b0100..12 bit DAC
+ *  0b0101..14 bit DAC
+ *  0b0110..16 bit DAC
+ */
+#define LPCMP_PARAM_DAC_RES(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_PARAM_DAC_RES_SHIFT)) & LPCMP_PARAM_DAC_RES_MASK)
+/*! @} */
+
+/*! @name CCR0 - Comparator Control Register 0 */
+/*! @{ */
+#define LPCMP_CCR0_CMP_EN_MASK                   (0x1U)
+#define LPCMP_CCR0_CMP_EN_SHIFT                  (0U)
+/*! CMP_EN - Comparator Module Enable
+ *  0b0..Analog Comparator is disabled.
+ *  0b1..Analog Comparator is enabled.
+ */
+#define LPCMP_CCR0_CMP_EN(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_EN_SHIFT)) & LPCMP_CCR0_CMP_EN_MASK)
+#define LPCMP_CCR0_CMP_STOP_EN_MASK              (0x2U)
+#define LPCMP_CCR0_CMP_STOP_EN_SHIFT             (1U)
+/*! CMP_STOP_EN - Comparator Module STOP Mode Enable
+ *  0b0..Comparator is disabled in STOP modes regardless of CMP_EN.
+ *  0b1..Comparator is enabled in STOP mode if CMP_EN is active
+ */
+#define LPCMP_CCR0_CMP_STOP_EN(x)                (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_STOP_EN_SHIFT)) & LPCMP_CCR0_CMP_STOP_EN_MASK)
+/*! @} */
+
+/*! @name CCR1 - Comparator Control Register 1 */
+/*! @{ */
+#define LPCMP_CCR1_WINDOW_EN_MASK                (0x1U)
+#define LPCMP_CCR1_WINDOW_EN_SHIFT               (0U)
+/*! WINDOW_EN - Windowing Enable
+ *  0b0..Windowing mode is not selected.
+ *  0b1..Windowing mode is selected.
+ */
+#define LPCMP_CCR1_WINDOW_EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_EN_SHIFT)) & LPCMP_CCR1_WINDOW_EN_MASK)
+#define LPCMP_CCR1_SAMPLE_EN_MASK                (0x2U)
+#define LPCMP_CCR1_SAMPLE_EN_SHIFT               (1U)
+/*! SAMPLE_EN - Sample Enable
+ *  0b0..Sampling mode is not selected.
+ *  0b1..Sampling mode is selected.
+ */
+#define LPCMP_CCR1_SAMPLE_EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_SAMPLE_EN_SHIFT)) & LPCMP_CCR1_SAMPLE_EN_MASK)
+#define LPCMP_CCR1_DMA_EN_MASK                   (0x4U)
+#define LPCMP_CCR1_DMA_EN_SHIFT                  (2U)
+/*! DMA_EN - DMA Enable
+ *  0b0..DMA is disabled.
+ *  0b1..DMA is enabled.
+ */
+#define LPCMP_CCR1_DMA_EN(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_DMA_EN_SHIFT)) & LPCMP_CCR1_DMA_EN_MASK)
+#define LPCMP_CCR1_COUT_INV_MASK                 (0x8U)
+#define LPCMP_CCR1_COUT_INV_SHIFT                (3U)
+/*! COUT_INV - Comparator invert
+ *  0b0..Does not invert the comparator output.
+ *  0b1..Inverts the comparator output.
+ */
+#define LPCMP_CCR1_COUT_INV(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_INV_SHIFT)) & LPCMP_CCR1_COUT_INV_MASK)
+#define LPCMP_CCR1_COUT_SEL_MASK                 (0x10U)
+#define LPCMP_CCR1_COUT_SEL_SHIFT                (4U)
+/*! COUT_SEL - Comparator Output Select
+ *  0b0..Set CMPO to equal COUT (filtered comparator output).
+ *  0b1..Set CMPO to equal COUTA (unfiltered comparator output).
+ */
+#define LPCMP_CCR1_COUT_SEL(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_SEL_SHIFT)) & LPCMP_CCR1_COUT_SEL_MASK)
+#define LPCMP_CCR1_COUT_PEN_MASK                 (0x20U)
+#define LPCMP_CCR1_COUT_PEN_SHIFT                (5U)
+/*! COUT_PEN - Comparator Output Pin Enable
+ *  0b0..When COUT_PEN is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin.
+ *  0b1..When COUT_PEN is 1, and if the software has configured the comparator to own a packaged pin, the comparator output is available in a packaged pin.
+ */
+#define LPCMP_CCR1_COUT_PEN(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_PEN_SHIFT)) & LPCMP_CCR1_COUT_PEN_MASK)
+#define LPCMP_CCR1_FILT_CNT_MASK                 (0x70000U)
+#define LPCMP_CCR1_FILT_CNT_SHIFT                (16U)
+/*! FILT_CNT - Filter Sample Count
+ *  0b000..Filter is disabled. If SAMPLE_EN = 1, then COUT is a logic zero (this is not a legal state in , and is not recommended). If SAMPLE_EN = 0, COUT = COUTA.
+ *  0b001..1 consecutive sample must agree (comparator output is simply sampled).
+ *  0b010..2 consecutive samples must agree.
+ *  0b011..3 consecutive samples must agree.
+ *  0b100..4 consecutive samples must agree.
+ *  0b101..5 consecutive samples must agree.
+ *  0b110..6 consecutive samples must agree.
+ *  0b111..7 consecutive samples must agree.
+ */
+#define LPCMP_CCR1_FILT_CNT(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_CNT_SHIFT)) & LPCMP_CCR1_FILT_CNT_MASK)
+#define LPCMP_CCR1_FILT_PER_MASK                 (0xFF000000U)
+#define LPCMP_CCR1_FILT_PER_SHIFT                (24U)
+#define LPCMP_CCR1_FILT_PER(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_PER_SHIFT)) & LPCMP_CCR1_FILT_PER_MASK)
+/*! @} */
+
+/*! @name CCR2 - Comparator Control Register 2 */
+/*! @{ */
+#define LPCMP_CCR2_CMP_HPMD_MASK                 (0x1U)
+#define LPCMP_CCR2_CMP_HPMD_SHIFT                (0U)
+/*! CMP_HPMD - CMP High Power Mode Select
+ *  0b0..Low speed comparison mode is selected.(when CMP_NPMD is 0)
+ *  0b1..High speed comparison mode is selected.(when CMP_NPMD is 0)
+ */
+#define LPCMP_CCR2_CMP_HPMD(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_HPMD_SHIFT)) & LPCMP_CCR2_CMP_HPMD_MASK)
+#define LPCMP_CCR2_CMP_NPMD_MASK                 (0x2U)
+#define LPCMP_CCR2_CMP_NPMD_SHIFT                (1U)
+/*! CMP_NPMD - CMP Nano Power Mode Select
+ *  0b0..Nano Power Comparator is not enabled (mode is determined by CMP_HPMD)
+ *  0b1..Nano Power Comparator is enabled
+ */
+#define LPCMP_CCR2_CMP_NPMD(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_NPMD_SHIFT)) & LPCMP_CCR2_CMP_NPMD_MASK)
+#define LPCMP_CCR2_HYSTCTR_MASK                  (0x30U)
+#define LPCMP_CCR2_HYSTCTR_SHIFT                 (4U)
+/*! HYSTCTR - Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level
+ *  0b00..The hard block output has level 0 hysteresis internally.
+ *  0b01..The hard block output has level 1 hysteresis internally.
+ *  0b10..The hard block output has level 2 hysteresis internally.
+ *  0b11..The hard block output has level 3 hysteresis internally.
+ */
+#define LPCMP_CCR2_HYSTCTR(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_HYSTCTR_SHIFT)) & LPCMP_CCR2_HYSTCTR_MASK)
+#define LPCMP_CCR2_PSEL_MASK                     (0x70000U)
+#define LPCMP_CCR2_PSEL_SHIFT                    (16U)
+/*! PSEL - Plus Input MUX Control
+ *  0b000..Input 0
+ *  0b001..Input 1
+ *  0b010..Input 2
+ *  0b011..Input 3
+ *  0b100..Input 4
+ *  0b101..Input 5
+ *  0b110..Input 6
+ *  0b111..Internal DAC output
+ */
+#define LPCMP_CCR2_PSEL(x)                       (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_PSEL_SHIFT)) & LPCMP_CCR2_PSEL_MASK)
+#define LPCMP_CCR2_MSEL_MASK                     (0x700000U)
+#define LPCMP_CCR2_MSEL_SHIFT                    (20U)
+/*! MSEL - Minus Input MUX Control
+ *  0b000..Input 0
+ *  0b001..Input 1
+ *  0b010..Input 2
+ *  0b011..Input 3
+ *  0b100..Input 4
+ *  0b101..Input 5
+ *  0b110..Input 6
+ *  0b111..Internal DAC output
+ */
+#define LPCMP_CCR2_MSEL(x)                       (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_MSEL_SHIFT)) & LPCMP_CCR2_MSEL_MASK)
+/*! @} */
+
+/*! @name DCR - DAC Control Register */
+/*! @{ */
+#define LPCMP_DCR_DAC_EN_MASK                    (0x1U)
+#define LPCMP_DCR_DAC_EN_SHIFT                   (0U)
+/*! DAC_EN - DAC Enable
+ *  0b0..DAC is disabled.
+ *  0b1..DAC is enabled.
+ */
+#define LPCMP_DCR_DAC_EN(x)                      (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_EN_SHIFT)) & LPCMP_DCR_DAC_EN_MASK)
+#define LPCMP_DCR_DAC_HPMD_MASK                  (0x2U)
+#define LPCMP_DCR_DAC_HPMD_SHIFT                 (1U)
+/*! DAC_HPMD - DAC High Power Mode Select
+ *  0b0..DAC high power mode is not enabled.
+ *  0b1..DAC high power mode is enabled.
+ */
+#define LPCMP_DCR_DAC_HPMD(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_HPMD_SHIFT)) & LPCMP_DCR_DAC_HPMD_MASK)
+#define LPCMP_DCR_VRSEL_MASK                     (0x100U)
+#define LPCMP_DCR_VRSEL_SHIFT                    (8U)
+/*! VRSEL - Supply Voltage Reference Source Select
+ *  0b0..vrefh_int is selected as resistor ladder network supply reference Vin.
+ *  0b1..vrefh_ext is selected as resistor ladder network supply reference Vin.
+ */
+#define LPCMP_DCR_VRSEL(x)                       (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_VRSEL_SHIFT)) & LPCMP_DCR_VRSEL_MASK)
+#define LPCMP_DCR_DAC_DATA_MASK                  (0x3F0000U)
+#define LPCMP_DCR_DAC_DATA_SHIFT                 (16U)
+#define LPCMP_DCR_DAC_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_DATA_SHIFT)) & LPCMP_DCR_DAC_DATA_MASK)
+/*! @} */
+
+/*! @name IER - Interrupt Enable Register */
+/*! @{ */
+#define LPCMP_IER_CFR_IE_MASK                    (0x1U)
+#define LPCMP_IER_CFR_IE_SHIFT                   (0U)
+/*! CFR_IE - Comparator Flag Rising Interrupt Enable
+ *  0b0..CFR interrupt is disabled.
+ *  0b1..CFR interrupt is enabled.
+ */
+#define LPCMP_IER_CFR_IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFR_IE_SHIFT)) & LPCMP_IER_CFR_IE_MASK)
+#define LPCMP_IER_CFF_IE_MASK                    (0x2U)
+#define LPCMP_IER_CFF_IE_SHIFT                   (1U)
+/*! CFF_IE - Comparator Flag Falling Interrupt Enable
+ *  0b0..CFF interrupt is disabled.
+ *  0b1..CFF interrupt is enabled.
+ */
+#define LPCMP_IER_CFF_IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFF_IE_SHIFT)) & LPCMP_IER_CFF_IE_MASK)
+/*! @} */
+
+/*! @name CSR - Comparator Status Register */
+/*! @{ */
+#define LPCMP_CSR_CFR_MASK                       (0x1U)
+#define LPCMP_CSR_CFR_SHIFT                      (0U)
+/*! CFR - Analog Comparator Flag Rising
+ *  0b0..A rising edge has not been detected on COUT.
+ *  0b1..A rising edge on COUT has occurred.
+ */
+#define LPCMP_CSR_CFR(x)                         (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFR_SHIFT)) & LPCMP_CSR_CFR_MASK)
+#define LPCMP_CSR_CFF_MASK                       (0x2U)
+#define LPCMP_CSR_CFF_SHIFT                      (1U)
+/*! CFF - Analog Comparator Flag Falling
+ *  0b0..A falling edge has not been detected on COUT.
+ *  0b1..A falling edge on COUT has occurred.
+ */
+#define LPCMP_CSR_CFF(x)                         (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFF_SHIFT)) & LPCMP_CSR_CFF_MASK)
+#define LPCMP_CSR_COUT_MASK                      (0x100U)
+#define LPCMP_CSR_COUT_SHIFT                     (8U)
+#define LPCMP_CSR_COUT(x)                        (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_COUT_SHIFT)) & LPCMP_CSR_COUT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LPCMP_Register_Masks */
+
+
+/* LPCMP - Peripheral instance base addresses */
+/** Peripheral LPCMP0 base address */
+#define LPCMP0_BASE                              (0x4004B000u)
+/** Peripheral LPCMP0 base pointer */
+#define LPCMP0                                   ((LPCMP_Type *)LPCMP0_BASE)
+/** Peripheral LPCMP1 base address */
+#define LPCMP1_BASE                              (0x41038000u)
+/** Peripheral LPCMP1 base pointer */
+#define LPCMP1                                   ((LPCMP_Type *)LPCMP1_BASE)
+/** Array initializer of LPCMP peripheral base addresses */
+#define LPCMP_BASE_ADDRS                         { LPCMP0_BASE, LPCMP1_BASE }
+/** Array initializer of LPCMP peripheral base pointers */
+#define LPCMP_BASE_PTRS                          { LPCMP0, LPCMP1 }
+/** Interrupt vectors for the LPCMP peripheral type */
+#define LPCMP_IRQS                               { LPCMP0_IRQn, LPCMP1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPCMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPDAC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPDAC_Peripheral_Access_Layer LPDAC Peripheral Access Layer
+ * @{
+ */
+
+/** LPDAC - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version Identifier Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __O  uint32_t DATA;                              /**< DAC Data Register, offset: 0x8 */
+  __IO uint32_t GCR;                               /**< DAC Global Control Register, offset: 0xC */
+  __IO uint32_t FCR;                               /**< DAC FIFO Control Register, offset: 0x10 */
+  __I  uint32_t FPR;                               /**< DAC FIFO Pointer Register, offset: 0x14 */
+  __IO uint32_t FSR;                               /**< FIFO Status Register, offset: 0x18 */
+  __IO uint32_t IER;                               /**< DAC Interrupt Enable Register, offset: 0x1C */
+  __IO uint32_t DER;                               /**< DAC DMA Enable Register, offset: 0x20 */
+  __IO uint32_t RCR;                               /**< DAC Reset Control Register, offset: 0x24 */
+  __O  uint32_t TCR;                               /**< DAC Trigger Control Register, offset: 0x28 */
+} LPDAC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPDAC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPDAC_Register_Masks LPDAC Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version Identifier Register */
+/*! @{ */
+#define LPDAC_VERID_FEATURE_MASK                 (0xFFFFU)
+#define LPDAC_VERID_FEATURE_SHIFT                (0U)
+#define LPDAC_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_FEATURE_SHIFT)) & LPDAC_VERID_FEATURE_MASK)
+#define LPDAC_VERID_MINOR_MASK                   (0xFF0000U)
+#define LPDAC_VERID_MINOR_SHIFT                  (16U)
+#define LPDAC_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_MINOR_SHIFT)) & LPDAC_VERID_MINOR_MASK)
+#define LPDAC_VERID_MAJOR_MASK                   (0xFF000000U)
+#define LPDAC_VERID_MAJOR_SHIFT                  (24U)
+#define LPDAC_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_MAJOR_SHIFT)) & LPDAC_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define LPDAC_PARAM_FIFOSZ_MASK                  (0x7U)
+#define LPDAC_PARAM_FIFOSZ_SHIFT                 (0U)
+/*! FIFOSZ - FIFO size
+ *  0b000..Reserved
+ *  0b001..FIFO depth is 4
+ *  0b010..FIFO depth is 8
+ *  0b011..FIFO depth is 16
+ *  0b100..FIFO depth is 32
+ *  0b101..FIFO depth is 64
+ *  0b110..FIFO depth is 128
+ *  0b111..FIFO depth is 256
+ */
+#define LPDAC_PARAM_FIFOSZ(x)                    (((uint32_t)(((uint32_t)(x)) << LPDAC_PARAM_FIFOSZ_SHIFT)) & LPDAC_PARAM_FIFOSZ_MASK)
+/*! @} */
+
+/*! @name DATA - DAC Data Register */
+/*! @{ */
+#define LPDAC_DATA_DATA_MASK                     (0xFFFU)
+#define LPDAC_DATA_DATA_SHIFT                    (0U)
+#define LPDAC_DATA_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_DATA_DATA_SHIFT)) & LPDAC_DATA_DATA_MASK)
+/*! @} */
+
+/*! @name GCR - DAC Global Control Register */
+/*! @{ */
+#define LPDAC_GCR_DACEN_MASK                     (0x1U)
+#define LPDAC_GCR_DACEN_SHIFT                    (0U)
+/*! DACEN - DAC Enable
+ *  0b0..The DAC system is disabled.
+ *  0b1..The DAC system is enabled.
+ */
+#define LPDAC_GCR_DACEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACEN_SHIFT)) & LPDAC_GCR_DACEN_MASK)
+#define LPDAC_GCR_DACRFS_MASK                    (0x2U)
+#define LPDAC_GCR_DACRFS_SHIFT                   (1U)
+/*! DACRFS - DAC Reference Select
+ *  0b0..The DAC selects VREFH_INT as the reference voltage.
+ *  0b1..The DAC selects VREFH_EXT as the reference voltage.
+ */
+#define LPDAC_GCR_DACRFS(x)                      (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACRFS_SHIFT)) & LPDAC_GCR_DACRFS_MASK)
+#define LPDAC_GCR_LPEN_MASK                      (0x4U)
+#define LPDAC_GCR_LPEN_SHIFT                     (2U)
+/*! LPEN - Low Power Enable
+ *  0b0..High-Power mode
+ *  0b1..Low-Power mode
+ */
+#define LPDAC_GCR_LPEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_LPEN_SHIFT)) & LPDAC_GCR_LPEN_MASK)
+#define LPDAC_GCR_FIFOEN_MASK                    (0x8U)
+#define LPDAC_GCR_FIFOEN_SHIFT                   (3U)
+/*! FIFOEN - FIFO Enable
+ *  0b0..FIFO mode is disabled and buffer mode is enabled. Any data written to DATA[DATA] goes to buffer then goes to conversion.
+ *  0b1..FIFO mode is enabled. Data will be first read from FIFO to buffer then goes to conversion
+ */
+#define LPDAC_GCR_FIFOEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_FIFOEN_SHIFT)) & LPDAC_GCR_FIFOEN_MASK)
+#define LPDAC_GCR_SWMD_MASK                      (0x10U)
+#define LPDAC_GCR_SWMD_SHIFT                     (4U)
+/*! SWMD - Swing Back Mode
+ *  0b0..Swing back mode disable
+ *  0b1..Swing back mode enable
+ */
+#define LPDAC_GCR_SWMD(x)                        (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_SWMD_SHIFT)) & LPDAC_GCR_SWMD_MASK)
+#define LPDAC_GCR_TRGSEL_MASK                    (0x20U)
+#define LPDAC_GCR_TRGSEL_SHIFT                   (5U)
+/*! TRGSEL - DAC Trigger Select
+ *  0b0..The DAC hardware trigger is selected.
+ *  0b1..The DAC software trigger is selected.
+ */
+#define LPDAC_GCR_TRGSEL(x)                      (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_TRGSEL_SHIFT)) & LPDAC_GCR_TRGSEL_MASK)
+/*! @} */
+
+/*! @name FCR - DAC FIFO Control Register */
+/*! @{ */
+#define LPDAC_FCR_WML_MASK                       (0xFU)
+#define LPDAC_FCR_WML_SHIFT                      (0U)
+#define LPDAC_FCR_WML(x)                         (((uint32_t)(((uint32_t)(x)) << LPDAC_FCR_WML_SHIFT)) & LPDAC_FCR_WML_MASK)
+/*! @} */
+
+/*! @name FPR - DAC FIFO Pointer Register */
+/*! @{ */
+#define LPDAC_FPR_FIFO_RPT_MASK                  (0xFU)
+#define LPDAC_FPR_FIFO_RPT_SHIFT                 (0U)
+#define LPDAC_FPR_FIFO_RPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPDAC_FPR_FIFO_RPT_SHIFT)) & LPDAC_FPR_FIFO_RPT_MASK)
+#define LPDAC_FPR_FIFO_WPT_MASK                  (0xF0000U)
+#define LPDAC_FPR_FIFO_WPT_SHIFT                 (16U)
+#define LPDAC_FPR_FIFO_WPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPDAC_FPR_FIFO_WPT_SHIFT)) & LPDAC_FPR_FIFO_WPT_MASK)
+/*! @} */
+
+/*! @name FSR - FIFO Status Register */
+/*! @{ */
+#define LPDAC_FSR_FULL_MASK                      (0x1U)
+#define LPDAC_FSR_FULL_SHIFT                     (0U)
+/*! FULL - FIFO Full Flag
+ *  0b0..FIFO is not full
+ *  0b1..FIFO is full
+ */
+#define LPDAC_FSR_FULL(x)                        (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_FULL_SHIFT)) & LPDAC_FSR_FULL_MASK)
+#define LPDAC_FSR_EMPTY_MASK                     (0x2U)
+#define LPDAC_FSR_EMPTY_SHIFT                    (1U)
+/*! EMPTY - FIFO Empty Flag
+ *  0b0..FIFO is not empty
+ *  0b1..FIFO is empty
+ */
+#define LPDAC_FSR_EMPTY(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_EMPTY_SHIFT)) & LPDAC_FSR_EMPTY_MASK)
+#define LPDAC_FSR_WM_MASK                        (0x4U)
+#define LPDAC_FSR_WM_SHIFT                       (2U)
+/*! WM - FIFO Watermark Status Flag
+ *  0b0..Data in FIFO is more than watermark level
+ *  0b1..Data in FIFO is less than or equal to watermark level
+ */
+#define LPDAC_FSR_WM(x)                          (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_WM_SHIFT)) & LPDAC_FSR_WM_MASK)
+#define LPDAC_FSR_SWBK_MASK                      (0x8U)
+#define LPDAC_FSR_SWBK_SHIFT                     (3U)
+/*! SWBK - Swing Back One Cycle Complete Flag
+ *  0b0..No swing back cycle has completed since the last time the flag was cleared.
+ *  0b1..At least one swing back cycle has occurred since the last time the flag was cleared.
+ */
+#define LPDAC_FSR_SWBK(x)                        (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_SWBK_SHIFT)) & LPDAC_FSR_SWBK_MASK)
+#define LPDAC_FSR_OF_MASK                        (0x40U)
+#define LPDAC_FSR_OF_SHIFT                       (6U)
+/*! OF - FIFO Overflow Flag
+ *  0b0..No overflow has occurred since the last time the flag was cleared.
+ *  0b1..At least one FIFO overflow has occurred since the last time the flag was cleared.
+ */
+#define LPDAC_FSR_OF(x)                          (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_OF_SHIFT)) & LPDAC_FSR_OF_MASK)
+#define LPDAC_FSR_UF_MASK                        (0x80U)
+#define LPDAC_FSR_UF_SHIFT                       (7U)
+/*! UF - FIFO Underflow Flag
+ *  0b0..No underflow has occurred since the last time the flag was cleared.
+ *  0b1..At least one trigger underflow has occurred since the last time the flag was cleared.
+ */
+#define LPDAC_FSR_UF(x)                          (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_UF_SHIFT)) & LPDAC_FSR_UF_MASK)
+/*! @} */
+
+/*! @name IER - DAC Interrupt Enable Register */
+/*! @{ */
+#define LPDAC_IER_FULL_IE_MASK                   (0x1U)
+#define LPDAC_IER_FULL_IE_SHIFT                  (0U)
+/*! FULL_IE - FIFO Full Interrupt Enable
+ *  0b0..FIFO Full interrupt is disabled.
+ *  0b1..FIFO Full interrupt is enabled.
+ */
+#define LPDAC_IER_FULL_IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_FULL_IE_SHIFT)) & LPDAC_IER_FULL_IE_MASK)
+#define LPDAC_IER_EMPTY_IE_MASK                  (0x2U)
+#define LPDAC_IER_EMPTY_IE_SHIFT                 (1U)
+/*! EMPTY_IE - FIFO Empty Interrupt Enable
+ *  0b0..FIFO Empty interrupt is disabled.
+ *  0b1..FIFO Empty interrupt is enabled.
+ */
+#define LPDAC_IER_EMPTY_IE(x)                    (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_EMPTY_IE_SHIFT)) & LPDAC_IER_EMPTY_IE_MASK)
+#define LPDAC_IER_WM_IE_MASK                     (0x4U)
+#define LPDAC_IER_WM_IE_SHIFT                    (2U)
+/*! WM_IE - FIFO Watermark Interrupt Enable
+ *  0b0..Watermark interrupt is disabled.
+ *  0b1..Watermark interrupt is enabled.
+ */
+#define LPDAC_IER_WM_IE(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_WM_IE_SHIFT)) & LPDAC_IER_WM_IE_MASK)
+#define LPDAC_IER_SWBK_IE_MASK                   (0x8U)
+#define LPDAC_IER_SWBK_IE_SHIFT                  (3U)
+/*! SWBK_IE - Swing back One Cycle Complete Interrupt Enable
+ *  0b0..Swing back one time complete interrupt is disabled.
+ *  0b1..Swing back one time complete interrupt is enabled.
+ */
+#define LPDAC_IER_SWBK_IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_SWBK_IE_SHIFT)) & LPDAC_IER_SWBK_IE_MASK)
+#define LPDAC_IER_OF_IE_MASK                     (0x40U)
+#define LPDAC_IER_OF_IE_SHIFT                    (6U)
+/*! OF_IE - FIFO Overflow Interrupt Enable
+ *  0b0..Overflow interrupt is disabled
+ *  0b1..Overflow interrupt is enabled.
+ */
+#define LPDAC_IER_OF_IE(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_OF_IE_SHIFT)) & LPDAC_IER_OF_IE_MASK)
+#define LPDAC_IER_UF_IE_MASK                     (0x80U)
+#define LPDAC_IER_UF_IE_SHIFT                    (7U)
+/*! UF_IE - FIFO Underflow Interrupt Enable
+ *  0b0..Underflow interrupt is disabled.
+ *  0b1..Underflow interrupt is enabled.
+ */
+#define LPDAC_IER_UF_IE(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_UF_IE_SHIFT)) & LPDAC_IER_UF_IE_MASK)
+/*! @} */
+
+/*! @name DER - DAC DMA Enable Register */
+/*! @{ */
+#define LPDAC_DER_EMPTY_DMAEN_MASK               (0x2U)
+#define LPDAC_DER_EMPTY_DMAEN_SHIFT              (1U)
+/*! EMPTY_DMAEN - FIFO Empty DMA Enable
+ *  0b0..FIFO Empty DMA request is disabled.
+ *  0b1..FIFO Empty DMA request is enabled.
+ */
+#define LPDAC_DER_EMPTY_DMAEN(x)                 (((uint32_t)(((uint32_t)(x)) << LPDAC_DER_EMPTY_DMAEN_SHIFT)) & LPDAC_DER_EMPTY_DMAEN_MASK)
+#define LPDAC_DER_WM_DMAEN_MASK                  (0x4U)
+#define LPDAC_DER_WM_DMAEN_SHIFT                 (2U)
+/*! WM_DMAEN - FIFO Watermark DMA Enable
+ *  0b0..Watermark DMA request is disabled.
+ *  0b1..Watermark DMA request is enabled.
+ */
+#define LPDAC_DER_WM_DMAEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPDAC_DER_WM_DMAEN_SHIFT)) & LPDAC_DER_WM_DMAEN_MASK)
+/*! @} */
+
+/*! @name RCR - DAC Reset Control Register */
+/*! @{ */
+#define LPDAC_RCR_SWRST_MASK                     (0x1U)
+#define LPDAC_RCR_SWRST_SHIFT                    (0U)
+/*! SWRST - Software Reset
+ *  0b0..No effect
+ *  0b1..Software reset
+ */
+#define LPDAC_RCR_SWRST(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_RCR_SWRST_SHIFT)) & LPDAC_RCR_SWRST_MASK)
+#define LPDAC_RCR_FIFORST_MASK                   (0x2U)
+#define LPDAC_RCR_FIFORST_SHIFT                  (1U)
+/*! FIFORST - FIFO Reset
+ *  0b0..No effect
+ *  0b1..FIFO reset
+ */
+#define LPDAC_RCR_FIFORST(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_RCR_FIFORST_SHIFT)) & LPDAC_RCR_FIFORST_MASK)
+/*! @} */
+
+/*! @name TCR - DAC Trigger Control Register */
+/*! @{ */
+#define LPDAC_TCR_SWTRG_MASK                     (0x1U)
+#define LPDAC_TCR_SWTRG_SHIFT                    (0U)
+/*! SWTRG - Software Trigger
+ *  0b0..The DAC soft trigger is not valid.
+ *  0b1..The DAC soft trigger is valid.
+ */
+#define LPDAC_TCR_SWTRG(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_TCR_SWTRG_SHIFT)) & LPDAC_TCR_SWTRG_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LPDAC_Register_Masks */
+
+
+/* LPDAC - Peripheral instance base addresses */
+/** Peripheral LPDAC0 base address */
+#define LPDAC0_BASE                              (0x4004C000u)
+/** Peripheral LPDAC0 base pointer */
+#define LPDAC0                                   ((LPDAC_Type *)LPDAC0_BASE)
+/** Array initializer of LPDAC peripheral base addresses */
+#define LPDAC_BASE_ADDRS                         { LPDAC0_BASE }
+/** Array initializer of LPDAC peripheral base pointers */
+#define LPDAC_BASE_PTRS                          { LPDAC0 }
+/** Interrupt vectors for the LPDAC peripheral type */
+#define LPDAC_IRQS                               { LPDAC0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPDAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPI2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
+ * @{
+ */
+
+/** LPI2C - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t MCR;                               /**< Master Control Register, offset: 0x10 */
+  __IO uint32_t MSR;                               /**< Master Status Register, offset: 0x14 */
+  __IO uint32_t MIER;                              /**< Master Interrupt Enable Register, offset: 0x18 */
+  __IO uint32_t MDER;                              /**< Master DMA Enable Register, offset: 0x1C */
+  __IO uint32_t MCFGR0;                            /**< Master Configuration Register 0, offset: 0x20 */
+  __IO uint32_t MCFGR1;                            /**< Master Configuration Register 1, offset: 0x24 */
+  __IO uint32_t MCFGR2;                            /**< Master Configuration Register 2, offset: 0x28 */
+  __IO uint32_t MCFGR3;                            /**< Master Configuration Register 3, offset: 0x2C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t MDMR;                              /**< Master Data Match Register, offset: 0x40 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t MCCR0;                             /**< Master Clock Configuration Register 0, offset: 0x48 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t MCCR1;                             /**< Master Clock Configuration Register 1, offset: 0x50 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t MFCR;                              /**< Master FIFO Control Register, offset: 0x58 */
+  __I  uint32_t MFSR;                              /**< Master FIFO Status Register, offset: 0x5C */
+  __O  uint32_t MTDR;                              /**< Master Transmit Data Register, offset: 0x60 */
+       uint8_t RESERVED_5[12];
+  __I  uint32_t MRDR;                              /**< Master Receive Data Register, offset: 0x70 */
+       uint8_t RESERVED_6[156];
+  __IO uint32_t SCR;                               /**< Slave Control Register, offset: 0x110 */
+  __IO uint32_t SSR;                               /**< Slave Status Register, offset: 0x114 */
+  __IO uint32_t SIER;                              /**< Slave Interrupt Enable Register, offset: 0x118 */
+  __IO uint32_t SDER;                              /**< Slave DMA Enable Register, offset: 0x11C */
+       uint8_t RESERVED_7[4];
+  __IO uint32_t SCFGR1;                            /**< Slave Configuration Register 1, offset: 0x124 */
+  __IO uint32_t SCFGR2;                            /**< Slave Configuration Register 2, offset: 0x128 */
+       uint8_t RESERVED_8[20];
+  __IO uint32_t SAMR;                              /**< Slave Address Match Register, offset: 0x140 */
+       uint8_t RESERVED_9[12];
+  __I  uint32_t SASR;                              /**< Slave Address Status Register, offset: 0x150 */
+  __IO uint32_t STAR;                              /**< Slave Transmit ACK Register, offset: 0x154 */
+       uint8_t RESERVED_10[8];
+  __O  uint32_t STDR;                              /**< Slave Transmit Data Register, offset: 0x160 */
+       uint8_t RESERVED_11[12];
+  __I  uint32_t SRDR;                              /**< Slave Receive Data Register, offset: 0x170 */
+} LPI2C_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPI2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define LPI2C_VERID_FEATURE_MASK                 (0xFFFFU)
+#define LPI2C_VERID_FEATURE_SHIFT                (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000000000010..Master only, with standard feature set
+ *  0b0000000000000011..Master and slave, with standard feature set
+ */
+#define LPI2C_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
+#define LPI2C_VERID_MINOR_MASK                   (0xFF0000U)
+#define LPI2C_VERID_MINOR_SHIFT                  (16U)
+#define LPI2C_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
+#define LPI2C_VERID_MAJOR_MASK                   (0xFF000000U)
+#define LPI2C_VERID_MAJOR_SHIFT                  (24U)
+#define LPI2C_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define LPI2C_PARAM_MTXFIFO_MASK                 (0xFU)
+#define LPI2C_PARAM_MTXFIFO_SHIFT                (0U)
+#define LPI2C_PARAM_MTXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
+#define LPI2C_PARAM_MRXFIFO_MASK                 (0xF00U)
+#define LPI2C_PARAM_MRXFIFO_SHIFT                (8U)
+#define LPI2C_PARAM_MRXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
+/*! @} */
+
+/*! @name MCR - Master Control Register */
+/*! @{ */
+#define LPI2C_MCR_MEN_MASK                       (0x1U)
+#define LPI2C_MCR_MEN_SHIFT                      (0U)
+/*! MEN - Master Enable
+ *  0b0..Master logic is disabled
+ *  0b1..Master logic is enabled
+ */
+#define LPI2C_MCR_MEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
+#define LPI2C_MCR_RST_MASK                       (0x2U)
+#define LPI2C_MCR_RST_SHIFT                      (1U)
+/*! RST - Software Reset
+ *  0b0..Master logic is not reset
+ *  0b1..Master logic is reset
+ */
+#define LPI2C_MCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
+#define LPI2C_MCR_DOZEN_MASK                     (0x4U)
+#define LPI2C_MCR_DOZEN_SHIFT                    (2U)
+/*! DOZEN - Doze mode enable
+ *  0b0..Master is enabled in Doze mode
+ *  0b1..Master is disabled in Doze mode
+ */
+#define LPI2C_MCR_DOZEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
+#define LPI2C_MCR_DBGEN_MASK                     (0x8U)
+#define LPI2C_MCR_DBGEN_SHIFT                    (3U)
+/*! DBGEN - Debug Enable
+ *  0b0..Master is disabled in debug mode
+ *  0b1..Master is enabled in debug mode
+ */
+#define LPI2C_MCR_DBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
+#define LPI2C_MCR_RTF_MASK                       (0x100U)
+#define LPI2C_MCR_RTF_SHIFT                      (8U)
+/*! RTF - Reset Transmit FIFO
+ *  0b0..No effect
+ *  0b1..Transmit FIFO is reset
+ */
+#define LPI2C_MCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
+#define LPI2C_MCR_RRF_MASK                       (0x200U)
+#define LPI2C_MCR_RRF_SHIFT                      (9U)
+/*! RRF - Reset Receive FIFO
+ *  0b0..No effect
+ *  0b1..Receive FIFO is reset
+ */
+#define LPI2C_MCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
+/*! @} */
+
+/*! @name MSR - Master Status Register */
+/*! @{ */
+#define LPI2C_MSR_TDF_MASK                       (0x1U)
+#define LPI2C_MSR_TDF_SHIFT                      (0U)
+/*! TDF - Transmit Data Flag
+ *  0b0..Transmit data is not requested
+ *  0b1..Transmit data is requested
+ */
+#define LPI2C_MSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
+#define LPI2C_MSR_RDF_MASK                       (0x2U)
+#define LPI2C_MSR_RDF_SHIFT                      (1U)
+/*! RDF - Receive Data Flag
+ *  0b0..Receive Data is not ready
+ *  0b1..Receive data is ready
+ */
+#define LPI2C_MSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
+#define LPI2C_MSR_EPF_MASK                       (0x100U)
+#define LPI2C_MSR_EPF_SHIFT                      (8U)
+/*! EPF - End Packet Flag
+ *  0b0..Master has not generated a STOP or Repeated START condition
+ *  0b1..Master has generated a STOP or Repeated START condition
+ */
+#define LPI2C_MSR_EPF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
+#define LPI2C_MSR_SDF_MASK                       (0x200U)
+#define LPI2C_MSR_SDF_SHIFT                      (9U)
+/*! SDF - STOP Detect Flag
+ *  0b0..Master has not generated a STOP condition
+ *  0b1..Master has generated a STOP condition
+ */
+#define LPI2C_MSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
+#define LPI2C_MSR_NDF_MASK                       (0x400U)
+#define LPI2C_MSR_NDF_SHIFT                      (10U)
+/*! NDF - NACK Detect Flag
+ *  0b0..Unexpected NACK was not detected
+ *  0b1..Unexpected NACK was detected
+ */
+#define LPI2C_MSR_NDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
+#define LPI2C_MSR_ALF_MASK                       (0x800U)
+#define LPI2C_MSR_ALF_SHIFT                      (11U)
+/*! ALF - Arbitration Lost Flag
+ *  0b0..Master has not lost arbitration
+ *  0b1..Master has lost arbitration
+ */
+#define LPI2C_MSR_ALF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
+#define LPI2C_MSR_FEF_MASK                       (0x1000U)
+#define LPI2C_MSR_FEF_SHIFT                      (12U)
+/*! FEF - FIFO Error Flag
+ *  0b0..No error
+ *  0b1..Master sending or receiving data without a START condition
+ */
+#define LPI2C_MSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
+#define LPI2C_MSR_PLTF_MASK                      (0x2000U)
+#define LPI2C_MSR_PLTF_SHIFT                     (13U)
+/*! PLTF - Pin Low Timeout Flag
+ *  0b0..Pin low timeout has not occurred or is disabled
+ *  0b1..Pin low timeout has occurred
+ */
+#define LPI2C_MSR_PLTF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
+#define LPI2C_MSR_DMF_MASK                       (0x4000U)
+#define LPI2C_MSR_DMF_SHIFT                      (14U)
+/*! DMF - Data Match Flag
+ *  0b0..Have not received matching data
+ *  0b1..Have received matching data
+ */
+#define LPI2C_MSR_DMF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
+#define LPI2C_MSR_MBF_MASK                       (0x1000000U)
+#define LPI2C_MSR_MBF_SHIFT                      (24U)
+/*! MBF - Master Busy Flag
+ *  0b0..I2C Master is idle
+ *  0b1..I2C Master is busy
+ */
+#define LPI2C_MSR_MBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
+#define LPI2C_MSR_BBF_MASK                       (0x2000000U)
+#define LPI2C_MSR_BBF_SHIFT                      (25U)
+/*! BBF - Bus Busy Flag
+ *  0b0..I2C Bus is idle
+ *  0b1..I2C Bus is busy
+ */
+#define LPI2C_MSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
+/*! @} */
+
+/*! @name MIER - Master Interrupt Enable Register */
+/*! @{ */
+#define LPI2C_MIER_TDIE_MASK                     (0x1U)
+#define LPI2C_MIER_TDIE_SHIFT                    (0U)
+/*! TDIE - Transmit Data Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_MIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
+#define LPI2C_MIER_RDIE_MASK                     (0x2U)
+#define LPI2C_MIER_RDIE_SHIFT                    (1U)
+/*! RDIE - Receive Data Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_MIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
+#define LPI2C_MIER_EPIE_MASK                     (0x100U)
+#define LPI2C_MIER_EPIE_SHIFT                    (8U)
+/*! EPIE - End Packet Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_MIER_EPIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
+#define LPI2C_MIER_SDIE_MASK                     (0x200U)
+#define LPI2C_MIER_SDIE_SHIFT                    (9U)
+/*! SDIE - STOP Detect Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_MIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
+#define LPI2C_MIER_NDIE_MASK                     (0x400U)
+#define LPI2C_MIER_NDIE_SHIFT                    (10U)
+/*! NDIE - NACK Detect Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_MIER_NDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
+#define LPI2C_MIER_ALIE_MASK                     (0x800U)
+#define LPI2C_MIER_ALIE_SHIFT                    (11U)
+/*! ALIE - Arbitration Lost Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_MIER_ALIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
+#define LPI2C_MIER_FEIE_MASK                     (0x1000U)
+#define LPI2C_MIER_FEIE_SHIFT                    (12U)
+/*! FEIE - FIFO Error Interrupt Enable
+ *  0b0..Enabled
+ *  0b1..Disabled
+ */
+#define LPI2C_MIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
+#define LPI2C_MIER_PLTIE_MASK                    (0x2000U)
+#define LPI2C_MIER_PLTIE_SHIFT                   (13U)
+/*! PLTIE - Pin Low Timeout Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_MIER_PLTIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
+#define LPI2C_MIER_DMIE_MASK                     (0x4000U)
+#define LPI2C_MIER_DMIE_SHIFT                    (14U)
+/*! DMIE - Data Match Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_MIER_DMIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
+/*! @} */
+
+/*! @name MDER - Master DMA Enable Register */
+/*! @{ */
+#define LPI2C_MDER_TDDE_MASK                     (0x1U)
+#define LPI2C_MDER_TDDE_SHIFT                    (0U)
+/*! TDDE - Transmit Data DMA Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
+#define LPI2C_MDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
+#define LPI2C_MDER_RDDE_MASK                     (0x2U)
+#define LPI2C_MDER_RDDE_SHIFT                    (1U)
+/*! RDDE - Receive Data DMA Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
+#define LPI2C_MDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
+/*! @} */
+
+/*! @name MCFGR0 - Master Configuration Register 0 */
+/*! @{ */
+#define LPI2C_MCFGR0_HREN_MASK                   (0x1U)
+#define LPI2C_MCFGR0_HREN_SHIFT                  (0U)
+/*! HREN - Host Request Enable
+ *  0b0..Host request input is disabled
+ *  0b1..Host request input is enabled
+ */
+#define LPI2C_MCFGR0_HREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
+#define LPI2C_MCFGR0_HRPOL_MASK                  (0x2U)
+#define LPI2C_MCFGR0_HRPOL_SHIFT                 (1U)
+/*! HRPOL - Host Request Polarity
+ *  0b0..Active low
+ *  0b1..Active high
+ */
+#define LPI2C_MCFGR0_HRPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
+#define LPI2C_MCFGR0_HRSEL_MASK                  (0x4U)
+#define LPI2C_MCFGR0_HRSEL_SHIFT                 (2U)
+/*! HRSEL - Host Request Select
+ *  0b0..Host request input is pin HREQ
+ *  0b1..Host request input is input trigger
+ */
+#define LPI2C_MCFGR0_HRSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
+#define LPI2C_MCFGR0_CIRFIFO_MASK                (0x100U)
+#define LPI2C_MCFGR0_CIRFIFO_SHIFT               (8U)
+/*! CIRFIFO - Circular FIFO Enable
+ *  0b0..Circular FIFO is disabled
+ *  0b1..Circular FIFO is enabled
+ */
+#define LPI2C_MCFGR0_CIRFIFO(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
+#define LPI2C_MCFGR0_RDMO_MASK                   (0x200U)
+#define LPI2C_MCFGR0_RDMO_SHIFT                  (9U)
+/*! RDMO - Receive Data Match Only
+ *  0b0..Received data is stored in the receive FIFO
+ *  0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set
+ */
+#define LPI2C_MCFGR0_RDMO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
+/*! @} */
+
+/*! @name MCFGR1 - Master Configuration Register 1 */
+/*! @{ */
+#define LPI2C_MCFGR1_PRESCALE_MASK               (0x7U)
+#define LPI2C_MCFGR1_PRESCALE_SHIFT              (0U)
+/*! PRESCALE - Prescaler
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 4
+ *  0b011..Divide by 8
+ *  0b100..Divide by 16
+ *  0b101..Divide by 32
+ *  0b110..Divide by 64
+ *  0b111..Divide by 128
+ */
+#define LPI2C_MCFGR1_PRESCALE(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
+#define LPI2C_MCFGR1_AUTOSTOP_MASK               (0x100U)
+#define LPI2C_MCFGR1_AUTOSTOP_SHIFT              (8U)
+/*! AUTOSTOP - Automatic STOP Generation
+ *  0b0..No effect
+ *  0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy
+ */
+#define LPI2C_MCFGR1_AUTOSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
+#define LPI2C_MCFGR1_IGNACK_MASK                 (0x200U)
+#define LPI2C_MCFGR1_IGNACK_SHIFT                (9U)
+/*! IGNACK - IGNACK
+ *  0b0..LPI2C Master will receive ACK and NACK normally
+ *  0b1..LPI2C Master will treat a received NACK as if it (NACK) was an ACK
+ */
+#define LPI2C_MCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
+#define LPI2C_MCFGR1_TIMECFG_MASK                (0x400U)
+#define LPI2C_MCFGR1_TIMECFG_SHIFT               (10U)
+/*! TIMECFG - Timeout Configuration
+ *  0b0..Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout
+ *  0b1..Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout
+ */
+#define LPI2C_MCFGR1_TIMECFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
+#define LPI2C_MCFGR1_MATCFG_MASK                 (0x70000U)
+#define LPI2C_MCFGR1_MATCFG_SHIFT                (16U)
+/*! MATCFG - Match Configuration
+ *  0b000..Match is disabled
+ *  0b001..Reserved
+ *  0b010..Match is enabled (1st data word equals MATCH0 OR MATCH1)
+ *  0b011..Match is enabled (any data word equals MATCH0 OR MATCH1)
+ *  0b100..Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1)
+ *  0b101..Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1)
+ *  0b110..Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1)
+ *  0b111..Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1)
+ */
+#define LPI2C_MCFGR1_MATCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
+#define LPI2C_MCFGR1_PINCFG_MASK                 (0x7000000U)
+#define LPI2C_MCFGR1_PINCFG_SHIFT                (24U)
+/*! PINCFG - Pin Configuration
+ *  0b000..2-pin open drain mode
+ *  0b001..2-pin output only mode (ultra-fast mode)
+ *  0b010..2-pin push-pull mode
+ *  0b011..4-pin push-pull mode
+ *  0b100..2-pin open drain mode with separate LPI2C slave
+ *  0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave
+ *  0b110..2-pin push-pull mode with separate LPI2C slave
+ *  0b111..4-pin push-pull mode (inverted outputs)
+ */
+#define LPI2C_MCFGR1_PINCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
+/*! @} */
+
+/*! @name MCFGR2 - Master Configuration Register 2 */
+/*! @{ */
+#define LPI2C_MCFGR2_BUSIDLE_MASK                (0xFFFU)
+#define LPI2C_MCFGR2_BUSIDLE_SHIFT               (0U)
+#define LPI2C_MCFGR2_BUSIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
+#define LPI2C_MCFGR2_FILTSCL_MASK                (0xF0000U)
+#define LPI2C_MCFGR2_FILTSCL_SHIFT               (16U)
+#define LPI2C_MCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
+#define LPI2C_MCFGR2_FILTSDA_MASK                (0xF000000U)
+#define LPI2C_MCFGR2_FILTSDA_SHIFT               (24U)
+#define LPI2C_MCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
+/*! @} */
+
+/*! @name MCFGR3 - Master Configuration Register 3 */
+/*! @{ */
+#define LPI2C_MCFGR3_PINLOW_MASK                 (0xFFF00U)
+#define LPI2C_MCFGR3_PINLOW_SHIFT                (8U)
+#define LPI2C_MCFGR3_PINLOW(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
+/*! @} */
+
+/*! @name MDMR - Master Data Match Register */
+/*! @{ */
+#define LPI2C_MDMR_MATCH0_MASK                   (0xFFU)
+#define LPI2C_MDMR_MATCH0_SHIFT                  (0U)
+#define LPI2C_MDMR_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
+#define LPI2C_MDMR_MATCH1_MASK                   (0xFF0000U)
+#define LPI2C_MDMR_MATCH1_SHIFT                  (16U)
+#define LPI2C_MDMR_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
+/*! @} */
+
+/*! @name MCCR0 - Master Clock Configuration Register 0 */
+/*! @{ */
+#define LPI2C_MCCR0_CLKLO_MASK                   (0x3FU)
+#define LPI2C_MCCR0_CLKLO_SHIFT                  (0U)
+#define LPI2C_MCCR0_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
+#define LPI2C_MCCR0_CLKHI_MASK                   (0x3F00U)
+#define LPI2C_MCCR0_CLKHI_SHIFT                  (8U)
+#define LPI2C_MCCR0_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
+#define LPI2C_MCCR0_SETHOLD_MASK                 (0x3F0000U)
+#define LPI2C_MCCR0_SETHOLD_SHIFT                (16U)
+#define LPI2C_MCCR0_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
+#define LPI2C_MCCR0_DATAVD_MASK                  (0x3F000000U)
+#define LPI2C_MCCR0_DATAVD_SHIFT                 (24U)
+#define LPI2C_MCCR0_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
+/*! @} */
+
+/*! @name MCCR1 - Master Clock Configuration Register 1 */
+/*! @{ */
+#define LPI2C_MCCR1_CLKLO_MASK                   (0x3FU)
+#define LPI2C_MCCR1_CLKLO_SHIFT                  (0U)
+#define LPI2C_MCCR1_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
+#define LPI2C_MCCR1_CLKHI_MASK                   (0x3F00U)
+#define LPI2C_MCCR1_CLKHI_SHIFT                  (8U)
+#define LPI2C_MCCR1_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
+#define LPI2C_MCCR1_SETHOLD_MASK                 (0x3F0000U)
+#define LPI2C_MCCR1_SETHOLD_SHIFT                (16U)
+#define LPI2C_MCCR1_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
+#define LPI2C_MCCR1_DATAVD_MASK                  (0x3F000000U)
+#define LPI2C_MCCR1_DATAVD_SHIFT                 (24U)
+#define LPI2C_MCCR1_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
+/*! @} */
+
+/*! @name MFCR - Master FIFO Control Register */
+/*! @{ */
+#define LPI2C_MFCR_TXWATER_MASK                  (0x3U)
+#define LPI2C_MFCR_TXWATER_SHIFT                 (0U)
+#define LPI2C_MFCR_TXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
+#define LPI2C_MFCR_RXWATER_MASK                  (0x30000U)
+#define LPI2C_MFCR_RXWATER_SHIFT                 (16U)
+#define LPI2C_MFCR_RXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
+/*! @} */
+
+/*! @name MFSR - Master FIFO Status Register */
+/*! @{ */
+#define LPI2C_MFSR_TXCOUNT_MASK                  (0x7U)
+#define LPI2C_MFSR_TXCOUNT_SHIFT                 (0U)
+#define LPI2C_MFSR_TXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
+#define LPI2C_MFSR_RXCOUNT_MASK                  (0x70000U)
+#define LPI2C_MFSR_RXCOUNT_SHIFT                 (16U)
+#define LPI2C_MFSR_RXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
+/*! @} */
+
+/*! @name MTDR - Master Transmit Data Register */
+/*! @{ */
+#define LPI2C_MTDR_DATA_MASK                     (0xFFU)
+#define LPI2C_MTDR_DATA_SHIFT                    (0U)
+#define LPI2C_MTDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
+#define LPI2C_MTDR_CMD_MASK                      (0x700U)
+#define LPI2C_MTDR_CMD_SHIFT                     (8U)
+/*! CMD - Command Data
+ *  0b000..Transmit DATA[7:0]
+ *  0b001..Receive (DATA[7:0] + 1) bytes
+ *  0b010..Generate STOP condition
+ *  0b011..Receive and discard (DATA[7:0] + 1) bytes
+ *  0b100..Generate (repeated) START and transmit address in DATA[7:0]
+ *  0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned.
+ *  0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode
+ *  0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.
+ */
+#define LPI2C_MTDR_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
+/*! @} */
+
+/*! @name MRDR - Master Receive Data Register */
+/*! @{ */
+#define LPI2C_MRDR_DATA_MASK                     (0xFFU)
+#define LPI2C_MRDR_DATA_SHIFT                    (0U)
+#define LPI2C_MRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
+#define LPI2C_MRDR_RXEMPTY_MASK                  (0x4000U)
+#define LPI2C_MRDR_RXEMPTY_SHIFT                 (14U)
+/*! RXEMPTY - RX Empty
+ *  0b0..Receive FIFO is not empty
+ *  0b1..Receive FIFO is empty
+ */
+#define LPI2C_MRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
+/*! @} */
+
+/*! @name SCR - Slave Control Register */
+/*! @{ */
+#define LPI2C_SCR_SEN_MASK                       (0x1U)
+#define LPI2C_SCR_SEN_SHIFT                      (0U)
+/*! SEN - Slave Enable
+ *  0b0..I2C Slave mode is disabled
+ *  0b1..I2C Slave mode is enabled
+ */
+#define LPI2C_SCR_SEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
+#define LPI2C_SCR_RST_MASK                       (0x2U)
+#define LPI2C_SCR_RST_SHIFT                      (1U)
+/*! RST - Software Reset
+ *  0b0..Slave mode logic is not reset
+ *  0b1..Slave mode logic is reset
+ */
+#define LPI2C_SCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
+#define LPI2C_SCR_FILTEN_MASK                    (0x10U)
+#define LPI2C_SCR_FILTEN_SHIFT                   (4U)
+/*! FILTEN - Filter Enable
+ *  0b0..Disable digital filter and output delay counter for slave mode
+ *  0b1..Enable digital filter and output delay counter for slave mode
+ */
+#define LPI2C_SCR_FILTEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
+#define LPI2C_SCR_FILTDZ_MASK                    (0x20U)
+#define LPI2C_SCR_FILTDZ_SHIFT                   (5U)
+/*! FILTDZ - Filter Doze Enable
+ *  0b0..Filter remains enabled in Doze mode
+ *  0b1..Filter is disabled in Doze mode
+ */
+#define LPI2C_SCR_FILTDZ(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
+#define LPI2C_SCR_RTF_MASK                       (0x100U)
+#define LPI2C_SCR_RTF_SHIFT                      (8U)
+/*! RTF - Reset Transmit FIFO
+ *  0b0..No effect
+ *  0b1..Transmit Data Register is now empty
+ */
+#define LPI2C_SCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
+#define LPI2C_SCR_RRF_MASK                       (0x200U)
+#define LPI2C_SCR_RRF_SHIFT                      (9U)
+/*! RRF - Reset Receive FIFO
+ *  0b0..No effect
+ *  0b1..Receive Data Register is now empty
+ */
+#define LPI2C_SCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
+/*! @} */
+
+/*! @name SSR - Slave Status Register */
+/*! @{ */
+#define LPI2C_SSR_TDF_MASK                       (0x1U)
+#define LPI2C_SSR_TDF_SHIFT                      (0U)
+/*! TDF - Transmit Data Flag
+ *  0b0..Transmit data not requested
+ *  0b1..Transmit data is requested
+ */
+#define LPI2C_SSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
+#define LPI2C_SSR_RDF_MASK                       (0x2U)
+#define LPI2C_SSR_RDF_SHIFT                      (1U)
+/*! RDF - Receive Data Flag
+ *  0b0..Receive data is not ready
+ *  0b1..Receive data is ready
+ */
+#define LPI2C_SSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
+#define LPI2C_SSR_AVF_MASK                       (0x4U)
+#define LPI2C_SSR_AVF_SHIFT                      (2U)
+/*! AVF - Address Valid Flag
+ *  0b0..Address Status Register is not valid
+ *  0b1..Address Status Register is valid
+ */
+#define LPI2C_SSR_AVF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
+#define LPI2C_SSR_TAF_MASK                       (0x8U)
+#define LPI2C_SSR_TAF_SHIFT                      (3U)
+/*! TAF - Transmit ACK Flag
+ *  0b0..Transmit ACK/NACK is not required
+ *  0b1..Transmit ACK/NACK is required
+ */
+#define LPI2C_SSR_TAF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
+#define LPI2C_SSR_RSF_MASK                       (0x100U)
+#define LPI2C_SSR_RSF_SHIFT                      (8U)
+/*! RSF - Repeated Start Flag
+ *  0b0..Slave has not detected a Repeated START condition
+ *  0b1..Slave has detected a Repeated START condition
+ */
+#define LPI2C_SSR_RSF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
+#define LPI2C_SSR_SDF_MASK                       (0x200U)
+#define LPI2C_SSR_SDF_SHIFT                      (9U)
+/*! SDF - STOP Detect Flag
+ *  0b0..Slave has not detected a STOP condition
+ *  0b1..Slave has detected a STOP condition
+ */
+#define LPI2C_SSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
+#define LPI2C_SSR_BEF_MASK                       (0x400U)
+#define LPI2C_SSR_BEF_SHIFT                      (10U)
+/*! BEF - Bit Error Flag
+ *  0b0..Slave has not detected a bit error
+ *  0b1..Slave has detected a bit error
+ */
+#define LPI2C_SSR_BEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
+#define LPI2C_SSR_FEF_MASK                       (0x800U)
+#define LPI2C_SSR_FEF_SHIFT                      (11U)
+/*! FEF - FIFO Error Flag
+ *  0b0..FIFO underflow or overflow was not detected
+ *  0b1..FIFO underflow or overflow was detected
+ */
+#define LPI2C_SSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
+#define LPI2C_SSR_AM0F_MASK                      (0x1000U)
+#define LPI2C_SSR_AM0F_SHIFT                     (12U)
+/*! AM0F - Address Match 0 Flag
+ *  0b0..Have not received an ADDR0 matching address
+ *  0b1..Have received an ADDR0 matching address
+ */
+#define LPI2C_SSR_AM0F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
+#define LPI2C_SSR_AM1F_MASK                      (0x2000U)
+#define LPI2C_SSR_AM1F_SHIFT                     (13U)
+/*! AM1F - Address Match 1 Flag
+ *  0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address
+ *  0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address
+ */
+#define LPI2C_SSR_AM1F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
+#define LPI2C_SSR_GCF_MASK                       (0x4000U)
+#define LPI2C_SSR_GCF_SHIFT                      (14U)
+/*! GCF - General Call Flag
+ *  0b0..Slave has not detected the General Call Address or the General Call Address is disabled
+ *  0b1..Slave has detected the General Call Address
+ */
+#define LPI2C_SSR_GCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
+#define LPI2C_SSR_SARF_MASK                      (0x8000U)
+#define LPI2C_SSR_SARF_SHIFT                     (15U)
+/*! SARF - SMBus Alert Response Flag
+ *  0b0..SMBus Alert Response is disabled or not detected
+ *  0b1..SMBus Alert Response is enabled and detected
+ */
+#define LPI2C_SSR_SARF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
+#define LPI2C_SSR_SBF_MASK                       (0x1000000U)
+#define LPI2C_SSR_SBF_SHIFT                      (24U)
+/*! SBF - Slave Busy Flag
+ *  0b0..I2C Slave is idle
+ *  0b1..I2C Slave is busy
+ */
+#define LPI2C_SSR_SBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
+#define LPI2C_SSR_BBF_MASK                       (0x2000000U)
+#define LPI2C_SSR_BBF_SHIFT                      (25U)
+/*! BBF - Bus Busy Flag
+ *  0b0..I2C Bus is idle
+ *  0b1..I2C Bus is busy
+ */
+#define LPI2C_SSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
+/*! @} */
+
+/*! @name SIER - Slave Interrupt Enable Register */
+/*! @{ */
+#define LPI2C_SIER_TDIE_MASK                     (0x1U)
+#define LPI2C_SIER_TDIE_SHIFT                    (0U)
+/*! TDIE - Transmit Data Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_SIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
+#define LPI2C_SIER_RDIE_MASK                     (0x2U)
+#define LPI2C_SIER_RDIE_SHIFT                    (1U)
+/*! RDIE - Receive Data Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_SIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
+#define LPI2C_SIER_AVIE_MASK                     (0x4U)
+#define LPI2C_SIER_AVIE_SHIFT                    (2U)
+/*! AVIE - Address Valid Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_SIER_AVIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
+#define LPI2C_SIER_TAIE_MASK                     (0x8U)
+#define LPI2C_SIER_TAIE_SHIFT                    (3U)
+/*! TAIE - Transmit ACK Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_SIER_TAIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
+#define LPI2C_SIER_RSIE_MASK                     (0x100U)
+#define LPI2C_SIER_RSIE_SHIFT                    (8U)
+/*! RSIE - Repeated Start Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_SIER_RSIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
+#define LPI2C_SIER_SDIE_MASK                     (0x200U)
+#define LPI2C_SIER_SDIE_SHIFT                    (9U)
+/*! SDIE - STOP Detect Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_SIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
+#define LPI2C_SIER_BEIE_MASK                     (0x400U)
+#define LPI2C_SIER_BEIE_SHIFT                    (10U)
+/*! BEIE - Bit Error Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_SIER_BEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
+#define LPI2C_SIER_FEIE_MASK                     (0x800U)
+#define LPI2C_SIER_FEIE_SHIFT                    (11U)
+/*! FEIE - FIFO Error Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_SIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
+#define LPI2C_SIER_AM0IE_MASK                    (0x1000U)
+#define LPI2C_SIER_AM0IE_SHIFT                   (12U)
+/*! AM0IE - Address Match 0 Interrupt Enable
+ *  0b0..Enabled
+ *  0b1..Disabled
+ */
+#define LPI2C_SIER_AM0IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
+#define LPI2C_SIER_AM1F_MASK                     (0x2000U)
+#define LPI2C_SIER_AM1F_SHIFT                    (13U)
+/*! AM1F - Address Match 1 Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_SIER_AM1F(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)
+#define LPI2C_SIER_GCIE_MASK                     (0x4000U)
+#define LPI2C_SIER_GCIE_SHIFT                    (14U)
+/*! GCIE - General Call Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_SIER_GCIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
+#define LPI2C_SIER_SARIE_MASK                    (0x8000U)
+#define LPI2C_SIER_SARIE_SHIFT                   (15U)
+/*! SARIE - SMBus Alert Response Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPI2C_SIER_SARIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
+/*! @} */
+
+/*! @name SDER - Slave DMA Enable Register */
+/*! @{ */
+#define LPI2C_SDER_TDDE_MASK                     (0x1U)
+#define LPI2C_SDER_TDDE_SHIFT                    (0U)
+/*! TDDE - Transmit Data DMA Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
+#define LPI2C_SDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
+#define LPI2C_SDER_RDDE_MASK                     (0x2U)
+#define LPI2C_SDER_RDDE_SHIFT                    (1U)
+/*! RDDE - Receive Data DMA Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
+#define LPI2C_SDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
+#define LPI2C_SDER_AVDE_MASK                     (0x4U)
+#define LPI2C_SDER_AVDE_SHIFT                    (2U)
+/*! AVDE - Address Valid DMA Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
+#define LPI2C_SDER_AVDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
+/*! @} */
+
+/*! @name SCFGR1 - Slave Configuration Register 1 */
+/*! @{ */
+#define LPI2C_SCFGR1_ADRSTALL_MASK               (0x1U)
+#define LPI2C_SCFGR1_ADRSTALL_SHIFT              (0U)
+/*! ADRSTALL - Address SCL Stall
+ *  0b0..Clock stretching is disabled
+ *  0b1..Clock stretching is enabled
+ */
+#define LPI2C_SCFGR1_ADRSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
+#define LPI2C_SCFGR1_RXSTALL_MASK                (0x2U)
+#define LPI2C_SCFGR1_RXSTALL_SHIFT               (1U)
+/*! RXSTALL - RX SCL Stall
+ *  0b0..Clock stretching is disabled
+ *  0b1..Clock stretching is enabled
+ */
+#define LPI2C_SCFGR1_RXSTALL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
+#define LPI2C_SCFGR1_TXDSTALL_MASK               (0x4U)
+#define LPI2C_SCFGR1_TXDSTALL_SHIFT              (2U)
+/*! TXDSTALL - TX Data SCL Stall
+ *  0b0..Clock stretching is disabled
+ *  0b1..Clock stretching is enabled
+ */
+#define LPI2C_SCFGR1_TXDSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
+#define LPI2C_SCFGR1_ACKSTALL_MASK               (0x8U)
+#define LPI2C_SCFGR1_ACKSTALL_SHIFT              (3U)
+/*! ACKSTALL - ACK SCL Stall
+ *  0b0..Clock stretching is disabled
+ *  0b1..Clock stretching is enabled
+ */
+#define LPI2C_SCFGR1_ACKSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
+#define LPI2C_SCFGR1_GCEN_MASK                   (0x100U)
+#define LPI2C_SCFGR1_GCEN_SHIFT                  (8U)
+/*! GCEN - General Call Enable
+ *  0b0..General Call address is disabled
+ *  0b1..General Call address is enabled
+ */
+#define LPI2C_SCFGR1_GCEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
+#define LPI2C_SCFGR1_SAEN_MASK                   (0x200U)
+#define LPI2C_SCFGR1_SAEN_SHIFT                  (9U)
+/*! SAEN - SMBus Alert Enable
+ *  0b0..Disables match on SMBus Alert
+ *  0b1..Enables match on SMBus Alert
+ */
+#define LPI2C_SCFGR1_SAEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
+#define LPI2C_SCFGR1_TXCFG_MASK                  (0x400U)
+#define LPI2C_SCFGR1_TXCFG_SHIFT                 (10U)
+/*! TXCFG - Transmit Flag Configuration
+ *  0b0..Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty
+ *  0b1..Transmit Data Flag will assert whenever the Transmit Data register is empty
+ */
+#define LPI2C_SCFGR1_TXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
+#define LPI2C_SCFGR1_RXCFG_MASK                  (0x800U)
+#define LPI2C_SCFGR1_RXCFG_SHIFT                 (11U)
+/*! RXCFG - Receive Data Configuration
+ *  0b0..Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]).
+ *  0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]).
+ */
+#define LPI2C_SCFGR1_RXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
+#define LPI2C_SCFGR1_IGNACK_MASK                 (0x1000U)
+#define LPI2C_SCFGR1_IGNACK_SHIFT                (12U)
+/*! IGNACK - Ignore NACK
+ *  0b0..Slave will end transfer when NACK is detected
+ *  0b1..Slave will not end transfer when NACK detected
+ */
+#define LPI2C_SCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
+#define LPI2C_SCFGR1_HSMEN_MASK                  (0x2000U)
+#define LPI2C_SCFGR1_HSMEN_SHIFT                 (13U)
+/*! HSMEN - High Speed Mode Enable
+ *  0b0..Disables detection of HS-mode master code
+ *  0b1..Enables detection of HS-mode master code
+ */
+#define LPI2C_SCFGR1_HSMEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
+#define LPI2C_SCFGR1_ADDRCFG_MASK                (0x70000U)
+#define LPI2C_SCFGR1_ADDRCFG_SHIFT               (16U)
+/*! ADDRCFG - Address Configuration
+ *  0b000..Address match 0 (7-bit)
+ *  0b001..Address match 0 (10-bit)
+ *  0b010..Address match 0 (7-bit) or Address match 1 (7-bit)
+ *  0b011..Address match 0 (10-bit) or Address match 1 (10-bit)
+ *  0b100..Address match 0 (7-bit) or Address match 1 (10-bit)
+ *  0b101..Address match 0 (10-bit) or Address match 1 (7-bit)
+ *  0b110..From Address match 0 (7-bit) to Address match 1 (7-bit)
+ *  0b111..From Address match 0 (10-bit) to Address match 1 (10-bit)
+ */
+#define LPI2C_SCFGR1_ADDRCFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
+/*! @} */
+
+/*! @name SCFGR2 - Slave Configuration Register 2 */
+/*! @{ */
+#define LPI2C_SCFGR2_CLKHOLD_MASK                (0xFU)
+#define LPI2C_SCFGR2_CLKHOLD_SHIFT               (0U)
+#define LPI2C_SCFGR2_CLKHOLD(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
+#define LPI2C_SCFGR2_DATAVD_MASK                 (0x3F00U)
+#define LPI2C_SCFGR2_DATAVD_SHIFT                (8U)
+#define LPI2C_SCFGR2_DATAVD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
+#define LPI2C_SCFGR2_FILTSCL_MASK                (0xF0000U)
+#define LPI2C_SCFGR2_FILTSCL_SHIFT               (16U)
+#define LPI2C_SCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
+#define LPI2C_SCFGR2_FILTSDA_MASK                (0xF000000U)
+#define LPI2C_SCFGR2_FILTSDA_SHIFT               (24U)
+#define LPI2C_SCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
+/*! @} */
+
+/*! @name SAMR - Slave Address Match Register */
+/*! @{ */
+#define LPI2C_SAMR_ADDR0_MASK                    (0x7FEU)
+#define LPI2C_SAMR_ADDR0_SHIFT                   (1U)
+#define LPI2C_SAMR_ADDR0(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
+#define LPI2C_SAMR_ADDR1_MASK                    (0x7FE0000U)
+#define LPI2C_SAMR_ADDR1_SHIFT                   (17U)
+#define LPI2C_SAMR_ADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
+/*! @} */
+
+/*! @name SASR - Slave Address Status Register */
+/*! @{ */
+#define LPI2C_SASR_RADDR_MASK                    (0x7FFU)
+#define LPI2C_SASR_RADDR_SHIFT                   (0U)
+#define LPI2C_SASR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
+#define LPI2C_SASR_ANV_MASK                      (0x4000U)
+#define LPI2C_SASR_ANV_SHIFT                     (14U)
+/*! ANV - Address Not Valid
+ *  0b0..Received Address (RADDR) is valid
+ *  0b1..Received Address (RADDR) is not valid
+ */
+#define LPI2C_SASR_ANV(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
+/*! @} */
+
+/*! @name STAR - Slave Transmit ACK Register */
+/*! @{ */
+#define LPI2C_STAR_TXNACK_MASK                   (0x1U)
+#define LPI2C_STAR_TXNACK_SHIFT                  (0U)
+/*! TXNACK - Transmit NACK
+ *  0b0..Write a Transmit ACK for each received word
+ *  0b1..Write a Transmit NACK for each received word
+ */
+#define LPI2C_STAR_TXNACK(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
+/*! @} */
+
+/*! @name STDR - Slave Transmit Data Register */
+/*! @{ */
+#define LPI2C_STDR_DATA_MASK                     (0xFFU)
+#define LPI2C_STDR_DATA_SHIFT                    (0U)
+#define LPI2C_STDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
+/*! @} */
+
+/*! @name SRDR - Slave Receive Data Register */
+/*! @{ */
+#define LPI2C_SRDR_DATA_MASK                     (0xFFU)
+#define LPI2C_SRDR_DATA_SHIFT                    (0U)
+#define LPI2C_SRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
+#define LPI2C_SRDR_RXEMPTY_MASK                  (0x4000U)
+#define LPI2C_SRDR_RXEMPTY_SHIFT                 (14U)
+/*! RXEMPTY - RX Empty
+ *  0b0..The Receive Data Register is not empty
+ *  0b1..The Receive Data Register is empty
+ */
+#define LPI2C_SRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
+#define LPI2C_SRDR_SOF_MASK                      (0x8000U)
+#define LPI2C_SRDR_SOF_SHIFT                     (15U)
+/*! SOF - Start Of Frame
+ *  0b0..Indicates this is not the first data word since a (repeated) START or STOP condition
+ *  0b1..Indicates this is the first data word since a (repeated) START or STOP condition
+ */
+#define LPI2C_SRDR_SOF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LPI2C_Register_Masks */
+
+
+/* LPI2C - Peripheral instance base addresses */
+/** Peripheral LPI2C0 base address */
+#define LPI2C0_BASE                              (0x4003A000u)
+/** Peripheral LPI2C0 base pointer */
+#define LPI2C0                                   ((LPI2C_Type *)LPI2C0_BASE)
+/** Peripheral LPI2C1 base address */
+#define LPI2C1_BASE                              (0x4003B000u)
+/** Peripheral LPI2C1 base pointer */
+#define LPI2C1                                   ((LPI2C_Type *)LPI2C1_BASE)
+/** Peripheral LPI2C2 base address */
+#define LPI2C2_BASE                              (0x4003C000u)
+/** Peripheral LPI2C2 base pointer */
+#define LPI2C2                                   ((LPI2C_Type *)LPI2C2_BASE)
+/** Peripheral LPI2C3 base address */
+#define LPI2C3_BASE                              (0x4102E000u)
+/** Peripheral LPI2C3 base pointer */
+#define LPI2C3                                   ((LPI2C_Type *)LPI2C3_BASE)
+/** Array initializer of LPI2C peripheral base addresses */
+#define LPI2C_BASE_ADDRS                         { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE }
+/** Array initializer of LPI2C peripheral base pointers */
+#define LPI2C_BASE_PTRS                          { LPI2C0, LPI2C1, LPI2C2, LPI2C3 }
+/** Interrupt vectors for the LPI2C peripheral type */
+#define LPI2C_IRQS                               { LPI2C0_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPI2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPIT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPIT_Peripheral_Access_Layer LPIT Peripheral Access Layer
+ * @{
+ */
+
+/** LPIT - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __IO uint32_t MCR;                               /**< Module Control Register, offset: 0x8 */
+  __IO uint32_t MSR;                               /**< Module Status Register, offset: 0xC */
+  __IO uint32_t MIER;                              /**< Module Interrupt Enable Register, offset: 0x10 */
+  __IO uint32_t SETTEN;                            /**< Set Timer Enable Register, offset: 0x14 */
+  __O  uint32_t CLRTEN;                            /**< Clear Timer Enable Register, offset: 0x18 */
+       uint8_t RESERVED_0[4];
+  struct {                                         /* offset: 0x20, array step: 0x10 */
+    __IO uint32_t TVAL;                              /**< Timer Value Register, array offset: 0x20, array step: 0x10 */
+    __I  uint32_t CVAL;                              /**< Current Timer Value, array offset: 0x24, array step: 0x10 */
+    __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x28, array step: 0x10 */
+         uint8_t RESERVED_0[4];
+  } CHANNEL[4];
+} LPIT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPIT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPIT_Register_Masks LPIT Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define LPIT_VERID_FEATURE_MASK                  (0xFFFFU)
+#define LPIT_VERID_FEATURE_SHIFT                 (0U)
+#define LPIT_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_FEATURE_SHIFT)) & LPIT_VERID_FEATURE_MASK)
+#define LPIT_VERID_MINOR_MASK                    (0xFF0000U)
+#define LPIT_VERID_MINOR_SHIFT                   (16U)
+#define LPIT_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MINOR_SHIFT)) & LPIT_VERID_MINOR_MASK)
+#define LPIT_VERID_MAJOR_MASK                    (0xFF000000U)
+#define LPIT_VERID_MAJOR_SHIFT                   (24U)
+#define LPIT_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MAJOR_SHIFT)) & LPIT_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define LPIT_PARAM_CHANNEL_MASK                  (0xFFU)
+#define LPIT_PARAM_CHANNEL_SHIFT                 (0U)
+#define LPIT_PARAM_CHANNEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_CHANNEL_SHIFT)) & LPIT_PARAM_CHANNEL_MASK)
+#define LPIT_PARAM_EXT_TRIG_MASK                 (0xFF00U)
+#define LPIT_PARAM_EXT_TRIG_SHIFT                (8U)
+#define LPIT_PARAM_EXT_TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_EXT_TRIG_SHIFT)) & LPIT_PARAM_EXT_TRIG_MASK)
+/*! @} */
+
+/*! @name MCR - Module Control Register */
+/*! @{ */
+#define LPIT_MCR_M_CEN_MASK                      (0x1U)
+#define LPIT_MCR_M_CEN_SHIFT                     (0U)
+/*! M_CEN - Module Clock Enable
+ *  0b0..Disable peripheral clock to timers
+ *  0b1..Enable peripheral clock to timers
+ */
+#define LPIT_MCR_M_CEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_M_CEN_SHIFT)) & LPIT_MCR_M_CEN_MASK)
+#define LPIT_MCR_SW_RST_MASK                     (0x2U)
+#define LPIT_MCR_SW_RST_SHIFT                    (1U)
+/*! SW_RST - Software Reset Bit
+ *  0b0..Timer channels and registers are not reset
+ *  0b1..Reset timer channels and registers
+ */
+#define LPIT_MCR_SW_RST(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_SW_RST_SHIFT)) & LPIT_MCR_SW_RST_MASK)
+#define LPIT_MCR_DOZE_EN_MASK                    (0x4U)
+#define LPIT_MCR_DOZE_EN_SHIFT                   (2U)
+/*! DOZE_EN - DOZE Mode Enable Bit
+ *  0b0..Stop timer channels in DOZE mode
+ *  0b1..Allow timer channels to continue to run in DOZE mode
+ */
+#define LPIT_MCR_DOZE_EN(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DOZE_EN_SHIFT)) & LPIT_MCR_DOZE_EN_MASK)
+#define LPIT_MCR_DBG_EN_MASK                     (0x8U)
+#define LPIT_MCR_DBG_EN_SHIFT                    (3U)
+/*! DBG_EN - Debug Enable Bit
+ *  0b0..Stop timer channels in Debug mode
+ *  0b1..Allow timer channels to continue to run in Debug mode
+ */
+#define LPIT_MCR_DBG_EN(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DBG_EN_SHIFT)) & LPIT_MCR_DBG_EN_MASK)
+/*! @} */
+
+/*! @name MSR - Module Status Register */
+/*! @{ */
+#define LPIT_MSR_TIF0_MASK                       (0x1U)
+#define LPIT_MSR_TIF0_SHIFT                      (0U)
+/*! TIF0 - Channel 0 Timer Interrupt Flag
+ *  0b0..Timer has not timed out
+ *  0b1..Timeout has occurred (timer has timed out)
+ */
+#define LPIT_MSR_TIF0(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF0_SHIFT)) & LPIT_MSR_TIF0_MASK)
+#define LPIT_MSR_TIF1_MASK                       (0x2U)
+#define LPIT_MSR_TIF1_SHIFT                      (1U)
+/*! TIF1 - Channel 1 Timer Interrupt Flag
+ *  0b0..Timer has not timed out
+ *  0b1..Timeout has occurred (timer has timed out)
+ */
+#define LPIT_MSR_TIF1(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF1_SHIFT)) & LPIT_MSR_TIF1_MASK)
+#define LPIT_MSR_TIF2_MASK                       (0x4U)
+#define LPIT_MSR_TIF2_SHIFT                      (2U)
+/*! TIF2 - Channel 2 Timer Interrupt Flag
+ *  0b0..Timer has not timed out
+ *  0b1..Timeout has occurred (timer has timed out)
+ */
+#define LPIT_MSR_TIF2(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF2_SHIFT)) & LPIT_MSR_TIF2_MASK)
+#define LPIT_MSR_TIF3_MASK                       (0x8U)
+#define LPIT_MSR_TIF3_SHIFT                      (3U)
+/*! TIF3 - Channel 3 Timer Interrupt Flag
+ *  0b0..Timer has not timed out
+ *  0b1..Timeout has occurred (timer has timed out)
+ */
+#define LPIT_MSR_TIF3(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF3_SHIFT)) & LPIT_MSR_TIF3_MASK)
+/*! @} */
+
+/*! @name MIER - Module Interrupt Enable Register */
+/*! @{ */
+#define LPIT_MIER_TIE0_MASK                      (0x1U)
+#define LPIT_MIER_TIE0_SHIFT                     (0U)
+/*! TIE0 - Channel 0 Timer Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPIT_MIER_TIE0(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE0_SHIFT)) & LPIT_MIER_TIE0_MASK)
+#define LPIT_MIER_TIE1_MASK                      (0x2U)
+#define LPIT_MIER_TIE1_SHIFT                     (1U)
+/*! TIE1 - Channel 1 Timer Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPIT_MIER_TIE1(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE1_SHIFT)) & LPIT_MIER_TIE1_MASK)
+#define LPIT_MIER_TIE2_MASK                      (0x4U)
+#define LPIT_MIER_TIE2_SHIFT                     (2U)
+/*! TIE2 - Channel 2 Timer Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPIT_MIER_TIE2(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE2_SHIFT)) & LPIT_MIER_TIE2_MASK)
+#define LPIT_MIER_TIE3_MASK                      (0x8U)
+#define LPIT_MIER_TIE3_SHIFT                     (3U)
+/*! TIE3 - Channel 3 Timer Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPIT_MIER_TIE3(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE3_SHIFT)) & LPIT_MIER_TIE3_MASK)
+/*! @} */
+
+/*! @name SETTEN - Set Timer Enable Register */
+/*! @{ */
+#define LPIT_SETTEN_SET_T_EN_0_MASK              (0x1U)
+#define LPIT_SETTEN_SET_T_EN_0_SHIFT             (0U)
+/*! SET_T_EN_0 - Set Timer 0 Enable
+ *  0b0..No effect
+ *  0b1..Enables Timer Channel 0
+ */
+#define LPIT_SETTEN_SET_T_EN_0(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_0_SHIFT)) & LPIT_SETTEN_SET_T_EN_0_MASK)
+#define LPIT_SETTEN_SET_T_EN_1_MASK              (0x2U)
+#define LPIT_SETTEN_SET_T_EN_1_SHIFT             (1U)
+/*! SET_T_EN_1 - Set Timer 1 Enable
+ *  0b0..No Effect
+ *  0b1..Enables Timer Channel 1
+ */
+#define LPIT_SETTEN_SET_T_EN_1(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_1_SHIFT)) & LPIT_SETTEN_SET_T_EN_1_MASK)
+#define LPIT_SETTEN_SET_T_EN_2_MASK              (0x4U)
+#define LPIT_SETTEN_SET_T_EN_2_SHIFT             (2U)
+/*! SET_T_EN_2 - Set Timer 2 Enable
+ *  0b0..No Effect
+ *  0b1..Enables Timer Channel 2
+ */
+#define LPIT_SETTEN_SET_T_EN_2(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_2_SHIFT)) & LPIT_SETTEN_SET_T_EN_2_MASK)
+#define LPIT_SETTEN_SET_T_EN_3_MASK              (0x8U)
+#define LPIT_SETTEN_SET_T_EN_3_SHIFT             (3U)
+/*! SET_T_EN_3 - Set Timer 3 Enable
+ *  0b0..No effect
+ *  0b1..Enables Timer Channel 3
+ */
+#define LPIT_SETTEN_SET_T_EN_3(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_3_SHIFT)) & LPIT_SETTEN_SET_T_EN_3_MASK)
+/*! @} */
+
+/*! @name CLRTEN - Clear Timer Enable Register */
+/*! @{ */
+#define LPIT_CLRTEN_CLR_T_EN_0_MASK              (0x1U)
+#define LPIT_CLRTEN_CLR_T_EN_0_SHIFT             (0U)
+/*! CLR_T_EN_0 - Clear Timer 0 Enable
+ *  0b0..No action
+ *  0b1..Clear the Timer Enable bit (TCTRL0[T_EN]) for Timer Channel 0
+ */
+#define LPIT_CLRTEN_CLR_T_EN_0(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_0_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_0_MASK)
+#define LPIT_CLRTEN_CLR_T_EN_1_MASK              (0x2U)
+#define LPIT_CLRTEN_CLR_T_EN_1_SHIFT             (1U)
+/*! CLR_T_EN_1 - Clear Timer 1 Enable
+ *  0b0..No Action
+ *  0b1..Clear the Timer Enable bit (TCTRL1[T_EN]) for Timer Channel 1
+ */
+#define LPIT_CLRTEN_CLR_T_EN_1(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_1_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_1_MASK)
+#define LPIT_CLRTEN_CLR_T_EN_2_MASK              (0x4U)
+#define LPIT_CLRTEN_CLR_T_EN_2_SHIFT             (2U)
+/*! CLR_T_EN_2 - Clear Timer 2 Enable
+ *  0b0..No Action
+ *  0b1..Clear the Timer Enable bit (TCTRL2[T_EN]) for Timer Channel 2
+ */
+#define LPIT_CLRTEN_CLR_T_EN_2(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_2_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_2_MASK)
+#define LPIT_CLRTEN_CLR_T_EN_3_MASK              (0x8U)
+#define LPIT_CLRTEN_CLR_T_EN_3_SHIFT             (3U)
+/*! CLR_T_EN_3 - Clear Timer 3 Enable
+ *  0b0..No Action
+ *  0b1..Clear the Timer Enable bit (TCTRL3[T_EN]) for Timer Channel 3
+ */
+#define LPIT_CLRTEN_CLR_T_EN_3(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_3_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_3_MASK)
+/*! @} */
+
+/*! @name TVAL - Timer Value Register */
+/*! @{ */
+#define LPIT_TVAL_TMR_VAL_MASK                   (0xFFFFFFFFU)
+#define LPIT_TVAL_TMR_VAL_SHIFT                  (0U)
+/*! TMR_VAL - Timer Value
+ *  0b00000000000000000000000000000000..Invalid load value in compare mode
+ *  0b00000000000000000000000000000001..Invalid load value in compare mode
+ *  0b00000000000000000000000000000010-0b11111111111111111111111111111111..In compare mode: the value to be loaded; in capture mode, the value of the timer
+ */
+#define LPIT_TVAL_TMR_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << LPIT_TVAL_TMR_VAL_SHIFT)) & LPIT_TVAL_TMR_VAL_MASK)
+/*! @} */
+
+/* The count of LPIT_TVAL */
+#define LPIT_TVAL_COUNT                          (4U)
+
+/*! @name CVAL - Current Timer Value */
+/*! @{ */
+#define LPIT_CVAL_TMR_CUR_VAL_MASK               (0xFFFFFFFFU)
+#define LPIT_CVAL_TMR_CUR_VAL_SHIFT              (0U)
+#define LPIT_CVAL_TMR_CUR_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
+/*! @} */
+
+/* The count of LPIT_CVAL */
+#define LPIT_CVAL_COUNT                          (4U)
+
+/*! @name TCTRL - Timer Control Register */
+/*! @{ */
+#define LPIT_TCTRL_T_EN_MASK                     (0x1U)
+#define LPIT_TCTRL_T_EN_SHIFT                    (0U)
+/*! T_EN - Timer Enable
+ *  0b0..Timer Channel is disabled
+ *  0b1..Timer Channel is enabled
+ */
+#define LPIT_TCTRL_T_EN(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_T_EN_SHIFT)) & LPIT_TCTRL_T_EN_MASK)
+#define LPIT_TCTRL_CHAIN_MASK                    (0x2U)
+#define LPIT_TCTRL_CHAIN_SHIFT                   (1U)
+/*! CHAIN - Chain Channel
+ *  0b0..Channel Chaining is disabled. The channel timer runs independently.
+ *  0b1..Channel Chaining is enabled. The timer decrements on the previous channel's timeout.
+ */
+#define LPIT_TCTRL_CHAIN(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_CHAIN_SHIFT)) & LPIT_TCTRL_CHAIN_MASK)
+#define LPIT_TCTRL_MODE_MASK                     (0xCU)
+#define LPIT_TCTRL_MODE_SHIFT                    (2U)
+/*! MODE - Timer Operation Mode
+ *  0b00..32-bit Periodic Counter
+ *  0b01..Dual 16-bit Periodic Counter
+ *  0b10..32-bit Trigger Accumulator
+ *  0b11..32-bit Trigger Input Capture
+ */
+#define LPIT_TCTRL_MODE(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_MODE_SHIFT)) & LPIT_TCTRL_MODE_MASK)
+#define LPIT_TCTRL_TSOT_MASK                     (0x10000U)
+#define LPIT_TCTRL_TSOT_SHIFT                    (16U)
+/*! TSOT - Timer Start On Trigger
+ *  0b0..Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI))
+ *  0b1..Timer starts to decrement when a rising edge on a selected trigger is detected
+ */
+#define LPIT_TCTRL_TSOT(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOT_SHIFT)) & LPIT_TCTRL_TSOT_MASK)
+#define LPIT_TCTRL_TSOI_MASK                     (0x20000U)
+#define LPIT_TCTRL_TSOI_SHIFT                    (17U)
+/*! TSOI - Timer Stop On Interrupt
+ *  0b0..The channel timer does not stop after timeout
+ *  0b1..The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected.
+ */
+#define LPIT_TCTRL_TSOI(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOI_SHIFT)) & LPIT_TCTRL_TSOI_MASK)
+#define LPIT_TCTRL_TROT_MASK                     (0x40000U)
+#define LPIT_TCTRL_TROT_SHIFT                    (18U)
+/*! TROT - Timer Reload On Trigger
+ *  0b0..Timer will not reload on the selected trigger
+ *  0b1..Timer will reload on the selected trigger
+ */
+#define LPIT_TCTRL_TROT(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TROT_SHIFT)) & LPIT_TCTRL_TROT_MASK)
+#define LPIT_TCTRL_TRG_SRC_MASK                  (0x800000U)
+#define LPIT_TCTRL_TRG_SRC_SHIFT                 (23U)
+/*! TRG_SRC - Trigger Source
+ *  0b0..Selects external triggers
+ *  0b1..Selects internal triggers
+ */
+#define LPIT_TCTRL_TRG_SRC(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SRC_SHIFT)) & LPIT_TCTRL_TRG_SRC_MASK)
+#define LPIT_TCTRL_TRG_SEL_MASK                  (0xF000000U)
+#define LPIT_TCTRL_TRG_SEL_SHIFT                 (24U)
+/*! TRG_SEL - Trigger Select
+ *  0b0000-0b0011..Timer channel 0 - 3 trigger source is selected
+ *  0b0100-0b1111..Reserved
+ */
+#define LPIT_TCTRL_TRG_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SEL_SHIFT)) & LPIT_TCTRL_TRG_SEL_MASK)
+/*! @} */
+
+/* The count of LPIT_TCTRL */
+#define LPIT_TCTRL_COUNT                         (4U)
+
+
+/*!
+ * @}
+ */ /* end of group LPIT_Register_Masks */
+
+
+/* LPIT - Peripheral instance base addresses */
+/** Peripheral LPIT0 base address */
+#define LPIT0_BASE                               (0x40030000u)
+/** Peripheral LPIT0 base pointer */
+#define LPIT0                                    ((LPIT_Type *)LPIT0_BASE)
+/** Peripheral LPIT1 base address */
+#define LPIT1_BASE                               (0x4102A000u)
+/** Peripheral LPIT1 base pointer */
+#define LPIT1                                    ((LPIT_Type *)LPIT1_BASE)
+/** Array initializer of LPIT peripheral base addresses */
+#define LPIT_BASE_ADDRS                          { LPIT0_BASE, LPIT1_BASE }
+/** Array initializer of LPIT peripheral base pointers */
+#define LPIT_BASE_PTRS                           { LPIT0, LPIT1 }
+/** Interrupt vectors for the LPIT peripheral type */
+#define LPIT_IRQS                                { { LPIT0_IRQn, LPIT0_IRQn, LPIT0_IRQn, LPIT0_IRQn }, { LPIT1_IRQn, LPIT1_IRQn, LPIT1_IRQn, LPIT1_IRQn } }
+
+/*!
+ * @}
+ */ /* end of group LPIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPSPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
+ * @{
+ */
+
+/** LPSPI - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t CR;                                /**< Control Register, offset: 0x10 */
+  __IO uint32_t SR;                                /**< Status Register, offset: 0x14 */
+  __IO uint32_t IER;                               /**< Interrupt Enable Register, offset: 0x18 */
+  __IO uint32_t DER;                               /**< DMA Enable Register, offset: 0x1C */
+  __IO uint32_t CFGR0;                             /**< Configuration Register 0, offset: 0x20 */
+  __IO uint32_t CFGR1;                             /**< Configuration Register 1, offset: 0x24 */
+       uint8_t RESERVED_1[8];
+  __IO uint32_t DMR0;                              /**< Data Match Register 0, offset: 0x30 */
+  __IO uint32_t DMR1;                              /**< Data Match Register 1, offset: 0x34 */
+       uint8_t RESERVED_2[8];
+  __IO uint32_t CCR;                               /**< Clock Configuration Register, offset: 0x40 */
+       uint8_t RESERVED_3[20];
+  __IO uint32_t FCR;                               /**< FIFO Control Register, offset: 0x58 */
+  __I  uint32_t FSR;                               /**< FIFO Status Register, offset: 0x5C */
+  __IO uint32_t TCR;                               /**< Transmit Command Register, offset: 0x60 */
+  __O  uint32_t TDR;                               /**< Transmit Data Register, offset: 0x64 */
+       uint8_t RESERVED_4[8];
+  __I  uint32_t RSR;                               /**< Receive Status Register, offset: 0x70 */
+  __I  uint32_t RDR;                               /**< Receive Data Register, offset: 0x74 */
+} LPSPI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPSPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPSPI_Register_Masks LPSPI Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define LPSPI_VERID_FEATURE_MASK                 (0xFFFFU)
+#define LPSPI_VERID_FEATURE_SHIFT                (0U)
+/*! FEATURE - Module Identification Number
+ *  0b0000000000000100..Standard feature set supporting a 32-bit shift register.
+ */
+#define LPSPI_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
+#define LPSPI_VERID_MINOR_MASK                   (0xFF0000U)
+#define LPSPI_VERID_MINOR_SHIFT                  (16U)
+#define LPSPI_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
+#define LPSPI_VERID_MAJOR_MASK                   (0xFF000000U)
+#define LPSPI_VERID_MAJOR_SHIFT                  (24U)
+#define LPSPI_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define LPSPI_PARAM_TXFIFO_MASK                  (0xFFU)
+#define LPSPI_PARAM_TXFIFO_SHIFT                 (0U)
+#define LPSPI_PARAM_TXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
+#define LPSPI_PARAM_RXFIFO_MASK                  (0xFF00U)
+#define LPSPI_PARAM_RXFIFO_SHIFT                 (8U)
+#define LPSPI_PARAM_RXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
+/*! @} */
+
+/*! @name CR - Control Register */
+/*! @{ */
+#define LPSPI_CR_MEN_MASK                        (0x1U)
+#define LPSPI_CR_MEN_SHIFT                       (0U)
+/*! MEN - Module Enable
+ *  0b0..Module is disabled
+ *  0b1..Module is enabled
+ */
+#define LPSPI_CR_MEN(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
+#define LPSPI_CR_RST_MASK                        (0x2U)
+#define LPSPI_CR_RST_SHIFT                       (1U)
+/*! RST - Software Reset
+ *  0b0..Master logic is not reset
+ *  0b1..Master logic is reset
+ */
+#define LPSPI_CR_RST(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
+#define LPSPI_CR_DOZEN_MASK                      (0x4U)
+#define LPSPI_CR_DOZEN_SHIFT                     (2U)
+/*! DOZEN - Doze mode enable
+ *  0b0..Module is enabled in Doze mode
+ *  0b1..Module is disabled in Doze mode
+ */
+#define LPSPI_CR_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
+#define LPSPI_CR_DBGEN_MASK                      (0x8U)
+#define LPSPI_CR_DBGEN_SHIFT                     (3U)
+/*! DBGEN - Debug Enable
+ *  0b0..Module is disabled in debug mode
+ *  0b1..Module is enabled in debug mode
+ */
+#define LPSPI_CR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
+#define LPSPI_CR_RTF_MASK                        (0x100U)
+#define LPSPI_CR_RTF_SHIFT                       (8U)
+/*! RTF - Reset Transmit FIFO
+ *  0b0..No effect
+ *  0b1..Transmit FIFO is reset
+ */
+#define LPSPI_CR_RTF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
+#define LPSPI_CR_RRF_MASK                        (0x200U)
+#define LPSPI_CR_RRF_SHIFT                       (9U)
+/*! RRF - Reset Receive FIFO
+ *  0b0..No effect
+ *  0b1..Receive FIFO is reset
+ */
+#define LPSPI_CR_RRF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
+/*! @} */
+
+/*! @name SR - Status Register */
+/*! @{ */
+#define LPSPI_SR_TDF_MASK                        (0x1U)
+#define LPSPI_SR_TDF_SHIFT                       (0U)
+/*! TDF - Transmit Data Flag
+ *  0b0..Transmit data not requested
+ *  0b1..Transmit data is requested
+ */
+#define LPSPI_SR_TDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
+#define LPSPI_SR_RDF_MASK                        (0x2U)
+#define LPSPI_SR_RDF_SHIFT                       (1U)
+/*! RDF - Receive Data Flag
+ *  0b0..Receive Data is not ready
+ *  0b1..Receive data is ready
+ */
+#define LPSPI_SR_RDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
+#define LPSPI_SR_WCF_MASK                        (0x100U)
+#define LPSPI_SR_WCF_SHIFT                       (8U)
+/*! WCF - Word Complete Flag
+ *  0b0..Transfer of a received word has not yet completed
+ *  0b1..Transfer of a received word has completed
+ */
+#define LPSPI_SR_WCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
+#define LPSPI_SR_FCF_MASK                        (0x200U)
+#define LPSPI_SR_FCF_SHIFT                       (9U)
+/*! FCF - Frame Complete Flag
+ *  0b0..Frame transfer has not completed
+ *  0b1..Frame transfer has completed
+ */
+#define LPSPI_SR_FCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
+#define LPSPI_SR_TCF_MASK                        (0x400U)
+#define LPSPI_SR_TCF_SHIFT                       (10U)
+/*! TCF - Transfer Complete Flag
+ *  0b0..All transfers have not completed
+ *  0b1..All transfers have completed
+ */
+#define LPSPI_SR_TCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
+#define LPSPI_SR_TEF_MASK                        (0x800U)
+#define LPSPI_SR_TEF_SHIFT                       (11U)
+/*! TEF - Transmit Error Flag
+ *  0b0..Transmit FIFO underrun has not occurred
+ *  0b1..Transmit FIFO underrun has occurred
+ */
+#define LPSPI_SR_TEF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
+#define LPSPI_SR_REF_MASK                        (0x1000U)
+#define LPSPI_SR_REF_SHIFT                       (12U)
+/*! REF - Receive Error Flag
+ *  0b0..Receive FIFO has not overflowed
+ *  0b1..Receive FIFO has overflowed
+ */
+#define LPSPI_SR_REF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
+#define LPSPI_SR_DMF_MASK                        (0x2000U)
+#define LPSPI_SR_DMF_SHIFT                       (13U)
+/*! DMF - Data Match Flag
+ *  0b0..Have not received matching data
+ *  0b1..Have received matching data
+ */
+#define LPSPI_SR_DMF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
+#define LPSPI_SR_MBF_MASK                        (0x1000000U)
+#define LPSPI_SR_MBF_SHIFT                       (24U)
+/*! MBF - Module Busy Flag
+ *  0b0..LPSPI is idle
+ *  0b1..LPSPI is busy
+ */
+#define LPSPI_SR_MBF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
+/*! @} */
+
+/*! @name IER - Interrupt Enable Register */
+/*! @{ */
+#define LPSPI_IER_TDIE_MASK                      (0x1U)
+#define LPSPI_IER_TDIE_SHIFT                     (0U)
+/*! TDIE - Transmit Data Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_TDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
+#define LPSPI_IER_RDIE_MASK                      (0x2U)
+#define LPSPI_IER_RDIE_SHIFT                     (1U)
+/*! RDIE - Receive Data Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_RDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
+#define LPSPI_IER_WCIE_MASK                      (0x100U)
+#define LPSPI_IER_WCIE_SHIFT                     (8U)
+/*! WCIE - Word Complete Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_WCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
+#define LPSPI_IER_FCIE_MASK                      (0x200U)
+#define LPSPI_IER_FCIE_SHIFT                     (9U)
+/*! FCIE - Frame Complete Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_FCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
+#define LPSPI_IER_TCIE_MASK                      (0x400U)
+#define LPSPI_IER_TCIE_SHIFT                     (10U)
+/*! TCIE - Transfer Complete Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_TCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
+#define LPSPI_IER_TEIE_MASK                      (0x800U)
+#define LPSPI_IER_TEIE_SHIFT                     (11U)
+/*! TEIE - Transmit Error Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_TEIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
+#define LPSPI_IER_REIE_MASK                      (0x1000U)
+#define LPSPI_IER_REIE_SHIFT                     (12U)
+/*! REIE - Receive Error Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_REIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
+#define LPSPI_IER_DMIE_MASK                      (0x2000U)
+#define LPSPI_IER_DMIE_SHIFT                     (13U)
+/*! DMIE - Data Match Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_DMIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
+/*! @} */
+
+/*! @name DER - DMA Enable Register */
+/*! @{ */
+#define LPSPI_DER_TDDE_MASK                      (0x1U)
+#define LPSPI_DER_TDDE_SHIFT                     (0U)
+/*! TDDE - Transmit Data DMA Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
+#define LPSPI_DER_TDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
+#define LPSPI_DER_RDDE_MASK                      (0x2U)
+#define LPSPI_DER_RDDE_SHIFT                     (1U)
+/*! RDDE - Receive Data DMA Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
+#define LPSPI_DER_RDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
+/*! @} */
+
+/*! @name CFGR0 - Configuration Register 0 */
+/*! @{ */
+#define LPSPI_CFGR0_HREN_MASK                    (0x1U)
+#define LPSPI_CFGR0_HREN_SHIFT                   (0U)
+/*! HREN - Host Request Enable
+ *  0b0..Host request is disabled
+ *  0b1..Host request is enabled
+ */
+#define LPSPI_CFGR0_HREN(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
+#define LPSPI_CFGR0_HRPOL_MASK                   (0x2U)
+#define LPSPI_CFGR0_HRPOL_SHIFT                  (1U)
+/*! HRPOL - Host Request Polarity
+ *  0b0..Active low
+ *  0b1..Active high
+ */
+#define LPSPI_CFGR0_HRPOL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
+#define LPSPI_CFGR0_HRSEL_MASK                   (0x4U)
+#define LPSPI_CFGR0_HRSEL_SHIFT                  (2U)
+/*! HRSEL - Host Request Select
+ *  0b0..Host request input is the LPSPI_HREQ pin
+ *  0b1..Host request input is the input trigger
+ */
+#define LPSPI_CFGR0_HRSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
+#define LPSPI_CFGR0_CIRFIFO_MASK                 (0x100U)
+#define LPSPI_CFGR0_CIRFIFO_SHIFT                (8U)
+/*! CIRFIFO - Circular FIFO Enable
+ *  0b0..Circular FIFO is disabled
+ *  0b1..Circular FIFO is enabled
+ */
+#define LPSPI_CFGR0_CIRFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
+#define LPSPI_CFGR0_RDMO_MASK                    (0x200U)
+#define LPSPI_CFGR0_RDMO_SHIFT                   (9U)
+/*! RDMO - Receive Data Match Only
+ *  0b0..Received data is stored in the receive FIFO as in normal operations
+ *  0b1..Received data is discarded unless the Data Match Flag (DMF) is set
+ */
+#define LPSPI_CFGR0_RDMO(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
+/*! @} */
+
+/*! @name CFGR1 - Configuration Register 1 */
+/*! @{ */
+#define LPSPI_CFGR1_MASTER_MASK                  (0x1U)
+#define LPSPI_CFGR1_MASTER_SHIFT                 (0U)
+/*! MASTER - Master Mode
+ *  0b0..Slave mode
+ *  0b1..Master mode
+ */
+#define LPSPI_CFGR1_MASTER(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
+#define LPSPI_CFGR1_SAMPLE_MASK                  (0x2U)
+#define LPSPI_CFGR1_SAMPLE_SHIFT                 (1U)
+/*! SAMPLE - Sample Point
+ *  0b0..Input data is sampled on SCK edge
+ *  0b1..Input data is sampled on delayed SCK edge
+ */
+#define LPSPI_CFGR1_SAMPLE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
+#define LPSPI_CFGR1_AUTOPCS_MASK                 (0x4U)
+#define LPSPI_CFGR1_AUTOPCS_SHIFT                (2U)
+/*! AUTOPCS - Automatic PCS
+ *  0b0..Automatic PCS generation is disabled
+ *  0b1..Automatic PCS generation is enabled
+ */
+#define LPSPI_CFGR1_AUTOPCS(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
+#define LPSPI_CFGR1_NOSTALL_MASK                 (0x8U)
+#define LPSPI_CFGR1_NOSTALL_SHIFT                (3U)
+/*! NOSTALL - No Stall
+ *  0b0..Transfers will stall when the transmit FIFO is empty or the receive FIFO is full
+ *  0b1..Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur
+ */
+#define LPSPI_CFGR1_NOSTALL(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
+#define LPSPI_CFGR1_PCSPOL_MASK                  (0xF00U)
+#define LPSPI_CFGR1_PCSPOL_SHIFT                 (8U)
+/*! PCSPOL - Peripheral Chip Select Polarity
+ *  0b0000..The Peripheral Chip Select pin PCSx is active low
+ *  0b0001..The Peripheral Chip Select pin PCSx is active high
+ */
+#define LPSPI_CFGR1_PCSPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
+#define LPSPI_CFGR1_MATCFG_MASK                  (0x70000U)
+#define LPSPI_CFGR1_MATCFG_SHIFT                 (16U)
+/*! MATCFG - Match Configuration
+ *  0b000..Match is disabled
+ *  0b001..Reserved
+ *  0b010..010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1)
+ *  0b011..011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)
+ *  0b100..100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)]
+ *  0b101..101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)]
+ *  0b110..110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)]
+ *  0b111..111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)]
+ */
+#define LPSPI_CFGR1_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
+#define LPSPI_CFGR1_PINCFG_MASK                  (0x3000000U)
+#define LPSPI_CFGR1_PINCFG_SHIFT                 (24U)
+/*! PINCFG - Pin Configuration
+ *  0b00..SIN is used for input data and SOUT is used for output data
+ *  0b01..SIN is used for both input and output data
+ *  0b10..SOUT is used for both input and output data
+ *  0b11..SOUT is used for input data and SIN is used for output data
+ */
+#define LPSPI_CFGR1_PINCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
+#define LPSPI_CFGR1_OUTCFG_MASK                  (0x4000000U)
+#define LPSPI_CFGR1_OUTCFG_SHIFT                 (26U)
+/*! OUTCFG - Output Config
+ *  0b0..Output data retains last value when chip select is negated
+ *  0b1..Output data is tristated when chip select is negated
+ */
+#define LPSPI_CFGR1_OUTCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
+#define LPSPI_CFGR1_PCSCFG_MASK                  (0x8000000U)
+#define LPSPI_CFGR1_PCSCFG_SHIFT                 (27U)
+/*! PCSCFG - Peripheral Chip Select Configuration
+ *  0b0..PCS[3:2] are enabled
+ *  0b1..PCS[3:2] are disabled
+ */
+#define LPSPI_CFGR1_PCSCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
+/*! @} */
+
+/*! @name DMR0 - Data Match Register 0 */
+/*! @{ */
+#define LPSPI_DMR0_MATCH0_MASK                   (0xFFFFFFFFU)
+#define LPSPI_DMR0_MATCH0_SHIFT                  (0U)
+#define LPSPI_DMR0_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
+/*! @} */
+
+/*! @name DMR1 - Data Match Register 1 */
+/*! @{ */
+#define LPSPI_DMR1_MATCH1_MASK                   (0xFFFFFFFFU)
+#define LPSPI_DMR1_MATCH1_SHIFT                  (0U)
+#define LPSPI_DMR1_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
+/*! @} */
+
+/*! @name CCR - Clock Configuration Register */
+/*! @{ */
+#define LPSPI_CCR_SCKDIV_MASK                    (0xFFU)
+#define LPSPI_CCR_SCKDIV_SHIFT                   (0U)
+#define LPSPI_CCR_SCKDIV(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
+#define LPSPI_CCR_DBT_MASK                       (0xFF00U)
+#define LPSPI_CCR_DBT_SHIFT                      (8U)
+#define LPSPI_CCR_DBT(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
+#define LPSPI_CCR_PCSSCK_MASK                    (0xFF0000U)
+#define LPSPI_CCR_PCSSCK_SHIFT                   (16U)
+#define LPSPI_CCR_PCSSCK(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
+#define LPSPI_CCR_SCKPCS_MASK                    (0xFF000000U)
+#define LPSPI_CCR_SCKPCS_SHIFT                   (24U)
+#define LPSPI_CCR_SCKPCS(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
+/*! @} */
+
+/*! @name FCR - FIFO Control Register */
+/*! @{ */
+#define LPSPI_FCR_TXWATER_MASK                   (0x3U)
+#define LPSPI_FCR_TXWATER_SHIFT                  (0U)
+#define LPSPI_FCR_TXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
+#define LPSPI_FCR_RXWATER_MASK                   (0x30000U)
+#define LPSPI_FCR_RXWATER_SHIFT                  (16U)
+#define LPSPI_FCR_RXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
+/*! @} */
+
+/*! @name FSR - FIFO Status Register */
+/*! @{ */
+#define LPSPI_FSR_TXCOUNT_MASK                   (0x7U)
+#define LPSPI_FSR_TXCOUNT_SHIFT                  (0U)
+#define LPSPI_FSR_TXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
+#define LPSPI_FSR_RXCOUNT_MASK                   (0x70000U)
+#define LPSPI_FSR_RXCOUNT_SHIFT                  (16U)
+#define LPSPI_FSR_RXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
+/*! @} */
+
+/*! @name TCR - Transmit Command Register */
+/*! @{ */
+#define LPSPI_TCR_FRAMESZ_MASK                   (0xFFFU)
+#define LPSPI_TCR_FRAMESZ_SHIFT                  (0U)
+#define LPSPI_TCR_FRAMESZ(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
+#define LPSPI_TCR_WIDTH_MASK                     (0x30000U)
+#define LPSPI_TCR_WIDTH_SHIFT                    (16U)
+/*! WIDTH - Transfer Width
+ *  0b00..1 bit transfer
+ *  0b01..2 bit transfer
+ *  0b10..4 bit transfer
+ *  0b11..Reserved
+ */
+#define LPSPI_TCR_WIDTH(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
+#define LPSPI_TCR_TXMSK_MASK                     (0x40000U)
+#define LPSPI_TCR_TXMSK_SHIFT                    (18U)
+/*! TXMSK - Transmit Data Mask
+ *  0b0..Normal transfer
+ *  0b1..Mask transmit data
+ */
+#define LPSPI_TCR_TXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
+#define LPSPI_TCR_RXMSK_MASK                     (0x80000U)
+#define LPSPI_TCR_RXMSK_SHIFT                    (19U)
+/*! RXMSK - Receive Data Mask
+ *  0b0..Normal transfer
+ *  0b1..Receive data is masked
+ */
+#define LPSPI_TCR_RXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
+#define LPSPI_TCR_CONTC_MASK                     (0x100000U)
+#define LPSPI_TCR_CONTC_SHIFT                    (20U)
+/*! CONTC - Continuing Command
+ *  0b0..Command word for start of new transfer
+ *  0b1..Command word for continuing transfer
+ */
+#define LPSPI_TCR_CONTC(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
+#define LPSPI_TCR_CONT_MASK                      (0x200000U)
+#define LPSPI_TCR_CONT_SHIFT                     (21U)
+/*! CONT - Continuous Transfer
+ *  0b0..Continuous transfer is disabled
+ *  0b1..Continuous transfer is enabled
+ */
+#define LPSPI_TCR_CONT(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
+#define LPSPI_TCR_BYSW_MASK                      (0x400000U)
+#define LPSPI_TCR_BYSW_SHIFT                     (22U)
+/*! BYSW - Byte Swap
+ *  0b0..Byte swap is disabled
+ *  0b1..Byte swap is enabled
+ */
+#define LPSPI_TCR_BYSW(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
+#define LPSPI_TCR_LSBF_MASK                      (0x800000U)
+#define LPSPI_TCR_LSBF_SHIFT                     (23U)
+/*! LSBF - LSB First
+ *  0b0..Data is transferred MSB first
+ *  0b1..Data is transferred LSB first
+ */
+#define LPSPI_TCR_LSBF(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
+#define LPSPI_TCR_PCS_MASK                       (0x3000000U)
+#define LPSPI_TCR_PCS_SHIFT                      (24U)
+/*! PCS - Peripheral Chip Select
+ *  0b00..Transfer using LPSPI_PCS[0]
+ *  0b01..Transfer using LPSPI_PCS[1]
+ *  0b10..Transfer using LPSPI_PCS[2]
+ *  0b11..Transfer using LPSPI_PCS[3]
+ */
+#define LPSPI_TCR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
+#define LPSPI_TCR_PRESCALE_MASK                  (0x38000000U)
+#define LPSPI_TCR_PRESCALE_SHIFT                 (27U)
+/*! PRESCALE - Prescaler Value
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 4
+ *  0b011..Divide by 8
+ *  0b100..Divide by 16
+ *  0b101..Divide by 32
+ *  0b110..Divide by 64
+ *  0b111..Divide by 128
+ */
+#define LPSPI_TCR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
+#define LPSPI_TCR_CPHA_MASK                      (0x40000000U)
+#define LPSPI_TCR_CPHA_SHIFT                     (30U)
+/*! CPHA - Clock Phase
+ *  0b0..Data is captured on the leading edge of SCK and changed on the following edge of SCK
+ *  0b1..Data is changed on the leading edge of SCK and captured on the following edge of SCK
+ */
+#define LPSPI_TCR_CPHA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
+#define LPSPI_TCR_CPOL_MASK                      (0x80000000U)
+#define LPSPI_TCR_CPOL_SHIFT                     (31U)
+/*! CPOL - Clock Polarity
+ *  0b0..The inactive state value of SCK is low
+ *  0b1..The inactive state value of SCK is high
+ */
+#define LPSPI_TCR_CPOL(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
+/*! @} */
+
+/*! @name TDR - Transmit Data Register */
+/*! @{ */
+#define LPSPI_TDR_DATA_MASK                      (0xFFFFFFFFU)
+#define LPSPI_TDR_DATA_SHIFT                     (0U)
+#define LPSPI_TDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
+/*! @} */
+
+/*! @name RSR - Receive Status Register */
+/*! @{ */
+#define LPSPI_RSR_SOF_MASK                       (0x1U)
+#define LPSPI_RSR_SOF_SHIFT                      (0U)
+/*! SOF - Start Of Frame
+ *  0b0..Subsequent data word received after LPSPI_PCS assertion
+ *  0b1..First data word received after LPSPI_PCS assertion
+ */
+#define LPSPI_RSR_SOF(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
+#define LPSPI_RSR_RXEMPTY_MASK                   (0x2U)
+#define LPSPI_RSR_RXEMPTY_SHIFT                  (1U)
+/*! RXEMPTY - RX FIFO Empty
+ *  0b0..RX FIFO is not empty
+ *  0b1..RX FIFO is empty
+ */
+#define LPSPI_RSR_RXEMPTY(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
+/*! @} */
+
+/*! @name RDR - Receive Data Register */
+/*! @{ */
+#define LPSPI_RDR_DATA_MASK                      (0xFFFFFFFFU)
+#define LPSPI_RDR_DATA_SHIFT                     (0U)
+#define LPSPI_RDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LPSPI_Register_Masks */
+
+
+/* LPSPI - Peripheral instance base addresses */
+/** Peripheral LPSPI0 base address */
+#define LPSPI0_BASE                              (0x4003F000u)
+/** Peripheral LPSPI0 base pointer */
+#define LPSPI0                                   ((LPSPI_Type *)LPSPI0_BASE)
+/** Peripheral LPSPI1 base address */
+#define LPSPI1_BASE                              (0x40040000u)
+/** Peripheral LPSPI1 base pointer */
+#define LPSPI1                                   ((LPSPI_Type *)LPSPI1_BASE)
+/** Peripheral LPSPI2 base address */
+#define LPSPI2_BASE                              (0x40041000u)
+/** Peripheral LPSPI2 base pointer */
+#define LPSPI2                                   ((LPSPI_Type *)LPSPI2_BASE)
+/** Peripheral LPSPI3 base address */
+#define LPSPI3_BASE                              (0x41035000u)
+/** Peripheral LPSPI3 base pointer */
+#define LPSPI3                                   ((LPSPI_Type *)LPSPI3_BASE)
+/** Array initializer of LPSPI peripheral base addresses */
+#define LPSPI_BASE_ADDRS                         { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE }
+/** Array initializer of LPSPI peripheral base pointers */
+#define LPSPI_BASE_PTRS                          { LPSPI0, LPSPI1, LPSPI2, LPSPI3 }
+/** Interrupt vectors for the LPSPI peripheral type */
+#define LPSPI_IRQS                               { LPSPI0_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPSPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CSR;                               /**< Low Power Timer Control Status Register, offset: 0x0 */
+  __IO uint32_t PSR;                               /**< Low Power Timer Prescale Register, offset: 0x4 */
+  __IO uint32_t CMR;                               /**< Low Power Timer Compare Register, offset: 0x8 */
+  __IO uint32_t CNR;                               /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/*! @name CSR - Low Power Timer Control Status Register */
+/*! @{ */
+#define LPTMR_CSR_TEN_MASK                       (0x1U)
+#define LPTMR_CSR_TEN_SHIFT                      (0U)
+/*! TEN - Timer Enable
+ *  0b0..LPTMR is disabled and internal logic is reset.
+ *  0b1..LPTMR is enabled.
+ */
+#define LPTMR_CSR_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
+#define LPTMR_CSR_TMS_MASK                       (0x2U)
+#define LPTMR_CSR_TMS_SHIFT                      (1U)
+/*! TMS - Timer Mode Select
+ *  0b0..Time Counter mode.
+ *  0b1..Pulse Counter mode.
+ */
+#define LPTMR_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
+#define LPTMR_CSR_TFC_MASK                       (0x4U)
+#define LPTMR_CSR_TFC_SHIFT                      (2U)
+/*! TFC - Timer Free-Running Counter
+ *  0b0..CNR is reset whenever TCF is set.
+ *  0b1..CNR is reset on overflow.
+ */
+#define LPTMR_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
+#define LPTMR_CSR_TPP_MASK                       (0x8U)
+#define LPTMR_CSR_TPP_SHIFT                      (3U)
+/*! TPP - Timer Pin Polarity
+ *  0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.
+ *  0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.
+ */
+#define LPTMR_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
+#define LPTMR_CSR_TPS_MASK                       (0x30U)
+#define LPTMR_CSR_TPS_SHIFT                      (4U)
+/*! TPS - Timer Pin Select
+ *  0b00..Pulse counter input 0 is selected.
+ *  0b01..Pulse counter input 1 is selected.
+ *  0b10..Pulse counter input 2 is selected.
+ *  0b11..Pulse counter input 3 is selected.
+ */
+#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK                       (0x40U)
+#define LPTMR_CSR_TIE_SHIFT                      (6U)
+/*! TIE - Timer Interrupt Enable
+ *  0b0..Timer interrupt disabled.
+ *  0b1..Timer interrupt enabled.
+ */
+#define LPTMR_CSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
+#define LPTMR_CSR_TCF_MASK                       (0x80U)
+#define LPTMR_CSR_TCF_SHIFT                      (7U)
+/*! TCF - Timer Compare Flag
+ *  0b0..The value of CNR is not equal to CMR and increments.
+ *  0b1..The value of CNR is equal to CMR and increments.
+ */
+#define LPTMR_CSR_TCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
+#define LPTMR_CSR_TDRE_MASK                      (0x100U)
+#define LPTMR_CSR_TDRE_SHIFT                     (8U)
+/*! TDRE - Timer DMA Request Enable
+ *  0b0..Timer DMA Request disabled.
+ *  0b1..Timer DMA Request enabled.
+ */
+#define LPTMR_CSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK)
+/*! @} */
+
+/*! @name PSR - Low Power Timer Prescale Register */
+/*! @{ */
+#define LPTMR_PSR_PCS_MASK                       (0x3U)
+#define LPTMR_PSR_PCS_SHIFT                      (0U)
+/*! PCS - Prescaler Clock Select
+ *  0b00..Prescaler/glitch filter clock 0 selected.
+ *  0b01..Prescaler/glitch filter clock 1 selected.
+ *  0b10..Prescaler/glitch filter clock 2 selected.
+ *  0b11..Prescaler/glitch filter clock 3 selected.
+ */
+#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK                      (0x4U)
+#define LPTMR_PSR_PBYP_SHIFT                     (2U)
+/*! PBYP - Prescaler Bypass
+ *  0b0..Prescaler/glitch filter is enabled.
+ *  0b1..Prescaler/glitch filter is bypassed.
+ */
+#define LPTMR_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
+#define LPTMR_PSR_PRESCALE_MASK                  (0x78U)
+#define LPTMR_PSR_PRESCALE_SHIFT                 (3U)
+/*! PRESCALE - Prescale Value
+ *  0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.
+ *  0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.
+ *  0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.
+ *  0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.
+ *  0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.
+ *  0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.
+ *  0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.
+ *  0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.
+ *  0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.
+ *  0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.
+ *  0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.
+ *  0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.
+ *  0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.
+ *  0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.
+ *  0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.
+ *  0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.
+ */
+#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
+/*! @} */
+
+/*! @name CMR - Low Power Timer Compare Register */
+/*! @{ */
+#define LPTMR_CMR_COMPARE_MASK                   (0xFFFFFFFFU)
+#define LPTMR_CMR_COMPARE_SHIFT                  (0U)
+#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
+/*! @} */
+
+/*! @name CNR - Low Power Timer Counter Register */
+/*! @{ */
+#define LPTMR_CNR_COUNTER_MASK                   (0xFFFFFFFFU)
+#define LPTMR_CNR_COUNTER_SHIFT                  (0U)
+#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE                              (0x40032000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
+/** Peripheral LPTMR1 base address */
+#define LPTMR1_BASE                              (0x40033000u)
+/** Peripheral LPTMR1 base pointer */
+#define LPTMR1                                   ((LPTMR_Type *)LPTMR1_BASE)
+/** Peripheral LPTMR2 base address */
+#define LPTMR2_BASE                              (0x4102B000u)
+/** Peripheral LPTMR2 base pointer */
+#define LPTMR2                                   ((LPTMR_Type *)LPTMR2_BASE)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS                         { LPTMR0_BASE, LPTMR1_BASE, LPTMR2_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS                          { LPTMR0, LPTMR1, LPTMR2 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS                               { LPTMR0_IRQn, LPTMR1_IRQn, LPTMR2_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPUART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
+ * @{
+ */
+
+/** LPUART - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __IO uint32_t GLOBAL;                            /**< LPUART Global Register, offset: 0x8 */
+  __IO uint32_t PINCFG;                            /**< LPUART Pin Configuration Register, offset: 0xC */
+  __IO uint32_t BAUD;                              /**< LPUART Baud Rate Register, offset: 0x10 */
+  __IO uint32_t STAT;                              /**< LPUART Status Register, offset: 0x14 */
+  __IO uint32_t CTRL;                              /**< LPUART Control Register, offset: 0x18 */
+  __IO uint32_t DATA;                              /**< LPUART Data Register, offset: 0x1C */
+  __IO uint32_t MATCH;                             /**< LPUART Match Address Register, offset: 0x20 */
+  __IO uint32_t MODIR;                             /**< LPUART Modem IrDA Register, offset: 0x24 */
+  __IO uint32_t FIFO;                              /**< LPUART FIFO Register, offset: 0x28 */
+  __IO uint32_t WATER;                             /**< LPUART Watermark Register, offset: 0x2C */
+} LPUART_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPUART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Register_Masks LPUART Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define LPUART_VERID_FEATURE_MASK                (0xFFFFU)
+#define LPUART_VERID_FEATURE_SHIFT               (0U)
+/*! FEATURE - Feature Identification Number
+ *  0b0000000000000001..Standard feature set.
+ *  0b0000000000000011..Standard feature set with MODEM/IrDA support.
+ */
+#define LPUART_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
+#define LPUART_VERID_MINOR_MASK                  (0xFF0000U)
+#define LPUART_VERID_MINOR_SHIFT                 (16U)
+#define LPUART_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
+#define LPUART_VERID_MAJOR_MASK                  (0xFF000000U)
+#define LPUART_VERID_MAJOR_SHIFT                 (24U)
+#define LPUART_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define LPUART_PARAM_TXFIFO_MASK                 (0xFFU)
+#define LPUART_PARAM_TXFIFO_SHIFT                (0U)
+#define LPUART_PARAM_TXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
+#define LPUART_PARAM_RXFIFO_MASK                 (0xFF00U)
+#define LPUART_PARAM_RXFIFO_SHIFT                (8U)
+#define LPUART_PARAM_RXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
+/*! @} */
+
+/*! @name GLOBAL - LPUART Global Register */
+/*! @{ */
+#define LPUART_GLOBAL_RST_MASK                   (0x2U)
+#define LPUART_GLOBAL_RST_SHIFT                  (1U)
+/*! RST - Software Reset
+ *  0b0..Module is not reset.
+ *  0b1..Module is reset.
+ */
+#define LPUART_GLOBAL_RST(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
+/*! @} */
+
+/*! @name PINCFG - LPUART Pin Configuration Register */
+/*! @{ */
+#define LPUART_PINCFG_TRGSEL_MASK                (0x3U)
+#define LPUART_PINCFG_TRGSEL_SHIFT               (0U)
+/*! TRGSEL - Trigger Select
+ *  0b00..Input trigger is disabled.
+ *  0b01..Input trigger is used instead of RXD pin input.
+ *  0b10..Input trigger is used instead of CTS_B pin input.
+ *  0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger.
+ */
+#define LPUART_PINCFG_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
+/*! @} */
+
+/*! @name BAUD - LPUART Baud Rate Register */
+/*! @{ */
+#define LPUART_BAUD_SBR_MASK                     (0x1FFFU)
+#define LPUART_BAUD_SBR_SHIFT                    (0U)
+#define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
+#define LPUART_BAUD_SBNS_MASK                    (0x2000U)
+#define LPUART_BAUD_SBNS_SHIFT                   (13U)
+/*! SBNS - Stop Bit Number Select
+ *  0b0..One stop bit.
+ *  0b1..Two stop bits.
+ */
+#define LPUART_BAUD_SBNS(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
+#define LPUART_BAUD_RXEDGIE_MASK                 (0x4000U)
+#define LPUART_BAUD_RXEDGIE_SHIFT                (14U)
+/*! RXEDGIE - RX Input Active Edge Interrupt Enable
+ *  0b0..Hardware interrupts from LPUART_STAT[RXEDGIF] disabled.
+ *  0b1..Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1.
+ */
+#define LPUART_BAUD_RXEDGIE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
+#define LPUART_BAUD_LBKDIE_MASK                  (0x8000U)
+#define LPUART_BAUD_LBKDIE_SHIFT                 (15U)
+/*! LBKDIE - LIN Break Detect Interrupt Enable
+ *  0b0..Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling).
+ *  0b1..Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1.
+ */
+#define LPUART_BAUD_LBKDIE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
+#define LPUART_BAUD_RESYNCDIS_MASK               (0x10000U)
+#define LPUART_BAUD_RESYNCDIS_SHIFT              (16U)
+/*! RESYNCDIS - Resynchronization Disable
+ *  0b0..Resynchronization during received data word is supported
+ *  0b1..Resynchronization during received data word is disabled
+ */
+#define LPUART_BAUD_RESYNCDIS(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
+#define LPUART_BAUD_BOTHEDGE_MASK                (0x20000U)
+#define LPUART_BAUD_BOTHEDGE_SHIFT               (17U)
+/*! BOTHEDGE - Both Edge Sampling
+ *  0b0..Receiver samples input data using the rising edge of the baud rate clock.
+ *  0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.
+ */
+#define LPUART_BAUD_BOTHEDGE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
+#define LPUART_BAUD_MATCFG_MASK                  (0xC0000U)
+#define LPUART_BAUD_MATCFG_SHIFT                 (18U)
+/*! MATCFG - Match Configuration
+ *  0b00..Address Match Wakeup
+ *  0b01..Idle Match Wakeup
+ *  0b10..Match On and Match Off
+ *  0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input
+ */
+#define LPUART_BAUD_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
+#define LPUART_BAUD_RIDMAE_MASK                  (0x100000U)
+#define LPUART_BAUD_RIDMAE_SHIFT                 (20U)
+/*! RIDMAE - Receiver Idle DMA Enable
+ *  0b0..DMA request disabled.
+ *  0b1..DMA request enabled.
+ */
+#define LPUART_BAUD_RIDMAE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)
+#define LPUART_BAUD_RDMAE_MASK                   (0x200000U)
+#define LPUART_BAUD_RDMAE_SHIFT                  (21U)
+/*! RDMAE - Receiver Full DMA Enable
+ *  0b0..DMA request disabled.
+ *  0b1..DMA request enabled.
+ */
+#define LPUART_BAUD_RDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
+#define LPUART_BAUD_TDMAE_MASK                   (0x800000U)
+#define LPUART_BAUD_TDMAE_SHIFT                  (23U)
+/*! TDMAE - Transmitter DMA Enable
+ *  0b0..DMA request disabled.
+ *  0b1..DMA request enabled.
+ */
+#define LPUART_BAUD_TDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
+#define LPUART_BAUD_OSR_MASK                     (0x1F000000U)
+#define LPUART_BAUD_OSR_SHIFT                    (24U)
+/*! OSR - Oversampling Ratio
+ *  0b00000..Writing 0 to this field will result in an oversampling ratio of 16
+ *  0b00001..Reserved
+ *  0b00010..Reserved
+ *  0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set.
+ *  0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set.
+ *  0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set.
+ *  0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set.
+ *  0b00111..Oversampling ratio of 8.
+ *  0b01000..Oversampling ratio of 9.
+ *  0b01001..Oversampling ratio of 10.
+ *  0b01010..Oversampling ratio of 11.
+ *  0b01011..Oversampling ratio of 12.
+ *  0b01100..Oversampling ratio of 13.
+ *  0b01101..Oversampling ratio of 14.
+ *  0b01110..Oversampling ratio of 15.
+ *  0b01111..Oversampling ratio of 16.
+ *  0b10000..Oversampling ratio of 17.
+ *  0b10001..Oversampling ratio of 18.
+ *  0b10010..Oversampling ratio of 19.
+ *  0b10011..Oversampling ratio of 20.
+ *  0b10100..Oversampling ratio of 21.
+ *  0b10101..Oversampling ratio of 22.
+ *  0b10110..Oversampling ratio of 23.
+ *  0b10111..Oversampling ratio of 24.
+ *  0b11000..Oversampling ratio of 25.
+ *  0b11001..Oversampling ratio of 26.
+ *  0b11010..Oversampling ratio of 27.
+ *  0b11011..Oversampling ratio of 28.
+ *  0b11100..Oversampling ratio of 29.
+ *  0b11101..Oversampling ratio of 30.
+ *  0b11110..Oversampling ratio of 31.
+ *  0b11111..Oversampling ratio of 32.
+ */
+#define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
+#define LPUART_BAUD_M10_MASK                     (0x20000000U)
+#define LPUART_BAUD_M10_SHIFT                    (29U)
+/*! M10 - 10-bit Mode select
+ *  0b0..Receiver and transmitter use 7-bit to 9-bit data characters.
+ *  0b1..Receiver and transmitter use 10-bit data characters.
+ */
+#define LPUART_BAUD_M10(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
+#define LPUART_BAUD_MAEN2_MASK                   (0x40000000U)
+#define LPUART_BAUD_MAEN2_SHIFT                  (30U)
+/*! MAEN2 - Match Address Mode Enable 2
+ *  0b0..Normal operation.
+ *  0b1..Enables automatic address matching or data matching mode for MATCH[MA2].
+ */
+#define LPUART_BAUD_MAEN2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
+#define LPUART_BAUD_MAEN1_MASK                   (0x80000000U)
+#define LPUART_BAUD_MAEN1_SHIFT                  (31U)
+/*! MAEN1 - Match Address Mode Enable 1
+ *  0b0..Normal operation.
+ *  0b1..Enables automatic address matching or data matching mode for MATCH[MA1].
+ */
+#define LPUART_BAUD_MAEN1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
+/*! @} */
+
+/*! @name STAT - LPUART Status Register */
+/*! @{ */
+#define LPUART_STAT_MA2F_MASK                    (0x4000U)
+#define LPUART_STAT_MA2F_SHIFT                   (14U)
+/*! MA2F - Match 2 Flag
+ *  0b0..Received data is not equal to MA2
+ *  0b1..Received data is equal to MA2
+ */
+#define LPUART_STAT_MA2F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
+#define LPUART_STAT_MA1F_MASK                    (0x8000U)
+#define LPUART_STAT_MA1F_SHIFT                   (15U)
+/*! MA1F - Match 1 Flag
+ *  0b0..Received data is not equal to MA1
+ *  0b1..Received data is equal to MA1
+ */
+#define LPUART_STAT_MA1F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
+#define LPUART_STAT_PF_MASK                      (0x10000U)
+#define LPUART_STAT_PF_SHIFT                     (16U)
+/*! PF - Parity Error Flag
+ *  0b0..No parity error.
+ *  0b1..Parity error.
+ */
+#define LPUART_STAT_PF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
+#define LPUART_STAT_FE_MASK                      (0x20000U)
+#define LPUART_STAT_FE_SHIFT                     (17U)
+/*! FE - Framing Error Flag
+ *  0b0..No framing error detected. This does not guarantee the framing is correct.
+ *  0b1..Framing error.
+ */
+#define LPUART_STAT_FE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
+#define LPUART_STAT_NF_MASK                      (0x40000U)
+#define LPUART_STAT_NF_SHIFT                     (18U)
+/*! NF - Noise Flag
+ *  0b0..No noise detected.
+ *  0b1..Noise detected in the received character in LPUART_DATA.
+ */
+#define LPUART_STAT_NF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
+#define LPUART_STAT_OR_MASK                      (0x80000U)
+#define LPUART_STAT_OR_SHIFT                     (19U)
+/*! OR - Receiver Overrun Flag
+ *  0b0..No overrun.
+ *  0b1..Receive overrun (new LPUART data lost).
+ */
+#define LPUART_STAT_OR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
+#define LPUART_STAT_IDLE_MASK                    (0x100000U)
+#define LPUART_STAT_IDLE_SHIFT                   (20U)
+/*! IDLE - Idle Line Flag
+ *  0b0..No idle line detected.
+ *  0b1..Idle line was detected.
+ */
+#define LPUART_STAT_IDLE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
+#define LPUART_STAT_RDRF_MASK                    (0x200000U)
+#define LPUART_STAT_RDRF_SHIFT                   (21U)
+/*! RDRF - Receive Data Register Full Flag
+ *  0b0..Receive data buffer empty.
+ *  0b1..Receive data buffer full.
+ */
+#define LPUART_STAT_RDRF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
+#define LPUART_STAT_TC_MASK                      (0x400000U)
+#define LPUART_STAT_TC_SHIFT                     (22U)
+/*! TC - Transmission Complete Flag
+ *  0b0..Transmitter active (sending data, a preamble, or a break).
+ *  0b1..Transmitter idle (transmission activity complete).
+ */
+#define LPUART_STAT_TC(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
+#define LPUART_STAT_TDRE_MASK                    (0x800000U)
+#define LPUART_STAT_TDRE_SHIFT                   (23U)
+/*! TDRE - Transmit Data Register Empty Flag
+ *  0b0..Transmit data buffer full.
+ *  0b1..Transmit data buffer empty.
+ */
+#define LPUART_STAT_TDRE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
+#define LPUART_STAT_RAF_MASK                     (0x1000000U)
+#define LPUART_STAT_RAF_SHIFT                    (24U)
+/*! RAF - Receiver Active Flag
+ *  0b0..LPUART receiver idle waiting for a start bit.
+ *  0b1..LPUART receiver active (RXD input not idle).
+ */
+#define LPUART_STAT_RAF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
+#define LPUART_STAT_LBKDE_MASK                   (0x2000000U)
+#define LPUART_STAT_LBKDE_SHIFT                  (25U)
+/*! LBKDE - LIN Break Detection Enable
+ *  0b0..LIN break detect is disabled, normal break character can be detected.
+ *  0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1).
+ */
+#define LPUART_STAT_LBKDE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
+#define LPUART_STAT_BRK13_MASK                   (0x4000000U)
+#define LPUART_STAT_BRK13_SHIFT                  (26U)
+/*! BRK13 - Break Character Generation Length
+ *  0b0..Break character is transmitted with length of 9 to 13 bit times.
+ *  0b1..Break character is transmitted with length of 12 to 15 bit times.
+ */
+#define LPUART_STAT_BRK13(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
+#define LPUART_STAT_RWUID_MASK                   (0x8000000U)
+#define LPUART_STAT_RWUID_SHIFT                  (27U)
+/*! RWUID - Receive Wake Up Idle Detect
+ *  0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match.
+ *  0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match.
+ */
+#define LPUART_STAT_RWUID(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
+#define LPUART_STAT_RXINV_MASK                   (0x10000000U)
+#define LPUART_STAT_RXINV_SHIFT                  (28U)
+/*! RXINV - Receive Data Inversion
+ *  0b0..Receive data not inverted.
+ *  0b1..Receive data inverted.
+ */
+#define LPUART_STAT_RXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
+#define LPUART_STAT_MSBF_MASK                    (0x20000000U)
+#define LPUART_STAT_MSBF_SHIFT                   (29U)
+/*! MSBF - MSB First
+ *  0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
+ *  0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].
+ */
+#define LPUART_STAT_MSBF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
+#define LPUART_STAT_RXEDGIF_MASK                 (0x40000000U)
+#define LPUART_STAT_RXEDGIF_SHIFT                (30U)
+/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag
+ *  0b0..No active edge on the receive pin has occurred.
+ *  0b1..An active edge on the receive pin has occurred.
+ */
+#define LPUART_STAT_RXEDGIF(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
+#define LPUART_STAT_LBKDIF_MASK                  (0x80000000U)
+#define LPUART_STAT_LBKDIF_SHIFT                 (31U)
+/*! LBKDIF - LIN Break Detect Interrupt Flag
+ *  0b0..No LIN break character has been detected.
+ *  0b1..LIN break character has been detected.
+ */
+#define LPUART_STAT_LBKDIF(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
+/*! @} */
+
+/*! @name CTRL - LPUART Control Register */
+/*! @{ */
+#define LPUART_CTRL_PT_MASK                      (0x1U)
+#define LPUART_CTRL_PT_SHIFT                     (0U)
+/*! PT - Parity Type
+ *  0b0..Even parity.
+ *  0b1..Odd parity.
+ */
+#define LPUART_CTRL_PT(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
+#define LPUART_CTRL_PE_MASK                      (0x2U)
+#define LPUART_CTRL_PE_SHIFT                     (1U)
+/*! PE - Parity Enable
+ *  0b0..No hardware parity generation or checking.
+ *  0b1..Parity enabled.
+ */
+#define LPUART_CTRL_PE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
+#define LPUART_CTRL_ILT_MASK                     (0x4U)
+#define LPUART_CTRL_ILT_SHIFT                    (2U)
+/*! ILT - Idle Line Type Select
+ *  0b0..Idle character bit count starts after start bit.
+ *  0b1..Idle character bit count starts after stop bit.
+ */
+#define LPUART_CTRL_ILT(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
+#define LPUART_CTRL_WAKE_MASK                    (0x8U)
+#define LPUART_CTRL_WAKE_SHIFT                   (3U)
+/*! WAKE - Receiver Wakeup Method Select
+ *  0b0..Configures RWU for idle-line wakeup.
+ *  0b1..Configures RWU with address-mark wakeup.
+ */
+#define LPUART_CTRL_WAKE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
+#define LPUART_CTRL_M_MASK                       (0x10U)
+#define LPUART_CTRL_M_SHIFT                      (4U)
+/*! M - 9-Bit or 8-Bit Mode Select
+ *  0b0..Receiver and transmitter use 8-bit data characters.
+ *  0b1..Receiver and transmitter use 9-bit data characters.
+ */
+#define LPUART_CTRL_M(x)                         (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
+#define LPUART_CTRL_RSRC_MASK                    (0x20U)
+#define LPUART_CTRL_RSRC_SHIFT                   (5U)
+/*! RSRC - Receiver Source Select
+ *  0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin.
+ *  0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input.
+ */
+#define LPUART_CTRL_RSRC(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
+#define LPUART_CTRL_DOZEEN_MASK                  (0x40U)
+#define LPUART_CTRL_DOZEEN_SHIFT                 (6U)
+/*! DOZEEN - Doze Enable
+ *  0b0..LPUART is enabled in Doze mode.
+ *  0b1..LPUART is disabled in Doze mode.
+ */
+#define LPUART_CTRL_DOZEEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
+#define LPUART_CTRL_LOOPS_MASK                   (0x80U)
+#define LPUART_CTRL_LOOPS_SHIFT                  (7U)
+/*! LOOPS - Loop Mode Select
+ *  0b0..Normal operation - RXD and TXD use separate pins.
+ *  0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
+ */
+#define LPUART_CTRL_LOOPS(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
+#define LPUART_CTRL_IDLECFG_MASK                 (0x700U)
+#define LPUART_CTRL_IDLECFG_SHIFT                (8U)
+/*! IDLECFG - Idle Configuration
+ *  0b000..1 idle character
+ *  0b001..2 idle characters
+ *  0b010..4 idle characters
+ *  0b011..8 idle characters
+ *  0b100..16 idle characters
+ *  0b101..32 idle characters
+ *  0b110..64 idle characters
+ *  0b111..128 idle characters
+ */
+#define LPUART_CTRL_IDLECFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
+#define LPUART_CTRL_M7_MASK                      (0x800U)
+#define LPUART_CTRL_M7_SHIFT                     (11U)
+/*! M7 - 7-Bit Mode Select
+ *  0b0..Receiver and transmitter use 8-bit to 10-bit data characters.
+ *  0b1..Receiver and transmitter use 7-bit data characters.
+ */
+#define LPUART_CTRL_M7(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)
+#define LPUART_CTRL_MA2IE_MASK                   (0x4000U)
+#define LPUART_CTRL_MA2IE_SHIFT                  (14U)
+/*! MA2IE - Match 2 Interrupt Enable
+ *  0b0..MA2F interrupt disabled
+ *  0b1..MA2F interrupt enabled
+ */
+#define LPUART_CTRL_MA2IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
+#define LPUART_CTRL_MA1IE_MASK                   (0x8000U)
+#define LPUART_CTRL_MA1IE_SHIFT                  (15U)
+/*! MA1IE - Match 1 Interrupt Enable
+ *  0b0..MA1F interrupt disabled
+ *  0b1..MA1F interrupt enabled
+ */
+#define LPUART_CTRL_MA1IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
+#define LPUART_CTRL_SBK_MASK                     (0x10000U)
+#define LPUART_CTRL_SBK_SHIFT                    (16U)
+/*! SBK - Send Break
+ *  0b0..Normal transmitter operation.
+ *  0b1..Queue break character(s) to be sent.
+ */
+#define LPUART_CTRL_SBK(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
+#define LPUART_CTRL_RWU_MASK                     (0x20000U)
+#define LPUART_CTRL_RWU_SHIFT                    (17U)
+/*! RWU - Receiver Wakeup Control
+ *  0b0..Normal receiver operation.
+ *  0b1..LPUART receiver in standby waiting for wakeup condition.
+ */
+#define LPUART_CTRL_RWU(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
+#define LPUART_CTRL_RE_MASK                      (0x40000U)
+#define LPUART_CTRL_RE_SHIFT                     (18U)
+/*! RE - Receiver Enable
+ *  0b0..Receiver disabled.
+ *  0b1..Receiver enabled.
+ */
+#define LPUART_CTRL_RE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
+#define LPUART_CTRL_TE_MASK                      (0x80000U)
+#define LPUART_CTRL_TE_SHIFT                     (19U)
+/*! TE - Transmitter Enable
+ *  0b0..Transmitter disabled.
+ *  0b1..Transmitter enabled.
+ */
+#define LPUART_CTRL_TE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
+#define LPUART_CTRL_ILIE_MASK                    (0x100000U)
+#define LPUART_CTRL_ILIE_SHIFT                   (20U)
+/*! ILIE - Idle Line Interrupt Enable
+ *  0b0..Hardware interrupts from IDLE disabled; use polling.
+ *  0b1..Hardware interrupt requested when IDLE flag is 1.
+ */
+#define LPUART_CTRL_ILIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
+#define LPUART_CTRL_RIE_MASK                     (0x200000U)
+#define LPUART_CTRL_RIE_SHIFT                    (21U)
+/*! RIE - Receiver Interrupt Enable
+ *  0b0..Hardware interrupts from RDRF disabled; use polling.
+ *  0b1..Hardware interrupt requested when RDRF flag is 1.
+ */
+#define LPUART_CTRL_RIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
+#define LPUART_CTRL_TCIE_MASK                    (0x400000U)
+#define LPUART_CTRL_TCIE_SHIFT                   (22U)
+/*! TCIE - Transmission Complete Interrupt Enable for
+ *  0b0..Hardware interrupts from TC disabled; use polling.
+ *  0b1..Hardware interrupt requested when TC flag is 1.
+ */
+#define LPUART_CTRL_TCIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
+#define LPUART_CTRL_TIE_MASK                     (0x800000U)
+#define LPUART_CTRL_TIE_SHIFT                    (23U)
+/*! TIE - Transmit Interrupt Enable
+ *  0b0..Hardware interrupts from TDRE disabled; use polling.
+ *  0b1..Hardware interrupt requested when TDRE flag is 1.
+ */
+#define LPUART_CTRL_TIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
+#define LPUART_CTRL_PEIE_MASK                    (0x1000000U)
+#define LPUART_CTRL_PEIE_SHIFT                   (24U)
+/*! PEIE - Parity Error Interrupt Enable
+ *  0b0..PF interrupts disabled; use polling).
+ *  0b1..Hardware interrupt requested when PF is set.
+ */
+#define LPUART_CTRL_PEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
+#define LPUART_CTRL_FEIE_MASK                    (0x2000000U)
+#define LPUART_CTRL_FEIE_SHIFT                   (25U)
+/*! FEIE - Framing Error Interrupt Enable
+ *  0b0..FE interrupts disabled; use polling.
+ *  0b1..Hardware interrupt requested when FE is set.
+ */
+#define LPUART_CTRL_FEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
+#define LPUART_CTRL_NEIE_MASK                    (0x4000000U)
+#define LPUART_CTRL_NEIE_SHIFT                   (26U)
+/*! NEIE - Noise Error Interrupt Enable
+ *  0b0..NF interrupts disabled; use polling.
+ *  0b1..Hardware interrupt requested when NF is set.
+ */
+#define LPUART_CTRL_NEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
+#define LPUART_CTRL_ORIE_MASK                    (0x8000000U)
+#define LPUART_CTRL_ORIE_SHIFT                   (27U)
+/*! ORIE - Overrun Interrupt Enable
+ *  0b0..OR interrupts disabled; use polling.
+ *  0b1..Hardware interrupt requested when OR is set.
+ */
+#define LPUART_CTRL_ORIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
+#define LPUART_CTRL_TXINV_MASK                   (0x10000000U)
+#define LPUART_CTRL_TXINV_SHIFT                  (28U)
+/*! TXINV - Transmit Data Inversion
+ *  0b0..Transmit data not inverted.
+ *  0b1..Transmit data inverted.
+ */
+#define LPUART_CTRL_TXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
+#define LPUART_CTRL_TXDIR_MASK                   (0x20000000U)
+#define LPUART_CTRL_TXDIR_SHIFT                  (29U)
+/*! TXDIR - TXD Pin Direction in Single-Wire Mode
+ *  0b0..TXD pin is an input in single-wire mode.
+ *  0b1..TXD pin is an output in single-wire mode.
+ */
+#define LPUART_CTRL_TXDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
+#define LPUART_CTRL_R9T8_MASK                    (0x40000000U)
+#define LPUART_CTRL_R9T8_SHIFT                   (30U)
+#define LPUART_CTRL_R9T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
+#define LPUART_CTRL_R8T9_MASK                    (0x80000000U)
+#define LPUART_CTRL_R8T9_SHIFT                   (31U)
+#define LPUART_CTRL_R8T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
+/*! @} */
+
+/*! @name DATA - LPUART Data Register */
+/*! @{ */
+#define LPUART_DATA_R0T0_MASK                    (0x1U)
+#define LPUART_DATA_R0T0_SHIFT                   (0U)
+#define LPUART_DATA_R0T0(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
+#define LPUART_DATA_R1T1_MASK                    (0x2U)
+#define LPUART_DATA_R1T1_SHIFT                   (1U)
+#define LPUART_DATA_R1T1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
+#define LPUART_DATA_R2T2_MASK                    (0x4U)
+#define LPUART_DATA_R2T2_SHIFT                   (2U)
+#define LPUART_DATA_R2T2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
+#define LPUART_DATA_R3T3_MASK                    (0x8U)
+#define LPUART_DATA_R3T3_SHIFT                   (3U)
+#define LPUART_DATA_R3T3(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
+#define LPUART_DATA_R4T4_MASK                    (0x10U)
+#define LPUART_DATA_R4T4_SHIFT                   (4U)
+#define LPUART_DATA_R4T4(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
+#define LPUART_DATA_R5T5_MASK                    (0x20U)
+#define LPUART_DATA_R5T5_SHIFT                   (5U)
+#define LPUART_DATA_R5T5(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
+#define LPUART_DATA_R6T6_MASK                    (0x40U)
+#define LPUART_DATA_R6T6_SHIFT                   (6U)
+#define LPUART_DATA_R6T6(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
+#define LPUART_DATA_R7T7_MASK                    (0x80U)
+#define LPUART_DATA_R7T7_SHIFT                   (7U)
+#define LPUART_DATA_R7T7(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
+#define LPUART_DATA_R8T8_MASK                    (0x100U)
+#define LPUART_DATA_R8T8_SHIFT                   (8U)
+#define LPUART_DATA_R8T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
+#define LPUART_DATA_R9T9_MASK                    (0x200U)
+#define LPUART_DATA_R9T9_SHIFT                   (9U)
+#define LPUART_DATA_R9T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
+#define LPUART_DATA_IDLINE_MASK                  (0x800U)
+#define LPUART_DATA_IDLINE_SHIFT                 (11U)
+/*! IDLINE - Idle Line
+ *  0b0..Receiver was not idle before receiving this character.
+ *  0b1..Receiver was idle before receiving this character.
+ */
+#define LPUART_DATA_IDLINE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
+#define LPUART_DATA_RXEMPT_MASK                  (0x1000U)
+#define LPUART_DATA_RXEMPT_SHIFT                 (12U)
+/*! RXEMPT - Receive Buffer Empty
+ *  0b0..Receive buffer contains valid data.
+ *  0b1..Receive buffer is empty, data returned on read is not valid.
+ */
+#define LPUART_DATA_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
+#define LPUART_DATA_FRETSC_MASK                  (0x2000U)
+#define LPUART_DATA_FRETSC_SHIFT                 (13U)
+/*! FRETSC - Frame Error / Transmit Special Character
+ *  0b0..The dataword was received without a frame error on read, or transmit a normal character on write.
+ *  0b1..The dataword was received with a frame error, or transmit an idle or break character on transmit.
+ */
+#define LPUART_DATA_FRETSC(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
+#define LPUART_DATA_PARITYE_MASK                 (0x4000U)
+#define LPUART_DATA_PARITYE_SHIFT                (14U)
+/*! PARITYE - PARITYE
+ *  0b0..The dataword was received without a parity error.
+ *  0b1..The dataword was received with a parity error.
+ */
+#define LPUART_DATA_PARITYE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
+#define LPUART_DATA_NOISY_MASK                   (0x8000U)
+#define LPUART_DATA_NOISY_SHIFT                  (15U)
+/*! NOISY - NOISY
+ *  0b0..The dataword was received without noise.
+ *  0b1..The data was received with noise.
+ */
+#define LPUART_DATA_NOISY(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
+/*! @} */
+
+/*! @name MATCH - LPUART Match Address Register */
+/*! @{ */
+#define LPUART_MATCH_MA1_MASK                    (0x3FFU)
+#define LPUART_MATCH_MA1_SHIFT                   (0U)
+#define LPUART_MATCH_MA1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
+#define LPUART_MATCH_MA2_MASK                    (0x3FF0000U)
+#define LPUART_MATCH_MA2_SHIFT                   (16U)
+#define LPUART_MATCH_MA2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
+/*! @} */
+
+/*! @name MODIR - LPUART Modem IrDA Register */
+/*! @{ */
+#define LPUART_MODIR_TXCTSE_MASK                 (0x1U)
+#define LPUART_MODIR_TXCTSE_SHIFT                (0U)
+/*! TXCTSE - Transmitter clear-to-send enable
+ *  0b0..CTS has no effect on the transmitter.
+ *  0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
+ */
+#define LPUART_MODIR_TXCTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
+#define LPUART_MODIR_TXRTSE_MASK                 (0x2U)
+#define LPUART_MODIR_TXRTSE_SHIFT                (1U)
+/*! TXRTSE - Transmitter request-to-send enable
+ *  0b0..The transmitter has no effect on RTS.
+ *  0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit.
+ */
+#define LPUART_MODIR_TXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
+#define LPUART_MODIR_TXRTSPOL_MASK               (0x4U)
+#define LPUART_MODIR_TXRTSPOL_SHIFT              (2U)
+/*! TXRTSPOL - Transmitter request-to-send polarity
+ *  0b0..Transmitter RTS is active low.
+ *  0b1..Transmitter RTS is active high.
+ */
+#define LPUART_MODIR_TXRTSPOL(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
+#define LPUART_MODIR_RXRTSE_MASK                 (0x8U)
+#define LPUART_MODIR_RXRTSE_SHIFT                (3U)
+/*! RXRTSE - Receiver request-to-send enable
+ *  0b0..The receiver has no effect on RTS.
+ *  0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full.
+ */
+#define LPUART_MODIR_RXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
+#define LPUART_MODIR_TXCTSC_MASK                 (0x10U)
+#define LPUART_MODIR_TXCTSC_SHIFT                (4U)
+/*! TXCTSC - Transmit CTS Configuration
+ *  0b0..CTS input is sampled at the start of each character.
+ *  0b1..CTS input is sampled when the transmitter is idle.
+ */
+#define LPUART_MODIR_TXCTSC(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
+#define LPUART_MODIR_TXCTSSRC_MASK               (0x20U)
+#define LPUART_MODIR_TXCTSSRC_SHIFT              (5U)
+/*! TXCTSSRC - Transmit CTS Source
+ *  0b0..CTS input is the CTS_B pin.
+ *  0b1..CTS input is the inverted Receiver Match result.
+ */
+#define LPUART_MODIR_TXCTSSRC(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
+#define LPUART_MODIR_RTSWATER_MASK               (0x700U)
+#define LPUART_MODIR_RTSWATER_SHIFT              (8U)
+#define LPUART_MODIR_RTSWATER(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
+#define LPUART_MODIR_TNP_MASK                    (0x30000U)
+#define LPUART_MODIR_TNP_SHIFT                   (16U)
+/*! TNP - Transmitter narrow pulse
+ *  0b00..1/OSR.
+ *  0b01..2/OSR.
+ *  0b10..3/OSR.
+ *  0b11..4/OSR.
+ */
+#define LPUART_MODIR_TNP(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
+#define LPUART_MODIR_IREN_MASK                   (0x40000U)
+#define LPUART_MODIR_IREN_SHIFT                  (18U)
+/*! IREN - Infrared enable
+ *  0b0..IR disabled.
+ *  0b1..IR enabled.
+ */
+#define LPUART_MODIR_IREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
+/*! @} */
+
+/*! @name FIFO - LPUART FIFO Register */
+/*! @{ */
+#define LPUART_FIFO_RXFIFOSIZE_MASK              (0x7U)
+#define LPUART_FIFO_RXFIFOSIZE_SHIFT             (0U)
+/*! RXFIFOSIZE - Receive FIFO. Buffer Depth
+ *  0b000..Receive FIFO/Buffer depth = 1 dataword.
+ *  0b001..Receive FIFO/Buffer depth = 4 datawords.
+ *  0b010..Receive FIFO/Buffer depth = 8 datawords.
+ *  0b011..Receive FIFO/Buffer depth = 16 datawords.
+ *  0b100..Receive FIFO/Buffer depth = 32 datawords.
+ *  0b101..Receive FIFO/Buffer depth = 64 datawords.
+ *  0b110..Receive FIFO/Buffer depth = 128 datawords.
+ *  0b111..Receive FIFO/Buffer depth = 256 datawords.
+ */
+#define LPUART_FIFO_RXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
+#define LPUART_FIFO_RXFE_MASK                    (0x8U)
+#define LPUART_FIFO_RXFE_SHIFT                   (3U)
+/*! RXFE - Receive FIFO Enable
+ *  0b0..Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
+ *  0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
+ */
+#define LPUART_FIFO_RXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
+#define LPUART_FIFO_TXFIFOSIZE_MASK              (0x70U)
+#define LPUART_FIFO_TXFIFOSIZE_SHIFT             (4U)
+/*! TXFIFOSIZE - Transmit FIFO. Buffer Depth
+ *  0b000..Transmit FIFO/Buffer depth = 1 dataword.
+ *  0b001..Transmit FIFO/Buffer depth = 4 datawords.
+ *  0b010..Transmit FIFO/Buffer depth = 8 datawords.
+ *  0b011..Transmit FIFO/Buffer depth = 16 datawords.
+ *  0b100..Transmit FIFO/Buffer depth = 32 datawords.
+ *  0b101..Transmit FIFO/Buffer depth = 64 datawords.
+ *  0b110..Transmit FIFO/Buffer depth = 128 datawords.
+ *  0b111..Transmit FIFO/Buffer depth = 256 datawords
+ */
+#define LPUART_FIFO_TXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
+#define LPUART_FIFO_TXFE_MASK                    (0x80U)
+#define LPUART_FIFO_TXFE_SHIFT                   (7U)
+/*! TXFE - Transmit FIFO Enable
+ *  0b0..Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
+ *  0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
+ */
+#define LPUART_FIFO_TXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
+#define LPUART_FIFO_RXUFE_MASK                   (0x100U)
+#define LPUART_FIFO_RXUFE_SHIFT                  (8U)
+/*! RXUFE - Receive FIFO Underflow Interrupt Enable
+ *  0b0..RXUF flag does not generate an interrupt to the host.
+ *  0b1..RXUF flag generates an interrupt to the host.
+ */
+#define LPUART_FIFO_RXUFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
+#define LPUART_FIFO_TXOFE_MASK                   (0x200U)
+#define LPUART_FIFO_TXOFE_SHIFT                  (9U)
+/*! TXOFE - Transmit FIFO Overflow Interrupt Enable
+ *  0b0..TXOF flag does not generate an interrupt to the host.
+ *  0b1..TXOF flag generates an interrupt to the host.
+ */
+#define LPUART_FIFO_TXOFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
+#define LPUART_FIFO_RXIDEN_MASK                  (0x1C00U)
+#define LPUART_FIFO_RXIDEN_SHIFT                 (10U)
+/*! RXIDEN - Receiver Idle Empty Enable
+ *  0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle.
+ *  0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character.
+ *  0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters.
+ *  0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters.
+ *  0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters.
+ *  0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters.
+ *  0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters.
+ *  0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.
+ */
+#define LPUART_FIFO_RXIDEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
+#define LPUART_FIFO_RXFLUSH_MASK                 (0x4000U)
+#define LPUART_FIFO_RXFLUSH_SHIFT                (14U)
+/*! RXFLUSH - Receive FIFO/Buffer Flush
+ *  0b0..No flush operation occurs.
+ *  0b1..All data in the receive FIFO/buffer is cleared out.
+ */
+#define LPUART_FIFO_RXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
+#define LPUART_FIFO_TXFLUSH_MASK                 (0x8000U)
+#define LPUART_FIFO_TXFLUSH_SHIFT                (15U)
+/*! TXFLUSH - Transmit FIFO/Buffer Flush
+ *  0b0..No flush operation occurs.
+ *  0b1..All data in the transmit FIFO/Buffer is cleared out.
+ */
+#define LPUART_FIFO_TXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
+#define LPUART_FIFO_RXUF_MASK                    (0x10000U)
+#define LPUART_FIFO_RXUF_SHIFT                   (16U)
+/*! RXUF - Receiver Buffer Underflow Flag
+ *  0b0..No receive buffer underflow has occurred since the last time the flag was cleared.
+ *  0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared.
+ */
+#define LPUART_FIFO_RXUF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
+#define LPUART_FIFO_TXOF_MASK                    (0x20000U)
+#define LPUART_FIFO_TXOF_SHIFT                   (17U)
+/*! TXOF - Transmitter Buffer Overflow Flag
+ *  0b0..No transmit buffer overflow has occurred since the last time the flag was cleared.
+ *  0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared.
+ */
+#define LPUART_FIFO_TXOF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
+#define LPUART_FIFO_RXEMPT_MASK                  (0x400000U)
+#define LPUART_FIFO_RXEMPT_SHIFT                 (22U)
+/*! RXEMPT - Receive Buffer/FIFO Empty
+ *  0b0..Receive buffer is not empty.
+ *  0b1..Receive buffer is empty.
+ */
+#define LPUART_FIFO_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
+#define LPUART_FIFO_TXEMPT_MASK                  (0x800000U)
+#define LPUART_FIFO_TXEMPT_SHIFT                 (23U)
+/*! TXEMPT - Transmit Buffer/FIFO Empty
+ *  0b0..Transmit buffer is not empty.
+ *  0b1..Transmit buffer is empty.
+ */
+#define LPUART_FIFO_TXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
+/*! @} */
+
+/*! @name WATER - LPUART Watermark Register */
+/*! @{ */
+#define LPUART_WATER_TXWATER_MASK                (0x7U)
+#define LPUART_WATER_TXWATER_SHIFT               (0U)
+#define LPUART_WATER_TXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
+#define LPUART_WATER_TXCOUNT_MASK                (0xF00U)
+#define LPUART_WATER_TXCOUNT_SHIFT               (8U)
+#define LPUART_WATER_TXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
+#define LPUART_WATER_RXWATER_MASK                (0x70000U)
+#define LPUART_WATER_RXWATER_SHIFT               (16U)
+#define LPUART_WATER_RXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
+#define LPUART_WATER_RXCOUNT_MASK                (0xF000000U)
+#define LPUART_WATER_RXCOUNT_SHIFT               (24U)
+#define LPUART_WATER_RXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group LPUART_Register_Masks */
+
+
+/* LPUART - Peripheral instance base addresses */
+/** Peripheral LPUART0 base address */
+#define LPUART0_BASE                             (0x40042000u)
+/** Peripheral LPUART0 base pointer */
+#define LPUART0                                  ((LPUART_Type *)LPUART0_BASE)
+/** Peripheral LPUART1 base address */
+#define LPUART1_BASE                             (0x40043000u)
+/** Peripheral LPUART1 base pointer */
+#define LPUART1                                  ((LPUART_Type *)LPUART1_BASE)
+/** Peripheral LPUART2 base address */
+#define LPUART2_BASE                             (0x40044000u)
+/** Peripheral LPUART2 base pointer */
+#define LPUART2                                  ((LPUART_Type *)LPUART2_BASE)
+/** Peripheral LPUART3 base address */
+#define LPUART3_BASE                             (0x41036000u)
+/** Peripheral LPUART3 base pointer */
+#define LPUART3                                  ((LPUART_Type *)LPUART3_BASE)
+/** Array initializer of LPUART peripheral base addresses */
+#define LPUART_BASE_ADDRS                        { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE }
+/** Array initializer of LPUART peripheral base pointers */
+#define LPUART_BASE_PTRS                         { LPUART0, LPUART1, LPUART2, LPUART3 }
+/** Interrupt vectors for the LPUART peripheral type */
+#define LPUART_RX_TX_IRQS                        { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn }
+#define LPUART_ERR_IRQS                          { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPUART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[8];
+  __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+  __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+  __IO uint32_t CPCR;                              /**< Core Platform Control Register, offset: 0xC */
+       uint8_t RESERVED_1[36];
+  __IO uint32_t CPCR2;                             /**< Core Platform Control Register 2, offset: 0x34 */
+       uint8_t RESERVED_2[8];
+  __IO uint32_t CPO;                               /**< Compute Operation Control Register, offset: 0x40 */
+} MCM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
+/*! @{ */
+#define MCM_PLASC_ASC_MASK                       (0xFFU)
+#define MCM_PLASC_ASC_SHIFT                      (0U)
+/*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.
+ *  0b00000000..A bus slave connection to AXBS input port n is absent
+ *  0b00000001..A bus slave connection to AXBS input port n is present
+ */
+#define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
+/*! @} */
+
+/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
+/*! @{ */
+#define MCM_PLAMC_AMC_MASK                       (0xFFU)
+#define MCM_PLAMC_AMC_SHIFT                      (0U)
+/*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
+ *  0b00000000..A bus master connection to AXBS input port n is absent
+ *  0b00000001..A bus master connection to AXBS input port n is present
+ */
+#define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
+/*! @} */
+
+/*! @name CPCR - Core Platform Control Register */
+/*! @{ */
+#define MCM_CPCR_ARB_MASK                        (0x200U)
+#define MCM_CPCR_ARB_SHIFT                       (9U)
+/*! ARB - Arbitration select
+ *  0b0..Fixed-priority arbitration for the crossbar masters
+ *  0b1..Round-robin arbitration for the crossbar masters
+ */
+#define MCM_CPCR_ARB(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_CPCR_ARB_SHIFT)) & MCM_CPCR_ARB_MASK)
+/*! @} */
+
+/*! @name CPCR2 - Core Platform Control Register 2 */
+/*! @{ */
+#define MCM_CPCR2_CCBC_MASK                      (0x1U)
+#define MCM_CPCR2_CCBC_SHIFT                     (0U)
+#define MCM_CPCR2_CCBC(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_CCBC_SHIFT)) & MCM_CPCR2_CCBC_MASK)
+#define MCM_CPCR2_DCC_MASK                       (0x8U)
+#define MCM_CPCR2_DCC_SHIFT                      (3U)
+#define MCM_CPCR2_DCC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_DCC_SHIFT)) & MCM_CPCR2_DCC_MASK)
+#define MCM_CPCR2_CCSIZ_MASK                     (0xF0U)
+#define MCM_CPCR2_CCSIZ_SHIFT                    (4U)
+/*! CCSIZ - Code cache size
+ *  0b0000..No cache
+ *  0b0010..2KB
+ *  0b0011..4KB
+ *  0b0100..8KB
+ */
+#define MCM_CPCR2_CCSIZ(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_CCSIZ_SHIFT)) & MCM_CPCR2_CCSIZ_MASK)
+/*! @} */
+
+/*! @name CPO - Compute Operation Control Register */
+/*! @{ */
+#define MCM_CPO_CPOREQ_MASK                      (0x1U)
+#define MCM_CPO_CPOREQ_SHIFT                     (0U)
+/*! CPOREQ - Compute Operation request
+ *  0b0..Request is cleared.
+ *  0b1..Request Compute Operation.
+ */
+#define MCM_CPO_CPOREQ(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
+#define MCM_CPO_CPOACK_MASK                      (0x2U)
+#define MCM_CPO_CPOACK_SHIFT                     (1U)
+/*! CPOACK - Compute Operation acknowledge
+ *  0b0..Compute operation entry has not completed or compute operation exit has completed.
+ *  0b1..Compute operation entry has completed or compute operation exit has not completed.
+ */
+#define MCM_CPO_CPOACK(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
+#define MCM_CPO_CPOWOI_MASK                      (0x4U)
+#define MCM_CPO_CPOWOI_SHIFT                     (2U)
+/*! CPOWOI - Compute Operation wakeup on interrupt
+ *  0b0..No effect.
+ *  0b1..When set, the CPOREQ is cleared on any interrupt or exception vector fetch.
+ */
+#define MCM_CPO_CPOWOI(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM1 base address */
+#define MCM1_BASE                                (0xF0003000u)
+/** Peripheral MCM1 base pointer */
+#define MCM1                                     ((MCM_Type *)MCM1_BASE)
+/** Array initializer of MCM peripheral base addresses */
+#define MCM_BASE_ADDRS                           { 0u, MCM1_BASE }
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASE_PTRS                            { (MCM_Type *)0u, MCM1 }
+/* MCM compatibility definitions */
+#define MCM_BASE                  MCM1_BASE
+#define MCM                       MCM1
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MMDVSQ Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MMDVSQ_Peripheral_Access_Layer MMDVSQ Peripheral Access Layer
+ * @{
+ */
+
+/** MMDVSQ - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t DEND;                              /**< Dividend Register, offset: 0x0 */
+  __IO uint32_t DSOR;                              /**< Divisor Register, offset: 0x4 */
+  __IO uint32_t CSR;                               /**< Control/Status Register, offset: 0x8 */
+  __IO uint32_t RES;                               /**< Result Register, offset: 0xC */
+  __O  uint32_t RCND;                              /**< Radicand Register, offset: 0x10 */
+} MMDVSQ_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MMDVSQ Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MMDVSQ_Register_Masks MMDVSQ Register Masks
+ * @{
+ */
+
+/*! @name DEND - Dividend Register */
+/*! @{ */
+#define MMDVSQ_DEND_DIVIDEND_MASK                (0xFFFFFFFFU)
+#define MMDVSQ_DEND_DIVIDEND_SHIFT               (0U)
+#define MMDVSQ_DEND_DIVIDEND(x)                  (((uint32_t)(((uint32_t)(x)) << MMDVSQ_DEND_DIVIDEND_SHIFT)) & MMDVSQ_DEND_DIVIDEND_MASK)
+/*! @} */
+
+/*! @name DSOR - Divisor Register */
+/*! @{ */
+#define MMDVSQ_DSOR_DIVISOR_MASK                 (0xFFFFFFFFU)
+#define MMDVSQ_DSOR_DIVISOR_SHIFT                (0U)
+#define MMDVSQ_DSOR_DIVISOR(x)                   (((uint32_t)(((uint32_t)(x)) << MMDVSQ_DSOR_DIVISOR_SHIFT)) & MMDVSQ_DSOR_DIVISOR_MASK)
+/*! @} */
+
+/*! @name CSR - Control/Status Register */
+/*! @{ */
+#define MMDVSQ_CSR_SRT_MASK                      (0x1U)
+#define MMDVSQ_CSR_SRT_SHIFT                     (0U)
+/*! SRT - Start
+ *  0b0..No operation initiated
+ *  0b1..If CSR[DFS] = 1, then initiate a divide calculation, else ignore
+ */
+#define MMDVSQ_CSR_SRT(x)                        (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_SRT_SHIFT)) & MMDVSQ_CSR_SRT_MASK)
+#define MMDVSQ_CSR_USGN_MASK                     (0x2U)
+#define MMDVSQ_CSR_USGN_SHIFT                    (1U)
+/*! USGN - Unsigned calculation
+ *  0b0..Perform a signed divide
+ *  0b1..Perform an unsigned divide
+ */
+#define MMDVSQ_CSR_USGN(x)                       (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_USGN_SHIFT)) & MMDVSQ_CSR_USGN_MASK)
+#define MMDVSQ_CSR_REM_MASK                      (0x4U)
+#define MMDVSQ_CSR_REM_SHIFT                     (2U)
+/*! REM - REMainder calculation
+ *  0b0..Return the quotient in the RES for the divide calculation
+ *  0b1..Return the remainder in the RES for the divide calculation
+ */
+#define MMDVSQ_CSR_REM(x)                        (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_REM_SHIFT)) & MMDVSQ_CSR_REM_MASK)
+#define MMDVSQ_CSR_DZE_MASK                      (0x8U)
+#define MMDVSQ_CSR_DZE_SHIFT                     (3U)
+/*! DZE - Divide-by-Zero-Enable
+ *  0b0..Reads of the RES register return the register contents
+ *  0b1..If CSR[DZ] = 1, an attempted read of RES register is error terminated to signal a divide-by-zero, else the register contents are returned
+ */
+#define MMDVSQ_CSR_DZE(x)                        (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DZE_SHIFT)) & MMDVSQ_CSR_DZE_MASK)
+#define MMDVSQ_CSR_DZ_MASK                       (0x10U)
+#define MMDVSQ_CSR_DZ_SHIFT                      (4U)
+/*! DZ - Divide-by-Zero
+ *  0b0..The last divide operation had a non-zero divisor, that is, DSOR != 0
+ *  0b1..The last divide operation had a zero divisor, that is, DSOR = 0
+ */
+#define MMDVSQ_CSR_DZ(x)                         (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DZ_SHIFT)) & MMDVSQ_CSR_DZ_MASK)
+#define MMDVSQ_CSR_DFS_MASK                      (0x20U)
+#define MMDVSQ_CSR_DFS_SHIFT                     (5U)
+/*! DFS - Disable Fast Start
+ *  0b0..A divide operation is initiated by a write to the DSOR register
+ *  0b1..A divide operation is initiated by a write to the CSR register with CSR[SRT] = 1
+ */
+#define MMDVSQ_CSR_DFS(x)                        (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DFS_SHIFT)) & MMDVSQ_CSR_DFS_MASK)
+#define MMDVSQ_CSR_SQRT_MASK                     (0x20000000U)
+#define MMDVSQ_CSR_SQRT_SHIFT                    (29U)
+/*! SQRT - SQUARE ROOT
+ *  0b0..Current or last MMDVSQ operation was not a square root
+ *  0b1..Current or last MMDVSQ operation was a square root
+ */
+#define MMDVSQ_CSR_SQRT(x)                       (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_SQRT_SHIFT)) & MMDVSQ_CSR_SQRT_MASK)
+#define MMDVSQ_CSR_DIV_MASK                      (0x40000000U)
+#define MMDVSQ_CSR_DIV_SHIFT                     (30U)
+/*! DIV - DIVIDE
+ *  0b0..Current or last MMDVSQ operation was not a divide
+ *  0b1..Current or last MMDVSQ operation was a divide
+ */
+#define MMDVSQ_CSR_DIV(x)                        (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DIV_SHIFT)) & MMDVSQ_CSR_DIV_MASK)
+#define MMDVSQ_CSR_BUSY_MASK                     (0x80000000U)
+#define MMDVSQ_CSR_BUSY_SHIFT                    (31U)
+/*! BUSY - BUSY
+ *  0b0..MMDVSQ is idle
+ *  0b1..MMDVSQ is busy performing a divide or square root calculation
+ */
+#define MMDVSQ_CSR_BUSY(x)                       (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_BUSY_SHIFT)) & MMDVSQ_CSR_BUSY_MASK)
+/*! @} */
+
+/*! @name RES - Result Register */
+/*! @{ */
+#define MMDVSQ_RES_RESULT_MASK                   (0xFFFFFFFFU)
+#define MMDVSQ_RES_RESULT_SHIFT                  (0U)
+#define MMDVSQ_RES_RESULT(x)                     (((uint32_t)(((uint32_t)(x)) << MMDVSQ_RES_RESULT_SHIFT)) & MMDVSQ_RES_RESULT_MASK)
+/*! @} */
+
+/*! @name RCND - Radicand Register */
+/*! @{ */
+#define MMDVSQ_RCND_RADICAND_MASK                (0xFFFFFFFFU)
+#define MMDVSQ_RCND_RADICAND_SHIFT               (0U)
+#define MMDVSQ_RCND_RADICAND(x)                  (((uint32_t)(((uint32_t)(x)) << MMDVSQ_RCND_RADICAND_SHIFT)) & MMDVSQ_RCND_RADICAND_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group MMDVSQ_Register_Masks */
+
+
+/* MMDVSQ - Peripheral instance base addresses */
+/** Peripheral MMDVSQ1 base address */
+#define MMDVSQ1_BASE                             (0xF0004000u)
+/** Peripheral MMDVSQ1 base pointer */
+#define MMDVSQ1                                  ((MMDVSQ_Type *)MMDVSQ1_BASE)
+/** Array initializer of MMDVSQ peripheral base addresses */
+#define MMDVSQ_BASE_ADDRS                        { 0u, MMDVSQ1_BASE }
+/** Array initializer of MMDVSQ peripheral base pointers */
+#define MMDVSQ_BASE_PTRS                         { (MMDVSQ_Type *)0u, MMDVSQ1 }
+
+/*!
+ * @}
+ */ /* end of group MMDVSQ_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MSCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MSCM_Peripheral_Access_Layer MSCM Peripheral Access Layer
+ * @{
+ */
+
+/** MSCM - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t CPXTYPE;                           /**< Processor X Type Register, offset: 0x0 */
+  __I  uint32_t CPXNUM;                            /**< Processor X Number Register, offset: 0x4 */
+  __I  uint32_t CPXMASTER;                         /**< Processor X Master Register, offset: 0x8 */
+  __I  uint32_t CPXCOUNT;                          /**< Processor X Count Register, offset: 0xC */
+  __I  uint32_t CPXCFG0;                           /**< Processor X Configuration Register 0, offset: 0x10 */
+  __I  uint32_t CPXCFG1;                           /**< Processor X Configuration Register 1, offset: 0x14 */
+  __I  uint32_t CPXCFG2;                           /**< Processor X Configuration Register 2, offset: 0x18 */
+  __I  uint32_t CPXCFG3;                           /**< Processor X Configuration Register 3, offset: 0x1C */
+  struct {                                         /* offset: 0x20, array step: 0x20 */
+    __I  uint32_t TYPE;                              /**< Processor 0 Type Register..Processor 1 Type Register, array offset: 0x20, array step: 0x20 */
+    __I  uint32_t NUM;                               /**< Processor 0 Number Register..Processor 1 Number Register, array offset: 0x24, array step: 0x20 */
+    __I  uint32_t MASTER;                            /**< Processor 0 Master Register..Processor 1 Master Register, array offset: 0x28, array step: 0x20 */
+    __I  uint32_t COUNT;                             /**< Processor 0 Count Register..Processor 1 Count Register, array offset: 0x2C, array step: 0x20 */
+    __I  uint32_t CFG0;                              /**< Processor 0 Configuration Register 0..Processor 1 Configuration Register 0, array offset: 0x30, array step: 0x20 */
+    __I  uint32_t CFG1;                              /**< Processor 0 Configuration Register 1..Processor 1 Configuration Register 1, array offset: 0x34, array step: 0x20 */
+    __I  uint32_t CFG2;                              /**< Processor 0 Configuration Register 2..Processor 1 Configuration Register 2, array offset: 0x38, array step: 0x20 */
+    __I  uint32_t CFG3;                              /**< Processor 0 Configuration Register 3..Processor 1 Configuration Register 3, array offset: 0x3C, array step: 0x20 */
+  } CP[2];
+       uint8_t RESERVED_0[928];
+  __IO uint32_t OCMDR0;                            /**< On-Chip Memory Descriptor Register, offset: 0x400 */
+  __IO uint32_t OCMDR1;                            /**< On-Chip Memory Descriptor Register, offset: 0x404 */
+  __IO uint32_t OCMDR2;                            /**< On-Chip Memory Descriptor Register, offset: 0x408 */
+  __IO uint32_t OCMDR3;                            /**< On-Chip Memory Descriptor Register, offset: 0x40C */
+} MSCM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MSCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MSCM_Register_Masks MSCM Register Masks
+ * @{
+ */
+
+/*! @name CPXTYPE - Processor X Type Register */
+/*! @{ */
+#define MSCM_CPXTYPE_RYPZ_MASK                   (0xFFU)
+#define MSCM_CPXTYPE_RYPZ_SHIFT                  (0U)
+#define MSCM_CPXTYPE_RYPZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXTYPE_RYPZ_SHIFT)) & MSCM_CPXTYPE_RYPZ_MASK)
+#define MSCM_CPXTYPE_PERSONALITY_MASK            (0xFFFFFF00U)
+#define MSCM_CPXTYPE_PERSONALITY_SHIFT           (8U)
+#define MSCM_CPXTYPE_PERSONALITY(x)              (((uint32_t)(((uint32_t)(x)) << MSCM_CPXTYPE_PERSONALITY_SHIFT)) & MSCM_CPXTYPE_PERSONALITY_MASK)
+/*! @} */
+
+/*! @name CPXNUM - Processor X Number Register */
+/*! @{ */
+#define MSCM_CPXNUM_CPN_MASK                     (0x1U)
+#define MSCM_CPXNUM_CPN_SHIFT                    (0U)
+#define MSCM_CPXNUM_CPN(x)                       (((uint32_t)(((uint32_t)(x)) << MSCM_CPXNUM_CPN_SHIFT)) & MSCM_CPXNUM_CPN_MASK)
+/*! @} */
+
+/*! @name CPXMASTER - Processor X Master Register */
+/*! @{ */
+#define MSCM_CPXMASTER_PPMN_MASK                 (0x3FU)
+#define MSCM_CPXMASTER_PPMN_SHIFT                (0U)
+#define MSCM_CPXMASTER_PPMN(x)                   (((uint32_t)(((uint32_t)(x)) << MSCM_CPXMASTER_PPMN_SHIFT)) & MSCM_CPXMASTER_PPMN_MASK)
+/*! @} */
+
+/*! @name CPXCOUNT - Processor X Count Register */
+/*! @{ */
+#define MSCM_CPXCOUNT_PCNT_MASK                  (0x3U)
+#define MSCM_CPXCOUNT_PCNT_SHIFT                 (0U)
+#define MSCM_CPXCOUNT_PCNT(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCOUNT_PCNT_SHIFT)) & MSCM_CPXCOUNT_PCNT_MASK)
+/*! @} */
+
+/*! @name CPXCFG0 - Processor X Configuration Register 0 */
+/*! @{ */
+#define MSCM_CPXCFG0_DCWY_MASK                   (0xFFU)
+#define MSCM_CPXCFG0_DCWY_SHIFT                  (0U)
+#define MSCM_CPXCFG0_DCWY(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_DCWY_SHIFT)) & MSCM_CPXCFG0_DCWY_MASK)
+#define MSCM_CPXCFG0_DCSZ_MASK                   (0xFF00U)
+#define MSCM_CPXCFG0_DCSZ_SHIFT                  (8U)
+#define MSCM_CPXCFG0_DCSZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_DCSZ_SHIFT)) & MSCM_CPXCFG0_DCSZ_MASK)
+#define MSCM_CPXCFG0_ICWY_MASK                   (0xFF0000U)
+#define MSCM_CPXCFG0_ICWY_SHIFT                  (16U)
+#define MSCM_CPXCFG0_ICWY(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_ICWY_SHIFT)) & MSCM_CPXCFG0_ICWY_MASK)
+#define MSCM_CPXCFG0_ICSZ_MASK                   (0xFF000000U)
+#define MSCM_CPXCFG0_ICSZ_SHIFT                  (24U)
+#define MSCM_CPXCFG0_ICSZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_ICSZ_SHIFT)) & MSCM_CPXCFG0_ICSZ_MASK)
+/*! @} */
+
+/*! @name CPXCFG1 - Processor X Configuration Register 1 */
+/*! @{ */
+#define MSCM_CPXCFG1_L2WY_MASK                   (0xFF0000U)
+#define MSCM_CPXCFG1_L2WY_SHIFT                  (16U)
+#define MSCM_CPXCFG1_L2WY(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG1_L2WY_SHIFT)) & MSCM_CPXCFG1_L2WY_MASK)
+#define MSCM_CPXCFG1_L2SZ_MASK                   (0xFF000000U)
+#define MSCM_CPXCFG1_L2SZ_SHIFT                  (24U)
+#define MSCM_CPXCFG1_L2SZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG1_L2SZ_SHIFT)) & MSCM_CPXCFG1_L2SZ_MASK)
+/*! @} */
+
+/*! @name CPXCFG2 - Processor X Configuration Register 2 */
+/*! @{ */
+#define MSCM_CPXCFG2_TMUSZ_MASK                  (0xFF00U)
+#define MSCM_CPXCFG2_TMUSZ_SHIFT                 (8U)
+#define MSCM_CPXCFG2_TMUSZ(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG2_TMUSZ_SHIFT)) & MSCM_CPXCFG2_TMUSZ_MASK)
+#define MSCM_CPXCFG2_TMLSZ_MASK                  (0xFF000000U)
+#define MSCM_CPXCFG2_TMLSZ_SHIFT                 (24U)
+#define MSCM_CPXCFG2_TMLSZ(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG2_TMLSZ_SHIFT)) & MSCM_CPXCFG2_TMLSZ_MASK)
+/*! @} */
+
+/*! @name CPXCFG3 - Processor X Configuration Register 3 */
+/*! @{ */
+#define MSCM_CPXCFG3_FPU_MASK                    (0x1U)
+#define MSCM_CPXCFG3_FPU_SHIFT                   (0U)
+/*! FPU - Floating Point Unit
+ *  0b0..FPU support is not included.
+ *  0b1..FPU support is included.
+ */
+#define MSCM_CPXCFG3_FPU(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_FPU_SHIFT)) & MSCM_CPXCFG3_FPU_MASK)
+#define MSCM_CPXCFG3_SIMD_MASK                   (0x2U)
+#define MSCM_CPXCFG3_SIMD_SHIFT                  (1U)
+/*! SIMD - SIMD/NEON instruction support
+ *  0b0..SIMD/NEON support is not included.
+ *  0b1..SIMD/NEON support is included.
+ */
+#define MSCM_CPXCFG3_SIMD(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_SIMD_SHIFT)) & MSCM_CPXCFG3_SIMD_MASK)
+#define MSCM_CPXCFG3_JAZ_MASK                    (0x4U)
+#define MSCM_CPXCFG3_JAZ_SHIFT                   (2U)
+/*! JAZ - Jazelle support
+ *  0b0..Jazelle support is not included.
+ *  0b1..Jazelle support is included.
+ */
+#define MSCM_CPXCFG3_JAZ(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_JAZ_SHIFT)) & MSCM_CPXCFG3_JAZ_MASK)
+#define MSCM_CPXCFG3_MMU_MASK                    (0x8U)
+#define MSCM_CPXCFG3_MMU_SHIFT                   (3U)
+/*! MMU - Memory Management Unit
+ *  0b0..MMU support is not included.
+ *  0b1..MMU support is included.
+ */
+#define MSCM_CPXCFG3_MMU(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_MMU_SHIFT)) & MSCM_CPXCFG3_MMU_MASK)
+#define MSCM_CPXCFG3_TZ_MASK                     (0x10U)
+#define MSCM_CPXCFG3_TZ_SHIFT                    (4U)
+/*! TZ - Trust Zone
+ *  0b0..Trust Zone support is not included.
+ *  0b1..Trust Zone support is included.
+ */
+#define MSCM_CPXCFG3_TZ(x)                       (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_TZ_SHIFT)) & MSCM_CPXCFG3_TZ_MASK)
+#define MSCM_CPXCFG3_CMP_MASK                    (0x20U)
+#define MSCM_CPXCFG3_CMP_SHIFT                   (5U)
+/*! CMP - Core Memory Protection unit
+ *  0b0..Core Memory Protection is not included.
+ *  0b1..Core Memory Protection is included.
+ */
+#define MSCM_CPXCFG3_CMP(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_CMP_SHIFT)) & MSCM_CPXCFG3_CMP_MASK)
+#define MSCM_CPXCFG3_BB_MASK                     (0x40U)
+#define MSCM_CPXCFG3_BB_SHIFT                    (6U)
+/*! BB - Bit Banding
+ *  0b0..Bit Banding is not supported.
+ *  0b1..Bit Banding is supported.
+ */
+#define MSCM_CPXCFG3_BB(x)                       (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_BB_SHIFT)) & MSCM_CPXCFG3_BB_MASK)
+#define MSCM_CPXCFG3_SBP_MASK                    (0x300U)
+#define MSCM_CPXCFG3_SBP_SHIFT                   (8U)
+#define MSCM_CPXCFG3_SBP(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_SBP_SHIFT)) & MSCM_CPXCFG3_SBP_MASK)
+/*! @} */
+
+/*! @name TYPE - Processor 0 Type Register..Processor 1 Type Register */
+/*! @{ */
+#define MSCM_TYPE_RYPZ_MASK                      (0xFFU)
+#define MSCM_TYPE_RYPZ_SHIFT                     (0U)
+#define MSCM_TYPE_RYPZ(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_TYPE_RYPZ_SHIFT)) & MSCM_TYPE_RYPZ_MASK)
+#define MSCM_TYPE_PERSONALITY_MASK               (0xFFFFFF00U)
+#define MSCM_TYPE_PERSONALITY_SHIFT              (8U)
+#define MSCM_TYPE_PERSONALITY(x)                 (((uint32_t)(((uint32_t)(x)) << MSCM_TYPE_PERSONALITY_SHIFT)) & MSCM_TYPE_PERSONALITY_MASK)
+/*! @} */
+
+/* The count of MSCM_TYPE */
+#define MSCM_TYPE_COUNT                          (2U)
+
+/*! @name NUM - Processor 0 Number Register..Processor 1 Number Register */
+/*! @{ */
+#define MSCM_NUM_CPN_MASK                        (0x1U)
+#define MSCM_NUM_CPN_SHIFT                       (0U)
+#define MSCM_NUM_CPN(x)                          (((uint32_t)(((uint32_t)(x)) << MSCM_NUM_CPN_SHIFT)) & MSCM_NUM_CPN_MASK)
+/*! @} */
+
+/* The count of MSCM_NUM */
+#define MSCM_NUM_COUNT                           (2U)
+
+/*! @name MASTER - Processor 0 Master Register..Processor 1 Master Register */
+/*! @{ */
+#define MSCM_MASTER_PPMN_MASK                    (0x3FU)
+#define MSCM_MASTER_PPMN_SHIFT                   (0U)
+#define MSCM_MASTER_PPMN(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_MASTER_PPMN_SHIFT)) & MSCM_MASTER_PPMN_MASK)
+/*! @} */
+
+/* The count of MSCM_MASTER */
+#define MSCM_MASTER_COUNT                        (2U)
+
+/*! @name COUNT - Processor 0 Count Register..Processor 1 Count Register */
+/*! @{ */
+#define MSCM_COUNT_PCNT_MASK                     (0x3U)
+#define MSCM_COUNT_PCNT_SHIFT                    (0U)
+#define MSCM_COUNT_PCNT(x)                       (((uint32_t)(((uint32_t)(x)) << MSCM_COUNT_PCNT_SHIFT)) & MSCM_COUNT_PCNT_MASK)
+/*! @} */
+
+/* The count of MSCM_COUNT */
+#define MSCM_COUNT_COUNT                         (2U)
+
+/*! @name CFG0 - Processor 0 Configuration Register 0..Processor 1 Configuration Register 0 */
+/*! @{ */
+#define MSCM_CFG0_DCWY_MASK                      (0xFFU)
+#define MSCM_CFG0_DCWY_SHIFT                     (0U)
+#define MSCM_CFG0_DCWY(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_CFG0_DCWY_SHIFT)) & MSCM_CFG0_DCWY_MASK)
+#define MSCM_CFG0_DCSZ_MASK                      (0xFF00U)
+#define MSCM_CFG0_DCSZ_SHIFT                     (8U)
+#define MSCM_CFG0_DCSZ(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_CFG0_DCSZ_SHIFT)) & MSCM_CFG0_DCSZ_MASK)
+#define MSCM_CFG0_ICWY_MASK                      (0xFF0000U)
+#define MSCM_CFG0_ICWY_SHIFT                     (16U)
+#define MSCM_CFG0_ICWY(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_CFG0_ICWY_SHIFT)) & MSCM_CFG0_ICWY_MASK)
+#define MSCM_CFG0_ICSZ_MASK                      (0xFF000000U)
+#define MSCM_CFG0_ICSZ_SHIFT                     (24U)
+#define MSCM_CFG0_ICSZ(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_CFG0_ICSZ_SHIFT)) & MSCM_CFG0_ICSZ_MASK)
+/*! @} */
+
+/* The count of MSCM_CFG0 */
+#define MSCM_CFG0_COUNT                          (2U)
+
+/*! @name CFG1 - Processor 0 Configuration Register 1..Processor 1 Configuration Register 1 */
+/*! @{ */
+#define MSCM_CFG1_L2WY_MASK                      (0xFF0000U)
+#define MSCM_CFG1_L2WY_SHIFT                     (16U)
+#define MSCM_CFG1_L2WY(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_CFG1_L2WY_SHIFT)) & MSCM_CFG1_L2WY_MASK)
+#define MSCM_CFG1_L2SZ_MASK                      (0xFF000000U)
+#define MSCM_CFG1_L2SZ_SHIFT                     (24U)
+#define MSCM_CFG1_L2SZ(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_CFG1_L2SZ_SHIFT)) & MSCM_CFG1_L2SZ_MASK)
+/*! @} */
+
+/* The count of MSCM_CFG1 */
+#define MSCM_CFG1_COUNT                          (2U)
+
+/*! @name CFG2 - Processor 0 Configuration Register 2..Processor 1 Configuration Register 2 */
+/*! @{ */
+#define MSCM_CFG2_TMUSZ_MASK                     (0xFF00U)
+#define MSCM_CFG2_TMUSZ_SHIFT                    (8U)
+#define MSCM_CFG2_TMUSZ(x)                       (((uint32_t)(((uint32_t)(x)) << MSCM_CFG2_TMUSZ_SHIFT)) & MSCM_CFG2_TMUSZ_MASK)
+#define MSCM_CFG2_TMLSZ_MASK                     (0xFF000000U)
+#define MSCM_CFG2_TMLSZ_SHIFT                    (24U)
+#define MSCM_CFG2_TMLSZ(x)                       (((uint32_t)(((uint32_t)(x)) << MSCM_CFG2_TMLSZ_SHIFT)) & MSCM_CFG2_TMLSZ_MASK)
+/*! @} */
+
+/* The count of MSCM_CFG2 */
+#define MSCM_CFG2_COUNT                          (2U)
+
+/*! @name CFG3 - Processor 0 Configuration Register 3..Processor 1 Configuration Register 3 */
+/*! @{ */
+#define MSCM_CFG3_FPU_MASK                       (0x1U)
+#define MSCM_CFG3_FPU_SHIFT                      (0U)
+/*! FPU - Floating Point Unit
+ *  0b0..FPU support is not included.
+ *  0b1..FPU support is included.
+ */
+#define MSCM_CFG3_FPU(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_FPU_SHIFT)) & MSCM_CFG3_FPU_MASK)
+#define MSCM_CFG3_SIMD_MASK                      (0x2U)
+#define MSCM_CFG3_SIMD_SHIFT                     (1U)
+/*! SIMD - SIMD/NEON instruction support
+ *  0b0..SIMD/NEON support is not included.
+ *  0b1..SIMD/NEON support is included.
+ */
+#define MSCM_CFG3_SIMD(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_SIMD_SHIFT)) & MSCM_CFG3_SIMD_MASK)
+#define MSCM_CFG3_JAZ_MASK                       (0x4U)
+#define MSCM_CFG3_JAZ_SHIFT                      (2U)
+/*! JAZ - Jazelle support
+ *  0b0..Jazelle support is not included.
+ *  0b1..Jazelle support is included.
+ */
+#define MSCM_CFG3_JAZ(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_JAZ_SHIFT)) & MSCM_CFG3_JAZ_MASK)
+#define MSCM_CFG3_MMU_MASK                       (0x8U)
+#define MSCM_CFG3_MMU_SHIFT                      (3U)
+/*! MMU - Memory Management Unit
+ *  0b0..MMU support is not included.
+ *  0b1..MMU support is included.
+ */
+#define MSCM_CFG3_MMU(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_MMU_SHIFT)) & MSCM_CFG3_MMU_MASK)
+#define MSCM_CFG3_TZ_MASK                        (0x10U)
+#define MSCM_CFG3_TZ_SHIFT                       (4U)
+/*! TZ - Trust Zone
+ *  0b0..Trust Zone support is not included.
+ *  0b1..Trust Zone support is included.
+ */
+#define MSCM_CFG3_TZ(x)                          (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_TZ_SHIFT)) & MSCM_CFG3_TZ_MASK)
+#define MSCM_CFG3_CMP_MASK                       (0x20U)
+#define MSCM_CFG3_CMP_SHIFT                      (5U)
+/*! CMP - Core Memory Protection unit
+ *  0b0..Core Memory Protection is not included.
+ *  0b1..Core Memory Protection is included.
+ */
+#define MSCM_CFG3_CMP(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_CMP_SHIFT)) & MSCM_CFG3_CMP_MASK)
+#define MSCM_CFG3_BB_MASK                        (0x40U)
+#define MSCM_CFG3_BB_SHIFT                       (6U)
+/*! BB - Bit Banding
+ *  0b0..Bit Banding is not supported.
+ *  0b1..Bit Banding is supported.
+ */
+#define MSCM_CFG3_BB(x)                          (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_BB_SHIFT)) & MSCM_CFG3_BB_MASK)
+#define MSCM_CFG3_SBP_MASK                       (0x300U)
+#define MSCM_CFG3_SBP_SHIFT                      (8U)
+#define MSCM_CFG3_SBP(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_SBP_SHIFT)) & MSCM_CFG3_SBP_MASK)
+/*! @} */
+
+/* The count of MSCM_CFG3 */
+#define MSCM_CFG3_COUNT                          (2U)
+
+/*! @name OCMDR0 - On-Chip Memory Descriptor Register */
+/*! @{ */
+#define MSCM_OCMDR0_OCM1_MASK                    (0x30U)
+#define MSCM_OCMDR0_OCM1_SHIFT                   (4U)
+#define MSCM_OCMDR0_OCM1(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCM1_SHIFT)) & MSCM_OCMDR0_OCM1_MASK)
+#define MSCM_OCMDR0_OCMPU_MASK                   (0x1000U)
+#define MSCM_OCMDR0_OCMPU_SHIFT                  (12U)
+#define MSCM_OCMDR0_OCMPU(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMPU_SHIFT)) & MSCM_OCMDR0_OCMPU_MASK)
+#define MSCM_OCMDR0_OCMT_MASK                    (0xE000U)
+#define MSCM_OCMDR0_OCMT_SHIFT                   (13U)
+/*! OCMT - OCMT
+ *  0b000..Reserved
+ *  0b001..Reserved
+ *  0b010..Reserved
+ *  0b011..OCMEMn is a ROM.
+ *  0b100..OCMEMn is a Program Flash.
+ *  0b101..Reserved
+ *  0b110..OCMEMn is an EEE.
+ *  0b111..Reserved
+ */
+#define MSCM_OCMDR0_OCMT(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMT_SHIFT)) & MSCM_OCMDR0_OCMT_MASK)
+#define MSCM_OCMDR0_RO_MASK                      (0x10000U)
+#define MSCM_OCMDR0_RO_SHIFT                     (16U)
+/*! RO - RO
+ *  0b0..Writes to the OCMDRn[11:0] are allowed
+ *  0b1..Writes to the OCMDRn[11:0] are ignored
+ */
+#define MSCM_OCMDR0_RO(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_RO_SHIFT)) & MSCM_OCMDR0_RO_MASK)
+#define MSCM_OCMDR0_OCMW_MASK                    (0xE0000U)
+#define MSCM_OCMDR0_OCMW_SHIFT                   (17U)
+/*! OCMW - OCMW
+ *  0b000-0b001..Reserved
+ *  0b010..OCMEMn 32-bits wide
+ *  0b011..OCMEMn 64-bits wide
+ *  0b100..OCMEMn 128-bits wide
+ *  0b101..OCMEMn 256-bits wide
+ *  0b110-0b111..Reserved
+ */
+#define MSCM_OCMDR0_OCMW(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMW_SHIFT)) & MSCM_OCMDR0_OCMW_MASK)
+#define MSCM_OCMDR0_OCMSZ_MASK                   (0xF000000U)
+#define MSCM_OCMDR0_OCMSZ_SHIFT                  (24U)
+/*! OCMSZ - OCMSZ
+ *  0b0000..no OCMEMn
+ *  0b0001..1KB OCMEMn
+ *  0b0010..2KB OCMEMn
+ *  0b0011..4KB OCMEMn
+ *  0b0100..8KB OCMEMn
+ *  0b0101..16KB OCMEMn
+ *  0b0110..32KB OCMEMn
+ *  0b0111..64KB OCMEMn
+ *  0b1000..128KB OCMEMn
+ *  0b1001..256KB OCMEMn
+ *  0b1010..512KB OCMEMn
+ *  0b1011..1MB OCMEMn
+ *  0b1100..2MB OCMEMn
+ *  0b1101..4MB OCMEMn
+ *  0b1110..8MB OCMEMn
+ *  0b1111..16MB OCMEMn
+ */
+#define MSCM_OCMDR0_OCMSZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMSZ_SHIFT)) & MSCM_OCMDR0_OCMSZ_MASK)
+#define MSCM_OCMDR0_OCMSZH_MASK                  (0x10000000U)
+#define MSCM_OCMDR0_OCMSZH_SHIFT                 (28U)
+/*! OCMSZH - OCMSZH
+ *  0b0..OCMEMn is a power-of-2 capacity.
+ *  0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
+ */
+#define MSCM_OCMDR0_OCMSZH(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMSZH_SHIFT)) & MSCM_OCMDR0_OCMSZH_MASK)
+#define MSCM_OCMDR0_V_MASK                       (0x80000000U)
+#define MSCM_OCMDR0_V_SHIFT                      (31U)
+/*! V - V
+ *  0b0..OCMEMn is not present.
+ *  0b1..OCMEMn is present.
+ */
+#define MSCM_OCMDR0_V(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_V_SHIFT)) & MSCM_OCMDR0_V_MASK)
+/*! @} */
+
+/*! @name OCMDR1 - On-Chip Memory Descriptor Register */
+/*! @{ */
+#define MSCM_OCMDR1_OCM1_MASK                    (0x30U)
+#define MSCM_OCMDR1_OCM1_SHIFT                   (4U)
+#define MSCM_OCMDR1_OCM1(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCM1_SHIFT)) & MSCM_OCMDR1_OCM1_MASK)
+#define MSCM_OCMDR1_OCMPU_MASK                   (0x1000U)
+#define MSCM_OCMDR1_OCMPU_SHIFT                  (12U)
+#define MSCM_OCMDR1_OCMPU(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMPU_SHIFT)) & MSCM_OCMDR1_OCMPU_MASK)
+#define MSCM_OCMDR1_OCMT_MASK                    (0xE000U)
+#define MSCM_OCMDR1_OCMT_SHIFT                   (13U)
+/*! OCMT - OCMT
+ *  0b000..Reserved
+ *  0b001..Reserved
+ *  0b010..Reserved
+ *  0b011..OCMEMn is a ROM.
+ *  0b100..OCMEMn is a Program Flash.
+ *  0b101..Reserved
+ *  0b110..OCMEMn is an EEE.
+ *  0b111..Reserved
+ */
+#define MSCM_OCMDR1_OCMT(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMT_SHIFT)) & MSCM_OCMDR1_OCMT_MASK)
+#define MSCM_OCMDR1_RO_MASK                      (0x10000U)
+#define MSCM_OCMDR1_RO_SHIFT                     (16U)
+/*! RO - RO
+ *  0b0..Writes to the OCMDRn[11:0] are allowed
+ *  0b1..Writes to the OCMDRn[11:0] are ignored
+ */
+#define MSCM_OCMDR1_RO(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_RO_SHIFT)) & MSCM_OCMDR1_RO_MASK)
+#define MSCM_OCMDR1_OCMW_MASK                    (0xE0000U)
+#define MSCM_OCMDR1_OCMW_SHIFT                   (17U)
+/*! OCMW - OCMW
+ *  0b000-0b001..Reserved
+ *  0b010..OCMEMn 32-bits wide
+ *  0b011..OCMEMn 64-bits wide
+ *  0b100..OCMEMn 128-bits wide
+ *  0b101..OCMEMn 256-bits wide
+ *  0b110-0b111..Reserved
+ */
+#define MSCM_OCMDR1_OCMW(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMW_SHIFT)) & MSCM_OCMDR1_OCMW_MASK)
+#define MSCM_OCMDR1_OCMSZ_MASK                   (0xF000000U)
+#define MSCM_OCMDR1_OCMSZ_SHIFT                  (24U)
+/*! OCMSZ - OCMSZ
+ *  0b0000..no OCMEMn
+ *  0b0001..1KB OCMEMn
+ *  0b0010..2KB OCMEMn
+ *  0b0011..4KB OCMEMn
+ *  0b0100..8KB OCMEMn
+ *  0b0101..16KB OCMEMn
+ *  0b0110..32KB OCMEMn
+ *  0b0111..64KB OCMEMn
+ *  0b1000..128KB OCMEMn
+ *  0b1001..256KB OCMEMn
+ *  0b1010..512KB OCMEMn
+ *  0b1011..1MB OCMEMn
+ *  0b1100..2MB OCMEMn
+ *  0b1101..4MB OCMEMn
+ *  0b1110..8MB OCMEMn
+ *  0b1111..16MB OCMEMn
+ */
+#define MSCM_OCMDR1_OCMSZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMSZ_SHIFT)) & MSCM_OCMDR1_OCMSZ_MASK)
+#define MSCM_OCMDR1_OCMSZH_MASK                  (0x10000000U)
+#define MSCM_OCMDR1_OCMSZH_SHIFT                 (28U)
+/*! OCMSZH - OCMSZH
+ *  0b0..OCMEMn is a power-of-2 capacity.
+ *  0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
+ */
+#define MSCM_OCMDR1_OCMSZH(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMSZH_SHIFT)) & MSCM_OCMDR1_OCMSZH_MASK)
+#define MSCM_OCMDR1_V_MASK                       (0x80000000U)
+#define MSCM_OCMDR1_V_SHIFT                      (31U)
+/*! V - V
+ *  0b0..OCMEMn is not present.
+ *  0b1..OCMEMn is present.
+ */
+#define MSCM_OCMDR1_V(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_V_SHIFT)) & MSCM_OCMDR1_V_MASK)
+/*! @} */
+
+/*! @name OCMDR2 - On-Chip Memory Descriptor Register */
+/*! @{ */
+#define MSCM_OCMDR2_OCMPU_MASK                   (0x1000U)
+#define MSCM_OCMDR2_OCMPU_SHIFT                  (12U)
+#define MSCM_OCMDR2_OCMPU(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMPU_SHIFT)) & MSCM_OCMDR2_OCMPU_MASK)
+#define MSCM_OCMDR2_OCMT_MASK                    (0xE000U)
+#define MSCM_OCMDR2_OCMT_SHIFT                   (13U)
+/*! OCMT - OCMT
+ *  0b000..Reserved
+ *  0b001..Reserved
+ *  0b010..Reserved
+ *  0b011..OCMEMn is a ROM.
+ *  0b100..OCMEMn is a Program Flash.
+ *  0b101..Reserved
+ *  0b110..OCMEMn is an EEE.
+ *  0b111..Reserved
+ */
+#define MSCM_OCMDR2_OCMT(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMT_SHIFT)) & MSCM_OCMDR2_OCMT_MASK)
+#define MSCM_OCMDR2_RO_MASK                      (0x10000U)
+#define MSCM_OCMDR2_RO_SHIFT                     (16U)
+/*! RO - RO
+ *  0b0..Writes to the OCMDRn[11:0] are allowed
+ *  0b1..Writes to the OCMDRn[11:0] are ignored
+ */
+#define MSCM_OCMDR2_RO(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_RO_SHIFT)) & MSCM_OCMDR2_RO_MASK)
+#define MSCM_OCMDR2_OCMW_MASK                    (0xE0000U)
+#define MSCM_OCMDR2_OCMW_SHIFT                   (17U)
+/*! OCMW - OCMW
+ *  0b000-0b001..Reserved
+ *  0b010..OCMEMn 32-bits wide
+ *  0b011..OCMEMn 64-bits wide
+ *  0b100..OCMEMn 128-bits wide
+ *  0b101..OCMEMn 256-bits wide
+ *  0b110-0b111..Reserved
+ */
+#define MSCM_OCMDR2_OCMW(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMW_SHIFT)) & MSCM_OCMDR2_OCMW_MASK)
+#define MSCM_OCMDR2_OCMSZ_MASK                   (0xF000000U)
+#define MSCM_OCMDR2_OCMSZ_SHIFT                  (24U)
+/*! OCMSZ - OCMSZ
+ *  0b0000..no OCMEMn
+ *  0b0001..1KB OCMEMn
+ *  0b0010..2KB OCMEMn
+ *  0b0011..4KB OCMEMn
+ *  0b0100..8KB OCMEMn
+ *  0b0101..16KB OCMEMn
+ *  0b0110..32KB OCMEMn
+ *  0b0111..64KB OCMEMn
+ *  0b1000..128KB OCMEMn
+ *  0b1001..256KB OCMEMn
+ *  0b1010..512KB OCMEMn
+ *  0b1011..1MB OCMEMn
+ *  0b1100..2MB OCMEMn
+ *  0b1101..4MB OCMEMn
+ *  0b1110..8MB OCMEMn
+ *  0b1111..16MB OCMEMn
+ */
+#define MSCM_OCMDR2_OCMSZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMSZ_SHIFT)) & MSCM_OCMDR2_OCMSZ_MASK)
+#define MSCM_OCMDR2_OCMSZH_MASK                  (0x10000000U)
+#define MSCM_OCMDR2_OCMSZH_SHIFT                 (28U)
+/*! OCMSZH - OCMSZH
+ *  0b0..OCMEMn is a power-of-2 capacity.
+ *  0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
+ */
+#define MSCM_OCMDR2_OCMSZH(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMSZH_SHIFT)) & MSCM_OCMDR2_OCMSZH_MASK)
+#define MSCM_OCMDR2_V_MASK                       (0x80000000U)
+#define MSCM_OCMDR2_V_SHIFT                      (31U)
+/*! V - V
+ *  0b0..OCMEMn is not present.
+ *  0b1..OCMEMn is present.
+ */
+#define MSCM_OCMDR2_V(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_V_SHIFT)) & MSCM_OCMDR2_V_MASK)
+/*! @} */
+
+/*! @name OCMDR3 - On-Chip Memory Descriptor Register */
+/*! @{ */
+#define MSCM_OCMDR3_OCMPU_MASK                   (0x1000U)
+#define MSCM_OCMDR3_OCMPU_SHIFT                  (12U)
+#define MSCM_OCMDR3_OCMPU(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMPU_SHIFT)) & MSCM_OCMDR3_OCMPU_MASK)
+#define MSCM_OCMDR3_OCMT_MASK                    (0xE000U)
+#define MSCM_OCMDR3_OCMT_SHIFT                   (13U)
+/*! OCMT - OCMT
+ *  0b000..Reserved
+ *  0b001..Reserved
+ *  0b010..Reserved
+ *  0b011..OCMEMn is a ROM.
+ *  0b100..OCMEMn is a Program Flash.
+ *  0b101..Reserved
+ *  0b110..OCMEMn is an EEE.
+ *  0b111..Reserved
+ */
+#define MSCM_OCMDR3_OCMT(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMT_SHIFT)) & MSCM_OCMDR3_OCMT_MASK)
+#define MSCM_OCMDR3_RO_MASK                      (0x10000U)
+#define MSCM_OCMDR3_RO_SHIFT                     (16U)
+/*! RO - RO
+ *  0b0..Writes to the OCMDRn[11:0] are allowed
+ *  0b1..Writes to the OCMDRn[11:0] are ignored
+ */
+#define MSCM_OCMDR3_RO(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_RO_SHIFT)) & MSCM_OCMDR3_RO_MASK)
+#define MSCM_OCMDR3_OCMW_MASK                    (0xE0000U)
+#define MSCM_OCMDR3_OCMW_SHIFT                   (17U)
+/*! OCMW - OCMW
+ *  0b000-0b001..Reserved
+ *  0b010..OCMEMn 32-bits wide
+ *  0b011..OCMEMn 64-bits wide
+ *  0b100..OCMEMn 128-bits wide
+ *  0b101..OCMEMn 256-bits wide
+ *  0b110-0b111..Reserved
+ */
+#define MSCM_OCMDR3_OCMW(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMW_SHIFT)) & MSCM_OCMDR3_OCMW_MASK)
+#define MSCM_OCMDR3_OCMSZ_MASK                   (0xF000000U)
+#define MSCM_OCMDR3_OCMSZ_SHIFT                  (24U)
+/*! OCMSZ - OCMSZ
+ *  0b0000..no OCMEMn
+ *  0b0001..1KB OCMEMn
+ *  0b0010..2KB OCMEMn
+ *  0b0011..4KB OCMEMn
+ *  0b0100..8KB OCMEMn
+ *  0b0101..16KB OCMEMn
+ *  0b0110..32KB OCMEMn
+ *  0b0111..64KB OCMEMn
+ *  0b1000..128KB OCMEMn
+ *  0b1001..256KB OCMEMn
+ *  0b1010..512KB OCMEMn
+ *  0b1011..1MB OCMEMn
+ *  0b1100..2MB OCMEMn
+ *  0b1101..4MB OCMEMn
+ *  0b1110..8MB OCMEMn
+ *  0b1111..16MB OCMEMn
+ */
+#define MSCM_OCMDR3_OCMSZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMSZ_SHIFT)) & MSCM_OCMDR3_OCMSZ_MASK)
+#define MSCM_OCMDR3_OCMSZH_MASK                  (0x10000000U)
+#define MSCM_OCMDR3_OCMSZH_SHIFT                 (28U)
+/*! OCMSZH - OCMSZH
+ *  0b0..OCMEMn is a power-of-2 capacity.
+ *  0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
+ */
+#define MSCM_OCMDR3_OCMSZH(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMSZH_SHIFT)) & MSCM_OCMDR3_OCMSZH_MASK)
+#define MSCM_OCMDR3_V_MASK                       (0x80000000U)
+#define MSCM_OCMDR3_V_SHIFT                      (31U)
+/*! V - V
+ *  0b0..OCMEMn is not present.
+ *  0b1..OCMEMn is present.
+ */
+#define MSCM_OCMDR3_V(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_V_SHIFT)) & MSCM_OCMDR3_V_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group MSCM_Register_Masks */
+
+
+/* MSCM - Peripheral instance base addresses */
+/** Peripheral MSCM base address */
+#define MSCM_BASE                                (0x40001000u)
+/** Peripheral MSCM base pointer */
+#define MSCM                                     ((MSCM_Type *)MSCM_BASE)
+/** Array initializer of MSCM peripheral base addresses */
+#define MSCM_BASE_ADDRS                          { MSCM_BASE }
+/** Array initializer of MSCM peripheral base pointers */
+#define MSCM_BASE_PTRS                           { MSCM }
+
+/*!
+ * @}
+ */ /* end of group MSCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MTB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
+ * @{
+ */
+
+/** MTB - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t POSITION;                          /**< MTB Position Register, offset: 0x0 */
+  __IO uint32_t MASTER;                            /**< MTB Master Register, offset: 0x4 */
+  __IO uint32_t FLOW;                              /**< MTB Flow Register, offset: 0x8 */
+  __I  uint32_t BASE;                              /**< MTB Base Register, offset: 0xC */
+       uint8_t RESERVED_0[3824];
+  __I  uint32_t MODECTRL;                          /**< Integration Mode Control Register, offset: 0xF00 */
+       uint8_t RESERVED_1[156];
+  __I  uint32_t TAGSET;                            /**< Claim TAG Set Register, offset: 0xFA0 */
+  __I  uint32_t TAGCLEAR;                          /**< Claim TAG Clear Register, offset: 0xFA4 */
+       uint8_t RESERVED_2[8];
+  __I  uint32_t LOCKACCESS;                        /**< Lock Access Register, offset: 0xFB0 */
+  __I  uint32_t LOCKSTAT;                          /**< Lock Status Register, offset: 0xFB4 */
+  __I  uint32_t AUTHSTAT;                          /**< Authentication Status Register, offset: 0xFB8 */
+  __I  uint32_t DEVICEARCH;                        /**< Device Architecture Register, offset: 0xFBC */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t DEVICECFG;                         /**< Device Configuration Register, offset: 0xFC8 */
+  __I  uint32_t DEVICETYPID;                       /**< Device Type Identifier Register, offset: 0xFCC */
+  __I  uint32_t PERIPHID4;                         /**< Peripheral ID Register, offset: 0xFD0 */
+  __I  uint32_t PERIPHID5;                         /**< Peripheral ID Register, offset: 0xFD4 */
+  __I  uint32_t PERIPHID6;                         /**< Peripheral ID Register, offset: 0xFD8 */
+  __I  uint32_t PERIPHID7;                         /**< Peripheral ID Register, offset: 0xFDC */
+  __I  uint32_t PERIPHID0;                         /**< Peripheral ID Register, offset: 0xFE0 */
+  __I  uint32_t PERIPHID1;                         /**< Peripheral ID Register, offset: 0xFE4 */
+  __I  uint32_t PERIPHID2;                         /**< Peripheral ID Register, offset: 0xFE8 */
+  __I  uint32_t PERIPHID3;                         /**< Peripheral ID Register, offset: 0xFEC */
+  __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTB_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MTB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Register_Masks MTB Register Masks
+ * @{
+ */
+
+/*! @name POSITION - MTB Position Register */
+/*! @{ */
+#define MTB_POSITION_WRAP_MASK                   (0x4U)
+#define MTB_POSITION_WRAP_SHIFT                  (2U)
+#define MTB_POSITION_WRAP(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK)
+#define MTB_POSITION_POINTER_MASK                (0xFFF8U)
+#define MTB_POSITION_POINTER_SHIFT               (3U)
+#define MTB_POSITION_POINTER(x)                  (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK)
+/*! @} */
+
+/*! @name MASTER - MTB Master Register */
+/*! @{ */
+#define MTB_MASTER_MASK_MASK                     (0x1FU)
+#define MTB_MASTER_MASK_SHIFT                    (0U)
+#define MTB_MASTER_MASK(x)                       (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK)
+#define MTB_MASTER_TSTARTEN_MASK                 (0x20U)
+#define MTB_MASTER_TSTARTEN_SHIFT                (5U)
+#define MTB_MASTER_TSTARTEN(x)                   (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK)
+#define MTB_MASTER_TSTOPEN_MASK                  (0x40U)
+#define MTB_MASTER_TSTOPEN_SHIFT                 (6U)
+#define MTB_MASTER_TSTOPEN(x)                    (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK)
+#define MTB_MASTER_SFRWPRIV_MASK                 (0x80U)
+#define MTB_MASTER_SFRWPRIV_SHIFT                (7U)
+#define MTB_MASTER_SFRWPRIV(x)                   (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK)
+#define MTB_MASTER_RAMPRIV_MASK                  (0x100U)
+#define MTB_MASTER_RAMPRIV_SHIFT                 (8U)
+#define MTB_MASTER_RAMPRIV(x)                    (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK)
+#define MTB_MASTER_HALTREQ_MASK                  (0x200U)
+#define MTB_MASTER_HALTREQ_SHIFT                 (9U)
+#define MTB_MASTER_HALTREQ(x)                    (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK)
+#define MTB_MASTER_EN_MASK                       (0x80000000U)
+#define MTB_MASTER_EN_SHIFT                      (31U)
+#define MTB_MASTER_EN(x)                         (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK)
+/*! @} */
+
+/*! @name FLOW - MTB Flow Register */
+/*! @{ */
+#define MTB_FLOW_AUTOSTOP_MASK                   (0x1U)
+#define MTB_FLOW_AUTOSTOP_SHIFT                  (0U)
+#define MTB_FLOW_AUTOSTOP(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK)
+#define MTB_FLOW_AUTOHALT_MASK                   (0x2U)
+#define MTB_FLOW_AUTOHALT_SHIFT                  (1U)
+#define MTB_FLOW_AUTOHALT(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK)
+#define MTB_FLOW_WATERMARK_MASK                  (0xFFFFFFF8U)
+#define MTB_FLOW_WATERMARK_SHIFT                 (3U)
+#define MTB_FLOW_WATERMARK(x)                    (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK)
+/*! @} */
+
+/*! @name BASE - MTB Base Register */
+/*! @{ */
+#define MTB_BASE_BASEADDR_MASK                   (0xFFFFFFFFU)
+#define MTB_BASE_BASEADDR_SHIFT                  (0U)
+#define MTB_BASE_BASEADDR(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK)
+/*! @} */
+
+/*! @name MODECTRL - Integration Mode Control Register */
+/*! @{ */
+#define MTB_MODECTRL_MODECTRL_MASK               (0xFFFFFFFFU)
+#define MTB_MODECTRL_MODECTRL_SHIFT              (0U)
+#define MTB_MODECTRL_MODECTRL(x)                 (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK)
+/*! @} */
+
+/*! @name TAGSET - Claim TAG Set Register */
+/*! @{ */
+#define MTB_TAGSET_TAGSET_MASK                   (0xFFFFFFFFU)
+#define MTB_TAGSET_TAGSET_SHIFT                  (0U)
+#define MTB_TAGSET_TAGSET(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK)
+/*! @} */
+
+/*! @name TAGCLEAR - Claim TAG Clear Register */
+/*! @{ */
+#define MTB_TAGCLEAR_TAGCLEAR_MASK               (0xFFFFFFFFU)
+#define MTB_TAGCLEAR_TAGCLEAR_SHIFT              (0U)
+#define MTB_TAGCLEAR_TAGCLEAR(x)                 (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK)
+/*! @} */
+
+/*! @name LOCKACCESS - Lock Access Register */
+/*! @{ */
+#define MTB_LOCKACCESS_LOCKACCESS_MASK           (0xFFFFFFFFU)
+#define MTB_LOCKACCESS_LOCKACCESS_SHIFT          (0U)
+#define MTB_LOCKACCESS_LOCKACCESS(x)             (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK)
+/*! @} */
+
+/*! @name LOCKSTAT - Lock Status Register */
+/*! @{ */
+#define MTB_LOCKSTAT_LOCKSTAT_MASK               (0xFFFFFFFFU)
+#define MTB_LOCKSTAT_LOCKSTAT_SHIFT              (0U)
+#define MTB_LOCKSTAT_LOCKSTAT(x)                 (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK)
+/*! @} */
+
+/*! @name AUTHSTAT - Authentication Status Register */
+/*! @{ */
+#define MTB_AUTHSTAT_BIT0_MASK                   (0x1U)
+#define MTB_AUTHSTAT_BIT0_SHIFT                  (0U)
+#define MTB_AUTHSTAT_BIT0(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK)
+#define MTB_AUTHSTAT_BIT1_MASK                   (0x2U)
+#define MTB_AUTHSTAT_BIT1_SHIFT                  (1U)
+#define MTB_AUTHSTAT_BIT1(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT1_SHIFT)) & MTB_AUTHSTAT_BIT1_MASK)
+#define MTB_AUTHSTAT_BIT2_MASK                   (0x4U)
+#define MTB_AUTHSTAT_BIT2_SHIFT                  (2U)
+#define MTB_AUTHSTAT_BIT2(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK)
+#define MTB_AUTHSTAT_BIT3_MASK                   (0x8U)
+#define MTB_AUTHSTAT_BIT3_SHIFT                  (3U)
+#define MTB_AUTHSTAT_BIT3(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT3_SHIFT)) & MTB_AUTHSTAT_BIT3_MASK)
+/*! @} */
+
+/*! @name DEVICEARCH - Device Architecture Register */
+/*! @{ */
+#define MTB_DEVICEARCH_DEVICEARCH_MASK           (0xFFFFFFFFU)
+#define MTB_DEVICEARCH_DEVICEARCH_SHIFT          (0U)
+#define MTB_DEVICEARCH_DEVICEARCH(x)             (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK)
+/*! @} */
+
+/*! @name DEVICECFG - Device Configuration Register */
+/*! @{ */
+#define MTB_DEVICECFG_DEVICECFG_MASK             (0xFFFFFFFFU)
+#define MTB_DEVICECFG_DEVICECFG_SHIFT            (0U)
+#define MTB_DEVICECFG_DEVICECFG(x)               (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK)
+/*! @} */
+
+/*! @name DEVICETYPID - Device Type Identifier Register */
+/*! @{ */
+#define MTB_DEVICETYPID_DEVICETYPID_MASK         (0xFFFFFFFFU)
+#define MTB_DEVICETYPID_DEVICETYPID_SHIFT        (0U)
+#define MTB_DEVICETYPID_DEVICETYPID(x)           (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK)
+/*! @} */
+
+/*! @name PERIPHID4 - Peripheral ID Register */
+/*! @{ */
+#define MTB_PERIPHID4_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID4_PERIPHID_SHIFT             (0U)
+#define MTB_PERIPHID4_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID4_PERIPHID_SHIFT)) & MTB_PERIPHID4_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID5 - Peripheral ID Register */
+/*! @{ */
+#define MTB_PERIPHID5_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID5_PERIPHID_SHIFT             (0U)
+#define MTB_PERIPHID5_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID5_PERIPHID_SHIFT)) & MTB_PERIPHID5_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID6 - Peripheral ID Register */
+/*! @{ */
+#define MTB_PERIPHID6_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID6_PERIPHID_SHIFT             (0U)
+#define MTB_PERIPHID6_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID6_PERIPHID_SHIFT)) & MTB_PERIPHID6_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID7 - Peripheral ID Register */
+/*! @{ */
+#define MTB_PERIPHID7_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID7_PERIPHID_SHIFT             (0U)
+#define MTB_PERIPHID7_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID7_PERIPHID_SHIFT)) & MTB_PERIPHID7_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID0 - Peripheral ID Register */
+/*! @{ */
+#define MTB_PERIPHID0_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID0_PERIPHID_SHIFT             (0U)
+#define MTB_PERIPHID0_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID0_PERIPHID_SHIFT)) & MTB_PERIPHID0_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID1 - Peripheral ID Register */
+/*! @{ */
+#define MTB_PERIPHID1_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID1_PERIPHID_SHIFT             (0U)
+#define MTB_PERIPHID1_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID1_PERIPHID_SHIFT)) & MTB_PERIPHID1_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID2 - Peripheral ID Register */
+/*! @{ */
+#define MTB_PERIPHID2_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID2_PERIPHID_SHIFT             (0U)
+#define MTB_PERIPHID2_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID2_PERIPHID_SHIFT)) & MTB_PERIPHID2_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID3 - Peripheral ID Register */
+/*! @{ */
+#define MTB_PERIPHID3_PERIPHID_MASK              (0xFFFFFFFFU)
+#define MTB_PERIPHID3_PERIPHID_SHIFT             (0U)
+#define MTB_PERIPHID3_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID3_PERIPHID_SHIFT)) & MTB_PERIPHID3_PERIPHID_MASK)
+/*! @} */
+
+/*! @name COMPID - Component ID Register */
+/*! @{ */
+#define MTB_COMPID_COMPID_MASK                   (0xFFFFFFFFU)
+#define MTB_COMPID_COMPID_SHIFT                  (0U)
+#define MTB_COMPID_COMPID(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK)
+/*! @} */
+
+/* The count of MTB_COMPID */
+#define MTB_COMPID_COUNT                         (4U)
+
+
+/*!
+ * @}
+ */ /* end of group MTB_Register_Masks */
+
+
+/* MTB - Peripheral instance base addresses */
+/** Peripheral MTB base address */
+#define MTB_BASE                                 (0xF0000000u)
+/** Peripheral MTB base pointer */
+#define MTB                                      ((MTB_Type *)MTB_BASE)
+/** Array initializer of MTB peripheral base addresses */
+#define MTB_BASE_ADDRS                           { MTB_BASE }
+/** Array initializer of MTB peripheral base pointers */
+#define MTB_BASE_PTRS                            { MTB }
+
+/*!
+ * @}
+ */ /* end of group MTB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MTBDWT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
+ * @{
+ */
+
+/** MTBDWT - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t CTRL;                              /**< DWT Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[28];
+  struct {                                         /* offset: 0x20, array step: 0x10 */
+    __IO uint32_t COMP;                              /**< DWT Comparator Register, array offset: 0x20, array step: 0x10 */
+    __IO uint32_t MASK;                              /**< DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
+    __IO uint32_t FCT;                               /**< DWT Comparator Function Register 0..DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
+         uint8_t RESERVED_0[4];
+  } COMPARATOR[2];
+       uint8_t RESERVED_1[448];
+  __IO uint32_t TBCTRL;                            /**< DWT Trace Buffer Control Register, offset: 0x200 */
+       uint8_t RESERVED_2[3524];
+  __I  uint32_t DEVICECFG;                         /**< Device Configuration Register, offset: 0xFC8 */
+  __I  uint32_t DEVICETYPID;                       /**< Device Type Identifier Register, offset: 0xFCC */
+  __I  uint32_t PERIPHID4;                         /**< Peripheral ID Register, offset: 0xFD0 */
+  __I  uint32_t PERIPHID5;                         /**< Peripheral ID Register, offset: 0xFD4 */
+  __I  uint32_t PERIPHID6;                         /**< Peripheral ID Register, offset: 0xFD8 */
+  __I  uint32_t PERIPHID7;                         /**< Peripheral ID Register, offset: 0xFDC */
+  __I  uint32_t PERIPHID0;                         /**< Peripheral ID Register, offset: 0xFE0 */
+  __I  uint32_t PERIPHID1;                         /**< Peripheral ID Register, offset: 0xFE4 */
+  __I  uint32_t PERIPHID2;                         /**< Peripheral ID Register, offset: 0xFE8 */
+  __I  uint32_t PERIPHID3;                         /**< Peripheral ID Register, offset: 0xFEC */
+  __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTBDWT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MTBDWT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
+ * @{
+ */
+
+/*! @name CTRL - DWT Control Register */
+/*! @{ */
+#define MTBDWT_CTRL_DWTCFGCTRL_MASK              (0xFFFFFFFU)
+#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT             (0U)
+#define MTBDWT_CTRL_DWTCFGCTRL(x)                (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK)
+#define MTBDWT_CTRL_NUMCMP_MASK                  (0xF0000000U)
+#define MTBDWT_CTRL_NUMCMP_SHIFT                 (28U)
+#define MTBDWT_CTRL_NUMCMP(x)                    (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK)
+/*! @} */
+
+/*! @name COMP - DWT Comparator Register */
+/*! @{ */
+#define MTBDWT_COMP_COMP_MASK                    (0xFFFFFFFFU)
+#define MTBDWT_COMP_COMP_SHIFT                   (0U)
+#define MTBDWT_COMP_COMP(x)                      (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK)
+/*! @} */
+
+/* The count of MTBDWT_COMP */
+#define MTBDWT_COMP_COUNT                        (2U)
+
+/*! @name MASK - DWT Comparator Mask Register */
+/*! @{ */
+#define MTBDWT_MASK_MASK_MASK                    (0x1FU)
+#define MTBDWT_MASK_MASK_SHIFT                   (0U)
+#define MTBDWT_MASK_MASK(x)                      (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK)
+/*! @} */
+
+/* The count of MTBDWT_MASK */
+#define MTBDWT_MASK_COUNT                        (2U)
+
+/*! @name FCT - DWT Comparator Function Register 0..DWT Comparator Function Register 1 */
+/*! @{ */
+#define MTBDWT_FCT_FUNCTION_MASK                 (0xFU)
+#define MTBDWT_FCT_FUNCTION_SHIFT                (0U)
+/*! FUNCTION - Function
+ *  0b0000..Disabled.
+ *  0b0001-0b0011..Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.
+ *  0b0100..Instruction fetch.
+ *  0b0101..Data operand read.
+ *  0b0110..Data operand write.
+ *  0b0111..Data operand (read + write).
+ *  0b1000-0b1111..Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.
+ */
+#define MTBDWT_FCT_FUNCTION(x)                   (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK)
+#define MTBDWT_FCT_DATAVMATCH_MASK               (0x100U)
+#define MTBDWT_FCT_DATAVMATCH_SHIFT              (8U)
+/*! DATAVMATCH - Data Value Match
+ *  0b0..Perform address comparison.
+ *  0b1..Perform data value comparison.
+ */
+#define MTBDWT_FCT_DATAVMATCH(x)                 (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK)
+#define MTBDWT_FCT_DATAVSIZE_MASK                (0xC00U)
+#define MTBDWT_FCT_DATAVSIZE_SHIFT               (10U)
+/*! DATAVSIZE - Data Value Size
+ *  0b00..Byte.
+ *  0b01..Halfword.
+ *  0b10..Word.
+ *  0b11..Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.
+ */
+#define MTBDWT_FCT_DATAVSIZE(x)                  (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK)
+#define MTBDWT_FCT_DATAVADDR0_MASK               (0xF000U)
+#define MTBDWT_FCT_DATAVADDR0_SHIFT              (12U)
+#define MTBDWT_FCT_DATAVADDR0(x)                 (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK)
+#define MTBDWT_FCT_MATCHED_MASK                  (0x1000000U)
+#define MTBDWT_FCT_MATCHED_SHIFT                 (24U)
+/*! MATCHED - Comparator match
+ *  0b0..No match.
+ *  0b1..Match occurred.
+ */
+#define MTBDWT_FCT_MATCHED(x)                    (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK)
+/*! @} */
+
+/* The count of MTBDWT_FCT */
+#define MTBDWT_FCT_COUNT                         (2U)
+
+/*! @name TBCTRL - DWT Trace Buffer Control Register */
+/*! @{ */
+#define MTBDWT_TBCTRL_ACOMP0_MASK                (0x1U)
+#define MTBDWT_TBCTRL_ACOMP0_SHIFT               (0U)
+/*! ACOMP0 - Action based on Comparator 0 match
+ *  0b0..Trigger TSTOP based on the assertion of FCT0[MATCHED].
+ *  0b1..Trigger TSTART based on the assertion of FCT0[MATCHED].
+ */
+#define MTBDWT_TBCTRL_ACOMP0(x)                  (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK)
+#define MTBDWT_TBCTRL_ACOMP1_MASK                (0x2U)
+#define MTBDWT_TBCTRL_ACOMP1_SHIFT               (1U)
+/*! ACOMP1 - Action based on Comparator 1 match
+ *  0b0..Trigger TSTOP based on the assertion of FCT1[MATCHED].
+ *  0b1..Trigger TSTART based on the assertion of FCT1[MATCHED].
+ */
+#define MTBDWT_TBCTRL_ACOMP1(x)                  (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK)
+#define MTBDWT_TBCTRL_NUMCOMP_MASK               (0xF0000000U)
+#define MTBDWT_TBCTRL_NUMCOMP_SHIFT              (28U)
+#define MTBDWT_TBCTRL_NUMCOMP(x)                 (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK)
+/*! @} */
+
+/*! @name DEVICECFG - Device Configuration Register */
+/*! @{ */
+#define MTBDWT_DEVICECFG_DEVICECFG_MASK          (0xFFFFFFFFU)
+#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT         (0U)
+#define MTBDWT_DEVICECFG_DEVICECFG(x)            (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK)
+/*! @} */
+
+/*! @name DEVICETYPID - Device Type Identifier Register */
+/*! @{ */
+#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK      (0xFFFFFFFFU)
+#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT     (0U)
+#define MTBDWT_DEVICETYPID_DEVICETYPID(x)        (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
+/*! @} */
+
+/*! @name PERIPHID4 - Peripheral ID Register */
+/*! @{ */
+#define MTBDWT_PERIPHID4_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID4_PERIPHID_SHIFT          (0U)
+#define MTBDWT_PERIPHID4_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID4_PERIPHID_SHIFT)) & MTBDWT_PERIPHID4_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID5 - Peripheral ID Register */
+/*! @{ */
+#define MTBDWT_PERIPHID5_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID5_PERIPHID_SHIFT          (0U)
+#define MTBDWT_PERIPHID5_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID5_PERIPHID_SHIFT)) & MTBDWT_PERIPHID5_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID6 - Peripheral ID Register */
+/*! @{ */
+#define MTBDWT_PERIPHID6_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID6_PERIPHID_SHIFT          (0U)
+#define MTBDWT_PERIPHID6_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID6_PERIPHID_SHIFT)) & MTBDWT_PERIPHID6_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID7 - Peripheral ID Register */
+/*! @{ */
+#define MTBDWT_PERIPHID7_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID7_PERIPHID_SHIFT          (0U)
+#define MTBDWT_PERIPHID7_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID7_PERIPHID_SHIFT)) & MTBDWT_PERIPHID7_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID0 - Peripheral ID Register */
+/*! @{ */
+#define MTBDWT_PERIPHID0_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID0_PERIPHID_SHIFT          (0U)
+#define MTBDWT_PERIPHID0_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID0_PERIPHID_SHIFT)) & MTBDWT_PERIPHID0_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID1 - Peripheral ID Register */
+/*! @{ */
+#define MTBDWT_PERIPHID1_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID1_PERIPHID_SHIFT          (0U)
+#define MTBDWT_PERIPHID1_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID1_PERIPHID_SHIFT)) & MTBDWT_PERIPHID1_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID2 - Peripheral ID Register */
+/*! @{ */
+#define MTBDWT_PERIPHID2_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID2_PERIPHID_SHIFT          (0U)
+#define MTBDWT_PERIPHID2_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID2_PERIPHID_SHIFT)) & MTBDWT_PERIPHID2_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID3 - Peripheral ID Register */
+/*! @{ */
+#define MTBDWT_PERIPHID3_PERIPHID_MASK           (0xFFFFFFFFU)
+#define MTBDWT_PERIPHID3_PERIPHID_SHIFT          (0U)
+#define MTBDWT_PERIPHID3_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID3_PERIPHID_SHIFT)) & MTBDWT_PERIPHID3_PERIPHID_MASK)
+/*! @} */
+
+/*! @name COMPID - Component ID Register */
+/*! @{ */
+#define MTBDWT_COMPID_COMPID_MASK                (0xFFFFFFFFU)
+#define MTBDWT_COMPID_COMPID_SHIFT               (0U)
+#define MTBDWT_COMPID_COMPID(x)                  (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK)
+/*! @} */
+
+/* The count of MTBDWT_COMPID */
+#define MTBDWT_COMPID_COUNT                      (4U)
+
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Register_Masks */
+
+
+/* MTBDWT - Peripheral instance base addresses */
+/** Peripheral MTBDWT base address */
+#define MTBDWT_BASE                              (0xF0001000u)
+/** Peripheral MTBDWT base pointer */
+#define MTBDWT                                   ((MTBDWT_Type *)MTBDWT_BASE)
+/** Array initializer of MTBDWT peripheral base addresses */
+#define MTBDWT_BASE_ADDRS                        { MTBDWT_BASE }
+/** Array initializer of MTBDWT peripheral base pointers */
+#define MTBDWT_BASE_PTRS                         { MTBDWT }
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Peripheral_Access_Layer */
+
+/*!
+ * @brief Core boot mode.
+ */
+typedef enum _mu_core_boot_mode
+{
+    kMU_CoreBootFromPflashBase = 0x00U, /*!< Boot from pflash base.  */
+    kMU_CoreBootFromCore0RamBase = 0x02U, /*!< Boot from RI5CY RAM base. */
+} mu_core_boot_mode_t;
+/*!
+ * @brief Power mode on the other side definition.
+ */
+typedef enum _mu_power_mode
+{
+    kMU_PowerModeRun = 0x00U,  /*!< Run mode.           */
+    kMU_PowerModeCoo = 0x01U,  /*!< COO mode.           */
+    kMU_PowerModeWait = 0x02U, /*!< WAIT mode.          */
+    kMU_PowerModeStop = 0x03U, /*!< STOP/VLPS mode.     */
+    kMU_PowerModeDsm = 0x04U   /*!< DSM: LLS/VLLS mode. */
+} mu_power_mode_t;
+
+
+/* ----------------------------------------------------------------------------
+   -- MU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer
+ * @{
+ */
+
+/** MU - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VER;                               /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PAR;                               /**< Parameter Register, offset: 0x4 */
+       uint8_t RESERVED_0[24];
+  __IO uint32_t TR[4];                             /**< Transmit Register, array offset: 0x20, array step: 0x4 */
+       uint8_t RESERVED_1[16];
+  __I  uint32_t RR[4];                             /**< Receive Register, array offset: 0x40, array step: 0x4 */
+       uint8_t RESERVED_2[16];
+  __IO uint32_t SR;                                /**< Status Register, offset: 0x60 */
+  __IO uint32_t CR;                                /**< Control Register, offset: 0x64 */
+  __IO uint32_t CCR;                               /**< Core Control Register, offset: 0x68 */
+} MU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MU_Register_Masks MU Register Masks
+ * @{
+ */
+
+/*! @name VER - Version ID Register */
+/*! @{ */
+#define MU_VER_FEATURE_MASK                      (0xFFFFU)
+#define MU_VER_FEATURE_SHIFT                     (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b000000000000x1xx..Core Control and Status Registers are implemented in both MUA and MUB.
+ *  0b000000000000xx1x..RAIP/RAIE register bits are implemented.
+ *  0b000000000000xxx0..Standard features implemented
+ */
+#define MU_VER_FEATURE(x)                        (((uint32_t)(((uint32_t)(x)) << MU_VER_FEATURE_SHIFT)) & MU_VER_FEATURE_MASK)
+#define MU_VER_MINOR_MASK                        (0xFF0000U)
+#define MU_VER_MINOR_SHIFT                       (16U)
+#define MU_VER_MINOR(x)                          (((uint32_t)(((uint32_t)(x)) << MU_VER_MINOR_SHIFT)) & MU_VER_MINOR_MASK)
+#define MU_VER_MAJOR_MASK                        (0xFF000000U)
+#define MU_VER_MAJOR_SHIFT                       (24U)
+#define MU_VER_MAJOR(x)                          (((uint32_t)(((uint32_t)(x)) << MU_VER_MAJOR_SHIFT)) & MU_VER_MAJOR_MASK)
+/*! @} */
+
+/*! @name PAR - Parameter Register */
+/*! @{ */
+#define MU_PAR_PARAMETER_MASK                    (0xFFFFFFFFU)
+#define MU_PAR_PARAMETER_SHIFT                   (0U)
+#define MU_PAR_PARAMETER(x)                      (((uint32_t)(((uint32_t)(x)) << MU_PAR_PARAMETER_SHIFT)) & MU_PAR_PARAMETER_MASK)
+/*! @} */
+
+/*! @name TR - Transmit Register */
+/*! @{ */
+#define MU_TR_DATA_MASK                          (0xFFFFFFFFU)
+#define MU_TR_DATA_SHIFT                         (0U)
+#define MU_TR_DATA(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TR_DATA_SHIFT)) & MU_TR_DATA_MASK)
+/*! @} */
+
+/* The count of MU_TR */
+#define MU_TR_COUNT                              (4U)
+
+/*! @name RR - Receive Register */
+/*! @{ */
+#define MU_RR_DATA_MASK                          (0xFFFFFFFFU)
+#define MU_RR_DATA_SHIFT                         (0U)
+#define MU_RR_DATA(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RR_DATA_SHIFT)) & MU_RR_DATA_MASK)
+/*! @} */
+
+/* The count of MU_RR */
+#define MU_RR_COUNT                              (4U)
+
+/*! @name SR - Status Register */
+/*! @{ */
+#define MU_SR_Fn_MASK                            (0x7U)
+#define MU_SR_Fn_SHIFT                           (0U)
+/*! Fn - Fn
+ *  0b000..Fn bit in the MUA CR register is written 0 (default).
+ *  0b001..Fn bit in the MUA CR register is written 1.
+ */
+#define MU_SR_Fn(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK)
+#define MU_SR_NMIC_MASK                          (0x8U)
+#define MU_SR_NMIC_SHIFT                         (3U)
+/*! NMIC - NMIC
+ *  0b0..Default
+ *  0b1..Writing "1" clears the NMI bit in the MUA CR register.
+ */
+#define MU_SR_NMIC(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_NMIC_SHIFT)) & MU_SR_NMIC_MASK)
+#define MU_SR_EP_MASK                            (0x10U)
+#define MU_SR_EP_SHIFT                           (4U)
+/*! EP - EP
+ *  0b0..The MUB side event is not pending (default).
+ *  0b1..The MUB side event is pending.
+ */
+#define MU_SR_EP(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK)
+#define MU_SR_HRIP_MASK                          (0x80U)
+#define MU_SR_HRIP_SHIFT                         (7U)
+/*! HRIP - HRIP
+ *  0b0..MUA didn't issue hardware reset to Processor B
+ *  0b1..MUA had initiated a hardware reset to Processor B through HR bit.
+ */
+#define MU_SR_HRIP(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_HRIP_SHIFT)) & MU_SR_HRIP_MASK)
+#define MU_SR_FUP_MASK                           (0x100U)
+#define MU_SR_FUP_SHIFT                          (8U)
+/*! FUP - FUP
+ *  0b0..No flags updated, initiated by the MUB, in progress (default)
+ *  0b1..MUB initiated flags update, processing
+ */
+#define MU_SR_FUP(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK)
+#define MU_SR_RDIP_MASK                          (0x200U)
+#define MU_SR_RDIP_SHIFT                         (9U)
+/*! RDIP - RDIP
+ *  0b0..Processor A did not exit reset
+ *  0b1..Processor A exited from reset
+ */
+#define MU_SR_RDIP(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_RDIP_SHIFT)) & MU_SR_RDIP_MASK)
+#define MU_SR_RAIP_MASK                          (0x400U)
+#define MU_SR_RAIP_SHIFT                         (10U)
+/*! RAIP - RAIP
+ *  0b0..Processor A did not enter reset
+ *  0b1..Processor A entered reset
+ */
+#define MU_SR_RAIP(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_RAIP_SHIFT)) & MU_SR_RAIP_MASK)
+#define MU_SR_MURIP_MASK                         (0x800U)
+#define MU_SR_MURIP_SHIFT                        (11U)
+/*! MURIP - MURIP
+ *  0b0..Processor A did not issue MU reset
+ *  0b1..Processor A issued MU reset
+ */
+#define MU_SR_MURIP(x)                           (((uint32_t)(((uint32_t)(x)) << MU_SR_MURIP_SHIFT)) & MU_SR_MURIP_MASK)
+#define MU_SR_PM_MASK                            (0x7000U)
+#define MU_SR_PM_SHIFT                           (12U)
+/*! PM - PM
+ *  0b000..The MUA processor is in Run Mode.
+ *  0b001..The MUA processor is in COO Mode.
+ *  0b010..The MUA processor is in WAIT Mode.
+ *  0b011..The MUA processor is in STOP/VLPS Mode.
+ *  0b100..The MUA processor is in LLS/VLLS Mode.
+ */
+#define MU_SR_PM(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_PM_SHIFT)) & MU_SR_PM_MASK)
+#define MU_SR_TEn_MASK                           (0xF00000U)
+#define MU_SR_TEn_SHIFT                          (20U)
+/*! TEn - TEn
+ *  0b0000..MUB TRn register is not empty.
+ *  0b0001..MUB TRn register is empty (default).
+ */
+#define MU_SR_TEn(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK)
+#define MU_SR_RFn_MASK                           (0xF000000U)
+#define MU_SR_RFn_SHIFT                          (24U)
+/*! RFn - RFn
+ *  0b0000..MUB RRn register is not full (default).
+ *  0b0001..MUB RRn register has received data from MUA TRn register and is ready to be read by the MUB.
+ */
+#define MU_SR_RFn(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK)
+#define MU_SR_GIPn_MASK                          (0xF0000000U)
+#define MU_SR_GIPn_SHIFT                         (28U)
+/*! GIPn - GIPn
+ *  0b0000..MUB general purpose interrupt n is not pending. (default)
+ *  0b0001..MUB general purpose interrupt n is pending.
+ */
+#define MU_SR_GIPn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK)
+/*! @} */
+
+/*! @name CR - Control Register */
+/*! @{ */
+#define MU_CR_Fn_MASK                            (0x7U)
+#define MU_CR_Fn_SHIFT                           (0U)
+/*! Fn - Fn
+ *  0b000..Clears the Fn bit in the SR register.
+ *  0b001..Sets the Fn bit in the SR register.
+ */
+#define MU_CR_Fn(x)                              (((uint32_t)(((uint32_t)(x)) << MU_CR_Fn_SHIFT)) & MU_CR_Fn_MASK)
+#define MU_CR_NMI_MASK                           (0x8U)
+#define MU_CR_NMI_SHIFT                          (3U)
+/*! NMI - NMI
+ *  0b0..Non-maskable interrupt is not issued to the Processor A by the Processor B (default).
+ *  0b1..Non-maskable interrupt is issued to the Processor A by the Processor B.
+ */
+#define MU_CR_NMI(x)                             (((uint32_t)(((uint32_t)(x)) << MU_CR_NMI_SHIFT)) & MU_CR_NMI_MASK)
+#define MU_CR_MUR_MASK                           (0x20U)
+#define MU_CR_MUR_SHIFT                          (5U)
+/*! MUR - MUR
+ *  0b0..N/A. Self clearing bit (default).
+ *  0b1..Asserts the MU reset.
+ */
+#define MU_CR_MUR(x)                             (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
+#define MU_CR_RDIE_MASK                          (0x40U)
+#define MU_CR_RDIE_SHIFT                         (6U)
+/*! RDIE - RDIE
+ *  0b0..Disables Processor B General Purpose Interrupt 3 request due to Processor A reset de-assertion.
+ *  0b1..Enables Processor B General Purpose Interrupt 3 request due to Processor A reset de-assertion.
+ */
+#define MU_CR_RDIE(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_RDIE_SHIFT)) & MU_CR_RDIE_MASK)
+#define MU_CR_HRIE_MASK                          (0x80U)
+#define MU_CR_HRIE_SHIFT                         (7U)
+/*! HRIE - Processor B hardware reset interrupt enable
+ *  0b0..Disables Processor B General Purpose Interrupt 3 request due to Processor A issued HR to Processor B.
+ *  0b1..Enables Processor B General Purpose Interrupt 3 request due to Processor A issued HR to Processor B.
+ */
+#define MU_CR_HRIE(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_HRIE_SHIFT)) & MU_CR_HRIE_MASK)
+#define MU_CR_MURIE_MASK                         (0x800U)
+#define MU_CR_MURIE_SHIFT                        (11U)
+/*! MURIE - MURIE
+ *  0b0..Disables Processor B-side General Purpose Interrupt 3 request due to MU reset issued by MUA.
+ *  0b1..Enables Processor B-side General Purpose Interrupt 3 request due to MU reset issued by MUA.
+ */
+#define MU_CR_MURIE(x)                           (((uint32_t)(((uint32_t)(x)) << MU_CR_MURIE_SHIFT)) & MU_CR_MURIE_MASK)
+#define MU_CR_RAIE_MASK                          (0x1000U)
+#define MU_CR_RAIE_SHIFT                         (12U)
+/*! RAIE - RAIE
+ *  0b0..Disables Processor B-side General Purpose Interrupt 3 request due to Processor A reset assertion.
+ *  0b1..Enables Processor B-side General Purpose Interrupt 3 request due to Processor A reset assertion.
+ */
+#define MU_CR_RAIE(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_RAIE_SHIFT)) & MU_CR_RAIE_MASK)
+#define MU_CR_GIRn_MASK                          (0xF0000U)
+#define MU_CR_GIRn_SHIFT                         (16U)
+/*! GIRn - GIRn
+ *  0b0000..MUB General Interrupt n is not requested to the MUA (default).
+ *  0b0001..MUB General Interrupt n is requested to the MUA.
+ */
+#define MU_CR_GIRn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)
+#define MU_CR_TIEn_MASK                          (0xF00000U)
+#define MU_CR_TIEn_SHIFT                         (20U)
+/*! TIEn - TIEn
+ *  0b0000..Disables MUB Transmit Interrupt n. (default)
+ *  0b0001..Enables MUB Transmit Interrupt n.
+ */
+#define MU_CR_TIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK)
+#define MU_CR_RIEn_MASK                          (0xF000000U)
+#define MU_CR_RIEn_SHIFT                         (24U)
+/*! RIEn - RIEn
+ *  0b0000..Disables MUB Receive Interrupt n. (default)
+ *  0b0001..Enables MUB Receive Interrupt n.
+ */
+#define MU_CR_RIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK)
+#define MU_CR_GIEn_MASK                          (0xF0000000U)
+#define MU_CR_GIEn_SHIFT                         (28U)
+/*! GIEn - GIEn
+ *  0b0000..Disables MUB General Interrupt n. (default)
+ *  0b0001..Enables MUB General Interrupt n.
+ */
+#define MU_CR_GIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK)
+/*! @} */
+
+/*! @name CCR - Core Control Register */
+/*! @{ */
+#define MU_CCR_HR_MASK                           (0x1U)
+#define MU_CCR_HR_SHIFT                          (0U)
+/*! HR - HR
+ *  0b0..De-assert Hardware reset to the Processor A. (default)
+ *  0b1..Assert Hardware reset to the Processor A.
+ */
+#define MU_CCR_HR(x)                             (((uint32_t)(((uint32_t)(x)) << MU_CCR_HR_SHIFT)) & MU_CCR_HR_MASK)
+#define MU_CCR_HRM_MASK                          (0x2U)
+#define MU_CCR_HRM_SHIFT                         (1U)
+/*! HRM - When set, HR bit in MUA CCR has no effect
+ *  0b0..HR bit in MUA CCR is not masked, enables the hardware reset to the Processor B (default after hardware reset).
+ *  0b1..HR bit in MUA CCR is masked, disables the hardware reset request to the Processor B.
+ */
+#define MU_CCR_HRM(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CCR_HRM_SHIFT)) & MU_CCR_HRM_MASK)
+#define MU_CCR_RSTH_MASK                         (0x4U)
+#define MU_CCR_RSTH_SHIFT                        (2U)
+/*! RSTH - Processor A Reset Hold
+ *  0b0..Release Processor A from reset
+ *  0b1..Hold Processor A in reset
+ */
+#define MU_CCR_RSTH(x)                           (((uint32_t)(((uint32_t)(x)) << MU_CCR_RSTH_SHIFT)) & MU_CCR_RSTH_MASK)
+#define MU_CCR_CLKE_MASK                         (0x8U)
+#define MU_CCR_CLKE_SHIFT                        (3U)
+/*! CLKE - MUA clock enable
+ *  0b0..MUA platform clock gated when MUA-side enters a stop mode.
+ *  0b1..MUA platform clock kept running after MUA-side enters a stop mode, until MUB also enters a stop mode.
+ */
+#define MU_CCR_CLKE(x)                           (((uint32_t)(((uint32_t)(x)) << MU_CCR_CLKE_SHIFT)) & MU_CCR_CLKE_MASK)
+#define MU_CCR_BOOT_MASK                         (0x30U)
+#define MU_CCR_BOOT_SHIFT                        (4U)
+/*! BOOT - Slave Processor A Boot Config.
+ *  0b00..Boot from Pflash base
+ *  0b01..Reserved
+ *  0b10..Boot from CM4 RAM base
+ *  0b11..Reserved
+ */
+#define MU_CCR_BOOT(x)                           (((uint32_t)(((uint32_t)(x)) << MU_CCR_BOOT_SHIFT)) & MU_CCR_BOOT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group MU_Register_Masks */
+
+
+/* MU - Peripheral instance base addresses */
+/** Peripheral MUB base address */
+#define MUB_BASE                                 (0x41024000u)
+/** Peripheral MUB base pointer */
+#define MUB                                      ((MU_Type *)MUB_BASE)
+/** Array initializer of MU peripheral base addresses */
+#define MU_BASE_ADDRS                            { MUB_BASE }
+/** Array initializer of MU peripheral base pointers */
+#define MU_BASE_PTRS                             { MUB }
+/** Interrupt vectors for the MU peripheral type */
+#define MU_IRQS                                  { MUB_IRQn }
+
+/*!
+ * @}
+ */ /* end of group MU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PCC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PCC_Peripheral_Access_Layer PCC Peripheral Access Layer
+ * @{
+ */
+
+/** PCC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CLKCFG[130];                       /**< PCC MSCM Register..PCC EXT_CLK Register, array offset: 0x0, array step: 0x4 */
+} PCC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PCC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PCC_Register_Masks PCC Register Masks
+ * @{
+ */
+
+/*! @name CLKCFG - PCC MSCM Register..PCC EXT_CLK Register */
+/*! @{ */
+#define PCC_CLKCFG_PCD_MASK                      (0x7U)
+#define PCC_CLKCFG_PCD_SHIFT                     (0U)
+/*! PCD - Peripheral Clock Divider Select
+ *  0b000..Divide by 1.
+ *  0b001..Divide by 2.
+ *  0b010..Divide by 3.
+ *  0b011..Divide by 4.
+ *  0b100..Divide by 5.
+ *  0b101..Divide by 6.
+ *  0b110..Divide by 7.
+ *  0b111..Divide by 8.
+ */
+#define PCC_CLKCFG_PCD(x)                        (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PCD_SHIFT)) & PCC_CLKCFG_PCD_MASK)
+#define PCC_CLKCFG_FRAC_MASK                     (0x8U)
+#define PCC_CLKCFG_FRAC_SHIFT                    (3U)
+/*! FRAC - Peripheral Clock Divider Fraction
+ *  0b0..Fractional value is 0.
+ *  0b1..Fractional value is 1.
+ */
+#define PCC_CLKCFG_FRAC(x)                       (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_FRAC_SHIFT)) & PCC_CLKCFG_FRAC_MASK)
+#define PCC_CLKCFG_PCS_MASK                      (0x7000000U)
+#define PCC_CLKCFG_PCS_SHIFT                     (24U)
+/*! PCS - Peripheral Clock Source Select
+ *  0b000..Clock is off. An external clock can be enabled for this peripheral.
+ *  0b001..Clock option 1
+ *  0b010..Clock option 2
+ *  0b011..Clock option 3
+ *  0b100..Clock option 4
+ *  0b101..Clock option 5
+ *  0b110..Clock option 6
+ *  0b111..Clock option 7
+ */
+#define PCC_CLKCFG_PCS(x)                        (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PCS_SHIFT)) & PCC_CLKCFG_PCS_MASK)
+#define PCC_CLKCFG_INUSE_MASK                    (0x20000000U)
+#define PCC_CLKCFG_INUSE_SHIFT                   (29U)
+/*! INUSE - In use flag
+ *  0b0..Peripheral is not being used.
+ *  0b1..Peripheral is being used. Software cannot modify the existing clocking configuration.
+ */
+#define PCC_CLKCFG_INUSE(x)                      (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_INUSE_SHIFT)) & PCC_CLKCFG_INUSE_MASK)
+#define PCC_CLKCFG_CGC_MASK                      (0x40000000U)
+#define PCC_CLKCFG_CGC_SHIFT                     (30U)
+/*! CGC - Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled. The current clock selection and divider options are locked.
+ */
+#define PCC_CLKCFG_CGC(x)                        (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_CGC_SHIFT)) & PCC_CLKCFG_CGC_MASK)
+#define PCC_CLKCFG_PR_MASK                       (0x80000000U)
+#define PCC_CLKCFG_PR_SHIFT                      (31U)
+/*! PR - Present
+ *  0b0..Peripheral is not present.
+ *  0b1..Peripheral is present.
+ */
+#define PCC_CLKCFG_PR(x)                         (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PR_SHIFT)) & PCC_CLKCFG_PR_MASK)
+/*! @} */
+
+/* The count of PCC_CLKCFG */
+#define PCC_CLKCFG_COUNT                         (130U)
+
+
+/*!
+ * @}
+ */ /* end of group PCC_Register_Masks */
+
+
+/* PCC - Peripheral instance base addresses */
+/** Peripheral PCC0 base address */
+#define PCC0_BASE                                (0x4002B000u)
+/** Peripheral PCC0 base pointer */
+#define PCC0                                     ((PCC_Type *)PCC0_BASE)
+/** Peripheral PCC1 base address */
+#define PCC1_BASE                                (0x41027000u)
+/** Peripheral PCC1 base pointer */
+#define PCC1                                     ((PCC_Type *)PCC1_BASE)
+/** Array initializer of PCC peripheral base addresses */
+#define PCC_BASE_ADDRS                           { PCC0_BASE, PCC1_BASE }
+/** Array initializer of PCC peripheral base pointers */
+#define PCC_BASE_PTRS                            { PCC0, PCC1 }
+#define    PCC_INSTANCE_MASK            (0xFu)
+#define    PCC_INSTANCE_SHIFT           (12u)
+#define    PCC_PERIPHERAL_MASK          (0xFFFu)
+#define    PCC_PERIPHERAL_SHIFT         (0u)
+#define    PCC_INSTANCE_0               (0u)
+#define    PCC_INSTANCE_1               (1u)
+
+#define    PCC_MSCM_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 1U)
+#define    PCC_AXBS0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 4U)
+#define    PCC_DMA0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 8U)
+#define    PCC_FLEXBUS_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 12U)
+#define    PCC_XRDC_MGR_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 20U)
+#define    PCC0_XRDC_PAC_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 22U)
+#define    PCC0_XRDC_MRC_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 23U)
+#define    PCC_SEMA42_0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 27U)
+#define    PCC_DMAMUX0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 33U)
+#define    PCC_EWM_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 34U)
+#define    PCC_MUA_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 37U)
+#define    PCC_CRC0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 47U)
+#define    PCC_LPIT0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 48U)
+#define    PCC_TPM0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 53U)
+#define    PCC_TPM1_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 54U)
+#define    PCC_TPM2_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 55U)
+#define    PCC_EMVSIM0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 56U)
+#define    PCC_FLEXIO0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 57U)
+#define    PCC_LPI2C0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 58U)
+#define    PCC_LPI2C1_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 59U)
+#define    PCC_LPI2C2_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 60U)
+#define    PCC_I2S0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 61U)
+#define    PCC_USDHC0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 62U)
+#define    PCC_LPSPI0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 63U)
+#define    PCC_LPSPI1_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 64U)
+#define    PCC_LPSPI2_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 65U)
+#define    PCC_LPUART0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 66U)
+#define    PCC_LPUART1_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 67U)
+#define    PCC_LPUART2_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 68U)
+#define    PCC_USB0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 69U)
+#define    PCC_PORTA_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 70U)
+#define    PCC_PORTB_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 71U)
+#define    PCC_PORTC_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 72U)
+#define    PCC_PORTD_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 73U)
+#define    PCC_ADC0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 74U)
+#define    PCC_LPDAC0_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 76U)
+#define    PCC_VREF_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 77U)
+#define    PCC_TRACE_INDEX            ((uint16_t)((PCC_INSTANCE_0 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 128U)
+#define    PCC_DMA1_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 8U)
+#define    PCC_GPIOE_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 15U)
+#define    PCC1_XRDC_PAC_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 22U)
+#define    PCC1_XRDC_MRC_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 23U)
+#define    PCC_SEMA42_1_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 27U)
+#define    PCC_DMAMUX1_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 33U)
+#define    PCC_INTMUX1_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 34U)
+#define    PCC_MUB_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 36U)
+#define    PCC_CAU3_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 40U)
+#define    PCC_TRNG_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 41U)
+#define    PCC_LPIT1_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 42U)
+#define    PCC_TPM3_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 45U)
+#define    PCC_LPI2C3_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 46U)
+#define    PCC_LPSPI3_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 53U)
+#define    PCC_LPUART3_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 54U)
+#define    PCC_PORTE_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 55U)
+#define    PCC_MTB_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 128U)
+#define    PCC_EXT_CLK_INDEX            ((uint16_t)((PCC_INSTANCE_1 & PCC_INSTANCE_MASK) << PCC_INSTANCE_SHIFT) | 129U)
+#define    PCC_MSCM              (PCC0->CLKCFG[1])
+#define    PCC_AXBS0              (PCC0->CLKCFG[4])
+#define    PCC_DMA0              (PCC0->CLKCFG[8])
+#define    PCC_FLEXBUS              (PCC0->CLKCFG[12])
+#define    PCC_XRDC_MGR              (PCC0->CLKCFG[20])
+#define    PCC0_XRDC_PAC              (PCC0->CLKCFG[22])
+#define    PCC0_XRDC_MRC              (PCC0->CLKCFG[23])
+#define    PCC_SEMA42_0              (PCC0->CLKCFG[27])
+#define    PCC_DMAMUX0              (PCC0->CLKCFG[33])
+#define    PCC_EWM              (PCC0->CLKCFG[34])
+#define    PCC_MUA              (PCC0->CLKCFG[37])
+#define    PCC_CRC0              (PCC0->CLKCFG[47])
+#define    PCC_LPIT0              (PCC0->CLKCFG[48])
+#define    PCC_TPM0              (PCC0->CLKCFG[53])
+#define    PCC_TPM1              (PCC0->CLKCFG[54])
+#define    PCC_TPM2              (PCC0->CLKCFG[55])
+#define    PCC_EMVSIM0              (PCC0->CLKCFG[56])
+#define    PCC_FLEXIO0              (PCC0->CLKCFG[57])
+#define    PCC_LPI2C0              (PCC0->CLKCFG[58])
+#define    PCC_LPI2C1              (PCC0->CLKCFG[59])
+#define    PCC_LPI2C2              (PCC0->CLKCFG[60])
+#define    PCC_I2S0              (PCC0->CLKCFG[61])
+#define    PCC_USDHC0              (PCC0->CLKCFG[62])
+#define    PCC_LPSPI0              (PCC0->CLKCFG[63])
+#define    PCC_LPSPI1              (PCC0->CLKCFG[64])
+#define    PCC_LPSPI2              (PCC0->CLKCFG[65])
+#define    PCC_LPUART0              (PCC0->CLKCFG[66])
+#define    PCC_LPUART1              (PCC0->CLKCFG[67])
+#define    PCC_LPUART2              (PCC0->CLKCFG[68])
+#define    PCC_USB0              (PCC0->CLKCFG[69])
+#define    PCC_PORTA              (PCC0->CLKCFG[70])
+#define    PCC_PORTB              (PCC0->CLKCFG[71])
+#define    PCC_PORTC              (PCC0->CLKCFG[72])
+#define    PCC_PORTD              (PCC0->CLKCFG[73])
+#define    PCC_ADC0              (PCC0->CLKCFG[74])
+#define    PCC_LPDAC0              (PCC0->CLKCFG[76])
+#define    PCC_VREF              (PCC0->CLKCFG[77])
+#define    PCC_TRACE              (PCC0->CLKCFG[128])
+#define    PCC_DMA1              (PCC1->CLKCFG[8])
+#define    PCC_GPIOE              (PCC1->CLKCFG[15])
+#define    PCC1_XRDC_PAC              (PCC1->CLKCFG[22])
+#define    PCC1_XRDC_MRC              (PCC1->CLKCFG[23])
+#define    PCC_SEMA42_1              (PCC1->CLKCFG[27])
+#define    PCC_DMAMUX1              (PCC1->CLKCFG[33])
+#define    PCC_INTMUX1              (PCC1->CLKCFG[34])
+#define    PCC_MUB              (PCC1->CLKCFG[36])
+#define    PCC_CAU3              (PCC1->CLKCFG[40])
+#define    PCC_TRNG              (PCC1->CLKCFG[41])
+#define    PCC_LPIT1              (PCC1->CLKCFG[42])
+#define    PCC_TPM3              (PCC1->CLKCFG[45])
+#define    PCC_LPI2C3              (PCC1->CLKCFG[46])
+#define    PCC_LPSPI3              (PCC1->CLKCFG[53])
+#define    PCC_LPUART3              (PCC1->CLKCFG[54])
+#define    PCC_PORTE              (PCC1->CLKCFG[55])
+#define    PCC_MTB              (PCC1->CLKCFG[128])
+#define    PCC_EXT_CLK              (PCC1->CLKCFG[129])
+
+
+/*!
+ * @}
+ */ /* end of group PCC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PCR[32];                           /**< Pin Control Register 0..Pin Control Register 30, array offset: 0x0, array step: 0x4 */
+  __O  uint32_t GPCLR;                             /**< Global Pin Control Low Register, offset: 0x80 */
+  __O  uint32_t GPCHR;                             /**< Global Pin Control High Register, offset: 0x84 */
+  __O  uint32_t GICLR;                             /**< Global Interrupt Control Low Register, offset: 0x88 */
+  __O  uint32_t GICHR;                             /**< Global Interrupt Control High Register, offset: 0x8C */
+       uint8_t RESERVED_0[16];
+  __IO uint32_t ISFR;                              /**< Interrupt Status Flag Register, offset: 0xA0 */
+       uint8_t RESERVED_1[28];
+  __IO uint32_t DFER;                              /**< Digital Filter Enable Register, offset: 0xC0 */
+  __IO uint32_t DFCR;                              /**< Digital Filter Clock Register, offset: 0xC4 */
+  __IO uint32_t DFWR;                              /**< Digital Filter Width Register, offset: 0xC8 */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PORT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/*! @name PCR - Pin Control Register 0..Pin Control Register 30 */
+/*! @{ */
+#define PORT_PCR_PS_MASK                         (0x1U)
+#define PORT_PCR_PS_SHIFT                        (0U)
+/*! PS - Pull Select
+ *  0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
+ *  0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
+ */
+#define PORT_PCR_PS(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
+#define PORT_PCR_PE_MASK                         (0x2U)
+#define PORT_PCR_PE_SHIFT                        (1U)
+/*! PE - Pull Enable
+ *  0b0..Internal pull resistor is not enabled on the corresponding pin.
+ *  0b1..Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
+ */
+#define PORT_PCR_PE(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
+#define PORT_PCR_SRE_MASK                        (0x4U)
+#define PORT_PCR_SRE_SHIFT                       (2U)
+/*! SRE - Slew Rate Enable
+ *  0b0..Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
+ *  0b1..Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
+ */
+#define PORT_PCR_SRE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
+#define PORT_PCR_PFE_MASK                        (0x10U)
+#define PORT_PCR_PFE_SHIFT                       (4U)
+/*! PFE - Passive Filter Enable
+ *  0b0..Passive input filter is disabled on the corresponding pin.
+ *  0b1..Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
+ */
+#define PORT_PCR_PFE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
+#define PORT_PCR_ODE_MASK                        (0x20U)
+#define PORT_PCR_ODE_SHIFT                       (5U)
+/*! ODE - Open Drain Enable
+ *  0b0..Open drain output is disabled on the corresponding pin.
+ *  0b1..Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
+ */
+#define PORT_PCR_ODE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
+#define PORT_PCR_DSE_MASK                        (0x40U)
+#define PORT_PCR_DSE_SHIFT                       (6U)
+/*! DSE - Drive Strength Enable
+ *  0b0..Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
+ *  0b1..High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
+ */
+#define PORT_PCR_DSE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
+#define PORT_PCR_MUX_MASK                        (0x700U)
+#define PORT_PCR_MUX_SHIFT                       (8U)
+/*! MUX - Pin Mux Control
+ *  0b000..Pin disabled (Alternative 0) (analog).
+ *  0b001..Alternative 1 (GPIO).
+ *  0b010..Alternative 2 (chip-specific).
+ *  0b011..Alternative 3 (chip-specific).
+ *  0b100..Alternative 4 (chip-specific).
+ *  0b101..Alternative 5 (chip-specific).
+ *  0b110..Alternative 6 (chip-specific).
+ *  0b111..Alternative 7 (chip-specific).
+ */
+#define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK                         (0x8000U)
+#define PORT_PCR_LK_SHIFT                        (15U)
+/*! LK - Lock Register
+ *  0b0..Pin Control Register is not locked.
+ *  0b1..Pin Control Register is locked and cannot be updated until the next system reset.
+ */
+#define PORT_PCR_LK(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
+#define PORT_PCR_IRQC_MASK                       (0xF0000U)
+#define PORT_PCR_IRQC_SHIFT                      (16U)
+/*! IRQC - Interrupt Configuration
+ *  0b0000..Interrupt Status Flag (ISF) is disabled.
+ *  0b0001..ISF flag and DMA request on rising edge.
+ *  0b0010..ISF flag and DMA request on falling edge.
+ *  0b0011..ISF flag and DMA request on either edge.
+ *  0b0100..Reserved.
+ *  0b0101..Flag sets on rising edge.
+ *  0b0110..Flag sets on falling edge.
+ *  0b0111..Flag sets on either edge.
+ *  0b1000..ISF flag and Interrupt when logic 0.
+ *  0b1001..ISF flag and Interrupt on rising-edge.
+ *  0b1010..ISF flag and Interrupt on falling-edge.
+ *  0b1011..ISF flag and Interrupt on either edge.
+ *  0b1100..ISF flag and Interrupt when logic 1.
+ *  0b1101..Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]
+ *  0b1110..Enable active low trigger output, flag is disabled.
+ *  0b1111..Reserved.
+ */
+#define PORT_PCR_IRQC(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK                        (0x1000000U)
+#define PORT_PCR_ISF_SHIFT                       (24U)
+/*! ISF - Interrupt Status Flag
+ *  0b0..Configured interrupt is not detected.
+ *  0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
+ */
+#define PORT_PCR_ISF(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
+/*! @} */
+
+/* The count of PORT_PCR */
+#define PORT_PCR_COUNT                           (32U)
+
+/*! @name GPCLR - Global Pin Control Low Register */
+/*! @{ */
+#define PORT_GPCLR_GPWD_MASK                     (0xFFFFU)
+#define PORT_GPCLR_GPWD_SHIFT                    (0U)
+#define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK                     (0xFFFF0000U)
+#define PORT_GPCLR_GPWE_SHIFT                    (16U)
+#define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
+/*! @} */
+
+/*! @name GPCHR - Global Pin Control High Register */
+/*! @{ */
+#define PORT_GPCHR_GPWD_MASK                     (0xFFFFU)
+#define PORT_GPCHR_GPWD_SHIFT                    (0U)
+#define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK                     (0xFFFF0000U)
+#define PORT_GPCHR_GPWE_SHIFT                    (16U)
+#define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
+/*! @} */
+
+/*! @name GICLR - Global Interrupt Control Low Register */
+/*! @{ */
+#define PORT_GICLR_GIWE_MASK                     (0xFFFFU)
+#define PORT_GICLR_GIWE_SHIFT                    (0U)
+#define PORT_GICLR_GIWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GICLR_GIWE_SHIFT)) & PORT_GICLR_GIWE_MASK)
+#define PORT_GICLR_GIWD_MASK                     (0xFFFF0000U)
+#define PORT_GICLR_GIWD_SHIFT                    (16U)
+#define PORT_GICLR_GIWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GICLR_GIWD_SHIFT)) & PORT_GICLR_GIWD_MASK)
+/*! @} */
+
+/*! @name GICHR - Global Interrupt Control High Register */
+/*! @{ */
+#define PORT_GICHR_GIWE_MASK                     (0xFFFFU)
+#define PORT_GICHR_GIWE_SHIFT                    (0U)
+#define PORT_GICHR_GIWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GICHR_GIWE_SHIFT)) & PORT_GICHR_GIWE_MASK)
+#define PORT_GICHR_GIWD_MASK                     (0xFFFF0000U)
+#define PORT_GICHR_GIWD_SHIFT                    (16U)
+#define PORT_GICHR_GIWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GICHR_GIWD_SHIFT)) & PORT_GICHR_GIWD_MASK)
+/*! @} */
+
+/*! @name ISFR - Interrupt Status Flag Register */
+/*! @{ */
+#define PORT_ISFR_ISF_MASK                       (0xFFFFFFFFU)
+#define PORT_ISFR_ISF_SHIFT                      (0U)
+#define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
+/*! @} */
+
+/*! @name DFER - Digital Filter Enable Register */
+/*! @{ */
+#define PORT_DFER_DFE_MASK                       (0xFFFFFFFFU)
+#define PORT_DFER_DFE_SHIFT                      (0U)
+#define PORT_DFER_DFE(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
+/*! @} */
+
+/*! @name DFCR - Digital Filter Clock Register */
+/*! @{ */
+#define PORT_DFCR_CS_MASK                        (0x1U)
+#define PORT_DFCR_CS_SHIFT                       (0U)
+/*! CS - Clock Source
+ *  0b0..Digital filters are clocked by the bus clock.
+ *  0b1..Digital filters are clocked by the 8 clock.
+ */
+#define PORT_DFCR_CS(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
+/*! @} */
+
+/*! @name DFWR - Digital Filter Width Register */
+/*! @{ */
+#define PORT_DFWR_FILT_MASK                      (0x1FU)
+#define PORT_DFWR_FILT_SHIFT                     (0U)
+#define PORT_DFWR_FILT(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE                               (0x40046000u)
+/** Peripheral PORTA base pointer */
+#define PORTA                                    ((PORT_Type *)PORTA_BASE)
+/** Peripheral PORTB base address */
+#define PORTB_BASE                               (0x40047000u)
+/** Peripheral PORTB base pointer */
+#define PORTB                                    ((PORT_Type *)PORTB_BASE)
+/** Peripheral PORTC base address */
+#define PORTC_BASE                               (0x40048000u)
+/** Peripheral PORTC base pointer */
+#define PORTC                                    ((PORT_Type *)PORTC_BASE)
+/** Peripheral PORTD base address */
+#define PORTD_BASE                               (0x40049000u)
+/** Peripheral PORTD base pointer */
+#define PORTD                                    ((PORT_Type *)PORTD_BASE)
+/** Peripheral PORTE base address */
+#define PORTE_BASE                               (0x41037000u)
+/** Peripheral PORTE base pointer */
+#define PORTE                                    ((PORT_Type *)PORTE_BASE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS                          { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS                           { PORTA, PORTB, PORTC, PORTD, PORTE }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS                                { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ROM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
+ * @{
+ */
+
+/** ROM - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t ENTRY[4];                          /**< Entry, array offset: 0x0, array step: 0x4 */
+  __I  uint32_t TABLEMARK;                         /**< End of Table Marker Register, offset: 0x10 */
+       uint8_t RESERVED_0[4024];
+  __I  uint32_t SYSACCESS;                         /**< System Access Register, offset: 0xFCC */
+  __I  uint32_t PERIPHID4;                         /**< Peripheral ID Register, offset: 0xFD0 */
+  __I  uint32_t PERIPHID5;                         /**< Peripheral ID Register, offset: 0xFD4 */
+  __I  uint32_t PERIPHID6;                         /**< Peripheral ID Register, offset: 0xFD8 */
+  __I  uint32_t PERIPHID7;                         /**< Peripheral ID Register, offset: 0xFDC */
+  __I  uint32_t PERIPHID0;                         /**< Peripheral ID Register, offset: 0xFE0 */
+  __I  uint32_t PERIPHID1;                         /**< Peripheral ID Register, offset: 0xFE4 */
+  __I  uint32_t PERIPHID2;                         /**< Peripheral ID Register, offset: 0xFE8 */
+  __I  uint32_t PERIPHID3;                         /**< Peripheral ID Register, offset: 0xFEC */
+  __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} ROM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ROM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Register_Masks ROM Register Masks
+ * @{
+ */
+
+/*! @name ENTRY - Entry */
+/*! @{ */
+#define ROM_ENTRY_ENTRY_MASK                     (0xFFFFFFFFU)
+#define ROM_ENTRY_ENTRY_SHIFT                    (0U)
+#define ROM_ENTRY_ENTRY(x)                       (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK)
+/*! @} */
+
+/* The count of ROM_ENTRY */
+#define ROM_ENTRY_COUNT                          (4U)
+
+/*! @name TABLEMARK - End of Table Marker Register */
+/*! @{ */
+#define ROM_TABLEMARK_MARK_MASK                  (0xFFFFFFFFU)
+#define ROM_TABLEMARK_MARK_SHIFT                 (0U)
+#define ROM_TABLEMARK_MARK(x)                    (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK)
+/*! @} */
+
+/*! @name SYSACCESS - System Access Register */
+/*! @{ */
+#define ROM_SYSACCESS_SYSACCESS_MASK             (0xFFFFFFFFU)
+#define ROM_SYSACCESS_SYSACCESS_SHIFT            (0U)
+#define ROM_SYSACCESS_SYSACCESS(x)               (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK)
+/*! @} */
+
+/*! @name PERIPHID4 - Peripheral ID Register */
+/*! @{ */
+#define ROM_PERIPHID4_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID4_PERIPHID_SHIFT             (0U)
+#define ROM_PERIPHID4_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID5 - Peripheral ID Register */
+/*! @{ */
+#define ROM_PERIPHID5_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID5_PERIPHID_SHIFT             (0U)
+#define ROM_PERIPHID5_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID6 - Peripheral ID Register */
+/*! @{ */
+#define ROM_PERIPHID6_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID6_PERIPHID_SHIFT             (0U)
+#define ROM_PERIPHID6_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID7 - Peripheral ID Register */
+/*! @{ */
+#define ROM_PERIPHID7_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID7_PERIPHID_SHIFT             (0U)
+#define ROM_PERIPHID7_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID0 - Peripheral ID Register */
+/*! @{ */
+#define ROM_PERIPHID0_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID0_PERIPHID_SHIFT             (0U)
+#define ROM_PERIPHID0_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID1 - Peripheral ID Register */
+/*! @{ */
+#define ROM_PERIPHID1_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID1_PERIPHID_SHIFT             (0U)
+#define ROM_PERIPHID1_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID2 - Peripheral ID Register */
+/*! @{ */
+#define ROM_PERIPHID2_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID2_PERIPHID_SHIFT             (0U)
+#define ROM_PERIPHID2_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK)
+/*! @} */
+
+/*! @name PERIPHID3 - Peripheral ID Register */
+/*! @{ */
+#define ROM_PERIPHID3_PERIPHID_MASK              (0xFFFFFFFFU)
+#define ROM_PERIPHID3_PERIPHID_SHIFT             (0U)
+#define ROM_PERIPHID3_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK)
+/*! @} */
+
+/*! @name COMPID - Component ID Register */
+/*! @{ */
+#define ROM_COMPID_COMPID_MASK                   (0xFFFFFFFFU)
+#define ROM_COMPID_COMPID_SHIFT                  (0U)
+#define ROM_COMPID_COMPID(x)                     (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK)
+/*! @} */
+
+/* The count of ROM_COMPID */
+#define ROM_COMPID_COUNT                         (4U)
+
+
+/*!
+ * @}
+ */ /* end of group ROM_Register_Masks */
+
+
+/* ROM - Peripheral instance base addresses */
+/** Peripheral ROM base address */
+#define ROM_BASE                                 (0xF0002000u)
+/** Peripheral ROM base pointer */
+#define ROM                                      ((ROM_Type *)ROM_BASE)
+/** Array initializer of ROM peripheral base addresses */
+#define ROM_BASE_ADDRS                           { ROM_BASE }
+/** Array initializer of ROM peripheral base pointers */
+#define ROM_BASE_PTRS                            { ROM }
+
+/*!
+ * @}
+ */ /* end of group ROM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RSIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RSIM_Peripheral_Access_Layer RSIM Peripheral Access Layer
+ * @{
+ */
+
+/** RSIM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONTROL;                           /**< Radio System Control, offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  __IO uint32_t MISC;                              /**< Radio Miscellaneous, offset: 0x10 */
+  __IO uint32_t POWER;                             /**< RSIM Power Control, offset: 0x14 */
+  __IO uint32_t SW_CONFIG;                         /**< Radio Software Configuration, offset: 0x18 */
+       uint8_t RESERVED_1[228];
+  __I  uint32_t DSM_TIMER;                         /**< Deep Sleep Timer, offset: 0x100 */
+  __IO uint32_t DSM_CONTROL;                       /**< Deep Sleep Timer Control, offset: 0x104 */
+  __IO uint32_t DSM_WAKEUP;                        /**< Deep Sleep Wakeup Sequence, offset: 0x108 */
+  __I  uint32_t WOR_DURATION;                      /**< WOR Deep Sleep Duration, offset: 0x10C */
+  __IO uint32_t WOR_WAKE;                          /**< WOR Deep Sleep Wake Time, offset: 0x110 */
+       uint8_t RESERVED_2[8];
+  __IO uint32_t MAN_SLEEP;                         /**< MAN Deep Sleep Time, offset: 0x11C */
+  __IO uint32_t MAN_WAKE;                          /**< MAN Deep Sleep Wake Time, offset: 0x120 */
+  __IO uint32_t RF_OSC_CTRL;                       /**< Radio Oscillator Control, offset: 0x124 */
+  __IO uint32_t ANA_TEST;                          /**< Radio Analog Test Registers, offset: 0x128 */
+  __IO uint32_t ANA_TRIM;                          /**< Radio Analog Trim Registers, offset: 0x12C */
+} RSIM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RSIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RSIM_Register_Masks RSIM Register Masks
+ * @{
+ */
+
+/*! @name CONTROL - Radio System Control */
+/*! @{ */
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_EN_MASK    (0x1U)
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_EN_SHIFT   (0U)
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_POWER_REQ_EN_SHIFT)) & RSIM_CONTROL_BLE_RF_POWER_REQ_EN_MASK)
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_STAT_MASK  (0x2U)
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_STAT_SHIFT (1U)
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_STAT(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_POWER_REQ_STAT_SHIFT)) & RSIM_CONTROL_BLE_RF_POWER_REQ_STAT_MASK)
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT_EN_MASK (0x10U)
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT_EN_SHIFT (4U)
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT_EN(x)  (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_POWER_REQ_INT_EN_SHIFT)) & RSIM_CONTROL_BLE_RF_POWER_REQ_INT_EN_MASK)
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT_MASK   (0x20U)
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT_SHIFT  (5U)
+#define RSIM_CONTROL_BLE_RF_POWER_REQ_INT(x)     (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_POWER_REQ_INT_SHIFT)) & RSIM_CONTROL_BLE_RF_POWER_REQ_INT_MASK)
+#define RSIM_CONTROL_RF_OSC_EN_MASK              (0x100U)
+#define RSIM_CONTROL_RF_OSC_EN_SHIFT             (8U)
+#define RSIM_CONTROL_RF_OSC_EN(x)                (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_EN_SHIFT)) & RSIM_CONTROL_RF_OSC_EN_MASK)
+#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_MASK (0x1000U)
+#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_SHIFT (12U)
+#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_SHIFT)) & RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_MASK)
+#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_MASK (0x2000U)
+#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_SHIFT (13U)
+/*! RADIO_GASKET_BYPASS_OVRD - Radio Gasket Bypass Override
+ *  0b0..XCVR and Link Layer Register Clock is the RF Ref Osc Clock
+ *  0b1..XCVR and Link Layer Register Clock is the SoC IPG Clock
+ */
+#define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_SHIFT)) & RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_MASK)
+#define RSIM_CONTROL_IPP_OBE_BLE_EARLY_WARNING_MASK (0x4000U)
+#define RSIM_CONTROL_IPP_OBE_BLE_EARLY_WARNING_SHIFT (14U)
+#define RSIM_CONTROL_IPP_OBE_BLE_EARLY_WARNING(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_BLE_EARLY_WARNING_SHIFT)) & RSIM_CONTROL_IPP_OBE_BLE_EARLY_WARNING_MASK)
+#define RSIM_CONTROL_IPP_OBE_RF_ACTIVE_MASK      (0x8000U)
+#define RSIM_CONTROL_IPP_OBE_RF_ACTIVE_SHIFT     (15U)
+#define RSIM_CONTROL_IPP_OBE_RF_ACTIVE(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_RF_ACTIVE_SHIFT)) & RSIM_CONTROL_IPP_OBE_RF_ACTIVE_MASK)
+#define RSIM_CONTROL_IPP_OBE_RF_OSC_EN_MASK      (0x10000U)
+#define RSIM_CONTROL_IPP_OBE_RF_OSC_EN_SHIFT     (16U)
+#define RSIM_CONTROL_IPP_OBE_RF_OSC_EN(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_RF_OSC_EN_SHIFT)) & RSIM_CONTROL_IPP_OBE_RF_OSC_EN_MASK)
+#define RSIM_CONTROL_IPP_OBE_RF_STATUS_MASK      (0x40000U)
+#define RSIM_CONTROL_IPP_OBE_RF_STATUS_SHIFT     (18U)
+#define RSIM_CONTROL_IPP_OBE_RF_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_RF_STATUS_SHIFT)) & RSIM_CONTROL_IPP_OBE_RF_STATUS_MASK)
+#define RSIM_CONTROL_IPP_OBE_RF_PRIORITY_MASK    (0x80000U)
+#define RSIM_CONTROL_IPP_OBE_RF_PRIORITY_SHIFT   (19U)
+#define RSIM_CONTROL_IPP_OBE_RF_PRIORITY(x)      (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_RF_PRIORITY_SHIFT)) & RSIM_CONTROL_IPP_OBE_RF_PRIORITY_MASK)
+#define RSIM_CONTROL_BLE_DSM_EXIT_MASK           (0x100000U)
+#define RSIM_CONTROL_BLE_DSM_EXIT_SHIFT          (20U)
+#define RSIM_CONTROL_BLE_DSM_EXIT(x)             (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_DSM_EXIT_SHIFT)) & RSIM_CONTROL_BLE_DSM_EXIT_MASK)
+#define RSIM_CONTROL_WOR_DSM_EXIT_MASK           (0x200000U)
+#define RSIM_CONTROL_WOR_DSM_EXIT_SHIFT          (21U)
+#define RSIM_CONTROL_WOR_DSM_EXIT(x)             (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_WOR_DSM_EXIT_SHIFT)) & RSIM_CONTROL_WOR_DSM_EXIT_MASK)
+#define RSIM_CONTROL_RF_OSC_READY_MASK           (0x1000000U)
+#define RSIM_CONTROL_RF_OSC_READY_SHIFT          (24U)
+#define RSIM_CONTROL_RF_OSC_READY(x)             (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_READY_SHIFT)) & RSIM_CONTROL_RF_OSC_READY_MASK)
+#define RSIM_CONTROL_RF_OSC_READY_OVRD_EN_MASK   (0x2000000U)
+#define RSIM_CONTROL_RF_OSC_READY_OVRD_EN_SHIFT  (25U)
+#define RSIM_CONTROL_RF_OSC_READY_OVRD_EN(x)     (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_READY_OVRD_EN_SHIFT)) & RSIM_CONTROL_RF_OSC_READY_OVRD_EN_MASK)
+#define RSIM_CONTROL_RF_OSC_READY_OVRD_MASK      (0x4000000U)
+#define RSIM_CONTROL_RF_OSC_READY_OVRD_SHIFT     (26U)
+#define RSIM_CONTROL_RF_OSC_READY_OVRD(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_READY_OVRD_SHIFT)) & RSIM_CONTROL_RF_OSC_READY_OVRD_MASK)
+#define RSIM_CONTROL_RSIM_CGC_BLE_EN_MASK        (0x8000000U)
+#define RSIM_CONTROL_RSIM_CGC_BLE_EN_SHIFT       (27U)
+/*! RSIM_CGC_BLE_EN - BLE Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define RSIM_CONTROL_RSIM_CGC_BLE_EN(x)          (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_CGC_BLE_EN_SHIFT)) & RSIM_CONTROL_RSIM_CGC_BLE_EN_MASK)
+#define RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK       (0x10000000U)
+#define RSIM_CONTROL_RSIM_CGC_XCVR_EN_SHIFT      (28U)
+/*! RSIM_CGC_XCVR_EN - XCVR Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define RSIM_CONTROL_RSIM_CGC_XCVR_EN(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_CGC_XCVR_EN_SHIFT)) & RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK)
+#define RSIM_CONTROL_RSIM_CGC_ZIG_EN_MASK        (0x20000000U)
+#define RSIM_CONTROL_RSIM_CGC_ZIG_EN_SHIFT       (29U)
+/*! RSIM_CGC_ZIG_EN - ZIG Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define RSIM_CONTROL_RSIM_CGC_ZIG_EN(x)          (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_CGC_ZIG_EN_SHIFT)) & RSIM_CONTROL_RSIM_CGC_ZIG_EN_MASK)
+#define RSIM_CONTROL_RSIM_CGC_GEN_EN_MASK        (0x80000000U)
+#define RSIM_CONTROL_RSIM_CGC_GEN_EN_SHIFT       (31U)
+/*! RSIM_CGC_GEN_EN - GEN Clock Gate Control
+ *  0b0..Clock disabled
+ *  0b1..Clock enabled
+ */
+#define RSIM_CONTROL_RSIM_CGC_GEN_EN(x)          (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_CGC_GEN_EN_SHIFT)) & RSIM_CONTROL_RSIM_CGC_GEN_EN_MASK)
+/*! @} */
+
+/*! @name MISC - Radio Miscellaneous */
+/*! @{ */
+#define RSIM_MISC_RADIO_VERSION_MASK             (0xFF000000U)
+#define RSIM_MISC_RADIO_VERSION_SHIFT            (24U)
+#define RSIM_MISC_RADIO_VERSION(x)               (((uint32_t)(((uint32_t)(x)) << RSIM_MISC_RADIO_VERSION_SHIFT)) & RSIM_MISC_RADIO_VERSION_MASK)
+/*! @} */
+
+/*! @name POWER - RSIM Power Control */
+/*! @{ */
+#define RSIM_POWER_RADIO_STOP_MODE_STAT_MASK     (0x7U)
+#define RSIM_POWER_RADIO_STOP_MODE_STAT_SHIFT    (0U)
+#define RSIM_POWER_RADIO_STOP_MODE_STAT(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_STOP_MODE_STAT_SHIFT)) & RSIM_POWER_RADIO_STOP_MODE_STAT_MASK)
+#define RSIM_POWER_SPM_STOP_ACK_STAT_MASK        (0x8U)
+#define RSIM_POWER_SPM_STOP_ACK_STAT_SHIFT       (3U)
+#define RSIM_POWER_SPM_STOP_ACK_STAT(x)          (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_STOP_ACK_STAT_SHIFT)) & RSIM_POWER_SPM_STOP_ACK_STAT_MASK)
+#define RSIM_POWER_RADIO_STOP_MODE_OVRD_MASK     (0x70U)
+#define RSIM_POWER_RADIO_STOP_MODE_OVRD_SHIFT    (4U)
+#define RSIM_POWER_RADIO_STOP_MODE_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_STOP_MODE_OVRD_SHIFT)) & RSIM_POWER_RADIO_STOP_MODE_OVRD_MASK)
+#define RSIM_POWER_RADIO_STOP_MODE_OVRD_EN_MASK  (0x80U)
+#define RSIM_POWER_RADIO_STOP_MODE_OVRD_EN_SHIFT (7U)
+#define RSIM_POWER_RADIO_STOP_MODE_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_STOP_MODE_OVRD_EN_SHIFT)) & RSIM_POWER_RADIO_STOP_MODE_OVRD_EN_MASK)
+#define RSIM_POWER_RADIO_STOP_ACK_STAT_MASK      (0x100U)
+#define RSIM_POWER_RADIO_STOP_ACK_STAT_SHIFT     (8U)
+#define RSIM_POWER_RADIO_STOP_ACK_STAT(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_STOP_ACK_STAT_SHIFT)) & RSIM_POWER_RADIO_STOP_ACK_STAT_MASK)
+#define RSIM_POWER_RADIO_STOP_REQ_STAT_MASK      (0x200U)
+#define RSIM_POWER_RADIO_STOP_REQ_STAT_SHIFT     (9U)
+#define RSIM_POWER_RADIO_STOP_REQ_STAT(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_STOP_REQ_STAT_SHIFT)) & RSIM_POWER_RADIO_STOP_REQ_STAT_MASK)
+#define RSIM_POWER_RSIM_STOP_REQ_OVRD_MASK       (0x400U)
+#define RSIM_POWER_RSIM_STOP_REQ_OVRD_SHIFT      (10U)
+#define RSIM_POWER_RSIM_STOP_REQ_OVRD(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_STOP_REQ_OVRD_SHIFT)) & RSIM_POWER_RSIM_STOP_REQ_OVRD_MASK)
+#define RSIM_POWER_RSIM_STOP_REQ_OVRD_EN_MASK    (0x800U)
+#define RSIM_POWER_RSIM_STOP_REQ_OVRD_EN_SHIFT   (11U)
+#define RSIM_POWER_RSIM_STOP_REQ_OVRD_EN(x)      (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_STOP_REQ_OVRD_EN_SHIFT)) & RSIM_POWER_RSIM_STOP_REQ_OVRD_EN_MASK)
+#define RSIM_POWER_RF_OSC_EN_OVRD_MASK           (0x1000U)
+#define RSIM_POWER_RF_OSC_EN_OVRD_SHIFT          (12U)
+#define RSIM_POWER_RF_OSC_EN_OVRD(x)             (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RF_OSC_EN_OVRD_SHIFT)) & RSIM_POWER_RF_OSC_EN_OVRD_MASK)
+#define RSIM_POWER_RF_OSC_EN_OVRD_EN_MASK        (0x2000U)
+#define RSIM_POWER_RF_OSC_EN_OVRD_EN_SHIFT       (13U)
+#define RSIM_POWER_RF_OSC_EN_OVRD_EN(x)          (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RF_OSC_EN_OVRD_EN_SHIFT)) & RSIM_POWER_RF_OSC_EN_OVRD_EN_MASK)
+#define RSIM_POWER_RF_POWER_EN_OVRD_MASK         (0x4000U)
+#define RSIM_POWER_RF_POWER_EN_OVRD_SHIFT        (14U)
+#define RSIM_POWER_RF_POWER_EN_OVRD(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RF_POWER_EN_OVRD_SHIFT)) & RSIM_POWER_RF_POWER_EN_OVRD_MASK)
+#define RSIM_POWER_RF_POWER_EN_OVRD_EN_MASK      (0x8000U)
+#define RSIM_POWER_RF_POWER_EN_OVRD_EN_SHIFT     (15U)
+#define RSIM_POWER_RF_POWER_EN_OVRD_EN(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RF_POWER_EN_OVRD_EN_SHIFT)) & RSIM_POWER_RF_POWER_EN_OVRD_EN_MASK)
+#define RSIM_POWER_SPM_ISO_STAT_MASK             (0x10000U)
+#define RSIM_POWER_SPM_ISO_STAT_SHIFT            (16U)
+#define RSIM_POWER_SPM_ISO_STAT(x)               (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_ISO_STAT_SHIFT)) & RSIM_POWER_SPM_ISO_STAT_MASK)
+#define RSIM_POWER_RADIO_ISO_STAT_MASK           (0x20000U)
+#define RSIM_POWER_RADIO_ISO_STAT_SHIFT          (17U)
+#define RSIM_POWER_RADIO_ISO_STAT(x)             (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_ISO_STAT_SHIFT)) & RSIM_POWER_RADIO_ISO_STAT_MASK)
+#define RSIM_POWER_RSIM_ISO_OVRD_MASK            (0x40000U)
+#define RSIM_POWER_RSIM_ISO_OVRD_SHIFT           (18U)
+#define RSIM_POWER_RSIM_ISO_OVRD(x)              (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_ISO_OVRD_SHIFT)) & RSIM_POWER_RSIM_ISO_OVRD_MASK)
+#define RSIM_POWER_RSIM_ISO_OVRD_EN_MASK         (0x80000U)
+#define RSIM_POWER_RSIM_ISO_OVRD_EN_SHIFT        (19U)
+#define RSIM_POWER_RSIM_ISO_OVRD_EN(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_ISO_OVRD_EN_SHIFT)) & RSIM_POWER_RSIM_ISO_OVRD_EN_MASK)
+#define RSIM_POWER_SPM_RUN_ACK_STAT_MASK         (0x100000U)
+#define RSIM_POWER_SPM_RUN_ACK_STAT_SHIFT        (20U)
+#define RSIM_POWER_SPM_RUN_ACK_STAT(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_RUN_ACK_STAT_SHIFT)) & RSIM_POWER_SPM_RUN_ACK_STAT_MASK)
+#define RSIM_POWER_RADIO_RUN_REQ_STAT_MASK       (0x200000U)
+#define RSIM_POWER_RADIO_RUN_REQ_STAT_SHIFT      (21U)
+#define RSIM_POWER_RADIO_RUN_REQ_STAT(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RADIO_RUN_REQ_STAT_SHIFT)) & RSIM_POWER_RADIO_RUN_REQ_STAT_MASK)
+#define RSIM_POWER_RSIM_RUN_REQ_OVRD_MASK        (0x400000U)
+#define RSIM_POWER_RSIM_RUN_REQ_OVRD_SHIFT       (22U)
+#define RSIM_POWER_RSIM_RUN_REQ_OVRD(x)          (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_RUN_REQ_OVRD_SHIFT)) & RSIM_POWER_RSIM_RUN_REQ_OVRD_MASK)
+#define RSIM_POWER_RSIM_RUN_REQ_OVRD_EN_MASK     (0x800000U)
+#define RSIM_POWER_RSIM_RUN_REQ_OVRD_EN_SHIFT    (23U)
+#define RSIM_POWER_RSIM_RUN_REQ_OVRD_EN(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_RUN_REQ_OVRD_EN_SHIFT)) & RSIM_POWER_RSIM_RUN_REQ_OVRD_EN_MASK)
+#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_MASK    (0x1000000U)
+#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_SHIFT   (24U)
+#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD(x)      (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_SHIFT)) & RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_MASK)
+#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_EN_MASK (0x2000000U)
+#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_EN_SHIFT (25U)
+#define RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_EN(x)   (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_EN_SHIFT)) & RSIM_POWER_SPM_STOP_REQ_ACK_OVRD_EN_MASK)
+#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_MASK     (0x4000000U)
+#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_SHIFT    (26U)
+#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_SHIFT)) & RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_MASK)
+#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_EN_MASK  (0x8000000U)
+#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_EN_SHIFT (27U)
+#define RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_EN_SHIFT)) & RSIM_POWER_SPM_RUN_REQ_ACK_OVRD_EN_MASK)
+#define RSIM_POWER_RSIM_STOP_MODE_MASK           (0x70000000U)
+#define RSIM_POWER_RSIM_STOP_MODE_SHIFT          (28U)
+/*! RSIM_STOP_MODE - RSIM lowest allowed Stop Mode
+ *  0b000..Reserved
+ *  0b001..Reserved
+ *  0b011..RLLS mode (Radio State Retention mode)
+ *  0b111..RVLLS mode (This is the POR setting)
+ */
+#define RSIM_POWER_RSIM_STOP_MODE(x)             (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_STOP_MODE_SHIFT)) & RSIM_POWER_RSIM_STOP_MODE_MASK)
+#define RSIM_POWER_RSIM_RUN_REQUEST_MASK         (0x80000000U)
+#define RSIM_POWER_RSIM_RUN_REQUEST_SHIFT        (31U)
+#define RSIM_POWER_RSIM_RUN_REQUEST(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_POWER_RSIM_RUN_REQUEST_SHIFT)) & RSIM_POWER_RSIM_RUN_REQUEST_MASK)
+/*! @} */
+
+/*! @name SW_CONFIG - Radio Software Configuration */
+/*! @{ */
+#define RSIM_SW_CONFIG_RADIO_CONFIGURED_POR_RESET_MASK (0x1U)
+#define RSIM_SW_CONFIG_RADIO_CONFIGURED_POR_RESET_SHIFT (0U)
+#define RSIM_SW_CONFIG_RADIO_CONFIGURED_POR_RESET(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO_CONFIGURED_POR_RESET_SHIFT)) & RSIM_SW_CONFIG_RADIO_CONFIGURED_POR_RESET_MASK)
+#define RSIM_SW_CONFIG_RADIO_CONFIGURED_SYS_RESET_MASK (0x2U)
+#define RSIM_SW_CONFIG_RADIO_CONFIGURED_SYS_RESET_SHIFT (1U)
+#define RSIM_SW_CONFIG_RADIO_CONFIGURED_SYS_RESET(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO_CONFIGURED_SYS_RESET_SHIFT)) & RSIM_SW_CONFIG_RADIO_CONFIGURED_SYS_RESET_MASK)
+#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_MASK  (0x10U)
+#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_SHIFT (4U)
+#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_SHIFT)) & RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_MASK)
+#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_EN_MASK (0x20U)
+#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_EN_SHIFT (5U)
+#define RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_EN_SHIFT)) & RSIM_SW_CONFIG_RSIM_RF_ACTIVE_OVRD_EN_MASK)
+#define RSIM_SW_CONFIG_RADIO_POR_BIT_MASK        (0x100U)
+#define RSIM_SW_CONFIG_RADIO_POR_BIT_SHIFT       (8U)
+#define RSIM_SW_CONFIG_RADIO_POR_BIT(x)          (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO_POR_BIT_SHIFT)) & RSIM_SW_CONFIG_RADIO_POR_BIT_MASK)
+#define RSIM_SW_CONFIG_RSIM_RADIO_ISO_POR_OVRD_MASK (0x1000U)
+#define RSIM_SW_CONFIG_RSIM_RADIO_ISO_POR_OVRD_SHIFT (12U)
+#define RSIM_SW_CONFIG_RSIM_RADIO_ISO_POR_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RSIM_RADIO_ISO_POR_OVRD_SHIFT)) & RSIM_SW_CONFIG_RSIM_RADIO_ISO_POR_OVRD_MASK)
+#define RSIM_SW_CONFIG_RADIO_RESET_BIT_MASK      (0x10000U)
+#define RSIM_SW_CONFIG_RADIO_RESET_BIT_SHIFT     (16U)
+#define RSIM_SW_CONFIG_RADIO_RESET_BIT(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO_RESET_BIT_SHIFT)) & RSIM_SW_CONFIG_RADIO_RESET_BIT_MASK)
+#define RSIM_SW_CONFIG_WAKEUP_INTERRUPT_SOURCE_MASK (0x300000U)
+#define RSIM_SW_CONFIG_WAKEUP_INTERRUPT_SOURCE_SHIFT (20U)
+/*! WAKEUP_INTERRUPT_SOURCE - RSIM Wakeup Interrupt Source Selector
+ *  0b00..No Radio Power-On Sequence interrupt will be generated.
+ *  0b01..A Power-On Sequence interrupt will be generated when the RF Power Request occurs, including unblocked requests from an external source to use the RF OSC.
+ *  0b10..A Power-On Sequence interrupt will be generated when the RF OSC Request occurs, but not if the RF OSC request was from an external source.
+ *  0b11..A Power-On Sequence interrupt will be generated when the RSIM RF Active Warning occurs
+ */
+#define RSIM_SW_CONFIG_WAKEUP_INTERRUPT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_WAKEUP_INTERRUPT_SOURCE_SHIFT)) & RSIM_SW_CONFIG_WAKEUP_INTERRUPT_SOURCE_MASK)
+#define RSIM_SW_CONFIG_RADIO0_INTERRUPT_EN_MASK  (0x1000000U)
+#define RSIM_SW_CONFIG_RADIO0_INTERRUPT_EN_SHIFT (24U)
+#define RSIM_SW_CONFIG_RADIO0_INTERRUPT_EN(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO0_INTERRUPT_EN_SHIFT)) & RSIM_SW_CONFIG_RADIO0_INTERRUPT_EN_MASK)
+#define RSIM_SW_CONFIG_RADIO1_INTERRUPT_EN_MASK  (0x2000000U)
+#define RSIM_SW_CONFIG_RADIO1_INTERRUPT_EN_SHIFT (25U)
+#define RSIM_SW_CONFIG_RADIO1_INTERRUPT_EN(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_RADIO1_INTERRUPT_EN_SHIFT)) & RSIM_SW_CONFIG_RADIO1_INTERRUPT_EN_MASK)
+#define RSIM_SW_CONFIG_BLOCK_SOC_RESETS_MASK     (0x10000000U)
+#define RSIM_SW_CONFIG_BLOCK_SOC_RESETS_SHIFT    (28U)
+#define RSIM_SW_CONFIG_BLOCK_SOC_RESETS(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_BLOCK_SOC_RESETS_SHIFT)) & RSIM_SW_CONFIG_BLOCK_SOC_RESETS_MASK)
+#define RSIM_SW_CONFIG_BLOCK_RADIO_OUTPUTS_MASK  (0x20000000U)
+#define RSIM_SW_CONFIG_BLOCK_RADIO_OUTPUTS_SHIFT (29U)
+#define RSIM_SW_CONFIG_BLOCK_RADIO_OUTPUTS(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_BLOCK_RADIO_OUTPUTS_SHIFT)) & RSIM_SW_CONFIG_BLOCK_RADIO_OUTPUTS_MASK)
+#define RSIM_SW_CONFIG_ALLOW_DFT_RESETS_MASK     (0x40000000U)
+#define RSIM_SW_CONFIG_ALLOW_DFT_RESETS_SHIFT    (30U)
+#define RSIM_SW_CONFIG_ALLOW_DFT_RESETS(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_ALLOW_DFT_RESETS_SHIFT)) & RSIM_SW_CONFIG_ALLOW_DFT_RESETS_MASK)
+#define RSIM_SW_CONFIG_BLOCK_EXT_OSC_PWR_REQ_MASK (0x80000000U)
+#define RSIM_SW_CONFIG_BLOCK_EXT_OSC_PWR_REQ_SHIFT (31U)
+#define RSIM_SW_CONFIG_BLOCK_EXT_OSC_PWR_REQ(x)  (((uint32_t)(((uint32_t)(x)) << RSIM_SW_CONFIG_BLOCK_EXT_OSC_PWR_REQ_SHIFT)) & RSIM_SW_CONFIG_BLOCK_EXT_OSC_PWR_REQ_MASK)
+/*! @} */
+
+/*! @name DSM_TIMER - Deep Sleep Timer */
+/*! @{ */
+#define RSIM_DSM_TIMER_DSM_TIMER_MASK            (0xFFFFFFU)
+#define RSIM_DSM_TIMER_DSM_TIMER_SHIFT           (0U)
+#define RSIM_DSM_TIMER_DSM_TIMER(x)              (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_TIMER_DSM_TIMER_SHIFT)) & RSIM_DSM_TIMER_DSM_TIMER_MASK)
+/*! @} */
+
+/*! @name DSM_CONTROL - Deep Sleep Timer Control */
+/*! @{ */
+#define RSIM_DSM_CONTROL_DSM_WOR_READY_MASK      (0x1U)
+#define RSIM_DSM_CONTROL_DSM_WOR_READY_SHIFT     (0U)
+#define RSIM_DSM_CONTROL_DSM_WOR_READY(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_WOR_READY_SHIFT)) & RSIM_DSM_CONTROL_DSM_WOR_READY_MASK)
+#define RSIM_DSM_CONTROL_WOR_DEEP_SLEEP_STATUS_MASK (0x2U)
+#define RSIM_DSM_CONTROL_WOR_DEEP_SLEEP_STATUS_SHIFT (1U)
+#define RSIM_DSM_CONTROL_WOR_DEEP_SLEEP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_DEEP_SLEEP_STATUS_SHIFT)) & RSIM_DSM_CONTROL_WOR_DEEP_SLEEP_STATUS_MASK)
+#define RSIM_DSM_CONTROL_DSM_WOR_FINISHED_MASK   (0x4U)
+#define RSIM_DSM_CONTROL_DSM_WOR_FINISHED_SHIFT  (2U)
+#define RSIM_DSM_CONTROL_DSM_WOR_FINISHED(x)     (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_WOR_FINISHED_SHIFT)) & RSIM_DSM_CONTROL_DSM_WOR_FINISHED_MASK)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQUEST_EN_MASK (0x8U)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQUEST_EN_SHIFT (3U)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQUEST_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_WAKEUP_REQUEST_EN_SHIFT)) & RSIM_DSM_CONTROL_WOR_WAKEUP_REQUEST_EN_MASK)
+#define RSIM_DSM_CONTROL_WOR_SLEEP_REQUEST_MASK  (0x10U)
+#define RSIM_DSM_CONTROL_WOR_SLEEP_REQUEST_SHIFT (4U)
+#define RSIM_DSM_CONTROL_WOR_SLEEP_REQUEST(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_SLEEP_REQUEST_SHIFT)) & RSIM_DSM_CONTROL_WOR_SLEEP_REQUEST_MASK)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_MASK     (0x20U)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_SHIFT    (5U)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_SHIFT)) & RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_MASK)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_INTERRUPT_EN_MASK (0x40U)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_INTERRUPT_EN_SHIFT (6U)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_INTERRUPT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_WAKEUP_INTERRUPT_EN_SHIFT)) & RSIM_DSM_CONTROL_WOR_WAKEUP_INTERRUPT_EN_MASK)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_INT_MASK (0x80U)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_INT_SHIFT (7U)
+#define RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_INT(x)   (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_INT_SHIFT)) & RSIM_DSM_CONTROL_WOR_WAKEUP_REQ_INT_MASK)
+#define RSIM_DSM_CONTROL_DSM_MAN_READY_MASK      (0x100U)
+#define RSIM_DSM_CONTROL_DSM_MAN_READY_SHIFT     (8U)
+#define RSIM_DSM_CONTROL_DSM_MAN_READY(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_MAN_READY_SHIFT)) & RSIM_DSM_CONTROL_DSM_MAN_READY_MASK)
+#define RSIM_DSM_CONTROL_MAN_DEEP_SLEEP_STATUS_MASK (0x200U)
+#define RSIM_DSM_CONTROL_MAN_DEEP_SLEEP_STATUS_SHIFT (9U)
+#define RSIM_DSM_CONTROL_MAN_DEEP_SLEEP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_DEEP_SLEEP_STATUS_SHIFT)) & RSIM_DSM_CONTROL_MAN_DEEP_SLEEP_STATUS_MASK)
+#define RSIM_DSM_CONTROL_DSM_MAN_FINISHED_MASK   (0x400U)
+#define RSIM_DSM_CONTROL_DSM_MAN_FINISHED_SHIFT  (10U)
+#define RSIM_DSM_CONTROL_DSM_MAN_FINISHED(x)     (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_MAN_FINISHED_SHIFT)) & RSIM_DSM_CONTROL_DSM_MAN_FINISHED_MASK)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQUEST_EN_MASK (0x800U)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQUEST_EN_SHIFT (11U)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQUEST_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_WAKEUP_REQUEST_EN_SHIFT)) & RSIM_DSM_CONTROL_MAN_WAKEUP_REQUEST_EN_MASK)
+#define RSIM_DSM_CONTROL_MAN_SLEEP_REQUEST_MASK  (0x1000U)
+#define RSIM_DSM_CONTROL_MAN_SLEEP_REQUEST_SHIFT (12U)
+#define RSIM_DSM_CONTROL_MAN_SLEEP_REQUEST(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_SLEEP_REQUEST_SHIFT)) & RSIM_DSM_CONTROL_MAN_SLEEP_REQUEST_MASK)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_MASK     (0x2000U)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_SHIFT    (13U)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_SHIFT)) & RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_MASK)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_INTERRUPT_EN_MASK (0x4000U)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_INTERRUPT_EN_SHIFT (14U)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_INTERRUPT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_WAKEUP_INTERRUPT_EN_SHIFT)) & RSIM_DSM_CONTROL_MAN_WAKEUP_INTERRUPT_EN_MASK)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_INT_MASK (0x8000U)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_INT_SHIFT (15U)
+#define RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_INT(x)   (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_INT_SHIFT)) & RSIM_DSM_CONTROL_MAN_WAKEUP_REQ_INT_MASK)
+#define RSIM_DSM_CONTROL_WIFI_COEXIST_1_MASK     (0x10000U)
+#define RSIM_DSM_CONTROL_WIFI_COEXIST_1_SHIFT    (16U)
+#define RSIM_DSM_CONTROL_WIFI_COEXIST_1(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WIFI_COEXIST_1_SHIFT)) & RSIM_DSM_CONTROL_WIFI_COEXIST_1_MASK)
+#define RSIM_DSM_CONTROL_WIFI_COEXIST_2_MASK     (0x20000U)
+#define RSIM_DSM_CONTROL_WIFI_COEXIST_2_SHIFT    (17U)
+#define RSIM_DSM_CONTROL_WIFI_COEXIST_2(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WIFI_COEXIST_2_SHIFT)) & RSIM_DSM_CONTROL_WIFI_COEXIST_2_MASK)
+#define RSIM_DSM_CONTROL_WIFI_COEXIST_3_MASK     (0x40000U)
+#define RSIM_DSM_CONTROL_WIFI_COEXIST_3_SHIFT    (18U)
+#define RSIM_DSM_CONTROL_WIFI_COEXIST_3(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_WIFI_COEXIST_3_SHIFT)) & RSIM_DSM_CONTROL_WIFI_COEXIST_3_MASK)
+#define RSIM_DSM_CONTROL_RF_ACTIVE_ENDS_WITH_TSM_MASK (0x100000U)
+#define RSIM_DSM_CONTROL_RF_ACTIVE_ENDS_WITH_TSM_SHIFT (20U)
+#define RSIM_DSM_CONTROL_RF_ACTIVE_ENDS_WITH_TSM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_RF_ACTIVE_ENDS_WITH_TSM_SHIFT)) & RSIM_DSM_CONTROL_RF_ACTIVE_ENDS_WITH_TSM_MASK)
+#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_ENDS_WITH_TSM_MASK (0x200000U)
+#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_ENDS_WITH_TSM_SHIFT (21U)
+#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_ENDS_WITH_TSM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_SW_RF_ACTIVE_ENDS_WITH_TSM_SHIFT)) & RSIM_DSM_CONTROL_SW_RF_ACTIVE_ENDS_WITH_TSM_MASK)
+#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_BIT_MASK   (0x400000U)
+#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_BIT_SHIFT  (22U)
+#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_BIT(x)     (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_SW_RF_ACTIVE_BIT_SHIFT)) & RSIM_DSM_CONTROL_SW_RF_ACTIVE_BIT_MASK)
+#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_EN_MASK    (0x800000U)
+#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_EN_SHIFT   (23U)
+#define RSIM_DSM_CONTROL_SW_RF_ACTIVE_EN(x)      (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_SW_RF_ACTIVE_EN_SHIFT)) & RSIM_DSM_CONTROL_SW_RF_ACTIVE_EN_MASK)
+#define RSIM_DSM_CONTROL_DSM_TIMER_CLR_MASK      (0x8000000U)
+#define RSIM_DSM_CONTROL_DSM_TIMER_CLR_SHIFT     (27U)
+#define RSIM_DSM_CONTROL_DSM_TIMER_CLR(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_TIMER_CLR_SHIFT)) & RSIM_DSM_CONTROL_DSM_TIMER_CLR_MASK)
+#define RSIM_DSM_CONTROL_DSM_TIMER_EN_MASK       (0x80000000U)
+#define RSIM_DSM_CONTROL_DSM_TIMER_EN_SHIFT      (31U)
+#define RSIM_DSM_CONTROL_DSM_TIMER_EN(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_TIMER_EN_SHIFT)) & RSIM_DSM_CONTROL_DSM_TIMER_EN_MASK)
+/*! @} */
+
+/*! @name DSM_WAKEUP - Deep Sleep Wakeup Sequence */
+/*! @{ */
+#define RSIM_DSM_WAKEUP_DSM_POWER_OFFSET_TIME_MASK (0x3FFU)
+#define RSIM_DSM_WAKEUP_DSM_POWER_OFFSET_TIME_SHIFT (0U)
+#define RSIM_DSM_WAKEUP_DSM_POWER_OFFSET_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_WAKEUP_DSM_POWER_OFFSET_TIME_SHIFT)) & RSIM_DSM_WAKEUP_DSM_POWER_OFFSET_TIME_MASK)
+#define RSIM_DSM_WAKEUP_ACTIVE_WARNING_MASK      (0x3F000U)
+#define RSIM_DSM_WAKEUP_ACTIVE_WARNING_SHIFT     (12U)
+#define RSIM_DSM_WAKEUP_ACTIVE_WARNING(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_WAKEUP_ACTIVE_WARNING_SHIFT)) & RSIM_DSM_WAKEUP_ACTIVE_WARNING_MASK)
+#define RSIM_DSM_WAKEUP_FINE_DELAY_MASK          (0x3F00000U)
+#define RSIM_DSM_WAKEUP_FINE_DELAY_SHIFT         (20U)
+#define RSIM_DSM_WAKEUP_FINE_DELAY(x)            (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_WAKEUP_FINE_DELAY_SHIFT)) & RSIM_DSM_WAKEUP_FINE_DELAY_MASK)
+#define RSIM_DSM_WAKEUP_COARSE_DELAY_MASK        (0xF0000000U)
+#define RSIM_DSM_WAKEUP_COARSE_DELAY_SHIFT       (28U)
+#define RSIM_DSM_WAKEUP_COARSE_DELAY(x)          (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_WAKEUP_COARSE_DELAY_SHIFT)) & RSIM_DSM_WAKEUP_COARSE_DELAY_MASK)
+/*! @} */
+
+/*! @name WOR_DURATION - WOR Deep Sleep Duration */
+/*! @{ */
+#define RSIM_WOR_DURATION_WOR_DSM_DURATION_MASK  (0xFFFFFFU)
+#define RSIM_WOR_DURATION_WOR_DSM_DURATION_SHIFT (0U)
+#define RSIM_WOR_DURATION_WOR_DSM_DURATION(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_WOR_DURATION_WOR_DSM_DURATION_SHIFT)) & RSIM_WOR_DURATION_WOR_DSM_DURATION_MASK)
+/*! @} */
+
+/*! @name WOR_WAKE - WOR Deep Sleep Wake Time */
+/*! @{ */
+#define RSIM_WOR_WAKE_WOR_WAKE_TIME_MASK         (0xFFFFFFU)
+#define RSIM_WOR_WAKE_WOR_WAKE_TIME_SHIFT        (0U)
+#define RSIM_WOR_WAKE_WOR_WAKE_TIME(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_WOR_WAKE_WOR_WAKE_TIME_SHIFT)) & RSIM_WOR_WAKE_WOR_WAKE_TIME_MASK)
+#define RSIM_WOR_WAKE_WOR_FSM_STATE_MASK         (0x70000000U)
+#define RSIM_WOR_WAKE_WOR_FSM_STATE_SHIFT        (28U)
+#define RSIM_WOR_WAKE_WOR_FSM_STATE(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_WOR_WAKE_WOR_FSM_STATE_SHIFT)) & RSIM_WOR_WAKE_WOR_FSM_STATE_MASK)
+/*! @} */
+
+/*! @name MAN_SLEEP - MAN Deep Sleep Time */
+/*! @{ */
+#define RSIM_MAN_SLEEP_MAN_SLEEP_TIME_MASK       (0xFFFFFFU)
+#define RSIM_MAN_SLEEP_MAN_SLEEP_TIME_SHIFT      (0U)
+#define RSIM_MAN_SLEEP_MAN_SLEEP_TIME(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_MAN_SLEEP_MAN_SLEEP_TIME_SHIFT)) & RSIM_MAN_SLEEP_MAN_SLEEP_TIME_MASK)
+/*! @} */
+
+/*! @name MAN_WAKE - MAN Deep Sleep Wake Time */
+/*! @{ */
+#define RSIM_MAN_WAKE_MAN_WAKE_TIME_MASK         (0xFFFFFFU)
+#define RSIM_MAN_WAKE_MAN_WAKE_TIME_SHIFT        (0U)
+#define RSIM_MAN_WAKE_MAN_WAKE_TIME(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_MAN_WAKE_MAN_WAKE_TIME_SHIFT)) & RSIM_MAN_WAKE_MAN_WAKE_TIME_MASK)
+#define RSIM_MAN_WAKE_MAN_FSM_STATE_MASK         (0x70000000U)
+#define RSIM_MAN_WAKE_MAN_FSM_STATE_SHIFT        (28U)
+#define RSIM_MAN_WAKE_MAN_FSM_STATE(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_MAN_WAKE_MAN_FSM_STATE_SHIFT)) & RSIM_MAN_WAKE_MAN_FSM_STATE_MASK)
+/*! @} */
+
+/*! @name RF_OSC_CTRL - Radio Oscillator Control */
+/*! @{ */
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_MASK (0x3U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_SHIFT (0U)
+/*! BB_XTAL_ALC_COUNT_SEL - rmap_bb_xtal_alc_count_sel_hv[1:0]
+ *  0b00..2048 (64 us @ 32 MHz)
+ *  0b01..4096 (128 us @ 32 MHz)
+ *  0b10..8192 (256 us @ 32 MHz)
+ *  0b11..16384 (512 us @ 32 MHz)
+ */
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_MASK)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_MASK     (0x4U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_SHIFT    (2U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_MASK)
+#define RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_MASK   (0x8U)
+#define RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_SHIFT  (3U)
+#define RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN(x)     (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_SHIFT)) & RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_MASK)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_MASK  (0x1F0U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_SHIFT (4U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_MASK)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_MASK (0x200U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_SHIFT (9U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_MASK)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_MASK    (0x400U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_SHIFT   (10U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL(x)      (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_MASK)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_MASK (0x800U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_SHIFT (11U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON(x)   (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_MASK)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_GM_MASK         (0x1F000U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_GM_SHIFT        (12U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_GM(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_GM_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_GM_MASK)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_MASK    (0x20000U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_SHIFT   (17U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD(x)      (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_MASK)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_MASK (0x40000U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_SHIFT (18U)
+/*! BB_XTAL_ON_OVRD_ON - rmap_bb_xtal_on_ovrd_on_hv
+ *  0b0..rfctrl_bb_xtal_on_hv is asserted
+ *  0b1..rfctrl_bb_xtal_on_ovrd_hv is asserted
+ */
+#define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON(x)   (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_MASK)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_MASK (0x300000U)
+#define RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_SHIFT (20U)
+/*! BB_XTAL_READY_COUNT_SEL - rmap_bb_xtal_ready_count_sel_hv[1:0]
+ *  0b00..1024 counts (32 us @ 32 MHz)
+ *  0b01..2048 (64 us @ 32 MHz)
+ *  0b10..4096 (128 us @ 32 MHz)
+ *  0b11..8192 (256 us @ 32 MHz)
+ */
+#define RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_MASK)
+#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_MASK (0x8000000U)
+#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_SHIFT (27U)
+#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_MASK)
+#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK (0x10000000U)
+#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_SHIFT (28U)
+#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD(x)   (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK)
+#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK (0x20000000U)
+#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_SHIFT (29U)
+#define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK)
+#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_MASK (0x40000000U)
+#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_SHIFT (30U)
+#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD(x)  (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_SHIFT)) & RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_MASK)
+#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_EN_MASK (0x80000000U)
+#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_EN_SHIFT (31U)
+#define RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_EN_SHIFT)) & RSIM_RF_OSC_CTRL_RF_NOT_ALLOWED_OVRD_EN_MASK)
+/*! @} */
+
+/*! @name ANA_TEST - Radio Analog Test Registers */
+/*! @{ */
+#define RSIM_ANA_TEST_XTAL_OUT_BUF_EN_MASK       (0x10U)
+#define RSIM_ANA_TEST_XTAL_OUT_BUF_EN_SHIFT      (4U)
+#define RSIM_ANA_TEST_XTAL_OUT_BUF_EN(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_XTAL_OUT_BUF_EN_SHIFT)) & RSIM_ANA_TEST_XTAL_OUT_BUF_EN_MASK)
+/*! @} */
+
+/*! @name ANA_TRIM - Radio Analog Trim Registers */
+/*! @{ */
+#define RSIM_ANA_TRIM_BB_LDO_LS_SPARE_MASK       (0x3U)
+#define RSIM_ANA_TRIM_BB_LDO_LS_SPARE_SHIFT      (0U)
+#define RSIM_ANA_TRIM_BB_LDO_LS_SPARE(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_LS_SPARE_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_LS_SPARE_MASK)
+#define RSIM_ANA_TRIM_BB_LDO_LS_TRIM_MASK        (0x38U)
+#define RSIM_ANA_TRIM_BB_LDO_LS_TRIM_SHIFT       (3U)
+/*! BB_LDO_LS_TRIM - rmap_bb_ldo_ls_trim_hv[2:0]
+ *  0b000..1.20 V (Default)
+ *  0b001..1.25 V
+ *  0b010..1.28 V
+ *  0b011..1.33 V
+ *  0b100..1.40 V
+ *  0b101..1.44 V
+ *  0b110..1.50 V
+ *  0b111..1.66 V
+ */
+#define RSIM_ANA_TRIM_BB_LDO_LS_TRIM(x)          (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_LS_TRIM_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_LS_TRIM_MASK)
+#define RSIM_ANA_TRIM_BB_LDO_XO_SPARE_MASK       (0xC0U)
+#define RSIM_ANA_TRIM_BB_LDO_XO_SPARE_SHIFT      (6U)
+#define RSIM_ANA_TRIM_BB_LDO_XO_SPARE(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_XO_SPARE_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_XO_SPARE_MASK)
+#define RSIM_ANA_TRIM_BB_LDO_XO_TRIM_MASK        (0x700U)
+#define RSIM_ANA_TRIM_BB_LDO_XO_TRIM_SHIFT       (8U)
+/*! BB_LDO_XO_TRIM - rmap_bb_ldo_xo_trim_hv[2:0]
+ *  0b000..1.20 V (Default)
+ *  0b001..1.25 V
+ *  0b010..1.28 V
+ *  0b011..1.33 V
+ *  0b100..1.40 V
+ *  0b101..1.44 V
+ *  0b110..1.50 V
+ *  0b111..1.66 V
+ */
+#define RSIM_ANA_TRIM_BB_LDO_XO_TRIM(x)          (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_XO_TRIM_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_XO_TRIM_MASK)
+#define RSIM_ANA_TRIM_BB_XTAL_SPARE_MASK         (0xF800U)
+#define RSIM_ANA_TRIM_BB_XTAL_SPARE_SHIFT        (11U)
+#define RSIM_ANA_TRIM_BB_XTAL_SPARE(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_XTAL_SPARE_SHIFT)) & RSIM_ANA_TRIM_BB_XTAL_SPARE_MASK)
+#define RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK          (0xFF0000U)
+#define RSIM_ANA_TRIM_BB_XTAL_TRIM_SHIFT         (16U)
+#define RSIM_ANA_TRIM_BB_XTAL_TRIM(x)            (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_XTAL_TRIM_SHIFT)) & RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK)
+#define RSIM_ANA_TRIM_BG_1V_TRIM_MASK            (0xF000000U)
+#define RSIM_ANA_TRIM_BG_1V_TRIM_SHIFT           (24U)
+/*! BG_1V_TRIM - rmap_bg_1v_trim_hv[3:0]
+ *  0b0000..954.14 mV
+ *  0b0001..959.26 mV
+ *  0b0010..964.38 mV
+ *  0b0011..969.5 mV
+ *  0b0100..974.6 mV
+ *  0b0101..979.7 mV
+ *  0b0110..984.8 mV
+ *  0b0111..989.9 mV
+ *  0b1000..995 mV (Default)
+ *  0b1001..1 V
+ *  0b1010..1.005 V
+ *  0b1011..1.01 V
+ *  0b1100..1.015 V
+ *  0b1101..1.02 V
+ *  0b1110..1.025 V
+ *  0b1111..1.031 V
+ */
+#define RSIM_ANA_TRIM_BG_1V_TRIM(x)              (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BG_1V_TRIM_SHIFT)) & RSIM_ANA_TRIM_BG_1V_TRIM_MASK)
+#define RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_MASK      (0xF0000000U)
+#define RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_SHIFT     (28U)
+/*! BG_IBIAS_5U_TRIM - rmap_bg_ibias_5u_trim_hv[3:0]
+ *  0b0000..3.55 uA
+ *  0b0001..3.73 uA
+ *  0b0010..4.04 uA
+ *  0b0011..4.22 uA
+ *  0b0100..4.39 uA
+ *  0b0101..4.57 uA
+ *  0b0110..4.89 uA
+ *  0b0111..5.06 (Default)
+ *  0b1000..5.23 uA
+ *  0b1001..5.41 uA
+ *  0b1010..5.72 uA
+ *  0b1011..5.9 uA
+ *  0b1100..6.07 uA
+ *  0b1101..6.25 uA
+ *  0b1110..6.56 uA
+ *  0b1111..6.74 uA
+ */
+#define RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_SHIFT)) & RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group RSIM_Register_Masks */
+
+
+/* RSIM - Peripheral instance base addresses */
+/** Peripheral RSIM base address */
+#define RSIM_BASE                                (0x4102F000u)
+/** Peripheral RSIM base pointer */
+#define RSIM                                     ((RSIM_Type *)RSIM_BASE)
+/** Array initializer of RSIM peripheral base addresses */
+#define RSIM_BASE_ADDRS                          { RSIM_BASE }
+/** Array initializer of RSIM peripheral base pointers */
+#define RSIM_BASE_PTRS                           { RSIM }
+
+/*!
+ * @}
+ */ /* end of group RSIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TSR;                               /**< RTC Time Seconds Register, offset: 0x0 */
+  __IO uint32_t TPR;                               /**< RTC Time Prescaler Register, offset: 0x4 */
+  __IO uint32_t TAR;                               /**< RTC Time Alarm Register, offset: 0x8 */
+  __IO uint32_t TCR;                               /**< RTC Time Compensation Register, offset: 0xC */
+  __IO uint32_t CR;                                /**< RTC Control Register, offset: 0x10 */
+  __IO uint32_t SR;                                /**< RTC Status Register, offset: 0x14 */
+  __IO uint32_t LR;                                /**< RTC Lock Register, offset: 0x18 */
+  __IO uint32_t IER;                               /**< RTC Interrupt Enable Register, offset: 0x1C */
+  __I  uint32_t TTSR;                              /**< RTC Tamper Time Seconds Register, offset: 0x20 */
+  __IO uint32_t MER;                               /**< RTC Monotonic Enable Register, offset: 0x24 */
+  __IO uint32_t MCLR;                              /**< RTC Monotonic Counter Low Register, offset: 0x28 */
+  __IO uint32_t MCHR;                              /**< RTC Monotonic Counter High Register, offset: 0x2C */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TDR;                               /**< RTC Tamper Detect Register, offset: 0x34 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t TIR;                               /**< RTC Tamper Interrupt Register, offset: 0x3C */
+  __IO uint32_t PCR[4];                            /**< RTC Pin Configuration Register, array offset: 0x40, array step: 0x4 */
+       uint8_t RESERVED_2[1968];
+  __IO uint32_t WAR;                               /**< RTC Write Access Register, offset: 0x800 */
+  __IO uint32_t RAR;                               /**< RTC Read Access Register, offset: 0x804 */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/*! @name TSR - RTC Time Seconds Register */
+/*! @{ */
+#define RTC_TSR_TSR_MASK                         (0xFFFFFFFFU)
+#define RTC_TSR_TSR_SHIFT                        (0U)
+#define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
+/*! @} */
+
+/*! @name TPR - RTC Time Prescaler Register */
+/*! @{ */
+#define RTC_TPR_TPR_MASK                         (0xFFFFU)
+#define RTC_TPR_TPR_SHIFT                        (0U)
+#define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
+/*! @} */
+
+/*! @name TAR - RTC Time Alarm Register */
+/*! @{ */
+#define RTC_TAR_TAR_MASK                         (0xFFFFFFFFU)
+#define RTC_TAR_TAR_SHIFT                        (0U)
+#define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
+/*! @} */
+
+/*! @name TCR - RTC Time Compensation Register */
+/*! @{ */
+#define RTC_TCR_TCR_MASK                         (0xFFU)
+#define RTC_TCR_TCR_SHIFT                        (0U)
+/*! TCR - Time Compensation Register
+ *  0b10000000..Time Prescaler Register overflows every 32896 clock cycles.
+ *  0b10000001..Time Prescaler Register overflows every 32895 clock cycles.
+ *  0b11111111..Time Prescaler Register overflows every 32769 clock cycles.
+ *  0b00000000..Time Prescaler Register overflows every 32768 clock cycles.
+ *  0b00000001..Time Prescaler Register overflows every 32767 clock cycles.
+ *  0b01111110..Time Prescaler Register overflows every 32642 clock cycles.
+ *  0b01111111..Time Prescaler Register overflows every 32641 clock cycles.
+ */
+#define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK                         (0xFF00U)
+#define RTC_TCR_CIR_SHIFT                        (8U)
+#define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK                         (0xFF0000U)
+#define RTC_TCR_TCV_SHIFT                        (16U)
+#define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK                         (0xFF000000U)
+#define RTC_TCR_CIC_SHIFT                        (24U)
+#define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
+/*! @} */
+
+/*! @name CR - RTC Control Register */
+/*! @{ */
+#define RTC_CR_SWR_MASK                          (0x1U)
+#define RTC_CR_SWR_SHIFT                         (0U)
+/*! SWR - Software Reset
+ *  0b0..No effect.
+ *  0b1..Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software explicitly clearing it.
+ */
+#define RTC_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
+#define RTC_CR_WPE_MASK                          (0x2U)
+#define RTC_CR_WPE_SHIFT                         (1U)
+/*! WPE - Wakeup Pin Enable
+ *  0b0..RTC_WAKEUP pin is disabled.
+ *  0b1..RTC_WAKEUP pin is enabled and asserts if the RTC interrupt asserts or if the wakeup pin is forced on.
+ */
+#define RTC_CR_WPE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
+#define RTC_CR_SUP_MASK                          (0x4U)
+#define RTC_CR_SUP_SHIFT                         (2U)
+/*! SUP - Supervisor Access
+ *  0b0..Non-supervisor mode write accesses are not supported and generate a bus error.
+ *  0b1..Non-supervisor mode write accesses are supported.
+ */
+#define RTC_CR_SUP(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
+#define RTC_CR_UM_MASK                           (0x8U)
+#define RTC_CR_UM_SHIFT                          (3U)
+/*! UM - Update Mode
+ *  0b0..Registers cannot be written when locked.
+ *  0b1..Registers can be written when locked under limited conditions.
+ */
+#define RTC_CR_UM(x)                             (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
+#define RTC_CR_WPS_MASK                          (0x10U)
+#define RTC_CR_WPS_SHIFT                         (4U)
+/*! WPS - Wakeup Pin Select
+ *  0b0..RTC_WAKEUP pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on.
+ *  0b1..RTC_WAKEUP pin outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals.
+ */
+#define RTC_CR_WPS(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
+#define RTC_CR_CPS_MASK                          (0x20U)
+#define RTC_CR_CPS_SHIFT                         (5U)
+/*! CPS - Clock Pin Select
+ *  0b0..The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT.
+ *  0b1..The RTC 32.768 kHz clock is output on RTC_CLKOUT, provided it is output to other peripherals.
+ */
+#define RTC_CR_CPS(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_CPS_SHIFT)) & RTC_CR_CPS_MASK)
+#define RTC_CR_LPOS_MASK                         (0x80U)
+#define RTC_CR_LPOS_SHIFT                        (7U)
+/*! LPOS - LPO Select
+ *  0b0..RTC prescaler increments using 32.768 kHz clock.
+ *  0b1..RTC prescaler increments using 1 kHz LPO, bits [4:0] of the prescaler are ignored.
+ */
+#define RTC_CR_LPOS(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_LPOS_SHIFT)) & RTC_CR_LPOS_MASK)
+#define RTC_CR_OSCE_MASK                         (0x100U)
+#define RTC_CR_OSCE_SHIFT                        (8U)
+/*! OSCE - Oscillator Enable
+ *  0b0..32.768 kHz oscillator is disabled.
+ *  0b1..32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.
+ */
+#define RTC_CR_OSCE(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
+#define RTC_CR_CLKO_MASK                         (0x200U)
+#define RTC_CR_CLKO_SHIFT                        (9U)
+/*! CLKO - Clock Output
+ *  0b0..The 32 kHz clock is output to other peripherals.
+ *  0b1..The 32 kHz clock is not output to other peripherals.
+ */
+#define RTC_CR_CLKO(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
+#define RTC_CR_SC16P_MASK                        (0x400U)
+#define RTC_CR_SC16P_SHIFT                       (10U)
+/*! SC16P - Oscillator 16pF Load Configure
+ *  0b0..Disable the load.
+ *  0b1..Enable the additional load.
+ */
+#define RTC_CR_SC16P(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
+#define RTC_CR_SC8P_MASK                         (0x800U)
+#define RTC_CR_SC8P_SHIFT                        (11U)
+/*! SC8P - Oscillator 8pF Load Configure
+ *  0b0..Disable the load.
+ *  0b1..Enable the additional load.
+ */
+#define RTC_CR_SC8P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
+#define RTC_CR_SC4P_MASK                         (0x1000U)
+#define RTC_CR_SC4P_SHIFT                        (12U)
+/*! SC4P - Oscillator 4pF Load Configure
+ *  0b0..Disable the load.
+ *  0b1..Enable the additional load.
+ */
+#define RTC_CR_SC4P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
+#define RTC_CR_SC2P_MASK                         (0x2000U)
+#define RTC_CR_SC2P_SHIFT                        (13U)
+/*! SC2P - Oscillator 2pF Load Configure
+ *  0b0..Disable the load.
+ *  0b1..Enable the additional load.
+ */
+#define RTC_CR_SC2P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
+#define RTC_CR_OSCM_MASK                         (0x8000U)
+#define RTC_CR_OSCM_SHIFT                        (15U)
+/*! OSCM - Oscillator Mode Select
+ *  0b0..Configures the 32.768kHz crystal oscillator for robust operation supporting a wide range of crystals.
+ *  0b1..Configures the 32.768kHz crystal oscillator for low power operation supporting a more limited range of crystals.
+ */
+#define RTC_CR_OSCM(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCM_SHIFT)) & RTC_CR_OSCM_MASK)
+#define RTC_CR_PORS_MASK                         (0x30000U)
+#define RTC_CR_PORS_SHIFT                        (16U)
+/*! PORS - POR Select
+ *  0b00..POR brownout enabled for 120us every 128ms.
+ *  0b01..POR brownout enabled for 120us every 64ms.
+ *  0b10..POR brownout enabled for 120us every 32ms.
+ *  0b11..POR brownout always enabled.
+ */
+#define RTC_CR_PORS(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_PORS_SHIFT)) & RTC_CR_PORS_MASK)
+#define RTC_CR_CPE_MASK                          (0x3000000U)
+#define RTC_CR_CPE_SHIFT                         (24U)
+/*! CPE - Clock Pin Enable
+ *  0b00..The RTC_CLKOUT function is disabled.
+ *  0b01..Enable RTC_CLKOUT pin on pin 1.
+ *  0b10..Enable RTC_CLKOUT pin on pin 2.
+ *  0b11..Enable RTC_CLKOUT pin on pin 3.
+ */
+#define RTC_CR_CPE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_CPE_SHIFT)) & RTC_CR_CPE_MASK)
+/*! @} */
+
+/*! @name SR - RTC Status Register */
+/*! @{ */
+#define RTC_SR_TIF_MASK                          (0x1U)
+#define RTC_SR_TIF_SHIFT                         (0U)
+/*! TIF - Time Invalid Flag
+ *  0b0..Time is valid.
+ *  0b1..Time is invalid and time counter is read as zero.
+ */
+#define RTC_SR_TIF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
+#define RTC_SR_TOF_MASK                          (0x2U)
+#define RTC_SR_TOF_SHIFT                         (1U)
+/*! TOF - Time Overflow Flag
+ *  0b0..Time overflow has not occurred.
+ *  0b1..Time overflow has occurred and time counter is read as zero.
+ */
+#define RTC_SR_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
+#define RTC_SR_TAF_MASK                          (0x4U)
+#define RTC_SR_TAF_SHIFT                         (2U)
+/*! TAF - Time Alarm Flag
+ *  0b0..Time alarm has not occurred.
+ *  0b1..Time alarm has occurred.
+ */
+#define RTC_SR_TAF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
+#define RTC_SR_MOF_MASK                          (0x8U)
+#define RTC_SR_MOF_SHIFT                         (3U)
+/*! MOF - Monotonic Overflow Flag
+ *  0b0..Monotonic counter overflow has not occurred.
+ *  0b1..Monotonic counter overflow has occurred and monotonic counter is read as zero.
+ */
+#define RTC_SR_MOF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_MOF_SHIFT)) & RTC_SR_MOF_MASK)
+#define RTC_SR_TCE_MASK                          (0x10U)
+#define RTC_SR_TCE_SHIFT                         (4U)
+/*! TCE - Time Counter Enable
+ *  0b0..Time counter is disabled.
+ *  0b1..Time counter is enabled.
+ */
+#define RTC_SR_TCE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
+#define RTC_SR_TIDF_MASK                         (0x80U)
+#define RTC_SR_TIDF_SHIFT                        (7U)
+/*! TIDF - Tamper Interrupt Detect Flag
+ *  0b0..Tamper interrupt has not asserted.
+ *  0b1..Tamper interrupt has asserted.
+ */
+#define RTC_SR_TIDF(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIDF_SHIFT)) & RTC_SR_TIDF_MASK)
+/*! @} */
+
+/*! @name LR - RTC Lock Register */
+/*! @{ */
+#define RTC_LR_TCL_MASK                          (0x8U)
+#define RTC_LR_TCL_SHIFT                         (3U)
+/*! TCL - Time Compensation Lock
+ *  0b0..Time Compensation Register is locked and writes are ignored.
+ *  0b1..Time Compensation Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_TCL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
+#define RTC_LR_CRL_MASK                          (0x10U)
+#define RTC_LR_CRL_SHIFT                         (4U)
+/*! CRL - Control Register Lock
+ *  0b0..Control Register is locked and writes are ignored.
+ *  0b1..Control Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_CRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
+#define RTC_LR_SRL_MASK                          (0x20U)
+#define RTC_LR_SRL_SHIFT                         (5U)
+/*! SRL - Status Register Lock
+ *  0b0..Status Register is locked and writes are ignored.
+ *  0b1..Status Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_SRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
+#define RTC_LR_LRL_MASK                          (0x40U)
+#define RTC_LR_LRL_SHIFT                         (6U)
+/*! LRL - Lock Register Lock
+ *  0b0..Lock Register is locked and writes are ignored.
+ *  0b1..Lock Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_LRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
+#define RTC_LR_TTSL_MASK                         (0x100U)
+#define RTC_LR_TTSL_SHIFT                        (8U)
+/*! TTSL - Tamper Time Seconds Lock
+ *  0b0..Tamper Time Seconds Register is locked and writes are ignored.
+ *  0b1..Tamper Time Seconds Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_TTSL(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_LR_TTSL_SHIFT)) & RTC_LR_TTSL_MASK)
+#define RTC_LR_MEL_MASK                          (0x200U)
+#define RTC_LR_MEL_SHIFT                         (9U)
+/*! MEL - Monotonic Enable Lock
+ *  0b0..Monotonic Enable Register is locked and writes are ignored.
+ *  0b1..Monotonic Enable Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_MEL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_MEL_SHIFT)) & RTC_LR_MEL_MASK)
+#define RTC_LR_MCLL_MASK                         (0x400U)
+#define RTC_LR_MCLL_SHIFT                        (10U)
+/*! MCLL - Monotonic Counter Low Lock
+ *  0b0..Monotonic Counter Low Register is locked and writes are ignored.
+ *  0b1..Monotonic Counter Low Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_MCLL(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCLL_SHIFT)) & RTC_LR_MCLL_MASK)
+#define RTC_LR_MCHL_MASK                         (0x800U)
+#define RTC_LR_MCHL_SHIFT                        (11U)
+/*! MCHL - Monotonic Counter High Lock
+ *  0b0..Monotonic Counter High Register is locked and writes are ignored.
+ *  0b1..Monotonic Counter High Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_MCHL(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCHL_SHIFT)) & RTC_LR_MCHL_MASK)
+#define RTC_LR_TDL_MASK                          (0x2000U)
+#define RTC_LR_TDL_SHIFT                         (13U)
+/*! TDL - Tamper Detect Lock
+ *  0b0..Tamper Detect Register is locked and writes are ignored.
+ *  0b1..Tamper Detect Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_TDL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_TDL_SHIFT)) & RTC_LR_TDL_MASK)
+#define RTC_LR_TIL_MASK                          (0x8000U)
+#define RTC_LR_TIL_SHIFT                         (15U)
+/*! TIL - Tamper Interrupt Lock
+ *  0b0..Tamper Interrupt Register is locked and writes are ignored.
+ *  0b1..Tamper Interrupt Register is not locked and writes complete as normal.
+ */
+#define RTC_LR_TIL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_TIL_SHIFT)) & RTC_LR_TIL_MASK)
+#define RTC_LR_PCL_MASK                          (0xF0000U)
+#define RTC_LR_PCL_SHIFT                         (16U)
+#define RTC_LR_PCL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_PCL_SHIFT)) & RTC_LR_PCL_MASK)
+/*! @} */
+
+/*! @name IER - RTC Interrupt Enable Register */
+/*! @{ */
+#define RTC_IER_TIIE_MASK                        (0x1U)
+#define RTC_IER_TIIE_SHIFT                       (0U)
+/*! TIIE - Time Invalid Interrupt Enable
+ *  0b0..Time invalid flag does not generate an interrupt.
+ *  0b1..Time invalid flag does generate an interrupt.
+ */
+#define RTC_IER_TIIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
+#define RTC_IER_TOIE_MASK                        (0x2U)
+#define RTC_IER_TOIE_SHIFT                       (1U)
+/*! TOIE - Time Overflow Interrupt Enable
+ *  0b0..Time overflow flag does not generate an interrupt.
+ *  0b1..Time overflow flag does generate an interrupt.
+ */
+#define RTC_IER_TOIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
+#define RTC_IER_TAIE_MASK                        (0x4U)
+#define RTC_IER_TAIE_SHIFT                       (2U)
+/*! TAIE - Time Alarm Interrupt Enable
+ *  0b0..Time alarm flag does not generate an interrupt.
+ *  0b1..Time alarm flag does generate an interrupt.
+ */
+#define RTC_IER_TAIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
+#define RTC_IER_MOIE_MASK                        (0x8U)
+#define RTC_IER_MOIE_SHIFT                       (3U)
+/*! MOIE - Monotonic Overflow Interrupt Enable
+ *  0b0..Monotonic overflow flag does not generate an interrupt.
+ *  0b1..Monotonic overflow flag does generate an interrupt.
+ */
+#define RTC_IER_MOIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_MOIE_SHIFT)) & RTC_IER_MOIE_MASK)
+#define RTC_IER_TSIE_MASK                        (0x10U)
+#define RTC_IER_TSIE_SHIFT                       (4U)
+/*! TSIE - Time Seconds Interrupt Enable
+ *  0b0..Seconds interrupt is disabled.
+ *  0b1..Seconds interrupt is enabled.
+ */
+#define RTC_IER_TSIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
+#define RTC_IER_WPON_MASK                        (0x80U)
+#define RTC_IER_WPON_SHIFT                       (7U)
+/*! WPON - Wakeup Pin On
+ *  0b0..No effect.
+ *  0b1..If the RTC_WAKEUP pin is enabled, then the pin will assert.
+ */
+#define RTC_IER_WPON(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
+#define RTC_IER_TSIC_MASK                        (0x70000U)
+#define RTC_IER_TSIC_SHIFT                       (16U)
+/*! TSIC - Timer Seconds Interrupt Configuration
+ *  0b000..1 Hz.
+ *  0b001..2 Hz.
+ *  0b010..4 Hz.
+ *  0b011..8 Hz.
+ *  0b100..16 Hz.
+ *  0b101..32 Hz.
+ *  0b110..64 Hz.
+ *  0b111..128 Hz.
+ */
+#define RTC_IER_TSIC(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIC_SHIFT)) & RTC_IER_TSIC_MASK)
+/*! @} */
+
+/*! @name TTSR - RTC Tamper Time Seconds Register */
+/*! @{ */
+#define RTC_TTSR_TTS_MASK                        (0xFFFFFFFFU)
+#define RTC_TTSR_TTS_SHIFT                       (0U)
+#define RTC_TTSR_TTS(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_TTSR_TTS_SHIFT)) & RTC_TTSR_TTS_MASK)
+/*! @} */
+
+/*! @name MER - RTC Monotonic Enable Register */
+/*! @{ */
+#define RTC_MER_MCE_MASK                         (0x10U)
+#define RTC_MER_MCE_SHIFT                        (4U)
+/*! MCE - Monotonic Counter Enable
+ *  0b0..Writes to the monotonic counter load the counter with the value written.
+ *  0b1..Writes to the monotonic counter increment the counter.
+ */
+#define RTC_MER_MCE(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_MER_MCE_SHIFT)) & RTC_MER_MCE_MASK)
+/*! @} */
+
+/*! @name MCLR - RTC Monotonic Counter Low Register */
+/*! @{ */
+#define RTC_MCLR_MCL_MASK                        (0xFFFFFFFFU)
+#define RTC_MCLR_MCL_SHIFT                       (0U)
+#define RTC_MCLR_MCL(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_MCLR_MCL_SHIFT)) & RTC_MCLR_MCL_MASK)
+/*! @} */
+
+/*! @name MCHR - RTC Monotonic Counter High Register */
+/*! @{ */
+#define RTC_MCHR_MCH_MASK                        (0xFFFFFFFFU)
+#define RTC_MCHR_MCH_SHIFT                       (0U)
+#define RTC_MCHR_MCH(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_MCHR_MCH_SHIFT)) & RTC_MCHR_MCH_MASK)
+/*! @} */
+
+/*! @name TDR - RTC Tamper Detect Register */
+/*! @{ */
+#define RTC_TDR_LCTF_MASK                        (0x10U)
+#define RTC_TDR_LCTF_SHIFT                       (4U)
+/*! LCTF - Loss of Clock Tamper Flag
+ *  0b0..Tamper not detected.
+ *  0b1..Loss of Clock tamper detected.
+ */
+#define RTC_TDR_LCTF(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_TDR_LCTF_SHIFT)) & RTC_TDR_LCTF_MASK)
+#define RTC_TDR_STF_MASK                         (0x20U)
+#define RTC_TDR_STF_SHIFT                        (5U)
+/*! STF - Security Tamper Flag
+ *  0b0..Tamper not detected.
+ *  0b1..Security module tamper detected.
+ */
+#define RTC_TDR_STF(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TDR_STF_SHIFT)) & RTC_TDR_STF_MASK)
+#define RTC_TDR_FSF_MASK                         (0x40U)
+#define RTC_TDR_FSF_SHIFT                        (6U)
+/*! FSF - Flash Security Flag
+ *  0b0..Tamper not detected.
+ *  0b1..Flash security tamper detected.
+ */
+#define RTC_TDR_FSF(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TDR_FSF_SHIFT)) & RTC_TDR_FSF_MASK)
+#define RTC_TDR_TMF_MASK                         (0x80U)
+#define RTC_TDR_TMF_SHIFT                        (7U)
+/*! TMF - Test Mode Flag
+ *  0b0..Tamper not detected.
+ *  0b1..Test mode tamper detected.
+ */
+#define RTC_TDR_TMF(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TDR_TMF_SHIFT)) & RTC_TDR_TMF_MASK)
+#define RTC_TDR_TPF_MASK                         (0xF0000U)
+#define RTC_TDR_TPF_SHIFT                        (16U)
+#define RTC_TDR_TPF(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TDR_TPF_SHIFT)) & RTC_TDR_TPF_MASK)
+/*! @} */
+
+/*! @name TIR - RTC Tamper Interrupt Register */
+/*! @{ */
+#define RTC_TIR_LCIE_MASK                        (0x10U)
+#define RTC_TIR_LCIE_SHIFT                       (4U)
+/*! LCIE - Loss of Clock Interrupt Enable
+ *  0b0..Interupt disabled.
+ *  0b1..An interrupt is generated when the loss of clock flag is set.
+ */
+#define RTC_TIR_LCIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_TIR_LCIE_SHIFT)) & RTC_TIR_LCIE_MASK)
+#define RTC_TIR_SIE_MASK                         (0x20U)
+#define RTC_TIR_SIE_SHIFT                        (5U)
+/*! SIE - Security Module Interrupt Enable
+ *  0b0..Interupt disabled.
+ *  0b1..An interrupt is generated when the security module flag is set.
+ */
+#define RTC_TIR_SIE(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TIR_SIE_SHIFT)) & RTC_TIR_SIE_MASK)
+#define RTC_TIR_FSIE_MASK                        (0x40U)
+#define RTC_TIR_FSIE_SHIFT                       (6U)
+/*! FSIE - Flash Security Interrupt Enable
+ *  0b0..Interupt disabled.
+ *  0b1..An interrupt is generated when the flash security flag is set.
+ */
+#define RTC_TIR_FSIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_TIR_FSIE_SHIFT)) & RTC_TIR_FSIE_MASK)
+#define RTC_TIR_TMIE_MASK                        (0x80U)
+#define RTC_TIR_TMIE_SHIFT                       (7U)
+/*! TMIE - Test Mode Interrupt Enable
+ *  0b0..Interupt disabled.
+ *  0b1..An interrupt is generated when the test mode flag is set.
+ */
+#define RTC_TIR_TMIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_TIR_TMIE_SHIFT)) & RTC_TIR_TMIE_MASK)
+#define RTC_TIR_TPIE_MASK                        (0xF0000U)
+#define RTC_TIR_TPIE_SHIFT                       (16U)
+#define RTC_TIR_TPIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_TIR_TPIE_SHIFT)) & RTC_TIR_TPIE_MASK)
+/*! @} */
+
+/*! @name PCR - RTC Pin Configuration Register */
+/*! @{ */
+#define RTC_PCR_TPE_MASK                         (0x1000000U)
+#define RTC_PCR_TPE_SHIFT                        (24U)
+/*! TPE - Tamper Pull Enable
+ *  0b0..Pull resistor is disabled on tamper pin.
+ *  0b1..Pull resistor is enabled on tamper pin.
+ */
+#define RTC_PCR_TPE(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TPE_SHIFT)) & RTC_PCR_TPE_MASK)
+#define RTC_PCR_TPS_MASK                         (0x2000000U)
+#define RTC_PCR_TPS_SHIFT                        (25U)
+/*! TPS - Tamper Pull Select
+ *  0b0..Tamper pin pull resistor direction will assert the tamper pin.
+ *  0b1..Tamper pin pull resistor direction will negate the tamper pin.
+ */
+#define RTC_PCR_TPS(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TPS_SHIFT)) & RTC_PCR_TPS_MASK)
+#define RTC_PCR_TFE_MASK                         (0x4000000U)
+#define RTC_PCR_TFE_SHIFT                        (26U)
+/*! TFE - Tamper Filter Enable
+ *  0b0..Input filter is disabled on the tamper pin.
+ *  0b1..Input filter is enabled on the tamper pin.
+ */
+#define RTC_PCR_TFE(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TFE_SHIFT)) & RTC_PCR_TFE_MASK)
+#define RTC_PCR_TPP_MASK                         (0x8000000U)
+#define RTC_PCR_TPP_SHIFT                        (27U)
+/*! TPP - Tamper Pin Polarity
+ *  0b0..Tamper pin is active high.
+ *  0b1..Tamper pin is active low.
+ */
+#define RTC_PCR_TPP(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TPP_SHIFT)) & RTC_PCR_TPP_MASK)
+#define RTC_PCR_TPID_MASK                        (0x80000000U)
+#define RTC_PCR_TPID_SHIFT                       (31U)
+/*! TPID - Tamper Pin Input Data
+ *  0b0..Tamper pin input data is logic zero.
+ *  0b1..Tamper pin input data is logic one.
+ */
+#define RTC_PCR_TPID(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TPID_SHIFT)) & RTC_PCR_TPID_MASK)
+/*! @} */
+
+/* The count of RTC_PCR */
+#define RTC_PCR_COUNT                            (4U)
+
+/*! @name WAR - RTC Write Access Register */
+/*! @{ */
+#define RTC_WAR_TSRW_MASK                        (0x1U)
+#define RTC_WAR_TSRW_SHIFT                       (0U)
+/*! TSRW - Time Seconds Register Write
+ *  0b0..Writes to the Time Seconds Register are ignored.
+ *  0b1..Writes to the Time Seconds Register complete as normal.
+ */
+#define RTC_WAR_TSRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
+#define RTC_WAR_TPRW_MASK                        (0x2U)
+#define RTC_WAR_TPRW_SHIFT                       (1U)
+/*! TPRW - Time Prescaler Register Write
+ *  0b0..Writes to the Time Prescaler Register are ignored.
+ *  0b1..Writes to the Time Prescaler Register complete as normal.
+ */
+#define RTC_WAR_TPRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
+#define RTC_WAR_TARW_MASK                        (0x4U)
+#define RTC_WAR_TARW_SHIFT                       (2U)
+/*! TARW - Time Alarm Register Write
+ *  0b0..Writes to the Time Alarm Register are ignored.
+ *  0b1..Writes to the Time Alarm Register complete as normal.
+ */
+#define RTC_WAR_TARW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
+#define RTC_WAR_TCRW_MASK                        (0x8U)
+#define RTC_WAR_TCRW_SHIFT                       (3U)
+/*! TCRW - Time Compensation Register Write
+ *  0b0..Writes to the Time Compensation Register are ignored.
+ *  0b1..Writes to the Time Compensation Register complete as normal.
+ */
+#define RTC_WAR_TCRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
+#define RTC_WAR_CRW_MASK                         (0x10U)
+#define RTC_WAR_CRW_SHIFT                        (4U)
+/*! CRW - Control Register Write
+ *  0b0..Writes to the Control Register are ignored.
+ *  0b1..Writes to the Control Register complete as normal.
+ */
+#define RTC_WAR_CRW(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
+#define RTC_WAR_SRW_MASK                         (0x20U)
+#define RTC_WAR_SRW_SHIFT                        (5U)
+/*! SRW - Status Register Write
+ *  0b0..Writes to the Status Register are ignored.
+ *  0b1..Writes to the Status Register complete as normal.
+ */
+#define RTC_WAR_SRW(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
+#define RTC_WAR_LRW_MASK                         (0x40U)
+#define RTC_WAR_LRW_SHIFT                        (6U)
+/*! LRW - Lock Register Write
+ *  0b0..Writes to the Lock Register are ignored.
+ *  0b1..Writes to the Lock Register complete as normal.
+ */
+#define RTC_WAR_LRW(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
+#define RTC_WAR_IERW_MASK                        (0x80U)
+#define RTC_WAR_IERW_SHIFT                       (7U)
+/*! IERW - Interrupt Enable Register Write
+ *  0b0..Writes to the Interupt Enable Register are ignored.
+ *  0b1..Writes to the Interrupt Enable Register complete as normal.
+ */
+#define RTC_WAR_IERW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
+#define RTC_WAR_TTSW_MASK                        (0x100U)
+#define RTC_WAR_TTSW_SHIFT                       (8U)
+/*! TTSW - Tamper Time Seconds Write
+ *  0b0..Writes to the Tamper Time Seconds Register are ignored.
+ *  0b1..Writes to the Tamper Time Seconds Register complete as normal.
+ */
+#define RTC_WAR_TTSW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TTSW_SHIFT)) & RTC_WAR_TTSW_MASK)
+#define RTC_WAR_MERW_MASK                        (0x200U)
+#define RTC_WAR_MERW_SHIFT                       (9U)
+/*! MERW - Monotonic Enable Register Write
+ *  0b0..Writes to the Monotonic Enable Register are ignored.
+ *  0b1..Writes to the Monotonic Enable Register complete as normal.
+ */
+#define RTC_WAR_MERW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MERW_SHIFT)) & RTC_WAR_MERW_MASK)
+#define RTC_WAR_MCLW_MASK                        (0x400U)
+#define RTC_WAR_MCLW_SHIFT                       (10U)
+/*! MCLW - Monotonic Counter Low Write
+ *  0b0..Writes to the Monotonic Counter Low Register are ignored.
+ *  0b1..Writes to the Monotonic Counter Low Register complete as normal.
+ */
+#define RTC_WAR_MCLW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCLW_SHIFT)) & RTC_WAR_MCLW_MASK)
+#define RTC_WAR_MCHW_MASK                        (0x800U)
+#define RTC_WAR_MCHW_SHIFT                       (11U)
+/*! MCHW - Monotonic Counter High Write
+ *  0b0..Writes to the Monotonic Counter High Register are ignored.
+ *  0b1..Writes to the Monotonic Counter High Register complete as normal.
+ */
+#define RTC_WAR_MCHW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCHW_SHIFT)) & RTC_WAR_MCHW_MASK)
+#define RTC_WAR_TDRW_MASK                        (0x2000U)
+#define RTC_WAR_TDRW_SHIFT                       (13U)
+/*! TDRW - Tamper Detect Register Write
+ *  0b0..Writes to the Tamper Detect Register are ignored.
+ *  0b1..Writes to the Tamper Detect Register complete as normal.
+ */
+#define RTC_WAR_TDRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TDRW_SHIFT)) & RTC_WAR_TDRW_MASK)
+#define RTC_WAR_TIRW_MASK                        (0x8000U)
+#define RTC_WAR_TIRW_SHIFT                       (15U)
+/*! TIRW - Tamper Interrupt Register Write
+ *  0b0..Writes to the Tamper Interrupt Register are ignored.
+ *  0b1..Writes to the Tamper Interrupt Register complete as normal.
+ */
+#define RTC_WAR_TIRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TIRW_SHIFT)) & RTC_WAR_TIRW_MASK)
+#define RTC_WAR_PCRW_MASK                        (0xF0000U)
+#define RTC_WAR_PCRW_SHIFT                       (16U)
+#define RTC_WAR_PCRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_PCRW_SHIFT)) & RTC_WAR_PCRW_MASK)
+/*! @} */
+
+/*! @name RAR - RTC Read Access Register */
+/*! @{ */
+#define RTC_RAR_TSRR_MASK                        (0x1U)
+#define RTC_RAR_TSRR_SHIFT                       (0U)
+/*! TSRR - Time Seconds Register Read
+ *  0b0..Reads to the Time Seconds Register are ignored.
+ *  0b1..Reads to the Time Seconds Register complete as normal.
+ */
+#define RTC_RAR_TSRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
+#define RTC_RAR_TPRR_MASK                        (0x2U)
+#define RTC_RAR_TPRR_SHIFT                       (1U)
+/*! TPRR - Time Prescaler Register Read
+ *  0b0..Reads to the Time Pprescaler Register are ignored.
+ *  0b1..Reads to the Time Prescaler Register complete as normal.
+ */
+#define RTC_RAR_TPRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
+#define RTC_RAR_TARR_MASK                        (0x4U)
+#define RTC_RAR_TARR_SHIFT                       (2U)
+/*! TARR - Time Alarm Register Read
+ *  0b0..Reads to the Time Alarm Register are ignored.
+ *  0b1..Reads to the Time Alarm Register complete as normal.
+ */
+#define RTC_RAR_TARR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
+#define RTC_RAR_TCRR_MASK                        (0x8U)
+#define RTC_RAR_TCRR_SHIFT                       (3U)
+/*! TCRR - Time Compensation Register Read
+ *  0b0..Reads to the Time Compensation Register are ignored.
+ *  0b1..Reads to the Time Compensation Register complete as normal.
+ */
+#define RTC_RAR_TCRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
+#define RTC_RAR_CRR_MASK                         (0x10U)
+#define RTC_RAR_CRR_SHIFT                        (4U)
+/*! CRR - Control Register Read
+ *  0b0..Reads to the Control Register are ignored.
+ *  0b1..Reads to the Control Register complete as normal.
+ */
+#define RTC_RAR_CRR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
+#define RTC_RAR_SRR_MASK                         (0x20U)
+#define RTC_RAR_SRR_SHIFT                        (5U)
+/*! SRR - Status Register Read
+ *  0b0..Reads to the Status Register are ignored.
+ *  0b1..Reads to the Status Register complete as normal.
+ */
+#define RTC_RAR_SRR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
+#define RTC_RAR_LRR_MASK                         (0x40U)
+#define RTC_RAR_LRR_SHIFT                        (6U)
+/*! LRR - Lock Register Read
+ *  0b0..Reads to the Lock Register are ignored.
+ *  0b1..Reads to the Lock Register complete as normal.
+ */
+#define RTC_RAR_LRR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
+#define RTC_RAR_IERR_MASK                        (0x80U)
+#define RTC_RAR_IERR_SHIFT                       (7U)
+/*! IERR - Interrupt Enable Register Read
+ *  0b0..Reads to the Interrupt Enable Register are ignored.
+ *  0b1..Reads to the Interrupt Enable Register complete as normal.
+ */
+#define RTC_RAR_IERR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
+#define RTC_RAR_TTSR_MASK                        (0x100U)
+#define RTC_RAR_TTSR_SHIFT                       (8U)
+/*! TTSR - Tamper Time Seconds Read
+ *  0b0..Reads to the Tamper Time Seconds Register are ignored.
+ *  0b1..Reads to the Tamper Time Seconds Register complete as normal.
+ */
+#define RTC_RAR_TTSR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TTSR_SHIFT)) & RTC_RAR_TTSR_MASK)
+#define RTC_RAR_MERR_MASK                        (0x200U)
+#define RTC_RAR_MERR_SHIFT                       (9U)
+/*! MERR - Monotonic Enable Register Read
+ *  0b0..Reads to the Monotonic Enable Register are ignored.
+ *  0b1..Reads to the Monotonic Enable Register complete as normal.
+ */
+#define RTC_RAR_MERR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MERR_SHIFT)) & RTC_RAR_MERR_MASK)
+#define RTC_RAR_MCLR_MASK                        (0x400U)
+#define RTC_RAR_MCLR_SHIFT                       (10U)
+/*! MCLR - Monotonic Counter Low Read
+ *  0b0..Reads to the Monotonic Counter Low Register are ignored.
+ *  0b1..Reads to the Monotonic Counter Low Register complete as normal.
+ */
+#define RTC_RAR_MCLR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCLR_SHIFT)) & RTC_RAR_MCLR_MASK)
+#define RTC_RAR_MCHR_MASK                        (0x800U)
+#define RTC_RAR_MCHR_SHIFT                       (11U)
+/*! MCHR - Monotonic Counter High Read
+ *  0b0..Reads to the Monotonic Counter High Register are ignored.
+ *  0b1..Reads to the Monotonic Counter High Register complete as normal.
+ */
+#define RTC_RAR_MCHR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCHR_SHIFT)) & RTC_RAR_MCHR_MASK)
+#define RTC_RAR_TDRR_MASK                        (0x2000U)
+#define RTC_RAR_TDRR_SHIFT                       (13U)
+/*! TDRR - Tamper Detect Register Read
+ *  0b0..Reads to the Tamper Detect Register are ignored.
+ *  0b1..Reads to the Tamper Detect Register complete as normal.
+ */
+#define RTC_RAR_TDRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TDRR_SHIFT)) & RTC_RAR_TDRR_MASK)
+#define RTC_RAR_TIRR_MASK                        (0x8000U)
+#define RTC_RAR_TIRR_SHIFT                       (15U)
+/*! TIRR - Tamper Interrupt Register Read
+ *  0b0..Reads to the Tamper Interrupt Register are ignored.
+ *  0b1..Reads to the Tamper Interrupt Register complete as normal.
+ */
+#define RTC_RAR_TIRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TIRR_SHIFT)) & RTC_RAR_TIRR_MASK)
+#define RTC_RAR_PCRR_MASK                        (0xF0000U)
+#define RTC_RAR_PCRR_SHIFT                       (16U)
+#define RTC_RAR_PCRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_PCRR_SHIFT)) & RTC_RAR_PCRR_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE                                 (0x40031000u)
+/** Peripheral RTC base pointer */
+#define RTC                                      ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS                           { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS                            { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS                                 { RTC_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SCG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SCG_Peripheral_Access_Layer SCG Peripheral Access Layer
+ * @{
+ */
+
+/** SCG - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+       uint8_t RESERVED_0[8];
+  __I  uint32_t CSR;                               /**< Clock Status Register, offset: 0x10 */
+  __IO uint32_t RCCR;                              /**< Run Clock Control Register, offset: 0x14 */
+  __IO uint32_t VCCR;                              /**< VLPR Clock Control Register, offset: 0x18 */
+  __IO uint32_t HCCR;                              /**< HSRUN Clock Control Register, offset: 0x1C */
+  __IO uint32_t CLKOUTCNFG;                        /**< SCG CLKOUT Configuration Register, offset: 0x20 */
+       uint8_t RESERVED_1[220];
+  __IO uint32_t SOSCCSR;                           /**< System OSC Control Status Register, offset: 0x100 */
+  __IO uint32_t SOSCDIV;                           /**< System OSC Divide Register, offset: 0x104 */
+       uint8_t RESERVED_2[248];
+  __IO uint32_t SIRCCSR;                           /**< Slow IRC Control Status Register, offset: 0x200 */
+  __IO uint32_t SIRCDIV;                           /**< Slow IRC Divide Register, offset: 0x204 */
+  __IO uint32_t SIRCCFG;                           /**< Slow IRC Configuration Register, offset: 0x208 */
+       uint8_t RESERVED_3[244];
+  __IO uint32_t FIRCCSR;                           /**< Fast IRC Control Status Register, offset: 0x300 */
+  __IO uint32_t FIRCDIV;                           /**< Fast IRC Divide Register, offset: 0x304 */
+  __IO uint32_t FIRCCFG;                           /**< Fast IRC Configuration Register, offset: 0x308 */
+  __IO uint32_t FIRCTCFG;                          /**< Fast IRC Trim Configuration Register, offset: 0x30C */
+       uint8_t RESERVED_4[8];
+  __IO uint32_t FIRCSTAT;                          /**< Fast IRC Status Register, offset: 0x318 */
+       uint8_t RESERVED_5[228];
+  __IO uint32_t ROSCCSR;                           /**< RTC OSC Control Status Register, offset: 0x400 */
+       uint8_t RESERVED_6[252];
+  __IO uint32_t LPFLLCSR;                          /**< Low Power FLL Control Status Register, offset: 0x500 */
+  __IO uint32_t LPFLLDIV;                          /**< Low Power FLL Divide Register, offset: 0x504 */
+  __IO uint32_t LPFLLCFG;                          /**< Low Power FLL Configuration Register, offset: 0x508 */
+  __IO uint32_t LPFLLTCFG;                         /**< Low Power FLL Trim Configuration Register, offset: 0x50C */
+       uint8_t RESERVED_7[4];
+  __IO uint32_t LPFLLSTAT;                         /**< Low Power FLL Status Register, offset: 0x514 */
+} SCG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SCG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SCG_Register_Masks SCG Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define SCG_VERID_VERSION_MASK                   (0xFFFFFFFFU)
+#define SCG_VERID_VERSION_SHIFT                  (0U)
+#define SCG_VERID_VERSION(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_VERID_VERSION_SHIFT)) & SCG_VERID_VERSION_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define SCG_PARAM_CLKPRES_MASK                   (0xFFU)
+#define SCG_PARAM_CLKPRES_SHIFT                  (0U)
+/*! CLKPRES - Clock Present
+ *  0b00000000-0b00000001..Reserved.
+ *  0bxxxxxx1x..System OSC (SOSC) is present.
+ *  0bxxxxx1xx..Slow IRC (SIRC) is present.
+ *  0bxxxx1xxx..Fast IRC (FIRC) is present.
+ *  0bxxx1xxxx..RTC OSC (ROSC) is present.
+ *  0bxx1xxxxx..Low Power FLL (LPFLL) is present.
+ */
+#define SCG_PARAM_CLKPRES(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_CLKPRES_SHIFT)) & SCG_PARAM_CLKPRES_MASK)
+#define SCG_PARAM_DIVPRES_MASK                   (0xF8000000U)
+#define SCG_PARAM_DIVPRES_SHIFT                  (27U)
+/*! DIVPRES - Divider Present
+ *  0bxxxx1..System DIVSLOW is present.
+ *  0bxxx1x..System DIVBUS is present.
+ *  0bxx1xx..System DIVEXT is present.
+ *  0b1xxxx..System DIVCORE is present.
+ */
+#define SCG_PARAM_DIVPRES(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_DIVPRES_SHIFT)) & SCG_PARAM_DIVPRES_MASK)
+/*! @} */
+
+/*! @name CSR - Clock Status Register */
+/*! @{ */
+#define SCG_CSR_DIVSLOW_MASK                     (0xFU)
+#define SCG_CSR_DIVSLOW_SHIFT                    (0U)
+/*! DIVSLOW - Slow Clock Divide Ratio
+ *  0b0000..Reserved
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_CSR_DIVSLOW(x)                       (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
+#define SCG_CSR_DIVBUS_MASK                      (0xF0U)
+#define SCG_CSR_DIVBUS_SHIFT                     (4U)
+/*! DIVBUS - Bus Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_CSR_DIVBUS(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVBUS_SHIFT)) & SCG_CSR_DIVBUS_MASK)
+#define SCG_CSR_DIVEXT_MASK                      (0xF00U)
+#define SCG_CSR_DIVEXT_SHIFT                     (8U)
+/*! DIVEXT - External Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_CSR_DIVEXT(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVEXT_SHIFT)) & SCG_CSR_DIVEXT_MASK)
+#define SCG_CSR_DIVCORE_MASK                     (0xF0000U)
+#define SCG_CSR_DIVCORE_SHIFT                    (16U)
+/*! DIVCORE - Core Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_CSR_DIVCORE(x)                       (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVCORE_SHIFT)) & SCG_CSR_DIVCORE_MASK)
+#define SCG_CSR_SCS_MASK                         (0xF000000U)
+#define SCG_CSR_SCS_SHIFT                        (24U)
+/*! SCS - System Clock Source
+ *  0b0000..Reserved
+ *  0b0001..System OSC (SOSC_CLK)
+ *  0b0010..Slow IRC (SIRC_CLK)
+ *  0b0011..Fast IRC (FIRC_CLK)
+ *  0b0100..RTC OSC (ROSC_CLK)
+ *  0b0101..Low Power FLL (LPFLL_CLK)
+ *  0b0110..Reserved
+ *  0b0111..Reserved
+ */
+#define SCG_CSR_SCS(x)                           (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK)
+/*! @} */
+
+/*! @name RCCR - Run Clock Control Register */
+/*! @{ */
+#define SCG_RCCR_DIVSLOW_MASK                    (0xFU)
+#define SCG_RCCR_DIVSLOW_SHIFT                   (0U)
+/*! DIVSLOW - Slow Clock Divide Ratio
+ *  0b0000..Reserved
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_RCCR_DIVSLOW(x)                      (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVSLOW_SHIFT)) & SCG_RCCR_DIVSLOW_MASK)
+#define SCG_RCCR_DIVBUS_MASK                     (0xF0U)
+#define SCG_RCCR_DIVBUS_SHIFT                    (4U)
+/*! DIVBUS - Bus Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_RCCR_DIVBUS(x)                       (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVBUS_SHIFT)) & SCG_RCCR_DIVBUS_MASK)
+#define SCG_RCCR_DIVEXT_MASK                     (0xF00U)
+#define SCG_RCCR_DIVEXT_SHIFT                    (8U)
+/*! DIVEXT - External Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_RCCR_DIVEXT(x)                       (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVEXT_SHIFT)) & SCG_RCCR_DIVEXT_MASK)
+#define SCG_RCCR_DIVCORE_MASK                    (0xF0000U)
+#define SCG_RCCR_DIVCORE_SHIFT                   (16U)
+/*! DIVCORE - Core Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_RCCR_DIVCORE(x)                      (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVCORE_SHIFT)) & SCG_RCCR_DIVCORE_MASK)
+#define SCG_RCCR_SCS_MASK                        (0x7000000U)
+#define SCG_RCCR_SCS_SHIFT                       (24U)
+/*! SCS - System Clock Source
+ *  0b000..Reserved
+ *  0b001..System OSC (SOSC_CLK)
+ *  0b010..Slow IRC (SIRC_CLK)
+ *  0b011..Fast IRC (FIRC_CLK)
+ *  0b100..RTC OSC (ROSC_CLK)
+ *  0b101..Low Power FLL (LPFLL_CLK)
+ *  0b110..Reserved
+ *  0b111..Reserved
+ */
+#define SCG_RCCR_SCS(x)                          (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK)
+/*! @} */
+
+/*! @name VCCR - VLPR Clock Control Register */
+/*! @{ */
+#define SCG_VCCR_DIVSLOW_MASK                    (0xFU)
+#define SCG_VCCR_DIVSLOW_SHIFT                   (0U)
+/*! DIVSLOW - Slow Clock Divide Ratio
+ *  0b0000..Reserved
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_VCCR_DIVSLOW(x)                      (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVSLOW_SHIFT)) & SCG_VCCR_DIVSLOW_MASK)
+#define SCG_VCCR_DIVBUS_MASK                     (0xF0U)
+#define SCG_VCCR_DIVBUS_SHIFT                    (4U)
+/*! DIVBUS - Bus Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_VCCR_DIVBUS(x)                       (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVBUS_SHIFT)) & SCG_VCCR_DIVBUS_MASK)
+#define SCG_VCCR_DIVEXT_MASK                     (0xF00U)
+#define SCG_VCCR_DIVEXT_SHIFT                    (8U)
+/*! DIVEXT - External Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_VCCR_DIVEXT(x)                       (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVEXT_SHIFT)) & SCG_VCCR_DIVEXT_MASK)
+#define SCG_VCCR_DIVCORE_MASK                    (0xF0000U)
+#define SCG_VCCR_DIVCORE_SHIFT                   (16U)
+/*! DIVCORE - Core Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_VCCR_DIVCORE(x)                      (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)
+#define SCG_VCCR_SCS_MASK                        (0xF000000U)
+#define SCG_VCCR_SCS_SHIFT                       (24U)
+/*! SCS - System Clock Source
+ *  0b0000..Reserved
+ *  0b0001..System OSC (SOSC_CLK)
+ *  0b0010..Slow IRC (SIRC_CLK)
+ *  0b0011..Reserved
+ *  0b0100..RTC OSC (ROSC_CLK)
+ *  0b0101..Reserved
+ *  0b0110..Reserved
+ *  0b0111..Reserved
+ */
+#define SCG_VCCR_SCS(x)                          (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_SCS_SHIFT)) & SCG_VCCR_SCS_MASK)
+/*! @} */
+
+/*! @name HCCR - HSRUN Clock Control Register */
+/*! @{ */
+#define SCG_HCCR_DIVSLOW_MASK                    (0xFU)
+#define SCG_HCCR_DIVSLOW_SHIFT                   (0U)
+/*! DIVSLOW - Slow Clock Divide Ratio
+ *  0b0000..Reserved
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_HCCR_DIVSLOW(x)                      (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVSLOW_SHIFT)) & SCG_HCCR_DIVSLOW_MASK)
+#define SCG_HCCR_DIVBUS_MASK                     (0xF0U)
+#define SCG_HCCR_DIVBUS_SHIFT                    (4U)
+/*! DIVBUS - Bus Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_HCCR_DIVBUS(x)                       (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVBUS_SHIFT)) & SCG_HCCR_DIVBUS_MASK)
+#define SCG_HCCR_DIVEXT_MASK                     (0xF00U)
+#define SCG_HCCR_DIVEXT_SHIFT                    (8U)
+/*! DIVEXT - External Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_HCCR_DIVEXT(x)                       (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVEXT_SHIFT)) & SCG_HCCR_DIVEXT_MASK)
+#define SCG_HCCR_DIVCORE_MASK                    (0xF0000U)
+#define SCG_HCCR_DIVCORE_SHIFT                   (16U)
+/*! DIVCORE - Core Clock Divide Ratio
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b0010..Divide-by-3
+ *  0b0011..Divide-by-4
+ *  0b0100..Divide-by-5
+ *  0b0101..Divide-by-6
+ *  0b0110..Divide-by-7
+ *  0b0111..Divide-by-8
+ *  0b1000..Divide-by-9
+ *  0b1001..Divide-by-10
+ *  0b1010..Divide-by-11
+ *  0b1011..Divide-by-12
+ *  0b1100..Divide-by-13
+ *  0b1101..Divide-by-14
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define SCG_HCCR_DIVCORE(x)                      (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_DIVCORE_SHIFT)) & SCG_HCCR_DIVCORE_MASK)
+#define SCG_HCCR_SCS_MASK                        (0xF000000U)
+#define SCG_HCCR_SCS_SHIFT                       (24U)
+/*! SCS - System Clock Source
+ *  0b0000..Reserved
+ *  0b0001..System OSC (SOSC_CLK)
+ *  0b0010..Slow IRC (SIRC_CLK)
+ *  0b0011..Fast IRC (FIRC_CLK)
+ *  0b0100..RTC OSC (ROSC_CLK)
+ *  0b0101..Low Power FLL (LPFLL_CLK)
+ *  0b0110..Reserved
+ *  0b0111..Reserved
+ */
+#define SCG_HCCR_SCS(x)                          (((uint32_t)(((uint32_t)(x)) << SCG_HCCR_SCS_SHIFT)) & SCG_HCCR_SCS_MASK)
+/*! @} */
+
+/*! @name CLKOUTCNFG - SCG CLKOUT Configuration Register */
+/*! @{ */
+#define SCG_CLKOUTCNFG_CLKOUTSEL_MASK            (0xF000000U)
+#define SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT           (24U)
+/*! CLKOUTSEL - SCG Clkout Select
+ *  0b0000..SCG EXTERNAL Clock
+ *  0b0001..System OSC (SOSC_CLK)
+ *  0b0010..Slow IRC (SIRC_CLK)
+ *  0b0011..Fast IRC (FIRC_CLK)
+ *  0b0100..RTC OSC (ROSC_CLK)
+ *  0b0101..Low Power FLL (LPFLL_CLK)
+ *  0b0110..Reserved
+ *  0b0111..Reserved
+ *  0b1111..Reserved
+ */
+#define SCG_CLKOUTCNFG_CLKOUTSEL(x)              (((uint32_t)(((uint32_t)(x)) << SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT)) & SCG_CLKOUTCNFG_CLKOUTSEL_MASK)
+/*! @} */
+
+/*! @name SOSCCSR - System OSC Control Status Register */
+/*! @{ */
+#define SCG_SOSCCSR_SOSCEN_MASK                  (0x1U)
+#define SCG_SOSCCSR_SOSCEN_SHIFT                 (0U)
+/*! SOSCEN - System OSC Enable
+ *  0b0..System OSC is disabled
+ *  0b1..System OSC is enabled
+ */
+#define SCG_SOSCCSR_SOSCEN(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK)
+#define SCG_SOSCCSR_SOSCSTEN_MASK                (0x2U)
+#define SCG_SOSCCSR_SOSCSTEN_SHIFT               (1U)
+/*! SOSCSTEN - System OSC Stop Enable
+ *  0b0..System OSC is disabled in Stop modes
+ *  0b1..System OSC is enabled in Stop modes if SOSCEN=1. In VLLS0, system oscillator is disabled even if SOSCSTEN=1 and SOSCEN=1.
+ */
+#define SCG_SOSCCSR_SOSCSTEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSTEN_SHIFT)) & SCG_SOSCCSR_SOSCSTEN_MASK)
+#define SCG_SOSCCSR_SOSCLPEN_MASK                (0x4U)
+#define SCG_SOSCCSR_SOSCLPEN_SHIFT               (2U)
+/*! SOSCLPEN - System OSC Low Power Enable
+ *  0b0..System OSC is disabled in VLP modes
+ *  0b1..System OSC is enabled in VLP modes
+ */
+#define SCG_SOSCCSR_SOSCLPEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCLPEN_SHIFT)) & SCG_SOSCCSR_SOSCLPEN_MASK)
+#define SCG_SOSCCSR_SOSCCM_MASK                  (0x10000U)
+#define SCG_SOSCCSR_SOSCCM_SHIFT                 (16U)
+/*! SOSCCM - System OSC Clock Monitor
+ *  0b0..System OSC Clock Monitor is disabled
+ *  0b1..System OSC Clock Monitor is enabled
+ */
+#define SCG_SOSCCSR_SOSCCM(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCM_SHIFT)) & SCG_SOSCCSR_SOSCCM_MASK)
+#define SCG_SOSCCSR_SOSCCMRE_MASK                (0x20000U)
+#define SCG_SOSCCSR_SOSCCMRE_SHIFT               (17U)
+/*! SOSCCMRE - System OSC Clock Monitor Reset Enable
+ *  0b0..Clock Monitor generates interrupt when error detected
+ *  0b1..Clock Monitor generates reset when error detected
+ */
+#define SCG_SOSCCSR_SOSCCMRE(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCMRE_SHIFT)) & SCG_SOSCCSR_SOSCCMRE_MASK)
+#define SCG_SOSCCSR_LK_MASK                      (0x800000U)
+#define SCG_SOSCCSR_LK_SHIFT                     (23U)
+/*! LK - Lock Register
+ *  0b0..This Control Status Register can be written.
+ *  0b1..This Control Status Register cannot be written.
+ */
+#define SCG_SOSCCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_LK_SHIFT)) & SCG_SOSCCSR_LK_MASK)
+#define SCG_SOSCCSR_SOSCVLD_MASK                 (0x1000000U)
+#define SCG_SOSCCSR_SOSCVLD_SHIFT                (24U)
+/*! SOSCVLD - System OSC Valid
+ *  0b0..System OSC is not enabled or clock is not valid
+ *  0b1..System OSC is enabled and output clock is valid
+ */
+#define SCG_SOSCCSR_SOSCVLD(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK)
+#define SCG_SOSCCSR_SOSCSEL_MASK                 (0x2000000U)
+#define SCG_SOSCCSR_SOSCSEL_SHIFT                (25U)
+/*! SOSCSEL - System OSC Selected
+ *  0b0..System OSC is not the system clock source
+ *  0b1..System OSC is the system clock source
+ */
+#define SCG_SOSCCSR_SOSCSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSEL_SHIFT)) & SCG_SOSCCSR_SOSCSEL_MASK)
+#define SCG_SOSCCSR_SOSCERR_MASK                 (0x4000000U)
+#define SCG_SOSCCSR_SOSCERR_SHIFT                (26U)
+/*! SOSCERR - System OSC Clock Error
+ *  0b0..System OSC Clock Monitor is disabled or has not detected an error
+ *  0b1..System OSC Clock Monitor is enabled and detected an error
+ */
+#define SCG_SOSCCSR_SOSCERR(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERR_SHIFT)) & SCG_SOSCCSR_SOSCERR_MASK)
+/*! @} */
+
+/*! @name SOSCDIV - System OSC Divide Register */
+/*! @{ */
+#define SCG_SOSCDIV_SOSCDIV1_MASK                (0x7U)
+#define SCG_SOSCDIV_SOSCDIV1_SHIFT               (0U)
+/*! SOSCDIV1 - System OSC Clock Divide 1
+ *  0b000..Output disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_SOSCDIV_SOSCDIV1(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV1_SHIFT)) & SCG_SOSCDIV_SOSCDIV1_MASK)
+#define SCG_SOSCDIV_SOSCDIV2_MASK                (0x700U)
+#define SCG_SOSCDIV_SOSCDIV2_SHIFT               (8U)
+/*! SOSCDIV2 - System OSC Clock Divide 2
+ *  0b000..Output disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_SOSCDIV_SOSCDIV2(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV2_SHIFT)) & SCG_SOSCDIV_SOSCDIV2_MASK)
+#define SCG_SOSCDIV_SOSCDIV3_MASK                (0x70000U)
+#define SCG_SOSCDIV_SOSCDIV3_SHIFT               (16U)
+/*! SOSCDIV3 - System OSC Clock Divide 3
+ *  0b000..Output disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_SOSCDIV_SOSCDIV3(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV3_SHIFT)) & SCG_SOSCDIV_SOSCDIV3_MASK)
+/*! @} */
+
+/*! @name SIRCCSR - Slow IRC Control Status Register */
+/*! @{ */
+#define SCG_SIRCCSR_SIRCEN_MASK                  (0x1U)
+#define SCG_SIRCCSR_SIRCEN_SHIFT                 (0U)
+/*! SIRCEN - Slow IRC Enable
+ *  0b0..Slow IRC is disabled
+ *  0b1..Slow IRC is enabled
+ */
+#define SCG_SIRCCSR_SIRCEN(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCEN_SHIFT)) & SCG_SIRCCSR_SIRCEN_MASK)
+#define SCG_SIRCCSR_SIRCSTEN_MASK                (0x2U)
+#define SCG_SIRCCSR_SIRCSTEN_SHIFT               (1U)
+/*! SIRCSTEN - Slow IRC Stop Enable
+ *  0b0..Slow IRC is disabled in Stop modes
+ *  0b1..Slow IRC is enabled in Stop modes
+ */
+#define SCG_SIRCCSR_SIRCSTEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSTEN_SHIFT)) & SCG_SIRCCSR_SIRCSTEN_MASK)
+#define SCG_SIRCCSR_SIRCLPEN_MASK                (0x4U)
+#define SCG_SIRCCSR_SIRCLPEN_SHIFT               (2U)
+/*! SIRCLPEN - Slow IRC Low Power Enable
+ *  0b0..Slow IRC is disabled in VLP modes
+ *  0b1..Slow IRC is enabled in VLP modes
+ */
+#define SCG_SIRCCSR_SIRCLPEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCLPEN_SHIFT)) & SCG_SIRCCSR_SIRCLPEN_MASK)
+#define SCG_SIRCCSR_LK_MASK                      (0x800000U)
+#define SCG_SIRCCSR_LK_SHIFT                     (23U)
+/*! LK - Lock Register
+ *  0b0..Control Status Register can be written.
+ *  0b1..Control Status Register cannot be written.
+ */
+#define SCG_SIRCCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_LK_SHIFT)) & SCG_SIRCCSR_LK_MASK)
+#define SCG_SIRCCSR_SIRCVLD_MASK                 (0x1000000U)
+#define SCG_SIRCCSR_SIRCVLD_SHIFT                (24U)
+/*! SIRCVLD - Slow IRC Valid
+ *  0b0..Slow IRC is not enabled or clock is not valid
+ *  0b1..Slow IRC is enabled and output clock is valid
+ */
+#define SCG_SIRCCSR_SIRCVLD(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK)
+#define SCG_SIRCCSR_SIRCSEL_MASK                 (0x2000000U)
+#define SCG_SIRCCSR_SIRCSEL_SHIFT                (25U)
+/*! SIRCSEL - Slow IRC Selected
+ *  0b0..Slow IRC is not the system clock source
+ *  0b1..Slow IRC is the system clock source
+ */
+#define SCG_SIRCCSR_SIRCSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSEL_SHIFT)) & SCG_SIRCCSR_SIRCSEL_MASK)
+/*! @} */
+
+/*! @name SIRCDIV - Slow IRC Divide Register */
+/*! @{ */
+#define SCG_SIRCDIV_SIRCDIV1_MASK                (0x7U)
+#define SCG_SIRCDIV_SIRCDIV1_SHIFT               (0U)
+/*! SIRCDIV1 - Slow IRC Clock Divide 1
+ *  0b000..Output disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_SIRCDIV_SIRCDIV1(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV1_SHIFT)) & SCG_SIRCDIV_SIRCDIV1_MASK)
+#define SCG_SIRCDIV_SIRCDIV2_MASK                (0x700U)
+#define SCG_SIRCDIV_SIRCDIV2_SHIFT               (8U)
+/*! SIRCDIV2 - Slow IRC Clock Divide 2
+ *  0b000..Output disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_SIRCDIV_SIRCDIV2(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV2_SHIFT)) & SCG_SIRCDIV_SIRCDIV2_MASK)
+#define SCG_SIRCDIV_SIRCDIV3_MASK                (0x70000U)
+#define SCG_SIRCDIV_SIRCDIV3_SHIFT               (16U)
+/*! SIRCDIV3 - Slow IRC Clock Divider 3
+ *  0b000..Output disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_SIRCDIV_SIRCDIV3(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV3_SHIFT)) & SCG_SIRCDIV_SIRCDIV3_MASK)
+/*! @} */
+
+/*! @name SIRCCFG - Slow IRC Configuration Register */
+/*! @{ */
+#define SCG_SIRCCFG_RANGE_MASK                   (0x1U)
+#define SCG_SIRCCFG_RANGE_SHIFT                  (0U)
+/*! RANGE - Frequency Range
+ *  0b0..Slow IRC low range clock (2MHz)
+ *  0b1..Slow IRC high range clock (8 MHz)
+ */
+#define SCG_SIRCCFG_RANGE(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCFG_RANGE_SHIFT)) & SCG_SIRCCFG_RANGE_MASK)
+/*! @} */
+
+/*! @name FIRCCSR - Fast IRC Control Status Register */
+/*! @{ */
+#define SCG_FIRCCSR_FIRCEN_MASK                  (0x1U)
+#define SCG_FIRCCSR_FIRCEN_SHIFT                 (0U)
+/*! FIRCEN - Fast IRC Enable
+ *  0b0..Fast IRC is disabled
+ *  0b1..Fast IRC is enabled
+ */
+#define SCG_FIRCCSR_FIRCEN(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK)
+#define SCG_FIRCCSR_FIRCSTEN_MASK                (0x2U)
+#define SCG_FIRCCSR_FIRCSTEN_SHIFT               (1U)
+/*! FIRCSTEN - Fast IRC Stop Enable
+ *  0b0..Fast IRC is disabled in Stop modes.
+ *  0b1..Fast IRC is enabled in Stop modes
+ */
+#define SCG_FIRCCSR_FIRCSTEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSTEN_SHIFT)) & SCG_FIRCCSR_FIRCSTEN_MASK)
+#define SCG_FIRCCSR_FIRCLPEN_MASK                (0x4U)
+#define SCG_FIRCCSR_FIRCLPEN_SHIFT               (2U)
+/*! FIRCLPEN - Fast IRC Low Power Enable
+ *  0b0..Fast IRC is disabled in VLP modes
+ *  0b1..Fast IRC is enabled in VLP modes
+ */
+#define SCG_FIRCCSR_FIRCLPEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCLPEN_SHIFT)) & SCG_FIRCCSR_FIRCLPEN_MASK)
+#define SCG_FIRCCSR_FIRCREGOFF_MASK              (0x8U)
+#define SCG_FIRCCSR_FIRCREGOFF_SHIFT             (3U)
+/*! FIRCREGOFF - Fast IRC Regulator Enable
+ *  0b0..Fast IRC Regulator is enabled.
+ *  0b1..Fast IRC Regulator is disabled.
+ */
+#define SCG_FIRCCSR_FIRCREGOFF(x)                (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCREGOFF_SHIFT)) & SCG_FIRCCSR_FIRCREGOFF_MASK)
+#define SCG_FIRCCSR_FIRCTREN_MASK                (0x100U)
+#define SCG_FIRCCSR_FIRCTREN_SHIFT               (8U)
+/*! FIRCTREN - Fast IRC Trim Enable
+ *  0b0..Disable trimming Fast IRC to an external clock source
+ *  0b1..Enable trimming Fast IRC to an external clock source
+ */
+#define SCG_FIRCCSR_FIRCTREN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTREN_SHIFT)) & SCG_FIRCCSR_FIRCTREN_MASK)
+#define SCG_FIRCCSR_FIRCTRUP_MASK                (0x200U)
+#define SCG_FIRCCSR_FIRCTRUP_SHIFT               (9U)
+/*! FIRCTRUP - Fast IRC Trim Update
+ *  0b0..Disable Fast IRC trimming updates
+ *  0b1..Enable Fast IRC trimming updates
+ */
+#define SCG_FIRCCSR_FIRCTRUP(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTRUP_SHIFT)) & SCG_FIRCCSR_FIRCTRUP_MASK)
+#define SCG_FIRCCSR_LK_MASK                      (0x800000U)
+#define SCG_FIRCCSR_LK_SHIFT                     (23U)
+/*! LK - Lock Register
+ *  0b0..Control Status Register can be written.
+ *  0b1..Control Status Register cannot be written.
+ */
+#define SCG_FIRCCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_LK_SHIFT)) & SCG_FIRCCSR_LK_MASK)
+#define SCG_FIRCCSR_FIRCVLD_MASK                 (0x1000000U)
+#define SCG_FIRCCSR_FIRCVLD_SHIFT                (24U)
+/*! FIRCVLD - Fast IRC Valid status
+ *  0b0..Fast IRC is not enabled or clock is not valid.
+ *  0b1..Fast IRC is enabled and output clock is valid. The clock is valid once there is an output clock from the FIRC analog.
+ */
+#define SCG_FIRCCSR_FIRCVLD(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCVLD_SHIFT)) & SCG_FIRCCSR_FIRCVLD_MASK)
+#define SCG_FIRCCSR_FIRCSEL_MASK                 (0x2000000U)
+#define SCG_FIRCCSR_FIRCSEL_SHIFT                (25U)
+/*! FIRCSEL - Fast IRC Selected status
+ *  0b0..Fast IRC is not the system clock source
+ *  0b1..Fast IRC is the system clock source
+ */
+#define SCG_FIRCCSR_FIRCSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK)
+#define SCG_FIRCCSR_FIRCERR_MASK                 (0x4000000U)
+#define SCG_FIRCCSR_FIRCERR_SHIFT                (26U)
+/*! FIRCERR - Fast IRC Clock Error
+ *  0b0..Error not detected with the Fast IRC trimming.
+ *  0b1..Error detected with the Fast IRC trimming.
+ */
+#define SCG_FIRCCSR_FIRCERR(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_SHIFT)) & SCG_FIRCCSR_FIRCERR_MASK)
+/*! @} */
+
+/*! @name FIRCDIV - Fast IRC Divide Register */
+/*! @{ */
+#define SCG_FIRCDIV_FIRCDIV1_MASK                (0x7U)
+#define SCG_FIRCDIV_FIRCDIV1_SHIFT               (0U)
+/*! FIRCDIV1 - Fast IRC Clock Divide 1
+ *  0b000..Output disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_FIRCDIV_FIRCDIV1(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV1_SHIFT)) & SCG_FIRCDIV_FIRCDIV1_MASK)
+#define SCG_FIRCDIV_FIRCDIV2_MASK                (0x700U)
+#define SCG_FIRCDIV_FIRCDIV2_SHIFT               (8U)
+/*! FIRCDIV2 - Fast IRC Clock Divide 2
+ *  0b000..Output disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_FIRCDIV_FIRCDIV2(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV2_SHIFT)) & SCG_FIRCDIV_FIRCDIV2_MASK)
+#define SCG_FIRCDIV_FIRCDIV3_MASK                (0x70000U)
+#define SCG_FIRCDIV_FIRCDIV3_SHIFT               (16U)
+/*! FIRCDIV3 - Fast IRC Clock Divider 3
+ *  0b000..Clock disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_FIRCDIV_FIRCDIV3(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV3_SHIFT)) & SCG_FIRCDIV_FIRCDIV3_MASK)
+/*! @} */
+
+/*! @name FIRCCFG - Fast IRC Configuration Register */
+/*! @{ */
+#define SCG_FIRCCFG_RANGE_MASK                   (0x3U)
+#define SCG_FIRCCFG_RANGE_SHIFT                  (0U)
+/*! RANGE - Frequency Range
+ *  0b00..Fast IRC is trimmed to 48 MHz
+ *  0b01..Fast IRC is trimmed to 52 MHz
+ *  0b10..Fast IRC is trimmed to 56 MHz
+ *  0b11..Fast IRC is trimmed to 60 MHz
+ */
+#define SCG_FIRCCFG_RANGE(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCFG_RANGE_SHIFT)) & SCG_FIRCCFG_RANGE_MASK)
+/*! @} */
+
+/*! @name FIRCTCFG - Fast IRC Trim Configuration Register */
+/*! @{ */
+#define SCG_FIRCTCFG_TRIMSRC_MASK                (0x3U)
+#define SCG_FIRCTCFG_TRIMSRC_SHIFT               (0U)
+/*! TRIMSRC - Trim Source
+ *  0b00..Reserved
+ *  0b01..Reserved
+ *  0b10..System OSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency slower than 32kHz.
+ *  0b11..RTC OSC (32.768 kHz)
+ */
+#define SCG_FIRCTCFG_TRIMSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMSRC_SHIFT)) & SCG_FIRCTCFG_TRIMSRC_MASK)
+#define SCG_FIRCTCFG_TRIMDIV_MASK                (0x700U)
+#define SCG_FIRCTCFG_TRIMDIV_SHIFT               (8U)
+/*! TRIMDIV - Fast IRC Trim Predivide
+ *  0b000..Divide by 1
+ *  0b001..Divide by 128
+ *  0b010..Divide by 256
+ *  0b011..Divide by 512
+ *  0b100..Divide by 1024
+ *  0b101..Divide by 2048
+ *  0b110..Reserved. Writing this value will result in Divide by 1.
+ *  0b111..Reserved. Writing this value will result in a Divide by 1.
+ */
+#define SCG_FIRCTCFG_TRIMDIV(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMDIV_SHIFT)) & SCG_FIRCTCFG_TRIMDIV_MASK)
+/*! @} */
+
+/*! @name FIRCSTAT - Fast IRC Status Register */
+/*! @{ */
+#define SCG_FIRCSTAT_TRIMFINE_MASK               (0x7FU)
+#define SCG_FIRCSTAT_TRIMFINE_SHIFT              (0U)
+#define SCG_FIRCSTAT_TRIMFINE(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMFINE_SHIFT)) & SCG_FIRCSTAT_TRIMFINE_MASK)
+#define SCG_FIRCSTAT_TRIMCOAR_MASK               (0x3F00U)
+#define SCG_FIRCSTAT_TRIMCOAR_SHIFT              (8U)
+#define SCG_FIRCSTAT_TRIMCOAR(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMCOAR_SHIFT)) & SCG_FIRCSTAT_TRIMCOAR_MASK)
+/*! @} */
+
+/*! @name ROSCCSR - RTC OSC Control Status Register */
+/*! @{ */
+#define SCG_ROSCCSR_ROSCCM_MASK                  (0x10000U)
+#define SCG_ROSCCSR_ROSCCM_SHIFT                 (16U)
+/*! ROSCCM - RTC OSC Clock Monitor
+ *  0b0..RTC OSC Clock Monitor is disabled
+ *  0b1..RTC OSC Clock Monitor is enabled
+ */
+#define SCG_ROSCCSR_ROSCCM(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCCM_SHIFT)) & SCG_ROSCCSR_ROSCCM_MASK)
+#define SCG_ROSCCSR_ROSCCMRE_MASK                (0x20000U)
+#define SCG_ROSCCSR_ROSCCMRE_SHIFT               (17U)
+/*! ROSCCMRE - RTC OSC Clock Monitor Reset Enable
+ *  0b0..Clock Monitor generates interrupt when error detected
+ *  0b1..Clock Monitor generates reset when error detected
+ */
+#define SCG_ROSCCSR_ROSCCMRE(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCCMRE_SHIFT)) & SCG_ROSCCSR_ROSCCMRE_MASK)
+#define SCG_ROSCCSR_LK_MASK                      (0x800000U)
+#define SCG_ROSCCSR_LK_SHIFT                     (23U)
+/*! LK - Lock Register
+ *  0b0..Control Status Register can be written.
+ *  0b1..Control Status Register cannot be written.
+ */
+#define SCG_ROSCCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_LK_SHIFT)) & SCG_ROSCCSR_LK_MASK)
+#define SCG_ROSCCSR_ROSCVLD_MASK                 (0x1000000U)
+#define SCG_ROSCCSR_ROSCVLD_SHIFT                (24U)
+/*! ROSCVLD - RTC OSC Valid
+ *  0b0..RTC OSC is not enabled or clock is not valid
+ *  0b1..RTC OSC is enabled and output clock is valid
+ */
+#define SCG_ROSCCSR_ROSCVLD(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCVLD_SHIFT)) & SCG_ROSCCSR_ROSCVLD_MASK)
+#define SCG_ROSCCSR_ROSCSEL_MASK                 (0x2000000U)
+#define SCG_ROSCCSR_ROSCSEL_SHIFT                (25U)
+/*! ROSCSEL - RTC OSC Selected
+ *  0b0..RTC OSC is not the system clock source
+ *  0b1..RTC OSC is the system clock source
+ */
+#define SCG_ROSCCSR_ROSCSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCSEL_SHIFT)) & SCG_ROSCCSR_ROSCSEL_MASK)
+#define SCG_ROSCCSR_ROSCERR_MASK                 (0x4000000U)
+#define SCG_ROSCCSR_ROSCERR_SHIFT                (26U)
+/*! ROSCERR - RTC OSC Clock Error
+ *  0b0..RTC OSC Clock Monitor is disabled or has not detected an error
+ *  0b1..RTC OSC Clock Monitor is enabled and detected an RTC loss of clock error
+ */
+#define SCG_ROSCCSR_ROSCERR(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCERR_SHIFT)) & SCG_ROSCCSR_ROSCERR_MASK)
+/*! @} */
+
+/*! @name LPFLLCSR - Low Power FLL Control Status Register */
+/*! @{ */
+#define SCG_LPFLLCSR_LPFLLEN_MASK                (0x1U)
+#define SCG_LPFLLCSR_LPFLLEN_SHIFT               (0U)
+/*! LPFLLEN - LPFLL Enable
+ *  0b0..LPFLL is disabled
+ *  0b1..LPFLL is enabled
+ */
+#define SCG_LPFLLCSR_LPFLLEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLEN_SHIFT)) & SCG_LPFLLCSR_LPFLLEN_MASK)
+#define SCG_LPFLLCSR_LPFLLSTEN_MASK              (0x2U)
+#define SCG_LPFLLCSR_LPFLLSTEN_SHIFT             (1U)
+/*! LPFLLSTEN - LPFLL Stop Enable
+ *  0b0..LPFLL is disabled in Stop modes.
+ *  0b1..LPFLL is enabled in Stop modes
+ */
+#define SCG_LPFLLCSR_LPFLLSTEN(x)                (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLSTEN_SHIFT)) & SCG_LPFLLCSR_LPFLLSTEN_MASK)
+#define SCG_LPFLLCSR_LPFLLTREN_MASK              (0x100U)
+#define SCG_LPFLLCSR_LPFLLTREN_SHIFT             (8U)
+/*! LPFLLTREN - LPFLL Trim Enable
+ *  0b0..Disable trimming LPFLL to an reference clock source
+ *  0b1..Enable trimming LPFLL to an reference clock source
+ */
+#define SCG_LPFLLCSR_LPFLLTREN(x)                (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLTREN_SHIFT)) & SCG_LPFLLCSR_LPFLLTREN_MASK)
+#define SCG_LPFLLCSR_LPFLLTRUP_MASK              (0x200U)
+#define SCG_LPFLLCSR_LPFLLTRUP_SHIFT             (9U)
+/*! LPFLLTRUP - LPFLL Trim Update
+ *  0b0..Disable LPFLL trimming updates. LPFLL frequency determined by AUTOTRIM written value.
+ *  0b1..Enable LPFLL trimming updates. LPFLL frequency determined by reference clock multiplication
+ */
+#define SCG_LPFLLCSR_LPFLLTRUP(x)                (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLTRUP_SHIFT)) & SCG_LPFLLCSR_LPFLLTRUP_MASK)
+#define SCG_LPFLLCSR_LPFLLTRMLOCK_MASK           (0x400U)
+#define SCG_LPFLLCSR_LPFLLTRMLOCK_SHIFT          (10U)
+/*! LPFLLTRMLOCK - LPFLL Trim LOCK
+ *  0b0..LPFLL not Locked
+ *  0b1..LPFLL trimmed and Locked
+ */
+#define SCG_LPFLLCSR_LPFLLTRMLOCK(x)             (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLTRMLOCK_SHIFT)) & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK)
+#define SCG_LPFLLCSR_LPFLLCM_MASK                (0x10000U)
+#define SCG_LPFLLCSR_LPFLLCM_SHIFT               (16U)
+/*! LPFLLCM - LPFLL Clock Monitor
+ *  0b0..LPFLL Clock Monitor is disabled
+ *  0b1..LPFLL Clock Monitor is enabled
+ */
+#define SCG_LPFLLCSR_LPFLLCM(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLCM_SHIFT)) & SCG_LPFLLCSR_LPFLLCM_MASK)
+#define SCG_LPFLLCSR_LPFLLCMRE_MASK              (0x20000U)
+#define SCG_LPFLLCSR_LPFLLCMRE_SHIFT             (17U)
+/*! LPFLLCMRE - LPFLL Clock Monitor Reset Enable
+ *  0b0..Clock Monitor generates interrupt when error detected
+ *  0b1..Clock Monitor generates reset when error detected
+ */
+#define SCG_LPFLLCSR_LPFLLCMRE(x)                (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLCMRE_SHIFT)) & SCG_LPFLLCSR_LPFLLCMRE_MASK)
+#define SCG_LPFLLCSR_LK_MASK                     (0x800000U)
+#define SCG_LPFLLCSR_LK_SHIFT                    (23U)
+/*! LK - Lock Register
+ *  0b0..Control Status Register can be written.
+ *  0b1..Control Status Register cannot be written.
+ */
+#define SCG_LPFLLCSR_LK(x)                       (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LK_SHIFT)) & SCG_LPFLLCSR_LK_MASK)
+#define SCG_LPFLLCSR_LPFLLVLD_MASK               (0x1000000U)
+#define SCG_LPFLLCSR_LPFLLVLD_SHIFT              (24U)
+/*! LPFLLVLD - LPFLL Valid
+ *  0b0..LPFLL is not enabled or clock is not valid.
+ *  0b1..LPFLL is enabled and output clock is valid.
+ */
+#define SCG_LPFLLCSR_LPFLLVLD(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLVLD_SHIFT)) & SCG_LPFLLCSR_LPFLLVLD_MASK)
+#define SCG_LPFLLCSR_LPFLLSEL_MASK               (0x2000000U)
+#define SCG_LPFLLCSR_LPFLLSEL_SHIFT              (25U)
+/*! LPFLLSEL - LPFLL Selected
+ *  0b0..LPFLL is not the system clock source
+ *  0b1..LPFLL is the system clock source
+ */
+#define SCG_LPFLLCSR_LPFLLSEL(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLSEL_SHIFT)) & SCG_LPFLLCSR_LPFLLSEL_MASK)
+#define SCG_LPFLLCSR_LPFLLERR_MASK               (0x4000000U)
+#define SCG_LPFLLCSR_LPFLLERR_SHIFT              (26U)
+/*! LPFLLERR - LPFLL Clock Error
+ *  0b0..Error not detected with the LPFLL trimming.
+ *  0b1..Error detected with the LPFLL trimming.
+ */
+#define SCG_LPFLLCSR_LPFLLERR(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLERR_SHIFT)) & SCG_LPFLLCSR_LPFLLERR_MASK)
+/*! @} */
+
+/*! @name LPFLLDIV - Low Power FLL Divide Register */
+/*! @{ */
+#define SCG_LPFLLDIV_LPFLLDIV1_MASK              (0x7U)
+#define SCG_LPFLLDIV_LPFLLDIV1_SHIFT             (0U)
+/*! LPFLLDIV1 - LPFLL Clock Divide 1
+ *  0b000..Output disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_LPFLLDIV_LPFLLDIV1(x)                (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLDIV_LPFLLDIV1_SHIFT)) & SCG_LPFLLDIV_LPFLLDIV1_MASK)
+#define SCG_LPFLLDIV_LPFLLDIV2_MASK              (0x700U)
+#define SCG_LPFLLDIV_LPFLLDIV2_SHIFT             (8U)
+/*! LPFLLDIV2 - LPFLL Clock Divide 2
+ *  0b000..Output disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_LPFLLDIV_LPFLLDIV2(x)                (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLDIV_LPFLLDIV2_SHIFT)) & SCG_LPFLLDIV_LPFLLDIV2_MASK)
+#define SCG_LPFLLDIV_LPFLLDIV3_MASK              (0x70000U)
+#define SCG_LPFLLDIV_LPFLLDIV3_SHIFT             (16U)
+/*! LPFLLDIV3 - LPFLL Clock Divide 3
+ *  0b000..Clock disabled
+ *  0b001..Divide by 1
+ *  0b010..Divide by 2
+ *  0b011..Divide by 4
+ *  0b100..Divide by 8
+ *  0b101..Divide by 16
+ *  0b110..Divide by 32
+ *  0b111..Divide by 64
+ */
+#define SCG_LPFLLDIV_LPFLLDIV3(x)                (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLDIV_LPFLLDIV3_SHIFT)) & SCG_LPFLLDIV_LPFLLDIV3_MASK)
+/*! @} */
+
+/*! @name LPFLLCFG - Low Power FLL Configuration Register */
+/*! @{ */
+#define SCG_LPFLLCFG_FSEL_MASK                   (0x3U)
+#define SCG_LPFLLCFG_FSEL_SHIFT                  (0U)
+/*! FSEL - Frequency Select
+ *  0b00..LPFLL is trimmed to 48 MHz.
+ *  0b01..LPFLL is trimmed to 72 MHz.
+ *  0b10..Reserved
+ *  0b11..Reserved
+ */
+#define SCG_LPFLLCFG_FSEL(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCFG_FSEL_SHIFT)) & SCG_LPFLLCFG_FSEL_MASK)
+/*! @} */
+
+/*! @name LPFLLTCFG - Low Power FLL Trim Configuration Register */
+/*! @{ */
+#define SCG_LPFLLTCFG_TRIMSRC_MASK               (0x3U)
+#define SCG_LPFLLTCFG_TRIMSRC_SHIFT              (0U)
+/*! TRIMSRC - Trim Source
+ *  0b00..SIRC
+ *  0b01..FIRC
+ *  0b10..System OSC
+ *  0b11..RTC OSC
+ */
+#define SCG_LPFLLTCFG_TRIMSRC(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLTCFG_TRIMSRC_SHIFT)) & SCG_LPFLLTCFG_TRIMSRC_MASK)
+#define SCG_LPFLLTCFG_TRIMDIV_MASK               (0x1F00U)
+#define SCG_LPFLLTCFG_TRIMDIV_SHIFT              (8U)
+#define SCG_LPFLLTCFG_TRIMDIV(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLTCFG_TRIMDIV_SHIFT)) & SCG_LPFLLTCFG_TRIMDIV_MASK)
+#define SCG_LPFLLTCFG_LOCKW2LSB_MASK             (0x10000U)
+#define SCG_LPFLLTCFG_LOCKW2LSB_SHIFT            (16U)
+/*! LOCKW2LSB - Lock LPFLL with 2 LSBS
+ *  0b0..LPFLL locks within 1LSB (0.4%)
+ *  0b1..LPFLL locks within 2LSB (0.8%)
+ */
+#define SCG_LPFLLTCFG_LOCKW2LSB(x)               (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLTCFG_LOCKW2LSB_SHIFT)) & SCG_LPFLLTCFG_LOCKW2LSB_MASK)
+/*! @} */
+
+/*! @name LPFLLSTAT - Low Power FLL Status Register */
+/*! @{ */
+#define SCG_LPFLLSTAT_AUTOTRIM_MASK              (0xFFU)
+#define SCG_LPFLLSTAT_AUTOTRIM_SHIFT             (0U)
+#define SCG_LPFLLSTAT_AUTOTRIM(x)                (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLSTAT_AUTOTRIM_SHIFT)) & SCG_LPFLLSTAT_AUTOTRIM_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SCG_Register_Masks */
+
+
+/* SCG - Peripheral instance base addresses */
+/** Peripheral SCG base address */
+#define SCG_BASE                                 (0x4002C000u)
+/** Peripheral SCG base pointer */
+#define SCG                                      ((SCG_Type *)SCG_BASE)
+/** Array initializer of SCG peripheral base addresses */
+#define SCG_BASE_ADDRS                           { SCG_BASE }
+/** Array initializer of SCG peripheral base pointers */
+#define SCG_BASE_PTRS                            { SCG }
+/** Interrupt vectors for the SCG peripheral type */
+#define SCG_IRQS                                 { SCG_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SEMA42 Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SEMA42_Peripheral_Access_Layer SEMA42 Peripheral Access Layer
+ * @{
+ */
+
+/** SEMA42 - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t GATE3;                              /**< Gate Register, offset: 0x0 */
+  __IO uint8_t GATE2;                              /**< Gate Register, offset: 0x1 */
+  __IO uint8_t GATE1;                              /**< Gate Register, offset: 0x2 */
+  __IO uint8_t GATE0;                              /**< Gate Register, offset: 0x3 */
+  __IO uint8_t GATE7;                              /**< Gate Register, offset: 0x4 */
+  __IO uint8_t GATE6;                              /**< Gate Register, offset: 0x5 */
+  __IO uint8_t GATE5;                              /**< Gate Register, offset: 0x6 */
+  __IO uint8_t GATE4;                              /**< Gate Register, offset: 0x7 */
+  __IO uint8_t GATE11;                             /**< Gate Register, offset: 0x8 */
+  __IO uint8_t GATE10;                             /**< Gate Register, offset: 0x9 */
+  __IO uint8_t GATE9;                              /**< Gate Register, offset: 0xA */
+  __IO uint8_t GATE8;                              /**< Gate Register, offset: 0xB */
+  __IO uint8_t GATE15;                             /**< Gate Register, offset: 0xC */
+  __IO uint8_t GATE14;                             /**< Gate Register, offset: 0xD */
+  __IO uint8_t GATE13;                             /**< Gate Register, offset: 0xE */
+  __IO uint8_t GATE12;                             /**< Gate Register, offset: 0xF */
+       uint8_t RESERVED_0[50];
+  union {                                          /* offset: 0x42 */
+    __I  uint16_t RSTGT_R;                           /**< Reset Gate Read, offset: 0x42 */
+    __O  uint16_t RSTGT_W;                           /**< Reset Gate Write, offset: 0x42 */
+  };
+} SEMA42_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SEMA42 Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SEMA42_Register_Masks SEMA42 Register Masks
+ * @{
+ */
+
+/*! @name GATE3 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE3_GTFSM_MASK                  (0xFU)
+#define SEMA42_GATE3_GTFSM_SHIFT                 (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE3_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE3_GTFSM_SHIFT)) & SEMA42_GATE3_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE2 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE2_GTFSM_MASK                  (0xFU)
+#define SEMA42_GATE2_GTFSM_SHIFT                 (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE2_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE2_GTFSM_SHIFT)) & SEMA42_GATE2_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE1 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE1_GTFSM_MASK                  (0xFU)
+#define SEMA42_GATE1_GTFSM_SHIFT                 (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE1_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE1_GTFSM_SHIFT)) & SEMA42_GATE1_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE0 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE0_GTFSM_MASK                  (0xFU)
+#define SEMA42_GATE0_GTFSM_SHIFT                 (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE0_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE0_GTFSM_SHIFT)) & SEMA42_GATE0_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE7 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE7_GTFSM_MASK                  (0xFU)
+#define SEMA42_GATE7_GTFSM_SHIFT                 (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE7_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE7_GTFSM_SHIFT)) & SEMA42_GATE7_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE6 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE6_GTFSM_MASK                  (0xFU)
+#define SEMA42_GATE6_GTFSM_SHIFT                 (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE6_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE6_GTFSM_SHIFT)) & SEMA42_GATE6_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE5 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE5_GTFSM_MASK                  (0xFU)
+#define SEMA42_GATE5_GTFSM_SHIFT                 (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE5_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE5_GTFSM_SHIFT)) & SEMA42_GATE5_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE4 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE4_GTFSM_MASK                  (0xFU)
+#define SEMA42_GATE4_GTFSM_SHIFT                 (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE4_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE4_GTFSM_SHIFT)) & SEMA42_GATE4_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE11 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE11_GTFSM_MASK                 (0xFU)
+#define SEMA42_GATE11_GTFSM_SHIFT                (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE11_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE11_GTFSM_SHIFT)) & SEMA42_GATE11_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE10 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE10_GTFSM_MASK                 (0xFU)
+#define SEMA42_GATE10_GTFSM_SHIFT                (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE10_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE10_GTFSM_SHIFT)) & SEMA42_GATE10_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE9 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE9_GTFSM_MASK                  (0xFU)
+#define SEMA42_GATE9_GTFSM_SHIFT                 (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE9_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE9_GTFSM_SHIFT)) & SEMA42_GATE9_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE8 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE8_GTFSM_MASK                  (0xFU)
+#define SEMA42_GATE8_GTFSM_SHIFT                 (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE8_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE8_GTFSM_SHIFT)) & SEMA42_GATE8_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE15 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE15_GTFSM_MASK                 (0xFU)
+#define SEMA42_GATE15_GTFSM_SHIFT                (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE15_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE15_GTFSM_SHIFT)) & SEMA42_GATE15_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE14 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE14_GTFSM_MASK                 (0xFU)
+#define SEMA42_GATE14_GTFSM_SHIFT                (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE14_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE14_GTFSM_SHIFT)) & SEMA42_GATE14_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE13 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE13_GTFSM_MASK                 (0xFU)
+#define SEMA42_GATE13_GTFSM_SHIFT                (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE13_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE13_GTFSM_SHIFT)) & SEMA42_GATE13_GTFSM_MASK)
+/*! @} */
+
+/*! @name GATE12 - Gate Register */
+/*! @{ */
+#define SEMA42_GATE12_GTFSM_MASK                 (0xFU)
+#define SEMA42_GATE12_GTFSM_SHIFT                (0U)
+/*! GTFSM - GTFSM
+ *  0b0000..The gate is unlocked (free).
+ *  0b0001..The gate has been locked by processor 0.
+ *  0b0010..The gate has been locked by processor 1.
+ *  0b0011..The gate has been locked by processor 2.
+ *  0b0100..The gate has been locked by processor 3.
+ *  0b0101..The gate has been locked by processor 4.
+ *  0b0110..The gate has been locked by processor 5.
+ *  0b0111..The gate has been locked by processor 6.
+ *  0b1000..The gate has been locked by processor 7.
+ *  0b1001..The gate has been locked by processor 8.
+ *  0b1010..The gate has been locked by processor 9.
+ *  0b1011..The gate has been locked by processor 10.
+ *  0b1100..The gate has been locked by processor 11.
+ *  0b1101..The gate has been locked by processor 12.
+ *  0b1110..The gate has been locked by processor 13.
+ *  0b1111..The gate has been locked by processor 14.
+ */
+#define SEMA42_GATE12_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE12_GTFSM_SHIFT)) & SEMA42_GATE12_GTFSM_MASK)
+/*! @} */
+
+/*! @name RSTGT_R - Reset Gate Read */
+/*! @{ */
+#define SEMA42_RSTGT_R_RSTGTN_MASK               (0xFFU)
+#define SEMA42_RSTGT_R_RSTGTN_SHIFT              (0U)
+#define SEMA42_RSTGT_R_RSTGTN(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGTN_SHIFT)) & SEMA42_RSTGT_R_RSTGTN_MASK)
+#define SEMA42_RSTGT_R_RSTGMS_MASK               (0xF00U)
+#define SEMA42_RSTGT_R_RSTGMS_SHIFT              (8U)
+#define SEMA42_RSTGT_R_RSTGMS(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK)
+#define SEMA42_RSTGT_R_RSTGSM_MASK               (0x3000U)
+#define SEMA42_RSTGT_R_RSTGSM_SHIFT              (12U)
+/*! RSTGSM - RSTGSM
+ *  0b00..Idle, waiting for the first data pattern write.
+ *  0b01..Waiting for the second data pattern write.
+ *  0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, this machine returns to the idle (waiting for first data pattern write) state. The "01" state persists for only one clock cycle. Software cannot observe this state.
+ *  0b11..This state encoding is never used and therefore reserved.
+ */
+#define SEMA42_RSTGT_R_RSTGSM(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGSM_SHIFT)) & SEMA42_RSTGT_R_RSTGSM_MASK)
+#define SEMA42_RSTGT_R_ROZ_MASK                  (0xC000U)
+#define SEMA42_RSTGT_R_ROZ_SHIFT                 (14U)
+#define SEMA42_RSTGT_R_ROZ(x)                    (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_ROZ_SHIFT)) & SEMA42_RSTGT_R_ROZ_MASK)
+/*! @} */
+
+/*! @name RSTGT_W - Reset Gate Write */
+/*! @{ */
+#define SEMA42_RSTGT_W_RSTGTN_MASK               (0xFFU)
+#define SEMA42_RSTGT_W_RSTGTN_SHIFT              (0U)
+#define SEMA42_RSTGT_W_RSTGTN(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGTN_SHIFT)) & SEMA42_RSTGT_W_RSTGTN_MASK)
+#define SEMA42_RSTGT_W_RSTGDP_MASK               (0xFF00U)
+#define SEMA42_RSTGT_W_RSTGDP_SHIFT              (8U)
+#define SEMA42_RSTGT_W_RSTGDP(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGDP_SHIFT)) & SEMA42_RSTGT_W_RSTGDP_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SEMA42_Register_Masks */
+
+
+/* SEMA42 - Peripheral instance base addresses */
+/** Peripheral SEMA420 base address */
+#define SEMA420_BASE                             (0x4001B000u)
+/** Peripheral SEMA420 base pointer */
+#define SEMA420                                  ((SEMA42_Type *)SEMA420_BASE)
+/** Peripheral SEMA421 base address */
+#define SEMA421_BASE                             (0x4101B000u)
+/** Peripheral SEMA421 base pointer */
+#define SEMA421                                  ((SEMA42_Type *)SEMA421_BASE)
+/** Array initializer of SEMA42 peripheral base addresses */
+#define SEMA42_BASE_ADDRS                        { SEMA420_BASE, SEMA421_BASE }
+/** Array initializer of SEMA42 peripheral base pointers */
+#define SEMA42_BASE_PTRS                         { SEMA420, SEMA421 }
+
+/*!
+ * @}
+ */ /* end of group SEMA42_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[4];
+  __IO uint32_t CHIPCTRL;                          /**< Chip Control Register, offset: 0x4 */
+       uint8_t RESERVED_1[28];
+  __I  uint32_t SDID;                              /**< System Device Identification Register, offset: 0x24 */
+       uint8_t RESERVED_2[36];
+  __IO uint32_t FCFG1;                             /**< Flash Configuration Register 1, offset: 0x4C */
+  __I  uint32_t FCFG2;                             /**< Flash Configuration Register 2, offset: 0x50 */
+       uint8_t RESERVED_3[4];
+  __I  uint32_t UIDH;                              /**< Unique Identification Register High, offset: 0x58 */
+  __I  uint32_t UIDM;                              /**< Unique Identification Register Mid Middle, offset: 0x5C */
+  __I  uint32_t UIDL;                              /**< Unique Identification Register Mid Low, offset: 0x60 */
+  __I  uint32_t RFADDRL;                           /**< RF Mac Address Low, offset: 0x64 */
+  __I  uint32_t RFADDRH;                           /**< RF MAC Address High, offset: 0x68 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t MISC2;                             /**< MISC2 Register, offset: 0x70 */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/*! @name CHIPCTRL - Chip Control Register */
+/*! @{ */
+#define SIM_CHIPCTRL_FBSL_MASK                   (0x300U)
+#define SIM_CHIPCTRL_FBSL_SHIFT                  (8U)
+/*! FBSL - FLEXBUS security level
+ *  0b00..All off-chip access(instruction and data) via the Flexbus or sdram are disallowed
+ *  0b01..All off-chip access(instruction and data) via the Flexbus or sdram are disallowed
+ *  0b10..off-chip instruction access are disallowed, data access are allowed
+ *  0b11..off-chip instruction access and data access are allowed
+ */
+#define SIM_CHIPCTRL_FBSL(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTRL_FBSL_SHIFT)) & SIM_CHIPCTRL_FBSL_MASK)
+/*! @} */
+
+/*! @name SDID - System Device Identification Register */
+/*! @{ */
+#define SIM_SDID_PINID_MASK                      (0xFU)
+#define SIM_SDID_PINID_SHIFT                     (0U)
+/*! PINID - PINID
+ *  0b1000..176-pin
+ *  0b1101..191-pin
+ */
+#define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
+#define SIM_SDID_DIEID_MASK                      (0xF80U)
+#define SIM_SDID_DIEID_SHIFT                     (7U)
+#define SIM_SDID_DIEID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK                      (0xF000U)
+#define SIM_SDID_REVID_SHIFT                     (12U)
+#define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
+#define SIM_SDID_SERIESID_MASK                   (0xF00000U)
+#define SIM_SDID_SERIESID_SHIFT                  (20U)
+#define SIM_SDID_SERIESID(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK                   (0xF000000U)
+#define SIM_SDID_SUBFAMID_SHIFT                  (24U)
+/*! SUBFAMID - SUBFAMID
+ *  0b0010..02
+ *  0b0011..03
+ *  0b0100..04
+ */
+#define SIM_SDID_SUBFAMID(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMID_MASK                      (0xF0000000U)
+#define SIM_SDID_FAMID_SHIFT                     (28U)
+/*! FAMID - FAMID
+ *  0b0000..RV32M1
+ */
+#define SIM_SDID_FAMID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
+/*! @} */
+
+/*! @name FCFG1 - Flash Configuration Register 1 */
+/*! @{ */
+#define SIM_FCFG1_FLASHDIS_MASK                  (0x1U)
+#define SIM_FCFG1_FLASHDIS_SHIFT                 (0U)
+/*! FLASHDIS - Flash disable
+ *  0b0..Flash is enabled
+ *  0b1..Flash is disabled
+ */
+#define SIM_FCFG1_FLASHDIS(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
+#define SIM_FCFG1_FLASHDOZE_MASK                 (0x2U)
+#define SIM_FCFG1_FLASHDOZE_SHIFT                (1U)
+/*! FLASHDOZE - Flash Doze
+ *  0b0..Flash remains enabled during Doze mode
+ *  0b1..Flash is disabled for the duration of Doze mode
+ */
+#define SIM_FCFG1_FLASHDOZE(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
+#define SIM_FCFG1_FLSAUTODISEN_MASK              (0x4U)
+#define SIM_FCFG1_FLSAUTODISEN_SHIFT             (2U)
+/*! FLSAUTODISEN - Flash auto disable enabled.
+ *  0b0..Disable flash auto disable function
+ *  0b1..Enable flash auto disable function
+ */
+#define SIM_FCFG1_FLSAUTODISEN(x)                (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLSAUTODISEN_SHIFT)) & SIM_FCFG1_FLSAUTODISEN_MASK)
+#define SIM_FCFG1_FLSAUTODISWD_MASK              (0x3FF8U)
+#define SIM_FCFG1_FLSAUTODISWD_SHIFT             (3U)
+#define SIM_FCFG1_FLSAUTODISWD(x)                (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLSAUTODISWD_SHIFT)) & SIM_FCFG1_FLSAUTODISWD_MASK)
+#define SIM_FCFG1_CORE1_SRAMSIZE_MASK            (0xF0000U)
+#define SIM_FCFG1_CORE1_SRAMSIZE_SHIFT           (16U)
+/*! CORE1_SRAMSIZE
+ *  0b1001..CM0+ has 128 KB SRAM
+ */
+#define SIM_FCFG1_CORE1_SRAMSIZE(x)              (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_CORE1_SRAMSIZE_SHIFT)) & SIM_FCFG1_CORE1_SRAMSIZE_MASK)
+#define SIM_FCFG1_CORE0_SRAMSIZE_MASK            (0xF00000U)
+#define SIM_FCFG1_CORE0_SRAMSIZE_SHIFT           (20U)
+/*! CORE0_SRAMSIZE
+ *  0b1010..CM4 has 256 KB SRAM
+ */
+#define SIM_FCFG1_CORE0_SRAMSIZE(x)              (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_CORE0_SRAMSIZE_SHIFT)) & SIM_FCFG1_CORE0_SRAMSIZE_MASK)
+#define SIM_FCFG1_CORE1_PFSIZE_MASK              (0xF000000U)
+#define SIM_FCFG1_CORE1_PFSIZE_SHIFT             (24U)
+/*! CORE1_PFSIZE
+ *  0b1010..CM0+ has 256 KB flash size.
+ */
+#define SIM_FCFG1_CORE1_PFSIZE(x)                (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_CORE1_PFSIZE_SHIFT)) & SIM_FCFG1_CORE1_PFSIZE_MASK)
+#define SIM_FCFG1_CORE0_PFSIZE_MASK              (0xF0000000U)
+#define SIM_FCFG1_CORE0_PFSIZE_SHIFT             (28U)
+/*! CORE0_PFSIZE
+ *  0b1100..CM4 has 1 MB flash size.
+ */
+#define SIM_FCFG1_CORE0_PFSIZE(x)                (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_CORE0_PFSIZE_SHIFT)) & SIM_FCFG1_CORE0_PFSIZE_MASK)
+/*! @} */
+
+/*! @name FCFG2 - Flash Configuration Register 2 */
+/*! @{ */
+#define SIM_FCFG2_MAXADDR2_MASK                  (0x3F0000U)
+#define SIM_FCFG2_MAXADDR2_SHIFT                 (16U)
+#define SIM_FCFG2_MAXADDR2(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR2_SHIFT)) & SIM_FCFG2_MAXADDR2_MASK)
+#define SIM_FCFG2_MAXADDR01_MASK                 (0x7F000000U)
+#define SIM_FCFG2_MAXADDR01_SHIFT                (24U)
+#define SIM_FCFG2_MAXADDR01(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR01_SHIFT)) & SIM_FCFG2_MAXADDR01_MASK)
+#define SIM_FCFG2_SWAP_MASK                      (0x80000000U)
+#define SIM_FCFG2_SWAP_SHIFT                     (31U)
+/*! SWAP - SWAP
+ *  0b0..Logical P-flash Block 0 is located at relative address 0x0000
+ *  0b1..Logical P-flash Block 1 is located at relative address 0x0000
+ */
+#define SIM_FCFG2_SWAP(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_SWAP_SHIFT)) & SIM_FCFG2_SWAP_MASK)
+/*! @} */
+
+/*! @name UIDH - Unique Identification Register High */
+/*! @{ */
+#define SIM_UIDH_UID_MASK                        (0xFFFFU)
+#define SIM_UIDH_UID_SHIFT                       (0U)
+#define SIM_UIDH_UID(x)                          (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
+/*! @} */
+
+/*! @name UIDM - Unique Identification Register Mid Middle */
+/*! @{ */
+#define SIM_UIDM_UID_MASK                        (0xFFFFFFFFU)
+#define SIM_UIDM_UID_SHIFT                       (0U)
+#define SIM_UIDM_UID(x)                          (((uint32_t)(((uint32_t)(x)) << SIM_UIDM_UID_SHIFT)) & SIM_UIDM_UID_MASK)
+/*! @} */
+
+/*! @name UIDL - Unique Identification Register Mid Low */
+/*! @{ */
+#define SIM_UIDL_UID_MASK                        (0xFFFFFFFFU)
+#define SIM_UIDL_UID_SHIFT                       (0U)
+#define SIM_UIDL_UID(x)                          (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
+/*! @} */
+
+/*! @name RFADDRL - RF Mac Address Low */
+/*! @{ */
+#define SIM_RFADDRL_MACADDR0_MASK                (0xFFU)
+#define SIM_RFADDRL_MACADDR0_SHIFT               (0U)
+#define SIM_RFADDRL_MACADDR0(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_RFADDRL_MACADDR0_SHIFT)) & SIM_RFADDRL_MACADDR0_MASK)
+#define SIM_RFADDRL_MACADDR1_MASK                (0xFF00U)
+#define SIM_RFADDRL_MACADDR1_SHIFT               (8U)
+#define SIM_RFADDRL_MACADDR1(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_RFADDRL_MACADDR1_SHIFT)) & SIM_RFADDRL_MACADDR1_MASK)
+#define SIM_RFADDRL_MACADDR2_MASK                (0xFF0000U)
+#define SIM_RFADDRL_MACADDR2_SHIFT               (16U)
+#define SIM_RFADDRL_MACADDR2(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_RFADDRL_MACADDR2_SHIFT)) & SIM_RFADDRL_MACADDR2_MASK)
+#define SIM_RFADDRL_MACADDR3_MASK                (0xFF000000U)
+#define SIM_RFADDRL_MACADDR3_SHIFT               (24U)
+#define SIM_RFADDRL_MACADDR3(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_RFADDRL_MACADDR3_SHIFT)) & SIM_RFADDRL_MACADDR3_MASK)
+/*! @} */
+
+/*! @name RFADDRH - RF MAC Address High */
+/*! @{ */
+#define SIM_RFADDRH_MACADDR4_MASK                (0xFFU)
+#define SIM_RFADDRH_MACADDR4_SHIFT               (0U)
+#define SIM_RFADDRH_MACADDR4(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_RFADDRH_MACADDR4_SHIFT)) & SIM_RFADDRH_MACADDR4_MASK)
+/*! @} */
+
+/*! @name MISC2 - MISC2 Register */
+/*! @{ */
+#define SIM_MISC2_SYSTICK_CLK_EN_MASK            (0x1U)
+#define SIM_MISC2_SYSTICK_CLK_EN_SHIFT           (0U)
+/*! systick_clk_en - Systick clock enable
+ *  0b0..Systick clock is disabled
+ *  0b1..Systick clock is enabled
+ */
+#define SIM_MISC2_SYSTICK_CLK_EN(x)              (((uint32_t)(((uint32_t)(x)) << SIM_MISC2_SYSTICK_CLK_EN_SHIFT)) & SIM_MISC2_SYSTICK_CLK_EN_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE                                 (0x40026000u)
+/** Peripheral SIM base pointer */
+#define SIM                                      ((SIM_Type *)SIM_BASE)
+/** Array initializer of SIM peripheral base addresses */
+#define SIM_BASE_ADDRS                           { SIM_BASE }
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASE_PTRS                            { SIM }
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __IO uint32_t PMPROT;                            /**< Power Mode Protection register, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t PMCTRL;                            /**< Power Mode Control register, offset: 0x10 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t PMSTAT;                            /**< Power Mode Status register, offset: 0x18 */
+       uint8_t RESERVED_2[4];
+  __I  uint32_t SRS;                               /**< System Reset Status, offset: 0x20 */
+  __IO uint32_t RPC;                               /**< Reset Pin Control, offset: 0x24 */
+  __IO uint32_t SSRS;                              /**< Sticky System Reset Status, offset: 0x28 */
+  __IO uint32_t SRIE;                              /**< System Reset Interrupt Enable, offset: 0x2C */
+  __IO uint32_t SRIF;                              /**< System Reset Interrupt Flag, offset: 0x30 */
+       uint8_t RESERVED_3[12];
+  __IO uint32_t MR;                                /**< Mode Register, offset: 0x40 */
+       uint8_t RESERVED_4[12];
+  __IO uint32_t FM;                                /**< Force Mode Register, offset: 0x50 */
+       uint8_t RESERVED_5[12];
+  __IO uint32_t SRAMLPR;                           /**< SRAM Low Power Register, offset: 0x60 */
+  __IO uint32_t SRAMDSR;                           /**< SRAM Deep Sleep Register, offset: 0x64 */
+} SMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define SMC_VERID_FEATURE_MASK                   (0xFFFFU)
+#define SMC_VERID_FEATURE_SHIFT                  (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000010101011..Default features supported
+ */
+#define SMC_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << SMC_VERID_FEATURE_SHIFT)) & SMC_VERID_FEATURE_MASK)
+#define SMC_VERID_MINOR_MASK                     (0xFF0000U)
+#define SMC_VERID_MINOR_SHIFT                    (16U)
+#define SMC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_VERID_MINOR_SHIFT)) & SMC_VERID_MINOR_MASK)
+#define SMC_VERID_MAJOR_MASK                     (0xFF000000U)
+#define SMC_VERID_MAJOR_SHIFT                    (24U)
+#define SMC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_VERID_MAJOR_SHIFT)) & SMC_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define SMC_PARAM_PWRD_INDPT_MASK                (0x1U)
+#define SMC_PARAM_PWRD_INDPT_SHIFT               (0U)
+#define SMC_PARAM_PWRD_INDPT(x)                  (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_PWRD_INDPT_SHIFT)) & SMC_PARAM_PWRD_INDPT_MASK)
+/*! @} */
+
+/*! @name PMPROT - Power Mode Protection register */
+/*! @{ */
+#define SMC_PMPROT_AVLLS_MASK                    (0x3U)
+#define SMC_PMPROT_AVLLS_SHIFT                   (0U)
+/*! AVLLS - Allow Very-Low-Leakage Stop Mode
+ *  0b00..VLLS mode is not allowed
+ *  0b01..VLLS0/1 mode is allowed
+ *  0b10..VLLS2/3 mode is allowed
+ *  0b11..VLLS0/1/2/3 mode is allowed
+ */
+#define SMC_PMPROT_AVLLS(x)                      (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
+#define SMC_PMPROT_ALLS_MASK                     (0x8U)
+#define SMC_PMPROT_ALLS_SHIFT                    (3U)
+/*! ALLS - Allow Low-Leakage Stop Mode
+ *  0b0..LLS is not allowed
+ *  0b1..LLS is allowed
+ */
+#define SMC_PMPROT_ALLS(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
+#define SMC_PMPROT_AVLP_MASK                     (0x20U)
+#define SMC_PMPROT_AVLP_SHIFT                    (5U)
+/*! AVLP - Allow Very-Low-Power Modes
+ *  0b0..VLPR, VLPW, and VLPS are not allowed.
+ *  0b1..VLPR, VLPW, and VLPS are allowed.
+ */
+#define SMC_PMPROT_AVLP(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
+#define SMC_PMPROT_AHSRUN_MASK                   (0x80U)
+#define SMC_PMPROT_AHSRUN_SHIFT                  (7U)
+/*! AHSRUN - Allow High Speed Run mode
+ *  0b0..HSRUN is not allowed
+ *  0b1..HSRUN is allowed
+ */
+#define SMC_PMPROT_AHSRUN(x)                     (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK)
+/*! @} */
+
+/*! @name PMCTRL - Power Mode Control register */
+/*! @{ */
+#define SMC_PMCTRL_STOPM_MASK                    (0x7U)
+#define SMC_PMCTRL_STOPM_SHIFT                   (0U)
+/*! STOPM - Stop Mode Control
+ *  0b000..Normal Stop (STOP)
+ *  0b001..Reserved
+ *  0b010..Very-Low-Power Stop (VLPS)
+ *  0b011..Low-Leakage Stop (LLS)
+ *  0b100..Very-Low-Leakage Stop with SRAM retention(VLLS2/3)
+ *  0b101..Reserved
+ *  0b110..Very-Low-Leakage Stop without SRAM retention (VLLS0/1)
+ *  0b111..Reserved
+ */
+#define SMC_PMCTRL_STOPM(x)                      (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_RUNM_MASK                     (0x300U)
+#define SMC_PMCTRL_RUNM_SHIFT                    (8U)
+/*! RUNM - Run Mode Control
+ *  0b00..Normal Run mode (RUN)
+ *  0b01..Reserved
+ *  0b10..Very-Low-Power Run mode (VLPR)
+ *  0b11..High Speed Run mode (HSRUN)
+ */
+#define SMC_PMCTRL_RUNM(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
+#define SMC_PMCTRL_PSTOPO_MASK                   (0x30000U)
+#define SMC_PMCTRL_PSTOPO_SHIFT                  (16U)
+/*! PSTOPO - Partial Stop Option
+ *  0b00..STOP - Normal Stop mode
+ *  0b01..PSTOP1 - Partial Stop with system and bus clock disabled
+ *  0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
+ *  0b11..PSTOP3 - Partial Stop with system clock enabled and bus clock enabled
+ */
+#define SMC_PMCTRL_PSTOPO(x)                     (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_PSTOPO_SHIFT)) & SMC_PMCTRL_PSTOPO_MASK)
+/*! @} */
+
+/*! @name PMSTAT - Power Mode Status register */
+/*! @{ */
+#define SMC_PMSTAT_PMSTAT_MASK                   (0xFFU)
+#define SMC_PMSTAT_PMSTAT_SHIFT                  (0U)
+/*! PMSTAT - Power Mode Status
+ *  0b00000001..Current power mode is RUN.
+ *  0b00000010..Current power mode is any STOP mode.
+ *  0b00000100..Current power mode is VLPR.
+ *  0b10000000..Current power mode is HSRUN
+ */
+#define SMC_PMSTAT_PMSTAT(x)                     (((uint32_t)(((uint32_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
+#define SMC_PMSTAT_STOPSTAT_MASK                 (0xFF000000U)
+#define SMC_PMSTAT_STOPSTAT_SHIFT                (24U)
+#define SMC_PMSTAT_STOPSTAT(x)                   (((uint32_t)(((uint32_t)(x)) << SMC_PMSTAT_STOPSTAT_SHIFT)) & SMC_PMSTAT_STOPSTAT_MASK)
+/*! @} */
+
+/*! @name SRS - System Reset Status */
+/*! @{ */
+#define SMC_SRS_WAKEUP_MASK                      (0x1U)
+#define SMC_SRS_WAKEUP_SHIFT                     (0U)
+/*! WAKEUP - Wakeup Reset
+ *  0b0..Reset not generated by wakeup from VLLS mode.
+ *  0b1..Reset generated by wakeup from VLLS mode.
+ */
+#define SMC_SRS_WAKEUP(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_SRS_WAKEUP_SHIFT)) & SMC_SRS_WAKEUP_MASK)
+#define SMC_SRS_POR_MASK                         (0x2U)
+#define SMC_SRS_POR_SHIFT                        (1U)
+/*! POR - POR Reset
+ *  0b0..Reset not generated by POR.
+ *  0b1..Reset generated by POR.
+ */
+#define SMC_SRS_POR(x)                           (((uint32_t)(((uint32_t)(x)) << SMC_SRS_POR_SHIFT)) & SMC_SRS_POR_MASK)
+#define SMC_SRS_LVD_MASK                         (0x4U)
+#define SMC_SRS_LVD_SHIFT                        (2U)
+/*! LVD - LVD Reset
+ *  0b0..Reset not generated by LVD.
+ *  0b1..Reset generated by LVD.
+ */
+#define SMC_SRS_LVD(x)                           (((uint32_t)(((uint32_t)(x)) << SMC_SRS_LVD_SHIFT)) & SMC_SRS_LVD_MASK)
+#define SMC_SRS_HVD_MASK                         (0x8U)
+#define SMC_SRS_HVD_SHIFT                        (3U)
+/*! HVD - HVD Reset
+ *  0b0..Reset not generated by HVD.
+ *  0b1..Reset generated by HVD.
+ */
+#define SMC_SRS_HVD(x)                           (((uint32_t)(((uint32_t)(x)) << SMC_SRS_HVD_SHIFT)) & SMC_SRS_HVD_MASK)
+#define SMC_SRS_WARM_MASK                        (0x10U)
+#define SMC_SRS_WARM_SHIFT                       (4U)
+/*! WARM - Warm Reset
+ *  0b0..Reset not generated by Warm Reset source.
+ *  0b1..Reset generated by Warm Reset source.
+ */
+#define SMC_SRS_WARM(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SRS_WARM_SHIFT)) & SMC_SRS_WARM_MASK)
+#define SMC_SRS_FATAL_MASK                       (0x20U)
+#define SMC_SRS_FATAL_SHIFT                      (5U)
+/*! FATAL - Fatal Reset
+ *  0b0..Reset was not generated by a fatal reset source.
+ *  0b1..Reset was generated by a fatal reset source.
+ */
+#define SMC_SRS_FATAL(x)                         (((uint32_t)(((uint32_t)(x)) << SMC_SRS_FATAL_SHIFT)) & SMC_SRS_FATAL_MASK)
+#define SMC_SRS_CORE_MASK                        (0x80U)
+#define SMC_SRS_CORE_SHIFT                       (7U)
+/*! CORE - Core Reset
+ *  0b0..Reset source was not core only reset.
+ *  0b1..Reset source was core reset and reset the core only.
+ */
+#define SMC_SRS_CORE(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SRS_CORE_SHIFT)) & SMC_SRS_CORE_MASK)
+#define SMC_SRS_PIN_MASK                         (0x100U)
+#define SMC_SRS_PIN_SHIFT                        (8U)
+/*! PIN - Pin Reset
+ *  0b0..Reset was not generated from the assertion of RESET_B pin.
+ *  0b1..Reset was generated from the assertion of RESET_B pin.
+ */
+#define SMC_SRS_PIN(x)                           (((uint32_t)(((uint32_t)(x)) << SMC_SRS_PIN_SHIFT)) & SMC_SRS_PIN_MASK)
+#define SMC_SRS_MDM_MASK                         (0x200U)
+#define SMC_SRS_MDM_SHIFT                        (9U)
+/*! MDM - MDM Reset
+ *  0b0..Reset was not generated from the MDM reset request.
+ *  0b1..Reset was generated from the MDM reset request.
+ */
+#define SMC_SRS_MDM(x)                           (((uint32_t)(((uint32_t)(x)) << SMC_SRS_MDM_SHIFT)) & SMC_SRS_MDM_MASK)
+#define SMC_SRS_RSTACK_MASK                      (0x400U)
+#define SMC_SRS_RSTACK_SHIFT                     (10U)
+/*! RSTACK - Reset Timeout
+ *  0b0..Reset not generated from Reset Controller Timeout.
+ *  0b1..Reset generated from Reset Controller Timeout.
+ */
+#define SMC_SRS_RSTACK(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_SRS_RSTACK_SHIFT)) & SMC_SRS_RSTACK_MASK)
+#define SMC_SRS_STOPACK_MASK                     (0x800U)
+#define SMC_SRS_STOPACK_SHIFT                    (11U)
+/*! STOPACK - Stop Timeout Reset
+ *  0b0..Reset not generated by Stop Controller Timeout.
+ *  0b1..Reset generated by Stop Controller Timeout.
+ */
+#define SMC_SRS_STOPACK(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_SRS_STOPACK_SHIFT)) & SMC_SRS_STOPACK_MASK)
+#define SMC_SRS_SCG_MASK                         (0x1000U)
+#define SMC_SRS_SCG_SHIFT                        (12U)
+/*! SCG - SCG Reset
+ *  0b0..Reset is not generated from an SCG loss of lock or loss of clock.
+ *  0b1..Reset is generated from an SCG loss of lock or loss of clock.
+ */
+#define SMC_SRS_SCG(x)                           (((uint32_t)(((uint32_t)(x)) << SMC_SRS_SCG_SHIFT)) & SMC_SRS_SCG_MASK)
+#define SMC_SRS_WDOG_MASK                        (0x2000U)
+#define SMC_SRS_WDOG_SHIFT                       (13U)
+/*! WDOG - Watchdog Reset
+ *  0b0..Reset is not generated from the WatchDog timeout.
+ *  0b1..Reset is generated from the WatchDog timeout.
+ */
+#define SMC_SRS_WDOG(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SRS_WDOG_SHIFT)) & SMC_SRS_WDOG_MASK)
+#define SMC_SRS_SW_MASK                          (0x4000U)
+#define SMC_SRS_SW_SHIFT                         (14U)
+/*! SW - Software Reset
+ *  0b0..Reset not generated by software request from core.
+ *  0b1..Reset generated by software request from core.
+ */
+#define SMC_SRS_SW(x)                            (((uint32_t)(((uint32_t)(x)) << SMC_SRS_SW_SHIFT)) & SMC_SRS_SW_MASK)
+#define SMC_SRS_LOCKUP_MASK                      (0x8000U)
+#define SMC_SRS_LOCKUP_SHIFT                     (15U)
+/*! LOCKUP - Lockup Reset
+ *  0b0..Reset not generated by core lockup or exception.
+ *  0b1..Reset generated by core lockup or exception.
+ */
+#define SMC_SRS_LOCKUP(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_SRS_LOCKUP_SHIFT)) & SMC_SRS_LOCKUP_MASK)
+#define SMC_SRS_CORE0_MASK                       (0x10000U)
+#define SMC_SRS_CORE0_SHIFT                      (16U)
+/*! CORE0 - Core0 System Reset
+ *  0b0..Reset not generated from Core0 system reset source.
+ *  0b1..Reset generated from Core0 system reset source.
+ */
+#define SMC_SRS_CORE0(x)                         (((uint32_t)(((uint32_t)(x)) << SMC_SRS_CORE0_SHIFT)) & SMC_SRS_CORE0_MASK)
+#define SMC_SRS_CORE1_MASK                       (0x20000U)
+#define SMC_SRS_CORE1_SHIFT                      (17U)
+/*! CORE1 - Core1 System Reset
+ *  0b0..Reset not generated from Core1 system reset source.
+ *  0b1..Reset generated from Core1 system reset source.
+ */
+#define SMC_SRS_CORE1(x)                         (((uint32_t)(((uint32_t)(x)) << SMC_SRS_CORE1_SHIFT)) & SMC_SRS_CORE1_MASK)
+#define SMC_SRS_JTAG_MASK                        (0x10000000U)
+#define SMC_SRS_JTAG_SHIFT                       (28U)
+/*! JTAG - JTAG System Reset
+ *  0b0..Reset not generated by JTAG system reset.
+ *  0b1..Reset generated by JTAG system reset.
+ */
+#define SMC_SRS_JTAG(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SRS_JTAG_SHIFT)) & SMC_SRS_JTAG_MASK)
+/*! @} */
+
+/*! @name RPC - Reset Pin Control */
+/*! @{ */
+#define SMC_RPC_FILTCFG_MASK                     (0x1FU)
+#define SMC_RPC_FILTCFG_SHIFT                    (0U)
+#define SMC_RPC_FILTCFG(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_RPC_FILTCFG_SHIFT)) & SMC_RPC_FILTCFG_MASK)
+#define SMC_RPC_FILTEN_MASK                      (0x100U)
+#define SMC_RPC_FILTEN_SHIFT                     (8U)
+/*! FILTEN - Filter Enable
+ *  0b0..Slow clock reset pin filter disabled.
+ *  0b1..Slow clock reset pin filter enabled in Run modes.
+ */
+#define SMC_RPC_FILTEN(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_RPC_FILTEN_SHIFT)) & SMC_RPC_FILTEN_MASK)
+#define SMC_RPC_LPOFEN_MASK                      (0x200U)
+#define SMC_RPC_LPOFEN_SHIFT                     (9U)
+/*! LPOFEN - LPO Filter Enable
+ *  0b0..LPO clock reset pin filter disabled.
+ *  0b1..LPO clock reset pin filter enabled in all modes.
+ */
+#define SMC_RPC_LPOFEN(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_RPC_LPOFEN_SHIFT)) & SMC_RPC_LPOFEN_MASK)
+/*! @} */
+
+/*! @name SSRS - Sticky System Reset Status */
+/*! @{ */
+#define SMC_SSRS_WAKEUP_MASK                     (0x1U)
+#define SMC_SSRS_WAKEUP_SHIFT                    (0U)
+/*! WAKEUP - Wakeup Reset
+ *  0b0..Reset not generated by wakeup from VLLS mode.
+ *  0b1..Reset generated by wakeup from VLLS mode.
+ */
+#define SMC_SSRS_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_WAKEUP_SHIFT)) & SMC_SSRS_WAKEUP_MASK)
+#define SMC_SSRS_POR_MASK                        (0x2U)
+#define SMC_SSRS_POR_SHIFT                       (1U)
+/*! POR - POR Reset
+ *  0b0..Reset not generated by POR.
+ *  0b1..Reset generated by POR.
+ */
+#define SMC_SSRS_POR(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_POR_SHIFT)) & SMC_SSRS_POR_MASK)
+#define SMC_SSRS_LVD_MASK                        (0x4U)
+#define SMC_SSRS_LVD_SHIFT                       (2U)
+/*! LVD - LVD Reset
+ *  0b0..Reset not generated by LVD.
+ *  0b1..Reset generated by LVD.
+ */
+#define SMC_SSRS_LVD(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_LVD_SHIFT)) & SMC_SSRS_LVD_MASK)
+#define SMC_SSRS_HVD_MASK                        (0x8U)
+#define SMC_SSRS_HVD_SHIFT                       (3U)
+/*! HVD - HVD Reset
+ *  0b0..Reset not generated by HVD.
+ *  0b1..Reset generated by HVD.
+ */
+#define SMC_SSRS_HVD(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_HVD_SHIFT)) & SMC_SSRS_HVD_MASK)
+#define SMC_SSRS_WARM_MASK                       (0x10U)
+#define SMC_SSRS_WARM_SHIFT                      (4U)
+/*! WARM - Warm Reset
+ *  0b0..Reset not generated by system reset source.
+ *  0b1..Reset generated by system reset source.
+ */
+#define SMC_SSRS_WARM(x)                         (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_WARM_SHIFT)) & SMC_SSRS_WARM_MASK)
+#define SMC_SSRS_FATAL_MASK                      (0x20U)
+#define SMC_SSRS_FATAL_SHIFT                     (5U)
+/*! FATAL - Fatal Reset
+ *  0b0..Reset was not generated by a fatal reset source.
+ *  0b1..Reset was generated by a fatal reset source.
+ */
+#define SMC_SSRS_FATAL(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_FATAL_SHIFT)) & SMC_SSRS_FATAL_MASK)
+#define SMC_SSRS_PIN_MASK                        (0x100U)
+#define SMC_SSRS_PIN_SHIFT                       (8U)
+/*! PIN - Pin Reset
+ *  0b0..Reset was not generated from the RESET_B pin.
+ *  0b1..Reset was generated from the RESET_B pin.
+ */
+#define SMC_SSRS_PIN(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_PIN_SHIFT)) & SMC_SSRS_PIN_MASK)
+#define SMC_SSRS_MDM_MASK                        (0x200U)
+#define SMC_SSRS_MDM_SHIFT                       (9U)
+/*! MDM - MDM Reset
+ *  0b0..Reset was not generated from the MDM reset request.
+ *  0b1..Reset was generated from the MDM reset request.
+ */
+#define SMC_SSRS_MDM(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_MDM_SHIFT)) & SMC_SSRS_MDM_MASK)
+#define SMC_SSRS_RSTACK_MASK                     (0x400U)
+#define SMC_SSRS_RSTACK_SHIFT                    (10U)
+/*! RSTACK - Reset Timeout
+ *  0b0..Reset not generated from Reset Controller Timeout.
+ *  0b1..Reset generated from Reset Controller Timeout.
+ */
+#define SMC_SSRS_RSTACK(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_RSTACK_SHIFT)) & SMC_SSRS_RSTACK_MASK)
+#define SMC_SSRS_STOPACK_MASK                    (0x800U)
+#define SMC_SSRS_STOPACK_SHIFT                   (11U)
+/*! STOPACK - Stop Timeout Reset
+ *  0b0..Reset not generated by Stop Controller Timeout.
+ *  0b1..Reset generated by Stop Controller Timeout.
+ */
+#define SMC_SSRS_STOPACK(x)                      (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_STOPACK_SHIFT)) & SMC_SSRS_STOPACK_MASK)
+#define SMC_SSRS_SCG_MASK                        (0x1000U)
+#define SMC_SSRS_SCG_SHIFT                       (12U)
+/*! SCG - SCG Reset
+ *  0b0..Reset is not generated from an SCG loss of lock or loss of clock.
+ *  0b1..Reset is generated from an SCG loss of lock or loss of clock.
+ */
+#define SMC_SSRS_SCG(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_SCG_SHIFT)) & SMC_SSRS_SCG_MASK)
+#define SMC_SSRS_WDOG_MASK                       (0x2000U)
+#define SMC_SSRS_WDOG_SHIFT                      (13U)
+/*! WDOG - Watchdog Reset
+ *  0b0..Reset is not generated from the WatchDog timeout.
+ *  0b1..Reset is generated from the WatchDog timeout.
+ */
+#define SMC_SSRS_WDOG(x)                         (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_WDOG_SHIFT)) & SMC_SSRS_WDOG_MASK)
+#define SMC_SSRS_SW_MASK                         (0x4000U)
+#define SMC_SSRS_SW_SHIFT                        (14U)
+/*! SW - Software Reset
+ *  0b0..Reset not generated by software request from core.
+ *  0b1..Reset generated by software request from core.
+ */
+#define SMC_SSRS_SW(x)                           (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_SW_SHIFT)) & SMC_SSRS_SW_MASK)
+#define SMC_SSRS_LOCKUP_MASK                     (0x8000U)
+#define SMC_SSRS_LOCKUP_SHIFT                    (15U)
+/*! LOCKUP - Lockup Reset
+ *  0b0..Reset not generated by core lockup.
+ *  0b1..Reset generated by core lockup.
+ */
+#define SMC_SSRS_LOCKUP(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_LOCKUP_SHIFT)) & SMC_SSRS_LOCKUP_MASK)
+#define SMC_SSRS_CORE0_MASK                      (0x10000U)
+#define SMC_SSRS_CORE0_SHIFT                     (16U)
+/*! CORE0 - Core0 Reset
+ *  0b0..Reset not generated from Core0 reset source.
+ *  0b1..Reset generated from Core0 reset source.
+ */
+#define SMC_SSRS_CORE0(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_CORE0_SHIFT)) & SMC_SSRS_CORE0_MASK)
+#define SMC_SSRS_CORE1_MASK                      (0x20000U)
+#define SMC_SSRS_CORE1_SHIFT                     (17U)
+/*! CORE1 - Core1 Reset
+ *  0b0..Reset not generated from Core1 reset source.
+ *  0b1..Reset generated from Core1 reset source.
+ */
+#define SMC_SSRS_CORE1(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_CORE1_SHIFT)) & SMC_SSRS_CORE1_MASK)
+#define SMC_SSRS_JTAG_MASK                       (0x10000000U)
+#define SMC_SSRS_JTAG_SHIFT                      (28U)
+/*! JTAG - JTAG System Reset
+ *  0b0..Reset not generated by JTAG system reset.
+ *  0b1..Reset generated by JTAG system reset.
+ */
+#define SMC_SSRS_JTAG(x)                         (((uint32_t)(((uint32_t)(x)) << SMC_SSRS_JTAG_SHIFT)) & SMC_SSRS_JTAG_MASK)
+/*! @} */
+
+/*! @name SRIE - System Reset Interrupt Enable */
+/*! @{ */
+#define SMC_SRIE_PIN_MASK                        (0x100U)
+#define SMC_SRIE_PIN_SHIFT                       (8U)
+/*! PIN - Pin Reset
+ *  0b0..Interrupt disabled.
+ *  0b1..Interrupt enabled.
+ */
+#define SMC_SRIE_PIN(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_PIN_SHIFT)) & SMC_SRIE_PIN_MASK)
+#define SMC_SRIE_MDM_MASK                        (0x200U)
+#define SMC_SRIE_MDM_SHIFT                       (9U)
+/*! MDM - MDM Reset
+ *  0b0..Interrupt disabled.
+ *  0b1..Interrupt enabled.
+ */
+#define SMC_SRIE_MDM(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_MDM_SHIFT)) & SMC_SRIE_MDM_MASK)
+#define SMC_SRIE_STOPACK_MASK                    (0x800U)
+#define SMC_SRIE_STOPACK_SHIFT                   (11U)
+/*! STOPACK - Stop Timeout Reset
+ *  0b0..Interrupt disabled.
+ *  0b1..Interrupt enabled.
+ */
+#define SMC_SRIE_STOPACK(x)                      (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_STOPACK_SHIFT)) & SMC_SRIE_STOPACK_MASK)
+#define SMC_SRIE_WDOG_MASK                       (0x2000U)
+#define SMC_SRIE_WDOG_SHIFT                      (13U)
+/*! WDOG - Watchdog Reset
+ *  0b0..Interrupt disabled.
+ *  0b1..Interrupt enabled.
+ */
+#define SMC_SRIE_WDOG(x)                         (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_WDOG_SHIFT)) & SMC_SRIE_WDOG_MASK)
+#define SMC_SRIE_SW_MASK                         (0x4000U)
+#define SMC_SRIE_SW_SHIFT                        (14U)
+/*! SW - Software Reset
+ *  0b0..Interrupt disabled.
+ *  0b1..Interrupt enabled.
+ */
+#define SMC_SRIE_SW(x)                           (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_SW_SHIFT)) & SMC_SRIE_SW_MASK)
+#define SMC_SRIE_LOCKUP_MASK                     (0x8000U)
+#define SMC_SRIE_LOCKUP_SHIFT                    (15U)
+/*! LOCKUP - Lockup Reset
+ *  0b0..Interrupt disabled.
+ *  0b1..Interrupt enabled.
+ */
+#define SMC_SRIE_LOCKUP(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_LOCKUP_SHIFT)) & SMC_SRIE_LOCKUP_MASK)
+#define SMC_SRIE_CORE0_MASK                      (0x10000U)
+#define SMC_SRIE_CORE0_SHIFT                     (16U)
+/*! CORE0 - Core0 Reset
+ *  0b0..Interrupt disabled.
+ *  0b1..Interrupt enabled.
+ */
+#define SMC_SRIE_CORE0(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_CORE0_SHIFT)) & SMC_SRIE_CORE0_MASK)
+#define SMC_SRIE_CORE1_MASK                      (0x20000U)
+#define SMC_SRIE_CORE1_SHIFT                     (17U)
+/*! CORE1 - Core1 Reset
+ *  0b0..Interrupt disabled.
+ *  0b1..Interrupt enabled.
+ */
+#define SMC_SRIE_CORE1(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_SRIE_CORE1_SHIFT)) & SMC_SRIE_CORE1_MASK)
+/*! @} */
+
+/*! @name SRIF - System Reset Interrupt Flag */
+/*! @{ */
+#define SMC_SRIF_PIN_MASK                        (0x100U)
+#define SMC_SRIF_PIN_SHIFT                       (8U)
+/*! PIN - Pin Reset
+ *  0b0..Reset source not pending.
+ *  0b1..Reset source pending.
+ */
+#define SMC_SRIF_PIN(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_PIN_SHIFT)) & SMC_SRIF_PIN_MASK)
+#define SMC_SRIF_MDM_MASK                        (0x200U)
+#define SMC_SRIF_MDM_SHIFT                       (9U)
+/*! MDM - MDM Reset
+ *  0b0..Reset source not pending.
+ *  0b1..Reset source pending.
+ */
+#define SMC_SRIF_MDM(x)                          (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_MDM_SHIFT)) & SMC_SRIF_MDM_MASK)
+#define SMC_SRIF_STOPACK_MASK                    (0x800U)
+#define SMC_SRIF_STOPACK_SHIFT                   (11U)
+/*! STOPACK - Stop Timeout Reset
+ *  0b0..Reset source not pending.
+ *  0b1..Reset source pending.
+ */
+#define SMC_SRIF_STOPACK(x)                      (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_STOPACK_SHIFT)) & SMC_SRIF_STOPACK_MASK)
+#define SMC_SRIF_WDOG_MASK                       (0x2000U)
+#define SMC_SRIF_WDOG_SHIFT                      (13U)
+/*! WDOG - Watchdog Reset
+ *  0b0..Reset source not pending.
+ *  0b1..Reset source pending.
+ */
+#define SMC_SRIF_WDOG(x)                         (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_WDOG_SHIFT)) & SMC_SRIF_WDOG_MASK)
+#define SMC_SRIF_SW_MASK                         (0x4000U)
+#define SMC_SRIF_SW_SHIFT                        (14U)
+/*! SW - Software Reset
+ *  0b0..Reset source not pending.
+ *  0b1..Reset source pending.
+ */
+#define SMC_SRIF_SW(x)                           (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_SW_SHIFT)) & SMC_SRIF_SW_MASK)
+#define SMC_SRIF_LOCKUP_MASK                     (0x8000U)
+#define SMC_SRIF_LOCKUP_SHIFT                    (15U)
+/*! LOCKUP - Lockup Reset
+ *  0b0..Reset source not pending.
+ *  0b1..Reset source pending.
+ */
+#define SMC_SRIF_LOCKUP(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_LOCKUP_SHIFT)) & SMC_SRIF_LOCKUP_MASK)
+#define SMC_SRIF_CORE0_MASK                      (0x10000U)
+#define SMC_SRIF_CORE0_SHIFT                     (16U)
+/*! CORE0 - Core0 Reset
+ *  0b0..Reset source not pending.
+ *  0b1..Reset source pending.
+ */
+#define SMC_SRIF_CORE0(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_CORE0_SHIFT)) & SMC_SRIF_CORE0_MASK)
+#define SMC_SRIF_CORE1_MASK                      (0x20000U)
+#define SMC_SRIF_CORE1_SHIFT                     (17U)
+/*! CORE1 - Core1 Reset
+ *  0b0..Reset source not pending.
+ *  0b1..Reset source pending.
+ */
+#define SMC_SRIF_CORE1(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_SRIF_CORE1_SHIFT)) & SMC_SRIF_CORE1_MASK)
+/*! @} */
+
+/*! @name MR - Mode Register */
+/*! @{ */
+#define SMC_MR_BOOTCFG_MASK                      (0x3U)
+#define SMC_MR_BOOTCFG_SHIFT                     (0U)
+/*! BOOTCFG - Boot Configuration
+ *  0b00..Boot from Flash.
+ *  0b01..Boot from ROM due to BOOTCFG0 pin assertion.
+ *  0b10..Boot from ROM due to FOPT configuration.
+ *  0b11..Boot from ROM due to both BOOTCFG0 pin assertion and FOPT configuration.
+ */
+#define SMC_MR_BOOTCFG(x)                        (((uint32_t)(((uint32_t)(x)) << SMC_MR_BOOTCFG_SHIFT)) & SMC_MR_BOOTCFG_MASK)
+/*! @} */
+
+/*! @name FM - Force Mode Register */
+/*! @{ */
+#define SMC_FM_FORCECFG_MASK                     (0x3U)
+#define SMC_FM_FORCECFG_SHIFT                    (0U)
+/*! FORCECFG - Boot Configuration
+ *  0b00..No effect.
+ *  0b01..Assert corresponding bit in Mode Register on next system reset.
+ */
+#define SMC_FM_FORCECFG(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_FM_FORCECFG_SHIFT)) & SMC_FM_FORCECFG_MASK)
+/*! @} */
+
+/*! @name SRAMLPR - SRAM Low Power Register */
+/*! @{ */
+#define SMC_SRAMLPR_LPE_MASK                     (0xFFFFFFFFU)
+#define SMC_SRAMLPR_LPE_SHIFT                    (0U)
+#define SMC_SRAMLPR_LPE(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_SRAMLPR_LPE_SHIFT)) & SMC_SRAMLPR_LPE_MASK)
+/*! @} */
+
+/*! @name SRAMDSR - SRAM Deep Sleep Register */
+/*! @{ */
+#define SMC_SRAMDSR_DSE_MASK                     (0xFFFFFFFFU)
+#define SMC_SRAMDSR_DSE_SHIFT                    (0U)
+#define SMC_SRAMDSR_DSE(x)                       (((uint32_t)(((uint32_t)(x)) << SMC_SRAMDSR_DSE_SHIFT)) & SMC_SRAMDSR_DSE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC0 base address */
+#define SMC0_BASE                                (0x40020000u)
+/** Peripheral SMC0 base pointer */
+#define SMC0                                     ((SMC_Type *)SMC0_BASE)
+/** Peripheral SMC1 base address */
+#define SMC1_BASE                                (0x41020000u)
+/** Peripheral SMC1 base pointer */
+#define SMC1                                     ((SMC_Type *)SMC1_BASE)
+/** Array initializer of SMC peripheral base addresses */
+#define SMC_BASE_ADDRS                           { SMC0_BASE, SMC1_BASE }
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASE_PTRS                            { SMC0, SMC1 }
+/** Interrupt vectors for the SMC peripheral type */
+#define SMC_IRQS                                 { NotAvail_IRQn, CMC1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPM_Peripheral_Access_Layer SPM Peripheral Access Layer
+ * @{
+ */
+
+/** SPM - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+       uint8_t RESERVED_0[4];
+  __I  uint32_t RSR;                               /**< Regulator Status Register, offset: 0x8 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t RCTRL;                             /**< Run Control Register, offset: 0x10 */
+  __IO uint32_t LPCTRL;                            /**< Low Power Control Register, offset: 0x14 */
+       uint8_t RESERVED_2[232];
+  __IO uint32_t CORERCNFG;                         /**< CORE LDO RUN Configuration Register, offset: 0x100 */
+  __IO uint32_t CORELPCNFG;                        /**< CORE LDO Low Power Configuration register, offset: 0x104 */
+  __IO uint32_t CORESC;                            /**< Core LDO Status And Control register, offset: 0x108 */
+  __IO uint32_t LVDSC1;                            /**< Low Voltage Detect Status and Control 1 register, offset: 0x10C */
+  __IO uint32_t LVDSC2;                            /**< Low Voltage Detect Status and Control 2 register, offset: 0x110 */
+  __IO uint32_t HVDSC1;                            /**< High Voltage Detect Status And Control 1 register, offset: 0x114 */
+       uint8_t RESERVED_3[232];
+  __IO uint32_t RFLDOLPCNFG;                       /**< RF LDO Low Power Configuration register, offset: 0x200 */
+  __IO uint32_t RFLDOSC;                           /**< RF LDO Status And Control register, offset: 0x204 */
+       uint8_t RESERVED_4[252];
+  __IO uint32_t DCDCSC;                            /**< DCDC Status Control Register, offset: 0x304 */
+       uint8_t RESERVED_5[4];
+  __IO uint32_t DCDCC1;                            /**< DCDC Control Register 1, offset: 0x30C */
+  __IO uint32_t DCDCC2;                            /**< DCDC Control Register 2, offset: 0x310 */
+  __IO uint32_t DCDCC3;                            /**< DCDC Control Register 3, offset: 0x314 */
+  __IO uint32_t DCDCC4;                            /**< DCDC Control Register 4, offset: 0x318 */
+       uint8_t RESERVED_6[4];
+  __IO uint32_t DCDCC6;                            /**< DCDC Control Register 6, offset: 0x320 */
+       uint8_t RESERVED_7[232];
+  __IO uint32_t LPREQPINCNTRL;                     /**< LP Request Pin Control Register, offset: 0x40C */
+} SPM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SPM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPM_Register_Masks SPM Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define SPM_VERID_FEATURE_MASK                   (0xFFFFU)
+#define SPM_VERID_FEATURE_SHIFT                  (0U)
+/*! FEATURE - Feature Specification Number
+ *  0b0000000000000000..Standard features implemented.
+ */
+#define SPM_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << SPM_VERID_FEATURE_SHIFT)) & SPM_VERID_FEATURE_MASK)
+#define SPM_VERID_MINOR_MASK                     (0xFF0000U)
+#define SPM_VERID_MINOR_SHIFT                    (16U)
+#define SPM_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << SPM_VERID_MINOR_SHIFT)) & SPM_VERID_MINOR_MASK)
+#define SPM_VERID_MAJOR_MASK                     (0xFF000000U)
+#define SPM_VERID_MAJOR_SHIFT                    (24U)
+#define SPM_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << SPM_VERID_MAJOR_SHIFT)) & SPM_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name RSR - Regulator Status Register */
+/*! @{ */
+#define SPM_RSR_REGSEL_MASK                      (0x7U)
+#define SPM_RSR_REGSEL_SHIFT                     (0U)
+#define SPM_RSR_REGSEL(x)                        (((uint32_t)(((uint32_t)(x)) << SPM_RSR_REGSEL_SHIFT)) & SPM_RSR_REGSEL_MASK)
+#define SPM_RSR_MCUPMSTAT_MASK                   (0x1F0000U)
+#define SPM_RSR_MCUPMSTAT_SHIFT                  (16U)
+/*! MCUPMSTAT - MCU Power Mode Status
+ *  0b00000..Reserved
+ *  0b00001..Last Low Power mode is STOP.
+ *  0b00010..Last Low Power mode is VLPS.
+ *  0b00100..Last Low Power mode is LLS.
+ *  0b01000..Last Low Power mode is VLLS23.
+ *  0b10000..Last Low Power mode is VLLS01.
+ */
+#define SPM_RSR_MCUPMSTAT(x)                     (((uint32_t)(((uint32_t)(x)) << SPM_RSR_MCUPMSTAT_SHIFT)) & SPM_RSR_MCUPMSTAT_MASK)
+#define SPM_RSR_RFPMSTAT_MASK                    (0x7000000U)
+#define SPM_RSR_RFPMSTAT_SHIFT                   (24U)
+/*! RFPMSTAT - RADIO Power Mode Status
+ *  0b000..Reserved
+ *  0b001..Current Power mode is VLPS.
+ *  0b010..Current Power mode is LLS.
+ *  0b100..Current Power mode is VLLS.
+ */
+#define SPM_RSR_RFPMSTAT(x)                      (((uint32_t)(((uint32_t)(x)) << SPM_RSR_RFPMSTAT_SHIFT)) & SPM_RSR_RFPMSTAT_MASK)
+#define SPM_RSR_RFRUNFORCE_MASK                  (0x8000000U)
+#define SPM_RSR_RFRUNFORCE_SHIFT                 (27U)
+/*! RFRUNFORCE - RADIO Run Force Power Mode Status
+ *  0b0..Radio Run Force Regulator Off
+ *  0b1..Radio Run Force Regulator On.
+ */
+#define SPM_RSR_RFRUNFORCE(x)                    (((uint32_t)(((uint32_t)(x)) << SPM_RSR_RFRUNFORCE_SHIFT)) & SPM_RSR_RFRUNFORCE_MASK)
+/*! @} */
+
+/*! @name RCTRL - Run Control Register */
+/*! @{ */
+#define SPM_RCTRL_REGSEL_MASK                    (0x7U)
+#define SPM_RCTRL_REGSEL_SHIFT                   (0U)
+#define SPM_RCTRL_REGSEL(x)                      (((uint32_t)(((uint32_t)(x)) << SPM_RCTRL_REGSEL_SHIFT)) & SPM_RCTRL_REGSEL_MASK)
+/*! @} */
+
+/*! @name LPCTRL - Low Power Control Register */
+/*! @{ */
+#define SPM_LPCTRL_REGSEL_MASK                   (0x7U)
+#define SPM_LPCTRL_REGSEL_SHIFT                  (0U)
+#define SPM_LPCTRL_REGSEL(x)                     (((uint32_t)(((uint32_t)(x)) << SPM_LPCTRL_REGSEL_SHIFT)) & SPM_LPCTRL_REGSEL_MASK)
+/*! @} */
+
+/*! @name CORERCNFG - CORE LDO RUN Configuration Register */
+/*! @{ */
+#define SPM_CORERCNFG_VDDIOVDDMEN_MASK           (0x10000U)
+#define SPM_CORERCNFG_VDDIOVDDMEN_SHIFT          (16U)
+/*! VDDIOVDDMEN - VDDIOVDDMEN
+ *  0b0..VDDIO voltage monitor disabled in run modes.
+ *  0b1..VDDIO voltage monitor enabled in run modes.
+ */
+#define SPM_CORERCNFG_VDDIOVDDMEN(x)             (((uint32_t)(((uint32_t)(x)) << SPM_CORERCNFG_VDDIOVDDMEN_SHIFT)) & SPM_CORERCNFG_VDDIOVDDMEN_MASK)
+#define SPM_CORERCNFG_USBVDDMEN_MASK             (0x20000U)
+#define SPM_CORERCNFG_USBVDDMEN_SHIFT            (17U)
+/*! USBVDDMEN - USBVDDMEN
+ *  0b0..USB voltage monitor disabled in run modes.
+ *  0b1..USB voltage monitor enabled in run modes.
+ */
+#define SPM_CORERCNFG_USBVDDMEN(x)               (((uint32_t)(((uint32_t)(x)) << SPM_CORERCNFG_USBVDDMEN_SHIFT)) & SPM_CORERCNFG_USBVDDMEN_MASK)
+#define SPM_CORERCNFG_RTCVDDMEN_MASK             (0x40000U)
+#define SPM_CORERCNFG_RTCVDDMEN_SHIFT            (18U)
+/*! RTCVDDMEN - RTCVDDMEN
+ *  0b0..RTC voltage monitor disabled in run modes.
+ *  0b1..RTC voltage monitor enabled in run modes.
+ */
+#define SPM_CORERCNFG_RTCVDDMEN(x)               (((uint32_t)(((uint32_t)(x)) << SPM_CORERCNFG_RTCVDDMEN_SHIFT)) & SPM_CORERCNFG_RTCVDDMEN_MASK)
+/*! @} */
+
+/*! @name CORELPCNFG - CORE LDO Low Power Configuration register */
+/*! @{ */
+#define SPM_CORELPCNFG_LPSEL_MASK                (0x2U)
+#define SPM_CORELPCNFG_LPSEL_SHIFT               (1U)
+/*! LPSEL - LPSEL
+ *  0b0..Core LDO enters low power state in VLP/Stop modes.
+ *  0b1..Core LDO remains in high power state in VLP/Stop modes. If LPSEL = 1 in a low power mode then BGEN must also be set to 1.
+ */
+#define SPM_CORELPCNFG_LPSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_LPSEL_SHIFT)) & SPM_CORELPCNFG_LPSEL_MASK)
+#define SPM_CORELPCNFG_BGEN_MASK                 (0x4U)
+#define SPM_CORELPCNFG_BGEN_SHIFT                (2U)
+/*! BGEN - Bandgap Enable In Low Power Mode Operation
+ *  0b0..Bandgap is disabled in STOP/VLP/LLS and VLLS modes.
+ *  0b1..Bandgap remains enabled in STOP/VLP/LLS and VLLS modes.
+ */
+#define SPM_CORELPCNFG_BGEN(x)                   (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_BGEN_SHIFT)) & SPM_CORELPCNFG_BGEN_MASK)
+#define SPM_CORELPCNFG_BGBEN_MASK                (0x8U)
+#define SPM_CORELPCNFG_BGBEN_SHIFT               (3U)
+/*! BGBEN - Bandgap Buffer Enable
+ *  0b0..Bandgap buffer not enabled
+ *  0b1..Bandgap buffer enabled BGEN must be set when this bit is also set.
+ */
+#define SPM_CORELPCNFG_BGBEN(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_BGBEN_SHIFT)) & SPM_CORELPCNFG_BGBEN_MASK)
+#define SPM_CORELPCNFG_BGBDS_MASK                (0x10U)
+#define SPM_CORELPCNFG_BGBDS_SHIFT               (4U)
+/*! BGBDS - Bandgap Buffer Drive Select
+ *  0b0..Low Drive
+ *  0b1..High Drive
+ */
+#define SPM_CORELPCNFG_BGBDS(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_BGBDS_SHIFT)) & SPM_CORELPCNFG_BGBDS_MASK)
+#define SPM_CORELPCNFG_LPOEN_MASK                (0x80U)
+#define SPM_CORELPCNFG_LPOEN_SHIFT               (7U)
+/*! LPOEN - LPO Enabled
+ *  0b0..LPO is disabled in VLLS modes.
+ *  0b1..LPO remains enabled in VLLS modes.
+ */
+#define SPM_CORELPCNFG_LPOEN(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_LPOEN_SHIFT)) & SPM_CORELPCNFG_LPOEN_MASK)
+#define SPM_CORELPCNFG_POREN_MASK                (0x100U)
+#define SPM_CORELPCNFG_POREN_SHIFT               (8U)
+/*! POREN - POR Enabled
+ *  0b0..POR brownout is disabled in VLLS0/1 mode.
+ *  0b1..POR brownout remains enabled in VLLS0/1 mode.
+ */
+#define SPM_CORELPCNFG_POREN(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_POREN_SHIFT)) & SPM_CORELPCNFG_POREN_MASK)
+#define SPM_CORELPCNFG_LVDEN_MASK                (0x200U)
+#define SPM_CORELPCNFG_LVDEN_SHIFT               (9U)
+/*! LVDEN - LVD Enabled
+ *  0b0..LVD/HVD is disabled in low power modes.
+ *  0b1..LVD/HVD remains enabled in low power modes. BGEN must be set when this bit is also set.
+ */
+#define SPM_CORELPCNFG_LVDEN(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_LVDEN_SHIFT)) & SPM_CORELPCNFG_LVDEN_MASK)
+#define SPM_CORELPCNFG_LPHIDRIVE_MASK            (0x4000U)
+#define SPM_CORELPCNFG_LPHIDRIVE_SHIFT           (14U)
+/*! LPHIDRIVE - LPHIDRIVE
+ *  0b0..High Drive disabled.
+ *  0b1..High Drive enabled.
+ */
+#define SPM_CORELPCNFG_LPHIDRIVE(x)              (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_LPHIDRIVE_SHIFT)) & SPM_CORELPCNFG_LPHIDRIVE_MASK)
+#define SPM_CORELPCNFG_ALLREFEN_MASK             (0x8000U)
+#define SPM_CORELPCNFG_ALLREFEN_SHIFT            (15U)
+/*! ALLREFEN - All Reference Enable. This bit only has an affect in VLLS0/1.
+ *  0b0..All references are disabled in VLLS.
+ *  0b1..All references are enabled in VLLS0/1.
+ */
+#define SPM_CORELPCNFG_ALLREFEN(x)               (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_ALLREFEN_SHIFT)) & SPM_CORELPCNFG_ALLREFEN_MASK)
+#define SPM_CORELPCNFG_VDDIOVDDMEN_MASK          (0x10000U)
+#define SPM_CORELPCNFG_VDDIOVDDMEN_SHIFT         (16U)
+/*! VDDIOVDDMEN - VDDIOVDDMEN
+ *  0b0..VDDIO voltage monitor disabled in lp modes.
+ *  0b1..VDDIO voltage monitor enabled in lp modes. Note: voltage monitor is always disabled in VLLS0/1 modes.
+ */
+#define SPM_CORELPCNFG_VDDIOVDDMEN(x)            (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_VDDIOVDDMEN_SHIFT)) & SPM_CORELPCNFG_VDDIOVDDMEN_MASK)
+#define SPM_CORELPCNFG_USBVDDMEN_MASK            (0x20000U)
+#define SPM_CORELPCNFG_USBVDDMEN_SHIFT           (17U)
+/*! USBVDDMEN - USBVDDMEN
+ *  0b0..USB voltage monitor disabled in lp modes.
+ *  0b1..USB voltage monitor enabled in lp modes. Note: voltage monitor is always disabled in VLLS0/1 modes.
+ */
+#define SPM_CORELPCNFG_USBVDDMEN(x)              (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_USBVDDMEN_SHIFT)) & SPM_CORELPCNFG_USBVDDMEN_MASK)
+#define SPM_CORELPCNFG_RTCVDDMEN_MASK            (0x40000U)
+#define SPM_CORELPCNFG_RTCVDDMEN_SHIFT           (18U)
+/*! RTCVDDMEN - RTCVDDMEN
+ *  0b0..RTC voltage monitor disabled in lp modes.
+ *  0b1..RTC voltage monitor enabled in lp modes. Note: voltage monitor is always disabled in VLLS0/1 modes.
+ */
+#define SPM_CORELPCNFG_RTCVDDMEN(x)              (((uint32_t)(((uint32_t)(x)) << SPM_CORELPCNFG_RTCVDDMEN_SHIFT)) & SPM_CORELPCNFG_RTCVDDMEN_MASK)
+/*! @} */
+
+/*! @name CORESC - Core LDO Status And Control register */
+/*! @{ */
+#define SPM_CORESC_REGONS_MASK                   (0x4U)
+#define SPM_CORESC_REGONS_SHIFT                  (2U)
+/*! REGONS - CORE LDO Regulator in Run Regulation Status
+ *  0b0..Regulator is in low power state or in transition to/from it.
+ *  0b1..Regulator is in high power state.
+ */
+#define SPM_CORESC_REGONS(x)                     (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_REGONS_SHIFT)) & SPM_CORESC_REGONS_MASK)
+#define SPM_CORESC_ACKISO_MASK                   (0x8U)
+#define SPM_CORESC_ACKISO_SHIFT                  (3U)
+/*! ACKISO - Acknowledge Isolation
+ *  0b0..Peripherals and I/O pads are in normal run state.
+ *  0b1..Certain peripherals and I/O pads are in a isolated and latched state.
+ */
+#define SPM_CORESC_ACKISO(x)                     (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_ACKISO_SHIFT)) & SPM_CORESC_ACKISO_MASK)
+#define SPM_CORESC_TRIM_MASK                     (0x3F00U)
+#define SPM_CORESC_TRIM_SHIFT                    (8U)
+#define SPM_CORESC_TRIM(x)                       (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_TRIM_SHIFT)) & SPM_CORESC_TRIM_MASK)
+#define SPM_CORESC_VDDIOOVRIDE_MASK              (0x10000U)
+#define SPM_CORESC_VDDIOOVRIDE_SHIFT             (16U)
+/*! VDDIOOVRIDE - VDDIOOVRIDE
+ *  0b0..VDDIOOK status set to 1'b0.
+ *  0b1..VDDIOOK status set to 1'b1.
+ */
+#define SPM_CORESC_VDDIOOVRIDE(x)                (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_VDDIOOVRIDE_SHIFT)) & SPM_CORESC_VDDIOOVRIDE_MASK)
+#define SPM_CORESC_USBOVRIDE_MASK                (0x20000U)
+#define SPM_CORESC_USBOVRIDE_SHIFT               (17U)
+/*! USBOVRIDE - USBOVRIDE
+ *  0b0..USBVDDOK status set to 1'b0.
+ *  0b1..USBVDDOK status set to 1'b1.
+ */
+#define SPM_CORESC_USBOVRIDE(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_USBOVRIDE_SHIFT)) & SPM_CORESC_USBOVRIDE_MASK)
+#define SPM_CORESC_RTCOVRIDE_MASK                (0x40000U)
+#define SPM_CORESC_RTCOVRIDE_SHIFT               (18U)
+/*! RTCOVRIDE - RTCOVRIDE
+ *  0b0..RTCVDDOK status set to 1'b0.
+ *  0b1..RTCVDDOK status set to 1'b1.
+ */
+#define SPM_CORESC_RTCOVRIDE(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_RTCOVRIDE_SHIFT)) & SPM_CORESC_RTCOVRIDE_MASK)
+#define SPM_CORESC_VDDIOOK_MASK                  (0x1000000U)
+#define SPM_CORESC_VDDIOOK_SHIFT                 (24U)
+#define SPM_CORESC_VDDIOOK(x)                    (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_VDDIOOK_SHIFT)) & SPM_CORESC_VDDIOOK_MASK)
+#define SPM_CORESC_USBVDDOK_MASK                 (0x2000000U)
+#define SPM_CORESC_USBVDDOK_SHIFT                (25U)
+#define SPM_CORESC_USBVDDOK(x)                   (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_USBVDDOK_SHIFT)) & SPM_CORESC_USBVDDOK_MASK)
+#define SPM_CORESC_RTCVDDOK_MASK                 (0x4000000U)
+#define SPM_CORESC_RTCVDDOK_SHIFT                (26U)
+#define SPM_CORESC_RTCVDDOK(x)                   (((uint32_t)(((uint32_t)(x)) << SPM_CORESC_RTCVDDOK_SHIFT)) & SPM_CORESC_RTCVDDOK_MASK)
+/*! @} */
+
+/*! @name LVDSC1 - Low Voltage Detect Status and Control 1 register */
+/*! @{ */
+#define SPM_LVDSC1_COREVDD_LVDRE_MASK            (0x10U)
+#define SPM_LVDSC1_COREVDD_LVDRE_SHIFT           (4U)
+/*! COREVDD_LVDRE - Core Low-Voltage Detect Reset Enable
+ *  0b0..COREVDD_LVDF does not generate hardware resets
+ *  0b1..Force an MCU reset when CORE_LVDF = 1
+ */
+#define SPM_LVDSC1_COREVDD_LVDRE(x)              (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_COREVDD_LVDRE_SHIFT)) & SPM_LVDSC1_COREVDD_LVDRE_MASK)
+#define SPM_LVDSC1_COREVDD_LVDIE_MASK            (0x20U)
+#define SPM_LVDSC1_COREVDD_LVDIE_SHIFT           (5U)
+/*! COREVDD_LVDIE - Low-Voltage Detect Interrupt Enable
+ *  0b0..Hardware interrupt disabled (use polling)
+ *  0b1..Request a hardware interrupt when LVDF = 1
+ */
+#define SPM_LVDSC1_COREVDD_LVDIE(x)              (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_COREVDD_LVDIE_SHIFT)) & SPM_LVDSC1_COREVDD_LVDIE_MASK)
+#define SPM_LVDSC1_COREVDD_LVDACK_MASK           (0x40U)
+#define SPM_LVDSC1_COREVDD_LVDACK_SHIFT          (6U)
+#define SPM_LVDSC1_COREVDD_LVDACK(x)             (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_COREVDD_LVDACK_SHIFT)) & SPM_LVDSC1_COREVDD_LVDACK_MASK)
+#define SPM_LVDSC1_COREVDD_LVDF_MASK             (0x80U)
+#define SPM_LVDSC1_COREVDD_LVDF_SHIFT            (7U)
+/*! COREVDD_LVDF - Low-Voltage Detect Flag
+ *  0b0..Low-voltage event not detected
+ *  0b1..Low-voltage event detected
+ */
+#define SPM_LVDSC1_COREVDD_LVDF(x)               (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_COREVDD_LVDF_SHIFT)) & SPM_LVDSC1_COREVDD_LVDF_MASK)
+#define SPM_LVDSC1_VDD_LVDV_MASK                 (0x30000U)
+#define SPM_LVDSC1_VDD_LVDV_SHIFT                (16U)
+/*! VDD_LVDV - VDD Low-Voltage Detect Voltage Select
+ *  0b00..Low trip point selected (V LVD = V LVDL )
+ *  0b01..High trip point selected (V LVD = V LVDH )
+ *  0b10..Reserved
+ *  0b11..Reserved
+ */
+#define SPM_LVDSC1_VDD_LVDV(x)                   (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_VDD_LVDV_SHIFT)) & SPM_LVDSC1_VDD_LVDV_MASK)
+#define SPM_LVDSC1_VDD_LVDRE_MASK                (0x100000U)
+#define SPM_LVDSC1_VDD_LVDRE_SHIFT               (20U)
+/*! VDD_LVDRE - VDD Low-Voltage Detect Reset Enable
+ *  0b0..VDD_LVDF does not generate hardware resets
+ *  0b1..Force an MCU reset when VDD_LVDF = 1
+ */
+#define SPM_LVDSC1_VDD_LVDRE(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_VDD_LVDRE_SHIFT)) & SPM_LVDSC1_VDD_LVDRE_MASK)
+#define SPM_LVDSC1_VDD_LVDIE_MASK                (0x200000U)
+#define SPM_LVDSC1_VDD_LVDIE_SHIFT               (21U)
+/*! VDD_LVDIE - VDD Low-Voltage Detect Interrupt Enable
+ *  0b0..Hardware interrupt disabled (use polling)
+ *  0b1..Request a hardware interrupt when VDD_LVDF = 1
+ */
+#define SPM_LVDSC1_VDD_LVDIE(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_VDD_LVDIE_SHIFT)) & SPM_LVDSC1_VDD_LVDIE_MASK)
+#define SPM_LVDSC1_VDD_LVDACK_MASK               (0x400000U)
+#define SPM_LVDSC1_VDD_LVDACK_SHIFT              (22U)
+#define SPM_LVDSC1_VDD_LVDACK(x)                 (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_VDD_LVDACK_SHIFT)) & SPM_LVDSC1_VDD_LVDACK_MASK)
+#define SPM_LVDSC1_VDD_LVDF_MASK                 (0x800000U)
+#define SPM_LVDSC1_VDD_LVDF_SHIFT                (23U)
+/*! VDD_LVDF - VDD Low-Voltage Detect Flag
+ *  0b0..Low-voltage event not detected
+ *  0b1..Low-voltage event detected
+ */
+#define SPM_LVDSC1_VDD_LVDF(x)                   (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC1_VDD_LVDF_SHIFT)) & SPM_LVDSC1_VDD_LVDF_MASK)
+/*! @} */
+
+/*! @name LVDSC2 - Low Voltage Detect Status and Control 2 register */
+/*! @{ */
+#define SPM_LVDSC2_VDD_LVWV_MASK                 (0x30000U)
+#define SPM_LVDSC2_VDD_LVWV_SHIFT                (16U)
+/*! VDD_LVWV - VDD Low-Voltage Warning Voltage Select
+ *  0b00..Low trip point selected (V LVW = VLVW1)
+ *  0b01..Mid 1 trip point selected (V LVW = VLVW2)
+ *  0b10..Mid 2 trip point selected (V LVW = VLVW3)
+ *  0b11..High trip point selected (V LVW = VLVW4)
+ */
+#define SPM_LVDSC2_VDD_LVWV(x)                   (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC2_VDD_LVWV_SHIFT)) & SPM_LVDSC2_VDD_LVWV_MASK)
+#define SPM_LVDSC2_VDD_LVWIE_MASK                (0x200000U)
+#define SPM_LVDSC2_VDD_LVWIE_SHIFT               (21U)
+/*! VDD_LVWIE - VDD Low-Voltage Warning Interrupt Enable
+ *  0b0..Hardware interrupt disabled (use polling)
+ *  0b1..Request a hardware interrupt when VDD_LVWF = 1
+ */
+#define SPM_LVDSC2_VDD_LVWIE(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC2_VDD_LVWIE_SHIFT)) & SPM_LVDSC2_VDD_LVWIE_MASK)
+#define SPM_LVDSC2_VDD_LVWACK_MASK               (0x400000U)
+#define SPM_LVDSC2_VDD_LVWACK_SHIFT              (22U)
+#define SPM_LVDSC2_VDD_LVWACK(x)                 (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC2_VDD_LVWACK_SHIFT)) & SPM_LVDSC2_VDD_LVWACK_MASK)
+#define SPM_LVDSC2_VDD_LVWF_MASK                 (0x800000U)
+#define SPM_LVDSC2_VDD_LVWF_SHIFT                (23U)
+/*! VDD_LVWF - VDD Low-Voltage Warning Flag
+ *  0b0..Low-voltage warning event not detected
+ *  0b1..Low-voltage warning event detected
+ */
+#define SPM_LVDSC2_VDD_LVWF(x)                   (((uint32_t)(((uint32_t)(x)) << SPM_LVDSC2_VDD_LVWF_SHIFT)) & SPM_LVDSC2_VDD_LVWF_MASK)
+/*! @} */
+
+/*! @name HVDSC1 - High Voltage Detect Status And Control 1 register */
+/*! @{ */
+#define SPM_HVDSC1_VDD_HVDV_MASK                 (0x10000U)
+#define SPM_HVDSC1_VDD_HVDV_SHIFT                (16U)
+/*! VDD_HVDV - VDD High-Voltage Detect Voltage Select
+ *  0b0..Low trip point selected (V VDD = V VDD_HVDL )
+ *  0b1..High trip point selected (V VDD = V VDD_HVDH )
+ */
+#define SPM_HVDSC1_VDD_HVDV(x)                   (((uint32_t)(((uint32_t)(x)) << SPM_HVDSC1_VDD_HVDV_SHIFT)) & SPM_HVDSC1_VDD_HVDV_MASK)
+#define SPM_HVDSC1_VDD_HVDRE_MASK                (0x100000U)
+#define SPM_HVDSC1_VDD_HVDRE_SHIFT               (20U)
+/*! VDD_HVDRE - VDD High-Voltage Detect Reset Enable
+ *  0b0..VDD HVDF does not generate hardware resets
+ *  0b1..Force an MCU reset when VDD_HVDF = 1
+ */
+#define SPM_HVDSC1_VDD_HVDRE(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_HVDSC1_VDD_HVDRE_SHIFT)) & SPM_HVDSC1_VDD_HVDRE_MASK)
+#define SPM_HVDSC1_VDD_HVDIE_MASK                (0x200000U)
+#define SPM_HVDSC1_VDD_HVDIE_SHIFT               (21U)
+/*! VDD_HVDIE - VDD High-Voltage Detect Interrupt Enable
+ *  0b0..Hardware interrupt disabled (use polling)
+ *  0b1..Request a hardware interrupt when HVDF = 1
+ */
+#define SPM_HVDSC1_VDD_HVDIE(x)                  (((uint32_t)(((uint32_t)(x)) << SPM_HVDSC1_VDD_HVDIE_SHIFT)) & SPM_HVDSC1_VDD_HVDIE_MASK)
+#define SPM_HVDSC1_VDD_HVDACK_MASK               (0x400000U)
+#define SPM_HVDSC1_VDD_HVDACK_SHIFT              (22U)
+#define SPM_HVDSC1_VDD_HVDACK(x)                 (((uint32_t)(((uint32_t)(x)) << SPM_HVDSC1_VDD_HVDACK_SHIFT)) & SPM_HVDSC1_VDD_HVDACK_MASK)
+#define SPM_HVDSC1_VDD_HVDF_MASK                 (0x800000U)
+#define SPM_HVDSC1_VDD_HVDF_SHIFT                (23U)
+/*! VDD_HVDF - VDD High-Voltage Detect Flag
+ *  0b0..Vdd High-voltage event not detected
+ *  0b1..Vdd High-voltage event detected
+ */
+#define SPM_HVDSC1_VDD_HVDF(x)                   (((uint32_t)(((uint32_t)(x)) << SPM_HVDSC1_VDD_HVDF_SHIFT)) & SPM_HVDSC1_VDD_HVDF_MASK)
+/*! @} */
+
+/*! @name RFLDOLPCNFG - RF LDO Low Power Configuration register */
+/*! @{ */
+#define SPM_RFLDOLPCNFG_LPSEL_MASK               (0x2U)
+#define SPM_RFLDOLPCNFG_LPSEL_SHIFT              (1U)
+/*! LPSEL - LPSEL
+ *  0b0..RF LDO regulator enters low power state in VLP/Stop modes.
+ *  0b1..RF LDO regulator remains in high power state in VLP/Stop modes.
+ */
+#define SPM_RFLDOLPCNFG_LPSEL(x)                 (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOLPCNFG_LPSEL_SHIFT)) & SPM_RFLDOLPCNFG_LPSEL_MASK)
+/*! @} */
+
+/*! @name RFLDOSC - RF LDO Status And Control register */
+/*! @{ */
+#define SPM_RFLDOSC_IOREGVSEL_MASK               (0x1U)
+#define SPM_RFLDOSC_IOREGVSEL_SHIFT              (0U)
+/*! IOREGVSEL - IO Regulator Voltage Select
+ *  0b0..Regulate to 1.8V.
+ *  0b1..Regulate to 1.5V.
+ */
+#define SPM_RFLDOSC_IOREGVSEL(x)                 (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_IOREGVSEL_SHIFT)) & SPM_RFLDOSC_IOREGVSEL_MASK)
+#define SPM_RFLDOSC_VDD1P8SEL_MASK               (0x10U)
+#define SPM_RFLDOSC_VDD1P8SEL_SHIFT              (4U)
+/*! VDD1P8SEL - VDD 1p8 SNS Pin Select
+ *  0b0..VDD1p8_SNS0 selected.
+ *  0b1..VDD1p8_SNS1 selected.
+ */
+#define SPM_RFLDOSC_VDD1P8SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_VDD1P8SEL_SHIFT)) & SPM_RFLDOSC_VDD1P8SEL_MASK)
+#define SPM_RFLDOSC_ISINKEN_MASK                 (0x20U)
+#define SPM_RFLDOSC_ISINKEN_SHIFT                (5U)
+/*! ISINKEN - ISINKEN
+ *  0b0..Disable current sink feature of low power regulator.
+ *  0b1..Enable current sink feature of low power regulator.
+ */
+#define SPM_RFLDOSC_ISINKEN(x)                   (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_ISINKEN_SHIFT)) & SPM_RFLDOSC_ISINKEN_MASK)
+#define SPM_RFLDOSC_IOTRIM_MASK                  (0x1F00U)
+#define SPM_RFLDOSC_IOTRIM_SHIFT                 (8U)
+#define SPM_RFLDOSC_IOTRIM(x)                    (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_IOTRIM_SHIFT)) & SPM_RFLDOSC_IOTRIM_MASK)
+#define SPM_RFLDOSC_IOSSSEL_MASK                 (0x70000U)
+#define SPM_RFLDOSC_IOSSSEL_SHIFT                (16U)
+/*! IOSSSEL - IO 1.8 Reg Soft Start Select
+ *  0b000..Soft Start duration set to 110us.
+ *  0b001..Soft Start duration set to 95us.
+ *  0b010..Soft Start duration set to 60us.
+ *  0b011..Soft Start duration set to 48us.
+ *  0b100..Soft Start duration set to 38us.
+ *  0b101..Soft Start duration set to 30us.
+ *  0b110..Soft Start duration set to 24us.
+ *  0b111..Soft Start duration set to 17us.
+ */
+#define SPM_RFLDOSC_IOSSSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_IOSSSEL_SHIFT)) & SPM_RFLDOSC_IOSSSEL_MASK)
+#define SPM_RFLDOSC_SSDONE_MASK                  (0x1000000U)
+#define SPM_RFLDOSC_SSDONE_SHIFT                 (24U)
+#define SPM_RFLDOSC_SSDONE(x)                    (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_SSDONE_SHIFT)) & SPM_RFLDOSC_SSDONE_MASK)
+#define SPM_RFLDOSC_IOSPARE_OUT_MASK             (0xC000000U)
+#define SPM_RFLDOSC_IOSPARE_OUT_SHIFT            (26U)
+#define SPM_RFLDOSC_IOSPARE_OUT(x)               (((uint32_t)(((uint32_t)(x)) << SPM_RFLDOSC_IOSPARE_OUT_SHIFT)) & SPM_RFLDOSC_IOSPARE_OUT_MASK)
+/*! @} */
+
+/*! @name DCDCSC - DCDC Status Control Register */
+/*! @{ */
+#define SPM_DCDCSC_DCDC_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U)
+#define SPM_DCDCSC_DCDC_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U)
+#define SPM_DCDCSC_DCDC_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & SPM_DCDCSC_DCDC_DISABLE_AUTO_CLK_SWITCH_MASK)
+#define SPM_DCDCSC_DCDC_SEL_CLK_MASK             (0x4U)
+#define SPM_DCDCSC_DCDC_SEL_CLK_SHIFT            (2U)
+#define SPM_DCDCSC_DCDC_SEL_CLK(x)               (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_SEL_CLK_SHIFT)) & SPM_DCDCSC_DCDC_SEL_CLK_MASK)
+#define SPM_DCDCSC_DCDC_PWD_OSC_INT_MASK         (0x8U)
+#define SPM_DCDCSC_DCDC_PWD_OSC_INT_SHIFT        (3U)
+#define SPM_DCDCSC_DCDC_PWD_OSC_INT(x)           (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_PWD_OSC_INT_SHIFT)) & SPM_DCDCSC_DCDC_PWD_OSC_INT_MASK)
+#define SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_MASK       (0xC00U)
+#define SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_SHIFT      (10U)
+/*! DCDC_VBAT_DIV_CTRL - DCDC_VBAT_DIV_CTRL
+ *  0b00..OFF
+ *  0b01..VBAT
+ *  0b10..VBAT / 2
+ *  0b11..VBAT / 4
+ */
+#define SPM_DCDCSC_DCDC_VBAT_DIV_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_SHIFT)) & SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_MASK)
+#define SPM_DCDCSC_DCDC_LESS_I_MASK              (0x2000000U)
+#define SPM_DCDCSC_DCDC_LESS_I_SHIFT             (25U)
+#define SPM_DCDCSC_DCDC_LESS_I(x)                (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_LESS_I_SHIFT)) & SPM_DCDCSC_DCDC_LESS_I_MASK)
+#define SPM_DCDCSC_PWD_CMP_OFFSET_MASK           (0x4000000U)
+#define SPM_DCDCSC_PWD_CMP_OFFSET_SHIFT          (26U)
+#define SPM_DCDCSC_PWD_CMP_OFFSET(x)             (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_PWD_CMP_OFFSET_SHIFT)) & SPM_DCDCSC_PWD_CMP_OFFSET_MASK)
+#define SPM_DCDCSC_CLKFLT_FAULT_MASK             (0x40000000U)
+#define SPM_DCDCSC_CLKFLT_FAULT_SHIFT            (30U)
+#define SPM_DCDCSC_CLKFLT_FAULT(x)               (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_CLKFLT_FAULT_SHIFT)) & SPM_DCDCSC_CLKFLT_FAULT_MASK)
+#define SPM_DCDCSC_DCDC_STS_DC_OK_MASK           (0x80000000U)
+#define SPM_DCDCSC_DCDC_STS_DC_OK_SHIFT          (31U)
+#define SPM_DCDCSC_DCDC_STS_DC_OK(x)             (((uint32_t)(((uint32_t)(x)) << SPM_DCDCSC_DCDC_STS_DC_OK_SHIFT)) & SPM_DCDCSC_DCDC_STS_DC_OK_MASK)
+/*! @} */
+
+/*! @name DCDCC1 - DCDC Control Register 1 */
+/*! @{ */
+#define SPM_DCDCC1_POSLIMIT_BUCK_IN_MASK         (0x7FU)
+#define SPM_DCDCC1_POSLIMIT_BUCK_IN_SHIFT        (0U)
+#define SPM_DCDCC1_POSLIMIT_BUCK_IN(x)           (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC1_POSLIMIT_BUCK_IN_SHIFT)) & SPM_DCDCC1_POSLIMIT_BUCK_IN_MASK)
+#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_CM_HYST_MASK (0x4000000U)
+#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_CM_HYST_SHIFT (26U)
+#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_CM_HYST(x)   (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC1_DCDC_LOOPCTRL_EN_CM_HYST_SHIFT)) & SPM_DCDCC1_DCDC_LOOPCTRL_EN_CM_HYST_MASK)
+#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_DF_HYST_MASK (0x8000000U)
+#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_DF_HYST_SHIFT (27U)
+#define SPM_DCDCC1_DCDC_LOOPCTRL_EN_DF_HYST(x)   (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC1_DCDC_LOOPCTRL_EN_DF_HYST_SHIFT)) & SPM_DCDCC1_DCDC_LOOPCTRL_EN_DF_HYST_MASK)
+/*! @} */
+
+/*! @name DCDCC2 - DCDC Control Register 2 */
+/*! @{ */
+#define SPM_DCDCC2_DCDC_LOOPCTRL_HYST_SIGN_MASK  (0x2000U)
+#define SPM_DCDCC2_DCDC_LOOPCTRL_HYST_SIGN_SHIFT (13U)
+#define SPM_DCDCC2_DCDC_LOOPCTRL_HYST_SIGN(x)    (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC2_DCDC_LOOPCTRL_HYST_SIGN_SHIFT)) & SPM_DCDCC2_DCDC_LOOPCTRL_HYST_SIGN_MASK)
+#define SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_MASK (0x8000U)
+#define SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_SHIFT (15U)
+#define SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_SHIFT)) & SPM_DCDCC2_DCDC_BATTMONITOR_EN_BATADJ_MASK)
+#define SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL_MASK (0x3FF0000U)
+#define SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL_SHIFT (16U)
+#define SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL(x)  (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL_SHIFT)) & SPM_DCDCC2_DCDC_BATTMONITOR_BATT_VAL_MASK)
+/*! @} */
+
+/*! @name DCDCC3 - DCDC Control Register 3 */
+/*! @{ */
+#define SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS_MASK     (0x1U)
+#define SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS_SHIFT    (0U)
+#define SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS(x)       (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS_SHIFT)) & SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS_MASK)
+#define SPM_DCDCC3_DCDC_VBAT_VALUE_MASK          (0x1CU)
+#define SPM_DCDCC3_DCDC_VBAT_VALUE_SHIFT         (2U)
+#define SPM_DCDCC3_DCDC_VBAT_VALUE(x)            (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_VBAT_VALUE_SHIFT)) & SPM_DCDCC3_DCDC_VBAT_VALUE_MASK)
+#define SPM_DCDCC3_DCDC_VDD1P2CTRL_ADJTN_MASK    (0xF0000U)
+#define SPM_DCDCC3_DCDC_VDD1P2CTRL_ADJTN_SHIFT   (16U)
+#define SPM_DCDCC3_DCDC_VDD1P2CTRL_ADJTN(x)      (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_VDD1P2CTRL_ADJTN_SHIFT)) & SPM_DCDCC3_DCDC_VDD1P2CTRL_ADJTN_MASK)
+#define SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_MASK   (0x1000000U)
+#define SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_SHIFT  (24U)
+#define SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK(x)     (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_SHIFT)) & SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_MASK)
+#define SPM_DCDCC3_DCDC_MINPWR_EXTRA_DOUBLE_FETS_MASK (0x2000000U)
+#define SPM_DCDCC3_DCDC_MINPWR_EXTRA_DOUBLE_FETS_SHIFT (25U)
+#define SPM_DCDCC3_DCDC_MINPWR_EXTRA_DOUBLE_FETS(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_MINPWR_EXTRA_DOUBLE_FETS_SHIFT)) & SPM_DCDCC3_DCDC_MINPWR_EXTRA_DOUBLE_FETS_MASK)
+#define SPM_DCDCC3_DCDC_MINPWR_DOUBLE_FETS_MASK  (0x4000000U)
+#define SPM_DCDCC3_DCDC_MINPWR_DOUBLE_FETS_SHIFT (26U)
+#define SPM_DCDCC3_DCDC_MINPWR_DOUBLE_FETS(x)    (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_MINPWR_DOUBLE_FETS_SHIFT)) & SPM_DCDCC3_DCDC_MINPWR_DOUBLE_FETS_MASK)
+#define SPM_DCDCC3_DCDC_MINPWR_HALF_FETS_MASK    (0x8000000U)
+#define SPM_DCDCC3_DCDC_MINPWR_HALF_FETS_SHIFT   (27U)
+#define SPM_DCDCC3_DCDC_MINPWR_HALF_FETS(x)      (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_MINPWR_HALF_FETS_SHIFT)) & SPM_DCDCC3_DCDC_MINPWR_HALF_FETS_MASK)
+#define SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABLE_STEP_MASK (0x40000000U)
+#define SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABLE_STEP_SHIFT (30U)
+#define SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABLE_STEP_SHIFT)) & SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABLE_STEP_MASK)
+#define SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP_MASK (0x80000000U)
+#define SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP_SHIFT (31U)
+#define SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP_SHIFT)) & SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP_MASK)
+/*! @} */
+
+/*! @name DCDCC4 - DCDC Control Register 4 */
+/*! @{ */
+#define SPM_DCDCC4_INTEGRATOR_VALUE_MASK         (0x7FFFFU)
+#define SPM_DCDCC4_INTEGRATOR_VALUE_SHIFT        (0U)
+#define SPM_DCDCC4_INTEGRATOR_VALUE(x)           (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC4_INTEGRATOR_VALUE_SHIFT)) & SPM_DCDCC4_INTEGRATOR_VALUE_MASK)
+#define SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_MASK  (0x80000U)
+#define SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_SHIFT (19U)
+/*! INTEGRATOR_VALUE_SELECT - INTEGRATOR VALUE SELECT
+ *  0b0..Select the saved value in hardware
+ *  0b1..Select the integrator value in this register
+ */
+#define SPM_DCDCC4_INTEGRATOR_VALUE_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_SHIFT)) & SPM_DCDCC4_INTEGRATOR_VALUE_SELECT_MASK)
+#define SPM_DCDCC4_PULSE_RUN_SPEEDUP_MASK        (0x100000U)
+#define SPM_DCDCC4_PULSE_RUN_SPEEDUP_SHIFT       (20U)
+#define SPM_DCDCC4_PULSE_RUN_SPEEDUP(x)          (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC4_PULSE_RUN_SPEEDUP_SHIFT)) & SPM_DCDCC4_PULSE_RUN_SPEEDUP_MASK)
+/*! @} */
+
+/*! @name DCDCC6 - DCDC Control Register 6 */
+/*! @{ */
+#define SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG_MASK      (0x1FU)
+#define SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG_SHIFT     (0U)
+#define SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG(x)        (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG_SHIFT)) & SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG_MASK)
+#define SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK_MASK (0xF00U)
+#define SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK_SHIFT (8U)
+#define SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK(x)   (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK_SHIFT)) & SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK_MASK)
+#define SPM_DCDCC6_DCDC_HSVDD_TRIM_MASK          (0xF000000U)
+#define SPM_DCDCC6_DCDC_HSVDD_TRIM_SHIFT         (24U)
+#define SPM_DCDCC6_DCDC_HSVDD_TRIM(x)            (((uint32_t)(((uint32_t)(x)) << SPM_DCDCC6_DCDC_HSVDD_TRIM_SHIFT)) & SPM_DCDCC6_DCDC_HSVDD_TRIM_MASK)
+/*! @} */
+
+/*! @name LPREQPINCNTRL - LP Request Pin Control Register */
+/*! @{ */
+#define SPM_LPREQPINCNTRL_LPREQOE_MASK           (0x1U)
+#define SPM_LPREQPINCNTRL_LPREQOE_SHIFT          (0U)
+/*! LPREQOE - Low Power Request Output Enable Register
+ *  0b0..Low Power request output pin not enabled.
+ *  0b1..Low Power request output pin enabled.
+ */
+#define SPM_LPREQPINCNTRL_LPREQOE(x)             (((uint32_t)(((uint32_t)(x)) << SPM_LPREQPINCNTRL_LPREQOE_SHIFT)) & SPM_LPREQPINCNTRL_LPREQOE_MASK)
+#define SPM_LPREQPINCNTRL_POLARITY_MASK          (0x2U)
+#define SPM_LPREQPINCNTRL_POLARITY_SHIFT         (1U)
+/*! POLARITY - Low Power Request Output Pin Polarity Control Register
+ *  0b0..High true polarity.
+ *  0b1..Low true polarity.
+ */
+#define SPM_LPREQPINCNTRL_POLARITY(x)            (((uint32_t)(((uint32_t)(x)) << SPM_LPREQPINCNTRL_POLARITY_SHIFT)) & SPM_LPREQPINCNTRL_POLARITY_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SPM_Register_Masks */
+
+
+/* SPM - Peripheral instance base addresses */
+/** Peripheral SPM base address */
+#define SPM_BASE                                 (0x40028000u)
+/** Peripheral SPM base pointer */
+#define SPM                                      ((SPM_Type *)SPM_BASE)
+/** Array initializer of SPM peripheral base addresses */
+#define SPM_BASE_ADDRS                           { SPM_BASE }
+/** Array initializer of SPM peripheral base pointers */
+#define SPM_BASE_PTRS                            { SPM }
+/** Interrupt vectors for the SPM peripheral type */
+#define SPM_IRQS                                 { SPM_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- TPM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
+ * @{
+ */
+
+/** TPM - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+  __IO uint32_t GLOBAL;                            /**< TPM Global Register, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t SC;                                /**< Status and Control, offset: 0x10 */
+  __IO uint32_t CNT;                               /**< Counter, offset: 0x14 */
+  __IO uint32_t MOD;                               /**< Modulo, offset: 0x18 */
+  __IO uint32_t STATUS;                            /**< Capture and Compare Status, offset: 0x1C */
+  struct {                                         /* offset: 0x20, array step: 0x8 */
+    __IO uint32_t CnSC;                              /**< Channel (n) Status and Control, array offset: 0x20, array step: 0x8 */
+    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x24, array step: 0x8 */
+  } CONTROLS[6];
+       uint8_t RESERVED_1[20];
+  __IO uint32_t COMBINE;                           /**< Combine Channel Register, offset: 0x64 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t TRIG;                              /**< Channel Trigger, offset: 0x6C */
+  __IO uint32_t POL;                               /**< Channel Polarity, offset: 0x70 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t FILTER;                            /**< Filter Control, offset: 0x78 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control and Status, offset: 0x80 */
+  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
+} TPM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- TPM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Register_Masks TPM Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define TPM_VERID_FEATURE_MASK                   (0xFFFFU)
+#define TPM_VERID_FEATURE_SHIFT                  (0U)
+/*! FEATURE - Feature Identification Number
+ *  0b0000000000000001..Standard feature set.
+ *  0b0000000000000011..Standard feature set with Filter and Combine registers implemented.
+ *  0b0000000000000111..Standard feature set with Filter, Combine and Quadrature registers implemented.
+ */
+#define TPM_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_VERID_FEATURE_SHIFT)) & TPM_VERID_FEATURE_MASK)
+#define TPM_VERID_MINOR_MASK                     (0xFF0000U)
+#define TPM_VERID_MINOR_SHIFT                    (16U)
+#define TPM_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MINOR_SHIFT)) & TPM_VERID_MINOR_MASK)
+#define TPM_VERID_MAJOR_MASK                     (0xFF000000U)
+#define TPM_VERID_MAJOR_SHIFT                    (24U)
+#define TPM_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MAJOR_SHIFT)) & TPM_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define TPM_PARAM_CHAN_MASK                      (0xFFU)
+#define TPM_PARAM_CHAN_SHIFT                     (0U)
+#define TPM_PARAM_CHAN(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_CHAN_SHIFT)) & TPM_PARAM_CHAN_MASK)
+#define TPM_PARAM_TRIG_MASK                      (0xFF00U)
+#define TPM_PARAM_TRIG_SHIFT                     (8U)
+#define TPM_PARAM_TRIG(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_TRIG_SHIFT)) & TPM_PARAM_TRIG_MASK)
+#define TPM_PARAM_WIDTH_MASK                     (0xFF0000U)
+#define TPM_PARAM_WIDTH_SHIFT                    (16U)
+#define TPM_PARAM_WIDTH(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_WIDTH_SHIFT)) & TPM_PARAM_WIDTH_MASK)
+/*! @} */
+
+/*! @name GLOBAL - TPM Global Register */
+/*! @{ */
+#define TPM_GLOBAL_NOUPDATE_MASK                 (0x1U)
+#define TPM_GLOBAL_NOUPDATE_SHIFT                (0U)
+/*! NOUPDATE - No Update
+ *  0b0..Internal double buffered registers update as normal.
+ *  0b1..Internal double buffered registers do not update.
+ */
+#define TPM_GLOBAL_NOUPDATE(x)                   (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_NOUPDATE_SHIFT)) & TPM_GLOBAL_NOUPDATE_MASK)
+#define TPM_GLOBAL_RST_MASK                      (0x2U)
+#define TPM_GLOBAL_RST_SHIFT                     (1U)
+/*! RST - Software Reset
+ *  0b0..Module is not reset.
+ *  0b1..Module is reset.
+ */
+#define TPM_GLOBAL_RST(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_RST_SHIFT)) & TPM_GLOBAL_RST_MASK)
+/*! @} */
+
+/*! @name SC - Status and Control */
+/*! @{ */
+#define TPM_SC_PS_MASK                           (0x7U)
+#define TPM_SC_PS_SHIFT                          (0U)
+/*! PS - Prescale Factor Selection
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 4
+ *  0b011..Divide by 8
+ *  0b100..Divide by 16
+ *  0b101..Divide by 32
+ *  0b110..Divide by 64
+ *  0b111..Divide by 128
+ */
+#define TPM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
+#define TPM_SC_CMOD_MASK                         (0x18U)
+#define TPM_SC_CMOD_SHIFT                        (3U)
+/*! CMOD - Clock Mode Selection
+ *  0b00..TPM counter is disabled
+ *  0b01..TPM counter increments on every TPM counter clock
+ *  0b10..TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock
+ *  0b11..TPM counter increments on rising edge of the selected external input trigger.
+ */
+#define TPM_SC_CMOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
+#define TPM_SC_CPWMS_MASK                        (0x20U)
+#define TPM_SC_CPWMS_SHIFT                       (5U)
+/*! CPWMS - Center-Aligned PWM Select
+ *  0b0..TPM counter operates in up counting mode.
+ *  0b1..TPM counter operates in up-down counting mode.
+ */
+#define TPM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
+#define TPM_SC_TOIE_MASK                         (0x40U)
+#define TPM_SC_TOIE_SHIFT                        (6U)
+/*! TOIE - Timer Overflow Interrupt Enable
+ *  0b0..Disable TOF interrupts. Use software polling or DMA request.
+ *  0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.
+ */
+#define TPM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
+#define TPM_SC_TOF_MASK                          (0x80U)
+#define TPM_SC_TOF_SHIFT                         (7U)
+/*! TOF - Timer Overflow Flag
+ *  0b0..TPM counter has not overflowed.
+ *  0b1..TPM counter has overflowed.
+ */
+#define TPM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
+#define TPM_SC_DMA_MASK                          (0x100U)
+#define TPM_SC_DMA_SHIFT                         (8U)
+/*! DMA - DMA Enable
+ *  0b0..Disables DMA transfers.
+ *  0b1..Enables DMA transfers.
+ */
+#define TPM_SC_DMA(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
+/*! @} */
+
+/*! @name CNT - Counter */
+/*! @{ */
+#define TPM_CNT_COUNT_MASK                       (0xFFFFU)
+#define TPM_CNT_COUNT_SHIFT                      (0U)
+#define TPM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
+/*! @} */
+
+/*! @name MOD - Modulo */
+/*! @{ */
+#define TPM_MOD_MOD_MASK                         (0xFFFFU)
+#define TPM_MOD_MOD_SHIFT                        (0U)
+#define TPM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
+/*! @} */
+
+/*! @name STATUS - Capture and Compare Status */
+/*! @{ */
+#define TPM_STATUS_CH0F_MASK                     (0x1U)
+#define TPM_STATUS_CH0F_SHIFT                    (0U)
+/*! CH0F - Channel 0 Flag
+ *  0b0..No channel event has occurred.
+ *  0b1..A channel event has occurred.
+ */
+#define TPM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
+#define TPM_STATUS_CH1F_MASK                     (0x2U)
+#define TPM_STATUS_CH1F_SHIFT                    (1U)
+/*! CH1F - Channel 1 Flag
+ *  0b0..No channel event has occurred.
+ *  0b1..A channel event has occurred.
+ */
+#define TPM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
+#define TPM_STATUS_CH2F_MASK                     (0x4U)
+#define TPM_STATUS_CH2F_SHIFT                    (2U)
+/*! CH2F - Channel 2 Flag
+ *  0b0..No channel event has occurred.
+ *  0b1..A channel event has occurred.
+ */
+#define TPM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK)
+#define TPM_STATUS_CH3F_MASK                     (0x8U)
+#define TPM_STATUS_CH3F_SHIFT                    (3U)
+/*! CH3F - Channel 3 Flag
+ *  0b0..No channel event has occurred.
+ *  0b1..A channel event has occurred.
+ */
+#define TPM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK)
+#define TPM_STATUS_CH4F_MASK                     (0x10U)
+#define TPM_STATUS_CH4F_SHIFT                    (4U)
+/*! CH4F - Channel 4 Flag
+ *  0b0..No channel event has occurred.
+ *  0b1..A channel event has occurred.
+ */
+#define TPM_STATUS_CH4F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK)
+#define TPM_STATUS_CH5F_MASK                     (0x20U)
+#define TPM_STATUS_CH5F_SHIFT                    (5U)
+/*! CH5F - Channel 5 Flag
+ *  0b0..No channel event has occurred.
+ *  0b1..A channel event has occurred.
+ */
+#define TPM_STATUS_CH5F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK)
+#define TPM_STATUS_TOF_MASK                      (0x100U)
+#define TPM_STATUS_TOF_SHIFT                     (8U)
+/*! TOF - Timer Overflow Flag
+ *  0b0..TPM counter has not overflowed.
+ *  0b1..TPM counter has overflowed.
+ */
+#define TPM_STATUS_TOF(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
+/*! @} */
+
+/*! @name CnSC - Channel (n) Status and Control */
+/*! @{ */
+#define TPM_CnSC_DMA_MASK                        (0x1U)
+#define TPM_CnSC_DMA_SHIFT                       (0U)
+/*! DMA - DMA Enable
+ *  0b0..Disable DMA transfers.
+ *  0b1..Enable DMA transfers.
+ */
+#define TPM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
+#define TPM_CnSC_ELSA_MASK                       (0x4U)
+#define TPM_CnSC_ELSA_SHIFT                      (2U)
+#define TPM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
+#define TPM_CnSC_ELSB_MASK                       (0x8U)
+#define TPM_CnSC_ELSB_SHIFT                      (3U)
+#define TPM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
+#define TPM_CnSC_MSA_MASK                        (0x10U)
+#define TPM_CnSC_MSA_SHIFT                       (4U)
+#define TPM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
+#define TPM_CnSC_MSB_MASK                        (0x20U)
+#define TPM_CnSC_MSB_SHIFT                       (5U)
+#define TPM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
+#define TPM_CnSC_CHIE_MASK                       (0x40U)
+#define TPM_CnSC_CHIE_SHIFT                      (6U)
+/*! CHIE - Channel Interrupt Enable
+ *  0b0..Disable channel interrupts.
+ *  0b1..Enable channel interrupts.
+ */
+#define TPM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
+#define TPM_CnSC_CHF_MASK                        (0x80U)
+#define TPM_CnSC_CHF_SHIFT                       (7U)
+/*! CHF - Channel Flag
+ *  0b0..No channel event has occurred.
+ *  0b1..A channel event has occurred.
+ */
+#define TPM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
+/*! @} */
+
+/* The count of TPM_CnSC */
+#define TPM_CnSC_COUNT                           (6U)
+
+/*! @name CnV - Channel (n) Value */
+/*! @{ */
+#define TPM_CnV_VAL_MASK                         (0xFFFFU)
+#define TPM_CnV_VAL_SHIFT                        (0U)
+#define TPM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
+/*! @} */
+
+/* The count of TPM_CnV */
+#define TPM_CnV_COUNT                            (6U)
+
+/*! @name COMBINE - Combine Channel Register */
+/*! @{ */
+#define TPM_COMBINE_COMBINE0_MASK                (0x1U)
+#define TPM_COMBINE_COMBINE0_SHIFT               (0U)
+/*! COMBINE0 - Combine Channels 0 and 1
+ *  0b0..Channels 0 and 1 are independent.
+ *  0b1..Channels 0 and 1 are combined.
+ */
+#define TPM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)
+#define TPM_COMBINE_COMSWAP0_MASK                (0x2U)
+#define TPM_COMBINE_COMSWAP0_SHIFT               (1U)
+/*! COMSWAP0 - Combine Channel 0 and 1 Swap
+ *  0b0..Even channel is used for input capture and 1st compare.
+ *  0b1..Odd channel is used for input capture and 1st compare.
+ */
+#define TPM_COMBINE_COMSWAP0(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)
+#define TPM_COMBINE_COMBINE1_MASK                (0x100U)
+#define TPM_COMBINE_COMBINE1_SHIFT               (8U)
+/*! COMBINE1 - Combine Channels 2 and 3
+ *  0b0..Channels 2 and 3 are independent.
+ *  0b1..Channels 2 and 3 are combined.
+ */
+#define TPM_COMBINE_COMBINE1(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE1_SHIFT)) & TPM_COMBINE_COMBINE1_MASK)
+#define TPM_COMBINE_COMSWAP1_MASK                (0x200U)
+#define TPM_COMBINE_COMSWAP1_SHIFT               (9U)
+/*! COMSWAP1 - Combine Channels 2 and 3 Swap
+ *  0b0..Even channel is used for input capture and 1st compare.
+ *  0b1..Odd channel is used for input capture and 1st compare.
+ */
+#define TPM_COMBINE_COMSWAP1(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP1_SHIFT)) & TPM_COMBINE_COMSWAP1_MASK)
+#define TPM_COMBINE_COMBINE2_MASK                (0x10000U)
+#define TPM_COMBINE_COMBINE2_SHIFT               (16U)
+/*! COMBINE2 - Combine Channels 4 and 5
+ *  0b0..Channels 4 and 5 are independent.
+ *  0b1..Channels 4 and 5 are combined.
+ */
+#define TPM_COMBINE_COMBINE2(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE2_SHIFT)) & TPM_COMBINE_COMBINE2_MASK)
+#define TPM_COMBINE_COMSWAP2_MASK                (0x20000U)
+#define TPM_COMBINE_COMSWAP2_SHIFT               (17U)
+/*! COMSWAP2 - Combine Channels 4 and 5 Swap
+ *  0b0..Even channel is used for input capture and 1st compare.
+ *  0b1..Odd channel is used for input capture and 1st compare.
+ */
+#define TPM_COMBINE_COMSWAP2(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP2_SHIFT)) & TPM_COMBINE_COMSWAP2_MASK)
+/*! @} */
+
+/*! @name TRIG - Channel Trigger */
+/*! @{ */
+#define TPM_TRIG_TRIG0_MASK                      (0x1U)
+#define TPM_TRIG_TRIG0_SHIFT                     (0U)
+/*! TRIG0 - Channel 0 Trigger
+ *  0b0..No effect.
+ *  0b1..Configures trigger input 0 to be used by channel 0.
+ */
+#define TPM_TRIG_TRIG0(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG0_SHIFT)) & TPM_TRIG_TRIG0_MASK)
+#define TPM_TRIG_TRIG1_MASK                      (0x2U)
+#define TPM_TRIG_TRIG1_SHIFT                     (1U)
+/*! TRIG1 - Channel 1 Trigger
+ *  0b0..No effect.
+ *  0b1..Configures trigger input 1 to be used by channel 1.
+ */
+#define TPM_TRIG_TRIG1(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG1_SHIFT)) & TPM_TRIG_TRIG1_MASK)
+#define TPM_TRIG_TRIG2_MASK                      (0x4U)
+#define TPM_TRIG_TRIG2_SHIFT                     (2U)
+/*! TRIG2 - Channel 2 Trigger
+ *  0b0..No effect.
+ *  0b1..Configures trigger input 0 to be used by channel 2.
+ */
+#define TPM_TRIG_TRIG2(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG2_SHIFT)) & TPM_TRIG_TRIG2_MASK)
+#define TPM_TRIG_TRIG3_MASK                      (0x8U)
+#define TPM_TRIG_TRIG3_SHIFT                     (3U)
+/*! TRIG3 - Channel 3 Trigger
+ *  0b0..No effect.
+ *  0b1..Configures trigger input 1 to be used by channel 3.
+ */
+#define TPM_TRIG_TRIG3(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG3_SHIFT)) & TPM_TRIG_TRIG3_MASK)
+#define TPM_TRIG_TRIG4_MASK                      (0x10U)
+#define TPM_TRIG_TRIG4_SHIFT                     (4U)
+/*! TRIG4 - Channel 4 Trigger
+ *  0b0..No effect.
+ *  0b1..Configures trigger input 0 to be used by channel 4.
+ */
+#define TPM_TRIG_TRIG4(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG4_SHIFT)) & TPM_TRIG_TRIG4_MASK)
+#define TPM_TRIG_TRIG5_MASK                      (0x20U)
+#define TPM_TRIG_TRIG5_SHIFT                     (5U)
+/*! TRIG5 - Channel 5 Trigger
+ *  0b0..No effect.
+ *  0b1..Configures trigger input 1 to be used by channel 5.
+ */
+#define TPM_TRIG_TRIG5(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG5_SHIFT)) & TPM_TRIG_TRIG5_MASK)
+/*! @} */
+
+/*! @name POL - Channel Polarity */
+/*! @{ */
+#define TPM_POL_POL0_MASK                        (0x1U)
+#define TPM_POL_POL0_SHIFT                       (0U)
+/*! POL0 - Channel 0 Polarity
+ *  0b0..The channel polarity is active high.
+ *  0b1..The channel polarity is active low.
+ */
+#define TPM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)
+#define TPM_POL_POL1_MASK                        (0x2U)
+#define TPM_POL_POL1_SHIFT                       (1U)
+/*! POL1 - Channel 1 Polarity
+ *  0b0..The channel polarity is active high.
+ *  0b1..The channel polarity is active low.
+ */
+#define TPM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)
+#define TPM_POL_POL2_MASK                        (0x4U)
+#define TPM_POL_POL2_SHIFT                       (2U)
+/*! POL2 - Channel 2 Polarity
+ *  0b0..The channel polarity is active high.
+ *  0b1..The channel polarity is active low.
+ */
+#define TPM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK)
+#define TPM_POL_POL3_MASK                        (0x8U)
+#define TPM_POL_POL3_SHIFT                       (3U)
+/*! POL3 - Channel 3 Polarity
+ *  0b0..The channel polarity is active high.
+ *  0b1..The channel polarity is active low.
+ */
+#define TPM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK)
+#define TPM_POL_POL4_MASK                        (0x10U)
+#define TPM_POL_POL4_SHIFT                       (4U)
+/*! POL4 - Channel 4 Polarity
+ *  0b0..The channel polarity is active high
+ *  0b1..The channel polarity is active low.
+ */
+#define TPM_POL_POL4(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL4_SHIFT)) & TPM_POL_POL4_MASK)
+#define TPM_POL_POL5_MASK                        (0x20U)
+#define TPM_POL_POL5_SHIFT                       (5U)
+/*! POL5 - Channel 5 Polarity
+ *  0b0..The channel polarity is active high.
+ *  0b1..The channel polarity is active low.
+ */
+#define TPM_POL_POL5(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL5_SHIFT)) & TPM_POL_POL5_MASK)
+/*! @} */
+
+/*! @name FILTER - Filter Control */
+/*! @{ */
+#define TPM_FILTER_CH0FVAL_MASK                  (0xFU)
+#define TPM_FILTER_CH0FVAL_SHIFT                 (0U)
+#define TPM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)
+#define TPM_FILTER_CH1FVAL_MASK                  (0xF0U)
+#define TPM_FILTER_CH1FVAL_SHIFT                 (4U)
+#define TPM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)
+#define TPM_FILTER_CH2FVAL_MASK                  (0xF00U)
+#define TPM_FILTER_CH2FVAL_SHIFT                 (8U)
+#define TPM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH2FVAL_SHIFT)) & TPM_FILTER_CH2FVAL_MASK)
+#define TPM_FILTER_CH3FVAL_MASK                  (0xF000U)
+#define TPM_FILTER_CH3FVAL_SHIFT                 (12U)
+#define TPM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH3FVAL_SHIFT)) & TPM_FILTER_CH3FVAL_MASK)
+#define TPM_FILTER_CH4FVAL_MASK                  (0xF0000U)
+#define TPM_FILTER_CH4FVAL_SHIFT                 (16U)
+#define TPM_FILTER_CH4FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH4FVAL_SHIFT)) & TPM_FILTER_CH4FVAL_MASK)
+#define TPM_FILTER_CH5FVAL_MASK                  (0xF00000U)
+#define TPM_FILTER_CH5FVAL_SHIFT                 (20U)
+#define TPM_FILTER_CH5FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH5FVAL_SHIFT)) & TPM_FILTER_CH5FVAL_MASK)
+/*! @} */
+
+/*! @name QDCTRL - Quadrature Decoder Control and Status */
+/*! @{ */
+#define TPM_QDCTRL_QUADEN_MASK                   (0x1U)
+#define TPM_QDCTRL_QUADEN_SHIFT                  (0U)
+/*! QUADEN - QUADEN
+ *  0b0..Quadrature decoder mode is disabled.
+ *  0b1..Quadrature decoder mode is enabled.
+ */
+#define TPM_QDCTRL_QUADEN(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)
+#define TPM_QDCTRL_TOFDIR_MASK                   (0x2U)
+#define TPM_QDCTRL_TOFDIR_SHIFT                  (1U)
+/*! TOFDIR - TOFDIR
+ *  0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register).
+ *  0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero).
+ */
+#define TPM_QDCTRL_TOFDIR(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)
+#define TPM_QDCTRL_QUADIR_MASK                   (0x4U)
+#define TPM_QDCTRL_QUADIR_SHIFT                  (2U)
+/*! QUADIR - Counter Direction in Quadrature Decode Mode
+ *  0b0..Counter direction is decreasing (counter decrement).
+ *  0b1..Counter direction is increasing (counter increment).
+ */
+#define TPM_QDCTRL_QUADIR(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)
+#define TPM_QDCTRL_QUADMODE_MASK                 (0x8U)
+#define TPM_QDCTRL_QUADMODE_SHIFT                (3U)
+/*! QUADMODE - Quadrature Decoder Mode
+ *  0b0..Phase encoding mode.
+ *  0b1..Count and direction encoding mode.
+ */
+#define TPM_QDCTRL_QUADMODE(x)                   (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)
+/*! @} */
+
+/*! @name CONF - Configuration */
+/*! @{ */
+#define TPM_CONF_DOZEEN_MASK                     (0x20U)
+#define TPM_CONF_DOZEEN_SHIFT                    (5U)
+/*! DOZEEN - Doze Enable
+ *  0b0..Internal TPM counter continues in Doze mode.
+ *  0b1..Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are ignored, and PWM outputs are forced to their default state.
+ */
+#define TPM_CONF_DOZEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
+#define TPM_CONF_DBGMODE_MASK                    (0xC0U)
+#define TPM_CONF_DBGMODE_SHIFT                   (6U)
+/*! DBGMODE - Debug Mode
+ *  0b00..TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are ignored, and PWM outputs are forced to their default state.
+ *  0b11..TPM counter continues in debug mode.
+ */
+#define TPM_CONF_DBGMODE(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
+#define TPM_CONF_GTBSYNC_MASK                    (0x100U)
+#define TPM_CONF_GTBSYNC_SHIFT                   (8U)
+/*! GTBSYNC - Global Time Base Synchronization
+ *  0b0..Global timebase synchronization disabled.
+ *  0b1..Global timebase synchronization enabled.
+ */
+#define TPM_CONF_GTBSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)
+#define TPM_CONF_GTBEEN_MASK                     (0x200U)
+#define TPM_CONF_GTBEEN_SHIFT                    (9U)
+/*! GTBEEN - Global time base enable
+ *  0b0..All channels use the internally generated TPM counter as their timebase
+ *  0b1..All channels use an externally generated global timebase as their timebase
+ */
+#define TPM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
+#define TPM_CONF_CSOT_MASK                       (0x10000U)
+#define TPM_CONF_CSOT_SHIFT                      (16U)
+/*! CSOT - Counter Start on Trigger
+ *  0b0..TPM counter starts to increment immediately, once it is enabled.
+ *  0b1..TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.
+ */
+#define TPM_CONF_CSOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
+#define TPM_CONF_CSOO_MASK                       (0x20000U)
+#define TPM_CONF_CSOO_SHIFT                      (17U)
+/*! CSOO - Counter Stop On Overflow
+ *  0b0..TPM counter continues incrementing or decrementing after overflow
+ *  0b1..TPM counter stops incrementing or decrementing after overflow.
+ */
+#define TPM_CONF_CSOO(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
+#define TPM_CONF_CROT_MASK                       (0x40000U)
+#define TPM_CONF_CROT_SHIFT                      (18U)
+/*! CROT - Counter Reload On Trigger
+ *  0b0..Counter is not reloaded due to a rising edge on the selected input trigger
+ *  0b1..Counter is reloaded when a rising edge is detected on the selected input trigger
+ */
+#define TPM_CONF_CROT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
+#define TPM_CONF_CPOT_MASK                       (0x80000U)
+#define TPM_CONF_CPOT_SHIFT                      (19U)
+#define TPM_CONF_CPOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)
+#define TPM_CONF_TRGPOL_MASK                     (0x400000U)
+#define TPM_CONF_TRGPOL_SHIFT                    (22U)
+/*! TRGPOL - Trigger Polarity
+ *  0b0..Trigger is active high.
+ *  0b1..Trigger is active low.
+ */
+#define TPM_CONF_TRGPOL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)
+#define TPM_CONF_TRGSRC_MASK                     (0x800000U)
+#define TPM_CONF_TRGSRC_SHIFT                    (23U)
+/*! TRGSRC - Trigger Source
+ *  0b0..Trigger source selected by TRGSEL is external.
+ *  0b1..Trigger source selected by TRGSEL is internal (channel pin input capture).
+ */
+#define TPM_CONF_TRGSRC(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)
+#define TPM_CONF_TRGSEL_MASK                     (0x3000000U)
+#define TPM_CONF_TRGSEL_SHIFT                    (24U)
+/*! TRGSEL - Trigger Select
+ *  0b01..Channel 0 pin input capture
+ *  0b10..Channel 1 pin input capture
+ *  0b11..Channel 0 or Channel 1 pin input capture
+ */
+#define TPM_CONF_TRGSEL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group TPM_Register_Masks */
+
+
+/* TPM - Peripheral instance base addresses */
+/** Peripheral TPM0 base address */
+#define TPM0_BASE                                (0x40035000u)
+/** Peripheral TPM0 base pointer */
+#define TPM0                                     ((TPM_Type *)TPM0_BASE)
+/** Peripheral TPM1 base address */
+#define TPM1_BASE                                (0x40036000u)
+/** Peripheral TPM1 base pointer */
+#define TPM1                                     ((TPM_Type *)TPM1_BASE)
+/** Peripheral TPM2 base address */
+#define TPM2_BASE                                (0x40037000u)
+/** Peripheral TPM2 base pointer */
+#define TPM2                                     ((TPM_Type *)TPM2_BASE)
+/** Peripheral TPM3 base address */
+#define TPM3_BASE                                (0x4102D000u)
+/** Peripheral TPM3 base pointer */
+#define TPM3                                     ((TPM_Type *)TPM3_BASE)
+/** Array initializer of TPM peripheral base addresses */
+#define TPM_BASE_ADDRS                           { TPM0_BASE, TPM1_BASE, TPM2_BASE, TPM3_BASE }
+/** Array initializer of TPM peripheral base pointers */
+#define TPM_BASE_PTRS                            { TPM0, TPM1, TPM2, TPM3 }
+/** Interrupt vectors for the TPM peripheral type */
+#define TPM_IRQS                                 { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn, TPM3_IRQn }
+
+/*!
+ * @}
+ */ /* end of group TPM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- TRGMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TRGMUX_Peripheral_Access_Layer TRGMUX Peripheral Access Layer
+ * @{
+ */
+
+/** TRGMUX - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TRGCFG[25];                        /**< TRGMUX TRGMUX_DMAMUX0 Register..TRGMUX TRGMUX_LPDAC0 Register, array offset: 0x0, array step: 0x4 */
+} TRGMUX_Type;
+
+/* ----------------------------------------------------------------------------
+   -- TRGMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TRGMUX_Register_Masks TRGMUX Register Masks
+ * @{
+ */
+
+/*! @name TRGCFG - TRGMUX TRGMUX_DMAMUX0 Register..TRGMUX TRGMUX_LPDAC0 Register */
+/*! @{ */
+#define TRGMUX_TRGCFG_SEL0_MASK                  (0x3FU)
+#define TRGMUX_TRGCFG_SEL0_SHIFT                 (0U)
+#define TRGMUX_TRGCFG_SEL0(x)                    (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL0_SHIFT)) & TRGMUX_TRGCFG_SEL0_MASK)
+#define TRGMUX_TRGCFG_SEL1_MASK                  (0x3F00U)
+#define TRGMUX_TRGCFG_SEL1_SHIFT                 (8U)
+#define TRGMUX_TRGCFG_SEL1(x)                    (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL1_SHIFT)) & TRGMUX_TRGCFG_SEL1_MASK)
+#define TRGMUX_TRGCFG_SEL2_MASK                  (0x3F0000U)
+#define TRGMUX_TRGCFG_SEL2_SHIFT                 (16U)
+#define TRGMUX_TRGCFG_SEL2(x)                    (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL2_SHIFT)) & TRGMUX_TRGCFG_SEL2_MASK)
+#define TRGMUX_TRGCFG_SEL3_MASK                  (0x3F000000U)
+#define TRGMUX_TRGCFG_SEL3_SHIFT                 (24U)
+#define TRGMUX_TRGCFG_SEL3(x)                    (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL3_SHIFT)) & TRGMUX_TRGCFG_SEL3_MASK)
+#define TRGMUX_TRGCFG_LK_MASK                    (0x80000000U)
+#define TRGMUX_TRGCFG_LK_SHIFT                   (31U)
+/*! LK - TRGMUX register lock.
+ *  0b0..Register can be written.
+ *  0b1..Register cannot be written until the next system Reset.
+ */
+#define TRGMUX_TRGCFG_LK(x)                      (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_LK_SHIFT)) & TRGMUX_TRGCFG_LK_MASK)
+/*! @} */
+
+/* The count of TRGMUX_TRGCFG */
+#define TRGMUX_TRGCFG_COUNT                      (25U)
+
+
+/*!
+ * @}
+ */ /* end of group TRGMUX_Register_Masks */
+
+
+/* TRGMUX - Peripheral instance base addresses */
+/** Peripheral TRGMUX0 base address */
+#define TRGMUX0_BASE                             (0x40029000u)
+/** Peripheral TRGMUX0 base pointer */
+#define TRGMUX0                                  ((TRGMUX_Type *)TRGMUX0_BASE)
+/** Peripheral TRGMUX1 base address */
+#define TRGMUX1_BASE                             (0x41025000u)
+/** Peripheral TRGMUX1 base pointer */
+#define TRGMUX1                                  ((TRGMUX_Type *)TRGMUX1_BASE)
+/** Array initializer of TRGMUX peripheral base addresses */
+#define TRGMUX_BASE_ADDRS                        { TRGMUX0_BASE, TRGMUX1_BASE }
+/** Array initializer of TRGMUX peripheral base pointers */
+#define TRGMUX_BASE_PTRS                         { TRGMUX0, TRGMUX1 }
+
+/*!
+ * @}
+ */ /* end of group TRGMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- TRNG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer
+ * @{
+ */
+
+/** TRNG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCTL;                              /**< Miscellaneous Control Register, offset: 0x0 */
+  __IO uint32_t SCMISC;                            /**< Statistical Check Miscellaneous Register, offset: 0x4 */
+  __IO uint32_t PKRRNG;                            /**< Poker Range Register, offset: 0x8 */
+  union {                                          /* offset: 0xC */
+    __IO uint32_t PKRMAX;                            /**< Poker Maximum Limit Register, offset: 0xC */
+    __I  uint32_t PKRSQ;                             /**< Poker Square Calculation Result Register, offset: 0xC */
+  };
+  __IO uint32_t SDCTL;                             /**< Seed Control Register, offset: 0x10 */
+  union {                                          /* offset: 0x14 */
+    __IO uint32_t SBLIM;                             /**< Sparse Bit Limit Register, offset: 0x14 */
+    __I  uint32_t TOTSAM;                            /**< Total Samples Register, offset: 0x14 */
+  };
+  __IO uint32_t FRQMIN;                            /**< Frequency Count Minimum Limit Register, offset: 0x18 */
+  union {                                          /* offset: 0x1C */
+    __I  uint32_t FRQCNT;                            /**< Frequency Count Register, offset: 0x1C */
+    __IO uint32_t FRQMAX;                            /**< Frequency Count Maximum Limit Register, offset: 0x1C */
+  };
+  union {                                          /* offset: 0x20 */
+    __I  uint32_t SCMC;                              /**< Statistical Check Monobit Count Register, offset: 0x20 */
+    __IO uint32_t SCML;                              /**< Statistical Check Monobit Limit Register, offset: 0x20 */
+  };
+  union {                                          /* offset: 0x24 */
+    __I  uint32_t SCR1C;                             /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */
+    __IO uint32_t SCR1L;                             /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */
+  };
+  union {                                          /* offset: 0x28 */
+    __I  uint32_t SCR2C;                             /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */
+    __IO uint32_t SCR2L;                             /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */
+  };
+  union {                                          /* offset: 0x2C */
+    __I  uint32_t SCR3C;                             /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */
+    __IO uint32_t SCR3L;                             /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */
+  };
+  union {                                          /* offset: 0x30 */
+    __I  uint32_t SCR4C;                             /**< Statistical Check Run Length 4 Count Register, offset: 0x30 */
+    __IO uint32_t SCR4L;                             /**< Statistical Check Run Length 4 Limit Register, offset: 0x30 */
+  };
+  union {                                          /* offset: 0x34 */
+    __I  uint32_t SCR5C;                             /**< Statistical Check Run Length 5 Count Register, offset: 0x34 */
+    __IO uint32_t SCR5L;                             /**< Statistical Check Run Length 5 Limit Register, offset: 0x34 */
+  };
+  union {                                          /* offset: 0x38 */
+    __I  uint32_t SCR6PC;                            /**< Statistical Check Run Length 6+ Count Register, offset: 0x38 */
+    __IO uint32_t SCR6PL;                            /**< Statistical Check Run Length 6+ Limit Register, offset: 0x38 */
+  };
+  __I  uint32_t STATUS;                            /**< Status Register, offset: 0x3C */
+  __I  uint32_t ENT[16];                           /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */
+  __I  uint32_t PKRCNT10;                          /**< Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */
+  __I  uint32_t PKRCNT32;                          /**< Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */
+  __I  uint32_t PKRCNT54;                          /**< Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */
+  __I  uint32_t PKRCNT76;                          /**< Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */
+  __I  uint32_t PKRCNT98;                          /**< Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */
+  __I  uint32_t PKRCNTBA;                          /**< Statistical Check Poker Count B and A Register, offset: 0x94 */
+  __I  uint32_t PKRCNTDC;                          /**< Statistical Check Poker Count D and C Register, offset: 0x98 */
+  __I  uint32_t PKRCNTFE;                          /**< Statistical Check Poker Count F and E Register, offset: 0x9C */
+  __IO uint32_t SEC_CFG;                           /**< Security Configuration Register, offset: 0xA0 */
+  __IO uint32_t INT_CTRL;                          /**< Interrupt Control Register, offset: 0xA4 */
+  __IO uint32_t INT_MASK;                          /**< Mask Register, offset: 0xA8 */
+  __I  uint32_t INT_STATUS;                        /**< Interrupt Status Register, offset: 0xAC */
+       uint8_t RESERVED_0[64];
+  __I  uint32_t VID1;                              /**< Version ID Register (MS), offset: 0xF0 */
+  __I  uint32_t VID2;                              /**< Version ID Register (LS), offset: 0xF4 */
+} TRNG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- TRNG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TRNG_Register_Masks TRNG Register Masks
+ * @{
+ */
+
+/*! @name MCTL - Miscellaneous Control Register */
+/*! @{ */
+#define TRNG_MCTL_SAMP_MODE_MASK                 (0x3U)
+#define TRNG_MCTL_SAMP_MODE_SHIFT                (0U)
+/*! SAMP_MODE
+ *  0b00..use Von Neumann data into both Entropy shifter and Statistical Checker
+ *  0b01..use raw data into both Entropy shifter and Statistical Checker
+ *  0b10..use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker
+ *  0b11..undefined/reserved.
+ */
+#define TRNG_MCTL_SAMP_MODE(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)
+#define TRNG_MCTL_OSC_DIV_MASK                   (0xCU)
+#define TRNG_MCTL_OSC_DIV_SHIFT                  (2U)
+/*! OSC_DIV
+ *  0b00..use ring oscillator with no divide
+ *  0b01..use ring oscillator divided-by-2
+ *  0b10..use ring oscillator divided-by-4
+ *  0b11..use ring oscillator divided-by-8
+ */
+#define TRNG_MCTL_OSC_DIV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
+#define TRNG_MCTL_UNUSED4_MASK                   (0x10U)
+#define TRNG_MCTL_UNUSED4_SHIFT                  (4U)
+#define TRNG_MCTL_UNUSED4(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK)
+#define TRNG_MCTL_TRNG_ACC_MASK                  (0x20U)
+#define TRNG_MCTL_TRNG_ACC_SHIFT                 (5U)
+#define TRNG_MCTL_TRNG_ACC(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK)
+#define TRNG_MCTL_RST_DEF_MASK                   (0x40U)
+#define TRNG_MCTL_RST_DEF_SHIFT                  (6U)
+#define TRNG_MCTL_RST_DEF(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)
+#define TRNG_MCTL_FOR_SCLK_MASK                  (0x80U)
+#define TRNG_MCTL_FOR_SCLK_SHIFT                 (7U)
+#define TRNG_MCTL_FOR_SCLK(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)
+#define TRNG_MCTL_FCT_FAIL_MASK                  (0x100U)
+#define TRNG_MCTL_FCT_FAIL_SHIFT                 (8U)
+#define TRNG_MCTL_FCT_FAIL(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)
+#define TRNG_MCTL_FCT_VAL_MASK                   (0x200U)
+#define TRNG_MCTL_FCT_VAL_SHIFT                  (9U)
+#define TRNG_MCTL_FCT_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)
+#define TRNG_MCTL_ENT_VAL_MASK                   (0x400U)
+#define TRNG_MCTL_ENT_VAL_SHIFT                  (10U)
+#define TRNG_MCTL_ENT_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)
+#define TRNG_MCTL_TST_OUT_MASK                   (0x800U)
+#define TRNG_MCTL_TST_OUT_SHIFT                  (11U)
+#define TRNG_MCTL_TST_OUT(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)
+#define TRNG_MCTL_ERR_MASK                       (0x1000U)
+#define TRNG_MCTL_ERR_SHIFT                      (12U)
+#define TRNG_MCTL_ERR(x)                         (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)
+#define TRNG_MCTL_TSTOP_OK_MASK                  (0x2000U)
+#define TRNG_MCTL_TSTOP_OK_SHIFT                 (13U)
+#define TRNG_MCTL_TSTOP_OK(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)
+#define TRNG_MCTL_PRGM_MASK                      (0x10000U)
+#define TRNG_MCTL_PRGM_SHIFT                     (16U)
+#define TRNG_MCTL_PRGM(x)                        (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
+/*! @} */
+
+/*! @name SCMISC - Statistical Check Miscellaneous Register */
+/*! @{ */
+#define TRNG_SCMISC_LRUN_MAX_MASK                (0xFFU)
+#define TRNG_SCMISC_LRUN_MAX_SHIFT               (0U)
+#define TRNG_SCMISC_LRUN_MAX(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)
+#define TRNG_SCMISC_RTY_CT_MASK                  (0xF0000U)
+#define TRNG_SCMISC_RTY_CT_SHIFT                 (16U)
+#define TRNG_SCMISC_RTY_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
+/*! @} */
+
+/*! @name PKRRNG - Poker Range Register */
+/*! @{ */
+#define TRNG_PKRRNG_PKR_RNG_MASK                 (0xFFFFU)
+#define TRNG_PKRRNG_PKR_RNG_SHIFT                (0U)
+#define TRNG_PKRRNG_PKR_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)
+/*! @} */
+
+/*! @name PKRMAX - Poker Maximum Limit Register */
+/*! @{ */
+#define TRNG_PKRMAX_PKR_MAX_MASK                 (0xFFFFFFU)
+#define TRNG_PKRMAX_PKR_MAX_SHIFT                (0U)
+#define TRNG_PKRMAX_PKR_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)
+/*! @} */
+
+/*! @name PKRSQ - Poker Square Calculation Result Register */
+/*! @{ */
+#define TRNG_PKRSQ_PKR_SQ_MASK                   (0xFFFFFFU)
+#define TRNG_PKRSQ_PKR_SQ_SHIFT                  (0U)
+#define TRNG_PKRSQ_PKR_SQ(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)
+/*! @} */
+
+/*! @name SDCTL - Seed Control Register */
+/*! @{ */
+#define TRNG_SDCTL_SAMP_SIZE_MASK                (0xFFFFU)
+#define TRNG_SDCTL_SAMP_SIZE_SHIFT               (0U)
+#define TRNG_SDCTL_SAMP_SIZE(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)
+#define TRNG_SDCTL_ENT_DLY_MASK                  (0xFFFF0000U)
+#define TRNG_SDCTL_ENT_DLY_SHIFT                 (16U)
+#define TRNG_SDCTL_ENT_DLY(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
+/*! @} */
+
+/*! @name SBLIM - Sparse Bit Limit Register */
+/*! @{ */
+#define TRNG_SBLIM_SB_LIM_MASK                   (0x3FFU)
+#define TRNG_SBLIM_SB_LIM_SHIFT                  (0U)
+#define TRNG_SBLIM_SB_LIM(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)
+/*! @} */
+
+/*! @name TOTSAM - Total Samples Register */
+/*! @{ */
+#define TRNG_TOTSAM_TOT_SAM_MASK                 (0xFFFFFU)
+#define TRNG_TOTSAM_TOT_SAM_SHIFT                (0U)
+#define TRNG_TOTSAM_TOT_SAM(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)
+/*! @} */
+
+/*! @name FRQMIN - Frequency Count Minimum Limit Register */
+/*! @{ */
+#define TRNG_FRQMIN_FRQ_MIN_MASK                 (0x3FFFFFU)
+#define TRNG_FRQMIN_FRQ_MIN_SHIFT                (0U)
+#define TRNG_FRQMIN_FRQ_MIN(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
+/*! @} */
+
+/*! @name FRQCNT - Frequency Count Register */
+/*! @{ */
+#define TRNG_FRQCNT_FRQ_CT_MASK                  (0x3FFFFFU)
+#define TRNG_FRQCNT_FRQ_CT_SHIFT                 (0U)
+#define TRNG_FRQCNT_FRQ_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
+/*! @} */
+
+/*! @name FRQMAX - Frequency Count Maximum Limit Register */
+/*! @{ */
+#define TRNG_FRQMAX_FRQ_MAX_MASK                 (0x3FFFFFU)
+#define TRNG_FRQMAX_FRQ_MAX_SHIFT                (0U)
+#define TRNG_FRQMAX_FRQ_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
+/*! @} */
+
+/*! @name SCMC - Statistical Check Monobit Count Register */
+/*! @{ */
+#define TRNG_SCMC_MONO_CT_MASK                   (0xFFFFU)
+#define TRNG_SCMC_MONO_CT_SHIFT                  (0U)
+#define TRNG_SCMC_MONO_CT(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
+/*! @} */
+
+/*! @name SCML - Statistical Check Monobit Limit Register */
+/*! @{ */
+#define TRNG_SCML_MONO_MAX_MASK                  (0xFFFFU)
+#define TRNG_SCML_MONO_MAX_SHIFT                 (0U)
+#define TRNG_SCML_MONO_MAX(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)
+#define TRNG_SCML_MONO_RNG_MASK                  (0xFFFF0000U)
+#define TRNG_SCML_MONO_RNG_SHIFT                 (16U)
+#define TRNG_SCML_MONO_RNG(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
+/*! @} */
+
+/*! @name SCR1C - Statistical Check Run Length 1 Count Register */
+/*! @{ */
+#define TRNG_SCR1C_R1_0_CT_MASK                  (0x7FFFU)
+#define TRNG_SCR1C_R1_0_CT_SHIFT                 (0U)
+#define TRNG_SCR1C_R1_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)
+#define TRNG_SCR1C_R1_1_CT_MASK                  (0x7FFF0000U)
+#define TRNG_SCR1C_R1_1_CT_SHIFT                 (16U)
+#define TRNG_SCR1C_R1_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
+/*! @} */
+
+/*! @name SCR1L - Statistical Check Run Length 1 Limit Register */
+/*! @{ */
+#define TRNG_SCR1L_RUN1_MAX_MASK                 (0x7FFFU)
+#define TRNG_SCR1L_RUN1_MAX_SHIFT                (0U)
+#define TRNG_SCR1L_RUN1_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)
+#define TRNG_SCR1L_RUN1_RNG_MASK                 (0x7FFF0000U)
+#define TRNG_SCR1L_RUN1_RNG_SHIFT                (16U)
+#define TRNG_SCR1L_RUN1_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
+/*! @} */
+
+/*! @name SCR2C - Statistical Check Run Length 2 Count Register */
+/*! @{ */
+#define TRNG_SCR2C_R2_0_CT_MASK                  (0x3FFFU)
+#define TRNG_SCR2C_R2_0_CT_SHIFT                 (0U)
+#define TRNG_SCR2C_R2_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)
+#define TRNG_SCR2C_R2_1_CT_MASK                  (0x3FFF0000U)
+#define TRNG_SCR2C_R2_1_CT_SHIFT                 (16U)
+#define TRNG_SCR2C_R2_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
+/*! @} */
+
+/*! @name SCR2L - Statistical Check Run Length 2 Limit Register */
+/*! @{ */
+#define TRNG_SCR2L_RUN2_MAX_MASK                 (0x3FFFU)
+#define TRNG_SCR2L_RUN2_MAX_SHIFT                (0U)
+#define TRNG_SCR2L_RUN2_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)
+#define TRNG_SCR2L_RUN2_RNG_MASK                 (0x3FFF0000U)
+#define TRNG_SCR2L_RUN2_RNG_SHIFT                (16U)
+#define TRNG_SCR2L_RUN2_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
+/*! @} */
+
+/*! @name SCR3C - Statistical Check Run Length 3 Count Register */
+/*! @{ */
+#define TRNG_SCR3C_R3_0_CT_MASK                  (0x1FFFU)
+#define TRNG_SCR3C_R3_0_CT_SHIFT                 (0U)
+#define TRNG_SCR3C_R3_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)
+#define TRNG_SCR3C_R3_1_CT_MASK                  (0x1FFF0000U)
+#define TRNG_SCR3C_R3_1_CT_SHIFT                 (16U)
+#define TRNG_SCR3C_R3_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
+/*! @} */
+
+/*! @name SCR3L - Statistical Check Run Length 3 Limit Register */
+/*! @{ */
+#define TRNG_SCR3L_RUN3_MAX_MASK                 (0x1FFFU)
+#define TRNG_SCR3L_RUN3_MAX_SHIFT                (0U)
+#define TRNG_SCR3L_RUN3_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)
+#define TRNG_SCR3L_RUN3_RNG_MASK                 (0x1FFF0000U)
+#define TRNG_SCR3L_RUN3_RNG_SHIFT                (16U)
+#define TRNG_SCR3L_RUN3_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
+/*! @} */
+
+/*! @name SCR4C - Statistical Check Run Length 4 Count Register */
+/*! @{ */
+#define TRNG_SCR4C_R4_0_CT_MASK                  (0xFFFU)
+#define TRNG_SCR4C_R4_0_CT_SHIFT                 (0U)
+#define TRNG_SCR4C_R4_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)
+#define TRNG_SCR4C_R4_1_CT_MASK                  (0xFFF0000U)
+#define TRNG_SCR4C_R4_1_CT_SHIFT                 (16U)
+#define TRNG_SCR4C_R4_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)
+/*! @} */
+
+/*! @name SCR4L - Statistical Check Run Length 4 Limit Register */
+/*! @{ */
+#define TRNG_SCR4L_RUN4_MAX_MASK                 (0xFFFU)
+#define TRNG_SCR4L_RUN4_MAX_SHIFT                (0U)
+#define TRNG_SCR4L_RUN4_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)
+#define TRNG_SCR4L_RUN4_RNG_MASK                 (0xFFF0000U)
+#define TRNG_SCR4L_RUN4_RNG_SHIFT                (16U)
+#define TRNG_SCR4L_RUN4_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)
+/*! @} */
+
+/*! @name SCR5C - Statistical Check Run Length 5 Count Register */
+/*! @{ */
+#define TRNG_SCR5C_R5_0_CT_MASK                  (0x7FFU)
+#define TRNG_SCR5C_R5_0_CT_SHIFT                 (0U)
+#define TRNG_SCR5C_R5_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)
+#define TRNG_SCR5C_R5_1_CT_MASK                  (0x7FF0000U)
+#define TRNG_SCR5C_R5_1_CT_SHIFT                 (16U)
+#define TRNG_SCR5C_R5_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)
+/*! @} */
+
+/*! @name SCR5L - Statistical Check Run Length 5 Limit Register */
+/*! @{ */
+#define TRNG_SCR5L_RUN5_MAX_MASK                 (0x7FFU)
+#define TRNG_SCR5L_RUN5_MAX_SHIFT                (0U)
+#define TRNG_SCR5L_RUN5_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)
+#define TRNG_SCR5L_RUN5_RNG_MASK                 (0x7FF0000U)
+#define TRNG_SCR5L_RUN5_RNG_SHIFT                (16U)
+#define TRNG_SCR5L_RUN5_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)
+/*! @} */
+
+/*! @name SCR6PC - Statistical Check Run Length 6+ Count Register */
+/*! @{ */
+#define TRNG_SCR6PC_R6P_0_CT_MASK                (0x7FFU)
+#define TRNG_SCR6PC_R6P_0_CT_SHIFT               (0U)
+#define TRNG_SCR6PC_R6P_0_CT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)
+#define TRNG_SCR6PC_R6P_1_CT_MASK                (0x7FF0000U)
+#define TRNG_SCR6PC_R6P_1_CT_SHIFT               (16U)
+#define TRNG_SCR6PC_R6P_1_CT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)
+/*! @} */
+
+/*! @name SCR6PL - Statistical Check Run Length 6+ Limit Register */
+/*! @{ */
+#define TRNG_SCR6PL_RUN6P_MAX_MASK               (0x7FFU)
+#define TRNG_SCR6PL_RUN6P_MAX_SHIFT              (0U)
+#define TRNG_SCR6PL_RUN6P_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)
+#define TRNG_SCR6PL_RUN6P_RNG_MASK               (0x7FF0000U)
+#define TRNG_SCR6PL_RUN6P_RNG_SHIFT              (16U)
+#define TRNG_SCR6PL_RUN6P_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)
+/*! @} */
+
+/*! @name STATUS - Status Register */
+/*! @{ */
+#define TRNG_STATUS_TF1BR0_MASK                  (0x1U)
+#define TRNG_STATUS_TF1BR0_SHIFT                 (0U)
+#define TRNG_STATUS_TF1BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
+#define TRNG_STATUS_TF1BR1_MASK                  (0x2U)
+#define TRNG_STATUS_TF1BR1_SHIFT                 (1U)
+#define TRNG_STATUS_TF1BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
+#define TRNG_STATUS_TF2BR0_MASK                  (0x4U)
+#define TRNG_STATUS_TF2BR0_SHIFT                 (2U)
+#define TRNG_STATUS_TF2BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
+#define TRNG_STATUS_TF2BR1_MASK                  (0x8U)
+#define TRNG_STATUS_TF2BR1_SHIFT                 (3U)
+#define TRNG_STATUS_TF2BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
+#define TRNG_STATUS_TF3BR0_MASK                  (0x10U)
+#define TRNG_STATUS_TF3BR0_SHIFT                 (4U)
+#define TRNG_STATUS_TF3BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
+#define TRNG_STATUS_TF3BR1_MASK                  (0x20U)
+#define TRNG_STATUS_TF3BR1_SHIFT                 (5U)
+#define TRNG_STATUS_TF3BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
+#define TRNG_STATUS_TF4BR0_MASK                  (0x40U)
+#define TRNG_STATUS_TF4BR0_SHIFT                 (6U)
+#define TRNG_STATUS_TF4BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)
+#define TRNG_STATUS_TF4BR1_MASK                  (0x80U)
+#define TRNG_STATUS_TF4BR1_SHIFT                 (7U)
+#define TRNG_STATUS_TF4BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)
+#define TRNG_STATUS_TF5BR0_MASK                  (0x100U)
+#define TRNG_STATUS_TF5BR0_SHIFT                 (8U)
+#define TRNG_STATUS_TF5BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)
+#define TRNG_STATUS_TF5BR1_MASK                  (0x200U)
+#define TRNG_STATUS_TF5BR1_SHIFT                 (9U)
+#define TRNG_STATUS_TF5BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)
+#define TRNG_STATUS_TF6PBR0_MASK                 (0x400U)
+#define TRNG_STATUS_TF6PBR0_SHIFT                (10U)
+#define TRNG_STATUS_TF6PBR0(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)
+#define TRNG_STATUS_TF6PBR1_MASK                 (0x800U)
+#define TRNG_STATUS_TF6PBR1_SHIFT                (11U)
+#define TRNG_STATUS_TF6PBR1(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)
+#define TRNG_STATUS_TFSB_MASK                    (0x1000U)
+#define TRNG_STATUS_TFSB_SHIFT                   (12U)
+#define TRNG_STATUS_TFSB(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)
+#define TRNG_STATUS_TFLR_MASK                    (0x2000U)
+#define TRNG_STATUS_TFLR_SHIFT                   (13U)
+#define TRNG_STATUS_TFLR(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
+#define TRNG_STATUS_TFP_MASK                     (0x4000U)
+#define TRNG_STATUS_TFP_SHIFT                    (14U)
+#define TRNG_STATUS_TFP(x)                       (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)
+#define TRNG_STATUS_TFMB_MASK                    (0x8000U)
+#define TRNG_STATUS_TFMB_SHIFT                   (15U)
+#define TRNG_STATUS_TFMB(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
+#define TRNG_STATUS_RETRY_CT_MASK                (0xF0000U)
+#define TRNG_STATUS_RETRY_CT_SHIFT               (16U)
+#define TRNG_STATUS_RETRY_CT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
+/*! @} */
+
+/*! @name ENT - Entropy Read Register */
+/*! @{ */
+#define TRNG_ENT_ENT_MASK                        (0xFFFFFFFFU)
+#define TRNG_ENT_ENT_SHIFT                       (0U)
+#define TRNG_ENT_ENT(x)                          (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
+/*! @} */
+
+/* The count of TRNG_ENT */
+#define TRNG_ENT_COUNT                           (16U)
+
+/*! @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */
+/*! @{ */
+#define TRNG_PKRCNT10_PKR_0_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNT10_PKR_0_CT_SHIFT             (0U)
+#define TRNG_PKRCNT10_PKR_0_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)
+#define TRNG_PKRCNT10_PKR_1_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNT10_PKR_1_CT_SHIFT             (16U)
+#define TRNG_PKRCNT10_PKR_1_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)
+/*! @} */
+
+/*! @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */
+/*! @{ */
+#define TRNG_PKRCNT32_PKR_2_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNT32_PKR_2_CT_SHIFT             (0U)
+#define TRNG_PKRCNT32_PKR_2_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)
+#define TRNG_PKRCNT32_PKR_3_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNT32_PKR_3_CT_SHIFT             (16U)
+#define TRNG_PKRCNT32_PKR_3_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)
+/*! @} */
+
+/*! @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */
+/*! @{ */
+#define TRNG_PKRCNT54_PKR_4_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNT54_PKR_4_CT_SHIFT             (0U)
+#define TRNG_PKRCNT54_PKR_4_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)
+#define TRNG_PKRCNT54_PKR_5_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNT54_PKR_5_CT_SHIFT             (16U)
+#define TRNG_PKRCNT54_PKR_5_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)
+/*! @} */
+
+/*! @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */
+/*! @{ */
+#define TRNG_PKRCNT76_PKR_6_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNT76_PKR_6_CT_SHIFT             (0U)
+#define TRNG_PKRCNT76_PKR_6_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)
+#define TRNG_PKRCNT76_PKR_7_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNT76_PKR_7_CT_SHIFT             (16U)
+#define TRNG_PKRCNT76_PKR_7_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)
+/*! @} */
+
+/*! @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */
+/*! @{ */
+#define TRNG_PKRCNT98_PKR_8_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNT98_PKR_8_CT_SHIFT             (0U)
+#define TRNG_PKRCNT98_PKR_8_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)
+#define TRNG_PKRCNT98_PKR_9_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNT98_PKR_9_CT_SHIFT             (16U)
+#define TRNG_PKRCNT98_PKR_9_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)
+/*! @} */
+
+/*! @name PKRCNTBA - Statistical Check Poker Count B and A Register */
+/*! @{ */
+#define TRNG_PKRCNTBA_PKR_A_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNTBA_PKR_A_CT_SHIFT             (0U)
+#define TRNG_PKRCNTBA_PKR_A_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)
+#define TRNG_PKRCNTBA_PKR_B_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNTBA_PKR_B_CT_SHIFT             (16U)
+#define TRNG_PKRCNTBA_PKR_B_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)
+/*! @} */
+
+/*! @name PKRCNTDC - Statistical Check Poker Count D and C Register */
+/*! @{ */
+#define TRNG_PKRCNTDC_PKR_C_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNTDC_PKR_C_CT_SHIFT             (0U)
+#define TRNG_PKRCNTDC_PKR_C_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)
+#define TRNG_PKRCNTDC_PKR_D_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNTDC_PKR_D_CT_SHIFT             (16U)
+#define TRNG_PKRCNTDC_PKR_D_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)
+/*! @} */
+
+/*! @name PKRCNTFE - Statistical Check Poker Count F and E Register */
+/*! @{ */
+#define TRNG_PKRCNTFE_PKR_E_CT_MASK              (0xFFFFU)
+#define TRNG_PKRCNTFE_PKR_E_CT_SHIFT             (0U)
+#define TRNG_PKRCNTFE_PKR_E_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)
+#define TRNG_PKRCNTFE_PKR_F_CT_MASK              (0xFFFF0000U)
+#define TRNG_PKRCNTFE_PKR_F_CT_SHIFT             (16U)
+#define TRNG_PKRCNTFE_PKR_F_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)
+/*! @} */
+
+/*! @name SEC_CFG - Security Configuration Register */
+/*! @{ */
+#define TRNG_SEC_CFG_UNUSED0_MASK                (0x1U)
+#define TRNG_SEC_CFG_UNUSED0_SHIFT               (0U)
+#define TRNG_SEC_CFG_UNUSED0(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK)
+#define TRNG_SEC_CFG_NO_PRGM_MASK                (0x2U)
+#define TRNG_SEC_CFG_NO_PRGM_SHIFT               (1U)
+/*! NO_PRGM
+ *  0b0..Programability of registers controlled only by the Miscellaneous Control Register's access mode bit.
+ *  0b1..Overides Miscellaneous Control Register access mode and prevents TRNG register programming.
+ */
+#define TRNG_SEC_CFG_NO_PRGM(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
+#define TRNG_SEC_CFG_UNUSED2_MASK                (0x4U)
+#define TRNG_SEC_CFG_UNUSED2_SHIFT               (2U)
+#define TRNG_SEC_CFG_UNUSED2(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK)
+/*! @} */
+
+/*! @name INT_CTRL - Interrupt Control Register */
+/*! @{ */
+#define TRNG_INT_CTRL_HW_ERR_MASK                (0x1U)
+#define TRNG_INT_CTRL_HW_ERR_SHIFT               (0U)
+/*! HW_ERR
+ *  0b0..Corresponding bit of INT_STATUS register cleared.
+ *  0b1..Corresponding bit of INT_STATUS register active.
+ */
+#define TRNG_INT_CTRL_HW_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
+#define TRNG_INT_CTRL_ENT_VAL_MASK               (0x2U)
+#define TRNG_INT_CTRL_ENT_VAL_SHIFT              (1U)
+/*! ENT_VAL
+ *  0b0..Same behavior as bit 0 of this register.
+ *  0b1..Same behavior as bit 0 of this register.
+ */
+#define TRNG_INT_CTRL_ENT_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
+#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK           (0x4U)
+#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT          (2U)
+/*! FRQ_CT_FAIL
+ *  0b0..Same behavior as bit 0 of this register.
+ *  0b1..Same behavior as bit 0 of this register.
+ */
+#define TRNG_INT_CTRL_FRQ_CT_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
+#define TRNG_INT_CTRL_UNUSED_MASK                (0xFFFFFFF8U)
+#define TRNG_INT_CTRL_UNUSED_SHIFT               (3U)
+#define TRNG_INT_CTRL_UNUSED(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)
+/*! @} */
+
+/*! @name INT_MASK - Mask Register */
+/*! @{ */
+#define TRNG_INT_MASK_HW_ERR_MASK                (0x1U)
+#define TRNG_INT_MASK_HW_ERR_SHIFT               (0U)
+/*! HW_ERR
+ *  0b0..Corresponding interrupt of INT_STATUS is masked.
+ *  0b1..Corresponding bit of INT_STATUS is active.
+ */
+#define TRNG_INT_MASK_HW_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
+#define TRNG_INT_MASK_ENT_VAL_MASK               (0x2U)
+#define TRNG_INT_MASK_ENT_VAL_SHIFT              (1U)
+/*! ENT_VAL
+ *  0b0..Same behavior as bit 0 of this register.
+ *  0b1..Same behavior as bit 0 of this register.
+ */
+#define TRNG_INT_MASK_ENT_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
+#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK           (0x4U)
+#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT          (2U)
+/*! FRQ_CT_FAIL
+ *  0b0..Same behavior as bit 0 of this register.
+ *  0b1..Same behavior as bit 0 of this register.
+ */
+#define TRNG_INT_MASK_FRQ_CT_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
+/*! @} */
+
+/*! @name INT_STATUS - Interrupt Status Register */
+/*! @{ */
+#define TRNG_INT_STATUS_HW_ERR_MASK              (0x1U)
+#define TRNG_INT_STATUS_HW_ERR_SHIFT             (0U)
+/*! HW_ERR
+ *  0b0..no error
+ *  0b1..error detected.
+ */
+#define TRNG_INT_STATUS_HW_ERR(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
+#define TRNG_INT_STATUS_ENT_VAL_MASK             (0x2U)
+#define TRNG_INT_STATUS_ENT_VAL_SHIFT            (1U)
+/*! ENT_VAL
+ *  0b0..Busy generation entropy. Any value read is invalid.
+ *  0b1..TRNG can be stopped and entropy is valid if read.
+ */
+#define TRNG_INT_STATUS_ENT_VAL(x)               (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
+#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK         (0x4U)
+#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT        (2U)
+/*! FRQ_CT_FAIL
+ *  0b0..No hardware nor self test frequency errors.
+ *  0b1..The frequency counter has detected a failure.
+ */
+#define TRNG_INT_STATUS_FRQ_CT_FAIL(x)           (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
+/*! @} */
+
+/*! @name VID1 - Version ID Register (MS) */
+/*! @{ */
+#define TRNG_VID1_MIN_REV_MASK                   (0xFFU)
+#define TRNG_VID1_MIN_REV_SHIFT                  (0U)
+/*! MIN_REV
+ *  0b00000000..Minor revision number for TRNG.
+ */
+#define TRNG_VID1_MIN_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)
+#define TRNG_VID1_MAJ_REV_MASK                   (0xFF00U)
+#define TRNG_VID1_MAJ_REV_SHIFT                  (8U)
+/*! MAJ_REV
+ *  0b00000001..Major revision number for TRNG.
+ */
+#define TRNG_VID1_MAJ_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)
+#define TRNG_VID1_IP_ID_MASK                     (0xFFFF0000U)
+#define TRNG_VID1_IP_ID_SHIFT                    (16U)
+/*! IP_ID
+ *  0b0000000000110000..ID for TRNG.
+ */
+#define TRNG_VID1_IP_ID(x)                       (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)
+/*! @} */
+
+/*! @name VID2 - Version ID Register (LS) */
+/*! @{ */
+#define TRNG_VID2_CONFIG_OPT_MASK                (0xFFU)
+#define TRNG_VID2_CONFIG_OPT_SHIFT               (0U)
+/*! CONFIG_OPT
+ *  0b00000000..TRNG_CONFIG_OPT for TRNG.
+ */
+#define TRNG_VID2_CONFIG_OPT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)
+#define TRNG_VID2_ECO_REV_MASK                   (0xFF00U)
+#define TRNG_VID2_ECO_REV_SHIFT                  (8U)
+/*! ECO_REV
+ *  0b00000000..TRNG_ECO_REV for TRNG.
+ */
+#define TRNG_VID2_ECO_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)
+#define TRNG_VID2_INTG_OPT_MASK                  (0xFF0000U)
+#define TRNG_VID2_INTG_OPT_SHIFT                 (16U)
+/*! INTG_OPT
+ *  0b00000000..INTG_OPT for TRNG.
+ */
+#define TRNG_VID2_INTG_OPT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)
+#define TRNG_VID2_ERA_MASK                       (0xFF000000U)
+#define TRNG_VID2_ERA_SHIFT                      (24U)
+/*! ERA
+ *  0b00000000..COMPILE_OPT for TRNG.
+ */
+#define TRNG_VID2_ERA(x)                         (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group TRNG_Register_Masks */
+
+
+/* TRNG - Peripheral instance base addresses */
+/** Peripheral TRNG base address */
+#define TRNG_BASE                                (0x41029000u)
+/** Peripheral TRNG base pointer */
+#define TRNG                                     ((TRNG_Type *)TRNG_BASE)
+/** Array initializer of TRNG peripheral base addresses */
+#define TRNG_BASE_ADDRS                          { TRNG_BASE }
+/** Array initializer of TRNG peripheral base pointers */
+#define TRNG_BASE_PTRS                           { TRNG }
+/** Interrupt vectors for the TRNG peripheral type */
+#define TRNG_IRQS                                { TRNG_IRQn }
+/** Backward compatibility macros */
+#define TRNG0                                    TRNG
+
+
+/*!
+ * @}
+ */ /* end of group TRNG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- TSTMR Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TSTMR_Peripheral_Access_Layer TSTMR Peripheral Access Layer
+ * @{
+ */
+
+/** TSTMR - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t L;                                 /**< Time Stamp Timer Register Low, offset: 0x0 */
+  __I  uint32_t H;                                 /**< Time Stamp Timer Register High, offset: 0x4 */
+} TSTMR_Type;
+
+/* ----------------------------------------------------------------------------
+   -- TSTMR Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TSTMR_Register_Masks TSTMR Register Masks
+ * @{
+ */
+
+/*! @name L - Time Stamp Timer Register Low */
+/*! @{ */
+#define TSTMR_L_VALUE_MASK                       (0xFFFFFFFFU)
+#define TSTMR_L_VALUE_SHIFT                      (0U)
+#define TSTMR_L_VALUE(x)                         (((uint32_t)(((uint32_t)(x)) << TSTMR_L_VALUE_SHIFT)) & TSTMR_L_VALUE_MASK)
+/*! @} */
+
+/*! @name H - Time Stamp Timer Register High */
+/*! @{ */
+#define TSTMR_H_VALUE_MASK                       (0xFFFFFFU)
+#define TSTMR_H_VALUE_SHIFT                      (0U)
+#define TSTMR_H_VALUE(x)                         (((uint32_t)(((uint32_t)(x)) << TSTMR_H_VALUE_SHIFT)) & TSTMR_H_VALUE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group TSTMR_Register_Masks */
+
+
+/* TSTMR - Peripheral instance base addresses */
+/** Peripheral TSTMRB base address */
+#define TSTMRB_BASE                              (0x4102C000u)
+/** Peripheral TSTMRB base pointer */
+#define TSTMRB                                   ((TSTMR_Type *)TSTMRB_BASE)
+/** Array initializer of TSTMR peripheral base addresses */
+#define TSTMR_BASE_ADDRS                         { TSTMRB_BASE }
+/** Array initializer of TSTMR peripheral base pointers */
+#define TSTMR_BASE_PTRS                          { TSTMRB }
+
+/*!
+ * @}
+ */ /* end of group TSTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t PERID;                              /**< Peripheral ID register, offset: 0x0 */
+       uint8_t RESERVED_0[3];
+  __I  uint8_t IDCOMP;                             /**< Peripheral ID Complement register, offset: 0x4 */
+       uint8_t RESERVED_1[3];
+  __I  uint8_t REV;                                /**< Peripheral Revision register, offset: 0x8 */
+       uint8_t RESERVED_2[3];
+  __I  uint8_t ADDINFO;                            /**< Peripheral Additional Info register, offset: 0xC */
+       uint8_t RESERVED_3[15];
+  __IO uint8_t OTGCTL;                             /**< OTG Control register, offset: 0x1C */
+       uint8_t RESERVED_4[99];
+  __IO uint8_t ISTAT;                              /**< Interrupt Status register, offset: 0x80 */
+       uint8_t RESERVED_5[3];
+  __IO uint8_t INTEN;                              /**< Interrupt Enable register, offset: 0x84 */
+       uint8_t RESERVED_6[3];
+  __IO uint8_t ERRSTAT;                            /**< Error Interrupt Status register, offset: 0x88 */
+       uint8_t RESERVED_7[3];
+  __IO uint8_t ERREN;                              /**< Error Interrupt Enable register, offset: 0x8C */
+       uint8_t RESERVED_8[3];
+  __I  uint8_t STAT;                               /**< Status register, offset: 0x90 */
+       uint8_t RESERVED_9[3];
+  __IO uint8_t CTL;                                /**< Control register, offset: 0x94 */
+       uint8_t RESERVED_10[3];
+  __IO uint8_t ADDR;                               /**< Address register, offset: 0x98 */
+       uint8_t RESERVED_11[3];
+  __IO uint8_t BDTPAGE1;                           /**< BDT Page register 1, offset: 0x9C */
+       uint8_t RESERVED_12[3];
+  __IO uint8_t FRMNUML;                            /**< Frame Number register Low, offset: 0xA0 */
+       uint8_t RESERVED_13[3];
+  __IO uint8_t FRMNUMH;                            /**< Frame Number register High, offset: 0xA4 */
+       uint8_t RESERVED_14[11];
+  __IO uint8_t BDTPAGE2;                           /**< BDT Page Register 2, offset: 0xB0 */
+       uint8_t RESERVED_15[3];
+  __IO uint8_t BDTPAGE3;                           /**< BDT Page Register 3, offset: 0xB4 */
+       uint8_t RESERVED_16[11];
+  struct {                                         /* offset: 0xC0, array step: 0x4 */
+    __IO uint8_t ENDPT;                              /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+         uint8_t RESERVED_0[3];
+  } ENDPOINT[16];
+  __IO uint8_t USBCTRL;                            /**< USB Control register, offset: 0x100 */
+       uint8_t RESERVED_17[3];
+  __I  uint8_t OBSERVE;                            /**< USB OTG Observe register, offset: 0x104 */
+       uint8_t RESERVED_18[3];
+  __IO uint8_t CONTROL;                            /**< USB OTG Control register, offset: 0x108 */
+       uint8_t RESERVED_19[3];
+  __IO uint8_t USBTRC0;                            /**< USB Transceiver Control register 0, offset: 0x10C */
+       uint8_t RESERVED_20[23];
+  __IO uint8_t KEEP_ALIVE_CTRL;                    /**< Keep Alive mode control, offset: 0x124 */
+       uint8_t RESERVED_21[3];
+  __IO uint8_t KEEP_ALIVE_WKCTRL;                  /**< Keep Alive mode wakeup control, offset: 0x128 */
+       uint8_t RESERVED_22[3];
+  __IO uint8_t MISCCTRL;                           /**< Miscellaneous Control register, offset: 0x12C */
+       uint8_t RESERVED_23[3];
+  __IO uint8_t STALL_IL_DIS;                       /**< Peripheral mode stall disable for endpoints 7 to 0 in IN direction, offset: 0x130 */
+       uint8_t RESERVED_24[3];
+  __IO uint8_t STALL_IH_DIS;                       /**< Peripheral mode stall disable for endpoints 15 to 8 in IN direction, offset: 0x134 */
+       uint8_t RESERVED_25[3];
+  __IO uint8_t STALL_OL_DIS;                       /**< Peripheral mode stall disable for endpoints 7 to 0 in OUT direction, offset: 0x138 */
+       uint8_t RESERVED_26[3];
+  __IO uint8_t STALL_OH_DIS;                       /**< Peripheral mode stall disable for endpoints 15 to 8 in OUT direction, offset: 0x13C */
+       uint8_t RESERVED_27[3];
+  __IO uint8_t CLK_RECOVER_CTRL;                   /**< USB Clock recovery control, offset: 0x140 */
+       uint8_t RESERVED_28[3];
+  __IO uint8_t CLK_RECOVER_IRC_EN;                 /**< IRC48MFIRC oscillator enable register, offset: 0x144 */
+       uint8_t RESERVED_29[15];
+  __IO uint8_t CLK_RECOVER_INT_EN;                 /**< Clock recovery combined interrupt enable, offset: 0x154 */
+       uint8_t RESERVED_30[7];
+  __IO uint8_t CLK_RECOVER_INT_STATUS;             /**< Clock recovery separated interrupt status, offset: 0x15C */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/*! @name PERID - Peripheral ID register */
+/*! @{ */
+#define USB_PERID_ID_MASK                        (0x3FU)
+#define USB_PERID_ID_SHIFT                       (0U)
+#define USB_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
+/*! @} */
+
+/*! @name IDCOMP - Peripheral ID Complement register */
+/*! @{ */
+#define USB_IDCOMP_NID_MASK                      (0x3FU)
+#define USB_IDCOMP_NID_SHIFT                     (0U)
+#define USB_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
+/*! @} */
+
+/*! @name REV - Peripheral Revision register */
+/*! @{ */
+#define USB_REV_REV_MASK                         (0xFFU)
+#define USB_REV_REV_SHIFT                        (0U)
+#define USB_REV_REV(x)                           (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
+/*! @} */
+
+/*! @name ADDINFO - Peripheral Additional Info register */
+/*! @{ */
+#define USB_ADDINFO_IEHOST_MASK                  (0x1U)
+#define USB_ADDINFO_IEHOST_SHIFT                 (0U)
+#define USB_ADDINFO_IEHOST(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
+/*! @} */
+
+/*! @name OTGCTL - OTG Control register */
+/*! @{ */
+#define USB_OTGCTL_DPHIGH_MASK                   (0x80U)
+#define USB_OTGCTL_DPHIGH_SHIFT                  (7U)
+/*! DPHIGH - D+ Data Line pullup resistor enable
+ *  0b0..D+ pullup resistor is not enabled
+ *  0b1..D+ pullup resistor is enabled
+ */
+#define USB_OTGCTL_DPHIGH(x)                     (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
+/*! @} */
+
+/*! @name ISTAT - Interrupt Status register */
+/*! @{ */
+#define USB_ISTAT_USBRST_MASK                    (0x1U)
+#define USB_ISTAT_USBRST_SHIFT                   (0U)
+#define USB_ISTAT_USBRST(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
+#define USB_ISTAT_ERROR_MASK                     (0x2U)
+#define USB_ISTAT_ERROR_SHIFT                    (1U)
+#define USB_ISTAT_ERROR(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
+#define USB_ISTAT_SOFTOK_MASK                    (0x4U)
+#define USB_ISTAT_SOFTOK_SHIFT                   (2U)
+#define USB_ISTAT_SOFTOK(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
+#define USB_ISTAT_TOKDNE_MASK                    (0x8U)
+#define USB_ISTAT_TOKDNE_SHIFT                   (3U)
+#define USB_ISTAT_TOKDNE(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
+#define USB_ISTAT_SLEEP_MASK                     (0x10U)
+#define USB_ISTAT_SLEEP_SHIFT                    (4U)
+#define USB_ISTAT_SLEEP(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
+#define USB_ISTAT_RESUME_MASK                    (0x20U)
+#define USB_ISTAT_RESUME_SHIFT                   (5U)
+#define USB_ISTAT_RESUME(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
+#define USB_ISTAT_STALL_MASK                     (0x80U)
+#define USB_ISTAT_STALL_SHIFT                    (7U)
+#define USB_ISTAT_STALL(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
+/*! @} */
+
+/*! @name INTEN - Interrupt Enable register */
+/*! @{ */
+#define USB_INTEN_USBRSTEN_MASK                  (0x1U)
+#define USB_INTEN_USBRSTEN_SHIFT                 (0U)
+/*! USBRSTEN - USBRST Interrupt Enable
+ *  0b0..Disables the USBRST interrupt.
+ *  0b1..Enables the USBRST interrupt.
+ */
+#define USB_INTEN_USBRSTEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
+#define USB_INTEN_ERROREN_MASK                   (0x2U)
+#define USB_INTEN_ERROREN_SHIFT                  (1U)
+/*! ERROREN - ERROR Interrupt Enable
+ *  0b0..Disables the ERROR interrupt.
+ *  0b1..Enables the ERROR interrupt.
+ */
+#define USB_INTEN_ERROREN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
+#define USB_INTEN_SOFTOKEN_MASK                  (0x4U)
+#define USB_INTEN_SOFTOKEN_SHIFT                 (2U)
+/*! SOFTOKEN - SOFTOK Interrupt Enable
+ *  0b0..Disbles the SOFTOK interrupt.
+ *  0b1..Enables the SOFTOK interrupt.
+ */
+#define USB_INTEN_SOFTOKEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
+#define USB_INTEN_TOKDNEEN_MASK                  (0x8U)
+#define USB_INTEN_TOKDNEEN_SHIFT                 (3U)
+/*! TOKDNEEN - TOKDNE Interrupt Enable
+ *  0b0..Disables the TOKDNE interrupt.
+ *  0b1..Enables the TOKDNE interrupt.
+ */
+#define USB_INTEN_TOKDNEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
+#define USB_INTEN_SLEEPEN_MASK                   (0x10U)
+#define USB_INTEN_SLEEPEN_SHIFT                  (4U)
+/*! SLEEPEN - SLEEP Interrupt Enable
+ *  0b0..Disables the SLEEP interrupt.
+ *  0b1..Enables the SLEEP interrupt.
+ */
+#define USB_INTEN_SLEEPEN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
+#define USB_INTEN_RESUMEEN_MASK                  (0x20U)
+#define USB_INTEN_RESUMEEN_SHIFT                 (5U)
+/*! RESUMEEN - RESUME Interrupt Enable
+ *  0b0..Disables the RESUME interrupt.
+ *  0b1..Enables the RESUME interrupt.
+ */
+#define USB_INTEN_RESUMEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
+#define USB_INTEN_STALLEN_MASK                   (0x80U)
+#define USB_INTEN_STALLEN_SHIFT                  (7U)
+/*! STALLEN - STALL Interrupt Enable
+ *  0b0..Diasbles the STALL interrupt.
+ *  0b1..Enables the STALL interrupt.
+ */
+#define USB_INTEN_STALLEN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
+/*! @} */
+
+/*! @name ERRSTAT - Error Interrupt Status register */
+/*! @{ */
+#define USB_ERRSTAT_PIDERR_MASK                  (0x1U)
+#define USB_ERRSTAT_PIDERR_SHIFT                 (0U)
+#define USB_ERRSTAT_PIDERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
+#define USB_ERRSTAT_CRC5EOF_MASK                 (0x2U)
+#define USB_ERRSTAT_CRC5EOF_SHIFT                (1U)
+#define USB_ERRSTAT_CRC5EOF(x)                   (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
+#define USB_ERRSTAT_CRC16_MASK                   (0x4U)
+#define USB_ERRSTAT_CRC16_SHIFT                  (2U)
+#define USB_ERRSTAT_CRC16(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
+#define USB_ERRSTAT_DFN8_MASK                    (0x8U)
+#define USB_ERRSTAT_DFN8_SHIFT                   (3U)
+#define USB_ERRSTAT_DFN8(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
+#define USB_ERRSTAT_BTOERR_MASK                  (0x10U)
+#define USB_ERRSTAT_BTOERR_SHIFT                 (4U)
+#define USB_ERRSTAT_BTOERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
+#define USB_ERRSTAT_DMAERR_MASK                  (0x20U)
+#define USB_ERRSTAT_DMAERR_SHIFT                 (5U)
+#define USB_ERRSTAT_DMAERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
+#define USB_ERRSTAT_OWNERR_MASK                  (0x40U)
+#define USB_ERRSTAT_OWNERR_SHIFT                 (6U)
+#define USB_ERRSTAT_OWNERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK)
+#define USB_ERRSTAT_BTSERR_MASK                  (0x80U)
+#define USB_ERRSTAT_BTSERR_SHIFT                 (7U)
+#define USB_ERRSTAT_BTSERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
+/*! @} */
+
+/*! @name ERREN - Error Interrupt Enable register */
+/*! @{ */
+#define USB_ERREN_PIDERREN_MASK                  (0x1U)
+#define USB_ERREN_PIDERREN_SHIFT                 (0U)
+/*! PIDERREN - PIDERR Interrupt Enable
+ *  0b0..Disables the PIDERR interrupt.
+ *  0b1..Enters the PIDERR interrupt.
+ */
+#define USB_ERREN_PIDERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
+#define USB_ERREN_CRC5EOFEN_MASK                 (0x2U)
+#define USB_ERREN_CRC5EOFEN_SHIFT                (1U)
+/*! CRC5EOFEN - CRC5/EOF Interrupt Enable
+ *  0b0..Disables the CRC5/EOF interrupt.
+ *  0b1..Enables the CRC5/EOF interrupt.
+ */
+#define USB_ERREN_CRC5EOFEN(x)                   (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
+#define USB_ERREN_CRC16EN_MASK                   (0x4U)
+#define USB_ERREN_CRC16EN_SHIFT                  (2U)
+/*! CRC16EN - CRC16 Interrupt Enable
+ *  0b0..Disables the CRC16 interrupt.
+ *  0b1..Enables the CRC16 interrupt.
+ */
+#define USB_ERREN_CRC16EN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
+#define USB_ERREN_DFN8EN_MASK                    (0x8U)
+#define USB_ERREN_DFN8EN_SHIFT                   (3U)
+/*! DFN8EN - DFN8 Interrupt Enable
+ *  0b0..Disables the DFN8 interrupt.
+ *  0b1..Enables the DFN8 interrupt.
+ */
+#define USB_ERREN_DFN8EN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
+#define USB_ERREN_BTOERREN_MASK                  (0x10U)
+#define USB_ERREN_BTOERREN_SHIFT                 (4U)
+/*! BTOERREN - BTOERR Interrupt Enable
+ *  0b0..Disables the BTOERR interrupt.
+ *  0b1..Enables the BTOERR interrupt.
+ */
+#define USB_ERREN_BTOERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
+#define USB_ERREN_DMAERREN_MASK                  (0x20U)
+#define USB_ERREN_DMAERREN_SHIFT                 (5U)
+/*! DMAERREN - DMAERR Interrupt Enable
+ *  0b0..Disables the DMAERR interrupt.
+ *  0b1..Enables the DMAERR interrupt.
+ */
+#define USB_ERREN_DMAERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
+#define USB_ERREN_OWNERREN_MASK                  (0x40U)
+#define USB_ERREN_OWNERREN_SHIFT                 (6U)
+/*! OWNERREN - OWNERR Interrupt Enable
+ *  0b0..Disables the OWNERR interrupt.
+ *  0b1..Enables the OWNERR interrupt.
+ */
+#define USB_ERREN_OWNERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK)
+#define USB_ERREN_BTSERREN_MASK                  (0x80U)
+#define USB_ERREN_BTSERREN_SHIFT                 (7U)
+/*! BTSERREN - BTSERR Interrupt Enable
+ *  0b0..Disables the BTSERR interrupt.
+ *  0b1..Enables the BTSERR interrupt.
+ */
+#define USB_ERREN_BTSERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
+/*! @} */
+
+/*! @name STAT - Status register */
+/*! @{ */
+#define USB_STAT_ODD_MASK                        (0x4U)
+#define USB_STAT_ODD_SHIFT                       (2U)
+#define USB_STAT_ODD(x)                          (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
+#define USB_STAT_TX_MASK                         (0x8U)
+#define USB_STAT_TX_SHIFT                        (3U)
+/*! TX - Transmit Indicator
+ *  0b0..The most recent transaction was a receive operation.
+ *  0b1..The most recent transaction was a transmit operation.
+ */
+#define USB_STAT_TX(x)                           (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
+#define USB_STAT_ENDP_MASK                       (0xF0U)
+#define USB_STAT_ENDP_SHIFT                      (4U)
+#define USB_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
+/*! @} */
+
+/*! @name CTL - Control register */
+/*! @{ */
+#define USB_CTL_USBENSOFEN_MASK                  (0x1U)
+#define USB_CTL_USBENSOFEN_SHIFT                 (0U)
+/*! USBENSOFEN - USB Enable
+ *  0b0..Disables the USB Module.
+ *  0b1..Enables the USB Module.
+ */
+#define USB_CTL_USBENSOFEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
+#define USB_CTL_ODDRST_MASK                      (0x2U)
+#define USB_CTL_ODDRST_SHIFT                     (1U)
+#define USB_CTL_ODDRST(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
+#define USB_CTL_RESUME_MASK                      (0x4U)
+#define USB_CTL_RESUME_SHIFT                     (2U)
+#define USB_CTL_RESUME(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
+#define USB_CTL_HOSTMODEEN_MASK                  (0x8U)
+#define USB_CTL_HOSTMODEEN_SHIFT                 (3U)
+/*! HOSTMODEEN - Host mode enable
+ *  0b0..USB Module operates in Device mode.
+ *  0b1..USB Module operates in Host mode. In Host mode, the USB module performs USB transactions under the programmed control of the host processor.
+ */
+#define USB_CTL_HOSTMODEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK          (0x20U)
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT         (5U)
+#define USB_CTL_TXSUSPENDTOKENBUSY(x)            (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
+#define USB_CTL_SE0_MASK                         (0x40U)
+#define USB_CTL_SE0_SHIFT                        (6U)
+#define USB_CTL_SE0(x)                           (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
+#define USB_CTL_JSTATE_MASK                      (0x80U)
+#define USB_CTL_JSTATE_SHIFT                     (7U)
+#define USB_CTL_JSTATE(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
+/*! @} */
+
+/*! @name ADDR - Address register */
+/*! @{ */
+#define USB_ADDR_ADDR_MASK                       (0x7FU)
+#define USB_ADDR_ADDR_SHIFT                      (0U)
+#define USB_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
+/*! @} */
+
+/*! @name BDTPAGE1 - BDT Page register 1 */
+/*! @{ */
+#define USB_BDTPAGE1_BDTBA_MASK                  (0xFEU)
+#define USB_BDTPAGE1_BDTBA_SHIFT                 (1U)
+#define USB_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
+/*! @} */
+
+/*! @name FRMNUML - Frame Number register Low */
+/*! @{ */
+#define USB_FRMNUML_FRM_MASK                     (0xFFU)
+#define USB_FRMNUML_FRM_SHIFT                    (0U)
+#define USB_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
+/*! @} */
+
+/*! @name FRMNUMH - Frame Number register High */
+/*! @{ */
+#define USB_FRMNUMH_FRM_MASK                     (0x7U)
+#define USB_FRMNUMH_FRM_SHIFT                    (0U)
+#define USB_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
+/*! @} */
+
+/*! @name BDTPAGE2 - BDT Page Register 2 */
+/*! @{ */
+#define USB_BDTPAGE2_BDTBA_MASK                  (0xFFU)
+#define USB_BDTPAGE2_BDTBA_SHIFT                 (0U)
+#define USB_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
+/*! @} */
+
+/*! @name BDTPAGE3 - BDT Page Register 3 */
+/*! @{ */
+#define USB_BDTPAGE3_BDTBA_MASK                  (0xFFU)
+#define USB_BDTPAGE3_BDTBA_SHIFT                 (0U)
+#define USB_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
+/*! @} */
+
+/*! @name ENDPT - Endpoint Control register */
+/*! @{ */
+#define USB_ENDPT_EPHSHK_MASK                    (0x1U)
+#define USB_ENDPT_EPHSHK_SHIFT                   (0U)
+#define USB_ENDPT_EPHSHK(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
+#define USB_ENDPT_EPSTALL_MASK                   (0x2U)
+#define USB_ENDPT_EPSTALL_SHIFT                  (1U)
+#define USB_ENDPT_EPSTALL(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
+#define USB_ENDPT_EPTXEN_MASK                    (0x4U)
+#define USB_ENDPT_EPTXEN_SHIFT                   (2U)
+#define USB_ENDPT_EPTXEN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
+#define USB_ENDPT_EPRXEN_MASK                    (0x8U)
+#define USB_ENDPT_EPRXEN_SHIFT                   (3U)
+#define USB_ENDPT_EPRXEN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
+#define USB_ENDPT_EPCTLDIS_MASK                  (0x10U)
+#define USB_ENDPT_EPCTLDIS_SHIFT                 (4U)
+#define USB_ENDPT_EPCTLDIS(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
+/*! @} */
+
+/* The count of USB_ENDPT */
+#define USB_ENDPT_COUNT                          (16U)
+
+/*! @name USBCTRL - USB Control register */
+/*! @{ */
+#define USB_USBCTRL_UARTSEL_MASK                 (0x10U)
+#define USB_USBCTRL_UARTSEL_SHIFT                (4U)
+/*! UARTSEL - UART Select
+ *  0b0..USB signals are not used as UART signals.
+ *  0b1..USB signals are used as UART signals.
+ */
+#define USB_USBCTRL_UARTSEL(x)                   (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK)
+#define USB_USBCTRL_UARTCHLS_MASK                (0x20U)
+#define USB_USBCTRL_UARTCHLS_SHIFT               (5U)
+/*! UARTCHLS - UART Signal Channel Select
+ *  0b0..USB DP/DM signals are used as UART TX/RX.
+ *  0b1..USB DP/DM signals are used as UART RX/TX.
+ */
+#define USB_USBCTRL_UARTCHLS(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK)
+#define USB_USBCTRL_PDE_MASK                     (0x40U)
+#define USB_USBCTRL_PDE_SHIFT                    (6U)
+/*! PDE - Pulldown enable
+ *  0b0..Weak pulldowns are disabled on D+ and D-.
+ *  0b1..Weak pulldowns are enabled on D+ and D-.
+ */
+#define USB_USBCTRL_PDE(x)                       (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
+#define USB_USBCTRL_SUSP_MASK                    (0x80U)
+#define USB_USBCTRL_SUSP_SHIFT                   (7U)
+/*! SUSP - Suspend
+ *  0b0..USB transceiver is not in the Suspend state.
+ *  0b1..USB transceiver is in the Suspend state.
+ */
+#define USB_USBCTRL_SUSP(x)                      (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
+/*! @} */
+
+/*! @name OBSERVE - USB OTG Observe register */
+/*! @{ */
+#define USB_OBSERVE_DMPD_MASK                    (0x10U)
+#define USB_OBSERVE_DMPD_SHIFT                   (4U)
+/*! DMPD - DMPD
+ *  0b0..D- pulldown is disabled.
+ *  0b1..D- pulldown is enabled.
+ */
+#define USB_OBSERVE_DMPD(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
+#define USB_OBSERVE_DPPD_MASK                    (0x40U)
+#define USB_OBSERVE_DPPD_SHIFT                   (6U)
+/*! DPPD - DPPD
+ *  0b0..D+ pulldown is disabled.
+ *  0b1..D+ pulldown is enabled.
+ */
+#define USB_OBSERVE_DPPD(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
+#define USB_OBSERVE_DPPU_MASK                    (0x80U)
+#define USB_OBSERVE_DPPU_SHIFT                   (7U)
+/*! DPPU - DPPU
+ *  0b0..D+ pullup disabled.
+ *  0b1..D+ pullup enabled.
+ */
+#define USB_OBSERVE_DPPU(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
+/*! @} */
+
+/*! @name CONTROL - USB OTG Control register */
+/*! @{ */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK          (0x10U)
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT         (4U)
+/*! DPPULLUPNONOTG - DPPULLUPNONOTG
+ *  0b0..DP Pullup in non-OTG Device mode is not enabled.
+ *  0b1..DP Pullup in non-OTG Device mode is enabled.
+ */
+#define USB_CONTROL_DPPULLUPNONOTG(x)            (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
+/*! @} */
+
+/*! @name USBTRC0 - USB Transceiver Control register 0 */
+/*! @{ */
+#define USB_USBTRC0_USB_RESUME_INT_MASK          (0x1U)
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT         (0U)
+/*! USB_RESUME_INT - USB Asynchronous Interrupt
+ *  0b0..No interrupt was generated.
+ *  0b1..Interrupt was generated because of the USB asynchronous interrupt.
+ */
+#define USB_USBTRC0_USB_RESUME_INT(x)            (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
+#define USB_USBTRC0_SYNC_DET_MASK                (0x2U)
+#define USB_USBTRC0_SYNC_DET_SHIFT               (1U)
+/*! SYNC_DET - Synchronous USB Interrupt Detect
+ *  0b0..Synchronous interrupt has not been detected.
+ *  0b1..Synchronous interrupt has been detected.
+ */
+#define USB_USBTRC0_SYNC_DET(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK    (0x4U)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT   (2U)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x)      (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
+#define USB_USBTRC0_VREDG_DET_MASK               (0x8U)
+#define USB_USBTRC0_VREDG_DET_SHIFT              (3U)
+/*! VREDG_DET - VREGIN Rising Edge Interrupt Detect
+ *  0b0..VREGIN rising edge interrupt has not been detected.
+ *  0b1..VREGIN rising edge interrupt has been detected.
+ */
+#define USB_USBTRC0_VREDG_DET(x)                 (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK)
+#define USB_USBTRC0_VFEDG_DET_MASK               (0x10U)
+#define USB_USBTRC0_VFEDG_DET_SHIFT              (4U)
+/*! VFEDG_DET - VREGIN Falling Edge Interrupt Detect
+ *  0b0..VREGIN falling edge interrupt has not been detected.
+ *  0b1..VREGIN falling edge interrupt has been detected.
+ */
+#define USB_USBTRC0_VFEDG_DET(x)                 (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK)
+#define USB_USBTRC0_USBRESMEN_MASK               (0x20U)
+#define USB_USBTRC0_USBRESMEN_SHIFT              (5U)
+/*! USBRESMEN - Asynchronous Resume Interrupt Enable
+ *  0b0..USB asynchronous wakeup from Suspend mode is disabled.
+ *  0b1..USB asynchronous wakeup from Suspend mode is enabled.
+ */
+#define USB_USBTRC0_USBRESMEN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
+#define USB_USBTRC0_VREGIN_STS_MASK              (0x40U)
+#define USB_USBTRC0_VREGIN_STS_SHIFT             (6U)
+#define USB_USBTRC0_VREGIN_STS(x)                (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREGIN_STS_SHIFT)) & USB_USBTRC0_VREGIN_STS_MASK)
+#define USB_USBTRC0_USBRESET_MASK                (0x80U)
+#define USB_USBTRC0_USBRESET_SHIFT               (7U)
+/*! USBRESET - USB Reset
+ *  0b0..Normal USB module operation.
+ *  0b1..Returns the USB module to its reset state.
+ */
+#define USB_USBTRC0_USBRESET(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
+/*! @} */
+
+/*! @name KEEP_ALIVE_CTRL - Keep Alive mode control */
+/*! @{ */
+#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK   (0x1U)
+#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT  (0U)
+#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN(x)     (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK)
+#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK   (0x2U)
+#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT  (1U)
+#define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN(x)     (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK)
+#define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK (0x4U)
+#define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT (2U)
+/*! STOP_ACK_DLY_EN - STOP_ACK_DLY_EN
+ *  0b0..Enter KEEP_ALIVE mode until the USB core is idle and there is no USB AHB transfer.
+ *  0b1..Enter KEEP_ALIVE mode immediately when there is no USB AHB transfer.
+ */
+#define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN(x)   (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK)
+#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK     (0x8U)
+#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT    (3U)
+/*! WAKE_REQ_EN - WAKE_REQ_EN
+ *  0b0..USB bus wakeup request is disabled
+ *  0b1..USB bus wakeup request is enabled
+ */
+#define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN(x)       (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK)
+#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK     (0x10U)
+#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT    (4U)
+#define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN(x)       (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK)
+#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_MASK  (0x40U)
+#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_SHIFT (6U)
+/*! KEEP_ALIVE_STS - Keep Alive Status
+ *  0b0..USB is not in Keep Alive mode.
+ *  0b1..USB is in Keep Alive mode.
+ */
+#define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS(x)    (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_MASK)
+#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK    (0x80U)
+#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT   (7U)
+#define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS(x)      (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK)
+/*! @} */
+
+/*! @name KEEP_ALIVE_WKCTRL - Keep Alive mode wakeup control */
+/*! @{ */
+#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK  (0xFU)
+#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT (0U)
+/*! WAKE_ON_THIS - WAKE_ON_THIS
+ *  0b0001..Wake up after receiving OUT/SETUP token packet.
+ *  0b1101..Wake up after receiving SETUP token packet. All other values are reserved.
+ */
+#define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS(x)    (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK)
+#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK    (0xF0U)
+#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT   (4U)
+#define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT(x)      (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK)
+/*! @} */
+
+/*! @name MISCCTRL - Miscellaneous Control register */
+/*! @{ */
+#define USB_MISCCTRL_SOFDYNTHLD_MASK             (0x1U)
+#define USB_MISCCTRL_SOFDYNTHLD_SHIFT            (0U)
+/*! SOFDYNTHLD - Dynamic SOF Threshold Compare mode
+ *  0b0..SOF_TOK interrupt is set when byte times SOF threshold is reached.
+ *  0b1..SOF_TOK interrupt is set when 8 byte times SOF threshold is reached or overstepped.
+ */
+#define USB_MISCCTRL_SOFDYNTHLD(x)               (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFDYNTHLD_SHIFT)) & USB_MISCCTRL_SOFDYNTHLD_MASK)
+#define USB_MISCCTRL_SOFBUSSET_MASK              (0x2U)
+#define USB_MISCCTRL_SOFBUSSET_SHIFT             (1U)
+/*! SOFBUSSET - SOF_TOK Interrupt Generation Mode Select
+ *  0b0..SOF_TOK interrupt is set according to SOF threshold value.
+ *  0b1..SOF_TOK interrupt is set when SOF counter reaches 0.
+ */
+#define USB_MISCCTRL_SOFBUSSET(x)                (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFBUSSET_SHIFT)) & USB_MISCCTRL_SOFBUSSET_MASK)
+#define USB_MISCCTRL_OWNERRISODIS_MASK           (0x4U)
+#define USB_MISCCTRL_OWNERRISODIS_SHIFT          (2U)
+/*! OWNERRISODIS - OWN Error Detect for ISO IN / ISO OUT Disable
+ *  0b0..OWN error detect for ISO IN / ISO OUT is not disabled.
+ *  0b1..OWN error detect for ISO IN / ISO OUT is disabled.
+ */
+#define USB_MISCCTRL_OWNERRISODIS(x)             (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK)
+#define USB_MISCCTRL_VREDG_EN_MASK               (0x8U)
+#define USB_MISCCTRL_VREDG_EN_SHIFT              (3U)
+/*! VREDG_EN - VREGIN Rising Edge Interrupt Enable
+ *  0b0..VREGIN rising edge interrupt disabled.
+ *  0b1..VREGIN rising edge interrupt enabled.
+ */
+#define USB_MISCCTRL_VREDG_EN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK)
+#define USB_MISCCTRL_VFEDG_EN_MASK               (0x10U)
+#define USB_MISCCTRL_VFEDG_EN_SHIFT              (4U)
+/*! VFEDG_EN - VREGIN Falling Edge Interrupt Enable
+ *  0b0..VREGIN falling edge interrupt disabled.
+ *  0b1..VREGIN falling edge interrupt enabled.
+ */
+#define USB_MISCCTRL_VFEDG_EN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK)
+#define USB_MISCCTRL_STL_ADJ_EN_MASK             (0x80U)
+#define USB_MISCCTRL_STL_ADJ_EN_SHIFT            (7U)
+/*! STL_ADJ_EN - USB Peripheral mode Stall Adjust Enable
+ *  0b0..If USB_ENDPTn[END_STALL] = 1, both IN and OUT directions for the associated endpoint will be stalled
+ *  0b1..If USB_ENDPTn[END_STALL] = 1, the USB_STALL_xx_DIS registers control which directions for the associated endpoint will be stalled.
+ */
+#define USB_MISCCTRL_STL_ADJ_EN(x)               (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_STL_ADJ_EN_SHIFT)) & USB_MISCCTRL_STL_ADJ_EN_MASK)
+/*! @} */
+
+/*! @name STALL_IL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in IN direction */
+/*! @{ */
+#define USB_STALL_IL_DIS_STALL_I_DIS0_MASK       (0x1U)
+#define USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT      (0U)
+/*! STALL_I_DIS0 - STALL_I_DIS0
+ *  0b0..Endpoint 0 IN direction stall is enabled.
+ *  0b1..Endpoint 0 IN direction stall is disabled.
+ */
+#define USB_STALL_IL_DIS_STALL_I_DIS0(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS0_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS1_MASK       (0x2U)
+#define USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT      (1U)
+/*! STALL_I_DIS1 - STALL_I_DIS1
+ *  0b0..Endpoint 1 IN direction stall is enabled.
+ *  0b1..Endpoint 1 IN direction stall is disabled.
+ */
+#define USB_STALL_IL_DIS_STALL_I_DIS1(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS1_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS2_MASK       (0x4U)
+#define USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT      (2U)
+/*! STALL_I_DIS2 - STALL_I_DIS2
+ *  0b0..Endpoint 2 IN direction stall is enabled.
+ *  0b1..Endpoint 2 IN direction stall is disabled.
+ */
+#define USB_STALL_IL_DIS_STALL_I_DIS2(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS2_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS3_MASK       (0x8U)
+#define USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT      (3U)
+/*! STALL_I_DIS3 - STALL_I_DIS3
+ *  0b0..Endpoint 3 IN direction stall is enabled.
+ *  0b1..Endpoint 3 IN direction stall is disabled.
+ */
+#define USB_STALL_IL_DIS_STALL_I_DIS3(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS3_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS4_MASK       (0x10U)
+#define USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT      (4U)
+/*! STALL_I_DIS4 - STALL_I_DIS4
+ *  0b0..Endpoint 4 IN direction stall is enabled.
+ *  0b1..Endpoint 4 IN direction stall is disabled.
+ */
+#define USB_STALL_IL_DIS_STALL_I_DIS4(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS4_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS5_MASK       (0x20U)
+#define USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT      (5U)
+/*! STALL_I_DIS5 - STALL_I_DIS5
+ *  0b0..Endpoint 5 IN direction stall is enabled.
+ *  0b1..Endpoint 5 IN direction stall is disabled.
+ */
+#define USB_STALL_IL_DIS_STALL_I_DIS5(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS5_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS6_MASK       (0x40U)
+#define USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT      (6U)
+/*! STALL_I_DIS6 - STALL_I_DIS6
+ *  0b0..Endpoint 6 IN direction stall is enabled.
+ *  0b1..Endpoint 6 IN direction stall is disabled.
+ */
+#define USB_STALL_IL_DIS_STALL_I_DIS6(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS6_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS7_MASK       (0x80U)
+#define USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT      (7U)
+/*! STALL_I_DIS7 - STALL_I_DIS7
+ *  0b0..Endpoint 7 IN direction stall is enabled.
+ *  0b1..Endpoint 7 IN direction stall is disabled.
+ */
+#define USB_STALL_IL_DIS_STALL_I_DIS7(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS7_MASK)
+/*! @} */
+
+/*! @name STALL_IH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in IN direction */
+/*! @{ */
+#define USB_STALL_IH_DIS_STALL_I_DIS8_MASK       (0x1U)
+#define USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT      (0U)
+/*! STALL_I_DIS8 - STALL_I_DIS8
+ *  0b0..Endpoint 8 IN direction stall is enabled.
+ *  0b1..Endpoint 8 IN direction stall is disabled.
+ */
+#define USB_STALL_IH_DIS_STALL_I_DIS8(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS8_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS9_MASK       (0x2U)
+#define USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT      (1U)
+/*! STALL_I_DIS9 - STALL_I_DIS9
+ *  0b0..Endpoint 9 IN direction stall is enabled.
+ *  0b1..Endpoint 9 IN direction stall is disabled.
+ */
+#define USB_STALL_IH_DIS_STALL_I_DIS9(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS9_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS10_MASK      (0x4U)
+#define USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT     (2U)
+/*! STALL_I_DIS10 - STALL_I_DIS10
+ *  0b0..Endpoint 10 IN direction stall is enabled.
+ *  0b1..Endpoint 10 IN direction stall is disabled.
+ */
+#define USB_STALL_IH_DIS_STALL_I_DIS10(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS10_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS11_MASK      (0x8U)
+#define USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT     (3U)
+/*! STALL_I_DIS11 - STALL_I_DIS11
+ *  0b0..Endpoint 11 IN direction stall is enabled.
+ *  0b1..Endpoint 11 IN direction stall is disabled.
+ */
+#define USB_STALL_IH_DIS_STALL_I_DIS11(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS11_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS12_MASK      (0x10U)
+#define USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT     (4U)
+/*! STALL_I_DIS12 - STALL_I_DIS12
+ *  0b0..Endpoint 12 IN direction stall is enabled.
+ *  0b1..Endpoint 12 IN direction stall is disabled.
+ */
+#define USB_STALL_IH_DIS_STALL_I_DIS12(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS12_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS13_MASK      (0x20U)
+#define USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT     (5U)
+/*! STALL_I_DIS13 - STALL_I_DIS13
+ *  0b0..Endpoint 13 IN direction stall is enabled.
+ *  0b1..Endpoint 13 IN direction stall is disabled.
+ */
+#define USB_STALL_IH_DIS_STALL_I_DIS13(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS13_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS14_MASK      (0x40U)
+#define USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT     (6U)
+/*! STALL_I_DIS14 - STALL_I_DIS14
+ *  0b0..Endpoint 14 IN direction stall is enabled.
+ *  0b1..Endpoint 14 IN direction stall is disabled.
+ */
+#define USB_STALL_IH_DIS_STALL_I_DIS14(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS14_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS15_MASK      (0x80U)
+#define USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT     (7U)
+/*! STALL_I_DIS15 - STALL_I_DIS15
+ *  0b0..Endpoint 15 IN direction stall is enabled.
+ *  0b1..Endpoint 15 IN direction stall is disabled.
+ */
+#define USB_STALL_IH_DIS_STALL_I_DIS15(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS15_MASK)
+/*! @} */
+
+/*! @name STALL_OL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in OUT direction */
+/*! @{ */
+#define USB_STALL_OL_DIS_STALL_O_DIS0_MASK       (0x1U)
+#define USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT      (0U)
+/*! STALL_O_DIS0 - STALL_O_DIS0
+ *  0b0..Endpoint 0 OUT direction stall is enabled.
+ *  0b1..Endpoint 0 OUT direction stall is disabled.
+ */
+#define USB_STALL_OL_DIS_STALL_O_DIS0(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS0_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS1_MASK       (0x2U)
+#define USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT      (1U)
+/*! STALL_O_DIS1 - STALL_O_DIS1
+ *  0b0..Endpoint 1 OUT direction stall is enabled.
+ *  0b1..Endpoint 1 OUT direction stall is disabled.
+ */
+#define USB_STALL_OL_DIS_STALL_O_DIS1(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS1_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS2_MASK       (0x4U)
+#define USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT      (2U)
+/*! STALL_O_DIS2 - STALL_O_DIS2
+ *  0b0..Endpoint 2 OUT direction stall is enabled.
+ *  0b1..Endpoint 2 OUT direction stall is disabled.
+ */
+#define USB_STALL_OL_DIS_STALL_O_DIS2(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS2_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS3_MASK       (0x8U)
+#define USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT      (3U)
+/*! STALL_O_DIS3 - STALL_O_DIS3
+ *  0b0..Endpoint 3 OUT direction stall is enabled.
+ *  0b1..Endpoint 3 OUT direction stall is disabled.
+ */
+#define USB_STALL_OL_DIS_STALL_O_DIS3(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS3_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS4_MASK       (0x10U)
+#define USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT      (4U)
+/*! STALL_O_DIS4 - STALL_O_DIS4
+ *  0b0..Endpoint 4 OUT direction stall is enabled.
+ *  0b1..Endpoint 4 OUT direction stall is disabled.
+ */
+#define USB_STALL_OL_DIS_STALL_O_DIS4(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS4_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS5_MASK       (0x20U)
+#define USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT      (5U)
+/*! STALL_O_DIS5 - STALL_O_DIS5
+ *  0b0..Endpoint 5 OUT direction stall is enabled.
+ *  0b1..Endpoint 5 OUT direction stall is disabled.
+ */
+#define USB_STALL_OL_DIS_STALL_O_DIS5(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS5_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS6_MASK       (0x40U)
+#define USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT      (6U)
+/*! STALL_O_DIS6 - STALL_O_DIS6
+ *  0b0..Endpoint 6 OUT direction stall is enabled.
+ *  0b1..Endpoint 6 OUT direction stall is disabled.
+ */
+#define USB_STALL_OL_DIS_STALL_O_DIS6(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS6_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS7_MASK       (0x80U)
+#define USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT      (7U)
+/*! STALL_O_DIS7 - STALL_O_DIS7
+ *  0b0..Endpoint 7 OUT direction stall is enabled.
+ *  0b1..Endpoint 7 OUT direction stall is disabled.
+ */
+#define USB_STALL_OL_DIS_STALL_O_DIS7(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS7_MASK)
+/*! @} */
+
+/*! @name STALL_OH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in OUT direction */
+/*! @{ */
+#define USB_STALL_OH_DIS_STALL_O_DIS8_MASK       (0x1U)
+#define USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT      (0U)
+/*! STALL_O_DIS8 - STALL_O_DIS8
+ *  0b0..Endpoint 8 OUT direction stall is enabled.
+ *  0b1..Endpoint 8 OUT direction stall is disabled.
+ */
+#define USB_STALL_OH_DIS_STALL_O_DIS8(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS8_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS9_MASK       (0x2U)
+#define USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT      (1U)
+/*! STALL_O_DIS9 - STALL_O_DIS9
+ *  0b0..Endpoint 9 OUT direction stall is enabled.
+ *  0b1..Endpoint 9 OUT direction stall is disabled.
+ */
+#define USB_STALL_OH_DIS_STALL_O_DIS9(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS9_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS10_MASK      (0x4U)
+#define USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT     (2U)
+/*! STALL_O_DIS10 - STALL_O_DIS10
+ *  0b0..Endpoint 10 OUT direction stall is enabled.
+ *  0b1..Endpoint 10 OUT direction stall is disabled.
+ */
+#define USB_STALL_OH_DIS_STALL_O_DIS10(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS10_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS11_MASK      (0x8U)
+#define USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT     (3U)
+/*! STALL_O_DIS11 - STALL_O_DIS11
+ *  0b0..Endpoint 11 OUT direction stall is enabled.
+ *  0b1..Endpoint 11 OUT direction stall is disabled.
+ */
+#define USB_STALL_OH_DIS_STALL_O_DIS11(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS11_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS12_MASK      (0x10U)
+#define USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT     (4U)
+/*! STALL_O_DIS12 - STALL_O_DIS12
+ *  0b0..Endpoint 12 OUT direction stall is enabled.
+ *  0b1..Endpoint 12 OUT direction stall is disabled.
+ */
+#define USB_STALL_OH_DIS_STALL_O_DIS12(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS12_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS13_MASK      (0x20U)
+#define USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT     (5U)
+/*! STALL_O_DIS13 - STALL_O_DIS13
+ *  0b0..Endpoint 13 OUT direction stall is enabled.
+ *  0b1..Endpoint 13 OUT direction stall is disabled.
+ */
+#define USB_STALL_OH_DIS_STALL_O_DIS13(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS13_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS14_MASK      (0x40U)
+#define USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT     (6U)
+/*! STALL_O_DIS14 - STALL_O_DIS14
+ *  0b0..Endpoint 14 OUT direction stall is enabled.
+ *  0b1..Endpoint 14 OUT direction stall is disabled.
+ */
+#define USB_STALL_OH_DIS_STALL_O_DIS14(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS14_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS15_MASK      (0x80U)
+#define USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT     (7U)
+/*! STALL_O_DIS15 - STALL_O_DIS15
+ *  0b0..Endpoint 15 OUT direction stall is enabled.
+ *  0b1..Endpoint 15 OUT direction stall is disabled.
+ */
+#define USB_STALL_OH_DIS_STALL_O_DIS15(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS15_MASK)
+/*! @} */
+
+/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
+/*! @{ */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
+/*! RESTART_IFRTRIM_EN - Restart from IFR trim value
+ *  0b0..Trim fine adjustment always works based on the previous updated trim fine value (default).
+ *  0b1..Trim fine restarts from the IFR trim value, whenever bus_reset/bus_resume is detected or module enable is desasserted.
+ */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
+/*! RESET_RESUME_ROUGH_EN - Reset/resume to rough phase enable
+ *  0b0..Always works in tracking phase after the first time rough phase, to track transition (default).
+ *  0b1..Go back to rough stage whenever a bus reset or bus resume occurs.
+ */
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
+/*! CLOCK_RECOVER_EN - Crystal-less USB enable
+ *  0b0..Disable clock recovery block (default)
+ *  0b1..Enable clock recovery block
+ */
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
+/*! @} */
+
+/*! @name CLK_RECOVER_IRC_EN - IRC48MFIRC oscillator enable register */
+/*! @{ */
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK       (0x1U)
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT      (0U)
+/*! REG_EN - Regulator enable
+ *  0b0..IRC48M local regulator is disabled
+ *  0b1..IRC48M local regulator is enabled (default)
+ */
+#define USB_CLK_RECOVER_IRC_EN_REG_EN(x)         (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK       (0x2U)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT      (1U)
+/*! IRC_EN - IRC_EN
+ *  0b0..Disable the IRC48M module (default)
+ *  0b1..Enable the IRC48M module
+ */
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x)         (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
+/*! @} */
+
+/*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */
+/*! @{ */
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U)
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U)
+/*! OVF_ERROR_EN - OVF_ERROR_EN
+ *  0b0..The interrupt will be masked
+ *  0b1..The interrupt will be enabled (default)
+ */
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x)   (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
+/*! @} */
+
+/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
+/*! @{ */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
+/*! OVF_ERROR - OVF_ERROR
+ *  0b0..No interrupt is reported
+ *  0b1..Unmasked interrupt has been generated
+ */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x)  (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE                                (0x40045000u)
+/** Peripheral USB0 base pointer */
+#define USB0                                     ((USB_Type *)USB0_BASE)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS                           { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS                            { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS                                 { USB0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBVREG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBVREG_Peripheral_Access_Layer USBVREG Peripheral Access Layer
+ * @{
+ */
+
+/** USBVREG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< USB VREG Control Register, offset: 0x0 */
+  __IO uint32_t CFGCTRL;                           /**< USB VREG Configuration Control Register, offset: 0x4 */
+} USBVREG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USBVREG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBVREG_Register_Masks USBVREG Register Masks
+ * @{
+ */
+
+/*! @name CTRL - USB VREG Control Register */
+/*! @{ */
+#define USBVREG_CTRL_VSTBY_MASK                  (0x20000000U)
+#define USBVREG_CTRL_VSTBY_SHIFT                 (29U)
+/*! VSTBY - USB Voltage Regulator in Standby Mode during VLPR and VLPW modes
+ *  0b0..USB voltage regulator is not in standby during VLPR and VLPW modes.
+ *  0b1..USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+#define USBVREG_CTRL_VSTBY(x)                    (((uint32_t)(((uint32_t)(x)) << USBVREG_CTRL_VSTBY_SHIFT)) & USBVREG_CTRL_VSTBY_MASK)
+#define USBVREG_CTRL_SSTBY_MASK                  (0x40000000U)
+#define USBVREG_CTRL_SSTBY_SHIFT                 (30U)
+/*! SSTBY - USB Voltage Regulator in Standby Mode during Stop, VLPS, LLS and VLLS Modes
+ *  0b0..USB voltage regulator is not in standby during Stop,VLPS,LLS and VLLS modes.
+ *  0b1..USB voltage regulator is in standby during Stop,VLPS,LLS and VLLS modes.
+ */
+#define USBVREG_CTRL_SSTBY(x)                    (((uint32_t)(((uint32_t)(x)) << USBVREG_CTRL_SSTBY_SHIFT)) & USBVREG_CTRL_SSTBY_MASK)
+#define USBVREG_CTRL_EN_MASK                     (0x80000000U)
+#define USBVREG_CTRL_EN_SHIFT                    (31U)
+/*! EN - USB Voltage Regulator Enable
+ *  0b0..USB voltage regulator is disabled.
+ *  0b1..USB voltage regulator is enabled.
+ */
+#define USBVREG_CTRL_EN(x)                       (((uint32_t)(((uint32_t)(x)) << USBVREG_CTRL_EN_SHIFT)) & USBVREG_CTRL_EN_MASK)
+/*! @} */
+
+/*! @name CFGCTRL - USB VREG Configuration Control Register */
+/*! @{ */
+#define USBVREG_CFGCTRL_URWE_MASK                (0x1000000U)
+#define USBVREG_CFGCTRL_URWE_SHIFT               (24U)
+/*! URWE - USB Voltage Regulator Enable Write Enable
+ *  0b0..CTRL[EN] can not be written.
+ *  0b1..CTRL[EN] can be written.
+ */
+#define USBVREG_CFGCTRL_URWE(x)                  (((uint32_t)(((uint32_t)(x)) << USBVREG_CFGCTRL_URWE_SHIFT)) & USBVREG_CFGCTRL_URWE_MASK)
+#define USBVREG_CFGCTRL_UVSWE_MASK               (0x2000000U)
+#define USBVREG_CFGCTRL_UVSWE_SHIFT              (25U)
+/*! UVSWE - USB Voltage Regulator VLP Standby Write Enable
+ *  0b0..CTRL[VSTBY] cannot be written.
+ *  0b1..CTRL[VSTBY] can be written.
+ */
+#define USBVREG_CFGCTRL_UVSWE(x)                 (((uint32_t)(((uint32_t)(x)) << USBVREG_CFGCTRL_UVSWE_SHIFT)) & USBVREG_CFGCTRL_UVSWE_MASK)
+#define USBVREG_CFGCTRL_USSWE_MASK               (0x4000000U)
+#define USBVREG_CFGCTRL_USSWE_SHIFT              (26U)
+/*! USSWE - USB Voltage Rregulator Stop Standby Write Enable
+ *  0b0..CTRL[SSTBY] field cannot be written.
+ *  0b1..CTRL[SSTBY] can be written.
+ */
+#define USBVREG_CFGCTRL_USSWE(x)                 (((uint32_t)(((uint32_t)(x)) << USBVREG_CFGCTRL_USSWE_SHIFT)) & USBVREG_CFGCTRL_USSWE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USBVREG_Register_Masks */
+
+
+/* USBVREG - Peripheral instance base addresses */
+/** Peripheral USBVREG base address */
+#define USBVREG_BASE                             (0x40027000u)
+/** Peripheral USBVREG base pointer */
+#define USBVREG                                  ((USBVREG_Type *)USBVREG_BASE)
+/** Array initializer of USBVREG peripheral base addresses */
+#define USBVREG_BASE_ADDRS                       { USBVREG_BASE }
+/** Array initializer of USBVREG peripheral base pointers */
+#define USBVREG_BASE_PTRS                        { USBVREG }
+
+/*!
+ * @}
+ */ /* end of group USBVREG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USDHC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer
+ * @{
+ */
+
+/** USDHC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t DS_ADDR;                           /**< DMA System Address, offset: 0x0 */
+  __IO uint32_t BLK_ATT;                           /**< Block Attributes, offset: 0x4 */
+  __IO uint32_t CMD_ARG;                           /**< Command Argument, offset: 0x8 */
+  __IO uint32_t CMD_XFR_TYP;                       /**< Command Transfer Type, offset: 0xC */
+  __I  uint32_t CMD_RSP0;                          /**< Command Response0, offset: 0x10 */
+  __I  uint32_t CMD_RSP1;                          /**< Command Response1, offset: 0x14 */
+  __I  uint32_t CMD_RSP2;                          /**< Command Response2, offset: 0x18 */
+  __I  uint32_t CMD_RSP3;                          /**< Command Response3, offset: 0x1C */
+  __IO uint32_t DATA_BUFF_ACC_PORT;                /**< Data Buffer Access Port, offset: 0x20 */
+  __I  uint32_t PRES_STATE;                        /**< Present State, offset: 0x24 */
+  __IO uint32_t PROT_CTRL;                         /**< Protocol Control, offset: 0x28 */
+  __IO uint32_t SYS_CTRL;                          /**< System Control, offset: 0x2C */
+  __IO uint32_t INT_STATUS;                        /**< Interrupt Status, offset: 0x30 */
+  __IO uint32_t INT_STATUS_EN;                     /**< Interrupt Status Enable, offset: 0x34 */
+  __IO uint32_t INT_SIGNAL_EN;                     /**< Interrupt Signal Enable, offset: 0x38 */
+  __I  uint32_t AUTOCMD12_ERR_STATUS;              /**< Auto CMD12 Error Status, offset: 0x3C */
+  __I  uint32_t HOST_CTRL_CAP;                     /**< Host Controller Capabilities, offset: 0x40 */
+  __IO uint32_t WTMK_LVL;                          /**< Watermark Level, offset: 0x44 */
+  __IO uint32_t MIX_CTRL;                          /**< Mixer Control, offset: 0x48 */
+       uint8_t RESERVED_0[4];
+  __O  uint32_t FORCE_EVENT;                       /**< Force Event, offset: 0x50 */
+  __I  uint32_t ADMA_ERR_STATUS;                   /**< ADMA Error Status Register, offset: 0x54 */
+  __IO uint32_t ADMA_SYS_ADDR;                     /**< ADMA System Address, offset: 0x58 */
+       uint8_t RESERVED_1[100];
+  __IO uint32_t VEND_SPEC;                         /**< Vendor Specific Register, offset: 0xC0 */
+  __IO uint32_t MMC_BOOT;                          /**< MMC Boot Register, offset: 0xC4 */
+  __IO uint32_t VEND_SPEC2;                        /**< Vendor Specific 2 Register, offset: 0xC8 */
+} USDHC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USDHC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USDHC_Register_Masks USDHC Register Masks
+ * @{
+ */
+
+/*! @name DS_ADDR - DMA System Address */
+/*! @{ */
+#define USDHC_DS_ADDR_DS_ADDR_MASK               (0xFFFFFFFFU)
+#define USDHC_DS_ADDR_DS_ADDR_SHIFT              (0U)
+#define USDHC_DS_ADDR_DS_ADDR(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
+/*! @} */
+
+/*! @name BLK_ATT - Block Attributes */
+/*! @{ */
+#define USDHC_BLK_ATT_BLKSIZE_MASK               (0x1FFFU)
+#define USDHC_BLK_ATT_BLKSIZE_SHIFT              (0U)
+/*! BLKSIZE - Block Size
+ *  0b1000000000000..4096 Bytes
+ *  0b0100000000000..2048 Bytes
+ *  0b0001000000000..512 Bytes
+ *  0b0000111111111..511 Bytes
+ *  0b0000000000100..4 Bytes
+ *  0b0000000000011..3 Bytes
+ *  0b0000000000010..2 Bytes
+ *  0b0000000000001..1 Byte
+ *  0b0000000000000..No data transfer
+ */
+#define USDHC_BLK_ATT_BLKSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
+#define USDHC_BLK_ATT_BLKCNT_MASK                (0xFFFF0000U)
+#define USDHC_BLK_ATT_BLKCNT_SHIFT               (16U)
+/*! BLKCNT - Block Count
+ *  0b1111111111111111..65535 blocks
+ *  0b0000000000000010..2 blocks
+ *  0b0000000000000001..1 block
+ *  0b0000000000000000..Stop Count
+ */
+#define USDHC_BLK_ATT_BLKCNT(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
+/*! @} */
+
+/*! @name CMD_ARG - Command Argument */
+/*! @{ */
+#define USDHC_CMD_ARG_CMDARG_MASK                (0xFFFFFFFFU)
+#define USDHC_CMD_ARG_CMDARG_SHIFT               (0U)
+#define USDHC_CMD_ARG_CMDARG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
+/*! @} */
+
+/*! @name CMD_XFR_TYP - Command Transfer Type */
+/*! @{ */
+#define USDHC_CMD_XFR_TYP_RSPTYP_MASK            (0x30000U)
+#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT           (16U)
+/*! RSPTYP - Response Type Select
+ *  0b00..No Response
+ *  0b01..Response Length 136
+ *  0b10..Response Length 48
+ *  0b11..Response Length 48, check Busy after response
+ */
+#define USDHC_CMD_XFR_TYP_RSPTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
+#define USDHC_CMD_XFR_TYP_CCCEN_MASK             (0x80000U)
+#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT            (19U)
+/*! CCCEN - Command CRC Check Enable
+ *  0b1..Enable
+ *  0b0..Disable
+ */
+#define USDHC_CMD_XFR_TYP_CCCEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
+#define USDHC_CMD_XFR_TYP_CICEN_MASK             (0x100000U)
+#define USDHC_CMD_XFR_TYP_CICEN_SHIFT            (20U)
+/*! CICEN - Command Index Check Enable
+ *  0b1..Enable
+ *  0b0..Disable
+ */
+#define USDHC_CMD_XFR_TYP_CICEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
+#define USDHC_CMD_XFR_TYP_DPSEL_MASK             (0x200000U)
+#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT            (21U)
+/*! DPSEL - Data Present Select
+ *  0b1..Data Present
+ *  0b0..No Data Present
+ */
+#define USDHC_CMD_XFR_TYP_DPSEL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
+#define USDHC_CMD_XFR_TYP_CMDTYP_MASK            (0xC00000U)
+#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT           (22U)
+/*! CMDTYP - Command Type
+ *  0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR
+ *  0b10..Resume CMD52 for writing Function Select in CCCR
+ *  0b01..Suspend CMD52 for writing Bus Suspend in CCCR
+ *  0b00..Normal Other commands
+ */
+#define USDHC_CMD_XFR_TYP_CMDTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
+#define USDHC_CMD_XFR_TYP_CMDINX_MASK            (0x3F000000U)
+#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT           (24U)
+#define USDHC_CMD_XFR_TYP_CMDINX(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
+/*! @} */
+
+/*! @name CMD_RSP0 - Command Response0 */
+/*! @{ */
+#define USDHC_CMD_RSP0_CMDRSP0_MASK              (0xFFFFFFFFU)
+#define USDHC_CMD_RSP0_CMDRSP0_SHIFT             (0U)
+#define USDHC_CMD_RSP0_CMDRSP0(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
+/*! @} */
+
+/*! @name CMD_RSP1 - Command Response1 */
+/*! @{ */
+#define USDHC_CMD_RSP1_CMDRSP1_MASK              (0xFFFFFFFFU)
+#define USDHC_CMD_RSP1_CMDRSP1_SHIFT             (0U)
+#define USDHC_CMD_RSP1_CMDRSP1(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
+/*! @} */
+
+/*! @name CMD_RSP2 - Command Response2 */
+/*! @{ */
+#define USDHC_CMD_RSP2_CMDRSP2_MASK              (0xFFFFFFFFU)
+#define USDHC_CMD_RSP2_CMDRSP2_SHIFT             (0U)
+#define USDHC_CMD_RSP2_CMDRSP2(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
+/*! @} */
+
+/*! @name CMD_RSP3 - Command Response3 */
+/*! @{ */
+#define USDHC_CMD_RSP3_CMDRSP3_MASK              (0xFFFFFFFFU)
+#define USDHC_CMD_RSP3_CMDRSP3_SHIFT             (0U)
+#define USDHC_CMD_RSP3_CMDRSP3(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
+/*! @} */
+
+/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */
+/*! @{ */
+#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK    (0xFFFFFFFFU)
+#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT   (0U)
+#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
+/*! @} */
+
+/*! @name PRES_STATE - Present State */
+/*! @{ */
+#define USDHC_PRES_STATE_CIHB_MASK               (0x1U)
+#define USDHC_PRES_STATE_CIHB_SHIFT              (0U)
+/*! CIHB - Command Inhibit (CMD)
+ *  0b1..Cannot issue command
+ *  0b0..Can issue command using only CMD line
+ */
+#define USDHC_PRES_STATE_CIHB(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
+#define USDHC_PRES_STATE_CDIHB_MASK              (0x2U)
+#define USDHC_PRES_STATE_CDIHB_SHIFT             (1U)
+/*! CDIHB - Command Inhibit (DATA)
+ *  0b1..Cannot issue command which uses the DATA line
+ *  0b0..Can issue command which uses the DATA line
+ */
+#define USDHC_PRES_STATE_CDIHB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
+#define USDHC_PRES_STATE_DLA_MASK                (0x4U)
+#define USDHC_PRES_STATE_DLA_SHIFT               (2U)
+/*! DLA - Data Line Active
+ *  0b1..DATA Line Active
+ *  0b0..DATA Line Inactive
+ */
+#define USDHC_PRES_STATE_DLA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
+#define USDHC_PRES_STATE_SDSTB_MASK              (0x8U)
+#define USDHC_PRES_STATE_SDSTB_SHIFT             (3U)
+/*! SDSTB - SD Clock Stable
+ *  0b1..Clock is stable.
+ *  0b0..Clock is changing frequency and not stable.
+ */
+#define USDHC_PRES_STATE_SDSTB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
+#define USDHC_PRES_STATE_IPGOFF_MASK             (0x10U)
+#define USDHC_PRES_STATE_IPGOFF_SHIFT            (4U)
+/*! IPGOFF - IPG_CLK Gated Off Internally
+ *  0b1..IPG_CLK is gated off.
+ *  0b0..IPG_CLK is active.
+ */
+#define USDHC_PRES_STATE_IPGOFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
+#define USDHC_PRES_STATE_HCKOFF_MASK             (0x20U)
+#define USDHC_PRES_STATE_HCKOFF_SHIFT            (5U)
+/*! HCKOFF - HCLK Gated Off Internally
+ *  0b1..HCLK is gated off.
+ *  0b0..HCLK is active.
+ */
+#define USDHC_PRES_STATE_HCKOFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
+#define USDHC_PRES_STATE_PEROFF_MASK             (0x40U)
+#define USDHC_PRES_STATE_PEROFF_SHIFT            (6U)
+/*! PEROFF - IPG_PERCLK Gated Off Internally
+ *  0b1..IPG_PERCLK is gated off.
+ *  0b0..IPG_PERCLK is active.
+ */
+#define USDHC_PRES_STATE_PEROFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
+#define USDHC_PRES_STATE_SDOFF_MASK              (0x80U)
+#define USDHC_PRES_STATE_SDOFF_SHIFT             (7U)
+/*! SDOFF - SD Clock Gated Off Internally
+ *  0b1..SD Clock is gated off.
+ *  0b0..SD Clock is active.
+ */
+#define USDHC_PRES_STATE_SDOFF(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
+#define USDHC_PRES_STATE_WTA_MASK                (0x100U)
+#define USDHC_PRES_STATE_WTA_SHIFT               (8U)
+/*! WTA - Write Transfer Active
+ *  0b1..Transferring data
+ *  0b0..No valid data
+ */
+#define USDHC_PRES_STATE_WTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
+#define USDHC_PRES_STATE_RTA_MASK                (0x200U)
+#define USDHC_PRES_STATE_RTA_SHIFT               (9U)
+/*! RTA - Read Transfer Active
+ *  0b1..Transferring data
+ *  0b0..No valid data
+ */
+#define USDHC_PRES_STATE_RTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
+#define USDHC_PRES_STATE_BWEN_MASK               (0x400U)
+#define USDHC_PRES_STATE_BWEN_SHIFT              (10U)
+/*! BWEN - Buffer Write Enable
+ *  0b1..Write enable
+ *  0b0..Write disable
+ */
+#define USDHC_PRES_STATE_BWEN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
+#define USDHC_PRES_STATE_BREN_MASK               (0x800U)
+#define USDHC_PRES_STATE_BREN_SHIFT              (11U)
+/*! BREN - Buffer Read Enable
+ *  0b1..Read enable
+ *  0b0..Read disable
+ */
+#define USDHC_PRES_STATE_BREN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
+#define USDHC_PRES_STATE_CINST_MASK              (0x10000U)
+#define USDHC_PRES_STATE_CINST_SHIFT             (16U)
+/*! CINST - Card Inserted
+ *  0b1..Card Inserted
+ *  0b0..Power on Reset or No Card
+ */
+#define USDHC_PRES_STATE_CINST(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
+#define USDHC_PRES_STATE_CDPL_MASK               (0x40000U)
+#define USDHC_PRES_STATE_CDPL_SHIFT              (18U)
+/*! CDPL - Card Detect Pin Level
+ *  0b1..Card present (CD_B = 0)
+ *  0b0..No card present (CD_B = 1)
+ */
+#define USDHC_PRES_STATE_CDPL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
+#define USDHC_PRES_STATE_WPSPL_MASK              (0x80000U)
+#define USDHC_PRES_STATE_WPSPL_SHIFT             (19U)
+/*! WPSPL - Write Protect Switch Pin Level
+ *  0b1..Write enabled (WP = 0)
+ *  0b0..Write protected (WP = 1)
+ */
+#define USDHC_PRES_STATE_WPSPL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
+#define USDHC_PRES_STATE_CLSL_MASK               (0x800000U)
+#define USDHC_PRES_STATE_CLSL_SHIFT              (23U)
+#define USDHC_PRES_STATE_CLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
+#define USDHC_PRES_STATE_DLSL_MASK               (0xFF000000U)
+#define USDHC_PRES_STATE_DLSL_SHIFT              (24U)
+/*! DLSL - DATA[7:0] Line Signal Level
+ *  0b00000111..Data 7 line signal level
+ *  0b00000110..Data 6 line signal level
+ *  0b00000101..Data 5 line signal level
+ *  0b00000100..Data 4 line signal level
+ *  0b00000011..Data 3 line signal level
+ *  0b00000010..Data 2 line signal level
+ *  0b00000001..Data 1 line signal level
+ *  0b00000000..Data 0 line signal level
+ */
+#define USDHC_PRES_STATE_DLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
+/*! @} */
+
+/*! @name PROT_CTRL - Protocol Control */
+/*! @{ */
+#define USDHC_PROT_CTRL_LCTL_MASK                (0x1U)
+#define USDHC_PROT_CTRL_LCTL_SHIFT               (0U)
+/*! LCTL - LED Control
+ *  0b1..LED on
+ *  0b0..LED off
+ */
+#define USDHC_PROT_CTRL_LCTL(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)
+#define USDHC_PROT_CTRL_DTW_MASK                 (0x6U)
+#define USDHC_PROT_CTRL_DTW_SHIFT                (1U)
+/*! DTW - Data Transfer Width
+ *  0b10..8-bit mode
+ *  0b01..4-bit mode
+ *  0b00..1-bit mode
+ *  0b11..Reserved
+ */
+#define USDHC_PROT_CTRL_DTW(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
+#define USDHC_PROT_CTRL_D3CD_MASK                (0x8U)
+#define USDHC_PROT_CTRL_D3CD_SHIFT               (3U)
+/*! D3CD - DATA3 as Card Detection Pin
+ *  0b1..DATA3 as Card Detection Pin
+ *  0b0..DATA3 does not monitor Card Insertion
+ */
+#define USDHC_PROT_CTRL_D3CD(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
+#define USDHC_PROT_CTRL_EMODE_MASK               (0x30U)
+#define USDHC_PROT_CTRL_EMODE_SHIFT              (4U)
+/*! EMODE - Endian Mode
+ *  0b00..Big Endian Mode
+ *  0b01..Half Word Big Endian Mode
+ *  0b10..Little Endian Mode
+ *  0b11..Reserved
+ */
+#define USDHC_PROT_CTRL_EMODE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
+#define USDHC_PROT_CTRL_CDTL_MASK                (0x40U)
+#define USDHC_PROT_CTRL_CDTL_SHIFT               (6U)
+/*! CDTL - Card Detect Test Level
+ *  0b1..Card Detect Test Level is 1, card inserted
+ *  0b0..Card Detect Test Level is 0, no card inserted
+ */
+#define USDHC_PROT_CTRL_CDTL(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
+#define USDHC_PROT_CTRL_CDSS_MASK                (0x80U)
+#define USDHC_PROT_CTRL_CDSS_SHIFT               (7U)
+/*! CDSS - Card Detect Signal Selection
+ *  0b1..Card Detection Test Level is selected (for test purpose).
+ *  0b0..Card Detection Level is selected (for normal purpose).
+ */
+#define USDHC_PROT_CTRL_CDSS(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
+#define USDHC_PROT_CTRL_DMASEL_MASK              (0x300U)
+#define USDHC_PROT_CTRL_DMASEL_SHIFT             (8U)
+/*! DMASEL - DMA Select
+ *  0b00..No DMA or Simple DMA is selected
+ *  0b01..ADMA1 is selected
+ *  0b10..ADMA2 is selected
+ *  0b11..reserved
+ */
+#define USDHC_PROT_CTRL_DMASEL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
+#define USDHC_PROT_CTRL_SABGREQ_MASK             (0x10000U)
+#define USDHC_PROT_CTRL_SABGREQ_SHIFT            (16U)
+/*! SABGREQ - Stop At Block Gap Request
+ *  0b1..Stop
+ *  0b0..Transfer
+ */
+#define USDHC_PROT_CTRL_SABGREQ(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
+#define USDHC_PROT_CTRL_CREQ_MASK                (0x20000U)
+#define USDHC_PROT_CTRL_CREQ_SHIFT               (17U)
+/*! CREQ - Continue Request
+ *  0b1..Restart
+ *  0b0..No effect
+ */
+#define USDHC_PROT_CTRL_CREQ(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
+#define USDHC_PROT_CTRL_RWCTL_MASK               (0x40000U)
+#define USDHC_PROT_CTRL_RWCTL_SHIFT              (18U)
+/*! RWCTL - Read Wait Control
+ *  0b1..Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set
+ *  0b0..Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set
+ */
+#define USDHC_PROT_CTRL_RWCTL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
+#define USDHC_PROT_CTRL_IABG_MASK                (0x80000U)
+#define USDHC_PROT_CTRL_IABG_SHIFT               (19U)
+/*! IABG - Interrupt At Block Gap
+ *  0b1..Enabled
+ *  0b0..Disabled
+ */
+#define USDHC_PROT_CTRL_IABG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
+#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK     (0x100000U)
+#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT    (20U)
+#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
+#define USDHC_PROT_CTRL_WECINT_MASK              (0x1000000U)
+#define USDHC_PROT_CTRL_WECINT_SHIFT             (24U)
+/*! WECINT - Wakeup Event Enable On Card Interrupt
+ *  0b1..Enable
+ *  0b0..Disable
+ */
+#define USDHC_PROT_CTRL_WECINT(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
+#define USDHC_PROT_CTRL_WECINS_MASK              (0x2000000U)
+#define USDHC_PROT_CTRL_WECINS_SHIFT             (25U)
+/*! WECINS - Wakeup Event Enable On SD Card Insertion
+ *  0b1..Enable
+ *  0b0..Disable
+ */
+#define USDHC_PROT_CTRL_WECINS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
+#define USDHC_PROT_CTRL_WECRM_MASK               (0x4000000U)
+#define USDHC_PROT_CTRL_WECRM_SHIFT              (26U)
+/*! WECRM - Wakeup Event Enable On SD Card Removal
+ *  0b1..Enable
+ *  0b0..Disable
+ */
+#define USDHC_PROT_CTRL_WECRM(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
+#define USDHC_PROT_CTRL_BURST_LEN_EN_MASK        (0x38000000U)
+#define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT       (27U)
+/*! BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP
+ *  0bxx1..Burst length is enabled for INCR
+ *  0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16
+ *  0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP
+ */
+#define USDHC_PROT_CTRL_BURST_LEN_EN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)
+#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK    (0x40000000U)
+#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT   (30U)
+/*! NON_EXACT_BLK_RD - NON_EXACT_BLK_RD
+ *  0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.
+ *  0b0..The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read.
+ */
+#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
+/*! @} */
+
+/*! @name SYS_CTRL - System Control */
+/*! @{ */
+#define USDHC_SYS_CTRL_DVS_MASK                  (0xF0U)
+#define USDHC_SYS_CTRL_DVS_SHIFT                 (4U)
+/*! DVS - Divisor
+ *  0b0000..Divide-by-1
+ *  0b0001..Divide-by-2
+ *  0b1110..Divide-by-15
+ *  0b1111..Divide-by-16
+ */
+#define USDHC_SYS_CTRL_DVS(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
+#define USDHC_SYS_CTRL_SDCLKFS_MASK              (0xFF00U)
+#define USDHC_SYS_CTRL_SDCLKFS_SHIFT             (8U)
+#define USDHC_SYS_CTRL_SDCLKFS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
+#define USDHC_SYS_CTRL_DTOCV_MASK                (0xF0000U)
+#define USDHC_SYS_CTRL_DTOCV_SHIFT               (16U)
+/*! DTOCV - Data Timeout Counter Value
+ *  0b1111..SDCLK x 2 29
+ *  0b1110..SDCLK x 2 28
+ *  0b1101..SDCLK x 2 27
+ *  0b0001..SDCLK x 2 15
+ *  0b0000..SDCLK x 2 14
+ */
+#define USDHC_SYS_CTRL_DTOCV(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
+#define USDHC_SYS_CTRL_IPP_RST_N_MASK            (0x800000U)
+#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT           (23U)
+#define USDHC_SYS_CTRL_IPP_RST_N(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
+#define USDHC_SYS_CTRL_RSTA_MASK                 (0x1000000U)
+#define USDHC_SYS_CTRL_RSTA_SHIFT                (24U)
+/*! RSTA - Software Reset For ALL
+ *  0b1..Reset
+ *  0b0..No Reset
+ */
+#define USDHC_SYS_CTRL_RSTA(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
+#define USDHC_SYS_CTRL_RSTC_MASK                 (0x2000000U)
+#define USDHC_SYS_CTRL_RSTC_SHIFT                (25U)
+/*! RSTC - Software Reset For CMD Line
+ *  0b1..Reset
+ *  0b0..No Reset
+ */
+#define USDHC_SYS_CTRL_RSTC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
+#define USDHC_SYS_CTRL_RSTD_MASK                 (0x4000000U)
+#define USDHC_SYS_CTRL_RSTD_SHIFT                (26U)
+/*! RSTD - Software Reset For DATA Line
+ *  0b1..Reset
+ *  0b0..No Reset
+ */
+#define USDHC_SYS_CTRL_RSTD(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
+#define USDHC_SYS_CTRL_INITA_MASK                (0x8000000U)
+#define USDHC_SYS_CTRL_INITA_SHIFT               (27U)
+#define USDHC_SYS_CTRL_INITA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
+/*! @} */
+
+/*! @name INT_STATUS - Interrupt Status */
+/*! @{ */
+#define USDHC_INT_STATUS_CC_MASK                 (0x1U)
+#define USDHC_INT_STATUS_CC_SHIFT                (0U)
+/*! CC - Command Complete
+ *  0b1..Command complete
+ *  0b0..Command not complete
+ */
+#define USDHC_INT_STATUS_CC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
+#define USDHC_INT_STATUS_TC_MASK                 (0x2U)
+#define USDHC_INT_STATUS_TC_SHIFT                (1U)
+/*! TC - Transfer Complete
+ *  0b1..Transfer complete
+ *  0b0..Transfer not complete
+ */
+#define USDHC_INT_STATUS_TC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
+#define USDHC_INT_STATUS_BGE_MASK                (0x4U)
+#define USDHC_INT_STATUS_BGE_SHIFT               (2U)
+/*! BGE - Block Gap Event
+ *  0b1..Transaction stopped at block gap
+ *  0b0..No block gap event
+ */
+#define USDHC_INT_STATUS_BGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
+#define USDHC_INT_STATUS_DINT_MASK               (0x8U)
+#define USDHC_INT_STATUS_DINT_SHIFT              (3U)
+/*! DINT - DMA Interrupt
+ *  0b1..DMA Interrupt is generated
+ *  0b0..No DMA Interrupt
+ */
+#define USDHC_INT_STATUS_DINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
+#define USDHC_INT_STATUS_BWR_MASK                (0x10U)
+#define USDHC_INT_STATUS_BWR_SHIFT               (4U)
+/*! BWR - Buffer Write Ready
+ *  0b1..Ready to write buffer:
+ *  0b0..Not ready to write buffer
+ */
+#define USDHC_INT_STATUS_BWR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
+#define USDHC_INT_STATUS_BRR_MASK                (0x20U)
+#define USDHC_INT_STATUS_BRR_SHIFT               (5U)
+/*! BRR - Buffer Read Ready
+ *  0b1..Ready to read buffer
+ *  0b0..Not ready to read buffer
+ */
+#define USDHC_INT_STATUS_BRR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
+#define USDHC_INT_STATUS_CINS_MASK               (0x40U)
+#define USDHC_INT_STATUS_CINS_SHIFT              (6U)
+/*! CINS - Card Insertion
+ *  0b1..Card inserted
+ *  0b0..Card state unstable or removed
+ */
+#define USDHC_INT_STATUS_CINS(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
+#define USDHC_INT_STATUS_CRM_MASK                (0x80U)
+#define USDHC_INT_STATUS_CRM_SHIFT               (7U)
+/*! CRM - Card Removal
+ *  0b1..Card removed
+ *  0b0..Card state unstable or inserted
+ */
+#define USDHC_INT_STATUS_CRM(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
+#define USDHC_INT_STATUS_CINT_MASK               (0x100U)
+#define USDHC_INT_STATUS_CINT_SHIFT              (8U)
+/*! CINT - Card Interrupt
+ *  0b1..Generate Card Interrupt
+ *  0b0..No Card Interrupt
+ */
+#define USDHC_INT_STATUS_CINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
+#define USDHC_INT_STATUS_CTOE_MASK               (0x10000U)
+#define USDHC_INT_STATUS_CTOE_SHIFT              (16U)
+/*! CTOE - Command Timeout Error
+ *  0b1..Time out
+ *  0b0..No Error
+ */
+#define USDHC_INT_STATUS_CTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
+#define USDHC_INT_STATUS_CCE_MASK                (0x20000U)
+#define USDHC_INT_STATUS_CCE_SHIFT               (17U)
+/*! CCE - Command CRC Error
+ *  0b1..CRC Error Generated.
+ *  0b0..No Error
+ */
+#define USDHC_INT_STATUS_CCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
+#define USDHC_INT_STATUS_CEBE_MASK               (0x40000U)
+#define USDHC_INT_STATUS_CEBE_SHIFT              (18U)
+/*! CEBE - Command End Bit Error
+ *  0b1..End Bit Error Generated
+ *  0b0..No Error
+ */
+#define USDHC_INT_STATUS_CEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
+#define USDHC_INT_STATUS_CIE_MASK                (0x80000U)
+#define USDHC_INT_STATUS_CIE_SHIFT               (19U)
+/*! CIE - Command Index Error
+ *  0b1..Error
+ *  0b0..No Error
+ */
+#define USDHC_INT_STATUS_CIE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
+#define USDHC_INT_STATUS_DTOE_MASK               (0x100000U)
+#define USDHC_INT_STATUS_DTOE_SHIFT              (20U)
+/*! DTOE - Data Timeout Error
+ *  0b1..Time out
+ *  0b0..No Error
+ */
+#define USDHC_INT_STATUS_DTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
+#define USDHC_INT_STATUS_DCE_MASK                (0x200000U)
+#define USDHC_INT_STATUS_DCE_SHIFT               (21U)
+/*! DCE - Data CRC Error
+ *  0b1..Error
+ *  0b0..No Error
+ */
+#define USDHC_INT_STATUS_DCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
+#define USDHC_INT_STATUS_DEBE_MASK               (0x400000U)
+#define USDHC_INT_STATUS_DEBE_SHIFT              (22U)
+/*! DEBE - Data End Bit Error
+ *  0b1..Error
+ *  0b0..No Error
+ */
+#define USDHC_INT_STATUS_DEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
+#define USDHC_INT_STATUS_AC12E_MASK              (0x1000000U)
+#define USDHC_INT_STATUS_AC12E_SHIFT             (24U)
+/*! AC12E - Auto CMD12 Error
+ *  0b1..Error
+ *  0b0..No Error
+ */
+#define USDHC_INT_STATUS_AC12E(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
+#define USDHC_INT_STATUS_DMAE_MASK               (0x10000000U)
+#define USDHC_INT_STATUS_DMAE_SHIFT              (28U)
+/*! DMAE - DMA Error
+ *  0b1..Error
+ *  0b0..No Error
+ */
+#define USDHC_INT_STATUS_DMAE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
+/*! @} */
+
+/*! @name INT_STATUS_EN - Interrupt Status Enable */
+/*! @{ */
+#define USDHC_INT_STATUS_EN_CCSEN_MASK           (0x1U)
+#define USDHC_INT_STATUS_EN_CCSEN_SHIFT          (0U)
+/*! CCSEN - Command Complete Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
+#define USDHC_INT_STATUS_EN_TCSEN_MASK           (0x2U)
+#define USDHC_INT_STATUS_EN_TCSEN_SHIFT          (1U)
+/*! TCSEN - Transfer Complete Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_TCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
+#define USDHC_INT_STATUS_EN_BGESEN_MASK          (0x4U)
+#define USDHC_INT_STATUS_EN_BGESEN_SHIFT         (2U)
+/*! BGESEN - Block Gap Event Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_BGESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
+#define USDHC_INT_STATUS_EN_DINTSEN_MASK         (0x8U)
+#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT        (3U)
+/*! DINTSEN - DMA Interrupt Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_DINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
+#define USDHC_INT_STATUS_EN_BWRSEN_MASK          (0x10U)
+#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT         (4U)
+/*! BWRSEN - Buffer Write Ready Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_BWRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
+#define USDHC_INT_STATUS_EN_BRRSEN_MASK          (0x20U)
+#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT         (5U)
+/*! BRRSEN - Buffer Read Ready Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_BRRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
+#define USDHC_INT_STATUS_EN_CINSSEN_MASK         (0x40U)
+#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT        (6U)
+/*! CINSSEN - Card Insertion Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CINSSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
+#define USDHC_INT_STATUS_EN_CRMSEN_MASK          (0x80U)
+#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT         (7U)
+/*! CRMSEN - Card Removal Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CRMSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
+#define USDHC_INT_STATUS_EN_CINTSEN_MASK         (0x100U)
+#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT        (8U)
+/*! CINTSEN - Card Interrupt Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
+#define USDHC_INT_STATUS_EN_CTOESEN_MASK         (0x10000U)
+#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT        (16U)
+/*! CTOESEN - Command Timeout Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
+#define USDHC_INT_STATUS_EN_CCESEN_MASK          (0x20000U)
+#define USDHC_INT_STATUS_EN_CCESEN_SHIFT         (17U)
+/*! CCESEN - Command CRC Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
+#define USDHC_INT_STATUS_EN_CEBESEN_MASK         (0x40000U)
+#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT        (18U)
+/*! CEBESEN - Command End Bit Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
+#define USDHC_INT_STATUS_EN_CIESEN_MASK          (0x80000U)
+#define USDHC_INT_STATUS_EN_CIESEN_SHIFT         (19U)
+/*! CIESEN - Command Index Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_CIESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
+#define USDHC_INT_STATUS_EN_DTOESEN_MASK         (0x100000U)
+#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT        (20U)
+/*! DTOESEN - Data Timeout Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_DTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
+#define USDHC_INT_STATUS_EN_DCESEN_MASK          (0x200000U)
+#define USDHC_INT_STATUS_EN_DCESEN_SHIFT         (21U)
+/*! DCESEN - Data CRC Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_DCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
+#define USDHC_INT_STATUS_EN_DEBESEN_MASK         (0x400000U)
+#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT        (22U)
+/*! DEBESEN - Data End Bit Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_DEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
+#define USDHC_INT_STATUS_EN_AC12ESEN_MASK        (0x1000000U)
+#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT       (24U)
+/*! AC12ESEN - Auto CMD12 Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_AC12ESEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
+#define USDHC_INT_STATUS_EN_DMAESEN_MASK         (0x10000000U)
+#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT        (28U)
+/*! DMAESEN - DMA Error Status Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_STATUS_EN_DMAESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
+/*! @} */
+
+/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */
+/*! @{ */
+#define USDHC_INT_SIGNAL_EN_CCIEN_MASK           (0x1U)
+#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT          (0U)
+/*! CCIEN - Command Complete Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_TCIEN_MASK           (0x2U)
+#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT          (1U)
+/*! TCIEN - Transfer Complete Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_TCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK          (0x4U)
+#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT         (2U)
+/*! BGEIEN - Block Gap Event Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_BGEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK         (0x8U)
+#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT        (3U)
+/*! DINTIEN - DMA Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_DINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK          (0x10U)
+#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT         (4U)
+/*! BWRIEN - Buffer Write Ready Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_BWRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK          (0x20U)
+#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT         (5U)
+/*! BRRIEN - Buffer Read Ready Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_BRRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK         (0x40U)
+#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT        (6U)
+/*! CINSIEN - Card Insertion Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CINSIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK          (0x80U)
+#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT         (7U)
+/*! CRMIEN - Card Removal Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CRMIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK         (0x100U)
+#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT        (8U)
+/*! CINTIEN - Card Interrupt Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK         (0x10000U)
+#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT        (16U)
+/*! CTOEIEN - Command Timeout Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK          (0x20000U)
+#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT         (17U)
+/*! CCEIEN - Command CRC Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK         (0x40000U)
+#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT        (18U)
+/*! CEBEIEN - Command End Bit Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK          (0x80000U)
+#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT         (19U)
+/*! CIEIEN - Command Index Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_CIEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK         (0x100000U)
+#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT        (20U)
+/*! DTOEIEN - Data Timeout Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_DTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK          (0x200000U)
+#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT         (21U)
+/*! DCEIEN - Data CRC Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_DCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK         (0x400000U)
+#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT        (22U)
+/*! DEBEIEN - Data End Bit Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_DEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK        (0x1000000U)
+#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT       (24U)
+/*! AC12EIEN - Auto CMD12 Error Interrupt Enable
+ *  0b1..Enabled
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_AC12EIEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
+#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK         (0x10000000U)
+#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT        (28U)
+/*! DMAEIEN - DMA Error Interrupt Enable
+ *  0b1..Enable
+ *  0b0..Masked
+ */
+#define USDHC_INT_SIGNAL_EN_DMAEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
+/*! @} */
+
+/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */
+/*! @{ */
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK   (0x1U)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT  (0U)
+/*! AC12NE - Auto CMD12 Not Executed
+ *  0b1..Not executed
+ *  0b0..Executed
+ */
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK  (0x2U)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
+/*! AC12TOE - Auto CMD12 / 23 Timeout Error
+ *  0b1..Time out
+ *  0b0..No error
+ */
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK  (0x4U)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
+/*! AC12EBE - Auto CMD12 / 23 End Bit Error
+ *  0b1..End Bit Error Generated
+ *  0b0..No error
+ */
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK   (0x8U)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT  (3U)
+/*! AC12CE - Auto CMD12 / 23 CRC Error
+ *  0b1..CRC Error Met in Auto CMD12/23 Response
+ *  0b0..No CRC error
+ */
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK   (0x10U)
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT  (4U)
+/*! AC12IE - Auto CMD12 / 23 Index Error
+ *  0b1..Error, the CMD index in response is not CMD12/23
+ *  0b0..No error
+ */
+#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
+#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
+#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
+/*! CNIBAC12E - Command Not Issued By Auto CMD12 Error
+ *  0b1..Not Issued
+ *  0b0..No error
+ */
+#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
+/*! @} */
+
+/*! @name HOST_CTRL_CAP - Host Controller Capabilities */
+/*! @{ */
+#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK   (0x4U)
+#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT  (2U)
+#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
+#define USDHC_HOST_CTRL_CAP_MBL_MASK             (0x70000U)
+#define USDHC_HOST_CTRL_CAP_MBL_SHIFT            (16U)
+/*! MBL - Max Block Length
+ *  0b000..512 bytes
+ *  0b001..1024 bytes
+ *  0b010..2048 bytes
+ *  0b011..4096 bytes
+ */
+#define USDHC_HOST_CTRL_CAP_MBL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
+#define USDHC_HOST_CTRL_CAP_ADMAS_MASK           (0x100000U)
+#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT          (20U)
+/*! ADMAS - ADMA Support
+ *  0b1..Advanced DMA Supported
+ *  0b0..Advanced DMA Not supported
+ */
+#define USDHC_HOST_CTRL_CAP_ADMAS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
+#define USDHC_HOST_CTRL_CAP_HSS_MASK             (0x200000U)
+#define USDHC_HOST_CTRL_CAP_HSS_SHIFT            (21U)
+/*! HSS - High Speed Support
+ *  0b1..High Speed Supported
+ *  0b0..High Speed Not Supported
+ */
+#define USDHC_HOST_CTRL_CAP_HSS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
+#define USDHC_HOST_CTRL_CAP_DMAS_MASK            (0x400000U)
+#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT           (22U)
+/*! DMAS - DMA Support
+ *  0b1..DMA Supported
+ *  0b0..DMA not supported
+ */
+#define USDHC_HOST_CTRL_CAP_DMAS(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
+#define USDHC_HOST_CTRL_CAP_SRS_MASK             (0x800000U)
+#define USDHC_HOST_CTRL_CAP_SRS_SHIFT            (23U)
+/*! SRS - Suspend / Resume Support
+ *  0b1..Supported
+ *  0b0..Not supported
+ */
+#define USDHC_HOST_CTRL_CAP_SRS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
+#define USDHC_HOST_CTRL_CAP_VS33_MASK            (0x1000000U)
+#define USDHC_HOST_CTRL_CAP_VS33_SHIFT           (24U)
+/*! VS33 - Voltage Support 3.3V
+ *  0b1..3.3V supported
+ *  0b0..3.3V not supported
+ */
+#define USDHC_HOST_CTRL_CAP_VS33(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
+#define USDHC_HOST_CTRL_CAP_VS30_MASK            (0x2000000U)
+#define USDHC_HOST_CTRL_CAP_VS30_SHIFT           (25U)
+/*! VS30 - Voltage Support 3.0 V
+ *  0b1..3.0V supported
+ *  0b0..3.0V not supported
+ */
+#define USDHC_HOST_CTRL_CAP_VS30(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
+#define USDHC_HOST_CTRL_CAP_VS18_MASK            (0x4000000U)
+#define USDHC_HOST_CTRL_CAP_VS18_SHIFT           (26U)
+/*! VS18 - Voltage Support 1.8 V
+ *  0b1..1.8V supported
+ *  0b0..1.8V not supported
+ */
+#define USDHC_HOST_CTRL_CAP_VS18(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
+/*! @} */
+
+/*! @name WTMK_LVL - Watermark Level */
+/*! @{ */
+#define USDHC_WTMK_LVL_RD_WML_MASK               (0xFFU)
+#define USDHC_WTMK_LVL_RD_WML_SHIFT              (0U)
+#define USDHC_WTMK_LVL_RD_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
+#define USDHC_WTMK_LVL_RD_BRST_LEN_MASK          (0x1F00U)
+#define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT         (8U)
+#define USDHC_WTMK_LVL_RD_BRST_LEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)
+#define USDHC_WTMK_LVL_WR_WML_MASK               (0xFF0000U)
+#define USDHC_WTMK_LVL_WR_WML_SHIFT              (16U)
+#define USDHC_WTMK_LVL_WR_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
+#define USDHC_WTMK_LVL_WR_BRST_LEN_MASK          (0x1F000000U)
+#define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT         (24U)
+#define USDHC_WTMK_LVL_WR_BRST_LEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)
+/*! @} */
+
+/*! @name MIX_CTRL - Mixer Control */
+/*! @{ */
+#define USDHC_MIX_CTRL_DMAEN_MASK                (0x1U)
+#define USDHC_MIX_CTRL_DMAEN_SHIFT               (0U)
+/*! DMAEN - DMA Enable
+ *  0b1..Enable
+ *  0b0..Disable
+ */
+#define USDHC_MIX_CTRL_DMAEN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
+#define USDHC_MIX_CTRL_BCEN_MASK                 (0x2U)
+#define USDHC_MIX_CTRL_BCEN_SHIFT                (1U)
+/*! BCEN - Block Count Enable
+ *  0b1..Enable
+ *  0b0..Disable
+ */
+#define USDHC_MIX_CTRL_BCEN(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
+#define USDHC_MIX_CTRL_AC12EN_MASK               (0x4U)
+#define USDHC_MIX_CTRL_AC12EN_SHIFT              (2U)
+/*! AC12EN - Auto CMD12 Enable
+ *  0b1..Enable
+ *  0b0..Disable
+ */
+#define USDHC_MIX_CTRL_AC12EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
+#define USDHC_MIX_CTRL_DDR_EN_MASK               (0x8U)
+#define USDHC_MIX_CTRL_DDR_EN_SHIFT              (3U)
+#define USDHC_MIX_CTRL_DDR_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
+#define USDHC_MIX_CTRL_DTDSEL_MASK               (0x10U)
+#define USDHC_MIX_CTRL_DTDSEL_SHIFT              (4U)
+/*! DTDSEL - Data Transfer Direction Select
+ *  0b1..Read (Card to Host)
+ *  0b0..Write (Host to Card)
+ */
+#define USDHC_MIX_CTRL_DTDSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
+#define USDHC_MIX_CTRL_MSBSEL_MASK               (0x20U)
+#define USDHC_MIX_CTRL_MSBSEL_SHIFT              (5U)
+/*! MSBSEL - Multi / Single Block Select
+ *  0b1..Multiple Blocks
+ *  0b0..Single Block
+ */
+#define USDHC_MIX_CTRL_MSBSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
+#define USDHC_MIX_CTRL_NIBBLE_POS_MASK           (0x40U)
+#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT          (6U)
+#define USDHC_MIX_CTRL_NIBBLE_POS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
+#define USDHC_MIX_CTRL_AC23EN_MASK               (0x80U)
+#define USDHC_MIX_CTRL_AC23EN_SHIFT              (7U)
+#define USDHC_MIX_CTRL_AC23EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
+/*! @} */
+
+/*! @name FORCE_EVENT - Force Event */
+/*! @{ */
+#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK        (0x1U)
+#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT       (0U)
+#define USDHC_FORCE_EVENT_FEVTAC12NE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
+#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK       (0x2U)
+#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT      (1U)
+#define USDHC_FORCE_EVENT_FEVTAC12TOE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
+#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK        (0x4U)
+#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT       (2U)
+#define USDHC_FORCE_EVENT_FEVTAC12CE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
+#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK       (0x8U)
+#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT      (3U)
+#define USDHC_FORCE_EVENT_FEVTAC12EBE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
+#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK        (0x10U)
+#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT       (4U)
+#define USDHC_FORCE_EVENT_FEVTAC12IE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
+#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK     (0x80U)
+#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT    (7U)
+#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
+#define USDHC_FORCE_EVENT_FEVTCTOE_MASK          (0x10000U)
+#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT         (16U)
+#define USDHC_FORCE_EVENT_FEVTCTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
+#define USDHC_FORCE_EVENT_FEVTCCE_MASK           (0x20000U)
+#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT          (17U)
+#define USDHC_FORCE_EVENT_FEVTCCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
+#define USDHC_FORCE_EVENT_FEVTCEBE_MASK          (0x40000U)
+#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT         (18U)
+#define USDHC_FORCE_EVENT_FEVTCEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
+#define USDHC_FORCE_EVENT_FEVTCIE_MASK           (0x80000U)
+#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT          (19U)
+#define USDHC_FORCE_EVENT_FEVTCIE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
+#define USDHC_FORCE_EVENT_FEVTDTOE_MASK          (0x100000U)
+#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT         (20U)
+#define USDHC_FORCE_EVENT_FEVTDTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
+#define USDHC_FORCE_EVENT_FEVTDCE_MASK           (0x200000U)
+#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT          (21U)
+#define USDHC_FORCE_EVENT_FEVTDCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
+#define USDHC_FORCE_EVENT_FEVTDEBE_MASK          (0x400000U)
+#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT         (22U)
+#define USDHC_FORCE_EVENT_FEVTDEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
+#define USDHC_FORCE_EVENT_FEVTAC12E_MASK         (0x1000000U)
+#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT        (24U)
+#define USDHC_FORCE_EVENT_FEVTAC12E(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
+#define USDHC_FORCE_EVENT_FEVTDMAE_MASK          (0x10000000U)
+#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT         (28U)
+#define USDHC_FORCE_EVENT_FEVTDMAE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
+#define USDHC_FORCE_EVENT_FEVTCINT_MASK          (0x80000000U)
+#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT         (31U)
+#define USDHC_FORCE_EVENT_FEVTCINT(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
+/*! @} */
+
+/*! @name ADMA_ERR_STATUS - ADMA Error Status Register */
+/*! @{ */
+#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK        (0x3U)
+#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT       (0U)
+#define USDHC_ADMA_ERR_STATUS_ADMAES(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
+#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK       (0x4U)
+#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT      (2U)
+/*! ADMALME - ADMA Length Mismatch Error
+ *  0b1..Error
+ *  0b0..No Error
+ */
+#define USDHC_ADMA_ERR_STATUS_ADMALME(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
+#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK       (0x8U)
+#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT      (3U)
+/*! ADMADCE - ADMA Descriptor Error
+ *  0b1..Error
+ *  0b0..No Error
+ */
+#define USDHC_ADMA_ERR_STATUS_ADMADCE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
+/*! @} */
+
+/*! @name ADMA_SYS_ADDR - ADMA System Address */
+/*! @{ */
+#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK        (0xFFFFFFFCU)
+#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT       (2U)
+#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
+/*! @} */
+
+/*! @name VEND_SPEC - Vendor Specific Register */
+/*! @{ */
+#define USDHC_VEND_SPEC_VSELECT_MASK             (0x2U)
+#define USDHC_VEND_SPEC_VSELECT_SHIFT            (1U)
+/*! VSELECT - Voltage Selection
+ *  0b1..Change the voltage to low voltage range, around 1.8 V
+ *  0b0..Change the voltage to high voltage range, around 3.0 V
+ */
+#define USDHC_VEND_SPEC_VSELECT(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
+#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK     (0x4U)
+#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT    (2U)
+/*! CONFLICT_CHK_EN - Conflict check enable.
+ *  0b0..Conflict check disable
+ *  0b1..Conflict check enable
+ */
+#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
+#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK  (0x8U)
+#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
+/*! AC12_WR_CHKBUSY_EN - AC12_WR_CHKBUSY_EN
+ *  0b0..Do not check busy after auto CMD12 for write data packet
+ *  0b1..Check busy after auto CMD12 for write data packet
+ */
+#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
+#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK        (0x100U)
+#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT       (8U)
+/*! FRC_SDCLK_ON - FRC_SDCLK_ON
+ *  0b0..CLK active or inactive is fully controlled by the hardware.
+ *  0b1..Force CLK active.
+ */
+#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
+#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK         (0x8000U)
+#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT        (15U)
+/*! CRC_CHK_DIS - CRC Check Disable
+ *  0b0..Check CRC16 for every read data packet and check CRC bits for every write data packet
+ *  0b1..Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet
+ */
+#define USDHC_VEND_SPEC_CRC_CHK_DIS(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
+#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK         (0x80000000U)
+#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT        (31U)
+/*! CMD_BYTE_EN - CMD_BYTE_EN
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define USDHC_VEND_SPEC_CMD_BYTE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
+/*! @} */
+
+/*! @name MMC_BOOT - MMC Boot Register */
+/*! @{ */
+#define USDHC_MMC_BOOT_DTOCV_ACK_MASK            (0xFU)
+#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT           (0U)
+/*! DTOCV_ACK - DTOCV_ACK
+ *  0b0000..SDCLK x 2^14
+ *  0b0001..SDCLK x 2^15
+ *  0b0010..SDCLK x 2^16
+ *  0b0011..SDCLK x 2^17
+ *  0b0100..SDCLK x 2^18
+ *  0b0101..SDCLK x 2^19
+ *  0b0110..SDCLK x 2^20
+ *  0b0111..SDCLK x 2^21
+ *  0b1110..SDCLK x 2^28
+ *  0b1111..SDCLK x 2^29
+ */
+#define USDHC_MMC_BOOT_DTOCV_ACK(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
+#define USDHC_MMC_BOOT_BOOT_ACK_MASK             (0x10U)
+#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT            (4U)
+/*! BOOT_ACK - BOOT_ACK
+ *  0b0..No ack
+ *  0b1..Ack
+ */
+#define USDHC_MMC_BOOT_BOOT_ACK(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
+#define USDHC_MMC_BOOT_BOOT_MODE_MASK            (0x20U)
+#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT           (5U)
+/*! BOOT_MODE - BOOT_MODE
+ *  0b0..Normal boot
+ *  0b1..Alternative boot
+ */
+#define USDHC_MMC_BOOT_BOOT_MODE(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
+#define USDHC_MMC_BOOT_BOOT_EN_MASK              (0x40U)
+#define USDHC_MMC_BOOT_BOOT_EN_SHIFT             (6U)
+/*! BOOT_EN - BOOT_EN
+ *  0b0..Fast boot disable
+ *  0b1..Fast boot enable
+ */
+#define USDHC_MMC_BOOT_BOOT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
+#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK         (0x80U)
+#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT        (7U)
+#define USDHC_MMC_BOOT_AUTO_SABG_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
+#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK     (0x100U)
+#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT    (8U)
+/*! DISABLE_TIME_OUT - Disable Time Out
+ *  0b0..Enable time out
+ *  0b1..Disable time out
+ */
+#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
+#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK         (0xFFFF0000U)
+#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT        (16U)
+#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
+/*! @} */
+
+/*! @name VEND_SPEC2 - Vendor Specific 2 Register */
+/*! @{ */
+#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK   (0x8U)
+#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT  (3U)
+/*! CARD_INT_D3_TEST - Card Interrupt Detection Test
+ *  0b0..Check the card interrupt only when DATA3 is high.
+ *  0b1..Check the card interrupt by ignoring the status of DATA3.
+ */
+#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
+#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK    (0x1000U)
+#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT   (12U)
+/*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23
+ *  0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enable.
+ *  0b0..Disable
+ */
+#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
+#define USDHC_VEND_SPEC2_AHB_RST_MASK            (0x4000U)
+#define USDHC_VEND_SPEC2_AHB_RST_SHIFT           (14U)
+#define USDHC_VEND_SPEC2_AHB_RST(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_AHB_RST_SHIFT)) & USDHC_VEND_SPEC2_AHB_RST_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USDHC_Register_Masks */
+
+
+/* USDHC - Peripheral instance base addresses */
+/** Peripheral USDHC0 base address */
+#define USDHC0_BASE                              (0x4003E000u)
+/** Peripheral USDHC0 base pointer */
+#define USDHC0                                   ((USDHC_Type *)USDHC0_BASE)
+/** Array initializer of USDHC peripheral base addresses */
+#define USDHC_BASE_ADDRS                         { USDHC0_BASE }
+/** Array initializer of USDHC peripheral base pointers */
+#define USDHC_BASE_PTRS                          { USDHC0 }
+/** Interrupt vectors for the USDHC peripheral type */
+#define USDHC_IRQS                               { USDHC0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USDHC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- VREF Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t TRM;                                /**< VREF Trim Register, offset: 0x0 */
+  __IO uint8_t SC;                                 /**< VREF Status and Control Register, offset: 0x1 */
+       uint8_t RESERVED_0[3];
+  __IO uint8_t TRM4;                               /**< VREF Trim 2.1V Register, offset: 0x5 */
+} VREF_Type;
+
+/* ----------------------------------------------------------------------------
+   -- VREF Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/*! @name TRM - VREF Trim Register */
+/*! @{ */
+#define VREF_TRM_TRIM_MASK                       (0x3FU)
+#define VREF_TRM_TRIM_SHIFT                      (0U)
+/*! TRIM - Trim bits
+ *  0b000000..Min
+ *  0b111111..Max
+ */
+#define VREF_TRM_TRIM(x)                         (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK                     (0x40U)
+#define VREF_TRM_CHOPEN_SHIFT                    (6U)
+/*! CHOPEN - Chop oscillator enable. When set, the internal chopping operation is enabled and the internal analog offset will be minimized.
+ *  0b0..Chop oscillator is disabled.
+ *  0b1..Chop oscillator is enabled.
+ */
+#define VREF_TRM_CHOPEN(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
+/*! @} */
+
+/*! @name SC - VREF Status and Control Register */
+/*! @{ */
+#define VREF_SC_MODE_LV_MASK                     (0x3U)
+#define VREF_SC_MODE_LV_SHIFT                    (0U)
+/*! MODE_LV - Buffer Mode selection
+ *  0b00..Bandgap on only, for stabilization and startup
+ *  0b01..High power buffer mode enabled
+ *  0b10..Low-power buffer mode enabled
+ *  0b11..Reserved
+ */
+#define VREF_SC_MODE_LV(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK                      (0x4U)
+#define VREF_SC_VREFST_SHIFT                     (2U)
+/*! VREFST - Internal Voltage Reference stable
+ *  0b0..The module is disabled or not stable.
+ *  0b1..The module is stable.
+ */
+#define VREF_SC_VREFST(x)                        (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
+#define VREF_SC_ICOMPEN_MASK                     (0x20U)
+#define VREF_SC_ICOMPEN_SHIFT                    (5U)
+/*! ICOMPEN - Second order curvature compensation enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define VREF_SC_ICOMPEN(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
+#define VREF_SC_REGEN_MASK                       (0x40U)
+#define VREF_SC_REGEN_SHIFT                      (6U)
+/*! REGEN - Regulator enable
+ *  0b0..Internal 1.75 V regulator is disabled.
+ *  0b1..Internal 1.75 V regulator is enabled.
+ */
+#define VREF_SC_REGEN(x)                         (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
+#define VREF_SC_VREFEN_MASK                      (0x80U)
+#define VREF_SC_VREFEN_SHIFT                     (7U)
+/*! VREFEN - Internal Voltage Reference enable
+ *  0b0..The module is disabled.
+ *  0b1..The module is enabled.
+ */
+#define VREF_SC_VREFEN(x)                        (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
+/*! @} */
+
+/*! @name TRM4 - VREF Trim 2.1V Register */
+/*! @{ */
+#define VREF_TRM4_TRIM2V1_MASK                   (0x3FU)
+#define VREF_TRM4_TRIM2V1_SHIFT                  (0U)
+/*! TRIM2V1 - VREF 2.1V Trim Bits
+ *  0b000000..Max
+ *  0b111111..Min
+ */
+#define VREF_TRM4_TRIM2V1(x)                     (((uint8_t)(((uint8_t)(x)) << VREF_TRM4_TRIM2V1_SHIFT)) & VREF_TRM4_TRIM2V1_MASK)
+#define VREF_TRM4_VREF2V1_EN_MASK                (0x80U)
+#define VREF_TRM4_VREF2V1_EN_SHIFT               (7U)
+/*! VREF2V1_EN - Internal Voltage Reference (2.1V) Enable
+ *  0b0..VREF 2.1V is enabled
+ *  0b1..VREF 2.1V is disabled
+ */
+#define VREF_TRM4_VREF2V1_EN(x)                  (((uint8_t)(((uint8_t)(x)) << VREF_TRM4_VREF2V1_EN_SHIFT)) & VREF_TRM4_VREF2V1_EN_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE                                (0x4004D000u)
+/** Peripheral VREF base pointer */
+#define VREF                                     ((VREF_Type *)VREF_BASE)
+/** Array initializer of VREF peripheral base addresses */
+#define VREF_BASE_ADDRS                          { VREF_BASE }
+/** Array initializer of VREF peripheral base pointers */
+#define VREF_BASE_PTRS                           { VREF }
+
+/*!
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CS;                                /**< Watchdog Control and Status Register, offset: 0x0 */
+  __IO uint32_t CNT;                               /**< Watchdog Counter Register, offset: 0x4 */
+  __IO uint32_t TOVAL;                             /**< Watchdog Timeout Value Register, offset: 0x8 */
+  __IO uint32_t WIN;                               /**< Watchdog Window Register, offset: 0xC */
+} WDOG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/*! @name CS - Watchdog Control and Status Register */
+/*! @{ */
+#define WDOG_CS_STOP_MASK                        (0x1U)
+#define WDOG_CS_STOP_SHIFT                       (0U)
+/*! STOP - Stop Enable
+ *  0b0..Watchdog disabled in chip stop mode.
+ *  0b1..Watchdog enabled in chip stop mode.
+ */
+#define WDOG_CS_STOP(x)                          (((uint32_t)(((uint32_t)(x)) << WDOG_CS_STOP_SHIFT)) & WDOG_CS_STOP_MASK)
+#define WDOG_CS_WAIT_MASK                        (0x2U)
+#define WDOG_CS_WAIT_SHIFT                       (1U)
+/*! WAIT - Wait Enable
+ *  0b0..Watchdog disabled in chip wait mode.
+ *  0b1..Watchdog enabled in chip wait mode.
+ */
+#define WDOG_CS_WAIT(x)                          (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WAIT_SHIFT)) & WDOG_CS_WAIT_MASK)
+#define WDOG_CS_DBG_MASK                         (0x4U)
+#define WDOG_CS_DBG_SHIFT                        (2U)
+/*! DBG - Debug Enable
+ *  0b0..Watchdog disabled in chip debug mode.
+ *  0b1..Watchdog enabled in chip debug mode.
+ */
+#define WDOG_CS_DBG(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_DBG_SHIFT)) & WDOG_CS_DBG_MASK)
+#define WDOG_CS_TST_MASK                         (0x18U)
+#define WDOG_CS_TST_SHIFT                        (3U)
+/*! TST - Watchdog Test
+ *  0b00..Watchdog test mode disabled.
+ *  0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode.
+ *  0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW].
+ *  0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].
+ */
+#define WDOG_CS_TST(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_TST_SHIFT)) & WDOG_CS_TST_MASK)
+#define WDOG_CS_UPDATE_MASK                      (0x20U)
+#define WDOG_CS_UPDATE_SHIFT                     (5U)
+/*! UPDATE - Allow updates
+ *  0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset.
+ *  0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence.
+ */
+#define WDOG_CS_UPDATE(x)                        (((uint32_t)(((uint32_t)(x)) << WDOG_CS_UPDATE_SHIFT)) & WDOG_CS_UPDATE_MASK)
+#define WDOG_CS_INT_MASK                         (0x40U)
+#define WDOG_CS_INT_SHIFT                        (6U)
+/*! INT - Watchdog Interrupt
+ *  0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed.
+ *  0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch.
+ */
+#define WDOG_CS_INT(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_INT_SHIFT)) & WDOG_CS_INT_MASK)
+#define WDOG_CS_EN_MASK                          (0x80U)
+#define WDOG_CS_EN_SHIFT                         (7U)
+/*! EN - Watchdog Enable
+ *  0b0..Watchdog disabled.
+ *  0b1..Watchdog enabled.
+ */
+#define WDOG_CS_EN(x)                            (((uint32_t)(((uint32_t)(x)) << WDOG_CS_EN_SHIFT)) & WDOG_CS_EN_MASK)
+#define WDOG_CS_CLK_MASK                         (0x300U)
+#define WDOG_CS_CLK_SHIFT                        (8U)
+/*! CLK - Watchdog Clock
+ *  0b00..Bus clock
+ *  0b01..LPO clock
+ *  0b10..INTCLK (internal clock)
+ *  0b11..ERCLK (external reference clock)
+ */
+#define WDOG_CS_CLK(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CLK_SHIFT)) & WDOG_CS_CLK_MASK)
+#define WDOG_CS_RCS_MASK                         (0x400U)
+#define WDOG_CS_RCS_SHIFT                        (10U)
+/*! RCS - Reconfiguration Success
+ *  0b0..Reconfiguring WDOG.
+ *  0b1..Reconfiguration is successful.
+ */
+#define WDOG_CS_RCS(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_RCS_SHIFT)) & WDOG_CS_RCS_MASK)
+#define WDOG_CS_ULK_MASK                         (0x800U)
+#define WDOG_CS_ULK_SHIFT                        (11U)
+/*! ULK - Unlock status
+ *  0b0..WDOG is locked.
+ *  0b1..WDOG is unlocked.
+ */
+#define WDOG_CS_ULK(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_ULK_SHIFT)) & WDOG_CS_ULK_MASK)
+#define WDOG_CS_PRES_MASK                        (0x1000U)
+#define WDOG_CS_PRES_SHIFT                       (12U)
+/*! PRES - Watchdog prescaler
+ *  0b0..256 prescaler disabled.
+ *  0b1..256 prescaler enabled.
+ */
+#define WDOG_CS_PRES(x)                          (((uint32_t)(((uint32_t)(x)) << WDOG_CS_PRES_SHIFT)) & WDOG_CS_PRES_MASK)
+#define WDOG_CS_CMD32EN_MASK                     (0x2000U)
+#define WDOG_CS_CMD32EN_SHIFT                    (13U)
+/*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words
+ *  0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported.
+ *  0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported.
+ */
+#define WDOG_CS_CMD32EN(x)                       (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CMD32EN_SHIFT)) & WDOG_CS_CMD32EN_MASK)
+#define WDOG_CS_FLG_MASK                         (0x4000U)
+#define WDOG_CS_FLG_SHIFT                        (14U)
+/*! FLG - Watchdog Interrupt Flag
+ *  0b0..No interrupt occurred.
+ *  0b1..An interrupt occurred.
+ */
+#define WDOG_CS_FLG(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_FLG_SHIFT)) & WDOG_CS_FLG_MASK)
+#define WDOG_CS_WIN_MASK                         (0x8000U)
+#define WDOG_CS_WIN_SHIFT                        (15U)
+/*! WIN - Watchdog Window
+ *  0b0..Window mode disabled.
+ *  0b1..Window mode enabled.
+ */
+#define WDOG_CS_WIN(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WIN_SHIFT)) & WDOG_CS_WIN_MASK)
+/*! @} */
+
+/*! @name CNT - Watchdog Counter Register */
+/*! @{ */
+#define WDOG_CNT_CNTLOW_MASK                     (0xFFU)
+#define WDOG_CNT_CNTLOW_SHIFT                    (0U)
+#define WDOG_CNT_CNTLOW(x)                       (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTLOW_SHIFT)) & WDOG_CNT_CNTLOW_MASK)
+#define WDOG_CNT_CNTHIGH_MASK                    (0xFF00U)
+#define WDOG_CNT_CNTHIGH_SHIFT                   (8U)
+#define WDOG_CNT_CNTHIGH(x)                      (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTHIGH_SHIFT)) & WDOG_CNT_CNTHIGH_MASK)
+/*! @} */
+
+/*! @name TOVAL - Watchdog Timeout Value Register */
+/*! @{ */
+#define WDOG_TOVAL_TOVALLOW_MASK                 (0xFFU)
+#define WDOG_TOVAL_TOVALLOW_SHIFT                (0U)
+#define WDOG_TOVAL_TOVALLOW(x)                   (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALLOW_SHIFT)) & WDOG_TOVAL_TOVALLOW_MASK)
+#define WDOG_TOVAL_TOVALHIGH_MASK                (0xFF00U)
+#define WDOG_TOVAL_TOVALHIGH_SHIFT               (8U)
+#define WDOG_TOVAL_TOVALHIGH(x)                  (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALHIGH_SHIFT)) & WDOG_TOVAL_TOVALHIGH_MASK)
+/*! @} */
+
+/*! @name WIN - Watchdog Window Register */
+/*! @{ */
+#define WDOG_WIN_WINLOW_MASK                     (0xFFU)
+#define WDOG_WIN_WINLOW_SHIFT                    (0U)
+#define WDOG_WIN_WINLOW(x)                       (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINLOW_SHIFT)) & WDOG_WIN_WINLOW_MASK)
+#define WDOG_WIN_WINHIGH_MASK                    (0xFF00U)
+#define WDOG_WIN_WINHIGH_SHIFT                   (8U)
+#define WDOG_WIN_WINHIGH(x)                      (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINHIGH_SHIFT)) & WDOG_WIN_WINHIGH_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG0 base address */
+#define WDOG0_BASE                               (0x4002A000u)
+/** Peripheral WDOG0 base pointer */
+#define WDOG0                                    ((WDOG_Type *)WDOG0_BASE)
+/** Peripheral WDOG1 base address */
+#define WDOG1_BASE                               (0x41026000u)
+/** Peripheral WDOG1 base pointer */
+#define WDOG1                                    ((WDOG_Type *)WDOG1_BASE)
+/** Array initializer of WDOG peripheral base addresses */
+#define WDOG_BASE_ADDRS                          { WDOG0_BASE, WDOG1_BASE }
+/** Array initializer of WDOG peripheral base pointers */
+#define WDOG_BASE_PTRS                           { WDOG0, WDOG1 }
+/** Interrupt vectors for the WDOG peripheral type */
+#define WDOG_IRQS                                { NotAvail_IRQn, WDOG1_IRQn }
+/* Extra definition */
+#define WDOG_UPDATE_KEY                          (0xD928C520U)
+#define WDOG_REFRESH_KEY                         (0xB480A602U)
+
+
+/*!
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- XCVR_ANALOG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XCVR_ANALOG_Peripheral_Access_Layer XCVR_ANALOG Peripheral Access Layer
+ * @{
+ */
+
+/** XCVR_ANALOG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t BB_LDO_1;                          /**< RF Analog Baseband LDO Control 1, offset: 0x0 */
+  __IO uint32_t BB_LDO_2;                          /**< RF Analog Baseband LDO Control 2, offset: 0x4 */
+  __IO uint32_t RX_ADC;                            /**< RF Analog ADC Control, offset: 0x8 */
+  __IO uint32_t RX_BBA;                            /**< RF Analog BBA Control, offset: 0xC */
+  __IO uint32_t RX_LNA;                            /**< RF Analog LNA Control, offset: 0x10 */
+  __IO uint32_t RX_TZA;                            /**< RF Analog TZA Control, offset: 0x14 */
+  __IO uint32_t RX_AUXPLL;                         /**< RF Analog Aux PLL Control, offset: 0x18 */
+  __IO uint32_t SY_CTRL_1;                         /**< RF Analog Synthesizer Control 1, offset: 0x1C */
+  __IO uint32_t SY_CTRL_2;                         /**< RF Analog Synthesizer Control 2, offset: 0x20 */
+  __IO uint32_t TX_DAC_PA;                         /**< RF Analog TX HPM DAC and PA Control, offset: 0x24 */
+  __IO uint32_t BALUN_TX;                          /**< RF Analog Balun TX Mode Control, offset: 0x28 */
+  __IO uint32_t BALUN_RX;                          /**< RF Analog Balun RX Mode Control, offset: 0x2C */
+  __I  uint32_t DFT_OBSV_1;                        /**< RF Analog DFT Observation Register 1, offset: 0x30 */
+  __IO uint32_t DFT_OBSV_2;                        /**< RF Analog DFT Observation Register 2, offset: 0x34 */
+  __IO uint32_t DFT_OBSV_3;                        /**< RF Analog DFT Observation Register 3, offset: 0x38 */
+} XCVR_ANALOG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- XCVR_ANALOG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XCVR_ANALOG_Register_Masks XCVR_ANALOG Register Masks
+ * @{
+ */
+
+/*! @name BB_LDO_1 - RF Analog Baseband LDO Control 1 */
+/*! @{ */
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP_MASK (0x1U)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP_SHIFT (0U)
+/*! BB_LDO_ADCDAC_BYP - rmap_bb_ldo_adcdac_byp
+ *  0b0..Bypass disabled.
+ *  0b1..Bypass enabled
+ */
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP_MASK)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL_MASK (0x2U)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL_SHIFT (1U)
+/*! BB_LDO_ADCDAC_DIAGSEL - rmap_bb_ldo_adcdac_diagsel
+ *  0b0..Diag disable
+ *  0b1..Diag enable
+ */
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL_MASK)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE_MASK (0xCU)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE_SHIFT (2U)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE_MASK)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM_MASK (0x70U)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM_SHIFT (4U)
+/*! BB_LDO_ADCDAC_TRIM - rmap_bb_ldo_adcdac_trim[2:0]
+ *  0b000..1.20 V ( Default )
+ *  0b001..1.25 V
+ *  0b010..1.28 V
+ *  0b011..1.33 V
+ *  0b100..1.40 V
+ *  0b101..1.44 V
+ *  0b110..1.50 V
+ *  0b111..1.66 V
+ */
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM_MASK)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP_MASK (0x100U)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP_SHIFT (8U)
+/*! BB_LDO_BBA_BYP - rmap_bb_ldo_bba_byp
+ *  0b0..Bypass disabled.
+ *  0b1..Bypass enabled
+ */
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP_MASK)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL_MASK (0x200U)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL_SHIFT (9U)
+/*! BB_LDO_BBA_DIAGSEL - rmap_bb_ldo_bba_diagsel
+ *  0b0..Diag disable
+ *  0b1..Diag enable
+ */
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL_MASK)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE_MASK (0xC00U)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE_SHIFT (10U)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE_MASK)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM_MASK (0x7000U)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM_SHIFT (12U)
+/*! BB_LDO_BBA_TRIM - rmap_bb_ldo_bba_trim[2:0]
+ *  0b000..1.20 V ( Default )
+ *  0b001..1.25 V
+ *  0b010..1.28 V
+ *  0b011..1.33 V
+ *  0b100..1.40 V
+ *  0b101..1.44 V
+ *  0b110..1.50 V
+ *  0b111..1.66 V
+ */
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM_MASK)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP_MASK (0x10000U)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP_SHIFT (16U)
+/*! BB_LDO_FDBK_BYP - rmap_bb_ldo_fdbk_byp
+ *  0b0..Bypass disabled.
+ *  0b1..Bypass enabled
+ */
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP_MASK)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL_MASK (0x20000U)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL_SHIFT (17U)
+/*! BB_LDO_FDBK_DIAGSEL - rmap_bb_ldo_fdbk_diagsel
+ *  0b0..Diag disable
+ *  0b1..Diag enable
+ */
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL_MASK)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE_MASK (0xC0000U)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE_SHIFT (18U)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE_MASK)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_MASK (0x700000U)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_SHIFT (20U)
+/*! BB_LDO_FDBK_TRIM - rmap_bb_ldo_fdbk_trim[2:0]
+ *  0b000..1.2/1.176 V ( Default )
+ *  0b001..1.138/1.115 V
+ *  0b010..1.085/1.066 V
+ *  0b011..1.04/1.025 V
+ *  0b100..1.28/1.25 V
+ *  0b101..1.4/1.35 V
+ *  0b110..1.55/1.4 V
+ *  0b111..1.78/1.4 V
+ */
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_MASK)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP_MASK  (0x1000000U)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP_SHIFT (24U)
+/*! BB_LDO_HF_BYP - rmap_bb_ldo_hf_byp
+ *  0b0..Bypass disabled.
+ *  0b1..Bypass enabled
+ */
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP_MASK)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL_MASK (0x2000000U)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL_SHIFT (25U)
+/*! BB_LDO_HF_DIAGSEL - rmap_bb_ldo_hf_diagsel
+ *  0b0..Diag disable
+ *  0b1..Diag enable
+ */
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL_MASK)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE_MASK (0xC000000U)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE_SHIFT (26U)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE_MASK)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM_MASK (0x70000000U)
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM_SHIFT (28U)
+/*! BB_LDO_HF_TRIM - rmap_bb_ldo_hf_trim[2:0]
+ *  0b000..1.20 V ( Default )
+ *  0b001..1.25 V
+ *  0b010..1.28 V
+ *  0b011..1.33 V
+ *  0b100..1.40 V
+ *  0b101..1.44 V
+ *  0b110..1.50 V
+ *  0b111..1.66 V
+ */
+#define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM_MASK)
+/*! @} */
+
+/*! @name BB_LDO_2 - RF Analog Baseband LDO Control 2 */
+/*! @{ */
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP_MASK  (0x1U)
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP_SHIFT (0U)
+/*! BB_LDO_PD_BYP - rmap_bb_ldo_pd_byp
+ *  0b0..Bypass disabled.
+ *  0b1..Bypass enabled
+ */
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP_MASK)
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL_MASK (0x2U)
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL_SHIFT (1U)
+/*! BB_LDO_PD_DIAGSEL - rmap_bb_ldo_pd_diagsel
+ *  0b0..Diag disable
+ *  0b1..Diag enable
+ */
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL_MASK)
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE_MASK (0xCU)
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE_SHIFT (2U)
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE_MASK)
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM_MASK (0x70U)
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM_SHIFT (4U)
+/*! BB_LDO_PD_TRIM - rmap_bb_ldo_pd_trim[2:0]
+ *  0b000..1.20 V ( Default )
+ *  0b001..1.25 V
+ *  0b010..1.28 V
+ *  0b011..1.33 V
+ *  0b100..1.40 V
+ *  0b101..1.44 V
+ *  0b110..1.50 V
+ *  0b111..1.66 V
+ */
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM_MASK)
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE_MASK (0x300U)
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE_SHIFT (8U)
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE_MASK)
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP_MASK (0x400U)
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP_SHIFT (10U)
+/*! BB_LDO_VCOLO_BYP - rmap_bb_ldo_vcolo_byp
+ *  0b0..Bypass disabled.
+ *  0b1..Bypass enabled
+ */
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP_MASK)
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL_MASK (0x800U)
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL_SHIFT (11U)
+/*! BB_LDO_VCOLO_DIAGSEL - rmap_bb_ldo_vcolo_diagsel
+ *  0b0..Diag disable
+ *  0b1..Diag enable
+ */
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL_MASK)
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_MASK (0x7000U)
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_SHIFT (12U)
+/*! BB_LDO_VCOLO_TRIM - rmap_bb_ldo_vcolo_trim[2:0]
+ *  0b000..1.138/1.117 V ( Default )
+ *  0b001..1.076/1.058 V
+ *  0b010..1.027/1.012 V
+ *  0b011..0.98/0.97 V
+ *  0b100..1.22/1.19 V
+ *  0b101..1.33/1.3 V
+ *  0b110..1.5/1.4 V
+ *  0b111..1.82/1.4 V
+ */
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_MASK)
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL_MASK (0x10000U)
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL_SHIFT (16U)
+/*! BB_LDO_VTREF_DIAGSEL - rmap_bb_ldo_vtref_diagsel
+ *  0b0..Diag disable
+ *  0b1..Diag enable
+ */
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL_MASK)
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC_MASK (0x60000U)
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC_SHIFT (17U)
+/*! BB_LDO_VTREF_TC - rmap_bb_ldo_vtref_tc[1:0]
+ *  0b00..1.117/1.176 V
+ *  0b01..1.134/1.188 V
+ *  0b10..1.10/1.162 V
+ *  0b11..1.09/1.152 V
+ */
+#define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC_MASK)
+/*! @} */
+
+/*! @name RX_ADC - RF Analog ADC Control */
+/*! @{ */
+#define XCVR_ANALOG_RX_ADC_RX_ADC_BUMP_MASK      (0xFFU)
+#define XCVR_ANALOG_RX_ADC_RX_ADC_BUMP_SHIFT     (0U)
+#define XCVR_ANALOG_RX_ADC_RX_ADC_BUMP(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_BUMP_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_BUMP_MASK)
+#define XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL_MASK    (0x300U)
+#define XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL_SHIFT   (8U)
+/*! RX_ADC_FS_SEL - rmap_rx_adc_fs_sel[1:0]
+ *  0b00..52MHz (2x26MHz)
+ *  0b01..64MHz (2x32MHz)
+ *  0b10..+13% of 64MHz
+ *  0b11..- 11% of 64MHz
+ */
+#define XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL_MASK)
+#define XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL_MASK (0x400U)
+#define XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL_SHIFT (10U)
+#define XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL_MASK)
+#define XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL_MASK (0x800U)
+#define XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL_SHIFT (11U)
+#define XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL_MASK)
+#define XCVR_ANALOG_RX_ADC_RX_ADC_SPARE_MASK     (0xF000U)
+#define XCVR_ANALOG_RX_ADC_RX_ADC_SPARE_SHIFT    (12U)
+#define XCVR_ANALOG_RX_ADC_RX_ADC_SPARE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_SPARE_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_SPARE_MASK)
+/*! @} */
+
+/*! @name RX_BBA - RF Analog BBA Control */
+/*! @{ */
+#define XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK    (0x7U)
+#define XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_SHIFT   (0U)
+/*! RX_BBA_BW_SEL - rmap_rx_bba_bw_sel[2:0]
+ *  0b000..1000K
+ *  0b001..900K
+ *  0b010..800K
+ *  0b011..700K Default
+ *  0b100..600K
+ *  0b101..500K
+ */
+#define XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK)
+#define XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP_MASK  (0x8U)
+#define XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP_SHIFT (3U)
+#define XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP_MASK)
+#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1_MASK  (0x10U)
+#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1_SHIFT (4U)
+/*! RX_BBA_DIAGSEL1 - rmap_rx_bba_diagsel1
+ *  0b0..Diag disable
+ *  0b1..Diag enable
+ */
+#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1_MASK)
+#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2_MASK  (0x20U)
+#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2_SHIFT (5U)
+/*! RX_BBA_DIAGSEL2 - rmap_rx_bba_diagsel2
+ *  0b0..Diag disable
+ *  0b1..Diag enable
+ */
+#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2_MASK)
+#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3_MASK  (0x40U)
+#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3_SHIFT (6U)
+/*! RX_BBA_DIAGSEL3 - rmap_rx_bba_diagsel3
+ *  0b0..Diag disable
+ *  0b1..Diag enable
+ */
+#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3_MASK)
+#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4_MASK  (0x80U)
+#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4_SHIFT (7U)
+/*! RX_BBA_DIAGSEL4 - rmap_rx_bba_diagsel4
+ *  0b0..Diag disable
+ *  0b1..Diag enable
+ */
+#define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4_MASK)
+#define XCVR_ANALOG_RX_BBA_RX_BBA_SPARE_MASK     (0x3F0000U)
+#define XCVR_ANALOG_RX_BBA_RX_BBA_SPARE_SHIFT    (16U)
+/*! RX_BBA_SPARE - rmap_rx_bba_spare[5:0]
+ *  0b000000..600mV (Default)
+ *  0b000001..675mV
+ *  0b000010..450mV
+ *  0b000011..525mV
+ */
+#define XCVR_ANALOG_RX_BBA_RX_BBA_SPARE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_SPARE_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_SPARE_MASK)
+#define XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK   (0x7000000U)
+#define XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_SHIFT  (24U)
+/*! RX_BBA2_BW_SEL - rmap_bba2_bw_sel[2:0]
+ *  0b000..1000K
+ *  0b001..900K
+ *  0b010..800K
+ *  0b011..700K Default
+ *  0b100..600K
+ *  0b101..500K
+ */
+#define XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK)
+#define XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE_MASK    (0x70000000U)
+#define XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE_SHIFT   (28U)
+#define XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE_MASK)
+/*! @} */
+
+/*! @name RX_LNA - RF Analog LNA Control */
+/*! @{ */
+#define XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_MASK      (0xFU)
+#define XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_SHIFT     (0U)
+/*! RX_LNA_BUMP - rmap_rx_lna_bump[3:0]
+ *  0b0000..Default
+ *  0b0001..-25%
+ *  0b0010..+50%
+ *  0b0011..+25%
+ *  0b0100..CM 480mV
+ *  0b1000..CM 600mV
+ *  0b1100..CM 660mV
+ */
+#define XCVR_ANALOG_RX_LNA_RX_LNA_BUMP(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_MASK)
+#define XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL_MASK (0x10U)
+#define XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL_SHIFT (4U)
+#define XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL_MASK)
+#define XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE_MASK (0x20U)
+#define XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE_SHIFT (5U)
+#define XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE_MASK)
+#define XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL_MASK (0x40U)
+#define XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL_SHIFT (6U)
+#define XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL_MASK)
+#define XCVR_ANALOG_RX_LNA_RX_LNA_SPARE_MASK     (0x300U)
+#define XCVR_ANALOG_RX_LNA_RX_LNA_SPARE_SHIFT    (8U)
+#define XCVR_ANALOG_RX_LNA_RX_LNA_SPARE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_SPARE_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_SPARE_MASK)
+#define XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP_MASK    (0xF0000U)
+#define XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP_SHIFT   (16U)
+/*! RX_MIXER_BUMP - rmap_rx_mixer_bump[3:0]
+ *  0b0000..825mV (Default)
+ *  0b0001..750mV
+ *  0b0010..900mV
+ *  0b0011..975mV
+ */
+#define XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP_MASK)
+#define XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE_MASK   (0x100000U)
+#define XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE_SHIFT  (20U)
+#define XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE_MASK)
+/*! @} */
+
+/*! @name RX_TZA - RF Analog TZA Control */
+/*! @{ */
+#define XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK    (0x7U)
+#define XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_SHIFT   (0U)
+/*! RX_TZA_BW_SEL - rmap_rx_tza_bw_sel[2:0]
+ *  0b000..1000K
+ *  0b001..900K
+ *  0b010..800K
+ *  0b011..700K Default
+ *  0b100..600K
+ *  0b101..500K
+ */
+#define XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK)
+#define XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP_MASK  (0x8U)
+#define XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP_SHIFT (3U)
+#define XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP_MASK)
+#define XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP_MASK (0x10U)
+#define XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP_SHIFT (4U)
+#define XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP_MASK)
+#define XCVR_ANALOG_RX_TZA_RX_TZA_SPARE_MASK     (0x3F0000U)
+#define XCVR_ANALOG_RX_TZA_RX_TZA_SPARE_SHIFT    (16U)
+/*! RX_TZA_SPARE - rmap_rx_tza_spare[5:0]
+ *  0b000000..600mV (Default)
+ *  0b000001..675mV
+ *  0b000010..450mV
+ *  0b000011..525mV
+ */
+#define XCVR_ANALOG_RX_TZA_RX_TZA_SPARE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA_SPARE_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA_SPARE_MASK)
+#define XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL_MASK  (0x1000000U)
+#define XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL_SHIFT (24U)
+/*! RX_TZA1_DIAGSEL - rmap_rx_tza1_diagsel
+ *  0b0..Diag disable
+ *  0b1..Diag enable
+ */
+#define XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL_MASK)
+#define XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL_MASK  (0x2000000U)
+#define XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL_SHIFT (25U)
+/*! RX_TZA2_DIAGSEL - rmap_rx_tza2_diagsel
+ *  0b0..Diag disable
+ *  0b1..Diag enable
+ */
+#define XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL_MASK)
+#define XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL_MASK  (0x4000000U)
+#define XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL_SHIFT (26U)
+/*! RX_TZA3_DIAGSEL - rmap_rx_tza3_diagsel
+ *  0b0..Diag disable
+ *  0b1..Diag enable
+ */
+#define XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL_MASK)
+#define XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL_MASK  (0x8000000U)
+#define XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL_SHIFT (27U)
+/*! RX_TZA4_DIAGSEL - rmap_rx_tza4_diagsel
+ *  0b0..Diag disable
+ *  0b1..Diag enable
+ */
+#define XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL_MASK)
+/*! @} */
+
+/*! @name RX_AUXPLL - RF Analog Aux PLL Control */
+/*! @{ */
+#define XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM_MASK     (0x7U)
+#define XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM_SHIFT    (0U)
+#define XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM_MASK)
+#define XCVR_ANALOG_RX_AUXPLL_DIAGSEL1_MASK      (0x8U)
+#define XCVR_ANALOG_RX_AUXPLL_DIAGSEL1_SHIFT     (3U)
+#define XCVR_ANALOG_RX_AUXPLL_DIAGSEL1(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_DIAGSEL1_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_DIAGSEL1_MASK)
+#define XCVR_ANALOG_RX_AUXPLL_DIAGSEL2_MASK      (0x10U)
+#define XCVR_ANALOG_RX_AUXPLL_DIAGSEL2_SHIFT     (4U)
+#define XCVR_ANALOG_RX_AUXPLL_DIAGSEL2(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_DIAGSEL2_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_DIAGSEL2_MASK)
+#define XCVR_ANALOG_RX_AUXPLL_LF_CNTL_MASK       (0xE0U)
+#define XCVR_ANALOG_RX_AUXPLL_LF_CNTL_SHIFT      (5U)
+#define XCVR_ANALOG_RX_AUXPLL_LF_CNTL(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_LF_CNTL_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_LF_CNTL_MASK)
+#define XCVR_ANALOG_RX_AUXPLL_SPARE_MASK         (0xF00U)
+#define XCVR_ANALOG_RX_AUXPLL_SPARE_SHIFT        (8U)
+#define XCVR_ANALOG_RX_AUXPLL_SPARE(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_SPARE_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_SPARE_MASK)
+#define XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_MASK (0xF000U)
+#define XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_SHIFT (12U)
+#define XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_MASK)
+#define XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE_MASK (0x10000U)
+#define XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE_SHIFT (16U)
+#define XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE_MASK)
+#define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST_MASK (0x300000U)
+#define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST_SHIFT (20U)
+/*! RXTX_BAL_BIAST - rmap_rxtx_bal_biast[1:0]
+ *  0b00..0.6
+ *  0b01..0.4
+ *  0b10..0.9
+ *  0b11..1.2
+ */
+#define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST_MASK)
+#define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE_MASK (0x7000000U)
+#define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE_SHIFT (24U)
+#define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE_MASK)
+#define XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL_MASK (0x10000000U)
+#define XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL_SHIFT (28U)
+#define XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL_MASK)
+/*! @} */
+
+/*! @name SY_CTRL_1 - RF Analog Synthesizer Control 1 */
+/*! @{ */
+#define XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE_MASK (0x1U)
+#define XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE_SHIFT (0U)
+#define XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE_MASK)
+#define XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE_MASK (0x2U)
+#define XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE_SHIFT (1U)
+#define XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE_MASK)
+#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK_MASK (0x30U)
+#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK_SHIFT (4U)
+/*! SY_LO_BUMP_RTLO_FDBK - rmap_sy_lo_bump_rtlo_fdbk[1:0]
+ *  0b00..1.045 V
+ *  0b01..1.084 V
+ *  0b10..1.097 V
+ *  0b11..1.10 V
+ */
+#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK_MASK)
+#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX_MASK (0xC0U)
+#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX_SHIFT (6U)
+/*! SY_LO_BUMP_RTLO_RX - rmap_sy_lo_bump_rtlo_rx[1:0]
+ *  0b00..1.051/1.037 V
+ *  0b01..1.082/1.075 V
+ *  0b10..1.092/1.088 V
+ *  0b11..1.098/1.094 V
+ */
+#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX_MASK)
+#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX_MASK (0x300U)
+#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX_SHIFT (8U)
+/*! SY_LO_BUMP_RTLO_TX - rmap_sy_lo_bump_rtlo_tx[1:0]
+ *  0b00..1.071/1.065 V
+ *  0b01..1.092/1.090 V
+ *  0b10..1.099/1.098 V
+ *  0b11..1.10/1.1 V
+ */
+#define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX_MASK)
+#define XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL_MASK (0x400U)
+#define XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL_SHIFT (10U)
+/*! SY_LO_DIAGSEL - rmap_sy_lo_diagsel
+ *  0b0..Diag disable
+ *  0b1..Diag enable
+ */
+#define XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL_MASK)
+#define XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE_MASK   (0x7000U)
+#define XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE_SHIFT  (12U)
+#define XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE_MASK)
+#define XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_MASK (0x70000U)
+#define XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_SHIFT (16U)
+#define XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_MASK)
+#define XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE_MASK  (0x80000U)
+#define XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE_SHIFT (19U)
+#define XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE_MASK)
+#define XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL_MASK (0x100000U)
+#define XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL_SHIFT (20U)
+#define XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL_MASK)
+#define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE_MASK (0x600000U)
+#define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE_SHIFT (21U)
+#define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE_MASK)
+#define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL_MASK (0x800000U)
+#define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL_SHIFT (23U)
+/*! SY_PD_PCH_SEL - rmap_sy_pd_pch_sel
+ *  0b0..inverter based precharge
+ *  0b1..resistor divider based precharge
+ */
+#define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL_MASK)
+#define XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE_MASK   (0x3000000U)
+#define XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE_SHIFT  (24U)
+/*! SY_PD_SPARE - rmap_sy_pd_spare[1:0]
+ *  0b00..Default ;
+ *  0b01..PD output is pulled down.
+ */
+#define XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE_MASK)
+/*! @} */
+
+/*! @name SY_CTRL_2 - RF Analog Synthesizer Control 2 */
+/*! @{ */
+#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS_MASK   (0x7U)
+#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS_SHIFT  (0U)
+/*! SY_VCO_BIAS - rmap_sy_vco_bias[2:0]
+ *  0b000..0.97V
+ *  0b001..1.033V
+ *  0b010..1.06V
+ *  0b011..1.07V
+ *  0b100..1.08V
+ *  0b101..1.085V
+ *  0b110..1.090V
+ *  0b111..1.095V
+ */
+#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS_MASK)
+#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL_MASK (0x8U)
+#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL_SHIFT (3U)
+/*! SY_VCO_DIAGSEL - rmap_sy_vco_diagsel
+ *  0b1..Diag enable
+ *  0b0..Diag disable
+ */
+#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL_MASK)
+#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV_MASK     (0x70U)
+#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV_SHIFT    (4U)
+/*! SY_VCO_KV - rmap_sy_vco_kv[2:0]
+ *  0b000..50MHz/V
+ *  0b001..60MHz/V
+ *  0b010..70MHz/V
+ *  0b011..80MHz/V
+ *  0b100..80MHz/V
+ *  0b101..80MHz/V
+ *  0b110..80MHz/V
+ *  0b111..80MHz/V
+ */
+#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV_MASK)
+#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK    (0x700U)
+#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_SHIFT   (8U)
+/*! SY_VCO_KVM - rmap_sy_vco_kvm[2:0]
+ *  0b000..10MHz/V
+ *  0b001..20MHz/V
+ *  0b010..30MHz/V
+ *  0b011..40MHz/V
+ *  0b100..40MHz/V
+ *  0b101..40MHz/V
+ *  0b110..40MHz/V
+ *  0b111..40MHz/V
+ */
+#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK)
+#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON_MASK (0x1000U)
+#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON_SHIFT (12U)
+/*! SY_VCO_PK_DET_ON - rmap_sy_vco_pk_det_on
+ *  0b1..Enable
+ *  0b0..Disable
+ */
+#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON_MASK)
+#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE_MASK  (0x1C000U)
+#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE_SHIFT (14U)
+#define XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE_MASK)
+/*! @} */
+
+/*! @name TX_DAC_PA - RF Analog TX HPM DAC and PA Control */
+/*! @{ */
+#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP_MASK (0x3U)
+#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP_SHIFT (0U)
+/*! TX_DAC_BUMP_CAP - rmap_tx_dac_bump_cap[1:0]
+ *  0b00..1pF(default)
+ *  0b01..1.5pF
+ *  0b10..1.5pF
+ *  0b11..2pF
+ */
+#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP_MASK)
+#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC_MASK (0x18U)
+#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC_SHIFT (3U)
+/*! TX_DAC_BUMP_IDAC - rmap_tx_dac_bump_idac[1:0]
+ *  0b00..250nA(default)
+ *  0b01..207nA
+ *  0b10..312nA
+ *  0b11..415nA
+ */
+#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC_MASK)
+#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD_MASK (0xC0U)
+#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD_SHIFT (6U)
+/*! TX_DAC_BUMP_RLOAD - rmap_tx_dac_bump_rload[1:0]
+ *  0b00..3.12 kohms(default)
+ *  0b01..2.34 kohms
+ *  0b10..3.9 kohms
+ *  0b11..4.6 kohms
+ */
+#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD_MASK)
+#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL_MASK (0x200U)
+#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL_SHIFT (9U)
+/*! TX_DAC_DIAGSEL - rmap_tx_dac_diagsel
+ *  0b0..Disable Diag
+ *  0b1..Enable Diag
+ */
+#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL_MASK)
+#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK_MASK (0x400U)
+#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK_SHIFT (10U)
+#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK_MASK)
+#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL_MASK (0x800U)
+#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL_SHIFT (11U)
+/*! TX_DAC_OPAMP_DIAGSEL - rmap_tx_dac_opamp_diagsel
+ *  0b0..Disable Diag
+ *  0b1..Enable Diag
+ */
+#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL_MASK)
+#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE_MASK  (0xE000U)
+#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE_SHIFT (13U)
+#define XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE_MASK)
+#define XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_MASK (0xE0000U)
+#define XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_SHIFT (17U)
+/*! TX_PA_BUMP_VBIAS - rmap_tx_pa_bump_vbias[2:0]
+ *  0b000..0.557
+ *  0b001..0.651
+ *  0b010..0.741
+ *  0b011..0.822
+ *  0b100..0.590
+ *  0b101..0.683
+ *  0b110..0.771
+ *  0b111..0.850
+ */
+#define XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_MASK)
+#define XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL_MASK (0x200000U)
+#define XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL_SHIFT (21U)
+#define XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL_MASK)
+#define XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE_MASK   (0x3800000U)
+#define XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE_SHIFT  (23U)
+#define XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE_MASK)
+/*! @} */
+
+/*! @name BALUN_TX - RF Analog Balun TX Mode Control */
+/*! @{ */
+#define XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE_MASK (0xFFFFFFU)
+#define XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE_SHIFT (0U)
+#define XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE_SHIFT)) & XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE_MASK)
+/*! @} */
+
+/*! @name BALUN_RX - RF Analog Balun RX Mode Control */
+/*! @{ */
+#define XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE_MASK (0xFFFFFFU)
+#define XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE_SHIFT (0U)
+#define XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE_SHIFT)) & XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE_MASK)
+/*! @} */
+
+/*! @name DFT_OBSV_1 - RF Analog DFT Observation Register 1 */
+/*! @{ */
+#define XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER_MASK (0x7FFFFU)
+#define XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER_SHIFT (0U)
+#define XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER_SHIFT)) & XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER_MASK)
+#define XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF_MASK (0xFFF00000U)
+#define XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF_SHIFT (20U)
+#define XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF_SHIFT)) & XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF_MASK)
+/*! @} */
+
+/*! @name DFT_OBSV_2 - RF Analog DFT Observation Register 2 */
+/*! @{ */
+#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_MASK (0x1FFFFU)
+#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_SHIFT (0U)
+#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_SHIFT)) & XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_MASK)
+#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH_MASK (0x7F000000U)
+#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH_SHIFT (24U)
+#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH_SHIFT)) & XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH_MASK)
+#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS_MASK (0x80000000U)
+#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS_SHIFT (31U)
+#define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS_SHIFT)) & XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS_MASK)
+/*! @} */
+
+/*! @name DFT_OBSV_3 - RF Analog DFT Observation Register 3 */
+/*! @{ */
+#define XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_INCREMENT_MASK (0x7U)
+#define XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_INCREMENT_SHIFT (0U)
+#define XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_INCREMENT_SHIFT)) & XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_INCREMENT_MASK)
+#define XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_STOP_MASK (0xFF00U)
+#define XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_STOP_SHIFT (8U)
+#define XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_STOP(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_STOP_SHIFT)) & XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_STOP_MASK)
+#define XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_START_MASK (0xFF0000U)
+#define XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_START_SHIFT (16U)
+#define XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_START(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_START_SHIFT)) & XCVR_ANALOG_DFT_OBSV_3_HPM_BIST_START_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group XCVR_ANALOG_Register_Masks */
+
+
+/* XCVR_ANALOG - Peripheral instance base addresses */
+/** Peripheral XCVR_ANA base address */
+#define XCVR_ANA_BASE                            (0x41030500u)
+/** Peripheral XCVR_ANA base pointer */
+#define XCVR_ANA                                 ((XCVR_ANALOG_Type *)XCVR_ANA_BASE)
+/** Array initializer of XCVR_ANALOG peripheral base addresses */
+#define XCVR_ANALOG_BASE_ADDRS                   { XCVR_ANA_BASE }
+/** Array initializer of XCVR_ANALOG peripheral base pointers */
+#define XCVR_ANALOG_BASE_PTRS                    { XCVR_ANA }
+
+/*!
+ * @}
+ */ /* end of group XCVR_ANALOG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- XCVR_CTRL Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XCVR_CTRL_Peripheral_Access_Layer XCVR_CTRL Peripheral Access Layer
+ * @{
+ */
+
+/** XCVR_CTRL - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t XCVR_CTRL;                         /**< TRANSCEIVER CONTROL, offset: 0x0 */
+  __IO uint32_t XCVR_STATUS;                       /**< TRANSCEIVER STATUS, offset: 0x4 */
+  __IO uint32_t BLE_ARB_CTRL;                      /**< BLE ARBITRATION CONTROL, offset: 0x8 */
+  __IO uint32_t OVERWRITE_VER;                     /**< OVERWRITE VERSION, offset: 0xC */
+  __IO uint32_t DTEST_CTRL;                        /**< DIGITAL TEST MUX CONTROL, offset: 0x10 */
+  __IO uint32_t DMA_CTRL;                          /**< TRANSCEIVER DMA CONTROL, offset: 0x14 */
+  __I  uint32_t DMA_DATA;                          /**< TRANSCEIVER DMA DATA, offset: 0x18 */
+  __IO uint32_t PACKET_RAM_CTRL;                   /**< PACKET RAM CONTROL, offset: 0x1C */
+  __I  uint32_t RAM_STOP_ADDR;                     /**< PACKET RAM DEBUG RAM STOP ADDRESS, offset: 0x20 */
+  __IO uint32_t FAD_CTRL;                          /**< FAD CONTROL, offset: 0x24 */
+  __IO uint32_t LPPS_CTRL;                         /**< LOW POWER PREAMBLE SEARCH CONTROL, offset: 0x28 */
+  __IO uint32_t COEX_CTRL;                         /**< COEXISTENCE CONTROL, offset: 0x2C */
+  __IO uint32_t CRCW_CFG;                          /**< CRC/WHITENER CONFIG REGISTER, offset: 0x30 */
+  __I  uint32_t CRC_EC_MASK;                       /**< CRC ERROR CORRECTION MASK, offset: 0x34 */
+  __I  uint32_t CRC_RES_OUT;                       /**< CRC RESULT, offset: 0x38 */
+  __IO uint32_t CRCW_CFG2;                         /**< CRC/WHITENER CONFIG 2 REGISTER, offset: 0x3C */
+} XCVR_CTRL_Type;
+
+/* ----------------------------------------------------------------------------
+   -- XCVR_CTRL Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XCVR_CTRL_Register_Masks XCVR_CTRL Register Masks
+ * @{
+ */
+
+/*! @name XCVR_CTRL - TRANSCEIVER CONTROL */
+/*! @{ */
+#define XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK        (0xFU)
+#define XCVR_CTRL_XCVR_CTRL_PROTOCOL_SHIFT       (0U)
+/*! PROTOCOL - Radio Protocol Selection
+ *  0b0000..BLE
+ *  0b0001..BLE in MBAN
+ *  0b0010..BLE overlap MBAN
+ *  0b0011..Reserved
+ *  0b0100..802.15.4
+ *  0b0101..802.15.4j
+ *  0b0110..Radio Channels 0-127 selectable, FSK
+ *  0b0111..Radio Channels 0-127 selectable, GFSK
+ *  0b1000..Generic GFSK, with Gaussian Filter
+ *  0b1001..Generic MSK, O-QPSK encoding
+ *  0b1010..Generic FSK, direct +/- Fdev FSK
+ */
+#define XCVR_CTRL_XCVR_CTRL_PROTOCOL(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_PROTOCOL_SHIFT)) & XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK)
+#define XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK     (0x70U)
+#define XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_SHIFT    (4U)
+#define XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_SHIFT)) & XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK)
+#define XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_MASK    (0x300U)
+#define XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_SHIFT   (8U)
+/*! REF_CLK_FREQ - Radio Reference Clock Frequency
+ *  0b00..32 MHz
+ *  0b01..26 MHz
+ *  0b10..Reserved
+ *  0b11..Reserved
+ */
+#define XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_SHIFT)) & XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_MASK)
+#define XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN_MASK (0x800U)
+#define XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN_SHIFT (11U)
+#define XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN_SHIFT)) & XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN_MASK)
+#define XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK       (0x3000U)
+#define XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_SHIFT      (12U)
+/*! DEMOD_SEL - Demodulator Selector
+ *  0b00..No demodulator selected
+ *  0b01..Use NXP Multi-standard PHY demodulator
+ *  0b10..Use Legacy 802.15.4 demodulator
+ *  0b11..Reserved
+ */
+#define XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_SHIFT)) & XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK)
+#define XCVR_CTRL_XCVR_CTRL_MAN_DSM_SEL_MASK     (0xC000U)
+#define XCVR_CTRL_XCVR_CTRL_MAN_DSM_SEL_SHIFT    (14U)
+#define XCVR_CTRL_XCVR_CTRL_MAN_DSM_SEL(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_MAN_DSM_SEL_SHIFT)) & XCVR_CTRL_XCVR_CTRL_MAN_DSM_SEL_MASK)
+#define XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK  (0x70000U)
+#define XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_SHIFT (16U)
+/*! RADIO0_IRQ_SEL - RADIO0_IRQ_SEL
+ *  0b000..Assign Radio #0 Interrupt to BLE
+ *  0b001..Assign Radio #0 Interrupt to 802.15.4
+ *  0b010..Radio #0 Interrupt unassigned
+ *  0b011..Assign Radio #0 Interrupt to GENERIC_FSK
+ *  0b100..Radio #0 Interrupt unassigned
+ *  0b101..Radio #0 Interrupt unassigned
+ *  0b110..Radio #0 Interrupt unassigned
+ *  0b111..Radio #0 Interrupt unassigned
+ */
+#define XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_SHIFT)) & XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK)
+#define XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK  (0x700000U)
+#define XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_SHIFT (20U)
+/*! RADIO1_IRQ_SEL - RADIO1_IRQ_SEL
+ *  0b000..Assign Radio #1 Interrupt to BLE
+ *  0b001..Assign Radio #1 Interrupt to 802.15.4
+ *  0b010..Radio #1 Interrupt unassigned
+ *  0b011..Assign Radio #1 Interrupt to GENERIC_FSK
+ *  0b100..Radio #1 Interrupt unassigned
+ *  0b101..Radio #1 Interrupt unassigned
+ *  0b110..Radio #1 Interrupt unassigned
+ *  0b111..Radio #1 Interrupt unassigned
+ */
+#define XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_SHIFT)) & XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK)
+#define XCVR_CTRL_XCVR_CTRL_TSM_LL_INHIBIT_MASK  (0xF000000U)
+#define XCVR_CTRL_XCVR_CTRL_TSM_LL_INHIBIT_SHIFT (24U)
+#define XCVR_CTRL_XCVR_CTRL_TSM_LL_INHIBIT(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_TSM_LL_INHIBIT_SHIFT)) & XCVR_CTRL_XCVR_CTRL_TSM_LL_INHIBIT_MASK)
+/*! @} */
+
+/*! @name XCVR_STATUS - TRANSCEIVER STATUS */
+/*! @{ */
+#define XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK     (0xFFU)
+#define XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT    (0U)
+#define XCVR_CTRL_XCVR_STATUS_TSM_COUNT(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT)) & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK)
+#define XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE_MASK (0xF00U)
+#define XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE_SHIFT (8U)
+/*! PLL_SEQ_STATE - PLL Sequence State
+ *  0b0000..PLL OFF
+ *  0b0010..CTUNE
+ *  0b0011..CTUNE_SETTLE
+ *  0b0110..HPMCAL1
+ *  0b1000..HPMCAL1_SETTLE
+ *  0b1010..HPMCAL2
+ *  0b1100..HPMCAL2_SETTLE
+ *  0b1111..PLLREADY
+ */
+#define XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE_SHIFT)) & XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE_MASK)
+#define XCVR_CTRL_XCVR_STATUS_RX_MODE_MASK       (0x1000U)
+#define XCVR_CTRL_XCVR_STATUS_RX_MODE_SHIFT      (12U)
+#define XCVR_CTRL_XCVR_STATUS_RX_MODE(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_RX_MODE_SHIFT)) & XCVR_CTRL_XCVR_STATUS_RX_MODE_MASK)
+#define XCVR_CTRL_XCVR_STATUS_TX_MODE_MASK       (0x2000U)
+#define XCVR_CTRL_XCVR_STATUS_TX_MODE_SHIFT      (13U)
+#define XCVR_CTRL_XCVR_STATUS_TX_MODE(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_TX_MODE_SHIFT)) & XCVR_CTRL_XCVR_STATUS_TX_MODE_MASK)
+#define XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ_MASK (0x10000U)
+#define XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ_SHIFT (16U)
+#define XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ_SHIFT)) & XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ_MASK)
+#define XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE_MASK (0x20000U)
+#define XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE_SHIFT (17U)
+#define XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE_SHIFT)) & XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE_MASK)
+#define XCVR_CTRL_XCVR_STATUS_XTAL_READY_MASK    (0x40000U)
+#define XCVR_CTRL_XCVR_STATUS_XTAL_READY_SHIFT   (18U)
+/*! XTAL_READY - RF Osciallator Xtal Ready
+ *  0b0..Indicates that the RF Oscillator is disabled or has not completed its warmup.
+ *  0b1..Indicates that the RF Oscillator has completed its warmup count and is ready for use.
+ */
+#define XCVR_CTRL_XCVR_STATUS_XTAL_READY(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_XTAL_READY_SHIFT)) & XCVR_CTRL_XCVR_STATUS_XTAL_READY_MASK)
+#define XCVR_CTRL_XCVR_STATUS_TSM_IRQ0_MASK      (0x1000000U)
+#define XCVR_CTRL_XCVR_STATUS_TSM_IRQ0_SHIFT     (24U)
+/*! TSM_IRQ0 - TSM Interrupt #0
+ *  0b0..TSM Interrupt #0 is not asserted.
+ *  0b1..TSM Interrupt #0 is asserted. Write '1' to this bit to clear it.
+ */
+#define XCVR_CTRL_XCVR_STATUS_TSM_IRQ0(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_TSM_IRQ0_SHIFT)) & XCVR_CTRL_XCVR_STATUS_TSM_IRQ0_MASK)
+#define XCVR_CTRL_XCVR_STATUS_TSM_IRQ1_MASK      (0x2000000U)
+#define XCVR_CTRL_XCVR_STATUS_TSM_IRQ1_SHIFT     (25U)
+/*! TSM_IRQ1 - TSM Interrupt #1
+ *  0b0..TSM Interrupt #1 is not asserted.
+ *  0b1..TSM Interrupt #1 is asserted. Write '1' to this bit to clear it.
+ */
+#define XCVR_CTRL_XCVR_STATUS_TSM_IRQ1(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_TSM_IRQ1_SHIFT)) & XCVR_CTRL_XCVR_STATUS_TSM_IRQ1_MASK)
+/*! @} */
+
+/*! @name BLE_ARB_CTRL - BLE ARBITRATION CONTROL */
+/*! @{ */
+#define XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH_MASK (0x1U)
+#define XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH_SHIFT (0U)
+#define XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH_SHIFT)) & XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH_MASK)
+#define XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY_MASK    (0x2U)
+#define XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY_SHIFT   (1U)
+/*! XCVR_BUSY - Transceiver Busy Status Bit
+ *  0b0..RF Channel in available (TSM is idle)
+ *  0b1..RF Channel in use (TSM is busy)
+ */
+#define XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY_SHIFT)) & XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY_MASK)
+/*! @} */
+
+/*! @name OVERWRITE_VER - OVERWRITE VERSION */
+/*! @{ */
+#define XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER_MASK (0xFFU)
+#define XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER_SHIFT (0U)
+#define XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER_SHIFT)) & XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER_MASK)
+/*! @} */
+
+/*! @name DTEST_CTRL - DIGITAL TEST MUX CONTROL */
+/*! @{ */
+#define XCVR_CTRL_DTEST_CTRL_DTEST_PAGE_MASK     (0x3FU)
+#define XCVR_CTRL_DTEST_CTRL_DTEST_PAGE_SHIFT    (0U)
+/*! DTEST_PAGE - DTEST Page Selector
+ *  0b000000..PLLFREQCAL
+ *  0b000001..PLLBESTDIFF
+ *  0b000010..PLLRIPPLE
+ *  0b000011..PLLHPMCAL
+ *  0b000100..PLLVCOMOD
+ *  0b000101..PLLUNLOCK
+ *  0b000110..PLLCYCSLIP
+ *  0b000111..PLLCHAN
+ *  0b001000..TXWARMUP
+ *  0b001001..TXPOWER
+ *  0b001010..TXFREQWORD
+ *  0b001011..RXWARMUP
+ *  0b001100..RXADC
+ *  0b001101..RXDMA
+ *  0b001110..RXDIGIQ
+ *  0b001111..RXDMA2
+ *  0b010000..RXINPH
+ *  0b010001..RSSI0
+ *  0b010010..RSSI1
+ *  0b010011..AGC0
+ *  0b010100..AGC1
+ *  0b010101..DCOC0
+ *  0b010110..DCOC1
+ *  0b010111..DCOC2
+ *  0b011000..DCOC3
+ *  0b011001..TSM
+ *  0b011010..MTTSMCAL
+ *  0b011011..MTADV
+ *  0b011100..MTINIT
+ *  0b011101..MTSCAN
+ *  0b011110..MTCONN
+ *  0b011111..MTDTM
+ *  0b100000..MTADVXCV
+ *  0b100001..MTCONXCV
+ *  0b100010..MTDTM2
+ *  0b100011..DSM
+ *  0b100100..PHY_FSK_STATE
+ *  0b100101..PHY_CFO_EST_PD
+ *  0b100110..PHY_CFO_EST_PD2
+ *  0b100111..PHY_EARLY_LATE
+ *  0b101000..PHY_FSK_DEMOD
+ *  0b101001..PHY_AA_SEARCH
+ *  0b101010..PHY_DATA_OUT
+ *  0b101011..PHY_SAMP_TIME
+ *  0b101100..CCA_ED_LQI
+ *  0b101101..CCA_ED_LQI2
+ *  0b101110..Reserved
+ *  0b101111..Reserved
+ *  0b110000..Reserved
+ *  0b110001..Reserved
+ *  0b110010..Reserved
+ *  0b110011..Reserved
+ *  0b110100..Reserved
+ *  0b110101..Reserved
+ *  0b110110..Reserved
+ *  0b110111..Reserved
+ *  0b111000..Reserved
+ *  0b111001..Reserved
+ *  0b111010..RCCAL
+ *  0b111011..AUXPLLFCAL
+ *  0b111100..GENFSKTX
+ *  0b111101..GENFSKRX
+ *  0b111110..GENFSKSTATE
+ *  0b111111..GENFILTER
+ */
+#define XCVR_CTRL_DTEST_CTRL_DTEST_PAGE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_DTEST_PAGE_SHIFT)) & XCVR_CTRL_DTEST_CTRL_DTEST_PAGE_MASK)
+#define XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK       (0x80U)
+#define XCVR_CTRL_DTEST_CTRL_DTEST_EN_SHIFT      (7U)
+/*! DTEST_EN - DTEST Enable
+ *  0b0..Disables DTEST. The DTEST pins assume their mission function.
+ *  0b1..Enables DTEST. The contents of the selected page (DTEST_PAGE) will appear on the DTEST output pins.
+ */
+#define XCVR_CTRL_DTEST_CTRL_DTEST_EN(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_DTEST_EN_SHIFT)) & XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK)
+#define XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN_MASK (0xF00U)
+#define XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN_SHIFT (8U)
+#define XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN_SHIFT)) & XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN_MASK)
+#define XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN_MASK (0xF000U)
+#define XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN_SHIFT (12U)
+#define XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN_SHIFT)) & XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN_MASK)
+#define XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY_MASK (0x30000U)
+#define XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY_SHIFT (16U)
+/*! TSM_GPIO_OVLAY - TSM GPIO Overlay Pin Control
+ *  0b00..there is no overlay, and the DTEST Page Table dictates the node that appears on each DTEST pin.
+ *  0b01..the register GPIO0_OVLAY_PIN[3:0] selects the DTEST pin on which GPIO0_TRIG_EN will appear.
+ *  0b10..the register GPIO1_OVLAY_PIN[3:0] selects the DTEST pin on which GPIO1_TRIG_EN will appear.
+ *  0b11..the register GPIO0_OVLAY_PIN[3:0] selects the DTEST pin on which GPIO0_TRIG_EN will appear, and the register GPIO1_OVLAY_PIN[3:0] selects the DTEST pin on which GPIO1_TRIG_EN will appear.
+ */
+#define XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY_SHIFT)) & XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY_MASK)
+#define XCVR_CTRL_DTEST_CTRL_DTEST_SHFT_MASK     (0x7000000U)
+#define XCVR_CTRL_DTEST_CTRL_DTEST_SHFT_SHIFT    (24U)
+#define XCVR_CTRL_DTEST_CTRL_DTEST_SHFT(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_DTEST_SHFT_SHIFT)) & XCVR_CTRL_DTEST_CTRL_DTEST_SHFT_MASK)
+#define XCVR_CTRL_DTEST_CTRL_DTEST_CCA2_SEL_MASK (0x8000000U)
+#define XCVR_CTRL_DTEST_CTRL_DTEST_CCA2_SEL_SHIFT (27U)
+/*! DTEST_CCA2_SEL - DTEST CCA Mode 2 Selector
+ *  0b0..cca2_max_or_sym[7:0] = cca2_cnt_sym[7:0]
+ *  0b1..cca2_max_or_sym[7:0] = cca2_cnt_max[7:0]
+ */
+#define XCVR_CTRL_DTEST_CTRL_DTEST_CCA2_SEL(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_DTEST_CCA2_SEL_SHIFT)) & XCVR_CTRL_DTEST_CTRL_DTEST_CCA2_SEL_MASK)
+#define XCVR_CTRL_DTEST_CTRL_RAW_MODE_I_MASK     (0x10000000U)
+#define XCVR_CTRL_DTEST_CTRL_RAW_MODE_I_SHIFT    (28U)
+#define XCVR_CTRL_DTEST_CTRL_RAW_MODE_I(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_RAW_MODE_I_SHIFT)) & XCVR_CTRL_DTEST_CTRL_RAW_MODE_I_MASK)
+#define XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q_MASK     (0x20000000U)
+#define XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q_SHIFT    (29U)
+#define XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q_SHIFT)) & XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q_MASK)
+/*! @} */
+
+/*! @name DMA_CTRL - TRANSCEIVER DMA CONTROL */
+/*! @{ */
+#define XCVR_CTRL_DMA_CTRL_DMA_PAGE_MASK         (0xFU)
+#define XCVR_CTRL_DMA_CTRL_DMA_PAGE_SHIFT        (0U)
+/*! DMA_PAGE - Transceiver DMA Page Selector
+ *  0b0000..DMA Idle
+ *  0b0001..RX_DIG I and Q
+ *  0b0010..RX_DIG I Only
+ *  0b0011..RX_DIG Q Only
+ *  0b0100..RAW ADC I and Q
+ *  0b0101..RAW ADC I Only
+ *  0b0110..RAW ADC Q only
+ *  0b0111..DC Estimator I and Q
+ *  0b1000..DC Estimator I Only
+ *  0b1001..DC Estimator Q only
+ *  0b1010..RX_DIG Phase Output
+ *  0b1011..Reserved
+ *  0b1100..Demodulator Soft Decision
+ *  0b1101..Demodulator Data Output
+ *  0b1110..Demodulator CFO Phase Output
+ *  0b1111..Reserved
+ */
+#define XCVR_CTRL_DMA_CTRL_DMA_PAGE(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_PAGE_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_PAGE_MASK)
+#define XCVR_CTRL_DMA_CTRL_DMA_EN_MASK           (0x10U)
+#define XCVR_CTRL_DMA_CTRL_DMA_EN_SHIFT          (4U)
+#define XCVR_CTRL_DMA_CTRL_DMA_EN(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_EN_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_EN_MASK)
+#define XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC_MASK  (0x20U)
+#define XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC_SHIFT (5U)
+/*! BYPASS_DMA_SYNC - Bypass External DMA Synchronization
+ *  0b0..Don't Bypass External Synchronization. Use this setting if SINGLE_REQ_MODE=1.
+ *  0b1..Bypass External Synchronization. This setting is mandatory if SINGLE_REQ_MODE=0.
+ */
+#define XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC_SHIFT)) & XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC_MASK)
+#define XCVR_CTRL_DMA_CTRL_DMA_AA_TRIGGERED_MASK (0x40U)
+#define XCVR_CTRL_DMA_CTRL_DMA_AA_TRIGGERED_SHIFT (6U)
+#define XCVR_CTRL_DMA_CTRL_DMA_AA_TRIGGERED(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_AA_TRIGGERED_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_AA_TRIGGERED_MASK)
+#define XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_MASK    (0x80U)
+#define XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_SHIFT   (7U)
+/*! DMA_TIMED_OUT - DMA Transfer Timed Out
+ *  0b0..A DMA timeout has not occurred
+ *  0b1..A DMA timeout has occurred in Single Request Mode since the last time this bit was cleared
+ */
+#define XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_MASK)
+#define XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT_MASK      (0xF00U)
+#define XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT_SHIFT     (8U)
+#define XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT_MASK)
+#define XCVR_CTRL_DMA_CTRL_DMA_START_TRG_MASK    (0x7000U)
+#define XCVR_CTRL_DMA_CTRL_DMA_START_TRG_SHIFT   (12U)
+#define XCVR_CTRL_DMA_CTRL_DMA_START_TRG(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_START_TRG_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_START_TRG_MASK)
+#define XCVR_CTRL_DMA_CTRL_DMA_START_EDGE_MASK   (0x8000U)
+#define XCVR_CTRL_DMA_CTRL_DMA_START_EDGE_SHIFT  (15U)
+/*! DMA_START_EDGE - DMA Start Trigger Edge Selector
+ *  0b0..Trigger fires on a rising edge of the selected trigger source
+ *  0b1..Trigger fires on a falling edge of the selected trigger source
+ */
+#define XCVR_CTRL_DMA_CTRL_DMA_START_EDGE(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_START_EDGE_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_START_EDGE_MASK)
+#define XCVR_CTRL_DMA_CTRL_DMA_START_TRIGGERED_MASK (0x10000U)
+#define XCVR_CTRL_DMA_CTRL_DMA_START_TRIGGERED_SHIFT (16U)
+#define XCVR_CTRL_DMA_CTRL_DMA_START_TRIGGERED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_START_TRIGGERED_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_START_TRIGGERED_MASK)
+#define XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE_MASK  (0x20000U)
+#define XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE_SHIFT (17U)
+/*! SINGLE_REQ_MODE - DMA Single Request Mode
+ *  0b0..Disable Single Request Mode. The transceiver will assert ipd_req_radio_rx whenever it has a new sample ready for transfer.
+ *  0b1..Enable Single Request Mode. A single initial request by the transceiver will transfer the entire DMA block of data
+ */
+#define XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE_SHIFT)) & XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE_MASK)
+/*! @} */
+
+/*! @name DMA_DATA - TRANSCEIVER DMA DATA */
+/*! @{ */
+#define XCVR_CTRL_DMA_DATA_DMA_DATA_MASK         (0xFFFFFFFFU)
+#define XCVR_CTRL_DMA_DATA_DMA_DATA_SHIFT        (0U)
+#define XCVR_CTRL_DMA_DATA_DMA_DATA(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_DATA_DMA_DATA_SHIFT)) & XCVR_CTRL_DMA_DATA_DMA_DATA_MASK)
+/*! @} */
+
+/*! @name PACKET_RAM_CTRL - PACKET RAM CONTROL */
+/*! @{ */
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK  (0xFU)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_SHIFT (0U)
+/*! DBG_PAGE - Packet RAM Debug Page Selector
+ *  0b0000..Packet RAM Debug Mode Idle
+ *  0b0001..RX_DIG I and Q
+ *  0b0010..Reserved
+ *  0b0011..Reserved
+ *  0b0100..RAW ADC I and Q
+ *  0b0101..Reserved
+ *  0b0110..Reserved
+ *  0b0111..DC Estimator I and Q
+ *  0b1000..Reserved
+ *  0b1001..Reserved
+ *  0b1010..RX_DIG Phase Output
+ *  0b1011..Reserved
+ *  0b1100..Demodulator Soft Decision
+ *  0b1101..Demodulator Data Output
+ *  0b1110..Demodulator CFO Phase Output
+ *  0b1111..Reserved
+ */
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_EN_MASK    (0x10U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_EN_SHIFT   (4U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_EN_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_EN_MASK)
+#define XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_PAGE_MASK (0x20U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_PAGE_SHIFT (5U)
+/*! XCVR_RAM_PAGE - RAM Page Selector for XCVR Access
+ *  0b0..RAM0 is mapped into XCVR address space, between XCVR_BASE + 0x700, and XCVR_BASE + 0xFFF
+ *  0b1..RAM1 is mapped into XCVR address space, between XCVR_BASE + 0x700, and XCVR_BASE + 0xFFF
+ */
+#define XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_PAGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_PAGE_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_PAGE_MASK)
+#define XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK (0x40U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_SHIFT (6U)
+/*! XCVR_RAM_ALLOW - Allow Packet RAM Transceiver Access
+ *  0b0..Protocol Engines, and associated IPS busses, have exclusive access to Packet RAM (mission mode)
+ *  0b1..Transceiver-space access to Packet RAM, including Packet RAM debug mode, are allowed
+ */
+#define XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK)
+#define XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW_MASK (0x80U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW_SHIFT (7U)
+/*! ALL_PROTOCOLS_ALLOW - Allow IPS bus access to Packet RAM for any protocol at any time.
+ *  0b0..IPS bus access to Packet RAM is restricted to the protocol engine currently selected by XCVR_CTRL[PROTOCOL].
+ *  0b1..All IPS bus access to Packet RAM permitted, regardless of XCVR_CTRL[PROTOCOL] setting
+ */
+#define XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW_MASK)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL_MASK (0x300U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL_SHIFT (8U)
+/*! DBG_RAM_FULL - DBG_RAM_FULL[1:0]
+ *  0b00..Neither Packet RAM0 nor RAM1 is full
+ *  0bx1..Packet RAM0 has been filled to capacity.
+ *  0b1x..Packet RAM1 has been filled to capacity.
+ */
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL_MASK)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_AA_TRIGGERED_MASK (0x400U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_AA_TRIGGERED_SHIFT (10U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_AA_TRIGGERED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_AA_TRIGGERED_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_AA_TRIGGERED_MASK)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_SOFT_INFO_SEL_MASK (0x800U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_SOFT_INFO_SEL_SHIFT (11U)
+/*! DBG_SOFT_INFO_SEL - Packet RAM Debug PHY Soft Info Output Selector
+ *  0b0..PHY output bit_valid_int is used to capture soft decision data
+ *  0b1..PHY output demod_vout is used to capture soft decision data
+ */
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_SOFT_INFO_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_SOFT_INFO_SEL_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_SOFT_INFO_SEL_MASK)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_TRG_MASK (0x7000U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_TRG_SHIFT (12U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_TRG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_TRG_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_TRG_MASK)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_EDGE_MASK (0x8000U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_EDGE_SHIFT (15U)
+/*! DBG_START_EDGE - Packet RAM Debug Start Trigger Edge Selector
+ *  0b0..Trigger fires on a rising edge of the selected trigger source
+ *  0b1..Trigger fires on a falling edge of the selected trigger source
+ */
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_EDGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_EDGE_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_EDGE_MASK)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_TRG_MASK (0xF0000U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_TRG_SHIFT (16U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_TRG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_TRG_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_TRG_MASK)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_EDGE_MASK (0x100000U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_EDGE_SHIFT (20U)
+/*! DBG_STOP_EDGE - Packet RAM Debug Stop Trigger Edge Selector
+ *  0b0..Trigger fires on a rising edge of the selected trigger source
+ *  0b1..Trigger fires on a falling edge of the selected trigger source
+ */
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_EDGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_EDGE_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_EDGE_MASK)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_TRIGGERED_MASK (0x200000U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_TRIGGERED_SHIFT (21U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_TRIGGERED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_TRIGGERED_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_TRIGGERED_MASK)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_TRIGGERED_MASK (0x400000U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_TRIGGERED_SHIFT (22U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_TRIGGERED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_TRIGGERED_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_TRIGGERED_MASK)
+#define XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT_MASK (0x800000U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT_SHIFT (23U)
+/*! PB_PROTECT - Packet Buffer Protect
+ *  0b0..Incoming received packets overwrite Packet Buffer RX contents (default)
+ *  0b1..Incoming received packets are blocked from overwriting Packet Buffer RX contents
+ */
+#define XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT_MASK)
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN_MASK (0x1000000U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN_SHIFT (24U)
+/*! RAM0_CLK_ON_OVRD_EN - Override control for RAM0 Clock Gate Enable
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RAM0_CLK_ON_OVRD to override the RAM0 Clock Gate Enable.
+ */
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN_MASK)
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_MASK (0x2000000U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_SHIFT (25U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_MASK)
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN_MASK (0x4000000U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN_SHIFT (26U)
+/*! RAM1_CLK_ON_OVRD_EN - Override control for RAM1 Clock Gate Enable
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RAM1_CLK_ON_OVRD to override the RAM1 Clock Gate Enable.
+ */
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN_MASK)
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_MASK (0x8000000U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_SHIFT (27U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_MASK)
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN_MASK (0x10000000U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN_SHIFT (28U)
+/*! RAM0_CE_ON_OVRD_EN - Override control for RAM0 CE (Chip Enable)
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RAM0_CE_ON_OVRD to override the RAM0 CE.
+ */
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN_MASK)
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_MASK (0x20000000U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_SHIFT (29U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_MASK)
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN_MASK (0x40000000U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN_SHIFT (30U)
+/*! RAM1_CE_ON_OVRD_EN - Override control for RAM1 CE (Chip Enable)
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RAM1_CE_ON_OVRD to override the RAM1 CE.
+ */
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN_MASK)
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_MASK (0x80000000U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_SHIFT (31U)
+#define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_MASK)
+/*! @} */
+
+/*! @name RAM_STOP_ADDR - PACKET RAM DEBUG RAM STOP ADDRESS */
+/*! @{ */
+#define XCVR_CTRL_RAM_STOP_ADDR_RAM0_STOP_ADDR_MASK (0x7FFU)
+#define XCVR_CTRL_RAM_STOP_ADDR_RAM0_STOP_ADDR_SHIFT (0U)
+#define XCVR_CTRL_RAM_STOP_ADDR_RAM0_STOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_RAM_STOP_ADDR_RAM0_STOP_ADDR_SHIFT)) & XCVR_CTRL_RAM_STOP_ADDR_RAM0_STOP_ADDR_MASK)
+#define XCVR_CTRL_RAM_STOP_ADDR_RAM1_STOP_ADDR_MASK (0x7FF0000U)
+#define XCVR_CTRL_RAM_STOP_ADDR_RAM1_STOP_ADDR_SHIFT (16U)
+#define XCVR_CTRL_RAM_STOP_ADDR_RAM1_STOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_RAM_STOP_ADDR_RAM1_STOP_ADDR_SHIFT)) & XCVR_CTRL_RAM_STOP_ADDR_RAM1_STOP_ADDR_MASK)
+/*! @} */
+
+/*! @name FAD_CTRL - FAD CONTROL */
+/*! @{ */
+#define XCVR_CTRL_FAD_CTRL_FAD_EN_MASK           (0x1U)
+#define XCVR_CTRL_FAD_CTRL_FAD_EN_SHIFT          (0U)
+/*! FAD_EN - Fast Antenna Diversity Enable
+ *  0b0..Fast Antenna Diversity disabled
+ *  0b1..Fast Antenna Diversity enabled
+ */
+#define XCVR_CTRL_FAD_CTRL_FAD_EN(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_FAD_EN_SHIFT)) & XCVR_CTRL_FAD_CTRL_FAD_EN_MASK)
+#define XCVR_CTRL_FAD_CTRL_ANTX_MASK             (0x2U)
+#define XCVR_CTRL_FAD_CTRL_ANTX_SHIFT            (1U)
+#define XCVR_CTRL_FAD_CTRL_ANTX(x)               (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_MASK)
+#define XCVR_CTRL_FAD_CTRL_ANTX_OVRD_EN_MASK     (0x4U)
+#define XCVR_CTRL_FAD_CTRL_ANTX_OVRD_EN_SHIFT    (2U)
+#define XCVR_CTRL_FAD_CTRL_ANTX_OVRD_EN(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_OVRD_EN_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_OVRD_EN_MASK)
+#define XCVR_CTRL_FAD_CTRL_ANTX_OVRD_MASK        (0x8U)
+#define XCVR_CTRL_FAD_CTRL_ANTX_OVRD_SHIFT       (3U)
+#define XCVR_CTRL_FAD_CTRL_ANTX_OVRD(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_OVRD_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_OVRD_MASK)
+#define XCVR_CTRL_FAD_CTRL_ANTX_EN_MASK          (0x30U)
+#define XCVR_CTRL_FAD_CTRL_ANTX_EN_SHIFT         (4U)
+/*! ANTX_EN - FAD Antenna Controls Enable
+ *  0b00..all disabled (held low)
+ *  0b01..only RX/TX_SWITCH enabled
+ *  0b10..only ANT_A/B enabled
+ *  0b11..all enabled
+ */
+#define XCVR_CTRL_FAD_CTRL_ANTX_EN(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_EN_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_EN_MASK)
+#define XCVR_CTRL_FAD_CTRL_ANTX_HZ_MASK          (0x40U)
+#define XCVR_CTRL_FAD_CTRL_ANTX_HZ_SHIFT         (6U)
+/*! ANTX_HZ - FAD PAD Tristate Control
+ *  0b0..ANT_A, ANT_B, RX_SWITCH and TX_SWITCH are actively driven outputs.
+ *  0b1..Antenna controls high impedance- Set ANT_A, ANT_B, RX_SWITCH and TX_SWITCH in high impedance.
+ */
+#define XCVR_CTRL_FAD_CTRL_ANTX_HZ(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_HZ_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_HZ_MASK)
+#define XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE_MASK    (0x80U)
+#define XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE_SHIFT   (7U)
+#define XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE_MASK)
+#define XCVR_CTRL_FAD_CTRL_ANTX_POL_MASK         (0xF00U)
+#define XCVR_CTRL_FAD_CTRL_ANTX_POL_SHIFT        (8U)
+#define XCVR_CTRL_FAD_CTRL_ANTX_POL(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_POL_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_POL_MASK)
+#define XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK     (0xF000U)
+#define XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_SHIFT    (12U)
+#define XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_SHIFT)) & XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK)
+/*! @} */
+
+/*! @name LPPS_CTRL - LOW POWER PREAMBLE SEARCH CONTROL */
+/*! @{ */
+#define XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE_MASK     (0x1U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE_SHIFT    (0U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE_MASK)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW_MASK  (0x2U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW_SHIFT (1U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW_MASK)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW_MASK  (0x4U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW_SHIFT (2U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW_MASK)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW_MASK  (0x8U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW_SHIFT (3U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW_MASK)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW_MASK (0x10U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW_SHIFT (4U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW_MASK)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW_MASK (0x20U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW_SHIFT (5U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW_MASK)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW_MASK (0x40U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW_SHIFT (6U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW_MASK)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW_MASK (0x80U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW_SHIFT (7U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW_MASK)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW_MASK (0x100U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW_SHIFT (8U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW_MASK)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW_MASK (0x200U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW_SHIFT (9U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW_MASK)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_START_RX_MASK   (0xFF0000U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_START_RX_SHIFT  (16U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_START_RX(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_START_RX_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_START_RX_MASK)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX_MASK    (0xFF000000U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX_SHIFT   (24U)
+#define XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX_MASK)
+/*! @} */
+
+/*! @name COEX_CTRL - COEXISTENCE CONTROL */
+/*! @{ */
+#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_EN_MASK (0xFU)
+#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_EN_SHIFT (0U)
+#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_EN_SHIFT)) & XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_EN_MASK)
+#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_NO_TX_MASK (0x10U)
+#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_NO_TX_SHIFT (4U)
+/*! RF_NOT_ALLOWED_NO_TX - RF_NOT_ALLOWED_NO_TX
+ *  0b0..Assertion on RF_NOT_ALLOWED has no effect on TX
+ *  0b1..Assertion on RF_NOT_ALLOWED can abort TX
+ */
+#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_NO_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_NO_TX_SHIFT)) & XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_NO_TX_MASK)
+#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_NO_RX_MASK (0x20U)
+#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_NO_RX_SHIFT (5U)
+/*! RF_NOT_ALLOWED_NO_RX - RF_NOT_ALLOWED_NO_RX
+ *  0b0..Assertion on RF_NOT_ALLOWED has no effect on RX
+ *  0b1..Assertion on RF_NOT_ALLOWED can abort RX
+ */
+#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_NO_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_NO_RX_SHIFT)) & XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_NO_RX_MASK)
+#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_ASSERTED_MASK (0x40U)
+#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_ASSERTED_SHIFT (6U)
+/*! RF_NOT_ALLOWED_ASSERTED - RF_NOT_ALLOWED_ASSERTED
+ *  0b0..Assertion on RF_NOT_ALLOWED has not occurred
+ *  0b1..Assertion on RF_NOT_ALLOWED has occurred since the last time this bit was cleared
+ */
+#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_ASSERTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_ASSERTED_SHIFT)) & XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_ASSERTED_MASK)
+#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_TX_ABORT_MASK (0x80U)
+#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_TX_ABORT_SHIFT (7U)
+/*! RF_NOT_ALLOWED_TX_ABORT - RF_NOT_ALLOWED_TX_ABORT
+ *  0b0..A TX abort due to assertion on RF_NOT_ALLOWED has not occurred
+ *  0b1..A TX abort due to assertion on RF_NOT_ALLOWED has occurred since the last time this bit was cleared
+ */
+#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_TX_ABORT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_TX_ABORT_SHIFT)) & XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_TX_ABORT_MASK)
+#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_RX_ABORT_MASK (0x100U)
+#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_RX_ABORT_SHIFT (8U)
+/*! RF_NOT_ALLOWED_RX_ABORT - RF_NOT_ALLOWED_RX_ABORT
+ *  0b0..A RX abort due to assertion on RF_NOT_ALLOWED has not occurred
+ *  0b1..A RX abort due to assertion on RF_NOT_ALLOWED has occurred since the last time this bit was cleared
+ */
+#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_RX_ABORT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_RX_ABORT_SHIFT)) & XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_RX_ABORT_MASK)
+#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_MASK  (0x200U)
+#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_SHIFT (9U)
+#define XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_SHIFT)) & XCVR_CTRL_COEX_CTRL_RF_NOT_ALLOWED_MASK)
+#define XCVR_CTRL_COEX_CTRL_TSM_SPARE1_EXTEND_MASK (0xFF0000U)
+#define XCVR_CTRL_COEX_CTRL_TSM_SPARE1_EXTEND_SHIFT (16U)
+#define XCVR_CTRL_COEX_CTRL_TSM_SPARE1_EXTEND(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_COEX_CTRL_TSM_SPARE1_EXTEND_SHIFT)) & XCVR_CTRL_COEX_CTRL_TSM_SPARE1_EXTEND_MASK)
+/*! @} */
+
+/*! @name CRCW_CFG - CRC/WHITENER CONFIG REGISTER */
+/*! @{ */
+#define XCVR_CTRL_CRCW_CFG_CRCW_EN_MASK          (0x1U)
+#define XCVR_CTRL_CRCW_CFG_CRCW_EN_SHIFT         (0U)
+#define XCVR_CTRL_CRCW_CFG_CRCW_EN(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRCW_EN_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRCW_EN_MASK)
+#define XCVR_CTRL_CRCW_CFG_CRCW_EC_EN_MASK       (0x2U)
+#define XCVR_CTRL_CRCW_CFG_CRCW_EC_EN_SHIFT      (1U)
+#define XCVR_CTRL_CRCW_CFG_CRCW_EC_EN(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRCW_EC_EN_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRCW_EC_EN_MASK)
+#define XCVR_CTRL_CRCW_CFG_CRC_ZERO_MASK         (0x4U)
+#define XCVR_CTRL_CRCW_CFG_CRC_ZERO_SHIFT        (2U)
+#define XCVR_CTRL_CRCW_CFG_CRC_ZERO(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_ZERO_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_ZERO_MASK)
+#define XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL_MASK   (0x8U)
+#define XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL_SHIFT  (3U)
+#define XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL_MASK)
+#define XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD_MASK  (0x10U)
+#define XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD_SHIFT (4U)
+#define XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD_MASK)
+#define XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET_MASK    (0x7FF0000U)
+#define XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET_SHIFT   (16U)
+#define XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET_MASK)
+#define XCVR_CTRL_CRCW_CFG_CRC_EC_DONE_MASK      (0x10000000U)
+#define XCVR_CTRL_CRCW_CFG_CRC_EC_DONE_SHIFT     (28U)
+#define XCVR_CTRL_CRCW_CFG_CRC_EC_DONE(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_EC_DONE_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_EC_DONE_MASK)
+#define XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL_MASK      (0x20000000U)
+#define XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL_SHIFT     (29U)
+#define XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL_MASK)
+/*! @} */
+
+/*! @name CRC_EC_MASK - CRC ERROR CORRECTION MASK */
+/*! @{ */
+#define XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK_MASK   (0xFFFFFFFFU)
+#define XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK_SHIFT  (0U)
+#define XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK_SHIFT)) & XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK_MASK)
+/*! @} */
+
+/*! @name CRC_RES_OUT - CRC RESULT */
+/*! @{ */
+#define XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT_MASK   (0xFFFFFFFFU)
+#define XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT_SHIFT  (0U)
+#define XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT_SHIFT)) & XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT_MASK)
+/*! @} */
+
+/*! @name CRCW_CFG2 - CRC/WHITENER CONFIG 2 REGISTER */
+/*! @{ */
+#define XCVR_CTRL_CRCW_CFG2_CRC_EC_SPKT_BYTES_MASK (0xFFU)
+#define XCVR_CTRL_CRCW_CFG2_CRC_EC_SPKT_BYTES_SHIFT (0U)
+#define XCVR_CTRL_CRCW_CFG2_CRC_EC_SPKT_BYTES(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG2_CRC_EC_SPKT_BYTES_SHIFT)) & XCVR_CTRL_CRCW_CFG2_CRC_EC_SPKT_BYTES_MASK)
+#define XCVR_CTRL_CRCW_CFG2_CRC_EC_SPKT_WND_MASK (0xF00U)
+#define XCVR_CTRL_CRCW_CFG2_CRC_EC_SPKT_WND_SHIFT (8U)
+#define XCVR_CTRL_CRCW_CFG2_CRC_EC_SPKT_WND(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG2_CRC_EC_SPKT_WND_SHIFT)) & XCVR_CTRL_CRCW_CFG2_CRC_EC_SPKT_WND_MASK)
+#define XCVR_CTRL_CRCW_CFG2_CRC_EC_LPKT_WND_MASK (0xF000U)
+#define XCVR_CTRL_CRCW_CFG2_CRC_EC_LPKT_WND_SHIFT (12U)
+#define XCVR_CTRL_CRCW_CFG2_CRC_EC_LPKT_WND(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG2_CRC_EC_LPKT_WND_SHIFT)) & XCVR_CTRL_CRCW_CFG2_CRC_EC_LPKT_WND_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group XCVR_CTRL_Register_Masks */
+
+
+/* XCVR_CTRL - Peripheral instance base addresses */
+/** Peripheral XCVR_MISC base address */
+#define XCVR_MISC_BASE                           (0x41030280u)
+/** Peripheral XCVR_MISC base pointer */
+#define XCVR_MISC                                ((XCVR_CTRL_Type *)XCVR_MISC_BASE)
+/** Array initializer of XCVR_CTRL peripheral base addresses */
+#define XCVR_CTRL_BASE_ADDRS                     { XCVR_MISC_BASE }
+/** Array initializer of XCVR_CTRL peripheral base pointers */
+#define XCVR_CTRL_BASE_PTRS                      { XCVR_MISC }
+
+/*!
+ * @}
+ */ /* end of group XCVR_CTRL_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- XCVR_PHY Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XCVR_PHY_Peripheral_Access_Layer XCVR_PHY Peripheral Access Layer
+ * @{
+ */
+
+/** XCVR_PHY - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PHY_FSK_PD_CFG0;                   /**< Preamble Detect Config 0, offset: 0x0 */
+  __IO uint32_t PHY_FSK_PD_CFG1;                   /**< Preamble Detect Config 1, offset: 0x4 */
+  __IO uint32_t PHY_FSK_CFG;                       /**< PHY Configuration, offset: 0x8 */
+  __IO uint32_t PHY_FSK_MISC;                      /**< PHY Misc. Configuration, offset: 0xC */
+  __IO uint32_t NTW_ADR_BSM;                       /**< PHY BSM Network Address, offset: 0x10 */
+  __I  uint32_t FSK_STAT;                          /**< PHY Status, offset: 0x14 */
+  __IO uint32_t FSK_FAD_CTRL;                      /**< PHY FAD control, offset: 0x18 */
+} XCVR_PHY_Type;
+
+/* ----------------------------------------------------------------------------
+   -- XCVR_PHY Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XCVR_PHY_Register_Masks XCVR_PHY Register Masks
+ * @{
+ */
+
+/*! @name PHY_FSK_PD_CFG0 - Preamble Detect Config 0 */
+/*! @{ */
+#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF0_MASK   (0x1FU)
+#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF0_SHIFT  (0U)
+#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF0(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF0_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF0_MASK)
+#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF1_MASK   (0x3E0U)
+#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF1_SHIFT  (5U)
+#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF1(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF1_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF1_MASK)
+#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF2_MASK   (0x7C00U)
+#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF2_SHIFT  (10U)
+#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF2(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF2_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF2_MASK)
+#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF3_MASK   (0xF8000U)
+#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF3_SHIFT  (15U)
+#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF3(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF3_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF3_MASK)
+#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF4_MASK   (0x1F00000U)
+#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF4_SHIFT  (20U)
+#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF4(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF4_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF4_MASK)
+#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF5_MASK   (0x3E000000U)
+#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF5_SHIFT  (25U)
+#define XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF5(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF5_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG0_PRE_REF5_MASK)
+#define XCVR_PHY_PHY_FSK_PD_CFG0_PHY_CLK_ON_MASK (0x80000000U)
+#define XCVR_PHY_PHY_FSK_PD_CFG0_PHY_CLK_ON_SHIFT (31U)
+#define XCVR_PHY_PHY_FSK_PD_CFG0_PHY_CLK_ON(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG0_PHY_CLK_ON_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG0_PHY_CLK_ON_MASK)
+/*! @} */
+
+/*! @name PHY_FSK_PD_CFG1 - Preamble Detect Config 1 */
+/*! @{ */
+#define XCVR_PHY_PHY_FSK_PD_CFG1_PRE_REF6_MASK   (0x1FU)
+#define XCVR_PHY_PHY_FSK_PD_CFG1_PRE_REF6_SHIFT  (0U)
+#define XCVR_PHY_PHY_FSK_PD_CFG1_PRE_REF6(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG1_PRE_REF6_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG1_PRE_REF6_MASK)
+#define XCVR_PHY_PHY_FSK_PD_CFG1_PRE_REF7_MASK   (0x3E0U)
+#define XCVR_PHY_PHY_FSK_PD_CFG1_PRE_REF7_SHIFT  (5U)
+#define XCVR_PHY_PHY_FSK_PD_CFG1_PRE_REF7(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG1_PRE_REF7_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG1_PRE_REF7_MASK)
+#define XCVR_PHY_PHY_FSK_PD_CFG1_PD_TIMEOUT_MASK (0x7C00U)
+#define XCVR_PHY_PHY_FSK_PD_CFG1_PD_TIMEOUT_SHIFT (10U)
+#define XCVR_PHY_PHY_FSK_PD_CFG1_PD_TIMEOUT(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG1_PD_TIMEOUT_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG1_PD_TIMEOUT_MASK)
+#define XCVR_PHY_PHY_FSK_PD_CFG1_PD_THRESH_MASK  (0xFF0000U)
+#define XCVR_PHY_PHY_FSK_PD_CFG1_PD_THRESH_SHIFT (16U)
+#define XCVR_PHY_PHY_FSK_PD_CFG1_PD_THRESH(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG1_PD_THRESH_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG1_PD_THRESH_MASK)
+#define XCVR_PHY_PHY_FSK_PD_CFG1_PD_FREQ_THRESH_MASK (0xFE000000U)
+#define XCVR_PHY_PHY_FSK_PD_CFG1_PD_FREQ_THRESH_SHIFT (25U)
+#define XCVR_PHY_PHY_FSK_PD_CFG1_PD_FREQ_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_PD_CFG1_PD_FREQ_THRESH_SHIFT)) & XCVR_PHY_PHY_FSK_PD_CFG1_PD_FREQ_THRESH_MASK)
+/*! @} */
+
+/*! @name PHY_FSK_CFG - PHY Configuration */
+/*! @{ */
+#define XCVR_PHY_PHY_FSK_CFG_AA_PLAYBACK_MASK    (0x1U)
+#define XCVR_PHY_PHY_FSK_CFG_AA_PLAYBACK_SHIFT   (0U)
+/*! AA_PLAYBACK
+ *  0b0..PHY will only output bits after the AA.
+ *  0b1..PHY will output the AA, followed by the rest of the packet bits.
+ */
+#define XCVR_PHY_PHY_FSK_CFG_AA_PLAYBACK(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_AA_PLAYBACK_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_AA_PLAYBACK_MASK)
+#define XCVR_PHY_PHY_FSK_CFG_AA_OUT_SEL_MASK     (0x2U)
+#define XCVR_PHY_PHY_FSK_CFG_AA_OUT_SEL_SHIFT    (1U)
+/*! AA_OUT_SEL
+ *  0b0..When AA playback is enabled, play back desired AA.
+ *  0b1..When AA playback is enabled, play back received AA.
+ */
+#define XCVR_PHY_PHY_FSK_CFG_AA_OUT_SEL(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_AA_OUT_SEL_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_AA_OUT_SEL_MASK)
+#define XCVR_PHY_PHY_FSK_CFG_FSK_BIT_INVERT_MASK (0x4U)
+#define XCVR_PHY_PHY_FSK_CFG_FSK_BIT_INVERT_SHIFT (2U)
+/*! FSK_BIT_INVERT
+ *  0b0..Normal demodulation.
+ *  0b1..Invert demodulated bits. This applies at the demodulator, so it affects both AA and the data portions of the packet.
+ */
+#define XCVR_PHY_PHY_FSK_CFG_FSK_BIT_INVERT(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_FSK_BIT_INVERT_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_FSK_BIT_INVERT_MASK)
+#define XCVR_PHY_PHY_FSK_CFG_BSM_EN_BLE_MASK     (0x8U)
+#define XCVR_PHY_PHY_FSK_CFG_BSM_EN_BLE_SHIFT    (3U)
+#define XCVR_PHY_PHY_FSK_CFG_BSM_EN_BLE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_BSM_EN_BLE_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_BSM_EN_BLE_MASK)
+#define XCVR_PHY_PHY_FSK_CFG_AA_CORR_GAIN_MASK   (0x3F0U)
+#define XCVR_PHY_PHY_FSK_CFG_AA_CORR_GAIN_SHIFT  (4U)
+#define XCVR_PHY_PHY_FSK_CFG_AA_CORR_GAIN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_AA_CORR_GAIN_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_AA_CORR_GAIN_MASK)
+#define XCVR_PHY_PHY_FSK_CFG_PDB_CONF_EN_MASK    (0x400U)
+#define XCVR_PHY_PHY_FSK_CFG_PDB_CONF_EN_SHIFT   (10U)
+#define XCVR_PHY_PHY_FSK_CFG_PDB_CONF_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_PDB_CONF_EN_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_PDB_CONF_EN_MASK)
+#define XCVR_PHY_PHY_FSK_CFG_PDA_CONF_EN_MASK    (0x800U)
+#define XCVR_PHY_PHY_FSK_CFG_PDA_CONF_EN_SHIFT   (11U)
+#define XCVR_PHY_PHY_FSK_CFG_PDA_CONF_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_PDA_CONF_EN_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_PDA_CONF_EN_MASK)
+#define XCVR_PHY_PHY_FSK_CFG_DEMOD_TIMEOUT_MASK  (0x3F000U)
+#define XCVR_PHY_PHY_FSK_CFG_DEMOD_TIMEOUT_SHIFT (12U)
+#define XCVR_PHY_PHY_FSK_CFG_DEMOD_TIMEOUT(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_DEMOD_TIMEOUT_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_DEMOD_TIMEOUT_MASK)
+#define XCVR_PHY_PHY_FSK_CFG_PDB_COMP_EN_MASK    (0x40000U)
+#define XCVR_PHY_PHY_FSK_CFG_PDB_COMP_EN_SHIFT   (18U)
+#define XCVR_PHY_PHY_FSK_CFG_PDB_COMP_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_PDB_COMP_EN_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_PDB_COMP_EN_MASK)
+#define XCVR_PHY_PHY_FSK_CFG_PDA_COMP_EN_MASK    (0x80000U)
+#define XCVR_PHY_PHY_FSK_CFG_PDA_COMP_EN_SHIFT   (19U)
+#define XCVR_PHY_PHY_FSK_CFG_PDA_COMP_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_PDA_COMP_EN_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_PDA_COMP_EN_MASK)
+#define XCVR_PHY_PHY_FSK_CFG_BLE_NTW_ADR_THR_MASK (0x700000U)
+#define XCVR_PHY_PHY_FSK_CFG_BLE_NTW_ADR_THR_SHIFT (20U)
+#define XCVR_PHY_PHY_FSK_CFG_BLE_NTW_ADR_THR(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_BLE_NTW_ADR_THR_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_BLE_NTW_ADR_THR_MASK)
+#define XCVR_PHY_PHY_FSK_CFG_PD_LAT_BASE_MASK    (0x7800000U)
+#define XCVR_PHY_PHY_FSK_CFG_PD_LAT_BASE_SHIFT   (23U)
+#define XCVR_PHY_PHY_FSK_CFG_PD_LAT_BASE(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_PD_LAT_BASE_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_PD_LAT_BASE_MASK)
+#define XCVR_PHY_PHY_FSK_CFG_PD_MODE_SW_EN_MASK  (0x8000000U)
+#define XCVR_PHY_PHY_FSK_CFG_PD_MODE_SW_EN_SHIFT (27U)
+#define XCVR_PHY_PHY_FSK_CFG_PD_MODE_SW_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_PD_MODE_SW_EN_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_PD_MODE_SW_EN_MASK)
+#define XCVR_PHY_PHY_FSK_CFG_PD_MODE_A_MASK      (0x30000000U)
+#define XCVR_PHY_PHY_FSK_CFG_PD_MODE_A_SHIFT     (28U)
+/*! PD_MODE_A
+ *  0b10..PD mode 2, pattern based preamble detection.
+ *  0b11..PD mode 3, peak based preamble detection.
+ */
+#define XCVR_PHY_PHY_FSK_CFG_PD_MODE_A(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_PD_MODE_A_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_PD_MODE_A_MASK)
+#define XCVR_PHY_PHY_FSK_CFG_PD_MODE_B_MASK      (0xC0000000U)
+#define XCVR_PHY_PHY_FSK_CFG_PD_MODE_B_SHIFT     (30U)
+/*! PD_MODE_B
+ *  0b10..PD mode 2, pattern based preamble detection.
+ *  0b11..PD mode 3, peak based preamble detection.
+ */
+#define XCVR_PHY_PHY_FSK_CFG_PD_MODE_B(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_CFG_PD_MODE_B_SHIFT)) & XCVR_PHY_PHY_FSK_CFG_PD_MODE_B_MASK)
+/*! @} */
+
+/*! @name PHY_FSK_MISC - PHY Misc. Configuration */
+/*! @{ */
+#define XCVR_PHY_PHY_FSK_MISC_FORCE_AA_MASK      (0x1U)
+#define XCVR_PHY_PHY_FSK_MISC_FORCE_AA_SHIFT     (0U)
+#define XCVR_PHY_PHY_FSK_MISC_FORCE_AA(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_MISC_FORCE_AA_SHIFT)) & XCVR_PHY_PHY_FSK_MISC_FORCE_AA_MASK)
+#define XCVR_PHY_PHY_FSK_MISC_EL_EN_MASK         (0x2U)
+#define XCVR_PHY_PHY_FSK_MISC_EL_EN_SHIFT        (1U)
+#define XCVR_PHY_PHY_FSK_MISC_EL_EN(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_MISC_EL_EN_SHIFT)) & XCVR_PHY_PHY_FSK_MISC_EL_EN_MASK)
+#define XCVR_PHY_PHY_FSK_MISC_EL_WIN_SZ_MASK     (0xF0U)
+#define XCVR_PHY_PHY_FSK_MISC_EL_WIN_SZ_SHIFT    (4U)
+#define XCVR_PHY_PHY_FSK_MISC_EL_WIN_SZ(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_MISC_EL_WIN_SZ_SHIFT)) & XCVR_PHY_PHY_FSK_MISC_EL_WIN_SZ_MASK)
+#define XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL_MASK   (0x3F00U)
+#define XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL_SHIFT  (8U)
+#define XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL_SHIFT)) & XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL_MASK)
+#define XCVR_PHY_PHY_FSK_MISC_MSK_EN_MASK        (0x4000U)
+#define XCVR_PHY_PHY_FSK_MISC_MSK_EN_SHIFT       (14U)
+#define XCVR_PHY_PHY_FSK_MISC_MSK_EN(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_MISC_MSK_EN_SHIFT)) & XCVR_PHY_PHY_FSK_MISC_MSK_EN_MASK)
+#define XCVR_PHY_PHY_FSK_MISC_PD_THRESH_B_MASK   (0xFF0000U)
+#define XCVR_PHY_PHY_FSK_MISC_PD_THRESH_B_SHIFT  (16U)
+#define XCVR_PHY_PHY_FSK_MISC_PD_THRESH_B(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_MISC_PD_THRESH_B_SHIFT)) & XCVR_PHY_PHY_FSK_MISC_PD_THRESH_B_MASK)
+#define XCVR_PHY_PHY_FSK_MISC_FIFO_PRE_CHARGE_MASK (0xF000000U)
+#define XCVR_PHY_PHY_FSK_MISC_FIFO_PRE_CHARGE_SHIFT (24U)
+#define XCVR_PHY_PHY_FSK_MISC_FIFO_PRE_CHARGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_MISC_FIFO_PRE_CHARGE_SHIFT)) & XCVR_PHY_PHY_FSK_MISC_FIFO_PRE_CHARGE_MASK)
+#define XCVR_PHY_PHY_FSK_MISC_CLK_CTRL_MASK      (0xF0000000U)
+#define XCVR_PHY_PHY_FSK_MISC_CLK_CTRL_SHIFT     (28U)
+/*! CLK_CTRL
+ *  0b0001..Gate off PHY clock when phy_en is not asserted.
+ *  0b0010..Gate off preamble detect clock when pd_enable is not asserted (internal signal).
+ *  0b0100..Gate off AA synchronizer clock when synchronizer is not in use.
+ *  0b1000..Gate off demodulator clock when demodulator is not in use.
+ */
+#define XCVR_PHY_PHY_FSK_MISC_CLK_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_MISC_CLK_CTRL_SHIFT)) & XCVR_PHY_PHY_FSK_MISC_CLK_CTRL_MASK)
+/*! @} */
+
+/*! @name NTW_ADR_BSM - PHY BSM Network Address */
+/*! @{ */
+#define XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM_MASK    (0xFFFFFFFFU)
+#define XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM_SHIFT   (0U)
+#define XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM_SHIFT)) & XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM_MASK)
+/*! @} */
+
+/*! @name FSK_STAT - PHY Status */
+/*! @{ */
+#define XCVR_PHY_FSK_STAT_PREAMBLE_FOUND_MASK    (0x1U)
+#define XCVR_PHY_FSK_STAT_PREAMBLE_FOUND_SHIFT   (0U)
+#define XCVR_PHY_FSK_STAT_PREAMBLE_FOUND(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_STAT_PREAMBLE_FOUND_SHIFT)) & XCVR_PHY_FSK_STAT_PREAMBLE_FOUND_MASK)
+#define XCVR_PHY_FSK_STAT_AA_MATCHED_MASK        (0x2U)
+#define XCVR_PHY_FSK_STAT_AA_MATCHED_SHIFT       (1U)
+#define XCVR_PHY_FSK_STAT_AA_MATCHED(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_STAT_AA_MATCHED_SHIFT)) & XCVR_PHY_FSK_STAT_AA_MATCHED_MASK)
+#define XCVR_PHY_FSK_STAT_AA_MATCH_MASK          (0xF0U)
+#define XCVR_PHY_FSK_STAT_AA_MATCH_SHIFT         (4U)
+#define XCVR_PHY_FSK_STAT_AA_MATCH(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_STAT_AA_MATCH_SHIFT)) & XCVR_PHY_FSK_STAT_AA_MATCH_MASK)
+#define XCVR_PHY_FSK_STAT_HAMM_DIST_MASK         (0xF00U)
+#define XCVR_PHY_FSK_STAT_HAMM_DIST_SHIFT        (8U)
+#define XCVR_PHY_FSK_STAT_HAMM_DIST(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_STAT_HAMM_DIST_SHIFT)) & XCVR_PHY_FSK_STAT_HAMM_DIST_MASK)
+#define XCVR_PHY_FSK_STAT_CFO_EST_MASK           (0xFF0000U)
+#define XCVR_PHY_FSK_STAT_CFO_EST_SHIFT          (16U)
+#define XCVR_PHY_FSK_STAT_CFO_EST(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_STAT_CFO_EST_SHIFT)) & XCVR_PHY_FSK_STAT_CFO_EST_MASK)
+#define XCVR_PHY_FSK_STAT_TOF_OFF_MASK           (0xF000000U)
+#define XCVR_PHY_FSK_STAT_TOF_OFF_SHIFT          (24U)
+#define XCVR_PHY_FSK_STAT_TOF_OFF(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_STAT_TOF_OFF_SHIFT)) & XCVR_PHY_FSK_STAT_TOF_OFF_MASK)
+/*! @} */
+
+/*! @name FSK_FAD_CTRL - PHY FAD control */
+/*! @{ */
+#define XCVR_PHY_FSK_FAD_CTRL_FAD_EN_MASK        (0x1U)
+#define XCVR_PHY_FSK_FAD_CTRL_FAD_EN_SHIFT       (0U)
+#define XCVR_PHY_FSK_FAD_CTRL_FAD_EN(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_FAD_CTRL_FAD_EN_SHIFT)) & XCVR_PHY_FSK_FAD_CTRL_FAD_EN_MASK)
+#define XCVR_PHY_FSK_FAD_CTRL_FAD_PROC_DUR_MASK  (0x7F0U)
+#define XCVR_PHY_FSK_FAD_CTRL_FAD_PROC_DUR_SHIFT (4U)
+#define XCVR_PHY_FSK_FAD_CTRL_FAD_PROC_DUR(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_FAD_CTRL_FAD_PROC_DUR_SHIFT)) & XCVR_PHY_FSK_FAD_CTRL_FAD_PROC_DUR_MASK)
+#define XCVR_PHY_FSK_FAD_CTRL_FAD_PROC_DLY_MASK  (0x7F000U)
+#define XCVR_PHY_FSK_FAD_CTRL_FAD_PROC_DLY_SHIFT (12U)
+#define XCVR_PHY_FSK_FAD_CTRL_FAD_PROC_DLY(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_FAD_CTRL_FAD_PROC_DLY_SHIFT)) & XCVR_PHY_FSK_FAD_CTRL_FAD_PROC_DLY_MASK)
+#define XCVR_PHY_FSK_FAD_CTRL_FAD_THRESH_MASK    (0xFF00000U)
+#define XCVR_PHY_FSK_FAD_CTRL_FAD_THRESH_SHIFT   (20U)
+#define XCVR_PHY_FSK_FAD_CTRL_FAD_THRESH(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_FAD_CTRL_FAD_THRESH_SHIFT)) & XCVR_PHY_FSK_FAD_CTRL_FAD_THRESH_MASK)
+#define XCVR_PHY_FSK_FAD_CTRL_PHY_DBG_CFG_MASK   (0xF0000000U)
+#define XCVR_PHY_FSK_FAD_CTRL_PHY_DBG_CFG_SHIFT  (28U)
+#define XCVR_PHY_FSK_FAD_CTRL_PHY_DBG_CFG(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_FSK_FAD_CTRL_PHY_DBG_CFG_SHIFT)) & XCVR_PHY_FSK_FAD_CTRL_PHY_DBG_CFG_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group XCVR_PHY_Register_Masks */
+
+
+/* XCVR_PHY - Peripheral instance base addresses */
+/** Peripheral XCVR_PHY base address */
+#define XCVR_PHY_BASE                            (0x41030400u)
+/** Peripheral XCVR_PHY base pointer */
+#define XCVR_PHY                                 ((XCVR_PHY_Type *)XCVR_PHY_BASE)
+/** Array initializer of XCVR_PHY peripheral base addresses */
+#define XCVR_PHY_BASE_ADDRS                      { XCVR_PHY_BASE }
+/** Array initializer of XCVR_PHY peripheral base pointers */
+#define XCVR_PHY_BASE_PTRS                       { XCVR_PHY }
+
+/*!
+ * @}
+ */ /* end of group XCVR_PHY_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- XCVR_PKT_RAM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XCVR_PKT_RAM_Peripheral_Access_Layer XCVR_PKT_RAM Peripheral Access Layer
+ * @{
+ */
+
+/** XCVR_PKT_RAM - Register Layout Typedef */
+typedef struct {
+  __IO uint16_t PACKET_RAM[1152];                  /**< Shared Packet RAM for multiple Link Layer usage., array offset: 0x0, array step: 0x2 */
+} XCVR_PKT_RAM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- XCVR_PKT_RAM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XCVR_PKT_RAM_Register_Masks XCVR_PKT_RAM Register Masks
+ * @{
+ */
+
+/*! @name PACKET_RAM - Shared Packet RAM for multiple Link Layer usage. */
+/*! @{ */
+#define XCVR_PKT_RAM_PACKET_RAM_LSBYTE_MASK      (0xFFU)
+#define XCVR_PKT_RAM_PACKET_RAM_LSBYTE_SHIFT     (0U)
+#define XCVR_PKT_RAM_PACKET_RAM_LSBYTE(x)        (((uint16_t)(((uint16_t)(x)) << XCVR_PKT_RAM_PACKET_RAM_LSBYTE_SHIFT)) & XCVR_PKT_RAM_PACKET_RAM_LSBYTE_MASK)
+#define XCVR_PKT_RAM_PACKET_RAM_MSBYTE_MASK      (0xFF00U)
+#define XCVR_PKT_RAM_PACKET_RAM_MSBYTE_SHIFT     (8U)
+#define XCVR_PKT_RAM_PACKET_RAM_MSBYTE(x)        (((uint16_t)(((uint16_t)(x)) << XCVR_PKT_RAM_PACKET_RAM_MSBYTE_SHIFT)) & XCVR_PKT_RAM_PACKET_RAM_MSBYTE_MASK)
+/*! @} */
+
+/* The count of XCVR_PKT_RAM_PACKET_RAM */
+#define XCVR_PKT_RAM_PACKET_RAM_COUNT            (1152U)
+
+
+/*!
+ * @}
+ */ /* end of group XCVR_PKT_RAM_Register_Masks */
+
+
+/* XCVR_PKT_RAM - Peripheral instance base addresses */
+/** Peripheral XCVR_PKT_RAM base address */
+#define XCVR_PKT_RAM_BASE                        (0x41030700u)
+/** Peripheral XCVR_PKT_RAM base pointer */
+#define XCVR_PKT_RAM                             ((XCVR_PKT_RAM_Type *)XCVR_PKT_RAM_BASE)
+/** Array initializer of XCVR_PKT_RAM peripheral base addresses */
+#define XCVR_PKT_RAM_BASE_ADDRS                  { XCVR_PKT_RAM_BASE }
+/** Array initializer of XCVR_PKT_RAM peripheral base pointers */
+#define XCVR_PKT_RAM_BASE_PTRS                   { XCVR_PKT_RAM }
+
+/*!
+ * @}
+ */ /* end of group XCVR_PKT_RAM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- XCVR_PLL_DIG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XCVR_PLL_DIG_Peripheral_Access_Layer XCVR_PLL_DIG Peripheral Access Layer
+ * @{
+ */
+
+/** XCVR_PLL_DIG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t HPM_BUMP;                          /**< PLL HPM Analog Bump Control, offset: 0x0 */
+  __IO uint32_t MOD_CTRL;                          /**< PLL Modulation Control, offset: 0x4 */
+  __IO uint32_t CHAN_MAP;                          /**< PLL Channel Mapping, offset: 0x8 */
+  __IO uint32_t LOCK_DETECT;                       /**< PLL Lock Detect Control, offset: 0xC */
+  __IO uint32_t HPM_CTRL;                          /**< PLL High Port Modulator Control, offset: 0x10 */
+       uint8_t RESERVED_0[12];
+  __IO uint32_t HPM_SDM_RES;                       /**< PLL High Port Sigma Delta Results, offset: 0x20 */
+  __IO uint32_t LPM_CTRL;                          /**< PLL Low Port Modulator Control, offset: 0x24 */
+  __IO uint32_t LPM_SDM_CTRL1;                     /**< PLL Low Port Sigma Delta Control 1, offset: 0x28 */
+  __IO uint32_t LPM_SDM_CTRL2;                     /**< PLL Low Port Sigma Delta Control 2, offset: 0x2C */
+  __IO uint32_t LPM_SDM_CTRL3;                     /**< PLL Low Port Sigma Delta Control 3, offset: 0x30 */
+  __I  uint32_t LPM_SDM_RES1;                      /**< PLL Low Port Sigma Delta Result 1, offset: 0x34 */
+  __I  uint32_t LPM_SDM_RES2;                      /**< PLL Low Port Sigma Delta Result 2, offset: 0x38 */
+  __IO uint32_t DELAY_MATCH;                       /**< PLL Delay Matching, offset: 0x3C */
+  __IO uint32_t CTUNE_CTRL;                        /**< PLL Coarse Tune Control, offset: 0x40 */
+       uint8_t RESERVED_1[16];
+  __I  uint32_t CTUNE_RES;                         /**< PLL Coarse Tune Results, offset: 0x54 */
+} XCVR_PLL_DIG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- XCVR_PLL_DIG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XCVR_PLL_DIG_Register_Masks XCVR_PLL_DIG Register Masks
+ * @{
+ */
+
+/*! @name HPM_BUMP - PLL HPM Analog Bump Control */
+/*! @{ */
+#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_MASK    (0x7U)
+#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_SHIFT   (0U)
+/*! HPM_VCM_TX - rfctrl_tx_dac_bump_vcm[2:0] during Transmission
+ *  0b000..432 mV
+ *  0b001..328 mV
+ *  0b010..456 mV
+ *  0b011..473 mV
+ *  0b100..488 mV
+ *  0b101..408 mV
+ *  0b110..392 mV
+ *  0b111..376 mV
+ */
+#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_MASK)
+#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_MASK   (0x70U)
+#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_SHIFT  (4U)
+/*! HPM_VCM_CAL - rfctrl_tx_dac_bump_vcm[2:0] during Calibration
+ *  0b000..432 mV
+ *  0b001..328 mV
+ *  0b010..456 mV
+ *  0b011..473 mV
+ *  0b100..488 mV
+ *  0b101..408 mV
+ *  0b110..392 mV
+ *  0b111..376 mV
+ */
+#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_MASK)
+#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_MASK (0x300U)
+#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_SHIFT (8U)
+/*! HPM_FDB_RES_TX - rfctrl_tx_dac_bump_fdb_res[1:0] during Transmission
+ *  0b00..29 kohms
+ *  0b01..58 kohms(gain of 2)
+ *  0b10..13 kohms
+ *  0b11..23.7 kohms
+ */
+#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_MASK)
+#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_MASK (0x3000U)
+#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_SHIFT (12U)
+/*! HPM_FDB_RES_CAL - rfctrl_tx_dac_bump_fdb_res[1:0] during Calibration
+ *  0b00..29 kohms
+ *  0b01..58 kohms(gain of 2)
+ *  0b10..13 kohms
+ *  0b11..23.7 kohms
+ */
+#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_MASK)
+/*! @} */
+
+/*! @name MOD_CTRL - PLL Modulation Control */
+/*! @{ */
+#define XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_MASK (0x1FFFU)
+#define XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_SHIFT (0U)
+#define XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_MASK)
+#define XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_MASK   (0x8000U)
+#define XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_SHIFT  (15U)
+#define XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_MASK)
+#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_MASK (0xFF0000U)
+#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_SHIFT (16U)
+#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_MASK)
+#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_MASK (0x8000000U)
+#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_SHIFT (27U)
+#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_MASK)
+#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_MASK (0x30000000U)
+#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_SHIFT (28U)
+#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_MASK)
+#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_MASK (0x80000000U)
+#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_SHIFT (31U)
+#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_MASK)
+/*! @} */
+
+/*! @name CHAN_MAP - PLL Channel Mapping */
+/*! @{ */
+#define XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK   (0x7FU)
+#define XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_SHIFT  (0U)
+#define XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK)
+#define XCVR_PLL_DIG_CHAN_MAP_BOC_MASK           (0x100U)
+#define XCVR_PLL_DIG_CHAN_MAP_BOC_SHIFT          (8U)
+/*! BOC - BLE Channel Number Override
+ *  0b0..BLE channel number comes from the BLE Link Layer
+ *  0b1..BLE channel number comes from the CHANNEL_NUM register (BLE protocols 0 and 2)
+ */
+#define XCVR_PLL_DIG_CHAN_MAP_BOC(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_BOC_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_BOC_MASK)
+#define XCVR_PLL_DIG_CHAN_MAP_BMR_MASK           (0x200U)
+#define XCVR_PLL_DIG_CHAN_MAP_BMR_SHIFT          (9U)
+/*! BMR - BLE MBAN Channel Remap
+ *  0b0..BLE channel 39 is mapped to BLE channel 39, 2.480 GHz
+ *  0b1..BLE channel 39 is mapped to MBAN channel 39, 2.399 GHz
+ */
+#define XCVR_PLL_DIG_CHAN_MAP_BMR(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_BMR_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_BMR_MASK)
+#define XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK           (0x400U)
+#define XCVR_PLL_DIG_CHAN_MAP_ZOC_SHIFT          (10U)
+/*! ZOC - 802.15.4 Channel Number Override
+ *  0b0..802.15.4 channel number comes from the 802.15.4 Link Layer.
+ *  0b1..802.15.4 channel number comes from the CHANNEL_NUM register (802.15.4 protocols 4 and 5)
+ */
+#define XCVR_PLL_DIG_CHAN_MAP_ZOC(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_ZOC_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK)
+#define XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_MASK (0x70000U)
+#define XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_SHIFT (16U)
+/*! HOP_TBL_CFG_OVRD - Hop Table Configuration Override
+ *  0b010..DFT_PATTERN[15:7] is signed offset to DFT_PATTERN[6:0] mapped channel number
+ *  0b011..DFT_PATTERN[15:1] is signed Numerator, DFT_PATTERN[0] is integer selection
+ */
+#define XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_MASK)
+#define XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_MASK (0x80000U)
+#define XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_SHIFT (19U)
+#define XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_MASK)
+/*! @} */
+
+/*! @name LOCK_DETECT - PLL Lock Detect Control */
+/*! @{ */
+#define XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_MASK    (0x1U)
+#define XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_SHIFT   (0U)
+#define XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_MASK)
+#define XCVR_PLL_DIG_LOCK_DETECT_CTFF_MASK       (0x2U)
+#define XCVR_PLL_DIG_LOCK_DETECT_CTFF_SHIFT      (1U)
+#define XCVR_PLL_DIG_LOCK_DETECT_CTFF(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CTFF_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CTFF_MASK)
+#define XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL_MASK    (0x4U)
+#define XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL_SHIFT   (2U)
+#define XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL_MASK)
+#define XCVR_PLL_DIG_LOCK_DETECT_CSFF_MASK       (0x8U)
+#define XCVR_PLL_DIG_LOCK_DETECT_CSFF_SHIFT      (3U)
+#define XCVR_PLL_DIG_LOCK_DETECT_CSFF(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CSFF_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CSFF_MASK)
+#define XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_MASK    (0x10U)
+#define XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_SHIFT   (4U)
+#define XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_MASK)
+#define XCVR_PLL_DIG_LOCK_DETECT_FTFF_MASK       (0x20U)
+#define XCVR_PLL_DIG_LOCK_DETECT_FTFF_SHIFT      (5U)
+#define XCVR_PLL_DIG_LOCK_DETECT_FTFF(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTFF_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTFF_MASK)
+#define XCVR_PLL_DIG_LOCK_DETECT_TAFF_MASK       (0x80U)
+#define XCVR_PLL_DIG_LOCK_DETECT_TAFF_SHIFT      (7U)
+#define XCVR_PLL_DIG_LOCK_DETECT_TAFF(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_TAFF_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_TAFF_MASK)
+#define XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_MASK (0xF00U)
+#define XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_SHIFT (8U)
+#define XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_MASK)
+#define XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_MASK (0x3F000U)
+#define XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_SHIFT (12U)
+#define XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_MASK)
+#define XCVR_PLL_DIG_LOCK_DETECT_FTW_RX_MASK     (0x80000U)
+#define XCVR_PLL_DIG_LOCK_DETECT_FTW_RX_SHIFT    (19U)
+/*! FTW_RX - RX Frequency Target Window time select
+ *  0b0..4 us
+ *  0b1..8 us
+ */
+#define XCVR_PLL_DIG_LOCK_DETECT_FTW_RX(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTW_RX_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTW_RX_MASK)
+#define XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_MASK (0x3F00000U)
+#define XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_SHIFT (20U)
+#define XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_MASK)
+#define XCVR_PLL_DIG_LOCK_DETECT_FTW_TX_MASK     (0x8000000U)
+#define XCVR_PLL_DIG_LOCK_DETECT_FTW_TX_SHIFT    (27U)
+/*! FTW_TX - TX Frequency Target Window time select
+ *  0b0..4 us
+ *  0b1..8 us
+ */
+#define XCVR_PLL_DIG_LOCK_DETECT_FTW_TX(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTW_TX_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTW_TX_MASK)
+#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_MASK (0x10000000U)
+#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_SHIFT (28U)
+#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_MASK)
+#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_MASK (0x20000000U)
+#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_SHIFT (29U)
+#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_MASK)
+#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_MASK (0xC0000000U)
+#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_SHIFT (30U)
+/*! FREQ_COUNT_TIME - Frequency Meter Count Time
+ *  0b00..800 us
+ *  0b01..25 us
+ *  0b10..50 us
+ *  0b11..100 us
+ */
+#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_MASK)
+/*! @} */
+
+/*! @name HPM_CTRL - PLL High Port Modulator Control */
+/*! @{ */
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_MASK (0x3FFU)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_SHIFT (0U)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_MASK)
+#define XCVR_PLL_DIG_HPM_CTRL_HPFF_MASK          (0x2000U)
+#define XCVR_PLL_DIG_HPM_CTRL_HPFF_SHIFT         (13U)
+#define XCVR_PLL_DIG_HPM_CTRL_HPFF(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPFF_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPFF_MASK)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_MASK (0x4000U)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_SHIFT (14U)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_MASK)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_MASK (0x8000U)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_SHIFT (15U)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_MASK)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_MASK (0x70000U)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_SHIFT (16U)
+/*! HPM_LFSR_SIZE - HPM LFSR Length
+ *  0b000..LFSR 9, tap mask 100010000
+ *  0b001..LFSR 10, tap mask 1001000000
+ *  0b010..LFSR 11, tap mask 11101000000
+ *  0b011..LFSR 13, tap mask 1101100000000
+ *  0b100..LFSR 15, tap mask 111010000000000
+ *  0b101..LFSR 17, tap mask 11110000000000000
+ *  0b110..Reserved
+ *  0b111..Reserved
+ */
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_MASK)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_MASK   (0x100000U)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_SHIFT  (20U)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_MASK)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_MASK    (0x800000U)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_SHIFT   (23U)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_MASK)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE_MASK (0x3000000U)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE_SHIFT (24U)
+/*! HPM_INTEGER_SCALE - High Port Modulation Integer Scale
+ *  0b00..No Scaling
+ *  0b01..Multiply by 2
+ *  0b10..Divide by 2
+ *  0b11..Reserved
+ */
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE_MASK)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_MASK (0x8000000U)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_SHIFT (27U)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_MASK)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_MASK (0x10000000U)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_SHIFT (28U)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_MASK)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_MASK (0x80000000U)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_SHIFT (31U)
+#define XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_MASK)
+/*! @} */
+
+/*! @name HPM_SDM_RES - PLL High Port Sigma Delta Results */
+/*! @{ */
+#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_MASK (0x3FFU)
+#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_SHIFT (0U)
+#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_SHIFT)) & XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_MASK)
+#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_MASK  (0x3FF0000U)
+#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_SHIFT (16U)
+#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_SHIFT)) & XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_MASK)
+#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_MASK (0xF0000000U)
+#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_SHIFT (28U)
+#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_SHIFT)) & XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_MASK)
+/*! @} */
+
+/*! @name LPM_CTRL - PLL Low Port Modulator Control */
+/*! @{ */
+#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_MASK (0x1FU)
+#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_SHIFT (0U)
+#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_MASK)
+#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_MASK (0x800U)
+#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_SHIFT (11U)
+#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_MASK)
+#define XCVR_PLL_DIG_LPM_CTRL_LPFF_MASK          (0x2000U)
+#define XCVR_PLL_DIG_LPM_CTRL_LPFF_SHIFT         (13U)
+#define XCVR_PLL_DIG_LPM_CTRL_LPFF(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPFF_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPFF_MASK)
+#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_MASK   (0x4000U)
+#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_SHIFT  (14U)
+#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_MASK)
+#define XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_MASK   (0x8000U)
+#define XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_SHIFT  (15U)
+#define XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_MASK)
+#define XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_MASK   (0xF0000U)
+#define XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_SHIFT  (16U)
+/*! LPM_DTH_SCL - LPM Dither Scale
+ *  0b0000..Reserved
+ *  0b0001..Reserved
+ *  0b0010..Reserved
+ *  0b0011..Reserved
+ *  0b0100..Reserved
+ *  0b0101..-128 to 96
+ *  0b0110..-256 to 192
+ *  0b0111..-512 to 384
+ *  0b1000..-1024 to 768, this is the intended setting for normal operation.
+ *  0b1001..-2048 to 1536
+ *  0b1010..-4096 to 3072
+ *  0b1011..-8192 to 6144
+ *  0b1100..Reserved
+ *  0b1101..Reserved
+ *  0b1110..Reserved
+ *  0b1111..Reserved
+ */
+#define XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_MASK)
+#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_MASK    (0x400000U)
+#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_SHIFT   (22U)
+#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_MASK)
+#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_MASK    (0x800000U)
+#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_SHIFT   (23U)
+#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_MASK)
+#define XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_MASK     (0xF000000U)
+#define XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_SHIFT    (24U)
+/*! LPM_SCALE - LPM Scale Factor
+ *  0b0000..No Scaling
+ *  0b0001..Multiply by 2
+ *  0b0010..Multiply by 4
+ *  0b0011..Multiply by 8
+ *  0b0100..Multiply by 16
+ *  0b0101..Multiply by 32
+ *  0b0110..Multiply by 64
+ *  0b0111..Multiply by 128
+ *  0b1000..Multiply by 256, this is the intended setting for normal operation.
+ *  0b1001..Multiply by 512
+ *  0b1010..Multiply by 1024
+ *  0b1011..Multiply by 2048
+ *  0b1100..Reserved
+ *  0b1101..Reserved
+ *  0b1110..Reserved
+ *  0b1111..Reserved
+ */
+#define XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_MASK)
+#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_MASK (0x80000000U)
+#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_SHIFT (31U)
+#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_MASK)
+/*! @} */
+
+/*! @name LPM_SDM_CTRL1 - PLL Low Port Sigma Delta Control 1 */
+/*! @{ */
+#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_MASK (0x7FU)
+#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_SHIFT (0U)
+#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_MASK)
+#define XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_MASK (0x7F00U)
+#define XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_SHIFT (8U)
+#define XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_MASK)
+#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK (0x7F0000U)
+#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SHIFT (16U)
+#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK)
+#define XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK (0x80000000U)
+#define XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_SHIFT (31U)
+#define XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK)
+/*! @} */
+
+/*! @name LPM_SDM_CTRL2 - PLL Low Port Sigma Delta Control 2 */
+/*! @{ */
+#define XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_MASK  (0xFFFFFFFU)
+#define XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_SHIFT (0U)
+#define XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_MASK)
+/*! @} */
+
+/*! @name LPM_SDM_CTRL3 - PLL Low Port Sigma Delta Control 3 */
+/*! @{ */
+#define XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_MASK (0xFFFFFFFU)
+#define XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_SHIFT (0U)
+#define XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_MASK)
+/*! @} */
+
+/*! @name LPM_SDM_RES1 - PLL Low Port Sigma Delta Result 1 */
+/*! @{ */
+#define XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_MASK (0xFFFFFFFU)
+#define XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_SHIFT (0U)
+#define XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_MASK)
+/*! @} */
+
+/*! @name LPM_SDM_RES2 - PLL Low Port Sigma Delta Result 2 */
+/*! @{ */
+#define XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_MASK (0xFFFFFFFU)
+#define XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_SHIFT (0U)
+#define XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_MASK)
+/*! @} */
+
+/*! @name DELAY_MATCH - PLL Delay Matching */
+/*! @{ */
+#define XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_MASK (0xFU)
+#define XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_SHIFT (0U)
+#define XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_SHIFT)) & XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_MASK)
+#define XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_MASK (0xF00U)
+#define XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_SHIFT (8U)
+#define XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_SHIFT)) & XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_MASK)
+#define XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_MASK (0xF0000U)
+#define XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_SHIFT (16U)
+#define XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_SHIFT)) & XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_MASK)
+/*! @} */
+
+/*! @name CTUNE_CTRL - PLL Coarse Tune Control */
+/*! @{ */
+#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_MASK (0xFFFU)
+#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_SHIFT (0U)
+#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_MASK)
+#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_MASK (0x8000U)
+#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_SHIFT (15U)
+#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_MASK)
+#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_MASK (0xF0000U)
+#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_SHIFT (16U)
+#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_MASK)
+#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_MASK (0x7F000000U)
+#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_SHIFT (24U)
+#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_MASK)
+#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_MASK (0x80000000U)
+#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_SHIFT (31U)
+#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_MASK)
+/*! @} */
+
+/*! @name CTUNE_RES - PLL Coarse Tune Results */
+/*! @{ */
+#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_MASK (0x7FU)
+#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_SHIFT (0U)
+#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_SHIFT)) & XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_MASK)
+#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_MASK (0xFF00U)
+#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_SHIFT (8U)
+#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_SHIFT)) & XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_MASK)
+#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_MASK (0xFFF0000U)
+#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_SHIFT (16U)
+#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_SHIFT)) & XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group XCVR_PLL_DIG_Register_Masks */
+
+
+/* XCVR_PLL_DIG - Peripheral instance base addresses */
+/** Peripheral XCVR_PLL_DIG base address */
+#define XCVR_PLL_DIG_BASE                        (0x41030224u)
+/** Peripheral XCVR_PLL_DIG base pointer */
+#define XCVR_PLL_DIG                             ((XCVR_PLL_DIG_Type *)XCVR_PLL_DIG_BASE)
+/** Array initializer of XCVR_PLL_DIG peripheral base addresses */
+#define XCVR_PLL_DIG_BASE_ADDRS                  { XCVR_PLL_DIG_BASE }
+/** Array initializer of XCVR_PLL_DIG peripheral base pointers */
+#define XCVR_PLL_DIG_BASE_PTRS                   { XCVR_PLL_DIG }
+
+/*!
+ * @}
+ */ /* end of group XCVR_PLL_DIG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- XCVR_RX_DIG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XCVR_RX_DIG_Peripheral_Access_Layer XCVR_RX_DIG Peripheral Access Layer
+ * @{
+ */
+
+/** XCVR_RX_DIG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t RX_DIG_CTRL;                       /**< RX Digital Control, offset: 0x0 */
+  __IO uint32_t AGC_CTRL_0;                        /**< AGC Control 0, offset: 0x4 */
+  __IO uint32_t AGC_CTRL_1;                        /**< AGC Control 1, offset: 0x8 */
+  __IO uint32_t AGC_CTRL_2;                        /**< AGC Control 2, offset: 0xC */
+  __IO uint32_t AGC_CTRL_3;                        /**< AGC Control 3, offset: 0x10 */
+  __I  uint32_t AGC_STAT;                          /**< AGC Status, offset: 0x14 */
+  __IO uint32_t RSSI_CTRL_0;                       /**< RSSI Control 0, offset: 0x18 */
+  __IO uint32_t RSSI_CTRL_1;                       /**< RSSI Control 1, offset: 0x1C */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t DCOC_CTRL_0;                       /**< DCOC Control 0, offset: 0x24 */
+  __IO uint32_t DCOC_CTRL_1;                       /**< DCOC Control 1, offset: 0x28 */
+  __IO uint32_t DCOC_DAC_INIT;                     /**< DCOC DAC Initialization, offset: 0x2C */
+  __IO uint32_t DCOC_DIG_MAN;                      /**< DCOC Digital Correction Manual Override, offset: 0x30 */
+  __IO uint32_t DCOC_CAL_GAIN;                     /**< DCOC Calibration Gain, offset: 0x34 */
+  __I  uint32_t DCOC_STAT;                         /**< DCOC Status, offset: 0x38 */
+  __I  uint32_t DCOC_DC_EST;                       /**< DCOC DC Estimate, offset: 0x3C */
+  __IO uint32_t DCOC_CAL_RCP;                      /**< DCOC Calibration Reciprocals, offset: 0x40 */
+  __IO uint32_t DCOC_CTRL_2;                       /**< DCOC Control 2, offset: 0x44 */
+  __IO uint32_t IQMC_CTRL;                         /**< IQMC Control, offset: 0x48 */
+  __IO uint32_t IQMC_CAL;                          /**< IQMC Calibration, offset: 0x4C */
+  __IO uint32_t LNA_GAIN_VAL_3_0;                  /**< LNA_GAIN Step Values 3..0, offset: 0x50 */
+  __IO uint32_t LNA_GAIN_VAL_7_4;                  /**< LNA_GAIN Step Values 7..4, offset: 0x54 */
+  __IO uint32_t LNA_GAIN_VAL_8;                    /**< LNA_GAIN Step Values 8, offset: 0x58 */
+  __IO uint32_t BBA_RES_TUNE_VAL_7_0;              /**< BBA Resistor Tune Values 7..0, offset: 0x5C */
+  __IO uint32_t BBA_RES_TUNE_VAL_10_8;             /**< BBA Resistor Tune Values 10..8, offset: 0x60 */
+  __IO uint32_t LNA_GAIN_LIN_VAL_2_0;              /**< LNA Linear Gain Values 2..0, offset: 0x64 */
+  __IO uint32_t LNA_GAIN_LIN_VAL_5_3;              /**< LNA Linear Gain Values 5..3, offset: 0x68 */
+  __IO uint32_t LNA_GAIN_LIN_VAL_8_6;              /**< LNA Linear Gain Values 8..6, offset: 0x6C */
+  __IO uint32_t LNA_GAIN_LIN_VAL_9;                /**< LNA Linear Gain Values 9, offset: 0x70 */
+  __IO uint32_t BBA_RES_TUNE_LIN_VAL_3_0;          /**< BBA Resistor Tune Values 3..0, offset: 0x74 */
+  __IO uint32_t BBA_RES_TUNE_LIN_VAL_7_4;          /**< BBA Resistor Tune Values 7..4, offset: 0x78 */
+  __IO uint32_t BBA_RES_TUNE_LIN_VAL_10_8;         /**< BBA Resistor Tune Values 10..8, offset: 0x7C */
+  __IO uint32_t AGC_GAIN_TBL_03_00;                /**< AGC Gain Tables Step 03..00, offset: 0x80 */
+  __IO uint32_t AGC_GAIN_TBL_07_04;                /**< AGC Gain Tables Step 07..04, offset: 0x84 */
+  __IO uint32_t AGC_GAIN_TBL_11_08;                /**< AGC Gain Tables Step 11..08, offset: 0x88 */
+  __IO uint32_t AGC_GAIN_TBL_15_12;                /**< AGC Gain Tables Step 15..12, offset: 0x8C */
+  __IO uint32_t AGC_GAIN_TBL_19_16;                /**< AGC Gain Tables Step 19..16, offset: 0x90 */
+  __IO uint32_t AGC_GAIN_TBL_23_20;                /**< AGC Gain Tables Step 23..20, offset: 0x94 */
+  __IO uint32_t AGC_GAIN_TBL_26_24;                /**< AGC Gain Tables Step 26..24, offset: 0x98 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t DCOC_OFFSET[27];                   /**< DCOC Offset, array offset: 0xA0, array step: 0x4 */
+  __IO uint32_t DCOC_BBA_STEP;                     /**< DCOC BBA DAC Step, offset: 0x10C */
+  __IO uint32_t DCOC_TZA_STEP_0;                   /**< DCOC TZA DAC Step 0, offset: 0x110 */
+  __IO uint32_t DCOC_TZA_STEP_1;                   /**< DCOC TZA DAC Step 1, offset: 0x114 */
+  __IO uint32_t DCOC_TZA_STEP_2;                   /**< DCOC TZA DAC Step 2, offset: 0x118 */
+  __IO uint32_t DCOC_TZA_STEP_3;                   /**< DCOC TZA DAC Step 3, offset: 0x11C */
+  __IO uint32_t DCOC_TZA_STEP_4;                   /**< DCOC TZA DAC Step 4, offset: 0x120 */
+  __IO uint32_t DCOC_TZA_STEP_5;                   /**< DCOC TZA DAC Step 5, offset: 0x124 */
+  __IO uint32_t DCOC_TZA_STEP_6;                   /**< DCOC TZA DAC Step 6, offset: 0x128 */
+  __IO uint32_t DCOC_TZA_STEP_7;                   /**< DCOC TZA DAC Step 7, offset: 0x12C */
+  __IO uint32_t DCOC_TZA_STEP_8;                   /**< DCOC TZA DAC Step 5, offset: 0x130 */
+  __IO uint32_t DCOC_TZA_STEP_9;                   /**< DCOC TZA DAC Step 9, offset: 0x134 */
+  __IO uint32_t DCOC_TZA_STEP_10;                  /**< DCOC TZA DAC Step 10, offset: 0x138 */
+       uint8_t RESERVED_2[36];
+  __IO uint32_t DCOC_CAL_FAIL_TH;                  /**< DCOC Calibration Fail Thresholds, offset: 0x160 */
+  __IO uint32_t DCOC_CAL_PASS_TH;                  /**< DCOC Calibration Pass Thresholds, offset: 0x164 */
+  __I  uint32_t DCOC_CAL_ALPHA;                    /**< DCOC Calibration Alpha, offset: 0x168 */
+  __I  uint32_t DCOC_CAL_BETA_Q;                   /**< DCOC Calibration Beta Q, offset: 0x16C */
+  __I  uint32_t DCOC_CAL_BETA_I;                   /**< DCOC Calibration Beta I, offset: 0x170 */
+  __I  uint32_t DCOC_CAL_GAMMA;                    /**< DCOC Calibration Gamma, offset: 0x174 */
+  __IO uint32_t DCOC_CAL_IIR;                      /**< DCOC Calibration IIR, offset: 0x178 */
+       uint8_t RESERVED_3[4];
+  __I  uint32_t DCOC_CAL[3];                       /**< DCOC Calibration Result, array offset: 0x180, array step: 0x4 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t CCA_ED_LQI_CTRL_0;                 /**< RX_DIG CCA ED LQI Control Register 0, offset: 0x190 */
+  __IO uint32_t CCA_ED_LQI_CTRL_1;                 /**< RX_DIG CCA ED LQI Control Register 1, offset: 0x194 */
+  __I  uint32_t CCA_ED_LQI_STAT_0;                 /**< RX_DIG CCA ED LQI Status Register 0, offset: 0x198 */
+       uint8_t RESERVED_5[4];
+  __IO uint32_t RX_CHF_COEF_0;                     /**< Receive Channel Filter Coefficient 0, offset: 0x1A0 */
+  __IO uint32_t RX_CHF_COEF_1;                     /**< Receive Channel Filter Coefficient 1, offset: 0x1A4 */
+  __IO uint32_t RX_CHF_COEF_2;                     /**< Receive Channel Filter Coefficient 2, offset: 0x1A8 */
+  __IO uint32_t RX_CHF_COEF_3;                     /**< Receive Channel Filter Coefficient 3, offset: 0x1AC */
+  __IO uint32_t RX_CHF_COEF_4;                     /**< Receive Channel Filter Coefficient 4, offset: 0x1B0 */
+  __IO uint32_t RX_CHF_COEF_5;                     /**< Receive Channel Filter Coefficient 5, offset: 0x1B4 */
+  __IO uint32_t RX_CHF_COEF_6;                     /**< Receive Channel Filter Coefficient 6, offset: 0x1B8 */
+  __IO uint32_t RX_CHF_COEF_7;                     /**< Receive Channel Filter Coefficient 7, offset: 0x1BC */
+  __IO uint32_t RX_CHF_COEF_8;                     /**< Receive Channel Filter Coefficient 8, offset: 0x1C0 */
+  __IO uint32_t RX_CHF_COEF_9;                     /**< Receive Channel Filter Coefficient 9, offset: 0x1C4 */
+  __IO uint32_t RX_CHF_COEF_10;                    /**< Receive Channel Filter Coefficient 10, offset: 0x1C8 */
+  __IO uint32_t RX_CHF_COEF_11;                    /**< Receive Channel Filter Coefficient 11, offset: 0x1CC */
+  __IO uint32_t AGC_MAN_AGC_IDX;                   /**< AGC Manual AGC Index, offset: 0x1D0 */
+  __IO uint32_t DC_RESID_CTRL;                     /**< DC Residual Control, offset: 0x1D4 */
+  __I  uint32_t DC_RESID_EST;                      /**< DC Residual Estimate, offset: 0x1D8 */
+  __IO uint32_t RX_RCCAL_CTRL0;                    /**< RX RC Calibration Control0, offset: 0x1DC */
+  __IO uint32_t RX_RCCAL_CTRL1;                    /**< RX RC Calibration Control1, offset: 0x1E0 */
+  __I  uint32_t RX_RCCAL_STAT;                     /**< RX RC Calibration Status, offset: 0x1E4 */
+  __IO uint32_t AUXPLL_FCAL_CTRL;                  /**< Aux PLL Frequency Calibration Control, offset: 0x1E8 */
+  __I  uint32_t AUXPLL_FCAL_CNT6;                  /**< Aux PLL Frequency Calibration Count 6, offset: 0x1EC */
+  __I  uint32_t AUXPLL_FCAL_CNT5_4;                /**< Aux PLL Frequency Calibration Count 5 and 4, offset: 0x1F0 */
+  __I  uint32_t AUXPLL_FCAL_CNT3_2;                /**< Aux PLL Frequency Calibration Count 3 and 2, offset: 0x1F4 */
+  __I  uint32_t AUXPLL_FCAL_CNT1_0;                /**< Aux PLL Frequency Calibration Count 1 and 0, offset: 0x1F8 */
+} XCVR_RX_DIG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- XCVR_RX_DIG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XCVR_RX_DIG_Register_Masks XCVR_RX_DIG Register Masks
+ * @{
+ */
+
+/*! @name RX_DIG_CTRL - RX Digital Control */
+/*! @{ */
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE_MASK (0x1U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE_SHIFT (0U)
+/*! RX_ADC_NEGEDGE - Receive ADC Negative Edge Selection
+ *  0b0..Register ADC data on positive edge of clock
+ *  0b1..Register ADC data on negative edge of clock
+ */
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE_MASK)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS_MASK (0x2U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS_SHIFT (1U)
+/*! RX_CH_FILT_BYPASS - Receive Channel Filter Bypass
+ *  0b0..Channel filter is enabled.
+ *  0b1..Disable and bypass channel filter.
+ */
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS_MASK)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL_MASK  (0x8U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL_SHIFT (3U)
+/*! RX_ADC_POL - Receive ADC Polarity
+ *  0b0..ADC output of 1'b0 maps to -1, 1'b1 maps to +1 (default)
+ *  0b1..ADC output of 1'b0 maps to +1, 1'b1 maps to -1
+ */
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL_MASK)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_MASK (0xF0U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_SHIFT (4U)
+/*! RX_DEC_FILT_OSR - Decimation Filter Oversampling
+ *  0b0000..OSR 4
+ *  0b0001..OSR 8
+ *  0b0010..OSR 16
+ *  0b0100..OSR 32
+ *  0b1000..OSR 64
+ *  0b0011..OSR 6
+ *  0b0101..OSR 12
+ *  0b0110..OSR 24
+ *  0b0111..OSR 48
+ */
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_MASK)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL_MASK (0x100U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL_SHIFT (8U)
+/*! RX_FSK_ZB_SEL - FSK / 802.15.4 demodulator select
+ *  0b0..FSK demodulator.
+ *  0b1..802.15.4 demodulator.
+ */
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL_MASK)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_SUPP_EN_MASK (0x200U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_SUPP_EN_SHIFT (9U)
+/*! RX_NORM_SUPP_EN - Normalizer Suppression Enable
+ *  0b0..Normalizer suppression is disabled.
+ *  0b1..Normalizer suppression is enabled.
+ */
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_SUPP_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_SUPP_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_SUPP_EN_MASK)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN_MASK  (0x400U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN_SHIFT (10U)
+/*! RX_RSSI_EN - RSSI Measurement Enable
+ *  0b0..RSSI measurement is disabled.
+ *  0b1..RSSI measurement is enabled.
+ */
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN_MASK)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK   (0x800U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_SHIFT  (11U)
+/*! RX_AGC_EN - AGC Global Enable
+ *  0b0..AGC is disabled.
+ *  0b1..AGC is enabled.
+ */
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN_MASK  (0x1000U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN_SHIFT (12U)
+/*! RX_DCOC_EN - DCOC Enable
+ *  0b0..DCOC is disabled.
+ *  0b1..DCOC is enabled.
+ */
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN_MASK)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK (0x2000U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_SHIFT (13U)
+/*! RX_DCOC_CAL_EN - DCOC Calibration Enable
+ *  0b0..DCOC calibration is disabled.
+ *  0b1..DCOC calibration is enabled.
+ */
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP_MASK  (0x4000U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP_SHIFT (14U)
+/*! RX_IQ_SWAP - RX IQ Swap
+ *  0b0..IQ swap is disabled.
+ *  0b1..IQ swap is enabled.
+ */
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP_MASK)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK (0x8000U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_SHIFT (15U)
+/*! RX_DC_RESID_EN - DC Residual Enable
+ *  0b0..DC Residual block is disabled.
+ *  0b1..DC Residual block is enabled.
+ */
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_MASK   (0x10000U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_SHIFT  (16U)
+/*! RX_SRC_EN - RX Sample Rate Converter Enable
+ *  0b0..SRC is disabled.
+ *  0b1..SRC is enabled.
+ */
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_MASK)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE_MASK (0x20000U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE_SHIFT (17U)
+/*! RX_SRC_RATE - RX Sample Rate Converter Rate Selections
+ *  0b0..SRC is configured for a First Order Hold rate of 8/13.
+ *  0b1..SRC is configured for a Zero Order Hold rate of 12/13.
+ */
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE_MASK)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK (0x40000U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_SHIFT (18U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_LP_MASK (0x80000U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_LP_SHIFT (19U)
+/*! RX_DEC_FILT_LP - RX Decimator Low Power
+ *  0b0..Decimator operates in normal mode.
+ *  0b1..Decimator operates in low power mode.
+ */
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_LP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_LP_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_LP_MASK)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN_MASK (0x1F00000U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN_SHIFT (20U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN_MASK)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS_MASK (0x2000000U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS_SHIFT (25U)
+/*! RX_DEC_FILT_HZD_CORR_DIS - Decimator filter hazard correction disable
+ *  0b0..Hazard correction is enabled
+ *  0b1..Hazard correction is disabled
+ */
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS_MASK)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_LEN_MASK (0x4000000U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_LEN_SHIFT (26U)
+/*! RX_CH_FILT_LEN - RX Channel Filter Length
+ *  0b0..Channel filter length is 24.
+ *  0b1..Channel filter length is 16. Only RX_CHF_COEF_4 - RX_CHF_COEF_11 are used in this mode.
+ */
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_LEN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_LEN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_LEN_MASK)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_SUPP_TH_MASK (0x8000000U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_SUPP_TH_SHIFT (27U)
+/*! RX_NORM_SUPP_TH - Normalizer Suppression Threshold
+ *  0b0..Normalizer suppression threshold is 12'd7.
+ *  0b1..Normalizer suppression threshold is 12'd15.
+ */
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_SUPP_TH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_SUPP_TH_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_SUPP_TH_MASK)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD_MASK (0x10000000U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD_SHIFT (28U)
+/*! RX_DEC_FILT_HAZARD - Decimator output, hazard condition detected
+ *  0b0..A hazard condition has not been detected
+ *  0b1..A hazard condition has been detected
+ */
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD_MASK)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD_MASK (0x20000000U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD_SHIFT (29U)
+/*! RX_RSSI_FILT_HAZARD - Decimator output for RSSI, hazard condition detected
+ *  0b0..A hazard condition has not been detected
+ *  0b1..A hazard condition has been detected
+ */
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD_MASK)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I_MASK (0x40000000U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I_SHIFT (30U)
+/*! RX_DEC_FILT_SAT_I - Decimator output, saturation detected for I channel
+ *  0b0..A saturation condition has not occurred.
+ *  0b1..A saturation condition has occurred.
+ */
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I_MASK)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q_MASK (0x80000000U)
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q_SHIFT (31U)
+/*! RX_DEC_FILT_SAT_Q - Decimator output, saturation detected for Q channel
+ *  0b0..A saturation condition has not occurred.
+ *  0b1..A saturation condition has occurred.
+ */
+#define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q_MASK)
+/*! @} */
+
+/*! @name AGC_CTRL_0 - AGC Control 0 */
+/*! @{ */
+#define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN_MASK  (0x1U)
+#define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN_SHIFT (0U)
+#define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC_MASK (0x6U)
+#define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC_SHIFT (1U)
+/*! SLOW_AGC_SRC - Slow AGC Source Selection
+ *  0b00..Access Address match (for active protocol)
+ *  0b01..Preamble Detect (for active protocol)
+ *  0b10..Fast AGC expire timer
+ *  0b11..Reserved
+ */
+#define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN_MASK (0x8U)
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN_SHIFT (3U)
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_SRC_MASK (0x30U)
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_SRC_SHIFT (4U)
+/*! AGC_FREEZE_SRC - AGC Freeze Source Selection
+ *  0b00..Access Address match (for active protocol)
+ *  0b01..Preamble Detect (for active protocol)
+ *  0b10..PD confirmation / Access Address match (for active protocol)
+ */
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_SRC_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_SRC_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN_MASK    (0x40U)
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN_SHIFT   (6U)
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC_MASK   (0x80U)
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC_SHIFT  (7U)
+/*! AGC_UP_SRC - AGC Up Source
+ *  0b0..PDET LO
+ *  0b1..RSSI
+ */
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ_MASK (0xF00U)
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ_SHIFT (8U)
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ_MASK (0xF000U)
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ_SHIFT (12U)
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH_MASK (0xFF0000U)
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH_SHIFT (16U)
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_MASK (0xFF000000U)
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_SHIFT (24U)
+#define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_MASK)
+/*! @} */
+
+/*! @name AGC_CTRL_1 - AGC Control 1 */
+/*! @{ */
+#define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_UP_THRESH_MASK (0xFU)
+#define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_UP_THRESH_SHIFT (0U)
+#define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_UP_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_UP_THRESH_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_UP_THRESH_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_DOWN_THRESH_MASK (0xF0U)
+#define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_DOWN_THRESH_SHIFT (4U)
+#define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_DOWN_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_DOWN_THRESH_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_DOWN_THRESH_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN_MASK (0xF000U)
+#define XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN_SHIFT (12U)
+#define XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN_MASK (0xF0000U)
+#define XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN_SHIFT (16U)
+#define XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_MASK (0x100000U)
+#define XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_SHIFT (20U)
+#define XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_MASK (0x200000U)
+#define XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_SHIFT (21U)
+#define XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN_MASK   (0x400000U)
+#define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN_SHIFT  (22U)
+/*! PRESLOW_EN - Pre-slow Enable
+ *  0b0..Pre-slow is disabled.
+ *  0b1..Pre-slow is enabled.
+ */
+#define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_1_PDET_HI_SEL_HOLD_MASK (0x800000U)
+#define XCVR_RX_DIG_AGC_CTRL_1_PDET_HI_SEL_HOLD_SHIFT (23U)
+/*! PDET_HI_SEL_HOLD - AGC HOLD hysteresis
+ *  0b0..Disabled.
+ *  0b1..Enabled.
+ */
+#define XCVR_RX_DIG_AGC_CTRL_1_PDET_HI_SEL_HOLD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_PDET_HI_SEL_HOLD_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_PDET_HI_SEL_HOLD_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME_MASK (0xFF000000U)
+#define XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME_SHIFT (24U)
+#define XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME_MASK)
+/*! @} */
+
+/*! @name AGC_CTRL_2 - AGC Control 2 */
+/*! @{ */
+#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST_MASK (0x1U)
+#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST_SHIFT (0U)
+#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST_MASK (0x2U)
+#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST_SHIFT (1U)
+#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST_MASK (0x4U)
+#define XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST_SHIFT (2U)
+/*! MAN_PDET_RST - MAN PDET Reset
+ *  0b0..The peak detector reset signals are controlled automatically by the AGC.
+ *  0b1..The BBA_PDET_RST and TZA_PDET_RST are used to manually control the peak detector reset signals.
+ */
+#define XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME_MASK (0xFF0U)
+#define XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME_SHIFT (4U)
+#define XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO_MASK (0x7000U)
+#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO_SHIFT (12U)
+/*! BBA_PDET_SEL_LO - BBA PDET Threshold Low
+ *  0b000..0.600V
+ *  0b001..0.615V
+ *  0b010..0.630V
+ *  0b011..0.645V
+ *  0b100..0.660V
+ *  0b101..0.675V
+ *  0b110..0.690V
+ *  0b111..0.705V
+ */
+#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI_MASK (0x38000U)
+#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI_SHIFT (15U)
+/*! BBA_PDET_SEL_HI - BBA PDET Threshold High
+ *  0b000..0.600V
+ *  0b001..0.795V
+ *  0b010..0.900V
+ *  0b011..0.945V
+ *  0b100..1.005V
+ *  0b101..1.050V
+ *  0b110..1.095V
+ *  0b111..1.155V
+ */
+#define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO_MASK (0x1C0000U)
+#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO_SHIFT (18U)
+/*! TZA_PDET_SEL_LO - TZA PDET Threshold Low
+ *  0b000..0.600V
+ *  0b001..0.615V
+ *  0b010..0.630V
+ *  0b011..0.645V
+ *  0b100..0.660V
+ *  0b101..0.675V
+ *  0b110..0.690V
+ *  0b111..0.705V
+ */
+#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI_MASK (0xE00000U)
+#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI_SHIFT (21U)
+/*! TZA_PDET_SEL_HI - TZA PDET Threshold High
+ *  0b000..0.600V
+ *  0b001..0.645V
+ *  0b010..0.705V
+ *  0b011..0.750V
+ *  0b100..0.795V
+ *  0b101..0.855V
+ *  0b110..0.900V
+ *  0b111..0.945V
+ */
+#define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE_MASK (0x3F000000U)
+#define XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE_SHIFT (24U)
+#define XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR_MASK (0x40000000U)
+#define XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR_SHIFT (30U)
+#define XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR_MASK (0x80000000U)
+#define XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR_SHIFT (31U)
+#define XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR_MASK)
+/*! @} */
+
+/*! @name AGC_CTRL_3 - AGC Control 3 */
+/*! @{ */
+#define XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME_MASK (0x1FFFU)
+#define XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME_SHIFT (0U)
+#define XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY_MASK (0xE000U)
+#define XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY_SHIFT (13U)
+#define XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S_MASK (0x7F0000U)
+#define XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S_SHIFT (16U)
+#define XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ_MASK (0xF800000U)
+#define XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ_SHIFT (23U)
+#define XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ_MASK)
+#define XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ_MASK (0xF0000000U)
+#define XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ_SHIFT (28U)
+#define XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ_MASK)
+/*! @} */
+
+/*! @name AGC_STAT - AGC Status */
+/*! @{ */
+#define XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT_MASK (0x1U)
+#define XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT_SHIFT (0U)
+#define XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT_SHIFT)) & XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT_MASK)
+#define XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT_MASK (0x2U)
+#define XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT_SHIFT (1U)
+#define XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT_SHIFT)) & XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT_MASK)
+#define XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT_MASK (0x4U)
+#define XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT_SHIFT (2U)
+#define XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT_SHIFT)) & XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT_MASK)
+#define XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT_MASK (0x8U)
+#define XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT_SHIFT (3U)
+#define XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT_SHIFT)) & XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT_MASK)
+#define XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX_MASK   (0x1F0U)
+#define XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX_SHIFT  (4U)
+#define XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX_SHIFT)) & XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX_MASK)
+#define XCVR_RX_DIG_AGC_STAT_AGC_FROZEN_MASK     (0x200U)
+#define XCVR_RX_DIG_AGC_STAT_AGC_FROZEN_SHIFT    (9U)
+/*! AGC_FROZEN - AGC Frozen Status
+ *  0b0..AGC is not frozen.
+ *  0b1..AGC is frozen.
+ */
+#define XCVR_RX_DIG_AGC_STAT_AGC_FROZEN(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_AGC_FROZEN_SHIFT)) & XCVR_RX_DIG_AGC_STAT_AGC_FROZEN_MASK)
+#define XCVR_RX_DIG_AGC_STAT_AGC_IDX_AA_MATCH_MASK (0x7C00U)
+#define XCVR_RX_DIG_AGC_STAT_AGC_IDX_AA_MATCH_SHIFT (10U)
+#define XCVR_RX_DIG_AGC_STAT_AGC_IDX_AA_MATCH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_AGC_IDX_AA_MATCH_SHIFT)) & XCVR_RX_DIG_AGC_STAT_AGC_IDX_AA_MATCH_MASK)
+#define XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW_MASK   (0xFF0000U)
+#define XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW_SHIFT  (16U)
+#define XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW_SHIFT)) & XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW_MASK)
+/*! @} */
+
+/*! @name RSSI_CTRL_0 - RSSI Control 0 */
+/*! @{ */
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS_MASK (0x1U)
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS_SHIFT (0U)
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS_MASK)
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC_MASK (0x6U)
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC_SHIFT (1U)
+/*! RSSI_HOLD_SRC - RSSI Hold Source Selection
+ *  0b00..Access Address match
+ *  0b01..Preamble Detect
+ *  0b10..Reserved
+ *  0b11..802.15.4 LQI done (1=freeze, 0=run AGC)
+ */
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC_MASK)
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN_MASK (0x8U)
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN_SHIFT (3U)
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN_MASK)
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK (0x60U)
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_SHIFT (5U)
+/*! RSSI_IIR_CW_WEIGHT - RSSI IIR CW Weighting
+ *  0b00..Bypass
+ *  0b01..1/8
+ *  0b10..1/16
+ *  0b11..1/32
+ */
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK)
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_NB_MASK (0x380U)
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_NB_SHIFT (7U)
+/*! RSSI_N_WINDOW_NB - RSSI N Window Average Narrowband
+ *  0b000..No averaging
+ *  0b001..Averaging window length is 2 samples
+ *  0b010..Averaging window length is 4 samples
+ *  0b011..Averaging window length is 8 samples
+ *  0b100..Averaging window length is 16 samples
+ *  0b101..Averaging window length is 32 samples
+ */
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_NB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_NB_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_NB_MASK)
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY_MASK (0xFC00U)
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY_SHIFT (10U)
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY_MASK)
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WT_NB_MASK (0x70000U)
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WT_NB_SHIFT (16U)
+/*! RSSI_IIR_WT_NB - RSSI IIR Weighting Narrowband
+ *  0b000..Bypass
+ *  0b001..1/2
+ *  0b010..1/4
+ *  0b011..1/8
+ *  0b100..1/16
+ *  0b101..1/32
+ */
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WT_NB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WT_NB_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WT_NB_MASK)
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE_MASK (0x700000U)
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE_SHIFT (20U)
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE_MASK)
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK    (0xFF000000U)
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_SHIFT   (24U)
+#define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK)
+/*! @} */
+
+/*! @name RSSI_CTRL_1 - RSSI Control 1 */
+/*! @{ */
+#define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_N_WINDOW_WB_MASK (0x7U)
+#define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_N_WINDOW_WB_SHIFT (0U)
+/*! RSSI_N_WINDOW_WB - RSSI N Window Average Wideband
+ *  0b000..No averaging
+ *  0b001..Averaging window length is 2 samples
+ *  0b010..Averaging window length is 4 samples
+ *  0b011..Averaging window length is 8 samples
+ *  0b100..Averaging window length is 16 samples
+ *  0b101..Averaging window length is 32 samples
+ */
+#define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_N_WINDOW_WB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_1_RSSI_N_WINDOW_WB_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_1_RSSI_N_WINDOW_WB_MASK)
+#define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_IIR_WT_WB_MASK (0x70U)
+#define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_IIR_WT_WB_SHIFT (4U)
+/*! RSSI_IIR_WT_WB - RSSI IIR Weighting Wideband
+ *  0b000..Bypass
+ *  0b001..1/2
+ *  0b010..1/4
+ *  0b011..1/8
+ *  0b100..1/16
+ *  0b101..1/32
+ */
+#define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_IIR_WT_WB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_1_RSSI_IIR_WT_WB_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_1_RSSI_IIR_WT_WB_MASK)
+#define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_MASK    (0xFF000000U)
+#define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_SHIFT   (24U)
+#define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_MASK)
+/*! @} */
+
+/*! @name DCOC_CTRL_0 - DCOC Control 0 */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS_MASK (0x1U)
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS_SHIFT (0U)
+/*! DCOC_MIDPWR_TRK_DIS - DCOC Mid Power Tracking Disable
+ *  0b0..Tracking corrections are enabled as determined by DCOC_CORRECT_SRC and DCOC_TRK_MIN_AGC_IDX.
+ *  0b1..Tracking corrections are disabled when either the TZA or BBA lo peak detector asserts.
+ */
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS_MASK)
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_MASK    (0x2U)
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_SHIFT   (1U)
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_MASK)
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR_MASK (0x4U)
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR_SHIFT (2U)
+/*! DCOC_TRK_EST_OVR - Override for the DCOC tracking estimator
+ *  0b0..The tracking estimator is enabled only as needed by the corrector
+ *  0b1..The tracking estimator remains enabled whenever the DCOC is active
+ */
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR_MASK)
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_MASK (0x8U)
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_SHIFT (3U)
+/*! DCOC_CORRECT_SRC - DCOC Corrector Source
+ *  0b0..If correction is enabled, the DCOC will use only the DCOC calibration table to correct the DC offset.
+ *  0b1..If correction is enabled, the DCOC will use the DCOC calibration table and then the tracking estimator to correct the DC offset.
+ */
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_MASK)
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN_MASK (0x10U)
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN_SHIFT (4U)
+/*! DCOC_CORRECT_EN - DCOC Correction Enable
+ *  0b0..Correction disabled. The DCOC will not correct the DC offset.
+ *  0b1..Correction enabled. The DCOC will use the TZA and BBA DACs, and apply digital corrections (if DCOC_CORRECT_SRC=1) to correct the DC offset.
+ */
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN_MASK)
+#define XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO_MASK (0x20U)
+#define XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO_SHIFT (5U)
+/*! TRACK_FROM_ZERO - Track from Zero
+ *  0b0..Track from current I/Q sample.
+ *  0b1..Track from zero.
+ */
+#define XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO_MASK)
+#define XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL_MASK (0x40U)
+#define XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL_SHIFT (6U)
+/*! BBA_CORR_POL - BBA Correction Polarity
+ *  0b0..Normal polarity.
+ *  0b1..Negative polarity. This should be set if the ADC output is inverted, or if the BBA DACs were implemented with negative polarity.
+ */
+#define XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL_MASK)
+#define XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL_MASK (0x80U)
+#define XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL_SHIFT (7U)
+/*! TZA_CORR_POL - TZA Correction Polarity
+ *  0b0..Normal polarity.
+ *  0b1..Negative polarity. This should be set if the ADC output is inverted, or if the TZA DACs were implemented with negative polarity.
+ */
+#define XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL_MASK)
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION_MASK (0x1F00U)
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION_SHIFT (8U)
+/*! DCOC_CAL_DURATION - DCOC Calibration Duration
+ *  0b00000..Reserved
+ *  0b00001-0b11111..For a 32MHz reference clock, this is the calibration duration in microseconds; for other reference clock frequencies, the delay is scaled accordingly.
+ */
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION_MASK)
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN_MASK (0x8000U)
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN_SHIFT (15U)
+/*! DCOC_CAL_CHECK_EN - DCOC Calibration Check Enable
+ *  0b0..Calibration checking disabled. The DCOC_OFFSET_n registers are always updated during calibration.
+ *  0b1..Calibration checking enabled. The DCOC_OFFSET_n registers are updated conditionally depending on the outcome of the pass/fail threshold checks performed on the alpha-hat and beta-hat estimates during calibration.
+ */
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN_MASK)
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY_MASK (0x1F0000U)
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY_SHIFT (16U)
+/*! DCOC_CORR_DLY - DCOC Correction Delay
+ *  0b00000..Reserved
+ *  0b00001-0b11111..For a 32MHz reference clock, this is the wait time in microseconds; for other reference clock frequencies, the delay is scaled accordingly.
+ */
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY_MASK)
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_MASK (0x7F000000U)
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_SHIFT (24U)
+/*! DCOC_CORR_HOLD_TIME - DCOC Correction Hold Time
+ *  0b0000000..Reserved
+ *  0b0000001-0b1111110..For a 32MHz reference clock, this is the delay in microseconds; for other reference clock frequencies, the delay is scaled accordingly.
+ *  0b1111111..The DC correction is not frozen.
+ */
+#define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_MASK)
+/*! @} */
+
+/*! @name DCOC_CTRL_1 - DCOC Control 1 */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX_MASK (0x3U)
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX_SHIFT (0U)
+/*! DCOC_SIGN_SCALE_IDX - DCOC Sign Scaling
+ *  0b00..1/8
+ *  0b01..1/16
+ *  0b10..1/32
+ *  0b11..1/64
+ */
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX_MASK)
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX_MASK (0x1CU)
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX_SHIFT (2U)
+/*! DCOC_ALPHAC_SCALE_IDX - DCOC Alpha-C Scaling
+ *  0b000..1/2
+ *  0b001..1/4
+ *  0b010..1/8
+ *  0b011..1/16
+ *  0b100..1/32
+ *  0b101..1/64
+ *  0b110..Reserved
+ *  0b111..Reserved
+ */
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX_MASK)
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX_MASK (0xE0U)
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX_SHIFT (5U)
+/*! DCOC_ALPHA_RADIUS_IDX - Alpha-R Scaling
+ *  0b000..1
+ *  0b001..1/2
+ *  0b010..1/4
+ *  0b011..1/8
+ *  0b100..1/16
+ *  0b101..1/32
+ *  0b110..1/64
+ *  0b111..Reserved
+ */
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX_MASK)
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT_MASK (0x7000U)
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT_SHIFT (12U)
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT_MASK)
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX_MASK (0x30000U)
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX_SHIFT (16U)
+/*! DCOC_SIGN_SCALE_GS_IDX - DCOC Sign Scaling for Gearshift
+ *  0b00..1/8
+ *  0b01..1/16
+ *  0b10..1/32
+ *  0b11..1/64
+ */
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX_MASK)
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX_MASK (0x1C0000U)
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX_SHIFT (18U)
+/*! DCOC_ALPHAC_SCALE_GS_IDX - DCOC Alpha-C Scaling for Gearshift
+ *  0b000..1/2
+ *  0b001..1/4
+ *  0b010..1/8
+ *  0b011..1/16
+ *  0b100..1/32
+ *  0b101..1/64
+ *  0b110..Reserved
+ *  0b111..Reserved
+ */
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX_MASK)
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX_MASK (0xE00000U)
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX_SHIFT (21U)
+/*! DCOC_ALPHA_RADIUS_GS_IDX - Alpha-R Scaling for Gearshift
+ *  0b000..1
+ *  0b001..1/2
+ *  0b010..1/4
+ *  0b011..1/8
+ *  0b100..1/16
+ *  0b101..1/32
+ *  0b110..1/64
+ *  0b111..Reserved
+ */
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX_MASK)
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_MASK (0x1F000000U)
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_SHIFT (24U)
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_MASK)
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_CFG_MASK (0x80000000U)
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_CFG_SHIFT (31U)
+/*! DCOC_TRK_MIN_AGC_IDX_CFG - DCOC_TRK_MIN_AGC_IDX Configuration
+ *  0b0..Tracking is disabled when the AGC index is less than DCOC_TRK_MIN_AGC_IDX
+ *  0b1..Tracking is enabled when AGC index is less than DCOC_TRK_MIN_AGC_IDX, but DCOC_CORR_DLY_ALT and DCOC_CORR_HOLD_TIME_ALT are used instead of DCOC_CORR_DLY and DCOC_CORR_HOLD_TIME
+ */
+#define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_CFG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_CFG_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_CFG_MASK)
+/*! @} */
+
+/*! @name DCOC_DAC_INIT - DCOC DAC Initialization */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK (0x3FU)
+#define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_SHIFT (0U)
+#define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_SHIFT)) & XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK)
+#define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK (0x3F00U)
+#define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_SHIFT (8U)
+#define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_SHIFT)) & XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK)
+#define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I_MASK (0xFF0000U)
+#define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I_SHIFT (16U)
+#define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I_SHIFT)) & XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I_MASK)
+#define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q_MASK (0xFF000000U)
+#define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q_SHIFT (24U)
+#define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q_SHIFT)) & XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q_MASK)
+/*! @} */
+
+/*! @name DCOC_DIG_MAN - DCOC Digital Correction Manual Override */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I_MASK (0xFFFU)
+#define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I_SHIFT (0U)
+#define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I_SHIFT)) & XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I_MASK)
+#define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q_MASK (0xFFF0000U)
+#define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q_SHIFT (16U)
+#define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q_SHIFT)) & XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q_MASK)
+/*! @} */
+
+/*! @name DCOC_CAL_GAIN - DCOC Calibration Gain */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1_MASK (0xF00U)
+#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1_SHIFT (8U)
+#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1_MASK)
+#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1_MASK (0xF000U)
+#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1_SHIFT (12U)
+#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1_MASK)
+#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2_MASK (0xF0000U)
+#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2_SHIFT (16U)
+#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2_MASK)
+#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2_MASK (0xF00000U)
+#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2_SHIFT (20U)
+#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2_MASK)
+#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3_MASK (0xF000000U)
+#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3_SHIFT (24U)
+#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3_MASK)
+#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3_MASK (0xF0000000U)
+#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3_SHIFT (28U)
+#define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3_MASK)
+/*! @} */
+
+/*! @name DCOC_STAT - DCOC Status */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I_MASK    (0x3FU)
+#define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I_SHIFT   (0U)
+#define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I_MASK)
+#define XCVR_RX_DIG_DCOC_STAT_DCOC_CAL_GTWSR_MASK (0x80U)
+#define XCVR_RX_DIG_DCOC_STAT_DCOC_CAL_GTWSR_SHIFT (7U)
+/*! DCOC_CAL_GTWSR - DCOC calibration Good Table Written Since Reset
+ *  0b0..A Passing calibration result has not occurred since the last radio reset.
+ *  0b1..A Passing calibration result has occurred since the last radio reset.
+ */
+#define XCVR_RX_DIG_DCOC_STAT_DCOC_CAL_GTWSR(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_DCOC_CAL_GTWSR_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_DCOC_CAL_GTWSR_MASK)
+#define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q_MASK    (0x3F00U)
+#define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q_SHIFT   (8U)
+#define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q_MASK)
+#define XCVR_RX_DIG_DCOC_STAT_DCOC_CAL_RESULT_MASK (0xC000U)
+#define XCVR_RX_DIG_DCOC_STAT_DCOC_CAL_RESULT_SHIFT (14U)
+/*! DCOC_CAL_RESULT - DCOC_CAL_RESULT
+ *  0b00..Calibration checks failed. DCOC_OFFSET_n tables not updated.
+ *  0b01..Calibration checks neither passed nor failed, DCOC_OFFSET_n tables not updated.
+ *  0b10..Calibration checks neither passed nor failed, DCOC_OFFSET_n tables updated since no previous Pass condition has occurred since the last radio reset.
+ *  0b11..Calibration checks passed. DCOC_OFFSET_n tables updated
+ */
+#define XCVR_RX_DIG_DCOC_STAT_DCOC_CAL_RESULT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_DCOC_CAL_RESULT_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_DCOC_CAL_RESULT_MASK)
+#define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I_MASK    (0xFF0000U)
+#define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I_SHIFT   (16U)
+#define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I_MASK)
+#define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q_MASK    (0xFF000000U)
+#define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q_SHIFT   (24U)
+#define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q_MASK)
+/*! @} */
+
+/*! @name DCOC_DC_EST - DCOC DC Estimate */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_MASK    (0xFFFU)
+#define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_SHIFT   (0U)
+#define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_SHIFT)) & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_MASK)
+#define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_MASK    (0xFFF0000U)
+#define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_SHIFT   (16U)
+#define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_SHIFT)) & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_MASK)
+/*! @} */
+
+/*! @name DCOC_CAL_RCP - DCOC Calibration Reciprocals */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_MASK (0x7FFU)
+#define XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_SHIFT (0U)
+#define XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_MASK)
+#define XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP_MASK (0x7FF0000U)
+#define XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP_SHIFT (16U)
+#define XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP_MASK)
+/*! @} */
+
+/*! @name DCOC_CTRL_2 - DCOC Control 2 */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_CTRL_2_DCOC_CORR_DLY_ALT_MASK (0x1F0000U)
+#define XCVR_RX_DIG_DCOC_CTRL_2_DCOC_CORR_DLY_ALT_SHIFT (16U)
+/*! DCOC_CORR_DLY_ALT - DCOC Correction Delay Alternate
+ *  0b00000..Reserved
+ *  0b00001-0b11111..For a 32MHz reference clock, this is the wait time in microseconds; for other reference clock frequencies, the delay is scaled accordingly.
+ */
+#define XCVR_RX_DIG_DCOC_CTRL_2_DCOC_CORR_DLY_ALT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_2_DCOC_CORR_DLY_ALT_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_2_DCOC_CORR_DLY_ALT_MASK)
+#define XCVR_RX_DIG_DCOC_CTRL_2_DCOC_CORR_HOLD_TIME_ALT_MASK (0x7F000000U)
+#define XCVR_RX_DIG_DCOC_CTRL_2_DCOC_CORR_HOLD_TIME_ALT_SHIFT (24U)
+/*! DCOC_CORR_HOLD_TIME_ALT - DCOC Correction Hold Time Alternate
+ *  0b0000000..Reserved
+ *  0b0000001-0b1111110..For a 32MHz reference clock, this is the delay in microseconds; for other reference clock frequencies, the delay is scaled accordingly.
+ *  0b1111111..The DC correction is not frozen.
+ */
+#define XCVR_RX_DIG_DCOC_CTRL_2_DCOC_CORR_HOLD_TIME_ALT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_2_DCOC_CORR_HOLD_TIME_ALT_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_2_DCOC_CORR_HOLD_TIME_ALT_MASK)
+/*! @} */
+
+/*! @name IQMC_CTRL - IQMC Control */
+/*! @{ */
+#define XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN_MASK   (0x1U)
+#define XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN_SHIFT  (0U)
+#define XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN_SHIFT)) & XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN_MASK)
+#define XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER_MASK (0xFF00U)
+#define XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER_SHIFT (8U)
+#define XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER_SHIFT)) & XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER_MASK)
+#define XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ_MASK (0x7FF0000U)
+#define XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ_SHIFT (16U)
+#define XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ_SHIFT)) & XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ_MASK)
+/*! @} */
+
+/*! @name IQMC_CAL - IQMC Calibration */
+/*! @{ */
+#define XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ_MASK  (0x7FFU)
+#define XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ_SHIFT (0U)
+#define XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ_SHIFT)) & XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ_MASK)
+#define XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ_MASK (0xFFF0000U)
+#define XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ_SHIFT (16U)
+#define XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ_SHIFT)) & XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ_MASK)
+/*! @} */
+
+/*! @name LNA_GAIN_VAL_3_0 - LNA_GAIN Step Values 3..0 */
+/*! @{ */
+#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0_MASK (0xFFU)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0_SHIFT (0U)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0_MASK)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1_MASK (0xFF00U)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1_SHIFT (8U)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1_MASK)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2_MASK (0xFF0000U)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2_SHIFT (16U)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2_MASK)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3_MASK (0xFF000000U)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3_SHIFT (24U)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3_MASK)
+/*! @} */
+
+/*! @name LNA_GAIN_VAL_7_4 - LNA_GAIN Step Values 7..4 */
+/*! @{ */
+#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4_MASK (0xFFU)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4_SHIFT (0U)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4_MASK)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5_MASK (0xFF00U)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5_SHIFT (8U)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5_MASK)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6_MASK (0xFF0000U)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6_SHIFT (16U)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6_MASK)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7_MASK (0xFF000000U)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7_SHIFT (24U)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7_MASK)
+/*! @} */
+
+/*! @name LNA_GAIN_VAL_8 - LNA_GAIN Step Values 8 */
+/*! @{ */
+#define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8_MASK (0xFFU)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8_SHIFT (0U)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8_MASK)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9_MASK (0xFF00U)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9_SHIFT (8U)
+#define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9_MASK)
+/*! @} */
+
+/*! @name BBA_RES_TUNE_VAL_7_0 - BBA Resistor Tune Values 7..0 */
+/*! @{ */
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0_MASK (0xFU)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0_SHIFT (0U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0_MASK)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1_MASK (0xF0U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1_SHIFT (4U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1_MASK)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2_MASK (0xF00U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2_SHIFT (8U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2_MASK)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3_MASK (0xF000U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3_SHIFT (12U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3_MASK)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4_MASK (0xF0000U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4_SHIFT (16U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4_MASK)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5_MASK (0xF00000U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5_SHIFT (20U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5_MASK)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6_MASK (0xF000000U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6_SHIFT (24U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6_MASK)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7_MASK (0xF0000000U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7_SHIFT (28U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7_MASK)
+/*! @} */
+
+/*! @name BBA_RES_TUNE_VAL_10_8 - BBA Resistor Tune Values 10..8 */
+/*! @{ */
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8_MASK (0xFU)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8_SHIFT (0U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8_MASK)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9_MASK (0xF0U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9_SHIFT (4U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9_MASK)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10_MASK (0xF00U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10_SHIFT (8U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10_MASK)
+/*! @} */
+
+/*! @name LNA_GAIN_LIN_VAL_2_0 - LNA Linear Gain Values 2..0 */
+/*! @{ */
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0_MASK (0x3FFU)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0_SHIFT (0U)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0_MASK)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1_MASK (0xFFC00U)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1_SHIFT (10U)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1_MASK)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2_MASK (0x3FF00000U)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2_SHIFT (20U)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2_MASK)
+/*! @} */
+
+/*! @name LNA_GAIN_LIN_VAL_5_3 - LNA Linear Gain Values 5..3 */
+/*! @{ */
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3_MASK (0x3FFU)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3_SHIFT (0U)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3_MASK)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4_MASK (0xFFC00U)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4_SHIFT (10U)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4_MASK)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5_MASK (0x3FF00000U)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5_SHIFT (20U)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5_MASK)
+/*! @} */
+
+/*! @name LNA_GAIN_LIN_VAL_8_6 - LNA Linear Gain Values 8..6 */
+/*! @{ */
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6_MASK (0x3FFU)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6_SHIFT (0U)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6_MASK)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7_MASK (0xFFC00U)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7_SHIFT (10U)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7_MASK)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8_MASK (0x3FF00000U)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8_SHIFT (20U)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8_MASK)
+/*! @} */
+
+/*! @name LNA_GAIN_LIN_VAL_9 - LNA Linear Gain Values 9 */
+/*! @{ */
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9_MASK (0x3FFU)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9_SHIFT (0U)
+#define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9_MASK)
+/*! @} */
+
+/*! @name BBA_RES_TUNE_LIN_VAL_3_0 - BBA Resistor Tune Values 3..0 */
+/*! @{ */
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0_MASK (0xFFU)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0_SHIFT (0U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0_MASK)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1_MASK (0xFF00U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1_SHIFT (8U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1_MASK)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2_MASK (0xFF0000U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2_SHIFT (16U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2_MASK)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3_MASK (0xFF000000U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3_SHIFT (24U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3_MASK)
+/*! @} */
+
+/*! @name BBA_RES_TUNE_LIN_VAL_7_4 - BBA Resistor Tune Values 7..4 */
+/*! @{ */
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4_MASK (0xFFU)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4_SHIFT (0U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4_MASK)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5_MASK (0xFF00U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5_SHIFT (8U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5_MASK)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6_MASK (0xFF0000U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6_SHIFT (16U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6_MASK)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7_MASK (0xFF000000U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7_SHIFT (24U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7_MASK)
+/*! @} */
+
+/*! @name BBA_RES_TUNE_LIN_VAL_10_8 - BBA Resistor Tune Values 10..8 */
+/*! @{ */
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8_MASK (0x3FFU)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8_SHIFT (0U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8_MASK)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9_MASK (0xFFC00U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9_SHIFT (10U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9_MASK)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10_MASK (0x3FF00000U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10_SHIFT (20U)
+#define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10_MASK)
+/*! @} */
+
+/*! @name AGC_GAIN_TBL_03_00 - AGC Gain Tables Step 03..00 */
+/*! @{ */
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00_MASK (0xFU)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00_SHIFT (0U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00_MASK (0xF0U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00_SHIFT (4U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01_MASK (0xF00U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01_SHIFT (8U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01_MASK (0xF000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01_SHIFT (12U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02_MASK (0xF0000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02_SHIFT (16U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02_MASK (0xF00000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02_SHIFT (20U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03_MASK (0xF000000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03_SHIFT (24U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03_MASK (0xF0000000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03_SHIFT (28U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03_MASK)
+/*! @} */
+
+/*! @name AGC_GAIN_TBL_07_04 - AGC Gain Tables Step 07..04 */
+/*! @{ */
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04_MASK (0xFU)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04_SHIFT (0U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04_MASK (0xF0U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04_SHIFT (4U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05_MASK (0xF00U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05_SHIFT (8U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05_MASK (0xF000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05_SHIFT (12U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06_MASK (0xF0000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06_SHIFT (16U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06_MASK (0xF00000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06_SHIFT (20U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07_MASK (0xF000000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07_SHIFT (24U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07_MASK (0xF0000000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07_SHIFT (28U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07_MASK)
+/*! @} */
+
+/*! @name AGC_GAIN_TBL_11_08 - AGC Gain Tables Step 11..08 */
+/*! @{ */
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08_MASK (0xFU)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08_SHIFT (0U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08_MASK (0xF0U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08_SHIFT (4U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09_MASK (0xF00U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09_SHIFT (8U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09_MASK (0xF000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09_SHIFT (12U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10_MASK (0xF0000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10_SHIFT (16U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10_MASK (0xF00000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10_SHIFT (20U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11_MASK (0xF000000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11_SHIFT (24U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11_MASK (0xF0000000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11_SHIFT (28U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11_MASK)
+/*! @} */
+
+/*! @name AGC_GAIN_TBL_15_12 - AGC Gain Tables Step 15..12 */
+/*! @{ */
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12_MASK (0xFU)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12_SHIFT (0U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12_MASK (0xF0U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12_SHIFT (4U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13_MASK (0xF00U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13_SHIFT (8U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13_MASK (0xF000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13_SHIFT (12U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14_MASK (0xF0000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14_SHIFT (16U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14_MASK (0xF00000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14_SHIFT (20U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15_MASK (0xF000000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15_SHIFT (24U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15_MASK (0xF0000000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15_SHIFT (28U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15_MASK)
+/*! @} */
+
+/*! @name AGC_GAIN_TBL_19_16 - AGC Gain Tables Step 19..16 */
+/*! @{ */
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16_MASK (0xFU)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16_SHIFT (0U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16_MASK (0xF0U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16_SHIFT (4U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17_MASK (0xF00U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17_SHIFT (8U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17_MASK (0xF000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17_SHIFT (12U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18_MASK (0xF0000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18_SHIFT (16U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18_MASK (0xF00000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18_SHIFT (20U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19_MASK (0xF000000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19_SHIFT (24U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19_MASK (0xF0000000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19_SHIFT (28U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19_MASK)
+/*! @} */
+
+/*! @name AGC_GAIN_TBL_23_20 - AGC Gain Tables Step 23..20 */
+/*! @{ */
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20_MASK (0xFU)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20_SHIFT (0U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20_MASK (0xF0U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20_SHIFT (4U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21_MASK (0xF00U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21_SHIFT (8U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21_MASK (0xF000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21_SHIFT (12U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22_MASK (0xF0000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22_SHIFT (16U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22_MASK (0xF00000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22_SHIFT (20U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23_MASK (0xF000000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23_SHIFT (24U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23_MASK (0xF0000000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23_SHIFT (28U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23_MASK)
+/*! @} */
+
+/*! @name AGC_GAIN_TBL_26_24 - AGC Gain Tables Step 26..24 */
+/*! @{ */
+#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24_MASK (0xFU)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24_SHIFT (0U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24_MASK (0xF0U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24_SHIFT (4U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25_MASK (0xF00U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25_SHIFT (8U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25_MASK (0xF000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25_SHIFT (12U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26_MASK (0xF0000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26_SHIFT (16U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26_MASK)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26_MASK (0xF00000U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26_SHIFT (20U)
+#define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26_MASK)
+/*! @} */
+
+/*! @name DCOC_OFFSET - DCOC Offset */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I_MASK (0x3FU)
+#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I_SHIFT (0U)
+#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I_SHIFT)) & XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I_MASK)
+#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q_MASK (0x3F00U)
+#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q_SHIFT (8U)
+#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q_SHIFT)) & XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q_MASK)
+#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I_MASK (0xFF0000U)
+#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I_SHIFT (16U)
+#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I_SHIFT)) & XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I_MASK)
+#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q_MASK (0xFF000000U)
+#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q_SHIFT (24U)
+#define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q_SHIFT)) & XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q_MASK)
+/*! @} */
+
+/* The count of XCVR_RX_DIG_DCOC_OFFSET */
+#define XCVR_RX_DIG_DCOC_OFFSET_COUNT            (27U)
+
+/*! @name DCOC_BBA_STEP - DCOC BBA DAC Step */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP_MASK (0x1FFFU)
+#define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP_SHIFT (0U)
+#define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP_SHIFT)) & XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP_MASK)
+#define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_MASK (0x1FF0000U)
+#define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_SHIFT (16U)
+#define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_SHIFT)) & XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_MASK)
+/*! @} */
+
+/*! @name DCOC_TZA_STEP_0 - DCOC TZA DAC Step 0 */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0_MASK (0x1FFFU)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0_SHIFT (0U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0_MASK)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_MASK (0xFFF0000U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT (16U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_MASK)
+/*! @} */
+
+/*! @name DCOC_TZA_STEP_1 - DCOC TZA DAC Step 1 */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1_MASK (0x1FFFU)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1_SHIFT (0U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1_MASK)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1_MASK (0xFFF0000U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1_SHIFT (16U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1_MASK)
+/*! @} */
+
+/*! @name DCOC_TZA_STEP_2 - DCOC TZA DAC Step 2 */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2_MASK (0x1FFFU)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2_SHIFT (0U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2_MASK)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2_MASK (0xFFF0000U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2_SHIFT (16U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2_MASK)
+/*! @} */
+
+/*! @name DCOC_TZA_STEP_3 - DCOC TZA DAC Step 3 */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3_MASK (0x1FFFU)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3_SHIFT (0U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3_MASK)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3_MASK (0xFFF0000U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3_SHIFT (16U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3_MASK)
+/*! @} */
+
+/*! @name DCOC_TZA_STEP_4 - DCOC TZA DAC Step 4 */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4_MASK (0x1FFFU)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4_SHIFT (0U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4_MASK)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4_MASK (0xFFF0000U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4_SHIFT (16U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4_MASK)
+/*! @} */
+
+/*! @name DCOC_TZA_STEP_5 - DCOC TZA DAC Step 5 */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5_MASK (0x1FFFU)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5_SHIFT (0U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5_MASK)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5_MASK (0xFFF0000U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5_SHIFT (16U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5_MASK)
+/*! @} */
+
+/*! @name DCOC_TZA_STEP_6 - DCOC TZA DAC Step 6 */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6_MASK (0x1FFFU)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6_SHIFT (0U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6_MASK)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6_MASK (0xFFF0000U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6_SHIFT (16U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6_MASK)
+/*! @} */
+
+/*! @name DCOC_TZA_STEP_7 - DCOC TZA DAC Step 7 */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7_MASK (0x1FFFU)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7_SHIFT (0U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7_MASK)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7_MASK (0x1FFF0000U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7_SHIFT (16U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7_MASK)
+/*! @} */
+
+/*! @name DCOC_TZA_STEP_8 - DCOC TZA DAC Step 5 */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8_MASK (0x1FFFU)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8_SHIFT (0U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8_MASK)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8_MASK (0x1FFF0000U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8_SHIFT (16U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8_MASK)
+/*! @} */
+
+/*! @name DCOC_TZA_STEP_9 - DCOC TZA DAC Step 9 */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9_MASK (0x1FFFU)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9_SHIFT (0U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9_MASK)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9_MASK (0x3FFF0000U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9_SHIFT (16U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9_MASK)
+/*! @} */
+
+/*! @name DCOC_TZA_STEP_10 - DCOC TZA DAC Step 10 */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10_MASK (0x1FFFU)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10_SHIFT (0U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10_MASK)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10_MASK (0x3FFF0000U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10_SHIFT (16U)
+#define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10_MASK)
+/*! @} */
+
+/*! @name DCOC_CAL_FAIL_TH - DCOC Calibration Fail Thresholds */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_BETA_F_TH_MASK (0x7FFU)
+#define XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_BETA_F_TH_SHIFT (0U)
+#define XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_BETA_F_TH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_BETA_F_TH_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_BETA_F_TH_MASK)
+#define XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_ALPHA_F_TH_MASK (0x3FF0000U)
+#define XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_ALPHA_F_TH_SHIFT (16U)
+#define XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_ALPHA_F_TH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_ALPHA_F_TH_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_ALPHA_F_TH_MASK)
+/*! @} */
+
+/*! @name DCOC_CAL_PASS_TH - DCOC Calibration Pass Thresholds */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_BETA_P_TH_MASK (0x7FFU)
+#define XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_BETA_P_TH_SHIFT (0U)
+#define XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_BETA_P_TH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_BETA_P_TH_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_BETA_P_TH_MASK)
+#define XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_ALPHA_P_TH_MASK (0x3FF0000U)
+#define XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_ALPHA_P_TH_SHIFT (16U)
+#define XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_ALPHA_P_TH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_ALPHA_P_TH_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_ALPHA_P_TH_MASK)
+/*! @} */
+
+/*! @name DCOC_CAL_ALPHA - DCOC Calibration Alpha */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_MASK (0x7FFU)
+#define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_SHIFT (0U)
+#define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_MASK)
+#define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_MASK (0x7FF0000U)
+#define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_SHIFT (16U)
+#define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_MASK)
+/*! @} */
+
+/*! @name DCOC_CAL_BETA_Q - DCOC Calibration Beta Q */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q_MASK (0x1FFFFU)
+#define XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q_SHIFT (0U)
+#define XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q_MASK)
+/*! @} */
+
+/*! @name DCOC_CAL_BETA_I - DCOC Calibration Beta I */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I_MASK (0x1FFFFU)
+#define XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I_SHIFT (0U)
+#define XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I_MASK)
+/*! @} */
+
+/*! @name DCOC_CAL_GAMMA - DCOC Calibration Gamma */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_MASK (0xFFFFU)
+#define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_SHIFT (0U)
+#define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_MASK)
+#define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_MASK (0xFFFF0000U)
+#define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_SHIFT (16U)
+#define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_MASK)
+/*! @} */
+
+/*! @name DCOC_CAL_IIR - DCOC Calibration IIR */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_MASK (0x3U)
+#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_SHIFT (0U)
+/*! DCOC_CAL_IIR1A_IDX - DCOC Calibration IIR 1A Index
+ *  0b00..1/1
+ *  0b01..1/4
+ *  0b10..1/8
+ *  0b11..1/16
+ */
+#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_MASK)
+#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_MASK (0xCU)
+#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_SHIFT (2U)
+/*! DCOC_CAL_IIR2A_IDX - DCOC Calibration IIR 2A Index
+ *  0b00..1/1
+ *  0b01..1/4
+ *  0b10..1/8
+ *  0b11..1/16
+ */
+#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_MASK)
+#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_MASK (0x30U)
+#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_SHIFT (4U)
+/*! DCOC_CAL_IIR3A_IDX - DCOC Calibration IIR 3A Index
+ *  0b00..1/4
+ *  0b01..1/8
+ *  0b10..1/16
+ *  0b11..1/32
+ */
+#define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_MASK)
+/*! @} */
+
+/*! @name DCOC_CAL - DCOC Calibration Result */
+/*! @{ */
+#define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I_MASK (0xFFFU)
+#define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I_SHIFT (0U)
+#define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I_MASK)
+#define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q_MASK (0xFFF0000U)
+#define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q_SHIFT (16U)
+#define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q_MASK)
+/*! @} */
+
+/* The count of XCVR_RX_DIG_DCOC_CAL */
+#define XCVR_RX_DIG_DCOC_CAL_COUNT               (3U)
+
+/*! @name CCA_ED_LQI_CTRL_0 - RX_DIG CCA ED LQI Control Register 0 */
+/*! @{ */
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH_MASK (0xFFU)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH_SHIFT (0U)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH_MASK)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH_MASK (0xFF00U)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH_SHIFT (8U)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH_MASK)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR_MASK (0xFF0000U)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR_SHIFT (16U)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR_MASK)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ_MASK (0x3F000000U)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ_SHIFT (24U)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ_MASK)
+/*! @} */
+
+/*! @name CCA_ED_LQI_CTRL_1 - RX_DIG CCA ED LQI Control Register 1 */
+/*! @{ */
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY_MASK (0x3FU)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY_SHIFT (0U)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY_MASK)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR_MASK (0x1C0U)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR_SHIFT (6U)
+/*! RSSI_NOISE_AVG_FACTOR - RSSI Noise Averaging Factor
+ *  0b000..1
+ *  0b001..64
+ *  0b010..70
+ *  0b011..128
+ *  0b100..139
+ *  0b101..256
+ *  0b110..277
+ *  0b111..512
+ */
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR_MASK)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT_MASK (0xE00U)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT_SHIFT (9U)
+/*! LQI_RSSI_WEIGHT - LQI RSSI Weight
+ *  0b000..2.0
+ *  0b001..2.125
+ *  0b010..2.25
+ *  0b011..2.375
+ *  0b100..2.5
+ *  0b101..2.625
+ *  0b110..2.75
+ *  0b111..2.875
+ */
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT_MASK)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS_MASK (0xF000U)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS_SHIFT (12U)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS_MASK)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS_MASK (0x10000U)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS_SHIFT (16U)
+/*! SNR_LQI_DIS - SNR LQI Disable
+ *  0b0..Normal operation.
+ *  0b1..The RX_DIG CCA/ED/LQI block ignores the AA match input which starts an LQI measurement.
+ */
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS_MASK)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE_MASK (0x20000U)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE_SHIFT (17U)
+/*! SEL_SNR_MODE - Select SNR Mode
+ *  0b0..SNR estimate
+ *  0b1..Mapped correlation magnitude
+ */
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE_MASK)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE_MASK (0x40000U)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE_SHIFT (18U)
+/*! MEAS_TRANS_TO_IDLE - Measurement Transition to IDLE
+ *  0b0..Module transitions to RSSI state
+ *  0b1..Module transitions to IDLE state
+ */
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE_MASK)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS_MASK (0x80000U)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS_SHIFT (19U)
+/*! CCA1_ED_EN_DIS - CCA1_ED_EN Disable
+ *  0b0..Normal operation
+ *  0b1..CCA1_ED_EN input is disabled
+ */
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS_MASK)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE_MASK (0x100000U)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE_SHIFT (20U)
+/*! MAN_MEAS_COMPLETE - Manual measurement complete
+ *  0b0..Normal operation
+ *  0b1..Manually asserts the measurement complete signal for the RX_DIG CCA/ED/LQI blocks. Intended to be used only for debug.
+ */
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE_MASK)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_NB_WB_OVRD_MASK (0x200000U)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_NB_WB_OVRD_SHIFT (21U)
+/*! NB_WB_OVRD - Narrowband Wideband Override
+ *  0b0..RSSI forced to be in Wideband mode if NB_WB_OVRD_EN is set
+ *  0b1..RSSI forced to be in Narrowband mode if NB_WB_OVRD_EN is set
+ */
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_NB_WB_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_NB_WB_OVRD_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_NB_WB_OVRD_MASK)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_NB_WB_OVRD_EN_MASK (0x400000U)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_NB_WB_OVRD_EN_SHIFT (22U)
+/*! NB_WB_OVRD_EN - Narrowband Wideband Override Enable
+ *  0b0..Normal operation
+ *  0b1..RSSI narrowband/wideband selection is via NB_WB_OVRD
+ */
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_NB_WB_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_NB_WB_OVRD_EN_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_NB_WB_OVRD_EN_MASK)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT_MASK (0xF000000U)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT_SHIFT (24U)
+/*! SNR_LQI_WEIGHT - SNR LQI Weight
+ *  0b0000..0.0
+ *  0b0001..1.0
+ *  0b0010..1.125
+ *  0b0011..1.25
+ *  0b0100..1.375
+ *  0b0101..1.5
+ *  0b0110..1.625
+ *  0b0111..1.75
+ *  0b1000..1.875
+ *  0b1001..2.0
+ *  0b1010..2.125
+ *  0b1011..2.25
+ *  0b1100..2.375
+ *  0b1101..2.5
+ *  0b1110..2.625
+ *  0b1111..2.75
+ */
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT_MASK)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS_MASK (0xF0000000U)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS_SHIFT (28U)
+#define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS_MASK)
+/*! @} */
+
+/*! @name CCA_ED_LQI_STAT_0 - RX_DIG CCA ED LQI Status Register 0 */
+/*! @{ */
+#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT_MASK (0xFFU)
+#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT_SHIFT (0U)
+#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT_MASK)
+#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT_MASK (0xFF00U)
+#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT_SHIFT (8U)
+#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT_MASK)
+#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT_MASK (0xFF0000U)
+#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT_SHIFT (16U)
+#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT_MASK)
+#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE_MASK (0x1000000U)
+#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE_SHIFT (24U)
+#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE_MASK)
+#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE_MASK (0x2000000U)
+#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE_SHIFT (25U)
+#define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE_MASK)
+/*! @} */
+
+/*! @name RX_CHF_COEF_0 - Receive Channel Filter Coefficient 0 */
+/*! @{ */
+#define XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0_MASK (0x3FU)
+#define XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0_SHIFT (0U)
+#define XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0_MASK)
+/*! @} */
+
+/*! @name RX_CHF_COEF_1 - Receive Channel Filter Coefficient 1 */
+/*! @{ */
+#define XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1_MASK (0x3FU)
+#define XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1_SHIFT (0U)
+#define XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1_MASK)
+/*! @} */
+
+/*! @name RX_CHF_COEF_2 - Receive Channel Filter Coefficient 2 */
+/*! @{ */
+#define XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2_MASK (0x7FU)
+#define XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2_SHIFT (0U)
+#define XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2_MASK)
+/*! @} */
+
+/*! @name RX_CHF_COEF_3 - Receive Channel Filter Coefficient 3 */
+/*! @{ */
+#define XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3_MASK (0x7FU)
+#define XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3_SHIFT (0U)
+#define XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3_MASK)
+/*! @} */
+
+/*! @name RX_CHF_COEF_4 - Receive Channel Filter Coefficient 4 */
+/*! @{ */
+#define XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4_MASK (0x7FU)
+#define XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4_SHIFT (0U)
+#define XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4_MASK)
+/*! @} */
+
+/*! @name RX_CHF_COEF_5 - Receive Channel Filter Coefficient 5 */
+/*! @{ */
+#define XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5_MASK (0x7FU)
+#define XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5_SHIFT (0U)
+#define XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5_MASK)
+/*! @} */
+
+/*! @name RX_CHF_COEF_6 - Receive Channel Filter Coefficient 6 */
+/*! @{ */
+#define XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6_MASK (0xFFU)
+#define XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6_SHIFT (0U)
+#define XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6_MASK)
+/*! @} */
+
+/*! @name RX_CHF_COEF_7 - Receive Channel Filter Coefficient 7 */
+/*! @{ */
+#define XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7_MASK (0xFFU)
+#define XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7_SHIFT (0U)
+#define XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7_MASK)
+/*! @} */
+
+/*! @name RX_CHF_COEF_8 - Receive Channel Filter Coefficient 8 */
+/*! @{ */
+#define XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8_MASK (0x1FFU)
+#define XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8_SHIFT (0U)
+#define XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8_MASK)
+/*! @} */
+
+/*! @name RX_CHF_COEF_9 - Receive Channel Filter Coefficient 9 */
+/*! @{ */
+#define XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9_MASK (0x1FFU)
+#define XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9_SHIFT (0U)
+#define XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9_MASK)
+/*! @} */
+
+/*! @name RX_CHF_COEF_10 - Receive Channel Filter Coefficient 10 */
+/*! @{ */
+#define XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10_MASK (0x3FFU)
+#define XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10_SHIFT (0U)
+#define XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10_MASK)
+/*! @} */
+
+/*! @name RX_CHF_COEF_11 - Receive Channel Filter Coefficient 11 */
+/*! @{ */
+#define XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11_MASK (0x3FFU)
+#define XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11_SHIFT (0U)
+#define XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11_MASK)
+/*! @} */
+
+/*! @name AGC_MAN_AGC_IDX - AGC Manual AGC Index */
+/*! @{ */
+#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_IDX_CMP_PHY_MASK (0x1FU)
+#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_IDX_CMP_PHY_SHIFT (0U)
+#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_IDX_CMP_PHY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_IDX_CMP_PHY_SHIFT)) & XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_IDX_CMP_PHY_MASK)
+#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_MASK (0x1F0000U)
+#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_SHIFT (16U)
+#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_SHIFT)) & XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_MASK)
+#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN_MASK (0x1000000U)
+#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN_SHIFT (24U)
+#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN_SHIFT)) & XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN_MASK)
+#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT_MASK (0x2000000U)
+#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT_SHIFT (25U)
+#define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT_SHIFT)) & XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT_MASK)
+/*! @} */
+
+/*! @name DC_RESID_CTRL - DC Residual Control */
+/*! @{ */
+#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_MASK (0x7FU)
+#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_SHIFT (0U)
+#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_MASK)
+#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_MASK (0xF00U)
+#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_SHIFT (8U)
+#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_MASK)
+#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_MASK (0x7000U)
+#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_SHIFT (12U)
+#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_MASK)
+#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_MASK (0x70000U)
+#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_SHIFT (16U)
+#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_MASK)
+#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_MASK (0x100000U)
+#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_SHIFT (20U)
+/*! DC_RESID_EXT_DC_EN - DC Residual External DC Enable
+ *  0b0..External DC disable. The DC Residual activates at a delay specified by DC_RESID_DLY after an AGC gain change pulse. The DC Residual is initialized with a DC offset of 0.
+ *  0b1..External DC enable. The DC residual activates after the DCOC's tracking hold timer expires. The DC Residual is initialized with the DC estimate from the DCOC tracking estimator.
+ */
+#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_MASK)
+#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_MASK (0x1F000000U)
+#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_SHIFT (24U)
+#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_MASK)
+/*! @} */
+
+/*! @name DC_RESID_EST - DC Residual Estimate */
+/*! @{ */
+#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_MASK (0x1FFFU)
+#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_SHIFT (0U)
+#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_SHIFT)) & XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_MASK)
+#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_MASK (0x1FFF0000U)
+#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_SHIFT (16U)
+#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_SHIFT)) & XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_MASK)
+/*! @} */
+
+/*! @name RX_RCCAL_CTRL0 - RX RC Calibration Control0 */
+/*! @{ */
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET_MASK (0xFU)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET_SHIFT (0U)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET_MASK)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL_MASK (0x1F0U)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL_SHIFT (4U)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL_MASK)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS_MASK (0x200U)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS_SHIFT (9U)
+/*! BBA_RCCAL_DIS - BBA RC Calibration Disable
+ *  0b0..BBA RC Calibration is enabled
+ *  0b1..BBA RC Calibration is disabled
+ */
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS_MASK)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY_MASK (0x3000U)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY_SHIFT (12U)
+/*! RCCAL_SMP_DLY - RC Calibration Sample Delay
+ *  0b00..The comp_out signal is sampled 0 clk cycle after sample signal is deasserted
+ *  0b01..The comp_out signal is sampled 1 clk cycle after sample signal is deasserted
+ *  0b10..The comp_out signal is sampled 2 clk cycle after sample signal is deasserted
+ *  0b11..The comp_out signal is sampled 3 clk cycle after sample signal is deasserted
+ */
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY_MASK)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV_MASK (0x8000U)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV_SHIFT (15U)
+/*! RCCAL_COMP_INV - RC Calibration comp_out Invert
+ *  0b0..The comp_out signal polarity is NOT inverted
+ *  0b1..The comp_out signal polarity is inverted
+ */
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV_MASK)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET_MASK (0xF0000U)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET_SHIFT (16U)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET_MASK)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL_MASK (0x1F00000U)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL_SHIFT (20U)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL_MASK)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS_MASK (0x2000000U)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS_SHIFT (25U)
+/*! TZA_RCCAL_DIS - TZA RC Calibration Disable
+ *  0b0..TZA RC Calibration is enabled
+ *  0b1..TZA RC Calibration is disabled
+ */
+#define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS_MASK)
+/*! @} */
+
+/*! @name RX_RCCAL_CTRL1 - RX RC Calibration Control1 */
+/*! @{ */
+#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET_MASK (0xFU)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET_SHIFT (0U)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET_MASK)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL_MASK (0x1F0U)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL_SHIFT (4U)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL_MASK)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS_MASK (0x200U)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS_SHIFT (9U)
+/*! ADC_RCCAL_DIS - ADC RC Calibration Disable
+ *  0b0..ADC RC Calibration is enabled
+ *  0b1..ADC RC Calibration is disabled
+ */
+#define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS_MASK)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET_MASK (0xF0000U)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET_SHIFT (16U)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET_MASK)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL_MASK (0x1F00000U)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL_SHIFT (20U)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL_MASK)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS_MASK (0x2000000U)
+#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS_SHIFT (25U)
+/*! BBA2_RCCAL_DIS - BBA2 RC Calibration Disable
+ *  0b0..BBA2 RC Calibration is enabled
+ *  0b1..BBA2 RC Calibration is disabled
+ */
+#define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS_MASK)
+/*! @} */
+
+/*! @name RX_RCCAL_STAT - RX RC Calibration Status */
+/*! @{ */
+#define XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE_MASK (0x1FU)
+#define XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE_SHIFT (0U)
+#define XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE_MASK)
+#define XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL_MASK (0x3E0U)
+#define XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL_SHIFT (5U)
+#define XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL_MASK)
+#define XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL_MASK (0x7C00U)
+#define XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL_SHIFT (10U)
+#define XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL_MASK)
+#define XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL_MASK (0x1F0000U)
+#define XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL_SHIFT (16U)
+#define XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL_MASK)
+#define XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL_MASK (0x3E00000U)
+#define XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL_SHIFT (21U)
+#define XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL_MASK)
+/*! @} */
+
+/*! @name AUXPLL_FCAL_CTRL - Aux PLL Frequency Calibration Control */
+/*! @{ */
+#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL_MASK (0x7FU)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL_SHIFT (0U)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL_MASK)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS_MASK (0x80U)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS_SHIFT (7U)
+/*! AUXPLL_DAC_CAL_ADJUST_DIS - Aux PLL Frequency Calibration Disable
+ *  0b0..Calibration is enabled
+ *  0b1..Calibration is disabled
+ */
+#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS_MASK)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT_MASK (0x100U)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT_SHIFT (8U)
+/*! FCAL_RUN_CNT - Aux PLL Frequency Calibration Run Count
+ *  0b0..Run count is 256 clock cycles
+ *  0b1..Run count is 512 clock cycles
+ */
+#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT_MASK)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV_MASK (0x200U)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV_SHIFT (9U)
+/*! FCAL_COMP_INV - Aux PLL Frequency Calibration Comparison Invert
+ *  0b0..(Default) The comparison associated with the count is not inverted.
+ *  0b1..The comparison associated with the count is inverted
+ */
+#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV_MASK)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY_MASK (0xC00U)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY_SHIFT (10U)
+/*! FCAL_SMP_DLY - Aux PLL Frequency Calibration Sample Delay
+ *  0b00..The count signal is sampled 1 clk cycle after fcal_run signal is deasserted
+ *  0b01..The count signal is sampled 2 clk cycle after fcal_run signal is deasserted
+ *  0b10..The count signal is sampled 3 clk cycle after fcal_run signal is deasserted
+ *  0b11..The count signal is sampled 4 clk cycle after fcal_run signal is deasserted
+ */
+#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY_MASK)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MASK (0x7F0000U)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_SHIFT (16U)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MASK)
+/*! @} */
+
+/*! @name AUXPLL_FCAL_CNT6 - Aux PLL Frequency Calibration Count 6 */
+/*! @{ */
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6_MASK (0x3FFU)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6_SHIFT (0U)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6_MASK)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF_MASK (0x3FF0000U)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF_SHIFT (16U)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF_MASK)
+/*! @} */
+
+/*! @name AUXPLL_FCAL_CNT5_4 - Aux PLL Frequency Calibration Count 5 and 4 */
+/*! @{ */
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4_MASK (0x3FFU)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4_SHIFT (0U)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4_MASK)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5_MASK (0x3FF0000U)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5_SHIFT (16U)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5_MASK)
+/*! @} */
+
+/*! @name AUXPLL_FCAL_CNT3_2 - Aux PLL Frequency Calibration Count 3 and 2 */
+/*! @{ */
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2_MASK (0x3FFU)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2_SHIFT (0U)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2_MASK)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3_MASK (0x3FF0000U)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3_SHIFT (16U)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3_MASK)
+/*! @} */
+
+/*! @name AUXPLL_FCAL_CNT1_0 - Aux PLL Frequency Calibration Count 1 and 0 */
+/*! @{ */
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0_MASK (0x3FFU)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0_SHIFT (0U)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0_MASK)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1_MASK (0x3FF0000U)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1_SHIFT (16U)
+#define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group XCVR_RX_DIG_Register_Masks */
+
+
+/* XCVR_RX_DIG - Peripheral instance base addresses */
+/** Peripheral XCVR_RX_DIG base address */
+#define XCVR_RX_DIG_BASE                         (0x41030000u)
+/** Peripheral XCVR_RX_DIG base pointer */
+#define XCVR_RX_DIG                              ((XCVR_RX_DIG_Type *)XCVR_RX_DIG_BASE)
+/** Array initializer of XCVR_RX_DIG peripheral base addresses */
+#define XCVR_RX_DIG_BASE_ADDRS                   { XCVR_RX_DIG_BASE }
+/** Array initializer of XCVR_RX_DIG peripheral base pointers */
+#define XCVR_RX_DIG_BASE_PTRS                    { XCVR_RX_DIG }
+
+/*!
+ * @}
+ */ /* end of group XCVR_RX_DIG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- XCVR_TSM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XCVR_TSM_Peripheral_Access_Layer XCVR_TSM Peripheral Access Layer
+ * @{
+ */
+
+/** XCVR_TSM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< TSM CONTROL, offset: 0x0 */
+  __IO uint32_t END_OF_SEQ;                        /**< TSM END OF SEQUENCE, offset: 0x4 */
+  __IO uint32_t PA_POWER;                          /**< PA POWER, offset: 0x8 */
+  __IO uint32_t PA_RAMP_TBL0;                      /**< PA RAMP TABLE 0, offset: 0xC */
+  __IO uint32_t PA_RAMP_TBL1;                      /**< PA RAMP TABLE 1, offset: 0x10 */
+  __IO uint32_t PA_RAMP_TBL2;                      /**< PA RAMP TABLE 2, offset: 0x14 */
+  __IO uint32_t PA_RAMP_TBL3;                      /**< PA RAMP TABLE 3, offset: 0x18 */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t RECYCLE_COUNT;                     /**< TSM RECYCLE COUNT, offset: 0x24 */
+  __IO uint32_t FAST_CTRL1;                        /**< TSM FAST WARMUP CONTROL 1, offset: 0x28 */
+  __IO uint32_t FAST_CTRL2;                        /**< TSM FAST WARMUP CONTROL 2, offset: 0x2C */
+  __IO uint32_t TIMING00;                          /**< TSM_TIMING00, offset: 0x30 */
+  __IO uint32_t TIMING01;                          /**< TSM_TIMING01, offset: 0x34 */
+  __IO uint32_t TIMING02;                          /**< TSM_TIMING02, offset: 0x38 */
+  __IO uint32_t TIMING03;                          /**< TSM_TIMING03, offset: 0x3C */
+  __IO uint32_t TIMING04;                          /**< TSM_TIMING04, offset: 0x40 */
+  __IO uint32_t TIMING05;                          /**< TSM_TIMING05, offset: 0x44 */
+  __IO uint32_t TIMING06;                          /**< TSM_TIMING06, offset: 0x48 */
+  __IO uint32_t TIMING07;                          /**< TSM_TIMING07, offset: 0x4C */
+  __IO uint32_t TIMING08;                          /**< TSM_TIMING08, offset: 0x50 */
+  __IO uint32_t TIMING09;                          /**< TSM_TIMING09, offset: 0x54 */
+  __IO uint32_t TIMING10;                          /**< TSM_TIMING10, offset: 0x58 */
+  __IO uint32_t TIMING11;                          /**< TSM_TIMING11, offset: 0x5C */
+  __IO uint32_t TIMING12;                          /**< TSM_TIMING12, offset: 0x60 */
+  __IO uint32_t TIMING13;                          /**< TSM_TIMING13, offset: 0x64 */
+  __IO uint32_t TIMING14;                          /**< TSM_TIMING14, offset: 0x68 */
+  __IO uint32_t TIMING15;                          /**< TSM_TIMING15, offset: 0x6C */
+  __IO uint32_t TIMING16;                          /**< TSM_TIMING16, offset: 0x70 */
+  __IO uint32_t TIMING17;                          /**< TSM_TIMING17, offset: 0x74 */
+  __IO uint32_t TIMING18;                          /**< TSM_TIMING18, offset: 0x78 */
+  __IO uint32_t TIMING19;                          /**< TSM_TIMING19, offset: 0x7C */
+  __IO uint32_t TIMING20;                          /**< TSM_TIMING20, offset: 0x80 */
+  __IO uint32_t TIMING21;                          /**< TSM_TIMING21, offset: 0x84 */
+  __IO uint32_t TIMING22;                          /**< TSM_TIMING22, offset: 0x88 */
+  __IO uint32_t TIMING23;                          /**< TSM_TIMING23, offset: 0x8C */
+  __IO uint32_t TIMING24;                          /**< TSM_TIMING24, offset: 0x90 */
+  __IO uint32_t TIMING25;                          /**< TSM_TIMING25, offset: 0x94 */
+  __IO uint32_t TIMING26;                          /**< TSM_TIMING26, offset: 0x98 */
+  __IO uint32_t TIMING27;                          /**< TSM_TIMING27, offset: 0x9C */
+  __IO uint32_t TIMING28;                          /**< TSM_TIMING28, offset: 0xA0 */
+  __IO uint32_t TIMING29;                          /**< TSM_TIMING29, offset: 0xA4 */
+  __IO uint32_t TIMING30;                          /**< TSM_TIMING30, offset: 0xA8 */
+  __IO uint32_t TIMING31;                          /**< TSM_TIMING31, offset: 0xAC */
+  __IO uint32_t TIMING32;                          /**< TSM_TIMING32, offset: 0xB0 */
+  __IO uint32_t TIMING33;                          /**< TSM_TIMING33, offset: 0xB4 */
+  __IO uint32_t TIMING34;                          /**< TSM_TIMING34, offset: 0xB8 */
+  __IO uint32_t TIMING35;                          /**< TSM_TIMING35, offset: 0xBC */
+  __IO uint32_t TIMING36;                          /**< TSM_TIMING36, offset: 0xC0 */
+  __IO uint32_t TIMING37;                          /**< TSM_TIMING37, offset: 0xC4 */
+  __IO uint32_t TIMING38;                          /**< TSM_TIMING38, offset: 0xC8 */
+  __IO uint32_t TIMING39;                          /**< TSM_TIMING39, offset: 0xCC */
+  __IO uint32_t TIMING40;                          /**< TSM_TIMING40, offset: 0xD0 */
+  __IO uint32_t TIMING41;                          /**< TSM_TIMING41, offset: 0xD4 */
+  __IO uint32_t TIMING42;                          /**< TSM_TIMING42, offset: 0xD8 */
+  __IO uint32_t TIMING43;                          /**< TSM_TIMING43, offset: 0xDC */
+  __IO uint32_t TIMING44;                          /**< TSM_TIMING44, offset: 0xE0 */
+  __IO uint32_t TIMING45;                          /**< TSM_TIMING45, offset: 0xE4 */
+  __IO uint32_t TIMING46;                          /**< TSM_TIMING46, offset: 0xE8 */
+  __IO uint32_t TIMING47;                          /**< TSM_TIMING47, offset: 0xEC */
+  __IO uint32_t TIMING48;                          /**< TSM_TIMING48, offset: 0xF0 */
+  __IO uint32_t TIMING49;                          /**< TSM_TIMING49, offset: 0xF4 */
+  __IO uint32_t TIMING50;                          /**< TSM_TIMING50, offset: 0xF8 */
+  __IO uint32_t TIMING51;                          /**< TSM_TIMING51, offset: 0xFC */
+  __IO uint32_t TIMING52;                          /**< TSM_TIMING52, offset: 0x100 */
+  __IO uint32_t TIMING53;                          /**< TSM_TIMING53, offset: 0x104 */
+  __IO uint32_t TIMING54;                          /**< TSM_TIMING54, offset: 0x108 */
+  __IO uint32_t TIMING55;                          /**< TSM_TIMING55, offset: 0x10C */
+  __IO uint32_t TIMING56;                          /**< TSM_TIMING56, offset: 0x110 */
+  __IO uint32_t TIMING57;                          /**< TSM_TIMING57, offset: 0x114 */
+  __IO uint32_t TIMING58;                          /**< TSM_TIMING58, offset: 0x118 */
+  __IO uint32_t OVRD0;                             /**< TSM OVERRIDE REGISTER 0, offset: 0x11C */
+  __IO uint32_t OVRD1;                             /**< TSM OVERRIDE REGISTER 1, offset: 0x120 */
+  __IO uint32_t OVRD2;                             /**< TSM OVERRIDE REGISTER 2, offset: 0x124 */
+  __IO uint32_t OVRD3;                             /**< TSM OVERRIDE REGISTER 3, offset: 0x128 */
+} XCVR_TSM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- XCVR_TSM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XCVR_TSM_Register_Masks XCVR_TSM Register Masks
+ * @{
+ */
+
+/*! @name CTRL - TSM CONTROL */
+/*! @{ */
+#define XCVR_TSM_CTRL_TSM_SOFT_RESET_MASK        (0x2U)
+#define XCVR_TSM_CTRL_TSM_SOFT_RESET_SHIFT       (1U)
+/*! TSM_SOFT_RESET - TSM Soft Reset
+ *  0b0..TSM Soft Reset removed. Normal operation.
+ *  0b1..TSM Soft Reset engaged. TSM forced to IDLE, and holds there until the bit is cleared.
+ */
+#define XCVR_TSM_CTRL_TSM_SOFT_RESET(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_TSM_SOFT_RESET_SHIFT)) & XCVR_TSM_CTRL_TSM_SOFT_RESET_MASK)
+#define XCVR_TSM_CTRL_FORCE_TX_EN_MASK           (0x4U)
+#define XCVR_TSM_CTRL_FORCE_TX_EN_SHIFT          (2U)
+/*! FORCE_TX_EN - Force Transmit Enable
+ *  0b0..TSM Idle
+ *  0b1..TSM executes a TX sequence
+ */
+#define XCVR_TSM_CTRL_FORCE_TX_EN(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_FORCE_TX_EN_SHIFT)) & XCVR_TSM_CTRL_FORCE_TX_EN_MASK)
+#define XCVR_TSM_CTRL_FORCE_RX_EN_MASK           (0x8U)
+#define XCVR_TSM_CTRL_FORCE_RX_EN_SHIFT          (3U)
+/*! FORCE_RX_EN - Force Receive Enable
+ *  0b0..TSM Idle
+ *  0b1..TSM executes a RX sequence
+ */
+#define XCVR_TSM_CTRL_FORCE_RX_EN(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_FORCE_RX_EN_SHIFT)) & XCVR_TSM_CTRL_FORCE_RX_EN_MASK)
+#define XCVR_TSM_CTRL_PA_RAMP_SEL_MASK           (0x30U)
+#define XCVR_TSM_CTRL_PA_RAMP_SEL_SHIFT          (4U)
+#define XCVR_TSM_CTRL_PA_RAMP_SEL(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_PA_RAMP_SEL_SHIFT)) & XCVR_TSM_CTRL_PA_RAMP_SEL_MASK)
+#define XCVR_TSM_CTRL_DATA_PADDING_EN_MASK       (0xC0U)
+#define XCVR_TSM_CTRL_DATA_PADDING_EN_SHIFT      (6U)
+/*! DATA_PADDING_EN - Data Padding Enable
+ *  0b00..Disable TX Data Padding
+ *  0b01..Enable TX Data Padding
+ */
+#define XCVR_TSM_CTRL_DATA_PADDING_EN(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_DATA_PADDING_EN_SHIFT)) & XCVR_TSM_CTRL_DATA_PADDING_EN_MASK)
+#define XCVR_TSM_CTRL_TSM_IRQ0_EN_MASK           (0x100U)
+#define XCVR_TSM_CTRL_TSM_IRQ0_EN_SHIFT          (8U)
+/*! TSM_IRQ0_EN - TSM_IRQ0 Enable/Disable bit
+ *  0b0..TSM_IRQ0 is disabled
+ *  0b1..TSM_IRQ0 is enabled
+ */
+#define XCVR_TSM_CTRL_TSM_IRQ0_EN(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_TSM_IRQ0_EN_SHIFT)) & XCVR_TSM_CTRL_TSM_IRQ0_EN_MASK)
+#define XCVR_TSM_CTRL_TSM_IRQ1_EN_MASK           (0x200U)
+#define XCVR_TSM_CTRL_TSM_IRQ1_EN_SHIFT          (9U)
+/*! TSM_IRQ1_EN - TSM_IRQ1 Enable/Disable bit
+ *  0b0..TSM_IRQ1 is disabled
+ *  0b1..TSM_IRQ1 is enabled
+ */
+#define XCVR_TSM_CTRL_TSM_IRQ1_EN(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_TSM_IRQ1_EN_SHIFT)) & XCVR_TSM_CTRL_TSM_IRQ1_EN_MASK)
+#define XCVR_TSM_CTRL_RAMP_DN_DELAY_MASK         (0xF000U)
+#define XCVR_TSM_CTRL_RAMP_DN_DELAY_SHIFT        (12U)
+#define XCVR_TSM_CTRL_RAMP_DN_DELAY(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_RAMP_DN_DELAY_SHIFT)) & XCVR_TSM_CTRL_RAMP_DN_DELAY_MASK)
+#define XCVR_TSM_CTRL_TX_ABORT_DIS_MASK          (0x10000U)
+#define XCVR_TSM_CTRL_TX_ABORT_DIS_SHIFT         (16U)
+#define XCVR_TSM_CTRL_TX_ABORT_DIS(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_TX_ABORT_DIS_SHIFT)) & XCVR_TSM_CTRL_TX_ABORT_DIS_MASK)
+#define XCVR_TSM_CTRL_RX_ABORT_DIS_MASK          (0x20000U)
+#define XCVR_TSM_CTRL_RX_ABORT_DIS_SHIFT         (17U)
+#define XCVR_TSM_CTRL_RX_ABORT_DIS(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_RX_ABORT_DIS_SHIFT)) & XCVR_TSM_CTRL_RX_ABORT_DIS_MASK)
+#define XCVR_TSM_CTRL_ABORT_ON_CTUNE_MASK        (0x40000U)
+#define XCVR_TSM_CTRL_ABORT_ON_CTUNE_SHIFT       (18U)
+/*! ABORT_ON_CTUNE - Abort On Coarse Tune Lock Detect Failure
+ *  0b0..don't allow TSM abort on Coarse Tune Unlock Detect
+ *  0b1..allow TSM abort on Coarse Tune Unlock Detect
+ */
+#define XCVR_TSM_CTRL_ABORT_ON_CTUNE(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_ABORT_ON_CTUNE_SHIFT)) & XCVR_TSM_CTRL_ABORT_ON_CTUNE_MASK)
+#define XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_MASK   (0x80000U)
+#define XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_SHIFT  (19U)
+/*! ABORT_ON_CYCLE_SLIP - Abort On Cycle Slip Lock Detect Failure
+ *  0b0..don't allow TSM abort on Cycle Slip Unlock Detect
+ *  0b1..allow TSM abort on Cycle Slip Unlock Detect
+ */
+#define XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_SHIFT)) & XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_MASK)
+#define XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_MASK    (0x100000U)
+#define XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_SHIFT   (20U)
+/*! ABORT_ON_FREQ_TARG - Abort On Frequency Target Lock Detect Failure
+ *  0b0..don't allow TSM abort on Frequency Target Unlock Detect
+ *  0b1..allow TSM abort on Frequency Target Unlock Detect
+ */
+#define XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_SHIFT)) & XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_MASK)
+#define XCVR_TSM_CTRL_BKPT_MASK                  (0xFF000000U)
+#define XCVR_TSM_CTRL_BKPT_SHIFT                 (24U)
+#define XCVR_TSM_CTRL_BKPT(x)                    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_BKPT_SHIFT)) & XCVR_TSM_CTRL_BKPT_MASK)
+/*! @} */
+
+/*! @name END_OF_SEQ - TSM END OF SEQUENCE */
+/*! @{ */
+#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK    (0xFFU)
+#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT   (0U)
+#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK)
+#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_MASK    (0xFF00U)
+#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_SHIFT   (8U)
+#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_MASK)
+#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK    (0xFF0000U)
+#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT   (16U)
+#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK)
+#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_MASK    (0xFF000000U)
+#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_SHIFT   (24U)
+#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_MASK)
+/*! @} */
+
+/*! @name PA_POWER - PA POWER */
+/*! @{ */
+#define XCVR_TSM_PA_POWER_PA_POWER_MASK          (0x3FU)
+#define XCVR_TSM_PA_POWER_PA_POWER_SHIFT         (0U)
+#define XCVR_TSM_PA_POWER_PA_POWER(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_POWER_PA_POWER_SHIFT)) & XCVR_TSM_PA_POWER_PA_POWER_MASK)
+/*! @} */
+
+/*! @name PA_RAMP_TBL0 - PA RAMP TABLE 0 */
+/*! @{ */
+#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0_MASK      (0x3FU)
+#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0_SHIFT     (0U)
+#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0_SHIFT)) & XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0_MASK)
+#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1_MASK      (0x3F00U)
+#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1_SHIFT     (8U)
+#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1_SHIFT)) & XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1_MASK)
+#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2_MASK      (0x3F0000U)
+#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2_SHIFT     (16U)
+#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2_SHIFT)) & XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2_MASK)
+#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3_MASK      (0x3F000000U)
+#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3_SHIFT     (24U)
+#define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3_SHIFT)) & XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3_MASK)
+/*! @} */
+
+/*! @name PA_RAMP_TBL1 - PA RAMP TABLE 1 */
+/*! @{ */
+#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4_MASK      (0x3FU)
+#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4_SHIFT     (0U)
+#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4_SHIFT)) & XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4_MASK)
+#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5_MASK      (0x3F00U)
+#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5_SHIFT     (8U)
+#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5_SHIFT)) & XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5_MASK)
+#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6_MASK      (0x3F0000U)
+#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6_SHIFT     (16U)
+#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6_SHIFT)) & XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6_MASK)
+#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7_MASK      (0x3F000000U)
+#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7_SHIFT     (24U)
+#define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7_SHIFT)) & XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7_MASK)
+/*! @} */
+
+/*! @name PA_RAMP_TBL2 - PA RAMP TABLE 2 */
+/*! @{ */
+#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP8_MASK      (0x3FU)
+#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP8_SHIFT     (0U)
+#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP8(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL2_PA_RAMP8_SHIFT)) & XCVR_TSM_PA_RAMP_TBL2_PA_RAMP8_MASK)
+#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP9_MASK      (0x3F00U)
+#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP9_SHIFT     (8U)
+#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP9(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL2_PA_RAMP9_SHIFT)) & XCVR_TSM_PA_RAMP_TBL2_PA_RAMP9_MASK)
+#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP10_MASK     (0x3F0000U)
+#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP10_SHIFT    (16U)
+#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP10(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL2_PA_RAMP10_SHIFT)) & XCVR_TSM_PA_RAMP_TBL2_PA_RAMP10_MASK)
+#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP11_MASK     (0x3F000000U)
+#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP11_SHIFT    (24U)
+#define XCVR_TSM_PA_RAMP_TBL2_PA_RAMP11(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL2_PA_RAMP11_SHIFT)) & XCVR_TSM_PA_RAMP_TBL2_PA_RAMP11_MASK)
+/*! @} */
+
+/*! @name PA_RAMP_TBL3 - PA RAMP TABLE 3 */
+/*! @{ */
+#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP12_MASK     (0x3FU)
+#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP12_SHIFT    (0U)
+#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP12(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL3_PA_RAMP12_SHIFT)) & XCVR_TSM_PA_RAMP_TBL3_PA_RAMP12_MASK)
+#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP13_MASK     (0x3F00U)
+#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP13_SHIFT    (8U)
+#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP13(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL3_PA_RAMP13_SHIFT)) & XCVR_TSM_PA_RAMP_TBL3_PA_RAMP13_MASK)
+#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP14_MASK     (0x3F0000U)
+#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP14_SHIFT    (16U)
+#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP14(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL3_PA_RAMP14_SHIFT)) & XCVR_TSM_PA_RAMP_TBL3_PA_RAMP14_MASK)
+#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP15_MASK     (0x3F000000U)
+#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP15_SHIFT    (24U)
+#define XCVR_TSM_PA_RAMP_TBL3_PA_RAMP15(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL3_PA_RAMP15_SHIFT)) & XCVR_TSM_PA_RAMP_TBL3_PA_RAMP15_MASK)
+/*! @} */
+
+/*! @name RECYCLE_COUNT - TSM RECYCLE COUNT */
+/*! @{ */
+#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_MASK (0xFFU)
+#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_SHIFT (0U)
+#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_SHIFT)) & XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_MASK)
+#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_MASK (0xFF00U)
+#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_SHIFT (8U)
+#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_SHIFT)) & XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_MASK)
+#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2_MASK (0xFF0000U)
+#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2_SHIFT (16U)
+#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2_SHIFT)) & XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2_MASK)
+/*! @} */
+
+/*! @name FAST_CTRL1 - TSM FAST WARMUP CONTROL 1 */
+/*! @{ */
+#define XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_MASK   (0x1U)
+#define XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_SHIFT  (0U)
+/*! FAST_TX_WU_EN - Fast TSM TX Warmup Enable
+ *  0b0..Fast TSM TX Warmups are disabled
+ *  0b1..Fast TSM TX Warmups are enabled, if the RF channel has not changed since the last TX warmup, and for BLE mode, the RF channel is not an advertising channel.
+ */
+#define XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_MASK)
+#define XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_MASK   (0x2U)
+#define XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_SHIFT  (1U)
+/*! FAST_RX_WU_EN - Fast TSM RX Warmup Enable
+ *  0b0..Fast TSM RX Warmups are disabled
+ *  0b1..Fast TSM RX Warmups are enabled, if the RF channel has not changed since the last RX warmup, and for BLE mode, the RF channel is not an advertising channel.
+ */
+#define XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_MASK)
+#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_MASK   (0x4U)
+#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_SHIFT  (2U)
+/*! FAST_RX2TX_EN - Fast TSM RX-to-TX Transition Enable
+ *  0b0..Disable Fast RX-to-TX transitions
+ *  0b1..Enable Fast RX-to-TX transitions (if fast_rx2tx_wu is asserted by 802.15.4 ZSM)
+ */
+#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_MASK)
+#define XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR_MASK   (0x8U)
+#define XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR_SHIFT  (3U)
+#define XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR_MASK)
+#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_MASK (0xFF00U)
+#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_SHIFT (8U)
+#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_MASK)
+/*! @} */
+
+/*! @name FAST_CTRL2 - TSM FAST WARMUP CONTROL 2 */
+/*! @{ */
+#define XCVR_TSM_FAST_CTRL2_FAST_START_TX_MASK   (0xFFU)
+#define XCVR_TSM_FAST_CTRL2_FAST_START_TX_SHIFT  (0U)
+#define XCVR_TSM_FAST_CTRL2_FAST_START_TX(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_START_TX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_START_TX_MASK)
+#define XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_MASK    (0xFF00U)
+#define XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_SHIFT   (8U)
+#define XCVR_TSM_FAST_CTRL2_FAST_DEST_TX(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_MASK)
+#define XCVR_TSM_FAST_CTRL2_FAST_START_RX_MASK   (0xFF0000U)
+#define XCVR_TSM_FAST_CTRL2_FAST_START_RX_SHIFT  (16U)
+#define XCVR_TSM_FAST_CTRL2_FAST_START_RX(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_START_RX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_START_RX_MASK)
+#define XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_MASK    (0xFF000000U)
+#define XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_SHIFT   (24U)
+#define XCVR_TSM_FAST_CTRL2_FAST_DEST_RX(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_MASK)
+/*! @} */
+
+/*! @name TIMING00 - TSM_TIMING00 */
+/*! @{ */
+#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING01 - TSM_TIMING01 */
+/*! @{ */
+#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING02 - TSM_TIMING02 */
+/*! @{ */
+#define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING03 - TSM_TIMING03 */
+/*! @{ */
+#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING04 - TSM_TIMING04 */
+/*! @{ */
+#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING05 - TSM_TIMING05 */
+/*! @{ */
+#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING06 - TSM_TIMING06 */
+/*! @{ */
+#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING07 - TSM_TIMING07 */
+/*! @{ */
+#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING08 - TSM_TIMING08 */
+/*! @{ */
+#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING09 - TSM_TIMING09 */
+/*! @{ */
+#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING10 - TSM_TIMING10 */
+/*! @{ */
+#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING11 - TSM_TIMING11 */
+/*! @{ */
+#define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING12 - TSM_TIMING12 */
+/*! @{ */
+#define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING13 - TSM_TIMING13 */
+/*! @{ */
+#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_TX_HI_SHIFT)) & XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_TX_HI_MASK)
+#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_TX_LO_SHIFT)) & XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_TX_LO_MASK)
+#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_RX_HI_SHIFT)) & XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_RX_HI_MASK)
+#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_RX_LO_SHIFT)) & XCVR_TSM_TIMING13_PLL_LOOP_IS_OPEN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING14 - TSM_TIMING14 */
+/*! @{ */
+#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING15 - TSM_TIMING15 */
+/*! @{ */
+#define XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI_MASK   (0xFFU)
+#define XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI_SHIFT  (0U)
+#define XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO_MASK   (0xFF00U)
+#define XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO_SHIFT  (8U)
+#define XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI_MASK   (0xFF0000U)
+#define XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI_SHIFT  (16U)
+#define XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO_MASK   (0xFF000000U)
+#define XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO_SHIFT  (24U)
+#define XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING16 - TSM_TIMING16 */
+/*! @{ */
+#define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING17 - TSM_TIMING17 */
+/*! @{ */
+#define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING18 - TSM_TIMING18 */
+/*! @{ */
+#define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI_MASK  (0xFFU)
+#define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO_MASK  (0xFF00U)
+#define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI_MASK  (0xFF0000U)
+#define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO_MASK  (0xFF000000U)
+#define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING19 - TSM_TIMING19 */
+/*! @{ */
+#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING20 - TSM_TIMING20 */
+/*! @{ */
+#define XCVR_TSM_TIMING20_SY_PD_EN_TX_HI_MASK    (0xFFU)
+#define XCVR_TSM_TIMING20_SY_PD_EN_TX_HI_SHIFT   (0U)
+#define XCVR_TSM_TIMING20_SY_PD_EN_TX_HI(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SY_PD_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING20_SY_PD_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING20_SY_PD_EN_TX_LO_MASK    (0xFF00U)
+#define XCVR_TSM_TIMING20_SY_PD_EN_TX_LO_SHIFT   (8U)
+#define XCVR_TSM_TIMING20_SY_PD_EN_TX_LO(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SY_PD_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING20_SY_PD_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING20_SY_PD_EN_RX_HI_MASK    (0xFF0000U)
+#define XCVR_TSM_TIMING20_SY_PD_EN_RX_HI_SHIFT   (16U)
+#define XCVR_TSM_TIMING20_SY_PD_EN_RX_HI(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SY_PD_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING20_SY_PD_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING20_SY_PD_EN_RX_LO_MASK    (0xFF000000U)
+#define XCVR_TSM_TIMING20_SY_PD_EN_RX_LO_SHIFT   (24U)
+#define XCVR_TSM_TIMING20_SY_PD_EN_RX_LO(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SY_PD_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING20_SY_PD_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING21 - TSM_TIMING21 */
+/*! @{ */
+#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING22 - TSM_TIMING22 */
+/*! @{ */
+#define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING23 - TSM_TIMING23 */
+/*! @{ */
+#define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING24 - TSM_TIMING24 */
+/*! @{ */
+#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING25 - TSM_TIMING25 */
+/*! @{ */
+#define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING26 - TSM_TIMING26 */
+/*! @{ */
+#define XCVR_TSM_TIMING26_TX_PA_EN_TX_HI_MASK    (0xFFU)
+#define XCVR_TSM_TIMING26_TX_PA_EN_TX_HI_SHIFT   (0U)
+#define XCVR_TSM_TIMING26_TX_PA_EN_TX_HI(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING26_TX_PA_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING26_TX_PA_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING26_TX_PA_EN_TX_LO_MASK    (0xFF00U)
+#define XCVR_TSM_TIMING26_TX_PA_EN_TX_LO_SHIFT   (8U)
+#define XCVR_TSM_TIMING26_TX_PA_EN_TX_LO(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING26_TX_PA_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING26_TX_PA_EN_TX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING27 - TSM_TIMING27 */
+/*! @{ */
+#define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING28 - TSM_TIMING28 */
+/*! @{ */
+#define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING29 - TSM_TIMING29 */
+/*! @{ */
+#define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING30 - TSM_TIMING30 */
+/*! @{ */
+#define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING31 - TSM_TIMING31 */
+/*! @{ */
+#define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING32 - TSM_TIMING32 */
+/*! @{ */
+#define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING33 - TSM_TIMING33 */
+/*! @{ */
+#define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING34 - TSM_TIMING34 */
+/*! @{ */
+#define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI_MASK  (0xFFU)
+#define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO_MASK  (0xFF00U)
+#define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI_MASK  (0xFF0000U)
+#define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO_MASK  (0xFF000000U)
+#define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING35 - TSM_TIMING35 */
+/*! @{ */
+#define XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI_MASK   (0xFFU)
+#define XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI_SHIFT  (0U)
+#define XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO_MASK   (0xFF00U)
+#define XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO_SHIFT  (8U)
+#define XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING36 - TSM_TIMING36 */
+/*! @{ */
+#define XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI_MASK   (0xFF0000U)
+#define XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI_SHIFT  (16U)
+#define XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO_MASK   (0xFF000000U)
+#define XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO_SHIFT  (24U)
+#define XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING37 - TSM_TIMING37 */
+/*! @{ */
+#define XCVR_TSM_TIMING37_RX_INIT_RX_HI_MASK     (0xFF0000U)
+#define XCVR_TSM_TIMING37_RX_INIT_RX_HI_SHIFT    (16U)
+#define XCVR_TSM_TIMING37_RX_INIT_RX_HI(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING37_RX_INIT_RX_HI_SHIFT)) & XCVR_TSM_TIMING37_RX_INIT_RX_HI_MASK)
+#define XCVR_TSM_TIMING37_RX_INIT_RX_LO_MASK     (0xFF000000U)
+#define XCVR_TSM_TIMING37_RX_INIT_RX_LO_SHIFT    (24U)
+#define XCVR_TSM_TIMING37_RX_INIT_RX_LO(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING37_RX_INIT_RX_LO_SHIFT)) & XCVR_TSM_TIMING37_RX_INIT_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING38 - TSM_TIMING38 */
+/*! @{ */
+#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING39 - TSM_TIMING39 */
+/*! @{ */
+#define XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI_MASK   (0xFF0000U)
+#define XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI_SHIFT  (16U)
+#define XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO_MASK   (0xFF000000U)
+#define XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO_SHIFT  (24U)
+#define XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING40 - TSM_TIMING40 */
+/*! @{ */
+#define XCVR_TSM_TIMING40_DCOC_EN_RX_HI_MASK     (0xFF0000U)
+#define XCVR_TSM_TIMING40_DCOC_EN_RX_HI_SHIFT    (16U)
+#define XCVR_TSM_TIMING40_DCOC_EN_RX_HI(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING40_DCOC_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING40_DCOC_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING40_DCOC_EN_RX_LO_MASK     (0xFF000000U)
+#define XCVR_TSM_TIMING40_DCOC_EN_RX_LO_SHIFT    (24U)
+#define XCVR_TSM_TIMING40_DCOC_EN_RX_LO(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING40_DCOC_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING40_DCOC_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING41 - TSM_TIMING41 */
+/*! @{ */
+#define XCVR_TSM_TIMING41_DCOC_INIT_RX_HI_MASK   (0xFF0000U)
+#define XCVR_TSM_TIMING41_DCOC_INIT_RX_HI_SHIFT  (16U)
+#define XCVR_TSM_TIMING41_DCOC_INIT_RX_HI(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING41_DCOC_INIT_RX_HI_SHIFT)) & XCVR_TSM_TIMING41_DCOC_INIT_RX_HI_MASK)
+#define XCVR_TSM_TIMING41_DCOC_INIT_RX_LO_MASK   (0xFF000000U)
+#define XCVR_TSM_TIMING41_DCOC_INIT_RX_LO_SHIFT  (24U)
+#define XCVR_TSM_TIMING41_DCOC_INIT_RX_LO(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING41_DCOC_INIT_RX_LO_SHIFT)) & XCVR_TSM_TIMING41_DCOC_INIT_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING42 - TSM_TIMING42 */
+/*! @{ */
+#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING43 - TSM_TIMING43 */
+/*! @{ */
+#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING44 - TSM_TIMING44 */
+/*! @{ */
+#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING45 - TSM_TIMING45 */
+/*! @{ */
+#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING46 - TSM_TIMING46 */
+/*! @{ */
+#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING47 - TSM_TIMING47 */
+/*! @{ */
+#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING48 - TSM_TIMING48 */
+/*! @{ */
+#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING49 - TSM_TIMING49 */
+/*! @{ */
+#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING50 - TSM_TIMING50 */
+/*! @{ */
+#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO_MASK)
+#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING51 - TSM_TIMING51 */
+/*! @{ */
+#define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING52 - TSM_TIMING52 */
+/*! @{ */
+#define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING53 - TSM_TIMING53 */
+/*! @{ */
+#define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING54 - TSM_TIMING54 */
+/*! @{ */
+#define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING55 - TSM_TIMING55 */
+/*! @{ */
+#define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING56 - TSM_TIMING56 */
+/*! @{ */
+#define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING57 - TSM_TIMING57 */
+/*! @{ */
+#define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI_MASK (0xFF0000U)
+#define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI_SHIFT (16U)
+#define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI_MASK)
+#define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO_MASK (0xFF000000U)
+#define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO_SHIFT (24U)
+#define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO_MASK)
+/*! @} */
+
+/*! @name TIMING58 - TSM_TIMING58 */
+/*! @{ */
+#define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI_MASK (0xFFU)
+#define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI_SHIFT (0U)
+#define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI_MASK)
+#define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO_MASK (0xFF00U)
+#define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO_SHIFT (8U)
+#define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO_MASK)
+/*! @} */
+
+/*! @name OVRD0 - TSM OVERRIDE REGISTER 0 */
+/*! @{ */
+#define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN_MASK (0x1U)
+#define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN_SHIFT (0U)
+/*! BB_LDO_HF_EN_OVRD_EN - Override control for BB_LDO_HF_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of BB_LDO_HF_EN_OVRD to override the signal "bb_ldo_hf_en".
+ */
+#define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_MASK    (0x2U)
+#define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_SHIFT   (1U)
+#define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_MASK (0x4U)
+#define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_SHIFT (2U)
+/*! BB_LDO_ADCDAC_EN_OVRD_EN - Override control for BB_LDO_ADCDAC_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of BB_LDO_ADCDAC_EN_OVRD to override the signal "bb_ldo_adcdac_en".
+ */
+#define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_MASK (0x8U)
+#define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_SHIFT (3U)
+#define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN_MASK (0x10U)
+#define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN_SHIFT (4U)
+/*! BB_LDO_BBA_EN_OVRD_EN - Override control for BB_LDO_BBA_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of BB_LDO_BBA_EN_OVRD to override the signal "bb_ldo_bba_en".
+ */
+#define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_MASK   (0x20U)
+#define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_SHIFT  (5U)
+#define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN_MASK (0x40U)
+#define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN_SHIFT (6U)
+/*! BB_LDO_PD_EN_OVRD_EN - Override control for BB_LDO_PD_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of BB_LDO_PD_EN_OVRD to override the signal "bb_ldo_pd_en".
+ */
+#define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_MASK    (0x80U)
+#define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_SHIFT   (7U)
+#define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN_MASK (0x100U)
+#define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN_SHIFT (8U)
+/*! BB_LDO_FDBK_EN_OVRD_EN - Override control for BB_LDO_FDBK_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of BB_LDO_FDBK_EN_OVRD to override the signal "bb_ldo_fdbk_en".
+ */
+#define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_MASK  (0x200U)
+#define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_SHIFT (9U)
+#define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN_MASK (0x400U)
+#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN_SHIFT (10U)
+/*! BB_LDO_VCOLO_EN_OVRD_EN - Override control for BB_LDO_VCOLO_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of BB_LDO_VCOLO_EN_OVRD to override the signal "bb_ldo_vcolo_en".
+ */
+#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_MASK (0x800U)
+#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_SHIFT (11U)
+#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN_MASK (0x1000U)
+#define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN_SHIFT (12U)
+/*! BB_LDO_VTREF_EN_OVRD_EN - Override control for BB_LDO_VTREF_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of BB_LDO_VTREF_EN_OVRD to override the signal "bb_ldo_vtref_en".
+ */
+#define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_MASK (0x2000U)
+#define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_SHIFT (13U)
+#define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN_MASK (0x4000U)
+#define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN_SHIFT (14U)
+/*! BB_LDO_FDBK_BLEED_EN_OVRD_EN - Override control for BB_LDO_FDBK_BLEED_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of BB_LDO_FDBK_BLEED_EN_OVRD to override the signal "bb_ldo_fdbk_bleed_en".
+ */
+#define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_MASK (0x8000U)
+#define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_SHIFT (15U)
+#define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN_MASK (0x10000U)
+#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN_SHIFT (16U)
+/*! BB_LDO_VCOLO_BLEED_EN_OVRD_EN - Override control for BB_LDO_VCOLO_BLEED_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of BB_LDO_VCOLO_BLEED_EN_OVRD to override the signal "bb_ldo_vcolo_bleed_en".
+ */
+#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_MASK (0x20000U)
+#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_SHIFT (17U)
+#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN_MASK (0x40000U)
+#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN_SHIFT (18U)
+/*! BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN - Override control for BB_LDO_VCOLO_FASTCHARGE_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of BB_LDO_VCOLO_FASTCHARGE_EN_OVRD to override the signal "bb_ldo_vcolo_fastcharge_en".
+ */
+#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_MASK (0x80000U)
+#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_SHIFT (19U)
+#define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN_MASK (0x100000U)
+#define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN_SHIFT (20U)
+/*! BB_XTAL_PLL_REF_CLK_EN_OVRD_EN - Override control for BB_XTAL_PLL_REF_CLK_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of BB_XTAL_PLL_REF_CLK_EN_OVRD to override the signal "bb_xtal_pll_ref_clk_en".
+ */
+#define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_MASK (0x200000U)
+#define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_SHIFT (21U)
+#define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN_MASK (0x400000U)
+#define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN_SHIFT (22U)
+/*! BB_XTAL_DAC_REF_CLK_EN_OVRD_EN - Override control for BB_XTAL_DAC_REF_CLK_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of BB_XTAL_DAC_REF_CLK_EN_OVRD to override the signal "bb_xtal_dac_ref_clk_en".
+ */
+#define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_MASK (0x800000U)
+#define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_SHIFT (23U)
+#define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN_MASK (0x1000000U)
+#define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN_SHIFT (24U)
+/*! BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN - Override control for BB_XTAL_AUXPLL_REF_CLK_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of BB_XTAL_AUXPLL_REF_CLK_EN_OVRD to override the signal "bb_xtal_auxpll_ref_clk_en".
+ */
+#define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_MASK (0x2000000U)
+#define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_SHIFT (25U)
+#define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD0_PLL_LOOP_IS_OPEN_OVRD_EN_MASK (0x4000000U)
+#define XCVR_TSM_OVRD0_PLL_LOOP_IS_OPEN_OVRD_EN_SHIFT (26U)
+/*! PLL_LOOP_IS_OPEN_OVRD_EN - Override control for PLL_LOOP_IS_OPEN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of PLL_LOOP_IS_OPEN_OVRD to override the signal "pll_loop_is_open".
+ */
+#define XCVR_TSM_OVRD0_PLL_LOOP_IS_OPEN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_PLL_LOOP_IS_OPEN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_PLL_LOOP_IS_OPEN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD0_PLL_LOOP_IS_OPEN_OVRD_MASK (0x8000000U)
+#define XCVR_TSM_OVRD0_PLL_LOOP_IS_OPEN_OVRD_SHIFT (27U)
+#define XCVR_TSM_OVRD0_PLL_LOOP_IS_OPEN_OVRD(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_PLL_LOOP_IS_OPEN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_PLL_LOOP_IS_OPEN_OVRD_MASK)
+#define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN_MASK (0x10000000U)
+#define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN_SHIFT (28U)
+/*! SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN - Override control for SY_PD_CYCLE_SLIP_LD_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of SY_PD_CYCLE_SLIP_LD_EN_OVRD to override the signal "sy_pd_cycle_slip_ld_en".
+ */
+#define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_MASK (0x20000000U)
+#define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_SHIFT (29U)
+#define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN_MASK    (0x40000000U)
+#define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN_SHIFT   (30U)
+/*! SY_VCO_EN_OVRD_EN - Override control for SY_VCO_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of SY_VCO_EN_OVRD to override the signal "sy_vco_en".
+ */
+#define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_MASK       (0x80000000U)
+#define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_SHIFT      (31U)
+#define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_MASK)
+/*! @} */
+
+/*! @name OVRD1 - TSM OVERRIDE REGISTER 1 */
+/*! @{ */
+#define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN_MASK (0x1U)
+#define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN_SHIFT (0U)
+/*! SY_LO_RX_BUF_EN_OVRD_EN - Override control for SY_LO_RX_BUF_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of SY_LO_RX_BUF_EN_OVRD to override the signal "sy_lo_rx_buf_en".
+ */
+#define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_MASK (0x2U)
+#define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_SHIFT (1U)
+#define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN_MASK (0x4U)
+#define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN_SHIFT (2U)
+/*! SY_LO_TX_BUF_EN_OVRD_EN - Override control for SY_LO_TX_BUF_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of SY_LO_TX_BUF_EN_OVRD to override the signal "sy_lo_tx_buf_en".
+ */
+#define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_MASK (0x8U)
+#define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_SHIFT (3U)
+#define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN_MASK   (0x10U)
+#define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN_SHIFT  (4U)
+/*! SY_DIVN_EN_OVRD_EN - Override control for SY_DIVN_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of SY_DIVN_EN_OVRD to override the signal "sy_divn_en".
+ */
+#define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_MASK      (0x20U)
+#define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_SHIFT     (5U)
+#define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN_MASK (0x40U)
+#define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN_SHIFT (6U)
+/*! SY_PD_FILTER_CHARGE_EN_OVRD_EN - Override control for SY_PD_FILTER_CHARGE_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of SY_PD_FILTER_CHARGE_EN_OVRD to override the signal "sy_pd_filter_charge_en".
+ */
+#define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_MASK (0x80U)
+#define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_SHIFT (7U)
+#define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN_MASK     (0x100U)
+#define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN_SHIFT    (8U)
+/*! SY_PD_EN_OVRD_EN - Override control for SY_PD_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of SY_PD_EN_OVRD to override the signal "sy_pd_en".
+ */
+#define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_MASK        (0x200U)
+#define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_SHIFT       (9U)
+#define XCVR_TSM_OVRD1_SY_PD_EN_OVRD(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_PD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_PD_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN_MASK (0x400U)
+#define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN_SHIFT (10U)
+/*! SY_LO_DIVN_EN_OVRD_EN - Override control for SY_LO_DIVN_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of SY_LO_DIVN_EN_OVRD to override the signal "sy_lo_divn_en".
+ */
+#define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_MASK   (0x800U)
+#define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_SHIFT  (11U)
+#define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN_MASK  (0x1000U)
+#define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN_SHIFT (12U)
+/*! SY_LO_RX_EN_OVRD_EN - Override control for SY_LO_RX_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of SY_LO_RX_EN_OVRD to override the signal "sy_lo_rx_en".
+ */
+#define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_MASK     (0x2000U)
+#define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_SHIFT    (13U)
+#define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN_MASK  (0x4000U)
+#define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN_SHIFT (14U)
+/*! SY_LO_TX_EN_OVRD_EN - Override control for SY_LO_TX_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of SY_LO_TX_EN_OVRD to override the signal "sy_lo_tx_en".
+ */
+#define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_MASK     (0x8000U)
+#define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_SHIFT    (15U)
+#define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN_MASK (0x10000U)
+#define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN_SHIFT (16U)
+/*! SY_DIVN_CAL_EN_OVRD_EN - Override control for SY_DIVN_CAL_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of SY_DIVN_CAL_EN_OVRD to override the signal "sy_divn_cal_en".
+ */
+#define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_MASK  (0x20000U)
+#define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_SHIFT (17U)
+#define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN_MASK  (0x40000U)
+#define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN_SHIFT (18U)
+/*! RX_MIXER_EN_OVRD_EN - Override control for RX_MIXER_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RX_MIXER_EN_OVRD to override the signal "rx_mixer_en".
+ */
+#define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_MASK     (0x80000U)
+#define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_SHIFT    (19U)
+#define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN_MASK     (0x100000U)
+#define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN_SHIFT    (20U)
+/*! TX_PA_EN_OVRD_EN - Override control for TX_PA_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of TX_PA_EN_OVRD to override the signal "tx_pa_en".
+ */
+#define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_MASK        (0x200000U)
+#define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_SHIFT       (21U)
+#define XCVR_TSM_OVRD1_TX_PA_EN_OVRD(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_TX_PA_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_TX_PA_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN_MASK  (0x400000U)
+#define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN_SHIFT (22U)
+/*! RX_ADC_I_EN_OVRD_EN - Override control for RX_ADC_I_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RX_ADC_I_EN_OVRD to override the signal "rx_adc_i_en".
+ */
+#define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_MASK     (0x800000U)
+#define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_SHIFT    (23U)
+#define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN_MASK  (0x1000000U)
+#define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN_SHIFT (24U)
+/*! RX_ADC_Q_EN_OVRD_EN - Override control for RX_ADC_Q_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RX_ADC_Q_EN_OVRD to override the signal "rx_adc_q_en".
+ */
+#define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_MASK     (0x2000000U)
+#define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_SHIFT    (25U)
+#define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN_MASK (0x4000000U)
+#define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN_SHIFT (26U)
+/*! RX_ADC_RESET_EN_OVRD_EN - Override control for RX_ADC_RESET_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RX_ADC_RESET_EN_OVRD to override the signal "rx_adc_reset_en".
+ */
+#define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_MASK (0x8000000U)
+#define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_SHIFT (27U)
+#define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN_MASK  (0x10000000U)
+#define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN_SHIFT (28U)
+/*! RX_BBA_I_EN_OVRD_EN - Override control for RX_BBA_I_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RX_BBA_I_EN_OVRD to override the signal "rx_bba_i_en".
+ */
+#define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_MASK     (0x20000000U)
+#define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_SHIFT    (29U)
+#define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN_MASK  (0x40000000U)
+#define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN_SHIFT (30U)
+/*! RX_BBA_Q_EN_OVRD_EN - Override control for RX_BBA_Q_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RX_BBA_Q_EN_OVRD to override the signal "rx_bba_q_en".
+ */
+#define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_MASK     (0x80000000U)
+#define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_SHIFT    (31U)
+#define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_MASK)
+/*! @} */
+
+/*! @name OVRD2 - TSM OVERRIDE REGISTER 2 */
+/*! @{ */
+#define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN_MASK (0x1U)
+#define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN_SHIFT (0U)
+/*! RX_BBA_PDET_EN_OVRD_EN - Override control for RX_BBA_PDET_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RX_BBA_PDET_EN_OVRD to override the signal "rx_bba_pdet_en".
+ */
+#define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_MASK  (0x2U)
+#define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_SHIFT (1U)
+#define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN_MASK (0x4U)
+#define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN_SHIFT (2U)
+/*! RX_BBA_DCOC_EN_OVRD_EN - Override control for RX_BBA_DCOC_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RX_BBA_DCOC_EN_OVRD to override the signal "rx_bba_dcoc_en".
+ */
+#define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_MASK  (0x8U)
+#define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_SHIFT (3U)
+#define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN_MASK    (0x10U)
+#define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN_SHIFT   (4U)
+/*! RX_LNA_EN_OVRD_EN - Override control for RX_LNA_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RX_LNA_EN_OVRD to override the signal "rx_lna_en".
+ */
+#define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_MASK       (0x20U)
+#define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_SHIFT      (5U)
+#define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN_MASK  (0x40U)
+#define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN_SHIFT (6U)
+/*! RX_TZA_I_EN_OVRD_EN - Override control for RX_TZA_I_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RX_TZA_I_EN_OVRD to override the signal "rx_tza_i_en".
+ */
+#define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_MASK     (0x80U)
+#define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_SHIFT    (7U)
+#define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN_MASK  (0x100U)
+#define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN_SHIFT (8U)
+/*! RX_TZA_Q_EN_OVRD_EN - Override control for RX_TZA_Q_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RX_TZA_Q_EN_OVRD to override the signal "rx_tza_q_en".
+ */
+#define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_MASK     (0x200U)
+#define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_SHIFT    (9U)
+#define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN_MASK (0x400U)
+#define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN_SHIFT (10U)
+/*! RX_TZA_PDET_EN_OVRD_EN - Override control for RX_TZA_PDET_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RX_TZA_PDET_EN_OVRD to override the signal "rx_tza_pdet_en".
+ */
+#define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_MASK  (0x800U)
+#define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_SHIFT (11U)
+#define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN_MASK (0x1000U)
+#define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN_SHIFT (12U)
+/*! RX_TZA_DCOC_EN_OVRD_EN - Override control for RX_TZA_DCOC_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RX_TZA_DCOC_EN_OVRD to override the signal "rx_tza_dcoc_en".
+ */
+#define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_MASK  (0x2000U)
+#define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_SHIFT (13U)
+/*! RX_TZA_DCOC_EN_OVRD - Override control for RX_TZA_DCOC_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RX_TZA_DCOC_EN_OVRD to override the signal "rx_tza_dcoc_en".
+ */
+#define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_MASK   (0x4000U)
+#define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_SHIFT  (14U)
+/*! PLL_DIG_EN_OVRD_EN - Override control for PLL_DIG_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of PLL_DIG_EN_OVRD to override the signal "pll_dig_en".
+ */
+#define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_MASK      (0x8000U)
+#define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_SHIFT     (15U)
+#define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_MASK    (0x10000U)
+#define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_SHIFT   (16U)
+/*! TX_DIG_EN_OVRD_EN - Override control for TX_DIG_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of TX_DIG_EN_OVRD to override the signal "tx_dig_en".
+ */
+#define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_MASK       (0x20000U)
+#define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_SHIFT      (17U)
+#define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_MASK    (0x40000U)
+#define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_SHIFT   (18U)
+/*! RX_DIG_EN_OVRD_EN - Override control for RX_DIG_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RX_DIG_EN_OVRD to override the signal "rx_dig_en".
+ */
+#define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_MASK       (0x80000U)
+#define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_SHIFT      (19U)
+#define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_MASK      (0x100000U)
+#define XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_SHIFT     (20U)
+/*! RX_INIT_OVRD_EN - Override control for RX_INIT
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RX_INIT_OVRD to override the signal "rx_init".
+ */
+#define XCVR_TSM_OVRD2_RX_INIT_OVRD_EN(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD2_RX_INIT_OVRD_MASK         (0x200000U)
+#define XCVR_TSM_OVRD2_RX_INIT_OVRD_SHIFT        (21U)
+#define XCVR_TSM_OVRD2_RX_INIT_OVRD(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_INIT_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_INIT_OVRD_MASK)
+#define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_MASK (0x400000U)
+#define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_SHIFT (22U)
+/*! SIGMA_DELTA_EN_OVRD_EN - Override control for SIGMA_DELTA_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of SIGMA_DELTA_EN_OVRD to override the signal "sigma_delta_en".
+ */
+#define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_MASK  (0x800000U)
+#define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_SHIFT (23U)
+#define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN_MASK    (0x1000000U)
+#define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN_SHIFT   (24U)
+/*! RX_PHY_EN_OVRD_EN - Override control for RX_PHY_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RX_PHY_EN_OVRD to override the signal "rx_phy_en".
+ */
+#define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_MASK       (0x2000000U)
+#define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_SHIFT      (25U)
+#define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_MASK      (0x4000000U)
+#define XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_SHIFT     (26U)
+/*! DCOC_EN_OVRD_EN - Override control for DCOC_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of DCOC_EN_OVRD to override the signal "dcoc_en".
+ */
+#define XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD2_DCOC_EN_OVRD_MASK         (0x8000000U)
+#define XCVR_TSM_OVRD2_DCOC_EN_OVRD_SHIFT        (27U)
+#define XCVR_TSM_OVRD2_DCOC_EN_OVRD(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_DCOC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_DCOC_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_MASK    (0x10000000U)
+#define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_SHIFT   (28U)
+/*! DCOC_INIT_OVRD_EN - Override control for DCOC_INIT
+ *  0b0..Normal operation.
+ *  0b1..Use the state of DCOC_INIT_OVRD to override the signal "dcoc_init".
+ */
+#define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_MASK       (0x20000000U)
+#define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_SHIFT      (29U)
+#define XCVR_TSM_OVRD2_DCOC_INIT_OVRD(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_DCOC_INIT_OVRD_SHIFT)) & XCVR_TSM_OVRD2_DCOC_INIT_OVRD_MASK)
+#define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_MASK (0x40000000U)
+#define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_SHIFT (30U)
+/*! FREQ_TARG_LD_EN_OVRD_EN - Override control for FREQ_TARG_LD_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of FREQ_TARG_LD_EN_OVRD to override the signal "freq_targ_ld_en".
+ */
+#define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_MASK (0x80000000U)
+#define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_SHIFT (31U)
+#define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_MASK)
+/*! @} */
+
+/*! @name OVRD3 - TSM OVERRIDE REGISTER 3 */
+/*! @{ */
+#define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_MASK (0x1U)
+#define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_SHIFT (0U)
+/*! TSM_SPARE0_EN_OVRD_EN - Override control for TSM_SPARE0_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of TSM_SPARE0_EN_OVRD to override the signal "tsm_spare0_en".
+ */
+#define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_MASK   (0x2U)
+#define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_SHIFT  (1U)
+#define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_MASK (0x4U)
+#define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_SHIFT (2U)
+/*! TSM_SPARE1_EN_OVRD_EN - Override control for TSM_SPARE1_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of TSM_SPARE1_EN_OVRD to override the signal "tsm_spare1_en".
+ */
+#define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_MASK   (0x8U)
+#define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_SHIFT  (3U)
+#define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_MASK (0x10U)
+#define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_SHIFT (4U)
+/*! TSM_SPARE2_EN_OVRD_EN - Override control for TSM_SPARE2_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of TSM_SPARE2_EN_OVRD to override the signal "tsm_spare2_en".
+ */
+#define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_MASK   (0x20U)
+#define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_SHIFT  (5U)
+#define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_MASK (0x40U)
+#define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_SHIFT (6U)
+/*! TSM_SPARE3_EN_OVRD_EN - Override control for TSM_SPARE3_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of TSM_SPARE3_EN_OVRD to override the signal "tsm_spare3_en".
+ */
+#define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_MASK   (0x80U)
+#define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_SHIFT  (7U)
+#define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN_MASK (0x100U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN_SHIFT (8U)
+/*! RXTX_AUXPLL_BIAS_EN_OVRD_EN - Override control for RXTX_AUXPLL_BIAS_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RXTX_AUXPLL_BIAS_EN_OVRD to override the signal "rxtx_auxpll_bias_en".
+ */
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_MASK (0x200U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_SHIFT (9U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN_MASK (0x400U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN_SHIFT (10U)
+/*! RXTX_AUXPLL_VCO_EN_OVRD_EN - Override control for RXTX_AUXPLL_VCO_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RXTX_AUXPLL_VCO_EN_OVRD to override the signal "rxtx_auxpll_vco_en".
+ */
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_MASK (0x800U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_SHIFT (11U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN_MASK (0x1000U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN_SHIFT (12U)
+/*! RXTX_AUXPLL_FCAL_EN_OVRD_EN - Override control for RXTX_AUXPLL_FCAL_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RXTX_AUXPLL_FCAL_EN_OVRD to override the signal "rxtx_auxpll_fcal_en".
+ */
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_MASK (0x2000U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_SHIFT (13U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN_MASK (0x4000U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN_SHIFT (14U)
+/*! RXTX_AUXPLL_LF_EN_OVRD_EN - Override control for RXTX_AUXPLL_LF_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RXTX_AUXPLL_LF_EN_OVRD to override the signal "rxtx_auxpll_lf_en".
+ */
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_MASK (0x8000U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_SHIFT (15U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN_MASK (0x10000U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN_SHIFT (16U)
+/*! RXTX_AUXPLL_PD_EN_OVRD_EN - Override control for RXTX_AUXPLL_PD_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RXTX_AUXPLL_PD_EN_OVRD to override the signal "rxtx_auxpll_pd_en".
+ */
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_MASK (0x20000U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_SHIFT (17U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN_MASK (0x40000U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN_SHIFT (18U)
+/*! RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN - Override control for RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD to override the signal "rxtx_auxpll_pd_lf_filter_charge_en".
+ */
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_MASK (0x80000U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_SHIFT (19U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN_MASK (0x100000U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN_SHIFT (20U)
+/*! RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN - Override control for RXTX_AUXPLL_ADC_BUF_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RXTX_AUXPLL_ADC_BUF_EN_OVRD to override the signal "rxtx_auxpll_adc_buf_en".
+ */
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_MASK (0x200000U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_SHIFT (21U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN_MASK (0x400000U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN_SHIFT (22U)
+/*! RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN - Override control for RXTX_AUXPLL_DIG_BUF_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RXTX_AUXPLL_DIG_BUF_EN_OVRD to override the signal "rxtx_auxpll_dig_buf_en".
+ */
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_MASK (0x800000U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_SHIFT (23U)
+#define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN_MASK (0x1000000U)
+#define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN_SHIFT (24U)
+/*! RXTX_RCCAL_EN_OVRD_EN - Override control for RXTX_RCCAL_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RXTX_RCCAL_EN_OVRD to override the signal "rxtx_rccal_en".
+ */
+#define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_MASK   (0x2000000U)
+#define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_SHIFT  (25U)
+#define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN_MASK (0x4000000U)
+#define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN_SHIFT (26U)
+/*! TX_HPM_DAC_EN_OVRD_EN - Override control for TX_HPM_DAC_EN
+ *  0b0..Normal operation.
+ *  0b1..Use the state of TX_HPM_DAC_EN_OVRD to override the signal "tx_hpm_dac_en".
+ */
+#define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_MASK   (0x8000000U)
+#define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_SHIFT  (27U)
+#define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_MASK)
+#define XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_MASK      (0x10000000U)
+#define XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_SHIFT     (28U)
+/*! TX_MODE_OVRD_EN - Override control for TX_MODE
+ *  0b0..Normal operation.
+ *  0b1..Use the state of TX_MODE_OVRD to override the signal "tx_mode".
+ */
+#define XCVR_TSM_OVRD3_TX_MODE_OVRD_EN(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD3_TX_MODE_OVRD_MASK         (0x20000000U)
+#define XCVR_TSM_OVRD3_TX_MODE_OVRD_SHIFT        (29U)
+#define XCVR_TSM_OVRD3_TX_MODE_OVRD(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TX_MODE_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TX_MODE_OVRD_MASK)
+#define XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_MASK      (0x40000000U)
+#define XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_SHIFT     (30U)
+/*! RX_MODE_OVRD_EN - Override control for RX_MODE
+ *  0b0..Normal operation.
+ *  0b1..Use the state of RX_MODE_OVRD to override the signal "rx_mode".
+ */
+#define XCVR_TSM_OVRD3_RX_MODE_OVRD_EN(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_MASK)
+#define XCVR_TSM_OVRD3_RX_MODE_OVRD_MASK         (0x80000000U)
+#define XCVR_TSM_OVRD3_RX_MODE_OVRD_SHIFT        (31U)
+#define XCVR_TSM_OVRD3_RX_MODE_OVRD(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RX_MODE_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RX_MODE_OVRD_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group XCVR_TSM_Register_Masks */
+
+
+/* XCVR_TSM - Peripheral instance base addresses */
+/** Peripheral XCVR_TSM base address */
+#define XCVR_TSM_BASE                            (0x410302C0u)
+/** Peripheral XCVR_TSM base pointer */
+#define XCVR_TSM                                 ((XCVR_TSM_Type *)XCVR_TSM_BASE)
+/** Array initializer of XCVR_TSM peripheral base addresses */
+#define XCVR_TSM_BASE_ADDRS                      { XCVR_TSM_BASE }
+/** Array initializer of XCVR_TSM peripheral base pointers */
+#define XCVR_TSM_BASE_PTRS                       { XCVR_TSM }
+
+/*!
+ * @}
+ */ /* end of group XCVR_TSM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- XCVR_TX_DIG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XCVR_TX_DIG_Peripheral_Access_Layer XCVR_TX_DIG Peripheral Access Layer
+ * @{
+ */
+
+/** XCVR_TX_DIG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< TX Digital Control, offset: 0x0 */
+  __IO uint32_t DATA_PADDING;                      /**< TX Data Padding, offset: 0x4 */
+  __IO uint32_t GFSK_CTRL;                         /**< TX GFSK Modulator Control, offset: 0x8 */
+  __IO uint32_t GFSK_COEFF2;                       /**< TX GFSK Filter Coefficients 2, offset: 0xC */
+  __IO uint32_t GFSK_COEFF1;                       /**< TX GFSK Filter Coefficients 1, offset: 0x10 */
+  __IO uint32_t FSK_SCALE;                         /**< TX FSK Modulation Levels, offset: 0x14 */
+  __IO uint32_t DFT_PATTERN;                       /**< TX DFT Modulation Pattern, offset: 0x18 */
+} XCVR_TX_DIG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- XCVR_TX_DIG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XCVR_TX_DIG_Register_Masks XCVR_TX_DIG Register Masks
+ * @{
+ */
+
+/*! @name CTRL - TX Digital Control */
+/*! @{ */
+#define XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK     (0xFU)
+#define XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_SHIFT    (0U)
+/*! RADIO_DFT_MODE - Radio DFT Modes
+ *  0b0000..Normal Radio Operation, DFT not engaged.
+ *  0b0001..Carrier Frequency Only
+ *  0b0010..Pattern Register GFSK
+ *  0b0011..LFSR GFSK
+ *  0b0100..Pattern Register FSK
+ *  0b0101..LFSR FSK
+ *  0b0110..Pattern Register O-QPSK
+ *  0b0111..LFSR O-QPSK
+ *  0b1000..LFSR 802.15.4 Symbols
+ *  0b1001..PLL Modulation from RAM
+ *  0b1010..PLL Coarse Tune BIST
+ *  0b1011..PLL Frequency Synthesizer BIST
+ *  0b1100..High Port DAC BIST
+ *  0b1101..VCO Frequency Meter
+ *  0b1110..Reserved
+ *  0b1111..Reserved
+ */
+#define XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_SHIFT)) & XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK)
+#define XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK        (0x70U)
+#define XCVR_TX_DIG_CTRL_LFSR_LENGTH_SHIFT       (4U)
+/*! LFSR_LENGTH - LFSR Length
+ *  0b000..LFSR 9, tap mask 100010000
+ *  0b001..LFSR 10, tap mask 1001000000
+ *  0b010..LFSR 11, tap mask 11101000000
+ *  0b011..LFSR 13, tap mask 1101100000000
+ *  0b100..LFSR 15, tap mask 111010000000000
+ *  0b101..LFSR 17, tap mask 11110000000000000
+ *  0b110..Reserved
+ *  0b111..Reserved
+ */
+#define XCVR_TX_DIG_CTRL_LFSR_LENGTH(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_LFSR_LENGTH_SHIFT)) & XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK)
+#define XCVR_TX_DIG_CTRL_LFSR_EN_MASK            (0x80U)
+#define XCVR_TX_DIG_CTRL_LFSR_EN_SHIFT           (7U)
+#define XCVR_TX_DIG_CTRL_LFSR_EN(x)              (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_LFSR_EN_SHIFT)) & XCVR_TX_DIG_CTRL_LFSR_EN_MASK)
+#define XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK        (0x700U)
+#define XCVR_TX_DIG_CTRL_DFT_CLK_SEL_SHIFT       (8U)
+/*! DFT_CLK_SEL - DFT Clock Selection
+ *  0b000..62.5 kHz
+ *  0b001..125 kHz
+ *  0b010..250 kHz
+ *  0b011..500 kHz
+ *  0b100..1 MHz
+ *  0b101..2 MHz
+ *  0b110..4 MHz
+ *  0b111..RF OSC Clock
+ */
+#define XCVR_TX_DIG_CTRL_DFT_CLK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_DFT_CLK_SEL_SHIFT)) & XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK)
+#define XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK          (0x800U)
+#define XCVR_TX_DIG_CTRL_TX_DFT_EN_SHIFT         (11U)
+#define XCVR_TX_DIG_CTRL_TX_DFT_EN(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_TX_DFT_EN_SHIFT)) & XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK)
+#define XCVR_TX_DIG_CTRL_SOC_TEST_SEL_MASK       (0x3000U)
+#define XCVR_TX_DIG_CTRL_SOC_TEST_SEL_SHIFT      (12U)
+/*! SOC_TEST_SEL - Radio Clock Selector for SoC RF Clock Tests
+ *  0b00..No Clock Selected
+ *  0b01..PLL Sigma Delta Clock, divided by 2
+ *  0b10..Auxiliary PLL Clock, divided by 2
+ *  0b11..RF Ref Osc clock, divided by 2
+ */
+#define XCVR_TX_DIG_CTRL_SOC_TEST_SEL(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_SOC_TEST_SEL_SHIFT)) & XCVR_TX_DIG_CTRL_SOC_TEST_SEL_MASK)
+#define XCVR_TX_DIG_CTRL_TX_CAPTURE_POL_MASK     (0x10000U)
+#define XCVR_TX_DIG_CTRL_TX_CAPTURE_POL_SHIFT    (16U)
+#define XCVR_TX_DIG_CTRL_TX_CAPTURE_POL(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_TX_CAPTURE_POL_SHIFT)) & XCVR_TX_DIG_CTRL_TX_CAPTURE_POL_MASK)
+#define XCVR_TX_DIG_CTRL_ZERO_FDEV_MASK          (0x80000U)
+#define XCVR_TX_DIG_CTRL_ZERO_FDEV_SHIFT         (19U)
+#define XCVR_TX_DIG_CTRL_ZERO_FDEV(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_ZERO_FDEV_SHIFT)) & XCVR_TX_DIG_CTRL_ZERO_FDEV_MASK)
+#define XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_MASK      (0xFFC00000U)
+#define XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_SHIFT     (22U)
+#define XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_SHIFT)) & XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_MASK)
+/*! @} */
+
+/*! @name DATA_PADDING - TX Data Padding */
+/*! @{ */
+#define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0_MASK (0xFFU)
+#define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0_SHIFT (0U)
+#define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0_MASK)
+#define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1_MASK (0xFF00U)
+#define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1_SHIFT (8U)
+#define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1_MASK)
+#define XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT_MASK (0x7FFF0000U)
+#define XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT_SHIFT (16U)
+#define XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT_MASK)
+#define XCVR_TX_DIG_DATA_PADDING_LRM_MASK        (0x80000000U)
+#define XCVR_TX_DIG_DATA_PADDING_LRM_SHIFT       (31U)
+#define XCVR_TX_DIG_DATA_PADDING_LRM(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_LRM_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_LRM_MASK)
+/*! @} */
+
+/*! @name GFSK_CTRL - TX GFSK Modulator Control */
+/*! @{ */
+#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_MASK (0xFFFFU)
+#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_SHIFT (0U)
+#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_MASK)
+#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MI_MASK       (0x30000U)
+#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MI_SHIFT      (16U)
+/*! GFSK_MI - GFSK Modulation Index
+ *  0b00..0.32
+ *  0b01..0.50
+ *  0b10..0.70
+ *  0b11..1.00
+ */
+#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_MI_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_MI_MASK)
+#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD_MASK      (0x100000U)
+#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD_SHIFT     (20U)
+#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD_MASK)
+#define XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD_MASK      (0x200000U)
+#define XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD_SHIFT     (21U)
+#define XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD_MASK)
+#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING_MASK (0x7000000U)
+#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING_SHIFT (24U)
+/*! GFSK_MOD_INDEX_SCALING - GFSK Modulation Index Scaling Factor
+ *  0b000..1
+ *  0b001..1 + 1/32
+ *  0b010..1 + 1/16
+ *  0b011..1 + 1/8
+ *  0b100..1 - 1/32
+ *  0b101..1 - 1/16
+ *  0b110..1 - 1/8
+ *  0b111..Reserved
+ */
+#define XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING_MASK)
+#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN_MASK (0x10000000U)
+#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN_SHIFT (28U)
+#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN_MASK)
+#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD_MASK (0x20000000U)
+#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD_SHIFT (29U)
+#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD_MASK)
+#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD_MASK (0x40000000U)
+#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD_SHIFT (30U)
+#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD_MASK)
+#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD_MASK (0x80000000U)
+#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD_SHIFT (31U)
+#define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD_MASK)
+/*! @} */
+
+/*! @name GFSK_COEFF2 - TX GFSK Filter Coefficients 2 */
+/*! @{ */
+#define XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2_MASK (0xFFFFFFFFU)
+#define XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2_SHIFT (0U)
+#define XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2_MASK)
+/*! @} */
+
+/*! @name GFSK_COEFF1 - TX GFSK Filter Coefficients 1 */
+/*! @{ */
+#define XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1_MASK (0xFFFFFFFFU)
+#define XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1_SHIFT (0U)
+#define XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1_MASK)
+/*! @} */
+
+/*! @name FSK_SCALE - TX FSK Modulation Levels */
+/*! @{ */
+#define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0_MASK (0x1FFFU)
+#define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0_SHIFT (0U)
+#define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0_SHIFT)) & XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0_MASK)
+#define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1_MASK (0x1FFF0000U)
+#define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1_SHIFT (16U)
+#define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1_SHIFT)) & XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1_MASK)
+#define XCVR_TX_DIG_FSK_SCALE_FSK_BITRATE_SCALE_DISABLE_MASK (0x80000000U)
+#define XCVR_TX_DIG_FSK_SCALE_FSK_BITRATE_SCALE_DISABLE_SHIFT (31U)
+#define XCVR_TX_DIG_FSK_SCALE_FSK_BITRATE_SCALE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_FSK_SCALE_FSK_BITRATE_SCALE_DISABLE_SHIFT)) & XCVR_TX_DIG_FSK_SCALE_FSK_BITRATE_SCALE_DISABLE_MASK)
+/*! @} */
+
+/*! @name DFT_PATTERN - TX DFT Modulation Pattern */
+/*! @{ */
+#define XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN_MASK (0xFFFFFFFFU)
+#define XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN_SHIFT (0U)
+#define XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN_SHIFT)) & XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group XCVR_TX_DIG_Register_Masks */
+
+
+/* XCVR_TX_DIG - Peripheral instance base addresses */
+/** Peripheral XCVR_TX_DIG base address */
+#define XCVR_TX_DIG_BASE                         (0x41030200u)
+/** Peripheral XCVR_TX_DIG base pointer */
+#define XCVR_TX_DIG                              ((XCVR_TX_DIG_Type *)XCVR_TX_DIG_BASE)
+/** Array initializer of XCVR_TX_DIG peripheral base addresses */
+#define XCVR_TX_DIG_BASE_ADDRS                   { XCVR_TX_DIG_BASE }
+/** Array initializer of XCVR_TX_DIG peripheral base pointers */
+#define XCVR_TX_DIG_BASE_PTRS                    { XCVR_TX_DIG }
+
+/*!
+ * @}
+ */ /* end of group XCVR_TX_DIG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- XCVR_WOR Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XCVR_WOR_Peripheral_Access_Layer XCVR_WOR Peripheral Access Layer
+ * @{
+ */
+
+/** XCVR_WOR - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t WOR_CTRL;                          /**< WAKE-ON-RADIO CONTROL REGISTER, offset: 0x0 */
+  __IO uint32_t WOR_TIMEOUT;                       /**< WAKE-ON-RADIO TIMEOUT REGISTER, offset: 0x4 */
+  __I  uint32_t TIMESTAMP1;                        /**< WAKE-ON-RADIO TIMESTAMP 1, offset: 0x8 */
+  __I  uint32_t TIMESTAMP2;                        /**< WAKE-ON-RADIO TIMESTAMP 2, offset: 0xC */
+  __I  uint32_t TIMESTAMP3;                        /**< WAKE-ON-RADIO TIMESTAMP 3, offset: 0x10 */
+  __I  uint32_t WOR_STATUS;                        /**< WAKE-ON-RADIO STATUS REGISTER, offset: 0x14 */
+  __IO uint32_t WW_CTRL;                           /**< WINDOW-WIDENING CONTROL REGISTER, offset: 0x18 */
+  __IO uint32_t HOP_CTRL;                          /**< FREQUENCY HOP CONTROL REGISTER, offset: 0x1C */
+  __IO uint32_t SLOT0_DESC0;                       /**< SLOT 0 DESCRIPTOR (LSB), offset: 0x20 */
+  __IO uint32_t SLOT0_DESC1;                       /**< SLOT 0 DESCRIPTOR (MSB), offset: 0x24 */
+  __IO uint32_t SLOT1_DESC0;                       /**< SLOT 1 DESCRIPTOR (LSB), offset: 0x28 */
+  __IO uint32_t SLOT1_DESC1;                       /**< SLOT 1 DESCRIPTOR (MSB), offset: 0x2C */
+  __IO uint32_t SLOT2_DESC0;                       /**< SLOT 2 DESCRIPTOR (LSB), offset: 0x30 */
+  __IO uint32_t SLOT2_DESC1;                       /**< SLOT 2 DESCRIPTOR (MSB), offset: 0x34 */
+  __IO uint32_t SLOT3_DESC0;                       /**< SLOT 3 DESCRIPTOR (LSB), offset: 0x38 */
+  __IO uint32_t SLOT3_DESC1;                       /**< SLOT 3 DESCRIPTOR (MSB), offset: 0x3C */
+} XCVR_WOR_Type;
+
+/* ----------------------------------------------------------------------------
+   -- XCVR_WOR Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XCVR_WOR_Register_Masks XCVR_WOR Register Masks
+ * @{
+ */
+
+/*! @name WOR_CTRL - WAKE-ON-RADIO CONTROL REGISTER */
+/*! @{ */
+#define XCVR_WOR_WOR_CTRL_WOR_EN_MASK            (0x1U)
+#define XCVR_WOR_WOR_CTRL_WOR_EN_SHIFT           (0U)
+#define XCVR_WOR_WOR_CTRL_WOR_EN(x)              (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_CTRL_WOR_EN_SHIFT)) & XCVR_WOR_WOR_CTRL_WOR_EN_MASK)
+#define XCVR_WOR_WOR_CTRL_SCHEDULING_MODE_MASK   (0x2U)
+#define XCVR_WOR_WOR_CTRL_SCHEDULING_MODE_SHIFT  (1U)
+#define XCVR_WOR_WOR_CTRL_SCHEDULING_MODE(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_CTRL_SCHEDULING_MODE_SHIFT)) & XCVR_WOR_WOR_CTRL_SCHEDULING_MODE_MASK)
+#define XCVR_WOR_WOR_CTRL_WOR_PROTOCOL_MASK      (0xCU)
+#define XCVR_WOR_WOR_CTRL_WOR_PROTOCOL_SHIFT     (2U)
+#define XCVR_WOR_WOR_CTRL_WOR_PROTOCOL(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_CTRL_WOR_PROTOCOL_SHIFT)) & XCVR_WOR_WOR_CTRL_WOR_PROTOCOL_MASK)
+#define XCVR_WOR_WOR_CTRL_SLOTS_USED_MASK        (0x70U)
+#define XCVR_WOR_WOR_CTRL_SLOTS_USED_SHIFT       (4U)
+#define XCVR_WOR_WOR_CTRL_SLOTS_USED(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_CTRL_SLOTS_USED_SHIFT)) & XCVR_WOR_WOR_CTRL_SLOTS_USED_MASK)
+#define XCVR_WOR_WOR_CTRL_SKIP_FIRST_DSM_MASK    (0x80U)
+#define XCVR_WOR_WOR_CTRL_SKIP_FIRST_DSM_SHIFT   (7U)
+#define XCVR_WOR_WOR_CTRL_SKIP_FIRST_DSM(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_CTRL_SKIP_FIRST_DSM_SHIFT)) & XCVR_WOR_WOR_CTRL_SKIP_FIRST_DSM_MASK)
+#define XCVR_WOR_WOR_CTRL_DSM_GUARDBAND_MASK     (0xF0000U)
+#define XCVR_WOR_WOR_CTRL_DSM_GUARDBAND_SHIFT    (16U)
+#define XCVR_WOR_WOR_CTRL_DSM_GUARDBAND(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_CTRL_DSM_GUARDBAND_SHIFT)) & XCVR_WOR_WOR_CTRL_DSM_GUARDBAND_MASK)
+#define XCVR_WOR_WOR_CTRL_WOR_RESUME_MASK        (0x1000000U)
+#define XCVR_WOR_WOR_CTRL_WOR_RESUME_SHIFT       (24U)
+#define XCVR_WOR_WOR_CTRL_WOR_RESUME(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_CTRL_WOR_RESUME_SHIFT)) & XCVR_WOR_WOR_CTRL_WOR_RESUME_MASK)
+#define XCVR_WOR_WOR_CTRL_WOR_DEBUG_REG_MASK     (0x2000000U)
+#define XCVR_WOR_WOR_CTRL_WOR_DEBUG_REG_SHIFT    (25U)
+#define XCVR_WOR_WOR_CTRL_WOR_DEBUG_REG(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_CTRL_WOR_DEBUG_REG_SHIFT)) & XCVR_WOR_WOR_CTRL_WOR_DEBUG_REG_MASK)
+/*! @} */
+
+/*! @name WOR_TIMEOUT - WAKE-ON-RADIO TIMEOUT REGISTER */
+/*! @{ */
+#define XCVR_WOR_WOR_TIMEOUT_RECEIVE_TIMEOUT_MASK (0xFFFFU)
+#define XCVR_WOR_WOR_TIMEOUT_RECEIVE_TIMEOUT_SHIFT (0U)
+#define XCVR_WOR_WOR_TIMEOUT_RECEIVE_TIMEOUT(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_TIMEOUT_RECEIVE_TIMEOUT_SHIFT)) & XCVR_WOR_WOR_TIMEOUT_RECEIVE_TIMEOUT_MASK)
+#define XCVR_WOR_WOR_TIMEOUT_WAKE_ON_NTH_SLOT_MASK (0xFF0000U)
+#define XCVR_WOR_WOR_TIMEOUT_WAKE_ON_NTH_SLOT_SHIFT (16U)
+#define XCVR_WOR_WOR_TIMEOUT_WAKE_ON_NTH_SLOT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_TIMEOUT_WAKE_ON_NTH_SLOT_SHIFT)) & XCVR_WOR_WOR_TIMEOUT_WAKE_ON_NTH_SLOT_MASK)
+#define XCVR_WOR_WOR_TIMEOUT_WOR_SLOT_COUNT_MASK (0xFF000000U)
+#define XCVR_WOR_WOR_TIMEOUT_WOR_SLOT_COUNT_SHIFT (24U)
+#define XCVR_WOR_WOR_TIMEOUT_WOR_SLOT_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_TIMEOUT_WOR_SLOT_COUNT_SHIFT)) & XCVR_WOR_WOR_TIMEOUT_WOR_SLOT_COUNT_MASK)
+/*! @} */
+
+/*! @name TIMESTAMP1 - WAKE-ON-RADIO TIMESTAMP 1 */
+/*! @{ */
+#define XCVR_WOR_TIMESTAMP1_TIMESTAMP1_FRAC_MASK (0xFFU)
+#define XCVR_WOR_TIMESTAMP1_TIMESTAMP1_FRAC_SHIFT (0U)
+#define XCVR_WOR_TIMESTAMP1_TIMESTAMP1_FRAC(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_TIMESTAMP1_TIMESTAMP1_FRAC_SHIFT)) & XCVR_WOR_TIMESTAMP1_TIMESTAMP1_FRAC_MASK)
+#define XCVR_WOR_TIMESTAMP1_TIMESTAMP1_MASK      (0xFFFFFF00U)
+#define XCVR_WOR_TIMESTAMP1_TIMESTAMP1_SHIFT     (8U)
+#define XCVR_WOR_TIMESTAMP1_TIMESTAMP1(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_TIMESTAMP1_TIMESTAMP1_SHIFT)) & XCVR_WOR_TIMESTAMP1_TIMESTAMP1_MASK)
+/*! @} */
+
+/*! @name TIMESTAMP2 - WAKE-ON-RADIO TIMESTAMP 2 */
+/*! @{ */
+#define XCVR_WOR_TIMESTAMP2_TIMESTAMP2_FRAC_MASK (0xFFU)
+#define XCVR_WOR_TIMESTAMP2_TIMESTAMP2_FRAC_SHIFT (0U)
+#define XCVR_WOR_TIMESTAMP2_TIMESTAMP2_FRAC(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_TIMESTAMP2_TIMESTAMP2_FRAC_SHIFT)) & XCVR_WOR_TIMESTAMP2_TIMESTAMP2_FRAC_MASK)
+#define XCVR_WOR_TIMESTAMP2_TIMESTAMP2_MASK      (0xFFFFFF00U)
+#define XCVR_WOR_TIMESTAMP2_TIMESTAMP2_SHIFT     (8U)
+#define XCVR_WOR_TIMESTAMP2_TIMESTAMP2(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_TIMESTAMP2_TIMESTAMP2_SHIFT)) & XCVR_WOR_TIMESTAMP2_TIMESTAMP2_MASK)
+/*! @} */
+
+/*! @name TIMESTAMP3 - WAKE-ON-RADIO TIMESTAMP 3 */
+/*! @{ */
+#define XCVR_WOR_TIMESTAMP3_TIMESTAMP3_FRAC_MASK (0xFFU)
+#define XCVR_WOR_TIMESTAMP3_TIMESTAMP3_FRAC_SHIFT (0U)
+#define XCVR_WOR_TIMESTAMP3_TIMESTAMP3_FRAC(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_TIMESTAMP3_TIMESTAMP3_FRAC_SHIFT)) & XCVR_WOR_TIMESTAMP3_TIMESTAMP3_FRAC_MASK)
+#define XCVR_WOR_TIMESTAMP3_TIMESTAMP3_MASK      (0xFFFFFF00U)
+#define XCVR_WOR_TIMESTAMP3_TIMESTAMP3_SHIFT     (8U)
+#define XCVR_WOR_TIMESTAMP3_TIMESTAMP3(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_TIMESTAMP3_TIMESTAMP3_SHIFT)) & XCVR_WOR_TIMESTAMP3_TIMESTAMP3_MASK)
+/*! @} */
+
+/*! @name WOR_STATUS - WAKE-ON-RADIO STATUS REGISTER */
+/*! @{ */
+#define XCVR_WOR_WOR_STATUS_TIMESTAMP0_STS_MASK  (0x7U)
+#define XCVR_WOR_WOR_STATUS_TIMESTAMP0_STS_SHIFT (0U)
+#define XCVR_WOR_WOR_STATUS_TIMESTAMP0_STS(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_STATUS_TIMESTAMP0_STS_SHIFT)) & XCVR_WOR_WOR_STATUS_TIMESTAMP0_STS_MASK)
+#define XCVR_WOR_WOR_STATUS_TIMESTAMP1_STS_MASK  (0x38U)
+#define XCVR_WOR_WOR_STATUS_TIMESTAMP1_STS_SHIFT (3U)
+#define XCVR_WOR_WOR_STATUS_TIMESTAMP1_STS(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_STATUS_TIMESTAMP1_STS_SHIFT)) & XCVR_WOR_WOR_STATUS_TIMESTAMP1_STS_MASK)
+#define XCVR_WOR_WOR_STATUS_TIMESTAMP2_STS_MASK  (0x1C0U)
+#define XCVR_WOR_WOR_STATUS_TIMESTAMP2_STS_SHIFT (6U)
+#define XCVR_WOR_WOR_STATUS_TIMESTAMP2_STS(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_STATUS_TIMESTAMP2_STS_SHIFT)) & XCVR_WOR_WOR_STATUS_TIMESTAMP2_STS_MASK)
+#define XCVR_WOR_WOR_STATUS_TIMESTAMP3_STS_MASK  (0xE00U)
+#define XCVR_WOR_WOR_STATUS_TIMESTAMP3_STS_SHIFT (9U)
+#define XCVR_WOR_WOR_STATUS_TIMESTAMP3_STS(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_STATUS_TIMESTAMP3_STS_SHIFT)) & XCVR_WOR_WOR_STATUS_TIMESTAMP3_STS_MASK)
+#define XCVR_WOR_WOR_STATUS_SLOT_MASK            (0x3000U)
+#define XCVR_WOR_WOR_STATUS_SLOT_SHIFT           (12U)
+#define XCVR_WOR_WOR_STATUS_SLOT(x)              (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_STATUS_SLOT_SHIFT)) & XCVR_WOR_WOR_STATUS_SLOT_MASK)
+#define XCVR_WOR_WOR_STATUS_WOR_NO_RF_FLAG_MASK  (0x10000U)
+#define XCVR_WOR_WOR_STATUS_WOR_NO_RF_FLAG_SHIFT (16U)
+#define XCVR_WOR_WOR_STATUS_WOR_NO_RF_FLAG(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_STATUS_WOR_NO_RF_FLAG_SHIFT)) & XCVR_WOR_WOR_STATUS_WOR_NO_RF_FLAG_MASK)
+#define XCVR_WOR_WOR_STATUS_WOR_MAX_SLOT_FLAG_MASK (0x20000U)
+#define XCVR_WOR_WOR_STATUS_WOR_MAX_SLOT_FLAG_SHIFT (17U)
+#define XCVR_WOR_WOR_STATUS_WOR_MAX_SLOT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_STATUS_WOR_MAX_SLOT_FLAG_SHIFT)) & XCVR_WOR_WOR_STATUS_WOR_MAX_SLOT_FLAG_MASK)
+#define XCVR_WOR_WOR_STATUS_WOR_DSM_EXIT_FLAG_MASK (0x40000U)
+#define XCVR_WOR_WOR_STATUS_WOR_DSM_EXIT_FLAG_SHIFT (18U)
+#define XCVR_WOR_WOR_STATUS_WOR_DSM_EXIT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_STATUS_WOR_DSM_EXIT_FLAG_SHIFT)) & XCVR_WOR_WOR_STATUS_WOR_DSM_EXIT_FLAG_MASK)
+#define XCVR_WOR_WOR_STATUS_WOR_STATE_MASK       (0xF00000U)
+#define XCVR_WOR_WOR_STATUS_WOR_STATE_SHIFT      (20U)
+#define XCVR_WOR_WOR_STATUS_WOR_STATE(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_STATUS_WOR_STATE_SHIFT)) & XCVR_WOR_WOR_STATUS_WOR_STATE_MASK)
+/*! @} */
+
+/*! @name WW_CTRL - WINDOW-WIDENING CONTROL REGISTER */
+/*! @{ */
+#define XCVR_WOR_WW_CTRL_WW_EN_MASK              (0x1U)
+#define XCVR_WOR_WW_CTRL_WW_EN_SHIFT             (0U)
+#define XCVR_WOR_WW_CTRL_WW_EN(x)                (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WW_CTRL_WW_EN_SHIFT)) & XCVR_WOR_WW_CTRL_WW_EN_MASK)
+#define XCVR_WOR_WW_CTRL_WW_RESET_ON_RX_MASK     (0x2U)
+#define XCVR_WOR_WW_CTRL_WW_RESET_ON_RX_SHIFT    (1U)
+#define XCVR_WOR_WW_CTRL_WW_RESET_ON_RX(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WW_CTRL_WW_RESET_ON_RX_SHIFT)) & XCVR_WOR_WW_CTRL_WW_RESET_ON_RX_MASK)
+#define XCVR_WOR_WW_CTRL_WW_NULL_MASK            (0x4U)
+#define XCVR_WOR_WW_CTRL_WW_NULL_SHIFT           (2U)
+#define XCVR_WOR_WW_CTRL_WW_NULL(x)              (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WW_CTRL_WW_NULL_SHIFT)) & XCVR_WOR_WW_CTRL_WW_NULL_MASK)
+#define XCVR_WOR_WW_CTRL_WW_ADD_MASK             (0x8U)
+#define XCVR_WOR_WW_CTRL_WW_ADD_SHIFT            (3U)
+#define XCVR_WOR_WW_CTRL_WW_ADD(x)               (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WW_CTRL_WW_ADD_SHIFT)) & XCVR_WOR_WW_CTRL_WW_ADD_MASK)
+#define XCVR_WOR_WW_CTRL_WW_DSM_FACTOR_MASK      (0x1F00U)
+#define XCVR_WOR_WW_CTRL_WW_DSM_FACTOR_SHIFT     (8U)
+#define XCVR_WOR_WW_CTRL_WW_DSM_FACTOR(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WW_CTRL_WW_DSM_FACTOR_SHIFT)) & XCVR_WOR_WW_CTRL_WW_DSM_FACTOR_MASK)
+#define XCVR_WOR_WW_CTRL_WW_RUN_FACTOR_MASK      (0x1F0000U)
+#define XCVR_WOR_WW_CTRL_WW_RUN_FACTOR_SHIFT     (16U)
+#define XCVR_WOR_WW_CTRL_WW_RUN_FACTOR(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WW_CTRL_WW_RUN_FACTOR_SHIFT)) & XCVR_WOR_WW_CTRL_WW_RUN_FACTOR_MASK)
+#define XCVR_WOR_WW_CTRL_WW_INCREASE_MASK        (0xFF000000U)
+#define XCVR_WOR_WW_CTRL_WW_INCREASE_SHIFT       (24U)
+#define XCVR_WOR_WW_CTRL_WW_INCREASE(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WW_CTRL_WW_INCREASE_SHIFT)) & XCVR_WOR_WW_CTRL_WW_INCREASE_MASK)
+/*! @} */
+
+/*! @name HOP_CTRL - FREQUENCY HOP CONTROL REGISTER */
+/*! @{ */
+#define XCVR_WOR_HOP_CTRL_HOP_TBL_CFG_MASK       (0x7U)
+#define XCVR_WOR_HOP_CTRL_HOP_TBL_CFG_SHIFT      (0U)
+#define XCVR_WOR_HOP_CTRL_HOP_TBL_CFG(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_HOP_CTRL_HOP_TBL_CFG_SHIFT)) & XCVR_WOR_HOP_CTRL_HOP_TBL_CFG_MASK)
+#define XCVR_WOR_HOP_CTRL_NEW_HOP_IDX_MASK       (0x7F00U)
+#define XCVR_WOR_HOP_CTRL_NEW_HOP_IDX_SHIFT      (8U)
+#define XCVR_WOR_HOP_CTRL_NEW_HOP_IDX(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_HOP_CTRL_NEW_HOP_IDX_SHIFT)) & XCVR_WOR_HOP_CTRL_NEW_HOP_IDX_MASK)
+#define XCVR_WOR_HOP_CTRL_UPDATE_HOP_IDX_MASK    (0x8000U)
+#define XCVR_WOR_HOP_CTRL_UPDATE_HOP_IDX_SHIFT   (15U)
+#define XCVR_WOR_HOP_CTRL_UPDATE_HOP_IDX(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_HOP_CTRL_UPDATE_HOP_IDX_SHIFT)) & XCVR_WOR_HOP_CTRL_UPDATE_HOP_IDX_MASK)
+#define XCVR_WOR_HOP_CTRL_HOP_SEQ_LENGTH_MASK    (0x7F0000U)
+#define XCVR_WOR_HOP_CTRL_HOP_SEQ_LENGTH_SHIFT   (16U)
+#define XCVR_WOR_HOP_CTRL_HOP_SEQ_LENGTH(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_HOP_CTRL_HOP_SEQ_LENGTH_SHIFT)) & XCVR_WOR_HOP_CTRL_HOP_SEQ_LENGTH_MASK)
+/*! @} */
+
+/*! @name SLOT0_DESC0 - SLOT 0 DESCRIPTOR (LSB) */
+/*! @{ */
+#define XCVR_WOR_SLOT0_DESC0_SLOT0_DESC0_MASK    (0xFFFFFFF0U)
+#define XCVR_WOR_SLOT0_DESC0_SLOT0_DESC0_SHIFT   (4U)
+#define XCVR_WOR_SLOT0_DESC0_SLOT0_DESC0(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_SLOT0_DESC0_SLOT0_DESC0_SHIFT)) & XCVR_WOR_SLOT0_DESC0_SLOT0_DESC0_MASK)
+/*! @} */
+
+/*! @name SLOT0_DESC1 - SLOT 0 DESCRIPTOR (MSB) */
+/*! @{ */
+#define XCVR_WOR_SLOT0_DESC1_SLOT0_DESC1_MASK    (0x1FU)
+#define XCVR_WOR_SLOT0_DESC1_SLOT0_DESC1_SHIFT   (0U)
+#define XCVR_WOR_SLOT0_DESC1_SLOT0_DESC1(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_SLOT0_DESC1_SLOT0_DESC1_SHIFT)) & XCVR_WOR_SLOT0_DESC1_SLOT0_DESC1_MASK)
+#define XCVR_WOR_SLOT0_DESC1_WOR_HOP_IDX_MASK    (0x7F00U)
+#define XCVR_WOR_SLOT0_DESC1_WOR_HOP_IDX_SHIFT   (8U)
+#define XCVR_WOR_SLOT0_DESC1_WOR_HOP_IDX(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_SLOT0_DESC1_WOR_HOP_IDX_SHIFT)) & XCVR_WOR_SLOT0_DESC1_WOR_HOP_IDX_MASK)
+#define XCVR_WOR_SLOT0_DESC1_WOR_HOP_FREQ_WORD_MASK (0xFFFF0000U)
+#define XCVR_WOR_SLOT0_DESC1_WOR_HOP_FREQ_WORD_SHIFT (16U)
+#define XCVR_WOR_SLOT0_DESC1_WOR_HOP_FREQ_WORD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_SLOT0_DESC1_WOR_HOP_FREQ_WORD_SHIFT)) & XCVR_WOR_SLOT0_DESC1_WOR_HOP_FREQ_WORD_MASK)
+/*! @} */
+
+/*! @name SLOT1_DESC0 - SLOT 1 DESCRIPTOR (LSB) */
+/*! @{ */
+#define XCVR_WOR_SLOT1_DESC0_SLOT1_DESC0_MASK    (0xFFFFFFF0U)
+#define XCVR_WOR_SLOT1_DESC0_SLOT1_DESC0_SHIFT   (4U)
+#define XCVR_WOR_SLOT1_DESC0_SLOT1_DESC0(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_SLOT1_DESC0_SLOT1_DESC0_SHIFT)) & XCVR_WOR_SLOT1_DESC0_SLOT1_DESC0_MASK)
+/*! @} */
+
+/*! @name SLOT1_DESC1 - SLOT 1 DESCRIPTOR (MSB) */
+/*! @{ */
+#define XCVR_WOR_SLOT1_DESC1_SLOT1_DESC1_MASK    (0x1FU)
+#define XCVR_WOR_SLOT1_DESC1_SLOT1_DESC1_SHIFT   (0U)
+#define XCVR_WOR_SLOT1_DESC1_SLOT1_DESC1(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_SLOT1_DESC1_SLOT1_DESC1_SHIFT)) & XCVR_WOR_SLOT1_DESC1_SLOT1_DESC1_MASK)
+/*! @} */
+
+/*! @name SLOT2_DESC0 - SLOT 2 DESCRIPTOR (LSB) */
+/*! @{ */
+#define XCVR_WOR_SLOT2_DESC0_SLOT2_DESC0_MASK    (0xFFFFFFF0U)
+#define XCVR_WOR_SLOT2_DESC0_SLOT2_DESC0_SHIFT   (4U)
+#define XCVR_WOR_SLOT2_DESC0_SLOT2_DESC0(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_SLOT2_DESC0_SLOT2_DESC0_SHIFT)) & XCVR_WOR_SLOT2_DESC0_SLOT2_DESC0_MASK)
+/*! @} */
+
+/*! @name SLOT2_DESC1 - SLOT 2 DESCRIPTOR (MSB) */
+/*! @{ */
+#define XCVR_WOR_SLOT2_DESC1_SLOT2_DESC1_MASK    (0x1FU)
+#define XCVR_WOR_SLOT2_DESC1_SLOT2_DESC1_SHIFT   (0U)
+#define XCVR_WOR_SLOT2_DESC1_SLOT2_DESC1(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_SLOT2_DESC1_SLOT2_DESC1_SHIFT)) & XCVR_WOR_SLOT2_DESC1_SLOT2_DESC1_MASK)
+/*! @} */
+
+/*! @name SLOT3_DESC0 - SLOT 3 DESCRIPTOR (LSB) */
+/*! @{ */
+#define XCVR_WOR_SLOT3_DESC0_SLOT3_DESC0_MASK    (0xFFFFFFF0U)
+#define XCVR_WOR_SLOT3_DESC0_SLOT3_DESC0_SHIFT   (4U)
+#define XCVR_WOR_SLOT3_DESC0_SLOT3_DESC0(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_SLOT3_DESC0_SLOT3_DESC0_SHIFT)) & XCVR_WOR_SLOT3_DESC0_SLOT3_DESC0_MASK)
+/*! @} */
+
+/*! @name SLOT3_DESC1 - SLOT 3 DESCRIPTOR (MSB) */
+/*! @{ */
+#define XCVR_WOR_SLOT3_DESC1_SLOT3_DESC1_MASK    (0x1FU)
+#define XCVR_WOR_SLOT3_DESC1_SLOT3_DESC1_SHIFT   (0U)
+#define XCVR_WOR_SLOT3_DESC1_SLOT3_DESC1(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_SLOT3_DESC1_SLOT3_DESC1_SHIFT)) & XCVR_WOR_SLOT3_DESC1_SLOT3_DESC1_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group XCVR_WOR_Register_Masks */
+
+
+/* XCVR_WOR - Peripheral instance base addresses */
+/** Peripheral XCVR_WOR base address */
+#define XCVR_WOR_BASE                            (0x410304C0u)
+/** Peripheral XCVR_WOR base pointer */
+#define XCVR_WOR                                 ((XCVR_WOR_Type *)XCVR_WOR_BASE)
+/** Array initializer of XCVR_WOR peripheral base addresses */
+#define XCVR_WOR_BASE_ADDRS                      { XCVR_WOR_BASE }
+/** Array initializer of XCVR_WOR peripheral base pointers */
+#define XCVR_WOR_BASE_PTRS                       { XCVR_WOR }
+
+/*!
+ * @}
+ */ /* end of group XCVR_WOR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- XCVR_ZBDEM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XCVR_ZBDEM_Peripheral_Access_Layer XCVR_ZBDEM Peripheral Access Layer
+ * @{
+ */
+
+/** XCVR_ZBDEM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CORR_CTRL;                         /**< 802.15.4 DEMOD CORRELATOR CONTROL, offset: 0x0 */
+  __IO uint32_t PN_TYPE;                           /**< 802.15.4 DEMOD PN TYPE, offset: 0x4 */
+  __IO uint32_t PN_CODE;                           /**< 802.15.4 DEMOD PN CODE, offset: 0x8 */
+  __IO uint32_t SYNC_CTRL;                         /**< 802.15.4 DEMOD SYMBOL SYNC CONTROL, offset: 0xC */
+  __IO uint32_t CCA_LQI_SRC;                       /**< 802.15.4 CCA/LQI SOURCE, offset: 0x10 */
+  __IO uint32_t FAD_LPPS_THR;                      /**< FAD CORRELATOR THRESHOLD, offset: 0x14 */
+  __IO uint32_t ZBDEM_AFC;                         /**< 802.15.4 AFC STATUS, offset: 0x18 */
+  __IO uint32_t CCA2_CTRL;                         /**< CCA MODE 2 CONTROL REGISTER, offset: 0x1C */
+  __IO uint32_t CCA2_THRESH;                       /**< CCA MODE 2 CONTROL REGISTER, offset: 0x20 */
+  __I  uint32_t CCA2_STATUS;                       /**< CCA MODE 2 STATUS REGISTER, offset: 0x24 */
+} XCVR_ZBDEM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- XCVR_ZBDEM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XCVR_ZBDEM_Register_Masks XCVR_ZBDEM Register Masks
+ * @{
+ */
+
+/*! @name CORR_CTRL - 802.15.4 DEMOD CORRELATOR CONTROL */
+/*! @{ */
+#define XCVR_ZBDEM_CORR_CTRL_CORR_VT_MASK        (0xFFU)
+#define XCVR_ZBDEM_CORR_CTRL_CORR_VT_SHIFT       (0U)
+#define XCVR_ZBDEM_CORR_CTRL_CORR_VT(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_CORR_VT_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_CORR_VT_MASK)
+#define XCVR_ZBDEM_CORR_CTRL_CORR_NVAL_MASK      (0x700U)
+#define XCVR_ZBDEM_CORR_CTRL_CORR_NVAL_SHIFT     (8U)
+#define XCVR_ZBDEM_CORR_CTRL_CORR_NVAL(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_CORR_NVAL_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_CORR_NVAL_MASK)
+#define XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN_MASK    (0x800U)
+#define XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN_SHIFT   (11U)
+#define XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN_MASK)
+#define XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON_MASK   (0x8000U)
+#define XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON_SHIFT  (15U)
+/*! ZBDEM_CLK_ON - Force 802.15.4 Demodulator Clock On
+ *  0b0..Normal Operation
+ *  0b1..Force 802.15.4 Demodulator Clock On (debug purposes only)
+ */
+#define XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON_MASK)
+#define XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR_MASK    (0xFF0000U)
+#define XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR_SHIFT   (16U)
+#define XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR_MASK)
+#define XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE_MASK (0xFF000000U)
+#define XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE_SHIFT (24U)
+#define XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE_MASK)
+/*! @} */
+
+/*! @name PN_TYPE - 802.15.4 DEMOD PN TYPE */
+/*! @{ */
+#define XCVR_ZBDEM_PN_TYPE_PN_TYPE_MASK          (0x1U)
+#define XCVR_ZBDEM_PN_TYPE_PN_TYPE_SHIFT         (0U)
+#define XCVR_ZBDEM_PN_TYPE_PN_TYPE(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_PN_TYPE_PN_TYPE_SHIFT)) & XCVR_ZBDEM_PN_TYPE_PN_TYPE_MASK)
+#define XCVR_ZBDEM_PN_TYPE_TX_INV_MASK           (0x2U)
+#define XCVR_ZBDEM_PN_TYPE_TX_INV_SHIFT          (1U)
+#define XCVR_ZBDEM_PN_TYPE_TX_INV(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_PN_TYPE_TX_INV_SHIFT)) & XCVR_ZBDEM_PN_TYPE_TX_INV_MASK)
+/*! @} */
+
+/*! @name PN_CODE - 802.15.4 DEMOD PN CODE */
+/*! @{ */
+#define XCVR_ZBDEM_PN_CODE_PN_LSB_MASK           (0xFFFFU)
+#define XCVR_ZBDEM_PN_CODE_PN_LSB_SHIFT          (0U)
+#define XCVR_ZBDEM_PN_CODE_PN_LSB(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_PN_CODE_PN_LSB_SHIFT)) & XCVR_ZBDEM_PN_CODE_PN_LSB_MASK)
+#define XCVR_ZBDEM_PN_CODE_PN_MSB_MASK           (0xFFFF0000U)
+#define XCVR_ZBDEM_PN_CODE_PN_MSB_SHIFT          (16U)
+#define XCVR_ZBDEM_PN_CODE_PN_MSB(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_PN_CODE_PN_MSB_SHIFT)) & XCVR_ZBDEM_PN_CODE_PN_MSB_MASK)
+/*! @} */
+
+/*! @name SYNC_CTRL - 802.15.4 DEMOD SYMBOL SYNC CONTROL */
+/*! @{ */
+#define XCVR_ZBDEM_SYNC_CTRL_SYNC_PER_MASK       (0x7U)
+#define XCVR_ZBDEM_SYNC_CTRL_SYNC_PER_SHIFT      (0U)
+#define XCVR_ZBDEM_SYNC_CTRL_SYNC_PER(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_SYNC_CTRL_SYNC_PER_SHIFT)) & XCVR_ZBDEM_SYNC_CTRL_SYNC_PER_MASK)
+#define XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE_MASK   (0x8U)
+#define XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE_SHIFT  (3U)
+/*! TRACK_ENABLE - TRACK_ENABLE
+ *  0b0..symbol timing synchronization tracking disabled in Rx frontend
+ *  0b1..symbol timing synchronization tracking enabled in Rx frontend (default)
+ */
+#define XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE_SHIFT)) & XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE_MASK)
+/*! @} */
+
+/*! @name CCA_LQI_SRC - 802.15.4 CCA/LQI SOURCE */
+/*! @{ */
+#define XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG_MASK (0x1U)
+#define XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG_SHIFT (0U)
+/*! CCA1_FROM_RX_DIG - Selects the Source of CCA1 (Clear Channel Assessment Mode 1) Information Provided to the 802.15.4 Link Layer
+ *  0b0..Use the CCA1 information computed internally in the 802.15.4 Demod
+ *  0b1..Use the CCA1 information computed by the RX Digital
+ */
+#define XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG_SHIFT)) & XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG_MASK)
+#define XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG_MASK (0x2U)
+#define XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG_SHIFT (1U)
+/*! LQI_FROM_RX_DIG - Selects the Source of LQI (Link Quality Indicator) Information Provided to the 802.15.4 Link Layer
+ *  0b0..Use the LQI information computed internally in the 802.15.4 Demod
+ *  0b1..Use the LQI information computed by the RX Digital
+ */
+#define XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG_SHIFT)) & XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG_MASK)
+#define XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD_MASK (0x4U)
+#define XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD_SHIFT (2U)
+/*! LQI_START_AT_SFD - Select Start Point for LQI Computation
+ *  0b0..Start LQI computation at Preamble Detection (similar to previous NXP 802.15.4 products)
+ *  0b1..Start LQI computation at SFD (Start of Frame Delimiter) Detection
+ */
+#define XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD_SHIFT)) & XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD_MASK)
+#define XCVR_ZBDEM_CCA_LQI_SRC_ZBDEM_CCA_CLK_ON_MASK (0x8U)
+#define XCVR_ZBDEM_CCA_LQI_SRC_ZBDEM_CCA_CLK_ON_SHIFT (3U)
+#define XCVR_ZBDEM_CCA_LQI_SRC_ZBDEM_CCA_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA_LQI_SRC_ZBDEM_CCA_CLK_ON_SHIFT)) & XCVR_ZBDEM_CCA_LQI_SRC_ZBDEM_CCA_CLK_ON_MASK)
+/*! @} */
+
+/*! @name FAD_LPPS_THR - FAD CORRELATOR THRESHOLD */
+/*! @{ */
+#define XCVR_ZBDEM_FAD_LPPS_THR_FAD_THR_MASK     (0xFFU)
+#define XCVR_ZBDEM_FAD_LPPS_THR_FAD_THR_SHIFT    (0U)
+#define XCVR_ZBDEM_FAD_LPPS_THR_FAD_THR(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_FAD_LPPS_THR_FAD_THR_SHIFT)) & XCVR_ZBDEM_FAD_LPPS_THR_FAD_THR_MASK)
+#define XCVR_ZBDEM_FAD_LPPS_THR_FAD_FILL1_MASK   (0x7F00U)
+#define XCVR_ZBDEM_FAD_LPPS_THR_FAD_FILL1_SHIFT  (8U)
+#define XCVR_ZBDEM_FAD_LPPS_THR_FAD_FILL1(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_FAD_LPPS_THR_FAD_FILL1_SHIFT)) & XCVR_ZBDEM_FAD_LPPS_THR_FAD_FILL1_MASK)
+#define XCVR_ZBDEM_FAD_LPPS_THR_LPPS_FILL_COUNT_MASK (0x7F0000U)
+#define XCVR_ZBDEM_FAD_LPPS_THR_LPPS_FILL_COUNT_SHIFT (16U)
+#define XCVR_ZBDEM_FAD_LPPS_THR_LPPS_FILL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_FAD_LPPS_THR_LPPS_FILL_COUNT_SHIFT)) & XCVR_ZBDEM_FAD_LPPS_THR_LPPS_FILL_COUNT_MASK)
+#define XCVR_ZBDEM_FAD_LPPS_THR_LPPS_LP_EN_COUNT_MASK (0x7F000000U)
+#define XCVR_ZBDEM_FAD_LPPS_THR_LPPS_LP_EN_COUNT_SHIFT (24U)
+#define XCVR_ZBDEM_FAD_LPPS_THR_LPPS_LP_EN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_FAD_LPPS_THR_LPPS_LP_EN_COUNT_SHIFT)) & XCVR_ZBDEM_FAD_LPPS_THR_LPPS_LP_EN_COUNT_MASK)
+/*! @} */
+
+/*! @name ZBDEM_AFC - 802.15.4 AFC STATUS */
+/*! @{ */
+#define XCVR_ZBDEM_ZBDEM_AFC_AFC_EN_MASK         (0x1U)
+#define XCVR_ZBDEM_ZBDEM_AFC_AFC_EN_SHIFT        (0U)
+/*! AFC_EN - AFC_EN
+ *  0b0..AFC is disabled
+ *  0b1..AFC is enabled
+ */
+#define XCVR_ZBDEM_ZBDEM_AFC_AFC_EN(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_ZBDEM_AFC_AFC_EN_SHIFT)) & XCVR_ZBDEM_ZBDEM_AFC_AFC_EN_MASK)
+#define XCVR_ZBDEM_ZBDEM_AFC_DCD_EN_MASK         (0x2U)
+#define XCVR_ZBDEM_ZBDEM_AFC_DCD_EN_SHIFT        (1U)
+/*! DCD_EN - DCD_EN
+ *  0b0..NCD Mode (default)
+ *  0b1..DCD Mode
+ */
+#define XCVR_ZBDEM_ZBDEM_AFC_DCD_EN(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_ZBDEM_AFC_DCD_EN_SHIFT)) & XCVR_ZBDEM_ZBDEM_AFC_DCD_EN_MASK)
+#define XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT_MASK        (0x1F00U)
+#define XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT_SHIFT       (8U)
+#define XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT_SHIFT)) & XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT_MASK)
+/*! @} */
+
+/*! @name CCA2_CTRL - CCA MODE 2 CONTROL REGISTER */
+/*! @{ */
+#define XCVR_ZBDEM_CCA2_CTRL_CCA2_INTERVAL_MASK  (0x3U)
+#define XCVR_ZBDEM_CCA2_CTRL_CCA2_INTERVAL_SHIFT (0U)
+/*! CCA2_INTERVAL - CCA Mode 2 Measurement Window Duration
+ *  0b00..64 us
+ *  0b01..128 us
+ *  0b10..256 us
+ *  0b11..512 us
+ */
+#define XCVR_ZBDEM_CCA2_CTRL_CCA2_INTERVAL(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA2_CTRL_CCA2_INTERVAL_SHIFT)) & XCVR_ZBDEM_CCA2_CTRL_CCA2_INTERVAL_MASK)
+#define XCVR_ZBDEM_CCA2_CTRL_USE_DEMOD_CCA2_MASK (0x4U)
+#define XCVR_ZBDEM_CCA2_CTRL_USE_DEMOD_CCA2_SHIFT (2U)
+/*! USE_DEMOD_CCA2 - Selects CCA Mode 2 Computation Engine
+ *  0b0..Use standalone (new) CCA Mode 2 Engine, decoupled from demodulator
+ *  0b1..Use 802.15.4 demodulator-based (legacy) CCA Mode 2 Engine (default)
+ */
+#define XCVR_ZBDEM_CCA2_CTRL_USE_DEMOD_CCA2(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA2_CTRL_USE_DEMOD_CCA2_SHIFT)) & XCVR_ZBDEM_CCA2_CTRL_USE_DEMOD_CCA2_MASK)
+#define XCVR_ZBDEM_CCA2_CTRL_CCA2_REF_SEQ_MASK   (0xFF00U)
+#define XCVR_ZBDEM_CCA2_CTRL_CCA2_REF_SEQ_SHIFT  (8U)
+#define XCVR_ZBDEM_CCA2_CTRL_CCA2_REF_SEQ(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA2_CTRL_CCA2_REF_SEQ_SHIFT)) & XCVR_ZBDEM_CCA2_CTRL_CCA2_REF_SEQ_MASK)
+/*! @} */
+
+/*! @name CCA2_THRESH - CCA MODE 2 CONTROL REGISTER */
+/*! @{ */
+#define XCVR_ZBDEM_CCA2_THRESH_CCA2_CNT_THRESH_MASK (0x3FFU)
+#define XCVR_ZBDEM_CCA2_THRESH_CCA2_CNT_THRESH_SHIFT (0U)
+#define XCVR_ZBDEM_CCA2_THRESH_CCA2_CNT_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA2_THRESH_CCA2_CNT_THRESH_SHIFT)) & XCVR_ZBDEM_CCA2_THRESH_CCA2_CNT_THRESH_MASK)
+#define XCVR_ZBDEM_CCA2_THRESH_CCA2_SYM_THRESH_MASK (0x3FF0000U)
+#define XCVR_ZBDEM_CCA2_THRESH_CCA2_SYM_THRESH_SHIFT (16U)
+#define XCVR_ZBDEM_CCA2_THRESH_CCA2_SYM_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA2_THRESH_CCA2_SYM_THRESH_SHIFT)) & XCVR_ZBDEM_CCA2_THRESH_CCA2_SYM_THRESH_MASK)
+/*! @} */
+
+/*! @name CCA2_STATUS - CCA MODE 2 STATUS REGISTER */
+/*! @{ */
+#define XCVR_ZBDEM_CCA2_STATUS_CCA2_CNT_MAX_MASK (0x3FFU)
+#define XCVR_ZBDEM_CCA2_STATUS_CCA2_CNT_MAX_SHIFT (0U)
+#define XCVR_ZBDEM_CCA2_STATUS_CCA2_CNT_MAX(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA2_STATUS_CCA2_CNT_MAX_SHIFT)) & XCVR_ZBDEM_CCA2_STATUS_CCA2_CNT_MAX_MASK)
+#define XCVR_ZBDEM_CCA2_STATUS_CCA2_COMPLETE_MASK (0x400U)
+#define XCVR_ZBDEM_CCA2_STATUS_CCA2_COMPLETE_SHIFT (10U)
+#define XCVR_ZBDEM_CCA2_STATUS_CCA2_COMPLETE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA2_STATUS_CCA2_COMPLETE_SHIFT)) & XCVR_ZBDEM_CCA2_STATUS_CCA2_COMPLETE_MASK)
+#define XCVR_ZBDEM_CCA2_STATUS_CCA2_CHANNEL_STATE_MASK (0x800U)
+#define XCVR_ZBDEM_CCA2_STATUS_CCA2_CHANNEL_STATE_SHIFT (11U)
+#define XCVR_ZBDEM_CCA2_STATUS_CCA2_CHANNEL_STATE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA2_STATUS_CCA2_CHANNEL_STATE_SHIFT)) & XCVR_ZBDEM_CCA2_STATUS_CCA2_CHANNEL_STATE_MASK)
+#define XCVR_ZBDEM_CCA2_STATUS_CCA2_CNT_SYM_MASK (0x3FF0000U)
+#define XCVR_ZBDEM_CCA2_STATUS_CCA2_CNT_SYM_SHIFT (16U)
+#define XCVR_ZBDEM_CCA2_STATUS_CCA2_CNT_SYM(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA2_STATUS_CCA2_CNT_SYM_SHIFT)) & XCVR_ZBDEM_CCA2_STATUS_CCA2_CNT_SYM_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group XCVR_ZBDEM_Register_Masks */
+
+
+/* XCVR_ZBDEM - Peripheral instance base addresses */
+/** Peripheral XCVR_ZBDEM base address */
+#define XCVR_ZBDEM_BASE                          (0x41030480u)
+/** Peripheral XCVR_ZBDEM base pointer */
+#define XCVR_ZBDEM                               ((XCVR_ZBDEM_Type *)XCVR_ZBDEM_BASE)
+/** Array initializer of XCVR_ZBDEM peripheral base addresses */
+#define XCVR_ZBDEM_BASE_ADDRS                    { XCVR_ZBDEM_BASE }
+/** Array initializer of XCVR_ZBDEM peripheral base pointers */
+#define XCVR_ZBDEM_BASE_PTRS                     { XCVR_ZBDEM }
+
+/*!
+ * @}
+ */ /* end of group XCVR_ZBDEM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- XRDC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XRDC_Peripheral_Access_Layer XRDC Peripheral Access Layer
+ * @{
+ */
+
+/** XRDC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /**< Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[236];
+  __I  uint32_t HWCFG0;                            /**< Hardware Configuration Register 0, offset: 0xF0 */
+  __I  uint32_t HWCFG1;                            /**< Hardware Configuration Register 1, offset: 0xF4 */
+  __I  uint32_t HWCFG2;                            /**< Hardware Configuration Register 2, offset: 0xF8 */
+  __I  uint32_t HWCFG3;                            /**< Hardware Configuration Register 3, offset: 0xFC */
+  __I  uint8_t MDACFG[37];                         /**< Master Domain Assignment Configuration Register, array offset: 0x100, array step: 0x1 */
+       uint8_t RESERVED_1[27];
+  __I  uint8_t MRCFG[2];                           /**< Memory Region Configuration Register, array offset: 0x140, array step: 0x1 */
+       uint8_t RESERVED_2[186];
+  __IO uint32_t FDID;                              /**< Fault Domain ID, offset: 0x1FC */
+  __I  uint32_t DERRLOC[3];                        /**< Domain Error Location Register, array offset: 0x200, array step: 0x4 */
+       uint8_t RESERVED_3[500];
+  __IO uint32_t DERR_W[19][4];                     /**< Domain Error Word0 Register..Domain Error Word3 Register, array offset: 0x400, array step: index*0x10, index2*0x4 */
+       uint8_t RESERVED_4[464];
+  __IO uint32_t PID[37];                           /**< Process Identifier, array offset: 0x700, array step: 0x4 */
+       uint8_t RESERVED_5[108];
+  struct {                                         /* offset: 0x800, array step: 0x20 */
+    __IO uint32_t MDA_W[2];                          /**< Master Domain Assignment, array offset: 0x800, array step: index*0x20, index2*0x4 */
+         uint8_t RESERVED_0[24];
+  } MDA[37];
+       uint8_t RESERVED_6[864];
+  __IO uint32_t PDAC_W[289][2];                    /**< Peripheral Domain Access Control, array offset: 0x1000, array step: index*0x8, index2*0x4 */
+       uint8_t RESERVED_7[1784];
+  struct {                                         /* offset: 0x2000, array step: 0x20 */
+    __IO uint32_t MRGD_W[5];                         /**< Memory Region Descriptor, array offset: 0x2000, array step: index*0x20, index2*0x4 */
+         uint8_t RESERVED_0[12];
+  } MRGD[24];
+} XRDC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- XRDC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup XRDC_Register_Masks XRDC Register Masks
+ * @{
+ */
+
+/*! @name CR - Control Register */
+/*! @{ */
+#define XRDC_CR_GVLDM_MASK                       (0x1U)
+#define XRDC_CR_GVLDM_SHIFT                      (0U)
+/*! GVLDM - Global Valid MDACs(XRDC global enable/disable).
+ *  0b0..XRDC MDACs are disabled.
+ *  0b1..XRDC MDACs are enabled.
+ */
+#define XRDC_CR_GVLDM(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC_CR_GVLDM_SHIFT)) & XRDC_CR_GVLDM_MASK)
+#define XRDC_CR_HRL_MASK                         (0x1EU)
+#define XRDC_CR_HRL_SHIFT                        (1U)
+#define XRDC_CR_HRL(x)                           (((uint32_t)(((uint32_t)(x)) << XRDC_CR_HRL_SHIFT)) & XRDC_CR_HRL_MASK)
+#define XRDC_CR_VAW_MASK                         (0x100U)
+#define XRDC_CR_VAW_SHIFT                        (8U)
+/*! VAW - Virtualization aware
+ *  0b0..Implementation is not virtualization aware.
+ *  0b1..Implementation is virtualization aware.
+ */
+#define XRDC_CR_VAW(x)                           (((uint32_t)(((uint32_t)(x)) << XRDC_CR_VAW_SHIFT)) & XRDC_CR_VAW_MASK)
+#define XRDC_CR_GVLDP_MASK                       (0x4000U)
+#define XRDC_CR_GVLDP_SHIFT                      (14U)
+/*! GVLDP - Global Valid for PACs/MSCs
+ *  0b0..XRDC PACs/MSCs are disabled.
+ *  0b1..XRDC PACs/MSCs are enabled.
+ */
+#define XRDC_CR_GVLDP(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC_CR_GVLDP_SHIFT)) & XRDC_CR_GVLDP_MASK)
+#define XRDC_CR_GVLDC_MASK                       (0x8000U)
+#define XRDC_CR_GVLDC_SHIFT                      (15U)
+/*! GVLDC - Global Valid for MRCs
+ *  0b0..XRDC MRCs are disabled.
+ *  0b1..XRDC MRCs are enabled.
+ */
+#define XRDC_CR_GVLDC(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC_CR_GVLDC_SHIFT)) & XRDC_CR_GVLDC_MASK)
+#define XRDC_CR_LK1_MASK                         (0x40000000U)
+#define XRDC_CR_LK1_SHIFT                        (30U)
+/*! LK1 - 1-bit Lock
+ *  0b0..Register can be written by any secure privileged write.
+ *  0b1..Register is locked (read-only) until the next reset.
+ */
+#define XRDC_CR_LK1(x)                           (((uint32_t)(((uint32_t)(x)) << XRDC_CR_LK1_SHIFT)) & XRDC_CR_LK1_MASK)
+/*! @} */
+
+/*! @name HWCFG0 - Hardware Configuration Register 0 */
+/*! @{ */
+#define XRDC_HWCFG0_NDID_MASK                    (0xFFU)
+#define XRDC_HWCFG0_NDID_SHIFT                   (0U)
+#define XRDC_HWCFG0_NDID(x)                      (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NDID_SHIFT)) & XRDC_HWCFG0_NDID_MASK)
+#define XRDC_HWCFG0_NMSTR_MASK                   (0xFF00U)
+#define XRDC_HWCFG0_NMSTR_SHIFT                  (8U)
+#define XRDC_HWCFG0_NMSTR(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NMSTR_SHIFT)) & XRDC_HWCFG0_NMSTR_MASK)
+#define XRDC_HWCFG0_NMRC_MASK                    (0xFF0000U)
+#define XRDC_HWCFG0_NMRC_SHIFT                   (16U)
+#define XRDC_HWCFG0_NMRC(x)                      (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NMRC_SHIFT)) & XRDC_HWCFG0_NMRC_MASK)
+#define XRDC_HWCFG0_NPAC_MASK                    (0xF000000U)
+#define XRDC_HWCFG0_NPAC_SHIFT                   (24U)
+#define XRDC_HWCFG0_NPAC(x)                      (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_NPAC_SHIFT)) & XRDC_HWCFG0_NPAC_MASK)
+#define XRDC_HWCFG0_MID_MASK                     (0xF0000000U)
+#define XRDC_HWCFG0_MID_SHIFT                    (28U)
+#define XRDC_HWCFG0_MID(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG0_MID_SHIFT)) & XRDC_HWCFG0_MID_MASK)
+/*! @} */
+
+/*! @name HWCFG1 - Hardware Configuration Register 1 */
+/*! @{ */
+#define XRDC_HWCFG1_DID_MASK                     (0xFU)
+#define XRDC_HWCFG1_DID_SHIFT                    (0U)
+#define XRDC_HWCFG1_DID(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG1_DID_SHIFT)) & XRDC_HWCFG1_DID_MASK)
+/*! @} */
+
+/*! @name HWCFG2 - Hardware Configuration Register 2 */
+/*! @{ */
+#define XRDC_HWCFG2_PIDP0_MASK                   (0x1U)
+#define XRDC_HWCFG2_PIDP0_SHIFT                  (0U)
+/*! PIDP0 - Process identifier
+ *  0b0..Bus master 0 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 0 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP0(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP0_SHIFT)) & XRDC_HWCFG2_PIDP0_MASK)
+#define XRDC_HWCFG2_PIDP1_MASK                   (0x2U)
+#define XRDC_HWCFG2_PIDP1_SHIFT                  (1U)
+/*! PIDP1 - Process identifier
+ *  0b0..Bus master 1 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 1 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP1(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP1_SHIFT)) & XRDC_HWCFG2_PIDP1_MASK)
+#define XRDC_HWCFG2_PIDP2_MASK                   (0x4U)
+#define XRDC_HWCFG2_PIDP2_SHIFT                  (2U)
+/*! PIDP2 - Process identifier
+ *  0b0..Bus master 2 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 2 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP2(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP2_SHIFT)) & XRDC_HWCFG2_PIDP2_MASK)
+#define XRDC_HWCFG2_PIDP3_MASK                   (0x8U)
+#define XRDC_HWCFG2_PIDP3_SHIFT                  (3U)
+/*! PIDP3 - Process identifier
+ *  0b0..Bus master 3 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 3 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP3(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP3_SHIFT)) & XRDC_HWCFG2_PIDP3_MASK)
+#define XRDC_HWCFG2_PIDP4_MASK                   (0x10U)
+#define XRDC_HWCFG2_PIDP4_SHIFT                  (4U)
+/*! PIDP4 - Process identifier
+ *  0b0..Bus master 4 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 4 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP4(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP4_SHIFT)) & XRDC_HWCFG2_PIDP4_MASK)
+#define XRDC_HWCFG2_PIDP5_MASK                   (0x20U)
+#define XRDC_HWCFG2_PIDP5_SHIFT                  (5U)
+/*! PIDP5 - Process identifier
+ *  0b0..Bus master 5 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 5 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP5(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP5_SHIFT)) & XRDC_HWCFG2_PIDP5_MASK)
+#define XRDC_HWCFG2_PIDP6_MASK                   (0x40U)
+#define XRDC_HWCFG2_PIDP6_SHIFT                  (6U)
+/*! PIDP6 - Process identifier
+ *  0b0..Bus master 6 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 6 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP6(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP6_SHIFT)) & XRDC_HWCFG2_PIDP6_MASK)
+#define XRDC_HWCFG2_PIDP7_MASK                   (0x80U)
+#define XRDC_HWCFG2_PIDP7_SHIFT                  (7U)
+/*! PIDP7 - Process identifier
+ *  0b0..Bus master 7 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 7 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP7(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP7_SHIFT)) & XRDC_HWCFG2_PIDP7_MASK)
+#define XRDC_HWCFG2_PIDP8_MASK                   (0x100U)
+#define XRDC_HWCFG2_PIDP8_SHIFT                  (8U)
+/*! PIDP8 - Process identifier
+ *  0b0..Bus master 8 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 8 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP8(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP8_SHIFT)) & XRDC_HWCFG2_PIDP8_MASK)
+#define XRDC_HWCFG2_PIDP9_MASK                   (0x200U)
+#define XRDC_HWCFG2_PIDP9_SHIFT                  (9U)
+/*! PIDP9 - Process identifier
+ *  0b0..Bus master 9 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 9 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP9(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP9_SHIFT)) & XRDC_HWCFG2_PIDP9_MASK)
+#define XRDC_HWCFG2_PIDP10_MASK                  (0x400U)
+#define XRDC_HWCFG2_PIDP10_SHIFT                 (10U)
+/*! PIDP10 - Process identifier
+ *  0b0..Bus master 10 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 10 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP10(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP10_SHIFT)) & XRDC_HWCFG2_PIDP10_MASK)
+#define XRDC_HWCFG2_PIDP11_MASK                  (0x800U)
+#define XRDC_HWCFG2_PIDP11_SHIFT                 (11U)
+/*! PIDP11 - Process identifier
+ *  0b0..Bus master 11 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 11 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP11(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP11_SHIFT)) & XRDC_HWCFG2_PIDP11_MASK)
+#define XRDC_HWCFG2_PIDP12_MASK                  (0x1000U)
+#define XRDC_HWCFG2_PIDP12_SHIFT                 (12U)
+/*! PIDP12 - Process identifier
+ *  0b0..Bus master 12 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 12 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP12(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP12_SHIFT)) & XRDC_HWCFG2_PIDP12_MASK)
+#define XRDC_HWCFG2_PIDP13_MASK                  (0x2000U)
+#define XRDC_HWCFG2_PIDP13_SHIFT                 (13U)
+/*! PIDP13 - Process identifier
+ *  0b0..Bus master 13 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 13 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP13(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP13_SHIFT)) & XRDC_HWCFG2_PIDP13_MASK)
+#define XRDC_HWCFG2_PIDP14_MASK                  (0x4000U)
+#define XRDC_HWCFG2_PIDP14_SHIFT                 (14U)
+/*! PIDP14 - Process identifier
+ *  0b0..Bus master 14 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 14 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP14(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP14_SHIFT)) & XRDC_HWCFG2_PIDP14_MASK)
+#define XRDC_HWCFG2_PIDP15_MASK                  (0x8000U)
+#define XRDC_HWCFG2_PIDP15_SHIFT                 (15U)
+/*! PIDP15 - Process identifier
+ *  0b0..Bus master 15 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 15 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP15(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP15_SHIFT)) & XRDC_HWCFG2_PIDP15_MASK)
+#define XRDC_HWCFG2_PIDP16_MASK                  (0x10000U)
+#define XRDC_HWCFG2_PIDP16_SHIFT                 (16U)
+/*! PIDP16 - Process identifier
+ *  0b0..Bus master 16 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 16 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP16(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP16_SHIFT)) & XRDC_HWCFG2_PIDP16_MASK)
+#define XRDC_HWCFG2_PIDP17_MASK                  (0x20000U)
+#define XRDC_HWCFG2_PIDP17_SHIFT                 (17U)
+/*! PIDP17 - Process identifier
+ *  0b0..Bus master 17 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 17 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP17(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP17_SHIFT)) & XRDC_HWCFG2_PIDP17_MASK)
+#define XRDC_HWCFG2_PIDP18_MASK                  (0x40000U)
+#define XRDC_HWCFG2_PIDP18_SHIFT                 (18U)
+/*! PIDP18 - Process identifier
+ *  0b0..Bus master 18 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 18 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP18(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP18_SHIFT)) & XRDC_HWCFG2_PIDP18_MASK)
+#define XRDC_HWCFG2_PIDP19_MASK                  (0x80000U)
+#define XRDC_HWCFG2_PIDP19_SHIFT                 (19U)
+/*! PIDP19 - Process identifier
+ *  0b0..Bus master 19 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 19 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP19(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP19_SHIFT)) & XRDC_HWCFG2_PIDP19_MASK)
+#define XRDC_HWCFG2_PIDP20_MASK                  (0x100000U)
+#define XRDC_HWCFG2_PIDP20_SHIFT                 (20U)
+/*! PIDP20 - Process identifier
+ *  0b0..Bus master 20 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 20 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP20(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP20_SHIFT)) & XRDC_HWCFG2_PIDP20_MASK)
+#define XRDC_HWCFG2_PIDP21_MASK                  (0x200000U)
+#define XRDC_HWCFG2_PIDP21_SHIFT                 (21U)
+/*! PIDP21 - Process identifier
+ *  0b0..Bus master 21 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 21 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP21(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP21_SHIFT)) & XRDC_HWCFG2_PIDP21_MASK)
+#define XRDC_HWCFG2_PIDP22_MASK                  (0x400000U)
+#define XRDC_HWCFG2_PIDP22_SHIFT                 (22U)
+/*! PIDP22 - Process identifier
+ *  0b0..Bus master 22 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 22 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP22(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP22_SHIFT)) & XRDC_HWCFG2_PIDP22_MASK)
+#define XRDC_HWCFG2_PIDP23_MASK                  (0x800000U)
+#define XRDC_HWCFG2_PIDP23_SHIFT                 (23U)
+/*! PIDP23 - Process identifier
+ *  0b0..Bus master 23 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 23 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP23(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP23_SHIFT)) & XRDC_HWCFG2_PIDP23_MASK)
+#define XRDC_HWCFG2_PIDP24_MASK                  (0x1000000U)
+#define XRDC_HWCFG2_PIDP24_SHIFT                 (24U)
+/*! PIDP24 - Process identifier
+ *  0b0..Bus master 24 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 24 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP24(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP24_SHIFT)) & XRDC_HWCFG2_PIDP24_MASK)
+#define XRDC_HWCFG2_PIDP25_MASK                  (0x2000000U)
+#define XRDC_HWCFG2_PIDP25_SHIFT                 (25U)
+/*! PIDP25 - Process identifier
+ *  0b0..Bus master 25 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 25 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP25(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP25_SHIFT)) & XRDC_HWCFG2_PIDP25_MASK)
+#define XRDC_HWCFG2_PIDP26_MASK                  (0x4000000U)
+#define XRDC_HWCFG2_PIDP26_SHIFT                 (26U)
+/*! PIDP26 - Process identifier
+ *  0b0..Bus master 26 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 26 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP26(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP26_SHIFT)) & XRDC_HWCFG2_PIDP26_MASK)
+#define XRDC_HWCFG2_PIDP27_MASK                  (0x8000000U)
+#define XRDC_HWCFG2_PIDP27_SHIFT                 (27U)
+/*! PIDP27 - Process identifier
+ *  0b0..Bus master 27 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 27 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP27(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP27_SHIFT)) & XRDC_HWCFG2_PIDP27_MASK)
+#define XRDC_HWCFG2_PIDP28_MASK                  (0x10000000U)
+#define XRDC_HWCFG2_PIDP28_SHIFT                 (28U)
+/*! PIDP28 - Process identifier
+ *  0b0..Bus master 28 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 28 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP28(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP28_SHIFT)) & XRDC_HWCFG2_PIDP28_MASK)
+#define XRDC_HWCFG2_PIDP29_MASK                  (0x20000000U)
+#define XRDC_HWCFG2_PIDP29_SHIFT                 (29U)
+/*! PIDP29 - Process identifier
+ *  0b0..Bus master 29 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 29 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP29(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP29_SHIFT)) & XRDC_HWCFG2_PIDP29_MASK)
+#define XRDC_HWCFG2_PIDP30_MASK                  (0x40000000U)
+#define XRDC_HWCFG2_PIDP30_SHIFT                 (30U)
+/*! PIDP30 - Process identifier
+ *  0b0..Bus master 30 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 30 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP30(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP30_SHIFT)) & XRDC_HWCFG2_PIDP30_MASK)
+#define XRDC_HWCFG2_PIDP31_MASK                  (0x80000000U)
+#define XRDC_HWCFG2_PIDP31_SHIFT                 (31U)
+/*! PIDP31 - Process identifier
+ *  0b0..Bus master 31 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores.
+ *  0b1..Bus master 31 sources a process identifier register to the XRDC_MDAC logic.
+ */
+#define XRDC_HWCFG2_PIDP31(x)                    (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP31_SHIFT)) & XRDC_HWCFG2_PIDP31_MASK)
+/*! @} */
+
+/*! @name HWCFG3 - Hardware Configuration Register 3 */
+/*! @{ */
+#define XRDC_HWCFG3_PIDPn_MASK                   (0xFFFFFFFFU)
+#define XRDC_HWCFG3_PIDPn_SHIFT                  (0U)
+#define XRDC_HWCFG3_PIDPn(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG3_PIDPn_SHIFT)) & XRDC_HWCFG3_PIDPn_MASK)
+/*! @} */
+
+/*! @name MDACFG - Master Domain Assignment Configuration Register */
+/*! @{ */
+#define XRDC_MDACFG_NMDAR_MASK                   (0xFU)
+#define XRDC_MDACFG_NMDAR_SHIFT                  (0U)
+#define XRDC_MDACFG_NMDAR(x)                     (((uint8_t)(((uint8_t)(x)) << XRDC_MDACFG_NMDAR_SHIFT)) & XRDC_MDACFG_NMDAR_MASK)
+#define XRDC_MDACFG_NCM_MASK                     (0x80U)
+#define XRDC_MDACFG_NCM_SHIFT                    (7U)
+/*! NCM - Non-CPU Master
+ *  0b0..Bus master is a processor.
+ *  0b1..Bus master is a non-processor.
+ */
+#define XRDC_MDACFG_NCM(x)                       (((uint8_t)(((uint8_t)(x)) << XRDC_MDACFG_NCM_SHIFT)) & XRDC_MDACFG_NCM_MASK)
+/*! @} */
+
+/* The count of XRDC_MDACFG */
+#define XRDC_MDACFG_COUNT                        (37U)
+
+/*! @name MRCFG - Memory Region Configuration Register */
+/*! @{ */
+#define XRDC_MRCFG_NMRGD_MASK                    (0x1FU)
+#define XRDC_MRCFG_NMRGD_SHIFT                   (0U)
+#define XRDC_MRCFG_NMRGD(x)                      (((uint8_t)(((uint8_t)(x)) << XRDC_MRCFG_NMRGD_SHIFT)) & XRDC_MRCFG_NMRGD_MASK)
+/*! @} */
+
+/* The count of XRDC_MRCFG */
+#define XRDC_MRCFG_COUNT                         (2U)
+
+/*! @name FDID - Fault Domain ID */
+/*! @{ */
+#define XRDC_FDID_FDID_MASK                      (0xFU)
+#define XRDC_FDID_FDID_SHIFT                     (0U)
+#define XRDC_FDID_FDID(x)                        (((uint32_t)(((uint32_t)(x)) << XRDC_FDID_FDID_SHIFT)) & XRDC_FDID_FDID_MASK)
+/*! @} */
+
+/*! @name DERRLOC - Domain Error Location Register */
+/*! @{ */
+#define XRDC_DERRLOC_MRCINST_MASK                (0xFFFFU)
+#define XRDC_DERRLOC_MRCINST_SHIFT               (0U)
+#define XRDC_DERRLOC_MRCINST(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERRLOC_MRCINST_SHIFT)) & XRDC_DERRLOC_MRCINST_MASK)
+#define XRDC_DERRLOC_PACINST_MASK                (0xF0000U)
+#define XRDC_DERRLOC_PACINST_SHIFT               (16U)
+#define XRDC_DERRLOC_PACINST(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC_DERRLOC_PACINST_SHIFT)) & XRDC_DERRLOC_PACINST_MASK)
+/*! @} */
+
+/* The count of XRDC_DERRLOC */
+#define XRDC_DERRLOC_COUNT                       (3U)
+
+/*! @name DERR_W - Domain Error Word0 Register..Domain Error Word3 Register */
+/*! @{ */
+#define XRDC_DERR_W_EADDR_MASK                   (0xFFFFFFFFU)
+#define XRDC_DERR_W_EADDR_SHIFT                  (0U)
+#define XRDC_DERR_W_EADDR(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EADDR_SHIFT)) & XRDC_DERR_W_EADDR_MASK)
+#define XRDC_DERR_W_EDID_MASK                    (0xFU)
+#define XRDC_DERR_W_EDID_SHIFT                   (0U)
+#define XRDC_DERR_W_EDID(x)                      (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EDID_SHIFT)) & XRDC_DERR_W_EDID_MASK)
+#define XRDC_DERR_W_EATR_MASK                    (0x700U)
+#define XRDC_DERR_W_EATR_SHIFT                   (8U)
+/*! EATR - Error attributes
+ *  0b000..Secure user mode, instruction fetch access.
+ *  0b001..Secure user mode, data access.
+ *  0b010..Secure privileged mode, instruction fetch access.
+ *  0b011..Secure privileged mode, data access.
+ *  0b100..Nonsecure user mode, instruction fetch access.
+ *  0b101..Nonsecure user mode, data access.
+ *  0b110..Nonsecure privileged mode, instruction fetch access.
+ *  0b111..Nonsecure privileged mode, data access.
+ */
+#define XRDC_DERR_W_EATR(x)                      (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EATR_SHIFT)) & XRDC_DERR_W_EATR_MASK)
+#define XRDC_DERR_W_ERW_MASK                     (0x800U)
+#define XRDC_DERR_W_ERW_SHIFT                    (11U)
+/*! ERW - Error read/write
+ *  0b0..Read access
+ *  0b1..Write access
+ */
+#define XRDC_DERR_W_ERW(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_ERW_SHIFT)) & XRDC_DERR_W_ERW_MASK)
+#define XRDC_DERR_W_EPORT_MASK                   (0x7000000U)
+#define XRDC_DERR_W_EPORT_SHIFT                  (24U)
+#define XRDC_DERR_W_EPORT(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EPORT_SHIFT)) & XRDC_DERR_W_EPORT_MASK)
+#define XRDC_DERR_W_EST_MASK                     (0xC0000000U)
+#define XRDC_DERR_W_EST_SHIFT                    (30U)
+/*! EST - Error state
+ *  0b00..No access violation has been detected.
+ *  0b01..No access violation has been detected.
+ *  0b10..A single access violation has been detected.
+ *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
+ */
+#define XRDC_DERR_W_EST(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_EST_SHIFT)) & XRDC_DERR_W_EST_MASK)
+#define XRDC_DERR_W_RECR_MASK                    (0xC0000000U)
+#define XRDC_DERR_W_RECR_SHIFT                   (30U)
+#define XRDC_DERR_W_RECR(x)                      (((uint32_t)(((uint32_t)(x)) << XRDC_DERR_W_RECR_SHIFT)) & XRDC_DERR_W_RECR_MASK)
+/*! @} */
+
+/* The count of XRDC_DERR_W */
+#define XRDC_DERR_W_COUNT                        (19U)
+
+/* The count of XRDC_DERR_W */
+#define XRDC_DERR_W_COUNT2                       (4U)
+
+/*! @name PID - Process Identifier */
+/*! @{ */
+#define XRDC_PID_PID_MASK                        (0x3FU)
+#define XRDC_PID_PID_SHIFT                       (0U)
+#define XRDC_PID_PID(x)                          (((uint32_t)(((uint32_t)(x)) << XRDC_PID_PID_SHIFT)) & XRDC_PID_PID_MASK)
+#define XRDC_PID_SP4SM_MASK                      (0x8000000U)
+#define XRDC_PID_SP4SM_SHIFT                     (27U)
+#define XRDC_PID_SP4SM(x)                        (((uint32_t)(((uint32_t)(x)) << XRDC_PID_SP4SM_SHIFT)) & XRDC_PID_SP4SM_MASK)
+#define XRDC_PID_TSM_MASK                        (0x10000000U)
+#define XRDC_PID_TSM_SHIFT                       (28U)
+#define XRDC_PID_TSM(x)                          (((uint32_t)(((uint32_t)(x)) << XRDC_PID_TSM_SHIFT)) & XRDC_PID_TSM_MASK)
+#define XRDC_PID_LK2_MASK                        (0x60000000U)
+#define XRDC_PID_LK2_SHIFT                       (29U)
+/*! LK2 - Lock
+ *  0b00..Register can be written by any secure privileged write.
+ *  0b01..Register can be written by any secure privileged write.
+ *  0b10..Register can only be written by a secure privileged write from bus master m.
+ *  0b11..Register is locked (read-only) until the next reset.
+ */
+#define XRDC_PID_LK2(x)                          (((uint32_t)(((uint32_t)(x)) << XRDC_PID_LK2_SHIFT)) & XRDC_PID_LK2_MASK)
+/*! @} */
+
+/* The count of XRDC_PID */
+#define XRDC_PID_COUNT                           (37U)
+
+/*! @name MDA_W - Master Domain Assignment */
+/*! @{ */
+#define XRDC_MDA_W_DID_MASK                      (0xFU)
+#define XRDC_MDA_W_DID_SHIFT                     (0U)
+#define XRDC_MDA_W_DID(x)                        (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_DID_SHIFT)) & XRDC_MDA_W_DID_MASK)
+#define XRDC_MDA_W_DIDS_MASK                     (0x30U)
+#define XRDC_MDA_W_DIDS_SHIFT                    (4U)
+/*! DIDS - DID Select
+ *  0b00..Use MDAm[3:0] as the domain identifier.
+ *  0b01..Use the input DID as the domain identifier.
+ *  0b10..Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier.
+ *  0b11..Reserved for future use.
+ */
+#define XRDC_MDA_W_DIDS(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_DIDS_SHIFT)) & XRDC_MDA_W_DIDS_MASK)
+#define XRDC_MDA_W_PA_MASK                       (0x30U)
+#define XRDC_MDA_W_PA_SHIFT                      (4U)
+/*! PA - Privileged attribute
+ *  0b00..Force the bus attribute for this master to user.
+ *  0b01..Force the bus attribute for this master to privileged.
+ *  0b10..Use the bus master's privileged/user attribute directly.
+ *  0b11..Use the bus master's privileged/user attribute directly.
+ */
+#define XRDC_MDA_W_PA(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_PA_SHIFT)) & XRDC_MDA_W_PA_MASK)
+#define XRDC_MDA_W_PE_MASK                       (0xC0U)
+#define XRDC_MDA_W_PE_SHIFT                      (6U)
+/*! PE - Process identifier enable
+ *  0b00..No process identifier is included in the domain hit evaluation.
+ *  0b01..No process identifier is included in the domain hit evaluation.
+ *  0b10..The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM))
+ *  0b11..The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ~((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM))
+ */
+#define XRDC_MDA_W_PE(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_PE_SHIFT)) & XRDC_MDA_W_PE_MASK)
+#define XRDC_MDA_W_SA_MASK                       (0xC0U)
+#define XRDC_MDA_W_SA_SHIFT                      (6U)
+/*! SA - Secure attribute
+ *  0b00..Force the bus attribute for this master to secure.
+ *  0b01..Force the bus attribute for this master to nonsecure.
+ *  0b10..Use the bus master's secure/nonsecure attribute directly.
+ *  0b11..Use the bus master's secure/nonsecure attribute directly.
+ */
+#define XRDC_MDA_W_SA(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_SA_SHIFT)) & XRDC_MDA_W_SA_MASK)
+#define XRDC_MDA_W_DIDB_MASK                     (0x100U)
+#define XRDC_MDA_W_DIDB_SHIFT                    (8U)
+/*! DIDB - DID Bypass
+ *  0b0..Use MDAn[3:0] as the domain identifier.
+ *  0b1..Use the DID input as the domain identifier.
+ */
+#define XRDC_MDA_W_DIDB(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_DIDB_SHIFT)) & XRDC_MDA_W_DIDB_MASK)
+#define XRDC_MDA_W_PIDM_MASK                     (0x3F00U)
+#define XRDC_MDA_W_PIDM_SHIFT                    (8U)
+#define XRDC_MDA_W_PIDM(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_PIDM_SHIFT)) & XRDC_MDA_W_PIDM_MASK)
+#define XRDC_MDA_W_PID_MASK                      (0x3F0000U)
+#define XRDC_MDA_W_PID_SHIFT                     (16U)
+#define XRDC_MDA_W_PID(x)                        (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_PID_SHIFT)) & XRDC_MDA_W_PID_MASK)
+#define XRDC_MDA_W_DFMT_MASK                     (0x20000000U)
+#define XRDC_MDA_W_DFMT_SHIFT                    (29U)
+/*! DFMT - Domain format
+ *  0b0..Processor-core domain assignment
+ *  0b1..Non-processor domain assignment
+ */
+#define XRDC_MDA_W_DFMT(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_DFMT_SHIFT)) & XRDC_MDA_W_DFMT_MASK)
+#define XRDC_MDA_W_LK1_MASK                      (0x40000000U)
+#define XRDC_MDA_W_LK1_SHIFT                     (30U)
+/*! LK1 - 1-bit Lock
+ *  0b0..Register can be written by any secure privileged write.
+ *  0b1..Register is locked (read-only) until the next reset.
+ */
+#define XRDC_MDA_W_LK1(x)                        (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_LK1_SHIFT)) & XRDC_MDA_W_LK1_MASK)
+#define XRDC_MDA_W_VLD_MASK                      (0x80000000U)
+#define XRDC_MDA_W_VLD_SHIFT                     (31U)
+/*! VLD - Valid
+ *  0b0..The Wr domain assignment is invalid.
+ *  0b1..The Wr domain assignment is valid.
+ */
+#define XRDC_MDA_W_VLD(x)                        (((uint32_t)(((uint32_t)(x)) << XRDC_MDA_W_VLD_SHIFT)) & XRDC_MDA_W_VLD_MASK)
+/*! @} */
+
+/* The count of XRDC_MDA_W */
+#define XRDC_MDA_W_COUNT                         (37U)
+
+/* The count of XRDC_MDA_W */
+#define XRDC_MDA_W_COUNT2                        (2U)
+
+/*! @name PDAC_W - Peripheral Domain Access Control */
+/*! @{ */
+#define XRDC_PDAC_W_D0ACP_MASK                   (0x7U)
+#define XRDC_PDAC_W_D0ACP_SHIFT                  (0U)
+#define XRDC_PDAC_W_D0ACP(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D0ACP_SHIFT)) & XRDC_PDAC_W_D0ACP_MASK)
+#define XRDC_PDAC_W_D1ACP_MASK                   (0x38U)
+#define XRDC_PDAC_W_D1ACP_SHIFT                  (3U)
+#define XRDC_PDAC_W_D1ACP(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D1ACP_SHIFT)) & XRDC_PDAC_W_D1ACP_MASK)
+#define XRDC_PDAC_W_D2ACP_MASK                   (0x1C0U)
+#define XRDC_PDAC_W_D2ACP_SHIFT                  (6U)
+#define XRDC_PDAC_W_D2ACP(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_D2ACP_SHIFT)) & XRDC_PDAC_W_D2ACP_MASK)
+#define XRDC_PDAC_W_EAL_MASK                     (0x3000000U)
+#define XRDC_PDAC_W_EAL_SHIFT                    (24U)
+/*! EAL - Exclusive Access Lock
+ *  0b00..Lock disabled
+ *  0b01..Lock disabled until next reset
+ *  0b10..Lock enabled, lock state = available
+ *  0b11..Lock enabled, lock state = not available
+ */
+#define XRDC_PDAC_W_EAL(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_EAL_SHIFT)) & XRDC_PDAC_W_EAL_MASK)
+#define XRDC_PDAC_W_EALO_MASK                    (0xF000000U)
+#define XRDC_PDAC_W_EALO_SHIFT                   (24U)
+#define XRDC_PDAC_W_EALO(x)                      (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_EALO_SHIFT)) & XRDC_PDAC_W_EALO_MASK)
+#define XRDC_PDAC_W_LK2_MASK                     (0x60000000U)
+#define XRDC_PDAC_W_LK2_SHIFT                    (29U)
+/*! LK2 - Lock
+ *  0b00..Entire PDACs can be written.
+ *  0b01..Entire PDACs can be written.
+ *  0b10..Domain x can only update the DxACP field and the LK2 field; no other PDACs fields can be written.
+ *  0b11..PDACs is locked (read-only) until the next reset.
+ */
+#define XRDC_PDAC_W_LK2(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_LK2_SHIFT)) & XRDC_PDAC_W_LK2_MASK)
+#define XRDC_PDAC_W_VLD_MASK                     (0x80000000U)
+#define XRDC_PDAC_W_VLD_SHIFT                    (31U)
+/*! VLD - Valid
+ *  0b0..The PDACs assignment is invalid.
+ *  0b1..The PDACs assignment is valid.
+ */
+#define XRDC_PDAC_W_VLD(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_PDAC_W_VLD_SHIFT)) & XRDC_PDAC_W_VLD_MASK)
+/*! @} */
+
+/* The count of XRDC_PDAC_W */
+#define XRDC_PDAC_W_COUNT                        (289U)
+
+/* The count of XRDC_PDAC_W */
+#define XRDC_PDAC_W_COUNT2                       (2U)
+
+/*! @name MRGD_W - Memory Region Descriptor */
+/*! @{ */
+#define XRDC_MRGD_W_ACCSET1_MASK                 (0xFFFU)
+#define XRDC_MRGD_W_ACCSET1_SHIFT                (0U)
+#define XRDC_MRGD_W_ACCSET1(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_ACCSET1_SHIFT)) & XRDC_MRGD_W_ACCSET1_MASK)
+#define XRDC_MRGD_W_D0SEL_MASK                   (0x7U)
+#define XRDC_MRGD_W_D0SEL_SHIFT                  (0U)
+#define XRDC_MRGD_W_D0SEL(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D0SEL_SHIFT)) & XRDC_MRGD_W_D0SEL_MASK)
+#define XRDC_MRGD_W_D1SEL_MASK                   (0x38U)
+#define XRDC_MRGD_W_D1SEL_SHIFT                  (3U)
+#define XRDC_MRGD_W_D1SEL(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D1SEL_SHIFT)) & XRDC_MRGD_W_D1SEL_MASK)
+#define XRDC_MRGD_W_ENDADDR_MASK                 (0xFFFFFFE0U)
+#define XRDC_MRGD_W_ENDADDR_SHIFT                (5U)
+#define XRDC_MRGD_W_ENDADDR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_ENDADDR_SHIFT)) & XRDC_MRGD_W_ENDADDR_MASK)
+#define XRDC_MRGD_W_SRTADDR_MASK                 (0xFFFFFFE0U)
+#define XRDC_MRGD_W_SRTADDR_SHIFT                (5U)
+#define XRDC_MRGD_W_SRTADDR(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_SRTADDR_SHIFT)) & XRDC_MRGD_W_SRTADDR_MASK)
+#define XRDC_MRGD_W_D2SEL_MASK                   (0x1C0U)
+#define XRDC_MRGD_W_D2SEL_SHIFT                  (6U)
+#define XRDC_MRGD_W_D2SEL(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_D2SEL_SHIFT)) & XRDC_MRGD_W_D2SEL_MASK)
+#define XRDC_MRGD_W_LKAS1_MASK                   (0x1000U)
+#define XRDC_MRGD_W_LKAS1_SHIFT                  (12U)
+/*! LKAS1 - Lock ACCSET1
+ *  0b0..Writes to ACCSET1 affect lesser modes
+ *  0b1..ACCSET1 cannot be modified
+ */
+#define XRDC_MRGD_W_LKAS1(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_LKAS1_SHIFT)) & XRDC_MRGD_W_LKAS1_MASK)
+#define XRDC_MRGD_W_ACCSET2_MASK                 (0xFFF0000U)
+#define XRDC_MRGD_W_ACCSET2_SHIFT                (16U)
+#define XRDC_MRGD_W_ACCSET2(x)                   (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_ACCSET2_SHIFT)) & XRDC_MRGD_W_ACCSET2_MASK)
+#define XRDC_MRGD_W_EAL_MASK                     (0x3000000U)
+#define XRDC_MRGD_W_EAL_SHIFT                    (24U)
+/*! EAL - Exclusive Access Lock
+ *  0b00..Lock disabled
+ *  0b01..Lock disabled until next reset
+ *  0b10..Lock enabled, lock state = available
+ *  0b11..Lock enabled, lock state = not available
+ */
+#define XRDC_MRGD_W_EAL(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_EAL_SHIFT)) & XRDC_MRGD_W_EAL_MASK)
+#define XRDC_MRGD_W_EALO_MASK                    (0xF000000U)
+#define XRDC_MRGD_W_EALO_SHIFT                   (24U)
+#define XRDC_MRGD_W_EALO(x)                      (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_EALO_SHIFT)) & XRDC_MRGD_W_EALO_MASK)
+#define XRDC_MRGD_W_LKAS2_MASK                   (0x10000000U)
+#define XRDC_MRGD_W_LKAS2_SHIFT                  (28U)
+/*! LKAS2 - Lock ACCSET2
+ *  0b0..Writes to ACCSET2 affect lesser modes
+ *  0b1..ACCSET2 cannot be modified
+ */
+#define XRDC_MRGD_W_LKAS2(x)                     (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_LKAS2_SHIFT)) & XRDC_MRGD_W_LKAS2_MASK)
+#define XRDC_MRGD_W_LK2_MASK                     (0x60000000U)
+#define XRDC_MRGD_W_LK2_SHIFT                    (29U)
+/*! LK2 - Lock
+ *  0b00..Entire MRGDn can be written.
+ *  0b01..Entire MRGDn can be written.
+ *  0b10..Domain x can only update the DxACP field and the LK2 field; no other MRGDn fields can be written.
+ *  0b11..MRGDn is locked (read-only) until the next reset.
+ */
+#define XRDC_MRGD_W_LK2(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_LK2_SHIFT)) & XRDC_MRGD_W_LK2_MASK)
+#define XRDC_MRGD_W_CR_MASK                      (0x80000000U)
+#define XRDC_MRGD_W_CR_SHIFT                     (31U)
+#define XRDC_MRGD_W_CR(x)                        (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_CR_SHIFT)) & XRDC_MRGD_W_CR_MASK)
+#define XRDC_MRGD_W_VLD_MASK                     (0x80000000U)
+#define XRDC_MRGD_W_VLD_SHIFT                    (31U)
+/*! VLD - Valid
+ *  0b0..The MRGDn assignment is invalid.
+ *  0b1..The MRGDn assignment is valid.
+ */
+#define XRDC_MRGD_W_VLD(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC_MRGD_W_VLD_SHIFT)) & XRDC_MRGD_W_VLD_MASK)
+/*! @} */
+
+/* The count of XRDC_MRGD_W */
+#define XRDC_MRGD_W_COUNT                        (24U)
+
+/* The count of XRDC_MRGD_W */
+#define XRDC_MRGD_W_COUNT2                       (5U)
+
+
+/*!
+ * @}
+ */ /* end of group XRDC_Register_Masks */
+
+
+/* XRDC - Peripheral instance base addresses */
+/** Peripheral XRDC base address */
+#define XRDC_BASE                                (0x40014000u)
+/** Peripheral XRDC base pointer */
+#define XRDC                                     ((XRDC_Type *)XRDC_BASE)
+/** Array initializer of XRDC peripheral base addresses */
+#define XRDC_BASE_ADDRS                          { XRDC_BASE }
+/** Array initializer of XRDC peripheral base pointers */
+#define XRDC_BASE_PTRS                           { XRDC }
+
+/*!
+ * @}
+ */ /* end of group XRDC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ZLL Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ZLL_Peripheral_Access_Layer ZLL Peripheral Access Layer
+ * @{
+ */
+
+/** ZLL - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t IRQSTS;                            /**< INTERRUPT REQUEST STATUS, offset: 0x0 */
+  __IO uint32_t PHY_CTRL;                          /**< PHY CONTROL, offset: 0x4 */
+  __IO uint32_t EVENT_TMR;                         /**< EVENT TIMER, offset: 0x8 */
+  __I  uint32_t TIMESTAMP;                         /**< TIMESTAMP, offset: 0xC */
+  __IO uint32_t T1CMP;                             /**< T1 COMPARE, offset: 0x10 */
+  __IO uint32_t T2CMP;                             /**< T2 COMPARE, offset: 0x14 */
+  __IO uint32_t T2PRIMECMP;                        /**< T2 PRIME COMPARE, offset: 0x18 */
+  __IO uint32_t T3CMP;                             /**< T3 COMPARE, offset: 0x1C */
+  __IO uint32_t T4CMP;                             /**< T4 COMPARE, offset: 0x20 */
+  __IO uint32_t PA_PWR;                            /**< PA POWER, offset: 0x24 */
+  __IO uint32_t CHANNEL_NUM0;                      /**< CHANNEL NUMBER 0, offset: 0x28 */
+  __I  uint32_t LQI_AND_RSSI;                      /**< LQI AND RSSI, offset: 0x2C */
+  __IO uint32_t MACSHORTADDRS0;                    /**< MAC SHORT ADDRESS 0, offset: 0x30 */
+  __IO uint32_t MACLONGADDRS0_LSB;                 /**< MAC LONG ADDRESS 0 LSB, offset: 0x34 */
+  __IO uint32_t MACLONGADDRS0_MSB;                 /**< MAC LONG ADDRESS 0 MSB, offset: 0x38 */
+  __IO uint32_t RX_FRAME_FILTER;                   /**< RECEIVE FRAME FILTER, offset: 0x3C */
+  __IO uint32_t CCA_LQI_CTRL;                      /**< CCA AND LQI CONTROL, offset: 0x40 */
+  __IO uint32_t CCA2_CTRL;                         /**< CCA2 CONTROL, offset: 0x44 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t DSM_CTRL;                          /**< DSM CONTROL, offset: 0x4C */
+  __IO uint32_t BSM_CTRL;                          /**< BSM CONTROL, offset: 0x50 */
+  __IO uint32_t MACSHORTADDRS1;                    /**< MAC SHORT ADDRESS FOR PAN1, offset: 0x54 */
+  __IO uint32_t MACLONGADDRS1_LSB;                 /**< MAC LONG ADDRESS 1 LSB, offset: 0x58 */
+  __IO uint32_t MACLONGADDRS1_MSB;                 /**< MAC LONG ADDRESS 1 MSB, offset: 0x5C */
+  __IO uint32_t DUAL_PAN_CTRL;                     /**< DUAL PAN CONTROL, offset: 0x60 */
+  __IO uint32_t CHANNEL_NUM1;                      /**< CHANNEL NUMBER 1, offset: 0x64 */
+  __IO uint32_t SAM_CTRL;                          /**< SAM CONTROL, offset: 0x68 */
+  __IO uint32_t SAM_TABLE;                         /**< SOURCE ADDRESS MANAGEMENT TABLE, offset: 0x6C */
+  __I  uint32_t SAM_MATCH;                         /**< SOURCE ADDRESS MANAGEMENT MATCH, offset: 0x70 */
+  __I  uint32_t SAM_FREE_IDX;                      /**< SAM FREE INDEX, offset: 0x74 */
+  __IO uint32_t SEQ_CTRL_STS;                      /**< SEQUENCE CONTROL AND STATUS, offset: 0x78 */
+  __IO uint32_t ACKDELAY;                          /**< ACK DELAY, offset: 0x7C */
+  __IO uint32_t FILTERFAIL_CODE;                   /**< FILTER FAIL CODE, offset: 0x80 */
+  __IO uint32_t RX_WTR_MARK;                       /**< RECEIVE WATER MARK, offset: 0x84 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t SLOT_PRELOAD;                      /**< SLOT PRELOAD, offset: 0x8C */
+  __I  uint32_t SEQ_STATE;                         /**< 802.15.4 SEQUENCE STATE, offset: 0x90 */
+  __IO uint32_t TMR_PRESCALE;                      /**< TIMER PRESCALER, offset: 0x94 */
+  __IO uint32_t LENIENCY_LSB;                      /**< LENIENCY LSB, offset: 0x98 */
+  __IO uint32_t LENIENCY_MSB;                      /**< LENIENCY MSB, offset: 0x9C */
+  __I  uint32_t PART_ID;                           /**< PART ID, offset: 0xA0 */
+       uint8_t RESERVED_2[92];
+  __IO uint16_t PKT_BUFFER_TX[64];                 /**< Packet Buffer TX, array offset: 0x100, array step: 0x2 */
+  __IO uint16_t PKT_BUFFER_RX[64];                 /**< Packet Buffer RX, array offset: 0x180, array step: 0x2 */
+} ZLL_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ZLL Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ZLL_Register_Masks ZLL Register Masks
+ * @{
+ */
+
+/*! @name IRQSTS - INTERRUPT REQUEST STATUS */
+/*! @{ */
+#define ZLL_IRQSTS_SEQIRQ_MASK                   (0x1U)
+#define ZLL_IRQSTS_SEQIRQ_SHIFT                  (0U)
+/*! SEQIRQ - Sequencer IRQ
+ *  0b0..A Sequencer Interrupt has not occurred
+ *  0b1..A Sequencer Interrupt has occurred
+ */
+#define ZLL_IRQSTS_SEQIRQ(x)                     (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_SEQIRQ_SHIFT)) & ZLL_IRQSTS_SEQIRQ_MASK)
+#define ZLL_IRQSTS_TXIRQ_MASK                    (0x2U)
+#define ZLL_IRQSTS_TXIRQ_SHIFT                   (1U)
+/*! TXIRQ - TX IRQ
+ *  0b0..A TX Interrupt has not occurred
+ *  0b1..A TX Interrupt has occurred
+ */
+#define ZLL_IRQSTS_TXIRQ(x)                      (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TXIRQ_SHIFT)) & ZLL_IRQSTS_TXIRQ_MASK)
+#define ZLL_IRQSTS_RXIRQ_MASK                    (0x4U)
+#define ZLL_IRQSTS_RXIRQ_SHIFT                   (2U)
+/*! RXIRQ - RX IRQ
+ *  0b0..A RX Interrupt has not occurred
+ *  0b1..A RX Interrupt has occurred
+ */
+#define ZLL_IRQSTS_RXIRQ(x)                      (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_RXIRQ_SHIFT)) & ZLL_IRQSTS_RXIRQ_MASK)
+#define ZLL_IRQSTS_CCAIRQ_MASK                   (0x8U)
+#define ZLL_IRQSTS_CCAIRQ_SHIFT                  (3U)
+/*! CCAIRQ - CCA IRQ
+ *  0b0..A CCA Interrupt has not occurred
+ *  0b1..A CCA Interrupt has occurred
+ */
+#define ZLL_IRQSTS_CCAIRQ(x)                     (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_CCAIRQ_SHIFT)) & ZLL_IRQSTS_CCAIRQ_MASK)
+#define ZLL_IRQSTS_RXWTRMRKIRQ_MASK              (0x10U)
+#define ZLL_IRQSTS_RXWTRMRKIRQ_SHIFT             (4U)
+/*! RXWTRMRKIRQ - Receive Watermark IRQ
+ *  0b0..A Receive Watermark Interrupt has not occurred
+ *  0b1..A Receive Watermark Interrupt has occurred
+ */
+#define ZLL_IRQSTS_RXWTRMRKIRQ(x)                (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_RXWTRMRKIRQ_SHIFT)) & ZLL_IRQSTS_RXWTRMRKIRQ_MASK)
+#define ZLL_IRQSTS_FILTERFAIL_IRQ_MASK           (0x20U)
+#define ZLL_IRQSTS_FILTERFAIL_IRQ_SHIFT          (5U)
+/*! FILTERFAIL_IRQ - Filter Fail IRQ
+ *  0b0..A Filter Fail Interrupt has not occurred
+ *  0b1..A Filter Fail Interrupt has occurred
+ */
+#define ZLL_IRQSTS_FILTERFAIL_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_FILTERFAIL_IRQ_SHIFT)) & ZLL_IRQSTS_FILTERFAIL_IRQ_MASK)
+#define ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK           (0x40U)
+#define ZLL_IRQSTS_PLL_UNLOCK_IRQ_SHIFT          (6U)
+/*! PLL_UNLOCK_IRQ - PLL Unlock IRQ
+ *  0b0..A PLL Unlock Interrupt has not occurred
+ *  0b1..A PLL Unlock Interrupt has occurred
+ */
+#define ZLL_IRQSTS_PLL_UNLOCK_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_PLL_UNLOCK_IRQ_SHIFT)) & ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK)
+#define ZLL_IRQSTS_RX_FRM_PEND_MASK              (0x80U)
+#define ZLL_IRQSTS_RX_FRM_PEND_SHIFT             (7U)
+#define ZLL_IRQSTS_RX_FRM_PEND(x)                (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_RX_FRM_PEND_SHIFT)) & ZLL_IRQSTS_RX_FRM_PEND_MASK)
+#define ZLL_IRQSTS_WAKE_IRQ_MASK                 (0x100U)
+#define ZLL_IRQSTS_WAKE_IRQ_SHIFT                (8U)
+/*! WAKE_IRQ - WAKE Interrupt Request
+ *  0b0..A Wake Interrupt has not occurred
+ *  0b1..A Wake Interrupt has occurred
+ */
+#define ZLL_IRQSTS_WAKE_IRQ(x)                   (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_WAKE_IRQ_SHIFT)) & ZLL_IRQSTS_WAKE_IRQ_MASK)
+#define ZLL_IRQSTS_TSM_IRQ_MASK                  (0x400U)
+#define ZLL_IRQSTS_TSM_IRQ_SHIFT                 (10U)
+/*! TSM_IRQ - TSM IRQ
+ *  0b0..A TSM Interrupt has not occurred
+ *  0b1..A TSM Interrupt has occurred
+ */
+#define ZLL_IRQSTS_TSM_IRQ(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TSM_IRQ_SHIFT)) & ZLL_IRQSTS_TSM_IRQ_MASK)
+#define ZLL_IRQSTS_ENH_PKT_STATUS_MASK           (0x800U)
+#define ZLL_IRQSTS_ENH_PKT_STATUS_SHIFT          (11U)
+/*! ENH_PKT_STATUS - Enhanced Packet Status
+ *  0b0..The last packet received was neither 4e- nor 2015-compliant
+ *  0b1..The last packet received was 4e- or 2015-compliant (RX_FRAME_FILTER register should be queried for additional status bits)
+ */
+#define ZLL_IRQSTS_ENH_PKT_STATUS(x)             (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_ENH_PKT_STATUS_SHIFT)) & ZLL_IRQSTS_ENH_PKT_STATUS_MASK)
+#define ZLL_IRQSTS_PI_MASK                       (0x1000U)
+#define ZLL_IRQSTS_PI_SHIFT                      (12U)
+/*! PI - Poll Indication
+ *  0b0..the received packet was not a data request
+ *  0b1..the received packet was a data request, regardless of whether a Source Address table match occurred, or whether Source Address Management is enabled or not
+ */
+#define ZLL_IRQSTS_PI(x)                         (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_PI_SHIFT)) & ZLL_IRQSTS_PI_MASK)
+#define ZLL_IRQSTS_SRCADDR_MASK                  (0x2000U)
+#define ZLL_IRQSTS_SRCADDR_SHIFT                 (13U)
+#define ZLL_IRQSTS_SRCADDR(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_SRCADDR_SHIFT)) & ZLL_IRQSTS_SRCADDR_MASK)
+#define ZLL_IRQSTS_CCA_MASK                      (0x4000U)
+#define ZLL_IRQSTS_CCA_SHIFT                     (14U)
+/*! CCA - CCA Status
+ *  0b0..IDLE
+ *  0b1..BUSY
+ */
+#define ZLL_IRQSTS_CCA(x)                        (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_CCA_SHIFT)) & ZLL_IRQSTS_CCA_MASK)
+#define ZLL_IRQSTS_CRCVALID_MASK                 (0x8000U)
+#define ZLL_IRQSTS_CRCVALID_SHIFT                (15U)
+/*! CRCVALID - CRC Valid Status
+ *  0b0..Rx FCS != calculated CRC (incorrect)
+ *  0b1..Rx FCS = calculated CRC (correct)
+ */
+#define ZLL_IRQSTS_CRCVALID(x)                   (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_CRCVALID_SHIFT)) & ZLL_IRQSTS_CRCVALID_MASK)
+#define ZLL_IRQSTS_TMR1IRQ_MASK                  (0x10000U)
+#define ZLL_IRQSTS_TMR1IRQ_SHIFT                 (16U)
+#define ZLL_IRQSTS_TMR1IRQ(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR1IRQ_SHIFT)) & ZLL_IRQSTS_TMR1IRQ_MASK)
+#define ZLL_IRQSTS_TMR2IRQ_MASK                  (0x20000U)
+#define ZLL_IRQSTS_TMR2IRQ_SHIFT                 (17U)
+#define ZLL_IRQSTS_TMR2IRQ(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR2IRQ_SHIFT)) & ZLL_IRQSTS_TMR2IRQ_MASK)
+#define ZLL_IRQSTS_TMR3IRQ_MASK                  (0x40000U)
+#define ZLL_IRQSTS_TMR3IRQ_SHIFT                 (18U)
+#define ZLL_IRQSTS_TMR3IRQ(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR3IRQ_SHIFT)) & ZLL_IRQSTS_TMR3IRQ_MASK)
+#define ZLL_IRQSTS_TMR4IRQ_MASK                  (0x80000U)
+#define ZLL_IRQSTS_TMR4IRQ_SHIFT                 (19U)
+#define ZLL_IRQSTS_TMR4IRQ(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR4IRQ_SHIFT)) & ZLL_IRQSTS_TMR4IRQ_MASK)
+#define ZLL_IRQSTS_TMR1MSK_MASK                  (0x100000U)
+#define ZLL_IRQSTS_TMR1MSK_SHIFT                 (20U)
+/*! TMR1MSK - Timer Comperator 1 Interrupt Mask bit
+ *  0b0..allows interrupt when comparator matches event timer count
+ *  0b1..Interrupt generation is disabled, but a TMR1IRQ flag can be set
+ */
+#define ZLL_IRQSTS_TMR1MSK(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR1MSK_SHIFT)) & ZLL_IRQSTS_TMR1MSK_MASK)
+#define ZLL_IRQSTS_TMR2MSK_MASK                  (0x200000U)
+#define ZLL_IRQSTS_TMR2MSK_SHIFT                 (21U)
+/*! TMR2MSK - Timer Comperator 2 Interrupt Mask bit
+ *  0b0..allows interrupt when comparator matches event timer count
+ *  0b1..Interrupt generation is disabled, but a TMR2IRQ flag can be set
+ */
+#define ZLL_IRQSTS_TMR2MSK(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR2MSK_SHIFT)) & ZLL_IRQSTS_TMR2MSK_MASK)
+#define ZLL_IRQSTS_TMR3MSK_MASK                  (0x400000U)
+#define ZLL_IRQSTS_TMR3MSK_SHIFT                 (22U)
+/*! TMR3MSK - Timer Comperator 3 Interrupt Mask bit
+ *  0b0..allows interrupt when comparator matches event timer count
+ *  0b1..Interrupt generation is disabled, but a TMR3IRQ flag can be set
+ */
+#define ZLL_IRQSTS_TMR3MSK(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR3MSK_SHIFT)) & ZLL_IRQSTS_TMR3MSK_MASK)
+#define ZLL_IRQSTS_TMR4MSK_MASK                  (0x800000U)
+#define ZLL_IRQSTS_TMR4MSK_SHIFT                 (23U)
+/*! TMR4MSK - Timer Comperator 4 Interrupt Mask bit
+ *  0b0..allows interrupt when comparator matches event timer count
+ *  0b1..Interrupt generation is disabled, but a TMR4IRQ flag can be set
+ */
+#define ZLL_IRQSTS_TMR4MSK(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR4MSK_SHIFT)) & ZLL_IRQSTS_TMR4MSK_MASK)
+#define ZLL_IRQSTS_RX_FRAME_LENGTH_MASK          (0x7F000000U)
+#define ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT         (24U)
+#define ZLL_IRQSTS_RX_FRAME_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT)) & ZLL_IRQSTS_RX_FRAME_LENGTH_MASK)
+/*! @} */
+
+/*! @name PHY_CTRL - PHY CONTROL */
+/*! @{ */
+#define ZLL_PHY_CTRL_XCVSEQ_MASK                 (0x7U)
+#define ZLL_PHY_CTRL_XCVSEQ_SHIFT                (0U)
+/*! XCVSEQ - 802.15.4 Transceiver Sequence Selector
+ *  0b000..I (IDLE)
+ *  0b001..R (RECEIVE)
+ *  0b010..T (TRANSMIT)
+ *  0b011..C (CCA)
+ *  0b100..TR (TRANSMIT/RECEIVE)
+ *  0b101..CCCA (CONTINUOUS CCA)
+ *  0b110..Reserved
+ *  0b111..Reserved
+ */
+#define ZLL_PHY_CTRL_XCVSEQ(x)                   (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_XCVSEQ_SHIFT)) & ZLL_PHY_CTRL_XCVSEQ_MASK)
+#define ZLL_PHY_CTRL_AUTOACK_MASK                (0x8U)
+#define ZLL_PHY_CTRL_AUTOACK_SHIFT               (3U)
+/*! AUTOACK - Auto Acknowledge Enable
+ *  0b0..sequence manager will not follow a receive frame with a Tx Ack frame, under any conditions; the autosequence will terminate after the receive frame.
+ *  0b1..sequence manager will follow a receive frame with an automatic hardware-generated Tx Ack frame, assuming other necessary conditions are met.
+ */
+#define ZLL_PHY_CTRL_AUTOACK(x)                  (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_AUTOACK_SHIFT)) & ZLL_PHY_CTRL_AUTOACK_MASK)
+#define ZLL_PHY_CTRL_RXACKRQD_MASK               (0x10U)
+#define ZLL_PHY_CTRL_RXACKRQD_SHIFT              (4U)
+/*! RXACKRQD - Receive Acknowledge Frame required
+ *  0b0..An ordinary receive frame (any type of frame) follows the transmit frame.
+ *  0b1..A receive Ack frame is expected to follow the transmit frame (non-Ack frames are rejected).
+ */
+#define ZLL_PHY_CTRL_RXACKRQD(x)                 (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_RXACKRQD_SHIFT)) & ZLL_PHY_CTRL_RXACKRQD_MASK)
+#define ZLL_PHY_CTRL_CCABFRTX_MASK               (0x20U)
+#define ZLL_PHY_CTRL_CCABFRTX_SHIFT              (5U)
+/*! CCABFRTX - CCA Before TX
+ *  0b0..no CCA required, transmit operation begins immediately.
+ *  0b1..at least one CCA measurement is required prior to the transmit operation (see also SLOTTED).
+ */
+#define ZLL_PHY_CTRL_CCABFRTX(x)                 (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_CCABFRTX_SHIFT)) & ZLL_PHY_CTRL_CCABFRTX_MASK)
+#define ZLL_PHY_CTRL_SLOTTED_MASK                (0x40U)
+#define ZLL_PHY_CTRL_SLOTTED_SHIFT               (6U)
+#define ZLL_PHY_CTRL_SLOTTED(x)                  (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_SLOTTED_SHIFT)) & ZLL_PHY_CTRL_SLOTTED_MASK)
+#define ZLL_PHY_CTRL_TMRTRIGEN_MASK              (0x80U)
+#define ZLL_PHY_CTRL_TMRTRIGEN_SHIFT             (7U)
+/*! TMRTRIGEN - Timer2 Trigger Enable
+ *  0b0..programmed sequence initiates immediately upon write to XCVSEQ.
+ *  0b1..allow timer TC2 (or TC2') to initiate a preprogrammed sequence (see XCVSEQ register).
+ */
+#define ZLL_PHY_CTRL_TMRTRIGEN(x)                (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMRTRIGEN_SHIFT)) & ZLL_PHY_CTRL_TMRTRIGEN_MASK)
+#define ZLL_PHY_CTRL_SEQMSK_MASK                 (0x100U)
+#define ZLL_PHY_CTRL_SEQMSK_SHIFT                (8U)
+/*! SEQMSK - Sequencer Interrupt Mask
+ *  0b0..allows completion of an autosequence to generate a zigbee interrupt
+ *  0b1..Completion of an autosequence will set the SEQIRQ status bit, but a zigbee interrupt is not generated
+ */
+#define ZLL_PHY_CTRL_SEQMSK(x)                   (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_SEQMSK_SHIFT)) & ZLL_PHY_CTRL_SEQMSK_MASK)
+#define ZLL_PHY_CTRL_TXMSK_MASK                  (0x200U)
+#define ZLL_PHY_CTRL_TXMSK_SHIFT                 (9U)
+/*! TXMSK - TX Interrupt Mask
+ *  0b0..allows completion of a TX operation to generate a zigbee interrupt
+ *  0b1..Completion of a TX operation will set the TXIRQ status bit, but a zigbee interrupt is not generated
+ */
+#define ZLL_PHY_CTRL_TXMSK(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TXMSK_SHIFT)) & ZLL_PHY_CTRL_TXMSK_MASK)
+#define ZLL_PHY_CTRL_RXMSK_MASK                  (0x400U)
+#define ZLL_PHY_CTRL_RXMSK_SHIFT                 (10U)
+/*! RXMSK - RX Interrupt Mask
+ *  0b0..allows completion of a RX operation to generate a zigbee interrupt
+ *  0b1..Completion of a RX operation will set the RXIRQ status bit, but a zigbee interrupt is not generated
+ */
+#define ZLL_PHY_CTRL_RXMSK(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_RXMSK_SHIFT)) & ZLL_PHY_CTRL_RXMSK_MASK)
+#define ZLL_PHY_CTRL_CCAMSK_MASK                 (0x800U)
+#define ZLL_PHY_CTRL_CCAMSK_SHIFT                (11U)
+/*! CCAMSK - CCA Interrupt Mask
+ *  0b0..allows completion of a CCA operation to generate a zigbee interrupt
+ *  0b1..Completion of a CCA operation will set the CCA status bit, but a zigbee interrupt is not generated
+ */
+#define ZLL_PHY_CTRL_CCAMSK(x)                   (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_CCAMSK_SHIFT)) & ZLL_PHY_CTRL_CCAMSK_MASK)
+#define ZLL_PHY_CTRL_RX_WMRK_MSK_MASK            (0x1000U)
+#define ZLL_PHY_CTRL_RX_WMRK_MSK_SHIFT           (12U)
+/*! RX_WMRK_MSK - RX Watermark Interrupt Mask
+ *  0b0..allows a Received Byte Count match to the RX_WTR_MARK threshold register to generate a zigbee interrupt
+ *  0b1..A Received Byte Count match to the RX_WTR_MARK threshold register will set the RXWTRMRKIRQ status bit, but a zigbee interrupt is not generated
+ */
+#define ZLL_PHY_CTRL_RX_WMRK_MSK(x)              (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_RX_WMRK_MSK_SHIFT)) & ZLL_PHY_CTRL_RX_WMRK_MSK_MASK)
+#define ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK         (0x2000U)
+#define ZLL_PHY_CTRL_FILTERFAIL_MSK_SHIFT        (13U)
+/*! FILTERFAIL_MSK - FilterFail Interrupt Mask
+ *  0b0..allows Packet Processor Filtering Failure to generate a zigbee interrupt
+ *  0b1..A Packet Processor Filtering Failure will set the FILTERFAIL_IRQ status bit, but a zigbee interrupt is not generated
+ */
+#define ZLL_PHY_CTRL_FILTERFAIL_MSK(x)           (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_FILTERFAIL_MSK_SHIFT)) & ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK)
+#define ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK         (0x4000U)
+#define ZLL_PHY_CTRL_PLL_UNLOCK_MSK_SHIFT        (14U)
+/*! PLL_UNLOCK_MSK - PLL Unlock Interrupt Mask
+ *  0b0..allows PLL unlock event to generate a zigbee interrupt
+ *  0b1..A PLL unlock event will set the PLL_UNLOCK_IRQ status bit, but a zigbee interrupt is not generated
+ */
+#define ZLL_PHY_CTRL_PLL_UNLOCK_MSK(x)           (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_PLL_UNLOCK_MSK_SHIFT)) & ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK)
+#define ZLL_PHY_CTRL_CRC_MSK_MASK                (0x8000U)
+#define ZLL_PHY_CTRL_CRC_MSK_SHIFT               (15U)
+/*! CRC_MSK - CRC Mask
+ *  0b0..sequence manager ignores CRCVALID and considers the receive operation complete after the last octet of the frame has been received.
+ *  0b1..sequence manager requires CRCVALID=1 at the end of the received frame in order for the receive operation to complete successfully; if CRCVALID=0, sequence manager will return to preamble-detect mode after the last octet of the frame has been received.
+ */
+#define ZLL_PHY_CTRL_CRC_MSK(x)                  (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_CRC_MSK_SHIFT)) & ZLL_PHY_CTRL_CRC_MSK_MASK)
+#define ZLL_PHY_CTRL_WAKE_MSK_MASK               (0x10000U)
+#define ZLL_PHY_CTRL_WAKE_MSK_SHIFT              (16U)
+/*! WAKE_MSK
+ *  0b0..Allows a wakeup from DSM to generate a zigbee interrupt
+ *  0b1..Wakeup from DSM will set the WAKE_IRQ status bit, but a zigbee interrupt is not generated
+ */
+#define ZLL_PHY_CTRL_WAKE_MSK(x)                 (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_WAKE_MSK_SHIFT)) & ZLL_PHY_CTRL_WAKE_MSK_MASK)
+#define ZLL_PHY_CTRL_TSM_MSK_MASK                (0x40000U)
+#define ZLL_PHY_CTRL_TSM_MSK_SHIFT               (18U)
+/*! TSM_MSK
+ *  0b0..allows assertion of a TSM interrupt to generate a zigbee interrupt
+ *  0b1..Assertion of a TSM interrupt will set the TSM_IRQ status bit, but a zigbee interrupt is not generated
+ */
+#define ZLL_PHY_CTRL_TSM_MSK(x)                  (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TSM_MSK_SHIFT)) & ZLL_PHY_CTRL_TSM_MSK_MASK)
+#define ZLL_PHY_CTRL_TMR1CMP_EN_MASK             (0x100000U)
+#define ZLL_PHY_CTRL_TMR1CMP_EN_SHIFT            (20U)
+/*! TMR1CMP_EN - Timer 1 Compare Enable
+ *  0b0..Don't allow an Event Timer Match to T1CMP to set TMR1IRQ
+ *  0b1..Allow an Event Timer Match to T1CMP to set TMR1IRQ
+ */
+#define ZLL_PHY_CTRL_TMR1CMP_EN(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMR1CMP_EN_SHIFT)) & ZLL_PHY_CTRL_TMR1CMP_EN_MASK)
+#define ZLL_PHY_CTRL_TMR2CMP_EN_MASK             (0x200000U)
+#define ZLL_PHY_CTRL_TMR2CMP_EN_SHIFT            (21U)
+/*! TMR2CMP_EN - Timer 2 Compare Enable
+ *  0b0..Don't allow an Event Timer Match to T2CMP or T2PRIMECMP to set TMR2IRQ
+ *  0b1..Allow an Event Timer Match to T2CMP or T2PRIMECMP to set TMR2IRQ
+ */
+#define ZLL_PHY_CTRL_TMR2CMP_EN(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMR2CMP_EN_SHIFT)) & ZLL_PHY_CTRL_TMR2CMP_EN_MASK)
+#define ZLL_PHY_CTRL_TMR3CMP_EN_MASK             (0x400000U)
+#define ZLL_PHY_CTRL_TMR3CMP_EN_SHIFT            (22U)
+/*! TMR3CMP_EN - Timer 3 Compare Enable
+ *  0b0..Don't allow an Event Timer Match to T3CMP to set TMR3IRQ
+ *  0b1..Allow an Event Timer Match to T3CMP to set TMR3IRQ
+ */
+#define ZLL_PHY_CTRL_TMR3CMP_EN(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMR3CMP_EN_SHIFT)) & ZLL_PHY_CTRL_TMR3CMP_EN_MASK)
+#define ZLL_PHY_CTRL_TMR4CMP_EN_MASK             (0x800000U)
+#define ZLL_PHY_CTRL_TMR4CMP_EN_SHIFT            (23U)
+/*! TMR4CMP_EN - Timer 4 Compare Enable
+ *  0b0..Don't allow an Event Timer Match to T4CMP to set TMR4IRQ
+ *  0b1..Allow an Event Timer Match to T4CMP to set TMR4IRQ
+ */
+#define ZLL_PHY_CTRL_TMR4CMP_EN(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMR4CMP_EN_SHIFT)) & ZLL_PHY_CTRL_TMR4CMP_EN_MASK)
+#define ZLL_PHY_CTRL_TC2PRIME_EN_MASK            (0x1000000U)
+#define ZLL_PHY_CTRL_TC2PRIME_EN_SHIFT           (24U)
+/*! TC2PRIME_EN - Timer 2 Prime Compare Enable
+ *  0b0..Don't allow a match of the lower 16 bits of Event Timer to T2PRIMECMP to set TMR2IRQ
+ *  0b1..Allow a match of the lower 16 bits of Event Timer to T2PRIMECMP to set TMR2IRQ
+ */
+#define ZLL_PHY_CTRL_TC2PRIME_EN(x)              (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TC2PRIME_EN_SHIFT)) & ZLL_PHY_CTRL_TC2PRIME_EN_MASK)
+#define ZLL_PHY_CTRL_PROMISCUOUS_MASK            (0x2000000U)
+#define ZLL_PHY_CTRL_PROMISCUOUS_SHIFT           (25U)
+/*! PROMISCUOUS - Promiscuous Mode Enable
+ *  0b0..normal mode
+ *  0b1..all packet filtering except frame length checking (FrameLength>=5 and FrameLength<=127) is bypassed.
+ */
+#define ZLL_PHY_CTRL_PROMISCUOUS(x)              (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_PROMISCUOUS_SHIFT)) & ZLL_PHY_CTRL_PROMISCUOUS_MASK)
+#define ZLL_PHY_CTRL_TC3_POSTPONE_ON_SFD_MASK    (0x4000000U)
+#define ZLL_PHY_CTRL_TC3_POSTPONE_ON_SFD_SHIFT   (26U)
+/*! TC3_POSTPONE_ON_SFD - Postpone TC3 Timeout On SFD Enable
+ *  0b0..TC3 Abort will occur on TMR3 timeout, regardless of rx_sfd_detect
+ *  0b1..TC3 Abort will be deferred on TMR3 timeout if rx_sfd_detect is asserted; otherwise the TC3 Abort will occur immediately
+ */
+#define ZLL_PHY_CTRL_TC3_POSTPONE_ON_SFD(x)      (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TC3_POSTPONE_ON_SFD_SHIFT)) & ZLL_PHY_CTRL_TC3_POSTPONE_ON_SFD_MASK)
+#define ZLL_PHY_CTRL_CCATYPE_MASK                (0x18000000U)
+#define ZLL_PHY_CTRL_CCATYPE_SHIFT               (27U)
+/*! CCATYPE - Clear Channel Assessment Type
+ *  0b00..ENERGY DETECT
+ *  0b01..CCA MODE 1
+ *  0b10..CCA MODE 2
+ *  0b11..CCA MODE 3
+ */
+#define ZLL_PHY_CTRL_CCATYPE(x)                  (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_CCATYPE_SHIFT)) & ZLL_PHY_CTRL_CCATYPE_MASK)
+#define ZLL_PHY_CTRL_PANCORDNTR0_MASK            (0x20000000U)
+#define ZLL_PHY_CTRL_PANCORDNTR0_SHIFT           (29U)
+#define ZLL_PHY_CTRL_PANCORDNTR0(x)              (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_PANCORDNTR0_SHIFT)) & ZLL_PHY_CTRL_PANCORDNTR0_MASK)
+#define ZLL_PHY_CTRL_TC3TMOUT_MASK               (0x40000000U)
+#define ZLL_PHY_CTRL_TC3TMOUT_SHIFT              (30U)
+/*! TC3TMOUT - TMR3 Timeout Enable
+ *  0b0..TMR3 is a software timer only
+ *  0b1..Enable TMR3 to abort Rx or CCCA operations.
+ */
+#define ZLL_PHY_CTRL_TC3TMOUT(x)                 (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TC3TMOUT_SHIFT)) & ZLL_PHY_CTRL_TC3TMOUT_MASK)
+#define ZLL_PHY_CTRL_TRCV_MSK_MASK               (0x80000000U)
+#define ZLL_PHY_CTRL_TRCV_MSK_SHIFT              (31U)
+/*! TRCV_MSK - Transceiver Global Interrupt Mask
+ *  0b0..Enable any unmasked interrupt source to assert zigbee interrupt
+ *  0b1..Mask all interrupt sources from asserting zigbee interrupt
+ */
+#define ZLL_PHY_CTRL_TRCV_MSK(x)                 (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TRCV_MSK_SHIFT)) & ZLL_PHY_CTRL_TRCV_MSK_MASK)
+/*! @} */
+
+/*! @name EVENT_TMR - EVENT TIMER */
+/*! @{ */
+#define ZLL_EVENT_TMR_EVENT_TMR_LD_MASK          (0x1U)
+#define ZLL_EVENT_TMR_EVENT_TMR_LD_SHIFT         (0U)
+#define ZLL_EVENT_TMR_EVENT_TMR_LD(x)            (((uint32_t)(((uint32_t)(x)) << ZLL_EVENT_TMR_EVENT_TMR_LD_SHIFT)) & ZLL_EVENT_TMR_EVENT_TMR_LD_MASK)
+#define ZLL_EVENT_TMR_EVENT_TMR_ADD_MASK         (0x2U)
+#define ZLL_EVENT_TMR_EVENT_TMR_ADD_SHIFT        (1U)
+#define ZLL_EVENT_TMR_EVENT_TMR_ADD(x)           (((uint32_t)(((uint32_t)(x)) << ZLL_EVENT_TMR_EVENT_TMR_ADD_SHIFT)) & ZLL_EVENT_TMR_EVENT_TMR_ADD_MASK)
+#define ZLL_EVENT_TMR_EVENT_TMR_FRAC_MASK        (0xF0U)
+#define ZLL_EVENT_TMR_EVENT_TMR_FRAC_SHIFT       (4U)
+#define ZLL_EVENT_TMR_EVENT_TMR_FRAC(x)          (((uint32_t)(((uint32_t)(x)) << ZLL_EVENT_TMR_EVENT_TMR_FRAC_SHIFT)) & ZLL_EVENT_TMR_EVENT_TMR_FRAC_MASK)
+#define ZLL_EVENT_TMR_EVENT_TMR_MASK             (0xFFFFFF00U)
+#define ZLL_EVENT_TMR_EVENT_TMR_SHIFT            (8U)
+#define ZLL_EVENT_TMR_EVENT_TMR(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_EVENT_TMR_EVENT_TMR_SHIFT)) & ZLL_EVENT_TMR_EVENT_TMR_MASK)
+/*! @} */
+
+/*! @name TIMESTAMP - TIMESTAMP */
+/*! @{ */
+#define ZLL_TIMESTAMP_TIMESTAMP_FRAC_MASK        (0xF0U)
+#define ZLL_TIMESTAMP_TIMESTAMP_FRAC_SHIFT       (4U)
+#define ZLL_TIMESTAMP_TIMESTAMP_FRAC(x)          (((uint32_t)(((uint32_t)(x)) << ZLL_TIMESTAMP_TIMESTAMP_FRAC_SHIFT)) & ZLL_TIMESTAMP_TIMESTAMP_FRAC_MASK)
+#define ZLL_TIMESTAMP_TIMESTAMP_MASK             (0xFFFFFF00U)
+#define ZLL_TIMESTAMP_TIMESTAMP_SHIFT            (8U)
+#define ZLL_TIMESTAMP_TIMESTAMP(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_TIMESTAMP_TIMESTAMP_SHIFT)) & ZLL_TIMESTAMP_TIMESTAMP_MASK)
+/*! @} */
+
+/*! @name T1CMP - T1 COMPARE */
+/*! @{ */
+#define ZLL_T1CMP_T1CMP_MASK                     (0xFFFFFFU)
+#define ZLL_T1CMP_T1CMP_SHIFT                    (0U)
+#define ZLL_T1CMP_T1CMP(x)                       (((uint32_t)(((uint32_t)(x)) << ZLL_T1CMP_T1CMP_SHIFT)) & ZLL_T1CMP_T1CMP_MASK)
+/*! @} */
+
+/*! @name T2CMP - T2 COMPARE */
+/*! @{ */
+#define ZLL_T2CMP_T2CMP_MASK                     (0xFFFFFFU)
+#define ZLL_T2CMP_T2CMP_SHIFT                    (0U)
+#define ZLL_T2CMP_T2CMP(x)                       (((uint32_t)(((uint32_t)(x)) << ZLL_T2CMP_T2CMP_SHIFT)) & ZLL_T2CMP_T2CMP_MASK)
+/*! @} */
+
+/*! @name T2PRIMECMP - T2 PRIME COMPARE */
+/*! @{ */
+#define ZLL_T2PRIMECMP_T2PRIMECMP_MASK           (0xFFFFU)
+#define ZLL_T2PRIMECMP_T2PRIMECMP_SHIFT          (0U)
+#define ZLL_T2PRIMECMP_T2PRIMECMP(x)             (((uint32_t)(((uint32_t)(x)) << ZLL_T2PRIMECMP_T2PRIMECMP_SHIFT)) & ZLL_T2PRIMECMP_T2PRIMECMP_MASK)
+/*! @} */
+
+/*! @name T3CMP - T3 COMPARE */
+/*! @{ */
+#define ZLL_T3CMP_T3CMP_MASK                     (0xFFFFFFU)
+#define ZLL_T3CMP_T3CMP_SHIFT                    (0U)
+#define ZLL_T3CMP_T3CMP(x)                       (((uint32_t)(((uint32_t)(x)) << ZLL_T3CMP_T3CMP_SHIFT)) & ZLL_T3CMP_T3CMP_MASK)
+/*! @} */
+
+/*! @name T4CMP - T4 COMPARE */
+/*! @{ */
+#define ZLL_T4CMP_T4CMP_MASK                     (0xFFFFFFU)
+#define ZLL_T4CMP_T4CMP_SHIFT                    (0U)
+#define ZLL_T4CMP_T4CMP(x)                       (((uint32_t)(((uint32_t)(x)) << ZLL_T4CMP_T4CMP_SHIFT)) & ZLL_T4CMP_T4CMP_MASK)
+/*! @} */
+
+/*! @name PA_PWR - PA POWER */
+/*! @{ */
+#define ZLL_PA_PWR_PA_PWR_MASK                   (0x3FU)
+#define ZLL_PA_PWR_PA_PWR_SHIFT                  (0U)
+#define ZLL_PA_PWR_PA_PWR(x)                     (((uint32_t)(((uint32_t)(x)) << ZLL_PA_PWR_PA_PWR_SHIFT)) & ZLL_PA_PWR_PA_PWR_MASK)
+/*! @} */
+
+/*! @name CHANNEL_NUM0 - CHANNEL NUMBER 0 */
+/*! @{ */
+#define ZLL_CHANNEL_NUM0_CHANNEL_NUM0_MASK       (0x7FU)
+#define ZLL_CHANNEL_NUM0_CHANNEL_NUM0_SHIFT      (0U)
+#define ZLL_CHANNEL_NUM0_CHANNEL_NUM0(x)         (((uint32_t)(((uint32_t)(x)) << ZLL_CHANNEL_NUM0_CHANNEL_NUM0_SHIFT)) & ZLL_CHANNEL_NUM0_CHANNEL_NUM0_MASK)
+/*! @} */
+
+/*! @name LQI_AND_RSSI - LQI AND RSSI */
+/*! @{ */
+#define ZLL_LQI_AND_RSSI_LQI_VALUE_MASK          (0xFFU)
+#define ZLL_LQI_AND_RSSI_LQI_VALUE_SHIFT         (0U)
+#define ZLL_LQI_AND_RSSI_LQI_VALUE(x)            (((uint32_t)(((uint32_t)(x)) << ZLL_LQI_AND_RSSI_LQI_VALUE_SHIFT)) & ZLL_LQI_AND_RSSI_LQI_VALUE_MASK)
+#define ZLL_LQI_AND_RSSI_RSSI_MASK               (0xFF00U)
+#define ZLL_LQI_AND_RSSI_RSSI_SHIFT              (8U)
+#define ZLL_LQI_AND_RSSI_RSSI(x)                 (((uint32_t)(((uint32_t)(x)) << ZLL_LQI_AND_RSSI_RSSI_SHIFT)) & ZLL_LQI_AND_RSSI_RSSI_MASK)
+#define ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK        (0xFF0000U)
+#define ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT       (16U)
+#define ZLL_LQI_AND_RSSI_CCA1_ED_FNL(x)          (((uint32_t)(((uint32_t)(x)) << ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT)) & ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK)
+/*! @} */
+
+/*! @name MACSHORTADDRS0 - MAC SHORT ADDRESS 0 */
+/*! @{ */
+#define ZLL_MACSHORTADDRS0_MACPANID0_MASK        (0xFFFFU)
+#define ZLL_MACSHORTADDRS0_MACPANID0_SHIFT       (0U)
+#define ZLL_MACSHORTADDRS0_MACPANID0(x)          (((uint32_t)(((uint32_t)(x)) << ZLL_MACSHORTADDRS0_MACPANID0_SHIFT)) & ZLL_MACSHORTADDRS0_MACPANID0_MASK)
+#define ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK   (0xFFFF0000U)
+#define ZLL_MACSHORTADDRS0_MACSHORTADDRS0_SHIFT  (16U)
+#define ZLL_MACSHORTADDRS0_MACSHORTADDRS0(x)     (((uint32_t)(((uint32_t)(x)) << ZLL_MACSHORTADDRS0_MACSHORTADDRS0_SHIFT)) & ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK)
+/*! @} */
+
+/*! @name MACLONGADDRS0_LSB - MAC LONG ADDRESS 0 LSB */
+/*! @{ */
+#define ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_MASK (0xFFFFFFFFU)
+#define ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_SHIFT (0U)
+#define ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_SHIFT)) & ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_MASK)
+/*! @} */
+
+/*! @name MACLONGADDRS0_MSB - MAC LONG ADDRESS 0 MSB */
+/*! @{ */
+#define ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_MASK (0xFFFFFFFFU)
+#define ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_SHIFT (0U)
+#define ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_SHIFT)) & ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_MASK)
+/*! @} */
+
+/*! @name RX_FRAME_FILTER - RECEIVE FRAME FILTER */
+/*! @{ */
+#define ZLL_RX_FRAME_FILTER_BEACON_FT_MASK       (0x1U)
+#define ZLL_RX_FRAME_FILTER_BEACON_FT_SHIFT      (0U)
+/*! BEACON_FT - Beacon Frame Type Enable
+ *  0b0..reject all Beacon frames
+ *  0b1..Beacon frame type enabled.
+ */
+#define ZLL_RX_FRAME_FILTER_BEACON_FT(x)         (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_BEACON_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_BEACON_FT_MASK)
+#define ZLL_RX_FRAME_FILTER_DATA_FT_MASK         (0x2U)
+#define ZLL_RX_FRAME_FILTER_DATA_FT_SHIFT        (1U)
+/*! DATA_FT - Data Frame Type Enable
+ *  0b0..reject all Beacon frames
+ *  0b1..Data frame type enabled.
+ */
+#define ZLL_RX_FRAME_FILTER_DATA_FT(x)           (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_DATA_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_DATA_FT_MASK)
+#define ZLL_RX_FRAME_FILTER_ACK_FT_MASK          (0x4U)
+#define ZLL_RX_FRAME_FILTER_ACK_FT_SHIFT         (2U)
+/*! ACK_FT - Ack Frame Type Enable
+ *  0b0..reject all Acknowledge frames
+ *  0b1..Acknowledge frame type enabled.
+ */
+#define ZLL_RX_FRAME_FILTER_ACK_FT(x)            (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_ACK_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_ACK_FT_MASK)
+#define ZLL_RX_FRAME_FILTER_CMD_FT_MASK          (0x8U)
+#define ZLL_RX_FRAME_FILTER_CMD_FT_SHIFT         (3U)
+/*! CMD_FT - MAC Command Frame Type Enable
+ *  0b0..reject all MAC Command frames
+ *  0b1..MAC Command frame type enabled.
+ */
+#define ZLL_RX_FRAME_FILTER_CMD_FT(x)            (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_CMD_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_CMD_FT_MASK)
+#define ZLL_RX_FRAME_FILTER_LLDN_FT_MASK         (0x10U)
+#define ZLL_RX_FRAME_FILTER_LLDN_FT_SHIFT        (4U)
+/*! LLDN_FT - LLDN Frame Type Enable
+ *  0b0..reject all LLDN frames
+ *  0b1..LLDN frame type enabled (Frame Type 4).
+ */
+#define ZLL_RX_FRAME_FILTER_LLDN_FT(x)           (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_LLDN_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_LLDN_FT_MASK)
+#define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT_MASK (0x20U)
+#define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT_SHIFT (5U)
+/*! MULTIPURPOSE_FT - Multipurpose Frame Type Enable
+ *  0b0..reject all Multipurpose frames
+ *  0b1..Multipurpose frame type enabled (Frame Type 5).
+ */
+#define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT(x)   (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT_MASK)
+#define ZLL_RX_FRAME_FILTER_NS_FT_MASK           (0x40U)
+#define ZLL_RX_FRAME_FILTER_NS_FT_SHIFT          (6U)
+/*! NS_FT - "Not Specified" Frame Type Enable
+ *  0b0..reject all "Not Specified" frames
+ *  0b1..Not-specified (reserved) frame type enabled. Applies to Frame Type 6. No packet filtering is performed, except for frame length checking (FrameLength>=5 and FrameLength<=127). No AUTOACK is transmitted for this Frame Type
+ */
+#define ZLL_RX_FRAME_FILTER_NS_FT(x)             (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_NS_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_NS_FT_MASK)
+#define ZLL_RX_FRAME_FILTER_EXTENDED_FT_MASK     (0x80U)
+#define ZLL_RX_FRAME_FILTER_EXTENDED_FT_SHIFT    (7U)
+/*! EXTENDED_FT - Extended Frame Type Enable
+ *  0b0..reject all Extended frames
+ *  0b1..Extended frame type enabled (Frame Type 7).
+ */
+#define ZLL_RX_FRAME_FILTER_EXTENDED_FT(x)       (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_EXTENDED_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_EXTENDED_FT_MASK)
+#define ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_MASK  (0xF00U)
+#define ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_SHIFT (8U)
+#define ZLL_RX_FRAME_FILTER_FRM_VER_FILTER(x)    (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_SHIFT)) & ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_MASK)
+#define ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_MASK (0x4000U)
+#define ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_SHIFT (14U)
+/*! ACTIVE_PROMISCUOUS - Active Promiscuous
+ *  0b0..normal operation
+ *  0b1..Provide Data Indication on all received packets under the same rules which apply in PROMISCUOUS mode, however acknowledge those packets under rules which apply in non-PROMISCUOUS mode
+ */
+#define ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_SHIFT)) & ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_MASK)
+#define ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK_MASK (0x8000U)
+#define ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK_SHIFT (15U)
+/*! EXTENDED_FCS_CHK - Verify FCS on Frame Type Extended
+ *  0b0..Packet Processor will not check FCS for Frame Type EXTENDED (default)
+ *  0b1..Packet Processor will check FCS at end-of-packet based on packet length derived from PHR, for Frame Type EXTENDED
+ */
+#define ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK(x)  (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK_SHIFT)) & ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK_MASK)
+#define ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD_MASK (0x10000U)
+#define ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD_SHIFT (16U)
+/*! FV2_BEACON_RECD - Frame Version 2 Beacon Packet Received
+ *  0b0..The last packet received was not Frame Type Beacon with Frame Version 2
+ *  0b1..The last packet received was Frame Type Beacon with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets
+ */
+#define ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD(x)   (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD_MASK)
+#define ZLL_RX_FRAME_FILTER_FV2_DATA_RECD_MASK   (0x20000U)
+#define ZLL_RX_FRAME_FILTER_FV2_DATA_RECD_SHIFT  (17U)
+/*! FV2_DATA_RECD - Frame Version 2 Data Packet Received
+ *  0b0..The last packet received was not Frame Type Data with Frame Version 2
+ *  0b1..The last packet received was Frame Type Data with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets
+ */
+#define ZLL_RX_FRAME_FILTER_FV2_DATA_RECD(x)     (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FV2_DATA_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_FV2_DATA_RECD_MASK)
+#define ZLL_RX_FRAME_FILTER_FV2_ACK_RECD_MASK    (0x40000U)
+#define ZLL_RX_FRAME_FILTER_FV2_ACK_RECD_SHIFT   (18U)
+/*! FV2_ACK_RECD - Frame Version 2 Acknowledge Packet Received
+ *  0b0..The last packet received was not Frame Type Ack with Frame Version 2
+ *  0b1..The last packet received was Frame Type Ack with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets
+ */
+#define ZLL_RX_FRAME_FILTER_FV2_ACK_RECD(x)      (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FV2_ACK_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_FV2_ACK_RECD_MASK)
+#define ZLL_RX_FRAME_FILTER_FV2_CMD_RECD_MASK    (0x80000U)
+#define ZLL_RX_FRAME_FILTER_FV2_CMD_RECD_SHIFT   (19U)
+/*! FV2_CMD_RECD - Frame Version 2 MAC Command Packet Received
+ *  0b0..The last packet received was not Frame Type MAC Command with Frame Version 2
+ *  0b1..The last packet received was Frame Type MAC Command with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets
+ */
+#define ZLL_RX_FRAME_FILTER_FV2_CMD_RECD(x)      (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FV2_CMD_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_FV2_CMD_RECD_MASK)
+#define ZLL_RX_FRAME_FILTER_LLDN_RECD_MASK       (0x100000U)
+#define ZLL_RX_FRAME_FILTER_LLDN_RECD_SHIFT      (20U)
+/*! LLDN_RECD - LLDN Packet Received
+ *  0b0..The last packet received was not Frame Type LLDN
+ *  0b1..The last packet received was Frame Type LLDN, and LLDN_FT=1 to allow such packets.
+ */
+#define ZLL_RX_FRAME_FILTER_LLDN_RECD(x)         (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_LLDN_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_LLDN_RECD_MASK)
+#define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD_MASK (0x200000U)
+#define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD_SHIFT (21U)
+/*! MULTIPURPOSE_RECD - Multipurpose Packet Received
+ *  0b0..last packet received was not Frame Type MULTIPURPOSE
+ *  0b1..The last packet received was Frame Type MULTIPURPOSE, and MULTIPURPOSE_FT=1 to allow such packets.
+ */
+#define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD_MASK)
+#define ZLL_RX_FRAME_FILTER_EXTENDED_RECD_MASK   (0x800000U)
+#define ZLL_RX_FRAME_FILTER_EXTENDED_RECD_SHIFT  (23U)
+/*! EXTENDED_RECD - Extended Packet Received
+ *  0b0..The last packet received was not Frame Type EXTENDED
+ *  0b1..The last packet received was Frame Type EXTENDED, and EXTENDED_FT=1 to allow such packets.
+ */
+#define ZLL_RX_FRAME_FILTER_EXTENDED_RECD(x)     (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_EXTENDED_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_EXTENDED_RECD_MASK)
+/*! @} */
+
+/*! @name CCA_LQI_CTRL - CCA AND LQI CONTROL */
+/*! @{ */
+#define ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK        (0xFFU)
+#define ZLL_CCA_LQI_CTRL_CCA1_THRESH_SHIFT       (0U)
+#define ZLL_CCA_LQI_CTRL_CCA1_THRESH(x)          (((uint32_t)(((uint32_t)(x)) << ZLL_CCA_LQI_CTRL_CCA1_THRESH_SHIFT)) & ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK)
+#define ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_MASK    (0xFF0000U)
+#define ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_SHIFT   (16U)
+#define ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP(x)      (((uint32_t)(((uint32_t)(x)) << ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_SHIFT)) & ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_MASK)
+#define ZLL_CCA_LQI_CTRL_SIMUL_CCA_RX_MASK       (0x1000000U)
+#define ZLL_CCA_LQI_CTRL_SIMUL_CCA_RX_SHIFT      (24U)
+/*! SIMUL_CCA_RX - Simultaneous CCA and Receive Enable
+ *  0b0..Packets can't be received during CCA measurement
+ *  0b1..Packet reception is enabled during CCA measurement if preamble and SFD are detected
+ */
+#define ZLL_CCA_LQI_CTRL_SIMUL_CCA_RX(x)         (((uint32_t)(((uint32_t)(x)) << ZLL_CCA_LQI_CTRL_SIMUL_CCA_RX_SHIFT)) & ZLL_CCA_LQI_CTRL_SIMUL_CCA_RX_MASK)
+#define ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_MASK    (0x8000000U)
+#define ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_SHIFT   (27U)
+/*! CCA3_AND_NOT_OR - CCA Mode 3 AND not OR
+ *  0b0..CCA1 or CCA2
+ *  0b1..CCA1 and CCA2
+ */
+#define ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR(x)      (((uint32_t)(((uint32_t)(x)) << ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_SHIFT)) & ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_MASK)
+/*! @} */
+
+/*! @name CCA2_CTRL - CCA2 CONTROL */
+/*! @{ */
+#define ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_MASK   (0xFU)
+#define ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_SHIFT  (0U)
+#define ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS(x)     (((uint32_t)(((uint32_t)(x)) << ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_SHIFT)) & ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_MASK)
+#define ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_MASK  (0x70U)
+#define ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_SHIFT (4U)
+#define ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH(x)    (((uint32_t)(((uint32_t)(x)) << ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_SHIFT)) & ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_MASK)
+#define ZLL_CCA2_CTRL_CCA2_CORR_THRESH_MASK      (0xFF00U)
+#define ZLL_CCA2_CTRL_CCA2_CORR_THRESH_SHIFT     (8U)
+#define ZLL_CCA2_CTRL_CCA2_CORR_THRESH(x)        (((uint32_t)(((uint32_t)(x)) << ZLL_CCA2_CTRL_CCA2_CORR_THRESH_SHIFT)) & ZLL_CCA2_CTRL_CCA2_CORR_THRESH_MASK)
+/*! @} */
+
+/*! @name DSM_CTRL - DSM CONTROL */
+/*! @{ */
+#define ZLL_DSM_CTRL_ZIGBEE_SLEEP_REQUEST_MASK   (0x1U)
+#define ZLL_DSM_CTRL_ZIGBEE_SLEEP_REQUEST_SHIFT  (0U)
+#define ZLL_DSM_CTRL_ZIGBEE_SLEEP_REQUEST(x)     (((uint32_t)(((uint32_t)(x)) << ZLL_DSM_CTRL_ZIGBEE_SLEEP_REQUEST_SHIFT)) & ZLL_DSM_CTRL_ZIGBEE_SLEEP_REQUEST_MASK)
+/*! @} */
+
+/*! @name BSM_CTRL - BSM CONTROL */
+/*! @{ */
+#define ZLL_BSM_CTRL_BSM_EN_MASK                 (0x1U)
+#define ZLL_BSM_CTRL_BSM_EN_SHIFT                (0U)
+/*! BSM_EN - BSM Enable
+ *  0b0..802.15.4 Bit Streaming Mode Disabled
+ *  0b1..802.15.4 Bit Streaming Mode Enabled
+ */
+#define ZLL_BSM_CTRL_BSM_EN(x)                   (((uint32_t)(((uint32_t)(x)) << ZLL_BSM_CTRL_BSM_EN_SHIFT)) & ZLL_BSM_CTRL_BSM_EN_MASK)
+/*! @} */
+
+/*! @name MACSHORTADDRS1 - MAC SHORT ADDRESS FOR PAN1 */
+/*! @{ */
+#define ZLL_MACSHORTADDRS1_MACPANID1_MASK        (0xFFFFU)
+#define ZLL_MACSHORTADDRS1_MACPANID1_SHIFT       (0U)
+#define ZLL_MACSHORTADDRS1_MACPANID1(x)          (((uint32_t)(((uint32_t)(x)) << ZLL_MACSHORTADDRS1_MACPANID1_SHIFT)) & ZLL_MACSHORTADDRS1_MACPANID1_MASK)
+#define ZLL_MACSHORTADDRS1_MACSHORTADDRS1_MASK   (0xFFFF0000U)
+#define ZLL_MACSHORTADDRS1_MACSHORTADDRS1_SHIFT  (16U)
+#define ZLL_MACSHORTADDRS1_MACSHORTADDRS1(x)     (((uint32_t)(((uint32_t)(x)) << ZLL_MACSHORTADDRS1_MACSHORTADDRS1_SHIFT)) & ZLL_MACSHORTADDRS1_MACSHORTADDRS1_MASK)
+/*! @} */
+
+/*! @name MACLONGADDRS1_LSB - MAC LONG ADDRESS 1 LSB */
+/*! @{ */
+#define ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_MASK (0xFFFFFFFFU)
+#define ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_SHIFT (0U)
+#define ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_SHIFT)) & ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_MASK)
+/*! @} */
+
+/*! @name MACLONGADDRS1_MSB - MAC LONG ADDRESS 1 MSB */
+/*! @{ */
+#define ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_MASK (0xFFFFFFFFU)
+#define ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_SHIFT (0U)
+#define ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_SHIFT)) & ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_MASK)
+/*! @} */
+
+/*! @name DUAL_PAN_CTRL - DUAL PAN CONTROL */
+/*! @{ */
+#define ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_MASK    (0x1U)
+#define ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_SHIFT   (0U)
+/*! ACTIVE_NETWORK - Active Network Selector
+ *  0b0..Select PAN0
+ *  0b1..Select PAN1
+ */
+#define ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK(x)      (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_SHIFT)) & ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_MASK)
+#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_MASK     (0x2U)
+#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_SHIFT    (1U)
+#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO(x)       (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_SHIFT)) & ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_MASK)
+#define ZLL_DUAL_PAN_CTRL_PANCORDNTR1_MASK       (0x4U)
+#define ZLL_DUAL_PAN_CTRL_PANCORDNTR1_SHIFT      (2U)
+#define ZLL_DUAL_PAN_CTRL_PANCORDNTR1(x)         (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_PANCORDNTR1_SHIFT)) & ZLL_DUAL_PAN_CTRL_PANCORDNTR1_MASK)
+#define ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_MASK   (0x8U)
+#define ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_SHIFT  (3U)
+/*! CURRENT_NETWORK - Indicates which PAN is currently selected by hardware
+ *  0b0..PAN0 is selected
+ *  0b1..PAN1 is selected
+ */
+#define ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK(x)     (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_SHIFT)) & ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_MASK)
+#define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_MASK (0x10U)
+#define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_SHIFT (4U)
+#define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_SHIFT)) & ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_MASK)
+#define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_MASK (0x20U)
+#define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_SHIFT (5U)
+#define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_SHIFT)) & ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_MASK)
+#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_MASK    (0xFF00U)
+#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_SHIFT   (8U)
+#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL(x)      (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_SHIFT)) & ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_MASK)
+#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_MASK   (0x3F0000U)
+#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_SHIFT  (16U)
+#define ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN(x)     (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_SHIFT)) & ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_MASK)
+#define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_MASK      (0x400000U)
+#define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_SHIFT     (22U)
+#define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0(x)        (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_SHIFT)) & ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_MASK)
+#define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_MASK      (0x800000U)
+#define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_SHIFT     (23U)
+#define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1(x)        (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_SHIFT)) & ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_MASK)
+/*! @} */
+
+/*! @name CHANNEL_NUM1 - CHANNEL NUMBER 1 */
+/*! @{ */
+#define ZLL_CHANNEL_NUM1_CHANNEL_NUM1_MASK       (0x7FU)
+#define ZLL_CHANNEL_NUM1_CHANNEL_NUM1_SHIFT      (0U)
+#define ZLL_CHANNEL_NUM1_CHANNEL_NUM1(x)         (((uint32_t)(((uint32_t)(x)) << ZLL_CHANNEL_NUM1_CHANNEL_NUM1_SHIFT)) & ZLL_CHANNEL_NUM1_CHANNEL_NUM1_MASK)
+/*! @} */
+
+/*! @name SAM_CTRL - SAM CONTROL */
+/*! @{ */
+#define ZLL_SAM_CTRL_SAP0_EN_MASK                (0x1U)
+#define ZLL_SAM_CTRL_SAP0_EN_SHIFT               (0U)
+/*! SAP0_EN - Enables SAP0 Partition of the SAM Table
+ *  0b0..Disables SAP0 Partition
+ *  0b1..Enables SAP0 Partition
+ */
+#define ZLL_SAM_CTRL_SAP0_EN(x)                  (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAP0_EN_SHIFT)) & ZLL_SAM_CTRL_SAP0_EN_MASK)
+#define ZLL_SAM_CTRL_SAA0_EN_MASK                (0x2U)
+#define ZLL_SAM_CTRL_SAA0_EN_SHIFT               (1U)
+/*! SAA0_EN - Enables SAA0 Partition of the SAM Table
+ *  0b0..Disables SAA0 Partition
+ *  0b1..Enables SAA0 Partition
+ */
+#define ZLL_SAM_CTRL_SAA0_EN(x)                  (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAA0_EN_SHIFT)) & ZLL_SAM_CTRL_SAA0_EN_MASK)
+#define ZLL_SAM_CTRL_SAP1_EN_MASK                (0x4U)
+#define ZLL_SAM_CTRL_SAP1_EN_SHIFT               (2U)
+/*! SAP1_EN - Enables SAP1 Partition of the SAM Table
+ *  0b0..Disables SAP1 Partition
+ *  0b1..Enables SAP1 Partition
+ */
+#define ZLL_SAM_CTRL_SAP1_EN(x)                  (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAP1_EN_SHIFT)) & ZLL_SAM_CTRL_SAP1_EN_MASK)
+#define ZLL_SAM_CTRL_SAA1_EN_MASK                (0x8U)
+#define ZLL_SAM_CTRL_SAA1_EN_SHIFT               (3U)
+/*! SAA1_EN - Enables SAA1 Partition of the SAM Table
+ *  0b0..Disables SAA1 Partition
+ *  0b1..Enables SAA1 Partition
+ */
+#define ZLL_SAM_CTRL_SAA1_EN(x)                  (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAA1_EN_SHIFT)) & ZLL_SAM_CTRL_SAA1_EN_MASK)
+#define ZLL_SAM_CTRL_SAA0_START_MASK             (0xFF00U)
+#define ZLL_SAM_CTRL_SAA0_START_SHIFT            (8U)
+#define ZLL_SAM_CTRL_SAA0_START(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAA0_START_SHIFT)) & ZLL_SAM_CTRL_SAA0_START_MASK)
+#define ZLL_SAM_CTRL_SAP1_START_MASK             (0xFF0000U)
+#define ZLL_SAM_CTRL_SAP1_START_SHIFT            (16U)
+#define ZLL_SAM_CTRL_SAP1_START(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAP1_START_SHIFT)) & ZLL_SAM_CTRL_SAP1_START_MASK)
+#define ZLL_SAM_CTRL_SAA1_START_MASK             (0xFF000000U)
+#define ZLL_SAM_CTRL_SAA1_START_SHIFT            (24U)
+#define ZLL_SAM_CTRL_SAA1_START(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAA1_START_SHIFT)) & ZLL_SAM_CTRL_SAA1_START_MASK)
+/*! @} */
+
+/*! @name SAM_TABLE - SOURCE ADDRESS MANAGEMENT TABLE */
+/*! @{ */
+#define ZLL_SAM_TABLE_SAM_INDEX_MASK             (0x7FU)
+#define ZLL_SAM_TABLE_SAM_INDEX_SHIFT            (0U)
+#define ZLL_SAM_TABLE_SAM_INDEX(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_INDEX_SHIFT)) & ZLL_SAM_TABLE_SAM_INDEX_MASK)
+#define ZLL_SAM_TABLE_SAM_INDEX_WR_MASK          (0x80U)
+#define ZLL_SAM_TABLE_SAM_INDEX_WR_SHIFT         (7U)
+#define ZLL_SAM_TABLE_SAM_INDEX_WR(x)            (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_INDEX_WR_SHIFT)) & ZLL_SAM_TABLE_SAM_INDEX_WR_MASK)
+#define ZLL_SAM_TABLE_SAM_CHECKSUM_MASK          (0xFFFF00U)
+#define ZLL_SAM_TABLE_SAM_CHECKSUM_SHIFT         (8U)
+#define ZLL_SAM_TABLE_SAM_CHECKSUM(x)            (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_CHECKSUM_SHIFT)) & ZLL_SAM_TABLE_SAM_CHECKSUM_MASK)
+#define ZLL_SAM_TABLE_SAM_INDEX_INV_MASK         (0x1000000U)
+#define ZLL_SAM_TABLE_SAM_INDEX_INV_SHIFT        (24U)
+#define ZLL_SAM_TABLE_SAM_INDEX_INV(x)           (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_INDEX_INV_SHIFT)) & ZLL_SAM_TABLE_SAM_INDEX_INV_MASK)
+#define ZLL_SAM_TABLE_SAM_INDEX_EN_MASK          (0x2000000U)
+#define ZLL_SAM_TABLE_SAM_INDEX_EN_SHIFT         (25U)
+#define ZLL_SAM_TABLE_SAM_INDEX_EN(x)            (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_INDEX_EN_SHIFT)) & ZLL_SAM_TABLE_SAM_INDEX_EN_MASK)
+#define ZLL_SAM_TABLE_ACK_FRM_PND_MASK           (0x4000000U)
+#define ZLL_SAM_TABLE_ACK_FRM_PND_SHIFT          (26U)
+#define ZLL_SAM_TABLE_ACK_FRM_PND(x)             (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_ACK_FRM_PND_SHIFT)) & ZLL_SAM_TABLE_ACK_FRM_PND_MASK)
+#define ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_MASK      (0x8000000U)
+#define ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_SHIFT     (27U)
+/*! ACK_FRM_PND_CTRL - Manual Control for AutoTxAck FramePending field
+ *  0b0..the FramePending field of the Frame Control Field of the next automatic TX acknowledge packet is determined by hardware
+ *  0b1..the FramePending field of the Frame Control Field of the next automatic TX acknowledge packet tracks ACK_FRM_PEND
+ */
+#define ZLL_SAM_TABLE_ACK_FRM_PND_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_SHIFT)) & ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_MASK)
+#define ZLL_SAM_TABLE_FIND_FREE_IDX_MASK         (0x10000000U)
+#define ZLL_SAM_TABLE_FIND_FREE_IDX_SHIFT        (28U)
+#define ZLL_SAM_TABLE_FIND_FREE_IDX(x)           (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_FIND_FREE_IDX_SHIFT)) & ZLL_SAM_TABLE_FIND_FREE_IDX_MASK)
+#define ZLL_SAM_TABLE_INVALIDATE_ALL_MASK        (0x20000000U)
+#define ZLL_SAM_TABLE_INVALIDATE_ALL_SHIFT       (29U)
+#define ZLL_SAM_TABLE_INVALIDATE_ALL(x)          (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_INVALIDATE_ALL_SHIFT)) & ZLL_SAM_TABLE_INVALIDATE_ALL_MASK)
+#define ZLL_SAM_TABLE_SAM_BUSY_MASK              (0x80000000U)
+#define ZLL_SAM_TABLE_SAM_BUSY_SHIFT             (31U)
+#define ZLL_SAM_TABLE_SAM_BUSY(x)                (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_BUSY_SHIFT)) & ZLL_SAM_TABLE_SAM_BUSY_MASK)
+/*! @} */
+
+/*! @name SAM_MATCH - SOURCE ADDRESS MANAGEMENT MATCH */
+/*! @{ */
+#define ZLL_SAM_MATCH_SAP0_MATCH_MASK            (0x7FU)
+#define ZLL_SAM_MATCH_SAP0_MATCH_SHIFT           (0U)
+#define ZLL_SAM_MATCH_SAP0_MATCH(x)              (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAP0_MATCH_SHIFT)) & ZLL_SAM_MATCH_SAP0_MATCH_MASK)
+#define ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_MASK     (0x80U)
+#define ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_SHIFT    (7U)
+#define ZLL_SAM_MATCH_SAP0_ADDR_PRESENT(x)       (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_SHIFT)) & ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_MASK)
+#define ZLL_SAM_MATCH_SAA0_MATCH_MASK            (0x7F00U)
+#define ZLL_SAM_MATCH_SAA0_MATCH_SHIFT           (8U)
+#define ZLL_SAM_MATCH_SAA0_MATCH(x)              (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAA0_MATCH_SHIFT)) & ZLL_SAM_MATCH_SAA0_MATCH_MASK)
+#define ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_MASK      (0x8000U)
+#define ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_SHIFT     (15U)
+#define ZLL_SAM_MATCH_SAA0_ADDR_ABSENT(x)        (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_SHIFT)) & ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_MASK)
+#define ZLL_SAM_MATCH_SAP1_MATCH_MASK            (0x7F0000U)
+#define ZLL_SAM_MATCH_SAP1_MATCH_SHIFT           (16U)
+#define ZLL_SAM_MATCH_SAP1_MATCH(x)              (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAP1_MATCH_SHIFT)) & ZLL_SAM_MATCH_SAP1_MATCH_MASK)
+#define ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_MASK     (0x800000U)
+#define ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_SHIFT    (23U)
+#define ZLL_SAM_MATCH_SAP1_ADDR_PRESENT(x)       (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_SHIFT)) & ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_MASK)
+#define ZLL_SAM_MATCH_SAA1_MATCH_MASK            (0x7F000000U)
+#define ZLL_SAM_MATCH_SAA1_MATCH_SHIFT           (24U)
+#define ZLL_SAM_MATCH_SAA1_MATCH(x)              (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAA1_MATCH_SHIFT)) & ZLL_SAM_MATCH_SAA1_MATCH_MASK)
+#define ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_MASK      (0x80000000U)
+#define ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_SHIFT     (31U)
+#define ZLL_SAM_MATCH_SAA1_ADDR_ABSENT(x)        (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_SHIFT)) & ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_MASK)
+/*! @} */
+
+/*! @name SAM_FREE_IDX - SAM FREE INDEX */
+/*! @{ */
+#define ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_MASK  (0xFFU)
+#define ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_SHIFT (0U)
+#define ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX(x)    (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_SHIFT)) & ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_MASK)
+#define ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_MASK  (0xFF00U)
+#define ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_SHIFT (8U)
+#define ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX(x)    (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_SHIFT)) & ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_MASK)
+#define ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_MASK  (0xFF0000U)
+#define ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_SHIFT (16U)
+#define ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX(x)    (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_SHIFT)) & ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_MASK)
+#define ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_MASK  (0xFF000000U)
+#define ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_SHIFT (24U)
+#define ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX(x)    (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_SHIFT)) & ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_MASK)
+/*! @} */
+
+/*! @name SEQ_CTRL_STS - SEQUENCE CONTROL AND STATUS */
+/*! @{ */
+#define ZLL_SEQ_CTRL_STS_FORCE_CLK_ON_MASK       (0x2U)
+#define ZLL_SEQ_CTRL_STS_FORCE_CLK_ON_SHIFT      (1U)
+/*! FORCE_CLK_ON - Force On 802.15.4 phy_gck
+ *  0b0..Allow TSM to control 802.15.4 phy_gck, for minimum power consumption (default)
+ *  0b1..Force on 802.15.4 phy_gclk at all times, for debug purposes only
+ */
+#define ZLL_SEQ_CTRL_STS_FORCE_CLK_ON(x)         (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_FORCE_CLK_ON_SHIFT)) & ZLL_SEQ_CTRL_STS_FORCE_CLK_ON_MASK)
+#define ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_MASK (0x4U)
+#define ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_SHIFT (2U)
+#define ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT(x)  (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_SHIFT)) & ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_MASK)
+#define ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_MASK (0x8U)
+#define ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_SHIFT (3U)
+#define ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_SHIFT)) & ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_MASK)
+#define ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_MASK     (0x10U)
+#define ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_SHIFT    (4U)
+/*! LATCH_PREAMBLE - Stickiness Control for Preamble Detection
+ *  0b0..Don't make PREAMBLE_DET and SFD_DET bits of PHY_STS (SEQ_STATE) Register "sticky", i.e, these status bits reflect the realtime, dynamic state of preamble_detect and sfd_detect
+ *  0b1..Make PREAMBLE_DET and SFD_DET bits of PHY_STS (SEQ_STATE) Register "sticky", i.e.,occurrences of preamble and SFD detection are latched and held until the start of the next autosequence
+ */
+#define ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE(x)       (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_SHIFT)) & ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_MASK)
+#define ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_MASK      (0x20U)
+#define ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_SHIFT     (5U)
+#define ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE(x)        (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_SHIFT)) & ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_MASK)
+#define ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_MASK    (0x40U)
+#define ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_SHIFT   (6U)
+/*! FORCE_CRC_ERROR - Induce a CRC Error in Transmitted Packets
+ *  0b0..normal operation
+ *  0b1..Force the next transmitted packet to have a CRC error
+ */
+#define ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR(x)      (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_SHIFT)) & ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_MASK)
+#define ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_MASK      (0x80U)
+#define ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_SHIFT     (7U)
+/*! CONTINUOUS_EN - Enable Continuous TX or RX Mode
+ *  0b0..normal operation
+ *  0b1..Continuous TX or RX mode is enabled (depending on XCVSEQ setting).
+ */
+#define ZLL_SEQ_CTRL_STS_CONTINUOUS_EN(x)        (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_SHIFT)) & ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_MASK)
+#define ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_MASK      (0x700U)
+#define ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_SHIFT     (8U)
+#define ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL(x)        (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_SHIFT)) & ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_MASK)
+#define ZLL_SEQ_CTRL_STS_SEQ_IDLE_MASK           (0x800U)
+#define ZLL_SEQ_CTRL_STS_SEQ_IDLE_SHIFT          (11U)
+#define ZLL_SEQ_CTRL_STS_SEQ_IDLE(x)             (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_SEQ_IDLE_SHIFT)) & ZLL_SEQ_CTRL_STS_SEQ_IDLE_MASK)
+#define ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_MASK    (0x1000U)
+#define ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_SHIFT   (12U)
+#define ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT(x)      (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_SHIFT)) & ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_MASK)
+#define ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_MASK (0x2000U)
+#define ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_SHIFT (13U)
+#define ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING(x)   (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_SHIFT)) & ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_MASK)
+#define ZLL_SEQ_CTRL_STS_RX_MODE_MASK            (0x4000U)
+#define ZLL_SEQ_CTRL_STS_RX_MODE_SHIFT           (14U)
+#define ZLL_SEQ_CTRL_STS_RX_MODE(x)              (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_RX_MODE_SHIFT)) & ZLL_SEQ_CTRL_STS_RX_MODE_MASK)
+#define ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_MASK (0x8000U)
+#define ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_SHIFT (15U)
+#define ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED(x)  (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_SHIFT)) & ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_MASK)
+#define ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_MASK       (0x3F0000U)
+#define ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_SHIFT      (16U)
+#define ZLL_SEQ_CTRL_STS_SEQ_T_STATUS(x)         (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_SHIFT)) & ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_MASK)
+#define ZLL_SEQ_CTRL_STS_SW_ABORTED_MASK         (0x1000000U)
+#define ZLL_SEQ_CTRL_STS_SW_ABORTED_SHIFT        (24U)
+#define ZLL_SEQ_CTRL_STS_SW_ABORTED(x)           (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_SW_ABORTED_SHIFT)) & ZLL_SEQ_CTRL_STS_SW_ABORTED_MASK)
+#define ZLL_SEQ_CTRL_STS_TC3_ABORTED_MASK        (0x2000000U)
+#define ZLL_SEQ_CTRL_STS_TC3_ABORTED_SHIFT       (25U)
+#define ZLL_SEQ_CTRL_STS_TC3_ABORTED(x)          (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_TC3_ABORTED_SHIFT)) & ZLL_SEQ_CTRL_STS_TC3_ABORTED_MASK)
+#define ZLL_SEQ_CTRL_STS_PLL_ABORTED_MASK        (0x4000000U)
+#define ZLL_SEQ_CTRL_STS_PLL_ABORTED_SHIFT       (26U)
+#define ZLL_SEQ_CTRL_STS_PLL_ABORTED(x)          (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_PLL_ABORTED_SHIFT)) & ZLL_SEQ_CTRL_STS_PLL_ABORTED_MASK)
+#define ZLL_SEQ_CTRL_STS_EXT_ABORTED_MASK        (0x8000000U)
+#define ZLL_SEQ_CTRL_STS_EXT_ABORTED_SHIFT       (27U)
+#define ZLL_SEQ_CTRL_STS_EXT_ABORTED(x)          (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_EXT_ABORTED_SHIFT)) & ZLL_SEQ_CTRL_STS_EXT_ABORTED_MASK)
+/*! @} */
+
+/*! @name ACKDELAY - ACK DELAY */
+/*! @{ */
+#define ZLL_ACKDELAY_ACKDELAY_MASK               (0x3FU)
+#define ZLL_ACKDELAY_ACKDELAY_SHIFT              (0U)
+#define ZLL_ACKDELAY_ACKDELAY(x)                 (((uint32_t)(((uint32_t)(x)) << ZLL_ACKDELAY_ACKDELAY_SHIFT)) & ZLL_ACKDELAY_ACKDELAY_MASK)
+#define ZLL_ACKDELAY_TXDELAY_MASK                (0x3F00U)
+#define ZLL_ACKDELAY_TXDELAY_SHIFT               (8U)
+#define ZLL_ACKDELAY_TXDELAY(x)                  (((uint32_t)(((uint32_t)(x)) << ZLL_ACKDELAY_TXDELAY_SHIFT)) & ZLL_ACKDELAY_TXDELAY_MASK)
+/*! @} */
+
+/*! @name FILTERFAIL_CODE - FILTER FAIL CODE */
+/*! @{ */
+#define ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_MASK (0x3FFU)
+#define ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_SHIFT (0U)
+#define ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE(x)   (((uint32_t)(((uint32_t)(x)) << ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_SHIFT)) & ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_MASK)
+#define ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_MASK (0x8000U)
+#define ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_SHIFT (15U)
+/*! FILTERFAIL_PAN_SEL - PAN Selector for Filter Fail Code
+ *  0b0..FILTERFAIL_CODE[9:0] will report the FILTERFAIL status of PAN0
+ *  0b1..FILTERFAIL_CODE[9:0] will report the FILTERFAIL status of PAN1
+ */
+#define ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_SHIFT)) & ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_MASK)
+/*! @} */
+
+/*! @name RX_WTR_MARK - RECEIVE WATER MARK */
+/*! @{ */
+#define ZLL_RX_WTR_MARK_RX_WTR_MARK_MASK         (0xFFU)
+#define ZLL_RX_WTR_MARK_RX_WTR_MARK_SHIFT        (0U)
+#define ZLL_RX_WTR_MARK_RX_WTR_MARK(x)           (((uint32_t)(((uint32_t)(x)) << ZLL_RX_WTR_MARK_RX_WTR_MARK_SHIFT)) & ZLL_RX_WTR_MARK_RX_WTR_MARK_MASK)
+/*! @} */
+
+/*! @name SLOT_PRELOAD - SLOT PRELOAD */
+/*! @{ */
+#define ZLL_SLOT_PRELOAD_SLOT_PRELOAD_MASK       (0xFFU)
+#define ZLL_SLOT_PRELOAD_SLOT_PRELOAD_SHIFT      (0U)
+#define ZLL_SLOT_PRELOAD_SLOT_PRELOAD(x)         (((uint32_t)(((uint32_t)(x)) << ZLL_SLOT_PRELOAD_SLOT_PRELOAD_SHIFT)) & ZLL_SLOT_PRELOAD_SLOT_PRELOAD_MASK)
+/*! @} */
+
+/*! @name SEQ_STATE - 802.15.4 SEQUENCE STATE */
+/*! @{ */
+#define ZLL_SEQ_STATE_SEQ_STATE_MASK             (0x1FU)
+#define ZLL_SEQ_STATE_SEQ_STATE_SHIFT            (0U)
+#define ZLL_SEQ_STATE_SEQ_STATE(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_SEQ_STATE_SHIFT)) & ZLL_SEQ_STATE_SEQ_STATE_MASK)
+#define ZLL_SEQ_STATE_PREAMBLE_DET_MASK          (0x100U)
+#define ZLL_SEQ_STATE_PREAMBLE_DET_SHIFT         (8U)
+#define ZLL_SEQ_STATE_PREAMBLE_DET(x)            (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_PREAMBLE_DET_SHIFT)) & ZLL_SEQ_STATE_PREAMBLE_DET_MASK)
+#define ZLL_SEQ_STATE_SFD_DET_MASK               (0x200U)
+#define ZLL_SEQ_STATE_SFD_DET_SHIFT              (9U)
+#define ZLL_SEQ_STATE_SFD_DET(x)                 (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_SFD_DET_SHIFT)) & ZLL_SEQ_STATE_SFD_DET_MASK)
+#define ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_MASK   (0x400U)
+#define ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_SHIFT  (10U)
+#define ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL(x)     (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_SHIFT)) & ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_MASK)
+#define ZLL_SEQ_STATE_CRCVALID_MASK              (0x800U)
+#define ZLL_SEQ_STATE_CRCVALID_SHIFT             (11U)
+/*! CRCVALID - CRC Valid Indicator
+ *  0b0..Rx FCS != calculated CRC (incorrect)
+ *  0b1..Rx FCS = calculated CRC (correct)
+ */
+#define ZLL_SEQ_STATE_CRCVALID(x)                (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_CRCVALID_SHIFT)) & ZLL_SEQ_STATE_CRCVALID_MASK)
+#define ZLL_SEQ_STATE_PLL_ABORT_MASK             (0x1000U)
+#define ZLL_SEQ_STATE_PLL_ABORT_SHIFT            (12U)
+#define ZLL_SEQ_STATE_PLL_ABORT(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_PLL_ABORT_SHIFT)) & ZLL_SEQ_STATE_PLL_ABORT_MASK)
+#define ZLL_SEQ_STATE_PLL_ABORTED_MASK           (0x2000U)
+#define ZLL_SEQ_STATE_PLL_ABORTED_SHIFT          (13U)
+#define ZLL_SEQ_STATE_PLL_ABORTED(x)             (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_PLL_ABORTED_SHIFT)) & ZLL_SEQ_STATE_PLL_ABORTED_MASK)
+#define ZLL_SEQ_STATE_RX_BYTE_COUNT_MASK         (0xFF0000U)
+#define ZLL_SEQ_STATE_RX_BYTE_COUNT_SHIFT        (16U)
+#define ZLL_SEQ_STATE_RX_BYTE_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_RX_BYTE_COUNT_SHIFT)) & ZLL_SEQ_STATE_RX_BYTE_COUNT_MASK)
+#define ZLL_SEQ_STATE_CCCA_BUSY_CNT_MASK         (0x3F000000U)
+#define ZLL_SEQ_STATE_CCCA_BUSY_CNT_SHIFT        (24U)
+#define ZLL_SEQ_STATE_CCCA_BUSY_CNT(x)           (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_CCCA_BUSY_CNT_SHIFT)) & ZLL_SEQ_STATE_CCCA_BUSY_CNT_MASK)
+/*! @} */
+
+/*! @name TMR_PRESCALE - TIMER PRESCALER */
+/*! @{ */
+#define ZLL_TMR_PRESCALE_TMR_PRESCALE_MASK       (0x7U)
+#define ZLL_TMR_PRESCALE_TMR_PRESCALE_SHIFT      (0U)
+/*! TMR_PRESCALE - Timer Prescaler
+ *  0b000..Reserved
+ *  0b001..Reserved
+ *  0b010..500kHz (33.55 S)
+ *  0b011..250kHz (67.11 S)
+ *  0b100..125kHz (134.22 S)
+ *  0b101..62.5kHz (268.44 S) -- default
+ *  0b110..31.25kHz (536.87 S)
+ *  0b111..15.625kHz (1073.74 S)
+ */
+#define ZLL_TMR_PRESCALE_TMR_PRESCALE(x)         (((uint32_t)(((uint32_t)(x)) << ZLL_TMR_PRESCALE_TMR_PRESCALE_SHIFT)) & ZLL_TMR_PRESCALE_TMR_PRESCALE_MASK)
+/*! @} */
+
+/*! @name LENIENCY_LSB - LENIENCY LSB */
+/*! @{ */
+#define ZLL_LENIENCY_LSB_LENIENCY_LSB_MASK       (0xFFFFFFFFU)
+#define ZLL_LENIENCY_LSB_LENIENCY_LSB_SHIFT      (0U)
+#define ZLL_LENIENCY_LSB_LENIENCY_LSB(x)         (((uint32_t)(((uint32_t)(x)) << ZLL_LENIENCY_LSB_LENIENCY_LSB_SHIFT)) & ZLL_LENIENCY_LSB_LENIENCY_LSB_MASK)
+/*! @} */
+
+/*! @name LENIENCY_MSB - LENIENCY MSB */
+/*! @{ */
+#define ZLL_LENIENCY_MSB_LENIENCY_MSB_MASK       (0xFFU)
+#define ZLL_LENIENCY_MSB_LENIENCY_MSB_SHIFT      (0U)
+#define ZLL_LENIENCY_MSB_LENIENCY_MSB(x)         (((uint32_t)(((uint32_t)(x)) << ZLL_LENIENCY_MSB_LENIENCY_MSB_SHIFT)) & ZLL_LENIENCY_MSB_LENIENCY_MSB_MASK)
+/*! @} */
+
+/*! @name PART_ID - PART ID */
+/*! @{ */
+#define ZLL_PART_ID_PART_ID_MASK                 (0xFFU)
+#define ZLL_PART_ID_PART_ID_SHIFT                (0U)
+#define ZLL_PART_ID_PART_ID(x)                   (((uint32_t)(((uint32_t)(x)) << ZLL_PART_ID_PART_ID_SHIFT)) & ZLL_PART_ID_PART_ID_MASK)
+/*! @} */
+
+/*! @name PKT_BUFFER_TX - Packet Buffer TX */
+/*! @{ */
+#define ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX_MASK     (0xFFFFU)
+#define ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX_SHIFT    (0U)
+#define ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX(x)       (((uint16_t)(((uint16_t)(x)) << ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX_SHIFT)) & ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX_MASK)
+/*! @} */
+
+/* The count of ZLL_PKT_BUFFER_TX */
+#define ZLL_PKT_BUFFER_TX_COUNT                  (64U)
+
+/*! @name PKT_BUFFER_RX - Packet Buffer RX */
+/*! @{ */
+#define ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX_MASK     (0xFFFFU)
+#define ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX_SHIFT    (0U)
+#define ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX(x)       (((uint16_t)(((uint16_t)(x)) << ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX_SHIFT)) & ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX_MASK)
+/*! @} */
+
+/* The count of ZLL_PKT_BUFFER_RX */
+#define ZLL_PKT_BUFFER_RX_COUNT                  (64U)
+
+
+/*!
+ * @}
+ */ /* end of group ZLL_Register_Masks */
+
+
+/* ZLL - Peripheral instance base addresses */
+/** Peripheral ZLL base address */
+#define ZLL_BASE                                 (0x41034000u)
+/** Peripheral ZLL base pointer */
+#define ZLL                                      ((ZLL_Type *)ZLL_BASE)
+/** Array initializer of ZLL peripheral base addresses */
+#define ZLL_BASE_ADDRS                           { ZLL_BASE }
+/** Array initializer of ZLL peripheral base pointers */
+#define ZLL_BASE_PTRS                            { ZLL }
+
+/*!
+ * @}
+ */ /* end of group ZLL_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang system_header
+  #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDK Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
+ * @{
+ */
+
+#define EVENT_UNIT EVENT1
+#define INTMUX INTMUX1
+
+/*!
+ * @}
+ */ /* end of group SDK_Compatibility_Symbols */
+
+
+#endif  /* _RV32M1_ZERO_RISCY_H_ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/RV32M1_zero_riscy_features.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/RV32M1_zero_riscy_features.h
new file mode 100644
index 0000000..e66424c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/RV32M1_zero_riscy_features.h
@@ -0,0 +1,1582 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.0, 2018-10-02
+**     Build:               b180815
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2018-10-02)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+#ifndef _RV32M1_zero_riscy_FEATURES_H_
+#define _RV32M1_zero_riscy_FEATURES_H_
+
+/* SOC module features */
+
+/* @brief CAU3 availability on the SoC. */
+#define FSL_FEATURE_SOC_CAU3_COUNT (1)
+/* @brief CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_CRC_COUNT (1)
+/* @brief DMAMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
+/* @brief EDMA availability on the SoC. */
+#define FSL_FEATURE_SOC_EDMA_COUNT (1)
+/* @brief EMVSIM availability on the SoC. */
+#define FSL_FEATURE_SOC_EMVSIM_COUNT (1)
+/* @brief EVENT availability on the SoC. */
+#define FSL_FEATURE_SOC_EVENT_COUNT (1)
+/* @brief EWM availability on the SoC. */
+#define FSL_FEATURE_SOC_EWM_COUNT (1)
+/* @brief FB availability on the SoC. */
+#define FSL_FEATURE_SOC_FB_COUNT (1)
+/* @brief FGPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_FGPIO_COUNT (1)
+/* @brief FLASH availability on the SoC. */
+#define FSL_FEATURE_SOC_FLASH_COUNT (1)
+/* @brief FLEXIO availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXIO_COUNT (1)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (5)
+/* @brief I2S availability on the SoC. */
+#define FSL_FEATURE_SOC_I2S_COUNT (1)
+/* @brief INTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INTMUX_COUNT (1)
+/* @brief LLWU availability on the SoC. */
+#define FSL_FEATURE_SOC_LLWU_COUNT (2)
+/* @brief LPADC availability on the SoC. */
+#define FSL_FEATURE_SOC_LPADC_COUNT (1)
+/* @brief LPCMP availability on the SoC. */
+#define FSL_FEATURE_SOC_LPCMP_COUNT (2)
+/* @brief LPDAC availability on the SoC. */
+#define FSL_FEATURE_SOC_LPDAC_COUNT (1)
+/* @brief LPI2C availability on the SoC. */
+#define FSL_FEATURE_SOC_LPI2C_COUNT (4)
+/* @brief LPIT availability on the SoC. */
+#define FSL_FEATURE_SOC_LPIT_COUNT (2)
+/* @brief LPSPI availability on the SoC. */
+#define FSL_FEATURE_SOC_LPSPI_COUNT (4)
+/* @brief LPTMR availability on the SoC. */
+#define FSL_FEATURE_SOC_LPTMR_COUNT (3)
+/* @brief LPUART availability on the SoC. */
+#define FSL_FEATURE_SOC_LPUART_COUNT (4)
+/* @brief MCM availability on the SoC. */
+#define FSL_FEATURE_SOC_MCM_COUNT (1)
+/* @brief MMDVSQ availability on the SoC. */
+#define FSL_FEATURE_SOC_MMDVSQ_COUNT (1)
+/* @brief MSCM availability on the SoC. */
+#define FSL_FEATURE_SOC_MSCM_COUNT (1)
+/* @brief MTB availability on the SoC. */
+#define FSL_FEATURE_SOC_MTB_COUNT (1)
+/* @brief MTBDWT availability on the SoC. */
+#define FSL_FEATURE_SOC_MTBDWT_COUNT (1)
+/* @brief MU availability on the SoC. */
+#define FSL_FEATURE_SOC_MU_COUNT (1)
+/* @brief PCC availability on the SoC. */
+#define FSL_FEATURE_SOC_PCC_COUNT (2)
+/* @brief PORT availability on the SoC. */
+#define FSL_FEATURE_SOC_PORT_COUNT (5)
+/* @brief ROM availability on the SoC. */
+#define FSL_FEATURE_SOC_ROM_COUNT (1)
+/* @brief RSIM availability on the SoC. */
+#define FSL_FEATURE_SOC_RSIM_COUNT (1)
+/* @brief RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_RTC_COUNT (1)
+/* @brief SCG availability on the SoC. */
+#define FSL_FEATURE_SOC_SCG_COUNT (1)
+/* @brief SEMA42 availability on the SoC. */
+#define FSL_FEATURE_SOC_SEMA42_COUNT (2)
+/* @brief SIM availability on the SoC. */
+#define FSL_FEATURE_SOC_SIM_COUNT (1)
+/* @brief SMC availability on the SoC. */
+#define FSL_FEATURE_SOC_SMC_COUNT (2)
+/* @brief SPM availability on the SoC. */
+#define FSL_FEATURE_SOC_SPM_COUNT (1)
+/* @brief TPM availability on the SoC. */
+#define FSL_FEATURE_SOC_TPM_COUNT (4)
+/* @brief TRGMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_TRGMUX_COUNT (2)
+/* @brief TRNG availability on the SoC. */
+#define FSL_FEATURE_SOC_TRNG_COUNT (1)
+/* @brief TSTMR availability on the SoC. */
+#define FSL_FEATURE_SOC_TSTMR_COUNT (1)
+/* @brief USB availability on the SoC. */
+#define FSL_FEATURE_SOC_USB_COUNT (1)
+/* @brief USBVREG availability on the SoC. */
+#define FSL_FEATURE_SOC_USBVREG_COUNT (1)
+/* @brief USDHC availability on the SoC. */
+#define FSL_FEATURE_SOC_USDHC_COUNT (1)
+/* @brief VREF availability on the SoC. */
+#define FSL_FEATURE_SOC_VREF_COUNT (1)
+/* @brief WDOG availability on the SoC. */
+#define FSL_FEATURE_SOC_WDOG_COUNT (2)
+/* @brief XRDC availability on the SoC. */
+#define FSL_FEATURE_SOC_XRDC_COUNT (1)
+/* @brief ZLL availability on the SoC. */
+#define FSL_FEATURE_SOC_ZLL_COUNT (1)
+
+/* LPADC module features */
+
+/* @brief Has differential mode (bitfield CMDLn[DIFF]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0)
+/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0)
+/* @brief Has internal clock (bitfield CFG[ADCKEN]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (1)
+/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (1)
+/* @brief Has calibration (bitfield CFG[CALOFS]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (1)
+/* @brief Has offset trim (register OFSTRIM). */
+#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
+
+/* CRC module features */
+
+/* @brief Has data register with name CRC */
+#define FSL_FEATURE_CRC_HAS_CRC_REG (0)
+
+/* EDMA module features */
+
+/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_MODULE_CHANNEL (8)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (8)
+/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
+/* @brief Has DMA_Error interrupt vector. */
+#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0)
+/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (8)
+
+/* DMAMUX module features */
+
+/* @brief Number of DMA channels (related to number of register CHCFGn). */
+#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (8)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 8)
+/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
+#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
+/* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */
+#define FSL_FEATURE_DMAMUX_HAS_A_ON (1)
+
+/* EWM module features */
+
+/* @brief Has clock select (register CLKCTRL). */
+#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT  (0)
+/* @brief Has clock prescaler (register CLKPRESCALER). */
+#define FSL_FEATURE_EWM_HAS_PRESCALER  (1)
+
+/* FB module features */
+
+/* No feature definitions */
+
+/* FLEXIO module features */
+
+/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
+#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
+/* @brief Has Pin Data Input Register (FLEXIO_PIN) */
+#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1)
+/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
+#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1)
+/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
+#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1)
+/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */
+#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1)
+/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */
+#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1)
+/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */
+#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1)
+/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */
+#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1)
+/* @brief Reset value of the FLEXIO_VERID register */
+#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001)
+/* @brief Reset value of the FLEXIO_PARAM register */
+#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200808)
+
+/* FLASH module features */
+
+/* @brief Current core ID. */
+#define FSL_FEATURE_FLASH_CURRENT_CORE_ID (1)
+/* @brief Is of type FTFA. */
+#define FSL_FEATURE_FLASH_IS_FTFA (0)
+/* @brief Is of type FTFE. */
+#define FSL_FEATURE_FLASH_IS_FTFE (1)
+/* @brief Is of type FTFL. */
+#define FSL_FEATURE_FLASH_IS_FTFL (0)
+/* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+#define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
+/* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+#define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
+/* @brief Has EEPROM region protection (register FEPROT). */
+#define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
+/* @brief Has data flash region protection (register FDPROT). */
+#define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
+/* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+#define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1)
+/* @brief Has flash cache control in FMC module. */
+#define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
+/* @brief Has flash cache control in MCM module. */
+#define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
+/* @brief Has flash cache control in MSCM module. */
+#define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (1)
+/* @brief Has prefetch speculation control in flash, such as kv5x. */
+#define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
+/* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for RV32M1 */
+#define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (1)
+/* @brief P-Flash start address. */
+#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x01000000)
+/* @brief P-Flash block count. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
+/* @brief P-Flash block size. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144)
+/* @brief P-Flash sector size. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048)
+/* @brief P-Flash write unit size. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
+/* @brief P-Flash data path width. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8)
+/* @brief P-Flash block swap feature. */
+#define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
+/* @brief P-Flash protection region count. */
+#define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (16)
+/* @brief Has multiple flash. */
+#define FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH (1)
+/* @brief Flash memory count. */
+#define FSL_FEATURE_FLASH_MEMORY_COUNT (2)
+/* @brief P-Flash start address. */
+#define FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS (0x00000000)
+/* @brief P-Flash block count. */
+#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT (2)
+/* @brief P-Flash block size. */
+#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE (524288)
+/* @brief P-Flash sector size. */
+#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE (4096)
+/* @brief P-Flash write unit size. */
+#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE (8)
+/* @brief P-Flash data path width. */
+#define FSL_FEATURE_FLASH_PFLASH_1_BLOCK_DATA_PATH_WIDTH (16)
+/* @brief P-Flash protection region count. */
+#define FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT (64)
+/* @brief P-Flash block swap feature. */
+#define FSL_FEATURE_FLASH_HAS_1_PFLASH_BLOCK_SWAP (1)
+/* @brief Has FlexNVM memory. */
+#define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
+/* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+#define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
+/* @brief FlexNVM block count. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
+/* @brief FlexNVM block size. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
+/* @brief FlexNVM sector size. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
+/* @brief FlexNVM write unit size. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
+/* @brief FlexNVM data path width. */
+#define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
+/* @brief Has FlexRAM memory. */
+#define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
+/* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+#define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x48000000)
+/* @brief FlexRAM size. */
+#define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
+/* @brief Has 0x00 Read 1s Block command. */
+#define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
+/* @brief Flash 1 has 0x00 Read 1s Block command. */
+#define FSL_FEATURE_FLASH_HAS_1_READ_1S_BLOCK_CMD (1)
+/* @brief Has 0x01 Read 1s Section command. */
+#define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+/* @brief Has 0x02 Program Check command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+/* @brief Has 0x03 Read Resource command. */
+#define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (0)
+/* @brief Has 0x06 Program Longword command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
+/* @brief Has 0x07 Program Phrase command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
+/* @brief Has 0x08 Erase Flash Block command. */
+#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
+/* @brief Flash 1 has 0x08 Erase Flash Block command. */
+#define FSL_FEATURE_FLASH_HAS_1_ERASE_FLASH_BLOCK_CMD (1)
+/* @brief Has 0x09 Erase Flash Sector command. */
+#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+/* @brief Has 0x0B Program Section command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
+/* @brief Has 0x0C Generate CRC signature for selected program flash sectors. */
+#define FSL_FEATURE_FLASH_HAS_GENERATE_CRC_CMD (1)
+/* @brief Has 0x40 Read 1s All Blocks command. */
+#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
+/* @brief Has 0x41 Read Once command. */
+#define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+/* @brief Has 0x43 Program Once command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+/* @brief Has 0x44 Erase All Blocks command. */
+#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
+/* @brief Has 0x45 Verify Backdoor Access Key command. */
+#define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+/* @brief Has 0x46 Swap Control command. */
+#define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
+/* @brief Flash 1 has 0x46 Swap Control command. */
+#define FSL_FEATURE_FLASH_HAS_1_SWAP_CONTROL_CMD (1)
+/* @brief Has 0x49 Erase All Blocks Unsecure command. */
+#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1)
+/* @brief Has 0x4A Read 1s All Execute-only Segments command. */
+#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
+/* @brief Has 0x4B Erase All Execute-only Segments command. */
+#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
+/* @brief Has 0x80 Program Partition command. */
+#define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
+/* @brief Has 0x81 Set FlexRAM Function command. */
+#define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
+/* @brief P-Flash Erase/Read 1st all block command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
+/* @brief P-Flash Erase sector command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8)
+/* @brief P-Flash Erase sector command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT (16)
+/* @brief P-Flash Program/Verify section command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8)
+/* @brief P-Flash Program/Verify section command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT (16)
+/* @brief P-Flash Read resource command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
+/* @brief P-Flash Program check command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+/* @brief P-Flash Program check command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
+/* @brief P-Flash 1 Program check command address alignment. */
+#define FSL_FEATURE_FLASH_PFLASH_1_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16)
+/* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
+/* @brief FlexNVM Erase sector command address alignment. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
+/* @brief FlexNVM Rrogram/Verify section command address alignment. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
+/* @brief FlexNVM Read resource command address alignment. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
+/* @brief FlexNVM Program check command address alignment. */
+#define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
+/* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+/* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
+/* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+/* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+/* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
+/* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
+/* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
+/* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
+/* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
+/* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
+/* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
+/* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
+/* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+/* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+/* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+/* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+/* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+/* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
+
+/* GPIO module features */
+
+/* @brief Has fast (single cycle) access capability via a dedicated memory region. */
+#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1)
+/* @brief Has port input disable register (PIDR). */
+#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1)
+
+/* SAI module features */
+
+/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
+#define FSL_FEATURE_SAI_FIFO_COUNT (8)
+/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
+#define FSL_FEATURE_SAI_CHANNEL_COUNT (2)
+/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
+#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
+/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1)
+/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1)
+/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1)
+/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
+#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1)
+/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
+#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
+/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
+#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0)
+/* @brief Interrupt source number */
+#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1)
+/* @brief Has register of MCR. */
+#define FSL_FEATURE_SAI_HAS_MCR (0)
+/* @brief Has bit field MICS of the MCR register. */
+#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1)
+/* @brief Has register of MDR */
+#define FSL_FEATURE_SAI_HAS_MDR (0)
+/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */
+#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0)
+
+/* INTMUX module features */
+
+/* @brief Number of INTMUX channels (related to number of register CHn_CSR). */
+#define FSL_FEATURE_INTMUX_CHANNEL_COUNT (8)
+/* @brief Number of INTMUX IRQ source. */
+#define FSL_FEATURE_INTMUX_IRQ_COUNT (32)
+/* @brief The start IRQ index of first INTMUX source IRQ. */
+#define FSL_FEATURE_INTMUX_IRQ_START_INDEX (32)
+/* @brief The direction of INTMUX. OUT, route the CM4 subsystem IRQ to System. */
+#define FSL_FEATURE_INTMUX_DIRECTION_OUT (0)
+/* @brief The total number of level1 interrupt vectors. */
+#define FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS (32)
+
+/* LLWU module features */
+
+/* @brief Maximum number of pins connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (32)
+/* @brief Maximum number of internal modules connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
+/* @brief Number of digital filters. */
+#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
+/* @brief Has MF register. */
+#define FSL_FEATURE_LLWU_HAS_MF (0)
+/* @brief Has PF register. */
+#define FSL_FEATURE_LLWU_HAS_PF (1)
+/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
+#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
+/* @brief Has no internal module wakeup flag register. */
+#define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (1)
+/* @brief Has external pin 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
+/* @brief Has external pin 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
+/* @brief Has external pin 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (22)
+/* @brief Has external pin 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (30)
+/* @brief Has external pin 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (1)
+/* @brief Has external pin 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (2)
+/* @brief Has external pin 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (4)
+/* @brief Has external pin 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (6)
+/* @brief Has external pin 8 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (7)
+/* @brief Has external pin 9 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (8)
+/* @brief Has external pin 10 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (16)
+/* @brief Has external pin 11 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (20)
+/* @brief Has external pin 12 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (22)
+/* @brief Has external pin 13 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (25)
+/* @brief Has external pin 14 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (28)
+/* @brief Has external pin 15 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7)
+/* @brief Has external pin 16 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (9)
+/* @brief Has external pin 17 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (11)
+/* @brief Has external pin 18 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (12)
+/* @brief Has external pin 19 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (8)
+/* @brief Has external pin 20 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (10)
+/* @brief Has external pin 21 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (1)
+/* @brief Has external pin 22 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (3)
+/* @brief Has external pin 23 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (8)
+/* @brief Has external pin 24 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (9)
+/* @brief Has external pin 25 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (10)
+/* @brief Has external pin 26 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (12)
+/* @brief Has external pin 27 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
+/* @brief Has external pin 28 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
+/* @brief Has external pin 29 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
+/* @brief Has external pin 30 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
+/* @brief Has external pin 31 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
+/* @brief Has internal module 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
+/* @brief Has internal module 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
+/* @brief Has internal module 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
+/* @brief Has internal module 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
+/* @brief Has internal module 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
+/* @brief Has internal module 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
+/* @brief Has internal module 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (1)
+/* @brief Has internal module 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
+/* @brief Has LLWU_VERID. */
+#define FSL_FEATURE_LLWU_HAS_VERID (1)
+/* @brief Has LLWU_PARAM. */
+#define FSL_FEATURE_LLWU_HAS_PARAM (1)
+/* @brief LLWU register bit width. */
+#define FSL_FEATURE_LLWU_REG_BITWIDTH (32)
+/* @brief Has DMA Enable register LLWU_DE. */
+#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (1)
+
+/* LPDAC module features */
+
+/* @brief FIFO size. */
+#define FSL_FEATURE_LPDAC_FIFO_SIZE (16)
+
+/* LPI2C module features */
+
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4)
+
+/* LPIT module features */
+
+/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
+#define FSL_FEATURE_LPIT_TIMER_COUNT (4)
+/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
+#define FSL_FEATURE_LPIT_HAS_LIFETIME_TIMER (0)
+/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
+#define FSL_FEATURE_LPIT_HAS_CHAIN_MODE (0)
+/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
+#define FSL_FEATURE_LPIT_HAS_SHARED_IRQ_HANDLER (0)
+
+/* LPSPI module features */
+
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+
+/* LPTMR module features */
+
+/* @brief Has shared interrupt handler with another LPTMR module. */
+#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
+/* @brief Whether LPTMR counter is 32 bits width. */
+#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1)
+/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
+#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1)
+
+/* LPUART module features */
+
+/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
+#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
+/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
+/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPUART_HAS_FIFO (1)
+/* @brief Has 32-bit register MODIR */
+#define FSL_FEATURE_LPUART_HAS_MODIR (1)
+/* @brief Hardware flow control (RTS, CTS) is supported. */
+#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
+/* @brief Infrared (modulation) is supported. */
+#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
+/* @brief 2 bits long stop bit is available. */
+#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
+/* @brief If 10-bit mode is supported. */
+#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
+/* @brief If 7-bit mode is supported. */
+#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1)
+/* @brief Baud rate fine adjustment is available. */
+#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
+/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
+/* @brief Peripheral type. */
+#define FSL_FEATURE_LPUART_IS_SCI (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8)
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
+/* @brief Maximal data width with parity bit. */
+#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
+/* @brief Supports two match addresses to filter incoming frames. */
+#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
+/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
+/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
+#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
+/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
+#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
+/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
+#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
+/* @brief Has improved smart card (ISO7816 protocol) support. */
+#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
+/* @brief Has local operation network (CEA709.1-B protocol) support. */
+#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
+/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
+#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
+/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
+#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
+/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
+#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+/* @brief Has separate RX and TX interrupts. */
+#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
+/* @brief Has LPAURT_PARAM. */
+#define FSL_FEATURE_LPUART_HAS_PARAM (1)
+/* @brief Has LPUART_VERID. */
+#define FSL_FEATURE_LPUART_HAS_VERID (1)
+/* @brief Has LPUART_GLOBAL. */
+#define FSL_FEATURE_LPUART_HAS_GLOBAL (1)
+/* @brief Has LPUART_PINCFG. */
+#define FSL_FEATURE_LPUART_HAS_PINCFG (1)
+
+/* MCM module features */
+
+/* @brief Has L1 cache. */
+#define FSL_FEATURE_HAS_L1CACHE (1)
+
+/* MSCM module features */
+
+/* @brief Number of configuration information for processors. */
+#define FSL_FEATURE_MSCM_HAS_CP_COUNT (2)
+/* @brief Has data cache. */
+#define FSL_FEATURE_MSCM_HAS_DATACACHE (0)
+
+/* MU module features */
+
+/* @brief MU side for current core */
+#define FSL_FEATURE_MU_SIDE_B (1)
+/* @brief MU Has register CCR */
+#define FSL_FEATURE_MU_HAS_CCR (1)
+/* @brief MU Has register SR[RS], BSR[ARS] */
+#define FSL_FEATURE_MU_HAS_SR_RS (0)
+/* @brief MU Has register CR[RDIE], CR[RAIE], SR[RDIP], SR[RAIP] */
+#define FSL_FEATURE_MU_HAS_RESET_INT (1)
+/* @brief MU Has register SR[MURIP] */
+#define FSL_FEATURE_MU_HAS_SR_MURIP (1)
+/* @brief brief MU Has register SR[HRIP] */
+#define FSL_FEATURE_MU_HAS_SR_HRIP (1)
+/* @brief brief MU does not support enable clock of the other core, CR[CLKE] or CCR[CLKE]. */
+#define FSL_FEATURE_MU_NO_CLKE (0)
+/* @brief brief MU does not support NMI, CR[NMI]. */
+#define FSL_FEATURE_MU_NO_NMI (0)
+/* @brief brief MU does not support hold the other core reset. CR[RSTH] or CCR[RSTH]. */
+#define FSL_FEATURE_MU_NO_RSTH (0)
+/* @brief brief MU does not supports MU reset, CR[MUR]. */
+#define FSL_FEATURE_MU_NO_MUR (0)
+/* @brief brief MU does not supports hardware reset, CR[HR] or CCR[HR]. */
+#define FSL_FEATURE_MU_NO_HR (0)
+/* @brief brief MU supports mask the hardware reset. CR[HRM] or CCR[HRM]. */
+#define FSL_FEATURE_MU_HAS_HRM (1)
+
+/* interrupt module features */
+
+/* @brief Lowest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
+/* @brief Highest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31)
+
+/* PCC module features */
+
+/* @brief Has CLOCK GATE CONTROL bit (e.g PCC_CGC) */
+#define FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL (1)
+
+/* PORT module features */
+
+/* @brief Has control lock (register bit PCR[LK]). */
+#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
+/* @brief Has open drain control (register bit PCR[ODE]). */
+#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
+/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
+#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
+/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */
+#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
+/* @brief Has pull resistor selection available. */
+#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
+/* @brief Has pull resistor enable (register bit PCR[PE]). */
+#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
+/* @brief Has slew rate control (register bit PCR[SRE]). */
+#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
+/* @brief Has passive filter (register bit field PCR[PFE]). */
+#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
+/* @brief Has drive strength control (register bit PCR[DSE]). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
+/* @brief Defines width of PCR[MUX] field. */
+#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
+/* @brief Has independent interrupt control(register ICR). */
+#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0)
+/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
+#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (1)
+/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (1)
+/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (1)
+
+/* RADIO module features */
+
+/* @brief Zigbee availability. */
+#define FSL_FEATURE_RADIO_HAS_ZIGBEE (1)
+/* @brief Bluetooth availability. */
+#define FSL_FEATURE_RADIO_HAS_BLE (1)
+/* @brief ANT availability */
+#define FSL_FEATURE_RADIO_HAS_ANT (0)
+/* @brief Generic FSK module availability */
+#define FSL_FEATURE_RADIO_HAS_GENFSK (1)
+/* @brief Major version of the radio submodule */
+#define FSL_FEATURE_RADIO_VERSION_MAJOR (3)
+/* @brief Minor version of the radio submodule */
+#define FSL_FEATURE_RADIO_VERSION_MINOR (0)
+
+/* RTC module features */
+
+/* @brief Has wakeup pin. */
+#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
+/* @brief Has wakeup pin selection (bit field CR[WPS]). */
+#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
+/* @brief Has low power features (registers MER, MCLR and MCHR). */
+#define FSL_FEATURE_RTC_HAS_MONOTONIC (1)
+/* @brief Has read/write access control (registers WAR and RAR). */
+#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
+/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+#define FSL_FEATURE_RTC_HAS_SECURITY (1)
+/* @brief Has RTC_CLKIN available. */
+#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
+/* @brief Has prescaler adjust for LPO. */
+#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1)
+/* @brief Has Clock Pin Enable field. */
+#define FSL_FEATURE_RTC_HAS_CPE (1)
+/* @brief Has Timer Seconds Interrupt Configuration field. */
+#define FSL_FEATURE_RTC_HAS_TSIC (1)
+/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
+#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
+/* @brief Has Tamper Interrupt Register (register TIR). */
+#define FSL_FEATURE_RTC_HAS_TIR (1)
+/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */
+#define FSL_FEATURE_RTC_HAS_TIR_TPIE (1)
+/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */
+#define FSL_FEATURE_RTC_HAS_TIR_SIE (1)
+/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */
+#define FSL_FEATURE_RTC_HAS_TIR_LCIE (1)
+/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */
+#define FSL_FEATURE_RTC_HAS_SR_TIDF (1)
+/* @brief Has Tamper Detect Register (register TDR). */
+#define FSL_FEATURE_RTC_HAS_TDR (1)
+/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */
+#define FSL_FEATURE_RTC_HAS_TDR_TPF (1)
+/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */
+#define FSL_FEATURE_RTC_HAS_TDR_STF (1)
+/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */
+#define FSL_FEATURE_RTC_HAS_TDR_LCTF (1)
+/* @brief Has Tamper Time Seconds Register (register TTSR). */
+#define FSL_FEATURE_RTC_HAS_TTSR (1)
+/* @brief Has Pin Configuration Register (register PCR). */
+#define FSL_FEATURE_RTC_HAS_PCR (1)
+/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */
+#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (0)
+
+/* SCG module features */
+
+/* @brief Has platform clock divider SCG_CSR[DIVPLAT]. */
+#define FSL_FEATURE_SCG_HAS_DIVPLAT (0)
+/* @brief Has bus clock divider SCG_CSR[DIVBUS]. */
+#define FSL_FEATURE_SCG_HAS_DIVBUS (1)
+/* @brief Has external clock divide ratio SCG_CSR[DIVEXT]. */
+#define FSL_FEATURE_SCG_HAS_DIVEXT (1)
+/* @brief Has OSC capacitor setting SOSCCFG[SC2P ~ SC16P]. */
+#define FSL_FEATURE_SCG_HAS_OSC_SCXP (0)
+/* @brief Has SOSCCSR[SOSCERCLKEN]. */
+#define FSL_FEATURE_SCG_HAS_OSC_ERCLK (0)
+/* @brief Has OSC freq range SOSCCFG[RANGE]. */
+#define FSL_FEATURE_SCG_HAS_SOSC_RANGE (0)
+/* @brief Has CLKOUT configure register SCG_CLKOUTCNFG. */
+#define FSL_FEATURE_SCG_HAS_CLKOUTCNFG (1)
+/* @brief Has SCG_SOSCDIV[SOSCDIV3]. */
+#define FSL_FEATURE_SCG_HAS_SOSCDIV3 (1)
+/* @brief Has SCG_SIRCDIV[SIRCDIV3]. */
+#define FSL_FEATURE_SCG_HAS_SIRCDIV3 (1)
+/* @brief Has SCG_SIRCCSR[LPOPO]. */
+#define FSL_FEATURE_SCG_HAS_SIRC_LPOPO (0)
+/* @brief Has SCG_FIRCDIV[FIRCDIV3]. */
+#define FSL_FEATURE_SCG_HAS_FIRCDIV3 (1)
+/* @brief Has SCG_FIRCCSR[FIRCLPEN]. */
+#define FSL_FEATURE_SCG_HAS_FIRCLPEN (1)
+/* @brief Has SCG_FIRCCSR[FIRCREGOFF]. */
+#define FSL_FEATURE_SCG_HAS_FIRCREGOFF (1)
+/* @brief Has SCG_SPLLDIV[SPLLDIV3]. */
+#define FSL_FEATURE_SCG_HAS_SPLLDIV3 (0)
+/* @brief Has SCG_SPLLCFG[PLLPOSTDIV1]. */
+#define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV1 (0)
+/* @brief Has SCG_SPLLCFG[PLLPOSTDIV2]. */
+#define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV2 (0)
+/* @brief Has SCG_SPLLCFG[PLLS]. */
+#define FSL_FEATURE_SCG_HAS_SPLL_PLLS (0)
+/* @brief Has SCG_SPLLCFG[BYPASS]. */
+#define FSL_FEATURE_SCG_HAS_SPLL_BYPASS (0)
+/* @brief Has SCG_SPLLCFG[PFDSEL]. */
+#define FSL_FEATURE_SCG_HAS_SPLL_PFDSEL (0)
+/* @brief Has SCG_SPLLCSR[SPLLCM]. */
+#define FSL_FEATURE_SCG_HAS_SPLL_MONITOR (0)
+/* @brief Has SCG_LPFLLDIV[FLLDIV3]. */
+#define FSL_FEATURE_SCG_HAS_FLLDIV3 (1)
+/* @brief Has low power FLL, SCG_LPFLLCSR. */
+#define FSL_FEATURE_SCG_HAS_LPFLL (1)
+/* @brief Has system PLL, SCG_SPLLCSR. */
+#define FSL_FEATURE_SCG_HAS_SPLL (0)
+/* @brief Has system PLL PFD, SCG_SPLLPFD. */
+#define FSL_FEATURE_SCG_HAS_SPLLPFD (0)
+/* @brief Has auxiliary PLL, SCG_APLLCSR. */
+#define FSL_FEATURE_SCG_HAS_APLL (0)
+/* @brief Has RTC OSC control, SCG_ROSCCSR. */
+#define FSL_FEATURE_SCG_HAS_ROSC (1)
+/* @brief Has RTC OSC clock source. */
+#define FSL_FEATURE_SCG_HAS_ROSC_SYS_CLK_SRC (1)
+/* @brief Has RTC OSC clock out select. */
+#define FSL_FEATURE_SCG_HAS_ROSC_CLKOUT (1)
+/* @brief Has EXTERNAL clock out select. */
+#define FSL_FEATURE_SCG_HAS_EXT_CLKOUT (1)
+/* @brief Has no System OSC configuration register, SCG_SOSCCFG. */
+#define FSL_FEATURE_SCG_HAS_NO_SOSCCFG (1)
+/* @brief Has no SCG_SOSCCSR[SOSCEN]. */
+#define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCEN (0)
+/* @brief Has no SCG_SOSCCSR[SOSCSTEN]. */
+#define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCSTEN (0)
+/* @brief Has no SCG_SOSCCSR[SOSCLPEN]. */
+#define FSL_FEATURE_SCG_HAS_NO_SOSCCSR_SOSCLPEN (0)
+/* @brief Has no FIRC trim configuration register, SCG_FIRCTCFG. */
+#define FSL_FEATURE_SCG_HAS_NO_FIRCTCFG (0)
+/* @brief Has FIRC trim source USB0 Start of Frame. */
+#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB0 (0)
+/* @brief Has FIRC trim source USB1 Start of Frame. */
+#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB1 (0)
+/* @brief Has FIRC trim source system OSC. */
+#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_SOSC (1)
+/* @brief Has FIRC trim source RTC OSC. */
+#define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_RTCOSC (1)
+
+/* SEMA42 module features */
+
+/* @brief Gate counts */
+#define FSL_FEATURE_SEMA42_GATE_COUNT (16)
+
+/* SIM module features */
+
+/* @brief Has USB FS divider. */
+#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
+#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
+/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0)
+/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
+/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (0)
+/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (0)
+/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0)
+/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
+/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
+/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
+/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
+/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
+/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
+/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
+#define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
+/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
+#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
+/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
+#define FSL_FEATURE_SIM_OPT_UART_COUNT (0)
+/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
+/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
+/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
+/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
+/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
+/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
+/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
+/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
+/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
+/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
+/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0)
+/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0)
+/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0)
+/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0)
+/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0)
+/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0)
+/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0)
+/* @brief Has FTM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
+/* @brief Number of FTM modules. */
+#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
+/* @brief Number of FTM triggers with selectable source. */
+#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
+/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
+/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
+/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
+/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
+/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
+/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
+/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
+/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
+/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
+/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
+/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
+/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
+/* @brief Has TPM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
+/* @brief The highest TPM module index. */
+#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
+/* @brief Has TPM module with index 0. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
+/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
+/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
+/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
+/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
+/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
+/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
+/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
+/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0)
+/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0)
+/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
+/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
+/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
+/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
+/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
+/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
+/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0)
+/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
+/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
+/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
+/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
+/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
+/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
+/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
+/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
+/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
+/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_ADC_COUNT (0)
+/* @brief ADC module has alternate trigger (register bit SOPT7[ADC0ALTTRGEN]). */
+#define FSL_FEATURE_SIM_OPT_ADC_HAS_ALTERNATE_TRIGGER (0)
+/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (0)
+/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0)
+/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
+/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
+/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
+/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
+/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
+/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
+/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
+/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
+#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
+/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0)
+/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
+/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (0)
+/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (0)
+/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
+/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
+/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
+/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
+/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
+/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
+/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
+/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
+/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
+/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
+/* @brief Has device die ID (register bit field SDID[DIEID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
+/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
+/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
+/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
+/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
+/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
+/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
+/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
+/* @brief Has flash for core0(CM4) (register bit field FCFG1[CORE0_PFSIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_CORE0_PFSIZE (1)
+/* @brief Has flash for core1(CM0) (register bit field FCFG1[CORE1_PFSIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_CORE1_PFSIZE (1)
+/* @brief Has sram for core0(CM4) (register bit field FCFG1[CORE0_SRAMSIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_CORE0_SRAMSIZE (1)
+/* @brief Has sram for core1(CM0) (register bit field FCFG1[CORE1_SRAMSIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_CORE1_SRAMSIZE (1)
+/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (0)
+/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0)
+/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (1)
+/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
+/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
+/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
+/* @brief Has miscellanious control register (register MCR). */
+#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
+/* @brief Has COP watchdog (registers COPC and SRVCOP). */
+#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
+/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
+#define FSL_FEATURE_SIM_HAS_COP_STOP (0)
+/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
+#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
+/* @brief Has MISCCTRL reg. */
+#define FSL_FEATURE_SIM_HAS_MISCCTRL (0)
+/* @brief Has LTCEN bit (e.g SIM_MISCCTRL). */
+#define FSL_FEATURE_SIM_HAS_MISCCTRL_LTCEN (0)
+/* @brief Has DMAINTSEL0 bit (e.g SIM_MISCCTRL). */
+#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL0 (0)
+/* @brief Has DMAINTSEL1 bit (e.g SIM_MISCCTRL). */
+#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL1 (0)
+/* @brief Has DMAINTSEL2 bit (e.g SIM_MISCCTRL). */
+#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL2 (0)
+/* @brief Has DMAINTSEL3 bit (e.g SIM_MISCCTRL). */
+#define FSL_FEATURE_SIM_HAS_MISCCTRL_DMAINTSEL3 (0)
+/* @brief Has SECKEY0 reg. */
+#define FSL_FEATURE_SIM_HAS_SECKEY0 (0)
+/* @brief Has SECKEY bit (e.g SIM_SECKEY0). */
+#define FSL_FEATURE_SIM_HAS_SECKEY0_SECKEY (0)
+/* @brief Has SECKEY1 reg. */
+#define FSL_FEATURE_SIM_HAS_SECKEY1 (0)
+/* @brief Has SECKEY bit (e.g SIM_SECKEY1). */
+#define FSL_FEATURE_SIM_HAS_SECKEY1_SECKEY (0)
+/* @brief Has SECKEY2 reg. */
+#define FSL_FEATURE_SIM_HAS_SECKEY2 (0)
+/* @brief Has SECKEY bit (e.g SIM_SECKEY2). */
+#define FSL_FEATURE_SIM_HAS_SECKEY2_SECKEY (0)
+/* @brief Has SECKEY3 reg. */
+#define FSL_FEATURE_SIM_HAS_SECKEY3 (0)
+/* @brief Has SECKEY bit (e.g SIM_SECKEY3). */
+#define FSL_FEATURE_SIM_HAS_SECKEY3_SECKEY (0)
+/* @brief Has no SDID reg. */
+#define FSL_FEATURE_SIM_HAS_NO_SDID (0)
+/* @brief Has no UID reg. */
+#define FSL_FEATURE_SIM_HAS_NO_UID (0)
+/* @brief Has RFADDRL and RFADDRH registers. */
+#define FSL_FEATURE_SIM_HAS_RF_MAC_ADDR (1)
+/* @brief Has SYSTICK_CLK_EN bit in SIM_MISC2 register. */
+#define FSL_FEATURE_SIM_MISC2_HAS_SYSTICK_CLK_EN (1)
+/* @brief Has UIDM registers. */
+#define FSL_FEATURE_SIM_HAS_UIDM (1)
+
+/* SMC module features */
+
+/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
+#define FSL_FEATURE_SMC_HAS_PSTOPO (0)
+/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
+#define FSL_FEATURE_SMC_HAS_LPOPO (0)
+/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
+#define FSL_FEATURE_SMC_HAS_PORPO (0)
+/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
+#define FSL_FEATURE_SMC_HAS_LPWUI (0)
+/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
+#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
+/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
+#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
+/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
+/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
+/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
+#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1)
+/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
+#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
+/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
+#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
+/* @brief Has stop submode. */
+#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
+/* @brief Has stop submode 0(VLLS0). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
+/* @brief Has stop submode 2(VLLS2). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
+/* @brief Has SMC_PARAM. */
+#define FSL_FEATURE_SMC_HAS_PARAM (1)
+/* @brief Has SMC_VERID. */
+#define FSL_FEATURE_SMC_HAS_VERID (1)
+/* @brief Has SMC_CSRE. */
+#define FSL_FEATURE_SMC_HAS_CSRE (0)
+/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */
+#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (0)
+/* @brief Has tamper reset (register bit SRS[TAMPER]). */
+#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0)
+/* @brief Has security violation reset (register bit SRS[SECVIO]). */
+#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0)
+/* @brief Has security violation reset (register bit SRS[VBAT]). */
+#define FSL_FEATURE_SMC_HAS_SRS_VBAT (0)
+/* @brief Has security violation reset (register bit SRS[CORE0]). */
+#define FSL_FEATURE_SMC_HAS_SRS_CORE0 (1)
+/* @brief Has security violation reset (register bit SRS[CORE1]). */
+#define FSL_FEATURE_SMC_HAS_SRS_CORE1 (1)
+/* @brief Has security violation reset (register bit SRIE[VBAT]). */
+#define FSL_FEATURE_SMC_HAS_SRIE_VBAT (0)
+/* @brief Has security violation reset (register bit SRIE[CORE0]). */
+#define FSL_FEATURE_SMC_HAS_SRIE_CORE0 (1)
+/* @brief Has security violation reset (register bit SRIE[CORE1]). */
+#define FSL_FEATURE_SMC_HAS_SRIE_CORE1 (1)
+
+/* SysTick module features */
+
+/* @brief Systick has external reference clock. */
+#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1)
+/* @brief Systick external reference clock is core clock divided by this value. */
+#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16)
+
+/* TPM module features */
+
+/* @brief Number of channels. */
+#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \
+    ((x) == TPM0 ? (6) : \
+    ((x) == TPM1 ? (2) : \
+    ((x) == TPM2 ? (6) : \
+    ((x) == TPM3 ? (2) : (-1)))))
+/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
+#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
+/* @brief Has TPM_PARAM. */
+#define FSL_FEATURE_TPM_HAS_PARAM (1)
+/* @brief Has TPM_VERID. */
+#define FSL_FEATURE_TPM_HAS_VERID (1)
+/* @brief Has TPM_GLOBAL. */
+#define FSL_FEATURE_TPM_HAS_GLOBAL (1)
+/* @brief Has TPM_TRIG. */
+#define FSL_FEATURE_TPM_HAS_TRIG (1)
+/* @brief Has counter pause on trigger. */
+#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
+/* @brief Has external trigger selection. */
+#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1)
+/* @brief Has TPM_COMBINE register. */
+#define FSL_FEATURE_TPM_HAS_COMBINE (1)
+/* @brief Whether COMBINE register has effect. */
+#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1)
+/* @brief Has TPM_POL. */
+#define FSL_FEATURE_TPM_HAS_POL (1)
+/* @brief Has TPM_FILTER register. */
+#define FSL_FEATURE_TPM_HAS_FILTER (1)
+/* @brief Whether FILTER register has effect. */
+#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1)
+/* @brief Has TPM_QDCTRL register. */
+#define FSL_FEATURE_TPM_HAS_QDCTRL (1)
+/* @brief Whether QDCTRL register has effect. */
+#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1)
+
+/* TRGMUX module features */
+
+/* No feature definitions */
+
+/* TRNG module features */
+
+/* No feature definitions */
+
+/* TSTMR module features */
+
+/* @brief TSTMR clock frequency is 1MHZ. */
+#define FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_1MHZ (1)
+
+/* USB module features */
+
+/* @brief KHCI module instance count */
+#define FSL_FEATURE_USB_KHCI_COUNT (1)
+/* @brief HOST mode enabled */
+#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (0)
+/* @brief OTG mode enabled */
+#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (0)
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USB_KHCI_USB_RAM (2048)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS (1208025088)
+/* @brief Has KEEP_ALIVE_CTRL register */
+#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (1)
+/* @brief Mode control of the USB Keep Alive */
+#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_MODE_CONTROL (USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK)
+/* @brief Has the Dynamic SOF threshold compare support */
+#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1)
+/* @brief Has the VBUS detect support */
+#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (1)
+/* @brief Has the IRC48M module clock support */
+#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
+/* @brief Number of endpoints supported */
+#define FSL_FEATURE_USB_ENDPT_COUNT (16)
+/* @brief Has STALL_IL/OL_DIS registers */
+#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (1)
+/* @brief Has STALL_IH/OH_DIS registers */
+#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (1)
+
+/* USDHC module features */
+
+/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */
+#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0)
+/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */
+#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0)
+/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */
+#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (0)
+/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */
+#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (0)
+
+/* VREF module features */
+
+/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
+#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
+/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
+#define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
+/* @brief If high/low buffer mode supported */
+#define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
+/* @brief Module has also low reference (registers VREFL/VREFH) */
+#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
+/* @brief Has VREF_TRM4. */
+#define FSL_FEATURE_VREF_HAS_TRM4 (1)
+
+/* WDOG module features */
+
+/* @brief Watchdog is available. */
+#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
+/* @brief WDOG_CNT can be 32-bit written. */
+#define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1)
+
+/* XRDC module features */
+
+/* @brief Does not have global valid (register bit CR[GVLD]). */
+#define FSL_FEATURE_XRDC_HAS_NO_CR_GVLD (1)
+/* @brief Has domain ID of faulted access (register bit FDID[FDID]). */
+#define FSL_FEATURE_XRDC_HAS_FDID (1)
+/* @brief Has special 4-state model option (register bit PID[SP4SM]). */
+#define FSL_FEATURE_XRDC_PID_SP4SM (1)
+/* @brief Does not have logical partition identifier (register bit MDA_W[LPID]). */
+#define FSL_FEATURE_XRDC_NO_MDA_LPID (1)
+/* @brief Does not have logical partition enable option (register bit MDA_W[LPE]). */
+#define FSL_FEATURE_XRDC_NO_MDA_LPE (1)
+/* @brief Does not have peripheral semaphore enable option (register bit PDAC_W0[SE]). */
+#define FSL_FEATURE_XRDC_NO_PDAC_SE (1)
+/* @brief Does not have peripheral semaphore number (register bit PDAC_W0[SNUM]). */
+#define FSL_FEATURE_XRDC_NO_PDAC_SNUM (1)
+/* @brief Has peripheral excessive access lock owner (register bit PDAC_W0[EALO]). */
+#define FSL_FEATURE_XRDC_HAS_PDAC_EALO (1)
+/* @brief Has peripheral excessive access lock option (register bit PDAC_W1[EAL]). */
+#define FSL_FEATURE_XRDC_HAS_PDAC_EAL (1)
+/* @brief Has memory region end address (register bit MRGD_W1[ENDADDR]). */
+#define FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR (1)
+/* @brief Does not have memory region semaphore enable option (register bit MRGD_W2[SE]). */
+#define FSL_FEATURE_XRDC_NO_MRGD_SE (1)
+/* @brief Does not have memory region semaphore number (register bit MRGD_W2[SNUM]). */
+#define FSL_FEATURE_XRDC_NO_MRGD_SNUM (1)
+/* @brief Does not domain x access control policy option (register bit MRGD_W2[DxACP]). */
+#define FSL_FEATURE_XRDC_NO_MRGD_DXACP (1)
+/* @brief Does not have region size configuration (register bit MRGD_W2[SZ]). */
+#define FSL_FEATURE_XRDC_NO_MRGD_SZ (1)
+/* @brief Does not have subregion disable option (register bit MRGD_W2[SRD]). */
+#define FSL_FEATURE_XRDC_NO_MRGD_SRD (1)
+/* @brief Has memory region excessive access lock owner (register bit MRGD_W2[EALO]). */
+#define FSL_FEATURE_XRDC_HAS_MRGD_EALO (1)
+/* @brief Has domain x access policy select option (register bit MRGD_W2[DxSEL]). */
+#define FSL_FEATURE_XRDC_HAS_MRGD_DXSEL (1)
+/* @brief Has memory region excessive access lock option (register bit MRGD_W3[EAL]). */
+#define FSL_FEATURE_XRDC_HAS_MRGD_EAL (1)
+/* @brief Does not have lock option in MRGD_W3 register (register bit MRGD_W3[LK2]). */
+#define FSL_FEATURE_XRDC_NO_MRGD_W3_LK2 (1)
+/* @brief Does not have valid option in MRGD_W3 register (register bit MRGD_W3[VLD]). */
+#define FSL_FEATURE_XRDC_NO_MRGD_W3_VLD (1)
+/* @brief Has code region indicator select option (register bit MRGD_W3[CR]). */
+#define FSL_FEATURE_XRDC_HAS_MRGD_CR (1)
+/* @brief Has ASSSET lock option (register bit MRGD_W4[LKAS1]/[LKAS2]). */
+#define FSL_FEATURE_XRDC_HAS_MRGD_LKAS (1)
+/* @brief Has programmable access flags (register bit MRGD_W4[ACCSET1]/[ACCSET2]). */
+#define FSL_FEATURE_XRDC_HAS_MRGD_ACCSET (1)
+/* @brief Has lock option in MRGD_W4 register (register bit MRGD_W4[LK2]). */
+#define FSL_FEATURE_XRDC_HAS_MRGD_W4_LK2 (1)
+/* @brief Has valid option in MRGD_W4 register (register bit MRGD_W4[VLD]). */
+#define FSL_FEATURE_XRDC_HAS_MRGD_W4_VLD (1)
+/* @brief XRDC domain number (reset value of HWCFG0[NDID] plus 1). */
+#define FSL_FEATURE_XRDC_DOMAIN_COUNT (3)
+
+#endif /* _RV32M1_zero_riscy_FEATURES_H_ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_clock.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_clock.c
new file mode 100644
index 0000000..8cd4fcf
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_clock.c
@@ -0,0 +1,794 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright (c) 2016 - 2017 , NXP
+ * All rights reserved.
+ *
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define SCG_SIRC_LOW_RANGE_FREQ 2000000U  /* Slow IRC low range clock frequency. */
+#define SCG_SIRC_HIGH_RANGE_FREQ 8000000U /* Slow IRC high range clock frequency.   */
+
+#define SCG_FIRC_FREQ0 48000000U /* Fast IRC trimed clock frequency(48MHz). */
+#define SCG_FIRC_FREQ1 52000000U /* Fast IRC trimed clock frequency(52MHz). */
+#define SCG_FIRC_FREQ2 56000000U /* Fast IRC trimed clock frequency(56MHz). */
+#define SCG_FIRC_FREQ3 60000000U /* Fast IRC trimed clock frequency(60MHz). */
+
+#define SCG_LPFLL_FREQ0 48000000U  /* LPFLL trimed clock frequency(48MHz). */
+#define SCG_LPFLL_FREQ1 72000000U  /* LPFLL trimed clock frequency(72MHz). */
+#define SCG_LPFLL_FREQ2 96000000U  /* LPFLL trimed clock frequency(96MHz). */
+#define SCG_LPFLL_FREQ3 120000000U /* LPFLL trimed clock frequency(120MHz). */
+
+#define SCG_CSR_SCS_VAL ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT)
+#define SCG_SOSCDIV_SOSCDIV1_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV1_MASK) >> SCG_SOSCDIV_SOSCDIV1_SHIFT)
+#define SCG_SOSCDIV_SOSCDIV2_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV2_MASK) >> SCG_SOSCDIV_SOSCDIV2_SHIFT)
+#define SCG_SOSCDIV_SOSCDIV3_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV3_MASK) >> SCG_SOSCDIV_SOSCDIV3_SHIFT)
+#define SCG_SIRCDIV_SIRCDIV1_VAL ((SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV1_MASK) >> SCG_SIRCDIV_SIRCDIV1_SHIFT)
+#define SCG_SIRCDIV_SIRCDIV2_VAL ((SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV2_MASK) >> SCG_SIRCDIV_SIRCDIV2_SHIFT)
+#define SCG_SIRCDIV_SIRCDIV3_VAL ((SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV3_MASK) >> SCG_SIRCDIV_SIRCDIV3_SHIFT)
+#define SCG_FIRCDIV_FIRCDIV1_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV1_MASK) >> SCG_FIRCDIV_FIRCDIV1_SHIFT)
+#define SCG_FIRCDIV_FIRCDIV2_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV2_MASK) >> SCG_FIRCDIV_FIRCDIV2_SHIFT)
+#define SCG_FIRCDIV_FIRCDIV3_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV3_MASK) >> SCG_FIRCDIV_FIRCDIV3_SHIFT)
+
+#define SCG_LPFLLDIV_LPFLLDIV1_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV1_MASK) >> SCG_LPFLLDIV_LPFLLDIV1_SHIFT)
+#define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_LPFLLDIV2_SHIFT)
+#define SCG_LPFLLDIV_LPFLLDIV3_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV3_MASK) >> SCG_LPFLLDIV_LPFLLDIV3_SHIFT)
+
+#define SCG_SIRCCFG_RANGE_VAL ((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT)
+#define SCG_FIRCCFG_RANGE_VAL ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT)
+
+#define SCG_LPFLLCFG_FSEL_VAL ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT)
+
+/* Get the value of each field in PCC register. */
+#define PCC_PCS_VAL(reg) ((reg & PCC_CLKCFG_PCS_MASK) >> PCC_CLKCFG_PCS_SHIFT)
+#define PCC_FRAC_VAL(reg) ((reg & PCC_CLKCFG_FRAC_MASK) >> PCC_CLKCFG_FRAC_SHIFT)
+#define PCC_PCD_VAL(reg) ((reg & PCC_CLKCFG_PCD_MASK) >> PCC_CLKCFG_PCD_SHIFT)
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* External XTAL0 (OSC0) clock frequency. */
+uint32_t g_xtal0Freq;
+/* External XTAL32K clock frequency. */
+uint32_t g_xtal32Freq;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+uint32_t CLOCK_GetOsc32kClkFreq(void)
+{
+    assert(g_xtal32Freq);
+    return g_xtal32Freq;
+}
+
+uint32_t CLOCK_GetFlashClkFreq(void)
+{
+    return CLOCK_GetSysClkFreq(kSCG_SysClkSlow);
+}
+
+uint32_t CLOCK_GetBusClkFreq(void)
+{
+    return CLOCK_GetSysClkFreq(kSCG_SysClkSlow);
+}
+
+uint32_t CLOCK_GetPlatClkFreq(void)
+{
+    return CLOCK_GetSysClkFreq(kSCG_SysClkCore);
+}
+
+uint32_t CLOCK_GetCoreSysClkFreq(void)
+{
+    return CLOCK_GetSysClkFreq(kSCG_SysClkCore);
+}
+
+uint32_t CLOCK_GetExtClkFreq(void)
+{
+    return CLOCK_GetSysClkFreq(kSCG_SysClkExt);
+}
+
+uint32_t CLOCK_GetFreq(clock_name_t clockName)
+{
+    uint32_t freq;
+
+    switch (clockName)
+    {
+        /* System layer clock. */
+        case kCLOCK_CoreSysClk:
+        case kCLOCK_PlatClk:
+            freq = CLOCK_GetSysClkFreq(kSCG_SysClkCore);
+            break;
+        case kCLOCK_BusClk:
+            freq = CLOCK_GetSysClkFreq(kSCG_SysClkBus);
+            break;
+        case kCLOCK_FlashClk:
+            freq = CLOCK_GetSysClkFreq(kSCG_SysClkSlow);
+            break;
+        case kCLOCK_ExtClk:
+            freq = CLOCK_GetSysClkFreq(kSCG_SysClkExt);
+            break;
+        /* Original clock source. */
+        case kCLOCK_ScgSysOscClk:
+            freq = CLOCK_GetSysOscFreq();
+            break;
+        case kCLOCK_ScgSircClk:
+            freq = CLOCK_GetSircFreq();
+            break;
+        case kCLOCK_ScgFircClk:
+            freq = CLOCK_GetFircFreq();
+            break;
+        case kCLOCK_ScgLpFllClk:
+            freq = CLOCK_GetLpFllFreq();
+            break;
+
+        /* SOSC div clock. */
+        case kCLOCK_ScgSysOscAsyncDiv1Clk:
+            freq = CLOCK_GetSysOscAsyncFreq(kSCG_AsyncDiv1Clk);
+            break;
+        case kCLOCK_ScgSysOscAsyncDiv2Clk:
+            freq = CLOCK_GetSysOscAsyncFreq(kSCG_AsyncDiv2Clk);
+            break;
+        case kCLOCK_ScgSysOscAsyncDiv3Clk:
+            freq = CLOCK_GetSysOscAsyncFreq(kSCG_AsyncDiv3Clk);
+            break;
+
+        /* SIRC div clock. */
+        case kCLOCK_ScgSircAsyncDiv1Clk:
+            freq = CLOCK_GetSircAsyncFreq(kSCG_AsyncDiv1Clk);
+            break;
+        case kCLOCK_ScgSircAsyncDiv2Clk:
+            freq = CLOCK_GetSircAsyncFreq(kSCG_AsyncDiv2Clk);
+            break;
+        case kCLOCK_ScgSircAsyncDiv3Clk:
+            freq = CLOCK_GetSircAsyncFreq(kSCG_AsyncDiv3Clk);
+            break;
+
+        /* FIRC div clock. */
+        case kCLOCK_ScgFircAsyncDiv1Clk:
+            freq = CLOCK_GetFircAsyncFreq(kSCG_AsyncDiv1Clk);
+            break;
+        case kCLOCK_ScgFircAsyncDiv2Clk:
+            freq = CLOCK_GetFircAsyncFreq(kSCG_AsyncDiv2Clk);
+            break;
+        case kCLOCK_ScgFircAsyncDiv3Clk:
+            freq = CLOCK_GetFircAsyncFreq(kSCG_AsyncDiv3Clk);
+            break;
+
+        /* LPFLL div clock. */
+        case kCLOCK_ScgSysLpFllAsyncDiv1Clk:
+            freq = CLOCK_GetLpFllAsyncFreq(kSCG_AsyncDiv1Clk);
+            break;
+        case kCLOCK_ScgSysLpFllAsyncDiv2Clk:
+            freq = CLOCK_GetLpFllAsyncFreq(kSCG_AsyncDiv2Clk);
+            break;
+        case kCLOCK_ScgSysLpFllAsyncDiv3Clk:
+            freq = CLOCK_GetLpFllAsyncFreq(kSCG_AsyncDiv3Clk);
+            break;
+
+        /* Other clocks. */
+        case kCLOCK_LpoClk:
+            freq = CLOCK_GetLpoClkFreq();
+            break;
+        case kCLOCK_Osc32kClk:
+            freq = CLOCK_GetOsc32kClkFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+uint32_t CLOCK_GetIpFreq(clock_ip_name_t name)
+{
+    uint32_t reg = (*(volatile uint32_t *)name);
+
+    scg_async_clk_t asycClk;
+    uint32_t freq;
+
+    assert(reg & PCC_CLKCFG_PR_MASK);
+
+    switch (name)
+    {
+        case kCLOCK_Lpit0:
+        case kCLOCK_Lpit1:
+            asycClk = kSCG_AsyncDiv3Clk;
+            break;
+        case kCLOCK_Sdhc0:
+        case kCLOCK_Usb0:
+            asycClk = kSCG_AsyncDiv1Clk;
+            break;
+        default:
+            asycClk = kSCG_AsyncDiv2Clk;
+            break;
+    }
+
+    switch (PCC_PCS_VAL(reg))
+    {
+        case kCLOCK_IpSrcSysOscAsync:
+            freq = CLOCK_GetSysOscAsyncFreq(asycClk);
+            break;
+        case kCLOCK_IpSrcSircAsync:
+            freq = CLOCK_GetSircAsyncFreq(asycClk);
+            break;
+        case kCLOCK_IpSrcFircAsync:
+            freq = CLOCK_GetFircAsyncFreq(asycClk);
+            break;
+        case kCLOCK_IpSrcLpFllAsync:
+            freq = CLOCK_GetLpFllAsyncFreq(asycClk);
+            break;
+        default: /* kCLOCK_IpSrcNoneOrExt. */
+            freq = 0U;
+            break;
+    }
+
+    if (0U != (reg & (PCC_CLKCFG_PCD_MASK | PCC_CLKCFG_FRAC_MASK)))
+    {
+        return freq * (PCC_FRAC_VAL(reg) + 1U) / (PCC_PCD_VAL(reg) + 1U);
+    }
+    else
+    {
+        return freq;
+    }
+}
+
+bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
+{
+    bool ret = true;
+
+    CLOCK_SetIpSrc(kCLOCK_Usb0, kCLOCK_IpSrcFircAsync);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable clock gate. */
+    CLOCK_EnableClock(kCLOCK_Usb0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    USBVREG->CTRL |= USBVREG_CTRL_EN_MASK;
+    USB0->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK;
+
+    if (kCLOCK_UsbSrcIrc48M == src)
+    {
+        USB0->CLK_RECOVER_IRC_EN = 0x03U;
+        USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
+        USB0->CLK_RECOVER_INT_EN = 0x00U;
+    }
+    return ret;
+}
+
+uint32_t CLOCK_GetSysClkFreq(scg_sys_clk_t type)
+{
+    uint32_t freq;
+
+    scg_sys_clk_config_t sysClkConfig;
+
+    CLOCK_GetCurSysClkConfig(&sysClkConfig); /* Get the main clock for SoC platform. */
+
+    switch (sysClkConfig.src)
+    {
+        case kSCG_SysClkSrcSysOsc:
+            freq = CLOCK_GetSysOscFreq();
+            break;
+        case kSCG_SysClkSrcSirc:
+            freq = CLOCK_GetSircFreq();
+            break;
+        case kSCG_SysClkSrcFirc:
+            freq = CLOCK_GetFircFreq();
+            break;
+        case kSCG_SysClkSrcRosc:
+            freq = CLOCK_GetRtcOscFreq();
+            break;
+        case kSCG_SysClkSrcLpFll:
+            freq = CLOCK_GetLpFllFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    freq /= (sysClkConfig.divCore + 1U); /* divided by the DIVCORE firstly. */
+
+    if (kSCG_SysClkSlow == type)
+    {
+        freq /= (sysClkConfig.divSlow + 1U);
+    }
+    else if (kSCG_SysClkBus == type)
+    {
+        freq /= (sysClkConfig.divBus + 1U);
+    }
+    else if (kSCG_SysClkExt == type)
+    {
+        freq /= (sysClkConfig.divExt + 1U);
+    }
+    else
+    {
+    }
+
+    return freq;
+}
+
+status_t CLOCK_InitSysOsc(const scg_sosc_config_t *config)
+{
+    assert(config);
+    status_t status;
+    uint8_t tmp8;
+
+    /* De-init the SOSC first. */
+    status = CLOCK_DeinitSysOsc();
+
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    /* Now start to set up OSC clock. */
+    /* Step 1. Setup dividers. */
+    SCG->SOSCDIV =
+        SCG_SOSCDIV_SOSCDIV1(config->div1) | SCG_SOSCDIV_SOSCDIV2(config->div2) | SCG_SOSCDIV_SOSCDIV3(config->div3);
+
+    /* Step 2. Set OSC configuration. */
+
+    /* Step 3. Enable clock. */
+    /* SCG->SOSCCSR = SCG_SOSCCSR_SOSCEN_MASK | (config->enableMode); */
+    tmp8 = config->enableMode;
+    tmp8 |= SCG_SOSCCSR_SOSCEN_MASK;
+    SCG->SOSCCSR = tmp8;
+
+    /* Step 4. Wait for OSC clock to be valid. */
+    while (!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK))
+    {
+    }
+
+    /* Step 5. Enabe monitor. */
+    SCG->SOSCCSR |= (uint32_t)config->monitorMode;
+
+    return kStatus_Success;
+}
+
+status_t CLOCK_DeinitSysOsc(void)
+{
+    uint32_t reg = SCG->SOSCCSR;
+
+    /* If clock is used by system, return error. */
+    if (reg & SCG_SOSCCSR_SOSCSEL_MASK)
+    {
+        return kStatus_SCG_Busy;
+    }
+
+    /* If configure register is locked, return error. */
+    if (reg & SCG_SOSCCSR_LK_MASK)
+    {
+        return kStatus_ReadOnly;
+    }
+
+    SCG->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK;
+
+    return kStatus_Success;
+}
+
+uint32_t CLOCK_GetSysOscFreq(void)
+{
+    if (SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) /* System OSC clock is valid. */
+    {
+        /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
+        assert(g_xtal0Freq);
+        return g_xtal0Freq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+uint32_t CLOCK_GetSysOscAsyncFreq(scg_async_clk_t type)
+{
+    uint32_t oscFreq = CLOCK_GetSysOscFreq();
+    uint32_t divider = 0U;
+
+    /* Get divider. */
+    if (oscFreq)
+    {
+        switch (type)
+        {
+            case kSCG_AsyncDiv3Clk: /* SOSCDIV3_CLK. */
+                divider = SCG_SOSCDIV_SOSCDIV3_VAL;
+                break;
+            case kSCG_AsyncDiv2Clk: /* SOSCDIV2_CLK. */
+                divider = SCG_SOSCDIV_SOSCDIV2_VAL;
+                break;
+            case kSCG_AsyncDiv1Clk: /* SOSCDIV1_CLK. */
+                divider = SCG_SOSCDIV_SOSCDIV1_VAL;
+                break;
+            default:
+                break;
+        }
+    }
+    if (divider)
+    {
+        return oscFreq >> (divider - 1U);
+    }
+    else /* Output disabled. */
+    {
+        return 0U;
+    }
+}
+
+status_t CLOCK_InitSirc(const scg_sirc_config_t *config)
+{
+    assert(config);
+
+    status_t status;
+
+    /* De-init the SIRC first. */
+    status = CLOCK_DeinitSirc();
+
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    /* Now start to set up SIRC clock. */
+    /* Step 1. Setup dividers. */
+    SCG->SIRCDIV =
+        SCG_SIRCDIV_SIRCDIV1(config->div1) | SCG_SIRCDIV_SIRCDIV2(config->div2) | SCG_SIRCDIV_SIRCDIV3(config->div3);
+
+    /* Step 2. Set SIRC configuration. */
+    SCG->SIRCCFG = SCG_SIRCCFG_RANGE(config->range);
+
+    /* Step 3. Enable clock. */
+    SCG->SIRCCSR = SCG_SIRCCSR_SIRCEN_MASK | config->enableMode;
+
+    /* Step 4. Wait for SIRC clock to be valid. */
+    while (!(SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK))
+    {
+    }
+
+    return kStatus_Success;
+}
+
+status_t CLOCK_DeinitSirc(void)
+{
+    uint32_t reg = SCG->SIRCCSR;
+
+    /* If clock is used by system, return error. */
+    if (reg & SCG_SIRCCSR_SIRCSEL_MASK)
+    {
+        return kStatus_SCG_Busy;
+    }
+
+    /* If configure register is locked, return error. */
+    if (reg & SCG_SIRCCSR_LK_MASK)
+    {
+        return kStatus_ReadOnly;
+    }
+
+    SCG->SIRCCSR = 0U;
+
+    return kStatus_Success;
+}
+
+uint32_t CLOCK_GetSircFreq(void)
+{
+    static const uint32_t sircFreq[] = {SCG_SIRC_LOW_RANGE_FREQ, SCG_SIRC_HIGH_RANGE_FREQ};
+
+    if (SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK) /* SIRC is valid. */
+    {
+        return sircFreq[SCG_SIRCCFG_RANGE_VAL];
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+uint32_t CLOCK_GetSircAsyncFreq(scg_async_clk_t type)
+{
+    uint32_t sircFreq = CLOCK_GetSircFreq();
+    uint32_t divider = 0U;
+
+    /* Get divider. */
+    if (sircFreq)
+    {
+        switch (type)
+        {
+            case kSCG_AsyncDiv3Clk: /* SIRCDIV3_CLK. */
+                divider = SCG_SIRCDIV_SIRCDIV3_VAL;
+                break;
+            case kSCG_AsyncDiv2Clk: /* SIRCDIV2_CLK. */
+                divider = SCG_SIRCDIV_SIRCDIV2_VAL;
+                break;
+            case kSCG_AsyncDiv1Clk: /* SIRCDIV2_CLK. */
+                divider = SCG_SIRCDIV_SIRCDIV1_VAL;
+                break;
+            default:
+                break;
+        }
+    }
+    if (divider)
+    {
+        return sircFreq >> (divider - 1U);
+    }
+    else /* Output disabled. */
+    {
+        return 0U;
+    }
+}
+
+status_t CLOCK_InitFirc(const scg_firc_config_t *config)
+{
+    assert(config);
+
+    status_t status;
+
+    /* De-init the FIRC first. */
+    status = CLOCK_DeinitFirc();
+
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    /* Now start to set up FIRC clock. */
+    /* Step 1. Setup dividers. */
+    SCG->FIRCDIV =
+        SCG_FIRCDIV_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2) | SCG_FIRCDIV_FIRCDIV3(config->div3);
+
+    /* Step 2. Set FIRC configuration. */
+    SCG->FIRCCFG = SCG_FIRCCFG_RANGE(config->range);
+
+    /* Step 3. Set trimming configuration. */
+    if (config->trimConfig)
+    {
+        SCG->FIRCTCFG =
+            SCG_FIRCTCFG_TRIMDIV(config->trimConfig->trimDiv) | SCG_FIRCTCFG_TRIMSRC(config->trimConfig->trimSrc);
+
+        /* TODO: Write FIRCSTAT cause bus error: TKT266932. */
+        if (kSCG_FircTrimNonUpdate == config->trimConfig->trimMode)
+        {
+            SCG->FIRCSTAT = SCG_FIRCSTAT_TRIMCOAR(config->trimConfig->trimCoar) |
+                            SCG_FIRCSTAT_TRIMFINE(config->trimConfig->trimFine);
+        }
+
+        /* trim mode. */
+        SCG->FIRCCSR = config->trimConfig->trimMode;
+
+        if (SCG->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK)
+        {
+            return kStatus_Fail;
+        }
+    }
+
+    /* Step 4. Enable clock. */
+    SCG->FIRCCSR |= (SCG_FIRCCSR_FIRCEN_MASK | SCG_FIRCCSR_FIRCTREN_MASK | config->enableMode);
+
+    /* Step 5. Wait for FIRC clock to be valid. */
+    while (!(SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK))
+    {
+    }
+
+    return kStatus_Success;
+}
+
+status_t CLOCK_DeinitFirc(void)
+{
+    uint32_t reg = SCG->FIRCCSR;
+
+    /* If clock is used by system, return error. */
+    if (reg & SCG_FIRCCSR_FIRCSEL_MASK)
+    {
+        return kStatus_SCG_Busy;
+    }
+
+    /* If configure register is locked, return error. */
+    if (reg & SCG_FIRCCSR_LK_MASK)
+    {
+        return kStatus_ReadOnly;
+    }
+
+    SCG->FIRCCSR = SCG_FIRCCSR_FIRCERR_MASK;
+
+    return kStatus_Success;
+}
+
+uint32_t CLOCK_GetFircFreq(void)
+{
+    static const uint32_t fircFreq[] = {
+        SCG_FIRC_FREQ0, SCG_FIRC_FREQ1, SCG_FIRC_FREQ2, SCG_FIRC_FREQ3,
+    };
+
+    if (SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) /* FIRC is valid. */
+    {
+        return fircFreq[SCG_FIRCCFG_RANGE_VAL];
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+uint32_t CLOCK_GetFircAsyncFreq(scg_async_clk_t type)
+{
+    uint32_t fircFreq = CLOCK_GetFircFreq();
+    uint32_t divider = 0U;
+
+    /* Get divider. */
+    if (fircFreq)
+    {
+        switch (type)
+        {
+            case kSCG_AsyncDiv3Clk: /* FIRCDIV3_CLK. */
+                divider = SCG_FIRCDIV_FIRCDIV3_VAL;
+                break;
+            case kSCG_AsyncDiv2Clk: /* FIRCDIV2_CLK. */
+                divider = SCG_FIRCDIV_FIRCDIV2_VAL;
+                break;
+            case kSCG_AsyncDiv1Clk: /* FIRCDIV1_CLK. */
+                divider = SCG_FIRCDIV_FIRCDIV1_VAL;
+                break;
+            default:
+                break;
+        }
+    }
+    if (divider)
+    {
+        return fircFreq >> (divider - 1U);
+    }
+    else /* Output disabled. */
+    {
+        return 0U;
+    }
+}
+
+uint32_t CLOCK_GetRtcOscFreq(void)
+{
+    if (SCG->ROSCCSR & SCG_ROSCCSR_ROSCVLD_MASK) /* RTC OSC clock is valid. */
+    {
+        /* Please call CLOCK_SetXtal32Freq base on board setting before using RTC OSC clock. */
+        assert(g_xtal32Freq);
+        return g_xtal32Freq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+status_t CLOCK_InitLpFll(const scg_lpfll_config_t *config)
+{
+    assert(config);
+
+    status_t status;
+
+    /* De-init the LPFLL first. */
+    status = CLOCK_DeinitLpFll();
+
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    /* Now start to set up LPFLL clock. */
+    /* Step 1. Setup dividers. */
+    SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV1(config->div1) | SCG_LPFLLDIV_LPFLLDIV2(config->div2) |
+                    SCG_LPFLLDIV_LPFLLDIV3(config->div3);
+
+    /* Step 2. Set LPFLL configuration. */
+    SCG->LPFLLCFG = SCG_LPFLLCFG_FSEL(config->range);
+
+    /* Step 3. Set trimming configuration. */
+    if (config->trimConfig)
+    {
+        SCG->LPFLLTCFG = SCG_LPFLLTCFG_TRIMDIV(config->trimConfig->trimDiv) |
+                         SCG_LPFLLTCFG_TRIMSRC(config->trimConfig->trimSrc) |
+                         SCG_LPFLLTCFG_LOCKW2LSB(config->trimConfig->lockMode);
+
+        if (kSCG_LpFllTrimNonUpdate == config->trimConfig->trimMode)
+        {
+            SCG->LPFLLSTAT = config->trimConfig->trimValue;
+        }
+
+        /* Trim mode. */
+        SCG->LPFLLCSR = config->trimConfig->trimMode;
+
+        if (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLERR_MASK)
+        {
+            return kStatus_Fail;
+        }
+    }
+
+    /* Step 4. Enable clock. */
+    SCG->LPFLLCSR |= (SCG_LPFLLCSR_LPFLLEN_MASK | config->enableMode);
+
+    /* Step 5. Wait for LPFLL clock to be valid. */
+    while (!(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK))
+    {
+    }
+
+    /* Step 6. Wait for LPFLL trim lock. */
+    if ((config->trimConfig) && (kSCG_LpFllTrimUpdate == config->trimConfig->trimMode))
+    {
+        while (!(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK))
+        {
+        }
+    }
+
+    return kStatus_Success;
+}
+
+status_t CLOCK_DeinitLpFll(void)
+{
+    uint32_t reg = SCG->LPFLLCSR;
+
+    /* If clock is used by system, return error. */
+    if (reg & SCG_LPFLLCSR_LPFLLSEL_MASK)
+    {
+        return kStatus_SCG_Busy;
+    }
+
+    /* If configure register is locked, return error. */
+    if (reg & SCG_LPFLLCSR_LK_MASK)
+    {
+        return kStatus_ReadOnly;
+    }
+
+    SCG->LPFLLCSR = SCG_LPFLLCSR_LPFLLERR_MASK;
+
+    return kStatus_Success;
+}
+
+uint32_t CLOCK_GetLpFllFreq(void)
+{
+    static const uint32_t lpfllFreq[] = {
+        SCG_LPFLL_FREQ0, SCG_LPFLL_FREQ1, SCG_LPFLL_FREQ2, SCG_LPFLL_FREQ3,
+    };
+
+    if (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK) /* LPFLL is valid. */
+    {
+        return lpfllFreq[SCG_LPFLLCFG_FSEL_VAL];
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+uint32_t CLOCK_GetLpFllAsyncFreq(scg_async_clk_t type)
+{
+    uint32_t lpfllFreq = CLOCK_GetLpFllFreq();
+    uint32_t divider = 0U;
+
+    /* Get divider. */
+    if (lpfllFreq)
+    {
+        switch (type)
+        {
+            case kSCG_AsyncDiv2Clk: /* LPFLLDIV2_CLK. */
+                divider = SCG_LPFLLDIV_LPFLLDIV2_VAL;
+                break;
+            case kSCG_AsyncDiv1Clk: /* LPFLLDIV1_CLK. */
+                divider = SCG_LPFLLDIV_LPFLLDIV1_VAL;
+                break;
+            default:
+                break;
+        }
+    }
+    if (divider)
+    {
+        return lpfllFreq >> (divider - 1U);
+    }
+    else /* Output disabled. */
+    {
+        return 0U;
+    }
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_clock.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_clock.h
new file mode 100644
index 0000000..8fa75c3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_clock.h
@@ -0,0 +1,1582 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright (c) 2016 - 2017 , NXP
+ * All rights reserved.
+ *
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_CLOCK_H_
+#define _FSL_CLOCK_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup clock */
+/*! @{ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Configurations
+ ******************************************************************************/
+
+/*! @brief Configure whether driver controls clock
+ *
+ * When set to 0, peripheral drivers will enable clock in initialize function
+ * and disable clock in de-initialize function. When set to 1, peripheral
+ * driver will not control the clock, application could contol the clock out of
+ * the driver.
+ *
+ * @note All drivers share this feature switcher. If it is set to 1, application
+ * should handle clock enable and disable for all drivers.
+ */
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
+#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief CLOCK driver version 2.1.0. */
+#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*@}*/
+
+/*! @brief External XTAL0 (OSC0/SYSOSC) clock frequency.
+ *
+ * The XTAL0/EXTAL0 (OSC0/SYSOSC) clock frequency in Hz. When the clock is set up, use the
+ * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
+ * if XTAL0 is 8 MHz:
+ * @code
+ * CLOCK_InitSysOsc(...); // Set up the OSC0/SYSOSC
+ * CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value in the clock driver.
+ * @endcode
+ *
+ * This is important for the multicore platforms where only one core needs to set up the
+ * OSC0/SYSOSC using CLOCK_InitSysOsc. All other cores need to call the CLOCK_SetXtal0Freq
+ * to get a valid clock frequency.
+ */
+extern uint32_t g_xtal0Freq;
+
+/*! @brief External XTAL32/EXTAL32 clock frequency.
+ *
+ * The XTAL32/EXTAL32 clock frequency in Hz. When the clock is set up, use the
+ * function CLOCK_SetXtal32Freq to set the value in the clock driver.
+ *
+ * This is important for the multicore platforms where only one core needs to set up
+ * the clock. All other cores need to call the CLOCK_SetXtal32Freq
+ * to get a valid clock frequency.
+ */
+extern uint32_t g_xtal32Freq;
+
+/*! @brief Clock ip name array for MAX. */
+#define MAX_CLOCKS  \
+    {               \
+        kCLOCK_Max0 \
+    }
+
+/*! @brief Clock ip name array for EDMA. */
+#define EDMA_CLOCKS                \
+    {                              \
+        kCLOCK_Edma0, kCLOCK_Edma1 \
+    }
+
+/*! @brief Clock ip name array for FLEXBUS. */
+#define FLEXBUS_CLOCKS \
+    {                  \
+        kCLOCK_Flexbus \
+    }
+
+/*! @brief XRDC clock gate number. */
+#define FSL_CLOCK_XRDC_GATE_COUNT (5U)
+
+/*! @brief Clock ip name array for XRDC. */
+#define XRDC_CLOCKS                                                                           \
+    {                                                                                         \
+        kCLOCK_Xrdc0Mgr, kCLOCK_Xrdc0Pac, kCLOCK_Xrdc0Mrc, kCLOCK_Xrdc0PacB, kCLOCK_Xrdc0MrcB \
+    }
+
+/*! @brief Clock ip name array for SEMA42. */
+#define SEMA42_CLOCKS                  \
+    {                                  \
+        kCLOCK_Sema420, kCLOCK_Sema421 \
+    }
+
+/*! @brief Clock ip name array for DMAMUX. */
+#define DMAMUX_CLOCKS                  \
+    {                                  \
+        kCLOCK_Dmamux0, kCLOCK_Dmamux1 \
+    }
+
+/*! @brief Clock ip name array for MU. */
+#if (defined(RV32M1_cm0plus_SERIES) || defined(RV32M1_zero_riscy_SERIES))
+#define MU_CLOCKS  \
+    {              \
+        kCLOCK_MuB \
+    }
+#else
+#define MU_CLOCKS  \
+    {              \
+        kCLOCK_MuA \
+    }
+#endif
+
+/*! @brief Clock ip name array for CRC. */
+#define CRC_CLOCKS  \
+    {               \
+        kCLOCK_Crc0 \
+    }
+
+/*! @brief Clock ip name array for LPIT. */
+#define LPIT_CLOCKS                \
+    {                              \
+        kCLOCK_Lpit0, kCLOCK_Lpit1 \
+    }
+
+/*! @brief Clock ip name array for TPM. */
+#define TPM_CLOCKS                                         \
+    {                                                      \
+        kCLOCK_Tpm0, kCLOCK_Tpm1, kCLOCK_Tpm2, kCLOCK_Tpm3 \
+    }
+
+/*! @brief Clock ip name array for TRNG. */
+#define TRNG_CLOCKS \
+    {               \
+        kCLOCK_Trng \
+    }
+
+/*! @brief Clock ip name array for SMVSIM. */
+#define EMVSIM_CLOCKS  \
+    {                  \
+        kCLOCK_Emvsim0 \
+    }
+
+/*! @brief Clock ip name array for EWM. */
+#define EWM_CLOCKS  \
+    {               \
+        kCLOCK_Ewm0 \
+    }
+
+/*! @brief Clock ip name array for FLEXIO. */
+#define FLEXIO_CLOCKS  \
+    {                  \
+        kCLOCK_Flexio0 \
+    }
+
+/*! @brief Clock ip name array for LPI2C0. */
+#define LPI2C_CLOCKS                                               \
+    {                                                              \
+        kCLOCK_Lpi2c0, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3 \
+    }
+
+/*! @brief Clock ip name array for SAI. */
+#define SAI_CLOCKS  \
+    {               \
+        kCLOCK_Sai0 \
+    }
+
+/*! @brief Clock ip name array for SDHC. */
+#define USDHC_CLOCKS \
+    {                \
+        kCLOCK_Sdhc0 \
+    }
+
+/*! @brief Clock ip name array for LPSPI. */
+#define LPSPI_CLOCKS                                               \
+    {                                                              \
+        kCLOCK_Lpspi0, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3 \
+    }
+
+/*! @brief Clock ip name array for LPUART. */
+#define LPUART_CLOCKS                                                  \
+    {                                                                  \
+        kCLOCK_Lpuart0, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3 \
+    }
+
+/*! @brief Clock ip name array for USB. */
+#define USB_CLOCKS  \
+    {               \
+        kCLOCK_Usb0 \
+    }
+
+/*! @brief Clock ip name array for PORT. */
+#define PORT_CLOCKS                                                          \
+    {                                                                        \
+        kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
+    }
+
+/*! @brief Clock ip name array for LPADC. */
+#define LPADC_CLOCKS  \
+    {                 \
+        kCLOCK_Lpadc0 \
+    }
+
+/*! @brief Clock ip name array for DAC. */
+#define LPDAC_CLOCKS \
+    {                \
+        kCLOCK_Dac0  \
+    }
+
+/*! @brief Clock ip name array for INTMUX. */
+#if (defined(RV32M1_ri5cy_SERIES) || defined(RV32M1_zero_riscy_SERIES))
+#define INTMUX_CLOCKS                  \
+    {                                  \
+        kCLOCK_Intmux0, kCLOCK_Intmux1 \
+    }
+#else
+#define INTMUX_CLOCKS                    \
+    {                                    \
+        kCLOCK_IpInvalid, kCLOCK_Intmux0 \
+    }
+#endif
+
+/*! @brief Clock ip name array for EXT. */
+#define EXT_CLOCKS               \
+    {                            \
+        kCLOCK_Ext0, kCLOCK_Ext1 \
+    }
+
+/*! @brief Clock ip name array for VREF. */
+#define VREF_CLOCKS \
+    {               \
+        kCLOCK_Vref \
+    }
+
+/*! @brief Clock ip name array for FGPIO. */
+#define FGPIO_CLOCKS                                                                          \
+    {                                                                                         \
+        kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Rgpio1 \
+    }
+
+/*! @brief Clock name used to get clock frequency.
+ *
+ * These clocks source would be generated from SCG module.
+ */
+typedef enum _clock_name
+{
+    /* ----------------------------- System layer clock -------------------------------*/
+    kCLOCK_CoreSysClk, /*!< Core 0/1 clock. */
+    kCLOCK_SlowClk,    /*!< SLOW_CLK with DIVSLOW. */
+    kCLOCK_PlatClk,    /*!< PLAT_CLK. */
+    kCLOCK_SysClk,     /*!< SYS_CLK. */
+    kCLOCK_BusClk,     /*!< BUS_CLK with DIVBUS. */
+    kCLOCK_ExtClk,     /*!< One clock selection of CLKOUT from main clock after DIVCORE and DIVEXT divider.*/
+
+    /* ------------------------------------ SCG clock ---------------------------------*/
+    kCLOCK_ScgSysLpFllAsyncDiv1Clk, /*!< LPFLL_DIV1_CLK. */
+    kCLOCK_ScgSysLpFllAsyncDiv2Clk, /*!< LPFLL_DIV1_CLK. */
+    kCLOCK_ScgSysLpFllAsyncDiv3Clk, /*!< LPFLL_DIV1_CLK. */
+
+    kCLOCK_ScgSircAsyncDiv1Clk, /*!< SIRCDIV1_CLK.                                   */
+    kCLOCK_ScgSircAsyncDiv2Clk, /*!< SIRCDIV2_CLK.                                   */
+    kCLOCK_ScgSircAsyncDiv3Clk, /*!< SIRCDIV3_CLK.                                   */
+
+    kCLOCK_ScgFircAsyncDiv1Clk, /*!< FIRCDIV1_CLK.                                   */
+    kCLOCK_ScgFircAsyncDiv2Clk, /*!< FIRCDIV2_CLK.                                   */
+    kCLOCK_ScgFircAsyncDiv3Clk, /*!< FIRCDIV3_CLK.                                   */
+
+    kCLOCK_ScgSysOscAsyncDiv1Clk, /*!< SOSCDIV1_CLK.                                   */
+    kCLOCK_ScgSysOscAsyncDiv2Clk, /*!< SOSCDIV2_CLK.                                   */
+    kCLOCK_ScgSysOscAsyncDiv3Clk, /*!< SOSCDIV3_CLK.                                   */
+
+    /* For SCG_CLKOUT output */
+    /* kCLOCK_ExtClk, */
+    kCLOCK_ScgSysOscClk, /*!< SCG system OSC clock. (SYSOSC)                      */
+    kCLOCK_ScgSircClk,   /*!< SCG SIRC clock.                                     */
+    kCLOCK_ScgFircClk,   /*!< SCG FIRC clock.                                     */
+    kCLOCK_RtcOscClk,    /*!< RTC OSC clock. */
+    kCLOCK_ScgLpFllClk,  /*!< SCG Low-power FLL clock. (LPFLL)                     */
+
+    /* --------------------------------- Other clock ----------------------------------*/
+    kCLOCK_LpoClk,    /*!< LPO clock                                           */
+    kCLOCK_Osc32kClk, /*!< External OSC 32K clock (OSC32KCLK)                  */
+} clock_name_t;
+
+#define kCLOCK_FlashClk kCLOCK_SlowClk
+#define kCLOCK_RfClk kCLOCK_ScgSysOscClk
+#define LPO_CLK_FREQ 1000U
+
+/*!
+ * @brief Clock source for peripherals that support various clock selections.
+ *
+ * These options are for PCC->CLKCFG[PCS].
+ */
+typedef enum _clock_ip_src
+{
+    kCLOCK_IpSrcNoneOrExt = 0U,   /*!< Clock is off or external clock is used. */
+    kCLOCK_IpSrcSysOscAsync = 1U, /*!< System Oscillator async clock.          */
+    kCLOCK_IpSrcSircAsync = 2U,   /*!< Slow IRC async clock.                   */
+    kCLOCK_IpSrcFircAsync = 3U,   /*!< Fast IRC async clock.                   */
+    kCLOCK_IpSrcLpFllAsync = 6U   /*!< System LPFLL async clock.               */
+} clock_ip_src_t;
+
+/*!
+ * @brief Peripheral clock name difinition used for clock gate, clock source
+ * and clock divider setting. It is defined as the corresponding register address.
+ */
+#define MAKE_PCC_REGADDR(base, offset) ((base) + (offset))
+typedef enum _clock_ip_name
+{
+    kCLOCK_IpInvalid = 0U,
+    /* PCC 0 */
+    kCLOCK_Mscm = MAKE_PCC_REGADDR(PCC0_BASE, 0x4),
+    kCLOCK_Syspm = MAKE_PCC_REGADDR(PCC0_BASE, 0xC),
+    kCLOCK_Max0 = MAKE_PCC_REGADDR(PCC0_BASE, 0x10),
+    kCLOCK_Edma0 = MAKE_PCC_REGADDR(PCC0_BASE, 0x20),
+    kCLOCK_Flexbus = MAKE_PCC_REGADDR(PCC0_BASE, 0x30),
+    kCLOCK_Xrdc0Mgr = MAKE_PCC_REGADDR(PCC0_BASE, 0x50),
+    kCLOCK_Xrdc0Pac = MAKE_PCC_REGADDR(PCC0_BASE, 0x58),
+    kCLOCK_Xrdc0Mrc = MAKE_PCC_REGADDR(PCC0_BASE, 0x5C),
+    kCLOCK_Sema420 = MAKE_PCC_REGADDR(PCC0_BASE, 0x6C),
+    kCLOCK_Dmamux0 = MAKE_PCC_REGADDR(PCC0_BASE, 0x84),
+    kCLOCK_Ewm0 = MAKE_PCC_REGADDR(PCC0_BASE, 0x88),
+    kCLOCK_MuA = MAKE_PCC_REGADDR(PCC0_BASE, 0x94),
+    kCLOCK_Crc0 = MAKE_PCC_REGADDR(PCC0_BASE, 0xBC),
+    kCLOCK_Lpit0 = MAKE_PCC_REGADDR(PCC0_BASE, 0xC0),
+    kCLOCK_Tpm0 = MAKE_PCC_REGADDR(PCC0_BASE, 0xD4),
+    kCLOCK_Tpm1 = MAKE_PCC_REGADDR(PCC0_BASE, 0xD8),
+    kCLOCK_Tpm2 = MAKE_PCC_REGADDR(PCC0_BASE, 0xDC),
+    kCLOCK_Emvsim0 = MAKE_PCC_REGADDR(PCC0_BASE, 0xE0),
+    kCLOCK_Flexio0 = MAKE_PCC_REGADDR(PCC0_BASE, 0xE4),
+    kCLOCK_Lpi2c0 = MAKE_PCC_REGADDR(PCC0_BASE, 0xE8),
+    kCLOCK_Lpi2c1 = MAKE_PCC_REGADDR(PCC0_BASE, 0xEC),
+    kCLOCK_Lpi2c2 = MAKE_PCC_REGADDR(PCC0_BASE, 0xF0),
+    kCLOCK_Sai0 = MAKE_PCC_REGADDR(PCC0_BASE, 0xF4),
+    kCLOCK_Sdhc0 = MAKE_PCC_REGADDR(PCC0_BASE, 0xF8),
+    kCLOCK_Lpspi0 = MAKE_PCC_REGADDR(PCC0_BASE, 0xFC),
+    kCLOCK_Lpspi1 = MAKE_PCC_REGADDR(PCC0_BASE, 0x100),
+    kCLOCK_Lpspi2 = MAKE_PCC_REGADDR(PCC0_BASE, 0x104),
+    kCLOCK_Lpuart0 = MAKE_PCC_REGADDR(PCC0_BASE, 0x108),
+    kCLOCK_Lpuart1 = MAKE_PCC_REGADDR(PCC0_BASE, 0x10C),
+    kCLOCK_Lpuart2 = MAKE_PCC_REGADDR(PCC0_BASE, 0x110),
+    kCLOCK_Usb0 = MAKE_PCC_REGADDR(PCC0_BASE, 0x114),
+    kCLOCK_PortA = MAKE_PCC_REGADDR(PCC0_BASE, 0x118),
+    kCLOCK_PortB = MAKE_PCC_REGADDR(PCC0_BASE, 0x11C),
+    kCLOCK_PortC = MAKE_PCC_REGADDR(PCC0_BASE, 0x120),
+    kCLOCK_PortD = MAKE_PCC_REGADDR(PCC0_BASE, 0x124),
+    kCLOCK_Lpadc0 = MAKE_PCC_REGADDR(PCC0_BASE, 0x128),
+    kCLOCK_Dac0 = MAKE_PCC_REGADDR(PCC0_BASE, 0x130),
+    kCLOCK_Vref = MAKE_PCC_REGADDR(PCC0_BASE, 0x134),
+    kCLOCK_Atx = MAKE_PCC_REGADDR(PCC0_BASE, 0x138),
+#if (defined(RV32M1_ri5cy_SERIES) || defined(RV32M1_zero_riscy_SERIES))
+    kCLOCK_Intmux0 = MAKE_PCC_REGADDR(PCC0_BASE, 0x13C),
+#endif
+    kCLOCK_Trace = MAKE_PCC_REGADDR(PCC0_BASE, 0x200),
+    /* PCC1. */
+    kCLOCK_Edma1 = MAKE_PCC_REGADDR(PCC1_BASE, 0x20),
+    kCLOCK_Rgpio1 = MAKE_PCC_REGADDR(PCC1_BASE, 0x3C),
+    kCLOCK_Xrdc0PacB = MAKE_PCC_REGADDR(PCC1_BASE, 0x58),
+    kCLOCK_Xrdc0MrcB = MAKE_PCC_REGADDR(PCC1_BASE, 0x5C),
+    kCLOCK_Sema421 = MAKE_PCC_REGADDR(PCC1_BASE, 0x6C),
+    kCLOCK_Dmamux1 = MAKE_PCC_REGADDR(PCC1_BASE, 0x84),
+#if (defined(RV32M1_ri5cy_SERIES) || defined(RV32M1_zero_riscy_SERIES))
+    kCLOCK_Intmux1 = MAKE_PCC_REGADDR(PCC1_BASE, 0x88),
+#else
+    kCLOCK_Intmux0 = MAKE_PCC_REGADDR(PCC1_BASE, 0x88),
+#endif
+    kCLOCK_MuB = MAKE_PCC_REGADDR(PCC1_BASE, 0x90),
+    kCLOCK_Cau3 = MAKE_PCC_REGADDR(PCC1_BASE, 0xA0),
+    kCLOCK_Trng = MAKE_PCC_REGADDR(PCC1_BASE, 0xA4),
+    kCLOCK_Lpit1 = MAKE_PCC_REGADDR(PCC1_BASE, 0xA8),
+    kCLOCK_Tpm3 = MAKE_PCC_REGADDR(PCC1_BASE, 0xB4),
+    kCLOCK_Lpi2c3 = MAKE_PCC_REGADDR(PCC1_BASE, 0xB8),
+    kCLOCK_Lpspi3 = MAKE_PCC_REGADDR(PCC1_BASE, 0xD4),
+    kCLOCK_Lpuart3 = MAKE_PCC_REGADDR(PCC1_BASE, 0xD8),
+    kCLOCK_PortE = MAKE_PCC_REGADDR(PCC1_BASE, 0xDC),
+    kCLOCK_Ext0 = MAKE_PCC_REGADDR(PCC1_BASE, 0x200),
+    kCLOCK_Ext1 = MAKE_PCC_REGADDR(PCC1_BASE, 0x204),
+} clock_ip_name_t;
+
+/*!
+ * @brief USB clock source definition.
+ */
+typedef enum _clock_usb_src
+{
+    kCLOCK_UsbSrcIrc48M = 1,           /*!< Use IRC48M.    */
+    kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not
+                                               care the clock source. */
+} clock_usb_src_t;
+
+/*!
+ * @brief SCG status return codes.
+ */
+enum _scg_status
+{
+    kStatus_SCG_Busy = MAKE_STATUS(kStatusGroup_SCG, 1),      /*!< Clock is busy.  */
+    kStatus_SCG_InvalidSrc = MAKE_STATUS(kStatusGroup_SCG, 2) /*!< Invalid source. */
+};
+
+/*!
+ * @brief SCG system clock type.
+ */
+typedef enum _scg_sys_clk
+{
+    kSCG_SysClkSlow, /*!< System slow clock. */
+    kSCG_SysClkBus,  /*!< Bus clock.         */
+    kSCG_SysClkExt,  /*!< External clock.    */
+    kSCG_SysClkCore, /*!< Core clock.        */
+} scg_sys_clk_t;
+
+/*!
+ * @brief SCG system clock source.
+ */
+typedef enum _scg_sys_clk_src
+{
+    kSCG_SysClkSrcSysOsc = 1U, /*!< System OSC. */
+    kSCG_SysClkSrcSirc = 2U,   /*!< Slow IRC.   */
+    kSCG_SysClkSrcFirc = 3U,   /*!< Fast IRC.   */
+    kSCG_SysClkSrcRosc = 4U,   /*!< RTC OSC. */
+    kSCG_SysClkSrcLpFll = 5U,  /*!< Low power FLL. */
+} scg_sys_clk_src_t;
+
+/*!
+ * @brief SCG system clock divider value.
+ */
+typedef enum _scg_sys_clk_div
+{
+    kSCG_SysClkDivBy1 = 0U,   /*!< Divided by 1.  */
+    kSCG_SysClkDivBy2 = 1U,   /*!< Divided by 2.  */
+    kSCG_SysClkDivBy3 = 2U,   /*!< Divided by 3.  */
+    kSCG_SysClkDivBy4 = 3U,   /*!< Divided by 4.  */
+    kSCG_SysClkDivBy5 = 4U,   /*!< Divided by 5.  */
+    kSCG_SysClkDivBy6 = 5U,   /*!< Divided by 6.  */
+    kSCG_SysClkDivBy7 = 6U,   /*!< Divided by 7.  */
+    kSCG_SysClkDivBy8 = 7U,   /*!< Divided by 8.  */
+    kSCG_SysClkDivBy9 = 8U,   /*!< Divided by 9.  */
+    kSCG_SysClkDivBy10 = 9U,  /*!< Divided by 10. */
+    kSCG_SysClkDivBy11 = 10U, /*!< Divided by 11. */
+    kSCG_SysClkDivBy12 = 11U, /*!< Divided by 12. */
+    kSCG_SysClkDivBy13 = 12U, /*!< Divided by 13. */
+    kSCG_SysClkDivBy14 = 13U, /*!< Divided by 14. */
+    kSCG_SysClkDivBy15 = 14U, /*!< Divided by 15. */
+    kSCG_SysClkDivBy16 = 15U  /*!< Divided by 16. */
+} scg_sys_clk_div_t;
+
+/*!
+ * @brief SCG system clock configuration.
+ */
+typedef struct _scg_sys_clk_config
+{
+    uint32_t divSlow : 4; /*!< Slow clock divider, see @ref scg_sys_clk_div_t. */
+    uint32_t divBus : 4;  /*!< Bus clock divider, see @ref scg_sys_clk_div_t.  */
+    uint32_t divExt : 4;  /*!< External clock divider, see @ref scg_sys_clk_div_t.  */
+    uint32_t : 4;         /*!< Reserved. */
+    uint32_t divCore : 4; /*!< Core clock divider, see @ref scg_sys_clk_div_t. */
+    uint32_t : 4;         /*!< Reserved. */
+    uint32_t src : 4;     /*!< System clock source, see @ref scg_sys_clk_src_t. */
+    uint32_t : 4;         /*!< reserved. */
+} scg_sys_clk_config_t;
+
+/*!
+ * @brief SCG clock out configuration (CLKOUTSEL).
+ */
+typedef enum _clock_clkout_src
+{
+    kClockClkoutSelScgExt = 0U,    /*!< SCG external clock. */
+    kClockClkoutSelSysOsc = 1U,    /*!< System OSC.     */
+    kClockClkoutSelSirc = 2U,      /*!< Slow IRC.       */
+    kClockClkoutSelFirc = 3U,      /*!< Fast IRC.       */
+    kClockClkoutSelScgRtcOsc = 4U, /*!< SCG RTC OSC clock. */
+    kClockClkoutSelLpFll = 5U,     /*!< Low power FLL.  */
+} clock_clkout_src_t;
+
+/*!
+ * @brief SCG asynchronous clock type.
+ */
+typedef enum _scg_async_clk
+{
+    kSCG_AsyncDiv1Clk, /*!< The async clock by DIV1, e.g. SOSCDIV1_CLK, SIRCDIV1_CLK. */
+    kSCG_AsyncDiv2Clk, /*!< The async clock by DIV2, e.g. SOSCDIV2_CLK, SIRCDIV2_CLK. */
+    kSCG_AsyncDiv3Clk  /*!< The async clock by DIV3, e.g. SOSCDIV3_CLK, SIRCDIV3_CLK. */
+} scg_async_clk_t;
+
+/*!
+ * @brief SCG asynchronous clock divider value.
+ */
+typedef enum scg_async_clk_div
+{
+    kSCG_AsyncClkDisable = 0U, /*!< Clock output is disabled.  */
+    kSCG_AsyncClkDivBy1 = 1U,  /*!< Divided by 1.              */
+    kSCG_AsyncClkDivBy2 = 2U,  /*!< Divided by 2.              */
+    kSCG_AsyncClkDivBy4 = 3U,  /*!< Divided by 4.              */
+    kSCG_AsyncClkDivBy8 = 4U,  /*!< Divided by 8.              */
+    kSCG_AsyncClkDivBy16 = 5U, /*!< Divided by 16.             */
+    kSCG_AsyncClkDivBy32 = 6U, /*!< Divided by 32.             */
+    kSCG_AsyncClkDivBy64 = 7U  /*!< Divided by 64.             */
+} scg_async_clk_div_t;
+
+/*!
+ * @brief SCG system OSC monitor mode.
+ */
+typedef enum _scg_sosc_monitor_mode
+{
+    kSCG_SysOscMonitorDisable = 0U,                  /*!< Monitor disabled.                          */
+    kSCG_SysOscMonitorInt = SCG_SOSCCSR_SOSCCM_MASK, /*!< Interrupt when the system OSC error is detected. */
+    kSCG_SysOscMonitorReset =
+        SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK /*!< Reset when the system OSC error is detected.     */
+} scg_sosc_monitor_mode_t;
+
+/*! @brief OSC enable mode. */
+enum _scg_sosc_enable_mode
+{
+    kSCG_SysOscEnable = SCG_SOSCCSR_SOSCEN_MASK,             /*!< Enable OSC clock. */
+    kSCG_SysOscEnableInStop = SCG_SOSCCSR_SOSCSTEN_MASK,     /*!< Enable OSC in stop mode. */
+    kSCG_SysOscEnableInLowPower = SCG_SOSCCSR_SOSCLPEN_MASK, /*!< Enable OSC in low power mode. */
+};
+
+/*!
+ * @brief SCG system OSC configuration.
+ */
+typedef struct _scg_sosc_config
+{
+    uint32_t freq;                       /*!< System OSC frequency.                    */
+    scg_sosc_monitor_mode_t monitorMode; /*!< Clock monitor mode selected.     */
+    uint8_t enableMode;                  /*!< Enable mode, OR'ed value of _scg_sosc_enable_mode.  */
+
+    scg_async_clk_div_t div1; /*!< SOSCDIV1 value.                          */
+    scg_async_clk_div_t div2; /*!< SOSCDIV2 value.                          */
+    scg_async_clk_div_t div3; /*!< SOSCDIV3 value.                          */
+
+} scg_sosc_config_t;
+
+/*!
+ * @brief SCG slow IRC clock frequency range.
+ */
+typedef enum _scg_sirc_range
+{
+    kSCG_SircRangeLow, /*!< Slow IRC low range clock (2 MHz, 4 MHz for i.MX 7 ULP).  */
+    kSCG_SircRangeHigh /*!< Slow IRC high range clock (8 MHz, 16 MHz for i.MX 7 ULP). */
+} scg_sirc_range_t;
+
+/*! @brief SIRC enable mode. */
+enum _scg_sirc_enable_mode
+{
+    kSCG_SircEnable = SCG_SIRCCSR_SIRCEN_MASK,            /*!< Enable SIRC clock.             */
+    kSCG_SircEnableInStop = SCG_SIRCCSR_SIRCSTEN_MASK,    /*!< Enable SIRC in stop mode.      */
+    kSCG_SircEnableInLowPower = SCG_SIRCCSR_SIRCLPEN_MASK /*!< Enable SIRC in low power mode. */
+};
+
+/*!
+ * @brief SCG slow IRC clock configuration.
+ */
+typedef struct _scg_sirc_config
+{
+    uint32_t enableMode;      /*!< Enable mode, OR'ed value of _scg_sirc_enable_mode. */
+    scg_async_clk_div_t div1; /*!< SIRCDIV1 value.                          */
+    scg_async_clk_div_t div2; /*!< SIRCDIV2 value.                          */
+    scg_async_clk_div_t div3; /*!< SIRCDIV3 value.                          */
+
+    scg_sirc_range_t range; /*!< Slow IRC frequency range.                */
+} scg_sirc_config_t;
+
+/*!
+ * @brief SCG fast IRC trim mode.
+ */
+typedef enum _scg_firc_trim_mode
+{
+    kSCG_FircTrimNonUpdate = SCG_FIRCCSR_FIRCTREN_MASK,
+    /*!< FIRC trim enable but not enable trim value update. In this mode, the
+     trim value is fixed to the initialized value which is defined by
+     trimCoar and trimFine in configure structure \ref scg_firc_trim_config_t.*/
+
+    kSCG_FircTrimUpdate = SCG_FIRCCSR_FIRCTREN_MASK | SCG_FIRCCSR_FIRCTRUP_MASK
+    /*!< FIRC trim enable and trim value update enable. In this mode, the trim
+     value is auto update. */
+
+} scg_firc_trim_mode_t;
+
+/*!
+ * @brief SCG fast IRC trim predivided value for system OSC.
+ */
+typedef enum _scg_firc_trim_div
+{
+    kSCG_FircTrimDivBy1,    /*!< Divided by 1.    */
+    kSCG_FircTrimDivBy128,  /*!< Divided by 128.  */
+    kSCG_FircTrimDivBy256,  /*!< Divided by 256.  */
+    kSCG_FircTrimDivBy512,  /*!< Divided by 512.  */
+    kSCG_FircTrimDivBy1024, /*!< Divided by 1024. */
+    kSCG_FircTrimDivBy2048  /*!< Divided by 2048. */
+} scg_firc_trim_div_t;
+
+/*!
+ * @brief SCG fast IRC trim source.
+ */
+typedef enum _scg_firc_trim_src
+{
+    kSCG_FircTrimSrcSysOsc = 2U, /*!< System OSC.                 */
+    kSCG_FircTrimSrcRtcOsc = 3U, /*!< RTC OSC (32.768 kHz).       */
+} scg_firc_trim_src_t;
+
+/*!
+ * @brief SCG fast IRC clock trim configuration.
+ */
+typedef struct _scg_firc_trim_config
+{
+    scg_firc_trim_mode_t trimMode; /*!< FIRC trim mode.                       */
+    scg_firc_trim_src_t trimSrc;   /*!< Trim source.                          */
+    scg_firc_trim_div_t trimDiv;   /*!< Trim predivided value for the system OSC.  */
+
+    uint8_t trimCoar; /*!< Trim coarse value; Irrelevant if trimMode is kSCG_FircTrimUpdate. */
+    uint8_t trimFine; /*!< Trim fine value; Irrelevant if trimMode is kSCG_FircTrimUpdate. */
+} scg_firc_trim_config_t;
+
+/*!
+ * @brief SCG fast IRC clock frequency range.
+ */
+typedef enum _scg_firc_range
+{
+    kSCG_FircRange48M, /*!< Fast IRC is trimmed to 48 MHz.  */
+    kSCG_FircRange52M, /*!< Fast IRC is trimmed to 52 MHz.  */
+    kSCG_FircRange56M, /*!< Fast IRC is trimmed to 56 MHz.  */
+    kSCG_FircRange60M  /*!< Fast IRC is trimmed to 60 MHz.  */
+} scg_firc_range_t;
+
+/*! @brief FIRC enable mode. */
+enum _scg_firc_enable_mode
+{
+    kSCG_FircEnable = SCG_FIRCCSR_FIRCEN_MASK,              /*!< Enable FIRC clock.             */
+    kSCG_FircEnableInStop = SCG_FIRCCSR_FIRCSTEN_MASK,      /*!< Enable FIRC in stop mode.      */
+    kSCG_FircEnableInLowPower = SCG_FIRCCSR_FIRCLPEN_MASK,  /*!< Enable FIRC in low power mode. */
+    kSCG_FircDisableRegulator = SCG_FIRCCSR_FIRCREGOFF_MASK /*!< Disable regulator.             */
+};
+
+/*!
+ * @brief SCG fast IRC clock configuration.
+ */
+typedef struct _scg_firc_config_t
+{
+    uint32_t enableMode; /*!< Enable mode, OR'ed value of _scg_firc_enable_mode. */
+
+    scg_async_clk_div_t div1; /*!< FIRCDIV1 value.                          */
+    scg_async_clk_div_t div2; /*!< FIRCDIV2 value.                          */
+    scg_async_clk_div_t div3; /*!< FIRCDIV3 value.                          */
+
+    scg_firc_range_t range; /*!< Fast IRC frequency range.                 */
+
+    const scg_firc_trim_config_t *trimConfig; /*!< Pointer to the FIRC trim configuration; set NULL to disable trim. */
+} scg_firc_config_t;
+
+/*! @brief LPFLL enable mode. */
+enum _scg_lpfll_enable_mode
+{
+    kSCG_LpFllEnable = SCG_LPFLLCSR_LPFLLEN_MASK, /*!< Enable LPFLL clock.             */
+};
+
+/*!
+ * @brief SCG LPFLL clock frequency range.
+ */
+typedef enum _scg_lpfll_range
+{
+    kSCG_LpFllRange48M, /*!< LPFLL is trimmed to 48MHz.  */
+    kSCG_LpFllRange72M, /*!< LPFLL is trimmed to 72MHz.  */
+    kSCG_LpFllRange96M, /*!< LPFLL is trimmed to 96MHz.  */
+    kSCG_LpFllRange120M /*!< LPFLL is trimmed to 120MHz. */
+} scg_lpfll_range_t;
+
+/*!
+ * @brief SCG LPFLL trim mode.
+ */
+typedef enum _scg_lpfll_trim_mode
+{
+    kSCG_LpFllTrimNonUpdate = SCG_LPFLLCSR_LPFLLTREN_MASK,
+    /*!< LPFLL trim is enabled but the trim value update is not enabled. In this mode, the
+     trim value is fixed to the initialized value, which is defined by the @ref trimValue
+     in the structure @ref scg_lpfll_trim_config_t.*/
+
+    kSCG_LpFllTrimUpdate = SCG_LPFLLCSR_LPFLLTREN_MASK | SCG_LPFLLCSR_LPFLLTRUP_MASK
+    /*!< FIRC trim is enabled and trim value update is enabled. In this mode, the trim
+     value is automatically updated. */
+} scg_lpfll_trim_mode_t;
+
+/*!
+ * @brief SCG LPFLL trim source.
+ */
+typedef enum _scg_lpfll_trim_src
+{
+    kSCG_LpFllTrimSrcSirc = 0U,   /*!< SIRC.                 */
+    kSCG_LpFllTrimSrcFirc = 1U,   /*!< FIRC.                 */
+    kSCG_LpFllTrimSrcSysOsc = 2U, /*!< System OSC.           */
+    kSCG_LpFllTrimSrcRtcOsc = 3U, /*!< RTC OSC (32.768 kHz). */
+} scg_lpfll_trim_src_t;
+
+/*!
+ * @brief SCG LPFLL lock mode.
+ */
+typedef enum _scg_lpfll_lock_mode
+{
+    kSCG_LpFllLock1Lsb = 0U, /*!< Lock with 1 LSB. */
+    kSCG_LpFllLock2Lsb = 1U  /*!< Lock with 2 LSB. */
+} scg_lpfll_lock_mode_t;
+
+/*!
+ * @brief SCG LPFLL clock trim configuration.
+ */
+typedef struct _scg_lpfll_trim_config
+{
+    scg_lpfll_trim_mode_t trimMode; /*!< Trim mode.            */
+    scg_lpfll_lock_mode_t lockMode; /*!< Lock mode; Irrelevant if the trimMode is kSCG_LpFllTrimNonUpdate. */
+
+    scg_lpfll_trim_src_t trimSrc; /*!< Trim source.          */
+    uint8_t trimDiv;              /*!< Trim predivideds value, which can be 0 ~ 31.
+                                    [ Trim source frequency / (trimDiv + 1) ] must be 2 MHz or 32768 Hz. */
+
+    uint8_t trimValue; /*!< Trim value; Irrelevant if trimMode is the kSCG_LpFllTrimUpdate. */
+} scg_lpfll_trim_config_t;
+
+/*!
+ * @brief SCG low power FLL configuration.
+ */
+typedef struct _scg_lpfll_config
+{
+    uint8_t enableMode; /*!< Enable mode, OR'ed value of _scg_lpfll_enable_mode */
+
+    scg_async_clk_div_t div1; /*!< LPFLLDIV1 value.                          */
+    scg_async_clk_div_t div2; /*!< LPFLLDIV2 value.                          */
+    scg_async_clk_div_t div3; /*!< LPFLLDIV3 value.                          */
+
+    scg_lpfll_range_t range; /*!< LPFLL frequency range.                     */
+
+    const scg_lpfll_trim_config_t *trimConfig; /*!< Trim configuration; set NULL to disable trim. */
+} scg_lpfll_config_t;
+
+/*!
+ * @brief SCG RTC OSC monitor mode.
+ */
+typedef enum _scg_rosc_monitor_mode
+{
+    kSCG_rtcOscMonitorDisable = 0U,                  /*!< Monitor disable.                          */
+    kSCG_rtcOscMonitorInt = SCG_ROSCCSR_ROSCCM_MASK, /*!< Interrupt when the RTC OSC error is detected. */
+    kSCG_rtcOscMonitorReset =
+        SCG_ROSCCSR_ROSCCM_MASK | SCG_ROSCCSR_ROSCCMRE_MASK /*!< Reset when the RTC OSC error is detected.     */
+} scg_rosc_monitor_mode_t;
+
+/*!
+ * @brief SCG RTC OSC configuration.
+ */
+typedef struct _scg_rosc_config
+{
+    scg_rosc_monitor_mode_t monitorMode; /*!< Clock monitor mode selected.     */
+} scg_rosc_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @brief Enable the clock for specific IP.
+ *
+ * @param name  Which clock to enable, see \ref clock_ip_name_t.
+ */
+static inline void CLOCK_EnableClock(clock_ip_name_t name)
+{
+    assert((*(volatile uint32_t *)name) & PCC_CLKCFG_PR_MASK);
+
+    (*(volatile uint32_t *)name) |= PCC_CLKCFG_CGC_MASK;
+}
+
+/*!
+ * @brief Disable the clock for specific IP.
+ *
+ * @param name  Which clock to disable, see \ref clock_ip_name_t.
+ */
+static inline void CLOCK_DisableClock(clock_ip_name_t name)
+{
+    assert((*(volatile uint32_t *)name) & PCC_CLKCFG_PR_MASK);
+
+    (*(volatile uint32_t *)name) &= ~PCC_CLKCFG_CGC_MASK;
+}
+
+/*!
+ * @brief Check whether the clock is already enabled and configured by
+ * any other core.
+ *
+ * @param name Which peripheral to check, see \ref clock_ip_name_t.
+ * @return True if clock is already enabled, otherwise false.
+ */
+static inline bool CLOCK_IsEnabledByOtherCore(clock_ip_name_t name)
+{
+    assert((*(volatile uint32_t *)name) & PCC_CLKCFG_PR_MASK);
+
+    return ((*(volatile uint32_t *)name) & PCC_CLKCFG_INUSE_MASK) ? true : false;
+}
+
+/*!
+ * @brief Set the clock source for specific IP module.
+ *
+ * Set the clock source for specific IP, not all modules need to set the
+ * clock source, should only use this function for the modules need source
+ * setting.
+ *
+ * @param name Which peripheral to check, see \ref clock_ip_name_t.
+ * @param src Clock source to set.
+ */
+static inline void CLOCK_SetIpSrc(clock_ip_name_t name, clock_ip_src_t src)
+{
+    uint32_t reg = (*(volatile uint32_t *)name);
+
+    assert(reg & PCC_CLKCFG_PR_MASK);
+    assert(!(reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by other core. */
+
+    reg = (reg & ~PCC_CLKCFG_PCS_MASK) | PCC_CLKCFG_PCS(src);
+
+    /*
+     * If clock is already enabled, first disable it, then set the clock
+     * source and re-enable it.
+     */
+    (*(volatile uint32_t *)name) = reg & ~PCC_CLKCFG_CGC_MASK;
+    (*(volatile uint32_t *)name) = reg;
+}
+
+/*!
+ * @brief Set the clock source and divider for specific IP module.
+ *
+ * Set the clock source and divider for specific IP, not all modules need to
+ * set the clock source and divider, should only use this function for the
+ * modules need source and divider setting.
+ *
+ * Divider output clock = Divider input clock x [(fracValue+1)/(divValue+1)]).
+ *
+ * @param name Which peripheral to check, see \ref clock_ip_name_t.
+ * @param src Clock source to set.
+ * @param divValue  The divider value.
+ * @param fracValue The fraction multiply value.
+ */
+static inline void CLOCK_SetIpSrcDiv(clock_ip_name_t name, clock_ip_src_t src, uint8_t divValue, uint8_t fracValue)
+{
+    uint32_t reg = (*(volatile uint32_t *)name);
+
+    assert(reg & PCC_CLKCFG_PR_MASK);
+    assert(!(reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by other core. */
+
+    reg = (reg & ~(PCC_CLKCFG_PCS_MASK | PCC_CLKCFG_FRAC_MASK | PCC_CLKCFG_PCD_MASK)) | PCC_CLKCFG_PCS(src) |
+          PCC_CLKCFG_PCD(divValue) | PCC_CLKCFG_FRAC(fracValue);
+
+    /*
+     * If clock is already enabled, first disable it, then set the clock
+     * source and re-enable it.
+     */
+    (*(volatile uint32_t *)name) = reg & ~PCC_CLKCFG_CGC_MASK;
+    (*(volatile uint32_t *)name) = reg;
+}
+
+/*!
+ * @brief Gets the clock frequency for a specific clock name.
+ *
+ * This function checks the current clock configurations and then calculates
+ * the clock frequency for a specific clock name defined in clock_name_t.
+ *
+ * @param clockName Clock names defined in clock_name_t
+ * @return Clock frequency value in hertz
+ */
+uint32_t CLOCK_GetFreq(clock_name_t clockName);
+
+/*!
+ * @brief Get the core clock or system clock frequency.
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetCoreSysClkFreq(void);
+
+/*!
+ * @brief Get the platform clock frequency.
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetPlatClkFreq(void);
+
+/*!
+ * @brief Get the bus clock frequency.
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetBusClkFreq(void);
+
+/*!
+ * @brief Get the flash clock frequency.
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetFlashClkFreq(void);
+
+/*!
+ * @brief Get the OSC 32K clock frequency (OSC32KCLK).
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetOsc32kClkFreq(void);
+
+/*!
+ * @brief Get the external clock frequency (EXTCLK).
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetExtClkFreq(void);
+
+/*!
+ * @brief Get the LPO clock frequency.
+ *
+ * @return Clock frequency in Hz.
+ */
+static inline uint32_t CLOCK_GetLpoClkFreq(void)
+{
+    return LPO_CLK_FREQ; /* 1k Hz. */
+}
+
+/*!
+ * @brief Gets the functional clock frequency for a specific IP module.
+ *
+ * This function gets the IP module's functional clock frequency based on PCC
+ * registers. It is only used for the IP modules which could select clock source
+ * by PCC[PCS].
+ *
+ * @param name Which peripheral to get, see \ref clock_ip_name_t.
+ * @return Clock frequency value in Hz
+ */
+uint32_t CLOCK_GetIpFreq(clock_ip_name_t name);
+
+/*!
+* @brief Enable the RTC Oscillator.
+*
+* This function enables the Oscillator for RTC external crystal.
+*
+* @param enable Enable the Oscillator or not.
+*/
+static inline void CLOCK_EnableRtcOsc(bool enable)
+{
+    if (enable)
+    {
+        RTC->CR |= RTC_CR_OSCE_MASK;
+    }
+    else
+    {
+        RTC->CR &= ~RTC_CR_OSCE_MASK;
+    }
+}
+
+/*!
+* @brief Enable the RSIM Run Regulator Request.
+*
+* When this function is enabled, the RSIM will request the SPM Run Regulator to be turned on and the
+* RSIM will then stop requesting Stop after the Run Regulator Acknowledge signal is received from
+* the SPM module.
+* The RF OSC would be only available while this function is enabled.
+*
+* @param enable Enable the function or not.
+*/
+static inline void CLOCK_EnableRSIMRunRequest(bool enable)
+{
+    if (enable)
+    {
+        RSIM->POWER |= RSIM_POWER_RSIM_RUN_REQUEST_MASK;
+    }
+    else
+    {
+        RSIM->POWER &= ~RSIM_POWER_RSIM_RUN_REQUEST_MASK;
+    }
+}
+
+/*! @brief Enable USB FS clock.
+ *
+ * @param src  USB FS clock source.
+ * @param freq The frequency specified by src.
+ * @retval true The clock is set successfully.
+ * @retval false The clock source is invalid to get proper USB FS clock.
+ */
+bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
+
+/*! @brief Disable USB FS clock.
+ *
+ * Disable USB FS clock.
+ */
+static inline void CLOCK_DisableUsbfs0Clock(void)
+{
+    CLOCK_DisableClock(kCLOCK_Usb0);
+}
+
+/*!
+ * @name MCU System Clock.
+ * @{
+ */
+
+/*!
+ * @brief Gets the SCG system clock frequency.
+ *
+ * This function gets the SCG system clock frequency. These clocks are used for
+ * core, platform, external, and bus clock domains.
+ *
+ * @param type     Which type of clock to get, core clock or slow clock.
+ * @return  Clock frequency.
+ */
+uint32_t CLOCK_GetSysClkFreq(scg_sys_clk_t type);
+
+/*!
+ * @brief Sets the system clock configuration for VLPR mode.
+ *
+ * This function sets the system clock configuration for VLPR mode.
+ *
+ * @param config Pointer to the configuration.
+ */
+static inline void CLOCK_SetVlprModeSysClkConfig(const scg_sys_clk_config_t *config)
+{
+    assert(config);
+
+    SCG->VCCR = *(const uint32_t *)config;
+}
+
+/*!
+ * @brief Sets the system clock configuration for RUN mode.
+ *
+ * This function sets the system clock configuration for RUN mode.
+ *
+ * @param config Pointer to the configuration.
+ */
+static inline void CLOCK_SetRunModeSysClkConfig(const scg_sys_clk_config_t *config)
+{
+    assert(config);
+
+    SCG->RCCR = *(const uint32_t *)config;
+}
+
+/*!
+ * @brief Sets the system clock configuration for HSRUN mode.
+ *
+ * This function sets the system clock configuration for HSRUN mode.
+ *
+ * @param config Pointer to the configuration.
+ */
+static inline void CLOCK_SetHsrunModeSysClkConfig(const scg_sys_clk_config_t *config)
+{
+    assert(config);
+
+    SCG->HCCR = *(const uint32_t *)config;
+}
+
+/*!
+ * @brief Gets the system clock configuration in the current power mode.
+ *
+ * This function gets the system configuration in the current power mode.
+ *
+ * @param config Pointer to the configuration.
+ */
+static inline void CLOCK_GetCurSysClkConfig(scg_sys_clk_config_t *config)
+{
+    assert(config);
+
+    *(uint32_t *)config = SCG->CSR;
+}
+
+/*!
+ * @brief Sets the clock out selection.
+ *
+ * This function sets the clock out selection (CLKOUTSEL).
+ *
+ * @param setting The selection to set.
+ * @return  The current clock out selection.
+ */
+static inline void CLOCK_SetClkOutSel(clock_clkout_src_t setting)
+{
+    SCG->CLKOUTCNFG = SCG_CLKOUTCNFG_CLKOUTSEL(setting);
+}
+/* @} */
+
+/*!
+ * @name SCG System OSC Clock.
+ * @{
+ */
+
+/*!
+ * @brief Initializes the SCG system OSC.
+ *
+ * This function enables the SCG system OSC clock according to the
+ * configuration.
+ *
+ * @param config   Pointer to the configuration structure.
+ * @retval kStatus_Success System OSC is initialized.
+ * @retval kStatus_SCG_Busy System OSC has been enabled and is used by the system clock.
+ * @retval kStatus_ReadOnly System OSC control register is locked.
+ *
+ * @note This function can't detect whether the system OSC has been enabled and
+ * used by an IP.
+ */
+status_t CLOCK_InitSysOsc(const scg_sosc_config_t *config);
+
+/*!
+ * @brief De-initializes the SCG system OSC.
+ *
+ * This function disables the SCG system OSC clock.
+ *
+ * @retval kStatus_Success System OSC is deinitialized.
+ * @retval kStatus_SCG_Busy System OSC is used by the system clock.
+ * @retval kStatus_ReadOnly System OSC control register is locked.
+ *
+ * @note This function can't detect whether the system OSC is used by an IP.
+ */
+status_t CLOCK_DeinitSysOsc(void);
+
+/*!
+ * @brief Set the asynchronous clock divider.
+ *
+ * @param asyncClk Which asynchronous clock to configure.
+ * @param divider The divider value to set.
+ *
+ * @note There might be glitch when changing the asynchronous divider, so make sure
+ * the asynchronous clock is not used while changing divider.
+ */
+static inline void CLOCK_SetSysOscAsyncClkDiv(scg_async_clk_t asyncClk, scg_async_clk_div_t divider)
+{
+    uint32_t reg = SCG->SOSCDIV;
+
+    switch (asyncClk)
+    {
+        case kSCG_AsyncDiv3Clk:
+            reg = (reg & ~SCG_SOSCDIV_SOSCDIV3_MASK) | SCG_SOSCDIV_SOSCDIV3(divider);
+            break;
+        case kSCG_AsyncDiv2Clk:
+            reg = (reg & ~SCG_SOSCDIV_SOSCDIV2_MASK) | SCG_SOSCDIV_SOSCDIV2(divider);
+            break;
+        default:
+            reg = (reg & ~SCG_SOSCDIV_SOSCDIV1_MASK) | SCG_SOSCDIV_SOSCDIV1(divider);
+            break;
+    }
+
+    SCG->SOSCDIV = reg;
+}
+
+/*!
+ * @brief Gets the SCG system OSC clock frequency (SYSOSC).
+ *
+ * @return  Clock frequency; If the clock is invalid, returns 0.
+ */
+uint32_t CLOCK_GetSysOscFreq(void);
+
+/*!
+ * @brief Gets the SCG asynchronous clock frequency from the system OSC.
+ *
+ * @param type     The asynchronous clock type.
+ * @return  Clock frequency; If the clock is invalid, returns 0.
+ */
+uint32_t CLOCK_GetSysOscAsyncFreq(scg_async_clk_t type);
+
+/*!
+ * @brief Checks whether the system OSC clock error occurs.
+ *
+ * @return  True if the error occurs, false if not.
+ */
+static inline bool CLOCK_IsSysOscErr(void)
+{
+    return (bool)(SCG->SOSCCSR & SCG_SOSCCSR_SOSCERR_MASK);
+}
+
+/*!
+ * @brief Clears the system OSC clock error.
+ */
+static inline void CLOCK_ClearSysOscErr(void)
+{
+    SCG->SOSCCSR |= SCG_SOSCCSR_SOSCERR_MASK;
+}
+
+/*!
+ * @brief Sets the system OSC monitor mode.
+ *
+ * This function sets the system OSC monitor mode. The mode can be disabled,
+ * it can generate an interrupt when the error is disabled, or reset when the error is detected.
+ *
+ * @param mode Monitor mode to set.
+ */
+static inline void CLOCK_SetSysOscMonitorMode(scg_sosc_monitor_mode_t mode)
+{
+    uint32_t reg = SCG->SOSCCSR;
+
+    reg &= ~(SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK);
+
+    reg |= (uint32_t)mode;
+
+    SCG->SOSCCSR = reg;
+}
+
+/*!
+ * @brief Checks whether the system OSC clock is valid.
+ *
+ * @return  True if clock is valid, false if not.
+ */
+static inline bool CLOCK_IsSysOscValid(void)
+{
+    return (bool)(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK);
+}
+/* @} */
+
+/*!
+ * @name SCG Slow IRC Clock.
+ * @{
+ */
+
+/*!
+ * @brief Initializes the SCG slow IRC clock.
+ *
+ * This function enables the SCG slow IRC clock according to the
+ * configuration.
+ *
+ * @param config   Pointer to the configuration structure.
+ * @retval kStatus_Success SIRC is initialized.
+ * @retval kStatus_SCG_Busy SIRC has been enabled and is used by system clock.
+ * @retval kStatus_ReadOnly SIRC control register is locked.
+ *
+ * @note This function can't detect whether the system OSC has been enabled and
+ * used by an IP.
+ */
+status_t CLOCK_InitSirc(const scg_sirc_config_t *config);
+
+/*!
+ * @brief De-initializes the SCG slow IRC.
+ *
+ * This function disables the SCG slow IRC.
+ *
+ * @retval kStatus_Success SIRC is deinitialized.
+ * @retval kStatus_SCG_Busy SIRC is used by system clock.
+ * @retval kStatus_ReadOnly SIRC control register is locked.
+ *
+ * @note This function can't detect whether the SIRC is used by an IP.
+ */
+status_t CLOCK_DeinitSirc(void);
+
+/*!
+ * @brief Set the asynchronous clock divider.
+ *
+ * @param asyncClk Which asynchronous clock to configure.
+ * @param divider The divider value to set.
+ *
+ * @note There might be glitch when changing the asynchronous divider, so make sure
+ * the asynchronous clock is not used while changing divider.
+ */
+static inline void CLOCK_SetSircAsyncClkDiv(scg_async_clk_t asyncClk, scg_async_clk_div_t divider)
+{
+    uint32_t reg = SCG->SIRCDIV;
+
+    switch (asyncClk)
+    {
+        case kSCG_AsyncDiv3Clk:
+            reg = (reg & ~SCG_SIRCDIV_SIRCDIV3_MASK) | SCG_SIRCDIV_SIRCDIV3(divider);
+            break;
+        case kSCG_AsyncDiv2Clk:
+            reg = (reg & ~SCG_SIRCDIV_SIRCDIV2_MASK) | SCG_SIRCDIV_SIRCDIV2(divider);
+            break;
+        default:
+            reg = (reg & ~SCG_SIRCDIV_SIRCDIV1_MASK) | SCG_SIRCDIV_SIRCDIV1(divider);
+            break;
+    }
+
+    SCG->SIRCDIV = reg;
+}
+
+/*!
+ * @brief Gets the SCG SIRC clock frequency.
+ *
+ * @return  Clock frequency; If the clock is invalid, returns 0.
+ */
+uint32_t CLOCK_GetSircFreq(void);
+
+/*!
+ * @brief Gets the SCG asynchronous clock frequency from the SIRC.
+ *
+ * @param type     The asynchronous clock type.
+ * @return  Clock frequency; If the clock is invalid, returns 0.
+ */
+uint32_t CLOCK_GetSircAsyncFreq(scg_async_clk_t type);
+
+/*!
+ * @brief Checks whether the SIRC clock is valid.
+ *
+ * @return  True if clock is valid, false if not.
+ */
+static inline bool CLOCK_IsSircValid(void)
+{
+    return (bool)(SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK);
+}
+/* @} */
+
+/*!
+ * @name SCG Fast IRC Clock.
+ * @{
+ */
+
+/*!
+ * @brief Initializes the SCG fast IRC clock.
+ *
+ * This function enables the SCG fast IRC clock according to the configuration.
+ *
+ * @param config   Pointer to the configuration structure.
+ * @retval kStatus_Success FIRC is initialized.
+ * @retval kStatus_SCG_Busy FIRC has been enabled and is used by the system clock.
+ * @retval kStatus_ReadOnly FIRC control register is locked.
+ *
+ * @note This function can't detect whether the FIRC has been enabled and
+ * used by an IP.
+ */
+status_t CLOCK_InitFirc(const scg_firc_config_t *config);
+
+/*!
+ * @brief De-initializes the SCG fast IRC.
+ *
+ * This function disables the SCG fast IRC.
+ *
+ * @retval kStatus_Success FIRC is deinitialized.
+ * @retval kStatus_SCG_Busy FIRC is used by the system clock.
+ * @retval kStatus_ReadOnly FIRC control register is locked.
+ *
+ * @note This function can't detect whether the FIRC is used by an IP.
+ */
+status_t CLOCK_DeinitFirc(void);
+
+/*!
+ * @brief Set the asynchronous clock divider.
+ *
+ * @param asyncClk Which asynchronous clock to configure.
+ * @param divider The divider value to set.
+ *
+ * @note There might be glitch when changing the asynchronous divider, so make sure
+ * the asynchronous clock is not used while changing divider.
+ */
+static inline void CLOCK_SetFircAsyncClkDiv(scg_async_clk_t asyncClk, scg_async_clk_div_t divider)
+{
+    uint32_t reg = SCG->FIRCDIV;
+
+    switch (asyncClk)
+    {
+        case kSCG_AsyncDiv3Clk:
+            reg = (reg & ~SCG_FIRCDIV_FIRCDIV3_MASK) | SCG_FIRCDIV_FIRCDIV3(divider);
+            break;
+        case kSCG_AsyncDiv2Clk:
+            reg = (reg & ~SCG_FIRCDIV_FIRCDIV2_MASK) | SCG_FIRCDIV_FIRCDIV2(divider);
+            break;
+        default:
+            reg = (reg & ~SCG_FIRCDIV_FIRCDIV1_MASK) | SCG_FIRCDIV_FIRCDIV1(divider);
+            break;
+    }
+
+    SCG->FIRCDIV = reg;
+}
+
+/*!
+ * @brief Gets the SCG FIRC clock frequency.
+ *
+ * @return  Clock frequency; If the clock is invalid, returns 0.
+ */
+uint32_t CLOCK_GetFircFreq(void);
+
+/*!
+ * @brief Gets the SCG asynchronous clock frequency from the FIRC.
+ *
+ * @param type     The asynchronous clock type.
+ * @return  Clock frequency; If the clock is invalid, returns 0.
+ */
+uint32_t CLOCK_GetFircAsyncFreq(scg_async_clk_t type);
+
+/*!
+ * @brief Checks whether the FIRC clock error occurs.
+ *
+ * @return  True if the error occurs, false if not.
+ */
+static inline bool CLOCK_IsFircErr(void)
+{
+    return (bool)(SCG->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK);
+}
+
+/*!
+ * @brief Clears the FIRC clock error.
+ */
+static inline void CLOCK_ClearFircErr(void)
+{
+    SCG->FIRCCSR |= SCG_FIRCCSR_FIRCERR_MASK;
+}
+
+/*!
+ * @brief Checks whether the FIRC clock is valid.
+ *
+ * @return  True if clock is valid, false if not.
+ */
+static inline bool CLOCK_IsFircValid(void)
+{
+    return (bool)(SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK);
+}
+/* @} */
+
+/*!
+ * @brief Gets the SCG RTC OSC clock frequency.
+ *
+ * @return  Clock frequency; If the clock is invalid, returns 0.
+ */
+uint32_t CLOCK_GetRtcOscFreq(void);
+
+/*!
+ * @brief Checks whether the RTC OSC clock error occurs.
+ *
+ * @return  True if error occurs, false if not.
+ */
+static inline bool CLOCK_IsRtcOscErr(void)
+{
+    return (bool)(SCG->ROSCCSR & SCG_ROSCCSR_ROSCERR_MASK);
+}
+
+/*!
+ * @brief Clears the RTC OSC clock error.
+ */
+static inline void CLOCK_ClearRtcOscErr(void)
+{
+    SCG->ROSCCSR |= SCG_ROSCCSR_ROSCERR_MASK;
+}
+
+/*!
+ * @brief Sets the RTC OSC monitor mode.
+ *
+ * This function sets the RTC OSC monitor mode. The mode can be disabled.
+ * It can generate an interrupt when the error is disabled, or reset when the error is detected.
+ *
+ * @param mode Monitor mode to set.
+ */
+static inline void CLOCK_SetRtcOscMonitorMode(scg_rosc_monitor_mode_t mode)
+{
+    uint32_t reg = SCG->ROSCCSR;
+
+    reg &= ~(SCG_ROSCCSR_ROSCCM_MASK | SCG_ROSCCSR_ROSCCMRE_MASK);
+
+    reg |= (uint32_t)mode;
+
+    SCG->ROSCCSR = reg;
+}
+
+/*!
+ * @brief Checks whether the RTC OSC clock is valid.
+ *
+ * @return  True if the clock is valid, false if not.
+ */
+static inline bool CLOCK_IsRtcOscValid(void)
+{
+    return (bool)(SCG->ROSCCSR & SCG_ROSCCSR_ROSCVLD_MASK);
+}
+/* @} */
+
+/*!
+ * @name SCG Low Power FLL Clock.
+ * @{
+ */
+/*!
+ * @brief Initializes the SCG LPFLL clock.
+ *
+ * This function enables the SCG LPFLL clock according to the configuration.
+ *
+ * @param config   Pointer to the configuration structure.
+ * @retval kStatus_Success LPFLL is initialized.
+ * @retval kStatus_SCG_Busy LPFLL has been enabled and is used by the system clock.
+ * @retval kStatus_ReadOnly LPFLL control register is locked.
+ *
+ * @note This function can't detect whether the LPFLL has been enabled and
+ * used by an IP.
+ */
+status_t CLOCK_InitLpFll(const scg_lpfll_config_t *config);
+
+/*!
+ * @brief De-initializes the SCG LPFLL.
+ *
+ * This function disables the SCG LPFLL.
+ *
+ * @retval kStatus_Success LPFLL is deinitialized.
+ * @retval kStatus_SCG_Busy LPFLL is used by the system clock.
+ * @retval kStatus_ReadOnly LPFLL control register is locked.
+ *
+ * @note This function can't detect whether the LPFLL is used by an IP.
+ */
+status_t CLOCK_DeinitLpFll(void);
+
+/*!
+ * @brief Set the asynchronous clock divider.
+ *
+ * @param asyncClk Which asynchronous clock to configure.
+ * @param divider The divider value to set.
+ *
+ * @note There might be glitch when changing the asynchronous divider, so make sure
+ * the asynchronous clock is not used while changing divider.
+ */
+static inline void CLOCK_SetLpFllAsyncClkDiv(scg_async_clk_t asyncClk, scg_async_clk_div_t divider)
+{
+    uint32_t reg = SCG->LPFLLDIV;
+
+    switch (asyncClk)
+    {
+        case kSCG_AsyncDiv2Clk:
+            reg = (reg & ~SCG_LPFLLDIV_LPFLLDIV2_MASK) | SCG_LPFLLDIV_LPFLLDIV2(divider);
+            break;
+        default:
+            reg = (reg & ~SCG_LPFLLDIV_LPFLLDIV1_MASK) | SCG_LPFLLDIV_LPFLLDIV1(divider);
+            break;
+    }
+
+    SCG->LPFLLDIV = reg;
+}
+
+/*!
+ * @brief Gets the SCG LPFLL clock frequency.
+ *
+ * @return  Clock frequency in Hz; If the clock is invalid, returns 0.
+ */
+uint32_t CLOCK_GetLpFllFreq(void);
+
+/*!
+ * @brief Gets the SCG asynchronous clock frequency from the LPFLL.
+ *
+ * @param type     The asynchronous clock type.
+ * @return  Clock frequency in Hz; If the clock is invalid, returns 0.
+ */
+uint32_t CLOCK_GetLpFllAsyncFreq(scg_async_clk_t type);
+
+/*!
+ * @brief Checks whether the LPFLL clock is valid.
+ *
+ * @return  True if the clock is valid, false if not.
+ */
+static inline bool CLOCK_IsLpFllValid(void)
+{
+    return (bool)(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK);
+}
+/* @} */
+
+/*!
+ * @name External clock frequency
+ * @{
+ */
+
+/*!
+ * @brief Sets the XTAL0 frequency based on board settings.
+ *
+ * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
+ */
+static inline void CLOCK_SetXtal0Freq(uint32_t freq)
+{
+    g_xtal0Freq = freq;
+}
+
+/*!
+ * @brief Sets the XTAL32 frequency based on board settings.
+ *
+ * @param freq The XTAL32/EXTAL32 input clock frequency in Hz.
+ */
+static inline void CLOCK_SetXtal32Freq(uint32_t freq)
+{
+    g_xtal32Freq = freq;
+}
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_CLOCK_H_ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_common.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_common.c
new file mode 100644
index 0000000..be4ce2a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_common.c
@@ -0,0 +1,117 @@
+/*
+* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+* All rights reserved.
+*
+* 
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+
+#ifndef NDEBUG
+#if (defined(__CC_ARM)) || (defined(__ICCARM__))
+void __aeabi_assert(const char *failedExpr, const char *file, int line)
+{
+    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
+    for (;;)
+    {
+        __BKPT(0);
+    }
+}
+#elif(defined(__GNUC__))
+void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
+{
+    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
+    for (;;)
+    {
+        __BKPT(0);
+    }
+}
+#endif /* (defined(__CC_ARM)) ||  (defined (__ICCARM__)) */
+#endif /* NDEBUG */
+
+#ifndef __GIC_PRIO_BITS
+#ifndef __riscv
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
+{
+/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM)
+    extern uint32_t Image$$VECTOR_ROM$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$Base[];
+    extern uint32_t Image$$RW_m_data$$Base[];
+
+#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
+#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
+#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+#elif defined(__GNUC__)
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+    uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif /* defined(__CC_ARM) */
+    uint32_t n;
+    uint32_t ret;
+    uint32_t irqMaskValue;
+
+    irqMaskValue = DisableGlobalIRQ();
+    if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
+    {
+        /* Copy the vector table from ROM to RAM */
+        for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
+        {
+            __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+        }
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_RAM;
+    }
+
+    ret = __VECTOR_RAM[irq + 16];
+    /* make sure the __VECTOR_RAM is noncachable */
+    __VECTOR_RAM[irq + 16] = irqHandler;
+
+    EnableGlobalIRQ(irqMaskValue);
+
+    return ret;
+}
+#endif
+#endif
+
+#ifndef QN908XC_SERIES
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+
+void EnableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t index = 0;
+    uint32_t intNumber = (uint32_t)interrupt;
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    SYSCON->STARTERSET[index] = 1u << intNumber;
+    EnableIRQ(interrupt); /* also enable interrupt at NVIC */
+}
+
+void DisableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t index = 0;
+    uint32_t intNumber = (uint32_t)interrupt;
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    DisableIRQ(interrupt); /* also disable interrupt at NVIC */
+    SYSCON->STARTERCLR[index] = 1u << intNumber;
+}
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+#endif /* QN908XC_SERIES */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_common.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_common.h
new file mode 100644
index 0000000..3aea499
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_common.h
@@ -0,0 +1,485 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_COMMON_H_
+#define _FSL_COMMON_H_
+
+#include 
+#include 
+#include 
+#include 
+
+#if defined(__ICCARM__)
+#include 
+#endif
+
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Construct a status code value from a group and code number. */
+#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
+
+/*! @brief Construct the version number for drivers. */
+#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief common driver version 2.0.0. */
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/* Debug console type definition. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U     /*!< No debug console.             */
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U     /*!< Debug console base on UART.   */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U   /*!< Debug console base on LPUART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U    /*!< Debug console base on LPSCI.  */
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U   /*!< Debug console base on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U    /*!< Debug console base on i.MX UART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U   /*!< Debug console base on LPC_USART. */
+
+/*! @brief Status group numbers. */
+enum _status_groups
+{
+    kStatusGroup_Generic = 0,                 /*!< Group number for generic status codes. */
+    kStatusGroup_FLASH = 1,                   /*!< Group number for FLASH status codes. */
+    kStatusGroup_LPSPI = 4,                   /*!< Group number for LPSPI status codes. */
+    kStatusGroup_FLEXIO_SPI = 5,              /*!< Group number for FLEXIO SPI status codes. */
+    kStatusGroup_DSPI = 6,                    /*!< Group number for DSPI status codes. */
+    kStatusGroup_FLEXIO_UART = 7,             /*!< Group number for FLEXIO UART status codes. */
+    kStatusGroup_FLEXIO_I2C = 8,              /*!< Group number for FLEXIO I2C status codes. */
+    kStatusGroup_LPI2C = 9,                   /*!< Group number for LPI2C status codes. */
+    kStatusGroup_UART = 10,                   /*!< Group number for UART status codes. */
+    kStatusGroup_I2C = 11,                    /*!< Group number for UART status codes. */
+    kStatusGroup_LPSCI = 12,                  /*!< Group number for LPSCI status codes. */
+    kStatusGroup_LPUART = 13,                 /*!< Group number for LPUART status codes. */
+    kStatusGroup_SPI = 14,                    /*!< Group number for SPI status code.*/
+    kStatusGroup_XRDC = 15,                   /*!< Group number for XRDC status code.*/
+    kStatusGroup_SEMA42 = 16,                 /*!< Group number for SEMA42 status code.*/
+    kStatusGroup_SDHC = 17,                   /*!< Group number for SDHC status code */
+    kStatusGroup_SDMMC = 18,                  /*!< Group number for SDMMC status code */
+    kStatusGroup_SAI = 19,                    /*!< Group number for SAI status code */
+    kStatusGroup_MCG = 20,                    /*!< Group number for MCG status codes. */
+    kStatusGroup_SCG = 21,                    /*!< Group number for SCG status codes. */
+    kStatusGroup_SDSPI = 22,                  /*!< Group number for SDSPI status codes. */
+    kStatusGroup_FLEXIO_I2S = 23,             /*!< Group number for FLEXIO I2S status codes */
+    kStatusGroup_FLEXIO_MCULCD = 24,          /*!< Group number for FLEXIO LCD status codes */
+    kStatusGroup_FLASHIAP = 25,               /*!< Group number for FLASHIAP status codes */
+    kStatusGroup_FLEXCOMM_I2C = 26,           /*!< Group number for FLEXCOMM I2C status codes */
+    kStatusGroup_I2S = 27,                    /*!< Group number for I2S status codes */
+    kStatusGroup_IUART = 28,                  /*!< Group number for IUART status codes */
+    kStatusGroup_CSI = 29,                    /*!< Group number for CSI status codes */
+    kStatusGroup_SDRAMC = 35,                 /*!< Group number for SDRAMC status codes. */
+    kStatusGroup_POWER = 39,                  /*!< Group number for POWER status codes. */
+    kStatusGroup_ENET = 40,                   /*!< Group number for ENET status codes. */
+    kStatusGroup_PHY = 41,                    /*!< Group number for PHY status codes. */
+    kStatusGroup_TRGMUX = 42,                 /*!< Group number for TRGMUX status codes. */
+    kStatusGroup_SMARTCARD = 43,              /*!< Group number for SMARTCARD status codes. */
+    kStatusGroup_LMEM = 44,                   /*!< Group number for LMEM status codes. */
+    kStatusGroup_QSPI = 45,                   /*!< Group number for QSPI status codes. */
+    kStatusGroup_DMA = 50,                    /*!< Group number for DMA status codes. */
+    kStatusGroup_EDMA = 51,                   /*!< Group number for EDMA status codes. */
+    kStatusGroup_DMAMGR = 52,                 /*!< Group number for DMAMGR status codes. */
+    kStatusGroup_FLEXCAN = 53,                /*!< Group number for FlexCAN status codes. */
+    kStatusGroup_LTC = 54,                    /*!< Group number for LTC status codes. */
+    kStatusGroup_FLEXIO_CAMERA = 55,          /*!< Group number for FLEXIO CAMERA status codes. */
+    kStatusGroup_LPC_SPI = 56,                /*!< Group number for LPC_SPI status codes. */
+    kStatusGroup_LPC_USART = 57,              /*!< Group number for LPC_USART status codes. */
+    kStatusGroup_DMIC = 58,                   /*!< Group number for DMIC status codes. */
+    kStatusGroup_SDIF = 59,                   /*!< Group number for SDIF status codes.*/
+    kStatusGroup_SPIFI = 60,                  /*!< Group number for SPIFI status codes. */
+    kStatusGroup_OTP = 61,                    /*!< Group number for OTP status codes. */
+    kStatusGroup_MCAN = 62,                   /*!< Group number for MCAN status codes. */
+    kStatusGroup_CAAM = 63,                   /*!< Group number for CAAM status codes. */
+    kStatusGroup_ECSPI = 64,                  /*!< Group number for ECSPI status codes. */
+    kStatusGroup_USDHC = 65,                  /*!< Group number for USDHC status codes.*/
+    kStatusGroup_LPC_I2C = 66,                /*!< Group number for LPC_I2C status codes.*/
+    kStatusGroup_ESAI = 69,                   /*!< Group number for ESAI status codes. */
+    kStatusGroup_FLEXSPI = 70,                /*!< Group number for FLEXSPI status codes. */
+    kStatusGroup_MMDC = 71,                   /*!< Group number for MMDC status codes. */
+    kStatusGroup_MICFIL = 72,                 /*!< Group number for MIC status codes. */
+    kStatusGroup_SDMA = 73,                   /*!< Group number for SDMA status codes. */
+    kStatusGroup_ICS = 74,                    /*!< Group number for ICS status codes. */
+    kStatusGroup_NOTIFIER = 98,               /*!< Group number for NOTIFIER status codes. */
+    kStatusGroup_DebugConsole = 99,           /*!< Group number for debug console status codes. */
+    kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */
+};
+
+/*! @brief Generic status return codes. */
+enum _generic_status
+{
+    kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
+    kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
+    kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
+    kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
+    kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
+    kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
+    kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
+};
+
+/*! @brief Type used for all status and error return values. */
+typedef int32_t status_t;
+
+/*
+ * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
+ * defined in previous of this file.
+ */
+#include "fsl_clock.h"
+
+/*
+ * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
+ */
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+     (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+#include "fsl_reset.h"
+#endif
+
+/*! @name Min/max macros */
+/* @{ */
+#if !defined(MIN)
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#endif
+
+#if !defined(MAX)
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#endif
+/* @} */
+
+/*! @brief Computes the number of elements in an array. */
+#if !defined(ARRAY_SIZE)
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#endif
+
+/*! @name UINT16_MAX/UINT32_MAX value */
+/* @{ */
+#if !defined(UINT16_MAX)
+#define UINT16_MAX ((uint16_t)-1)
+#endif
+
+#if !defined(UINT32_MAX)
+#define UINT32_MAX ((uint32_t)-1)
+#endif
+/* @} */
+
+/*! @name Timer utilities */
+/* @{ */
+/*! Macro to convert a microsecond period to raw count value */
+#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
+/*! Macro to convert a raw count value to microsecond */
+#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
+
+/*! Macro to convert a millisecond period to raw count value */
+#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
+/*! Macro to convert a raw count value to millisecond */
+#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
+/* @} */
+
+/*! @name Alignment variable definition macros */
+/* @{ */
+#if (defined(__ICCARM__))
+/**
+ * Workaround to disable MISRA C message suppress warnings for IAR compiler.
+ * http://supp.iar.com/Support/?note=24725
+ */
+_Pragma("diag_suppress=Pm120")
+#define SDK_PRAGMA(x) _Pragma(#x)
+    _Pragma("diag_error=Pm120")
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
+#endif
+#elif defined(__CC_ARM)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
+#endif
+#elif defined(__GNUC__)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))
+#endif
+#else
+#error Toolchain not supported
+#define SDK_ALIGN(var, alignbytes) var
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) var
+#endif
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) var
+#endif
+#endif
+
+/*! Macro to change a value to a given size aligned value */
+#define SDK_SIZEALIGN(var, alignbytes) \
+    ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))
+/* @} */
+
+/*! @name Non-cacheable region definition macros */
+/* @{ */
+#if (defined(__ICCARM__))
+#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
+#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
+#else
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+#endif
+#elif(defined(__CC_ARM))
+#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+    __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var
+#else
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var
+#endif
+#elif(defined(__GNUC__))
+/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
+ * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
+ */
+#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+    __attribute__((section("NonCacheable"))) var __attribute__((aligned(alignbytes)))
+#else
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
+#endif
+#else
+#error Toolchain not supported.
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
+#endif
+/* @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Enable specific interrupt.
+ *
+ * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ number.
+ * @retval kStatus_Success Interrupt enabled successfully
+ * @retval kStatus_Fail Failed to enable the interrupt
+ */
+static inline status_t EnableIRQ(IRQn_Type interrupt)
+{
+    if (NotAvail_IRQn == interrupt)
+    {
+        return kStatus_Fail;
+    }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+    if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+    {
+        return kStatus_Fail;
+    }
+#endif
+
+#if defined(FSL_FEATURE_SOC_EVENT_COUNT) && (FSL_FEATURE_SOC_EVENT_COUNT > 0)
+    EVENT_UNIT->INTPTEN |= (uint32_t)(1 << interrupt);
+    /* Read back to make sure write finished. */
+    (void)EVENT_UNIT->INTPTEN;
+#else
+#if defined(__GIC_PRIO_BITS)
+    GIC_EnableIRQ(interrupt);
+#else
+    NVIC_EnableIRQ(interrupt);
+#endif
+#endif
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Disable specific interrupt.
+ *
+ * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ number.
+ * @retval kStatus_Success Interrupt disabled successfully
+ * @retval kStatus_Fail Failed to disable the interrupt
+ */
+static inline status_t DisableIRQ(IRQn_Type interrupt)
+{
+    if (NotAvail_IRQn == interrupt)
+    {
+        return kStatus_Fail;
+    }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+    if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+    {
+        return kStatus_Fail;
+    }
+#endif
+
+#if defined(FSL_FEATURE_SOC_EVENT_COUNT) && (FSL_FEATURE_SOC_EVENT_COUNT > 0)
+    EVENT_UNIT->INTPTEN &= ~(uint32_t)(1 << interrupt);
+    /* Read back to make sure write finished. */
+    (void)EVENT_UNIT->INTPTEN;
+#else
+#if defined(__GIC_PRIO_BITS)
+    GIC_DisableIRQ(interrupt);
+#else
+    NVIC_DisableIRQ(interrupt);
+#endif
+#endif
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Disable the global IRQ
+ *
+ * Disable the global interrupt and return the current primask register. User is required to provided the primask
+ * register for the EnableGlobalIRQ().
+ *
+ * @return Current primask value.
+ */
+static inline uint32_t DisableGlobalIRQ(void)
+{
+#ifndef __riscv
+#if defined(CPSR_I_Msk)
+    uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
+
+    __disable_irq();
+
+    return cpsr;
+#else
+    uint32_t regPrimask = __get_PRIMASK();
+
+    __disable_irq();
+
+    return regPrimask;
+#endif
+#else
+    uint32_t mstatus;
+
+    __ASM volatile ("csrrci %0, mstatus, 8" : "=r"(mstatus));
+
+    return mstatus;
+#endif
+}
+
+/*!
+ * @brief Enaable the global IRQ
+ *
+ * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
+ * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
+ * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
+ *
+ * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
+ * DisableGlobalIRQ().
+ */
+static inline void EnableGlobalIRQ(uint32_t primask)
+{
+#ifndef __riscv
+#if defined(CPSR_I_Msk)
+    __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
+#else
+    __set_PRIMASK(primask);
+#endif
+#else
+    __ASM volatile ("csrw mstatus, %0" : : "r"(primask));
+#endif
+}
+
+/*!
+ * @brief install IRQ handler
+ *
+ * @param irq IRQ number
+ * @param irqHandler IRQ handler address
+ * @return The old IRQ handler address
+ */
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+/*!
+ * @brief Enable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Enable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
+ *
+ * @param interrupt The IRQ number.
+ */
+void EnableDeepSleepIRQ(IRQn_Type interrupt);
+
+/*!
+ * @brief Disable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Disable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
+ *
+ * @param interrupt The IRQ number.
+ */
+void DisableDeepSleepIRQ(IRQn_Type interrupt);
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_COMMON_H_ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_gpio.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_gpio.c
new file mode 100644
index 0000000..1fa8cc4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_gpio.c
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_gpio.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static PORT_Type *const s_portBases[] = PORT_BASE_PTRS;
+static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
+
+#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
+
+#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Array to map FGPIO instance number to clock name. */
+static const clock_ip_name_t s_fgpioClockName[] = FGPIO_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */
+
+#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
+
+/*******************************************************************************
+* Prototypes
+******************************************************************************/
+
+/*!
+* @brief Gets the GPIO instance according to the GPIO base
+*
+* @param base    GPIO peripheral base pointer(PTA, PTB, PTC, etc.)
+* @retval GPIO instance
+*/
+static uint32_t GPIO_GetInstance(GPIO_Type *base);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t GPIO_GetInstance(GPIO_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++)
+    {
+        if (s_gpioBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_gpioBases));
+
+    return instance;
+}
+
+void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
+{
+    assert(config);
+
+    if (config->pinDirection == kGPIO_DigitalInput)
+    {
+        base->PDDR &= ~(1U << pin);
+    }
+    else
+    {
+        GPIO_WritePinOutput(base, pin, config->outputLogic);
+        base->PDDR |= (1U << pin);
+    }
+}
+
+uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base)
+{
+    uint8_t instance;
+    PORT_Type *portBase;
+    instance = GPIO_GetInstance(base);
+    portBase = s_portBases[instance];
+    return portBase->ISFR;
+}
+
+void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask)
+{
+    uint8_t instance;
+    PORT_Type *portBase;
+    instance = GPIO_GetInstance(base);
+    portBase = s_portBases[instance];
+    portBase->ISFR = mask;
+}
+
+#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
+void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute)
+{
+    base->GACR = ((uint32_t)attribute << GPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB1_SHIFT) |
+                 ((uint32_t)attribute << GPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB3_SHIFT);
+}
+#endif
+
+#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS;
+
+/*******************************************************************************
+* Prototypes
+******************************************************************************/
+/*!
+* @brief Gets the FGPIO instance according to the GPIO base
+*
+* @param base    FGPIO peripheral base pointer(PTA, PTB, PTC, etc.)
+* @retval FGPIO instance
+*/
+static uint32_t FGPIO_GetInstance(FGPIO_Type *base);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t FGPIO_GetInstance(FGPIO_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_fgpioBases); instance++)
+    {
+        if (s_fgpioBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_fgpioBases));
+
+    return instance;
+}
+
+#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
+void FGPIO_Init(FGPIO_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Ungate FGPIO periphral clock */
+    CLOCK_EnableClock(s_fgpioClockName[FGPIO_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */
+
+void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
+{
+    assert(config);
+
+    if (config->pinDirection == kGPIO_DigitalInput)
+    {
+        base->PDDR &= ~(1U << pin);
+    }
+    else
+    {
+        FGPIO_WritePinOutput(base, pin, config->outputLogic);
+        base->PDDR |= (1U << pin);
+    }
+}
+
+uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base)
+{
+    uint8_t instance;
+    instance = FGPIO_GetInstance(base);
+    PORT_Type *portBase;
+    portBase = s_portBases[instance];
+    return portBase->ISFR;
+}
+
+void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask)
+{
+    uint8_t instance;
+    instance = FGPIO_GetInstance(base);
+    PORT_Type *portBase;
+    portBase = s_portBases[instance];
+    portBase->ISFR = mask;
+}
+
+#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER
+void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute)
+{
+    base->GACR = (attribute << FGPIO_GACR_ACB0_SHIFT) | (attribute << FGPIO_GACR_ACB1_SHIFT) |
+                 (attribute << FGPIO_GACR_ACB2_SHIFT) | (attribute << FGPIO_GACR_ACB3_SHIFT);
+}
+#endif
+
+#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_gpio.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_gpio.h
new file mode 100644
index 0000000..8fc17c7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_gpio.h
@@ -0,0 +1,427 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_GPIO_H_
+#define _FSL_GPIO_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup gpio
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief GPIO driver version 2.2.0. */
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
+/*@}*/
+
+/*! @brief GPIO direction definition */
+typedef enum _gpio_pin_direction
+{
+    kGPIO_DigitalInput = 0U,  /*!< Set current pin as digital input*/
+    kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
+} gpio_pin_direction_t;
+
+#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
+/*! @brief GPIO checker attribute */
+typedef enum _gpio_checker_attribute
+{
+    kGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW =
+        0x00U, /*!< User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW =
+        0x01U, /*!< User nonsecure:Read;       User Secure:Read+Write; Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW =
+        0x02U, /*!< User nonsecure:None;       User Secure:Read+Write; Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW =
+        0x03U, /*!< User nonsecure:Read;       User Secure:Read;       Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW =
+        0x04U, /*!< User nonsecure:None;       User Secure:Read;       Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW =
+        0x05U, /*!< User nonsecure:None;       User Secure:None;       Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureNUsersecureNPrivilegedsecureR =
+        0x06U, /*!< User nonsecure:None;       User Secure:None;       Privileged Secure:Read */
+    kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN =
+        0x07U, /*!< User nonsecure:None;       User Secure:None;       Privileged Secure:None */
+    kGPIO_IgnoreAttributeCheck = 0x80U, /*!< Ignores the attribute check */
+} gpio_checker_attribute_t;
+#endif
+
+/*!
+ * @brief The GPIO pin configuration structure.
+ *
+ * Each pin can only be configured as either an output pin or an input pin at a time.
+ * If configured as an input pin, leave the outputConfig unused.
+ * Note that in some use cases, the corresponding port property should be configured in advance
+ *        with the PORT_SetPinConfig().
+ */
+typedef struct _gpio_pin_config
+{
+    gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
+    /* Output configurations; ignore if configured as an input pin */
+    uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */
+} gpio_pin_config_t;
+
+/*! @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @addtogroup gpio_driver
+ * @{
+ */
+
+/*! @name GPIO Configuration */
+/*@{*/
+
+/*!
+ * @brief Initializes a GPIO pin used by the board.
+ *
+ * To initialize the GPIO, define a pin configuration, as either input or output, in the user file.
+ * Then, call the GPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or an output pin configuration.
+ * @code
+ * // Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * //Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * @endcode
+ *
+ * @param base   GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param pin    GPIO port pin number
+ * @param config GPIO pin configuration pointer
+ */
+void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
+
+/*@}*/
+
+/*! @name GPIO Output Operations */
+/*@{*/
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0.
+ *
+ * @param base    GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param pin     GPIO pin number
+ * @param output  GPIO pin output logic level.
+ *        - 0: corresponding pin output low-logic level.
+ *        - 1: corresponding pin output high-logic level.
+ */
+static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output)
+{
+    if (output == 0U)
+    {
+        base->PCOR = 1U << pin;
+    }
+    else
+    {
+        base->PSOR = 1U << pin;
+    }
+}
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 1.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask)
+{
+    base->PSOR = mask;
+}
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 0.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask)
+{
+    base->PCOR = mask;
+}
+
+/*!
+ * @brief Reverses the current output logic of the multiple GPIO pins.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask)
+{
+    base->PTOR = mask;
+}
+/*@}*/
+
+/*! @name GPIO Input Operations */
+/*@{*/
+
+/*!
+ * @brief Reads the current input value of the GPIO port.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param pin     GPIO pin number
+ * @retval GPIO port input value
+ *        - 0: corresponding pin input low-logic level.
+ *        - 1: corresponding pin input high-logic level.
+ */
+static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin)
+{
+    return (((base->PDIR) >> pin) & 0x01U);
+}
+/*@}*/
+
+/*! @name GPIO Interrupt */
+/*@{*/
+
+/*!
+ * @brief Reads the GPIO port interrupt status flag.
+ *
+ * If a pin is configured to generate the DMA request, the corresponding flag
+ * is cleared automatically at the completion of the requested DMA transfer.
+ * Otherwise, the flag remains set until a logic one is written to that flag.
+ * If configured for a level sensitive interrupt that remains asserted, the flag
+ * is set again immediately.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @retval The current GPIO port interrupt status flag, for example, 0x00010001 means the
+ *         pin 0 and 17 have the interrupt.
+ */
+uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base);
+
+/*!
+ * @brief Clears multiple GPIO pin interrupt status flags.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask);
+
+#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
+/*!
+ * @brief The GPIO module supports a device-specific number of data ports, organized as 32-bit
+ * words. Each 32-bit data port includes a GACR register, which defines the byte-level
+ * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data
+ * bytes in the GACR follow a standard little endian
+ * data convention.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute);
+#endif
+
+/*@}*/
+/*! @} */
+
+/*!
+ * @addtogroup fgpio_driver
+ * @{
+ */
+
+/*
+ * Introduces the FGPIO feature.
+ *
+ * The FGPIO features are only support on some Kinetis MCUs. The FGPIO registers are aliased to the IOPORT
+ * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and
+ * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO.
+ */
+
+#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
+
+/*! @name FGPIO Configuration */
+/*@{*/
+
+/*!
+ * @brief Initializes the FGPIO peripheral.
+ *
+ * This function ungates the FGPIO clock.
+ *
+ * @param base   FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ */
+ void FGPIO_Init(FGPIO_Type *base);
+
+/*!
+ * @brief Initializes a FGPIO pin used by the board.
+ *
+ * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file.
+ * Then, call the FGPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or an output pin configuration:
+ * @code
+ * // Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * //Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * @endcode
+ *
+ * @param base   FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param pin    FGPIO port pin number
+ * @param config FGPIO pin configuration pointer
+ */
+void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
+
+/*@}*/
+
+/*! @name FGPIO Output Operations */
+/*@{*/
+
+/*!
+ * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0.
+ *
+ * @param base    FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param pin     FGPIO pin number
+ * @param output  FGPIOpin output logic level.
+ *        - 0: corresponding pin output low-logic level.
+ *        - 1: corresponding pin output high-logic level.
+ */
+static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output)
+{
+    if (output == 0U)
+    {
+        base->PCOR = 1 << pin;
+    }
+    else
+    {
+        base->PSOR = 1 << pin;
+    }
+}
+
+/*!
+ * @brief Sets the output level of the multiple FGPIO pins to the logic 1.
+ *
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
+ */
+static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask)
+{
+    base->PSOR = mask;
+}
+
+/*!
+ * @brief Sets the output level of the multiple FGPIO pins to the logic 0.
+ *
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
+ */
+static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask)
+{
+    base->PCOR = mask;
+}
+
+/*!
+ * @brief Reverses the current output logic of the multiple FGPIO pins.
+ *
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
+ */
+static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask)
+{
+    base->PTOR = mask;
+}
+/*@}*/
+
+/*! @name FGPIO Input Operations */
+/*@{*/
+
+/*!
+ * @brief Reads the current input value of the FGPIO port.
+ *
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param pin  FGPIO pin number
+ * @retval FGPIO port input value
+ *        - 0: corresponding pin input low-logic level.
+ *        - 1: corresponding pin input high-logic level.
+ */
+static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin)
+{
+    return (((base->PDIR) >> pin) & 0x01U);
+}
+/*@}*/
+
+/*! @name FGPIO Interrupt */
+/*@{*/
+
+/*!
+ * @brief Reads the FGPIO port interrupt status flag.
+ *
+ * If a pin is configured to generate the DMA request, the corresponding flag
+ * is cleared automatically at the completion of the requested DMA transfer.
+ * Otherwise, the flag remains set until a logic one is written to that flag.
+ * If configured for a level-sensitive interrupt that remains asserted, the flag
+ * is set again immediately.
+ *
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the
+ *         pin 0 and 17 have the interrupt.
+ */
+uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base);
+
+/*!
+ * @brief Clears the multiple FGPIO pin interrupt status flag.
+ *
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
+ */
+void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask);
+
+#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
+/*!
+ * @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit
+ * words. Each 32-bit data port includes a GACR register, which defines the byte-level
+ * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data
+ * bytes in the GACR follow a standard little endian
+ * data convention.
+ *
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
+ */
+void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute);
+#endif
+
+/*@}*/
+
+#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* _FSL_GPIO_H_*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart.c
new file mode 100644
index 0000000..c65a934
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart.c
@@ -0,0 +1,1459 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_lpuart.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* LPUART transfer state. */
+enum _lpuart_transfer_states
+{
+    kLPUART_TxIdle, /*!< TX idle. */
+    kLPUART_TxBusy, /*!< TX busy. */
+    kLPUART_RxIdle, /*!< RX idle. */
+    kLPUART_RxBusy  /*!< RX busy. */
+};
+
+/* Typedef for interrupt handler. */
+typedef void (*lpuart_isr_t)(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get the LPUART instance from peripheral base address.
+ *
+ * @param base LPUART peripheral base address.
+ * @return LPUART instance.
+ */
+uint32_t LPUART_GetInstance(LPUART_Type *base);
+
+/*!
+ * @brief Get the length of received data in RX ring buffer.
+ *
+ * @userData handle LPUART handle pointer.
+ * @return Length of received data in RX ring buffer.
+ */
+static size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief Check whether the RX ring buffer is full.
+ *
+ * @userData handle LPUART handle pointer.
+ * @retval true  RX ring buffer is full.
+ * @retval false RX ring buffer is not full.
+ */
+static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief Write to TX register using non-blocking method.
+ *
+ * This function writes data to the TX register directly, upper layer must make
+ * sure the TX register is empty or TX FIFO has empty room before calling this function.
+ *
+ * @note This function does not check whether all the data has been sent out to bus,
+ * so before disable TX, check kLPUART_TransmissionCompleteFlag to ensure the TX is
+ * finished.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start addresss of the data to write.
+ * @param length Size of the buffer to be sent.
+ */
+static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
+
+/*!
+ * @brief Read RX register using non-blocking method.
+ *
+ * This function reads data from the TX register directly, upper layer must make
+ * sure the RX register is full or TX FIFO has data before calling this function.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start addresss of the buffer to store the received data.
+ * @param length Size of the buffer.
+ */
+static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Array of LPUART handle. */
+static lpuart_handle_t *s_lpuartHandle[FSL_FEATURE_SOC_LPUART_COUNT];
+/* Array of LPUART peripheral base address. */
+static LPUART_Type *const s_lpuartBases[] = LPUART_BASE_PTRS;
+/* Array of LPUART IRQ number. */
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+static const IRQn_Type s_lpuartRxIRQ[] = LPUART_RX_IRQS;
+static const IRQn_Type s_lpuartTxIRQ[] = LPUART_TX_IRQS;
+#else
+static const IRQn_Type s_lpuartIRQ[] = LPUART_RX_TX_IRQS;
+#endif
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/* Array of LPUART clock name. */
+static const clock_ip_name_t s_lpuartClock[] = LPUART_CLOCKS;
+
+#if defined(LPUART_PERIPH_CLOCKS)
+/* Array of LPUART functional clock name. */
+static const clock_ip_name_t s_lpuartPeriphClocks[] = LPUART_PERIPH_CLOCKS;
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/* LPUART ISR for transactional APIs. */
+static lpuart_isr_t s_lpuartIsr;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+uint32_t LPUART_GetInstance(LPUART_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_lpuartBases); instance++)
+    {
+        if (s_lpuartBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_lpuartBases));
+
+    return instance;
+}
+
+static size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle)
+{
+    assert(handle);
+
+    size_t size;
+
+    if (handle->rxRingBufferTail > handle->rxRingBufferHead)
+    {
+        size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail);
+    }
+    else
+    {
+        size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail);
+    }
+
+    return size;
+}
+
+static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle)
+{
+    assert(handle);
+
+    bool full;
+
+    if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U))
+    {
+        full = true;
+    }
+    else
+    {
+        full = false;
+    }
+    return full;
+}
+
+static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
+{
+    assert(data);
+
+    size_t i;
+
+    /* The Non Blocking write data API assume user have ensured there is enough space in
+    peripheral to write. */
+    for (i = 0; i < length; i++)
+    {
+        base->DATA = data[i];
+    }
+}
+
+static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length)
+{
+    assert(data);
+
+    size_t i;
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    uint32_t ctrl = base->CTRL;
+    bool isSevenDataBits =
+        ((ctrl & LPUART_CTRL_M7_MASK) ||
+         ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
+#endif
+
+    /* The Non Blocking read data API assume user have ensured there is enough space in
+    peripheral to write. */
+    for (i = 0; i < length; i++)
+    {
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+        if (isSevenDataBits)
+        {
+            data[i] = (base->DATA & 0x7F);
+        }
+        else
+        {
+            data[i] = base->DATA;
+        }
+#else
+        data[i] = base->DATA;
+#endif
+    }
+}
+
+status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz)
+{
+    assert(config);
+    assert(config->baudRate_Bps);
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->txFifoWatermark);
+    assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->rxFifoWatermark);
+#endif
+
+    uint32_t temp;
+    uint16_t sbr, sbrTemp;
+    uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff;
+
+    /* This LPUART instantiation uses a slightly different baud rate calculation
+     * The idea is to use the best OSR (over-sampling rate) possible
+     * Note, OSR is typically hard-set to 16 in other LPUART instantiations
+     * loop to find the best OSR value possible, one that generates minimum baudDiff
+     * iterate through the rest of the supported values of OSR */
+
+    baudDiff = config->baudRate_Bps;
+    osr = 0;
+    sbr = 0;
+    for (osrTemp = 4; osrTemp <= 32; osrTemp++)
+    {
+        /* calculate the temporary sbr value   */
+        sbrTemp = (srcClock_Hz / (config->baudRate_Bps * osrTemp));
+        /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
+        if (sbrTemp == 0)
+        {
+            sbrTemp = 1;
+        }
+        /* Calculate the baud rate based on the temporary OSR and SBR values */
+        calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp));
+
+        tempDiff = calculatedBaud - config->baudRate_Bps;
+
+        /* Select the better value between srb and (sbr + 1) */
+        if (tempDiff > (config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)))))
+        {
+            tempDiff = config->baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)));
+            sbrTemp++;
+        }
+
+        if (tempDiff <= baudDiff)
+        {
+            baudDiff = tempDiff;
+            osr = osrTemp; /* update and store the best OSR value calculated */
+            sbr = sbrTemp; /* update store the best SBR value calculated */
+        }
+    }
+
+    /* Check to see if actual baud rate is within 3% of desired baud rate
+     * based on the best calculate OSR value */
+    if (baudDiff > ((config->baudRate_Bps / 100) * 3))
+    {
+        /* Unacceptable baud rate difference of more than 3%*/
+        return kStatus_LPUART_BaudrateNotSupport;
+    }
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+
+    uint32_t instance = LPUART_GetInstance(base);
+
+    /* Enable lpuart clock */
+    CLOCK_EnableClock(s_lpuartClock[instance]);
+#if defined(LPUART_PERIPH_CLOCKS)
+    CLOCK_EnableClock(s_lpuartPeriphClocks[instance]);
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL
+    /*Reset all internal logic and registers, except the Global Register */
+    LPUART_SoftwareReset(base);
+#else
+    /* Disable LPUART TX RX before setting. */
+    base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
+#endif
+
+    temp = base->BAUD;
+
+    /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
+     * If so, then "BOTHEDGE" sampling must be turned on */
+    if ((osr > 3) && (osr < 8))
+    {
+        temp |= LPUART_BAUD_BOTHEDGE_MASK;
+    }
+
+    /* program the osr value (bit value is one less than actual value) */
+    temp &= ~LPUART_BAUD_OSR_MASK;
+    temp |= LPUART_BAUD_OSR(osr - 1);
+
+    /* write the sbr value to the BAUD registers */
+    temp &= ~LPUART_BAUD_SBR_MASK;
+    base->BAUD = temp | LPUART_BAUD_SBR(sbr);
+
+    /* Set bit count and parity mode. */
+    base->BAUD &= ~LPUART_BAUD_M10_MASK;
+
+    temp = base->CTRL &
+           ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK |
+             LPUART_CTRL_IDLECFG_MASK);
+
+    temp |=
+        (uint8_t)config->parityMode | LPUART_CTRL_IDLECFG(config->rxIdleConfig) | LPUART_CTRL_ILT(config->rxIdleType);
+
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    if (kLPUART_SevenDataBits == config->dataBitsCount)
+    {
+        if (kLPUART_ParityDisabled != config->parityMode)
+        {
+            temp &= ~LPUART_CTRL_M7_MASK; /* Seven data bits and one parity bit */
+        }
+        else
+        {
+            temp |= LPUART_CTRL_M7_MASK;
+        }
+    }
+    else
+#endif
+    {
+        if (kLPUART_ParityDisabled != config->parityMode)
+        {
+            temp |= LPUART_CTRL_M_MASK; /* Eight data bits and one parity bit */
+        }
+    }
+
+    base->CTRL = temp;
+
+#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
+    /* set stop bit per char */
+    temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK;
+    base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount);
+#endif
+
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    /* Set tx/rx WATER watermark
+       Note:
+       Take care of the RX FIFO, RX interrupt request only assert when received bytes
+       equal or more than RX water mark, there is potential issue if RX water
+       mark larger than 1.
+       For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and
+       5 bytes are received. the last byte will be saved in FIFO but not trigger
+       RX interrupt because the water mark is 2.
+     */
+    base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16) | config->txFifoWatermark);
+
+    /* Enable tx/rx FIFO */
+    base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK);
+
+    /* Flush FIFO */
+    base->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK);
+#endif
+
+    /* Clear all status flags */
+    temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
+            LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
+
+#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
+    temp |= LPUART_STAT_LBKDIF_MASK;
+#endif
+
+#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
+    temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK);
+#endif
+
+#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
+    /* Set the CTS configuration/TX CTS source. */
+    base->MODIR |= LPUART_MODIR_TXCTSC(config->txCtsConfig) | LPUART_MODIR_TXCTSSRC(config->txCtsSource);
+    if (config->enableRxRTS)
+    {
+        /* Enable the receiver RTS(request-to-send) function. */
+        base->MODIR |= LPUART_MODIR_RXRTSE_MASK;
+    }
+    if (config->enableTxCTS)
+    {
+        /* Enable the CTS(clear-to-send) function. */
+        base->MODIR |= LPUART_MODIR_TXCTSE_MASK;
+    }
+#endif
+
+    /* Set data bits order. */
+    if (config->isMsb)
+    {
+        temp |= LPUART_STAT_MSBF_MASK;
+    }
+    else
+    {
+        temp &= ~LPUART_STAT_MSBF_MASK;
+    }
+
+    base->STAT |= temp;
+
+    /* Enable TX/RX base on configure structure. */
+    temp = base->CTRL;
+    if (config->enableTx)
+    {
+        temp |= LPUART_CTRL_TE_MASK;
+    }
+
+    if (config->enableRx)
+    {
+        temp |= LPUART_CTRL_RE_MASK;
+    }
+
+    base->CTRL = temp;
+
+    return kStatus_Success;
+}
+void LPUART_Deinit(LPUART_Type *base)
+{
+    uint32_t temp;
+
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    /* Wait tx FIFO send out*/
+    while (0 != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT))
+    {
+    }
+#endif
+    /* Wait last char shoft out */
+    while (0 == (base->STAT & LPUART_STAT_TC_MASK))
+    {
+    }
+
+    /* Clear all status flags */
+    temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
+            LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
+
+#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
+    temp |= LPUART_STAT_LBKDIF_MASK;
+#endif
+
+#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
+    temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK);
+#endif
+
+    base->STAT |= temp;
+
+    /* Disable the module. */
+    base->CTRL = 0;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    uint32_t instance = LPUART_GetInstance(base);
+
+    /* Disable lpuart clock */
+    CLOCK_DisableClock(s_lpuartClock[instance]);
+
+#if defined(LPUART_PERIPH_CLOCKS)
+    CLOCK_DisableClock(s_lpuartPeriphClocks[instance]);
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void LPUART_GetDefaultConfig(lpuart_config_t *config)
+{
+    assert(config);
+
+    config->baudRate_Bps = 115200U;
+    config->parityMode = kLPUART_ParityDisabled;
+    config->dataBitsCount = kLPUART_EightDataBits;
+    config->isMsb = false;
+#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
+    config->stopBitCount = kLPUART_OneStopBit;
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    config->txFifoWatermark = 0;
+    config->rxFifoWatermark = 0;
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
+    config->enableRxRTS = false;
+    config->enableTxCTS = false;
+    config->txCtsConfig = kLPUART_CtsSampleAtStart;
+    config->txCtsSource = kLPUART_CtsSourcePin;
+#endif
+    config->rxIdleType = kLPUART_IdleTypeStartBit;
+    config->rxIdleConfig = kLPUART_IdleCharacter1;
+    config->enableTx = false;
+    config->enableRx = false;
+}
+
+status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
+{
+    assert(baudRate_Bps);
+
+    uint32_t temp, oldCtrl;
+    uint16_t sbr, sbrTemp;
+    uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff;
+
+    /* This LPUART instantiation uses a slightly different baud rate calculation
+     * The idea is to use the best OSR (over-sampling rate) possible
+     * Note, OSR is typically hard-set to 16 in other LPUART instantiations
+     * loop to find the best OSR value possible, one that generates minimum baudDiff
+     * iterate through the rest of the supported values of OSR */
+
+    baudDiff = baudRate_Bps;
+    osr = 0;
+    sbr = 0;
+    for (osrTemp = 4; osrTemp <= 32; osrTemp++)
+    {
+        /* calculate the temporary sbr value   */
+        sbrTemp = (srcClock_Hz / (baudRate_Bps * osrTemp));
+        /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
+        if (sbrTemp == 0)
+        {
+            sbrTemp = 1;
+        }
+        /* Calculate the baud rate based on the temporary OSR and SBR values */
+        calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp));
+
+        tempDiff = calculatedBaud - baudRate_Bps;
+
+        /* Select the better value between srb and (sbr + 1) */
+        if (tempDiff > (baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)))))
+        {
+            tempDiff = baudRate_Bps - (srcClock_Hz / (osrTemp * (sbrTemp + 1)));
+            sbrTemp++;
+        }
+
+        if (tempDiff <= baudDiff)
+        {
+            baudDiff = tempDiff;
+            osr = osrTemp; /* update and store the best OSR value calculated */
+            sbr = sbrTemp; /* update store the best SBR value calculated */
+        }
+    }
+
+    /* Check to see if actual baud rate is within 3% of desired baud rate
+     * based on the best calculate OSR value */
+    if (baudDiff < ((baudRate_Bps / 100) * 3))
+    {
+        /* Store CTRL before disable Tx and Rx */
+        oldCtrl = base->CTRL;
+
+        /* Disable LPUART TX RX before setting. */
+        base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
+
+        temp = base->BAUD;
+
+        /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
+         * If so, then "BOTHEDGE" sampling must be turned on */
+        if ((osr > 3) && (osr < 8))
+        {
+            temp |= LPUART_BAUD_BOTHEDGE_MASK;
+        }
+
+        /* program the osr value (bit value is one less than actual value) */
+        temp &= ~LPUART_BAUD_OSR_MASK;
+        temp |= LPUART_BAUD_OSR(osr - 1);
+
+        /* write the sbr value to the BAUD registers */
+        temp &= ~LPUART_BAUD_SBR_MASK;
+        base->BAUD = temp | LPUART_BAUD_SBR(sbr);
+
+        /* Restore CTRL. */
+        base->CTRL = oldCtrl;
+
+        return kStatus_Success;
+    }
+    else
+    {
+        /* Unacceptable baud rate difference of more than 3%*/
+        return kStatus_LPUART_BaudrateNotSupport;
+    }
+}
+
+void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)
+{
+    base->BAUD |= ((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK));
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) |
+                 ((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
+#endif
+    mask &= 0xFFFFFF00U;
+    base->CTRL |= mask;
+}
+
+void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask)
+{
+    base->BAUD &= ~((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK));
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) &
+                 ~((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
+#endif
+    mask &= 0xFFFFFF00U;
+    base->CTRL &= ~mask;
+}
+
+uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base)
+{
+    uint32_t temp;
+    temp = (base->BAUD & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)) >> 8;
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    temp |= (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)) >> 8;
+#endif
+    temp |= (base->CTRL & 0xFF0C000);
+
+    return temp;
+}
+
+uint32_t LPUART_GetStatusFlags(LPUART_Type *base)
+{
+    uint32_t temp;
+    temp = base->STAT;
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    temp |= (base->FIFO &
+             (LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >>
+            16;
+#endif
+    return temp;
+}
+
+status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)
+{
+    uint32_t temp;
+    status_t status;
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    temp = (uint32_t)base->FIFO;
+    temp &= (uint32_t)(~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK));
+    temp |= (mask << 16) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK);
+    base->FIFO = temp;
+#endif
+    temp = (uint32_t)base->STAT;
+#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
+    temp &= (uint32_t)(~(LPUART_STAT_LBKDIF_MASK));
+    temp |= mask & LPUART_STAT_LBKDIF_MASK;
+#endif
+    temp &= (uint32_t)(~(LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
+                         LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK));
+    temp |= mask & (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
+                    LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
+#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
+    temp &= (uint32_t)(~(LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK));
+    temp |= mask & (LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK);
+#endif
+    base->STAT = temp;
+    /* If some flags still pending. */
+    if (mask & LPUART_GetStatusFlags(base))
+    {
+        /* Some flags can only clear or set by the hardware itself, these flags are: kLPUART_TxDataRegEmptyFlag,
+        kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag,
+        kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag,
+        kLPUART_TxFifoEmptyFlag, kLPUART_RxFifoEmptyFlag. */
+        status = kStatus_LPUART_FlagCannotClearManually; /* flags can not clear manually */
+    }
+    else
+    {
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
+{
+    assert(data);
+
+    /* This API can only ensure that the data is written into the data buffer but can't
+    ensure all data in the data buffer are sent into the transmit shift buffer. */
+    while (length--)
+    {
+        while (!(base->STAT & LPUART_STAT_TDRE_MASK))
+        {
+        }
+        base->DATA = *(data++);
+    }
+}
+
+status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length)
+{
+    assert(data);
+
+    uint32_t statusFlag;
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    uint32_t ctrl = base->CTRL;
+    bool isSevenDataBits =
+        ((ctrl & LPUART_CTRL_M7_MASK) ||
+         ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
+#endif
+
+    while (length--)
+    {
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+        while (0 == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT))
+#else
+        while (!(base->STAT & LPUART_STAT_RDRF_MASK))
+#endif
+        {
+            statusFlag = LPUART_GetStatusFlags(base);
+
+            if (statusFlag & kLPUART_RxOverrunFlag)
+            {
+                LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag);
+                return kStatus_LPUART_RxHardwareOverrun;
+            }
+
+            if (statusFlag & kLPUART_NoiseErrorFlag)
+            {
+                LPUART_ClearStatusFlags(base, kLPUART_NoiseErrorFlag);
+                return kStatus_LPUART_NoiseError;
+            }
+
+            if (statusFlag & kLPUART_FramingErrorFlag)
+            {
+                LPUART_ClearStatusFlags(base, kLPUART_FramingErrorFlag);
+                return kStatus_LPUART_FramingError;
+            }
+
+            if (statusFlag & kLPUART_ParityErrorFlag)
+            {
+                LPUART_ClearStatusFlags(base, kLPUART_ParityErrorFlag);
+                return kStatus_LPUART_ParityError;
+            }
+        }
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+        if (isSevenDataBits)
+        {
+            *(data++) = (base->DATA & 0x7F);
+        }
+        else
+        {
+            *(data++) = base->DATA;
+        }
+#else
+        *(data++) = base->DATA;
+#endif
+    }
+
+    return kStatus_Success;
+}
+
+void LPUART_TransferCreateHandle(LPUART_Type *base,
+                                 lpuart_handle_t *handle,
+                                 lpuart_transfer_callback_t callback,
+                                 void *userData)
+{
+    assert(handle);
+
+    uint32_t instance;
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    uint32_t ctrl = base->CTRL;
+    bool isSevenDataBits =
+        ((ctrl & LPUART_CTRL_M7_MASK) ||
+         ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
+#endif
+
+    /* Zero the handle. */
+    memset(handle, 0, sizeof(lpuart_handle_t));
+
+    /* Set the TX/RX state. */
+    handle->rxState = kLPUART_RxIdle;
+    handle->txState = kLPUART_TxIdle;
+
+    /* Set the callback and user data. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    /* Initial seven data bits flag */
+    handle->isSevenDataBits = isSevenDataBits;
+#endif
+
+    /* Get instance from peripheral base address. */
+    instance = LPUART_GetInstance(base);
+
+    /* Save the handle in global variables to support the double weak mechanism. */
+    s_lpuartHandle[instance] = handle;
+
+    s_lpuartIsr = LPUART_TransferHandleIRQ;
+
+/* Enable interrupt in NVIC. */
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+    EnableIRQ(s_lpuartRxIRQ[instance]);
+    EnableIRQ(s_lpuartTxIRQ[instance]);
+#else
+    EnableIRQ(s_lpuartIRQ[instance]);
+#endif
+}
+
+void LPUART_TransferStartRingBuffer(LPUART_Type *base,
+                                    lpuart_handle_t *handle,
+                                    uint8_t *ringBuffer,
+                                    size_t ringBufferSize)
+{
+    assert(handle);
+    assert(ringBuffer);
+
+    /* Setup the ring buffer address */
+    handle->rxRingBuffer = ringBuffer;
+    handle->rxRingBufferSize = ringBufferSize;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+
+    /* Enable the interrupt to accept the data when user need the ring buffer. */
+    LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
+}
+
+void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle)
+{
+    assert(handle);
+
+    if (handle->rxState == kLPUART_RxIdle)
+    {
+        LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
+    }
+
+    handle->rxRingBuffer = NULL;
+    handle->rxRingBufferSize = 0U;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+}
+
+status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer)
+{
+    assert(handle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
+
+    status_t status;
+
+    /* Return error if current TX busy. */
+    if (kLPUART_TxBusy == handle->txState)
+    {
+        status = kStatus_LPUART_TxBusy;
+    }
+    else
+    {
+        handle->txData = xfer->data;
+        handle->txDataSize = xfer->dataSize;
+        handle->txDataSizeAll = xfer->dataSize;
+        handle->txState = kLPUART_TxBusy;
+
+        /* Enable transmiter interrupt. */
+        LPUART_EnableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle)
+{
+    assert(handle);
+
+    LPUART_DisableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_TransmissionCompleteInterruptEnable);
+
+    handle->txDataSize = 0;
+    handle->txState = kLPUART_TxIdle;
+}
+
+status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
+{
+    assert(handle);
+    assert(count);
+
+    if (kLPUART_TxIdle == handle->txState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->txDataSizeAll - handle->txDataSize;
+
+    return kStatus_Success;
+}
+
+status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
+                                           lpuart_handle_t *handle,
+                                           lpuart_transfer_t *xfer,
+                                           size_t *receivedBytes)
+{
+    assert(handle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
+
+    uint32_t i;
+    status_t status;
+    /* How many bytes to copy from ring buffer to user memory. */
+    size_t bytesToCopy = 0U;
+    /* How many bytes to receive. */
+    size_t bytesToReceive;
+    /* How many bytes currently have received. */
+    size_t bytesCurrentReceived;
+
+    /* How to get data:
+       1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
+          to lpuart handle, enable interrupt to store received data to xfer->data. When
+          all data received, trigger callback.
+       2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
+          If there are enough data in ring buffer, copy them to xfer->data and return.
+          If there are not enough data in ring buffer, copy all of them to xfer->data,
+          save the xfer->data remained empty space to lpuart handle, receive data
+          to this empty space and trigger callback when finished. */
+
+    if (kLPUART_RxBusy == handle->rxState)
+    {
+        status = kStatus_LPUART_RxBusy;
+    }
+    else
+    {
+        bytesToReceive = xfer->dataSize;
+        bytesCurrentReceived = 0;
+
+        /* If RX ring buffer is used. */
+        if (handle->rxRingBuffer)
+        {
+            /* Disable LPUART RX IRQ, protect ring buffer. */
+            LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable);
+
+            /* How many bytes in RX ring buffer currently. */
+            bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle);
+
+            if (bytesToCopy)
+            {
+                bytesToCopy = MIN(bytesToReceive, bytesToCopy);
+
+                bytesToReceive -= bytesToCopy;
+
+                /* Copy data from ring buffer to user memory. */
+                for (i = 0U; i < bytesToCopy; i++)
+                {
+                    xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
+
+                    /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
+                    if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferTail = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferTail++;
+                    }
+                }
+            }
+
+            /* If ring buffer does not have enough data, still need to read more data. */
+            if (bytesToReceive)
+            {
+                /* No data in ring buffer, save the request to LPUART handle. */
+                handle->rxData = xfer->data + bytesCurrentReceived;
+                handle->rxDataSize = bytesToReceive;
+                handle->rxDataSizeAll = bytesToReceive;
+                handle->rxState = kLPUART_RxBusy;
+            }
+            /* Enable LPUART RX IRQ if previously enabled. */
+            LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable);
+
+            /* Call user callback since all data are received. */
+            if (0 == bytesToReceive)
+            {
+                if (handle->callback)
+                {
+                    handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
+                }
+            }
+        }
+        /* Ring buffer not used. */
+        else
+        {
+            handle->rxData = xfer->data + bytesCurrentReceived;
+            handle->rxDataSize = bytesToReceive;
+            handle->rxDataSizeAll = bytesToReceive;
+            handle->rxState = kLPUART_RxBusy;
+
+            /* Enable RX interrupt. */
+            LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable |
+                                              kLPUART_IdleLineInterruptEnable);
+        }
+
+        /* Return the how many bytes have read. */
+        if (receivedBytes)
+        {
+            *receivedBytes = bytesCurrentReceived;
+        }
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle)
+{
+    assert(handle);
+
+    /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
+    if (!handle->rxRingBuffer)
+    {
+        /* Disable RX interrupt. */
+        LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable |
+                                           kLPUART_IdleLineInterruptEnable);
+    }
+
+    handle->rxDataSize = 0U;
+    handle->rxState = kLPUART_RxIdle;
+}
+
+status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
+{
+    assert(handle);
+    assert(count);
+
+    if (kLPUART_RxIdle == handle->rxState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->rxDataSizeAll - handle->rxDataSize;
+
+    return kStatus_Success;
+}
+
+void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle)
+{
+    assert(handle);
+
+    uint8_t count;
+    uint8_t tempCount;
+
+    /* If RX overrun. */
+    if (LPUART_STAT_OR_MASK & base->STAT)
+    {
+        /* Clear overrun flag, otherwise the RX does not work. */
+        base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK);
+
+        /* Trigger callback. */
+        if (handle->callback)
+        {
+            handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData);
+        }
+    }
+
+    /* If IDLE flag is set and the IDLE interrupt is enabled. */
+    if ((LPUART_STAT_IDLE_MASK & base->STAT) && (LPUART_CTRL_ILIE_MASK & base->CTRL))
+    {
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+        count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT));
+
+        while ((count) && (handle->rxDataSize))
+        {
+            tempCount = MIN(handle->rxDataSize, count);
+
+            /* Using non block API to read the data from the registers. */
+            LPUART_ReadNonBlocking(base, handle->rxData, tempCount);
+            handle->rxData += tempCount;
+            handle->rxDataSize -= tempCount;
+            count -= tempCount;
+
+            /* If rxDataSize is 0, disable idle line interrupt.*/
+            if (!(handle->rxDataSize))
+            {
+                handle->rxState = kLPUART_RxIdle;
+
+                LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
+                if (handle->callback)
+                {
+                    handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
+                }
+            }
+        }
+#endif
+        /* Clear IDLE flag.*/
+        base->STAT |= LPUART_STAT_IDLE_MASK;
+
+        /* If rxDataSize is 0, disable idle line interrupt.*/
+        if (!(handle->rxDataSize))
+        {
+            LPUART_DisableInterrupts(base, kLPUART_IdleLineInterruptEnable);
+        }
+        /* If callback is not NULL and rxDataSize is not 0. */
+        if ((handle->callback) && (handle->rxDataSize))
+        {
+            handle->callback(base, handle, kStatus_LPUART_IdleLineDetected, handle->userData);
+        }
+    }
+    /* Receive data register full */
+    if ((LPUART_STAT_RDRF_MASK & base->STAT) && (LPUART_CTRL_RIE_MASK & base->CTRL))
+    {
+/* Get the size that can be stored into buffer for this interrupt. */
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+        count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT));
+#else
+        count = 1;
+#endif
+
+        /* If handle->rxDataSize is not 0, first save data to handle->rxData. */
+        while ((count) && (handle->rxDataSize))
+        {
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+            tempCount = MIN(handle->rxDataSize, count);
+#else
+            tempCount = 1;
+#endif
+
+            /* Using non block API to read the data from the registers. */
+            LPUART_ReadNonBlocking(base, handle->rxData, tempCount);
+            handle->rxData += tempCount;
+            handle->rxDataSize -= tempCount;
+            count -= tempCount;
+
+            /* If all the data required for upper layer is ready, trigger callback. */
+            if (!handle->rxDataSize)
+            {
+                handle->rxState = kLPUART_RxIdle;
+
+                if (handle->callback)
+                {
+                    handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
+                }
+            }
+        }
+
+        /* If use RX ring buffer, receive data to ring buffer. */
+        if (handle->rxRingBuffer)
+        {
+            while (count--)
+            {
+                /* If RX ring buffer is full, trigger callback to notify over run. */
+                if (LPUART_TransferIsRxRingBufferFull(base, handle))
+                {
+                    if (handle->callback)
+                    {
+                        handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData);
+                    }
+                }
+
+                /* If ring buffer is still full after callback function, the oldest data is overrided. */
+                if (LPUART_TransferIsRxRingBufferFull(base, handle))
+                {
+                    /* Increase handle->rxRingBufferTail to make room for new data. */
+                    if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferTail = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferTail++;
+                    }
+                }
+
+/* Read data. */
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+                if (handle->isSevenDataBits)
+                {
+                    handle->rxRingBuffer[handle->rxRingBufferHead] = (base->DATA & 0x7F);
+                }
+                else
+                {
+                    handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA;
+                }
+#else
+                handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA;
+#endif
+
+                /* Increase handle->rxRingBufferHead. */
+                if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
+                {
+                    handle->rxRingBufferHead = 0U;
+                }
+                else
+                {
+                    handle->rxRingBufferHead++;
+                }
+            }
+        }
+        /* If no receive requst pending, stop RX interrupt. */
+        else if (!handle->rxDataSize)
+        {
+            LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
+        }
+        else
+        {
+        }
+    }
+
+    /* Send data register empty and the interrupt is enabled. */
+    if ((base->STAT & LPUART_STAT_TDRE_MASK) && (base->CTRL & LPUART_CTRL_TIE_MASK))
+    {
+/* Get the bytes that available at this moment. */
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+        count = FSL_FEATURE_LPUART_FIFO_SIZEn(base) -
+                ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT);
+#else
+        count = 1;
+#endif
+
+        while ((count) && (handle->txDataSize))
+        {
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+            tempCount = MIN(handle->txDataSize, count);
+#else
+            tempCount = 1;
+#endif
+
+            /* Using non block API to write the data to the registers. */
+            LPUART_WriteNonBlocking(base, handle->txData, tempCount);
+            handle->txData += tempCount;
+            handle->txDataSize -= tempCount;
+            count -= tempCount;
+
+            /* If all the data are written to data register, notify user with the callback, then TX finished. */
+            if (!handle->txDataSize)
+            {
+                handle->txState = kLPUART_TxIdle;
+
+                /* Disable TX register empty interrupt. */
+                base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK);
+
+                /* Trigger callback. */
+                if (handle->callback)
+                {
+                    handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData);
+                }
+            }
+        }
+    }
+}
+
+void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle)
+{
+    /* To be implemented by User. */
+}
+#if defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART0_LPUART1_RX_DriverIRQHandler(void)
+{
+    if (CLOCK_isEnabledClock(s_lpuartClock[0]))
+    {
+        if ((LPUART_STAT_OR_MASK & LPUART0->STAT) ||
+            ((LPUART_STAT_RDRF_MASK & LPUART0->STAT) && (LPUART_CTRL_RIE_MASK & LPUART0->CTRL)))
+        {
+            s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
+        }
+    }
+    if (CLOCK_isEnabledClock(s_lpuartClock[1]))
+    {
+        if ((LPUART_STAT_OR_MASK & LPUART1->STAT) ||
+            ((LPUART_STAT_RDRF_MASK & LPUART1->STAT) && (LPUART_CTRL_RIE_MASK & LPUART1->CTRL)))
+        {
+            s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
+        }
+    }
+}
+void LPUART0_LPUART1_TX_DriverIRQHandler(void)
+{
+    if (CLOCK_isEnabledClock(s_lpuartClock[0]))
+    {
+        if ((LPUART_STAT_OR_MASK & LPUART0->STAT) ||
+            ((LPUART0->STAT & LPUART_STAT_TDRE_MASK) && (LPUART0->CTRL & LPUART_CTRL_TIE_MASK)))
+        {
+            s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
+        }
+    }
+    if (CLOCK_isEnabledClock(s_lpuartClock[1]))
+    {
+        if ((LPUART_STAT_OR_MASK & LPUART1->STAT) ||
+            ((LPUART1->STAT & LPUART_STAT_TDRE_MASK) && (LPUART1->CTRL & LPUART_CTRL_TIE_MASK)))
+        {
+            s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
+        }
+    }
+}
+#else
+void LPUART0_LPUART1_DriverIRQHandler(void)
+{
+    if (CLOCK_isEnabledClock(s_lpuartClock[0]))
+    {
+        if ((LPUART_STAT_OR_MASK & LPUART0->STAT) ||
+            ((LPUART_STAT_RDRF_MASK & LPUART0->STAT) && (LPUART_CTRL_RIE_MASK & LPUART0->CTRL)) ||
+            ((LPUART0->STAT & LPUART_STAT_TDRE_MASK) && (LPUART0->CTRL & LPUART_CTRL_TIE_MASK)))
+        {
+            s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
+        }
+    }
+    if (CLOCK_isEnabledClock(s_lpuartClock[1]))
+    {
+        if ((LPUART_STAT_OR_MASK & LPUART1->STAT) ||
+            ((LPUART_STAT_RDRF_MASK & LPUART1->STAT) && (LPUART_CTRL_RIE_MASK & LPUART1->CTRL)) ||
+            ((LPUART1->STAT & LPUART_STAT_TDRE_MASK) && (LPUART1->CTRL & LPUART_CTRL_TIE_MASK)))
+        {
+            s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
+        }
+    }
+}
+#endif
+#endif
+
+#if defined(LPUART0)
+#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART0_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
+}
+void LPUART0_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
+}
+#else
+void LPUART0_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
+}
+#endif
+#endif
+#endif
+
+#if defined(LPUART1)
+#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART1_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
+}
+void LPUART1_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
+}
+#else
+void LPUART1_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
+}
+#endif
+#endif
+#endif
+
+#if defined(LPUART2)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART2_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
+}
+void LPUART2_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
+}
+#else
+void LPUART2_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
+}
+#endif
+#endif
+
+#if defined(LPUART3)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART3_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
+}
+void LPUART3_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
+}
+#else
+void LPUART3_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
+}
+#endif
+#endif
+
+#if defined(LPUART4)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART4_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
+}
+void LPUART4_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
+}
+#else
+void LPUART4_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
+}
+#endif
+#endif
+
+#if defined(LPUART5)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART5_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
+}
+void LPUART5_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
+}
+#else
+void LPUART5_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
+}
+#endif
+#endif
+
+#if defined(CM4_0_LPUART)
+void M4_0_LPUART_DriverIRQHandler(void)
+{
+    s_lpuartIsr(CM4_0_LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_0_LPUART)]);
+}
+#endif
+
+#if defined(CM4_1_LPUART)
+void M4_1_LPUART_DriverIRQHandler(void)
+{
+    s_lpuartIsr(CM4_1_LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_1_LPUART)]);
+}
+#endif
+
+#if defined(DMA_LPUART0)
+void DMA_UART0_INT_IRQHandler(void)
+{
+    s_lpuartIsr(DMA_LPUART0, s_lpuartHandle[LPUART_GetInstance(DMA_LPUART0)]);
+}
+#endif
+
+#if defined(DMA_LPUART1)
+void DMA_UART1_INT_IRQHandler(void)
+{
+    s_lpuartIsr(DMA_LPUART1, s_lpuartHandle[LPUART_GetInstance(DMA_LPUART1)]);
+}
+#endif
+
+#if defined(DMA_LPUART2)
+void DMA_UART2_INT_IRQHandler(void)
+{
+    s_lpuartIsr(DMA_LPUART2, s_lpuartHandle[LPUART_GetInstance(DMA_LPUART2)]);
+}
+#endif
+
+#if defined(DMA_LPUART3)
+void DMA_UART3_INT_IRQHandler(void)
+{
+    s_lpuartIsr(DMA_LPUART3, s_lpuartHandle[LPUART_GetInstance(DMA_LPUART3)]);
+}
+#endif
+
+#if defined(DMA_LPUART4)
+void DMA_UART4_INT_IRQHandler(void)
+{
+    s_lpuartIsr(DMA_LPUART4, s_lpuartHandle[LPUART_GetInstance(DMA_LPUART4)]);
+}
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart.h
new file mode 100644
index 0000000..6e44872
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart.h
@@ -0,0 +1,842 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_LPUART_H_
+#define _FSL_LPUART_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpuart_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief LPUART driver version 2.2.3. */
+#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 4))
+/*@}*/
+
+/*! @brief Error codes for the LPUART driver. */
+enum _lpuart_status
+{
+    kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0),                  /*!< TX busy */
+    kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1),                  /*!< RX busy */
+    kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2),                  /*!< LPUART transmitter is idle. */
+    kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3),                  /*!< LPUART receiver is idle. */
+    kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4),     /*!< TX FIFO watermark too large  */
+    kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5),     /*!< RX FIFO watermark too large  */
+    kStatus_LPUART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */
+    kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7),                   /*!< Error happens on LPUART. */
+    kStatus_LPUART_RxRingBufferOverrun =
+        MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */
+    kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */
+    kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10),       /*!< LPUART noise error. */
+    kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11),     /*!< LPUART framing error. */
+    kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12),      /*!< LPUART parity error. */
+    kStatus_LPUART_BaudrateNotSupport =
+        MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */
+    kStatus_LPUART_IdleLineDetected = MAKE_STATUS(kStatusGroup_LPUART, 14), /*!< IDLE flag. */
+};
+
+/*! @brief LPUART parity mode. */
+typedef enum _lpuart_parity_mode
+{
+    kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */
+    kLPUART_ParityEven = 0x2U,     /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
+    kLPUART_ParityOdd = 0x3U,      /*!< Parity enabled, type odd,  bit setting: PE|PT = 11 */
+} lpuart_parity_mode_t;
+
+/*! @brief LPUART data bits count. */
+typedef enum _lpuart_data_bits
+{
+    kLPUART_EightDataBits = 0x0U, /*!< Eight data bit */
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    kLPUART_SevenDataBits = 0x1U, /*!< Seven data bit */
+#endif
+} lpuart_data_bits_t;
+
+/*! @brief LPUART stop bit count. */
+typedef enum _lpuart_stop_bit_count
+{
+    kLPUART_OneStopBit = 0U, /*!< One stop bit */
+    kLPUART_TwoStopBit = 1U, /*!< Two stop bits */
+} lpuart_stop_bit_count_t;
+
+#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
+/*! @brief LPUART transmit CTS source. */
+typedef enum _lpuart_transmit_cts_source
+{
+    kLPUART_CtsSourcePin = 0U,         /*!< CTS resource is the LPUART_CTS pin. */
+    kLPUART_CtsSourceMatchResult = 1U, /*!< CTS resource is the match result. */
+} lpuart_transmit_cts_source_t;
+
+/*! @brief LPUART transmit CTS configure. */
+typedef enum _lpuart_transmit_cts_config
+{
+    kLPUART_CtsSampleAtStart = 0U, /*!< CTS input is sampled at the start of each character. */
+    kLPUART_CtsSampleAtIdle = 1U,  /*!< CTS input is sampled when the transmitter is idle */
+} lpuart_transmit_cts_config_t;
+#endif
+
+/*! @brief LPUART idle flag type defines when the receiver starts counting. */
+typedef enum _lpuart_idle_type_select
+{
+    kLPUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */
+    kLPUART_IdleTypeStopBit = 1U,  /*!< Start conuting after a stop bit. */
+} lpuart_idle_type_select_t;
+
+/*! @brief LPUART idle detected configuration.
+ *  This structure defines the number of idle characters that must be received before
+ *  the IDLE flag is set.
+ */
+typedef enum _lpuart_idle_config
+{
+    kLPUART_IdleCharacter1 = 0U,   /*!< the number of idle characters. */
+    kLPUART_IdleCharacter2 = 1U,   /*!< the number of idle characters. */
+    kLPUART_IdleCharacter4 = 2U,   /*!< the number of idle characters. */
+    kLPUART_IdleCharacter8 = 3U,   /*!< the number of idle characters. */
+    kLPUART_IdleCharacter16 = 4U,  /*!< the number of idle characters. */
+    kLPUART_IdleCharacter32 = 5U,  /*!< the number of idle characters. */
+    kLPUART_IdleCharacter64 = 6U,  /*!< the number of idle characters. */
+    kLPUART_IdleCharacter128 = 7U, /*!< the number of idle characters. */
+} lpuart_idle_config_t;
+
+/*!
+ * @brief LPUART interrupt configuration structure, default settings all disabled.
+ *
+ * This structure contains the settings for all LPUART interrupt configurations.
+ */
+enum _lpuart_interrupt_enable
+{
+#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
+    kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8), /*!< LIN break detect. */
+#endif
+    kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8), /*!< Receive Active Edge. */
+    kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK),        /*!< Transmit data register empty. */
+    kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. */
+    kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK),         /*!< Receiver data register full. */
+    kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK),             /*!< Idle line. */
+    kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK),            /*!< Receiver Overrun. */
+    kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK),           /*!< Noise error flag. */
+    kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK),         /*!< Framing error flag. */
+    kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK),          /*!< Parity error flag. */
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK >> 8),  /*!< Transmit FIFO Overflow. */
+    kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK >> 8), /*!< Receive FIFO Underflow. */
+#endif
+};
+
+/*!
+ * @brief LPUART status flags.
+ *
+ * This provides constants for the LPUART status flags for use in the LPUART functions.
+ */
+enum _lpuart_flags
+{
+    kLPUART_TxDataRegEmptyFlag =
+        (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty */
+    kLPUART_TransmissionCompleteFlag =
+        (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete */
+    kLPUART_RxDataRegFullFlag =
+        (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive data buffer is full */
+    kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected */
+    kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK),  /*!< Receive Overrun, sets when new data is received before data is
+                                                       read from receive register */
+    kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit.  If any of these
+                                                       samples differ, noise flag sets */
+    kLPUART_FramingErrorFlag =
+        (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */
+    kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection */
+#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
+    kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break char
+                                                         detected and LIN circuit enabled */
+#endif
+    kLPUART_RxActiveEdgeFlag =
+        (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active edge detected */
+    kLPUART_RxActiveFlag =
+        (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */
+#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
+    kLPUART_DataMatch1Flag = LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1*/
+    kLPUART_DataMatch2Flag = LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2*/
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS
+    kLPUART_NoiseErrorInRxDataRegFlag =
+        (LPUART_DATA_NOISY_MASK >> 10), /*!< NOISY bit, sets if noise detected in current data word */
+    kLPUART_ParityErrorInRxDataRegFlag =
+        (LPUART_DATA_PARITYE_MASK >> 10), /*!< PARITYE bit, sets if noise detected in current data word */
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    kLPUART_TxFifoEmptyFlag = (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty */
+    kLPUART_RxFifoEmptyFlag = (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty */
+    kLPUART_TxFifoOverflowFlag =
+        (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred */
+    kLPUART_RxFifoUnderflowFlag =
+        (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred */
+#endif
+};
+
+/*! @brief LPUART configuration structure. */
+typedef struct _lpuart_config
+{
+    uint32_t baudRate_Bps;            /*!< LPUART baud rate  */
+    lpuart_parity_mode_t parityMode;  /*!< Parity mode, disabled (default), even, odd */
+    lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */
+    bool isMsb;                       /*!< Data bits order, LSB (default), MSB */
+#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
+    lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits  */
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    uint8_t txFifoWatermark; /*!< TX FIFO watermark */
+    uint8_t rxFifoWatermark; /*!< RX FIFO watermark */
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
+    bool enableRxRTS;                         /*!< RX RTS enable */
+    bool enableTxCTS;                         /*!< TX CTS enable */
+    lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */
+    lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */
+#endif
+    lpuart_idle_type_select_t rxIdleType; /*!< RX IDLE type. */
+    lpuart_idle_config_t rxIdleConfig;    /*!< RX IDLE configuration. */
+    bool enableTx;                        /*!< Enable TX */
+    bool enableRx;                        /*!< Enable RX */
+} lpuart_config_t;
+
+/*! @brief LPUART transfer structure. */
+typedef struct _lpuart_transfer
+{
+    uint8_t *data;   /*!< The buffer of data to be transfer.*/
+    size_t dataSize; /*!< The byte count to be transfer. */
+} lpuart_transfer_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _lpuart_handle lpuart_handle_t;
+
+/*! @brief LPUART transfer callback function. */
+typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData);
+
+/*! @brief LPUART handle structure. */
+struct _lpuart_handle
+{
+    uint8_t *volatile txData;   /*!< Address of remaining data to send. */
+    volatile size_t txDataSize; /*!< Size of the remaining data to send. */
+    size_t txDataSizeAll;       /*!< Size of the data to send out. */
+    uint8_t *volatile rxData;   /*!< Address of remaining data to receive. */
+    volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */
+    size_t rxDataSizeAll;       /*!< Size of the data to receive. */
+
+    uint8_t *rxRingBuffer;              /*!< Start address of the receiver ring buffer. */
+    size_t rxRingBufferSize;            /*!< Size of the ring buffer. */
+    volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
+    volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
+
+    lpuart_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                      /*!< LPUART callback function parameter.*/
+
+    volatile uint8_t txState; /*!< TX transfer state. */
+    volatile uint8_t rxState; /*!< RX transfer state. */
+
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    bool isSevenDataBits; /*!< Seven data bits flag. */
+#endif
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL
+
+/*!
+ * @name Software Reset
+ * @{
+ */
+
+/*!
+ * @brief Resets the LPUART using software.
+ *
+ * This function resets all internal logic and registers except the Global Register.
+ * Remains set until cleared by software.
+ *
+ * @param base LPUART peripheral base address.
+ */
+static inline void LPUART_SoftwareReset(LPUART_Type *base)
+{
+    base->GLOBAL |= LPUART_GLOBAL_RST_MASK;
+    base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
+}
+/* @} */
+#endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock.
+ *
+ * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function
+ * to configure the configuration structure and get the default configuration.
+ * The example below shows how to use this API to configure the LPUART.
+ * @code
+ *  lpuart_config_t lpuartConfig;
+ *  lpuartConfig.baudRate_Bps = 115200U;
+ *  lpuartConfig.parityMode = kLPUART_ParityDisabled;
+ *  lpuartConfig.dataBitsCount = kLPUART_EightDataBits;
+ *  lpuartConfig.isMsb = false;
+ *  lpuartConfig.stopBitCount = kLPUART_OneStopBit;
+ *  lpuartConfig.txFifoWatermark = 0;
+ *  lpuartConfig.rxFifoWatermark = 1;
+ *  LPUART_Init(LPUART1, &lpuartConfig, 20000000U);
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @param config Pointer to a user-defined configuration structure.
+ * @param srcClock_Hz LPUART clock source frequency in HZ.
+ * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_Success LPUART initialize succeed
+ */
+status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Deinitializes a LPUART instance.
+ *
+ * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock.
+ *
+ * @param base LPUART peripheral base address.
+ */
+void LPUART_Deinit(LPUART_Type *base);
+
+/*!
+ * @brief Gets the default configuration structure.
+ *
+ * This function initializes the LPUART configuration structure to a default value. The default
+ * values are:
+ *   lpuartConfig->baudRate_Bps = 115200U;
+ *   lpuartConfig->parityMode = kLPUART_ParityDisabled;
+ *   lpuartConfig->dataBitsCount = kLPUART_EightDataBits;
+ *   lpuartConfig->isMsb = false;
+ *   lpuartConfig->stopBitCount = kLPUART_OneStopBit;
+ *   lpuartConfig->txFifoWatermark = 0;
+ *   lpuartConfig->rxFifoWatermark = 1;
+ *   lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit;
+ *   lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1;
+ *   lpuartConfig->enableTx = false;
+ *   lpuartConfig->enableRx = false;
+ *
+ * @param config Pointer to a configuration structure.
+ */
+void LPUART_GetDefaultConfig(lpuart_config_t *config);
+
+/*!
+ * @brief Sets the LPUART instance baudrate.
+ *
+ * This function configures the LPUART module baudrate. This function is used to update
+ * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init.
+ * @code
+ *  LPUART_SetBaudRate(LPUART1, 115200U, 20000000U);
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @param baudRate_Bps LPUART baudrate to be set.
+ * @param srcClock_Hz LPUART clock source frequency in HZ.
+ * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source.
+ * @retval kStatus_Success Set baudrate succeeded.
+ */
+status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
+
+/* @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets LPUART status flags.
+ *
+ * This function gets all LPUART status flags. The flags are returned as the logical
+ * OR value of the enumerators @ref _lpuart_flags. To check for a specific status,
+ * compare the return value with enumerators in the @ref _lpuart_flags.
+ * For example, to check whether the TX is empty:
+ * @code
+ *     if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1))
+ *     {
+ *         ...
+ *     }
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags.
+ */
+uint32_t LPUART_GetStatusFlags(LPUART_Type *base);
+
+/*!
+ * @brief Clears status flags with a provided mask.
+ *
+ * This function clears LPUART status flags with a provided mask. Automatically cleared flags
+ * can't be cleared by this function.
+ * Flags that can only cleared or set by hardware are:
+ *    kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag,
+ *    kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag,
+ *    kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag
+ * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.
+ *
+ * @param base LPUART peripheral base address.
+ * @param mask the status flags to be cleared. The user can use the enumerators in the
+ *  _lpuart_status_flag_t to do the OR operation and get the mask.
+ * @return 0 succeed, others failed.
+ * @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but
+ *         it is cleared automatically by hardware.
+ * @retval kStatus_Success Status in the mask are cleared.
+ */
+status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask);
+
+/* @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables LPUART interrupts according to a provided mask.
+ *
+ * This function enables the LPUART interrupts according to a provided mask. The mask
+ * is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable.
+ * This examples shows how to enable TX empty interrupt and RX full interrupt:
+ * @code
+ *     LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable.
+ */
+void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables  LPUART interrupts according to a provided mask.
+ *
+ * This function disables the LPUART interrupts according to a provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable.
+ * This example shows how to disable the TX empty interrupt and RX full interrupt:
+ * @code
+ *     LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable.
+ */
+void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask);
+
+/*!
+ * @brief Gets enabled LPUART interrupts.
+ *
+ * This function gets the enabled LPUART interrupts. The enabled interrupts are returned
+ * as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check
+ * a specific interrupt enable status, compare the return value with enumerators
+ * in @ref _lpuart_interrupt_enable.
+ * For example, to check whether the TX empty interrupt is enabled:
+ * @code
+ *     uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1);
+ *
+ *     if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)
+ *     {
+ *         ...
+ *     }
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable.
+ */
+uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base);
+
+#if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE
+/*!
+ * @brief Gets the LPUART data register address.
+ *
+ * This function returns the LPUART data register address, which is mainly used by the DMA/eDMA.
+ *
+ * @param base LPUART peripheral base address.
+ * @return LPUART data register addresses which are used both by the transmitter and receiver.
+ */
+static inline uint32_t LPUART_GetDataRegisterAddress(LPUART_Type *base)
+{
+    return (uint32_t) & (base->DATA);
+}
+
+/*!
+ * @brief Enables or disables the LPUART transmitter DMA request.
+ *
+ * This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests.
+ *
+ * @param base LPUART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->BAUD |= LPUART_BAUD_TDMAE_MASK;
+        base->CTRL |= LPUART_CTRL_TIE_MASK;
+    }
+    else
+    {
+        base->BAUD &= ~LPUART_BAUD_TDMAE_MASK;
+        base->CTRL &= ~LPUART_CTRL_TIE_MASK;
+    }
+}
+
+/*!
+ * @brief Enables or disables the LPUART receiver DMA.
+ *
+ * This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests.
+ *
+ * @param base LPUART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->BAUD |= LPUART_BAUD_RDMAE_MASK;
+        base->CTRL |= LPUART_CTRL_RIE_MASK;
+    }
+    else
+    {
+        base->BAUD &= ~LPUART_BAUD_RDMAE_MASK;
+        base->CTRL &= ~LPUART_CTRL_RIE_MASK;
+    }
+}
+
+/* @} */
+#endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Enables or disables the LPUART transmitter.
+ *
+ * This function enables or disables the LPUART transmitter.
+ *
+ * @param base LPUART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void LPUART_EnableTx(LPUART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTRL |= LPUART_CTRL_TE_MASK;
+    }
+    else
+    {
+        base->CTRL &= ~LPUART_CTRL_TE_MASK;
+    }
+}
+
+/*!
+ * @brief Enables or disables the LPUART receiver.
+ *
+ * This function enables or disables the LPUART receiver.
+ *
+ * @param base LPUART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void LPUART_EnableRx(LPUART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTRL |= LPUART_CTRL_RE_MASK;
+    }
+    else
+    {
+        base->CTRL &= ~LPUART_CTRL_RE_MASK;
+    }
+}
+
+/*!
+ * @brief Writes to the transmitter register.
+ *
+ * This function writes data to the transmitter register directly. The upper layer must
+ * ensure that the TX register is empty or that the TX FIFO has room before calling this function.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Data write to the TX register.
+ */
+static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data)
+{
+    base->DATA = data;
+}
+
+/*!
+ * @brief Reads the receiver register.
+ *
+ * This function reads data from the receiver register directly. The upper layer must
+ * ensure that the receiver register is full or that the RX FIFO has data before calling this function.
+ *
+ * @param base LPUART peripheral base address.
+ * @return Data read from data register.
+ */
+static inline uint8_t LPUART_ReadByte(LPUART_Type *base)
+{
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    uint32_t ctrl = base->CTRL;
+    bool isSevenDataBits =
+        ((ctrl & LPUART_CTRL_M7_MASK) ||
+         ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
+
+    if (isSevenDataBits)
+    {
+        return (base->DATA & 0x7F);
+    }
+    else
+    {
+        return base->DATA;
+    }
+#else
+    return base->DATA;
+#endif
+}
+
+/*!
+ * @brief Writes to the transmitter register using a blocking method.
+ *
+ * This function polls the transmitter register, waits for the register to be empty or  for TX FIFO to have
+ * room, and writes data to the transmitter buffer.
+ *
+ * @note This function does not check whether all data has been sent out to the bus.
+ * Before disabling the transmitter, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is
+ * finished.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ */
+void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
+
+/*!
+* @brief Reads the receiver data register using a blocking method.
+ *
+ * This function polls the receiver register, waits for the receiver register full or receiver FIFO
+ * has data, and reads data from the TX register.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data.
+ * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data.
+ * @retval kStatus_LPUART_FramingError Framing error happened while receiving data.
+ * @retval kStatus_LPUART_ParityError Parity error happened while receiving data.
+ * @retval kStatus_Success Successfully received all data.
+ */
+status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length);
+
+/* @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the LPUART handle.
+ *
+ * This function initializes the LPUART handle, which can be used for other LPUART
+ * transactional APIs. Usually, for a specified LPUART instance,
+ * call this API once to get the initialized handle.
+ *
+ * The LPUART driver supports the "background" receiving, which means that user can set up
+ * an RX ring buffer optionally. Data received is stored into the ring buffer even when the
+ * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ * The ring buffer is disabled if passing NULL as @p ringBuffer.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param callback Callback function.
+ * @param userData User data.
+ */
+void LPUART_TransferCreateHandle(LPUART_Type *base,
+                                 lpuart_handle_t *handle,
+                                 lpuart_transfer_callback_t callback,
+                                 void *userData);
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function send data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data written to the transmitter register. When
+ * all data is written to the TX register in the ISR, the LPUART driver calls the callback
+ * function and passes the @ref kStatus_LPUART_TxIdle as status parameter.
+ *
+ * @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written
+ * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX,
+ * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param xfer LPUART transfer structure, see #lpuart_transfer_t.
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer);
+
+/*!
+ * @brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific UART handle.
+ *
+ * When the RX ring buffer is used, data received is stored into the ring buffer even when
+ * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * @note When using RX ring buffer, one byte is reserved for internal use. In other
+ * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * @param ringBufferSize size of the ring buffer.
+ */
+void LPUART_TransferStartRingBuffer(LPUART_Type *base,
+                                    lpuart_handle_t *handle,
+                                    uint8_t *ringBuffer,
+                                    size_t ringBufferSize);
+
+/*!
+ * @brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ */
+void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
+ * how many bytes are not sent out.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ */
+void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief Gets the number of bytes that have been written to the LPUART transmitter register.
+ *
+ * This function gets the number of bytes that have been written to LPUART TX
+ * register by an interrupt method.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_NoTransferInProgress No send in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief Receives a buffer of data using the interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function
+ * which returns without waiting to ensure that all data are received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough for read, the receive
+ * request is saved by the LPUART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the LPUART driver notifies the upper layer
+ * through a callback function and passes a status parameter @ref kStatus_UART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer.
+ * The 5 bytes are copied to xfer->data, which returns with the
+ * parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is
+ * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to xfer->data. When all data is received, the upper layer is notified.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param xfer LPUART transfer structure, see #uart_transfer_t.
+ * @param receivedBytes Bytes received from the ring buffer directly.
+ * @retval kStatus_Success Successfully queue the transfer into the transmit queue.
+ * @retval kStatus_LPUART_RxBusy Previous receive request is not finished.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
+                                           lpuart_handle_t *handle,
+                                           lpuart_transfer_t *xfer,
+                                           size_t *receivedBytes);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
+ * how many bytes not received yet.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ */
+void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief LPUART IRQ handle function.
+ *
+ * This function handles the LPUART transmit and receive IRQ request.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ */
+void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief LPUART Error IRQ handle function.
+ *
+ * This function handles the LPUART error IRQ request.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ */
+void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_LPUART_H_ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_msmc.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_msmc.c
new file mode 100644
index 0000000..ed982a6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_msmc.c
@@ -0,0 +1,290 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_msmc.h"
+
+#if defined(__riscv)
+#define CONFIG_NORMAL_SLEEP EVENT_UNIT->SLPCTRL = (EVENT_UNIT->SLPCTRL & ~0x03) | (1 << 0)
+#define CONFIG_DEEP_SLEEP EVENT_UNIT->SLPCTRL |= 0x03;
+#else
+#define CONFIG_NORMAL_SLEEP SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk
+#define CONFIG_DEEP_SLEEP SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk
+#endif
+
+status_t SMC_SetPowerModeRun(SMC_Type *base)
+{
+    uint32_t reg;
+
+    reg = base->PMCTRL;
+    /* configure Normal RUN mode */
+    reg &= ~SMC_PMCTRL_RUNM_MASK;
+    reg |= (kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT);
+    base->PMCTRL = reg;
+
+    return kStatus_Success;
+}
+
+status_t SMC_SetPowerModeHsrun(SMC_Type *base)
+{
+    uint32_t reg;
+
+    reg = base->PMCTRL;
+    /* configure High Speed RUN mode */
+    reg &= ~SMC_PMCTRL_RUNM_MASK;
+    reg |= (kSMC_Hsrun << SMC_PMCTRL_RUNM_SHIFT);
+    base->PMCTRL = reg;
+
+    return kStatus_Success;
+}
+
+status_t SMC_SetPowerModeWait(SMC_Type *base)
+{
+    /* configure Normal Wait mode */
+    CONFIG_NORMAL_SLEEP;
+
+    __DSB();
+    __WFI();
+    __ISB();
+
+    return kStatus_Success;
+}
+
+status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option)
+{
+    uint32_t reg;
+
+    /* configure the Partial Stop mode in Noraml Stop mode */
+    reg = base->PMCTRL;
+    reg &= ~(SMC_PMCTRL_PSTOPO_MASK | SMC_PMCTRL_STOPM_MASK);
+    reg |= ((uint32_t)option << SMC_PMCTRL_PSTOPO_SHIFT) | (kSMC_StopNormal << SMC_PMCTRL_STOPM_SHIFT);
+    base->PMCTRL = reg;
+
+    /* Set the SLEEPDEEP bit to enable deep sleep mode (stop mode) */
+    CONFIG_DEEP_SLEEP;
+
+    /* read back to make sure the configuration valid before entering stop mode */
+    (void)base->PMCTRL;
+    __DSB();
+    __WFI();
+    __ISB();
+
+#if (defined(FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) && FSL_FEATURE_SMC_HAS_PMCTRL_STOPA)
+    /* check whether the power mode enter Stop mode succeed */
+    if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
+    {
+        return kStatus_SMC_StopAbort;
+    }
+    else
+    {
+        return kStatus_Success;
+    }
+#else
+    return kStatus_Success;
+#endif /* FSL_FEATURE_SMC_HAS_PMCTRL_STOPA */
+}
+
+status_t SMC_SetPowerModeVlpr(SMC_Type *base)
+{
+    uint32_t reg;
+
+    reg = base->PMCTRL;
+    /* configure VLPR mode */
+    reg &= ~SMC_PMCTRL_RUNM_MASK;
+    reg |= (kSMC_RunVlpr << SMC_PMCTRL_RUNM_SHIFT);
+    base->PMCTRL = reg;
+
+    return kStatus_Success;
+}
+
+status_t SMC_SetPowerModeVlpw(SMC_Type *base)
+{
+    /* configure VLPW mode */
+    /* Clear the SLEEPDEEP bit to disable deep sleep mode */
+    CONFIG_NORMAL_SLEEP;
+
+    __DSB();
+    __WFI();
+    __ISB();
+
+    return kStatus_Success;
+}
+
+status_t SMC_SetPowerModeVlps(SMC_Type *base)
+{
+    uint32_t reg;
+
+    /* configure VLPS mode */
+    reg = base->PMCTRL;
+    reg &= ~SMC_PMCTRL_STOPM_MASK;
+    reg |= (kSMC_StopVlps << SMC_PMCTRL_STOPM_SHIFT);
+    base->PMCTRL = reg;
+
+    /* Set the SLEEPDEEP bit to enable deep sleep mode */
+    CONFIG_DEEP_SLEEP;
+
+    /* read back to make sure the configuration valid before enter stop mode */
+    (void)base->PMCTRL;
+    __DSB();
+    __WFI();
+    __ISB();
+
+#if (defined(FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) && FSL_FEATURE_SMC_HAS_PMCTRL_STOPA)
+    /* check whether the power mode enter Stop mode succeed */
+    if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
+    {
+        return kStatus_SMC_StopAbort;
+    }
+    else
+    {
+        return kStatus_Success;
+    }
+#else
+    return kStatus_Success;
+#endif /* FSL_FEATURE_SMC_HAS_PMCTRL_STOPA */
+}
+
+status_t SMC_SetPowerModeLls(SMC_Type *base)
+{
+    uint32_t reg;
+
+    /* configure to LLS mode */
+    reg = base->PMCTRL;
+    reg &= ~SMC_PMCTRL_STOPM_MASK;
+    reg |= (kSMC_StopLls << SMC_PMCTRL_STOPM_SHIFT);
+    base->PMCTRL = reg;
+
+    /* Set the SLEEPDEEP bit to enable deep sleep mode */
+    CONFIG_DEEP_SLEEP;
+
+    /* read back to make sure the configuration valid before entering stop mode */
+    (void)base->PMCTRL;
+    __DSB();
+    __WFI();
+    __ISB();
+
+#if (defined(FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) && FSL_FEATURE_SMC_HAS_PMCTRL_STOPA)
+    /* check whether the power mode enter Stop mode succeed */
+    if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
+    {
+        return kStatus_SMC_StopAbort;
+    }
+    else
+    {
+        return kStatus_Success;
+    }
+#else
+    return kStatus_Success;
+#endif /* FSL_FEATURE_SMC_HAS_PMCTRL_STOPA */
+}
+
+#if (defined(FSL_FEATURE_SMC_HAS_SUB_STOP_MODE) && FSL_FEATURE_SMC_HAS_SUB_STOP_MODE)
+
+#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE0) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE0)
+status_t SMC_SetPowerModeVlls0(SMC_Type *base)
+{
+    uint32_t reg;
+
+    /* configure to VLLS mode */
+    reg = base->PMCTRL;
+    reg &= ~SMC_PMCTRL_STOPM_MASK;
+    reg |= (kSMC_StopVlls0 << SMC_PMCTRL_STOPM_SHIFT);
+    base->PMCTRL = reg;
+
+    /* Set the SLEEPDEEP bit to enable deep sleep mode */
+    CONFIG_DEEP_SLEEP;
+
+    /* read back to make sure the configuration valid before enter stop mode */
+    (void)base->PMCTRL;
+    __DSB();
+    __WFI();
+    __ISB();
+
+    return kStatus_Success;
+}
+#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */
+
+#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE2) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE2)
+status_t SMC_SetPowerModeVlls2(SMC_Type *base)
+{
+    uint32_t reg;
+
+    /* configure to VLLS mode */
+    reg = base->PMCTRL;
+    reg &= ~SMC_PMCTRL_STOPM_MASK;
+    reg |= (kSMC_StopVlls2 << SMC_PMCTRL_STOPM_SHIFT);
+    base->PMCTRL = reg;
+
+    /* Set the SLEEPDEEP bit to enable deep sleep mode */
+    CONFIG_DEEP_SLEEP;
+
+    /* read back to make sure the configuration valid before enter stop mode */
+    (void)base->PMCTRL;
+    __DSB();
+    __WFI();
+    __ISB();
+
+    return kStatus_Success;
+}
+#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */
+
+#else /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */
+status_t SMC_SetPowerModeVlls(SMC_Type *base)
+{
+    uint32_t reg;
+
+    /* configure to VLLS mode */
+    reg = base->PMCTRL;
+    reg &= ~SMC_PMCTRL_STOPM_MASK;
+    reg |= (kSMC_StopVlls << SMC_PMCTRL_STOPM_SHIFT);
+    base->PMCTRL = reg;
+
+#if defined(__riscv)
+    EVENT->SCR = (EVENT->SCR & ~0x03) | (1 << 1);
+#else
+    /* Set the SLEEPDEEP bit to enable deep sleep mode */
+    CONFIG_DEEP_SLEEP;
+#endif
+
+    /* read back to make sure the configuration valid before enter stop mode */
+    (void)base->PMCTRL;
+    __DSB();
+    __WFI();
+    __ISB();
+
+#if (defined(FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) && FSL_FEATURE_SMC_HAS_PMCTRL_STOPA)
+    /* check whether the power mode enter Stop mode succeed */
+    if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
+    {
+        return kStatus_SMC_StopAbort;
+    }
+    else
+    {
+        return kStatus_Success;
+    }
+#else
+    return kStatus_Success;
+#endif /* FSL_FEATURE_SMC_HAS_PMCTRL_STOPA */
+}
+#endif /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */
+
+void SMC_ConfigureResetPinFilter(SMC_Type *base, const smc_reset_pin_filter_config_t *config)
+{
+    assert(config);
+
+    uint32_t reg;
+
+    reg = SMC_RPC_FILTCFG(config->slowClockFilterCount) | SMC_RPC_FILTEN(config->enableFilter);
+#if (defined(FSL_FEATURE_SMC_HAS_RPC_LPOFEN) && FSL_FEATURE_SMC_HAS_RPC_LPOFEN)
+    if (config->enableLpoFilter)
+    {
+        reg |= SMC_RPC_LPOFEN_MASK;
+    }
+#endif /* FSL_FEATURE_SMC_HAS_RPC_LPOFEN */
+
+    base->RPC = reg;
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_msmc.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_msmc.h
new file mode 100644
index 0000000..8b0907b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_msmc.h
@@ -0,0 +1,701 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_MSMC_H_
+#define _FSL_MSMC_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup msmc */
+/*! @{*/
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief MSMC driver version 2.1.0. */
+#define FSL_MSMC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*@}*/
+
+/*!
+ * @brief Power Modes Protection
+ */
+typedef enum _smc_power_mode_protection
+{
+    kSMC_AllowPowerModeVlls = SMC_PMPROT_AVLLS_MASK,   /*!< Allow Very-Low-Leakage Stop Mode. */
+    kSMC_AllowPowerModeLls = SMC_PMPROT_ALLS_MASK,     /*!< Allow Low-Leakage Stop Mode.      */
+    kSMC_AllowPowerModeVlp = SMC_PMPROT_AVLP_MASK,     /*!< Allow Very-Low-Power Mode.        */
+    kSMC_AllowPowerModeHsrun = SMC_PMPROT_AHSRUN_MASK, /*!< Allow High Speed Run mode.        */
+    kSMC_AllowPowerModeAll = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK |
+                             SMC_PMPROT_AHSRUN_MASK /*!< Allow all power mode.              */
+} smc_power_mode_protection_t;
+
+/*!
+ * @brief Power Modes in PMSTAT
+ */
+typedef enum _smc_power_state
+{
+    kSMC_PowerStateRun = 1U,        /*!< 0000_0001 - Current power mode is RUN   */
+    kSMC_PowerStateStop = 1U << 1U, /*!< 0000_0010 - Current power mode is any STOP mode  */
+    kSMC_PowerStateVlpr = 1U << 2U, /*!< 0000_0100 - Current power mode is VLPR  */
+    kSMC_PowerStateHsrun = 1U << 7U /*!< 1000_0000 - Current power mode is HSRUN */
+} smc_power_state_t;
+
+/*!
+ * @brief Power Stop Entry Status in PMSTAT
+ */
+typedef enum _smc_power_stop_entry_status
+{
+    kSMC_PowerStopEntryAlt0 = 1U,      /*!< Indicates a Stop mode entry since this field was last cleared. */
+    kSMC_PowerStopEntryAlt1 = 1U << 1, /*!< Indicates the system bus masters acknowledged the Stop mode entry. */
+    kSMC_PowerStopEntryAlt2 = 1U << 2, /*!< Indicates the system clock peripherals acknowledged the Stop mode entry. */
+    kSMC_PowerStopEntryAlt3 = 1U << 3, /*!< Indicates the bus clock peripherals acknowledged the Stop mode entry. */
+    kSMC_PowerStopEntryAlt4 = 1U << 4, /*!< Indicates the slow clock peripherals acknowledged the Stop mode entry. */
+    kSMC_PowerStopEntryAlt5 = 1U << 5, /*!< Indicates Stop mode entry completed. */
+} smc_power_stop_entry_status_t;
+
+/*!
+ * @brief Run mode definition
+ */
+typedef enum _smc_run_mode
+{
+    kSMC_RunNormal = 0U, /*!< normal RUN mode.             */
+    kSMC_RunVlpr = 2U,   /*!< Very-Low-Power RUN mode.     */
+    kSMC_Hsrun = 3U      /*!< High Speed Run mode (HSRUN). */
+} smc_run_mode_t;
+
+/*!
+ * @brief Stop mode definition
+ */
+typedef enum _smc_stop_mode
+{
+    kSMC_StopNormal = 0U, /*!< Normal STOP mode.           */
+    kSMC_StopVlps = 2U,   /*!< Very-Low-Power STOP mode.   */
+    kSMC_StopLls = 3U,    /*!< Low-Leakage Stop mode.      */
+#if (defined(FSL_FEATURE_SMC_HAS_SUB_STOP_MODE) && FSL_FEATURE_SMC_HAS_SUB_STOP_MODE)
+#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE2) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE2)
+    kSMC_StopVlls2 = 4U, /*!< Very-Low-Leakage Stop mode, VLPS2/3. */
+#endif                   /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 */
+#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE0) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE0)
+    kSMC_StopVlls0 = 6U, /*!< Very-Low-Leakage Stop mode, VLPS0/1. */
+#endif                   /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */
+#else
+    kSMC_StopVlls = 4U, /*!< Very-Low-Leakage Stop mode. */
+#endif /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */
+} smc_stop_mode_t;
+
+/*!
+ * @brief Partial STOP option
+ */
+typedef enum _smc_partial_stop_mode
+{
+    kSMC_PartialStop = 0U,  /*!< STOP - Normal Stop mode*/
+    kSMC_PartialStop1 = 1U, /*!< Partial Stop with both system and bus clocks disabled*/
+    kSMC_PartialStop2 = 2U, /*!< Partial Stop with system clock disabled and bus clock enabled*/
+    kSMC_PartialStop3 = 3U, /*!< Partial Stop with system clock enabled and bus clock disabled*/
+} smc_partial_stop_option_t;
+
+/*!
+ * @brief SMC configuration status
+ */
+enum _smc_status
+{
+    kStatus_SMC_StopAbort = MAKE_STATUS(kStatusGroup_POWER, 0), /*!< Entering Stop mode is abort*/
+};
+
+/*!
+ * @brief System Reset Source Name definitions
+ */
+typedef enum _smc_reset_source
+{
+    kSMC_SourceWakeup = SMC_SRS_WAKEUP_MASK, /*!< Very low-leakage wakeup reset */
+    kSMC_SourcePor = SMC_SRS_POR_MASK,       /*!< Power on reset */
+    kSMC_SourceLvd = SMC_SRS_LVD_MASK,       /*!< Low-voltage detect reset */
+    kSMC_SourceHvd = SMC_SRS_HVD_MASK,       /*!< High-voltage detect reset */
+    kSMC_SourceWarm = SMC_SRS_WARM_MASK,     /*!< Warm reset. Warm Reset flag will assert if any of the system reset
+                                                 sources in this register assert (SRS[31:8]) */
+    kSMC_SourceFatal = SMC_SRS_FATAL_MASK,   /*!< Fatal reset */
+    kSMC_SourceCore =
+        SMC_SRS_CORE_MASK, /*!< Software reset that only reset the core, NOT a sticky system reset source. */
+    kSMC_SourcePin = SMC_SRS_PIN_MASK,         /*!< RESET_B pin reset. */
+    kSMC_SourceMdm = SMC_SRS_MDM_MASK,         /*!< MDM reset. */
+    kSMC_SourceRstAck = SMC_SRS_RSTACK_MASK,   /*!< Reset Controller timeout reset. */
+    kSMC_SourceStopAck = SMC_SRS_STOPACK_MASK, /*!< Stop timeout reset */
+    kSMC_SourceScg = SMC_SRS_SCG_MASK,         /*!< SCG loss of lock or loss of clock */
+    kSMC_SourceWdog = SMC_SRS_WDOG_MASK,       /*!< Watchdog reset */
+    kSMC_SourceSoftware = SMC_SRS_SW_MASK,     /*!< Software reset */
+    kSMC_SourceLockup = SMC_SRS_LOCKUP_MASK,   /*!< Lockup reset. Core lockup or exception. */
+    kSMC_SourceJtag = SMC_SRS_JTAG_MASK,       /*!< JTAG system reset */
+#if (defined(FSL_FEATURE_SMC_HAS_SRS_SECVIO) && FSL_FEATURE_SMC_HAS_SRS_SECVIO)
+    kSMC_SourceSecVio = SMC_SRS_SECVIO_MASK, /*!< Security violation reset */
+#endif                                       /* FSL_FEATURE_SMC_HAS_SRS_SECVIO */
+#if (defined(FSL_FEATURE_SMC_HAS_SRS_TAMPER) && FSL_FEATURE_SMC_HAS_SRS_TAMPER)
+    kSMC_SourceTamper = SMC_SRS_TAMPER_MASK, /*!< Tamper reset */
+#endif                                       /* FSL_FEATURE_SMC_HAS_SRS_TAMPER */
+#if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE0) && FSL_FEATURE_SMC_HAS_SRS_CORE0)
+    kSMC_SourceCore0 = SMC_SRS_CORE0_MASK, /*!< Core0 System Reset. */
+#endif                                     /* FSL_FEATURE_SMC_HAS_SRS_CORE0 */
+#if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE1) && FSL_FEATURE_SMC_HAS_SRS_CORE1)
+    kSMC_SourceCore1 = SMC_SRS_CORE1_MASK, /*!< Core1 System Reset. */
+#endif                                     /* FSL_FEATURE_SMC_HAS_SRS_CORE1 */
+    /* Source All. */
+    kSMC_SourceAll = SMC_SRS_WAKEUP_MASK | SMC_SRS_POR_MASK | SMC_SRS_LVD_MASK | SMC_SRS_HVD_MASK | SMC_SRS_WARM_MASK |
+                     SMC_SRS_FATAL_MASK | SMC_SRS_CORE_MASK | SMC_SRS_PIN_MASK | SMC_SRS_MDM_MASK |
+                     SMC_SRS_RSTACK_MASK | SMC_SRS_STOPACK_MASK | SMC_SRS_SCG_MASK | SMC_SRS_WDOG_MASK |
+                     SMC_SRS_SW_MASK | SMC_SRS_LOCKUP_MASK | SMC_SRS_JTAG_MASK
+#if (defined(FSL_FEATURE_SMC_HAS_SRS_SECVIO) && FSL_FEATURE_SMC_HAS_SRS_SECVIO)
+                     |
+                     SMC_SRS_SECVIO_MASK
+#endif /* FSL_FEATURE_SMC_HAS_SRS_SECVIO */
+#if (defined(FSL_FEATURE_SMC_HAS_SRS_TAMPER) && FSL_FEATURE_SMC_HAS_SRS_TAMPER)
+                     |
+                     SMC_SRS_TAMPER_MASK
+#endif /* FSL_FEATURE_SMC_HAS_SRS_TAMPER */
+#if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE0) && FSL_FEATURE_SMC_HAS_SRS_CORE0)
+                     |
+                     SMC_SRS_CORE0_MASK
+#endif /* FSL_FEATURE_SMC_HAS_SRS_CORE0 */
+#if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE1) && FSL_FEATURE_SMC_HAS_SRS_CORE1)
+                     |
+                     SMC_SRS_CORE1_MASK
+#endif /* FSL_FEATURE_SMC_HAS_SRS_CORE1 */
+    ,
+} smc_reset_source_t;
+
+/*!
+ * @brief System reset interrupt enable bit definitions.
+ */
+typedef enum _smc_interrupt_enable
+{
+    kSMC_IntNone = 0U,                       /*!< No interrupt enabled.       */
+    kSMC_IntPin = SMC_SRIE_PIN_MASK,         /*!< Pin reset interrupt.        */
+    kSMC_IntMdm = SMC_SRIE_MDM_MASK,         /*!< MDM reset interrupt.        */
+    kSMC_IntStopAck = SMC_SRIE_STOPACK_MASK, /*!< Stop timeout reset interrupt.  */
+    kSMC_IntWdog = SMC_SRIE_WDOG_MASK,       /*!< Watchdog interrupt.         */
+    kSMC_IntSoftware = SMC_SRIE_SW_MASK,     /*!< Software reset interrupts.  */
+    kSMC_IntLockup = SMC_SRIE_LOCKUP_MASK,   /*!< Lock up interrupt.          */
+#if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE0) && FSL_FEATURE_SMC_HAS_CSRE_CORE0)
+    kSMC_IntCore0 = SMC_SRIE_CORE0_MASK, /*! Core 0 interrupts. */
+#endif                                   /* FSL_FEATURE_SMC_HAS_CSRE_CORE0 */
+#if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE1) && FSL_FEATURE_SMC_HAS_CSRE_CORE1)
+    kSMC_IntCore1 = SMC_SRIE_CORE1_MASK, /*! Core 1 interrupts. */
+#endif                                   /* FSL_FEATURE_SMC_HAS_CSRE_CORE1 */
+    kSMC_IntAll = SMC_SRIE_PIN_MASK |    /*!< All system reset interrupts.      */
+                  SMC_SRIE_MDM_MASK |
+                  SMC_SRIE_STOPACK_MASK | SMC_SRIE_WDOG_MASK | SMC_SRIE_SW_MASK | SMC_SRIE_LOCKUP_MASK
+#if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE0) && FSL_FEATURE_SMC_HAS_CSRE_CORE0)
+                  |
+                  SMC_SRIE_CORE0_MASK
+#endif /* FSL_FEATURE_SMC_HAS_CSRE_CORE0 */
+#if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE1) && FSL_FEATURE_SMC_HAS_CSRE_CORE1)
+                  |
+                  SMC_SRIE_CORE1_MASK
+#endif /* FSL_FEATURE_SMC_HAS_CSRE_CORE1 */
+} smc_interrupt_enable_t;
+
+/*!
+ * @brief Reset pin filter configuration
+ */
+typedef struct _smc_reset_pin_filter_config
+{
+    uint8_t slowClockFilterCount; /*!< Reset pin bus clock filter width from 1 to 32 slow clock cycles.  */
+    bool enableFilter;            /*!< Reset pin filter enable/disable. */
+#if (defined(FSL_FEATURE_SMC_HAS_RPC_LPOFEN) && FSL_FEATURE_SMC_HAS_RPC_LPOFEN)
+    bool enableLpoFilter; /*!< LPO clock reset pin filter enabled in all modes. */
+#endif                    /* FSL_FEATURE_SMC_HAS_RPC_LPOFEN */
+} smc_reset_pin_filter_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name System mode controller APIs*/
+/*@{*/
+
+/*!
+ * @brief Configures all power mode protection settings.
+ *
+ * This function  configures the power mode protection settings for
+ * supported power modes in the specified chip family. The available power modes
+ * are defined in the smc_power_mode_protection_t. This should be done at an early
+ * system level initialization stage. See the reference manual for details.
+ * This register can only write once after the power reset.
+ *
+ * The allowed modes are passed as bit map, for example, to allow LLS and VLLS,
+ * use SMC_SetPowerModeProtection(kSMC_AllowPowerModeLls | kSMC_AllowPowerModeVlls).
+ * To allow all modes, use SMC_SetPowerModeProtection(kSMC_AllowPowerModeAll).
+ *
+ * @param allowedModes Bitmap of the allowed power modes.
+ */
+static inline void SMC_SetPowerModeProtection(SMC_Type *base, uint8_t allowedModes)
+{
+    base->PMPROT = allowedModes;
+}
+
+/*!
+ * @brief Gets the current power mode status.
+ *
+ * This function  returns the current power mode stat. Once application
+ * switches the power mode, it should always check the stat to check whether it
+ * runs into the specified mode or not. An application  should  check
+ * this mode before switching to a different mode. The system  requires that
+ * only certain modes can switch to other specific modes. See the
+ * reference manual for details and the smc_power_state_t for information about
+ * the power stat.
+ *
+ * @param base SMC peripheral base address.
+ * @return Current power mode status.
+ */
+static inline smc_power_state_t SMC_GetPowerModeState(SMC_Type *base)
+{
+    return (smc_power_state_t)((base->PMSTAT & SMC_PMSTAT_PMSTAT_MASK) >> SMC_PMSTAT_PMSTAT_SHIFT);
+}
+
+#if (defined(FSL_FEATURE_SMC_HAS_PMSTAT_STOPSTAT) && FSL_FEATURE_SMC_HAS_PMSTAT_STOPSTAT)
+/*!
+ * @brief Gets the result of the previous stop mode entry.
+ *
+ * This function  returns the result of the previous stop mode entry.
+ *
+ * @param base SMC peripheral base address.
+ * @return Current power stop entry status.
+ */
+static inline smc_power_stop_entry_status_t SMC_GetStopEntryStatus(SMC_Type *base)
+{
+    return (smc_power_stop_entry_status_t)((base->PMSTAT & SMC_PMSTAT_STOPSTAT_MASK) >> SMC_PMSTAT_STOPSTAT_SHIFT);
+}
+
+/*!
+ * @brief Clears all the result of the previous stop mode entry.
+ *
+ * This function clears all the result of the previous stop mode entry.
+ *
+ * @param base SMC peripheral base address.
+ * @return Current power stop entry status.
+ */
+static inline void SMC_ClearStopEntryStatus(SMC_Type *base)
+{
+    /* Only write 0x01 to clear this field, all other writes are ignored. */
+    base->PMSTAT = (base->PMSTAT & ~SMC_PMSTAT_STOPSTAT_MASK) | SMC_PMSTAT_STOPSTAT(0x01);
+}
+
+#endif /* FSL_FEATURE_SMC_HAS_PMSTAT_STOPSTAT */
+
+/*!
+ * @brief Prepare to enter stop modes
+ *
+ * This function should be called before entering STOP/VLPS/LLS/VLLS modes.
+ */
+static inline void SMC_PreEnterStopModes(void)
+{
+    __disable_irq();
+    __ISB();
+}
+
+/*!
+ * @brief Recovering after wake up from stop modes
+ *
+ * This function should be called after wake up from STOP/VLPS/LLS/VLLS modes.
+ * It is used together with @ref SMC_PreEnterStopModes.
+ */
+static inline void SMC_PostExitStopModes(void)
+{
+    __enable_irq();
+    __ISB();
+}
+
+/*!
+ * @brief Prepare to enter wait modes
+ *
+ * This function should be called before entering WAIT/VLPW modes..
+ */
+static inline void SMC_PreEnterWaitModes(void)
+{
+    __disable_irq();
+    __ISB();
+}
+
+/*!
+ * @brief Recovering after wake up from stop modes
+ *
+ * This function should be called after wake up from WAIT/VLPW modes.
+ * It is used together with @ref SMC_PreEnterWaitModes.
+ */
+static inline void SMC_PostExitWaitModes(void)
+{
+    __enable_irq();
+    __ISB();
+}
+
+/*!
+ * @brief Configure the system to RUN power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeRun(SMC_Type *base);
+
+/*!
+ * @brief Configure the system to HSRUN power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeHsrun(SMC_Type *base);
+
+/*!
+ * @brief Configure the system to WAIT power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeWait(SMC_Type *base);
+
+/*!
+ * @brief Configure the system to Stop power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @param  option Partial Stop mode option.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option);
+
+/*!
+ * @brief Configure the system to VLPR power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlpr(SMC_Type *base);
+
+/*!
+ * @brief Configure the system to VLPW power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlpw(SMC_Type *base);
+
+/*!
+ * @brief Configure the system to VLPS power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlps(SMC_Type *base);
+/*!
+ * @brief Configure the system to LLS power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeLls(SMC_Type *base);
+
+#if (defined(FSL_FEATURE_SMC_HAS_SUB_STOP_MODE) && FSL_FEATURE_SMC_HAS_SUB_STOP_MODE)
+#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE0) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE0)
+/*!
+ * @brief Configure the system to VLLS0 power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlls0(SMC_Type *base);
+#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */
+#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE2) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE2)
+/*!
+ * @brief Configure the system to VLLS2 power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlls2(SMC_Type *base);
+#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 */
+#else
+                        /*!
+                         * @brief Configure the system to VLLS power mode.
+                         *
+                         * @param base SMC peripheral base address.
+                         * @return SMC configuration error code.
+                         */
+status_t SMC_SetPowerModeVlls(SMC_Type *base);
+#endif /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */
+
+/*!
+ * @brief Gets the reset source status which caused a previous reset.
+ *
+ * This function gets the current reset source status. Use source masks
+ * defined in the smc_reset_source_t to get the desired source status.
+ *
+ * Example:
+   @code
+   uint32_t resetStatus;
+
+   // To get all reset source statuses.
+   resetStatus = SMC_GetPreviousResetSources(SMC0) & kSMC_SourceAll;
+
+   // To test whether the MCU is reset using Watchdog.
+   resetStatus = SMC_GetPreviousResetSources(SMC0) & kSMC_SourceWdog;
+
+   // To test multiple reset sources.
+   resetStatus = SMC_GetPreviousResetSources(SMC0) & (kSMC_SourceWdog | kSMC_SourcePin);
+   @endcode
+ *
+ * @param base SMC peripheral base address.
+ * @return All reset source status bit map.
+ */
+static inline uint32_t SMC_GetPreviousResetSources(SMC_Type *base)
+{
+    return base->SRS;
+}
+
+/*!
+ * @brief Gets the sticky reset source status.
+ *
+ * This function gets the current reset source status that has not been cleared
+ * by software for some specific source.
+ *
+ * Example:
+   @code
+   uint32_t resetStatus;
+
+   // To get all reset source statuses.
+   resetStatus = SMC_GetStickyResetSources(SMC0) & kSMC_SourceAll;
+
+   // To test whether the MCU is reset using Watchdog.
+   resetStatus = SMC_GetStickyResetSources(SMC0) & kSMC_SourceWdog;
+
+   // To test multiple reset sources.
+   resetStatus = SMC_GetStickyResetSources(SMC0) & (kSMC_SourceWdog | kSMC_SourcePin);
+   @endcode
+ *
+ * @param base SMC peripheral base address.
+ * @return All reset source status bit map.
+ */
+static inline uint32_t SMC_GetStickyResetSources(SMC_Type *base)
+{
+    return base->SSRS;
+}
+
+/*!
+ * @brief Clears the sticky reset source status.
+ *
+ * This function clears the sticky system reset flags indicated by source masks.
+ *
+ * Example:
+   @code
+   // Clears multiple reset sources.
+   SMC_ClearStickyResetSources(SMC0, (kSMC_SourceWdog | kSMC_SourcePin));
+   @endcode
+ *
+ * @param base SMC peripheral base address.
+ * @param sourceMasks reset source status bit map
+ */
+static inline void SMC_ClearStickyResetSources(SMC_Type *base, uint32_t sourceMasks)
+{
+    base->SSRS = sourceMasks;
+}
+
+/*!
+ * @brief Configures the reset pin filter.
+ *
+ * This function sets the reset pin filter including the enablement/disablement and filter width.
+ *
+ * @param base SMC peripheral base address.
+ * @param config Pointer to the configuration structure.
+ */
+void SMC_ConfigureResetPinFilter(SMC_Type *base, const smc_reset_pin_filter_config_t *config);
+
+/*!
+ * @brief Sets the system reset interrupt configuration.
+ *
+ * For a graceful shut down, the MSMC supports delaying the assertion of the system
+ * reset for a period of time when the reset interrupt is generated. This function
+ * can be used to enable the interrupt.
+ * The interrupts are passed in as bit mask. See smc_interrupt_enable_t for details.
+ * For example, to delay a reset after the WDOG timeout or PIN reset occurs, configure as follows:
+ * SMC_SetSystemResetInterruptConfig(SMC0, (kSMC_IntWdog | kSMC_IntPin));
+ *
+ * @param base SMC peripheral base address.
+ * @param intMask   Bit mask of the system reset interrupts to enable. See
+ *                  smc_interrupt_enable_t for details.
+ */
+static inline void SMC_SetSystemResetInterruptConfig(SMC_Type *base, uint32_t intMask)
+{
+    base->SRIE = intMask;
+}
+
+/*!
+ * @brief Gets the source status of the system reset interrupt.
+ *
+ * This function gets the source status of the reset interrupt. Use source masks
+ * defined in the smc_interrupt_enable_t to get the desired source status.
+ *
+ * Example:
+   @code
+   uint32_t interruptStatus;
+
+   // To get all reset interrupt source statuses.
+   interruptStatus = SMC_GetResetInterruptSourcesStatus(SMC0) & kSMC_IntAll;
+
+   // To test whether the reset interrupt of Watchdog is pending.
+   interruptStatus = SMC_GetResetInterruptSourcesStatus(SMC0) & kSMC_IntWdog;
+
+   // To test multiple reset interrupt sources.
+   interruptStatus = SMC_GetResetInterruptSourcesStatus(SMC0) & (kSMC_IntWdog | kSMC_IntPin);
+   @endcode
+ *
+ * @param base SMC peripheral base address.
+ * @return All reset interrupt source status bit map.
+ */
+static inline uint32_t SMC_GetResetInterruptSourcesStatus(SMC_Type *base)
+{
+    return base->SRIF;
+}
+
+/*!
+ * @brief Clears the source status of the system reset interrupt.
+ *
+ * This function clears the source status of the reset interrupt. Use source masks
+ * defined in the smc_interrupt_enable_t to get the desired source status.
+ *
+ * Example:
+   @code
+   uint32_t interruptStatus;
+
+   // To clear all reset interrupt source statuses.
+   MMC_ClearResetInterruptSourcesStatus(SMC0, kSMC_IntAll);
+
+   // To clear the reset interrupt of Watchdog.
+   SMC_ClearResetInterruptSourcesStatus(SMC0, kSMC_IntWdog);
+
+   // To clear multiple reset interrupt sources status.
+   SMC_ClearResetInterruptSourcesStatus(SMC0, (kSMC_IntWdog | kSMC_IntPin));
+   @endcode
+ *
+ * @param base SMC peripheral base address.
+ * @param All reset interrupt source status bit map to clear.
+ */
+static inline void SMC_ClearResetInterruptSourcesStatus(SMC_Type *base, uint32_t intMask)
+{
+    base->SRIF = intMask;
+}
+
+#if (defined(FSL_FEATURE_SMC_HAS_CSRE) && FSL_FEATURE_SMC_HAS_CSRE)
+/*!
+ * @brief Sets the core software reset feature configuration.
+ *
+ * The MSMC supports delaying the assertion of the system reset for a period of time while a core
+ * software reset is generated. This allows software to recover without reseting the entire system.
+ * This function can be used to enable/disable the core software reset feature.
+ * The interrupts are passed in as bit mask. See smc_interrupt_enable_t for details.
+ * For example, to delay a system after the WDOG timeout or PIN core software reset occurs, configure as follows:
+ * SMC_SetCoreSoftwareResetConfig(SMC0, (kSMC_IntWdog | kSMC_IntPin));
+ *
+ * @param base SMC peripheral base address.
+ * @param intMask   Bit mask of the core software reset to enable. See
+ *                  smc_interrupt_enable_t for details.
+ */
+static inline void SMC_SetCoreSoftwareResetConfig(SMC_Type *base, uint32_t intMask)
+{
+    base->CSRE = intMask;
+}
+#endif /* FSL_FEATURE_SMC_HAS_CSRE */
+
+/*!
+ * @brief Gets the boot option configuration.
+ *
+ * This function gets the boot option configuration of MSMC.
+ *
+ * @param base SMC peripheral base address.
+ * @return The boot option configuration. 1 means boot option enabled. 0 means not.
+ */
+static inline uint32_t SMC_GetBootOptionConfig(SMC_Type *base)
+{
+    return base->MR;
+}
+
+#if (defined(FSL_FEATURE_SMC_HAS_FM) && FSL_FEATURE_SMC_HAS_FM)
+/*!
+ * @brief Sets the force boot option configuration.
+ *
+ * This function sets the focus boot option configuration of MSMC. It can force the corresponding
+ * boot option config to assert on next system reset.
+ *
+ * @param base SMC peripheral base address.
+ * @param val The boot option configuration for next system reset. 1 - boot option enabled. 0 - not.
+ */
+static inline void SMC_SetForceBootOptionConfig(SMC_Type *base, uint32_t val)
+{
+    base->FM = val;
+}
+
+#if (defined(FSL_FEATURE_SMC_HAS_SRAMLPR) && FSL_FEATURE_SMC_HAS_SRAMLPR)
+/*!
+ * @brief Enables the conresponding SRAM array in low power retention mode.
+ *
+ * This function enables the conresponding SRAM array in low power retention mode. By default, the SRAM low pwer is
+ * disabled, and only in RUN mode.
+ *
+ * @param base SMC peripheral base address.
+ * @param arrayIdx Index of responding SRAM array.
+ * @param enable Enable the SRAM array in low power retention mode.
+ */
+static inline void SMC_SRAMEnableLowPowerMode(SMC_Type *base, uint32_t arrayIdx, bool enable)
+{
+    if (enable)
+    {
+        base->SRAMLPR |= (1U << arrayIdx); /* Set to be placed in RUN modes. */
+    }
+    else
+    {
+        base->SRAMLPR &= ~(1U << arrayIdx); /* Clear to be placed in low power retention mode. */
+    }
+}
+#endif /* FSL_FEATURE_SMC_HAS_SRAMLPR */
+
+#if (defined(FSL_FEATURE_SMC_HAS_SRAMDSR) && FSL_FEATURE_SMC_HAS_SRAMDSR)
+/*!
+ * @brief Enables the conresponding SRAM array in STOP mode.
+ *
+ * This function enables the conresponding SRAM array in STOP modes. By default, the SRAM is retained in STOP modes.
+ * When disabled, the corresponding SRAM array is powered off in STOP modes.
+ *
+ * @param base SMC peripheral base address.
+ * @param arrayIdx Index of responding SRAM array.
+ * @param enable Enable the SRAM array in STOP modes.
+ */
+static inline void SMC_SRAMEnableDeepSleepMode(SMC_Type *base, uint32_t arrayIdx, bool enable)
+{
+    if (enable)
+    {
+        base->SRAMDSR &= ~(1U << arrayIdx); /* Clear to be retained in STOP modes. */
+    }
+    else
+    {
+        base->SRAMDSR |= (1U << arrayIdx); /* Set to be powered off in STOP modes. */
+    }
+}
+#endif /* FSL_FEATURE_SMC_HAS_SRAMDSR */
+
+#endif /* FSL_FEATURE_SMC_HAS_FM */
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* _FSL_MSMC_H_ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_port.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_port.h
new file mode 100644
index 0000000..e0e808c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_port.h
@@ -0,0 +1,464 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_PORT_H_
+#define _FSL_PORT_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup port
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! Version 2.0.2. */
+#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
+/*! @brief Internal resistor pull feature selection */
+enum _port_pull
+{
+    kPORT_PullDisable = 0U, /*!< Internal pull-up/down resistor is disabled. */
+    kPORT_PullDown = 2U,    /*!< Internal pull-down resistor is enabled. */
+    kPORT_PullUp = 3U,      /*!< Internal pull-up resistor is enabled. */
+};
+#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
+
+#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
+/*! @brief Slew rate selection */
+enum _port_slew_rate
+{
+    kPORT_FastSlewRate = 0U, /*!< Fast slew rate is configured. */
+    kPORT_SlowSlewRate = 1U, /*!< Slow slew rate is configured. */
+};
+#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
+
+#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
+/*! @brief Open Drain feature enable/disable */
+enum _port_open_drain_enable
+{
+    kPORT_OpenDrainDisable = 0U, /*!< Open drain output is disabled. */
+    kPORT_OpenDrainEnable = 1U,  /*!< Open drain output is enabled. */
+};
+#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
+
+#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
+/*! @brief Passive filter feature enable/disable */
+enum _port_passive_filter_enable
+{
+    kPORT_PassiveFilterDisable = 0U, /*!< Passive input filter is disabled. */
+    kPORT_PassiveFilterEnable = 1U,  /*!< Passive input filter is enabled. */
+};
+#endif
+
+#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
+/*! @brief Configures the drive strength. */
+enum _port_drive_strength
+{
+    kPORT_LowDriveStrength = 0U,  /*!< Low-drive strength is configured. */
+    kPORT_HighDriveStrength = 1U, /*!< High-drive strength is configured. */
+};
+#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */
+
+#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
+/*! @brief Unlock/lock the pin control register field[15:0] */
+enum _port_lock_register
+{
+    kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */
+    kPORT_LockRegister = 1U,   /*!< Pin Control Register fields [15:0] are locked. */
+};
+#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
+
+#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
+/*! @brief Pin mux selection */
+typedef enum _port_mux
+{
+    kPORT_PinDisabledOrAnalog = 0U, /*!< Corresponding pin is disabled, but is used as an analog pin. */
+    kPORT_MuxAsGpio = 1U,           /*!< Corresponding pin is configured as GPIO. */
+    kPORT_MuxAlt2 = 2U,             /*!< Chip-specific */
+    kPORT_MuxAlt3 = 3U,             /*!< Chip-specific */
+    kPORT_MuxAlt4 = 4U,             /*!< Chip-specific */
+    kPORT_MuxAlt5 = 5U,             /*!< Chip-specific */
+    kPORT_MuxAlt6 = 6U,             /*!< Chip-specific */
+    kPORT_MuxAlt7 = 7U,             /*!< Chip-specific */
+    kPORT_MuxAlt8 = 8U,             /*!< Chip-specific */
+    kPORT_MuxAlt9 = 9U,             /*!< Chip-specific */
+    kPORT_MuxAlt10 = 10U,           /*!< Chip-specific */
+    kPORT_MuxAlt11 = 11U,           /*!< Chip-specific */
+    kPORT_MuxAlt12 = 12U,           /*!< Chip-specific */
+    kPORT_MuxAlt13 = 13U,           /*!< Chip-specific */
+    kPORT_MuxAlt14 = 14U,           /*!< Chip-specific */
+    kPORT_MuxAlt15 = 15U,           /*!< Chip-specific */
+} port_mux_t;
+#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
+
+/*! @brief Configures the interrupt generation condition. */
+typedef enum _port_interrupt
+{
+    kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */
+#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST
+    kPORT_DMARisingEdge = 0x1U,  /*!< DMA request on rising edge. */
+    kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */
+    kPORT_DMAEitherEdge = 0x3U,  /*!< DMA request on either edge. */
+#endif
+#if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG
+    kPORT_FlagRisingEdge = 0x05U,  /*!< Flag sets on rising edge. */
+    kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */
+    kPORT_FlagEitherEdge = 0x07U,  /*!< Flag sets on either edge. */
+#endif
+    kPORT_InterruptLogicZero = 0x8U,   /*!< Interrupt when logic zero. */
+    kPORT_InterruptRisingEdge = 0x9U,  /*!< Interrupt on rising edge. */
+    kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */
+    kPORT_InterruptEitherEdge = 0xBU,  /*!< Interrupt on either edge. */
+    kPORT_InterruptLogicOne = 0xCU,    /*!< Interrupt when logic one. */
+#if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER
+    kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */
+    kPORT_ActiveLowTriggerOutputEnable = 0xEU,  /*!< Enable active low-trigger output. */
+#endif
+} port_interrupt_t;
+
+#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
+/*! @brief Digital filter clock source selection */
+typedef enum _port_digital_filter_clock_source
+{
+    kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */
+    kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */
+} port_digital_filter_clock_source_t;
+
+/*! @brief PORT digital filter feature configuration definition */
+typedef struct _port_digital_filter_config
+{
+    uint32_t digitalFilterWidth;                    /*!< Set digital filter width */
+    port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */
+} port_digital_filter_config_t;
+#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
+
+#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
+/*! @brief PORT pin configuration structure */
+typedef struct _port_pin_config
+{
+#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
+    uint16_t pullSelect : 2; /*!< No-pull/pull-down/pull-up select */
+#else
+    uint16_t : 2;
+#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
+
+#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
+    uint16_t slewRate : 1; /*!< Fast/slow slew rate Configure */
+#else
+    uint16_t : 1;
+#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
+
+    uint16_t : 1;
+
+#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
+    uint16_t passiveFilterEnable : 1; /*!< Passive filter enable/disable */
+#else
+    uint16_t : 1;
+#endif /* FSL_FEATURE_PORT_HAS_PASSIVE_FILTER */
+
+#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
+    uint16_t openDrainEnable : 1; /*!< Open drain enable/disable */
+#else
+    uint16_t : 1;
+#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
+
+#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
+    uint16_t driveStrength : 1; /*!< Fast/slow drive strength configure */
+#else
+    uint16_t : 1;
+#endif
+
+    uint16_t : 1;
+
+#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 3)
+    uint16_t mux : 3; /*!< Pin mux Configure */
+    uint16_t : 4;
+#elif defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 4)
+    uint16_t mux : 4; /*!< Pin mux Configure */
+    uint16_t : 3;
+#else
+    uint16_t : 7,
+#endif
+
+#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
+    uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */
+#else
+    uint16_t : 1;
+#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
+} port_pin_config_t;
+#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
+
+/*******************************************************************************
+* API
+******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the port PCR register.
+ *
+ * This is an example to define an input pin or output pin PCR configuration.
+ * @code
+ * // Define a digital input pin PCR configuration
+ * port_pin_config_t config = {
+ *      kPORT_PullUp,
+ *      kPORT_FastSlewRate,
+ *      kPORT_PassiveFilterDisable,
+ *      kPORT_OpenDrainDisable,
+ *      kPORT_LowDriveStrength,
+ *      kPORT_MuxAsGpio,
+ *      kPORT_UnLockRegister,
+ * };
+ * @endcode
+ *
+ * @param base   PORT peripheral base pointer.
+ * @param pin    PORT pin number.
+ * @param config PORT PCR register configuration structure.
+ */
+static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)
+{
+    assert(config);
+    uint32_t addr = (uint32_t)&base->PCR[pin];
+    *(volatile uint16_t *)(addr) = *((const uint16_t *)config);
+}
+
+/*!
+ * @brief Sets the port PCR register for multiple pins.
+ *
+ * This is an example to define input pins or output pins PCR configuration.
+ * @code
+ * // Define a digital input pin PCR configuration
+ * port_pin_config_t config = {
+ *      kPORT_PullUp ,
+ *      kPORT_PullEnable,
+ *      kPORT_FastSlewRate,
+ *      kPORT_PassiveFilterDisable,
+ *      kPORT_OpenDrainDisable,
+ *      kPORT_LowDriveStrength,
+ *      kPORT_MuxAsGpio,
+ *      kPORT_UnlockRegister,
+ * };
+ * @endcode
+ *
+ * @param base   PORT peripheral base pointer.
+ * @param mask   PORT pin number macro.
+ * @param config PORT PCR register configuration structure.
+ */
+static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)
+{
+    assert(config);
+
+    uint16_t pcrl = *((const uint16_t *)config);
+
+    if (mask & 0xffffU)
+    {
+        base->GPCLR = ((mask & 0xffffU) << 16) | pcrl;
+    }
+    if (mask >> 16)
+    {
+        base->GPCHR = (mask & 0xffff0000U) | pcrl;
+    }
+}
+
+#if defined(FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG) && FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG
+/*!
+ * @brief Sets the port interrupt configuration in PCR register for multiple pins.
+ *
+ * @param base   PORT peripheral base pointer.
+ * @param mask   PORT pin number macro.
+ * @param config  PORT pin interrupt configuration.
+ *        - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
+ *        - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
+ *        - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
+ *        - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
+ *        - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
+ *        - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
+ *        - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
+ *        - #kPORT_InterruptLogicZero  : Interrupt when logic zero.
+ *        - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
+ *        - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
+ *        - #kPORT_InterruptEitherEdge : Interrupt on either edge.
+ *        - #kPORT_InterruptLogicOne   : Interrupt when logic one.
+ *        - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
+ *        - #kPORT_ActiveLowTriggerOutputEnable  : Enable active low-trigger output (if the trigger states exit)..
+ */
+static inline void PORT_SetMultipleInterruptPinsConfig(PORT_Type *base, uint32_t mask, port_interrupt_t config)
+{
+    assert(config);
+
+    if (mask & 0xffffU)
+    {
+        base->GICLR = (config << 16) | (mask & 0xffffU);
+    }
+    if (mask >> 16)
+    {
+        base->GICHR = (config << 16) | (mask & 0xffff0000U);
+    }
+}
+#endif
+
+/*!
+ * @brief Configures the pin muxing.
+ *
+ * @param base  PORT peripheral base pointer.
+ * @param pin   PORT pin number.
+ * @param mux   pin muxing slot selection.
+ *        - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function.
+ *        - #kPORT_MuxAsGpio          : Set as GPIO.
+ *        - #kPORT_MuxAlt2            : chip-specific.
+ *        - #kPORT_MuxAlt3            : chip-specific.
+ *        - #kPORT_MuxAlt4            : chip-specific.
+ *        - #kPORT_MuxAlt5            : chip-specific.
+ *        - #kPORT_MuxAlt6            : chip-specific.
+ *        - #kPORT_MuxAlt7            : chip-specific.
+ * @Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because
+ *         the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is
+ *         reset to zero : kPORT_PinDisabledOrAnalog).
+ *        This function is recommended to use to reset the pin mux
+ *
+ */
+static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)
+{
+    base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux);
+}
+#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
+
+#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
+
+/*!
+ * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin.
+ *
+ * @param base  PORT peripheral base pointer.
+ * @param mask  PORT pin number macro.
+ */
+static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)
+{
+    if (enable == true)
+    {
+        base->DFER |= mask;
+    }
+    else
+    {
+        base->DFER &= ~mask;
+    }
+}
+
+/*!
+ * @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin.
+ *
+ * @param base   PORT peripheral base pointer.
+ * @param config PORT digital filter configuration structure.
+ */
+static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config)
+{
+    assert(config);
+
+    base->DFCR = PORT_DFCR_CS(config->clockSource);
+    base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth);
+}
+
+#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
+
+/*@}*/
+
+/*! @name Interrupt */
+/*@{*/
+
+/*!
+ * @brief Configures the port pin interrupt/DMA request.
+ *
+ * @param base    PORT peripheral base pointer.
+ * @param pin     PORT pin number.
+ * @param config  PORT pin interrupt configuration.
+ *        - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
+ *        - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
+ *        - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
+ *        - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
+ *        - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
+ *        - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
+ *        - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
+ *        - #kPORT_InterruptLogicZero  : Interrupt when logic zero.
+ *        - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
+ *        - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
+ *        - #kPORT_InterruptEitherEdge : Interrupt on either edge.
+ *        - #kPORT_InterruptLogicOne   : Interrupt when logic one.
+ *        - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
+ *        - #kPORT_ActiveLowTriggerOutputEnable  : Enable active low-trigger output (if the trigger states exit).
+ */
+static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config)
+{
+    base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config);
+}
+
+#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
+/*!
+ * @brief Configures the port pin drive strength.
+ *
+ * @param base    PORT peripheral base pointer.
+ * @param pin     PORT pin number.
+ * @param config  PORT pin drive strength
+ *        - #kPORT_LowDriveStrength = 0U - Low-drive strength is configured.
+ *        - #kPORT_HighDriveStrength = 1U - High-drive strength is configured.
+ */
+static inline void PORT_SetPinDriveStrength(PORT_Type* base, uint32_t pin, uint8_t strength)
+{
+    base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE_MASK) |  PORT_PCR_DSE(strength);
+}
+#endif
+
+/*!
+ * @brief Reads the whole port status flag.
+ *
+ * If a pin is configured to generate the DMA request,  the corresponding flag
+ * is cleared automatically at the completion of the requested DMA transfer.
+ * Otherwise, the flag remains set until a logic one is written to that flag.
+ * If configured for a level sensitive interrupt that remains asserted, the flag
+ * is set again immediately.
+ *
+ * @param base PORT peripheral base pointer.
+ * @return Current port interrupt status flags, for example, 0x00010001 means the
+ *         pin 0 and 16 have the interrupt.
+ */
+static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base)
+{
+    return base->ISFR;
+}
+
+/*!
+ * @brief Clears the multiple pin interrupt status flag.
+ *
+ * @param base PORT peripheral base pointer.
+ * @param mask PORT pin number macro.
+ */
+static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask)
+{
+    base->ISFR = mask;
+}
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_PORT_H_ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/fsl_device_registers.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/fsl_device_registers.h
new file mode 100644
index 0000000..391d54f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/fsl_device_registers.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if defined(CPU_RV32M1_cm0plus)
+
+#define RV32M1_cm0plus_SERIES
+
+/* CMSIS-style register definitions */
+#include "RV32M1_cm0plus.h"
+/* CPU specific feature definitions */
+#include "RV32M1_cm0plus_features.h"
+
+#elif defined(CPU_RV32M1_cm4)
+
+#define RV32M1_cm4_SERIES
+
+/* CMSIS-style register definitions */
+#include "RV32M1_cm4.h"
+/* CPU specific feature definitions */
+#include "RV32M1_cm4_features.h"
+
+#elif defined(CPU_RV32M1_zero_riscy)
+
+#define RV32M1_zero_riscy_SERIES
+
+/* CMSIS-style register definitions */
+#include "RV32M1_zero_riscy.h"
+/* CPU specific feature definitions */
+#include "RV32M1_zero_riscy_features.h"
+
+#elif defined(CPU_RV32M1_ri5cy)
+
+#define RV32M1_ri5cy_SERIES
+
+/* CMSIS-style register definitions */
+#include "RV32M1_ri5cy.h"
+/* CPU specific feature definitions */
+#include "RV32M1_ri5cy_features.h"
+
+#else
+    #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/gcc/startup_RV32M1_ri5cy.S b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/gcc/startup_RV32M1_ri5cy.S
new file mode 100644
index 0000000..f6b382c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/gcc/startup_RV32M1_ri5cy.S
@@ -0,0 +1,228 @@
+/* ------------------------------------------------------------------------- */
+/*  @file:    startup_RV32M1_ri5cy.s                                         */
+/*  @purpose: RI5CY Core Device Startup File                                 */
+/*            RV32M1_ri5cy                                                   */
+/*  @version: 1.0                                                            */
+/*  @date:    2018-10-2                                                      */
+/*  @build:   b180926                                                        */
+/* ------------------------------------------------------------------------- */
+/*                                                                           */
+/* Copyright 1997-2016 Freescale Semiconductor, Inc.                         */
+/* Copyright 2016-2018 NXP                                                   */
+/* All rights reserved.                                                      */
+/*                                                                           */
+/* SPDX-License-Identifier: BSD-3-Clause                                     */
+
+
+// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+.extern freertos_risc_v_trap_handler
+
+#define EXCEPTION_STACK_SIZE 0x58
+
+    .text
+    .section .vectors, "ax"
+    .option norvc;
+
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+
+    // reset vector
+    jal x0, Reset_Handler
+
+    // Illegal instrution exception
+    jal x0, IllegalInstruction_Handler
+
+    // ecall handler
+    jal x0, freertos_risc_v_trap_handler
+
+    // LSU error
+    jal x0, LSU_Handler
+
+    .section .startup
+
+/* Reset Handler */
+Reset_Handler:
+
+    # Disable global interrupt. */
+    csrci mstatus, 8
+
+    # initialize stack pointer
+    la sp, __StackTop
+
+    # initialize global pointer
+    la gp, __global_pointer
+
+#ifndef __NO_SYSTEM_INIT
+    jal SystemInit
+#endif
+
+    call __libc_init_array
+
+    # Enable global interrupt. */
+    csrsi mstatus, 8
+
+    jal main
+    ebreak
+
+    .size Reset_Handler, . - Reset_Handler
+
+    .global _init
+    .global _fini
+_init:
+_fini:
+    ret
+
+  // saves all caller-saved registers (except return address)
+store_regs:
+    sw  x3, 0x00(x2)  // gp
+    sw  x4, 0x04(x2)  // tp
+    sw  x5, 0x08(x2)  // t0
+    sw  x6, 0x0c(x2)  // t1
+    sw  x7, 0x10(x2)  // t2
+    sw x10, 0x14(x2)  // a0
+    sw x11, 0x18(x2)  // a1
+    sw x12, 0x1c(x2)  // a2
+    sw x13, 0x20(x2)  // a3
+    sw x14, 0x24(x2)  // a4
+    sw x15, 0x28(x2)  // a5
+    sw x16, 0x2c(x2)  // a6
+    sw x17, 0x30(x2)  // a7
+
+    csrr a0, 0x7B0
+    csrr a1, 0x7B1
+    csrr a2, 0x7B2
+    sw a0, 0x34(x2)  // lpstart[0]
+    sw a1, 0x38(x2)  // lpend[0]
+    sw a2, 0x3c(x2)  // lpcount[0]
+    csrr a0, 0x7B4
+    csrr a1, 0x7B5
+    csrr a2, 0x7B6
+    sw a0, 0x40(x2)  // lpstart[1]
+    sw a1, 0x44(x2)  // lpend[1]
+    sw a2, 0x48(x2)  // lpcount[1]
+
+    csrr a0, 0x341
+    sw a0, 0x4c(x2)  // mepc
+    csrr a1, 0x300
+    sw a1, 0x50(x2)  // mstatus
+    jalr x0, x1
+
+    // load back registers from stack
+end_except:
+    lw a1, 0x50(x2)  // mstatus
+    csrrw x0, 0x300, a1
+    lw a0, 0x4c(x2)  // mepc
+    csrrw x0, 0x341, a0
+
+    lw a0, 0x40(x2)  // lpstart[1]
+    lw a1, 0x44(x2)  // lpend[1]
+    lw a2, 0x48(x2)  // lpcount[1]
+    csrrw x0, 0x7B4, a0
+    csrrw x0, 0x7B5, a1
+    csrrw x0, 0x7B6, a2
+    lw a0, 0x34(x2)  // lpstart[0]
+    lw a1, 0x38(x2)  // lpend[0]
+    lw a2, 0x3c(x2)  // lpcount[0]
+    csrrw x0, 0x7B0, a0
+    csrrw x0, 0x7B1, a1
+    csrrw x0, 0x7B2, a2
+
+    lw  x3, 0x00(x2)  // gp
+    lw  x4, 0x04(x2)  // tp
+    lw  x5, 0x08(x2)  // t0
+    lw  x6, 0x0c(x2)  // t1
+    lw  x7, 0x10(x2)  // t2
+    lw x10, 0x14(x2)  // a0
+    lw x11, 0x18(x2)  // a1
+    lw x12, 0x1c(x2)  // a2
+    lw x13, 0x20(x2)  // a3
+    lw x14, 0x24(x2)  // a4
+    lw x15, 0x28(x2)  // a5
+    lw x16, 0x2c(x2)  // a6
+    lw x17, 0x30(x2)  // a7
+
+    lw  x1, 0x54(x2)
+    addi x2, x2, EXCEPTION_STACK_SIZE
+    mret
+
+    .weak IRQ_Handler
+    .type IRQ_Handler, %function
+IRQ_Handler:
+    addi x2, x2, -EXCEPTION_STACK_SIZE
+    sw x1, 0x54(x2)
+    jal x1, store_regs
+    la x1, end_except
+    csrr a0, mcause
+    jal x0, SystemIrqHandler
+    .size IRQ_Handler, . - IRQ_Handler
+
+    .macro define_exception_entry entry_name handler_name
+    .weak \entry_name
+\entry_name:
+    addi x2, x2, -EXCEPTION_STACK_SIZE
+    sw x1, 0x54(x2)
+    jal x1, store_regs
+    la x1, end_except
+    jal x0, \handler_name
+    .endm
+
+define_exception_entry IllegalInstruction_Handler IllegalInstruction_HandlerFunc
+define_exception_entry Ecall_Handler Ecall_HandlerFunc
+define_exception_entry LSU_Handler LSU_HandlerFunc
+
+    .weak IllegalInstruction_HandlerFunc
+    .type IllegalInstruction_HandlerFunc, %function
+IllegalInstruction_HandlerFunc:
+    j .
+    .size IllegalInstruction_HandlerFunc, . - IllegalInstruction_HandlerFunc
+
+    .weak Ecall_HandlerFunc
+    .type Ecall_HandlerFunc, %function
+Ecall_HandlerFunc:
+    j .
+    .size Ecall_HandlerFunc, . - Ecall_HandlerFunc
+
+    .weak LSU_HandlerFunc
+    .type LSU_HandlerFunc, %function
+LSU_HandlerFunc:
+    j .
+    .size LSU_HandlerFunc, . - LSU_HandlerFunc
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/gcc/startup_RV32M1_zero_riscy.S b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/gcc/startup_RV32M1_zero_riscy.S
new file mode 100644
index 0000000..45bad81
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/gcc/startup_RV32M1_zero_riscy.S
@@ -0,0 +1,225 @@
+/* ------------------------------------------------------------------------- */
+/*  @file:    startup_RV32M1_zero_riscy.s                                    */
+/*  @purpose: ZERO_RISCY Core Device Startup File                            */
+/*            RV32M1_zero_riscy                                              */
+/*  @version: 1.0                                                            */
+/*  @date:    2018-10-2                                                      */
+/*  @build:   b180926                                                        */
+/* ------------------------------------------------------------------------- */
+/*                                                                           */
+/* Copyright 1997-2016 Freescale Semiconductor, Inc.                         */
+/* Copyright 2016-2018 NXP                                                   */
+/* All rights reserved.                                                      */
+/*                                                                           */
+/* SPDX-License-Identifier: BSD-3-Clause                                     */
+
+// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+#define EXCEPTION_STACK_SIZE 0x58
+
+    .text
+    .section .vectors, "ax"
+    .option norvc;
+
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+
+    // reset vector
+    jal x0, Reset_Handler
+
+    // Illegal instrution exception
+    jal x0, IllegalInstruction_Handler
+
+    // ecall handler
+    jal x0, Ecall_Handler
+
+    // LSU error
+    jal x0, LSU_Handler
+
+    .section .startup
+
+/* Reset Handler */
+Reset_Handler:
+
+    # Disable global interrupt. */
+    csrci mstatus, 8
+
+    # initialize stack pointer
+    la sp, __StackTop
+
+    # initialize global pointer
+    la gp, __global_pointer
+
+#ifndef __NO_SYSTEM_INIT
+    jal SystemInit
+#endif
+
+    call __libc_init_array
+
+    # Enable global interrupt. */
+    csrsi mstatus, 8
+
+    jal main
+    ebreak
+
+    .size Reset_Handler, . - Reset_Handler
+
+    .global _init
+    .global _fini
+_init:
+_fini:
+    ret
+
+  // saves all caller-saved registers (except return address)
+store_regs:
+    sw  x3, 0x00(x2)  // gp
+    sw  x4, 0x04(x2)  // tp
+    sw  x5, 0x08(x2)  // t0
+    sw  x6, 0x0c(x2)  // t1
+    sw  x7, 0x10(x2)  // t2
+    sw x10, 0x14(x2)  // a0
+    sw x11, 0x18(x2)  // a1
+    sw x12, 0x1c(x2)  // a2
+    sw x13, 0x20(x2)  // a3
+    sw x14, 0x24(x2)  // a4
+    sw x15, 0x28(x2)  // a5
+    sw x16, 0x2c(x2)  // a6
+    sw x17, 0x30(x2)  // a7
+
+    csrr a0, 0x7B0
+    csrr a1, 0x7B1
+    csrr a2, 0x7B2
+    sw a0, 0x34(x2)  // lpstart[0]
+    sw a1, 0x38(x2)  // lpend[0]
+    sw a2, 0x3c(x2)  // lpcount[0]
+    csrr a0, 0x7B4
+    csrr a1, 0x7B5
+    csrr a2, 0x7B6
+    sw a0, 0x40(x2)  // lpstart[1]
+    sw a1, 0x44(x2)  // lpend[1]
+    sw a2, 0x48(x2)  // lpcount[1]
+
+    csrr a0, 0x341
+    sw a0, 0x4c(x2)  // mepc
+    csrr a1, 0x300
+    sw a1, 0x50(x2)  // mstatus
+    jalr x0, x1
+
+    // load back registers from stack
+end_except:
+    lw a1, 0x50(x2)  // mstatus
+    csrrw x0, 0x300, a1
+    lw a0, 0x4c(x2)  // mepc
+    csrrw x0, 0x341, a0
+
+    lw a0, 0x40(x2)  // lpstart[1]
+    lw a1, 0x44(x2)  // lpend[1]
+    lw a2, 0x48(x2)  // lpcount[1]
+    csrrw x0, 0x7B4, a0
+    csrrw x0, 0x7B5, a1
+    csrrw x0, 0x7B6, a2
+    lw a0, 0x34(x2)  // lpstart[0]
+    lw a1, 0x38(x2)  // lpend[0]
+    lw a2, 0x3c(x2)  // lpcount[0]
+    csrrw x0, 0x7B0, a0
+    csrrw x0, 0x7B1, a1
+    csrrw x0, 0x7B2, a2
+
+    lw  x3, 0x00(x2)  // gp
+    lw  x4, 0x04(x2)  // tp
+    lw  x5, 0x08(x2)  // t0
+    lw  x6, 0x0c(x2)  // t1
+    lw  x7, 0x10(x2)  // t2
+    lw x10, 0x14(x2)  // a0
+    lw x11, 0x18(x2)  // a1
+    lw x12, 0x1c(x2)  // a2
+    lw x13, 0x20(x2)  // a3
+    lw x14, 0x24(x2)  // a4
+    lw x15, 0x28(x2)  // a5
+    lw x16, 0x2c(x2)  // a6
+    lw x17, 0x30(x2)  // a7
+
+    lw  x1, 0x54(x2)
+    addi x2, x2, EXCEPTION_STACK_SIZE
+    mret
+
+    .weak IRQ_Handler
+    .type IRQ_Handler, %function
+IRQ_Handler:
+    addi x2, x2, -EXCEPTION_STACK_SIZE
+    sw x1, 0x54(x2)
+    jal x1, store_regs
+    la x1, end_except
+    csrr a0, mcause
+    jal x0, SystemIrqHandler
+    .size IRQ_Handler, . - IRQ_Handler
+
+    .macro define_exception_entry entry_name handler_name
+    .weak \entry_name
+\entry_name:
+    addi x2, x2, -EXCEPTION_STACK_SIZE
+    sw x1, 0x54(x2)
+    jal x1, store_regs
+    la x1, end_except
+    jal x0, \handler_name
+    .endm
+
+define_exception_entry IllegalInstruction_Handler IllegalInstruction_HandlerFunc
+define_exception_entry Ecall_Handler Ecall_HandlerFunc
+define_exception_entry LSU_Handler LSU_HandlerFunc
+
+    .weak IllegalInstruction_HandlerFunc
+    .type IllegalInstruction_HandlerFunc, %function
+IllegalInstruction_HandlerFunc:
+    j .
+    .size IllegalInstruction_HandlerFunc, . - IllegalInstruction_HandlerFunc
+
+    .weak Ecall_HandlerFunc
+    .type Ecall_HandlerFunc, %function
+Ecall_HandlerFunc:
+    j .
+    .size Ecall_HandlerFunc, . - Ecall_HandlerFunc
+
+    .weak LSU_HandlerFunc
+    .type LSU_HandlerFunc, %function
+LSU_HandlerFunc:
+    j .
+    .size LSU_HandlerFunc, . - LSU_HandlerFunc
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_ri5cy.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_ri5cy.c
new file mode 100644
index 0000000..87838a8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_ri5cy.c
@@ -0,0 +1,556 @@
+/*
+** ###################################################################
+**     Processors:          RV32M1_ri5cy
+**                          RV32M1_ri5cy
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
+**     Version:             rev. 1.0, 2018-10-02
+**     Build:               b180926
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2018-10-02)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file RV32M1_ri5cy
+ * @version 1.0
+ * @date 2018-10-02
+ * @brief Device specific configuration file for RV32M1_ri5cy
+ *        (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include 
+#include "fsl_device_registers.h"
+#include "fsl_common.h"
+
+typedef void (*irq_handler_t)(void);
+
+extern void DMA0_0_4_8_12_DriverIRQHandler(void);
+extern void DMA0_1_5_9_13_DriverIRQHandler(void);
+extern void DMA0_2_6_10_14_DriverIRQHandler(void);
+extern void DMA0_3_7_11_15_DriverIRQHandler(void);
+extern void DMA0_Error_IRQHandler(void);
+extern void CMC0_IRQHandler(void);
+extern void EWM_IRQHandler(void);
+extern void FTFE_Command_Complete_IRQHandler(void);
+extern void FTFE_Read_Collision_IRQHandler(void);
+extern void LLWU0_IRQHandler(void);
+extern void MUA_IRQHandler(void);
+extern void SPM_IRQHandler(void);
+extern void WDOG0_IRQHandler(void);
+extern void SCG_IRQHandler(void);
+extern void LPIT0_IRQHandler(void);
+extern void RTC_IRQHandler(void);
+extern void LPTMR0_IRQHandler(void);
+extern void LPTMR1_IRQHandler(void);
+extern void TPM0_IRQHandler(void);
+extern void TPM1_IRQHandler(void);
+extern void TPM2_IRQHandler(void);
+extern void EMVSIM0_IRQHandler(void);
+extern void FLEXIO0_DriverIRQHandler(void);
+extern void LPI2C0_DriverIRQHandler(void);
+extern void LPI2C1_DriverIRQHandler(void);
+extern void LPI2C2_DriverIRQHandler(void);
+extern void I2S0_DriverIRQHandler(void);
+extern void USDHC0_DriverIRQHandler(void);
+extern void LPSPI0_DriverIRQHandler(void);
+extern void LPSPI1_DriverIRQHandler(void);
+extern void LPSPI2_DriverIRQHandler(void);
+extern void LPUART0_DriverIRQHandler(void);
+extern void LPUART1_DriverIRQHandler(void);
+extern void LPUART2_DriverIRQHandler(void);
+extern void USB0_IRQHandler(void);
+extern void PORTA_IRQHandler(void);
+extern void PORTB_IRQHandler(void);
+extern void PORTC_IRQHandler(void);
+extern void PORTD_IRQHandler(void);
+extern void ADC0_IRQHandler(void);
+extern void LPCMP0_IRQHandler(void);
+extern void LPDAC0_IRQHandler(void);
+extern void CAU3_Task_Complete_IRQHandler(void);
+extern void CAU3_Security_Violation_IRQHandler(void);
+extern void TRNG_IRQHandler(void);
+extern void LPIT1_IRQHandler(void);
+extern void LPTMR2_IRQHandler(void);
+extern void TPM3_IRQHandler(void);
+extern void LPI2C3_DriverIRQHandler(void);
+extern void LPSPI3_DriverIRQHandler(void);
+extern void LPUART3_DriverIRQHandler(void);
+extern void PORTE_IRQHandler(void);
+extern void LPCMP1_IRQHandler(void);
+extern void RF0_0_IRQHandler(void);
+extern void RF0_1_IRQHandler(void);
+extern void INTMUX0_0_DriverIRQHandler(void);
+extern void INTMUX0_1_DriverIRQHandler(void);
+extern void INTMUX0_2_DriverIRQHandler(void);
+extern void INTMUX0_3_DriverIRQHandler(void);
+extern void INTMUX0_4_DriverIRQHandler(void);
+extern void INTMUX0_5_DriverIRQHandler(void);
+extern void INTMUX0_6_DriverIRQHandler(void);
+extern void INTMUX0_7_DriverIRQHandler(void);
+extern void INTMUX0_8_DriverIRQHandler(void);
+extern void DMA0_0_4_8_12_IRQHandler(void);
+extern void DMA0_1_5_9_13_IRQHandler(void);
+extern void DMA0_2_6_10_14_IRQHandler(void);
+extern void DMA0_3_7_11_15_IRQHandler(void);
+extern void FLEXIO0_IRQHandler(void);
+extern void LPI2C0_IRQHandler(void);
+extern void LPI2C1_IRQHandler(void);
+extern void LPI2C2_IRQHandler(void);
+extern void I2S0_IRQHandler(void);
+extern void USDHC0_IRQHandler(void);
+extern void LPSPI0_IRQHandler(void);
+extern void LPSPI1_IRQHandler(void);
+extern void LPSPI2_IRQHandler(void);
+extern void LPUART0_IRQHandler(void);
+extern void LPUART1_IRQHandler(void);
+extern void LPUART2_IRQHandler(void);
+extern void LPI2C3_IRQHandler(void);
+extern void LPSPI3_IRQHandler(void);
+extern void LPUART3_IRQHandler(void);
+extern void INTMUX0_0_IRQHandler(void);
+extern void INTMUX0_1_IRQHandler(void);
+extern void INTMUX0_2_IRQHandler(void);
+extern void INTMUX0_3_IRQHandler(void);
+extern void INTMUX0_4_IRQHandler(void);
+extern void INTMUX0_5_IRQHandler(void);
+extern void INTMUX0_6_IRQHandler(void);
+extern void INTMUX0_7_IRQHandler(void);
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+
+static void copy_section(uint32_t * p_load, uint32_t * p_vma, uint32_t * p_vma_end)
+{
+    while(p_vma <= p_vma_end)
+    {
+        *p_vma = *p_load;
+        ++p_load;
+        ++p_vma;
+    }
+}
+
+static void zero_section(uint32_t * start, uint32_t * end)
+{
+    uint32_t * p_zero = start;
+
+    while(p_zero <= end)
+    {
+        *p_zero = 0;
+        ++p_zero;
+    }
+}
+
+#define DEFINE_IRQ_HANDLER(irq_handler, driver_irq_handler) \
+    void __attribute__((weak)) irq_handler(void) { driver_irq_handler();}
+
+#define DEFINE_DEFAULT_IRQ_HANDLER(irq_handler) void irq_handler() __attribute__((weak, alias("DefaultIRQHandler")))
+
+DEFINE_DEFAULT_IRQ_HANDLER(DMA0_0_4_8_12_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(DMA0_1_5_9_13_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(DMA0_2_6_10_14_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(DMA0_3_7_11_15_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(DMA0_Error_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(CMC0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(EWM_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Command_Complete_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Read_Collision_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LLWU0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(MUA_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(SPM_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(WDOG0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(SCG_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPIT0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(RTC_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPTMR0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPTMR1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(TPM0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(TPM1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(TPM2_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(EMVSIM0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(FLEXIO0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPI2C0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPI2C1_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPI2C2_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(I2S0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(USDHC0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPSPI0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPSPI1_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPSPI2_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPUART0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPUART1_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPUART2_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(USB0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(PORTA_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(PORTB_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(PORTC_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(PORTD_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(ADC0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPCMP0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPDAC0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Task_Complete_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Security_Violation_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(TRNG_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPIT1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPTMR2_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(TPM3_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPI2C3_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPSPI3_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPUART3_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(PORTE_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPCMP1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(RF0_0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(RF0_1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_1_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_2_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_3_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_4_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_5_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_6_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_7_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_8_DriverIRQHandler);
+
+DEFINE_IRQ_HANDLER(DMA0_0_4_8_12_IRQHandler, DMA0_0_4_8_12_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(DMA0_1_5_9_13_IRQHandler, DMA0_1_5_9_13_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(DMA0_2_6_10_14_IRQHandler, DMA0_2_6_10_14_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(DMA0_3_7_11_15_IRQHandler, DMA0_3_7_11_15_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(FLEXIO0_IRQHandler, FLEXIO0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPI2C0_IRQHandler, LPI2C0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPI2C1_IRQHandler, LPI2C1_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPI2C2_IRQHandler, LPI2C2_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(I2S0_IRQHandler, I2S0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(USDHC0_IRQHandler, USDHC0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPSPI0_IRQHandler, LPSPI0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPSPI1_IRQHandler, LPSPI1_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPSPI2_IRQHandler, LPSPI2_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPUART0_IRQHandler, LPUART0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPUART1_IRQHandler, LPUART1_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPUART2_IRQHandler, LPUART2_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPI2C3_IRQHandler, LPI2C3_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPSPI3_IRQHandler, LPSPI3_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPUART3_IRQHandler, LPUART3_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX0_0_IRQHandler, INTMUX0_0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX0_1_IRQHandler, INTMUX0_1_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX0_2_IRQHandler, INTMUX0_2_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX0_3_IRQHandler, INTMUX0_3_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX0_4_IRQHandler, INTMUX0_4_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX0_5_IRQHandler, INTMUX0_5_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX0_6_IRQHandler, INTMUX0_6_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX0_7_IRQHandler, INTMUX0_7_DriverIRQHandler);
+
+__attribute__((section("user_vectors"))) const irq_handler_t isrTable[] =
+{
+    DMA0_0_4_8_12_IRQHandler,
+    DMA0_1_5_9_13_IRQHandler,
+    DMA0_2_6_10_14_IRQHandler,
+    DMA0_3_7_11_15_IRQHandler,
+    DMA0_Error_IRQHandler,
+    CMC0_IRQHandler,
+    MUA_IRQHandler,
+    USB0_IRQHandler,
+    USDHC0_IRQHandler,
+    I2S0_IRQHandler,
+    FLEXIO0_IRQHandler,
+    EMVSIM0_IRQHandler,
+    LPIT0_IRQHandler,
+    LPSPI0_IRQHandler,
+    LPSPI1_IRQHandler,
+    LPI2C0_IRQHandler,
+    LPI2C1_IRQHandler,
+    LPUART0_IRQHandler,
+    PORTA_IRQHandler,
+    TPM0_IRQHandler,
+    LPDAC0_IRQHandler,
+    ADC0_IRQHandler,
+    LPCMP0_IRQHandler,
+    RTC_IRQHandler,
+    INTMUX0_0_IRQHandler,
+    INTMUX0_1_IRQHandler,
+    INTMUX0_2_IRQHandler,
+    INTMUX0_3_IRQHandler,
+    INTMUX0_4_IRQHandler,
+    INTMUX0_5_IRQHandler,
+    INTMUX0_6_IRQHandler,
+    INTMUX0_7_IRQHandler,
+    EWM_IRQHandler,
+    FTFE_Command_Complete_IRQHandler,
+    FTFE_Read_Collision_IRQHandler,
+    LLWU0_IRQHandler,
+    SPM_IRQHandler,
+    WDOG0_IRQHandler,
+    SCG_IRQHandler,
+    LPTMR0_IRQHandler,
+    LPTMR1_IRQHandler,
+    TPM1_IRQHandler,
+    TPM2_IRQHandler,
+    LPI2C2_IRQHandler,
+    LPSPI2_IRQHandler,
+    LPUART1_IRQHandler,
+    LPUART2_IRQHandler,
+    PORTB_IRQHandler,
+    PORTC_IRQHandler,
+    PORTD_IRQHandler,
+    CAU3_Task_Complete_IRQHandler,
+    CAU3_Security_Violation_IRQHandler,
+    TRNG_IRQHandler,
+    LPIT1_IRQHandler,
+    LPTMR2_IRQHandler,
+    TPM3_IRQHandler,
+    LPI2C3_IRQHandler,
+    LPSPI3_IRQHandler,
+    LPUART3_IRQHandler,
+    PORTE_IRQHandler,
+    LPCMP1_IRQHandler,
+    RF0_0_IRQHandler,
+    RF0_1_IRQHandler,
+};
+
+extern uint32_t __VECTOR_TABLE[];
+
+static uint32_t irqNesting = 0;
+
+static void DefaultIRQHandler(void)
+{
+    for (;;)
+    {
+    }
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if (DISABLE_WDOG)
+  WDOG0->CNT = 0xD928C520U;
+  WDOG0->TOVAL = 0xFFFF;
+  WDOG0->CS = (uint32_t) ((WDOG0->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
+#endif /* (DISABLE_WDOG) */
+
+  SystemInitHook();
+
+  copy_section(&__etext, &__data_start__, &__data_end__);
+  zero_section(&__bss_start__, &__bss_end__);
+
+  /* Setup the vector table address. */
+  irqNesting = 0;
+
+  __ASM volatile("csrw 0x305, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* MTVEC */
+  __ASM volatile("csrw 0x005, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* UTVEC */
+
+  /* Clear all pending flags. */
+  EVENT_UNIT->INTPTPENDCLEAR = 0xFFFFFFFF;
+  EVENT_UNIT->EVTPENDCLEAR = 0xFFFFFFFF;
+  /* Set all interrupt as secure interrupt. */
+  EVENT_UNIT->INTPTSECURE = 0xFFFFFFFF;
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+
+  uint32_t SCGOUTClock;                                 /* Variable to store output clock frequency of the SCG module */
+  uint16_t Divider;
+  Divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1;
+
+  switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) {
+    case 0x1:
+      /* System OSC */
+      SCGOUTClock = CPU_XTAL_CLK_HZ;
+      break;
+    case 0x2:
+      /* Slow IRC */
+      SCGOUTClock = (((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) ? 8000000 : 2000000);
+      break;
+    case 0x3:
+      /* Fast IRC */
+      SCGOUTClock = 48000000 + ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000;
+      break;
+    case 0x5:
+      /* Low Power FLL */
+      SCGOUTClock = 48000000 + ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT) * 24000000;
+      break;
+    default:
+      return;
+  }
+  SystemCoreClock = (SCGOUTClock / Divider);
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemInitHook()
+   ---------------------------------------------------------------------------- */
+
+__attribute__ ((weak)) void SystemInitHook (void) {
+  /* Void implementation of the weak function. */
+}
+
+#if defined(__IAR_SYSTEMS_ICC__)
+#pragma weak SystemIrqHandler
+void SystemIrqHandler(uint32_t mcause) {
+#elif defined(__GNUC__)
+__attribute__((weak)) void SystemIrqHandler(uint32_t mcause) {
+#else
+  #error Not supported compiler type
+#endif
+    uint32_t intNum;
+
+    if (mcause & 0x80000000) /* For external interrupt. */
+    {
+        intNum = mcause & 0x1FUL;
+
+        irqNesting++;
+
+        /* Clear pending flag in EVENT unit .*/
+        EVENT_UNIT->INTPTPENDCLEAR = (1U << intNum);
+
+        /* Read back to make sure write finished. */
+        (void)(EVENT_UNIT->INTPTPENDCLEAR);
+
+        __enable_irq();      /* Support nesting interrupt */
+
+        /* Now call the real irq handler for intNum */
+        isrTable[intNum]();
+
+        __disable_irq();
+
+        irqNesting--;
+    }
+}
+
+/* Use LIPT0 channel 0 for systick. */
+#define SYSTICK_LPIT LPIT0
+#define SYSTICK_LPIT_CH 0
+#define SYSTICK_LPIT_IRQn LPIT0_IRQn
+
+/* Leverage LPIT0 to provide Systick */
+void SystemSetupSystick(uint32_t tickRateHz, uint32_t intPriority)
+{
+    /* Init pit module */
+    CLOCK_EnableClock(kCLOCK_Lpit0);
+
+    /* Reset the timer channels and registers except the MCR register */
+    SYSTICK_LPIT->MCR |= LPIT_MCR_SW_RST_MASK;
+    SYSTICK_LPIT->MCR &= ~LPIT_MCR_SW_RST_MASK;
+
+    /* Setup timer operation in debug and doze modes and enable the module */
+    SYSTICK_LPIT->MCR = LPIT_MCR_DBG_EN_MASK | LPIT_MCR_DOZE_EN_MASK | LPIT_MCR_M_CEN_MASK;
+
+    /* Set timer period for channel 0 */
+    SYSTICK_LPIT->CHANNEL[SYSTICK_LPIT_CH].TVAL = (CLOCK_GetIpFreq(kCLOCK_Lpit0) / tickRateHz) - 1;
+
+    /* Enable timer interrupts for channel 0 */
+    SYSTICK_LPIT->MIER |= (1U << SYSTICK_LPIT_CH);
+
+    /* Set interrupt priority. */
+    EVENT_SetIRQPriority(SYSTICK_LPIT_IRQn, intPriority);
+
+    /* Enable interrupt at the EVENT unit */
+    EnableIRQ(SYSTICK_LPIT_IRQn);
+
+    /* Start channel 0 */
+    SYSTICK_LPIT->SETTEN |= (LPIT_SETTEN_SET_T_EN_0_MASK << SYSTICK_LPIT_CH);
+}
+
+uint32_t SystemGetIRQNestingLevel(void)
+{
+    return irqNesting;
+}
+
+void SystemClearSystickFlag(void)
+{
+    /* Channel 0. */
+    SYSTICK_LPIT->MSR = (1U << SYSTICK_LPIT_CH);
+}
+
+void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority)
+{
+    uint8_t regIdx;
+    uint8_t regOffset;
+
+    if ((IRQn < 32) && (intPriority < 8))
+    {
+        /*
+         * 4 priority control registers, each register controls 8 interrupts.
+         * Bit 0-2: interrupt 0
+         * Bit 4-7: interrupt 1
+         * ...
+         * Bit 28-30: interrupt 7
+         */
+        regIdx = IRQn >> 3U;
+        regOffset = (IRQn & 0x07U) * 4U;
+
+        EVENT_UNIT->INTPTPRI[regIdx] = (EVENT_UNIT->INTPTPRI[regIdx] & ~(0x0F << regOffset)) | (intPriority << regOffset);
+    }
+}
+
+uint8_t EVENT_GetIRQPriority(IRQn_Type IRQn)
+{
+    uint8_t regIdx;
+    uint8_t regOffset;
+    int32_t intPriority;
+
+    if ((IRQn < 32))
+    {
+        /*
+         * 4 priority control registers, each register controls 8 interrupts.
+         * Bit 0-2: interrupt 0
+         * Bit 4-7: interrupt 1
+         * ...
+         * Bit 28-30: interrupt 7
+         */
+        regIdx = IRQn >> 3U;
+        regOffset = (IRQn & 0x07U) << 2U;
+
+        intPriority = (EVENT_UNIT->INTPTPRI[regIdx] >> regOffset) & 0xF;
+        return (uint8_t)intPriority;
+    }
+    return 0;
+}
+
+bool SystemInISR(void)
+{
+    return ((EVENT_UNIT->INTPTENACTIVE) != 0);;
+}
+
+void EVENT_SystemReset(void)
+{
+    EVENT_UNIT->SLPCTRL |= EVENT_SLPCTRL_SYSRSTREQST_MASK;
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_ri5cy.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_ri5cy.h
new file mode 100644
index 0000000..c46b2e7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_ri5cy.h
@@ -0,0 +1,182 @@
+/*
+** ###################################################################
+**     Processors:          RV32M1_ri5cy
+**                          RV32M1_ri5cy
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
+**     Version:             rev. 1.0, 2018-10-02
+**     Build:               b180926
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2018-10-02)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file RV32M1_ri5cy
+ * @version 1.0
+ * @date 2018-10-02
+ * @brief Device specific configuration file for RV32M1_ri5cy (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_RV32M1_ri5cy_H_
+#define _SYSTEM_RV32M1_ri5cy_H_             /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+#include 
+
+
+#ifndef DISABLE_WDOG
+  #define DISABLE_WDOG  1
+#endif
+
+/* Define clock source values */
+#define CPU_XTAL_CLK_HZ                 8000000u            /* Value of the external crystal or oscillator clock frequency in Hz */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AHSRUN=1, AVLP=1,ALLS=1,AVLLS=0x3 */
+#define SYSTEM_SMC_PMPROT_VALUE        0xABu               /* SMC_PMPROT */
+#define SYSTEM_SMC_PMCTRL_VALUE        0x0u                /* SMC_PMCTRL */
+
+#define DEFAULT_SYSTEM_CLOCK           48000000u           /* Default System clock value */
+
+
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+/**
+ * @brief SystemInit function hook.
+ *
+ * This weak function allows to call specific initialization code during the
+ * SystemInit() execution.This can be used when an application specific code needs
+ * to be called as close to the reset entry as possible (for example the Multicore
+ * Manager MCMGR_EarlyInit() function call).
+ * NOTE: No global r/w variables can be used in this hook function because the
+ * initialization of these variables happens after this function.
+ */
+void SystemInitHook (void);
+
+/**
+ * @brief System IRQ handler which dispatches specific IRQ to corresponding registered handler.
+ *
+ * It is called from IRQ exception context and dispatches to registered handler according to
+ * MCAUSE interrupt number.
+ *
+ * @param mcause IRQ acknowledge value read from MCAUSE
+ */
+void SystemIrqHandler(uint32_t mcause);
+
+/**
+ * @brief Get IRQ nesting level of current context.
+ *
+ * If the return value is 0, then the context is not ISR, otherwise the context is ISR.
+ *
+ * @return IRQ nesting level
+ */
+uint32_t SystemGetIRQNestingLevel (void);
+
+/**
+ * @brief Setup systick for RTOS system.
+ *
+ * @param tickRateHz Tick number per second
+ * @param intPriority IRQ interrupt priority (the smaller, the higher priority)
+ */
+void SystemSetupSystick (uint32_t tickRateHz, uint32_t intPriority);
+
+/**
+ * @brief Clear systick flag status so that next tick interrupt may occur.
+ */
+void SystemClearSystickFlag (void);
+
+/**
+ * @brief Sysem is in ISR or not.
+ */
+bool SystemInISR(void);
+
+#define SysTick_Handler LPIT0_IRQHandler
+
+/**
+ * @brief Set interrupt priority in Event unit.
+ */
+void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority);
+
+/**
+ * @brief Get interrupt priority in Event unit.
+ */
+uint8_t EVENT_GetIRQPriority(IRQn_Type IRQn);
+
+/**
+ * @brief Reset the system.
+ */
+void EVENT_SystemReset(void);
+
+#define NVIC_SystemReset EVENT_SystemReset
+
+/* Priority setting macro remap. */
+#define NVIC_SetPriority EVENT_SetIRQPriority
+
+/* Priority getting macro remap. */
+#define NVIC_GetPriority EVENT_GetIRQPriority
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SYSTEM_RV32M1_ri5cy_H_ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_zero_riscy.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_zero_riscy.c
new file mode 100644
index 0000000..0370097
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_zero_riscy.c
@@ -0,0 +1,535 @@
+/*
+** ###################################################################
+**     Processors:          RV32M1_zero_riscy
+**                          RV32M1_zero_riscy
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
+**     Version:             rev. 1.0, 2018-10-02
+**     Build:               b180926
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2018-10-02)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file RV32M1_zero_riscy
+ * @version 1.0
+ * @date 2018-10-02
+ * @brief Device specific configuration file for RV32M1_zero_riscy
+ *        (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include 
+#include "fsl_device_registers.h"
+#include "fsl_common.h"
+
+typedef void (*irq_handler_t)(void);
+
+extern void CTI1_IRQHandler(void);
+extern void DMA1_04_DriverIRQHandler(void);
+extern void DMA1_15_DriverIRQHandler(void);
+extern void DMA1_26_DriverIRQHandler(void);
+extern void DMA1_37_DriverIRQHandler(void);
+extern void DMA1_Error_DriverIRQHandler(void);
+extern void CMC1_IRQHandler(void);
+extern void LLWU1_IRQHandler(void);
+extern void MUB_IRQHandler(void);
+extern void WDOG1_IRQHandler(void);
+extern void CAU3_Task_Complete_IRQHandler(void);
+extern void CAU3_Security_Violation_IRQHandler(void);
+extern void TRNG_IRQHandler(void);
+extern void LPIT1_IRQHandler(void);
+extern void LPTMR2_IRQHandler(void);
+extern void TPM3_IRQHandler(void);
+extern void LPI2C3_DriverIRQHandler(void);
+extern void RF0_0_IRQHandler(void);
+extern void RF0_1_IRQHandler(void);
+extern void LPSPI3_DriverIRQHandler(void);
+extern void LPUART3_DriverIRQHandler(void);
+extern void PORTE_IRQHandler(void);
+extern void LPCMP1_IRQHandler(void);
+extern void RTC_IRQHandler(void);
+extern void INTMUX1_0_DriverIRQHandler(void);
+extern void INTMUX1_1_DriverIRQHandler(void);
+extern void INTMUX1_2_DriverIRQHandler(void);
+extern void INTMUX1_3_DriverIRQHandler(void);
+extern void INTMUX1_4_DriverIRQHandler(void);
+extern void INTMUX1_5_DriverIRQHandler(void);
+extern void INTMUX1_6_DriverIRQHandler(void);
+extern void INTMUX1_7_DriverIRQHandler(void);
+extern void EWM_IRQHandler(void);
+extern void FTFE_Command_Complete_IRQHandler(void);
+extern void FTFE_Read_Collision_IRQHandler(void);
+extern void SPM_IRQHandler(void);
+extern void SCG_IRQHandler(void);
+extern void LPIT0_IRQHandler(void);
+extern void LPTMR0_IRQHandler(void);
+extern void LPTMR1_IRQHandler(void);
+extern void TPM0_IRQHandler(void);
+extern void TPM1_IRQHandler(void);
+extern void TPM2_IRQHandler(void);
+extern void EMVSIM0_IRQHandler(void);
+extern void FLEXIO0_DriverIRQHandler(void);
+extern void LPI2C0_DriverIRQHandler(void);
+extern void LPI2C1_DriverIRQHandler(void);
+extern void LPI2C2_DriverIRQHandler(void);
+extern void I2S0_DriverIRQHandler(void);
+extern void USDHC0_DriverIRQHandler(void);
+extern void LPSPI0_DriverIRQHandler(void);
+extern void LPSPI1_DriverIRQHandler(void);
+extern void LPSPI2_DriverIRQHandler(void);
+extern void LPUART0_DriverIRQHandler(void);
+extern void LPUART1_DriverIRQHandler(void);
+extern void LPUART2_DriverIRQHandler(void);
+extern void USB0_IRQHandler(void);
+extern void PORTA_IRQHandler(void);
+extern void PORTB_IRQHandler(void);
+extern void PORTC_IRQHandler(void);
+extern void PORTD_IRQHandler(void);
+extern void ADC0_IRQHandler(void);
+extern void LPCMP0_IRQHandler(void);
+extern void LPDAC0_IRQHandler(void);
+extern void DMA1_15_IRQHandler(void);
+extern void DMA1_26_IRQHandler(void);
+extern void DMA1_37_IRQHandler(void);
+extern void DMA1_Error_IRQHandler(void);
+extern void LPI2C3_IRQHandler(void);
+extern void LPSPI3_IRQHandler(void);
+extern void LPUART3_IRQHandler(void);
+extern void INTMUX1_0_IRQHandler(void);
+extern void INTMUX1_1_IRQHandler(void);
+extern void INTMUX1_2_IRQHandler(void);
+extern void INTMUX1_3_IRQHandler(void);
+extern void INTMUX1_4_IRQHandler(void);
+extern void INTMUX1_5_IRQHandler(void);
+extern void INTMUX1_6_IRQHandler(void);
+extern void INTMUX1_7_IRQHandler(void);
+extern void FLEXIO0_IRQHandler(void);
+extern void LPI2C0_IRQHandler(void);
+extern void LPI2C1_IRQHandler(void);
+extern void LPI2C2_IRQHandler(void);
+extern void I2S0_IRQHandler(void);
+extern void USDHC0_IRQHandler(void);
+extern void LPSPI0_IRQHandler(void);
+extern void LPSPI1_IRQHandler(void);
+extern void LPSPI2_IRQHandler(void);
+extern void LPUART0_IRQHandler(void);
+extern void LPUART1_IRQHandler(void);
+extern void LPUART2_IRQHandler(void);
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+
+static void copy_section(uint32_t * p_load, uint32_t * p_vma, uint32_t * p_vma_end)
+{
+    while(p_vma <= p_vma_end)
+    {
+        *p_vma = *p_load;
+        ++p_load;
+        ++p_vma;
+    }
+}
+
+static void zero_section(uint32_t * start, uint32_t * end)
+{
+    uint32_t * p_zero = start;
+
+    while(p_zero <= end)
+    {
+        *p_zero = 0;
+        ++p_zero;
+    }
+}
+
+#define DEFINE_IRQ_HANDLER(irq_handler, driver_irq_handler) \
+    void __attribute__((weak)) irq_handler(void) { driver_irq_handler();}
+
+#define DEFINE_DEFAULT_IRQ_HANDLER(irq_handler) void irq_handler() __attribute__((weak, alias("DefaultIRQHandler")))
+
+DEFINE_DEFAULT_IRQ_HANDLER(CTI1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(DMA1_04_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(DMA1_15_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(DMA1_26_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(DMA1_37_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(DMA1_Error_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(CMC1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LLWU1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(MUB_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(WDOG1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Task_Complete_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Security_Violation_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(TRNG_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPIT1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPTMR2_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(TPM3_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPI2C3_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(RF0_0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(RF0_1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPSPI3_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPUART3_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(PORTE_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPCMP1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(RTC_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_1_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_2_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_3_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_4_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_5_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_6_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_7_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(EWM_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Command_Complete_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Read_Collision_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(SPM_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(SCG_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPIT0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPTMR0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPTMR1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(TPM0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(TPM1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(TPM2_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(EMVSIM0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(FLEXIO0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPI2C0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPI2C1_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPI2C2_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(I2S0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(USDHC0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPSPI0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPSPI1_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPSPI2_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPUART0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPUART1_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPUART2_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(USB0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(PORTA_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(PORTB_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(PORTC_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(PORTD_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(ADC0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPCMP0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPDAC0_IRQHandler);
+
+DEFINE_IRQ_HANDLER(DMA1_04_IRQHandler, DMA1_04_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(DMA1_15_IRQHandler, DMA1_15_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(DMA1_26_IRQHandler, DMA1_26_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(DMA1_37_IRQHandler, DMA1_37_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(DMA1_Error_IRQHandler, DMA1_Error_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPI2C3_IRQHandler, LPI2C3_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPSPI3_IRQHandler, LPSPI3_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPUART3_IRQHandler, LPUART3_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX1_0_IRQHandler, INTMUX1_0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX1_1_IRQHandler, INTMUX1_1_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX1_2_IRQHandler, INTMUX1_2_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX1_3_IRQHandler, INTMUX1_3_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX1_4_IRQHandler, INTMUX1_4_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX1_5_IRQHandler, INTMUX1_5_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX1_6_IRQHandler, INTMUX1_6_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX1_7_IRQHandler, INTMUX1_7_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(FLEXIO0_IRQHandler, FLEXIO0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPI2C0_IRQHandler, LPI2C0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPI2C1_IRQHandler, LPI2C1_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPI2C2_IRQHandler, LPI2C2_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(I2S0_IRQHandler, I2S0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(USDHC0_IRQHandler, USDHC0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPSPI0_IRQHandler, LPSPI0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPSPI1_IRQHandler, LPSPI1_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPSPI2_IRQHandler, LPSPI2_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPUART0_IRQHandler, LPUART0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPUART1_IRQHandler, LPUART1_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPUART2_IRQHandler, LPUART2_DriverIRQHandler);
+
+__attribute__((section("user_vectors"))) const irq_handler_t isrTable[] =
+{
+	CTI1_IRQHandler,
+	DMA1_04_IRQHandler,
+	DMA1_15_IRQHandler,
+	DMA1_26_IRQHandler,
+	DMA1_37_IRQHandler,
+	DMA1_Error_IRQHandler,
+	CMC1_IRQHandler,
+	LLWU1_IRQHandler,
+	MUB_IRQHandler,
+	WDOG1_IRQHandler,
+	CAU3_Task_Complete_IRQHandler,
+	CAU3_Security_Violation_IRQHandler,
+	TRNG_IRQHandler,
+	LPIT1_IRQHandler,
+	LPTMR2_IRQHandler,
+	TPM3_IRQHandler,
+	LPI2C3_IRQHandler,
+	RF0_0_IRQHandler,
+	RF0_1_IRQHandler,
+	LPSPI3_IRQHandler,
+	LPUART3_IRQHandler,
+	PORTE_IRQHandler,
+	LPCMP1_IRQHandler,
+	RTC_IRQHandler,
+	INTMUX1_0_IRQHandler,
+	INTMUX1_1_IRQHandler,
+	INTMUX1_2_IRQHandler,
+	INTMUX1_3_IRQHandler,
+	INTMUX1_4_IRQHandler,
+	INTMUX1_5_IRQHandler,
+	INTMUX1_6_IRQHandler,
+	INTMUX1_7_IRQHandler,
+	EWM_IRQHandler,
+	FTFE_Command_Complete_IRQHandler,
+	FTFE_Read_Collision_IRQHandler,
+	SPM_IRQHandler,
+	SCG_IRQHandler,
+	LPIT0_IRQHandler,
+	LPTMR0_IRQHandler,
+	LPTMR1_IRQHandler,
+	TPM0_IRQHandler,
+	TPM1_IRQHandler,
+	TPM2_IRQHandler,
+	EMVSIM0_IRQHandler,
+	FLEXIO0_IRQHandler,
+	LPI2C0_IRQHandler,
+	LPI2C1_IRQHandler,
+	LPI2C2_IRQHandler,
+	I2S0_IRQHandler,
+	USDHC0_IRQHandler,
+	LPSPI0_IRQHandler,
+	LPSPI1_IRQHandler,
+	LPSPI2_IRQHandler,
+	LPUART0_IRQHandler,
+	LPUART1_IRQHandler,
+	LPUART2_IRQHandler,
+	USB0_IRQHandler,
+	PORTA_IRQHandler,
+	PORTB_IRQHandler,
+	PORTC_IRQHandler,
+	PORTD_IRQHandler,
+	ADC0_IRQHandler,
+	LPCMP0_IRQHandler,
+	LPDAC0_IRQHandler,
+};
+
+extern uint32_t __VECTOR_TABLE[];
+
+static uint32_t irqNesting = 0;
+
+static void DefaultIRQHandler(void)
+{
+    for (;;)
+    {
+    }
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if (DISABLE_WDOG)
+  WDOG1->CNT = 0xD928C520U;
+  WDOG1->TOVAL = 0xFFFF;
+  WDOG1->CS = (uint32_t) ((WDOG1->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
+#endif /* (DISABLE_WDOG) */
+
+  SystemInitHook();
+
+  copy_section(&__etext, &__data_start__, &__data_end__);
+  zero_section(&__bss_start__, &__bss_end__);
+
+  /* Setup the vector table address. */
+  irqNesting = 0;
+
+  __ASM volatile("csrw 0x305, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* MTVEC */
+  __ASM volatile("csrw 0x005, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* UTVEC */
+
+  /* Clear all pending flags. */
+  EVENT_UNIT->INTPTPENDCLEAR = 0xFFFFFFFF;
+  EVENT_UNIT->EVTPENDCLEAR = 0xFFFFFFFF;
+  /* Set all interrupt as secure interrupt. */
+  EVENT_UNIT->INTPTSECURE = 0xFFFFFFFF;
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+
+  uint32_t SCGOUTClock;                                 /* Variable to store output clock frequency of the SCG module */
+  uint16_t Divider;
+  Divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1;
+
+  switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) {
+    case 0x1:
+      /* System OSC */
+      SCGOUTClock = CPU_XTAL_CLK_HZ;
+      break;
+    case 0x2:
+      /* Slow IRC */
+      SCGOUTClock = (((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) ? 8000000 : 2000000);
+      break;
+    case 0x3:
+      /* Fast IRC */
+      SCGOUTClock = 48000000 + ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000;
+      break;
+    case 0x5:
+      /* Low Power FLL */
+      SCGOUTClock = 48000000 + ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT) * 24000000;
+      break;
+    default:
+      return;
+  }
+  SystemCoreClock = (SCGOUTClock / Divider);
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemInitHook()
+   ---------------------------------------------------------------------------- */
+
+__attribute__ ((weak)) void SystemInitHook (void) {
+  /* Void implementation of the weak function. */
+}
+
+#if defined(__IAR_SYSTEMS_ICC__)
+#pragma weak SystemIrqHandler
+void SystemIrqHandler(uint32_t mcause) {
+#elif defined(__GNUC__)
+__attribute__((weak)) void SystemIrqHandler(uint32_t mcause) {
+#else
+  #error Not supported compiler type
+#endif
+    uint32_t intNum;
+
+    if (mcause & 0x80000000) /* For external interrupt. */
+    {
+        intNum = mcause & 0x1FUL;
+
+        irqNesting++;
+
+        /* Clear pending flag in EVENT unit .*/
+        EVENT_UNIT->INTPTPENDCLEAR = (1U << intNum);
+
+        /* Read back to make sure write finished. */
+        (void)(EVENT_UNIT->INTPTPENDCLEAR);
+
+        __enable_irq();      /* Support nesting interrupt */
+
+        /* Now call the real irq handler for intNum */
+        isrTable[intNum]();
+
+        __disable_irq();
+
+        irqNesting--;
+    }
+}
+
+/* Use LIPT1 channel 0 for systick. */
+#define SYSTICK_LPIT LPIT1
+#define SYSTICK_LPIT_CH 0
+#define SYSTICK_LPIT_IRQn LPIT1_IRQn
+
+/* Leverage LPIT0 to provide Systick */
+void SystemSetupSystick(uint32_t tickRateHz, uint32_t intPriority)
+{
+    /* Init pit module */
+    CLOCK_EnableClock(kCLOCK_Lpit1);
+
+    /* Reset the timer channels and registers except the MCR register */
+    SYSTICK_LPIT->MCR |= LPIT_MCR_SW_RST_MASK;
+    SYSTICK_LPIT->MCR &= ~LPIT_MCR_SW_RST_MASK;
+
+    /* Setup timer operation in debug and doze modes and enable the module */
+    SYSTICK_LPIT->MCR = LPIT_MCR_DBG_EN_MASK | LPIT_MCR_DOZE_EN_MASK | LPIT_MCR_M_CEN_MASK;
+
+    /* Set timer period for channel 0 */
+    SYSTICK_LPIT->CHANNEL[SYSTICK_LPIT_CH].TVAL = (CLOCK_GetIpFreq(kCLOCK_Lpit1) / tickRateHz) - 1;
+
+    /* Enable timer interrupts for channel 0 */
+    SYSTICK_LPIT->MIER |= (1U << SYSTICK_LPIT_CH);
+
+    /* Set interrupt priority. */
+    EVENT_SetIRQPriority(SYSTICK_LPIT_IRQn, intPriority);
+
+    /* Enable interrupt at the EVENT unit */
+    EnableIRQ(SYSTICK_LPIT_IRQn);
+
+    /* Start channel 0 */
+    SYSTICK_LPIT->SETTEN |= (LPIT_SETTEN_SET_T_EN_0_MASK << SYSTICK_LPIT_CH);
+}
+
+uint32_t SystemGetIRQNestingLevel(void)
+{
+    return irqNesting;
+}
+
+void SystemClearSystickFlag(void)
+{
+    /* Channel 0. */
+    SYSTICK_LPIT->MSR = (1U << SYSTICK_LPIT_CH);
+}
+
+void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority)
+{
+    uint8_t regIdx;
+    uint8_t regOffset;
+
+    if ((IRQn < 32) && (intPriority < 8))
+    {
+        /*
+         * 4 priority control registers, each register controls 8 interrupts.
+         * Bit 0-2: interrupt 0
+         * Bit 4-7: interrupt 1
+         * ...
+         * Bit 28-30: interrupt 7
+         */
+        regIdx = IRQn >> 3U;
+        regOffset = (IRQn & 0x07U) * 4U;
+
+        EVENT_UNIT->INTPTPRI[regIdx] = (EVENT_UNIT->INTPTPRI[regIdx] & ~(0x0F << regOffset)) | (intPriority << regOffset);
+    }
+}
+
+bool SystemInISR(void)
+{
+    return ((EVENT_UNIT->INTPTENACTIVE) != 0);;
+}
+
+void EVENT_SystemReset(void)
+{
+    EVENT_UNIT->SLPCTRL |= EVENT_SLPCTRL_SYSRSTREQST_MASK;
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_zero_riscy.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_zero_riscy.h
new file mode 100644
index 0000000..733ac53
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_zero_riscy.h
@@ -0,0 +1,174 @@
+/*
+** ###################################################################
+**     Processors:          RV32M1_zero_riscy
+**                          RV32M1_zero_riscy
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
+**     Version:             rev. 1.0, 2018-10-02
+**     Build:               b180926
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2018-10-02)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file RV32M1_zero_riscy
+ * @version 1.0
+ * @date 2018-10-02
+ * @brief Device specific configuration file for RV32M1_zero_riscy (header
+ *        file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_RV32M1_zero_riscy_H_
+#define _SYSTEM_RV32M1_zero_riscy_H_        /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+#include 
+
+
+#ifndef DISABLE_WDOG
+  #define DISABLE_WDOG  1
+#endif
+
+/* Define clock source values */
+#define CPU_XTAL_CLK_HZ                 8000000u            /* Value of the external crystal or oscillator clock frequency in Hz */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AHSRUN=1, AVLP=1,ALLS=1,AVLLS=0x3 */
+#define SYSTEM_SMC_PMPROT_VALUE        0xABu               /* SMC_PMPROT */
+#define SYSTEM_SMC_PMCTRL_VALUE        0x0u                /* SMC_PMCTRL */
+
+#define DEFAULT_SYSTEM_CLOCK           48000000u           /* Default System clock value */
+
+
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+/**
+ * @brief SystemInit function hook.
+ *
+ * This weak function allows to call specific initialization code during the
+ * SystemInit() execution.This can be used when an application specific code needs
+ * to be called as close to the reset entry as possible (for example the Multicore
+ * Manager MCMGR_EarlyInit() function call).
+ * NOTE: No global r/w variables can be used in this hook function because the
+ * initialization of these variables happens after this function.
+ */
+void SystemInitHook (void);
+
+/**
+ * @brief System IRQ handler which dispatches specific IRQ to corresponding registered handler.
+ *
+ * It is called from IRQ exception context and dispatches to registered handler according to
+ * MCAUSE interrupt number.
+ *
+ * @param mcause IRQ acknowledge value read from MCAUSE
+ */
+void SystemIrqHandler(uint32_t mcause);
+
+/**
+ * @brief Get IRQ nesting level of current context.
+ *
+ * If the return value is 0, then the context is not ISR, otherwise the context is ISR.
+ *
+ * @return IRQ nesting level
+ */
+uint32_t SystemGetIRQNestingLevel (void);
+
+/**
+ * @brief Setup systick for RTOS system.
+ *
+ * @param tickRateHz Tick number per second
+ * @param intPriority IRQ interrupt priority (the smaller, the higher priority)
+ */
+void SystemSetupSystick (uint32_t tickRateHz, uint32_t intPriority);
+
+/**
+ * @brief Clear systick flag status so that next tick interrupt may occur.
+ */
+void SystemClearSystickFlag (void);
+
+#define SysTick_Handler LPIT1_IRQHandler
+
+/**
+ * @brief Sysem is in ISR or not.
+ */
+bool SystemInISR(void);
+
+/**
+ * @brief Set interrupt priority in Event unit.
+ */
+void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority);
+
+/* Priority setting macro remap. */
+#define NVIC_SetPriority EVENT_SetIRQPriority
+
+/**
+ * @brief Reset the system.
+ */
+void EVENT_SystemReset(void);
+
+#define NVIC_SystemReset EVENT_SystemReset
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SYSTEM_RV32M1_zero_riscy_H_ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_debug_console.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_debug_console.c
new file mode 100644
index 0000000..f4b3fb0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_debug_console.c
@@ -0,0 +1,386 @@
+/*
+ * This is a modified version of the file printf.c, which was distributed
+ * by Motorola as part of the M5407C3BOOT.zip package used to initialize
+ * the M5407C3 evaluation board.
+ *
+ * Copyright:
+ *      1999-2000 MOTOROLA, INC. All Rights Reserved.
+ *  You are hereby granted a copyright license to use, modify, and
+ *  distribute the SOFTWARE so long as this entire notice is
+ *  retained without alteration in any modified and/or redistributed
+ *  versions, and that such modified versions are clearly identified
+ *  as such. No licenses are granted by implication, estoppel or
+ *  otherwise under any patents or trademarks of Motorola, Inc. This
+ *  software is provided on an "AS IS" basis and without warranty.
+ *
+ *  To the maximum extent permitted by applicable law, MOTOROLA
+ *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
+ *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
+ *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY
+ *  ACCOMPANYING WRITTEN MATERIALS.
+ *
+ *  To the maximum extent permitted by applicable law, IN NO EVENT
+ *  SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING
+ *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
+ *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
+ *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+ *
+ *  Motorola assumes no responsibility for the maintenance and support
+ *  of this software
+
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include 
+#include 
+#if defined(__CC_ARM)
+#include 
+#endif
+
+#include "fsl_debug_console.h"
+#include "fsl_debug_console_conf.h"
+#include "fsl_log.h"
+#include "fsl_str.h"
+
+#if defined(__riscv)
+#include 
+#include 
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief This is a printf call back function which is used to relocate the log to buffer
+ * or print the log immediately when the local buffer is full.
+ *
+ * @param[in] buf   Buffer to store log.
+ * @param[in] indicator Buffer index.
+ * @param[in] val Target character to store.
+ * @param[in] len length of the character
+ *
+ */
+#if SDK_DEBUGCONSOLE
+static void DbgConsole_RelocateLog(char *buf, int32_t *indicator, char val, int len);
+#endif
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/
+
+/* See fsl_debug_console.h for documentation of this function. */
+status_t DbgConsole_Init(uint32_t baseAddr, uint32_t baudRate, uint8_t device, uint32_t clkSrcFreq)
+{
+    assert(device != DEBUG_CONSOLE_DEVICE_TYPE_NONE);
+
+    return LOG_Init(baseAddr, device, baudRate, clkSrcFreq);
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+status_t DbgConsole_Deinit(void)
+{
+    /* LOG deinit */
+    LOG_Deinit();
+
+    return kStatus_Success;
+}
+
+status_t DbgConsole_Flush(void)
+{
+    /* wait log and io idle */
+    return LOG_WaitIdle();
+}
+
+#if SDK_DEBUGCONSOLE
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Printf(const char *fmt_s, ...)
+{
+    va_list ap;
+    int logLength = 0U, result = 0U;
+    char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {0U};
+
+    va_start(ap, fmt_s);
+    /* format print log first */
+    logLength = StrFormatPrintf(fmt_s, ap, printBuf, DbgConsole_RelocateLog);
+    /* print log */
+    result = LOG_Push((uint8_t *)printBuf, logLength);
+
+    va_end(ap);
+
+    return result;
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Putchar(int ch)
+{
+    /* print char */
+    return LOG_Push((uint8_t *)&ch, 1U);
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Scanf(char *fmt_ptr, ...)
+{
+    va_list ap;
+    int result;
+    char scanfBuf[DEBUG_CONSOLE_SCANF_MAX_LOG_LEN + 1U] = {0U};
+
+    /* scanf log */
+    LOG_ReadLine((uint8_t *)scanfBuf, DEBUG_CONSOLE_SCANF_MAX_LOG_LEN);
+    /* get va_list */
+    va_start(ap, fmt_ptr);
+    /* format scanf log */
+    result = StrFormatScanf(scanfBuf, fmt_ptr, ap);
+
+    va_end(ap);
+
+    return result;
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Getchar(void)
+{
+    uint8_t ch;
+
+    /* Get char */
+    LOG_ReadCharacter(&ch);
+
+    return ch;
+}
+
+static void DbgConsole_RelocateLog(char *buf, int32_t *indicator, char val, int len)
+{
+    int i = 0;
+
+    for (i = 0; i < len; i++)
+    {
+        if ((*indicator + 1) >= DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN)
+        {
+            LOG_Push((uint8_t *)buf, *indicator);
+            *indicator = 0U;
+        }
+
+        buf[*indicator] = val;
+        (*indicator)++;
+    }
+}
+
+#endif /* SDK_DEBUGCONSOLE */
+/*************Code to support toolchain's printf, scanf *******************************/
+/* These function __write and __read is used to support IAR toolchain to printf and scanf*/
+#if (defined(__ICCARM__))
+#pragma weak __write
+size_t __write(int handle, const unsigned char *buffer, size_t size)
+{
+    if (buffer == 0)
+    {
+        /*
+         * This means that we should flush internal buffers.  Since we don't we just return.
+         * (Remember, "handle" == -1 means that all handles should be flushed.)
+         */
+        return 0;
+    }
+
+    /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+    if ((handle != 1) && (handle != 2))
+    {
+        return ((size_t)-1);
+    }
+
+    /* Send data. */
+    LOG_Push((uint8_t *)buffer, 1U);
+
+    return size;
+}
+
+#pragma weak __read
+size_t __read(int handle, unsigned char *buffer, size_t size)
+{
+    /* This function only reads from "standard in", for all other file  handles it returns failure. */
+    if (handle != 0)
+    {
+        return ((size_t)-1);
+    }
+
+    /* Receive data.*/
+    LOG_ReadLine(buffer, size);
+
+    return size;
+}
+
+/* support LPC Xpresso with RedLib */
+#elif(defined(__REDLIB__))
+
+#if (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART))
+int __attribute__((weak)) __sys_write(int handle, char *buffer, int size)
+{
+    if (buffer == 0)
+    {
+        /* return -1 if error. */
+        return -1;
+    }
+
+    /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+    if ((handle != 1) && (handle != 2))
+    {
+        return -1;
+    }
+
+    /* Send data. */
+    LOG_Push((uint8_t *)buffer, size);
+
+    return 0;
+}
+
+int __attribute__((weak)) __sys_readc(void)
+{
+    char tmp;
+
+    /* Receive data. */
+    LOG_ReadCharacter((uint8_t *)&tmp);
+
+    return tmp;
+}
+#endif
+
+/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/
+#elif(defined(__GNUC__))
+
+#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO))) || \
+     (defined(__MCUXPRESSO) && (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART))))
+
+int __attribute__((weak)) _write(int handle, char *buffer, int size)
+{
+    if (buffer == 0)
+    {
+        /* return -1 if error. */
+        return -1;
+    }
+
+    /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+    if ((handle != 1) && (handle != 2))
+    {
+        return -1;
+    }
+
+    /* Send data. */
+    LOG_Push((uint8_t *)buffer, size);
+
+    return size;
+}
+
+int __attribute__((weak)) _read(int handle, char *buffer, int size)
+{
+    /* This function only reads from "standard in", for all other file handles it returns failure. */
+    if (handle != 0)
+    {
+        return -1;
+    }
+
+    /* Receive data. */
+    return LOG_ReadLine((uint8_t *)buffer, size);
+}
+#endif
+
+/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/
+#elif defined(__CC_ARM)
+struct __FILE
+{
+    int handle;
+    /*
+     * Whatever you require here. If the only file you are using is standard output using printf() for debugging,
+     * no file handling is required.
+     */
+};
+
+/* FILE is typedef in stdio.h. */
+#pragma weak __stdout
+#pragma weak __stdin
+FILE __stdout;
+FILE __stdin;
+
+#pragma weak fputc
+int fputc(int ch, FILE *f)
+{
+    /* Send data. */
+    return LOG_Push((uint8_t *)(&ch), 1);
+}
+
+#pragma weak fgetc
+int fgetc(FILE *f)
+{
+    char ch;
+
+    /* Receive data. */
+    LOG_ReadCharacter((uint8_t *)&ch);
+
+    return ch;
+}
+#endif /* __ICCARM__ */
+
+#if defined(__riscv)
+int isatty(int fd)
+{
+    return 1;
+}
+
+int fstat(int fd, struct stat *st)
+{
+    st->st_mode = S_IFCHR;
+    return 0;
+}
+
+int lseek(int fd, off_t ptr, int dir)
+{
+    return 0;
+}
+
+int close(int fd)
+{
+    return -1;
+}
+
+int read(int fd, void* ptr, size_t len)
+{
+    /* This function only reads from "standard in", for all other file handles it returns failure. */
+    if (fd != 0)
+    {
+        return -1;
+    }
+
+    /* Receive data. */
+    return LOG_ReadLine((uint8_t *)ptr, len);
+}
+
+int write(int fd, const void* ptr, size_t len)
+{
+    if (ptr == 0)
+    {
+        /* return -1 if error. */
+        return -1;
+    }
+
+    /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+    if ((fd != 1) && (fd != 2))
+    {
+        return -1;
+    }
+
+    /* Send data. */
+    LOG_Push((uint8_t *)ptr, len);
+
+    return len;
+}
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_debug_console.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_debug_console.h
new file mode 100644
index 0000000..0dadeaa
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_debug_console.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Debug console shall provide input and output functions to scan and print formatted data.
+ * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier"
+ *   - [flags] :'-', '+', '#', ' ', '0'
+ *   - [width]:  number (0,1...)
+ *   - [.precision]: number (0,1...)
+ *   - [length]: do not support
+ *   - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n'
+ * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier"
+ *   - [*]: is supported.
+ *   - [width]: number (0,1...)
+ *   - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t')
+ *   - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's'
+ */
+
+#ifndef _FSL_DEBUGCONSOLE_H_
+#define _FSL_DEBUGCONSOLE_H_
+
+#include "fsl_common.h"
+/*
+ * @addtogroup debugconsole
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Definition to select sdk or toolchain printf, scanf. */
+#ifndef SDK_DEBUGCONSOLE
+#define SDK_DEBUGCONSOLE 1U
+#endif
+
+#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE)
+#include 
+#endif
+
+#if SDK_DEBUGCONSOLE /* Select printf, scanf, putchar, getchar of SDK version. */
+#define PRINTF DbgConsole_Printf
+#define SCANF DbgConsole_Scanf
+#define PUTCHAR DbgConsole_Putchar
+#define GETCHAR DbgConsole_Getchar
+#else /* Select printf, scanf, putchar, getchar of toolchain. */
+#define PRINTF printf
+#define SCANF scanf
+#define PUTCHAR putchar
+#define GETCHAR getchar
+#endif /* SDK_DEBUGCONSOLE */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*! @name Initialization*/
+/* @{ */
+
+/*!
+ * @brief Initializes the the peripheral used for debug messages.
+ *
+ * Call this function to enable debug log messages to be output via the specified peripheral,
+ * frequency of peripheral source clock, and base address at the specified baud rate.
+ * After this function has returned, stdout and stdin are connected to the selected peripheral.
+ *
+ * @param baseAddr      Indicates the address of the peripheral used to send debug messages.
+ * @param baudRate      The desired baud rate in bits per second.
+ * @param device        Low level device type for the debug console, can be one of the following.
+ *                      @arg DEBUG_CONSOLE_DEVICE_TYPE_UART,
+ *                      @arg DEBUG_CONSOLE_DEVICE_TYPE_LPUART,
+ *                      @arg DEBUG_CONSOLE_DEVICE_TYPE_LPSCI,
+ *                      @arg DEBUG_CONSOLE_DEVICE_TYPE_USBCDC.
+ * @param clkSrcFreq    Frequency of peripheral source clock.
+ *
+ * @return              Indicates whether initialization was successful or not.
+ * @retval kStatus_Success          Execution successfully
+ * @retval kStatus_Fail             Execution failure
+ * @retval kStatus_InvalidArgument  Invalid argument existed
+ */
+status_t DbgConsole_Init(uint32_t baseAddr, uint32_t baudRate, uint8_t device, uint32_t clkSrcFreq);
+
+/*!
+ * @brief De-initializes the peripheral used for debug messages.
+ *
+ * Call this function to disable debug log messages to be output via the specified peripheral
+ * base address and at the specified baud rate.
+ *
+ * @return Indicates whether de-initialization was successful or not.
+ */
+status_t DbgConsole_Deinit(void);
+
+/*!
+ * @brief Debug console flush log.
+ *
+ * Call this function to wait the buffer empty and io idle before.
+ * If interrupt transfer is using, make sure the global IRQ is enable before call this function
+ * This function should be called when
+ * 1, before enter power down mode
+ * 2, log is required to print to terminal immediately
+ * @return Indicates whether wait idle was successful or not.
+ */
+status_t DbgConsole_Flush(void);
+
+#if SDK_DEBUGCONSOLE
+/*!
+ * @brief Writes formatted output to the standard output stream.
+ *
+ * Call this function to write a formatted output to the standard output stream.
+ *
+ * @param   fmt_s Format control string.
+ * @return  Returns the number of characters printed or a negative value if an error occurs.
+ */
+int DbgConsole_Printf(const char *fmt_s, ...);
+
+/*!
+ * @brief Writes a character to stdout.
+ *
+ * Call this function to write a character to stdout.
+ *
+ * @param   ch Character to be written.
+ * @return  Returns the character written.
+ */
+int DbgConsole_Putchar(int ch);
+
+/*!
+ * @brief Reads formatted data from the standard input stream.
+ *
+ * Call this function to read formatted data from the standard input stream.
+ *
+ * @param   fmt_ptr Format control string.
+ * @return  Returns the number of fields successfully converted and assigned.
+ */
+int DbgConsole_Scanf(char *fmt_ptr, ...);
+
+/*!
+ * @brief Reads a character from standard input.
+ *
+ * Call this function to read a character from standard input.
+ *
+ * @return Returns the character read.
+ */
+int DbgConsole_Getchar(void);
+
+#endif /* SDK_DEBUGCONSOLE */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_DEBUGCONSOLE_H_ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_debug_console_conf.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_debug_console_conf.h
new file mode 100644
index 0000000..de62234
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_debug_console_conf.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_DEBUG_CONSOLE_CONF_H_
+#define _FSL_DEBUG_CONSOLE_CONF_H_
+
+/****************Debug console configuration********************/
+
+/*! @brief If Non-blocking mode is needed, please define it at project setting,
+* otherwise blocking mode is the default transfer mode.
+* Warning: If you want to use non-blocking transfer,please make sure the corresponding
+* IO interrupt is enable, otherwise there is no output.
+* And non-blocking is combine with buffer, no matter bare-metal or rtos.
+*/
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically
+* when
+* non-blocking transfer is using,
+* This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
+* If it is configured too small, log maybe missed , because the log will not be
+* buffered if the buffer is full, and the print will return immediately with -1.
+* And this value should be multiple of 4 to meet memory alignment.
+*
+*/
+#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN
+#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U)
+#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */
+
+/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when
+* non-blocking transfer is using,
+* This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
+* If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small.
+* And this value should be multiple of 4 to meet memory alignment.
+*
+*/
+#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN
+#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (512U)
+#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */
+
+#else
+#define DEBUG_CONSOLE_TRANSFER_BLOCKING
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log
+* length can not bigger than this value.
+* This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if
+* the buffer is too big and current task stack size not big enough.
+*/
+#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN
+#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U)
+#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */
+
+/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log
+* length can not bigger than this value.
+* As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN.
+*/
+#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN
+#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U)
+#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */
+
+/*! @brief Debug console synchronization
+* User should not change these macro for synchronization mode, but add the
+* corresponding synchronization mechanism per different software environment.
+* Such as, if another RTOS is used,
+* add:
+*  #define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3
+* in this configuration file and implement the synchronization in fsl.log.c.
+*/
+/*! @brief synchronization for baremetal software */
+#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0
+/*! @brief synchronization for freertos software */
+#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1
+
+/*! @brief RTOS synchronization mechanism disable
+* If not defined, default is enable, to avoid multitask log print mess.
+* If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c
+* If synchronization is disabled, log maybe messed on terminal.
+*/
+#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#ifdef FSL_RTOS_FREE_RTOS
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS
+#else
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
+#endif /* FSL_RTOS_FREE_RTOS */
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */
+
+/*! @brief echo function support
+* If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO
+* at your project setting.
+*/
+#ifndef DEBUG_CONSOLE_ENABLE_ECHO
+#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0
+#else
+#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1
+#endif /* DEBUG_CONSOLE_ENABLE_ECHO */
+
+/*********************************************************************/
+
+/***************Debug console other configuration*********************/
+/*! @brief Definition to printf the float number. */
+#ifndef PRINTF_FLOAT_ENABLE
+#define PRINTF_FLOAT_ENABLE 0U
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*! @brief Definition to scanf the float number. */
+#ifndef SCANF_FLOAT_ENABLE
+#define SCANF_FLOAT_ENABLE 0U
+#endif /* SCANF_FLOAT_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for printf. */
+#ifndef PRINTF_ADVANCED_ENABLE
+#define PRINTF_ADVANCED_ENABLE 0U
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for scanf. */
+#ifndef SCANF_ADVANCED_ENABLE
+#define SCANF_ADVANCED_ENABLE 0U
+#endif /* SCANF_ADVANCED_ENABLE */
+
+/*******************************************************************/
+
+#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_io.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_io.c
new file mode 100644
index 0000000..10900d7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_io.c
@@ -0,0 +1,655 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include "fsl_io.h"
+#include "fsl_debug_console_conf.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* check avaliable device  */
+#if (defined(FSL_FEATURE_SOC_UART_COUNT) && (FSL_FEATURE_SOC_UART_COUNT != 0))
+#define DEBUG_CONSOLE_IO_UART
+#endif
+
+#if (defined(FSL_FEATURE_SOC_IUART_COUNT) && (FSL_FEATURE_SOC_IUART_COUNT != 0))
+#define DEBUG_CONSOLE_IO_IUART
+#endif
+
+#if (defined(FSL_FEATURE_SOC_LPUART_COUNT) && (FSL_FEATURE_SOC_LPUART_COUNT != 0))
+#define DEBUG_CONSOLE_IO_LPUART
+#endif
+
+#if (defined(FSL_FEATURE_SOC_LPSCI_COUNT) && (FSL_FEATURE_SOC_LPSCI_COUNT != 0))
+#define DEBUG_CONSOLE_IO_LPSCI
+#endif
+
+#if ((defined(FSL_FEATURE_SOC_USB_COUNT) && (FSL_FEATURE_SOC_USB_COUNT == 0)) && defined(BOARD_USE_VIRTUALCOM))
+#define DEBUG_CONSOLE_IO_USBCDC
+#endif
+
+#if (defined(FSL_FEATURE_SOC_FLEXCOMM_COUNT) && (FSL_FEATURE_SOC_FLEXCOMM_COUNT != 0))
+#define DEBUG_CONSOLE_IO_FLEXCOMM
+#endif
+
+#if (defined(FSL_FEATURE_SOC_VFIFO_COUNT) && (FSL_FEATURE_SOC_VFIFO_COUNT != 0))
+#define DEBUG_CONSOLE_IO_VUSART
+#endif
+
+/* configuration for debug console device */
+/* If new device is required as the low level device for debug console,
+ * Add the #elif branch and add the preprocessor macro to judge whether
+ * this kind of device exist in this SOC. */
+#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART)
+#include "fsl_uart.h"
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+static uart_handle_t s_ioUartHandler;
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+#endif /* defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART */
+
+#if defined DEBUG_CONSOLE_IO_LPUART
+#include "fsl_lpuart.h"
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+static lpuart_handle_t s_ioLpuartHandler;
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+#endif /* DEBUG_CONSOLE_IO_LPUART */
+
+#if defined DEBUG_CONSOLE_IO_LPSCI
+#include "fsl_lpsci.h"
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+static lpsci_handle_t s_ioLpsciHandler;
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+#endif /* DEBUG_CONSOLE_IO_LPSCI */
+
+#if defined DEBUG_CONSOLE_IO_USBCDC
+#include "usb_device_config.h"
+#include "usb.h"
+#include "usb_device_cdc_acm.h"
+#include "usb_device_ch9.h"
+#include "virtual_com.h"
+#endif /* DEBUG_CONSOLE_IO_USBCDC */
+
+#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART)
+#include "fsl_usart.h"
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+static usart_handle_t s_ioUsartHandler;
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+#endif /* defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Debug console IO state information. */
+static io_state_t s_debugConsoleIO = {
+    .ioBase = NULL,
+    .ioType = DEBUG_CONSOLE_DEVICE_TYPE_NONE,
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+    .callBack = NULL,
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+};
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+
+#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART)
+static void UART_Callback(UART_Type *base, uart_handle_t *handle, status_t status, void *userData)
+{
+    bool tx = false, rx = false;
+    size_t size = 0U;
+
+    if (status == kStatus_UART_RxIdle)
+    {
+        rx = true;
+        size = handle->txDataSizeAll;
+    }
+
+    if (status == kStatus_UART_TxIdle)
+    {
+        tx = true;
+        size = handle->txDataSizeAll;
+    }
+
+    /* inform the buffer layer that transfer is complete */
+    if (s_debugConsoleIO.callBack != NULL)
+    {
+        /* call buffer callback function */
+        s_debugConsoleIO.callBack(&size, rx, tx);
+    }
+}
+#endif /* defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART */
+
+#if defined DEBUG_CONSOLE_IO_LPSCI
+static void LPSCI_Callback(UART0_Type *base, lpsci_handle_t *handle, status_t status, void *userData)
+{
+    bool tx = false, rx = false;
+    size_t size = 0U;
+
+    if (status == kStatus_LPSCI_RxIdle)
+    {
+        rx = true;
+        size = handle->txDataSizeAll;
+    }
+
+    if (status == kStatus_LPSCI_TxIdle)
+    {
+        tx = true;
+        size = handle->txDataSizeAll;
+    }
+
+    /* inform the buffer layer that transfer is complete */
+    if (s_debugConsoleIO.callBack != NULL)
+    {
+        /* call buffer callback function */
+        s_debugConsoleIO.callBack(&size, rx, tx);
+    }
+}
+#endif /* DEBUG_CONSOLE_IO_LPSCI */
+
+#if defined DEBUG_CONSOLE_IO_LPUART
+static void LPUART_Callback(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData)
+{
+    bool tx = false, rx = false;
+    size_t size = 0U;
+
+    if (status == kStatus_LPUART_RxIdle)
+    {
+        rx = true;
+        size = handle->txDataSizeAll;
+    }
+
+    if (status == kStatus_LPUART_TxIdle)
+    {
+        tx = true;
+        size = handle->txDataSizeAll;
+    }
+
+    /* inform the buffer layer that transfer is complete */
+    if (s_debugConsoleIO.callBack != NULL)
+    {
+        /* call buffer callback function */
+        s_debugConsoleIO.callBack(&size, rx, tx);
+    }
+}
+#endif /* DEBUG_CONSOLE_IO_LPUART */
+
+#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART)
+static void USART_Callback(USART_Type *base, usart_handle_t *handle, status_t status, void *userData)
+{
+    bool tx = false, rx = false;
+    size_t size = 0U;
+
+    if (status == kStatus_USART_RxIdle)
+    {
+        rx = true;
+        size = handle->txDataSizeAll;
+    }
+
+    if (status == kStatus_USART_TxIdle)
+    {
+        tx = true;
+        size = handle->txDataSizeAll;
+    }
+
+    /* inform the buffer layer that transfer is complete */
+    if (s_debugConsoleIO.callBack != NULL)
+    {
+        /* call buffer callback function */
+        s_debugConsoleIO.callBack(&size, rx, tx);
+    }
+}
+#endif /* defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART */
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+void IO_Init(io_state_t *io, uint32_t baudRate, uint32_t clkSrcFreq, uint8_t *ringBuffer)
+{
+    assert(NULL != io);
+
+    /* record device type/base */
+    s_debugConsoleIO.ioType = io->ioType;
+    s_debugConsoleIO.ioBase = (void *)(io->ioBase);
+
+    switch (s_debugConsoleIO.ioType)
+    {
+#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART)
+        case DEBUG_CONSOLE_DEVICE_TYPE_UART:
+        case DEBUG_CONSOLE_DEVICE_TYPE_IUART:
+        {
+            uart_config_t uart_config;
+            UART_GetDefaultConfig(&uart_config);
+            uart_config.baudRate_Bps = baudRate;
+            /* Enable clock and initial UART module follow user configure structure. */
+            UART_Init((UART_Type *)s_debugConsoleIO.ioBase, &uart_config, clkSrcFreq);
+            UART_EnableTx(s_debugConsoleIO.ioBase, true);
+            UART_EnableRx(s_debugConsoleIO.ioBase, true);
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+            s_debugConsoleIO.callBack = io->callBack;
+            /* create handler for interrupt transfer */
+            UART_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioUartHandler, UART_Callback, NULL);
+            /* start ring buffer */
+            UART_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioUartHandler, ringBuffer,
+                                         DEBUG_CONSOLE_RECEIVE_BUFFER_LEN);
+#endif
+        }
+        break;
+#endif
+
+#if defined DEBUG_CONSOLE_IO_LPUART
+        case DEBUG_CONSOLE_DEVICE_TYPE_LPUART:
+        {
+            lpuart_config_t lpuart_config;
+            LPUART_GetDefaultConfig(&lpuart_config);
+            lpuart_config.baudRate_Bps = baudRate;
+            /* Enable clock and initial UART module follow user configure structure. */
+            LPUART_Init((LPUART_Type *)s_debugConsoleIO.ioBase, &lpuart_config, clkSrcFreq);
+            LPUART_EnableTx(s_debugConsoleIO.ioBase, true);
+            LPUART_EnableRx(s_debugConsoleIO.ioBase, true);
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+            s_debugConsoleIO.callBack = io->callBack;
+            /* create handler for interrupt transfer */
+            LPUART_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioLpuartHandler, LPUART_Callback, NULL);
+            /* start ring buffer */
+            LPUART_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioLpuartHandler, ringBuffer,
+                                           DEBUG_CONSOLE_RECEIVE_BUFFER_LEN);
+#endif
+        }
+        break;
+#endif
+#if defined DEBUG_CONSOLE_IO_LPSCI
+        case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI:
+        {
+            lpsci_config_t lpsci_config;
+            LPSCI_GetDefaultConfig(&lpsci_config);
+            lpsci_config.baudRate_Bps = baudRate;
+            /* Enable clock and initial UART module follow user configure structure. */
+            LPSCI_Init((UART0_Type *)s_debugConsoleIO.ioBase, &lpsci_config, clkSrcFreq);
+            LPSCI_EnableTx(s_debugConsoleIO.ioBase, true);
+            LPSCI_EnableRx(s_debugConsoleIO.ioBase, true);
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+            s_debugConsoleIO.callBack = io->callBack;
+            /* create handler for interrupt transfer */
+            LPSCI_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioLpsciHandler, LPSCI_Callback, NULL);
+            /* start ring buffer */
+            LPSCI_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioLpsciHandler, ringBuffer,
+                                          DEBUG_CONSOLE_RECEIVE_BUFFER_LEN);
+#endif
+        }
+        break;
+#endif
+#if defined DEBUG_CONSOLE_IO_USBCDC
+        case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC:
+        {
+            s_debugConsoleIO.ioBase = USB_VcomInit();
+        }
+        break;
+#endif
+#if defined DEBUG_CONSOLE_IO_FLEXCOMM
+        case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM:
+        {
+            usart_config_t usart_config;
+            USART_GetDefaultConfig(&usart_config);
+            usart_config.baudRate_Bps = baudRate;
+            /* Enable clock and initial UART module follow user configure structure. */
+            USART_Init((USART_Type *)s_debugConsoleIO.ioBase, &usart_config, clkSrcFreq);
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+            s_debugConsoleIO.callBack = io->callBack;
+            /* create handler for interrupt transfer */
+            USART_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioUsartHandler, USART_Callback, NULL);
+            /* start ring buffer */
+            USART_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioUsartHandler, ringBuffer,
+                                          DEBUG_CONSOLE_RECEIVE_BUFFER_LEN);
+#endif
+        }
+        break;
+#endif
+#if defined DEBUG_CONSOLE_IO_VUSART
+        case DEBUG_CONSOLE_DEVICE_TYPE_VUSART:
+        {
+            usart_config_t usart_config;
+            USART_GetDefaultConfig(&usart_config);
+            usart_config.baudRate_Bps = baudRate;
+            usart_config.enableRx = true;
+            usart_config.enableTx = true;
+            /* Enable clock and initial UART module follow user configure structure. */
+            USART_Init((USART_Type *)s_debugConsoleIO.ioBase, &usart_config, clkSrcFreq);
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+            s_debugConsoleIO.callBack = io->callBack;
+            /* create handler for interrupt transfer */
+            USART_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioUsartHandler, USART_Callback, NULL);
+            /* start ring buffer */
+            USART_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioUsartHandler, ringBuffer,
+                                          DEBUG_CONSOLE_RECEIVE_BUFFER_LEN);
+#endif
+        }
+        break;
+#endif
+    }
+}
+
+status_t IO_Deinit(void)
+{
+    if (s_debugConsoleIO.ioType == DEBUG_CONSOLE_DEVICE_TYPE_NONE)
+    {
+        return kStatus_Success;
+    }
+
+    switch (s_debugConsoleIO.ioType)
+    {
+#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART)
+        case DEBUG_CONSOLE_DEVICE_TYPE_UART:
+        case DEBUG_CONSOLE_DEVICE_TYPE_IUART:
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+            /* stop ring buffer */
+            UART_TransferStopRingBuffer(s_debugConsoleIO.ioBase, &s_ioUartHandler);
+#endif
+            /* Disable UART module. */
+            UART_Deinit((UART_Type *)s_debugConsoleIO.ioBase);
+
+            break;
+#endif
+#if defined DEBUG_CONSOLE_IO_LPSCI
+        case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI:
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+            /* stop ring buffer */
+            LPSCI_TransferStopRingBuffer(s_debugConsoleIO.ioBase, &s_ioLpsciHandler);
+#endif
+            /* Disable LPSCI module. */
+            LPSCI_Deinit((UART0_Type *)s_debugConsoleIO.ioBase);
+
+            break;
+#endif
+#if defined DEBUG_CONSOLE_IO_LPUART
+        case DEBUG_CONSOLE_DEVICE_TYPE_LPUART:
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+            /* stop ring buffer */
+            LPUART_TransferStopRingBuffer(s_debugConsoleIO.ioBase, &s_ioLpuartHandler);
+#endif
+            /* Disable LPUART module. */
+            LPUART_Deinit((LPUART_Type *)s_debugConsoleIO.ioBase);
+
+            break;
+#endif
+#if defined DEBUG_CONSOLE_IO_USBCDC
+        case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC:
+            /* Disable USBCDC module. */
+            USB_VcomDeinit(s_debugConsoleIO.ioBase);
+            break;
+#endif
+#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART)
+        case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM:
+        case DEBUG_CONSOLE_DEVICE_TYPE_VUSART:
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+            /* stop ring buffer */
+            USART_TransferStopRingBuffer(s_debugConsoleIO.ioBase, &s_ioUsartHandler);
+#endif
+            /* deinit IO */
+            USART_Deinit((USART_Type *)s_debugConsoleIO.ioBase);
+
+            break;
+#endif
+        default:
+            s_debugConsoleIO.ioType = DEBUG_CONSOLE_DEVICE_TYPE_NONE;
+            break;
+    }
+
+    s_debugConsoleIO.ioType = DEBUG_CONSOLE_DEVICE_TYPE_NONE;
+
+    return kStatus_Success;
+}
+
+status_t IO_WaitIdle(void)
+{
+    switch (s_debugConsoleIO.ioType)
+    {
+#if (defined DEBUG_CONSOLE_IO_UART)
+        case DEBUG_CONSOLE_DEVICE_TYPE_UART:
+            /* wait transfer complete flag */
+            while (!(UART_GetStatusFlags(s_debugConsoleIO.ioBase) & kUART_TransmissionCompleteFlag))
+                ;
+            break;
+#endif
+
+#if (defined DEBUG_CONSOLE_IO_IUART)
+        case DEBUG_CONSOLE_DEVICE_TYPE_IUART:
+            /* wait transfer complete flag */
+            while (!(UART_GetStatusFlag(s_debugConsoleIO.ioBase, kUART_TxCompleteFlag)))
+                ;
+            break;
+#endif
+
+#if defined DEBUG_CONSOLE_IO_LPSCI
+        case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI:
+            /* wait transfer complete flag */
+            while (!(LPSCI_GetStatusFlags(s_debugConsoleIO.ioBase) & kLPSCI_TransmissionCompleteFlag))
+                ;
+            break;
+#endif
+
+#if defined DEBUG_CONSOLE_IO_LPUART
+        case DEBUG_CONSOLE_DEVICE_TYPE_LPUART:
+            /* wait transfer complete flag */
+            while (!(LPUART_GetStatusFlags(s_debugConsoleIO.ioBase) & kLPUART_TransmissionCompleteFlag))
+                ;
+            break;
+#endif
+
+#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART)
+        case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM:
+        case DEBUG_CONSOLE_DEVICE_TYPE_VUSART:
+            /* wait transfer complete flag */
+            while (!(USART_GetStatusFlags(s_debugConsoleIO.ioBase) & kUSART_TxFifoEmptyFlag))
+                ;
+            break;
+#endif
+        default:
+            break;
+    }
+
+    return kStatus_Success;
+}
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+
+status_t IO_Transfer(uint8_t *ch, size_t size, bool tx)
+{
+    status_t status = kStatus_Fail;
+
+    switch (s_debugConsoleIO.ioType)
+    {
+#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART)
+        case DEBUG_CONSOLE_DEVICE_TYPE_UART:
+        case DEBUG_CONSOLE_DEVICE_TYPE_IUART:
+        {
+            uart_transfer_t transfer = {0U};
+            transfer.data = ch;
+            transfer.dataSize = size;
+            /* transfer data */
+            if (tx)
+            {
+                status = UART_TransferSendNonBlocking(s_debugConsoleIO.ioBase, &s_ioUartHandler, &transfer);
+            }
+            else
+            {
+                status = UART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioUartHandler, &transfer, NULL);
+            }
+        }
+        break;
+#endif
+#if defined DEBUG_CONSOLE_IO_LPSCI
+        case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI:
+        {
+            lpsci_transfer_t transfer = {0U};
+            transfer.data = ch;
+            transfer.dataSize = size;
+            /* transfer data */
+            if (tx)
+            {
+                status = LPSCI_TransferSendNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpsciHandler, &transfer);
+            }
+            else
+            {
+                status = LPSCI_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpsciHandler, &transfer, NULL);
+            }
+        }
+        break;
+#endif
+
+#if defined DEBUG_CONSOLE_IO_LPUART
+        case DEBUG_CONSOLE_DEVICE_TYPE_LPUART:
+        {
+            lpuart_transfer_t transfer = {0U};
+            transfer.data = ch;
+            transfer.dataSize = size;
+            /* transfer data */
+            if (tx)
+            {
+                status = LPUART_TransferSendNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpuartHandler, &transfer);
+            }
+            else
+            {
+                status =
+                    LPUART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpuartHandler, &transfer, NULL);
+            }
+        }
+        break;
+#endif
+
+#if defined DEBUG_CONSOLE_IO_USBCDC
+        case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC:
+        {
+            if (tx)
+            {
+                USB_VcomWriteBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+            else
+            {
+                USB_VcomReadBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+        }
+        break;
+#endif
+
+#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART)
+        case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM:
+        case DEBUG_CONSOLE_DEVICE_TYPE_VUSART:
+        {
+            usart_transfer_t transfer = {0U};
+            transfer.data = ch;
+            transfer.dataSize = size;
+            /* transfer data */
+            if (tx)
+            {
+                status = USART_TransferSendNonBlocking(s_debugConsoleIO.ioBase, &s_ioUsartHandler, &transfer);
+            }
+            else
+            {
+                status = USART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioUsartHandler, &transfer, NULL);
+            }
+        }
+        break;
+#endif
+        default:
+            break;
+    }
+
+    return status;
+}
+
+#else
+
+status_t IO_Transfer(uint8_t *ch, size_t size, bool tx)
+{
+    status_t status = kStatus_Success;
+    switch (s_debugConsoleIO.ioType)
+    {
+#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART)
+        case DEBUG_CONSOLE_DEVICE_TYPE_UART:
+        case DEBUG_CONSOLE_DEVICE_TYPE_IUART:
+        {
+            if (tx)
+            {
+                UART_WriteBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+            else
+            {
+                status = UART_ReadBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+        }
+        break;
+#endif
+#if defined DEBUG_CONSOLE_IO_LPSCI
+        case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI:
+        {
+            if (tx)
+            {
+                LPSCI_WriteBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+            else
+            {
+                status = LPSCI_ReadBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+        }
+        break;
+#endif
+
+#if defined DEBUG_CONSOLE_IO_LPUART
+        case DEBUG_CONSOLE_DEVICE_TYPE_LPUART:
+        {
+            if (tx)
+            {
+                LPUART_WriteBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+            else
+            {
+                status = LPUART_ReadBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+        }
+        break;
+#endif
+
+#if defined DEBUG_CONSOLE_IO_USBCDC
+        case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC:
+        {
+            if (tx)
+            {
+                USB_VcomWriteBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+            else
+            {
+                status = USB_VcomReadBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+        }
+        break;
+#endif
+
+#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART)
+        case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM:
+        case DEBUG_CONSOLE_DEVICE_TYPE_VUSART:
+        {
+            if (tx)
+            {
+                USART_WriteBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+            else
+            {
+                status = USART_ReadBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+        }
+        break;
+#endif
+        default:
+            status = kStatus_Fail;
+            break;
+    }
+
+    return status;
+}
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_io.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_io.h
new file mode 100644
index 0000000..01367a8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_io.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FSL_IO_H
+#define _FSL_IO_H
+
+#include "fsl_common.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief define a notify callback for IO
+* @param size , transfer data size.
+* @param rx, indicate a rx transfer is success.
+* @param tx, indicate a tx transfer is success.
+*/
+typedef void (*notify)(size_t *size, bool rx, bool tx);
+
+/*! @brief State structure storing io. */
+typedef struct io_State
+{
+    void *ioBase;   /*!< Base of the IP register. */
+    uint8_t ioType; /*!< device type */
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+    notify callBack; /*!< define the callback function for buffer */
+#endif
+
+} io_state_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @brief io init function.
+ *
+ * Call this function to init IO.
+ *
+ * @param io configuration pointer
+ * @param baudRate baud rate
+ * @param clkSrcFreq clock freq
+ * @param ringbuffer used to receive character
+ */
+void IO_Init(io_state_t *io, uint32_t baudRate, uint32_t clkSrcFreq, uint8_t *ringBuffer);
+
+/*!
+ * @brief Deinit IO.
+ *
+ * Call this function to Deinit IO.
+ *
+ * @return deinit status
+ */
+status_t IO_Deinit(void);
+
+/*!
+ * @brief io transfer function.
+ *
+ * Call this function to transfer log.
+ * Print log:
+ * @code
+ * IO_Transfer(ch, size, true);
+ * @endcode
+ * Scanf log:
+ * @code
+ * IO_Transfer(ch, size, false);
+ * @endcode
+ *
+ * @param   ch  transfer buffer pointer
+ * @param	size transfer size
+ * @param   tx indicate the transfer is TX or RX
+ */
+status_t IO_Transfer(uint8_t *ch, size_t size, bool tx);
+
+/*!
+ * @brief io wait idle.
+ *
+ * Call this function to wait the io idle
+ *
+ * @return Indicates whether wait idle was successful or not.
+ */
+status_t IO_WaitIdle(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _FSL_IO_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_log.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_log.c
new file mode 100644
index 0000000..4dd3caa
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_log.c
@@ -0,0 +1,547 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include "fsl_log.h"
+#include "fsl_debug_console_conf.h"
+#include "fsl_io.h"
+#ifdef FSL_RTOS_FREE_RTOS
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+#endif
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifndef BACKSPACE
+/*! @brief character backspace ASCII value */
+#define BACKSPACE 127
+#endif
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*! @brief increase pop member */
+#define LOG_CHECK_BUFFER_INDEX_OVERFLOW(index)          \
+    {                                                   \
+        if (index >= DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN) \
+        {                                               \
+            index -= DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN; \
+        }                                               \
+    \
+\
+}
+
+/*! @brief get current runing environment is ISR or not */
+#ifdef __CA7_REV
+#define IS_RUNNING_IN_ISR() SystemGetIRQNestingLevel()
+#else
+#define IS_RUNNING_IN_ISR() __get_IPSR()
+#endif /* __CA7_REV */
+
+#else
+#define IS_RUNNING_IN_ISR() (0U)
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+/* define for rtos */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+/* metex semaphore */
+#define LOG_CREATE_MUTEX_SEMAPHORE(mutex) (mutex = xSemaphoreCreateMutex())
+
+#define LOG_GIVE_MUTEX_SEMAPHORE(mutex) \
+    \
+{                                \
+        if (IS_RUNNING_IN_ISR() == 0U)  \
+        {                               \
+            xSemaphoreGive(mutex);      \
+        }                               \
+    \
+}
+
+#define LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex)  \
+    \
+{                                          \
+        if (IS_RUNNING_IN_ISR() == 0U)            \
+        {                                         \
+            xSemaphoreTake(mutex, portMAX_DELAY); \
+        }                                         \
+    \
+}
+
+#define LOG_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) \
+    \
+{                                                    \
+        if (IS_RUNNING_IN_ISR() == 0U)                      \
+        {                                                   \
+            result = xSemaphoreTake(mutex, 0U);             \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            result = 1U;                                    \
+        }                                                   \
+    \
+}
+
+/* Binary semaphore */
+#define LOG_CREATE_BINARY_SEMAPHORE(binary) (binary = xSemaphoreCreateBinary())
+#define LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) (xSemaphoreTake(binary, portMAX_DELAY))
+#define LOG_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (xSemaphoreGiveFromISR(binary, NULL))
+
+#elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM)
+
+#define LOG_CREATE_MUTEX_SEMAPHORE(mutex)
+#define LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex)
+#define LOG_GIVE_MUTEX_SEMAPHORE(mutex)
+#define LOG_CREATE_BINARY_SEMAPHORE(binary)
+#define LOG_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U)
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#define LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) \
+    \
+{                                           \
+        while (!binary)                            \
+            ;                                      \
+        binary = false;                            \
+    \
+\
+}
+#define LOG_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (binary = true)
+#else
+#define LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(binary)
+#define LOG_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary)
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+/* add other implementation here
+*such as :
+* #elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_xxx)
+*/
+
+#else
+
+#define LOG_CREATE_MUTEX_SEMAPHORE(mutex)
+#define LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex)
+#define LOG_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U)
+#define LOG_GIVE_MUTEX_SEMAPHORE(mutex)
+#define LOG_CREATE_BINARY_SEMAPHORE(binary)
+#define LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(binary)
+#define LOG_GIVE_BINARY_SEMAPHORE(binary)
+#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*! @brief Define the buffer
+* The total buffer size should be calucate as (BUFFER_SUPPORT_LOG_LENGTH + 1) * BUFFER_SUPPORT_LOG_NUM * 4
+*/
+typedef struct _log_buffer
+{
+    volatile uint16_t totalIndex;                     /*!< indicate the total usage of the buffer */
+    volatile uint16_t pushIndex;                      /*!< indicate the next push index */
+    volatile uint16_t popIndex;                       /*!< indicate the pop index */
+    uint8_t txBuf[DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN]; /*!< buffer to store printf log */
+
+    uint8_t rxBuf[DEBUG_CONSOLE_RECEIVE_BUFFER_LEN]; /*!< buffer to store scanf log */
+} log_buffer_t;
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/* A global log buffer */
+static log_buffer_t s_log_buffer;
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+/* lock definition */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+static SemaphoreHandle_t s_logPushSemaphore = NULL;
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+static SemaphoreHandle_t s_logPopSemaphore = NULL;
+static SemaphoreHandle_t s_logReadSemaphore = NULL;
+
+#elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM)
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+
+static volatile bool s_logReadSemaphore = false; /* transferred event from ISR for bare-metal + interrupt */
+
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+#else
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+/*******************************************************************************
+* Prototypes
+******************************************************************************/
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*!
+ * @brief callback function for IO layer to notify LOG
+ *
+ * @param size last transfer data size
+ * @param receive indicate a RX transfer
+ * @param transmit indicate a TX transfer
+ *
+ */
+static void LOG_Transferred(size_t *size, bool receive, bool transmit);
+
+/*!
+ * @brief log push function
+ *
+ * @param buf target buffer
+ * @param size log size
+ *
+ */
+static int LOG_BufPush(uint8_t *buf, size_t size);
+
+/*!
+ * @brief Get next avaliable log
+ *
+ * @param next avaliable size
+ * @return next avaliable address
+ */
+static uint8_t *LOG_BufGetNextAvaliableLog(size_t *size);
+
+/*!
+ * @brief buf pop
+ *
+ * @param size log size popped and next available log size
+ * @return next avaliable address
+ */
+static uint8_t *LOG_BufPop(size_t *size);
+
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+/*!
+ * @brief read one character
+ *
+ * @param ch character address
+ * @return indicate the read status
+ *
+ */
+static status_t LOG_ReadOneCharacter(uint8_t *ch);
+
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+/*!
+ * @brief echo one character
+ *
+ * @param ch character address
+ * @param isGetchar flag to distinguish getchar from scanf
+ * @param index special for scanf to support backspace
+ * @return indicate the read status
+ *
+ */
+static status_t LOG_EchoCharacter(uint8_t *ch, bool isGetChar, int *index);
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+status_t LOG_Init(uint32_t baseAddr, uint8_t device, uint32_t baudRate, uint32_t clkSrcFreq)
+{
+    io_state_t io;
+    /* init io */
+    io.ioBase = (void *)baseAddr;
+    io.ioType = device;
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+    /* memset the global queue */
+    memset(&s_log_buffer, 0U, sizeof(s_log_buffer));
+    /* init callback for NON-BLOCKING */
+    io.callBack = LOG_Transferred;
+    /* io init function */
+    IO_Init(&io, baudRate, clkSrcFreq, s_log_buffer.rxBuf);
+    /* Debug console buffer push lock create */
+    LOG_CREATE_MUTEX_SEMAPHORE(s_logPushSemaphore);
+#else
+    IO_Init(&io, baudRate, clkSrcFreq, NULL);
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+    /* Debug console lock create */
+    LOG_CREATE_MUTEX_SEMAPHORE(s_logPopSemaphore);
+    LOG_CREATE_BINARY_SEMAPHORE(s_logReadSemaphore);
+
+    return kStatus_Success;
+}
+
+void LOG_Deinit(void)
+{
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+    /* memset the global queue */
+    memset(&s_log_buffer, 0U, sizeof(s_log_buffer));
+#endif /*DEBUG_CONSOLE_TRANSFER_NON_BLOCKING*/
+    /* Deinit IO */
+    IO_Deinit();
+}
+
+status_t LOG_WaitIdle(void)
+{
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+    /* wait buffer empty */
+    while (!(s_log_buffer.totalIndex == 0U))
+        ;
+#endif /*DEBUG_CONSOLE_TRANSFER_NON_BLOCKING*/
+    /* wait IO idle */
+    IO_WaitIdle();
+
+    return kStatus_Success;
+}
+
+int LOG_Push(uint8_t *buf, size_t size)
+{
+    assert(buf != NULL);
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+    /* push to buffer */
+    LOG_BufPush(buf, size);
+    buf = LOG_BufGetNextAvaliableLog(&size);
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+    /* pop log */
+    return LOG_Pop(buf, size);
+}
+
+int LOG_Pop(uint8_t *buf, size_t size)
+{
+    uint8_t getLock = 0U;
+
+    if ((0 != size) && (NULL != buf))
+    {
+        /* take POP lock, should be non-blocking */
+        LOG_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(s_logPopSemaphore, getLock);
+
+        if (getLock)
+        {
+            /* call IO transfer function */
+            if (IO_Transfer(buf, size, true) != kStatus_Success)
+            {
+                size = 0U;
+            }
+            /* release POP lock */
+            LOG_GIVE_MUTEX_SEMAPHORE(s_logPopSemaphore);
+        }
+    }
+
+    return size;
+}
+
+int LOG_ReadLine(uint8_t *buf, size_t size)
+{
+    assert(buf != NULL);
+
+    int i = 0;
+
+    /* take mutex lock function */
+    LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_logPushSemaphore);
+
+    for (i = 0; i < size; i++)
+    {
+        /* recieve one char every time */
+        if (LOG_ReadOneCharacter(&buf[i]) != kStatus_Success)
+        {
+            return -1;
+        }
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+        LOG_EchoCharacter(&buf[i], false, &i);
+#endif
+        /* analysis data */
+        if ((buf[i] == '\r') || (buf[i] == '\n'))
+        {
+            /* End of Line. */
+            if (i == 0)
+            {
+                buf[i] = '\0';
+                i = -1;
+            }
+            else
+            {
+                break;
+            }
+        }
+    }
+    /* get char should not add '\0'*/
+    if (i == size)
+    {
+        buf[i] = '\0';
+    }
+    else
+    {
+        buf[i + 1] = '\0';
+    }
+
+    /* release mutex lock function */
+    LOG_GIVE_MUTEX_SEMAPHORE(s_logPushSemaphore);
+
+    return i;
+}
+
+int LOG_ReadCharacter(uint8_t *ch)
+{
+    assert(ch != NULL);
+    int ret = 0;
+
+    /* take mutex lock function */
+    LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_logPushSemaphore);
+    /* read one character */
+    if (LOG_ReadOneCharacter(ch) == kStatus_Success)
+    {
+        ret = 1;
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+        LOG_EchoCharacter(ch, true, NULL);
+#endif
+    }
+    else
+    {
+        ret = -1;
+    }
+    /* release mutex lock function */
+    LOG_GIVE_MUTEX_SEMAPHORE(s_logPushSemaphore);
+
+    return ret;
+}
+
+static status_t LOG_ReadOneCharacter(uint8_t *ch)
+{
+    /* recieve one char every time */
+    if (IO_Transfer(ch, 1U, false) != kStatus_Success)
+    {
+        return kStatus_Fail;
+    }
+
+    /* wait release from ISR */
+    LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(s_logReadSemaphore);
+
+    return kStatus_Success;
+}
+
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+static status_t LOG_EchoCharacter(uint8_t *ch, bool isGetChar, int *index)
+{
+    /* Due to scanf take \n and \r as end of string,should not echo */
+    if (((*ch != '\r') && (*ch != '\n')) || (isGetChar))
+    {
+        /* recieve one char every time */
+        if (IO_Transfer(ch, 1U, true) != kStatus_Success)
+        {
+            return kStatus_Fail;
+        }
+    }
+
+    if (!isGetChar)
+    {
+        if ((*index > 0) && (*ch == BACKSPACE))
+        {
+            *index -= 2;
+        }
+    }
+
+    return kStatus_Success;
+}
+#endif
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+static int LOG_BufPush(uint8_t *buf, size_t size)
+{
+    uint32_t pushIndex = 0U, i = 0U;
+    bool pushAvaliable = false;
+
+    /* take mutex lock function */
+    LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_logPushSemaphore);
+    if (size <= (DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN - s_log_buffer.totalIndex))
+    {
+        /* get push index */
+        pushIndex = s_log_buffer.pushIndex;
+        s_log_buffer.pushIndex += size;
+        /* check index overflow */
+        LOG_CHECK_BUFFER_INDEX_OVERFLOW(s_log_buffer.pushIndex);
+        /* update push/total index value */
+        s_log_buffer.totalIndex += size;
+        pushAvaliable = true;
+    }
+    /* release mutex lock function */
+    LOG_GIVE_MUTEX_SEMAPHORE(s_logPushSemaphore);
+
+    /* check the buffer if have enough space to store the log */
+    if (pushAvaliable)
+    {
+        for (i = size; i > 0; i--)
+        {
+            /* copy log to buffer, the buffer only support a fixed length argument, if the log argument
+            is longer than the fixed length, the left argument will be losed */
+            s_log_buffer.txBuf[pushIndex] = *buf++;
+            /* increase index */
+            pushIndex++;
+            /* check index overflow */
+            LOG_CHECK_BUFFER_INDEX_OVERFLOW(pushIndex);
+        }
+    }
+    else
+    {
+        size = 0U;
+    }
+
+    return size;
+}
+
+static uint8_t *LOG_BufGetNextAvaliableLog(size_t *size)
+{
+    uint16_t popIndex = s_log_buffer.popIndex;
+
+    /* get avaliable size */
+    if (s_log_buffer.totalIndex > (DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN - popIndex))
+    {
+        *size = (DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN - popIndex);
+    }
+    else
+    {
+        *size = s_log_buffer.totalIndex;
+    }
+
+    /* return address */
+    return (&(s_log_buffer.txBuf[popIndex]));
+}
+
+static uint8_t *LOG_BufPop(size_t *size)
+{
+    if (s_log_buffer.totalIndex >= *size)
+    {
+        /* decrease the log total member */
+        s_log_buffer.totalIndex -= *size;
+        /* there is more log in the queue to be pushed */
+        if (s_log_buffer.totalIndex > 0U)
+        {
+            /* update the pop index */
+            s_log_buffer.popIndex += *size;
+            /* check index overflow */
+            LOG_CHECK_BUFFER_INDEX_OVERFLOW(s_log_buffer.popIndex);
+
+            return LOG_BufGetNextAvaliableLog(size);
+        }
+        else
+        {
+            /* reset push and pop */
+            s_log_buffer.popIndex = 0U;
+            s_log_buffer.pushIndex = 0U;
+            *size = 0U;
+        }
+    }
+
+    return NULL;
+}
+
+static void LOG_Transferred(size_t *size, bool receive, bool transmit)
+{
+    uint8_t *addr = NULL;
+
+    if (transmit)
+    {
+        addr = LOG_BufPop(size);
+        /* continue pop log from buffer */
+        LOG_Pop(addr, *size);
+    }
+
+    if (receive)
+    {
+        /* release from ISR */
+        LOG_GIVE_BINARY_SEMAPHORE_FROM_ISR(s_logReadSemaphore);
+    }
+}
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_log.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_log.h
new file mode 100644
index 0000000..c49aa1c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_log.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FSL_LOG_H
+#define _FSL_LOG_H
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*************************************************************************************************
+ * Prototypes
+ ************************************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @brief Initializes
+ *
+ * Call this function to init the buffer
+ * @param baseAddr, device base address
+ * @param device, device type
+ * @param baudRate, device communicate baudrate
+ * @param clkSrcFreq, device source clock freq
+ *
+ * @return              	Indicates whether initialization was successful or not.
+ * @retval kStatus_Success  Execution successfully
+ * @retval kStatus_Fail     Execution failure
+ */
+status_t LOG_Init(uint32_t baseAddr, uint8_t device, uint32_t baudRate, uint32_t clkSrcFreq);
+
+/*!
+ * @brief De-Initializes
+ *
+ * Call this function to deinit the buffer
+ *
+ * @return Indicates whether Deinit was successful or not.
+ */
+void LOG_Deinit(void);
+
+/*!
+ * @brief log push interface
+ *
+ * Call this function to print log
+ * @param fmt, buffer pointer
+ * @param size, avaliable size
+ * @return indicate the push size
+ * @retval-1 indicate buffer is full or transfer fail.
+ * @retval size return the push log size.
+ */
+int LOG_Push(uint8_t *buf, size_t size);
+
+/*!
+ * @brief log read one line function
+ *
+ * Call this function to print log
+ * @param fmt, buffer pointer
+ * @param size, avaliable size
+ * @reutrn the number of the recieved character
+ */
+int LOG_ReadLine(uint8_t *buf, size_t size);
+
+/*!
+ * @brief log read one character function
+ *
+ * Call this function to GETCHAR
+ * @param ch receive address
+ * @reutrn the number of the recieved character
+ */
+int LOG_ReadCharacter(uint8_t *ch);
+
+/*!
+ * @brief wait log and io idle
+ *
+ * Call this function to wait log buffer empty and io idle before enter low power mode.
+ * @return Indicates whether wait idle was successful or not.
+ */
+status_t LOG_WaitIdle(void);
+
+/*!
+ * @brief log pop function
+ *
+ * Call this function to pop log from buffer.
+ * @param buf buffer address to pop
+ * @param size log size to pop
+ * @return pop log size.
+ */
+int LOG_Pop(uint8_t *buf, size_t size);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_str.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_str.c
new file mode 100644
index 0000000..a0e7dac
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_str.c
@@ -0,0 +1,1300 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include 
+#include 
+#include 
+#include "fsl_str.h"
+#include "fsl_debug_console_conf.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief The overflow value.*/
+#ifndef HUGE_VAL
+#define HUGE_VAL (99.e99)
+#endif /* HUGE_VAL */
+
+#if SCANF_FLOAT_ENABLE
+static double fnum = 0.0;
+#endif /* SCANF_FLOAT_ENABLE */
+
+#if PRINTF_ADVANCED_ENABLE
+/*! @brief Specification modifier flags for printf. */
+enum _debugconsole_printf_flag
+{
+    kPRINTF_Minus = 0x01U,              /*!< Minus FLag. */
+    kPRINTF_Plus = 0x02U,               /*!< Plus Flag. */
+    kPRINTF_Space = 0x04U,              /*!< Space Flag. */
+    kPRINTF_Zero = 0x08U,               /*!< Zero Flag. */
+    kPRINTF_Pound = 0x10U,              /*!< Pound Flag. */
+    kPRINTF_LengthChar = 0x20U,         /*!< Length: Char Flag. */
+    kPRINTF_LengthShortInt = 0x40U,     /*!< Length: Short Int Flag. */
+    kPRINTF_LengthLongInt = 0x80U,      /*!< Length: Long Int Flag. */
+    kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */
+};
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+/*! @brief Specification modifier flags for scanf. */
+enum _debugconsole_scanf_flag
+{
+    kSCANF_Suppress = 0x2U,      /*!< Suppress Flag. */
+    kSCANF_DestMask = 0x7cU,     /*!< Destination Mask. */
+    kSCANF_DestChar = 0x4U,      /*!< Destination Char Flag. */
+    kSCANF_DestString = 0x8U,    /*!< Destination String FLag. */
+    kSCANF_DestSet = 0x10U,      /*!< Destination Set Flag. */
+    kSCANF_DestInt = 0x20U,      /*!< Destination Int Flag. */
+    kSCANF_DestFloat = 0x30U,    /*!< Destination Float Flag. */
+    kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */
+#if SCANF_ADVANCED_ENABLE
+    kSCANF_LengthChar = 0x100U,        /*!< Length Char Flag. */
+    kSCANF_LengthShortInt = 0x200U,    /*!< Length ShortInt Flag. */
+    kSCANF_LengthLongInt = 0x400U,     /*!< Length LongInt Flag. */
+    kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */
+#endif                                 /* SCANF_ADVANCED_ENABLE */
+#if PRINTF_FLOAT_ENABLE
+    kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */
+#endif                                     /*PRINTF_FLOAT_ENABLE */
+    kSCANF_TypeSinged = 0x2000U,           /*!< TypeSinged Flag. */
+};
+
+/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */
+#if defined(__CC_ARM)
+#pragma diag_suppress 1256
+#endif /* __CC_ARM */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Scanline function which ignores white spaces.
+ *
+ * @param[in]   s The address of the string pointer to update.
+ * @return      String without white spaces.
+ */
+static uint32_t ScanIgnoreWhiteSpace(const char **s);
+
+/*!
+ * @brief Converts a radix number to a string and return its length.
+ *
+ * @param[in] numstr    Converted string of the number.
+ * @param[in] nump      Pointer to the number.
+ * @param[in] neg       Polarity of the number.
+ * @param[in] radix     The radix to be converted to.
+ * @param[in] use_caps  Used to identify %x/X output format.
+
+ * @return Length of the converted string.
+ */
+static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps);
+
+#if PRINTF_FLOAT_ENABLE
+/*!
+ * @brief Converts a floating radix number to a string and return its length.
+ *
+ * @param[in] numstr            Converted string of the number.
+ * @param[in] nump              Pointer to the number.
+ * @param[in] radix             The radix to be converted to.
+ * @param[in] precision_width   Specify the precision width.
+
+ * @return Length of the converted string.
+ */
+static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width);
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*!
+*
+ */
+double modf(double input_dbl, double *intpart_ptr);
+
+/*************Code for process formatted data*******************************/
+
+static uint32_t ScanIgnoreWhiteSpace(const char **s)
+{
+    uint8_t count = 0;
+    uint8_t c;
+
+    c = **s;
+    while ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f'))
+    {
+        count++;
+        (*s)++;
+        c = **s;
+    }
+    return count;
+}
+
+static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps)
+{
+#if PRINTF_ADVANCED_ENABLE
+    int64_t a;
+    int64_t b;
+    int64_t c;
+
+    uint64_t ua;
+    uint64_t ub;
+    uint64_t uc;
+#else
+    int32_t a;
+    int32_t b;
+    int32_t c;
+
+    uint32_t ua;
+    uint32_t ub;
+    uint32_t uc;
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+    int32_t nlen;
+    char *nstrp;
+
+    nlen = 0;
+    nstrp = numstr;
+    *nstrp++ = '\0';
+
+    if (neg)
+    {
+#if PRINTF_ADVANCED_ENABLE
+        a = *(int64_t *)nump;
+#else
+        a = *(int32_t *)nump;
+#endif /* PRINTF_ADVANCED_ENABLE */
+        if (a == 0)
+        {
+            *nstrp = '0';
+            ++nlen;
+            return nlen;
+        }
+        while (a != 0)
+        {
+#if PRINTF_ADVANCED_ENABLE
+            b = (int64_t)a / (int64_t)radix;
+            c = (int64_t)a - ((int64_t)b * (int64_t)radix);
+            if (c < 0)
+            {
+                uc = (uint64_t)c;
+                c = (int64_t)(~uc) + 1 + '0';
+            }
+#else
+            b = a / radix;
+            c = a - (b * radix);
+            if (c < 0)
+            {
+                uc = (uint32_t)c;
+                c = (uint32_t)(~uc) + 1 + '0';
+            }
+#endif /* PRINTF_ADVANCED_ENABLE */
+            else
+            {
+                c = c + '0';
+            }
+            a = b;
+            *nstrp++ = (char)c;
+            ++nlen;
+        }
+    }
+    else
+    {
+#if PRINTF_ADVANCED_ENABLE
+        ua = *(uint64_t *)nump;
+#else
+        ua = *(uint32_t *)nump;
+#endif /* PRINTF_ADVANCED_ENABLE */
+        if (ua == 0)
+        {
+            *nstrp = '0';
+            ++nlen;
+            return nlen;
+        }
+        while (ua != 0)
+        {
+#if PRINTF_ADVANCED_ENABLE
+            ub = (uint64_t)ua / (uint64_t)radix;
+            uc = (uint64_t)ua - ((uint64_t)ub * (uint64_t)radix);
+#else
+            ub = ua / (uint32_t)radix;
+            uc = ua - (ub * (uint32_t)radix);
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+            if (uc < 10)
+            {
+                uc = uc + '0';
+            }
+            else
+            {
+                uc = uc - 10 + (use_caps ? 'A' : 'a');
+            }
+            ua = ub;
+            *nstrp++ = (char)uc;
+            ++nlen;
+        }
+    }
+    return nlen;
+}
+
+#if PRINTF_FLOAT_ENABLE
+static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width)
+{
+    int32_t a;
+    int32_t b;
+    int32_t c;
+    int32_t i;
+    uint32_t uc;
+    double fa;
+    double dc;
+    double fb;
+    double r;
+    double fractpart;
+    double intpart;
+
+    int32_t nlen;
+    char *nstrp;
+    nlen = 0;
+    nstrp = numstr;
+    *nstrp++ = '\0';
+    r = *(double *)nump;
+    if (!r)
+    {
+        *nstrp = '0';
+        ++nlen;
+        return nlen;
+    }
+    fractpart = modf((double)r, (double *)&intpart);
+    /* Process fractional part. */
+    for (i = 0; i < precision_width; i++)
+    {
+        fractpart *= radix;
+    }
+    if (r >= 0)
+    {
+        fa = fractpart + (double)0.5;
+        if (fa >= pow(10, precision_width))
+        {
+            intpart++;
+        }
+    }
+    else
+    {
+        fa = fractpart - (double)0.5;
+        if (fa <= -pow(10, precision_width))
+        {
+            intpart--;
+        }
+    }
+    for (i = 0; i < precision_width; i++)
+    {
+        fb = fa / (int32_t)radix;
+        dc = (fa - (int64_t)fb * (int32_t)radix);
+        c = (int32_t)dc;
+        if (c < 0)
+        {
+            uc = (uint32_t)c;
+            c = (int32_t)(~uc) + 1 + '0';
+        }
+        else
+        {
+            c = c + '0';
+        }
+        fa = fb;
+        *nstrp++ = (char)c;
+        ++nlen;
+    }
+    *nstrp++ = (char)'.';
+    ++nlen;
+    a = (int32_t)intpart;
+    if (a == 0)
+    {
+        *nstrp++ = '0';
+        ++nlen;
+    }
+    else
+    {
+        while (a != 0)
+        {
+            b = (int32_t)a / (int32_t)radix;
+            c = (int32_t)a - ((int32_t)b * (int32_t)radix);
+            if (c < 0)
+            {
+                uc = (uint32_t)c;
+                c = (int32_t)(~uc) + 1 + '0';
+            }
+            else
+            {
+                c = c + '0';
+            }
+            a = b;
+            *nstrp++ = (char)c;
+            ++nlen;
+        }
+    }
+    return nlen;
+}
+#endif /* PRINTF_FLOAT_ENABLE */
+
+int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb)
+{
+    /* va_list ap; */
+    char *p;
+    int32_t c;
+
+    char vstr[33];
+    char *vstrp = NULL;
+    int32_t vlen = 0;
+
+    int32_t done;
+    int32_t count = 0;
+
+    uint32_t field_width;
+    uint32_t precision_width;
+    char *sval;
+    int32_t cval;
+    bool use_caps;
+    uint8_t radix = 0;
+
+#if PRINTF_ADVANCED_ENABLE
+    uint32_t flags_used;
+    int32_t schar, dschar;
+    int64_t ival;
+    uint64_t uval = 0;
+    bool valid_precision_width;
+#else
+    int32_t ival;
+    uint32_t uval = 0;
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+#if PRINTF_FLOAT_ENABLE
+    double fval;
+#endif /* PRINTF_FLOAT_ENABLE */
+
+    /* Start parsing apart the format string and display appropriate formats and data. */
+    for (p = (char *)fmt; (c = *p) != 0; p++)
+    {
+        /*
+         * All formats begin with a '%' marker.  Special chars like
+         * '\n' or '\t' are normally converted to the appropriate
+         * character by the __compiler__.  Thus, no need for this
+         * routine to account for the '\' character.
+         */
+        if (c != '%')
+        {
+            cb(buf, &count, c, 1);
+            /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */
+            continue;
+        }
+
+        use_caps = true;
+
+#if PRINTF_ADVANCED_ENABLE
+        /* First check for specification modifier flags. */
+        flags_used = 0;
+        done = false;
+        while (!done)
+        {
+            switch (*++p)
+            {
+                case '-':
+                    flags_used |= kPRINTF_Minus;
+                    break;
+                case '+':
+                    flags_used |= kPRINTF_Plus;
+                    break;
+                case ' ':
+                    flags_used |= kPRINTF_Space;
+                    break;
+                case '0':
+                    flags_used |= kPRINTF_Zero;
+                    break;
+                case '#':
+                    flags_used |= kPRINTF_Pound;
+                    break;
+                default:
+                    /* We've gone one char too far. */
+                    --p;
+                    done = true;
+                    break;
+            }
+        }
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+        /* Next check for minimum field width. */
+        field_width = 0;
+        done = false;
+        while (!done)
+        {
+            c = *++p;
+            if ((c >= '0') && (c <= '9'))
+            {
+                field_width = (field_width * 10) + (c - '0');
+            }
+#if PRINTF_ADVANCED_ENABLE
+            else if (c == '*')
+            {
+                field_width = (uint32_t)va_arg(ap, uint32_t);
+            }
+#endif /* PRINTF_ADVANCED_ENABLE */
+            else
+            {
+                /* We've gone one char too far. */
+                --p;
+                done = true;
+            }
+        }
+        /* Next check for the width and precision field separator. */
+        precision_width = 6;
+#if PRINTF_ADVANCED_ENABLE
+        valid_precision_width = false;
+#endif /* PRINTF_ADVANCED_ENABLE */
+        if (*++p == '.')
+        {
+            /* Must get precision field width, if present. */
+            precision_width = 0;
+            done = false;
+            while (!done)
+            {
+                c = *++p;
+                if ((c >= '0') && (c <= '9'))
+                {
+                    precision_width = (precision_width * 10) + (c - '0');
+#if PRINTF_ADVANCED_ENABLE
+                    valid_precision_width = true;
+#endif /* PRINTF_ADVANCED_ENABLE */
+                }
+#if PRINTF_ADVANCED_ENABLE
+                else if (c == '*')
+                {
+                    precision_width = (uint32_t)va_arg(ap, uint32_t);
+                    valid_precision_width = true;
+                }
+#endif /* PRINTF_ADVANCED_ENABLE */
+                else
+                {
+                    /* We've gone one char too far. */
+                    --p;
+                    done = true;
+                }
+            }
+        }
+        else
+        {
+            /* We've gone one char too far. */
+            --p;
+        }
+#if PRINTF_ADVANCED_ENABLE
+        /*
+         * Check for the length modifier.
+         */
+        switch (/* c = */ *++p)
+        {
+            case 'h':
+                if (*++p != 'h')
+                {
+                    flags_used |= kPRINTF_LengthShortInt;
+                    --p;
+                }
+                else
+                {
+                    flags_used |= kPRINTF_LengthChar;
+                }
+                break;
+            case 'l':
+                if (*++p != 'l')
+                {
+                    flags_used |= kPRINTF_LengthLongInt;
+                    --p;
+                }
+                else
+                {
+                    flags_used |= kPRINTF_LengthLongLongInt;
+                }
+                break;
+            default:
+                /* we've gone one char too far */
+                --p;
+                break;
+        }
+#endif /* PRINTF_ADVANCED_ENABLE */
+        /* Now we're ready to examine the format. */
+        c = *++p;
+        {
+            if ((c == 'd') || (c == 'i') || (c == 'f') || (c == 'F') || (c == 'x') || (c == 'X') || (c == 'o') ||
+                (c == 'b') || (c == 'p') || (c == 'u'))
+            {
+                if ((c == 'd') || (c == 'i'))
+                {
+#if PRINTF_ADVANCED_ENABLE
+                    if (flags_used & kPRINTF_LengthLongLongInt)
+                    {
+                        ival = (int64_t)va_arg(ap, int64_t);
+                    }
+                    else
+#endif /* PRINTF_ADVANCED_ENABLE */
+                    {
+                        ival = (int32_t)va_arg(ap, int32_t);
+                    }
+                    vlen = ConvertRadixNumToString(vstr, &ival, true, 10, use_caps);
+                    vstrp = &vstr[vlen];
+#if PRINTF_ADVANCED_ENABLE
+                    if (ival < 0)
+                    {
+                        schar = '-';
+                        ++vlen;
+                    }
+                    else
+                    {
+                        if (flags_used & kPRINTF_Plus)
+                        {
+                            schar = '+';
+                            ++vlen;
+                        }
+                        else
+                        {
+                            if (flags_used & kPRINTF_Space)
+                            {
+                                schar = ' ';
+                                ++vlen;
+                            }
+                            else
+                            {
+                                schar = 0;
+                            }
+                        }
+                    }
+                    dschar = false;
+                    /* Do the ZERO pad. */
+                    if (flags_used & kPRINTF_Zero)
+                    {
+                        if (schar)
+                        {
+                            cb(buf, &count, schar, 1);
+                        }
+                        dschar = true;
+
+                        cb(buf, &count, '0', field_width - vlen);
+                        vlen = field_width;
+                    }
+                    else
+                    {
+                        if (!(flags_used & kPRINTF_Minus))
+                        {
+                            cb(buf, &count, ' ', field_width - vlen);
+                            if (schar)
+                            {
+                                cb(buf, &count, schar, 1);
+                            }
+                            dschar = true;
+                        }
+                    }
+                    /* The string was built in reverse order, now display in correct order. */
+                    if ((!dschar) && schar)
+                    {
+                        cb(buf, &count, schar, 1);
+                    }
+#endif /* PRINTF_ADVANCED_ENABLE */
+                }
+
+#if PRINTF_FLOAT_ENABLE
+                if ((c == 'f') || (c == 'F'))
+                {
+                    fval = (double)va_arg(ap, double);
+                    vlen = ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width);
+                    vstrp = &vstr[vlen];
+
+#if PRINTF_ADVANCED_ENABLE
+                    if (fval < 0)
+                    {
+                        schar = '-';
+                        ++vlen;
+                    }
+                    else
+                    {
+                        if (flags_used & kPRINTF_Plus)
+                        {
+                            schar = '+';
+                            ++vlen;
+                        }
+                        else
+                        {
+                            if (flags_used & kPRINTF_Space)
+                            {
+                                schar = ' ';
+                                ++vlen;
+                            }
+                            else
+                            {
+                                schar = 0;
+                            }
+                        }
+                    }
+                    dschar = false;
+                    if (flags_used & kPRINTF_Zero)
+                    {
+                        if (schar)
+                        {
+                            cb(buf, &count, schar, 1);
+                        }
+                        dschar = true;
+                        cb(buf, &count, '0', field_width - vlen);
+                        vlen = field_width;
+                    }
+                    else
+                    {
+                        if (!(flags_used & kPRINTF_Minus))
+                        {
+                            cb(buf, &count, ' ', field_width - vlen);
+                            if (schar)
+                            {
+                                cb(buf, &count, schar, 1);
+                            }
+                            dschar = true;
+                        }
+                    }
+                    if ((!dschar) && schar)
+                    {
+                        cb(buf, &count, schar, 1);
+                    }
+#endif /* PRINTF_ADVANCED_ENABLE */
+                }
+#endif /* PRINTF_FLOAT_ENABLE */
+                if ((c == 'X') || (c == 'x'))
+                {
+                    if (c == 'x')
+                    {
+                        use_caps = false;
+                    }
+#if PRINTF_ADVANCED_ENABLE
+                    if (flags_used & kPRINTF_LengthLongLongInt)
+                    {
+                        uval = (uint64_t)va_arg(ap, uint64_t);
+                    }
+                    else
+#endif /* PRINTF_ADVANCED_ENABLE */
+                    {
+                        uval = (uint32_t)va_arg(ap, uint32_t);
+                    }
+                    vlen = ConvertRadixNumToString(vstr, &uval, false, 16, use_caps);
+                    vstrp = &vstr[vlen];
+
+#if PRINTF_ADVANCED_ENABLE
+                    dschar = false;
+                    if (flags_used & kPRINTF_Zero)
+                    {
+                        if (flags_used & kPRINTF_Pound)
+                        {
+                            cb(buf, &count, '0', 1);
+                            cb(buf, &count, (use_caps ? 'X' : 'x'), 1);
+                            dschar = true;
+                        }
+                        cb(buf, &count, '0', field_width - vlen);
+                        vlen = field_width;
+                    }
+                    else
+                    {
+                        if (!(flags_used & kPRINTF_Minus))
+                        {
+                            if (flags_used & kPRINTF_Pound)
+                            {
+                                vlen += 2;
+                            }
+                            cb(buf, &count, ' ', field_width - vlen);
+                            if (flags_used & kPRINTF_Pound)
+                            {
+                                cb(buf, &count, '0', 1);
+                                cb(buf, &count, (use_caps ? 'X' : 'x'), 1);
+                                dschar = true;
+                            }
+                        }
+                    }
+
+                    if ((flags_used & kPRINTF_Pound) && (!dschar))
+                    {
+                        cb(buf, &count, '0', 1);
+                        cb(buf, &count, (use_caps ? 'X' : 'x'), 1);
+                        vlen += 2;
+                    }
+#endif /* PRINTF_ADVANCED_ENABLE */
+                }
+                if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u'))
+                {
+#if PRINTF_ADVANCED_ENABLE
+                    if (flags_used & kPRINTF_LengthLongLongInt)
+                    {
+                        uval = (uint64_t)va_arg(ap, uint64_t);
+                    }
+                    else
+#endif /* PRINTF_ADVANCED_ENABLE */
+                    {
+                        uval = (uint32_t)va_arg(ap, uint32_t);
+                    }
+                    switch (c)
+                    {
+                        case 'o':
+                            radix = 8;
+                            break;
+                        case 'b':
+                            radix = 2;
+                            break;
+                        case 'p':
+                            radix = 16;
+                            break;
+                        case 'u':
+                            radix = 10;
+                            break;
+                        default:
+                            break;
+                    }
+                    vlen = ConvertRadixNumToString(vstr, &uval, false, radix, use_caps);
+                    vstrp = &vstr[vlen];
+#if PRINTF_ADVANCED_ENABLE
+                    if (flags_used & kPRINTF_Zero)
+                    {
+                        cb(buf, &count, '0', field_width - vlen);
+                        vlen = field_width;
+                    }
+                    else
+                    {
+                        if (!(flags_used & kPRINTF_Minus))
+                        {
+                            cb(buf, &count, ' ', field_width - vlen);
+                        }
+                    }
+#endif /* PRINTF_ADVANCED_ENABLE */
+                }
+#if !PRINTF_ADVANCED_ENABLE
+                cb(buf, &count, ' ', field_width - vlen);
+#endif /* !PRINTF_ADVANCED_ENABLE */
+                if (vstrp != NULL)
+                {
+                    while (*vstrp)
+                    {
+                        cb(buf, &count, *vstrp--, 1);
+                    }
+                }
+#if PRINTF_ADVANCED_ENABLE
+                if (flags_used & kPRINTF_Minus)
+                {
+                    cb(buf, &count, ' ', field_width - vlen);
+                }
+#endif /* PRINTF_ADVANCED_ENABLE */
+            }
+            else if (c == 'c')
+            {
+                cval = (char)va_arg(ap, uint32_t);
+                cb(buf, &count, cval, 1);
+            }
+            else if (c == 's')
+            {
+                sval = (char *)va_arg(ap, char *);
+                if (sval)
+                {
+#if PRINTF_ADVANCED_ENABLE
+                    if (valid_precision_width)
+                    {
+                        vlen = precision_width;
+                    }
+                    else
+                    {
+                        vlen = strlen(sval);
+                    }
+#else
+                    vlen = strlen(sval);
+#endif /* PRINTF_ADVANCED_ENABLE */
+#if PRINTF_ADVANCED_ENABLE
+                    if (!(flags_used & kPRINTF_Minus))
+#endif /* PRINTF_ADVANCED_ENABLE */
+                    {
+                        cb(buf, &count, ' ', field_width - vlen);
+                    }
+
+#if PRINTF_ADVANCED_ENABLE
+                    if (valid_precision_width)
+                    {
+                        while ((*sval) && (vlen > 0))
+                        {
+                            cb(buf, &count, *sval++, 1);
+                            vlen--;
+                        }
+                        /* In case that vlen sval is shorter than vlen */
+                        vlen = precision_width - vlen;
+                    }
+                    else
+                    {
+#endif /* PRINTF_ADVANCED_ENABLE */
+                        while (*sval)
+                        {
+                            cb(buf, &count, *sval++, 1);
+                        }
+#if PRINTF_ADVANCED_ENABLE
+                    }
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+#if PRINTF_ADVANCED_ENABLE
+                    if (flags_used & kPRINTF_Minus)
+                    {
+                        cb(buf, &count, ' ', field_width - vlen);
+                    }
+#endif /* PRINTF_ADVANCED_ENABLE */
+                }
+            }
+            else
+            {
+                cb(buf, &count, c, 1);
+            }
+        }
+    }
+
+    return count;
+}
+
+int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr)
+{
+    uint8_t base;
+    int8_t neg;
+    /* Identifier for the format string. */
+    char *c = format;
+    char temp;
+    char *buf;
+    /* Flag telling the conversion specification. */
+    uint32_t flag = 0;
+    /* Filed width for the matching input streams. */
+    uint32_t field_width;
+    /* How many arguments are assigned except the suppress. */
+    uint32_t nassigned = 0;
+    /* How many characters are read from the input streams. */
+    uint32_t n_decode = 0;
+
+    int32_t val;
+
+    const char *s;
+    /* Identifier for the input string. */
+    const char *p = line_ptr;
+
+    /* Return EOF error before any conversion. */
+    if (*p == '\0')
+    {
+        return -1;
+    }
+
+    /* Decode directives. */
+    while ((*c) && (*p))
+    {
+        /* Ignore all white-spaces in the format strings. */
+        if (ScanIgnoreWhiteSpace((const char **)&c))
+        {
+            n_decode += ScanIgnoreWhiteSpace(&p);
+        }
+        else if ((*c != '%') || ((*c == '%') && (*(c + 1) == '%')))
+        {
+            /* Ordinary characters. */
+            c++;
+            if (*p == *c)
+            {
+                n_decode++;
+                p++;
+                c++;
+            }
+            else
+            {
+                /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream.
+                 * However, it is deserted now. */
+                break;
+            }
+        }
+        else
+        {
+            /* convernsion specification */
+            c++;
+            /* Reset. */
+            flag = 0;
+            field_width = 0;
+            base = 0;
+
+            /* Loop to get full conversion specification. */
+            while ((*c) && (!(flag & kSCANF_DestMask)))
+            {
+                switch (*c)
+                {
+#if SCANF_ADVANCED_ENABLE
+                    case '*':
+                        if (flag & kSCANF_Suppress)
+                        {
+                            /* Match failure. */
+                            return nassigned;
+                        }
+                        flag |= kSCANF_Suppress;
+                        c++;
+                        break;
+                    case 'h':
+                        if (flag & kSCANF_LengthMask)
+                        {
+                            /* Match failure. */
+                            return nassigned;
+                        }
+
+                        if (c[1] == 'h')
+                        {
+                            flag |= kSCANF_LengthChar;
+                            c++;
+                        }
+                        else
+                        {
+                            flag |= kSCANF_LengthShortInt;
+                        }
+                        c++;
+                        break;
+                    case 'l':
+                        if (flag & kSCANF_LengthMask)
+                        {
+                            /* Match failure. */
+                            return nassigned;
+                        }
+
+                        if (c[1] == 'l')
+                        {
+                            flag |= kSCANF_LengthLongLongInt;
+                            c++;
+                        }
+                        else
+                        {
+                            flag |= kSCANF_LengthLongInt;
+                        }
+                        c++;
+                        break;
+#endif /* SCANF_ADVANCED_ENABLE */
+#if SCANF_FLOAT_ENABLE
+                    case 'L':
+                        if (flag & kSCANF_LengthMask)
+                        {
+                            /* Match failure. */
+                            return nassigned;
+                        }
+                        flag |= kSCANF_LengthLongLongDouble;
+                        c++;
+                        break;
+#endif /* SCANF_FLOAT_ENABLE */
+                    case '0':
+                    case '1':
+                    case '2':
+                    case '3':
+                    case '4':
+                    case '5':
+                    case '6':
+                    case '7':
+                    case '8':
+                    case '9':
+                        if (field_width)
+                        {
+                            /* Match failure. */
+                            return nassigned;
+                        }
+                        do
+                        {
+                            field_width = field_width * 10 + *c - '0';
+                            c++;
+                        } while ((*c >= '0') && (*c <= '9'));
+                        break;
+                    case 'd':
+                        base = 10;
+                        flag |= kSCANF_TypeSinged;
+                        flag |= kSCANF_DestInt;
+                        c++;
+                        break;
+                    case 'u':
+                        base = 10;
+                        flag |= kSCANF_DestInt;
+                        c++;
+                        break;
+                    case 'o':
+                        base = 8;
+                        flag |= kSCANF_DestInt;
+                        c++;
+                        break;
+                    case 'x':
+                    case 'X':
+                        base = 16;
+                        flag |= kSCANF_DestInt;
+                        c++;
+                        break;
+                    case 'i':
+                        base = 0;
+                        flag |= kSCANF_DestInt;
+                        c++;
+                        break;
+#if SCANF_FLOAT_ENABLE
+                    case 'a':
+                    case 'A':
+                    case 'e':
+                    case 'E':
+                    case 'f':
+                    case 'F':
+                    case 'g':
+                    case 'G':
+                        flag |= kSCANF_DestFloat;
+                        c++;
+                        break;
+#endif /* SCANF_FLOAT_ENABLE */
+                    case 'c':
+                        flag |= kSCANF_DestChar;
+                        if (!field_width)
+                        {
+                            field_width = 1;
+                        }
+                        c++;
+                        break;
+                    case 's':
+                        flag |= kSCANF_DestString;
+                        c++;
+                        break;
+                    default:
+                        return nassigned;
+                }
+            }
+
+            if (!(flag & kSCANF_DestMask))
+            {
+                /* Format strings are exhausted. */
+                return nassigned;
+            }
+
+            if (!field_width)
+            {
+                /* Large than length of a line. */
+                field_width = 99;
+            }
+
+            /* Matching strings in input streams and assign to argument. */
+            switch (flag & kSCANF_DestMask)
+            {
+                case kSCANF_DestChar:
+                    s = (const char *)p;
+                    buf = va_arg(args_ptr, char *);
+                    while ((field_width--) && (*p))
+                    {
+                        if (!(flag & kSCANF_Suppress))
+                        {
+                            *buf++ = *p++;
+                        }
+                        else
+                        {
+                            p++;
+                        }
+                        n_decode++;
+                    }
+
+                    if ((!(flag & kSCANF_Suppress)) && (s != p))
+                    {
+                        nassigned++;
+                    }
+                    break;
+                case kSCANF_DestString:
+                    n_decode += ScanIgnoreWhiteSpace(&p);
+                    s = p;
+                    buf = va_arg(args_ptr, char *);
+                    while ((field_width--) && (*p != '\0') && (*p != ' ') && (*p != '\t') && (*p != '\n') &&
+                           (*p != '\r') && (*p != '\v') && (*p != '\f'))
+                    {
+                        if (flag & kSCANF_Suppress)
+                        {
+                            p++;
+                        }
+                        else
+                        {
+                            *buf++ = *p++;
+                        }
+                        n_decode++;
+                    }
+
+                    if ((!(flag & kSCANF_Suppress)) && (s != p))
+                    {
+                        /* Add NULL to end of string. */
+                        *buf = '\0';
+                        nassigned++;
+                    }
+                    break;
+                case kSCANF_DestInt:
+                    n_decode += ScanIgnoreWhiteSpace(&p);
+                    s = p;
+                    val = 0;
+                    if ((base == 0) || (base == 16))
+                    {
+                        if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X')))
+                        {
+                            base = 16;
+                            if (field_width >= 1)
+                            {
+                                p += 2;
+                                n_decode += 2;
+                                field_width -= 2;
+                            }
+                        }
+                    }
+
+                    if (base == 0)
+                    {
+                        if (s[0] == '0')
+                        {
+                            base = 8;
+                        }
+                        else
+                        {
+                            base = 10;
+                        }
+                    }
+
+                    neg = 1;
+                    switch (*p)
+                    {
+                        case '-':
+                            neg = -1;
+                            n_decode++;
+                            p++;
+                            field_width--;
+                            break;
+                        case '+':
+                            neg = 1;
+                            n_decode++;
+                            p++;
+                            field_width--;
+                            break;
+                        default:
+                            break;
+                    }
+
+                    while ((*p) && (field_width--))
+                    {
+                        if ((*p <= '9') && (*p >= '0'))
+                        {
+                            temp = *p - '0';
+                        }
+                        else if ((*p <= 'f') && (*p >= 'a'))
+                        {
+                            temp = *p - 'a' + 10;
+                        }
+                        else if ((*p <= 'F') && (*p >= 'A'))
+                        {
+                            temp = *p - 'A' + 10;
+                        }
+                        else
+                        {
+                            temp = base;
+                        }
+
+                        if (temp >= base)
+                        {
+                            break;
+                        }
+                        else
+                        {
+                            val = base * val + temp;
+                        }
+                        p++;
+                        n_decode++;
+                    }
+                    val *= neg;
+                    if (!(flag & kSCANF_Suppress))
+                    {
+#if SCANF_ADVANCED_ENABLE
+                        switch (flag & kSCANF_LengthMask)
+                        {
+                            case kSCANF_LengthChar:
+                                if (flag & kSCANF_TypeSinged)
+                                {
+                                    *va_arg(args_ptr, signed char *) = (signed char)val;
+                                }
+                                else
+                                {
+                                    *va_arg(args_ptr, unsigned char *) = (unsigned char)val;
+                                }
+                                break;
+                            case kSCANF_LengthShortInt:
+                                if (flag & kSCANF_TypeSinged)
+                                {
+                                    *va_arg(args_ptr, signed short *) = (signed short)val;
+                                }
+                                else
+                                {
+                                    *va_arg(args_ptr, unsigned short *) = (unsigned short)val;
+                                }
+                                break;
+                            case kSCANF_LengthLongInt:
+                                if (flag & kSCANF_TypeSinged)
+                                {
+                                    *va_arg(args_ptr, signed long int *) = (signed long int)val;
+                                }
+                                else
+                                {
+                                    *va_arg(args_ptr, unsigned long int *) = (unsigned long int)val;
+                                }
+                                break;
+                            case kSCANF_LengthLongLongInt:
+                                if (flag & kSCANF_TypeSinged)
+                                {
+                                    *va_arg(args_ptr, signed long long int *) = (signed long long int)val;
+                                }
+                                else
+                                {
+                                    *va_arg(args_ptr, unsigned long long int *) = (unsigned long long int)val;
+                                }
+                                break;
+                            default:
+                                /* The default type is the type int. */
+                                if (flag & kSCANF_TypeSinged)
+                                {
+                                    *va_arg(args_ptr, signed int *) = (signed int)val;
+                                }
+                                else
+                                {
+                                    *va_arg(args_ptr, unsigned int *) = (unsigned int)val;
+                                }
+                                break;
+                        }
+#else
+                        /* The default type is the type int. */
+                        if (flag & kSCANF_TypeSinged)
+                        {
+                            *va_arg(args_ptr, signed int *) = (signed int)val;
+                        }
+                        else
+                        {
+                            *va_arg(args_ptr, unsigned int *) = (unsigned int)val;
+                        }
+#endif /* SCANF_ADVANCED_ENABLE */
+                        nassigned++;
+                    }
+                    break;
+#if SCANF_FLOAT_ENABLE
+                case kSCANF_DestFloat:
+                    n_decode += ScanIgnoreWhiteSpace(&p);
+                    fnum = strtod(p, (char **)&s);
+
+                    if ((fnum >= HUGE_VAL) || (fnum <= -HUGE_VAL))
+                    {
+                        break;
+                    }
+
+                    n_decode += (int)(s) - (int)(p);
+                    p = s;
+                    if (!(flag & kSCANF_Suppress))
+                    {
+                        if (flag & kSCANF_LengthLongLongDouble)
+                        {
+                            *va_arg(args_ptr, double *) = fnum;
+                        }
+                        else
+                        {
+                            *va_arg(args_ptr, float *) = (float)fnum;
+                        }
+                        nassigned++;
+                    }
+                    break;
+#endif /* SCANF_FLOAT_ENABLE */
+                default:
+                    return nassigned;
+            }
+        }
+    }
+    return nassigned;
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_str.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_str.h
new file mode 100644
index 0000000..a0c40c5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_str.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FSL_STR_H
+#define _FSL_STR_H
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @brief A function pointer which is used when format printf log.
+ */
+typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len);
+
+/*!
+ * @brief This function outputs its parameters according to a formatted string.
+ *
+ * @note I/O is performed by calling given function pointer using following
+ * (*func_ptr)(c);
+ *
+ * @param[in] fmt_ptr   Format string for printf.
+ * @param[in] args_ptr  Arguments to printf.
+ * @param[in] buf  pointer to the buffer
+ * @param cb print callbck function pointer
+ *
+ * @return Number of characters to be print
+ */
+int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb);
+
+/*!
+ * @brief Converts an input line of ASCII characters based upon a provided
+ * string format.
+ *
+ * @param[in] line_ptr The input line of ASCII data.
+ * @param[in] format   Format first points to the format string.
+ * @param[in] args_ptr The list of parameters.
+ *
+ * @return Number of input items converted and assigned.
+ * @retval IO_EOF When line_ptr is empty string "".
+ */
+int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _FSL_STR_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/.cproject b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/.cproject
new file mode 100644
index 0000000..54955b3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/.cproject
@@ -0,0 +1,219 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+					
+						
+					
+					
+						
+					
+				
+			
+			
+			
+		
+	
+	
+		
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+	
+	
+		
+			
+		
+		
+			
+		
+	
+	
+	
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/.project b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/.project
new file mode 100644
index 0000000..7cd3f63
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/.project
@@ -0,0 +1,434 @@
+
+
+	RTOSDemo_ri5cy
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		org.eclipse.cdt.core.cnature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			FreeRTOS_Source
+			2
+			FREERTOS_ROOT/FreeRTOS/Source
+		
+		
+			FreeRTOS_startup_RV32M1_ri5cy.S
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/gcc/startup_RV32M1_ri5cy.S
+		
+		
+			common
+			2
+			virtual:/virtual
+		
+		
+			common/pin_mux.c
+			1
+			PARENT-2-PROJECT_LOC/common/pin_mux.c
+		
+		
+			common/pin_mux.h
+			1
+			PARENT-2-PROJECT_LOC/common/pin_mux.h
+		
+		
+			common/rv32m1_ri5cy.cfg
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_ri5cy.cfg
+		
+		
+			common/rv32m1_sdk_riscv
+			2
+			virtual:/virtual
+		
+		
+			full_demo/common_demo_files
+			2
+			virtual:/virtual
+		
+		
+			common/rv32m1_sdk_riscv/RISCV
+			2
+			virtual:/virtual
+		
+		
+			common/rv32m1_sdk_riscv/board
+			2
+			virtual:/virtual
+		
+		
+			common/rv32m1_sdk_riscv/devices
+			2
+			virtual:/virtual
+		
+		
+			full_demo/common_demo_files/AbortDelay.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/AbortDelay.c
+		
+		
+			full_demo/common_demo_files/EventGroupsDemo.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/EventGroupsDemo.c
+		
+		
+			full_demo/common_demo_files/GenQTest.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/GenQTest.c
+		
+		
+			full_demo/common_demo_files/MessageBufferDemo.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/MessageBufferDemo.c
+		
+		
+			full_demo/common_demo_files/StreamBufferDemo.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/StreamBufferDemo.c
+		
+		
+			full_demo/common_demo_files/StreamBufferInterrupt.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/StreamBufferInterrupt.c
+		
+		
+			full_demo/common_demo_files/TaskNotify.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/TaskNotify.c
+		
+		
+			full_demo/common_demo_files/TimerDemo.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/TimerDemo.c
+		
+		
+			full_demo/common_demo_files/blocktim.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/blocktim.c
+		
+		
+			full_demo/common_demo_files/countsem.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/countsem.c
+		
+		
+			full_demo/common_demo_files/death.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/death.c
+		
+		
+			full_demo/common_demo_files/dynamic.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/dynamic.c
+		
+		
+			full_demo/common_demo_files/include
+			2
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/include
+		
+		
+			full_demo/common_demo_files/recmutex.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/recmutex.c
+		
+		
+			common/rv32m1_sdk_riscv/RISCV/core_riscv32.h
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/RISCV/core_riscv32.h
+		
+		
+			common/rv32m1_sdk_riscv/board/board.c
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/board/board.c
+		
+		
+			common/rv32m1_sdk_riscv/board/board.h
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/board/board.h
+		
+		
+			common/rv32m1_sdk_riscv/board/clock_config.c
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/board/clock_config.c
+		
+		
+			common/rv32m1_sdk_riscv/board/clock_config.h
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/board/clock_config.h
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1
+			2
+			virtual:/virtual
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/RV32M1_ri5cy.h
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/RV32M1_ri5cy.h
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/RV32M1_ri5cy_features.h
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/RV32M1_ri5cy_features.h
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/drivers
+			2
+			virtual:/virtual
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/fsl_device_registers.h
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/fsl_device_registers.h
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_ri5cy.c
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_ri5cy.c
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_ri5cy.h
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_ri5cy.h
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/utilities
+			2
+			virtual:/virtual
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_clock.c
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_clock.c
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_clock.h
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_clock.h
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_common.c
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_common.c
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_common.h
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_common.h
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_gpio.c
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_gpio.c
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_gpio.h
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_gpio.h
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart.c
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart.c
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart.h
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart.h
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_msmc.c
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_msmc.c
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_msmc.h
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_msmc.h
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_port.h
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_port.h
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_debug_console.c
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_debug_console.c
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_debug_console.h
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_debug_console.h
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_debug_console_conf.h
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_debug_console_conf.h
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_io.c
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_io.c
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_io.h
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_io.h
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_log.c
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_log.c
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_log.h
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_log.h
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_str.c
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_str.c
+		
+		
+			common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_str.h
+			1
+			PARENT-2-PROJECT_LOC/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_str.h
+		
+	
+	
+		
+			1544746783235
+			FreeRTOS_Source
+			5
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-event_groups.c
+			
+		
+		
+			1544746783242
+			FreeRTOS_Source
+			5
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-list.c
+			
+		
+		
+			1544746783249
+			FreeRTOS_Source
+			5
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-queue.c
+			
+		
+		
+			1544746783255
+			FreeRTOS_Source
+			5
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-stream_buffer.c
+			
+		
+		
+			1544746783260
+			FreeRTOS_Source
+			5
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-tasks.c
+			
+		
+		
+			1544746783266
+			FreeRTOS_Source
+			5
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-timers.c
+			
+		
+		
+			1544746838986
+			FreeRTOS_Source/portable
+			9
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-GCC
+			
+		
+		
+			1544746838993
+			FreeRTOS_Source/portable
+			9
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-MemMang
+			
+		
+		
+			1544746861827
+			FreeRTOS_Source/portable/GCC
+			9
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-RISC-V
+			
+		
+		
+			1544746990721
+			FreeRTOS_Source/portable/MemMang
+			5
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-heap_4.c
+			
+		
+		
+			1544746990726
+			FreeRTOS_Source/portable/MemMang
+			5
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-readme.*
+			
+		
+		
+			1546226557819
+			FreeRTOS_Source/portable/GCC/RISC-V/chip_specific_extensions
+			9
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-Pulpino_Vega_RV32M1RM
+			
+		
+	
+	
+		
+			FREERTOS_ROOT
+			$%7BPARENT-5-PROJECT_LOC%7D
+		
+	
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/.settings/language.settings.xml b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/.settings/language.settings.xml
new file mode 100644
index 0000000..2a6e54a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/.settings/language.settings.xml
@@ -0,0 +1,14 @@
+
+
+	
+		
+			
+			
+			
+			
+				
+				
+			
+		
+	
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/.settings/org.eclipse.cdt.managedbuilder.core.prefs
new file mode 100644
index 0000000..80003f3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,11 @@
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.2124579326/CPATH/delimiter=;
+environment/buildEnvironmentInclude/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.2124579326/CPATH/operation=remove
+environment/buildEnvironmentInclude/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.2124579326/C_INCLUDE_PATH/delimiter=;
+environment/buildEnvironmentInclude/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.2124579326/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.2124579326/append=true
+environment/buildEnvironmentInclude/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.2124579326/appendContributed=true
+environment/buildEnvironmentLibrary/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.2124579326/LIBRARY_PATH/delimiter=;
+environment/buildEnvironmentLibrary/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.2124579326/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentLibrary/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.2124579326/append=true
+environment/buildEnvironmentLibrary/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.2124579326/appendContributed=true
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/Demo Documentation.url b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/Demo Documentation.url
new file mode 100644
index 0000000..904bb01
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/Demo Documentation.url	
@@ -0,0 +1,5 @@
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,11
+[InternetShortcut]
+IDList=
+URL=https://freertos.org/RTOS-RISC-V-Vegaboard_Pulp.html
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/FreeRTOSConfig.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/FreeRTOSConfig.h
new file mode 100644
index 0000000..28859d5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/FreeRTOSConfig.h
@@ -0,0 +1,148 @@
+/*
+    FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include "clock_config.h"
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configCLINT_BASE_ADDRESS		0 /* There is no CLINT so the base address must be set to 0. */
+#define configUSE_PREEMPTION			1
+#define configUSE_IDLE_HOOK				1
+#define configUSE_TICK_HOOK				1
+#define configCPU_CLOCK_HZ				BOARD_BOOTCLOCKRUN_CORE_CLOCK
+#define configTICK_RATE_HZ				( ( TickType_t ) 1000 )
+#define configMAX_PRIORITIES			( 5 )
+#define configMINIMAL_STACK_SIZE		( ( unsigned short ) 200 ) /* Can be as low as 60 but some of the demo tasks that use this constant require it to be higher. */
+#define configTOTAL_HEAP_SIZE			( ( size_t ) ( 100 * 1024 ) )
+#define configMAX_TASK_NAME_LEN			( 16 )
+#define configUSE_TRACE_FACILITY		0
+#define configUSE_16_BIT_TICKS			0
+#define configIDLE_SHOULD_YIELD			0
+#define configUSE_MUTEXES				1
+#define configQUEUE_REGISTRY_SIZE		8
+#define configCHECK_FOR_STACK_OVERFLOW	2
+#define configUSE_RECURSIVE_MUTEXES		1
+#define configUSE_MALLOC_FAILED_HOOK	1
+#define configUSE_APPLICATION_TASK_TAG	0
+#define configUSE_COUNTING_SEMAPHORES	1
+#define configGENERATE_RUN_TIME_STATS	0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 			0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Software timer definitions. */
+#define configUSE_TIMERS				1
+#define configTIMER_TASK_PRIORITY		( configMAX_PRIORITIES - 1 )
+#define configTIMER_QUEUE_LENGTH		4
+#define configTIMER_TASK_STACK_DEPTH	( configMINIMAL_STACK_SIZE )
+
+/* Task priorities.  Allow these to be overridden. */
+#ifndef uartPRIMARY_PRIORITY
+	#define uartPRIMARY_PRIORITY		( configMAX_PRIORITIES - 3 )
+#endif
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet			1
+#define INCLUDE_uxTaskPriorityGet			1
+#define INCLUDE_vTaskDelete					1
+#define INCLUDE_vTaskCleanUpResources		1
+#define INCLUDE_vTaskSuspend				1
+#define INCLUDE_vTaskDelayUntil				1
+#define INCLUDE_vTaskDelay					1
+#define INCLUDE_eTaskGetState				1
+#define INCLUDE_xTimerPendFunctionCall		1
+#define INCLUDE_xTaskAbortDelay				1
+#define INCLUDE_xTaskGetHandle				1
+#define INCLUDE_xSemaphoreGetMutexHolder	1
+
+/* Normal assert() semantics without relying on the provision of an assert.h
+header file. */
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); __asm volatile( "ebreak" ); for( ;; ); }
+
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configKERNEL_INTERRUPT_PRIORITY 7
+
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/RTOSDemo_ri5cy.launch b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/RTOSDemo_ri5cy.launch
new file mode 100644
index 0000000..9e3ce58
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/RTOSDemo_ri5cy.launch
@@ -0,0 +1,61 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/RV32M1_ri5cy_flash.ld b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/RV32M1_ri5cy_flash.ld
new file mode 100644
index 0000000..95554cd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/RV32M1_ri5cy_flash.ld
@@ -0,0 +1,181 @@
+/*
+** ###################################################################
+**     Processors:          RV32M1_ri5cy
+**                          RV32M1_ri5cy
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
+**     Version:             rev. 1.0, 2018-10-02
+**     Build:               b171115
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
+**     All rights reserved.
+**     
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+OUTPUT_ARCH( "riscv" )
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_vector              (RX)  : ORIGIN = 0x000FFF00, LENGTH = 0x00000100
+  m_text                (RX)  : ORIGIN = 0x00000000, LENGTH = 0x000FFF00
+  m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000 - 0x1800
+  rpmsg_sh_mem          (RW)  : ORIGIN = 0x2002E800, LENGTH = 0x1800
+  m_usb_sram            (RW)  : ORIGIN = 0x48010000, LENGTH = 0x00000800
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* NOINIT section for rpmsg_sh_mem */
+  .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)
+  {
+     *(.noinit.$rpmsg_sh_mem*)
+     . = ALIGN(4) ;
+  } > rpmsg_sh_mem
+
+  .vectors : ALIGN(4)
+  {
+    __VECTOR_TABLE = .;
+    KEEP(*(.vectors))
+  } > m_vector
+
+
+  /* The program code and other data goes into internal flash */
+  .text :
+  {
+    . = ALIGN(4);
+    KEEP(*(.startup))
+    . = ALIGN(4);
+    __user_vector = .;
+    KEEP(*(user_vectors))
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.srodata .srodata.*)
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    *(.init)
+    *(.fini)
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __global_pointer = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    *(.sdata .sdata.*)
+    *(.heapsram*)            /* This is only for the pulpino official test code. */
+    __noncachedata_start__ = .;   /* create a global symbol at ncache data start */
+	*(NonCacheable)
+    __noncachedata_end__ = .;     /* define a global symbol at ncache data end */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  _edata = .;
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss*)
+    *(.sbss)
+    *(.sbss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  /* End of uninitalized data segement */
+  _end = .;
+  PROVIDE(end = .);
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __heap_start = .;
+    . += HEAP_SIZE;
+    __heap_end = .;
+    _heap_end = __heap_end;
+  } > m_data
+
+  .stack :
+  {
+    . = ALIGN(8);
+    __StackLimit = .;
+    . += STACK_SIZE;
+    __StackTop = .;
+    __freertos_irq_stack_top = .;
+  } > m_data
+
+  m_usb_bdt (NOLOAD) :
+  {
+    . = ALIGN(512);
+    *(m_usb_bdt)
+  } > m_usb_sram
+
+  m_usb_global (NOLOAD) :
+  {
+    *(m_usb_global)
+  } > m_usb_sram
+
+  /* Initializes stack on the end of block */
+  PROVIDE(__stack = __StackTop);
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/blinky_demo/main_blinky.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/blinky_demo/main_blinky.c
new file mode 100644
index 0000000..bfd6cfd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/blinky_demo/main_blinky.c
@@ -0,0 +1,206 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/******************************************************************************
+ * NOTE 1:  This project provides two demo applications.  A simple blinky
+ * style project, and a more comprehensive test and demo application.  The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
+ * between the two.  See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
+ * in main.c.  This file implements the simply blinky style version.
+ *
+ * NOTE 2:  This file only contains the source code that is specific to the
+ * basic demo.  Generic functions, such FreeRTOS hook functions, and functions
+ * required to configure the hardware are defined in main.c.
+ ******************************************************************************
+ *
+ * main_blinky() creates one queue, and two tasks.  It then starts the
+ * scheduler.
+ *
+ * The Queue Send Task:
+ * The queue send task is implemented by the prvQueueSendTask() function in
+ * this file.  prvQueueSendTask() sits in a loop that causes it to repeatedly
+ * block for 1000 milliseconds, before sending the value 100 to the queue that
+ * was created within main_blinky().  Once the value is sent, the task loops
+ * back around to block for another 1000 milliseconds...and so on.
+ *
+ * The Queue Receive Task:
+ * The queue receive task is implemented by the prvQueueReceiveTask() function
+ * in this file.  prvQueueReceiveTask() sits in a loop where it repeatedly
+ * blocks on attempts to read data from the queue that was created within
+ * main_blinky().  When data is received, the task checks the value of the
+ * data, and if the value equals the expected 100, writes 'Blink' to the UART
+ * (the UART is used in place of the LED to allow easy execution in QEMU).  The
+ * 'block time' parameter passed to the queue receive function specifies that
+ * the task should be held in the Blocked state indefinitely to wait for data to
+ * be available on the queue.  The queue receive task will only leave the
+ * Blocked state when the queue send task writes to the queue.  As the queue
+ * send task writes to the queue every 1000 milliseconds, the queue receive
+ * task leaves the Blocked state every 1000 milliseconds, and therefore toggles
+ * the LED every 200 milliseconds.
+ */
+
+/* Standard includes. */
+#include 
+#include 
+#include 
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* Priorities used by the tasks. */
+#define mainQUEUE_RECEIVE_TASK_PRIORITY		( tskIDLE_PRIORITY + 2 )
+#define	mainQUEUE_SEND_TASK_PRIORITY		( tskIDLE_PRIORITY + 1 )
+
+/* The rate at which data is sent to the queue.  The 200ms value is converted
+to ticks using the pdMS_TO_TICKS() macro. */
+#define mainQUEUE_SEND_FREQUENCY_MS			pdMS_TO_TICKS( 1000 )
+
+/* The maximum number items the queue can hold.  The priority of the receiving
+task is above the priority of the sending task, so the receiving task will
+preempt the sending task and remove the queue items each time the sending task
+writes to the queue.  Therefore the queue will never have more than one item in
+it at any time, and even with a queue length of 1, the sending task will never
+find the queue full. */
+#define mainQUEUE_LENGTH					( 1 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in
+ * main.c.
+ */
+void main_blinky( void );
+
+/*
+ * The tasks as described in the comments at the top of this file.
+ */
+static void prvQueueReceiveTask( void *pvParameters );
+static void prvQueueSendTask( void *pvParameters );
+
+/*-----------------------------------------------------------*/
+
+/* The queue used by both tasks. */
+static QueueHandle_t xQueue = NULL;
+
+/*-----------------------------------------------------------*/
+
+void main_blinky( void )
+{
+	/* Create the queue. */
+	xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );
+
+	if( xQueue != NULL )
+	{
+		/* Start the two tasks as described in the comments at the top of this
+		file. */
+		xTaskCreate( prvQueueReceiveTask,				/* The function that implements the task. */
+					"Rx", 								/* The text name assigned to the task - for debug only as it is not used by the kernel. */
+					configMINIMAL_STACK_SIZE * 2U, 		/* The size of the stack to allocate to the task. */
+					NULL, 								/* The parameter passed to the task - not used in this case. */
+					mainQUEUE_RECEIVE_TASK_PRIORITY, 	/* The priority assigned to the task. */
+					NULL );								/* The task handle is not required, so NULL is passed. */
+
+		xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE * 2U, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
+
+		/* Start the tasks and timer running. */
+		vTaskStartScheduler();
+	}
+
+	/* If all is well, the scheduler will now be running, and the following
+	line will never be reached.  If the following line does execute, then
+	there was insufficient FreeRTOS heap memory available for the Idle and/or
+	timer tasks to be created.  See the memory management section on the
+	FreeRTOS web site for more details on the FreeRTOS heap
+	http://www.freertos.org/a00111.html. */
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueSendTask( void *pvParameters )
+{
+TickType_t xNextWakeTime;
+const unsigned long ulValueToSend = 100UL;
+BaseType_t xReturned;
+
+	/* Remove compiler warning about unused parameter. */
+	( void ) pvParameters;
+
+	/* Initialise xNextWakeTime - this only needs to be done once. */
+	xNextWakeTime = xTaskGetTickCount();
+
+	for( ;; )
+	{
+		/* Place this task in the blocked state until it is time to run again. */
+		vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
+
+		/* Send to the queue - causing the queue receive task to unblock and
+		toggle the LED.  0 is used as the block time so the sending operation
+		will not block - it shouldn't need to block as the queue should always
+		be empty at this point in the code. */
+		xReturned = xQueueSend( xQueue, &ulValueToSend, 0U );
+		configASSERT( xReturned == pdPASS );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueReceiveTask( void *pvParameters )
+{
+unsigned long ulReceivedValue;
+const unsigned long ulExpectedValue = 100UL;
+const char * const pcPassMessage = "Blink\r\n";
+const char * const pcFailMessage = "Unexpected value received\r\n";
+extern void vSendString( const char * const pcString );
+extern void vToggleLED( void );
+
+	/* Remove compiler warning about unused parameter. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		/* Wait until something arrives in the queue - this task will block
+		indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
+		FreeRTOSConfig.h. */
+		xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
+
+		/*  To get here something must have been received from the queue, but
+		is it the expected value?  If it is, toggle the LED. */
+		if( ulReceivedValue == ulExpectedValue )
+		{
+			vSendString( pcPassMessage );
+			vToggleLED();
+			ulReceivedValue = 0U;
+		}
+		else
+		{
+			vSendString( pcFailMessage );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/RegTest.S b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/RegTest.S
new file mode 100644
index 0000000..b40c18d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/RegTest.S
@@ -0,0 +1,341 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	.extern ulRegTest1LoopCounter
+	.extern ulRegTest2LoopCounter
+
+	.global vRegTest1Implementation
+	.global vRegTest2Implementation
+
+/*-----------------------------------------------------------*/
+
+/* Constants to define the additional registers found on the Pulpino RI5KY. */
+#define lpstart0 	0x7b0
+#define lpend0 		0x7b1
+#define lpcount0 	0x7b2
+#define lpstart1 	0x7b4
+#define lpend1 		0x7b5
+#define lpcount1 	0x7b6
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The register check tasks are described in the comments at the top of
+ * main_full.c.
+ */
+vRegTest1Implementation:
+
+	/* Fill the additional registers with known values. */
+	li t0, 0xaa
+	csrw lpstart0, t0
+	li t0, 0xab
+	csrw lpstart1, t0
+	li t0, 0xac
+	csrw lpend0, t0
+	li t0, 0xad
+	csrw lpend1, t0
+	li t0, 0xae
+	csrw lpcount0, t0
+	li t0, 0xaf
+	csrw lpcount1, t0
+
+	/* Fill the core registers with known values. */
+	li x5, 0x5
+	li x6, 0x6
+	li x7, 0x7
+	li x8, 0x8
+	li x9, 0x9
+	li x10, 0xa
+	li x11, 0xb
+	li x12, 0xc
+	li x13, 0xd
+	li x14, 0xe
+	li x15, 0xf
+	li x16, 0x10
+	li x17, 0x11
+	li x18, 0x12
+	li x19, 0x13
+	li x20, 0x14
+	li x21, 0x15
+	li x22, 0x16
+	li x23, 0x17
+	li x24, 0x18
+	li x25, 0x19
+	li x26, 0x1a
+	li x27, 0x1b
+	li x28, 0x1c
+	li x29, 0x1d
+	li x30, 0x1e
+
+reg1_loop:
+
+	/* Check each register still contains the expected known value.
+	vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation
+	uses x5 as the temporary. */
+	li x31, 0x5
+	bne x31, x5, reg1_error_loop
+	li x31, 0x6
+	bne x31, x6, reg1_error_loop
+	li x31, 0x7
+	bne x31, x7, reg1_error_loop
+	li x31, 0x8
+	bne x31, x8, reg1_error_loop
+	li x31, 0x9
+	bne x31, x9, reg1_error_loop
+	li x31, 0xa
+	bne x31, x10, reg1_error_loop
+	li x31, 0xb
+	bne x31, x11, reg1_error_loop
+	li x31, 0xc
+	bne x31, x12, reg1_error_loop
+	li x31, 0xd
+	bne x31, x13, reg1_error_loop
+	li x31, 0xe
+	bne x31, x14, reg1_error_loop
+	li x31, 0xf
+	bne x31, x15, reg1_error_loop
+	li x31, 0x10
+	bne x31, x16, reg1_error_loop
+	li x31, 0x11
+	bne x31, x17, reg1_error_loop
+	li x31, 0x12
+	bne x31, x18, reg1_error_loop
+	li x31, 0x13
+	bne x31, x19, reg1_error_loop
+	li x31, 0x14
+	bne x31, x20, reg1_error_loop
+	li x31, 0x15
+	bne x31, x21, reg1_error_loop
+	li x31, 0x16
+	bne x31, x22, reg1_error_loop
+	li x31, 0x17
+	bne x31, x23, reg1_error_loop
+	li x31, 0x18
+	bne x31, x24, reg1_error_loop
+	li x31, 0x19
+	bne x31, x25, reg1_error_loop
+	li x31, 0x1a
+	bne x31, x26, reg1_error_loop
+	li x31, 0x1b
+	bne x31, x27, reg1_error_loop
+	li x31, 0x1c
+	bne x31, x28, reg1_error_loop
+	li x31, 0x1d
+	bne x31, x29, reg1_error_loop
+	li x31, 0x1e
+	bne x31, x30, reg1_error_loop
+
+	/* Check additional chip specific registers still contain the expected
+	values. */
+	csrr x30, lpstart0
+	li x31, 0xaa
+	bne x30, x31, reg1_error_loop
+	csrr x30, lpstart1
+	li x31, 0xab
+	bne x30, x31, reg1_error_loop
+	csrr x30, lpend0
+	li x31, 0xac
+	bne x30, x31, reg1_error_loop
+	csrr x30, lpend1
+	li x31, 0xad
+	bne x30, x31, reg1_error_loop
+	csrr x30, lpcount0
+	li x31, 0xae
+	bne x30, x31, reg1_error_loop
+	csrr x30, lpcount1
+	li x31, 0xaf
+	bne x30, x31, reg1_error_loop
+
+	/* Everything passed, increment the loop counter. */
+	lw x31, ulRegTest1LoopCounterConst
+	lw x30, 0(x31)
+	addi x30, x30, 1
+	sw x30, 0(x31)
+
+	/* Restore clobbered register reading for next loop. */
+	li x30, 0x1e
+
+	/* Yield to increase code coverage. */
+	ecall
+
+	/* Start again. */
+	jal reg1_loop
+
+reg1_error_loop:
+	/* Jump here if a register contains an uxpected value.  This stops the loop
+	counter being incremented so the check task knows an error was found. */
+	ebreak
+	jal reg1_error_loop
+
+ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter
+
+/*-----------------------------------------------------------*/
+
+vRegTest2Implementation:
+
+	/* Fill the additional registers with known values. */
+	li t0, 0x1aa
+	csrw lpstart0, t0
+	li t0, 0x1ab
+	csrw lpstart1, t0
+	li t0, 0x1ac
+	csrw lpend0, t0
+	li t0, 0x1ad
+	csrw lpend1, t0
+	li t0, 0x1ae
+	csrw lpcount0, t0
+	li t0, 0x1af
+	csrw lpcount1, t0
+
+	/* Fill the core registers with known values. */
+	li x6, 0x61
+	li x7, 0x71
+	li x8, 0x81
+	li x9, 0x91
+	li x10, 0xa1
+	li x11, 0xb1
+	li x12, 0xc1
+	li x13, 0xd1
+	li x14, 0xe1
+	li x15, 0xf1
+	li x16, 0x20
+	li x17, 0x21
+	li x18, 0x22
+	li x19, 0x23
+	li x20, 0x24
+	li x21, 0x25
+	li x22, 0x26
+	li x23, 0x27
+	li x24, 0x28
+	li x25, 0x29
+	li x26, 0x2a
+	li x27, 0x2b
+	li x28, 0x2c
+	li x29, 0x2d
+	li x30, 0x2e
+	li x31, 0x2f
+
+Reg2_loop:
+
+	/* Check each register still contains the expected known value.
+	vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation
+	uses x31 as the temporary. */
+	li x5, 0x61
+	bne x5, x6, reg2_error_loop
+	li x5, 0x71
+	bne x5, x7, reg2_error_loop
+	li x5, 0x81
+	bne x5, x8, reg2_error_loop
+	li x5, 0x91
+	bne x5, x9, reg2_error_loop
+	li x5, 0xa1
+	bne x5, x10, reg2_error_loop
+	li x5, 0xb1
+	bne x5, x11, reg2_error_loop
+	li x5, 0xc1
+	bne x5, x12, reg2_error_loop
+	li x5, 0xd1
+	bne x5, x13, reg2_error_loop
+	li x5, 0xe1
+	bne x5, x14, reg2_error_loop
+	li x5, 0xf1
+	bne x5, x15, reg2_error_loop
+	li x5, 0x20
+	bne x5, x16, reg2_error_loop
+	li x5, 0x21
+	bne x5, x17, reg2_error_loop
+	li x5, 0x22
+	bne x5, x18, reg2_error_loop
+	li x5, 0x23
+	bne x5, x19, reg2_error_loop
+	li x5, 0x24
+	bne x5, x20, reg2_error_loop
+	li x5, 0x25
+	bne x5, x21, reg2_error_loop
+	li x5, 0x26
+	bne x5, x22, reg2_error_loop
+	li x5, 0x27
+	bne x5, x23, reg2_error_loop
+	li x5, 0x28
+	bne x5, x24, reg2_error_loop
+	li x5, 0x29
+	bne x5, x25, reg2_error_loop
+	li x5, 0x2a
+	bne x5, x26, reg2_error_loop
+	li x5, 0x2b
+	bne x5, x27, reg2_error_loop
+	li x5, 0x2c
+	bne x5, x28, reg2_error_loop
+	li x5, 0x2d
+	bne x5, x29, reg2_error_loop
+	li x5, 0x2e
+	bne x5, x30, reg2_error_loop
+	li x5, 0x2f
+	bne x5, x31, reg2_error_loop
+
+	/* Check additional chip specific registers still contain the expected
+	values. */
+	csrr x5, lpstart0
+	li x6, 0x1aa
+	bne x5, x6, reg2_error_loop
+	csrr x5, lpstart1
+	li x6, 0x1ab
+	bne x5, x6, reg2_error_loop
+	csrr x5, lpend0
+	li x6, 0x1ac
+	bne x5, x6, reg2_error_loop
+	csrr x5, lpend1
+	li x6, 0x1ad
+	bne x5, x6, reg2_error_loop
+	csrr x5, lpcount0
+	li x6, 0x1ae
+	bne x5, x6, reg2_error_loop
+	csrr x5, lpcount1
+	li x6, 0x1af
+	bne x5, x6, reg2_error_loop
+
+	/* Everything passed, increment the loop counter. */
+	lw x5, ulRegTest2LoopCounterConst
+	lw x6, 0(x5)
+	addi x6, x6, 1
+	sw x6, 0(x5)
+
+	/* Restore clobbered register reading for next loop. */
+	li x6, 0x61
+
+	/* Start again. */
+	jal Reg2_loop
+
+reg2_error_loop:
+	/* Jump here if a register contains an uxpected value.  This stops the loop
+	counter being incremented so the check task knows an error was found. */
+	ebreak
+	jal reg2_error_loop
+
+ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/main_full.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/main_full.c
new file mode 100644
index 0000000..501e7ad
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/main_full.c
@@ -0,0 +1,407 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/******************************************************************************
+ * NOTE 1:  This project provides two demo applications.  A simple blinky style
+ * project, and a more comprehensive test and demo application.  The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
+ * between the two.  See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
+ * in main.c.  This file implements the comprehensive test and demo version.
+ *
+ * NOTE 2:  This file only contains the source code that is specific to the
+ * full demo.  Generic functions, such FreeRTOS hook functions, and functions
+ * required to configure the hardware, are defined in main.c.
+ *
+ ******************************************************************************
+ *
+ * main_full() creates all the demo application tasks and software timers, then
+ * starts the scheduler.  The web documentation provides more details of the
+ * standard demo application tasks, which provide no particular functionality,
+ * but do provide a good example of how to use the FreeRTOS API.
+ *
+ * In addition to the standard demo tasks, the following tasks and tests are
+ * defined and/or created within this file:
+ *
+ * "Reg test" tasks - These fill both the core registers with known values, then
+ * check that each register maintains its expected value for the lifetime of the
+ * task.  Each task uses a different set of values.  The reg test tasks execute
+ * with a very low priority, so get preempted very frequently.  A register
+ * containing an unexpected value is indicative of an error in the context
+ * switching mechanism.
+ *
+ * "Check" task - The check executes every three seconds.  It checks that all
+ * the standard demo tasks, and the register check tasks, are not only still
+ * executing, but are executing without reporting any errors.  If the check task
+ * discovers that a task has either stalled, or reported an error, then it
+ * prints an error message to the UART, otherwise it prints "Pass.".
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "semphr.h"
+
+/* Standard demo application includes. */
+#include "dynamic.h"
+#include "blocktim.h"
+#include "GenQTest.h"
+#include "recmutex.h"
+#include "TimerDemo.h"
+#include "EventGroupsDemo.h"
+#include "TaskNotify.h"
+#include "AbortDelay.h"
+#include "countsem.h"
+#include "death.h"
+#include "MessageBufferDemo.h"
+#include "StreamBufferDemo.h"
+#include "StreamBufferInterrupt.h"
+
+/* Priorities for the demo application tasks. */
+#define mainCHECK_TASK_PRIORITY				( configMAX_PRIORITIES - 1 )
+#define mainCREATOR_TASK_PRIORITY			( tskIDLE_PRIORITY + 3UL )
+
+/* The period of the check task, in ms, converted to ticks using the
+pdMS_TO_TICKS() macro.  mainNO_ERROR_CHECK_TASK_PERIOD is used if no errors have
+been found, mainERROR_CHECK_TASK_PERIOD is used if an error has been found. */
+#define mainNO_ERROR_CHECK_TASK_PERIOD		pdMS_TO_TICKS( 3000UL )
+#define mainERROR_CHECK_TASK_PERIOD			pdMS_TO_TICKS( 500UL )
+
+/* Parameters that are passed into the register check tasks solely for the
+purpose of ensuring parameters are passed into tasks correctly. */
+#define mainREG_TEST_TASK_1_PARAMETER		( ( void * ) 0x12345678 )
+#define mainREG_TEST_TASK_2_PARAMETER		( ( void * ) 0x87654321 )
+
+/* The base period used by the timer test tasks. */
+#define mainTIMER_TEST_PERIOD				( 50 )
+
+/* The size of the stack allocated to the check task (as described in the
+comments at the top of this file.  This is surprisingly large as it calls
+the logging library's print function, which allocates a 128 byte buffer on its
+stack. */
+#define mainCHECK_TASK_STACK_SIZE_WORDS 200
+
+/* Size of the stacks to allocated for the register check tasks. */
+#define mainREG_TEST_STACK_SIZE_WORDS 150
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by main() to run the full demo (as opposed to the blinky demo) when
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
+ */
+void main_full( void );
+
+/*
+ * The check task, as described at the top of this file.
+ */
+static void prvCheckTask( void *pvParameters );
+
+/*
+ * Initialise and start the peripheral timers that are used to exercise external
+ * interrupt processing.
+ */
+static void prvSetupPeripheralTimers( void );
+
+/*
+ * Register check tasks as described at the top of this file.  The nature of
+ * these files necessitates that they are written in an assembly file, but the
+ * entry points are kept in the C file for the convenience of checking the task
+ * parameter.
+ */
+static void prvRegTestTaskEntry1( void *pvParameters );
+extern void vRegTest1Implementation( void );
+static void prvRegTestTaskEntry2( void *pvParameters );
+extern void vRegTest2Implementation( void );
+
+/*
+ * Tick hook used by the full demo, which includes code that interacts with
+ * some of the tests.
+ */
+void vFullDemoTickHook( void );
+
+/*-----------------------------------------------------------*/
+
+/* The following two variables are used to communicate the status of the
+register check tasks to the check task.  If the variables keep incrementing,
+then the register check tasks have not discovered any errors.  If a variable
+stops incrementing, then an error has been found. */
+volatile uint32_t ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
+
+/*-----------------------------------------------------------*/
+
+void main_full( void )
+{
+	/* Start all the other standard demo/test tasks.  They have no particular
+	functionality, but do demonstrate how to use the FreeRTOS API and test the
+	kernel port. */
+	vStartDynamicPriorityTasks();
+	vCreateBlockTimeTasks();
+	vStartGenericQueueTasks( tskIDLE_PRIORITY );
+	vStartRecursiveMutexTasks();
+	vStartTimerDemoTask( mainTIMER_TEST_PERIOD );
+	vStartEventGroupTasks();
+	vStartTaskNotifyTask();
+	vCreateAbortDelayTasks();
+	vStartCountingSemaphoreTasks();
+	vStartMessageBufferTasks( configMINIMAL_STACK_SIZE  );
+	vStartStreamBufferTasks();
+	vStartStreamBufferInterruptDemo();
+
+	/* Create the register check tasks, as described at the top of this	file.
+	Use xTaskCreateStatic() to create a task using only statically allocated
+	memory. */
+	xTaskCreate( prvRegTestTaskEntry1, 			/* The function that implements the task. */
+				 "Reg1", 						/* The name of the task. */
+				 mainREG_TEST_STACK_SIZE_WORDS, /* Size of stack to allocate for the task - in words not bytes!. */
+				 mainREG_TEST_TASK_1_PARAMETER, /* Parameter passed into the task. */
+				 tskIDLE_PRIORITY, 				/* Priority of the task. */
+				 NULL );						/* Can be used to pass out a handle to the created task. */
+	xTaskCreate( prvRegTestTaskEntry2, "Reg2", mainREG_TEST_STACK_SIZE_WORDS, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL );
+
+	/* Create the task that performs the 'check' functionality,	as described at
+	the top of this file. */
+	xTaskCreate( prvCheckTask, "Check", mainCHECK_TASK_STACK_SIZE_WORDS, NULL, mainCHECK_TASK_PRIORITY, NULL );
+
+	/* The set of tasks created by the following function call have to be
+	created last as they keep account of the number of tasks they expect to see
+	running. */
+	vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
+
+	/* Start the timers that are used to exercise external interrupt handling. */
+	prvSetupPeripheralTimers();
+
+	/* Start the scheduler. */
+	vTaskStartScheduler();
+
+	/* If all is well, the scheduler will now be running, and the following
+	line will never be reached.  If the following line does execute, then
+	there was insufficient FreeRTOS heap memory available for the Idle and/or
+	timer tasks to be created.  See the memory management section on the
+	FreeRTOS web site for more details on the FreeRTOS heap
+	http://www.freertos.org/a00111.html. */
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTask( void *pvParameters )
+{
+TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;
+TickType_t xLastExecutionTime;
+uint32_t ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
+char * const pcPassMessage = ".";
+char * pcStatusMessage = pcPassMessage;
+extern void vSendString( const char * const pcString );
+extern void vToggleLED( void );
+
+	/* Just to stop compiler warnings. */
+	( void ) pvParameters;
+
+	/* Output "pass", then an additional '.' character for each successful
+	loop. */
+	vSendString( "Pass" );
+
+	/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
+	works correctly. */
+	xLastExecutionTime = xTaskGetTickCount();
+
+	/* Cycle for ever, delaying then checking all the other tasks are still
+	operating without error.  The onboard LED is toggled on each iteration.
+	If an error is detected then the delay period is decreased from
+	mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD.  This has the
+	effect of increasing the rate at which the onboard LED toggles, and in so
+	doing gives visual feedback of the system status. */
+	for( ;; )
+	{
+		/* Delay until it is time to execute again. */
+		vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );
+
+		/* Check all the demo tasks (other than the flash tasks) to ensure
+		that they are all still running, and that none have detected an error. */
+		if( xAreDynamicPriorityTasksStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Dynamic priority demo/tests.\r\n";
+		}
+
+		if( xAreBlockTimeTestTasksStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Block time demo/tests.\r\n";
+		}
+
+		if( xAreGenericQueueTasksStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Generic queue demo/tests.\r\n";
+		}
+
+		if( xAreRecursiveMutexTasksStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Recursive mutex demo/tests.\r\n";
+		}
+
+		if( xAreTimerDemoTasksStillRunning( ( TickType_t ) xDelayPeriod ) == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Timer demo/tests.\r\n";
+		}
+
+		if( xAreEventGroupTasksStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Event group demo/tests.\r\n";
+		}
+
+		if( xAreTaskNotificationTasksStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Task notification demo/tests.\r\n";
+		}
+
+		if( xAreAbortDelayTestTasksStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Abort delay.\r\n";
+		}
+
+		if( xAreCountingSemaphoreTasksStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Counting semaphores.\r\n";
+		}
+
+		if( xIsCreateTaskStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Suicide tasks.\r\n";
+		}
+
+		if( xAreMessageBufferTasksStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Message buffer.\r\n";
+		}
+
+		if( xAreStreamBufferTasksStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Stream buffer.\r\n";
+		}
+
+		if( xIsInterruptStreamBufferDemoStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Stream buffer interrupt.\r\n";
+		}
+
+		/* Check that the register test 1 task is still running. */
+		if( ulLastRegTest1Value == ulRegTest1LoopCounter )
+		{
+			pcStatusMessage = "ERROR: Register test 1.\r\n";
+		}
+		ulLastRegTest1Value = ulRegTest1LoopCounter;
+
+		/* Check that the register test 2 task is still running. */
+		if( ulLastRegTest2Value == ulRegTest2LoopCounter )
+		{
+			pcStatusMessage = "ERROR: Register test 2.\r\n";
+		}
+		ulLastRegTest2Value = ulRegTest2LoopCounter;
+
+		/* Write the status message to the UART. */
+		vToggleLED();
+		vSendString( pcStatusMessage );
+
+		/* If an error has been found then increase the LED toggle rate by
+		increasing the cycle frequency. */
+		if( pcStatusMessage != pcPassMessage )
+		{
+			xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTestTaskEntry1( void *pvParameters )
+{
+	/* Although the regtest task is written in assembler, its entry point is
+	written in C for convenience of checking the task parameter is being passed
+	in correctly. */
+	if( pvParameters == mainREG_TEST_TASK_1_PARAMETER )
+	{
+		/* Start the part of the test that is written in assembler. */
+		vRegTest1Implementation();
+	}
+
+	/* The following line will only execute if the task parameter is found to
+	be incorrect.  The check task will detect that the regtest loop counter is
+	not being incremented and flag an error. */
+	vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTestTaskEntry2( void *pvParameters )
+{
+	/* Although the regtest task is written in assembler, its entry point is
+	written in C for convenience of checking the task parameter is being passed
+	in correctly. */
+	if( pvParameters == mainREG_TEST_TASK_2_PARAMETER )
+	{
+		/* Start the part of the test that is written in assembler. */
+		vRegTest2Implementation();
+	}
+
+	/* The following line will only execute if the task parameter is found to
+	be incorrect.  The check task will detect that the regtest loop counter is
+	not being incremented and flag an error. */
+	vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+void vFullDemoTickHook( void )
+{
+	/* The full demo includes a software timer demo/test that requires
+	prodding periodically from the tick interrupt. */
+	vTimerPeriodicISRTests();
+
+	/* Call the periodic event group from ISR demo. */
+	vPeriodicEventGroupsProcessing();
+
+	/* Use task notifications from an interrupt. */
+	xNotifyTaskFromISR();
+
+	/* Writes to stream buffer byte by byte to test the stream buffer trigger
+	level functionality. */
+	vPeriodicStreamBufferProcessing();
+
+	/* Writes a string to a string buffer four bytes at a time to demonstrate
+	a stream being sent from an interrupt to a task. */
+	vBasicStreamBufferSendFromISR();
+
+	/* Called from vApplicationTickHook() when the project is configured to
+	build the full test/demo applications. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupPeripheralTimers( void )
+{
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/main.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/main.c
new file mode 100644
index 0000000..b8741cd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/main.c
@@ -0,0 +1,252 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*
+ * Create implementation of vPortSetupTimerInterrupt() if the CLINT is not
+ * available, but make sure the configCLINT_BASE_ADDRESS constant is still
+ * defined.
+ *
+ * Define vPortHandleInterrupt to whatever the interrupt handler is called.  In
+ * this case done by defining vPortHandleInterrupt=SystemIrqHandler on the
+ * assembler command line as SystemIrqHandler is referenced from both FreeRTOS
+ * code and the libraries that come with the Vega board.
+ */
+
+/* FreeRTOS kernel includes. */
+#include 
+#include 
+
+/* Vega includes. */
+#include "fsl_device_registers.h"
+#include "fsl_debug_console.h"
+#include "board.h"
+#include "pin_mux.h"
+#include "clock_config.h"
+
+
+/******************************************************************************
+ * This project provides two demo applications.  A simple blinky style project,
+ * and a more comprehensive test and demo application.  The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to
+ * select between the two.  The simply blinky demo is implemented and described
+ * in main_blinky.c.  The more comprehensive test and demo application is
+ * implemented and described in main_full.c.
+ *
+ * This file implements the code that is not demo specific, including the
+ * hardware setup and standard FreeRTOS hook functions.
+ *
+ * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON
+ * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO
+ * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!
+ *
+ */
+
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
+or 0 to run the more comprehensive test and demo application. */
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY	0
+
+/*
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
+ */
+#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1
+	extern void main_blinky( void );
+#else
+	extern void main_full( void );
+#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */
+
+/* Prototypes for the standard FreeRTOS callback/hook functions implemented
+within this file.  See https://www.freertos.org/a00016.html */
+void vApplicationMallocFailedHook( void );
+void vApplicationIdleHook( void );
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );
+void vApplicationTickHook( void );
+
+/* Prepare haredware to run the demo. */
+static void prvSetupHardware( void );
+
+/* Send a messaage to the UART initialised in prvSetupHardware. */
+void vSendString( const char * const pcString );
+
+/*-----------------------------------------------------------*/
+
+void main( void )
+{
+	prvSetupHardware();
+
+	/* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top
+	of this file. */
+	#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )
+	{
+		main_blinky();
+	}
+	#else
+	{
+		main_full();
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupHardware( void )
+{
+gpio_pin_config_t mGpioPinConfigStruct;
+
+	/* Init board hardware. */
+	BOARD_InitPins();
+	BOARD_BootClockRUN();
+	BOARD_InitDebugConsole();
+
+	/* For LED. */
+	mGpioPinConfigStruct.outputLogic = 1U; /* High. */
+	mGpioPinConfigStruct.pinDirection = kGPIO_DigitalOutput;
+	GPIO_PinInit( BOARD_LED1_GPIO, BOARD_LED1_GPIO_PIN, &mGpioPinConfigStruct );
+}
+/*-----------------------------------------------------------*/
+
+void vToggleLED( void )
+{
+	GPIO_TogglePinsOutput( BOARD_LED1_GPIO, 1U << BOARD_LED1_GPIO_PIN );
+}
+/*-----------------------------------------------------------*/
+
+void vSendString( const char * const pcString )
+{
+	PRINTF( pcString );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationMallocFailedHook( void )
+{
+	/* vApplicationMallocFailedHook() will only be called if
+	configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h.  It is a hook
+	function that will get called if a call to pvPortMalloc() fails.
+	pvPortMalloc() is called internally by the kernel whenever a task, queue,
+	timer or semaphore is created.  It is also called by various parts of the
+	demo application.  If heap_1.c or heap_2.c are used, then the size of the
+	heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
+	FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
+	to query the size of free heap space that remains (although it does not
+	provide information on how the remaining heap might be fragmented). */
+	taskDISABLE_INTERRUPTS();
+	__asm volatile( "ebreak" );
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+	/* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
+	to 1 in FreeRTOSConfig.h.  It will be called on each iteration of the idle
+	task.  It is essential that code added to this hook function never attempts
+	to block in any way (for example, call xQueueReceive() with a block time
+	specified, or call vTaskDelay()).  If the application makes use of the
+	vTaskDelete() API function (as this demo application does) then it is also
+	important that vApplicationIdleHook() is permitted to return to its calling
+	function, because it is the responsibility of the idle task to clean up
+	memory allocated by the kernel to any task that has since been deleted. */
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
+{
+	( void ) pcTaskName;
+	( void ) pxTask;
+
+	/* Run time stack overflow checking is performed if
+	configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2.  This hook
+	function is called if a stack overflow is detected. */
+	taskDISABLE_INTERRUPTS();
+	__asm volatile( "ebreak" );
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationTickHook( void )
+{
+	/* The tests in the full demo expect some interaction with interrupts. */
+	#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 )
+	{
+		extern void vFullDemoTickHook( void );
+		vFullDemoTickHook();
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetupTimerInterrupt( void )
+{
+extern void SystemSetupSystick(uint32_t tickRateHz, uint32_t intPriority );
+
+	/* No CLINT so use the LPIT (Low Power Interrupt Timer) to generate the tick
+	interrupt. */
+	CLOCK_SetIpSrc( kCLOCK_Lpit0, kCLOCK_IpSrcFircAsync );
+	SystemSetupSystick( configTICK_RATE_HZ, configKERNEL_INTERRUPT_PRIORITY - 1 );
+}
+/*-----------------------------------------------------------*/
+
+void LPIT0_IRQHandler( void )
+{
+BaseType_t xTaskIncrementTick( void );
+void vTaskSwitchContext( void );
+
+#warning requires critical section if interrpt nesting is used.
+
+	/* vPortSetupTimerInterrupt() uses LPIT0 to generate the tick interrupt. */
+	if( xTaskIncrementTick() != 0 )
+	{
+		vTaskSwitchContext();
+	}
+
+	/* Clear LPIT0 interrupt. */
+	LPIT0->MSR = 1U;
+}
+/*-----------------------------------------------------------*/
+
+/* At the time of writing, interrupt nesting is not supported, so do not use
+the default SystemIrqHandler() implementation as that enables interrupts.  A
+version that does not enable interrupts is provided below.  THIS INTERRUPT
+HANDLER IS SPECIFIC TO THE VEGA BOARD WHICH DOES NOT INCLUDE A CLINT! */
+void SystemIrqHandler( uint32_t mcause )
+{
+uint32_t ulInterruptNumber;
+typedef void ( * irq_handler_t )( void );
+extern const irq_handler_t isrTable[];
+
+	ulInterruptNumber = mcause & 0x1FUL;
+
+	/* Clear pending flag in EVENT unit .*/
+	EVENT_UNIT->INTPTPENDCLEAR = ( 1U << ulInterruptNumber );
+
+	/* Read back to make sure write finished. */
+	(void)(EVENT_UNIT->INTPTPENDCLEAR);
+
+	/* Now call the real irq handler for ulInterruptNumber */
+	isrTable[ ulInterruptNumber ]();
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/.cproject b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/.cproject
new file mode 100644
index 0000000..ec8b664
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/.cproject
@@ -0,0 +1,374 @@
+
+
+    	
+    
+        		
+        
+            			
+            
+                				
+                
+                				
+                
+                    					
+                    
+                    					
+                    
+                    					
+                    
+                    					
+                    
+                    					
+                    
+                    					
+                    
+                    				
+                
+                			
+            
+            			
+            
+                				
+                
+                    					
+                    
+                        						
+                        
+                            							
+                            
+                        					
+                    
+                    					
+                    
+                        						
+                        
+                            							
+                            
+                        					
+                    
+                    					
+                    
+                        						
+                        
+                        					
+                    
+                    				
+                
+                			
+            
+            			
+            
+            		
+        
+        	
+    
+    	
+    
+        		
+        
+        	
+    
+    	
+    
+        		
+        
+        		
+        
+            			
+            
+            		
+        
+        		
+        
+            			
+            
+            		
+        
+        	
+    
+    	
+    
+    	
+    
+    	
+    
+        		
+        
+            			
+            
+            		
+        
+        	
+    
+    
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/.project b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/.project
new file mode 100644
index 0000000..a336498
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/.project
@@ -0,0 +1,237 @@
+
+
+	RTOSDemo
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		org.eclipse.cdt.core.cnature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			FreeRTOS_Source
+			2
+			FREERTOS_ROOT/FreeRTOS/Source
+		
+		
+			full_demo/common_demo_tasks
+			2
+			virtual:/virtual
+		
+		
+			full_demo/common_demo_tasks/AbortDelay.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/AbortDelay.c
+		
+		
+			full_demo/common_demo_tasks/EventGroupsDemo.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/EventGroupsDemo.c
+		
+		
+			full_demo/common_demo_tasks/GenQTest.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/GenQTest.c
+		
+		
+			full_demo/common_demo_tasks/MessageBufferDemo.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/MessageBufferDemo.c
+		
+		
+			full_demo/common_demo_tasks/StreamBufferDemo.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/StreamBufferDemo.c
+		
+		
+			full_demo/common_demo_tasks/StreamBufferInterrupt.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/StreamBufferInterrupt.c
+		
+		
+			full_demo/common_demo_tasks/TaskNotify.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/TaskNotify.c
+		
+		
+			full_demo/common_demo_tasks/TimerDemo.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/TimerDemo.c
+		
+		
+			full_demo/common_demo_tasks/blocktim.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/blocktim.c
+		
+		
+			full_demo/common_demo_tasks/countsem.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/countsem.c
+		
+		
+			full_demo/common_demo_tasks/death.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/death.c
+		
+		
+			full_demo/common_demo_tasks/dynamic.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/dynamic.c
+		
+		
+			full_demo/common_demo_tasks/include
+			2
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/include
+		
+		
+			full_demo/common_demo_tasks/recmutex.c
+			1
+			FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/recmutex.c
+		
+	
+	
+		
+			1529524430510
+			FreeRTOS_Source
+			9
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-include
+			
+		
+		
+			1529524430514
+			FreeRTOS_Source
+			9
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-portable
+			
+		
+		
+			1529524430518
+			FreeRTOS_Source
+			5
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-event_groups.c
+			
+		
+		
+			1529524430521
+			FreeRTOS_Source
+			5
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-list.c
+			
+		
+		
+			1529524430525
+			FreeRTOS_Source
+			5
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-queue.c
+			
+		
+		
+			1529524430529
+			FreeRTOS_Source
+			5
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-stream_buffer.c
+			
+		
+		
+			1529524430533
+			FreeRTOS_Source
+			5
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-tasks.c
+			
+		
+		
+			1529524430538
+			FreeRTOS_Source
+			5
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-timers.c
+			
+		
+		
+			1531000165521
+			FreeRTOS_Source/portable
+			9
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-GCC
+			
+		
+		
+			1531000165526
+			FreeRTOS_Source/portable
+			9
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-MemMang
+			
+		
+		
+			1531000203197
+			FreeRTOS_Source/portable/GCC
+			9
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-RISC-V
+			
+		
+		
+			1529524494421
+			FreeRTOS_Source/portable/MemMang
+			5
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-heap_4.c
+			
+		
+		
+			1546279974088
+			FreeRTOS_Source/portable/GCC/RISC-V/chip_specific_extensions
+			9
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-RV32I_CLINT_no_extensions
+			
+		
+	
+	
+		
+			FREERTOS_ROOT
+			$%7BPARENT-3-PROJECT_LOC%7D
+		
+		
+			copy_PARENT
+			$%7BPARENT-4-PROJECT_LOC%7D/FreeRTOS/WorkingCopy/FreeRTOS
+		
+	
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/.settings/language.settings.xml b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/.settings/language.settings.xml
new file mode 100644
index 0000000..2b14205
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/.settings/language.settings.xml
@@ -0,0 +1,26 @@
+
+
+    	
+    
+        		
+        
+            			
+            
+            			
+            
+            			
+            
+            			
+            
+                				
+                
+                				
+                
+                			
+            
+            		
+        
+        	
+    
+    
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Demo Documentation.url b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Demo Documentation.url
new file mode 100644
index 0000000..c3cf125
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Demo Documentation.url	
@@ -0,0 +1,5 @@
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,11
+[InternetShortcut]
+IDList=
+URL=https://freertos.org/RTOS-RISC-V-SoftConsole-Renode-SiFive.html
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/FreeRTOSConfig.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/FreeRTOSConfig.h
new file mode 100644
index 0000000..724426b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/FreeRTOSConfig.h
@@ -0,0 +1,146 @@
+/*
+    FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include "hw_platform.h"
+#include "riscv_plic.h"
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configCLINT_BASE_ADDRESS		PRCI_BASE
+#define configUSE_PREEMPTION			1
+#define configUSE_IDLE_HOOK				1
+#define configUSE_TICK_HOOK				1
+#define configCPU_CLOCK_HZ				( ( uint32_t ) ( SYS_CLK_FREQ ) )
+#define configTICK_RATE_HZ				( ( TickType_t ) 1000 )
+#define configMAX_PRIORITIES			( 5 )
+#define configMINIMAL_STACK_SIZE		( ( uint32_t ) 170 ) /* Can be as low as 60 but some of the demo tasks that use this constant require it to be higher. */
+#define configTOTAL_HEAP_SIZE			( ( size_t ) ( 280 * 1024 ) )
+#define configMAX_TASK_NAME_LEN			( 16 )
+#define configUSE_TRACE_FACILITY		0
+#define configUSE_16_BIT_TICKS			0
+#define configIDLE_SHOULD_YIELD			0
+#define configUSE_MUTEXES				1
+#define configQUEUE_REGISTRY_SIZE		8
+#define configCHECK_FOR_STACK_OVERFLOW	2
+#define configUSE_RECURSIVE_MUTEXES		1
+#define configUSE_MALLOC_FAILED_HOOK	1
+#define configUSE_APPLICATION_TASK_TAG	0
+#define configUSE_COUNTING_SEMAPHORES	1
+#define configGENERATE_RUN_TIME_STATS	0
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 			0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Software timer definitions. */
+#define configUSE_TIMERS				1
+#define configTIMER_TASK_PRIORITY		( configMAX_PRIORITIES - 1 )
+#define configTIMER_QUEUE_LENGTH		4
+#define configTIMER_TASK_STACK_DEPTH	( configMINIMAL_STACK_SIZE )
+
+/* Task priorities.  Allow these to be overridden. */
+#ifndef uartPRIMARY_PRIORITY
+	#define uartPRIMARY_PRIORITY		( configMAX_PRIORITIES - 3 )
+#endif
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet			1
+#define INCLUDE_uxTaskPriorityGet			1
+#define INCLUDE_vTaskDelete					1
+#define INCLUDE_vTaskCleanUpResources		1
+#define INCLUDE_vTaskSuspend				1
+#define INCLUDE_vTaskDelayUntil				1
+#define INCLUDE_vTaskDelay					1
+#define INCLUDE_eTaskGetState				1
+#define INCLUDE_xTimerPendFunctionCall		1
+#define INCLUDE_xTaskAbortDelay				1
+#define INCLUDE_xTaskGetHandle				1
+#define INCLUDE_xSemaphoreGetMutexHolder	1
+
+/* Normal assert() semantics without relying on the provision of an assert.h
+header file. */
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); __asm volatile( "ebreak" ); for( ;; ); }
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/Packages/.repos.xml b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/Packages/.repos.xml
new file mode 100644
index 0000000..76dbb89
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/Packages/.repos.xml
@@ -0,0 +1,8 @@
+
+
+  
+    CMSIS Pack
+    Keil
+    http://www.keil.com/pack/index.pidx
+  
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/Core16550/core16550_regs.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/Core16550/core16550_regs.h
new file mode 100644
index 0000000..0b921ce
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/Core16550/core16550_regs.h
@@ -0,0 +1,582 @@
+/*******************************************************************************
+ * (c) Copyright 2007-2015 Microsemi SoC Products Group. All rights reserved.
+ *
+ * IP core registers definitions. This file contains the definitions required
+ * for accessing the IP core through the hardware abstraction layer (HAL).
+ * This file was automatically generated, using "get_header.exe" version 0.4.0,
+ * from the IP-XACT description for:
+ *
+ *             Core16550    version: 2.0.0
+ *
+ * SVN $Revision: 7963 $
+ * SVN $Date: 2015-10-09 17:58:21 +0530 (Fri, 09 Oct 2015) $
+ *
+ *******************************************************************************/
+#ifndef CORE_16550_REGISTERS_H_
+#define CORE_16550_REGISTERS_H_ 1
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * RBR register:
+ *------------------------------------------------------------------------------
+ * Receive Buffer Register
+ */
+#define RBR_REG_OFFSET	0x00U
+
+/*******************************************************************************
+ * THR register:
+ *------------------------------------------------------------------------------
+ * Transmit Holding Register
+ */
+#define THR_REG_OFFSET	0x00U
+
+/*******************************************************************************
+ * DLR register:
+ *------------------------------------------------------------------------------
+ * Divisor Latch(LSB) Register
+ */
+#define DLR_REG_OFFSET	0x00U
+
+/*******************************************************************************
+ * DMR register:
+ *------------------------------------------------------------------------------
+ * Divisor Latch(MSB) Register
+ */
+#define DMR_REG_OFFSET	0x04U
+
+/*******************************************************************************
+ * IER register:
+ *------------------------------------------------------------------------------
+ * Interrupt Enable Register
+ */
+#define IER_REG_OFFSET	0x04U
+
+/*------------------------------------------------------------------------------
+ * IER_ERBFI:
+ *   ERBFI field of register IER.
+ *------------------------------------------------------------------------------
+ * Enables Received Data Available Interrupt. 0 - Disabled; 1 - Enabled
+ */
+#define IER_ERBFI_OFFSET   0x04U
+#define IER_ERBFI_MASK     0x01U
+#define IER_ERBFI_SHIFT    0U
+
+/*------------------------------------------------------------------------------
+ * IER_ETBEI:
+ *   ETBEI field of register IER.
+ *------------------------------------------------------------------------------
+ * Enables the Transmitter Holding Register Empty Interrupt. 0 - Disabled; 1 - 
+ * Enabled
+ */
+#define IER_ETBEI_OFFSET   0x04U
+#define IER_ETBEI_MASK     0x02U
+#define IER_ETBEI_SHIFT    1U
+
+/*------------------------------------------------------------------------------
+ * IER_ELSI:
+ *   ELSI field of register IER.
+ *------------------------------------------------------------------------------
+ * Enables the Receiver Line Status Interrupt. 0 - Disabled; 1 - Enabled
+ */
+#define IER_ELSI_OFFSET   0x04U
+#define IER_ELSI_MASK     0x04U
+#define IER_ELSI_SHIFT    2U
+
+/*------------------------------------------------------------------------------
+ * IER_EDSSI:
+ *   EDSSI field of register IER.
+ *------------------------------------------------------------------------------
+ *  Enables the Modem Status Interrupt 0 - Disabled; 1 - Enabled
+ */
+#define IER_EDSSI_OFFSET   0x04U
+#define IER_EDSSI_MASK     0x08U
+#define IER_EDSSI_SHIFT    3U
+
+/*******************************************************************************
+ * IIR register:
+ *------------------------------------------------------------------------------
+ * Interrupt Identification
+ */
+#define IIR_REG_OFFSET	0x08U
+
+/*------------------------------------------------------------------------------
+ * IIR_IIR:
+ *   IIR field of register IIR.
+ *------------------------------------------------------------------------------
+ * Interrupt Identification bits.
+ */
+#define IIR_IIR_OFFSET   0x08U
+#define IIR_IIR_MASK     0x0FU
+#define IIR_IIR_SHIFT    0U
+
+/*------------------------------------------------------------------------------
+ * IIR_IIR:
+ *   IIR field of register IIR.
+ *------------------------------------------------------------------------------
+ * Interrupt Identification bits.
+ */
+
+/*------------------------------------------------------------------------------
+ * IIR_Mode:
+ *   Mode field of register IIR.
+ *------------------------------------------------------------------------------
+ * 11 - FIFO mode
+ */
+#define IIR_MODE_OFFSET   0x08U
+#define IIR_MODE_MASK     0xC0U
+#define IIR_MODE_SHIFT    6U
+
+/*******************************************************************************
+ * FCR register:
+ *------------------------------------------------------------------------------
+ * FIFO Control Register
+ */
+#define FCR_REG_OFFSET	0x08
+
+/*------------------------------------------------------------------------------
+ * FCR_Bit0:
+ *   Bit0 field of register FCR.
+ *------------------------------------------------------------------------------
+ * This bit enables both the TX and RX FIFOs.
+ */
+#define FCR_BIT0_OFFSET   0x08U
+#define FCR_BIT0_MASK     0x01U
+#define FCR_BIT0_SHIFT    0U
+
+#define FCR_ENABLE_OFFSET   0x08U
+#define FCR_ENABLE_MASK     0x01U
+#define FCR_ENABLE_SHIFT    0U
+
+/*------------------------------------------------------------------------------
+ * FCR_Bit1:
+ *   Bit1 field of register FCR.
+ *------------------------------------------------------------------------------
+ * Clears all bytes in the RX FIFO and resets its counter logic. The shift 
+ * register is not cleared.  0 - Disabled; 1 - Enabled
+ */
+#define FCR_BIT1_OFFSET   0x08U
+#define FCR_BIT1_MASK     0x02U
+#define FCR_BIT1_SHIFT    1U
+
+#define FCR_CLEAR_RX_OFFSET   0x08U
+#define FCR_CLEAR_RX_MASK     0x02U
+#define FCR_CLEAR_RX_SHIFT    1U
+
+/*------------------------------------------------------------------------------
+ * FCR_Bit2:
+ *   Bit2 field of register FCR.
+ *------------------------------------------------------------------------------
+ * Clears all bytes in the TX FIFO and resets its counter logic. The shift 
+ * register is not cleared.  0 - Disabled; 1 - Enabled
+ */
+#define FCR_BIT2_OFFSET   0x08U
+#define FCR_BIT2_MASK     0x04U
+#define FCR_BIT2_SHIFT    2U
+
+#define FCR_CLEAR_TX_OFFSET   0x08U
+#define FCR_CLEAR_TX_MASK     0x04U
+#define FCR_CLEAR_TX_SHIFT    2U
+
+/*------------------------------------------------------------------------------
+ * FCR_Bit3:
+ *   Bit3 field of register FCR.
+ *------------------------------------------------------------------------------
+ * Enables RXRDYN and TXRDYN pins when set to 1. Otherwise, they are disabled.
+ */
+#define FCR_BIT3_OFFSET   0x08U
+#define FCR_BIT3_MASK     0x08U
+#define FCR_BIT3_SHIFT    3U
+
+#define FCR_RDYN_EN_OFFSET   0x08U
+#define FCR_RDYN_EN_MASK     0x08U
+#define FCR_RDYN_EN_SHIFT    3U
+
+/*------------------------------------------------------------------------------
+ * FCR_Bit6:
+ *   Bit6 field of register FCR.
+ *------------------------------------------------------------------------------
+ * These bits are used to set the trigger level for the RX FIFO interrupt. RX 
+ * FIFO Trigger Level: 0 - 1; 1 - 4; 2 - 8; 3 - 14
+ */
+#define FCR_BIT6_OFFSET   0x08U
+#define FCR_BIT6_MASK     0xC0U
+#define FCR_BIT6_SHIFT    6U
+
+#define FCR_TRIG_LEVEL_OFFSET   0x08U
+#define FCR_TRIG_LEVEL_MASK     0xC0U
+#define FCR_TRIG_LEVEL_SHIFT    6U
+
+/*******************************************************************************
+ * LCR register:
+ *------------------------------------------------------------------------------
+ * Line Control Register
+ */
+#define LCR_REG_OFFSET	0x0CU
+
+/*------------------------------------------------------------------------------
+ * LCR_WLS:
+ *   WLS field of register LCR.
+ *------------------------------------------------------------------------------
+ * Word Length Select: 00 - 5 bits; 01 - 6 bits; 10 - 7 bits; 11 - 8 bits
+ */
+#define LCR_WLS_OFFSET   0x0CU
+#define LCR_WLS_MASK     0x03U
+#define LCR_WLS_SHIFT    0U
+
+/*------------------------------------------------------------------------------
+ * LCR_STB:
+ *   STB field of register LCR.
+ *------------------------------------------------------------------------------
+ * Number of Stop Bits: 0 - 1 stop bit; 1 - 1½ stop bits when WLS = 00, 2 stop 
+ * bits in other cases
+ */
+#define LCR_STB_OFFSET   0x0CU
+#define LCR_STB_MASK     0x04U
+#define LCR_STB_SHIFT    2U
+
+/*------------------------------------------------------------------------------
+ * LCR_PEN:
+ *   PEN field of register LCR.
+ *------------------------------------------------------------------------------
+ * Parity Enable 0 - Disabled; 1 - Enabled. Parity is added in transmission and 
+ * checked in receiving.
+ */
+#define LCR_PEN_OFFSET   0x0CU
+#define LCR_PEN_MASK     0x08U
+#define LCR_PEN_SHIFT    3U
+
+/*------------------------------------------------------------------------------
+ * LCR_EPS:
+ *   EPS field of register LCR.
+ *------------------------------------------------------------------------------
+ * Even Parity Select 0 - Odd parity; 1 - Even parity
+ */
+#define LCR_EPS_OFFSET   0x0CU
+#define LCR_EPS_MASK     0x10U
+#define LCR_EPS_SHIFT    4U
+
+/*------------------------------------------------------------------------------
+ * LCR_SP:
+ *   SP field of register LCR.
+ *------------------------------------------------------------------------------
+ * Stick Parity 0 - Disabled; 1 - Enabled When stick parity is enabled, it 
+ * works as follows: Bits 4..3, 11 - 0 will be sent as a parity bit, and 
+ * checked in receiving.  01 - 1 will be sent as a parity bit, and checked in 
+ * receiving.
+ */
+#define LCR_SP_OFFSET   0x0CU
+#define LCR_SP_MASK     0x20U
+#define LCR_SP_SHIFT    5U
+
+/*------------------------------------------------------------------------------
+ * LCR_SB:
+ *   SB field of register LCR.
+ *------------------------------------------------------------------------------
+ * Set Break 0 - Disabled 1 - Set break. SOUT is forced to 0. This does not 
+ * have any effect on transmitter logic. The break is disabled by setting the 
+ * bit to 0.
+ */
+#define LCR_SB_OFFSET   0x0CU
+#define LCR_SB_MASK     0x40U
+#define LCR_SB_SHIFT    6U
+
+/*------------------------------------------------------------------------------
+ * LCR_DLAB:
+ *   DLAB field of register LCR.
+ *------------------------------------------------------------------------------
+ * Divisor Latch Access Bit 0 - Disabled. Normal addressing mode in use 1 - 
+ * Enabled. Enables access to the Divisor Latch registers during read or write 
+ * operation to addresses 0 and 1.
+ */
+#define LCR_DLAB_OFFSET   0x0CU
+#define LCR_DLAB_MASK     0x80U
+#define LCR_DLAB_SHIFT    7U
+
+/*******************************************************************************
+ * MCR register:
+ *------------------------------------------------------------------------------
+ * Modem Control Register
+ */
+#define MCR_REG_OFFSET	0x10U
+
+/*------------------------------------------------------------------------------
+ * MCR_DTR:
+ *   DTR field of register MCR.
+ *------------------------------------------------------------------------------
+ * Controls the Data Terminal Ready (DTRn) output.  0 - DTRn <= 1; 1 - DTRn <= 0
+ */
+#define MCR_DTR_OFFSET   0x10U
+#define MCR_DTR_MASK     0x01U
+#define MCR_DTR_SHIFT    0U
+
+/*------------------------------------------------------------------------------
+ * MCR_RTS:
+ *   RTS field of register MCR.
+ *------------------------------------------------------------------------------
+ * Controls the Request to Send (RTSn) output.  0 - RTSn <= 1; 1 - RTSn <= 0
+ */
+#define MCR_RTS_OFFSET   0x10U
+#define MCR_RTS_MASK     0x02U
+#define MCR_RTS_SHIFT    1U
+
+/*------------------------------------------------------------------------------
+ * MCR_Out1:
+ *   Out1 field of register MCR.
+ *------------------------------------------------------------------------------
+ * Controls the Output1 (OUT1n) signal.  0 - OUT1n <= 1; 1 - OUT1n <= 0
+ */
+#define MCR_OUT1_OFFSET   0x10U
+#define MCR_OUT1_MASK     0x04U
+#define MCR_OUT1_SHIFT    2U
+
+/*------------------------------------------------------------------------------
+ * MCR_Out2:
+ *   Out2 field of register MCR.
+ *------------------------------------------------------------------------------
+ * Controls the Output2 (OUT2n) signal.  0 - OUT2n <=1; 1 - OUT2n <=0
+ */
+#define MCR_OUT2_OFFSET   0x10U
+#define MCR_OUT2_MASK     0x08U
+#define MCR_OUT2_SHIFT    3U
+
+/*------------------------------------------------------------------------------
+ * MCR_Loop:
+ *   Loop field of register MCR.
+ *------------------------------------------------------------------------------
+ * Loop enable bit 0 - Disabled; 1 - Enabled. The following happens in loop 
+ * mode: SOUT is set to 1. The SIN, DSRn, CTSn, RIn, and DCDn inputs are 
+ * disconnected.  The output of the Transmitter Shift Register is looped back 
+ * into the Receiver Shift Register. The modem control outputs (DTRn, RTSn, 
+ * OUT1n, and OUT2n) are connected internally to the modem control inputs, and 
+ * the modem control output pins are set at 1. In loopback mode, the 
+ * transmitted data is immediately received, allowing the CPU to check the 
+ * operation of the UART. The interrupts are operating in loop mode.
+ */
+#define MCR_LOOP_OFFSET   0x10U
+#define MCR_LOOP_MASK     0x10U
+#define MCR_LOOP_SHIFT    4U
+
+/*******************************************************************************
+ * LSR register:
+ *------------------------------------------------------------------------------
+ * Line Status Register
+ */
+#define LSR_REG_OFFSET	0x14U
+
+/*------------------------------------------------------------------------------
+ * LSR_DR:
+ *   DR field of register LSR.
+ *------------------------------------------------------------------------------
+ * Data Ready indicator 1 when a data byte has been received and stored in the 
+ * FIFO. DR is cleared to 0 when the CPU reads the data from the FIFO.
+ */
+#define LSR_DR_OFFSET   0x14U
+#define LSR_DR_MASK     0x01U
+#define LSR_DR_SHIFT    0U
+
+/*------------------------------------------------------------------------------
+ * LSR_OE:
+ *   OE field of register LSR.
+ *------------------------------------------------------------------------------
+ * Overrun Error indicator Indicates that the new byte was received before the 
+ * CPU read the byte from the receive buffer, and that the earlier data byte 
+ * was destroyed. OE is cleared when the CPU reads the Line Status Register. If 
+ * the data continues to fill the FIFO beyond the trigger level, an overrun 
+ * error will occur once the FIFO is full and the next character has been 
+ * completely received in the shift register. The character in the shift 
+ * register is overwritten, but it is not transferred to the FIFO.
+ */
+#define LSR_OE_OFFSET   0x14U
+#define LSR_OE_MASK     0x02U
+#define LSR_OE_SHIFT    1U
+
+/*------------------------------------------------------------------------------
+ * LSR_PE:
+ *   PE field of register LSR.
+ *------------------------------------------------------------------------------
+ * Parity Error indicator Indicates that the received byte had a parity error. 
+ * PE is cleared when the CPU reads the Line Status Register. This error is 
+ * revealed to the CPU when its associated character is at the top of the FIFO.
+ */
+#define LSR_PE_OFFSET   0x14U
+#define LSR_PE_MASK     0x04U
+#define LSR_PE_SHIFT    2U
+
+/*------------------------------------------------------------------------------
+ * LSR_FE:
+ *   FE field of register LSR.
+ *------------------------------------------------------------------------------
+ *  Framing Error indicator Indicates that the received byte did not have a 
+ * valid Stop bit. FE is cleared when the CPU reads the Line Status Register. 
+ * The UART will try to re-synchronize after a framing error. To do this, it
+ * assumes that the framing error was due to the next start bit, so it samples 
+ * this start bit twice, and then starts receiving the data.  This error is 
+ * revealed to the CPU when its associated character is at the top of the FIFO.
+ */
+#define LSR_FE_OFFSET   0x14U
+#define LSR_FE_MASK     0x08U
+#define LSR_FE_SHIFT    3U
+
+/*------------------------------------------------------------------------------
+ * LSR_BI:
+ *   BI field of register LSR.
+ *------------------------------------------------------------------------------
+ * Break Interrupt indicator Indicates that the received data is at 0 longer 
+ * than a full word transmission time (start bit + data bits + parity + stop 
+ * bits). BI is cleared when the CPU reads the Line Status Register. This error 
+ * is revealed to the CPU when its associated character is at the top of the 
+ * FIFO. When break occurs, only one zero character is loaded into the FIFO.
+ */
+#define LSR_BI_OFFSET   0x14U
+#define LSR_BI_MASK     0x10U
+#define LSR_BI_SHIFT    4U
+
+/*------------------------------------------------------------------------------
+ * LSR_THRE:
+ *   THRE field of register LSR.
+ *------------------------------------------------------------------------------
+ *  Transmitter Holding Register Empty indicator Indicates that the UART is 
+ * ready to transmit a new data byte. THRE causes an interrupt to the CPU when 
+ * bit 1 (ETBEI) in the Interrupt Enable Register is 1.  This bit is set when 
+ * the TX FIFO is empty. It is cleared when at least one byte is written to the 
+ * TX FIFO.
+ */
+#define LSR_THRE_OFFSET   0x14U
+#define LSR_THRE_MASK     0x20U
+#define LSR_THRE_SHIFT    5U
+
+/*------------------------------------------------------------------------------
+ * LSR_TEMT:
+ *   TEMT field of register LSR.
+ *------------------------------------------------------------------------------
+ *  Transmitter Empty indicator This bit is set to 1 when both the transmitter 
+ * FIFO and shift registers are empty.
+ */
+#define LSR_TEMT_OFFSET   0x14U
+#define LSR_TEMT_MASK     0x40U
+#define LSR_TEMT_SHIFT    6U
+
+/*------------------------------------------------------------------------------
+ * LSR_FIER:
+ *   FIER field of register LSR.
+ *------------------------------------------------------------------------------
+ *  This bit is set when there is at least one parity error, framing error, or 
+ * break indication in the FIFO. FIER is cleared when the CPU reads the LSR if 
+ * there are no subsequent errors in the FIFO.
+ */
+#define LSR_FIER_OFFSET   0x14U
+#define LSR_FIER_MASK     0x80U
+#define LSR_FIER_SHIFT    7U
+
+/*******************************************************************************
+ * MSR register:
+ *------------------------------------------------------------------------------
+ * Modem Status Register
+ */
+#define MSR_REG_OFFSET	0x18U
+
+/*------------------------------------------------------------------------------
+ * MSR_DCTS:
+ *   DCTS field of register MSR.
+ *------------------------------------------------------------------------------
+ * Delta Clear to Send indicator.  Indicates that the CTSn input has changed 
+ * state since the last time it was read by the CPU.
+ */
+#define MSR_DCTS_OFFSET   0x18U
+#define MSR_DCTS_MASK     0x01U
+#define MSR_DCTS_SHIFT    0U
+
+/*------------------------------------------------------------------------------
+ * MSR_DDSR:
+ *   DDSR field of register MSR.
+ *------------------------------------------------------------------------------
+ * Delta Data Set Ready indicator Indicates that the DSRn input has changed 
+ * state since the last time it was read by the CPU.
+ */
+#define MSR_DDSR_OFFSET   0x18U
+#define MSR_DDSR_MASK     0x02U
+#define MSR_DDSR_SHIFT    1U
+
+/*------------------------------------------------------------------------------
+ * MSR_TERI:
+ *   TERI field of register MSR.
+ *------------------------------------------------------------------------------
+ * Trailing Edge of Ring Indicator detector. Indicates that RI input has 
+ * changed from 0 to 1.
+ */
+#define MSR_TERI_OFFSET   0x18U
+#define MSR_TERI_MASK     0x04U
+#define MSR_TERI_SHIFT    2U
+
+/*------------------------------------------------------------------------------
+ * MSR_DDCD:
+ *   DDCD field of register MSR.
+ *------------------------------------------------------------------------------
+ * Delta Data Carrier Detect indicator Indicates that DCD input has changed 
+ * state.  NOTE: Whenever bit 0, 1, 2, or 3 is set to 1, a Modem Status 
+ * Interrupt is generated.
+ */
+#define MSR_DDCD_OFFSET   0x18U
+#define MSR_DDCD_MASK     0x08U
+#define MSR_DDCD_SHIFT    3U
+
+/*------------------------------------------------------------------------------
+ * MSR_CTS:
+ *   CTS field of register MSR.
+ *------------------------------------------------------------------------------
+ * Clear to Send The complement of the CTSn input. When bit 4 of the Modem 
+ * Control Register (MCR) is set to 1 (loop), this bit is equivalent to DTR in 
+ * the MCR.
+ */
+#define MSR_CTS_OFFSET   0x18U
+#define MSR_CTS_MASK     0x10U
+#define MSR_CTS_SHIFT    4U
+
+/*------------------------------------------------------------------------------
+ * MSR_DSR:
+ *   DSR field of register MSR.
+ *------------------------------------------------------------------------------
+ * Data Set Ready The complement of the DSR input. When bit 4 of the MCR is set 
+ * to 1 (loop), this bit is equivalent to RTSn in the MCR.
+ */
+#define MSR_DSR_OFFSET   0x18U
+#define MSR_DSR_MASK     0x20U
+#define MSR_DSR_SHIFT    5U
+
+/*------------------------------------------------------------------------------
+ * MSR_RI:
+ *   RI field of register MSR.
+ *------------------------------------------------------------------------------
+ * Ring Indicator The complement of the RIn input. When bit 4 of the MCR is set 
+ * to 1 (loop), this bit is equivalent to OUT1 in the MCR.
+ */
+#define MSR_RI_OFFSET   0x18U
+#define MSR_RI_MASK     0x40U
+#define MSR_RI_SHIFT    6U
+
+/*------------------------------------------------------------------------------
+ * MSR_DCD:
+ *   DCD field of register MSR.
+ *------------------------------------------------------------------------------
+ * Data Carrier Detect The complement of DCDn input. When bit 4 of the MCR is 
+ * set to 1 (loop), this bit is equivalent to OUT2 in the MCR.
+ */
+#define MSR_DCD_OFFSET   0x18U
+#define MSR_DCD_MASK     0x80U
+#define MSR_DCD_SHIFT    7U
+
+/*******************************************************************************
+ * SR register:
+ *------------------------------------------------------------------------------
+ * Scratch Register
+ */
+#define SR_REG_OFFSET	0x1CU
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CORE_16550_REGISTERS_H_*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/Core16550/core_16550.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/Core16550/core_16550.c
new file mode 100644
index 0000000..ca735e6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/Core16550/core_16550.c
@@ -0,0 +1,865 @@
+/*******************************************************************************
+ * (c) Copyright 2007-2015 Microsemi SoC Products Group. All rights reserved.
+ *
+ * Core16550 driver implementation. See file "core_16550.h" for a
+ * description of the functions implemented in this file.
+ *
+ * SVN $Revision: 7963 $
+ * SVN $Date: 2015-10-09 17:58:21 +0530 (Fri, 09 Oct 2015) $
+ */
+#include "hal.h"
+#include "core_16550.h"
+#include "core16550_regs.h"
+#include "hal_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * Definitions for transmitter states
+ */
+#define TX_COMPLETE     0x00U
+
+/*******************************************************************************
+ * Definition for transmitter FIFO size
+ */
+#define TX_FIFO_SIZE    16U
+
+/*******************************************************************************
+ * Default receive interrupt trigger level
+ */
+#define DEFAULT_RX_TRIG_LEVEL  ((uint8_t)UART_16550_FIFO_SINGLE_BYTE)
+
+/*******************************************************************************
+ * Receiver error status mask and shift offset
+ */
+#define STATUS_ERROR_MASK   ( LSR_OE_MASK | LSR_PE_MASK |  \
+                              LSR_FE_MASK | LSR_BI_MASK | LSR_FIER_MASK)
+
+/*******************************************************************************
+ * Definitions for invalid parameters with proper type
+ */
+#define INVALID_INTERRUPT   0U
+#define INVALID_IRQ_HANDLER ( (uart_16550_irq_handler_t) 0 )
+
+/*******************************************************************************
+ * Possible values for Interrupt Identification Register Field.
+ */
+#define IIRF_MODEM_STATUS       0x00U
+#define IIRF_THRE               0x02U
+#define IIRF_RX_DATA            0x04U
+#define IIRF_RX_LINE_STATUS     0x06U
+#define IIRF_DATA_TIMEOUT       0x0CU
+
+/*******************************************************************************
+ * Null parameters with appropriate type definitions
+ */
+#define NULL_ADDR       ( ( addr_t ) 0 )
+#define NULL_INSTANCE   ( ( uart_16550_instance_t * ) 0 )
+#define NULL_BUFF       ( ( uint8_t * ) 0 )
+
+/*******************************************************************************
+ * Possible states for different register bit fields
+ */
+enum {
+    DISABLE = 0U,
+    ENABLE  = 1U
+};
+
+/*******************************************************************************
+ * Static function declarations
+ */
+static void default_tx_handler(uart_16550_instance_t * this_uart);
+
+/*******************************************************************************
+ * Public function definitions
+ */
+
+/***************************************************************************//**
+ * UART_16550_init.
+ * See core_16550.h for details of how to use this function.
+ */
+void
+UART_16550_init
+(
+    uart_16550_instance_t* this_uart,
+    addr_t base_addr,
+    uint16_t baud_value,
+    uint8_t line_config
+)
+{
+#ifndef NDEBUG
+    uint8_t dbg1;
+    uint8_t dbg2;
+#endif
+    uint8_t fifo_config;
+    uint8_t temp;
+
+    HAL_ASSERT( base_addr != NULL_ADDR );
+    HAL_ASSERT( this_uart != NULL_INSTANCE );
+
+    if( ( base_addr != NULL_ADDR ) && ( this_uart != NULL_INSTANCE ) )
+    {
+        /* disable interrupts */
+        HAL_set_8bit_reg(base_addr, IER, DISABLE);
+
+        /* reset divisor latch */
+        HAL_set_8bit_reg_field(base_addr, LCR_DLAB, ENABLE);
+#ifndef NDEBUG
+        dbg1 =  HAL_get_8bit_reg_field(base_addr, LCR_DLAB );
+        HAL_ASSERT( dbg1 == ENABLE );
+#endif
+        /* MSB of baud value */
+        temp = (uint8_t)(baud_value >> 8);
+        HAL_set_8bit_reg(base_addr, DMR, temp );
+        /* LSB of baud value */
+        HAL_set_8bit_reg(base_addr, DLR, ( (uint8_t)baud_value ) );
+#ifndef NDEBUG
+        dbg1 =  HAL_get_8bit_reg(base_addr, DMR );
+        dbg2 =  HAL_get_8bit_reg(base_addr, DLR );
+        HAL_ASSERT( ( ( ( (uint16_t) dbg1 ) << 8 ) | dbg2 ) == baud_value );
+#endif
+        /* reset divisor latch */
+        HAL_set_8bit_reg_field(base_addr, LCR_DLAB, DISABLE);
+#ifndef NDEBUG
+        dbg1 =  HAL_get_8bit_reg_field(base_addr, LCR_DLAB );
+        HAL_ASSERT( dbg1 == DISABLE );
+#endif
+        /* set the line control register (bit length, stop bits, parity) */
+        HAL_set_8bit_reg( base_addr, LCR, line_config );
+#ifndef NDEBUG
+        dbg1 =  HAL_get_8bit_reg(base_addr, LCR );
+        HAL_ASSERT( dbg1 == line_config)
+#endif
+        /* Enable and configure the RX and TX FIFOs. */
+        fifo_config = ((uint8_t)(DEFAULT_RX_TRIG_LEVEL << FCR_TRIG_LEVEL_SHIFT) |
+                                 FCR_RDYN_EN_MASK | FCR_CLEAR_RX_MASK |
+                                 FCR_CLEAR_TX_MASK | FCR_ENABLE_MASK );
+        HAL_set_8bit_reg( base_addr, FCR, fifo_config );
+
+        /* disable loopback */
+        HAL_set_8bit_reg_field( base_addr, MCR_LOOP, DISABLE );
+#ifndef NDEBUG
+        dbg1 =  HAL_get_8bit_reg_field(base_addr, MCR_LOOP);
+        HAL_ASSERT( dbg1 == DISABLE );
+#endif
+
+        /* Instance setup */
+        this_uart->base_address = base_addr;
+        this_uart->tx_buffer    = NULL_BUFF;
+        this_uart->tx_buff_size = TX_COMPLETE;
+        this_uart->tx_idx       = 0U;
+        this_uart->tx_handler   = default_tx_handler;
+
+        this_uart->rx_handler  = ( (uart_16550_irq_handler_t) 0 );
+        this_uart->linests_handler  = ( (uart_16550_irq_handler_t) 0 );
+        this_uart->modemsts_handler = ( (uart_16550_irq_handler_t) 0 );
+        this_uart->status = 0U;
+    }
+}
+
+/***************************************************************************//**
+ * UART_16550_polled_tx.
+ * See core_16550.h for details of how to use this function.
+ */
+void
+UART_16550_polled_tx
+(
+    uart_16550_instance_t * this_uart,
+    const uint8_t * pbuff,
+    uint32_t tx_size
+)
+{
+    uint32_t char_idx = 0U;
+    uint32_t size_sent;
+    uint8_t status;
+
+    HAL_ASSERT( this_uart != NULL_INSTANCE );
+    HAL_ASSERT( pbuff != NULL_BUFF );
+    HAL_ASSERT( tx_size > 0U );
+
+    if( ( this_uart != NULL_INSTANCE ) &&
+        ( pbuff != NULL_BUFF ) &&
+        ( tx_size > 0U ) )
+    {
+        /* Remain in this loop until the entire input buffer
+         * has been transferred to the UART.
+         */
+        do {
+            /* Read the Line Status Register and update the sticky record */
+            status = HAL_get_8bit_reg( this_uart->base_address, LSR );
+            this_uart->status |= status;
+
+            /* Check if TX FIFO is empty. */
+            if( status & LSR_THRE_MASK )
+            {
+                uint32_t fill_size = TX_FIFO_SIZE;
+
+                /* Calculate the number of bytes to transmit. */
+                if ( tx_size < TX_FIFO_SIZE )
+                {
+                    fill_size = tx_size;
+                }
+
+                /* Fill the TX FIFO with the calculated the number of bytes. */
+                for ( size_sent = 0U; size_sent < fill_size; ++size_sent )
+                {
+                    /* Send next character in the buffer. */
+                    HAL_set_8bit_reg( this_uart->base_address, THR,
+                                      (uint_fast8_t)pbuff[char_idx++]);
+                }
+
+                /* Calculate the number of untransmitted bytes remaining. */
+                tx_size -= size_sent;
+            }
+        } while ( tx_size );
+    }
+}
+
+/***************************************************************************//**
+ * UART_16550_polled_tx_string.
+ * See core_16550.h for details of how to use this function.
+ */
+void
+UART_16550_polled_tx_string
+(
+    uart_16550_instance_t * this_uart,
+    const uint8_t * p_sz_string
+)
+{
+    uint32_t char_idx = 0U;
+    uint32_t fill_size;
+    uint_fast8_t data_byte;
+    uint8_t status;
+
+    HAL_ASSERT( this_uart != NULL_INSTANCE );
+    HAL_ASSERT( p_sz_string != NULL_BUFF );
+
+    if( ( this_uart != NULL_INSTANCE ) && ( p_sz_string != NULL_BUFF ) )
+    {
+        char_idx = 0U;
+
+        /* Get the first data byte from the input buffer */
+        data_byte = (uint_fast8_t)p_sz_string[char_idx];
+
+        /* First check for the NULL terminator byte.
+         * Then remain in this loop until the entire string in the input buffer
+         * has been transferred to the UART.
+         */
+        while ( 0U != data_byte )
+        {
+            /* Wait until TX FIFO is empty. */
+            do {
+                status = HAL_get_8bit_reg( this_uart->base_address,LSR);
+                this_uart->status |= status;
+            } while ( !( status & LSR_THRE_MASK ) );
+
+            /* Send bytes from the input buffer until the TX FIFO is full
+             * or we reach the NULL terminator byte.
+             */
+            fill_size = 0U;
+            while ( (0U != data_byte) && (fill_size < TX_FIFO_SIZE) )
+            {
+                /* Send the data byte */
+                HAL_set_8bit_reg( this_uart->base_address, THR, data_byte );
+                ++fill_size;
+                char_idx++;
+                /* Get the next data byte from the input buffer */
+                data_byte = (uint_fast8_t)p_sz_string[char_idx];
+            }
+        }
+    }
+}
+
+
+/***************************************************************************//**
+ * UART_16550_irq_tx.
+ * See core_16550.h for details of how to use this function.
+ */
+void
+UART_16550_irq_tx
+(
+    uart_16550_instance_t * this_uart,
+    const uint8_t * pbuff,
+    uint32_t tx_size
+)
+{
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+    HAL_ASSERT( pbuff != NULL_BUFF )
+    HAL_ASSERT( tx_size > 0U )
+
+    if( ( this_uart != NULL_INSTANCE ) &&
+        ( pbuff != NULL_BUFF ) &&
+        ( tx_size > 0U ) )
+    {
+        /*Initialize the UART instance with
+          parameters required for transmission.*/
+        this_uart->tx_buffer = pbuff;
+        this_uart->tx_buff_size = tx_size;
+        /* char_idx; */
+        this_uart->tx_idx = 0U;
+        /* assign handler for default data transmission */
+        this_uart->tx_handler = default_tx_handler;
+
+        /* enables TX interrupt */
+        HAL_set_8bit_reg_field(this_uart->base_address, IER_ETBEI, ENABLE);
+    }
+}
+
+/***************************************************************************//**
+ * UART_16550_tx_complete.
+ * See core_16550.h for details of how to use this function.
+ */
+int8_t
+UART_16550_tx_complete
+(
+    uart_16550_instance_t * this_uart
+)
+{
+    int8_t returnvalue = 0;
+    uint8_t status = 0U;
+
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+
+    if( this_uart != NULL_INSTANCE )
+    {
+        status = HAL_get_8bit_reg(this_uart->base_address,LSR);
+        this_uart->status |= status;
+
+        if( ( this_uart->tx_buff_size == TX_COMPLETE ) &&
+                             ( status & LSR_TEMT_MASK ) )
+        {
+            returnvalue = (int8_t)1;
+        }
+    }
+    return returnvalue;
+}
+
+
+/***************************************************************************//**
+ * UART_16550_get_rx.
+ * See core_16550.h for details of how to use this function.
+ */
+size_t
+UART_16550_get_rx
+(
+    uart_16550_instance_t * this_uart,
+    uint8_t * rx_buff,
+    size_t buff_size
+)
+{
+    uint8_t status;
+    size_t rx_size = 0U;
+
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+    HAL_ASSERT( rx_buff != (uint8_t *)0 )
+    HAL_ASSERT( buff_size > 0U )
+
+    if( ( this_uart != NULL_INSTANCE ) &&
+        ( rx_buff != (uint8_t *)0 ) &&
+        ( buff_size > 0U ) )
+    {
+        status = HAL_get_8bit_reg( this_uart->base_address, LSR );
+        this_uart->status |= status;
+        while ( ((status & LSR_DR_MASK) != 0U) && ( rx_size < buff_size ) )
+        {
+            rx_buff[rx_size] = HAL_get_8bit_reg( this_uart->base_address, RBR );
+            rx_size++;
+            status = HAL_get_8bit_reg( this_uart->base_address, LSR );
+            this_uart->status |= status;
+        }
+    }
+    return rx_size;
+}
+
+/***************************************************************************//**
+ * UART_16550_isr.
+ * See core_16550.h for details of how to use this function.
+ */
+void
+UART_16550_isr
+(
+    uart_16550_instance_t * this_uart
+)
+{
+    uint8_t iirf;
+
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+
+    if(this_uart != NULL_INSTANCE )
+    {
+        iirf = HAL_get_8bit_reg_field( this_uart->base_address, IIR_IIR );
+
+        switch ( iirf )
+        {
+            /* Modem status interrupt */
+            case IIRF_MODEM_STATUS:
+            {
+                if( INVALID_IRQ_HANDLER != this_uart->modemsts_handler  )
+                {
+                    HAL_ASSERT( INVALID_IRQ_HANDLER != this_uart->modemsts_handler );
+                    if( INVALID_IRQ_HANDLER != this_uart->modemsts_handler )
+                    {
+                        (*(this_uart->modemsts_handler))(this_uart);
+                    }
+                }
+            }
+            break;
+            /* Transmitter Holding Register Empty interrupt */
+            case IIRF_THRE:
+            {
+                HAL_ASSERT( INVALID_IRQ_HANDLER != this_uart->tx_handler );
+                if ( INVALID_IRQ_HANDLER != this_uart->tx_handler )
+                {
+                    (*(this_uart->tx_handler))(this_uart);
+                }
+            }
+            break;
+            /* Received Data Available interrupt */
+            case IIRF_RX_DATA:
+            case IIRF_DATA_TIMEOUT:
+            {
+                HAL_ASSERT( INVALID_IRQ_HANDLER != this_uart->rx_handler );
+                if ( INVALID_IRQ_HANDLER != this_uart->rx_handler )
+                {
+                    (*(this_uart->rx_handler))(this_uart);
+                }
+            }
+            break;
+            /* Line status interrupt */
+            case IIRF_RX_LINE_STATUS:
+            {
+                HAL_ASSERT( INVALID_IRQ_HANDLER != this_uart->linests_handler );
+                if ( INVALID_IRQ_HANDLER != this_uart->linests_handler )
+                {
+                    (*(this_uart->linests_handler))(this_uart);
+                }
+            }
+            break;
+            /* Unidentified interrupt */
+            default:
+            {
+                HAL_ASSERT( INVALID_INTERRUPT )
+            }
+        }
+    }
+}
+
+/***************************************************************************//**
+ * UART_16550_set_rx_handler.
+ * See core_16550.h for details of how to use this function.
+ */
+void
+UART_16550_set_rx_handler
+(
+    uart_16550_instance_t * this_uart,
+    uart_16550_irq_handler_t handler,
+    uart_16550_rx_trig_level_t trigger_level
+)
+{
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+    HAL_ASSERT( handler != INVALID_IRQ_HANDLER)
+    HAL_ASSERT( trigger_level < UART_16550_FIFO_INVALID_TRIG_LEVEL)
+
+    if( ( this_uart != NULL_INSTANCE ) &&
+        ( handler != INVALID_IRQ_HANDLER) &&
+        ( trigger_level < UART_16550_FIFO_INVALID_TRIG_LEVEL) )
+    {
+        this_uart->rx_handler = handler;
+
+        /* Set the receive interrupt trigger level. */
+        HAL_set_8bit_reg_field( this_uart->base_address,
+                            FCR_TRIG_LEVEL, trigger_level );
+
+        /* Enable receive interrupt. */
+        HAL_set_8bit_reg_field( this_uart->base_address, IER_ERBFI, ENABLE );
+    }
+}
+
+/***************************************************************************//**
+ * UART_16550_set_loopback.
+ * See core_16550.h for details of how to use this function.
+ */
+void
+UART_16550_set_loopback
+(
+    uart_16550_instance_t * this_uart,
+    uart_16550_loopback_t loopback
+)
+{
+    HAL_ASSERT( this_uart != NULL_INSTANCE );
+    HAL_ASSERT( loopback < UART_16550_INVALID_LOOPBACK );
+
+    if( ( this_uart != NULL_INSTANCE ) &&
+        ( loopback < UART_16550_INVALID_LOOPBACK ) )
+    {
+        if ( loopback == UART_16550_LOOPBACK_OFF )
+        {
+            HAL_set_8bit_reg_field( this_uart->base_address,
+                                    MCR_LOOP,
+                                    DISABLE );
+        }
+        else
+        {
+            HAL_set_8bit_reg_field( this_uart->base_address,
+                                    MCR_LOOP,
+                                    ENABLE );
+        }
+    }
+}
+
+/***************************************************************************//**
+ * UART_16550_get_rx_status.
+ * See core_16550.h for details of how to use this function.
+ */
+uint8_t
+UART_16550_get_rx_status
+(
+    uart_16550_instance_t * this_uart
+)
+{
+    uint8_t status = UART_16550_INVALID_PARAM;
+    HAL_ASSERT( this_uart != NULL_INSTANCE );
+
+    if( ( this_uart != NULL_INSTANCE ) )
+    {
+        /*
+         * Bit 1 - Overflow error status
+         * Bit 2 - Parity error status
+         * Bit 3 - Frame error status
+         * Bit 4 - Break interrupt indicator
+         * Bit 7 - FIFO data error status
+         */
+        this_uart->status |= HAL_get_8bit_reg( this_uart->base_address, LSR );
+        status = ( this_uart->status & STATUS_ERROR_MASK );
+        /*
+         * Clear the sticky status for this instance.
+         */
+        this_uart->status = (uint8_t)0;
+    }
+    return status;
+}
+
+/***************************************************************************//**
+ * UART_16550_get_modem_status.
+ * See core_16550.h for details of how to use this function.
+ */
+uint8_t
+UART_16550_get_modem_status
+(
+    uart_16550_instance_t * this_uart
+)
+{
+    uint8_t status = UART_16550_NO_ERROR;
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+
+    if( ( this_uart != NULL_INSTANCE ) )
+    {
+        /*
+         * Extract UART error status and place in lower bits of "status".
+         * Bit 0 - Delta Clear to Send Indicator
+         * Bit 1 - Delta Clear to Receive Indicator
+         * Bit 2 - Trailing edge of Ring Indicator detector
+         * Bit 3 - Delta Data Carrier Detect indicator
+         * Bit 4 - Clear To Send
+         * Bit 5 - Data Set Ready
+         * Bit 6 - Ring Indicator
+         * Bit 7 - Data Carrier Detect
+         */
+        status = HAL_get_8bit_reg( this_uart->base_address, MSR );
+    }
+    return status;
+}
+
+/***************************************************************************//**
+ * Default TX interrupt handler to automatically transmit data from
+ * user assgined TX buffer.
+ */
+static void
+default_tx_handler
+(
+    uart_16550_instance_t * this_uart
+)
+{
+    uint8_t status;
+
+    HAL_ASSERT( NULL_INSTANCE != this_uart )
+
+    if ( this_uart != NULL_INSTANCE )
+    {
+        HAL_ASSERT( NULL_BUFF != this_uart->tx_buffer )
+        HAL_ASSERT( 0U != this_uart->tx_buff_size )
+
+        if ( ( this_uart->tx_buffer != NULL_BUFF ) &&
+             ( 0U != this_uart->tx_buff_size ) )
+        {
+            /* Read the Line Status Register and update the sticky record. */
+            status = HAL_get_8bit_reg( this_uart->base_address,LSR);
+            this_uart->status |= status;
+    
+            /*
+             * This function should only be called as a result of a THRE interrupt.
+             * Verify that this is true before proceeding to transmit data.
+             */
+            if ( status & LSR_THRE_MASK )
+            {
+                uint32_t size_sent = 0U;
+                uint32_t fill_size = TX_FIFO_SIZE;
+                uint32_t tx_remain = this_uart->tx_buff_size - this_uart->tx_idx;
+    
+                /* Calculate the number of bytes to transmit. */
+                if ( tx_remain < TX_FIFO_SIZE )
+                {
+                    fill_size = tx_remain;
+                }
+    
+                /* Fill the TX FIFO with the calculated the number of bytes. */
+                for ( size_sent = 0U; size_sent < fill_size; ++size_sent )
+                {
+                    /* Send next character in the buffer. */
+                    HAL_set_8bit_reg( this_uart->base_address, THR,
+                            (uint_fast8_t)this_uart->tx_buffer[this_uart->tx_idx]);
+                    ++this_uart->tx_idx;
+                }
+            }
+    
+            /* Flag Tx as complete if all data has been pushed into the Tx FIFO. */
+            if ( this_uart->tx_idx == this_uart->tx_buff_size )
+            {
+                this_uart->tx_buff_size = TX_COMPLETE;
+                /* disables TX interrupt */
+                HAL_set_8bit_reg_field( this_uart->base_address,
+                                        IER_ETBEI, DISABLE);
+            }
+        }
+    }
+}
+
+/***************************************************************************//**
+ * UART_16550_enable_irq.
+ * See core_16550.h for details of how to use this function.
+ */
+void
+UART_16550_enable_irq
+(
+    uart_16550_instance_t * this_uart,
+    uint8_t irq_mask
+)
+{
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+
+    if( this_uart != NULL_INSTANCE )
+    {
+        /* irq_mask encoding: 1- enable
+         * bit 0 - Receive Data Available Interrupt
+         * bit 1 - Transmitter Holding  Register Empty Interrupt
+         * bit 2 - Receiver Line Status Interrupt
+         * bit 3 - Modem Status Interrupt
+         */
+        /* read present interrupts for enabled ones*/
+        irq_mask |= HAL_get_8bit_reg( this_uart->base_address, IER );
+        /* Enable interrupts */
+        HAL_set_8bit_reg( this_uart->base_address, IER, irq_mask );
+    }
+}
+
+/***************************************************************************//**
+ * UART_16550_disable_irq.
+ * See core_16550.h for details of how to use this function.
+ */
+void
+UART_16550_disable_irq
+(
+    uart_16550_instance_t * this_uart,
+    uint8_t irq_mask
+)
+{
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+
+    if( this_uart != NULL_INSTANCE )
+    {
+        /* irq_mask encoding:  1 - disable
+         * bit 0 - Receive Data Available Interrupt
+         * bit 1 - Transmitter Holding  Register Empty Interrupt
+         * bit 2 - Receiver Line Status Interrupt
+         * bit 3 - Modem Status Interrupt
+         */
+        /* read present interrupts for enabled ones */
+        irq_mask = (( (uint8_t)~irq_mask ) & 
+                    HAL_get_8bit_reg( this_uart->base_address, IER ));
+        /* Disable interrupts */
+        HAL_set_8bit_reg( this_uart->base_address, IER, irq_mask );
+    }
+}
+
+/***************************************************************************//**
+ * UART_16550_set_rxstatus_handler.
+ * See core_16550.h for details of how to use this function.
+ */
+void
+UART_16550_set_rxstatus_handler
+(
+    uart_16550_instance_t * this_uart,
+    uart_16550_irq_handler_t handler
+)
+{
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+    HAL_ASSERT( handler != INVALID_IRQ_HANDLER)
+
+    if( ( this_uart != NULL_INSTANCE ) &&
+        ( handler != INVALID_IRQ_HANDLER) )
+    {
+        this_uart->linests_handler = handler;
+        /* Enable receiver line status interrupt. */
+        HAL_set_8bit_reg_field( this_uart->base_address, IER_ELSI, ENABLE );
+    }
+}
+
+/***************************************************************************//**
+ * UART_16550_set_tx_handler.
+ * See core_16550.h for details of how to use this function.
+ */
+void
+UART_16550_set_tx_handler
+(
+    uart_16550_instance_t * this_uart,
+    uart_16550_irq_handler_t handler
+)
+{
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+    HAL_ASSERT( handler != INVALID_IRQ_HANDLER)
+
+    if( ( this_uart != NULL_INSTANCE ) &&
+        ( handler != INVALID_IRQ_HANDLER) )
+    {
+        this_uart->tx_handler = handler;
+
+        /* Make TX buffer info invalid */
+        this_uart->tx_buffer = NULL_BUFF;
+        this_uart->tx_buff_size = 0U;
+
+        /* Enable transmitter holding register Empty interrupt. */
+        HAL_set_8bit_reg_field( this_uart->base_address, IER_ETBEI, ENABLE );
+    }
+}
+
+/***************************************************************************//**
+ * UART_16550_set_modemstatus_handler.
+ * See core_16550.h for details of how to use this function.
+ */
+void
+UART_16550_set_modemstatus_handler
+(
+    uart_16550_instance_t * this_uart,
+    uart_16550_irq_handler_t handler
+)
+{
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+    HAL_ASSERT( handler != INVALID_IRQ_HANDLER)
+
+    if( ( this_uart != NULL_INSTANCE ) &&
+        ( handler != INVALID_IRQ_HANDLER) )
+    {
+        this_uart->modemsts_handler = handler;
+        /* Enable modem status interrupt. */
+        HAL_set_8bit_reg_field( this_uart->base_address, IER_EDSSI, ENABLE );
+    }
+}
+
+/***************************************************************************//**
+ * UART_16550_fill_tx_fifo.
+ * See core_16550.h for details of how to use this function.
+ */
+size_t
+UART_16550_fill_tx_fifo
+(
+    uart_16550_instance_t * this_uart,
+    const uint8_t * tx_buffer,
+    size_t tx_size
+)
+{
+    uint8_t status;
+    size_t size_sent = 0U;
+
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+    HAL_ASSERT( tx_buffer != NULL_BUFF )
+    HAL_ASSERT( tx_size > 0U )
+
+    /* Fill the UART's Tx FIFO until the FIFO is full or the complete input
+     * buffer has been written. */
+    if( (this_uart != NULL_INSTANCE) &&
+        (tx_buffer != NULL_BUFF)   &&
+        (tx_size > 0U) )
+    {
+        /* Read the Line Status Register and update the sticky record. */
+        status = HAL_get_8bit_reg( this_uart->base_address, LSR );
+        this_uart->status |= status;
+
+        /* Check if TX FIFO is empty. */
+        if( status & LSR_THRE_MASK )
+        {
+            uint32_t fill_size = TX_FIFO_SIZE;
+
+            /* Calculate the number of bytes to transmit. */
+            if ( tx_size < TX_FIFO_SIZE )
+            {
+                fill_size = tx_size;
+            }
+
+            /* Fill the TX FIFO with the calculated the number of bytes. */
+            for ( size_sent = 0U; size_sent < fill_size; ++size_sent )
+            {
+                /* Send next character in the buffer. */
+                HAL_set_8bit_reg( this_uart->base_address, THR,
+                                  (uint_fast8_t)tx_buffer[size_sent]);
+            }
+        }
+    }
+    return size_sent;
+}
+
+/***************************************************************************//**
+ * UART_16550_get_tx_status.
+ * See core_16550.h for details of how to use this function.
+ */
+uint8_t
+UART_16550_get_tx_status
+(
+    uart_16550_instance_t * this_uart
+)
+{
+    uint8_t status = UART_16550_TX_BUSY;
+    HAL_ASSERT( this_uart != NULL_INSTANCE );
+
+    if( ( this_uart != NULL_INSTANCE ) )
+    {
+        /* Read the Line Status Register and update the sticky record. */
+        status = HAL_get_8bit_reg( this_uart->base_address, LSR );
+        this_uart->status |= status;
+        /*
+         * Extract the transmit status bits from the UART's Line Status Register.
+         * Bit 5 - Transmitter Holding Register/FIFO Empty (THRE) status. (If = 1, TX FIFO is empty)
+         * Bit 6 - Transmitter Empty (TEMT) status. (If = 1, both TX FIFO and shift register are empty)
+         */
+        status &= ( LSR_THRE_MASK | LSR_TEMT_MASK );
+    }
+    return status;
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/Core16550/core_16550.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/Core16550/core_16550.h
new file mode 100644
index 0000000..98b1f16
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/Core16550/core_16550.h
@@ -0,0 +1,1264 @@
+/*******************************************************************************
+ * (c) Copyright 2007-2015 Microsemi SoC Products Group. All rights reserved.
+ *
+ * This file contains the application programming interface for the Core16550
+ * bare metal driver.
+ *
+ * SVN $Revision: 7963 $
+ * SVN $Date: 2015-10-09 17:58:21 +0530 (Fri, 09 Oct 2015) $
+ */
+/*=========================================================================*//**
+  @mainpage Core16550 Bare Metal Driver.
+
+  @section intro_sec Introduction
+  The Core16550 is an implementation of the Universal Asynchronous
+  Receiver/Transmitter aimed at complete compliance to standard 16550 UART.
+  The Core16550 bare metal software driver is designed for use in systems
+  with no operating system.
+
+  The Core16550 driver provides functions for polled and interrupt driven
+  transmitting and receiving. It also provides functions for reading the
+  values from different status registers, enabling and disabling interrupts
+  at Core16550 level. The Core16550 driver is provided as C source code.
+
+  @section driver_configuration Driver Configuration
+  Your application software should configure the Core16550 driver through
+  calls to the UART_16550_init() function for each Core16550 instance in
+  the hardware design. The configuration parameters include the Core16550
+  hardware instance base address and other runtime parameters, such as baud
+  value, bit width, and parity.
+
+  No Core16550 hardware configuration parameters are needed by the driver,
+  apart from the Core16550 hardware instance base address. Hence, no
+  additional configuration files are required to use the driver.
+
+  @section theory_op Theory of Operation
+  The Core16550 software driver is designed to allow the control of multiple
+  instances of Core16550. Each instance of Core16550 in the hardware design
+  is associated with a single instance of the uart_16550_instance_t structure
+  in the software. You need to allocate memory for one unique
+  uart_16550_instance_t structure instance for each Core16550 hardware instance.
+  The contents of these data structures are initialized during calls to
+  function UART_16550_init(). A pointer to the structure is passed to
+  subsequent driver functions in order to identify the Core16550 hardware
+  instance you wish to perform the requested operation on.
+
+  Note:     Do not attempt to directly manipulate the content of
+  uart_16550_instance_t structures. This structure is only intended to be
+  modified by the driver function.
+
+  Initialization
+  The Core16550 driver is initialized through a call to the UART_16550_init()
+  function. This function takes the UART’s configuration as parameters.
+  The UART_16550_init() function must be called before any other Core16550
+  driver functions can be called.
+
+  Polled Transmission and Reception
+  The driver can be used to transmit and receive data once initialized. Polled
+  operations where the driver constantly polls the state of the UART registers
+  in order to control data transmit or data receive are performed using these
+  functions:
+         •  UART_16550_polled_tx()
+         •  UART_16550_polled_tx_string
+         •  UART_16550_fill_tx_fifo()
+         •  UART_16550_get_rx()
+
+  Data is transmitted using the UART_16550_polled_tx() function. This function
+  is blocking, meaning that it will only return once the data passed to the
+  function has been sent to the Core16550 hardware. Data received by the
+  Core16550 hardware can be read by the UART_16550_get_rx() function.
+
+  The UART_16550_polled_tx_string() function is provided to transmit a NULL (‘\0’)
+  terminated string in polled mode. This function is blocking, meaning that it
+  will only return once the data passed to the function has been sent to the
+  Core16550 hardware.
+
+  The UART_16550_fill_tx_fifo() function fills the Core16550 hardware transmit
+  FIFO with data from a buffer passed as a parameter and returns the number of
+  bytes transferred to the FIFO. If the transmit FIFO is not empty when the
+  UART_16550_fill_tx_fifo() function is called it returns immediately without
+  transferring any data to the FIFO.
+
+  Interrupt Driven Operations
+  The driver can also transmit or receive data under interrupt control, freeing
+  your application to perform other tasks until an interrupt occurs indicating
+  that the driver’s attention is required. Interrupt controlled UART operations
+  are performed using these functions:
+        •   UART_16550_isr()
+        •   UART_16550_irq_tx()
+        •   UART_16550_tx_complete()
+        •   UART_16550_set_tx_handler()
+        •   UART_16550_set_rx_handler()
+        •   UART_16550_set_rxstatus_handler()
+        •   UART_16550_set_modemstatus_handler()
+        •   UART_16550_enable_irq()
+        •   UART_16550_disable_irq()
+
+  Interrupt Handlers
+  The UART_16550_isr() function is the top level interrupt handler function for
+  the Core16550 driver. You must call it from the system level
+  (CoreInterrupt and NVIC level) interrupt service routine (ISR) assigned to the
+  interrupt triggered by the Core16550 INTR signal. The UART_16550_isr() function
+  identifies the source of the Core16550 interrupt and calls the corresponding
+  handler function previously registered with the driver through calls to the
+  UART_16550_set_rx_handler(), UART_16550_set_tx_handler(),
+  UART_16550_set_rxstatus_handler(), and UART_16550_set_modemstatus_handler()
+  functions. You are responsible for creating these lower level interrupt handlers
+  as part of your application program and registering them with the driver.
+  The UART_16550_enable_irq() and UART_16550_disable_irq() functions are used to
+  enable or disable the received line status, received data available/character
+  timeout, transmit holding register empty and modem status interrupts at the
+  Core16550 level.
+
+  Transmitting Data
+  Interrupt-driven transmit is initiated by a call to UART_16550_irq_tx(),
+  specifying the block of data to transmit. Your application is then free to
+  perform other tasks and inquire later whether transmit has completed by calling
+  the UART_16550_tx_complete() function. The UART_16550_irq_tx() function enables
+  the UART’s transmit holding register empty (THRE) interrupt and then, when the
+  interrupt goes active, the driver’s default THRE interrupt handler transfers
+  the data block to the UART until the entire block is transmitted.
+
+  Note:     You can use the UART_16550_set_tx_handler() function to assign an
+  alternative handler to the THRE interrupt. In this case, you must not use the
+  UART_16550_irq_tx() function to initiate the transmit, as this will re-assign
+  the driver’s default THRE interrupt handler to the THRE interrupt. Instead,
+  your alternative THRE interrupt handler must include a call to the
+  UART_16550_fill_tx_fifo() function to transfer the data to the UART.
+
+  Receiving Data
+  Interrupt-driven receive is performed by first calling UART_16550_set_rx_handler()
+  to register a receive handler function that will be called by the driver whenever
+  receive data is available. You must provide this receive handler function which
+  must include a call to the UART_16550_get_rx() function to actually read the
+  received data.
+
+  UART Status
+  The function UART_16550_get_rx_status() is used to read the receiver error status.
+  This function returns the overrun, parity, framing, break, and FIFO error status
+  of the receiver.
+  The function UART_16550_get_tx_status() is used to read the transmitter status.
+  This function returns the transmit empty (TEMT) and transmit holding register
+  empty (THRE) status of the transmitter.
+  The function UART_16550_get_modem_status() is used to read the modem status flags.
+  This function returns the current value of the modem status register.
+
+  Loopback
+  The function UART_16550_set_loopback() is used to enable or disable loopback
+  between Tx and Rx lines internal to Core16550.
+*//*=========================================================================*/
+#ifndef __CORE_16550_H
+#define __CORE_16550_H 1
+
+#include "cpu_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * Receiver Error Status
+ * The following defines are used to determine the UART receiver error type.
+ * These bit mask constants are used with the return value of the
+ * UART_16550_get_rx_status() function to find out if any errors occurred
+ * while receiving data.
+ */
+#define UART_16550_NO_ERROR         ( (uint8_t) 0x00 )
+#define UART_16550_OVERRUN_ERROR    ( (uint8_t) 0x02 )
+#define UART_16550_PARITY_ERROR     ( (uint8_t) 0x04 )
+#define UART_16550_FRAMING_ERROR    ( (uint8_t) 0x08 )
+#define UART_16550_BREAK_ERROR      ( (uint8_t) 0x10 )
+#define UART_16550_FIFO_ERROR       ( (uint8_t) 0x80 )
+#define UART_16550_INVALID_PARAM    ( (uint8_t) 0xFF )
+
+/***************************************************************************//**
+ * Modem Status
+ * The following defines are used to determine the modem status. These bit
+ * mask constants are used with the return value of the
+ * UART_16550_get_modem_status() function to find out the modem status of
+ * the UART.
+ */
+#define UART_16550_DCTS             ( (uint8_t) 0x01 )
+#define UART_16550_DDSR             ( (uint8_t) 0x02 )
+#define UART_16550_TERI             ( (uint8_t) 0x04 )
+#define UART_16550_DDCD             ( (uint8_t) 0x08 )
+#define UART_16550_CTS              ( (uint8_t) 0x10 )
+#define UART_16550_DSR              ( (uint8_t) 0x20 )
+#define UART_16550_RI               ( (uint8_t) 0x40 )
+#define UART_16550_DCD              ( (uint8_t) 0x80 )
+
+/***************************************************************************//**
+ * Transmitter Status
+ * The following definitions are used to determine the UART transmitter status.
+ * These bit mask constants are used with the return value of the
+ * UART_16550_get_tx_status() function to find out the status of the
+ * transmitter.
+ */
+#define UART_16550_TX_BUSY          ( (uint8_t) 0x00 )
+#define UART_16550_THRE             ( (uint8_t) 0x20 )
+#define UART_16550_TEMT             ( (uint8_t) 0x40 )
+
+/***************************************************************************//**
+ * Core16550 Interrupts
+ * The following defines are used to enable and disable Core16550 interrupts.
+ * They are used to build the value of the irq_mask parameter for the
+ * UART_16550_enable_irq() and UART_16550_disable_irq() functions. A bitwise
+ * OR of these constants is used to enable or disable multiple interrupts.
+ */
+#define UART_16550_RBF_IRQ          ( (uint8_t) 0x01 )
+#define UART_16550_TBE_IRQ          ( (uint8_t) 0x02 )
+#define UART_16550_LS_IRQ           ( (uint8_t) 0x04 )
+#define UART_16550_MS_IRQ           ( (uint8_t) 0x08 )
+
+/***************************************************************************//**
+ * Data Width
+ * The following defines are used to build the value of the UART_16550_init()
+ * function line_config parameter.
+ */
+#define UART_16550_DATA_5_BITS      ( (uint8_t) 0x00 )
+#define UART_16550_DATA_6_BITS      ( (uint8_t) 0x01 )
+#define UART_16550_DATA_7_BITS      ( (uint8_t) 0x02 )
+#define UART_16550_DATA_8_BITS      ( (uint8_t) 0x03 )
+
+/***************************************************************************//**
+ * Parity Control
+ * The following defines are used to build the value of the UART_16550_init()
+ * function line_config parameter.
+ */
+#define UART_16550_NO_PARITY            ( (uint8_t) 0x00 )
+#define UART_16550_ODD_PARITY           ( (uint8_t) 0x08 )
+#define UART_16550_EVEN_PARITY          ( (uint8_t) 0x18 )
+#define UART_16550_STICK_PARITY_1       ( (uint8_t) 0x28 )
+#define UART_16550_STICK_PARITY_0       ( (uint8_t) 0x38 )
+
+/***************************************************************************//**
+ * Number of Stop Bits
+ * The following defines are used to build the value of the UART_16550_init()
+ * function line_config parameter.
+ */
+#define UART_16550_ONE_STOP_BIT     ( (uint8_t) 0x00 )
+/*only when data bits is 5*/
+#define UART_16550_ONEHALF_STOP_BIT ( (uint8_t) 0x04 )
+/*only when data bits is not 5*/
+#define UART_16550_TWO_STOP_BITS    ( (uint8_t) 0x04 )
+
+/***************************************************************************//**
+  This enumeration specifies the receiver FIFO trigger level. This is the number
+  of bytes that must be received before the UART generates a receive data
+  available interrupt. It provides the allowed values for the
+  UART_16550_set_rx_handler() function’s trigger_level parameter.
+ */
+typedef enum {
+    UART_16550_FIFO_SINGLE_BYTE    = 0,
+    UART_16550_FIFO_FOUR_BYTES     = 1,
+    UART_16550_FIFO_EIGHT_BYTES    = 2,
+    UART_16550_FIFO_FOURTEEN_BYTES = 3,
+    UART_16550_FIFO_INVALID_TRIG_LEVEL
+} uart_16550_rx_trig_level_t;
+
+/***************************************************************************//**
+  This enumeration specifies the Loopback configuration of the UART. It provides
+  the allowed values for the UART_16550_set_loopback() function’s loopback
+  parameter.
+ */
+typedef enum {
+    UART_16550_LOOPBACK_OFF   = 0,
+    UART_16550_LOOPBACK_ON    = 1,
+    UART_16550_INVALID_LOOPBACK
+} uart_16550_loopback_t;
+
+/***************************************************************************//**
+  This is type definition for Core16550 instance. You need to create and
+  maintain a record of this type. This holds all data regarding the Core16550
+  instance.
+ */
+typedef struct uart_16550_instance uart_16550_instance_t;
+
+/***************************************************************************//**
+  This typedef specifies the function prototype for Core16550 interrupt handlers.
+  All interrupt handlers registered with the Core16550 driver must be of this
+  type. The interrupt handlers are registered with the driver through the
+  UART_16550_set_rx_handler(), UART_16550_set_tx_handler(),
+  UART_16550_set_rxstatus_handler(), and UART_16550_set_modemstatus_handler()
+  functions.
+
+  The this_uart parameter is a pointer to a uart_16550_instance_t structure that
+  holds all data regarding this instance of the Core16550.
+ */
+typedef void (*uart_16550_irq_handler_t)(uart_16550_instance_t * this_uart);
+
+/***************************************************************************//**
+  uart_16550_instance.
+  This structure is used to identify the various Core16550 hardware instances
+  in your system. Your application software should declare one instance of this
+  structure for each instance of Core16550 in your system. The function
+  UART_16550_init() initializes this structure. A pointer to an initialized
+  instance of the structure should be passed as the first parameter to the
+  Core16550 driver functions, to identify which Core16550 hardware instance
+  should perform the requested operation.
+ */
+struct uart_16550_instance{
+    /* Core16550 instance base address: */
+    addr_t      base_address;
+    /* Accumulated status: */
+    uint8_t     status;
+
+    /* transmit related info: */
+    const uint8_t*  tx_buffer;
+    uint32_t        tx_buff_size;
+    uint32_t        tx_idx;
+
+    /* line status (OE, PE, FE & BI) interrupt handler:*/
+    uart_16550_irq_handler_t linests_handler;
+    /* receive interrupt handler:*/
+    uart_16550_irq_handler_t rx_handler;
+    /* transmitter holding register interrupt handler:*/
+    uart_16550_irq_handler_t tx_handler;
+    /* modem status interrupt handler:*/
+    uart_16550_irq_handler_t modemsts_handler;
+};
+
+/***************************************************************************//**
+ * The UART_16550_init() function initializes the driver’s data structures and
+ * the Core16550 hardware with the configuration passed as parameters.. The
+ * configuration parameters are the baud_value used to generate the baud rate,
+ * and the line_config used to specify the line configuration (bit length,
+ * stop bits and parity).
+ *
+ * @param this_uart     The this_uart parameter is a pointer to a
+ *                      uart_16550_instance_t structure that holds all data
+ *                      regarding this instance of the Core16550. This pointer
+ *                      is used to identify the target Core16550 hardware
+ *                      instance in subsequent calls to the Core16550 driver
+ *                      functions.
+ * @param base_addr     The base_address parameter is the base address in the
+ *                      processor's memory map for the registers of the
+ *                      Core16550 instance being initialized.
+ * @param baud_value    The baud_value parameter is used to select the baud rate
+ *                      for the UART. The baud value is calculated from the
+ *                      frequency of the system clock in Hertz and the desired
+ *                      baud rate using the following equation:
+ *
+ *                      baud_value = (clock /(baud_rate * 16))
+ *
+ *                      The baud_value parameter must be a value in the range 0
+ *                      to 65535 (or 0x0000 to 0xFFFF).
+ * @param line_config   This parameter is the line configuration specifying the
+ *                      bit length, number of stop bits and parity settings. This
+ *                      is a bitwise OR of one value from each of the following
+ *                      groups of allowed values:
+ *                      •   Data lengths:
+ *                          UART_16550_DATA_5_BITS
+ *                          UART_16550_DATA_6_BITS
+ *                          UART_16550_DATA_7_BITS
+ *                          UART_16550_DATA_8_BITS
+ *                      •   Parity types:
+ *                          UART_16550_NO_PARITY
+ *                          UART_16550_EVEN_PARITY
+ *                          UART_16550_ODD_PARITY
+ *                          UART_16550_STICK_PARITY_0
+ *                          UART_16550_STICK_PARITY_1
+ *                      •   Number of stop bits:
+ *                          UART_16550_ONE_STOP_BIT
+ *                          UART_16550_ONEHALF_STOP_BIT
+ *                          UART_16550_TWO_STOP_BITS
+ * @return              This function does not return a value.
+ *
+ * Example:
+ * @code
+ * #define UART_16550_BASE_ADDR   0x2A000000
+ * #define BAUD_VALUE_57600    26
+ *
+ * uart_16550_instance_t g_uart;
+ *
+ * UART_16550_init( &g_uart, UART_16550_BASE_ADDR, BAUD_VALUE_57600,
+ *                  (UART_16550_DATA_8_BITS |
+ *                   UART_16550_EVEN_PARITY |
+ *                   UART_16550_ONE_STOP_BIT) );
+ * @endcode
+ */
+void
+UART_16550_init
+(
+    uart_16550_instance_t* this_uart,
+    addr_t base_addr,
+    uint16_t baud_value,
+    uint8_t line_config
+);
+
+/***************************************************************************//**
+ * The UART_16550_polled_tx() function is used to transmit data. It transfers
+ * the contents of the transmitter data buffer, passed as a function parameter,
+ * into the UART's hardware transmitter FIFO. It returns when the full content
+ * of the transmitter data buffer has been transferred to the UART's transmitter
+ * FIFO. It is safe to release or reuse the memory used as the transmitter data
+ * buffer once this function returns.
+ *
+ * Note:    This function reads the UART’s line status register (LSR) to poll
+ * for the active state of the transmitter holding register empty (THRE) bit
+ * before transferring data from the data buffer to the transmitter FIFO. It
+ * transfers data to the transmitter FIFO in blocks of 16 bytes or less and
+ * allows the FIFO to empty before transferring the next block of data.
+ *
+ * Note:    The actual transmission over the serial connection will still be in
+ * progress when this function returns. Use the UART_16550_get_tx_status()
+ * function if you need to know when the transmitter is empty.
+ *
+ * @param this_uart     The this_uart parameter is a pointer to a
+ *                      uart_16550_instance_t structure that holds all
+ *                      data regarding this instance of the Core16550.
+ * @param pbuff         The pbuff parameter is a pointer to a buffer containing
+ *                      the data to be transmitted.
+ * @param tx_size       The tx_size parameter is the size, in bytes, of the
+ *                      data to be transmitted.
+ * @return              This function does not return a value.
+ *
+ * Example:
+ * @code
+ *   uint8_t testmsg1[] = {"\n\r\n\r\n\rUART_16550_polled_tx() test message 1"};
+ *   UART_16550_polled_tx(&g_uart,(const uint8_t *)testmsg1,sizeof(testmsg1));
+ * @endcode
+ */
+void
+UART_16550_polled_tx
+(
+    uart_16550_instance_t * this_uart,
+    const uint8_t * pbuff,
+    uint32_t tx_size
+);
+/***************************************************************************//**
+ * The UART_16550_polled_tx_string() function is used to transmit a NULL ('\0')
+ * terminated string. It transfers the text string, from the buffer starting at
+ * the address pointed to by p_sz_string, into the UART’s hardware transmitter
+ * FIFO. It returns when the complete string has been transferred to the UART's
+ * transmit FIFO. It is safe to release or reuse the memory used as the string
+ * buffer once this function returns.
+ *
+ * Note:    This function reads the UART’s line status register (LSR) to poll
+ * for the active state of the transmitter holding register empty (THRE) bit
+ * before transferring data from the data buffer to the transmitter FIFO. It
+ * transfers data to the transmitter FIFO in blocks of 16 bytes or less and
+ * allows the FIFO to empty before transferring the next block of data.
+ *
+ * Note:    The actual transmission over the serial connection will still be
+ * in progress when this function returns. Use the UART_16550_get_tx_status()
+ * function if you need to know when the transmitter is empty.
+ *
+ * @param this_uart     The this_uart parameter is a pointer to a
+ *                      uart_16550_instance_t structure that holds all data
+ *                      regarding this instance of the Core16550.
+ * @param p_sz_string   The p_sz_string parameter is a pointer to a buffer
+ *                      containing the NULL ('\0') terminated string to be
+ *                      transmitted.
+ * @return              This function does not return a value.
+ *
+ * Example:
+ * @code
+ *   uint8_t testmsg1[] = {"\r\n\r\nUART_16550_polled_tx_string() test message 1\0"};
+ *   UART_16550_polled_tx_string(&g_uart,(const uint8_t *)testmsg1);
+ * @endcode
+ */
+void
+UART_16550_polled_tx_string
+(
+    uart_16550_instance_t * this_uart,
+    const uint8_t * p_sz_string
+);
+
+/***************************************************************************//**
+ * The UART_16550_irq_tx() function is used to initiate an interrupt driven
+ * transmit. It returns immediately after making a note of the transmit buffer
+ * location and enabling the transmitter holding register empty (THRE) interrupt
+ * at the Core16550 level. This function takes a pointer via the pbuff parameter
+ * to a memory buffer containing the data to transmit. The memory buffer
+ * specified through this pointer must remain allocated and contain the data to
+ * transmit until the transmit completion has been detected through calls to
+ * function UART_16550_tx_complete().The actual transmission over the serial
+ * connection is still in progress until calls to the UART_16550_tx_complete()
+ * function indicate transmit completion.
+ *
+ * Note:    It is your responsibility to call UART_16550_isr(), the driver’s
+ * top level interrupt handler function, from the system level (CoreInterrupt
+ * and NVIC level) interrupt handler assigned to the interrupt triggered by the
+ * Core16550 INTR signal. You must do this before using the UART_16550_irq_tx()
+ * function.
+ *
+ * Note:    It is also your responsibility to enable the system level
+ * (CoreInterrupt and NVIC level) interrupt connected to the Core16550 INTR
+ * interrupt signal.
+ *
+ * Note:    The UART_16550_irq_tx() function assigns an internal default transmit
+ * interrupt handler function to the UART’s THRE interrupt. This interrupt handler
+ * overrides any custom interrupt handler that you may have previously registered
+ * using the UART_16550_set_tx_handler() function.
+ *
+ * Note:    The UART_16550_irq_tx() function’s default transmit interrupt handler
+ * disables the UART’s THRE interrupt when all of the data has been transferred
+ * to the UART's transmit FIFO.
+ *
+ * @param this_uart     The this_uart parameter is a pointer to a
+ *                      uart_16550_instance_t structure that holds all data
+ *                      regarding this instance of the Core16550.
+ * @param pbuff         The pbuff parameter is a pointer to a buffer containing
+ *                      the data to be transmitted.
+ * @param tx_size       The tx_size parameter specifies the size, in bytes, of
+ *                      the data to be transmitted.
+ * @return              This function does not return a value.
+ *
+ * Example:
+ * @code
+ * uint8_t tx_buff[10] = "abcdefghi";
+ *
+ * UART_16550_irq_tx( &g_uart, tx_buff, sizeof(tx_buff));
+ * while ( 0 == UART_16550_tx_complete( &g_uart ) )
+ * { ; }
+ * @endcode
+ */
+void
+UART_16550_irq_tx
+(
+    uart_16550_instance_t * this_uart,
+    const uint8_t * pbuff,
+    uint32_t tx_size
+);
+
+/***************************************************************************//**
+ * The UART_16550_tx_complete() function is used to find out if the interrupt
+ * driven transmit previously initiated through a call to UART_16550_irq_tx()
+ * is complete. This function is typically used to find out when it is safe
+ * to reuse or release the memory buffer holding the transmit data.
+ *
+ * Note:    The transfer of all of the data from the memory buffer to the UART’s
+ * transmit FIFO and the actual transmission over the serial connection are both
+ * complete when a call to the UART_16550_tx_complete() function indicate
+ * transmit completion.
+ *
+ * @param this_uart     The this_uart parameter is a pointer to a
+ *                      uart_16550_instance_t structure that holds all data
+ *                      regarding this instance of the Core16550.
+ * @return              This function returns a non-zero value if transmit has
+ *                      completed, otherwise it returns zero.
+ *  Example:
+ *   See the UART_16550_irq_tx() function for an example that uses the
+ *   UART_16550_tx_complete() function.
+ */
+int8_t
+UART_16550_tx_complete
+(
+   uart_16550_instance_t * this_uart
+);
+
+/***************************************************************************//**
+ * The UART_16550_get_rx() function reads the content of the Core16550
+ * receiver’s FIFO and stores it in the receive buffer that is passed via the
+ * rx_buff function parameter. It copies either the full contents of the FIFO
+ * into the receive buffer, or just enough data from the FIFO to fill the receive
+ * buffer, dependent upon the size of the receive buffer passed by the buff_size
+ * parameter. The UART_16550_get_rx() function returns the number of bytes copied
+ * into the receive buffer .This function is non-blocking and will return 0
+ * immediately if no data has been received.
+ *
+ * Note:    The UART_16550_get_rx() function reads and accumulates the receiver
+ * status of the Core16550 instance before reading each byte from the receiver's
+ * data register/FIFO. This allows the driver to maintain a sticky record of any
+ * receiver errors that occur as the UART receives each data byte; receiver errors
+ * would otherwise be lost after each read from the receiver's data register. A call
+ * to the UART_16550_get_rx_status() function returns any receiver errors accumulated
+ * during the execution of the UART_16550_get_rx() function.
+ *
+ * Note:    If you need to read the error status for each byte received, set the
+ * buff_size to 1 and read the receive line error status for each byte using the
+ * UART_16550_get_rx_status() function.
+ * The UART_16550_get_rx() function can be used in polled mode, where it is called
+ * at regular intervals to find out if any data has been received, or in interrupt
+ * driven-mode, where it is called as part of a receive handler that is called by
+ * the driver as a result of data being received.
+ *
+ * Note:    In interrupt driven mode you should call the UART_16550_get_rx()
+ * function as part of the receive handler function that you register with the
+ * Core16550 driver through a call to UART_16550_set_rx_handler().
+ *
+ * @param this_uart     The this_uart parameter is a pointer to a
+ *                      uart_16550_instance_t structure that holds all data
+ *                      regarding this instance of the Core16550.
+ * @param rx_buff       The rx_buff parameter is a pointer to a memory buffer
+ *                      where the received data is copied.
+ * @param buff_size     The buff_size parameter is the size of the receive
+ *                      buffer in bytes.
+ * @return              This function returns the number of bytes copied into
+ *                      the receive buffer.
+ * Example:
+ * @code
+ *   #define MAX_RX_DATA_SIZE    256
+ *
+ *   uint8_t rx_data[MAX_RX_DATA_SIZE];
+ *   uint8_t rx_size = 0;
+ *
+ *   rx_size = UART_16550_get_rx( &g_uart, rx_data, sizeof(rx_data) );
+ * @endcode
+ */
+size_t
+UART_16550_get_rx
+(
+   uart_16550_instance_t * this_uart,
+   uint8_t * rx_buff,
+   size_t buff_size
+);
+
+/***************************************************************************//**
+ * The UART_16550_isr() function is the top level interrupt handler function for
+ * the Core16550 driver. You must call UART_16550_isr() from the system level
+ * (CoreInterrupt and NVIC level) interrupt handler assigned to the interrupt
+ * triggered by the Core16550 INTR signal. Your system level interrupt handler
+ * must also clear the system level interrupt triggered by the Core16550 INTR
+ * signal before returning, to prevent a re-assertion of the same interrupt.
+ *
+ * Note:    This function supports all types of interrupt triggered by Core16550.
+ * It is not a complete interrupt handler by itself; rather, it is a top level
+ * wrapper that abstracts Core16550 interrupt handling by calling lower level
+ * handler functions specific to each type of Core16550 interrupt. You must
+ * create the lower level handler functions to suit your application and
+ * register them with the driver through calls to the UART_16550_set_rx_handler(),
+ * UART_16550_set_tx_handler(), UART_16550_set_rxstatus_handler() and
+ * UART_16550_set_modemstatus_handler() functions.
+ *
+ * @param this_uart     The this_uart parameter is a pointer to a
+ *                      uart_16550_instance_t structure that holds all data
+ *                      regarding this instance of the Core16550.
+ *
+ * @return              This function does not return a value.
+ *
+ * Example:
+ * @code
+ *   void CIC_irq1_handler(void)
+ *   {
+ *      UART_16550_isr( &g_uart );
+ *   }
+ * @endcode
+ */
+void
+UART_16550_isr
+(
+   uart_16550_instance_t * this_uart
+);
+
+/***************************************************************************//**
+ * The UART_16550_set_rx_handler() function is used to register a receive handler
+ * function that is called by the driver when a UART receive data available (RDA)
+ * interrupt occurs. The UART_16550_set_rx_handler() function also enables the
+ * RDA interrupt at the Core16550 level. You must create and register the receive
+ * handler function to suit your application and it must include a call to the
+ * UART_16550_get_rx() function to actually read the received data.
+ *
+ * Note:    The driver’s top level interrupt handler function UART_16550_isr()
+ * will call your receive handler function in response to an RDA interrupt from
+ * the Core16550.
+ *
+ * Note:    You can disable the RDA interrupt once the data is received by calling
+ * the UART_16550_disable_irq() function. This is your choice and is dependent
+ * upon your application.
+ *
+ * @param this_uart     The this_uart parameter is a pointer to a
+ *                      uart_16550_instance_t structure that holds all data
+ *                      regarding this instance of the Core16550.
+ * @param handler       The handler parameter is a pointer to a receive interrupt
+ *                      handler function provided by your application that will be
+ *                      called as a result of a UART RDA interrupt. This handler
+ *                      function must be of type uart_16550_irq_handler_t.
+ * @param trigger_level The trigger_level parameter is the receive FIFO
+ *                      trigger level. This specifies the number of bytes that
+ *                      must be received before the UART triggers an RDA
+ *                      interrupt.
+ * @return              This function does not return a value.
+ *
+ * Example:
+ * @code
+ * #include "core_16550.h"
+ *
+ * #define RX_BUFF_SIZE    64
+ * #define UART_57600_BAUD 26
+ *
+ * uint8_t g_rx_buff[RX_BUFF_SIZE];
+ * uart_16550_instance_t g_uart;
+ * void uart_rx_handler( uart_16550_instance_t * this_uart )
+ * {
+ *     UART_16550_get_rx( this_uart, g_rx_buff, RX_BUFF_SIZE );
+ * }
+ *
+ * int main(void)
+ * {
+ *     UART_16550_init( &g_uart, UART_57600_BAUD,
+ *                       ( UART_16550_DATA_8_BITS | UART_16550_NO_PARITY ) );
+ *     UART_16550_set_rx_handler( &g_uart, uart_rx_handler,
+ *                                UART_16550_FIFO_SINGLE_BYTE);
+ *     while ( 1 )
+ *     {
+ *         ;
+ *     }
+ *     return(0);
+ * }
+ * @endcode
+ */
+void
+UART_16550_set_rx_handler
+(
+    uart_16550_instance_t * this_uart,
+    uart_16550_irq_handler_t handler,
+    uart_16550_rx_trig_level_t trigger_level
+);
+
+/***************************************************************************//**
+ * The UART_16550_set_loopback() function is used to locally loopback the Tx
+ * and Rx lines of a Core16550 UART.
+ *
+ * @param this_uart     The this_uart parameter is a pointer to a
+ *                      uart_16550_instance_t structure that holds all data
+ *                      regarding this instance of the Core16550.
+ * @param loopback      The loopback parameter indicates whether or not the
+ *                      UART's transmit and receive lines should be looped back.
+ *                      Allowed values are as follows:
+ *                      •   UART_16550_LOOPBACK_ON
+ *                      •   UART_16550_LOOPBACK_OFF
+ * @return              This function does not return a value.
+ *
+ * Example:
+ * @code
+ * #include "core_16550.h"
+ *
+ * #define UART_57600_BAUD 26
+ * #define DATA_SIZE 4
+ *
+ * uart_16550_instance_t g_uart;
+ *
+ * int main(void)
+ * {
+ *      uint8_t txbuf[DATA_SIZE] = "abc";
+ *      uint8_t rxbuf[DATA_SIZE];
+ *      UART_16550_init( &g_uart, UART_57600_BAUD,
+ *                        ( UART_16550_DATA_8_BITS | UART_16550_NO_PARITY |
+ *                                               UART_16550_ONE_STOP_BIT) );
+ *      UART_16550_set_loopback( &g_uart, UART_16550_LOOPBACK_ON );
+ *
+ *      while(1)
+ *      {
+ *          UART_16550_polled_tx( &g_uart, txbuf, DATA_SIZE);
+ *          delay(100);
+ *          UART_16550_get_rx( &g_uart, rxbuf, DATA_SIZE);
+ *      }
+ * }
+ * @endcode
+ */
+void
+UART_16550_set_loopback
+(
+    uart_16550_instance_t * this_uart,
+    uart_16550_loopback_t loopback
+);
+
+/***************************************************************************//**
+ * The UART_16550_get_rx_status() function returns the receiver error status of
+ * the Core16550 instance. It reads both the current error status of the receiver
+ * from the UART’s line status register (LSR) and the accumulated error status
+ * from preceding calls to the UART_16550_get_rx() function, and it combines
+ * them using a bitwise OR. It returns the cumulative overrun, parity, framing,
+ * break and FIFO error status of the receiver, since the previous call to
+ * UART_16550_get_rx_status(), as an 8-bit encoded value.
+ *
+ * Note:    The UART_16550_get_rx() function reads and accumulates the receiver
+ * status of the Core16550 instance before reading each byte from the receiver’s
+ * data register/FIFO. The driver maintains a sticky record of the cumulative
+ * receiver error status, which persists after the UART_16550_get_rx() function
+ * returns. The UART_16550_get_rx_status() function clears the driver’s sticky
+ * receiver error record before returning.
+ *
+ * Note:    The driver’s transmit functions also read the line status register
+ * (LSR) as part of their implementation. When the driver reads the LSR, the
+ * UART clears any active receiver error bits in the LSR. This could result in
+ * the driver losing receiver errors. To avoid any loss of receiver errors, the
+ * transmit functions also update the driver’s sticky record of the cumulative
+ * receiver error status whenever they read the LSR.
+ *
+ * @param this_uart     The this_uart parameter is a pointer to a
+ *                      uart_16550_instance_t structure that holds all data
+ *                      regarding this instance of the Core16550.
+ * @return              This function returns the UART’s receiver error status
+ *                      as an 8-bit unsigned integer. The returned value is 0
+ *                      if no receiver errors occurred. The driver provides a
+ *                      set of bit mask constants that should be compared with
+ *                      and/or used to mask the returned value to determine the
+ *                      receiver error status.
+ *                      When the return value is compared to the following bit
+ *                      masks, a non-zero result indicates that the
+ *                      corresponding error occurred:
+ *                      •   UART_16550_OVERRUN_ERROR    (bit mask = 0x02)
+ *                      •   UART_16550_PARITY_ERROR     (bit mask = 0x04)
+ *                      •   UART_16550_FRAMING_ERROR    (bit mask = 0x08)
+ *                      •   UART_16550_BREAK_ERROR      (bit mask = 0x10)
+ *                      •   UART_16550_FIFO_ERROR       (bit mask = 0x80)
+ *                      When the return value is compared to the following bit
+ *                      mask, a non-zero result indicates that no error occurred:
+ *                      •   UART_16550_NO_ERROR         (bit mask = 0x00)
+ *                      Upon unsuccessful execution, this function returns:
+ *                      •   UART_16550_INVALID_PARAM    (bit mask = 0xFF)
+ *
+ * Example:
+ * @code
+ *   uart_16550_instance_t g_uart;
+ *   uint8_t rx_data[MAX_RX_DATA_SIZE];
+ *   uint8_t err_status;
+ *
+ *   err_status = UART_16550_get_rx_status(&g_uart);
+ *   if(UART_16550_NO_ERROR == err_status )
+ *   {
+ *        rx_size = UART_16550_get_rx( &g_uart, rx_data, MAX_RX_DATA_SIZE );
+ *   }
+ * @endcode
+ */
+uint8_t
+UART_16550_get_rx_status
+(
+    uart_16550_instance_t * this_uart
+);
+/***************************************************************************//**
+ * The UART_16550_enable_irq() function enables the Core16550 interrupts
+ * specified by the irq_mask parameter. The irq_mask parameter identifies the
+ * Core16550 interrupts by bit position, as defined in the interrupt enable
+ * register (IER) of Core16550. The Core16550 interrupts and their identifying
+ * irq_mask bit positions are as follows:
+ *      •   Receive data available interrupt (RDA)      (irq_mask bit 0)
+ *      •   Transmit holding register empty interrupt (THRE)    (irq_mask bit 1)
+ *      •   Receiver line status interrupt (LS)         (irq_mask bit 2)
+ *      •   Modem status interrupt (MS)         (irq_mask bit 3)
+ * When an irq_mask bit position is set to 1, this function enables the
+ * corresponding Core16550 interrupt in the IER register. When an irq_mask
+ * bit position is set to 0, the corresponding interrupt’s state remains
+ * unchanged in the IER register.
+ *
+ * @param this_uart     The this_uart parameter is a pointer to a
+ *                      uart_16550_instance_t structure that holds all data
+ *                      regarding this instance of the Core16550.
+ * @param irq_mask      The irq_mask parameter is used to select which of the
+ *                      Core16550’s interrupts you want to enable. The allowed
+ *                      value for the irq_mask parameter is one of the
+ *                      following constants or a bitwise OR of more than one:
+ *                      •   UART_16550_RBF_IRQ      (bit mask = 0x01)
+ *                      •   UART_16550_TBE_IRQ      (bit mask = 0x02)
+ *                      •   UART_16550_LS_IRQ       (bit mask = 0x04)
+ *                      •   UART_16550_MS_IRQ       (bit mask = 0x08)
+ * @return              This function does not return a value.
+ *
+ * Example:
+ * @code
+ *   UART_16550_enable_irq( &g_uart,( UART_16550_RBF_IRQ | UART_16550_TBE_IRQ ) );
+ * @endcode
+ */
+void
+UART_16550_enable_irq
+(
+    uart_16550_instance_t * this_uart,
+    uint8_t irq_mask
+);
+
+/***************************************************************************//**
+ * The UART_16550_disable_irq() function disables the Core16550 interrupts
+ * specified by the irq_mask parameter. The irq_mask parameter identifies the
+ * Core16550 interrupts by bit position, as defined in the interrupt enable
+ * register (IER) of Core16550. The Core16550 interrupts and their identifying
+ * bit positions are as follows:
+ *      •   Receive data available interrupt (RDA)              (irq_mask bit 0)
+ *      •   Transmit holding register empty interrupt (THRE)    (irq_mask bit 1)
+ *      •   Receiver line status interrupt (LS)                 (irq_mask bit 2)
+ *      •   Modem status interrupt (MS)                         (irq_mask bit 3)
+ * When an irq_mask bit position is set to 1, this function disables the
+ * corresponding Core16550 interrupt in the IER register. When an irq_mask bit
+ * position is set to 0, the corresponding interrupt’s state remains unchanged
+ * in the IER register.
+ *
+ * @param this_uart     The this_uart parameter is a pointer to a
+ *                      uart_16550_instance_t structure that holds all data
+ *                      regarding this instance of the Core16550.
+ * @param irq_mask      The irq_mask parameter is used to select which of the
+ *                      Core16550’s interrupts you want to disable. The allowed
+ *                      value for the irq_mask parameter is one of the
+ *                      following constants or a bitwise OR of more than one:
+ *                      •   UART_16550_RBF_IRQ      (bit mask = 0x01)
+ *                      •   UART_16550_TBE_IRQ      (bit mask = 0x02)
+ *                      •   UART_16550_LS_IRQ       (bit mask = 0x04)
+ *                      •   UART_16550_MS_IRQ       (bit mask = 0x08)
+ * @return              This function does not return a value.
+ *
+ * Example:
+ * @code
+ *   UART_16550_disable_irq( &g_uart, ( UART_16550_RBF_IRQ | UART_16550_TBE_IRQ ) );
+ * @endcode
+ */
+void
+UART_16550_disable_irq
+(
+    uart_16550_instance_t * this_uart,
+    uint8_t irq_mask
+);
+
+/***************************************************************************//**
+ * The UART_16550_get_modem_status() function returns the modem status of the
+ * Core16550 instance. It reads the modem status register (MSR) and returns the
+ * 8 bit value. The bit encoding of the returned value is exactly the same as
+ * the definition of the bits in the MSR.
+ *
+ * @param this_uart     The this_uart parameter is a pointer to a
+ *                      uart_16550_instance_t structure that holds all data
+ *                      regarding this instance of the Core16550.
+ * @return              This function returns current state of the UART's MSR
+ *                      as an 8 bit unsigned integer. The driver provides the
+ *                      following set of bit mask constants that should be
+ *                      compared with and/or used to mask the returned value
+ *                      to determine the modem status:
+ *                      •   UART_16550_DCTS (bit mask = 0x01)
+ *                      •   UART_16550_DDSR (bit mask = 0x02)
+ *                      •   UART_16550_TERI (bit mask = 0x04)
+ *                      •   UART_16550_DDCD (bit mask = 0x08)
+ *                      •   UART_16550_CTS  (bit mask = 0x10)
+ *                      •   UART_16550_DSR  (bit mask = 0x20)
+ *                      •   UART_16550_RI   (bit mask = 0x40)
+ *                      •   UART_16550_DCD  (bit mask = 0x80)
+ * Example:
+ * @code
+ *   void uart_modem_status_isr(uart_16550_instance_t * this_uart)
+ *   {
+ *      uint8_t status;
+ *      status = UART_16550_get_modem_status( this_uart );
+ *      if( status & UART_16550_DCTS )
+ *      {
+ *          uart_dcts_handler();
+ *      }
+ *      if( status & UART_16550_CTS )
+ *      {
+ *          uart_cts_handler();
+ *      }
+ *   }
+ * @endcode
+ */
+uint8_t
+UART_16550_get_modem_status
+(
+    uart_16550_instance_t * this_uart
+);
+
+/***************************************************************************//**
+ * The UART_16550_set_rxstatus_handler() function is used to register a receiver
+ * status handler function that is called by the driver when a UART receiver
+ * line status (RLS) interrupt occurs. The UART_16550_set_rxstatus_handler()
+ * function also enables the RLS interrupt at the Core16550 level. You must
+ * create and register the receiver status handler function to suit your
+ * application.
+ *
+ * Note:    The driver’s top level interrupt handler function UART_16550_isr()
+ * will call your receive status handler function in response to an RLS
+ * interrupt from the Core16550.
+ *
+ * Note:    You can disable the RLS interrupt when required by calling the
+ * UART_16550_disable_irq() function. This is your choice and is dependent
+ * upon your application.
+ *
+ * @param this_uart     The this_uart parameter is a pointer to a
+ *                      uart_16550_instance_t structure that holds all data
+ *                      regarding this instance of the Core16550.
+ * @param handler       The handler parameter is a pointer to a receiver line
+ *                      status interrupt handler function provided by your
+ *                      application that will be called as a result of a
+ *                      UART RLS interrupt. This handler function must be
+ *                      of type uart_16550_irq_handler_t.
+ * Example:
+ * @code
+ * #include "core_16550.h"
+ *
+ * #define UART_57600_BAUD 26
+ *
+ * uart_16550_instance_t g_uart;
+ *
+ * void uart_rxsts_handler( uart_16550_instance_t * this_uart )
+ * {
+ *      uint8_t status;
+ *      status = UART_16550_get_rx_status( this_uart );
+ *      if( status & UART_16550_OVERUN_ERROR )
+ *      {
+ *          discard_rx_data();
+ *      }
+ * }
+ *
+ * int main(void)
+ * {
+ *     UART_16550_init( &g_uart, UART_57600_BAUD,
+ *                      UART_16550_DATA_8_BITS | UART_16550_NO_PARITY |
+ *                                             UART_16550_ONE_STOP_BIT );
+ *     UART_16550_set_rxstatus_handler( &g_uart, uart_rxsts_handler );
+ *
+ *     while ( 1 )
+ *     {
+ *         ;
+ *     }
+ *     return(0);
+ * }
+ * @endcode
+ */
+void
+UART_16550_set_rxstatus_handler
+(
+    uart_16550_instance_t * this_uart,
+    uart_16550_irq_handler_t handler
+);
+
+/***************************************************************************//**
+ * The UART_16550_set_tx_handler() function is used to register a transmit
+ * handler function that is called by the driver when a UART transmit holding
+ * register empty (THRE) interrupt occurs. The UART_16550_set_tx_handler()
+ * function also enables the THRE interrupt at the Core16550 level. You must
+ * create and register the transmit handler function to suit your application.
+ * You can use the UART_16550_fill_tx_fifo() function in your transmit handler
+ * function to write data to the transmitter.
+ *
+ * Note:    The driver’s top level interrupt handler function UART_16550_isr()
+ * will call your transmit handler function in response to an THRE interrupt
+ * from the Core16550.
+ *
+ * Note:    You can disable the THRE interrupt when required by calling the
+ * UART_16550_disable_irq() function. This is your choice and is dependent
+ * upon your application.
+ *
+ * Note:    The UART_16550_irq_tx() function does not use the transmit handler
+ * function that you register with the UART_16550_set_tx_handler() function.
+ * It uses its own internal THRE interrupt handler function that overrides any
+ * custom interrupt handler that you register using the
+ * UART_16550_set_tx_handler() function.
+ *
+ * @param this_uart     The this_uart parameter is a pointer to a
+ *                      uart_16550_instance_t structure that holds all data
+ *                      regarding this instance of the Core16550.
+ * @param handler       The handler parameter is a pointer to a transmitter
+ *                      interrupt handler function provided by your application,
+ *                      which will be called as a result of a UART THRE interrupt.
+ *                      This handler is of uart_16550_irq_handler_t type.
+ * @return              This function does not return a value.
+ *
+ * Example:
+ * @code
+ * #include "core_16550.h"
+ *
+ * #define UART_57600_BAUD 26
+ *
+ * uart_16550_instance_t g_uart;
+ *
+ * uint8_t * g_tx_buffer;
+ * size_t g_tx_size = 0;
+ *
+ * void uart_tx_handler( uart_16550_instance_t * this_uart )
+ * {
+ *      size_t size_in_fifo;
+ *
+ *      size_in_fifo = UART_16550_fill_tx_fifo( this_uart,
+ *                                              (const uint8_t *)g_tx_buffer,
+ *                                              g_tx_size );
+ *
+ *      if(size_in_fifo == g_tx_size)
+ *      {
+ *         g_tx_size = 0;
+ *         UART_16550_disable_irq( this_uart, UART_16550_TBE_IRQ );
+ *      }
+ *      else
+ *      {
+ *         g_tx_buffer = &g_tx_buffer[size_in_fifo];
+ *         g_tx_size = g_tx_size - size_in_fifo;
+ *      }
+ *  }
+ *
+ *  int main(void)
+ *  {
+ *      uint8_t message[12] = "Hello world";
+ *
+ *      UART_16550_init( &g_uart, UART_57600_BAUD,
+ *                       UART_16550_DATA_8_BITS | UART_16550_NO_PARITY |
+ *                                            UART_16550_ONE_STOP_BIT );
+ *
+ *      g_tx_buffer = message;
+ *      g_tx_size = sizeof(message);
+ *
+ *      UART_16550_set_tx_handler( &g_uart, uart_tx_handler);
+ *
+ *      while ( 1 )
+ *      {
+ *          ;
+ *      }
+ *      return(0);
+ *  }
+ *
+ * @endcode
+ */
+void
+UART_16550_set_tx_handler
+(
+    uart_16550_instance_t * this_uart,
+    uart_16550_irq_handler_t handler
+);
+
+/***************************************************************************//**
+ * The UART_16550_set_modemstatus_handler() function is used to register a
+ * modem status handler function that is called by the driver when a UART modem
+ * status (MS) interrupt occurs. The UART_16550_set_modemstatus_handler()
+ * function also enables the MS interrupt at the Core16550 level. You must
+ * create and register the modem status handler function to suit your
+ * application.
+ *
+ * Note:    The driver’s top level interrupt handler function UART_16550_isr()
+ * will call your receive status handler function in response to an MS interrupt
+ * from the Core16550.
+ *
+ * Note:    You can disable the MS interrupt when required by calling the
+ * UART_16550_disable_irq() function. This is your choice and is dependent
+ * upon your application.
+ *
+ * @param this_uart     The this_uart parameter is a pointer to a
+ *                      uart_16550_instance_t structure that holds all data
+ *                      regarding this instance of the Core16550.
+ * @param handler       The handler parameter is a pointer to a modem status
+ *                      interrupt handler function provided by your application
+ *                      that will be called as a result of a UART MS interrupt.
+ *                      This handler function must be of type
+ *                      uart_16550_irq_handler_t.
+ * @return              This function does not return a value.
+ *
+ * Example:
+ * @code
+ * #include "core_16550.h"
+ *
+ * #define UART_57600_BAUD 26
+ *
+ * uart_16550_instance_t g_uart;
+ *
+ * void uart_modem_handler( uart_16550_instance_t * this_uart )
+ * {
+ *      uint8_t status;
+ *      status = UART_16550_get_modem_status( this_uart );
+ *      if( status & UART_16550_CTS )
+ *      {
+ *          uart_cts_handler();
+ *      }
+ * }
+ *
+ * int main(void)
+ * {
+ *     UART_16550_init( &g_uart, UART_57600_BAUD,
+ *                      UART_16550_DATA_8_BITS | UART_16550_NO_PARITY |
+                                              UART_16550_ONE_STOP_BIT);
+ *     UART_16550_set_modemstatus_handler( &g_uart, uart_modem_handler);
+ *
+ *     while ( 1 )
+ *     {
+ *         ;
+ *     }
+ *     return(0);
+ * }
+ * @endcode
+ */
+void
+UART_16550_set_modemstatus_handler
+(
+    uart_16550_instance_t * this_uart,
+    uart_16550_irq_handler_t handler
+);
+
+/***************************************************************************//**
+ * The UART_16550_fill_tx_fifo() function fills the UART's hardware transmitter
+ * FIFO with the data found in the transmitter buffer that is passed via the
+ * tx_buffer function parameter. If the transmitter FIFO is not empty when the
+ * function is called, the function returns immediately without transferring
+ * any data to the FIFO; otherwise, the function transfers data from the
+ * transmitter buffer to the FIFO until it is full or until the complete
+ * contents of the transmitter buffer have been copied into the FIFO. The
+ * function returns the number of bytes copied into the UART's transmitter FIFO.
+ *
+ * Note:    This function reads the UART’s line status register (LSR) to check
+ * for the active state of the transmitter holding register empty (THRE) bit
+ * before transferring data from the data buffer to the transmitter FIFO. If
+ * THRE is 0, the function returns immediately, without transferring any data
+ * to the FIFO. If THRE is 1, the function transfers up to 16 bytes of data to
+ * the FIFO and then returns.
+ *
+ * Note:    The actual transmission over the serial connection will still be in
+ * progress when this function returns. Use the UART_16550_get_tx_status()
+ * function if you need to know when the transmitter is empty.
+ *
+ * @param this_uart     The this_uart parameter is a pointer to a
+ *                      uart_16550_instance_t structure that holds all data
+ *                      regarding this instance of the Core16550.
+ * @param tx_buffer     The tx_buffer parameter is a pointer to a buffer
+ *                      containing the data to be transmitted.
+ * @param tx_size       The tx_size parameter is the size in bytes, of the data
+ *                      to be transmitted.
+ * @return              This function returns the number of bytes copied
+ *                      into the UART's transmitter FIFO.
+ *
+ * Example:
+ * @code
+ *   void send_using_interrupt(uint8_t * pbuff, size_t tx_size)
+ *   {
+ *       size_t size_in_fifo;
+ *       size_in_fifo = UART_16550_fill_tx_fifo( &g_uart, pbuff, tx_size );
+ *   }
+ * @endcode
+ */
+size_t
+UART_16550_fill_tx_fifo
+(
+    uart_16550_instance_t * this_uart,
+    const uint8_t * tx_buffer,
+    size_t tx_size
+);
+
+/***************************************************************************//**
+ * The UART_16550_get_tx_status() function returns the transmitter status of
+ * the Core16550 instance. It reads both the UART’s line status register (LSR)
+ * and returns the status of the transmit holding register empty (THRE) and
+ * transmitter empty (TEMT) bits.
+ *
+ * @param this_uart     The this_uart parameter is a pointer to a
+ *                      uart_16550_instance_t structure that holds all data
+ *                      regarding this instance of the Core16550.
+ * @return              This function returns the UART’s transmitter status
+ *                      as an 8-bit unsigned integer. The returned value is 0
+ *                      if the transmitter status bits are not set or the
+ *                      function execution failed. The driver provides a set
+ *                      of bit mask constants that should be compared with
+ *                      and/or used to mask the returned value to determine
+ *                      the transmitter status.
+ *                      When the return value is compared to the following
+ *                      bitmasks, a non-zero result indicates that the
+ *                      corresponding transmitter status bit is set:
+ *                      •   UART_16550_THRE     (bit mask = 0x20)
+ *                      •   UART_16550_TEMT     (bit mask = 0x40)
+ *                      When the return value is compared to the following
+ *                      bit mask, a non-zero result indicates that the
+ *                      transmitter is busy or the function execution failed.
+ *                      •   UART_16550_TX_BUSY      (bit mask = 0x00)
+ * Example:
+ * @code
+ *   uint8_t tx_buff[10] = "abcdefghi";
+ *
+ *   UART_16550_polled_tx( &g_uart, tx_buff, sizeof(tx_buff));
+ *
+ *   while ( ! (UART_16550_TEMT & UART_16550_get_tx_status( &g_uart ) )  )
+ *   {
+ *      ;
+ *   }
+ * @endcode
+ */
+uint8_t
+UART_16550_get_tx_status
+(
+    uart_16550_instance_t * this_uart
+);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_16550_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreGPIO/core_gpio.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreGPIO/core_gpio.c
new file mode 100644
index 0000000..e5dbd7e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreGPIO/core_gpio.c
@@ -0,0 +1,461 @@
+/*******************************************************************************
+ * (c) Copyright 2008-2015 Microsemi SoC Products Group. All rights reserved.
+ * 
+ * CoreGPIO bare metal driver implementation.
+ *
+ * SVN $Revision: 7964 $
+ * SVN $Date: 2015-10-09 18:26:53 +0530 (Fri, 09 Oct 2015) $
+ */
+#include "core_gpio.h"
+#include "hal.h"
+#include "hal_assert.h"
+#include "coregpio_regs.h"
+
+/*-------------------------------------------------------------------------*//**
+ *
+ */
+#define GPIO_INT_ENABLE_MASK        (uint32_t)0x00000008UL
+#define OUTPUT_BUFFER_ENABLE_MASK   0x00000004UL
+
+
+#define NB_OF_GPIO  32
+
+#define CLEAR_ALL_IRQ32     (uint32_t)0xFFFFFFFF
+#define CLEAR_ALL_IRQ16     (uint16_t)0xFFFF
+#define CLEAR_ALL_IRQ8      (uint8_t)0xFF
+
+/*-------------------------------------------------------------------------*//**
+ * GPIO_init()
+ * See "core_gpio.h" for details of how to use this function.
+ */
+void GPIO_init
+(
+    gpio_instance_t *   this_gpio,
+    addr_t              base_addr,
+    gpio_apb_width_t    bus_width
+)
+{
+    uint8_t i = 0;
+    addr_t cfg_reg_addr = base_addr;
+    
+    this_gpio->base_addr = base_addr;
+    this_gpio->apb_bus_width = bus_width;
+    
+    /* Clear configuration. */
+    for( i = 0, cfg_reg_addr = base_addr; i < NB_OF_GPIO; ++i )
+    {
+        HW_set_8bit_reg( cfg_reg_addr, 0 );
+        cfg_reg_addr += 4;
+    }
+    /* Clear any pending interrupts */
+    switch( this_gpio->apb_bus_width )
+    {
+        case GPIO_APB_32_BITS_BUS:
+            HAL_set_32bit_reg( this_gpio->base_addr, IRQ, CLEAR_ALL_IRQ32 );
+            break;
+            
+        case GPIO_APB_16_BITS_BUS:
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ0, (uint16_t)CLEAR_ALL_IRQ16 );
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, (uint16_t)CLEAR_ALL_IRQ16 );
+            break;
+            
+        case GPIO_APB_8_BITS_BUS:
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ0, (uint8_t)CLEAR_ALL_IRQ8 );
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ1, (uint8_t)CLEAR_ALL_IRQ8 );
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ2, (uint8_t)CLEAR_ALL_IRQ8 );
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ3, (uint8_t)CLEAR_ALL_IRQ8 );
+            break;
+            
+        default:
+            HAL_ASSERT(0);
+            break;
+    }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * GPIO_config
+ * See "core_gpio.h" for details of how to use this function.
+ */
+void GPIO_config
+(
+    gpio_instance_t *   this_gpio,
+    gpio_id_t           port_id,
+    uint32_t            config
+)
+{
+    HAL_ASSERT( port_id < NB_OF_GPIO );
+    
+    if ( port_id < NB_OF_GPIO )
+    {
+        uint32_t cfg_reg_addr = this_gpio->base_addr;
+        cfg_reg_addr += (port_id * 4);
+        HW_set_32bit_reg( cfg_reg_addr, config );
+        
+        /*
+         * Verify that the configuration was correctly written. Failure to read
+         * back the expected value may indicate that the GPIO port was configured
+         * as part of the hardware flow and cannot be modified through software.
+         * It may also indicate that the base address passed as parameter to
+         * GPIO_init() was incorrect.
+         */
+        HAL_ASSERT( HW_get_32bit_reg( cfg_reg_addr ) == config );
+    }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * GPIO_set_outputs
+ * See "core_gpio.h" for details of how to use this function.
+ */
+void GPIO_set_outputs
+(
+    gpio_instance_t *   this_gpio,
+    uint32_t            value
+)
+{
+    switch( this_gpio->apb_bus_width )
+    {
+        case GPIO_APB_32_BITS_BUS:
+            HAL_set_32bit_reg( this_gpio->base_addr, GPIO_OUT, value );
+            break;
+            
+        case GPIO_APB_16_BITS_BUS:
+            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT0, (uint16_t)value );
+            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint16_t)(value >> 16) );
+            break;
+            
+        case GPIO_APB_8_BITS_BUS:
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT0, (uint8_t)value );
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint8_t)(value >> 8) );
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT2, (uint8_t)(value >> 16) );
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT3, (uint8_t)(value >> 24) );
+            break;
+            
+        default:
+            HAL_ASSERT(0);
+            break;
+    }
+    
+    /*
+     * Verify that the output register was correctly written. Failure to read back
+     * the expected value may indicate that some of the GPIOs may not exist due to
+     * the number of GPIOs selected in the CoreGPIO hardware flow configuration.
+     * It may also indicate that the base address or APB bus width passed as
+     * parameter to the GPIO_init() function do not match the hardware design.
+     */
+    HAL_ASSERT( GPIO_get_outputs( this_gpio ) == value );
+}
+
+/*-------------------------------------------------------------------------*//**
+ * GPIO_get_inputs
+ * See "core_gpio.h" for details of how to use this function.
+ */
+uint32_t GPIO_get_inputs
+(
+    gpio_instance_t *   this_gpio
+)
+{
+    uint32_t gpio_in = 0;
+    
+    switch( this_gpio->apb_bus_width )
+    {
+        case GPIO_APB_32_BITS_BUS:
+            gpio_in = HAL_get_32bit_reg( this_gpio->base_addr, GPIO_IN );
+            break;
+            
+        case GPIO_APB_16_BITS_BUS:
+            gpio_in |= HAL_get_16bit_reg( this_gpio->base_addr, GPIO_IN0 );
+            gpio_in |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_IN1 ) << 16);
+            break;
+            
+        case GPIO_APB_8_BITS_BUS:
+            gpio_in |= HAL_get_8bit_reg( this_gpio->base_addr, GPIO_IN0 );
+            gpio_in |= (HAL_get_8bit_reg( this_gpio->base_addr, GPIO_IN1 ) << 8);
+            gpio_in |= (HAL_get_8bit_reg( this_gpio->base_addr, GPIO_IN2 ) << 16);
+            gpio_in |= (HAL_get_8bit_reg( this_gpio->base_addr, GPIO_IN3 ) << 24);
+            break;
+            
+        default:
+            HAL_ASSERT(0);
+            break;
+    }
+    
+    return gpio_in;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * GPIO_get_outputs
+ * See "core_gpio.h" for details of how to use this function.
+ */
+uint32_t GPIO_get_outputs
+(
+    gpio_instance_t *   this_gpio
+)
+{
+    uint32_t gpio_out = 0;
+    
+    switch( this_gpio->apb_bus_width )
+    {
+        case GPIO_APB_32_BITS_BUS:
+            gpio_out = HAL_get_32bit_reg( this_gpio->base_addr, GPIO_OUT );
+            break;
+            
+        case GPIO_APB_16_BITS_BUS:
+            gpio_out |= HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT0 );
+            gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT1 ) << 16);
+            break;
+            
+        case GPIO_APB_8_BITS_BUS:
+            gpio_out |= HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT0 );
+            gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT1 ) << 8);
+            gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT2 ) << 16);
+            gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT3 ) << 24);
+            break;
+            
+        default:
+            HAL_ASSERT(0);
+            break;
+    }
+    
+    return gpio_out;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * GPIO_set_output
+ * See "core_gpio.h" for details of how to use this function.
+ */
+void GPIO_set_output
+(
+    gpio_instance_t *   this_gpio,
+    gpio_id_t           port_id,
+    uint8_t             value
+)
+{
+    HAL_ASSERT( port_id < NB_OF_GPIO );
+    
+            
+    switch( this_gpio->apb_bus_width )
+    {
+        case GPIO_APB_32_BITS_BUS:
+            {
+                uint32_t outputs_state;
+                
+                outputs_state = HAL_get_32bit_reg( this_gpio->base_addr, GPIO_OUT );
+                if ( 0 == value )
+                {
+                    outputs_state &= ~(1 << port_id);
+                }
+                else
+                {
+                    outputs_state |= 1 << port_id;
+                }
+                HAL_set_32bit_reg( this_gpio->base_addr, GPIO_OUT, outputs_state );
+                
+                /*
+                 * Verify that the output register was correctly written. Failure to read back
+                 * the expected value may indicate that some of the GPIOs may not exist due to
+                 * the number of GPIOs selected in the CoreGPIO hardware flow configuration.
+                 * It may also indicate that the base address or APB bus width passed as
+                 * parameter to the GPIO_init() function do not match the hardware design.
+                 */
+                HAL_ASSERT( HAL_get_32bit_reg( this_gpio->base_addr, GPIO_OUT ) == outputs_state );
+            }
+            break;
+            
+        case GPIO_APB_16_BITS_BUS:
+            {
+                uint16_t outputs_state;
+                uint32_t gpio_out_reg_addr = this_gpio->base_addr + GPIO_OUT_REG_OFFSET + ((port_id >> 4) * 4);
+                
+                outputs_state = HW_get_16bit_reg( gpio_out_reg_addr );
+                if ( 0 == value )
+                {
+                    outputs_state &= ~(1 << (port_id & 0x0F));
+                }
+                else
+                {
+                    outputs_state |= 1 << (port_id & 0x0F);
+                }
+                HW_set_16bit_reg( gpio_out_reg_addr, outputs_state );
+                
+                /*
+                 * Verify that the output register was correctly written. Failure to read back
+                 * the expected value may indicate that some of the GPIOs may not exist due to
+                 * the number of GPIOs selected in the CoreGPIO hardware flow configuration.
+                 * It may also indicate that the base address or APB bus width passed as
+                 * parameter to the GPIO_init() function do not match the hardware design.
+                 */
+                HAL_ASSERT( HW_get_16bit_reg( gpio_out_reg_addr ) == outputs_state );
+            }
+            break;
+            
+        case GPIO_APB_8_BITS_BUS:
+            {
+                uint8_t outputs_state;
+                uint32_t gpio_out_reg_addr = this_gpio->base_addr + GPIO_OUT_REG_OFFSET + ((port_id >> 3) * 4);
+                
+                outputs_state = HW_get_8bit_reg( gpio_out_reg_addr );
+                if ( 0 == value )
+                {
+                    outputs_state &= ~(1 << (port_id & 0x07));
+                }
+                else
+                {
+                    outputs_state |= 1 << (port_id & 0x07);
+                }
+                HW_set_8bit_reg( gpio_out_reg_addr, outputs_state );
+                
+                /*
+                 * Verify that the output register was correctly written. Failure to read back
+                 * the expected value may indicate that some of the GPIOs may not exist due to
+                 * the number of GPIOs selected in the CoreGPIO hardware flow configuration.
+                 * It may also indicate that the base address or APB bus width passed as
+                 * parameter to the GPIO_init() function do not match the hardware design.
+                 */
+                HAL_ASSERT( HW_get_8bit_reg( gpio_out_reg_addr ) == outputs_state );
+            }
+            break;
+            
+        default:
+            HAL_ASSERT(0);
+            break;
+    }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * GPIO_drive_inout
+ * See "core_gpio.h" for details of how to use this function.
+ */
+void GPIO_drive_inout
+(
+    gpio_instance_t *   this_gpio,
+    gpio_id_t           port_id,
+    gpio_inout_state_t  inout_state
+)
+{
+    uint32_t config;
+    uint32_t cfg_reg_addr = this_gpio->base_addr;
+    
+    HAL_ASSERT( port_id < NB_OF_GPIO );
+
+    switch( inout_state )
+    {
+        case GPIO_DRIVE_HIGH:
+            /* Set output high */
+            GPIO_set_output( this_gpio, port_id, 1 );
+            
+            /* Enable output buffer */
+            cfg_reg_addr = this_gpio->base_addr + (port_id * 4);
+            config = HW_get_8bit_reg( cfg_reg_addr );
+            config |= OUTPUT_BUFFER_ENABLE_MASK;
+            HW_set_8bit_reg( cfg_reg_addr, config );
+            break;
+            
+        case GPIO_DRIVE_LOW:
+            /* Set output low */
+            GPIO_set_output( this_gpio, port_id, 0 );
+            
+            /* Enable output buffer */
+            cfg_reg_addr = this_gpio->base_addr + (port_id * 4);
+            config = HW_get_8bit_reg( cfg_reg_addr );
+            config |= OUTPUT_BUFFER_ENABLE_MASK;
+            HW_set_8bit_reg( cfg_reg_addr, config );
+            break;
+            
+        case GPIO_HIGH_Z:
+            /* Disable output buffer */
+            cfg_reg_addr = this_gpio->base_addr + (port_id * 4);
+            config = HW_get_8bit_reg( cfg_reg_addr );
+            config &= ~OUTPUT_BUFFER_ENABLE_MASK;
+            HW_set_8bit_reg( cfg_reg_addr, config );
+            break;
+            
+        default:
+            HAL_ASSERT(0);
+            break;
+    }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * GPIO_enable_irq
+ * See "core_gpio.h" for details of how to use this function.
+ */
+void GPIO_enable_irq
+(
+    gpio_instance_t *   this_gpio,
+    gpio_id_t           port_id
+)
+{
+    uint32_t cfg_value;
+    uint32_t cfg_reg_addr = this_gpio->base_addr;
+   
+    HAL_ASSERT( port_id < NB_OF_GPIO );
+    
+    if ( port_id < NB_OF_GPIO )
+    {
+        cfg_reg_addr += (port_id * 4);
+        cfg_value = HW_get_8bit_reg( cfg_reg_addr );
+        cfg_value |= GPIO_INT_ENABLE_MASK;
+        HW_set_8bit_reg( cfg_reg_addr, cfg_value );
+    }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * GPIO_disable_irq
+ * See "core_gpio.h" for details of how to use this function.
+ */
+void GPIO_disable_irq
+(
+    gpio_instance_t *   this_gpio,
+    gpio_id_t           port_id
+)
+{
+    uint32_t cfg_value;
+    uint32_t cfg_reg_addr = this_gpio->base_addr;
+   
+    HAL_ASSERT( port_id < NB_OF_GPIO );
+    
+    if ( port_id < NB_OF_GPIO )
+    {
+        cfg_reg_addr += (port_id * 4);
+        cfg_value = HW_get_8bit_reg( cfg_reg_addr );
+        cfg_value &= ~GPIO_INT_ENABLE_MASK;
+        HW_set_8bit_reg( cfg_reg_addr, cfg_value );
+    }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * GPIO_clear_irq
+ * See "core_gpio.h" for details of how to use this function.
+ */
+void GPIO_clear_irq
+(
+    gpio_instance_t *   this_gpio,
+    gpio_id_t           port_id
+)
+{
+    uint32_t irq_clr_value = ((uint32_t)1) << ((uint32_t)port_id);
+    
+    switch( this_gpio->apb_bus_width )
+    {
+        case GPIO_APB_32_BITS_BUS:
+            HAL_set_32bit_reg( this_gpio->base_addr, IRQ, irq_clr_value );
+            break;
+            
+        case GPIO_APB_16_BITS_BUS:
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ0, irq_clr_value );
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, irq_clr_value >> 16 );
+            break;
+            
+        case GPIO_APB_8_BITS_BUS:
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ0, irq_clr_value );
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ1, irq_clr_value >> 8 );
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ2, irq_clr_value >> 16 );
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ3, irq_clr_value >> 24 );
+            break;
+            
+        default:
+            HAL_ASSERT(0);
+            break;
+    }
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreGPIO/core_gpio.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreGPIO/core_gpio.h
new file mode 100644
index 0000000..68799be
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreGPIO/core_gpio.h
@@ -0,0 +1,552 @@
+/*******************************************************************************
+ * (c) Copyright 2008-2015 Microsemi SoC Products Group. All rights reserved.
+ * 
+ *  CoreGPIO bare metal driver public API.
+ *
+ * SVN $Revision: 7964 $
+ * SVN $Date: 2015-10-09 18:26:53 +0530 (Fri, 09 Oct 2015) $
+ */
+
+/*=========================================================================*//**
+  @mainpage CoreGPIO Bare Metal Driver.
+
+  @section intro_sec Introduction
+  The CoreGPIO hardware IP includes up to 32 general purpose input output GPIOs.
+  This driver provides a set of functions for controlling the GPIOs as part of a
+  bare metal system where no operating system is available. These drivers
+  can be adapted for use as part of an operating system but the implementation
+  of the adaptation layer between this driver and the operating system's driver
+  model is outside the scope of this driver.
+  
+  @section driver_configuration Driver Configuration
+  The CoreGPIO individual IOs can be configured either in the hardware flow or
+  as part of the software application through calls to the GPIO_config() function.
+  GPIOs configured as as part of the hardware is fixed and cannot be modified
+  using a call to the GPI_config() function.
+  
+  @section theory_op Theory of Operation
+  The CoreGPIO driver uses the Actel Hardware Abstraction Layer (HAL) to access
+  hardware registers. You must ensure that the Actel HAL is included as part of
+  your software project. The Actel HAL is available through the Actel Firmware
+  Catalog.
+  
+  The CoreGPIO driver functions are logically grouped into the following groups:
+    - Initiliazation
+    - Configuration
+    - Reading and writing GPIO state
+    - Interrupt control
+  
+  The CoreGPIO driver is initialized through a call to the GPIO_init() function.
+  The GPIO_init() function must be called before any other GPIO driver functions
+  can be called.
+  
+  Each GPIO port is individually configured through a call to the
+  GPIO_config() function. Configuration includes deciding if a GPIO port
+  will be used as input, output or both. GPIO ports configured as inputs can be
+  further configured to generate interrupts based on the input's state.
+  Interrupts can be level or edge sensitive.
+  Please note that a CoreGPIO hardware instance can be generated, as part of the
+  hardware flow, with a fixed configuration for some or all of its IOs. Attempting
+  to modify the configuration of such a hardware configured IO using the
+  GPIO_config() function has no effect.
+  
+  The state of the GPIO ports can be read and written using the following
+  functions:
+    - GPIO_get_inputs()
+    - GPIO_get_outputs()
+    - GPIO_set_outputs()
+    - GPIO_drive_inout()
+    
+  Interrupts generated by GPIO ports configured as inputs are controlled using
+  the following functions:
+    - GPIO_enable_irq()
+    - GPIO_disable_irq()
+    - GPIO_clear_irq()
+  
+ *//*=========================================================================*/
+#ifndef CORE_GPIO_H_
+#define CORE_GPIO_H_
+
+#include 
+#include "cpu_types.h"
+
+/*-------------------------------------------------------------------------*//**
+  The gpio_id_t enumeration is used to identify GPIOs as part of the
+  parameter to functions:
+    - GPIO_config(),
+    - GPIO_drive_inout(),
+    - GPIO_enable_int(),
+    - GPIO_disable_int(),
+    - GPIO_clear_int()
+ */
+typedef enum __gpio_id_t
+{
+    GPIO_0 = 0,
+    GPIO_1 = 1,
+    GPIO_2 = 2,
+    GPIO_3 = 3,
+    GPIO_4 = 4,
+    GPIO_5 = 5,
+    GPIO_6 = 6,
+    GPIO_7 = 7,
+    GPIO_8 = 8,
+    GPIO_9 = 9,
+    GPIO_10 = 10,
+    GPIO_11 = 11,
+    GPIO_12 = 12,
+    GPIO_13 = 13,
+    GPIO_14 = 14,
+    GPIO_15 = 15,
+    GPIO_16 = 16,
+    GPIO_17 = 17,
+    GPIO_18 = 18,
+    GPIO_19 = 19,
+    GPIO_20 = 20,
+    GPIO_21 = 21,
+    GPIO_22 = 22,
+    GPIO_23 = 23,
+    GPIO_24 = 24,
+    GPIO_25 = 25,
+    GPIO_26 = 26,
+    GPIO_27 = 27,
+    GPIO_28 = 28,
+    GPIO_29 = 29,
+    GPIO_30 = 30,
+    GPIO_31 = 31
+} gpio_id_t;
+
+typedef enum __gpio_apb_width_t
+{
+    GPIO_APB_8_BITS_BUS = 0,
+    GPIO_APB_16_BITS_BUS = 1,
+    GPIO_APB_32_BITS_BUS = 2,
+    GPIO_APB_UNKNOWN_BUS_WIDTH = 3
+} gpio_apb_width_t;
+
+/*-------------------------------------------------------------------------*//**
+ */
+typedef struct __gpio_instance_t
+{
+    addr_t              base_addr;
+    gpio_apb_width_t    apb_bus_width;
+} gpio_instance_t;
+
+/*-------------------------------------------------------------------------*//**
+  GPIO ports definitions used to identify GPIOs as part of the parameter to
+  function GPIO_set_outputs().
+  These definitions can also be used to identity GPIO through logical
+  operations on the return value of function GPIO_get_inputs().
+ */
+#define GPIO_0_MASK		    0x00000001UL
+#define GPIO_1_MASK		    0x00000002UL
+#define GPIO_2_MASK         0x00000004UL
+#define GPIO_3_MASK	        0x00000008UL
+#define GPIO_4_MASK	        0x00000010UL
+#define GPIO_5_MASK	        0x00000020UL
+#define GPIO_6_MASK	        0x00000040UL
+#define GPIO_7_MASK	        0x00000080UL
+#define GPIO_8_MASK	        0x00000100UL
+#define GPIO_9_MASK		    0x00000200UL
+#define GPIO_10_MASK		0x00000400UL
+#define GPIO_11_MASK		0x00000800UL
+#define GPIO_12_MASK		0x00001000UL
+#define GPIO_13_MASK		0x00002000UL
+#define GPIO_14_MASK		0x00004000UL
+#define GPIO_15_MASK		0x00008000UL
+#define GPIO_16_MASK		0x00010000UL
+#define GPIO_17_MASK		0x00020000UL
+#define GPIO_18_MASK		0x00040000UL
+#define GPIO_19_MASK		0x00080000UL
+#define GPIO_20_MASK		0x00100000UL
+#define GPIO_21_MASK		0x00200000UL
+#define GPIO_22_MASK		0x00400000UL
+#define GPIO_23_MASK		0x00800000UL
+#define GPIO_24_MASK		0x01000000UL
+#define GPIO_25_MASK		0x02000000UL
+#define GPIO_26_MASK		0x04000000UL
+#define GPIO_27_MASK		0x08000000UL
+#define GPIO_28_MASK		0x10000000UL
+#define GPIO_29_MASK		0x20000000UL
+#define GPIO_30_MASK		0x40000000UL
+#define GPIO_31_MASK		0x80000000UL
+
+/*-------------------------------------------------------------------------*//**
+ * GPIO modes
+ */
+#define GPIO_INPUT_MODE              0x0000000002UL
+#define GPIO_OUTPUT_MODE             0x0000000005UL
+#define GPIO_INOUT_MODE              0x0000000003UL
+
+/*-------------------------------------------------------------------------*//**
+ * Possible GPIO inputs interrupt configurations.
+ */
+#define GPIO_IRQ_LEVEL_HIGH			0x0000000000UL
+#define GPIO_IRQ_LEVEL_LOW			0x0000000020UL
+#define GPIO_IRQ_EDGE_POSITIVE		0x0000000040UL
+#define GPIO_IRQ_EDGE_NEGATIVE		0x0000000060UL
+#define GPIO_IRQ_EDGE_BOTH			0x0000000080UL
+
+/*-------------------------------------------------------------------------*//**
+ * Possible states for GPIO configured as INOUT.
+ */
+typedef enum gpio_inout_state
+{
+    GPIO_DRIVE_LOW = 0,
+    GPIO_DRIVE_HIGH,
+    GPIO_HIGH_Z
+} gpio_inout_state_t;
+
+/*-------------------------------------------------------------------------*//**
+  The GPIO_init() function initialises a CoreGPIO hardware instance and the data
+  structure associated with the CoreGPIO hardware instance.
+  Please note that a CoreGPIO hardware instance can be generated with a fixed
+  configuration for some or all of its IOs as part of the hardware flow. Attempting
+  to modify the configuration of such a hardware configured IO using the
+  GPIO_config() function has no effect.
+
+  @param this_gpio
+    Pointer to the gpio_instance_t data structure instance holding all data
+    regarding the CoreGPIO hardware instance being initialized. A pointer to the
+    same data structure will be used in subsequent calls to the CoreGPIO driver
+    functions in order to identify the CoreGPIO instance that should perform the
+    operation implemented by the called driver function.
+
+  @param base_addr
+    The base_addr parameter is the base address in the processor's memory map for
+    the registers of the GPIO instance being initialized.
+    
+  @param bus_width
+    The bus_width parameter informs the driver of the APB bus width selected during
+    the hardware flow configuration of the CoreGPIO hardware instance. It indicates
+    to the driver whether the CoreGPIO hardware registers will be visible as 8, 16
+    or 32 bits registers. Allowed value are:
+        - GPIO_APB_8_BITS_BUS
+        - GPIO_APB_16_BITS_BUS
+        - GPIO_APB_32_BITS_BUS
+  
+  @return
+    none.
+    
+  Example:
+  @code
+    #define COREGPIO_BASE_ADDR  0xC2000000
+    
+    gpio_instance_t g_gpio;
+    
+    void system_init( void )
+    {
+        GPIO_init( &g_gpio,	COREGPIO_BASE_ADDR, GPIO_APB_32_BITS_BUS );
+    }
+  @endcode
+  */
+void GPIO_init
+(
+    gpio_instance_t *   this_gpio,
+    addr_t              base_addr,
+    gpio_apb_width_t    bus_width
+);
+
+/*-------------------------------------------------------------------------*//**
+  The GPIO_config() function is used to configure an individual GPIO port.
+ 
+  @param this_gpio
+    The this_gpio parameter is a pointer to the gpio_instance_t structure holding
+    all data regarding the CoreGPIO instance controlled through this function call.
+
+  @param port_id
+    The port_id parameter identifies the GPIO port to be configured.
+    An enumeration item of the form GPIO_n where n is the number of the GPIO
+    port is used to identify the GPIO port. For example GPIO_0 identifies the
+    first GPIO port and GPIO_31 the last one.
+    
+  @param config
+    The config parameter specifies the configuration to be applied to the GPIO
+    port identified by the first parameter. It is a logical OR of GPIO mode and
+    the interrupt mode. The interrupt mode is only relevant if the GPIO is
+    configured as input.
+       Possible modes are:
+           - GPIO_INPUT_MODE,
+           - GPIO_OUTPUT_MODE,
+           - GPIO_INOUT_MODE.
+       Possible interrupt modes are:
+           - GPIO_IRQ_LEVEL_HIGH,
+           - GPIO_IRQ_LEVEL_LOW,
+           - GPIO_IRQ_EDGE_POSITIVE,
+           - GPIO_IRQ_EDGE_NEGATIVE,
+           - GPIO_IRQ_EDGE_BOTH
+ 
+  @return
+    none.
+    
+  For example the following call will configure GPIO 4 as an input generating
+  interrupts on a low to high transition of the input:
+  @code
+  GPIO_config( &g_gpio, GPIO_4, GPIO_INPUT_MODE | GPIO_IRQ_EDGE_POSITIVE );
+  @endcode
+ */
+void GPIO_config
+(
+    gpio_instance_t *   this_gpio,
+    gpio_id_t           port_id,
+    uint32_t            config
+);
+
+/*-------------------------------------------------------------------------*//**
+  The GPIO_set_outputs() function is used to set the state of the GPIO ports
+  configured as outputs.
+ 
+  @param this_gpio
+    The this_gpio parameter is a pointer to the gpio_instance_t structure holding
+    all data regarding the CoreGPIO instance controlled through this function call.
+
+  @param value
+    The value parameter specifies the state of the GPIO ports configured as
+    outputs. It is a bit mask of the form (GPIO_n_MASK | GPIO_m_MASK) where n
+    and m are numbers identifying GPIOs.
+    For example (GPIO_0_MASK | GPIO_1_MASK | GPIO_2_MASK ) specifies that the
+    first, second and third GPIOs' must be set high and all other outputs set
+    low.
+
+  @return
+    none.
+    
+  Example 1:
+    Set GPIOs outputs 0 and 8 high and all other GPIO outputs low.
+    @code
+        GPIO_set_outputs( &g_gpio, GPIO_0_MASK | GPIO_8_MASK );
+    @endcode
+
+  Example 2:
+    Set GPIOs outputs 2 and 4 low without affecting other GPIO outputs.
+    @code
+        uint32_t gpio_outputs;
+        gpio_outputs = GPIO_get_outputs( &g_gpio );
+        gpio_outputs &= ~( GPIO_2_MASK | GPIO_4_MASK );
+        GPIO_set_outputs( &g_gpio, gpio_outputs );
+    @endcode
+
+  @see GPIO_get_outputs()
+ */
+void GPIO_set_outputs
+(
+    gpio_instance_t *   this_gpio,
+    uint32_t            value
+);
+
+/*-------------------------------------------------------------------------*//**
+  The GPIO_set_output() function is used to set the state of a single GPIO
+  port configured as output.
+ 
+  @param this_gpio
+    The this_gpio parameter is a pointer to the gpio_instance_t structure holding
+    all data regarding the CoreGPIO instance controlled through this function call.
+
+  @param port_id
+    The port_id parameter specifies the GPIO port that will have its output set
+    by a call to this function.
+  
+  @param value
+    The value parameter specifies the desired state for the GPIO output. A value
+    of 0 will set the output low and a value of 1 will set the port high.
+  
+  @return
+    none.
+ */
+void GPIO_set_output
+(
+    gpio_instance_t *   this_gpio,
+    gpio_id_t           port_id,
+    uint8_t             value
+);
+
+/*-------------------------------------------------------------------------*//**
+  The GPIO_get_inputs() function is used to read the state of all GPIOs
+  confgured as inputs.
+ 
+  @param this_gpio
+    The this_gpio parameter is a pointer to the gpio_instance_t structure holding
+    all data regarding the CoreGPIO instance controlled through this function call.
+
+  @return
+    This function returns a 32 bit unsigned integer where each bit represents
+    the state of an input. The least significant bit representing the state of
+    GPIO 0 and the most significant bit the state of GPIO 31.
+ */
+uint32_t GPIO_get_inputs
+(
+    gpio_instance_t *   this_gpio
+);
+
+/*-------------------------------------------------------------------------*//**
+  The GPIO_get_outputs() function is used to read the current state of all
+  GPIO outputs.
+ 
+  @param this_gpio
+    The this_gpio parameter is a pointer to the gpio_instance_t structure holding
+    all data regarding the CoreGPIO instance controlled through this function call.
+
+  @return
+     This function returns a 32 bit unsigned integer where each bit represents
+     the state of an output. The least significant bit representing the state
+     of GPIO 0 and the most significant bit the state of GPIO 31.
+ */
+uint32_t GPIO_get_outputs
+(
+    gpio_instance_t *   this_gpio
+);
+
+/*-------------------------------------------------------------------------*//**
+  The GPIO_drive_inout() function is used to set the output state of a
+  GPIO configured as INOUT. An INOUT GPIO can be in one of three states:
+    - high
+    - low
+    - high impedance
+  An INOUT output would typically be used where several devices can drive the
+  state of a signal. The high and low states are equivalent to the high and low
+  states of a GPIO configured as output. The high impedance state is used to
+  prevent the GPIO from driving the state of the output and therefore allow
+  reading the state of the GPIO as an input.
+  Please note that the GPIO port you wish to use as INOUT through this function
+  must be configurable through software. Therefore the GPIO ports used as INOUT
+  must not have a fixed configuration selected as part of the hardware flow.
+ 
+  @param this_gpio
+    The this_gpio parameter is a pointer to the gpio_instance_t structure holding
+    all data regarding the CoreGPIO instance controlled through this function call.
+
+  @param port_id
+    The port_id parameter identifies the GPIO for whcih this function will
+    change the output state.
+    An enumeration item of the form GPIO_n where n is the number of the GPIO
+    port is used to identify the GPIO port. For example GPIO_0 identifies the
+    first GPIO port and GPIO_31 the last one.
+    
+  @param inout_state
+    The inout_state parameter specifies the state of the I/O identified by the
+    first parameter. Possible states are:
+                           - GPIO_DRIVE_HIGH,
+                           - GPIO_DRIVE_LOW,
+                           - GPIO_HIGH_Z (high impedance)
+
+  @return
+    none.
+    
+  Example:
+    The call to GPIO_drive_inout() below will set the GPIO 7 output to
+    high impedance state.
+    @code
+    GPIO_drive_inout( &g_gpio, GPIO_7, GPIO_HIGH_Z );
+    @endcode
+ */
+void GPIO_drive_inout
+(
+    gpio_instance_t *   this_gpio,
+    gpio_id_t           port_id,
+    gpio_inout_state_t  inout_state
+);
+
+/*-------------------------------------------------------------------------*//**
+  The GPIO_enable_irq() function is used to enable an interrupt to be
+  generated based on the state of the input identified as parameter.
+ 
+  @param this_gpio
+    The this_gpio parameter is a pointer to the gpio_instance_t structure holding
+    all data regarding the CoreGPIO instance controlled through this function call.
+
+  @param port_id
+    The port_id parameter identifies the GPIO input the call to
+    GPIO_enable_irq() will enable to generate interrupts.
+    An enumeration item of the form GPIO_n where n is the number of the GPIO
+    port is used to identify the GPIO port. For example GPIO_0 identifies the
+    first GPIO port and GPIO_31 the last one.
+    
+  @return
+    none.
+    
+  Example:
+    The call to GPIO_enable_irq() below will allow GPIO 8 to generate
+    interrupts.
+    @code
+    GPIO_enable_irq( &g_gpio, GPIO_8 );
+    @endcode
+ */
+void GPIO_enable_irq
+(
+    gpio_instance_t *   this_gpio,
+    gpio_id_t           port_id
+);
+
+/*-------------------------------------------------------------------------*//**
+  The GPIO_disable_irq() function is used to disable interrupt from being
+  generated based on the state of the input specified as parameter.
+ 
+  @param this_gpio
+    The this_gpio parameter is a pointer to the gpio_instance_t structure holding
+    all data regarding the CoreGPIO instance controlled through this function call.
+
+  @param port_id
+    The port_id parameter identifies the GPIO input the call to
+    GPIO_disable_irq() will disable from generating interrupts.
+    An enumeration item of the form GPIO_n where n is the number of the GPIO
+    port is used to identify the GPIO port. For example GPIO_0 identifies the
+    first GPIO port and GPIO_31 the last one.
+ 
+  @return
+    none.
+    
+  Example:
+    The call to GPIO_disable_irq() below will prevent GPIO 8 from generating
+    interrupts.
+    @code
+    GPIO_disable_irq( &g_gpio, GPIO_8 );
+    @endcode
+ */
+void GPIO_disable_irq
+(
+    gpio_instance_t *   this_gpio,
+    gpio_id_t           port_id
+);
+
+/*-------------------------------------------------------------------------*//**
+  The GPIO_clear_irq() function is used to clear the interrupt generated by
+  the GPIO specified as parameter. The GPIO_clear_irq() function  must be
+  called as part of a GPIO interrupt service routine (ISR) in order to prevent
+  the same interrupt event retriggering a call to the GPIO ISR.
+  Please note that interrupts may also need to be cleared in the processor's
+  interrupt controller.
+ 
+  @param this_gpio
+    The this_gpio parameter is a pointer to the gpio_instance_t structure holding
+    all data regarding the CoreGPIO instance controlled through this function call.
+
+  @param port_id
+    The port_id parameter identifies the GPIO input for which to clear the
+    interrupt.
+    An enumeration item of the form GPIO_n where n is the number of the GPIO
+    port is used to identify the GPIO port. For example GPIO_0 identifies the
+    first GPIO port and GPIO_31 the last one.
+    
+  @return
+    none.
+    
+  Example:
+    The example below demonstrates the use of the GPIO_clear_irq() function as
+    part of the GPIO 9 interrupt service routine on a Cortex-M processor.  
+    @code
+    void GPIO9_IRQHandler( void )
+    {
+        do_interrupt_processing();
+        
+        GPIO_clear_irq( &g_gpio, GPIO_9 );
+        
+        NVIC_ClearPendingIRQ( GPIO9_IRQn );
+    }
+    @endcode
+ */
+void GPIO_clear_irq
+(
+    gpio_instance_t *   this_gpio,
+    gpio_id_t           port_id
+);
+
+#endif /* CORE_GPIO_H_ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreGPIO/coregpio_regs.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreGPIO/coregpio_regs.h
new file mode 100644
index 0000000..afbbfbc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreGPIO/coregpio_regs.h
@@ -0,0 +1,40 @@
+/*******************************************************************************
+ * (c) Copyright 2009-2015 Microsemi SoC Products Group. All rights reserved.
+ * 
+ * SVN $Revision: 7964 $
+ * SVN $Date: 2015-10-09 18:26:53 +0530 (Fri, 09 Oct 2015) $
+ */
+#ifndef __CORE_GPIO_REGISTERS_H
+#define __CORE_GPIO_REGISTERS_H		1
+
+/*------------------------------------------------------------------------------
+ * 
+ */
+#define IRQ_REG_OFFSET          0x80
+
+#define IRQ0_REG_OFFSET         0x80
+#define IRQ1_REG_OFFSET         0x84
+#define IRQ2_REG_OFFSET         0x88
+#define IRQ3_REG_OFFSET         0x8C
+
+/*------------------------------------------------------------------------------
+ * 
+ */
+#define GPIO_IN_REG_OFFSET      0x90
+
+#define GPIO_IN0_REG_OFFSET     0x90
+#define GPIO_IN1_REG_OFFSET     0x94
+#define GPIO_IN2_REG_OFFSET     0x98
+#define GPIO_IN3_REG_OFFSET     0x9C
+
+/*------------------------------------------------------------------------------
+ * 
+ */
+#define GPIO_OUT_REG_OFFSET     0xA0
+
+#define GPIO_OUT0_REG_OFFSET    0xA0
+#define GPIO_OUT1_REG_OFFSET    0xA4
+#define GPIO_OUT2_REG_OFFSET    0xA8
+#define GPIO_OUT3_REG_OFFSET    0xAC
+
+#endif /* __CORE_GPIO_REGISTERS_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreI2C/core_i2c.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreI2C/core_i2c.c
new file mode 100644
index 0000000..daa1887
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreI2C/core_i2c.c
@@ -0,0 +1,1563 @@
+/*******************************************************************************
+ * (c) Copyright 2009-2015 Microsemi  SoC Products Group.  All rights reserved.
+ * 
+ * CoreI2C software driver implementation.
+ * 
+ * SVN $Revision: 7984 $
+ * SVN $Date: 2015-10-12 12:07:40 +0530 (Mon, 12 Oct 2015) $
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "cpu_types.h"
+#include "core_smbus_regs.h"
+#include "core_i2c.h"
+#include "hal.h"
+#include "hal_assert.h"
+
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * I2C transaction direction.
+ */
+#define WRITE_DIR    0u
+#define READ_DIR     1u
+
+/* -- TRANSACTIONS TYPES -- */
+#define NO_TRANSACTION                      0u
+#define MASTER_WRITE_TRANSACTION            1u
+#define MASTER_READ_TRANSACTION             2u
+#define MASTER_RANDOM_READ_TRANSACTION      3u
+#define WRITE_SLAVE_TRANSACTION             4u
+#define READ_SLAVE_TRANSACTION              5u
+
+/* -- SMBUS H/W STATES -- */
+/* -- MASTER STATES -- */
+#define ST_BUS_ERROR        0x00u           /* Bus error during MST or selected slave modes */
+#define ST_I2C_IDLE         0xF8u           /* No activity and no interrupt either... */
+#define ST_START            0x08u           /* start condition sent */
+#define ST_RESTART          0x10u           /* repeated start */
+#define ST_SLAW_ACK         0x18u           /* SLA+W sent, ack received */
+#define ST_SLAW_NACK        0x20u           /* SLA+W sent, nack received */
+#define ST_TX_DATA_ACK      0x28u           /* Data sent, ACK'ed */
+#define ST_TX_DATA_NACK     0x30u           /* Data sent, NACK'ed */
+#define ST_LOST_ARB         0x38u           /* Master lost arbitration */
+#define ST_SLAR_ACK         0x40u           /* SLA+R sent, ACK'ed */
+#define ST_SLAR_NACK        0x48u           /* SLA+R sent, NACK'ed */
+#define ST_RX_DATA_ACK      0x50u           /* Data received, ACK sent */
+#define ST_RX_DATA_NACK     0x58u           /* Data received, NACK sent */
+#define ST_RESET_ACTIVATED  0xD0u           /* Master reset is activated */
+#define ST_STOP_TRANSMIT    0xE0u           /* Stop has been transmitted */
+
+/* -- SLAVE STATES -- */
+#define ST_SLAVE_SLAW       0x60u           /* SLA+W received */
+#define ST_SLAVE_SLAR_ACK   0xA8u           /* SLA+R received, ACK returned */
+#define ST_SLV_LA           0x68u           /* Slave lost arbitration */
+#define ST_GCA              0x70u           /* GCA received */
+#define ST_GCA_LA           0x78u           /* GCA lost arbitration */
+#define ST_RDATA            0x80u           /* Data received */
+#define ST_SLA_NACK         0x88u           /* Slave addressed, NACK returned */
+#define ST_GCA_ACK          0x90u           /* Previously addresses with GCA, data ACKed */
+#define ST_GCA_NACK         0x98u           /* GCA addressed, NACK returned */
+#define ST_RSTOP            0xA0u           /* Stop received */
+#define ST_SLARW_LA         0xB0u           /* Arbitration lost */
+#define ST_RACK             0xB8u           /* Byte sent, ACK received */
+#define ST_SLAVE_RNACK      0xC0u           /* Byte sent, NACK received */
+#define ST_FINAL            0xC8u           /* Final byte sent, ACK received */
+#define ST_SLV_RST          0xD8u           /* Slave reset state */
+
+
+/* I2C Channel base offset */
+#define CHANNEL_BASE_SHIFT    5u
+#define CHANNEL_MASK        0x1E0u
+
+/*
+ * Maximum address offset length in slave write-read transactions.
+ * A maximum of two bytes will be interpreted as address offset within the slave
+ * tx buffer.
+ */
+#define MAX_OFFSET_LENGTH       2u
+
+/*------------------------------------------------------------------------------
+ * I2C interrupts control functions implemented "i2c_interrupt.c".
+ * the implementation of these functions depend on the underlying hardware
+ * design and how the CoreI2C interrupt line is connected to the system's
+ * interrupt controller.
+ */
+void I2C_enable_irq( i2c_instance_t * this_i2c );
+void I2C_disable_irq( i2c_instance_t * this_i2c );
+static void enable_slave_if_required(i2c_instance_t * this_i2c);
+
+/*------------------------------------------------------------------------------
+ * I2C_init()
+ * See "core_i2c.h" for details of how to use this function.
+ */
+void I2C_init
+(
+    i2c_instance_t * this_i2c,
+    addr_t base_address,
+    uint8_t ser_address,
+    i2c_clock_divider_t ser_clock_speed
+)
+{
+    psr_t saved_psr;
+    uint_fast16_t clock_speed = (uint_fast16_t)ser_clock_speed;
+    
+    /*
+     * We need to disable ints while doing this as there is no guarantee we
+     * have not been called already and the ISR is active.
+     */
+
+   saved_psr=HAL_disable_interrupts();
+    
+    /*
+     * Initialize all items of the this_i2c data structure to zero. This
+     * initializes all state variables to their init value. It relies on
+     * the fact that NO_TRANSACTION, I2C_SUCCESS and I2C_RELEASE_BUS all
+     * have an actual value of zero.
+     */
+    memset(this_i2c, 0, sizeof(i2c_instance_t));
+    
+    /*
+     * Set base address of I2C hardware used by this instance.
+     */
+    this_i2c->base_address = base_address;
+
+    /*
+     * Update Serial address of the device
+     */
+    this_i2c->ser_address = ((uint_fast8_t)ser_address << 1u);
+    
+    /*
+     * Configure hardware.
+     */
+    HAL_set_8bit_reg_field(this_i2c->base_address, ENS1, 0x00); /* Reset I2C hardware. */
+    HAL_set_8bit_reg_field(this_i2c->base_address, ENS1, 0x01); /* set enable bit */
+    HAL_set_8bit_reg_field(this_i2c->base_address, CR2, ( (clock_speed >> 2) & 0x01) );
+    HAL_set_8bit_reg_field(this_i2c->base_address, CR1, ( (clock_speed >> 1) & 0x01) );
+    HAL_set_8bit_reg_field(this_i2c->base_address, CR0, ( clock_speed & 0x01) );
+
+    HAL_set_8bit_reg(this_i2c->base_address, ADDRESS, this_i2c->ser_address);
+    HAL_set_8bit_reg(this_i2c->base_address, ADDRESS1, this_i2c->ser_address);
+    
+    /*
+     * Finally safe to enable interrupts.
+     */
+
+   	HAL_restore_interrupts( saved_psr );
+}
+/*------------------------------------------------------------------------------
+ * I2C_channel_init()
+ * See "core_i2c.h" for details of how to use this function.
+ */
+void I2C_channel_init
+(
+    i2c_instance_t * this_i2c_channel,
+    i2c_instance_t * this_i2c,
+    i2c_channel_number_t channel_number,
+    i2c_clock_divider_t ser_clock_speed
+)
+{
+    psr_t saved_psr;
+    uint_fast16_t clock_speed = (uint_fast16_t)ser_clock_speed;
+    
+    HAL_ASSERT(channel_number < I2C_MAX_CHANNELS);
+    HAL_ASSERT(I2C_CHANNEL_0 != channel_number);
+
+    /* 
+     * Cannot allow channel 0 in this function as we will trash the hardware
+     * base address and slave address.
+     */
+    if ((channel_number < I2C_MAX_CHANNELS) &&
+        (I2C_CHANNEL_0 != channel_number))
+    {
+        /*
+         * We need to disable ints while doing this as the hardware should already
+         * be active at this stage.
+         */
+
+   	saved_psr=HAL_disable_interrupts();
+        /*
+         * Initialize channel data.
+         */
+        memset(this_i2c_channel, 0, sizeof(i2c_instance_t));
+        
+        this_i2c_channel->base_address =
+               ((this_i2c->base_address) & ~((addr_t)CHANNEL_MASK)) 
+            | (((addr_t)channel_number) << CHANNEL_BASE_SHIFT);
+
+        this_i2c_channel->ser_address = this_i2c->ser_address;
+
+        HAL_set_8bit_reg_field(this_i2c_channel->base_address, ENS1, 0x00); /* Reset I2C channel hardware. */
+        HAL_set_8bit_reg_field(this_i2c_channel->base_address, ENS1, 0x01); /* set enable bit */
+        HAL_set_8bit_reg_field(this_i2c_channel->base_address, CR2, ( (clock_speed >> 2) & 0x01) );
+        HAL_set_8bit_reg_field(this_i2c_channel->base_address, CR1, ( (clock_speed >> 1) & 0x01) );
+        HAL_set_8bit_reg_field(this_i2c_channel->base_address, CR0, ( clock_speed & 0x01) );
+        /*
+         * Finally safe to enable interrupts.
+         */
+
+   	HAL_restore_interrupts( saved_psr );
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_write()
+ * See "core_i2c.h" for details of how to use this function.
+ */
+void I2C_write
+(
+    i2c_instance_t * this_i2c,
+    uint8_t serial_addr,
+    const uint8_t * write_buffer,
+    uint16_t write_size,
+    uint8_t options
+)
+{
+    psr_t saved_psr;
+    volatile uint8_t stat_ctrl;
+
+
+   	saved_psr=HAL_disable_interrupts();
+
+    /* Update the transaction only when there is no transaction going on I2C */
+    if( this_i2c->transaction == NO_TRANSACTION)
+    {
+      this_i2c->transaction = MASTER_WRITE_TRANSACTION;
+    }
+
+    /* Update the Pending transaction information so that transaction can restarted */
+    this_i2c->pending_transaction = MASTER_WRITE_TRANSACTION ;
+
+    /* Update target address */
+    this_i2c->target_addr = (uint_fast8_t)serial_addr << 1u;
+    this_i2c->dir = WRITE_DIR;
+    this_i2c->master_tx_buffer = write_buffer;
+    this_i2c->master_tx_size = write_size;
+    this_i2c->master_tx_idx = 0u;
+
+    /* Set I2C status in progress */
+    this_i2c->master_status = I2C_IN_PROGRESS;
+    this_i2c->options = options;
+
+    if(I2C_IN_PROGRESS == this_i2c->slave_status)
+    {
+        this_i2c->is_transaction_pending = 1u;
+    }
+    else
+    {
+        HAL_set_8bit_reg_field(this_i2c->base_address, STA, 0x01u);
+    }
+
+    /*
+     * Clear interrupts if required (depends on repeated starts).
+     * Since the Bus is on hold, only then prior status needs to
+     * be cleared.
+     */
+    if ( I2C_HOLD_BUS == this_i2c->bus_status )
+    {
+        HAL_set_8bit_reg_field(this_i2c->base_address, SI, 0x00u);
+    }
+
+    stat_ctrl = HAL_get_8bit_reg( this_i2c->base_address, STATUS);
+    stat_ctrl = stat_ctrl;  /* Avoids lint warning. */
+
+    /* Enable the interrupt. ( Re-enable) */
+    I2C_enable_irq( this_i2c );
+
+
+   	HAL_restore_interrupts(saved_psr);
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_read()
+ * See "core_i2c.h" for details of how to use this function.
+ */
+void I2C_read
+(
+    i2c_instance_t * this_i2c,
+    uint8_t serial_addr,
+    uint8_t * read_buffer,
+    uint16_t read_size,
+    uint8_t options
+)
+{
+    psr_t saved_psr;
+    volatile uint8_t stat_ctrl;
+
+
+   	saved_psr=HAL_disable_interrupts();
+    
+    /* Update the transaction only when there is no transaction going on I2C */
+    if( this_i2c->transaction == NO_TRANSACTION)
+    {
+      this_i2c->transaction = MASTER_READ_TRANSACTION;
+    }
+
+    /* Update the Pending transaction information so that transaction can restarted */
+    this_i2c->pending_transaction = MASTER_READ_TRANSACTION ;
+
+    /* Update target address */
+    this_i2c->target_addr = (uint_fast8_t)serial_addr << 1u;
+
+    this_i2c->dir = READ_DIR;
+
+    this_i2c->master_rx_buffer = read_buffer;
+    this_i2c->master_rx_size = read_size;
+    this_i2c->master_rx_idx = 0u;
+
+    /* Set I2C status in progress */
+    this_i2c->master_status = I2C_IN_PROGRESS;
+
+    this_i2c->options = options;
+    
+    if(I2C_IN_PROGRESS == this_i2c->slave_status)
+    {
+        this_i2c->is_transaction_pending = 1u;
+    }
+    else
+    {
+        HAL_set_8bit_reg_field(this_i2c->base_address, STA, 0x01u);
+    }
+
+    /*
+     * Clear interrupts if required (depends on repeated starts).
+     * Since the Bus is on hold, only then prior status needs to
+     * be cleared.
+     */
+    if ( I2C_HOLD_BUS == this_i2c->bus_status )
+    {
+        HAL_set_8bit_reg_field(this_i2c->base_address, SI, 0x00u);
+    }
+
+    stat_ctrl = HAL_get_8bit_reg( this_i2c->base_address, STATUS);
+    stat_ctrl = stat_ctrl;  /* Avoids lint warning. */
+
+    /* Enable the interrupt. ( Re-enable) */
+    I2C_enable_irq( this_i2c );
+
+   	HAL_restore_interrupts( saved_psr );
+
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_write_read()
+ * See "core_i2c.h" for details of how to use this function.
+ */
+void I2C_write_read
+(
+    i2c_instance_t * this_i2c,
+    uint8_t serial_addr,
+    const uint8_t * addr_offset,
+    uint16_t offset_size,
+    uint8_t * read_buffer,
+    uint16_t read_size,
+    uint8_t options
+)
+{
+    HAL_ASSERT(offset_size > 0u);
+    HAL_ASSERT(addr_offset != (uint8_t *)0);
+    HAL_ASSERT(read_size > 0u);
+    HAL_ASSERT(read_buffer != (uint8_t *)0);
+    
+    this_i2c->master_status = I2C_FAILED;
+    
+    if((read_size > 0u) && (offset_size > 0u))
+    {
+        psr_t saved_psr;
+        volatile uint8_t stat_ctrl;
+
+
+   	saved_psr=HAL_disable_interrupts();
+
+        /* Update the transaction only when there is no transaction going on I2C */
+        if( this_i2c->transaction == NO_TRANSACTION)
+        {
+            this_i2c->transaction = MASTER_RANDOM_READ_TRANSACTION;
+        }
+
+        /* Update the Pending transaction information so that transaction can restarted */
+        this_i2c->pending_transaction = MASTER_RANDOM_READ_TRANSACTION ;
+
+        /* Update target address */
+        this_i2c->target_addr = (uint_fast8_t)serial_addr << 1u;
+
+        this_i2c->dir = WRITE_DIR;
+
+        this_i2c->master_tx_buffer = addr_offset;
+        this_i2c->master_tx_size = offset_size;
+        this_i2c->master_tx_idx = 0u;
+
+        this_i2c->master_rx_buffer = read_buffer;
+        this_i2c->master_rx_size = read_size;
+        this_i2c->master_rx_idx = 0u;
+        
+        /* Set I2C status in progress */
+        this_i2c->master_status = I2C_IN_PROGRESS;
+        this_i2c->options = options;
+        
+        if(I2C_IN_PROGRESS == this_i2c->slave_status)
+        {
+            this_i2c->is_transaction_pending = 1u;
+        }
+        else
+        {
+            HAL_set_8bit_reg_field(this_i2c->base_address, STA, 0x01u);
+        }
+
+        /*
+         * Clear interrupts if required (depends on repeated starts).
+         * Since the Bus is on hold, only then prior status needs to
+         * be cleared.
+         */
+        if ( I2C_HOLD_BUS == this_i2c->bus_status )
+        {
+            HAL_set_8bit_reg_field(this_i2c->base_address, SI, 0x00u);
+        }
+
+        stat_ctrl = HAL_get_8bit_reg( this_i2c->base_address, STATUS);
+        stat_ctrl = stat_ctrl;  /* Avoids lint warning. */
+            
+        /* Enable the interrupt. ( Re-enable) */
+        I2C_enable_irq( this_i2c );
+
+
+   	HAL_restore_interrupts( saved_psr );
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_get_status()
+ * See "core_i2c.h" for details of how to use this function.
+ */
+i2c_status_t I2C_get_status
+(
+    i2c_instance_t * this_i2c
+)
+{
+    i2c_status_t i2c_status ;
+
+    i2c_status = this_i2c->master_status ;
+
+    return i2c_status;
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_wait_complete()
+ * See "core_i2c.h" for details of how to use this function.
+ */
+i2c_status_t I2C_wait_complete
+(
+    i2c_instance_t * this_i2c,
+    uint32_t timeout_ms
+)
+{
+    i2c_status_t i2c_status;
+    psr_t saved_psr;
+    /*
+     * Because we have no idea of what CPU we are supposed to be running on
+     * we need to guard this write to the timeout value to avoid ISR/user code
+     * interaction issues. Checking the status below should be fine as only a
+     * single byte should change in that.
+     */
+
+   	saved_psr=HAL_disable_interrupts();
+    this_i2c->master_timeout_ms = timeout_ms;
+
+   	HAL_restore_interrupts( saved_psr );
+
+    /* Run the loop until state returns I2C_FAILED  or I2C_SUCESS*/
+    do {
+        i2c_status = this_i2c->master_status;
+    } while(I2C_IN_PROGRESS == i2c_status);
+    return i2c_status;
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_system_tick()
+ * See "core_i2c.h" for details of how to use this function.
+ */
+void I2C_system_tick
+(
+    i2c_instance_t * this_i2c,
+    uint32_t ms_since_last_tick
+)
+{
+    if(this_i2c->master_timeout_ms != I2C_NO_TIMEOUT)
+    {
+       if(this_i2c->master_timeout_ms > ms_since_last_tick)
+        {
+            this_i2c->master_timeout_ms -= ms_since_last_tick;
+        }
+        else
+        {
+            psr_t saved_psr;
+            /*
+             * We need to disable interrupts here to ensure we can update the
+             * shared data without the I2C ISR interrupting us.
+             */
+
+   	saved_psr=HAL_disable_interrupts();
+
+            /*
+             * Mark current transaction as having timed out.
+             */
+            this_i2c->master_status = I2C_TIMED_OUT;
+            this_i2c->transaction = NO_TRANSACTION;
+            this_i2c->is_transaction_pending = 0;
+
+
+   	HAL_restore_interrupts( saved_psr );
+            
+            /*
+             * Make sure we do not incorrectly signal a timeout for subsequent
+             * transactions.
+             */
+            this_i2c->master_timeout_ms = I2C_NO_TIMEOUT;
+        }
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_set_slave_tx_buffer()
+ * See "core_i2c.h" for details of how to use this function.
+ */
+void I2C_set_slave_tx_buffer
+(
+    i2c_instance_t * this_i2c,
+    const uint8_t * tx_buffer,
+    uint16_t tx_size
+)
+{
+    psr_t saved_psr;
+
+    /*
+     * We need to disable interrupts here to ensure we can update the
+     * shared data without the I2C ISR interrupting us.
+     */
+
+   	saved_psr=HAL_disable_interrupts();
+    
+    this_i2c->slave_tx_buffer = tx_buffer;
+    this_i2c->slave_tx_size = tx_size;
+    this_i2c->slave_tx_idx = 0u;
+    
+
+   	HAL_restore_interrupts( saved_psr );
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_set_slave_rx_buffer()
+ * See "core_i2c.h" for details of how to use this function.
+ */
+void I2C_set_slave_rx_buffer
+(
+    i2c_instance_t * this_i2c,
+    uint8_t * rx_buffer,
+    uint16_t rx_size
+)
+{
+    psr_t saved_psr;
+
+    /*
+     * We need to disable interrupts here to ensure we can update the
+     * shared data without the I2C ISR interrupting us.
+     */
+
+   	saved_psr=HAL_disable_interrupts();
+
+    this_i2c->slave_rx_buffer = rx_buffer;
+    this_i2c->slave_rx_size = rx_size;
+    this_i2c->slave_rx_idx = 0u;
+
+
+   	HAL_restore_interrupts( saved_psr );
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_set_slave_mem_offset_length()
+ * See "core_i2c.h" for details of how to use this function.
+ */
+void I2C_set_slave_mem_offset_length
+(
+    i2c_instance_t * this_i2c,
+    uint8_t offset_length
+)
+{
+    HAL_ASSERT(offset_length <= MAX_OFFSET_LENGTH);
+    
+    /*
+     * Single byte update, should be interrupt safe
+     */
+    if(offset_length > MAX_OFFSET_LENGTH)
+    {
+        this_i2c->slave_mem_offset_length = MAX_OFFSET_LENGTH;
+    }
+    else
+    {
+        this_i2c->slave_mem_offset_length = offset_length;
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_register_write_handler()
+ * See "core_i2c.h" for details of how to use this function.
+ */
+void I2C_register_write_handler
+(
+    i2c_instance_t * this_i2c,
+    i2c_slave_wr_handler_t handler
+)
+{
+    psr_t saved_psr;
+
+    /*
+     * We need to disable interrupts here to ensure we can update the
+     * shared data without the I2C ISR interrupting us.
+     */
+
+   	saved_psr=HAL_disable_interrupts();
+
+    this_i2c->slave_write_handler = handler;
+
+
+   	HAL_restore_interrupts( saved_psr );
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_enable_slave()
+ * See "core_i2c.h" for details of how to use this function.
+ */
+void I2C_enable_slave
+(
+    i2c_instance_t * this_i2c
+)
+{
+    psr_t saved_psr;
+
+    /*
+     * We need to disable interrupts here to ensure we can update the
+     * hardware register and slave mode flag without the I2C ISR interrupting
+     * us.
+     */
+
+   	saved_psr=HAL_disable_interrupts();
+
+    /* Set the Assert Acknowledge bit. */
+    HAL_set_8bit_reg_field(this_i2c->base_address, AA, 0x01u);
+
+    /* Enable slave mode */
+    this_i2c->is_slave_enabled = 1u;
+
+
+   	HAL_restore_interrupts( saved_psr );
+
+    /* Enable I2C IRQ*/
+    I2C_enable_irq( this_i2c );
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_disable_slave()
+ * See "core_i2c.h" for details of how to use this function.
+ */
+void I2C_disable_slave
+(
+    i2c_instance_t * this_i2c
+)
+{
+    psr_t saved_psr;
+
+    /*
+     * We need to disable interrupts here to ensure we can update the
+     * hardware register without the I2C ISR interrupting us.
+     */
+
+   	saved_psr=HAL_disable_interrupts();
+    
+    /* Reset the assert acknowledge bit. */
+    HAL_set_8bit_reg_field(this_i2c->base_address, AA, 0x00u);
+
+    /* Disable slave mode with IRQ blocked to make whole change atomic */
+    this_i2c->is_slave_enabled = 0u;
+
+
+   	HAL_restore_interrupts( saved_psr );
+}
+
+/*------------------------------------------------------------------------------
+ * 
+ */
+static void enable_slave_if_required
+(
+    i2c_instance_t * this_i2c
+)
+{
+    /*
+     * This function is only called from within the ISR and so does not need
+     * guarding on the register access.
+     */
+    if( 0 != this_i2c->is_slave_enabled )
+    {
+        HAL_set_8bit_reg_field( this_i2c->base_address, AA, 0x01u );
+    }
+}
+/*------------------------------------------------------------------------------
+ * I2C_set_slave_second_addr()
+ * See "i2c.h" for details of how to use this function.
+ */
+void I2C_set_slave_second_addr
+(
+    i2c_instance_t * this_i2c,
+    uint8_t second_slave_addr
+)
+{
+    uint8_t second_slave_address;
+    
+    /*
+      This function does not support CoreI2C hardware configured with a fixed 
+      second slave address.  The current implementation of the ADDR1[0] register
+      bit makes it difficult for the driver to support both programmable and
+      fixed second slave address, so we choose to support programmable only.
+      With the programmable configuration, ADDR1[0] and ADDR0[0] both control
+      enable/disable of GCA recognition, as an effective OR of the 2 bit fields.
+      Therefore we set ADDR1[0] to 0 here, so that only ADDR0[0] controls GCA.
+     */
+    second_slave_address = (uint8_t)((second_slave_addr << 1u) & (~SLAVE1_EN_MASK));
+
+    /*
+     * Single byte register write, should be interrupt safe
+     */
+    HAL_set_8bit_reg(this_i2c->base_address, ADDRESS1, second_slave_address);
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_disable_slave_second_addr()
+ * See "i2c.h" for details of how to use this function.
+ */
+void I2C_disable_slave_second_addr
+(
+    i2c_instance_t * this_i2c
+)
+{
+    /*
+      We are disabling the second slave address by setting the value of the 2nd
+      slave address to the primary slave address. The reason for using this method
+      of disabling 2nd slave address is that ADDRESS1[0] has different meaning 
+      depending on hardware configuration. Its use would likely interfere with
+      the intended GCA setting.
+     */
+    /*
+     * Single byte register write, should be interrupt safe
+     */
+    HAL_set_8bit_reg(this_i2c->base_address, ADDRESS1, this_i2c->ser_address);
+}
+
+/*------------------------------------------------------------------------------
+ * i2C_set_gca()
+ * See "i2c.h" for details of how to use this function.
+ */
+
+void I2C_set_gca
+(
+    i2c_instance_t * this_i2c
+)
+{
+    /* 
+     * This read modify write access should be interrupt safe as the address
+     * register is not written to in the ISR.
+     */
+    /* accept GC addressing. */
+    HAL_set_8bit_reg_field(this_i2c->base_address, GC, 0x01u);
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_clear_gca()
+ * See "i2c.h" for details of how to use this function.
+ */
+void I2C_clear_gca
+(
+    i2c_instance_t * this_i2c
+)
+{
+    /* 
+     * This read modify write access should be interrupt safe as the address
+     * register is not written to in the ISR.
+     */
+    /* Clear GC addressing. */
+    HAL_set_8bit_reg_field(this_i2c->base_address, GC, 0x00u);
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_isr()
+ * See "core_i2c.h" for details of how to use this function.
+ */
+void I2C_isr
+(
+    i2c_instance_t * this_i2c
+)
+{
+    volatile uint8_t status;
+    uint8_t data;
+    uint8_t hold_bus;
+    uint8_t clear_irq = 1u;
+
+    status = HAL_get_8bit_reg( this_i2c->base_address, STATUS);
+    
+    switch( status )
+    {
+        /************** MASTER TRANSMITTER / RECEIVER *******************/
+      
+        case ST_START: /* start has been xmt'd */
+        case ST_RESTART: /* repeated start has been xmt'd */
+  	    //write_hex(STDOUT_FILENO, status);
+            HAL_set_8bit_reg_field( this_i2c->base_address, STA, 0x00u);
+            HAL_set_8bit_reg( this_i2c->base_address, DATA, this_i2c->target_addr); /* write call address */
+            HAL_set_8bit_reg_field( this_i2c->base_address, DIR, this_i2c->dir); /* set direction bit */
+            if(this_i2c->dir == WRITE_DIR)
+            {
+                 this_i2c->master_tx_idx = 0u;
+            }
+            else
+            {
+                 this_i2c->master_rx_idx = 0u;
+            }
+
+            /*
+             * Clear the pending transaction. This condition will be true if the slave 
+             * has acquired the bus to carry out pending master transaction which 
+             * it had received during its slave transmission or reception mode. 
+             */
+            if(this_i2c->is_transaction_pending)
+            {
+                this_i2c->is_transaction_pending = 0u;
+            }
+
+            /*
+             * Make sure to update proper transaction after master START
+             * or RESTART
+             */
+            if(this_i2c->transaction != this_i2c->pending_transaction)
+            {
+                this_i2c->transaction = this_i2c->pending_transaction;
+            }
+            break;
+            
+        case ST_LOST_ARB:
+              /* Set start bit.  Let's keep trying!  Don't give up! */
+              HAL_set_8bit_reg_field(this_i2c->base_address, STA, 0x01u);
+              break;
+
+        case ST_STOP_TRANSMIT:
+             /* Stop has been transmitted. Do nothing */
+              break;
+
+        /******************* MASTER TRANSMITTER *************************/
+        case ST_SLAW_NACK:
+  	    //write_hex(STDOUT_FILENO, status);
+            /* SLA+W has been transmitted; not ACK has been received - let's stop. */
+            HAL_set_8bit_reg_field(this_i2c->base_address, STO, 0x01u);
+            this_i2c->master_status = I2C_FAILED;
+            this_i2c->transaction = NO_TRANSACTION;
+            enable_slave_if_required(this_i2c);
+            break;
+            
+        case ST_SLAW_ACK:
+        case ST_TX_DATA_ACK:
+  	    //write_hex(STDOUT_FILENO, status);
+            /* data byte has been xmt'd with ACK, time to send stop bit or repeated start. */
+            if (this_i2c->master_tx_idx < this_i2c->master_tx_size)
+            {    
+                HAL_set_8bit_reg(this_i2c->base_address, DATA, (uint_fast8_t)this_i2c->master_tx_buffer[this_i2c->master_tx_idx++]);
+            }
+            else if ( this_i2c->transaction == MASTER_RANDOM_READ_TRANSACTION )
+            {
+                /* We are finished sending the address offset part of a random read transaction.
+                 * It is is time to send a restart in order to change direction. */
+                 this_i2c->dir = READ_DIR;
+                 HAL_set_8bit_reg_field(this_i2c->base_address, STA, 0x01u);
+            }
+            else /* done sending. let's stop */
+            {
+                /*
+                 * Set the transaction back to NO_TRANSACTION to allow user to do further
+                 * transaction
+                 */
+                this_i2c->transaction = NO_TRANSACTION;
+                hold_bus = this_i2c->options & I2C_HOLD_BUS;
+
+                /* Store the information of current I2C bus status in the bus_status*/
+                this_i2c->bus_status  = hold_bus;
+                if ( hold_bus == 0u )
+                { 
+                    HAL_set_8bit_reg_field(this_i2c->base_address, STO, 0x01u);  /*xmt stop condition */
+                    enable_slave_if_required(this_i2c);
+                }
+                else
+                {
+                    I2C_disable_irq( this_i2c );
+                    clear_irq = 0u;
+                }
+                this_i2c->master_status = I2C_SUCCESS;
+            }
+            break;
+
+          case ST_TX_DATA_NACK:
+  	    //write_hex(STDOUT_FILENO, status);
+            /* data byte SENT, ACK to be received
+             * In fact, this means we've received a NACK (This may not be 
+             * obvious, but if we've rec'd an ACK then we would be in state 
+             * 0x28!) hence, let's send a stop bit
+             */
+            HAL_set_8bit_reg_field(this_i2c->base_address, STO, 0x01u);/* xmt stop condition */
+            this_i2c->master_status = I2C_FAILED;
+
+            /*
+             * Set the transaction back to NO_TRANSACTION to allow user to do further
+             * transaction
+             */
+            this_i2c->transaction = NO_TRANSACTION;
+            enable_slave_if_required(this_i2c);
+            break;
+              
+      /********************* MASTER (or slave?) RECEIVER *************************/
+      
+      /* STATUS codes 08H, 10H, 38H are all covered in MTX mode */
+        case ST_SLAR_ACK: /* SLA+R tx'ed. */
+//  	    //write_hex(STDOUT_FILENO, status);
+            /* Let's make sure we ACK the first data byte received (set AA bit in CTRL) unless
+             * the next byte is the last byte of the read transaction.
+             */
+            if(this_i2c->master_rx_size > 1u)
+            {
+                HAL_set_8bit_reg_field(this_i2c->base_address, AA, 0x01u);
+            }
+            else if(1u == this_i2c->master_rx_size)
+            {
+                HAL_set_8bit_reg_field(this_i2c->base_address, AA, 0x00u);
+            }
+            else /* this_i2c->master_rx_size == 0u */
+            {
+                HAL_set_8bit_reg_field(this_i2c->base_address, AA, 0x01u);
+                HAL_set_8bit_reg_field(this_i2c->base_address, STO, 0x01u);
+                this_i2c->master_status = I2C_SUCCESS;
+                this_i2c->transaction = NO_TRANSACTION;
+            }
+            break;
+            
+        case ST_SLAR_NACK: /* SLA+R tx'ed; let's release the bus (send a stop condition) */
+//  	    //write_hex(STDOUT_FILENO, status);
+            HAL_set_8bit_reg_field(this_i2c->base_address, STO, 0x01u);
+            this_i2c->master_status = I2C_FAILED;
+
+            /*
+             * Set the transaction back to NO_TRANSACTION to allow user to do further
+             * transaction
+             */
+            this_i2c->transaction = NO_TRANSACTION;
+            enable_slave_if_required(this_i2c);
+            break;
+          
+        case ST_RX_DATA_ACK: /* Data byte received, ACK returned */
+//  	    //write_hex(STDOUT_FILENO, status);
+            /* First, get the data */
+            this_i2c->master_rx_buffer[this_i2c->master_rx_idx++] = HAL_get_8bit_reg(this_i2c->base_address, DATA);
+            if( this_i2c->master_rx_idx >= (this_i2c->master_rx_size - 1u))
+            {
+                /* If we're at the second last byte, let's set AA to 0 so
+                 * we return a NACK at the last byte. */
+                HAL_set_8bit_reg_field(this_i2c->base_address, AA, 0x00u);
+            }
+            break;
+            
+        case ST_RX_DATA_NACK: /* Data byte received, NACK returned */
+//  	    //write_hex(STDOUT_FILENO, status);
+            /* Get the data, then send a stop condition */
+            this_i2c->master_rx_buffer[this_i2c->master_rx_idx] = HAL_get_8bit_reg(this_i2c->base_address, DATA);
+          
+            hold_bus = this_i2c->options & I2C_HOLD_BUS; 
+
+            /* Store the information of current I2C bus status in the bus_status*/
+            this_i2c->bus_status  = hold_bus;
+            if ( hold_bus == 0u )
+            { 
+                HAL_set_8bit_reg_field(this_i2c->base_address, STO, 0x01u);  /*xmt stop condition */
+
+                /* Bus is released, now we can start listening to bus, if it is slave */
+                   enable_slave_if_required(this_i2c);
+            }
+            else
+            {
+                I2C_disable_irq( this_i2c );
+                clear_irq = 0u;
+            }
+            /*
+             * Set the transaction back to NO_TRANSACTION to allow user to do further
+             * transaction
+             */
+            this_i2c->transaction = NO_TRANSACTION;
+            this_i2c->master_status = I2C_SUCCESS;
+            break;
+        
+        /******************** SLAVE RECEIVER **************************/
+        case ST_GCA_NACK: /* NACK after, GCA addressing */
+        case ST_SLA_NACK: /* Re-enable AA (assert ack) bit for future transmissions */
+  	    //write_hex(STDOUT_FILENO, status);
+            HAL_set_8bit_reg_field(this_i2c->base_address, AA, 0x01u);
+
+            this_i2c->transaction = NO_TRANSACTION;
+            this_i2c->slave_status = I2C_SUCCESS;
+            
+            /* Check if transaction was pending. If yes, set the START bit */
+            if(this_i2c->is_transaction_pending)
+            {
+                HAL_set_8bit_reg_field(this_i2c->base_address, STA, 0x01u);
+            }
+            break;
+            
+        case ST_GCA_LA: /* Arbitr. lost (GCA rec'd) */
+        case ST_SLV_LA: /* Arbitr. lost (SLA rec'd) */
+  	    //write_hex(STDOUT_FILENO, status);
+            /*
+             *  We lost arbitration and either the GCE or our address was the
+             *  one received so pend the master operation we were starting.
+             */
+            this_i2c->is_transaction_pending = 1u;
+            /* Fall through to normal ST processing as we are now in slave mode */
+
+        case ST_GCA: /* General call address received, ACK returned */
+        case ST_SLAVE_SLAW: /* SLA+W received, ACK returned */
+  	    //write_hex(STDOUT_FILENO, status);
+            this_i2c->transaction = WRITE_SLAVE_TRANSACTION;
+            this_i2c->slave_rx_idx = 0u;
+            this_i2c->random_read_addr = 0u;
+            /*
+             * If Start Bit is set clear it, but store that information since it is because of
+             * pending transaction
+             */
+            if(HAL_get_8bit_reg_field(this_i2c->base_address, STA))
+            {
+                HAL_set_8bit_reg_field(this_i2c->base_address, STA, 0x00u);
+                this_i2c->is_transaction_pending = 1u;
+            }
+            this_i2c->slave_status = I2C_IN_PROGRESS;
+#ifdef INCLUDE_SLA_IN_RX_PAYLOAD
+            /* Fall through to put address as first byte in payload buffer */
+#else
+            /* Only break from this case if the slave address must NOT be included at the
+             * beginning of the received write data. */
+            break;
+#endif            
+        case ST_GCA_ACK: /* DATA received; ACK sent after GCA */
+        case ST_RDATA: /* DATA received; must clear DATA register */
+  	    //write_hex(STDOUT_FILENO, status);
+            if((this_i2c->slave_rx_buffer != (uint8_t *)0)
+               && (this_i2c->slave_rx_idx < this_i2c->slave_rx_size))
+            {
+                data = HAL_get_8bit_reg(this_i2c->base_address, DATA);
+                this_i2c->slave_rx_buffer[this_i2c->slave_rx_idx++] = data;
+                
+#ifdef INCLUDE_SLA_IN_RX_PAYLOAD
+                if((ST_RDATA == status) || (ST_GCA_ACK == status))
+                {
+                    /* Ignore the slave address byte in the random read address
+                       computation in the case where INCLUDE_SLA_IN_RX_PAYLOAD
+                       is defined. */
+#endif
+                    this_i2c->random_read_addr = (this_i2c->random_read_addr << 8) + data;
+#ifdef INCLUDE_SLA_IN_RX_PAYLOAD
+                }
+#endif
+            }
+            
+            if(this_i2c->slave_rx_idx >= this_i2c->slave_rx_size)
+            {
+                /* Rx buffer is full. NACK next received byte. */
+                HAL_set_8bit_reg_field(this_i2c->base_address, AA, 0x00u); 
+            }
+            break;
+            
+        case ST_RSTOP:
+  	    //write_hex(STDOUT_FILENO, status);
+            /* STOP or repeated START occurred. */
+            /* We cannot be sure if the transaction has actually completed as
+             * this hardware state reports that either a STOP or repeated START
+             * condition has occurred. We assume that this is a repeated START
+             * if the transaction was a write from the master to this point.*/
+            if ( this_i2c->transaction == WRITE_SLAVE_TRANSACTION )
+            {
+                if ( this_i2c->slave_rx_idx == this_i2c->slave_mem_offset_length )
+                {
+                    this_i2c->slave_tx_idx = this_i2c->random_read_addr;
+                }
+                /* Call the slave's write transaction handler if it exists. */
+                if ( this_i2c->slave_write_handler != 0u )
+                {
+                    i2c_slave_handler_ret_t h_ret;
+                    h_ret = this_i2c->slave_write_handler( this_i2c, this_i2c->slave_rx_buffer, (uint16_t)this_i2c->slave_rx_idx );
+                    if ( I2C_REENABLE_SLAVE_RX == h_ret )
+                    {
+                        /* There is a small risk that the write handler could
+                         * call I2C_disable_slave() but return
+                         * I2C_REENABLE_SLAVE_RX in error so we only enable
+                         * ACKs if still in slave mode. */
+                         enable_slave_if_required(this_i2c);
+                    }
+                    else
+                    {
+                        HAL_set_8bit_reg_field( this_i2c->base_address, AA, 0x0u );
+                        /* Clear slave mode flag as well otherwise in mixed
+                         * master/slave applications, the AA bit will get set by
+                         * subsequent master operations. */
+                        this_i2c->is_slave_enabled = 0u;
+                    }
+                }
+                else
+                {
+                    /* Re-enable address acknowledge in case we were ready to nack the next received byte. */
+                    HAL_set_8bit_reg_field( this_i2c->base_address, AA, 0x01u );
+                }
+            }
+            else /* A stop or repeated start outside a write/read operation */
+            {
+                /*
+                 * Reset slave_tx_idx so that a subsequent read will result in the slave's
+                 * transmit buffer being sent from the first byte.
+                 */
+                this_i2c->slave_tx_idx = 0u;
+                /*
+                 * See if we need to re-enable acknowledgement as some error conditions, such
+                 * as a master prematurely ending a transfer, can see us get here with AA set
+                 * to 0 which will disable slave operation if we are not careful.
+                 */
+                enable_slave_if_required(this_i2c);
+            }
+
+            /* Mark any previous master write transaction as complete. */
+            this_i2c->slave_status = I2C_SUCCESS;
+            
+            /* Check if transaction was pending. If yes, set the START bit */
+            if(this_i2c->is_transaction_pending)
+            {
+                HAL_set_8bit_reg_field(this_i2c->base_address, STA, 0x01u);
+            }
+
+            /*
+             * Set the transaction back to NO_TRANSACTION to allow user to do further
+             * transaction
+             */
+            this_i2c->transaction = NO_TRANSACTION;
+
+            break;
+            
+        case ST_SLV_RST: /* SMBUS ONLY: timeout state. must clear interrupt */
+  	    //write_hex(STDOUT_FILENO, status);
+            /*
+             * Set the transaction back to NO_TRANSACTION to allow user to do further
+             * transaction.
+             */
+            this_i2c->transaction = NO_TRANSACTION;
+            /*
+             * Reset slave_tx_idx so that a subsequent read will result in the slave's
+             * transmit buffer being sent from the first byte.
+             */
+            this_i2c->slave_tx_idx = 0u;
+            /*
+             * Clear status to I2C_FAILED only if there was an operation in progress.
+             */
+            if(I2C_IN_PROGRESS == this_i2c->slave_status)
+            {
+                this_i2c->slave_status = I2C_FAILED;
+            }
+
+            enable_slave_if_required(this_i2c); /* Make sure AA is set correctly */
+
+            break;
+            
+        /****************** SLAVE TRANSMITTER **************************/
+        case ST_SLAVE_SLAR_ACK: /* SLA+R received, ACK returned */
+        case ST_SLARW_LA:       /* Arbitration lost, and: */
+        case ST_RACK:           /* Data tx'ed, ACK received */
+  	    //write_hex(STDOUT_FILENO, status);
+            if ( status == ST_SLAVE_SLAR_ACK )
+            {
+                this_i2c->transaction = READ_SLAVE_TRANSACTION;
+                this_i2c->random_read_addr = 0u;
+                this_i2c->slave_status = I2C_IN_PROGRESS;
+                /* If Start Bit is set clear it, but store that information since it is because of
+                 * pending transaction
+                 */
+                if(HAL_get_8bit_reg_field(this_i2c->base_address, STA))
+                {
+                    HAL_set_8bit_reg_field(this_i2c->base_address, STA, 0x00u);
+                    this_i2c->is_transaction_pending = 1u;
+                 }
+            }
+            if (this_i2c->slave_tx_idx >= this_i2c->slave_tx_size)
+            {
+                /* Ensure 0xFF is returned to the master when the slave specifies
+                 * an empty transmit buffer. */
+                HAL_set_8bit_reg(this_i2c->base_address, DATA, 0xFFu);
+            }
+            else
+            {
+                /* Load the data the data byte to be sent to the master. */
+                HAL_set_8bit_reg(this_i2c->base_address, DATA, (uint_fast8_t)this_i2c->slave_tx_buffer[this_i2c->slave_tx_idx++]);
+            }
+            /* Determine if this is the last data byte to send to the master. */
+            if (this_i2c->slave_tx_idx >= this_i2c->slave_tx_size) /* last byte? */
+            {
+                 HAL_set_8bit_reg_field(this_i2c->base_address, AA, 0x00u); 
+                /* Next read transaction will result in slave's transmit buffer
+                 * being sent from the first byte. */
+                this_i2c->slave_tx_idx = 0u;
+            }
+            break;
+        
+        case ST_SLAVE_RNACK:    /* Data byte has been transmitted; not-ACK has been received. */
+        case ST_FINAL: /* Last Data byte tx'ed, ACK received */
+  	    //write_hex(STDOUT_FILENO, status);
+            /* We assume that the transaction will be stopped by the master.
+             * Reset slave_tx_idx so that a subsequent read will result in the slave's
+             * transmit buffer being sent from the first byte. */
+            this_i2c->slave_tx_idx = 0u;
+            HAL_set_8bit_reg_field(this_i2c->base_address, AA, 0x01u); 
+
+            /*  Mark previous state as complete */
+            this_i2c->slave_status = I2C_SUCCESS;
+            /* Check if transaction was pending. If yes, set the START bit */
+            if(this_i2c->is_transaction_pending)
+            {
+                HAL_set_8bit_reg_field(this_i2c->base_address, STA, 0x01u);
+            }
+            /*
+             * Set the transaction back to NO_TRANSACTION to allow user to do further
+             * transaction
+             */
+            this_i2c->transaction = NO_TRANSACTION;
+
+            break;
+
+        /* Master Reset has been activated Wait 35 ms for interrupt to be set,
+         * clear interrupt and proceed to 0xF8 state. */
+        case ST_RESET_ACTIVATED:
+        case ST_BUS_ERROR: /* Bus error during MST or selected slave modes */
+        default:
+  	    //write_hex(STDOUT_FILENO, status);
+            /* Some undefined state has encountered. Clear Start bit to make
+             * sure, next good transaction happen */
+            HAL_set_8bit_reg_field(this_i2c->base_address, STA, 0x00u);
+            /*
+             * Set the transaction back to NO_TRANSACTION to allow user to do further
+             * transaction.
+             */
+            this_i2c->transaction = NO_TRANSACTION;
+            /*
+             * Reset slave_tx_idx so that a subsequent read will result in the slave's
+             * transmit buffer being sent from the first byte.
+             */
+            this_i2c->slave_tx_idx = 0u;
+            /*
+             * Clear statuses to I2C_FAILED only if there was an operation in progress.
+             */
+            if(I2C_IN_PROGRESS == this_i2c->master_status)
+            {
+                this_i2c->master_status = I2C_FAILED;
+            }
+
+            if(I2C_IN_PROGRESS == this_i2c->slave_status)
+            {
+                this_i2c->slave_status = I2C_FAILED;
+            }
+
+            break;
+    }
+    
+    if ( clear_irq )
+    {
+        /* clear interrupt. */
+        HAL_set_8bit_reg_field(this_i2c->base_address, SI, 0x00u);
+    }
+    
+    /* Read the status register to ensure the last I2C registers write took place
+     * in a system built around a bus making use of posted writes. */
+//    status = HAL_get_8bit_reg( this_i2c->base_address, STATUS);
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_smbus_init()
+ * See "i2c.h" for details of how to use this function.
+ */
+ 
+/*
+ * SMBSUS_NO    = 1
+ * SMBALERT_NO  = 1
+ * SMBus enable = 1
+ */
+#define INIT_AND_ENABLE_SMBUS   0x54u
+void I2C_smbus_init
+(
+    i2c_instance_t * this_i2c
+)
+{
+    /*
+     * Single byte register write, should be interrupt safe
+     */
+    /* Enable SMBUS */
+    HAL_set_8bit_reg(this_i2c->base_address, SMBUS, INIT_AND_ENABLE_SMBUS);
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_enable_smbus_irq()
+ * See "i2c.h" for details of how to use this function.
+ */
+void I2C_enable_smbus_irq
+(
+    i2c_instance_t * this_i2c,
+    uint8_t  irq_type
+)
+{
+    psr_t saved_psr;
+
+    /*
+     * We need to disable interrupts here to ensure we can update the
+     * hardware register without the SMBUS IRQs interrupting us.
+     */
+
+   	saved_psr=HAL_disable_interrupts();
+
+    if ( irq_type & I2C_SMBALERT_IRQ)
+    {
+        HAL_set_8bit_reg_field(this_i2c->base_address, SMBALERT_IE, 0x01u);
+    }
+    if ( irq_type & I2C_SMBSUS_IRQ)
+    {
+        HAL_set_8bit_reg_field(this_i2c->base_address, SMBSUS_IE, 0x01u);
+    }
+    
+
+   	HAL_restore_interrupts( saved_psr );
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_disable_smbus_irq()
+ * See "i2c.h" for details of how to use this function.
+ */
+void I2C_disable_smbus_irq
+(
+    i2c_instance_t * this_i2c,
+    uint8_t  irq_type
+)
+{
+    psr_t saved_psr;
+
+    /*
+     * We need to disable interrupts here to ensure we can update the
+     * hardware register without the SMBUS IRQs interrupting us.
+     */
+
+   	saved_psr=HAL_disable_interrupts();
+
+    if ( irq_type & I2C_SMBALERT_IRQ)
+    {
+        HAL_set_8bit_reg_field(this_i2c->base_address, SMBALERT_IE, 0x00u);
+    }
+    if (irq_type & I2C_SMBSUS_IRQ )
+    {
+        HAL_set_8bit_reg_field(this_i2c->base_address, SMBSUS_IE, 0x00u);
+    }
+    
+
+   	HAL_restore_interrupts( saved_psr );
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_suspend_smbus_slave()
+ * See "i2c.h" for details of how to use this function.
+ */
+void I2C_suspend_smbus_slave
+(
+    i2c_instance_t * this_i2c
+)
+{
+    psr_t saved_psr;
+
+    /*
+     * We need to disable interrupts here to ensure we can update the
+     * hardware register without the SMBUS IRQs interrupting us.
+     */
+
+   	saved_psr=HAL_disable_interrupts();
+
+    HAL_set_8bit_reg_field(this_i2c->base_address, SMBSUS_NO_CONTROL, 0x00u);
+
+
+   	HAL_restore_interrupts( saved_psr );
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_resume_smbus_slave()
+ * See "i2c.h" for details of how to use this function.
+ */
+void I2C_resume_smbus_slave
+(
+    i2c_instance_t * this_i2c
+)
+{
+    psr_t saved_psr;
+
+    /*
+     * We need to disable interrupts here to ensure we can update the
+     * hardware register without the SMBUS IRQs interrupting us.
+     */
+
+   	saved_psr=HAL_disable_interrupts();
+
+    HAL_set_8bit_reg_field(this_i2c->base_address, SMBSUS_NO_CONTROL, 0x01u);
+
+
+   	HAL_restore_interrupts( saved_psr );
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_reset_smbus()
+ * See "i2c.h" for details of how to use this function.
+ */
+void I2C_reset_smbus
+(
+    i2c_instance_t * this_i2c
+)
+{
+    psr_t saved_psr;
+
+    /*
+     * We need to disable interrupts here to ensure we can update the
+     * hardware register without the SMBUS IRQs interrupting us.
+     */
+
+   	saved_psr=HAL_disable_interrupts();
+    HAL_set_8bit_reg_field(this_i2c->base_address, SMBUS_MST_RESET, 0x01u);
+    
+
+   	HAL_restore_interrupts( saved_psr );
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_set_smbus_alert()
+ * See "i2c.h" for details of how to use this function.
+ */
+void I2C_set_smbus_alert
+(
+    i2c_instance_t * this_i2c
+)
+{
+    psr_t saved_psr;
+
+    /*
+     * We need to disable interrupts here to ensure we can update the
+     * hardware register without the SMBUS IRQs interrupting us.
+     */
+
+   	saved_psr=HAL_disable_interrupts();
+    HAL_set_8bit_reg_field(this_i2c->base_address, SMBALERT_NO_CONTROL, 0x00u);
+
+
+   	HAL_restore_interrupts( saved_psr );
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_clear_smbus_alert()
+ * See "i2c.h" for details of how to use this function.
+ */
+void I2C_clear_smbus_alert
+(
+    i2c_instance_t * this_i2c
+)
+{
+    psr_t saved_psr;
+
+    /*
+     * We need to disable interrupts here to ensure we can update the
+     * hardware register without the SMBUS IRQs interrupting us.
+     */
+
+   	saved_psr=HAL_disable_interrupts();
+
+    HAL_set_8bit_reg_field(this_i2c->base_address, SMBALERT_NO_CONTROL, 0x01u);
+
+
+   	HAL_restore_interrupts( saved_psr );
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_get_irq_status()
+ * See "i2c.h" for details of how to use this function.
+ */
+uint8_t I2C_get_irq_status
+(
+    i2c_instance_t * this_i2c
+)
+{
+    uint8_t status ;
+    uint8_t irq_type = I2C_NO_IRQ ;
+
+    status = HAL_get_8bit_reg(this_i2c->base_address, SMBUS);
+
+    if( status & (uint8_t)SMBALERT_NI_STATUS_MASK )
+    {
+        irq_type |= I2C_SMBALERT_IRQ ;
+    }
+
+    if( status & (uint8_t)SMBSUS_NI_STATUS_MASK )
+    {
+        irq_type |= I2C_SMBSUS_IRQ ;
+    }
+
+    status = HAL_get_8bit_reg(this_i2c->base_address, CONTROL);
+
+    if( status & (uint8_t)SI_MASK )
+    {
+        irq_type |= I2C_INTR_IRQ ;
+    }
+    return(irq_type);
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_set_slave_addr2()
+ * See "i2c.h" for details of how to use this function.
+ */
+void I2C_set_user_data
+(
+    i2c_instance_t * this_i2c,
+    void * p_user_data
+)
+{
+    this_i2c->p_user_data = p_user_data ;
+}
+
+/*------------------------------------------------------------------------------
+ * I2C_get_user_data()
+ * See "i2c.h" for details of how to use this function.
+ */
+void * I2C_get_user_data
+(
+    i2c_instance_t * this_i2c
+)
+{
+    return( this_i2c->p_user_data);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreI2C/core_i2c.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreI2C/core_i2c.h
new file mode 100644
index 0000000..2b1d5ac
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreI2C/core_i2c.h
@@ -0,0 +1,2280 @@
+/*******************************************************************************
+ * (c) Copyright 2009-2015 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * CoreI2C software driver Application Programming Interface.
+ * This file contains defines and function declarations allowing to interface
+ * with the CoreI2C software driver.
+ * 
+ * SVN $Revision: 7984 $
+ * SVN $Date: 2015-10-12 12:07:40 +0530 (Mon, 12 Oct 2015) $
+ */
+/*=========================================================================*//**
+  @mainpage CoreI2C Bare Metal Driver.
+   The CoreI2C bare metal software driver supports I2C master and slave
+   operations.
+
+  @section intro_sec Introduction
+  The CoreI2C driver provides a set of functions for controlling the Microsemi
+  CoreI2C hardware IP. The driver supports up to 16 separate I2C channels per
+  CoreI2C instance, with common slave address settings shared between channels
+  on a device.
+  
+  Optional features of the CoreI2C allow it operate with I2C based protocols
+  such as System Management Bus (SMBus), Power Management Bus (PMBus) and
+  Intelligent Platform Management Interface (IPMI). This driver provides support
+  for these features when enabled in the CoreI2C IP.
+  
+  The major features provided by CoreI2C driver are:
+    - Support for configuring the I2C channels of each CoreI2C peripheral.
+    - I2C master operations.
+    - I2C slave operations.
+    - SMBus related operations.
+
+  This driver can be used as part of a bare metal system where no operating 
+  system  is available. The driver can be adapted for use as part of an 
+  operating system, but the implementation of the adaptation layer between the 
+  driver and  the operating system's driver model is outside the scope of this 
+  driver.
+  
+  @section hw_dependencies Hardware Flow Dependencies
+  Your application software should configure the CoreI2C driver through
+  calls to the I2C_init() function for each CoreI2C instance in the
+  hardware design.  The configuration parameters include the CoreI2C hardware
+  instance base address and other runtime parameters, such as the I2C serial
+  clock frequency and I2C device address.
+  
+  Once channel 0 of a CoreI2C peripheral has been initialized via I2C_init(),
+  any additional channels present should be configured by calling
+  I2C_channel_init() for each of the remaining channels.
+  
+  No CoreI2C hardware configuration parameters are used by the driver, apart
+  from the CoreI2C hardware instance base address. Hence, no additional
+  configuration files are required to use the driver. 
+  
+  Interrupt Control
+  The CoreI2C driver has to enable and disable the generation of interrupts by
+  CoreI2C at various times when it is operating. This enabling and disabling of
+  interrupts must be done through the system’s interrupt controller. For that
+  reason, the method of controlling the CoreI2C interrupt is system specific
+  and it is necessary to customize the I2C_enable_irq() and I2C_disable_irq()
+  functions. These functions are found in the file i2c_interrupt.c. Their
+  default implementation fires an assertion to attract attention to the fact
+  that these functions must be modified.
+  
+  The implementation of the I2C_enable_irq() function should permit interrupts
+  generated by a CoreI2C instance to interrupt the processor. The implementation
+  of the I2C_disable_irq() function should prevent interrupts generated by a
+  CoreI2C instance from interrupting the processor. Please refer to the provided
+  example projects for a working implementation of these functions.
+  
+  The function I2C_register_write_handler() is used to register a write handler
+  function with the CoreI2C driver that it calls on completion of an I2C write
+  transaction by the CoreI2C slave. It is your responsibility to create and
+  register the implementation of this handler function that processes or
+  trigger the processing of the received data.
+  
+  The SMBSUS and SMBALERT interrupts are related to the SMBus interface and are
+  enabled and disabled through I2C_enable_smbus_irq() and 
+  I2C_disable_smbus_irq() respectively. It is your responsibility to create
+  interrupt handler functions in your application to get the desired response
+  for the SMBus interrupts.
+
+  Note: You must include the path to any application header files that are
+        included in the i2c_interrupt.c file, as an include path in your
+        project’s compiler settings. The details of how to do this will depend
+        on your development software.
+
+  SMBus Logic options
+  SMBus related APIs will not have any effect if in CoreI2C hardware
+  configuration "Generate SMBus Logic" is not enabled. The APIs which will not
+  give desired results in case SMBus Logic is disabled are:
+  
+      I2C_smbus_init()
+      I2C_reset_smbus()
+      I2C_enable_smbus_irq()
+      I2C_disable_smbus_irq()
+      I2C_suspend_smbus_slave()
+      I2C_resume_smbus_slave()
+      I2C_set_smsbus_alert()
+      I2C_clear_smsbus_alert()
+      I2C_get_irq_status() 
+
+  Fixed Baud Rate Values
+  The serial clock frequency parameter passed to the I2C_init() and 
+  I2C_channel_init() functions may not have any effect if fixed values were
+  selected for Baud rate in the hardware configuration of CoreI2C. When fixed
+  values are selected for these baud rates, the driver cannot overwrite
+  the fixed values.
+
+  Fixed Slave Address Options Values
+  The primary slave address  parameter passed to the I2C_init() function, and
+  secondary address value passed to the I2C_set_slave_second_addr() function,
+  may not have the desired effect if fixed values were selected for the slave 0
+  address and slave 1 address respectively. Proper operation of this version of
+  the driver requires the slave addresses to be programmable.
+
+  @section theory_op Theory of Operation
+  The CoreI2C software driver is designed to allow the control of multiple
+  instances of CoreI2C with one or more I2C channels. Each channel in an
+  instance of CoreI2C in the hardware design is associated with a single 
+  instance of the i2c_instance_t structure in the software. You must allocate
+  memory for one unique i2c_instance_t structure instance for each channel of
+  each CoreI2C hardware instance. The contents of these data structures are
+  initialised during calls to I2C_init() and if necessary I2C_channel_init().
+  A pointer to the structure is passed to subsequent driver functions in order
+  to identify the CoreI2C hardware instance and channel you wish to perform the
+  requested operation.
+
+  Note: Do not attempt to directly manipulate the contents of i2c_instance_t
+       structures. These structures are only intended to be modified by the driver
+       functions.
+
+  The CoreI2C driver functions are grouped into the following categories:
+    - Initialization and configuration functions
+    - Interrupt control
+    - I2C slave addressing functions
+    - I2C master operations functions to handle write, read and write-read 
+      transactions
+    - I2C slave operations functions to handle write, read and write-read 
+      transactions
+    - Mixed master-slave operations 
+    - SMBus interface configuration and control.
+    
+  Initialization and Configuration
+    The CoreI2C device is first initialized through a call to the I2C_init()
+    function. Since each CoreI2C peripheral supports up to 16 channels, an
+    additional function, I2C_channel_init(), is required to initialize the
+    remaining channels with their own data structures.
+
+    I2C_init() initializes channel 0 of a CoreI2C and the i2c_instance_t for
+    channel 0 acts as the basis for further channel initialization as the
+    hardware base address and I2C serial address are same across all the
+    channels. I2C_init() must be called before any other  I2C driver function
+    calls. The I2C_init() call for each CoreI2C takes the I2C serial address
+    assigned to the I2C and the serial clock divider to be used to generate its
+    I2C clock as configuration parameters. 
+    
+    I2C_channel_init() takes as input parameters a pointer to the CoreI2C 
+    i2c_instance_t which has been initialized via I2C_init() and a pointer to a
+    separate i2c_instance_t which represents this new channel. Another input
+    parameter which is required by this function is serial clock divider which
+    generates its I2C clock. 
+    
+  Interrupt Control
+    The CoreI2C driver is interrupt driven and it uses each channels INT
+    interrupt to drive the state machine which is at the heart of the driver.
+    The application is responsible for providing the link between the interrupt
+    generating hardware and the CoreI2C interrupt handler and must ensure that
+    the I2C_isr() function is called with the correct i2c_instance_t structure
+    pointer for the CoreI2C channel initiating the interrupt.
+    
+    The driver enables and disables the generation of INT interrupts by CoreI2C
+    at various times when it is operating through the user supplied
+    I2C_enable_irq() and I2C_disable_irq() functions. 
+    
+    The function I2C_register_write_handler() is used to register a write
+    handler function with the CoreI2C driver which is called on completion
+    of an I2C write transaction by the CoreI2C slave. It is the user
+    applications responsibility to create and register the implementation of
+    this handler function that processes or triggers the processing of the
+    received data. 
+    
+    The other two interrupt sources in the CoreI2C, are related to SMBus
+    operation and are enabled and disabled through I2C_enable_smbus_irq() and
+    I2C_disable_smbus_irq() respectively. Due to the application specific
+    nature of the response to SMBus interrupts, you must design interrupt
+    handler functions in the application to get the desired behaviour for
+    SMBus related interrupts.
+    
+    If enabled, the SMBA_INT signal from the CoreI2C is asserted if an
+    SMBALERT condition is signalled on the SMBALERT_NI input for the channel.
+    
+    If enabled, the SMBS_INT signal from the CoreI2C is asserted if an
+    SMBSUSPEND condition is signalled on the SMBSUS_NI input for the channel.
+
+  I2C slave addressing functions
+    A CoreI2C peripheral can respond to three slave addresses:
+    - Slave address 0 - This is the primary slave address which is used for
+                        accessing a CoreI2C channel when it acts as a slave in
+                        I2C transactions. You must configure the primary slave
+                        address via I2C_init().
+                        
+    - Slave address 1 - This is the secondary slave address which might be
+                        required in certain application specific scenarios.
+                        The secondary slave address can be configured via
+                        I2C_set_slave_second_addr() and disabled via 
+                        I2C_disable_slave_second_addr().
+                        
+    - General call address - A CoreI2C slave can be configured to respond to
+                        a broadcast command by a master transmitting the
+                        general call address of 0x00. Use the I2C_set_gca()
+                        function to enable the slave to respond to the general
+                        call address. If the CoreI2C slave is not required to
+                        respond to the general call address, disable this
+                        address by calling I2C_clear_gca().
+
+    Note: All channels on a CoreI2C instance share the same slave address logic.
+          This means that they cannot have separate slave addresses and rely on
+          the separate physical I2C bus connections to distinguish them.
+          
+  Transaction Types
+    The I2C driver is designed to handle three types of I2C transaction:
+      Write transactions
+      Read transactions
+      Write-read transactions
+ 
+    Write transaction
+      The master I2C device initiates a write transaction by sending a START bit
+      as soon as the bus becomes free. The START bit is followed by the 7-bit
+      serial address of the target slave device followed by the read/write bit
+      indicating the direction of the transaction. The slave acknowledges the
+      receipt of it's address with an acknowledge bit. The master sends data one
+      byte at a time to the slave, which must acknowledge receipt of each byte
+      for the next byte to be sent. The master sends a STOP bit to complete the
+      transaction. The slave can abort the transaction by replying with a 
+      non-acknowledge bit instead of an acknowledge.
+      
+      The application programmer can choose not to send a STOP bit at the end of
+      the transaction causing the next transaction to begin with a repeated 
+      START bit.
+      
+    Read transaction
+      The master I2C device initiates a read transaction by sending a START bit
+      as soon as the bus becomes free. The START bit is followed by the 7-bit
+      serial address of the target slave device followed by the read/write bit
+      indicating the direction of the transaction. The slave acknowledges
+      receipt of it's slave address with an acknowledge bit. The slave sends
+      data one byte at a time to the master, which must acknowledge receipt of
+      each byte for the next byte to be sent. The master sends a non-acknowledge
+      bit following the last byte it wishes to read followed by a STOP bit.
+      
+      The application programmer can choose not to send a STOP bit at the end of
+      the transaction causing the next transaction to begin with a repeated 
+      START bit.
+ 
+    Write-read transaction
+      The write-read transaction is a combination of a write transaction
+      immediately followed by a read transaction. There is no STOP bit between
+      the write and read phases of a write-read transaction. A repeated START
+      bit is sent between the write and read phases.
+      
+      Whilst the write handler is being executed, the slave holds the clock line
+      low to stretch the clock until the response is ready.
+      
+      The write-read transaction is typically used to send a command or offset
+      in the write transaction specifying the logical data to be transferred
+      during the read phase.
+      
+      The application programmer can choose not to send a STOP bit at the end of
+      the transaction causing the next transaction to begin with a repeated
+      START bit.
+
+  Master Operations
+    The application can use the I2C_write(), I2C_read() and I2C_write_read()
+    functions to initiate an I2C bus transaction. The application can then wait
+    for the transaction to complete using the I2C_wait_complete() function
+    or poll the status of the I2C transaction using the I2C_get_status()
+    function until it returns a value different from I2C_IN_PROGRESS. The
+    I2C_system_tick() function can be used to set a time base for the
+    I2C_wait_complete() function’s time out delay.
+
+  Slave Operations
+    The configuration of the  I2C driver to operate as an I2C slave requires
+    the use of the following functions:
+       I2C_set_slave_tx_buffer()
+       I2C_set_slave_rx_buffer()
+       I2C_set_slave_mem_offset_length()
+       I2C_register_write_handler()
+       I2C_enable_slave()
+       
+    Use of all functions is not required if the slave I2C does not need to support
+    all types of I2C read transactions. The subsequent sections list the functions
+    that must be used to support each transaction type. 
+    
+    Responding to read transactions
+      The following functions are used to configure the  CoreI2C driver to
+      respond to I2C read transactions:
+        I2C_set_slave_tx_buffer()
+        I2C_enable_slave()
+        
+      The function I2C_set_slave_tx_buffer() specifies the data buffer that
+      will be transmitted when the I2C slave is the target of an I2C read
+      transaction. It is then up to the application to manage the content of
+      that buffer to control the data that will be transmitted to the I2C
+      master as a result of the read transaction.
+      
+      The function I2C_enable_slave() enables the  I2C hardware instance
+      to respond to I2C transactions. It must be called after the  I2C driver
+      has been configured to respond to the required transaction types.
+
+    Responding to write transactions
+      The following functions are used to configure the  I2C driver to respond
+      to I2C write transactions:
+        I2C_set_slave_rx_buffer()
+        I2C_register_write_handler()
+        I2C_enable_slave()
+        
+      The function I2C_set_slave_rx_buffer() specifies the data buffer that
+      will be used to store the data received by the I2C slave when it is the
+      target an I2C  write transaction.
+      
+      The function I2C_register_write_handler() specifies the handler function
+      that must be called on completion of the I2C write transaction. It is this
+      handler function that processes or triggers the processing of the received
+      data.
+      
+      The function I2C_enable_slave() enables the  I2C hardware instance
+      to respond to I2C transactions. It must be called after the  I2C driver
+      has been configured to respond to the required transaction types.
+
+    Responding to write-read transactions
+      The following functions are used to configure the CoreI2C driver to 
+      respond to write-read transactions:
+        I2C_set_slave_mem_offset_length()
+        I2C_set_slave_tx_buffer()
+        I2C_set_slave_rx_buffer()
+        I2C_register_write_handler()
+        I2C_enable_slave()
+        
+      The function I2C_set_slave_mem_offset_length() specifies the number of
+      bytes expected by the I2C slave during the write phase of the write-read
+      transaction.
+      
+      The function I2C_set_slave_tx_buffer() specifies the data that will be
+      transmitted to the I2C master during the read phase of the write-read
+      transaction. The value received by the I2C slave during the write phase of
+      the transaction will be used as an index into the transmit buffer
+      specified by this function to decide which part of the transmit buffer
+      will be transmitted to the I2C master as part of the read phase of the
+      write-read transaction. 
+      
+      The function I2C_set_slave_rx_buffer() specifies the data buffer that
+      will be used to store the data received by the I2C slave during the write
+      phase of the write-read transaction. This buffer must be at least large
+      enough to accommodate the number of bytes specified through the
+      I2C_set_slave_mem_offset_length() function.
+      
+      The function I2C_register_write_handler() can optionally be used to
+      specify a handler function that is called on completion of the write phase
+      of the I2C write-read transaction. If a handler function is registered, it
+      is responsible for processing the received data in the slave receive
+      buffer and populating the slave transmit buffer with the data that will be
+      transmitted to the I2C master as part of the read phase of the write-read
+      transaction.
+      
+      The function I2C_enable_slave() enables the CoreI2C hardware instance to 
+      respond to I2C transactions. It must be called after the CoreI2C driver
+      has been configured to respond to the required transaction types.
+
+  Mixed Master-Slave Operations
+    The CoreI2C device supports mixed master and slave operations. If the 
+    CoreI2C slave has a transaction in progress and your application attempts to
+    begin a master mode transaction, the CoreI2C driver queu3es the master mode
+    transaction until the bus is released and the CoreI2C can switch to master
+    mode and acquire the bus. The CoreI2C master then starts the previously
+    queued master transaction.
+    
+  SMBus Control
+    The CoreI2C driver enables the CoreI2C peripheral’s SMBus functionality
+    using the I2C_smbus_init() function.
+    
+    The I2C_suspend_smbus_slave() function is used, with a master mode CoreI2C,
+    to force slave devices on the SMBus to enter their power-down/suspend mode.
+    The I2C_resume_smbus_slave() function is used to end the suspend operation
+    on the SMBus.
+    
+    The I2C_reset_smbus() function is used, with a master mode CoreI2C, to force
+    all devices on the SMBus to reset their SMBUs interface.
+    
+    The I2C_set_smsbus_alert() function is used, by a slave mode CoreI2C, to
+    force communication with the SMBus master. Once communications with the
+    master is initiated, the I2C_clear_smsbus_alert() function is used to clear
+    the alert condition.
+    
+    The I2C_enable_smbus_irq() and I2C_disable_smbus_irq() functions are used to
+    enable and disable the SMBSUS and SMBALERT SMBus interrupts.
+
+ *//*=========================================================================*/
+
+#ifndef CORE_I2C_H_
+#define CORE_I2C_H_
+
+#include "cpu_types.h"
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+/*-------------------------------------------------------------------------*//**
+  The I2C_RELEASE_BUS constant is used to specify the options parameter to
+  functions I2C_read(), I2C_write() and I2C_write_read() to indicate
+  that a STOP bit must be generated at the end of the I2C transaction to release
+  the bus.
+ */
+#define I2C_RELEASE_BUS     0x00u
+
+/*-------------------------------------------------------------------------*//**
+  The I2C_HOLD_BUS constant is used to specify the options parameter to
+  functions I2C_read(), I2C_write() and I2C_write_read() to indicate
+  that a STOP bit must not be generated at the end of the I2C transaction in
+  order to retain the bus ownership. This causes the next transaction to
+  begin with a repeated START bit and no STOP bit between the transactions.
+ */
+#define I2C_HOLD_BUS        0x01u
+
+/*-------------------------------------------------------------------------*//**
+  The following constants specify the interrupt identifier number which will be
+  solely used by driver API. This has nothing to do with hardware interrupt line.
+  I2C_INT_IRQ is the primary interrupt signal which drives the state machine
+  of the CoreI2C driver. The I2C_SMBALERT_IRQ and I2C_SMBUS_IRQ are used by
+  SMBus interrupt enable and disable functions. These IRQ numbers are also used
+  by I2C_get_irq_status().
+ */
+#define I2C_NO_IRQ             0x00u
+#define I2C_SMBALERT_IRQ       0x01u
+#define I2C_SMBSUS_IRQ         0x02u
+#define I2C_INTR_IRQ           0x04u
+
+/*-------------------------------------------------------------------------*//**
+  The I2C_NO_TIMEOUT constant is used as parameter to the I2C_wait_complete()
+  function to indicate that the wait for completion of the transaction should
+  not time out.
+ */
+#define I2C_NO_TIMEOUT  0u
+
+/*-------------------------------------------------------------------------*//**
+  The i2c_channel_number_t type is used to specify the channel number of a
+  CoreI2C instance.
+ */
+typedef enum i2c_channel_number {
+    I2C_CHANNEL_0 = 0u,
+    I2C_CHANNEL_1,
+    I2C_CHANNEL_2,
+    I2C_CHANNEL_3,
+    I2C_CHANNEL_4,
+    I2C_CHANNEL_5,
+    I2C_CHANNEL_6,
+    I2C_CHANNEL_7,
+    I2C_CHANNEL_8,
+    I2C_CHANNEL_9,
+    I2C_CHANNEL_10,
+    I2C_CHANNEL_11,
+    I2C_CHANNEL_12,
+    I2C_CHANNEL_13,
+    I2C_CHANNEL_14,
+    I2C_CHANNEL_15,
+    I2C_MAX_CHANNELS = 16u
+} i2c_channel_number_t;
+
+/*-------------------------------------------------------------------------*//**
+  The i2c_clock_divider_t type is used to specify the divider to be applied
+  to the I2C PCLK or BCLK signal in order to generate the I2C clock.
+  The I2C_BCLK_DIV_8 value selects a clock frequency based on division of BCLK,
+  all other values select a clock frequency based on division of PCLK.
+ */
+typedef enum i2c_clock_divider {
+    I2C_PCLK_DIV_256 = 0u,
+    I2C_PCLK_DIV_224,
+    I2C_PCLK_DIV_192,
+    I2C_PCLK_DIV_160,
+    I2C_PCLK_DIV_960,
+    I2C_PCLK_DIV_120,
+    I2C_PCLK_DIV_60,
+    I2C_BCLK_DIV_8
+} i2c_clock_divider_t;
+
+/*-------------------------------------------------------------------------*//**
+  The i2c_status_t type is used to report the status of I2C transactions.
+ */
+typedef enum i2c_status
+{
+    I2C_SUCCESS = 0u,
+    I2C_IN_PROGRESS,
+    I2C_FAILED,
+    I2C_TIMED_OUT
+} i2c_status_t;
+
+/*-------------------------------------------------------------------------*//**
+  The i2c_slave_handler_ret_t type is used by slave write handler functions
+  to indicate whether or not the received data buffer should be released.
+ */
+typedef enum i2c_slave_handler_ret {
+    I2C_REENABLE_SLAVE_RX = 0u,
+    I2C_PAUSE_SLAVE_RX = 1u
+} i2c_slave_handler_ret_t;
+
+typedef struct i2c_instance i2c_instance_t ;
+
+/*-------------------------------------------------------------------------*//**
+  Slave write handler functions prototype.
+  ------------------------------------------------------------------------------
+  This defines the function prototype that must be followed by  I2C slave write
+  handler functions. These functions are registered with the CoreI2C driver
+  through the I2C_register_write_handler() function.
+
+  Declaring and Implementing Slave Write Handler Functions:
+    Slave write handler functions should follow the following prototype:
+    i2c_slave_handler_ret_t write_handler
+    ( 
+        i2c_instance_t *instance, uint8_t * data, uint16_t size 
+    );
+
+    The instance parameter is a pointer to the i2c_instance_t for which this
+    slave write handler has been declared.
+    
+    The data parameter is a pointer to a buffer (received data buffer) holding
+    the data written to the I2C slave.
+    
+    Defining the macro INCLUDE_SLA_IN_RX_PAYLOAD causes the driver to insert the
+    actual address used to access the slave as the first byte in the buffer.
+    This allows applications tailor their response based on the actual address
+    used to access the slave (primary address, secondary address or GCA).
+    
+    The size parameter is the number of bytes held in the received data buffer.
+    Handler functions must return one of the following values:
+        I2C_REENABLE_SLAVE_RX
+        I2C_PAUSE_SLAVE_RX.
+        
+    If the handler function returns I2C_REENABLE_SLAVE_RX, the driver releases
+    the received data buffer and allows further I2C write transactions to the
+    I2C slave to take place.
+    
+    If the handler function returns I2C_PAUSE_SLAVE_RX, the I2C slave responds
+    to subsequent write requests with a non-acknowledge bit (NACK), until the
+    received data buffer content has been processed by some other part of the
+    software application.
+    
+    A call to I2C_enable_slave() is required at some point after returning
+    I2C_PAUSE_SLAVE_RX in order to release the received data buffer so it can
+    be used to store data received by subsequent I2C write transactions.
+ */
+typedef i2c_slave_handler_ret_t (*i2c_slave_wr_handler_t)(i2c_instance_t *instance, uint8_t *, uint16_t );
+
+
+/*-------------------------------------------------------------------------*//**
+  i2c_instance_t
+  ------------------------------------------------------------------------------
+  This structure is used to identify the various CoreI2C hardware instances in
+  your system and the I2C channels within them. Your application software should
+  declare one instance of this structure for each channel of each instance of
+  CoreI2C in your system. The functions I2C_init() and I2C_channel_init() 
+  initialize this structure depending on whether it is channel 0 or one of the
+  additional channels respectively. A pointer to an initialized instance of the
+  structure should be passed as the first parameter to the CoreI2C driver
+  functions, to identify which CoreI2C hardware instance and channel should
+  perform the requested operation.
+  
+  The contents of this data structure should not be modified or used outside of
+  the CoreI2C driver. Software using the CoreI2C driver should only need to 
+  create one single instance of this data structure for each channel of each 
+  CoreI2C hardware instance in the system then pass a pointer to these data
+  structures with each call to the CoreI2C driver in order to identify the
+  CoreI2C hardware instance it wishes to use.
+ */
+struct i2c_instance
+{
+    addr_t base_address;
+    uint_fast8_t ser_address;
+
+    /* Transmit related info:*/
+    uint_fast8_t target_addr;
+
+    /* Current transaction type (WRITE, READ, RANDOM_READ)*/
+    uint8_t transaction;
+    
+    uint_fast16_t random_read_addr;
+
+    uint8_t options;
+    
+    /* Master TX INFO: */
+    const uint8_t * master_tx_buffer;
+    uint_fast16_t master_tx_size;
+    uint_fast16_t master_tx_idx;
+    uint_fast8_t dir;
+    
+    /* Master RX INFO: */
+    uint8_t * master_rx_buffer;
+    uint_fast16_t master_rx_size;
+    uint_fast16_t master_rx_idx;
+
+    /* Master Status */
+    volatile i2c_status_t master_status;
+    uint32_t master_timeout_ms;
+
+    /* Slave TX INFO */
+    const uint8_t * slave_tx_buffer;
+    uint_fast16_t slave_tx_size;
+    uint_fast16_t slave_tx_idx;
+    
+    /* Slave RX INFO */
+    uint8_t * slave_rx_buffer;
+    uint_fast16_t slave_rx_size;
+    uint_fast16_t slave_rx_idx;
+    /* Slave Status */
+    volatile i2c_status_t slave_status;
+    
+    /* Slave data: */
+    uint_fast8_t slave_mem_offset_length;
+    i2c_slave_wr_handler_t slave_write_handler;
+    uint8_t is_slave_enabled;
+    
+    /* user  specific data */
+    void *p_user_data ;
+
+    /* I2C bus status */
+    uint8_t bus_status;
+
+    /* Is transaction pending flag */
+    uint8_t is_transaction_pending;
+
+    /* I2C Pending transaction */
+    uint8_t pending_transaction;
+};
+
+/*-------------------------------------------------------------------------*//**
+  I2C initialization routine.
+  ------------------------------------------------------------------------------
+  The I2C_init() function is used to configure channel 0 of a CoreI2C instance.
+  It sets the base hardware address which is used to locate the CoreI2C instance
+  in memory and also used internally by I2C_channel_init() to calculate the
+  register addresses for any additional channels. The slave serial address set
+  is shared by all channels on a CoreI2C instance. 
+  
+  If only one channel is configured in a CoreI2C, the address of the 
+  i2c_instance_t used in I2C_Init() will also be used in subsequent calls to the
+  CoreI2C driver functions. If more than one channel is configured in the
+  CoreI2C, I2C_channel_init() will be called after I2C_init(), which initializes
+  the i2c_instance_t data structure for a specific channel.
+  ------------------------------------------------------------------------------
+ @param this_i2c:
+    Pointer to the i2c_instance_t data structure which will hold all data
+    related to channel 0 of the CoreI2C instance being initialized. A pointer
+    to this structure will be used in all subsequent calls to CoreI2C driver
+    functions which are to operate on channel 0 of this CoreI2C instance.
+  
+  @param base_address:
+    Base address in the processor's memory map of the registers of the CoreI2C
+    instance being initialized.
+ 
+  @param ser_address:
+    This parameter sets the primary I2C serial address (SLAVE0 address) for the
+    CoreI2C being initialized. It is the principal I2C bus address to which the
+    CoreI2C instance will respond. CoreI2C can operate in master mode or slave
+    mode and the serial address is significant only in the case of I2C slave
+    mode. In master mode, CoreI2C does not require a serial address and the
+    value of this parameter is not important. If you do not intend to use the
+    CoreI2C device in slave mode, then any dummy slave address value can be
+    provided to this parameter. However, in systems where the CoreI2C may be
+    expected to switch from master mode to slave mode, it is advisable to
+    initialize the CoreI2C device with a valid serial slave address.
+    
+    You need to call the I2C_init() function whenever it is required to change 
+    the primary slave address as there is no separate function to set the
+    primary slave address of the I2C device. The serial address being
+    initialized through this function is basically the primary slave address or
+    slave address0. I2C_set_slave_second_addr() can be used to set the
+    secondary slave address or slave address 1.
+    Note : ser_address parameter does not have any affect if fixed slave 
+           address is enabled in CoreI2C hardware design. CoreI2C will 
+           be always addressed with the hardware configured fixed slave
+           address.
+    Note : ser_address parameter will not have any affect if the CoreI2C
+           instance is only used in master mode.
+
+  @param ser_clock_speed:
+    This parameter sets the I2C serial clock frequency. It selects the divider
+    that will be used to generate the serial clock from the APB PCLK or from
+    the BCLK. It can be one of the following:
+        I2C_PCLK_DIV_256
+        I2C_PCLK_DIV_224
+        I2C_PCLK_DIV_192
+        I2C_PCLK_DIV_160
+        I2C_PCLK_DIV_960
+        I2C_PCLK_DIV_120
+        I2C_PCLK_DIV_60
+        I2C_BCLK_DIV_8
+    Note: serial_clock_speed value will have no affect if Fixed baud rate is 
+          enabled in CoreI2C hardware instance configuration dialogue window. 
+          The fixed baud rate divider value will override the value
+          passed as parameter in this function.
+    Note: serial_clock_speed value is not critical for devices that only operate
+          as slaves and can be set to any of the above values.  
+
+  @return none.  
+  
+  Example:
+  @code
+    #define COREI2C_BASE_ADDR  0xC0000000u
+    #define COREI2C_SER_ADDR   0x10u
+
+    i2c_instance_t g_i2c_inst;
+
+    void system_init( void )
+    {
+        I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, COREI2C_SER_ADDR,
+                  I2C_PCLK_DIV_256 );
+    }
+  @endcode
+ */
+void I2C_init
+(
+    i2c_instance_t * this_i2c,
+    addr_t base_address,
+    uint8_t ser_address,
+    i2c_clock_divider_t ser_clock_speed
+);
+
+/*-------------------------------------------------------------------------*//**
+  I2C channel initialization routine.
+  ------------------------------------------------------------------------------
+  The I2C_channel_init() function initializes and configures hardware and data
+  structures of one of the additional channels of a CoreI2C instance.
+  I2C_init() must be called before calling this function to set the CoreI2C
+  instance hardware base address and I2C serial address. I2C_channel_init() also
+  initializes I2C serial clock divider to set the serial clock baud rate.  
+  The pointer to data structure i2c_instance_t used for a particular channel
+  will be used as an input parameter to subsequent CoreI2C driver functions
+  which operate on this channel.
+  ------------------------------------------------------------------------------
+  @param this_i2c_channel
+    Pointer to the i2c_instance_t data structure holding all data related to the
+    CoreI2C channel being initialized. A pointer to the same data structure will
+    be used in subsequent calls to the CoreI2C driver functions in order to
+    identify the CoreI2C channel instance that should perform the operation 
+    implemented by the called driver function.
+
+  @param this_i2c:
+    This is a pointer to an i2c_instance_t structure previously initialized by
+    I2C_init(). It holds information regarding the hardware base address and
+    I2C serial address for the CoreI2C containing the channel to be
+    initialized. This information is required by I2C_channel_init() to
+    initialize the i2c_instance_t structure pointed to by this_i2c_channel as
+    all channels in a CoreI2C instance share the same base address and serial
+    address. It is very important that the i2c_instance_t structure pointed to
+    by this_i2c has been previously initialized with a call to I2C_init().
+    
+  @param channel_number:
+    This parameter of type i2c_channel_number_t identifies the channel to be
+    initialized.
+
+  @param ser_clock_speed:
+    This parameter sets the I2C serial clock frequency. It selects the divider
+    that will be used to generate the serial clock from the APB PCLK or from
+    the BCLK. It can be one of the following:
+        I2C_PCLK_DIV_256
+        I2C_PCLK_DIV_224
+        I2C_PCLK_DIV_192
+        I2C_PCLK_DIV_160
+        I2C_PCLK_DIV_960
+        I2C_PCLK_DIV_120
+        I2C_PCLK_DIV_60
+        I2C_BCLK_DIV_8
+    
+    Note: serial_clock_speed value will have no affect if Fixed baud rate is 
+          enabled in CoreI2C hardware instance configuration dialogue window. 
+          The fixed baud rate divider value will supersede the value 
+          passed as parameter in this function.
+
+    Note: ser_clock_speed value is not critical for devices that only operate
+          as slaves and can be set to any of the above values.  
+  @return none.  
+  
+  Example:
+  @code
+    #define COREI2C_BASE_ADDR  0xC0000000u
+    #define COREI2C_SER_ADDR   0x10u
+    #define DATA_LENGTH        16u
+
+    i2c_instance_t g_i2c_inst;
+    i2c_instance_t g_i2c_channel_1_inst;
+
+    uint8_t  tx_buffer[DATA_LENGTH];
+    uint8_t  write_length = DATA_LENGTH;
+
+    void system_init( void )
+    {
+        uint8_t  target_slave_addr = 0x12;
+        
+        // Initialize base CoreI2C instance
+        I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, COREI2C_SER_ADDR,
+                  I2C_PCLK_DIV_256 );
+        
+        // Initialize CoreI2C channel 1 with different clock speed
+        I2C_channel_init( &g_i2c_channel_1_inst, &g_i2c_inst, I2C_CHANNEL_1,
+                          I2C_PCLK_DIV_224 );
+        
+        // Write data to Channel 1 of CoreI2C instance.
+        I2C_write( &g_i2c_channel_1_inst, target_slave_addr, tx_buffer,
+                   write_length, I2C_RELEASE_BUS );
+    }
+  @endcode
+          
+*/
+void I2C_channel_init
+(
+    i2c_instance_t * this_i2c_channel,
+    i2c_instance_t * this_i2c,
+    i2c_channel_number_t channel_number,
+    i2c_clock_divider_t ser_clock_speed
+);
+
+/*------------------------------------------------------------------------------
+  CoreI2C interrupt service routine.
+  ------------------------------------------------------------------------------
+    The function I2C_isr is the CoreI2C interrupt service routine. User must
+    call this function from their application level CoreI2C interrupt handler
+    function. This function runs the I2C state machine based on previous and 
+    current status.
+  ------------------------------------------------------------------------------
+    @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+    
+    @return none
+    
+    Example:
+    @code
+    
+    #define COREI2C_BASE_ADDR  0xC0000000u
+    #define COREINTERRUPT_BASE_ADDR  0xCC000000u
+    #define COREI2C_SER_ADDR   0x10u
+    #define I2C_IRQ_NB           2u
+    
+    i2c_instance_t g_i2c_inst;
+
+    void core_i2c_isr( void )
+    {
+       I2C_isr( &g_i2c_inst );
+    }
+    
+   void main( void )
+    {
+        CIC_init( COREINTERRUPT_BASE_ADDR );
+        NVIC_init();
+        CIC_set_irq_handler( I2C_IRQ_NB, core_i2c_isr );
+        I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, COREI2C_SER_ADDR,
+                  I2C_PCLK_DIV_256 );
+        NVIC_enable_interrupt( NVIC_IRQ_0 );
+    }
+    @endcode
+ */
+void I2C_isr
+(
+    i2c_instance_t * this_i2c
+);
+
+/*******************************************************************************
+ *******************************************************************************
+ * 
+ *                           Master specific functions
+ * 
+ * The following functions are only used within an I2C master's implementation.
+ */
+ 
+/*-------------------------------------------------------------------------*//**
+  I2C master write function.
+  ------------------------------------------------------------------------------
+  This function initiates an I2C master write transaction. This function returns
+  immediately after initiating the transaction. The content of the write buffer
+  passed as parameter should not be modified until the write transaction
+  completes. It also means that the memory allocated for the write buffer should
+  not be freed or should not go out of scope before the write completes. You can
+  check for the write transaction completion using the I2C_status() function.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+
+  @param serial_addr:
+    This parameter specifies the serial address of the target I2C device.
+  
+  @param write_buffer:
+    This parameter is a pointer to a buffer holding the data to be written to
+    the target I2C device.
+    Care must be taken not to release the memory used by this buffer before the
+    write transaction completes. For example, it is not appropriate to return
+    from a function allocating this buffer as an auto array variable before the
+    write transaction completes as this would result in the buffer's memory 
+    being de-allocated from the stack when the function returns. This memory
+    could then be subsequently reused and modified causing unexpected data to 
+    be written to the target I2C device.
+  
+  @param write_size:
+    Number of bytes held in the write_buffer to be written to the target I2C
+    device.
+ 
+  @param options:
+    The options parameter is used to indicate if the I2C bus should be released
+    on completion of the write transaction. Using the I2C_RELEASE_BUS
+    constant for the options parameter causes a STOP bit to be generated at the
+    end of the write transaction causing the bus to be released for other I2C
+    devices to use. Using the I2C_HOLD_BUS constant as options parameter
+    prevents a STOP bit from being generated at the end of the write
+    transaction, preventing other I2C devices from initiating a bus transaction.
+  
+  @return none.  
+  
+  Example:
+  @code
+    #define COREI2C_BASE_ADDR  0xC0000000u
+    #define COREI2C_DUMMY_ADDR   0x10u
+    #define DATA_LENGTH           16u
+
+    i2c_instance_t g_i2c_inst;
+
+    uint8_t  tx_buffer[DATA_LENGTH];
+    uint8_t  write_length = DATA_LENGTH;     
+
+    void main( void )
+    {
+        uint8_t  target_slave_addr = 0x12;
+        i2c_status_t status;
+        
+        // Initialize base CoreI2C instance
+        I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, COREI2C_DUMMY_ADDR,
+                  I2C_PCLK_DIV_256 );
+        
+        // Write data to Channel 0 of CoreI2C instance.
+        I2C_write( &g_i2c_inst, target_slave_addr, tx_buffer, write_length,
+                   I2C_RELEASE_BUS );
+                   
+        // Wait for completion and record the outcome
+        status = I2C_wait_complete( &g_i2c_inst, I2C_NO_TIMEOUT );
+    }
+  @endcode
+ */
+void I2C_write
+(
+    i2c_instance_t * this_i2c,
+    uint8_t serial_addr,
+    const uint8_t * write_buffer,
+    uint16_t write_size,
+    uint8_t options
+);
+
+/*-------------------------------------------------------------------------*//**
+  I2C master read.
+  ------------------------------------------------------------------------------
+  This function initiates an I2C master read transaction. This function returns
+  immediately after initiating the transaction.
+  The contents of the read buffer passed as parameter should not be modified
+  until the read transaction completes. It also means that the memory allocated
+  for the read buffer should not be freed or should not go out of scope before
+  the read completes. You can check for the read transaction completion using 
+  the I2C_status() function.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+  
+  @param serial_addr:
+    This parameter specifies the serial address of the target I2C device.
+  
+  @param read_buffer
+    This is a pointer to a buffer where the data received from the target device
+    will be stored.
+    Care must be taken not to release the memory used by this buffer before the
+    read transaction completes. For example, it is not appropriate to return
+    from a function allocating this buffer as an auto array variable before the
+    read transaction completes as this would result in the buffer's memory being
+    de-allocated from the stack when the function returns. This memory could
+    then be subsequently reallocated resulting in the read transaction
+    corrupting the newly allocated memory. 
+
+  @param read_size:
+    This parameter specifies the number of bytes to read from the target device.
+    This size must not exceed the size of the read_buffer buffer.
+ 
+  @param options:
+    The options parameter is used to indicate if the I2C bus should be released
+    on completion of the read transaction. Using the I2C_RELEASE_BUS
+    constant for the options parameter causes a STOP bit to be generated at the
+    end of the read transaction causing the bus to be released for other I2C
+    devices to use. Using the I2C_HOLD_BUS constant as options parameter
+    prevents a STOP bit from being generated at the end of the read transaction,
+    preventing other I2C devices from initiating a bus transaction.
+    
+  @return none.  
+  
+  Example:
+  @code
+    #define COREI2C_BASE_ADDR  0xC0000000u
+    #define COREI2C_DUMMY_ADDR   0x10u
+    #define DATA_LENGTH           16u
+
+    i2c_instance_t g_i2c_inst;
+
+    uint8_t  rx_buffer[DATA_LENGTH];
+    uint8_t  read_length = DATA_LENGTH;     
+
+    void main( void )
+    {
+        uint8_t  target_slave_addr = 0x12;
+        i2c_status_t status;
+        
+        // Initialize base CoreI2C instance
+        I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, COREI2C_DUMMY_ADDR,
+                  I2C_PCLK_DIV_256 );
+        
+        // Read data from target slave Channel 0 of CoreI2C instance.
+        I2C_read( &g_i2c_inst, target_slave_addr, rx_buffer, read_length,
+                  I2C_RELEASE_BUS );
+        
+        status = I2C_wait_complete( &g_i2c_inst, I2C_NO_TIMEOUT );
+    }
+  @endcode
+ */
+void I2C_read
+(
+    i2c_instance_t * this_i2c,
+    uint8_t serial_addr,
+    uint8_t * read_buffer,
+    uint16_t read_size,
+    uint8_t options
+);
+
+/*-------------------------------------------------------------------------*//**
+  I2C master write-read
+  ------------------------------------------------------------------------------
+  This function initiates an I2C write-read transaction where data is first
+  written to the target device before issuing a restart condition and changing
+  the direction of the I2C transaction in order to read from the target device.
+  
+  The same warnings about buffer allocation in I2C_write() and I2C_read() 
+  apply to this function.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of
+    channel 0 of the instantiated CoreI2C hardware.
+  
+  @param serial_addr:
+    This parameter specifies the serial address of the target I2C device.
+  
+  @param addr_offset:
+    This parameter is a pointer to the buffer containing the data that will be
+    sent to the slave during the write phase of the write-read transaction. This
+    data is typically used to specify an address offset specifying to the I2C
+    slave device what data it must return during the read phase of the
+    write-read transaction.
+  
+  @param offset_size:
+    This parameter specifies the number of offset bytes to be written during the
+    write phase of the write-read transaction. This is typically the size of the
+    buffer pointed to by the addr_offset parameter.
+  
+  @param read_buffer:
+    This parameter is a pointer to the buffer where the data read from the I2C
+    slave will be stored.
+  
+  @param read_size:
+    This parameter specifies the number of bytes to read from the target I2C
+    slave device. This size must not exceed the size of the buffer pointed to by
+    the read_buffer parameter.
+ 
+  @param options:
+    The options parameter is used to indicate if the I2C bus should be released
+    on completion of the write-read transaction. Using the I2C_RELEASE_BUS
+    constant for the options parameter causes a STOP bit to be generated at the
+    end of the write-read transaction causing the bus to be released for other
+    I2C devices to use. Using the I2C_HOLD_BUS constant as options parameter
+    prevents a STOP bit from being generated at the end of the write-read
+    transaction, preventing other I2C devices from initiating a bus transaction.
+        
+  @return none.  
+  
+  Example:
+  @code
+    #define COREI2C_BASE_ADDR    0xC0000000u
+    #define COREI2C_DUMMY_ADDR   0x10u
+    #define TX_LENGTH            16u
+    #define RX_LENGTH            8u
+
+    i2c_instance_t g_i2c_inst;
+    uint8_t  rx_buffer[RX_LENGTH];
+    uint8_t  read_length = RX_LENGTH;     
+    uint8_t  tx_buffer[TX_LENGTH];
+    uint8_t  write_length = TX_LENGTH;  
+    
+    void main( void )
+    {
+        uint8_t  target_slave_addr = 0x12;
+        i2c_status_t status;
+        // Initialize base CoreI2C instance
+        I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, COREI2C_DUMMY_ADDR,
+                  I2C_PCLK_DIV_256 );
+                  
+        I2C_write_read( &g_i2c_inst, target_slave_addr, tx_buffer, write_length,
+                        rx_buffer, read_length, I2C_RELEASE_BUS );
+                        
+        status = I2C_wait_complete( &g_i2c_inst, I2C_NO_TIMEOUT );
+    }
+  @endcode
+ */
+void I2C_write_read
+(
+    i2c_instance_t * this_i2c,
+    uint8_t serial_addr,
+    const uint8_t * addr_offset,
+    uint16_t offset_size,
+    uint8_t * read_buffer,
+    uint16_t read_size,
+    uint8_t options
+);
+    
+/*-------------------------------------------------------------------------*//**
+  I2C status
+  ------------------------------------------------------------------------------
+  This function indicates the current state of a CoreI2C channel.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+  ------------------------------------------------------------------------------
+  @return
+    The return value indicates the current state of a CoreI2C channel or the
+    outcome of the previous transaction if no transaction is in progress. 
+    Possible return values are:
+      I2C_SUCCESS
+        The last I2C transaction has completed successfully.  
+      I2C_IN_PROGRESS
+        There is an I2C transaction in progress.
+      I2C_FAILED
+        The last I2C transaction failed.
+      I2C_TIMED_OUT
+        The request has failed to complete in the allotted time.      
+  
+  Example:
+  @code
+    i2c_instance_t g_i2c_inst;
+    
+    while( I2C_IN_PROGRESS == I2C_get_status( &g_i2c_inst ) )
+    {
+        // Do something useful while waiting for I2C operation to complete
+        our_i2c_busy_task();
+    }
+    
+    if( I2C_SUCCESS != I2C_get_status( &g_i2c_inst ) )
+    {
+        // Something went wrong... 
+        our_i2c_error_recovery( &g_i2c_inst );
+    }
+  @endcode
+ */
+i2c_status_t I2C_get_status
+(
+    i2c_instance_t * this_i2c
+);
+
+/*-------------------------------------------------------------------------*//**
+  Wait for I2C transaction completion.
+  ------------------------------------------------------------------------------
+  This function waits for the current I2C transaction to complete. The return
+  value indicates whether the last I2C transaction was successful or not.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of
+    channel 0 of the instantiated CoreI2C hardware.
+  @param timeout_ms:
+    The timeout_ms parameter specified the delay within which the current I2C 
+    transaction is expected to complete. The time out delay is given in 
+    milliseconds. I2C_wait_complete() will return I2C_TIMED_OUT if the current
+    transaction has not completed after the time out delay has expired. This
+    parameter can be set to I2C_NO_TIMEOUT to indicate that I2C_wait_complete()
+    must not time out.
+  ------------------------------------------------------------------------------
+  @return
+    The return value indicates the outcome of the last I2C transaction. It can
+    be one of the following: 
+      I2C_SUCCESS
+        The last I2C transaction has completed successfully.
+      I2C_FAILED
+        The last I2C transaction failed.
+      I2C_TIMED_OUT
+        The last transaction failed to complete within the time out delay given
+        as second parameter.
+
+  Example:
+  @code
+    #define COREI2C_BASE_ADDR  0xC0000000u
+    #define COREI2C_DUMMY_ADDR   0x10u
+    #define DATA_LENGTH           16u
+
+    i2c_instance_t g_i2c_inst;
+
+    uint8_t  rx_buffer[DATA_LENGTH];
+    uint8_t  read_length = DATA_LENGTH;     
+
+    void main( void )
+    {
+        uint8_t  target_slave_addr = 0x12;
+        i2c_status_t status;
+        
+        // Initialize base CoreI2C instance
+        I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, COREI2C_DUMMY_ADDR,
+                  I2C_PCLK_DIV_256 );
+        
+        // Read data from Channel 0 of CoreI2C instance.
+        I2C_read( &g_i2c_inst, target_slave_addr, rx_buffer, read_length,
+                  I2C_RELEASE_BUS );
+        
+        // Wait for completion and record the outcome
+        status = I2C_wait_complete( &g_i2c_inst, I2C_NO_TIMEOUT );
+    }
+  @endcode
+ */
+i2c_status_t I2C_wait_complete
+(
+    i2c_instance_t * this_i2c,
+    uint32_t timeout_ms
+);
+
+/*-------------------------------------------------------------------------*//**
+  Time out delay expiration.
+  ------------------------------------------------------------------------------
+  This function is used to control the expiration of the time out delay
+  specified as a parameter to the I2C_wait_complete() function. It must be
+  called from the interrupt service routine of a periodic interrupt source such
+  as the Cortex-M3 SysTick timer interrupt. It takes the period of the interrupt
+  source as its ms_since_last_tick parameter and uses it as the time base for
+  the I2C_wait_complete() function’s time out delay.
+  
+  Note: This function does not need to be called if the I2C_wait_complete()
+        function is called with a timeout_ms value of I2C_NO_TIMEOUT.
+  Note: If this function is not called then the I2C_wait_complete() function
+        will behave as if its timeout_ms was specified as I2C_NO_TIMEOUT and it
+        will not time out.
+  Note: If this function is being called from an interrupt handler (e.g SysTick)
+        it is important that the calling interrupt have a lower priority than
+        the CoreI2C interrupt(s) to ensure any updates to shared data are
+        protected.
+  
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+  @param ms_since_last_tick:
+    The ms_since_last_tick parameter specifies the number of milliseconds that
+    elapsed since the last call to I2C_system_tick(). This parameter would
+    typically be a constant specifying the interrupt rate of a timer used to
+    generate system ticks.
+  ------------------------------------------------------------------------------
+  @return
+    none.
+
+  Example:
+    The example below shows an example of how the I2C_system_tick() function
+    would be called in a Cortex-M3 based system. I2C_system_tick() is called for
+    each I2C channel from the Cortex-M3 SysTick timer interrupt service routine.
+    The SysTick is configured to generate an interrupt every 10 milliseconds in
+    the example below.
+  @code
+    #define SYSTICK_INTERVAL_MS 10
+   
+    void SysTick_Handler(void)
+    {
+        I2C_system_tick(&g_core_i2c0, SYSTICK_INTERVAL_MS);
+        I2C_system_tick(&g_core_i2c2, SYSTICK_INTERVAL_MS);
+    }
+  @endcode
+ */
+void I2C_system_tick
+(
+    i2c_instance_t * this_i2c,
+    uint32_t ms_since_last_tick
+);
+
+/*******************************************************************************
+ *******************************************************************************
+ * 
+ *                           Slave specific functions
+ * 
+ * The following functions are only used within the implementation of an I2C
+ * slave device.
+ */
+
+/*-------------------------------------------------------------------------*//**
+  I2C slave transmit buffer configuration.
+  ------------------------------------------------------------------------------
+  This function specifies the memory buffer holding the data that will be sent
+  to the I2C master when this CoreI2C channel is the target of an I2C read or
+  write-read transaction.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+  
+  @param tx_buffer:
+    This parameter is a pointer to the memory buffer holding the data to be
+    returned to the I2C master when this CoreI2C channel is the target of an
+    I2C read or write-read transaction.
+  
+  @param tx_size:
+    Size of the transmit buffer pointed to by the tx_buffer parameter.
+
+  @return none.  
+      
+  Example:
+  @code
+    #define COREI2C_BASE_ADDR    0xC0000000u
+    #define SLAVE_SER_ADDR       0x10u
+    #define SLAVE_TX_BUFFER_SIZE 10u
+
+    i2c_instance_t g_i2c_inst;
+
+    uint8_t g_slave_tx_buffer[SLAVE_TX_BUFFER_SIZE] = { 1, 2, 3, 4, 5,
+                                                        6, 7, 8, 9, 10 };
+
+    void main( void )
+    {
+        // Initialize the CoreI2C driver with its base address, I2C serial
+        // address and serial clock divider.
+        I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
+                  I2C_PCLK_DIV_256 );
+       
+        // Specify the transmit buffer containing the data that will be
+        // returned to the master during read and write-read transactions.
+        I2C_set_slave_tx_buffer( &g_i2c_inst, g_slave_tx_buffer, 
+                                 sizeof(g_slave_tx_buffer) );
+    }
+  @endcode
+ */
+void I2C_set_slave_tx_buffer
+(
+    i2c_instance_t * this_i2c,
+    const uint8_t * tx_buffer,
+    uint16_t tx_size
+);
+
+/*-------------------------------------------------------------------------*//**
+  I2C slave receive buffer configuration.
+  ------------------------------------------------------------------------------
+  This function specifies the memory buffer that will be used by the CoreI2C
+  channel to receive data when it is a slave. This buffer is the memory where
+  data will be stored when the CoreI2C channel is the target of an I2C master
+  write transaction (i.e. when it is the slave).
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+  
+  @param rx_buffer:
+    This parameter is a pointer to the memory buffer allocated by the caller
+    software to be used as a slave receive buffer.
+  
+  @param rx_size:
+    Size of the slave receive buffer. This is the amount of memory that is
+    allocated to the buffer pointed to by rx_buffer.
+    Note:   This buffer size indirectly specifies the maximum I2C write
+            transaction length this CoreI2C channel can be the target of. This
+            is because this CoreI2C channel responds to further received
+            bytes with a non-acknowledge bit (NACK) as soon as its receive
+            buffer is full. This causes the write transaction to fail.
+            
+  @return none.  
+      
+  Example:
+  @code
+    #define COREI2C_BASE_ADDR    0xC0000000u
+    #define SLAVE_SER_ADDR       0x10u
+    #define SLAVE_RX_BUFFER_SIZE 10u
+
+    i2c_instance_t g_i2c_inst;
+
+    uint8_t g_slave_rx_buffer[SLAVE_RX_BUFFER_SIZE];
+
+    void main( void )
+    {
+        // Initialize the CoreI2C driver with its base address, I2C serial
+        // address and serial clock divider.
+        I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
+                  I2C_PCLK_DIV_256 );
+       
+        // Specify the buffer used to store the data written by the I2C master.
+        I2C_set_slave_rx_buffer( &g_i2c_inst, g_slave_rx_buffer, 
+                                 sizeof(g_slave_rx_buffer) );
+    }
+  @endcode
+ */
+void I2C_set_slave_rx_buffer
+(
+    i2c_instance_t * this_i2c,
+    uint8_t * rx_buffer,
+    uint16_t rx_size
+);
+
+/*-------------------------------------------------------------------------*//**
+  I2C slave memory offset length configuration.
+  ------------------------------------------------------------------------------
+  This function is used as part of the configuration of a CoreI2C channel for
+  operation as a slave supporting write-read transactions. It specifies the
+  number of bytes expected as part of the write phase of a write-read
+  transaction. The bytes received during the write phase of a write-read
+  transaction will be interpreted as an offset into the slave's transmit buffer.
+  This allows random access into the I2C slave transmit buffer from a remote
+  I2C master.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+  
+  @param offset_length:
+    The offset_length parameter configures the number of bytes to be interpreted
+    by the CoreI2C slave as a memory offset value during the write phase of
+    write-read transactions. The maximum value for the offset_length parameter
+    is two. The value of offset_length has the following effect on the 
+    interpretation of the received data.
+    
+      If offset_length is 0, the offset into the transmit buffer is fixed at 0.
+      
+      If offset_length is 1, a single byte of received data is interpreted as an
+      unsigned 8 bit offset value in the range 0 to 255.
+      
+      If offset_length is 2, 2 bytes of received data are interpreted as an
+      unsigned 16 bit offset value in the range 0 to 65535. The first byte
+      received in this case provides the high order bits of the offset and
+      the second byte provides the low order bits.
+      
+    If the number of bytes received does not match the non 0 value of
+    offset_length the transmit buffer offset is set to 0.
+            
+  @return none.  
+      
+  Example:
+  @code
+    #define COREI2C_BASE_ADDR    0xC0000000u
+    #define SLAVE_SER_ADDR       0x10u
+    #define SLAVE_TX_BUFFER_SIZE 10u
+
+    i2c_instance_t g_i2c_inst;
+
+    uint8_t g_slave_tx_buffer[SLAVE_TX_BUFFER_SIZE] = { 1, 2, 3, 4, 5,
+                                                        6, 7, 8, 9, 10 };
+
+    void main( void )
+    {
+        // Initialize the CoreI2C driver with its base address, I2C serial
+        // address and serial clock divider.
+        I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
+                  I2C_PCLK_DIV_256 );
+        I2C_set_slave_tx_buffer( &g_i2c_inst, g_slave_tx_buffer, 
+                                 sizeof(g_slave_tx_buffer) );
+        I2C_set_slave_mem_offset_length( &g_i2c_inst, 1 );
+    }
+  @endcode        
+ */
+void I2C_set_slave_mem_offset_length
+(
+    i2c_instance_t * this_i2c,
+    uint8_t offset_length
+);
+
+/*-------------------------------------------------------------------------*//**
+  I2C write handler registration. 
+  ------------------------------------------------------------------------------
+  Register the function that is called to process the data written to this
+  CoreI2C channel when it is the slave in an I2C write transaction.
+  Note: If a write handler is registered, it is called on completion of the
+        write phase of a write-read transaction and responsible for processing
+        the received data in the slave receive buffer and populating the slave
+        transmit buffer with the data that will be transmitted to the I2C master
+        as part of the read phase of the write-read transaction. If a write
+        handler is not registered, the write data of a write read transaction is
+        interpreted as an offset into the slave’s transmit buffer and handled by
+        the driver.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+  
+  @param handler:
+    Pointer to the function that will process the I2C write request.
+            
+  @return none.  
+      
+  Example:
+  @code
+    #define COREI2C_BASE_ADDR    0xC0000000u
+    #define SLAVE_SER_ADDR       0x10u
+    #define SLAVE_TX_BUFFER_SIZE 10u
+
+    i2c_instance_t g_i2c_inst;
+
+    uint8_t g_slave_tx_buffer[SLAVE_TX_BUFFER_SIZE] = { 1, 2, 3, 4, 5,
+                                                       6, 7, 8, 9, 10 };
+
+    // local function prototype
+    void slave_write_handler
+    (
+        i2c_instance_t * this_i2c,
+        uint8_t * p_rx_data,
+        uint16_t rx_size
+    );
+
+    void main( void )
+    {
+        // Initialize the CoreI2C driver with its base address, I2C serial
+        // address and serial clock divider.
+        I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR, 
+                  I2C_PCLK_DIV_256 );
+        I2C_set_slave_tx_buffer( &g_i2c_inst, g_slave_tx_buffer, 
+                                 sizeof(g_slave_tx_buffer) );
+        I2C_set_slave_mem_offset_length( &g_i2c_inst, 1 );
+        I2C_register_write_handler( &g_i2c_inst, slave_write_handler );
+    }
+  @endcode    
+*/
+void I2C_register_write_handler
+(
+    i2c_instance_t * this_i2c,
+    i2c_slave_wr_handler_t handler
+);
+
+/*-------------------------------------------------------------------------*//**
+  I2C slave enable.
+  ------------------------------------------------------------------------------
+  This function enables slave mode operation for a CoreI2C channel. It enables 
+  the CoreI2C slave to receive data when it is the target of an I2C read, write
+  or write-read transaction.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+
+  @return none.
+
+  Example:
+  @code
+    // Enable I2C slave
+    I2C_enable_slave( &g_i2c_inst );
+  @endcode
+ */
+void I2C_enable_slave
+(
+    i2c_instance_t * this_i2c
+);
+
+/*-------------------------------------------------------------------------*//**
+  I2C slave disable.
+  ------------------------------------------------------------------------------
+  This function disables slave mode operation for a CoreI2C channel. It stops
+  the CoreI2C slave acknowledging I2C read, write or write-read transactions
+  targeted at it.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+
+  @return none.
+
+  Example:
+  @code
+   // Disable I2C slave
+   I2C_disable_slave( &g_i2c_inst );
+  @endcode
+ */
+void I2C_disable_slave
+(
+    i2c_instance_t * this_i2c
+);
+/*-------------------------------------------------------------------------*//**
+  Set I2C slave second address.
+  ------------------------------------------------------------------------------
+  The function I2C_set_slave_second_addr() sets the secondary slave address for
+  a CoreI2C slave device. This is an additional slave address which might be
+  required in certain applications, for example to enable fail-safe operation in
+  a system. As the CoreI2C device supports 7-bit addressing, the highest value
+  which can be assigned to second slave address is 127 (0x7F).
+  Note: This function does not support CoreI2C hardware configured with a fixed 
+      second slave address.  The current implementation of the ADDR1[0] register
+      bit makes it difficult for the driver to support both programmable and
+      fixed second slave address, so we choose to support programmable only.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+
+  @param second_slave_addr:
+    The second_slave_addr parameter is the secondary slave address of the I2C
+    device.
+
+  @return
+    none.
+
+  Example:
+  @code
+    #define COREI2C_BASE_ADDR  0xC0000000u
+    #define SLAVE_SER_ADDR     0x10u
+    #define SECOND_SLAVE_ADDR  0x20u
+
+    i2c_instance_t g_i2c_inst;
+    void main( void )
+    {
+        // Initialize the CoreI2C driver with its base address, primary I2C
+        // serial address and serial clock divider.
+        I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR, 
+                  I2C_PCLK_DIV_256 );
+        I2C_set_slave_second_addr( &g_i2c_inst, SECOND_SLAVE_ADDR );
+    }
+  @endcode
+ */
+void I2C_set_slave_second_addr
+(
+    i2c_instance_t * this_i2c,
+    uint8_t second_slave_addr
+);
+
+/*-------------------------------------------------------------------------*//**
+  Disable second slave address.
+  ------------------------------------------------------------------------------
+  The function I2C_disable_slave_second_addr() disables the secondary slave
+  address of the CoreI2C slave device. 
+  Note: This version of the driver only supports CoreI2C hardware configured
+        with a programmable second slave address.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+
+  @return
+    none.
+
+  Example:
+  @code
+    i2c_instance_t g_i2c_inst;
+    I2C_disable_slave_second_addr( &g_i2c_inst);
+  @endcode
+ */
+void I2C_disable_slave_second_addr
+(
+    i2c_instance_t * this_i2c
+);
+
+/*-------------------------------------------------------------------------*//**
+  The I2C_set_gca() function is used to set the general call acknowledgement bit
+  of a CoreI2C slave device. This allows all channels of the CoreI2C slave
+  device respond to a general call or broadcast message from an I2C master.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+
+  @return
+    none.
+
+  Example:
+  @code
+    i2c_instance_t g_i2c_inst;
+
+    // Enable recognition of the General Call Address
+    I2C_set_gca( &g_i2c_inst ); 
+  @endcode
+ */
+void I2C_set_gca
+(
+    i2c_instance_t * this_i2c
+);
+
+/*-------------------------------------------------------------------------*//**
+  The I2C_clear_gca() function is used to clear the general call acknowledgement
+  bit of a CoreI2C slave device. This will stop all channels of the I2C slave
+  device responding to any general call or broadcast message from the master.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+
+  @return
+    none.
+
+  Example:
+  @code
+    i2c_instance_t g_i2c_inst;
+
+    // Disable recognition of the General Call Address
+    I2C_clear_gca( &g_i2c_inst );
+  @endcode
+ */
+
+void I2C_clear_gca
+(
+    i2c_instance_t * this_i2c
+);
+
+/*------------------------------------------------------------------------------
+                      I2C SMBUS specific APIs
+ ----------------------------------------------------------------------------*/
+
+/*-------------------------------------------------------------------------*//**
+  The I2C_smbus_init() function enables SMBus timeouts and status logic for a
+  CoreI2C channel.
+  Note: This and any of the other SMBus related functionality will only have an
+        effect if the CoreI2C was instantiated with the Generate SMBus Logic
+        option checked.
+  Note: If the CoreI2C was instantiated with the Generate IPMI Logic option
+        checked this function will enable the IPMI 3mS SCL low timeout but none
+        of the other SMBus functions will have any effect.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+
+  @return
+    none.
+
+  Example:
+  @code
+   #define COREI2C_BASE_ADDR  0xC0000000u
+   #define SLAVE_SER_ADDR     0x10u
+
+   i2c_instance_t g_i2c_inst;
+
+   void system_init( void )
+   {
+        I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
+                  I2C_PCLK_DIV_256 );
+        
+        // Initialize SMBus feature
+        I2C_smbus_init( &g_i2c_inst);
+   }
+  @endcode    
+ */
+void I2C_smbus_init
+(
+    i2c_instance_t * this_i2c
+);
+
+/*-------------------------------------------------------------------------*//**
+  The I2C_enable_smbus_irq() function is used to enable the CoreI2C channel’s 
+  SMBSUS and SMBALERT SMBus interrupts.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+
+  @param irq_type
+    The irq_type specify the SMBUS interrupt(s) which will be enabled.
+    The two possible interrupts are:
+      I2C_SMBALERT_IRQ
+      I2C_SMBSUS_IRQ
+    To enable both ints in one call, use I2C_SMBALERT_IRQ | I2C_SMBSUS_IRQ.
+    
+  @return
+    none
+  
+  Example:
+  @code
+    #define COREI2C_BASE_ADDR  0xC0000000u
+    #define SLAVE_SER_ADDR     0x10u
+
+    i2c_instance_t g_i2c_inst;
+
+    void main( void )
+    {
+        I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
+                  I2C_PCLK_DIV_256 );
+        
+        // Initialize SMBus feature
+        I2C_smbus_init( &g_i2c_inst );
+        
+        // Enable both I2C_SMBALERT_IRQ & I2C_SMBSUS_IRQ interrupts
+        I2C_enable_smbus_irq( &g_i2c_inst,
+                              (uint8_t)(I2C_SMBALERT_IRQ | I2C_SMBSUS_IRQ) );
+   }
+   @endcode
+ */
+void I2C_enable_smbus_irq
+(
+    i2c_instance_t * this_i2c,
+    uint8_t  irq_type
+);
+
+/*-------------------------------------------------------------------------*//**
+  The I2C_disable_smbus_irq() function is used to disable the CoreI2C channel’s
+  SMBSUS and SMBALERT SMBus interrupts.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+
+  @param irq_type
+    The irq_type specifies the SMBUS interrupt(s) which will be disabled.
+    The two possible interrupts are:
+      I2C_SMBALERT_IRQ
+      I2C_SMBSUS_IRQ
+    To disable both ints in one call, use I2C_SMBALERT_IRQ | I2C_SMBSUS_IRQ.
+
+  @return
+    none.
+      
+  Example:
+  @code
+    #define COREI2C_BASE_ADDR  0xC0000000u
+    #define SLAVE_SER_ADDR     0x10u
+
+    i2c_instance_t g_i2c_inst;
+
+    void main( void )
+    {
+        I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
+                  I2C_PCLK_DIV_256 );
+        
+        // Initialize SMBus feature
+        I2C_smbus_init( &g_i2c_inst );
+        
+        // Enable both SMBALERT & SMBSUS interrupts
+        I2C_enable_smbus_irq( &g_i2c_inst,
+                              (uint8_t)(I2C_SMBALERT_IRQ | I2C_SMBSUS_IRQ));
+        
+        ...        
+
+        // Disable the SMBALERT interrupt
+        I2C_disable_smbus_irq( &g_i2c_inst, I2C_SMBALERT_IRQ );
+    }
+  @endcode
+ */
+void I2C_disable_smbus_irq
+(
+    i2c_instance_t * this_i2c,
+    uint8_t  irq_type
+);
+
+/*-------------------------------------------------------------------------*//**
+  The function I2C_suspend_smbus_slave() forces any SMBUS slave devices
+  connected to a CoreI2C channel into power down or suspend mode by asserting
+  the channel's SMBSUS signal. The CoreI2C channel is the SMBus master in this
+  case.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+
+  @return
+    none.
+    
+  Example:
+  @code
+    #define COREI2C_BASE_ADDR  0xC0000000u
+    #define SLAVE_SER_ADDR     0x10u
+
+    i2c_instance_t g_i2c_inst;
+    
+    void main( void )
+    {
+        I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR, 
+                  I2C_PCLK_DIV_256 );
+
+        // Initialize SMBus feature
+        I2C_smbus_init( &g_i2c_inst );
+
+        // suspend SMBus slaves
+        I2C_suspend_smbus_slave( &g_i2c_inst );
+
+        ...
+
+        // Re-enable SMBus slaves
+        I2C_resume_smbus_slave( &g_i2c_inst );
+    }
+  @endcode
+ */
+void I2C_suspend_smbus_slave
+(
+    i2c_instance_t * this_i2c
+);
+
+/*-------------------------------------------------------------------------*//**
+  The function I2C_resume_smbus_slave() de-asserts the CoreI2C channel's SMBSUS
+  signal to take any connected slave devices out of suspend mode. The CoreI2C
+  channel is the SMBus master in this case.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+
+  @return
+    none.
+    
+  Example:
+  @code
+    #define COREI2C_BASE_ADDR  0xC0000000u
+    #define SLAVE_SER_ADDR     0x10u
+
+    i2c_instance_t g_i2c_inst;
+    
+    void main( void )
+    {
+        I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR, 
+                  I2C_PCLK_DIV_256 );
+
+        // Initialize SMBus feature
+        I2C_smbus_init( &g_i2c_inst );
+
+        // suspend SMBus slaves
+        I2C_suspend_smbus_slave( &g_i2c_inst );
+
+        ...
+
+        // Re-enable SMBus slaves
+        I2C_resume_smbus_slave( &g_i2c_inst );
+    }
+  @endcode
+ */
+void I2C_resume_smbus_slave
+(
+    i2c_instance_t * this_i2c
+);
+
+/*-------------------------------------------------------------------------*//**
+  The I2C_reset_smbus() function resets the CoreI2C channel's SMBus connection
+  by forcing SCLK low for 35mS. The reset is automatically cleared after 35ms
+  have elapsed. The CoreI2C channel is the SMBus master in this case.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+
+  @return
+    none.
+
+  Example:
+  @code
+    #define COREI2C_BASE_ADDR  0xC0000000u
+    #define SLAVE_SER_ADDR     0x10u
+
+    i2c_instance_t g_i2c_inst;
+    
+    void main( void )
+    {
+        I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR, 
+                  I2C_PCLK_DIV_256 );
+
+        // Initialize SMBus feature
+        I2C_smbus_init( &g_i2c_inst );
+
+        // Make sure the SMBus channel is in a known state by resetting it
+        I2C_reset_smbus( &g_i2c_inst ); 
+    }
+  @endcode
+ */
+void I2C_reset_smbus
+(
+    i2c_instance_t * this_i2c
+);
+
+/*-------------------------------------------------------------------------*//**
+  The I2C_set_smbus_alert() function is used to force master communication with
+  an I2C slave device by asserting the CoreI2C channel’s SMBALERT signal. The
+  CoreI2C channel is the SMBus slave in this case.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+
+  @return
+    none.
+
+  Example:
+  @code
+    #define COREI2C_BASE_ADDR  0xC0000000u
+    #define SLAVE_SER_ADDR     0x10u
+
+    i2c_instance_t g_i2c_inst;
+    
+    void main( void )
+    {
+        I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR, 
+                  I2C_PCLK_DIV_256 );
+
+        // Initialize SMBus feature
+        I2C_smbus_init( &g_i2c_inst );
+
+        // Get the SMBus masters attention
+        I2C_set_smbus_alert( &g_i2c_inst );
+
+        ...
+
+        // Once we are happy, drop the alert
+        I2C_clear_smbus_alert( &g_i2c_inst );
+    }
+  @endcode
+ */
+void I2C_set_smbus_alert
+(
+    i2c_instance_t * this_i2c
+);
+
+/*-------------------------------------------------------------------------*//**
+  The I2C_clear_smbus_alert() function is used de-assert the CoreI2C channel’s 
+  SMBALERT signal once a slave device has had a response from the master. The
+  CoreI2C channel is the SMBus slave in this case.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+
+  @return
+    none.
+    
+  Example:
+  @code
+    #define COREI2C_BASE_ADDR  0xC0000000u
+    #define SLAVE_SER_ADDR     0x10u
+
+    i2c_instance_t g_i2c_inst;
+    
+    void main( void )
+    {
+        I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR, 
+                  I2C_PCLK_DIV_256 );
+
+        // Initialize SMBus feature
+        I2C_smbus_init( &g_i2c_inst );
+
+        // Get the SMBus masters attention
+        I2C_set_smbus_alert( &g_i2c_inst );
+
+        ...
+
+        // Once we are happy, drop the alert
+        I2C_clear_smbus_alert( &g_i2c_inst );
+    }
+  @endcode
+ */
+void I2C_clear_smbus_alert
+(
+    i2c_instance_t * this_i2c
+);
+
+/*-------------------------------------------------------------------------*//**
+  The I2C_get_irq_status function returns information on which interrupts are
+  currently pending in a CoreI2C channel.
+  The interrupts supported by CoreI2C are:
+    * SMBUSALERT
+    * SMBSUS
+    * INTR
+  The macros I2C_NO_IRQ, I2C_SMBALERT_IRQ, I2C_SMBSUS_IRQ and I2C_INTR_IRQ are
+  provided for use with this function.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+
+  @return
+    This function returns the status of the CoreI2C channel’s interrupts as a 
+    single byte bitmap where a bit is set to indicate a pending interrupt.
+    The following are the bit positions associated with each interrupt type:
+        Bit 0 - SMBUS_ALERT_IRQ
+        Bit 1 - SMBSUS_IRQ
+        Bit 2 - INTR_IRQ
+    It returns 0, if there are no pending interrupts.
+
+  Example
+  @code
+   #define COREI2C_BASE_ADDR  0xC0000000u
+   #define SLAVE_SER_ADDR     0x10u
+
+   i2c_instance_t g_i2c_inst;
+   
+   void main( void )
+   {
+        uint8_t irq_to_enable = I2C_SMBALERT_IRQ | I2C_SMBSUS_IRQ;
+        uint8_t pending_irq = 0u;
+        
+        I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
+                  I2C_PCLK_DIV_256 );
+
+        // Initialize SMBus feature
+        I2C_smbus_init( &g_i2c_inst );
+
+        // Enable both I2C_SMBALERT_IRQ & I2C_SMBSUS_IRQ irq
+        I2C_enable_smbus_irq( &g_i2c_inst, irq_to_enable );
+
+        // Get I2C IRQ type
+        pending_irq = I2C_get_irq_status( &g_i2c_inst );
+
+        // Let's assume, in system, INTR and SMBALERT IRQ is pending.
+        // So pending_irq will return status of both the IRQs
+
+        if( pending_irq & I2C_SMBALERT_IRQ )
+        {
+           // if true, it means SMBALERT_IRQ is there in pending IRQ list
+        }
+        if( pending_irq & I2C_INTR_IRQ )
+        {
+           // if true, it means I2C_INTR_IRQ is there in pending IRQ list
+        }
+   }
+  @endcode
+ */
+uint8_t I2C_get_irq_status
+(
+    i2c_instance_t * this_i2c
+);
+
+/*-------------------------------------------------------------------------*//**
+  The I2C_set_user_data() function is used to allow the association of a block
+  of application specific data with a CoreI2C channel. The composition of the 
+  data block is an application matter and the driver simply provides the means
+  for the application to set and retrieve the pointer. This may for example be
+  used to provide additional channel specific information to the slave write 
+  handler.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+
+  @param p_user_data:
+    The p_user_data parameter is a pointer to the user specific data block for
+    this channel. It is defined as void * as the driver does not know the actual
+    type of data being pointed to and simply stores the pointer for later
+    retrieval by the application.
+
+  @return
+    none.
+    
+  Example
+  @code
+    #define COREI2C_BASE_ADDR  0xC0000000u
+    #define SLAVE_SER_ADDR     0x10u
+
+    i2c_instance_t g_i2c_inst;
+    app_data_t channel_xdata;
+  
+    void main( void )
+    {
+        app_data_t *p_xdata;
+
+        I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR, 
+                  I2C_PCLK_DIV_256 );
+
+        // Store location of user data in instance structure
+        I2C_set_user_data( &g_i2c_inst, (void *)&channel_xdata );
+
+        ...
+
+        // Retrieve location of user data and do some work on it
+        p_xdata = (app_data_t *)I2C_get_user_data( &g_i2c_inst );
+        if( NULL != p_xdata )
+        {
+            p_xdata->foo = 123;
+        }
+    }
+  @endcode
+ */
+void I2C_set_user_data
+(
+    i2c_instance_t * this_i2c,
+    void * p_user_data
+);
+
+/*-------------------------------------------------------------------------*//**
+  The I2C_get_user_data() function is used to allow the retrieval of the address
+  of a block of application specific data associated with a CoreI2C channel.
+  The composition of the data block is an application matter and the driver 
+  simply provides the means for the application to set and retrieve the pointer.
+  This may for example be used to provide additional channel specific
+  information to the slave write handler.
+  ------------------------------------------------------------------------------
+  @param this_i2c:
+    The this_i2c parameter is a pointer to the i2c_instance_t data structure
+    holding all data related to a specific CoreI2C channel. For example, if only
+    one channel is initialized, this data structure holds the information of 
+    channel 0 of the instantiated CoreI2C hardware.
+
+  @return
+    This function returns a pointer to the user specific data block for this 
+    channel. It is defined as void * as the driver does not know the actual type
+    of data being pointed. If no user data has been registered for this channel
+    a NULL pointer is returned.
+    
+  Example
+  @code
+    #define COREI2C_BASE_ADDR  0xC0000000u
+    #define SLAVE_SER_ADDR     0x10u
+
+    i2c_instance_t g_i2c_inst;
+    app_data_t channel_xdata;
+  
+    void main( void )
+    {
+        app_data_t *p_xdata;
+
+        I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
+                  I2C_PCLK_DIV_256 );
+
+        // Store location of user data in instance structure
+        I2C_set_user_data( &g_i2c_inst, (void *)&channel_xdata );
+
+        ...
+        
+        // Retrieve location of user data and do some work on it
+        p_xdata = (app_data_t *)I2C_get_user_data( &g_i2c_inst );
+        if( NULL != p_xdata )
+        {
+            p_xdata->foo = 123;
+        }
+    }
+  @endcode
+ */
+void * I2C_get_user_data
+(
+    i2c_instance_t * this_i2c
+);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreI2C/core_smbus_regs.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreI2C/core_smbus_regs.h
new file mode 100644
index 0000000..67da7a5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreI2C/core_smbus_regs.h
@@ -0,0 +1,190 @@
+/*******************************************************************************
+ * (c) Copyright 2009-2015 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * SVN $Revision: 7984 $
+ * SVN $Date: 2015-10-12 12:07:40 +0530 (Mon, 12 Oct 2015) $
+ */
+
+#ifndef __CORE_SMBUS_REGISTERS
+#define __CORE_SMBUS_REGISTERS    1
+
+/*------------------------------------------------------------------------------
+ * CONTROL register details
+ */
+#define CONTROL_REG_OFFSET    0x00u
+
+/*
+ * CR0 bits.
+ */
+#define CR0_OFFSET   0x00u
+#define CR0_MASK     0x01u
+#define CR0_SHIFT    0u
+
+/*
+ * CR1 bits.
+ */
+#define CR1_OFFSET   0x00u
+#define CR1_MASK     0x02u
+#define CR1_SHIFT    1u
+
+/*
+ * AA bits.
+ */
+#define AA_OFFSET   0x00u
+#define AA_MASK     0x04u
+#define AA_SHIFT    2u
+
+/*
+ * SI bits.
+ */
+#define SI_OFFSET   0x00u
+#define SI_MASK     0x08u
+#define SI_SHIFT    3u
+
+/*
+ * STO bits.
+ */
+#define STO_OFFSET   0x00u
+#define STO_MASK     0x10u
+#define STO_SHIFT    4u
+
+/*
+ * STA bits.
+ */
+#define STA_OFFSET   0x00u
+#define STA_MASK     0x20u
+#define STA_SHIFT    5u
+
+/*
+ * ENS1 bits.
+ */
+#define ENS1_OFFSET   0x00u
+#define ENS1_MASK     0x40u
+#define ENS1_SHIFT    6u
+
+/*
+ * CR2 bits.
+ */
+#define CR2_OFFSET   0x00u
+#define CR2_MASK     0x80u
+#define CR2_SHIFT    7u
+
+/*------------------------------------------------------------------------------
+ * STATUS register details
+ */
+#define STATUS_REG_OFFSET    0x04u
+
+/*------------------------------------------------------------------------------
+ * DATA register details
+ */
+#define DATA_REG_OFFSET    0x08u
+
+/*
+ * TARGET_ADDR bits.
+ */
+#define TARGET_ADDR_OFFSET    0x08u
+#define TARGET_ADDR_MASK      0xFEu
+#define TARGET_ADDR_SHIFT     1u
+ 
+/*
+ * DIR bit.
+ */
+#define DIR_OFFSET   0x08u
+#define DIR_MASK     0x01u
+#define DIR_SHIFT    0u
+
+
+/*------------------------------------------------------------------------------
+ * ADDRESS register details
+ */
+#define ADDRESS_REG_OFFSET    0x0Cu
+
+/*
+ * GC bits.
+ */
+#define GC_OFFSET   0x0Cu
+#define GC_MASK     0x01u
+#define GC_SHIFT    0u
+
+/*
+ * ADR bits.
+ */
+#define OWN_SLAVE_ADDR_OFFSET   0x0Cu
+#define OWN_SLAVE_ADDR_MASK     0xFEu
+#define OWN_SLAVE_ADDR_SHIFT    1u
+
+/*------------------------------------------------------------------------------
+ * SMBUS register details
+ */
+#define SMBUS_REG_OFFSET    0x10u
+
+/*
+ * SMBALERT_IE bits.
+ */
+#define SMBALERT_IE_OFFSET   0x10u
+#define SMBALERT_IE_MASK     0x01u
+#define SMBALERT_IE_SHIFT    0u
+
+/*
+ * SMBSUS_IE bits.
+ */
+#define SMBSUS_IE_OFFSET   0x10u
+#define SMBSUS_IE_MASK     0x02u
+#define SMBSUS_IE_SHIFT    1u
+
+/*
+ * SMB_IPMI_EN bits.
+ */
+#define SMB_IPMI_EN_OFFSET   0x10u
+#define SMB_IPMI_EN_MASK     0x04u
+#define SMB_IPMI_EN_SHIFT    2u
+
+/*
+ * SMBALERT_NI_STATUS bits.
+ */
+#define SMBALERT_NI_STATUS_OFFSET   0x10u
+#define SMBALERT_NI_STATUS_MASK     0x08u
+#define SMBALERT_NI_STATUS_SHIFT    3u
+
+/*
+ * SMBALERT_NO_CONTROL bits.
+ */
+#define SMBALERT_NO_CONTROL_OFFSET   0x10u
+#define SMBALERT_NO_CONTROL_MASK     0x10u
+#define SMBALERT_NO_CONTROL_SHIFT    4u
+
+/*
+ * SMBSUS_NI_STATUS bits.
+ */
+#define SMBSUS_NI_STATUS_OFFSET   0x10u
+#define SMBSUS_NI_STATUS_MASK     0x20u
+#define SMBSUS_NI_STATUS_SHIFT    5u
+
+/*
+ * SMBSUS_NO_CONTROL bits.
+ */
+#define SMBSUS_NO_CONTROL_OFFSET   0x10u
+#define SMBSUS_NO_CONTROL_MASK     0x40u
+#define SMBSUS_NO_CONTROL_SHIFT    6u
+
+/*
+ * SMBUS_MST_RESET bits.
+ */
+#define SMBUS_MST_RESET_OFFSET   0x10u
+#define SMBUS_MST_RESET_MASK     0x80u
+#define SMBUS_MST_RESET_SHIFT    7u
+
+/*------------------------------------------------------------------------------
+ * SLAVE ADDRESS 1 register details
+ */
+
+#define ADDRESS1_REG_OFFSET    0x1Cu
+
+/*
+ * SLAVE1_EN bit of Slave Address 1 .
+ */
+#define SLAVE1_EN_OFFSET      0x1Cu
+#define SLAVE1_EN_MASK        0x01u
+#define SLAVE1_EN_SHIFT          0u
+
+#endif    /* __CORE_SMBUS_REGISTERS */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreI2C/i2c_interrupt.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreI2C/i2c_interrupt.c
new file mode 100644
index 0000000..f918b8c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreI2C/i2c_interrupt.c
@@ -0,0 +1,35 @@
+/*******************************************************************************
+ * (c) Copyright 2009-2015 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * CoreI2C driver interrupt control.
+ * 
+ * SVN $Revision: 7984 $
+ * SVN $Date: 2015-10-12 12:07:40 +0530 (Mon, 12 Oct 2015) $
+ */
+#include "hal.h"
+#include "hal_assert.h"
+#include "core_i2c.h"
+#include "riscv_hal.h"
+
+
+#define I2C_IRQn					    External_29_IRQn
+
+/*------------------------------------------------------------------------------
+ * This function must be modified to enable interrupts generated from the
+ * CoreI2C instance identified as parameter.
+ */
+void I2C_enable_irq( i2c_instance_t * this_i2c )
+{
+	PLIC_EnableIRQ(I2C_IRQn);
+//    HAL_ASSERT(0)
+}
+
+/*------------------------------------------------------------------------------
+ * This function must be modified to disable interrupts generated from the
+ * CoreI2C instance identified as parameter.
+ */
+void I2C_disable_irq( i2c_instance_t * this_i2c )
+{
+	PLIC_DisableIRQ(I2C_IRQn);
+//    HAL_ASSERT(0)
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreTimer/core_timer.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreTimer/core_timer.c
new file mode 100644
index 0000000..3f6720b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreTimer/core_timer.c
@@ -0,0 +1,158 @@
+/*******************************************************************************
+ * (c) Copyright 2007-2015 Microsemi SoC Products Group. All rights reserved.
+ * 
+ * CoreTimer driver implementation.
+ * 
+ * SVN $Revision: 7967 $
+ * SVN $Date: 2015-10-09 18:48:26 +0530 (Fri, 09 Oct 2015) $
+ */
+
+#include "core_timer.h"
+#include "coretimer_regs.h"
+#include "hal.h"
+#include "hal_assert.h"
+
+#ifndef NDEBUG
+static timer_instance_t* NULL_timer_instance;
+#endif
+
+/***************************************************************************//**
+ * TMR_init()
+ * See "core_timer.h" for details of how to use this function.
+ */
+void 
+TMR_init
+(
+	timer_instance_t * this_timer,
+	addr_t address,
+	uint8_t mode,
+	uint32_t prescale,
+	uint32_t load_value
+)
+{
+	HAL_ASSERT( this_timer != NULL_timer_instance )
+	HAL_ASSERT( prescale <= PRESCALER_DIV_1024 )
+	HAL_ASSERT( load_value != 0 )
+    
+    this_timer->base_address = address;
+
+    /* Disable interrupts. */
+    HAL_set_32bit_reg_field( address, InterruptEnable,0 );
+
+    /* Disable timer. */
+    HAL_set_32bit_reg_field( address, TimerEnable, 0 );
+
+    /* Clear pending interrupt. */
+    HAL_set_32bit_reg( address, TimerIntClr, 1 );
+
+    /* Configure prescaler and load value. */	
+    HAL_set_32bit_reg( address, TimerPrescale, prescale );
+    HAL_set_32bit_reg( address, TimerLoad, load_value );
+
+    /* Set the interrupt mode. */
+    if ( mode == TMR_CONTINUOUS_MODE )
+    {
+        HAL_set_32bit_reg_field( address, TimerMode, 0 );
+    }
+    else
+    {
+        /* TMR_ONE_SHOT_MODE */
+        HAL_set_32bit_reg_field( address, TimerMode, 1 );
+    }
+}
+
+/***************************************************************************//**
+ * TMR_start()
+ * See "core_timer.h" for details of how to use this function.
+ */
+void
+TMR_start
+(
+    timer_instance_t * this_timer
+)
+{
+	HAL_ASSERT( this_timer != NULL_timer_instance )
+    
+    HAL_set_32bit_reg_field( this_timer->base_address, TimerEnable, 1 );
+}
+
+/***************************************************************************//**
+ * TMR_stop()
+ * See "core_timer.h" for details of how to use this function.
+ */
+void
+TMR_stop
+(
+    timer_instance_t * this_timer
+)
+{
+	HAL_ASSERT( this_timer != NULL_timer_instance )
+    
+    HAL_set_32bit_reg_field( this_timer->base_address, TimerEnable, 0 );
+}
+
+
+/***************************************************************************//**
+ * TMR_enable_int()
+ * See "core_timer.h" for details of how to use this function.
+ */
+void
+TMR_enable_int
+(
+    timer_instance_t * this_timer
+)
+{
+	HAL_ASSERT( this_timer != NULL_timer_instance )
+    
+    HAL_set_32bit_reg_field( this_timer->base_address, InterruptEnable, 1 );
+}
+
+/***************************************************************************//**
+ * TMR_clear_int()
+ * See "core_timer.h" for details of how to use this function.
+ */
+void
+TMR_clear_int
+(
+    timer_instance_t * this_timer
+)
+{
+	HAL_ASSERT( this_timer != NULL_timer_instance )
+    
+    HAL_set_32bit_reg( this_timer->base_address, TimerIntClr, 0x01 );
+}
+
+/***************************************************************************//**
+ * TMR_current_value()
+ * See "core_timer.h" for details of how to use this function.
+ */
+uint32_t
+TMR_current_value
+(
+    timer_instance_t * this_timer
+)
+{
+	uint32_t value = 0;
+	HAL_ASSERT( this_timer != NULL_timer_instance )
+    
+    value = HAL_get_32bit_reg( this_timer->base_address, TimerValue );
+    
+	return value;
+}
+
+/***************************************************************************//**
+ * TMR_reload()
+ * See "core_timer.h" for details of how to use this function.
+ */
+void TMR_reload
+(
+	timer_instance_t * this_timer,
+	uint32_t load_value
+)
+{
+	HAL_ASSERT( this_timer != NULL_timer_instance )
+	HAL_ASSERT( load_value != 0 )
+	
+	HAL_set_32bit_reg(this_timer->base_address, TimerLoad, load_value );
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreTimer/core_timer.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreTimer/core_timer.h
new file mode 100644
index 0000000..04b7a6e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreTimer/core_timer.h
@@ -0,0 +1,206 @@
+/*******************************************************************************
+ * (c) Copyright 2007-2015 Microsemi SoC Products Group. All rights reserved.
+ * 
+ * CoreTimer public API.
+ * 
+ * SVN $Revision: 7967 $
+ * SVN $Date: 2015-10-09 18:48:26 +0530 (Fri, 09 Oct 2015) $
+ */
+#ifndef CORE_TIMER_H_
+#define CORE_TIMER_H_
+
+#include "cpu_types.h"
+
+/***************************************************************************//**
+ * The following definitions are used to select the CoreTimer driver operating
+ * mode. They allow selecting continuous or one-shot mode.
+ * 1. Continuous Mode
+ * In continuous mode the timer's counter is decremented from the load value 
+ * until it reaches zero. The timer counter is automatically reloaded, with the
+ * load value, upon reaching zero. An interrupt is generated every time the
+ * counter reaches zero if interrupt is enabled.
+ * This mode is typically used to generate an interrupt at constant time
+ * intervals.
+ * 2. One-shot mode: 
+ * In one-shot mode, the counter decrements from the load value and until it
+ * reaches zero. An interrupt can be generated, if enabled, when the counter
+ * reaches zero. The timer's counter must be reloaded to begin counting down
+ * again.
+ */
+#define TMR_CONTINUOUS_MODE		0
+#define TMR_ONE_SHOT_MODE		1
+
+/***************************************************************************//**
+ * The following definitions are used to configure the CoreTimer prescaler.
+ * The prescaler is used to divide down the clock used to decrement the
+ * CoreTimer counter. It can be configure to divide the clock by 2, 4, 8,
+ * 16, 32, 64, 128, 256, 512, or 1024.
+ */
+#define PRESCALER_DIV_2			0
+#define PRESCALER_DIV_4			1
+#define PRESCALER_DIV_8			2
+#define PRESCALER_DIV_16		3
+#define PRESCALER_DIV_32		4
+#define PRESCALER_DIV_64		5
+#define PRESCALER_DIV_128		6
+#define PRESCALER_DIV_256		7
+#define PRESCALER_DIV_512		8
+#define PRESCALER_DIV_1024		9
+
+/***************************************************************************//**
+ * There should be one instance of this structure for each instance of CoreTimer
+ * in your system. The function TMR_init() initializes this structure. It is
+ * used to identify the various CoreTimer hardware instances in your system.
+ * An initialized timer instance structure should be passed as first parameter to
+ * CoreTimer driver functions to identify which CoreTimer instance should perform
+ * the requested operation.
+ * Software using this driver should only need to create one single instance of 
+ * this data structure for each hardware timer instance in the system.
+ */
+typedef struct __timer_instance_t
+{
+	addr_t base_address;
+} timer_instance_t;
+
+/***************************************************************************//**
+ * The function TMR_init() initializes the data structures and sets relevant
+ * CoreTimer registers. This function will prepare the Timer for use in a given
+ * hardware/software configuration. It should be called before any other Timer
+ * API functions.
+ * The timer will not start counting down immediately after this function is
+ * called. It is necessary to call TMR_start() to start the timer decrementing.
+ * The CoreTimer interrupt is disabled as part of this function.
+ *
+ * @param this_timer    Pointer to a timer_instance_t structure holding all 
+ *                      relevant data associated with the target timer hardware
+ * 						instance. This pointer will be used to identify the
+ * 						target CoreTimer hardware instance in subsequent calls
+ * 						to the CoreTimer functions.
+ * @param address       Base address in the processor's memory map of the 
+ *                      registers of the CoreTimer instance being initialized.
+ * @param mode          This parameter is used to select the operating mode of
+ * 						the timer driver. This can be either TMR_CONTINUOUS_MODE
+ * 						or TMR_ONE_SHOT_MODE.
+ * @param prescale    	This parameter is used to select the prescaler divider
+ * 						used to divide down the clock used to decrement the
+ * 						timer’s counter. This can be set using one of the 
+ * 						PRESCALER_DIV_ definitions, where  is the
+ * 						divider’s value.  
+ * @param load_value	This parameter is used to set the timer’s load value
+ * 						from which the CoreTimer counter will decrement.
+ * 						In Continuous mode, this value will be used to reload 
+ * 						the timer’s counter whenever it reaches zero.
+ */
+void
+TMR_init
+(
+	timer_instance_t * this_timer,
+	addr_t address,
+	uint8_t mode,
+	uint32_t prescale,
+	uint32_t load_value
+);
+
+/***************************************************************************//**
+ * The function TMR_start() enables the timer to start counting down.
+ * This function only needs to be called once after the timer has been
+ * initialized through a call to TMR_init(). It does not need to be called after
+ * each call to TMR_reload() when the timer is used in one-shot mode.
+ *
+ * @param this_timer    Pointer to a timer_instance_t structure holding all 
+ *                      relevant data associated with the target timer hardware
+ * 						instance. This pointer is used to identify the target
+ * 						CoreTimer hardware instance.
+ */
+void
+TMR_start
+(
+    timer_instance_t * this_timer
+);
+
+/***************************************************************************//**
+ * The function TMR_stop() stops the timer counting down. It can be used to 
+ * stop interrupts from being generated when continuous mode is used and
+ * interrupts must be paused from being generated.
+ *
+ * @param this_timer    Pointer to a timer_instance_t structure holding all 
+ *                      relevant data associated with the target timer hardware
+ * 						instance. This pointer is used to identify the target
+ * 						CoreTimer hardware instance.
+ */
+void
+TMR_stop
+(
+    timer_instance_t * this_timer
+);
+
+/***************************************************************************//**
+ * The function TMR_enable_int() enables the timer interrupt. A call to this
+ * function will allow the interrupt signal coming out of CoreTimer to be
+ * asserted. 
+ *
+ * @param this_timer    Pointer to a timer_instance_t structure holding all 
+ *                      relevant data associated with the target timer hardware
+ * 						instance. This pointer is used to identify the target
+ * 						CoreTimer hardware instance.
+ */
+void
+TMR_enable_int
+(
+    timer_instance_t * this_timer
+);
+
+/***************************************************************************//**
+ * The function TMR_clear_int() clears the timer interrupt. This function should
+ * be called within the interrupt handler servicing interrupts from the timer.
+ * Failure to clear the timer interrupt will result in the interrupt signal
+ * generating from CoreTimer to remain asserted. This assertion may cause the
+ * interrupt service routine to be continuously called, causing the system to
+ * lock up.
+ *
+ * @param this_timer    Pointer to a timer_instance_t structure holding all 
+ *                      relevant data associated with the target timer hardware
+ * 						instance. This pointer is used to identify the target
+ * 						CoreTimer hardware instance.
+ */
+void
+TMR_clear_int
+(
+    timer_instance_t * this_timer
+);
+
+/***************************************************************************//**
+ * The TMR_current_value() function returns the current value of the counter.
+ *
+ * @param this_timer    Pointer to a timer_instance_t structure holding all 
+ *                      relevant data associated with the target timer hardware
+ * 						instance. This pointer is used to identify the target
+ * 						CoreTimer hardware instance.
+ *
+ * @return              Returns the current value of the timer counter value.
+ */
+uint32_t
+TMR_current_value
+(
+    timer_instance_t * this_timer
+);
+
+/***************************************************************************//**
+ * The TMR_reload() function is used in one-shot mode. It reloads the timer
+ * counter with the values passed as parameter. This will result in an interrupt
+ * being generated when the timer counter reaches 0 if interrupt is enabled.
+ * 
+ * @param this_timer    Pointer to a timer_instance_t structure holding all 
+ *                      relevant data associated with the target timer hardware
+ * 						instance. This pointer is used to identify the target
+ * 						CoreTimer hardware instance.
+ * @param load_value	This parameter sets the value from which the CoreTimer
+ * 						counter will decrement. 
+ */
+void TMR_reload
+(
+	timer_instance_t * this_timer,
+	uint32_t load_value
+);
+	
+#endif /* CORE_TIMER_H_ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreTimer/coretimer_regs.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreTimer/coretimer_regs.h
new file mode 100644
index 0000000..5d7c67d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreTimer/coretimer_regs.h
@@ -0,0 +1,109 @@
+/*******************************************************************************
+ * (c) Copyright 2007-2015 Microsemi SoC Products Group. All rights reserved.
+ * 
+ * SVN $Revision: 7967 $
+ * SVN $Date: 2015-10-09 18:48:26 +0530 (Fri, 09 Oct 2015) $
+ */
+
+#ifndef __CORE_TIMER_REGISTERS
+#define __CORE_TIMER_REGISTERS	1
+
+/*------------------------------------------------------------------------------
+ * TimerLoad register details
+ */
+#define TimerLoad_REG_OFFSET	0x00
+
+/*
+ * LoadValue bits.
+ */
+#define LoadValue_OFFSET   0x00
+#define LoadValue_MASK     0xFFFFFFFF
+#define LoadValue_SHIFT    0
+
+/*------------------------------------------------------------------------------
+ * TimerValue register details
+ */
+#define TimerValue_REG_OFFSET	0x04
+
+/*
+ * CurrentValue bits.
+ */
+#define CurrentValue_OFFSET   0x04
+#define CurrentValue_MASK     0xFFFFFFFF
+#define CurrentValue_SHIFT    0
+
+/*------------------------------------------------------------------------------
+ * TimerControl register details
+ */
+#define TimerControl_REG_OFFSET	0x08
+
+/*
+ * TimerEnable bits.
+ */
+#define TimerEnable_OFFSET   0x08
+#define TimerEnable_MASK     0x00000001
+#define TimerEnable_SHIFT    0
+
+/*
+ * InterruptEnable bits.
+ */
+#define InterruptEnable_OFFSET   0x08
+#define InterruptEnable_MASK     0x00000002
+#define InterruptEnable_SHIFT    1
+
+/*
+ * TimerMode bits.
+ */
+#define TimerMode_OFFSET   0x08
+#define TimerMode_MASK     0x00000004
+#define TimerMode_SHIFT    2
+
+/*------------------------------------------------------------------------------
+ * TimerPrescale register details
+ */
+#define TimerPrescale_REG_OFFSET	0x0C
+
+/*
+ * Prescale bits.
+ */
+#define Prescale_OFFSET   0x0C
+#define Prescale_MASK     0x0000000F
+#define Prescale_SHIFT    0
+
+/*------------------------------------------------------------------------------
+ * TimerIntClr register details
+ */
+#define TimerIntClr_REG_OFFSET	0x10
+
+/*
+ * TimerIntClr bits.
+ */
+#define TimerIntClr_OFFSET   0x10
+#define TimerIntClr_MASK     0xFFFFFFFF
+#define TimerIntClr_SHIFT    0
+
+/*------------------------------------------------------------------------------
+ * TimerRIS register details
+ */
+#define TimerRIS_REG_OFFSET	0x14
+
+/*
+ * RawTimerInterrupt bits.
+ */
+#define RawTimerInterrupt_OFFSET   0x14
+#define RawTimerInterrupt_MASK     0x00000001
+#define RawTimerInterrupt_SHIFT    0
+
+/*------------------------------------------------------------------------------
+ * TimerMIS register details
+ */
+#define TimerMIS_REG_OFFSET	0x18
+
+/*
+ * TimerInterrupt bits.
+ */
+#define TimerInterrupt_OFFSET   0x18
+#define TimerInterrupt_MASK     0x00000001
+#define TimerInterrupt_SHIFT    0
+
+#endif /* __CORE_TIMER_REGISTERS */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreUARTapb/core_uart_apb.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreUARTapb/core_uart_apb.c
new file mode 100644
index 0000000..b4f40dc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreUARTapb/core_uart_apb.c
@@ -0,0 +1,296 @@
+/*******************************************************************************
+ * (c) Copyright 2007-2017 Microsemi SoC Products Group. All rights reserved.
+ * 
+ * CoreUARTapb driver implementation. See file "core_uart_apb.h" for a
+ * description of the functions implemented in this file.
+ * 
+ * SVN $Revision: 9082 $
+ * SVN $Date: 2017-04-28 11:51:36 +0530 (Fri, 28 Apr 2017) $
+ */
+#include "hal.h"
+#include "coreuartapb_regs.h"
+#include "core_uart_apb.h"
+#include "hal_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NULL_INSTANCE ( ( UART_instance_t* ) 0 )
+#define NULL_BUFFER   ( ( uint8_t* ) 0 )
+
+#define MAX_LINE_CONFIG     ( ( uint8_t )( DATA_8_BITS | ODD_PARITY ) )
+#define MAX_BAUD_VALUE      ( ( uint16_t )( 0x1FFF ) )
+#define STATUS_ERROR_MASK   ( ( uint8_t )( STATUS_PARITYERR_MASK | \
+                                           STATUS_OVERFLOW_MASK  | \
+                                           STATUS_FRAMERR_MASK ) )
+#define BAUDVALUE_LSB ( (uint16_t) (0x00FF) )
+#define BAUDVALUE_MSB ( (uint16_t) (0xFF00) )
+#define BAUDVALUE_SHIFT ( (uint8_t) (5) )
+
+#define STATUS_ERROR_OFFSET STATUS_PARITYERR_SHIFT 
+
+/***************************************************************************//**
+ * UART_init()
+ * See "core_uart_apb.h" for details of how to use this function.
+ */
+void
+UART_init
+(
+    UART_instance_t * this_uart,
+    addr_t base_addr,
+    uint16_t baud_value,
+    uint8_t line_config
+)
+{
+    uint8_t rx_full;
+    
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+    HAL_ASSERT( line_config <= MAX_LINE_CONFIG )
+    HAL_ASSERT( baud_value <= MAX_BAUD_VALUE )
+
+    if( ( this_uart != NULL_INSTANCE ) &&
+        ( line_config <= MAX_LINE_CONFIG ) &&
+        ( baud_value <= MAX_BAUD_VALUE ) )
+    {
+        /*
+         * Store lower 8-bits of baud value in CTRL1.
+         */
+        HAL_set_8bit_reg( base_addr, CTRL1, (uint_fast8_t)(baud_value &
+                                                       BAUDVALUE_LSB ) );
+    
+        /*
+         * Extract higher 5-bits of baud value and store in higher 5-bits 
+         * of CTRL2, along with line configuration in lower 3 three bits.
+         */
+        HAL_set_8bit_reg( base_addr, CTRL2, (uint_fast8_t)line_config | 
+                                           (uint_fast8_t)((baud_value &
+                                   BAUDVALUE_MSB) >> BAUDVALUE_SHIFT ) );
+    
+        this_uart->base_address = base_addr;
+#ifndef NDEBUG
+        {
+            uint8_t  config;
+            uint8_t  temp;
+            uint16_t baud_val;
+            baud_val = HAL_get_8bit_reg( this_uart->base_address, CTRL1 );
+            config =  HAL_get_8bit_reg( this_uart->base_address, CTRL2 );
+            /*
+             * To resolve operator precedence between & and <<
+             */
+            temp =  ( config  &  (uint8_t)(CTRL2_BAUDVALUE_MASK ) );
+            baud_val |= (uint16_t)( (uint16_t)(temp) << BAUDVALUE_SHIFT );
+            config &= (uint8_t)(~CTRL2_BAUDVALUE_MASK);
+            HAL_ASSERT( baud_val == baud_value );
+            HAL_ASSERT( config == line_config );
+        }        
+#endif
+        
+        /*
+         * Flush the receive FIFO of data that may have been received before the
+         * driver was initialized.
+         */
+        rx_full = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+                                                    STATUS_RXFULL_MASK;
+        while ( rx_full )
+        {
+            HAL_get_8bit_reg( this_uart->base_address, RXDATA );
+            rx_full = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+                                                        STATUS_RXFULL_MASK;
+        }
+
+        /*
+         * Clear status of the UART instance.
+         */
+        this_uart->status = (uint8_t)0;
+    }
+}
+
+/***************************************************************************//**
+ * UART_send()
+ * See "core_uart_apb.h" for details of how to use this function.
+ */
+void
+UART_send
+(
+    UART_instance_t * this_uart,
+    const uint8_t * tx_buffer,
+    size_t tx_size
+)
+{
+    size_t char_idx;
+    uint8_t tx_ready;
+
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+    HAL_ASSERT( tx_buffer != NULL_BUFFER )
+    HAL_ASSERT( tx_size > 0 )
+      
+    if( (this_uart != NULL_INSTANCE) &&
+        (tx_buffer != NULL_BUFFER)   &&
+        (tx_size > (size_t)0) )
+    {
+        for ( char_idx = (size_t)0; char_idx < tx_size; char_idx++ )
+        {
+            /* Wait for UART to become ready to transmit. */
+            do {
+                tx_ready = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+                                                              STATUS_TXRDY_MASK;
+            } while ( !tx_ready );
+            /* Send next character in the buffer. */
+            HAL_set_8bit_reg( this_uart->base_address, TXDATA,
+                              (uint_fast8_t)tx_buffer[char_idx] );
+        }
+    }
+}
+
+/***************************************************************************//**
+ * UART_fill_tx_fifo()
+ * See "core_uart_apb.h" for details of how to use this function.
+ */
+size_t
+UART_fill_tx_fifo
+(
+    UART_instance_t * this_uart,
+    const uint8_t * tx_buffer,
+    size_t tx_size
+)
+{
+    uint8_t tx_ready;
+    size_t size_sent = 0u;
+    
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+    HAL_ASSERT( tx_buffer != NULL_BUFFER )
+    HAL_ASSERT( tx_size > 0 )
+      
+    /* Fill the UART's Tx FIFO until the FIFO is full or the complete input 
+     * buffer has been written. */
+    if( (this_uart != NULL_INSTANCE) &&
+        (tx_buffer != NULL_BUFFER)   &&
+        (tx_size > 0u) )
+    {
+        tx_ready = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+                                                      STATUS_TXRDY_MASK;
+        if ( tx_ready )
+        {
+            do {
+                HAL_set_8bit_reg( this_uart->base_address, TXDATA,
+                                  (uint_fast8_t)tx_buffer[size_sent] );
+                size_sent++;
+                tx_ready = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+                                                              STATUS_TXRDY_MASK;
+            } while ( (tx_ready) && ( size_sent < tx_size ) );
+        }
+    }    
+    return size_sent;
+}
+
+/***************************************************************************//**
+ * UART_get_rx()
+ * See "core_uart_apb.h" for details of how to use this function.
+ */
+size_t
+UART_get_rx
+(
+    UART_instance_t * this_uart,
+    uint8_t * rx_buffer,
+    size_t buff_size
+)
+{
+    uint8_t new_status;
+    uint8_t rx_full;
+    size_t rx_idx = 0u;
+    
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+    HAL_ASSERT( rx_buffer != NULL_BUFFER )
+    HAL_ASSERT( buff_size > 0 )
+      
+    if( (this_uart != NULL_INSTANCE) &&
+        (rx_buffer != NULL_BUFFER)   &&
+        (buff_size > 0u) )
+    {
+        rx_idx = 0u;
+        new_status = HAL_get_8bit_reg( this_uart->base_address, STATUS );
+        this_uart->status |= new_status;
+        rx_full = new_status & STATUS_RXFULL_MASK;
+        while ( ( rx_full ) && ( rx_idx < buff_size ) )
+        {
+            rx_buffer[rx_idx] = HAL_get_8bit_reg( this_uart->base_address,
+                                                  RXDATA );
+            rx_idx++;
+            new_status = HAL_get_8bit_reg( this_uart->base_address, STATUS );
+            this_uart->status |= new_status;
+            rx_full = new_status & STATUS_RXFULL_MASK;
+        }
+    }
+    return rx_idx;
+}
+
+/***************************************************************************//**
+ * UART_polled_tx_string()
+ * See "core_uart_apb.h" for details of how to use this function.
+ */
+void 
+UART_polled_tx_string
+( 
+    UART_instance_t * this_uart, 
+    const uint8_t * p_sz_string
+)
+{
+    uint32_t char_idx;
+    uint8_t tx_ready;
+
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+    HAL_ASSERT( p_sz_string != NULL_BUFFER )
+    
+    if( ( this_uart != NULL_INSTANCE ) && ( p_sz_string != NULL_BUFFER ) )
+    {
+        char_idx = 0U;
+        while( 0U != p_sz_string[char_idx] )
+        {
+            /* Wait for UART to become ready to transmit. */
+            do {
+                tx_ready = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+                                                              STATUS_TXRDY_MASK;
+            } while ( !tx_ready );
+            /* Send next character in the buffer. */
+            HAL_set_8bit_reg( this_uart->base_address, TXDATA,
+                              (uint_fast8_t)p_sz_string[char_idx] );
+            char_idx++;
+        }
+    }
+}
+
+/***************************************************************************//**
+ * UART_get_rx_status()
+ * See "core_uart_apb.h" for details of how to use this function.
+ */
+uint8_t
+UART_get_rx_status
+(
+    UART_instance_t * this_uart
+)
+{
+    uint8_t status = UART_APB_INVALID_PARAM;
+
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+    /*
+     * Extract UART error status and place in lower bits of "status".
+     * Bit 0 - Parity error status
+     * Bit 1 - Overflow error status
+     * Bit 2 - Frame error status
+     */
+    if( this_uart != NULL_INSTANCE )
+    {
+        status = ( ( this_uart->status & STATUS_ERROR_MASK ) >> 
+                                          STATUS_ERROR_OFFSET );
+        /*
+         * Clear the sticky status for this instance.
+         */
+        this_uart->status = (uint8_t)0;
+    }
+    return status;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreUARTapb/core_uart_apb.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreUARTapb/core_uart_apb.h
new file mode 100644
index 0000000..680b68d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreUARTapb/core_uart_apb.h
@@ -0,0 +1,407 @@
+/*******************************************************************************
+ * (c) Copyright 2007-2017 Microsemi SoC Products Group. All rights reserved.
+ * 
+ * This file contains the application programming interface for the CoreUARTapb
+ * bare metal driver.
+ * 
+ * SVN $Revision: 9082 $
+ * SVN $Date: 2017-04-28 11:51:36 +0530 (Fri, 28 Apr 2017) $
+ */
+/*=========================================================================*//**
+  @mainpage CoreUARTapb Bare Metal Driver.
+
+  @section intro_sec Introduction
+  CoreUARTapb is an implementation of the Universal Asynchronous 
+  Receiver/Transmitter aimed at a minimal FPGA tile usage within an Microsemi
+  FPGA. The CoreUARTapb bare metal software driver is designed for use in 
+  systems with no operating system.
+
+  The CoreUARTapb driver provides functions for basic polled transmitting and 
+  receiving operations. It also provides functions allowing use of the 
+  CoreUARTapb in interrupt-driven mode, but leaves the management of interrupts 
+  to the calling application, as interrupt enabling and disabling cannot be 
+  controlled through the CoreUARTapb registers. The CoreUARTapb driver is 
+  provided as C source code.
+
+  @section driver_configuration Driver Configuration
+  Your application software should configure the CoreUARTapb driver, through 
+  calls to the UART_init() function for each CoreUARTapb instance in the 
+  hardware design. The configuration parameters include the CoreUARTapb 
+  hardware instance base address and other runtime parameters, such as baud 
+  rate, bit width, and parity. No CoreUARTapb hardware configuration parameters 
+  are needed by the driver, apart from the CoreUARTapb hardware instance base 
+  address. Hence, no additional configuration files are required to use the driver.
+
+  A CoreUARTapb hardware instance can be generated with fixed baud value, 
+  character size and parity configuration settings as part of the hardware flow. 
+  The baud_value and line_config parameter values passed to the UART_init() 
+  function will not have any effect if fixed values were selected for the 
+  baud value, character size and parity in the hardware configuration of 
+  CoreUARTapb. When fixed values are selected for these hardware configuration 
+  parameters, the driver cannot overwrite the fixed values in the CoreUARTapb 
+  control registers, CTRL1 and CTRL2.
+
+  @section theory_op Theory of Operation
+  The CoreUARTapb software driver is designed to allow the control of multiple 
+  instances of CoreUARTapb. Each instance of CoreUARTapb in the hardware design 
+  is associated with a single instance of the UART_instance_t structure in the 
+  software. You need to allocate memory for one unique UART_instance_t  
+  structure instance for each CoreUARTapb hardware instance. The contents of 
+  these data structures are initialized during calls to function UART_init(). 
+  A pointer to the structure is passed to subsequent driver functions in order
+  to identify the CoreUARTapb hardware instance you wish to perform the 
+  requested operation on.
+  
+  Note: Do not attempt to directly manipulate the content of UART_instance_t 
+  structures. This structure is only intended to be modified by the driver 
+  function.
+
+  The driver can be used to transmit and receive data once initialized. 
+  Transmit can be performed using the UART_send() function. This function
+  is blocking, meaning that it will only return once the data passed to 
+  the function has been sent to the CoreUARTapb hardware. Data received 
+  by the CoreUARTapb hardware can be read by the user application using 
+  the UART_get_rx() function.
+
+  The function UART_fill_tx_fifo() is also provided to be used as part of 
+  interrupt-driven transmit. This function fills the CoreUARTapb hardware 
+  transmit FIFO with the content of a data buffer passed as a parameter before 
+  returning. The control of the interrupts must be implemented outside the 
+  driver as the CoreUARTapb hardware does not provide the ability to enable 
+  or disable its interrupt sources.
+
+  The function UART_polled_tx_string() is provided to transmit a NULL 
+  terminated string in polled mode. This function is blocking, meaning that it 
+  will only return once the data passed to the function has been sent to the 
+  CoreUARTapb hardware.
+
+  The function UART_get_rx_status() returns the error status of the CoreUARTapb
+  receiver. This can be used by applications to take appropriate action in case
+  of receiver errors.
+*//*=========================================================================*/
+#ifndef __CORE_UART_APB_H
+#define __CORE_UART_APB_H 1
+
+#include "cpu_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * Data bits length defines:
+ */
+#define DATA_7_BITS     0x00u
+#define DATA_8_BITS     0x01u
+
+/***************************************************************************//**
+ * Parity defines:
+ */
+#define NO_PARITY       0x00u
+#define EVEN_PARITY     0x02u
+#define ODD_PARITY      0x06u
+
+/***************************************************************************//**
+ * Error Status definitions:
+ */
+#define UART_APB_PARITY_ERROR    0x01u
+#define UART_APB_OVERFLOW_ERROR  0x02u
+#define UART_APB_FRAMING_ERROR   0x04u
+#define UART_APB_NO_ERROR        0x00u
+#define UART_APB_INVALID_PARAM   0xFFu
+
+/***************************************************************************//**
+ * UART_instance_t
+ * 
+ * There should be one instance of this structure for each instance of CoreUARTapb
+ * in your system. This structure instance is used to identify the various UARTs
+ * in a system and should be passed as first parameter to UART functions to 
+ * identify which UART should perform the requested operation. The 'status' 
+ * element in the structure is used to provide sticky status information. 
+ */
+typedef struct
+{
+    addr_t      base_address;
+    uint8_t     status;
+} UART_instance_t;
+
+/***************************************************************************//**
+ * The function UART_init() initializes the UART with the configuration passed 
+ * as parameters. The configuration parameters are the baud_value used to 
+ * generate the baud rate and the line configuration (bit length and parity).
+ *
+ * @param this_uart   The this_uart parameter is a pointer to a UART_instance_t
+ *                    structure which holds all data regarding this instance of
+ *                    the CoreUARTapb. This pointer will be used to identify 
+ *                    the target CoreUARTapb hardware instance in subsequent 
+ *                    calls to the CoreUARTapb functions.
+ * @param base_addr   The base_address parameter is the base address in the 
+ *                    processor's memory map for the registers of the 
+ *                    CoreUARTapb instance being initialized.
+ * @param baud_value  The baud_value parameter is used to select the baud rate 
+ *                    for the UART. The baud value is calculated from the 
+ *                    frequency of the system clock in hertz and the desired 
+ *                    baud rate using the following equation: 
+ *                    
+ *                    baud_value = (clock /(baud_rate * 16)) - 1.
+ * 
+ *                    The baud_value parameter must be a value in the range 0 
+ *                    to 8191 (or 0x0000 to 0x1FFF).
+ * @param line_config This parameter is the line configuration specifying the 
+ *                    bit length and parity settings. This is a logical OR of:
+ *                      - DATA_7_BITS
+ *                    - DATA_8_BITS
+ *                    - NO_PARITY
+ *                    - EVEN_PARITY
+ *                    - ODD_PARITY
+ *                    For example, 8 bits even parity would be specified as 
+ *                    (DATA_8_BITS | EVEN_PARITY). 
+ * @return            This function does not return a value.
+ * Example:
+ * @code
+ *   #define BAUD_VALUE_57600    25
+ *   
+ *   #define COREUARTAPB0_BASE_ADDR      0xC3000000UL
+ *   
+ *   UART_instance_t g_uart;
+ *   int main()
+ *   {
+ *      UART_init(&g_uart, COREUARTAPB0_BASE_ADDR, 
+                  BAUD_VALUE_57600, (DATA_8_BITS | EVEN_PARITY));
+ *   }
+ * @endcode
+ */
+void
+UART_init
+(
+    UART_instance_t * this_uart,
+    addr_t base_addr,
+    uint16_t baud_value,
+    uint8_t line_config
+);
+
+/***************************************************************************//**
+ * The function UART_send() is used to transmit data. It transfers the contents
+ * of the transmitter data buffer, passed as a function parameter, into the 
+ * UART's hardware transmitter FIFO. It returns when the full content of the 
+ * transmitter data buffer has been transferred to the UART's transmitter FIFO. 
+ *
+ * Note: you cannot assume that the data you are sending using this function has
+ * been received at the other end by the time this function returns. The actual
+ * transmit over the serial connection will still be taking place at the time of
+ * the function return. It is safe to release or reuse the memory used as the
+ * transmit buffer once this function returns.
+ *
+ * @param this_uart     The this_uart parameter is a pointer to a 
+ *                      UART_instance_t structure which holds all data regarding 
+ *                      this instance of the CoreUARTapbUART.
+ * @param tx_buffer     The tx_buffer parameter is a pointer to a buffer 
+ *                      containing the data to be transmitted.
+ * @param tx_size       The tx_size parameter is the size, in bytes, of 
+ *                      the data to be transmitted.
+ *
+ * @return              This function does not return a value.
+ *
+ * Example:
+ * @code
+ *   uint8_t testmsg1[] = {"\n\r\n\r\n\rUART_send() test message 1"};
+ *   UART_send(&g_uart,(const uint8_t *)&testmsg1,sizeof(testmsg1));
+ * @endcode
+ */
+void
+UART_send
+(
+    UART_instance_t * this_uart,
+    const uint8_t * tx_buffer,
+    size_t tx_size
+);
+
+/***************************************************************************//**
+ * The function UART_fill_tx_fifo() fills the UART's transmitter hardware FIFO 
+ * with the data found in the transmitter buffer that is passed in as a 
+ * function parameter. The function returns either when the FIFO is full or 
+ * when the complete contents of the transmitter buffer have been copied into 
+ * the FIFO. It returns the number of bytes copied into the UART's transmitter
+ * hardware FIFO. This function is intended to be used as part of 
+ * interrupt-driven transmission.
+ *
+ * Note:    You cannot assume that the data you transmit using this function has 
+ *          been received at the other end by the time this function returns. 
+ *          The actual transmission over the serial connection will still be 
+ *          taking place at the time of the function return. 
+ *
+ * @param this_uart     The this_uart parameter is a pointer to a UART_instance_t
+ *                      structure which holds all data regarding this instance of
+ *                      the UART.
+ * @param tx_buffer     The tx_buffer parameter is a pointer to a buffer 
+ *                      containing the data to be transmitted.
+ * @param tx_size       The tx_size parameter is the size in bytes, of the data 
+ *                      to be transmitted.
+ * @return              This function returns the number of bytes copied 
+ *                      into the UART's transmitter hardware FIFO. 
+ *
+ * Example:
+ * @code
+ *   void send_using_interrupt
+ *   (
+ *       uint8_t * pbuff,
+ *       size_t tx_size
+ *   )
+ *   {
+ *       size_t size_in_fifo;
+ *       size_in_fifo = UART_fill_tx_fifo( &g_uart, pbuff, tx_size );
+ *   }
+ * @endcode
+ */
+size_t
+UART_fill_tx_fifo
+(
+    UART_instance_t * this_uart,
+    const uint8_t * tx_buffer,
+    size_t tx_size
+);
+
+/***************************************************************************//**
+ * The function UART_get_rx() reads the content of the UART's receiver hardware 
+ * FIFO and stores it in the receiver buffer that is passed in as a function 
+ * parameter. It copies either the full contents of the FIFO into the receiver 
+ * buffer, or just enough data from the FIFO to fill the receiver buffer, 
+ * dependent upon the size of the receiver buffer.  The size of the receiver 
+ * buffer is passed in as a function parameter. UART_get_rx() returns the number
+ * of bytes copied into the receiver buffer. If no data was received at the time
+ * the function is called, the function returns 0.
+ *
+ * Note:    This function reads and accumulates the receiver status of the 
+ *          CoreUARTapb instance before reading each byte from the receiver's 
+ *          data register/FIFO. This allows the driver to maintain a sticky 
+ *          record of any receiver errors that occur as the UART receives each 
+ *          data byte; receiver errors would otherwise be lost after each read 
+ *          from the receiver's data register. A call to the UART_get_rx_status()
+ *          function returns any receiver errors accumulated during the execution
+ *          of the UART_get_rx() function.
+ * Note:    When FIFO mode is disabled in the CoreUARTapb hardware configuration,
+ *          the driver accumulates a sticky record of any parity errors, framing 
+ *          errors or overflow errors. When FIFO mode is enabled, the driver 
+ *          accumulates a sticky record of overflow errors only; in this case 
+ *          interrupts must be used to handle parity errors or framing errors.
+ *
+ * @param this_uart     The this_uart parameter is a pointer to a UART_instance_t 
+ *                      structure which holds all data regarding this instance of 
+ *                      the UART.
+ * @param rx_buffer     The rx_buffer parameter is a pointer to a buffer where the 
+ *                      received data will be copied.
+ * @param buff_size     The buff_size parameter is the size of the receive buffer 
+ *                      in bytes.
+ * @return              This function returns the number of bytes copied into the 
+ *                      receive buffer.
+ *
+ * Example:
+ * @code
+ *   #define MAX_RX_DATA_SIZE    256
+ *   
+ *   uint8_t rx_data[MAX_RX_DATA_SIZE];
+ *   uint8_t rx_size = 0;
+ *           
+ *   rx_size = UART_get_rx( &g_uart, rx_data, sizeof(rx_data) );
+ * @endcode
+ */
+size_t
+UART_get_rx
+(
+    UART_instance_t * this_uart,
+    uint8_t * rx_buffer,
+    size_t buff_size
+);
+
+/***************************************************************************//**
+ * The function UART_polled_tx_string() is used to transmit a NULL ('\0') 
+ * terminated string. Internally, it polls for the transmit ready status and
+ * transfers the text starting at the address pointed to by p_sz_string into
+ * the UART's hardware transmitter FIFO. It is a blocking function and returns
+ * only when the complete string has been transferred to the UART's transmit 
+ * FIFO.
+ *
+ * Note:    You cannot assume that the data you transmit using this function 
+ *          has been received at the other end by the time this function 
+ *          returns. The actual transmission over the serial connection will
+ *          still be taking place at the time of the function return.
+ *
+ * @param this_uart     The this_uart parameter is a pointer to a 
+ *                      UART_instance_t structure which holds
+ *                      all data regarding this instance of the UART.
+ * @param p_sz_string   The p_sz_string parameter is a pointer to a buffer
+ *                      containing the NULL ('\0') terminated string to be 
+ *                      transmitted.
+ * @return              This function does not return a value.
+ *
+ * Example:
+ * @code
+ *   uint8_t testmsg1[] = {"\r\n\r\nUART_polled_tx_string() test message 1\0"};
+ *   UART_polled_tx_string(&g_uart,(const uint8_t *)&testmsg1);
+ * @endcode
+ */
+void 
+UART_polled_tx_string
+( 
+    UART_instance_t * this_uart, 
+    const uint8_t * p_sz_string
+);
+
+/***************************************************************************//**
+ * The UART_get_rx_status() function returns the receiver error status of the 
+ * CoreUARTapb instance. It reads both the current error status of the receiver
+ * and the accumulated error status from preceding calls to the UART_get_rx() 
+ * function and combines them using a bitwise OR. It returns the cumulative 
+ * parity, framing and overflow error status of the receiver, since the 
+ * previous call to UART_get_rx_status(), as an 8-bit encoded value.
+ *
+ * Note:    The UART_get_rx() function reads and accumulates the receiver status 
+ *          of the CoreUARTapb instance before reading each byte from the 
+ *          receiver's data register/FIFO. The driver maintains a sticky record 
+ *          of the cumulative error status, which persists after the 
+ *          UART_get_rx() function returns. The UART_get_rx_status() function 
+ *          clears this accumulated record of receiver errors before returning.
+ * 
+ * @param this_uart     The this_uart parameter is a pointer to a UART_instance_t
+ *                      structure which holds all data regarding this instance 
+ *                      of the UART.
+ * @return              This function returns the UART receiver error status as 
+ *                      an 8-bit encoded value. The returned value is 0 if no 
+ *                      receiver errors occurred. The driver provides a set of 
+ *                      bit mask constants which should be compared with and/or
+ *                      used to mask the returned value to determine the 
+ *                      receiver error status. 
+ *                      When the return value is compared to the following bit 
+ *                      masks, a non-zero result indicates that the 
+ *                      corresponding error occurred:
+ *                      UART_APB_PARITY_ERROR    (bit mask = 0x01)
+ *                      UART_APB_OVERFLOW_ERROR  (bit mask = 0x02)
+ *                      UART_APB_FRAMING_ERROR   (bit mask = 0x04)
+ *                      When the return value is compared to the following bit 
+ *                      mask, a non-zero result indicates that no error occurred:
+ *                      UART_APB_NO_ERROR        (0x00)
+ *
+ * Example:
+ * @code
+ *   UART_instance_t g_uart;
+ *   uint8_t rx_data[MAX_RX_DATA_SIZE];
+ *   uint8_t err_status;
+ *   err_status = UART_get_err_status(&g_uart);
+ *   
+ *   if(UART_APB_NO_ERROR == err_status )
+ *   {
+ *        rx_size = UART_get_rx( &g_uart, rx_data, MAX_RX_DATA_SIZE );
+ *   }
+ * @endcode
+ */
+uint8_t
+UART_get_rx_status
+(
+    UART_instance_t * this_uart
+);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_UART_APB_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreUARTapb/coreuartapb_regs.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreUARTapb/coreuartapb_regs.h
new file mode 100644
index 0000000..e6cc8c1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/drivers/CoreUARTapb/coreuartapb_regs.h
@@ -0,0 +1,130 @@
+/*******************************************************************************
+ * (c) Copyright 2007-2017 Microsemi SoC Products Group. All rights reserved.
+ * 
+ * SVN $Revision: 9082 $
+ * SVN $Date: 2017-04-28 11:51:36 +0530 (Fri, 28 Apr 2017) $
+ */
+
+#ifndef __CORE_UART_APB_REGISTERS
+#define __CORE_UART_APB_REGISTERS   1
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * TxData register details
+ */
+#define TXDATA_REG_OFFSET   0x0u
+
+/*
+ * TxData bits.
+ */
+#define TXDATA_OFFSET   0x0u
+#define TXDATA_MASK     0xFFu
+#define TXDATA_SHIFT    0u
+
+/*------------------------------------------------------------------------------
+ * RxData register details
+ */
+#define RXDATA_REG_OFFSET   0x4u
+
+/*
+ * RxData bits.
+ */
+#define RXDATA_OFFSET   0x4u
+#define RXDATA_MASK     0xFFu
+#define RXDATA_SHIFT    0u
+
+/*------------------------------------------------------------------------------
+ * ControReg1 register details
+ */
+#define CTRL1_REG_OFFSET        0x8u
+
+/*
+ * Baud value (Lower 8-bits)
+ */
+#define CTRL1_BAUDVALUE_OFFSET   0x8u
+#define CTRL1_BAUDVALUE_MASK     0xFFu
+#define CTRL1_BAUDVALUE_SHIFT    0u
+
+/*------------------------------------------------------------------------------
+ * ControReg2 register details
+ */
+#define CTRL2_REG_OFFSET          0xCu
+
+/*
+ * Bit length
+ */
+#define CTRL2_BIT_LENGTH_OFFSET   0xCu
+#define CTRL2_BIT_LENGTH_MASK     0x01u
+#define CTRL2_BIT_LENGTH_SHIFT    0u
+
+/*
+ * Parity enable.
+ */
+#define CTRL2_PARITY_EN_OFFSET    0xCu
+#define CTRL2_PARITY_EN_MASK      0x02u
+#define CTRL2_PARITY_EN_SHIFT     1u
+
+/*
+ * Odd/even parity selection.
+ */
+#define CTRL2_ODD_EVEN_OFFSET     0xCu
+#define CTRL2_ODD_EVEN_MASK       0x04u
+#define CTRL2_ODD_EVEN_SHIFT      2u
+
+/*
+ *  Baud value (Higher 5-bits)
+ */
+#define CTRL2_BAUDVALUE_OFFSET    0xCu
+#define CTRL2_BAUDVALUE_MASK      0xF8u
+#define CTRL2_BAUDVALUE_SHIFT     3u
+
+/*------------------------------------------------------------------------------
+ * StatusReg register details
+ */
+#define StatusReg_REG_OFFSET    0x10u
+
+#define STATUS_REG_OFFSET       0x10u
+
+/*
+ * Transmit ready.
+ */
+#define STATUS_TXRDY_OFFSET   0x10u
+#define STATUS_TXRDY_MASK     0x01u
+#define STATUS_TXRDY_SHIFT    0u
+
+/*
+ * Receive full.
+ */
+#define STATUS_RXFULL_OFFSET   0x10u
+#define STATUS_RXFULL_MASK     0x02u
+#define STATUS_RXFULL_SHIFT    1u
+
+/*
+ * Parity error.
+ */
+#define STATUS_PARITYERR_OFFSET   0x10u
+#define STATUS_PARITYERR_MASK     0x04u
+#define STATUS_PARITYERR_SHIFT    2u
+
+/*
+ * Overflow.
+ */
+#define STATUS_OVERFLOW_OFFSET   0x10u
+#define STATUS_OVERFLOW_MASK     0x08u
+#define STATUS_OVERFLOW_SHIFT    3u
+
+/*
+ * Frame Error.
+ */
+#define STATUS_FRAMERR_OFFSET   0x10u
+#define STATUS_FRAMERR_MASK     0x10u
+#define STATUS_FRAMERR_SHIFT    4u
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* __CORE_UART_APB_REGISTERS */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/hal/cpu_types.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/hal/cpu_types.h
new file mode 100644
index 0000000..1beae8c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/hal/cpu_types.h
@@ -0,0 +1,31 @@
+/*******************************************************************************
+ * (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved.
+ * 
+ * SVN $Revision: 9661 $
+ * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
+ */
+#ifndef __CPU_TYPES_H
+#define __CPU_TYPES_H   1
+
+#include 
+
+/*------------------------------------------------------------------------------
+ */
+typedef unsigned int size_t;
+
+/*------------------------------------------------------------------------------
+ * addr_t: address type.
+ * Used to specify the address of peripherals present in the processor's memory
+ * map.
+ */
+typedef unsigned int addr_t;
+
+/*------------------------------------------------------------------------------
+ * psr_t: processor state register.
+ * Used by HAL_disable_interrupts() and HAL_restore_interrupts() to store the
+ * processor's state between disabling and restoring interrupts.
+ */
+typedef unsigned int psr_t;
+
+#endif  /* __CPU_TYPES_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/hal/hal.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/hal/hal.h
new file mode 100644
index 0000000..5b82ed0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/hal/hal.h
@@ -0,0 +1,207 @@
+/***************************************************************************//**
+ * (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved.
+ * 
+ * Hardware abstraction layer functions.
+ * 
+ * SVN $Revision: 9661 $
+ * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
+ */
+#ifndef HAL_H_
+#define HAL_H_
+
+#include "cpu_types.h"
+#include "hw_reg_access.h"
+
+/***************************************************************************//**
+ * Enable all interrupts at the processor level.
+ */
+void HAL_enable_interrupts( void );
+
+/***************************************************************************//**
+ * Disable all interrupts at the processor core level.
+ * Return the interrupts enable state before disabling occured so that it can 
+ * later be restored. 
+ */
+psr_t HAL_disable_interrupts( void );
+
+/***************************************************************************//**
+ * Restore the interrupts enable state at the processor core level.
+ * This function is normally passed the value returned from a previous call to
+ * HAL_disable_interrupts(). 
+ */
+void HAL_restore_interrupts( psr_t saved_psr );
+
+/***************************************************************************//**
+ */
+#define FIELD_OFFSET(FIELD_NAME)  (FIELD_NAME##_OFFSET)
+#define FIELD_SHIFT(FIELD_NAME)   (FIELD_NAME##_SHIFT)
+#define FIELD_MASK(FIELD_NAME)    (FIELD_NAME##_MASK)
+
+/***************************************************************************//**
+ * The macro HAL_set_32bit_reg() allows writing a 32 bits wide register.
+ *
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the
+ *              peripheral containing the register.
+ * REG_NAME:    A string identifying the register to write. These strings are
+ *              specified in a header file associated with the peripheral.
+ * VALUE:       A variable of type uint32_t containing the value to write.
+ */
+#define HAL_set_32bit_reg(BASE_ADDR, REG_NAME, VALUE) \
+          (HW_set_32bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) ))
+
+/***************************************************************************//**
+ * The macro HAL_get_32bit_reg() is used to read the value  of a 32 bits wide
+ * register.
+ * 
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the
+ *              peripheral containing the register.
+ * REG_NAME:    A string identifying the register to read. These strings are
+ *              specified in a header file associated with the peripheral.
+ * RETURN:      This function-like macro returns a uint32_t value.
+ */
+#define HAL_get_32bit_reg(BASE_ADDR, REG_NAME) \
+          (HW_get_32bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)) ))
+
+/***************************************************************************//**
+ * The macro HAL_set_32bit_reg_field() is used to write a field within a
+ * 32 bits wide register. The field written can be one or more bits.
+ * 
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the
+ *              peripheral containing the register.
+ * FIELD_NAME:  A string identifying the register field to write. These strings
+ *              are specified in a header file associated with the peripheral.
+ * VALUE:       A variable of type uint32_t containing the field value to write.
+ */
+#define HAL_set_32bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \
+            (HW_set_32bit_reg_field(\
+                (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
+                FIELD_SHIFT(FIELD_NAME),\
+                FIELD_MASK(FIELD_NAME),\
+                (VALUE)))
+  
+/***************************************************************************//**
+ * The macro HAL_get_32bit_reg_field() is used to read a register field from
+ * within a 32 bit wide peripheral register. The field can be one or more bits.
+ * 
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the
+ *              peripheral containing the register.
+ * FIELD_NAME:  A string identifying the register field to write. These strings
+ *              are specified in a header file associated with the peripheral.
+ * RETURN:      This function-like macro returns a uint32_t value.
+ */
+#define HAL_get_32bit_reg_field(BASE_ADDR, FIELD_NAME) \
+            (HW_get_32bit_reg_field(\
+                (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
+                FIELD_SHIFT(FIELD_NAME),\
+                FIELD_MASK(FIELD_NAME)))
+  
+/***************************************************************************//**
+ * The macro HAL_set_16bit_reg() allows writing a 16 bits wide register.
+ *
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the
+ *              peripheral containing the register.
+ * REG_NAME:    A string identifying the register to write. These strings are
+ *              specified in a header file associated with the peripheral.
+ * VALUE:       A variable of type uint_fast16_t containing the value to write.
+ */
+#define HAL_set_16bit_reg(BASE_ADDR, REG_NAME, VALUE) \
+            (HW_set_16bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) ))
+
+/***************************************************************************//**
+ * The macro HAL_get_16bit_reg() is used to read the value  of a 16 bits wide
+ * register.
+ * 
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the
+ *              peripheral containing the register.
+ * REG_NAME:    A string identifying the register to read. These strings are
+ *              specified in a header file associated with the peripheral.
+ * RETURN:      This function-like macro returns a uint16_t value.
+ */
+#define HAL_get_16bit_reg(BASE_ADDR, REG_NAME) \
+            (HW_get_16bit_reg( (BASE_ADDR) + (REG_NAME##_REG_OFFSET) ))
+
+/***************************************************************************//**
+ * The macro HAL_set_16bit_reg_field() is used to write a field within a
+ * 16 bits wide register. The field written can be one or more bits.
+ * 
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the
+ *              peripheral containing the register.
+ * FIELD_NAME:  A string identifying the register field to write. These strings
+ *              are specified in a header file associated with the peripheral.
+ * VALUE:       A variable of type uint16_t containing the field value to write.
+ */
+#define HAL_set_16bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \
+            (HW_set_16bit_reg_field(\
+                (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
+                FIELD_SHIFT(FIELD_NAME),\
+                FIELD_MASK(FIELD_NAME),\
+                (VALUE)))  
+
+/***************************************************************************//**
+ * The macro HAL_get_16bit_reg_field() is used to read a register field from
+ * within a 8 bit wide peripheral register. The field can be one or more bits.
+ * 
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the
+ *              peripheral containing the register.
+ * FIELD_NAME:  A string identifying the register field to write. These strings
+ *              are specified in a header file associated with the peripheral.
+ * RETURN:      This function-like macro returns a uint16_t value.
+ */
+#define HAL_get_16bit_reg_field(BASE_ADDR, FIELD_NAME) \
+            (HW_get_16bit_reg_field(\
+                (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
+                FIELD_SHIFT(FIELD_NAME),\
+                FIELD_MASK(FIELD_NAME)))
+
+/***************************************************************************//**
+ * The macro HAL_set_8bit_reg() allows writing a 8 bits wide register.
+ *
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the
+ *              peripheral containing the register.
+ * REG_NAME:    A string identifying the register to write. These strings are
+ *              specified in a header file associated with the peripheral.
+ * VALUE:       A variable of type uint_fast8_t containing the value to write.
+ */
+#define HAL_set_8bit_reg(BASE_ADDR, REG_NAME, VALUE) \
+          (HW_set_8bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) ))
+
+/***************************************************************************//**
+ * The macro HAL_get_8bit_reg() is used to read the value of a 8 bits wide
+ * register.
+ * 
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the
+ *              peripheral containing the register.
+ * REG_NAME:    A string identifying the register to read. These strings are
+ *              specified in a header file associated with the peripheral.
+ * RETURN:      This function-like macro returns a uint8_t value.
+ */
+#define HAL_get_8bit_reg(BASE_ADDR, REG_NAME) \
+          (HW_get_8bit_reg( (BASE_ADDR) + (REG_NAME##_REG_OFFSET) ))
+
+/***************************************************************************//**
+ */
+#define HAL_set_8bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \
+            (HW_set_8bit_reg_field(\
+                (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
+                FIELD_SHIFT(FIELD_NAME),\
+                FIELD_MASK(FIELD_NAME),\
+                (VALUE)))
+
+/***************************************************************************//**
+ * The macro HAL_get_8bit_reg_field() is used to read a register field from
+ * within a 8 bit wide peripheral register. The field can be one or more bits.
+ * 
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the
+ *              peripheral containing the register.
+ * FIELD_NAME:  A string identifying the register field to write. These strings
+ *              are specified in a header file associated with the peripheral.
+ * RETURN:      This function-like macro returns a uint8_t value.
+ */
+#define HAL_get_8bit_reg_field(BASE_ADDR, FIELD_NAME) \
+            (HW_get_8bit_reg_field(\
+                (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
+                FIELD_SHIFT(FIELD_NAME),\
+                FIELD_MASK(FIELD_NAME)))
+  
+#endif /*HAL_H_*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/hal/hal_assert.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/hal/hal_assert.h
new file mode 100644
index 0000000..db8ab77
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/hal/hal_assert.h
@@ -0,0 +1,29 @@
+/*******************************************************************************
+ * (c) Copyright 2008-2018 Microsemi SoC Products Group. All rights reserved.
+ * 
+ * SVN $Revision: 9661 $
+ * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
+ */
+#ifndef HAL_ASSERT_HEADER
+#define HAL_ASSERT_HEADER
+
+#define NDEBUG 1
+
+#if defined(NDEBUG)
+/***************************************************************************//**
+ * HAL_ASSERT() is defined out when the NDEBUG symbol is used.
+ ******************************************************************************/
+#define HAL_ASSERT(CHECK)
+
+#else
+/***************************************************************************//**
+ * Default behaviour for HAL_ASSERT() macro:
+ *------------------------------------------------------------------------------
+  The behaviour is toolchain specific and project setting specific.
+ ******************************************************************************/
+#define HAL_ASSERT(CHECK)     ASSERT(CHECK);
+
+#endif  /* NDEBUG */
+
+#endif  /* HAL_ASSERT_HEADER */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/hal/hal_irq.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/hal/hal_irq.c
new file mode 100644
index 0000000..52f6301
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/hal/hal_irq.c
@@ -0,0 +1,36 @@
+/***************************************************************************//**
+ * (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved.
+ * 
+ * Legacy interrupt control functions for the Microsemi driver library hardware
+ * abstraction layer.
+ *
+ * SVN $Revision: 9661 $
+ * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
+ */
+#include "hal.h"
+#include "riscv_hal.h"
+
+/*------------------------------------------------------------------------------
+ * 
+ */
+void HAL_enable_interrupts(void) {
+    __enable_irq();
+}
+
+/*------------------------------------------------------------------------------
+ * 
+ */
+psr_t HAL_disable_interrupts(void) {
+    psr_t psr;
+    psr = read_csr(mstatus);
+    __disable_irq();
+    return(psr);
+}
+
+/*------------------------------------------------------------------------------
+ * 
+ */
+void HAL_restore_interrupts(psr_t saved_psr) {
+    write_csr(mstatus, saved_psr);
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/hal/hw_macros.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/hal/hw_macros.h
new file mode 100644
index 0000000..2149544
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/hal/hw_macros.h
@@ -0,0 +1,97 @@
+/*******************************************************************************
+ * (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved.
+ * 
+ *  Hardware registers access macros.
+ * 
+ *  THE MACROS DEFINED IN THIS FILE ARE DEPRECATED. DO NOT USED FOR NEW 
+ *  DEVELOPMENT.
+ *
+ * These macros are used to access peripheral's registers. They allow access to
+ * 8, 16 and 32 bit wide registers. All accesses to peripheral registers should
+ * be done through these macros in order to ease porting across different 
+ * processors/bus architectures.
+ * 
+ * Some of these macros also allow to access a specific register field.
+ * 
+ * SVN $Revision: 9661 $
+ * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
+ */
+#ifndef __HW_REGISTER_MACROS_H
+#define __HW_REGISTER_MACROS_H 1
+
+/*------------------------------------------------------------------------------
+ * 32 bits registers access:
+ */
+#define HW_get_uint32_reg(BASE_ADDR, REG_OFFSET) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
+
+#define HW_set_uint32_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
+
+#define HW_set_uint32_reg_field(BASE_ADDR, FIELD, VALUE) \
+            (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) =  \
+                ( \
+                    (uint32_t) \
+                    ( \
+                    (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
+                    (uint32_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
+                ) \
+            )
+
+#define HW_get_uint32_reg_field( BASE_ADDR, FIELD ) \
+            (( (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
+
+/*------------------------------------------------------------------------------
+ * 32 bits memory access:
+ */
+#define HW_get_uint32(BASE_ADDR) (*((uint32_t volatile *)(BASE_ADDR)))
+
+#define HW_set_uint32(BASE_ADDR, VALUE) (*((uint32_t volatile *)(BASE_ADDR)) = (VALUE))
+
+/*------------------------------------------------------------------------------
+ * 16 bits registers access:
+ */
+#define HW_get_uint16_reg(BASE_ADDR, REG_OFFSET) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
+
+#define HW_set_uint16_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
+
+#define HW_set_uint16_reg_field(BASE_ADDR, FIELD, VALUE) \
+            (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) =  \
+                ( \
+                    (uint16_t) \
+                    ( \
+                    (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
+                    (uint16_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
+                ) \
+            )
+
+#define HW_get_uint16_reg_field( BASE_ADDR, FIELD ) \
+            (( (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
+
+/*------------------------------------------------------------------------------
+ * 8 bits registers access:
+ */
+#define HW_get_uint8_reg(BASE_ADDR, REG_OFFSET) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
+
+#define HW_set_uint8_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
+ 
+#define HW_set_uint8_reg_field(BASE_ADDR, FIELD, VALUE) \
+            (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) =  \
+                ( \
+                    (uint8_t) \
+                    ( \
+                    (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
+                    (uint8_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
+                ) \
+            )
+
+#define HW_get_uint8_reg_field( BASE_ADDR, FIELD ) \
+            (( (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
+
+/*------------------------------------------------------------------------------
+ * 8 bits memory access:
+ */
+#define HW_get_uint8(BASE_ADDR) (*((uint8_t volatile *)(BASE_ADDR)))
+
+#define HW_set_uint8(BASE_ADDR, VALUE) (*((uint8_t volatile *)(BASE_ADDR)) = (VALUE))
+ 
+#endif  /* __HW_REGISTER_MACROS_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/hal/hw_reg_access.S b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/hal/hw_reg_access.S
new file mode 100644
index 0000000..68d93dd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/hal/hw_reg_access.S
@@ -0,0 +1,209 @@
+/***************************************************************************//**
+ * (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved.
+ *
+ * Hardware registers access functions.
+ * The implementation of these function is platform and toolchain specific.
+ * The functions declared here are implemented using assembler as part of the
+ * processor/toolchain specific HAL.
+ *
+ * SVN $Revision: 9661 $
+ * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
+ */
+
+.section .text
+    .globl HW_set_32bit_reg
+    .globl HW_get_32bit_reg
+    .globl HW_set_32bit_reg_field
+    .globl HW_get_32bit_reg_field
+    .globl HW_set_16bit_reg
+    .globl HW_get_16bit_reg
+    .globl HW_set_16bit_reg_field
+    .globl HW_get_16bit_reg_field
+    .globl HW_set_8bit_reg
+    .globl HW_get_8bit_reg
+    .globl HW_set_8bit_reg_field
+    .globl HW_get_8bit_reg_field
+
+
+/***************************************************************************//**
+ * HW_set_32bit_reg is used to write the content of a 32 bits wide peripheral
+ * register.
+ *
+ * a0:   addr_t reg_addr
+ * a1:   uint32_t value
+ */
+HW_set_32bit_reg:
+    sw a1, 0(a0)
+    ret
+
+/***************************************************************************//**
+ * HW_get_32bit_reg is used to read the content of a 32 bits wide peripheral
+ * register.
+ *
+ * R0:   addr_t reg_addr
+ * @return          32 bits value read from the peripheral register.
+ */
+HW_get_32bit_reg:
+    lw a0, 0(a0)
+    ret
+
+/***************************************************************************//**
+ * HW_set_32bit_reg_field is used to set the content of a field in a 32 bits
+ * wide peripheral register.
+ *
+ * a0:   addr_t reg_addr
+ * a1:   int_fast8_t shift
+ * a2:   uint32_t mask
+ * a3:   uint32_t value
+ */
+HW_set_32bit_reg_field:
+    mv t3, a3
+    sll t3, t3, a1
+    and  t3, t3, a2
+    lw t1, 0(a0)
+    mv t2, a2
+    not t2, t2
+    and t1, t1, t2
+    or t1, t1, t3
+    sw t1, 0(a0)
+    ret
+
+/***************************************************************************//**
+ * HW_get_32bit_reg_field is used to read the content of a field out of a
+ * 32 bits wide peripheral register.
+ *
+ * a0:   addr_t reg_addr
+ * a1:   int_fast8_t shift
+ * a2:   uint32_t mask
+ *
+ * @return          32 bits value containing the register field value specified
+ *                  as parameter.
+ */
+HW_get_32bit_reg_field:
+    lw a0, 0(a0)
+    and a0, a0, a2
+    srl a0, a0, a1
+    ret
+
+/***************************************************************************//**
+ * HW_set_16bit_reg is used to write the content of a 16 bits wide peripheral
+ * register.
+ *
+ * a0:   addr_t reg_addr
+ * a1:   uint_fast16_t value
+ */
+HW_set_16bit_reg:
+    sh a1, 0(a0)
+    ret
+
+/***************************************************************************//**
+ * HW_get_16bit_reg is used to read the content of a 16 bits wide peripheral
+ * register.
+ *
+ * a0:   addr_t reg_addr
+ * @return          16 bits value read from the peripheral register.
+ */
+HW_get_16bit_reg:
+    lh a0, (a0)
+    ret
+
+/***************************************************************************//**
+ * HW_set_16bit_reg_field is used to set the content of a field in a 16 bits
+ * wide peripheral register.
+ *
+ * a0:   addr_t reg_addr
+ * a1:   int_fast8_t shift
+ * a2:   uint_fast16_t mask
+ * a3:   uint_fast16_t value
+ * @param value     Value to be written in the specified field.
+ */
+HW_set_16bit_reg_field:
+    mv t3, a3
+    sll t3, t3, a1
+    and  t3, t3, a2
+    lh t1, 0(a0)
+    mv t2, a2
+    not t2, t2
+    and t1, t1, t2
+    or t1, t1, t3
+    sh t1, 0(a0)
+    ret
+
+/***************************************************************************//**
+ * HW_get_16bit_reg_field is used to read the content of a field from a
+ * 16 bits wide peripheral register.
+ *
+ * a0:   addr_t reg_addr
+ * a1:   int_fast8_t shift
+ * a2:   uint_fast16_t mask
+ *
+ * @return          16 bits value containing the register field value specified
+ *                  as parameter.
+ */
+HW_get_16bit_reg_field:
+    lh a0, 0(a0)
+    and a0, a0, a2
+    srl a0, a0, a1
+    ret
+
+/***************************************************************************//**
+ * HW_set_8bit_reg is used to write the content of a 8 bits wide peripheral
+ * register.
+ *
+ * a0:   addr_t reg_addr
+ * a1:   uint_fast8_t value
+ */
+HW_set_8bit_reg:
+    sb a1, 0(a0)
+    ret
+
+/***************************************************************************//**
+ * HW_get_8bit_reg is used to read the content of a 8 bits wide peripheral
+ * register.
+ *
+ * a0:   addr_t reg_addr
+ * @return          8 bits value read from the peripheral register.
+ */
+HW_get_8bit_reg:
+    lb a0, 0(a0)
+    ret
+
+/***************************************************************************//**
+ * HW_set_8bit_reg_field is used to set the content of a field in a 8 bits
+ * wide peripheral register.
+ *
+ * a0:   addr_t reg_addr,
+ * a1:   int_fast8_t shift
+ * a2:   uint_fast8_t mask
+ * a3:   uint_fast8_t value
+ */
+HW_set_8bit_reg_field:
+    mv t3, a3
+    sll t3, t3, a1
+    and  t3, t3, a2
+    lb t1, 0(a0)
+    mv t2, a2
+    not t2, t2
+    and t1, t1, t2
+    or t1, t1, t3
+    sb t1, 0(a0)
+    ret
+
+/***************************************************************************//**
+ * HW_get_8bit_reg_field is used to read the content of a field from a
+ * 8 bits wide peripheral register.
+ *
+ * a0:   addr_t reg_addr
+ * a1:   int_fast8_t shift
+ * a2:   uint_fast8_t mask
+ *
+ * @return          8 bits value containing the register field value specified
+ *                  as parameter.
+ */
+HW_get_8bit_reg_field:
+    lb a0, 0(a0)
+    and a0, a0, a2
+    srl a0, a0, a1
+    ret
+
+.end
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/hal/hw_reg_access.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/hal/hw_reg_access.h
new file mode 100644
index 0000000..bc3dd65
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/hal/hw_reg_access.h
@@ -0,0 +1,229 @@
+/***************************************************************************//**
+ * (c) Copyright 2007-2018 Microsemi SoC Products Group. All rights reserved.
+ * 
+ * Hardware registers access functions.
+ * The implementation of these function is platform and toolchain specific.
+ * The functions declared here are implemented using assembler as part of the 
+ * processor/toolchain specific HAL.
+ * 
+ * SVN $Revision: 9661 $
+ * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
+ */
+#ifndef HW_REG_ACCESS
+#define HW_REG_ACCESS
+
+#include "cpu_types.h"
+/***************************************************************************//**
+ * HW_set_32bit_reg is used to write the content of a 32 bits wide peripheral
+ * register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  write.
+ * @param value     Value to be written into the peripheral register.
+ */
+void
+HW_set_32bit_reg
+(
+    addr_t reg_addr,
+    uint32_t value
+);
+
+/***************************************************************************//**
+ * HW_get_32bit_reg is used to read the content of a 32 bits wide peripheral
+ * register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  read.
+ * @return          32 bits value read from the peripheral register.
+ */
+uint32_t
+HW_get_32bit_reg
+(
+    addr_t reg_addr
+);
+
+/***************************************************************************//**
+ * HW_set_32bit_reg_field is used to set the content of a field in a 32 bits 
+ * wide peripheral register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  be written.
+ * @param shift     Bit offset of the register field to be read within the 
+ *                  register.
+ * @param mask      Bit mask to be applied to the raw register value to filter
+ *                  out the other register fields values.
+ * @param value     Value to be written in the specified field.
+ */
+void
+HW_set_32bit_reg_field
+(
+    addr_t reg_addr,
+    int_fast8_t shift,
+    uint32_t mask,
+    uint32_t value
+);
+
+/***************************************************************************//**
+ * HW_get_32bit_reg_field is used to read the content of a field out of a 
+ * 32 bits wide peripheral register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  read.
+ * @param shift     Bit offset of the register field to be written within the 
+ *                  register.
+ * @param mask      Bit mask to be applied to the raw register value to filter
+ *                  out the other register fields values.
+ *
+ * @return          32 bits value containing the register field value specified
+ *                  as parameter.
+ */
+uint32_t 
+HW_get_32bit_reg_field
+(
+    addr_t reg_addr,
+    int_fast8_t shift,
+    uint32_t mask
+);
+
+/***************************************************************************//**
+ * HW_set_16bit_reg is used to write the content of a 16 bits wide peripheral
+ * register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  write.
+ * @param value     Value to be written into the peripheral register.
+ */
+void
+HW_set_16bit_reg
+(
+    addr_t reg_addr,
+    uint_fast16_t value
+);
+
+/***************************************************************************//**
+ * HW_get_16bit_reg is used to read the content of a 16 bits wide peripheral
+ * register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  read.
+ * @return          16 bits value read from the peripheral register.
+ */
+uint16_t
+HW_get_16bit_reg
+(
+    addr_t reg_addr
+);
+
+/***************************************************************************//**
+ * HW_set_16bit_reg_field is used to set the content of a field in a 16 bits 
+ * wide peripheral register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  be written.
+ * @param shift     Bit offset of the register field to be read within the 
+ *                  register.
+ * @param mask      Bit mask to be applied to the raw register value to filter
+ *                  out the other register fields values.
+ * @param value     Value to be written in the specified field.
+ */
+void HW_set_16bit_reg_field
+(
+    addr_t reg_addr,
+    int_fast8_t shift,
+    uint_fast16_t mask,
+    uint_fast16_t value
+);
+
+/***************************************************************************//**
+ * HW_get_16bit_reg_field is used to read the content of a field from a 
+ * 16 bits wide peripheral register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  read.
+ * @param shift     Bit offset of the register field to be written within the 
+ *                  register.
+ * @param mask      Bit mask to be applied to the raw register value to filter
+ *                  out the other register fields values.
+ *
+ * @return          16 bits value containing the register field value specified
+ *                  as parameter.
+ */
+uint16_t HW_get_16bit_reg_field
+(
+    addr_t reg_addr,
+    int_fast8_t shift,
+    uint_fast16_t mask
+);
+
+/***************************************************************************//**
+ * HW_set_8bit_reg is used to write the content of a 8 bits wide peripheral
+ * register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  write.
+ * @param value     Value to be written into the peripheral register.
+ */
+void
+HW_set_8bit_reg
+(
+    addr_t reg_addr,
+    uint_fast8_t value
+);
+
+/***************************************************************************//**
+ * HW_get_8bit_reg is used to read the content of a 8 bits wide peripheral
+ * register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  read.
+ * @return          8 bits value read from the peripheral register.
+ */
+uint8_t
+HW_get_8bit_reg
+(
+    addr_t reg_addr
+);
+
+/***************************************************************************//**
+ * HW_set_8bit_reg_field is used to set the content of a field in a 8 bits 
+ * wide peripheral register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  be written.
+ * @param shift     Bit offset of the register field to be read within the 
+ *                  register.
+ * @param mask      Bit mask to be applied to the raw register value to filter
+ *                  out the other register fields values.
+ * @param value     Value to be written in the specified field.
+ */
+void HW_set_8bit_reg_field
+(
+    addr_t reg_addr,
+    int_fast8_t shift,
+    uint_fast8_t mask,
+    uint_fast8_t value
+);
+
+/***************************************************************************//**
+ * HW_get_8bit_reg_field is used to read the content of a field from a 
+ * 8 bits wide peripheral register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  read.
+ * @param shift     Bit offset of the register field to be written within the 
+ *                  register.
+ * @param mask      Bit mask to be applied to the raw register value to filter
+ *                  out the other register fields values.
+ *
+ * @return          8 bits value containing the register field value specified
+ *                  as parameter.
+ */
+uint8_t HW_get_8bit_reg_field
+(
+    addr_t reg_addr,
+    int_fast8_t shift,
+    uint_fast8_t mask
+);
+
+#endif /* HW_REG_ACCESS */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/encoding.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/encoding.h
new file mode 100644
index 0000000..aa379ee
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/encoding.h
@@ -0,0 +1,596 @@
+/*******************************************************************************
+ * (c) Copyright 2016-2018 Microsemi SoC Products Group.  All rights reserved.
+ *
+ * @file encodings.h
+ * @author Microsemi SoC Products Group
+ * @brief Mi-V soft processor register bit mask and shift constants encodings.
+ *
+ * SVN $Revision: 9825 $
+ * SVN $Date: 2018-03-19 10:31:41 +0530 (Mon, 19 Mar 2018) $
+ */
+#ifndef RISCV_CSR_ENCODING_H
+#define RISCV_CSR_ENCODING_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MSTATUS_UIE         0x00000001
+#define MSTATUS_SIE         0x00000002
+#define MSTATUS_HIE         0x00000004
+#define MSTATUS_MIE         0x00000008
+#define MSTATUS_UPIE        0x00000010
+#define MSTATUS_SPIE        0x00000020
+#define MSTATUS_HPIE        0x00000040
+#define MSTATUS_MPIE        0x00000080
+#define MSTATUS_SPP         0x00000100
+#define MSTATUS_HPP         0x00000600
+#define MSTATUS_MPP         0x00001800
+#define MSTATUS_FS          0x00006000
+#define MSTATUS_XS          0x00018000
+#define MSTATUS_MPRV        0x00020000
+#define MSTATUS_SUM         0x00040000      /*changed in v1.10*/
+#define MSTATUS_MXR         0x00080000      /*changed in v1.10*/
+#define MSTATUS_TVM         0x00100000      /*changed in v1.10*/
+#define MSTATUS_TW          0x00200000      /*changed in v1.10*/
+#define MSTATUS_TSR         0x00400000      /*changed in v1.10*/
+#define MSTATUS_RES         0x7F800000      /*changed in v1.10*/
+#define MSTATUS32_SD        0x80000000
+#define MSTATUS64_SD        0x8000000000000000
+
+#define MCAUSE32_CAUSE       0x7FFFFFFF
+#define MCAUSE64_CAUSE       0x7FFFFFFFFFFFFFFF
+#define MCAUSE32_INT         0x80000000
+#define MCAUSE64_INT         0x8000000000000000
+
+#define SSTATUS_UIE         0x00000001
+#define SSTATUS_SIE         0x00000002
+#define SSTATUS_UPIE        0x00000010
+#define SSTATUS_SPIE        0x00000020
+#define SSTATUS_SPP         0x00000100
+#define SSTATUS_FS          0x00006000
+#define SSTATUS_XS          0x00018000
+#define SSTATUS_PUM         0x00040000
+#define SSTATUS32_SD        0x80000000
+#define SSTATUS64_SD        0x8000000000000000
+
+#define MIP_SSIP            (1u << IRQ_S_SOFT)
+#define MIP_HSIP            (1u << IRQ_H_SOFT)
+#define MIP_MSIP            (1u << IRQ_M_SOFT)
+#define MIP_STIP            (1u << IRQ_S_TIMER)
+#define MIP_HTIP            (1u << IRQ_H_TIMER)
+#define MIP_MTIP            (1u << IRQ_M_TIMER)
+#define MIP_SEIP            (1u << IRQ_S_EXT)
+#define MIP_HEIP            (1u << IRQ_H_EXT)
+#define MIP_MEIP            (1u << IRQ_M_EXT)
+
+#define SIP_SSIP            MIP_SSIP
+#define SIP_STIP            MIP_STIP
+
+#define PRV_U               0
+#define PRV_S               1
+#define PRV_H               2
+#define PRV_M               3
+
+#define VM_MBARE            0
+#define VM_MBB              1
+#define VM_MBBID            2
+#define VM_SV32             8
+#define VM_SV39             9
+#define VM_SV48             10
+
+#define IRQ_S_SOFT          1
+#define IRQ_H_SOFT          2
+#define IRQ_M_SOFT          3
+#define IRQ_S_TIMER         5
+#define IRQ_H_TIMER         6
+#define IRQ_M_TIMER         7
+#define IRQ_S_EXT           9
+#define IRQ_H_EXT           10
+#define IRQ_M_EXT           11
+
+#define DEFAULT_RSTVEC      0x00001000
+#define DEFAULT_NMIVEC      0x00001004
+#define DEFAULT_MTVEC       0x00001010
+#define CONFIG_STRING_ADDR  0x0000100C
+#define EXT_IO_BASE         0x40000000
+#define DRAM_BASE           0x80000000
+
+/* page table entry (PTE) fields */
+#define PTE_V               0x001       /* Valid */
+#define PTE_TYPE            0x01E       /* Type  */
+#define PTE_R               0x020       /* Referenced */
+#define PTE_D               0x040       /* Dirty */
+#define PTE_SOFT            0x380       /* Reserved for Software */
+
+#define PTE_TYPE_TABLE        0x00
+#define PTE_TYPE_TABLE_GLOBAL 0x02
+#define PTE_TYPE_URX_SR       0x04
+#define PTE_TYPE_URWX_SRW     0x06
+#define PTE_TYPE_UR_SR        0x08
+#define PTE_TYPE_URW_SRW      0x0A
+#define PTE_TYPE_URX_SRX      0x0C
+#define PTE_TYPE_URWX_SRWX    0x0E
+#define PTE_TYPE_SR           0x10
+#define PTE_TYPE_SRW          0x12
+#define PTE_TYPE_SRX          0x14
+#define PTE_TYPE_SRWX         0x16
+#define PTE_TYPE_SR_GLOBAL    0x18
+#define PTE_TYPE_SRW_GLOBAL   0x1A
+#define PTE_TYPE_SRX_GLOBAL   0x1C
+#define PTE_TYPE_SRWX_GLOBAL  0x1E
+
+#define PTE_PPN_SHIFT 10
+
+#define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1)
+#define PTE_UR(PTE)    ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1)
+#define PTE_UW(PTE)    ((0x00008880U >> ((PTE) & 0x1F)) & 1)
+#define PTE_UX(PTE)    ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1)
+#define PTE_SR(PTE)    ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1)
+#define PTE_SW(PTE)    ((0x88888880U >> ((PTE) & 0x1F)) & 1)
+#define PTE_SX(PTE)    ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1)
+
+#define PTE_CHECK_PERM(PTE, SUPERVISOR, STORE, FETCH) \
+  ((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \
+   (FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \
+             ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
+
+#ifdef __riscv
+
+#if __riscv_xlen == 64
+# define MSTATUS_SD             MSTATUS64_SD
+# define SSTATUS_SD             SSTATUS64_SD
+# define MCAUSE_INT             MCAUSE64_INT
+# define MCAUSE_CAUSE           MCAUSE64_CAUSE
+# define RISCV_PGLEVEL_BITS     9
+#else
+# define MSTATUS_SD             MSTATUS32_SD
+# define SSTATUS_SD             SSTATUS32_SD
+# define RISCV_PGLEVEL_BITS     10
+# define MCAUSE_INT             MCAUSE32_INT
+# define MCAUSE_CAUSE           MCAUSE32_CAUSE
+#endif
+
+#define RISCV_PGSHIFT           12
+#define RISCV_PGSIZE            (1 << RISCV_PGSHIFT)
+
+#ifndef __ASSEMBLER__
+
+#ifdef __GNUC__
+
+#define read_csr(reg) ({ unsigned long __tmp; \
+  asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+  __tmp; })
+
+#define write_csr(reg, val) ({ \
+  if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+    asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
+  else \
+    asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
+
+#define swap_csr(reg, val) ({ unsigned long __tmp; \
+  if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+    asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
+  else \
+    asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
+  __tmp; })
+
+#define set_csr(reg, bit) ({ unsigned long __tmp; \
+  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+    asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+  else \
+    asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+  __tmp; })
+
+#define clear_csr(reg, bit) ({ unsigned long __tmp; \
+  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+    asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+  else \
+    asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+  __tmp; })
+
+#define rdtime() read_csr(time)
+#define rdcycle() read_csr(cycle)
+#define rdinstret() read_csr(instret)
+
+#ifdef __riscv_atomic
+
+#define MASK(nr)                    (1UL << nr)
+#define MASK_NOT(nr)                (~(1UL << nr))
+
+/**
+ * atomic_read - read atomic variable
+ * @v: pointer of type int
+ *
+ * Atomically reads the value of @v.
+ */
+static inline int atomic_read(const int *v)
+{
+    return *((volatile int *)(v));
+}
+
+/**
+ * atomic_set - set atomic variable
+ * @v: pointer of type int
+ * @i: required value
+ *
+ * Atomically sets the value of @v to @i.
+ */
+static inline void atomic_set(int *v, int i)
+{
+    *v = i;
+}
+
+/**
+ * atomic_add - add integer to atomic variable
+ * @i: integer value to add
+ * @v: pointer of type int
+ *
+ * Atomically adds @i to @v.
+ */
+static inline void atomic_add(int i, int *v)
+{
+    __asm__ __volatile__ (
+        "amoadd.w zero, %1, %0"
+        : "+A" (*v)
+        : "r" (i));
+}
+
+static inline int atomic_fetch_add(unsigned int mask, int *v)
+{
+    int out;
+
+    __asm__ __volatile__ (
+        "amoadd.w %2, %1, %0"
+        : "+A" (*v), "=r" (out)
+        : "r" (mask));
+    return out;
+}
+
+/**
+ * atomic_sub - subtract integer from atomic variable
+ * @i: integer value to subtract
+ * @v: pointer of type int
+ *
+ * Atomically subtracts @i from @v.
+ */
+static inline void atomic_sub(int i, int *v)
+{
+    atomic_add(-i, v);
+}
+
+static inline int atomic_fetch_sub(unsigned int mask, int *v)
+{
+    int out;
+
+    __asm__ __volatile__ (
+        "amosub.w %2, %1, %0"
+        : "+A" (*v), "=r" (out)
+        : "r" (mask));
+    return out;
+}
+
+/**
+ * atomic_add_return - add integer to atomic variable
+ * @i: integer value to add
+ * @v: pointer of type int
+ *
+ * Atomically adds @i to @v and returns the result
+ */
+static inline int atomic_add_return(int i, int *v)
+{
+    register int c;
+    __asm__ __volatile__ (
+        "amoadd.w %0, %2, %1"
+        : "=r" (c), "+A" (*v)
+        : "r" (i));
+    return (c + i);
+}
+
+/**
+ * atomic_sub_return - subtract integer from atomic variable
+ * @i: integer value to subtract
+ * @v: pointer of type int
+ *
+ * Atomically subtracts @i from @v and returns the result
+ */
+static inline int atomic_sub_return(int i, int *v)
+{
+    return atomic_add_return(-i, v);
+}
+
+/**
+ * atomic_inc - increment atomic variable
+ * @v: pointer of type int
+ *
+ * Atomically increments @v by 1.
+ */
+static inline void atomic_inc(int *v)
+{
+    atomic_add(1, v);
+}
+
+/**
+ * atomic_dec - decrement atomic variable
+ * @v: pointer of type int
+ *
+ * Atomically decrements @v by 1.
+ */
+static inline void atomic_dec(int *v)
+{
+    atomic_add(-1, v);
+}
+
+static inline int atomic_inc_return(int *v)
+{
+    return atomic_add_return(1, v);
+}
+
+static inline int atomic_dec_return(int *v)
+{
+    return atomic_sub_return(1, v);
+}
+
+/**
+ * atomic_sub_and_test - subtract value from variable and test result
+ * @i: integer value to subtract
+ * @v: pointer of type int
+ *
+ * Atomically subtracts @i from @v and returns
+ * true if the result is zero, or false for all
+ * other cases.
+ */
+static inline int atomic_sub_and_test(int i, int *v)
+{
+    return (atomic_sub_return(i, v) == 0);
+}
+
+/**
+ * atomic_inc_and_test - increment and test
+ * @v: pointer of type int
+ *
+ * Atomically increments @v by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+static inline int atomic_inc_and_test(int *v)
+{
+    return (atomic_inc_return(v) == 0);
+}
+
+/**
+ * atomic_dec_and_test - decrement and test
+ * @v: pointer of type int
+ *
+ * Atomically decrements @v by 1 and
+ * returns true if the result is 0, or false for all other
+ * cases.
+ */
+static inline int atomic_dec_and_test(int *v)
+{
+    return (atomic_dec_return(v) == 0);
+}
+
+/**
+ * atomic_add_negative - add and test if negative
+ * @i: integer value to add
+ * @v: pointer of type int
+ *
+ * Atomically adds @i to @v and returns true
+ * if the result is negative, or false when
+ * result is greater than or equal to zero.
+ */
+static inline int atomic_add_negative(int i, int *v)
+{
+    return (atomic_add_return(i, v) < 0);
+}
+
+static inline int atomic_xchg(int *v, int n)
+{
+    register int c;
+    __asm__ __volatile__ (
+        "amoswap.w %0, %2, %1"
+        : "=r" (c), "+A" (*v)
+        : "r" (n));
+    return c;
+}
+
+/**
+ * atomic_and - Atomically clear bits in atomic variable
+ * @mask: Mask of the bits to be retained
+ * @v: pointer of type int
+ *
+ * Atomically retains the bits set in @mask from @v
+ */
+static inline void atomic_and(unsigned int mask, int *v)
+{
+    __asm__ __volatile__ (
+        "amoand.w zero, %1, %0"
+        : "+A" (*v)
+        : "r" (mask));
+}
+
+static inline int atomic_fetch_and(unsigned int mask, int *v)
+{
+    int out;
+    __asm__ __volatile__ (
+        "amoand.w %2, %1, %0"
+        : "+A" (*v), "=r" (out)
+        : "r" (mask));
+    return out;
+}
+
+/**
+ * atomic_or - Atomically set bits in atomic variable
+ * @mask: Mask of the bits to be set
+ * @v: pointer of type int
+ *
+ * Atomically sets the bits set in @mask in @v
+ */
+static inline void atomic_or(unsigned int mask, int *v)
+{
+    __asm__ __volatile__ (
+        "amoor.w zero, %1, %0"
+        : "+A" (*v)
+        : "r" (mask));
+}
+
+static inline int atomic_fetch_or(unsigned int mask, int *v)
+{
+    int out;
+    __asm__ __volatile__ (
+        "amoor.w %2, %1, %0"
+        : "+A" (*v), "=r" (out)
+        : "r" (mask));
+    return out;
+}
+
+/**
+ * atomic_xor - Atomically flips bits in atomic variable
+ * @mask: Mask of the bits to be flipped
+ * @v: pointer of type int
+ *
+ * Atomically flips the bits set in @mask in @v
+ */
+static inline void atomic_xor(unsigned int mask, int *v)
+{
+    __asm__ __volatile__ (
+        "amoxor.w zero, %1, %0"
+        : "+A" (*v)
+        : "r" (mask));
+}
+
+static inline int atomic_fetch_xor(unsigned int mask, int *v)
+{
+    int out;
+    __asm__ __volatile__ (
+        "amoxor.w %2, %1, %0"
+        : "+A" (*v), "=r" (out)
+        : "r" (mask));
+    return out;
+}
+
+/*----------------------------------------------------*/
+
+/**
+ * test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
+{
+    unsigned long __res, __mask;
+    __mask = MASK(nr);
+    __asm__ __volatile__ (                \
+        "amoor.w %0, %2, %1"            \
+        : "=r" (__res), "+A" (*addr)    \
+        : "r" (__mask));                \
+
+        return ((__res & __mask) != 0);
+}
+
+
+/**
+ * test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to clear
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
+{
+    unsigned long __res, __mask;
+    __mask = MASK_NOT(nr);
+    __asm__ __volatile__ (                \
+        "amoand.w %0, %2, %1"            \
+        : "=r" (__res), "+A" (*addr)    \
+        : "r" (__mask));                \
+
+        return ((__res & __mask) != 0);
+}
+
+/**
+ * test_and_change_bit - Change a bit and return its old value
+ * @nr: Bit to change
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
+{
+
+    unsigned long __res, __mask;
+    __mask = MASK(nr);
+    __asm__ __volatile__ (                \
+        "amoxor.w %0, %2, %1"            \
+        : "=r" (__res), "+A" (*addr)    \
+        : "r" (__mask));                \
+
+        return ((__res & __mask) != 0);
+}
+
+/**
+ * set_bit - Atomically set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * This function is atomic and may not be reordered. 
+ */
+
+static inline void set_bit(int nr, volatile unsigned long *addr)
+{
+    __asm__ __volatile__ (                    \
+        "AMOOR.w zero, %1, %0"            \
+        : "+A" (*addr)            \
+        : "r" (MASK(nr)));
+}
+
+/**
+ * clear_bit - Clears a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * clear_bit() is atomic and may not be reordered.  
+ */
+static inline void clear_bit(int nr, volatile unsigned long *addr)
+{
+    __asm__ __volatile__ (                    \
+        "AMOAND.w zero, %1, %0"            \
+        : "+A" (*addr)            \
+        : "r" (MASK_NOT(nr)));
+}
+
+/**
+ * change_bit - Toggle a bit in memory
+ * @nr: Bit to change
+ * @addr: Address to start counting from
+ *
+ * change_bit() is atomic and may not be reordered.
+ */
+static inline void change_bit(int nr, volatile unsigned long *addr)
+{
+    __asm__ __volatile__ (                    \
+            "AMOXOR.w zero, %1, %0"            \
+            : "+A" (*addr)            \
+            : "r" (MASK(nr)));
+}
+
+#endif /* __riscv_atomic */
+
+#endif  /*__GNUC__*/
+
+#endif  /*__ASSEMBLER__*/
+
+#endif  /*__riscv*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif    /*RISCV_CSR_ENCODING_H*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/entry.S b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/entry.S
new file mode 100644
index 0000000..6412370
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/entry.S
@@ -0,0 +1,162 @@
+/*******************************************************************************
+ * (c) Copyright 2016-2018 Microsemi SoC Products Group.  All rights reserved.
+ *
+ * @file entry.S
+ * @author Microsemi SoC Products Group
+ * @brief Mi-V soft processor vectors, trap handling and startup code.
+ *
+ * SVN $Revision: 9947 $
+ * SVN $Date: 2018-04-30 20:28:49 +0530 (Mon, 30 Apr 2018) $
+ */
+#ifndef ENTRY_S
+#define ENTRY_S
+
+#include "encoding.h"
+
+#if __riscv_xlen == 64
+# define LREG ld
+# define SREG sd
+# define REGBYTES 8
+#else
+# define LREG lw
+# define SREG sw
+# define REGBYTES 4
+#endif
+
+  .section      .text.entry
+  .extern freertos_risc_v_trap_handler
+  .globl _start
+
+_start:
+  j handle_reset
+
+nmi_vector:
+  j nmi_vector
+
+trap_vector:
+  j freertos_risc_v_trap_handler
+
+handle_reset:
+  la t0, freertos_risc_v_trap_handler
+  csrw mtvec, t0
+  csrwi mstatus, 0
+  csrwi mie, 0
+
+/*Floating point support configuration*/
+
+#ifdef __riscv_flen
+  csrr t0, mstatus
+  lui t1, 0xffffa
+  addi t1, t1, -1
+  and t0, t0, t1
+  lui t1, 0x4
+  or t1, t0, t1
+  csrw mstatus, t1
+
+  lui t0, 0x0
+  fscsr t0
+#endif
+.option push
+
+# Ensure the instruction is not optimized, since gp is not yet set
+
+.option norelax
+  # initialize global pointer
+  la gp, __global_pointer$
+
+.option pop
+
+  # initialize stack pointer
+  la sp, __stack_top
+
+  # perform the rest of initialization in C
+  j _init
+
+#if 0
+trap_entry:
+  addi sp, sp, -32*REGBYTES
+
+  SREG x1, 0 * REGBYTES(sp)
+  SREG x2, 1 * REGBYTES(sp)
+  SREG x3, 2 * REGBYTES(sp)
+  SREG x4, 3 * REGBYTES(sp)
+  SREG x5, 4 * REGBYTES(sp)
+  SREG x6, 5 * REGBYTES(sp)
+  SREG x7, 6 * REGBYTES(sp)
+  SREG x8, 7 * REGBYTES(sp)
+  SREG x9, 8 * REGBYTES(sp)
+  SREG x10, 9 * REGBYTES(sp)
+  SREG x11, 10 * REGBYTES(sp)
+  SREG x12, 11 * REGBYTES(sp)
+  SREG x13, 12 * REGBYTES(sp)
+  SREG x14, 13 * REGBYTES(sp)
+  SREG x15, 14 * REGBYTES(sp)
+  SREG x16, 15 * REGBYTES(sp)
+  SREG x17, 16 * REGBYTES(sp)
+  SREG x18, 17 * REGBYTES(sp)
+  SREG x19, 18 * REGBYTES(sp)
+  SREG x20, 19 * REGBYTES(sp)
+  SREG x21, 20 * REGBYTES(sp)
+  SREG x22, 21 * REGBYTES(sp)
+  SREG x23, 22 * REGBYTES(sp)
+  SREG x24, 23 * REGBYTES(sp)
+  SREG x25, 24 * REGBYTES(sp)
+  SREG x26, 25 * REGBYTES(sp)
+  SREG x27, 26 * REGBYTES(sp)
+  SREG x28, 27 * REGBYTES(sp)
+  SREG x29, 28 * REGBYTES(sp)
+  SREG x30, 29 * REGBYTES(sp)
+  SREG x31, 30 * REGBYTES(sp)
+
+
+  csrr t0, mepc
+  SREG t0, 31 * REGBYTES(sp)
+
+  csrr a0, mcause
+  csrr a1, mepc
+  mv a2, sp
+  jal handle_trap
+  csrw mepc, a0
+
+  # Remain in M-mode after mret
+  li t0, MSTATUS_MPP
+  csrs mstatus, t0
+
+  LREG x1, 0 * REGBYTES(sp)
+  LREG x2, 1 * REGBYTES(sp)
+  LREG x3, 2 * REGBYTES(sp)
+  LREG x4, 3 * REGBYTES(sp)
+  LREG x5, 4 * REGBYTES(sp)
+  LREG x6, 5 * REGBYTES(sp)
+  LREG x7, 6 * REGBYTES(sp)
+  LREG x8, 7 * REGBYTES(sp)
+  LREG x9, 8 * REGBYTES(sp)
+  LREG x10, 9 * REGBYTES(sp)
+  LREG x11, 10 * REGBYTES(sp)
+  LREG x12, 11 * REGBYTES(sp)
+  LREG x13, 12 * REGBYTES(sp)
+  LREG x14, 13 * REGBYTES(sp)
+  LREG x15, 14 * REGBYTES(sp)
+  LREG x16, 15 * REGBYTES(sp)
+  LREG x17, 16 * REGBYTES(sp)
+  LREG x18, 17 * REGBYTES(sp)
+  LREG x19, 18 * REGBYTES(sp)
+  LREG x20, 19 * REGBYTES(sp)
+  LREG x21, 20 * REGBYTES(sp)
+  LREG x22, 21 * REGBYTES(sp)
+  LREG x23, 22 * REGBYTES(sp)
+  LREG x24, 23 * REGBYTES(sp)
+  LREG x25, 24 * REGBYTES(sp)
+  LREG x26, 25 * REGBYTES(sp)
+  LREG x27, 26 * REGBYTES(sp)
+  LREG x28, 27 * REGBYTES(sp)
+  LREG x29, 28 * REGBYTES(sp)
+  LREG x30, 29 * REGBYTES(sp)
+  LREG x31, 30 * REGBYTES(sp)
+
+  addi sp, sp, 32*REGBYTES
+  mret
+#endif /* 0 */
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/init.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/init.c
new file mode 100644
index 0000000..8c5998f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/init.c
@@ -0,0 +1,80 @@
+/*******************************************************************************
+ * (c) Copyright 2016-2018 Microsemi SoC Products Group.  All rights reserved.
+ *
+ * @file init.c
+ * @author Microsemi SoC Products Group
+ * @brief Mi-V soft processor memory section initializations and start-up code.
+ *
+ * SVN $Revision: 9661 $
+ * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
+ */
+
+#include 
+#include 
+#include 
+
+#include "encoding.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t     __sdata_load;
+extern uint32_t     __sdata_start;
+extern uint32_t     __sdata_end;
+
+extern uint32_t     __data_load;
+extern uint32_t     __data_start;
+extern uint32_t     __data_end;
+
+extern uint32_t     __sbss_start;
+extern uint32_t     __sbss_end;
+extern uint32_t     __bss_start;
+extern uint32_t     __bss_end;
+
+
+static void copy_section(uint32_t * p_load, uint32_t * p_vma, uint32_t * p_vma_end)
+{
+    while(p_vma <= p_vma_end)
+    {
+        *p_vma = *p_load;
+        ++p_load;
+        ++p_vma;
+    }
+}
+
+static void zero_section(uint32_t * start, uint32_t * end)
+{
+    uint32_t * p_zero = start;
+    
+    while(p_zero <= end)
+    {
+        *p_zero = 0;
+        ++p_zero;
+    }
+}
+
+void _init(void)
+{
+    extern int main(int, char**);
+    const char *argv0 = "hello";
+    char *argv[] = {(char *)argv0, NULL, NULL};
+
+    copy_section(&__sdata_load, &__sdata_start, &__sdata_end);
+    copy_section(&__data_load, &__data_start, &__data_end);
+    zero_section(&__sbss_start, &__sbss_end);
+    zero_section(&__bss_start, &__bss_end);
+    
+    main(1, argv);
+}
+
+/* Function called after main() finishes */
+void
+_fini()
+{
+}
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/microsemi-riscv-igloo2.ld b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/microsemi-riscv-igloo2.ld
new file mode 100644
index 0000000..68d030d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/microsemi-riscv-igloo2.ld
@@ -0,0 +1,139 @@
+/*******************************************************************************
+ * (c) Copyright 2016-2018 Microsemi SoC Products Group.  All rights reserved.
+ *
+ * file name : microsemi-riscv-igloo2.ld
+ * Mi-V soft processor linker script for creating a SoftConsole downloadable
+ * image executing in eNVM.
+ *
+ * This linker script assumes that the eNVM is connected at on the Mi-V soft
+ * processor memory space.
+ *
+ * SVN $Revision: 9661 $
+ * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
+ */
+
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+
+MEMORY
+{
+    envm (rx) : ORIGIN = 0x60000000, LENGTH = 240k
+    ram (rwx) : ORIGIN = 0x80000000, LENGTH = 64k
+}
+
+RAM_START_ADDRESS   = 0x80000000;       /* Must be the same value MEMORY region ram ORIGIN above. */
+RAM_SIZE            = 64k;              /* Must be the same value MEMORY region ram LENGTH above. */
+STACK_SIZE          = 2k;               /* needs to be calculated for your application */
+HEAP_SIZE           = 2k;               /* needs to be calculated for your application */
+
+SECTIONS
+{
+  .text : ALIGN(0x10)
+  {
+    KEEP (*(SORT_NONE(.text.entry)))
+    . = ALIGN(0x10);
+    *(.text .text.* .gnu.linkonce.t.*)
+    *(.plt)
+    . = ALIGN(0x10);
+
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*crtend.o(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*crtend.o(.dtors))
+
+    *(.rodata .rodata.* .gnu.linkonce.r.*)
+    *(.gcc_except_table)
+    *(.eh_frame_hdr)
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(0x10);
+
+  } >envm
+
+  /* short/global data section */
+  .sdata : ALIGN(0x10)
+  {
+    __sdata_load = LOADADDR(.sdata);
+    __sdata_start = .;
+    PROVIDE( __global_pointer$ = . + 0x800);
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+    *(.srodata*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+    . = ALIGN(0x10);
+    __sdata_end = .;
+  } >ram AT>envm
+
+  /* data section */
+  .data : ALIGN(0x10)
+  {
+    __data_load = LOADADDR(.data);
+    __data_start = .;
+    *(.got.plt) *(.got)
+    *(.shdata)
+    *(.data .data.* .gnu.linkonce.d.*)
+    . = ALIGN(0x10);
+    __data_end = .;
+  } >ram AT>envm
+
+  /* sbss section */
+  .sbss : ALIGN(0x10)
+  {
+    __sbss_start = .;
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+    . = ALIGN(0x10);
+    __sbss_end = .;
+  } > ram
+
+  /* sbss section */
+  .bss : ALIGN(0x10)
+  {
+    __bss_start = .;
+    *(.shbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(0x10);
+    __bss_end = .;
+  } > ram
+
+  /* End of uninitialized data segment */
+  _end = .;
+
+  .heap : ALIGN(0x10)
+  {
+    __heap_start = .;
+    . += HEAP_SIZE;
+    __heap_end = .;
+    . = ALIGN(0x10);
+    _heap_end = __heap_end;
+  } > ram
+
+  .stack : ALIGN(0x10)
+  {
+    __stack_bottom = .;
+    . += STACK_SIZE;
+    __stack_top = .;
+    _sp = .;
+	__freertos_irq_stack_top = .;
+  } > ram
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/microsemi-riscv-ram.ld b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/microsemi-riscv-ram.ld
new file mode 100644
index 0000000..6b08b83
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/microsemi-riscv-ram.ld
@@ -0,0 +1,139 @@
+/*******************************************************************************
+ * (c) Copyright 2016-2018 Microsemi SoC Products Group.  All rights reserved.
+ *
+ * file name : microsemi-riscv-ram.ld
+ * Mi-V soft processor linker script for creating a SoftConsole downloadable
+ * debug image executing in SRAM.
+ *
+ * This linker script assumes that the SRAM is connected at on the Mi-V soft
+ * processor memory space. The start address and size of the memory space must
+ * be correct as per the Libero design.
+ *
+ * SVN $Revision: 9661 $
+ * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
+ */
+
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+
+MEMORY
+{
+    ram (rwx) : ORIGIN = 0x80000000, LENGTH = 512k
+}
+
+RAM_START_ADDRESS   = 0x80000000;       /* Must be the same value MEMORY region ram ORIGIN above. */
+RAM_SIZE            = 512k;              /* Must be the same value MEMORY region ram LENGTH above. */
+STACK_SIZE          = 2k;               /* needs to be calculated for your application */
+HEAP_SIZE           = 4;               /* needs to be calculated for your application */
+
+SECTIONS
+{
+  .text : ALIGN(0x10)
+  {
+    KEEP (*(SORT_NONE(.text.entry)))
+    . = ALIGN(0x10);
+    *(.text .text.* .gnu.linkonce.t.*)
+    *(.plt)
+    . = ALIGN(0x10);
+
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*crtend.o(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*crtend.o(.dtors))
+
+    *(.rodata .rodata.* .gnu.linkonce.r.*)
+    *(.gcc_except_table)
+    *(.eh_frame_hdr)
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(0x10);
+
+  } > ram
+
+  /* short/global data section */
+  .sdata : ALIGN(0x10)
+  {
+    __sdata_load = LOADADDR(.sdata);
+    __sdata_start = .;
+    PROVIDE( __global_pointer$ = . + 0x800);
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+    *(.srodata*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+    . = ALIGN(0x10);
+    __sdata_end = .;
+  } > ram
+
+  /* data section */
+  .data : ALIGN(0x10)
+  {
+    __data_load = LOADADDR(.data);
+    __data_start = .;
+    *(.got.plt) *(.got)
+    *(.shdata)
+    *(.data .data.* .gnu.linkonce.d.*)
+    . = ALIGN(0x10);
+    __data_end = .;
+  } > ram
+
+  /* sbss section */
+  .sbss : ALIGN(0x10)
+  {
+    __sbss_start = .;
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+    . = ALIGN(0x10);
+    __sbss_end = .;
+  } > ram
+
+  /* sbss section */
+  .bss : ALIGN(0x10)
+  {
+    __bss_start = .;
+    *(.shbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(0x10);
+    __bss_end = .;
+  } > ram
+
+  /* End of uninitialized data segment */
+  _end = .;
+
+  .heap : ALIGN(0x10)
+  {
+    __heap_start = .;
+    . += HEAP_SIZE;
+    __heap_end = .;
+    . = ALIGN(0x10);
+    _heap_end = __heap_end;
+  } > ram
+
+  .stack : ALIGN(0x10)
+  {
+    __stack_bottom = .;
+    . += STACK_SIZE;
+    __stack_top = .;
+    _sp = .;
+	__freertos_irq_stack_top = .;
+  } > ram
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/riscv_hal.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/riscv_hal.c
new file mode 100644
index 0000000..14ecf7b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/riscv_hal.c
@@ -0,0 +1,130 @@
+/*******************************************************************************
+ * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved.
+ *
+ * @file riscv_hal.c
+ * @author Microsemi SoC Products Group
+ * @brief Implementation of Hardware Abstraction Layer for Mi-V soft processors
+ *
+ * SVN $Revision: 9835 $
+ * SVN $Date: 2018-03-19 19:11:35 +0530 (Mon, 19 Mar 2018) $
+ */
+#include 
+#include 
+#include 
+
+#include "riscv_hal.h"
+
+#include "FreeRTOS.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RTC_PRESCALER 100UL
+
+#define SUCCESS 0U
+#define ERROR   1U
+
+/*------------------------------------------------------------------------------
+ *
+ */
+uint8_t Invalid_IRQHandler(void);
+uint8_t External_1_IRQHandler(void);
+uint8_t External_2_IRQHandler(void);
+uint8_t External_3_IRQHandler(void);
+uint8_t External_4_IRQHandler(void);
+uint8_t External_5_IRQHandler(void);
+uint8_t External_6_IRQHandler(void);
+uint8_t External_7_IRQHandler(void);
+uint8_t External_8_IRQHandler(void);
+uint8_t External_9_IRQHandler(void);
+uint8_t External_10_IRQHandler(void);
+uint8_t External_11_IRQHandler(void);
+uint8_t External_12_IRQHandler(void);
+uint8_t External_13_IRQHandler(void);
+uint8_t External_14_IRQHandler(void);
+uint8_t External_15_IRQHandler(void);
+uint8_t External_16_IRQHandler(void);
+uint8_t External_17_IRQHandler(void);
+uint8_t External_18_IRQHandler(void);
+uint8_t External_19_IRQHandler(void);
+uint8_t External_20_IRQHandler(void);
+uint8_t External_21_IRQHandler(void);
+uint8_t External_22_IRQHandler(void);
+uint8_t External_23_IRQHandler(void);
+uint8_t External_24_IRQHandler(void);
+uint8_t External_25_IRQHandler(void);
+uint8_t External_26_IRQHandler(void);
+uint8_t External_27_IRQHandler(void);
+uint8_t External_28_IRQHandler(void);
+uint8_t External_29_IRQHandler(void);
+uint8_t External_30_IRQHandler(void);
+uint8_t External_31_IRQHandler(void);
+
+/*------------------------------------------------------------------------------
+ *
+ */
+extern void Software_IRQHandler(void);
+extern void Timer_IRQHandle( void );
+
+/*------------------------------------------------------------------------------
+ * RISC-V interrupt handler for external interrupts.
+ */
+uint8_t (*ext_irq_handler_table[32])(void) =
+{
+    Invalid_IRQHandler,
+    External_1_IRQHandler,
+    External_2_IRQHandler,
+    External_3_IRQHandler,
+    External_4_IRQHandler,
+    External_5_IRQHandler,
+    External_6_IRQHandler,
+    External_7_IRQHandler,
+    External_8_IRQHandler,
+    External_9_IRQHandler,
+    External_10_IRQHandler,
+    External_11_IRQHandler,
+    External_12_IRQHandler,
+    External_13_IRQHandler,
+    External_14_IRQHandler,
+    External_15_IRQHandler,
+    External_16_IRQHandler,
+    External_17_IRQHandler,
+    External_18_IRQHandler,
+    External_19_IRQHandler,
+    External_20_IRQHandler,
+    External_21_IRQHandler,
+    External_22_IRQHandler,
+    External_23_IRQHandler,
+    External_24_IRQHandler,
+    External_25_IRQHandler,
+    External_26_IRQHandler,
+    External_27_IRQHandler,
+    External_28_IRQHandler,
+    External_29_IRQHandler,
+    External_30_IRQHandler,
+    External_31_IRQHandler
+};
+
+/*------------------------------------------------------------------------------
+ *
+ */
+void handle_m_ext_interrupt(void)
+{
+    uint32_t int_num  = PLIC_ClaimIRQ();
+    uint8_t disable = EXT_IRQ_KEEP_ENABLED;
+
+    disable = ext_irq_handler_table[int_num]();
+
+    PLIC_CompleteIRQ(int_num);
+
+    if(EXT_IRQ_DISABLE == disable)
+    {
+        PLIC_DisableIRQ((IRQn_Type)int_num);
+    }
+}
+
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/riscv_hal.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/riscv_hal.h
new file mode 100644
index 0000000..7c3835f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/riscv_hal.h
@@ -0,0 +1,55 @@
+/*******************************************************************************
+ * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved.
+ *
+ * @file riscv_hal.h
+ * @author Microsemi SoC Products Group
+ * @brief Hardware Abstraction Layer functions for Mi-V soft processors
+ *
+ * SVN $Revision: 9835 $
+ * SVN $Date: 2018-03-19 19:11:35 +0530 (Mon, 19 Mar 2018) $
+ */
+
+#ifndef RISCV_HAL_H
+#define RISCV_HAL_H
+
+#include "riscv_plic.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *Return value from External IRQ handler. This will be used to disable the External
+ *interrupt.
+ */
+#define EXT_IRQ_KEEP_ENABLED                0U
+#define EXT_IRQ_DISABLE                     1U
+
+/*------------------------------------------------------------------------------
+ * Interrupt enable/disable.
+ */
+void __disable_irq(void);
+void __enable_irq(void);
+
+/*------------------------------------------------------------------------------
+ *  System tick handler. This is generated from the RISC-V machine timer.
+ */
+void SysTick_Handler(void);
+
+/*------------------------------------------------------------------------------
+ * System tick configuration.
+ * Configures the machine timer to generate a system tick interrupt at regular
+ * intervals.
+ * Takes the number of system clock ticks between interrupts.
+ *
+ * Returns 0 if successful.
+ * Returns 1 if the interrupt interval cannot be achieved.
+ */
+uint32_t SysTick_Config(uint32_t ticks);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* RISCV_HAL_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/riscv_hal_stubs.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/riscv_hal_stubs.c
new file mode 100644
index 0000000..29a4f40
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/riscv_hal_stubs.c
@@ -0,0 +1,227 @@
+/*******************************************************************************
+ * (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved.
+ *
+ * @file riscv_hal_stubs.c
+ * @author Microsemi SoC Products Group
+ * @brief Mi-V soft processor Interrupt Function stubs.
+ * The functions below will only be linked with the application code if the user
+ * does not provide an implementation for these functions. These functions are
+ * defined with weak linking so that they can be overridden by a function with
+ * same prototype in the user's application code.
+ *
+ * SVN $Revision: 9835 $
+ * SVN $Date: 2018-03-19 19:11:35 +0530 (Mon, 19 Mar 2018) $
+ */
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) void Software_IRQHandler(void)
+{
+    _exit(10);
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) void SysTick_Handler(void)
+{
+	/*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t Invalid_IRQHandler(void)
+{
+    return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_1_IRQHandler(void)
+{
+    return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_2_IRQHandler(void)
+{
+    return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_3_IRQHandler(void)
+{
+    return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_4_IRQHandler(void)
+{
+	return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_5_IRQHandler(void)
+{
+    return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_6_IRQHandler(void)
+{
+    return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_7_IRQHandler(void)
+{
+    return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_8_IRQHandler(void)
+{
+    return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_9_IRQHandler(void)
+{
+    return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_10_IRQHandler(void)
+{
+    return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_11_IRQHandler(void)
+{
+    return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_12_IRQHandler(void)
+{
+	return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_13_IRQHandler(void)
+{
+	return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_14_IRQHandler(void)
+{
+	return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_15_IRQHandler(void)
+{
+	return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_16_IRQHandler(void)
+{
+	return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_17_IRQHandler(void)
+{
+	return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_18_IRQHandler(void)
+{
+	return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_19_IRQHandler(void)
+{
+	return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_20_IRQHandler(void)
+{
+	return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_21_IRQHandler(void)
+{
+	return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_22_IRQHandler(void)
+{
+	return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_23_IRQHandler(void)
+{
+	return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_24_IRQHandler(void)
+{
+	return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_25_IRQHandler(void)
+{
+	return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_26_IRQHandler(void)
+{
+	return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_27_IRQHandler(void)
+{
+	return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_28_IRQHandler(void)
+{
+	return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_29_IRQHandler(void)
+{
+	return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provided*/
+__attribute__((weak)) uint8_t External_30_IRQHandler(void)
+{
+	return(0U); /*Default handler*/
+}
+
+/*Weakly linked handler. Will be replaced with user's definition if provide*/
+__attribute__((weak)) uint8_t External_31_IRQHandler(void)
+{
+	return(0U); /*Default handler*/
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/riscv_plic.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/riscv_plic.h
new file mode 100644
index 0000000..2d09518
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/riscv_plic.h
@@ -0,0 +1,249 @@
+/*******************************************************************************
+ * (c) Copyright 2016-2018 Microsemi SoC Products Group.  All rights reserved.
+ *
+ * @file riscv_plic.h
+ * @author Microsemi SoC Products Group
+ * @brief Mi-V soft processor PLIC and PRCI access data structures and functions.
+ *
+ * SVN $Revision: 9838 $
+ * SVN $Date: 2018-03-19 19:22:54 +0530 (Mon, 19 Mar 2018) $
+ */
+#ifndef RISCV_PLIC_H
+#define RISCV_PLIC_H
+
+#include 
+
+#include "encoding.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PLIC_NUM_SOURCES 31
+#define PLIC_NUM_PRIORITIES 0
+
+/*==============================================================================
+ * Interrupt numbers:
+ */
+typedef enum
+{
+    NoInterrupt_IRQn = 0,
+    External_1_IRQn  = 1,
+    External_2_IRQn  = 2,
+    External_3_IRQn  = 3, 
+    External_4_IRQn  = 4,
+    External_5_IRQn  = 5,
+    External_6_IRQn  = 6,
+    External_7_IRQn  = 7,
+    External_8_IRQn  = 8,
+    External_9_IRQn  = 9,
+    External_10_IRQn = 10,
+    External_11_IRQn = 11,
+    External_12_IRQn = 12,
+    External_13_IRQn = 13,
+    External_14_IRQn = 14,
+    External_15_IRQn = 15,
+    External_16_IRQn = 16,
+    External_17_IRQn = 17,
+    External_18_IRQn = 18,
+    External_19_IRQn = 19,
+    External_20_IRQn = 20,
+    External_21_IRQn = 21,
+    External_22_IRQn = 22,
+    External_23_IRQn = 23,
+    External_24_IRQn = 24,
+    External_25_IRQn = 25,
+    External_26_IRQn = 26,
+    External_27_IRQn = 27,
+    External_28_IRQn = 28,
+    External_29_IRQn = 29,
+    External_30_IRQn = 30,
+    External_31_IRQn = 31
+} IRQn_Type;
+
+
+/*==============================================================================
+ * PLIC: Platform Level Interrupt Controller
+ */
+#define PLIC_BASE_ADDR 0x40000000UL
+
+typedef struct
+{
+    volatile uint32_t PRIORITY_THRESHOLD;
+    volatile uint32_t CLAIM_COMPLETE;
+    volatile uint32_t reserved[1022];
+} IRQ_Target_Type;
+
+typedef struct
+{
+    volatile uint32_t ENABLES[32];
+} Target_Enables_Type;
+
+typedef struct
+{
+    /*-------------------- Source Priority --------------------*/
+    volatile uint32_t SOURCE_PRIORITY[1024];
+    
+    /*-------------------- Pending array --------------------*/
+    volatile const uint32_t PENDING_ARRAY[32];
+    volatile uint32_t RESERVED1[992];
+    
+    /*-------------------- Target enables --------------------*/
+    volatile Target_Enables_Type TARGET_ENABLES[15808];
+
+    volatile uint32_t RESERVED2[16384];
+    
+    /*--- Target Priority threshold and claim/complete---------*/
+    IRQ_Target_Type TARGET[15872];
+    
+} PLIC_Type;
+
+
+#define PLIC    ((PLIC_Type *)PLIC_BASE_ADDR)
+
+/*==============================================================================
+ * PRCI: Power, Reset, Clock, Interrupt
+ */
+#define PRCI_BASE   0x44000000UL
+
+typedef struct
+{
+    volatile uint32_t MSIP[4095];
+    volatile uint32_t reserved;
+    volatile uint64_t MTIMECMP[4095];
+    volatile const uint64_t MTIME;
+} PRCI_Type;
+
+#define PRCI    ((PRCI_Type *)PRCI_BASE) 
+
+/*==============================================================================
+ * The function PLIC_init() initializes the PLIC controller and enables the 
+ * global external interrupt bit.
+ */
+static inline void PLIC_init(void)
+{
+    uint32_t inc;
+    unsigned long hart_id = read_csr(mhartid);
+
+    /* Disable all interrupts for the current hart. */
+    for(inc = 0; inc < ((PLIC_NUM_SOURCES + 32u) / 32u); ++inc)
+    {
+        PLIC->TARGET_ENABLES[hart_id].ENABLES[inc] = 0;
+    }
+
+    /* Set priorities to zero. */
+    /* Should this really be done??? Calling PLIC_init() on one hart will cause
+    * the priorities previously set by other harts to be messed up. */
+    for(inc = 0; inc < PLIC_NUM_SOURCES; ++inc)
+    {
+        PLIC->SOURCE_PRIORITY[inc] = 0;
+    }
+
+    /* Set the threshold to zero. */
+    PLIC->TARGET[hart_id].PRIORITY_THRESHOLD = 0;
+
+    /* Enable machine external interrupts. */
+    set_csr(mie, MIP_MEIP);
+}
+
+/*==============================================================================
+ * The function PLIC_EnableIRQ() enables the external interrupt for the interrupt
+ * number indicated by the parameter IRQn.
+ */
+static inline void PLIC_EnableIRQ(IRQn_Type IRQn)
+{
+    unsigned long hart_id = read_csr(mhartid);
+    uint32_t current = PLIC->TARGET_ENABLES[hart_id].ENABLES[IRQn / 32];
+    current |= (uint32_t)1 << (IRQn % 32);
+    PLIC->TARGET_ENABLES[hart_id].ENABLES[IRQn / 32] = current;
+}
+
+/*==============================================================================
+ * The function PLIC_DisableIRQ() disables the external interrupt for the interrupt
+ * number indicated by the parameter IRQn.
+
+ * NOTE:
+ * 	This function can be used to disable the external interrupt from outside
+ * 	external interrupt handler function.
+ * 	This function MUST NOT be used from within the External Interrupt handler.
+ * 	If you wish to disable the external interrupt while the interrupt handler
+ * 	for that external interrupt is executing then you must use the return value
+ * 	EXT_IRQ_DISABLE to return from the extern interrupt handler.
+ */
+static inline void PLIC_DisableIRQ(IRQn_Type IRQn)
+{
+    unsigned long hart_id = read_csr(mhartid);
+    uint32_t current = PLIC->TARGET_ENABLES[hart_id].ENABLES[IRQn / 32];
+
+    current &= ~((uint32_t)1 << (IRQn % 32));
+
+    PLIC->TARGET_ENABLES[hart_id].ENABLES[IRQn / 32] = current;
+}
+
+/*==============================================================================
+ * The function PLIC_SetPriority() sets the priority for the external interrupt 
+ * for the interrupt number indicated by the parameter IRQn.
+ */
+static inline void PLIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 
+{
+    PLIC->SOURCE_PRIORITY[IRQn] = priority;
+}
+
+/*==============================================================================
+ * The function PLIC_GetPriority() returns the priority for the external interrupt 
+ * for the interrupt number indicated by the parameter IRQn.
+ */
+static inline uint32_t PLIC_GetPriority(IRQn_Type IRQn)
+{
+    return PLIC->SOURCE_PRIORITY[IRQn];
+}
+
+/*==============================================================================
+ * The function PLIC_ClaimIRQ() claims the interrupt from the PLIC controller.
+ */
+static inline uint32_t PLIC_ClaimIRQ(void)
+{
+    unsigned long hart_id = read_csr(mhartid);
+
+    return PLIC->TARGET[hart_id].CLAIM_COMPLETE;
+}
+
+/*==============================================================================
+ * The function PLIC_CompleteIRQ() indicates to the PLIC controller the interrupt
+ * is processed and claim is complete.
+ */
+static inline void PLIC_CompleteIRQ(uint32_t source)
+{
+    unsigned long hart_id = read_csr(mhartid);
+
+    PLIC->TARGET[hart_id].CLAIM_COMPLETE = source;
+}
+
+/*==============================================================================
+ * The function raise_soft_interrupt() raises a synchronous software interrupt by
+ * writing into the MSIP register.
+ */
+static inline void raise_soft_interrupt()
+{
+    unsigned long hart_id = read_csr(mhartid);
+
+    /*You need to make sure that the global interrupt is enabled*/
+    set_csr(mie, MIP_MSIP);       /*Enable software interrupt bit */
+    PRCI->MSIP[hart_id] = 0x01;   /*raise soft interrupt for hart0*/
+}
+
+/*==============================================================================
+ * The function clear_soft_interrupt() clears a synchronous software interrupt by
+ * clearing the MSIP register.
+ */
+static inline void clear_soft_interrupt()
+{
+    unsigned long hart_id = read_csr(mhartid);
+    PRCI->MSIP[hart_id] = 0x00;   /*clear soft interrupt for hart0*/
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* RISCV_PLIC_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/sample_hw_platform.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/sample_hw_platform.h
new file mode 100644
index 0000000..d0604a1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/sample_hw_platform.h
@@ -0,0 +1,121 @@
+/*******************************************************************************
+ * (c) Copyright 2016-2018 Microsemi Corporation.  All rights reserved.
+ *
+ * Platform definitions
+ * Version based on requirements of RISCV-HAL
+ *
+ * SVN $Revision: 9946 $
+ * SVN $Date: 2018-04-30 20:26:55 +0530 (Mon, 30 Apr 2018) $
+ */
+ /*=========================================================================*//**
+  @mainpage Sample file detailing how hw_platform.h should be constructed for 
+    the Mi-V processors.
+
+    @section intro_sec Introduction
+    The hw_platform.h is to be located in the project root directory.
+    Currently this file must be hand crafted when using the Mi-V Soft Processor.
+    
+    You can use this file as sample.
+    Rename this file from sample_hw_platform.h to hw_platform.h and store it in
+    the root folder of your project. Then customize it per your HW design.
+
+    @section driver_configuration Project configuration Instructions
+    1. Change SYS_CLK_FREQ define to frequency of Mi-V Soft processor clock
+    2  Add all other core BASE addresses
+    3. Add peripheral Core Interrupt to Mi-V Soft processor interrupt mappings
+    4. Define MSCC_STDIO_UART_BASE_ADDR if you want a CoreUARTapb mapped to STDIO
+*//*=========================================================================*/
+
+#ifndef HW_PLATFORM_H
+#define HW_PLATFORM_H
+
+/***************************************************************************//**
+ * Soft-processor clock definition
+ * This is the only clock brought over from the Mi-V Soft processor Libero design.
+ */
+#ifndef SYS_CLK_FREQ
+#define SYS_CLK_FREQ                    83000000UL
+#endif
+
+
+/***************************************************************************//**
+ * Non-memory Peripheral base addresses
+ * Format of define is:
+ * __BASE_ADDR
+ */
+#define COREUARTAPB0_BASE_ADDR          0x70001000UL
+#define COREGPIO_BASE_ADDR              0x70002000UL
+#define COREGPIO_IN_BASE_ADDR           0x70002000UL
+#define CORETIMER0_BASE_ADDR            0x70003000UL
+#define CORETIMER1_BASE_ADDR            0x70004000UL
+#define COREGPIO_OUT_BASE_ADDR          0x70005000UL
+#define FLASH_CORE_SPI_BASE             0x70006000UL
+#define CORE16550_BASE_ADDR             0x70007000UL
+
+/***************************************************************************//**
+ * Peripheral Interrupts are mapped to the corresponding Mi-V Soft processor
+ * interrupt from the Libero design.
+ * There can be up to 31 external interrupts (IRQ[30:0] pins) on the Mi-V Soft
+ * processor.The Mi-V Soft processor external interrupts are defined in the
+ * riscv_plic.h
+ * These are of the form
+ * typedef enum
+{
+    NoInterrupt_IRQn = 0,
+    External_1_IRQn  = 1,
+    External_2_IRQn  = 2,
+    .
+    .
+    .
+    External_31_IRQn = 31
+} IRQn_Type;
+ 
+ The interrupt 0 on RISC-V processor is not used. The pin IRQ[0] should map to
+ External_1_IRQn likewise IRQ[30] should map to External_31_IRQn
+ * Format of define is:
+ * __
+ */
+
+#define TIMER0_IRQn                     External_30_IRQn
+#define TIMER1_IRQn                     External_31_IRQn
+
+/****************************************************************************
+ * Baud value to achieve a 115200 baud rate with a 83MHz system clock.
+ * This value is calculated using the following equation:
+ *      BAUD_VALUE = (CLOCK / (16 * BAUD_RATE)) - 1
+ *****************************************************************************/
+#define BAUD_VALUE_115200               (SYS_CLK_FREQ / (16 * 115200)) - 1
+
+/***************************************************************************//**
+ * User edit section- Edit sections below if required
+ */
+#ifdef MSCC_STDIO_THRU_CORE_UART_APB
+/*
+ * A base address mapping for the STDIO printf/scanf mapping to CortUARTapb
+ * must be provided if it is being used
+ *
+ * e.g. #define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB1_BASE_ADDR
+ */
+#define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB0_BASE_ADDR
+
+#ifndef MSCC_STDIO_UART_BASE_ADDR
+#error MSCC_STDIO_UART_BASE_ADDR not defined- e.g. #define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB1_BASE_ADDR
+#endif
+
+#ifndef MSCC_STDIO_BAUD_VALUE
+/*
+ * The MSCC_STDIO_BAUD_VALUE define should be set in your project's settings to
+ * specify the baud value used by the standard output CoreUARTapb instance for
+ * generating the UART's baud rate if you want a different baud rate from the
+ * default of 115200 baud
+ */
+#define MSCC_STDIO_BAUD_VALUE           115200
+#endif  /*MSCC_STDIO_BAUD_VALUE*/
+
+#endif  /* end of MSCC_STDIO_THRU_CORE_UART_APB */
+/*******************************************************************************
+ * End of user edit section
+ */
+#endif /* HW_PLATFORM_H */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/syscall.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/syscall.c
new file mode 100644
index 0000000..4c99f80
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/syscall.c
@@ -0,0 +1,266 @@
+/*******************************************************************************
+ * (c) Copyright 2016-2018 Microsemi SoC Products Group.  All rights reserved.
+ *
+ * @file syscall.c
+ * @author Microsemi SoC Products Group
+ * @brief Stubs for system calls.
+ *
+ * SVN $Revision: 9661 $
+ * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "encoding.h"
+
+#ifdef MSCC_STDIO_THRU_CORE_UART_APB
+
+#include "core_uart_apb.h"
+#include "hw_platform.h"
+
+#endif  /*MSCC_STDIO_THRU_CORE_UART_APB*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef MSCC_STDIO_THRU_CORE_UART_APB
+
+/*------------------------------------------------------------------------------
+ * CoreUARTapb instance data for the CoreUARTapb instance used for standard
+ * output.
+ */
+static UART_instance_t g_stdio_uart;
+
+/*==============================================================================
+ * Flag used to indicate if the UART driver needs to be initialized.
+ */
+static int g_stdio_uart_init_done = 0;
+#endif /*MSCC_STDIO_THRU_CORE_UART_APB*/
+
+#undef errno
+int errno;
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+void write_hex(int fd, uint32_t hex)
+{
+    uint8_t ii;
+    uint8_t jj;
+    char towrite;
+    uint8_t digit;
+
+    write( fd , "0x", 2 );
+
+    for (ii = 8 ; ii > 0; ii--)
+    {
+        jj = ii-1;
+        digit = ((hex & (0xF << (jj*4))) >> (jj*4));
+        towrite = digit < 0xA ? ('0' + digit) : ('A' +  (digit - 0xA));
+        write( fd, &towrite, 1);
+    }
+}
+
+               
+void _exit(int code)
+{
+#ifdef MSCC_STDIO_THRU_CORE_UART_APB
+    const char * message = "\nProgam has exited with code:";
+
+    write(STDERR_FILENO, message, strlen(message));
+    write_hex(STDERR_FILENO, code);
+#endif
+
+    while (1);
+}
+
+void *_sbrk(ptrdiff_t incr)
+{
+    extern char _end[];
+    extern char _heap_end[];
+    static char *curbrk = _end;
+
+    if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
+    {
+        return ((char *) - 1);
+    }
+
+    curbrk += incr;
+    return curbrk - incr;
+}
+
+int _isatty(int fd)
+{
+    if (fd == STDOUT_FILENO || fd == STDERR_FILENO)
+    {
+        return 1;
+    }
+
+    errno = EBADF;
+    return 0;
+}
+
+static int stub(int err)
+{
+    errno = err;
+    return -1;
+}
+
+int _open(const char* name, int flags, int mode)
+{
+    return stub(ENOENT);
+}
+
+int _openat(int dirfd, const char* name, int flags, int mode)
+{
+    return stub(ENOENT);
+}
+
+int _close(int fd)
+{
+    return stub(EBADF);
+}
+
+int _execve(const char* name, char* const argv[], char* const env[])
+{
+    return stub(ENOMEM);
+}
+
+int _fork()
+{
+    return stub(EAGAIN);
+}
+
+int _fstat(int fd, struct stat *st)
+{
+    if (isatty(fd))
+    {
+        st->st_mode = S_IFCHR;
+        return 0;
+    }
+
+    return stub(EBADF);
+}
+
+int _getpid()
+{
+    return 1;
+}
+
+int _kill(int pid, int sig)
+{
+    return stub(EINVAL);
+}
+
+int _link(const char *old_name, const char *new_name)
+{
+    return stub(EMLINK);
+}
+
+off_t _lseek(int fd, off_t ptr, int dir)
+{
+    if (_isatty(fd))
+    {
+        return 0;
+    }
+
+    return stub(EBADF);
+}
+
+ssize_t _read(int fd, void* ptr, size_t len)
+{
+#ifdef MSCC_STDIO_THRU_CORE_UART_APB
+    if (_isatty(fd))
+    {
+        /*--------------------------------------------------------------------------
+        * Initialize the UART driver if it is the first time this function is
+        * called.
+        */
+        if ( !g_stdio_uart_init_done )
+        {
+            /******************************************************************************
+            * Baud value:
+            * This value is calculated using the following equation:
+            *      BAUD_VALUE = (CLOCK / (16 * BAUD_RATE)) - 1
+            *****************************************************************************/
+            UART_init( &g_stdio_uart, MSCC_STDIO_UART_BASE_ADDR, ((SYS_CLK_FREQ/(16 * MSCC_STDIO_BAUD_VALUE))-1), (DATA_8_BITS | NO_PARITY));
+            g_stdio_uart_init_done = 1;
+        }
+
+        return UART_get_rx(&g_stdio_uart, (uint8_t*) ptr, len);
+    }
+#endif
+
+    return stub(EBADF);
+}
+
+int _stat(const char* file, struct stat* st)
+{
+    return stub(EACCES);
+}
+
+clock_t _times(struct tms* buf)
+{
+    return stub(EACCES);
+}
+
+int _unlink(const char* name)
+{
+    return stub(ENOENT);
+}
+
+int _wait(int* status)
+{
+    return stub(ECHILD);
+}
+
+ssize_t _write(int fd, const void* ptr, size_t len)
+{
+
+#ifdef MSCC_STDIO_THRU_CORE_UART_APB
+  const uint8_t * current = (const uint8_t *) ptr;
+  size_t jj;
+
+  if (_isatty(fd))
+  {
+        /*--------------------------------------------------------------------------
+        * Initialize the UART driver if it is the first time this function is
+        * called.
+        */
+        if ( !g_stdio_uart_init_done )
+        {
+            /******************************************************************************
+            * Baud value:
+            * This value is calculated using the following equation:
+            *      BAUD_VALUE = (CLOCK / (16 * BAUD_RATE)) - 1
+            *****************************************************************************/
+            UART_init( &g_stdio_uart, MSCC_STDIO_UART_BASE_ADDR, ((SYS_CLK_FREQ/(16 * MSCC_STDIO_BAUD_VALUE))-1), (DATA_8_BITS | NO_PARITY));
+            g_stdio_uart_init_done = 1;
+        }
+
+    for (jj = 0; jj < len; jj++)
+    {
+        UART_send(&g_stdio_uart, current + jj, 1);
+        if (current[jj] == '\n')
+        {
+            UART_send(&g_stdio_uart, (const uint8_t *)"\r", 1);
+        }
+    }
+    return len;
+  }
+#endif
+
+  return stub(EBADF);
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/RTOSDemo Debug Renode.launch b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/RTOSDemo Debug Renode.launch
new file mode 100644
index 0000000..3a67cbc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/RTOSDemo Debug Renode.launch	
@@ -0,0 +1,62 @@
+
+
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+        
+    
+    
+        
+    
+    
+    
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/RTOSDemo-start-renode-emulator-and-attach.launch b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/RTOSDemo-start-renode-emulator-and-attach.launch
new file mode 100644
index 0000000..383dbed
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/RTOSDemo-start-renode-emulator-and-attach.launch
@@ -0,0 +1,14 @@
+
+
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/blinky_demo/main_blinky.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/blinky_demo/main_blinky.c
new file mode 100644
index 0000000..68440c8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/blinky_demo/main_blinky.c
@@ -0,0 +1,206 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/******************************************************************************
+ * NOTE 1:  This project provides two demo applications.  A simple blinky
+ * style project, and a more comprehensive test and demo application.  The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
+ * between the two.  See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
+ * in main.c.  This file implements the simply blinky style version.
+ *
+ * NOTE 2:  This file only contains the source code that is specific to the
+ * basic demo.  Generic functions, such FreeRTOS hook functions, and functions
+ * required to configure the hardware are defined in main.c.
+ ******************************************************************************
+ *
+ * main_blinky() creates one queue, and two tasks.  It then starts the
+ * scheduler.
+ *
+ * The Queue Send Task:
+ * The queue send task is implemented by the prvQueueSendTask() function in
+ * this file.  prvQueueSendTask() sits in a loop that causes it to repeatedly
+ * block for 1000 milliseconds, before sending the value 100 to the queue that
+ * was created within main_blinky().  Once the value is sent, the task loops
+ * back around to block for another 1000 milliseconds...and so on.
+ *
+ * The Queue Receive Task:
+ * The queue receive task is implemented by the prvQueueReceiveTask() function
+ * in this file.  prvQueueReceiveTask() sits in a loop where it repeatedly
+ * blocks on attempts to read data from the queue that was created within
+ * main_blinky().  When data is received, the task checks the value of the
+ * data, and if the value equals the expected 100, writes 'Blink' to the UART
+ * (the UART is used in place of the LED to allow easy execution in QEMU).  The
+ * 'block time' parameter passed to the queue receive function specifies that
+ * the task should be held in the Blocked state indefinitely to wait for data to
+ * be available on the queue.  The queue receive task will only leave the
+ * Blocked state when the queue send task writes to the queue.  As the queue
+ * send task writes to the queue every 1000 milliseconds, the queue receive
+ * task leaves the Blocked state every 1000 milliseconds, and therefore toggles
+ * the LED every 200 milliseconds.
+ */
+
+/* Standard includes. */
+#include 
+#include 
+#include 
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* Priorities used by the tasks. */
+#define mainQUEUE_RECEIVE_TASK_PRIORITY		( tskIDLE_PRIORITY + 2 )
+#define	mainQUEUE_SEND_TASK_PRIORITY		( tskIDLE_PRIORITY + 1 )
+
+/* The rate at which data is sent to the queue.  The 200ms value is converted
+to ticks using the pdMS_TO_TICKS() macro. */
+#define mainQUEUE_SEND_FREQUENCY_MS			pdMS_TO_TICKS( 1000 )
+
+/* The maximum number items the queue can hold.  The priority of the receiving
+task is above the priority of the sending task, so the receiving task will
+preempt the sending task and remove the queue items each time the sending task
+writes to the queue.  Therefore the queue will never have more than one item in
+it at any time, and even with a queue length of 1, the sending task will never
+find the queue full. */
+#define mainQUEUE_LENGTH					( 1 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in
+ * main.c.
+ */
+void main_blinky( void );
+
+/*
+ * The tasks as described in the comments at the top of this file.
+ */
+static void prvQueueReceiveTask( void *pvParameters );
+static void prvQueueSendTask( void *pvParameters );
+
+/*-----------------------------------------------------------*/
+
+/* The queue used by both tasks. */
+static QueueHandle_t xQueue = NULL;
+
+/*-----------------------------------------------------------*/
+
+void main_blinky( void )
+{
+	/* Create the queue. */
+	xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );
+
+	if( xQueue != NULL )
+	{
+		/* Start the two tasks as described in the comments at the top of this
+		file. */
+		xTaskCreate( prvQueueReceiveTask,				/* The function that implements the task. */
+					"Rx", 								/* The text name assigned to the task - for debug only as it is not used by the kernel. */
+					configMINIMAL_STACK_SIZE * 2U, 			/* The size of the stack to allocate to the task. */
+					NULL, 								/* The parameter passed to the task - not used in this case. */
+					mainQUEUE_RECEIVE_TASK_PRIORITY, 	/* The priority assigned to the task. */
+					NULL );								/* The task handle is not required, so NULL is passed. */
+
+		xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE * 2U, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
+
+		/* Start the tasks and timer running. */
+		vTaskStartScheduler();
+	}
+
+	/* If all is well, the scheduler will now be running, and the following
+	line will never be reached.  If the following line does execute, then
+	there was insufficient FreeRTOS heap memory available for the Idle and/or
+	timer tasks to be created.  See the memory management section on the
+	FreeRTOS web site for more details on the FreeRTOS heap
+	http://www.freertos.org/a00111.html. */
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueSendTask( void *pvParameters )
+{
+TickType_t xNextWakeTime;
+const unsigned long ulValueToSend = 100UL;
+BaseType_t xReturned;
+
+	/* Remove compiler warning about unused parameter. */
+	( void ) pvParameters;
+
+	/* Initialise xNextWakeTime - this only needs to be done once. */
+	xNextWakeTime = xTaskGetTickCount();
+
+	for( ;; )
+	{
+		/* Place this task in the blocked state until it is time to run again. */
+		vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
+
+		/* Send to the queue - causing the queue receive task to unblock and
+		toggle the LED.  0 is used as the block time so the sending operation
+		will not block - it shouldn't need to block as the queue should always
+		be empty at this point in the code. */
+		xReturned = xQueueSend( xQueue, &ulValueToSend, 0U );
+		configASSERT( xReturned == pdPASS );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueReceiveTask( void *pvParameters )
+{
+unsigned long ulReceivedValue;
+const unsigned long ulExpectedValue = 100UL;
+const char * const pcPassMessage = "Blink\r\n";
+const char * const pcFailMessage = "Unexpected value received\r\n";
+extern void vSendString( const char * const pcString );
+extern void vToggleLED( void );
+
+	/* Remove compiler warning about unused parameter. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		/* Wait until something arrives in the queue - this task will block
+		indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
+		FreeRTOSConfig.h. */
+		xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
+
+		/*  To get here something must have been received from the queue, but
+		is it the expected value?  If it is, toggle the LED. */
+		if( ulReceivedValue == ulExpectedValue )
+		{
+			vSendString( pcPassMessage );
+			vToggleLED();
+			ulReceivedValue = 0U;
+		}
+		else
+		{
+			vSendString( pcFailMessage );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/full_demo/RegTest.S b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/full_demo/RegTest.S
new file mode 100644
index 0000000..67d902a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/full_demo/RegTest.S
@@ -0,0 +1,260 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	.extern ulRegTest1LoopCounter
+	.extern ulRegTest2LoopCounter
+
+	.global vRegTest1Implementation
+	.global vRegTest2Implementation
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The register check tasks are described in the comments at the top of
+ * main_full.c.
+ */
+
+vRegTest1Implementation:
+
+	/* Fill the core registers with known values. */
+	li x5, 0x5
+	li x6, 0x6
+	li x7, 0x7
+	li x8, 0x8
+	li x9, 0x9
+	li x10, 0xa
+	li x11, 0xb
+	li x12, 0xc
+	li x13, 0xd
+	li x14, 0xe
+	li x15, 0xf
+	li x16, 0x10
+	li x17, 0x11
+	li x18, 0x12
+	li x19, 0x13
+	li x20, 0x14
+	li x21, 0x15
+	li x22, 0x16
+	li x23, 0x17
+	li x24, 0x18
+	li x25, 0x19
+	li x26, 0x1a
+	li x27, 0x1b
+	li x28, 0x1c
+	li x29, 0x1d
+	li x30, 0x1e
+
+reg1_loop:
+
+	/* Check each register still contains the expected known value.
+	vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation
+	uses x5 as the temporary. */
+	li x31, 0x5
+	bne x31, x5, reg1_error_loop
+	li x31, 0x6
+	bne x31, x6, reg1_error_loop
+	li x31, 0x7
+	bne x31, x7, reg1_error_loop
+	li x31, 0x8
+	bne x31, x8, reg1_error_loop
+	li x31, 0x9
+	bne x31, x9, reg1_error_loop
+	li x31, 0xa
+	bne x31, x10, reg1_error_loop
+	li x31, 0xb
+	bne x31, x11, reg1_error_loop
+	li x31, 0xc
+	bne x31, x12, reg1_error_loop
+	li x31, 0xd
+	bne x31, x13, reg1_error_loop
+	li x31, 0xe
+	bne x31, x14, reg1_error_loop
+	li x31, 0xf
+	bne x31, x15, reg1_error_loop
+	li x31, 0x10
+	bne x31, x16, reg1_error_loop
+	li x31, 0x11
+	bne x31, x17, reg1_error_loop
+	li x31, 0x12
+	bne x31, x18, reg1_error_loop
+	li x31, 0x13
+	bne x31, x19, reg1_error_loop
+	li x31, 0x14
+	bne x31, x20, reg1_error_loop
+	li x31, 0x15
+	bne x31, x21, reg1_error_loop
+	li x31, 0x16
+	bne x31, x22, reg1_error_loop
+	li x31, 0x17
+	bne x31, x23, reg1_error_loop
+	li x31, 0x18
+	bne x31, x24, reg1_error_loop
+	li x31, 0x19
+	bne x31, x25, reg1_error_loop
+	li x31, 0x1a
+	bne x31, x26, reg1_error_loop
+	li x31, 0x1b
+	bne x31, x27, reg1_error_loop
+	li x31, 0x1c
+	bne x31, x28, reg1_error_loop
+	li x31, 0x1d
+	bne x31, x29, reg1_error_loop
+	li x31, 0x1e
+	bne x31, x30, reg1_error_loop
+
+	/* Everything passed, increment the loop counter. */
+	lw x31, ulRegTest1LoopCounterConst
+	lw x30, 0(x31)
+	addi x30, x30, 1
+	sw x30, 0(x31)
+
+	/* Restore clobbered register reading for next loop. */
+	li x30, 0x1e
+
+	/* Yield to increase code coverage. */
+	ecall
+
+	/* Start again. */
+	jal reg1_loop
+
+reg1_error_loop:
+	/* Jump here if a register contains an uxpected value.  This stops the loop
+	counter being incremented so the check task knows an error was found. */
+	jal reg1_error_loop
+
+ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter
+
+/*-----------------------------------------------------------*/
+
+vRegTest2Implementation:
+
+	/* Fill the core registers with known values. */
+	li x6, 0x61
+	li x7, 0x71
+	li x8, 0x81
+	li x9, 0x91
+	li x10, 0xa1
+	li x11, 0xb1
+	li x12, 0xc1
+	li x13, 0xd1
+	li x14, 0xe1
+	li x15, 0xf1
+	li x16, 0x20
+	li x17, 0x21
+	li x18, 0x22
+	li x19, 0x23
+	li x20, 0x24
+	li x21, 0x25
+	li x22, 0x26
+	li x23, 0x27
+	li x24, 0x28
+	li x25, 0x29
+	li x26, 0x2a
+	li x27, 0x2b
+	li x28, 0x2c
+	li x29, 0x2d
+	li x30, 0x2e
+	li x31, 0x2f
+
+Reg2_loop:
+
+	/* Check each register still contains the expected known value.
+	vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation
+	uses x31 as the temporary. */
+	li x5, 0x61
+	bne x5, x6, reg2_error_loop
+	li x5, 0x71
+	bne x5, x7, reg2_error_loop
+	li x5, 0x81
+	bne x5, x8, reg2_error_loop
+	li x5, 0x91
+	bne x5, x9, reg2_error_loop
+	li x5, 0xa1
+	bne x5, x10, reg2_error_loop
+	li x5, 0xb1
+	bne x5, x11, reg2_error_loop
+	li x5, 0xc1
+	bne x5, x12, reg2_error_loop
+	li x5, 0xd1
+	bne x5, x13, reg2_error_loop
+	li x5, 0xe1
+	bne x5, x14, reg2_error_loop
+	li x5, 0xf1
+	bne x5, x15, reg2_error_loop
+	li x5, 0x20
+	bne x5, x16, reg2_error_loop
+	li x5, 0x21
+	bne x5, x17, reg2_error_loop
+	li x5, 0x22
+	bne x5, x18, reg2_error_loop
+	li x5, 0x23
+	bne x5, x19, reg2_error_loop
+	li x5, 0x24
+	bne x5, x20, reg2_error_loop
+	li x5, 0x25
+	bne x5, x21, reg2_error_loop
+	li x5, 0x26
+	bne x5, x22, reg2_error_loop
+	li x5, 0x27
+	bne x5, x23, reg2_error_loop
+	li x5, 0x28
+	bne x5, x24, reg2_error_loop
+	li x5, 0x29
+	bne x5, x25, reg2_error_loop
+	li x5, 0x2a
+	bne x5, x26, reg2_error_loop
+	li x5, 0x2b
+	bne x5, x27, reg2_error_loop
+	li x5, 0x2c
+	bne x5, x28, reg2_error_loop
+	li x5, 0x2d
+	bne x5, x29, reg2_error_loop
+	li x5, 0x2e
+	bne x5, x30, reg2_error_loop
+	li x5, 0x2f
+	bne x5, x31, reg2_error_loop
+
+	/* Everything passed, increment the loop counter. */
+	lw x5, ulRegTest2LoopCounterConst
+	lw x6, 0(x5)
+	addi x6, x6, 1
+	sw x6, 0(x5)
+
+	/* Restore clobbered register reading for next loop. */
+	li x6, 0x61
+
+	/* Start again. */
+	jal Reg2_loop
+
+reg2_error_loop:
+	/* Jump here if a register contains an uxpected value.  This stops the loop
+	counter being incremented so the check task knows an error was found. */
+	jal reg2_error_loop
+
+ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/full_demo/main_full.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/full_demo/main_full.c
new file mode 100644
index 0000000..53f79d9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/full_demo/main_full.c
@@ -0,0 +1,479 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/******************************************************************************
+ * NOTE 1:  This project provides two demo applications.  A simple blinky style
+ * project, and a more comprehensive test and demo application.  The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
+ * between the two.  See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
+ * in main.c.  This file implements the comprehensive test and demo version.
+ *
+ * NOTE 2:  This file only contains the source code that is specific to the
+ * full demo.  Generic functions, such FreeRTOS hook functions, and functions
+ * required to configure the hardware, are defined in main.c.
+ *
+ ******************************************************************************
+ *
+ * main_full() creates all the demo application tasks and software timers, then
+ * starts the scheduler.  The web documentation provides more details of the
+ * standard demo application tasks, which provide no particular functionality,
+ * but do provide a good example of how to use the FreeRTOS API.
+ *
+ * In addition to the standard demo tasks, the following tasks and tests are
+ * defined and/or created within this file:
+ *
+ * "Reg test" tasks - These fill both the core registers with known values, then
+ * check that each register maintains its expected value for the lifetime of the
+ * task.  Each task uses a different set of values.  The reg test tasks execute
+ * with a very low priority, so get preempted very frequently.  A register
+ * containing an unexpected value is indicative of an error in the context
+ * switching mechanism.
+ *
+ * "Check" task - The check executes every three seconds.  It checks that all
+ * the standard demo tasks, and the register check tasks, are not only still
+ * executing, but are executing without reporting any errors.  If the check task
+ * discovers that a task has either stalled, or reported an error, then it
+ * prints an error message to the UART, otherwise it prints "Pass.".
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "semphr.h"
+
+/* Microsemi incldues. */
+#include "core_timer.h"
+#include "riscv_hal.h"
+
+/* Standard demo application includes. */
+#include "dynamic.h"
+#include "blocktim.h"
+#include "GenQTest.h"
+#include "recmutex.h"
+#include "TimerDemo.h"
+#include "EventGroupsDemo.h"
+#include "TaskNotify.h"
+#include "AbortDelay.h"
+#include "countsem.h"
+#include "death.h"
+#include "MessageBufferDemo.h"
+#include "StreamBufferDemo.h"
+#include "StreamBufferInterrupt.h"
+
+/* Priorities for the demo application tasks. */
+#define mainCHECK_TASK_PRIORITY				( configMAX_PRIORITIES - 1 )
+#define mainCREATOR_TASK_PRIORITY			( tskIDLE_PRIORITY + 3UL )
+
+/* The period of the check task, in ms, converted to ticks using the
+pdMS_TO_TICKS() macro.  mainNO_ERROR_CHECK_TASK_PERIOD is used if no errors have
+been found, mainERROR_CHECK_TASK_PERIOD is used if an error has been found. */
+#define mainNO_ERROR_CHECK_TASK_PERIOD		pdMS_TO_TICKS( 3000UL )
+#define mainERROR_CHECK_TASK_PERIOD		pdMS_TO_TICKS( 500UL )
+
+/* Parameters that are passed into the register check tasks solely for the
+purpose of ensuring parameters are passed into tasks correctly. */
+#define mainREG_TEST_TASK_1_PARAMETER		( ( void * ) 0x12345678 )
+#define mainREG_TEST_TASK_2_PARAMETER		( ( void * ) 0x87654321 )
+
+/* The base period used by the timer test tasks. */
+#define mainTIMER_TEST_PERIOD				( 50 )
+
+/* The size of the stack allocated to the check task (as described in the
+comments at the top of this file. */
+#define mainCHECK_TASK_STACK_SIZE_WORDS 100
+
+/* Size of the stacks to allocated for the register check tasks. */
+#define mainREG_TEST_STACK_SIZE_WORDS 70
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by main() to run the full demo (as opposed to the blinky demo) when
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
+ */
+void main_full( void );
+
+/*
+ * The check task, as described at the top of this file.
+ */
+static void prvCheckTask( void *pvParameters );
+
+/*
+ * Initialise and start the peripheral timers that are used to exercise external
+ * interrupt processing.
+ */
+static void prvSetupPeripheralTimers( void );
+
+/*
+ * Register check tasks as described at the top of this file.  The nature of
+ * these files necessitates that they are written in an assembly file, but the
+ * entry points are kept in the C file for the convenience of checking the task
+ * parameter.
+ */
+static void prvRegTestTaskEntry1( void *pvParameters );
+extern void vRegTest1Implementation( void );
+static void prvRegTestTaskEntry2( void *pvParameters );
+extern void vRegTest2Implementation( void );
+
+/*
+ * Tick hook used by the full demo, which includes code that interacts with
+ * some of the tests.
+ */
+void vFullDemoTickHook( void );
+
+/*-----------------------------------------------------------*/
+
+/* Timers used to exercise external interrupt processing. */
+static timer_instance_t g_timer0, g_timer1;
+
+/* Variables incremented by the peripheral timers used to exercise external
+interrupts. */
+volatile uint32_t ulTimer0Interrupts = 0, ulTimer1Interrupts = 0;
+
+/* The following two variables are used to communicate the status of the
+register check tasks to the check task.  If the variables keep incrementing,
+then the register check tasks have not discovered any errors.  If a variable
+stops incrementing, then an error has been found. */
+volatile uint32_t ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
+
+/*-----------------------------------------------------------*/
+
+void main_full( void )
+{
+	/* Start all the other standard demo/test tasks.  They have no particular
+	functionality, but do demonstrate how to use the FreeRTOS API and test the
+	kernel port. */
+	vStartDynamicPriorityTasks();
+	vCreateBlockTimeTasks();
+	vStartGenericQueueTasks( tskIDLE_PRIORITY );
+	vStartRecursiveMutexTasks();
+	vStartTimerDemoTask( mainTIMER_TEST_PERIOD );
+	vStartEventGroupTasks();
+	vStartTaskNotifyTask();
+	vCreateAbortDelayTasks();
+	vStartCountingSemaphoreTasks();
+	vStartMessageBufferTasks( configMINIMAL_STACK_SIZE  );
+	vStartStreamBufferTasks();
+	vStartStreamBufferInterruptDemo();
+
+	/* Create the register check tasks, as described at the top of this	file.
+	Use xTaskCreateStatic() to create a task using only statically allocated
+	memory. */
+	xTaskCreate( prvRegTestTaskEntry1, 			/* The function that implements the task. */
+				 "Reg1", 						/* The name of the task. */
+				 mainREG_TEST_STACK_SIZE_WORDS, /* Size of stack to allocate for the task - in words not bytes!. */
+				 mainREG_TEST_TASK_1_PARAMETER, /* Parameter passed into the task. */
+				 tskIDLE_PRIORITY, 				/* Priority of the task. */
+				 NULL );						/* Can be used to pass out a handle to the created task. */
+	xTaskCreate( prvRegTestTaskEntry2, "Reg2", mainREG_TEST_STACK_SIZE_WORDS, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL );
+
+	/* Create the task that performs the 'check' functionality,	as described at
+	the top of this file. */
+	xTaskCreate( prvCheckTask, "Check", mainCHECK_TASK_STACK_SIZE_WORDS, NULL, mainCHECK_TASK_PRIORITY, NULL );
+
+	/* The set of tasks created by the following function call have to be
+	created last as they keep account of the number of tasks they expect to see
+	running. */
+	vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
+
+	/* Start the timers that are used to exercise external interrupt handling. */
+	prvSetupPeripheralTimers();
+
+	/* Start the scheduler. */
+	vTaskStartScheduler();
+
+	/* If all is well, the scheduler will now be running, and the following
+	line will never be reached.  If the following line does execute, then
+	there was insufficient FreeRTOS heap memory available for the Idle and/or
+	timer tasks to be created.  See the memory management section on the
+	FreeRTOS web site for more details on the FreeRTOS heap
+	http://www.freertos.org/a00111.html. */
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTask( void *pvParameters )
+{
+TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;
+TickType_t xLastExecutionTime;
+uint32_t ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
+uint32_t ulLastTimer0Interrupts = 0, ulLastTimer1Interrupts = 0;
+char * const pcPassMessage = ".";
+char * pcStatusMessage = pcPassMessage;
+extern void vSendString( const char * const pcString );
+extern void vToggleLED( void );
+
+	/* Just to stop compiler warnings. */
+	( void ) pvParameters;
+
+	/* Start with a pass message, after which a '.' character will be printed
+	out on each successful loop. */
+	vSendString( "Pass" );
+
+	/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
+	works correctly. */
+	xLastExecutionTime = xTaskGetTickCount();
+
+	/* Cycle for ever, delaying then checking all the other tasks are still
+	operating without error.  The onboard LED is toggled on each iteration.
+	If an error is detected then the delay period is decreased from
+	mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD.  This has the
+	effect of increasing the rate at which the onboard LED toggles, and in so
+	doing gives visual feedback of the system status. */
+	for( ;; )
+	{
+		/* Delay until it is time to execute again. */
+		vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );
+
+		/* Check all the demo tasks (other than the flash tasks) to ensure
+		that they are all still running, and that none have detected an error. */
+		if( xAreDynamicPriorityTasksStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Dynamic priority demo/tests.\r\n";
+		}
+
+		if( xAreBlockTimeTestTasksStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Block time demo/tests.\r\n";
+		}
+
+		if( xAreGenericQueueTasksStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Generic queue demo/tests.\r\n";
+		}
+
+		if( xAreRecursiveMutexTasksStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Recursive mutex demo/tests.\r\n";
+		}
+
+		if( xAreTimerDemoTasksStillRunning( ( TickType_t ) xDelayPeriod ) == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Timer demo/tests.\r\n";
+		}
+
+		if( xAreEventGroupTasksStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Event group demo/tests.\r\n";
+		}
+
+		if( xAreTaskNotificationTasksStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Task notification demo/tests.\r\n";
+		}
+
+		if( xAreAbortDelayTestTasksStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Abort delay.\r\n";
+		}
+
+		if( xAreCountingSemaphoreTasksStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Counting semaphores.\r\n";
+		}
+
+		if( xIsCreateTaskStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Suicide tasks.\r\n";
+		}
+
+		if( xAreMessageBufferTasksStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Message buffer.\r\n";
+		}
+
+		if( xAreStreamBufferTasksStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Stream buffer.\r\n";
+		}
+
+		if( xIsInterruptStreamBufferDemoStillRunning() == pdFALSE )
+		{
+			pcStatusMessage = "ERROR: Stream buffer interrupt.\r\n";
+		}
+
+		/* Check that the register test 1 task is still running. */
+		if( ulLastRegTest1Value == ulRegTest1LoopCounter )
+		{
+			pcStatusMessage = "ERROR: Register test 1.\r\n";
+		}
+		ulLastRegTest1Value = ulRegTest1LoopCounter;
+
+		/* Check that the register test 2 task is still running. */
+		if( ulLastRegTest2Value == ulRegTest2LoopCounter )
+		{
+			pcStatusMessage = "ERROR: Register test 2.\r\n";
+		}
+		ulLastRegTest2Value = ulRegTest2LoopCounter;
+
+		/* Check interrupts from the peripheral timers are being handled. */
+		if( ulLastTimer0Interrupts == ulTimer0Interrupts )
+		{
+			pcStatusMessage = "ERROR: Peripheral timer 0.\r\n";
+		}
+		ulLastTimer0Interrupts = ulTimer0Interrupts;
+
+		if( ulLastTimer1Interrupts == ulTimer1Interrupts )
+		{
+			pcStatusMessage = "ERROR: Peripheral timer 1.\r\n";
+		}
+		ulLastTimer1Interrupts = ulTimer1Interrupts;
+
+		/* Write the status message to the UART. */
+		vSendString( pcStatusMessage );
+
+		/* If an error has been found then increase the LED toggle rate by
+		increasing the cycle frequency. */
+		if( pcStatusMessage != pcPassMessage )
+		{
+			xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTestTaskEntry1( void *pvParameters )
+{
+	/* Although the regtest task is written in assembler, its entry point is
+	written in C for convenience of checking the task parameter is being passed
+	in correctly. */
+	if( pvParameters == mainREG_TEST_TASK_1_PARAMETER )
+	{
+		/* Start the part of the test that is written in assembler. */
+		vRegTest1Implementation();
+	}
+
+	/* The following line will only execute if the task parameter is found to
+	be incorrect.  The check task will detect that the regtest loop counter is
+	not being incremented and flag an error. */
+	vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTestTaskEntry2( void *pvParameters )
+{
+	/* Although the regtest task is written in assembler, its entry point is
+	written in C for convenience of checking the task parameter is being passed
+	in correctly. */
+	if( pvParameters == mainREG_TEST_TASK_2_PARAMETER )
+	{
+		/* Start the part of the test that is written in assembler. */
+		vRegTest2Implementation();
+	}
+
+	/* The following line will only execute if the task parameter is found to
+	be incorrect.  The check task will detect that the regtest loop counter is
+	not being incremented and flag an error. */
+	vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+void vFullDemoTickHook( void )
+{
+	/* The full demo includes a software timer demo/test that requires
+	prodding periodically from the tick interrupt. */
+	vTimerPeriodicISRTests();
+
+	/* Call the periodic event group from ISR demo. */
+	vPeriodicEventGroupsProcessing();
+
+	/* Use task notifications from an interrupt. */
+	xNotifyTaskFromISR();
+
+	/* Writes to stream buffer byte by byte to test the stream buffer trigger
+	level functionality. */
+	vPeriodicStreamBufferProcessing();
+
+	/* Writes a string to a string buffer four bytes at a time to demonstrate
+	a stream being sent from an interrupt to a task. */
+	vBasicStreamBufferSendFromISR();
+
+	/* Called from vApplicationTickHook() when the project is configured to
+	build the full test/demo applications. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupPeripheralTimers( void )
+{
+	TMR_init( 	&g_timer0,
+				CORETIMER0_BASE_ADDR,
+				TMR_CONTINUOUS_MODE,
+				PRESCALER_DIV_1024,
+				83000 );
+
+    TMR_init( 	&g_timer1,
+				CORETIMER1_BASE_ADDR,
+				TMR_CONTINUOUS_MODE,
+				PRESCALER_DIV_512,
+				42000 );
+
+	/* In this version of the PLIC, the priorities are fixed at 1.
+	Lower numbered devices have higher priorities. But this code is given as
+	an example.
+	*/
+	PLIC_SetPriority( External_30_IRQn, 1 );
+	PLIC_SetPriority( External_31_IRQn, 1 );
+
+	/*Enable Timer 1 & 0 Interrupt*/
+	PLIC_EnableIRQ( External_30_IRQn );
+	PLIC_EnableIRQ( External_31_IRQn );
+
+	/* Enable the timers */
+	TMR_enable_int( &g_timer0 );
+	TMR_enable_int( &g_timer1 );
+
+	/* Make sure timers don't interrupt until the scheduler is running. */
+	portDISABLE_INTERRUPTS();
+
+	/*Start the timer*/
+	TMR_start( &g_timer0 );
+	TMR_start( &g_timer1 );
+}
+/*-----------------------------------------------------------*/
+
+/*Core Timer 0 Interrupt Handler*/
+uint8_t External_30_IRQHandler( void )
+{
+	ulTimer0Interrupts++;
+    TMR_clear_int(&g_timer0);
+    return( EXT_IRQ_KEEP_ENABLED );
+}
+/*-----------------------------------------------------------*/
+
+/*Core Timer 1 Interrupt Handler*/
+uint8_t External_31_IRQHandler( void )
+{
+	ulTimer1Interrupts++;
+    TMR_clear_int(&g_timer1);
+
+    return( EXT_IRQ_KEEP_ENABLED );
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/hw_platform.h b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/hw_platform.h
new file mode 100644
index 0000000..c945d59
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/hw_platform.h
@@ -0,0 +1,119 @@
+/*******************************************************************************
+ * (c) Copyright 2016-2017 Microsemi Corporation.  All rights reserved.
+ *
+ * Platform definitions
+ * Version based on requirements of RISCV-HAL
+ *
+ * SVN $Revision: 9587 $
+ * SVN $Date: 2017-11-16 12:53:31 +0530 (Thu, 16 Nov 2017) $
+ */
+ /*=========================================================================*//**
+  @mainpage Sample file detailing how hw_platform.h should be constructed for 
+    the Mi-V processors.
+
+    @section intro_sec Introduction
+    The hw_platform.h is to be located in the project root directory.
+    Currently this file must be hand crafted when using the Mi-V Soft Processor.
+    
+    You can use this file as sample.
+    Rename this file from sample_hw_platform.h to hw_platform.h and store it in
+    the root folder of your project. Then customize it per your HW design.
+
+    @section driver_configuration Project configuration Instructions
+    1. Change SYS_CLK_FREQ define to frequency of Mi-V Soft processor clock
+    2  Add all other core BASE addresses
+    3. Add peripheral Core Interrupt to Mi-V Soft processor interrupt mappings
+    4. Define MSCC_STDIO_UART_BASE_ADDR if you want a CoreUARTapb mapped to STDIO
+*//*=========================================================================*/
+
+#ifndef HW_PLATFORM_H
+#define HW_PLATFORM_H
+
+/***************************************************************************//**
+ * Soft-processor clock definition
+ * This is the only clock brought over from the Mi-V Soft processor Libero design.
+ */
+#ifndef SYS_CLK_FREQ
+#define SYS_CLK_FREQ                    66000000UL
+#endif
+
+/***************************************************************************//**
+ * Non-memory Peripheral base addresses
+ * Format of define is:
+ * __BASE_ADDR
+ */
+#define COREUARTAPB0_BASE_ADDR          0x70001000UL
+#define COREGPIO_IN_BASE_ADDR           0x70002000UL
+#define CORETIMER0_BASE_ADDR            0x70003000UL
+#define CORETIMER1_BASE_ADDR            0x70004000UL
+#define COREGPIO_OUT_BASE_ADDR          0x70005000UL
+#define FLASH_CORE_SPI_BASE             0x70006000UL
+#define CORE16550_BASE_ADDR             0x70007000UL
+
+/***************************************************************************//**
+ * Peripheral Interrupts are mapped to the corresponding Mi-V Soft processor
+ * interrupt from the Libero design.
+ * There can be up to 31 external interrupts (IRQ[30:0] pins) on the Mi-V Soft
+ * processor.The Mi-V Soft processor external interrupts are defined in the
+ * riscv_plic.h
+ * These are of the form
+ * typedef enum
+{
+    NoInterrupt_IRQn = 0,
+    External_1_IRQn  = 1,
+    External_2_IRQn  = 2,
+    .
+    .
+    .
+    External_31_IRQn = 31
+} IRQn_Type;
+ 
+ The interrupt 0 on RISC-V processor is not used. The pin IRQ[0] should map to
+ External_1_IRQn likewise IRQ[30] should map to External_31_IRQn
+ * Format of define is:
+ * __
+ */
+
+#define TIMER0_IRQn                     External_30_IRQn
+#define TIMER1_IRQn                     External_31_IRQn
+
+/****************************************************************************
+ * Baud value to achieve a 115200 baud rate with a 83MHz system clock.
+ * This value is calculated using the following equation:
+ *      BAUD_VALUE = (CLOCK / (16 * BAUD_RATE)) - 1
+ *****************************************************************************/
+#define BAUD_VALUE_115200               (SYS_CLK_FREQ / (16 * 115200)) - 1
+
+/***************************************************************************//**
+ * User edit section- Edit sections below if required
+ */
+#ifdef MSCC_STDIO_THRU_CORE_UART_APB
+/*
+ * A base address mapping for the STDIO printf/scanf mapping to CortUARTapb
+ * must be provided if it is being used
+ *
+ * e.g. #define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB1_BASE_ADDR
+ */
+#define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB0_BASE_ADDR
+
+#ifndef MSCC_STDIO_UART_BASE_ADDR
+#error MSCC_STDIO_UART_BASE_ADDR not defined- e.g. #define MSCC_STDIO_UART_BASE_ADDR COREUARTAPB1_BASE_ADDR
+#endif
+
+#ifndef MSCC_STDIO_BAUD_VALUE
+/*
+ * The MSCC_STDIO_BAUD_VALUE define should be set in your project's settings to
+ * specify the baud value used by the standard output CoreUARTapb instance for
+ * generating the UART's baud rate if you want a different baud rate from the
+ * default of 115200 baud
+ */
+#define MSCC_STDIO_BAUD_VALUE           115200
+#endif  /*MSCC_STDIO_BAUD_VALUE*/
+
+#endif  /* end of MSCC_STDIO_THRU_CORE_UART_APB */
+/*******************************************************************************
+ * End of user edit section
+ */
+#endif /* HW_PLATFORM_H */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/main.c b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/main.c
new file mode 100644
index 0000000..700421c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/main.c
@@ -0,0 +1,185 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* FreeRTOS kernel includes. */
+#include 
+#include 
+
+/* Microsemi includes. */
+#include "core_uart_apb.h"
+#include "core_gpio.h"
+
+/******************************************************************************
+ * This project provides two demo applications.  A simple blinky style project,
+ * and a more comprehensive test and demo application.  The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to
+ * select between the two.  The simply blinky demo is implemented and described
+ * in main_blinky.c.  The more comprehensive test and demo application is
+ * implemented and described in main_full.c.
+ *
+ * This file implements the code that is not demo specific, including the
+ * hardware setup and standard FreeRTOS hook functions.
+ *
+ * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON
+ * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO
+ * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!
+ *
+ */
+
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
+or 0 to run the more comprehensive test and demo application. */
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY	0
+
+/*
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
+ */
+#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1
+	extern void main_blinky( void );
+#else
+	extern void main_full( void );
+#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */
+
+/* Prototypes for the standard FreeRTOS callback/hook functions implemented
+within this file.  See https://www.freertos.org/a00016.html */
+void vApplicationMallocFailedHook( void );
+void vApplicationIdleHook( void );
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );
+void vApplicationTickHook( void );
+
+/* Prepare haredware to run the demo. */
+static void prvSetupHardware( void );
+
+/* Send a messaage to the UART initialised in prvSetupHardware. */
+void vSendString( const char * const pcString );
+
+/*-----------------------------------------------------------*/
+
+/* The UART to which strings are output, and the GPIO used to toggle the LED. */
+static UART_instance_t g_uart;
+static gpio_instance_t g_gpio_out;
+
+/*-----------------------------------------------------------*/
+
+int main( void )
+{
+	prvSetupHardware();
+
+	/* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top
+	of this file. */
+	#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )
+	{
+		main_blinky();
+	}
+	#else
+	{
+		main_full();
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupHardware( void )
+{
+	PLIC_init();
+	UART_init( &g_uart, COREUARTAPB0_BASE_ADDR, BAUD_VALUE_115200, ( DATA_8_BITS | NO_PARITY ) );
+}
+/*-----------------------------------------------------------*/
+
+void vToggleLED( void )
+{
+static uint32_t ulLEDState = 0;
+
+	GPIO_set_outputs( &g_gpio_out, ulLEDState );
+	ulLEDState = !ulLEDState;
+}
+/*-----------------------------------------------------------*/
+
+void vSendString( const char * const pcString )
+{
+	UART_polled_tx_string( &g_uart, pcString );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationMallocFailedHook( void )
+{
+	/* vApplicationMallocFailedHook() will only be called if
+	configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h.  It is a hook
+	function that will get called if a call to pvPortMalloc() fails.
+	pvPortMalloc() is called internally by the kernel whenever a task, queue,
+	timer or semaphore is created.  It is also called by various parts of the
+	demo application.  If heap_1.c or heap_2.c are used, then the size of the
+	heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
+	FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
+	to query the size of free heap space that remains (although it does not
+	provide information on how the remaining heap might be fragmented). */
+	taskDISABLE_INTERRUPTS();
+	__asm volatile( "ebreak" );
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+	/* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
+	to 1 in FreeRTOSConfig.h.  It will be called on each iteration of the idle
+	task.  It is essential that code added to this hook function never attempts
+	to block in any way (for example, call xQueueReceive() with a block time
+	specified, or call vTaskDelay()).  If the application makes use of the
+	vTaskDelete() API function (as this demo application does) then it is also
+	important that vApplicationIdleHook() is permitted to return to its calling
+	function, because it is the responsibility of the idle task to clean up
+	memory allocated by the kernel to any task that has since been deleted. */
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
+{
+	( void ) pcTaskName;
+	( void ) pxTask;
+
+	/* Run time stack overflow checking is performed if
+	configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2.  This hook
+	function is called if a stack overflow is detected. */
+	taskDISABLE_INTERRUPTS();
+	__asm volatile( "ebreak" );
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationTickHook( void )
+{
+	/* The tests in the full demo expect some interaction with interrupts. */
+	#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 )
+	{
+		extern void vFullDemoTickHook( void );
+		vFullDemoTickHook();
+	}
+	#endif
+}
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/microsemi-riscv-renode.ld b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/microsemi-riscv-renode.ld
new file mode 100644
index 0000000..6b08b83
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/microsemi-riscv-renode.ld
@@ -0,0 +1,139 @@
+/*******************************************************************************
+ * (c) Copyright 2016-2018 Microsemi SoC Products Group.  All rights reserved.
+ *
+ * file name : microsemi-riscv-ram.ld
+ * Mi-V soft processor linker script for creating a SoftConsole downloadable
+ * debug image executing in SRAM.
+ *
+ * This linker script assumes that the SRAM is connected at on the Mi-V soft
+ * processor memory space. The start address and size of the memory space must
+ * be correct as per the Libero design.
+ *
+ * SVN $Revision: 9661 $
+ * SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
+ */
+
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+
+MEMORY
+{
+    ram (rwx) : ORIGIN = 0x80000000, LENGTH = 512k
+}
+
+RAM_START_ADDRESS   = 0x80000000;       /* Must be the same value MEMORY region ram ORIGIN above. */
+RAM_SIZE            = 512k;              /* Must be the same value MEMORY region ram LENGTH above. */
+STACK_SIZE          = 2k;               /* needs to be calculated for your application */
+HEAP_SIZE           = 4;               /* needs to be calculated for your application */
+
+SECTIONS
+{
+  .text : ALIGN(0x10)
+  {
+    KEEP (*(SORT_NONE(.text.entry)))
+    . = ALIGN(0x10);
+    *(.text .text.* .gnu.linkonce.t.*)
+    *(.plt)
+    . = ALIGN(0x10);
+
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*crtend.o(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*crtend.o(.dtors))
+
+    *(.rodata .rodata.* .gnu.linkonce.r.*)
+    *(.gcc_except_table)
+    *(.eh_frame_hdr)
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(0x10);
+
+  } > ram
+
+  /* short/global data section */
+  .sdata : ALIGN(0x10)
+  {
+    __sdata_load = LOADADDR(.sdata);
+    __sdata_start = .;
+    PROVIDE( __global_pointer$ = . + 0x800);
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+    *(.srodata*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+    . = ALIGN(0x10);
+    __sdata_end = .;
+  } > ram
+
+  /* data section */
+  .data : ALIGN(0x10)
+  {
+    __data_load = LOADADDR(.data);
+    __data_start = .;
+    *(.got.plt) *(.got)
+    *(.shdata)
+    *(.data .data.* .gnu.linkonce.d.*)
+    . = ALIGN(0x10);
+    __data_end = .;
+  } > ram
+
+  /* sbss section */
+  .sbss : ALIGN(0x10)
+  {
+    __sbss_start = .;
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+    . = ALIGN(0x10);
+    __sbss_end = .;
+  } > ram
+
+  /* sbss section */
+  .bss : ALIGN(0x10)
+  {
+    __bss_start = .;
+    *(.shbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(0x10);
+    __bss_end = .;
+  } > ram
+
+  /* End of uninitialized data segment */
+  _end = .;
+
+  .heap : ALIGN(0x10)
+  {
+    __heap_start = .;
+    . += HEAP_SIZE;
+    __heap_end = .;
+    . = ALIGN(0x10);
+    _heap_end = __heap_end;
+  } > ram
+
+  .stack : ALIGN(0x10)
+  {
+    __stack_bottom = .;
+    . += STACK_SIZE;
+    __stack_top = .;
+    _sp = .;
+	__freertos_irq_stack_top = .;
+  } > ram
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Demo/readme.txt b/FreeRTOSv10.2.1/FreeRTOS/Demo/readme.txt
new file mode 100644
index 0000000..8a744ff
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Demo/readme.txt
@@ -0,0 +1,19 @@
+Links to a documentation page for each demo are provided on the following
+URL: http://www.freertos.org/a00090.html
+
+Each RTOS port has a demo application to demonstrate it's use.
+
++ The Demo/Common directory contains the demo application files as described on 
+the http://www.FreeRTOS.org WEB site.  Each file creates one or more tasks.
+The files in the Demo/Common directory are used by every demo application for
+every port.
+
++ All the other directories contain a project or makefile for the demo
+application targeted at a particular microcontroller.  
+
+
+For example, if you are interested in the ATMega323 demo application for
+the WinAVR tools then the AVR_ATMega323_WinAVR directory contains the 
+relevant makefile.  The makefile includes files from the Demo/ATMega323 
+and the Demo/Common directories.  If this is the only port you are 
+interested in then all the other directories can be ignored.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/License/license.txt b/FreeRTOSv10.2.1/FreeRTOS/License/license.txt
new file mode 100644
index 0000000..9c59050
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/License/license.txt
@@ -0,0 +1,37 @@
+The FreeRTOS kernel is released under the MIT open source license, the text of
+which is provided below.
+
+This license covers the FreeRTOS kernel source files, which are located in the
+/FreeRTOS/Source directory of the official FreeRTOS kernel download.  It also
+covers most of the source files in the demo application projects, which are
+located in the /FreeRTOS/Demo directory of the official FreeRTOS download.  The
+demo projects may also include third party software that is not part of FreeRTOS
+and is licensed separately to FreeRTOS.  Examples of third party software
+includes header files provided by chip or tools vendors, linker scripts,
+peripheral drivers, etc.  All the software in subdirectories of the /FreeRTOS
+directory is either open source or distributed with permission, and is free for
+use.  For the avoidance of doubt, refer to the comments at the top of each
+source file.
+
+
+License text:
+-------------
+
+Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+the Software, and to permit persons to whom the Software is furnished to do so,
+subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/croutine.c b/FreeRTOSv10.2.1/FreeRTOS/Source/croutine.c
new file mode 100644
index 0000000..565691b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/croutine.c
@@ -0,0 +1,353 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "croutine.h"
+
+/* Remove the whole file is co-routines are not being used. */
+#if( configUSE_CO_ROUTINES != 0 )
+
+/*
+ * Some kernel aware debuggers require data to be viewed to be global, rather
+ * than file scope.
+ */
+#ifdef portREMOVE_STATIC_QUALIFIER
+	#define static
+#endif
+
+
+/* Lists for ready and blocked co-routines. --------------------*/
+static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ];	/*< Prioritised ready co-routines. */
+static List_t xDelayedCoRoutineList1;									/*< Delayed co-routines. */
+static List_t xDelayedCoRoutineList2;									/*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */
+static List_t * pxDelayedCoRoutineList;									/*< Points to the delayed co-routine list currently being used. */
+static List_t * pxOverflowDelayedCoRoutineList;							/*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */
+static List_t xPendingReadyCoRoutineList;								/*< Holds co-routines that have been readied by an external event.  They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */
+
+/* Other file private variables. --------------------------------*/
+CRCB_t * pxCurrentCoRoutine = NULL;
+static UBaseType_t uxTopCoRoutineReadyPriority = 0;
+static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;
+
+/* The initial state of the co-routine when it is created. */
+#define corINITIAL_STATE	( 0 )
+
+/*
+ * Place the co-routine represented by pxCRCB into the appropriate ready queue
+ * for the priority.  It is inserted at the end of the list.
+ *
+ * This macro accesses the co-routine ready lists and therefore must not be
+ * used from within an ISR.
+ */
+#define prvAddCoRoutineToReadyQueue( pxCRCB )																		\
+{																													\
+	if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority )															\
+	{																												\
+		uxTopCoRoutineReadyPriority = pxCRCB->uxPriority;															\
+	}																												\
+	vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) );	\
+}
+
+/*
+ * Utility to ready all the lists used by the scheduler.  This is called
+ * automatically upon the creation of the first co-routine.
+ */
+static void prvInitialiseCoRoutineLists( void );
+
+/*
+ * Co-routines that are readied by an interrupt cannot be placed directly into
+ * the ready lists (there is no mutual exclusion).  Instead they are placed in
+ * in the pending ready list in order that they can later be moved to the ready
+ * list by the co-routine scheduler.
+ */
+static void prvCheckPendingReadyList( void );
+
+/*
+ * Macro that looks at the list of co-routines that are currently delayed to
+ * see if any require waking.
+ *
+ * Co-routines are stored in the queue in the order of their wake time -
+ * meaning once one co-routine has been found whose timer has not expired
+ * we need not look any further down the list.
+ */
+static void prvCheckDelayedList( void );
+
+/*-----------------------------------------------------------*/
+
+BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex )
+{
+BaseType_t xReturn;
+CRCB_t *pxCoRoutine;
+
+	/* Allocate the memory that will store the co-routine control block. */
+	pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );
+	if( pxCoRoutine )
+	{
+		/* If pxCurrentCoRoutine is NULL then this is the first co-routine to
+		be created and the co-routine data structures need initialising. */
+		if( pxCurrentCoRoutine == NULL )
+		{
+			pxCurrentCoRoutine = pxCoRoutine;
+			prvInitialiseCoRoutineLists();
+		}
+
+		/* Check the priority is within limits. */
+		if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES )
+		{
+			uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1;
+		}
+
+		/* Fill out the co-routine control block from the function parameters. */
+		pxCoRoutine->uxState = corINITIAL_STATE;
+		pxCoRoutine->uxPriority = uxPriority;
+		pxCoRoutine->uxIndex = uxIndex;
+		pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode;
+
+		/* Initialise all the other co-routine control block parameters. */
+		vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) );
+		vListInitialiseItem( &( pxCoRoutine->xEventListItem ) );
+
+		/* Set the co-routine control block as a link back from the ListItem_t.
+		This is so we can get back to the containing CRCB from a generic item
+		in a list. */
+		listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine );
+		listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine );
+
+		/* Event lists are always in priority order. */
+		listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) );
+
+		/* Now the co-routine has been initialised it can be added to the ready
+		list at the correct priority. */
+		prvAddCoRoutineToReadyQueue( pxCoRoutine );
+
+		xReturn = pdPASS;
+	}
+	else
+	{
+		xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList )
+{
+TickType_t xTimeToWake;
+
+	/* Calculate the time to wake - this may overflow but this is
+	not a problem. */
+	xTimeToWake = xCoRoutineTickCount + xTicksToDelay;
+
+	/* We must remove ourselves from the ready list before adding
+	ourselves to the blocked list as the same list item is used for
+	both lists. */
+	( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+
+	/* The list item will be inserted in wake time order. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake );
+
+	if( xTimeToWake < xCoRoutineTickCount )
+	{
+		/* Wake time has overflowed.  Place this item in the
+		overflow list. */
+		vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+	}
+	else
+	{
+		/* The wake time has not overflowed, so we can use the
+		current block list. */
+		vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+	}
+
+	if( pxEventList )
+	{
+		/* Also add the co-routine to an event list.  If this is done then the
+		function must be called with interrupts disabled. */
+		vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckPendingReadyList( void )
+{
+	/* Are there any co-routines waiting to get moved to the ready list?  These
+	are co-routines that have been readied by an ISR.  The ISR cannot access
+	the	ready lists itself. */
+	while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE )
+	{
+		CRCB_t *pxUnblockedCRCB;
+
+		/* The pending ready list can be accessed by an ISR. */
+		portDISABLE_INTERRUPTS();
+		{
+			pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyCoRoutineList) );
+			( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
+		}
+		portENABLE_INTERRUPTS();
+
+		( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) );
+		prvAddCoRoutineToReadyQueue( pxUnblockedCRCB );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckDelayedList( void )
+{
+CRCB_t *pxCRCB;
+
+	xPassedTicks = xTaskGetTickCount() - xLastTickCount;
+	while( xPassedTicks )
+	{
+		xCoRoutineTickCount++;
+		xPassedTicks--;
+
+		/* If the tick count has overflowed we need to swap the ready lists. */
+		if( xCoRoutineTickCount == 0 )
+		{
+			List_t * pxTemp;
+
+			/* Tick count has overflowed so we need to swap the delay lists.  If there are
+			any items in pxDelayedCoRoutineList here then there is an error! */
+			pxTemp = pxDelayedCoRoutineList;
+			pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList;
+			pxOverflowDelayedCoRoutineList = pxTemp;
+		}
+
+		/* See if this tick has made a timeout expire. */
+		while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE )
+		{
+			pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList );
+
+			if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) )
+			{
+				/* Timeout not yet expired. */
+				break;
+			}
+
+			portDISABLE_INTERRUPTS();
+			{
+				/* The event could have occurred just before this critical
+				section.  If this is the case then the generic list item will
+				have been moved to the pending ready list and the following
+				line is still valid.  Also the pvContainer parameter will have
+				been set to NULL so the following lines are also valid. */
+				( void ) uxListRemove( &( pxCRCB->xGenericListItem ) );
+
+				/* Is the co-routine waiting on an event also? */
+				if( pxCRCB->xEventListItem.pxContainer )
+				{
+					( void ) uxListRemove( &( pxCRCB->xEventListItem ) );
+				}
+			}
+			portENABLE_INTERRUPTS();
+
+			prvAddCoRoutineToReadyQueue( pxCRCB );
+		}
+	}
+
+	xLastTickCount = xCoRoutineTickCount;
+}
+/*-----------------------------------------------------------*/
+
+void vCoRoutineSchedule( void )
+{
+	/* See if any co-routines readied by events need moving to the ready lists. */
+	prvCheckPendingReadyList();
+
+	/* See if any delayed co-routines have timed out. */
+	prvCheckDelayedList();
+
+	/* Find the highest priority queue that contains ready co-routines. */
+	while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) )
+	{
+		if( uxTopCoRoutineReadyPriority == 0 )
+		{
+			/* No more co-routines to check. */
+			return;
+		}
+		--uxTopCoRoutineReadyPriority;
+	}
+
+	/* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines
+	 of the	same priority get an equal share of the processor time. */
+	listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) );
+
+	/* Call the co-routine. */
+	( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );
+
+	return;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseCoRoutineLists( void )
+{
+UBaseType_t uxPriority;
+
+	for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ )
+	{
+		vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) );
+	}
+
+	vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 );
+	vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 );
+	vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList );
+
+	/* Start with pxDelayedCoRoutineList using list1 and the
+	pxOverflowDelayedCoRoutineList using list2. */
+	pxDelayedCoRoutineList = &xDelayedCoRoutineList1;
+	pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList )
+{
+CRCB_t *pxUnblockedCRCB;
+BaseType_t xReturn;
+
+	/* This function is called from within an interrupt.  It can only access
+	event lists and the pending ready list.  This function assumes that a
+	check has already been made to ensure pxEventList is not empty. */
+	pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
+	( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
+	vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) );
+
+	if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+
+#endif /* configUSE_CO_ROUTINES == 0 */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/event_groups.c b/FreeRTOSv10.2.1/FreeRTOS/Source/event_groups.c
new file mode 100644
index 0000000..81c1965
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/event_groups.c
@@ -0,0 +1,753 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "event_groups.h"
+
+/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */
+
+/* The following bit fields convey control information in a task's event list
+item value.  It is important they don't clash with the
+taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */
+#if configUSE_16_BIT_TICKS == 1
+	#define eventCLEAR_EVENTS_ON_EXIT_BIT	0x0100U
+	#define eventUNBLOCKED_DUE_TO_BIT_SET	0x0200U
+	#define eventWAIT_FOR_ALL_BITS			0x0400U
+	#define eventEVENT_BITS_CONTROL_BYTES	0xff00U
+#else
+	#define eventCLEAR_EVENTS_ON_EXIT_BIT	0x01000000UL
+	#define eventUNBLOCKED_DUE_TO_BIT_SET	0x02000000UL
+	#define eventWAIT_FOR_ALL_BITS			0x04000000UL
+	#define eventEVENT_BITS_CONTROL_BYTES	0xff000000UL
+#endif
+
+typedef struct EventGroupDef_t
+{
+	EventBits_t uxEventBits;
+	List_t xTasksWaitingForBits;		/*< List of tasks waiting for a bit to be set. */
+
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxEventGroupNumber;
+	#endif
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+} EventGroup_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Test the bits set in uxCurrentEventBits to see if the wait condition is met.
+ * The wait condition is defined by xWaitForAllBits.  If xWaitForAllBits is
+ * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor
+ * are also set in uxCurrentEventBits.  If xWaitForAllBits is pdFALSE then the
+ * wait condition is met if any of the bits set in uxBitsToWait for are also set
+ * in uxCurrentEventBits.
+ */
+static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer )
+	{
+	EventGroup_t *pxEventBits;
+
+		/* A StaticEventGroup_t object must be provided. */
+		configASSERT( pxEventGroupBuffer );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticEventGroup_t equals the size of the real
+			event group structure. */
+			volatile size_t xSize = sizeof( StaticEventGroup_t );
+			configASSERT( xSize == sizeof( EventGroup_t ) );
+		} /*lint !e529 xSize is referenced if configASSERT() is defined. */
+		#endif /* configASSERT_DEFINED */
+
+		/* The user has provided a statically allocated event group - use it. */
+		pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */
+
+		if( pxEventBits != NULL )
+		{
+			pxEventBits->uxEventBits = 0;
+			vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
+
+			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+			{
+				/* Both static and dynamic allocation can be used, so note that
+				this event group was created statically in case the event group
+				is later deleted. */
+				pxEventBits->ucStaticallyAllocated = pdTRUE;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			traceEVENT_GROUP_CREATE( pxEventBits );
+		}
+		else
+		{
+			/* xEventGroupCreateStatic should only ever be called with
+			pxEventGroupBuffer pointing to a pre-allocated (compile time
+			allocated) StaticEventGroup_t variable. */
+			traceEVENT_GROUP_CREATE_FAILED();
+		}
+
+		return pxEventBits;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	EventGroupHandle_t xEventGroupCreate( void )
+	{
+	EventGroup_t *pxEventBits;
+
+		/* Allocate the event group.  Justification for MISRA deviation as
+		follows:  pvPortMalloc() always ensures returned memory blocks are
+		aligned per the requirements of the MCU stack.  In this case
+		pvPortMalloc() must return a pointer that is guaranteed to meet the
+		alignment requirements of the EventGroup_t structure - which (if you
+		follow it through) is the alignment requirements of the TickType_t type
+		(EventBits_t being of TickType_t itself).  Therefore, whenever the
+		stack alignment requirements are greater than or equal to the
+		TickType_t alignment requirements the cast is safe.  In other cases,
+		where the natural word size of the architecture is less than
+		sizeof( TickType_t ), the TickType_t variables will be accessed in two
+		or more reads operations, and the alignment requirements is only that
+		of each individual read. */
+		pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */
+
+		if( pxEventBits != NULL )
+		{
+			pxEventBits->uxEventBits = 0;
+			vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* Both static and dynamic allocation can be used, so note this
+				event group was allocated statically in case the event group is
+				later deleted. */
+				pxEventBits->ucStaticallyAllocated = pdFALSE;
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+			traceEVENT_GROUP_CREATE( pxEventBits );
+		}
+		else
+		{
+			traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */
+		}
+
+		return pxEventBits;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait )
+{
+EventBits_t uxOriginalBitValue, uxReturn;
+EventGroup_t *pxEventBits = xEventGroup;
+BaseType_t xAlreadyYielded;
+BaseType_t xTimeoutOccurred = pdFALSE;
+
+	configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+	configASSERT( uxBitsToWaitFor != 0 );
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+	vTaskSuspendAll();
+	{
+		uxOriginalBitValue = pxEventBits->uxEventBits;
+
+		( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );
+
+		if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )
+		{
+			/* All the rendezvous bits are now set - no need to block. */
+			uxReturn = ( uxOriginalBitValue | uxBitsToSet );
+
+			/* Rendezvous always clear the bits.  They will have been cleared
+			already unless this is the only task in the rendezvous. */
+			pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+
+			xTicksToWait = 0;
+		}
+		else
+		{
+			if( xTicksToWait != ( TickType_t ) 0 )
+			{
+				traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );
+
+				/* Store the bits that the calling task is waiting for in the
+				task's event list item so the kernel knows when a match is
+				found.  Then enter the blocked state. */
+				vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );
+
+				/* This assignment is obsolete as uxReturn will get set after
+				the task unblocks, but some compilers mistakenly generate a
+				warning about uxReturn being returned without being set if the
+				assignment is omitted. */
+				uxReturn = 0;
+			}
+			else
+			{
+				/* The rendezvous bits were not set, but no block time was
+				specified - just return the current event bit value. */
+				uxReturn = pxEventBits->uxEventBits;
+				xTimeoutOccurred = pdTRUE;
+			}
+		}
+	}
+	xAlreadyYielded = xTaskResumeAll();
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* The task blocked to wait for its required bits to be set - at this
+		point either the required bits were set or the block time expired.  If
+		the required bits were set they will have been stored in the task's
+		event list item, and they should now be retrieved then cleared. */
+		uxReturn = uxTaskResetEventItemValue();
+
+		if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
+		{
+			/* The task timed out, just return the current event bit value. */
+			taskENTER_CRITICAL();
+			{
+				uxReturn = pxEventBits->uxEventBits;
+
+				/* Although the task got here because it timed out before the
+				bits it was waiting for were set, it is possible that since it
+				unblocked another task has set the bits.  If this is the case
+				then it needs to clear the bits before exiting. */
+				if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )
+				{
+					pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			taskEXIT_CRITICAL();
+
+			xTimeoutOccurred = pdTRUE;
+		}
+		else
+		{
+			/* The task unblocked because the bits were set. */
+		}
+
+		/* Control bits might be set as the task had blocked should not be
+		returned. */
+		uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
+	}
+
+	traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );
+
+	/* Prevent compiler warnings when trace macros are not used. */
+	( void ) xTimeoutOccurred;
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait )
+{
+EventGroup_t *pxEventBits = xEventGroup;
+EventBits_t uxReturn, uxControlBits = 0;
+BaseType_t xWaitConditionMet, xAlreadyYielded;
+BaseType_t xTimeoutOccurred = pdFALSE;
+
+	/* Check the user is not attempting to wait on the bits used by the kernel
+	itself, and that at least one bit is being requested. */
+	configASSERT( xEventGroup );
+	configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+	configASSERT( uxBitsToWaitFor != 0 );
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+	vTaskSuspendAll();
+	{
+		const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;
+
+		/* Check to see if the wait condition is already met or not. */
+		xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );
+
+		if( xWaitConditionMet != pdFALSE )
+		{
+			/* The wait condition has already been met so there is no need to
+			block. */
+			uxReturn = uxCurrentEventBits;
+			xTicksToWait = ( TickType_t ) 0;
+
+			/* Clear the wait bits if requested to do so. */
+			if( xClearOnExit != pdFALSE )
+			{
+				pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else if( xTicksToWait == ( TickType_t ) 0 )
+		{
+			/* The wait condition has not been met, but no block time was
+			specified, so just return the current value. */
+			uxReturn = uxCurrentEventBits;
+			xTimeoutOccurred = pdTRUE;
+		}
+		else
+		{
+			/* The task is going to block to wait for its required bits to be
+			set.  uxControlBits are used to remember the specified behaviour of
+			this call to xEventGroupWaitBits() - for use when the event bits
+			unblock the task. */
+			if( xClearOnExit != pdFALSE )
+			{
+				uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			if( xWaitForAllBits != pdFALSE )
+			{
+				uxControlBits |= eventWAIT_FOR_ALL_BITS;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Store the bits that the calling task is waiting for in the
+			task's event list item so the kernel knows when a match is
+			found.  Then enter the blocked state. */
+			vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );
+
+			/* This is obsolete as it will get set after the task unblocks, but
+			some compilers mistakenly generate a warning about the variable
+			being returned without being set if it is not done. */
+			uxReturn = 0;
+
+			traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );
+		}
+	}
+	xAlreadyYielded = xTaskResumeAll();
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* The task blocked to wait for its required bits to be set - at this
+		point either the required bits were set or the block time expired.  If
+		the required bits were set they will have been stored in the task's
+		event list item, and they should now be retrieved then cleared. */
+		uxReturn = uxTaskResetEventItemValue();
+
+		if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
+		{
+			taskENTER_CRITICAL();
+			{
+				/* The task timed out, just return the current event bit value. */
+				uxReturn = pxEventBits->uxEventBits;
+
+				/* It is possible that the event bits were updated between this
+				task leaving the Blocked state and running again. */
+				if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE )
+				{
+					if( xClearOnExit != pdFALSE )
+					{
+						pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+				xTimeoutOccurred = pdTRUE;
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			/* The task unblocked because the bits were set. */
+		}
+
+		/* The task blocked so control bits may have been set. */
+		uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
+	}
+	traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );
+
+	/* Prevent compiler warnings when trace macros are not used. */
+	( void ) xTimeoutOccurred;
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )
+{
+EventGroup_t *pxEventBits = xEventGroup;
+EventBits_t uxReturn;
+
+	/* Check the user is not attempting to clear the bits used by the kernel
+	itself. */
+	configASSERT( xEventGroup );
+	configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+
+	taskENTER_CRITICAL();
+	{
+		traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );
+
+		/* The value returned is the event group value prior to the bits being
+		cleared. */
+		uxReturn = pxEventBits->uxEventBits;
+
+		/* Clear the bits. */
+		pxEventBits->uxEventBits &= ~uxBitsToClear;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+
+	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )
+	{
+		BaseType_t xReturn;
+
+		traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );
+		xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */
+
+		return xReturn;
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )
+{
+UBaseType_t uxSavedInterruptStatus;
+EventGroup_t const * const pxEventBits = xEventGroup;
+EventBits_t uxReturn;
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		uxReturn = pxEventBits->uxEventBits;
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return uxReturn;
+} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet )
+{
+ListItem_t *pxListItem, *pxNext;
+ListItem_t const *pxListEnd;
+List_t const * pxList;
+EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;
+EventGroup_t *pxEventBits = xEventGroup;
+BaseType_t xMatchFound = pdFALSE;
+
+	/* Check the user is not attempting to set the bits used by the kernel
+	itself. */
+	configASSERT( xEventGroup );
+	configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+
+	pxList = &( pxEventBits->xTasksWaitingForBits );
+	pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+	vTaskSuspendAll();
+	{
+		traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );
+
+		pxListItem = listGET_HEAD_ENTRY( pxList );
+
+		/* Set the bits. */
+		pxEventBits->uxEventBits |= uxBitsToSet;
+
+		/* See if the new bit value should unblock any tasks. */
+		while( pxListItem != pxListEnd )
+		{
+			pxNext = listGET_NEXT( pxListItem );
+			uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );
+			xMatchFound = pdFALSE;
+
+			/* Split the bits waited for from the control bits. */
+			uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;
+			uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;
+
+			if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )
+			{
+				/* Just looking for single bit being set. */
+				if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )
+				{
+					xMatchFound = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )
+			{
+				/* All bits are set. */
+				xMatchFound = pdTRUE;
+			}
+			else
+			{
+				/* Need all bits to be set, but not all the bits were set. */
+			}
+
+			if( xMatchFound != pdFALSE )
+			{
+				/* The bits match.  Should the bits be cleared on exit? */
+				if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )
+				{
+					uxBitsToClear |= uxBitsWaitedFor;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* Store the actual event flag value in the task's event list
+				item before removing the task from the event list.  The
+				eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows
+				that is was unblocked due to its required bits matching, rather
+				than because it timed out. */
+				vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );
+			}
+
+			/* Move onto the next list item.  Note pxListItem->pxNext is not
+			used here as the list item may have been removed from the event list
+			and inserted into the ready/pending reading list. */
+			pxListItem = pxNext;
+		}
+
+		/* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT
+		bit was set in the control word. */
+		pxEventBits->uxEventBits &= ~uxBitsToClear;
+	}
+	( void ) xTaskResumeAll();
+
+	return pxEventBits->uxEventBits;
+}
+/*-----------------------------------------------------------*/
+
+void vEventGroupDelete( EventGroupHandle_t xEventGroup )
+{
+EventGroup_t *pxEventBits = xEventGroup;
+const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );
+
+	vTaskSuspendAll();
+	{
+		traceEVENT_GROUP_DELETE( xEventGroup );
+
+		while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )
+		{
+			/* Unblock the task, returning 0 as the event list is being deleted
+			and cannot therefore have any bits set. */
+			configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );
+			vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );
+		}
+
+		#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+		{
+			/* The event group can only have been allocated dynamically - free
+			it again. */
+			vPortFree( pxEventBits );
+		}
+		#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+		{
+			/* The event group could have been allocated statically or
+			dynamically, so check before attempting to free the memory. */
+			if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+			{
+				vPortFree( pxEventBits );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+	}
+	( void ) xTaskResumeAll();
+}
+/*-----------------------------------------------------------*/
+
+/* For internal use only - execute a 'set bits' command that was pended from
+an interrupt. */
+void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet )
+{
+	( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */
+}
+/*-----------------------------------------------------------*/
+
+/* For internal use only - execute a 'clear bits' command that was pended from
+an interrupt. */
+void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear )
+{
+	( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits )
+{
+BaseType_t xWaitConditionMet = pdFALSE;
+
+	if( xWaitForAllBits == pdFALSE )
+	{
+		/* Task only has to wait for one bit within uxBitsToWaitFor to be
+		set.  Is one already set? */
+		if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )
+		{
+			xWaitConditionMet = pdTRUE;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		/* Task has to wait for all the bits in uxBitsToWaitFor to be set.
+		Are they set already? */
+		if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )
+		{
+			xWaitConditionMet = pdTRUE;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	return xWaitConditionMet;
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+
+	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	BaseType_t xReturn;
+
+		traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );
+		xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */
+
+		return xReturn;
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if (configUSE_TRACE_FACILITY == 1)
+
+	UBaseType_t uxEventGroupGetNumber( void* xEventGroup )
+	{
+	UBaseType_t xReturn;
+	EventGroup_t const *pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */
+
+		if( xEventGroup == NULL )
+		{
+			xReturn = 0;
+		}
+		else
+		{
+			xReturn = pxEventBits->uxEventGroupNumber;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vEventGroupSetNumber( void * xEventGroup, UBaseType_t uxEventGroupNumber )
+	{
+		( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/include/FreeRTOS.h b/FreeRTOSv10.2.1/FreeRTOS/Source/include/FreeRTOS.h
new file mode 100644
index 0000000..45c778a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/include/FreeRTOS.h
@@ -0,0 +1,1278 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef INC_FREERTOS_H
+#define INC_FREERTOS_H
+
+/*
+ * Include the generic headers required for the FreeRTOS port being used.
+ */
+#include 
+
+/*
+ * If stdint.h cannot be located then:
+ *   + If using GCC ensure the -nostdint options is *not* being used.
+ *   + Ensure the project's include path includes the directory in which your
+ *     compiler stores stdint.h.
+ *   + Set any compiler options necessary for it to support C99, as technically
+ *     stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any
+ *     other way).
+ *   + The FreeRTOS download includes a simple stdint.h definition that can be
+ *     used in cases where none is provided by the compiler.  The files only
+ *     contains the typedefs required to build FreeRTOS.  Read the instructions
+ *     in FreeRTOS/source/stdint.readme for more information.
+ */
+#include  /* READ COMMENT ABOVE. */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Application specific configuration options. */
+#include "FreeRTOSConfig.h"
+
+/* Basic FreeRTOS definitions. */
+#include "projdefs.h"
+
+/* Definitions specific to the port being used. */
+#include "portable.h"
+
+/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */
+#ifndef configUSE_NEWLIB_REENTRANT
+	#define configUSE_NEWLIB_REENTRANT 0
+#endif
+
+/* Required if struct _reent is used. */
+#if ( configUSE_NEWLIB_REENTRANT == 1 )
+	#include 
+#endif
+/*
+ * Check all the required application specific macros have been defined.
+ * These macros are application specific and (as downloaded) are defined
+ * within FreeRTOSConfig.h.
+ */
+
+#ifndef configMINIMAL_STACK_SIZE
+	#error Missing definition:  configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h.  configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task.  Refer to the demo project provided for your port for a suitable value.
+#endif
+
+#ifndef configMAX_PRIORITIES
+	#error Missing definition:  configMAX_PRIORITIES must be defined in FreeRTOSConfig.h.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#if configMAX_PRIORITIES < 1
+	#error configMAX_PRIORITIES must be defined to be greater than or equal to 1.
+#endif
+
+#ifndef configUSE_PREEMPTION
+	#error Missing definition:  configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_IDLE_HOOK
+	#error Missing definition:  configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_TICK_HOOK
+	#error Missing definition:  configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_16_BIT_TICKS
+	#error Missing definition:  configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_CO_ROUTINES
+	#define configUSE_CO_ROUTINES 0
+#endif
+
+#ifndef INCLUDE_vTaskPrioritySet
+	#define INCLUDE_vTaskPrioritySet 0
+#endif
+
+#ifndef INCLUDE_uxTaskPriorityGet
+	#define INCLUDE_uxTaskPriorityGet 0
+#endif
+
+#ifndef INCLUDE_vTaskDelete
+	#define INCLUDE_vTaskDelete 0
+#endif
+
+#ifndef INCLUDE_vTaskSuspend
+	#define INCLUDE_vTaskSuspend 0
+#endif
+
+#ifndef INCLUDE_vTaskDelayUntil
+	#define INCLUDE_vTaskDelayUntil 0
+#endif
+
+#ifndef INCLUDE_vTaskDelay
+	#define INCLUDE_vTaskDelay 0
+#endif
+
+#ifndef INCLUDE_xTaskGetIdleTaskHandle
+	#define INCLUDE_xTaskGetIdleTaskHandle 0
+#endif
+
+#ifndef INCLUDE_xTaskAbortDelay
+	#define INCLUDE_xTaskAbortDelay 0
+#endif
+
+#ifndef INCLUDE_xQueueGetMutexHolder
+	#define INCLUDE_xQueueGetMutexHolder 0
+#endif
+
+#ifndef INCLUDE_xSemaphoreGetMutexHolder
+	#define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder
+#endif
+
+#ifndef INCLUDE_xTaskGetHandle
+	#define INCLUDE_xTaskGetHandle 0
+#endif
+
+#ifndef INCLUDE_uxTaskGetStackHighWaterMark
+	#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#endif
+
+#ifndef INCLUDE_uxTaskGetStackHighWaterMark2
+	#define INCLUDE_uxTaskGetStackHighWaterMark2 0
+#endif
+
+#ifndef INCLUDE_eTaskGetState
+	#define INCLUDE_eTaskGetState 0
+#endif
+
+#ifndef INCLUDE_xTaskResumeFromISR
+	#define INCLUDE_xTaskResumeFromISR 1
+#endif
+
+#ifndef INCLUDE_xTimerPendFunctionCall
+	#define INCLUDE_xTimerPendFunctionCall 0
+#endif
+
+#ifndef INCLUDE_xTaskGetSchedulerState
+	#define INCLUDE_xTaskGetSchedulerState 0
+#endif
+
+#ifndef INCLUDE_xTaskGetCurrentTaskHandle
+	#define INCLUDE_xTaskGetCurrentTaskHandle 0
+#endif
+
+#if configUSE_CO_ROUTINES != 0
+	#ifndef configMAX_CO_ROUTINE_PRIORITIES
+		#error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1.
+	#endif
+#endif
+
+#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK
+	#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
+#endif
+
+#ifndef configUSE_APPLICATION_TASK_TAG
+	#define configUSE_APPLICATION_TASK_TAG 0
+#endif
+
+#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS
+	#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0
+#endif
+
+#ifndef configUSE_RECURSIVE_MUTEXES
+	#define configUSE_RECURSIVE_MUTEXES 0
+#endif
+
+#ifndef configUSE_MUTEXES
+	#define configUSE_MUTEXES 0
+#endif
+
+#ifndef configUSE_TIMERS
+	#define configUSE_TIMERS 0
+#endif
+
+#ifndef configUSE_COUNTING_SEMAPHORES
+	#define configUSE_COUNTING_SEMAPHORES 0
+#endif
+
+#ifndef configUSE_ALTERNATIVE_API
+	#define configUSE_ALTERNATIVE_API 0
+#endif
+
+#ifndef portCRITICAL_NESTING_IN_TCB
+	#define portCRITICAL_NESTING_IN_TCB 0
+#endif
+
+#ifndef configMAX_TASK_NAME_LEN
+	#define configMAX_TASK_NAME_LEN 16
+#endif
+
+#ifndef configIDLE_SHOULD_YIELD
+	#define configIDLE_SHOULD_YIELD		1
+#endif
+
+#if configMAX_TASK_NAME_LEN < 1
+	#error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h
+#endif
+
+#ifndef configASSERT
+	#define configASSERT( x )
+	#define configASSERT_DEFINED 0
+#else
+	#define configASSERT_DEFINED 1
+#endif
+
+#ifndef portMEMORY_BARRIER
+	#define portMEMORY_BARRIER()
+#endif
+
+/* The timers module relies on xTaskGetSchedulerState(). */
+#if configUSE_TIMERS == 1
+
+	#ifndef configTIMER_TASK_PRIORITY
+		#error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined.
+	#endif /* configTIMER_TASK_PRIORITY */
+
+	#ifndef configTIMER_QUEUE_LENGTH
+		#error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined.
+	#endif /* configTIMER_QUEUE_LENGTH */
+
+	#ifndef configTIMER_TASK_STACK_DEPTH
+		#error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined.
+	#endif /* configTIMER_TASK_STACK_DEPTH */
+
+#endif /* configUSE_TIMERS */
+
+#ifndef portSET_INTERRUPT_MASK_FROM_ISR
+	#define portSET_INTERRUPT_MASK_FROM_ISR() 0
+#endif
+
+#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR
+	#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
+#endif
+
+#ifndef portCLEAN_UP_TCB
+	#define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB
+#endif
+
+#ifndef portPRE_TASK_DELETE_HOOK
+	#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending )
+#endif
+
+#ifndef portSETUP_TCB
+	#define portSETUP_TCB( pxTCB ) ( void ) pxTCB
+#endif
+
+#ifndef configQUEUE_REGISTRY_SIZE
+	#define configQUEUE_REGISTRY_SIZE 0U
+#endif
+
+#if ( configQUEUE_REGISTRY_SIZE < 1 )
+	#define vQueueAddToRegistry( xQueue, pcName )
+	#define vQueueUnregisterQueue( xQueue )
+	#define pcQueueGetName( xQueue )
+#endif
+
+#ifndef portPOINTER_SIZE_TYPE
+	#define portPOINTER_SIZE_TYPE uint32_t
+#endif
+
+/* Remove any unused trace macros. */
+#ifndef traceSTART
+	/* Used to perform any necessary initialisation - for example, open a file
+	into which trace is to be written. */
+	#define traceSTART()
+#endif
+
+#ifndef traceEND
+	/* Use to close a trace, for example close a file into which trace has been
+	written. */
+	#define traceEND()
+#endif
+
+#ifndef traceTASK_SWITCHED_IN
+	/* Called after a task has been selected to run.  pxCurrentTCB holds a pointer
+	to the task control block of the selected task. */
+	#define traceTASK_SWITCHED_IN()
+#endif
+
+#ifndef traceINCREASE_TICK_COUNT
+	/* Called before stepping the tick count after waking from tickless idle
+	sleep. */
+	#define traceINCREASE_TICK_COUNT( x )
+#endif
+
+#ifndef traceLOW_POWER_IDLE_BEGIN
+	/* Called immediately before entering tickless idle. */
+	#define traceLOW_POWER_IDLE_BEGIN()
+#endif
+
+#ifndef	traceLOW_POWER_IDLE_END
+	/* Called when returning to the Idle task after a tickless idle. */
+	#define traceLOW_POWER_IDLE_END()
+#endif
+
+#ifndef traceTASK_SWITCHED_OUT
+	/* Called before a task has been selected to run.  pxCurrentTCB holds a pointer
+	to the task control block of the task being switched out. */
+	#define traceTASK_SWITCHED_OUT()
+#endif
+
+#ifndef traceTASK_PRIORITY_INHERIT
+	/* Called when a task attempts to take a mutex that is already held by a
+	lower priority task.  pxTCBOfMutexHolder is a pointer to the TCB of the task
+	that holds the mutex.  uxInheritedPriority is the priority the mutex holder
+	will inherit (the priority of the task that is attempting to obtain the
+	muted. */
+	#define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority )
+#endif
+
+#ifndef traceTASK_PRIORITY_DISINHERIT
+	/* Called when a task releases a mutex, the holding of which had resulted in
+	the task inheriting the priority of a higher priority task.
+	pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the
+	mutex.  uxOriginalPriority is the task's configured (base) priority. */
+	#define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority )
+#endif
+
+#ifndef traceBLOCKING_ON_QUEUE_RECEIVE
+	/* Task is about to block because it cannot read from a
+	queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
+	upon which the read was attempted.  pxCurrentTCB points to the TCB of the
+	task that attempted the read. */
+	#define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue )
+#endif
+
+#ifndef traceBLOCKING_ON_QUEUE_PEEK
+	/* Task is about to block because it cannot read from a
+	queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
+	upon which the read was attempted.  pxCurrentTCB points to the TCB of the
+	task that attempted the read. */
+	#define traceBLOCKING_ON_QUEUE_PEEK( pxQueue )
+#endif
+
+#ifndef traceBLOCKING_ON_QUEUE_SEND
+	/* Task is about to block because it cannot write to a
+	queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
+	upon which the write was attempted.  pxCurrentTCB points to the TCB of the
+	task that attempted the write. */
+	#define traceBLOCKING_ON_QUEUE_SEND( pxQueue )
+#endif
+
+#ifndef configCHECK_FOR_STACK_OVERFLOW
+	#define configCHECK_FOR_STACK_OVERFLOW 0
+#endif
+
+#ifndef configRECORD_STACK_HIGH_ADDRESS
+	#define configRECORD_STACK_HIGH_ADDRESS 0
+#endif
+
+#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H
+	#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0
+#endif
+
+/* The following event macros are embedded in the kernel API calls. */
+
+#ifndef traceMOVED_TASK_TO_READY_STATE
+	#define traceMOVED_TASK_TO_READY_STATE( pxTCB )
+#endif
+
+#ifndef tracePOST_MOVED_TASK_TO_READY_STATE
+	#define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
+#endif
+
+#ifndef traceQUEUE_CREATE
+	#define traceQUEUE_CREATE( pxNewQueue )
+#endif
+
+#ifndef traceQUEUE_CREATE_FAILED
+	#define traceQUEUE_CREATE_FAILED( ucQueueType )
+#endif
+
+#ifndef traceCREATE_MUTEX
+	#define traceCREATE_MUTEX( pxNewQueue )
+#endif
+
+#ifndef traceCREATE_MUTEX_FAILED
+	#define traceCREATE_MUTEX_FAILED()
+#endif
+
+#ifndef traceGIVE_MUTEX_RECURSIVE
+	#define traceGIVE_MUTEX_RECURSIVE( pxMutex )
+#endif
+
+#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED
+	#define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex )
+#endif
+
+#ifndef traceTAKE_MUTEX_RECURSIVE
+	#define traceTAKE_MUTEX_RECURSIVE( pxMutex )
+#endif
+
+#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED
+	#define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex )
+#endif
+
+#ifndef traceCREATE_COUNTING_SEMAPHORE
+	#define traceCREATE_COUNTING_SEMAPHORE()
+#endif
+
+#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED
+	#define traceCREATE_COUNTING_SEMAPHORE_FAILED()
+#endif
+
+#ifndef traceQUEUE_SEND
+	#define traceQUEUE_SEND( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FAILED
+	#define traceQUEUE_SEND_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE
+	#define traceQUEUE_RECEIVE( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK
+	#define traceQUEUE_PEEK( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK_FAILED
+	#define traceQUEUE_PEEK_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK_FROM_ISR
+	#define traceQUEUE_PEEK_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FAILED
+	#define traceQUEUE_RECEIVE_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FROM_ISR
+	#define traceQUEUE_SEND_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FROM_ISR_FAILED
+	#define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FROM_ISR
+	#define traceQUEUE_RECEIVE_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED
+	#define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED
+	#define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_DELETE
+	#define traceQUEUE_DELETE( pxQueue )
+#endif
+
+#ifndef traceTASK_CREATE
+	#define traceTASK_CREATE( pxNewTCB )
+#endif
+
+#ifndef traceTASK_CREATE_FAILED
+	#define traceTASK_CREATE_FAILED()
+#endif
+
+#ifndef traceTASK_DELETE
+	#define traceTASK_DELETE( pxTaskToDelete )
+#endif
+
+#ifndef traceTASK_DELAY_UNTIL
+	#define traceTASK_DELAY_UNTIL( x )
+#endif
+
+#ifndef traceTASK_DELAY
+	#define traceTASK_DELAY()
+#endif
+
+#ifndef traceTASK_PRIORITY_SET
+	#define traceTASK_PRIORITY_SET( pxTask, uxNewPriority )
+#endif
+
+#ifndef traceTASK_SUSPEND
+	#define traceTASK_SUSPEND( pxTaskToSuspend )
+#endif
+
+#ifndef traceTASK_RESUME
+	#define traceTASK_RESUME( pxTaskToResume )
+#endif
+
+#ifndef traceTASK_RESUME_FROM_ISR
+	#define traceTASK_RESUME_FROM_ISR( pxTaskToResume )
+#endif
+
+#ifndef traceTASK_INCREMENT_TICK
+	#define traceTASK_INCREMENT_TICK( xTickCount )
+#endif
+
+#ifndef traceTIMER_CREATE
+	#define traceTIMER_CREATE( pxNewTimer )
+#endif
+
+#ifndef traceTIMER_CREATE_FAILED
+	#define traceTIMER_CREATE_FAILED()
+#endif
+
+#ifndef traceTIMER_COMMAND_SEND
+	#define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn )
+#endif
+
+#ifndef traceTIMER_EXPIRED
+	#define traceTIMER_EXPIRED( pxTimer )
+#endif
+
+#ifndef traceTIMER_COMMAND_RECEIVED
+	#define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue )
+#endif
+
+#ifndef traceMALLOC
+    #define traceMALLOC( pvAddress, uiSize )
+#endif
+
+#ifndef traceFREE
+    #define traceFREE( pvAddress, uiSize )
+#endif
+
+#ifndef traceEVENT_GROUP_CREATE
+	#define traceEVENT_GROUP_CREATE( xEventGroup )
+#endif
+
+#ifndef traceEVENT_GROUP_CREATE_FAILED
+	#define traceEVENT_GROUP_CREATE_FAILED()
+#endif
+
+#ifndef traceEVENT_GROUP_SYNC_BLOCK
+	#define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor )
+#endif
+
+#ifndef traceEVENT_GROUP_SYNC_END
+	#define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred
+#endif
+
+#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK
+	#define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor )
+#endif
+
+#ifndef traceEVENT_GROUP_WAIT_BITS_END
+	#define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred
+#endif
+
+#ifndef traceEVENT_GROUP_CLEAR_BITS
+	#define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear )
+#endif
+
+#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR
+	#define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear )
+#endif
+
+#ifndef traceEVENT_GROUP_SET_BITS
+	#define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet )
+#endif
+
+#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR
+	#define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet )
+#endif
+
+#ifndef traceEVENT_GROUP_DELETE
+	#define traceEVENT_GROUP_DELETE( xEventGroup )
+#endif
+
+#ifndef tracePEND_FUNC_CALL
+	#define tracePEND_FUNC_CALL(xFunctionToPend, pvParameter1, ulParameter2, ret)
+#endif
+
+#ifndef tracePEND_FUNC_CALL_FROM_ISR
+	#define tracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend, pvParameter1, ulParameter2, ret)
+#endif
+
+#ifndef traceQUEUE_REGISTRY_ADD
+	#define traceQUEUE_REGISTRY_ADD(xQueue, pcQueueName)
+#endif
+
+#ifndef traceTASK_NOTIFY_TAKE_BLOCK
+	#define traceTASK_NOTIFY_TAKE_BLOCK()
+#endif
+
+#ifndef traceTASK_NOTIFY_TAKE
+	#define traceTASK_NOTIFY_TAKE()
+#endif
+
+#ifndef traceTASK_NOTIFY_WAIT_BLOCK
+	#define traceTASK_NOTIFY_WAIT_BLOCK()
+#endif
+
+#ifndef traceTASK_NOTIFY_WAIT
+	#define traceTASK_NOTIFY_WAIT()
+#endif
+
+#ifndef traceTASK_NOTIFY
+	#define traceTASK_NOTIFY()
+#endif
+
+#ifndef traceTASK_NOTIFY_FROM_ISR
+	#define traceTASK_NOTIFY_FROM_ISR()
+#endif
+
+#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR
+	#define traceTASK_NOTIFY_GIVE_FROM_ISR()
+#endif
+
+#ifndef traceSTREAM_BUFFER_CREATE_FAILED
+	#define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED
+	#define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_CREATE
+	#define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_DELETE
+	#define traceSTREAM_BUFFER_DELETE( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RESET
+	#define traceSTREAM_BUFFER_RESET( xStreamBuffer )
+#endif
+
+#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND
+	#define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_SEND
+	#define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent )
+#endif
+
+#ifndef traceSTREAM_BUFFER_SEND_FAILED
+	#define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR
+	#define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent )
+#endif
+
+#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE
+	#define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RECEIVE
+	#define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED
+	#define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR
+	#define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength )
+#endif
+
+#ifndef configGENERATE_RUN_TIME_STATS
+	#define configGENERATE_RUN_TIME_STATS 0
+#endif
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+	#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS
+		#error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined.  portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base.
+	#endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */
+
+	#ifndef portGET_RUN_TIME_COUNTER_VALUE
+		#ifndef portALT_GET_RUN_TIME_COUNTER_VALUE
+			#error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined.  See the examples provided and the FreeRTOS web site for more information.
+		#endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */
+	#endif /* portGET_RUN_TIME_COUNTER_VALUE */
+
+#endif /* configGENERATE_RUN_TIME_STATS */
+
+#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS
+	#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
+#endif
+
+#ifndef configUSE_MALLOC_FAILED_HOOK
+	#define configUSE_MALLOC_FAILED_HOOK 0
+#endif
+
+#ifndef portPRIVILEGE_BIT
+	#define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 )
+#endif
+
+#ifndef portYIELD_WITHIN_API
+	#define portYIELD_WITHIN_API portYIELD
+#endif
+
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )
+#endif
+
+#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP
+	#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2
+#endif
+
+#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2
+	#error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2
+#endif
+
+#ifndef configUSE_TICKLESS_IDLE
+	#define configUSE_TICKLESS_IDLE 0
+#endif
+
+#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING
+	#define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x )
+#endif
+
+#ifndef configPRE_SLEEP_PROCESSING
+	#define configPRE_SLEEP_PROCESSING( x )
+#endif
+
+#ifndef configPOST_SLEEP_PROCESSING
+	#define configPOST_SLEEP_PROCESSING( x )
+#endif
+
+#ifndef configUSE_QUEUE_SETS
+	#define configUSE_QUEUE_SETS 0
+#endif
+
+#ifndef portTASK_USES_FLOATING_POINT
+	#define portTASK_USES_FLOATING_POINT()
+#endif
+
+#ifndef portALLOCATE_SECURE_CONTEXT
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+#endif
+
+#ifndef portDONT_DISCARD
+	#define portDONT_DISCARD
+#endif
+
+#ifndef configUSE_TIME_SLICING
+	#define configUSE_TIME_SLICING 1
+#endif
+
+#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS
+	#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0
+#endif
+
+#ifndef configUSE_STATS_FORMATTING_FUNCTIONS
+	#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+#endif
+
+#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()
+#endif
+
+#ifndef configUSE_TRACE_FACILITY
+	#define configUSE_TRACE_FACILITY 0
+#endif
+
+#ifndef mtCOVERAGE_TEST_MARKER
+	#define mtCOVERAGE_TEST_MARKER()
+#endif
+
+#ifndef mtCOVERAGE_TEST_DELAY
+	#define mtCOVERAGE_TEST_DELAY()
+#endif
+
+#ifndef portASSERT_IF_IN_ISR
+	#define portASSERT_IF_IN_ISR()
+#endif
+
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#endif
+
+#ifndef configAPPLICATION_ALLOCATED_HEAP
+	#define configAPPLICATION_ALLOCATED_HEAP 0
+#endif
+
+#ifndef configUSE_TASK_NOTIFICATIONS
+	#define configUSE_TASK_NOTIFICATIONS 1
+#endif
+
+#ifndef configUSE_POSIX_ERRNO
+	#define configUSE_POSIX_ERRNO 0
+#endif
+
+#ifndef portTICK_TYPE_IS_ATOMIC
+	#define portTICK_TYPE_IS_ATOMIC 0
+#endif
+
+#ifndef configSUPPORT_STATIC_ALLOCATION
+	/* Defaults to 0 for backward compatibility. */
+	#define configSUPPORT_STATIC_ALLOCATION 0
+#endif
+
+#ifndef configSUPPORT_DYNAMIC_ALLOCATION
+	/* Defaults to 1 for backward compatibility. */
+	#define configSUPPORT_DYNAMIC_ALLOCATION 1
+#endif
+
+#ifndef configSTACK_DEPTH_TYPE
+	/* Defaults to uint16_t for backward compatibility, but can be overridden
+	in FreeRTOSConfig.h if uint16_t is too restrictive. */
+	#define configSTACK_DEPTH_TYPE uint16_t
+#endif
+
+#ifndef configMESSAGE_BUFFER_LENGTH_TYPE
+	/* Defaults to size_t for backward compatibility, but can be overridden
+	in FreeRTOSConfig.h if lengths will always be less than the number of bytes
+	in a size_t. */
+	#define configMESSAGE_BUFFER_LENGTH_TYPE size_t
+#endif
+
+/* Sanity check the configuration. */
+#if( configUSE_TICKLESS_IDLE != 0 )
+	#if( INCLUDE_vTaskSuspend != 1 )
+		#error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0
+	#endif /* INCLUDE_vTaskSuspend */
+#endif /* configUSE_TICKLESS_IDLE */
+
+#if( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )
+	#error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1.
+#endif
+
+#if( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) )
+	#error configUSE_MUTEXES must be set to 1 to use recursive mutexes
+#endif
+
+#ifndef configINITIAL_TICK_COUNT
+	#define configINITIAL_TICK_COUNT 0
+#endif
+
+#if( portTICK_TYPE_IS_ATOMIC == 0 )
+	/* Either variables of tick type cannot be read atomically, or
+	portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when
+	the tick count is returned to the standard critical section macros. */
+	#define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL()
+	#define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL()
+	#define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()
+	#define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) )
+#else
+	/* The tick type can be read atomically, so critical sections used when the
+	tick count is returned can be defined away. */
+	#define portTICK_TYPE_ENTER_CRITICAL()
+	#define portTICK_TYPE_EXIT_CRITICAL()
+	#define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0
+	#define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x
+#endif
+
+/* Definitions to allow backward compatibility with FreeRTOS versions prior to
+V8 if desired. */
+#ifndef configENABLE_BACKWARD_COMPATIBILITY
+	#define configENABLE_BACKWARD_COMPATIBILITY 1
+#endif
+
+#ifndef configPRINTF
+	/* configPRINTF() was not defined, so define it away to nothing.  To use
+	configPRINTF() then define it as follows (where MyPrintFunction() is
+	provided by the application writer):
+
+	void MyPrintFunction(const char *pcFormat, ... );
+	#define configPRINTF( X )   MyPrintFunction X
+
+	Then call like a standard printf() function, but placing brackets around
+	all parameters so they are passed as a single parameter.  For example:
+	configPRINTF( ("Value = %d", MyVariable) ); */
+	#define configPRINTF( X )
+#endif
+
+#ifndef configMAX
+	/* The application writer has not provided their own MAX macro, so define
+	the following generic implementation. */
+	#define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) )
+#endif
+
+#ifndef configMIN
+	/* The application writer has not provided their own MAX macro, so define
+	the following generic implementation. */
+	#define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) )
+#endif
+
+#if configENABLE_BACKWARD_COMPATIBILITY == 1
+	#define eTaskStateGet eTaskGetState
+	#define portTickType TickType_t
+	#define xTaskHandle TaskHandle_t
+	#define xQueueHandle QueueHandle_t
+	#define xSemaphoreHandle SemaphoreHandle_t
+	#define xQueueSetHandle QueueSetHandle_t
+	#define xQueueSetMemberHandle QueueSetMemberHandle_t
+	#define xTimeOutType TimeOut_t
+	#define xMemoryRegion MemoryRegion_t
+	#define xTaskParameters TaskParameters_t
+	#define xTaskStatusType	TaskStatus_t
+	#define xTimerHandle TimerHandle_t
+	#define xCoRoutineHandle CoRoutineHandle_t
+	#define pdTASK_HOOK_CODE TaskHookFunction_t
+	#define portTICK_RATE_MS portTICK_PERIOD_MS
+	#define pcTaskGetTaskName pcTaskGetName
+	#define pcTimerGetTimerName pcTimerGetName
+	#define pcQueueGetQueueName pcQueueGetName
+	#define vTaskGetTaskInfo vTaskGetInfo
+
+	/* Backward compatibility within the scheduler code only - these definitions
+	are not really required but are included for completeness. */
+	#define tmrTIMER_CALLBACK TimerCallbackFunction_t
+	#define pdTASK_CODE TaskFunction_t
+	#define xListItem ListItem_t
+	#define xList List_t
+
+	/* For libraries that break the list data hiding, and access list structure
+	members directly (which is not supposed to be done). */
+	#define pxContainer pvContainer
+#endif /* configENABLE_BACKWARD_COMPATIBILITY */
+
+#if( configUSE_ALTERNATIVE_API != 0 )
+	#error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0
+#endif
+
+/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even
+if floating point hardware is otherwise supported by the FreeRTOS port in use.
+This constant is not supported by all FreeRTOS ports that include floating
+point support. */
+#ifndef configUSE_TASK_FPU_SUPPORT
+	#define configUSE_TASK_FPU_SUPPORT 1
+#endif
+
+/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is
+currently used in ARMv8M ports. */
+#ifndef configENABLE_MPU
+	#define configENABLE_MPU 0
+#endif
+
+/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is
+currently used in ARMv8M ports. */
+#ifndef configENABLE_FPU
+	#define configENABLE_FPU 1
+#endif
+
+/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it.
+This is currently used in ARMv8M ports. */
+#ifndef configENABLE_TRUSTZONE
+	#define configENABLE_TRUSTZONE 1
+#endif
+
+/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on
+the Secure Side only. */
+#ifndef configRUN_FREERTOS_SECURE_ONLY
+	#define configRUN_FREERTOS_SECURE_ONLY 0
+#endif
+
+/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
+ * dynamically allocated RAM, in which case when any task is deleted it is known
+ * that both the task's stack and TCB need to be freed.  Sometimes the
+ * FreeRTOSConfig.h settings only allow a task to be created using statically
+ * allocated RAM, in which case when any task is deleted it is known that neither
+ * the task's stack or TCB should be freed.  Sometimes the FreeRTOSConfig.h
+ * settings allow a task to be created using either statically or dynamically
+ * allocated RAM, in which case a member of the TCB is used to record whether the
+ * stack and/or TCB were allocated statically or dynamically, so when a task is
+ * deleted the RAM that was allocated dynamically is freed again and no attempt is
+ * made to free the RAM that was allocated statically.
+ * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a
+ * task to be created using either statically or dynamically allocated RAM.  Note
+ * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with
+ * a statically allocated stack and a dynamically allocated TCB.
+ *
+ * The following table lists various combinations of portUSING_MPU_WRAPPERS,
+ * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and
+ * when it is possible to have both static and dynamic allocation:
+ *  +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ * | MPU | Dynamic | Static |     Available Functions     |       Possible Allocations        | Both Dynamic and | Need Free |
+ * |     |         |        |                             |                                   | Static Possible  |           |
+ * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ * | 0   | 0       | 1      | xTaskCreateStatic           | TCB - Static, Stack - Static      | No               | No        |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 0   | 1       | 0      | xTaskCreate                 | TCB - Dynamic, Stack - Dynamic    | No               | Yes       |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 0   | 1       | 1      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
+ * |     |         |        | xTaskCreateStatic           | 2. TCB - Static, Stack - Static   |                  |           |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1   | 0       | 1      | xTaskCreateStatic,          | TCB - Static, Stack - Static      | No               | No        |
+ * |     |         |        | xTaskCreateRestrictedStatic |                                   |                  |           |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1   | 1       | 0      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
+ * |     |         |        | xTaskCreateRestricted       | 2. TCB - Dynamic, Stack - Static  |                  |           |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1   | 1       | 1      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
+ * |     |         |        | xTaskCreateStatic,          | 2. TCB - Dynamic, Stack - Static  |                  |           |
+ * |     |         |        | xTaskCreateRestricted,      | 3. TCB - Static, Stack - Static   |                  |           |
+ * |     |         |        | xTaskCreateRestrictedStatic |                                   |                  |           |
+ * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ */
+#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE	( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \
+													  ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) )
+
+/*
+ * In line with software engineering best practice, FreeRTOS implements a strict
+ * data hiding policy, so the real structures used by FreeRTOS to maintain the
+ * state of tasks, queues, semaphores, etc. are not accessible to the application
+ * code.  However, if the application writer wants to statically allocate such
+ * an object then the size of the object needs to be know.  Dummy structures
+ * that are guaranteed to have the same size and alignment requirements of the
+ * real objects are used for this purpose.  The dummy list and list item
+ * structures below are used for inclusion in such a dummy structure.
+ */
+struct xSTATIC_LIST_ITEM
+{
+	#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+		TickType_t xDummy1;
+	#endif
+	TickType_t xDummy2;
+	void *pvDummy3[ 4 ];
+	#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+		TickType_t xDummy4;
+	#endif
+};
+typedef struct xSTATIC_LIST_ITEM StaticListItem_t;
+
+/* See the comments above the struct xSTATIC_LIST_ITEM definition. */
+struct xSTATIC_MINI_LIST_ITEM
+{
+	#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+		TickType_t xDummy1;
+	#endif
+	TickType_t xDummy2;
+	void *pvDummy3[ 2 ];
+};
+typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t;
+
+/* See the comments above the struct xSTATIC_LIST_ITEM definition. */
+typedef struct xSTATIC_LIST
+{
+	#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+		TickType_t xDummy1;
+	#endif
+	UBaseType_t uxDummy2;
+	void *pvDummy3;
+	StaticMiniListItem_t xDummy4;
+	#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+		TickType_t xDummy5;
+	#endif
+} StaticList_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the Task structure used internally by
+ * FreeRTOS is not accessible to application code.  However, if the application
+ * writer wants to statically allocate the memory required to create a task then
+ * the size of the task object needs to be know.  The StaticTask_t structure
+ * below is provided for this purpose.  Its sizes and alignment requirements are
+ * guaranteed to match those of the genuine structure, no matter which
+ * architecture is being used, and no matter how the values in FreeRTOSConfig.h
+ * are set.  Its contents are somewhat obfuscated in the hope users will
+ * recognise that it would be unwise to make direct use of the structure members.
+ */
+typedef struct xSTATIC_TCB
+{
+	void				*pxDummy1;
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+		xMPU_SETTINGS	xDummy2;
+	#endif
+	StaticListItem_t	xDummy3[ 2 ];
+	UBaseType_t			uxDummy5;
+	void				*pxDummy6;
+	uint8_t				ucDummy7[ configMAX_TASK_NAME_LEN ];
+	#if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+		void			*pxDummy8;
+	#endif
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+		UBaseType_t		uxDummy9;
+	#endif
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t		uxDummy10[ 2 ];
+	#endif
+	#if ( configUSE_MUTEXES == 1 )
+		UBaseType_t		uxDummy12[ 2 ];
+	#endif
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+		void			*pxDummy14;
+	#endif
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+		void			*pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+	#endif
+	#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		uint32_t		ulDummy16;
+	#endif
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		struct	_reent	xDummy17;
+	#endif
+	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+		uint32_t 		ulDummy18;
+		uint8_t 		ucDummy19;
+	#endif
+	#if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+		uint8_t			uxDummy20;
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+		uint8_t ucDummy21;
+	#endif
+	#if ( configUSE_POSIX_ERRNO == 1 )
+		int				iDummy22;
+	#endif
+} StaticTask_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the Queue structure used internally by
+ * FreeRTOS is not accessible to application code.  However, if the application
+ * writer wants to statically allocate the memory required to create a queue
+ * then the size of the queue object needs to be know.  The StaticQueue_t
+ * structure below is provided for this purpose.  Its sizes and alignment
+ * requirements are guaranteed to match those of the genuine structure, no
+ * matter which architecture is being used, and no matter how the values in
+ * FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in the hope
+ * users will recognise that it would be unwise to make direct use of the
+ * structure members.
+ */
+typedef struct xSTATIC_QUEUE
+{
+	void *pvDummy1[ 3 ];
+
+	union
+	{
+		void *pvDummy2;
+		UBaseType_t uxDummy2;
+	} u;
+
+	StaticList_t xDummy3[ 2 ];
+	UBaseType_t uxDummy4[ 3 ];
+	uint8_t ucDummy5[ 2 ];
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t ucDummy6;
+	#endif
+
+	#if ( configUSE_QUEUE_SETS == 1 )
+		void *pvDummy7;
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxDummy8;
+		uint8_t ucDummy9;
+	#endif
+
+} StaticQueue_t;
+typedef StaticQueue_t StaticSemaphore_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the event group structure used
+ * internally by FreeRTOS is not accessible to application code.  However, if
+ * the application writer wants to statically allocate the memory required to
+ * create an event group then the size of the event group object needs to be
+ * know.  The StaticEventGroup_t structure below is provided for this purpose.
+ * Its sizes and alignment requirements are guaranteed to match those of the
+ * genuine structure, no matter which architecture is being used, and no matter
+ * how the values in FreeRTOSConfig.h are set.  Its contents are somewhat
+ * obfuscated in the hope users will recognise that it would be unwise to make
+ * direct use of the structure members.
+ */
+typedef struct xSTATIC_EVENT_GROUP
+{
+	TickType_t xDummy1;
+	StaticList_t xDummy2;
+
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxDummy3;
+	#endif
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+			uint8_t ucDummy4;
+	#endif
+
+} StaticEventGroup_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the software timer structure used
+ * internally by FreeRTOS is not accessible to application code.  However, if
+ * the application writer wants to statically allocate the memory required to
+ * create a software timer then the size of the queue object needs to be know.
+ * The StaticTimer_t structure below is provided for this purpose.  Its sizes
+ * and alignment requirements are guaranteed to match those of the genuine
+ * structure, no matter which architecture is being used, and no matter how the
+ * values in FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in
+ * the hope users will recognise that it would be unwise to make direct use of
+ * the structure members.
+ */
+typedef struct xSTATIC_TIMER
+{
+	void				*pvDummy1;
+	StaticListItem_t	xDummy2;
+	TickType_t			xDummy3;
+	void 				*pvDummy5;
+	TaskFunction_t		pvDummy6;
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t		uxDummy7;
+	#endif
+	uint8_t 			ucDummy8;
+
+} StaticTimer_t;
+
+/*
+* In line with software engineering best practice, especially when supplying a
+* library that is likely to change in future versions, FreeRTOS implements a
+* strict data hiding policy.  This means the stream buffer structure used
+* internally by FreeRTOS is not accessible to application code.  However, if
+* the application writer wants to statically allocate the memory required to
+* create a stream buffer then the size of the stream buffer object needs to be
+* know.  The StaticStreamBuffer_t structure below is provided for this purpose.
+* Its size and alignment requirements are guaranteed to match those of the
+* genuine structure, no matter which architecture is being used, and no matter
+* how the values in FreeRTOSConfig.h are set.  Its contents are somewhat
+* obfuscated in the hope users will recognise that it would be unwise to make
+* direct use of the structure members.
+*/
+typedef struct xSTATIC_STREAM_BUFFER
+{
+	size_t uxDummy1[ 4 ];
+	void * pvDummy2[ 3 ];
+	uint8_t ucDummy3;
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxDummy4;
+	#endif
+} StaticStreamBuffer_t;
+
+/* Message buffers are built on stream buffers. */
+typedef StaticStreamBuffer_t StaticMessageBuffer_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* INC_FREERTOS_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/include/StackMacros.h b/FreeRTOSv10.2.1/FreeRTOS/Source/include/StackMacros.h
new file mode 100644
index 0000000..000d866
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/include/StackMacros.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef STACK_MACROS_H
+#define STACK_MACROS_H
+
+#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */
+	#warning The name of this file has changed to stack_macros.h.  Please update your code accordingly.  This source file (which has the original name) will be removed in future released.
+#endif
+
+/*
+ * Call the stack overflow hook function if the stack of the task being swapped
+ * out is currently overflowed, or looks like it might have overflowed in the
+ * past.
+ *
+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
+ * the current stack state only - comparing the current top of stack value to
+ * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
+ * will also cause the last few stack bytes to be checked to ensure the value
+ * to which the bytes were set when the task was created have not been
+ * overwritten.  Note this second test does not guarantee that an overflowed
+ * stack will always be recognised.
+ */
+
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )										\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+																										\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )									\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;							\
+		const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;											\
+																										\
+		if( ( pulStack[ 0 ] != ulCheckValue ) ||												\
+			( pulStack[ 1 ] != ulCheckValue ) ||												\
+			( pulStack[ 2 ] != ulCheckValue ) ||												\
+			( pulStack[ 3 ] != ulCheckValue ) )												\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																								\
+	{																																	\
+	int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;																		\
+	static const uint8_t ucExpectedStackBytes[] = {	tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };	\
+																																		\
+																																		\
+		pcEndOfStack -= sizeof( ucExpectedStackBytes );																					\
+																																		\
+		/* Has the extremity of the task stack ever been written over? */																\
+		if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )					\
+		{																																\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );									\
+		}																																\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+/* Remove stack overflow macro if not being used. */
+#ifndef taskCHECK_FOR_STACK_OVERFLOW
+	#define taskCHECK_FOR_STACK_OVERFLOW()
+#endif
+
+
+
+#endif /* STACK_MACROS_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/include/croutine.h b/FreeRTOSv10.2.1/FreeRTOS/Source/include/croutine.h
new file mode 100644
index 0000000..a781749
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/include/croutine.h
@@ -0,0 +1,720 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef CO_ROUTINE_H
+#define CO_ROUTINE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include croutine.h"
+#endif
+
+#include "list.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Used to hide the implementation of the co-routine control block.  The
+control block structure however has to be included in the header due to
+the macro implementation of the co-routine functionality. */
+typedef void * CoRoutineHandle_t;
+
+/* Defines the prototype to which co-routine functions must conform. */
+typedef void (*crCOROUTINE_CODE)( CoRoutineHandle_t, UBaseType_t );
+
+typedef struct corCoRoutineControlBlock
+{
+	crCOROUTINE_CODE 	pxCoRoutineFunction;
+	ListItem_t			xGenericListItem;	/*< List item used to place the CRCB in ready and blocked queues. */
+	ListItem_t			xEventListItem;		/*< List item used to place the CRCB in event lists. */
+	UBaseType_t 		uxPriority;			/*< The priority of the co-routine in relation to other co-routines. */
+	UBaseType_t 		uxIndex;			/*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */
+	uint16_t 			uxState;			/*< Used internally by the co-routine implementation. */
+} CRCB_t; /* Co-routine control block.  Note must be identical in size down to uxPriority with TCB_t. */
+
+/**
+ * croutine. h
+ *
+ BaseType_t xCoRoutineCreate(
+                                 crCOROUTINE_CODE pxCoRoutineCode,
+                                 UBaseType_t uxPriority,
+                                 UBaseType_t uxIndex
+                               );

+ *
+ * Create a new co-routine and add it to the list of co-routines that are
+ * ready to run.
+ *
+ * @param pxCoRoutineCode Pointer to the co-routine function.  Co-routine
+ * functions require special syntax - see the co-routine section of the WEB
+ * documentation for more information.
+ *
+ * @param uxPriority The priority with respect to other co-routines at which
+ *  the co-routine will run.
+ *
+ * @param uxIndex Used to distinguish between different co-routines that
+ * execute the same function.  See the example below and the co-routine section
+ * of the WEB documentation for further information.
+ *
+ * @return pdPASS if the co-routine was successfully created and added to a ready
+ * list, otherwise an error code defined with ProjDefs.h.
+ *
+ * Example usage:
+   
+ // Co-routine to be created.
+ void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ static const char cLedToFlash[ 2 ] = { 5, 6 };
+ static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // This co-routine just delays for a fixed period, then toggles
+         // an LED.  Two co-routines are created using this function, so
+         // the uxIndex parameter is used to tell the co-routine which
+         // LED to flash and how int32_t to delay.  This assumes xQueue has
+         // already been created.
+         vParTestToggleLED( cLedToFlash[ uxIndex ] );
+         crDELAY( xHandle, uxFlashRates[ uxIndex ] );
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+
+ // Function that creates two co-routines.
+ void vOtherFunction( void )
+ {
+ uint8_t ucParameterToPass;
+ TaskHandle_t xHandle;
+
+     // Create two co-routines at priority 0.  The first is given index 0
+     // so (from the code above) toggles LED 5 every 200 ticks.  The second
+     // is given index 1 so toggles LED 6 every 400 ticks.
+     for( uxIndex = 0; uxIndex < 2; uxIndex++ )
+     {
+         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
+     }
+ }
+   

+ * \defgroup xCoRoutineCreate xCoRoutineCreate
+ * \ingroup Tasks
+ */
+BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex );
+
+
+/**
+ * croutine. h
+ *
+ void vCoRoutineSchedule( void );

+ *
+ * Run a co-routine.
+ *
+ * vCoRoutineSchedule() executes the highest priority co-routine that is able
+ * to run.  The co-routine will execute until it either blocks, yields or is
+ * preempted by a task.  Co-routines execute cooperatively so one
+ * co-routine cannot be preempted by another, but can be preempted by a task.
+ *
+ * If an application comprises of both tasks and co-routines then
+ * vCoRoutineSchedule should be called from the idle task (in an idle task
+ * hook).
+ *
+ * Example usage:
+   
+ // This idle task hook will schedule a co-routine each time it is called.
+ // The rest of the idle task will execute between co-routine calls.
+ void vApplicationIdleHook( void )
+ {
+	vCoRoutineSchedule();
+ }
+
+ // Alternatively, if you do not require any other part of the idle task to
+ // execute, the idle task hook can call vCoRoutineScheduler() within an
+ // infinite loop.
+ void vApplicationIdleHook( void )
+ {
+    for( ;; )
+    {
+        vCoRoutineSchedule();
+    }
+ }
+ 

+ * \defgroup vCoRoutineSchedule vCoRoutineSchedule
+ * \ingroup Tasks
+ */
+void vCoRoutineSchedule( void );
+
+/**
+ * croutine. h
+ * 
+ crSTART( CoRoutineHandle_t xHandle );

+ *
+ * This macro MUST always be called at the start of a co-routine function.
+ *
+ * Example usage:
+   
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }

+ * \defgroup crSTART crSTART
+ * \ingroup Tasks
+ */
+#define crSTART( pxCRCB ) switch( ( ( CRCB_t * )( pxCRCB ) )->uxState ) { case 0:
+
+/**
+ * croutine. h
+ * 
+ crEND();

+ *
+ * This macro MUST always be called at the end of a co-routine function.
+ *
+ * Example usage:
+   
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }

+ * \defgroup crSTART crSTART
+ * \ingroup Tasks
+ */
+#define crEND() }
+
+/*
+ * These macros are intended for internal use by the co-routine implementation
+ * only.  The macros should not be used directly by application writers.
+ */
+#define crSET_STATE0( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2):
+#define crSET_STATE1( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1):
+
+/**
+ * croutine. h
+ *
+ crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );

+ *
+ * Delay a co-routine for a fixed period of time.
+ *
+ * crDELAY can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * @param xHandle The handle of the co-routine to delay.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should delay
+ * for.  The actual amount of time this equates to is defined by
+ * configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant portTICK_PERIOD_MS
+ * can be used to convert ticks to milliseconds.
+ *
+ * Example usage:
+   
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ // We are to delay for 200ms.
+ static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+        // Delay for 200ms.
+        crDELAY( xHandle, xDelayTime );
+
+        // Do something here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }

+ * \defgroup crDELAY crDELAY
+ * \ingroup Tasks
+ */
+#define crDELAY( xHandle, xTicksToDelay )												\
+	if( ( xTicksToDelay ) > 0 )															\
+	{																					\
+		vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL );							\
+	}																					\
+	crSET_STATE0( ( xHandle ) );
+
+/**
+ * 
+ crQUEUE_SEND(
+                  CoRoutineHandle_t xHandle,
+                  QueueHandle_t pxQueue,
+                  void *pvItemToQueue,
+                  TickType_t xTicksToWait,
+                  BaseType_t *pxResult
+             )

+ *
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
+ *
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
+ * xQueueSend() and xQueueReceive() can only be used from tasks.
+ *
+ * crQUEUE_SEND can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xHandle The handle of the calling co-routine.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param pxQueue The handle of the queue on which the data will be posted.
+ * The handle is obtained as the return value when the queue is created using
+ * the xQueueCreate() API function.
+ *
+ * @param pvItemToQueue A pointer to the data being posted onto the queue.
+ * The number of bytes of each queued item is specified when the queue is
+ * created.  This number of bytes is copied from pvItemToQueue into the queue
+ * itself.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should block
+ * to wait for space to become available on the queue, should space not be
+ * available immediately. The actual amount of time this equates to is defined
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant
+ * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example
+ * below).
+ *
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
+ * data was successfully posted onto the queue, otherwise it will be set to an
+ * error defined within ProjDefs.h.
+ *
+ * Example usage:
+   
+ // Co-routine function that blocks for a fixed period then posts a number onto
+ // a queue.
+ static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xNumberToPost = 0;
+ static BaseType_t xResult;
+
+    // Co-routines must begin with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // This assumes the queue has already been created.
+        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
+
+        if( xResult != pdPASS )
+        {
+            // The message was not posted!
+        }
+
+        // Increment the number to be posted onto the queue.
+        xNumberToPost++;
+
+        // Delay for 100 ticks.
+        crDELAY( xHandle, 100 );
+    }
+
+    // Co-routines must end with a call to crEND().
+    crEND();
+ }

+ * \defgroup crQUEUE_SEND crQUEUE_SEND
+ * \ingroup Tasks
+ */
+#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult )			\
+{																						\
+	*( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) );	\
+	if( *( pxResult ) == errQUEUE_BLOCKED )												\
+	{																					\
+		crSET_STATE0( ( xHandle ) );													\
+		*pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 );					\
+	}																					\
+	if( *pxResult == errQUEUE_YIELD )													\
+	{																					\
+		crSET_STATE1( ( xHandle ) );													\
+		*pxResult = pdPASS;																\
+	}																					\
+}
+
+/**
+ * croutine. h
+ * 
+  crQUEUE_RECEIVE(
+                     CoRoutineHandle_t xHandle,
+                     QueueHandle_t pxQueue,
+                     void *pvBuffer,
+                     TickType_t xTicksToWait,
+                     BaseType_t *pxResult
+                 )

+ *
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
+ *
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
+ * xQueueSend() and xQueueReceive() can only be used from tasks.
+ *
+ * crQUEUE_RECEIVE can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xHandle The handle of the calling co-routine.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param pxQueue The handle of the queue from which the data will be received.
+ * The handle is obtained as the return value when the queue is created using
+ * the xQueueCreate() API function.
+ *
+ * @param pvBuffer The buffer into which the received item is to be copied.
+ * The number of bytes of each queued item is specified when the queue is
+ * created.  This number of bytes is copied into pvBuffer.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should block
+ * to wait for data to become available from the queue, should data not be
+ * available immediately. The actual amount of time this equates to is defined
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant
+ * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the
+ * crQUEUE_SEND example).
+ *
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
+ * data was successfully retrieved from the queue, otherwise it will be set to
+ * an error code as defined within ProjDefs.h.
+ *
+ * Example usage:
+ 
+ // A co-routine receives the number of an LED to flash from a queue.  It
+ // blocks on the queue until the number is received.
+ static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xResult;
+ static UBaseType_t uxLEDToFlash;
+
+    // All co-routines must start with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // Wait for data to become available on the queue.
+        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+        if( xResult == pdPASS )
+        {
+            // We received the LED to flash - flash it!
+            vParTestToggleLED( uxLEDToFlash );
+        }
+    }
+
+    crEND();
+ }

+ * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE
+ * \ingroup Tasks
+ */
+#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult )			\
+{																						\
+	*( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) );		\
+	if( *( pxResult ) == errQUEUE_BLOCKED ) 											\
+	{																					\
+		crSET_STATE0( ( xHandle ) );													\
+		*( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 );				\
+	}																					\
+	if( *( pxResult ) == errQUEUE_YIELD )												\
+	{																					\
+		crSET_STATE1( ( xHandle ) );													\
+		*( pxResult ) = pdPASS;															\
+	}																					\
+}
+
+/**
+ * croutine. h
+ * 
+  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvItemToQueue,
+                            BaseType_t xCoRoutinePreviouslyWoken
+                       )

+ *
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
+ * functions used by tasks.
+ *
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and
+ * ISR.
+ *
+ * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue
+ * that is being used from within a co-routine.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto
+ * the same queue multiple times from a single interrupt.  The first call
+ * should always pass in pdFALSE.  Subsequent calls should pass in
+ * the value returned from the previous call.
+ *
+ * @return pdTRUE if a co-routine was woken by posting onto the queue.  This is
+ * used by the ISR to determine if a context switch may be required following
+ * the ISR.
+ *
+ * Example usage:
+ 
+ // A co-routine that blocks on a queue waiting for characters to be received.
+ static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ char cRxedChar;
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Wait for data to become available on the queue.  This assumes the
+         // queue xCommsRxQueue has already been created!
+         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+         // Was a character received?
+         if( xResult == pdPASS )
+         {
+             // Process the character here.
+         }
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to send characters received on a serial port to
+ // a co-routine.
+ void vUART_ISR( void )
+ {
+ char cRxedChar;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     // We loop around reading characters until there are none left in the UART.
+     while( UART_RX_REG_NOT_EMPTY() )
+     {
+         // Obtain the character from the UART.
+         cRxedChar = UART_RX_REG;
+
+         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
+         // the first time around the loop.  If the post causes a co-routine
+         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
+         // In this manner we can ensure that if more than one co-routine is
+         // blocked on the queue only one is woken by this ISR no matter how
+         // many characters are posted to the queue.
+         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
+     }
+ }

+ * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR
+ * \ingroup Tasks
+ */
+#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) )
+
+
+/**
+ * croutine. h
+ * 
+  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvBuffer,
+                            BaseType_t * pxCoRoutineWoken
+                       )

+ *
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
+ * functions used by tasks.
+ *
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and
+ * ISR.
+ *
+ * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data
+ * from a queue that is being used from within a co-routine (a co-routine
+ * posted to the queue).
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvBuffer A pointer to a buffer into which the received item will be
+ * placed.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from the queue into
+ * pvBuffer.
+ *
+ * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become
+ * available on the queue.  If crQUEUE_RECEIVE_FROM_ISR causes such a
+ * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise
+ * *pxCoRoutineWoken will remain unchanged.
+ *
+ * @return pdTRUE an item was successfully received from the queue, otherwise
+ * pdFALSE.
+ *
+ * Example usage:
+ 
+ // A co-routine that posts a character to a queue then blocks for a fixed
+ // period.  The character is incremented each time.
+ static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // cChar holds its value while this co-routine is blocked and must therefore
+ // be declared static.
+ static char cCharToTx = 'a';
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Send the next character to the queue.
+         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
+
+         if( xResult == pdPASS )
+         {
+             // The character was successfully posted to the queue.
+         }
+		 else
+		 {
+			// Could not post the character to the queue.
+		 }
+
+         // Enable the UART Tx interrupt to cause an interrupt in this
+		 // hypothetical UART.  The interrupt will obtain the character
+		 // from the queue and send it.
+		 ENABLE_RX_INTERRUPT();
+
+		 // Increment to the next character then block for a fixed period.
+		 // cCharToTx will maintain its value across the delay as it is
+		 // declared static.
+		 cCharToTx++;
+		 if( cCharToTx > 'x' )
+		 {
+			cCharToTx = 'a';
+		 }
+		 crDELAY( 100 );
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to receive characters to send on a UART.
+ void vUART_ISR( void )
+ {
+ char cCharToTx;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     while( UART_TX_REG_EMPTY() )
+     {
+         // Are there any characters in the queue waiting to be sent?
+		 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
+		 // is woken by the post - ensuring that only a single co-routine is
+		 // woken no matter how many times we go around this loop.
+         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
+		 {
+			 SEND_CHARACTER( cCharToTx );
+		 }
+     }
+ }

+ * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR
+ * \ingroup Tasks
+ */
+#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) )
+
+/*
+ * This function is intended for internal use by the co-routine macros only.
+ * The macro nature of the co-routine implementation requires that the
+ * prototype appears here.  The function should not be used by application
+ * writers.
+ *
+ * Removes the current co-routine from its ready list and places it in the
+ * appropriate delayed list.
+ */
+void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList );
+
+/*
+ * This function is intended for internal use by the queue implementation only.
+ * The function should not be used by application writers.
+ *
+ * Removes the highest priority co-routine from the event list and places it in
+ * the pending ready list.
+ */
+BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CO_ROUTINE_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/include/deprecated_definitions.h b/FreeRTOSv10.2.1/FreeRTOS/Source/include/deprecated_definitions.h
new file mode 100644
index 0000000..4d0ce01
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/include/deprecated_definitions.h
@@ -0,0 +1,279 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef DEPRECATED_DEFINITIONS_H
+#define DEPRECATED_DEFINITIONS_H
+
+
+/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
+pre-processor definition was used to ensure the pre-processor found the correct
+portmacro.h file for the port being used.  That scheme was deprecated in favour
+of setting the compiler's include path such that it found the correct
+portmacro.h file - removing the need for the constant and allowing the
+portmacro.h file to be located anywhere in relation to the port being used.  The
+definitions below remain in the code for backward compatibility only.  New
+projects should not use them. */
+
+#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT
+	#include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h"
+	typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT
+	#include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h"
+	typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef GCC_MEGA_AVR
+	#include "../portable/GCC/ATMega323/portmacro.h"
+#endif
+
+#ifdef IAR_MEGA_AVR
+	#include "../portable/IAR/ATMega323/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC24_PORT
+	#include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
+#endif
+
+#ifdef MPLAB_DSPIC_PORT
+	#include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC18F_PORT
+	#include "../../Source/portable/MPLAB/PIC18F/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC32MX_PORT
+	#include "../../Source/portable/MPLAB/PIC32MX/portmacro.h"
+#endif
+
+#ifdef _FEDPICC
+	#include "libFreeRTOS/Include/portmacro.h"
+#endif
+
+#ifdef SDCC_CYGNAL
+	#include "../../Source/portable/SDCC/Cygnal/portmacro.h"
+#endif
+
+#ifdef GCC_ARM7
+	#include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h"
+#endif
+
+#ifdef GCC_ARM7_ECLIPSE
+	#include "portmacro.h"
+#endif
+
+#ifdef ROWLEY_LPC23xx
+	#include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h"
+#endif
+
+#ifdef IAR_MSP430
+	#include "..\..\Source\portable\IAR\MSP430\portmacro.h"
+#endif
+
+#ifdef GCC_MSP430
+	#include "../../Source/portable/GCC/MSP430F449/portmacro.h"
+#endif
+
+#ifdef ROWLEY_MSP430
+	#include "../../Source/portable/Rowley/MSP430F449/portmacro.h"
+#endif
+
+#ifdef ARM7_LPC21xx_KEIL_RVDS
+	#include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h"
+#endif
+
+#ifdef SAM7_GCC
+	#include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h"
+#endif
+
+#ifdef SAM7_IAR
+	#include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h"
+#endif
+
+#ifdef SAM9XE_IAR
+	#include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h"
+#endif
+
+#ifdef LPC2000_IAR
+	#include "..\..\Source\portable\IAR\LPC2000\portmacro.h"
+#endif
+
+#ifdef STR71X_IAR
+	#include "..\..\Source\portable\IAR\STR71x\portmacro.h"
+#endif
+
+#ifdef STR75X_IAR
+	#include "..\..\Source\portable\IAR\STR75x\portmacro.h"
+#endif
+
+#ifdef STR75X_GCC
+	#include "..\..\Source\portable\GCC\STR75x\portmacro.h"
+#endif
+
+#ifdef STR91X_IAR
+	#include "..\..\Source\portable\IAR\STR91x\portmacro.h"
+#endif
+
+#ifdef GCC_H8S
+	#include "../../Source/portable/GCC/H8S2329/portmacro.h"
+#endif
+
+#ifdef GCC_AT91FR40008
+	#include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h"
+#endif
+
+#ifdef RVDS_ARMCM3_LM3S102
+	#include "../../Source/portable/RVDS/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef GCC_ARMCM3_LM3S102
+	#include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef GCC_ARMCM3
+	#include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef IAR_ARM_CM3
+	#include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef IAR_ARMCM3_LM
+	#include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef HCS12_CODE_WARRIOR
+	#include "../../Source/portable/CodeWarrior/HCS12/portmacro.h"
+#endif
+
+#ifdef MICROBLAZE_GCC
+	#include "../../Source/portable/GCC/MicroBlaze/portmacro.h"
+#endif
+
+#ifdef TERN_EE
+	#include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h"
+#endif
+
+#ifdef GCC_HCS12
+	#include "../../Source/portable/GCC/HCS12/portmacro.h"
+#endif
+
+#ifdef GCC_MCF5235
+    #include "../../Source/portable/GCC/MCF5235/portmacro.h"
+#endif
+
+#ifdef COLDFIRE_V2_GCC
+	#include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h"
+#endif
+
+#ifdef COLDFIRE_V2_CODEWARRIOR
+	#include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h"
+#endif
+
+#ifdef GCC_PPC405
+	#include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h"
+#endif
+
+#ifdef GCC_PPC440
+	#include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h"
+#endif
+
+#ifdef _16FX_SOFTUNE
+	#include "..\..\Source\portable\Softune\MB96340\portmacro.h"
+#endif
+
+#ifdef BCC_INDUSTRIAL_PC_PORT
+	/* A short file name has to be used in place of the normal
+	FreeRTOSConfig.h when using the Borland compiler. */
+	#include "frconfig.h"
+	#include "..\portable\BCC\16BitDOS\PC\prtmacro.h"
+    typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef BCC_FLASH_LITE_186_PORT
+	/* A short file name has to be used in place of the normal
+	FreeRTOSConfig.h when using the Borland compiler. */
+	#include "frconfig.h"
+	#include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h"
+    typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef __GNUC__
+   #ifdef __AVR32_AVR32A__
+	   #include "portmacro.h"
+   #endif
+#endif
+
+#ifdef __ICCAVR32__
+   #ifdef __CORE__
+      #if __CORE__ == __AVR32A__
+	      #include "portmacro.h"
+      #endif
+   #endif
+#endif
+
+#ifdef __91467D
+	#include "portmacro.h"
+#endif
+
+#ifdef __96340
+	#include "portmacro.h"
+#endif
+
+
+#ifdef __IAR_V850ES_Fx3__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx3__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx3_L__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx2__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Hx2__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_78K0R_Kx3__
+	#include "../../Source/portable/IAR/78K0R/portmacro.h"
+#endif
+
+#ifdef __IAR_78K0R_Kx3L__
+	#include "../../Source/portable/IAR/78K0R/portmacro.h"
+#endif
+
+#endif /* DEPRECATED_DEFINITIONS_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/include/event_groups.h b/FreeRTOSv10.2.1/FreeRTOS/Source/include/event_groups.h
new file mode 100644
index 0000000..522b0b6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/include/event_groups.h
@@ -0,0 +1,757 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef EVENT_GROUPS_H
+#define EVENT_GROUPS_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include event_groups.h"
+#endif
+
+/* FreeRTOS includes. */
+#include "timers.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * An event group is a collection of bits to which an application can assign a
+ * meaning.  For example, an application may create an event group to convey
+ * the status of various CAN bus related events in which bit 0 might mean "A CAN
+ * message has been received and is ready for processing", bit 1 might mean "The
+ * application has queued a message that is ready for sending onto the CAN
+ * network", and bit 2 might mean "It is time to send a SYNC message onto the
+ * CAN network" etc.  A task can then test the bit values to see which events
+ * are active, and optionally enter the Blocked state to wait for a specified
+ * bit or a group of specified bits to be active.  To continue the CAN bus
+ * example, a CAN controlling task can enter the Blocked state (and therefore
+ * not consume any processing time) until either bit 0, bit 1 or bit 2 are
+ * active, at which time the bit that was actually active would inform the task
+ * which action it had to take (process a received message, send a message, or
+ * send a SYNC).
+ *
+ * The event groups implementation contains intelligence to avoid race
+ * conditions that would otherwise occur were an application to use a simple
+ * variable for the same purpose.  This is particularly important with respect
+ * to when a bit within an event group is to be cleared, and when bits have to
+ * be set and then tested atomically - as is the case where event groups are
+ * used to create a synchronisation point between multiple tasks (a
+ * 'rendezvous').
+ *
+ * \defgroup EventGroup
+ */
+
+
+
+/**
+ * event_groups.h
+ *
+ * Type by which event groups are referenced.  For example, a call to
+ * xEventGroupCreate() returns an EventGroupHandle_t variable that can then
+ * be used as a parameter to other event group functions.
+ *
+ * \defgroup EventGroupHandle_t EventGroupHandle_t
+ * \ingroup EventGroup
+ */
+struct EventGroupDef_t;
+typedef struct EventGroupDef_t * EventGroupHandle_t;
+
+/*
+ * The type that holds event bits always matches TickType_t - therefore the
+ * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1,
+ * 32 bits if set to 0.
+ *
+ * \defgroup EventBits_t EventBits_t
+ * \ingroup EventGroup
+ */
+typedef TickType_t EventBits_t;
+
+/**
+ * event_groups.h
+ *
+ EventGroupHandle_t xEventGroupCreate( void );
+ 

+ *
+ * Create a new event group.
+ *
+ * Internally, within the FreeRTOS implementation, event groups use a [small]
+ * block of memory, in which the event group's structure is stored.  If an event
+ * groups is created using xEventGropuCreate() then the required memory is
+ * automatically dynamically allocated inside the xEventGroupCreate() function.
+ * (see http://www.freertos.org/a00111.html).  If an event group is created
+ * using xEventGropuCreateStatic() then the application writer must instead
+ * provide the memory that will get used by the event group.
+ * xEventGroupCreateStatic() therefore allows an event group to be created
+ * without using any dynamic memory allocation.
+ *
+ * Although event groups are not related to ticks, for internal implementation
+ * reasons the number of bits available for use in an event group is dependent
+ * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If
+ * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit
+ * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has
+ * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store
+ * event bits within an event group.
+ *
+ * @return If the event group was created then a handle to the event group is
+ * returned.  If there was insufficient FreeRTOS heap available to create the
+ * event group then NULL is returned.  See http://www.freertos.org/a00111.html
+ *
+ * Example usage:
+   
+	// Declare a variable to hold the created event group.
+	EventGroupHandle_t xCreatedEventGroup;
+
+	// Attempt to create the event group.
+	xCreatedEventGroup = xEventGroupCreate();
+
+	// Was the event group created successfully?
+	if( xCreatedEventGroup == NULL )
+	{
+		// The event group was not created because there was insufficient
+		// FreeRTOS heap available.
+	}
+	else
+	{
+		// The event group was created.
+	}
+   

+ * \defgroup xEventGroupCreate xEventGroupCreate
+ * \ingroup EventGroup
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * event_groups.h
+ *
+ EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );
+ 

+ *
+ * Create a new event group.
+ *
+ * Internally, within the FreeRTOS implementation, event groups use a [small]
+ * block of memory, in which the event group's structure is stored.  If an event
+ * groups is created using xEventGropuCreate() then the required memory is
+ * automatically dynamically allocated inside the xEventGroupCreate() function.
+ * (see http://www.freertos.org/a00111.html).  If an event group is created
+ * using xEventGropuCreateStatic() then the application writer must instead
+ * provide the memory that will get used by the event group.
+ * xEventGroupCreateStatic() therefore allows an event group to be created
+ * without using any dynamic memory allocation.
+ *
+ * Although event groups are not related to ticks, for internal implementation
+ * reasons the number of bits available for use in an event group is dependent
+ * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If
+ * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit
+ * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has
+ * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store
+ * event bits within an event group.
+ *
+ * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type
+ * StaticEventGroup_t, which will be then be used to hold the event group's data
+ * structures, removing the need for the memory to be allocated dynamically.
+ *
+ * @return If the event group was created then a handle to the event group is
+ * returned.  If pxEventGroupBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+   
+	// StaticEventGroup_t is a publicly accessible structure that has the same
+	// size and alignment requirements as the real event group structure.  It is
+	// provided as a mechanism for applications to know the size of the event
+	// group (which is dependent on the architecture and configuration file
+	// settings) without breaking the strict data hiding policy by exposing the
+	// real event group internals.  This StaticEventGroup_t variable is passed
+	// into the xSemaphoreCreateEventGroupStatic() function and is used to store
+	// the event group's data structures
+	StaticEventGroup_t xEventGroupBuffer;
+
+	// Create the event group without dynamically allocating any memory.
+	xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
+   

+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * event_groups.h
+ *
+	EventBits_t xEventGroupWaitBits( 	EventGroupHandle_t xEventGroup,
+										const EventBits_t uxBitsToWaitFor,
+										const BaseType_t xClearOnExit,
+										const BaseType_t xWaitForAllBits,
+										const TickType_t xTicksToWait );
+ 

+ *
+ * [Potentially] block to wait for one or more bits to be set within a
+ * previously created event group.
+ *
+ * This function cannot be called from an interrupt.
+ *
+ * @param xEventGroup The event group in which the bits are being tested.  The
+ * event group must have previously been created using a call to
+ * xEventGroupCreate().
+ *
+ * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
+ * inside the event group.  For example, to wait for bit 0 and/or bit 2 set
+ * uxBitsToWaitFor to 0x05.  To wait for bits 0 and/or bit 1 and/or bit 2 set
+ * uxBitsToWaitFor to 0x07.  Etc.
+ *
+ * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within
+ * uxBitsToWaitFor that are set within the event group will be cleared before
+ * xEventGroupWaitBits() returns if the wait condition was met (if the function
+ * returns for a reason other than a timeout).  If xClearOnExit is set to
+ * pdFALSE then the bits set in the event group are not altered when the call to
+ * xEventGroupWaitBits() returns.
+ *
+ * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then
+ * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor
+ * are set or the specified block time expires.  If xWaitForAllBits is set to
+ * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set
+ * in uxBitsToWaitFor is set or the specified block time expires.  The block
+ * time is specified by the xTicksToWait parameter.
+ *
+ * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
+ * for one/all (depending on the xWaitForAllBits value) of the bits specified by
+ * uxBitsToWaitFor to become set.
+ *
+ * @return The value of the event group at the time either the bits being waited
+ * for became set, or the block time expired.  Test the return value to know
+ * which bits were set.  If xEventGroupWaitBits() returned because its timeout
+ * expired then not all the bits being waited for will be set.  If
+ * xEventGroupWaitBits() returned because the bits it was waiting for were set
+ * then the returned value is the event group value before any bits were
+ * automatically cleared in the case that xClearOnExit parameter was set to
+ * pdTRUE.
+ *
+ * Example usage:
+   
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+   const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+		// Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
+		// the event group.  Clear the bits before exiting.
+		uxBits = xEventGroupWaitBits(
+					xEventGroup,	// The event group being tested.
+					BIT_0 | BIT_4,	// The bits within the event group to wait for.
+					pdTRUE,			// BIT_0 and BIT_4 should be cleared before returning.
+					pdFALSE,		// Don't wait for both bits, either bit will do.
+					xTicksToWait );	// Wait a maximum of 100ms for either bit to be set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// xEventGroupWaitBits() returned because both bits were set.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_0 was set.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_4 was set.
+		}
+		else
+		{
+			// xEventGroupWaitBits() returned because xTicksToWait ticks passed
+			// without either BIT_0 or BIT_4 becoming set.
+		}
+   }
+   

+ * \defgroup xEventGroupWaitBits xEventGroupWaitBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *
+	EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
+ 

+ *
+ * Clear bits within an event group.  This function cannot be called from an
+ * interrupt.
+ *
+ * @param xEventGroup The event group in which the bits are to be cleared.
+ *
+ * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear
+ * in the event group.  For example, to clear bit 3 only, set uxBitsToClear to
+ * 0x08.  To clear bit 3 and bit 0 set uxBitsToClear to 0x09.
+ *
+ * @return The value of the event group before the specified bits were cleared.
+ *
+ * Example usage:
+   
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Clear bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupClearBits(
+								xEventGroup,	// The event group being updated.
+								BIT_0 | BIT_4 );// The bits being cleared.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 were set before xEventGroupClearBits() was
+			// called.  Both will now be clear (not set).
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 were set in the first place.
+		}
+   }
+   

+ * \defgroup xEventGroupClearBits xEventGroupClearBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *
+	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+ 

+ *
+ * A version of xEventGroupClearBits() that can be called from an interrupt.
+ *
+ * Setting bits in an event group is not a deterministic operation because there
+ * are an unknown number of tasks that may be waiting for the bit or bits being
+ * set.  FreeRTOS does not allow nondeterministic operations to be performed
+ * while interrupts are disabled, so protects event groups that are accessed
+ * from tasks by suspending the scheduler rather than disabling interrupts.  As
+ * a result event groups cannot be accessed directly from an interrupt service
+ * routine.  Therefore xEventGroupClearBitsFromISR() sends a message to the
+ * timer task to have the clear operation performed in the context of the timer
+ * task.
+ *
+ * @param xEventGroup The event group in which the bits are to be cleared.
+ *
+ * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear.
+ * For example, to clear bit 3 only, set uxBitsToClear to 0x08.  To clear bit 3
+ * and bit 0 set uxBitsToClear to 0x09.
+ *
+ * @return If the request to execute the function was posted successfully then
+ * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned
+ * if the timer service queue was full.
+ *
+ * Example usage:
+   
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+		// Clear bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupClearBitsFromISR(
+							xEventGroup,	 // The event group being updated.
+							BIT_0 | BIT_4 ); // The bits being set.
+
+		if( xResult == pdPASS )
+		{
+			// The message was posted successfully.
+		}
+  }
+   

+ * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR
+ * \ingroup EventGroup
+ */
+#if( configUSE_TRACE_FACILITY == 1 )
+	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
+#else
+	#define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL )
+#endif
+
+/**
+ * event_groups.h
+ *
+	EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+ 

+ *
+ * Set bits within an event group.
+ * This function cannot be called from an interrupt.  xEventGroupSetBitsFromISR()
+ * is a version that can be called from an interrupt.
+ *
+ * Setting bits in an event group will automatically unblock tasks that are
+ * blocked waiting for the bits.
+ *
+ * @param xEventGroup The event group in which the bits are to be set.
+ *
+ * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
+ * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3
+ * and bit 0 set uxBitsToSet to 0x09.
+ *
+ * @return The value of the event group at the time the call to
+ * xEventGroupSetBits() returns.  There are two reasons why the returned value
+ * might have the bits specified by the uxBitsToSet parameter cleared.  First,
+ * if setting a bit results in a task that was waiting for the bit leaving the
+ * blocked state then it is possible the bit will be cleared automatically
+ * (see the xClearBitOnExit parameter of xEventGroupWaitBits()).  Second, any
+ * unblocked (or otherwise Ready state) task that has a priority above that of
+ * the task that called xEventGroupSetBits() will execute and may change the
+ * event group value before the call to xEventGroupSetBits() returns.
+ *
+ * Example usage:
+   
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupSetBits(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4 );// The bits being set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 remained set when the function returned.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 remained set when the function returned, but bit 4 was
+			// cleared.  It might be that bit 4 was cleared automatically as a
+			// task that was waiting for bit 4 was removed from the Blocked
+			// state.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 remained set when the function returned, but bit 0 was
+			// cleared.  It might be that bit 0 was cleared automatically as a
+			// task that was waiting for bit 0 was removed from the Blocked
+			// state.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 remained set.  It might be that a task
+			// was waiting for both of the bits to be set, and the bits were
+			// cleared as the task left the Blocked state.
+		}
+   }
+   

+ * \defgroup xEventGroupSetBits xEventGroupSetBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *
+	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
+ 

+ *
+ * A version of xEventGroupSetBits() that can be called from an interrupt.
+ *
+ * Setting bits in an event group is not a deterministic operation because there
+ * are an unknown number of tasks that may be waiting for the bit or bits being
+ * set.  FreeRTOS does not allow nondeterministic operations to be performed in
+ * interrupts or from critical sections.  Therefore xEventGroupSetBitsFromISR()
+ * sends a message to the timer task to have the set operation performed in the
+ * context of the timer task - where a scheduler lock is used in place of a
+ * critical section.
+ *
+ * @param xEventGroup The event group in which the bits are to be set.
+ *
+ * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
+ * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3
+ * and bit 0 set uxBitsToSet to 0x09.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task.  If the
+ * priority of the timer daemon task is higher than the priority of the
+ * currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE by
+ * xEventGroupSetBitsFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits.  For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
+ * example code below.
+ *
+ * @return If the request to execute the function was posted successfully then
+ * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned
+ * if the timer service queue was full.
+ *
+ * Example usage:
+   
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+   BaseType_t xHigherPriorityTaskWoken, xResult;
+
+		// xHigherPriorityTaskWoken must be initialised to pdFALSE.
+		xHigherPriorityTaskWoken = pdFALSE;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupSetBitsFromISR(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4   // The bits being set.
+							&xHigherPriorityTaskWoken );
+
+		// Was the message posted successfully?
+		if( xResult == pdPASS )
+		{
+			// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+			// switch should be requested.  The macro used is port specific and
+			// will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+			// refer to the documentation page for the port being used.
+			portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+		}
+  }
+   

+ * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR
+ * \ingroup EventGroup
+ */
+#if( configUSE_TRACE_FACILITY == 1 )
+	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#else
+	#define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken )
+#endif
+
+/**
+ * event_groups.h
+ *
+	EventBits_t xEventGroupSync(	EventGroupHandle_t xEventGroup,
+									const EventBits_t uxBitsToSet,
+									const EventBits_t uxBitsToWaitFor,
+									TickType_t xTicksToWait );
+ 

+ *
+ * Atomically set bits within an event group, then wait for a combination of
+ * bits to be set within the same event group.  This functionality is typically
+ * used to synchronise multiple tasks, where each task has to wait for the other
+ * tasks to reach a synchronisation point before proceeding.
+ *
+ * This function cannot be used from an interrupt.
+ *
+ * The function will return before its block time expires if the bits specified
+ * by the uxBitsToWait parameter are set, or become set within that time.  In
+ * this case all the bits specified by uxBitsToWait will be automatically
+ * cleared before the function returns.
+ *
+ * @param xEventGroup The event group in which the bits are being tested.  The
+ * event group must have previously been created using a call to
+ * xEventGroupCreate().
+ *
+ * @param uxBitsToSet The bits to set in the event group before determining
+ * if, and possibly waiting for, all the bits specified by the uxBitsToWait
+ * parameter are set.
+ *
+ * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
+ * inside the event group.  For example, to wait for bit 0 and bit 2 set
+ * uxBitsToWaitFor to 0x05.  To wait for bits 0 and bit 1 and bit 2 set
+ * uxBitsToWaitFor to 0x07.  Etc.
+ *
+ * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
+ * for all of the bits specified by uxBitsToWaitFor to become set.
+ *
+ * @return The value of the event group at the time either the bits being waited
+ * for became set, or the block time expired.  Test the return value to know
+ * which bits were set.  If xEventGroupSync() returned because its timeout
+ * expired then not all the bits being waited for will be set.  If
+ * xEventGroupSync() returned because all the bits it was waiting for were
+ * set then the returned value is the event group value before any bits were
+ * automatically cleared.
+ *
+ * Example usage:
+ 
+ // Bits used by the three tasks.
+ #define TASK_0_BIT		( 1 << 0 )
+ #define TASK_1_BIT		( 1 << 1 )
+ #define TASK_2_BIT		( 1 << 2 )
+
+ #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
+
+ // Use an event group to synchronise three tasks.  It is assumed this event
+ // group has already been created elsewhere.
+ EventGroupHandle_t xEventBits;
+
+ void vTask0( void *pvParameters )
+ {
+ EventBits_t uxReturn;
+ TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 0 in the event flag to note this task has reached the
+		// sync point.  The other two tasks will set the other two bits defined
+		// by ALL_SYNC_BITS.  All three tasks have reached the synchronisation
+		// point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms
+		// for this to happen.
+		uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
+
+		if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
+		{
+			// All three tasks reached the synchronisation point before the call
+			// to xEventGroupSync() timed out.
+		}
+	}
+ }
+
+ void vTask1( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 1 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	 }
+ }
+
+ void vTask2( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 2 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	}
+ }
+
+ 

+ * \defgroup xEventGroupSync xEventGroupSync
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+
+/**
+ * event_groups.h
+ *
+	EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
+ 

+ *
+ * Returns the current value of the bits in an event group.  This function
+ * cannot be used from an interrupt.
+ *
+ * @param xEventGroup The event group being queried.
+ *
+ * @return The event group bits at the time xEventGroupGetBits() was called.
+ *
+ * \defgroup xEventGroupGetBits xEventGroupGetBits
+ * \ingroup EventGroup
+ */
+#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 )
+
+/**
+ * event_groups.h
+ *
+	EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
+ 

+ *
+ * A version of xEventGroupGetBits() that can be called from an ISR.
+ *
+ * @param xEventGroup The event group being queried.
+ *
+ * @return The event group bits at the time xEventGroupGetBitsFromISR() was called.
+ *
+ * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *
+	void xEventGroupDelete( EventGroupHandle_t xEventGroup );
+ 

+ *
+ * Delete an event group that was previously created by a call to
+ * xEventGroupCreate().  Tasks that are blocked on the event group will be
+ * unblocked and obtain 0 as the event group's value.
+ *
+ * @param xEventGroup The event group being deleted.
+ */
+void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
+
+/* For internal use only. */
+void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION;
+void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
+
+
+#if (configUSE_TRACE_FACILITY == 1)
+	UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) PRIVILEGED_FUNCTION;
+	void vEventGroupSetNumber( void* xEventGroup, UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EVENT_GROUPS_H */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/include/list.h b/FreeRTOSv10.2.1/FreeRTOS/Source/include/list.h
new file mode 100644
index 0000000..b2bb46d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/include/list.h
@@ -0,0 +1,412 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * This is the list implementation used by the scheduler.  While it is tailored
+ * heavily for the schedulers needs, it is also available for use by
+ * application code.
+ *
+ * list_ts can only store pointers to list_item_ts.  Each ListItem_t contains a
+ * numeric value (xItemValue).  Most of the time the lists are sorted in
+ * descending item value order.
+ *
+ * Lists are created already containing one list item.  The value of this
+ * item is the maximum possible that can be stored, it is therefore always at
+ * the end of the list and acts as a marker.  The list member pxHead always
+ * points to this marker - even though it is at the tail of the list.  This
+ * is because the tail contains a wrap back pointer to the true head of
+ * the list.
+ *
+ * In addition to it's value, each list item contains a pointer to the next
+ * item in the list (pxNext), a pointer to the list it is in (pxContainer)
+ * and a pointer to back to the object that contains it.  These later two
+ * pointers are included for efficiency of list manipulation.  There is
+ * effectively a two way link between the object containing the list item and
+ * the list item itself.
+ *
+ *
+ * \page ListIntroduction List Implementation
+ * \ingroup FreeRTOSIntro
+ */
+
+#ifndef INC_FREERTOS_H
+	#error FreeRTOS.h must be included before list.h
+#endif
+
+#ifndef LIST_H
+#define LIST_H
+
+/*
+ * The list structure members are modified from within interrupts, and therefore
+ * by rights should be declared volatile.  However, they are only modified in a
+ * functionally atomic way (within critical sections of with the scheduler
+ * suspended) and are either passed by reference into a function or indexed via
+ * a volatile variable.  Therefore, in all use cases tested so far, the volatile
+ * qualifier can be omitted in order to provide a moderate performance
+ * improvement without adversely affecting functional behaviour.  The assembly
+ * instructions generated by the IAR, ARM and GCC compilers when the respective
+ * compiler's options were set for maximum optimisation has been inspected and
+ * deemed to be as intended.  That said, as compiler technology advances, and
+ * especially if aggressive cross module optimisation is used (a use case that
+ * has not been exercised to any great extend) then it is feasible that the
+ * volatile qualifier will be needed for correct optimisation.  It is expected
+ * that a compiler removing essential code because, without the volatile
+ * qualifier on the list structure members and with aggressive cross module
+ * optimisation, the compiler deemed the code unnecessary will result in
+ * complete and obvious failure of the scheduler.  If this is ever experienced
+ * then the volatile qualifier can be inserted in the relevant places within the
+ * list structures by simply defining configLIST_VOLATILE to volatile in
+ * FreeRTOSConfig.h (as per the example at the bottom of this comment block).
+ * If configLIST_VOLATILE is not defined then the preprocessor directives below
+ * will simply #define configLIST_VOLATILE away completely.
+ *
+ * To use volatile list structure members then add the following line to
+ * FreeRTOSConfig.h (without the quotes):
+ * "#define configLIST_VOLATILE volatile"
+ */
+#ifndef configLIST_VOLATILE
+	#define configLIST_VOLATILE
+#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Macros that can be used to place known values within the list structures,
+then check that the known values do not get corrupted during the execution of
+the application.   These may catch the list data structures being overwritten in
+memory.  They will not catch data errors caused by incorrect configuration or
+use of FreeRTOS.*/
+#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 )
+	/* Define the macros to do nothing. */
+	#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE
+	#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE
+	#define listFIRST_LIST_INTEGRITY_CHECK_VALUE
+	#define listSECOND_LIST_INTEGRITY_CHECK_VALUE
+	#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
+	#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
+	#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )
+	#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )
+	#define listTEST_LIST_ITEM_INTEGRITY( pxItem )
+	#define listTEST_LIST_INTEGRITY( pxList )
+#else
+	/* Define macros that add new members into the list structures. */
+	#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE				TickType_t xListItemIntegrityValue1;
+	#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE				TickType_t xListItemIntegrityValue2;
+	#define listFIRST_LIST_INTEGRITY_CHECK_VALUE					TickType_t xListIntegrityValue1;
+	#define listSECOND_LIST_INTEGRITY_CHECK_VALUE					TickType_t xListIntegrityValue2;
+
+	/* Define macros that set the new structure members to known values. */
+	#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )		( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
+	#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )	( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
+	#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )		( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
+	#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )		( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
+
+	/* Define macros that will assert if one of the structure members does not
+	contain its expected value. */
+	#define listTEST_LIST_ITEM_INTEGRITY( pxItem )		configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
+	#define listTEST_LIST_INTEGRITY( pxList )			configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
+#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */
+
+
+/*
+ * Definition of the only type of object that a list can contain.
+ */
+struct xLIST;
+struct xLIST_ITEM
+{
+	listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE			/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	configLIST_VOLATILE TickType_t xItemValue;			/*< The value being listed.  In most cases this is used to sort the list in descending order. */
+	struct xLIST_ITEM * configLIST_VOLATILE pxNext;		/*< Pointer to the next ListItem_t in the list. */
+	struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;	/*< Pointer to the previous ListItem_t in the list. */
+	void * pvOwner;										/*< Pointer to the object (normally a TCB) that contains the list item.  There is therefore a two way link between the object containing the list item and the list item itself. */
+	struct xLIST * configLIST_VOLATILE pxContainer;		/*< Pointer to the list in which this list item is placed (if any). */
+	listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE			/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+};
+typedef struct xLIST_ITEM ListItem_t;					/* For some reason lint wants this as two separate definitions. */
+
+struct xMINI_LIST_ITEM
+{
+	listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE			/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	configLIST_VOLATILE TickType_t xItemValue;
+	struct xLIST_ITEM * configLIST_VOLATILE pxNext;
+	struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;
+};
+typedef struct xMINI_LIST_ITEM MiniListItem_t;
+
+/*
+ * Definition of the type of queue used by the scheduler.
+ */
+typedef struct xLIST
+{
+	listFIRST_LIST_INTEGRITY_CHECK_VALUE				/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	volatile UBaseType_t uxNumberOfItems;
+	ListItem_t * configLIST_VOLATILE pxIndex;			/*< Used to walk through the list.  Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */
+	MiniListItem_t xListEnd;							/*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */
+	listSECOND_LIST_INTEGRITY_CHECK_VALUE				/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+} List_t;
+
+/*
+ * Access macro to set the owner of a list item.  The owner of a list item
+ * is the object (usually a TCB) that contains the list item.
+ *
+ * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
+ * \ingroup LinkedList
+ */
+#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner )		( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )
+
+/*
+ * Access macro to get the owner of a list item.  The owner of a list item
+ * is the object (usually a TCB) that contains the list item.
+ *
+ * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
+ * \ingroup LinkedList
+ */
+#define listGET_LIST_ITEM_OWNER( pxListItem )	( ( pxListItem )->pvOwner )
+
+/*
+ * Access macro to set the value of the list item.  In most cases the value is
+ * used to sort the list in descending order.
+ *
+ * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listSET_LIST_ITEM_VALUE( pxListItem, xValue )	( ( pxListItem )->xItemValue = ( xValue ) )
+
+/*
+ * Access macro to retrieve the value of the list item.  The value can
+ * represent anything - for example the priority of a task, or the time at
+ * which a task should be unblocked.
+ *
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listGET_LIST_ITEM_VALUE( pxListItem )	( ( pxListItem )->xItemValue )
+
+/*
+ * Access macro to retrieve the value of the list item at the head of a given
+ * list.
+ *
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList )	( ( ( pxList )->xListEnd ).pxNext->xItemValue )
+
+/*
+ * Return the list item at the head of the list.
+ *
+ * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_HEAD_ENTRY( pxList )	( ( ( pxList )->xListEnd ).pxNext )
+
+/*
+ * Return the list item at the head of the list.
+ *
+ * \page listGET_NEXT listGET_NEXT
+ * \ingroup LinkedList
+ */
+#define listGET_NEXT( pxListItem )	( ( pxListItem )->pxNext )
+
+/*
+ * Return the list item that marks the end of the list
+ *
+ * \page listGET_END_MARKER listGET_END_MARKER
+ * \ingroup LinkedList
+ */
+#define listGET_END_MARKER( pxList )	( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )
+
+/*
+ * Access macro to determine if a list contains any items.  The macro will
+ * only have the value true if the list is empty.
+ *
+ * \page listLIST_IS_EMPTY listLIST_IS_EMPTY
+ * \ingroup LinkedList
+ */
+#define listLIST_IS_EMPTY( pxList )	( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE )
+
+/*
+ * Access macro to return the number of items in the list.
+ */
+#define listCURRENT_LIST_LENGTH( pxList )	( ( pxList )->uxNumberOfItems )
+
+/*
+ * Access function to obtain the owner of the next entry in a list.
+ *
+ * The list member pxIndex is used to walk through a list.  Calling
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list
+ * and returns that entry's pxOwner parameter.  Using multiple calls to this
+ * function it is therefore possible to move through every item contained in
+ * a list.
+ *
+ * The pxOwner parameter of a list item is a pointer to the object that owns
+ * the list item.  In the scheduler this is normally a task control block.
+ * The pxOwner parameter effectively creates a two way link between the list
+ * item and its owner.
+ *
+ * @param pxTCB pxTCB is set to the address of the owner of the next list item.
+ * @param pxList The list from which the next item owner is to be returned.
+ *
+ * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList )										\
+{																							\
+List_t * const pxConstList = ( pxList );													\
+	/* Increment the index to the next item and return the item, ensuring */				\
+	/* we don't return the marker used at the end of the list.  */							\
+	( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;							\
+	if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) )	\
+	{																						\
+		( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;						\
+	}																						\
+	( pxTCB ) = ( pxConstList )->pxIndex->pvOwner;											\
+}
+
+
+/*
+ * Access function to obtain the owner of the first entry in a list.  Lists
+ * are normally sorted in ascending item value order.
+ *
+ * This function returns the pxOwner member of the first item in the list.
+ * The pxOwner parameter of a list item is a pointer to the object that owns
+ * the list item.  In the scheduler this is normally a task control block.
+ * The pxOwner parameter effectively creates a two way link between the list
+ * item and its owner.
+ *
+ * @param pxList The list from which the owner of the head item is to be
+ * returned.
+ *
+ * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_OWNER_OF_HEAD_ENTRY( pxList )  ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner )
+
+/*
+ * Check to see if a list item is within a list.  The list item maintains a
+ * "container" pointer that points to the list it is in.  All this macro does
+ * is check to see if the container and the list match.
+ *
+ * @param pxList The list we want to know if the list item is within.
+ * @param pxListItem The list item we want to know if is in the list.
+ * @return pdTRUE if the list item is in the list, otherwise pdFALSE.
+ */
+#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) )
+
+/*
+ * Return the list a list item is contained within (referenced from).
+ *
+ * @param pxListItem The list item being queried.
+ * @return A pointer to the List_t object that references the pxListItem
+ */
+#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer )
+
+/*
+ * This provides a crude means of knowing if a list has been initialised, as
+ * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise()
+ * function.
+ */
+#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )
+
+/*
+ * Must be called before a list is used!  This initialises all the members
+ * of the list structure and inserts the xListEnd item into the list as a
+ * marker to the back of the list.
+ *
+ * @param pxList Pointer to the list being initialised.
+ *
+ * \page vListInitialise vListInitialise
+ * \ingroup LinkedList
+ */
+void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION;
+
+/*
+ * Must be called before a list item is used.  This sets the list container to
+ * null so the item does not think that it is already contained in a list.
+ *
+ * @param pxItem Pointer to the list item being initialised.
+ *
+ * \page vListInitialiseItem vListInitialiseItem
+ * \ingroup LinkedList
+ */
+void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert a list item into a list.  The item will be inserted into the list in
+ * a position determined by its item value (descending item value order).
+ *
+ * @param pxList The list into which the item is to be inserted.
+ *
+ * @param pxNewListItem The item that is to be placed in the list.
+ *
+ * \page vListInsert vListInsert
+ * \ingroup LinkedList
+ */
+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert a list item into a list.  The item will be inserted in a position
+ * such that it will be the last item within the list returned by multiple
+ * calls to listGET_OWNER_OF_NEXT_ENTRY.
+ *
+ * The list member pxIndex is used to walk through a list.  Calling
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list.
+ * Placing an item in a list using vListInsertEnd effectively places the item
+ * in the list position pointed to by pxIndex.  This means that every other
+ * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before
+ * the pxIndex parameter again points to the item being inserted.
+ *
+ * @param pxList The list into which the item is to be inserted.
+ *
+ * @param pxNewListItem The list item to be inserted into the list.
+ *
+ * \page vListInsertEnd vListInsertEnd
+ * \ingroup LinkedList
+ */
+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Remove an item from a list.  The list item has a pointer to the list that
+ * it is in, so only the list item need be passed into the function.
+ *
+ * @param uxListRemove The item to be removed.  The item will remove itself from
+ * the list pointed to by it's pxContainer parameter.
+ *
+ * @return The number of items that remain in the list after the list item has
+ * been removed.
+ *
+ * \page uxListRemove uxListRemove
+ * \ingroup LinkedList
+ */
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/include/message_buffer.h b/FreeRTOSv10.2.1/FreeRTOS/Source/include/message_buffer.h
new file mode 100644
index 0000000..9ee3f4d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/include/message_buffer.h
@@ -0,0 +1,799 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*
+ * Message buffers build functionality on top of FreeRTOS stream buffers.
+ * Whereas stream buffers are used to send a continuous stream of data from one
+ * task or interrupt to another, message buffers are used to send variable
+ * length discrete messages from one task or interrupt to another.  Their
+ * implementation is light weight, making them particularly suited for interrupt
+ * to task and core to core communication scenarios.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * timeout to 0.
+ *
+ * Message buffers hold variable length messages.  To enable that, when a
+ * message is written to the message buffer an additional sizeof( size_t ) bytes
+ * are also written to store the message's length (that happens internally, with
+ * the API function).  sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so writing a 10 byte message to a message buffer on a 32-bit
+ * architecture will actually reduce the available space in the message buffer
+ * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length
+ * of the message).
+ */
+
+#ifndef FREERTOS_MESSAGE_BUFFER_H
+#define FREERTOS_MESSAGE_BUFFER_H
+
+/* Message buffers are built onto of stream buffers. */
+#include "stream_buffer.h"
+
+#if defined( __cplusplus )
+extern "C" {
+#endif
+
+/**
+ * Type by which message buffers are referenced.  For example, a call to
+ * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can
+ * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(),
+ * etc.
+ */
+typedef void * MessageBufferHandle_t;
+
+/*-----------------------------------------------------------*/
+
+/**
+ * message_buffer.h
+ *
+
+MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
+

+ *
+ * Creates a new message buffer using dynamically allocated memory.  See
+ * xMessageBufferCreateStatic() for a version that uses statically allocated
+ * memory (memory that is allocated at compile time).
+ *
+ * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
+ * FreeRTOSConfig.h for xMessageBufferCreate() to be available.
+ *
+ * @param xBufferSizeBytes The total number of bytes (not messages) the message
+ * buffer will be able to hold at any one time.  When a message is written to
+ * the message buffer an additional sizeof( size_t ) bytes are also written to
+ * store the message's length.  sizeof( size_t ) is typically 4 bytes on a
+ * 32-bit architecture, so on most 32-bit architectures a 10 byte message will
+ * take up 14 bytes of message buffer space.
+ *
+ * @return If NULL is returned, then the message buffer cannot be created
+ * because there is insufficient heap memory available for FreeRTOS to allocate
+ * the message buffer data structures and storage area.  A non-NULL value being
+ * returned indicates that the message buffer has been created successfully -
+ * the returned value should be stored as the handle to the created message
+ * buffer.
+ *
+ * Example use:
+
+
+void vAFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+const size_t xMessageBufferSizeBytes = 100;
+
+    // Create a message buffer that can hold 100 bytes.  The memory used to hold
+    // both the message buffer structure and the messages themselves is allocated
+    // dynamically.  Each message added to the buffer consumes an additional 4
+    // bytes which are used to hold the lengh of the message.
+    xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
+
+    if( xMessageBuffer == NULL )
+    {
+        // There was not enough heap memory space available to create the
+        // message buffer.
+    }
+    else
+    {
+        // The message buffer was created successfully and can now be used.
+    }
+
+

+ * \defgroup xMessageBufferCreate xMessageBufferCreate
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferCreate( xBufferSizeBytes ) ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE )
+
+/**
+ * message_buffer.h
+ *
+
+MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
+                                                  uint8_t *pucMessageBufferStorageArea,
+                                                  StaticMessageBuffer_t *pxStaticMessageBuffer );
+

+ * Creates a new message buffer using statically allocated memory.  See
+ * xMessageBufferCreate() for a version that uses dynamically allocated memory.
+ *
+ * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
+ * pucMessageBufferStorageArea parameter.  When a message is written to the
+ * message buffer an additional sizeof( size_t ) bytes are also written to store
+ * the message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so on most 32-bit architecture a 10 byte message will take up
+ * 14 bytes of message buffer space.  The maximum number of bytes that can be
+ * stored in the message buffer is actually (xBufferSizeBytes - 1).
+ *
+ * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at
+ * least xBufferSizeBytes + 1 big.  This is the array to which messages are
+ * copied when they are written to the message buffer.
+ *
+ * @param pxStaticMessageBuffer Must point to a variable of type
+ * StaticMessageBuffer_t, which will be used to hold the message buffer's data
+ * structure.
+ *
+ * @return If the message buffer is created successfully then a handle to the
+ * created message buffer is returned. If either pucMessageBufferStorageArea or
+ * pxStaticmessageBuffer are NULL then NULL is returned.
+ *
+ * Example use:
+
+
+// Used to dimension the array used to hold the messages.  The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the messages within the message
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the message buffer structure.
+StaticMessageBuffer_t xMessageBufferStruct;
+
+void MyFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+
+    xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ),
+                                                 ucBufferStorage,
+                                                 &xMessageBufferStruct );
+
+    // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
+    // parameters were NULL, xMessageBuffer will not be NULL, and can be used to
+    // reference the created message buffer in other message buffer API calls.
+
+    // Other code that uses the message buffer can go here.
+}
+
+

+ * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer )
+
+/**
+ * message_buffer.h
+ *
+
+size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
+                           const void *pvTxData,
+                           size_t xDataLengthBytes,
+                           TickType_t xTicksToWait );
+
+ *
+ * Sends a discrete message to the message buffer.  The message can be any
+ * length that fits within the buffer's free space, and is copied into the
+ * buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param xTicksToWait The maximum amount of time the calling task should remain
+ * in the Blocked state to wait for enough space to become available in the
+ * message buffer, should the message buffer have insufficient space when
+ * xMessageBufferSend() is called.  The calling task will never block if
+ * xTicksToWait is zero.  The block time is specified in tick periods, so the
+ * absolute time it represents is dependent on the tick frequency.  The macro
+ * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into
+ * a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will cause
+ * the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The number of bytes written to the message buffer.  If the call to
+ * xMessageBufferSend() times out before there was enough space to write the
+ * message into the message buffer then zero is returned.  If the call did not
+ * time out then xDataLengthBytes is returned.
+ *
+ * Example use:
+
+void vAFunction( MessageBufferHandle_t xMessageBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+    // Send an array to the message buffer, blocking for a maximum of 100ms to
+    // wait for enough space to be available in the message buffer.
+    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+    if( xBytesSent != sizeof( ucArrayToSend ) )
+    {
+        // The call to xMessageBufferSend() times out before there was enough
+        // space in the buffer for the data to be written.
+    }
+
+    // Send the string to the message buffer.  Return immediately if there is
+    // not enough space in the buffer.
+    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The string could not be added to the message buffer because there was
+        // not enough free space in the buffer.
+    }
+}
+

+ * \defgroup xMessageBufferSend xMessageBufferSend
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
+
+/**
+ * message_buffer.h
+ *
+
+size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
+                                  const void *pvTxData,
+                                  size_t xDataLengthBytes,
+                                  BaseType_t *pxHigherPriorityTaskWoken );
+
+ *
+ * Interrupt safe version of the API function that sends a discrete message to
+ * the message buffer.  The message can be any length that fits within the
+ * buffer's free space, and is copied into the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xMessageBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xMessageBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes actually written to the message buffer.  If the
+ * message buffer didn't have enough free space for the message to be stored
+ * then 0 is returned, otherwise xDataLengthBytes is returned.
+ *
+ * Example use:
+
+// A message buffer that has already been created.
+MessageBufferHandle_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+    // Attempt to send the string to the message buffer.
+    xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
+                                            ( void * ) pcStringToSend,
+                                            strlen( pcStringToSend ),
+                                            &xHigherPriorityTaskWoken );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The string could not be added to the message buffer because there was
+        // not enough free space in the buffer.
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xMessageBufferSendFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
+size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
+                              void *pvRxData,
+                              size_t xBufferLengthBytes,
+                              TickType_t xTicksToWait );
+

+ *
+ * Receives a discrete message from a message buffer.  Messages can be of
+ * variable length and are copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for a message, should the message buffer be empty.
+ * xMessageBufferReceive() will return immediately if xTicksToWait is zero and
+ * the message buffer is empty.  The block time is specified in tick periods, so
+ * the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.  If xMessageBufferReceive() times out before a message became available
+ * then zero is returned.  If the length of the message is greater than
+ * xBufferLengthBytes then the message will be left in the message buffer and
+ * zero is returned.
+ *
+ * Example use:
+
+void vAFunction( MessageBuffer_t xMessageBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+    // Receive the next message from the message buffer.  Wait in the Blocked
+    // state (so not using any CPU processing time) for a maximum of 100ms for
+    // a message to become available.
+    xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
+                                            ( void * ) ucRxData,
+                                            sizeof( ucRxData ),
+                                            xBlockTime );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains a message that is xReceivedBytes long.  Process
+        // the message here....
+    }
+}
+

+ * \defgroup xMessageBufferReceive xMessageBufferReceive
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
+
+
+/**
+ * message_buffer.h
+ *
+
+size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
+                                     void *pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * An interrupt safe version of the API function that receives a discrete
+ * message from a message buffer.  Messages can be of variable length and are
+ * copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xMessageBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.
+ *
+ * Example use:
+
+// A message buffer that has already been created.
+MessageBuffer_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+
+    // Receive the next message from the message buffer.
+    xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
+                                                  ( void * ) ucRxData,
+                                                  sizeof( ucRxData ),
+                                                  &xHigherPriorityTaskWoken );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains a message that is xReceivedBytes long.  Process
+        // the message here....
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xMessageBufferReceiveFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
+void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
+

+ *
+ * Deletes a message buffer that was previously created using a call to
+ * xMessageBufferCreate() or xMessageBufferCreateStatic().  If the message
+ * buffer was created using dynamic memory (that is, by xMessageBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A message buffer handle must not be used after the message buffer has been
+ * deleted.
+ *
+ * @param xMessageBuffer The handle of the message buffer to be deleted.
+ *
+ */
+#define vMessageBufferDelete( xMessageBuffer ) vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
+BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ) );
+

+ *
+ * Tests to see if a message buffer is full.  A message buffer is full if it
+ * cannot accept any more messages, of any size, until space is made available
+ * by a message being removed from the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is full then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ */
+#define xMessageBufferIsFull( xMessageBuffer ) xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
+BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ) );
+

+ *
+ * Tests to see if a message buffer is empty (does not contain any messages).
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is empty then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ *
+ */
+#define xMessageBufferIsEmpty( xMessageBuffer ) xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
+BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
+

+ *
+ * Resets a message buffer to its initial empty state, discarding any message it
+ * contained.
+ *
+ * A message buffer can only be reset if there are no tasks blocked on it.
+ *
+ * @param xMessageBuffer The handle of the message buffer being reset.
+ *
+ * @return If the message buffer was reset then pdPASS is returned.  If the
+ * message buffer could not be reset because either there was a task blocked on
+ * the message queue to wait for space to become available, or to wait for a
+ * a message to be available, then pdFAIL is returned.
+ *
+ * \defgroup xMessageBufferReset xMessageBufferReset
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReset( xMessageBuffer ) xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer )
+
+
+/**
+ * message_buffer.h
+
+size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );
+

+ * Returns the number of bytes of free space in the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The number of bytes that can be written to the message buffer before
+ * the message buffer would be full.  When a message is written to the message
+ * buffer an additional sizeof( size_t ) bytes are also written to store the
+ * message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size
+ * of the largest message that can be written to the message buffer is 6 bytes.
+ *
+ * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSpaceAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer )
+#define xMessageBufferSpacesAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */
+
+/**
+ * message_buffer.h
+ 
+ size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ) );
+ 

+ * Returns the length (in bytes) of the next message in a message buffer.
+ * Useful if xMessageBufferReceive() returned 0 because the size of the buffer
+ * passed into xMessageBufferReceive() was too small to hold the next message.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The length (in bytes) of the next message in the message buffer, or 0
+ * if the message buffer is empty.
+ *
+ * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferNextLengthBytes( xMessageBuffer ) xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * message_buffer.h
+ *
+
+BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xMessageBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferSendCompletedFromISR().  If calling
+ * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
+BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xMessageBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferReceiveCompletedFromISR().  If calling
+ * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+#if defined( __cplusplus )
+} /* extern "C" */
+#endif
+
+#endif	/* !defined( FREERTOS_MESSAGE_BUFFER_H ) */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/include/mpu_prototypes.h b/FreeRTOSv10.2.1/FreeRTOS/Source/include/mpu_prototypes.h
new file mode 100644
index 0000000..f0b3337
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/include/mpu_prototypes.h
@@ -0,0 +1,157 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * When the MPU is used the standard (non MPU) API functions are mapped to
+ * equivalents that start "MPU_", the prototypes for which are defined in this
+ * header files.  This will cause the application code to call the MPU_ version
+ * which wraps the non-MPU version with privilege promoting then demoting code,
+ * so the kernel code always runs will full privileges.
+ */
+
+
+#ifndef MPU_PROTOTYPES_H
+#define MPU_PROTOTYPES_H
+
+/* MPU versions of tasks.h API functions. */
+BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
+TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of queue.h API functions. */
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of timers.h API functions. */
+TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL;
+TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of event_group.h API functions. */
+EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;
+EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of message/stream_buffer.h API functions. */
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL;
+
+
+
+#endif /* MPU_PROTOTYPES_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/include/mpu_wrappers.h b/FreeRTOSv10.2.1/FreeRTOS/Source/include/mpu_wrappers.h
new file mode 100644
index 0000000..56d9c7e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/include/mpu_wrappers.h
@@ -0,0 +1,186 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef MPU_WRAPPERS_H
+#define MPU_WRAPPERS_H
+
+/* This file redefines API functions to be called through a wrapper macro, but
+only for ports that are using the MPU. */
+#ifdef portUSING_MPU_WRAPPERS
+
+	/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
+	included from queue.c or task.c to prevent it from having an effect within
+	those files. */
+	#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+		/*
+		 * Map standard (non MPU) API functions to equivalents that start
+		 * "MPU_".  This will cause the application code to call the MPU_
+		 * version, which wraps the non-MPU version with privilege promoting
+		 * then demoting code, so the kernel code always runs will full
+		 * privileges.
+		 */
+
+		/* Map standard tasks.h API functions to the MPU equivalents. */
+		#define xTaskCreate								MPU_xTaskCreate
+		#define xTaskCreateStatic						MPU_xTaskCreateStatic
+		#define xTaskCreateRestricted					MPU_xTaskCreateRestricted
+		#define vTaskAllocateMPURegions					MPU_vTaskAllocateMPURegions
+		#define vTaskDelete								MPU_vTaskDelete
+		#define vTaskDelay								MPU_vTaskDelay
+		#define vTaskDelayUntil							MPU_vTaskDelayUntil
+		#define xTaskAbortDelay							MPU_xTaskAbortDelay
+		#define uxTaskPriorityGet						MPU_uxTaskPriorityGet
+		#define eTaskGetState							MPU_eTaskGetState
+		#define vTaskGetInfo							MPU_vTaskGetInfo
+		#define vTaskPrioritySet						MPU_vTaskPrioritySet
+		#define vTaskSuspend							MPU_vTaskSuspend
+		#define vTaskResume								MPU_vTaskResume
+		#define vTaskSuspendAll							MPU_vTaskSuspendAll
+		#define xTaskResumeAll							MPU_xTaskResumeAll
+		#define xTaskGetTickCount						MPU_xTaskGetTickCount
+		#define uxTaskGetNumberOfTasks					MPU_uxTaskGetNumberOfTasks
+		#define pcTaskGetName							MPU_pcTaskGetName
+		#define xTaskGetHandle							MPU_xTaskGetHandle
+		#define uxTaskGetStackHighWaterMark				MPU_uxTaskGetStackHighWaterMark
+		#define uxTaskGetStackHighWaterMark2			MPU_uxTaskGetStackHighWaterMark2
+		#define vTaskSetApplicationTaskTag				MPU_vTaskSetApplicationTaskTag
+		#define xTaskGetApplicationTaskTag				MPU_xTaskGetApplicationTaskTag
+		#define vTaskSetThreadLocalStoragePointer		MPU_vTaskSetThreadLocalStoragePointer
+		#define pvTaskGetThreadLocalStoragePointer		MPU_pvTaskGetThreadLocalStoragePointer
+		#define xTaskCallApplicationTaskHook			MPU_xTaskCallApplicationTaskHook
+		#define xTaskGetIdleTaskHandle					MPU_xTaskGetIdleTaskHandle
+		#define uxTaskGetSystemState					MPU_uxTaskGetSystemState
+		#define vTaskList								MPU_vTaskList
+		#define vTaskGetRunTimeStats					MPU_vTaskGetRunTimeStats
+		#define xTaskGetIdleRunTimeCounter				MPU_xTaskGetIdleRunTimeCounter
+		#define xTaskGenericNotify						MPU_xTaskGenericNotify
+		#define xTaskNotifyWait							MPU_xTaskNotifyWait
+		#define ulTaskNotifyTake						MPU_ulTaskNotifyTake
+		#define xTaskNotifyStateClear					MPU_xTaskNotifyStateClear
+
+		#define xTaskGetCurrentTaskHandle				MPU_xTaskGetCurrentTaskHandle
+		#define vTaskSetTimeOutState					MPU_vTaskSetTimeOutState
+		#define xTaskCheckForTimeOut					MPU_xTaskCheckForTimeOut
+		#define xTaskGetSchedulerState					MPU_xTaskGetSchedulerState
+
+		/* Map standard queue.h API functions to the MPU equivalents. */
+		#define xQueueGenericSend						MPU_xQueueGenericSend
+		#define xQueueReceive							MPU_xQueueReceive
+		#define xQueuePeek								MPU_xQueuePeek
+		#define xQueueSemaphoreTake						MPU_xQueueSemaphoreTake
+		#define uxQueueMessagesWaiting					MPU_uxQueueMessagesWaiting
+		#define uxQueueSpacesAvailable					MPU_uxQueueSpacesAvailable
+		#define vQueueDelete							MPU_vQueueDelete
+		#define xQueueCreateMutex						MPU_xQueueCreateMutex
+		#define xQueueCreateMutexStatic					MPU_xQueueCreateMutexStatic
+		#define xQueueCreateCountingSemaphore			MPU_xQueueCreateCountingSemaphore
+		#define xQueueCreateCountingSemaphoreStatic		MPU_xQueueCreateCountingSemaphoreStatic
+		#define xQueueGetMutexHolder					MPU_xQueueGetMutexHolder
+		#define xQueueTakeMutexRecursive				MPU_xQueueTakeMutexRecursive
+		#define xQueueGiveMutexRecursive				MPU_xQueueGiveMutexRecursive
+		#define xQueueGenericCreate						MPU_xQueueGenericCreate
+		#define xQueueGenericCreateStatic				MPU_xQueueGenericCreateStatic
+		#define xQueueCreateSet							MPU_xQueueCreateSet
+		#define xQueueAddToSet							MPU_xQueueAddToSet
+		#define xQueueRemoveFromSet						MPU_xQueueRemoveFromSet
+		#define xQueueSelectFromSet						MPU_xQueueSelectFromSet
+		#define xQueueGenericReset						MPU_xQueueGenericReset
+
+		#if( configQUEUE_REGISTRY_SIZE > 0 )
+			#define vQueueAddToRegistry						MPU_vQueueAddToRegistry
+			#define vQueueUnregisterQueue					MPU_vQueueUnregisterQueue
+			#define pcQueueGetName							MPU_pcQueueGetName
+		#endif
+
+		/* Map standard timer.h API functions to the MPU equivalents. */
+		#define xTimerCreate							MPU_xTimerCreate
+		#define xTimerCreateStatic						MPU_xTimerCreateStatic
+		#define pvTimerGetTimerID						MPU_pvTimerGetTimerID
+		#define vTimerSetTimerID						MPU_vTimerSetTimerID
+		#define xTimerIsTimerActive						MPU_xTimerIsTimerActive
+		#define xTimerGetTimerDaemonTaskHandle			MPU_xTimerGetTimerDaemonTaskHandle
+		#define xTimerPendFunctionCall					MPU_xTimerPendFunctionCall
+		#define pcTimerGetName							MPU_pcTimerGetName
+		#define vTimerSetReloadMode						MPU_vTimerSetReloadMode
+		#define xTimerGetPeriod							MPU_xTimerGetPeriod
+		#define xTimerGetExpiryTime						MPU_xTimerGetExpiryTime
+		#define xTimerGenericCommand					MPU_xTimerGenericCommand
+
+		/* Map standard event_group.h API functions to the MPU equivalents. */
+		#define xEventGroupCreate						MPU_xEventGroupCreate
+		#define xEventGroupCreateStatic					MPU_xEventGroupCreateStatic
+		#define xEventGroupWaitBits						MPU_xEventGroupWaitBits
+		#define xEventGroupClearBits					MPU_xEventGroupClearBits
+		#define xEventGroupSetBits						MPU_xEventGroupSetBits
+		#define xEventGroupSync							MPU_xEventGroupSync
+		#define vEventGroupDelete						MPU_vEventGroupDelete
+
+		/* Map standard message/stream_buffer.h API functions to the MPU
+		equivalents. */
+		#define xStreamBufferSend						MPU_xStreamBufferSend
+		#define xStreamBufferReceive					MPU_xStreamBufferReceive
+		#define xStreamBufferNextMessageLengthBytes		MPU_xStreamBufferNextMessageLengthBytes
+		#define vStreamBufferDelete						MPU_vStreamBufferDelete
+		#define xStreamBufferIsFull						MPU_xStreamBufferIsFull
+		#define xStreamBufferIsEmpty					MPU_xStreamBufferIsEmpty
+		#define xStreamBufferReset						MPU_xStreamBufferReset
+		#define xStreamBufferSpacesAvailable			MPU_xStreamBufferSpacesAvailable
+		#define xStreamBufferBytesAvailable				MPU_xStreamBufferBytesAvailable
+		#define xStreamBufferSetTriggerLevel			MPU_xStreamBufferSetTriggerLevel
+		#define xStreamBufferGenericCreate				MPU_xStreamBufferGenericCreate
+		#define xStreamBufferGenericCreateStatic		MPU_xStreamBufferGenericCreateStatic
+
+
+		/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
+		macro so applications can place data in privileged access sections
+		(useful when using statically allocated objects). */
+		#define PRIVILEGED_FUNCTION
+		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+		#define FREERTOS_SYSTEM_CALL
+
+	#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+		/* Ensure API functions go in the privileged execution section. */
+		#define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))
+		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+		#define FREERTOS_SYSTEM_CALL __attribute__((section( "freertos_system_calls")))
+
+	#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+#else /* portUSING_MPU_WRAPPERS */
+
+	#define PRIVILEGED_FUNCTION
+	#define PRIVILEGED_DATA
+	#define FREERTOS_SYSTEM_CALL
+	#define portUSING_MPU_WRAPPERS 0
+
+#endif /* portUSING_MPU_WRAPPERS */
+
+
+#endif /* MPU_WRAPPERS_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/include/portable.h b/FreeRTOSv10.2.1/FreeRTOS/Source/include/portable.h
new file mode 100644
index 0000000..a1bb449
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/include/portable.h
@@ -0,0 +1,181 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Portable layer API.  Each function must be defined for each port.
+ *----------------------------------------------------------*/
+
+#ifndef PORTABLE_H
+#define PORTABLE_H
+
+/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
+pre-processor definition was used to ensure the pre-processor found the correct
+portmacro.h file for the port being used.  That scheme was deprecated in favour
+of setting the compiler's include path such that it found the correct
+portmacro.h file - removing the need for the constant and allowing the
+portmacro.h file to be located anywhere in relation to the port being used.
+Purely for reasons of backward compatibility the old method is still valid, but
+to make it clear that new projects should not use it, support for the port
+specific constants has been moved into the deprecated_definitions.h header
+file. */
+#include "deprecated_definitions.h"
+
+/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h
+did not result in a portmacro.h header file being included - and it should be
+included here.  In this case the path to the correct portmacro.h header file
+must be set in the compiler's include path. */
+#ifndef portENTER_CRITICAL
+	#include "portmacro.h"
+#endif
+
+#if portBYTE_ALIGNMENT == 32
+	#define portBYTE_ALIGNMENT_MASK ( 0x001f )
+#endif
+
+#if portBYTE_ALIGNMENT == 16
+	#define portBYTE_ALIGNMENT_MASK ( 0x000f )
+#endif
+
+#if portBYTE_ALIGNMENT == 8
+	#define portBYTE_ALIGNMENT_MASK ( 0x0007 )
+#endif
+
+#if portBYTE_ALIGNMENT == 4
+	#define portBYTE_ALIGNMENT_MASK	( 0x0003 )
+#endif
+
+#if portBYTE_ALIGNMENT == 2
+	#define portBYTE_ALIGNMENT_MASK	( 0x0001 )
+#endif
+
+#if portBYTE_ALIGNMENT == 1
+	#define portBYTE_ALIGNMENT_MASK	( 0x0000 )
+#endif
+
+#ifndef portBYTE_ALIGNMENT_MASK
+	#error "Invalid portBYTE_ALIGNMENT definition"
+#endif
+
+#ifndef portNUM_CONFIGURABLE_REGIONS
+	#define portNUM_CONFIGURABLE_REGIONS 1
+#endif
+
+#ifndef portHAS_STACK_OVERFLOW_CHECKING
+	#define portHAS_STACK_OVERFLOW_CHECKING 0
+#endif
+
+#ifndef portARCH_NAME
+	#define portARCH_NAME NULL
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mpu_wrappers.h"
+
+/*
+ * Setup the stack of a new task so it is ready to be placed under the
+ * scheduler control.  The registers have to be placed on the stack in
+ * the order that the port expects to find them.
+ *
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+	#else
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+	#endif
+#else
+	#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+	#else
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+	#endif
+#endif
+
+/* Used by heap_5.c. */
+typedef struct HeapRegion
+{
+	uint8_t *pucStartAddress;
+	size_t xSizeInBytes;
+} HeapRegion_t;
+
+/*
+ * Used to define multiple heap regions for use by heap_5.c.  This function
+ * must be called before any calls to pvPortMalloc() - not creating a task,
+ * queue, semaphore, mutex, software timer, event group, etc. will result in
+ * pvPortMalloc being called.
+ *
+ * pxHeapRegions passes in an array of HeapRegion_t structures - each of which
+ * defines a region of memory that can be used as the heap.  The array is
+ * terminated by a HeapRegions_t structure that has a size of 0.  The region
+ * with the lowest start address must appear first in the array.
+ */
+void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
+
+
+/*
+ * Map to the memory management routines required for the port.
+ */
+void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
+void vPortFree( void *pv ) PRIVILEGED_FUNCTION;
+void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the hardware ready for the scheduler to take control.  This generally
+ * sets up a tick interrupt and sets timers for the correct tick frequency.
+ */
+BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
+ * the hardware is left in its original condition after the scheduler stops
+ * executing.
+ */
+void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The structures and methods of manipulating the MPU are contained within the
+ * port layer.
+ *
+ * Fills the xMPUSettings structure with the memory region information
+ * contained in xRegions.
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	struct xMEMORY_REGION;
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTABLE_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/include/projdefs.h b/FreeRTOSv10.2.1/FreeRTOS/Source/include/projdefs.h
new file mode 100644
index 0000000..dbcf9bb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/include/projdefs.h
@@ -0,0 +1,124 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PROJDEFS_H
+#define PROJDEFS_H
+
+/*
+ * Defines the prototype to which task functions must conform.  Defined in this
+ * file to ensure the type is known before portable.h is included.
+ */
+typedef void (*TaskFunction_t)( void * );
+
+/* Converts a time in milliseconds to a time in ticks.  This macro can be
+overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
+definition here is not suitable for your application. */
+#ifndef pdMS_TO_TICKS
+	#define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000 ) )
+#endif
+
+#define pdFALSE			( ( BaseType_t ) 0 )
+#define pdTRUE			( ( BaseType_t ) 1 )
+
+#define pdPASS			( pdTRUE )
+#define pdFAIL			( pdFALSE )
+#define errQUEUE_EMPTY	( ( BaseType_t ) 0 )
+#define errQUEUE_FULL	( ( BaseType_t ) 0 )
+
+/* FreeRTOS error definitions. */
+#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY	( -1 )
+#define errQUEUE_BLOCKED						( -4 )
+#define errQUEUE_YIELD							( -5 )
+
+/* Macros used for basic data corruption checks. */
+#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
+	#define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0
+#endif
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a
+#else
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL
+#endif
+
+/* The following errno values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_ERRNO_NONE			0	/* No errors */
+#define	pdFREERTOS_ERRNO_ENOENT			2	/* No such file or directory */
+#define	pdFREERTOS_ERRNO_EINTR			4	/* Interrupted system call */
+#define	pdFREERTOS_ERRNO_EIO			5	/* I/O error */
+#define	pdFREERTOS_ERRNO_ENXIO			6	/* No such device or address */
+#define	pdFREERTOS_ERRNO_EBADF			9	/* Bad file number */
+#define	pdFREERTOS_ERRNO_EAGAIN			11	/* No more processes */
+#define	pdFREERTOS_ERRNO_EWOULDBLOCK	11	/* Operation would block */
+#define	pdFREERTOS_ERRNO_ENOMEM			12	/* Not enough memory */
+#define	pdFREERTOS_ERRNO_EACCES			13	/* Permission denied */
+#define	pdFREERTOS_ERRNO_EFAULT			14	/* Bad address */
+#define	pdFREERTOS_ERRNO_EBUSY			16	/* Mount device busy */
+#define	pdFREERTOS_ERRNO_EEXIST			17	/* File exists */
+#define	pdFREERTOS_ERRNO_EXDEV			18	/* Cross-device link */
+#define	pdFREERTOS_ERRNO_ENODEV			19	/* No such device */
+#define	pdFREERTOS_ERRNO_ENOTDIR		20	/* Not a directory */
+#define	pdFREERTOS_ERRNO_EISDIR			21	/* Is a directory */
+#define	pdFREERTOS_ERRNO_EINVAL			22	/* Invalid argument */
+#define	pdFREERTOS_ERRNO_ENOSPC			28	/* No space left on device */
+#define	pdFREERTOS_ERRNO_ESPIPE			29	/* Illegal seek */
+#define	pdFREERTOS_ERRNO_EROFS			30	/* Read only file system */
+#define	pdFREERTOS_ERRNO_EUNATCH		42	/* Protocol driver not attached */
+#define	pdFREERTOS_ERRNO_EBADE			50	/* Invalid exchange */
+#define	pdFREERTOS_ERRNO_EFTYPE			79	/* Inappropriate file type or format */
+#define	pdFREERTOS_ERRNO_ENMFILE		89	/* No more files */
+#define	pdFREERTOS_ERRNO_ENOTEMPTY		90	/* Directory not empty */
+#define	pdFREERTOS_ERRNO_ENAMETOOLONG 	91	/* File or path name too long */
+#define	pdFREERTOS_ERRNO_EOPNOTSUPP		95	/* Operation not supported on transport endpoint */
+#define	pdFREERTOS_ERRNO_ENOBUFS		105	/* No buffer space available */
+#define	pdFREERTOS_ERRNO_ENOPROTOOPT	109	/* Protocol not available */
+#define	pdFREERTOS_ERRNO_EADDRINUSE		112	/* Address already in use */
+#define	pdFREERTOS_ERRNO_ETIMEDOUT		116	/* Connection timed out */
+#define	pdFREERTOS_ERRNO_EINPROGRESS	119	/* Connection already in progress */
+#define	pdFREERTOS_ERRNO_EALREADY		120	/* Socket already connected */
+#define	pdFREERTOS_ERRNO_EADDRNOTAVAIL 	125	/* Address not available */
+#define	pdFREERTOS_ERRNO_EISCONN		127	/* Socket is already connected */
+#define	pdFREERTOS_ERRNO_ENOTCONN		128	/* Socket is not connected */
+#define	pdFREERTOS_ERRNO_ENOMEDIUM		135	/* No medium inserted */
+#define	pdFREERTOS_ERRNO_EILSEQ			138	/* An invalid UTF-16 sequence was encountered. */
+#define	pdFREERTOS_ERRNO_ECANCELED		140	/* Operation canceled. */
+
+/* The following endian values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_LITTLE_ENDIAN		0
+#define pdFREERTOS_BIG_ENDIAN			1
+
+/* Re-defining endian values for generic naming. */
+#define pdLITTLE_ENDIAN					pdFREERTOS_LITTLE_ENDIAN
+#define pdBIG_ENDIAN					pdFREERTOS_BIG_ENDIAN
+
+
+#endif /* PROJDEFS_H */
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/include/queue.h b/FreeRTOSv10.2.1/FreeRTOS/Source/include/queue.h
new file mode 100644
index 0000000..5072c45
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/include/queue.h
@@ -0,0 +1,1655 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef QUEUE_H
+#define QUEUE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include queue.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "task.h"
+
+/**
+ * Type by which queues are referenced.  For example, a call to xQueueCreate()
+ * returns an QueueHandle_t variable that can then be used as a parameter to
+ * xQueueSend(), xQueueReceive(), etc.
+ */
+struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */
+typedef struct QueueDefinition * QueueHandle_t;
+
+/**
+ * Type by which queue sets are referenced.  For example, a call to
+ * xQueueCreateSet() returns an xQueueSet variable that can then be used as a
+ * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.
+ */
+typedef struct QueueDefinition * QueueSetHandle_t;
+
+/**
+ * Queue sets can contain both queues and semaphores, so the
+ * QueueSetMemberHandle_t is defined as a type to be used where a parameter or
+ * return value can be either an QueueHandle_t or an SemaphoreHandle_t.
+ */
+typedef struct QueueDefinition * QueueSetMemberHandle_t;
+
+/* For internal use only. */
+#define	queueSEND_TO_BACK		( ( BaseType_t ) 0 )
+#define	queueSEND_TO_FRONT		( ( BaseType_t ) 1 )
+#define queueOVERWRITE			( ( BaseType_t ) 2 )
+
+/* For internal use only.  These definitions *must* match those in queue.c. */
+#define queueQUEUE_TYPE_BASE				( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_SET					( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_MUTEX 				( ( uint8_t ) 1U )
+#define queueQUEUE_TYPE_COUNTING_SEMAPHORE	( ( uint8_t ) 2U )
+#define queueQUEUE_TYPE_BINARY_SEMAPHORE	( ( uint8_t ) 3U )
+#define queueQUEUE_TYPE_RECURSIVE_MUTEX		( ( uint8_t ) 4U )
+
+/**
+ * queue. h
+ * 
+ QueueHandle_t xQueueCreate(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize
+						  );
+ * 

+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @return If the queue is successfully create then a handle to the newly
+ * created queue is returned.  If the queue cannot be created then 0 is
+ * returned.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+	if( xQueue1 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue2 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueCreate xQueueCreate
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) )
+#endif
+
+/**
+ * queue. h
+ * 
+ QueueHandle_t xQueueCreateStatic(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize,
+							  uint8_t *pucQueueStorageBuffer,
+							  StaticQueue_t *pxQueueBuffer
+						  );
+ * 

+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @param pucQueueStorageBuffer If uxItemSize is not zero then
+ * pucQueueStorageBuffer must point to a uint8_t array that is at least large
+ * enough to hold the maximum number of items that can be in the queue at any
+ * one time - which is ( uxQueueLength * uxItemsSize ) bytes.  If uxItemSize is
+ * zero then pucQueueStorageBuffer can be NULL.
+ *
+ * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which
+ * will be used to hold the queue's data structure.
+ *
+ * @return If the queue is created then a handle to the created queue is
+ * returned.  If pxQueueBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ #define QUEUE_LENGTH 10
+ #define ITEM_SIZE sizeof( uint32_t )
+
+ // xQueueBuffer will hold the queue structure.
+ StaticQueue_t xQueueBuffer;
+
+ // ucQueueStorage will hold the items posted to the queue.  Must be at least
+ // [(queue length) * ( queue item size)] bytes long.
+ uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.
+							ITEM_SIZE	  // The size of each item in the queue
+							&( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.
+							&xQueueBuffer ); // The buffer that will hold the queue structure.
+
+	// The queue is guaranteed to be created successfully as no dynamic memory
+	// allocation is used.  Therefore xQueue1 is now a handle to a valid queue.
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueCreateStatic xQueueCreateStatic
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer ) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToToFront(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ * 

+ *
+ * Post an item to the front of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToBack(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ * 

+ *
+ * This is a macro that calls xQueueGenericSend().
+ *
+ * Post an item to the back of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the queue
+ * is full.  The  time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSend(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  TickType_t xTicksToWait
+						 );
+ * 

+ *
+ * This is a macro that calls xQueueGenericSend().  It is included for
+ * backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToFront() and xQueueSendToBack() macros.  It is
+ * equivalent to xQueueSendToBack().
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueOverwrite(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue
+						 );
+ * 

+ *
+ * Only for use with queues that have a length of one - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * This function must not be called from an interrupt service routine.
+ * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle of the queue to which the data is being sent.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and
+ * therefore has the same return values as xQueueSendToFront().  However, pdPASS
+ * is the only value that can be returned because xQueueOverwrite() will write
+ * to the queue even when the queue is already full.
+ *
+ * Example usage:
+   
+
+ void vFunction( void *pvParameters )
+ {
+ QueueHandle_t xQueue;
+ uint32_t ulVarToSend, ulValReceived;
+
+	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwrite() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+
+	// Write the value 10 to the queue using xQueueOverwrite().
+	ulVarToSend = 10;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// Peeking the queue should now return 10, but leave the value 10 in
+	// the queue.  A block time of zero is used as it is known that the
+	// queue holds a value.
+	ulValReceived = 0;
+	xQueuePeek( xQueue, &ulValReceived, 0 );
+
+	if( ulValReceived != 10 )
+	{
+		// Error unless the item was removed by a different task.
+	}
+
+	// The queue is still full.  Use xQueueOverwrite() to overwrite the
+	// value held in the queue with 100.
+	ulVarToSend = 100;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// This time read from the queue, leaving the queue empty once more.
+	// A block time of 0 is used again.
+	xQueueReceive( xQueue, &ulValReceived, 0 );
+
+	// The value read should be the last value written, even though the
+	// queue was already full when the value was written.
+	if( ulValReceived != 100 )
+	{
+		// Error!
+	}
+
+	// ...
+}
+ 

+ * \defgroup xQueueOverwrite xQueueOverwrite
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwrite( xQueue, pvItemToQueue ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )
+
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueGenericSend(
+									QueueHandle_t xQueue,
+									const void * pvItemToQueue,
+									TickType_t xTicksToWait
+									BaseType_t xCopyPosition
+								);
+ * 

+ *
+ * It is preferred that the macros xQueueSend(), xQueueSendToFront() and
+ * xQueueSendToBack() are used in place of calling this function directly.
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueuePeek(
+							 QueueHandle_t xQueue,
+							 void * const pvBuffer,
+							 TickType_t xTicksToWait
+						 );

+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * This macro must not be used in an interrupt service routine.  See
+ * xQueuePeekFromISR() for an alternative that can be called from an interrupt
+ * service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.	 The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue
+ * is empty.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to peek the data from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Peek a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask, but the item still remains on the queue.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueuePeek xQueuePeek
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueuePeekFromISR(
+									QueueHandle_t xQueue,
+									void *pvBuffer,
+								);

+ *
+ * A version of xQueuePeek() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * \defgroup xQueuePeekFromISR xQueuePeekFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueReceive(
+								 QueueHandle_t xQueue,
+								 void *pvBuffer,
+								 TickType_t xTicksToWait
+							);

+ *
+ * Receive an item from a queue.  The item is received by copy so a buffer of
+ * adequate size must be provided.  The number of bytes copied into the buffer
+ * was defined when the queue was created.
+ *
+ * Successfully received items are removed from the queue.
+ *
+ * This function must not be used in an interrupt service routine.  See
+ * xQueueReceiveFromISR for an alternative that can.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.	 xQueueReceive() will return immediately if xTicksToWait
+ * is zero and the queue is empty.  The time is defined in tick periods so the
+ * constant portTICK_PERIOD_MS should be used to convert to real time if this is
+ * required.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to receive from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Receive a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueReceive xQueueReceive
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );

+ *
+ * Return the number of messages stored in a queue.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of messages available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );

+ *
+ * Return the number of free spaces available in a queue.  This is equal to the
+ * number of items that can be sent to the queue before the queue becomes full
+ * if no items are removed.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of spaces available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
void vQueueDelete( QueueHandle_t xQueue );

+ *
+ * Delete a queue - freeing all the memory allocated for storing of items
+ * placed on the queue.
+ *
+ * @param xQueue A handle to the queue to be deleted.
+ *
+ * \defgroup vQueueDelete vQueueDelete
+ * \ingroup QueueManagement
+ */
+void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToFrontFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+ 

+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the front of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToFromFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPrioritTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )
+
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToBackFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+ 

+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the back of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueOverwriteFromISR(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  BaseType_t *pxHigherPriorityTaskWoken
+						 );
+ * 

+ *
+ * A version of xQueueOverwrite() that can be used in an interrupt service
+ * routine (ISR).
+ *
+ * Only for use with queues that can hold a single item - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueOverwriteFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return xQueueOverwriteFromISR() is a macro that calls
+ * xQueueGenericSendFromISR(), and therefore has the same return values as
+ * xQueueSendToFrontFromISR().  However, pdPASS is the only value that can be
+ * returned because xQueueOverwriteFromISR() will write to the queue even when
+ * the queue is already full.
+ *
+ * Example usage:
+   
+
+ QueueHandle_t xQueue;
+
+ void vFunction( void *pvParameters )
+ {
+ 	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwriteFromISR() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+}
+
+void vAnInterruptHandler( void )
+{
+// xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+uint32_t ulVarToSend, ulValReceived;
+
+	// Write the value 10 to the queue using xQueueOverwriteFromISR().
+	ulVarToSend = 10;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// The queue is full, but calling xQueueOverwriteFromISR() again will still
+	// pass because the value held in the queue will be overwritten with the
+	// new value.
+	ulVarToSend = 100;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// Reading from the queue will now return 100.
+
+	// ...
+
+	if( xHigherPrioritytaskWoken == pdTRUE )
+	{
+		// Writing to the queue caused a task to unblock and the unblocked task
+		// has a priority higher than or equal to the priority of the currently
+		// executing task (the task this interrupt interrupted).  Perform a context
+		// switch so this interrupt returns directly to the unblocked task.
+		portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
+	}
+}
+ 

+ * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendFromISR(
+									 QueueHandle_t xQueue,
+									 const void *pvItemToQueue,
+									 BaseType_t *pxHigherPriorityTaskWoken
+								);
+ 

+ *
+ * This is a macro that calls xQueueGenericSendFromISR().  It is included
+ * for backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()
+ * macros.
+ *
+ * Post an item to the back of a queue.  It is safe to use this function from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		// Actual macro used here is port specific.
+		portYIELD_FROM_ISR ();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueGenericSendFromISR(
+										   QueueHandle_t		xQueue,
+										   const	void	*pvItemToQueue,
+										   BaseType_t	*pxHigherPriorityTaskWoken,
+										   BaseType_t	xCopyPosition
+									   );
+ 

+ *
+ * It is preferred that the macros xQueueSendFromISR(),
+ * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place
+ * of calling this function directly.  xQueueGiveFromISR() is an
+ * equivalent for use by semaphores that don't actually copy any data.
+ *
+ * Post an item on a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueGenericSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWokenByPost;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWokenByPost = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post each byte.
+		xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.  Note that the
+	// name of the yield function required is port specific.
+	if( xHigherPriorityTaskWokenByPost )
+	{
+		taskYIELD_YIELD_FROM_ISR();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueReceiveFromISR(
+									   QueueHandle_t	xQueue,
+									   void	*pvBuffer,
+									   BaseType_t *pxTaskWoken
+								   );
+ * 

+ *
+ * Receive an item from a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param pxTaskWoken A task may be blocked waiting for space to become
+ * available on the queue.  If xQueueReceiveFromISR causes such a task to
+ * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
+ * remain unchanged.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
+
+ QueueHandle_t xQueue;
+
+ // Function to create a queue and post some values.
+ void vAFunction( void *pvParameters )
+ {
+ char cValueToPost;
+ const TickType_t xTicksToWait = ( TickType_t )0xff;
+
+	// Create a queue capable of containing 10 characters.
+	xQueue = xQueueCreate( 10, sizeof( char ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Post some characters that will be used within an ISR.  If the queue
+	// is full then this task will block for xTicksToWait ticks.
+	cValueToPost = 'a';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+	cValueToPost = 'b';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+
+	// ... keep posting characters ... this task may block when the queue
+	// becomes full.
+
+	cValueToPost = 'c';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ }
+
+ // ISR that outputs all the characters received on the queue.
+ void vISR_Routine( void )
+ {
+ BaseType_t xTaskWokenByReceive = pdFALSE;
+ char cRxedChar;
+
+	while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
+	{
+		// A character was received.  Output the character now.
+		vOutputCharacter( cRxedChar );
+
+		// If removing the character from the queue woke the task that was
+		// posting onto the queue cTaskWokenByReceive will have been set to
+		// pdTRUE.  No matter how many times this loop iterates only one
+		// task will be woken.
+	}
+
+	if( cTaskWokenByPost != ( char ) pdFALSE;
+	{
+		taskYIELD ();
+	}
+ }
+ 

+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/*
+ * Utilities to query queues that are safe to use from an ISR.  These utilities
+ * should be used only from witin an ISR, or within a critical section.
+ */
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * The functions defined above are for passing data to and from tasks.  The
+ * functions below are the equivalents for passing data to and from
+ * co-routines.
+ *
+ * These functions are called from the co-routine macro implementation and
+ * should not be called directly from application code.  Instead use the macro
+ * wrappers defined within croutine.h.
+ */
+BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken );
+BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxTaskWoken );
+BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait );
+BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait );
+
+/*
+ * For internal use only.  Use xSemaphoreCreateMutex(),
+ * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling
+ * these functions directly.
+ */
+QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Use xSemaphoreTakeMutexRecursive() or
+ * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
+ */
+BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
+
+/*
+ * Reset a queue back to its original empty state.  The return value is now
+ * obsolete and is always set to pdPASS.
+ */
+#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE )
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger.  If you are not using a kernel
+ * aware debugger then this function can be ignored.
+ *
+ * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the
+ * registry can hold.  configQUEUE_REGISTRY_SIZE must be greater than 0
+ * within FreeRTOSConfig.h for the registry to be available.  Its value
+ * does not effect the number of queues, semaphores and mutexes that can be
+ * created - just the number that the registry can hold.
+ *
+ * @param xQueue The handle of the queue being added to the registry.  This
+ * is the handle returned by a call to xQueueCreate().  Semaphore and mutex
+ * handles can also be passed in here.
+ *
+ * @param pcName The name to be associated with the handle.  This is the
+ * name that the kernel aware debugger will display.  The queue registry only
+ * stores a pointer to the string - so the string must be persistent (global or
+ * preferably in ROM/Flash), not on the stack.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to
+ * remove the queue, semaphore or mutex from the register.  If you are not using
+ * a kernel aware debugger then this function can be ignored.
+ *
+ * @param xQueue The handle of the queue being removed from the registry.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * The queue registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call pcQueueGetName() to look
+ * up and return the name of a queue in the queue registry from the queue's
+ * handle.
+ *
+ * @param xQueue The handle of the queue the name of which will be returned.
+ * @return If the queue is in the registry then a pointer to the name of the
+ * queue is returned.  If the queue is not in the registry then NULL is
+ * returned.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	const char *pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Queue sets provide a mechanism to allow a task to block (pend) on a read
+ * operation from multiple queues or semaphores simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * A queue set must be explicitly created using a call to xQueueCreateSet()
+ * before it can be used.  Once created, standard FreeRTOS queues and semaphores
+ * can be added to the set using calls to xQueueAddToSet().
+ * xQueueSelectFromSet() is then used to determine which, if any, of the queues
+ * or semaphores contained in the set is in a state where a queue read or
+ * semaphore take operation would be successful.
+ *
+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  An additional 4 bytes of RAM is required for each space in a every
+ * queue added to a queue set.  Therefore counting semaphores that have a high
+ * maximum count value should not be added to a queue set.
+ *
+ * Note 4:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param uxEventQueueLength Queue sets store events that occur on
+ * the queues and semaphores contained in the set.  uxEventQueueLength specifies
+ * the maximum number of events that can be queued at once.  To be absolutely
+ * certain that events are not lost uxEventQueueLength should be set to the
+ * total sum of the length of the queues added to the set, where binary
+ * semaphores and mutexes have a length of 1, and counting semaphores have a
+ * length set by their maximum count value.  Examples:
+ *  + If a queue set is to hold a queue of length 5, another queue of length 12,
+ *    and a binary semaphore, then uxEventQueueLength should be set to
+ *    (5 + 12 + 1), or 18.
+ *  + If a queue set is to hold three binary semaphores then uxEventQueueLength
+ *    should be set to (1 + 1 + 1 ), or 3.
+ *  + If a queue set is to hold a counting semaphore that has a maximum count of
+ *    5, and a counting semaphore that has a maximum count of 3, then
+ *    uxEventQueueLength should be set to (5 + 3), or 8.
+ *
+ * @return If the queue set is created successfully then a handle to the created
+ * queue set is returned.  Otherwise NULL is returned.
+ */
+QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * Adds a queue or semaphore to a queue set that was previously created by a
+ * call to xQueueCreateSet().
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being added to
+ * the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set to which the queue or semaphore
+ * is being added.
+ *
+ * @return If the queue or semaphore was successfully added to the queue set
+ * then pdPASS is returned.  If the queue could not be successfully added to the
+ * queue set because it is already a member of a different queue set then pdFAIL
+ * is returned.
+ */
+BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * Removes a queue or semaphore from a queue set.  A queue or semaphore can only
+ * be removed from a set if the queue or semaphore is empty.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being removed
+ * from the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set in which the queue or semaphore
+ * is included.
+ *
+ * @return If the queue or semaphore was successfully removed from the queue set
+ * then pdPASS is returned.  If the queue was not in the queue set, or the
+ * queue (or semaphore) was not empty, then pdFAIL is returned.
+ */
+BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * xQueueSelectFromSet() selects from the members of a queue set a queue or
+ * semaphore that either contains data (in the case of a queue) or is available
+ * to take (in the case of a semaphore).  xQueueSelectFromSet() effectively
+ * allows a task to block (pend) on a read operation on all the queues and
+ * semaphores in a queue set simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueSet The queue set on which the task will (potentially) block.
+ *
+ * @param xTicksToWait The maximum time, in ticks, that the calling task will
+ * remain in the Blocked state (with other tasks executing) to wait for a member
+ * of the queue set to be ready for a successful queue read or semaphore take
+ * operation.
+ *
+ * @return xQueueSelectFromSet() will return the handle of a queue (cast to
+ * a QueueSetMemberHandle_t type) contained in the queue set that contains data,
+ * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained
+ * in the queue set that is available, or NULL if no such queue or semaphore
+ * exists before before the specified block time expires.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * A version of xQueueSelectFromSet() that can be used from an ISR.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/* Not public API functions. */
+void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
+void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* QUEUE_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/include/semphr.h b/FreeRTOSv10.2.1/FreeRTOS/Source/include/semphr.h
new file mode 100644
index 0000000..32b4e5e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/include/semphr.h
@@ -0,0 +1,1140 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef SEMAPHORE_H
+#define SEMAPHORE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include semphr.h"
+#endif
+
+#include "queue.h"
+
+typedef QueueHandle_t SemaphoreHandle_t;
+
+#define semBINARY_SEMAPHORE_QUEUE_LENGTH	( ( uint8_t ) 1U )
+#define semSEMAPHORE_QUEUE_ITEM_LENGTH		( ( uint8_t ) 0U )
+#define semGIVE_BLOCK_TIME					( ( TickType_t ) 0U )
+
+
+/**
+ * semphr. h
+ * 
vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore )

+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * Macro that implements a semaphore by using the existing queue mechanism.
+ * The queue length is 1 as this is a binary semaphore.  The data size is 0
+ * as we don't want to actually store any data - we just want to know if the
+ * queue is empty or full.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param xSemaphore Handle to the created semaphore.  Should be of type SemaphoreHandle_t.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
+    // This is a macro so pass the variable in directly.
+    vSemaphoreCreateBinary( xSemaphore );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define vSemaphoreCreateBinary( xSemaphore )																							\
+		{																																	\
+			( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE );	\
+			if( ( xSemaphore ) != NULL )																									\
+			{																																\
+				( void ) xSemaphoreGive( ( xSemaphore ) );																					\
+			}																																\
+		}
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateBinary( void )

+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @return Handle to the created semaphore, or NULL if the memory required to
+ * hold the semaphore's data structures could not be allocated.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer )

+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * NOTE: In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the semaphore is created then a handle to the created semaphore is
+ * returned.  If pxSemaphoreBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // The semaphore's data structures will be placed in the xSemaphoreBuffer
+    // variable, the address of which is passed into the function.  The
+    // function's parameter is not NULL, so the function will not attempt any
+    // dynamic memory allocation, and therefore the function will not return
+    // return NULL.
+    xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );
+
+    // Rest of task code goes here.
+ }
+ 

+ * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
xSemaphoreTake(
+ *                   SemaphoreHandle_t xSemaphore,
+ *                   TickType_t xBlockTime
+ *               )

+ *
+ * Macro to obtain a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting().
+ *
+ * @param xSemaphore A handle to the semaphore being taken - obtained when
+ * the semaphore was created.
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  A block
+ * time of portMAX_DELAY can be used to block indefinitely (provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE
+ * if xBlockTime expired without the semaphore becoming available.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // A task that creates a semaphore.
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = xSemaphoreCreateBinary();
+ }
+
+ // A task that uses the semaphore.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xSemaphore != NULL )
+    {
+        // See if we can obtain the semaphore.  If the semaphore is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the semaphore and can now access the
+            // shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource.  Release the
+            // semaphore.
+            xSemaphoreGive( xSemaphore );
+        }
+        else
+        {
+            // We could not obtain the semaphore and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreTake xSemaphoreTake
+ * \ingroup Semaphores
+ */
+#define xSemaphoreTake( xSemaphore, xBlockTime )		xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) )
+
+/**
+ * semphr. h
+ * xSemaphoreTakeRecursive(
+ *                          SemaphoreHandle_t xMutex,
+ *                          TickType_t xBlockTime
+ *                        )
+ *
+ * Macro to recursively obtain, or 'take', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being obtained.  This is the
+ * handle returned by xSemaphoreCreateRecursiveMutex();
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  If
+ * the task already owns the semaphore then xSemaphoreTakeRecursive() will
+ * return immediately no matter what the value of xBlockTime.
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE if xBlockTime
+ * expired without the semaphore becoming available.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+            // xSemaphoreTakeRecursive() are made on the same mutex.  In real
+            // code these would not be just sequential calls as this would make
+            // no sense.  Instead the calls are likely to be buried inside
+            // a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+            // available to another task until it has also been given back
+            // three times.  Again it is unlikely that real code would have
+            // these calls sequentially, but instead buried in a more complex
+            // call structure.  This is just for illustrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+            xSemaphoreGiveRecursive( xMutex );
+            xSemaphoreGiveRecursive( xMutex );
+
+            // Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+	#define xSemaphoreTakeRecursive( xMutex, xBlockTime )	xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )
+#endif
+
+/**
+ * semphr. h
+ * 
xSemaphoreGive( SemaphoreHandle_t xSemaphore )

+ *
+ * Macro to release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().
+ *
+ * This macro must not be used from an ISR.  See xSemaphoreGiveFromISR () for
+ * an alternative which can be used from an ISR.
+ *
+ * This macro must also not be used on semaphores created using
+ * xSemaphoreCreateRecursiveMutex().
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @return pdTRUE if the semaphore was released.  pdFALSE if an error occurred.
+ * Semaphores are implemented using queues.  An error can occur if there is
+ * no space on the queue to post a message - indicating that the
+ * semaphore was not first obtained correctly.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = vSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+        {
+            // We would expect this call to fail because we cannot give
+            // a semaphore without first "taking" it!
+        }
+
+        // Obtain the semaphore - don't block if the semaphore is not
+        // immediately available.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
+        {
+            // We now have the semaphore and can access the shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource so can free the
+            // semaphore.
+            if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+            {
+                // We would not expect this call to fail because we must have
+                // obtained the semaphore to get here.
+            }
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreGive xSemaphoreGive
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGive( xSemaphore )		xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )
+
+/**
+ * semphr. h
+ * 
xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex )

+ *
+ * Macro to recursively release, or 'give', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being released, or 'given'.  This is the
+ * handle returned by xSemaphoreCreateMutex();
+ *
+ * @return pdTRUE if the semaphore was given.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
+			// code these would not be just sequential calls as this would make
+			// no sense.  Instead the calls are likely to be buried inside
+			// a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+			// available to another task until it has also been given back
+			// three times.  Again it is unlikely that real code would have
+			// these calls sequentially, it would be more likely that the calls
+			// to xSemaphoreGiveRecursive() would be called as a call stack
+			// unwound.  This is just for demonstrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+
+			// Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+	#define xSemaphoreGiveRecursive( xMutex )	xQueueGiveMutexRecursive( ( xMutex ) )
+#endif
+
+/**
+ * semphr. h
+ * 
+ xSemaphoreGiveFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )

+ *
+ * Macro to  release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR.
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreGiveFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ 
+ \#define LONG_TIME 0xffff
+ \#define TICKS_TO_WAIT	10
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // Repetitive task.
+ void vATask( void * pvParameters )
+ {
+    for( ;; )
+    {
+        // We want this task to run every 10 ticks of a timer.  The semaphore
+        // was created before this task was started.
+
+        // Block waiting for the semaphore to become available.
+        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
+        {
+            // It is time to execute.
+
+            // ...
+
+            // We have finished our task.  Return to the top of the loop where
+            // we will block on the semaphore until it is time to execute
+            // again.  Note when using the semaphore for synchronisation with an
+			// ISR in this manner there is no need to 'give' the semaphore back.
+        }
+    }
+ }
+
+ // Timer ISR
+ void vTimerISR( void * pvParameters )
+ {
+ static uint8_t ucLocalTickCount = 0;
+ static BaseType_t xHigherPriorityTaskWoken;
+
+    // A timer tick has occurred.
+
+    // ... Do other time functions.
+
+    // Is it time for vATask () to run?
+	xHigherPriorityTaskWoken = pdFALSE;
+    ucLocalTickCount++;
+    if( ucLocalTickCount >= TICKS_TO_WAIT )
+    {
+        // Unblock the task by releasing the semaphore.
+        xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
+
+        // Reset the count so we release the semaphore again in 10 ticks time.
+        ucLocalTickCount = 0;
+    }
+
+    if( xHigherPriorityTaskWoken != pdFALSE )
+    {
+        // We can force a context switch here.  Context switching from an
+        // ISR uses port specific syntax.  Check the demo task for your port
+        // to find the syntax required.
+    }
+ }
+ 

+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * 
+ xSemaphoreTakeFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )

+ *
+ * Macro to  take a semaphore from an ISR.  The semaphore must have
+ * previously been created with a call to xSemaphoreCreateBinary() or
+ * xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR, however taking a semaphore from an ISR
+ * is not a common operation.  It is likely to only be useful when taking a
+ * counting semaphore when an interrupt is obtaining an object from a resource
+ * pool (when the semaphore count indicates the number of resources available).
+ *
+ * @param xSemaphore A handle to the semaphore being taken.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreTakeFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully taken, otherwise
+ * pdFALSE
+ */
+#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateMutex( void )

+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * semaphore is returned.  If there was not enough heap to allocate the mutex
+ * data structures then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer )

+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will be used to hold the mutex's data structure, removing the need for
+ * the memory to be allocated dynamically.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * mutex is returned.  If pxMutexBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A mutex cannot be used before it has been created.  xMutexBuffer is
+    // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is
+    // attempted.
+    xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+ 

+ * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic
+ * \ingroup Semaphores
+ */
+ #if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void )

+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return xSemaphore Handle to the created mutex semaphore.  Should be of type
+ * SemaphoreHandle_t.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateRecursiveMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+	#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer )

+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the recursive mutex's data structure,
+ * removing the need for the memory to be allocated dynamically.
+ *
+ * @return If the recursive mutex was successfully created then a handle to the
+ * created recursive mutex is returned.  If pxMutexBuffer was NULL then NULL is
+ * returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A recursive semaphore cannot be used before it is created.  Here a
+    // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().
+    // The address of xMutexBuffer is passed into the function, and will hold
+    // the mutexes data structures - so no dynamic memory allocation will be
+    // attempted.
+    xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+ 

+ * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+	#define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount )

+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * http://www.freertos.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer can
+ * instead optionally provide the memory that will get used by the counting
+ * semaphore.  xSemaphoreCreateCountingStatic() therefore allows a counting
+ * semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @return Handle to the created semaphore.  Null if the semaphore could not be
+ *         created.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
+    // The max value to which the semaphore can count should be 10, and the
+    // initial value assigned to the count should be 0.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0 );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer )

+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * http://www.freertos.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer must
+ * provide the memory.  xSemaphoreCreateCountingStatic() therefore allows a
+ * counting semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the counting semaphore was successfully created then a handle to
+ * the created counting semaphore is returned.  If pxSemaphoreBuffer was NULL
+ * then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Counting semaphore cannot be used before they have been created.  Create
+    // a counting semaphore using xSemaphoreCreateCountingStatic().  The max
+    // value to which the semaphore can count is 10, and the initial value
+    // assigned to the count will be 0.  The address of xSemaphoreBuffer is
+    // passed in and will be used to hold the semaphore structure, so no dynamic
+    // memory allocation will be used.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );
+
+    // No memory allocation was attempted so xSemaphore cannot be NULL, so there
+    // is no need to check its value.
+ }
+ 

+ * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer ) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );

+ *
+ * Delete a semaphore.  This function must be used with care.  For example,
+ * do not delete a mutex type semaphore if the mutex is held by a task.
+ *
+ * @param xSemaphore A handle to the semaphore to be deleted.
+ *
+ * \defgroup vSemaphoreDelete vSemaphoreDelete
+ * \ingroup Semaphores
+ */
+#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );

+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ * Note: This is a good way of determining if the calling task is the mutex
+ * holder, but not a good way of determining the identity of the mutex holder as
+ * the holder may change between the function exiting and the returned value
+ * being tested.
+ */
+#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );

+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ */
+#define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );

+ *
+ * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns
+ * its current count value.  If the semaphore is a binary semaphore then
+ * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the
+ * semaphore is not available.
+ *
+ */
+#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )
+
+#endif /* SEMAPHORE_H */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/include/stack_macros.h b/FreeRTOSv10.2.1/FreeRTOS/Source/include/stack_macros.h
new file mode 100644
index 0000000..fb5ed15
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/include/stack_macros.h
@@ -0,0 +1,129 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef STACK_MACROS_H
+#define STACK_MACROS_H
+
+/*
+ * Call the stack overflow hook function if the stack of the task being swapped
+ * out is currently overflowed, or looks like it might have overflowed in the
+ * past.
+ *
+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
+ * the current stack state only - comparing the current top of stack value to
+ * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
+ * will also cause the last few stack bytes to be checked to ensure the value
+ * to which the bytes were set when the task was created have not been
+ * overwritten.  Note this second test does not guarantee that an overflowed
+ * stack will always be recognised.
+ */
+
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )										\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+																										\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )									\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;							\
+		const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;											\
+																										\
+		if( ( pulStack[ 0 ] != ulCheckValue ) ||														\
+			( pulStack[ 1 ] != ulCheckValue ) ||														\
+			( pulStack[ 2 ] != ulCheckValue ) ||														\
+			( pulStack[ 3 ] != ulCheckValue ) )															\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																								\
+	{																																	\
+	int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;																		\
+	static const uint8_t ucExpectedStackBytes[] = {	tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };	\
+																																		\
+																																		\
+		pcEndOfStack -= sizeof( ucExpectedStackBytes );																					\
+																																		\
+		/* Has the extremity of the task stack ever been written over? */																\
+		if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )					\
+		{																																\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );									\
+		}																																\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+/* Remove stack overflow macro if not being used. */
+#ifndef taskCHECK_FOR_STACK_OVERFLOW
+	#define taskCHECK_FOR_STACK_OVERFLOW()
+#endif
+
+
+
+#endif /* STACK_MACROS_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/include/stdint.readme b/FreeRTOSv10.2.1/FreeRTOS/Source/include/stdint.readme
new file mode 100644
index 0000000..6d86149
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/include/stdint.readme
@@ -0,0 +1,27 @@
+
+#ifndef FREERTOS_STDINT
+#define FREERTOS_STDINT
+
+/*******************************************************************************
+ * THIS IS NOT A FULL stdint.h IMPLEMENTATION - It only contains the definitions
+ * necessary to build the FreeRTOS code.  It is provided to allow FreeRTOS to be
+ * built using compilers that do not provide their own stdint.h definition.
+ *
+ * To use this file:
+ *
+ *    1) Copy this file into the directory that contains your FreeRTOSConfig.h
+ *       header file, as that directory will already be in the compilers include
+ *       path.
+ *
+ *    2) Rename the copied file stdint.h.
+ *
+ */
+
+typedef signed char int8_t;
+typedef unsigned char uint8_t;
+typedef short int16_t;
+typedef unsigned short uint16_t;
+typedef long int32_t;
+typedef unsigned long uint32_t;
+
+#endif /* FREERTOS_STDINT */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/include/stream_buffer.h b/FreeRTOSv10.2.1/FreeRTOS/Source/include/stream_buffer.h
new file mode 100644
index 0000000..5f9e012
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/include/stream_buffer.h
@@ -0,0 +1,855 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Stream buffers are used to send a continuous stream of data from one task or
+ * interrupt to another.  Their implementation is light weight, making them
+ * particularly suited for interrupt to task and core to core communication
+ * scenarios.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section section and set the
+ * receive block time to 0.
+ *
+ */
+
+#ifndef STREAM_BUFFER_H
+#define STREAM_BUFFER_H
+
+#if defined( __cplusplus )
+extern "C" {
+#endif
+
+/**
+ * Type by which stream buffers are referenced.  For example, a call to
+ * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can
+ * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),
+ * etc.
+ */
+struct StreamBufferDef_t;
+typedef struct StreamBufferDef_t * StreamBufferHandle_t;
+
+
+/**
+ * message_buffer.h
+ *
+
+StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
+

+ *
+ * Creates a new stream buffer using dynamically allocated memory.  See
+ * xStreamBufferCreateStatic() for a version that uses statically allocated
+ * memory (memory that is allocated at compile time).
+ *
+ * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
+ * FreeRTOSConfig.h for xStreamBufferCreate() to be available.
+ *
+ * @param xBufferSizeBytes The total number of bytes the stream buffer will be
+ * able to hold at any one time.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @return If NULL is returned, then the stream buffer cannot be created
+ * because there is insufficient heap memory available for FreeRTOS to allocate
+ * the stream buffer data structures and storage area.  A non-NULL value being
+ * returned indicates that the stream buffer has been created successfully -
+ * the returned value should be stored as the handle to the created stream
+ * buffer.
+ *
+ * Example use:
+
+
+void vAFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
+
+    // Create a stream buffer that can hold 100 bytes.  The memory used to hold
+    // both the stream buffer structure and the data in the stream buffer is
+    // allocated dynamically.
+    xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
+
+    if( xStreamBuffer == NULL )
+    {
+        // There was not enough heap memory space available to create the
+        // stream buffer.
+    }
+    else
+    {
+        // The stream buffer was created successfully and can now be used.
+    }
+}
+

+ * \defgroup xStreamBufferCreate xStreamBufferCreate
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE )
+
+/**
+ * stream_buffer.h
+ *
+
+StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
+                                                size_t xTriggerLevelBytes,
+                                                uint8_t *pucStreamBufferStorageArea,
+                                                StaticStreamBuffer_t *pxStaticStreamBuffer );
+

+ * Creates a new stream buffer using statically allocated memory.  See
+ * xStreamBufferCreate() for a version that uses dynamically allocated memory.
+ *
+ * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
+ * xStreamBufferCreateStatic() to be available.
+ *
+ * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
+ * pucStreamBufferStorageArea parameter.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
+ * least xBufferSizeBytes + 1 big.  This is the array to which streams are
+ * copied when they are written to the stream buffer.
+ *
+ * @param pxStaticStreamBuffer Must point to a variable of type
+ * StaticStreamBuffer_t, which will be used to hold the stream buffer's data
+ * structure.
+ *
+ * @return If the stream buffer is created successfully then a handle to the
+ * created stream buffer is returned. If either pucStreamBufferStorageArea or
+ * pxStaticstreamBuffer are NULL then NULL is returned.
+ *
+ * Example use:
+
+
+// Used to dimension the array used to hold the streams.  The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the streams within the stream
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the stream buffer structure.
+StaticStreamBuffer_t xStreamBufferStruct;
+
+void MyFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xTriggerLevel = 1;
+
+    xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ),
+                                               xTriggerLevel,
+                                               ucBufferStorage,
+                                               &xStreamBufferStruct );
+
+    // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
+    // parameters were NULL, xStreamBuffer will not be NULL, and can be used to
+    // reference the created stream buffer in other stream buffer API calls.
+
+    // Other code that uses the stream buffer can go here.
+}
+
+

+ * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer )
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                          const void *pvTxData,
+                          size_t xDataLengthBytes,
+                          TickType_t xTicksToWait );
+

+ *
+ * Sends bytes to a stream buffer.  The bytes are copied into the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the buffer that holds the bytes to be copied
+ * into the stream buffer.
+ *
+ * @param xDataLengthBytes   The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for enough space to become available in the stream
+ * buffer, should the stream buffer contain too little space to hold the
+ * another xDataLengthBytes bytes.  The block time is specified in tick periods,
+ * so the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  If a task times out
+ * before it can write all xDataLengthBytes into the buffer it will still write
+ * as many bytes as possible.  A task does not use any CPU time when it is in
+ * the blocked state.
+ *
+ * @return The number of bytes written to the stream buffer.  If a task times
+ * out before it can write all xDataLengthBytes into the buffer it will still
+ * write as many bytes as possible.
+ *
+ * Example use:
+
+void vAFunction( StreamBufferHandle_t xStreamBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+    // Send an array to the stream buffer, blocking for a maximum of 100ms to
+    // wait for enough space to be available in the stream buffer.
+    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+    if( xBytesSent != sizeof( ucArrayToSend ) )
+    {
+        // The call to xStreamBufferSend() times out before there was enough
+        // space in the buffer for the data to be written, but it did
+        // successfully write xBytesSent bytes.
+    }
+
+    // Send the string to the stream buffer.  Return immediately if there is not
+    // enough space in the buffer.
+    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The entire string could not be added to the stream buffer because
+        // there was not enough free space in the buffer, but xBytesSent bytes
+        // were sent.  Could try again to send the remaining bytes.
+    }
+}
+

+ * \defgroup xStreamBufferSend xStreamBufferSend
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+						  const void *pvTxData,
+						  size_t xDataLengthBytes,
+						  TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+                                 const void *pvTxData,
+                                 size_t xDataLengthBytes,
+                                 BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * Interrupt safe version of the API function that sends a stream of bytes to
+ * the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the data that is to be copied into the stream
+ * buffer.
+ *
+ * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xStreamBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xStreamBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the example code below for an example.
+ *
+ * @return The number of bytes actually written to the stream buffer, which will
+ * be less than xDataLengthBytes if the stream buffer didn't have enough free
+ * space for all the bytes to be written.
+ *
+ * Example use:
+
+// A stream buffer that has already been created.
+StreamBufferHandle_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+    // Attempt to send the string to the stream buffer.
+    xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,
+                                           ( void * ) pcStringToSend,
+                                           strlen( pcStringToSend ),
+                                           &xHigherPriorityTaskWoken );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // There was not enough free space in the stream buffer for the entire
+        // string to be written, ut xBytesSent bytes were written.
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xStreamBufferSendFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+								 const void *pvTxData,
+								 size_t xDataLengthBytes,
+								 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                             void *pvRxData,
+                             size_t xBufferLengthBytes,
+                             TickType_t xTicksToWait );
+

+ *
+ * Receives bytes from a stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferReceive() to read from a stream buffer from a task.  Use
+ * xStreamBufferReceiveFromISR() to read from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which bytes are to
+ * be received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes will be
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for data to become available if the stream buffer is
+ * empty.  xStreamBufferReceive() will return immediately if xTicksToWait is
+ * zero.  The block time is specified in tick periods, so the absolute time it
+ * represents is dependent on the tick frequency.  The macro pdMS_TO_TICKS() can
+ * be used to convert a time specified in milliseconds into a time specified in
+ * ticks.  Setting xTicksToWait to portMAX_DELAY will cause the task to wait
+ * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1
+ * in FreeRTOSConfig.h.  A task does not use any CPU time when it is in the
+ * Blocked state.
+ *
+ * @return The number of bytes actually read from the stream buffer, which will
+ * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed
+ * out before xBufferLengthBytes were available.
+ *
+ * Example use:
+
+void vAFunction( StreamBuffer_t xStreamBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+    // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.
+    // Wait in the Blocked state (so not using any CPU processing time) for a
+    // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be
+    // available.
+    xReceivedBytes = xStreamBufferReceive( xStreamBuffer,
+                                           ( void * ) ucRxData,
+                                           sizeof( ucRxData ),
+                                           xBlockTime );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains another xRecievedBytes bytes of data, which can
+        // be processed here....
+    }
+}
+

+ * \defgroup xStreamBufferReceive xStreamBufferReceive
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+							 void *pvRxData,
+							 size_t xBufferLengthBytes,
+							 TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+                                    void *pvRxData,
+                                    size_t xBufferLengthBytes,
+                                    BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * An interrupt safe version of the API function that receives bytes from a
+ * stream buffer.
+ *
+ * Use xStreamBufferReceive() to read bytes from a stream buffer from a task.
+ * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which a stream
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes are
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xStreamBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes read from the stream buffer, if any.
+ *
+ * Example use:
+
+// A stream buffer that has already been created.
+StreamBuffer_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+
+    // Receive the next stream from the stream buffer.
+    xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,
+                                                  ( void * ) ucRxData,
+                                                  sizeof( ucRxData ),
+                                                  &xHigherPriorityTaskWoken );
+
+    if( xReceivedBytes > 0 )
+    {
+        // ucRxData contains xReceivedBytes read from the stream buffer.
+        // Process the stream here....
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xStreamBufferReceiveFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+									void *pvRxData,
+									size_t xBufferLengthBytes,
+									BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Deletes a stream buffer that was previously created using a call to
+ * xStreamBufferCreate() or xStreamBufferCreateStatic().  If the stream
+ * buffer was created using dynamic memory (that is, by xStreamBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A stream buffer handle must not be used after the stream buffer has been
+ * deleted.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to be deleted.
+ *
+ * \defgroup vStreamBufferDelete vStreamBufferDelete
+ * \ingroup StreamBufferManagement
+ */
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see if it is full.  A stream buffer is full if it
+ * does not have any free space, and therefore cannot accept any more data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is full then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsFull xStreamBufferIsFull
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see if it is empty.  A stream buffer is empty if
+ * it does not contain any data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is empty then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Resets a stream buffer to its initial, empty, state.  Any data that was in
+ * the stream buffer is discarded.  A stream buffer can only be reset if there
+ * are no tasks blocked waiting to either send to or receive from the stream
+ * buffer.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being reset.
+ *
+ * @return If the stream buffer is reset then pdPASS is returned.  If there was
+ * a task blocked waiting to send to or read from the stream buffer then the
+ * stream buffer is not reset and pdFAIL is returned.
+ *
+ * \defgroup xStreamBufferReset xStreamBufferReset
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see how much free space it contains, which is
+ * equal to the amount of data that can be sent to the stream buffer before it
+ * is full.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be written to the stream buffer before
+ * the stream buffer would be full.
+ *
+ * \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see how much data it contains, which is equal to
+ * the number of bytes that can be read from the stream buffer before the stream
+ * buffer would be empty.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be read from the stream buffer before
+ * the stream buffer would be empty.
+ *
+ * \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
+

+ *
+ * A stream buffer's trigger level is the number of bytes that must be in the
+ * stream buffer before a task that is blocked on the stream buffer to
+ * wait for data is moved out of the blocked state.  For example, if a task is
+ * blocked on a read of an empty stream buffer that has a trigger level of 1
+ * then the task will be unblocked when a single byte is written to the buffer
+ * or the task's block time expires.  As another example, if a task is blocked
+ * on a read of an empty stream buffer that has a trigger level of 10 then the
+ * task will not be unblocked until the stream buffer contains at least 10 bytes
+ * or the task's block time expires.  If a reading task's block time expires
+ * before the trigger level is reached then the task will still receive however
+ * many bytes are actually available.  Setting a trigger level of 0 will result
+ * in a trigger level of 1 being used.  It is not valid to specify a trigger
+ * level that is greater than the buffer size.
+ *
+ * A trigger level is set when the stream buffer is created, and can be modified
+ * using xStreamBufferSetTriggerLevel().
+ *
+ * @param xStreamBuffer The handle of the stream buffer being updated.
+ *
+ * @param xTriggerLevel The new trigger level for the stream buffer.
+ *
+ * @return If xTriggerLevel was less than or equal to the stream buffer's length
+ * then the trigger level will be updated and pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xStreamBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferSendCompletedFromISR().  If calling
+ * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xStreamBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferReceiveCompletedFromISR().  If calling
+ * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/* Functions below here are not part of the public API. */
+StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+												 size_t xTriggerLevelBytes,
+												 BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;
+
+StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+													   size_t xTriggerLevelBytes,
+													   BaseType_t xIsMessageBuffer,
+													   uint8_t * const pucStreamBufferStorageArea,
+													   StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;
+	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+#endif
+
+#if defined( __cplusplus )
+}
+#endif
+
+#endif	/* !defined( STREAM_BUFFER_H ) */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/include/task.h b/FreeRTOSv10.2.1/FreeRTOS/Source/include/task.h
new file mode 100644
index 0000000..4041bbf
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/include/task.h
@@ -0,0 +1,2421 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef INC_TASK_H
+#define INC_TASK_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include task.h"
+#endif
+
+#include "list.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+#define tskKERNEL_VERSION_NUMBER "V10.2.0"
+#define tskKERNEL_VERSION_MAJOR 10
+#define tskKERNEL_VERSION_MINOR 2
+#define tskKERNEL_VERSION_BUILD 0
+
+/* MPU region parameters passed in ulParameters
+ * of MemoryRegion_t struct. */
+#define tskMPU_REGION_READ_ONLY			( 1UL << 0UL )
+#define tskMPU_REGION_READ_WRITE		( 1UL << 1UL )
+#define tskMPU_REGION_EXECUTE_NEVER		( 1UL << 2UL )
+#define tskMPU_REGION_NORMAL_MEMORY		( 1UL << 3UL )
+#define tskMPU_REGION_DEVICE_MEMORY		( 1UL << 4UL )
+
+/**
+ * task. h
+ *
+ * Type by which tasks are referenced.  For example, a call to xTaskCreate
+ * returns (via a pointer parameter) an TaskHandle_t variable that can then
+ * be used as a parameter to vTaskDelete to delete the task.
+ *
+ * \defgroup TaskHandle_t TaskHandle_t
+ * \ingroup Tasks
+ */
+struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tskTaskControlBlock* TaskHandle_t;
+
+/*
+ * Defines the prototype to which the application task hook function must
+ * conform.
+ */
+typedef BaseType_t (*TaskHookFunction_t)( void * );
+
+/* Task states returned by eTaskGetState. */
+typedef enum
+{
+	eRunning = 0,	/* A task is querying the state of itself, so must be running. */
+	eReady,			/* The task being queried is in a read or pending ready list. */
+	eBlocked,		/* The task being queried is in the Blocked state. */
+	eSuspended,		/* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
+	eDeleted,		/* The task being queried has been deleted, but its TCB has not yet been freed. */
+	eInvalid		/* Used as an 'invalid state' value. */
+} eTaskState;
+
+/* Actions that can be performed when vTaskNotify() is called. */
+typedef enum
+{
+	eNoAction = 0,				/* Notify the task without updating its notify value. */
+	eSetBits,					/* Set bits in the task's notification value. */
+	eIncrement,					/* Increment the task's notification value. */
+	eSetValueWithOverwrite,		/* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */
+	eSetValueWithoutOverwrite	/* Set the task's notification value if the previous value has been read by the task. */
+} eNotifyAction;
+
+/*
+ * Used internally only.
+ */
+typedef struct xTIME_OUT
+{
+	BaseType_t xOverflowCount;
+	TickType_t xTimeOnEntering;
+} TimeOut_t;
+
+/*
+ * Defines the memory ranges allocated to the task when an MPU is used.
+ */
+typedef struct xMEMORY_REGION
+{
+	void *pvBaseAddress;
+	uint32_t ulLengthInBytes;
+	uint32_t ulParameters;
+} MemoryRegion_t;
+
+/*
+ * Parameters required to create an MPU protected task.
+ */
+typedef struct xTASK_PARAMETERS
+{
+	TaskFunction_t pvTaskCode;
+	const char * const pcName;	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	configSTACK_DEPTH_TYPE usStackDepth;
+	void *pvParameters;
+	UBaseType_t uxPriority;
+	StackType_t *puxStackBuffer;
+	MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];
+	#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+		StaticTask_t * const pxTaskBuffer;
+	#endif
+} TaskParameters_t;
+
+/* Used with the uxTaskGetSystemState() function to return the state of each task
+in the system. */
+typedef struct xTASK_STATUS
+{
+	TaskHandle_t xHandle;			/* The handle of the task to which the rest of the information in the structure relates. */
+	const char *pcTaskName;			/* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	UBaseType_t xTaskNumber;		/* A number unique to the task. */
+	eTaskState eCurrentState;		/* The state in which the task existed when the structure was populated. */
+	UBaseType_t uxCurrentPriority;	/* The priority at which the task was running (may be inherited) when the structure was populated. */
+	UBaseType_t uxBasePriority;		/* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
+	uint32_t ulRunTimeCounter;		/* The total run time allocated to the task so far, as defined by the run time stats clock.  See http://www.freertos.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
+	StackType_t *pxStackBase;		/* Points to the lowest address of the task's stack area. */
+	configSTACK_DEPTH_TYPE usStackHighWaterMark;	/* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */
+} TaskStatus_t;
+
+/* Possible return values for eTaskConfirmSleepModeStatus(). */
+typedef enum
+{
+	eAbortSleep = 0,		/* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
+	eStandardSleep,			/* Enter a sleep mode that will not last any longer than the expected idle time. */
+	eNoTasksWaitingTimeout	/* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
+} eSleepModeStatus;
+
+/**
+ * Defines the priority used by the idle task.  This must not be modified.
+ *
+ * \ingroup TaskUtils
+ */
+#define tskIDLE_PRIORITY			( ( UBaseType_t ) 0U )
+
+/**
+ * task. h
+ *
+ * Macro for forcing a context switch.
+ *
+ * \defgroup taskYIELD taskYIELD
+ * \ingroup SchedulerControl
+ */
+#define taskYIELD()					portYIELD()
+
+/**
+ * task. h
+ *
+ * Macro to mark the start of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskENTER_CRITICAL()		portENTER_CRITICAL()
+#define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()
+
+/**
+ * task. h
+ *
+ * Macro to mark the end of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskEXIT_CRITICAL()			portEXIT_CRITICAL()
+#define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x )
+/**
+ * task. h
+ *
+ * Macro to disable all maskable interrupts.
+ *
+ * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskDISABLE_INTERRUPTS()	portDISABLE_INTERRUPTS()
+
+/**
+ * task. h
+ *
+ * Macro to enable microcontroller interrupts.
+ *
+ * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskENABLE_INTERRUPTS()		portENABLE_INTERRUPTS()
+
+/* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is
+0 to generate more optimal code when configASSERT() is defined as the constant
+is used in assert() statements. */
+#define taskSCHEDULER_SUSPENDED		( ( BaseType_t ) 0 )
+#define taskSCHEDULER_NOT_STARTED	( ( BaseType_t ) 1 )
+#define taskSCHEDULER_RUNNING		( ( BaseType_t ) 2 )
+
+
+/*-----------------------------------------------------------
+ * TASK CREATION API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ *
+ BaseType_t xTaskCreate(
+							  TaskFunction_t pvTaskCode,
+							  const char * const pcName,
+							  configSTACK_DEPTH_TYPE usStackDepth,
+							  void *pvParameters,
+							  UBaseType_t uxPriority,
+							  TaskHandle_t *pvCreatedTask
+						  );

+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * See xTaskCreateStatic() for a version that does not use any dynamic memory
+ * allocation.
+ *
+ * xTaskCreate() can only be used to create a task that has unrestricted
+ * access to the entire microcontroller memory map.  Systems that include MPU
+ * support can alternatively create an MPU constrained task using
+ * xTaskCreateRestricted().
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default
+ * is 16.
+ *
+ * @param usStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task should run.  Systems that
+ * include MPU support can optionally create tasks in a privileged (system)
+ * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For
+ * example, to create a privileged task at priority 2 the uxPriority parameter
+ * should be set to ( 2 | portPRIVILEGE_BIT ).
+ *
+ * @param pvCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
+ // Task to be created.
+ void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+	 }
+ }
+
+ // Function that creates a task.
+ void vOtherFunction( void )
+ {
+ static uint8_t ucParameterToPass;
+ TaskHandle_t xHandle = NULL;
+
+	 // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass
+	 // must exist for the lifetime of the task, so in this case is declared static.  If it was just an
+	 // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
+	 // the new task attempts to access it.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
+     configASSERT( xHandle );
+
+	 // Use the handle to delete the task.
+     if( xHandle != NULL )
+     {
+	     vTaskDelete( xHandle );
+     }
+ }
+   

+ * \defgroup xTaskCreate xTaskCreate
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
+							const char * const pcName,	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
+ TaskHandle_t xTaskCreateStatic( TaskFunction_t pvTaskCode,
+								 const char * const pcName,
+								 uint32_t ulStackDepth,
+								 void *pvParameters,
+								 UBaseType_t uxPriority,
+								 StackType_t *pxStackBuffer,
+								 StaticTask_t *pxTaskBuffer );

+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  The maximum length of the string is defined by
+ * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.
+ *
+ * @param ulStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task will run.
+ *
+ * @param pxStackBuffer Must point to a StackType_t array that has at least
+ * ulStackDepth indexes - the array will then be used as the task's stack,
+ * removing the need for the stack to be allocated dynamically.
+ *
+ * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will
+ * then be used to hold the task's data structures, removing the need for the
+ * memory to be allocated dynamically.
+ *
+ * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will
+ * be created and a handle to the created task is returned.  If either
+ * pxStackBuffer or pxTaskBuffer are NULL then the task will not be created and
+ * NULL is returned.
+ *
+ * Example usage:
+   
+
+    // Dimensions the buffer that the task being created will use as its stack.
+    // NOTE:  This is the number of words the stack will hold, not the number of
+    // bytes.  For example, if each stack item is 32-bits, and this is set to 100,
+    // then 400 bytes (100 * 32-bits) will be allocated.
+    #define STACK_SIZE 200
+
+    // Structure that will hold the TCB of the task being created.
+    StaticTask_t xTaskBuffer;
+
+    // Buffer that the task being created will use as its stack.  Note this is
+    // an array of StackType_t variables.  The size of StackType_t is dependent on
+    // the RTOS port.
+    StackType_t xStack[ STACK_SIZE ];
+
+    // Function that implements the task being created.
+    void vTaskCode( void * pvParameters )
+    {
+        // The parameter value is expected to be 1 as 1 is passed in the
+        // pvParameters value in the call to xTaskCreateStatic().
+        configASSERT( ( uint32_t ) pvParameters == 1UL );
+
+        for( ;; )
+        {
+            // Task code goes here.
+        }
+    }
+
+    // Function that creates a task.
+    void vOtherFunction( void )
+    {
+        TaskHandle_t xHandle = NULL;
+
+        // Create the task without using any dynamic memory allocation.
+        xHandle = xTaskCreateStatic(
+                      vTaskCode,       // Function that implements the task.
+                      "NAME",          // Text name for the task.
+                      STACK_SIZE,      // Stack size in words, not bytes.
+                      ( void * ) 1,    // Parameter passed into the task.
+                      tskIDLE_PRIORITY,// Priority at which the task is created.
+                      xStack,          // Array to use as the task's stack.
+                      &xTaskBuffer );  // Variable to hold the task's data structure.
+
+        // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have
+        // been created, and xHandle will be the task's handle.  Use the handle
+        // to suspend the task.
+        vTaskSuspend( xHandle );
+    }
+   

+ * \defgroup xTaskCreateStatic xTaskCreateStatic
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
+									const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * task. h
+ *
+ BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );

+ *
+ * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestricted() should only be used in systems that include an MPU
+ * implementation.
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ * The function parameters define the memory regions and associated access
+ * permissions allocated to the task.
+ *
+ * See xTaskCreateRestrictedStatic() for a version that does not use any
+ * dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
+// Create an TaskParameters_t structure that defines the task to be created.
+static const TaskParameters_t xCheckTaskParameters =
+{
+	vATask,		// pvTaskCode - the function that implements the task.
+	"ATask",	// pcName - just a text name for the task to assist debugging.
+	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
+	NULL,		// pvParameters - passed into the task function as the function parameters.
+	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+	// xRegions - Allocate up to three separate memory regions for access by
+	// the task, with appropriate access permissions.  Different processors have
+	// different memory alignment requirements - refer to the FreeRTOS documentation
+	// for full information.
+	{
+		// Base address					Length	Parameters
+        { cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+        { cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+        { cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+	}
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+	// Create a task from the const structure defined above.  The task handle
+	// is requested (the second parameter is not NULL) but in this case just for
+	// demonstration purposes as its not actually used.
+	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+	// Start the scheduler.
+	vTaskStartScheduler();
+
+	// Will only get here if there was insufficient memory to create the idle
+	// and/or timer task.
+	for( ;; );
+}
+   

+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
+ BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );

+ *
+ * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestrictedStatic() should only be used in systems that include an
+ * MPU implementation.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreateRestricted() then the stack is provided by the application writer,
+ * and the memory used to hold the task's data structure is automatically
+ * dynamically allocated inside the xTaskCreateRestricted() function.  If a task
+ * is created using xTaskCreateRestrictedStatic() then the application writer
+ * must provide the memory used to hold the task's data structures too.
+ * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be
+ * created without using any dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.  If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure
+ * contains an additional member, which is used to point to a variable of type
+ * StaticTask_t - which is then used to hold the task's data structure.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
+// Create an TaskParameters_t structure that defines the task to be created.
+// The StaticTask_t variable is only included in the structure when
+// configSUPPORT_STATIC_ALLOCATION is set to 1.  The PRIVILEGED_DATA macro can
+// be used to force the variable into the RTOS kernel's privileged data area.
+static PRIVILEGED_DATA StaticTask_t xTaskBuffer;
+static const TaskParameters_t xCheckTaskParameters =
+{
+	vATask,		// pvTaskCode - the function that implements the task.
+	"ATask",	// pcName - just a text name for the task to assist debugging.
+	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
+	NULL,		// pvParameters - passed into the task function as the function parameters.
+	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+	// xRegions - Allocate up to three separate memory regions for access by
+	// the task, with appropriate access permissions.  Different processors have
+	// different memory alignment requirements - refer to the FreeRTOS documentation
+	// for full information.
+	{
+		// Base address					Length	Parameters
+        { cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+        { cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+        { cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+	}
+
+	&xTaskBuffer; // Holds the task's data structure.
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+	// Create a task from the const structure defined above.  The task handle
+	// is requested (the second parameter is not NULL) but in this case just for
+	// demonstration purposes as its not actually used.
+	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+	// Start the scheduler.
+	vTaskStartScheduler();
+
+	// Will only get here if there was insufficient memory to create the idle
+	// and/or timer task.
+	for( ;; );
+}
+   

+ * \defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic
+ * \ingroup Tasks
+ */
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
+ void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );

+ *
+ * Memory regions are assigned to a restricted task when the task is created by
+ * a call to xTaskCreateRestricted().  These regions can be redefined using
+ * vTaskAllocateMPURegions().
+ *
+ * @param xTask The handle of the task being updated.
+ *
+ * @param xRegions A pointer to an MemoryRegion_t structure that contains the
+ * new memory region definitions.
+ *
+ * Example usage:
+   
+// Define an array of MemoryRegion_t structures that configures an MPU region
+// allowing read/write access for 1024 bytes starting at the beginning of the
+// ucOneKByte array.  The other two of the maximum 3 definable regions are
+// unused so set to zero.
+static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
+{
+	// Base address		Length		Parameters
+	{ ucOneKByte,		1024,		portMPU_REGION_READ_WRITE },
+	{ 0,				0,			0 },
+	{ 0,				0,			0 }
+};
+
+void vATask( void *pvParameters )
+{
+	// This task was created such that it has access to certain regions of
+	// memory as defined by the MPU configuration.  At some point it is
+	// desired that these MPU regions are replaced with that defined in the
+	// xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()
+	// for this purpose.  NULL is used as the task handle to indicate that this
+	// function should modify the MPU regions of the calling task.
+	vTaskAllocateMPURegions( NULL, xAltRegions );
+
+	// Now the task can continue its function, but from this point on can only
+	// access its stack and the ucOneKByte array (unless any other statically
+	// defined or shared regions have been declared elsewhere).
+}
+   

+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskDelete( TaskHandle_t xTask );

+ *
+ * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Remove a task from the RTOS real time kernel's management.  The task being
+ * deleted will be removed from all ready, blocked, suspended and event lists.
+ *
+ * NOTE:  The idle task is responsible for freeing the kernel allocated
+ * memory from tasks that have been deleted.  It is therefore important that
+ * the idle task is not starved of microcontroller processing time if your
+ * application makes any calls to vTaskDelete ().  Memory allocated by the
+ * task code is not automatically freed, and should be freed before the task
+ * is deleted.
+ *
+ * See the demo application file death.c for sample code that utilises
+ * vTaskDelete ().
+ *
+ * @param xTask The handle of the task to be deleted.  Passing NULL will
+ * cause the calling task to be deleted.
+ *
+ * Example usage:
+   
+ void vOtherFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create the task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // Use the handle to delete the task.
+	 vTaskDelete( xHandle );
+ }
+   

+ * \defgroup vTaskDelete vTaskDelete
+ * \ingroup Tasks
+ */
+void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK CONTROL API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
void vTaskDelay( const TickType_t xTicksToDelay );

+ *
+ * Delay a task for a given number of ticks.  The actual time that the
+ * task remains blocked depends on the tick rate.  The constant
+ * portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ *
+ * vTaskDelay() specifies a time at which the task wishes to unblock relative to
+ * the time at which vTaskDelay() is called.  For example, specifying a block
+ * period of 100 ticks will cause the task to unblock 100 ticks after
+ * vTaskDelay() is called.  vTaskDelay() does not therefore provide a good method
+ * of controlling the frequency of a periodic task as the path taken through the
+ * code, as well as other task and interrupt activity, will effect the frequency
+ * at which vTaskDelay() gets called and therefore the time at which the task
+ * next executes.  See vTaskDelayUntil() for an alternative API function designed
+ * to facilitate fixed frequency execution.  It does this by specifying an
+ * absolute time (rather than a relative time) at which the calling task should
+ * unblock.
+ *
+ * @param xTicksToDelay The amount of time, in tick periods, that
+ * the calling task should block.
+ *
+ * Example usage:
+
+ void vTaskFunction( void * pvParameters )
+ {
+ // Block for 500ms.
+ const TickType_t xDelay = 500 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		 // Simply toggle the LED every 500ms, blocking between each toggle.
+		 vToggleLED();
+		 vTaskDelay( xDelay );
+	 }
+ }
+
+ * \defgroup vTaskDelay vTaskDelay
+ * \ingroup TaskCtrl
+ */
+void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );

+ *
+ * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Delay a task until a specified time.  This function can be used by periodic
+ * tasks to ensure a constant execution frequency.
+ *
+ * This function differs from vTaskDelay () in one important aspect:  vTaskDelay () will
+ * cause a task to block for the specified number of ticks from the time vTaskDelay () is
+ * called.  It is therefore difficult to use vTaskDelay () by itself to generate a fixed
+ * execution frequency as the time between a task starting to execute and that task
+ * calling vTaskDelay () may not be fixed [the task may take a different path though the
+ * code between calls, or may get interrupted or preempted a different number of times
+ * each time it executes].
+ *
+ * Whereas vTaskDelay () specifies a wake time relative to the time at which the function
+ * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to
+ * unblock.
+ *
+ * The constant portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the
+ * task was last unblocked.  The variable must be initialised with the current time
+ * prior to its first use (see the example below).  Following this the variable is
+ * automatically updated within vTaskDelayUntil ().
+ *
+ * @param xTimeIncrement The cycle time period.  The task will be unblocked at
+ * time *pxPreviousWakeTime + xTimeIncrement.  Calling vTaskDelayUntil with the
+ * same xTimeIncrement parameter value will cause the task to execute with
+ * a fixed interface period.
+ *
+ * Example usage:
+   
+ // Perform an action every 10 ticks.
+ void vTaskFunction( void * pvParameters )
+ {
+ TickType_t xLastWakeTime;
+ const TickType_t xFrequency = 10;
+
+	 // Initialise the xLastWakeTime variable with the current time.
+	 xLastWakeTime = xTaskGetTickCount ();
+	 for( ;; )
+	 {
+		 // Wait for the next cycle.
+		 vTaskDelayUntil( &xLastWakeTime, xFrequency );
+
+		 // Perform action here.
+	 }
+ }
+   

+ * \defgroup vTaskDelayUntil vTaskDelayUntil
+ * \ingroup TaskCtrl
+ */
+void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskAbortDelay( TaskHandle_t xTask );

+ *
+ * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this
+ * function to be available.
+ *
+ * A task will enter the Blocked state when it is waiting for an event.  The
+ * event it is waiting for can be a temporal event (waiting for a time), such
+ * as when vTaskDelay() is called, or an event on an object, such as when
+ * xQueueReceive() or ulTaskNotifyTake() is called.  If the handle of a task
+ * that is in the Blocked state is used in a call to xTaskAbortDelay() then the
+ * task will leave the Blocked state, and return from whichever function call
+ * placed the task into the Blocked state.
+ *
+ * @param xTask The handle of the task to remove from the Blocked state.
+ *
+ * @return If the task referenced by xTask was not in the Blocked state then
+ * pdFAIL is returned.  Otherwise pdPASS is returned.
+ *
+ * \defgroup xTaskAbortDelay xTaskAbortDelay
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );

+ *
+ * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the priority of any task.
+ *
+ * @param xTask Handle of the task to be queried.  Passing a NULL
+ * handle results in the priority of the calling task being returned.
+ *
+ * @return The priority of xTask.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to obtain the priority of the created task.
+	 // It was created with tskIDLE_PRIORITY, but may have changed
+	 // it itself.
+	 if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
+	 {
+		 // The task has changed it's priority.
+	 }
+
+	 // ...
+
+	 // Is our priority higher than the created task?
+	 if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
+	 {
+		 // Our priority (obtained using NULL handle) is higher.
+	 }
+ }
+   

+ * \defgroup uxTaskPriorityGet uxTaskPriorityGet
+ * \ingroup TaskCtrl
+ */
+UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );

+ *
+ * A version of uxTaskPriorityGet() that can be used from an ISR.
+ */
+UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
eTaskState eTaskGetState( TaskHandle_t xTask );

+ *
+ * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the state of any task.  States are encoded by the eTaskState
+ * enumerated type.
+ *
+ * @param xTask Handle of the task to be queried.
+ *
+ * @return The state of xTask at the time the function was called.  Note the
+ * state of the task might change between the function being called, and the
+ * functions return value being tested by the calling task.
+ */
+eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );

+ *
+ * configUSE_TRACE_FACILITY must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * Populates a TaskStatus_t structure with information about a task.
+ *
+ * @param xTask Handle of the task being queried.  If xTask is NULL then
+ * information will be returned about the calling task.
+ *
+ * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be
+ * filled with information about the task referenced by the handle passed using
+ * the xTask parameter.
+ *
+ * @xGetFreeStackSpace The TaskStatus_t structure contains a member to report
+ * the stack high water mark of the task being queried.  Calculating the stack
+ * high water mark takes a relatively long time, and can make the system
+ * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to
+ * allow the high water mark checking to be skipped.  The high watermark value
+ * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is
+ * not set to pdFALSE;
+ *
+ * @param eState The TaskStatus_t structure contains a member to report the
+ * state of the task being queried.  Obtaining the task state is not as fast as
+ * a simple assignment - so the eState parameter is provided to allow the state
+ * information to be omitted from the TaskStatus_t structure.  To obtain state
+ * information then set eState to eInvalid - otherwise the value passed in
+ * eState will be reported as the task state in the TaskStatus_t structure.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+ TaskStatus_t xTaskDetails;
+
+    // Obtain the handle of a task from its name.
+    xHandle = xTaskGetHandle( "Task_Name" );
+
+    // Check the handle is not NULL.
+    configASSERT( xHandle );
+
+    // Use the handle to obtain further information about the task.
+    vTaskGetInfo( xHandle,
+                  &xTaskDetails,
+                  pdTRUE, // Include the high water mark in xTaskDetails.
+                  eInvalid ); // Include the task state in xTaskDetails.
+ }
+   

+ * \defgroup vTaskGetInfo vTaskGetInfo
+ * \ingroup TaskCtrl
+ */
+void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );

+ *
+ * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Set the priority of any task.
+ *
+ * A context switch will occur before the function returns if the priority
+ * being set is higher than the currently executing task.
+ *
+ * @param xTask Handle to the task for which the priority is being set.
+ * Passing a NULL handle results in the priority of the calling task being set.
+ *
+ * @param uxNewPriority The priority to which the task will be set.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to raise the priority of the created task.
+	 vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
+
+	 // ...
+
+	 // Use a NULL handle to raise our priority to the same value.
+	 vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
+ }
+   

+ * \defgroup vTaskPrioritySet vTaskPrioritySet
+ * \ingroup TaskCtrl
+ */
+void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskSuspend( TaskHandle_t xTaskToSuspend );

+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Suspend any task.  When suspended a task will never get any microcontroller
+ * processing time, no matter what its priority.
+ *
+ * Calls to vTaskSuspend are not accumulative -
+ * i.e. calling vTaskSuspend () twice on the same task still only requires one
+ * call to vTaskResume () to ready the suspended task.
+ *
+ * @param xTaskToSuspend Handle to the task being suspended.  Passing a NULL
+ * handle will cause the calling task to be suspended.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Suspend ourselves.
+	 vTaskSuspend( NULL );
+
+	 // We cannot get here unless another task calls vTaskResume
+	 // with our handle as the parameter.
+ }
+   

+ * \defgroup vTaskSuspend vTaskSuspend
+ * \ingroup TaskCtrl
+ */
+void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskResume( TaskHandle_t xTaskToResume );

+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Resumes a suspended task.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * vTaskResume ().
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Resume the suspended task ourselves.
+	 vTaskResume( xHandle );
+
+	 // The created task will once again get microcontroller processing
+	 // time in accordance with its priority within the system.
+ }
+   

+ * \defgroup vTaskResume vTaskResume
+ * \ingroup TaskCtrl
+ */
+void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void xTaskResumeFromISR( TaskHandle_t xTaskToResume );

+ *
+ * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * An implementation of vTaskResume() that can be called from within an ISR.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * xTaskResumeFromISR ().
+ *
+ * xTaskResumeFromISR() should not be used to synchronise a task with an
+ * interrupt if there is a chance that the interrupt could arrive prior to the
+ * task being suspended - as this can lead to interrupts being missed. Use of a
+ * semaphore as a synchronisation mechanism would avoid this eventuality.
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * @return pdTRUE if resuming the task should result in a context switch,
+ * otherwise pdFALSE. This is used by the ISR to determine if a context switch
+ * may be required following the ISR.
+ *
+ * \defgroup vTaskResumeFromISR vTaskResumeFromISR
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * SCHEDULER CONTROL
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
void vTaskStartScheduler( void );

+ *
+ * Starts the real time kernel tick processing.  After calling the kernel
+ * has control over which tasks are executed and when.
+ *
+ * See the demo application file main.c for an example of creating
+ * tasks and starting the kernel.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will not get here unless a task calls vTaskEndScheduler ()
+ }
+   

+ *
+ * \defgroup vTaskStartScheduler vTaskStartScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskEndScheduler( void );

+ *
+ * NOTE:  At the time of writing only the x86 real mode port, which runs on a PC
+ * in place of DOS, implements this function.
+ *
+ * Stops the real time kernel tick.  All created tasks will be automatically
+ * deleted and multitasking (either preemptive or cooperative) will
+ * stop.  Execution then resumes from the point where vTaskStartScheduler ()
+ * was called, as if vTaskStartScheduler () had just returned.
+ *
+ * See the demo application file main. c in the demo/PC directory for an
+ * example that uses vTaskEndScheduler ().
+ *
+ * vTaskEndScheduler () requires an exit function to be defined within the
+ * portable layer (see vPortEndScheduler () in port. c for the PC port).  This
+ * performs hardware specific operations such as stopping the kernel tick.
+ *
+ * vTaskEndScheduler () will cause all of the resources allocated by the
+ * kernel to be freed - but will not free resources allocated by application
+ * tasks.
+ *
+ * Example usage:
+   
+ void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // At some point we want to end the real time kernel processing
+		 // so call ...
+		 vTaskEndScheduler ();
+	 }
+ }
+
+ void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will only get here when the vTaskCode () task has called
+	 // vTaskEndScheduler ().  When we get here we are back to single task
+	 // execution.
+ }
+   

+ *
+ * \defgroup vTaskEndScheduler vTaskEndScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskSuspendAll( void );

+ *
+ * Suspends the scheduler without disabling interrupts.  Context switches will
+ * not occur while the scheduler is suspended.
+ *
+ * After calling vTaskSuspendAll () the calling task will continue to execute
+ * without risk of being swapped out until a call to xTaskResumeAll () has been
+ * made.
+ *
+ * API functions that have the potential to cause a context switch (for example,
+ * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler
+ * is suspended.
+ *
+ * Example usage:
+   
+ void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the kernel
+		 // tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.
+		 xTaskResumeAll ();
+	 }
+ }
+   

+ * \defgroup vTaskSuspendAll vTaskSuspendAll
+ * \ingroup SchedulerControl
+ */
+void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskResumeAll( void );

+ *
+ * Resumes scheduler activity after it was suspended by a call to
+ * vTaskSuspendAll().
+ *
+ * xTaskResumeAll() only resumes the scheduler.  It does not unsuspend tasks
+ * that were previously suspended by a call to vTaskSuspend().
+ *
+ * @return If resuming the scheduler caused a context switch then pdTRUE is
+ *		  returned, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+   
+ void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the real
+		 // time kernel tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.  We want to force
+		 // a context switch - but there is no point if resuming the scheduler
+		 // caused a context switch already.
+		 if( !xTaskResumeAll () )
+		 {
+			  taskYIELD ();
+		 }
+	 }
+ }
+   

+ * \defgroup xTaskResumeAll xTaskResumeAll
+ * \ingroup SchedulerControl
+ */
+BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK UTILITIES
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
TickType_t xTaskGetTickCount( void );

+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * \defgroup xTaskGetTickCount xTaskGetTickCount
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
TickType_t xTaskGetTickCountFromISR( void );

+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * This is a version of xTaskGetTickCount() that is safe to be called from an
+ * ISR - provided that TickType_t is the natural word size of the
+ * microcontroller being used or interrupt nesting is either not supported or
+ * not being used.
+ *
+ * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
uint16_t uxTaskGetNumberOfTasks( void );

+ *
+ * @return The number of tasks that the real time kernel is currently managing.
+ * This includes all ready, blocked and suspended tasks.  A task that
+ * has been deleted but not yet freed by the idle task will also be
+ * included in the count.
+ *
+ * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks
+ * \ingroup TaskUtils
+ */
+UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
char *pcTaskGetName( TaskHandle_t xTaskToQuery );

+ *
+ * @return The text (human readable) name of the task referenced by the handle
+ * xTaskToQuery.  A task can query its own name by either passing in its own
+ * handle, or by setting xTaskToQuery to NULL.
+ *
+ * \defgroup pcTaskGetName pcTaskGetName
+ * \ingroup TaskUtils
+ */
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * 
TaskHandle_t xTaskGetHandle( const char *pcNameToQuery );

+ *
+ * NOTE:  This function takes a relatively long time to complete and should be
+ * used sparingly.
+ *
+ * @return The handle of the task that has the human readable name pcNameToQuery.
+ * NULL is returned if no matching name is found.  INCLUDE_xTaskGetHandle
+ * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available.
+ *
+ * \defgroup pcTaskGetHandle pcTaskGetHandle
+ * \ingroup TaskUtils
+ */
+TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task.h
+ * 
UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );

+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * 
configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );

+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/* When using trace macros it is sometimes necessary to include task.h before
+FreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,
+so the following two prototypes will cause a compilation error.  This can be
+fixed by simply guarding against the inclusion of these two prototypes unless
+they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration
+constant. */
+#ifdef configUSE_APPLICATION_TASK_TAG
+	#if configUSE_APPLICATION_TASK_TAG == 1
+		/**
+		 * task.h
+		 * 
void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );

+		 *
+		 * Sets pxHookFunction to be the task hook function used by the task xTask.
+		 * Passing xTask as NULL has the effect of setting the calling tasks hook
+		 * function.
+		 */
+		void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;
+
+		/**
+		 * task.h
+		 * 
void xTaskGetApplicationTaskTag( TaskHandle_t xTask );

+		 *
+		 * Returns the pxHookFunction value assigned to the task xTask.  Do not
+		 * call from an interrupt service routine - call
+		 * xTaskGetApplicationTaskTagFromISR() instead.
+		 */
+		TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+		/**
+		 * task.h
+		 * 
void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );

+		 *
+		 * Returns the pxHookFunction value assigned to the task xTask.  Can
+		 * be called from an interrupt service routine.
+		 */
+		TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+	#endif /* configUSE_APPLICATION_TASK_TAG ==1 */
+#endif /* ifdef configUSE_APPLICATION_TASK_TAG */
+
+#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+
+	/* Each task contains an array of pointers that is dimensioned by the
+	configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.  The
+	kernel does not use the pointers itself, so the application writer can use
+	the pointers for any purpose they wish.  The following two functions are
+	used to set and query a pointer respectively. */
+	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) PRIVILEGED_FUNCTION;
+	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/**
+ * task.h
+ * 
BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );

+ *
+ * Calls the hook function associated with xTask.  Passing xTask as NULL has
+ * the effect of calling the Running tasks (the calling task) hook function.
+ *
+ * pvParameter is passed to the hook function for the task to interpret as it
+ * wants.  The return value is the value returned by the task hook function
+ * registered by the user.
+ */
+BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) PRIVILEGED_FUNCTION;
+
+/**
+ * xTaskGetIdleTaskHandle() is only available if
+ * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.
+ *
+ * Simply returns the handle of the idle task.  It is not valid to call
+ * xTaskGetIdleTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
+ * uxTaskGetSystemState() to be available.
+ *
+ * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in
+ * the system.  TaskStatus_t structures contain, among other things, members
+ * for the task handle, task name, task priority, task state, and total amount
+ * of run time consumed by the task.  See the TaskStatus_t structure
+ * definition in this file for the full member list.
+ *
+ * NOTE:  This function is intended for debugging use only as its use results in
+ * the scheduler remaining suspended for an extended period.
+ *
+ * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.
+ * The array must contain at least one TaskStatus_t structure for each task
+ * that is under the control of the RTOS.  The number of tasks under the control
+ * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.
+ *
+ * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray
+ * parameter.  The size is specified as the number of indexes in the array, or
+ * the number of TaskStatus_t structures contained in the array, not by the
+ * number of bytes in the array.
+ *
+ * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in
+ * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the
+ * total run time (as defined by the run time stats clock, see
+ * http://www.freertos.org/rtos-run-time-stats.html) since the target booted.
+ * pulTotalRunTime can be set to NULL to omit the total run time information.
+ *
+ * @return The number of TaskStatus_t structures that were populated by
+ * uxTaskGetSystemState().  This should equal the number returned by the
+ * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed
+ * in the uxArraySize parameter was too small.
+ *
+ * Example usage:
+   
+    // This example demonstrates how a human readable table of run time stats
+	// information is generated from raw data provided by uxTaskGetSystemState().
+	// The human readable table is written to pcWriteBuffer
+	void vTaskGetRunTimeStats( char *pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	volatile UBaseType_t uxArraySize, x;
+	uint32_t ulTotalRunTime, ulStatsAsPercentage;
+
+		// Make sure the write buffer does not contain a string.
+		*pcWriteBuffer = 0x00;
+
+		// Take a snapshot of the number of tasks in case it changes while this
+		// function is executing.
+		uxArraySize = uxTaskGetNumberOfTasks();
+
+		// Allocate a TaskStatus_t structure for each task.  An array could be
+		// allocated statically at compile time.
+		pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );
+
+		if( pxTaskStatusArray != NULL )
+		{
+			// Generate raw status information about each task.
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
+
+			// For percentage calculations.
+			ulTotalRunTime /= 100UL;
+
+			// Avoid divide by zero errors.
+			if( ulTotalRunTime > 0 )
+			{
+				// For each populated position in the pxTaskStatusArray array,
+				// format the raw data as human readable ASCII data
+				for( x = 0; x < uxArraySize; x++ )
+				{
+					// What percentage of the total run time has the task used?
+					// This will always be rounded down to the nearest integer.
+					// ulTotalRunTimeDiv100 has already been divided by 100.
+					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
+
+					if( ulStatsAsPercentage > 0UL )
+					{
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+					}
+					else
+					{
+						// If the percentage is zero here then the task has
+						// consumed less than 1% of the total run time.
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
+					}
+
+					pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );
+				}
+			}
+
+			// The array is no longer needed, free the memory it consumes.
+			vPortFree( pxTaskStatusArray );
+		}
+	}
+	

+ */
+UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskList( char *pcWriteBuffer );

+ *
+ * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
+ * both be defined as 1 for this function to be available.  See the
+ * configuration section of the FreeRTOS.org website for more information.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Lists all the current tasks, along with their current state and stack
+ * usage high water mark.
+ *
+ * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
+ * suspended ('S').
+ *
+ * PLEASE NOTE:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays task
+ * names, states and stack usage.
+ *
+ * vTaskList() has a dependency on the sprintf() C library function that might
+ * bloat the code size, use a lot of stack, and provide different results on
+ * different platforms.  An alternative, tiny, third party, and limited
+ * functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState()
+ * directly to get access to raw stats data, rather than indirectly through a
+ * call to vTaskList().
+ *
+ * @param pcWriteBuffer A buffer into which the above mentioned details
+ * will be written, in ASCII form.  This buffer is assumed to be large
+ * enough to contain the generated report.  Approximately 40 bytes per
+ * task should be sufficient.
+ *
+ * \defgroup vTaskList vTaskList
+ * \ingroup TaskUtils
+ */
+void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * 
void vTaskGetRunTimeStats( char *pcWriteBuffer );

+ *
+ * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+ * must both be defined as 1 for this function to be available.  The application
+ * must also then provide definitions for
+ * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+ * to configure a peripheral timer/counter and return the timers current count
+ * value respectively.  The counter should be at least 10 times the frequency of
+ * the tick count.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+ * accumulated execution time being stored for each task.  The resolution
+ * of the accumulated time value depends on the frequency of the timer
+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+ * Calling vTaskGetRunTimeStats() writes the total execution time of each
+ * task into a buffer, both as an absolute count value and as a percentage
+ * of the total system execution time.
+ *
+ * NOTE 2:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays the
+ * amount of time each task has spent in the Running state in both absolute and
+ * percentage terms.
+ *
+ * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function
+ * that might bloat the code size, use a lot of stack, and provide different
+ * results on different platforms.  An alternative, tiny, third party, and
+ * limited functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState() directly
+ * to get access to raw stats data, rather than indirectly through a call to
+ * vTaskGetRunTimeStats().
+ *
+ * @param pcWriteBuffer A buffer into which the execution times will be
+ * written, in ASCII form.  This buffer is assumed to be large enough to
+ * contain the generated report.  Approximately 40 bytes per task should
+ * be sufficient.
+ *
+ * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats
+ * \ingroup TaskUtils
+ */
+void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+* task. h
+* 
TickType_t xTaskGetIdleRunTimeCounter( void );

+*
+* configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+* must both be defined as 1 for this function to be available.  The application
+* must also then provide definitions for
+* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+* to configure a peripheral timer/counter and return the timers current count
+* value respectively.  The counter should be at least 10 times the frequency of
+* the tick count.
+*
+* Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+* accumulated execution time being stored for each task.  The resolution
+* of the accumulated time value depends on the frequency of the timer
+* configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+* While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total
+* execution time of each task into a buffer, xTaskGetIdleRunTimeCounter()
+* returns the total execution time of just the idle task.
+*
+* @return The total run time of the idle task.  This is the amount of time the
+* idle task has actually been executing.  The unit of time is dependent on the
+* frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
+* portGET_RUN_TIME_COUNTER_VALUE() macros.
+*
+* \defgroup xTaskGetIdleRunTimeCounter xTaskGetIdleRunTimeCounter
+* \ingroup TaskUtils
+*/
+TickType_t xTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ *  pulPreviousNotificationValue -
+ *  Can be used to pass out the subject task's notification value before any
+ *  bits are modified by the notify function.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) PRIVILEGED_FUNCTION;
+#define xTaskNotify( xTaskToNotify, ulValue, eAction ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL )
+#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotify() that can be used from an interrupt service routine
+ * (ISR).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ * @param pxHigherPriorityTaskWoken  xTaskNotifyFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should
+ * be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )
+#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value
+ * will be cleared in the calling task's notification value before the task
+ * checks to see if any notifications are pending, and optionally blocks if no
+ * notifications are pending.  Setting ulBitsToClearOnEntry to ULONG_MAX (if
+ * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have
+ * the effect of resetting the task's notification value to 0.  Setting
+ * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.
+ *
+ * @param ulBitsToClearOnExit If a notification is pending or received before
+ * the calling task exits the xTaskNotifyWait() function then the task's
+ * notification value (see the xTaskNotify() API function) is passed out using
+ * the pulNotificationValue parameter.  Then any bits that are set in
+ * ulBitsToClearOnExit will be cleared in the task's notification value (note
+ * *pulNotificationValue is set before any bits are cleared).  Setting
+ * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL
+ * (if limits.h is not included) will have the effect of resetting the task's
+ * notification value to 0 before the function exits.  Setting
+ * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged
+ * when the function exits (in which case the value passed out in
+ * pulNotificationValue will match the task's notification value).
+ *
+ * @param pulNotificationValue Used to pass the task's notification value out
+ * of the function.  Note the value passed out will not be effected by the
+ * clearing of any bits caused by ulBitsToClearOnExit being non-zero.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for a notification to be received, should a notification
+ * not already be pending when xTaskNotifyWait() was called.  The task
+ * will not consume any processing time while it is in the Blocked state.  This
+ * is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be
+ * used to convert a time specified in milliseconds to a time specified in
+ * ticks.
+ *
+ * @return If a notification was received (including notifications that were
+ * already pending when xTaskNotifyWait was called) then pdPASS is
+ * returned.  Otherwise pdFAIL is returned.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * xTaskNotifyGive() is a helper macro intended for use when task notifications
+ * are used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given using the xSemaphoreGive() API function,
+ * the equivalent action that instead uses a task notification is
+ * xTaskNotifyGive().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the
+ * eAction parameter set to eIncrement - so pdPASS is always returned.
+ *
+ * \defgroup xTaskNotifyGive xTaskNotifyGive
+ * \ingroup TaskNotifications
+ */
+#define xTaskNotifyGive( xTaskToNotify ) xTaskGenericNotify( ( xTaskToNotify ), ( 0 ), eIncrement, NULL )
+
+/**
+ * task. h
+ * 
void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotifyGive() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * vTaskNotifyGiveFromISR() is intended for use when task notifications are
+ * used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given from an ISR using the
+ * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses
+ * a task notification is vTaskNotifyGiveFromISR().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param pxHigherPriorityTaskWoken  vTaskNotifyGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch
+ * should be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * ulTaskNotifyTake() is intended for use when a task notification is used as a
+ * faster and lighter weight binary or counting semaphore alternative.  Actual
+ * FreeRTOS semaphores are taken using the xSemaphoreTake() API function, the
+ * equivalent action that instead uses a task notification is
+ * ulTaskNotifyTake().
+ *
+ * When a task is using its notification value as a binary or counting semaphore
+ * other tasks should send notifications to it using the xTaskNotifyGive()
+ * macro, or xTaskNotify() function with the eAction parameter set to
+ * eIncrement.
+ *
+ * ulTaskNotifyTake() can either clear the task's notification value to
+ * zero on exit, in which case the notification value acts like a binary
+ * semaphore, or decrement the task's notification value on exit, in which case
+ * the notification value acts like a counting semaphore.
+ *
+ * A task can use ulTaskNotifyTake() to [optionally] block to wait for a
+ * the task's notification value to be non-zero.  The task does not consume any
+ * CPU time while it is in the Blocked state.
+ *
+ * Where as xTaskNotifyWait() will return when a notification is pending,
+ * ulTaskNotifyTake() will return when the task's notification value is
+ * not zero.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's
+ * notification value is decremented when the function exits.  In this way the
+ * notification value acts like a counting semaphore.  If xClearCountOnExit is
+ * not pdFALSE then the task's notification value is cleared to zero when the
+ * function exits.  In this way the notification value acts like a binary
+ * semaphore.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for the task's notification value to be greater than zero,
+ * should the count not already be greater than zero when
+ * ulTaskNotifyTake() was called.  The task will not consume any processing
+ * time while it is in the Blocked state.  This is specified in kernel ticks,
+ * the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time
+ * specified in milliseconds to a time specified in ticks.
+ *
+ * @return The task's notification count before it is either cleared to zero or
+ * decremented (see the xClearCountOnExit parameter).
+ *
+ * \defgroup ulTaskNotifyTake ulTaskNotifyTake
+ * \ingroup TaskNotifications
+ */
+uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );

+ *
+ * If the notification state of the task referenced by the handle xTask is
+ * eNotified, then set the task's notification state to eNotWaitingNotification.
+ * The task's notification value is not altered.  Set xTask to NULL to clear the
+ * notification state of the calling task.
+ *
+ * @return pdTRUE if the task's notification state was set to
+ * eNotWaitingNotification, otherwise pdFALSE.
+ * \defgroup xTaskNotifyStateClear xTaskNotifyStateClear
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );
+
+/*-----------------------------------------------------------
+ * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
+ *----------------------------------------------------------*/
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Called from the real time kernel tick (either preemptive or cooperative),
+ * this increments the tick count and checks if any tasks that are blocked
+ * for a finite period required removing from a blocked list and placing on
+ * a ready list.  If a non-zero value is returned then a context switch is
+ * required because either:
+ *   + A task was removed from a blocked list because its timeout had expired,
+ *     or
+ *   + Time slicing is in use and there is a task of equal priority to the
+ *     currently running task.
+ */
+BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes the calling task from the ready list and places it both
+ * on the list of tasks waiting for a particular event, and the
+ * list of delayed tasks.  The task will be removed from both lists
+ * and replaced on the ready list should either the event occur (and
+ * there be no higher priority tasks waiting on the same event) or
+ * the delay period expires.
+ *
+ * The 'unordered' version replaces the event list item value with the
+ * xItemValue value, and inserts the list item at the end of the list.
+ *
+ * The 'ordered' version uses the existing event list item value (which is the
+ * owning tasks priority) to insert the list item into the event list is task
+ * priority order.
+ *
+ * @param pxEventList The list containing tasks that are blocked waiting
+ * for the event to occur.
+ *
+ * @param xItemValue The item value to use for the event list item when the
+ * event list is not ordered by task priority.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait
+ * for the event to occur.  This is specified in kernel ticks,the constant
+ * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time
+ * period.
+ */
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * This function performs nearly the same function as vTaskPlaceOnEventList().
+ * The difference being that this function does not permit tasks to block
+ * indefinitely, whereas vTaskPlaceOnEventList() does.
+ *
+ */
+void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes a task from both the specified event list and the list of blocked
+ * tasks, and places it on a ready queue.
+ *
+ * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called
+ * if either an event occurs to unblock a task, or the block timeout period
+ * expires.
+ *
+ * xTaskRemoveFromEventList() is used when the event list is in task priority
+ * order.  It removes the list item from the head of the event list as that will
+ * have the highest priority owning task of all the tasks on the event list.
+ * vTaskRemoveFromUnorderedEventList() is used when the event list is not
+ * ordered and the event list items hold something other than the owning tasks
+ * priority.  In this case the event list item value is updated to the value
+ * passed in the xItemValue parameter.
+ *
+ * @return pdTRUE if the task being removed has a higher priority than the task
+ * making the call, otherwise pdFALSE.
+ */
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Sets the pointer to the current TCB to the TCB of the highest priority task
+ * that is ready to run.
+ */
+portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY
+ * THE EVENT BITS MODULE.
+ */
+TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the handle of the calling task.
+ */
+TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Capture the current time status for future reference.
+ */
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+/*
+ * Compare the time status now with that previously captured to see if the
+ * timeout has expired.
+ */
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * Shortcut used by the queue implementation to prevent unnecessary call to
+ * taskYIELD();
+ */
+void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns the scheduler state as taskSCHEDULER_RUNNING,
+ * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.
+ */
+BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Raises the priority of the mutex holder to that of the calling task should
+ * the mutex holder have a priority less than the calling task.
+ */
+BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the priority of a task back to its proper priority in the case that it
+ * inherited a higher priority while it was holding a semaphore.
+ */
+BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a higher priority task attempting to obtain a mutex caused a lower
+ * priority task to inherit the higher priority task's priority - but the higher
+ * priority task then timed out without obtaining the mutex, then the lower
+ * priority task will disinherit the priority again - but only down as far as
+ * the highest priority task that is still waiting for the mutex (if there were
+ * more than one task waiting for the mutex).
+ */
+void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.
+ */
+UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the uxTaskNumber of the task referenced by the xTask parameter to
+ * uxHandle.
+ */
+void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * If tickless mode is being used, or a low power mode is implemented, then
+ * the tick interrupt will not execute during idle periods.  When this is the
+ * case, the tick count value maintained by the scheduler needs to be kept up
+ * to date with the actual execution time by being skipped forward by a time
+ * equal to the idle period.
+ */
+void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
+ * specific sleep function to determine if it is ok to proceed with the sleep,
+ * and if it is ok to proceed, if it is ok to sleep indefinitely.
+ *
+ * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only
+ * called with the scheduler suspended, not from within a critical section.  It
+ * is therefore possible for an interrupt to request a context switch between
+ * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being
+ * entered.  eTaskConfirmSleepModeStatus() should be called from a short
+ * critical section between the timer being stopped and the sleep mode being
+ * entered to ensure it is ok to proceed into the sleep mode.
+ */
+eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Increment the mutex held count when a mutex is
+ * taken and return the handle of the task that has taken the mutex.
+ */
+TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Same as vTaskSetTimeOutState(), but without a critial
+ * section.
+ */
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* INC_TASK_H */
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/include/timers.h b/FreeRTOSv10.2.1/FreeRTOS/Source/include/timers.h
new file mode 100644
index 0000000..5abb7f1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/include/timers.h
@@ -0,0 +1,1295 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef TIMERS_H
+#define TIMERS_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include timers.h"
+#endif
+
+/*lint -save -e537 This headers are only multiply included if the application code
+happens to also be including task.h. */
+#include "task.h"
+/*lint -restore */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+/* IDs for commands that can be sent/received on the timer queue.  These are to
+be used solely through the macros that make up the public software timer API,
+as defined below.  The commands that are sent from interrupts must use the
+highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task
+or interrupt version of the queue send function should be used. */
+#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR 	( ( BaseType_t ) -2 )
+#define tmrCOMMAND_EXECUTE_CALLBACK				( ( BaseType_t ) -1 )
+#define tmrCOMMAND_START_DONT_TRACE				( ( BaseType_t ) 0 )
+#define tmrCOMMAND_START					    ( ( BaseType_t ) 1 )
+#define tmrCOMMAND_RESET						( ( BaseType_t ) 2 )
+#define tmrCOMMAND_STOP							( ( BaseType_t ) 3 )
+#define tmrCOMMAND_CHANGE_PERIOD				( ( BaseType_t ) 4 )
+#define tmrCOMMAND_DELETE						( ( BaseType_t ) 5 )
+
+#define tmrFIRST_FROM_ISR_COMMAND				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_START_FROM_ISR				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_RESET_FROM_ISR				( ( BaseType_t ) 7 )
+#define tmrCOMMAND_STOP_FROM_ISR				( ( BaseType_t ) 8 )
+#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR		( ( BaseType_t ) 9 )
+
+
+/**
+ * Type by which software timers are referenced.  For example, a call to
+ * xTimerCreate() returns an TimerHandle_t variable that can then be used to
+ * reference the subject timer in calls to other software timer API functions
+ * (for example, xTimerStart(), xTimerReset(), etc.).
+ */
+struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tmrTimerControl * TimerHandle_t;
+
+/*
+ * Defines the prototype to which timer callback functions must conform.
+ */
+typedef void (*TimerCallbackFunction_t)( TimerHandle_t xTimer );
+
+/*
+ * Defines the prototype to which functions used with the
+ * xTimerPendFunctionCallFromISR() function must conform.
+ */
+typedef void (*PendedFunction_t)( void *, uint32_t );
+
+/**
+ * TimerHandle_t xTimerCreate( 	const char * const pcTimerName,
+ * 								TickType_t xTimerPeriodInTicks,
+ * 								UBaseType_t uxAutoReload,
+ * 								void * pvTimerID,
+ * 								TimerCallbackFunction_t pxCallbackFunction );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is	"void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @return If the timer is successfully created then a handle to the newly
+ * created timer is returned.  If the timer cannot be created (because either
+ * there is insufficient FreeRTOS heap remaining to allocate the timer
+ * structures, or the timer period was set to 0) then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ * #define NUM_TIMERS 5
+ *
+ * // An array to hold handles to the created timers.
+ * TimerHandle_t xTimers[ NUM_TIMERS ];
+ *
+ * // An array to hold a count of the number of times each timer expires.
+ * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };
+ *
+ * // Define a callback function that will be used by multiple timer instances.
+ * // The callback function does nothing but count the number of times the
+ * // associated timer expires, and stop the timer once the timer has expired
+ * // 10 times.
+ * void vTimerCallback( TimerHandle_t pxTimer )
+ * {
+ * int32_t lArrayIndex;
+ * const int32_t xMaxExpiryCountBeforeStopping = 10;
+ *
+ * 	   // Optionally do something if the pxTimer parameter is NULL.
+ * 	   configASSERT( pxTimer );
+ *
+ *     // Which timer expired?
+ *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );
+ *
+ *     // Increment the number of times that pxTimer has expired.
+ *     lExpireCounters[ lArrayIndex ] += 1;
+ *
+ *     // If the timer has expired 10 times then stop it from running.
+ *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )
+ *     {
+ *         // Do not use a block time if calling a timer API function from a
+ *         // timer callback function, as doing so could cause a deadlock!
+ *         xTimerStop( pxTimer, 0 );
+ *     }
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start some timers.  Starting the timers before the scheduler
+ *     // has been started means the timers will start running immediately that
+ *     // the scheduler starts.
+ *     for( x = 0; x < NUM_TIMERS; x++ )
+ *     {
+ *         xTimers[ x ] = xTimerCreate(    "Timer",       // Just a text name, not used by the kernel.
+ *                                         ( 100 * x ),   // The timer period in ticks.
+ *                                         pdTRUE,        // The timers will auto-reload themselves when they expire.
+ *                                         ( void * ) x,  // Assign each timer a unique id equal to its array index.
+ *                                         vTimerCallback // Each timer calls the same callback when it expires.
+ *                                     );
+ *
+ *         if( xTimers[ x ] == NULL )
+ *         {
+ *             // The timer was not created.
+ *         }
+ *         else
+ *         {
+ *             // Start the timer.  No block time is specified, and even if one was
+ *             // it would be ignored because the scheduler has not yet been
+ *             // started.
+ *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )
+ *             {
+ *                 // The timer could not be set into the Active state.
+ *             }
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+								const TickType_t xTimerPeriodInTicks,
+								const UBaseType_t uxAutoReload,
+								void * const pvTimerID,
+								TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName,
+ * 									TickType_t xTimerPeriodInTicks,
+ * 									UBaseType_t uxAutoReload,
+ * 									void * pvTimerID,
+ * 									TimerCallbackFunction_t pxCallbackFunction,
+ *									StaticTimer_t *pxTimerBuffer );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is "void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which
+ * will be then be used to hold the software timer's data structures, removing
+ * the need for the memory to be allocated dynamically.
+ *
+ * @return If the timer is created then a handle to the created timer is
+ * returned.  If pxTimerBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ * // The buffer used to hold the software timer's data structure.
+ * static StaticTimer_t xTimerBuffer;
+ *
+ * // A variable that will be incremented by the software timer's callback
+ * // function.
+ * UBaseType_t uxVariableToIncrement = 0;
+ *
+ * // A software timer callback function that increments a variable passed to
+ * // it when the software timer was created.  After the 5th increment the
+ * // callback function stops the software timer.
+ * static void prvTimerCallback( TimerHandle_t xExpiredTimer )
+ * {
+ * UBaseType_t *puxVariableToIncrement;
+ * BaseType_t xReturned;
+ *
+ *     // Obtain the address of the variable to increment from the timer ID.
+ *     puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );
+ *
+ *     // Increment the variable to show the timer callback has executed.
+ *     ( *puxVariableToIncrement )++;
+ *
+ *     // If this callback has executed the required number of times, stop the
+ *     // timer.
+ *     if( *puxVariableToIncrement == 5 )
+ *     {
+ *         // This is called from a timer callback so must not block.
+ *         xTimerStop( xExpiredTimer, staticDONT_BLOCK );
+ *     }
+ * }
+ *
+ *
+ * void main( void )
+ * {
+ *     // Create the software time.  xTimerCreateStatic() has an extra parameter
+ *     // than the normal xTimerCreate() API function.  The parameter is a pointer
+ *     // to the StaticTimer_t structure that will hold the software timer
+ *     // structure.  If the parameter is passed as NULL then the structure will be
+ *     // allocated dynamically, just as if xTimerCreate() had been called.
+ *     xTimer = xTimerCreateStatic( "T1",             // Text name for the task.  Helps debugging only.  Not used by FreeRTOS.
+ *                                  xTimerPeriod,     // The period of the timer in ticks.
+ *                                  pdTRUE,           // This is an auto-reload timer.
+ *                                  ( void * ) &uxVariableToIncrement,    // A variable incremented by the software timer's callback function
+ *                                  prvTimerCallback, // The function to execute when the timer expires.
+ *                                  &xTimerBuffer );  // The buffer that will hold the software timer structure.
+ *
+ *     // The scheduler has not started yet so a block time is not used.
+ *     xReturned = xTimerStart( xTimer, 0 );
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+										const TickType_t xTimerPeriodInTicks,
+										const UBaseType_t uxAutoReload,
+										void * const pvTimerID,
+										TimerCallbackFunction_t pxCallbackFunction,
+										StaticTimer_t *pxTimerBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * void *pvTimerGetTimerID( TimerHandle_t xTimer );
+ *
+ * Returns the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer, and by calling the
+ * vTimerSetTimerID() API function.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return The ID assigned to the timer being queried.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void *pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
+ *
+ * Sets the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being updated.
+ *
+ * @param pvNewID The ID to assign to the timer.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );
+ *
+ * Queries a timer to see if it is active or dormant.
+ *
+ * A timer will be dormant if:
+ *     1) It has been created but not started, or
+ *     2) It is an expired one-shot timer that has not been restarted.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the
+ * active state.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return pdFALSE will be returned if the timer is dormant.  A value other than
+ * pdFALSE will be returned if the timer is active.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is active, do something.
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, do something else.
+ *     }
+ * }
+ * @endverbatim
+ */
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
+ *
+ * Simply returns the handle of the timer service/daemon task.  It it not valid
+ * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStart() starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerStart() has equivalent functionality
+ * to the xTimerReset() API function.
+ *
+ * Starting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerStart() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerStart() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerStart() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the start command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStart( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStop() stops a timer that was previously started using either of the
+ * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),
+ * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.
+ *
+ * Stopping a timer ensures the timer is not in the active state.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the stop command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStop( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerChangePeriod( 	TimerHandle_t xTimer,
+ *										TickType_t xNewPeriod,
+ *										TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerChangePeriod() changes the period of a timer that was previously
+ * created using the xTimerCreate() API function.
+ *
+ * xTimerChangePeriod() can be called to change the period of an active or
+ * dormant state timer.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerChangePeriod() to be available.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the change period command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if
+ * xTimerChangePeriod() is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the change period command could not be
+ * sent to the timer command queue even after xTicksToWait ticks had passed.
+ * pdPASS will be returned if the command was successfully sent to the timer
+ * command queue.  When the command is actually processed will depend on the
+ * priority of the timer service/daemon task relative to other tasks in the
+ * system.  The timer service/daemon task priority is set by the
+ * configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.  If the timer
+ * // referenced by xTimer is already active when it is called, then the timer
+ * // is deleted.  If the timer referenced by xTimer is not active when it is
+ * // called, then the period of the timer is set to 500ms and the timer is
+ * // started.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is already active - delete it.
+ *         xTimerDelete( xTimer );
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, change its period to 500ms.  This will also
+ *         // cause the timer to start.  Block for a maximum of 100 ticks if the
+ *         // change period command cannot immediately be sent to the timer
+ *         // command queue.
+ *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )
+ *         {
+ *             // The command was successfully sent.
+ *         }
+ *         else
+ *         {
+ *             // The command could not be sent, even after waiting for 100 ticks
+ *             // to pass.  Take appropriate action here.
+ *         }
+ *     }
+ * }
+ * @endverbatim
+ */
+ #define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerDelete() deletes a timer that was previously created using the
+ * xTimerCreate() API function.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerDelete() to be available.
+ *
+ * @param xTimer The handle of the timer being deleted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the delete command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()
+ * is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the delete command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerChangePeriod() API function example usage scenario.
+ */
+#define xTimerDelete( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerReset() re-starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerReset() will cause the timer to
+ * re-evaluate its expiry time so that it is relative to when xTimerReset() was
+ * called.  If the timer was in the dormant state then xTimerReset() has
+ * equivalent functionality to the xTimerStart() API function.
+ *
+ * Resetting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerReset() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerReset() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerReset() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being reset/started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the reset command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer.
+ *
+ * TimerHandle_t xBacklightTimer = NULL;
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press event handler.
+ * void vKeyPressEventHandler( char cKey )
+ * {
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  Wait 10 ticks for the command to be successfully sent
+ *     // if it cannot be sent immediately.
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start the one-shot timer that is responsible for turning
+ *     // the back-light off if no keys are pressed within a 5 second period.
+ *     xBacklightTimer = xTimerCreate( "BacklightTimer",           // Just a text name, not used by the kernel.
+ *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
+ *                                     pdFALSE,                    // The timer is a one-shot timer.
+ *                                     0,                          // The id is not used by the callback so can take any value.
+ *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.
+ *                                   );
+ *
+ *     if( xBacklightTimer == NULL )
+ *     {
+ *         // The timer was not created.
+ *     }
+ *     else
+ *     {
+ *         // Start the timer.  No block time is specified, and even if one was
+ *         // it would be ignored because the scheduler has not yet been
+ *         // started.
+ *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )
+ *         {
+ *             // The timer could not be set into the Active state.
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timer running as it has already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#define xTimerReset( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStartFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStart() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStartFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStartFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStartFromISR() function.  If
+ * xTimerStartFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerStartFromISR() is actually called.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then restart the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The start command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerStopFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStop() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStopFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStopFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStopFromISR() function.  If
+ * xTimerStopFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the timer should be simply stopped.
+ *
+ * // The interrupt service routine that stops the timer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - simply stop the timer.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The stop command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,
+ *										 TickType_t xNewPeriod,
+ *										 BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerChangePeriod() that can be called from an interrupt
+ * service routine.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the
+ * timer command queue, so has the potential to transition the timer service/
+ * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()
+ * causes the timer service/daemon task to leave the Blocked state, and the
+ * timer service/daemon task has a priority equal to or greater than the
+ * currently executing task (the task that was interrupted), then
+ * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the
+ * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets
+ * this value to pdTRUE then a context switch should be performed before the
+ * interrupt exits.
+ *
+ * @return pdFAIL will be returned if the command to change the timers period
+ * could not be sent to the timer command queue.  pdPASS will be returned if the
+ * command was successfully sent to the timer command queue.  When the command
+ * is actually processed will depend on the priority of the timer service/daemon
+ * task relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the period of xTimer should be changed to 500ms.
+ *
+ * // The interrupt service routine that changes the period of xTimer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - change the period of xTimer to 500ms.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The command to change the timers period was not executed
+ *         // successfully.  Take appropriate action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerResetFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerReset() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer that is to be started, reset, or
+ * restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerResetFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerResetFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerResetFromISR() function.  If
+ * xTimerResetFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon
+ * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+
+/**
+ * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
+ *                                          void *pvParameter1,
+ *                                          uint32_t ulParameter2,
+ *                                          BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ *
+ * Used from application interrupt service routines to defer the execution of a
+ * function to the RTOS daemon task (the timer service task, hence this function
+ * is implemented in timers.c and is prefixed with 'Timer').
+ *
+ * Ideally an interrupt service routine (ISR) is kept as short as possible, but
+ * sometimes an ISR either has a lot of processing to do, or needs to perform
+ * processing that is not deterministic.  In these cases
+ * xTimerPendFunctionCallFromISR() can be used to defer processing of a function
+ * to the RTOS daemon task.
+ *
+ * A mechanism is provided that allows the interrupt to return directly to the
+ * task that will subsequently execute the pended callback function.  This
+ * allows the callback function to execute contiguously in time with the
+ * interrupt - just as if the callback had executed in the interrupt itself.
+ *
+ * @param xFunctionToPend The function to execute from the timer service/
+ * daemon task.  The function must conform to the PendedFunction_t
+ * prototype.
+ *
+ * @param pvParameter1 The value of the callback function's first parameter.
+ * The parameter has a void * type to allow it to be used to pass any type.
+ * For example, unsigned longs can be cast to a void *, or the void * can be
+ * used to point to a structure.
+ *
+ * @param ulParameter2 The value of the callback function's second parameter.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task.  If the
+ * priority of the timer daemon task (which is set using
+ * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of
+ * the currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE within
+ * xTimerPendFunctionCallFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits.  For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
+ * example code below.
+ *
+ * @return pdPASS is returned if the message was successfully sent to the
+ * timer daemon task, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ *	// The callback function that will execute in the context of the daemon task.
+ *  // Note callback functions must all use this same prototype.
+ *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )
+ *	{
+ *		BaseType_t xInterfaceToService;
+ *
+ *		// The interface that requires servicing is passed in the second
+ *      // parameter.  The first parameter is not used in this case.
+ *		xInterfaceToService = ( BaseType_t ) ulParameter2;
+ *
+ *		// ...Perform the processing here...
+ *	}
+ *
+ *	// An ISR that receives data packets from multiple interfaces
+ *  void vAnISR( void )
+ *	{
+ *		BaseType_t xInterfaceToService, xHigherPriorityTaskWoken;
+ *
+ *		// Query the hardware to determine which interface needs processing.
+ *		xInterfaceToService = prvCheckInterfaces();
+ *
+ *      // The actual processing is to be deferred to a task.  Request the
+ *      // vProcessInterface() callback function is executed, passing in the
+ *		// number of the interface that needs processing.  The interface to
+ *		// service is passed in the second parameter.  The first parameter is
+ *		// not used in this case.
+ *		xHigherPriorityTaskWoken = pdFALSE;
+ *		xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );
+ *
+ *		// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ *		// switch should be requested.  The macro used is port specific and will
+ *		// be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to
+ *		// the documentation page for the port being used.
+ *		portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ *
+ *	}
+ * @endverbatim
+ */
+BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+ /**
+  * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+  *                                    void *pvParameter1,
+  *                                    uint32_t ulParameter2,
+  *                                    TickType_t xTicksToWait );
+  *
+  *
+  * Used to defer the execution of a function to the RTOS daemon task (the timer
+  * service task, hence this function is implemented in timers.c and is prefixed
+  * with 'Timer').
+  *
+  * @param xFunctionToPend The function to execute from the timer service/
+  * daemon task.  The function must conform to the PendedFunction_t
+  * prototype.
+  *
+  * @param pvParameter1 The value of the callback function's first parameter.
+  * The parameter has a void * type to allow it to be used to pass any type.
+  * For example, unsigned longs can be cast to a void *, or the void * can be
+  * used to point to a structure.
+  *
+  * @param ulParameter2 The value of the callback function's second parameter.
+  *
+  * @param xTicksToWait Calling this function will result in a message being
+  * sent to the timer daemon task on a queue.  xTicksToWait is the amount of
+  * time the calling task should remain in the Blocked state (so not using any
+  * processing time) for space to become available on the timer queue if the
+  * queue is found to be full.
+  *
+  * @return pdPASS is returned if the message was successfully sent to the
+  * timer daemon task, otherwise pdFALSE is returned.
+  *
+  */
+BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * const char * const pcTimerGetName( TimerHandle_t xTimer );
+ *
+ * Returns the name that was assigned to a timer when the timer was created.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The name assigned to the timer specified by the xTimer parameter.
+ */
+const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload );
+ *
+ * Updates a timer to be either an autoreload timer, in which case the timer
+ * automatically resets itself each time it expires, or a one shot timer, in
+ * which case the timer will only expire once unless it is manually restarted.
+ *
+ * @param xTimer The handle of the timer being updated.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the timer's period (see the
+ * xTimerPeriodInTicks parameter of the xTimerCreate() API function).  If
+ * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ */
+void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION;
+
+/**
+ * TickType_t xTimerGetPeriod( TimerHandle_t xTimer );
+ *
+ * Returns the period of a timer.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The period of the timer in ticks.
+ */
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+* TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer );
+*
+* Returns the time in ticks at which the timer will expire.  If this is less
+* than the current tick count then the expiry time has overflowed from the
+* current time.
+*
+* @param xTimer The handle of the timer being queried.
+*
+* @return If the timer is running then the time in ticks at which the timer
+* will next expire is returned.  If the timer is not running then the return
+* value is undefined.
+*/
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Functions beyond this part are not part of the public API and are intended
+ * for use by the kernel only.
+ */
+BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;
+	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* TIMERS_H */
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/list.c b/FreeRTOSv10.2.1/FreeRTOS/Source/list.c
new file mode 100644
index 0000000..9875b90
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/list.c
@@ -0,0 +1,198 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#include 
+#include "FreeRTOS.h"
+#include "list.h"
+
+/*-----------------------------------------------------------
+ * PUBLIC LIST API documented in list.h
+ *----------------------------------------------------------*/
+
+void vListInitialise( List_t * const pxList )
+{
+	/* The list structure contains a list item which is used to mark the
+	end of the list.  To initialise the list the list end is inserted
+	as the only list entry. */
+	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	/* The list end value is the highest possible value in the list to
+	ensure it remains at the end of the list. */
+	pxList->xListEnd.xItemValue = portMAX_DELAY;
+
+	/* The list end next and previous pointers point to itself so we know
+	when the list is empty. */
+	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
+
+	/* Write known values into the list if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
+	listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
+}
+/*-----------------------------------------------------------*/
+
+void vListInitialiseItem( ListItem_t * const pxItem )
+{
+	/* Make sure the list item is not recorded as being on a list. */
+	pxItem->pxContainer = NULL;
+
+	/* Write known values into the list item if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+	listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+}
+/*-----------------------------------------------------------*/
+
+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t * const pxIndex = pxList->pxIndex;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert a new list item into pxList, but rather than sort the list,
+	makes the new list item the last item to be removed by a call to
+	listGET_OWNER_OF_NEXT_ENTRY(). */
+	pxNewListItem->pxNext = pxIndex;
+	pxNewListItem->pxPrevious = pxIndex->pxPrevious;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	pxIndex->pxPrevious->pxNext = pxNewListItem;
+	pxIndex->pxPrevious = pxNewListItem;
+
+	/* Remember which list the item is in. */
+	pxNewListItem->pxContainer = pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t *pxIterator;
+const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert the new list item into the list, sorted in xItemValue order.
+
+	If the list already contains a list item with the same item value then the
+	new list item should be placed after it.  This ensures that TCBs which are
+	stored in ready lists (all of which have the same xItemValue value) get a
+	share of the CPU.  However, if the xItemValue is the same as the back marker
+	the iteration loop below will not end.  Therefore the value is checked
+	first, and the algorithm slightly modified if necessary. */
+	if( xValueOfInsertion == portMAX_DELAY )
+	{
+		pxIterator = pxList->xListEnd.pxPrevious;
+	}
+	else
+	{
+		/* *** NOTE ***********************************************************
+		If you find your application is crashing here then likely causes are
+		listed below.  In addition see https://www.freertos.org/FAQHelp.html for
+		more tips, and ensure configASSERT() is defined!
+		https://www.freertos.org/a00110.html#configASSERT
+
+			1) Stack overflow -
+			   see https://www.freertos.org/Stacks-and-stack-overflow-checking.html
+			2) Incorrect interrupt priority assignment, especially on Cortex-M
+			   parts where numerically high priority values denote low actual
+			   interrupt priorities, which can seem counter intuitive.  See
+			   https://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition
+			   of configMAX_SYSCALL_INTERRUPT_PRIORITY on
+			   https://www.freertos.org/a00110.html
+			3) Calling an API function from within a critical section or when
+			   the scheduler is suspended, or calling an API function that does
+			   not end in "FromISR" from an interrupt.
+			4) Using a queue or semaphore before it has been initialised or
+			   before the scheduler has been started (are interrupts firing
+			   before vTaskStartScheduler() has been called?).
+		**********************************************************************/
+
+		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
+		{
+			/* There is nothing to do here, just iterating to the wanted
+			insertion position. */
+		}
+	}
+
+	pxNewListItem->pxNext = pxIterator->pxNext;
+	pxNewListItem->pxNext->pxPrevious = pxNewListItem;
+	pxNewListItem->pxPrevious = pxIterator;
+	pxIterator->pxNext = pxNewListItem;
+
+	/* Remember which list the item is in.  This allows fast removal of the
+	item later. */
+	pxNewListItem->pxContainer = pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
+{
+/* The list item knows which list it is in.  Obtain the list from the list
+item. */
+List_t * const pxList = pxItemToRemove->pxContainer;
+
+	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
+	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	/* Make sure the index is left pointing to a valid item. */
+	if( pxList->pxIndex == pxItemToRemove )
+	{
+		pxList->pxIndex = pxItemToRemove->pxPrevious;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxItemToRemove->pxContainer = NULL;
+	( pxList->uxNumberOfItems )--;
+
+	return pxList->uxNumberOfItems;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/ReadMe.txt b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/ReadMe.txt
new file mode 100644
index 0000000..0bb046a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/ReadMe.txt
@@ -0,0 +1,10 @@
+This directory tree contains the master copy of the FreeeRTOS Cortex-M33 port.
+Do not use the files located here!  These file are copied into separate
+FreeRTOS/Source/portable/[compiler]/ARM_CM33_NNN directories prior to each
+FreeRTOS release.
+
+If your Cortex-M33 application uses TrustZone then use the files from the
+FreeRTOS/Source/portable/[compiler]/ARM_CM33 directories.
+
+If your Cortex-M33 application does not use TrustZone then use the files from
+the FreeRTOS/Source/portable/[compiler]/ARM_CM33_NTZ directories.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/copy_files.py b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/copy_files.py
new file mode 100644
index 0000000..e99c1b1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/copy_files.py
@@ -0,0 +1,103 @@
+#/*
+# * FreeRTOS Kernel V10.2.1
+# * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+# *
+# * Permission is hereby granted, free of charge, to any person obtaining a copy of
+# * this software and associated documentation files (the "Software"), to deal in
+# * the Software without restriction, including without limitation the rights to
+# * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+# * the Software, and to permit persons to whom the Software is furnished to do so,
+# * subject to the following conditions:
+# *
+# * The above copyright notice and this permission notice shall be included in all
+# * copies or substantial portions of the Software.
+# *
+# * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+# * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+# * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+# * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+# * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+# *
+# * http://www.FreeRTOS.org
+# * http://aws.amazon.com/freertos
+# *
+# * 1 tab == 4 spaces!
+# */
+
+import os
+import shutil
+
+_THIS_FILE_DIRECTORY_ = os.path.dirname(os.path.realpath(__file__))
+_FREERTOS_PORTABLE_DIRECTORY_ = os.path.dirname(_THIS_FILE_DIRECTORY_)
+
+_COMPILERS_ = ['GCC', 'IAR']
+_ARCH_NS_ = ['ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ']
+_ARCH_S_ = ['ARM_CM33', 'ARM_CM23']
+
+_SUPPORTED_CONFIGS_ =   {
+                            'GCC' : ['ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ'],
+                            'IAR' : ['ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ']
+                        }
+
+# Files to be complied in the Secure Project
+_SECURE_FILE_PATHS_ = [
+    os.path.join('secure', 'context'),
+    os.path.join('secure', 'context', 'portable', '_COMPILER_ARCH_'),
+    os.path.join('secure', 'heap'),
+    os.path.join('secure', 'init'),
+    os.path.join('secure', 'macros')
+]
+
+# Files to be complied in the Non-Secure Project
+_NONSECURE_FILE_PATHS_ = [
+    'non_secure',
+    os.path.join('non_secure', 'portable', '_COMPILER_ARCH_')
+]
+
+
+def is_supported_config(compiler, arch):
+    return arch in _SUPPORTED_CONFIGS_[compiler]
+
+
+def copy_files_in_dir(src_abs_path, dst_abs_path):
+    for src_file in os.listdir(src_abs_path):
+        src_file_abs_path = os.path.join(src_abs_path, src_file)
+        if os.path.isfile(src_file_abs_path) and src_file != 'ReadMe.txt':
+            if not os.path.exists(dst_abs_path):
+                os.makedirs(dst_abs_path)
+            print('Copying {}...'.format(os.path.basename(src_file_abs_path)))
+            shutil.copy2(src_file_abs_path, dst_abs_path)
+
+
+def copy_files_for_compiler_and_arch(compiler, arch, src_paths, dst_path):
+    _COMPILER_ARCH_ = os.path.join(compiler, arch)
+    for src_path in src_paths:
+        src_path_sanitized = src_path.replace('_COMPILER_ARCH_', _COMPILER_ARCH_ )
+
+        src_abs_path = os.path.join(_THIS_FILE_DIRECTORY_, src_path_sanitized)
+        dst_abs_path = os.path.join(_FREERTOS_PORTABLE_DIRECTORY_, _COMPILER_ARCH_, dst_path)
+
+        copy_files_in_dir(src_abs_path, dst_abs_path)
+
+
+def copy_files():
+    # Copy Secure Files
+    for compiler in _COMPILERS_:
+        for arch in _ARCH_S_:
+            if is_supported_config(compiler, arch):
+                copy_files_for_compiler_and_arch(compiler, arch, _SECURE_FILE_PATHS_, 'secure')
+
+    # Copy Non-Secure Files
+    for compiler in _COMPILERS_:
+        for arch in _ARCH_NS_:
+            if is_supported_config(compiler, arch):
+                copy_files_for_compiler_and_arch(compiler, arch, _NONSECURE_FILE_PATHS_, 'non_secure')
+
+
+def main():
+    copy_files()
+
+
+if __name__ == '__main__':
+    main()
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/ReadMe.txt b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/ReadMe.txt
new file mode 100644
index 0000000..994d937
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/ReadMe.txt
@@ -0,0 +1,11 @@
+This directory tree contains the master copy of the FreeeRTOS Cortex-M33 port.
+Do not use the files located here!  These file are copied into separate
+FreeRTOS/Source/portable/[compiler]/ARM_CM33_NNN directories prior to each
+FreeRTOS release.
+
+If your Cortex-M33 application uses TrustZone then use the files from the
+FreeRTOS/Source/portable/[compiler]/ARM_CM33 directories.
+
+If your Cortex-M33 application does not use TrustZone then use the files from
+the FreeRTOS/Source/portable/[compiler]/ARM_CM33_NTZ directories.
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/port.c
new file mode 100644
index 0000000..b0394fb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/* Secure components includes. */
+	#include "secure_context.h"
+	#include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK				( 0x00000004 )
+#define portNVIC_SYSTICK_INT				( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
+#define portNVIC_PENDSVSET					( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY			( 255UL )
+#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE				( 3UL )
+#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS					( 20UL )
+#define portCPACR_CP11_POS					( 22UL )
+
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS					( 31UL )
+#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS					( 30UL )
+#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS				( 0UL )
+#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS				( 8UL )
+#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS				( 16UL )
+#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS				( 24UL )
+#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS				( 0UL )
+#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS				( 8UL )
+#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS				( 16UL )
+#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS				( 24UL )
+#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE			( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE						( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR					( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         FD
+	 * 1111 1111  1111 1111  1111 1111  1111 1101
+	 *
+	 * Bit[6] - 1 --> The exception was taken from the Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 1 --> The exception was taken to the Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
+#else
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         BC
+	 * 1111 1111  1111 1111  1111 1111  1011 1100
+	 *
+	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS			prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS				1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT				0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Setup the Memory Protection Unit (MPU).
+	 */
+	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+	/**
+	 * @brief Setup the Floating Point Unit (FPU).
+	 */
+	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Saved as part of the task context to indicate which context the
+	 * task is using on the secure side.
+	 */
+	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Stop and reset the SysTick. */
+	*( portNVIC_SYSTICK_CTRL ) = 0UL;
+	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+	/* A function that implements a task must not exit or attempt to return to
+	 * its caller as there is nothing to return to. If a task wants to exit it
+	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
+	 * to be triggered if configASSERT() is defined, then stop here so
+	 * application writers can catch the error. */
+	configASSERT( ulCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		 * started to remove a compiler warning about the function being
+		 * defined but never called.  ulDummy is used purely to quieten other
+		 * warnings about code appearing after this function is called - making
+		 * ulDummy volatile makes the compiler think the function could return
+		 * and therefore not output an 'unreachable code' warning for code that
+		 * appears after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __privileged_functions_start__;
+		extern uint32_t * __privileged_functions_end__;
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+		extern uint32_t * __unprivileged_flash_start__;
+		extern uint32_t * __unprivileged_flash_end__;
+		extern uint32_t * __privileged_sram_start__;
+		extern uint32_t * __privileged_sram_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __privileged_functions_start__[];
+		extern uint32_t __privileged_functions_end__[];
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+		extern uint32_t __unprivileged_flash_start__[];
+		extern uint32_t __unprivileged_flash_end__[];
+		extern uint32_t __privileged_sram_start__[];
+		extern uint32_t __privileged_sram_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+
+		/* Check that the MPU is present. */
+		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+		{
+			/* MAIR0 - Index 0. */
+			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+			/* MAIR0 - Index 1. */
+			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+			/* Setup privileged flash as Read Only so that privileged tasks can
+			 * read it but not modify. */
+			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged flash as Read Only by both privileged and
+			 * unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged syscalls flash as Read Only by both privileged
+			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup RAM containing kernel data for privileged access only. */
+			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+								( portMPU_REGION_EXECUTE_NEVER );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Enable mem fault. */
+			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+			/* Enable MPU with privileged background access i.e. unmapped
+			 * regions have privileged access. */
+			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			/* Enable non-secure access to the FPU. */
+			SecureInit_EnableNSFPUAccess();
+		}
+		#endif /* configENABLE_TRUSTZONE */
+
+		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+		 * unprivileged code should be able to access FPU. CP11 should be
+		 * programmed to the same value as CP10. */
+		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+							);
+
+		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
+		 * context on exception entry and restore on exception return.
+		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
+		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+	}
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Set a PendSV to request a context switch. */
+	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	portDISABLE_INTERRUPTS();
+	ulCriticalNesting++;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	configASSERT( ulCriticalNesting );
+	ulCriticalNesting--;
+
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	uint32_t ulR0;
+	#if( configENABLE_MPU == 1 )
+		uint32_t ulControl, ulIsTaskPrivileged;
+	#endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
+	 * R12, LR, PC, xPSR. */
+	ulPC = pulCallerStackAddress[ 6 ];
+	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+	switch( ucSVCNumber )
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+			case portSVC_ALLOCATE_SECURE_CONTEXT:
+			{
+				/* R0 contains the stack size passed as parameter to the
+				 * vPortAllocateSecureContext function. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Read the CONTROL register value. */
+					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+					/* The task that raised the SVC is privileged if Bit[0]
+					 * in the CONTROL register is 0. */
+					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+				}
+				#else
+				{
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0 );
+				}
+				#endif /* configENABLE_MPU */
+
+				configASSERT( xSecureContext != NULL );
+				SecureContext_LoadContext( xSecureContext );
+			}
+			break;
+
+			case portSVC_FREE_SECURE_CONTEXT:
+			{
+				/* R0 contains the secure context handle to be freed. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				/* Free the secure context. */
+				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+			}
+			break;
+		#endif /* configENABLE_TRUSTZONE */
+
+		case portSVC_START_SCHEDULER:
+		{
+			#if( configENABLE_TRUSTZONE == 1 )
+			{
+				/* De-prioritize the non-secure exceptions so that the
+				 * non-secure pendSV runs at the lowest priority. */
+				SecureInit_DePrioritizeNSExceptions();
+
+				/* Initialize the secure context management system. */
+				SecureContext_Init();
+			}
+			#endif /* configENABLE_TRUSTZONE */
+
+			#if( configENABLE_FPU == 1 )
+			{
+				/* Setup the Floating Point Unit (FPU). */
+				prvSetupFPU();
+			}
+			#endif /* configENABLE_FPU */
+
+			/* Setup the context of the first task so that the first task starts
+			 * executing. */
+			vRestoreContextOfFirstTask();
+		}
+		break;
+
+		#if( configENABLE_MPU == 1 )
+			case portSVC_RAISE_PRIVILEGE:
+			{
+				/* Only raise the privilege, if the svc was raised from any of
+				 * the system calls. */
+				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+				{
+					vRaisePrivilege();
+				}
+			}
+			break;
+		#endif /* configENABLE_MPU */
+
+		default:
+		{
+			/* Incorrect SVC call. */
+			configASSERT( pdFALSE );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	 * interrupt. */
+	#if( portPRELOAD_REGISTERS == 0 )
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
+		*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#else /* portPRELOAD_REGISTERS */
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
+		pxTopOfStack--;
+		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#endif /* portPRELOAD_REGISTERS */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+	#if( configENABLE_MPU == 1 )
+	{
+		/* Setup the Memory Protection Unit (MPU). */
+		prvSetupMPU();
+	}
+	#endif /* configENABLE_MPU */
+
+	/* Start the timer that generates the tick ISR. Interrupts are disabled
+	 * here already. */
+	prvSetupTimerInterrupt();
+
+	/* Initialize the critical nesting count ready for the first task. */
+	ulCriticalNesting = 0;
+
+	/* Start the first task. */
+	vStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing. Call the task
+	 * exit error function to prevent compiler warnings about a static function
+	 * not being called in the case that the application writer overrides this
+	 * functionality by defining configTASK_RETURN_ADDRESS. Call
+	 * vTaskSwitchContext() so link time optimization does not remove the
+	 * symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Not implemented in ports where there is nothing to return to.
+	 * Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+	{
+	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+	int32_t lIndex = 0;
+
+		/* Setup MAIR0. */
+		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+		/* This function is called automatically when the task is created - in
+		 * which case the stack region parameters will be valid.  At all other
+		 * times the stack parameters will not be valid and it is assumed that
+		 * the stack region has already been configured. */
+		if( ulStackDepth > 0 )
+		{
+			/* Define the region that allows access to the stack. */
+			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
+															( portMPU_REGION_NON_SHAREABLE ) |
+															( portMPU_REGION_READ_WRITE ) |
+															( portMPU_REGION_EXECUTE_NEVER );
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
+															( portMPU_RLAR_ATTR_INDEX0 ) |
+															( portMPU_RLAR_REGION_ENABLE );
+		}
+
+		/* User supplied configurable regions. */
+		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+		{
+			/* If xRegions is NULL i.e. the task has not specified any MPU
+			 * region, the else part ensures that all the configurable MPU
+			 * regions are invalidated. */
+			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+			{
+				/* Translate the generic region definition contained in xRegions
+				 * into the ARMv8 specific MPU settings that are then stored in
+				 * xMPUSettings. */
+				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+				/* Start address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
+																			( portMPU_REGION_NON_SHAREABLE );
+
+				/* RO/RW. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+				}
+				else
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+				}
+
+				/* XN. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+				}
+
+				/* End Address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
+																			( portMPU_RLAR_REGION_ENABLE );
+
+				/* Normal memory/ Device memory. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+				{
+					/* Attr1 in MAIR0 is configured as device memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+				}
+				else
+				{
+					/* Attr1 in MAIR0 is configured as normal memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+				}
+			}
+			else
+			{
+				/* Invalidate the region. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+			}
+
+			lIndex++;
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
new file mode 100644
index 0000000..e4fbe2d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
@@ -0,0 +1,468 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"													\n"
+	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr  r3, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr  r0, [r3]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r5, #1										\n" /* r5 = 1. */
+	"	bics r4, r5										\n" /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+	"	ldr  r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
+	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str  r4, [r2]									\n" /* Program MAIR0. */
+	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+	"	movs r5, #4										\n" /* r5 = 4. */
+	"	str  r5, [r2]									\n" /* Program RNR = 4. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read first set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write first set of RBAR/RLAR registers. */
+	"	movs r5, #5										\n" /* r5 = 5. */
+	"	str  r5, [r2]									\n" /* Program RNR = 5. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read second set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write second set of RBAR/RLAR registers. */
+	"	movs r5, #6										\n" /* r5 = 6. */
+	"	str  r5, [r2]									\n" /* Program RNR = 6. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read third set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write third set of RBAR/RLAR registers. */
+	"	movs r5, #7										\n" /* r5 = 7. */
+	"	str  r5, [r2]									\n" /* Program RNR = 7. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write fourth set of RBAR/RLAR registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r5, #1										\n" /* r5 = 1. */
+	"	orrs r4, r5										\n" /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	ldm  r0!, {r1-r4}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+	"	ldr  r5, xSecureContextConst2					\n"
+	"	str  r1, [r5]									\n" /* Set xSecureContext to this task's value for the same. */
+	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
+	"	msr  control, r3								\n" /* Set this task's CONTROL value. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r4											\n" /* Finally, branch to EXC_RETURN. */
+	#else /* configENABLE_MPU */
+	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+	"	ldr  r4, xSecureContextConst2					\n"
+	"	str  r1, [r4]									\n" /* Set xSecureContext to this task's value for the same. */
+	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
+	"	movs r1, #2										\n" /* r1 = 2. */
+	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+	"xSecureContextConst2: .word xSecureContext			\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst2: .word 0xe000ed94					\n"
+	"xMAIR0Const2: .word 0xe000edc0						\n"
+	"xRNRConst2: .word 0xe000ed98						\n"
+	"xRBARConst2: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	movs r1, #1										\n" /* r1 = 1. */
+	"	tst r0, r1										\n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+	"	beq running_privileged							\n" /* If the result of previous AND operation was 0, branch. */
+	"	movs r0, #0										\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	"	bx lr											\n" /* Return. */
+	" running_privileged:								\n"
+	"	movs r0, #1										\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	"	bx lr											\n" /* Return. */
+	"													\n"
+	"	.align 4										\n"
+	::: "r0", "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	 __asm volatile
+	(
+	"	mrs r0, control									\n" /* Read the CONTROL register. */
+	"	movs r1, #1										\n" /* r1 = 1. */
+	"	bics r0, r1										\n" /* Clear the bit 0. */
+	"	msr control, r0									\n" /* Write back the new CONTROL value. */
+	"	bx lr											\n" /* Return to the caller. */
+	::: "r0", "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	movs r1, #1										\n" /* r1 = 1. */
+	"	orrs r0, r1										\n" /* r0 = r0 | r1. */
+	"	msr control, r0									\n" /* CONTROL = r0. */
+	"	bx lr											\n" /* Return to the caller. */
+	:::"r0", "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
+	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
+	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
+	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
+	"	cpsie i											\n" /* Globally enable interrupts. */
+	"	dsb												\n"
+	"	isb												\n"
+	"	svc %0											\n" /* System call to start the first task. */
+	"	nop												\n"
+	"													\n"
+	"   .align 4										\n"
+	"xVTORConst: .word 0xe000ed08						\n"
+	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	mrs r0, PRIMASK									\n"
+	"	cpsid i											\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* To avoid compiler warnings.  The return statement will never be reached,
+	 * but some compilers warn if it is not included, while others won't compile
+	 * if it is. */
+	return 0;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	msr PRIMASK, r0									\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* Just to avoid compiler warning.  ulMask is used from the asm code but
+	 * the compiler can't see that.  Some compilers generate warnings without
+	 * the following line, while others generate warnings if the line is
+	 * included. */
+	( void ) ulMask;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"	.extern SecureContext_SaveContext				\n"
+	"	.extern SecureContext_LoadContext				\n"
+	"													\n"
+	"	mrs r1, psp										\n" /* Read PSP in r1. */
+	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	"	ldr r0, [r2]									\n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+	"													\n"
+	"	cbz r0, save_ns_context							\n" /* No secure context to save. */
+	"	push {r0-r2, r14}								\n"
+	"	bl SecureContext_SaveContext					\n"
+	"	pop {r0-r3}										\n" /* LR is now in r3. */
+	"	mov lr, r3										\n" /* LR = r3. */
+	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	"	bpl save_ns_context								\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
+	#if( configENABLE_MPU == 1 )
+	"	subs r1, r1, #16								\n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mrs r3, control									\n" /* r3 = CONTROL. */
+	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
+	"	stmia r1!, {r0, r2-r4}							\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	#else /* configENABLE_MPU */
+	"	subs r1, r1, #12								\n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+	#endif /* configENABLE_MPU */
+	"	b select_next_task								\n"
+	"													\n"
+	" save_ns_context:									\n"
+	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
+	#if( configENABLE_MPU == 1 )
+	"	subs r1, r1, #48								\n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	adds r1, r1, #16								\n" /* r1 = r1 + 16. */
+	"	stmia r1!, {r4-r7}								\n" /* Store the low registers that are not saved automatically. */
+	"	mov r4, r8										\n" /* r4 = r8. */
+	"	mov r5, r9										\n" /* r5 = r9. */
+	"	mov r6, r10										\n" /* r6 = r10. */
+	"	mov r7, r11										\n" /* r7 = r11. */
+	"	stmia r1!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mrs r3, control									\n" /* r3 = CONTROL. */
+	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
+	"	subs r1, r1, #48								\n" /* r1 = r1 - 48. */
+	"	stmia r1!, {r0, r2-r4}							\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	#else /* configENABLE_MPU */
+	"	subs r1, r1, #44								\n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	stmia r1!, {r0, r2-r7}							\n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
+	"	mov r4, r8										\n" /* r4 = r8. */
+	"	mov r5, r9										\n" /* r5 = r9. */
+	"	mov r6, r10										\n" /* r6 = r10. */
+	"	mov r7, r11										\n" /* r7 = r11. */
+	"	stmia r1!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	" select_next_task:									\n"
+	"	cpsid i											\n"
+	"	bl vTaskSwitchContext							\n"
+	"	cpsie i											\n"
+	"													\n"
+	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r3, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr r1, [r3]									\n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r5, #1										\n" /* r5 = 1. */
+	"	bics r4, r5										\n" /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+	"	ldr r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
+	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str r4, [r2]									\n" /* Program MAIR0. */
+	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+	"	movs r5, #4										\n" /* r5 = 4. */
+	"	str  r5, [r2]									\n" /* Program RNR = 4. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read first set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write first set of RBAR/RLAR registers. */
+	"	movs r5, #5										\n" /* r5 = 5. */
+	"	str  r5, [r2]									\n" /* Program RNR = 5. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read second set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write second set of RBAR/RLAR registers. */
+	"	movs r5, #6										\n" /* r5 = 6. */
+	"	str  r5, [r2]									\n" /* Program RNR = 6. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read third set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write third set of RBAR/RLAR registers. */
+	"	movs r5, #7										\n" /* r5 = 7. */
+	"	str  r5, [r2]									\n" /* Program RNR = 7. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write fourth set of RBAR/RLAR registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r5, #1										\n" /* r5 = 1. */
+	"	orrs r4, r5										\n" /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	ldmia r1!, {r0, r2-r4}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
+	"	msr control, r3									\n" /* Restore the CONTROL register value for the task. */
+	"	mov lr, r4										\n" /* LR = r4. */
+	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
+	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
+	"	push {r1,r4}									\n"
+	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
+	"	pop {r1,r4}										\n"
+	"	mov lr, r4										\n" /* LR = r4. */
+	"	lsls r2, r4, #25								\n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
+	"	bx lr											\n"
+	#else /* configENABLE_MPU */
+	"	ldmia r1!, {r0, r2-r3}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
+	"	mov lr, r3										\n" /* LR = r3. */
+	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
+	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
+	"	push {r1,r3}									\n"
+	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
+	"	pop {r1,r3}										\n"
+	"	mov lr, r3										\n" /* LR = r3. */
+	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
+	"	bx lr											\n"
+	#endif /* configENABLE_MPU */
+	"													\n"
+	" restore_ns_context:								\n"
+	"	adds r1, r1, #16								\n" /* Move to the high registers. */
+	"	ldmia r1!, {r4-r7}								\n" /* Restore the high registers that are not automatically restored. */
+	"	mov r8, r4										\n" /* r8 = r4. */
+	"	mov r9, r5										\n" /* r9 = r5. */
+	"	mov r10, r6										\n" /* r10 = r6. */
+	"	mov r11, r7										\n" /* r11 = r7. */
+	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
+	"	subs r1, r1, #32								\n" /* Go back to the low registers. */
+	"	ldmia r1!, {r4-r7}								\n" /* Restore the low registers that are not automatically restored. */
+	"	bx lr											\n"
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
+	"xSecureContextConst: .word xSecureContext			\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst: .word 0xe000ed94					\n"
+	"xMAIR0Const: .word 0xe000edc0						\n"
+	"xRNRConst: .word 0xe000ed98						\n"
+	"xRBARConst: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	movs r0, #4										\n"
+	"	mov r1, lr										\n"
+	"	tst r0, r1										\n"
+	"	beq stacking_used_msp							\n"
+	"	mrs r0, psp										\n"
+	"	ldr r2, svchandler_address_const				\n"
+	"	bx r2											\n"
+	" stacking_used_msp:								\n"
+	"	mrs r0, msp										\n"
+	"	ldr r2, svchandler_address_const				\n"
+	"	bx r2											\n"
+	"													\n"
+	"	.align 4										\n"
+	"svchandler_address_const: .word vPortSVCHandler_C	\n"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	svc %0											\n" /* Secure context is allocated in the supervisor call. */
+	"	bx lr											\n" /* Return. */
+	:: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	ldr r1, [r0]									\n" /* The first item in the TCB is the top of the stack. */
+	"	ldr r0, [r1]									\n" /* The first item on the stack is the task's xSecureContext. */
+	"	cmp r0, #0										\n" /* Raise svc if task's xSecureContext is not NULL. */
+	"	beq free_secure_context							\n"
+	"	bx lr											\n" /* There is no secure context (xSecureContext is NULL). */
+	" free_secure_context:								\n"
+	"	svc %0											\n" /* Secure context is freed in the supervisor call. */
+	"	bx lr											\n" /* Return. */
+	:: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
new file mode 100644
index 0000000..bebd9f6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M23"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__attribute__(( used ))
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
new file mode 100644
index 0000000..3ce52c3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
@@ -0,0 +1,381 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"													\n"
+	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr  r1, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr  r0, [r1]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r4, #1										\n" /* r4 = 1. */
+	"	bics r3, r4										\n" /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+	"	str r3, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	"	ldr  r4, [r1]									\n" /* r4 = *r1 i.e. r4 = MAIR0. */
+	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str  r4, [r2]									\n" /* Program MAIR0. */
+	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	"	movs r4, #4										\n" /* r4 = 4. */
+	"	str  r4, [r2]									\n" /* Program RNR = 4. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read first set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write first set of RBAR/RLAR registers. */
+	"	movs r4, #5										\n" /* r4 = 5. */
+	"	str  r4, [r2]									\n" /* Program RNR = 5. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read second set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write second set of RBAR/RLAR registers. */
+	"	movs r4, #6										\n" /* r4 = 6. */
+	"	str  r4, [r2]									\n" /* Program RNR = 6. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read third set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write third set of RBAR/RLAR registers. */
+	"	movs r4, #7										\n" /* r4 = 7. */
+	"	str  r4, [r2]									\n" /* Program RNR = 7. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write fourth set of RBAR/RLAR registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r4, #1										\n" /* r4 = 1. */
+	"	orrs r3, r4										\n" /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+	"	str r3, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
+	"	msr  control, r2								\n" /* Set this task's CONTROL value. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
+	#else /* configENABLE_MPU */
+	"	ldm  r0!, {r1-r2}								\n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
+	"	movs r1, #2										\n" /* r1 = 2. */
+	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r2											\n" /* Finally, branch to EXC_RETURN. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst2: .word 0xe000ed94					\n"
+	"xMAIR0Const2: .word 0xe000edc0						\n"
+	"xRNRConst2: .word 0xe000ed98						\n"
+	"xRBARConst2: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	movs r1, #1										\n" /* r1 = 1. */
+	"	tst r0, r1										\n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+	"	beq running_privileged							\n" /* If the result of previous AND operation was 0, branch. */
+	"	movs r0, #0										\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	"	bx lr											\n" /* Return. */
+	" running_privileged:								\n"
+	"	movs r0, #1										\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	"	bx lr											\n" /* Return. */
+	"													\n"
+	"	.align 4										\n"
+	::: "r0", "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	 __asm volatile
+	(
+	"	mrs  r0, control								\n" /* Read the CONTROL register. */
+	"	movs r1, #1										\n" /* r1 = 1. */
+	"	bics r0, r1										\n" /* Clear the bit 0. */
+	"	msr  control, r0								\n" /* Write back the new CONTROL value. */
+	"	bx lr											\n" /* Return to the caller. */
+	::: "r0", "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	movs r1, #1										\n" /* r1 = 1. */
+	"	orrs r0, r1										\n" /* r0 = r0 | r1. */
+	"	msr control, r0									\n" /* CONTROL = r0. */
+	"	bx lr											\n" /* Return to the caller. */
+	:::"r0", "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
+	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
+	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
+	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
+	"	cpsie i											\n" /* Globally enable interrupts. */
+	"	dsb												\n"
+	"	isb												\n"
+	"	svc %0											\n" /* System call to start the first task. */
+	"	nop												\n"
+	"													\n"
+	"   .align 4										\n"
+	"xVTORConst: .word 0xe000ed08						\n"
+	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	mrs r0, PRIMASK									\n"
+	"	cpsid i											\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* To avoid compiler warnings.  The return statement will never be reached,
+	 * but some compilers warn if it is not included, while others won't compile
+	 * if it is. */
+	return 0;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	msr PRIMASK, r0									\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* Just to avoid compiler warning.  ulMask is used from the asm code but
+	 * the compiler can't see that.  Some compilers generate warnings without
+	 * the following line, while others generate warnings if the line is
+	 * included. */
+	( void ) ulMask;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"													\n"
+	"	mrs r0, psp										\n" /* Read PSP in r0. */
+	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
+	#if( configENABLE_MPU == 1 )
+	"	subs r0, r0, #44								\n" /* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+	"	str r0, [r1]									\n" /* Save the new top of stack in TCB. */
+	"	mrs r1, psplim									\n" /* r1 = PSPLIM. */
+	"	mrs r2, control									\n" /* r2 = CONTROL. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	stmia r0!, {r1-r7}								\n" /* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */
+	"	mov r4, r8										\n" /* r4 = r8. */
+	"	mov r5, r9										\n" /* r5 = r9. */
+	"	mov r6, r10										\n" /* r6 = r10. */
+	"	mov r7, r11										\n" /* r7 = r11. */
+	"	stmia r0!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
+	#else /* configENABLE_MPU */
+	"	subs r0, r0, #40								\n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */
+	"	str r0, [r1]									\n" /* Save the new top of stack in TCB. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	stmia r0!, {r2-r7}								\n" /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
+	"	mov r4, r8										\n" /* r4 = r8. */
+	"	mov r5, r9										\n" /* r5 = r9. */
+	"	mov r6, r10										\n" /* r6 = r10. */
+	"	mov r7, r11										\n" /* r7 = r11. */
+	"	stmia r0!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	"	cpsid i											\n"
+	"	bl vTaskSwitchContext							\n"
+	"	cpsie i											\n"
+	"													\n"
+	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr r0, [r1]									\n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r4, #1										\n" /* r4 = 1. */
+	"	bics r3, r4										\n" /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+	"	str r3, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	"	ldr  r4, [r1]									\n" /* r4 = *r1 i.e. r4 = MAIR0. */
+	"	ldr  r2, xMAIR0Const							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str  r4, [r2]									\n" /* Program MAIR0. */
+	"	ldr  r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	"	movs r4, #4										\n" /* r4 = 4. */
+	"	str  r4, [r2]									\n" /* Program RNR = 4. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read first set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write first set of RBAR/RLAR registers. */
+	"	movs r4, #5										\n" /* r4 = 5. */
+	"	str  r4, [r2]									\n" /* Program RNR = 5. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read second set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write second set of RBAR/RLAR registers. */
+	"	movs r4, #6										\n" /* r4 = 6. */
+	"	str  r4, [r2]									\n" /* Program RNR = 6. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read third set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write third set of RBAR/RLAR registers. */
+	"	movs r4, #7										\n" /* r4 = 7. */
+	"	str  r4, [r2]									\n" /* Program RNR = 7. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write fourth set of RBAR/RLAR registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r4, #1										\n" /* r4 = 1. */
+	"	orrs r3, r4										\n" /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+	"	str r3, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	adds r0, r0, #28								\n" /* Move to the high registers. */
+	"	ldmia r0!, {r4-r7}								\n" /* Restore the high registers that are not automatically restored. */
+	"	mov r8, r4										\n" /* r8 = r4. */
+	"	mov r9, r5										\n" /* r9 = r5. */
+	"	mov r10, r6										\n" /* r10 = r6. */
+	"	mov r11, r7										\n" /* r11 = r7. */
+	"	msr psp, r0										\n" /* Remember the new top of stack for the task. */
+	"	subs r0, r0, #44								\n" /* Move to the starting of the saved context. */
+	"	ldmia r0!, {r1-r7}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */
+	"	msr psplim, r1									\n" /* Restore the PSPLIM register value for the task. */
+	"	msr control, r2									\n" /* Restore the CONTROL register value for the task. */
+	"	bx r3											\n"
+	#else /* configENABLE_MPU */
+	"	adds r0, r0, #24								\n" /* Move to the high registers. */
+	"	ldmia r0!, {r4-r7}								\n" /* Restore the high registers that are not automatically restored. */
+	"	mov r8, r4										\n" /* r8 = r4. */
+	"	mov r9, r5										\n" /* r9 = r5. */
+	"	mov r10, r6										\n" /* r10 = r6. */
+	"	mov r11, r7										\n" /* r11 = r7. */
+	"	msr psp, r0										\n" /* Remember the new top of stack for the task. */
+	"	subs r0, r0, #40								\n" /* Move to the starting of the saved context. */
+	"	ldmia r0!, {r2-r7}								\n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
+	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
+	"	bx r3											\n"
+	#endif /* configENABLE_MPU */
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst: .word 0xe000ed94					\n"
+	"xMAIR0Const: .word 0xe000edc0						\n"
+	"xRNRConst: .word 0xe000ed98						\n"
+	"xRBARConst: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	movs r0, #4										\n"
+	"	mov r1, lr										\n"
+	"	tst r0, r1										\n"
+	"	beq stacking_used_msp							\n"
+	"	mrs r0, psp										\n"
+	"	ldr r2, svchandler_address_const				\n"
+	"	bx r2											\n"
+	" stacking_used_msp:								\n"
+	"	mrs r0, msp										\n"
+	"	ldr r2, svchandler_address_const				\n"
+	"	bx r2											\n"
+	"													\n"
+	"	.align 4										\n"
+	"svchandler_address_const: .word vPortSVCHandler_C	\n"
+	);
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
new file mode 100644
index 0000000..bebd9f6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M23"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__attribute__(( used ))
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
new file mode 100644
index 0000000..f4be178
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
@@ -0,0 +1,415 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"													\n"
+	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr  r3, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr  r0, [r3]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+	"	ldr  r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
+	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str  r4, [r2]									\n" /* Program MAIR0. */
+	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	movs r4, #4										\n" /* r4 = 4. */
+	"	str  r4, [r2]									\n" /* Program RNR = 4. */
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+	"	ldr  r2, xRBARConst2							\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+	"	ldmia r3!, {r4-r11}								\n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	ldm  r0!, {r1-r4}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+	"	ldr  r5, xSecureContextConst2					\n"
+	"	str  r1, [r5]									\n" /* Set xSecureContext to this task's value for the same. */
+	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
+	"	msr  control, r3								\n" /* Set this task's CONTROL value. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r4											\n" /* Finally, branch to EXC_RETURN. */
+	#else /* configENABLE_MPU */
+	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+	"	ldr  r4, xSecureContextConst2					\n"
+	"	str  r1, [r4]									\n" /* Set xSecureContext to this task's value for the same. */
+	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
+	"	movs r1, #2										\n" /* r1 = 2. */
+	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+	"xSecureContextConst2: .word xSecureContext			\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst2: .word 0xe000ed94					\n"
+	"xMAIR0Const2: .word 0xe000edc0						\n"
+	"xRNRConst2: .word 0xe000ed98						\n"
+	"xRBARConst2: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	tst r0, #1										\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	"	ite ne											\n"
+	"	movne r0, #0									\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	"	moveq r0, #1									\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	"	bx lr											\n" /* Return. */
+	"													\n"
+	"	.align 4										\n"
+	::: "r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	 __asm volatile
+	(
+	"	mrs r0, control									\n" /* Read the CONTROL register. */
+	"	bic r0, #1										\n" /* Clear the bit 0. */
+	"	msr control, r0									\n" /* Write back the new CONTROL value. */
+	"	bx lr											\n" /* Return to the caller. */
+	::: "r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	orr r0, #1										\n" /* r0 = r0 | 1. */
+	"	msr control, r0									\n" /* CONTROL = r0. */
+	"	bx lr											\n" /* Return to the caller. */
+	:::"r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
+	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
+	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
+	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
+	"	cpsie i											\n" /* Globally enable interrupts. */
+	"	cpsie f											\n"
+	"	dsb												\n"
+	"	isb												\n"
+	"	svc %0											\n" /* System call to start the first task. */
+	"	nop												\n"
+	"													\n"
+	"   .align 4										\n"
+	"xVTORConst: .word 0xe000ed08						\n"
+	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	mrs r0, PRIMASK									\n"
+	"	cpsid i											\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* To avoid compiler warnings.  The return statement will never be reached,
+	 * but some compilers warn if it is not included, while others won't compile
+	 * if it is. */
+	return 0;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	msr PRIMASK, r0									\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* Just to avoid compiler warning.  ulMask is used from the asm code but
+	 * the compiler can't see that.  Some compilers generate warnings without
+	 * the following line, while others generate warnings if the line is
+	 * included. */
+	( void ) ulMask;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"	.extern SecureContext_SaveContext				\n"
+	"	.extern SecureContext_LoadContext				\n"
+	"													\n"
+	"	mrs r1, psp										\n" /* Read PSP in r1. */
+	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	"	ldr r0, [r2]									\n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+	"													\n"
+	"	cbz r0, save_ns_context							\n" /* No secure context to save. */
+	"	push {r0-r2, r14}								\n"
+	"	bl SecureContext_SaveContext					\n"
+	"	pop {r0-r3}										\n" /* LR is now in r3. */
+	"	mov lr, r3										\n" /* LR = r3. */
+	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	"	bpl save_ns_context								\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
+	#if( configENABLE_MPU == 1 )
+	"	subs r1, r1, #16								\n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mrs r3, control									\n" /* r3 = CONTROL. */
+	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
+	"	stmia r1!, {r0, r2-r4}							\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	#else /* configENABLE_MPU */
+	"	subs r1, r1, #12								\n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+	#endif /* configENABLE_MPU */
+	"	b select_next_task								\n"
+	"													\n"
+	" save_ns_context:									\n"
+	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
+	#if( configENABLE_FPU == 1 )
+	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+	"	it eq											\n"
+	"	vstmdbeq r1!, {s16-s31}							\n" /* Store the FPU registers which are not saved automatically. */
+	#endif /* configENABLE_FPU */
+	#if( configENABLE_MPU == 1 )
+	"	subs r1, r1, #48								\n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	adds r1, r1, #16								\n" /* r1 = r1 + 16. */
+	"	stm r1, {r4-r11}								\n" /* Store the registers that are not saved automatically. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mrs r3, control									\n" /* r3 = CONTROL. */
+	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
+	"	subs r1, r1, #16								\n" /* r1 = r1 - 16. */
+	"	stm r1, {r0, r2-r4}								\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	#else /* configENABLE_MPU */
+	"	subs r1, r1, #44								\n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	adds r1, r1, #12								\n" /* r1 = r1 + 12. */
+	"	stm r1, {r4-r11}								\n" /* Store the registers that are not saved automatically. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	subs r1, r1, #12								\n" /* r1 = r1 - 12. */
+	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	" select_next_task:									\n"
+	"	cpsid i											\n"
+	"	bl vTaskSwitchContext							\n"
+	"	cpsie i											\n"
+	"													\n"
+	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r3, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr r1, [r3]									\n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+	"	ldr r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
+	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str r4, [r2]									\n" /* Program MAIR0. */
+	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	movs r4, #4										\n" /* r4 = 4. */
+	"	str r4, [r2]									\n" /* Program RNR = 4. */
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+	"	ldr  r2, xRBARConst								\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+	"	ldmia r3!, {r4-r11}								\n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	ldmia r1!, {r0, r2-r4}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
+	"	msr control, r3									\n" /* Restore the CONTROL register value for the task. */
+	"	mov lr, r4										\n" /* LR = r4. */
+	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
+	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
+	"	push {r1,r4}									\n"
+	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
+	"	pop {r1,r4}										\n"
+	"	mov lr, r4										\n" /* LR = r4. */
+	"	lsls r2, r4, #25								\n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
+	"	bx lr											\n"
+	#else /* configENABLE_MPU */
+	"	ldmia r1!, {r0, r2-r3}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
+	"	mov lr, r3										\n" /* LR = r3. */
+	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
+	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
+	"	push {r1,r3}									\n"
+	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
+	"	pop {r1,r3}										\n"
+	"	mov lr, r3										\n" /* LR = r3. */
+	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
+	"	bx lr											\n"
+	#endif /* configENABLE_MPU */
+	"													\n"
+	" restore_ns_context:								\n"
+	"	ldmia r1!, {r4-r11}								\n" /* Restore the registers that are not automatically restored. */
+	#if( configENABLE_FPU == 1 )
+	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+	"	it eq											\n"
+	"	vldmiaeq r1!, {s16-s31}							\n" /* Restore the FPU registers which are not restored automatically. */
+	#endif /* configENABLE_FPU */
+	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
+	"	bx lr											\n"
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
+	"xSecureContextConst: .word xSecureContext			\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst: .word 0xe000ed94					\n"
+	"xMAIR0Const: .word 0xe000edc0						\n"
+	"xRNRConst: .word 0xe000ed98						\n"
+	"xRBARConst: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	tst lr, #4										\n"
+	"	ite eq											\n"
+	"	mrseq r0, msp									\n"
+	"	mrsne r0, psp									\n"
+	"	ldr r1, svchandler_address_const				\n"
+	"	bx r1											\n"
+	"													\n"
+	"	.align 4										\n"
+	"svchandler_address_const: .word vPortSVCHandler_C	\n"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	svc %0											\n" /* Secure context is allocated in the supervisor call. */
+	"	bx lr											\n" /* Return. */
+	:: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	ldr r1, [r0]									\n" /* The first item in the TCB is the top of the stack. */
+	"	ldr r0, [r1]									\n" /* The first item on the stack is the task's xSecureContext. */
+	"	cmp r0, #0										\n" /* Raise svc if task's xSecureContext is not NULL. */
+	"	it ne											\n"
+	"	svcne %0										\n" /* Secure context is freed in the supervisor call. */
+	"	bx lr											\n" /* Return. */
+	:: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
new file mode 100644
index 0000000..90d9bc2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M33"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__attribute__(( used ))
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
new file mode 100644
index 0000000..2f87d0f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
@@ -0,0 +1,321 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"													\n"
+	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr  r1, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr  r0, [r1]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	"	ldr  r3, [r1]									\n" /* r3 = *r1 i.e. r3 = MAIR0. */
+	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str  r3, [r2]									\n" /* Program MAIR0. */
+	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	movs r3, #4										\n" /* r3 = 4. */
+	"	str  r3, [r2]									\n" /* Program RNR = 4. */
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	"	ldr  r2, xRBARConst2							\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+	"	ldmia r1!, {r4-r11}								\n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
+	"	msr  control, r2								\n" /* Set this task's CONTROL value. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
+	#else /* configENABLE_MPU */
+	"	ldm  r0!, {r1-r2}								\n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
+	"	movs r1, #2										\n" /* r1 = 2. */
+	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r2											\n" /* Finally, branch to EXC_RETURN. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst2: .word 0xe000ed94					\n"
+	"xMAIR0Const2: .word 0xe000edc0						\n"
+	"xRNRConst2: .word 0xe000ed98						\n"
+	"xRBARConst2: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	tst r0, #1										\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	"	ite ne											\n"
+	"	movne r0, #0									\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	"	moveq r0, #1									\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	"	bx lr											\n" /* Return. */
+	"													\n"
+	"	.align 4										\n"
+	::: "r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	 __asm volatile
+	(
+	"	mrs  r0, control								\n" /* Read the CONTROL register. */
+	"	bic r0, #1										\n" /* Clear the bit 0. */
+	"	msr  control, r0								\n" /* Write back the new CONTROL value. */
+	"	bx lr											\n" /* Return to the caller. */
+	::: "r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	orr r0, #1										\n" /* r0 = r0 | 1. */
+	"	msr control, r0									\n" /* CONTROL = r0. */
+	"	bx lr											\n" /* Return to the caller. */
+	:::"r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
+	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
+	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
+	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
+	"	cpsie i											\n" /* Globally enable interrupts. */
+	"	cpsie f											\n"
+	"	dsb												\n"
+	"	isb												\n"
+	"	svc %0											\n" /* System call to start the first task. */
+	"	nop												\n"
+	"													\n"
+	"   .align 4										\n"
+	"xVTORConst: .word 0xe000ed08						\n"
+	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	mrs r0, PRIMASK									\n"
+	"	cpsid i											\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* To avoid compiler warnings.  The return statement will never be reached,
+	 * but some compilers warn if it is not included, while others won't compile
+	 * if it is. */
+	return 0;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	msr PRIMASK, r0									\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* Just to avoid compiler warning.  ulMask is used from the asm code but
+	 * the compiler can't see that.  Some compilers generate warnings without
+	 * the following line, while others generate warnings if the line is
+	 * included. */
+	( void ) ulMask;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"													\n"
+	"	mrs r0, psp										\n" /* Read PSP in r0. */
+	#if( configENABLE_FPU == 1 )
+	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+	"	it eq											\n"
+	"	vstmdbeq r0!, {s16-s31}							\n" /* Store the FPU registers which are not saved automatically. */
+	#endif /* configENABLE_FPU */
+	#if( configENABLE_MPU == 1 )
+	"	mrs r1, psplim									\n" /* r1 = PSPLIM. */
+	"	mrs r2, control									\n" /* r2 = CONTROL. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	stmdb r0!, {r1-r11}								\n" /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
+	#else /* configENABLE_MPU */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	stmdb r0!, {r2-r11}								\n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
+	"	str r0, [r1]									\n" /* Save the new top of stack in TCB. */
+	"													\n"
+	"	cpsid i											\n"
+	"	bl vTaskSwitchContext							\n"
+	"	cpsie i											\n"
+	"													\n"
+	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr r0, [r1]									\n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	"	ldr r3, [r1]									\n" /* r3 = *r1 i.e. r3 = MAIR0. */
+	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str r3, [r2]									\n" /* Program MAIR0. */
+	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	movs r3, #4										\n" /* r3 = 4. */
+	"	str r3, [r2]									\n" /* Program RNR = 4. */
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	"	ldr r2, xRBARConst								\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+	"	ldmia r1!, {r4-r11}								\n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	ldmia r0!, {r1-r11}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
+	#else /* configENABLE_MPU */
+	"	ldmia r0!, {r2-r11}								\n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_FPU == 1 )
+	"	tst r3, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+	"	it eq											\n"
+	"	vldmiaeq r0!, {s16-s31}							\n" /* Restore the FPU registers which are not restored automatically. */
+	#endif /* configENABLE_FPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	msr psplim, r1									\n" /* Restore the PSPLIM register value for the task. */
+	"	msr control, r2									\n" /* Restore the CONTROL register value for the task. */
+	#else /* configENABLE_MPU */
+	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
+	#endif /* configENABLE_MPU */
+	"	msr psp, r0										\n" /* Remember the new top of stack for the task. */
+	"	bx r3											\n"
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst: .word 0xe000ed94					\n"
+	"xMAIR0Const: .word 0xe000edc0						\n"
+	"xRNRConst: .word 0xe000ed98						\n"
+	"xRBARConst: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	tst lr, #4										\n"
+	"	ite eq											\n"
+	"	mrseq r0, msp									\n"
+	"	mrsne r0, psp									\n"
+	"	ldr r1, svchandler_address_const				\n"
+	"	bx r1											\n"
+	"													\n"
+	"	.align 4										\n"
+	"svchandler_address_const: .word vPortSVCHandler_C	\n"
+	);
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
new file mode 100644
index 0000000..90d9bc2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M33"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__attribute__(( used ))
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s
new file mode 100644
index 0000000..36872fa
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s
@@ -0,0 +1,377 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	EXTERN pxCurrentTCB
+	EXTERN xSecureContext
+	EXTERN vTaskSwitchContext
+	EXTERN vPortSVCHandler_C
+	EXTERN SecureContext_SaveContext
+	EXTERN SecureContext_LoadContext
+
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
+	PUBLIC vPortAllocateSecureContext
+	PUBLIC vRestoreContextOfFirstTask
+	PUBLIC vRaisePrivilege
+	PUBLIC vStartFirstTask
+	PUBLIC ulSetInterruptMaskFromISR
+	PUBLIC vClearInterruptMaskFromISR
+	PUBLIC PendSV_Handler
+	PUBLIC SVC_Handler
+	PUBLIC vPortFreeSecureContext
+
+#if ( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+	mrs r0, control							/* r0 = CONTROL. */
+	movs r1, #1								/* r1 = 1. */
+	tst r0, r1								/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+	beq running_privileged					/* If the result of previous AND operation was 0, branch. */
+	movs r0, #0								/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	bx lr									/* Return. */
+	running_privileged:
+		movs r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+		bx lr								/* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+	mrs r0, control							/* r0 = CONTROL. */
+	movs r1, #1								/* r1 = 1. */
+	orrs r0, r1								/* r0 = r0 | r1. */
+	msr control, r0							/* CONTROL = r0. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vPortAllocateSecureContext:
+	svc 0									/* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION privileged_functions:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr  r3, [r2]							/* Read pxCurrentTCB. */
+	ldr  r0, [r3]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	movs r5, #1								/* r5 = 1. */
+	bics r4, r5								/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+	str r4, [r2]							/* Disable MPU. */
+
+	adds r3, #4								/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+	ldr  r4, [r3]							/* r4 = *r3 i.e. r4 = MAIR0. */
+	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str  r4, [r2]							/* Program MAIR0. */
+	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+	adds r3, #4								/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+	movs r5, #4								/* r5 = 4. */
+	str  r5, [r2]							/* Program RNR = 4. */
+	ldmia r3!, {r6,r7}						/* Read first set of RBAR/RLAR from TCB. */
+	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
+	stmia r4!, {r6,r7}						/* Write first set of RBAR/RLAR registers. */
+	movs r5, #5								/* r5 = 5. */
+	str  r5, [r2]							/* Program RNR = 5. */
+	ldmia r3!, {r6,r7}						/* Read second set of RBAR/RLAR from TCB. */
+	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
+	stmia r4!, {r6,r7}						/* Write second set of RBAR/RLAR registers. */
+	movs r5, #6								/* r5 = 6. */
+	str  r5, [r2]							/* Program RNR = 6. */
+	ldmia r3!, {r6,r7}						/* Read third set of RBAR/RLAR from TCB. */
+	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
+	stmia r4!, {r6,r7}						/* Write third set of RBAR/RLAR registers. */
+	movs r5, #7								/* r5 = 7. */
+	str  r5, [r2]							/* Program RNR = 7. */
+	ldmia r3!, {r6,r7}						/* Read fourth set of RBAR/RLAR from TCB. */
+	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
+	stmia r4!, {r6,r7}						/* Write fourth set of RBAR/RLAR registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	movs r5, #1								/* r5 = 1. */
+	orrs r4, r5								/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+	str r4, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldm  r0!, {r1-r4}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+	ldr  r5, =xSecureContext
+	str  r1, [r5]							/* Set xSecureContext to this task's value for the same. */
+	msr  psplim, r2							/* Set this task's PSPLIM value. */
+	msr  control, r3						/* Set this task's CONTROL value. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r4									/* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+	ldm  r0!, {r1-r3}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+	ldr  r4, =xSecureContext
+	str  r1, [r4]							/* Set xSecureContext to this task's value for the same. */
+	msr  psplim, r2							/* Set this task's PSPLIM value. */
+	movs r1, #2								/* r1 = 2. */
+	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r3									/* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+	mrs r0, control							/* Read the CONTROL register. */
+	movs r1, #1								/* r1 = 1. */
+	bics r0, r1								/* Clear the bit 0. */
+	msr control, r0							/* Write back the new CONTROL value. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
+	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
+	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
+	msr msp, r0								/* Set the MSP back to the start of the stack. */
+	cpsie i									/* Globally enable interrupts. */
+	dsb
+	isb
+	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMaskFromISR:
+	mrs r0, PRIMASK
+	cpsid i
+	bx lr
+/*-----------------------------------------------------------*/
+
+vClearInterruptMaskFromISR:
+	msr PRIMASK, r0
+	bx lr
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+	mrs r1, psp								/* Read PSP in r1. */
+	ldr r2, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	ldr r0, [r2]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+
+	cbz r0, save_ns_context					/* No secure context to save. */
+	push {r0-r2, r14}
+	bl SecureContext_SaveContext
+	pop {r0-r3}								/* LR is now in r3. */
+	mov lr, r3								/* LR = r3. */
+	lsls r2, r3, #25						/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	bpl save_ns_context						/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r2, [r3]							/* Read pxCurrentTCB. */
+#if ( configENABLE_MPU == 1 )
+	subs r1, r1, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	str r1, [r2]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mrs r3, control							/* r3 = CONTROL. */
+	mov r4, lr								/* r4 = LR/EXC_RETURN. */
+	stmia r1!, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+#else /* configENABLE_MPU */
+	subs r1, r1, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+	str r1, [r2]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmia r1!, {r0, r2-r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
+#endif /* configENABLE_MPU */
+	b select_next_task
+
+	save_ns_context:
+		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r2, [r3]						/* Read pxCurrentTCB. */
+	#if ( configENABLE_MPU == 1 )
+		subs r1, r1, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+		str r1, [r2]						/* Save the new top of stack in TCB. */
+		adds r1, r1, #16					/* r1 = r1 + 16. */
+		stmia r1!, {r4-r7}					/* Store the low registers that are not saved automatically. */
+		mov r4, r8							/* r4 = r8. */
+		mov r5, r9							/* r5 = r9. */
+		mov r6, r10							/* r6 = r10. */
+		mov r7, r11							/* r7 = r11. */
+		stmia r1!, {r4-r7}					/* Store the high registers that are not saved automatically. */
+		mrs r2, psplim						/* r2 = PSPLIM. */
+		mrs r3, control						/* r3 = CONTROL. */
+		mov r4, lr							/* r4 = LR/EXC_RETURN. */
+		subs r1, r1, #48					/* r1 = r1 - 48. */
+		stmia r1!, {r0, r2-r4}				/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	#else /* configENABLE_MPU */
+		subs r1, r1, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+		str r1, [r2]						/* Save the new top of stack in TCB. */
+		mrs r2, psplim						/* r2 = PSPLIM. */
+		mov r3, lr							/* r3 = LR/EXC_RETURN. */
+		stmia r1!, {r0, r2-r7}				/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
+		mov r4, r8							/* r4 = r8. */
+		mov r5, r9							/* r5 = r9. */
+		mov r6, r10							/* r6 = r10. */
+		mov r7, r11							/* r7 = r11. */
+		stmia r1!, {r4-r7}					/* Store the high registers that are not saved automatically. */
+	#endif /* configENABLE_MPU */
+
+	select_next_task:
+		cpsid i
+		bl vTaskSwitchContext
+		cpsie i
+
+		ldr r2, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r3, [r2]						/* Read pxCurrentTCB. */
+		ldr r1, [r3]						/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+
+	#if ( configENABLE_MPU == 1 )
+		dmb									/* Complete outstanding transfers before disabling MPU. */
+		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		movs r5, #1							/* r5 = 1. */
+		bics r4, r5							/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+		str r4, [r2]						/* Disable MPU. */
+
+		adds r3, #4							/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+		ldr r4, [r3]						/* r4 = *r3 i.e. r4 = MAIR0. */
+		ldr r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+		str r4, [r2]						/* Program MAIR0. */
+		ldr r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+		adds r3, #4							/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+		movs r5, #4							/* r5 = 4. */
+		str  r5, [r2]						/* Program RNR = 4. */
+		ldmia r3!, {r6,r7}					/* Read first set of RBAR/RLAR from TCB. */
+		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		stmia r4!, {r6,r7}					/* Write first set of RBAR/RLAR registers. */
+		movs r5, #5							/* r5 = 5. */
+		str  r5, [r2]						/* Program RNR = 5. */
+		ldmia r3!, {r6,r7}					/* Read second set of RBAR/RLAR from TCB. */
+		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		stmia r4!, {r6,r7}					/* Write second set of RBAR/RLAR registers. */
+		movs r5, #6							/* r5 = 6. */
+		str  r5, [r2]						/* Program RNR = 6. */
+		ldmia r3!, {r6,r7}					/* Read third set of RBAR/RLAR from TCB. */
+		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		stmia r4!, {r6,r7}					/* Write third set of RBAR/RLAR registers. */
+		movs r5, #7							/* r5 = 7. */
+		str  r5, [r2]						/* Program RNR = 7. */
+		ldmia r3!, {r6,r7}					/* Read fourth set of RBAR/RLAR from TCB. */
+		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		stmia r4!, {r6,r7}					/* Write fourth set of RBAR/RLAR registers. */
+
+		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		movs r5, #1							/* r5 = 1. */
+		orrs r4, r5							/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+		str r4, [r2]						/* Enable MPU. */
+		dsb									/* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+
+	#if ( configENABLE_MPU == 1 )
+		ldmia r1!, {r0, r2-r4}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		msr control, r3						/* Restore the CONTROL register value for the task. */
+		mov lr, r4							/* LR = r4. */
+		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r2]						/* Restore the task's xSecureContext. */
+		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
+		push {r1,r4}
+		bl SecureContext_LoadContext		/* Restore the secure context. */
+		pop {r1,r4}
+		mov lr, r4							/* LR = r4. */
+		lsls r2, r4, #25					/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+	#else /* configENABLE_MPU */
+		ldmia r1!, {r0, r2-r3}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		mov lr, r3							/* LR = r3. */
+		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r2]						/* Restore the task's xSecureContext. */
+		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
+		push {r1,r3}
+		bl SecureContext_LoadContext		/* Restore the secure context. */
+		pop {r1,r3}
+		mov lr, r3							/* LR = r3. */
+		lsls r2, r3, #25					/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+	#endif /* configENABLE_MPU */
+
+	restore_ns_context:
+		adds r1, r1, #16					/* Move to the high registers. */
+		ldmia r1!, {r4-r7}					/* Restore the high registers that are not automatically restored. */
+		mov r8, r4							/* r8 = r4. */
+		mov r9, r5							/* r9 = r5. */
+		mov r10, r6							/* r10 = r6. */
+		mov r11, r7							/* r11 = r7. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		subs r1, r1, #32					/* Go back to the low registers. */
+		ldmia r1!, {r4-r7}					/* Restore the low registers that are not automatically restored. */
+		bx lr
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+	movs r0, #4
+	mov r1, lr
+	tst r0, r1
+	beq stacking_used_msp
+	mrs r0, psp
+	b vPortSVCHandler_C
+	stacking_used_msp:
+		mrs r0, msp
+		b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+vPortFreeSecureContext:
+	ldr r1, [r0]							/* The first item in the TCB is the top of the stack. */
+	ldr r0, [r1]							/* The first item on the stack is the task's xSecureContext. */
+	cmp r0, #0								/* Raise svc if task's xSecureContext is not NULL. */
+	beq free_secure_context
+	bx lr									/* There is no secure context (xSecureContext is NULL). */
+	free_secure_context:
+		svc 1								/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
+		bx lr								/* Return. */
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
new file mode 100644
index 0000000..969c563
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M23"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s
new file mode 100644
index 0000000..b84c356
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s
@@ -0,0 +1,303 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	EXTERN pxCurrentTCB
+	EXTERN vTaskSwitchContext
+	EXTERN vPortSVCHandler_C
+
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
+	PUBLIC vRestoreContextOfFirstTask
+	PUBLIC vRaisePrivilege
+	PUBLIC vStartFirstTask
+	PUBLIC ulSetInterruptMaskFromISR
+	PUBLIC vClearInterruptMaskFromISR
+	PUBLIC PendSV_Handler
+	PUBLIC SVC_Handler
+
+#if ( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+	mrs r0, control							/* r0 = CONTROL. */
+	movs r1, #1								/* r1 = 1. */
+	tst r0, r1								/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+	beq running_privileged					/* If the result of previous AND operation was 0, branch. */
+	movs r0, #0								/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	bx lr									/* Return. */
+	running_privileged:
+		movs r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+		bx lr								/* Return. */
+
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+	mrs r0, control							/* r0 = CONTROL. */
+	movs r1, #1								/* r1 = 1. */
+	orrs r0, r1								/* r0 = r0 | r1. */
+	msr control, r0							/* CONTROL = r0. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION privileged_functions:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr  r1, [r2]							/* Read pxCurrentTCB. */
+	ldr  r0, [r1]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
+	movs r4, #1								/* r4 = 1. */
+	bics r3, r4								/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+	str r3, [r2]							/* Disable MPU. */
+
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	ldr  r4, [r1]							/* r4 = *r1 i.e. r4 = MAIR0. */
+	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str  r4, [r2]							/* Program MAIR0. */
+	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	movs r4, #4								/* r4 = 4. */
+	str  r4, [r2]							/* Program RNR = 4. */
+	ldmia r1!, {r5,r6}						/* Read first set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write first set of RBAR/RLAR registers. */
+	movs r4, #5								/* r4 = 5. */
+	str  r4, [r2]							/* Program RNR = 5. */
+	ldmia r1!, {r5,r6}						/* Read second set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write second set of RBAR/RLAR registers. */
+	movs r4, #6								/* r4 = 6. */
+	str  r4, [r2]							/* Program RNR = 6. */
+	ldmia r1!, {r5,r6}						/* Read third set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write third set of RBAR/RLAR registers. */
+	movs r4, #7								/* r4 = 7. */
+	str  r4, [r2]							/* Program RNR = 7. */
+	ldmia r1!, {r5,r6}						/* Read fourth set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write fourth set of RBAR/RLAR registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
+	movs r4, #1								/* r4 = 1. */
+	orrs r3, r4								/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+	str r3, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldm  r0!, {r1-r3}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+	msr  psplim, r1							/* Set this task's PSPLIM value. */
+	msr  control, r2						/* Set this task's CONTROL value. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r3									/* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+	ldm  r0!, {r1-r2}						/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+	msr  psplim, r1							/* Set this task's PSPLIM value. */
+	movs r1, #2								/* r1 = 2. */
+	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r2									/* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+	mrs  r0, control						/* Read the CONTROL register. */
+	movs r1, #1								/* r1 = 1. */
+	bics r0, r1								/* Clear the bit 0. */
+	msr  control, r0						/* Write back the new CONTROL value. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
+	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
+	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
+	msr msp, r0								/* Set the MSP back to the start of the stack. */
+	cpsie i									/* Globally enable interrupts. */
+	dsb
+	isb
+	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+	nop
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMaskFromISR:
+	mrs r0, PRIMASK
+	cpsid i
+	bx lr
+/*-----------------------------------------------------------*/
+
+vClearInterruptMaskFromISR:
+	msr PRIMASK, r0
+	bx lr
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+	mrs r0, psp								/* Read PSP in r0. */
+	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r1, [r2]							/* Read pxCurrentTCB. */
+#if ( configENABLE_MPU == 1 )
+	subs r0, r0, #44						/* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+	str r0, [r1]							/* Save the new top of stack in TCB. */
+	mrs r1, psplim							/* r1 = PSPLIM. */
+	mrs r2, control							/* r2 = CONTROL. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmia r0!, {r1-r7}						/* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */
+	mov r4, r8								/* r4 = r8. */
+	mov r5, r9								/* r5 = r9. */
+	mov r6, r10								/* r6 = r10. */
+	mov r7, r11								/* r7 = r11. */
+	stmia r0!, {r4-r7}						/* Store the high registers that are not saved automatically. */
+#else /* configENABLE_MPU */
+	subs r0, r0, #40						/* Make space for PSPLIM, LR and the remaining registers on the stack. */
+	str r0, [r1]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmia r0!, {r2-r7}						/* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
+	mov r4, r8								/* r4 = r8. */
+	mov r5, r9								/* r5 = r9. */
+	mov r6, r10								/* r6 = r10. */
+	mov r7, r11								/* r7 = r11. */
+	stmia r0!, {r4-r7}						/* Store the high registers that are not saved automatically. */
+#endif /* configENABLE_MPU */
+
+	cpsid i
+	bl vTaskSwitchContext
+	cpsie i
+
+	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r1, [r2]							/* Read pxCurrentTCB. */
+	ldr r0, [r1]							/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
+	movs r4, #1								/* r4 = 1. */
+	bics r3, r4								/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+	str r3, [r2]							/* Disable MPU. */
+
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	ldr  r4, [r1]							/* r4 = *r1 i.e. r4 = MAIR0. */
+	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str  r4, [r2]							/* Program MAIR0. */
+	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	movs r4, #4								/* r4 = 4. */
+	str  r4, [r2]							/* Program RNR = 4. */
+	ldmia r1!, {r5,r6}						/* Read first set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write first set of RBAR/RLAR registers. */
+	movs r4, #5								/* r4 = 5. */
+	str  r4, [r2]							/* Program RNR = 5. */
+	ldmia r1!, {r5,r6}						/* Read second set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write second set of RBAR/RLAR registers. */
+	movs r4, #6								/* r4 = 6. */
+	str  r4, [r2]							/* Program RNR = 6. */
+	ldmia r1!, {r5,r6}						/* Read third set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write third set of RBAR/RLAR registers. */
+	movs r4, #7								/* r4 = 7. */
+	str  r4, [r2]							/* Program RNR = 7. */
+	ldmia r1!, {r5,r6}						/* Read fourth set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write fourth set of RBAR/RLAR registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
+	movs r4, #1								/* r4 = 1. */
+	orrs r3, r4								/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+	str r3, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	adds r0, r0, #28						/* Move to the high registers. */
+	ldmia r0!, {r4-r7}						/* Restore the high registers that are not automatically restored. */
+	mov r8, r4								/* r8 = r4. */
+	mov r9, r5								/* r9 = r5. */
+	mov r10, r6								/* r10 = r6. */
+	mov r11, r7								/* r11 = r7. */
+	msr psp, r0								/* Remember the new top of stack for the task. */
+	subs r0, r0, #44						/* Move to the starting of the saved context. */
+	ldmia r0!, {r1-r7}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */
+	msr psplim, r1							/* Restore the PSPLIM register value for the task. */
+	msr control, r2							/* Restore the CONTROL register value for the task. */
+	bx r3
+#else /* configENABLE_MPU */
+	adds r0, r0, #24						/* Move to the high registers. */
+	ldmia r0!, {r4-r7}						/* Restore the high registers that are not automatically restored. */
+	mov r8, r4								/* r8 = r4. */
+	mov r9, r5								/* r9 = r5. */
+	mov r10, r6								/* r10 = r6. */
+	mov r11, r7								/* r11 = r7. */
+	msr psp, r0								/* Remember the new top of stack for the task. */
+	subs r0, r0, #40						/* Move to the starting of the saved context. */
+	ldmia r0!, {r2-r7}						/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
+	msr psplim, r2							/* Restore the PSPLIM register value for the task. */
+	bx r3
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+	movs r0, #4
+	mov r1, lr
+	tst r0, r1
+	beq stacking_used_msp
+	mrs r0, psp
+	b vPortSVCHandler_C
+	stacking_used_msp:
+		mrs r0, msp
+		b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
new file mode 100644
index 0000000..969c563
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M23"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
new file mode 100644
index 0000000..8d9bcc9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
@@ -0,0 +1,326 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	EXTERN pxCurrentTCB
+	EXTERN xSecureContext
+	EXTERN vTaskSwitchContext
+	EXTERN vPortSVCHandler_C
+	EXTERN SecureContext_SaveContext
+	EXTERN SecureContext_LoadContext
+
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
+	PUBLIC vPortAllocateSecureContext
+	PUBLIC vRestoreContextOfFirstTask
+	PUBLIC vRaisePrivilege
+	PUBLIC vStartFirstTask
+	PUBLIC ulSetInterruptMaskFromISR
+	PUBLIC vClearInterruptMaskFromISR
+	PUBLIC PendSV_Handler
+	PUBLIC SVC_Handler
+	PUBLIC vPortFreeSecureContext
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+	mrs r0, control							/* r0 = CONTROL. */
+	tst r0, #1								/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	ite ne
+	movne r0, #0							/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	moveq r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+	mrs r0, control							/* r0 = CONTROL. */
+	orr r0, r0, #1							/* r0 = r0 | 1. */
+	msr control, r0							/* CONTROL = r0. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vPortAllocateSecureContext:
+	svc 0									/* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION privileged_functions:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr  r3, [r2]							/* Read pxCurrentTCB. */
+	ldr  r0, [r3]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	str r4, [r2]							/* Disable MPU. */
+
+	adds r3, #4								/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+	ldr  r4, [r3]							/* r4 = *r3 i.e. r4 = MAIR0. */
+	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str  r4, [r2]							/* Program MAIR0. */
+	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+	movs r4, #4								/* r4 = 4. */
+	str  r4, [r2]							/* Program RNR = 4. */
+	adds r3, #4								/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+	ldr  r2, =0xe000ed9c					/* r2 = 0xe000ed9c [Location of RBAR]. */
+	ldmia r3!, {r4-r11}						/* Read 4 set of RBAR/RLAR registers from TCB. */
+	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	str r4, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldm  r0!, {r1-r4}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+	ldr  r5, =xSecureContext
+	str  r1, [r5]							/* Set xSecureContext to this task's value for the same. */
+	msr  psplim, r2							/* Set this task's PSPLIM value. */
+	msr  control, r3						/* Set this task's CONTROL value. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r4									/* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+	ldm  r0!, {r1-r3}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+	ldr  r4, =xSecureContext
+	str  r1, [r4]							/* Set xSecureContext to this task's value for the same. */
+	msr  psplim, r2							/* Set this task's PSPLIM value. */
+	movs r1, #2								/* r1 = 2. */
+	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r3									/* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+	mrs  r0, control						/* Read the CONTROL register. */
+	bic r0, r0, #1							/* Clear the bit 0. */
+	msr  control, r0						/* Write back the new CONTROL value. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
+	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
+	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
+	msr msp, r0								/* Set the MSP back to the start of the stack. */
+	cpsie i									/* Globally enable interrupts. */
+	cpsie f
+	dsb
+	isb
+	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMaskFromISR:
+	mrs r0, PRIMASK
+	cpsid i
+	bx lr
+/*-----------------------------------------------------------*/
+
+vClearInterruptMaskFromISR:
+	msr PRIMASK, r0
+	bx lr
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+	mrs r1, psp								/* Read PSP in r1. */
+	ldr r2, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	ldr r0, [r2]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+
+	cbz r0, save_ns_context					/* No secure context to save. */
+	push {r0-r2, r14}
+	bl SecureContext_SaveContext
+	pop {r0-r3}								/* LR is now in r3. */
+	mov lr, r3								/* LR = r3. */
+	lsls r2, r3, #25						/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	bpl save_ns_context						/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r2, [r3]							/* Read pxCurrentTCB. */
+#if ( configENABLE_MPU == 1 )
+	subs r1, r1, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	str r1, [r2]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mrs r3, control							/* r3 = CONTROL. */
+	mov r4, lr								/* r4 = LR/EXC_RETURN. */
+	stmia r1!, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+#else /* configENABLE_MPU */
+	subs r1, r1, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+	str r1, [r2]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmia r1!, {r0, r2-r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
+#endif /* configENABLE_MPU */
+	b select_next_task
+
+	save_ns_context:
+		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r2, [r3]						/* Read pxCurrentTCB. */
+	#if ( configENABLE_FPU == 1 )
+		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+		it eq
+		vstmdbeq r1!, {s16-s31}				/* Store the FPU registers which are not saved automatically. */
+	#endif /* configENABLE_FPU */
+	#if ( configENABLE_MPU == 1 )
+		subs r1, r1, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+		str r1, [r2]						/* Save the new top of stack in TCB. */
+		adds r1, r1, #16					/* r1 = r1 + 16. */
+		stm r1, {r4-r11}					/* Store the registers that are not saved automatically. */
+		mrs r2, psplim						/* r2 = PSPLIM. */
+		mrs r3, control						/* r3 = CONTROL. */
+		mov r4, lr							/* r4 = LR/EXC_RETURN. */
+		subs r1, r1, #16					/* r1 = r1 - 16. */
+		stm r1, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	#else /* configENABLE_MPU */
+		subs r1, r1, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+		str r1, [r2]						/* Save the new top of stack in TCB. */
+		adds r1, r1, #12					/* r1 = r1 + 12. */
+		stm r1, {r4-r11}					/* Store the registers that are not saved automatically. */
+		mrs r2, psplim						/* r2 = PSPLIM. */
+		mov r3, lr							/* r3 = LR/EXC_RETURN. */
+		subs r1, r1, #12					/* r1 = r1 - 12. */
+		stmia r1!, {r0, r2-r3}				/* Store xSecureContext, PSPLIM and LR on the stack. */
+	#endif /* configENABLE_MPU */
+
+	select_next_task:
+		cpsid i
+		bl vTaskSwitchContext
+		cpsie i
+
+		ldr r2, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r3, [r2]						/* Read pxCurrentTCB. */
+		ldr r1, [r3]						/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+
+	#if ( configENABLE_MPU == 1 )
+		dmb									/* Complete outstanding transfers before disabling MPU. */
+		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		bic r4, r4, #1						/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+		str r4, [r2]						/* Disable MPU. */
+
+		adds r3, #4							/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+		ldr r4, [r3]						/* r4 = *r3 i.e. r4 = MAIR0. */
+		ldr r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+		str r4, [r2]						/* Program MAIR0. */
+		ldr r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+		movs r4, #4							/* r4 = 4. */
+		str r4, [r2]						/* Program RNR = 4. */
+		adds r3, #4							/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+		ldr  r2, =0xe000ed9c				/* r2 = 0xe000ed9c [Location of RBAR]. */
+		ldmia r3!, {r4-r11}					/* Read 4 sets of RBAR/RLAR registers from TCB. */
+		stmia r2!, {r4-r11}					/* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		orr r4, r4, #1						/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+		str r4, [r2]						/* Enable MPU. */
+		dsb									/* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+
+	#if ( configENABLE_MPU == 1 )
+		ldmia r1!, {r0, r2-r4}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		msr control, r3						/* Restore the CONTROL register value for the task. */
+		mov lr, r4							/* LR = r4. */
+		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r2]						/* Restore the task's xSecureContext. */
+		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
+		push {r1,r4}
+		bl SecureContext_LoadContext		/* Restore the secure context. */
+		pop {r1,r4}
+		mov lr, r4							/* LR = r4. */
+		lsls r2, r4, #25					/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+	#else /* configENABLE_MPU */
+		ldmia r1!, {r0, r2-r3}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		mov lr, r3							/* LR = r3. */
+		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r2]						/* Restore the task's xSecureContext. */
+		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
+		push {r1,r3}
+		bl SecureContext_LoadContext		/* Restore the secure context. */
+		pop {r1,r3}
+		mov lr, r3							/* LR = r3. */
+		lsls r2, r3, #25					/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+	#endif /* configENABLE_MPU */
+
+	restore_ns_context:
+		ldmia r1!, {r4-r11}					/* Restore the registers that are not automatically restored. */
+	#if ( configENABLE_FPU == 1 )
+		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+		it eq
+		vldmiaeq r1!, {s16-s31}				/* Restore the FPU registers which are not restored automatically. */
+	#endif /* configENABLE_FPU */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+	tst lr, #4
+	ite eq
+	mrseq r0, msp
+	mrsne r0, psp
+	b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+vPortFreeSecureContext:
+	/* r0 = uint32_t *pulTCB. */
+	ldr r1, [r0]							/* The first item in the TCB is the top of the stack. */
+	ldr r0, [r1]							/* The first item on the stack is the task's xSecureContext. */
+	cmp r0, #0								/* Raise svc if task's xSecureContext is not NULL. */
+	it ne
+	svcne 1									/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
new file mode 100644
index 0000000..c09b3ce
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M33"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
new file mode 100644
index 0000000..31623f2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
@@ -0,0 +1,242 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	EXTERN pxCurrentTCB
+	EXTERN vTaskSwitchContext
+	EXTERN vPortSVCHandler_C
+
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
+	PUBLIC vRestoreContextOfFirstTask
+	PUBLIC vRaisePrivilege
+	PUBLIC vStartFirstTask
+	PUBLIC ulSetInterruptMaskFromISR
+	PUBLIC vClearInterruptMaskFromISR
+	PUBLIC PendSV_Handler
+	PUBLIC SVC_Handler
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+	mrs r0, control							/* r0 = CONTROL. */
+	tst r0, #1								/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	ite ne
+	movne r0, #0							/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	moveq r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+	mrs r0, control							/* r0 = CONTROL. */
+	orr r0, r0, #1							/* r0 = r0 | 1. */
+	msr control, r0							/* CONTROL = r0. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION privileged_functions:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr  r1, [r2]							/* Read pxCurrentTCB. */
+	ldr  r0, [r1]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	str r4, [r2]							/* Disable MPU. */
+
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	ldr r3, [r1]							/* r3 = *r1 i.e. r3 = MAIR0. */
+	ldr r2, =0xe000edc0						/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str r3, [r2]							/* Program MAIR0. */
+	ldr r2, =0xe000ed98						/* r2 = 0xe000ed98 [Location of RNR]. */
+	movs r3, #4								/* r3 = 4. */
+	str r3, [r2]							/* Program RNR = 4. */
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	ldr r2, =0xe000ed9c						/* r2 = 0xe000ed9c [Location of RBAR]. */
+	ldmia r1!, {r4-r11}						/* Read 4 sets of RBAR/RLAR registers from TCB. */
+	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	str r4, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldm  r0!, {r1-r3}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+	msr  psplim, r1							/* Set this task's PSPLIM value. */
+	msr  control, r2						/* Set this task's CONTROL value. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r3									/* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+	ldm  r0!, {r1-r2}						/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+	msr  psplim, r1							/* Set this task's PSPLIM value. */
+	movs r1, #2								/* r1 = 2. */
+	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r2									/* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+	mrs  r0, control						/* Read the CONTROL register. */
+	bic r0, r0, #1							/* Clear the bit 0. */
+	msr  control, r0						/* Write back the new CONTROL value. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
+	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
+	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
+	msr msp, r0								/* Set the MSP back to the start of the stack. */
+	cpsie i									/* Globally enable interrupts. */
+	cpsie f
+	dsb
+	isb
+	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMaskFromISR:
+	mrs r0, PRIMASK
+	cpsid i
+	bx lr
+/*-----------------------------------------------------------*/
+
+vClearInterruptMaskFromISR:
+	msr PRIMASK, r0
+	bx lr
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+	mrs r0, psp								/* Read PSP in r0. */
+#if ( configENABLE_FPU == 1 )
+	tst lr, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+	it eq
+	vstmdbeq r0!, {s16-s31}					/* Store the FPU registers which are not saved automatically. */
+#endif /* configENABLE_FPU */
+#if ( configENABLE_MPU == 1 )
+	mrs r1, psplim							/* r1 = PSPLIM. */
+	mrs r2, control							/* r2 = CONTROL. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmdb r0!, {r1-r11}						/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
+#else /* configENABLE_MPU */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmdb r0!, {r2-r11}						/* Store on the stack - PSPLIM, LR and registers that are not automatically. */
+#endif /* configENABLE_MPU */
+
+	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r1, [r2]							/* Read pxCurrentTCB. */
+	str r0, [r1]							/* Save the new top of stack in TCB. */
+
+	cpsid i
+	bl vTaskSwitchContext
+	cpsie i
+
+	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r1, [r2]							/* Read pxCurrentTCB. */
+	ldr r0, [r1]							/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	str r4, [r2]							/* Disable MPU. */
+
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	ldr r3, [r1]							/* r3 = *r1 i.e. r3 = MAIR0. */
+	ldr r2, =0xe000edc0						/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str r3, [r2]							/* Program MAIR0. */
+	ldr r2, =0xe000ed98						/* r2 = 0xe000ed98 [Location of RNR]. */
+	movs r3, #4								/* r3 = 4. */
+	str r3, [r2]							/* Program RNR = 4. */
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	ldr r2, =0xe000ed9c						/* r2 = 0xe000ed9c [Location of RBAR]. */
+	ldmia r1!, {r4-r11}						/* Read 4 sets of RBAR/RLAR registers from TCB. */
+	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	str r4, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldmia r0!, {r1-r11}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
+#else /* configENABLE_MPU */
+	ldmia r0!, {r2-r11}						/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_FPU == 1 )
+	tst r3, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+	it eq
+	vldmiaeq r0!, {s16-s31}					/* Restore the FPU registers which are not restored automatically. */
+#endif /* configENABLE_FPU */
+
+ #if ( configENABLE_MPU == 1 )
+	msr psplim, r1							/* Restore the PSPLIM register value for the task. */
+	msr control, r2							/* Restore the CONTROL register value for the task. */
+#else /* configENABLE_MPU */
+	msr psplim, r2							/* Restore the PSPLIM register value for the task. */
+#endif /* configENABLE_MPU */
+	msr psp, r0								/* Remember the new top of stack for the task. */
+	bx r3
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+	tst lr, #4
+	ite eq
+	mrseq r0, msp
+	mrsne r0, psp
+	b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
new file mode 100644
index 0000000..c09b3ce
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M33"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portasm.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portasm.h
new file mode 100644
index 0000000..6314e96
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/ReadMe.txt b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/ReadMe.txt
new file mode 100644
index 0000000..0bb046a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/ReadMe.txt
@@ -0,0 +1,10 @@
+This directory tree contains the master copy of the FreeeRTOS Cortex-M33 port.
+Do not use the files located here!  These file are copied into separate
+FreeRTOS/Source/portable/[compiler]/ARM_CM33_NNN directories prior to each
+FreeRTOS release.
+
+If your Cortex-M33 application uses TrustZone then use the files from the
+FreeRTOS/Source/portable/[compiler]/ARM_CM33 directories.
+
+If your Cortex-M33 application does not use TrustZone then use the files from
+the FreeRTOS/Source/portable/[compiler]/ARM_CM33_NTZ directories.
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c
new file mode 100644
index 0000000..4e63dd3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c
@@ -0,0 +1,91 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+#if( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+	/* xSecureContextHandle value is in r0. */
+	__asm volatile
+	(
+	"	.syntax unified							\n"
+	"											\n"
+	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
+	"	cbz r1, load_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
+	"	ldmia r0!, {r1, r2}						\n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+	#if( configENABLE_MPU == 1 )
+	"	ldmia r1!, {r3}							\n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
+	"	msr control, r3							\n" /* CONTROL = r3. */
+	#endif /* configENABLE_MPU */
+	"	msr psplim, r2							\n" /* PSPLIM = r2. */
+	"	msr psp, r1								\n" /* PSP = r1. */
+	"											\n"
+	" load_ctx_therad_mode:						\n"
+	"	nop										\n"
+	"											\n"
+	:::"r0", "r1", "r2"
+	);
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+	/* xSecureContextHandle value is in r0. */
+	__asm volatile
+	(
+	"	.syntax unified							\n"
+	"											\n"
+	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
+	"	cbz r1, save_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
+	"	mrs r1, psp								\n" /* r1 = PSP. */
+	#if( configENABLE_MPU == 1 )
+	"	mrs r2, control							\n" /* r2 = CONTROL. */
+	"	subs r1, r1, #4							\n" /* Make space for the CONTROL value on the stack. */
+	"	str r1, [r0]							\n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+	"	stmia r1!, {r2}							\n" /* Store CONTROL value on the stack. */
+	#else /* configENABLE_MPU */
+	"	str r1, [r0]							\n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+	#endif /* configENABLE_MPU */
+	"	movs r1, %0								\n" /* r1 = securecontextNO_STACK. */
+	"	msr psplim, r1							\n" /* PSPLIM = securecontextNO_STACK. */
+	"	msr psp, r1								\n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+	"											\n"
+	" save_ctx_therad_mode:						\n"
+	"	nop										\n"
+	"											\n"
+	:: "i" ( securecontextNO_STACK ) : "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c
new file mode 100644
index 0000000..245adff
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c
@@ -0,0 +1,88 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+	/* xSecureContextHandle value is in r0. */
+	__asm volatile
+	(
+	"	.syntax unified							\n"
+	"											\n"
+	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
+	"	cbz r1, load_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
+	"	ldmia r0!, {r1, r2}						\n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+	#if( configENABLE_MPU == 1 )
+	"	ldmia r1!, {r3}							\n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
+	"	msr control, r3							\n" /* CONTROL = r3. */
+	#endif /* configENABLE_MPU */
+	"	msr psplim, r2							\n" /* PSPLIM = r2. */
+	"	msr psp, r1								\n" /* PSP = r1. */
+	"											\n"
+	" load_ctx_therad_mode:						\n"
+	"	nop										\n"
+	"											\n"
+	:::"r0", "r1", "r2"
+	);
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+	/* xSecureContextHandle value is in r0. */
+	__asm volatile
+	(
+	"	.syntax unified							\n"
+	"											\n"
+	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
+	"	cbz r1, save_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
+	"	mrs r1, psp								\n" /* r1 = PSP. */
+	#if( configENABLE_FPU == 1 )
+	"	vstmdb r1!, {s0}						\n" /* Trigger the defferred stacking of FPU registers. */
+	"	vldmia r1!, {s0}						\n" /* Nullify the effect of the pervious statement. */
+	#endif /* configENABLE_FPU */
+	#if( configENABLE_MPU == 1 )
+	"	mrs r2, control							\n" /* r2 = CONTROL. */
+	"	stmdb r1!, {r2}							\n" /* Store CONTROL value on the stack. */
+	#endif /* configENABLE_MPU */
+	"	str r1, [r0]							\n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+	"	movs r1, %0								\n" /* r1 = securecontextNO_STACK. */
+	"	msr psplim, r1							\n" /* PSPLIM = securecontextNO_STACK. */
+	"	msr psp, r1								\n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+	"											\n"
+	" save_ctx_therad_mode:						\n"
+	"	nop										\n"
+	"											\n"
+	:: "i" ( securecontextNO_STACK ) : "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port.c
new file mode 100644
index 0000000..6df620d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port.c
@@ -0,0 +1,48 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/* Functions implemented in assembler file. */
+extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );
+extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+	SecureContext_LoadContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+	SecureContext_SaveContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s
new file mode 100644
index 0000000..947e70a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s
@@ -0,0 +1,76 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+
+	PUBLIC SecureContext_LoadContextAsm
+	PUBLIC SecureContext_SaveContextAsm
+
+#if ( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+/*-----------------------------------------------------------*/
+
+SecureContext_LoadContextAsm:
+	/* xSecureContextHandle value is in r0. */
+	mrs r1, ipsr							/* r1 = IPSR. */
+	cbz r1, load_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
+	ldmia r0!, {r1, r2}						/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+#if ( configENABLE_MPU == 1 )
+	ldmia r1!, {r3}							/* Read CONTROL register value from task's stack. r3 = CONTROL. */
+	msr control, r3							/* CONTROL = r3. */
+#endif /* configENABLE_MPU */
+	msr psplim, r2							/* PSPLIM = r2. */
+	msr psp, r1								/* PSP = r1. */
+
+	load_ctx_therad_mode:
+		bx lr
+/*-----------------------------------------------------------*/
+
+SecureContext_SaveContextAsm:
+	/* xSecureContextHandle value is in r0. */
+	mrs r1, ipsr							/* r1 = IPSR. */
+	cbz r1, save_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
+	mrs r1, psp								/* r1 = PSP. */
+#if ( configENABLE_MPU == 1 )
+	mrs r2, control							/* r2 = CONTROL. */
+	subs r1, r1, #4							/* Make space for the CONTROL value on the stack. */
+	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+	stmia r1!, {r2}							/* Store CONTROL value on the stack. */
+#else /* configENABLE_MPU */
+	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+#endif /* configENABLE_MPU */
+	movs r1, #0								/* r1 = securecontextNO_STACK. */
+	msr psplim, r1							/* PSPLIM = securecontextNO_STACK. */
+	msr psp, r1								/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+
+	save_ctx_therad_mode:
+		bx lr
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port.c
new file mode 100644
index 0000000..6df620d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port.c
@@ -0,0 +1,48 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/* Functions implemented in assembler file. */
+extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );
+extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+	SecureContext_LoadContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+	SecureContext_SaveContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s
new file mode 100644
index 0000000..759a21f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s
@@ -0,0 +1,73 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+
+	PUBLIC SecureContext_LoadContextAsm
+	PUBLIC SecureContext_SaveContextAsm
+/*-----------------------------------------------------------*/
+
+SecureContext_LoadContextAsm:
+	/* xSecureContextHandle value is in r0. */
+	mrs r1, ipsr							/* r1 = IPSR. */
+	cbz r1, load_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
+	ldmia r0!, {r1, r2}						/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+#if ( configENABLE_MPU == 1 )
+	ldmia r1!, {r3}							/* Read CONTROL register value from task's stack. r3 = CONTROL. */
+	msr control, r3							/* CONTROL = r3. */
+#endif /* configENABLE_MPU */
+	msr psplim, r2							/* PSPLIM = r2. */
+	msr psp, r1								/* PSP = r1. */
+
+	load_ctx_therad_mode:
+		bx lr
+/*-----------------------------------------------------------*/
+
+SecureContext_SaveContextAsm:
+	/* xSecureContextHandle value is in r0. */
+	mrs r1, ipsr							/* r1 = IPSR. */
+	cbz r1, save_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
+	mrs r1, psp								/* r1 = PSP. */
+#if ( configENABLE_FPU == 1 )
+	vstmdb r1!, {s0}						/* Trigger the defferred stacking of FPU registers. */
+	vldmia r1!, {s0}						/* Nullify the effect of the pervious statement. */
+#endif /* configENABLE_FPU */
+#if ( configENABLE_MPU == 1 )
+	mrs r2, control							/* r2 = CONTROL. */
+	stmdb r1!, {r2}							/* Store CONTROL value on the stack. */
+#endif /* configENABLE_MPU */
+	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+	movs r1, #0								/* r1 = securecontextNO_STACK. */
+	msr psplim, r1							/* PSPLIM = securecontextNO_STACK. */
+	msr psp, r1								/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+
+	save_ctx_therad_mode:
+		bx lr
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/secure_context.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/secure_context.c
new file mode 100644
index 0000000..8a42230
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/secure_context.c
@@ -0,0 +1,204 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED		0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED		0x03
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first addess of the allocated memory.
+ */
+typedef struct SecureContext
+{
+	uint8_t *pucCurrentStackPointer;	/**< Current value of stack pointer (PSP). */
+	uint8_t *pucStackLimit;				/**< Last location of the stack memory (PSPLIM). */
+	uint8_t *pucStackStart;				/**< First location of the stack memory. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+	uint32_t ulIPSR;
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* No stack for thread mode until a task's context is loaded. */
+		secureportSET_PSPLIM( securecontextNO_STACK );
+		secureportSET_PSP( securecontextNO_STACK );
+
+		#if( configENABLE_MPU == 1 )
+		{
+			/* Configure thread mode to use PSP and to be unprivileged. */
+			secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+		}
+		#else /* configENABLE_MPU */
+		{
+			/* Configure thread mode to use PSP and to be privileged.. */
+			secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+		}
+		#endif /* configENABLE_MPU */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
+#else /* configENABLE_MPU */
+	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
+#endif /* configENABLE_MPU */
+{
+	uint8_t *pucStackMemory = NULL;
+	uint32_t ulIPSR;
+	SecureContextHandle_t xSecureContextHandle = NULL;
+	#if( configENABLE_MPU == 1 )
+		uint32_t *pulCurrentStackPointer = NULL;
+	#endif /* configENABLE_MPU */
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* Allocate the context structure. */
+		xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
+
+		if( xSecureContextHandle != NULL )
+		{
+			/* Allocate the stack space. */
+			pucStackMemory = pvPortMalloc( ulSecureStackSize );
+
+			if( pucStackMemory != NULL )
+			{
+				/* Since stack grows down, the starting point will be the last
+				 * location. Note that this location is next to the last
+				 * allocated byte because the hardware decrements the stack
+				 * pointer before writing i.e. if stack pointer is 0x2, a push
+				 * operation will decrement the stack pointer to 0x1 and then
+				 * write at 0x1. */
+				xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
+
+				/* The stack cannot go beyond this location. This value is
+				 * programmed in the PSPLIM register on context switch.*/
+				xSecureContextHandle->pucStackLimit = pucStackMemory;
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Store the correct CONTROL value for the task on the stack.
+					 * This value is programmed in the CONTROL register on
+					 * context switch. */
+					pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
+					pulCurrentStackPointer--;
+					if( ulIsTaskPrivileged )
+					{
+						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+					}
+					else
+					{
+						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+					}
+
+					/* Store the current stack pointer. This value is programmed in
+					 * the PSP register on context switch. */
+					xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+				}
+				#else /* configENABLE_MPU */
+				{
+					/* Current SP is set to the starting of the stack. This
+					 * value programmed in the PSP register on context switch. */
+					xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
+
+				}
+				#endif /* configENABLE_MPU */
+			}
+			else
+			{
+				/* Free the context to avoid memory leak and make sure to return
+				 * NULL to indicate failure. */
+				vPortFree( xSecureContextHandle );
+				xSecureContextHandle = NULL;
+			}
+		}
+	}
+
+	return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
+{
+	uint32_t ulIPSR;
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* Ensure that valid parameters are passed. */
+		secureportASSERT( xSecureContextHandle != NULL );
+
+		/* Free the stack space. */
+		vPortFree( xSecureContextHandle->pucStackLimit );
+
+		/* Free the context itself. */
+		vPortFree( xSecureContextHandle );
+	}
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/secure_context.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/secure_context.h
new file mode 100644
index 0000000..a98a7d0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/context/secure_context.h
@@ -0,0 +1,111 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include 
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no task's context is loaded.
+ */
+#define securecontextNO_STACK	0x0
+
+/**
+ * @brief Opaque handle.
+ */
+struct SecureContext;
+typedef struct SecureContext*	SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if( configENABLE_MPU == 1 )
+	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
+#else /* configENABLE_MPU */
+	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/heap/secure_heap.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/heap/secure_heap.c
new file mode 100644
index 0000000..c4f613f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/heap/secure_heap.c
@@ -0,0 +1,450 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#define secureconfigTOTAL_HEAP_SIZE		( ( ( size_t ) ( 10 * 1024 ) ) )
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+	#define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+	#define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+	#define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE			( ( size_t ) 8 )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+	/* The application writer has already defined the array used for the RTOS
+	 * heap - probably so it can be placed in a special segment or address. */
+	extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+	static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/**< The next free block in the list. */
+	size_t xBlockSize;						/**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/**
+ * @brief Gets set to the top bit of an size_t type.
+ *
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set
+ * then the block belongs to the application. When the bit is free the block is
+ * still part of the free heap space.
+ */
+static size_t xBlockAllocatedBit = 0;
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	uxAddress = ( size_t ) ucHeap;
+
+	if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+	{
+		uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+		uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+	}
+
+	pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	 * blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+	xStart.xBlockSize = ( size_t ) 0;
+
+	/* pxEnd is used to mark the end of the list of free blocks and is inserted
+	 * at the end of the heap space. */
+	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+	uxAddress -= xHeapStructSize;
+	uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+	pxEnd = ( void * ) uxAddress;
+	pxEnd->xBlockSize = 0;
+	pxEnd->pxNextFreeBlock = NULL;
+
+	/* To start with there is a single free block that is sized to take up the
+	 * entire heap space, minus the space taken by pxEnd. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+	/* Only one block exists - and it covers the entire usable heap space. */
+	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	 * than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+	{
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	 * make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+		pxBlockToInsert = pxIterator;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	 * make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+	}
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	 * before and the block after, then it's pxNextFreeBlock pointer will have
+	 * already been set, and should not be set here as that would make it point
+	 * to itself. */
+	if( pxIterator != pxBlockToInsert )
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+	/* If this is the first call to malloc then the heap will require
+	 * initialisation to setup the list of free blocks. */
+	if( pxEnd == NULL )
+	{
+		prvHeapInit();
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Check the requested block size is not so large that the top bit is set.
+	 * The top bit of the block size member of the BlockLink_t structure is used
+	 * to determine who owns the block - the application or the kernel, so it
+	 * must be free. */
+	if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+	{
+		/* The wanted size is increased so it can contain a BlockLink_t
+		 * structure in addition to the requested amount of bytes. */
+		if( xWantedSize > 0 )
+		{
+			xWantedSize += xHeapStructSize;
+
+			/* Ensure that blocks are always aligned to the required number of
+			 * bytes. */
+			if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+			{
+				/* Byte alignment required. */
+				xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+				secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+		{
+			/* Traverse the list from the start (lowest address) block until
+			 * one of adequate size is found. */
+			pxPreviousBlock = &xStart;
+			pxBlock = xStart.pxNextFreeBlock;
+			while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+			{
+				pxPreviousBlock = pxBlock;
+				pxBlock = pxBlock->pxNextFreeBlock;
+			}
+
+			/* If the end marker was reached then a block of adequate size was
+			 * not found. */
+			if( pxBlock != pxEnd )
+			{
+				/* Return the memory space pointed to - jumping over the
+				 * BlockLink_t structure at its start. */
+				pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+				/* This block is being returned for use so must be taken out
+				 * of the list of free blocks. */
+				pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+				/* If the block is larger than required it can be split into
+				 * two. */
+				if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+				{
+					/* This block is to be split into two.  Create a new
+					 * block following the number of bytes requested. The void
+					 * cast is used to prevent byte alignment warnings from the
+					 * compiler. */
+					pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+					secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+					/* Calculate the sizes of two blocks split from the single
+					 * block. */
+					pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+					pxBlock->xBlockSize = xWantedSize;
+
+					/* Insert the new block into the list of free blocks. */
+					prvInsertBlockIntoFreeList( pxNewBlockLink );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+				if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+				{
+					xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* The block is being returned - it is allocated and owned by
+				 * the application and has no "next" block. */
+				pxBlock->xBlockSize |= xBlockAllocatedBit;
+				pxBlock->pxNextFreeBlock = NULL;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceMALLOC( pvReturn, xWantedSize );
+
+	#if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		 * before it. */
+		puc -= xHeapStructSize;
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+
+		/* Check the block is actually allocated. */
+		secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+		secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+			{
+				/* The block is being returned to the heap - it is no longer
+				 * allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+				secureportDISABLE_NON_SECURE_INTERRUPTS();
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+				}
+				secureportENABLE_NON_SECURE_INTERRUPTS();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+	return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/heap/secure_heap.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/heap/secure_heap.h
new file mode 100644
index 0000000..aae5cfc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/heap/secure_heap.h
@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include 
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void *pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void *pv );
+
+#endif /* __SECURE_HEAP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.c
new file mode 100644
index 0000000..60ef1e8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.c
@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR					( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS		( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK	( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS		( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK		( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR						( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS			( 29UL )
+#define secureinitFPCCR_LSPENS_MASK			( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS				( 26UL )
+#define secureinitFPCCR_TS_MASK				( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR						( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS			( 10UL )
+#define secureinitNSACR_CP10_MASK			( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS			( 11UL )
+#define secureinitNSACR_CP11_MASK			( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+	uint32_t ulIPSR;
+
+	 /* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		*( secureinitSCB_AIRCR ) =	( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+									( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+									( ( 0x1UL	<< secureinitSCB_AIRCR_PRIS_POS )	& secureinitSCB_AIRCR_PRIS_MASK );
+	}
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+	uint32_t ulIPSR;
+
+	 /* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+		 * permitted. CP11 should be programmed to the same value as CP10. */
+		*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+		/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+		 * that we can enable/disable lazy stacking in port.c file. */
+		*( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
+
+		/* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+		 * registers (S16-S31) are also pushed to stack on exception entry and
+		 * restored on exception return. */
+		*( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+	}
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.h
new file mode 100644
index 0000000..3954e13
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.h
@@ -0,0 +1,53 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/macros/secure_port_macros.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/macros/secure_port_macros.h
new file mode 100644
index 0000000..f392537
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ARMv8M/secure/macros/secure_port_macros.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT					8
+#define secureportBYTE_ALIGNMENT_MASK				( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+	#define secureportNON_SECURE_CALLABLE			__cmse_nonsecure_entry __root
+#else
+	#define secureportNON_SECURE_CALLABLE			__attribute__((cmse_nonsecure_entry)) __attribute__((used))
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+	__asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+	__asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+	__asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+	__asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+	__asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+	__asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+	__asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+	__asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL		0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL	1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS()		secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x )						\
+	if( ( x ) == 0 )								\
+	{												\
+		secureportDISABLE_SECURE_INTERRUPTS();		\
+		secureportDISABLE_NON_SECURE_INTERRUPTS();	\
+		for( ;; );									\
+	}
+
+#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/BCC/16BitDOS/Flsh186/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/BCC/16BitDOS/Flsh186/port.c
new file mode 100644
index 0000000..fc8cca0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/BCC/16BitDOS/Flsh186/port.c
@@ -0,0 +1,244 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V1.00:
+
+	+ Call to taskYIELD() from within tick ISR has been replaced by the more
+	  efficient portSWITCH_CONTEXT().
+	+ ISR function definitions renamed to include the prv prefix.
+
+Changes from V2.6.1
+
+	+ Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
+	  macro to be consistent with the later ports.
+*/
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the Flashlite 186
+ * port.
+ *----------------------------------------------------------*/
+
+#include 
+#include 
+#include 
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "portasm.h"
+
+/*lint -e950 Non ANSI reserved words okay in this file only. */
+
+#define portTIMER_EOI_TYPE		( 8 )
+#define portRESET_PIC()			portOUTPUT_WORD( ( uint16_t ) 0xff22, portTIMER_EOI_TYPE )
+#define portTIMER_INT_NUMBER	0x12
+
+#define portTIMER_1_CONTROL_REGISTER	( ( uint16_t ) 0xff5e )
+#define portTIMER_0_CONTROL_REGISTER	( ( uint16_t ) 0xff56 )
+#define portTIMER_INTERRUPT_ENABLE		( ( uint16_t ) 0x2000 )
+
+/* Setup the hardware to generate the required tick frequency. */
+static void prvSetTickFrequency( uint32_t ulTickRateHz );
+
+/* Set the hardware back to the state as per before the scheduler started. */
+static void prvExitFunction( void );
+
+/* The ISR used depends on whether the preemptive or cooperative scheduler
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
+	/* Tick service routine used by the scheduler when preemptive scheduling is
+	being used. */
+	static void __interrupt __far prvPreemptiveTick( void );
+#else
+	/* Tick service routine used by the scheduler when cooperative scheduling is
+	being used. */
+	static void __interrupt __far prvNonPreemptiveTick( void );
+#endif
+
+/* Trap routine used by taskYIELD() to manually cause a context switch. */
+static void __interrupt __far prvYieldProcessor( void );
+
+/*lint -e956 File scopes necessary here. */
+
+/* Set true when the vectors are set so the scheduler will service the tick. */
+static BaseType_t xSchedulerRunning = pdFALSE;
+
+/* Points to the original routine installed on the vector we use for manual
+context switches.  This is then used to restore the original routine during
+prvExitFunction(). */
+static void ( __interrupt __far *pxOldSwitchISR )();
+
+/* Used to restore the original DOS context when the scheduler is ended. */
+static jmp_buf xJumpBuf;
+
+/*lint +e956 */
+
+/*-----------------------------------------------------------*/
+BaseType_t xPortStartScheduler( void )
+{
+	/* This is called with interrupts already disabled. */
+
+	/* Remember what was on the interrupts we are going to use
+	so we can put them back later if required. */
+	pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
+
+	/* Put our manual switch (yield) function on a known
+	vector. */
+	_dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
+
+	#if( configUSE_PREEMPTION == 1 )
+	{
+		/* Put our tick switch function on the timer interrupt. */
+		_dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
+	}
+	#else
+	{
+		/* We want the timer interrupt to just increment the tick count. */
+		_dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );
+	}
+	#endif
+
+	prvSetTickFrequency( configTICK_RATE_HZ );
+
+	/* Clean up function if we want to return to DOS. */
+	if( setjmp( xJumpBuf ) != 0 )
+	{
+		prvExitFunction();
+		xSchedulerRunning = pdFALSE;
+	}
+	else
+	{
+		xSchedulerRunning = pdTRUE;
+
+		/* Kick off the scheduler by setting up the context of the first task. */
+		portFIRST_CONTEXT();
+	}
+
+	return xSchedulerRunning;
+}
+/*-----------------------------------------------------------*/
+
+/* The ISR used depends on whether the preemptive or cooperative scheduler
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
+	static void __interrupt __far prvPreemptiveTick( void )
+	{
+		/* Get the scheduler to update the task states following the tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Switch in the context of the next task to be run. */
+			portSWITCH_CONTEXT();
+		}
+
+		/* Reset the PIC ready for the next time. */
+		portRESET_PIC();
+	}
+#else
+	static void __interrupt __far prvNonPreemptiveTick( void )
+	{
+		/* Same as preemptive tick, but the cooperative scheduler is being used
+		so we don't have to switch in the context of the next task. */
+		xTaskIncrementTick();
+		portRESET_PIC();
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+static void __interrupt __far prvYieldProcessor( void )
+{
+	/* Switch in the context of the next task to be run. */
+	portSWITCH_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Jump back to the processor state prior to starting the
+	scheduler.  This means we are not going to be using a
+	task stack frame so the task can be deleted. */
+	longjmp( xJumpBuf, 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvExitFunction( void )
+{
+const uint16_t usTimerDisable = 0x0000;
+uint16_t usTimer0Control;
+
+	/* Interrupts should be disabled here anyway - but no
+	harm in making sure. */
+	portDISABLE_INTERRUPTS();
+	if( xSchedulerRunning == pdTRUE )
+	{
+		/* Put back the switch interrupt routines that was in place
+		before the scheduler started. */
+		_dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
+	}
+
+	/* Disable the timer used for the tick to ensure the scheduler is
+	not called before restoring interrupts.  There was previously nothing
+	on this timer so there is no old ISR to restore. */
+	portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable );
+
+	/* Restart the DOS tick. */
+	usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );
+	usTimer0Control |= portTIMER_INTERRUPT_ENABLE;
+	portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );
+
+
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetTickFrequency( uint32_t ulTickRateHz )
+{
+const uint16_t usMaxCountRegister = 0xff5a;
+const uint16_t usTimerPriorityRegister = 0xff32;
+const uint16_t usTimerEnable = 0xC000;
+const uint16_t usRetrigger = 0x0001;
+const uint16_t usTimerHighPriority = 0x0000;
+uint16_t usTimer0Control;
+
+/* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */
+
+const uint32_t ulClockFrequency = ( uint32_t ) 0x7f31a0UL;
+
+uint32_t ulTimerCount = ulClockFrequency / ulTickRateHz;
+
+	portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger );
+	portOUTPUT_WORD( usMaxCountRegister, ( uint16_t ) ulTimerCount );
+	portOUTPUT_WORD( usTimerPriorityRegister, usTimerHighPriority );
+
+	/* Stop the DOS tick - don't do this if you want to maintain a TOD clock. */
+	usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );
+	usTimer0Control &= ~portTIMER_INTERRUPT_ENABLE;
+	portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );
+}
+
+
+/*lint +e950 */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h
new file mode 100644
index 0000000..834ea3d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h
@@ -0,0 +1,97 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		long
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	uint16_t
+#define portBASE_TYPE	portSHORT
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+#define portENTER_CRITICAL()			__asm{ pushf }  \
+										__asm{ cli 	 }	\
+
+#define portEXIT_CRITICAL()				__asm{ popf }
+
+#define portDISABLE_INTERRUPTS()		__asm{ cli }
+
+#define portENABLE_INTERRUPTS()			__asm{ sti }
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portNOP()						__asm{ nop }
+#define portSTACK_GROWTH				( -1 )
+#define portSWITCH_INT_NUMBER 			0x80
+#define portYIELD()						__asm{ int portSWITCH_INT_NUMBER }
+#define portTICK_PERIOD_MS		( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT      2
+#define portINITIAL_SW		( ( portSTACK_TYPE ) 0x0202 )	/* Start the tasks with interrupts enabled. */
+/*-----------------------------------------------------------*/
+
+/* Compiler specifics. */
+#define portINPUT_BYTE( xAddr )				inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )	outp( xAddr, ucValue )
+#define portINPUT_WORD( xAddr )				inpw( xAddr )
+#define portOUTPUT_WORD( xAddr, usValue )	outpw( xAddr, usValue )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/BCC/16BitDOS/PC/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/BCC/16BitDOS/PC/port.c
new file mode 100644
index 0000000..3a70695
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/BCC/16BitDOS/PC/port.c
@@ -0,0 +1,288 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V2.6.1
+
+	+ Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
+	  macro to be consistent with the later ports.
+
+Changes from V4.0.1
+	
+	+ Add function prvSetTickFrequencyDefault() to set the DOS tick back to
+	  its proper value when the scheduler exits. 
+*/
+
+#include 
+#include 
+#include 
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "portasm.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the industrial
+ * PC port.
+ *----------------------------------------------------------*/
+
+/*lint -e950 Non ANSI reserved words okay in this file only. */
+
+#define portTIMER_INT_NUMBER	0x08
+
+/* Setup hardware for required tick interrupt rate. */
+static void prvSetTickFrequency( uint32_t ulTickRateHz );
+
+/* Restore hardware to as it was prior to starting the scheduler. */
+static void prvExitFunction( void );
+
+/* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC
+directly.  We chain to the DOS tick as close as possible to the standard DOS
+tick rate. */
+static void prvPortResetPIC( void );
+
+/* The ISR used depends on whether the preemptive or cooperative
+scheduler is being used. */
+#if( configUSE_PREEMPTION == 1 )
+	/* Tick service routine used by the scheduler when preemptive scheduling is
+	being used. */
+	static void __interrupt __far prvPreemptiveTick( void );
+#else
+	/* Tick service routine used by the scheduler when cooperative scheduling is
+	being used. */
+	static void __interrupt __far prvNonPreemptiveTick( void );
+#endif
+
+/* Trap routine used by taskYIELD() to manually cause a context switch. */
+static void __interrupt __far prvYieldProcessor( void );
+
+/* Set the tick frequency back so the floppy drive works correctly when the
+scheduler exits. */
+static void prvSetTickFrequencyDefault( void );
+
+/*lint -e956 File scopes necessary here. */
+
+/* Used to signal when to chain to the DOS tick, and when to just clear the PIC ourselves. */
+static int16_t sDOSTickCounter;
+
+/* Set true when the vectors are set so the scheduler will service the tick. */
+static BaseType_t xSchedulerRunning = pdFALSE;				
+
+/* Points to the original routine installed on the vector we use for manual context switches.  This is then used to restore the original routine during prvExitFunction(). */
+static void ( __interrupt __far *pxOldSwitchISR )();		
+
+/* Points to the original routine installed on the vector we use to chain to the DOS tick.  This is then used to restore the original routine during prvExitFunction(). */
+static void ( __interrupt __far *pxOldSwitchISRPlus1 )();	
+
+/* Used to restore the original DOS context when the scheduler is ended. */
+static jmp_buf xJumpBuf;
+
+/*lint +e956 */
+
+/*-----------------------------------------------------------*/
+BaseType_t xPortStartScheduler( void )
+{
+pxISR pxOriginalTickISR;
+	
+	/* This is called with interrupts already disabled. */
+
+	/* Remember what was on the interrupts we are going to use
+	so we can put them back later if required. */
+	pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
+	pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER );
+	pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
+
+	prvSetTickFrequency( configTICK_RATE_HZ );
+
+	/* Put our manual switch (yield) function on a known
+	vector. */
+	_dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
+
+	/* Put the old tick on a different interrupt number so we can
+	call it when we want. */
+	_dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR );
+
+	/* The ISR used depends on whether the preemptive or cooperative
+	scheduler is being used. */
+	#if( configUSE_PREEMPTION == 1 )
+	{
+		/* Put our tick switch function on the timer interrupt. */
+		_dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
+	}
+	#else
+	{
+		/* We want the timer interrupt to just increment the tick count. */
+		_dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );
+	}
+    #endif
+
+	/* Setup a counter that is used to call the DOS interrupt as close
+	to it's original frequency as can be achieved given our chosen tick
+	frequency. */
+	sDOSTickCounter = portTICKS_PER_DOS_TICK;
+
+	/* Clean up function if we want to return to DOS. */
+	if( setjmp( xJumpBuf ) != 0 )
+	{
+		prvExitFunction();
+		xSchedulerRunning = pdFALSE;
+	}
+	else
+	{
+		xSchedulerRunning = pdTRUE;
+
+		/* Kick off the scheduler by setting up the context of the first task. */
+		portFIRST_CONTEXT();
+	}
+
+	return xSchedulerRunning;
+}
+/*-----------------------------------------------------------*/
+
+/* The ISR used depends on whether the preemptive or cooperative
+scheduler is being used. */
+#if( configUSE_PREEMPTION == 1 )
+	static void __interrupt __far prvPreemptiveTick( void )
+	{
+		/* Get the scheduler to update the task states following the tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Switch in the context of the next task to be run. */
+			portSWITCH_CONTEXT();
+		}
+
+		/* Reset the PIC ready for the next time. */
+		prvPortResetPIC();
+	}
+#else
+	static void __interrupt __far prvNonPreemptiveTick( void )
+	{
+		/* Same as preemptive tick, but the cooperative scheduler is being used
+		so we don't have to switch in the context of the next task. */
+		xTaskIncrementTick();
+		prvPortResetPIC();
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+static void __interrupt __far prvYieldProcessor( void )
+{
+	/* Switch in the context of the next task to be run. */
+	portSWITCH_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortResetPIC( void )
+{
+	/* We are going to call the DOS tick interrupt at as close a
+	frequency to the normal DOS tick as possible. */
+
+	/* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */
+	--sDOSTickCounter;
+	if( sDOSTickCounter <= 0 )
+	{
+		sDOSTickCounter = ( int16_t ) portTICKS_PER_DOS_TICK;
+		__asm{ int	portSWITCH_INT_NUMBER + 1 };		 
+	}
+	else
+	{
+		/* Reset the PIC as the DOS tick is not being called to
+		do it. */
+		__asm
+		{
+			mov	al, 20H
+			out 20H, al
+		};
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Jump back to the processor state prior to starting the
+	scheduler.  This means we are not going to be using a
+	task stack frame so the task can be deleted. */
+	longjmp( xJumpBuf, 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvExitFunction( void )
+{
+void ( __interrupt __far *pxOriginalTickISR )();
+
+	/* Interrupts should be disabled here anyway - but no 
+	harm in making sure. */
+	portDISABLE_INTERRUPTS();
+	if( xSchedulerRunning == pdTRUE )
+	{
+		/* Set the DOS tick back onto the timer ticker. */
+		pxOriginalTickISR = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
+		_dos_setvect( portTIMER_INT_NUMBER, pxOriginalTickISR );
+		prvSetTickFrequencyDefault();
+
+		/* Put back the switch interrupt routines that was in place
+		before the scheduler started. */
+		_dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
+		_dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 );
+	}
+	/* The tick timer is back how DOS wants it.  We can re-enable
+	interrupts without the scheduler being called. */
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetTickFrequency( uint32_t ulTickRateHz )
+{
+const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
+const uint16_t usPIT0 = ( uint16_t ) 0x40;
+const uint32_t ulPIT_CONST = ( uint32_t ) 1193180UL;
+const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
+uint32_t ulOutput;
+
+	/* Setup the 8245 to tick at the wanted frequency. */
+	portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
+	ulOutput = ulPIT_CONST / ulTickRateHz;
+	portOUTPUT_BYTE( usPIT0, ( uint16_t )( ulOutput & ( uint32_t ) 0xff ) );
+	ulOutput >>= 8;
+	portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetTickFrequencyDefault( void )
+{
+const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
+const uint16_t usPIT0 = ( uint16_t ) 0x40;
+const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
+
+	portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
+	portOUTPUT_BYTE( usPIT0,0 );
+	portOUTPUT_BYTE( usPIT0,0 );
+}
+
+
+/*lint +e950 */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/BCC/16BitDOS/PC/prtmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/BCC/16BitDOS/PC/prtmacro.h
new file mode 100644
index 0000000..67fd78c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/BCC/16BitDOS/PC/prtmacro.h
@@ -0,0 +1,97 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		long
+#define portDOUBLE		long
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	uint16_t
+#define portBASE_TYPE	portSHORT
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#define portENTER_CRITICAL()			__asm{ pushf }  \
+										__asm{ cli 	 }	\
+
+#define portEXIT_CRITICAL()				__asm{ popf }
+
+#define portDISABLE_INTERRUPTS()		__asm{ cli }
+
+#define portENABLE_INTERRUPTS()			__asm{ sti }
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portNOP()				__asm{ nop }
+#define portSTACK_GROWTH		( -1 )
+#define portSWITCH_INT_NUMBER 	0x80
+#define portYIELD()				__asm{ int portSWITCH_INT_NUMBER }
+#define portDOS_TICK_RATE		( 18.20648 )
+#define portTICK_PERIOD_MS		( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portTICKS_PER_DOS_TICK	( ( uint16_t ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) )
+#define portINITIAL_SW			( ( portSTACK_TYPE ) 0x0202 )	/* Start the tasks with interrupts enabled. */
+#define portBYTE_ALIGNMENT		( 2 )
+/*-----------------------------------------------------------*/
+
+/* Compiler specifics. */
+#define portINPUT_BYTE( xAddr )				inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )	outp( xAddr, ucValue )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/BCC/16BitDOS/common/portasm.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/BCC/16BitDOS/common/portasm.h
new file mode 100644
index 0000000..ca4d44c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/BCC/16BitDOS/common/portasm.h
@@ -0,0 +1,87 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORT_ASM_H
+#define PORT_ASM_H
+
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+extern void vTaskSwitchContext( void );
+
+/*
+ * Saves the stack pointer for one task into its TCB, calls
+ * vTaskSwitchContext() to update the TCB being used, then restores the stack
+ * from the new TCB read to run the task.
+ */
+void portSWITCH_CONTEXT( void );
+
+/*
+ * Load the stack pointer from the TCB of the task which is going to be first
+ * to execute.  Then force an IRET so the registers and IP are popped off the
+ * stack.
+ */
+void portFIRST_CONTEXT( void );
+
+/* There are slightly different versions depending on whether you are building
+to include debugger information.  If debugger information is used then there
+are a couple of extra bytes left of the ISR stack (presumably for use by the
+debugger).  The true stack pointer is then stored in the bp register.  We add
+2 to the stack pointer to remove the extra bytes before we restore our context. */
+
+#define portSWITCH_CONTEXT()											\
+							asm { mov	ax, seg pxCurrentTCB		}	\
+							asm { mov	ds, ax						}	\
+							asm { les	bx, pxCurrentTCB			}	/* Save the stack pointer into the TCB. */		\
+							asm { mov	es:0x2[ bx ], ss			}	\
+							asm { mov	es:[ bx ], sp				}	\
+							asm { call  far ptr vTaskSwitchContext	}	/* Perform the switch. */						\
+							asm { mov	ax, seg pxCurrentTCB		}	/* Restore the stack pointer from the TCB. */	\
+							asm { mov	ds, ax						}	\
+							asm { les	bx, dword ptr pxCurrentTCB	}	\
+							asm { mov	ss, es:[ bx + 2 ]			}	\
+							asm { mov	sp, es:[ bx ]				}
+
+#define portFIRST_CONTEXT()												\
+							__asm { mov	ax, seg pxCurrentTCB		}	\
+							__asm { mov	ds, ax						}	\
+							__asm { les	bx, dword ptr pxCurrentTCB	}	\
+							__asm { mov	ss, es:[ bx + 2 ]			}	\
+							__asm { mov	sp, es:[ bx ]				}	\
+							__asm { pop	bp							}	\
+							__asm { pop	di							}	\
+							__asm { pop	si							}	\
+							__asm { pop	ds							}	\
+							__asm { pop	es							}	\
+							__asm { pop	dx							}	\
+							__asm { pop	cx							}	\
+							__asm { pop	bx							}	\
+							__asm { pop	ax							}	\
+							__asm { iret							}
+
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/BCC/16BitDOS/common/portcomn.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/BCC/16BitDOS/common/portcomn.c
new file mode 100644
index 0000000..f4d2052
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/BCC/16BitDOS/common/portcomn.c
@@ -0,0 +1,120 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V1.00:
+
+	+ pxPortInitialiseStack() now initialises the stack of new tasks to the
+	  same format used by the compiler.  This allows the compiler generated
+	  interrupt mechanism to be used for context switches.
+
+Changes from V2.6.1
+
+	+ Move usPortCheckFreeStackSpace() to tasks.c.
+*/
+
+
+#include 
+#include 
+#include "FreeRTOS.h"
+
+/*-----------------------------------------------------------*/
+
+/* See header file for description. */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t DS_Reg = 0;
+
+	/* Place a few bytes of known values on the bottom of the stack.
+	This is just useful for debugging. */
+
+	*pxTopOfStack = 0x1111;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2222;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x3333;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x4444;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x5555;
+	pxTopOfStack--;
+
+
+	/*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
+
+	/* We are going to start the scheduler using a return from interrupt
+	instruction to load the program counter, so first there would be the
+	function call with parameters preamble. */
+	
+	*pxTopOfStack = FP_SEG( pvParameters );
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pvParameters );
+	pxTopOfStack--;
+	*pxTopOfStack = FP_SEG( pxCode );
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pxCode );
+	pxTopOfStack--;
+
+	/* Next the status register and interrupt return address. */
+	*pxTopOfStack = portINITIAL_SW; 
+	pxTopOfStack--;
+	*pxTopOfStack = FP_SEG( pxCode );
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pxCode );
+	pxTopOfStack--;
+
+	/* The remaining registers would be pushed on the stack by our context
+	switch function.  These are loaded with values simply to make debugging
+	easier. */
+	*pxTopOfStack = ( StackType_t ) 0xAAAA;	/* AX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xCCCC;	/* CX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xDDDD;	/* DX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xEEEE;	/* ES */
+	pxTopOfStack--;
+
+	/* We need the true data segment. */
+	__asm{	MOV DS_Reg, DS };
+
+	*pxTopOfStack = DS_Reg;						/* DS */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0123;	/* SI */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xDDDD;	/* DI */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BP */
+
+	/*lint +e950 +e611 +e923 */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_CM3/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_CM3/port.c
new file mode 100644
index 0000000..a159ab2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_CM3/port.c
@@ -0,0 +1,621 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM4F port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
+	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK					( 0xFFUL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR					( 0x01000000 )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR			( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK		( ( StackType_t ) 0xfffffffeUL )
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortSysTickHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+extern void vPortStartFirstTask( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Required to allow portasm.asm access the configMAX_SYSCALL_INTERRUPT_PRIORITY
+setting. */
+const uint32_t ulMaxSyscallInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+
+	/* Offset added to account for the way the MCU uses the stack on entry/exit
+	of interrupts, and to ensure alignment. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* LR */
+
+	/* Save code space by skipping register initialisation. */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Start the first task. */
+	vPortStartFirstTask();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
+	executes all interrupts must be unmasked.  There is therefore no need to
+	save and then restore the interrupt mask value as its value is already
+	known. */
+	( void ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE == 1 )
+
+	#pragma WEAK( vPortSuppressTicksAndSleep )
+	void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+	TickType_t xModifiableIdleTime;
+
+		/* Make sure the SysTick reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
+		is accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+		/* Calculate the reload value required to wait xExpectedIdleTime
+		tick periods.  -1 is used because this code will execute part way
+		through one of the tick periods. */
+		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+		if( ulReloadValue > ulStoppedTimerCompensation )
+		{
+			ulReloadValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Enter a critical section but don't use the taskENTER_CRITICAL()
+		method as that will mask interrupts that should exit sleep mode. */
+		__asm( "	cpsid i" );
+		__asm( "	dsb" );
+		__asm( "	isb" );
+
+
+		/* If a context switch is pending or a task is waiting for the scheduler
+		to be unsuspended then abandon the low power entry. */
+		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+		{
+			/* Restart from whatever is left in the count register to complete
+			this tick period. */
+			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Reset the reload register to the value required for normal tick
+			periods. */
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Re-enable interrupts - see comments above __disable_interrupt()
+			call above. */
+			__asm( "	cpsie i" );
+		}
+		else
+		{
+			/* Set the new reload value. */
+			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+			/* Clear the SysTick count flag and set the count value back to
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+			set its parameter to 0 to indicate that its implementation contains
+			its own wait for interrupt or wait for event instruction, and so wfi
+			should not be executed again.  However, the original expected idle
+			time variable must remain unmodified, so a copy is taken. */
+			xModifiableIdleTime = xExpectedIdleTime;
+			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+			if( xModifiableIdleTime > 0 )
+			{
+				__asm( "	dsb" );
+				__asm( "	wfi" );
+				__asm( "	isb" );
+			}
+			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+			/* Re-enable interrupts to allow the interrupt that brought the MCU
+			out of sleep mode to execute immediately.  see comments above
+			__disable_interrupt() call above. */
+			__asm( "	cpsie i" );
+			__asm( "	dsb" );
+			__asm( "	isb" );
+
+			/* Disable interrupts again because the clock is about to be stopped
+			and interrupts that execute while the clock is stopped will increase
+			any slippage between the time maintained by the RTOS and calendar
+			time. */
+			__asm( "	cpsid i" );
+			__asm( "	dsb" );
+			__asm( "	isb" );
+
+			/* Disable the SysTick clock without reading the
+			portNVIC_SYSTICK_CTRL_REG register to ensure the
+			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+			the time the SysTick is stopped for is accounted for as best it can
+			be, but using the tickless mode will inevitably result in some tiny
+			drift of the time maintained by the kernel with respect to calendar
+			time*/
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+			/* Determine if the SysTick clock has already counted to zero and
+			been set back to the current reload value (the reload back being
+			correct for the entire expected idle time) or if the SysTick is yet
+			to count to zero (in which case an interrupt other than the SysTick
+			must have brought the system out of sleep mode). */
+			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			{
+				uint32_t ulCalculatedLoadValue;
+
+				/* The tick interrupt is already pending, and the SysTick count
+				reloaded with ulReloadValue.  Reset the
+				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+				period. */
+				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+				/* Don't allow a tiny value, or values that have somehow
+				underflowed because the post sleep hook did something
+				that took too long. */
+				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+				{
+					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+				}
+
+				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+				/* As the pending tick will be processed as soon as this
+				function exits, the tick value maintained by the tick is stepped
+				forward by one less than the time spent waiting. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				Work out how long the sleep lasted rounded to complete tick
+				periods (not the ulReload value which accounted for part
+				ticks). */
+				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+				/* How many complete tick periods passed while the processor
+				was waiting? */
+				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+				/* The reload value is set to whatever fraction of a single tick
+				period remains. */
+				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+			}
+
+			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+			value. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+			vTaskStepTick( ulCompleteTickPeriods );
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Exit with interrpts enabled. */
+			__asm( "	cpsie i" );
+		}
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+#pragma WEAK( vPortSetupTimerInterrupt )
+void vPortSetupTimerInterrupt( void )
+{
+	/* Calculate the constants required to configure the tick interrupt. */
+	#if( configUSE_TICKLESS_IDLE == 1 )
+	{
+		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+	}
+	#endif /* configUSE_TICKLESS_IDLE */
+
+	/* Stop and clear the SysTick. */
+	portNVIC_SYSTICK_CTRL_REG = 0UL;
+	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	extern uint32_t ulPortGetIPSR( void );
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		ulCurrentInterrupt = ulPortGetIPSR();
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredictable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_CM3/portasm.asm b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_CM3/portasm.asm
new file mode 100644
index 0000000..f792963
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_CM3/portasm.asm
@@ -0,0 +1,144 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	.thumb
+
+	.ref pxCurrentTCB
+	.ref vTaskSwitchContext
+	.ref ulMaxSyscallInterruptPriority
+
+	.def xPortPendSVHandler
+	.def ulPortGetIPSR
+	.def vPortSVCHandler
+	.def vPortStartFirstTask
+
+NVICOffsetConst:					.word 	0xE000ED08
+CPACRConst:							.word 	0xE000ED88
+pxCurrentTCBConst:					.word	pxCurrentTCB
+ulMaxSyscallInterruptPriorityConst: .word ulMaxSyscallInterruptPriority
+
+; -----------------------------------------------------------
+
+	.align 4
+ulPortGetIPSR: .asmfunc
+ 	mrs r0, ipsr
+ 	bx r14
+ 	.endasmfunc
+ ; -----------------------------------------------------------
+
+	.align 4
+vPortSetInterruptMask: .asmfunc
+	push {r0}
+	ldr r0, ulMaxSyscallInterruptPriorityConst
+	msr basepri, r0
+	pop {r0}
+	bx r14
+	.endasmfunc
+; -----------------------------------------------------------
+
+	.align 4
+xPortPendSVHandler: .asmfunc
+	mrs r0, psp
+	isb
+
+	;/* Get the location of the current TCB. */
+	ldr	r3, pxCurrentTCBConst
+	ldr	r2, [r3]
+
+	;/* Save the core registers. */
+	stmdb r0!, {r4-r11}
+
+	;/* Save the new top of stack into the first member of the TCB. */
+	str r0, [r2]
+
+	stmdb sp!, {r3, r14}
+	ldr r0, ulMaxSyscallInterruptPriorityConst
+	ldr r1, [r0]
+	msr basepri, r1
+	dsb
+	isb
+	bl vTaskSwitchContext
+	mov r0, #0
+	msr basepri, r0
+	ldmia sp!, {r3, r14}
+
+	;/* The first item in pxCurrentTCB is the task top of stack. */
+	ldr r1, [r3]
+	ldr r0, [r1]
+
+	;/* Pop the core registers. */
+	ldmia r0!, {r4-r11}
+
+	msr psp, r0
+	isb
+	bx r14
+	.endasmfunc
+
+; -----------------------------------------------------------
+
+	.align 4
+vPortSVCHandler: .asmfunc
+	;/* Get the location of the current TCB. */
+	ldr	r3, pxCurrentTCBConst
+	ldr r1, [r3]
+	ldr r0, [r1]
+	;/* Pop the core registers. */
+	ldmia r0!, {r4-r11}
+	msr psp, r0
+	isb
+	mov r0, #0
+	msr	basepri, r0
+	orr r14, #0xd
+	bx r14
+	.endasmfunc
+
+; -----------------------------------------------------------
+
+	.align 4
+vPortStartFirstTask: .asmfunc
+	;/* Use the NVIC offset register to locate the stack. */
+	ldr r0, NVICOffsetConst
+	ldr r0, [r0]
+	ldr r0, [r0]
+	;/* Set the msp back to the start of the stack. */
+	msr msp, r0
+	;/* Clear the bit that indicates the FPU is in use in case the FPU was used
+	;before the scheduler was started - which would otherwise result in the
+	;unnecessary leaving of space in the SVC stack for lazy saving of FPU
+	;registers. */
+	mov r0, #0
+	msr control, r0
+	;/* Call SVC to start the first task. */
+	cpsie i
+	cpsie f
+	dsb
+	isb
+	svc #0
+	.endasmfunc
+
+; -----------------------------------------------------------
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_CM3/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_CM3/portmacro.h
new file mode 100644
index 0000000..a73c5eb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_CM3/portmacro.h
@@ -0,0 +1,171 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+
+/*-----------------------------------------------------------*/
+
+/* Compiler directives. */
+#define portWEAK_SYMBOL				__attribute__((weak))
+
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD()											\
+{															\
+	/* Set a PendSV to request a context switch. */			\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;			\
+	__asm( "	dsb" );										\
+	__asm( "	isb" );										\
+}
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()										\
+{																		\
+	_set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY );	\
+	__asm( "	dsb" );													\
+	__asm( "	isb" );													\
+}
+
+#define portENABLE_INTERRUPTS()					_set_interrupt_priority( 0 )
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()		_set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( "	dsb" ); __asm( "	isb" )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	_set_interrupt_priority( x )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_CM4F/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_CM4F/port.c
new file mode 100644
index 0000000..452aafc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_CM4F/port.c
@@ -0,0 +1,644 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM4F port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __TI_VFP_SUPPORT__
+	#error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
+	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK					( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS			( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR					( 0x01000000 )
+#define portINITIAL_EXC_RETURN				( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR			( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK		( ( StackType_t ) 0xfffffffeUL )
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortSysTickHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+extern void vPortStartFirstTask( void );
+
+/*
+ * Turn the VFP on.
+ */
+extern void vPortEnableVFP( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Required to allow portasm.asm access the configMAX_SYSCALL_INTERRUPT_PRIORITY
+setting. */
+const uint32_t ulMaxSyscallInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+
+	/* Offset added to account for the way the MCU uses the stack on entry/exit
+	of interrupts, and to ensure alignment. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* LR */
+
+	/* Save code space by skipping register initialisation. */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+
+	/* A save method is being used that requires each task to maintain its
+	own exec return value. */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+		
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Ensure the VFP is enabled - it should be anyway. */
+	vPortEnableVFP();
+
+	/* Lazy save always. */
+	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+	/* Start the first task. */
+	vPortStartFirstTask();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
+	executes all interrupts must be unmasked.  There is therefore no need to
+	save and then restore the interrupt mask value as its value is already
+	known. */
+	( void ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE == 1 )
+
+	#pragma WEAK( vPortSuppressTicksAndSleep )
+	void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+	TickType_t xModifiableIdleTime;
+
+		/* Make sure the SysTick reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
+		is accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+		/* Calculate the reload value required to wait xExpectedIdleTime
+		tick periods.  -1 is used because this code will execute part way
+		through one of the tick periods. */
+		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+		if( ulReloadValue > ulStoppedTimerCompensation )
+		{
+			ulReloadValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Enter a critical section but don't use the taskENTER_CRITICAL()
+		method as that will mask interrupts that should exit sleep mode. */
+		__asm( "	cpsid i" );
+		__asm( "	dsb" );
+		__asm( "	isb" );
+
+
+		/* If a context switch is pending or a task is waiting for the scheduler
+		to be unsuspended then abandon the low power entry. */
+		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+		{
+			/* Restart from whatever is left in the count register to complete
+			this tick period. */
+			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Reset the reload register to the value required for normal tick
+			periods. */
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Re-enable interrupts - see comments above __disable_interrupt()
+			call above. */
+			__asm( "	cpsie i" );
+		}
+		else
+		{
+			/* Set the new reload value. */
+			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+			/* Clear the SysTick count flag and set the count value back to
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+			set its parameter to 0 to indicate that its implementation contains
+			its own wait for interrupt or wait for event instruction, and so wfi
+			should not be executed again.  However, the original expected idle
+			time variable must remain unmodified, so a copy is taken. */
+			xModifiableIdleTime = xExpectedIdleTime;
+			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+			if( xModifiableIdleTime > 0 )
+			{
+				__asm( "	dsb" );
+				__asm( "	wfi" );
+				__asm( "	isb" );
+			}
+			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+			/* Re-enable interrupts to allow the interrupt that brought the MCU
+			out of sleep mode to execute immediately.  see comments above
+			__disable_interrupt() call above. */
+			__asm( "	cpsie i" );
+			__asm( "	dsb" );
+			__asm( "	isb" );
+
+			/* Disable interrupts again because the clock is about to be stopped
+			and interrupts that execute while the clock is stopped will increase
+			any slippage between the time maintained by the RTOS and calendar
+			time. */
+			__asm( "	cpsid i" );
+			__asm( "	dsb" );
+			__asm( "	isb" );
+
+			/* Disable the SysTick clock without reading the
+			portNVIC_SYSTICK_CTRL_REG register to ensure the
+			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+			the time the SysTick is stopped for is accounted for as best it can
+			be, but using the tickless mode will inevitably result in some tiny
+			drift of the time maintained by the kernel with respect to calendar
+			time*/
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+			/* Determine if the SysTick clock has already counted to zero and
+			been set back to the current reload value (the reload back being
+			correct for the entire expected idle time) or if the SysTick is yet
+			to count to zero (in which case an interrupt other than the SysTick
+			must have brought the system out of sleep mode). */
+			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			{
+				uint32_t ulCalculatedLoadValue;
+
+				/* The tick interrupt is already pending, and the SysTick count
+				reloaded with ulReloadValue.  Reset the
+				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+				period. */
+				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+				/* Don't allow a tiny value, or values that have somehow
+				underflowed because the post sleep hook did something
+				that took too long. */
+				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+				{
+					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+				}
+
+				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+				/* As the pending tick will be processed as soon as this
+				function exits, the tick value maintained by the tick is stepped
+				forward by one less than the time spent waiting. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				Work out how long the sleep lasted rounded to complete tick
+				periods (not the ulReload value which accounted for part
+				ticks). */
+				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+				/* How many complete tick periods passed while the processor
+				was waiting? */
+				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+				/* The reload value is set to whatever fraction of a single tick
+				period remains. */
+				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+			}
+
+			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+			value. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+			vTaskStepTick( ulCompleteTickPeriods );
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Exit with interrpts enabled. */
+			__asm( "	cpsie i" );
+		}
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+#pragma WEAK( vPortSetupTimerInterrupt )
+void vPortSetupTimerInterrupt( void )
+{
+	/* Calculate the constants required to configure the tick interrupt. */
+	#if( configUSE_TICKLESS_IDLE == 1 )
+	{
+		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+	}
+	#endif /* configUSE_TICKLESS_IDLE */
+
+	/* Stop and clear the SysTick. */
+	portNVIC_SYSTICK_CTRL_REG = 0UL;
+	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	extern uint32_t ulPortGetIPSR( void );
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		ulCurrentInterrupt = ulPortGetIPSR();
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredictable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_CM4F/portasm.asm b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_CM4F/portasm.asm
new file mode 100644
index 0000000..347fe84
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_CM4F/portasm.asm
@@ -0,0 +1,171 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	.thumb
+
+	.ref pxCurrentTCB
+	.ref vTaskSwitchContext
+	.ref ulMaxSyscallInterruptPriority
+
+	.def xPortPendSVHandler
+	.def ulPortGetIPSR
+	.def vPortSVCHandler
+	.def vPortStartFirstTask
+	.def vPortEnableVFP
+
+NVICOffsetConst:					.word 	0xE000ED08
+CPACRConst:							.word 	0xE000ED88
+pxCurrentTCBConst:					.word	pxCurrentTCB
+ulMaxSyscallInterruptPriorityConst: .word ulMaxSyscallInterruptPriority
+
+; -----------------------------------------------------------
+
+	.align 4
+ulPortGetIPSR: .asmfunc
+ 	mrs r0, ipsr
+ 	bx r14
+ 	.endasmfunc
+ ; -----------------------------------------------------------
+
+	.align 4
+vPortSetInterruptMask: .asmfunc
+	push {r0}
+	ldr r0, ulMaxSyscallInterruptPriorityConst
+	msr basepri, r0
+	pop {r0}
+	bx r14
+	.endasmfunc
+; -----------------------------------------------------------
+
+	.align 4
+xPortPendSVHandler: .asmfunc
+	mrs r0, psp
+	isb
+
+	;/* Get the location of the current TCB. */
+	ldr	r3, pxCurrentTCBConst
+	ldr	r2, [r3]
+
+	;/* Is the task using the FPU context?  If so, push high vfp registers. */
+	tst r14, #0x10
+	it eq
+	vstmdbeq r0!, {s16-s31}
+
+	;/* Save the core registers. */
+	stmdb r0!, {r4-r11, r14}
+
+	;/* Save the new top of stack into the first member of the TCB. */
+	str r0, [r2]
+
+	stmdb sp!, {r0, r3}
+	ldr r0, ulMaxSyscallInterruptPriorityConst
+	ldr r1, [r0]
+	msr basepri, r1
+	dsb
+	isb
+	bl vTaskSwitchContext
+	mov r0, #0
+	msr basepri, r0
+	ldmia sp!, {r0, r3}
+
+	;/* The first item in pxCurrentTCB is the task top of stack. */
+	ldr r1, [r3]
+	ldr r0, [r1]
+
+	;/* Pop the core registers. */
+	ldmia r0!, {r4-r11, r14}
+
+	;/* Is the task using the FPU context?  If so, pop the high vfp registers
+	;too. */
+	tst r14, #0x10
+	it eq
+	vldmiaeq r0!, {s16-s31}
+
+	msr psp, r0
+	isb
+	bx r14
+	.endasmfunc
+
+; -----------------------------------------------------------
+
+	.align 4
+vPortSVCHandler: .asmfunc
+	;/* Get the location of the current TCB. */
+	ldr	r3, pxCurrentTCBConst
+	ldr r1, [r3]
+	ldr r0, [r1]
+	;/* Pop the core registers. */
+	ldmia r0!, {r4-r11, r14}
+	msr psp, r0
+	isb
+	mov r0, #0
+	msr	basepri, r0
+	bx r14
+	.endasmfunc
+
+; -----------------------------------------------------------
+
+	.align 4
+vPortStartFirstTask: .asmfunc
+	;/* Use the NVIC offset register to locate the stack. */
+	ldr r0, NVICOffsetConst
+	ldr r0, [r0]
+	ldr r0, [r0]
+	;/* Set the msp back to the start of the stack. */
+	msr msp, r0
+	;/* Clear the bit that indicates the FPU is in use in case the FPU was used
+	;before the scheduler was started - which would otherwise result in the
+	;unnecessary leaving of space in the SVC stack for lazy saving of FPU
+	;registers. */
+	mov r0, #0
+	msr control, r0
+	;/* Call SVC to start the first task. */
+	cpsie i
+	cpsie f
+	dsb
+	isb
+	svc #0
+	.endasmfunc
+
+; -----------------------------------------------------------
+
+	.align 4
+vPortEnableVFP: .asmfunc
+	;/* The FPU enable bits are in the CPACR. */
+	ldr.w r0, CPACRConst
+	ldr	r1, [r0]
+
+	;/* Enable CP10 and CP11 coprocessors, then save back. */
+	orr	r1, r1, #( 0xf << 20 )
+	str r1, [r0]
+	bx	r14
+	.endasmfunc
+
+	.end
+
+; -----------------------------------------------------------
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_CM4F/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_CM4F/portmacro.h
new file mode 100644
index 0000000..a94ec7d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_CM4F/portmacro.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD()											\
+{															\
+	/* Set a PendSV to request a context switch. */			\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;			\
+	__asm( "	dsb" );										\
+	__asm( "	isb" );										\
+}
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()										\
+{																		\
+	_set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY );	\
+	__asm( "	dsb" );													\
+	__asm( "	isb" );													\
+}
+
+#define portENABLE_INTERRUPTS()					_set_interrupt_priority( 0 )
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()		_set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( "	dsb" ); __asm( "	isb" )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	_set_interrupt_priority( x )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/port.c
new file mode 100644
index 0000000..31904d4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/port.c
@@ -0,0 +1,312 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------*/
+
+/* Count of the critical section nesting depth. */
+uint32_t ulCriticalNesting = 9999;
+
+/*-----------------------------------------------------------*/
+
+/* Registers required to configure the RTI. */
+#define portRTI_GCTRL_REG  		( * ( ( volatile uint32_t * ) 0xFFFFFC00 ) )
+#define portRTI_TBCTRL_REG  	( * ( ( volatile uint32_t * ) 0xFFFFFC04 ) )
+#define portRTI_COMPCTRL_REG  	( * ( ( volatile uint32_t * ) 0xFFFFFC0C ) )
+#define portRTI_CNT0_FRC0_REG  	( * ( ( volatile uint32_t * ) 0xFFFFFC10 ) )
+#define portRTI_CNT0_UC0_REG  	( * ( ( volatile uint32_t * ) 0xFFFFFC14 ) )
+#define portRTI_CNT0_CPUC0_REG  ( * ( ( volatile uint32_t * ) 0xFFFFFC18 ) )
+#define portRTI_CNT0_COMP0_REG  ( * ( ( volatile uint32_t * ) 0xFFFFFC50 ) )
+#define portRTI_CNT0_UDCP0_REG  ( * ( ( volatile uint32_t * ) 0xFFFFFC54 ) )
+#define portRTI_SETINTENA_REG  	( * ( ( volatile uint32_t * ) 0xFFFFFC80 ) )
+#define portRTI_CLEARINTENA_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC84 ) )
+#define portRTI_INTFLAG_REG  	( * ( ( volatile uint32_t * ) 0xFFFFFC88 ) )
+
+
+/* Constants required to set up the initial stack of each task. */
+#define portINITIAL_SPSR	   	( ( StackType_t ) 0x1F )
+#define portINITIAL_FPSCR	  	( ( StackType_t ) 0x00 )
+#define portINSTRUCTION_SIZE   	( ( StackType_t ) 0x04 )
+#define portTHUMB_MODE_BIT		( ( StackType_t ) 0x20 )
+
+/* The number of words on the stack frame between the saved Top Of Stack and
+R0 (in which the parameters are passed. */
+#define portSPACE_BETWEEN_TOS_AND_PARAMETERS	( 12 )
+
+/*-----------------------------------------------------------*/
+
+/* vPortStartFirstSTask() is defined in portASM.asm */
+extern void vPortStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/* Saved as part of the task context.  Set to pdFALSE if the task does not
+require an FPU context. */
+uint32_t ulTaskHasFPUContext = 0;
+
+/*-----------------------------------------------------------*/
+
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	#if __TI_VFP_SUPPORT__
+	{
+		/* Ensure the stack is correctly aligned on exit. */
+		pxTopOfStack--;
+	}
+	#endif
+
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which is the start of the as
+	the task has not executed yet.  The offset is added to make the return
+	address appear as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0x00000000;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+
+	#ifdef portPRELOAD_TASK_REGISTERS
+	{
+		*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+		pxTopOfStack--;
+	}
+	#else
+	{
+		pxTopOfStack -= portSPACE_BETWEEN_TOS_AND_PARAMETERS;
+	}
+	#endif
+
+	/* Function parameters are passed in R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* Set the status register for system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) ( ( _get_CPSR() & ~0xFF ) | portINITIAL_SPSR );
+
+	if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
+	{
+		/* The task will start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+
+	#ifdef __TI_VFP_SUPPORT__
+	{
+		pxTopOfStack--;
+
+		/* The last thing on the stack is the tasks ulUsingFPU value, which by
+		default is set to indicate that the stack frame does not include FPU
+		registers. */
+		*pxTopOfStack = pdFALSE;
+	}
+	#endif
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt(void)
+{
+	/* Disable timer 0. */
+	portRTI_GCTRL_REG &= 0xFFFFFFFEUL;
+
+	/* Use the internal counter. */
+	portRTI_TBCTRL_REG = 0x00000000U;
+
+	/* COMPSEL0 will use the RTIFRC0 counter. */
+	portRTI_COMPCTRL_REG = 0x00000000U;
+
+	/* Initialise the counter and the prescale counter registers. */
+	portRTI_CNT0_UC0_REG =  0x00000000U;
+	portRTI_CNT0_FRC0_REG =  0x00000000U;
+
+	/* Set Prescalar for RTI clock. */
+	portRTI_CNT0_CPUC0_REG = 0x00000001U;
+	portRTI_CNT0_COMP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;
+	portRTI_CNT0_UDCP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;
+
+	/* Clear interrupts. */
+	portRTI_INTFLAG_REG =  0x0007000FU;
+	portRTI_CLEARINTENA_REG	= 0x00070F0FU;
+
+	/* Enable the compare 0 interrupt. */
+	portRTI_SETINTENA_REG = 0x00000001U;
+	portRTI_GCTRL_REG |= 0x00000001U;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler(void)
+{
+	/* Start the timer that generates the tick ISR. */
+	prvSetupTimerInterrupt();
+
+	/* Reset the critical section nesting count read to execute the first task. */
+	ulCriticalNesting = 0;
+
+	/* Start the first task.  This is done from portASM.asm as ARM mode must be
+	used. */
+	vPortStartFirstTask();
+
+	/* Should not get here! */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+void vPortEndScheduler(void)
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 0
+
+	/* The cooperative scheduler requires a normal IRQ service routine to
+	 * simply increment the system tick. */
+	__interrupt void vPortNonPreemptiveTick( void )
+	{
+		/* clear clock interrupt flag */
+		portRTI_INTFLAG_REG = 0x00000001;
+
+		/* Increment the tick count - this may make a delaying task ready
+		to run - but a context switch is not performed. */
+		xTaskIncrementTick();
+	}
+
+ #else
+
+	/*
+	 **************************************************************************
+	 * The preemptive scheduler ISR is written in assembler and can be found
+	 * in the portASM.asm file. This will only get used if portUSE_PREEMPTION
+	 * is set to 1 in portmacro.h
+	 **************************************************************************
+	 */
+	void vPortPreemptiveTick( void );
+
+#endif
+/*-----------------------------------------------------------*/
+
+
+/*
+ * Disable interrupts, and keep a count of the nesting depth.
+ */
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
+	portDISABLE_INTERRUPTS();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Decrement the critical nesting count, and if it has reached zero, re-enable
+ * interrupts.
+ */
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > 0 )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == 0 )
+		{
+			/* Enable interrupts as per portENABLE_INTERRUPTS(). */
+			portENABLE_INTERRUPTS();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if __TI_VFP_SUPPORT__
+
+	void vPortTaskUsesFPU( void )
+	{
+	extern void vPortInitialiseFPSCR( void );
+
+		/* A task is registering the fact that it needs an FPU context.  Set the
+		FPU flag (saved as part of the task context. */
+		ulTaskHasFPUContext = pdTRUE;
+
+		/* Initialise the floating point status register. */
+		vPortInitialiseFPSCR();
+	}
+
+#endif /* __TI_VFP_SUPPORT__ */
+
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portASM.asm b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portASM.asm
new file mode 100644
index 0000000..fa13b18
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portASM.asm
@@ -0,0 +1,229 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+        .text
+        .arm
+        .ref vTaskSwitchContext
+        .ref xTaskIncrementTick
+        .ref ulTaskHasFPUContext
+		.ref pxCurrentTCB
+
+;/*-----------------------------------------------------------*/
+;
+; Save Task Context
+;
+portSAVE_CONTEXT .macro
+		DSB
+
+		; Push R0 as we are going to use it
+		STMDB	SP!, {R0}
+
+		; Set R0 to point to the task stack pointer.
+		STMDB	SP,{SP}^
+		SUB	SP, SP, #4
+		LDMIA	SP!,{R0}
+
+		; Push the return address onto the stack.
+		STMDB	R0!, {LR}
+
+		; Now LR has been saved, it can be used instead of R0.
+		MOV	LR, R0
+
+		; Pop R0 so it can be saved onto the task stack.
+		LDMIA	SP!, {R0}
+
+		; Push all the system mode registers onto the task stack.
+		STMDB	LR,{R0-LR}^
+		SUB	LR, LR, #60
+
+		; Push the SPSR onto the task stack.
+		MRS	R0, SPSR
+		STMDB	LR!, {R0}
+
+    .if (__TI_VFP_SUPPORT__)
+		;Determine if the task maintains an FPU context.
+		LDR	R0, ulFPUContextConst
+		LDR	R0, [R0]
+
+		; Test the flag
+		CMP		R0, #0
+
+		; If the task is not using a floating point context then skip the
+		; saving of the FPU registers.
+		BEQ		$+16
+		FSTMDBD	LR!, {D0-D15}
+		FMRX    R1,  FPSCR
+		STMFD   LR!, {R1}
+
+		; Save the flag
+		STMDB	LR!, {R0}
+	.endif
+
+		; Store the new top of stack for the task.
+		LDR	R0, pxCurrentTCBConst
+		LDR	R0, [R0]
+		STR	LR, [R0]
+
+        .endm
+
+;/*-----------------------------------------------------------*/
+;
+; Restore Task Context
+;
+portRESTORE_CONTEXT .macro
+		LDR		R0, pxCurrentTCBConst
+		LDR		R0, [R0]
+		LDR		LR, [R0]
+
+	.if (__TI_VFP_SUPPORT__)
+		; The floating point context flag is the first thing on the stack.
+		LDR		R0, ulFPUContextConst
+		LDMFD	LR!, {R1}
+		STR		R1, [R0]
+
+		; Test the flag
+		CMP		R1, #0
+
+		; If the task is not using a floating point context then skip the
+		; VFP register loads.
+		BEQ		$+16
+
+		; Restore the floating point context.
+		LDMFD   LR!, {R0}
+		FLDMIAD	LR!, {D0-D15}
+		FMXR    FPSCR, R0
+	.endif
+
+		; Get the SPSR from the stack.
+		LDMFD	LR!, {R0}
+		MSR		SPSR_CSXF, R0
+
+		; Restore all system mode registers for the task.
+		LDMFD	LR, {R0-R14}^
+
+		; Restore the return address.
+		LDR		LR, [LR, #+60]
+
+		; And return - correcting the offset in the LR to obtain the
+		; correct address.
+		SUBS	PC, LR, #4
+        .endm
+
+;/*-----------------------------------------------------------*/
+; Start the first task by restoring its context.
+
+        .def vPortStartFirstTask
+
+vPortStartFirstTask:
+        portRESTORE_CONTEXT
+
+;/*-----------------------------------------------------------*/
+; Yield to another task.
+
+        .def vPortYieldProcessor
+
+vPortYieldProcessor:
+		; Within an IRQ ISR the link register has an offset from the true return
+		; address.  SWI doesn't do this. Add the offset manually so the ISR
+		; return code can be used.
+        ADD     LR, LR, #4
+
+        ; First save the context of the current task.
+        portSAVE_CONTEXT
+
+        ; Select the next task to execute. */
+        BL      vTaskSwitchContext
+
+        ; Restore the context of the task selected to execute.
+        portRESTORE_CONTEXT
+
+;/*-----------------------------------------------------------*/
+; Yield to another task from within the FreeRTOS API
+
+		.def vPortYeildWithinAPI
+
+vPortYeildWithinAPI:
+		; Save the context of the current task.
+
+        portSAVE_CONTEXT
+		; Clear SSI flag.
+		MOVW    R0, #0xFFF4
+		MOVT 	R0, #0xFFFF
+		LDR     R0, [R0]
+
+		; Select the next task to execute. */
+        BL      vTaskSwitchContext
+
+        ; Restore the context of the task selected to execute.
+        portRESTORE_CONTEXT
+
+;/*-----------------------------------------------------------*/
+; Preemptive Tick
+
+        .def vPortPreemptiveTick
+
+vPortPreemptiveTick:
+
+		; Save the context of the current task.
+        portSAVE_CONTEXT
+
+        ; Clear interrupt flag
+        MOVW    R0, #0xFC88
+        MOVT    R0, #0xFFFF
+        MOV     R1, #1
+        STR     R1, [R0]
+
+        ; Increment the tick count, making any adjustments to the blocked lists
+        ; that may be necessary.
+        BL      xTaskIncrementTick
+
+        ; Select the next task to execute.
+        CMP	R0, #0
+        BLNE    vTaskSwitchContext
+
+        ; Restore the context of the task selected to execute.
+        portRESTORE_CONTEXT
+
+;-------------------------------------------------------------------------------
+
+	.if (__TI_VFP_SUPPORT__)
+
+		.def vPortInitialiseFPSCR
+
+vPortInitialiseFPSCR:
+
+		MOV		R0, #0
+		FMXR    FPSCR, R0
+		BX		LR
+
+	.endif ;__TI_VFP_SUPPORT__
+
+
+pxCurrentTCBConst	.word	pxCurrentTCB
+ulFPUContextConst 	.word   ulTaskHasFPUContext
+;-------------------------------------------------------------------------------
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portmacro.h
new file mode 100644
index 0000000..1257b7d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portmacro.h
@@ -0,0 +1,117 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORTMACRO_H__
+#define __PORTMACRO_H__
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint32_t
+#define portBASE_TYPE   long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if (configUSE_16_BIT_TICKS == 1)
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY (TickType_t) 0xFFFF
+#else
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY (TickType_t) 0xFFFFFFFFF
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH    (-1)
+#define portTICK_PERIOD_MS    ((TickType_t) 1000 / configTICK_RATE_HZ)
+#define portBYTE_ALIGNMENT  8
+
+/* Critical section handling. */
+extern void vPortEnterCritical(void);
+extern void vPortExitCritical(void);
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+#define portDISABLE_INTERRUPTS()	asm( " CPSID I" )
+#define portENABLE_INTERRUPTS()		asm( " CPSIE I" )
+
+/* Scheduler utilities. */
+#pragma SWI_ALIAS( vPortYield, 0 )
+extern void vPortYield( void );
+#define portYIELD()             	vPortYield()
+#define portSYS_SSIR1_REG			( * ( ( volatile uint32_t * ) 0xFFFFFFB0 ) )
+#define portSYS_SSIR1_SSKEY			( 0x7500UL )
+#define portYIELD_WITHIN_API()		{ portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY;  asm( " DSB " ); asm( " ISB " ); }
+#define portYIELD_FROM_ISR( x )		if( x != pdFALSE ){ portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY;  ( void ) portSYS_SSIR1_REG; }
+
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+/* Architecture specific optimisations. */
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION(vFunction, pvParameters)       void vFunction(void *pvParameters)
+#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters)
+
+#endif /* __PORTMACRO_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/MSP430X/data_model.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/MSP430X/data_model.h
new file mode 100644
index 0000000..018a4b0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/MSP430X/data_model.h
@@ -0,0 +1,53 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	.if $DEFINED( __LARGE_DATA_MODEL__ )
+		.define "pushm.a", pushm_x
+		.define "popm.a", popm_x
+		.define "push.a", push_x
+		.define "pop.a", pop_x
+		.define "mov.a", mov_x
+	.else
+		.define "pushm.w", pushm_x
+		.define "popm.w", popm_x
+		.define "push.w", push_x
+		.define "pop.w", pop_x
+		.define "mov.w", mov_x
+	.endif
+
+	.if $DEFINED( __LARGE_CODE_MODEL__ )
+		.define "calla", call_x
+		.define "reta", ret_x
+	.else
+		.define "call", call_x
+		.define "ret", ret_x
+	.endif
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/MSP430X/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/MSP430X/port.c
new file mode 100644
index 0000000..c9087ff
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/MSP430X/port.c
@@ -0,0 +1,187 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MSP430X port.
+ *----------------------------------------------------------*/
+
+/* Constants required for hardware setup.  The tick ISR runs off the ACLK,
+not the MCLK. */
+#define portACLK_FREQUENCY_HZ			( ( TickType_t ) 32768 )
+#define portINITIAL_CRITICAL_NESTING	( ( uint16_t ) 10 )
+#define portFLAGS_INT_ENABLED			( ( StackType_t ) 0x08 )
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/* Each task maintains a count of the critical section nesting depth.  Each
+time a critical section is entered the count is incremented.  Each time a
+critical section is exited the count is decremented - with interrupts only
+being re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as this will cause problems during the startup
+sequence. */
+volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
+/*-----------------------------------------------------------*/
+
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
+ * could have alternatively used the watchdog timer or timer 1.
+ */
+void vPortSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint16_t *pusTopOfStack;
+uint32_t *pulTopOfStack, ulTemp;
+
+	/*
+		Place a few bytes of known values on the bottom of the stack.
+		This is just useful for debugging and can be included if required.
+
+		*pxTopOfStack = ( StackType_t ) 0x1111;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x2222;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x3333;
+		pxTopOfStack--;
+	*/
+
+	/* Data types are need either 16 bits or 32 bits depending on the data 
+	and code model used. */
+	if( sizeof( pxCode ) == sizeof( uint16_t ) )
+	{
+		pusTopOfStack = ( uint16_t * ) pxTopOfStack;
+		ulTemp = ( uint32_t ) pxCode;
+		*pusTopOfStack = ( uint16_t ) ulTemp;
+	}
+	else
+	{
+		/* Make room for a 20 bit value stored as a 32 bit value. */
+		pusTopOfStack = ( uint16_t * ) pxTopOfStack;		
+		pusTopOfStack--;
+		pulTopOfStack = ( uint32_t * ) pusTopOfStack;
+		*pulTopOfStack = ( uint32_t ) pxCode;
+	}
+
+	pusTopOfStack--;
+	*pusTopOfStack = portFLAGS_INT_ENABLED;
+	pusTopOfStack -= ( sizeof( StackType_t ) / 2 );
+	
+	/* From here on the size of stacked items depends on the memory model. */
+	pxTopOfStack = ( StackType_t * ) pusTopOfStack;
+
+	/* Next the general purpose registers. */
+	#ifdef PRELOAD_REGISTER_VALUES
+		*pxTopOfStack = ( StackType_t ) 0xffff;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0xeeee;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0xdddd;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pvParameters;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0xbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0xaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x9999;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x8888;
+		pxTopOfStack--;	
+		*pxTopOfStack = ( StackType_t ) 0x5555;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x6666;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x5555;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x4444;
+		pxTopOfStack--;
+	#else
+		pxTopOfStack -= 3;
+		*pxTopOfStack = ( StackType_t ) pvParameters;
+		pxTopOfStack -= 9;
+	#endif
+
+	/* A variable is used to keep track of the critical section nesting.
+	This variable has to be stored as part of the task context and is
+	initially set to zero. */
+	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;	
+
+	/* Return a pointer to the top of the stack we have generated so this can
+	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the MSP430 port will get stopped.  If required simply
+	disable the tick interrupt here. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.
+ */
+void vPortSetupTimerInterrupt( void )
+{
+	vApplicationSetupTimerInterrupt();
+}
+/*-----------------------------------------------------------*/
+
+#pragma vector=configTICK_VECTOR
+interrupt void vTickISREntry( void )
+{
+extern void vPortTickISR( void );
+
+	__bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF );
+	#if configUSE_PREEMPTION == 1
+		extern void vPortPreemptiveTickISR( void );
+		vPortPreemptiveTickISR();
+	#else
+		extern void vPortCooperativeTickISR( void );
+		vPortCooperativeTickISR();
+	#endif
+}
+
+	
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/MSP430X/portext.asm b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/MSP430X/portext.asm
new file mode 100644
index 0000000..9e29a5d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/MSP430X/portext.asm
@@ -0,0 +1,159 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+; * The definition of the "register test" tasks, as described at the top of
+; * main.c
+
+	.include data_model.h
+
+	.global xTaskIncrementTick
+	.global vTaskSwitchContext
+	.global vPortSetupTimerInterrupt
+	.global pxCurrentTCB
+	.global usCriticalNesting
+
+	.def vPortPreemptiveTickISR
+	.def vPortCooperativeTickISR
+	.def vPortYield
+	.def xPortStartScheduler
+
+;-----------------------------------------------------------
+
+portSAVE_CONTEXT .macro
+
+	;Save the remaining registers.
+	pushm_x	#12, r15
+	mov.w	&usCriticalNesting, r14
+	push_x r14
+	mov_x	&pxCurrentTCB, r12
+	mov_x	sp, 0( r12 )
+	.endm
+;-----------------------------------------------------------
+
+portRESTORE_CONTEXT .macro
+
+	mov_x	&pxCurrentTCB, r12
+	mov_x	@r12, sp
+	pop_x	r15
+	mov.w	r15, &usCriticalNesting
+	popm_x	#12, r15
+	nop
+	pop.w	sr
+	nop
+	ret_x
+	.endm
+;-----------------------------------------------------------
+
+;*
+;* The RTOS tick ISR.
+;*
+;* If the cooperative scheduler is in use this simply increments the tick
+;* count.
+;*
+;* If the preemptive scheduler is in use a context switch can also occur.
+;*/
+
+	.text
+	.align 2
+
+vPortPreemptiveTickISR: .asmfunc
+
+	; The sr is not saved in portSAVE_CONTEXT() because vPortYield() needs
+	;to save it manually before it gets modified (interrupts get disabled).
+	push.w sr
+	portSAVE_CONTEXT
+
+	call_x	#xTaskIncrementTick
+	call_x	#vTaskSwitchContext
+
+	portRESTORE_CONTEXT
+	.endasmfunc
+;-----------------------------------------------------------
+
+	.align 2
+
+vPortCooperativeTickISR: .asmfunc
+
+	; The sr is not saved in portSAVE_CONTEXT() because vPortYield() needs
+	;to save it manually before it gets modified (interrupts get disabled).
+	push.w sr
+	portSAVE_CONTEXT
+
+	call_x	#xTaskIncrementTick
+
+	portRESTORE_CONTEXT
+
+	.endasmfunc
+;-----------------------------------------------------------
+
+;
+; Manual context switch called by the portYIELD() macro.
+;
+
+	.align 2
+
+vPortYield: .asmfunc
+
+	; The sr needs saving before it is modified.
+	push.w	sr
+
+	; Now the SR is stacked we can disable interrupts.
+	dint
+	nop
+
+	; Save the context of the current task.
+	portSAVE_CONTEXT
+
+	; Select the next task to run.
+	call_x	#vTaskSwitchContext
+
+	; Restore the context of the new task.
+	portRESTORE_CONTEXT
+	.endasmfunc
+;-----------------------------------------------------------
+
+
+;
+; Start off the scheduler by initialising the RTOS tick timer, then restoring
+; the context of the first task.
+;
+
+	.align 2
+
+xPortStartScheduler: .asmfunc
+
+	; Setup the hardware to generate the tick.  Interrupts are disabled
+	; when this function is called.
+	call_x	#vPortSetupTimerInterrupt
+
+	; Restore the context of the first task that is going to run.
+	portRESTORE_CONTEXT
+	.endasmfunc
+;-----------------------------------------------------------
+
+	.end
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/MSP430X/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/MSP430X/portmacro.h
new file mode 100644
index 0000000..3a46b01
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CCS/MSP430X/portmacro.h
@@ -0,0 +1,143 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Hardware includes. */
+#include "msp430.h"
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		int
+#define portBASE_TYPE	portSHORT
+
+/* The stack type changes depending on the data model. */
+#ifdef __LARGE_DATA_MODEL__
+	#define portSTACK_TYPE uint32_t
+#else
+	#define portSTACK_TYPE uint16_t
+	#define portPOINTER_SIZE_TYPE uint16_t
+#endif
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS()	_disable_interrupt(); _nop()
+#define portENABLE_INTERRUPTS()		_enable_interrupt(); _nop()
+/*-----------------------------------------------------------*/
+
+/* Critical section control macros. */
+#define portNO_CRITICAL_SECTION_NESTING		( ( uint16_t ) 0 )
+
+#define portENTER_CRITICAL()													\
+{																				\
+extern volatile uint16_t usCriticalNesting;										\
+																				\
+	portDISABLE_INTERRUPTS();													\
+																				\
+	/* Now interrupts are disabled usCriticalNesting can be accessed */			\
+	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
+	/* times portENTER_CRITICAL() has been called. */							\
+	usCriticalNesting++;														\
+}
+
+#define portEXIT_CRITICAL()														\
+{																				\
+extern volatile uint16_t usCriticalNesting;										\
+																				\
+	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
+	{																			\
+		/* Decrement the nesting count as we are leaving a critical section. */	\
+		usCriticalNesting--;													\
+																				\
+		/* If the nesting level has reached zero then interrupts should be */	\
+		/* re-enabled. */														\
+		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
+		{																		\
+			portENABLE_INTERRUPTS();											\
+		}																		\
+	}																			\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.
+ */
+extern void vPortYield( void );
+#define portYIELD() vPortYield()
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			2
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					__no_operation()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+extern void vTaskSwitchContext( void );
+#define portYIELD_FROM_ISR( x ) if( x ) vPortYield()
+
+void vApplicationSetupTimerInterrupt( void );
+
+/* sizeof( int ) != sizeof( long ) so a full printf() library is required if
+run time stats information is to be displayed. */
+#define portLU_PRINTF_SPECIFIER_REQUIRED
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/port.c
new file mode 100644
index 0000000..4d261bc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/port.c
@@ -0,0 +1,183 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+
+#define portINITIAL_FORMAT_VECTOR		( ( StackType_t ) 0x4000 )
+
+/* Supervisor mode set. */
+#define portINITIAL_STATUS_REGISTER		( ( StackType_t ) 0x2000)
+
+/* The clock prescale into the timer peripheral. */
+#define portPRESCALE_VALUE				( ( uint8_t ) 10 )
+
+/* The clock frequency into the RTC. */
+#define portRTC_CLOCK_HZ				( ( uint32_t ) 1000 )
+
+asm void interrupt VectorNumber_VL1swi vPortYieldISR( void );
+static void prvSetupTimerInterrupt( void );
+
+/* Used to keep track of the number of nested calls to taskENTER_CRITICAL().  This
+will be set to 0 prior to the first task being started. */
+static uint32_t ulCriticalNesting = 0x9999UL;
+
+/*-----------------------------------------------------------*/
+
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+
+uint32_t ulOriginalA5;
+
+	__asm{ MOVE.L A5, ulOriginalA5 };
+
+
+	*pxTopOfStack = (StackType_t) 0xDEADBEEF;
+	pxTopOfStack--;
+
+	/* Exception stack frame starts with the return address. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER );
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0x0; /*FP*/
+	pxTopOfStack -= 14; /* A5 to D0. */
+
+	/* Parameter in A0. */
+	*( pxTopOfStack + 8 ) = ( StackType_t ) pvParameters;
+
+	/* A5 must be maintained as it is resurved by the compiler. */
+	*( pxTopOfStack + 13 ) = ulOriginalA5;
+
+	return pxTopOfStack;  
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+
+	ulCriticalNesting = 0UL;
+
+	/* Configure a timer to generate the tick interrupt. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task executing. */
+	vPortStartFirstTask();
+
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{				
+	/* Prescale by 1 - ie no prescale. */
+	RTCSC |= 8;
+	
+	/* Compare match value. */
+	RTCMOD = portRTC_CLOCK_HZ / configTICK_RATE_HZ;
+	
+	/* Enable the RTC to generate interrupts - interrupts are already disabled
+	when this code executes. */
+	RTCSC_RTIE = 1;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented as there is nothing to return to. */
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	if( ulCriticalNesting == 0UL )
+	{
+		/* Guard against context switches being pended simultaneously with a
+		critical section being entered. */
+		do
+		{
+			portDISABLE_INTERRUPTS();
+			if( INTC_FRC == 0UL )
+			{
+				break;
+			}
+
+			portENABLE_INTERRUPTS();
+
+		} while( 1 );
+	}
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	ulCriticalNesting--;
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortYieldHandler( void )
+{
+uint32_t ulSavedInterruptMask;
+
+	ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Note this will clear all forced interrupts - this is done for speed. */
+		INTC_CFRC = 0x3E;
+		vTaskSwitchContext();
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
+}
+/*-----------------------------------------------------------*/
+
+void interrupt VectorNumber_Vrtc vPortTickISR( void )
+{
+uint32_t ulSavedInterruptMask;
+
+	/* Clear the interrupt. */
+	RTCSC |= RTCSC_RTIF_MASK;
+
+	/* Increment the RTOS tick. */
+	ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			taskYIELD();
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/portasm.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/portasm.S
new file mode 100644
index 0000000..b05e20e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/portasm.S
@@ -0,0 +1,130 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Purpose: Lowest level routines for all ColdFire processors.
+ *
+ * Notes:
+ * 
+ * ulPortSetIPL() and mcf5xxx_wr_cacr() copied with permission from FreeScale
+ * supplied source files.
+ */
+
+    .global ulPortSetIPL
+    .global _ulPortSetIPL
+    .global mcf5xxx_wr_cacrx
+    .global _mcf5xxx_wr_cacrx
+    .global vPortYieldISR
+    .global _vPortYieldISR
+    .global vPortStartFirstTask
+    .global _vPortStartFirstTask
+    .extern _pxCurrentTCB
+    .extern _vPortYieldHandler
+
+    .text
+
+.macro portSAVE_CONTEXT
+
+	lea.l		(-60, sp), sp
+	movem.l		d0-a6, (sp)
+	move.l		_pxCurrentTCB, a0
+	move.l		sp, (a0)
+
+	.endm
+
+.macro portRESTORE_CONTEXT
+
+	move.l		_pxCurrentTCB, a0
+	move.l		(a0), sp
+	movem.l		(sp), d0-a6
+	lea.l		(60, sp), sp
+	rte
+
+	.endm
+
+/********************************************************************/
+/*
+ * This routines changes the IPL to the value passed into the routine.
+ * It also returns the old IPL value back.
+ * Calling convention from C:
+ *   old_ipl = asm_set_ipl(new_ipl);
+ * For the Diab Data C compiler, it passes return value thru D0.
+ * Note that only the least significant three bits of the passed
+ * value are used.
+ */
+
+ulPortSetIPL:
+_ulPortSetIPL:
+    link    A6,#-8
+    movem.l D6-D7,(SP)
+
+    move.w  SR,D7       /* current sr    */
+
+    move.l  D7,D6       /* prepare return value  */
+    andi.l  #0x0700,D6  /* mask out IPL  */
+    lsr.l   #8,D6       /* IPL   */
+
+    andi.l  #0x07,D0    /* least significant three bits  */
+    lsl.l   #8,D0       /* move over to make mask    */
+
+    andi.l  #0x0000F8FF,D7  /* zero out current IPL  */
+    or.l    D0,D7           /* place new IPL in sr   */
+    move.w  D7,SR
+
+	move.l	D6, D0		/* Return value in D0. */
+    movem.l (SP),D6-D7
+    lea     8(SP),SP
+    unlk    A6
+    rts
+/********************************************************************/
+
+mcf5xxx_wr_cacrx:
+_mcf5xxx_wr_cacrx:
+    move.l  4(sp),d0
+    .long   0x4e7b0002  /* movec d0,cacr   */
+    nop
+    rts
+
+/********************************************************************/
+
+/* Yield interrupt. */
+_vPortYieldISR:
+vPortYieldISR:
+	portSAVE_CONTEXT
+	jsr _vPortYieldHandler
+	portRESTORE_CONTEXT
+
+/********************************************************************/
+
+
+vPortStartFirstTask:
+_vPortStartFirstTask:
+	portRESTORE_CONTEXT
+
+    .end
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/portmacro.h
new file mode 100644
index 0000000..0a18bc7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/portmacro.h
@@ -0,0 +1,115 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			4
+#define portSTACK_GROWTH			-1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortSetIPL( uint32_t );
+#define portDISABLE_INTERRUPTS()	ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portENABLE_INTERRUPTS()		ulPortSetIPL( 0 )
+
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+
+extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
+extern void vPortClearInterruptMaskFromISR( UBaseType_t );
+#define portSET_INTERRUPT_MASK_FROM_ISR()	ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+#define portNOP()	asm volatile ( "nop" )
+
+/* Context switches are requested using the force register. */
+#define portYIELD()	INTC_SFRC = 0x3E; portNOP(); portNOP(); portNOP(); portNOP(); portNOP()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#define portEND_SWITCHING_ISR( xSwitchRequired )	if( xSwitchRequired != pdFALSE )	\
+													{									\
+														portYIELD();					\
+													}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/port.c
new file mode 100644
index 0000000..6059756
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/port.c
@@ -0,0 +1,147 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+
+#define portINITIAL_FORMAT_VECTOR		( ( StackType_t ) 0x4000 )
+
+/* Supervisor mode set. */
+#define portINITIAL_STATUS_REGISTER		( ( StackType_t ) 0x2000)
+
+/* Used to keep track of the number of nested calls to taskENTER_CRITICAL().  This
+will be set to 0 prior to the first task being started. */
+static uint32_t ulCriticalNesting = 0x9999UL;
+
+
+#define portSAVE_CONTEXT()				\
+	lea.l		(-60, %sp), %sp;		\
+	movem.l		%d0-%fp, (%sp);			\
+	move.l		pxCurrentTCB, %a0;		\
+	move.l		%sp, (%a0);
+
+#define portRESTORE_CONTEXT()			\
+	move.l		pxCurrentTCB, %a0;		\
+	move.l		(%a0), %sp;				\
+	movem.l		(%sp), %d0-%fp;			\
+	lea.l		%sp@(60), %sp;			\
+	rte
+
+
+
+/*-----------------------------------------------------------*/
+
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	*pxTopOfStack = ( StackType_t ) pvParameters;
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) 0xDEADBEEF;
+	pxTopOfStack--;
+
+	/* Exception stack frame starts with the return address. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER );
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0x0; /*FP*/
+	pxTopOfStack -= 14; /* A5 to D0. */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+
+	ulCriticalNesting = 0UL;
+
+	/* Configure the interrupts used by this port. */
+	vApplicationSetupInterrupts();
+
+	/* Start the first task executing. */
+	vPortStartFirstTask();
+
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented as there is nothing to return to. */
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	if( ulCriticalNesting == 0UL )
+	{
+		/* Guard against context switches being pended simultaneously with a
+		critical section being entered. */
+		do
+		{
+			portDISABLE_INTERRUPTS();
+			if( MCF_INTC0_INTFRCH == 0UL )
+			{
+				break;
+			}
+
+			portENABLE_INTERRUPTS();
+
+		} while( 1 );
+	}
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	ulCriticalNesting--;
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortYieldHandler( void )
+{
+uint32_t ulSavedInterruptMask;
+
+	ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+		/* Note this will clear all forced interrupts - this is done for speed. */
+		MCF_INTC0_INTFRCL = 0;
+		vTaskSwitchContext();
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/portasm.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/portasm.S
new file mode 100644
index 0000000..c20204e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/portasm.S
@@ -0,0 +1,130 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Purpose: Lowest level routines for all ColdFire processors.
+ *
+ * Notes:
+ * 
+ * ulPortSetIPL() and mcf5xxx_wr_cacr() copied with permission from FreeScale
+ * supplied source files.
+ */
+
+    .global ulPortSetIPL
+    .global _ulPortSetIPL
+    .global mcf5xxx_wr_cacrx
+    .global _mcf5xxx_wr_cacrx
+    .global vPortYieldISR
+    .global _vPortYieldISR
+    .global vPortStartFirstTask
+    .global _vPortStartFirstTask
+    .extern _pxCurrentTCB
+    .extern _vPortYieldHandler
+
+    .text
+
+.macro portSAVE_CONTEXT
+
+	lea.l		(-60, sp), sp
+	movem.l		d0-a6, (sp)
+	move.l		_pxCurrentTCB, a0
+	move.l		sp, (a0)
+
+	.endm
+
+.macro portRESTORE_CONTEXT
+
+	move.l		_pxCurrentTCB, a0
+	move.l		(a0), sp
+	movem.l		(sp), d0-a6
+	lea.l		(60, sp), sp
+	rte
+
+	.endm
+
+/********************************************************************/
+/*
+ * This routines changes the IPL to the value passed into the routine.
+ * It also returns the old IPL value back.
+ * Calling convention from C:
+ *   old_ipl = asm_set_ipl(new_ipl);
+ * For the Diab Data C compiler, it passes return value thru D0.
+ * Note that only the least significant three bits of the passed
+ * value are used.
+ */
+
+ulPortSetIPL:
+_ulPortSetIPL:
+    link    A6,#-8
+    movem.l D6-D7,(SP)
+
+    move.w  SR,D7       /* current sr    */
+
+    move.l  D7,D0       /* prepare return value  */
+    andi.l  #0x0700,D0  /* mask out IPL  */
+    lsr.l   #8,D0       /* IPL   */
+
+    move.l  8(A6),D6    /* get argument  */
+    andi.l  #0x07,D6    /* least significant three bits  */
+    lsl.l   #8,D6       /* move over to make mask    */
+
+    andi.l  #0x0000F8FF,D7  /* zero out current IPL  */
+    or.l    D6,D7           /* place new IPL in sr   */
+    move.w  D7,SR
+
+    movem.l (SP),D6-D7
+    lea     8(SP),SP
+    unlk    A6
+    rts
+/********************************************************************/
+
+mcf5xxx_wr_cacrx:
+_mcf5xxx_wr_cacrx:
+    move.l  4(sp),d0
+    .long   0x4e7b0002  /* movec d0,cacr   */
+    nop
+    rts
+
+/********************************************************************/
+
+/* Yield interrupt. */
+_vPortYieldISR:
+vPortYieldISR:
+	portSAVE_CONTEXT
+	jsr _vPortYieldHandler
+	portRESTORE_CONTEXT
+
+/********************************************************************/
+
+
+vPortStartFirstTask:
+_vPortStartFirstTask:
+	portRESTORE_CONTEXT
+
+    .end
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/portmacro.h
new file mode 100644
index 0000000..a2092cf
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/portmacro.h
@@ -0,0 +1,114 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			4
+#define portSTACK_GROWTH			-1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+uint32_t ulPortSetIPL( uint32_t );
+#define portDISABLE_INTERRUPTS()	ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portENABLE_INTERRUPTS()		ulPortSetIPL( 0 )
+
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+
+extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
+extern void vPortClearInterruptMaskFromISR( UBaseType_t );
+#define portSET_INTERRUPT_MASK_FROM_ISR()	ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+#define portNOP()	asm volatile ( 	"nop" )
+
+/* Note this will overwrite all other bits in the force register, it is done this way for speed. */
+#define portYIELD()			MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP() /* -32 as we are using the high word of the 64bit mask. */
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#define portEND_SWITCHING_ISR( xSwitchRequired )	if( xSwitchRequired != pdFALSE )	\
+													{									\
+														portYIELD();					\
+													}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/HCS12/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/HCS12/port.c
new file mode 100644
index 0000000..b27341c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/HCS12/port.c
@@ -0,0 +1,237 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the HCS12 port.
+ *----------------------------------------------------------*/
+
+
+/*
+ * Configure a timer to generate the RTOS tick at the frequency specified 
+ * within FreeRTOSConfig.h.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/* Interrupt service routines have to be in non-banked memory - as does the
+scheduler startup function. */
+#pragma CODE_SEG __NEAR_SEG NON_BANKED
+
+	/* Manual context switch function.  This is the SWI ISR. */
+	void interrupt vPortYield( void );
+
+	/* Tick context switch function.  This is the timer ISR. */
+	void interrupt vPortTickInterrupt( void );
+	
+	/* Simply called by xPortStartScheduler().  xPortStartScheduler() does not
+	start the scheduler directly because the header file containing the 
+	xPortStartScheduler() prototype is part of the common kernel code, and 
+	therefore cannot use the CODE_SEG pragma. */
+	static BaseType_t xBankedStartScheduler( void );
+
+#pragma CODE_SEG DEFAULT
+
+/* Calls to portENTER_CRITICAL() can be nested.  When they are nested the 
+critical section should not be left (i.e. interrupts should not be re-enabled)
+until the nesting depth reaches 0.  This variable simply tracks the nesting 
+depth.  Each task maintains it's own critical nesting depth variable so 
+uxCriticalNesting is saved and restored from the task stack during a context
+switch. */
+volatile UBaseType_t uxCriticalNesting = 0xff;
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* 
+		Place a few bytes of known values on the bottom of the stack.
+		This can be uncommented to provide useful stack markers when debugging.
+
+		*pxTopOfStack = ( StackType_t ) 0x11;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x22;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x33;
+		pxTopOfStack--;
+	*/
+
+
+
+	/* Setup the initial stack of the task.  The stack is set exactly as 
+	expected by the portRESTORE_CONTEXT() macro.  In this case the stack as
+	expected by the HCS12 RTI instruction. */
+
+
+	/* The address of the task function is placed in the stack byte at a time. */
+	*pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 1 );
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 0 );
+	pxTopOfStack--;
+
+	/* Next are all the registers that form part of the task context. */
+
+	/* Y register */
+	*pxTopOfStack = ( StackType_t ) 0xff;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xee;
+	pxTopOfStack--;
+
+	/* X register */
+	*pxTopOfStack = ( StackType_t ) 0xdd;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xcc;
+	pxTopOfStack--;
+ 
+	/* A register contains parameter high byte. */
+	*pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 0 );
+	pxTopOfStack--;
+
+	/* B register contains parameter low byte. */
+	*pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 1 );
+	pxTopOfStack--;
+
+	/* CCR: Note that when the task starts interrupts will be enabled since
+	"I" bit of CCR is cleared */
+	*pxTopOfStack = ( StackType_t ) 0x00;
+	pxTopOfStack--;
+	
+	#ifdef BANKED_MODEL
+		/* The page of the task. */
+		*pxTopOfStack = ( StackType_t ) ( ( int ) pxCode );
+		pxTopOfStack--;
+	#endif
+	
+	/* Finally the critical nesting depth is initialised with 0 (not within
+	a critical section). */
+	*pxTopOfStack = ( StackType_t ) 0x00;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the HCS12 port will get stopped. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+	TickTimer_SetFreqHz( configTICK_RATE_HZ );
+	TickTimer_Enable();
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* xPortStartScheduler() does not start the scheduler directly because 
+	the header file containing the xPortStartScheduler() prototype is part 
+	of the common kernel code, and therefore cannot use the CODE_SEG pragma. 
+	Instead it simply calls the locally defined xBankedStartScheduler() - 
+	which does use the CODE_SEG pragma. */
+
+	return xBankedStartScheduler();
+}
+/*-----------------------------------------------------------*/
+
+#pragma CODE_SEG __NEAR_SEG NON_BANKED
+
+static BaseType_t xBankedStartScheduler( void )
+{
+	/* Configure the timer that will generate the RTOS tick.  Interrupts are
+	disabled when this function is called. */
+	prvSetupTimerInterrupt();
+
+	/* Restore the context of the first task. */
+	portRESTORE_CONTEXT();
+
+	/* Simulate the end of an interrupt to start the scheduler off. */
+	__asm( "rti" );
+
+	/* Should not get here! */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Context switch functions.  These are both interrupt service routines.
+ */
+
+/*
+ * Manual context switch forced by calling portYIELD().  This is the SWI
+ * handler.
+ */
+void interrupt vPortYield( void )
+{
+	portSAVE_CONTEXT();
+	vTaskSwitchContext();
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * RTOS tick interrupt service routine.  If the cooperative scheduler is 
+ * being used then this simply increments the tick count.  If the 
+ * preemptive scheduler is being used a context switch can occur.
+ */
+void interrupt vPortTickInterrupt( void )
+{
+	#if configUSE_PREEMPTION == 1
+	{
+		/* A context switch might happen so save the context. */
+		portSAVE_CONTEXT();
+
+		/* Increment the tick ... */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			vTaskSwitchContext();
+		}
+
+		TFLG1 = 1;								   
+
+		/* Restore the context of a task - which may be a different task
+		to that interrupted. */
+		portRESTORE_CONTEXT();	
+	}
+	#else
+	{
+		xTaskIncrementTick();
+		TFLG1 = 1;
+	}
+	#endif
+}
+
+#pragma CODE_SEG DEFAULT
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/HCS12/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/HCS12/portmacro.h
new file mode 100644
index 0000000..e28d788
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/CodeWarrior/HCS12/portmacro.h
@@ -0,0 +1,202 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint8_t
+#define portBASE_TYPE	char
+
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			1
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portYIELD()					__asm( "swi" );
+#define portNOP()					__asm( "nop" );
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+#define portENABLE_INTERRUPTS()				__asm( "cli" )
+#define portDISABLE_INTERRUPTS()			__asm( "sei" )
+
+/*
+ * Disable interrupts before incrementing the count of critical section nesting.
+ * The nesting count is maintained so we know when interrupts should be
+ * re-enabled.  Once interrupts are disabled the nesting count can be accessed
+ * directly.  Each task maintains its own nesting count.
+ */
+#define portENTER_CRITICAL()  									\
+{																\
+	extern volatile UBaseType_t uxCriticalNesting;	\
+																\
+	portDISABLE_INTERRUPTS();									\
+	uxCriticalNesting++;										\
+}
+
+/*
+ * Interrupts are disabled so we can access the nesting count directly.  If the
+ * nesting is found to be 0 (no nesting) then we are leaving the critical
+ * section and interrupts can be re-enabled.
+ */
+#define  portEXIT_CRITICAL()									\
+{																\
+	extern volatile UBaseType_t uxCriticalNesting;	\
+																\
+	uxCriticalNesting--;										\
+	if( uxCriticalNesting == 0 )								\
+	{															\
+		portENABLE_INTERRUPTS();								\
+	}															\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/*
+ * These macros are very simple as the processor automatically saves and
+ * restores its registers as interrupts are entered and exited.  In
+ * addition to the (automatically stacked) registers we also stack the
+ * critical nesting count.  Each task maintains its own critical nesting
+ * count as it is legitimate for a task to yield from within a critical
+ * section.  If the banked memory model is being used then the PPAGE
+ * register is also stored as part of the tasks context.
+ */
+
+#ifdef BANKED_MODEL
+	/*
+	 * Load the stack pointer for the task, then pull the critical nesting
+	 * count and PPAGE register from the stack.  The remains of the
+	 * context are restored by the RTI instruction.
+	 */
+	#define portRESTORE_CONTEXT()									\
+	{																\
+		extern volatile void * pxCurrentTCB;						\
+		extern volatile UBaseType_t uxCriticalNesting;	\
+																	\
+		__asm( "ldx pxCurrentTCB" );								\
+		__asm( "lds 0, x" );										\
+		__asm( "pula" );											\
+		__asm( "staa uxCriticalNesting" );							\
+		__asm( "pula" );											\
+		__asm( "staa 0x30" ); /* 0x30 = PPAGE */					\
+	}
+
+	/*
+	 * By the time this macro is called the processor has already stacked the
+	 * registers.  Simply stack the nesting count and PPAGE value, then save
+	 * the task stack pointer.
+	 */
+	#define portSAVE_CONTEXT()										\
+	{																\
+		extern volatile void * pxCurrentTCB;						\
+		extern volatile UBaseType_t uxCriticalNesting;	\
+																	\
+		__asm( "ldaa 0x30" );  /* 0x30 = PPAGE */					\
+		__asm( "psha" );											\
+		__asm( "ldaa uxCriticalNesting" );							\
+		__asm( "psha" );											\
+		__asm( "ldx pxCurrentTCB" );								\
+		__asm( "sts 0, x" );										\
+	}
+#else
+
+	/*
+	 * These macros are as per the BANKED versions above, but without saving
+	 * and restoring the PPAGE register.
+	 */
+
+	#define portRESTORE_CONTEXT()									\
+	{																\
+		extern volatile void * pxCurrentTCB;						\
+		extern volatile UBaseType_t uxCriticalNesting;	\
+																	\
+		__asm( "ldx pxCurrentTCB" );								\
+		__asm( "lds 0, x" );										\
+		__asm( "pula" );											\
+		__asm( "staa uxCriticalNesting" );							\
+	}
+
+	#define portSAVE_CONTEXT()										\
+	{																\
+		extern volatile void * pxCurrentTCB;						\
+		extern volatile UBaseType_t uxCriticalNesting;	\
+																	\
+		__asm( "ldaa uxCriticalNesting" );							\
+		__asm( "psha" );											\
+		__asm( "ldx pxCurrentTCB" );								\
+		__asm( "sts 0, x" );										\
+	}
+#endif
+
+/*
+ * Utility macro to call macros above in correct order in order to perform a
+ * task switch from within a standard ISR.  This macro can only be used if
+ * the ISR does not use any local (stack) variables.  If the ISR uses stack
+ * variables portYIELD() should be used in it's place.
+ */
+#define portTASK_SWITCH_FROM_ISR()								\
+	portSAVE_CONTEXT();											\
+	vTaskSwitchContext();										\
+	portRESTORE_CONTEXT();
+
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Common/mpu_wrappers.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Common/mpu_wrappers.c
new file mode 100644
index 0000000..fd4db0b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Common/mpu_wrappers.c
@@ -0,0 +1,1337 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Implementation of the wrapper functions used to raise the processor privilege
+ * before calling a standard FreeRTOS API function.
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+#include "event_groups.h"
+#include "stream_buffer.h"
+#include "mpu_prototypes.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+BaseType_t xPortRaisePrivilege( void ) FREERTOS_SYSTEM_CALL;
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+void vPortResetPrivilege( BaseType_t xRunningPrivileged );
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortRaisePrivilege( void ) /* FREERTOS_SYSTEM_CALL */
+{
+BaseType_t xRunningPrivileged;
+
+	/* Check whether the processor is already privileged. */
+	xRunningPrivileged = portIS_PRIVILEGED();
+
+	/* If the processor is not already privileged, raise privilege. */
+	if( xRunningPrivileged != pdTRUE )
+	{
+		portRAISE_PRIVILEGE();
+	}
+
+	return xRunningPrivileged;
+}
+/*-----------------------------------------------------------*/
+
+void vPortResetPrivilege( BaseType_t xRunningPrivileged )
+{
+	if( xRunningPrivileged != pdTRUE )
+	{
+		portRESET_PRIVILEGE();
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTaskCreateRestricted( pxTaskDefinition, pxCreatedTask );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif /* conifgSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTaskCreateRestrictedStatic( pxTaskDefinition, pxCreatedTask );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif /* conifgSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode, const char * const pcName, uint16_t usStackDepth, void *pvParameters, UBaseType_t uxPriority, TaskHandle_t *pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) /* FREERTOS_SYSTEM_CALL */
+	{
+	TaskHandle_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const xRegions ) /* FREERTOS_SYSTEM_CALL */
+{
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	vTaskAllocateMPURegions( xTask, xRegions );
+	vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+	void MPU_vTaskDelete( TaskHandle_t pxTaskToDelete ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		vTaskDelete( pxTaskToDelete );
+		vPortResetPrivilege( xRunningPrivileged );
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelayUntil == 1 )
+	void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, TickType_t xTimeIncrement ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );
+		vPortResetPrivilege( xRunningPrivileged );
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskAbortDelay == 1 )
+	BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTaskAbortDelay( xTask );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelay == 1 )
+	void MPU_vTaskDelay( TickType_t xTicksToDelay ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		vTaskDelay( xTicksToDelay );
+		vPortResetPrivilege( xRunningPrivileged );
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+	UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */
+	{
+	UBaseType_t uxReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		uxReturn = uxTaskPriorityGet( pxTask );
+		vPortResetPrivilege( xRunningPrivileged );
+		return uxReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskPrioritySet == 1 )
+	void MPU_vTaskPrioritySet( TaskHandle_t pxTask, UBaseType_t uxNewPriority ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		vTaskPrioritySet( pxTask, uxNewPriority );
+		vPortResetPrivilege( xRunningPrivileged );
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_eTaskGetState == 1 )
+	eTaskState MPU_eTaskGetState( TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+	eTaskState eReturn;
+
+		eReturn = eTaskGetState( pxTask );
+		vPortResetPrivilege( xRunningPrivileged );
+		return eReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState );
+		vPortResetPrivilege( xRunningPrivileged );
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+	TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
+	{
+	TaskHandle_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTaskGetIdleTaskHandle();
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+	void MPU_vTaskSuspend( TaskHandle_t pxTaskToSuspend ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		vTaskSuspend( pxTaskToSuspend );
+		vPortResetPrivilege( xRunningPrivileged );
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+	void MPU_vTaskResume( TaskHandle_t pxTaskToResume ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		vTaskResume( pxTaskToResume );
+		vPortResetPrivilege( xRunningPrivileged );
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+void MPU_vTaskSuspendAll( void ) /* FREERTOS_SYSTEM_CALL */
+{
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	vTaskSuspendAll();
+	vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t MPU_xTaskResumeAll( void ) /* FREERTOS_SYSTEM_CALL */
+{
+BaseType_t xReturn;
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	xReturn = xTaskResumeAll();
+	vPortResetPrivilege( xRunningPrivileged );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t MPU_xTaskGetTickCount( void ) /* FREERTOS_SYSTEM_CALL */
+{
+TickType_t xReturn;
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	xReturn = xTaskGetTickCount();
+	vPortResetPrivilege( xRunningPrivileged );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* FREERTOS_SYSTEM_CALL */
+{
+UBaseType_t uxReturn;
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	uxReturn = uxTaskGetNumberOfTasks();
+	vPortResetPrivilege( xRunningPrivileged );
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */
+{
+char *pcReturn;
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	pcReturn = pcTaskGetName( xTaskToQuery );
+	vPortResetPrivilege( xRunningPrivileged );
+	return pcReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+	TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) /* FREERTOS_SYSTEM_CALL */
+	{
+	TaskHandle_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTaskGetHandle( pcNameToQuery );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+	void MPU_vTaskList( char *pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		vTaskList( pcWriteBuffer );
+		vPortResetPrivilege( xRunningPrivileged );
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+	void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		vTaskGetRunTimeStats( pcWriteBuffer );
+		vPortResetPrivilege( xRunningPrivileged );
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+	TickType_t MPU_xTaskGetIdleRunTimeCounter( void ) /* FREERTOS_SYSTEM_CALL */
+	{
+	TickType_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTaskGetIdleRunTimeCounter();
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+	void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxTagValue ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		vTaskSetApplicationTaskTag( xTask, pxTagValue );
+		vPortResetPrivilege( xRunningPrivileged );
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+	TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+	{
+	TaskHookFunction_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTaskGetApplicationTaskTag( xTask );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+	void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue );
+		vPortResetPrivilege( xRunningPrivileged );
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+	void *MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) /* FREERTOS_SYSTEM_CALL */
+	{
+	void *pvReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		pvReturn = pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex );
+		vPortResetPrivilege( xRunningPrivileged );
+		return pvReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+	BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+	UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t *pxTaskStatusArray, UBaseType_t uxArraySize, uint32_t *pulTotalRunTime ) /* FREERTOS_SYSTEM_CALL */
+	{
+	UBaseType_t uxReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		uxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime );
+		vPortResetPrivilege( xRunningPrivileged );
+		return uxReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+	UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+	{
+	UBaseType_t uxReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		uxReturn = uxTaskGetStackHighWaterMark( xTask );
+		vPortResetPrivilege( xRunningPrivileged );
+		return uxReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+	configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+	{
+	configSTACK_DEPTH_TYPE uxReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		uxReturn = uxTaskGetStackHighWaterMark2( xTask );
+		vPortResetPrivilege( xRunningPrivileged );
+		return uxReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 )
+	TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
+	{
+	TaskHandle_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTaskGetCurrentTaskHandle();
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetSchedulerState == 1 )
+	BaseType_t MPU_xTaskGetSchedulerState( void ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTaskGetSchedulerState();
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* FREERTOS_SYSTEM_CALL */
+{
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	vTaskSetTimeOutState( pxTimeOut );
+	vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+BaseType_t xReturn;
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	xReturn = xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait );
+	vPortResetPrivilege( xRunningPrivileged );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+	BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTaskGenericNotify( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+	BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTaskNotifyWait( ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+	uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+	{
+	uint32_t ulReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		ulReturn = ulTaskNotifyTake( xClearCountOnExit, xTicksToWait );
+		vPortResetPrivilege( xRunningPrivileged );
+		return ulReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+	BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTaskNotifyStateClear( xTask );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength, UBaseType_t uxItemSize, uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
+	{
+	QueueHandle_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
+	{
+	QueueHandle_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue, BaseType_t xNewQueue ) /* FREERTOS_SYSTEM_CALL */
+{
+BaseType_t xReturn;
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	xReturn = xQueueGenericReset( pxQueue, xNewQueue );
+	vPortResetPrivilege( xRunningPrivileged );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition ) /* FREERTOS_SYSTEM_CALL */
+{
+BaseType_t xReturn;
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );
+	vPortResetPrivilege( xRunningPrivileged );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t pxQueue ) /* FREERTOS_SYSTEM_CALL */
+{
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+UBaseType_t uxReturn;
+
+	uxReturn = uxQueueMessagesWaiting( pxQueue );
+	vPortResetPrivilege( xRunningPrivileged );
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
+{
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+UBaseType_t uxReturn;
+
+	uxReturn = uxQueueSpacesAvailable( xQueue );
+	vPortResetPrivilege( xRunningPrivileged );
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t MPU_xQueueReceive( QueueHandle_t pxQueue, void * const pvBuffer, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+BaseType_t xReturn;
+
+	xReturn = xQueueReceive( pxQueue, pvBuffer, xTicksToWait );
+	vPortResetPrivilege( xRunningPrivileged );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+BaseType_t xReturn;
+
+	xReturn = xQueuePeek( xQueue, pvBuffer, xTicksToWait );
+	vPortResetPrivilege( xRunningPrivileged );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+BaseType_t xReturn;
+
+	xReturn = xQueueSemaphoreTake( xQueue, xTicksToWait );
+	vPortResetPrivilege( xRunningPrivileged );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+	TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+	void * xReturn;
+
+		xReturn = xQueueGetMutexHolder( xSemaphore );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+	QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
+	{
+	QueueHandle_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xQueueCreateMutex( ucQueueType );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */
+	{
+	QueueHandle_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xQueueCreateMutexStatic( ucQueueType, pxStaticQueue );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+	QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue, UBaseType_t uxInitialCount ) /* FREERTOS_SYSTEM_CALL */
+	{
+	QueueHandle_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */
+	{
+	QueueHandle_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+	BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xBlockTime ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+	BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t xMutex ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xQueueGiveMutexRecursive( xMutex );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+	QueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength ) /* FREERTOS_SYSTEM_CALL */
+	{
+	QueueSetHandle_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xQueueCreateSet( uxEventQueueLength );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+	QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t xBlockTimeTicks ) /* FREERTOS_SYSTEM_CALL */
+	{
+	QueueSetMemberHandle_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xQueueSelectFromSet( xQueueSet, xBlockTimeTicks );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+	BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xQueueAddToSet( xQueueOrSemaphore, xQueueSet );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+	BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet );
+		vPortResetPrivilege( xRunningPrivileged );
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if configQUEUE_REGISTRY_SIZE > 0
+	void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		vQueueAddToRegistry( xQueue, pcName );
+
+		vPortResetPrivilege( xRunningPrivileged );
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if configQUEUE_REGISTRY_SIZE > 0
+	void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		vQueueUnregisterQueue( xQueue );
+
+		vPortResetPrivilege( xRunningPrivileged );
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if configQUEUE_REGISTRY_SIZE > 0
+	const char *MPU_pcQueueGetName( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+	const char *pcReturn;
+
+		pcReturn = pcQueueGetName( xQueue );
+
+		vPortResetPrivilege( xRunningPrivileged );
+		return pcReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+void MPU_vQueueDelete( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
+{
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	vQueueDelete( xQueue );
+
+	vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	void *MPU_pvPortMalloc( size_t xSize ) /* FREERTOS_SYSTEM_CALL */
+	{
+	void *pvReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		pvReturn = pvPortMalloc( xSize );
+
+		vPortResetPrivilege( xRunningPrivileged );
+
+		return pvReturn;
+	}
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	void MPU_vPortFree( void *pv ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		vPortFree( pv );
+
+		vPortResetPrivilege( xRunningPrivileged );
+	}
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	void MPU_vPortInitialiseBlocks( void ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		vPortInitialiseBlocks();
+
+		vPortResetPrivilege( xRunningPrivileged );
+	}
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	size_t MPU_xPortGetFreeHeapSize( void ) /* FREERTOS_SYSTEM_CALL */
+	{
+	size_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xPortGetFreeHeapSize();
+
+		vPortResetPrivilege( xRunningPrivileged );
+
+		return xReturn;
+	}
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) )
+	TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) /* FREERTOS_SYSTEM_CALL */
+	{
+	TimerHandle_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTimerCreate( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction );
+		vPortResetPrivilege( xRunningPrivileged );
+
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) )
+	TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) /* FREERTOS_SYSTEM_CALL */
+	{
+	TimerHandle_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxTimerBuffer );
+		vPortResetPrivilege( xRunningPrivileged );
+
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+	void *MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+	{
+	void * pvReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		pvReturn = pvTimerGetTimerID( xTimer );
+		vPortResetPrivilege( xRunningPrivileged );
+
+		return pvReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+	void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		vTimerSetTimerID( xTimer, pvNewID );
+		vPortResetPrivilege( xRunningPrivileged );
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+	BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTimerIsTimerActive( xTimer );
+		vPortResetPrivilege( xRunningPrivileged );
+
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+	TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
+	{
+	TaskHandle_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTimerGetTimerDaemonTaskHandle();
+		vPortResetPrivilege( xRunningPrivileged );
+
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+	BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTimerPendFunctionCall( xFunctionToPend, pvParameter1, ulParameter2, xTicksToWait );
+		vPortResetPrivilege( xRunningPrivileged );
+
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+	void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		vTimerSetReloadMode( xTimer, uxAutoReload );
+		vPortResetPrivilege( xRunningPrivileged );
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+	const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+	{
+	const char * pcReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		pcReturn = pcTimerGetName( xTimer );
+		vPortResetPrivilege( xRunningPrivileged );
+
+		return pcReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+	TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+	{
+	TickType_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTimerGetPeriod( xTimer );
+		vPortResetPrivilege( xRunningPrivileged );
+
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+	TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+	{
+	TickType_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTimerGetExpiryTime( xTimer );
+		vPortResetPrivilege( xRunningPrivileged );
+
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+	BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+	{
+	BaseType_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
+		vPortResetPrivilege( xRunningPrivileged );
+
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	EventGroupHandle_t MPU_xEventGroupCreate( void ) /* FREERTOS_SYSTEM_CALL */
+	{
+	EventGroupHandle_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xEventGroupCreate();
+		vPortResetPrivilege( xRunningPrivileged );
+
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) /* FREERTOS_SYSTEM_CALL */
+	{
+	EventGroupHandle_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xEventGroupCreateStatic( pxEventGroupBuffer );
+		vPortResetPrivilege( xRunningPrivileged );
+
+		return xReturn;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+EventBits_t xReturn;
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	xReturn = xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
+	vPortResetPrivilege( xRunningPrivileged );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */
+{
+EventBits_t xReturn;
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	xReturn = xEventGroupClearBits( xEventGroup, uxBitsToClear );
+	vPortResetPrivilege( xRunningPrivileged );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */
+{
+EventBits_t xReturn;
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	xReturn = xEventGroupSetBits( xEventGroup, uxBitsToSet );
+	vPortResetPrivilege( xRunningPrivileged );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+EventBits_t xReturn;
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	xReturn = xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
+	vPortResetPrivilege( xRunningPrivileged );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* FREERTOS_SYSTEM_CALL */
+{
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	vEventGroupDelete( xEventGroup );
+	vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+size_t xReturn;
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	xReturn = xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait );
+	vPortResetPrivilege( xRunningPrivileged );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+{
+size_t xReturn;
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer );
+	vPortResetPrivilege( xRunningPrivileged );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+size_t xReturn;
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	xReturn = xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait );
+	vPortResetPrivilege( xRunningPrivileged );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+{
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	vStreamBufferDelete( xStreamBuffer );
+	vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+{
+BaseType_t xReturn;
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	xReturn = xStreamBufferIsFull( xStreamBuffer );
+	vPortResetPrivilege( xRunningPrivileged );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+{
+BaseType_t xReturn;
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	xReturn = xStreamBufferIsEmpty( xStreamBuffer );
+	vPortResetPrivilege( xRunningPrivileged );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+{
+BaseType_t xReturn;
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	xReturn = xStreamBufferReset( xStreamBuffer );
+	vPortResetPrivilege( xRunningPrivileged );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+{
+size_t xReturn;
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	xReturn = xStreamBufferSpacesAvailable( xStreamBuffer );
+	vPortResetPrivilege( xRunningPrivileged );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+{
+size_t xReturn;
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	xReturn = xStreamBufferBytesAvailable( xStreamBuffer );
+	vPortResetPrivilege( xRunningPrivileged );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */
+{
+BaseType_t xReturn;
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	xReturn = xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel );
+	vPortResetPrivilege( xRunningPrivileged );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) /* FREERTOS_SYSTEM_CALL */
+	{
+	StreamBufferHandle_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer );
+		vPortResetPrivilege( xRunningPrivileged );
+
+		return xReturn;
+	}
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+	{
+	StreamBufferHandle_t xReturn;
+	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+		xReturn = xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer, pucStreamBufferStorageArea, pxStaticStreamBuffer );
+		vPortResetPrivilege( xRunningPrivileged );
+
+		return xReturn;
+	}
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+
+/* Functions that the application writer wants to execute in privileged mode
+can be defined in application_defined_privileged_functions.h.  The functions
+must take the same format as those above whereby the privilege state on exit
+equals the privilege state on entry.  For example:
+
+void MPU_FunctionName( [parameters ] )
+{
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	FunctionName( [parameters ] );
+
+	vPortResetPrivilege( xRunningPrivileged );
+}
+*/
+
+#if configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS == 1
+	#include "application_defined_privileged_functions.h"
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/port.c
new file mode 100644
index 0000000..00c694c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/port.c
@@ -0,0 +1,238 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the Atmel AT91R40008
+ * port.
+ *
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in this file.  The ISR routines, which can only be compiled
+ * to ARM mode are contained in portISR.c.
+ *----------------------------------------------------------*/
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Hardware specific definitions. */
+#include "AT91R40008.h"
+#include "pio.h"
+#include "aic.h"
+#include "tc.h"
+
+/* Constants required to setup the task context. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING	( ( StackType_t ) 0 )
+#define portTICK_PRIORITY_6				( 6 )
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* 
+ * The scheduler can only be started from ARM mode, so 
+ * vPortISRStartFirstSTask() is defined in portISR.c. 
+ */
+extern void vPortISRStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+	
+	/* To ensure asserts in tasks.c don't fail, although in this case the assert
+	is not really required. */
+	pxTopOfStack--;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as 
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The last thing onto the stack is the status register, which is set for
+	system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	#ifdef THUMB_INTERWORK
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+	#endif
+
+	pxTopOfStack--;
+
+	/* Some optimisation levels use the stack differently to others.  This 
+	means the interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortISRStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the tick timer to generate the tick interrupts at the required frequency.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+volatile uint32_t ulDummy;
+
+	/* Enable clock to the tick timer... */
+	AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT;
+
+	/* Stop the tick timer... */
+	portTIMER_REG_BASE_PTR->TC_CCR = TC_CLKDIS;
+
+	/* Start with tick timer interrupts disabled... */
+	portTIMER_REG_BASE_PTR->TC_IDR = 0xFFFFFFFF;
+
+	/* Clear any pending tick timer interrupts... */
+	ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
+
+	/* Store interrupt handler function address in tick timer vector register...
+	The ISR installed depends on whether the preemptive or cooperative
+	scheduler is being used. */
+	#if configUSE_PREEMPTION == 1
+	{
+		extern void ( vPreemptiveTick )( void );
+		AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( uint32_t ) vPreemptiveTick;
+	}
+	#else  // else use cooperative scheduler
+	{
+		extern void ( vNonPreemptiveTick )( void );
+		AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( uint32_t ) vNonPreemptiveTick;
+	}
+	#endif
+
+	/* Tick timer interrupt level-sensitive, priority 6... */
+	AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6;
+
+	/* Enable the tick timer interrupt...
+
+	First at timer level */
+	portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS;
+
+	/* Then at the AIC level. */
+	AT91C_BASE_AIC->AIC_IECR = (1 << portTIMER_AIC_CHANNEL);
+
+	/* Calculate timer compare value to achieve the desired tick rate... */
+	if( (configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2) ) <= 0xFFFF )
+	{
+		/* The tick rate is fast enough for us to use the faster timer input
+		clock (main clock / 2). */
+		portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG;
+		portTIMER_REG_BASE_PTR->TC_RC  = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2);
+	}
+	else
+	{
+		/* We must use a slower timer input clock (main clock / 8) because the
+		tick rate is too slow for the faster input clock. */
+		portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG;
+		portTIMER_REG_BASE_PTR->TC_RC  = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 8);
+	}
+
+	/* Start tick timer... */
+	portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG | TC_CLKEN;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/portISR.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/portISR.c
new file mode 100644
index 0000000..ac1e40f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/portISR.c
@@ -0,0 +1,233 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*-----------------------------------------------------------
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c  The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
+
+/*
+	Changes from V3.2.4
+
+	+ The assembler statements are now included in a single asm block rather
+	  than each line having its own asm block.
+*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to handle interrupts. */
+#define portCLEAR_AIC_INTERRUPT		( ( uint32_t ) 0 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING		( ( uint32_t ) 0 )
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/*-----------------------------------------------------------*/
+
+/* ISR to handle manual context switches (from a call to taskYIELD()). */
+void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
+
+/* 
+ * The scheduler can only be started from ARM mode, hence the inclusion of this
+ * function here.
+ */
+void vPortISRStartFirstTask( void );
+/*-----------------------------------------------------------*/
+
+void vPortISRStartFirstTask( void )
+{
+	/* Simply start the scheduler.  This is included here as it can only be
+	called from ARM mode. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by portYIELD() or taskYIELD() to manually force a context switch.
+ *
+ * When a context switch is performed from the task level the saved task 
+ * context is made to look as if it occurred from within the tick ISR.  This
+ * way the same restore context function can be used when restoring the context
+ * saved from the ISR or that saved from a call to vPortYieldProcessor.
+ */
+void vPortYieldProcessor( void )
+{
+	/* Within an IRQ ISR the link register has an offset from the true return 
+	address, but an SWI ISR does not.  Add the offset manually so the same 
+	ISR return code can be used in both cases. */
+	asm volatile ( "ADD		LR, LR, #4" );
+
+	/* Perform the context switch.  First save the context of the current task. */
+	portSAVE_CONTEXT();
+
+	/* Find the highest priority task that is ready to run. */
+	vTaskSwitchContext();
+
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT();	
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * The ISR used for the scheduler tick depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+
+#if configUSE_PREEMPTION == 0
+
+	/* The cooperative scheduler requires a normal IRQ service routine to 
+	simply increment the system tick. */
+	void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
+	void vNonPreemptiveTick( void )
+	{		
+	static volatile uint32_t ulDummy;
+
+		/* Clear tick timer interrupt indication. */
+		ulDummy = portTIMER_REG_BASE_PTR->TC_SR;  
+
+		xTaskIncrementTick();
+
+		/* Acknowledge the interrupt at AIC level... */
+		AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;
+	}
+
+#else  /* else preemption is turned on */
+
+	/* The preemptive scheduler is defined as "naked" as the full context is
+	saved on entry as part of the context switch. */
+	void vPreemptiveTick( void ) __attribute__((naked));
+	void vPreemptiveTick( void )
+	{
+		/* Save the context of the interrupted task. */
+		portSAVE_CONTEXT();	
+
+		/* WARNING - Do not use local (stack) variables here.  Use globals
+					 if you must! */
+		static volatile uint32_t ulDummy;
+
+		/* Clear tick timer interrupt indication. */
+		ulDummy = portTIMER_REG_BASE_PTR->TC_SR;  
+
+		/* Increment the RTOS tick count, then look for the highest priority 
+		task that is ready to run. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			vTaskSwitchContext();
+		}
+
+		/* Acknowledge the interrupt at AIC level... */
+		AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;
+
+		/* Restore the context of the new task. */
+		portRESTORE_CONTEXT();
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to
+ * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then
+ * the utilities are defined as macros in portmacro.h - as per other ports.
+ */
+#ifdef THUMB_INTERWORK
+
+	void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	void vPortDisableInterruptsFromThumb( void )
+	{
+		asm volatile ( 
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.						*/
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+			
+	void vPortEnableInterruptsFromThumb( void )
+	{
+		asm volatile ( 
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/	
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/	
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.							*/	
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/	
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+
+#endif /* THUMB_INTERWORK */
+
+/* The code generated by the GCC compiler uses the stack in different ways at
+different optimisation levels.  The interrupt flags can therefore not always
+be saved to the stack.  Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 							*/
+	asm volatile ( 
+		"STMDB	SP!, {R0}			\n\t"	/* Push R0.								*/
+		"MRS	R0, CPSR			\n\t"	/* Get CPSR.							*/
+		"ORR	R0, R0, #0xC0		\n\t"	/* Disable IRQ, FIQ.					*/
+		"MSR	CPSR, R0			\n\t"	/* Write back modified value.			*/
+		"LDMIA	SP!, {R0}" );				/* Pop R0.								*/
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed 
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Enable interrupts as per portEXIT_CRITICAL().				*/
+			asm volatile ( 
+				"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	
+				"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	
+				"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	
+				"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	
+				"LDMIA	SP!, {R0}" );			/* Pop R0.						*/
+		}
+	}
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h
new file mode 100644
index 0000000..6f65665
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h
@@ -0,0 +1,255 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+	Changes from V3.2.3
+
+	+ Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
+
+	Changes from V3.2.4
+
+	+ Removed the use of the %0 parameter within the assembler macros and
+	  replaced them with hard coded registers.  This will ensure the
+	  assembler does not select the link register as the temp register as
+	  was occasionally happening previously.
+
+	+ The assembler statements are now included in a single asm block rather
+	  than each line having its own asm block.
+
+	Changes from V4.5.0
+
+	+ Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
+	  and replaced them with portYIELD_FROM_ISR() macro.  Application code
+	  should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+	  macros as per the V4.5.1 demo code.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+#define portYIELD()					asm volatile ( "SWI 0" )
+#define portNOP()					asm volatile ( "NOP" )
+
+/*
+ * These define the timer to use for generating the tick interrupt.
+ * They are put in this file so they can be shared between "port.c"
+ * and "portisr.c".
+ */
+#define portTIMER_REG_BASE_PTR		AT91C_BASE_TC0
+#define portTIMER_CLK_ENABLE_BIT	AT91C_PS_TC0
+#define portTIMER_AIC_CHANNEL		( ( uint32_t ) 4 )
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/*
+ * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
+ * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
+ * are included here for efficiency.  An attempt to call one from
+ * THUMB mode code will result in a compile time error.
+ */
+
+#define portRESTORE_CONTEXT()											\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile uint32_t ulCriticalNesting;					\
+																		\
+	/* Set the LR to the task stack. */									\
+	asm volatile (														\
+	"LDR		R0, =pxCurrentTCB								\n\t"	\
+	"LDR		R0, [R0]										\n\t"	\
+	"LDR		LR, [R0]										\n\t"	\
+																		\
+	/* The critical nesting depth is the first item on the stack. */	\
+	/* Load it into the ulCriticalNesting variable. */					\
+	"LDR		R0, =ulCriticalNesting							\n\t"	\
+	"LDMFD	LR!, {R1}											\n\t"	\
+	"STR		R1, [R0]										\n\t"	\
+																		\
+	/* Get the SPSR from the stack. */									\
+	"LDMFD	LR!, {R0}											\n\t"	\
+	"MSR		SPSR, R0										\n\t"	\
+																		\
+	/* Restore all system mode registers for the task. */				\
+	"LDMFD	LR, {R0-R14}^										\n\t"	\
+	"NOP														\n\t"	\
+																		\
+	/* Restore the return address. */									\
+	"LDR		LR, [LR, #+60]									\n\t"	\
+																		\
+	/* And return - correcting the offset in the LR to obtain the */	\
+	/* correct address. */												\
+	"SUBS	PC, LR, #4											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+/*-----------------------------------------------------------*/
+
+#define portSAVE_CONTEXT()												\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile uint32_t ulCriticalNesting;					\
+																		\
+	/* Push R0 as we are going to use the register. */					\
+	asm volatile (														\
+	"STMDB	SP!, {R0}											\n\t"	\
+																		\
+	/* Set R0 to point to the task stack pointer. */					\
+	"STMDB	SP,{SP}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	SP, SP, #4											\n\t"	\
+	"LDMIA	SP!,{R0}											\n\t"	\
+																		\
+	/* Push the return address onto the stack. */						\
+	"STMDB	R0!, {LR}											\n\t"	\
+																		\
+	/* Now we have saved LR we can use it instead of R0. */				\
+	"MOV	LR, R0												\n\t"	\
+																		\
+	/* Pop R0 so we can save it onto the system mode stack. */			\
+	"LDMIA	SP!, {R0}											\n\t"	\
+																		\
+	/* Push all the system mode registers onto the task stack. */		\
+	"STMDB	LR,{R0-LR}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	LR, LR, #60											\n\t"	\
+																		\
+	/* Push the SPSR onto the task stack. */							\
+	"MRS	R0, SPSR											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	"LDR	R0, =ulCriticalNesting								\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	/* Store the new top of stack for the task. */						\
+	"LDR	R0, =pxCurrentTCB									\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STR	LR, [R0]											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
+
+/* Critical section handling. */
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions in
+ * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not
+ * defined then the utilities are defined as macros here - as per other ports.
+ */
+
+#ifdef THUMB_INTERWORK
+
+	extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	#define portDISABLE_INTERRUPTS()	vPortDisableInterruptsFromThumb()
+	#define portENABLE_INTERRUPTS()		vPortEnableInterruptsFromThumb()
+
+#else
+
+	#define portDISABLE_INTERRUPTS()											\
+		asm volatile (															\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.			*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+	#define portENABLE_INTERRUPTS()												\
+		asm volatile (															\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+#endif /* THUMB_INTERWORK */
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h
new file mode 100644
index 0000000..a14279e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h
@@ -0,0 +1,2731 @@
+//  ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+//  ----------------------------------------------------------------------------
+//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  ----------------------------------------------------------------------------
+// File Name           : AT91SAM7X256.h
+// Object              : AT91SAM7X256 definitions
+// Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
+// 
+// CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
+// CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
+// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
+// CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
+// CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
+// CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
+// CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
+// CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
+// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
+// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
+// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
+// CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
+// CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
+// CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+//  ----------------------------------------------------------------------------
+
+#ifndef AT91SAM7X256_H
+#define AT91SAM7X256_H
+
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYS {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+	AT91_REG	 Reserved2[45]; 	// 
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved3[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved4[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+	AT91_REG	 Reserved5[54]; 	// 
+	AT91_REG	 PIOA_PER; 	// PIO Enable Register
+	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOA_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved6[1]; 	// 
+	AT91_REG	 PIOA_OER; 	// Output Enable Register
+	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOA_OSR; 	// Output Status Register
+	AT91_REG	 Reserved7[1]; 	// 
+	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved8[1]; 	// 
+	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved9[1]; 	// 
+	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved10[1]; 	// 
+	AT91_REG	 PIOA_ASR; 	// Select A Register
+	AT91_REG	 PIOA_BSR; 	// Select B Register
+	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved11[9]; 	// 
+	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved12[85]; 	// 
+	AT91_REG	 PIOB_PER; 	// PIO Enable Register
+	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOB_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved13[1]; 	// 
+	AT91_REG	 PIOB_OER; 	// Output Enable Register
+	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOB_OSR; 	// Output Status Register
+	AT91_REG	 Reserved14[1]; 	// 
+	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved15[1]; 	// 
+	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved16[1]; 	// 
+	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved17[1]; 	// 
+	AT91_REG	 PIOB_ASR; 	// Select A Register
+	AT91_REG	 PIOB_BSR; 	// Select B Register
+	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved18[9]; 	// 
+	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved19[341]; 	// 
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved20[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved21[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved22[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved23[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved24[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved25[36]; 	// 
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+	AT91_REG	 Reserved26[5]; 	// 
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+	AT91_REG	 Reserved27[5]; 	// 
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_SYS, *AT91PS_SYS;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
+#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
+	AT91_REG	 PDC_RCR; 	// Receive Counter Register
+	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
+	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved0[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved1[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+	AT91_REG	 PIO_PER; 	// PIO Enable Register
+	AT91_REG	 PIO_PDR; 	// PIO Disable Register
+	AT91_REG	 PIO_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PIO_OER; 	// Output Enable Register
+	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIO_OSR; 	// Output Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PIO_SODR; 	// Set Output Data Register
+	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved3[1]; 	// 
+	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved4[1]; 	// 
+	AT91_REG	 PIO_ASR; 	// Select A Register
+	AT91_REG	 PIO_BSR; 	// Select B Register
+	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved5[9]; 	// 
+	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
+	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 CKGR_PLLR; 	// PLL Register
+} AT91S_CKGR, *AT91PS_CKGR;
+
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
+#define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
+#define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
+#define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved3[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved4[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RSTC {
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
+
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define 	AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RTTC {
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PITC {
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_WDTC {
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_VREG {
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_VREG, *AT91PS_VREG;
+
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
+#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+	AT91_REG	 MC_RCR; 	// MC Remap Control Register
+	AT91_REG	 MC_ASR; 	// MC Abort Status Register
+	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
+	AT91_REG	 Reserved0[21]; 	// 
+	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
+	AT91_REG	 MC_FCR; 	// MC Flash Command Register
+	AT91_REG	 MC_FSR; 	// MC Flash Status Register
+} AT91S_MC, *AT91PS_MC;
+
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
+#define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
+#define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
+#define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
+#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
+#define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
+#define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
+#define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
+#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
+#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
+#define 	AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
+#define 	AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
+#define 	AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
+#define 	AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
+#define 	AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define 	AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define 	AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define 	AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
+#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+	AT91_REG	 SPI_CR; 	// Control Register
+	AT91_REG	 SPI_MR; 	// Mode Register
+	AT91_REG	 SPI_RDR; 	// Receive Data Register
+	AT91_REG	 SPI_TDR; 	// Transmit Data Register
+	AT91_REG	 SPI_SR; 	// Status Register
+	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
+	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
+	AT91_REG	 Reserved1[48]; 	// 
+	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
+	AT91_REG	 SPI_RCR; 	// Receive Counter Register
+	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
+	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+	AT91_REG	 US_CR; 	// Control Register
+	AT91_REG	 US_MR; 	// Mode Register
+	AT91_REG	 US_IER; 	// Interrupt Enable Register
+	AT91_REG	 US_IDR; 	// Interrupt Disable Register
+	AT91_REG	 US_IMR; 	// Interrupt Mask Register
+	AT91_REG	 US_CSR; 	// Channel Status Register
+	AT91_REG	 US_RHR; 	// Receiver Holding Register
+	AT91_REG	 US_THR; 	// Transmitter Holding Register
+	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
+	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
+	AT91_REG	 Reserved0[5]; 	// 
+	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
+	AT91_REG	 US_NER; 	// Nb Errors Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 US_IF; 	// IRDA_FILTER Register
+	AT91_REG	 Reserved2[44]; 	// 
+	AT91_REG	 US_RPR; 	// Receive Pointer Register
+	AT91_REG	 US_RCR; 	// Receive Counter Register
+	AT91_REG	 US_TPR; 	// Transmit Pointer Register
+	AT91_REG	 US_TCR; 	// Transmit Counter Register
+	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+	AT91_REG	 SSC_CR; 	// Control Register
+	AT91_REG	 SSC_CMR; 	// Clock Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
+	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
+	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
+	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
+	AT91_REG	 SSC_RHR; 	// Receive Holding Register
+	AT91_REG	 SSC_THR; 	// Transmit Holding Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
+	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 SSC_SR; 	// Status Register
+	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
+	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved3[44]; 	// 
+	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
+	AT91_REG	 SSC_RCR; 	// Receive Counter Register
+	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
+	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+	AT91_REG	 TWI_CR; 	// Control Register
+	AT91_REG	 TWI_MMR; 	// Master Mode Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 TWI_IADR; 	// Internal Address Register
+	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
+	AT91_REG	 Reserved1[3]; 	// 
+	AT91_REG	 TWI_SR; 	// Status Register
+	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
+	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TWI_RHR; 	// Receive Holding Register
+	AT91_REG	 TWI_THR; 	// Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
+
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC_CH {
+	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
+	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
+	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
+	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
+	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
+	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
+
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define 	AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH) 
+#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC {
+	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
+	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
+	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
+	AT91_REG	 PWMC_SR; 	// PWMC Status Register
+	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
+	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
+	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
+	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
+	AT91_REG	 Reserved0[55]; 	// 
+	AT91_REG	 PWMC_VR; 	// PWMC Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
+} AT91S_PWMC, *AT91PS_PWMC;
+
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
+#define 	AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC) 
+#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define 	AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC) 
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+	AT91_REG	 UDP_NUM; 	// Frame Number Register
+	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
+	AT91_REG	 UDP_FADDR; 	// Function Address Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
+	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
+	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
+	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
+	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
+	AT91_REG	 Reserved4[3]; 	// 
+	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
+
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_ESR         ((unsigned int) 0x1 <<  2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+#define AT91C_UDP_TXVDIS      ((unsigned int) 0x1 <<  8) // (UDP) 
+#define AT91C_UDP_PUON        ((unsigned int) 0x1 <<  9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+	AT91_REG	 TC_CCR; 	// Channel Control Register
+	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TC_CV; 	// Counter Value
+	AT91_REG	 TC_RA; 	// Register A
+	AT91_REG	 TC_RB; 	// Register B
+	AT91_REG	 TC_RC; 	// Register C
+	AT91_REG	 TC_SR; 	// Status Register
+	AT91_REG	 TC_IER; 	// Interrupt Enable Register
+	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_TIOB                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_XC0                  ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC1                  ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC2                  ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) 
+#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRGS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA       ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+	AT91S_TC	 TCB_TC0; 	// TC Channel 0
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91S_TC	 TCB_TC1; 	// TC Channel 1
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91S_TC	 TCB_TC2; 	// TC Channel 2
+	AT91_REG	 Reserved2[4]; 	// 
+	AT91_REG	 TCB_BCR; 	// TC Block Control Register
+	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x3 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x3 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x3 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA1                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN_MB {
+	AT91_REG	 CAN_MB_MMR; 	// MailBox Mode Register
+	AT91_REG	 CAN_MB_MAM; 	// MailBox Acceptance Mask Register
+	AT91_REG	 CAN_MB_MID; 	// MailBox ID Register
+	AT91_REG	 CAN_MB_MFID; 	// MailBox Family ID Register
+	AT91_REG	 CAN_MB_MSR; 	// MailBox Status Register
+	AT91_REG	 CAN_MB_MDL; 	// MailBox Data Low Register
+	AT91_REG	 CAN_MB_MDH; 	// MailBox Data High Register
+	AT91_REG	 CAN_MB_MCR; 	// MailBox Control Register
+} AT91S_CAN_MB, *AT91PS_CAN_MB;
+
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
+#define AT91C_CAN_MTIMEMARK   ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR       ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT         ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define 	AT91C_CAN_MOT_DIS                  ((unsigned int) 0x0 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RX                   ((unsigned int) 0x1 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RXOVERWRITE          ((unsigned int) 0x2 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_TX                   ((unsigned int) 0x3 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_CONSUMER             ((unsigned int) 0x4 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_PRODUCER             ((unsigned int) 0x5 << 24) // (CAN_MB) 
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
+#define AT91C_CAN_MIDvB       ((unsigned int) 0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA       ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE        ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
+#define AT91C_CAN_MTIMESTAMP  ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC        ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR        ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT        ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI         ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
+#define AT91C_CAN_MACR        ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN {
+	AT91_REG	 CAN_MR; 	// Mode Register
+	AT91_REG	 CAN_IER; 	// Interrupt Enable Register
+	AT91_REG	 CAN_IDR; 	// Interrupt Disable Register
+	AT91_REG	 CAN_IMR; 	// Interrupt Mask Register
+	AT91_REG	 CAN_SR; 	// Status Register
+	AT91_REG	 CAN_BR; 	// Baudrate Register
+	AT91_REG	 CAN_TIM; 	// Timer Register
+	AT91_REG	 CAN_TIMESTP; 	// Time Stamp Register
+	AT91_REG	 CAN_ECR; 	// Error Counter Register
+	AT91_REG	 CAN_TCR; 	// Transfer Command Register
+	AT91_REG	 CAN_ACR; 	// Abort Command Register
+	AT91_REG	 Reserved0[52]; 	// 
+	AT91_REG	 CAN_VR; 	// Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_CAN_MB	 CAN_MB0; 	// CAN Mailbox 0
+	AT91S_CAN_MB	 CAN_MB1; 	// CAN Mailbox 1
+	AT91S_CAN_MB	 CAN_MB2; 	// CAN Mailbox 2
+	AT91S_CAN_MB	 CAN_MB3; 	// CAN Mailbox 3
+	AT91S_CAN_MB	 CAN_MB4; 	// CAN Mailbox 4
+	AT91S_CAN_MB	 CAN_MB5; 	// CAN Mailbox 5
+	AT91S_CAN_MB	 CAN_MB6; 	// CAN Mailbox 6
+	AT91S_CAN_MB	 CAN_MB7; 	// CAN Mailbox 7
+	AT91S_CAN_MB	 CAN_MB8; 	// CAN Mailbox 8
+	AT91S_CAN_MB	 CAN_MB9; 	// CAN Mailbox 9
+	AT91S_CAN_MB	 CAN_MB10; 	// CAN Mailbox 10
+	AT91S_CAN_MB	 CAN_MB11; 	// CAN Mailbox 11
+	AT91S_CAN_MB	 CAN_MB12; 	// CAN Mailbox 12
+	AT91S_CAN_MB	 CAN_MB13; 	// CAN Mailbox 13
+	AT91S_CAN_MB	 CAN_MB14; 	// CAN Mailbox 14
+	AT91S_CAN_MB	 CAN_MB15; 	// CAN Mailbox 15
+} AT91S_CAN, *AT91PS_CAN;
+
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
+#define AT91C_CAN_CANEN       ((unsigned int) 0x1 <<  0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM         ((unsigned int) 0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM         ((unsigned int) 0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL         ((unsigned int) 0x1 <<  3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF        ((unsigned int) 0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM         ((unsigned int) 0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ      ((unsigned int) 0x1 <<  6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT        ((unsigned int) 0x1 <<  7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
+#define AT91C_CAN_MB0         ((unsigned int) 0x1 <<  0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1         ((unsigned int) 0x1 <<  1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2         ((unsigned int) 0x1 <<  2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3         ((unsigned int) 0x1 <<  3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4         ((unsigned int) 0x1 <<  4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5         ((unsigned int) 0x1 <<  5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6         ((unsigned int) 0x1 <<  6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7         ((unsigned int) 0x1 <<  7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8         ((unsigned int) 0x1 <<  8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9         ((unsigned int) 0x1 <<  9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10        ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11        ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12        ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13        ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14        ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15        ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA        ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN        ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP        ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF        ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP       ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP      ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF        ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP        ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR        ((unsigned int) 0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR        ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR        ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR        ((unsigned int) 0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR        ((unsigned int) 0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
+#define AT91C_CAN_RBSY        ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY        ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY        ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
+#define AT91C_CAN_PHASE2      ((unsigned int) 0x7 <<  0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1      ((unsigned int) 0x7 <<  4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG      ((unsigned int) 0x7 <<  8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC        ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP         ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP         ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
+#define AT91C_CAN_TIMER       ((unsigned int) 0xFFFF <<  0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
+#define AT91C_CAN_REC         ((unsigned int) 0xFF <<  0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC         ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
+#define AT91C_CAN_TIMRST      ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// *****************************************************************************
+typedef struct _AT91S_EMAC {
+	AT91_REG	 EMAC_NCR; 	// Network Control Register
+	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
+	AT91_REG	 EMAC_NSR; 	// Network Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
+	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
+	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
+	AT91_REG	 EMAC_RSR; 	// Receive Status Register
+	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
+	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
+	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
+	AT91_REG	 EMAC_PTR; 	// Pause Time Register
+	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
+	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
+	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
+	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
+	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
+	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
+	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
+	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
+	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
+	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
+	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
+	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
+	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
+	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
+	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
+	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
+	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
+	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
+	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
+	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
+	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
+	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
+	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
+	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
+	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
+	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
+	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
+	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
+	AT91_REG	 Reserved1[13]; 	// 
+	AT91_REG	 EMAC_REV; 	// Revision Register
+} AT91S_EMAC, *AT91PS_EMAC;
+
+// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local. 
+#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable. 
+#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable. 
+#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable. 
+#define AT91C_EMAC_CLRSTAT    ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers. 
+#define AT91C_EMAC_INCSTAT    ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers. 
+#define AT91C_EMAC_WESTAT     ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers. 
+#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure. 
+#define AT91C_EMAC_TSTART     ((unsigned int) 0x1 <<  9) // (EMAC) Start Transmission. 
+#define AT91C_EMAC_THALT      ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. 
+#define AT91C_EMAC_TPFR       ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame 
+#define AT91C_EMAC_TZQ        ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed. 
+#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex. 
+#define AT91C_EMAC_JFRAME     ((unsigned int) 0x1 <<  3) // (EMAC) Jumbo Frames. 
+#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames. 
+#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast. 
+#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable. 
+#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes. 
+#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable. 
+#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC) 
+#define 	AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
+#define 	AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
+#define 	AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
+#define 	AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PAE        ((unsigned int) 0x1 << 13) // (EMAC) 
+#define AT91C_EMAC_RBOF       ((unsigned int) 0x3 << 14) // (EMAC) 
+#define 	AT91C_EMAC_RBOF_OFFSET_0             ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_1             ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_2             ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_3             ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE       ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS      ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD      ((unsigned int) 0x1 << 18) // (EMAC) 
+#define AT91C_EMAC_IRXFCS     ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+#define AT91C_EMAC_LINKR      ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+#define AT91C_EMAC_UBR        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RLES       ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TGO        ((unsigned int) 0x1 <<  3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX        ((unsigned int) 0x1 <<  4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC) 
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+#define AT91C_EMAC_MFD        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_RCOMP      ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RXUBR      ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TXUBR      ((unsigned int) 0x1 <<  3) // (EMAC) 
+#define AT91C_EMAC_TUNDR      ((unsigned int) 0x1 <<  4) // (EMAC) 
+#define AT91C_EMAC_RLEX       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_TXERR      ((unsigned int) 0x1 <<  6) // (EMAC) 
+#define AT91C_EMAC_TCOMP      ((unsigned int) 0x1 <<  7) // (EMAC) 
+#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC) 
+#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC) 
+#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC) 
+#define AT91C_EMAC_PFRE       ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PTZ        ((unsigned int) 0x1 << 13) // (EMAC) 
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC) 
+#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC) 
+#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC) 
+#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC) 
+#define AT91C_EMAC_SOF        ((unsigned int) 0x3 << 30) // (EMAC) 
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+#define AT91C_EMAC_RMII       ((unsigned int) 0x1 <<  0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+#define AT91C_EMAC_IP         ((unsigned int) 0xFFFF <<  0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG        ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP        ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1        ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+#define AT91C_EMAC_REVREF     ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_PARTREF    ((unsigned int) 0xFFFF << 16) // (EMAC) 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// *****************************************************************************
+typedef struct _AT91S_ADC {
+	AT91_REG	 ADC_CR; 	// ADC Control Register
+	AT91_REG	 ADC_MR; 	// ADC Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
+	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
+	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
+	AT91_REG	 ADC_SR; 	// ADC Status Register
+	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
+	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
+	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
+	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
+	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
+	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
+	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
+	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
+	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
+	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
+	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
+	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
+	AT91_REG	 Reserved1[44]; 	// 
+	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
+	AT91_REG	 ADC_RCR; 	// Receive Counter Register
+	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
+	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
+
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
+#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
+#define 	AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define 	AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
+#define 	AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
+#define 	AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
+#define 	AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
+#define 	AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
+#define 	AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
+#define 	AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
+#define 	AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
+#define 	AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
+#define 	AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define 	AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
+#define 	AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
+// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
+#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
+#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
+#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
+#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
+#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
+#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
+#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
+// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_AES {
+	AT91_REG	 AES_CR; 	// Control Register
+	AT91_REG	 AES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AES_IER; 	// Interrupt Enable Register
+	AT91_REG	 AES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 AES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AES_ISR; 	// Interrupt Status Register
+	AT91_REG	 AES_KEYWxR[4]; 	// Key Word x Register
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91_REG	 AES_IDATAxR[4]; 	// Input Data x Register
+	AT91_REG	 AES_ODATAxR[4]; 	// Output Data x Register
+	AT91_REG	 AES_IVxR[4]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved2[35]; 	// 
+	AT91_REG	 AES_VR; 	// AES Version Register
+	AT91_REG	 AES_RPR; 	// Receive Pointer Register
+	AT91_REG	 AES_RCR; 	// Receive Counter Register
+	AT91_REG	 AES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 AES_TCR; 	// Transmit Counter Register
+	AT91_REG	 AES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 AES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 AES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 AES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 AES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 AES_PTSR; 	// PDC Transfer Status Register
+} AT91S_AES, *AT91PS_AES;
+
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
+#define AT91C_AES_START       ((unsigned int) 0x1 <<  0) // (AES) Starts Processing
+#define AT91C_AES_SWRST       ((unsigned int) 0x1 <<  8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED    ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
+#define AT91C_AES_CIPHER      ((unsigned int) 0x1 <<  0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY     ((unsigned int) 0xF <<  4) // (AES) Processing Delay
+#define AT91C_AES_SMOD        ((unsigned int) 0x3 <<  8) // (AES) Start Mode
+#define 	AT91C_AES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define 	AT91C_AES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define 	AT91C_AES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD       ((unsigned int) 0x7 << 12) // (AES) Operation Mode
+#define 	AT91C_AES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define 	AT91C_AES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define 	AT91C_AES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
+#define 	AT91C_AES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define 	AT91C_AES_OPMOD_CTR                  ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD         ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS        ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
+#define 	AT91C_AES_CFBS_128_BIT              ((unsigned int) 0x0 << 16) // (AES) 128-bit.
+#define 	AT91C_AES_CFBS_64_BIT               ((unsigned int) 0x1 << 16) // (AES) 64-bit.
+#define 	AT91C_AES_CFBS_32_BIT               ((unsigned int) 0x2 << 16) // (AES) 32-bit.
+#define 	AT91C_AES_CFBS_16_BIT               ((unsigned int) 0x3 << 16) // (AES) 16-bit.
+#define 	AT91C_AES_CFBS_8_BIT                ((unsigned int) 0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY        ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE       ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
+#define 	AT91C_AES_CTYPE_TYPE1_EN             ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE2_EN             ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE3_EN             ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE4_EN             ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE5_EN             ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_AES_DATRDY      ((unsigned int) 0x1 <<  0) // (AES) DATRDY
+#define AT91C_AES_ENDRX       ((unsigned int) 0x1 <<  1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX       ((unsigned int) 0x1 <<  2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF      ((unsigned int) 0x1 <<  3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE      ((unsigned int) 0x1 <<  4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD        ((unsigned int) 0x1 <<  8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_AES_URAT        ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define 	AT91C_AES_URAT_WO_REG_READ          ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_TDES {
+	AT91_REG	 TDES_CR; 	// Control Register
+	AT91_REG	 TDES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TDES_IER; 	// Interrupt Enable Register
+	AT91_REG	 TDES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TDES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TDES_ISR; 	// Interrupt Status Register
+	AT91_REG	 TDES_KEY1WxR[2]; 	// Key 1 Word x Register
+	AT91_REG	 TDES_KEY2WxR[2]; 	// Key 2 Word x Register
+	AT91_REG	 TDES_KEY3WxR[2]; 	// Key 3 Word x Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 TDES_IDATAxR[2]; 	// Input Data x Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 TDES_ODATAxR[2]; 	// Output Data x Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 TDES_IVxR[2]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved4[37]; 	// 
+	AT91_REG	 TDES_VR; 	// TDES Version Register
+	AT91_REG	 TDES_RPR; 	// Receive Pointer Register
+	AT91_REG	 TDES_RCR; 	// Receive Counter Register
+	AT91_REG	 TDES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 TDES_TCR; 	// Transmit Counter Register
+	AT91_REG	 TDES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 TDES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 TDES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 TDES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 TDES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 TDES_PTSR; 	// PDC Transfer Status Register
+} AT91S_TDES, *AT91PS_TDES;
+
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
+#define AT91C_TDES_START      ((unsigned int) 0x1 <<  0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST      ((unsigned int) 0x1 <<  8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
+#define AT91C_TDES_CIPHER     ((unsigned int) 0x1 <<  0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD    ((unsigned int) 0x1 <<  1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD     ((unsigned int) 0x1 <<  4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD       ((unsigned int) 0x3 <<  8) // (TDES) Start Mode
+#define 	AT91C_TDES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define 	AT91C_TDES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define 	AT91C_TDES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD      ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
+#define 	AT91C_TDES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define 	AT91C_TDES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define 	AT91C_TDES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define 	AT91C_TDES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD        ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS       ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define 	AT91C_TDES_CFBS_64_BIT               ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
+#define 	AT91C_TDES_CFBS_32_BIT               ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
+#define 	AT91C_TDES_CFBS_16_BIT               ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
+#define 	AT91C_TDES_CFBS_8_BIT                ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_TDES_DATRDY     ((unsigned int) 0x1 <<  0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX      ((unsigned int) 0x1 <<  1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX      ((unsigned int) 0x1 <<  2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF     ((unsigned int) 0x1 <<  3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE     ((unsigned int) 0x1 <<  4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD       ((unsigned int) 0x1 <<  8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_TDES_URAT       ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
+#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
+#define 	AT91C_TDES_URAT_WO_REG_READ          ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ========== 
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_IVR   ((AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR   ((AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR   ((AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR   ((AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR ((AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR   ((AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR  ((AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR  ((AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR   ((AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR   ((AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR   ((AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER  ((AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR  ((AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR  ((AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR  ((AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR  ((AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR  ((AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU   ((AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_TCR  ((AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR  ((AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR  ((AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR  ((AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR ((AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_EXID ((AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR  ((AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR  ((AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR ((AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR   ((AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR  ((AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR   ((AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR  ((AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR  ((AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER  ((AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_ODR  ((AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR ((AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR  ((AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER  ((AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR  ((AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER  ((AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR ((AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR  ((AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR  ((AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR  ((AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR  ((AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER  ((AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR  ((AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ========== 
+#define AT91C_PIOB_OWDR ((AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER ((AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR  ((AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR  ((AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR  ((AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER  ((AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR ((AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER ((AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR ((AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR ((AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR ((AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR  ((AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR ((AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR  ((AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR  ((AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR ((AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER ((AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR ((AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR  ((AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR ((AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR  ((AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR ((AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER ((AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR  ((AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR ((AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER  ((AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER  ((AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_MOR  ((AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR ((AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_IDR   ((AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER  ((AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR  ((AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR  ((AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR  ((AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR  ((AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR  ((AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR  ((AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_SCER  ((AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR   ((AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER   ((AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR    ((AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RCR  ((AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR  ((AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR  ((AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR ((AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR ((AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR ((AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR ((AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIVR ((AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR ((AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR ((AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR ((AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDCR ((AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR ((AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR ((AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ========== 
+#define AT91C_VREG_MR   ((AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ========== 
+#define AT91C_MC_ASR    ((AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR    ((AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR    ((AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR   ((AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR    ((AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR    ((AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ========== 
+#define AT91C_SPI1_PTCR ((AT91_REG *) 	0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR  ((AT91_REG *) 	0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR ((AT91_REG *) 	0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR  ((AT91_REG *) 	0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR ((AT91_REG *) 	0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR  ((AT91_REG *) 	0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR  ((AT91_REG *) 	0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR ((AT91_REG *) 	0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR ((AT91_REG *) 	0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR ((AT91_REG *) 	0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ========== 
+#define AT91C_SPI1_IMR  ((AT91_REG *) 	0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER  ((AT91_REG *) 	0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR   ((AT91_REG *) 	0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR  ((AT91_REG *) 	0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR  ((AT91_REG *) 	0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR   ((AT91_REG *) 	0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR  ((AT91_REG *) 	0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR   ((AT91_REG *) 	0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR  ((AT91_REG *) 	0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ========== 
+#define AT91C_SPI0_PTCR ((AT91_REG *) 	0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR  ((AT91_REG *) 	0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR  ((AT91_REG *) 	0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR  ((AT91_REG *) 	0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR ((AT91_REG *) 	0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR ((AT91_REG *) 	0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR  ((AT91_REG *) 	0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR ((AT91_REG *) 	0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR ((AT91_REG *) 	0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR ((AT91_REG *) 	0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ========== 
+#define AT91C_SPI0_IER  ((AT91_REG *) 	0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR   ((AT91_REG *) 	0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR  ((AT91_REG *) 	0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR   ((AT91_REG *) 	0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR   ((AT91_REG *) 	0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR  ((AT91_REG *) 	0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR  ((AT91_REG *) 	0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR  ((AT91_REG *) 	0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR  ((AT91_REG *) 	0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_RNCR  ((AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR  ((AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR  ((AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR  ((AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR  ((AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR  ((AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_IF    ((AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER   ((AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI  ((AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_TNPR  ((AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR  ((AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR  ((AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR  ((AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR  ((AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR  ((AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER   ((AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI  ((AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF    ((AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ========== 
+#define AT91C_SSC_TNCR  ((AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR   ((AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR  ((AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR   ((AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR  ((AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR   ((AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR   ((AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR  ((AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR  ((AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR  ((AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ========== 
+#define AT91C_SSC_RHR   ((AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR  ((AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR  ((AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR   ((AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR   ((AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR  ((AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER   ((AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR  ((AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR    ((AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR   ((AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR  ((AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR    ((AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR   ((AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR  ((AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ========== 
+#define AT91C_TWI_IER   ((AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR    ((AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR    ((AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR   ((AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR   ((AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR   ((AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR  ((AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR   ((AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR  ((AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR   ((AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ========== 
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ========== 
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ========== 
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ========== 
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ========== 
+#define AT91C_PWMC_IDR  ((AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS  ((AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER  ((AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR   ((AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR  ((AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR   ((AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR  ((AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR   ((AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA  ((AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ========== 
+#define AT91C_UDP_IMR   ((AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM   ((AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR   ((AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR   ((AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR   ((AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR   ((AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR   ((AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC  ((AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER   ((AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_RB    ((AT91_REG *) 	0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV    ((AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV    ((AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA    ((AT91_REG *) 	0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB    ((AT91_REG *) 	0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC    ((AT91_REG *) 	0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER   ((AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ========== 
+#define AT91C_TCB_BMR   ((AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR   ((AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ========== 
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 	0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 	0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 	0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 	0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 	0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 	0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 	0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 	0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ========== 
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 	0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 	0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 	0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 	0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 	0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 	0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 	0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 	0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ========== 
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 	0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 	0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 	0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 	0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 	0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 	0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 	0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 	0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ========== 
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 	0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 	0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 	0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 	0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 	0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 	0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 	0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 	0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ========== 
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 	0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 	0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 	0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 	0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 	0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 	0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 	0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 	0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ========== 
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 	0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 	0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 	0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 	0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 	0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 	0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 	0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 	0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ========== 
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 	0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 	0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 	0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 	0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 	0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 	0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 	0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 	0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ========== 
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 	0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 	0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 	0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 	0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 	0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 	0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 	0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 	0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ========== 
+#define AT91C_CAN_TCR   ((AT91_REG *) 	0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR   ((AT91_REG *) 	0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER   ((AT91_REG *) 	0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR   ((AT91_REG *) 	0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 	0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR    ((AT91_REG *) 	0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR   ((AT91_REG *) 	0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR   ((AT91_REG *) 	0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM   ((AT91_REG *) 	0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR    ((AT91_REG *) 	0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR    ((AT91_REG *) 	0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR    ((AT91_REG *) 	0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ========== 
+#define AT91C_EMAC_ISR  ((AT91_REG *) 	0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H ((AT91_REG *) 	0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L ((AT91_REG *) 	0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE  ((AT91_REG *) 	0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL ((AT91_REG *) 	0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE  ((AT91_REG *) 	0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL  ((AT91_REG *) 	0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF  ((AT91_REG *) 	0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND ((AT91_REG *) 	0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR  ((AT91_REG *) 	0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L ((AT91_REG *) 	0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR  ((AT91_REG *) 	0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L ((AT91_REG *) 	0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR  ((AT91_REG *) 	0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR  ((AT91_REG *) 	0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE  ((AT91_REG *) 	0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL ((AT91_REG *) 	0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID  ((AT91_REG *) 	0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB  ((AT91_REG *) 	0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP ((AT91_REG *) 	0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO ((AT91_REG *) 	0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR  ((AT91_REG *) 	0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H ((AT91_REG *) 	0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV  ((AT91_REG *) 	0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE  ((AT91_REG *) 	0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA  ((AT91_REG *) 	0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP ((AT91_REG *) 	0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF  ((AT91_REG *) 	0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 	0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT  ((AT91_REG *) 	0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF  ((AT91_REG *) 	0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE ((AT91_REG *) 	0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ  ((AT91_REG *) 	0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN  ((AT91_REG *) 	0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO  ((AT91_REG *) 	0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV  ((AT91_REG *) 	0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR  ((AT91_REG *) 	0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF  ((AT91_REG *) 	0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR  ((AT91_REG *) 	0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF  ((AT91_REG *) 	0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR  ((AT91_REG *) 	0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L ((AT91_REG *) 	0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO  ((AT91_REG *) 	0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER  ((AT91_REG *) 	0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H ((AT91_REG *) 	0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE  ((AT91_REG *) 	0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H ((AT91_REG *) 	0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE  ((AT91_REG *) 	0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE  ((AT91_REG *) 	0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ========== 
+#define AT91C_ADC_PTSR  ((AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR  ((AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR  ((AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR  ((AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR  ((AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR  ((AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR   ((AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR   ((AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR   ((AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR   ((AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ========== 
+#define AT91C_ADC_CDR2  ((AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3  ((AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0  ((AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5  ((AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR  ((AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR    ((AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4  ((AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1  ((AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR  ((AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR   ((AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR    ((AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7  ((AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6  ((AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER   ((AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER  ((AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR  ((AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR    ((AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR   ((AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ========== 
+#define AT91C_AES_TPR   ((AT91_REG *) 	0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR  ((AT91_REG *) 	0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR  ((AT91_REG *) 	0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR  ((AT91_REG *) 	0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR   ((AT91_REG *) 	0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR   ((AT91_REG *) 	0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR  ((AT91_REG *) 	0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR  ((AT91_REG *) 	0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR   ((AT91_REG *) 	0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR  ((AT91_REG *) 	0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ========== 
+#define AT91C_AES_IVxR  ((AT91_REG *) 	0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR    ((AT91_REG *) 	0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR    ((AT91_REG *) 	0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR ((AT91_REG *) 	0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR ((AT91_REG *) 	0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR    ((AT91_REG *) 	0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR   ((AT91_REG *) 	0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR   ((AT91_REG *) 	0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER   ((AT91_REG *) 	0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR ((AT91_REG *) 	0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR   ((AT91_REG *) 	0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ========== 
+#define AT91C_TDES_RNCR ((AT91_REG *) 	0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR  ((AT91_REG *) 	0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR  ((AT91_REG *) 	0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR ((AT91_REG *) 	0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR ((AT91_REG *) 	0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR  ((AT91_REG *) 	0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR ((AT91_REG *) 	0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR  ((AT91_REG *) 	0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR ((AT91_REG *) 	0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR ((AT91_REG *) 	0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ========== 
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 	0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 	0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR  ((AT91_REG *) 	0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR   ((AT91_REG *) 	0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR ((AT91_REG *) 	0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 	0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR  ((AT91_REG *) 	0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR   ((AT91_REG *) 	0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR   ((AT91_REG *) 	0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER  ((AT91_REG *) 	0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR  ((AT91_REG *) 	0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 	0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 	0xFFFA8020) // (TDES) Key 1 Word x Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0     ((unsigned int) AT91C_PIO_PA0) //  USART 0 Receive Data
+#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0     ((unsigned int) AT91C_PIO_PA1) //  USART 0 Transmit Data
+#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD      ((unsigned int) AT91C_PIO_PA10) //  TWI Two-wire Serial Data
+#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK     ((unsigned int) AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00   ((unsigned int) AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01   ((unsigned int) AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1     ((unsigned int) AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02   ((unsigned int) AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1     ((unsigned int) AT91C_PIO_PA14) //  External Interrupt 1
+#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03   ((unsigned int) AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0    ((unsigned int) AT91C_PIO_PA16) //  SPI 0 Master In Slave
+#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0    ((unsigned int) AT91C_PIO_PA17) //  SPI 0 Master Out Slave
+#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0    ((unsigned int) AT91C_PIO_PA18) //  SPI 0 Serial Clock
+#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX    ((unsigned int) AT91C_PIO_PA19) //  CAN Receive
+#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
+#define AT91C_PA2_NPCS11   ((unsigned int) AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX    ((unsigned int) AT91C_PIO_PA20) //  CAN Transmit
+#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF       ((unsigned int) AT91C_PIO_PA21) //  SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10   ((unsigned int) AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK       ((unsigned int) AT91C_PIO_PA22) //  SSC Transmit Clock
+#define AT91C_PA22_SPCK1    ((unsigned int) AT91C_PIO_PA22) //  SPI 1 Serial Clock
+#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD       ((unsigned int) AT91C_PIO_PA23) //  SSC Transmit data
+#define AT91C_PA23_MOSI1    ((unsigned int) AT91C_PIO_PA23) //  SPI 1 Master Out Slave
+#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD       ((unsigned int) AT91C_PIO_PA24) //  SSC Receive Data
+#define AT91C_PA24_MISO1    ((unsigned int) AT91C_PIO_PA24) //  SPI 1 Master In Slave
+#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK       ((unsigned int) AT91C_PIO_PA25) //  SSC Receive Clock
+#define AT91C_PA25_NPCS11   ((unsigned int) AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF       ((unsigned int) AT91C_PIO_PA26) //  SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12   ((unsigned int) AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD     ((unsigned int) AT91C_PIO_PA27) //  DBGU Debug Receive Data
+#define AT91C_PA27_PCK3     ((unsigned int) AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD     ((unsigned int) AT91C_PIO_PA28) //  DBGU Debug Transmit Data
+#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ      ((unsigned int) AT91C_PIO_PA29) //  AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13   ((unsigned int) AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0     ((unsigned int) AT91C_PIO_PA3) //  USART 0 Ready To Send
+#define AT91C_PA3_NPCS12   ((unsigned int) AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 0
+#define AT91C_PA30_PCK2     ((unsigned int) AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0     ((unsigned int) AT91C_PIO_PA4) //  USART 0 Clear To Send
+#define AT91C_PA4_NPCS13   ((unsigned int) AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1     ((unsigned int) AT91C_PIO_PA5) //  USART 1 Receive Data
+#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1     ((unsigned int) AT91C_PIO_PA6) //  USART 1 Transmit Data
+#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1     ((unsigned int) AT91C_PIO_PA7) //  USART 1 Serial Clock
+#define AT91C_PA7_NPCS01   ((unsigned int) AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1     ((unsigned int) AT91C_PIO_PA8) //  USART 1 Ready To Send
+#define AT91C_PA8_NPCS02   ((unsigned int) AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1     ((unsigned int) AT91C_PIO_PA9) //  USART 1 Clear To Send
+#define AT91C_PA9_NPCS03   ((unsigned int) AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0     ((unsigned int) AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN    ((unsigned int) AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2     ((unsigned int) AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11   ((unsigned int) AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3     ((unsigned int) AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12   ((unsigned int) AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER    ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0    ((unsigned int) AT91C_PIO_PB12) //  Timer Counter 0 external clock input
+#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01   ((unsigned int) AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3     ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02   ((unsigned int) AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV    ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13   ((unsigned int) AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03   ((unsigned int) AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100    ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG    ((unsigned int) AT91C_PIO_PB18) //  ADC External Trigger
+#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0     ((unsigned int) AT91C_PIO_PB19) //  PWM Channel 0
+#define AT91C_PB19_TCLK1    ((unsigned int) AT91C_PIO_PB19) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0     ((unsigned int) AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1     ((unsigned int) AT91C_PIO_PB20) //  PWM Channel 1
+#define AT91C_PB20_PCK0     ((unsigned int) AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2     ((unsigned int) AT91C_PIO_PB21) //  PWM Channel 2
+#define AT91C_PB21_PCK1     ((unsigned int) AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3     ((unsigned int) AT91C_PIO_PB22) //  PWM Channel 3
+#define AT91C_PB22_PCK2     ((unsigned int) AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0    ((unsigned int) AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0    ((unsigned int) AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Data Set ready
+#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1    ((unsigned int) AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Terminal ready
+#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1    ((unsigned int) AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1      ((unsigned int) AT91C_PIO_PB26) //  USART 1 Ring Indicator
+#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2    ((unsigned int) AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0     ((unsigned int) AT91C_PIO_PB27) //  PWM Channel 0
+#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2    ((unsigned int) AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1     ((unsigned int) AT91C_PIO_PB28) //  PWM Channel 1
+#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1     ((unsigned int) AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2     ((unsigned int) AT91C_PIO_PB29) //  PWM Channel 2
+#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1     ((unsigned int) AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30       ((unsigned int) 1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2     ((unsigned int) AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3     ((unsigned int) AT91C_PIO_PB30) //  PWM Channel 3
+#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0     ((unsigned int) AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1     ((unsigned int) AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER    ((unsigned int) AT91C_PIO_PB7) //  Ethernet MAC Receive Error
+#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC     ((unsigned int) AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO    ((unsigned int) AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
+#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A
+#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
+#define AT91C_ID_SPI0   ((unsigned int)  4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1   ((unsigned int)  5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
+#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
+#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
+#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
+#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
+#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
+#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
+#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
+#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
+#define AT91C_ID_CAN    ((unsigned int) 15) // Control Area Network Controller
+#define AT91C_ID_EMAC   ((unsigned int) 16) // Ethernet MAC
+#define AT91C_ID_ADC    ((unsigned int) 17) // Analog-to-Digital Converter
+#define AT91C_ID_AES    ((unsigned int) 18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES   ((unsigned int) 19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
+#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_BASE_SYS       ((AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU      ((AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB      ((AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR      ((AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC       ((AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC      ((AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC      ((AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC      ((AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC      ((AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG      ((AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC        ((AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1  ((AT91PS_PDC) 	0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1      ((AT91PS_SPI) 	0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0  ((AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0      ((AT91PS_SPI) 	0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC       ((AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI       ((AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC      ((AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP       ((AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB       ((AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0   ((AT91PS_CAN_MB) 	0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1   ((AT91PS_CAN_MB) 	0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2   ((AT91PS_CAN_MB) 	0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3   ((AT91PS_CAN_MB) 	0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4   ((AT91PS_CAN_MB) 	0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5   ((AT91PS_CAN_MB) 	0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6   ((AT91PS_CAN_MB) 	0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7   ((AT91PS_CAN_MB) 	0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN       ((AT91PS_CAN) 	0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC      ((AT91PS_EMAC) 	0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC       ((AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES   ((AT91PS_PDC) 	0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES       ((AT91PS_AES) 	0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES  ((AT91PS_PDC) 	0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES      ((AT91PS_TDES) 	0xFFFA8000) // (TDES) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ISRAM	 ((char *) 	0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE	 ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)
+#define AT91C_IFLASH	 ((char *) 	0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE	 ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)
+
+#define AT91F_AIC_ConfigureIt( irq_id, priority, src_type, newHandler )		\
+{																			\
+    unsigned int mask ;														\
+																			\
+    mask = 0x1 << irq_id;													\
+    /* Disable the interrupt on the interrupt controller */					\
+    AT91C_BASE_AIC->AIC_IDCR = mask ;										\
+    /* Save the interrupt handler routine pointer and the interrupt priority */	\
+    AT91C_BASE_AIC->AIC_SVR[irq_id] = (unsigned int) newHandler ;			\
+    /* Store the Source Mode Register */									\
+    AT91C_BASE_AIC->AIC_SMR[irq_id] = src_type | priority  ;				\
+    /* Clear the interrupt on the interrupt controller */					\
+    AT91C_BASE_AIC->AIC_ICCR = mask ;										\
+}
+
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h
new file mode 100644
index 0000000..8ea721e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h
@@ -0,0 +1,4698 @@
+// - ----------------------------------------------------------------------------
+// -          ATMEL Microcontroller Software Support  -  ROUSSET  -
+// - ----------------------------------------------------------------------------
+// -  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// -  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// -  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// -  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// -  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// -  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// -  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// -  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// -  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// -  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// - ----------------------------------------------------------------------------
+// - File Name           : AT91SAM7X256.h
+// - Object              : AT91SAM7X256 definitions
+// - Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
+// - 
+// - CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
+// - CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
+// - CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// - CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
+// - CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
+// - CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// - CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// - CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// - CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
+// - CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
+// - CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
+// - CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
+// - CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
+// - CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
+// - CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// - CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// - CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// - CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// - CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// - CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// - CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
+// - CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
+// - CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// - CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
+// - CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+// - ----------------------------------------------------------------------------
+
+#ifndef AT91SAM7X256_H
+#define AT91SAM7X256_H
+
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYS {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+	AT91_REG	 Reserved2[45]; 	// 
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved3[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved4[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+	AT91_REG	 Reserved5[54]; 	// 
+	AT91_REG	 PIOA_PER; 	// PIO Enable Register
+	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOA_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved6[1]; 	// 
+	AT91_REG	 PIOA_OER; 	// Output Enable Register
+	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOA_OSR; 	// Output Status Register
+	AT91_REG	 Reserved7[1]; 	// 
+	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved8[1]; 	// 
+	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved9[1]; 	// 
+	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved10[1]; 	// 
+	AT91_REG	 PIOA_ASR; 	// Select A Register
+	AT91_REG	 PIOA_BSR; 	// Select B Register
+	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved11[9]; 	// 
+	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved12[85]; 	// 
+	AT91_REG	 PIOB_PER; 	// PIO Enable Register
+	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOB_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved13[1]; 	// 
+	AT91_REG	 PIOB_OER; 	// Output Enable Register
+	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOB_OSR; 	// Output Status Register
+	AT91_REG	 Reserved14[1]; 	// 
+	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved15[1]; 	// 
+	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved16[1]; 	// 
+	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved17[1]; 	// 
+	AT91_REG	 PIOB_ASR; 	// Select A Register
+	AT91_REG	 PIOB_BSR; 	// Select B Register
+	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved18[9]; 	// 
+	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved19[341]; 	// 
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved20[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved21[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved22[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved23[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved24[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved25[36]; 	// 
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+	AT91_REG	 Reserved26[5]; 	// 
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+	AT91_REG	 Reserved27[5]; 	// 
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_SYS, *AT91PS_SYS;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
+#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
+	AT91_REG	 PDC_RCR; 	// Receive Counter Register
+	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
+	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved0[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved1[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+	AT91_REG	 PIO_PER; 	// PIO Enable Register
+	AT91_REG	 PIO_PDR; 	// PIO Disable Register
+	AT91_REG	 PIO_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PIO_OER; 	// Output Enable Register
+	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIO_OSR; 	// Output Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PIO_SODR; 	// Set Output Data Register
+	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved3[1]; 	// 
+	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved4[1]; 	// 
+	AT91_REG	 PIO_ASR; 	// Select A Register
+	AT91_REG	 PIO_BSR; 	// Select B Register
+	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved5[9]; 	// 
+	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
+	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 CKGR_PLLR; 	// PLL Register
+} AT91S_CKGR, *AT91PS_CKGR;
+
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
+#define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
+#define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
+#define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved3[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved4[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RSTC {
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
+
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define 	AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RTTC {
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PITC {
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_WDTC {
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_VREG {
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_VREG, *AT91PS_VREG;
+
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
+#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+	AT91_REG	 MC_RCR; 	// MC Remap Control Register
+	AT91_REG	 MC_ASR; 	// MC Abort Status Register
+	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
+	AT91_REG	 Reserved0[21]; 	// 
+	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
+	AT91_REG	 MC_FCR; 	// MC Flash Command Register
+	AT91_REG	 MC_FSR; 	// MC Flash Status Register
+} AT91S_MC, *AT91PS_MC;
+
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
+#define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
+#define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
+#define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
+#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
+#define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
+#define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
+#define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
+#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
+#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
+#define 	AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
+#define 	AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
+#define 	AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
+#define 	AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
+#define 	AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define 	AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define 	AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define 	AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
+#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+	AT91_REG	 SPI_CR; 	// Control Register
+	AT91_REG	 SPI_MR; 	// Mode Register
+	AT91_REG	 SPI_RDR; 	// Receive Data Register
+	AT91_REG	 SPI_TDR; 	// Transmit Data Register
+	AT91_REG	 SPI_SR; 	// Status Register
+	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
+	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
+	AT91_REG	 Reserved1[48]; 	// 
+	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
+	AT91_REG	 SPI_RCR; 	// Receive Counter Register
+	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
+	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+	AT91_REG	 US_CR; 	// Control Register
+	AT91_REG	 US_MR; 	// Mode Register
+	AT91_REG	 US_IER; 	// Interrupt Enable Register
+	AT91_REG	 US_IDR; 	// Interrupt Disable Register
+	AT91_REG	 US_IMR; 	// Interrupt Mask Register
+	AT91_REG	 US_CSR; 	// Channel Status Register
+	AT91_REG	 US_RHR; 	// Receiver Holding Register
+	AT91_REG	 US_THR; 	// Transmitter Holding Register
+	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
+	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
+	AT91_REG	 Reserved0[5]; 	// 
+	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
+	AT91_REG	 US_NER; 	// Nb Errors Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 US_IF; 	// IRDA_FILTER Register
+	AT91_REG	 Reserved2[44]; 	// 
+	AT91_REG	 US_RPR; 	// Receive Pointer Register
+	AT91_REG	 US_RCR; 	// Receive Counter Register
+	AT91_REG	 US_TPR; 	// Transmit Pointer Register
+	AT91_REG	 US_TCR; 	// Transmit Counter Register
+	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+	AT91_REG	 SSC_CR; 	// Control Register
+	AT91_REG	 SSC_CMR; 	// Clock Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
+	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
+	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
+	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
+	AT91_REG	 SSC_RHR; 	// Receive Holding Register
+	AT91_REG	 SSC_THR; 	// Transmit Holding Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
+	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 SSC_SR; 	// Status Register
+	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
+	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved3[44]; 	// 
+	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
+	AT91_REG	 SSC_RCR; 	// Receive Counter Register
+	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
+	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+	AT91_REG	 TWI_CR; 	// Control Register
+	AT91_REG	 TWI_MMR; 	// Master Mode Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 TWI_IADR; 	// Internal Address Register
+	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
+	AT91_REG	 Reserved1[3]; 	// 
+	AT91_REG	 TWI_SR; 	// Status Register
+	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
+	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TWI_RHR; 	// Receive Holding Register
+	AT91_REG	 TWI_THR; 	// Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
+
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC_CH {
+	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
+	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
+	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
+	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
+	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
+	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
+
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define 	AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH) 
+#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC {
+	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
+	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
+	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
+	AT91_REG	 PWMC_SR; 	// PWMC Status Register
+	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
+	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
+	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
+	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
+	AT91_REG	 Reserved0[55]; 	// 
+	AT91_REG	 PWMC_VR; 	// PWMC Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
+} AT91S_PWMC, *AT91PS_PWMC;
+
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
+#define 	AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC) 
+#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define 	AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC) 
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+	AT91_REG	 UDP_NUM; 	// Frame Number Register
+	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
+	AT91_REG	 UDP_FADDR; 	// Function Address Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
+	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
+	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
+	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
+	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
+	AT91_REG	 Reserved4[3]; 	// 
+	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
+
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_ESR         ((unsigned int) 0x1 <<  2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+#define AT91C_UDP_TXVDIS      ((unsigned int) 0x1 <<  8) // (UDP) 
+#define AT91C_UDP_PUON        ((unsigned int) 0x1 <<  9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+	AT91_REG	 TC_CCR; 	// Channel Control Register
+	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TC_CV; 	// Counter Value
+	AT91_REG	 TC_RA; 	// Register A
+	AT91_REG	 TC_RB; 	// Register B
+	AT91_REG	 TC_RC; 	// Register C
+	AT91_REG	 TC_SR; 	// Status Register
+	AT91_REG	 TC_IER; 	// Interrupt Enable Register
+	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_TIOB                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_XC0                  ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC1                  ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC2                  ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) 
+#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRGS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA       ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+	AT91S_TC	 TCB_TC0; 	// TC Channel 0
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91S_TC	 TCB_TC1; 	// TC Channel 1
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91S_TC	 TCB_TC2; 	// TC Channel 2
+	AT91_REG	 Reserved2[4]; 	// 
+	AT91_REG	 TCB_BCR; 	// TC Block Control Register
+	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x3 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x3 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x3 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA1                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN_MB {
+	AT91_REG	 CAN_MB_MMR; 	// MailBox Mode Register
+	AT91_REG	 CAN_MB_MAM; 	// MailBox Acceptance Mask Register
+	AT91_REG	 CAN_MB_MID; 	// MailBox ID Register
+	AT91_REG	 CAN_MB_MFID; 	// MailBox Family ID Register
+	AT91_REG	 CAN_MB_MSR; 	// MailBox Status Register
+	AT91_REG	 CAN_MB_MDL; 	// MailBox Data Low Register
+	AT91_REG	 CAN_MB_MDH; 	// MailBox Data High Register
+	AT91_REG	 CAN_MB_MCR; 	// MailBox Control Register
+} AT91S_CAN_MB, *AT91PS_CAN_MB;
+
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
+#define AT91C_CAN_MTIMEMARK   ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR       ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT         ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define 	AT91C_CAN_MOT_DIS                  ((unsigned int) 0x0 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RX                   ((unsigned int) 0x1 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RXOVERWRITE          ((unsigned int) 0x2 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_TX                   ((unsigned int) 0x3 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_CONSUMER             ((unsigned int) 0x4 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_PRODUCER             ((unsigned int) 0x5 << 24) // (CAN_MB) 
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
+#define AT91C_CAN_MIDvB       ((unsigned int) 0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA       ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE        ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
+#define AT91C_CAN_MTIMESTAMP  ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC        ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR        ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT        ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI         ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
+#define AT91C_CAN_MACR        ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN {
+	AT91_REG	 CAN_MR; 	// Mode Register
+	AT91_REG	 CAN_IER; 	// Interrupt Enable Register
+	AT91_REG	 CAN_IDR; 	// Interrupt Disable Register
+	AT91_REG	 CAN_IMR; 	// Interrupt Mask Register
+	AT91_REG	 CAN_SR; 	// Status Register
+	AT91_REG	 CAN_BR; 	// Baudrate Register
+	AT91_REG	 CAN_TIM; 	// Timer Register
+	AT91_REG	 CAN_TIMESTP; 	// Time Stamp Register
+	AT91_REG	 CAN_ECR; 	// Error Counter Register
+	AT91_REG	 CAN_TCR; 	// Transfer Command Register
+	AT91_REG	 CAN_ACR; 	// Abort Command Register
+	AT91_REG	 Reserved0[52]; 	// 
+	AT91_REG	 CAN_VR; 	// Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_CAN_MB	 CAN_MB0; 	// CAN Mailbox 0
+	AT91S_CAN_MB	 CAN_MB1; 	// CAN Mailbox 1
+	AT91S_CAN_MB	 CAN_MB2; 	// CAN Mailbox 2
+	AT91S_CAN_MB	 CAN_MB3; 	// CAN Mailbox 3
+	AT91S_CAN_MB	 CAN_MB4; 	// CAN Mailbox 4
+	AT91S_CAN_MB	 CAN_MB5; 	// CAN Mailbox 5
+	AT91S_CAN_MB	 CAN_MB6; 	// CAN Mailbox 6
+	AT91S_CAN_MB	 CAN_MB7; 	// CAN Mailbox 7
+	AT91S_CAN_MB	 CAN_MB8; 	// CAN Mailbox 8
+	AT91S_CAN_MB	 CAN_MB9; 	// CAN Mailbox 9
+	AT91S_CAN_MB	 CAN_MB10; 	// CAN Mailbox 10
+	AT91S_CAN_MB	 CAN_MB11; 	// CAN Mailbox 11
+	AT91S_CAN_MB	 CAN_MB12; 	// CAN Mailbox 12
+	AT91S_CAN_MB	 CAN_MB13; 	// CAN Mailbox 13
+	AT91S_CAN_MB	 CAN_MB14; 	// CAN Mailbox 14
+	AT91S_CAN_MB	 CAN_MB15; 	// CAN Mailbox 15
+} AT91S_CAN, *AT91PS_CAN;
+
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
+#define AT91C_CAN_CANEN       ((unsigned int) 0x1 <<  0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM         ((unsigned int) 0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM         ((unsigned int) 0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL         ((unsigned int) 0x1 <<  3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF        ((unsigned int) 0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM         ((unsigned int) 0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ      ((unsigned int) 0x1 <<  6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT        ((unsigned int) 0x1 <<  7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
+#define AT91C_CAN_MB0         ((unsigned int) 0x1 <<  0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1         ((unsigned int) 0x1 <<  1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2         ((unsigned int) 0x1 <<  2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3         ((unsigned int) 0x1 <<  3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4         ((unsigned int) 0x1 <<  4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5         ((unsigned int) 0x1 <<  5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6         ((unsigned int) 0x1 <<  6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7         ((unsigned int) 0x1 <<  7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8         ((unsigned int) 0x1 <<  8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9         ((unsigned int) 0x1 <<  9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10        ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11        ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12        ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13        ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14        ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15        ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA        ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN        ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP        ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF        ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP       ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP      ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF        ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP        ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR        ((unsigned int) 0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR        ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR        ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR        ((unsigned int) 0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR        ((unsigned int) 0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
+#define AT91C_CAN_RBSY        ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY        ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY        ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
+#define AT91C_CAN_PHASE2      ((unsigned int) 0x7 <<  0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1      ((unsigned int) 0x7 <<  4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG      ((unsigned int) 0x7 <<  8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC        ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP         ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP         ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
+#define AT91C_CAN_TIMER       ((unsigned int) 0xFFFF <<  0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
+#define AT91C_CAN_REC         ((unsigned int) 0xFF <<  0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC         ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
+#define AT91C_CAN_TIMRST      ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// *****************************************************************************
+typedef struct _AT91S_EMAC {
+	AT91_REG	 EMAC_NCR; 	// Network Control Register
+	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
+	AT91_REG	 EMAC_NSR; 	// Network Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
+	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
+	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
+	AT91_REG	 EMAC_RSR; 	// Receive Status Register
+	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
+	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
+	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
+	AT91_REG	 EMAC_PTR; 	// Pause Time Register
+	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
+	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
+	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
+	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
+	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
+	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
+	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
+	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
+	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
+	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
+	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
+	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
+	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
+	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
+	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
+	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
+	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
+	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
+	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
+	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
+	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
+	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
+	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
+	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
+	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
+	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
+	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
+	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
+	AT91_REG	 Reserved1[13]; 	// 
+	AT91_REG	 EMAC_REV; 	// Revision Register
+} AT91S_EMAC, *AT91PS_EMAC;
+
+// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local. 
+#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable. 
+#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable. 
+#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable. 
+#define AT91C_EMAC_CLRSTAT    ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers. 
+#define AT91C_EMAC_INCSTAT    ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers. 
+#define AT91C_EMAC_WESTAT     ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers. 
+#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure. 
+#define AT91C_EMAC_TSTART     ((unsigned int) 0x1 <<  9) // (EMAC) Start Transmission. 
+#define AT91C_EMAC_THALT      ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. 
+#define AT91C_EMAC_TPFR       ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame 
+#define AT91C_EMAC_TZQ        ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed. 
+#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex. 
+#define AT91C_EMAC_JFRAME     ((unsigned int) 0x1 <<  3) // (EMAC) Jumbo Frames. 
+#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames. 
+#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast. 
+#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable. 
+#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes. 
+#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable. 
+#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC) 
+#define 	AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
+#define 	AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
+#define 	AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
+#define 	AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PAE        ((unsigned int) 0x1 << 13) // (EMAC) 
+#define AT91C_EMAC_RBOF       ((unsigned int) 0x3 << 14) // (EMAC) 
+#define 	AT91C_EMAC_RBOF_OFFSET_0             ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_1             ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_2             ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_3             ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE       ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS      ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD      ((unsigned int) 0x1 << 18) // (EMAC) 
+#define AT91C_EMAC_IRXFCS     ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+#define AT91C_EMAC_LINKR      ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+#define AT91C_EMAC_UBR        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RLES       ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TGO        ((unsigned int) 0x1 <<  3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX        ((unsigned int) 0x1 <<  4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC) 
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+#define AT91C_EMAC_MFD        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_RCOMP      ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RXUBR      ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TXUBR      ((unsigned int) 0x1 <<  3) // (EMAC) 
+#define AT91C_EMAC_TUNDR      ((unsigned int) 0x1 <<  4) // (EMAC) 
+#define AT91C_EMAC_RLEX       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_TXERR      ((unsigned int) 0x1 <<  6) // (EMAC) 
+#define AT91C_EMAC_TCOMP      ((unsigned int) 0x1 <<  7) // (EMAC) 
+#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC) 
+#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC) 
+#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC) 
+#define AT91C_EMAC_PFRE       ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PTZ        ((unsigned int) 0x1 << 13) // (EMAC) 
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC) 
+#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC) 
+#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC) 
+#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC) 
+#define AT91C_EMAC_SOF        ((unsigned int) 0x3 << 30) // (EMAC) 
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+#define AT91C_EMAC_RMII       ((unsigned int) 0x1 <<  0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+#define AT91C_EMAC_IP         ((unsigned int) 0xFFFF <<  0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG        ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP        ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1        ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+#define AT91C_EMAC_REVREF     ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_PARTREF    ((unsigned int) 0xFFFF << 16) // (EMAC) 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// *****************************************************************************
+typedef struct _AT91S_ADC {
+	AT91_REG	 ADC_CR; 	// ADC Control Register
+	AT91_REG	 ADC_MR; 	// ADC Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
+	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
+	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
+	AT91_REG	 ADC_SR; 	// ADC Status Register
+	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
+	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
+	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
+	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
+	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
+	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
+	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
+	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
+	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
+	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
+	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
+	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
+	AT91_REG	 Reserved1[44]; 	// 
+	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
+	AT91_REG	 ADC_RCR; 	// Receive Counter Register
+	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
+	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
+
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
+#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
+#define 	AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define 	AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
+#define 	AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
+#define 	AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
+#define 	AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
+#define 	AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
+#define 	AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
+#define 	AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
+#define 	AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
+#define 	AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
+#define 	AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define 	AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
+#define 	AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
+// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
+#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
+#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
+#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
+#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
+#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
+#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
+#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
+// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_AES {
+	AT91_REG	 AES_CR; 	// Control Register
+	AT91_REG	 AES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AES_IER; 	// Interrupt Enable Register
+	AT91_REG	 AES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 AES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AES_ISR; 	// Interrupt Status Register
+	AT91_REG	 AES_KEYWxR[4]; 	// Key Word x Register
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91_REG	 AES_IDATAxR[4]; 	// Input Data x Register
+	AT91_REG	 AES_ODATAxR[4]; 	// Output Data x Register
+	AT91_REG	 AES_IVxR[4]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved2[35]; 	// 
+	AT91_REG	 AES_VR; 	// AES Version Register
+	AT91_REG	 AES_RPR; 	// Receive Pointer Register
+	AT91_REG	 AES_RCR; 	// Receive Counter Register
+	AT91_REG	 AES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 AES_TCR; 	// Transmit Counter Register
+	AT91_REG	 AES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 AES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 AES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 AES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 AES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 AES_PTSR; 	// PDC Transfer Status Register
+} AT91S_AES, *AT91PS_AES;
+
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
+#define AT91C_AES_START       ((unsigned int) 0x1 <<  0) // (AES) Starts Processing
+#define AT91C_AES_SWRST       ((unsigned int) 0x1 <<  8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED    ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
+#define AT91C_AES_CIPHER      ((unsigned int) 0x1 <<  0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY     ((unsigned int) 0xF <<  4) // (AES) Processing Delay
+#define AT91C_AES_SMOD        ((unsigned int) 0x3 <<  8) // (AES) Start Mode
+#define 	AT91C_AES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define 	AT91C_AES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define 	AT91C_AES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD       ((unsigned int) 0x7 << 12) // (AES) Operation Mode
+#define 	AT91C_AES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define 	AT91C_AES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define 	AT91C_AES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
+#define 	AT91C_AES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define 	AT91C_AES_OPMOD_CTR                  ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD         ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS        ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
+#define 	AT91C_AES_CFBS_128_BIT              ((unsigned int) 0x0 << 16) // (AES) 128-bit.
+#define 	AT91C_AES_CFBS_64_BIT               ((unsigned int) 0x1 << 16) // (AES) 64-bit.
+#define 	AT91C_AES_CFBS_32_BIT               ((unsigned int) 0x2 << 16) // (AES) 32-bit.
+#define 	AT91C_AES_CFBS_16_BIT               ((unsigned int) 0x3 << 16) // (AES) 16-bit.
+#define 	AT91C_AES_CFBS_8_BIT                ((unsigned int) 0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY        ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE       ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
+#define 	AT91C_AES_CTYPE_TYPE1_EN             ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE2_EN             ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE3_EN             ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE4_EN             ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE5_EN             ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_AES_DATRDY      ((unsigned int) 0x1 <<  0) // (AES) DATRDY
+#define AT91C_AES_ENDRX       ((unsigned int) 0x1 <<  1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX       ((unsigned int) 0x1 <<  2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF      ((unsigned int) 0x1 <<  3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE      ((unsigned int) 0x1 <<  4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD        ((unsigned int) 0x1 <<  8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_AES_URAT        ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define 	AT91C_AES_URAT_WO_REG_READ          ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_TDES {
+	AT91_REG	 TDES_CR; 	// Control Register
+	AT91_REG	 TDES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TDES_IER; 	// Interrupt Enable Register
+	AT91_REG	 TDES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TDES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TDES_ISR; 	// Interrupt Status Register
+	AT91_REG	 TDES_KEY1WxR[2]; 	// Key 1 Word x Register
+	AT91_REG	 TDES_KEY2WxR[2]; 	// Key 2 Word x Register
+	AT91_REG	 TDES_KEY3WxR[2]; 	// Key 3 Word x Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 TDES_IDATAxR[2]; 	// Input Data x Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 TDES_ODATAxR[2]; 	// Output Data x Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 TDES_IVxR[2]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved4[37]; 	// 
+	AT91_REG	 TDES_VR; 	// TDES Version Register
+	AT91_REG	 TDES_RPR; 	// Receive Pointer Register
+	AT91_REG	 TDES_RCR; 	// Receive Counter Register
+	AT91_REG	 TDES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 TDES_TCR; 	// Transmit Counter Register
+	AT91_REG	 TDES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 TDES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 TDES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 TDES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 TDES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 TDES_PTSR; 	// PDC Transfer Status Register
+} AT91S_TDES, *AT91PS_TDES;
+
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
+#define AT91C_TDES_START      ((unsigned int) 0x1 <<  0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST      ((unsigned int) 0x1 <<  8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
+#define AT91C_TDES_CIPHER     ((unsigned int) 0x1 <<  0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD    ((unsigned int) 0x1 <<  1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD     ((unsigned int) 0x1 <<  4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD       ((unsigned int) 0x3 <<  8) // (TDES) Start Mode
+#define 	AT91C_TDES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define 	AT91C_TDES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define 	AT91C_TDES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD      ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
+#define 	AT91C_TDES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define 	AT91C_TDES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define 	AT91C_TDES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define 	AT91C_TDES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD        ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS       ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define 	AT91C_TDES_CFBS_64_BIT               ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
+#define 	AT91C_TDES_CFBS_32_BIT               ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
+#define 	AT91C_TDES_CFBS_16_BIT               ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
+#define 	AT91C_TDES_CFBS_8_BIT                ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_TDES_DATRDY     ((unsigned int) 0x1 <<  0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX      ((unsigned int) 0x1 <<  1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX      ((unsigned int) 0x1 <<  2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF     ((unsigned int) 0x1 <<  3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE     ((unsigned int) 0x1 <<  4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD       ((unsigned int) 0x1 <<  8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_TDES_URAT       ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
+#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
+#define 	AT91C_TDES_URAT_WO_REG_READ          ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ========== 
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_IVR   ((AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR   ((AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR   ((AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR   ((AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR ((AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR   ((AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR  ((AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR  ((AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR   ((AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR   ((AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR   ((AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER  ((AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR  ((AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR  ((AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR  ((AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR  ((AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR  ((AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU   ((AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_TCR  ((AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR  ((AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR  ((AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR  ((AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR ((AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_EXID ((AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR  ((AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR  ((AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR ((AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR   ((AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR  ((AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR   ((AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR  ((AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR  ((AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER  ((AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_ODR  ((AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR ((AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR  ((AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER  ((AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR  ((AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER  ((AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR ((AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR  ((AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR  ((AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR  ((AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR  ((AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER  ((AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR  ((AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ========== 
+#define AT91C_PIOB_OWDR ((AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER ((AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR  ((AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR  ((AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR  ((AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER  ((AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR ((AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER ((AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR ((AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR ((AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR ((AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR  ((AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR ((AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR  ((AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR  ((AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR ((AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER ((AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR ((AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR  ((AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR ((AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR  ((AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR ((AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER ((AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR  ((AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR ((AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER  ((AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER  ((AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_MOR  ((AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR ((AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_IDR   ((AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER  ((AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR  ((AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR  ((AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR  ((AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR  ((AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR  ((AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR  ((AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_SCER  ((AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR   ((AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER   ((AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR    ((AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RCR  ((AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR  ((AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR  ((AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR ((AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR ((AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR ((AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR ((AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIVR ((AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR ((AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR ((AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR ((AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDCR ((AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR ((AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR ((AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ========== 
+#define AT91C_VREG_MR   ((AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ========== 
+#define AT91C_MC_ASR    ((AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR    ((AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR    ((AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR   ((AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR    ((AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR    ((AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ========== 
+#define AT91C_SPI1_PTCR ((AT91_REG *) 	0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR  ((AT91_REG *) 	0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR ((AT91_REG *) 	0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR  ((AT91_REG *) 	0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR ((AT91_REG *) 	0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR  ((AT91_REG *) 	0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR  ((AT91_REG *) 	0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR ((AT91_REG *) 	0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR ((AT91_REG *) 	0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR ((AT91_REG *) 	0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ========== 
+#define AT91C_SPI1_IMR  ((AT91_REG *) 	0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER  ((AT91_REG *) 	0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR   ((AT91_REG *) 	0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR  ((AT91_REG *) 	0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR  ((AT91_REG *) 	0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR   ((AT91_REG *) 	0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR  ((AT91_REG *) 	0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR   ((AT91_REG *) 	0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR  ((AT91_REG *) 	0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ========== 
+#define AT91C_SPI0_PTCR ((AT91_REG *) 	0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR  ((AT91_REG *) 	0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR  ((AT91_REG *) 	0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR  ((AT91_REG *) 	0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR ((AT91_REG *) 	0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR ((AT91_REG *) 	0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR  ((AT91_REG *) 	0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR ((AT91_REG *) 	0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR ((AT91_REG *) 	0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR ((AT91_REG *) 	0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ========== 
+#define AT91C_SPI0_IER  ((AT91_REG *) 	0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR   ((AT91_REG *) 	0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR  ((AT91_REG *) 	0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR   ((AT91_REG *) 	0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR   ((AT91_REG *) 	0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR  ((AT91_REG *) 	0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR  ((AT91_REG *) 	0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR  ((AT91_REG *) 	0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR  ((AT91_REG *) 	0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_RNCR  ((AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR  ((AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR  ((AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR  ((AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR  ((AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR  ((AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_IF    ((AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER   ((AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI  ((AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_TNPR  ((AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR  ((AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR  ((AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR  ((AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR  ((AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR  ((AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER   ((AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI  ((AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF    ((AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ========== 
+#define AT91C_SSC_TNCR  ((AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR   ((AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR  ((AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR   ((AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR  ((AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR   ((AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR   ((AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR  ((AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR  ((AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR  ((AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ========== 
+#define AT91C_SSC_RHR   ((AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR  ((AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR  ((AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR   ((AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR   ((AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR  ((AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER   ((AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR  ((AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR    ((AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR   ((AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR  ((AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR    ((AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR   ((AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR  ((AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ========== 
+#define AT91C_TWI_IER   ((AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR    ((AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR    ((AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR   ((AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR   ((AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR   ((AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR  ((AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR   ((AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR  ((AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR   ((AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ========== 
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ========== 
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ========== 
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ========== 
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ========== 
+#define AT91C_PWMC_IDR  ((AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS  ((AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER  ((AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR   ((AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR  ((AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR   ((AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR  ((AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR   ((AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA  ((AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ========== 
+#define AT91C_UDP_IMR   ((AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM   ((AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR   ((AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR   ((AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR   ((AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR   ((AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR   ((AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC  ((AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER   ((AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_RB    ((AT91_REG *) 	0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV    ((AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV    ((AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA    ((AT91_REG *) 	0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB    ((AT91_REG *) 	0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC    ((AT91_REG *) 	0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER   ((AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ========== 
+#define AT91C_TCB_BMR   ((AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR   ((AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ========== 
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 	0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 	0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 	0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 	0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 	0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 	0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 	0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 	0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ========== 
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 	0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 	0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 	0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 	0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 	0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 	0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 	0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 	0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ========== 
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 	0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 	0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 	0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 	0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 	0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 	0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 	0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 	0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ========== 
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 	0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 	0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 	0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 	0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 	0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 	0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 	0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 	0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ========== 
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 	0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 	0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 	0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 	0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 	0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 	0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 	0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 	0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ========== 
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 	0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 	0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 	0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 	0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 	0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 	0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 	0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 	0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ========== 
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 	0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 	0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 	0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 	0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 	0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 	0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 	0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 	0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ========== 
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 	0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 	0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 	0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 	0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 	0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 	0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 	0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 	0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ========== 
+#define AT91C_CAN_TCR   ((AT91_REG *) 	0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR   ((AT91_REG *) 	0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER   ((AT91_REG *) 	0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR   ((AT91_REG *) 	0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 	0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR    ((AT91_REG *) 	0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR   ((AT91_REG *) 	0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR   ((AT91_REG *) 	0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM   ((AT91_REG *) 	0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR    ((AT91_REG *) 	0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR    ((AT91_REG *) 	0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR    ((AT91_REG *) 	0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ========== 
+#define AT91C_EMAC_ISR  ((AT91_REG *) 	0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H ((AT91_REG *) 	0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L ((AT91_REG *) 	0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE  ((AT91_REG *) 	0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL ((AT91_REG *) 	0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE  ((AT91_REG *) 	0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL  ((AT91_REG *) 	0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF  ((AT91_REG *) 	0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND ((AT91_REG *) 	0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR  ((AT91_REG *) 	0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L ((AT91_REG *) 	0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR  ((AT91_REG *) 	0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L ((AT91_REG *) 	0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR  ((AT91_REG *) 	0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR  ((AT91_REG *) 	0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE  ((AT91_REG *) 	0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL ((AT91_REG *) 	0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID  ((AT91_REG *) 	0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB  ((AT91_REG *) 	0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP ((AT91_REG *) 	0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO ((AT91_REG *) 	0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR  ((AT91_REG *) 	0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H ((AT91_REG *) 	0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV  ((AT91_REG *) 	0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE  ((AT91_REG *) 	0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA  ((AT91_REG *) 	0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP ((AT91_REG *) 	0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF  ((AT91_REG *) 	0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 	0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT  ((AT91_REG *) 	0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF  ((AT91_REG *) 	0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE ((AT91_REG *) 	0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ  ((AT91_REG *) 	0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN  ((AT91_REG *) 	0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO  ((AT91_REG *) 	0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV  ((AT91_REG *) 	0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR  ((AT91_REG *) 	0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF  ((AT91_REG *) 	0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR  ((AT91_REG *) 	0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF  ((AT91_REG *) 	0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR  ((AT91_REG *) 	0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L ((AT91_REG *) 	0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO  ((AT91_REG *) 	0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER  ((AT91_REG *) 	0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H ((AT91_REG *) 	0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE  ((AT91_REG *) 	0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H ((AT91_REG *) 	0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE  ((AT91_REG *) 	0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE  ((AT91_REG *) 	0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ========== 
+#define AT91C_ADC_PTSR  ((AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR  ((AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR  ((AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR  ((AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR  ((AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR  ((AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR   ((AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR   ((AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR   ((AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR   ((AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ========== 
+#define AT91C_ADC_CDR2  ((AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3  ((AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0  ((AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5  ((AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR  ((AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR    ((AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4  ((AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1  ((AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR  ((AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR   ((AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR    ((AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7  ((AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6  ((AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER   ((AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER  ((AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR  ((AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR    ((AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR   ((AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ========== 
+#define AT91C_AES_TPR   ((AT91_REG *) 	0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR  ((AT91_REG *) 	0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR  ((AT91_REG *) 	0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR  ((AT91_REG *) 	0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR   ((AT91_REG *) 	0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR   ((AT91_REG *) 	0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR  ((AT91_REG *) 	0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR  ((AT91_REG *) 	0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR   ((AT91_REG *) 	0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR  ((AT91_REG *) 	0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ========== 
+#define AT91C_AES_IVxR  ((AT91_REG *) 	0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR    ((AT91_REG *) 	0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR    ((AT91_REG *) 	0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR ((AT91_REG *) 	0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR ((AT91_REG *) 	0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR    ((AT91_REG *) 	0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR   ((AT91_REG *) 	0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR   ((AT91_REG *) 	0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER   ((AT91_REG *) 	0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR ((AT91_REG *) 	0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR   ((AT91_REG *) 	0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ========== 
+#define AT91C_TDES_RNCR ((AT91_REG *) 	0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR  ((AT91_REG *) 	0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR  ((AT91_REG *) 	0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR ((AT91_REG *) 	0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR ((AT91_REG *) 	0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR  ((AT91_REG *) 	0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR ((AT91_REG *) 	0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR  ((AT91_REG *) 	0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR ((AT91_REG *) 	0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR ((AT91_REG *) 	0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ========== 
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 	0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 	0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR  ((AT91_REG *) 	0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR   ((AT91_REG *) 	0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR ((AT91_REG *) 	0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 	0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR  ((AT91_REG *) 	0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR   ((AT91_REG *) 	0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR   ((AT91_REG *) 	0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER  ((AT91_REG *) 	0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR  ((AT91_REG *) 	0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 	0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 	0xFFFA8020) // (TDES) Key 1 Word x Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0     ((unsigned int) AT91C_PIO_PA0) //  USART 0 Receive Data
+#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0     ((unsigned int) AT91C_PIO_PA1) //  USART 0 Transmit Data
+#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD      ((unsigned int) AT91C_PIO_PA10) //  TWI Two-wire Serial Data
+#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK     ((unsigned int) AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00   ((unsigned int) AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01   ((unsigned int) AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1     ((unsigned int) AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02   ((unsigned int) AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1     ((unsigned int) AT91C_PIO_PA14) //  External Interrupt 1
+#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03   ((unsigned int) AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0    ((unsigned int) AT91C_PIO_PA16) //  SPI 0 Master In Slave
+#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0    ((unsigned int) AT91C_PIO_PA17) //  SPI 0 Master Out Slave
+#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0    ((unsigned int) AT91C_PIO_PA18) //  SPI 0 Serial Clock
+#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX    ((unsigned int) AT91C_PIO_PA19) //  CAN Receive
+#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
+#define AT91C_PA2_NPCS11   ((unsigned int) AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX    ((unsigned int) AT91C_PIO_PA20) //  CAN Transmit
+#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF       ((unsigned int) AT91C_PIO_PA21) //  SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10   ((unsigned int) AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK       ((unsigned int) AT91C_PIO_PA22) //  SSC Transmit Clock
+#define AT91C_PA22_SPCK1    ((unsigned int) AT91C_PIO_PA22) //  SPI 1 Serial Clock
+#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD       ((unsigned int) AT91C_PIO_PA23) //  SSC Transmit data
+#define AT91C_PA23_MOSI1    ((unsigned int) AT91C_PIO_PA23) //  SPI 1 Master Out Slave
+#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD       ((unsigned int) AT91C_PIO_PA24) //  SSC Receive Data
+#define AT91C_PA24_MISO1    ((unsigned int) AT91C_PIO_PA24) //  SPI 1 Master In Slave
+#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK       ((unsigned int) AT91C_PIO_PA25) //  SSC Receive Clock
+#define AT91C_PA25_NPCS11   ((unsigned int) AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF       ((unsigned int) AT91C_PIO_PA26) //  SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12   ((unsigned int) AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD     ((unsigned int) AT91C_PIO_PA27) //  DBGU Debug Receive Data
+#define AT91C_PA27_PCK3     ((unsigned int) AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD     ((unsigned int) AT91C_PIO_PA28) //  DBGU Debug Transmit Data
+#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ      ((unsigned int) AT91C_PIO_PA29) //  AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13   ((unsigned int) AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0     ((unsigned int) AT91C_PIO_PA3) //  USART 0 Ready To Send
+#define AT91C_PA3_NPCS12   ((unsigned int) AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 0
+#define AT91C_PA30_PCK2     ((unsigned int) AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0     ((unsigned int) AT91C_PIO_PA4) //  USART 0 Clear To Send
+#define AT91C_PA4_NPCS13   ((unsigned int) AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1     ((unsigned int) AT91C_PIO_PA5) //  USART 1 Receive Data
+#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1     ((unsigned int) AT91C_PIO_PA6) //  USART 1 Transmit Data
+#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1     ((unsigned int) AT91C_PIO_PA7) //  USART 1 Serial Clock
+#define AT91C_PA7_NPCS01   ((unsigned int) AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1     ((unsigned int) AT91C_PIO_PA8) //  USART 1 Ready To Send
+#define AT91C_PA8_NPCS02   ((unsigned int) AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1     ((unsigned int) AT91C_PIO_PA9) //  USART 1 Clear To Send
+#define AT91C_PA9_NPCS03   ((unsigned int) AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0     ((unsigned int) AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN    ((unsigned int) AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2     ((unsigned int) AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11   ((unsigned int) AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3     ((unsigned int) AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12   ((unsigned int) AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER    ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0    ((unsigned int) AT91C_PIO_PB12) //  Timer Counter 0 external clock input
+#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01   ((unsigned int) AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3     ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02   ((unsigned int) AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV    ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13   ((unsigned int) AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03   ((unsigned int) AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100    ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG    ((unsigned int) AT91C_PIO_PB18) //  ADC External Trigger
+#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0     ((unsigned int) AT91C_PIO_PB19) //  PWM Channel 0
+#define AT91C_PB19_TCLK1    ((unsigned int) AT91C_PIO_PB19) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0     ((unsigned int) AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1     ((unsigned int) AT91C_PIO_PB20) //  PWM Channel 1
+#define AT91C_PB20_PCK0     ((unsigned int) AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2     ((unsigned int) AT91C_PIO_PB21) //  PWM Channel 2
+#define AT91C_PB21_PCK1     ((unsigned int) AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3     ((unsigned int) AT91C_PIO_PB22) //  PWM Channel 3
+#define AT91C_PB22_PCK2     ((unsigned int) AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0    ((unsigned int) AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0    ((unsigned int) AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Data Set ready
+#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1    ((unsigned int) AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Terminal ready
+#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1    ((unsigned int) AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1      ((unsigned int) AT91C_PIO_PB26) //  USART 1 Ring Indicator
+#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2    ((unsigned int) AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0     ((unsigned int) AT91C_PIO_PB27) //  PWM Channel 0
+#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2    ((unsigned int) AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1     ((unsigned int) AT91C_PIO_PB28) //  PWM Channel 1
+#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1     ((unsigned int) AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2     ((unsigned int) AT91C_PIO_PB29) //  PWM Channel 2
+#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1     ((unsigned int) AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30       ((unsigned int) 1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2     ((unsigned int) AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3     ((unsigned int) AT91C_PIO_PB30) //  PWM Channel 3
+#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0     ((unsigned int) AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1     ((unsigned int) AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER    ((unsigned int) AT91C_PIO_PB7) //  Ethernet MAC Receive Error
+#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC     ((unsigned int) AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO    ((unsigned int) AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
+#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A
+#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
+#define AT91C_ID_SPI0   ((unsigned int)  4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1   ((unsigned int)  5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
+#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
+#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
+#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
+#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
+#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
+#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
+#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
+#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
+#define AT91C_ID_CAN    ((unsigned int) 15) // Control Area Network Controller
+#define AT91C_ID_EMAC   ((unsigned int) 16) // Ethernet MAC
+#define AT91C_ID_ADC    ((unsigned int) 17) // Analog-to-Digital Converter
+#define AT91C_ID_AES    ((unsigned int) 18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES   ((unsigned int) 19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
+#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_BASE_SYS       ((AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU      ((AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB      ((AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR      ((AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC       ((AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC      ((AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC      ((AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC      ((AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC      ((AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG      ((AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC        ((AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1  ((AT91PS_PDC) 	0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1      ((AT91PS_SPI) 	0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0  ((AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0      ((AT91PS_SPI) 	0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC       ((AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI       ((AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC      ((AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP       ((AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB       ((AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0   ((AT91PS_CAN_MB) 	0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1   ((AT91PS_CAN_MB) 	0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2   ((AT91PS_CAN_MB) 	0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3   ((AT91PS_CAN_MB) 	0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4   ((AT91PS_CAN_MB) 	0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5   ((AT91PS_CAN_MB) 	0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6   ((AT91PS_CAN_MB) 	0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7   ((AT91PS_CAN_MB) 	0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN       ((AT91PS_CAN) 	0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC      ((AT91PS_EMAC) 	0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC       ((AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES   ((AT91PS_PDC) 	0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES       ((AT91PS_AES) 	0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES  ((AT91PS_PDC) 	0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES      ((AT91PS_TDES) 	0xFFFA8000) // (TDES) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ISRAM	 ((char *) 	0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE	 ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)
+#define AT91C_IFLASH	 ((char *) 	0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE	 ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)
+
+
+
+// - Hardware register definition
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR System Peripherals
+// - *****************************************************************************
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// - *****************************************************************************
+// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#if 0 /*_RB_*/
+AT91C_AIC_PRIOR           EQU (0x7 <<  0) ;- (AIC) Priority Level
+AT91C_AIC_PRIOR_LOWEST    EQU (0x0) ;- (AIC) Lowest priority level
+AT91C_AIC_PRIOR_HIGHEST   EQU (0x7) ;- (AIC) Highest priority level
+AT91C_AIC_SRCTYPE         EQU (0x3 <<  5) ;- (AIC) Interrupt Source Type
+AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 <<  5) ;- (AIC) Internal Sources Code Label High-level Sensitive
+AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 <<  5) ;- (AIC) External Sources Code Label Low-level Sensitive
+AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 <<  5) ;- (AIC) Internal Sources Code Label Positive Edge triggered
+AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 <<  5) ;- (AIC) External Sources Code Label Negative Edge triggered
+AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 <<  5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive
+AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 <<  5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+AT91C_AIC_NFIQ            EQU (0x1 <<  0) ;- (AIC) NFIQ Status
+AT91C_AIC_NIRQ            EQU (0x1 <<  1) ;- (AIC) NIRQ Status
+// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+AT91C_AIC_DCR_PROT        EQU (0x1 <<  0) ;- (AIC) Protection Mode
+AT91C_AIC_DCR_GMSK        EQU (0x1 <<  1) ;- (AIC) General Mask
+#endif
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// - *****************************************************************************
+// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+AT91C_PDC_RXTEN           EQU (0x1 <<  0) ;- (PDC) Receiver Transfer Enable
+AT91C_PDC_RXTDIS          EQU (0x1 <<  1) ;- (PDC) Receiver Transfer Disable
+AT91C_PDC_TXTEN           EQU (0x1 <<  8) ;- (PDC) Transmitter Transfer Enable
+AT91C_PDC_TXTDIS          EQU (0x1 <<  9) ;- (PDC) Transmitter Transfer Disable
+// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Debug Unit
+// - *****************************************************************************
+// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+AT91C_US_RSTRX            EQU (0x1 <<  2) ;- (DBGU) Reset Receiver
+AT91C_US_RSTTX            EQU (0x1 <<  3) ;- (DBGU) Reset Transmitter
+AT91C_US_RXEN             EQU (0x1 <<  4) ;- (DBGU) Receiver Enable
+AT91C_US_RXDIS            EQU (0x1 <<  5) ;- (DBGU) Receiver Disable
+AT91C_US_TXEN             EQU (0x1 <<  6) ;- (DBGU) Transmitter Enable
+AT91C_US_TXDIS            EQU (0x1 <<  7) ;- (DBGU) Transmitter Disable
+AT91C_US_RSTSTA           EQU (0x1 <<  8) ;- (DBGU) Reset Status Bits
+// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+AT91C_US_PAR              EQU (0x7 <<  9) ;- (DBGU) Parity type
+AT91C_US_PAR_EVEN         EQU (0x0 <<  9) ;- (DBGU) Even Parity
+AT91C_US_PAR_ODD          EQU (0x1 <<  9) ;- (DBGU) Odd Parity
+AT91C_US_PAR_SPACE        EQU (0x2 <<  9) ;- (DBGU) Parity forced to 0 (Space)
+AT91C_US_PAR_MARK         EQU (0x3 <<  9) ;- (DBGU) Parity forced to 1 (Mark)
+AT91C_US_PAR_NONE         EQU (0x4 <<  9) ;- (DBGU) No Parity
+AT91C_US_PAR_MULTI_DROP   EQU (0x6 <<  9) ;- (DBGU) Multi-drop mode
+AT91C_US_CHMODE           EQU (0x3 << 14) ;- (DBGU) Channel Mode
+AT91C_US_CHMODE_NORMAL    EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+AT91C_US_CHMODE_AUTO      EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+AT91C_US_CHMODE_LOCAL     EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+AT91C_US_CHMODE_REMOTE    EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+AT91C_US_RXRDY            EQU (0x1 <<  0) ;- (DBGU) RXRDY Interrupt
+AT91C_US_TXRDY            EQU (0x1 <<  1) ;- (DBGU) TXRDY Interrupt
+AT91C_US_ENDRX            EQU (0x1 <<  3) ;- (DBGU) End of Receive Transfer Interrupt
+AT91C_US_ENDTX            EQU (0x1 <<  4) ;- (DBGU) End of Transmit Interrupt
+AT91C_US_OVRE             EQU (0x1 <<  5) ;- (DBGU) Overrun Interrupt
+AT91C_US_FRAME            EQU (0x1 <<  6) ;- (DBGU) Framing Error Interrupt
+AT91C_US_PARE             EQU (0x1 <<  7) ;- (DBGU) Parity Error Interrupt
+AT91C_US_TXEMPTY          EQU (0x1 <<  9) ;- (DBGU) TXEMPTY Interrupt
+AT91C_US_TXBUFE           EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt
+AT91C_US_RXBUFF           EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt
+AT91C_US_COMM_TX          EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt
+AT91C_US_COMM_RX          EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt
+// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+AT91C_US_FORCE_NTRST      EQU (0x1 <<  0) ;- (DBGU) Force NTRST in JTAG
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// - *****************************************************************************
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// - *****************************************************************************
+// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+AT91C_CKGR_MOSCEN         EQU (0x1 <<  0) ;- (CKGR) Main Oscillator Enable
+AT91C_CKGR_OSCBYPASS      EQU (0x1 <<  1) ;- (CKGR) Main Oscillator Bypass
+AT91C_CKGR_OSCOUNT        EQU (0xFF <<  8) ;- (CKGR) Main Oscillator Start-up Time
+// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+AT91C_CKGR_MAINF          EQU (0xFFFF <<  0) ;- (CKGR) Main Clock Frequency
+AT91C_CKGR_MAINRDY        EQU (0x1 << 16) ;- (CKGR) Main Clock Ready
+// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+AT91C_CKGR_DIV            EQU (0xFF <<  0) ;- (CKGR) Divider Selected
+AT91C_CKGR_DIV_0          EQU (0x0) ;- (CKGR) Divider output is 0
+AT91C_CKGR_DIV_BYPASS     EQU (0x1) ;- (CKGR) Divider is bypassed
+AT91C_CKGR_PLLCOUNT       EQU (0x3F <<  8) ;- (CKGR) PLL Counter
+AT91C_CKGR_OUT            EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range
+AT91C_CKGR_OUT_0          EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_1          EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_2          EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_3          EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_MUL            EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier
+AT91C_CKGR_USBDIV         EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks
+AT91C_CKGR_USBDIV_0       EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output
+AT91C_CKGR_USBDIV_1       EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2
+AT91C_CKGR_USBDIV_2       EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Power Management Controler
+// - *****************************************************************************
+// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+AT91C_PMC_PCK             EQU (0x1 <<  0) ;- (PMC) Processor Clock
+AT91C_PMC_UDP             EQU (0x1 <<  7) ;- (PMC) USB Device Port Clock
+AT91C_PMC_PCK0            EQU (0x1 <<  8) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK1            EQU (0x1 <<  9) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK2            EQU (0x1 << 10) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK3            EQU (0x1 << 11) ;- (PMC) Programmable Clock Output
+// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+AT91C_PMC_CSS             EQU (0x3 <<  0) ;- (PMC) Programmable Clock Selection
+AT91C_PMC_CSS_SLOW_CLK    EQU (0x0) ;- (PMC) Slow Clock is selected
+AT91C_PMC_CSS_MAIN_CLK    EQU (0x1) ;- (PMC) Main Clock is selected
+AT91C_PMC_CSS_PLL_CLK     EQU (0x3) ;- (PMC) Clock from PLL is selected
+AT91C_PMC_PRES            EQU (0x7 <<  2) ;- (PMC) Programmable Clock Prescaler
+AT91C_PMC_PRES_CLK        EQU (0x0 <<  2) ;- (PMC) Selected clock
+AT91C_PMC_PRES_CLK_2      EQU (0x1 <<  2) ;- (PMC) Selected clock divided by 2
+AT91C_PMC_PRES_CLK_4      EQU (0x2 <<  2) ;- (PMC) Selected clock divided by 4
+AT91C_PMC_PRES_CLK_8      EQU (0x3 <<  2) ;- (PMC) Selected clock divided by 8
+AT91C_PMC_PRES_CLK_16     EQU (0x4 <<  2) ;- (PMC) Selected clock divided by 16
+AT91C_PMC_PRES_CLK_32     EQU (0x5 <<  2) ;- (PMC) Selected clock divided by 32
+AT91C_PMC_PRES_CLK_64     EQU (0x6 <<  2) ;- (PMC) Selected clock divided by 64
+// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+AT91C_PMC_MOSCS           EQU (0x1 <<  0) ;- (PMC) MOSC Status/Enable/Disable/Mask
+AT91C_PMC_LOCK            EQU (0x1 <<  2) ;- (PMC) PLL Status/Enable/Disable/Mask
+AT91C_PMC_MCKRDY          EQU (0x1 <<  3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK0RDY         EQU (0x1 <<  8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK1RDY         EQU (0x1 <<  9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK2RDY         EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK3RDY         EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// - *****************************************************************************
+// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+AT91C_RSTC_PROCRST        EQU (0x1 <<  0) ;- (RSTC) Processor Reset
+AT91C_RSTC_PERRST         EQU (0x1 <<  2) ;- (RSTC) Peripheral Reset
+AT91C_RSTC_EXTRST         EQU (0x1 <<  3) ;- (RSTC) External Reset
+AT91C_RSTC_KEY            EQU (0xFF << 24) ;- (RSTC) Password
+// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+AT91C_RSTC_URSTS          EQU (0x1 <<  0) ;- (RSTC) User Reset Status
+AT91C_RSTC_BODSTS         EQU (0x1 <<  1) ;- (RSTC) Brownout Detection Status
+AT91C_RSTC_RSTTYP         EQU (0x7 <<  8) ;- (RSTC) Reset Type
+AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 <<  8) ;- (RSTC) Power-up Reset. VDDCORE rising.
+AT91C_RSTC_RSTTYP_WAKEUP  EQU (0x1 <<  8) ;- (RSTC) WakeUp Reset. VDDCORE rising.
+AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 <<  8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured.
+AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 <<  8) ;- (RSTC) Software Reset. Processor reset required by the software.
+AT91C_RSTC_RSTTYP_USER    EQU (0x4 <<  8) ;- (RSTC) User Reset. NRST pin detected low.
+AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 <<  8) ;- (RSTC) Brownout Reset occured.
+AT91C_RSTC_NRSTL          EQU (0x1 << 16) ;- (RSTC) NRST pin level
+AT91C_RSTC_SRCMP          EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress.
+// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+AT91C_RSTC_URSTEN         EQU (0x1 <<  0) ;- (RSTC) User Reset Enable
+AT91C_RSTC_URSTIEN        EQU (0x1 <<  4) ;- (RSTC) User Reset Interrupt Enable
+AT91C_RSTC_ERSTL          EQU (0xF <<  8) ;- (RSTC) User Reset Enable
+AT91C_RSTC_BODIEN         EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// - *****************************************************************************
+// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+AT91C_RTTC_RTPRES         EQU (0xFFFF <<  0) ;- (RTTC) Real-time Timer Prescaler Value
+AT91C_RTTC_ALMIEN         EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable
+AT91C_RTTC_RTTINCIEN      EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable
+AT91C_RTTC_RTTRST         EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart
+// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+AT91C_RTTC_ALMV           EQU (0x0 <<  0) ;- (RTTC) Alarm Value
+// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+AT91C_RTTC_CRTV           EQU (0x0 <<  0) ;- (RTTC) Current Real-time Value
+// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+AT91C_RTTC_ALMS           EQU (0x1 <<  0) ;- (RTTC) Real-time Alarm Status
+AT91C_RTTC_RTTINC         EQU (0x1 <<  1) ;- (RTTC) Real-time Timer Increment
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// - *****************************************************************************
+// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+AT91C_PITC_PIV            EQU (0xFFFFF <<  0) ;- (PITC) Periodic Interval Value
+AT91C_PITC_PITEN          EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled
+AT91C_PITC_PITIEN         EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable
+// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+AT91C_PITC_PITS           EQU (0x1 <<  0) ;- (PITC) Periodic Interval Timer Status
+// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+AT91C_PITC_CPIV           EQU (0xFFFFF <<  0) ;- (PITC) Current Periodic Interval Value
+AT91C_PITC_PICNT          EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter
+// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// - *****************************************************************************
+// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+AT91C_WDTC_WDRSTT         EQU (0x1 <<  0) ;- (WDTC) Watchdog Restart
+AT91C_WDTC_KEY            EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password
+// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+AT91C_WDTC_WDV            EQU (0xFFF <<  0) ;- (WDTC) Watchdog Timer Restart
+AT91C_WDTC_WDFIEN         EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable
+AT91C_WDTC_WDRSTEN        EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable
+AT91C_WDTC_WDRPROC        EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart
+AT91C_WDTC_WDDIS          EQU (0x1 << 15) ;- (WDTC) Watchdog Disable
+AT91C_WDTC_WDD            EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value
+AT91C_WDTC_WDDBGHLT       EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt
+AT91C_WDTC_WDIDLEHLT      EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt
+// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+AT91C_WDTC_WDUNF          EQU (0x1 <<  0) ;- (WDTC) Watchdog Underflow
+AT91C_WDTC_WDERR          EQU (0x1 <<  1) ;- (WDTC) Watchdog Error
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
+// - *****************************************************************************
+// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
+AT91C_VREG_PSTDBY         EQU (0x1 <<  0) ;- (VREG) Voltage Regulator Power Standby Mode
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// - *****************************************************************************
+// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+AT91C_MC_RCB              EQU (0x1 <<  0) ;- (MC) Remap Command Bit
+// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+AT91C_MC_UNDADD           EQU (0x1 <<  0) ;- (MC) Undefined Addess Abort Status
+AT91C_MC_MISADD           EQU (0x1 <<  1) ;- (MC) Misaligned Addess Abort Status
+AT91C_MC_ABTSZ            EQU (0x3 <<  8) ;- (MC) Abort Size Status
+AT91C_MC_ABTSZ_BYTE       EQU (0x0 <<  8) ;- (MC) Byte
+AT91C_MC_ABTSZ_HWORD      EQU (0x1 <<  8) ;- (MC) Half-word
+AT91C_MC_ABTSZ_WORD       EQU (0x2 <<  8) ;- (MC) Word
+AT91C_MC_ABTTYP           EQU (0x3 << 10) ;- (MC) Abort Type Status
+AT91C_MC_ABTTYP_DATAR     EQU (0x0 << 10) ;- (MC) Data Read
+AT91C_MC_ABTTYP_DATAW     EQU (0x1 << 10) ;- (MC) Data Write
+AT91C_MC_ABTTYP_FETCH     EQU (0x2 << 10) ;- (MC) Code Fetch
+AT91C_MC_MST0             EQU (0x1 << 16) ;- (MC) Master 0 Abort Source
+AT91C_MC_MST1             EQU (0x1 << 17) ;- (MC) Master 1 Abort Source
+AT91C_MC_SVMST0           EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source
+AT91C_MC_SVMST1           EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source
+// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+AT91C_MC_FRDY             EQU (0x1 <<  0) ;- (MC) Flash Ready
+AT91C_MC_LOCKE            EQU (0x1 <<  2) ;- (MC) Lock Error
+AT91C_MC_PROGE            EQU (0x1 <<  3) ;- (MC) Programming Error
+AT91C_MC_NEBP             EQU (0x1 <<  7) ;- (MC) No Erase Before Programming
+AT91C_MC_FWS              EQU (0x3 <<  8) ;- (MC) Flash Wait State
+AT91C_MC_FWS_0FWS         EQU (0x0 <<  8) ;- (MC) 1 cycle for Read, 2 for Write operations
+AT91C_MC_FWS_1FWS         EQU (0x1 <<  8) ;- (MC) 2 cycles for Read, 3 for Write operations
+AT91C_MC_FWS_2FWS         EQU (0x2 <<  8) ;- (MC) 3 cycles for Read, 4 for Write operations
+AT91C_MC_FWS_3FWS         EQU (0x3 <<  8) ;- (MC) 4 cycles for Read, 4 for Write operations
+AT91C_MC_FMCN             EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number
+// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+AT91C_MC_FCMD             EQU (0xF <<  0) ;- (MC) Flash Command
+AT91C_MC_FCMD_START_PROG  EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN.
+AT91C_MC_FCMD_LOCK        EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed.
+AT91C_MC_FCMD_UNLOCK      EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+AT91C_MC_FCMD_ERASE_ALL   EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+AT91C_MC_FCMD_SET_GP_NVM  EQU (0xB) ;- (MC) Set General Purpose NVM bits.
+AT91C_MC_FCMD_CLR_GP_NVM  EQU (0xD) ;- (MC) Clear General Purpose NVM bits.
+AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit.
+AT91C_MC_PAGEN            EQU (0x3FF <<  8) ;- (MC) Page Number
+AT91C_MC_KEY              EQU (0xFF << 24) ;- (MC) Writing Protect Key
+// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+AT91C_MC_SECURITY         EQU (0x1 <<  4) ;- (MC) Security Bit Status
+AT91C_MC_GPNVM0           EQU (0x1 <<  8) ;- (MC) Sector 0 Lock Status
+AT91C_MC_GPNVM1           EQU (0x1 <<  9) ;- (MC) Sector 1 Lock Status
+AT91C_MC_GPNVM2           EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status
+AT91C_MC_GPNVM3           EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status
+AT91C_MC_GPNVM4           EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status
+AT91C_MC_GPNVM5           EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status
+AT91C_MC_GPNVM6           EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status
+AT91C_MC_GPNVM7           EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status
+AT91C_MC_LOCKS0           EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status
+AT91C_MC_LOCKS1           EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status
+AT91C_MC_LOCKS2           EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status
+AT91C_MC_LOCKS3           EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status
+AT91C_MC_LOCKS4           EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status
+AT91C_MC_LOCKS5           EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status
+AT91C_MC_LOCKS6           EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status
+AT91C_MC_LOCKS7           EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status
+AT91C_MC_LOCKS8           EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status
+AT91C_MC_LOCKS9           EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status
+AT91C_MC_LOCKS10          EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status
+AT91C_MC_LOCKS11          EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status
+AT91C_MC_LOCKS12          EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status
+AT91C_MC_LOCKS13          EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status
+AT91C_MC_LOCKS14          EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status
+AT91C_MC_LOCKS15          EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// - *****************************************************************************
+// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+AT91C_SPI_SPIEN           EQU (0x1 <<  0) ;- (SPI) SPI Enable
+AT91C_SPI_SPIDIS          EQU (0x1 <<  1) ;- (SPI) SPI Disable
+AT91C_SPI_SWRST           EQU (0x1 <<  7) ;- (SPI) SPI Software reset
+AT91C_SPI_LASTXFER        EQU (0x1 << 24) ;- (SPI) SPI Last Transfer
+// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+AT91C_SPI_MSTR            EQU (0x1 <<  0) ;- (SPI) Master/Slave Mode
+AT91C_SPI_PS              EQU (0x1 <<  1) ;- (SPI) Peripheral Select
+AT91C_SPI_PS_FIXED        EQU (0x0 <<  1) ;- (SPI) Fixed Peripheral Select
+AT91C_SPI_PS_VARIABLE     EQU (0x1 <<  1) ;- (SPI) Variable Peripheral Select
+AT91C_SPI_PCSDEC          EQU (0x1 <<  2) ;- (SPI) Chip Select Decode
+AT91C_SPI_FDIV            EQU (0x1 <<  3) ;- (SPI) Clock Selection
+AT91C_SPI_MODFDIS         EQU (0x1 <<  4) ;- (SPI) Mode Fault Detection
+AT91C_SPI_LLB             EQU (0x1 <<  7) ;- (SPI) Clock Selection
+AT91C_SPI_PCS             EQU (0xF << 16) ;- (SPI) Peripheral Chip Select
+AT91C_SPI_DLYBCS          EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects
+// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+AT91C_SPI_RD              EQU (0xFFFF <<  0) ;- (SPI) Receive Data
+AT91C_SPI_RPCS            EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
+// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+AT91C_SPI_TD              EQU (0xFFFF <<  0) ;- (SPI) Transmit Data
+AT91C_SPI_TPCS            EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
+// - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+AT91C_SPI_RDRF            EQU (0x1 <<  0) ;- (SPI) Receive Data Register Full
+AT91C_SPI_TDRE            EQU (0x1 <<  1) ;- (SPI) Transmit Data Register Empty
+AT91C_SPI_MODF            EQU (0x1 <<  2) ;- (SPI) Mode Fault Error
+AT91C_SPI_OVRES           EQU (0x1 <<  3) ;- (SPI) Overrun Error Status
+AT91C_SPI_ENDRX           EQU (0x1 <<  4) ;- (SPI) End of Receiver Transfer
+AT91C_SPI_ENDTX           EQU (0x1 <<  5) ;- (SPI) End of Receiver Transfer
+AT91C_SPI_RXBUFF          EQU (0x1 <<  6) ;- (SPI) RXBUFF Interrupt
+AT91C_SPI_TXBUFE          EQU (0x1 <<  7) ;- (SPI) TXBUFE Interrupt
+AT91C_SPI_NSSR            EQU (0x1 <<  8) ;- (SPI) NSSR Interrupt
+AT91C_SPI_TXEMPTY         EQU (0x1 <<  9) ;- (SPI) TXEMPTY Interrupt
+AT91C_SPI_SPIENS          EQU (0x1 << 16) ;- (SPI) Enable Status
+// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+AT91C_SPI_CPOL            EQU (0x1 <<  0) ;- (SPI) Clock Polarity
+AT91C_SPI_NCPHA           EQU (0x1 <<  1) ;- (SPI) Clock Phase
+AT91C_SPI_CSAAT           EQU (0x1 <<  3) ;- (SPI) Chip Select Active After Transfer
+AT91C_SPI_BITS            EQU (0xF <<  4) ;- (SPI) Bits Per Transfer
+AT91C_SPI_BITS_8          EQU (0x0 <<  4) ;- (SPI) 8 Bits Per transfer
+AT91C_SPI_BITS_9          EQU (0x1 <<  4) ;- (SPI) 9 Bits Per transfer
+AT91C_SPI_BITS_10         EQU (0x2 <<  4) ;- (SPI) 10 Bits Per transfer
+AT91C_SPI_BITS_11         EQU (0x3 <<  4) ;- (SPI) 11 Bits Per transfer
+AT91C_SPI_BITS_12         EQU (0x4 <<  4) ;- (SPI) 12 Bits Per transfer
+AT91C_SPI_BITS_13         EQU (0x5 <<  4) ;- (SPI) 13 Bits Per transfer
+AT91C_SPI_BITS_14         EQU (0x6 <<  4) ;- (SPI) 14 Bits Per transfer
+AT91C_SPI_BITS_15         EQU (0x7 <<  4) ;- (SPI) 15 Bits Per transfer
+AT91C_SPI_BITS_16         EQU (0x8 <<  4) ;- (SPI) 16 Bits Per transfer
+AT91C_SPI_SCBR            EQU (0xFF <<  8) ;- (SPI) Serial Clock Baud Rate
+AT91C_SPI_DLYBS           EQU (0xFF << 16) ;- (SPI) Delay Before SPCK
+AT91C_SPI_DLYBCT          EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Usart
+// - *****************************************************************************
+// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+AT91C_US_STTBRK           EQU (0x1 <<  9) ;- (USART) Start Break
+AT91C_US_STPBRK           EQU (0x1 << 10) ;- (USART) Stop Break
+AT91C_US_STTTO            EQU (0x1 << 11) ;- (USART) Start Time-out
+AT91C_US_SENDA            EQU (0x1 << 12) ;- (USART) Send Address
+AT91C_US_RSTIT            EQU (0x1 << 13) ;- (USART) Reset Iterations
+AT91C_US_RSTNACK          EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge
+AT91C_US_RETTO            EQU (0x1 << 15) ;- (USART) Rearm Time-out
+AT91C_US_DTREN            EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable
+AT91C_US_DTRDIS           EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable
+AT91C_US_RTSEN            EQU (0x1 << 18) ;- (USART) Request to Send enable
+AT91C_US_RTSDIS           EQU (0x1 << 19) ;- (USART) Request to Send Disable
+// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+AT91C_US_USMODE           EQU (0xF <<  0) ;- (USART) Usart mode
+AT91C_US_USMODE_NORMAL    EQU (0x0) ;- (USART) Normal
+AT91C_US_USMODE_RS485     EQU (0x1) ;- (USART) RS485
+AT91C_US_USMODE_HWHSH     EQU (0x2) ;- (USART) Hardware Handshaking
+AT91C_US_USMODE_MODEM     EQU (0x3) ;- (USART) Modem
+AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0
+AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1
+AT91C_US_USMODE_IRDA      EQU (0x8) ;- (USART) IrDA
+AT91C_US_USMODE_SWHSH     EQU (0xC) ;- (USART) Software Handshaking
+AT91C_US_CLKS             EQU (0x3 <<  4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
+AT91C_US_CLKS_CLOCK       EQU (0x0 <<  4) ;- (USART) Clock
+AT91C_US_CLKS_FDIV1       EQU (0x1 <<  4) ;- (USART) fdiv1
+AT91C_US_CLKS_SLOW        EQU (0x2 <<  4) ;- (USART) slow_clock (ARM)
+AT91C_US_CLKS_EXT         EQU (0x3 <<  4) ;- (USART) External (SCK)
+AT91C_US_CHRL             EQU (0x3 <<  6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
+AT91C_US_CHRL_5_BITS      EQU (0x0 <<  6) ;- (USART) Character Length: 5 bits
+AT91C_US_CHRL_6_BITS      EQU (0x1 <<  6) ;- (USART) Character Length: 6 bits
+AT91C_US_CHRL_7_BITS      EQU (0x2 <<  6) ;- (USART) Character Length: 7 bits
+AT91C_US_CHRL_8_BITS      EQU (0x3 <<  6) ;- (USART) Character Length: 8 bits
+AT91C_US_SYNC             EQU (0x1 <<  8) ;- (USART) Synchronous Mode Select
+AT91C_US_NBSTOP           EQU (0x3 << 12) ;- (USART) Number of Stop bits
+AT91C_US_NBSTOP_1_BIT     EQU (0x0 << 12) ;- (USART) 1 stop bit
+AT91C_US_NBSTOP_15_BIT    EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+AT91C_US_NBSTOP_2_BIT     EQU (0x2 << 12) ;- (USART) 2 stop bits
+AT91C_US_MSBF             EQU (0x1 << 16) ;- (USART) Bit Order
+AT91C_US_MODE9            EQU (0x1 << 17) ;- (USART) 9-bit Character length
+AT91C_US_CKLO             EQU (0x1 << 18) ;- (USART) Clock Output Select
+AT91C_US_OVER             EQU (0x1 << 19) ;- (USART) Over Sampling Mode
+AT91C_US_INACK            EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge
+AT91C_US_DSNACK           EQU (0x1 << 21) ;- (USART) Disable Successive NACK
+AT91C_US_MAX_ITER         EQU (0x1 << 24) ;- (USART) Number of Repetitions
+AT91C_US_FILTER           EQU (0x1 << 28) ;- (USART) Receive Line Filter
+// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+AT91C_US_RXBRK            EQU (0x1 <<  2) ;- (USART) Break Received/End of Break
+AT91C_US_TIMEOUT          EQU (0x1 <<  8) ;- (USART) Receiver Time-out
+AT91C_US_ITERATION        EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached
+AT91C_US_NACK             EQU (0x1 << 13) ;- (USART) Non Acknowledge
+AT91C_US_RIIC             EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag
+AT91C_US_DSRIC            EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag
+AT91C_US_DCDIC            EQU (0x1 << 18) ;- (USART) Data Carrier Flag
+AT91C_US_CTSIC            EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag
+// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+AT91C_US_RI               EQU (0x1 << 20) ;- (USART) Image of RI Input
+AT91C_US_DSR              EQU (0x1 << 21) ;- (USART) Image of DSR Input
+AT91C_US_DCD              EQU (0x1 << 22) ;- (USART) Image of DCD Input
+AT91C_US_CTS              EQU (0x1 << 23) ;- (USART) Image of CTS Input
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// - *****************************************************************************
+// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+AT91C_SSC_RXEN            EQU (0x1 <<  0) ;- (SSC) Receive Enable
+AT91C_SSC_RXDIS           EQU (0x1 <<  1) ;- (SSC) Receive Disable
+AT91C_SSC_TXEN            EQU (0x1 <<  8) ;- (SSC) Transmit Enable
+AT91C_SSC_TXDIS           EQU (0x1 <<  9) ;- (SSC) Transmit Disable
+AT91C_SSC_SWRST           EQU (0x1 << 15) ;- (SSC) Software Reset
+// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+AT91C_SSC_CKS             EQU (0x3 <<  0) ;- (SSC) Receive/Transmit Clock Selection
+AT91C_SSC_CKS_DIV         EQU (0x0) ;- (SSC) Divided Clock
+AT91C_SSC_CKS_TK          EQU (0x1) ;- (SSC) TK Clock signal
+AT91C_SSC_CKS_RK          EQU (0x2) ;- (SSC) RK pin
+AT91C_SSC_CKO             EQU (0x7 <<  2) ;- (SSC) Receive/Transmit Clock Output Mode Selection
+AT91C_SSC_CKO_NONE        EQU (0x0 <<  2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+AT91C_SSC_CKO_CONTINOUS   EQU (0x1 <<  2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output
+AT91C_SSC_CKO_DATA_TX     EQU (0x2 <<  2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+AT91C_SSC_CKI             EQU (0x1 <<  5) ;- (SSC) Receive/Transmit Clock Inversion
+AT91C_SSC_START           EQU (0xF <<  8) ;- (SSC) Receive/Transmit Start Selection
+AT91C_SSC_START_CONTINOUS EQU (0x0 <<  8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+AT91C_SSC_START_TX        EQU (0x1 <<  8) ;- (SSC) Transmit/Receive start
+AT91C_SSC_START_LOW_RF    EQU (0x2 <<  8) ;- (SSC) Detection of a low level on RF input
+AT91C_SSC_START_HIGH_RF   EQU (0x3 <<  8) ;- (SSC) Detection of a high level on RF input
+AT91C_SSC_START_FALL_RF   EQU (0x4 <<  8) ;- (SSC) Detection of a falling edge on RF input
+AT91C_SSC_START_RISE_RF   EQU (0x5 <<  8) ;- (SSC) Detection of a rising edge on RF input
+AT91C_SSC_START_LEVEL_RF  EQU (0x6 <<  8) ;- (SSC) Detection of any level change on RF input
+AT91C_SSC_START_EDGE_RF   EQU (0x7 <<  8) ;- (SSC) Detection of any edge on RF input
+AT91C_SSC_START_0         EQU (0x8 <<  8) ;- (SSC) Compare 0
+AT91C_SSC_STTDLY          EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay
+AT91C_SSC_PERIOD          EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection
+// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+AT91C_SSC_DATLEN          EQU (0x1F <<  0) ;- (SSC) Data Length
+AT91C_SSC_LOOP            EQU (0x1 <<  5) ;- (SSC) Loop Mode
+AT91C_SSC_MSBF            EQU (0x1 <<  7) ;- (SSC) Most Significant Bit First
+AT91C_SSC_DATNB           EQU (0xF <<  8) ;- (SSC) Data Number per Frame
+AT91C_SSC_FSLEN           EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length
+AT91C_SSC_FSOS            EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection
+AT91C_SSC_FSOS_NONE       EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+AT91C_SSC_FSOS_NEGATIVE   EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+AT91C_SSC_FSOS_POSITIVE   EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+AT91C_SSC_FSOS_LOW        EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+AT91C_SSC_FSOS_HIGH       EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+AT91C_SSC_FSOS_TOGGLE     EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+AT91C_SSC_FSEDGE          EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection
+// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+AT91C_SSC_DATDEF          EQU (0x1 <<  5) ;- (SSC) Data Default Value
+AT91C_SSC_FSDEN           EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable
+// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+AT91C_SSC_TXRDY           EQU (0x1 <<  0) ;- (SSC) Transmit Ready
+AT91C_SSC_TXEMPTY         EQU (0x1 <<  1) ;- (SSC) Transmit Empty
+AT91C_SSC_ENDTX           EQU (0x1 <<  2) ;- (SSC) End Of Transmission
+AT91C_SSC_TXBUFE          EQU (0x1 <<  3) ;- (SSC) Transmit Buffer Empty
+AT91C_SSC_RXRDY           EQU (0x1 <<  4) ;- (SSC) Receive Ready
+AT91C_SSC_OVRUN           EQU (0x1 <<  5) ;- (SSC) Receive Overrun
+AT91C_SSC_ENDRX           EQU (0x1 <<  6) ;- (SSC) End of Reception
+AT91C_SSC_RXBUFF          EQU (0x1 <<  7) ;- (SSC) Receive Buffer Full
+AT91C_SSC_TXSYN           EQU (0x1 << 10) ;- (SSC) Transmit Sync
+AT91C_SSC_RXSYN           EQU (0x1 << 11) ;- (SSC) Receive Sync
+AT91C_SSC_TXENA           EQU (0x1 << 16) ;- (SSC) Transmit Enable
+AT91C_SSC_RXENA           EQU (0x1 << 17) ;- (SSC) Receive Enable
+// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// - *****************************************************************************
+// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+AT91C_TWI_START           EQU (0x1 <<  0) ;- (TWI) Send a START Condition
+AT91C_TWI_STOP            EQU (0x1 <<  1) ;- (TWI) Send a STOP Condition
+AT91C_TWI_MSEN            EQU (0x1 <<  2) ;- (TWI) TWI Master Transfer Enabled
+AT91C_TWI_MSDIS           EQU (0x1 <<  3) ;- (TWI) TWI Master Transfer Disabled
+AT91C_TWI_SWRST           EQU (0x1 <<  7) ;- (TWI) Software Reset
+// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+AT91C_TWI_IADRSZ          EQU (0x3 <<  8) ;- (TWI) Internal Device Address Size
+AT91C_TWI_IADRSZ_NO       EQU (0x0 <<  8) ;- (TWI) No internal device address
+AT91C_TWI_IADRSZ_1_BYTE   EQU (0x1 <<  8) ;- (TWI) One-byte internal device address
+AT91C_TWI_IADRSZ_2_BYTE   EQU (0x2 <<  8) ;- (TWI) Two-byte internal device address
+AT91C_TWI_IADRSZ_3_BYTE   EQU (0x3 <<  8) ;- (TWI) Three-byte internal device address
+AT91C_TWI_MREAD           EQU (0x1 << 12) ;- (TWI) Master Read Direction
+AT91C_TWI_DADR            EQU (0x7F << 16) ;- (TWI) Device Address
+// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+AT91C_TWI_CLDIV           EQU (0xFF <<  0) ;- (TWI) Clock Low Divider
+AT91C_TWI_CHDIV           EQU (0xFF <<  8) ;- (TWI) Clock High Divider
+AT91C_TWI_CKDIV           EQU (0x7 << 16) ;- (TWI) Clock Divider
+// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+AT91C_TWI_TXCOMP          EQU (0x1 <<  0) ;- (TWI) Transmission Completed
+AT91C_TWI_RXRDY           EQU (0x1 <<  1) ;- (TWI) Receive holding register ReaDY
+AT91C_TWI_TXRDY           EQU (0x1 <<  2) ;- (TWI) Transmit holding register ReaDY
+AT91C_TWI_OVRE            EQU (0x1 <<  6) ;- (TWI) Overrun Error
+AT91C_TWI_UNRE            EQU (0x1 <<  7) ;- (TWI) Underrun Error
+AT91C_TWI_NACK            EQU (0x1 <<  8) ;- (TWI) Not Acknowledged
+// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// - *****************************************************************************
+// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+AT91C_PWMC_CPRE           EQU (0xF <<  0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+AT91C_PWMC_CPRE_MCK       EQU (0x0) ;- (PWMC_CH) 
+AT91C_PWMC_CPRE_MCKA      EQU (0xB) ;- (PWMC_CH) 
+AT91C_PWMC_CPRE_MCKB      EQU (0xC) ;- (PWMC_CH) 
+AT91C_PWMC_CALG           EQU (0x1 <<  8) ;- (PWMC_CH) Channel Alignment
+AT91C_PWMC_CPOL           EQU (0x1 <<  9) ;- (PWMC_CH) Channel Polarity
+AT91C_PWMC_CPD            EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period
+// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+AT91C_PWMC_CDTY           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Duty Cycle
+// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+AT91C_PWMC_CPRD           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Period
+// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+AT91C_PWMC_CCNT           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Counter
+// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+AT91C_PWMC_CUPD           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Update
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// - *****************************************************************************
+// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+AT91C_PWMC_DIVA           EQU (0xFF <<  0) ;- (PWMC) CLKA divide factor.
+AT91C_PWMC_PREA           EQU (0xF <<  8) ;- (PWMC) Divider Input Clock Prescaler A
+AT91C_PWMC_PREA_MCK       EQU (0x0 <<  8) ;- (PWMC) 
+AT91C_PWMC_DIVB           EQU (0xFF << 16) ;- (PWMC) CLKB divide factor.
+AT91C_PWMC_PREB           EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B
+AT91C_PWMC_PREB_MCK       EQU (0x0 << 24) ;- (PWMC) 
+// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+AT91C_PWMC_CHID0          EQU (0x1 <<  0) ;- (PWMC) Channel ID 0
+AT91C_PWMC_CHID1          EQU (0x1 <<  1) ;- (PWMC) Channel ID 1
+AT91C_PWMC_CHID2          EQU (0x1 <<  2) ;- (PWMC) Channel ID 2
+AT91C_PWMC_CHID3          EQU (0x1 <<  3) ;- (PWMC) Channel ID 3
+// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR USB Device Interface
+// - *****************************************************************************
+// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+AT91C_UDP_FRM_NUM         EQU (0x7FF <<  0) ;- (UDP) Frame Number as Defined in the Packet Field Formats
+AT91C_UDP_FRM_ERR         EQU (0x1 << 16) ;- (UDP) Frame Error
+AT91C_UDP_FRM_OK          EQU (0x1 << 17) ;- (UDP) Frame OK
+// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+AT91C_UDP_FADDEN          EQU (0x1 <<  0) ;- (UDP) Function Address Enable
+AT91C_UDP_CONFG           EQU (0x1 <<  1) ;- (UDP) Configured
+AT91C_UDP_ESR             EQU (0x1 <<  2) ;- (UDP) Enable Send Resume
+AT91C_UDP_RSMINPR         EQU (0x1 <<  3) ;- (UDP) A Resume Has Been Sent to the Host
+AT91C_UDP_RMWUPE          EQU (0x1 <<  4) ;- (UDP) Remote Wake Up Enable
+// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+AT91C_UDP_FADD            EQU (0xFF <<  0) ;- (UDP) Function Address Value
+AT91C_UDP_FEN             EQU (0x1 <<  8) ;- (UDP) Function Enable
+// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+AT91C_UDP_EPINT0          EQU (0x1 <<  0) ;- (UDP) Endpoint 0 Interrupt
+AT91C_UDP_EPINT1          EQU (0x1 <<  1) ;- (UDP) Endpoint 0 Interrupt
+AT91C_UDP_EPINT2          EQU (0x1 <<  2) ;- (UDP) Endpoint 2 Interrupt
+AT91C_UDP_EPINT3          EQU (0x1 <<  3) ;- (UDP) Endpoint 3 Interrupt
+AT91C_UDP_EPINT4          EQU (0x1 <<  4) ;- (UDP) Endpoint 4 Interrupt
+AT91C_UDP_EPINT5          EQU (0x1 <<  5) ;- (UDP) Endpoint 5 Interrupt
+AT91C_UDP_RXSUSP          EQU (0x1 <<  8) ;- (UDP) USB Suspend Interrupt
+AT91C_UDP_RXRSM           EQU (0x1 <<  9) ;- (UDP) USB Resume Interrupt
+AT91C_UDP_EXTRSM          EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt
+AT91C_UDP_SOFINT          EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt
+AT91C_UDP_WAKEUP          EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt
+// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+AT91C_UDP_ENDBUSRES       EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt
+// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+AT91C_UDP_EP0             EQU (0x1 <<  0) ;- (UDP) Reset Endpoint 0
+AT91C_UDP_EP1             EQU (0x1 <<  1) ;- (UDP) Reset Endpoint 1
+AT91C_UDP_EP2             EQU (0x1 <<  2) ;- (UDP) Reset Endpoint 2
+AT91C_UDP_EP3             EQU (0x1 <<  3) ;- (UDP) Reset Endpoint 3
+AT91C_UDP_EP4             EQU (0x1 <<  4) ;- (UDP) Reset Endpoint 4
+AT91C_UDP_EP5             EQU (0x1 <<  5) ;- (UDP) Reset Endpoint 5
+// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+AT91C_UDP_TXCOMP          EQU (0x1 <<  0) ;- (UDP) Generates an IN packet with data previously written in the DPR
+AT91C_UDP_RX_DATA_BK0     EQU (0x1 <<  1) ;- (UDP) Receive Data Bank 0
+AT91C_UDP_RXSETUP         EQU (0x1 <<  2) ;- (UDP) Sends STALL to the Host (Control endpoints)
+AT91C_UDP_ISOERROR        EQU (0x1 <<  3) ;- (UDP) Isochronous error (Isochronous endpoints)
+AT91C_UDP_TXPKTRDY        EQU (0x1 <<  4) ;- (UDP) Transmit Packet Ready
+AT91C_UDP_FORCESTALL      EQU (0x1 <<  5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+AT91C_UDP_RX_DATA_BK1     EQU (0x1 <<  6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+AT91C_UDP_DIR             EQU (0x1 <<  7) ;- (UDP) Transfer Direction
+AT91C_UDP_EPTYPE          EQU (0x7 <<  8) ;- (UDP) Endpoint type
+AT91C_UDP_EPTYPE_CTRL     EQU (0x0 <<  8) ;- (UDP) Control
+AT91C_UDP_EPTYPE_ISO_OUT  EQU (0x1 <<  8) ;- (UDP) Isochronous OUT
+AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 <<  8) ;- (UDP) Bulk OUT
+AT91C_UDP_EPTYPE_INT_OUT  EQU (0x3 <<  8) ;- (UDP) Interrupt OUT
+AT91C_UDP_EPTYPE_ISO_IN   EQU (0x5 <<  8) ;- (UDP) Isochronous IN
+AT91C_UDP_EPTYPE_BULK_IN  EQU (0x6 <<  8) ;- (UDP) Bulk IN
+AT91C_UDP_EPTYPE_INT_IN   EQU (0x7 <<  8) ;- (UDP) Interrupt IN
+AT91C_UDP_DTGLE           EQU (0x1 << 11) ;- (UDP) Data Toggle
+AT91C_UDP_EPEDS           EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable
+AT91C_UDP_RXBYTECNT       EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO
+// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+AT91C_UDP_TXVDIS          EQU (0x1 <<  8) ;- (UDP) 
+AT91C_UDP_PUON            EQU (0x1 <<  9) ;- (UDP) Pull-up ON
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// - *****************************************************************************
+// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+AT91C_TC_CLKEN            EQU (0x1 <<  0) ;- (TC) Counter Clock Enable Command
+AT91C_TC_CLKDIS           EQU (0x1 <<  1) ;- (TC) Counter Clock Disable Command
+AT91C_TC_SWTRG            EQU (0x1 <<  2) ;- (TC) Software Trigger Command
+// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+AT91C_TC_CLKS             EQU (0x7 <<  0) ;- (TC) Clock Selection
+AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK
+AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK
+AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK
+AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK
+AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK
+AT91C_TC_CLKS_XC0         EQU (0x5) ;- (TC) Clock selected: XC0
+AT91C_TC_CLKS_XC1         EQU (0x6) ;- (TC) Clock selected: XC1
+AT91C_TC_CLKS_XC2         EQU (0x7) ;- (TC) Clock selected: XC2
+AT91C_TC_CLKI             EQU (0x1 <<  3) ;- (TC) Clock Invert
+AT91C_TC_BURST            EQU (0x3 <<  4) ;- (TC) Burst Signal Selection
+AT91C_TC_BURST_NONE       EQU (0x0 <<  4) ;- (TC) The clock is not gated by an external signal
+AT91C_TC_BURST_XC0        EQU (0x1 <<  4) ;- (TC) XC0 is ANDed with the selected clock
+AT91C_TC_BURST_XC1        EQU (0x2 <<  4) ;- (TC) XC1 is ANDed with the selected clock
+AT91C_TC_BURST_XC2        EQU (0x3 <<  4) ;- (TC) XC2 is ANDed with the selected clock
+AT91C_TC_CPCSTOP          EQU (0x1 <<  6) ;- (TC) Counter Clock Stopped with RC Compare
+AT91C_TC_LDBSTOP          EQU (0x1 <<  6) ;- (TC) Counter Clock Stopped with RB Loading
+AT91C_TC_CPCDIS           EQU (0x1 <<  7) ;- (TC) Counter Clock Disable with RC Compare
+AT91C_TC_LDBDIS           EQU (0x1 <<  7) ;- (TC) Counter Clock Disabled with RB Loading
+AT91C_TC_ETRGEDG          EQU (0x3 <<  8) ;- (TC) External Trigger Edge Selection
+AT91C_TC_ETRGEDG_NONE     EQU (0x0 <<  8) ;- (TC) Edge: None
+AT91C_TC_ETRGEDG_RISING   EQU (0x1 <<  8) ;- (TC) Edge: rising edge
+AT91C_TC_ETRGEDG_FALLING  EQU (0x2 <<  8) ;- (TC) Edge: falling edge
+AT91C_TC_ETRGEDG_BOTH     EQU (0x3 <<  8) ;- (TC) Edge: each edge
+AT91C_TC_EEVTEDG          EQU (0x3 <<  8) ;- (TC) External Event Edge Selection
+AT91C_TC_EEVTEDG_NONE     EQU (0x0 <<  8) ;- (TC) Edge: None
+AT91C_TC_EEVTEDG_RISING   EQU (0x1 <<  8) ;- (TC) Edge: rising edge
+AT91C_TC_EEVTEDG_FALLING  EQU (0x2 <<  8) ;- (TC) Edge: falling edge
+AT91C_TC_EEVTEDG_BOTH     EQU (0x3 <<  8) ;- (TC) Edge: each edge
+AT91C_TC_EEVT             EQU (0x3 << 10) ;- (TC) External Event  Selection
+AT91C_TC_EEVT_TIOB        EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input
+AT91C_TC_EEVT_XC0         EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output
+AT91C_TC_EEVT_XC1         EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output
+AT91C_TC_EEVT_XC2         EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output
+AT91C_TC_ABETRG           EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection
+AT91C_TC_ENETRG           EQU (0x1 << 12) ;- (TC) External Event Trigger enable
+AT91C_TC_WAVESEL          EQU (0x3 << 13) ;- (TC) Waveform  Selection
+AT91C_TC_WAVESEL_UP       EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare
+AT91C_TC_WAVESEL_UPDOWN   EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare
+AT91C_TC_WAVESEL_UP_AUTO  EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare
+AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare
+AT91C_TC_CPCTRG           EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable
+AT91C_TC_WAVE             EQU (0x1 << 15) ;- (TC) 
+AT91C_TC_ACPA             EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA
+AT91C_TC_ACPA_NONE        EQU (0x0 << 16) ;- (TC) Effect: none
+AT91C_TC_ACPA_SET         EQU (0x1 << 16) ;- (TC) Effect: set
+AT91C_TC_ACPA_CLEAR       EQU (0x2 << 16) ;- (TC) Effect: clear
+AT91C_TC_ACPA_TOGGLE      EQU (0x3 << 16) ;- (TC) Effect: toggle
+AT91C_TC_LDRA             EQU (0x3 << 16) ;- (TC) RA Loading Selection
+AT91C_TC_LDRA_NONE        EQU (0x0 << 16) ;- (TC) Edge: None
+AT91C_TC_LDRA_RISING      EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA
+AT91C_TC_LDRA_FALLING     EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA
+AT91C_TC_LDRA_BOTH        EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA
+AT91C_TC_ACPC             EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA
+AT91C_TC_ACPC_NONE        EQU (0x0 << 18) ;- (TC) Effect: none
+AT91C_TC_ACPC_SET         EQU (0x1 << 18) ;- (TC) Effect: set
+AT91C_TC_ACPC_CLEAR       EQU (0x2 << 18) ;- (TC) Effect: clear
+AT91C_TC_ACPC_TOGGLE      EQU (0x3 << 18) ;- (TC) Effect: toggle
+AT91C_TC_LDRB             EQU (0x3 << 18) ;- (TC) RB Loading Selection
+AT91C_TC_LDRB_NONE        EQU (0x0 << 18) ;- (TC) Edge: None
+AT91C_TC_LDRB_RISING      EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA
+AT91C_TC_LDRB_FALLING     EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA
+AT91C_TC_LDRB_BOTH        EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA
+AT91C_TC_AEEVT            EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA
+AT91C_TC_AEEVT_NONE       EQU (0x0 << 20) ;- (TC) Effect: none
+AT91C_TC_AEEVT_SET        EQU (0x1 << 20) ;- (TC) Effect: set
+AT91C_TC_AEEVT_CLEAR      EQU (0x2 << 20) ;- (TC) Effect: clear
+AT91C_TC_AEEVT_TOGGLE     EQU (0x3 << 20) ;- (TC) Effect: toggle
+AT91C_TC_ASWTRG           EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA
+AT91C_TC_ASWTRG_NONE      EQU (0x0 << 22) ;- (TC) Effect: none
+AT91C_TC_ASWTRG_SET       EQU (0x1 << 22) ;- (TC) Effect: set
+AT91C_TC_ASWTRG_CLEAR     EQU (0x2 << 22) ;- (TC) Effect: clear
+AT91C_TC_ASWTRG_TOGGLE    EQU (0x3 << 22) ;- (TC) Effect: toggle
+AT91C_TC_BCPB             EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB
+AT91C_TC_BCPB_NONE        EQU (0x0 << 24) ;- (TC) Effect: none
+AT91C_TC_BCPB_SET         EQU (0x1 << 24) ;- (TC) Effect: set
+AT91C_TC_BCPB_CLEAR       EQU (0x2 << 24) ;- (TC) Effect: clear
+AT91C_TC_BCPB_TOGGLE      EQU (0x3 << 24) ;- (TC) Effect: toggle
+AT91C_TC_BCPC             EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB
+AT91C_TC_BCPC_NONE        EQU (0x0 << 26) ;- (TC) Effect: none
+AT91C_TC_BCPC_SET         EQU (0x1 << 26) ;- (TC) Effect: set
+AT91C_TC_BCPC_CLEAR       EQU (0x2 << 26) ;- (TC) Effect: clear
+AT91C_TC_BCPC_TOGGLE      EQU (0x3 << 26) ;- (TC) Effect: toggle
+AT91C_TC_BEEVT            EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB
+AT91C_TC_BEEVT_NONE       EQU (0x0 << 28) ;- (TC) Effect: none
+AT91C_TC_BEEVT_SET        EQU (0x1 << 28) ;- (TC) Effect: set
+AT91C_TC_BEEVT_CLEAR      EQU (0x2 << 28) ;- (TC) Effect: clear
+AT91C_TC_BEEVT_TOGGLE     EQU (0x3 << 28) ;- (TC) Effect: toggle
+AT91C_TC_BSWTRG           EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB
+AT91C_TC_BSWTRG_NONE      EQU (0x0 << 30) ;- (TC) Effect: none
+AT91C_TC_BSWTRG_SET       EQU (0x1 << 30) ;- (TC) Effect: set
+AT91C_TC_BSWTRG_CLEAR     EQU (0x2 << 30) ;- (TC) Effect: clear
+AT91C_TC_BSWTRG_TOGGLE    EQU (0x3 << 30) ;- (TC) Effect: toggle
+// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+AT91C_TC_COVFS            EQU (0x1 <<  0) ;- (TC) Counter Overflow
+AT91C_TC_LOVRS            EQU (0x1 <<  1) ;- (TC) Load Overrun
+AT91C_TC_CPAS             EQU (0x1 <<  2) ;- (TC) RA Compare
+AT91C_TC_CPBS             EQU (0x1 <<  3) ;- (TC) RB Compare
+AT91C_TC_CPCS             EQU (0x1 <<  4) ;- (TC) RC Compare
+AT91C_TC_LDRAS            EQU (0x1 <<  5) ;- (TC) RA Loading
+AT91C_TC_LDRBS            EQU (0x1 <<  6) ;- (TC) RB Loading
+AT91C_TC_ETRGS            EQU (0x1 <<  7) ;- (TC) External Trigger
+AT91C_TC_CLKSTA           EQU (0x1 << 16) ;- (TC) Clock Enabling
+AT91C_TC_MTIOA            EQU (0x1 << 17) ;- (TC) TIOA Mirror
+AT91C_TC_MTIOB            EQU (0x1 << 18) ;- (TC) TIOA Mirror
+// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// - *****************************************************************************
+// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+AT91C_TCB_SYNC            EQU (0x1 <<  0) ;- (TCB) Synchro Command
+// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+AT91C_TCB_TC0XC0S         EQU (0x3 <<  0) ;- (TCB) External Clock Signal 0 Selection
+AT91C_TCB_TC0XC0S_TCLK0   EQU (0x0) ;- (TCB) TCLK0 connected to XC0
+AT91C_TCB_TC0XC0S_NONE    EQU (0x1) ;- (TCB) None signal connected to XC0
+AT91C_TCB_TC0XC0S_TIOA1   EQU (0x2) ;- (TCB) TIOA1 connected to XC0
+AT91C_TCB_TC0XC0S_TIOA2   EQU (0x3) ;- (TCB) TIOA2 connected to XC0
+AT91C_TCB_TC1XC1S         EQU (0x3 <<  2) ;- (TCB) External Clock Signal 1 Selection
+AT91C_TCB_TC1XC1S_TCLK1   EQU (0x0 <<  2) ;- (TCB) TCLK1 connected to XC1
+AT91C_TCB_TC1XC1S_NONE    EQU (0x1 <<  2) ;- (TCB) None signal connected to XC1
+AT91C_TCB_TC1XC1S_TIOA0   EQU (0x2 <<  2) ;- (TCB) TIOA0 connected to XC1
+AT91C_TCB_TC1XC1S_TIOA2   EQU (0x3 <<  2) ;- (TCB) TIOA2 connected to XC1
+AT91C_TCB_TC2XC2S         EQU (0x3 <<  4) ;- (TCB) External Clock Signal 2 Selection
+AT91C_TCB_TC2XC2S_TCLK2   EQU (0x0 <<  4) ;- (TCB) TCLK2 connected to XC2
+AT91C_TCB_TC2XC2S_NONE    EQU (0x1 <<  4) ;- (TCB) None signal connected to XC2
+AT91C_TCB_TC2XC2S_TIOA0   EQU (0x2 <<  4) ;- (TCB) TIOA0 connected to XC2
+AT91C_TCB_TC2XC2S_TIOA1   EQU (0x3 <<  4) ;- (TCB) TIOA2 connected to XC2
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
+// - *****************************************************************************
+// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
+AT91C_CAN_MTIMEMARK       EQU (0xFFFF <<  0) ;- (CAN_MB) Mailbox Timemark
+AT91C_CAN_PRIOR           EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority
+AT91C_CAN_MOT             EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type
+AT91C_CAN_MOT_DIS         EQU (0x0 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_RX          EQU (0x1 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_TX          EQU (0x3 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_CONSUMER    EQU (0x4 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_PRODUCER    EQU (0x5 << 24) ;- (CAN_MB) 
+// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
+AT91C_CAN_MIDvB           EQU (0x3FFFF <<  0) ;- (CAN_MB) Complementary bits for identifier in extended mode
+AT91C_CAN_MIDvA           EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode
+AT91C_CAN_MIDE            EQU (0x1 << 29) ;- (CAN_MB) Identifier Version
+// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
+// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
+// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
+AT91C_CAN_MTIMESTAMP      EQU (0xFFFF <<  0) ;- (CAN_MB) Timer Value
+AT91C_CAN_MDLC            EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code
+AT91C_CAN_MRTR            EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request
+AT91C_CAN_MABT            EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort
+AT91C_CAN_MRDY            EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready
+AT91C_CAN_MMI             EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored
+// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
+// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
+// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
+AT91C_CAN_MACR            EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox
+AT91C_CAN_MTCR            EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Control Area Network Interface
+// - *****************************************************************************
+// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
+AT91C_CAN_CANEN           EQU (0x1 <<  0) ;- (CAN) CAN Controller Enable
+AT91C_CAN_LPM             EQU (0x1 <<  1) ;- (CAN) Disable/Enable Low Power Mode
+AT91C_CAN_ABM             EQU (0x1 <<  2) ;- (CAN) Disable/Enable Autobaud/Listen Mode
+AT91C_CAN_OVL             EQU (0x1 <<  3) ;- (CAN) Disable/Enable Overload Frame
+AT91C_CAN_TEOF            EQU (0x1 <<  4) ;- (CAN) Time Stamp messages at each end of Frame
+AT91C_CAN_TTM             EQU (0x1 <<  5) ;- (CAN) Disable/Enable Time Trigger Mode
+AT91C_CAN_TIMFRZ          EQU (0x1 <<  6) ;- (CAN) Enable Timer Freeze
+AT91C_CAN_DRPT            EQU (0x1 <<  7) ;- (CAN) Disable Repeat
+// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
+AT91C_CAN_MB0             EQU (0x1 <<  0) ;- (CAN) Mailbox 0 Flag
+AT91C_CAN_MB1             EQU (0x1 <<  1) ;- (CAN) Mailbox 1 Flag
+AT91C_CAN_MB2             EQU (0x1 <<  2) ;- (CAN) Mailbox 2 Flag
+AT91C_CAN_MB3             EQU (0x1 <<  3) ;- (CAN) Mailbox 3 Flag
+AT91C_CAN_MB4             EQU (0x1 <<  4) ;- (CAN) Mailbox 4 Flag
+AT91C_CAN_MB5             EQU (0x1 <<  5) ;- (CAN) Mailbox 5 Flag
+AT91C_CAN_MB6             EQU (0x1 <<  6) ;- (CAN) Mailbox 6 Flag
+AT91C_CAN_MB7             EQU (0x1 <<  7) ;- (CAN) Mailbox 7 Flag
+AT91C_CAN_MB8             EQU (0x1 <<  8) ;- (CAN) Mailbox 8 Flag
+AT91C_CAN_MB9             EQU (0x1 <<  9) ;- (CAN) Mailbox 9 Flag
+AT91C_CAN_MB10            EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag
+AT91C_CAN_MB11            EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag
+AT91C_CAN_MB12            EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag
+AT91C_CAN_MB13            EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag
+AT91C_CAN_MB14            EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag
+AT91C_CAN_MB15            EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag
+AT91C_CAN_ERRA            EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag
+AT91C_CAN_WARN            EQU (0x1 << 17) ;- (CAN) Warning Limit Flag
+AT91C_CAN_ERRP            EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag
+AT91C_CAN_BOFF            EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag
+AT91C_CAN_SLEEP           EQU (0x1 << 20) ;- (CAN) Sleep Flag
+AT91C_CAN_WAKEUP          EQU (0x1 << 21) ;- (CAN) Wakeup Flag
+AT91C_CAN_TOVF            EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag
+AT91C_CAN_TSTP            EQU (0x1 << 23) ;- (CAN) Timestamp Flag
+AT91C_CAN_CERR            EQU (0x1 << 24) ;- (CAN) CRC Error
+AT91C_CAN_SERR            EQU (0x1 << 25) ;- (CAN) Stuffing Error
+AT91C_CAN_AERR            EQU (0x1 << 26) ;- (CAN) Acknowledgment Error
+AT91C_CAN_FERR            EQU (0x1 << 27) ;- (CAN) Form Error
+AT91C_CAN_BERR            EQU (0x1 << 28) ;- (CAN) Bit Error
+// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
+// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
+// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
+AT91C_CAN_RBSY            EQU (0x1 << 29) ;- (CAN) Receiver Busy
+AT91C_CAN_TBSY            EQU (0x1 << 30) ;- (CAN) Transmitter Busy
+AT91C_CAN_OVLY            EQU (0x1 << 31) ;- (CAN) Overload Busy
+// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
+AT91C_CAN_PHASE2          EQU (0x7 <<  0) ;- (CAN) Phase 2 segment
+AT91C_CAN_PHASE1          EQU (0x7 <<  4) ;- (CAN) Phase 1 segment
+AT91C_CAN_PROPAG          EQU (0x7 <<  8) ;- (CAN) Programmation time segment
+AT91C_CAN_SYNC            EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment
+AT91C_CAN_BRP             EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler
+AT91C_CAN_SMP             EQU (0x1 << 24) ;- (CAN) Sampling mode
+// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
+AT91C_CAN_TIMER           EQU (0xFFFF <<  0) ;- (CAN) Timer field
+// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
+// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
+AT91C_CAN_REC             EQU (0xFF <<  0) ;- (CAN) Receive Error Counter
+AT91C_CAN_TEC             EQU (0xFF << 16) ;- (CAN) Transmit Error Counter
+// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
+AT91C_CAN_TIMRST          EQU (0x1 << 31) ;- (CAN) Timer Reset Field
+// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// - *****************************************************************************
+// - -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+AT91C_EMAC_LB             EQU (0x1 <<  0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+AT91C_EMAC_LLB            EQU (0x1 <<  1) ;- (EMAC) Loopback local. 
+AT91C_EMAC_RE             EQU (0x1 <<  2) ;- (EMAC) Receive enable. 
+AT91C_EMAC_TE             EQU (0x1 <<  3) ;- (EMAC) Transmit enable. 
+AT91C_EMAC_MPE            EQU (0x1 <<  4) ;- (EMAC) Management port enable. 
+AT91C_EMAC_CLRSTAT        EQU (0x1 <<  5) ;- (EMAC) Clear statistics registers. 
+AT91C_EMAC_INCSTAT        EQU (0x1 <<  6) ;- (EMAC) Increment statistics registers. 
+AT91C_EMAC_WESTAT         EQU (0x1 <<  7) ;- (EMAC) Write enable for statistics registers. 
+AT91C_EMAC_BP             EQU (0x1 <<  8) ;- (EMAC) Back pressure. 
+AT91C_EMAC_TSTART         EQU (0x1 <<  9) ;- (EMAC) Start Transmission. 
+AT91C_EMAC_THALT          EQU (0x1 << 10) ;- (EMAC) Transmission Halt. 
+AT91C_EMAC_TPFR           EQU (0x1 << 11) ;- (EMAC) Transmit pause frame 
+AT91C_EMAC_TZQ            EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame
+// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+AT91C_EMAC_SPD            EQU (0x1 <<  0) ;- (EMAC) Speed. 
+AT91C_EMAC_FD             EQU (0x1 <<  1) ;- (EMAC) Full duplex. 
+AT91C_EMAC_JFRAME         EQU (0x1 <<  3) ;- (EMAC) Jumbo Frames. 
+AT91C_EMAC_CAF            EQU (0x1 <<  4) ;- (EMAC) Copy all frames. 
+AT91C_EMAC_NBC            EQU (0x1 <<  5) ;- (EMAC) No broadcast. 
+AT91C_EMAC_MTI            EQU (0x1 <<  6) ;- (EMAC) Multicast hash event enable
+AT91C_EMAC_UNI            EQU (0x1 <<  7) ;- (EMAC) Unicast hash enable. 
+AT91C_EMAC_BIG            EQU (0x1 <<  8) ;- (EMAC) Receive 1522 bytes. 
+AT91C_EMAC_EAE            EQU (0x1 <<  9) ;- (EMAC) External address match enable. 
+AT91C_EMAC_CLK            EQU (0x3 << 10) ;- (EMAC) 
+AT91C_EMAC_CLK_HCLK_8     EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8
+AT91C_EMAC_CLK_HCLK_16    EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16
+AT91C_EMAC_CLK_HCLK_32    EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32
+AT91C_EMAC_CLK_HCLK_64    EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64
+AT91C_EMAC_RTY            EQU (0x1 << 12) ;- (EMAC) 
+AT91C_EMAC_PAE            EQU (0x1 << 13) ;- (EMAC) 
+AT91C_EMAC_RBOF           EQU (0x3 << 14) ;- (EMAC) 
+AT91C_EMAC_RBOF_OFFSET_0  EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_1  EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_2  EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_3  EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer
+AT91C_EMAC_RLCE           EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable
+AT91C_EMAC_DRFCS          EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS
+AT91C_EMAC_EFRHD          EQU (0x1 << 18) ;- (EMAC) 
+AT91C_EMAC_IRXFCS         EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS
+// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+AT91C_EMAC_LINKR          EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_MDIO           EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_IDLE           EQU (0x1 <<  2) ;- (EMAC) 
+// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+AT91C_EMAC_UBR            EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_COL            EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_RLES           EQU (0x1 <<  2) ;- (EMAC) 
+AT91C_EMAC_TGO            EQU (0x1 <<  3) ;- (EMAC) Transmit Go
+AT91C_EMAC_BEX            EQU (0x1 <<  4) ;- (EMAC) Buffers exhausted mid frame
+AT91C_EMAC_COMP           EQU (0x1 <<  5) ;- (EMAC) 
+AT91C_EMAC_UND            EQU (0x1 <<  6) ;- (EMAC) 
+// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+AT91C_EMAC_BNA            EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_REC            EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_OVR            EQU (0x1 <<  2) ;- (EMAC) 
+// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+AT91C_EMAC_MFD            EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_RCOMP          EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_RXUBR          EQU (0x1 <<  2) ;- (EMAC) 
+AT91C_EMAC_TXUBR          EQU (0x1 <<  3) ;- (EMAC) 
+AT91C_EMAC_TUNDR          EQU (0x1 <<  4) ;- (EMAC) 
+AT91C_EMAC_RLEX           EQU (0x1 <<  5) ;- (EMAC) 
+AT91C_EMAC_TXERR          EQU (0x1 <<  6) ;- (EMAC) 
+AT91C_EMAC_TCOMP          EQU (0x1 <<  7) ;- (EMAC) 
+AT91C_EMAC_LINK           EQU (0x1 <<  9) ;- (EMAC) 
+AT91C_EMAC_ROVR           EQU (0x1 << 10) ;- (EMAC) 
+AT91C_EMAC_HRESP          EQU (0x1 << 11) ;- (EMAC) 
+AT91C_EMAC_PFRE           EQU (0x1 << 12) ;- (EMAC) 
+AT91C_EMAC_PTZ            EQU (0x1 << 13) ;- (EMAC) 
+// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+AT91C_EMAC_DATA           EQU (0xFFFF <<  0) ;- (EMAC) 
+AT91C_EMAC_CODE           EQU (0x3 << 16) ;- (EMAC) 
+AT91C_EMAC_REGA           EQU (0x1F << 18) ;- (EMAC) 
+AT91C_EMAC_PHYA           EQU (0x1F << 23) ;- (EMAC) 
+AT91C_EMAC_RW             EQU (0x3 << 28) ;- (EMAC) 
+AT91C_EMAC_SOF            EQU (0x3 << 30) ;- (EMAC) 
+// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+AT91C_EMAC_RMII           EQU (0x1 <<  0) ;- (EMAC) Reduce MII
+// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+AT91C_EMAC_IP             EQU (0xFFFF <<  0) ;- (EMAC) ARP request IP address
+AT91C_EMAC_MAG            EQU (0x1 << 16) ;- (EMAC) Magic packet event enable
+AT91C_EMAC_ARP            EQU (0x1 << 17) ;- (EMAC) ARP request event enable
+AT91C_EMAC_SA1            EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable
+// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+AT91C_EMAC_REVREF         EQU (0xFFFF <<  0) ;- (EMAC) 
+AT91C_EMAC_PARTREF        EQU (0xFFFF << 16) ;- (EMAC) 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// - *****************************************************************************
+// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+AT91C_ADC_SWRST           EQU (0x1 <<  0) ;- (ADC) Software Reset
+AT91C_ADC_START           EQU (0x1 <<  1) ;- (ADC) Start Conversion
+// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+AT91C_ADC_TRGEN           EQU (0x1 <<  0) ;- (ADC) Trigger Enable
+AT91C_ADC_TRGEN_DIS       EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+AT91C_ADC_TRGEN_EN        EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled.
+AT91C_ADC_TRGSEL          EQU (0x7 <<  1) ;- (ADC) Trigger Selection
+AT91C_ADC_TRGSEL_TIOA0    EQU (0x0 <<  1) ;- (ADC) Selected TRGSEL = TIAO0
+AT91C_ADC_TRGSEL_TIOA1    EQU (0x1 <<  1) ;- (ADC) Selected TRGSEL = TIAO1
+AT91C_ADC_TRGSEL_TIOA2    EQU (0x2 <<  1) ;- (ADC) Selected TRGSEL = TIAO2
+AT91C_ADC_TRGSEL_TIOA3    EQU (0x3 <<  1) ;- (ADC) Selected TRGSEL = TIAO3
+AT91C_ADC_TRGSEL_TIOA4    EQU (0x4 <<  1) ;- (ADC) Selected TRGSEL = TIAO4
+AT91C_ADC_TRGSEL_TIOA5    EQU (0x5 <<  1) ;- (ADC) Selected TRGSEL = TIAO5
+AT91C_ADC_TRGSEL_EXT      EQU (0x6 <<  1) ;- (ADC) Selected TRGSEL = External Trigger
+AT91C_ADC_LOWRES          EQU (0x1 <<  4) ;- (ADC) Resolution.
+AT91C_ADC_LOWRES_10_BIT   EQU (0x0 <<  4) ;- (ADC) 10-bit resolution
+AT91C_ADC_LOWRES_8_BIT    EQU (0x1 <<  4) ;- (ADC) 8-bit resolution
+AT91C_ADC_SLEEP           EQU (0x1 <<  5) ;- (ADC) Sleep Mode
+AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 <<  5) ;- (ADC) Normal Mode
+AT91C_ADC_SLEEP_MODE      EQU (0x1 <<  5) ;- (ADC) Sleep Mode
+AT91C_ADC_PRESCAL         EQU (0x3F <<  8) ;- (ADC) Prescaler rate selection
+AT91C_ADC_STARTUP         EQU (0x1F << 16) ;- (ADC) Startup Time
+AT91C_ADC_SHTIM           EQU (0xF << 24) ;- (ADC) Sample & Hold Time
+// - -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+AT91C_ADC_CH0             EQU (0x1 <<  0) ;- (ADC) Channel 0
+AT91C_ADC_CH1             EQU (0x1 <<  1) ;- (ADC) Channel 1
+AT91C_ADC_CH2             EQU (0x1 <<  2) ;- (ADC) Channel 2
+AT91C_ADC_CH3             EQU (0x1 <<  3) ;- (ADC) Channel 3
+AT91C_ADC_CH4             EQU (0x1 <<  4) ;- (ADC) Channel 4
+AT91C_ADC_CH5             EQU (0x1 <<  5) ;- (ADC) Channel 5
+AT91C_ADC_CH6             EQU (0x1 <<  6) ;- (ADC) Channel 6
+AT91C_ADC_CH7             EQU (0x1 <<  7) ;- (ADC) Channel 7
+// - -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// - -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+AT91C_ADC_EOC0            EQU (0x1 <<  0) ;- (ADC) End of Conversion
+AT91C_ADC_EOC1            EQU (0x1 <<  1) ;- (ADC) End of Conversion
+AT91C_ADC_EOC2            EQU (0x1 <<  2) ;- (ADC) End of Conversion
+AT91C_ADC_EOC3            EQU (0x1 <<  3) ;- (ADC) End of Conversion
+AT91C_ADC_EOC4            EQU (0x1 <<  4) ;- (ADC) End of Conversion
+AT91C_ADC_EOC5            EQU (0x1 <<  5) ;- (ADC) End of Conversion
+AT91C_ADC_EOC6            EQU (0x1 <<  6) ;- (ADC) End of Conversion
+AT91C_ADC_EOC7            EQU (0x1 <<  7) ;- (ADC) End of Conversion
+AT91C_ADC_OVRE0           EQU (0x1 <<  8) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE1           EQU (0x1 <<  9) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE2           EQU (0x1 << 10) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE3           EQU (0x1 << 11) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE4           EQU (0x1 << 12) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE5           EQU (0x1 << 13) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE6           EQU (0x1 << 14) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE7           EQU (0x1 << 15) ;- (ADC) Overrun Error
+AT91C_ADC_DRDY            EQU (0x1 << 16) ;- (ADC) Data Ready
+AT91C_ADC_GOVRE           EQU (0x1 << 17) ;- (ADC) General Overrun
+AT91C_ADC_ENDRX           EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer
+AT91C_ADC_RXBUFF          EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt
+// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+AT91C_ADC_LDATA           EQU (0x3FF <<  0) ;- (ADC) Last Data Converted
+// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+AT91C_ADC_DATA            EQU (0x3FF <<  0) ;- (ADC) Converted Data
+// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
+// - *****************************************************************************
+// - -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
+AT91C_AES_START           EQU (0x1 <<  0) ;- (AES) Starts Processing
+AT91C_AES_SWRST           EQU (0x1 <<  8) ;- (AES) Software Reset
+AT91C_AES_LOADSEED        EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading
+// - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
+AT91C_AES_CIPHER          EQU (0x1 <<  0) ;- (AES) Processing Mode
+AT91C_AES_PROCDLY         EQU (0xF <<  4) ;- (AES) Processing Delay
+AT91C_AES_SMOD            EQU (0x3 <<  8) ;- (AES) Start Mode
+AT91C_AES_SMOD_MANUAL     EQU (0x0 <<  8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+AT91C_AES_SMOD_AUTO       EQU (0x1 <<  8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+AT91C_AES_SMOD_PDC        EQU (0x2 <<  8) ;- (AES) PDC Mode (cf datasheet).
+AT91C_AES_OPMOD           EQU (0x7 << 12) ;- (AES) Operation Mode
+AT91C_AES_OPMOD_ECB       EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode.
+AT91C_AES_OPMOD_CBC       EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode.
+AT91C_AES_OPMOD_OFB       EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode.
+AT91C_AES_OPMOD_CFB       EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode.
+AT91C_AES_OPMOD_CTR       EQU (0x4 << 12) ;- (AES) CTR Counter mode.
+AT91C_AES_LOD             EQU (0x1 << 15) ;- (AES) Last Output Data Mode
+AT91C_AES_CFBS            EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size
+AT91C_AES_CFBS_128_BIT    EQU (0x0 << 16) ;- (AES) 128-bit.
+AT91C_AES_CFBS_64_BIT     EQU (0x1 << 16) ;- (AES) 64-bit.
+AT91C_AES_CFBS_32_BIT     EQU (0x2 << 16) ;- (AES) 32-bit.
+AT91C_AES_CFBS_16_BIT     EQU (0x3 << 16) ;- (AES) 16-bit.
+AT91C_AES_CFBS_8_BIT      EQU (0x4 << 16) ;- (AES) 8-bit.
+AT91C_AES_CKEY            EQU (0xF << 20) ;- (AES) Countermeasure Key
+AT91C_AES_CTYPE           EQU (0x1F << 24) ;- (AES) Countermeasure Type
+AT91C_AES_CTYPE_TYPE1_EN  EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled.
+AT91C_AES_CTYPE_TYPE2_EN  EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled.
+AT91C_AES_CTYPE_TYPE3_EN  EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled.
+AT91C_AES_CTYPE_TYPE4_EN  EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled.
+AT91C_AES_CTYPE_TYPE5_EN  EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled.
+// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
+AT91C_AES_DATRDY          EQU (0x1 <<  0) ;- (AES) DATRDY
+AT91C_AES_ENDRX           EQU (0x1 <<  1) ;- (AES) PDC Read Buffer End
+AT91C_AES_ENDTX           EQU (0x1 <<  2) ;- (AES) PDC Write Buffer End
+AT91C_AES_RXBUFF          EQU (0x1 <<  3) ;- (AES) PDC Read Buffer Full
+AT91C_AES_TXBUFE          EQU (0x1 <<  4) ;- (AES) PDC Write Buffer Empty
+AT91C_AES_URAD            EQU (0x1 <<  8) ;- (AES) Unspecified Register Access Detection
+// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
+// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
+// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
+AT91C_AES_URAT            EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status
+AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode.
+AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing.
+AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing.
+AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation.
+AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation.
+AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access.
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
+// - *****************************************************************************
+// - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
+AT91C_TDES_START          EQU (0x1 <<  0) ;- (TDES) Starts Processing
+AT91C_TDES_SWRST          EQU (0x1 <<  8) ;- (TDES) Software Reset
+// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
+AT91C_TDES_CIPHER         EQU (0x1 <<  0) ;- (TDES) Processing Mode
+AT91C_TDES_TDESMOD        EQU (0x1 <<  1) ;- (TDES) Single or Triple DES Mode
+AT91C_TDES_KEYMOD         EQU (0x1 <<  4) ;- (TDES) Key Mode
+AT91C_TDES_SMOD           EQU (0x3 <<  8) ;- (TDES) Start Mode
+AT91C_TDES_SMOD_MANUAL    EQU (0x0 <<  8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+AT91C_TDES_SMOD_AUTO      EQU (0x1 <<  8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+AT91C_TDES_SMOD_PDC       EQU (0x2 <<  8) ;- (TDES) PDC Mode (cf datasheet).
+AT91C_TDES_OPMOD          EQU (0x3 << 12) ;- (TDES) Operation Mode
+AT91C_TDES_OPMOD_ECB      EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode.
+AT91C_TDES_OPMOD_CBC      EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode.
+AT91C_TDES_OPMOD_OFB      EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode.
+AT91C_TDES_OPMOD_CFB      EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode.
+AT91C_TDES_LOD            EQU (0x1 << 15) ;- (TDES) Last Output Data Mode
+AT91C_TDES_CFBS           EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size
+AT91C_TDES_CFBS_64_BIT    EQU (0x0 << 16) ;- (TDES) 64-bit.
+AT91C_TDES_CFBS_32_BIT    EQU (0x1 << 16) ;- (TDES) 32-bit.
+AT91C_TDES_CFBS_16_BIT    EQU (0x2 << 16) ;- (TDES) 16-bit.
+AT91C_TDES_CFBS_8_BIT     EQU (0x3 << 16) ;- (TDES) 8-bit.
+// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
+AT91C_TDES_DATRDY         EQU (0x1 <<  0) ;- (TDES) DATRDY
+AT91C_TDES_ENDRX          EQU (0x1 <<  1) ;- (TDES) PDC Read Buffer End
+AT91C_TDES_ENDTX          EQU (0x1 <<  2) ;- (TDES) PDC Write Buffer End
+AT91C_TDES_RXBUFF         EQU (0x1 <<  3) ;- (TDES) PDC Read Buffer Full
+AT91C_TDES_TXBUFE         EQU (0x1 <<  4) ;- (TDES) PDC Write Buffer Empty
+AT91C_TDES_URAD           EQU (0x1 <<  8) ;- (TDES) Unspecified Register Access Detection
+// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
+// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
+// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
+AT91C_TDES_URAT           EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status
+AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode.
+AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing.
+AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing.
+AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access.
+
+// - *****************************************************************************
+// -               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
+// - *****************************************************************************
+// - ========== Register definition for SYS peripheral ========== 
+// - ========== Register definition for AIC peripheral ========== 
+AT91C_AIC_IVR             EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register
+AT91C_AIC_SMR             EQU (0xFFFFF000) ;- (AIC) Source Mode Register
+AT91C_AIC_FVR             EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register
+AT91C_AIC_DCR             EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect)
+AT91C_AIC_EOICR           EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register
+AT91C_AIC_SVR             EQU (0xFFFFF080) ;- (AIC) Source Vector Register
+AT91C_AIC_FFSR            EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register
+AT91C_AIC_ICCR            EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register
+AT91C_AIC_ISR             EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register
+AT91C_AIC_IMR             EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register
+AT91C_AIC_IPR             EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register
+AT91C_AIC_FFER            EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register
+AT91C_AIC_IECR            EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register
+AT91C_AIC_ISCR            EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register
+AT91C_AIC_FFDR            EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register
+AT91C_AIC_CISR            EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register
+AT91C_AIC_IDCR            EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register
+AT91C_AIC_SPU             EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register
+// - ========== Register definition for PDC_DBGU peripheral ========== 
+AT91C_DBGU_TCR            EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register
+AT91C_DBGU_RNPR           EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register
+AT91C_DBGU_TNPR           EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register
+AT91C_DBGU_TPR            EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register
+AT91C_DBGU_RPR            EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register
+AT91C_DBGU_RCR            EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register
+AT91C_DBGU_RNCR           EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register
+AT91C_DBGU_PTCR           EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register
+AT91C_DBGU_PTSR           EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register
+AT91C_DBGU_TNCR           EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register
+// - ========== Register definition for DBGU peripheral ========== 
+AT91C_DBGU_EXID           EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register
+AT91C_DBGU_BRGR           EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register
+AT91C_DBGU_IDR            EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register
+AT91C_DBGU_CSR            EQU (0xFFFFF214) ;- (DBGU) Channel Status Register
+AT91C_DBGU_CIDR           EQU (0xFFFFF240) ;- (DBGU) Chip ID Register
+AT91C_DBGU_MR             EQU (0xFFFFF204) ;- (DBGU) Mode Register
+AT91C_DBGU_IMR            EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register
+AT91C_DBGU_CR             EQU (0xFFFFF200) ;- (DBGU) Control Register
+AT91C_DBGU_FNTR           EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register
+AT91C_DBGU_THR            EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register
+AT91C_DBGU_RHR            EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register
+AT91C_DBGU_IER            EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register
+// - ========== Register definition for PIOA peripheral ========== 
+AT91C_PIOA_ODR            EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr
+AT91C_PIOA_SODR           EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register
+AT91C_PIOA_ISR            EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register
+AT91C_PIOA_ABSR           EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register
+AT91C_PIOA_IER            EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register
+AT91C_PIOA_PPUDR          EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register
+AT91C_PIOA_IMR            EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register
+AT91C_PIOA_PER            EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register
+AT91C_PIOA_IFDR           EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register
+AT91C_PIOA_OWDR           EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register
+AT91C_PIOA_MDSR           EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register
+AT91C_PIOA_IDR            EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register
+AT91C_PIOA_ODSR           EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register
+AT91C_PIOA_PPUSR          EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register
+AT91C_PIOA_OWSR           EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register
+AT91C_PIOA_BSR            EQU (0xFFFFF474) ;- (PIOA) Select B Register
+AT91C_PIOA_OWER           EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register
+AT91C_PIOA_IFER           EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register
+AT91C_PIOA_PDSR           EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register
+AT91C_PIOA_PPUER          EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register
+AT91C_PIOA_OSR            EQU (0xFFFFF418) ;- (PIOA) Output Status Register
+AT91C_PIOA_ASR            EQU (0xFFFFF470) ;- (PIOA) Select A Register
+AT91C_PIOA_MDDR           EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register
+AT91C_PIOA_CODR           EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register
+AT91C_PIOA_MDER           EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register
+AT91C_PIOA_PDR            EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register
+AT91C_PIOA_IFSR           EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register
+AT91C_PIOA_OER            EQU (0xFFFFF410) ;- (PIOA) Output Enable Register
+AT91C_PIOA_PSR            EQU (0xFFFFF408) ;- (PIOA) PIO Status Register
+// - ========== Register definition for PIOB peripheral ========== 
+AT91C_PIOB_OWDR           EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register
+AT91C_PIOB_MDER           EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register
+AT91C_PIOB_PPUSR          EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register
+AT91C_PIOB_IMR            EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register
+AT91C_PIOB_ASR            EQU (0xFFFFF670) ;- (PIOB) Select A Register
+AT91C_PIOB_PPUDR          EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register
+AT91C_PIOB_PSR            EQU (0xFFFFF608) ;- (PIOB) PIO Status Register
+AT91C_PIOB_IER            EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register
+AT91C_PIOB_CODR           EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register
+AT91C_PIOB_OWER           EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register
+AT91C_PIOB_ABSR           EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register
+AT91C_PIOB_IFDR           EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register
+AT91C_PIOB_PDSR           EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register
+AT91C_PIOB_IDR            EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register
+AT91C_PIOB_OWSR           EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register
+AT91C_PIOB_PDR            EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register
+AT91C_PIOB_ODR            EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr
+AT91C_PIOB_IFSR           EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register
+AT91C_PIOB_PPUER          EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register
+AT91C_PIOB_SODR           EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register
+AT91C_PIOB_ISR            EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register
+AT91C_PIOB_ODSR           EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register
+AT91C_PIOB_OSR            EQU (0xFFFFF618) ;- (PIOB) Output Status Register
+AT91C_PIOB_MDSR           EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register
+AT91C_PIOB_IFER           EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register
+AT91C_PIOB_BSR            EQU (0xFFFFF674) ;- (PIOB) Select B Register
+AT91C_PIOB_MDDR           EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register
+AT91C_PIOB_OER            EQU (0xFFFFF610) ;- (PIOB) Output Enable Register
+AT91C_PIOB_PER            EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register
+// - ========== Register definition for CKGR peripheral ========== 
+AT91C_CKGR_MOR            EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register
+AT91C_CKGR_PLLR           EQU (0xFFFFFC2C) ;- (CKGR) PLL Register
+AT91C_CKGR_MCFR           EQU (0xFFFFFC24) ;- (CKGR) Main Clock  Frequency Register
+// - ========== Register definition for PMC peripheral ========== 
+AT91C_PMC_IDR             EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register
+AT91C_PMC_MOR             EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register
+AT91C_PMC_PLLR            EQU (0xFFFFFC2C) ;- (PMC) PLL Register
+AT91C_PMC_PCER            EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register
+AT91C_PMC_PCKR            EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register
+AT91C_PMC_MCKR            EQU (0xFFFFFC30) ;- (PMC) Master Clock Register
+AT91C_PMC_SCDR            EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register
+AT91C_PMC_PCDR            EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register
+AT91C_PMC_SCSR            EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register
+AT91C_PMC_PCSR            EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register
+AT91C_PMC_MCFR            EQU (0xFFFFFC24) ;- (PMC) Main Clock  Frequency Register
+AT91C_PMC_SCER            EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register
+AT91C_PMC_IMR             EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register
+AT91C_PMC_IER             EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register
+AT91C_PMC_SR              EQU (0xFFFFFC68) ;- (PMC) Status Register
+// - ========== Register definition for RSTC peripheral ========== 
+AT91C_RSTC_RCR            EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register
+AT91C_RSTC_RMR            EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register
+AT91C_RSTC_RSR            EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register
+// - ========== Register definition for RTTC peripheral ========== 
+AT91C_RTTC_RTSR           EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register
+AT91C_RTTC_RTMR           EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register
+AT91C_RTTC_RTVR           EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register
+AT91C_RTTC_RTAR           EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register
+// - ========== Register definition for PITC peripheral ========== 
+AT91C_PITC_PIVR           EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register
+AT91C_PITC_PISR           EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register
+AT91C_PITC_PIIR           EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register
+AT91C_PITC_PIMR           EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register
+// - ========== Register definition for WDTC peripheral ========== 
+AT91C_WDTC_WDCR           EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register
+AT91C_WDTC_WDSR           EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register
+AT91C_WDTC_WDMR           EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register
+// - ========== Register definition for VREG peripheral ========== 
+AT91C_VREG_MR             EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register
+// - ========== Register definition for MC peripheral ========== 
+AT91C_MC_ASR              EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register
+AT91C_MC_RCR              EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register
+AT91C_MC_FCR              EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register
+AT91C_MC_AASR             EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register
+AT91C_MC_FSR              EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register
+AT91C_MC_FMR              EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register
+// - ========== Register definition for PDC_SPI1 peripheral ========== 
+AT91C_SPI1_PTCR           EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register
+AT91C_SPI1_RPR            EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register
+AT91C_SPI1_TNCR           EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register
+AT91C_SPI1_TPR            EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register
+AT91C_SPI1_TNPR           EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register
+AT91C_SPI1_TCR            EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register
+AT91C_SPI1_RCR            EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register
+AT91C_SPI1_RNPR           EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register
+AT91C_SPI1_RNCR           EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register
+AT91C_SPI1_PTSR           EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register
+// - ========== Register definition for SPI1 peripheral ========== 
+AT91C_SPI1_IMR            EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register
+AT91C_SPI1_IER            EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register
+AT91C_SPI1_MR             EQU (0xFFFE4004) ;- (SPI1) Mode Register
+AT91C_SPI1_RDR            EQU (0xFFFE4008) ;- (SPI1) Receive Data Register
+AT91C_SPI1_IDR            EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register
+AT91C_SPI1_SR             EQU (0xFFFE4010) ;- (SPI1) Status Register
+AT91C_SPI1_TDR            EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register
+AT91C_SPI1_CR             EQU (0xFFFE4000) ;- (SPI1) Control Register
+AT91C_SPI1_CSR            EQU (0xFFFE4030) ;- (SPI1) Chip Select Register
+// - ========== Register definition for PDC_SPI0 peripheral ========== 
+AT91C_SPI0_PTCR           EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register
+AT91C_SPI0_TPR            EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register
+AT91C_SPI0_TCR            EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register
+AT91C_SPI0_RCR            EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register
+AT91C_SPI0_PTSR           EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register
+AT91C_SPI0_RNPR           EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register
+AT91C_SPI0_RPR            EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register
+AT91C_SPI0_TNCR           EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register
+AT91C_SPI0_RNCR           EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register
+AT91C_SPI0_TNPR           EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register
+// - ========== Register definition for SPI0 peripheral ========== 
+AT91C_SPI0_IER            EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register
+AT91C_SPI0_SR             EQU (0xFFFE0010) ;- (SPI0) Status Register
+AT91C_SPI0_IDR            EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register
+AT91C_SPI0_CR             EQU (0xFFFE0000) ;- (SPI0) Control Register
+AT91C_SPI0_MR             EQU (0xFFFE0004) ;- (SPI0) Mode Register
+AT91C_SPI0_IMR            EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register
+AT91C_SPI0_TDR            EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register
+AT91C_SPI0_RDR            EQU (0xFFFE0008) ;- (SPI0) Receive Data Register
+AT91C_SPI0_CSR            EQU (0xFFFE0030) ;- (SPI0) Chip Select Register
+// - ========== Register definition for PDC_US1 peripheral ========== 
+AT91C_US1_RNCR            EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register
+AT91C_US1_PTCR            EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register
+AT91C_US1_TCR             EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register
+AT91C_US1_PTSR            EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register
+AT91C_US1_TNPR            EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register
+AT91C_US1_RCR             EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register
+AT91C_US1_RNPR            EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register
+AT91C_US1_RPR             EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register
+AT91C_US1_TNCR            EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register
+AT91C_US1_TPR             EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register
+// - ========== Register definition for US1 peripheral ========== 
+AT91C_US1_IF              EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register
+AT91C_US1_NER             EQU (0xFFFC4044) ;- (US1) Nb Errors Register
+AT91C_US1_RTOR            EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register
+AT91C_US1_CSR             EQU (0xFFFC4014) ;- (US1) Channel Status Register
+AT91C_US1_IDR             EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register
+AT91C_US1_IER             EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register
+AT91C_US1_THR             EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register
+AT91C_US1_TTGR            EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register
+AT91C_US1_RHR             EQU (0xFFFC4018) ;- (US1) Receiver Holding Register
+AT91C_US1_BRGR            EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register
+AT91C_US1_IMR             EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register
+AT91C_US1_FIDI            EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register
+AT91C_US1_CR              EQU (0xFFFC4000) ;- (US1) Control Register
+AT91C_US1_MR              EQU (0xFFFC4004) ;- (US1) Mode Register
+// - ========== Register definition for PDC_US0 peripheral ========== 
+AT91C_US0_TNPR            EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register
+AT91C_US0_RNPR            EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register
+AT91C_US0_TCR             EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register
+AT91C_US0_PTCR            EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register
+AT91C_US0_PTSR            EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register
+AT91C_US0_TNCR            EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register
+AT91C_US0_TPR             EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register
+AT91C_US0_RCR             EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register
+AT91C_US0_RPR             EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register
+AT91C_US0_RNCR            EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register
+// - ========== Register definition for US0 peripheral ========== 
+AT91C_US0_BRGR            EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register
+AT91C_US0_NER             EQU (0xFFFC0044) ;- (US0) Nb Errors Register
+AT91C_US0_CR              EQU (0xFFFC0000) ;- (US0) Control Register
+AT91C_US0_IMR             EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register
+AT91C_US0_FIDI            EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register
+AT91C_US0_TTGR            EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register
+AT91C_US0_MR              EQU (0xFFFC0004) ;- (US0) Mode Register
+AT91C_US0_RTOR            EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register
+AT91C_US0_CSR             EQU (0xFFFC0014) ;- (US0) Channel Status Register
+AT91C_US0_RHR             EQU (0xFFFC0018) ;- (US0) Receiver Holding Register
+AT91C_US0_IDR             EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register
+AT91C_US0_THR             EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register
+AT91C_US0_IF              EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register
+AT91C_US0_IER             EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register
+// - ========== Register definition for PDC_SSC peripheral ========== 
+AT91C_SSC_TNCR            EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register
+AT91C_SSC_RPR             EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register
+AT91C_SSC_RNCR            EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register
+AT91C_SSC_TPR             EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register
+AT91C_SSC_PTCR            EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register
+AT91C_SSC_TCR             EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register
+AT91C_SSC_RCR             EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register
+AT91C_SSC_RNPR            EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register
+AT91C_SSC_TNPR            EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register
+AT91C_SSC_PTSR            EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register
+// - ========== Register definition for SSC peripheral ========== 
+AT91C_SSC_RHR             EQU (0xFFFD4020) ;- (SSC) Receive Holding Register
+AT91C_SSC_RSHR            EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register
+AT91C_SSC_TFMR            EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register
+AT91C_SSC_IDR             EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register
+AT91C_SSC_THR             EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register
+AT91C_SSC_RCMR            EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister
+AT91C_SSC_IER             EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register
+AT91C_SSC_TSHR            EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register
+AT91C_SSC_SR              EQU (0xFFFD4040) ;- (SSC) Status Register
+AT91C_SSC_CMR             EQU (0xFFFD4004) ;- (SSC) Clock Mode Register
+AT91C_SSC_TCMR            EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register
+AT91C_SSC_CR              EQU (0xFFFD4000) ;- (SSC) Control Register
+AT91C_SSC_IMR             EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register
+AT91C_SSC_RFMR            EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register
+// - ========== Register definition for TWI peripheral ========== 
+AT91C_TWI_IER             EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register
+AT91C_TWI_CR              EQU (0xFFFB8000) ;- (TWI) Control Register
+AT91C_TWI_SR              EQU (0xFFFB8020) ;- (TWI) Status Register
+AT91C_TWI_IMR             EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register
+AT91C_TWI_THR             EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register
+AT91C_TWI_IDR             EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register
+AT91C_TWI_IADR            EQU (0xFFFB800C) ;- (TWI) Internal Address Register
+AT91C_TWI_MMR             EQU (0xFFFB8004) ;- (TWI) Master Mode Register
+AT91C_TWI_CWGR            EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register
+AT91C_TWI_RHR             EQU (0xFFFB8030) ;- (TWI) Receive Holding Register
+// - ========== Register definition for PWMC_CH3 peripheral ========== 
+AT91C_PWMC_CH3_CUPDR      EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register
+AT91C_PWMC_CH3_Reserved   EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved
+AT91C_PWMC_CH3_CPRDR      EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register
+AT91C_PWMC_CH3_CDTYR      EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register
+AT91C_PWMC_CH3_CCNTR      EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register
+AT91C_PWMC_CH3_CMR        EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register
+// - ========== Register definition for PWMC_CH2 peripheral ========== 
+AT91C_PWMC_CH2_Reserved   EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved
+AT91C_PWMC_CH2_CMR        EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register
+AT91C_PWMC_CH2_CCNTR      EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register
+AT91C_PWMC_CH2_CPRDR      EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register
+AT91C_PWMC_CH2_CUPDR      EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register
+AT91C_PWMC_CH2_CDTYR      EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register
+// - ========== Register definition for PWMC_CH1 peripheral ========== 
+AT91C_PWMC_CH1_Reserved   EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved
+AT91C_PWMC_CH1_CUPDR      EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register
+AT91C_PWMC_CH1_CPRDR      EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register
+AT91C_PWMC_CH1_CCNTR      EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register
+AT91C_PWMC_CH1_CDTYR      EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register
+AT91C_PWMC_CH1_CMR        EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register
+// - ========== Register definition for PWMC_CH0 peripheral ========== 
+AT91C_PWMC_CH0_Reserved   EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved
+AT91C_PWMC_CH0_CPRDR      EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register
+AT91C_PWMC_CH0_CDTYR      EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register
+AT91C_PWMC_CH0_CMR        EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register
+AT91C_PWMC_CH0_CUPDR      EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register
+AT91C_PWMC_CH0_CCNTR      EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register
+// - ========== Register definition for PWMC peripheral ========== 
+AT91C_PWMC_IDR            EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register
+AT91C_PWMC_DIS            EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register
+AT91C_PWMC_IER            EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register
+AT91C_PWMC_VR             EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register
+AT91C_PWMC_ISR            EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register
+AT91C_PWMC_SR             EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register
+AT91C_PWMC_IMR            EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register
+AT91C_PWMC_MR             EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register
+AT91C_PWMC_ENA            EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register
+// - ========== Register definition for UDP peripheral ========== 
+AT91C_UDP_IMR             EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register
+AT91C_UDP_FADDR           EQU (0xFFFB0008) ;- (UDP) Function Address Register
+AT91C_UDP_NUM             EQU (0xFFFB0000) ;- (UDP) Frame Number Register
+AT91C_UDP_FDR             EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register
+AT91C_UDP_ISR             EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register
+AT91C_UDP_CSR             EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register
+AT91C_UDP_IDR             EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register
+AT91C_UDP_ICR             EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register
+AT91C_UDP_RSTEP           EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register
+AT91C_UDP_TXVC            EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register
+AT91C_UDP_GLBSTATE        EQU (0xFFFB0004) ;- (UDP) Global State Register
+AT91C_UDP_IER             EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register
+// - ========== Register definition for TC0 peripheral ========== 
+AT91C_TC0_SR              EQU (0xFFFA0020) ;- (TC0) Status Register
+AT91C_TC0_RC              EQU (0xFFFA001C) ;- (TC0) Register C
+AT91C_TC0_RB              EQU (0xFFFA0018) ;- (TC0) Register B
+AT91C_TC0_CCR             EQU (0xFFFA0000) ;- (TC0) Channel Control Register
+AT91C_TC0_CMR             EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC0_IER             EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register
+AT91C_TC0_RA              EQU (0xFFFA0014) ;- (TC0) Register A
+AT91C_TC0_IDR             EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register
+AT91C_TC0_CV              EQU (0xFFFA0010) ;- (TC0) Counter Value
+AT91C_TC0_IMR             EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register
+// - ========== Register definition for TC1 peripheral ========== 
+AT91C_TC1_RB              EQU (0xFFFA0058) ;- (TC1) Register B
+AT91C_TC1_CCR             EQU (0xFFFA0040) ;- (TC1) Channel Control Register
+AT91C_TC1_IER             EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register
+AT91C_TC1_IDR             EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register
+AT91C_TC1_SR              EQU (0xFFFA0060) ;- (TC1) Status Register
+AT91C_TC1_CMR             EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC1_RA              EQU (0xFFFA0054) ;- (TC1) Register A
+AT91C_TC1_RC              EQU (0xFFFA005C) ;- (TC1) Register C
+AT91C_TC1_IMR             EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register
+AT91C_TC1_CV              EQU (0xFFFA0050) ;- (TC1) Counter Value
+// - ========== Register definition for TC2 peripheral ========== 
+AT91C_TC2_CMR             EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC2_CCR             EQU (0xFFFA0080) ;- (TC2) Channel Control Register
+AT91C_TC2_CV              EQU (0xFFFA0090) ;- (TC2) Counter Value
+AT91C_TC2_RA              EQU (0xFFFA0094) ;- (TC2) Register A
+AT91C_TC2_RB              EQU (0xFFFA0098) ;- (TC2) Register B
+AT91C_TC2_IDR             EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register
+AT91C_TC2_IMR             EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register
+AT91C_TC2_RC              EQU (0xFFFA009C) ;- (TC2) Register C
+AT91C_TC2_IER             EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register
+AT91C_TC2_SR              EQU (0xFFFA00A0) ;- (TC2) Status Register
+// - ========== Register definition for TCB peripheral ========== 
+AT91C_TCB_BMR             EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register
+AT91C_TCB_BCR             EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register
+// - ========== Register definition for CAN_MB0 peripheral ========== 
+AT91C_CAN_MB0_MDL         EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register
+AT91C_CAN_MB0_MAM         EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register
+AT91C_CAN_MB0_MCR         EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register
+AT91C_CAN_MB0_MID         EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register
+AT91C_CAN_MB0_MSR         EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register
+AT91C_CAN_MB0_MFID        EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register
+AT91C_CAN_MB0_MDH         EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register
+AT91C_CAN_MB0_MMR         EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register
+// - ========== Register definition for CAN_MB1 peripheral ========== 
+AT91C_CAN_MB1_MDL         EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register
+AT91C_CAN_MB1_MID         EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register
+AT91C_CAN_MB1_MMR         EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register
+AT91C_CAN_MB1_MSR         EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register
+AT91C_CAN_MB1_MAM         EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register
+AT91C_CAN_MB1_MDH         EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register
+AT91C_CAN_MB1_MCR         EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register
+AT91C_CAN_MB1_MFID        EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register
+// - ========== Register definition for CAN_MB2 peripheral ========== 
+AT91C_CAN_MB2_MCR         EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register
+AT91C_CAN_MB2_MDH         EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register
+AT91C_CAN_MB2_MID         EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register
+AT91C_CAN_MB2_MDL         EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register
+AT91C_CAN_MB2_MMR         EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register
+AT91C_CAN_MB2_MAM         EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register
+AT91C_CAN_MB2_MFID        EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register
+AT91C_CAN_MB2_MSR         EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register
+// - ========== Register definition for CAN_MB3 peripheral ========== 
+AT91C_CAN_MB3_MFID        EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register
+AT91C_CAN_MB3_MAM         EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register
+AT91C_CAN_MB3_MID         EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register
+AT91C_CAN_MB3_MCR         EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register
+AT91C_CAN_MB3_MMR         EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register
+AT91C_CAN_MB3_MSR         EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register
+AT91C_CAN_MB3_MDL         EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register
+AT91C_CAN_MB3_MDH         EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register
+// - ========== Register definition for CAN_MB4 peripheral ========== 
+AT91C_CAN_MB4_MID         EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register
+AT91C_CAN_MB4_MMR         EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register
+AT91C_CAN_MB4_MDH         EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register
+AT91C_CAN_MB4_MFID        EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register
+AT91C_CAN_MB4_MSR         EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register
+AT91C_CAN_MB4_MCR         EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register
+AT91C_CAN_MB4_MDL         EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register
+AT91C_CAN_MB4_MAM         EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register
+// - ========== Register definition for CAN_MB5 peripheral ========== 
+AT91C_CAN_MB5_MSR         EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register
+AT91C_CAN_MB5_MCR         EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register
+AT91C_CAN_MB5_MFID        EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register
+AT91C_CAN_MB5_MDH         EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register
+AT91C_CAN_MB5_MID         EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register
+AT91C_CAN_MB5_MMR         EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register
+AT91C_CAN_MB5_MDL         EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register
+AT91C_CAN_MB5_MAM         EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register
+// - ========== Register definition for CAN_MB6 peripheral ========== 
+AT91C_CAN_MB6_MFID        EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register
+AT91C_CAN_MB6_MID         EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register
+AT91C_CAN_MB6_MAM         EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register
+AT91C_CAN_MB6_MSR         EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register
+AT91C_CAN_MB6_MDL         EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register
+AT91C_CAN_MB6_MCR         EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register
+AT91C_CAN_MB6_MDH         EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register
+AT91C_CAN_MB6_MMR         EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register
+// - ========== Register definition for CAN_MB7 peripheral ========== 
+AT91C_CAN_MB7_MCR         EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register
+AT91C_CAN_MB7_MDH         EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register
+AT91C_CAN_MB7_MFID        EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register
+AT91C_CAN_MB7_MDL         EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register
+AT91C_CAN_MB7_MID         EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register
+AT91C_CAN_MB7_MMR         EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register
+AT91C_CAN_MB7_MAM         EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register
+AT91C_CAN_MB7_MSR         EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register
+// - ========== Register definition for CAN peripheral ========== 
+AT91C_CAN_TCR             EQU (0xFFFD0024) ;- (CAN) Transfer Command Register
+AT91C_CAN_IMR             EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register
+AT91C_CAN_IER             EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register
+AT91C_CAN_ECR             EQU (0xFFFD0020) ;- (CAN) Error Counter Register
+AT91C_CAN_TIMESTP         EQU (0xFFFD001C) ;- (CAN) Time Stamp Register
+AT91C_CAN_MR              EQU (0xFFFD0000) ;- (CAN) Mode Register
+AT91C_CAN_IDR             EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register
+AT91C_CAN_ACR             EQU (0xFFFD0028) ;- (CAN) Abort Command Register
+AT91C_CAN_TIM             EQU (0xFFFD0018) ;- (CAN) Timer Register
+AT91C_CAN_SR              EQU (0xFFFD0010) ;- (CAN) Status Register
+AT91C_CAN_BR              EQU (0xFFFD0014) ;- (CAN) Baudrate Register
+AT91C_CAN_VR              EQU (0xFFFD00FC) ;- (CAN) Version Register
+// - ========== Register definition for EMAC peripheral ========== 
+AT91C_EMAC_ISR            EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register
+AT91C_EMAC_SA4H           EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes
+AT91C_EMAC_SA1L           EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes
+AT91C_EMAC_ELE            EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register
+AT91C_EMAC_LCOL           EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register
+AT91C_EMAC_RLE            EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register
+AT91C_EMAC_WOL            EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register
+AT91C_EMAC_DTF            EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register
+AT91C_EMAC_TUND           EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register
+AT91C_EMAC_NCR            EQU (0xFFFDC000) ;- (EMAC) Network Control Register
+AT91C_EMAC_SA4L           EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes
+AT91C_EMAC_RSR            EQU (0xFFFDC020) ;- (EMAC) Receive Status Register
+AT91C_EMAC_SA3L           EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes
+AT91C_EMAC_TSR            EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register
+AT91C_EMAC_IDR            EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register
+AT91C_EMAC_RSE            EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register
+AT91C_EMAC_ECOL           EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register
+AT91C_EMAC_TID            EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register
+AT91C_EMAC_HRB            EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0]
+AT91C_EMAC_TBQP           EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer
+AT91C_EMAC_USRIO          EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register
+AT91C_EMAC_PTR            EQU (0xFFFDC038) ;- (EMAC) Pause Time Register
+AT91C_EMAC_SA2H           EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes
+AT91C_EMAC_ROV            EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register
+AT91C_EMAC_ALE            EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register
+AT91C_EMAC_RJA            EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register
+AT91C_EMAC_RBQP           EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer
+AT91C_EMAC_TPF            EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register
+AT91C_EMAC_NCFGR          EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register
+AT91C_EMAC_HRT            EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32]
+AT91C_EMAC_USF            EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register
+AT91C_EMAC_FCSE           EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register
+AT91C_EMAC_TPQ            EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register
+AT91C_EMAC_MAN            EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register
+AT91C_EMAC_FTO            EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register
+AT91C_EMAC_REV            EQU (0xFFFDC0FC) ;- (EMAC) Revision Register
+AT91C_EMAC_IMR            EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register
+AT91C_EMAC_SCF            EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register
+AT91C_EMAC_PFR            EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register
+AT91C_EMAC_MCF            EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register
+AT91C_EMAC_NSR            EQU (0xFFFDC008) ;- (EMAC) Network Status Register
+AT91C_EMAC_SA2L           EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes
+AT91C_EMAC_FRO            EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register
+AT91C_EMAC_IER            EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register
+AT91C_EMAC_SA1H           EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes
+AT91C_EMAC_CSE            EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register
+AT91C_EMAC_SA3H           EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes
+AT91C_EMAC_RRE            EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register
+AT91C_EMAC_STE            EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register
+// - ========== Register definition for PDC_ADC peripheral ========== 
+AT91C_ADC_PTSR            EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register
+AT91C_ADC_PTCR            EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register
+AT91C_ADC_TNPR            EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register
+AT91C_ADC_TNCR            EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register
+AT91C_ADC_RNPR            EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register
+AT91C_ADC_RNCR            EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register
+AT91C_ADC_RPR             EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register
+AT91C_ADC_TCR             EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register
+AT91C_ADC_TPR             EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register
+AT91C_ADC_RCR             EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register
+// - ========== Register definition for ADC peripheral ========== 
+AT91C_ADC_CDR2            EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2
+AT91C_ADC_CDR3            EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3
+AT91C_ADC_CDR0            EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0
+AT91C_ADC_CDR5            EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5
+AT91C_ADC_CHDR            EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register
+AT91C_ADC_SR              EQU (0xFFFD801C) ;- (ADC) ADC Status Register
+AT91C_ADC_CDR4            EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4
+AT91C_ADC_CDR1            EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1
+AT91C_ADC_LCDR            EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register
+AT91C_ADC_IDR             EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register
+AT91C_ADC_CR              EQU (0xFFFD8000) ;- (ADC) ADC Control Register
+AT91C_ADC_CDR7            EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7
+AT91C_ADC_CDR6            EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6
+AT91C_ADC_IER             EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register
+AT91C_ADC_CHER            EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register
+AT91C_ADC_CHSR            EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register
+AT91C_ADC_MR              EQU (0xFFFD8004) ;- (ADC) ADC Mode Register
+AT91C_ADC_IMR             EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register
+// - ========== Register definition for PDC_AES peripheral ========== 
+AT91C_AES_TPR             EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register
+AT91C_AES_PTCR            EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register
+AT91C_AES_RNPR            EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register
+AT91C_AES_TNCR            EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register
+AT91C_AES_TCR             EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register
+AT91C_AES_RCR             EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register
+AT91C_AES_RNCR            EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register
+AT91C_AES_TNPR            EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register
+AT91C_AES_RPR             EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register
+AT91C_AES_PTSR            EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register
+// - ========== Register definition for AES peripheral ========== 
+AT91C_AES_IVxR            EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register
+AT91C_AES_MR              EQU (0xFFFA4004) ;- (AES) Mode Register
+AT91C_AES_VR              EQU (0xFFFA40FC) ;- (AES) AES Version Register
+AT91C_AES_ODATAxR         EQU (0xFFFA4050) ;- (AES) Output Data x Register
+AT91C_AES_IDATAxR         EQU (0xFFFA4040) ;- (AES) Input Data x Register
+AT91C_AES_CR              EQU (0xFFFA4000) ;- (AES) Control Register
+AT91C_AES_IDR             EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register
+AT91C_AES_IMR             EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register
+AT91C_AES_IER             EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register
+AT91C_AES_KEYWxR          EQU (0xFFFA4020) ;- (AES) Key Word x Register
+AT91C_AES_ISR             EQU (0xFFFA401C) ;- (AES) Interrupt Status Register
+// - ========== Register definition for PDC_TDES peripheral ========== 
+AT91C_TDES_RNCR           EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register
+AT91C_TDES_TCR            EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register
+AT91C_TDES_RCR            EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register
+AT91C_TDES_TNPR           EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register
+AT91C_TDES_RNPR           EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register
+AT91C_TDES_RPR            EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register
+AT91C_TDES_TNCR           EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register
+AT91C_TDES_TPR            EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register
+AT91C_TDES_PTSR           EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register
+AT91C_TDES_PTCR           EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register
+// - ========== Register definition for TDES peripheral ========== 
+AT91C_TDES_KEY2WxR        EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register
+AT91C_TDES_KEY3WxR        EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register
+AT91C_TDES_IDR            EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register
+AT91C_TDES_VR             EQU (0xFFFA80FC) ;- (TDES) TDES Version Register
+AT91C_TDES_IVxR           EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register
+AT91C_TDES_ODATAxR        EQU (0xFFFA8050) ;- (TDES) Output Data x Register
+AT91C_TDES_IMR            EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register
+AT91C_TDES_MR             EQU (0xFFFA8004) ;- (TDES) Mode Register
+AT91C_TDES_CR             EQU (0xFFFA8000) ;- (TDES) Control Register
+AT91C_TDES_IER            EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register
+AT91C_TDES_ISR            EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register
+AT91C_TDES_IDATAxR        EQU (0xFFFA8040) ;- (TDES) Input Data x Register
+AT91C_TDES_KEY1WxR        EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register
+
+// - *****************************************************************************
+// -               PIO DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_PIO_PA0             EQU (1 <<  0) ;- Pin Controlled by PA0
+AT91C_PA0_RXD0            EQU (AT91C_PIO_PA0) ;-  USART 0 Receive Data
+AT91C_PIO_PA1             EQU (1 <<  1) ;- Pin Controlled by PA1
+AT91C_PA1_TXD0            EQU (AT91C_PIO_PA1) ;-  USART 0 Transmit Data
+AT91C_PIO_PA10            EQU (1 << 10) ;- Pin Controlled by PA10
+AT91C_PA10_TWD            EQU (AT91C_PIO_PA10) ;-  TWI Two-wire Serial Data
+AT91C_PIO_PA11            EQU (1 << 11) ;- Pin Controlled by PA11
+AT91C_PA11_TWCK           EQU (AT91C_PIO_PA11) ;-  TWI Two-wire Serial Clock
+AT91C_PIO_PA12            EQU (1 << 12) ;- Pin Controlled by PA12
+AT91C_PA12_NPCS00         EQU (AT91C_PIO_PA12) ;-  SPI 0 Peripheral Chip Select 0
+AT91C_PIO_PA13            EQU (1 << 13) ;- Pin Controlled by PA13
+AT91C_PA13_NPCS01         EQU (AT91C_PIO_PA13) ;-  SPI 0 Peripheral Chip Select 1
+AT91C_PA13_PCK1           EQU (AT91C_PIO_PA13) ;-  PMC Programmable Clock Output 1
+AT91C_PIO_PA14            EQU (1 << 14) ;- Pin Controlled by PA14
+AT91C_PA14_NPCS02         EQU (AT91C_PIO_PA14) ;-  SPI 0 Peripheral Chip Select 2
+AT91C_PA14_IRQ1           EQU (AT91C_PIO_PA14) ;-  External Interrupt 1
+AT91C_PIO_PA15            EQU (1 << 15) ;- Pin Controlled by PA15
+AT91C_PA15_NPCS03         EQU (AT91C_PIO_PA15) ;-  SPI 0 Peripheral Chip Select 3
+AT91C_PA15_TCLK2          EQU (AT91C_PIO_PA15) ;-  Timer Counter 2 external clock input
+AT91C_PIO_PA16            EQU (1 << 16) ;- Pin Controlled by PA16
+AT91C_PA16_MISO0          EQU (AT91C_PIO_PA16) ;-  SPI 0 Master In Slave
+AT91C_PIO_PA17            EQU (1 << 17) ;- Pin Controlled by PA17
+AT91C_PA17_MOSI0          EQU (AT91C_PIO_PA17) ;-  SPI 0 Master Out Slave
+AT91C_PIO_PA18            EQU (1 << 18) ;- Pin Controlled by PA18
+AT91C_PA18_SPCK0          EQU (AT91C_PIO_PA18) ;-  SPI 0 Serial Clock
+AT91C_PIO_PA19            EQU (1 << 19) ;- Pin Controlled by PA19
+AT91C_PA19_CANRX          EQU (AT91C_PIO_PA19) ;-  CAN Receive
+AT91C_PIO_PA2             EQU (1 <<  2) ;- Pin Controlled by PA2
+AT91C_PA2_SCK0            EQU (AT91C_PIO_PA2) ;-  USART 0 Serial Clock
+AT91C_PA2_NPCS11          EQU (AT91C_PIO_PA2) ;-  SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PA20            EQU (1 << 20) ;- Pin Controlled by PA20
+AT91C_PA20_CANTX          EQU (AT91C_PIO_PA20) ;-  CAN Transmit
+AT91C_PIO_PA21            EQU (1 << 21) ;- Pin Controlled by PA21
+AT91C_PA21_TF             EQU (AT91C_PIO_PA21) ;-  SSC Transmit Frame Sync
+AT91C_PA21_NPCS10         EQU (AT91C_PIO_PA21) ;-  SPI 1 Peripheral Chip Select 0
+AT91C_PIO_PA22            EQU (1 << 22) ;- Pin Controlled by PA22
+AT91C_PA22_TK             EQU (AT91C_PIO_PA22) ;-  SSC Transmit Clock
+AT91C_PA22_SPCK1          EQU (AT91C_PIO_PA22) ;-  SPI 1 Serial Clock
+AT91C_PIO_PA23            EQU (1 << 23) ;- Pin Controlled by PA23
+AT91C_PA23_TD             EQU (AT91C_PIO_PA23) ;-  SSC Transmit data
+AT91C_PA23_MOSI1          EQU (AT91C_PIO_PA23) ;-  SPI 1 Master Out Slave
+AT91C_PIO_PA24            EQU (1 << 24) ;- Pin Controlled by PA24
+AT91C_PA24_RD             EQU (AT91C_PIO_PA24) ;-  SSC Receive Data
+AT91C_PA24_MISO1          EQU (AT91C_PIO_PA24) ;-  SPI 1 Master In Slave
+AT91C_PIO_PA25            EQU (1 << 25) ;- Pin Controlled by PA25
+AT91C_PA25_RK             EQU (AT91C_PIO_PA25) ;-  SSC Receive Clock
+AT91C_PA25_NPCS11         EQU (AT91C_PIO_PA25) ;-  SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PA26            EQU (1 << 26) ;- Pin Controlled by PA26
+AT91C_PA26_RF             EQU (AT91C_PIO_PA26) ;-  SSC Receive Frame Sync
+AT91C_PA26_NPCS12         EQU (AT91C_PIO_PA26) ;-  SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PA27            EQU (1 << 27) ;- Pin Controlled by PA27
+AT91C_PA27_DRXD           EQU (AT91C_PIO_PA27) ;-  DBGU Debug Receive Data
+AT91C_PA27_PCK3           EQU (AT91C_PIO_PA27) ;-  PMC Programmable Clock Output 3
+AT91C_PIO_PA28            EQU (1 << 28) ;- Pin Controlled by PA28
+AT91C_PA28_DTXD           EQU (AT91C_PIO_PA28) ;-  DBGU Debug Transmit Data
+AT91C_PIO_PA29            EQU (1 << 29) ;- Pin Controlled by PA29
+AT91C_PA29_FIQ            EQU (AT91C_PIO_PA29) ;-  AIC Fast Interrupt Input
+AT91C_PA29_NPCS13         EQU (AT91C_PIO_PA29) ;-  SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PA3             EQU (1 <<  3) ;- Pin Controlled by PA3
+AT91C_PA3_RTS0            EQU (AT91C_PIO_PA3) ;-  USART 0 Ready To Send
+AT91C_PA3_NPCS12          EQU (AT91C_PIO_PA3) ;-  SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PA30            EQU (1 << 30) ;- Pin Controlled by PA30
+AT91C_PA30_IRQ0           EQU (AT91C_PIO_PA30) ;-  External Interrupt 0
+AT91C_PA30_PCK2           EQU (AT91C_PIO_PA30) ;-  PMC Programmable Clock Output 2
+AT91C_PIO_PA4             EQU (1 <<  4) ;- Pin Controlled by PA4
+AT91C_PA4_CTS0            EQU (AT91C_PIO_PA4) ;-  USART 0 Clear To Send
+AT91C_PA4_NPCS13          EQU (AT91C_PIO_PA4) ;-  SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PA5             EQU (1 <<  5) ;- Pin Controlled by PA5
+AT91C_PA5_RXD1            EQU (AT91C_PIO_PA5) ;-  USART 1 Receive Data
+AT91C_PIO_PA6             EQU (1 <<  6) ;- Pin Controlled by PA6
+AT91C_PA6_TXD1            EQU (AT91C_PIO_PA6) ;-  USART 1 Transmit Data
+AT91C_PIO_PA7             EQU (1 <<  7) ;- Pin Controlled by PA7
+AT91C_PA7_SCK1            EQU (AT91C_PIO_PA7) ;-  USART 1 Serial Clock
+AT91C_PA7_NPCS01          EQU (AT91C_PIO_PA7) ;-  SPI 0 Peripheral Chip Select 1
+AT91C_PIO_PA8             EQU (1 <<  8) ;- Pin Controlled by PA8
+AT91C_PA8_RTS1            EQU (AT91C_PIO_PA8) ;-  USART 1 Ready To Send
+AT91C_PA8_NPCS02          EQU (AT91C_PIO_PA8) ;-  SPI 0 Peripheral Chip Select 2
+AT91C_PIO_PA9             EQU (1 <<  9) ;- Pin Controlled by PA9
+AT91C_PA9_CTS1            EQU (AT91C_PIO_PA9) ;-  USART 1 Clear To Send
+AT91C_PA9_NPCS03          EQU (AT91C_PIO_PA9) ;-  SPI 0 Peripheral Chip Select 3
+AT91C_PIO_PB0             EQU (1 <<  0) ;- Pin Controlled by PB0
+AT91C_PB0_ETXCK_EREFCK    EQU (AT91C_PIO_PB0) ;-  Ethernet MAC Transmit Clock/Reference Clock
+AT91C_PB0_PCK0            EQU (AT91C_PIO_PB0) ;-  PMC Programmable Clock Output 0
+AT91C_PIO_PB1             EQU (1 <<  1) ;- Pin Controlled by PB1
+AT91C_PB1_ETXEN           EQU (AT91C_PIO_PB1) ;-  Ethernet MAC Transmit Enable
+AT91C_PIO_PB10            EQU (1 << 10) ;- Pin Controlled by PB10
+AT91C_PB10_ETX2           EQU (AT91C_PIO_PB10) ;-  Ethernet MAC Transmit Data 2
+AT91C_PB10_NPCS11         EQU (AT91C_PIO_PB10) ;-  SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PB11            EQU (1 << 11) ;- Pin Controlled by PB11
+AT91C_PB11_ETX3           EQU (AT91C_PIO_PB11) ;-  Ethernet MAC Transmit Data 3
+AT91C_PB11_NPCS12         EQU (AT91C_PIO_PB11) ;-  SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PB12            EQU (1 << 12) ;- Pin Controlled by PB12
+AT91C_PB12_ETXER          EQU (AT91C_PIO_PB12) ;-  Ethernet MAC Transmikt Coding Error
+AT91C_PB12_TCLK0          EQU (AT91C_PIO_PB12) ;-  Timer Counter 0 external clock input
+AT91C_PIO_PB13            EQU (1 << 13) ;- Pin Controlled by PB13
+AT91C_PB13_ERX2           EQU (AT91C_PIO_PB13) ;-  Ethernet MAC Receive Data 2
+AT91C_PB13_NPCS01         EQU (AT91C_PIO_PB13) ;-  SPI 0 Peripheral Chip Select 1
+AT91C_PIO_PB14            EQU (1 << 14) ;- Pin Controlled by PB14
+AT91C_PB14_ERX3           EQU (AT91C_PIO_PB14) ;-  Ethernet MAC Receive Data 3
+AT91C_PB14_NPCS02         EQU (AT91C_PIO_PB14) ;-  SPI 0 Peripheral Chip Select 2
+AT91C_PIO_PB15            EQU (1 << 15) ;- Pin Controlled by PB15
+AT91C_PB15_ERXDV          EQU (AT91C_PIO_PB15) ;-  Ethernet MAC Receive Data Valid
+AT91C_PIO_PB16            EQU (1 << 16) ;- Pin Controlled by PB16
+AT91C_PB16_ECOL           EQU (AT91C_PIO_PB16) ;-  Ethernet MAC Collision Detected
+AT91C_PB16_NPCS13         EQU (AT91C_PIO_PB16) ;-  SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PB17            EQU (1 << 17) ;- Pin Controlled by PB17
+AT91C_PB17_ERXCK          EQU (AT91C_PIO_PB17) ;-  Ethernet MAC Receive Clock
+AT91C_PB17_NPCS03         EQU (AT91C_PIO_PB17) ;-  SPI 0 Peripheral Chip Select 3
+AT91C_PIO_PB18            EQU (1 << 18) ;- Pin Controlled by PB18
+AT91C_PB18_EF100          EQU (AT91C_PIO_PB18) ;-  Ethernet MAC Force 100 Mbits/sec
+AT91C_PB18_ADTRG          EQU (AT91C_PIO_PB18) ;-  ADC External Trigger
+AT91C_PIO_PB19            EQU (1 << 19) ;- Pin Controlled by PB19
+AT91C_PB19_PWM0           EQU (AT91C_PIO_PB19) ;-  PWM Channel 0
+AT91C_PB19_TCLK1          EQU (AT91C_PIO_PB19) ;-  Timer Counter 1 external clock input
+AT91C_PIO_PB2             EQU (1 <<  2) ;- Pin Controlled by PB2
+AT91C_PB2_ETX0            EQU (AT91C_PIO_PB2) ;-  Ethernet MAC Transmit Data 0
+AT91C_PIO_PB20            EQU (1 << 20) ;- Pin Controlled by PB20
+AT91C_PB20_PWM1           EQU (AT91C_PIO_PB20) ;-  PWM Channel 1
+AT91C_PB20_PCK0           EQU (AT91C_PIO_PB20) ;-  PMC Programmable Clock Output 0
+AT91C_PIO_PB21            EQU (1 << 21) ;- Pin Controlled by PB21
+AT91C_PB21_PWM2           EQU (AT91C_PIO_PB21) ;-  PWM Channel 2
+AT91C_PB21_PCK1           EQU (AT91C_PIO_PB21) ;-  PMC Programmable Clock Output 1
+AT91C_PIO_PB22            EQU (1 << 22) ;- Pin Controlled by PB22
+AT91C_PB22_PWM3           EQU (AT91C_PIO_PB22) ;-  PWM Channel 3
+AT91C_PB22_PCK2           EQU (AT91C_PIO_PB22) ;-  PMC Programmable Clock Output 2
+AT91C_PIO_PB23            EQU (1 << 23) ;- Pin Controlled by PB23
+AT91C_PB23_TIOA0          EQU (AT91C_PIO_PB23) ;-  Timer Counter 0 Multipurpose Timer I/O Pin A
+AT91C_PB23_DCD1           EQU (AT91C_PIO_PB23) ;-  USART 1 Data Carrier Detect
+AT91C_PIO_PB24            EQU (1 << 24) ;- Pin Controlled by PB24
+AT91C_PB24_TIOB0          EQU (AT91C_PIO_PB24) ;-  Timer Counter 0 Multipurpose Timer I/O Pin B
+AT91C_PB24_DSR1           EQU (AT91C_PIO_PB24) ;-  USART 1 Data Set ready
+AT91C_PIO_PB25            EQU (1 << 25) ;- Pin Controlled by PB25
+AT91C_PB25_TIOA1          EQU (AT91C_PIO_PB25) ;-  Timer Counter 1 Multipurpose Timer I/O Pin A
+AT91C_PB25_DTR1           EQU (AT91C_PIO_PB25) ;-  USART 1 Data Terminal ready
+AT91C_PIO_PB26            EQU (1 << 26) ;- Pin Controlled by PB26
+AT91C_PB26_TIOB1          EQU (AT91C_PIO_PB26) ;-  Timer Counter 1 Multipurpose Timer I/O Pin B
+AT91C_PB26_RI1            EQU (AT91C_PIO_PB26) ;-  USART 1 Ring Indicator
+AT91C_PIO_PB27            EQU (1 << 27) ;- Pin Controlled by PB27
+AT91C_PB27_TIOA2          EQU (AT91C_PIO_PB27) ;-  Timer Counter 2 Multipurpose Timer I/O Pin A
+AT91C_PB27_PWM0           EQU (AT91C_PIO_PB27) ;-  PWM Channel 0
+AT91C_PIO_PB28            EQU (1 << 28) ;- Pin Controlled by PB28
+AT91C_PB28_TIOB2          EQU (AT91C_PIO_PB28) ;-  Timer Counter 2 Multipurpose Timer I/O Pin B
+AT91C_PB28_PWM1           EQU (AT91C_PIO_PB28) ;-  PWM Channel 1
+AT91C_PIO_PB29            EQU (1 << 29) ;- Pin Controlled by PB29
+AT91C_PB29_PCK1           EQU (AT91C_PIO_PB29) ;-  PMC Programmable Clock Output 1
+AT91C_PB29_PWM2           EQU (AT91C_PIO_PB29) ;-  PWM Channel 2
+AT91C_PIO_PB3             EQU (1 <<  3) ;- Pin Controlled by PB3
+AT91C_PB3_ETX1            EQU (AT91C_PIO_PB3) ;-  Ethernet MAC Transmit Data 1
+AT91C_PIO_PB30            EQU (1 << 30) ;- Pin Controlled by PB30
+AT91C_PB30_PCK2           EQU (AT91C_PIO_PB30) ;-  PMC Programmable Clock Output 2
+AT91C_PB30_PWM3           EQU (AT91C_PIO_PB30) ;-  PWM Channel 3
+AT91C_PIO_PB4             EQU (1 <<  4) ;- Pin Controlled by PB4
+AT91C_PB4_ECRS_ECRSDV     EQU (AT91C_PIO_PB4) ;-  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+AT91C_PIO_PB5             EQU (1 <<  5) ;- Pin Controlled by PB5
+AT91C_PB5_ERX0            EQU (AT91C_PIO_PB5) ;-  Ethernet MAC Receive Data 0
+AT91C_PIO_PB6             EQU (1 <<  6) ;- Pin Controlled by PB6
+AT91C_PB6_ERX1            EQU (AT91C_PIO_PB6) ;-  Ethernet MAC Receive Data 1
+AT91C_PIO_PB7             EQU (1 <<  7) ;- Pin Controlled by PB7
+AT91C_PB7_ERXER           EQU (AT91C_PIO_PB7) ;-  Ethernet MAC Receive Error
+AT91C_PIO_PB8             EQU (1 <<  8) ;- Pin Controlled by PB8
+AT91C_PB8_EMDC            EQU (AT91C_PIO_PB8) ;-  Ethernet MAC Management Data Clock
+AT91C_PIO_PB9             EQU (1 <<  9) ;- Pin Controlled by PB9
+AT91C_PB9_EMDIO           EQU (AT91C_PIO_PB9) ;-  Ethernet MAC Management Data Input/Output
+
+// - *****************************************************************************
+// -               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_ID_FIQ              EQU ( 0) ;- Advanced Interrupt Controller (FIQ)
+AT91C_ID_SYS              EQU ( 1) ;- System Peripheral
+AT91C_ID_PIOA             EQU ( 2) ;- Parallel IO Controller A
+AT91C_ID_PIOB             EQU ( 3) ;- Parallel IO Controller B
+AT91C_ID_SPI0             EQU ( 4) ;- Serial Peripheral Interface 0
+AT91C_ID_SPI1             EQU ( 5) ;- Serial Peripheral Interface 1
+AT91C_ID_US0              EQU ( 6) ;- USART 0
+AT91C_ID_US1              EQU ( 7) ;- USART 1
+AT91C_ID_SSC              EQU ( 8) ;- Serial Synchronous Controller
+AT91C_ID_TWI              EQU ( 9) ;- Two-Wire Interface
+AT91C_ID_PWMC             EQU (10) ;- PWM Controller
+AT91C_ID_UDP              EQU (11) ;- USB Device Port
+AT91C_ID_TC0              EQU (12) ;- Timer Counter 0
+AT91C_ID_TC1              EQU (13) ;- Timer Counter 1
+AT91C_ID_TC2              EQU (14) ;- Timer Counter 2
+AT91C_ID_CAN              EQU (15) ;- Control Area Network Controller
+AT91C_ID_EMAC             EQU (16) ;- Ethernet MAC
+AT91C_ID_ADC              EQU (17) ;- Analog-to-Digital Converter
+AT91C_ID_AES              EQU (18) ;- Advanced Encryption Standard 128-bit
+AT91C_ID_TDES             EQU (19) ;- Triple Data Encryption Standard
+AT91C_ID_20_Reserved      EQU (20) ;- Reserved
+AT91C_ID_21_Reserved      EQU (21) ;- Reserved
+AT91C_ID_22_Reserved      EQU (22) ;- Reserved
+AT91C_ID_23_Reserved      EQU (23) ;- Reserved
+AT91C_ID_24_Reserved      EQU (24) ;- Reserved
+AT91C_ID_25_Reserved      EQU (25) ;- Reserved
+AT91C_ID_26_Reserved      EQU (26) ;- Reserved
+AT91C_ID_27_Reserved      EQU (27) ;- Reserved
+AT91C_ID_28_Reserved      EQU (28) ;- Reserved
+AT91C_ID_29_Reserved      EQU (29) ;- Reserved
+AT91C_ID_IRQ0             EQU (30) ;- Advanced Interrupt Controller (IRQ0)
+AT91C_ID_IRQ1             EQU (31) ;- Advanced Interrupt Controller (IRQ1)
+
+// - *****************************************************************************
+// -               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_BASE_SYS            EQU (0xFFFFF000) ;- (SYS) Base Address
+AT91C_BASE_AIC            EQU (0xFFFFF000) ;- (AIC) Base Address
+AT91C_BASE_PDC_DBGU       EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address
+AT91C_BASE_DBGU           EQU (0xFFFFF200) ;- (DBGU) Base Address
+AT91C_BASE_PIOA           EQU (0xFFFFF400) ;- (PIOA) Base Address
+AT91C_BASE_PIOB           EQU (0xFFFFF600) ;- (PIOB) Base Address
+AT91C_BASE_CKGR           EQU (0xFFFFFC20) ;- (CKGR) Base Address
+AT91C_BASE_PMC            EQU (0xFFFFFC00) ;- (PMC) Base Address
+AT91C_BASE_RSTC           EQU (0xFFFFFD00) ;- (RSTC) Base Address
+AT91C_BASE_RTTC           EQU (0xFFFFFD20) ;- (RTTC) Base Address
+AT91C_BASE_PITC           EQU (0xFFFFFD30) ;- (PITC) Base Address
+AT91C_BASE_WDTC           EQU (0xFFFFFD40) ;- (WDTC) Base Address
+AT91C_BASE_VREG           EQU (0xFFFFFD60) ;- (VREG) Base Address
+AT91C_BASE_MC             EQU (0xFFFFFF00) ;- (MC) Base Address
+AT91C_BASE_PDC_SPI1       EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address
+AT91C_BASE_SPI1           EQU (0xFFFE4000) ;- (SPI1) Base Address
+AT91C_BASE_PDC_SPI0       EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address
+AT91C_BASE_SPI0           EQU (0xFFFE0000) ;- (SPI0) Base Address
+AT91C_BASE_PDC_US1        EQU (0xFFFC4100) ;- (PDC_US1) Base Address
+AT91C_BASE_US1            EQU (0xFFFC4000) ;- (US1) Base Address
+AT91C_BASE_PDC_US0        EQU (0xFFFC0100) ;- (PDC_US0) Base Address
+AT91C_BASE_US0            EQU (0xFFFC0000) ;- (US0) Base Address
+AT91C_BASE_PDC_SSC        EQU (0xFFFD4100) ;- (PDC_SSC) Base Address
+AT91C_BASE_SSC            EQU (0xFFFD4000) ;- (SSC) Base Address
+AT91C_BASE_TWI            EQU (0xFFFB8000) ;- (TWI) Base Address
+AT91C_BASE_PWMC_CH3       EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address
+AT91C_BASE_PWMC_CH2       EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address
+AT91C_BASE_PWMC_CH1       EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address
+AT91C_BASE_PWMC_CH0       EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address
+AT91C_BASE_PWMC           EQU (0xFFFCC000) ;- (PWMC) Base Address
+AT91C_BASE_UDP            EQU (0xFFFB0000) ;- (UDP) Base Address
+AT91C_BASE_TC0            EQU (0xFFFA0000) ;- (TC0) Base Address
+AT91C_BASE_TC1            EQU (0xFFFA0040) ;- (TC1) Base Address
+AT91C_BASE_TC2            EQU (0xFFFA0080) ;- (TC2) Base Address
+AT91C_BASE_TCB            EQU (0xFFFA0000) ;- (TCB) Base Address
+AT91C_BASE_CAN_MB0        EQU (0xFFFD0200) ;- (CAN_MB0) Base Address
+AT91C_BASE_CAN_MB1        EQU (0xFFFD0220) ;- (CAN_MB1) Base Address
+AT91C_BASE_CAN_MB2        EQU (0xFFFD0240) ;- (CAN_MB2) Base Address
+AT91C_BASE_CAN_MB3        EQU (0xFFFD0260) ;- (CAN_MB3) Base Address
+AT91C_BASE_CAN_MB4        EQU (0xFFFD0280) ;- (CAN_MB4) Base Address
+AT91C_BASE_CAN_MB5        EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address
+AT91C_BASE_CAN_MB6        EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address
+AT91C_BASE_CAN_MB7        EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address
+AT91C_BASE_CAN            EQU (0xFFFD0000) ;- (CAN) Base Address
+AT91C_BASE_EMAC           EQU (0xFFFDC000) ;- (EMAC) Base Address
+AT91C_BASE_PDC_ADC        EQU (0xFFFD8100) ;- (PDC_ADC) Base Address
+AT91C_BASE_ADC            EQU (0xFFFD8000) ;- (ADC) Base Address
+AT91C_BASE_PDC_AES        EQU (0xFFFA4100) ;- (PDC_AES) Base Address
+AT91C_BASE_AES            EQU (0xFFFA4000) ;- (AES) Base Address
+AT91C_BASE_PDC_TDES       EQU (0xFFFA8100) ;- (PDC_TDES) Base Address
+AT91C_BASE_TDES           EQU (0xFFFA8000) ;- (TDES) Base Address
+
+// - *****************************************************************************
+// -               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_ISRAM               EQU (0x00200000) ;- Internal SRAM base address
+AT91C_ISRAM_SIZE          EQU (0x00010000) ;- Internal SRAM size in byte (64 Kbyte)
+AT91C_IFLASH              EQU (0x00100000) ;- Internal ROM base address
+AT91C_IFLASH_SIZE         EQU (0x00040000) ;- Internal ROM size in byte (256 Kbyte)
+
+
+
+#endif /* AT91SAM7X256_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c
new file mode 100644
index 0000000..9cbd823
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c
@@ -0,0 +1,51 @@
+//* ----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//* ----------------------------------------------------------------------------
+//* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//* ----------------------------------------------------------------------------
+//* File Name           : lib_AT91SAM7X256.h
+//* Object              : AT91SAM7X256 inlined functions
+//* Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
+//*
+//* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
+//* CVS Reference       : /lib_pmc_SAM7X.h/1.1/Tue Feb  1 08:32:10 2005//
+//* CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005//
+//* CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004//
+//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
+//* CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004//
+//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
+//* CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
+//* CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004//
+//* CVS Reference       : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
+//* CVS Reference       : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
+//* CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
+//* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
+//* CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004//
+//* CVS Reference       : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
+//* CVS Reference       : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
+//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+//* CVS Reference       : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
+//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
+//* CVS Reference       : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
+//* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+//* CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002//
+//* ----------------------------------------------------------------------------
+
+
+#include "AT91SAM7X256.h"
+
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_ConfigureIt
+//* \brief Interrupt Handler Initialization
+//*----------------------------------------------------------------------------
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h
new file mode 100644
index 0000000..e66b4e1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h
@@ -0,0 +1,4558 @@
+//* ----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//* ----------------------------------------------------------------------------
+//* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//* ----------------------------------------------------------------------------
+//* File Name           : lib_AT91SAM7X256.h
+//* Object              : AT91SAM7X256 inlined functions
+//* Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
+//*
+//* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
+//* CVS Reference       : /lib_pmc_SAM7X.h/1.1/Tue Feb  1 08:32:10 2005//
+//* CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005//
+//* CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004//
+//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
+//* CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004//
+//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
+//* CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
+//* CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004//
+//* CVS Reference       : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
+//* CVS Reference       : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
+//* CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
+//* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
+//* CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004//
+//* CVS Reference       : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
+//* CVS Reference       : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
+//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+//* CVS Reference       : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
+//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
+//* CVS Reference       : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
+//* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+//* CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002//
+//* ----------------------------------------------------------------------------
+
+#ifndef lib_AT91SAM7X256_H
+#define lib_AT91SAM7X256_H
+
+/* *****************************************************************************
+                SOFTWARE API FOR AIC
+   ***************************************************************************** */
+#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_ConfigureIt
+//* \brief Interrupt Handler Initialization
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_ConfigureIt (
+	AT91PS_AIC pAic,  // \arg pointer to the AIC registers
+	unsigned int irq_id,     // \arg interrupt number to initialize
+	unsigned int priority,   // \arg priority to give to the interrupt
+	unsigned int src_type,   // \arg activation and sense of activation
+	void (*newHandler) (void) ) // \arg address of the interrupt handler
+{
+	unsigned int oldHandler;
+    unsigned int mask ;
+
+    oldHandler = pAic->AIC_SVR[irq_id];
+
+    mask = 0x1 << irq_id ;
+    //* Disable the interrupt on the interrupt controller
+    pAic->AIC_IDCR = mask ;
+    //* Save the interrupt handler routine pointer and the interrupt priority
+    pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
+    //* Store the Source Mode Register
+    pAic->AIC_SMR[irq_id] = src_type | priority  ;
+    //* Clear the interrupt on the interrupt controller
+    pAic->AIC_ICCR = mask ;
+
+	return oldHandler;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_EnableIt
+//* \brief Enable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_EnableIt (
+	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
+	unsigned int irq_id ) // \arg interrupt number to initialize
+{
+    //* Enable the interrupt on the interrupt controller
+    pAic->AIC_IECR = 0x1 << irq_id ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_DisableIt
+//* \brief Disable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_DisableIt (
+	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
+	unsigned int irq_id ) // \arg interrupt number to initialize
+{
+    unsigned int mask = 0x1 << irq_id;
+    //* Disable the interrupt on the interrupt controller
+    pAic->AIC_IDCR = mask ;
+    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+    pAic->AIC_ICCR = mask ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_ClearIt
+//* \brief Clear corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_ClearIt (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg interrupt number to initialize
+{
+    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+    pAic->AIC_ICCR = (0x1 << irq_id);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_AcknowledgeIt
+//* \brief Acknowledge corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_AcknowledgeIt (
+	AT91PS_AIC pAic)     // \arg pointer to the AIC registers
+{
+    pAic->AIC_EOICR = pAic->AIC_EOICR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_SetExceptionVector
+//* \brief Configure vector handler
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_SetExceptionVector (
+	unsigned int *pVector, // \arg pointer to the AIC registers
+	void (*Handler) () )   // \arg Interrupt Handler
+{
+	unsigned int oldVector = *pVector;
+
+	if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
+		*pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
+	else
+		*pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
+
+	return oldVector;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_Trig
+//* \brief Trig an IT
+//*----------------------------------------------------------------------------
+__inline void  AT91F_AIC_Trig (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg interrupt number
+{
+	pAic->AIC_ISCR = (0x1 << irq_id) ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_IsActive
+//* \brief Test if an IT is active
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_IsActive (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg Interrupt Number
+{
+	return (pAic->AIC_ISR & (0x1 << irq_id));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_IsPending
+//* \brief Test if an IT is pending
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_IsPending (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg Interrupt Number
+{
+	return (pAic->AIC_IPR & (0x1 << irq_id));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_Open
+//* \brief Set exception vectors and AIC registers to default values
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_Open(
+	AT91PS_AIC pAic,        // \arg pointer to the AIC registers
+	void (*IrqHandler) (),  // \arg Default IRQ vector exception
+	void (*FiqHandler) (),  // \arg Default FIQ vector exception
+	void (*DefaultHandler)  (), // \arg Default Handler set in ISR
+	void (*SpuriousHandler) (), // \arg Default Spurious Handler
+	unsigned int protectMode)   // \arg Debug Control Register
+{
+	int i;
+
+	// Disable all interrupts and set IVR to the default handler
+	for (i = 0; i < 32; ++i) {
+		AT91F_AIC_DisableIt(pAic, i);
+		AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);
+	}
+
+	// Set the IRQ exception vector
+	AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
+	// Set the Fast Interrupt exception vector
+	AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
+
+	pAic->AIC_SPU = (unsigned int) SpuriousHandler;
+	pAic->AIC_DCR = protectMode;
+}
+/* *****************************************************************************
+                SOFTWARE API FOR PDC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetNextRx
+//* \brief Set the next receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextRx (
+	AT91PS_PDC pPDC,     // \arg pointer to a PDC controller
+	char *address,       // \arg address to the next bloc to be received
+	unsigned int bytes)  // \arg number of bytes to be received
+{
+	pPDC->PDC_RNPR = (unsigned int) address;
+	pPDC->PDC_RNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetNextTx
+//* \brief Set the next transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextTx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be transmitted
+	unsigned int bytes)    // \arg number of bytes to be transmitted
+{
+	pPDC->PDC_TNPR = (unsigned int) address;
+	pPDC->PDC_TNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetRx
+//* \brief Set the receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetRx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be received
+	unsigned int bytes)    // \arg number of bytes to be received
+{
+	pPDC->PDC_RPR = (unsigned int) address;
+	pPDC->PDC_RCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetTx
+//* \brief Set the transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetTx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be transmitted
+	unsigned int bytes)    // \arg number of bytes to be transmitted
+{
+	pPDC->PDC_TPR = (unsigned int) address;
+	pPDC->PDC_TCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_EnableTx
+//* \brief Enable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableTx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_EnableRx
+//* \brief Enable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableRx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_DisableTx
+//* \brief Disable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableTx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_DisableRx
+//* \brief Disable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableRx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsTxEmpty
+//* \brief Test if the current transfer descriptor has been sent
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_TCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsNextTxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_TNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsRxEmpty
+//* \brief Test if the current transfer descriptor has been filled
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_RCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsNextRxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_RNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_Open
+//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Open (
+	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
+{
+    //* Disable the RX and TX PDC transfer requests
+	AT91F_PDC_DisableRx(pPDC);
+	AT91F_PDC_DisableTx(pPDC);
+
+	//* Reset all Counter register Next buffer first
+	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+    //* Enable the RX and TX PDC transfer requests
+	AT91F_PDC_EnableRx(pPDC);
+	AT91F_PDC_EnableTx(pPDC);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_Close
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Close (
+	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
+{
+    //* Disable the RX and TX PDC transfer requests
+	AT91F_PDC_DisableRx(pPDC);
+	AT91F_PDC_DisableTx(pPDC);
+
+	//* Reset all Counter register Next buffer first
+	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SendFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_SendFrame(
+	AT91PS_PDC pPDC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	if (AT91F_PDC_IsTxEmpty(pPDC)) {
+		//* Buffer and next buffer can be initialized
+		AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
+		AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
+		return 2;
+	}
+	else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
+		//* Only one buffer can be initialized
+		AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
+		return 1;
+	}
+	else {
+		//* All buffer are in use...
+		return 0;
+	}
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_ReceiveFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_ReceiveFrame (
+	AT91PS_PDC pPDC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	if (AT91F_PDC_IsRxEmpty(pPDC)) {
+		//* Buffer and next buffer can be initialized
+		AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
+		AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
+		return 2;
+	}
+	else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
+		//* Only one buffer can be initialized
+		AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
+		return 1;
+	}
+	else {
+		//* All buffer are in use...
+		return 0;
+	}
+}
+/* *****************************************************************************
+                SOFTWARE API FOR DBGU
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_InterruptEnable
+//* \brief Enable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptEnable(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  dbgu interrupt to be enabled
+{
+        pDbgu->DBGU_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_InterruptDisable
+//* \brief Disable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptDisable(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  dbgu interrupt to be disabled
+{
+        pDbgu->DBGU_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_GetInterruptMaskStatus
+//* \brief Return DBGU Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
+        AT91PS_DBGU pDbgu) // \arg  pointer to a DBGU controller
+{
+        return pDbgu->DBGU_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_IsInterruptMasked
+//* \brief Test if DBGU Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_DBGU_IsInterruptMasked(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PIO
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgPeriph
+//* \brief Enable pins to be drived by peripheral
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPeriph(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int periphAEnable,  // \arg PERIPH A to enable
+	unsigned int periphBEnable)  // \arg PERIPH B to enable
+
+{
+	pPio->PIO_ASR = periphAEnable;
+	pPio->PIO_BSR = periphBEnable;
+	pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgOutput
+//* \brief Enable PIO in output mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOutput(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int pioEnable)      // \arg PIO to be enabled
+{
+	pPio->PIO_PER = pioEnable; // Set in PIO mode
+	pPio->PIO_OER = pioEnable; // Configure in Output
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgInput
+//* \brief Enable PIO in input mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInput(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int inputEnable)      // \arg PIO to be enabled
+{
+	// Disable output
+	pPio->PIO_ODR  = inputEnable;
+	pPio->PIO_PER  = inputEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgOpendrain
+//* \brief Configure PIO in open drain
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOpendrain(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int multiDrvEnable) // \arg pio to be configured in open drain
+{
+	// Configure the multi-drive option
+	pPio->PIO_MDDR = ~multiDrvEnable;
+	pPio->PIO_MDER = multiDrvEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgPullup
+//* \brief Enable pullup on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPullup(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int pullupEnable)   // \arg enable pullup on PIO
+{
+		// Connect or not Pullup
+	pPio->PIO_PPUDR = ~pullupEnable;
+	pPio->PIO_PPUER = pullupEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgDirectDrive
+//* \brief Enable direct drive on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgDirectDrive(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int directDrive)    // \arg PIO to be configured with direct drive
+
+{
+	// Configure the Direct Drive
+	pPio->PIO_OWDR  = ~directDrive;
+	pPio->PIO_OWER  = directDrive;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgInputFilter
+//* \brief Enable input filter on input PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInputFilter(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int inputFilter)    // \arg PIO to be configured with input filter
+
+{
+	// Configure the Direct Drive
+	pPio->PIO_IFDR  = ~inputFilter;
+	pPio->PIO_IFER  = inputFilter;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInput
+//* \brief Return PIO input value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
+	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+	return pPio->PIO_PDSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInputSet
+//* \brief Test if PIO is input flag is active
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputSet(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PIO_GetInput(pPio) & flag);
+}
+
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_SetOutput
+//* \brief Set to 1 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_SetOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be set
+{
+	pPio->PIO_SODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_ClearOutput
+//* \brief Set to 0 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ClearOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be cleared
+{
+	pPio->PIO_CODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_ForceOutput
+//* \brief Force output when Direct drive option is enabled
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ForceOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be forced
+{
+	pPio->PIO_ODSR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Enable
+//* \brief Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Enable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be enabled 
+{
+        pPio->PIO_PER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Disable
+//* \brief Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Disable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be disabled 
+{
+        pPio->PIO_PDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetStatus
+//* \brief Return PIO Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_PSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsSet
+//* \brief Test if PIO is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputEnable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output to be enabled
+{
+        pPio->PIO_OER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputDisable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output to be disabled
+{
+        pPio->PIO_ODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputStatus
+//* \brief Return PIO Output Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_OSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOuputSet
+//* \brief Test if PIO Output is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InputFilterEnable
+//* \brief Input Filter Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio input filter to be enabled
+{
+        pPio->PIO_IFER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InputFilterDisable
+//* \brief Input Filter Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio input filter to be disabled
+{
+        pPio->PIO_IFDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInputFilterStatus
+//* \brief Return PIO Input Filter Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_IFSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInputFilterSet
+//* \brief Test if PIO Input filter is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputFilterSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputDataStatus
+//* \brief Return PIO Output Data Status 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status 
+	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ODSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InterruptEnable
+//* \brief Enable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio interrupt to be enabled
+{
+        pPio->PIO_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InterruptDisable
+//* \brief Disable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio interrupt to be disabled
+{
+        pPio->PIO_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInterruptMaskStatus
+//* \brief Return PIO Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInterruptStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInterruptMasked
+//* \brief Test if PIO Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptMasked(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInterruptSet
+//* \brief Test if PIO Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_MultiDriverEnable
+//* \brief Multi Driver Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be enabled
+{
+        pPio->PIO_MDER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_MultiDriverDisable
+//* \brief Multi Driver Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be disabled
+{
+        pPio->PIO_MDDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetMultiDriverStatus
+//* \brief Return PIO Multi Driver Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_MDSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsMultiDriverSet
+//* \brief Test if PIO MultiDriver is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsMultiDriverSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_A_RegisterSelection
+//* \brief PIO A Register Selection 
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_A_RegisterSelection(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio A register selection
+{
+        pPio->PIO_ASR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_B_RegisterSelection
+//* \brief PIO B Register Selection 
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_B_RegisterSelection(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio B register selection 
+{
+        pPio->PIO_BSR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Get_AB_RegisterStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ABSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsAB_RegisterSet
+//* \brief Test if PIO AB Register is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsAB_RegisterSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputWriteEnable
+//* \brief Output Write Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output write to be enabled
+{
+        pPio->PIO_OWER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputWriteDisable
+//* \brief Output Write Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output write to be disabled
+{
+        pPio->PIO_OWDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputWriteStatus
+//* \brief Return PIO Output Write Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_OWSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOutputWriteSet
+//* \brief Test if PIO OutputWrite is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputWriteSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetCfgPullup
+//* \brief Return PIO Configuration Pullup
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup 
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_PPUSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOutputDataStatusSet
+//* \brief Test if PIO Output Data Status is Set 
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputDataStatusSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsCfgPullupStatusSet
+//* \brief Test if PIO Configuration Pullup Status is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsCfgPullupStatusSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PMC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgSysClkEnableReg
+//* \brief Configure the System Clock Enable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkEnableReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	//* Write to the SCER register
+	pPMC->PMC_SCER = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgSysClkDisableReg
+//* \brief Configure the System Clock Disable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkDisableReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	//* Write to the SCDR register
+	pPMC->PMC_SCDR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetSysClkStatusReg
+//* \brief Return the System Clock Status Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
+	AT91PS_PMC pPMC // pointer to a CAN controller
+	)
+{
+	return pPMC->PMC_SCSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnablePeriphClock
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePeriphClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int periphIds)  // \arg IDs of peripherals to enable
+{
+	pPMC->PMC_PCER = periphIds;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisablePeriphClock
+//* \brief Disable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePeriphClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int periphIds)  // \arg IDs of peripherals to enable
+{
+	pPMC->PMC_PCDR = periphIds;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetPeriphClock
+//* \brief Get peripheral clock status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetPeriphClock (
+	AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+	return pPMC->PMC_PCSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_CfgMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscillatorReg (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int mode)
+{
+	pCKGR->CKGR_MOR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	return pCKGR->CKGR_MOR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_EnableMainOscillator
+//* \brief Enable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_EnableMainOscillator(
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_DisableMainOscillator
+//* \brief Disable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_DisableMainOscillator (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_CfgMainOscStartUpTime
+//* \brief Cfg MOR Register according to the main osc startup time
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscStartUpTime (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int startup_time,  // \arg main osc startup time in microsecond (us)
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
+	pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainClockFreqReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	return pCKGR->CKGR_MCFR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainClock
+//* \brief Return Main clock in Hz
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClock (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	return ((pCKGR->CKGR_MCFR  & AT91C_CKGR_MAINF) * slowClock) >> 4;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgMCKReg
+//* \brief Cfg Master Clock Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgMCKReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	pPMC->PMC_MCKR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetMCKReg
+//* \brief Return Master Clock Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMCKReg(
+	AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+	return pPMC->PMC_MCKR;
+}
+
+//*------------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetMasterClock
+//* \brief Return master clock in Hz which correponds to processor clock for ARM7
+//*------------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMasterClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	unsigned int reg = pPMC->PMC_MCKR;
+	unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
+	unsigned int pllDivider, pllMultiplier;
+
+	switch (reg & AT91C_PMC_CSS) {
+		case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
+			return slowClock / prescaler;
+		case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
+			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
+		case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
+			reg = pCKGR->CKGR_PLLR;
+			pllDivider    = (reg  & AT91C_CKGR_DIV);
+			pllMultiplier = ((reg  & AT91C_CKGR_MUL) >> 16) + 1;
+			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
+	}
+	return 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePCK (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int pck,  // \arg Peripheral clock identifier 0 .. 7
+	unsigned int mode)
+{
+	pPMC->PMC_PCKR[pck] = mode;
+	pPMC->PMC_SCER = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePCK (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int pck)  // \arg Peripheral clock identifier 0 .. 7
+{
+	pPMC->PMC_SCDR = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnableIt
+//* \brief Enable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnableIt (
+	AT91PS_PMC pPMC,     // pointer to a PMC controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pPMC->PMC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisableIt
+//* \brief Disable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisableIt (
+	AT91PS_PMC pPMC, // pointer to a PMC controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pPMC->PMC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetStatus
+//* \brief Return PMC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
+	AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+	return pPMC->PMC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetInterruptMaskStatus
+//* \brief Return PMC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
+	AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+	return pPMC->PMC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_IsInterruptMasked
+//* \brief Test if PMC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsInterruptMasked(
+        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_IsStatusSet
+//* \brief Test if PMC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsStatusSet(
+        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PMC_GetStatus(pPMC) & flag);
+}/* *****************************************************************************
+                SOFTWARE API FOR RSTC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTSoftReset
+//* \brief Start Software Reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTSoftReset(
+        AT91PS_RSTC pRSTC,
+        unsigned int reset)
+{
+	pRSTC->RSTC_RCR = (0xA5000000 | reset);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTSetMode
+//* \brief Set Reset Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTSetMode(
+        AT91PS_RSTC pRSTC,
+        unsigned int mode)
+{
+	pRSTC->RSTC_RMR = (0xA5000000 | mode);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTGetMode
+//* \brief Get Reset Mode
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTGetMode(
+        AT91PS_RSTC pRSTC)
+{
+	return (pRSTC->RSTC_RMR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTGetStatus
+//* \brief Get Reset Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTGetStatus(
+        AT91PS_RSTC pRSTC)
+{
+	return (pRSTC->RSTC_RSR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTIsSoftRstActive
+//* \brief Return !=0 if software reset is still not completed
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTIsSoftRstActive(
+        AT91PS_RSTC pRSTC)
+{
+	return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR RTTC
+   ***************************************************************************** */
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_SetRTT_TimeBase()
+//* \brief  Set the RTT prescaler according to the TimeBase in ms
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTSetTimeBase(
+        AT91PS_RTTC pRTTC, 
+        unsigned int ms)
+{
+	if (ms > 2000)
+		return 1;   // AT91C_TIME_OUT_OF_RANGE
+	pRTTC->RTTC_RTMR &= ~0xFFFF;	
+	pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF);	
+	return 0;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTTSetPrescaler()
+//* \brief  Set the new prescaler value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTSetPrescaler(
+        AT91PS_RTTC pRTTC, 
+        unsigned int rtpres)
+{
+	pRTTC->RTTC_RTMR &= ~0xFFFF;	
+	pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF);	
+	return (pRTTC->RTTC_RTMR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTTRestart()
+//* \brief  Restart the RTT prescaler
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTRestart(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;	
+}
+
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_SetAlarmINT()
+//* \brief  Enable RTT Alarm Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetAlarmINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_ClearAlarmINT()
+//* \brief  Disable RTT Alarm Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTClearAlarmINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_SetRttIncINT()
+//* \brief  Enable RTT INC Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetRttIncINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_ClearRttIncINT()
+//* \brief  Disable RTT INC Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTClearRttIncINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_SetAlarmValue()
+//* \brief  Set RTT Alarm Value
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetAlarmValue(
+        AT91PS_RTTC pRTTC, unsigned int alarm)
+{
+	pRTTC->RTTC_RTAR = alarm;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_GetAlarmValue()
+//* \brief  Get RTT Alarm Value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTGetAlarmValue(
+        AT91PS_RTTC pRTTC)
+{
+	return(pRTTC->RTTC_RTAR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTTGetStatus()
+//* \brief  Read the RTT status
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTGetStatus(
+        AT91PS_RTTC pRTTC)
+{
+	return(pRTTC->RTTC_RTSR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_ReadValue()
+//* \brief  Read the RTT value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTReadValue(
+        AT91PS_RTTC pRTTC)
+{
+        register volatile unsigned int val1,val2;
+	do
+	{
+		val1 = pRTTC->RTTC_RTVR;
+		val2 = pRTTC->RTTC_RTVR;
+	}	
+	while(val1 != val2);
+	return(val1);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR PITC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITInit
+//* \brief System timer init : period in µsecond, system clock freq in MHz
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITInit(
+        AT91PS_PITC pPITC,
+        unsigned int period,
+        unsigned int pit_frequency)
+{
+	pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10
+	pPITC->PITC_PIMR |= AT91C_PITC_PITEN;	 
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITSetPIV
+//* \brief Set the PIT Periodic Interval Value 
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITSetPIV(
+        AT91PS_PITC pPITC,
+        unsigned int piv)
+{
+	pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITEnableInt
+//* \brief Enable PIT periodic interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITEnableInt(
+        AT91PS_PITC pPITC)
+{
+	pPITC->PITC_PIMR |= AT91C_PITC_PITIEN;	 
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITDisableInt
+//* \brief Disable PIT periodic interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITDisableInt(
+        AT91PS_PITC pPITC)
+{
+	pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;	 
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetMode
+//* \brief Read PIT mode register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetMode(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PIMR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetStatus
+//* \brief Read PIT status register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetStatus(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PISR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetPIIR
+//* \brief Read PIT CPIV and PICNT without ressetting the counters
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetPIIR(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PIIR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetPIVR
+//* \brief Read System timer CPIV and PICNT without ressetting the counters
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetPIVR(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PIVR);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR WDTC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTSetMode
+//* \brief Set Watchdog Mode Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTSetMode(
+        AT91PS_WDTC pWDTC,
+        unsigned int Mode)
+{
+	pWDTC->WDTC_WDMR = Mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTRestart
+//* \brief Restart Watchdog
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTRestart(
+        AT91PS_WDTC pWDTC)
+{
+	pWDTC->WDTC_WDCR = 0xA5000001;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTSGettatus
+//* \brief Get Watchdog Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_WDTSGettatus(
+        AT91PS_WDTC pWDTC)
+{
+	return(pWDTC->WDTC_WDSR & 0x3);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTGetPeriod
+//* \brief Translate ms into Watchdog Compatible value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms)
+{
+	if ((ms < 4) || (ms > 16000))
+		return 0;
+	return((ms << 8) / 1000);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR VREG
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_VREG_Enable_LowPowerMode
+//* \brief Enable VREG Low Power Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_Enable_LowPowerMode(
+        AT91PS_VREG pVREG)
+{
+	pVREG->VREG_MR |= AT91C_VREG_PSTDBY;	 
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_VREG_Disable_LowPowerMode
+//* \brief Disable VREG Low Power Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_Disable_LowPowerMode(
+        AT91PS_VREG pVREG)
+{
+	pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY;	 
+}/* *****************************************************************************
+                SOFTWARE API FOR MC
+   ***************************************************************************** */
+
+#define AT91C_MC_CORRECT_KEY  ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_Remap
+//* \brief Make Remap
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_Remap (void)     //  
+{
+    AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
+    
+    pMC->MC_RCR = AT91C_MC_RCB;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_CfgModeReg
+//* \brief Configure the EFC Mode Register of the MC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_CfgModeReg (
+	AT91PS_MC pMC, // pointer to a MC controller
+	unsigned int mode)        // mode register 
+{
+	// Write to the FMR register
+	pMC->MC_FMR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_GetModeReg
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetModeReg(
+	AT91PS_MC pMC) // pointer to a MC controller
+{
+	return pMC->MC_FMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_ComputeFMCN
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_ComputeFMCN(
+	int master_clock) // master clock in Hz
+{
+	return (master_clock/1000000 +2);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_PerformCmd
+//* \brief Perform EFC Command
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_PerformCmd (
+	AT91PS_MC pMC, // pointer to a MC controller
+    unsigned int transfer_cmd)
+{
+	pMC->MC_FCR = transfer_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_GetStatus
+//* \brief Return MC EFC Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetStatus(
+	AT91PS_MC pMC) // pointer to a MC controller
+{
+	return pMC->MC_FSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_IsInterruptMasked
+//* \brief Test if EFC MC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
+        AT91PS_MC pMC,   // \arg  pointer to a MC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_IsInterruptSet
+//* \brief Test if EFC MC Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptSet(
+        AT91PS_MC pMC,   // \arg  pointer to a MC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_MC_EFC_GetStatus(pMC) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR SPI
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Open
+//* \brief Open a SPI Port
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_Open (
+        const unsigned int null)  // \arg
+{
+        /* NOT DEFINED AT THIS MOMENT */
+        return ( 0 );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgCs
+//* \brief Configure SPI chip select register
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgCs (
+	AT91PS_SPI pSPI,     // pointer to a SPI controller
+	int cs,     // SPI cs number (0 to 3)
+ 	int val)   //  chip select register
+{
+	//* Write to the CSR register
+	*(pSPI->SPI_CSR + cs) = val;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_EnableIt
+//* \brief Enable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_EnableIt (
+	AT91PS_SPI pSPI,     // pointer to a SPI controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pSPI->SPI_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_DisableIt
+//* \brief Disable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_DisableIt (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pSPI->SPI_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Reset
+//* \brief Reset the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Reset (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SWRST;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Enable
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Enable (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SPIEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Disable
+//* \brief Disable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Disable (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SPIDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgMode
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgMode (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	int mode)        // mode register 
+{
+	//* Write to the MR register
+	pSPI->SPI_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgPCS
+//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgPCS (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	char PCS_Device) // PCS of the Device
+{	
+ 	//* Write to the MR register
+	pSPI->SPI_MR &= 0xFFF0FFFF;
+	pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_ReceiveFrame (
+	AT91PS_SPI pSPI,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pSPI->SPI_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_SendFrame(
+	AT91PS_SPI pSPI,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pSPI->SPI_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Close
+//* \brief Close SPI: disable IT disable transfert, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Close (
+	AT91PS_SPI pSPI)     // \arg pointer to a SPI controller
+{
+    //* Reset all the Chip Select register
+    pSPI->SPI_CSR[0] = 0 ;
+    pSPI->SPI_CSR[1] = 0 ;
+    pSPI->SPI_CSR[2] = 0 ;
+    pSPI->SPI_CSR[3] = 0 ;
+
+    //* Reset the SPI mode
+    pSPI->SPI_MR = 0  ;
+
+    //* Disable all interrupts
+    pSPI->SPI_IDR = 0xFFFFFFFF ;
+
+    //* Abort the Peripheral Data Transfers
+    AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
+
+    //* Disable receiver and transmitter and stop any activity immediately
+    pSPI->SPI_CR = AT91C_SPI_SPIDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_PutChar (
+	AT91PS_SPI pSPI,
+	unsigned int character,
+             unsigned int cs_number )
+{
+    unsigned int value_for_cs;
+    value_for_cs = (~(1 << cs_number)) & 0xF;  //Place a zero among a 4 ONEs number
+    pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_GetChar (
+	const AT91PS_SPI pSPI)
+{
+    return((pSPI->SPI_RDR) & 0xFFFF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_GetInterruptMaskStatus
+//* \brief Return SPI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
+        AT91PS_SPI pSpi) // \arg  pointer to a SPI controller
+{
+        return pSpi->SPI_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_IsInterruptMasked
+//* \brief Test if SPI Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_IsInterruptMasked(
+        AT91PS_SPI pSpi,   // \arg  pointer to a SPI controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR USART
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Baudrate
+//* \brief Calculate the baudrate
+//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
+                        AT91C_US_NBSTOP_1_BIT + \
+                        AT91C_US_PAR_NONE + \
+                        AT91C_US_CHRL_8_BITS + \
+                        AT91C_US_CLKS_CLOCK )
+
+//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
+                            AT91C_US_NBSTOP_1_BIT + \
+                            AT91C_US_PAR_NONE + \
+                            AT91C_US_CHRL_8_BITS + \
+                            AT91C_US_CLKS_EXT )
+
+//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
+                       AT91C_US_USMODE_NORMAL + \
+                       AT91C_US_NBSTOP_1_BIT + \
+                       AT91C_US_PAR_NONE + \
+                       AT91C_US_CHRL_8_BITS + \
+                       AT91C_US_CLKS_CLOCK )
+
+//* SCK used Label
+#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
+
+//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
+#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
+					   		 AT91C_US_CLKS_CLOCK +\
+                       		 AT91C_US_NBSTOP_1_BIT + \
+                       		 AT91C_US_PAR_EVEN + \
+                       		 AT91C_US_CHRL_8_BITS + \
+                       		 AT91C_US_CKLO +\
+                       		 AT91C_US_OVER)
+
+//* Standard IRDA mode
+#define AT91C_US_ASYNC_IRDA_MODE (  AT91C_US_USMODE_IRDA + \
+                            AT91C_US_NBSTOP_1_BIT + \
+                            AT91C_US_PAR_NONE + \
+                            AT91C_US_CHRL_8_BITS + \
+                            AT91C_US_CLKS_CLOCK )
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Baudrate
+//* \brief Caluculate baud_value according to the main clock and the baud rate
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Baudrate (
+	const unsigned int main_clock, // \arg peripheral clock
+	const unsigned int baud_rate)  // \arg UART baudrate
+{
+	unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
+	if ((baud_value % 10) >= 5)
+		baud_value = (baud_value / 10) + 1;
+	else
+		baud_value /= 10;
+	return baud_value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetBaudrate (
+	AT91PS_USART pUSART,    // \arg pointer to a USART controller
+	unsigned int mainClock, // \arg peripheral clock
+	unsigned int speed)     // \arg UART baudrate
+{
+	//* Define the baud rate divisor register
+	pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetTimeguard
+//* \brief Set USART timeguard
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetTimeguard (
+	AT91PS_USART pUSART,    // \arg pointer to a USART controller
+	unsigned int timeguard) // \arg timeguard value
+{
+	//* Write the Timeguard Register
+	pUSART->US_TTGR = timeguard ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableIt
+//* \brief Enable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableIt (
+	AT91PS_USART pUSART, // \arg pointer to a USART controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pUSART->US_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableIt
+//* \brief Disable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableIt (
+	AT91PS_USART pUSART, // \arg pointer to a USART controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IER register
+	pUSART->US_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Configure
+//* \brief Configure USART
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Configure (
+	AT91PS_USART pUSART,     // \arg pointer to a USART controller
+	unsigned int mainClock,  // \arg peripheral clock
+	unsigned int mode ,      // \arg mode Register to be programmed
+	unsigned int baudRate ,  // \arg baudrate to be programmed
+	unsigned int timeguard ) // \arg timeguard to be programmed
+{
+    //* Disable interrupts
+    pUSART->US_IDR = (unsigned int) -1;
+
+    //* Reset receiver and transmitter
+    pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
+
+	//* Define the baud rate divisor register
+	AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
+
+	//* Write the Timeguard Register
+	AT91F_US_SetTimeguard(pUSART, timeguard);
+
+    //* Clear Transmit and Receive Counters
+    AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
+
+    //* Define the USART mode
+    pUSART->US_MR = mode  ;
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableRx
+//* \brief Enable receiving characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Enable receiver
+    pUSART->US_CR = AT91C_US_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableTx
+//* \brief Enable sending characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Enable  transmitter
+    pUSART->US_CR = AT91C_US_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ResetRx
+//* \brief Reset Receiver and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+	//* Reset receiver
+	pUSART->US_CR = AT91C_US_RSTRX;
+    //* Re-Enable receiver
+    pUSART->US_CR = AT91C_US_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ResetTx
+//* \brief Reset Transmitter and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+	//* Reset transmitter
+	pUSART->US_CR = AT91C_US_RSTTX;
+    //* Enable transmitter
+    pUSART->US_CR = AT91C_US_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableRx
+//* \brief Disable Receiver
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Disable receiver
+    pUSART->US_CR = AT91C_US_RXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableTx
+//* \brief Disable Transmitter
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Disable transmitter
+    pUSART->US_CR = AT91C_US_TXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Close
+//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Close (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Reset the baud rate divisor register
+    pUSART->US_BRGR = 0 ;
+
+    //* Reset the USART mode
+    pUSART->US_MR = 0  ;
+
+    //* Reset the Timeguard Register
+    pUSART->US_TTGR = 0;
+
+    //* Disable all interrupts
+    pUSART->US_IDR = 0xFFFFFFFF ;
+
+    //* Abort the Peripheral Data Transfers
+    AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
+
+    //* Disable receiver and transmitter and stop any activity immediately
+    pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_TxReady
+//* \brief Return 1 if a character can be written in US_THR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_TxReady (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR & AT91C_US_TXRDY);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_RxReady
+//* \brief Return 1 if a character can be read in US_RHR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_RxReady (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR & AT91C_US_RXRDY);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Error
+//* \brief Return the error flag
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Error (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR &
+    	(AT91C_US_OVRE |  // Overrun error
+    	 AT91C_US_FRAME | // Framing error
+    	 AT91C_US_PARE));  // Parity error
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_PutChar (
+	AT91PS_USART pUSART,
+	int character )
+{
+    pUSART->US_THR = (character & 0x1FF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_US_GetChar (
+	const AT91PS_USART pUSART)
+{
+    return((pUSART->US_RHR) & 0x1FF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_SendFrame(
+	AT91PS_USART pUSART,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pUSART->US_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_ReceiveFrame (
+	AT91PS_USART pUSART,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pUSART->US_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetIrdaFilter
+//* \brief Set the value of IrDa filter tregister
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetIrdaFilter (
+	AT91PS_USART pUSART,
+	unsigned char value
+)
+{
+	pUSART->US_IF = value;
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR SSC
+   ***************************************************************************** */
+//* Define the standard I2S mode configuration
+
+//* Configuration to set in the SSC Transmit Clock Mode Register
+//* Parameters :  nb_bit_by_slot : 8, 16 or 32 bits
+//* 			  nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+									   AT91C_SSC_CKS_DIV   +\
+                            		   AT91C_SSC_CKO_CONTINOUS      +\
+                            		   AT91C_SSC_CKG_NONE    +\
+                                       AT91C_SSC_START_FALL_RF +\
+                           			   AT91C_SSC_STTOUT  +\
+                            		   ((1<<16) & AT91C_SSC_STTDLY) +\
+                            		   ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
+
+
+//* Configuration to set in the SSC Transmit Frame Mode Register
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
+//* 			 nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+									(nb_bit_by_slot-1)  +\
+                            		AT91C_SSC_MSBF   +\
+                            		(((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB)  +\
+                            		(((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
+                            		AT91C_SSC_FSOS_NEGATIVE)
+
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_SetBaudrate (
+        AT91PS_SSC pSSC,        // \arg pointer to a SSC controller
+        unsigned int mainClock, // \arg peripheral clock
+        unsigned int speed)     // \arg SSC baudrate
+{
+        unsigned int baud_value;
+        //* Define the baud rate divisor register
+        if (speed == 0)
+           baud_value = 0;
+        else
+        {
+           baud_value = (unsigned int) (mainClock * 10)/(2*speed);
+           if ((baud_value % 10) >= 5)
+                  baud_value = (baud_value / 10) + 1;
+           else
+                  baud_value /= 10;
+        }
+
+        pSSC->SSC_CMR = baud_value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_Configure
+//* \brief Configure SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_Configure (
+             AT91PS_SSC pSSC,          // \arg pointer to a SSC controller
+             unsigned int syst_clock,  // \arg System Clock Frequency
+             unsigned int baud_rate,   // \arg Expected Baud Rate Frequency
+             unsigned int clock_rx,    // \arg Receiver Clock Parameters
+             unsigned int mode_rx,     // \arg mode Register to be programmed
+             unsigned int clock_tx,    // \arg Transmitter Clock Parameters
+             unsigned int mode_tx)     // \arg mode Register to be programmed
+{
+    //* Disable interrupts
+	pSSC->SSC_IDR = (unsigned int) -1;
+
+    //* Reset receiver and transmitter
+	pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
+
+    //* Define the Clock Mode Register
+	AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
+
+     //* Write the Receive Clock Mode Register
+	pSSC->SSC_RCMR =  clock_rx;
+
+     //* Write the Transmit Clock Mode Register
+	pSSC->SSC_TCMR =  clock_tx;
+
+     //* Write the Receive Frame Mode Register
+	pSSC->SSC_RFMR =  mode_rx;
+
+     //* Write the Transmit Frame Mode Register
+	pSSC->SSC_TFMR =  mode_tx;
+
+    //* Clear Transmit and Receive Counters
+	AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
+
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableRx
+//* \brief Enable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableRx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Enable receiver
+    pSSC->SSC_CR = AT91C_SSC_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableRx
+//* \brief Disable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableRx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Disable receiver
+    pSSC->SSC_CR = AT91C_SSC_RXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableTx
+//* \brief Enable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableTx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Enable  transmitter
+    pSSC->SSC_CR = AT91C_SSC_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableTx
+//* \brief Disable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableTx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Disable  transmitter
+    pSSC->SSC_CR = AT91C_SSC_TXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableIt
+//* \brief Enable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableIt (
+	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pSSC->SSC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableIt
+//* \brief Disable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableIt (
+	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pSSC->SSC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_ReceiveFrame (
+	AT91PS_SSC pSSC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pSSC->SSC_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_SendFrame(
+	AT91PS_SSC pSSC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pSSC->SSC_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_GetInterruptMaskStatus
+//* \brief Return SSC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
+        AT91PS_SSC pSsc) // \arg  pointer to a SSC controller
+{
+        return pSsc->SSC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_IsInterruptMasked
+//* \brief Test if SSC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_SSC_IsInterruptMasked(
+        AT91PS_SSC pSsc,   // \arg  pointer to a SSC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR TWI
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_EnableIt
+//* \brief Enable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_EnableIt (
+	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pTWI->TWI_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_DisableIt
+//* \brief Disable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_DisableIt (
+	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pTWI->TWI_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_Configure
+//* \brief Configure TWI in master mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI )          // \arg pointer to a TWI controller
+{
+    //* Disable interrupts
+	pTWI->TWI_IDR = (unsigned int) -1;
+
+    //* Reset peripheral
+	pTWI->TWI_CR = AT91C_TWI_SWRST;
+
+	//* Set Master mode
+	pTWI->TWI_CR = AT91C_TWI_MSEN;
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_GetInterruptMaskStatus
+//* \brief Return TWI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
+        AT91PS_TWI pTwi) // \arg  pointer to a TWI controller
+{
+        return pTwi->TWI_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_IsInterruptMasked
+//* \brief Test if TWI Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_TWI_IsInterruptMasked(
+        AT91PS_TWI pTwi,   // \arg  pointer to a TWI controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PWMC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_GetStatus
+//* \brief Return PWM Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
+	AT91PS_PWMC pPWM) // pointer to a PWM controller
+{
+	return pPWM->PWMC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_InterruptEnable
+//* \brief Enable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptEnable(
+        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  PWM interrupt to be enabled
+{
+        pPwm->PWMC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_InterruptDisable
+//* \brief Disable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptDisable(
+        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  PWM interrupt to be disabled
+{
+        pPwm->PWMC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_GetInterruptMaskStatus
+//* \brief Return PWM Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
+        AT91PS_PWMC pPwm) // \arg  pointer to a PWM controller
+{
+        return pPwm->PWMC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_IsInterruptMasked
+//* \brief Test if PWM Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsInterruptMasked(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_IsStatusSet
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsStatusSet(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PWMC_GetStatus(pPWM) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_CfgChannel
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int channelId, // \arg PWM channel ID
+        unsigned int mode, // \arg  PWM mode
+        unsigned int period, // \arg PWM period
+        unsigned int duty) // \arg PWM duty cycle
+{
+	pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
+	pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
+	pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_StartChannel
+//* \brief Enable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StartChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_ENA = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_StopChannel
+//* \brief Disable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StopChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_DIS = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_UpdateChannel
+//* \brief Update Period or Duty Cycle
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_UpdateChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int channelId, // \arg PWM channel ID
+        unsigned int update) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR UDP
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EnableIt
+//* \brief Enable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableIt (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pUDP->UDP_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_DisableIt
+//* \brief Disable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableIt (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pUDP->UDP_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_SetAddress
+//* \brief Set UDP functional address
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetAddress (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char address)   // \arg new UDP address
+{
+	pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EnableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableEp (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char endpoint)   // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_DisableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableEp (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char endpoint)   // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_SetState
+//* \brief Set UDP Device state
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetState (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg new UDP address
+{
+	pUDP->UDP_GLBSTATE  &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
+	pUDP->UDP_GLBSTATE  |= flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_GetState
+//* \brief return UDP Device state
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
+	AT91PS_UDP pUDP)     // \arg pointer to a UDP controller
+{
+	return (pUDP->UDP_GLBSTATE  & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_ResetEp
+//* \brief Reset UDP endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_ResetEp ( // \return the UDP device state
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg Endpoints to be reset
+{
+	pUDP->UDP_RSTEP = flag;
+	pUDP->UDP_RSTEP = 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpStall
+//* \brief Endpoint will STALL requests
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpStall(
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char endpoint)   // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpWrite
+//* \brief Write value in the DPR
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpWrite(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned char value)     // \arg value to be written in the DPR
+{
+	pUDP->UDP_FDR[endpoint] = value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpRead
+//* \brief Return value from the DPR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpRead(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	return pUDP->UDP_FDR[endpoint];
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpEndOfWr
+//* \brief Notify the UDP that values in DPR are ready to be sent
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpEndOfWr(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpClear
+//* \brief Clear flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpClear(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned int flag)       // \arg flag to be cleared
+{
+	pUDP->UDP_CSR[endpoint] &= ~(flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpSet
+//* \brief Set flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpSet(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned int flag)       // \arg flag to be cleared
+{
+	pUDP->UDP_CSR[endpoint] |= flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpStatus
+//* \brief Return the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpStatus(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	return pUDP->UDP_CSR[endpoint];
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_GetInterruptMaskStatus
+//* \brief Return UDP Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status
+        AT91PS_UDP pUdp) // \arg  pointer to a UDP controller
+{
+        return pUdp->UDP_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_IsInterruptMasked
+//* \brief Test if UDP Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_UDP_IsInterruptMasked(
+        AT91PS_UDP pUdp,   // \arg  pointer to a UDP controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR TC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_InterruptEnable
+//* \brief Enable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptEnable(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  TC interrupt to be enabled
+{
+        pTc->TC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_InterruptDisable
+//* \brief Disable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptDisable(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  TC interrupt to be disabled
+{
+        pTc->TC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_GetInterruptMaskStatus
+//* \brief Return TC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
+        AT91PS_TC pTc) // \arg  pointer to a TC controller
+{
+        return pTc->TC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_IsInterruptMasked
+//* \brief Test if TC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_TC_IsInterruptMasked(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR CAN
+   ***************************************************************************** */
+#define	STANDARD_FORMAT 0
+#define	EXTENDED_FORMAT 1
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_InitMailboxRegisters()
+//* \brief Configure the corresponding mailbox
+//*----------------------------------------------------------------------------
+__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB	CAN_Mailbox,
+								int  			mode_reg,
+								int 			acceptance_mask_reg,
+								int  			id_reg,
+								int  			data_low_reg,
+								int  			data_high_reg,
+								int  			control_reg)
+{
+	CAN_Mailbox->CAN_MB_MCR 	= 0x0;
+	CAN_Mailbox->CAN_MB_MMR 	= mode_reg;
+	CAN_Mailbox->CAN_MB_MAM 	= acceptance_mask_reg;
+	CAN_Mailbox->CAN_MB_MID 	= id_reg;
+	CAN_Mailbox->CAN_MB_MDL 	= data_low_reg; 		
+	CAN_Mailbox->CAN_MB_MDH 	= data_high_reg;
+	CAN_Mailbox->CAN_MB_MCR 	= control_reg;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_EnableCAN()
+//* \brief 
+//*----------------------------------------------------------------------------
+__inline void AT91F_EnableCAN(
+	AT91PS_CAN pCAN)     // pointer to a CAN controller
+{
+	pCAN->CAN_MR |= AT91C_CAN_CANEN;
+
+	// Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver
+	while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DisableCAN()
+//* \brief 
+//*----------------------------------------------------------------------------
+__inline void AT91F_DisableCAN(
+	AT91PS_CAN pCAN)     // pointer to a CAN controller
+{
+	pCAN->CAN_MR &= ~AT91C_CAN_CANEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_EnableIt
+//* \brief Enable CAN interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_EnableIt (
+	AT91PS_CAN pCAN,     // pointer to a CAN controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pCAN->CAN_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_DisableIt
+//* \brief Disable CAN interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_DisableIt (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pCAN->CAN_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetStatus
+//* \brief Return CAN Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status
+	AT91PS_CAN pCAN) // pointer to a CAN controller
+{
+	return pCAN->CAN_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetInterruptMaskStatus
+//* \brief Return CAN Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status
+	AT91PS_CAN pCAN) // pointer to a CAN controller
+{
+	return pCAN->CAN_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_IsInterruptMasked
+//* \brief Test if CAN Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_IsInterruptMasked(
+        AT91PS_CAN pCAN,   // \arg  pointer to a CAN controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_IsStatusSet
+//* \brief Test if CAN Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_IsStatusSet(
+        AT91PS_CAN pCAN,   // \arg  pointer to a CAN controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_CAN_GetStatus(pCAN) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgModeReg
+//* \brief Configure the Mode Register of the CAN controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgModeReg (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+	unsigned int mode)        // mode register 
+{
+	//* Write to the MR register
+	pCAN->CAN_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetModeReg
+//* \brief Return the Mode Register of the CAN controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetModeReg (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgBaudrateReg
+//* \brief Configure the Baudrate of the CAN controller for the network
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgBaudrateReg (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+	unsigned int baudrate_cfg)
+{
+	//* Write to the BR register
+	pCAN->CAN_BR = baudrate_cfg;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetBaudrate
+//* \brief Return the Baudrate of the CAN controller for the network value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetBaudrate (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_BR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetInternalCounter
+//* \brief Return CAN Timer Regsiter Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetInternalCounter (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_TIM;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetTimestamp
+//* \brief Return CAN Timestamp Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetTimestamp (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_TIMESTP;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetErrorCounter
+//* \brief Return CAN Error Counter Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetErrorCounter (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_ECR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_InitTransferRequest
+//* \brief Request for a transfer on the corresponding mailboxes
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_InitTransferRequest (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+    unsigned int transfer_cmd)
+{
+	pCAN->CAN_TCR = transfer_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_InitAbortRequest
+//* \brief Abort the corresponding mailboxes
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_InitAbortRequest (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+    unsigned int abort_cmd)
+{
+	pCAN->CAN_ACR = abort_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageModeReg
+//* \brief Program the Message Mode Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageModeReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int mode)
+{
+	CAN_Mailbox->CAN_MB_MMR = mode;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageModeReg
+//* \brief Return the Message Mode Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageModeReg (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MMR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageIDReg
+//* \brief Program the Message ID Register
+//* \brief Version == 0 for Standard messsage, Version == 1 for Extended  
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageIDReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int id,
+    unsigned char version)
+{
+	if(version==0)	// IDvA Standard Format
+		CAN_Mailbox->CAN_MB_MID = id<<18;
+	else	// IDvB Extended Format
+		CAN_Mailbox->CAN_MB_MID = id | (1<<29);	// set MIDE bit
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageIDReg
+//* \brief Return the Message ID Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageIDReg (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MID;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageAcceptanceMaskReg
+//* \brief Program the Message Acceptance Mask Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int mask)
+{
+	CAN_Mailbox->CAN_MB_MAM = mask;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageAcceptanceMaskReg
+//* \brief Return the Message Acceptance Mask Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MAM;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetFamilyID
+//* \brief Return the Message ID Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetFamilyID (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MFID;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageCtrl
+//* \brief Request and config for a transfer on the corresponding mailbox
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageCtrlReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int message_ctrl_cmd)
+{
+	CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageStatus
+//* \brief Return CAN Mailbox Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageStatus (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MSR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageDataLow
+//* \brief Program data low value
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageDataLow (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int data)
+{
+	CAN_Mailbox->CAN_MB_MDL = data;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageDataLow
+//* \brief Return data low value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageDataLow (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MDL;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageDataHigh
+//* \brief Program data high value
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageDataHigh (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int data)
+{
+	CAN_Mailbox->CAN_MB_MDH = data;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageDataHigh
+//* \brief Return data high value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageDataHigh (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MDH;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_Open
+//* \brief Open a CAN Port
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_Open (
+        const unsigned int null)  // \arg
+{
+        /* NOT DEFINED AT THIS MOMENT */
+        return ( 0 );
+}
+/* *****************************************************************************
+                SOFTWARE API FOR ADC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_EnableIt
+//* \brief Enable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableIt (
+	AT91PS_ADC pADC,     // pointer to a ADC controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pADC->ADC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_DisableIt
+//* \brief Disable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableIt (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pADC->ADC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetStatus
+//* \brief Return ADC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
+	AT91PS_ADC pADC) // pointer to a ADC controller
+{
+	return pADC->ADC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetInterruptMaskStatus
+//* \brief Return ADC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
+	AT91PS_ADC pADC) // pointer to a ADC controller
+{
+	return pADC->ADC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_IsInterruptMasked
+//* \brief Test if ADC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsInterruptMasked(
+        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_IsStatusSet
+//* \brief Test if ADC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsStatusSet(
+        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_ADC_GetStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgModeReg
+//* \brief Configure the Mode Register of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgModeReg (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int mode)        // mode register 
+{
+	//* Write to the MR register
+	pADC->ADC_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetModeReg
+//* \brief Return the Mode Register of the ADC controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetModeReg (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgTimings
+//* \brief Configure the different necessary timings of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgTimings (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int mck_clock, // in MHz 
+	unsigned int adc_clock, // in MHz 
+	unsigned int startup_time, // in us 
+	unsigned int sample_and_hold_time)	// in ns  
+{
+	unsigned int prescal,startup,shtim;
+	
+	prescal = mck_clock/(2*adc_clock) - 1;
+	startup = adc_clock*startup_time/8 - 1;
+	shtim = adc_clock*sample_and_hold_time/1000 - 1;
+	
+	//* Write to the MR register
+	pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_EnableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableChannel (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int channel)        // mode register 
+{
+	//* Write to the CHER register
+	pADC->ADC_CHER = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_DisableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableChannel (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int channel)        // mode register 
+{
+	//* Write to the CHDR register
+	pADC->ADC_CHDR = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetChannelStatus
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetChannelStatus (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CHSR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_StartConversion
+//* \brief Software request for a analog to digital conversion 
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_StartConversion (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	pADC->ADC_CR = AT91C_ADC_START;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_SoftReset
+//* \brief Software reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_SoftReset (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	pADC->ADC_CR = AT91C_ADC_SWRST;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetLastConvertedData
+//* \brief Return the Last Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetLastConvertedData (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_LCDR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH0
+//* \brief Return the Channel 0 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR0;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH1
+//* \brief Return the Channel 1 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR1;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH2
+//* \brief Return the Channel 2 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR2;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH3
+//* \brief Return the Channel 3 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR3;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH4
+//* \brief Return the Channel 4 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR4;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH5
+//* \brief Return the Channel 5 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR5;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH6
+//* \brief Return the Channel 6 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR6;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH7
+//* \brief Return the Channel 7 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR7;	
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR AES
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_EnableIt
+//* \brief Enable AES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_EnableIt (
+	AT91PS_AES pAES,     // pointer to a AES controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pAES->AES_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_DisableIt
+//* \brief Disable AES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_DisableIt (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pAES->AES_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetStatus
+//* \brief Return AES Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status
+	AT91PS_AES pAES) // pointer to a AES controller
+{
+	return pAES->AES_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetInterruptMaskStatus
+//* \brief Return AES Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status
+	AT91PS_AES pAES) // pointer to a AES controller
+{
+	return pAES->AES_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_IsInterruptMasked
+//* \brief Test if AES Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_IsInterruptMasked(
+        AT91PS_AES pAES,   // \arg  pointer to a AES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_IsStatusSet
+//* \brief Test if AES Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_IsStatusSet(
+        AT91PS_AES pAES,   // \arg  pointer to a AES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_AES_GetStatus(pAES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_CfgModeReg
+//* \brief Configure the Mode Register of the AES controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_CfgModeReg (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned int mode)        // mode register 
+{
+	//* Write to the MR register
+	pAES->AES_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetModeReg
+//* \brief Return the Mode Register of the AES controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetModeReg (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	return pAES->AES_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_StartProcessing
+//* \brief Start Encryption or Decryption
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_StartProcessing (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	pAES->AES_CR = AT91C_AES_START;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_SoftReset
+//* \brief Reset AES
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SoftReset (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	pAES->AES_CR = AT91C_AES_SWRST;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_LoadNewSeed
+//* \brief Load New Seed in the random number generator
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_LoadNewSeed (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	pAES->AES_CR = AT91C_AES_LOADSEED;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_SetCryptoKey
+//* \brief Set Cryptographic Key x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SetCryptoKey (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pAES->AES_KEYWxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_InputData
+//* \brief Set Input Data x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_InputData (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index,
+	unsigned int indata
+	)
+{
+	pAES->AES_IDATAxR[index] = indata;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetOutputData
+//* \brief Get Output Data x
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetOutputData (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index
+	)
+{
+	return pAES->AES_ODATAxR[index];	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_SetInitializationVector
+//* \brief Set Initialization Vector (or Counter) x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SetInitializationVector (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index,
+	unsigned int initvector
+	)
+{
+	pAES->AES_IVxR[index] = initvector;	
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR TDES
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_EnableIt
+//* \brief Enable TDES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_EnableIt (
+	AT91PS_TDES pTDES,     // pointer to a TDES controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pTDES->TDES_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_DisableIt
+//* \brief Disable TDES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_DisableIt (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pTDES->TDES_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetStatus
+//* \brief Return TDES Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status
+	AT91PS_TDES pTDES) // pointer to a TDES controller
+{
+	return pTDES->TDES_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetInterruptMaskStatus
+//* \brief Return TDES Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status
+	AT91PS_TDES pTDES) // pointer to a TDES controller
+{
+	return pTDES->TDES_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_IsInterruptMasked
+//* \brief Test if TDES Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_IsInterruptMasked(
+        AT91PS_TDES pTDES,   // \arg  pointer to a TDES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_IsStatusSet
+//* \brief Test if TDES Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_IsStatusSet(
+        AT91PS_TDES pTDES,   // \arg  pointer to a TDES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_TDES_GetStatus(pTDES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_CfgModeReg
+//* \brief Configure the Mode Register of the TDES controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_CfgModeReg (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned int mode)        // mode register 
+{
+	//* Write to the MR register
+	pTDES->TDES_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetModeReg
+//* \brief Return the Mode Register of the TDES controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetModeReg (
+	AT91PS_TDES pTDES // pointer to a TDES controller
+	)
+{
+	return pTDES->TDES_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_StartProcessing
+//* \brief Start Encryption or Decryption
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_StartProcessing (
+	AT91PS_TDES pTDES // pointer to a TDES controller
+	)
+{
+	pTDES->TDES_CR = AT91C_TDES_START;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SoftReset
+//* \brief Reset TDES
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SoftReset (
+	AT91PS_TDES pTDES // pointer to a TDES controller
+	)
+{
+	pTDES->TDES_CR = AT91C_TDES_SWRST;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetCryptoKey1
+//* \brief Set Cryptographic Key 1 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey1 (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pTDES->TDES_KEY1WxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetCryptoKey2
+//* \brief Set Cryptographic Key 2 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey2 (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pTDES->TDES_KEY2WxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetCryptoKey3
+//* \brief Set Cryptographic Key 3 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey3 (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pTDES->TDES_KEY3WxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_InputData
+//* \brief Set Input Data x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_InputData (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int indata
+	)
+{
+	pTDES->TDES_IDATAxR[index] = indata;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetOutputData
+//* \brief Get Output Data x
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetOutputData (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index
+	)
+{
+	return pTDES->TDES_ODATAxR[index];	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetInitializationVector
+//* \brief Set Initialization Vector x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetInitializationVector (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int initvector
+	)
+{
+	pTDES->TDES_IVxR[index] = initvector;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  DBGU
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_CfgPIO
+//* \brief Configure PIO controllers to drive DBGU signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA27_DRXD    ) |
+		((unsigned int) AT91C_PA28_DTXD    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgPIO
+//* \brief Configure PIO controllers to drive PMC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB30_PCK2    ) |
+		((unsigned int) AT91C_PB29_PCK1    ), // Peripheral A
+		((unsigned int) AT91C_PB20_PCK0    ) |
+		((unsigned int) AT91C_PB0_PCK0    ) |
+		((unsigned int) AT91C_PB22_PCK2    ) |
+		((unsigned int) AT91C_PB21_PCK1    )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA30_PCK2    ) |
+		((unsigned int) AT91C_PA13_PCK1    ) |
+		((unsigned int) AT91C_PA27_PCK3    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_VREG_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  VREG
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  RSTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SSC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_CfgPIO
+//* \brief Configure PIO controllers to drive SSC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA25_RK      ) |
+		((unsigned int) AT91C_PA22_TK      ) |
+		((unsigned int) AT91C_PA21_TF      ) |
+		((unsigned int) AT91C_PA24_RD      ) |
+		((unsigned int) AT91C_PA26_RF      ) |
+		((unsigned int) AT91C_PA23_TD      ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  WDTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  US1
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_US1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US1_CfgPIO
+//* \brief Configure PIO controllers to drive US1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB26_RI1     ) |
+		((unsigned int) AT91C_PB24_DSR1    ) |
+		((unsigned int) AT91C_PB23_DCD1    ) |
+		((unsigned int) AT91C_PB25_DTR1    )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA7_SCK1    ) |
+		((unsigned int) AT91C_PA8_RTS1    ) |
+		((unsigned int) AT91C_PA6_TXD1    ) |
+		((unsigned int) AT91C_PA5_RXD1    ) |
+		((unsigned int) AT91C_PA9_CTS1    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  US0
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_US0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US0_CfgPIO
+//* \brief Configure PIO controllers to drive US0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA0_RXD0    ) |
+		((unsigned int) AT91C_PA4_CTS0    ) |
+		((unsigned int) AT91C_PA3_RTS0    ) |
+		((unsigned int) AT91C_PA2_SCK0    ) |
+		((unsigned int) AT91C_PA1_TXD0    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  SPI1
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI1_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SPI1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI1_CfgPIO
+//* \brief Configure PIO controllers to drive SPI1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB16_NPCS13  ) |
+		((unsigned int) AT91C_PB10_NPCS11  ) |
+		((unsigned int) AT91C_PB11_NPCS12  )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA4_NPCS13  ) |
+		((unsigned int) AT91C_PA29_NPCS13  ) |
+		((unsigned int) AT91C_PA21_NPCS10  ) |
+		((unsigned int) AT91C_PA22_SPCK1   ) |
+		((unsigned int) AT91C_PA25_NPCS11  ) |
+		((unsigned int) AT91C_PA2_NPCS11  ) |
+		((unsigned int) AT91C_PA24_MISO1   ) |
+		((unsigned int) AT91C_PA3_NPCS12  ) |
+		((unsigned int) AT91C_PA26_NPCS12  ) |
+		((unsigned int) AT91C_PA23_MOSI1   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  SPI0
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI0_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SPI0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI0_CfgPIO
+//* \brief Configure PIO controllers to drive SPI0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB13_NPCS01  ) |
+		((unsigned int) AT91C_PB17_NPCS03  ) |
+		((unsigned int) AT91C_PB14_NPCS02  )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA16_MISO0   ) |
+		((unsigned int) AT91C_PA13_NPCS01  ) |
+		((unsigned int) AT91C_PA15_NPCS03  ) |
+		((unsigned int) AT91C_PA17_MOSI0   ) |
+		((unsigned int) AT91C_PA18_SPCK0   ) |
+		((unsigned int) AT91C_PA14_NPCS02  ) |
+		((unsigned int) AT91C_PA12_NPCS00  ), // Peripheral A
+		((unsigned int) AT91C_PA7_NPCS01  ) |
+		((unsigned int) AT91C_PA9_NPCS03  ) |
+		((unsigned int) AT91C_PA8_NPCS02  )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PITC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  AIC
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_FIQ) |
+		((unsigned int) 1 << AT91C_ID_IRQ0) |
+		((unsigned int) 1 << AT91C_ID_IRQ1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_CfgPIO
+//* \brief Configure PIO controllers to drive AIC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA30_IRQ0    ) |
+		((unsigned int) AT91C_PA29_FIQ     ), // Peripheral A
+		((unsigned int) AT91C_PA14_IRQ1    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  AES
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_AES));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TWI
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TWI));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_CfgPIO
+//* \brief Configure PIO controllers to drive TWI signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA11_TWCK    ) |
+		((unsigned int) AT91C_PA10_TWD     ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  ADC
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_ADC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgPIO
+//* \brief Configure PIO controllers to drive ADC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB18_ADTRG   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH3_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH3 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH3_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB22_PWM3    ), // Peripheral A
+		((unsigned int) AT91C_PB30_PWM3    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH2_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH2_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB21_PWM2    ), // Peripheral A
+		((unsigned int) AT91C_PB29_PWM2    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH1_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB20_PWM1    ), // Peripheral A
+		((unsigned int) AT91C_PB28_PWM1    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH0_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB19_PWM0    ), // Peripheral A
+		((unsigned int) AT91C_PB27_PWM0    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RTTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  RTTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_RTTC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  UDP
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_UDP));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TDES
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TDES));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_EMAC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  EMAC
+//*----------------------------------------------------------------------------
+__inline void AT91F_EMAC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_EMAC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_EMAC_CfgPIO
+//* \brief Configure PIO controllers to drive EMAC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_EMAC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB2_ETX0    ) |
+		((unsigned int) AT91C_PB12_ETXER   ) |
+		((unsigned int) AT91C_PB16_ECOL    ) |
+		((unsigned int) AT91C_PB11_ETX3    ) |
+		((unsigned int) AT91C_PB6_ERX1    ) |
+		((unsigned int) AT91C_PB15_ERXDV   ) |
+		((unsigned int) AT91C_PB13_ERX2    ) |
+		((unsigned int) AT91C_PB3_ETX1    ) |
+		((unsigned int) AT91C_PB8_EMDC    ) |
+		((unsigned int) AT91C_PB5_ERX0    ) |
+		//((unsigned int) AT91C_PB18_EF100   ) |
+		((unsigned int) AT91C_PB14_ERX3    ) |
+		((unsigned int) AT91C_PB4_ECRS_ECRSDV) |
+		((unsigned int) AT91C_PB1_ETXEN   ) |
+		((unsigned int) AT91C_PB10_ETX2    ) |
+		((unsigned int) AT91C_PB0_ETXCK_EREFCK) |
+		((unsigned int) AT91C_PB9_EMDIO   ) |
+		((unsigned int) AT91C_PB7_ERXER   ) |
+		((unsigned int) AT91C_PB17_ERXCK   ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC0
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC0_CfgPIO
+//* \brief Configure PIO controllers to drive TC0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB23_TIOA0   ) |
+		((unsigned int) AT91C_PB24_TIOB0   ), // Peripheral A
+		((unsigned int) AT91C_PB12_TCLK0   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC1
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC1_CfgPIO
+//* \brief Configure PIO controllers to drive TC1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB25_TIOA1   ) |
+		((unsigned int) AT91C_PB26_TIOB1   ), // Peripheral A
+		((unsigned int) AT91C_PB19_TCLK1   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC2_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC2
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC2));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC2_CfgPIO
+//* \brief Configure PIO controllers to drive TC2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB28_TIOB2   ) |
+		((unsigned int) AT91C_PB27_TIOA2   ), // Peripheral A
+		0); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA15_TCLK2   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  MC
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIOA_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PIOA
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIOA_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_PIOA));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIOB_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PIOB
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIOB_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_PIOB));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  CAN
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_CAN));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgPIO
+//* \brief Configure PIO controllers to drive CAN signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA20_CANTX   ) |
+		((unsigned int) AT91C_PA19_CANRX   ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PWMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_PWMC));
+}
+
+#endif // lib_AT91SAM7X256_H
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/port.c
new file mode 100644
index 0000000..426318d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/port.c
@@ -0,0 +1,213 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM7 port.
+ *
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in this file.  The ISR routines, which can only be compiled
+ * to ARM mode are contained in portISR.c.
+ *----------------------------------------------------------*/
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Processor constants. */
+#include "AT91SAM7X256.h"
+
+/* Constants required to setup the task context. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING	( ( StackType_t ) 0 )
+
+/* Constants required to setup the tick ISR. */
+#define portENABLE_TIMER			( ( uint8_t ) 0x01 )
+#define portPRESCALE_VALUE			0x00
+#define portINTERRUPT_ON_MATCH		( ( uint32_t ) 0x01 )
+#define portRESET_COUNT_ON_MATCH	( ( uint32_t ) 0x02 )
+
+/* Constants required to setup the PIT. */
+#define portPIT_CLOCK_DIVISOR			( ( uint32_t ) 16 )
+#define portPIT_COUNTER_VALUE			( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
+
+#define portINT_LEVEL_SENSITIVE  0
+#define portPIT_ENABLE      	( ( uint16_t ) 0x1 << 24 )
+#define portPIT_INT_ENABLE     	( ( uint16_t ) 0x1 << 25 )
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* 
+ * The scheduler can only be started from ARM mode, so 
+ * vPortISRStartFirstSTask() is defined in portISR.c. 
+ */
+extern void vPortISRStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* To ensure asserts in tasks.c don't fail, although in this case the assert
+	is not really required. */
+	pxTopOfStack--;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as 
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0x00000000;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The last thing onto the stack is the status register, which is set for
+	system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	#ifdef THUMB_INTERWORK
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+	#endif
+
+	pxTopOfStack--;
+
+	/* Some optimisation levels use the stack differently to others.  This 
+	means the interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortISRStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the timer 0 to generate the tick interrupts at the required frequency.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+AT91PS_PITC pxPIT = AT91C_BASE_PITC;
+
+	/* Setup the AIC for PIT interrupts.  The interrupt routine chosen depends
+	on whether the preemptive or cooperative scheduler is being used. */
+	#if configUSE_PREEMPTION == 0
+
+		extern void ( vNonPreemptiveTick ) ( void );
+		AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vNonPreemptiveTick );
+
+	#else
+		
+		extern void ( vPreemptiveTick )( void );
+		AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPreemptiveTick );
+
+	#endif
+
+	/* Configure the PIT period. */
+	pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
+
+	/* Enable the interrupt.  Global interrupts are disables at this point so 
+	this is safe. */
+    AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SYS;
+}
+/*-----------------------------------------------------------*/
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c
new file mode 100644
index 0000000..bbd5bde
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c
@@ -0,0 +1,227 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*-----------------------------------------------------------
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c  The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
+
+/*
+	Changes from V3.2.4
+
+	+ The assembler statements are now included in a single asm block rather
+	  than each line having its own asm block.
+*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#include "AT91SAM7X256.h"
+
+/* Constants required to handle interrupts. */
+#define portTIMER_MATCH_ISR_BIT		( ( uint8_t ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT		( ( uint32_t ) 0 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING		( ( uint32_t ) 0 )
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/*-----------------------------------------------------------*/
+
+/* ISR to handle manual context switches (from a call to taskYIELD()). */
+void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
+
+/*
+ * The scheduler can only be started from ARM mode, hence the inclusion of this
+ * function here.
+ */
+void vPortISRStartFirstTask( void );
+/*-----------------------------------------------------------*/
+
+void vPortISRStartFirstTask( void )
+{
+	/* Simply start the scheduler.  This is included here as it can only be
+	called from ARM mode. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by portYIELD() or taskYIELD() to manually force a context switch.
+ *
+ * When a context switch is performed from the task level the saved task
+ * context is made to look as if it occurred from within the tick ISR.  This
+ * way the same restore context function can be used when restoring the context
+ * saved from the ISR or that saved from a call to vPortYieldProcessor.
+ */
+void vPortYieldProcessor( void )
+{
+	/* Within an IRQ ISR the link register has an offset from the true return
+	address, but an SWI ISR does not.  Add the offset manually so the same
+	ISR return code can be used in both cases. */
+	__asm volatile ( "ADD		LR, LR, #4" );
+
+	/* Perform the context switch.  First save the context of the current task. */
+	portSAVE_CONTEXT();
+
+	/* Find the highest priority task that is ready to run. */
+	vTaskSwitchContext();
+
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * The ISR used for the scheduler tick depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+
+#if configUSE_PREEMPTION == 0
+
+	/* The cooperative scheduler requires a normal IRQ service routine to
+	simply increment the system tick. */
+	void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
+	void vNonPreemptiveTick( void )
+	{
+		uint32_t ulDummy;
+
+		/* Increment the tick count - which may wake some tasks but as the
+		preemptive scheduler is not being used any woken task is not given
+		processor time no matter what its priority. */
+		xTaskIncrementTick();
+
+		/* Clear the PIT interrupt. */
+		ulDummy = AT91C_BASE_PITC->PITC_PIVR;
+
+		/* End the interrupt in the AIC. */
+		AT91C_BASE_AIC->AIC_EOICR = ulDummy;
+	}
+
+#else
+
+	/* The preemptive scheduler is defined as "naked" as the full context is
+	saved on entry as part of the context switch. */
+	void vPreemptiveTick( void ) __attribute__((naked));
+	void vPreemptiveTick( void )
+	{
+		/* Save the context of the current task. */
+		portSAVE_CONTEXT();
+
+		/* Increment the tick count - this may wake a task. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Find the highest priority task that is ready to run. */
+			vTaskSwitchContext();
+		}
+
+		/* End the interrupt in the AIC. */
+		AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;
+
+		portRESTORE_CONTEXT();
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to
+ * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then
+ * the utilities are defined as macros in portmacro.h - as per other ports.
+ */
+void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+void vPortDisableInterruptsFromThumb( void )
+{
+	__asm volatile (
+		"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
+		"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
+		"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.						*/
+		"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
+		"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+		"BX		R14" );					/* Return back to thumb.					*/
+}
+
+void vPortEnableInterruptsFromThumb( void )
+{
+	__asm volatile (
+		"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
+		"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
+		"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.							*/
+		"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
+		"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+		"BX		R14" );					/* Return back to thumb.					*/
+}
+
+
+/* The code generated by the GCC compiler uses the stack in different ways at
+different optimisation levels.  The interrupt flags can therefore not always
+be saved to the stack.  Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 							*/
+	__asm volatile (
+		"STMDB	SP!, {R0}			\n\t"	/* Push R0.								*/
+		"MRS	R0, CPSR			\n\t"	/* Get CPSR.							*/
+		"ORR	R0, R0, #0xC0		\n\t"	/* Disable IRQ, FIQ.					*/
+		"MSR	CPSR, R0			\n\t"	/* Write back modified value.			*/
+		"LDMIA	SP!, {R0}" );				/* Pop R0.								*/
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Enable interrupts as per portEXIT_CRITICAL().					*/
+			__asm volatile (
+				"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/
+				"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/
+				"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/
+				"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/
+				"LDMIA	SP!, {R0}" );			/* Pop R0.						*/
+		}
+	}
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h
new file mode 100644
index 0000000..12117d4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h
@@ -0,0 +1,249 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+	Changes from V3.2.3
+
+	+ Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
+
+	Changes from V3.2.4
+
+	+ Removed the use of the %0 parameter within the assembler macros and
+	  replaced them with hard coded registers.  This will ensure the
+	  assembler does not select the link register as the temp register as
+	  was occasionally happening previously.
+
+	+ The assembler statements are now included in a single asm block rather
+	  than each line having its own asm block.
+
+	Changes from V4.5.0
+
+	+ Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
+	  and replaced them with portYIELD_FROM_ISR() macro.  Application code
+	  should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+	  macros as per the V4.5.1 demo code.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	portLONG
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+#define portNOP()					__asm volatile ( "NOP" );
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+
+/*
+ * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
+ * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
+ * are included here for efficiency.  An attempt to call one from
+ * THUMB mode code will result in a compile time error.
+ */
+
+#define portRESTORE_CONTEXT()											\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile uint32_t ulCriticalNesting;					\
+																		\
+	/* Set the LR to the task stack. */									\
+	__asm volatile (													\
+	"LDR		R0, =pxCurrentTCB								\n\t"	\
+	"LDR		R0, [R0]										\n\t"	\
+	"LDR		LR, [R0]										\n\t"	\
+																		\
+	/* The critical nesting depth is the first item on the stack. */	\
+	/* Load it into the ulCriticalNesting variable. */					\
+	"LDR		R0, =ulCriticalNesting							\n\t"	\
+	"LDMFD	LR!, {R1}											\n\t"	\
+	"STR		R1, [R0]										\n\t"	\
+																		\
+	/* Get the SPSR from the stack. */									\
+	"LDMFD	LR!, {R0}											\n\t"	\
+	"MSR		SPSR, R0										\n\t"	\
+																		\
+	/* Restore all system mode registers for the task. */				\
+	"LDMFD	LR, {R0-R14}^										\n\t"	\
+	"NOP														\n\t"	\
+																		\
+	/* Restore the return address. */									\
+	"LDR		LR, [LR, #+60]									\n\t"	\
+																		\
+	/* And return - correcting the offset in the LR to obtain the */	\
+	/* correct address. */												\
+	"SUBS	PC, LR, #4											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+/*-----------------------------------------------------------*/
+
+#define portSAVE_CONTEXT()												\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile uint32_t ulCriticalNesting;					\
+																		\
+	/* Push R0 as we are going to use the register. */					\
+	__asm volatile (													\
+	"STMDB	SP!, {R0}											\n\t"	\
+																		\
+	/* Set R0 to point to the task stack pointer. */					\
+	"STMDB	SP,{SP}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	SP, SP, #4											\n\t"	\
+	"LDMIA	SP!,{R0}											\n\t"	\
+																		\
+	/* Push the return address onto the stack. */						\
+	"STMDB	R0!, {LR}											\n\t"	\
+																		\
+	/* Now we have saved LR we can use it instead of R0. */				\
+	"MOV	LR, R0												\n\t"	\
+																		\
+	/* Pop R0 so we can save it onto the system mode stack. */			\
+	"LDMIA	SP!, {R0}											\n\t"	\
+																		\
+	/* Push all the system mode registers onto the task stack. */		\
+	"STMDB	LR,{R0-LR}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	LR, LR, #60											\n\t"	\
+																		\
+	/* Push the SPSR onto the task stack. */							\
+	"MRS	R0, SPSR											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	"LDR	R0, =ulCriticalNesting								\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	/* Store the new top of stack for the task. */						\
+	"LDR	R0, =pxCurrentTCB									\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STR	LR, [R0]											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+
+
+#define portYIELD_FROM_ISR()		vTaskSwitchContext()
+#define portYIELD()					__asm volatile ( "SWI 0" )
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions in
+ * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not
+ * defined then the utilities are defined as macros here - as per other ports.
+ */
+
+#ifdef THUMB_INTERWORK
+
+	extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	#define portDISABLE_INTERRUPTS()	vPortDisableInterruptsFromThumb()
+	#define portENABLE_INTERRUPTS()		vPortEnableInterruptsFromThumb()
+
+#else
+
+	#define portDISABLE_INTERRUPTS()											\
+		__asm volatile (														\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.			*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+	#define portENABLE_INTERRUPTS()												\
+		__asm volatile (														\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+#endif /* THUMB_INTERWORK */
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/port.c
new file mode 100644
index 0000000..826c7c2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/port.c
@@ -0,0 +1,221 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM7 port.
+ *
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in this file.  The ISR routines, which can only be compiled
+ * to ARM mode are contained in portISR.c.
+ *----------------------------------------------------------*/
+
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup the task context. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING	( ( StackType_t ) 0 )
+
+/* Constants required to setup the tick ISR. */
+#define portENABLE_TIMER			( ( uint8_t ) 0x01 )
+#define portPRESCALE_VALUE			0x00
+#define portINTERRUPT_ON_MATCH		( ( uint32_t ) 0x01 )
+#define portRESET_COUNT_ON_MATCH	( ( uint32_t ) 0x02 )
+
+/* Constants required to setup the VIC for the tick ISR. */
+#define portTIMER_VIC_CHANNEL		( ( uint32_t ) 0x0004 )
+#define portTIMER_VIC_CHANNEL_BIT	( ( uint32_t ) 0x0010 )
+#define portTIMER_VIC_ENABLE		( ( uint32_t ) 0x0020 )
+
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* 
+ * The scheduler can only be started from ARM mode, so 
+ * vPortISRStartFirstSTask() is defined in portISR.c. 
+ */
+extern void vPortISRStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* To ensure asserts in tasks.c don't fail, although in this case the assert
+	is not really required. */
+	pxTopOfStack--;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as 
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The last thing onto the stack is the status register, which is set for
+	system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+
+	pxTopOfStack--;
+
+	/* Some optimisation levels use the stack differently to others.  This 
+	means the interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortISRStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the timer 0 to generate the tick interrupts at the required frequency.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+uint32_t ulCompareMatch;
+extern void ( vTickISR )( void );
+
+	/* A 1ms tick does not require the use of the timer prescale.  This is
+	defaulted to zero but can be used if necessary. */
+	T0_PR = portPRESCALE_VALUE;
+
+	/* Calculate the match value required for our wanted tick rate. */
+	ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+	/* Protect against divide by zero.  Using an if() statement still results
+	in a warning - hence the #if. */
+	#if portPRESCALE_VALUE != 0
+	{
+		ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
+	}
+	#endif
+	T0_MR0 = ulCompareMatch;
+
+	/* Generate tick with timer 0 compare match. */
+	T0_MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
+
+	/* Setup the VIC for the timer. */
+	VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
+	VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
+	
+	/* The ISR installed depends on whether the preemptive or cooperative
+	scheduler is being used. */
+
+	VICVectAddr0 = ( int32_t ) vTickISR;
+	VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
+
+	/* Start the timer - interrupts are disabled when this function is called
+	so it is okay to do this here. */
+	T0_TCR = portENABLE_TIMER;
+}
+/*-----------------------------------------------------------*/
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/portISR.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/portISR.c
new file mode 100644
index 0000000..ab02033
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/portISR.c
@@ -0,0 +1,215 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*-----------------------------------------------------------
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c  The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
+
+/*
+	Changes from V2.5.2
+
+	+ The critical section management functions have been changed.  These no
+	  longer modify the stack and are safe to use at all optimisation levels.
+	  The functions are now also the same for both ARM and THUMB modes.
+
+	Changes from V2.6.0
+
+	+ Removed the 'static' from the definition of vNonPreemptiveTick() to
+	  allow the demo to link when using the cooperative scheduler.
+
+	Changes from V3.2.4
+
+	+ The assembler statements are now included in a single asm block rather
+	  than each line having its own asm block.
+*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* Constants required to handle interrupts. */
+#define portTIMER_MATCH_ISR_BIT		( ( uint8_t ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT		( ( uint32_t ) 0 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING		( ( uint32_t ) 0 )
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/*-----------------------------------------------------------*/
+
+/* ISR to handle manual context switches (from a call to taskYIELD()). */
+void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
+
+/*
+ * The scheduler can only be started from ARM mode, hence the inclusion of this
+ * function here.
+ */
+void vPortISRStartFirstTask( void );
+/*-----------------------------------------------------------*/
+
+void vPortISRStartFirstTask( void )
+{
+	/* Simply start the scheduler.  This is included here as it can only be
+	called from ARM mode. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by portYIELD() or taskYIELD() to manually force a context switch.
+ *
+ * When a context switch is performed from the task level the saved task
+ * context is made to look as if it occurred from within the tick ISR.  This
+ * way the same restore context function can be used when restoring the context
+ * saved from the ISR or that saved from a call to vPortYieldProcessor.
+ */
+void vPortYieldProcessor( void )
+{
+	/* Within an IRQ ISR the link register has an offset from the true return
+	address, but an SWI ISR does not.  Add the offset manually so the same
+	ISR return code can be used in both cases. */
+	__asm volatile ( "ADD		LR, LR, #4" );
+
+	/* Perform the context switch.  First save the context of the current task. */
+	portSAVE_CONTEXT();
+
+	/* Find the highest priority task that is ready to run. */
+	__asm volatile ( "bl vTaskSwitchContext" );
+
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * The ISR used for the scheduler tick.
+ */
+void vTickISR( void ) __attribute__((naked));
+void vTickISR( void )
+{
+	/* Save the context of the interrupted task. */
+	portSAVE_CONTEXT();
+
+	/* Increment the RTOS tick count, then look for the highest priority
+	task that is ready to run. */
+	__asm volatile
+	(
+		"	bl xTaskIncrementTick	\t\n" \
+		"	cmp r0, #0				\t\n" \
+		"	beq SkipContextSwitch	\t\n" \
+		"	bl vTaskSwitchContext	\t\n" \
+		"SkipContextSwitch:			\t\n"
+	);
+
+	/* Ready for the next interrupt. */
+	T0_IR = portTIMER_MATCH_ISR_BIT;
+	VICVectAddr = portCLEAR_VIC_INTERRUPT;
+
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to
+ * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then
+ * the utilities are defined as macros in portmacro.h - as per other ports.
+ */
+#ifdef THUMB_INTERWORK
+
+	void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	void vPortDisableInterruptsFromThumb( void )
+	{
+		__asm volatile (
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.						*/
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+
+	void vPortEnableInterruptsFromThumb( void )
+	{
+		__asm volatile (
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.							*/
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+
+#endif /* THUMB_INTERWORK */
+
+/* The code generated by the GCC compiler uses the stack in different ways at
+different optimisation levels.  The interrupt flags can therefore not always
+be saved to the stack.  Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 							*/
+	__asm volatile (
+		"STMDB	SP!, {R0}			\n\t"	/* Push R0.								*/
+		"MRS	R0, CPSR			\n\t"	/* Get CPSR.							*/
+		"ORR	R0, R0, #0xC0		\n\t"	/* Disable IRQ, FIQ.					*/
+		"MSR	CPSR, R0			\n\t"	/* Write back modified value.			*/
+		"LDMIA	SP!, {R0}" );				/* Pop R0.								*/
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Enable interrupts as per portEXIT_CRITICAL().					*/
+			__asm volatile (
+				"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/
+				"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/
+				"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/
+				"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/
+				"LDMIA	SP!, {R0}" );			/* Pop R0.						*/
+		}
+	}
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/portmacro.h
new file mode 100644
index 0000000..758bc36
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/portmacro.h
@@ -0,0 +1,226 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	portLONG
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+#define portNOP()					__asm volatile ( "NOP" );
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+
+/*
+ * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
+ * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
+ * are included here for efficiency.  An attempt to call one from
+ * THUMB mode code will result in a compile time error.
+ */
+
+#define portRESTORE_CONTEXT()											\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile uint32_t ulCriticalNesting;					\
+																		\
+	/* Set the LR to the task stack. */									\
+	__asm volatile (													\
+	"LDR		R0, =pxCurrentTCB								\n\t"	\
+	"LDR		R0, [R0]										\n\t"	\
+	"LDR		LR, [R0]										\n\t"	\
+																		\
+	/* The critical nesting depth is the first item on the stack. */	\
+	/* Load it into the ulCriticalNesting variable. */					\
+	"LDR		R0, =ulCriticalNesting							\n\t"	\
+	"LDMFD	LR!, {R1}											\n\t"	\
+	"STR		R1, [R0]										\n\t"	\
+																		\
+	/* Get the SPSR from the stack. */									\
+	"LDMFD	LR!, {R0}											\n\t"	\
+	"MSR		SPSR, R0										\n\t"	\
+																		\
+	/* Restore all system mode registers for the task. */				\
+	"LDMFD	LR, {R0-R14}^										\n\t"	\
+	"NOP														\n\t"	\
+																		\
+	/* Restore the return address. */									\
+	"LDR		LR, [LR, #+60]									\n\t"	\
+																		\
+	/* And return - correcting the offset in the LR to obtain the */	\
+	/* correct address. */												\
+	"SUBS	PC, LR, #4											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+/*-----------------------------------------------------------*/
+
+#define portSAVE_CONTEXT()												\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile uint32_t ulCriticalNesting;					\
+																		\
+	/* Push R0 as we are going to use the register. */					\
+	__asm volatile (													\
+	"STMDB	SP!, {R0}											\n\t"	\
+																		\
+	/* Set R0 to point to the task stack pointer. */					\
+	"STMDB	SP,{SP}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	SP, SP, #4											\n\t"	\
+	"LDMIA	SP!,{R0}											\n\t"	\
+																		\
+	/* Push the return address onto the stack. */						\
+	"STMDB	R0!, {LR}											\n\t"	\
+																		\
+	/* Now we have saved LR we can use it instead of R0. */				\
+	"MOV	LR, R0												\n\t"	\
+																		\
+	/* Pop R0 so we can save it onto the system mode stack. */			\
+	"LDMIA	SP!, {R0}											\n\t"	\
+																		\
+	/* Push all the system mode registers onto the task stack. */		\
+	"STMDB	LR,{R0-LR}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	LR, LR, #60											\n\t"	\
+																		\
+	/* Push the SPSR onto the task stack. */							\
+	"MRS	R0, SPSR											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	"LDR	R0, =ulCriticalNesting								\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	/* Store the new top of stack for the task. */						\
+	"LDR	R0, =pxCurrentTCB									\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STR	LR, [R0]											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+
+extern void vTaskSwitchContext( void );
+#define portYIELD_FROM_ISR()		vTaskSwitchContext()
+#define portYIELD()					__asm volatile ( "SWI 0" )
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions in
+ * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not
+ * defined then the utilities are defined as macros here - as per other ports.
+ */
+
+#ifdef THUMB_INTERWORK
+
+	extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	#define portDISABLE_INTERRUPTS()	vPortDisableInterruptsFromThumb()
+	#define portENABLE_INTERRUPTS()		vPortEnableInterruptsFromThumb()
+
+#else
+
+	#define portDISABLE_INTERRUPTS()											\
+		__asm volatile (														\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.			*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+	#define portENABLE_INTERRUPTS()												\
+		__asm volatile (														\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+#endif /* THUMB_INTERWORK */
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/port.c
new file mode 100644
index 0000000..4930766
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/port.c
@@ -0,0 +1,233 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM7 port.
+ *
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in this file.  The ISR routines, which can only be compiled
+ * to ARM mode are contained in portISR.c.
+ *----------------------------------------------------------*/
+
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup the task context. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING	( ( StackType_t ) 0 )
+
+/* Constants required to setup the tick ISR. */
+#define portENABLE_TIMER                ( ( uint8_t ) 0x01 )
+#define portPRESCALE_VALUE              0x00
+#define portINTERRUPT_ON_MATCH          ( ( uint32_t ) 0x01 )
+#define portRESET_COUNT_ON_MATCH        ( ( uint32_t ) 0x02 )
+
+/* Constants required to setup the VIC for the tick ISR. */
+#define portTIMER_VIC_CHANNEL           ( ( uint32_t ) 0x0004 )
+#define portTIMER_VIC_CHANNEL_BIT       ( ( uint32_t ) 0x0010 )
+#define portTIMER_VIC_ENABLE            ( ( uint32_t ) 0x0020 )
+
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* 
+ * The scheduler can only be started from ARM mode, so 
+ * vPortISRStartFirstSTask() is defined in portISR.c. 
+ */
+extern void vPortISRStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+	
+	/* To ensure asserts in tasks.c don't fail, although in this case the assert
+	is not really required. */
+	pxTopOfStack--;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as 
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0x00000000;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The last thing onto the stack is the status register, which is set for
+	system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+
+	pxTopOfStack--;
+
+	/* Some optimisation levels use the stack differently to others.  This 
+	means the interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortISRStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the timer 0 to generate the tick interrupts at the required frequency.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+uint32_t ulCompareMatch;
+
+	PCLKSEL0 = (PCLKSEL0 & (~(0x3<<2))) | (0x01 << 2);
+	T0TCR  = 2;         /* Stop and reset the timer */
+	T0CTCR = 0;         /* Timer mode               */
+	
+	/* A 1ms tick does not require the use of the timer prescale.  This is
+	defaulted to zero but can be used if necessary. */
+	T0PR = portPRESCALE_VALUE;
+
+	/* Calculate the match value required for our wanted tick rate. */
+	ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+	/* Protect against divide by zero.  Using an if() statement still results
+	in a warning - hence the #if. */
+	#if portPRESCALE_VALUE != 0
+	{
+		ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
+	}
+	#endif
+	T0MR1 = ulCompareMatch;
+
+	/* Generate tick with timer 0 compare match. */
+	T0MCR  = (3 << 3);  /* Reset timer on match and generate interrupt */
+
+	/* Setup the VIC for the timer. */
+	VICIntEnable = 0x00000010;
+	
+	/* The ISR installed depends on whether the preemptive or cooperative
+	scheduler is being used. */
+	#if configUSE_PREEMPTION == 1
+	{
+		extern void ( vPreemptiveTick )( void );
+		VICVectAddr4 = ( int32_t ) vPreemptiveTick;
+	}
+	#else
+	{
+		extern void ( vNonPreemptiveTick )( void );
+		VICVectAddr4 = ( int32_t ) vNonPreemptiveTick;
+	}
+	#endif
+
+	VICVectCntl4 = 1;
+
+	/* Start the timer - interrupts are disabled when this function is called
+	so it is okay to do this here. */
+	T0TCR = portENABLE_TIMER;
+}
+/*-----------------------------------------------------------*/
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/portISR.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/portISR.c
new file mode 100644
index 0000000..74b5228
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/portISR.c
@@ -0,0 +1,218 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*-----------------------------------------------------------
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c  The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to handle interrupts. */
+#define portTIMER_MATCH_ISR_BIT		( ( uint8_t ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT		( ( uint32_t ) 0 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING		( ( uint32_t ) 0 )
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/*-----------------------------------------------------------*/
+
+/* ISR to handle manual context switches (from a call to taskYIELD()). */
+void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
+
+/* 
+ * The scheduler can only be started from ARM mode, hence the inclusion of this
+ * function here.
+ */
+void vPortISRStartFirstTask( void );
+/*-----------------------------------------------------------*/
+
+void vPortISRStartFirstTask( void )
+{
+	/* Simply start the scheduler.  This is included here as it can only be
+	called from ARM mode. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by portYIELD() or taskYIELD() to manually force a context switch.
+ *
+ * When a context switch is performed from the task level the saved task 
+ * context is made to look as if it occurred from within the tick ISR.  This
+ * way the same restore context function can be used when restoring the context
+ * saved from the ISR or that saved from a call to vPortYieldProcessor.
+ */
+void vPortYieldProcessor( void )
+{
+	/* Within an IRQ ISR the link register has an offset from the true return 
+	address, but an SWI ISR does not.  Add the offset manually so the same 
+	ISR return code can be used in both cases. */
+	__asm volatile ( "ADD		LR, LR, #4" );
+
+	/* Perform the context switch.  First save the context of the current task. */
+	portSAVE_CONTEXT();
+
+	/* Find the highest priority task that is ready to run. */
+	__asm volatile( "bl			vTaskSwitchContext" );
+
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT();	
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * The ISR used for the scheduler tick depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+
+
+#if configUSE_PREEMPTION == 0
+
+	/* The cooperative scheduler requires a normal IRQ service routine to 
+	simply increment the system tick. */
+	void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
+	void vNonPreemptiveTick( void )
+	{	
+		xTaskIncrementTick();
+		T0IR = 2;
+		VICVectAddr = portCLEAR_VIC_INTERRUPT;
+	}
+
+#else
+
+	/* The preemptive scheduler is defined as "naked" as the full context is
+	saved on entry as part of the context switch. */
+	void vPreemptiveTick( void ) __attribute__((naked));
+	void vPreemptiveTick( void )
+	{
+		/* Save the context of the interrupted task. */
+		portSAVE_CONTEXT();	
+
+		/* Increment the RTOS tick count, then look for the highest priority 
+		task that is ready to run. */
+		__asm volatile
+		(
+			"	bl xTaskIncrementTick	\t\n" \
+			"	cmp r0, #0				\t\n" \
+			"	beq SkipContextSwitch	\t\n" \
+			"	bl vTaskSwitchContext	\t\n" \
+			"SkipContextSwitch:			\t\n"
+		);
+
+		/* Ready for the next interrupt. */
+		T0IR = 2;
+		VICVectAddr = portCLEAR_VIC_INTERRUPT;
+		
+		/* Restore the context of the new task. */
+		portRESTORE_CONTEXT();
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to
+ * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then
+ * the utilities are defined as macros in portmacro.h - as per other ports.
+ */
+#ifdef THUMB_INTERWORK
+
+	void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	void vPortDisableInterruptsFromThumb( void )
+	{
+		__asm volatile ( 
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.						*/
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+			
+	void vPortEnableInterruptsFromThumb( void )
+	{
+		__asm volatile ( 
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/	
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/	
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.							*/	
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/	
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+
+#endif /* THUMB_INTERWORK */
+
+/* The code generated by the GCC compiler uses the stack in different ways at
+different optimisation levels.  The interrupt flags can therefore not always
+be saved to the stack.  Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 							*/
+	__asm volatile ( 
+		"STMDB	SP!, {R0}			\n\t"	/* Push R0.								*/
+		"MRS	R0, CPSR			\n\t"	/* Get CPSR.							*/
+		"ORR	R0, R0, #0xC0		\n\t"	/* Disable IRQ, FIQ.					*/
+		"MSR	CPSR, R0			\n\t"	/* Write back modified value.			*/
+		"LDMIA	SP!, {R0}" );				/* Pop R0.								*/
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed 
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Enable interrupts as per portEXIT_CRITICAL().					*/
+			__asm volatile ( 
+				"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	
+				"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	
+				"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	
+				"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	
+				"LDMIA	SP!, {R0}" );			/* Pop R0.						*/
+		}
+	}
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/portmacro.h
new file mode 100644
index 0000000..34838f9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/portmacro.h
@@ -0,0 +1,249 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+	Changes from V3.2.3
+
+	+ Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
+
+	Changes from V3.2.4
+
+	+ Removed the use of the %0 parameter within the assembler macros and
+	  replaced them with hard coded registers.  This will ensure the
+	  assembler does not select the link register as the temp register as
+	  was occasionally happening previously.
+
+	+ The assembler statements are now included in a single asm block rather
+	  than each line having its own asm block.
+
+	Changes from V4.5.0
+
+	+ Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
+	  and replaced them with portYIELD_FROM_ISR() macro.  Application code
+	  should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+	  macros as per the V4.5.1 demo code.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	portLONG
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+#define portNOP()					__asm volatile ( "NOP" );
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+
+/*
+ * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
+ * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
+ * are included here for efficiency.  An attempt to call one from
+ * THUMB mode code will result in a compile time error.
+ */
+
+#define portRESTORE_CONTEXT()											\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile uint32_t ulCriticalNesting;					\
+																		\
+	/* Set the LR to the task stack. */									\
+	__asm volatile (													\
+	"LDR		R0, =pxCurrentTCB								\n\t"	\
+	"LDR		R0, [R0]										\n\t"	\
+	"LDR		LR, [R0]										\n\t"	\
+																		\
+	/* The critical nesting depth is the first item on the stack. */	\
+	/* Load it into the ulCriticalNesting variable. */					\
+	"LDR		R0, =ulCriticalNesting							\n\t"	\
+	"LDMFD	LR!, {R1}											\n\t"	\
+	"STR		R1, [R0]										\n\t"	\
+																		\
+	/* Get the SPSR from the stack. */									\
+	"LDMFD	LR!, {R0}											\n\t"	\
+	"MSR		SPSR, R0										\n\t"	\
+																		\
+	/* Restore all system mode registers for the task. */				\
+	"LDMFD	LR, {R0-R14}^										\n\t"	\
+	"NOP														\n\t"	\
+																		\
+	/* Restore the return address. */									\
+	"LDR		LR, [LR, #+60]									\n\t"	\
+																		\
+	/* And return - correcting the offset in the LR to obtain the */	\
+	/* correct address. */												\
+	"SUBS	PC, LR, #4											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+/*-----------------------------------------------------------*/
+
+#define portSAVE_CONTEXT()												\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile uint32_t ulCriticalNesting;					\
+																		\
+	/* Push R0 as we are going to use the register. */					\
+	__asm volatile (													\
+	"STMDB	SP!, {R0}											\n\t"	\
+																		\
+	/* Set R0 to point to the task stack pointer. */					\
+	"STMDB	SP,{SP}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	SP, SP, #4											\n\t"	\
+	"LDMIA	SP!,{R0}											\n\t"	\
+																		\
+	/* Push the return address onto the stack. */						\
+	"STMDB	R0!, {LR}											\n\t"	\
+																		\
+	/* Now we have saved LR we can use it instead of R0. */				\
+	"MOV	LR, R0												\n\t"	\
+																		\
+	/* Pop R0 so we can save it onto the system mode stack. */			\
+	"LDMIA	SP!, {R0}											\n\t"	\
+																		\
+	/* Push all the system mode registers onto the task stack. */		\
+	"STMDB	LR,{R0-LR}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	LR, LR, #60											\n\t"	\
+																		\
+	/* Push the SPSR onto the task stack. */							\
+	"MRS	R0, SPSR											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	"LDR	R0, =ulCriticalNesting								\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	/* Store the new top of stack for the task. */						\
+	"LDR	R0, =pxCurrentTCB									\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STR	LR, [R0]											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+
+
+#define portYIELD_FROM_ISR()		vTaskSwitchContext()
+#define portYIELD()					__asm volatile ( "SWI 0" )
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions in
+ * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not
+ * defined then the utilities are defined as macros here - as per other ports.
+ */
+
+#ifdef THUMB_INTERWORK
+
+	extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	#define portDISABLE_INTERRUPTS()	vPortDisableInterruptsFromThumb()
+	#define portENABLE_INTERRUPTS()		vPortEnableInterruptsFromThumb()
+
+#else
+
+	#define portDISABLE_INTERRUPTS()											\
+		__asm volatile (															\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.			*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+	#define portENABLE_INTERRUPTS()												\
+		__asm volatile (															\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+#endif /* THUMB_INTERWORK */
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c
new file mode 100644
index 0000000..fdfae40
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c
@@ -0,0 +1,518 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
+	#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
+	#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configUNIQUE_INTERRUPT_PRIORITIES
+	#error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configSETUP_TICK_INTERRUPT
+	#error configSETUP_TICK_INTERRUPT() must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif /* configSETUP_TICK_INTERRUPT */
+
+#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/* In case security extensions are implemented. */
+#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+#endif
+
+/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
+portmacro.h. */
+#ifndef configCLEAR_TICK_INTERRUPT
+	#define configCLEAR_TICK_INTERRUPT()
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+this value. */
+#define portNO_CRITICAL_NESTING			( ( size_t ) 0 )
+
+/* In all GICs 255 can be written to the priority mask register to unmask all
+(but the lowest) interrupt priority. */
+#define portUNMASK_VALUE				( 0xFFUL )
+
+/* Tasks are not created with a floating point context, but can be given a
+floating point context after they have been created.  A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
+
+/* Constants required to setup the initial task context. */
+#define portSP_ELx						( ( StackType_t ) 0x01 )
+#define portSP_EL0						( ( StackType_t ) 0x00 )
+
+#if defined( GUEST )
+	#define portEL1						( ( StackType_t ) 0x04 )
+	#define portINITIAL_PSTATE				( portEL1 | portSP_EL0 )
+#else
+	#define portEL3						( ( StackType_t ) 0x0c )
+	/* At the time of writing, the BSP only supports EL3. */
+	#define portINITIAL_PSTATE			( portEL3 | portSP_EL0 )
+#endif
+
+
+/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
+point is zero. */
+#define portBINARY_POINT_BITS			( ( uint8_t ) 0x03 )
+
+/* Masks all bits in the APSR other than the mode bits. */
+#define portAPSR_MODE_BITS_MASK			( 0x0C )
+
+/* The I bit in the DAIF bits. */
+#define portDAIF_I						( 0x80 )
+
+/* Macro to unmask all interrupt priorities. */
+#define portCLEAR_INTERRUPT_MASK()									\
+{																	\
+	portDISABLE_INTERRUPTS();										\
+	portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;			\
+	__asm volatile (	"DSB SY		\n"								\
+						"ISB SY		\n" );							\
+	portENABLE_INTERRUPTS();										\
+}
+
+/* Hardware specifics used when sanity checking the configuration. */
+#define portINTERRUPT_PRIORITY_REGISTER_OFFSET		0x400UL
+#define portMAX_8_BIT_VALUE							( ( uint8_t ) 0xff )
+#define portBIT_0_SET								( ( uint8_t ) 0x01 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing.  This function is necessarily written in
+ * assembly code so is implemented in portASM.s.
+ */
+extern void vPortRestoreTaskContext( void );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting.  This
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts.  As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
+volatile uint64_t ullCriticalNesting = 9999ULL;
+
+/* Saved as part of the task context.  If ullPortTaskHasFPUContext is non-zero
+then floating point context must be saved and restored for the task. */
+uint64_t ullPortTaskHasFPUContext = pdFALSE;
+
+/* Set to 1 to pend a context switch from an ISR. */
+uint64_t ullPortYieldRequired = pdFALSE;
+
+/* Counts the interrupt nesting depth.  A context switch is only performed if
+if the nesting depth is 0. */
+uint64_t ullPortInterruptNesting = 0;
+
+/* Used in the ASM code. */
+__attribute__(( used )) const uint64_t ullICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
+__attribute__(( used )) const uint64_t ullICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
+__attribute__(( used )) const uint64_t ullICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
+__attribute__(( used )) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First all the general purpose registers. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x0101010101010101ULL;	/* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x0303030303030303ULL;	/* R3 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x0202020202020202ULL;	/* R2 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x0505050505050505ULL;	/* R5 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x0404040404040404ULL;	/* R4 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x0707070707070707ULL;	/* R7 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x0606060606060606ULL;	/* R6 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x0909090909090909ULL;	/* R9 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x0808080808080808ULL;	/* R8 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x1111111111111111ULL;	/* R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x1010101010101010ULL;	/* R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x1313131313131313ULL;	/* R13 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x1212121212121212ULL;	/* R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x1515151515151515ULL;	/* R15 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x1414141414141414ULL;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x1717171717171717ULL;	/* R17 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x1616161616161616ULL;	/* R16 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x1919191919191919ULL;	/* R19 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x1818181818181818ULL;	/* R18 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2121212121212121ULL;	/* R21 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2020202020202020ULL;	/* R20 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2323232323232323ULL;	/* R23 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2222222222222222ULL;	/* R22 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2525252525252525ULL;	/* R25 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2424242424242424ULL;	/* R24 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2727272727272727ULL;	/* R27 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2626262626262626ULL;	/* R26 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2929292929292929ULL;	/* R29 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2828282828282828ULL;	/* R28 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00;	/* XZR - has no effect, used so there are an even number of registers. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00;	/* R30 - procedure call link register. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = portINITIAL_PSTATE;
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */
+	pxTopOfStack--;
+
+	/* The task will start with a critical nesting count of 0 as interrupts are
+	enabled. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+	pxTopOfStack--;
+
+	/* The task will start without a floating point context.  A task that uses
+	the floating point hardware must call vPortTaskUsesFPU() before executing
+	any floating point instructions. */
+	*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+uint32_t ulAPSR;
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine how many priority bits are implemented in the GIC.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to
+		all possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Shift to the least significant bits. */
+		while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
+		{
+			ucMaxPriorityValue >>= ( uint8_t ) 0x01;
+		}
+
+		/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
+		value. */
+
+		configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY );
+
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+
+	/* At the time of writing, the BSP only supports EL3. */
+	__asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) );
+	ulAPSR &= portAPSR_MODE_BITS_MASK;
+
+#if defined( GUEST )
+	#warning Building for execution as a guest under XEN. THIS IS NOT A FULLY TESTED PATH.
+	configASSERT( ulAPSR == portEL1 );
+	if( ulAPSR == portEL1 )
+#else
+	configASSERT( ulAPSR == portEL3 );
+	if( ulAPSR == portEL3 )
+#endif
+	{
+		/* Only continue if the binary point value is set to its lowest possible
+		setting.  See the comments in vPortValidateInterruptPriority() below for
+		more information. */
+		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+
+		if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
+		{
+			/* Interrupts are turned off in the CPU itself to ensure a tick does
+			not execute	while the scheduler is being started.  Interrupts are
+			automatically turned back on in the CPU when the first task starts
+			executing. */
+			portDISABLE_INTERRUPTS();
+
+			/* Start the timer that generates the tick ISR. */
+			configSETUP_TICK_INTERRUPT();
+
+			/* Start the first task executing. */
+			vPortRestoreTaskContext();
+		}
+	}
+
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( ullCriticalNesting == 1000ULL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	/* Mask interrupts up to the max syscall interrupt priority. */
+	uxPortSetInterruptMask();
+
+	/* Now interrupts are disabled ullCriticalNesting can be accessed
+	directly.  Increment ullCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ullCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( ullCriticalNesting == 1ULL )
+	{
+		configASSERT( ullPortInterruptNesting == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ullCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as the critical section is being
+		exited. */
+		ullCriticalNesting--;
+
+		/* If the nesting level has reached zero then all interrupt
+		priorities must be re-enabled. */
+		if( ullCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Critical nesting has reached zero so all interrupt priorities
+			should be unmasked. */
+			portCLEAR_INTERRUPT_MASK();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void FreeRTOS_Tick_Handler( void )
+{
+	/* Must be the lowest possible priority. */
+	#if !defined( QEMU )
+	{
+		configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER == ( uint32_t ) ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+	}
+	#endif
+
+	/* Interrupts should not be enabled before this point. */
+	#if( configASSERT_DEFINED == 1 )
+	{
+		uint32_t ulMaskBits;
+
+		__asm volatile( "mrs %0, daif" : "=r"( ulMaskBits ) :: "memory" );
+		configASSERT( ( ulMaskBits & portDAIF_I ) != 0 );
+	}
+	#endif /* configASSERT_DEFINED */
+
+	/* Set interrupt mask before altering scheduler structures.   The tick
+	handler runs at the lowest priority, so interrupts cannot already be masked,
+	so there is no need to save and restore the current mask value.  It is
+	necessary to turn off interrupts in the CPU itself while the ICCPMR is being
+	updated. */
+	portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+	__asm volatile (	"dsb sy		\n"
+						"isb sy		\n" ::: "memory" );
+
+	/* Ok to enable interrupts after the interrupt source has been cleared. */
+	configCLEAR_TICK_INTERRUPT();
+	portENABLE_INTERRUPTS();
+
+	/* Increment the RTOS tick. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		ullPortYieldRequired = pdTRUE;
+	}
+
+	/* Ensure all interrupt priorities are active again. */
+	portCLEAR_INTERRUPT_MASK();
+}
+/*-----------------------------------------------------------*/
+
+void vPortTaskUsesFPU( void )
+{
+	/* A task is registering the fact that it needs an FPU context.  Set the
+	FPU flag (which is saved as part of the task context). */
+	ullPortTaskHasFPUContext = pdTRUE;
+
+	/* Consider initialising the FPSR here - but probably not necessary in
+	AArch64. */
+}
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMask( UBaseType_t uxNewMaskValue )
+{
+	if( uxNewMaskValue == pdFALSE )
+	{
+		portCLEAR_INTERRUPT_MASK();
+	}
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxPortSetInterruptMask( void )
+{
+uint32_t ulReturn;
+
+	/* Interrupt in the CPU must be turned off while the ICCPMR is being
+	updated. */
+	portDISABLE_INTERRUPTS();
+	if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
+	{
+		/* Interrupts were already masked. */
+		ulReturn = pdTRUE;
+	}
+	else
+	{
+		ulReturn = pdFALSE;
+		portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+		__asm volatile (	"dsb sy		\n"
+							"isb sy		\n" ::: "memory" );
+	}
+	portENABLE_INTERRUPTS();
+
+	return ulReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+		/* The following assertion will fail if a service routine (ISR) for
+		an interrupt that has been assigned a priority above
+		configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+		function.  ISR safe FreeRTOS API functions must *only* be called
+		from interrupts that have been assigned a priority at or below
+		configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+		Numerically low interrupt priority numbers represent logically high
+		interrupt priorities, therefore the priority of the interrupt must
+		be set to a value equal to or numerically *higher* than
+		configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+		FreeRTOS maintains separate thread and ISR API functions to ensure
+		interrupt entry is as fast and simple as possible. */
+		configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+
+		/* Priority grouping:  The interrupt controller (GIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		The priority grouping is configured by the GIC's binary point register
+		(ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
+		possible value (which may be above 0). */
+		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+	}
+
+#endif /* configASSERT_DEFINED */
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portASM.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portASM.S
new file mode 100644
index 0000000..1b1609a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portASM.S
@@ -0,0 +1,431 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	.text
+
+	/* Variables and functions. */
+	.extern ullMaxAPIPriorityMask
+	.extern pxCurrentTCB
+	.extern vTaskSwitchContext
+	.extern vApplicationIRQHandler
+	.extern ullPortInterruptNesting
+	.extern ullPortTaskHasFPUContext
+	.extern ullCriticalNesting
+	.extern ullPortYieldRequired
+	.extern ullICCEOIR
+	.extern ullICCIAR
+	.extern _freertos_vector_table
+
+	.global FreeRTOS_IRQ_Handler
+	.global FreeRTOS_SWI_Handler
+	.global vPortRestoreTaskContext
+
+
+.macro portSAVE_CONTEXT
+
+	/* Switch to use the EL0 stack pointer. */
+	MSR 	SPSEL, #0
+
+	/* Save the entire context. */
+	STP 	X0, X1, [SP, #-0x10]!
+	STP 	X2, X3, [SP, #-0x10]!
+	STP 	X4, X5, [SP, #-0x10]!
+	STP 	X6, X7, [SP, #-0x10]!
+	STP 	X8, X9, [SP, #-0x10]!
+	STP 	X10, X11, [SP, #-0x10]!
+	STP 	X12, X13, [SP, #-0x10]!
+	STP 	X14, X15, [SP, #-0x10]!
+	STP 	X16, X17, [SP, #-0x10]!
+	STP 	X18, X19, [SP, #-0x10]!
+	STP 	X20, X21, [SP, #-0x10]!
+	STP 	X22, X23, [SP, #-0x10]!
+	STP 	X24, X25, [SP, #-0x10]!
+	STP 	X26, X27, [SP, #-0x10]!
+	STP 	X28, X29, [SP, #-0x10]!
+	STP 	X30, XZR, [SP, #-0x10]!
+
+	/* Save the SPSR. */
+#if defined( GUEST )
+	MRS		X3, SPSR_EL1
+	MRS		X2, ELR_EL1
+#else
+	MRS		X3, SPSR_EL3
+	/* Save the ELR. */
+	MRS		X2, ELR_EL3
+#endif
+
+	STP 	X2, X3, [SP, #-0x10]!
+
+	/* Save the critical section nesting depth. */
+	LDR		X0, ullCriticalNestingConst
+	LDR		X3, [X0]
+
+	/* Save the FPU context indicator. */
+	LDR		X0, ullPortTaskHasFPUContextConst
+	LDR		X2, [X0]
+
+	/* Save the FPU context, if any (32 128-bit registers). */
+	CMP		X2, #0
+	B.EQ	1f
+	STP		Q0, Q1, [SP,#-0x20]!
+	STP		Q2, Q3, [SP,#-0x20]!
+	STP		Q4, Q5, [SP,#-0x20]!
+	STP		Q6, Q7, [SP,#-0x20]!
+	STP		Q8, Q9, [SP,#-0x20]!
+	STP		Q10, Q11, [SP,#-0x20]!
+	STP		Q12, Q13, [SP,#-0x20]!
+	STP		Q14, Q15, [SP,#-0x20]!
+	STP		Q16, Q17, [SP,#-0x20]!
+	STP		Q18, Q19, [SP,#-0x20]!
+	STP		Q20, Q21, [SP,#-0x20]!
+	STP		Q22, Q23, [SP,#-0x20]!
+	STP		Q24, Q25, [SP,#-0x20]!
+	STP		Q26, Q27, [SP,#-0x20]!
+	STP		Q28, Q29, [SP,#-0x20]!
+	STP		Q30, Q31, [SP,#-0x20]!
+
+1:
+	/* Store the critical nesting count and FPU context indicator. */
+	STP 	X2, X3, [SP, #-0x10]!
+
+	LDR 	X0, pxCurrentTCBConst
+	LDR 	X1, [X0]
+	MOV 	X0, SP   /* Move SP into X0 for saving. */
+	STR 	X0, [X1]
+
+	/* Switch to use the ELx stack pointer. */
+	MSR 	SPSEL, #1
+
+	.endm
+
+; /**********************************************************************/
+
+.macro portRESTORE_CONTEXT
+
+	/* Switch to use the EL0 stack pointer. */
+	MSR 	SPSEL, #0
+
+	/* Set the SP to point to the stack of the task being restored. */
+	LDR		X0, pxCurrentTCBConst
+	LDR		X1, [X0]
+	LDR		X0, [X1]
+	MOV		SP, X0
+
+	LDP 	X2, X3, [SP], #0x10  /* Critical nesting and FPU context. */
+
+	/* Set the PMR register to be correct for the current critical nesting
+	depth. */
+	LDR		X0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */
+	MOV		X1, #255					/* X1 holds the unmask value. */
+	LDR		X4, ullICCPMRConst			/* X4 holds the address of the ICCPMR constant. */
+	CMP		X3, #0
+	LDR		X5, [X4] 					/* X5 holds the address of the ICCPMR register. */
+	B.EQ	1f
+	LDR		X6, ullMaxAPIPriorityMaskConst
+	LDR		X1, [X6]					/* X1 holds the mask value. */
+1:
+	STR		W1, [X5]					/* Write the mask value to ICCPMR. */
+	DSB 	SY							/* _RB_Barriers probably not required here. */
+	ISB 	SY
+	STR		X3, [X0]					/* Restore the task's critical nesting count. */
+
+	/* Restore the FPU context indicator. */
+	LDR		X0, ullPortTaskHasFPUContextConst
+	STR		X2, [X0]
+
+	/* Restore the FPU context, if any. */
+	CMP		X2, #0
+	B.EQ	1f
+	LDP		Q30, Q31, [SP], #0x20
+	LDP		Q28, Q29, [SP], #0x20
+	LDP		Q26, Q27, [SP], #0x20
+	LDP		Q24, Q25, [SP], #0x20
+	LDP		Q22, Q23, [SP], #0x20
+	LDP		Q20, Q21, [SP], #0x20
+	LDP		Q18, Q19, [SP], #0x20
+	LDP		Q16, Q17, [SP], #0x20
+	LDP		Q14, Q15, [SP], #0x20
+	LDP		Q12, Q13, [SP], #0x20
+	LDP		Q10, Q11, [SP], #0x20
+	LDP		Q8, Q9, [SP], #0x20
+	LDP		Q6, Q7, [SP], #0x20
+	LDP		Q4, Q5, [SP], #0x20
+	LDP		Q2, Q3, [SP], #0x20
+	LDP		Q0, Q1, [SP], #0x20
+1:
+	LDP 	X2, X3, [SP], #0x10  /* SPSR and ELR. */
+
+#if defined( GUEST )
+	/* Restore the SPSR. */
+	MSR		SPSR_EL1, X3
+	/* Restore the ELR. */
+	MSR		ELR_EL1, X2
+#else
+	/* Restore the SPSR. */
+	MSR		SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */
+	/* Restore the ELR. */
+	MSR		ELR_EL3, X2
+#endif
+
+	LDP 	X30, XZR, [SP], #0x10
+	LDP 	X28, X29, [SP], #0x10
+	LDP 	X26, X27, [SP], #0x10
+	LDP 	X24, X25, [SP], #0x10
+	LDP 	X22, X23, [SP], #0x10
+	LDP 	X20, X21, [SP], #0x10
+	LDP 	X18, X19, [SP], #0x10
+	LDP 	X16, X17, [SP], #0x10
+	LDP 	X14, X15, [SP], #0x10
+	LDP 	X12, X13, [SP], #0x10
+	LDP 	X10, X11, [SP], #0x10
+	LDP 	X8, X9, [SP], #0x10
+	LDP 	X6, X7, [SP], #0x10
+	LDP 	X4, X5, [SP], #0x10
+	LDP 	X2, X3, [SP], #0x10
+	LDP 	X0, X1, [SP], #0x10
+
+	/* Switch to use the ELx stack pointer.  _RB_ Might not be required. */
+	MSR 	SPSEL, #1
+
+	ERET
+
+	.endm
+
+
+/******************************************************************************
+ * FreeRTOS_SWI_Handler handler is used to perform a context switch.
+ *****************************************************************************/
+.align 8
+.type FreeRTOS_SWI_Handler, %function
+FreeRTOS_SWI_Handler:
+	/* Save the context of the current task and select a new task to run. */
+	portSAVE_CONTEXT
+#if defined( GUEST )
+	MRS		X0, ESR_EL1
+#else
+	MRS		X0, ESR_EL3
+#endif
+
+	LSR		X1, X0, #26
+
+#if defined( GUEST )
+	CMP		X1, #0x15 	/* 0x15 = SVC instruction. */
+#else
+	CMP		X1, #0x17 	/* 0x17 = SMC instruction. */
+#endif
+	B.NE	FreeRTOS_Abort
+	BL 		vTaskSwitchContext
+
+	portRESTORE_CONTEXT
+
+FreeRTOS_Abort:
+	/* Full ESR is in X0, exception class code is in X1. */
+	B		.
+
+/******************************************************************************
+ * vPortRestoreTaskContext is used to start the scheduler.
+ *****************************************************************************/
+.align 8
+.type vPortRestoreTaskContext, %function
+vPortRestoreTaskContext:
+.set freertos_vector_base,	_freertos_vector_table
+
+	/* Install the FreeRTOS interrupt handlers. */
+	LDR		X1, =freertos_vector_base
+#if defined( GUEST )
+	MSR		VBAR_EL1, X1
+#else
+	MSR		VBAR_EL3, X1
+#endif
+	DSB		SY
+	ISB		SY
+
+	/* Start the first task. */
+	portRESTORE_CONTEXT
+
+
+/******************************************************************************
+ * FreeRTOS_IRQ_Handler handles IRQ entry and exit.
+ *****************************************************************************/
+.align 8
+.type FreeRTOS_IRQ_Handler, %function
+FreeRTOS_IRQ_Handler:
+	/* Save volatile registers. */
+	STP		X0, X1, [SP, #-0x10]!
+	STP		X2, X3, [SP, #-0x10]!
+	STP		X4, X5, [SP, #-0x10]!
+	STP		X6, X7, [SP, #-0x10]!
+	STP		X8, X9, [SP, #-0x10]!
+	STP		X10, X11, [SP, #-0x10]!
+	STP		X12, X13, [SP, #-0x10]!
+	STP		X14, X15, [SP, #-0x10]!
+	STP		X16, X17, [SP, #-0x10]!
+	STP		X18, X19, [SP, #-0x10]!
+	STP		X29, X30, [SP, #-0x10]!
+
+	/* Save the SPSR and ELR. */
+#if defined( GUEST )
+	MRS		X3, SPSR_EL1
+	MRS		X2, ELR_EL1
+#else
+	MRS		X3, SPSR_EL3
+	MRS		X2, ELR_EL3
+#endif
+	STP 	X2, X3, [SP, #-0x10]!
+
+	/* Increment the interrupt nesting counter. */
+	LDR		X5, ullPortInterruptNestingConst
+	LDR		X1, [X5]	/* Old nesting count in X1. */
+	ADD		X6, X1, #1
+	STR		X6, [X5]	/* Address of nesting count variable in X5. */
+
+	/* Maintain the interrupt nesting information across the function call. */
+	STP		X1, X5, [SP, #-0x10]!
+
+	/* Read value from the interrupt acknowledge register, which is stored in W0
+	for future parameter and interrupt clearing use. */
+	LDR 	X2, ullICCIARConst
+	LDR		X3, [X2]
+	LDR		W0, [X3]	/* ICCIAR in W0 as parameter. */
+
+	/* Maintain the ICCIAR value across the function call. */
+	STP		X0, X1, [SP, #-0x10]!
+
+	/* Call the C handler. */
+	BL vApplicationIRQHandler
+
+	/* Disable interrupts. */
+	MSR 	DAIFSET, #2
+	DSB		SY
+	ISB		SY
+
+	/* Restore the ICCIAR value. */
+	LDP		X0, X1, [SP], #0x10
+
+	/* End IRQ processing by writing ICCIAR to the EOI register. */
+	LDR 	X4, ullICCEOIRConst
+	LDR		X4, [X4]
+	STR		W0, [X4]
+
+	/* Restore the critical nesting count. */
+	LDP		X1, X5, [SP], #0x10
+	STR		X1, [X5]
+
+	/* Has interrupt nesting unwound? */
+	CMP		X1, #0
+	B.NE	Exit_IRQ_No_Context_Switch
+
+	/* Is a context switch required? */
+	LDR		X0, ullPortYieldRequiredConst
+	LDR		X1, [X0]
+	CMP		X1, #0
+	B.EQ	Exit_IRQ_No_Context_Switch
+
+	/* Reset ullPortYieldRequired to 0. */
+	MOV		X2, #0
+	STR		X2, [X0]
+
+	/* Restore volatile registers. */
+	LDP 	X4, X5, [SP], #0x10  /* SPSR and ELR. */
+#if defined( GUEST )
+	MSR		SPSR_EL1, X5
+	MSR		ELR_EL1, X4
+#else
+	MSR		SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
+	MSR		ELR_EL3, X4
+#endif
+	DSB		SY
+	ISB		SY
+
+	LDP		X29, X30, [SP], #0x10
+	LDP		X18, X19, [SP], #0x10
+	LDP		X16, X17, [SP], #0x10
+	LDP		X14, X15, [SP], #0x10
+	LDP		X12, X13, [SP], #0x10
+	LDP		X10, X11, [SP], #0x10
+	LDP		X8, X9, [SP], #0x10
+	LDP		X6, X7, [SP], #0x10
+	LDP		X4, X5, [SP], #0x10
+	LDP		X2, X3, [SP], #0x10
+	LDP		X0, X1, [SP], #0x10
+
+	/* Save the context of the current task and select a new task to run. */
+	portSAVE_CONTEXT
+	BL vTaskSwitchContext
+	portRESTORE_CONTEXT
+
+Exit_IRQ_No_Context_Switch:
+	/* Restore volatile registers. */
+	LDP 	X4, X5, [SP], #0x10  /* SPSR and ELR. */
+#if defined( GUEST )
+	MSR		SPSR_EL1, X5
+	MSR		ELR_EL1, X4
+#else
+	MSR		SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
+	MSR		ELR_EL3, X4
+#endif
+	DSB		SY
+	ISB		SY
+
+	LDP		X29, X30, [SP], #0x10
+	LDP		X18, X19, [SP], #0x10
+	LDP		X16, X17, [SP], #0x10
+	LDP		X14, X15, [SP], #0x10
+	LDP		X12, X13, [SP], #0x10
+	LDP		X10, X11, [SP], #0x10
+	LDP		X8, X9, [SP], #0x10
+	LDP		X6, X7, [SP], #0x10
+	LDP		X4, X5, [SP], #0x10
+	LDP		X2, X3, [SP], #0x10
+	LDP		X0, X1, [SP], #0x10
+
+	ERET
+
+
+
+
+.align 8
+pxCurrentTCBConst: .dword pxCurrentTCB
+ullCriticalNestingConst: .dword ullCriticalNesting
+ullPortTaskHasFPUContextConst: .dword ullPortTaskHasFPUContext
+
+ullICCPMRConst: .dword ullICCPMR
+ullMaxAPIPriorityMaskConst: .dword ullMaxAPIPriorityMask
+vApplicationIRQHandlerConst: .word vApplicationIRQHandler
+ullPortInterruptNestingConst: .dword ullPortInterruptNesting
+ullPortYieldRequiredConst: .dword ullPortYieldRequired
+ullICCIARConst:	.dword ullICCIAR
+ullICCEOIRConst: .dword ullICCEOIR
+
+
+
+.end
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h
new file mode 100644
index 0000000..50d154a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h
@@ -0,0 +1,211 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+	extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	size_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef portBASE_TYPE BaseType_t;
+typedef uint64_t UBaseType_t;
+
+typedef uint64_t TickType_t;
+#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff )
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			16
+#define portPOINTER_SIZE_TYPE 		uint64_t
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* Called at the end of an ISR that can cause a context switch. */
+#define portEND_SWITCHING_ISR( xSwitchRequired )\
+{												\
+extern uint64_t ullPortYieldRequired;			\
+												\
+	if( xSwitchRequired != pdFALSE )			\
+	{											\
+		ullPortYieldRequired = pdTRUE;			\
+	}											\
+}
+
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#if defined( GUEST )
+	#define portYIELD() __asm volatile ( "SVC 0" ::: "memory" )
+#else
+	#define portYIELD() __asm volatile ( "SMC 0" ::: "memory" )
+#endif
+/*-----------------------------------------------------------
+ * Critical section control
+ *----------------------------------------------------------*/
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern UBaseType_t uxPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue );
+extern void vPortInstallFreeRTOSVectorTable( void );
+
+#define portDISABLE_INTERRUPTS()									\
+	__asm volatile ( "MSR DAIFSET, #2" ::: "memory" );				\
+	__asm volatile ( "DSB SY" );									\
+	__asm volatile ( "ISB SY" );
+
+#define portENABLE_INTERRUPTS()										\
+	__asm volatile ( "MSR DAIFCLR, #2" ::: "memory" );				\
+	__asm volatile ( "DSB SY" );									\
+	__asm volatile ( "ISB SY" );
+
+
+/* These macros do not globally disable/enable interrupts.  They do mask off
+interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+#define portSET_INTERRUPT_MASK_FROM_ISR()		uxPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask(x)
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
+
+/* Prototype of the FreeRTOS tick handler.  This must be installed as the
+handler for whichever peripheral is used to generate the RTOS tick. */
+void FreeRTOS_Tick_Handler( void );
+
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+before any floating point instructions are executed. */
+void vPortTaskUsesFPU( void );
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif /* configASSERT */
+
+#define portNOP() __asm volatile( "NOP" )
+#define portINLINE __inline
+
+#ifdef __cplusplus
+	} /* extern C */
+#endif
+
+
+/* The number of bits to shift for an interrupt priority is dependent on the
+number of bits implemented by the interrupt controller. */
+#if configUNIQUE_INTERRUPT_PRIORITIES == 16
+	#define portPRIORITY_SHIFT 4
+	#define portMAX_BINARY_POINT_VALUE	3
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
+	#define portPRIORITY_SHIFT 3
+	#define portMAX_BINARY_POINT_VALUE	2
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
+	#define portPRIORITY_SHIFT 2
+	#define portMAX_BINARY_POINT_VALUE	1
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
+	#define portPRIORITY_SHIFT 1
+	#define portMAX_BINARY_POINT_VALUE	0
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
+	#define portPRIORITY_SHIFT 0
+	#define portMAX_BINARY_POINT_VALUE	0
+#else
+	#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
+#endif
+
+/* Interrupt controller access addresses. */
+#define portICCPMR_PRIORITY_MASK_OFFSET  						( 0x04 )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET 				( 0x0C )
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET 					( 0x10 )
+#define portICCBPR_BINARY_POINT_OFFSET							( 0x08 )
+#define portICCRPR_RUNNING_PRIORITY_OFFSET						( 0x14 )
+
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS 		( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER 					( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS 	( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS 		( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS 			( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+#define portICCBPR_BINARY_POINT_REGISTER 					( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+#define portICCRPR_RUNNING_PRIORITY_REGISTER 				( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CA9/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CA9/port.c
new file mode 100644
index 0000000..f8c9572
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CA9/port.c
@@ -0,0 +1,568 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
+	#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
+	#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configUNIQUE_INTERRUPT_PRIORITIES
+	#error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configSETUP_TICK_INTERRUPT
+	#error configSETUP_TICK_INTERRUPT() must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif /* configSETUP_TICK_INTERRUPT */
+
+#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/* In case security extensions are implemented. */
+#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+#endif
+
+/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
+portmacro.h. */
+#ifndef configCLEAR_TICK_INTERRUPT
+	#define configCLEAR_TICK_INTERRUPT()
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+this value. */
+#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
+
+/* In all GICs 255 can be written to the priority mask register to unmask all
+(but the lowest) interrupt priority. */
+#define portUNMASK_VALUE				( 0xFFUL )
+
+/* Tasks are not created with a floating point context, but can be given a
+floating point context after they have been created.  A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
+
+/* Constants required to setup the initial task context. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portINTERRUPT_ENABLE_BIT		( 0x80UL )
+#define portTHUMB_MODE_ADDRESS			( 0x01UL )
+
+/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
+point is zero. */
+#define portBINARY_POINT_BITS			( ( uint8_t ) 0x03 )
+
+/* Masks all bits in the APSR other than the mode bits. */
+#define portAPSR_MODE_BITS_MASK			( 0x1F )
+
+/* The value of the mode bits in the APSR when the CPU is executing in user
+mode. */
+#define portAPSR_USER_MODE				( 0x10 )
+
+/* The critical section macros only mask interrupts up to an application
+determined priority level.  Sometimes it is necessary to turn interrupt off in
+the CPU itself before modifying certain hardware registers. */
+#define portCPU_IRQ_DISABLE()										\
+	__asm volatile ( "CPSID i" ::: "memory" );						\
+	__asm volatile ( "DSB" );										\
+	__asm volatile ( "ISB" );
+
+#define portCPU_IRQ_ENABLE()										\
+	__asm volatile ( "CPSIE i" ::: "memory" );						\
+	__asm volatile ( "DSB" );										\
+	__asm volatile ( "ISB" );
+
+
+/* Macro to unmask all interrupt priorities. */
+#define portCLEAR_INTERRUPT_MASK()									\
+{																	\
+	portCPU_IRQ_DISABLE();											\
+	portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;			\
+	__asm volatile (	"DSB		\n"								\
+						"ISB		\n" );							\
+	portCPU_IRQ_ENABLE();											\
+}
+
+#define portINTERRUPT_PRIORITY_REGISTER_OFFSET		0x400UL
+#define portMAX_8_BIT_VALUE							( ( uint8_t ) 0xff )
+#define portBIT_0_SET								( ( uint8_t ) 0x01 )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/* The space on the stack required to hold the FPU registers.  This is 32 64-bit
+registers, plus a 32-bit status register. */
+#define portFPU_REGISTER_WORDS	( ( 32 * 2 ) + 1 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing.  This function is necessarily written in
+ * assembly code so is implemented in portASM.s.
+ */
+extern void vPortRestoreTaskContext( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*
+ * If the application provides an implementation of vApplicationIRQHandler(),
+ * then it will get called directly without saving the FPU registers on
+ * interrupt entry, and this weak implementation of
+ * vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors -
+ * it should never actually get called so its implementation contains a
+ * call to configASSERT() that will always fail.
+ *
+ * If the application provides its own implementation of
+ * vApplicationFPUSafeIRQHandler() then the implementation of
+ * vApplicationIRQHandler() provided in portASM.S will save the FPU registers
+ * before calling it.
+ *
+ * Therefore, if the application writer wants FPU registers to be saved on
+ * interrupt entry their IRQ handler must be called
+ * vApplicationFPUSafeIRQHandler(), and if the application writer does not want
+ * FPU registers to be saved on interrupt entry their IRQ handler must be
+ * called vApplicationIRQHandler().
+ */
+void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__((weak) );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting.  This
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts.  As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then
+a floating point context must be saved and restored for the task. */
+volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
+
+/* Set to 1 to pend a context switch from an ISR. */
+volatile uint32_t ulPortYieldRequired = pdFALSE;
+
+/* Counts the interrupt nesting depth.  A context switch is only performed if
+if the nesting depth is 0. */
+volatile uint32_t ulPortInterruptNesting = 0UL;
+
+/* Used in the asm file. */
+__attribute__(( used )) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
+__attribute__(( used )) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
+__attribute__(( used )) const uint32_t ulICCPMR	= portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
+__attribute__(( used )) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro.
+
+	The fist real value on the stack is the status register, which is set for
+	system mode, with interrupts enabled.  A few NULLs are added first to ensure
+	GDB does not try decoding a non-existent return address. */
+	*pxTopOfStack = ( StackType_t ) NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+	{
+		/* The task will start in THUMB mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+
+	pxTopOfStack--;
+
+	/* Next the return address, which in this case is the start of the task. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+
+	/* Next all the registers other than the stack pointer. */
+	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The task will start with a critical nesting count of 0 as interrupts are
+	enabled. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+
+	#if( configUSE_TASK_FPU_SUPPORT == 1 )
+	{
+		/* The task will start without a floating point context.  A task that
+		uses the floating point hardware must call vPortTaskUsesFPU() before
+		executing any floating point instructions. */
+		pxTopOfStack--;
+		*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+	}
+	#elif( configUSE_TASK_FPU_SUPPORT == 2 )
+	{
+		/* The task will start with a floating point context.  Leave enough
+		space for the registers - and ensure they are initialised to 0. */
+		pxTopOfStack -= portFPU_REGISTER_WORDS;
+		memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
+
+		pxTopOfStack--;
+		*pxTopOfStack = pdTRUE;
+		ulPortTaskHasFPUContext = pdTRUE;
+	}
+	#else
+	{
+		#error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined.
+	}
+	#endif
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( ulPortInterruptNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+uint32_t ulAPSR;
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine how many priority bits are implemented in the GIC.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to
+		all possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Shift to the least significant bits. */
+		while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
+		{
+			ucMaxPriorityValue >>= ( uint8_t ) 0x01;
+		}
+
+		/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
+		value. */
+		configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+
+	/* Only continue if the CPU is not in User mode.  The CPU must be in a
+	Privileged mode for the scheduler to start. */
+	__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );
+	ulAPSR &= portAPSR_MODE_BITS_MASK;
+	configASSERT( ulAPSR != portAPSR_USER_MODE );
+
+	if( ulAPSR != portAPSR_USER_MODE )
+	{
+		/* Only continue if the binary point value is set to its lowest possible
+		setting.  See the comments in vPortValidateInterruptPriority() below for
+		more information. */
+		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+
+		if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
+		{
+			/* Interrupts are turned off in the CPU itself to ensure tick does
+			not execute	while the scheduler is being started.  Interrupts are
+			automatically turned back on in the CPU when the first task starts
+			executing. */
+			portCPU_IRQ_DISABLE();
+
+			/* Start the timer that generates the tick ISR. */
+			configSETUP_TICK_INTERRUPT();
+
+			/* Start the first task executing. */
+			vPortRestoreTaskContext();
+		}
+	}
+
+	/* Will only get here if vTaskStartScheduler() was called with the CPU in
+	a non-privileged mode or the binary point register was not set to its lowest
+	possible value.  prvTaskExitError() is referenced to prevent a compiler
+	warning about it being defined but not referenced in the case that the user
+	defines their own exit address. */
+	( void ) prvTaskExitError;
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	/* Mask interrupts up to the max syscall interrupt priority. */
+	ulPortSetInterruptMask();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( ulCriticalNesting == 1 )
+	{
+		configASSERT( ulPortInterruptNesting == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as the critical section is being
+		exited. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then all interrupt
+		priorities must be re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Critical nesting has reached zero so all interrupt priorities
+			should be unmasked. */
+			portCLEAR_INTERRUPT_MASK();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void FreeRTOS_Tick_Handler( void )
+{
+	/* Set interrupt mask before altering scheduler structures.   The tick
+	handler runs at the lowest priority, so interrupts cannot already be masked,
+	so there is no need to save and restore the current mask value.  It is
+	necessary to turn off interrupts in the CPU itself while the ICCPMR is being
+	updated. */
+	portCPU_IRQ_DISABLE();
+	portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+	__asm volatile (	"dsb		\n"
+						"isb		\n" ::: "memory" );
+	portCPU_IRQ_ENABLE();
+
+	/* Increment the RTOS tick. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		ulPortYieldRequired = pdTRUE;
+	}
+
+	/* Ensure all interrupt priorities are active again. */
+	portCLEAR_INTERRUPT_MASK();
+	configCLEAR_TICK_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_FPU_SUPPORT != 2 )
+
+	void vPortTaskUsesFPU( void )
+	{
+	uint32_t ulInitialFPSCR = 0;
+
+		/* A task is registering the fact that it needs an FPU context.  Set the
+		FPU flag (which is saved as part of the task context). */
+		ulPortTaskHasFPUContext = pdTRUE;
+
+		/* Initialise the floating point status register. */
+		__asm volatile ( "FMXR 	FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );
+	}
+
+#endif /* configUSE_TASK_FPU_SUPPORT */
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMask( uint32_t ulNewMaskValue )
+{
+	if( ulNewMaskValue == pdFALSE )
+	{
+		portCLEAR_INTERRUPT_MASK();
+	}
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortSetInterruptMask( void )
+{
+uint32_t ulReturn;
+
+	/* Interrupt in the CPU must be turned off while the ICCPMR is being
+	updated. */
+	portCPU_IRQ_DISABLE();
+	if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
+	{
+		/* Interrupts were already masked. */
+		ulReturn = pdTRUE;
+	}
+	else
+	{
+		ulReturn = pdFALSE;
+		portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+		__asm volatile (	"dsb		\n"
+							"isb		\n" ::: "memory" );
+	}
+	portCPU_IRQ_ENABLE();
+
+	return ulReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+		/* The following assertion will fail if a service routine (ISR) for
+		an interrupt that has been assigned a priority above
+		configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+		function.  ISR safe FreeRTOS API functions must *only* be called
+		from interrupts that have been assigned a priority at or below
+		configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+		Numerically low interrupt priority numbers represent logically high
+		interrupt priorities, therefore the priority of the interrupt must
+		be set to a value equal to or numerically *higher* than
+		configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+		FreeRTOS maintains separate thread and ISR API functions to ensure
+		interrupt entry is as fast and simple as possible. */
+		configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+
+		/* Priority grouping:  The interrupt controller (GIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		The priority grouping is configured by the GIC's binary point register
+		(ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
+		possible value (which may be above 0). */
+		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+	}
+
+#endif /* configASSERT_DEFINED */
+/*-----------------------------------------------------------*/
+
+void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR )
+{
+	( void ) ulICCIAR;
+	configASSERT( ( volatile void * ) NULL );
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CA9/portASM.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CA9/portASM.S
new file mode 100644
index 0000000..f005084
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CA9/portASM.S
@@ -0,0 +1,323 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	.text
+	.arm
+
+	.set SYS_MODE,	0x1f
+	.set SVC_MODE,	0x13
+	.set IRQ_MODE,	0x12
+
+	/* Hardware registers. */
+	.extern ulICCIAR
+	.extern ulICCEOIR
+	.extern ulICCPMR
+
+	/* Variables and functions. */
+	.extern ulMaxAPIPriorityMask
+	.extern _freertos_vector_table
+	.extern pxCurrentTCB
+	.extern vTaskSwitchContext
+	.extern vApplicationIRQHandler
+	.extern ulPortInterruptNesting
+	.extern ulPortTaskHasFPUContext
+
+	.global FreeRTOS_IRQ_Handler
+	.global FreeRTOS_SWI_Handler
+	.global vPortRestoreTaskContext
+
+
+
+
+.macro portSAVE_CONTEXT
+
+	/* Save the LR and SPSR onto the system mode stack before switching to
+	system mode to save the remaining system mode registers. */
+	SRSDB	sp!, #SYS_MODE
+	CPS		#SYS_MODE
+	PUSH	{R0-R12, R14}
+
+	/* Push the critical nesting count. */
+	LDR		R2, ulCriticalNestingConst
+	LDR		R1, [R2]
+	PUSH	{R1}
+
+	/* Does the task have a floating point context that needs saving?  If
+	ulPortTaskHasFPUContext is 0 then no. */
+	LDR		R2, ulPortTaskHasFPUContextConst
+	LDR		R3, [R2]
+	CMP		R3, #0
+
+	/* Save the floating point context, if any. */
+	FMRXNE  R1,  FPSCR
+	VPUSHNE {D0-D15}
+	VPUSHNE	{D16-D31}
+	PUSHNE	{R1}
+
+	/* Save ulPortTaskHasFPUContext itself. */
+	PUSH	{R3}
+
+	/* Save the stack pointer in the TCB. */
+	LDR		R0, pxCurrentTCBConst
+	LDR		R1, [R0]
+	STR		SP, [R1]
+
+	.endm
+
+; /**********************************************************************/
+
+.macro portRESTORE_CONTEXT
+
+	/* Set the SP to point to the stack of the task being restored. */
+	LDR		R0, pxCurrentTCBConst
+	LDR		R1, [R0]
+	LDR		SP, [R1]
+
+	/* Is there a floating point context to restore?  If the restored
+	ulPortTaskHasFPUContext is zero then no. */
+	LDR		R0, ulPortTaskHasFPUContextConst
+	POP		{R1}
+	STR		R1, [R0]
+	CMP		R1, #0
+
+	/* Restore the floating point context, if any. */
+	POPNE 	{R0}
+	VPOPNE	{D16-D31}
+	VPOPNE	{D0-D15}
+	VMSRNE  FPSCR, R0
+
+	/* Restore the critical section nesting depth. */
+	LDR		R0, ulCriticalNestingConst
+	POP		{R1}
+	STR		R1, [R0]
+
+	/* Ensure the priority mask is correct for the critical nesting depth. */
+	LDR		R2, ulICCPMRConst
+	LDR		R2, [R2]
+	CMP		R1, #0
+	MOVEQ	R4, #255
+	LDRNE	R4, ulMaxAPIPriorityMaskConst
+	LDRNE	R4, [R4]
+	STR		R4, [R2]
+
+	/* Restore all system mode registers other than the SP (which is already
+	being used). */
+	POP		{R0-R12, R14}
+
+	/* Return to the task code, loading CPSR on the way. */
+	RFEIA	sp!
+
+	.endm
+
+
+
+
+/******************************************************************************
+ * SVC handler is used to start the scheduler.
+ *****************************************************************************/
+.align 4
+.type FreeRTOS_SWI_Handler, %function
+FreeRTOS_SWI_Handler:
+	/* Save the context of the current task and select a new task to run. */
+	portSAVE_CONTEXT
+	LDR R0, vTaskSwitchContextConst
+	BLX	R0
+	portRESTORE_CONTEXT
+
+
+/******************************************************************************
+ * vPortRestoreTaskContext is used to start the scheduler.
+ *****************************************************************************/
+.type vPortRestoreTaskContext, %function
+vPortRestoreTaskContext:
+	/* Switch to system mode. */
+	CPS		#SYS_MODE
+	portRESTORE_CONTEXT
+
+.align 4
+.type FreeRTOS_IRQ_Handler, %function
+FreeRTOS_IRQ_Handler:
+	/* Return to the interrupted instruction. */
+	SUB		lr, lr, #4
+
+	/* Push the return address and SPSR. */
+	PUSH	{lr}
+	MRS		lr, SPSR
+	PUSH	{lr}
+
+	/* Change to supervisor mode to allow reentry. */
+	CPS		#SVC_MODE
+
+	/* Push used registers. */
+	PUSH	{r0-r4, r12}
+
+	/* Increment nesting count.  r3 holds the address of ulPortInterruptNesting
+	for future use.  r1 holds the original ulPortInterruptNesting value for
+	future use. */
+	LDR		r3, ulPortInterruptNestingConst
+	LDR		r1, [r3]
+	ADD		r4, r1, #1
+	STR		r4, [r3]
+
+	/* Read value from the interrupt acknowledge register, which is stored in r0
+	for future parameter and interrupt clearing use. */
+	LDR 	r2, ulICCIARConst
+	LDR		r2, [r2]
+	LDR		r0, [r2]
+
+	/* Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
+	future use.  _RB_ Does this ever actually need to be done provided the start
+	of the stack is 8-byte aligned? */
+	MOV		r2, sp
+	AND		r2, r2, #4
+	SUB		sp, sp, r2
+
+	/* Call the interrupt handler.  r4 pushed to maintain alignment. */
+	PUSH	{r0-r4, lr}
+	LDR		r1, vApplicationIRQHandlerConst
+	BLX		r1
+	POP		{r0-r4, lr}
+	ADD		sp, sp, r2
+
+	CPSID	i
+	DSB
+	ISB
+
+	/* Write the value read from ICCIAR to ICCEOIR. */
+	LDR 	r4, ulICCEOIRConst
+	LDR		r4, [r4]
+	STR		r0, [r4]
+
+	/* Restore the old nesting count. */
+	STR		r1, [r3]
+
+	/* A context switch is never performed if the nesting count is not 0. */
+	CMP		r1, #0
+	BNE		exit_without_switch
+
+	/* Did the interrupt request a context switch?  r1 holds the address of
+	ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
+	use. */
+	LDR		r1, =ulPortYieldRequired
+	LDR		r0, [r1]
+	CMP		r0, #0
+	BNE		switch_before_exit
+
+exit_without_switch:
+	/* No context switch.  Restore used registers, LR_irq and SPSR before
+	returning. */
+	POP		{r0-r4, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	MOVS	PC, LR
+
+switch_before_exit:
+	/* A context swtich is to be performed.  Clear the context switch pending
+	flag. */
+	MOV		r0, #0
+	STR		r0, [r1]
+
+	/* Restore used registers, LR-irq and SPSR before saving the context
+	to the task stack. */
+	POP		{r0-r4, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	portSAVE_CONTEXT
+
+	/* Call the function that selects the new task to execute.
+	vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
+	instructions, or 8 byte aligned stack allocated data.  LR does not need
+	saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
+	LDR		R0, vTaskSwitchContextConst
+	BLX		R0
+
+	/* Restore the context of, and branch to, the task selected to execute
+	next. */
+	portRESTORE_CONTEXT
+
+
+/******************************************************************************
+ * If the application provides an implementation of vApplicationIRQHandler(),
+ * then it will get called directly without saving the FPU registers on
+ * interrupt entry, and this weak implementation of
+ * vApplicationIRQHandler() will not get called.
+ *
+ * If the application provides its own implementation of
+ * vApplicationFPUSafeIRQHandler() then this implementation of
+ * vApplicationIRQHandler() will be called, save the FPU registers, and then
+ * call vApplicationFPUSafeIRQHandler().
+ *
+ * Therefore, if the application writer wants FPU registers to be saved on
+ * interrupt entry their IRQ handler must be called
+ * vApplicationFPUSafeIRQHandler(), and if the application writer does not want
+ * FPU registers to be saved on interrupt entry their IRQ handler must be
+ * called vApplicationIRQHandler().
+ *****************************************************************************/
+
+.align 4
+.weak vApplicationIRQHandler
+.type vApplicationIRQHandler, %function
+vApplicationIRQHandler:
+	PUSH	{LR}
+	FMRX	R1,  FPSCR
+	VPUSH	{D0-D15}
+	VPUSH	{D16-D31}
+	PUSH	{R1}
+
+	LDR		r1, vApplicationFPUSafeIRQHandlerConst
+	BLX		r1
+
+	POP		{R0}
+	VPOP	{D16-D31}
+	VPOP	{D0-D15}
+	VMSR	FPSCR, R0
+
+	POP {PC}
+
+
+ulICCIARConst:	.word ulICCIAR
+ulICCEOIRConst:	.word ulICCEOIR
+ulICCPMRConst: .word ulICCPMR
+pxCurrentTCBConst: .word pxCurrentTCB
+ulCriticalNestingConst: .word ulCriticalNesting
+ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
+ulMaxAPIPriorityMaskConst: .word ulMaxAPIPriorityMask
+vTaskSwitchContextConst: .word vTaskSwitchContext
+vApplicationIRQHandlerConst: .word vApplicationIRQHandler
+ulPortInterruptNestingConst: .word ulPortInterruptNesting
+vApplicationFPUSafeIRQHandlerConst: .word vApplicationFPUSafeIRQHandler
+
+.end
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h
new file mode 100644
index 0000000..6b50588
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h
@@ -0,0 +1,208 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+	extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+typedef uint32_t TickType_t;
+#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* Called at the end of an ISR that can cause a context switch. */
+#define portEND_SWITCHING_ISR( xSwitchRequired )\
+{												\
+extern uint32_t ulPortYieldRequired;			\
+												\
+	if( xSwitchRequired != pdFALSE )			\
+	{											\
+		ulPortYieldRequired = pdTRUE;			\
+	}											\
+}
+
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() __asm volatile ( "SWI 0" ::: "memory" );
+
+
+/*-----------------------------------------------------------
+ * Critical section control
+ *----------------------------------------------------------*/
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+extern void vPortInstallFreeRTOSVectorTable( void );
+
+/* These macros do not globally disable/enable interrupts.  They do mask off
+interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+#define portDISABLE_INTERRUPTS()	ulPortSetInterruptMask()
+#define portENABLE_INTERRUPTS()		vPortClearInterruptMask( 0 )
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask(x)
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
+
+/* Prototype of the FreeRTOS tick handler.  This must be installed as the
+handler for whichever peripheral is used to generate the RTOS tick. */
+void FreeRTOS_Tick_Handler( void );
+
+/* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are
+created without an FPU context and must call vPortTaskUsesFPU() to give
+themselves an FPU context before using any FPU instructions.  If
+configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context
+by default. */
+#if( configUSE_TASK_FPU_SUPPORT != 2 )
+	void vPortTaskUsesFPU( void );
+#else
+	/* Each task has an FPU context already, so define this function away to
+	nothing to prevent it being called accidentally. */
+	#define vPortTaskUsesFPU()
+#endif
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif /* configASSERT */
+
+#define portNOP() __asm volatile( "NOP" )
+#define portINLINE __inline
+
+#ifdef __cplusplus
+	} /* extern C */
+#endif
+
+
+/* The number of bits to shift for an interrupt priority is dependent on the
+number of bits implemented by the interrupt controller. */
+#if configUNIQUE_INTERRUPT_PRIORITIES == 16
+	#define portPRIORITY_SHIFT 4
+	#define portMAX_BINARY_POINT_VALUE	3
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
+	#define portPRIORITY_SHIFT 3
+	#define portMAX_BINARY_POINT_VALUE	2
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
+	#define portPRIORITY_SHIFT 2
+	#define portMAX_BINARY_POINT_VALUE	1
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
+	#define portPRIORITY_SHIFT 1
+	#define portMAX_BINARY_POINT_VALUE	0
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
+	#define portPRIORITY_SHIFT 0
+	#define portMAX_BINARY_POINT_VALUE	0
+#else
+	#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
+#endif
+
+/* Interrupt controller access addresses. */
+#define portICCPMR_PRIORITY_MASK_OFFSET  						( 0x04 )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET 				( 0x0C )
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET 					( 0x10 )
+#define portICCBPR_BINARY_POINT_OFFSET							( 0x08 )
+#define portICCRPR_RUNNING_PRIORITY_OFFSET						( 0x14 )
+
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS 		( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER 					( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS 	( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS 		( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS 			( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+#define portICCBPR_BINARY_POINT_REGISTER 					( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+#define portICCRPR_RUNNING_PRIORITY_REGISTER 				( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c
new file mode 100644
index 0000000..78601f6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c
@@ -0,0 +1,362 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM0 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to manipulate the NVIC. */
+#define portNVIC_SYSTICK_CTRL			( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD			( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE	( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL				( ( volatile uint32_t *) 0xe000ed04 )
+#define portNVIC_SYSPRI2				( ( volatile uint32_t *) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK			0x00000004
+#define portNVIC_SYSTICK_INT			0x00000002
+#define portNVIC_SYSTICK_ENABLE			0x00000001
+#define portNVIC_PENDSVSET				0x10000000
+#define portMIN_INTERRUPT_PRIORITY		( 255UL )
+#define portNVIC_PENDSV_PRI				( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI			( portMIN_INTERRUPT_PRIORITY << 24UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR			( 0x01000000 )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__ (( naked ));
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void vPortStartFirstTask( void ) __attribute__ (( naked ));
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+	pxTopOfStack -= 8; /* R11..R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		started to remove a compiler warning about the function being defined
+		but never called.  ulDummy is used purely to quieten other warnings
+		about code appearing after this function is called - making ulDummy
+		volatile makes the compiler think the function could return and
+		therefore not output an 'unreachable code' warning for code that appears
+		after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+	/* This function is no longer used, but retained for backward
+	compatibility. */
+}
+/*-----------------------------------------------------------*/
+
+void vPortStartFirstTask( void )
+{
+	/* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
+	table offset register that can be used to locate the initial stack value.
+	Not all M0 parts have the application vector table at address 0. */
+	__asm volatile(
+	"	.syntax unified				\n"
+	"	ldr  r2, pxCurrentTCBConst2	\n" /* Obtain location of pxCurrentTCB. */
+	"	ldr  r3, [r2]				\n"
+	"	ldr  r0, [r3]				\n" /* The first item in pxCurrentTCB is the task top of stack. */
+	"	adds r0, #32					\n" /* Discard everything up to r0. */
+	"	msr  psp, r0					\n" /* This is now the new top of stack to use in the task. */
+	"	movs r0, #2					\n" /* Switch to the psp stack. */
+	"	msr  CONTROL, r0				\n"
+	"	isb							\n"
+	"	pop  {r0-r5}					\n" /* Pop the registers that are saved automatically. */
+	"	mov  lr, r5					\n" /* lr is now in r5. */
+	"	pop  {r3}					\n" /* Return address is now in r3. */
+	"	pop  {r2}					\n" /* Pop and discard XPSR. */
+	"	cpsie i						\n" /* The first task has its context and interrupts can be enabled. */
+	"	bx   r3						\n" /* Finally, jump to the user defined task code. */
+	"								\n"
+	"	.align 4					\n"
+	"pxCurrentTCBConst2: .word pxCurrentTCB	  "
+				  );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+	*(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
+	*(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Start the first task. */
+	vPortStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing!  Call the task
+	exit error function to prevent compiler warnings about a static function
+	not being called in the case that the application writer overrides this
+	functionality by defining configTASK_RETURN_ADDRESS.  Call
+	vTaskSwitchContext() so link time optimisation does not remove the
+	symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortYield( void )
+{
+	/* Set a PendSV to request a context switch. */
+	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+	/* Barriers are normally not required but do ensure the code is completely
+	within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+    uxCriticalNesting--;
+    if( uxCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void )
+{
+	__asm volatile(
+					" mrs r0, PRIMASK	\n"
+					" cpsid i			\n"
+					" bx lr				  "
+					::: "memory"
+				  );
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* To avoid compiler warnings.  The return statement will nevere be reached,
+	but some compilers warn if it is not included, while others won't compile if
+	it is. */
+	return 0;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask )
+{
+	__asm volatile(
+					" msr PRIMASK, r0	\n"
+					" bx lr				  "
+					::: "memory"
+				  );
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* Just to avoid compiler warning.  ulMask is used from the asm code but
+	the compiler can't see that.  Some compilers generate warnings without the
+	following line, while others generate warnings if the line is included. */
+	( void ) ulMask;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+	/* This is a naked function. */
+
+	__asm volatile
+	(
+	"	.syntax unified						\n"
+	"	mrs r0, psp							\n"
+	"										\n"
+	"	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
+	"	ldr	r2, [r3]						\n"
+	"										\n"
+	"	subs r0, r0, #32					\n" /* Make space for the remaining low registers. */
+	"	str r0, [r2]						\n" /* Save the new top of stack. */
+	"	stmia r0!, {r4-r7}					\n" /* Store the low registers that are not saved automatically. */
+	" 	mov r4, r8							\n" /* Store the high registers. */
+	" 	mov r5, r9							\n"
+	" 	mov r6, r10							\n"
+	" 	mov r7, r11							\n"
+	" 	stmia r0!, {r4-r7}					\n"
+	"										\n"
+	"	push {r3, r14}						\n"
+	"	cpsid i								\n"
+	"	bl vTaskSwitchContext				\n"
+	"	cpsie i								\n"
+	"	pop {r2, r3}						\n" /* lr goes in r3. r2 now holds tcb pointer. */
+	"										\n"
+	"	ldr r1, [r2]						\n"
+	"	ldr r0, [r1]						\n" /* The first item in pxCurrentTCB is the task top of stack. */
+	"	adds r0, r0, #16					\n" /* Move to the high registers. */
+	"	ldmia r0!, {r4-r7}					\n" /* Pop the high registers. */
+	" 	mov r8, r4							\n"
+	" 	mov r9, r5							\n"
+	" 	mov r10, r6							\n"
+	" 	mov r11, r7							\n"
+	"										\n"
+	"	msr psp, r0							\n" /* Remember the new top of stack for the task. */
+	"										\n"
+	"	subs r0, r0, #32					\n" /* Go back for the low registers that are not automatically restored. */
+	" 	ldmia r0!, {r4-r7}					\n" /* Pop low registers.  */
+	"										\n"
+	"	bx r3								\n"
+	"										\n"
+	"	.align 4							\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB	  "
+	);
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+uint32_t ulPreviousMask;
+
+	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+void prvSetupTimerInterrupt( void )
+{
+	/* Stop and reset the SysTick. */
+	*(portNVIC_SYSTICK_CTRL) = 0UL;
+	*(portNVIC_SYSTICK_CURRENT_VALUE) = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	*(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	*(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h
new file mode 100644
index 0000000..108a55e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h
@@ -0,0 +1,117 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+extern void vPortYield( void );
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portYIELD()					vPortYield()
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulSetInterruptMaskFromISR( void ) __attribute__((naked));
+extern void vClearInterruptMaskFromISR( uint32_t ulMask )  __attribute__((naked));
+
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()				__asm volatile 	( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()					__asm volatile 	( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#define portNOP()
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/port.c
new file mode 100644
index 0000000..b0394fb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/* Secure components includes. */
+	#include "secure_context.h"
+	#include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK				( 0x00000004 )
+#define portNVIC_SYSTICK_INT				( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
+#define portNVIC_PENDSVSET					( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY			( 255UL )
+#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE				( 3UL )
+#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS					( 20UL )
+#define portCPACR_CP11_POS					( 22UL )
+
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS					( 31UL )
+#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS					( 30UL )
+#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS				( 0UL )
+#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS				( 8UL )
+#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS				( 16UL )
+#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS				( 24UL )
+#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS				( 0UL )
+#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS				( 8UL )
+#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS				( 16UL )
+#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS				( 24UL )
+#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE			( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE						( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR					( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         FD
+	 * 1111 1111  1111 1111  1111 1111  1111 1101
+	 *
+	 * Bit[6] - 1 --> The exception was taken from the Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 1 --> The exception was taken to the Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
+#else
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         BC
+	 * 1111 1111  1111 1111  1111 1111  1011 1100
+	 *
+	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS			prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS				1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT				0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Setup the Memory Protection Unit (MPU).
+	 */
+	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+	/**
+	 * @brief Setup the Floating Point Unit (FPU).
+	 */
+	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Saved as part of the task context to indicate which context the
+	 * task is using on the secure side.
+	 */
+	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Stop and reset the SysTick. */
+	*( portNVIC_SYSTICK_CTRL ) = 0UL;
+	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+	/* A function that implements a task must not exit or attempt to return to
+	 * its caller as there is nothing to return to. If a task wants to exit it
+	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
+	 * to be triggered if configASSERT() is defined, then stop here so
+	 * application writers can catch the error. */
+	configASSERT( ulCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		 * started to remove a compiler warning about the function being
+		 * defined but never called.  ulDummy is used purely to quieten other
+		 * warnings about code appearing after this function is called - making
+		 * ulDummy volatile makes the compiler think the function could return
+		 * and therefore not output an 'unreachable code' warning for code that
+		 * appears after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __privileged_functions_start__;
+		extern uint32_t * __privileged_functions_end__;
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+		extern uint32_t * __unprivileged_flash_start__;
+		extern uint32_t * __unprivileged_flash_end__;
+		extern uint32_t * __privileged_sram_start__;
+		extern uint32_t * __privileged_sram_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __privileged_functions_start__[];
+		extern uint32_t __privileged_functions_end__[];
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+		extern uint32_t __unprivileged_flash_start__[];
+		extern uint32_t __unprivileged_flash_end__[];
+		extern uint32_t __privileged_sram_start__[];
+		extern uint32_t __privileged_sram_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+
+		/* Check that the MPU is present. */
+		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+		{
+			/* MAIR0 - Index 0. */
+			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+			/* MAIR0 - Index 1. */
+			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+			/* Setup privileged flash as Read Only so that privileged tasks can
+			 * read it but not modify. */
+			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged flash as Read Only by both privileged and
+			 * unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged syscalls flash as Read Only by both privileged
+			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup RAM containing kernel data for privileged access only. */
+			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+								( portMPU_REGION_EXECUTE_NEVER );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Enable mem fault. */
+			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+			/* Enable MPU with privileged background access i.e. unmapped
+			 * regions have privileged access. */
+			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			/* Enable non-secure access to the FPU. */
+			SecureInit_EnableNSFPUAccess();
+		}
+		#endif /* configENABLE_TRUSTZONE */
+
+		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+		 * unprivileged code should be able to access FPU. CP11 should be
+		 * programmed to the same value as CP10. */
+		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+							);
+
+		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
+		 * context on exception entry and restore on exception return.
+		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
+		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+	}
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Set a PendSV to request a context switch. */
+	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	portDISABLE_INTERRUPTS();
+	ulCriticalNesting++;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	configASSERT( ulCriticalNesting );
+	ulCriticalNesting--;
+
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	uint32_t ulR0;
+	#if( configENABLE_MPU == 1 )
+		uint32_t ulControl, ulIsTaskPrivileged;
+	#endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
+	 * R12, LR, PC, xPSR. */
+	ulPC = pulCallerStackAddress[ 6 ];
+	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+	switch( ucSVCNumber )
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+			case portSVC_ALLOCATE_SECURE_CONTEXT:
+			{
+				/* R0 contains the stack size passed as parameter to the
+				 * vPortAllocateSecureContext function. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Read the CONTROL register value. */
+					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+					/* The task that raised the SVC is privileged if Bit[0]
+					 * in the CONTROL register is 0. */
+					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+				}
+				#else
+				{
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0 );
+				}
+				#endif /* configENABLE_MPU */
+
+				configASSERT( xSecureContext != NULL );
+				SecureContext_LoadContext( xSecureContext );
+			}
+			break;
+
+			case portSVC_FREE_SECURE_CONTEXT:
+			{
+				/* R0 contains the secure context handle to be freed. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				/* Free the secure context. */
+				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+			}
+			break;
+		#endif /* configENABLE_TRUSTZONE */
+
+		case portSVC_START_SCHEDULER:
+		{
+			#if( configENABLE_TRUSTZONE == 1 )
+			{
+				/* De-prioritize the non-secure exceptions so that the
+				 * non-secure pendSV runs at the lowest priority. */
+				SecureInit_DePrioritizeNSExceptions();
+
+				/* Initialize the secure context management system. */
+				SecureContext_Init();
+			}
+			#endif /* configENABLE_TRUSTZONE */
+
+			#if( configENABLE_FPU == 1 )
+			{
+				/* Setup the Floating Point Unit (FPU). */
+				prvSetupFPU();
+			}
+			#endif /* configENABLE_FPU */
+
+			/* Setup the context of the first task so that the first task starts
+			 * executing. */
+			vRestoreContextOfFirstTask();
+		}
+		break;
+
+		#if( configENABLE_MPU == 1 )
+			case portSVC_RAISE_PRIVILEGE:
+			{
+				/* Only raise the privilege, if the svc was raised from any of
+				 * the system calls. */
+				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+				{
+					vRaisePrivilege();
+				}
+			}
+			break;
+		#endif /* configENABLE_MPU */
+
+		default:
+		{
+			/* Incorrect SVC call. */
+			configASSERT( pdFALSE );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	 * interrupt. */
+	#if( portPRELOAD_REGISTERS == 0 )
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
+		*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#else /* portPRELOAD_REGISTERS */
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
+		pxTopOfStack--;
+		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#endif /* portPRELOAD_REGISTERS */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+	#if( configENABLE_MPU == 1 )
+	{
+		/* Setup the Memory Protection Unit (MPU). */
+		prvSetupMPU();
+	}
+	#endif /* configENABLE_MPU */
+
+	/* Start the timer that generates the tick ISR. Interrupts are disabled
+	 * here already. */
+	prvSetupTimerInterrupt();
+
+	/* Initialize the critical nesting count ready for the first task. */
+	ulCriticalNesting = 0;
+
+	/* Start the first task. */
+	vStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing. Call the task
+	 * exit error function to prevent compiler warnings about a static function
+	 * not being called in the case that the application writer overrides this
+	 * functionality by defining configTASK_RETURN_ADDRESS. Call
+	 * vTaskSwitchContext() so link time optimization does not remove the
+	 * symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Not implemented in ports where there is nothing to return to.
+	 * Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+	{
+	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+	int32_t lIndex = 0;
+
+		/* Setup MAIR0. */
+		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+		/* This function is called automatically when the task is created - in
+		 * which case the stack region parameters will be valid.  At all other
+		 * times the stack parameters will not be valid and it is assumed that
+		 * the stack region has already been configured. */
+		if( ulStackDepth > 0 )
+		{
+			/* Define the region that allows access to the stack. */
+			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
+															( portMPU_REGION_NON_SHAREABLE ) |
+															( portMPU_REGION_READ_WRITE ) |
+															( portMPU_REGION_EXECUTE_NEVER );
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
+															( portMPU_RLAR_ATTR_INDEX0 ) |
+															( portMPU_RLAR_REGION_ENABLE );
+		}
+
+		/* User supplied configurable regions. */
+		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+		{
+			/* If xRegions is NULL i.e. the task has not specified any MPU
+			 * region, the else part ensures that all the configurable MPU
+			 * regions are invalidated. */
+			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+			{
+				/* Translate the generic region definition contained in xRegions
+				 * into the ARMv8 specific MPU settings that are then stored in
+				 * xMPUSettings. */
+				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+				/* Start address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
+																			( portMPU_REGION_NON_SHAREABLE );
+
+				/* RO/RW. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+				}
+				else
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+				}
+
+				/* XN. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+				}
+
+				/* End Address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
+																			( portMPU_RLAR_REGION_ENABLE );
+
+				/* Normal memory/ Device memory. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+				{
+					/* Attr1 in MAIR0 is configured as device memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+				}
+				else
+				{
+					/* Attr1 in MAIR0 is configured as normal memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+				}
+			}
+			else
+			{
+				/* Invalidate the region. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+			}
+
+			lIndex++;
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.c
new file mode 100644
index 0000000..e4fbe2d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.c
@@ -0,0 +1,468 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"													\n"
+	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr  r3, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr  r0, [r3]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r5, #1										\n" /* r5 = 1. */
+	"	bics r4, r5										\n" /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+	"	ldr  r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
+	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str  r4, [r2]									\n" /* Program MAIR0. */
+	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+	"	movs r5, #4										\n" /* r5 = 4. */
+	"	str  r5, [r2]									\n" /* Program RNR = 4. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read first set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write first set of RBAR/RLAR registers. */
+	"	movs r5, #5										\n" /* r5 = 5. */
+	"	str  r5, [r2]									\n" /* Program RNR = 5. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read second set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write second set of RBAR/RLAR registers. */
+	"	movs r5, #6										\n" /* r5 = 6. */
+	"	str  r5, [r2]									\n" /* Program RNR = 6. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read third set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write third set of RBAR/RLAR registers. */
+	"	movs r5, #7										\n" /* r5 = 7. */
+	"	str  r5, [r2]									\n" /* Program RNR = 7. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write fourth set of RBAR/RLAR registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r5, #1										\n" /* r5 = 1. */
+	"	orrs r4, r5										\n" /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	ldm  r0!, {r1-r4}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+	"	ldr  r5, xSecureContextConst2					\n"
+	"	str  r1, [r5]									\n" /* Set xSecureContext to this task's value for the same. */
+	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
+	"	msr  control, r3								\n" /* Set this task's CONTROL value. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r4											\n" /* Finally, branch to EXC_RETURN. */
+	#else /* configENABLE_MPU */
+	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+	"	ldr  r4, xSecureContextConst2					\n"
+	"	str  r1, [r4]									\n" /* Set xSecureContext to this task's value for the same. */
+	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
+	"	movs r1, #2										\n" /* r1 = 2. */
+	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+	"xSecureContextConst2: .word xSecureContext			\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst2: .word 0xe000ed94					\n"
+	"xMAIR0Const2: .word 0xe000edc0						\n"
+	"xRNRConst2: .word 0xe000ed98						\n"
+	"xRBARConst2: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	movs r1, #1										\n" /* r1 = 1. */
+	"	tst r0, r1										\n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+	"	beq running_privileged							\n" /* If the result of previous AND operation was 0, branch. */
+	"	movs r0, #0										\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	"	bx lr											\n" /* Return. */
+	" running_privileged:								\n"
+	"	movs r0, #1										\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	"	bx lr											\n" /* Return. */
+	"													\n"
+	"	.align 4										\n"
+	::: "r0", "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	 __asm volatile
+	(
+	"	mrs r0, control									\n" /* Read the CONTROL register. */
+	"	movs r1, #1										\n" /* r1 = 1. */
+	"	bics r0, r1										\n" /* Clear the bit 0. */
+	"	msr control, r0									\n" /* Write back the new CONTROL value. */
+	"	bx lr											\n" /* Return to the caller. */
+	::: "r0", "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	movs r1, #1										\n" /* r1 = 1. */
+	"	orrs r0, r1										\n" /* r0 = r0 | r1. */
+	"	msr control, r0									\n" /* CONTROL = r0. */
+	"	bx lr											\n" /* Return to the caller. */
+	:::"r0", "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
+	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
+	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
+	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
+	"	cpsie i											\n" /* Globally enable interrupts. */
+	"	dsb												\n"
+	"	isb												\n"
+	"	svc %0											\n" /* System call to start the first task. */
+	"	nop												\n"
+	"													\n"
+	"   .align 4										\n"
+	"xVTORConst: .word 0xe000ed08						\n"
+	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	mrs r0, PRIMASK									\n"
+	"	cpsid i											\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* To avoid compiler warnings.  The return statement will never be reached,
+	 * but some compilers warn if it is not included, while others won't compile
+	 * if it is. */
+	return 0;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	msr PRIMASK, r0									\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* Just to avoid compiler warning.  ulMask is used from the asm code but
+	 * the compiler can't see that.  Some compilers generate warnings without
+	 * the following line, while others generate warnings if the line is
+	 * included. */
+	( void ) ulMask;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"	.extern SecureContext_SaveContext				\n"
+	"	.extern SecureContext_LoadContext				\n"
+	"													\n"
+	"	mrs r1, psp										\n" /* Read PSP in r1. */
+	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	"	ldr r0, [r2]									\n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+	"													\n"
+	"	cbz r0, save_ns_context							\n" /* No secure context to save. */
+	"	push {r0-r2, r14}								\n"
+	"	bl SecureContext_SaveContext					\n"
+	"	pop {r0-r3}										\n" /* LR is now in r3. */
+	"	mov lr, r3										\n" /* LR = r3. */
+	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	"	bpl save_ns_context								\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
+	#if( configENABLE_MPU == 1 )
+	"	subs r1, r1, #16								\n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mrs r3, control									\n" /* r3 = CONTROL. */
+	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
+	"	stmia r1!, {r0, r2-r4}							\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	#else /* configENABLE_MPU */
+	"	subs r1, r1, #12								\n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+	#endif /* configENABLE_MPU */
+	"	b select_next_task								\n"
+	"													\n"
+	" save_ns_context:									\n"
+	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
+	#if( configENABLE_MPU == 1 )
+	"	subs r1, r1, #48								\n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	adds r1, r1, #16								\n" /* r1 = r1 + 16. */
+	"	stmia r1!, {r4-r7}								\n" /* Store the low registers that are not saved automatically. */
+	"	mov r4, r8										\n" /* r4 = r8. */
+	"	mov r5, r9										\n" /* r5 = r9. */
+	"	mov r6, r10										\n" /* r6 = r10. */
+	"	mov r7, r11										\n" /* r7 = r11. */
+	"	stmia r1!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mrs r3, control									\n" /* r3 = CONTROL. */
+	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
+	"	subs r1, r1, #48								\n" /* r1 = r1 - 48. */
+	"	stmia r1!, {r0, r2-r4}							\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	#else /* configENABLE_MPU */
+	"	subs r1, r1, #44								\n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	stmia r1!, {r0, r2-r7}							\n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
+	"	mov r4, r8										\n" /* r4 = r8. */
+	"	mov r5, r9										\n" /* r5 = r9. */
+	"	mov r6, r10										\n" /* r6 = r10. */
+	"	mov r7, r11										\n" /* r7 = r11. */
+	"	stmia r1!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	" select_next_task:									\n"
+	"	cpsid i											\n"
+	"	bl vTaskSwitchContext							\n"
+	"	cpsie i											\n"
+	"													\n"
+	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r3, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr r1, [r3]									\n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r5, #1										\n" /* r5 = 1. */
+	"	bics r4, r5										\n" /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+	"	ldr r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
+	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str r4, [r2]									\n" /* Program MAIR0. */
+	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+	"	movs r5, #4										\n" /* r5 = 4. */
+	"	str  r5, [r2]									\n" /* Program RNR = 4. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read first set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write first set of RBAR/RLAR registers. */
+	"	movs r5, #5										\n" /* r5 = 5. */
+	"	str  r5, [r2]									\n" /* Program RNR = 5. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read second set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write second set of RBAR/RLAR registers. */
+	"	movs r5, #6										\n" /* r5 = 6. */
+	"	str  r5, [r2]									\n" /* Program RNR = 6. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read third set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write third set of RBAR/RLAR registers. */
+	"	movs r5, #7										\n" /* r5 = 7. */
+	"	str  r5, [r2]									\n" /* Program RNR = 7. */
+	"	ldmia r3!, {r6,r7}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
+	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r4!, {r6,r7}								\n" /* Write fourth set of RBAR/RLAR registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r5, #1										\n" /* r5 = 1. */
+	"	orrs r4, r5										\n" /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	ldmia r1!, {r0, r2-r4}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
+	"	msr control, r3									\n" /* Restore the CONTROL register value for the task. */
+	"	mov lr, r4										\n" /* LR = r4. */
+	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
+	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
+	"	push {r1,r4}									\n"
+	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
+	"	pop {r1,r4}										\n"
+	"	mov lr, r4										\n" /* LR = r4. */
+	"	lsls r2, r4, #25								\n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
+	"	bx lr											\n"
+	#else /* configENABLE_MPU */
+	"	ldmia r1!, {r0, r2-r3}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
+	"	mov lr, r3										\n" /* LR = r3. */
+	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
+	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
+	"	push {r1,r3}									\n"
+	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
+	"	pop {r1,r3}										\n"
+	"	mov lr, r3										\n" /* LR = r3. */
+	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
+	"	bx lr											\n"
+	#endif /* configENABLE_MPU */
+	"													\n"
+	" restore_ns_context:								\n"
+	"	adds r1, r1, #16								\n" /* Move to the high registers. */
+	"	ldmia r1!, {r4-r7}								\n" /* Restore the high registers that are not automatically restored. */
+	"	mov r8, r4										\n" /* r8 = r4. */
+	"	mov r9, r5										\n" /* r9 = r5. */
+	"	mov r10, r6										\n" /* r10 = r6. */
+	"	mov r11, r7										\n" /* r11 = r7. */
+	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
+	"	subs r1, r1, #32								\n" /* Go back to the low registers. */
+	"	ldmia r1!, {r4-r7}								\n" /* Restore the low registers that are not automatically restored. */
+	"	bx lr											\n"
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
+	"xSecureContextConst: .word xSecureContext			\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst: .word 0xe000ed94					\n"
+	"xMAIR0Const: .word 0xe000edc0						\n"
+	"xRNRConst: .word 0xe000ed98						\n"
+	"xRBARConst: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	movs r0, #4										\n"
+	"	mov r1, lr										\n"
+	"	tst r0, r1										\n"
+	"	beq stacking_used_msp							\n"
+	"	mrs r0, psp										\n"
+	"	ldr r2, svchandler_address_const				\n"
+	"	bx r2											\n"
+	" stacking_used_msp:								\n"
+	"	mrs r0, msp										\n"
+	"	ldr r2, svchandler_address_const				\n"
+	"	bx r2											\n"
+	"													\n"
+	"	.align 4										\n"
+	"svchandler_address_const: .word vPortSVCHandler_C	\n"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	svc %0											\n" /* Secure context is allocated in the supervisor call. */
+	"	bx lr											\n" /* Return. */
+	:: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	ldr r1, [r0]									\n" /* The first item in the TCB is the top of the stack. */
+	"	ldr r0, [r1]									\n" /* The first item on the stack is the task's xSecureContext. */
+	"	cmp r0, #0										\n" /* Raise svc if task's xSecureContext is not NULL. */
+	"	beq free_secure_context							\n"
+	"	bx lr											\n" /* There is no secure context (xSecureContext is NULL). */
+	" free_secure_context:								\n"
+	"	svc %0											\n" /* Secure context is freed in the supervisor call. */
+	"	bx lr											\n" /* Return. */
+	:: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.h
new file mode 100644
index 0000000..6314e96
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h
new file mode 100644
index 0000000..bebd9f6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M23"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__attribute__(( used ))
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.c
new file mode 100644
index 0000000..8a42230
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.c
@@ -0,0 +1,204 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED		0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED		0x03
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first addess of the allocated memory.
+ */
+typedef struct SecureContext
+{
+	uint8_t *pucCurrentStackPointer;	/**< Current value of stack pointer (PSP). */
+	uint8_t *pucStackLimit;				/**< Last location of the stack memory (PSPLIM). */
+	uint8_t *pucStackStart;				/**< First location of the stack memory. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+	uint32_t ulIPSR;
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* No stack for thread mode until a task's context is loaded. */
+		secureportSET_PSPLIM( securecontextNO_STACK );
+		secureportSET_PSP( securecontextNO_STACK );
+
+		#if( configENABLE_MPU == 1 )
+		{
+			/* Configure thread mode to use PSP and to be unprivileged. */
+			secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+		}
+		#else /* configENABLE_MPU */
+		{
+			/* Configure thread mode to use PSP and to be privileged.. */
+			secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+		}
+		#endif /* configENABLE_MPU */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
+#else /* configENABLE_MPU */
+	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
+#endif /* configENABLE_MPU */
+{
+	uint8_t *pucStackMemory = NULL;
+	uint32_t ulIPSR;
+	SecureContextHandle_t xSecureContextHandle = NULL;
+	#if( configENABLE_MPU == 1 )
+		uint32_t *pulCurrentStackPointer = NULL;
+	#endif /* configENABLE_MPU */
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* Allocate the context structure. */
+		xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
+
+		if( xSecureContextHandle != NULL )
+		{
+			/* Allocate the stack space. */
+			pucStackMemory = pvPortMalloc( ulSecureStackSize );
+
+			if( pucStackMemory != NULL )
+			{
+				/* Since stack grows down, the starting point will be the last
+				 * location. Note that this location is next to the last
+				 * allocated byte because the hardware decrements the stack
+				 * pointer before writing i.e. if stack pointer is 0x2, a push
+				 * operation will decrement the stack pointer to 0x1 and then
+				 * write at 0x1. */
+				xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
+
+				/* The stack cannot go beyond this location. This value is
+				 * programmed in the PSPLIM register on context switch.*/
+				xSecureContextHandle->pucStackLimit = pucStackMemory;
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Store the correct CONTROL value for the task on the stack.
+					 * This value is programmed in the CONTROL register on
+					 * context switch. */
+					pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
+					pulCurrentStackPointer--;
+					if( ulIsTaskPrivileged )
+					{
+						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+					}
+					else
+					{
+						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+					}
+
+					/* Store the current stack pointer. This value is programmed in
+					 * the PSP register on context switch. */
+					xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+				}
+				#else /* configENABLE_MPU */
+				{
+					/* Current SP is set to the starting of the stack. This
+					 * value programmed in the PSP register on context switch. */
+					xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
+
+				}
+				#endif /* configENABLE_MPU */
+			}
+			else
+			{
+				/* Free the context to avoid memory leak and make sure to return
+				 * NULL to indicate failure. */
+				vPortFree( xSecureContextHandle );
+				xSecureContextHandle = NULL;
+			}
+		}
+	}
+
+	return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
+{
+	uint32_t ulIPSR;
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* Ensure that valid parameters are passed. */
+		secureportASSERT( xSecureContextHandle != NULL );
+
+		/* Free the stack space. */
+		vPortFree( xSecureContextHandle->pucStackLimit );
+
+		/* Free the context itself. */
+		vPortFree( xSecureContextHandle );
+	}
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.h
new file mode 100644
index 0000000..a98a7d0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.h
@@ -0,0 +1,111 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include 
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no task's context is loaded.
+ */
+#define securecontextNO_STACK	0x0
+
+/**
+ * @brief Opaque handle.
+ */
+struct SecureContext;
+typedef struct SecureContext*	SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if( configENABLE_MPU == 1 )
+	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
+#else /* configENABLE_MPU */
+	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c
new file mode 100644
index 0000000..4e63dd3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c
@@ -0,0 +1,91 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+#if( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+	/* xSecureContextHandle value is in r0. */
+	__asm volatile
+	(
+	"	.syntax unified							\n"
+	"											\n"
+	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
+	"	cbz r1, load_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
+	"	ldmia r0!, {r1, r2}						\n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+	#if( configENABLE_MPU == 1 )
+	"	ldmia r1!, {r3}							\n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
+	"	msr control, r3							\n" /* CONTROL = r3. */
+	#endif /* configENABLE_MPU */
+	"	msr psplim, r2							\n" /* PSPLIM = r2. */
+	"	msr psp, r1								\n" /* PSP = r1. */
+	"											\n"
+	" load_ctx_therad_mode:						\n"
+	"	nop										\n"
+	"											\n"
+	:::"r0", "r1", "r2"
+	);
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+	/* xSecureContextHandle value is in r0. */
+	__asm volatile
+	(
+	"	.syntax unified							\n"
+	"											\n"
+	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
+	"	cbz r1, save_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
+	"	mrs r1, psp								\n" /* r1 = PSP. */
+	#if( configENABLE_MPU == 1 )
+	"	mrs r2, control							\n" /* r2 = CONTROL. */
+	"	subs r1, r1, #4							\n" /* Make space for the CONTROL value on the stack. */
+	"	str r1, [r0]							\n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+	"	stmia r1!, {r2}							\n" /* Store CONTROL value on the stack. */
+	#else /* configENABLE_MPU */
+	"	str r1, [r0]							\n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+	#endif /* configENABLE_MPU */
+	"	movs r1, %0								\n" /* r1 = securecontextNO_STACK. */
+	"	msr psplim, r1							\n" /* PSPLIM = securecontextNO_STACK. */
+	"	msr psp, r1								\n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+	"											\n"
+	" save_ctx_therad_mode:						\n"
+	"	nop										\n"
+	"											\n"
+	:: "i" ( securecontextNO_STACK ) : "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.c
new file mode 100644
index 0000000..c4f613f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.c
@@ -0,0 +1,450 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#define secureconfigTOTAL_HEAP_SIZE		( ( ( size_t ) ( 10 * 1024 ) ) )
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+	#define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+	#define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+	#define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE			( ( size_t ) 8 )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+	/* The application writer has already defined the array used for the RTOS
+	 * heap - probably so it can be placed in a special segment or address. */
+	extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+	static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/**< The next free block in the list. */
+	size_t xBlockSize;						/**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/**
+ * @brief Gets set to the top bit of an size_t type.
+ *
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set
+ * then the block belongs to the application. When the bit is free the block is
+ * still part of the free heap space.
+ */
+static size_t xBlockAllocatedBit = 0;
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	uxAddress = ( size_t ) ucHeap;
+
+	if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+	{
+		uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+		uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+	}
+
+	pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	 * blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+	xStart.xBlockSize = ( size_t ) 0;
+
+	/* pxEnd is used to mark the end of the list of free blocks and is inserted
+	 * at the end of the heap space. */
+	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+	uxAddress -= xHeapStructSize;
+	uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+	pxEnd = ( void * ) uxAddress;
+	pxEnd->xBlockSize = 0;
+	pxEnd->pxNextFreeBlock = NULL;
+
+	/* To start with there is a single free block that is sized to take up the
+	 * entire heap space, minus the space taken by pxEnd. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+	/* Only one block exists - and it covers the entire usable heap space. */
+	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	 * than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+	{
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	 * make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+		pxBlockToInsert = pxIterator;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	 * make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+	}
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	 * before and the block after, then it's pxNextFreeBlock pointer will have
+	 * already been set, and should not be set here as that would make it point
+	 * to itself. */
+	if( pxIterator != pxBlockToInsert )
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+	/* If this is the first call to malloc then the heap will require
+	 * initialisation to setup the list of free blocks. */
+	if( pxEnd == NULL )
+	{
+		prvHeapInit();
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Check the requested block size is not so large that the top bit is set.
+	 * The top bit of the block size member of the BlockLink_t structure is used
+	 * to determine who owns the block - the application or the kernel, so it
+	 * must be free. */
+	if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+	{
+		/* The wanted size is increased so it can contain a BlockLink_t
+		 * structure in addition to the requested amount of bytes. */
+		if( xWantedSize > 0 )
+		{
+			xWantedSize += xHeapStructSize;
+
+			/* Ensure that blocks are always aligned to the required number of
+			 * bytes. */
+			if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+			{
+				/* Byte alignment required. */
+				xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+				secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+		{
+			/* Traverse the list from the start (lowest address) block until
+			 * one of adequate size is found. */
+			pxPreviousBlock = &xStart;
+			pxBlock = xStart.pxNextFreeBlock;
+			while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+			{
+				pxPreviousBlock = pxBlock;
+				pxBlock = pxBlock->pxNextFreeBlock;
+			}
+
+			/* If the end marker was reached then a block of adequate size was
+			 * not found. */
+			if( pxBlock != pxEnd )
+			{
+				/* Return the memory space pointed to - jumping over the
+				 * BlockLink_t structure at its start. */
+				pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+				/* This block is being returned for use so must be taken out
+				 * of the list of free blocks. */
+				pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+				/* If the block is larger than required it can be split into
+				 * two. */
+				if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+				{
+					/* This block is to be split into two.  Create a new
+					 * block following the number of bytes requested. The void
+					 * cast is used to prevent byte alignment warnings from the
+					 * compiler. */
+					pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+					secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+					/* Calculate the sizes of two blocks split from the single
+					 * block. */
+					pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+					pxBlock->xBlockSize = xWantedSize;
+
+					/* Insert the new block into the list of free blocks. */
+					prvInsertBlockIntoFreeList( pxNewBlockLink );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+				if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+				{
+					xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* The block is being returned - it is allocated and owned by
+				 * the application and has no "next" block. */
+				pxBlock->xBlockSize |= xBlockAllocatedBit;
+				pxBlock->pxNextFreeBlock = NULL;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceMALLOC( pvReturn, xWantedSize );
+
+	#if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		 * before it. */
+		puc -= xHeapStructSize;
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+
+		/* Check the block is actually allocated. */
+		secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+		secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+			{
+				/* The block is being returned to the heap - it is no longer
+				 * allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+				secureportDISABLE_NON_SECURE_INTERRUPTS();
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+				}
+				secureportENABLE_NON_SECURE_INTERRUPTS();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+	return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.h
new file mode 100644
index 0000000..aae5cfc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.h
@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include 
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void *pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void *pv );
+
+#endif /* __SECURE_HEAP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.c
new file mode 100644
index 0000000..60ef1e8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.c
@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR					( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS		( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK	( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS		( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK		( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR						( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS			( 29UL )
+#define secureinitFPCCR_LSPENS_MASK			( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS				( 26UL )
+#define secureinitFPCCR_TS_MASK				( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR						( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS			( 10UL )
+#define secureinitNSACR_CP10_MASK			( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS			( 11UL )
+#define secureinitNSACR_CP11_MASK			( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+	uint32_t ulIPSR;
+
+	 /* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		*( secureinitSCB_AIRCR ) =	( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+									( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+									( ( 0x1UL	<< secureinitSCB_AIRCR_PRIS_POS )	& secureinitSCB_AIRCR_PRIS_MASK );
+	}
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+	uint32_t ulIPSR;
+
+	 /* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+		 * permitted. CP11 should be programmed to the same value as CP10. */
+		*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+		/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+		 * that we can enable/disable lazy stacking in port.c file. */
+		*( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
+
+		/* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+		 * registers (S16-S31) are also pushed to stack on exception entry and
+		 * restored on exception return. */
+		*( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+	}
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.h
new file mode 100644
index 0000000..3954e13
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.h
@@ -0,0 +1,53 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h
new file mode 100644
index 0000000..f392537
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT					8
+#define secureportBYTE_ALIGNMENT_MASK				( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+	#define secureportNON_SECURE_CALLABLE			__cmse_nonsecure_entry __root
+#else
+	#define secureportNON_SECURE_CALLABLE			__attribute__((cmse_nonsecure_entry)) __attribute__((used))
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+	__asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+	__asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+	__asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+	__asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+	__asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+	__asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+	__asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+	__asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL		0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL	1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS()		secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x )						\
+	if( ( x ) == 0 )								\
+	{												\
+		secureportDISABLE_SECURE_INTERRUPTS();		\
+		secureportDISABLE_NON_SECURE_INTERRUPTS();	\
+		for( ;; );									\
+	}
+
+#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
new file mode 100644
index 0000000..b0394fb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/* Secure components includes. */
+	#include "secure_context.h"
+	#include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK				( 0x00000004 )
+#define portNVIC_SYSTICK_INT				( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
+#define portNVIC_PENDSVSET					( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY			( 255UL )
+#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE				( 3UL )
+#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS					( 20UL )
+#define portCPACR_CP11_POS					( 22UL )
+
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS					( 31UL )
+#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS					( 30UL )
+#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS				( 0UL )
+#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS				( 8UL )
+#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS				( 16UL )
+#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS				( 24UL )
+#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS				( 0UL )
+#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS				( 8UL )
+#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS				( 16UL )
+#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS				( 24UL )
+#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE			( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE						( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR					( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         FD
+	 * 1111 1111  1111 1111  1111 1111  1111 1101
+	 *
+	 * Bit[6] - 1 --> The exception was taken from the Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 1 --> The exception was taken to the Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
+#else
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         BC
+	 * 1111 1111  1111 1111  1111 1111  1011 1100
+	 *
+	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS			prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS				1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT				0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Setup the Memory Protection Unit (MPU).
+	 */
+	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+	/**
+	 * @brief Setup the Floating Point Unit (FPU).
+	 */
+	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Saved as part of the task context to indicate which context the
+	 * task is using on the secure side.
+	 */
+	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Stop and reset the SysTick. */
+	*( portNVIC_SYSTICK_CTRL ) = 0UL;
+	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+	/* A function that implements a task must not exit or attempt to return to
+	 * its caller as there is nothing to return to. If a task wants to exit it
+	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
+	 * to be triggered if configASSERT() is defined, then stop here so
+	 * application writers can catch the error. */
+	configASSERT( ulCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		 * started to remove a compiler warning about the function being
+		 * defined but never called.  ulDummy is used purely to quieten other
+		 * warnings about code appearing after this function is called - making
+		 * ulDummy volatile makes the compiler think the function could return
+		 * and therefore not output an 'unreachable code' warning for code that
+		 * appears after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __privileged_functions_start__;
+		extern uint32_t * __privileged_functions_end__;
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+		extern uint32_t * __unprivileged_flash_start__;
+		extern uint32_t * __unprivileged_flash_end__;
+		extern uint32_t * __privileged_sram_start__;
+		extern uint32_t * __privileged_sram_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __privileged_functions_start__[];
+		extern uint32_t __privileged_functions_end__[];
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+		extern uint32_t __unprivileged_flash_start__[];
+		extern uint32_t __unprivileged_flash_end__[];
+		extern uint32_t __privileged_sram_start__[];
+		extern uint32_t __privileged_sram_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+
+		/* Check that the MPU is present. */
+		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+		{
+			/* MAIR0 - Index 0. */
+			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+			/* MAIR0 - Index 1. */
+			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+			/* Setup privileged flash as Read Only so that privileged tasks can
+			 * read it but not modify. */
+			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged flash as Read Only by both privileged and
+			 * unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged syscalls flash as Read Only by both privileged
+			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup RAM containing kernel data for privileged access only. */
+			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+								( portMPU_REGION_EXECUTE_NEVER );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Enable mem fault. */
+			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+			/* Enable MPU with privileged background access i.e. unmapped
+			 * regions have privileged access. */
+			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			/* Enable non-secure access to the FPU. */
+			SecureInit_EnableNSFPUAccess();
+		}
+		#endif /* configENABLE_TRUSTZONE */
+
+		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+		 * unprivileged code should be able to access FPU. CP11 should be
+		 * programmed to the same value as CP10. */
+		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+							);
+
+		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
+		 * context on exception entry and restore on exception return.
+		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
+		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+	}
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Set a PendSV to request a context switch. */
+	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	portDISABLE_INTERRUPTS();
+	ulCriticalNesting++;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	configASSERT( ulCriticalNesting );
+	ulCriticalNesting--;
+
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	uint32_t ulR0;
+	#if( configENABLE_MPU == 1 )
+		uint32_t ulControl, ulIsTaskPrivileged;
+	#endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
+	 * R12, LR, PC, xPSR. */
+	ulPC = pulCallerStackAddress[ 6 ];
+	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+	switch( ucSVCNumber )
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+			case portSVC_ALLOCATE_SECURE_CONTEXT:
+			{
+				/* R0 contains the stack size passed as parameter to the
+				 * vPortAllocateSecureContext function. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Read the CONTROL register value. */
+					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+					/* The task that raised the SVC is privileged if Bit[0]
+					 * in the CONTROL register is 0. */
+					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+				}
+				#else
+				{
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0 );
+				}
+				#endif /* configENABLE_MPU */
+
+				configASSERT( xSecureContext != NULL );
+				SecureContext_LoadContext( xSecureContext );
+			}
+			break;
+
+			case portSVC_FREE_SECURE_CONTEXT:
+			{
+				/* R0 contains the secure context handle to be freed. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				/* Free the secure context. */
+				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+			}
+			break;
+		#endif /* configENABLE_TRUSTZONE */
+
+		case portSVC_START_SCHEDULER:
+		{
+			#if( configENABLE_TRUSTZONE == 1 )
+			{
+				/* De-prioritize the non-secure exceptions so that the
+				 * non-secure pendSV runs at the lowest priority. */
+				SecureInit_DePrioritizeNSExceptions();
+
+				/* Initialize the secure context management system. */
+				SecureContext_Init();
+			}
+			#endif /* configENABLE_TRUSTZONE */
+
+			#if( configENABLE_FPU == 1 )
+			{
+				/* Setup the Floating Point Unit (FPU). */
+				prvSetupFPU();
+			}
+			#endif /* configENABLE_FPU */
+
+			/* Setup the context of the first task so that the first task starts
+			 * executing. */
+			vRestoreContextOfFirstTask();
+		}
+		break;
+
+		#if( configENABLE_MPU == 1 )
+			case portSVC_RAISE_PRIVILEGE:
+			{
+				/* Only raise the privilege, if the svc was raised from any of
+				 * the system calls. */
+				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+				{
+					vRaisePrivilege();
+				}
+			}
+			break;
+		#endif /* configENABLE_MPU */
+
+		default:
+		{
+			/* Incorrect SVC call. */
+			configASSERT( pdFALSE );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	 * interrupt. */
+	#if( portPRELOAD_REGISTERS == 0 )
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
+		*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#else /* portPRELOAD_REGISTERS */
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
+		pxTopOfStack--;
+		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#endif /* portPRELOAD_REGISTERS */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+	#if( configENABLE_MPU == 1 )
+	{
+		/* Setup the Memory Protection Unit (MPU). */
+		prvSetupMPU();
+	}
+	#endif /* configENABLE_MPU */
+
+	/* Start the timer that generates the tick ISR. Interrupts are disabled
+	 * here already. */
+	prvSetupTimerInterrupt();
+
+	/* Initialize the critical nesting count ready for the first task. */
+	ulCriticalNesting = 0;
+
+	/* Start the first task. */
+	vStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing. Call the task
+	 * exit error function to prevent compiler warnings about a static function
+	 * not being called in the case that the application writer overrides this
+	 * functionality by defining configTASK_RETURN_ADDRESS. Call
+	 * vTaskSwitchContext() so link time optimization does not remove the
+	 * symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Not implemented in ports where there is nothing to return to.
+	 * Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+	{
+	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+	int32_t lIndex = 0;
+
+		/* Setup MAIR0. */
+		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+		/* This function is called automatically when the task is created - in
+		 * which case the stack region parameters will be valid.  At all other
+		 * times the stack parameters will not be valid and it is assumed that
+		 * the stack region has already been configured. */
+		if( ulStackDepth > 0 )
+		{
+			/* Define the region that allows access to the stack. */
+			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
+															( portMPU_REGION_NON_SHAREABLE ) |
+															( portMPU_REGION_READ_WRITE ) |
+															( portMPU_REGION_EXECUTE_NEVER );
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
+															( portMPU_RLAR_ATTR_INDEX0 ) |
+															( portMPU_RLAR_REGION_ENABLE );
+		}
+
+		/* User supplied configurable regions. */
+		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+		{
+			/* If xRegions is NULL i.e. the task has not specified any MPU
+			 * region, the else part ensures that all the configurable MPU
+			 * regions are invalidated. */
+			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+			{
+				/* Translate the generic region definition contained in xRegions
+				 * into the ARMv8 specific MPU settings that are then stored in
+				 * xMPUSettings. */
+				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+				/* Start address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
+																			( portMPU_REGION_NON_SHAREABLE );
+
+				/* RO/RW. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+				}
+				else
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+				}
+
+				/* XN. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+				}
+
+				/* End Address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
+																			( portMPU_RLAR_REGION_ENABLE );
+
+				/* Normal memory/ Device memory. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+				{
+					/* Attr1 in MAIR0 is configured as device memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+				}
+				else
+				{
+					/* Attr1 in MAIR0 is configured as normal memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+				}
+			}
+			else
+			{
+				/* Invalidate the region. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+			}
+
+			lIndex++;
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
new file mode 100644
index 0000000..3ce52c3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
@@ -0,0 +1,381 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"													\n"
+	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr  r1, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr  r0, [r1]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r4, #1										\n" /* r4 = 1. */
+	"	bics r3, r4										\n" /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+	"	str r3, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	"	ldr  r4, [r1]									\n" /* r4 = *r1 i.e. r4 = MAIR0. */
+	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str  r4, [r2]									\n" /* Program MAIR0. */
+	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	"	movs r4, #4										\n" /* r4 = 4. */
+	"	str  r4, [r2]									\n" /* Program RNR = 4. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read first set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write first set of RBAR/RLAR registers. */
+	"	movs r4, #5										\n" /* r4 = 5. */
+	"	str  r4, [r2]									\n" /* Program RNR = 5. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read second set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write second set of RBAR/RLAR registers. */
+	"	movs r4, #6										\n" /* r4 = 6. */
+	"	str  r4, [r2]									\n" /* Program RNR = 6. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read third set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write third set of RBAR/RLAR registers. */
+	"	movs r4, #7										\n" /* r4 = 7. */
+	"	str  r4, [r2]									\n" /* Program RNR = 7. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write fourth set of RBAR/RLAR registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r4, #1										\n" /* r4 = 1. */
+	"	orrs r3, r4										\n" /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+	"	str r3, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
+	"	msr  control, r2								\n" /* Set this task's CONTROL value. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
+	#else /* configENABLE_MPU */
+	"	ldm  r0!, {r1-r2}								\n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
+	"	movs r1, #2										\n" /* r1 = 2. */
+	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r2											\n" /* Finally, branch to EXC_RETURN. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst2: .word 0xe000ed94					\n"
+	"xMAIR0Const2: .word 0xe000edc0						\n"
+	"xRNRConst2: .word 0xe000ed98						\n"
+	"xRBARConst2: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	movs r1, #1										\n" /* r1 = 1. */
+	"	tst r0, r1										\n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+	"	beq running_privileged							\n" /* If the result of previous AND operation was 0, branch. */
+	"	movs r0, #0										\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	"	bx lr											\n" /* Return. */
+	" running_privileged:								\n"
+	"	movs r0, #1										\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	"	bx lr											\n" /* Return. */
+	"													\n"
+	"	.align 4										\n"
+	::: "r0", "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	 __asm volatile
+	(
+	"	mrs  r0, control								\n" /* Read the CONTROL register. */
+	"	movs r1, #1										\n" /* r1 = 1. */
+	"	bics r0, r1										\n" /* Clear the bit 0. */
+	"	msr  control, r0								\n" /* Write back the new CONTROL value. */
+	"	bx lr											\n" /* Return to the caller. */
+	::: "r0", "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	movs r1, #1										\n" /* r1 = 1. */
+	"	orrs r0, r1										\n" /* r0 = r0 | r1. */
+	"	msr control, r0									\n" /* CONTROL = r0. */
+	"	bx lr											\n" /* Return to the caller. */
+	:::"r0", "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
+	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
+	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
+	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
+	"	cpsie i											\n" /* Globally enable interrupts. */
+	"	dsb												\n"
+	"	isb												\n"
+	"	svc %0											\n" /* System call to start the first task. */
+	"	nop												\n"
+	"													\n"
+	"   .align 4										\n"
+	"xVTORConst: .word 0xe000ed08						\n"
+	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	mrs r0, PRIMASK									\n"
+	"	cpsid i											\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* To avoid compiler warnings.  The return statement will never be reached,
+	 * but some compilers warn if it is not included, while others won't compile
+	 * if it is. */
+	return 0;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	msr PRIMASK, r0									\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* Just to avoid compiler warning.  ulMask is used from the asm code but
+	 * the compiler can't see that.  Some compilers generate warnings without
+	 * the following line, while others generate warnings if the line is
+	 * included. */
+	( void ) ulMask;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"													\n"
+	"	mrs r0, psp										\n" /* Read PSP in r0. */
+	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
+	#if( configENABLE_MPU == 1 )
+	"	subs r0, r0, #44								\n" /* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+	"	str r0, [r1]									\n" /* Save the new top of stack in TCB. */
+	"	mrs r1, psplim									\n" /* r1 = PSPLIM. */
+	"	mrs r2, control									\n" /* r2 = CONTROL. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	stmia r0!, {r1-r7}								\n" /* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */
+	"	mov r4, r8										\n" /* r4 = r8. */
+	"	mov r5, r9										\n" /* r5 = r9. */
+	"	mov r6, r10										\n" /* r6 = r10. */
+	"	mov r7, r11										\n" /* r7 = r11. */
+	"	stmia r0!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
+	#else /* configENABLE_MPU */
+	"	subs r0, r0, #40								\n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */
+	"	str r0, [r1]									\n" /* Save the new top of stack in TCB. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	stmia r0!, {r2-r7}								\n" /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
+	"	mov r4, r8										\n" /* r4 = r8. */
+	"	mov r5, r9										\n" /* r5 = r9. */
+	"	mov r6, r10										\n" /* r6 = r10. */
+	"	mov r7, r11										\n" /* r7 = r11. */
+	"	stmia r0!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	"	cpsid i											\n"
+	"	bl vTaskSwitchContext							\n"
+	"	cpsie i											\n"
+	"													\n"
+	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr r0, [r1]									\n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r4, #1										\n" /* r4 = 1. */
+	"	bics r3, r4										\n" /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+	"	str r3, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	"	ldr  r4, [r1]									\n" /* r4 = *r1 i.e. r4 = MAIR0. */
+	"	ldr  r2, xMAIR0Const							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str  r4, [r2]									\n" /* Program MAIR0. */
+	"	ldr  r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	"	movs r4, #4										\n" /* r4 = 4. */
+	"	str  r4, [r2]									\n" /* Program RNR = 4. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read first set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write first set of RBAR/RLAR registers. */
+	"	movs r4, #5										\n" /* r4 = 5. */
+	"	str  r4, [r2]									\n" /* Program RNR = 5. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read second set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write second set of RBAR/RLAR registers. */
+	"	movs r4, #6										\n" /* r4 = 6. */
+	"	str  r4, [r2]									\n" /* Program RNR = 6. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read third set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write third set of RBAR/RLAR registers. */
+	"	movs r4, #7										\n" /* r4 = 7. */
+	"	str  r4, [r2]									\n" /* Program RNR = 7. */
+	"	ldmia r1!, {r5,r6}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
+	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+	"	stmia r3!, {r5,r6}								\n" /* Write fourth set of RBAR/RLAR registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	movs r4, #1										\n" /* r4 = 1. */
+	"	orrs r3, r4										\n" /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+	"	str r3, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	adds r0, r0, #28								\n" /* Move to the high registers. */
+	"	ldmia r0!, {r4-r7}								\n" /* Restore the high registers that are not automatically restored. */
+	"	mov r8, r4										\n" /* r8 = r4. */
+	"	mov r9, r5										\n" /* r9 = r5. */
+	"	mov r10, r6										\n" /* r10 = r6. */
+	"	mov r11, r7										\n" /* r11 = r7. */
+	"	msr psp, r0										\n" /* Remember the new top of stack for the task. */
+	"	subs r0, r0, #44								\n" /* Move to the starting of the saved context. */
+	"	ldmia r0!, {r1-r7}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */
+	"	msr psplim, r1									\n" /* Restore the PSPLIM register value for the task. */
+	"	msr control, r2									\n" /* Restore the CONTROL register value for the task. */
+	"	bx r3											\n"
+	#else /* configENABLE_MPU */
+	"	adds r0, r0, #24								\n" /* Move to the high registers. */
+	"	ldmia r0!, {r4-r7}								\n" /* Restore the high registers that are not automatically restored. */
+	"	mov r8, r4										\n" /* r8 = r4. */
+	"	mov r9, r5										\n" /* r9 = r5. */
+	"	mov r10, r6										\n" /* r10 = r6. */
+	"	mov r11, r7										\n" /* r11 = r7. */
+	"	msr psp, r0										\n" /* Remember the new top of stack for the task. */
+	"	subs r0, r0, #40								\n" /* Move to the starting of the saved context. */
+	"	ldmia r0!, {r2-r7}								\n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
+	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
+	"	bx r3											\n"
+	#endif /* configENABLE_MPU */
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst: .word 0xe000ed94					\n"
+	"xMAIR0Const: .word 0xe000edc0						\n"
+	"xRNRConst: .word 0xe000ed98						\n"
+	"xRBARConst: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	movs r0, #4										\n"
+	"	mov r1, lr										\n"
+	"	tst r0, r1										\n"
+	"	beq stacking_used_msp							\n"
+	"	mrs r0, psp										\n"
+	"	ldr r2, svchandler_address_const				\n"
+	"	bx r2											\n"
+	" stacking_used_msp:								\n"
+	"	mrs r0, msp										\n"
+	"	ldr r2, svchandler_address_const				\n"
+	"	bx r2											\n"
+	"													\n"
+	"	.align 4										\n"
+	"svchandler_address_const: .word vPortSVCHandler_C	\n"
+	);
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
new file mode 100644
index 0000000..6314e96
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
new file mode 100644
index 0000000..bebd9f6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M23"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__attribute__(( used ))
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
new file mode 100644
index 0000000..762a02a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
@@ -0,0 +1,717 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM3 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
+defined.  The value should also ensure backward compatibility.
+FreeRTOS.org versions prior to V4.4.0 did not include this definition. */
+#ifndef configKERNEL_INTERRUPT_PRIORITY
+	#define configKERNEL_INTERRUPT_PRIORITY 255
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK					( 0xFFUL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR					( 0x01000000UL )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR			( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__ (( naked ));
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void ) __attribute__ (( naked ));
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		started to remove a compiler warning about the function being defined
+		but never called.  ulDummy is used purely to quieten other warnings
+		about code appearing after this function is called - making ulDummy
+		volatile makes the compiler think the function could return and
+		therefore not output an 'unreachable code' warning for code that appears
+		after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+	__asm volatile (
+					"	ldr	r3, pxCurrentTCBConst2		\n" /* Restore the context. */
+					"	ldr r1, [r3]					\n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+					"	ldr r0, [r1]					\n" /* The first item in pxCurrentTCB is the task top of stack. */
+					"	ldmia r0!, {r4-r11}				\n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+					"	msr psp, r0						\n" /* Restore the task stack pointer. */
+					"	isb								\n"
+					"	mov r0, #0 						\n"
+					"	msr	basepri, r0					\n"
+					"	orr r14, #0xd					\n"
+					"	bx r14							\n"
+					"									\n"
+					"	.align 4						\n"
+					"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+				);
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortStartFirstTask( void )
+{
+	__asm volatile(
+					" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
+					" ldr r0, [r0] 			\n"
+					" ldr r0, [r0] 			\n"
+					" msr msp, r0			\n" /* Set the msp back to the start of the stack. */
+					" cpsie i				\n" /* Globally enable interrupts. */
+					" cpsie f				\n"
+					" dsb					\n"
+					" isb					\n"
+					" svc 0					\n" /* System call to start first task. */
+					" nop					\n"
+				);
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Start the first task. */
+	prvPortStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing!  Call the task
+	exit error function to prevent compiler warnings about a static function
+	not being called in the case that the application writer overrides this
+	functionality by defining configTASK_RETURN_ADDRESS.  Call
+	vTaskSwitchContext() so link time optimisation does not remove the
+	symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+	/* This is a naked function. */
+
+	__asm volatile
+	(
+	"	mrs r0, psp							\n"
+	"	isb									\n"
+	"										\n"
+	"	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
+	"	ldr	r2, [r3]						\n"
+	"										\n"
+	"	stmdb r0!, {r4-r11}					\n" /* Save the remaining registers. */
+	"	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */
+	"										\n"
+	"	stmdb sp!, {r3, r14}				\n"
+	"	mov r0, %0							\n"
+	"	msr basepri, r0						\n"
+	"	bl vTaskSwitchContext				\n"
+	"	mov r0, #0							\n"
+	"	msr basepri, r0						\n"
+	"	ldmia sp!, {r3, r14}				\n"
+	"										\n" /* Restore the context, including the critical nesting count. */
+	"	ldr r1, [r3]						\n"
+	"	ldr r0, [r1]						\n" /* The first item in pxCurrentTCB is the task top of stack. */
+	"	ldmia r0!, {r4-r11}					\n" /* Pop the registers. */
+	"	msr psp, r0							\n"
+	"	isb									\n"
+	"	bx r14								\n"
+	"										\n"
+	"	.align 4							\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB	\n"
+	::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
+	);
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
+	executes all interrupts must be unmasked.  There is therefore no need to
+	save and then restore the interrupt mask value as its value is already
+	known. */
+	portDISABLE_INTERRUPTS();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE == 1 )
+
+	__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+	TickType_t xModifiableIdleTime;
+
+		/* Make sure the SysTick reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
+		is accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+		/* Calculate the reload value required to wait xExpectedIdleTime
+		tick periods.  -1 is used because this code will execute part way
+		through one of the tick periods. */
+		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+		if( ulReloadValue > ulStoppedTimerCompensation )
+		{
+			ulReloadValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Enter a critical section but don't use the taskENTER_CRITICAL()
+		method as that will mask interrupts that should exit sleep mode. */
+		__asm volatile( "cpsid i" ::: "memory" );
+		__asm volatile( "dsb" );
+		__asm volatile( "isb" );
+
+		/* If a context switch is pending or a task is waiting for the scheduler
+		to be unsuspended then abandon the low power entry. */
+		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+		{
+			/* Restart from whatever is left in the count register to complete
+			this tick period. */
+			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Reset the reload register to the value required for normal tick
+			periods. */
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Re-enable interrupts - see comments above the cpsid instruction()
+			above. */
+			__asm volatile( "cpsie i" ::: "memory" );
+		}
+		else
+		{
+			/* Set the new reload value. */
+			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+			/* Clear the SysTick count flag and set the count value back to
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+			set its parameter to 0 to indicate that its implementation contains
+			its own wait for interrupt or wait for event instruction, and so wfi
+			should not be executed again.  However, the original expected idle
+			time variable must remain unmodified, so a copy is taken. */
+			xModifiableIdleTime = xExpectedIdleTime;
+			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+			if( xModifiableIdleTime > 0 )
+			{
+				__asm volatile( "dsb" ::: "memory" );
+				__asm volatile( "wfi" );
+				__asm volatile( "isb" );
+			}
+			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+			/* Re-enable interrupts to allow the interrupt that brought the MCU
+			out of sleep mode to execute immediately.  see comments above
+			__disable_interrupt() call above. */
+			__asm volatile( "cpsie i" ::: "memory" );
+			__asm volatile( "dsb" );
+			__asm volatile( "isb" );
+
+			/* Disable interrupts again because the clock is about to be stopped
+			and interrupts that execute while the clock is stopped will increase
+			any slippage between the time maintained by the RTOS and calendar
+			time. */
+			__asm volatile( "cpsid i" ::: "memory" );
+			__asm volatile( "dsb" );
+			__asm volatile( "isb" );
+
+			/* Disable the SysTick clock without reading the
+			portNVIC_SYSTICK_CTRL_REG register to ensure the
+			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+			the time the SysTick is stopped for is accounted for as best it can
+			be, but using the tickless mode will inevitably result in some tiny
+			drift of the time maintained by the kernel with respect to calendar
+			time*/
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+			/* Determine if the SysTick clock has already counted to zero and
+			been set back to the current reload value (the reload back being
+			correct for the entire expected idle time) or if the SysTick is yet
+			to count to zero (in which case an interrupt other than the SysTick
+			must have brought the system out of sleep mode). */
+			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			{
+				uint32_t ulCalculatedLoadValue;
+
+				/* The tick interrupt is already pending, and the SysTick count
+				reloaded with ulReloadValue.  Reset the
+				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+				period. */
+				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+				/* Don't allow a tiny value, or values that have somehow
+				underflowed because the post sleep hook did something
+				that took too long. */
+				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+				{
+					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+				}
+
+				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+				/* As the pending tick will be processed as soon as this
+				function exits, the tick value maintained by the tick is stepped
+				forward by one less than the time spent waiting. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				Work out how long the sleep lasted rounded to complete tick
+				periods (not the ulReload value which accounted for part
+				ticks). */
+				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+				/* How many complete tick periods passed while the processor
+				was waiting? */
+				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+				/* The reload value is set to whatever fraction of a single tick
+				period remains. */
+				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+			}
+
+			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+			value. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+			vTaskStepTick( ulCompleteTickPeriods );
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Exit with interrpts enabled. */
+			__asm volatile( "cpsie i" ::: "memory" );
+		}
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
+{
+	/* Calculate the constants required to configure the tick interrupt. */
+	#if( configUSE_TICKLESS_IDLE == 1 )
+	{
+		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+	}
+	#endif /* configUSE_TICKLESS_IDLE */
+
+	/* Stop and clear the SysTick. */
+	portNVIC_SYSTICK_CTRL_REG = 0UL;
+	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredictable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
new file mode 100644
index 0000000..a246227
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
@@ -0,0 +1,243 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD() 															\
+{																				\
+	/* Set a PendSV to request a context switch. */								\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
+																				\
+	/* Barriers are normally not required but do ensure the code is completely	\
+	within the specified behaviour for the architecture. */						\
+	__asm volatile( "dsb" ::: "memory" );										\
+	__asm volatile( "isb" );													\
+}
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
+#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()					vPortSetBASEPRI(0)
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Generic helper function. */
+	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+	{
+	uint8_t ucReturn;
+
+		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+		return ucReturn;
+	}
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE	__inline
+
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE inline __attribute__(( always_inline))
+#endif
+
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+uint32_t ulCurrentInterrupt;
+BaseType_t xReturn;
+
+	/* Obtain the number of the currently executing interrupt. */
+	__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+	if( ulCurrentInterrupt == 0 )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	return xReturn;
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+uint32_t ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mov %0, %1												\n" \
+		"	msr basepri, %0											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mrs %0, basepri											\n" \
+		"	mov %1, %2												\n" \
+		"	msr basepri, %1											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+
+	/* This return will not be reached but is necessary to prevent compiler
+	warnings. */
+	return ulOriginalBASEPRI;
+}
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+	__asm volatile
+	(
+		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/port.c
new file mode 100644
index 0000000..b0394fb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/* Secure components includes. */
+	#include "secure_context.h"
+	#include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK				( 0x00000004 )
+#define portNVIC_SYSTICK_INT				( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
+#define portNVIC_PENDSVSET					( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY			( 255UL )
+#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE				( 3UL )
+#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS					( 20UL )
+#define portCPACR_CP11_POS					( 22UL )
+
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS					( 31UL )
+#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS					( 30UL )
+#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS				( 0UL )
+#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS				( 8UL )
+#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS				( 16UL )
+#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS				( 24UL )
+#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS				( 0UL )
+#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS				( 8UL )
+#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS				( 16UL )
+#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS				( 24UL )
+#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE			( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE						( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR					( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         FD
+	 * 1111 1111  1111 1111  1111 1111  1111 1101
+	 *
+	 * Bit[6] - 1 --> The exception was taken from the Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 1 --> The exception was taken to the Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
+#else
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         BC
+	 * 1111 1111  1111 1111  1111 1111  1011 1100
+	 *
+	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS			prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS				1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT				0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Setup the Memory Protection Unit (MPU).
+	 */
+	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+	/**
+	 * @brief Setup the Floating Point Unit (FPU).
+	 */
+	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Saved as part of the task context to indicate which context the
+	 * task is using on the secure side.
+	 */
+	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Stop and reset the SysTick. */
+	*( portNVIC_SYSTICK_CTRL ) = 0UL;
+	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+	/* A function that implements a task must not exit or attempt to return to
+	 * its caller as there is nothing to return to. If a task wants to exit it
+	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
+	 * to be triggered if configASSERT() is defined, then stop here so
+	 * application writers can catch the error. */
+	configASSERT( ulCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		 * started to remove a compiler warning about the function being
+		 * defined but never called.  ulDummy is used purely to quieten other
+		 * warnings about code appearing after this function is called - making
+		 * ulDummy volatile makes the compiler think the function could return
+		 * and therefore not output an 'unreachable code' warning for code that
+		 * appears after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __privileged_functions_start__;
+		extern uint32_t * __privileged_functions_end__;
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+		extern uint32_t * __unprivileged_flash_start__;
+		extern uint32_t * __unprivileged_flash_end__;
+		extern uint32_t * __privileged_sram_start__;
+		extern uint32_t * __privileged_sram_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __privileged_functions_start__[];
+		extern uint32_t __privileged_functions_end__[];
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+		extern uint32_t __unprivileged_flash_start__[];
+		extern uint32_t __unprivileged_flash_end__[];
+		extern uint32_t __privileged_sram_start__[];
+		extern uint32_t __privileged_sram_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+
+		/* Check that the MPU is present. */
+		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+		{
+			/* MAIR0 - Index 0. */
+			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+			/* MAIR0 - Index 1. */
+			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+			/* Setup privileged flash as Read Only so that privileged tasks can
+			 * read it but not modify. */
+			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged flash as Read Only by both privileged and
+			 * unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged syscalls flash as Read Only by both privileged
+			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup RAM containing kernel data for privileged access only. */
+			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+								( portMPU_REGION_EXECUTE_NEVER );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Enable mem fault. */
+			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+			/* Enable MPU with privileged background access i.e. unmapped
+			 * regions have privileged access. */
+			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			/* Enable non-secure access to the FPU. */
+			SecureInit_EnableNSFPUAccess();
+		}
+		#endif /* configENABLE_TRUSTZONE */
+
+		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+		 * unprivileged code should be able to access FPU. CP11 should be
+		 * programmed to the same value as CP10. */
+		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+							);
+
+		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
+		 * context on exception entry and restore on exception return.
+		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
+		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+	}
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Set a PendSV to request a context switch. */
+	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	portDISABLE_INTERRUPTS();
+	ulCriticalNesting++;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	configASSERT( ulCriticalNesting );
+	ulCriticalNesting--;
+
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	uint32_t ulR0;
+	#if( configENABLE_MPU == 1 )
+		uint32_t ulControl, ulIsTaskPrivileged;
+	#endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
+	 * R12, LR, PC, xPSR. */
+	ulPC = pulCallerStackAddress[ 6 ];
+	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+	switch( ucSVCNumber )
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+			case portSVC_ALLOCATE_SECURE_CONTEXT:
+			{
+				/* R0 contains the stack size passed as parameter to the
+				 * vPortAllocateSecureContext function. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Read the CONTROL register value. */
+					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+					/* The task that raised the SVC is privileged if Bit[0]
+					 * in the CONTROL register is 0. */
+					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+				}
+				#else
+				{
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0 );
+				}
+				#endif /* configENABLE_MPU */
+
+				configASSERT( xSecureContext != NULL );
+				SecureContext_LoadContext( xSecureContext );
+			}
+			break;
+
+			case portSVC_FREE_SECURE_CONTEXT:
+			{
+				/* R0 contains the secure context handle to be freed. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				/* Free the secure context. */
+				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+			}
+			break;
+		#endif /* configENABLE_TRUSTZONE */
+
+		case portSVC_START_SCHEDULER:
+		{
+			#if( configENABLE_TRUSTZONE == 1 )
+			{
+				/* De-prioritize the non-secure exceptions so that the
+				 * non-secure pendSV runs at the lowest priority. */
+				SecureInit_DePrioritizeNSExceptions();
+
+				/* Initialize the secure context management system. */
+				SecureContext_Init();
+			}
+			#endif /* configENABLE_TRUSTZONE */
+
+			#if( configENABLE_FPU == 1 )
+			{
+				/* Setup the Floating Point Unit (FPU). */
+				prvSetupFPU();
+			}
+			#endif /* configENABLE_FPU */
+
+			/* Setup the context of the first task so that the first task starts
+			 * executing. */
+			vRestoreContextOfFirstTask();
+		}
+		break;
+
+		#if( configENABLE_MPU == 1 )
+			case portSVC_RAISE_PRIVILEGE:
+			{
+				/* Only raise the privilege, if the svc was raised from any of
+				 * the system calls. */
+				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+				{
+					vRaisePrivilege();
+				}
+			}
+			break;
+		#endif /* configENABLE_MPU */
+
+		default:
+		{
+			/* Incorrect SVC call. */
+			configASSERT( pdFALSE );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	 * interrupt. */
+	#if( portPRELOAD_REGISTERS == 0 )
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
+		*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#else /* portPRELOAD_REGISTERS */
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
+		pxTopOfStack--;
+		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#endif /* portPRELOAD_REGISTERS */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+	#if( configENABLE_MPU == 1 )
+	{
+		/* Setup the Memory Protection Unit (MPU). */
+		prvSetupMPU();
+	}
+	#endif /* configENABLE_MPU */
+
+	/* Start the timer that generates the tick ISR. Interrupts are disabled
+	 * here already. */
+	prvSetupTimerInterrupt();
+
+	/* Initialize the critical nesting count ready for the first task. */
+	ulCriticalNesting = 0;
+
+	/* Start the first task. */
+	vStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing. Call the task
+	 * exit error function to prevent compiler warnings about a static function
+	 * not being called in the case that the application writer overrides this
+	 * functionality by defining configTASK_RETURN_ADDRESS. Call
+	 * vTaskSwitchContext() so link time optimization does not remove the
+	 * symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Not implemented in ports where there is nothing to return to.
+	 * Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+	{
+	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+	int32_t lIndex = 0;
+
+		/* Setup MAIR0. */
+		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+		/* This function is called automatically when the task is created - in
+		 * which case the stack region parameters will be valid.  At all other
+		 * times the stack parameters will not be valid and it is assumed that
+		 * the stack region has already been configured. */
+		if( ulStackDepth > 0 )
+		{
+			/* Define the region that allows access to the stack. */
+			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
+															( portMPU_REGION_NON_SHAREABLE ) |
+															( portMPU_REGION_READ_WRITE ) |
+															( portMPU_REGION_EXECUTE_NEVER );
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
+															( portMPU_RLAR_ATTR_INDEX0 ) |
+															( portMPU_RLAR_REGION_ENABLE );
+		}
+
+		/* User supplied configurable regions. */
+		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+		{
+			/* If xRegions is NULL i.e. the task has not specified any MPU
+			 * region, the else part ensures that all the configurable MPU
+			 * regions are invalidated. */
+			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+			{
+				/* Translate the generic region definition contained in xRegions
+				 * into the ARMv8 specific MPU settings that are then stored in
+				 * xMPUSettings. */
+				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+				/* Start address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
+																			( portMPU_REGION_NON_SHAREABLE );
+
+				/* RO/RW. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+				}
+				else
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+				}
+
+				/* XN. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+				}
+
+				/* End Address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
+																			( portMPU_RLAR_REGION_ENABLE );
+
+				/* Normal memory/ Device memory. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+				{
+					/* Attr1 in MAIR0 is configured as device memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+				}
+				else
+				{
+					/* Attr1 in MAIR0 is configured as normal memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+				}
+			}
+			else
+			{
+				/* Invalidate the region. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+			}
+
+			lIndex++;
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.c
new file mode 100644
index 0000000..f4be178
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.c
@@ -0,0 +1,415 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"													\n"
+	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr  r3, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr  r0, [r3]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+	"	ldr  r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
+	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str  r4, [r2]									\n" /* Program MAIR0. */
+	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	movs r4, #4										\n" /* r4 = 4. */
+	"	str  r4, [r2]									\n" /* Program RNR = 4. */
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+	"	ldr  r2, xRBARConst2							\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+	"	ldmia r3!, {r4-r11}								\n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	ldm  r0!, {r1-r4}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+	"	ldr  r5, xSecureContextConst2					\n"
+	"	str  r1, [r5]									\n" /* Set xSecureContext to this task's value for the same. */
+	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
+	"	msr  control, r3								\n" /* Set this task's CONTROL value. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r4											\n" /* Finally, branch to EXC_RETURN. */
+	#else /* configENABLE_MPU */
+	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+	"	ldr  r4, xSecureContextConst2					\n"
+	"	str  r1, [r4]									\n" /* Set xSecureContext to this task's value for the same. */
+	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
+	"	movs r1, #2										\n" /* r1 = 2. */
+	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+	"xSecureContextConst2: .word xSecureContext			\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst2: .word 0xe000ed94					\n"
+	"xMAIR0Const2: .word 0xe000edc0						\n"
+	"xRNRConst2: .word 0xe000ed98						\n"
+	"xRBARConst2: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	tst r0, #1										\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	"	ite ne											\n"
+	"	movne r0, #0									\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	"	moveq r0, #1									\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	"	bx lr											\n" /* Return. */
+	"													\n"
+	"	.align 4										\n"
+	::: "r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	 __asm volatile
+	(
+	"	mrs r0, control									\n" /* Read the CONTROL register. */
+	"	bic r0, #1										\n" /* Clear the bit 0. */
+	"	msr control, r0									\n" /* Write back the new CONTROL value. */
+	"	bx lr											\n" /* Return to the caller. */
+	::: "r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	orr r0, #1										\n" /* r0 = r0 | 1. */
+	"	msr control, r0									\n" /* CONTROL = r0. */
+	"	bx lr											\n" /* Return to the caller. */
+	:::"r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
+	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
+	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
+	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
+	"	cpsie i											\n" /* Globally enable interrupts. */
+	"	cpsie f											\n"
+	"	dsb												\n"
+	"	isb												\n"
+	"	svc %0											\n" /* System call to start the first task. */
+	"	nop												\n"
+	"													\n"
+	"   .align 4										\n"
+	"xVTORConst: .word 0xe000ed08						\n"
+	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	mrs r0, PRIMASK									\n"
+	"	cpsid i											\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* To avoid compiler warnings.  The return statement will never be reached,
+	 * but some compilers warn if it is not included, while others won't compile
+	 * if it is. */
+	return 0;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	msr PRIMASK, r0									\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* Just to avoid compiler warning.  ulMask is used from the asm code but
+	 * the compiler can't see that.  Some compilers generate warnings without
+	 * the following line, while others generate warnings if the line is
+	 * included. */
+	( void ) ulMask;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"	.extern SecureContext_SaveContext				\n"
+	"	.extern SecureContext_LoadContext				\n"
+	"													\n"
+	"	mrs r1, psp										\n" /* Read PSP in r1. */
+	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	"	ldr r0, [r2]									\n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+	"													\n"
+	"	cbz r0, save_ns_context							\n" /* No secure context to save. */
+	"	push {r0-r2, r14}								\n"
+	"	bl SecureContext_SaveContext					\n"
+	"	pop {r0-r3}										\n" /* LR is now in r3. */
+	"	mov lr, r3										\n" /* LR = r3. */
+	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	"	bpl save_ns_context								\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
+	#if( configENABLE_MPU == 1 )
+	"	subs r1, r1, #16								\n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mrs r3, control									\n" /* r3 = CONTROL. */
+	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
+	"	stmia r1!, {r0, r2-r4}							\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	#else /* configENABLE_MPU */
+	"	subs r1, r1, #12								\n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+	#endif /* configENABLE_MPU */
+	"	b select_next_task								\n"
+	"													\n"
+	" save_ns_context:									\n"
+	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
+	#if( configENABLE_FPU == 1 )
+	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+	"	it eq											\n"
+	"	vstmdbeq r1!, {s16-s31}							\n" /* Store the FPU registers which are not saved automatically. */
+	#endif /* configENABLE_FPU */
+	#if( configENABLE_MPU == 1 )
+	"	subs r1, r1, #48								\n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	adds r1, r1, #16								\n" /* r1 = r1 + 16. */
+	"	stm r1, {r4-r11}								\n" /* Store the registers that are not saved automatically. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mrs r3, control									\n" /* r3 = CONTROL. */
+	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
+	"	subs r1, r1, #16								\n" /* r1 = r1 - 16. */
+	"	stm r1, {r0, r2-r4}								\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	#else /* configENABLE_MPU */
+	"	subs r1, r1, #44								\n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
+	"	adds r1, r1, #12								\n" /* r1 = r1 + 12. */
+	"	stm r1, {r4-r11}								\n" /* Store the registers that are not saved automatically. */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	subs r1, r1, #12								\n" /* r1 = r1 - 12. */
+	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	" select_next_task:									\n"
+	"	cpsid i											\n"
+	"	bl vTaskSwitchContext							\n"
+	"	cpsie i											\n"
+	"													\n"
+	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r3, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr r1, [r3]									\n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+	"	ldr r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
+	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str r4, [r2]									\n" /* Program MAIR0. */
+	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	movs r4, #4										\n" /* r4 = 4. */
+	"	str r4, [r2]									\n" /* Program RNR = 4. */
+	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+	"	ldr  r2, xRBARConst								\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+	"	ldmia r3!, {r4-r11}								\n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	ldmia r1!, {r0, r2-r4}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
+	"	msr control, r3									\n" /* Restore the CONTROL register value for the task. */
+	"	mov lr, r4										\n" /* LR = r4. */
+	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
+	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
+	"	push {r1,r4}									\n"
+	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
+	"	pop {r1,r4}										\n"
+	"	mov lr, r4										\n" /* LR = r4. */
+	"	lsls r2, r4, #25								\n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
+	"	bx lr											\n"
+	#else /* configENABLE_MPU */
+	"	ldmia r1!, {r0, r2-r3}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
+	"	mov lr, r3										\n" /* LR = r3. */
+	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
+	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
+	"	push {r1,r3}									\n"
+	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
+	"	pop {r1,r3}										\n"
+	"	mov lr, r3										\n" /* LR = r3. */
+	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
+	"	bx lr											\n"
+	#endif /* configENABLE_MPU */
+	"													\n"
+	" restore_ns_context:								\n"
+	"	ldmia r1!, {r4-r11}								\n" /* Restore the registers that are not automatically restored. */
+	#if( configENABLE_FPU == 1 )
+	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+	"	it eq											\n"
+	"	vldmiaeq r1!, {s16-s31}							\n" /* Restore the FPU registers which are not restored automatically. */
+	#endif /* configENABLE_FPU */
+	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
+	"	bx lr											\n"
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
+	"xSecureContextConst: .word xSecureContext			\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst: .word 0xe000ed94					\n"
+	"xMAIR0Const: .word 0xe000edc0						\n"
+	"xRNRConst: .word 0xe000ed98						\n"
+	"xRBARConst: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	tst lr, #4										\n"
+	"	ite eq											\n"
+	"	mrseq r0, msp									\n"
+	"	mrsne r0, psp									\n"
+	"	ldr r1, svchandler_address_const				\n"
+	"	bx r1											\n"
+	"													\n"
+	"	.align 4										\n"
+	"svchandler_address_const: .word vPortSVCHandler_C	\n"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	svc %0											\n" /* Secure context is allocated in the supervisor call. */
+	"	bx lr											\n" /* Return. */
+	:: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	ldr r1, [r0]									\n" /* The first item in the TCB is the top of the stack. */
+	"	ldr r0, [r1]									\n" /* The first item on the stack is the task's xSecureContext. */
+	"	cmp r0, #0										\n" /* Raise svc if task's xSecureContext is not NULL. */
+	"	it ne											\n"
+	"	svcne %0										\n" /* Secure context is freed in the supervisor call. */
+	"	bx lr											\n" /* Return. */
+	:: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.h
new file mode 100644
index 0000000..6314e96
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h
new file mode 100644
index 0000000..90d9bc2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M33"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__attribute__(( used ))
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.c
new file mode 100644
index 0000000..8a42230
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.c
@@ -0,0 +1,204 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED		0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED		0x03
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first addess of the allocated memory.
+ */
+typedef struct SecureContext
+{
+	uint8_t *pucCurrentStackPointer;	/**< Current value of stack pointer (PSP). */
+	uint8_t *pucStackLimit;				/**< Last location of the stack memory (PSPLIM). */
+	uint8_t *pucStackStart;				/**< First location of the stack memory. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+	uint32_t ulIPSR;
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* No stack for thread mode until a task's context is loaded. */
+		secureportSET_PSPLIM( securecontextNO_STACK );
+		secureportSET_PSP( securecontextNO_STACK );
+
+		#if( configENABLE_MPU == 1 )
+		{
+			/* Configure thread mode to use PSP and to be unprivileged. */
+			secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+		}
+		#else /* configENABLE_MPU */
+		{
+			/* Configure thread mode to use PSP and to be privileged.. */
+			secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+		}
+		#endif /* configENABLE_MPU */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
+#else /* configENABLE_MPU */
+	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
+#endif /* configENABLE_MPU */
+{
+	uint8_t *pucStackMemory = NULL;
+	uint32_t ulIPSR;
+	SecureContextHandle_t xSecureContextHandle = NULL;
+	#if( configENABLE_MPU == 1 )
+		uint32_t *pulCurrentStackPointer = NULL;
+	#endif /* configENABLE_MPU */
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* Allocate the context structure. */
+		xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
+
+		if( xSecureContextHandle != NULL )
+		{
+			/* Allocate the stack space. */
+			pucStackMemory = pvPortMalloc( ulSecureStackSize );
+
+			if( pucStackMemory != NULL )
+			{
+				/* Since stack grows down, the starting point will be the last
+				 * location. Note that this location is next to the last
+				 * allocated byte because the hardware decrements the stack
+				 * pointer before writing i.e. if stack pointer is 0x2, a push
+				 * operation will decrement the stack pointer to 0x1 and then
+				 * write at 0x1. */
+				xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
+
+				/* The stack cannot go beyond this location. This value is
+				 * programmed in the PSPLIM register on context switch.*/
+				xSecureContextHandle->pucStackLimit = pucStackMemory;
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Store the correct CONTROL value for the task on the stack.
+					 * This value is programmed in the CONTROL register on
+					 * context switch. */
+					pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
+					pulCurrentStackPointer--;
+					if( ulIsTaskPrivileged )
+					{
+						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+					}
+					else
+					{
+						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+					}
+
+					/* Store the current stack pointer. This value is programmed in
+					 * the PSP register on context switch. */
+					xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+				}
+				#else /* configENABLE_MPU */
+				{
+					/* Current SP is set to the starting of the stack. This
+					 * value programmed in the PSP register on context switch. */
+					xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
+
+				}
+				#endif /* configENABLE_MPU */
+			}
+			else
+			{
+				/* Free the context to avoid memory leak and make sure to return
+				 * NULL to indicate failure. */
+				vPortFree( xSecureContextHandle );
+				xSecureContextHandle = NULL;
+			}
+		}
+	}
+
+	return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
+{
+	uint32_t ulIPSR;
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* Ensure that valid parameters are passed. */
+		secureportASSERT( xSecureContextHandle != NULL );
+
+		/* Free the stack space. */
+		vPortFree( xSecureContextHandle->pucStackLimit );
+
+		/* Free the context itself. */
+		vPortFree( xSecureContextHandle );
+	}
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.h
new file mode 100644
index 0000000..a98a7d0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.h
@@ -0,0 +1,111 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include 
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no task's context is loaded.
+ */
+#define securecontextNO_STACK	0x0
+
+/**
+ * @brief Opaque handle.
+ */
+struct SecureContext;
+typedef struct SecureContext*	SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if( configENABLE_MPU == 1 )
+	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
+#else /* configENABLE_MPU */
+	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c
new file mode 100644
index 0000000..245adff
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c
@@ -0,0 +1,88 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+	/* xSecureContextHandle value is in r0. */
+	__asm volatile
+	(
+	"	.syntax unified							\n"
+	"											\n"
+	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
+	"	cbz r1, load_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
+	"	ldmia r0!, {r1, r2}						\n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+	#if( configENABLE_MPU == 1 )
+	"	ldmia r1!, {r3}							\n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
+	"	msr control, r3							\n" /* CONTROL = r3. */
+	#endif /* configENABLE_MPU */
+	"	msr psplim, r2							\n" /* PSPLIM = r2. */
+	"	msr psp, r1								\n" /* PSP = r1. */
+	"											\n"
+	" load_ctx_therad_mode:						\n"
+	"	nop										\n"
+	"											\n"
+	:::"r0", "r1", "r2"
+	);
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+	/* xSecureContextHandle value is in r0. */
+	__asm volatile
+	(
+	"	.syntax unified							\n"
+	"											\n"
+	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
+	"	cbz r1, save_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
+	"	mrs r1, psp								\n" /* r1 = PSP. */
+	#if( configENABLE_FPU == 1 )
+	"	vstmdb r1!, {s0}						\n" /* Trigger the defferred stacking of FPU registers. */
+	"	vldmia r1!, {s0}						\n" /* Nullify the effect of the pervious statement. */
+	#endif /* configENABLE_FPU */
+	#if( configENABLE_MPU == 1 )
+	"	mrs r2, control							\n" /* r2 = CONTROL. */
+	"	stmdb r1!, {r2}							\n" /* Store CONTROL value on the stack. */
+	#endif /* configENABLE_MPU */
+	"	str r1, [r0]							\n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+	"	movs r1, %0								\n" /* r1 = securecontextNO_STACK. */
+	"	msr psplim, r1							\n" /* PSPLIM = securecontextNO_STACK. */
+	"	msr psp, r1								\n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+	"											\n"
+	" save_ctx_therad_mode:						\n"
+	"	nop										\n"
+	"											\n"
+	:: "i" ( securecontextNO_STACK ) : "r1", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.c
new file mode 100644
index 0000000..c4f613f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.c
@@ -0,0 +1,450 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#define secureconfigTOTAL_HEAP_SIZE		( ( ( size_t ) ( 10 * 1024 ) ) )
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+	#define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+	#define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+	#define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE			( ( size_t ) 8 )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+	/* The application writer has already defined the array used for the RTOS
+	 * heap - probably so it can be placed in a special segment or address. */
+	extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+	static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/**< The next free block in the list. */
+	size_t xBlockSize;						/**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/**
+ * @brief Gets set to the top bit of an size_t type.
+ *
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set
+ * then the block belongs to the application. When the bit is free the block is
+ * still part of the free heap space.
+ */
+static size_t xBlockAllocatedBit = 0;
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	uxAddress = ( size_t ) ucHeap;
+
+	if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+	{
+		uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+		uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+	}
+
+	pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	 * blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+	xStart.xBlockSize = ( size_t ) 0;
+
+	/* pxEnd is used to mark the end of the list of free blocks and is inserted
+	 * at the end of the heap space. */
+	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+	uxAddress -= xHeapStructSize;
+	uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+	pxEnd = ( void * ) uxAddress;
+	pxEnd->xBlockSize = 0;
+	pxEnd->pxNextFreeBlock = NULL;
+
+	/* To start with there is a single free block that is sized to take up the
+	 * entire heap space, minus the space taken by pxEnd. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+	/* Only one block exists - and it covers the entire usable heap space. */
+	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	 * than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+	{
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	 * make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+		pxBlockToInsert = pxIterator;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	 * make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+	}
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	 * before and the block after, then it's pxNextFreeBlock pointer will have
+	 * already been set, and should not be set here as that would make it point
+	 * to itself. */
+	if( pxIterator != pxBlockToInsert )
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+	/* If this is the first call to malloc then the heap will require
+	 * initialisation to setup the list of free blocks. */
+	if( pxEnd == NULL )
+	{
+		prvHeapInit();
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Check the requested block size is not so large that the top bit is set.
+	 * The top bit of the block size member of the BlockLink_t structure is used
+	 * to determine who owns the block - the application or the kernel, so it
+	 * must be free. */
+	if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+	{
+		/* The wanted size is increased so it can contain a BlockLink_t
+		 * structure in addition to the requested amount of bytes. */
+		if( xWantedSize > 0 )
+		{
+			xWantedSize += xHeapStructSize;
+
+			/* Ensure that blocks are always aligned to the required number of
+			 * bytes. */
+			if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+			{
+				/* Byte alignment required. */
+				xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+				secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+		{
+			/* Traverse the list from the start (lowest address) block until
+			 * one of adequate size is found. */
+			pxPreviousBlock = &xStart;
+			pxBlock = xStart.pxNextFreeBlock;
+			while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+			{
+				pxPreviousBlock = pxBlock;
+				pxBlock = pxBlock->pxNextFreeBlock;
+			}
+
+			/* If the end marker was reached then a block of adequate size was
+			 * not found. */
+			if( pxBlock != pxEnd )
+			{
+				/* Return the memory space pointed to - jumping over the
+				 * BlockLink_t structure at its start. */
+				pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+				/* This block is being returned for use so must be taken out
+				 * of the list of free blocks. */
+				pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+				/* If the block is larger than required it can be split into
+				 * two. */
+				if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+				{
+					/* This block is to be split into two.  Create a new
+					 * block following the number of bytes requested. The void
+					 * cast is used to prevent byte alignment warnings from the
+					 * compiler. */
+					pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+					secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+					/* Calculate the sizes of two blocks split from the single
+					 * block. */
+					pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+					pxBlock->xBlockSize = xWantedSize;
+
+					/* Insert the new block into the list of free blocks. */
+					prvInsertBlockIntoFreeList( pxNewBlockLink );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+				if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+				{
+					xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* The block is being returned - it is allocated and owned by
+				 * the application and has no "next" block. */
+				pxBlock->xBlockSize |= xBlockAllocatedBit;
+				pxBlock->pxNextFreeBlock = NULL;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceMALLOC( pvReturn, xWantedSize );
+
+	#if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		 * before it. */
+		puc -= xHeapStructSize;
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+
+		/* Check the block is actually allocated. */
+		secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+		secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+			{
+				/* The block is being returned to the heap - it is no longer
+				 * allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+				secureportDISABLE_NON_SECURE_INTERRUPTS();
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+				}
+				secureportENABLE_NON_SECURE_INTERRUPTS();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+	return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.h
new file mode 100644
index 0000000..aae5cfc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.h
@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include 
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void *pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void *pv );
+
+#endif /* __SECURE_HEAP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.c
new file mode 100644
index 0000000..60ef1e8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.c
@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR					( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS		( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK	( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS		( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK		( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR						( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS			( 29UL )
+#define secureinitFPCCR_LSPENS_MASK			( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS				( 26UL )
+#define secureinitFPCCR_TS_MASK				( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR						( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS			( 10UL )
+#define secureinitNSACR_CP10_MASK			( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS			( 11UL )
+#define secureinitNSACR_CP11_MASK			( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+	uint32_t ulIPSR;
+
+	 /* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		*( secureinitSCB_AIRCR ) =	( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+									( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+									( ( 0x1UL	<< secureinitSCB_AIRCR_PRIS_POS )	& secureinitSCB_AIRCR_PRIS_MASK );
+	}
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+	uint32_t ulIPSR;
+
+	 /* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+		 * permitted. CP11 should be programmed to the same value as CP10. */
+		*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+		/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+		 * that we can enable/disable lazy stacking in port.c file. */
+		*( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
+
+		/* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+		 * registers (S16-S31) are also pushed to stack on exception entry and
+		 * restored on exception return. */
+		*( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+	}
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.h
new file mode 100644
index 0000000..3954e13
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.h
@@ -0,0 +1,53 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h
new file mode 100644
index 0000000..f392537
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT					8
+#define secureportBYTE_ALIGNMENT_MASK				( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+	#define secureportNON_SECURE_CALLABLE			__cmse_nonsecure_entry __root
+#else
+	#define secureportNON_SECURE_CALLABLE			__attribute__((cmse_nonsecure_entry)) __attribute__((used))
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+	__asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+	__asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+	__asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+	__asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+	__asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+	__asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+	__asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+	__asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL		0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL	1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS()		secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x )						\
+	if( ( x ) == 0 )								\
+	{												\
+		secureportDISABLE_SECURE_INTERRUPTS();		\
+		secureportDISABLE_NON_SECURE_INTERRUPTS();	\
+		for( ;; );									\
+	}
+
+#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
new file mode 100644
index 0000000..b0394fb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/* Secure components includes. */
+	#include "secure_context.h"
+	#include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK				( 0x00000004 )
+#define portNVIC_SYSTICK_INT				( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
+#define portNVIC_PENDSVSET					( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY			( 255UL )
+#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE				( 3UL )
+#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS					( 20UL )
+#define portCPACR_CP11_POS					( 22UL )
+
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS					( 31UL )
+#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS					( 30UL )
+#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS				( 0UL )
+#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS				( 8UL )
+#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS				( 16UL )
+#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS				( 24UL )
+#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS				( 0UL )
+#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS				( 8UL )
+#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS				( 16UL )
+#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS				( 24UL )
+#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE			( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE						( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR					( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         FD
+	 * 1111 1111  1111 1111  1111 1111  1111 1101
+	 *
+	 * Bit[6] - 1 --> The exception was taken from the Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 1 --> The exception was taken to the Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
+#else
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         BC
+	 * 1111 1111  1111 1111  1111 1111  1011 1100
+	 *
+	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS			prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS				1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT				0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Setup the Memory Protection Unit (MPU).
+	 */
+	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+	/**
+	 * @brief Setup the Floating Point Unit (FPU).
+	 */
+	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Saved as part of the task context to indicate which context the
+	 * task is using on the secure side.
+	 */
+	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Stop and reset the SysTick. */
+	*( portNVIC_SYSTICK_CTRL ) = 0UL;
+	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+	/* A function that implements a task must not exit or attempt to return to
+	 * its caller as there is nothing to return to. If a task wants to exit it
+	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
+	 * to be triggered if configASSERT() is defined, then stop here so
+	 * application writers can catch the error. */
+	configASSERT( ulCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		 * started to remove a compiler warning about the function being
+		 * defined but never called.  ulDummy is used purely to quieten other
+		 * warnings about code appearing after this function is called - making
+		 * ulDummy volatile makes the compiler think the function could return
+		 * and therefore not output an 'unreachable code' warning for code that
+		 * appears after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __privileged_functions_start__;
+		extern uint32_t * __privileged_functions_end__;
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+		extern uint32_t * __unprivileged_flash_start__;
+		extern uint32_t * __unprivileged_flash_end__;
+		extern uint32_t * __privileged_sram_start__;
+		extern uint32_t * __privileged_sram_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __privileged_functions_start__[];
+		extern uint32_t __privileged_functions_end__[];
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+		extern uint32_t __unprivileged_flash_start__[];
+		extern uint32_t __unprivileged_flash_end__[];
+		extern uint32_t __privileged_sram_start__[];
+		extern uint32_t __privileged_sram_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+
+		/* Check that the MPU is present. */
+		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+		{
+			/* MAIR0 - Index 0. */
+			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+			/* MAIR0 - Index 1. */
+			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+			/* Setup privileged flash as Read Only so that privileged tasks can
+			 * read it but not modify. */
+			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged flash as Read Only by both privileged and
+			 * unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged syscalls flash as Read Only by both privileged
+			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup RAM containing kernel data for privileged access only. */
+			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+								( portMPU_REGION_EXECUTE_NEVER );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Enable mem fault. */
+			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+			/* Enable MPU with privileged background access i.e. unmapped
+			 * regions have privileged access. */
+			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			/* Enable non-secure access to the FPU. */
+			SecureInit_EnableNSFPUAccess();
+		}
+		#endif /* configENABLE_TRUSTZONE */
+
+		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+		 * unprivileged code should be able to access FPU. CP11 should be
+		 * programmed to the same value as CP10. */
+		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+							);
+
+		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
+		 * context on exception entry and restore on exception return.
+		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
+		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+	}
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Set a PendSV to request a context switch. */
+	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	portDISABLE_INTERRUPTS();
+	ulCriticalNesting++;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	configASSERT( ulCriticalNesting );
+	ulCriticalNesting--;
+
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	uint32_t ulR0;
+	#if( configENABLE_MPU == 1 )
+		uint32_t ulControl, ulIsTaskPrivileged;
+	#endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
+	 * R12, LR, PC, xPSR. */
+	ulPC = pulCallerStackAddress[ 6 ];
+	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+	switch( ucSVCNumber )
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+			case portSVC_ALLOCATE_SECURE_CONTEXT:
+			{
+				/* R0 contains the stack size passed as parameter to the
+				 * vPortAllocateSecureContext function. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Read the CONTROL register value. */
+					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+					/* The task that raised the SVC is privileged if Bit[0]
+					 * in the CONTROL register is 0. */
+					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+				}
+				#else
+				{
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0 );
+				}
+				#endif /* configENABLE_MPU */
+
+				configASSERT( xSecureContext != NULL );
+				SecureContext_LoadContext( xSecureContext );
+			}
+			break;
+
+			case portSVC_FREE_SECURE_CONTEXT:
+			{
+				/* R0 contains the secure context handle to be freed. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				/* Free the secure context. */
+				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+			}
+			break;
+		#endif /* configENABLE_TRUSTZONE */
+
+		case portSVC_START_SCHEDULER:
+		{
+			#if( configENABLE_TRUSTZONE == 1 )
+			{
+				/* De-prioritize the non-secure exceptions so that the
+				 * non-secure pendSV runs at the lowest priority. */
+				SecureInit_DePrioritizeNSExceptions();
+
+				/* Initialize the secure context management system. */
+				SecureContext_Init();
+			}
+			#endif /* configENABLE_TRUSTZONE */
+
+			#if( configENABLE_FPU == 1 )
+			{
+				/* Setup the Floating Point Unit (FPU). */
+				prvSetupFPU();
+			}
+			#endif /* configENABLE_FPU */
+
+			/* Setup the context of the first task so that the first task starts
+			 * executing. */
+			vRestoreContextOfFirstTask();
+		}
+		break;
+
+		#if( configENABLE_MPU == 1 )
+			case portSVC_RAISE_PRIVILEGE:
+			{
+				/* Only raise the privilege, if the svc was raised from any of
+				 * the system calls. */
+				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+				{
+					vRaisePrivilege();
+				}
+			}
+			break;
+		#endif /* configENABLE_MPU */
+
+		default:
+		{
+			/* Incorrect SVC call. */
+			configASSERT( pdFALSE );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	 * interrupt. */
+	#if( portPRELOAD_REGISTERS == 0 )
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
+		*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#else /* portPRELOAD_REGISTERS */
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
+		pxTopOfStack--;
+		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#endif /* portPRELOAD_REGISTERS */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+	#if( configENABLE_MPU == 1 )
+	{
+		/* Setup the Memory Protection Unit (MPU). */
+		prvSetupMPU();
+	}
+	#endif /* configENABLE_MPU */
+
+	/* Start the timer that generates the tick ISR. Interrupts are disabled
+	 * here already. */
+	prvSetupTimerInterrupt();
+
+	/* Initialize the critical nesting count ready for the first task. */
+	ulCriticalNesting = 0;
+
+	/* Start the first task. */
+	vStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing. Call the task
+	 * exit error function to prevent compiler warnings about a static function
+	 * not being called in the case that the application writer overrides this
+	 * functionality by defining configTASK_RETURN_ADDRESS. Call
+	 * vTaskSwitchContext() so link time optimization does not remove the
+	 * symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Not implemented in ports where there is nothing to return to.
+	 * Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+	{
+	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+	int32_t lIndex = 0;
+
+		/* Setup MAIR0. */
+		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+		/* This function is called automatically when the task is created - in
+		 * which case the stack region parameters will be valid.  At all other
+		 * times the stack parameters will not be valid and it is assumed that
+		 * the stack region has already been configured. */
+		if( ulStackDepth > 0 )
+		{
+			/* Define the region that allows access to the stack. */
+			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
+															( portMPU_REGION_NON_SHAREABLE ) |
+															( portMPU_REGION_READ_WRITE ) |
+															( portMPU_REGION_EXECUTE_NEVER );
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
+															( portMPU_RLAR_ATTR_INDEX0 ) |
+															( portMPU_RLAR_REGION_ENABLE );
+		}
+
+		/* User supplied configurable regions. */
+		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+		{
+			/* If xRegions is NULL i.e. the task has not specified any MPU
+			 * region, the else part ensures that all the configurable MPU
+			 * regions are invalidated. */
+			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+			{
+				/* Translate the generic region definition contained in xRegions
+				 * into the ARMv8 specific MPU settings that are then stored in
+				 * xMPUSettings. */
+				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+				/* Start address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
+																			( portMPU_REGION_NON_SHAREABLE );
+
+				/* RO/RW. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+				}
+				else
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+				}
+
+				/* XN. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+				}
+
+				/* End Address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
+																			( portMPU_RLAR_REGION_ENABLE );
+
+				/* Normal memory/ Device memory. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+				{
+					/* Attr1 in MAIR0 is configured as device memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+				}
+				else
+				{
+					/* Attr1 in MAIR0 is configured as normal memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+				}
+			}
+			else
+			{
+				/* Invalidate the region. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+			}
+
+			lIndex++;
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
new file mode 100644
index 0000000..2f87d0f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
@@ -0,0 +1,321 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"													\n"
+	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr  r1, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr  r0, [r1]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	"	ldr  r3, [r1]									\n" /* r3 = *r1 i.e. r3 = MAIR0. */
+	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str  r3, [r2]									\n" /* Program MAIR0. */
+	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	movs r3, #4										\n" /* r3 = 4. */
+	"	str  r3, [r2]									\n" /* Program RNR = 4. */
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	"	ldr  r2, xRBARConst2							\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+	"	ldmia r1!, {r4-r11}								\n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
+	"	msr  control, r2								\n" /* Set this task's CONTROL value. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
+	#else /* configENABLE_MPU */
+	"	ldm  r0!, {r1-r2}								\n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
+	"	movs r1, #2										\n" /* r1 = 2. */
+	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
+	"	adds r0, #32									\n" /* Discard everything up to r0. */
+	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
+	"	isb												\n"
+	"	bx   r2											\n" /* Finally, branch to EXC_RETURN. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst2: .word 0xe000ed94					\n"
+	"xMAIR0Const2: .word 0xe000edc0						\n"
+	"xRNRConst2: .word 0xe000ed98						\n"
+	"xRBARConst2: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	tst r0, #1										\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	"	ite ne											\n"
+	"	movne r0, #0									\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	"	moveq r0, #1									\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	"	bx lr											\n" /* Return. */
+	"													\n"
+	"	.align 4										\n"
+	::: "r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	 __asm volatile
+	(
+	"	mrs  r0, control								\n" /* Read the CONTROL register. */
+	"	bic r0, #1										\n" /* Clear the bit 0. */
+	"	msr  control, r0								\n" /* Write back the new CONTROL value. */
+	"	bx lr											\n" /* Return to the caller. */
+	::: "r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control									\n" /* r0 = CONTROL. */
+	"	orr r0, #1										\n" /* r0 = r0 | 1. */
+	"	msr control, r0									\n" /* CONTROL = r0. */
+	"	bx lr											\n" /* Return to the caller. */
+	:::"r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
+	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
+	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
+	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
+	"	cpsie i											\n" /* Globally enable interrupts. */
+	"	cpsie f											\n"
+	"	dsb												\n"
+	"	isb												\n"
+	"	svc %0											\n" /* System call to start the first task. */
+	"	nop												\n"
+	"													\n"
+	"   .align 4										\n"
+	"xVTORConst: .word 0xe000ed08						\n"
+	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	mrs r0, PRIMASK									\n"
+	"	cpsid i											\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* To avoid compiler warnings.  The return statement will never be reached,
+	 * but some compilers warn if it is not included, while others won't compile
+	 * if it is. */
+	return 0;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	msr PRIMASK, r0									\n"
+	"	bx lr											\n"
+	::: "memory"
+	);
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+	/* Just to avoid compiler warning.  ulMask is used from the asm code but
+	 * the compiler can't see that.  Some compilers generate warnings without
+	 * the following line, while others generate warnings if the line is
+	 * included. */
+	( void ) ulMask;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	.syntax unified									\n"
+	"													\n"
+	"	mrs r0, psp										\n" /* Read PSP in r0. */
+	#if( configENABLE_FPU == 1 )
+	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+	"	it eq											\n"
+	"	vstmdbeq r0!, {s16-s31}							\n" /* Store the FPU registers which are not saved automatically. */
+	#endif /* configENABLE_FPU */
+	#if( configENABLE_MPU == 1 )
+	"	mrs r1, psplim									\n" /* r1 = PSPLIM. */
+	"	mrs r2, control									\n" /* r2 = CONTROL. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	stmdb r0!, {r1-r11}								\n" /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
+	#else /* configENABLE_MPU */
+	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
+	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
+	"	stmdb r0!, {r2-r11}								\n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
+	"	str r0, [r1]									\n" /* Save the new top of stack in TCB. */
+	"													\n"
+	"	cpsid i											\n"
+	"	bl vTaskSwitchContext							\n"
+	"	cpsie i											\n"
+	"													\n"
+	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
+	"	ldr r0, [r1]									\n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Disable MPU. */
+	"													\n"
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	"	ldr r3, [r1]									\n" /* r3 = *r1 i.e. r3 = MAIR0. */
+	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+	"	str r3, [r2]									\n" /* Program MAIR0. */
+	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
+	"	movs r3, #4										\n" /* r3 = 4. */
+	"	str r3, [r2]									\n" /* Program RNR = 4. */
+	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	"	ldr r2, xRBARConst								\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+	"	ldmia r1!, {r4-r11}								\n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+	"													\n"
+	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
+	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	"	str r4, [r2]									\n" /* Enable MPU. */
+	"	dsb												\n" /* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	ldmia r0!, {r1-r11}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
+	#else /* configENABLE_MPU */
+	"	ldmia r0!, {r2-r11}								\n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+	#endif /* configENABLE_MPU */
+	"													\n"
+	#if( configENABLE_FPU == 1 )
+	"	tst r3, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+	"	it eq											\n"
+	"	vldmiaeq r0!, {s16-s31}							\n" /* Restore the FPU registers which are not restored automatically. */
+	#endif /* configENABLE_FPU */
+	"													\n"
+	#if( configENABLE_MPU == 1 )
+	"	msr psplim, r1									\n" /* Restore the PSPLIM register value for the task. */
+	"	msr control, r2									\n" /* Restore the CONTROL register value for the task. */
+	#else /* configENABLE_MPU */
+	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
+	#endif /* configENABLE_MPU */
+	"	msr psp, r0										\n" /* Remember the new top of stack for the task. */
+	"	bx r3											\n"
+	"													\n"
+	"	.align 4										\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
+	#if( configENABLE_MPU == 1 )
+	"xMPUCTRLConst: .word 0xe000ed94					\n"
+	"xMAIR0Const: .word 0xe000edc0						\n"
+	"xRNRConst: .word 0xe000ed98						\n"
+	"xRBARConst: .word 0xe000ed9c						\n"
+	#endif /* configENABLE_MPU */
+	);
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+	__asm volatile
+	(
+	"	tst lr, #4										\n"
+	"	ite eq											\n"
+	"	mrseq r0, msp									\n"
+	"	mrsne r0, psp									\n"
+	"	ldr r1, svchandler_address_const				\n"
+	"	bx r1											\n"
+	"													\n"
+	"	.align 4										\n"
+	"svchandler_address_const: .word vPortSVCHandler_C	\n"
+	);
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
new file mode 100644
index 0000000..6314e96
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
new file mode 100644
index 0000000..90d9bc2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M33"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__attribute__(( used ))
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c
new file mode 100644
index 0000000..25eb413
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c
@@ -0,0 +1,797 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM3 port.
+ *----------------------------------------------------------*/
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK	( 0 )
+#endif
+
+/* Constants required to access and manipulate the NVIC. */
+#define portNVIC_SYSTICK_CTRL_REG				( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG				( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG		( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG					( *	( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSPRI1_REG					( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
+#define portNVIC_SYS_CTRL_STATE_REG				( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
+#define portNVIC_MEM_FAULT_ENABLE				( 1UL << 16UL )
+
+/* Constants required to access and manipulate the MPU. */
+#define portMPU_TYPE_REG						( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_REGION_BASE_ADDRESS_REG			( * ( ( volatile uint32_t * ) 0xe000ed9C ) )
+#define portMPU_REGION_ATTRIBUTE_REG			( * ( ( volatile uint32_t * ) 0xe000edA0 ) )
+#define portMPU_CTRL_REG						( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portEXPECTED_MPU_TYPE_VALUE				( 8UL << 8UL ) /* 8 regions, unified. */
+#define portMPU_ENABLE							( 0x01UL )
+#define portMPU_BACKGROUND_ENABLE				( 1UL << 2UL )
+#define portPRIVILEGED_EXECUTION_START_ADDRESS	( 0UL )
+#define portMPU_REGION_VALID					( 0x10UL )
+#define portMPU_REGION_ENABLE					( 0x01UL )
+#define portPERIPHERALS_START_ADDRESS			0x40000000UL
+#define portPERIPHERALS_END_ADDRESS				0x5FFFFFFFUL
+
+/* Constants required to access and manipulate the SysTick. */
+#define portNVIC_SYSTICK_INT					( 0x00000002UL )
+#define portNVIC_SYSTICK_ENABLE					( 0x00000001UL )
+#define portNVIC_PENDSV_PRI						( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portNVIC_SVC_PRI						( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR						( 0x01000000 )
+#define portINITIAL_CONTROL_IF_UNPRIVILEGED		( 0x03 )
+#define portINITIAL_CONTROL_IF_PRIVILEGED		( 0x02 )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Offsets in the stack to the parameters when inside the SVC handler. */
+#define portOFFSET_TO_PC						( 6 )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
+
+/*
+ * Configure a number of standard MPU regions that are used by all tasks.
+ */
+static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the smallest MPU region size that a given number of bytes will fit
+ * into.  The region size is returned as the value that should be programmed
+ * into the region attribute register for that region.
+ */
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Standard FreeRTOS exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+void xPortSysTickHandler( void )  __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;
+void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/*
+ * Starts the scheduler by restoring the context of the first task to run.
+ */
+static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/*
+ * C portion of the SVC handler.  The SVC handler is split between an asm entry
+ * and a C wrapper for simplicity of coding and maintenance.
+ */
+static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable.  Note this is not saved as part of the task context as context
+switches can only occur when uxCriticalNesting is zero. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = 0;	/* LR */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+	pxTopOfStack -= 9;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	if( xRunPrivileged == pdTRUE )
+	{
+		*pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
+	}
+	else
+	{
+		*pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
+	}
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+	/* Assumes psp was in use. */
+	__asm volatile
+	(
+		#ifndef USE_PROCESS_STACK	/* Code should not be required if a main() is using the process stack. */
+			"	tst lr, #4						\n"
+			"	ite eq							\n"
+			"	mrseq r0, msp					\n"
+			"	mrsne r0, psp					\n"
+		#else
+			"	mrs r0, psp						\n"
+		#endif
+			"	b %0							\n"
+			::"i"(prvSVCHandler):"r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+static void prvSVCHandler(	uint32_t *pulParam )
+{
+uint8_t ucSVCNumber;
+
+	/* The stack contains: r0, r1, r2, r3, r12, r14, the return address and
+	xPSR.  The first argument (r0) is pulParam[ 0 ]. */
+	ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];
+	switch( ucSVCNumber )
+	{
+		case portSVC_START_SCHEDULER	:	portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
+											prvRestoreContextOfFirstTask();
+											break;
+
+		case portSVC_YIELD				:	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+											/* Barriers are normally not required
+											but do ensure the code is completely
+											within the specified behaviour for the
+											architecture. */
+											__asm volatile( "dsb" ::: "memory" );
+											__asm volatile( "isb" );
+
+											break;
+
+		case portSVC_RAISE_PRIVILEGE	:	__asm volatile
+											(
+												"	mrs r1, control		\n" /* Obtain current control value. */
+												"	bic r1, #1			\n" /* Set privilege bit. */
+												"	msr control, r1		\n" /* Write back new control value. */
+												::: "r1", "memory"
+											);
+											break;
+
+		default							:	/* Unknown SVC call. */
+											break;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvRestoreContextOfFirstTask( void )
+{
+	__asm volatile
+	(
+		"	ldr r0, =0xE000ED08				\n" /* Use the NVIC offset register to locate the stack. */
+		"	ldr r0, [r0]					\n"
+		"	ldr r0, [r0]					\n"
+		"	msr msp, r0						\n" /* Set the msp back to the start of the stack. */
+		"	ldr	r3, pxCurrentTCBConst2		\n" /* Restore the context. */
+		"	ldr r1, [r3]					\n"
+		"	ldr r0, [r1]					\n" /* The first item in the TCB is the task top of stack. */
+		"	add r1, r1, #4					\n" /* Move onto the second item in the TCB... */
+		"	ldr r2, =0xe000ed9c				\n" /* Region Base Address register. */
+		"	ldmia r1!, {r4-r11}				\n" /* Read 4 sets of MPU registers. */
+		"	stmia r2!, {r4-r11}				\n" /* Write 4 sets of MPU registers. */
+		"	ldmia r0!, {r3, r4-r11}			\n" /* Pop the registers that are not automatically saved on exception entry. */
+		"	msr control, r3					\n"
+		"	msr psp, r0						\n" /* Restore the task stack pointer. */
+		"	mov r0, #0						\n"
+		"	msr	basepri, r0					\n"
+		"	ldr r14, =0xfffffffd			\n" /* Load exec return code. */
+		"	bx r14							\n"
+		"									\n"
+		"	.align 4						\n"
+		"pxCurrentTCBConst2: .word pxCurrentTCB	\n"
+	);
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See
+	http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+	configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the same priority as the kernel, and the SVC
+	handler higher priority so it can be used to exit a critical section (where
+	lower priorities are masked). */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Configure the regions in the MPU that are common to all tasks. */
+	prvSetupMPU();
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Start the first task. */
+	__asm volatile(
+					" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
+					" ldr r0, [r0] 			\n"
+					" ldr r0, [r0] 			\n"
+					" msr msp, r0			\n" /* Set the msp back to the start of the stack. */
+					" cpsie i				\n" /* Globally enable interrupts. */
+					" cpsie f				\n"
+					" dsb					\n"
+					" isb					\n"
+					" svc %0				\n" /* System call to start first task. */
+					" nop					\n"
+					:: "i" (portSVC_START_SCHEDULER) : "memory" );
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+	vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+	/* This is a naked function. */
+
+	__asm volatile
+	(
+		"	mrs r0, psp							\n"
+		"										\n"
+		"	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
+		"	ldr	r2, [r3]						\n"
+		"										\n"
+		"	mrs r1, control						\n"
+		"	stmdb r0!, {r1, r4-r11}				\n" /* Save the remaining registers. */
+		"	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */
+		"										\n"
+		"	stmdb sp!, {r3, r14}				\n"
+		"	mov r0, %0							\n"
+		"	msr basepri, r0						\n"
+		"	dsb									\n"
+		"	isb									\n"
+		"	bl vTaskSwitchContext				\n"
+		"	mov r0, #0							\n"
+		"	msr basepri, r0						\n"
+		"	ldmia sp!, {r3, r14}				\n"
+		"										\n"	/* Restore the context. */
+		"	ldr r1, [r3]						\n"
+		"	ldr r0, [r1]						\n" /* The first item in the TCB is the task top of stack. */
+		"	add r1, r1, #4						\n" /* Move onto the second item in the TCB... */
+		"	ldr r2, =0xe000ed9c					\n" /* Region Base Address register. */
+		"	ldmia r1!, {r4-r11}					\n" /* Read 4 sets of MPU registers. */
+		"	stmia r2!, {r4-r11}					\n" /* Write 4 sets of MPU registers. */
+		"	ldmia r0!, {r3, r4-r11}				\n" /* Pop the registers that are not automatically saved on exception entry. */
+		"	msr control, r3						\n"
+		"										\n"
+		"	msr psp, r0							\n"
+		"	bx r14								\n"
+		"										\n"
+		"	.align 4							\n"
+		"pxCurrentTCBConst: .word pxCurrentTCB	\n"
+		::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
+	);
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+uint32_t ulDummy;
+
+	ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
+{
+	/* Stop and clear the SysTick. */
+	portNVIC_SYSTICK_CTRL_REG = 0UL;
+	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupMPU( void )
+{
+extern uint32_t __privileged_functions_end__[];
+extern uint32_t __FLASH_segment_start__[];
+extern uint32_t __FLASH_segment_end__[];
+extern uint32_t __privileged_data_start__[];
+extern uint32_t __privileged_data_end__[];
+
+	/* Check the expected MPU is present. */
+	if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+	{
+		/* First setup the entire flash for unprivileged read only access. */
+		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
+											( portMPU_REGION_VALID ) |
+											( portUNPRIVILEGED_FLASH_REGION );
+
+		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_READ_ONLY ) |
+										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+										( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
+										( portMPU_REGION_ENABLE );
+
+		/* Setup the first 16K for privileged only access (even though less
+		than 10K is actually being used).  This is where the kernel code is
+		placed. */
+		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
+											( portMPU_REGION_VALID ) |
+											( portPRIVILEGED_FLASH_REGION );
+
+		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
+										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+										( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
+										( portMPU_REGION_ENABLE );
+
+		/* Setup the privileged data RAM region.  This is where the kernel data
+		is placed. */
+		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
+											( portMPU_REGION_VALID ) |
+											( portPRIVILEGED_RAM_REGION );
+
+		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+										prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
+										( portMPU_REGION_ENABLE );
+
+		/* By default allow everything to access the general peripherals.  The
+		system peripherals and registers are protected. */
+		portMPU_REGION_BASE_ADDRESS_REG =	( portPERIPHERALS_START_ADDRESS ) |
+											( portMPU_REGION_VALID ) |
+											( portGENERAL_PERIPHERALS_REGION );
+
+		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
+										( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
+										( portMPU_REGION_ENABLE );
+
+		/* Enable the memory fault exception. */
+		portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
+
+		/* Enable the MPU with the background region configured. */
+		portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
+{
+uint32_t ulRegionSize, ulReturnValue = 4;
+
+	/* 32 is the smallest region size, 31 is the largest valid value for
+	ulReturnValue. */
+	for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
+	{
+		if( ulActualSizeInBytes <= ulRegionSize )
+		{
+			break;
+		}
+		else
+		{
+			ulReturnValue++;
+		}
+	}
+
+	/* Shift the code by one before returning so it can be written directly
+	into the the correct bit position of the attribute register. */
+	return ( ulReturnValue << 1UL );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control							\n" /* r0 = CONTROL. */
+	"	tst r0, #1								\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	"	ite ne									\n"
+	"	movne r0, #0							\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	"	moveq r0, #1							\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	"	bx lr									\n" /* Return. */
+	"											\n"
+	"	.align 4								\n"
+	::: "r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control							\n" /* r0 = CONTROL. */
+	"	orr r0, #1								\n" /* r0 = r0 | 1. */
+	"	msr control, r0							\n" /* CONTROL = r0. */
+	"	bx lr									\n" /* Return to the caller. */
+	:::"r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+{
+extern uint32_t __SRAM_segment_start__[];
+extern uint32_t __SRAM_segment_end__[];
+extern uint32_t __privileged_data_start__[];
+extern uint32_t __privileged_data_end__[];
+int32_t lIndex;
+uint32_t ul;
+
+	if( xRegions == NULL )
+	{
+		/* No MPU regions are specified so allow access to all RAM. */
+		xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
+				( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
+				( portMPU_REGION_VALID ) |
+				( portSTACK_REGION );
+
+		xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
+				( portMPU_REGION_READ_WRITE ) |
+				( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+				( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
+				( portMPU_REGION_ENABLE );
+
+		/* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
+		just removed the privileged only parameters. */
+		xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
+				( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
+				( portMPU_REGION_VALID ) |
+				( portSTACK_REGION + 1 );
+
+		xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
+				( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+				( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+				prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
+				( portMPU_REGION_ENABLE );
+
+		/* Invalidate all other regions. */
+		for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+		{
+			xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+			xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
+		}
+	}
+	else
+	{
+		/* This function is called automatically when the task is created - in
+		which case the stack region parameters will be valid.  At all other
+		times the stack parameters will not be valid and it is assumed that the
+		stack region has already been configured. */
+		if( ulStackDepth > 0 )
+		{
+			/* Define the region that allows access to the stack. */
+			xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
+					( ( uint32_t ) pxBottomOfStack ) |
+					( portMPU_REGION_VALID ) |
+					( portSTACK_REGION ); /* Region number. */
+
+			xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
+					( portMPU_REGION_READ_WRITE ) | /* Read and write. */
+					( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
+					( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+					( portMPU_REGION_ENABLE );
+		}
+
+		lIndex = 0;
+
+		for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+		{
+			if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
+			{
+				/* Translate the generic region definition contained in
+				xRegions into the CM3 specific MPU settings that are then
+				stored in xMPUSettings. */
+				xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
+						( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
+						( portMPU_REGION_VALID ) |
+						( portSTACK_REGION + ul ); /* Region number. */
+
+				xMPUSettings->xRegion[ ul ].ulRegionAttribute =
+						( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
+						( xRegions[ lIndex ].ulParameters ) |
+						( portMPU_REGION_ENABLE );
+			}
+			else
+			{
+				/* Invalidate the region. */
+				xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+				xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
+			}
+
+			lIndex++;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredicable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+/*-----------------------------------------------------------*/
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
new file mode 100644
index 0000000..ff8ddb6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
@@ -0,0 +1,301 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* MPU specific constants. */
+#define portUSING_MPU_WRAPPERS		1
+#define portPRIVILEGE_BIT			( 0x80000000UL )
+
+#define portMPU_REGION_READ_WRITE				( 0x03UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY		( 0x05UL << 24UL )
+#define portMPU_REGION_READ_ONLY				( 0x06UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE	( 0x01UL << 24UL )
+#define portMPU_REGION_CACHEABLE_BUFFERABLE		( 0x07UL << 16UL )
+#define portMPU_REGION_EXECUTE_NEVER			( 0x01UL << 28UL )
+
+#define portUNPRIVILEGED_FLASH_REGION		( 0UL )
+#define portPRIVILEGED_FLASH_REGION			( 1UL )
+#define portPRIVILEGED_RAM_REGION			( 2UL )
+#define portGENERAL_PERIPHERALS_REGION		( 3UL )
+#define portSTACK_REGION					( 4UL )
+#define portFIRST_CONFIGURABLE_REGION	    ( 5UL )
+#define portLAST_CONFIGURABLE_REGION		( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS		( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS				( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
+
+typedef struct MPU_REGION_REGISTERS
+{
+	uint32_t ulRegionBaseAddress;
+	uint32_t ulRegionAttribute;
+} xMPU_REGION_REGISTERS;
+
+/* Plus 1 to create space for the stack region. */
+typedef struct MPU_SETTINGS
+{
+	xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
+} xMPU_SETTINGS;
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+/* SVC numbers for various services. */
+#define portSVC_START_SCHEDULER				0
+#define portSVC_YIELD						1
+#define portSVC_RAISE_PRIVILEGE				2
+
+/* Scheduler utilities. */
+
+#define portYIELD()				__asm volatile ( "	SVC	%0	\n" :: "i" (portSVC_YIELD) : "memory" )
+#define portYIELD_WITHIN_API() 													\
+{																				\
+	/* Set a PendSV to request a context switch. */								\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
+																				\
+	/* Barriers are normally not required but do ensure the code is completely	\
+	within the specified behaviour for the architecture. */						\
+	__asm volatile( "dsb" ::: "memory" );										\
+	__asm volatile( "isb" );													\
+}
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
+#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()					vPortSetBASEPRI(0)
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Generic helper function. */
+	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+	{
+	uint8_t ucReturn;
+
+		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+		return ucReturn;
+	}
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE	__inline
+
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE inline __attribute__(( always_inline))
+#endif
+/*-----------------------------------------------------------*/
+
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED()			xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+*/
+#define portRAISE_PRIVILEGE()		__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE()		vResetPrivilege()
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+uint32_t ulCurrentInterrupt;
+BaseType_t xReturn;
+
+	/* Obtain the number of the currently executing interrupt. */
+	__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+	if( ulCurrentInterrupt == 0 )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	return xReturn;
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+uint32_t ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mov %0, %1												\n"	\
+		"	msr basepri, %0											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mrs %0, basepri											\n" \
+		"	mov %1, %2												\n"	\
+		"	msr basepri, %1											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+
+	/* This return will not be reached but is necessary to prevent compiler
+	warnings. */
+	return ulOriginalBASEPRI;
+}
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+	__asm volatile
+	(
+		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
new file mode 100644
index 0000000..e84e9ba
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
@@ -0,0 +1,775 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM4F port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __VFP_FP__
+	#error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
+r0p1 port. */
+#define portCPUID							( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
+#define portCORTEX_M7_r0p1_ID				( 0x410FC271UL )
+#define portCORTEX_M7_r0p0_ID				( 0x410FC270UL )
+
+#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK					( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS			( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR					( 0x01000000 )
+#define portINITIAL_EXC_RETURN				( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK		( ( StackType_t ) 0xfffffffeUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR			( 45UL )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__ (( naked ));
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void ) __attribute__ (( naked ));
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
+
+/*
+ * Function to enable the VFP.
+ */
+static void vPortEnableVFP( void ) __attribute__ (( naked ));
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+
+	/* Offset added to account for the way the MCU uses the stack on entry/exit
+	of interrupts, and to ensure alignment. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+
+	/* Save code space by skipping register initialisation. */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+
+	/* A save method is being used that requires each task to maintain its
+	own exec return value. */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0;
+
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		started to remove a compiler warning about the function being defined
+		but never called.  ulDummy is used purely to quieten other warnings
+		about code appearing after this function is called - making ulDummy
+		volatile makes the compiler think the function could return and
+		therefore not output an 'unreachable code' warning for code that appears
+		after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+	__asm volatile (
+					"	ldr	r3, pxCurrentTCBConst2		\n" /* Restore the context. */
+					"	ldr r1, [r3]					\n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+					"	ldr r0, [r1]					\n" /* The first item in pxCurrentTCB is the task top of stack. */
+					"	ldmia r0!, {r4-r11, r14}		\n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+					"	msr psp, r0						\n" /* Restore the task stack pointer. */
+					"	isb								\n"
+					"	mov r0, #0 						\n"
+					"	msr	basepri, r0					\n"
+					"	bx r14							\n"
+					"									\n"
+					"	.align 4						\n"
+					"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+				);
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortStartFirstTask( void )
+{
+	/* Start the first task.  This also clears the bit that indicates the FPU is
+	in use in case the FPU was used before the scheduler was started - which
+	would otherwise result in the unnecessary leaving of space in the SVC stack
+	for lazy saving of FPU registers. */
+	__asm volatile(
+					" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
+					" ldr r0, [r0] 			\n"
+					" ldr r0, [r0] 			\n"
+					" msr msp, r0			\n" /* Set the msp back to the start of the stack. */
+					" mov r0, #0			\n" /* Clear the bit that indicates the FPU is in use, see comment above. */
+					" msr control, r0		\n"
+					" cpsie i				\n" /* Globally enable interrupts. */
+					" cpsie f				\n"
+					" dsb					\n"
+					" isb					\n"
+					" svc 0					\n" /* System call to start first task. */
+					" nop					\n"
+				);
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+	/* This port can be used on all revisions of the Cortex-M7 core other than
+	the r0p1 parts.  r0p1 parts should use the port from the
+	/source/portable/GCC/ARM_CM7/r0p1 directory. */
+	configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
+	configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Ensure the VFP is enabled - it should be anyway. */
+	vPortEnableVFP();
+
+	/* Lazy save always. */
+	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+	/* Start the first task. */
+	prvPortStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing!  Call the task
+	exit error function to prevent compiler warnings about a static function
+	not being called in the case that the application writer overrides this
+	functionality by defining configTASK_RETURN_ADDRESS.  Call
+	vTaskSwitchContext() so link time optimisation does not remove the
+	symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+	/* This is a naked function. */
+
+	__asm volatile
+	(
+	"	mrs r0, psp							\n"
+	"	isb									\n"
+	"										\n"
+	"	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
+	"	ldr	r2, [r3]						\n"
+	"										\n"
+	"	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, push high vfp registers. */
+	"	it eq								\n"
+	"	vstmdbeq r0!, {s16-s31}				\n"
+	"										\n"
+	"	stmdb r0!, {r4-r11, r14}			\n" /* Save the core registers. */
+	"	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */
+	"										\n"
+	"	stmdb sp!, {r0, r3}					\n"
+	"	mov r0, %0 							\n"
+	"	msr basepri, r0						\n"
+	"	dsb									\n"
+	"	isb									\n"
+	"	bl vTaskSwitchContext				\n"
+	"	mov r0, #0							\n"
+	"	msr basepri, r0						\n"
+	"	ldmia sp!, {r0, r3}					\n"
+	"										\n"
+	"	ldr r1, [r3]						\n" /* The first item in pxCurrentTCB is the task top of stack. */
+	"	ldr r0, [r1]						\n"
+	"										\n"
+	"	ldmia r0!, {r4-r11, r14}			\n" /* Pop the core registers. */
+	"										\n"
+	"	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */
+	"	it eq								\n"
+	"	vldmiaeq r0!, {s16-s31}				\n"
+	"										\n"
+	"	msr psp, r0							\n"
+	"	isb									\n"
+	"										\n"
+	#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
+		#if WORKAROUND_PMU_CM001 == 1
+	"			push { r14 }				\n"
+	"			pop { pc }					\n"
+		#endif
+	#endif
+	"										\n"
+	"	bx r14								\n"
+	"										\n"
+	"	.align 4							\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB	\n"
+	::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
+	);
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
+	executes all interrupts must be unmasked.  There is therefore no need to
+	save and then restore the interrupt mask value as its value is already
+	known. */
+	portDISABLE_INTERRUPTS();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE == 1 )
+
+	__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+	TickType_t xModifiableIdleTime;
+
+		/* Make sure the SysTick reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
+		is accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+		/* Calculate the reload value required to wait xExpectedIdleTime
+		tick periods.  -1 is used because this code will execute part way
+		through one of the tick periods. */
+		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+		if( ulReloadValue > ulStoppedTimerCompensation )
+		{
+			ulReloadValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Enter a critical section but don't use the taskENTER_CRITICAL()
+		method as that will mask interrupts that should exit sleep mode. */
+		__asm volatile( "cpsid i" ::: "memory" );
+		__asm volatile( "dsb" );
+		__asm volatile( "isb" );
+
+		/* If a context switch is pending or a task is waiting for the scheduler
+		to be unsuspended then abandon the low power entry. */
+		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+		{
+			/* Restart from whatever is left in the count register to complete
+			this tick period. */
+			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Reset the reload register to the value required for normal tick
+			periods. */
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Re-enable interrupts - see comments above the cpsid instruction()
+			above. */
+			__asm volatile( "cpsie i" ::: "memory" );
+		}
+		else
+		{
+			/* Set the new reload value. */
+			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+			/* Clear the SysTick count flag and set the count value back to
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+			set its parameter to 0 to indicate that its implementation contains
+			its own wait for interrupt or wait for event instruction, and so wfi
+			should not be executed again.  However, the original expected idle
+			time variable must remain unmodified, so a copy is taken. */
+			xModifiableIdleTime = xExpectedIdleTime;
+			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+			if( xModifiableIdleTime > 0 )
+			{
+				__asm volatile( "dsb" ::: "memory" );
+				__asm volatile( "wfi" );
+				__asm volatile( "isb" );
+			}
+			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+			/* Re-enable interrupts to allow the interrupt that brought the MCU
+			out of sleep mode to execute immediately.  see comments above
+			__disable_interrupt() call above. */
+			__asm volatile( "cpsie i" ::: "memory" );
+			__asm volatile( "dsb" );
+			__asm volatile( "isb" );
+
+			/* Disable interrupts again because the clock is about to be stopped
+			and interrupts that execute while the clock is stopped will increase
+			any slippage between the time maintained by the RTOS and calendar
+			time. */
+			__asm volatile( "cpsid i" ::: "memory" );
+			__asm volatile( "dsb" );
+			__asm volatile( "isb" );
+
+			/* Disable the SysTick clock without reading the
+			portNVIC_SYSTICK_CTRL_REG register to ensure the
+			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+			the time the SysTick is stopped for is accounted for as best it can
+			be, but using the tickless mode will inevitably result in some tiny
+			drift of the time maintained by the kernel with respect to calendar
+			time*/
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+			/* Determine if the SysTick clock has already counted to zero and
+			been set back to the current reload value (the reload back being
+			correct for the entire expected idle time) or if the SysTick is yet
+			to count to zero (in which case an interrupt other than the SysTick
+			must have brought the system out of sleep mode). */
+			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			{
+				uint32_t ulCalculatedLoadValue;
+
+				/* The tick interrupt is already pending, and the SysTick count
+				reloaded with ulReloadValue.  Reset the
+				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+				period. */
+				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+				/* Don't allow a tiny value, or values that have somehow
+				underflowed because the post sleep hook did something
+				that took too long. */
+				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+				{
+					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+				}
+
+				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+				/* As the pending tick will be processed as soon as this
+				function exits, the tick value maintained by the tick is stepped
+				forward by one less than the time spent waiting. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				Work out how long the sleep lasted rounded to complete tick
+				periods (not the ulReload value which accounted for part
+				ticks). */
+				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+				/* How many complete tick periods passed while the processor
+				was waiting? */
+				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+				/* The reload value is set to whatever fraction of a single tick
+				period remains. */
+				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+			}
+
+			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+			value. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+			vTaskStepTick( ulCompleteTickPeriods );
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Exit with interrpts enabled. */
+			__asm volatile( "cpsie i" ::: "memory" );
+		}
+	}
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
+{
+	/* Calculate the constants required to configure the tick interrupt. */
+	#if( configUSE_TICKLESS_IDLE == 1 )
+	{
+		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+	}
+	#endif /* configUSE_TICKLESS_IDLE */
+
+	/* Stop and clear the SysTick. */
+	portNVIC_SYSTICK_CTRL_REG = 0UL;
+	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+/* This is a naked function. */
+static void vPortEnableVFP( void )
+{
+	__asm volatile
+	(
+		"	ldr.w r0, =0xE000ED88		\n" /* The FPU enable bits are in the CPACR. */
+		"	ldr r1, [r0]				\n"
+		"								\n"
+		"	orr r1, r1, #( 0xf << 20 )	\n" /* Enable CP10 and CP11 coprocessors, then save back. */
+		"	str r1, [r0]				\n"
+		"	bx r14						"
+	);
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredictable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
new file mode 100644
index 0000000..868d384
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
@@ -0,0 +1,243 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD() 															\
+{																				\
+	/* Set a PendSV to request a context switch. */								\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
+																				\
+	/* Barriers are normally not required but do ensure the code is completely	\
+	within the specified behaviour for the architecture. */						\
+	__asm volatile( "dsb" ::: "memory" );										\
+	__asm volatile( "isb" );													\
+}
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
+#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()					vPortSetBASEPRI(0)
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Generic helper function. */
+	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+	{
+	uint8_t ucReturn;
+
+		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+		return ucReturn;
+	}
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE	__inline
+
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE inline __attribute__(( always_inline))
+#endif
+
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+uint32_t ulCurrentInterrupt;
+BaseType_t xReturn;
+
+	/* Obtain the number of the currently executing interrupt. */
+	__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+	if( ulCurrentInterrupt == 0 )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	return xReturn;
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+uint32_t ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mov %0, %1												\n"	\
+		"	msr basepri, %0											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mrs %0, basepri											\n" \
+		"	mov %1, %2												\n"	\
+		"	msr basepri, %1											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+
+	/* This return will not be reached but is necessary to prevent compiler
+	warnings. */
+	return ulOriginalBASEPRI;
+}
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+	__asm volatile
+	(
+		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c
new file mode 100644
index 0000000..a09da15
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c
@@ -0,0 +1,851 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM3 port.
+ *----------------------------------------------------------*/
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __VFP_FP__
+	#error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK	( 0 )
+#endif
+
+/* Constants required to access and manipulate the NVIC. */
+#define portNVIC_SYSTICK_CTRL_REG				( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG				( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG		( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG					( *	( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSPRI1_REG					( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
+#define portNVIC_SYS_CTRL_STATE_REG				( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
+#define portNVIC_MEM_FAULT_ENABLE				( 1UL << 16UL )
+
+/* Constants required to access and manipulate the MPU. */
+#define portMPU_TYPE_REG						( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_REGION_BASE_ADDRESS_REG			( * ( ( volatile uint32_t * ) 0xe000ed9C ) )
+#define portMPU_REGION_ATTRIBUTE_REG			( * ( ( volatile uint32_t * ) 0xe000edA0 ) )
+#define portMPU_CTRL_REG						( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portEXPECTED_MPU_TYPE_VALUE				( 8UL << 8UL ) /* 8 regions, unified. */
+#define portMPU_ENABLE							( 0x01UL )
+#define portMPU_BACKGROUND_ENABLE				( 1UL << 2UL )
+#define portPRIVILEGED_EXECUTION_START_ADDRESS	( 0UL )
+#define portMPU_REGION_VALID					( 0x10UL )
+#define portMPU_REGION_ENABLE					( 0x01UL )
+#define portPERIPHERALS_START_ADDRESS			0x40000000UL
+#define portPERIPHERALS_END_ADDRESS				0x5FFFFFFFUL
+
+/* Constants required to access and manipulate the SysTick. */
+#define portNVIC_SYSTICK_INT					( 0x00000002UL )
+#define portNVIC_SYSTICK_ENABLE					( 0x00000001UL )
+#define portNVIC_PENDSV_PRI						( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portNVIC_SVC_PRI						( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR								( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS				( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR						( 0x01000000UL )
+#define portINITIAL_EXC_RETURN					( 0xfffffffdUL )
+#define portINITIAL_CONTROL_IF_UNPRIVILEGED		( 0x03 )
+#define portINITIAL_CONTROL_IF_PRIVILEGED		( 0x02 )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Offsets in the stack to the parameters when inside the SVC handler. */
+#define portOFFSET_TO_PC						( 6 )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
+
+/*
+ * Configure a number of standard MPU regions that are used by all tasks.
+ */
+static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the smallest MPU region size that a given number of bytes will fit
+ * into.  The region size is returned as the value that should be programmed
+ * into the region attribute register for that region.
+ */
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Standard FreeRTOS exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+void xPortSysTickHandler( void )  __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;
+void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/*
+ * Starts the scheduler by restoring the context of the first task to run.
+ */
+static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/*
+ * C portion of the SVC handler.  The SVC handler is split between an asm entry
+ * and a C wrapper for simplicity of coding and maintenance.
+ */
+static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;
+
+/*
+ * Function to enable the VFP.
+ */
+ static void vPortEnableVFP( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable.  Note this is not saved as part of the task context as context
+switches can only occur when uxCriticalNesting is zero. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = 0;	/* LR */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+
+	/* A save method is being used that requires each task to maintain its
+	own exec return value. */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+	pxTopOfStack -= 9;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	if( xRunPrivileged == pdTRUE )
+	{
+		*pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
+	}
+	else
+	{
+		*pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
+	}
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+	/* Assumes psp was in use. */
+	__asm volatile
+	(
+		#ifndef USE_PROCESS_STACK	/* Code should not be required if a main() is using the process stack. */
+			"	tst lr, #4						\n"
+			"	ite eq							\n"
+			"	mrseq r0, msp					\n"
+			"	mrsne r0, psp					\n"
+		#else
+			"	mrs r0, psp						\n"
+		#endif
+			"	b %0							\n"
+			::"i"(prvSVCHandler):"r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+static void prvSVCHandler(	uint32_t *pulParam )
+{
+uint8_t ucSVCNumber;
+
+	/* The stack contains: r0, r1, r2, r3, r12, r14, the return address and
+	xPSR.  The first argument (r0) is pulParam[ 0 ]. */
+	ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];
+	switch( ucSVCNumber )
+	{
+		case portSVC_START_SCHEDULER	:	portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
+											prvRestoreContextOfFirstTask();
+											break;
+
+		case portSVC_YIELD				:	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+											/* Barriers are normally not required
+											but do ensure the code is completely
+											within the specified behaviour for the
+											architecture. */
+											__asm volatile( "dsb" ::: "memory" );
+											__asm volatile( "isb" );
+
+											break;
+
+		case portSVC_RAISE_PRIVILEGE	:	__asm volatile
+											(
+												"	mrs r1, control		\n" /* Obtain current control value. */
+												"	bic r1, #1			\n" /* Set privilege bit. */
+												"	msr control, r1		\n" /* Write back new control value. */
+												::: "r1", "memory"
+											);
+											break;
+
+		default							:	/* Unknown SVC call. */
+											break;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvRestoreContextOfFirstTask( void )
+{
+	__asm volatile
+	(
+		"	ldr r0, =0xE000ED08				\n" /* Use the NVIC offset register to locate the stack. */
+		"	ldr r0, [r0]					\n"
+		"	ldr r0, [r0]					\n"
+		"	msr msp, r0						\n" /* Set the msp back to the start of the stack. */
+		"	ldr	r3, pxCurrentTCBConst2		\n" /* Restore the context. */
+		"	ldr r1, [r3]					\n"
+		"	ldr r0, [r1]					\n" /* The first item in the TCB is the task top of stack. */
+		"	add r1, r1, #4					\n" /* Move onto the second item in the TCB... */
+		"	ldr r2, =0xe000ed9c				\n" /* Region Base Address register. */
+		"	ldmia r1!, {r4-r11}				\n" /* Read 4 sets of MPU registers. */
+		"	stmia r2!, {r4-r11}				\n" /* Write 4 sets of MPU registers. */
+		"	ldmia r0!, {r3-r11, r14}		\n" /* Pop the registers that are not automatically saved on exception entry. */
+		"	msr control, r3					\n"
+		"	msr psp, r0						\n" /* Restore the task stack pointer. */
+		"	mov r0, #0						\n"
+		"	msr	basepri, r0					\n"
+		"	bx r14							\n"
+		"									\n"
+		"	.align 4						\n"
+		"pxCurrentTCBConst2: .word pxCurrentTCB	\n"
+	);
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See
+	http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+	configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the same priority as the kernel, and the SVC
+	handler higher priority so it can be used to exit a critical section (where
+	lower priorities are masked). */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Configure the regions in the MPU that are common to all tasks. */
+	prvSetupMPU();
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Ensure the VFP is enabled - it should be anyway. */
+	vPortEnableVFP();
+
+	/* Lazy save always. */
+	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+	/* Start the first task.  This also clears the bit that indicates the FPU is
+	in use in case the FPU was used before the scheduler was started - which
+	would otherwise result in the unnecessary leaving of space in the SVC stack
+	for lazy saving of FPU registers. */
+	__asm volatile(
+					" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
+					" ldr r0, [r0] 			\n"
+					" ldr r0, [r0] 			\n"
+					" msr msp, r0			\n" /* Set the msp back to the start of the stack. */
+					" mov r0, #0			\n" /* Clear the bit that indicates the FPU is in use, see comment above. */
+					" msr control, r0		\n"
+					" cpsie i				\n" /* Globally enable interrupts. */
+					" cpsie f				\n"
+					" dsb					\n"
+					" isb					\n"
+					" svc %0				\n" /* System call to start first task. */
+					" nop					\n"
+					:: "i" (portSVC_START_SCHEDULER) : "memory" );
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+	vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+	/* This is a naked function. */
+
+	__asm volatile
+	(
+		"	mrs r0, psp							\n"
+		"	isb									\n"
+		"										\n"
+		"	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
+		"	ldr	r2, [r3]						\n"
+		"										\n"
+		"	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, push high vfp registers. */
+		"	it eq								\n"
+		"	vstmdbeq r0!, {s16-s31}				\n"
+		"										\n"
+		"	mrs r1, control						\n"
+		"	stmdb r0!, {r1, r4-r11, r14}		\n" /* Save the remaining registers. */
+		"	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */
+		"										\n"
+		"	stmdb sp!, {r0, r3}					\n"
+		"	mov r0, %0							\n"
+		"	msr basepri, r0						\n"
+		"	dsb									\n"
+		"	isb									\n"
+		"	bl vTaskSwitchContext				\n"
+		"	mov r0, #0							\n"
+		"	msr basepri, r0						\n"
+		"	ldmia sp!, {r0, r3}					\n"
+		"										\n" /* Restore the context. */
+		"	ldr r1, [r3]						\n"
+		"	ldr r0, [r1]						\n" /* The first item in the TCB is the task top of stack. */
+		"	add r1, r1, #4						\n" /* Move onto the second item in the TCB... */
+		"	ldr r2, =0xe000ed9c					\n" /* Region Base Address register. */
+		"	ldmia r1!, {r4-r11}					\n" /* Read 4 sets of MPU registers. */
+		"	stmia r2!, {r4-r11}					\n" /* Write 4 sets of MPU registers. */
+		"	ldmia r0!, {r3-r11, r14}			\n" /* Pop the registers that are not automatically saved on exception entry. */
+		"	msr control, r3						\n"
+		"										\n"
+		"	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */
+		"	it eq								\n"
+		"	vldmiaeq r0!, {s16-s31}				\n"
+		"										\n"
+		"	msr psp, r0							\n"
+		"	bx r14								\n"
+		"										\n"
+		"	.align 4							\n"
+		"pxCurrentTCBConst: .word pxCurrentTCB	\n"
+		::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
+	);
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+uint32_t ulDummy;
+
+	ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
+{
+	/* Stop and clear the SysTick. */
+	portNVIC_SYSTICK_CTRL_REG = 0UL;
+	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );
+}
+/*-----------------------------------------------------------*/
+
+/* This is a naked function. */
+static void vPortEnableVFP( void )
+{
+	__asm volatile
+	(
+		"	ldr.w r0, =0xE000ED88		\n" /* The FPU enable bits are in the CPACR. */
+		"	ldr r1, [r0]				\n"
+		"								\n"
+		"	orr r1, r1, #( 0xf << 20 )	\n" /* Enable CP10 and CP11 coprocessors, then save back. */
+		"	str r1, [r0]				\n"
+		"	bx r14						"
+	);
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupMPU( void )
+{
+extern uint32_t __privileged_functions_end__[];
+extern uint32_t __FLASH_segment_start__[];
+extern uint32_t __FLASH_segment_end__[];
+extern uint32_t __privileged_data_start__[];
+extern uint32_t __privileged_data_end__[];
+
+	/* Check the expected MPU is present. */
+	if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+	{
+		/* First setup the entire flash for unprivileged read only access. */
+		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
+											( portMPU_REGION_VALID ) |
+											( portUNPRIVILEGED_FLASH_REGION );
+
+		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_READ_ONLY ) |
+										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+										( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
+										( portMPU_REGION_ENABLE );
+
+		/* Setup the first nK for privileged only access (even though less
+		than 10K is actually being used).  This is where the kernel code is
+		placed. */
+		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
+											( portMPU_REGION_VALID ) |
+											( portPRIVILEGED_FLASH_REGION );
+
+		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
+										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+										( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
+										( portMPU_REGION_ENABLE );
+
+		/* Setup the privileged data RAM region.  This is where the kernel data
+		is placed. */
+		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
+											( portMPU_REGION_VALID ) |
+											( portPRIVILEGED_RAM_REGION );
+
+		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+										prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
+										( portMPU_REGION_ENABLE );
+
+		/* By default allow everything to access the general peripherals.  The
+		system peripherals and registers are protected. */
+		portMPU_REGION_BASE_ADDRESS_REG =	( portPERIPHERALS_START_ADDRESS ) |
+											( portMPU_REGION_VALID ) |
+											( portGENERAL_PERIPHERALS_REGION );
+
+		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
+										( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
+										( portMPU_REGION_ENABLE );
+
+		/* Enable the memory fault exception. */
+		portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
+
+		/* Enable the MPU with the background region configured. */
+		portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
+{
+uint32_t ulRegionSize, ulReturnValue = 4;
+
+	/* 32 is the smallest region size, 31 is the largest valid value for
+	ulReturnValue. */
+	for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
+	{
+		if( ulActualSizeInBytes <= ulRegionSize )
+		{
+			break;
+		}
+		else
+		{
+			ulReturnValue++;
+		}
+	}
+
+	/* Shift the code by one before returning so it can be written directly
+	into the the correct bit position of the attribute register. */
+	return ( ulReturnValue << 1UL );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control							\n" /* r0 = CONTROL. */
+	"	tst r0, #1								\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	"	ite ne									\n"
+	"	movne r0, #0							\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	"	moveq r0, #1							\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	"	bx lr									\n" /* Return. */
+	"											\n"
+	"	.align 4								\n"
+	::: "r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+	__asm volatile
+	(
+	"	mrs r0, control							\n" /* r0 = CONTROL. */
+	"	orr r0, #1								\n" /* r0 = r0 | 1. */
+	"	msr control, r0							\n" /* CONTROL = r0. */
+	"	bx lr									\n" /* Return to the caller. */
+	:::"r0", "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+{
+extern uint32_t __SRAM_segment_start__[];
+extern uint32_t __SRAM_segment_end__[];
+extern uint32_t __privileged_data_start__[];
+extern uint32_t __privileged_data_end__[];
+int32_t lIndex;
+uint32_t ul;
+
+	if( xRegions == NULL )
+	{
+		/* No MPU regions are specified so allow access to all RAM. */
+		xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
+				( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
+				( portMPU_REGION_VALID ) |
+				( portSTACK_REGION );
+
+		xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
+				( portMPU_REGION_READ_WRITE ) |
+				( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+				( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
+				( portMPU_REGION_ENABLE );
+
+		/* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
+		just removed the privileged only parameters. */
+		xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
+				( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
+				( portMPU_REGION_VALID ) |
+				( portSTACK_REGION + 1 );
+
+		xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
+				( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+				( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+				prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
+				( portMPU_REGION_ENABLE );
+
+		/* Invalidate all other regions. */
+		for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+		{
+			xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+			xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
+		}
+	}
+	else
+	{
+		/* This function is called automatically when the task is created - in
+		which case the stack region parameters will be valid.  At all other
+		times the stack parameters will not be valid and it is assumed that the
+		stack region has already been configured. */
+		if( ulStackDepth > 0 )
+		{
+			/* Define the region that allows access to the stack. */
+			xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
+					( ( uint32_t ) pxBottomOfStack ) |
+					( portMPU_REGION_VALID ) |
+					( portSTACK_REGION ); /* Region number. */
+
+			xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
+					( portMPU_REGION_READ_WRITE ) | /* Read and write. */
+					( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
+					( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+					( portMPU_REGION_ENABLE );
+		}
+
+		lIndex = 0;
+
+		for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+		{
+			if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
+			{
+				/* Translate the generic region definition contained in
+				xRegions into the CM3 specific MPU settings that are then
+				stored in xMPUSettings. */
+				xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
+						( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
+						( portMPU_REGION_VALID ) |
+						( portSTACK_REGION + ul ); /* Region number. */
+
+				xMPUSettings->xRegion[ ul ].ulRegionAttribute =
+						( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
+						( xRegions[ lIndex ].ulParameters ) |
+						( portMPU_REGION_ENABLE );
+			}
+			else
+			{
+				/* Invalidate the region. */
+				xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+				xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
+			}
+
+			lIndex++;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredicable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+/*-----------------------------------------------------------*/
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
new file mode 100644
index 0000000..ff8ddb6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -0,0 +1,301 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* MPU specific constants. */
+#define portUSING_MPU_WRAPPERS		1
+#define portPRIVILEGE_BIT			( 0x80000000UL )
+
+#define portMPU_REGION_READ_WRITE				( 0x03UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY		( 0x05UL << 24UL )
+#define portMPU_REGION_READ_ONLY				( 0x06UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE	( 0x01UL << 24UL )
+#define portMPU_REGION_CACHEABLE_BUFFERABLE		( 0x07UL << 16UL )
+#define portMPU_REGION_EXECUTE_NEVER			( 0x01UL << 28UL )
+
+#define portUNPRIVILEGED_FLASH_REGION		( 0UL )
+#define portPRIVILEGED_FLASH_REGION			( 1UL )
+#define portPRIVILEGED_RAM_REGION			( 2UL )
+#define portGENERAL_PERIPHERALS_REGION		( 3UL )
+#define portSTACK_REGION					( 4UL )
+#define portFIRST_CONFIGURABLE_REGION	    ( 5UL )
+#define portLAST_CONFIGURABLE_REGION		( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS		( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS				( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
+
+typedef struct MPU_REGION_REGISTERS
+{
+	uint32_t ulRegionBaseAddress;
+	uint32_t ulRegionAttribute;
+} xMPU_REGION_REGISTERS;
+
+/* Plus 1 to create space for the stack region. */
+typedef struct MPU_SETTINGS
+{
+	xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
+} xMPU_SETTINGS;
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+/* SVC numbers for various services. */
+#define portSVC_START_SCHEDULER				0
+#define portSVC_YIELD						1
+#define portSVC_RAISE_PRIVILEGE				2
+
+/* Scheduler utilities. */
+
+#define portYIELD()				__asm volatile ( "	SVC	%0	\n" :: "i" (portSVC_YIELD) : "memory" )
+#define portYIELD_WITHIN_API() 													\
+{																				\
+	/* Set a PendSV to request a context switch. */								\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
+																				\
+	/* Barriers are normally not required but do ensure the code is completely	\
+	within the specified behaviour for the architecture. */						\
+	__asm volatile( "dsb" ::: "memory" );										\
+	__asm volatile( "isb" );													\
+}
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
+#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()					vPortSetBASEPRI(0)
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Generic helper function. */
+	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+	{
+	uint8_t ucReturn;
+
+		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+		return ucReturn;
+	}
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE	__inline
+
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE inline __attribute__(( always_inline))
+#endif
+/*-----------------------------------------------------------*/
+
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED()			xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+*/
+#define portRAISE_PRIVILEGE()		__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE()		vResetPrivilege()
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+uint32_t ulCurrentInterrupt;
+BaseType_t xReturn;
+
+	/* Obtain the number of the currently executing interrupt. */
+	__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+	if( ulCurrentInterrupt == 0 )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	return xReturn;
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+uint32_t ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mov %0, %1												\n"	\
+		"	msr basepri, %0											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mrs %0, basepri											\n" \
+		"	mov %1, %2												\n"	\
+		"	msr basepri, %1											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+
+	/* This return will not be reached but is necessary to prevent compiler
+	warnings. */
+	return ulOriginalBASEPRI;
+}
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+	__asm volatile
+	(
+		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM7/ReadMe.txt b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM7/ReadMe.txt
new file mode 100644
index 0000000..d661449
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM7/ReadMe.txt
@@ -0,0 +1,18 @@
+There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers.
+The best option depends on the revision of the ARM Cortex-M7 core in use.  The
+revision is specified by an 'r' number, and a 'p' number, so will look something
+like 'r0p1'.  Check the documentation for the microcontroller in use to find the 
+revision of the Cortex-M7 core used in that microcontroller.  If in doubt, use 
+the FreeRTOS port provided specifically for r0p1 revisions, as that can be used
+with all core revisions.
+
+The first option is to use the ARM Cortex-M4F port, and the second option is to
+use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround.
+
+If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be
+used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in 
+the /FreeRTOS/Source/portable/GCC/ARM_CM4F directory.
+
+If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM
+Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1
+directory.
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c
new file mode 100644
index 0000000..4851012
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c
@@ -0,0 +1,765 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM4F port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __VFP_FP__
+	#error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK					( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS			( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR					( 0x01000000 )
+#define portINITIAL_EXC_RETURN				( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK		( ( StackType_t ) 0xfffffffeUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR			( 45UL )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__ (( naked ));
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void ) __attribute__ (( naked ));
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
+
+/*
+ * Function to enable the VFP.
+ */
+static void vPortEnableVFP( void ) __attribute__ (( naked ));
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+
+	/* Offset added to account for the way the MCU uses the stack on entry/exit
+	of interrupts, and to ensure alignment. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+
+	/* Save code space by skipping register initialisation. */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+
+	/* A save method is being used that requires each task to maintain its
+	own exec return value. */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0;
+
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		started to remove a compiler warning about the function being defined
+		but never called.  ulDummy is used purely to quieten other warnings
+		about code appearing after this function is called - making ulDummy
+		volatile makes the compiler think the function could return and
+		therefore not output an 'unreachable code' warning for code that appears
+		after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+	__asm volatile (
+					"	ldr	r3, pxCurrentTCBConst2		\n" /* Restore the context. */
+					"	ldr r1, [r3]					\n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+					"	ldr r0, [r1]					\n" /* The first item in pxCurrentTCB is the task top of stack. */
+					"	ldmia r0!, {r4-r11, r14}		\n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+					"	msr psp, r0						\n" /* Restore the task stack pointer. */
+					"	isb								\n"
+					"	mov r0, #0 						\n"
+					"	msr	basepri, r0					\n"
+					"	bx r14							\n"
+					"									\n"
+					"	.align 4						\n"
+					"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+				);
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortStartFirstTask( void )
+{
+	/* Start the first task.  This also clears the bit that indicates the FPU is
+	in use in case the FPU was used before the scheduler was started - which
+	would otherwise result in the unnecessary leaving of space in the SVC stack
+	for lazy saving of FPU registers. */
+	__asm volatile(
+					" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
+					" ldr r0, [r0] 			\n"
+					" ldr r0, [r0] 			\n"
+					" msr msp, r0			\n" /* Set the msp back to the start of the stack. */
+					" mov r0, #0			\n" /* Clear the bit that indicates the FPU is in use, see comment above. */
+					" msr control, r0		\n"
+					" cpsie i				\n" /* Globally enable interrupts. */
+					" cpsie f				\n"
+					" dsb					\n"
+					" isb					\n"
+					" svc 0					\n" /* System call to start first task. */
+					" nop					\n"
+				);
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Ensure the VFP is enabled - it should be anyway. */
+	vPortEnableVFP();
+
+	/* Lazy save always. */
+	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+	/* Start the first task. */
+	prvPortStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing!  Call the task
+	exit error function to prevent compiler warnings about a static function
+	not being called in the case that the application writer overrides this
+	functionality by defining configTASK_RETURN_ADDRESS.  Call
+	vTaskSwitchContext() so link time optimisation does not remove the
+	symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+	/* This is a naked function. */
+
+	__asm volatile
+	(
+	"	mrs r0, psp							\n"
+	"	isb									\n"
+	"										\n"
+	"	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
+	"	ldr	r2, [r3]						\n"
+	"										\n"
+	"	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, push high vfp registers. */
+	"	it eq								\n"
+	"	vstmdbeq r0!, {s16-s31}				\n"
+	"										\n"
+	"	stmdb r0!, {r4-r11, r14}			\n" /* Save the core registers. */
+	"	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */
+	"										\n"
+	"	stmdb sp!, {r0, r3}					\n"
+	"	mov r0, %0 							\n"
+	"	cpsid i								\n" /* Errata workaround. */
+	"	msr basepri, r0						\n"
+	"	dsb									\n"
+	"	isb									\n"
+	"	cpsie i								\n" /* Errata workaround. */
+	"	bl vTaskSwitchContext				\n"
+	"	mov r0, #0							\n"
+	"	msr basepri, r0						\n"
+	"	ldmia sp!, {r0, r3}					\n"
+	"										\n"
+	"	ldr r1, [r3]						\n" /* The first item in pxCurrentTCB is the task top of stack. */
+	"	ldr r0, [r1]						\n"
+	"										\n"
+	"	ldmia r0!, {r4-r11, r14}			\n" /* Pop the core registers. */
+	"										\n"
+	"	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */
+	"	it eq								\n"
+	"	vldmiaeq r0!, {s16-s31}				\n"
+	"										\n"
+	"	msr psp, r0							\n"
+	"	isb									\n"
+	"										\n"
+	#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
+		#if WORKAROUND_PMU_CM001 == 1
+	"			push { r14 }				\n"
+	"			pop { pc }					\n"
+		#endif
+	#endif
+	"										\n"
+	"	bx r14								\n"
+	"										\n"
+	"	.align 4							\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB	\n"
+	::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
+	);
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
+	executes all interrupts must be unmasked.  There is therefore no need to
+	save and then restore the interrupt mask value as its value is already
+	known. */
+	portDISABLE_INTERRUPTS();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE == 1 )
+
+	__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+	TickType_t xModifiableIdleTime;
+
+		/* Make sure the SysTick reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
+		is accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+		/* Calculate the reload value required to wait xExpectedIdleTime
+		tick periods.  -1 is used because this code will execute part way
+		through one of the tick periods. */
+		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+		if( ulReloadValue > ulStoppedTimerCompensation )
+		{
+			ulReloadValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Enter a critical section but don't use the taskENTER_CRITICAL()
+		method as that will mask interrupts that should exit sleep mode. */
+		__asm volatile( "cpsid i" ::: "memory" );
+		__asm volatile( "dsb" );
+		__asm volatile( "isb" );
+
+		/* If a context switch is pending or a task is waiting for the scheduler
+		to be unsuspended then abandon the low power entry. */
+		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+		{
+			/* Restart from whatever is left in the count register to complete
+			this tick period. */
+			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Reset the reload register to the value required for normal tick
+			periods. */
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Re-enable interrupts - see comments above the cpsid instruction()
+			above. */
+			__asm volatile( "cpsie i" ::: "memory" );
+		}
+		else
+		{
+			/* Set the new reload value. */
+			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+			/* Clear the SysTick count flag and set the count value back to
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+			set its parameter to 0 to indicate that its implementation contains
+			its own wait for interrupt or wait for event instruction, and so wfi
+			should not be executed again.  However, the original expected idle
+			time variable must remain unmodified, so a copy is taken. */
+			xModifiableIdleTime = xExpectedIdleTime;
+			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+			if( xModifiableIdleTime > 0 )
+			{
+				__asm volatile( "dsb" ::: "memory" );
+				__asm volatile( "wfi" );
+				__asm volatile( "isb" );
+			}
+			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+			/* Re-enable interrupts to allow the interrupt that brought the MCU
+			out of sleep mode to execute immediately.  see comments above
+			__disable_interrupt() call above. */
+			__asm volatile( "cpsie i" ::: "memory" );
+			__asm volatile( "dsb" );
+			__asm volatile( "isb" );
+
+			/* Disable interrupts again because the clock is about to be stopped
+			and interrupts that execute while the clock is stopped will increase
+			any slippage between the time maintained by the RTOS and calendar
+			time. */
+			__asm volatile( "cpsid i" ::: "memory" );
+			__asm volatile( "dsb" );
+			__asm volatile( "isb" );
+
+			/* Disable the SysTick clock without reading the
+			portNVIC_SYSTICK_CTRL_REG register to ensure the
+			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+			the time the SysTick is stopped for is accounted for as best it can
+			be, but using the tickless mode will inevitably result in some tiny
+			drift of the time maintained by the kernel with respect to calendar
+			time*/
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+			/* Determine if the SysTick clock has already counted to zero and
+			been set back to the current reload value (the reload back being
+			correct for the entire expected idle time) or if the SysTick is yet
+			to count to zero (in which case an interrupt other than the SysTick
+			must have brought the system out of sleep mode). */
+			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			{
+				uint32_t ulCalculatedLoadValue;
+
+				/* The tick interrupt is already pending, and the SysTick count
+				reloaded with ulReloadValue.  Reset the
+				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+				period. */
+				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+				/* Don't allow a tiny value, or values that have somehow
+				underflowed because the post sleep hook did something
+				that took too long. */
+				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+				{
+					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+				}
+
+				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+				/* As the pending tick will be processed as soon as this
+				function exits, the tick value maintained by the tick is stepped
+				forward by one less than the time spent waiting. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				Work out how long the sleep lasted rounded to complete tick
+				periods (not the ulReload value which accounted for part
+				ticks). */
+				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+				/* How many complete tick periods passed while the processor
+				was waiting? */
+				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+				/* The reload value is set to whatever fraction of a single tick
+				period remains. */
+				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+			}
+
+			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+			value. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+			vTaskStepTick( ulCompleteTickPeriods );
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Exit with interrpts enabled. */
+			__asm volatile( "cpsie i" ::: "memory" );
+		}
+	}
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
+{
+	/* Calculate the constants required to configure the tick interrupt. */
+	#if( configUSE_TICKLESS_IDLE == 1 )
+	{
+		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+	}
+	#endif /* configUSE_TICKLESS_IDLE */
+
+	/* Stop and clear the SysTick. */
+	portNVIC_SYSTICK_CTRL_REG = 0UL;
+	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+/* This is a naked function. */
+static void vPortEnableVFP( void )
+{
+	__asm volatile
+	(
+		"	ldr.w r0, =0xE000ED88		\n" /* The FPU enable bits are in the CPACR. */
+		"	ldr r1, [r0]				\n"
+		"								\n"
+		"	orr r1, r1, #( 0xf << 20 )	\n" /* Enable CP10 and CP11 coprocessors, then save back. */
+		"	str r1, [r0]				\n"
+		"	bx r14						"
+	);
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredictable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
new file mode 100644
index 0000000..1d7d653
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
@@ -0,0 +1,247 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD() 															\
+{																				\
+	/* Set a PendSV to request a context switch. */								\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
+																				\
+	/* Barriers are normally not required but do ensure the code is completely	\
+	within the specified behaviour for the architecture. */						\
+	__asm volatile( "dsb" ::: "memory" );										\
+	__asm volatile( "isb" );													\
+}
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
+#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()					vPortSetBASEPRI(0)
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Generic helper function. */
+	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+	{
+	uint8_t ucReturn;
+
+		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+		return ucReturn;
+	}
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE	__inline
+
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE inline __attribute__(( always_inline))
+#endif
+
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+uint32_t ulCurrentInterrupt;
+BaseType_t xReturn;
+
+	/* Obtain the number of the currently executing interrupt. */
+	__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+	if( ulCurrentInterrupt == 0 )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	return xReturn;
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+uint32_t ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mov %0, %1												\n"	\
+		"	cpsid i													\n" \
+		"	msr basepri, %0											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		"	cpsie i													\n" \
+		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mrs %0, basepri											\n" \
+		"	mov %1, %2												\n"	\
+		"	cpsid i													\n" \
+		"	msr basepri, %1											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		"	cpsie i													\n" \
+		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+
+	/* This return will not be reached but is necessary to prevent compiler
+	warnings. */
+	return ulOriginalBASEPRI;
+}
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+	__asm volatile
+	(
+		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c
new file mode 100644
index 0000000..6269568
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c
@@ -0,0 +1,525 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
+	#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
+	#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configUNIQUE_INTERRUPT_PRIORITIES
+	#error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configSETUP_TICK_INTERRUPT
+	#error configSETUP_TICK_INTERRUPT() must be defined.  Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif /* configSETUP_TICK_INTERRUPT */
+
+#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/* In case security extensions are implemented. */
+#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+#endif
+
+/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
+portmacro.h. */
+#ifndef configCLEAR_TICK_INTERRUPT
+	#define configCLEAR_TICK_INTERRUPT()
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+this value. */
+#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
+
+/* In all GICs 255 can be written to the priority mask register to unmask all
+(but the lowest) interrupt priority. */
+#define portUNMASK_VALUE				( 0xFFUL )
+
+/* Tasks are not created with a floating point context, but can be given a
+floating point context after they have been created.  A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
+
+/* Constants required to setup the initial task context. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portINTERRUPT_ENABLE_BIT		( 0x80UL )
+#define portTHUMB_MODE_ADDRESS			( 0x01UL )
+
+/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
+point is zero. */
+#define portBINARY_POINT_BITS			( ( uint8_t ) 0x03 )
+
+/* Masks all bits in the APSR other than the mode bits. */
+#define portAPSR_MODE_BITS_MASK			( 0x1F )
+
+/* The value of the mode bits in the APSR when the CPU is executing in user
+mode. */
+#define portAPSR_USER_MODE				( 0x10 )
+
+/* The critical section macros only mask interrupts up to an application
+determined priority level.  Sometimes it is necessary to turn interrupt off in
+the CPU itself before modifying certain hardware registers. */
+#define portCPU_IRQ_DISABLE()										\
+	__asm volatile ( "CPSID i" ::: "memory" );						\
+	__asm volatile ( "DSB" );										\
+	__asm volatile ( "ISB" );
+
+#define portCPU_IRQ_ENABLE()										\
+	__asm volatile ( "CPSIE i" ::: "memory" );						\
+	__asm volatile ( "DSB" );										\
+	__asm volatile ( "ISB" );
+
+
+/* Macro to unmask all interrupt priorities. */
+#define portCLEAR_INTERRUPT_MASK()									\
+{																	\
+	portCPU_IRQ_DISABLE();											\
+	portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;			\
+	__asm volatile (	"DSB		\n"								\
+						"ISB		\n" );							\
+	portCPU_IRQ_ENABLE();											\
+}
+
+#define portINTERRUPT_PRIORITY_REGISTER_OFFSET		0x400UL
+#define portMAX_8_BIT_VALUE							( ( uint8_t ) 0xff )
+#define portBIT_0_SET								( ( uint8_t ) 0x01 )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case is messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing.  This function is necessarily written in
+ * assembly code so is implemented in portASM.s.
+ */
+extern void vPortRestoreTaskContext( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting.  This
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts.  As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then
+a floating point context must be saved and restored for the task. */
+uint32_t ulPortTaskHasFPUContext = pdFALSE;
+
+/* Set to 1 to pend a context switch from an ISR. */
+uint32_t ulPortYieldRequired = pdFALSE;
+
+/* Counts the interrupt nesting depth.  A context switch is only performed if
+if the nesting depth is 0. */
+uint32_t ulPortInterruptNesting = 0UL;
+
+/* Used in asm code. */
+__attribute__(( used )) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
+__attribute__(( used )) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
+__attribute__(( used )) const uint32_t ulICCPMR	= portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
+__attribute__(( used )) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro.
+
+	The fist real value on the stack is the status register, which is set for
+	system mode, with interrupts enabled.  A few NULLs are added first to ensure
+	GDB does not try decoding a non-existent return address. */
+	*pxTopOfStack = ( StackType_t ) NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+	{
+		/* The task will start in THUMB mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+
+	pxTopOfStack--;
+
+	/* Next the return address, which in this case is the start of the task. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+
+	/* Next all the registers other than the stack pointer. */
+	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The task will start with a critical nesting count of 0 as interrupts are
+	enabled. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+	pxTopOfStack--;
+
+	/* The task will start without a floating point context.  A task that uses
+	the floating point hardware must call vPortTaskUsesFPU() before executing
+	any floating point instructions. */
+	*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( ulPortInterruptNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+uint32_t ulAPSR, ulCycles = 8; /* 8 bits per byte. */
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine how many priority bits are implemented in the GIC.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to
+		all possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Shift to the least significant bits. */
+		while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
+		{
+			ucMaxPriorityValue >>= ( uint8_t ) 0x01;
+
+			/* If ulCycles reaches 0 then ucMaxPriorityValue must have been
+			read as 0, indicating a misconfiguration. */
+			ulCycles--;
+			if( ulCycles == 0 )
+			{
+				break;
+			}
+		}
+
+		/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
+		value. */
+		configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Only continue if the CPU is not in User mode.  The CPU must be in a
+	Privileged mode for the scheduler to start. */
+	__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );
+	ulAPSR &= portAPSR_MODE_BITS_MASK;
+	configASSERT( ulAPSR != portAPSR_USER_MODE );
+
+	if( ulAPSR != portAPSR_USER_MODE )
+	{
+		/* Only continue if the binary point value is set to its lowest possible
+		setting.  See the comments in vPortValidateInterruptPriority() below for
+		more information. */
+		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+
+		if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
+		{
+			/* Interrupts are turned off in the CPU itself to ensure tick does
+			not execute	while the scheduler is being started.  Interrupts are
+			automatically turned back on in the CPU when the first task starts
+			executing. */
+			portCPU_IRQ_DISABLE();
+
+			/* Start the timer that generates the tick ISR. */
+			configSETUP_TICK_INTERRUPT();
+
+			/* Start the first task executing. */
+			vPortRestoreTaskContext();
+		}
+	}
+
+	/* Will only get here if vTaskStartScheduler() was called with the CPU in
+	a non-privileged mode or the binary point register was not set to its lowest
+	possible value.  prvTaskExitError() is referenced to prevent a compiler
+	warning about it being defined but not referenced in the case that the user
+	defines their own exit address. */
+	( void ) prvTaskExitError;
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	/* Mask interrupts up to the max syscall interrupt priority. */
+	ulPortSetInterruptMask();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( ulCriticalNesting == 1 )
+	{
+		configASSERT( ulPortInterruptNesting == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as the critical section is being
+		exited. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then all interrupt
+		priorities must be re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Critical nesting has reached zero so all interrupt priorities
+			should be unmasked. */
+			portCLEAR_INTERRUPT_MASK();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void FreeRTOS_Tick_Handler( void )
+{
+	/* Set interrupt mask before altering scheduler structures.   The tick
+	handler runs at the lowest priority, so interrupts cannot already be masked,
+	so there is no need to save and restore the current mask value.  It is
+	necessary to turn off interrupts in the CPU itself while the ICCPMR is being
+	updated. */
+	portCPU_IRQ_DISABLE();
+	portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+	__asm volatile (	"dsb		\n"
+						"isb		\n" ::: "memory" );
+	portCPU_IRQ_ENABLE();
+
+	/* Increment the RTOS tick. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		ulPortYieldRequired = pdTRUE;
+	}
+
+	/* Ensure all interrupt priorities are active again. */
+	portCLEAR_INTERRUPT_MASK();
+	configCLEAR_TICK_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortTaskUsesFPU( void )
+{
+uint32_t ulInitialFPSCR = 0;
+
+	/* A task is registering the fact that it needs an FPU context.  Set the
+	FPU flag (which is saved as part of the task context). */
+	ulPortTaskHasFPUContext = pdTRUE;
+
+	/* Initialise the floating point status register. */
+	__asm volatile ( "FMXR 	FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMask( uint32_t ulNewMaskValue )
+{
+	if( ulNewMaskValue == pdFALSE )
+	{
+		portCLEAR_INTERRUPT_MASK();
+	}
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortSetInterruptMask( void )
+{
+uint32_t ulReturn;
+
+	/* Interrupt in the CPU must be turned off while the ICCPMR is being
+	updated. */
+	portCPU_IRQ_DISABLE();
+	if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
+	{
+		/* Interrupts were already masked. */
+		ulReturn = pdTRUE;
+	}
+	else
+	{
+		ulReturn = pdFALSE;
+		portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+		__asm volatile (	"dsb		\n"
+							"isb		\n" ::: "memory" );
+	}
+	portCPU_IRQ_ENABLE();
+
+	return ulReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+		/* The following assertion will fail if a service routine (ISR) for
+		an interrupt that has been assigned a priority above
+		configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+		function.  ISR safe FreeRTOS API functions must *only* be called
+		from interrupts that have been assigned a priority at or below
+		configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+		Numerically low interrupt priority numbers represent logically high
+		interrupt priorities, therefore the priority of the interrupt must
+		be set to a value equal to or numerically *higher* than
+		configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+		FreeRTOS maintains separate thread and ISR API functions to ensure
+		interrupt entry is as fast and simple as possible. */
+
+		configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+
+		/* Priority grouping:  The interrupt controller (GIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		The priority grouping is configured by the GIC's binary point register
+		(ICCBPR).  Writing 0 to ICCBPR will ensure it is set to its lowest
+		possible value (which may be above 0). */
+		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+	}
+
+#endif /* configASSERT_DEFINED */
+/*-----------------------------------------------------------*/
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S
new file mode 100644
index 0000000..8f37686
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S
@@ -0,0 +1,280 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	.text
+	.arm
+
+	.set SYS_MODE,	0x1f
+	.set SVC_MODE,	0x13
+	.set IRQ_MODE,	0x12
+
+	/* Hardware registers. */
+	.extern ulICCIAR
+	.extern ulICCEOIR
+	.extern ulICCPMR
+
+	/* Variables and functions. */
+	.extern ulMaxAPIPriorityMask
+	.extern _freertos_vector_table
+	.extern pxCurrentTCB
+	.extern vTaskSwitchContext
+	.extern vApplicationIRQHandler
+	.extern ulPortInterruptNesting
+	.extern ulPortTaskHasFPUContext
+
+	.global FreeRTOS_IRQ_Handler
+	.global FreeRTOS_SWI_Handler
+	.global vPortRestoreTaskContext
+
+.macro portSAVE_CONTEXT
+
+	/* Save the LR and SPSR onto the system mode stack before switching to
+	system mode to save the remaining system mode registers. */
+	SRSDB	sp!, #SYS_MODE
+	CPS		#SYS_MODE
+	PUSH	{R0-R12, R14}
+
+	/* Push the critical nesting count. */
+	LDR		R2, ulCriticalNestingConst
+	LDR		R1, [R2]
+	PUSH	{R1}
+
+	/* Does the task have a floating point context that needs saving?  If
+	ulPortTaskHasFPUContext is 0 then no. */
+	LDR		R2, ulPortTaskHasFPUContextConst
+	LDR		R3, [R2]
+	CMP		R3, #0
+
+	/* Save the floating point context, if any. */
+	FMRXNE  R1,  FPSCR
+	VPUSHNE {D0-D15}
+	/*VPUSHNE	{D16-D31}*/
+	PUSHNE	{R1}
+
+	/* Save ulPortTaskHasFPUContext itself. */
+	PUSH	{R3}
+
+	/* Save the stack pointer in the TCB. */
+	LDR		R0, pxCurrentTCBConst
+	LDR		R1, [R0]
+	STR		SP, [R1]
+
+	.endm
+
+; /**********************************************************************/
+
+.macro portRESTORE_CONTEXT
+
+	/* Set the SP to point to the stack of the task being restored. */
+	LDR		R0, pxCurrentTCBConst
+	LDR		R1, [R0]
+	LDR		SP, [R1]
+
+	/* Is there a floating point context to restore?  If the restored
+	ulPortTaskHasFPUContext is zero then no. */
+	LDR		R0, ulPortTaskHasFPUContextConst
+	POP		{R1}
+	STR		R1, [R0]
+	CMP		R1, #0
+
+	/* Restore the floating point context, if any. */
+	POPNE 	{R0}
+	/*VPOPNE	{D16-D31}*/
+	VPOPNE	{D0-D15}
+	VMSRNE  FPSCR, R0
+
+	/* Restore the critical section nesting depth. */
+	LDR		R0, ulCriticalNestingConst
+	POP		{R1}
+	STR		R1, [R0]
+
+	/* Ensure the priority mask is correct for the critical nesting depth. */
+	LDR		R2, ulICCPMRConst
+	LDR		R2, [R2]
+	CMP		R1, #0
+	MOVEQ	R4, #255
+	LDRNE	R4, ulMaxAPIPriorityMaskConst
+	LDRNE	R4, [R4]
+	STR		R4, [R2]
+
+	/* Restore all system mode registers other than the SP (which is already
+	being used). */
+	POP		{R0-R12, R14}
+
+	/* Return to the task code, loading CPSR on the way. */
+	RFEIA	sp!
+
+	.endm
+
+
+
+
+/******************************************************************************
+ * SVC handler is used to start the scheduler.
+ *****************************************************************************/
+.align 4
+.type FreeRTOS_SWI_Handler, %function
+FreeRTOS_SWI_Handler:
+	/* Save the context of the current task and select a new task to run. */
+	portSAVE_CONTEXT
+	LDR R0, vTaskSwitchContextConst
+	BLX	R0
+	portRESTORE_CONTEXT
+
+
+/******************************************************************************
+ * vPortRestoreTaskContext is used to start the scheduler.
+ *****************************************************************************/
+.type vPortRestoreTaskContext, %function
+vPortRestoreTaskContext:
+	/* Switch to system mode. */
+	CPS		#SYS_MODE
+	portRESTORE_CONTEXT
+
+.align 4
+.type FreeRTOS_IRQ_Handler, %function
+FreeRTOS_IRQ_Handler:
+
+	/* Return to the interrupted instruction. */
+	SUB		lr, lr, #4
+
+	/* Push the return address and SPSR. */
+	PUSH	{lr}
+	MRS		lr, SPSR
+	PUSH	{lr}
+
+	/* Change to supervisor mode to allow reentry. */
+	CPS		#SVC_MODE
+
+	/* Push used registers. */
+	PUSH	{r0-r4, r12}
+
+	/* Increment nesting count.  r3 holds the address of ulPortInterruptNesting
+	for future use.  r1 holds the original ulPortInterruptNesting value for
+	future use. */
+	LDR		r3, ulPortInterruptNestingConst
+	LDR		r1, [r3]
+	ADD		r4, r1, #1
+	STR		r4, [r3]
+
+	/* Read value from the interrupt acknowledge register, which is stored in r0
+	for future parameter and interrupt clearing use. */
+	LDR 	r2, ulICCIARConst
+	LDR		r2, [r2]
+	LDR		r0, [r2]
+
+	/* Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
+	future use.  _RB_ Is this ever needed provided the start of the stack is
+	alligned on an 8-byte boundary? */
+	MOV		r2, sp
+	AND		r2, r2, #4
+	SUB		sp, sp, r2
+
+	/* Call the interrupt handler. */
+	PUSH	{r0-r4, lr}
+	LDR		r1, vApplicationIRQHandlerConst
+	BLX		r1
+	POP		{r0-r4, lr}
+	ADD		sp, sp, r2
+
+	CPSID	i
+	DSB
+	ISB
+
+	/* Write the value read from ICCIAR to ICCEOIR. */
+	LDR 	r4, ulICCEOIRConst
+	LDR		r4, [r4]
+	STR		r0, [r4]
+
+	/* Restore the old nesting count. */
+	STR		r1, [r3]
+
+	/* A context switch is never performed if the nesting count is not 0. */
+	CMP		r1, #0
+	BNE		exit_without_switch
+
+	/* Did the interrupt request a context switch?  r1 holds the address of
+	ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
+	use. */
+	LDR		r1, =ulPortYieldRequired
+	LDR		r0, [r1]
+	CMP		r0, #0
+	BNE		switch_before_exit
+
+exit_without_switch:
+	/* No context switch.  Restore used registers, LR_irq and SPSR before
+	returning. */
+	POP		{r0-r4, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	MOVS	PC, LR
+
+switch_before_exit:
+	/* A context swtich is to be performed.  Clear the context switch pending
+	flag. */
+	MOV		r0, #0
+	STR		r0, [r1]
+
+	/* Restore used registers, LR-irq and SPSR before saving the context
+	to the task stack. */
+	POP		{r0-r4, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	portSAVE_CONTEXT
+
+	/* Call the function that selects the new task to execute.
+	vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
+	instructions, or 8 byte aligned stack allocated data.  LR does not need
+	saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
+	LDR		R0, vTaskSwitchContextConst
+	BLX		R0
+
+	/* Restore the context of, and branch to, the task selected to execute
+	next. */
+	portRESTORE_CONTEXT
+
+ulICCIARConst:	.word ulICCIAR
+ulICCEOIRConst:	.word ulICCEOIR
+ulICCPMRConst: .word ulICCPMR
+pxCurrentTCBConst: .word pxCurrentTCB
+ulCriticalNestingConst: .word ulCriticalNesting
+ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
+ulMaxAPIPriorityMaskConst: .word ulMaxAPIPriorityMask
+vTaskSwitchContextConst: .word vTaskSwitchContext
+vApplicationIRQHandlerConst: .word vApplicationIRQHandler
+ulPortInterruptNestingConst: .word ulPortInterruptNesting
+
+.end
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h
new file mode 100644
index 0000000..bcb638b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h
@@ -0,0 +1,195 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+	extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+typedef uint32_t TickType_t;
+#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* Called at the end of an ISR that can cause a context switch. */
+#define portEND_SWITCHING_ISR( xSwitchRequired )\
+{												\
+extern uint32_t ulPortYieldRequired;			\
+												\
+	if( xSwitchRequired != pdFALSE )			\
+	{											\
+		ulPortYieldRequired = pdTRUE;			\
+	}											\
+}
+
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() __asm volatile ( "SWI 0" ::: "memory" );
+
+
+/*-----------------------------------------------------------
+ * Critical section control
+ *----------------------------------------------------------*/
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+extern void vPortInstallFreeRTOSVectorTable( void );
+
+/* These macros do not globally disable/enable interrupts.  They do mask off
+interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+#define portDISABLE_INTERRUPTS()	ulPortSetInterruptMask()
+#define portENABLE_INTERRUPTS()		vPortClearInterruptMask( 0 )
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask(x)
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
+
+/* Prototype of the FreeRTOS tick handler.  This must be installed as the
+handler for whichever peripheral is used to generate the RTOS tick. */
+void FreeRTOS_Tick_Handler( void );
+
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+before any floating point instructions are executed. */
+void vPortTaskUsesFPU( void );
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif /* configASSERT */
+
+#define portNOP() __asm volatile( "NOP" )
+
+
+#ifdef __cplusplus
+	} /* extern C */
+#endif
+
+
+/* The number of bits to shift for an interrupt priority is dependent on the
+number of bits implemented by the interrupt controller. */
+#if configUNIQUE_INTERRUPT_PRIORITIES == 16
+	#define portPRIORITY_SHIFT 4
+	#define portMAX_BINARY_POINT_VALUE	3
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
+	#define portPRIORITY_SHIFT 3
+	#define portMAX_BINARY_POINT_VALUE	2
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
+	#define portPRIORITY_SHIFT 2
+	#define portMAX_BINARY_POINT_VALUE	1
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
+	#define portPRIORITY_SHIFT 1
+	#define portMAX_BINARY_POINT_VALUE	0
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
+	#define portPRIORITY_SHIFT 0
+	#define portMAX_BINARY_POINT_VALUE	0
+#else
+	#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
+#endif
+
+/* Interrupt controller access addresses. */
+#define portICCPMR_PRIORITY_MASK_OFFSET  						( 0x04 )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET 				( 0x0C )
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET 					( 0x10 )
+#define portICCBPR_BINARY_POINT_OFFSET							( 0x08 )
+#define portICCRPR_RUNNING_PRIORITY_OFFSET						( 0x14 )
+
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS 		( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER 					( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS 	( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS 		( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS 			( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+#define portICCBPR_BINARY_POINT_REGISTER 					( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+#define portICCRPR_RUNNING_PRIORITY_REGISTER 				( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/port.c
new file mode 100644
index 0000000..facc5a8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/port.c
@@ -0,0 +1,319 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#ifndef configSETUP_TICK_INTERRUPT
+	#error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt.
+#endif
+
+#ifndef configCLEAR_TICK_INTERRUPT
+	#error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt.
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+this value. */
+#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
+
+/* Tasks are not created with a floating point context, but can be given a
+floating point context after they have been created.  A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
+
+/* Constants required to setup the initial task context. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS			( 0x01UL )
+
+/* Masks all bits in the APSR other than the mode bits. */
+#define portAPSR_MODE_BITS_MASK			( 0x1F )
+
+/* The value of the mode bits in the APSR when the CPU is executing in user
+mode. */
+#define portAPSR_USER_MODE				( 0x10 )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing.  This function is necessarily written in
+ * assembly code so is implemented in portASM.s.
+ */
+extern void vPortRestoreTaskContext( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting.  This
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts.  As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then
+a floating point context must be saved and restored for the task. */
+volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
+
+/* Set to 1 to pend a context switch from an ISR. */
+volatile uint32_t ulPortYieldRequired = pdFALSE;
+
+/* Counts the interrupt nesting depth.  A context switch is only performed if
+if the nesting depth is 0. */
+volatile uint32_t ulPortInterruptNesting = 0UL;
+
+/* Used in the asm file to clear an interrupt. */
+__attribute__(( used )) const uint32_t ulICCEOIR = configEOI_ADDRESS;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro.
+
+	The fist real value on the stack is the status register, which is set for
+	system mode, with interrupts enabled.  A few NULLs are added first to ensure
+	GDB does not try decoding a non-existent return address. */
+	*pxTopOfStack = ( StackType_t ) NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+	{
+		/* The task will start in THUMB mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+
+	pxTopOfStack--;
+
+	/* Next the return address, which in this case is the start of the task. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+
+	/* Next all the registers other than the stack pointer. */
+	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The task will start with a critical nesting count of 0 as interrupts are
+	enabled. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+	pxTopOfStack--;
+
+	/* The task will start without a floating point context.  A task that uses
+	the floating point hardware must call vPortTaskUsesFPU() before executing
+	any floating point instructions. */
+	*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( ulPortInterruptNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+uint32_t ulAPSR;
+
+	/* Only continue if the CPU is not in User mode.  The CPU must be in a
+	Privileged mode for the scheduler to start. */
+	__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );
+	ulAPSR &= portAPSR_MODE_BITS_MASK;
+	configASSERT( ulAPSR != portAPSR_USER_MODE );
+
+	if( ulAPSR != portAPSR_USER_MODE )
+	{
+		/* Start the timer that generates the tick ISR. */
+		portDISABLE_INTERRUPTS();
+		configSETUP_TICK_INTERRUPT();
+
+		/* Start the first task executing. */
+		vPortRestoreTaskContext();
+	}
+
+	/* Will only get here if vTaskStartScheduler() was called with the CPU in
+	a non-privileged mode or the binary point register was not set to its lowest
+	possible value.  prvTaskExitError() is referenced to prevent a compiler
+	warning about it being defined but not referenced in the case that the user
+	defines their own exit address. */
+	( void ) prvTaskExitError;
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( ulCriticalNesting == 1 )
+	{
+		configASSERT( ulPortInterruptNesting == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as the critical section is being
+		exited. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then all interrupt
+		priorities must be re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Critical nesting has reached zero so all interrupt priorities
+			should be unmasked. */
+			portENABLE_INTERRUPTS();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void FreeRTOS_Tick_Handler( void )
+{
+uint32_t ulInterruptStatus;
+
+	ulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+
+	/* Increment the RTOS tick. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		ulPortYieldRequired = pdTRUE;
+	}
+
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulInterruptStatus );
+
+	configCLEAR_TICK_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortTaskUsesFPU( void )
+{
+uint32_t ulInitialFPSCR = 0;
+
+	/* A task is registering the fact that it needs an FPU context.  Set the
+	FPU flag (which is saved as part of the task context). */
+	ulPortTaskHasFPUContext = pdTRUE;
+
+	/* Initialise the floating point status register. */
+	__asm volatile ( "FMXR 	FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portASM.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portASM.S
new file mode 100644
index 0000000..d5f0222
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portASM.S
@@ -0,0 +1,264 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	.text
+	.arm
+
+	.set SYS_MODE,	0x1f
+	.set SVC_MODE,	0x13
+	.set IRQ_MODE,	0x12
+
+	/* Variables and functions. */
+	.extern ulMaxAPIPriorityMask
+	.extern _freertos_vector_table
+	.extern pxCurrentTCB
+	.extern vTaskSwitchContext
+	.extern vApplicationIRQHandler
+	.extern ulPortInterruptNesting
+	.extern ulPortTaskHasFPUContext
+	.extern ulICCEOIR
+	.extern ulPortYieldRequired
+
+	.global FreeRTOS_IRQ_Handler
+	.global FreeRTOS_SVC_Handler
+	.global vPortRestoreTaskContext
+
+
+.macro portSAVE_CONTEXT
+
+	/* Save the LR and SPSR onto the system mode stack before switching to
+	system mode to save the remaining system mode registers. */
+	SRSDB	sp!, #SYS_MODE
+	CPS		#SYS_MODE
+	PUSH	{R0-R12, R14}
+
+	/* Push the critical nesting count. */
+	LDR		R2, ulCriticalNestingConst
+	LDR		R1, [R2]
+	PUSH	{R1}
+
+	/* Does the task have a floating point context that needs saving?  If
+	ulPortTaskHasFPUContext is 0 then no. */
+	LDR		R2, ulPortTaskHasFPUContextConst
+	LDR		R3, [R2]
+	CMP		R3, #0
+
+	/* Save the floating point context, if any. */
+	FMRXNE  R1,  FPSCR
+	VPUSHNE {D0-D15}
+#if configFPU_D32 == 1
+	VPUSHNE	{D16-D31}
+#endif /* configFPU_D32 */
+	PUSHNE	{R1}
+
+	/* Save ulPortTaskHasFPUContext itself. */
+	PUSH	{R3}
+
+	/* Save the stack pointer in the TCB. */
+	LDR		R0, pxCurrentTCBConst
+	LDR		R1, [R0]
+	STR		SP, [R1]
+
+	.endm
+
+; /**********************************************************************/
+
+.macro portRESTORE_CONTEXT
+
+	/* Set the SP to point to the stack of the task being restored. */
+	LDR		R0, pxCurrentTCBConst
+	LDR		R1, [R0]
+	LDR		SP, [R1]
+
+	/* Is there a floating point context to restore?  If the restored
+	ulPortTaskHasFPUContext is zero then no. */
+	LDR		R0, ulPortTaskHasFPUContextConst
+	POP		{R1}
+	STR		R1, [R0]
+	CMP		R1, #0
+
+	/* Restore the floating point context, if any. */
+	POPNE 	{R0}
+#if configFPU_D32 == 1
+	VPOPNE	{D16-D31}
+#endif /* configFPU_D32 */
+	VPOPNE	{D0-D15}
+	VMSRNE  FPSCR, R0
+
+	/* Restore the critical section nesting depth. */
+	LDR		R0, ulCriticalNestingConst
+	POP		{R1}
+	STR		R1, [R0]
+
+	/* Restore all system mode registers other than the SP (which is already
+	being used). */
+	POP		{R0-R12, R14}
+
+	/* Return to the task code, loading CPSR on the way. */
+	RFEIA	sp!
+
+	.endm
+
+
+
+
+/******************************************************************************
+ * SVC handler is used to yield.
+ *****************************************************************************/
+.align 4
+.type FreeRTOS_SVC_Handler, %function
+FreeRTOS_SVC_Handler:
+	/* Save the context of the current task and select a new task to run. */
+	portSAVE_CONTEXT
+	LDR R0, vTaskSwitchContextConst
+	BLX	R0
+	portRESTORE_CONTEXT
+
+
+/******************************************************************************
+ * vPortRestoreTaskContext is used to start the scheduler.
+ *****************************************************************************/
+.align 4
+.type vPortRestoreTaskContext, %function
+vPortRestoreTaskContext:
+	/* Switch to system mode. */
+	CPS		#SYS_MODE
+	portRESTORE_CONTEXT
+
+.align 4
+.type FreeRTOS_IRQ_Handler, %function
+FreeRTOS_IRQ_Handler:
+	/* Return to the interrupted instruction. */
+	SUB		lr, lr, #4
+
+	/* Push the return address and SPSR. */
+	PUSH	{lr}
+	MRS		lr, SPSR
+	PUSH	{lr}
+
+	/* Change to supervisor mode to allow reentry. */
+	CPS		#0x13
+
+	/* Push used registers. */
+	PUSH	{r0-r3, r12}
+
+	/* Increment nesting count.  r3 holds the address of ulPortInterruptNesting
+	for future use.  r1 holds the original ulPortInterruptNesting value for
+	future use. */
+	LDR		r3, ulPortInterruptNestingConst
+	LDR		r1, [r3]
+	ADD		r0, r1, #1
+	STR		r0, [r3]
+
+	/* Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
+	future use. */
+	MOV		r0, sp
+	AND		r2, r0, #4
+	SUB		sp, sp, r2
+
+	/* Call the interrupt handler. */
+	PUSH	{r0-r3, lr}
+	LDR		r1, vApplicationIRQHandlerConst
+	BLX		r1
+	POP		{r0-r3, lr}
+	ADD		sp, sp, r2
+
+	CPSID	i
+	DSB
+	ISB
+
+	/* Write to the EOI register. */
+	LDR 	r0, ulICCEOIRConst
+	LDR		r2, [r0]
+	STR		r0, [r2]
+
+	/* Restore the old nesting count. */
+	STR		r1, [r3]
+
+	/* A context switch is never performed if the nesting count is not 0. */
+	CMP		r1, #0
+	BNE		exit_without_switch
+
+	/* Did the interrupt request a context switch?  r1 holds the address of
+	ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
+	use. */
+	LDR		r1, ulPortYieldRequiredConst
+	LDR		r0, [r1]
+	CMP		r0, #0
+	BNE		switch_before_exit
+
+exit_without_switch:
+	/* No context switch.  Restore used registers, LR_irq and SPSR before
+	returning. */
+	POP		{r0-r3, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	MOVS	PC, LR
+
+switch_before_exit:
+	/* A context swtich is to be performed.  Clear the context switch pending
+	flag. */
+	MOV		r0, #0
+	STR		r0, [r1]
+
+	/* Restore used registers, LR-irq and SPSR before saving the context
+	to the task stack. */
+	POP		{r0-r3, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	portSAVE_CONTEXT
+
+	/* Call the function that selects the new task to execute.
+	vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
+	instructions, or 8 byte aligned stack allocated data.  LR does not need
+	saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
+	LDR		R0, vTaskSwitchContextConst
+	BLX		R0
+
+	/* Restore the context of, and branch to, the task selected to execute
+	next. */
+	portRESTORE_CONTEXT
+
+ulICCEOIRConst:	.word ulICCEOIR
+pxCurrentTCBConst: .word pxCurrentTCB
+ulCriticalNestingConst: .word ulCriticalNesting
+ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
+vTaskSwitchContextConst: .word vTaskSwitchContext
+vApplicationIRQHandlerConst: .word vApplicationIRQHandler
+ulPortInterruptNestingConst: .word ulPortInterruptNesting
+ulPortYieldRequiredConst: .word ulPortYieldRequired
+
+.end
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h
new file mode 100644
index 0000000..45960e6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h
@@ -0,0 +1,175 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+	extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+typedef uint32_t TickType_t;
+#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* Called at the end of an ISR that can cause a context switch. */
+#define portEND_SWITCHING_ISR( xSwitchRequired )\
+{												\
+extern volatile uint32_t ulPortYieldRequired;	\
+												\
+	if( xSwitchRequired != pdFALSE )			\
+	{											\
+		ulPortYieldRequired = pdTRUE;			\
+	}											\
+}
+
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() __asm volatile ( "SWI 0		\n"				\
+									 "ISB		  " ::: "memory" );
+
+
+/*-----------------------------------------------------------
+ * Critical section control
+ *----------------------------------------------------------*/
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+extern void vPortInstallFreeRTOSVectorTable( void );
+
+/* The I bit within the CPSR. */
+#define portINTERRUPT_ENABLE_BIT	( 1 << 7 )
+
+/* In the absence of a priority mask register, these functions and macros
+globally enable and disable interrupts. */
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+#define portENABLE_INTERRUPTS()		__asm volatile ( "CPSIE i 	\n"	::: "memory" );
+#define portDISABLE_INTERRUPTS()	__asm volatile ( "CPSID i 	\n"		\
+													 "DSB		\n"		\
+													 "ISB		  " ::: "memory" );
+
+__attribute__( ( always_inline ) ) static __inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void )
+{
+volatile uint32_t ulCPSR;
+
+	__asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) :: "memory" );
+	ulCPSR &= portINTERRUPT_ENABLE_BIT;
+	portDISABLE_INTERRUPTS();
+	return ulCPSR;
+}
+
+#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	if( x == 0 ) portENABLE_INTERRUPTS()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
+
+/* Prototype of the FreeRTOS tick handler.  This must be installed as the
+handler for whichever peripheral is used to generate the RTOS tick. */
+void FreeRTOS_Tick_Handler( void );
+
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+before any floating point instructions are executed. */
+void vPortTaskUsesFPU( void );
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#define portNOP() __asm volatile( "NOP" )
+#define portINLINE __inline
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#ifdef __cplusplus
+	} /* extern C */
+#endif
+
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ATMega323/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ATMega323/port.c
new file mode 100644
index 0000000..6220ef0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ATMega323/port.c
@@ -0,0 +1,426 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* 
+
+Changes from V2.6.0
+
+	+ AVR port - Replaced the inb() and outb() functions with direct memory
+	  access.  This allows the port to be built with the 20050414 build of
+	  WinAVR.
+*/
+
+#include 
+#include 
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the AVR port.
+ *----------------------------------------------------------*/
+
+/* Start tasks with interrupts enables. */
+#define portFLAGS_INT_ENABLED					( ( StackType_t ) 0x80 )
+
+/* Hardware constants for timer 1. */
+#define portCLEAR_COUNTER_ON_MATCH				( ( uint8_t ) 0x08 )
+#define portPRESCALE_64							( ( uint8_t ) 0x03 )
+#define portCLOCK_PRESCALER						( ( uint32_t ) 64 )
+#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE	( ( uint8_t ) 0x10 )
+
+/*-----------------------------------------------------------*/
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * Macro to save all the general purpose registers, the save the stack pointer
+ * into the TCB.  
+ * 
+ * The first thing we do is save the flags then disable interrupts.  This is to 
+ * guard our stack against having a context switch interrupt after we have already 
+ * pushed the registers onto the stack - causing the 32 registers to be on the 
+ * stack twice. 
+ * 
+ * r1 is set to zero as the compiler expects it to be thus, however some
+ * of the math routines make use of R1. 
+ * 
+ * The interrupts will have been disabled during the call to portSAVE_CONTEXT()
+ * so we need not worry about reading/writing to the stack pointer. 
+ */
+
+#define portSAVE_CONTEXT()									\
+	asm volatile (	"push	r0						\n\t"	\
+					"in		r0, __SREG__			\n\t"	\
+					"cli							\n\t"	\
+					"push	r0						\n\t"	\
+					"push	r1						\n\t"	\
+					"clr	r1						\n\t"	\
+					"push	r2						\n\t"	\
+					"push	r3						\n\t"	\
+					"push	r4						\n\t"	\
+					"push	r5						\n\t"	\
+					"push	r6						\n\t"	\
+					"push	r7						\n\t"	\
+					"push	r8						\n\t"	\
+					"push	r9						\n\t"	\
+					"push	r10						\n\t"	\
+					"push	r11						\n\t"	\
+					"push	r12						\n\t"	\
+					"push	r13						\n\t"	\
+					"push	r14						\n\t"	\
+					"push	r15						\n\t"	\
+					"push	r16						\n\t"	\
+					"push	r17						\n\t"	\
+					"push	r18						\n\t"	\
+					"push	r19						\n\t"	\
+					"push	r20						\n\t"	\
+					"push	r21						\n\t"	\
+					"push	r22						\n\t"	\
+					"push	r23						\n\t"	\
+					"push	r24						\n\t"	\
+					"push	r25						\n\t"	\
+					"push	r26						\n\t"	\
+					"push	r27						\n\t"	\
+					"push	r28						\n\t"	\
+					"push	r29						\n\t"	\
+					"push	r30						\n\t"	\
+					"push	r31						\n\t"	\
+					"lds	r26, pxCurrentTCB		\n\t"	\
+					"lds	r27, pxCurrentTCB + 1	\n\t"	\
+					"in		r0, 0x3d				\n\t"	\
+					"st		x+, r0					\n\t"	\
+					"in		r0, 0x3e				\n\t"	\
+					"st		x+, r0					\n\t"	\
+				);
+
+/* 
+ * Opposite to portSAVE_CONTEXT().  Interrupts will have been disabled during
+ * the context save so we can write to the stack pointer. 
+ */
+
+#define portRESTORE_CONTEXT()								\
+	asm volatile (	"lds	r26, pxCurrentTCB		\n\t"	\
+					"lds	r27, pxCurrentTCB + 1	\n\t"	\
+					"ld		r28, x+					\n\t"	\
+					"out	__SP_L__, r28			\n\t"	\
+					"ld		r29, x+					\n\t"	\
+					"out	__SP_H__, r29			\n\t"	\
+					"pop	r31						\n\t"	\
+					"pop	r30						\n\t"	\
+					"pop	r29						\n\t"	\
+					"pop	r28						\n\t"	\
+					"pop	r27						\n\t"	\
+					"pop	r26						\n\t"	\
+					"pop	r25						\n\t"	\
+					"pop	r24						\n\t"	\
+					"pop	r23						\n\t"	\
+					"pop	r22						\n\t"	\
+					"pop	r21						\n\t"	\
+					"pop	r20						\n\t"	\
+					"pop	r19						\n\t"	\
+					"pop	r18						\n\t"	\
+					"pop	r17						\n\t"	\
+					"pop	r16						\n\t"	\
+					"pop	r15						\n\t"	\
+					"pop	r14						\n\t"	\
+					"pop	r13						\n\t"	\
+					"pop	r12						\n\t"	\
+					"pop	r11						\n\t"	\
+					"pop	r10						\n\t"	\
+					"pop	r9						\n\t"	\
+					"pop	r8						\n\t"	\
+					"pop	r7						\n\t"	\
+					"pop	r6						\n\t"	\
+					"pop	r5						\n\t"	\
+					"pop	r4						\n\t"	\
+					"pop	r3						\n\t"	\
+					"pop	r2						\n\t"	\
+					"pop	r1						\n\t"	\
+					"pop	r0						\n\t"	\
+					"out	__SREG__, r0			\n\t"	\
+					"pop	r0						\n\t"	\
+				);
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Perform hardware setup to enable ticks from timer 1, compare match A.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint16_t usAddress;
+
+	/* Place a few bytes of known values on the bottom of the stack. 
+	This is just useful for debugging. */
+
+	*pxTopOfStack = 0x11;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33;
+	pxTopOfStack--;
+
+	/* Simulate how the stack would look after a call to vPortYield() generated by 
+	the compiler. */
+
+	/*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
+
+	/* The start of the task code will be popped off the stack last, so place
+	it on first. */
+	usAddress = ( uint16_t ) pxCode;
+	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+	pxTopOfStack--;
+
+	usAddress >>= 8;
+	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+	pxTopOfStack--;
+
+	/* Next simulate the stack as if after a call to portSAVE_CONTEXT().  
+	portSAVE_CONTEXT places the flags on the stack immediately after r0
+	to ensure the interrupts get disabled as soon as possible, and so ensuring
+	the stack use is minimal should a context switch interrupt occur. */
+	*pxTopOfStack = ( StackType_t ) 0x00;	/* R0 */
+	pxTopOfStack--;
+	*pxTopOfStack = portFLAGS_INT_ENABLED;
+	pxTopOfStack--;
+
+
+	/* Now the remaining registers.   The compiler expects R1 to be 0. */
+	*pxTopOfStack = ( StackType_t ) 0x00;	/* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x02;	/* R2 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x03;	/* R3 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x04;	/* R4 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x05;	/* R5 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x06;	/* R6 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x07;	/* R7 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x08;	/* R8 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x09;	/* R9 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x10;	/* R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x11;	/* R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12;	/* R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x13;	/* R13 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x14;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x15;	/* R15 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x16;	/* R16 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x17;	/* R17 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x18;	/* R18 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x19;	/* R19 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x20;	/* R20 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x21;	/* R21 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x22;	/* R22 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x23;	/* R23 */
+	pxTopOfStack--;
+
+	/* Place the parameter on the stack in the expected location. */
+	usAddress = ( uint16_t ) pvParameters;
+	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+	pxTopOfStack--;
+
+	usAddress >>= 8;
+	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0x26;	/* R26 X */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x27;	/* R27 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x28;	/* R28 Y */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x29;	/* R29 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x30;	/* R30 Z */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x031;	/* R31 */
+	pxTopOfStack--;
+
+	/*lint +e950 +e611 +e923 */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Setup the hardware to generate the tick. */
+	prvSetupTimerInterrupt();
+
+	/* Restore the context of the first task that is going to run. */
+	portRESTORE_CONTEXT();
+
+	/* Simulate a function call end as generated by the compiler.  We will now
+	jump to the start of the task the context of which we have just restored. */
+	asm volatile ( "ret" );
+
+	/* Should not get here. */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the AVR port will get stopped.  If required simply
+	disable the tick interrupt here. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch.  The first thing we do is save the registers so we
+ * can use a naked attribute.
+ */
+void vPortYield( void ) __attribute__ ( ( naked ) );
+void vPortYield( void )
+{
+	portSAVE_CONTEXT();
+	vTaskSwitchContext();
+	portRESTORE_CONTEXT();
+
+	asm volatile ( "ret" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Context switch function used by the tick.  This must be identical to 
+ * vPortYield() from the call to vTaskSwitchContext() onwards.  The only
+ * difference from vPortYield() is the tick count is incremented as the
+ * call comes from the tick ISR.
+ */
+void vPortYieldFromTick( void ) __attribute__ ( ( naked ) );
+void vPortYieldFromTick( void )
+{
+	portSAVE_CONTEXT();
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		vTaskSwitchContext();
+	}
+	portRESTORE_CONTEXT();
+
+	asm volatile ( "ret" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup timer 1 compare match A to generate a tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+uint32_t ulCompareMatch;
+uint8_t ucHighByte, ucLowByte;
+
+	/* Using 16bit timer 1 to generate the tick.  Correct fuses must be
+	selected for the configCPU_CLOCK_HZ clock. */
+
+	ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+	/* We only have 16 bits so have to scale to get our required tick rate. */
+	ulCompareMatch /= portCLOCK_PRESCALER;
+
+	/* Adjust for correct value. */
+	ulCompareMatch -= ( uint32_t ) 1;
+
+	/* Setup compare match value for compare match A.  Interrupts are disabled 
+	before this is called so we need not worry here. */
+	ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
+	ulCompareMatch >>= 8;
+	ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
+	OCR1AH = ucHighByte;
+	OCR1AL = ucLowByte;
+
+	/* Setup clock source and compare match behaviour. */
+	ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64;
+	TCCR1B = ucLowByte;
+
+	/* Enable the interrupt - this is okay as interrupt are currently globally
+	disabled. */
+	ucLowByte = TIMSK;
+	ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
+	TIMSK = ucLowByte;
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 1
+
+	/*
+	 * Tick ISR for preemptive scheduler.  We can use a naked attribute as
+	 * the context is saved at the start of vPortYieldFromTick().  The tick
+	 * count is incremented after the context is saved.
+	 */
+	void SIG_OUTPUT_COMPARE1A( void ) __attribute__ ( ( signal, naked ) );
+	void SIG_OUTPUT_COMPARE1A( void )
+	{
+		vPortYieldFromTick();
+		asm volatile ( "reti" );
+	}
+#else
+
+	/*
+	 * Tick ISR for the cooperative scheduler.  All this does is increment the
+	 * tick count.  We don't need to switch context, this can only be done by
+	 * manual calls to taskYIELD();
+	 */
+	void SIG_OUTPUT_COMPARE1A( void ) __attribute__ ( ( signal ) );
+	void SIG_OUTPUT_COMPARE1A( void )
+	{
+		xTaskIncrementTick();
+	}
+#endif
+
+
+	
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ATMega323/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ATMega323/portmacro.h
new file mode 100644
index 0000000..a29841f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ATMega323/portmacro.h
@@ -0,0 +1,107 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V1.2.3
+
+	+ portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it
+	  base 16.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	uint8_t
+#define portBASE_TYPE	char
+
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#define portENTER_CRITICAL()		asm volatile ( "in		__tmp_reg__, __SREG__" :: );	\
+									asm volatile ( "cli" :: );								\
+									asm volatile ( "push	__tmp_reg__" :: )
+
+#define portEXIT_CRITICAL()			asm volatile ( "pop		__tmp_reg__" :: );				\
+									asm volatile ( "out		__SREG__, __tmp_reg__" :: )
+
+#define portDISABLE_INTERRUPTS()	asm volatile ( "cli" :: );
+#define portENABLE_INTERRUPTS()		asm volatile ( "sei" :: );
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			1
+#define portNOP()					asm volatile ( "nop" );
+/*-----------------------------------------------------------*/
+
+/* Kernel utilities. */
+extern void vPortYield( void ) __attribute__ ( ( naked ) );
+#define portYIELD()					vPortYield()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/AVR32_UC3/exception.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/AVR32_UC3/exception.S
new file mode 100644
index 0000000..9a2833f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/AVR32_UC3/exception.S
@@ -0,0 +1,297 @@
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Exception and interrupt vectors.
+ *
+ * This file maps all events supported by an AVR32UC.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32UC devices with an INTC module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include 
+#include "intc.h"
+
+
+//! @{
+//! \verbatim
+
+
+  .section  .exception, "ax", @progbits
+
+
+// Start of Exception Vector Table.
+
+  // EVBA must be aligned with a power of two strictly greater than the EVBA-
+  // relative offset of the last vector.
+  .balign 0x200
+
+  // Export symbol.
+  .global _evba
+  .type _evba, @function
+_evba:
+
+        .org  0x000
+        // Unrecoverable Exception.
+_handle_Unrecoverable_Exception:
+        rjmp $
+
+        .org  0x004
+        // TLB Multiple Hit: UNUSED IN AVR32UC.
+_handle_TLB_Multiple_Hit:
+        rjmp $
+
+        .org  0x008
+        // Bus Error Data Fetch.
+_handle_Bus_Error_Data_Fetch:
+        rjmp $
+
+        .org  0x00C
+         // Bus Error Instruction Fetch.
+_handle_Bus_Error_Instruction_Fetch:
+        rjmp $
+
+        .org  0x010
+        // NMI.
+_handle_NMI:
+        rjmp $
+
+        .org  0x014
+        // Instruction Address.
+_handle_Instruction_Address:
+        rjmp $
+
+        .org  0x018
+        // ITLB Protection.
+_handle_ITLB_Protection:
+        rjmp $
+
+        .org  0x01C
+        // Breakpoint.
+_handle_Breakpoint:
+        rjmp $
+
+        .org  0x020
+        // Illegal Opcode.
+_handle_Illegal_Opcode:
+        rjmp $
+
+        .org  0x024
+        // Unimplemented Instruction.
+_handle_Unimplemented_Instruction:
+        rjmp $
+
+        .org  0x028
+        // Privilege Violation.
+_handle_Privilege_Violation:
+        rjmp $
+
+        .org  0x02C
+        // Floating-Point: UNUSED IN AVR32UC.
+_handle_Floating_Point:
+        rjmp $
+
+        .org  0x030
+        // Coprocessor Absent: UNUSED IN AVR32UC.
+_handle_Coprocessor_Absent:
+        rjmp $
+
+        .org  0x034
+        // Data Address (Read).
+_handle_Data_Address_Read:
+        rjmp $
+
+        .org  0x038
+        // Data Address (Write).
+_handle_Data_Address_Write:
+        rjmp $
+
+        .org  0x03C
+        // DTLB Protection (Read).
+_handle_DTLB_Protection_Read:
+        rjmp $
+
+        .org  0x040
+        // DTLB Protection (Write).
+_handle_DTLB_Protection_Write:
+        rjmp $
+
+        .org  0x044
+        // DTLB Modified: UNUSED IN AVR32UC.
+_handle_DTLB_Modified:
+        rjmp $
+
+        .org  0x050
+        // ITLB Miss: UNUSED IN AVR32UC.
+_handle_ITLB_Miss:
+        rjmp $
+
+        .org  0x060
+        // DTLB Miss (Read): UNUSED IN AVR32UC.
+_handle_DTLB_Miss_Read:
+        rjmp $
+
+        .org  0x070
+        // DTLB Miss (Write): UNUSED IN AVR32UC.
+_handle_DTLB_Miss_Write:
+        rjmp $
+
+        .org  0x100
+        // Supervisor Call.
+_handle_Supervisor_Call:
+        lda.w   pc, SCALLYield
+
+
+// Interrupt support.
+// The interrupt controller must provide the offset address relative to EVBA.
+// Important note:
+//   All interrupts call a C function named _get_interrupt_handler.
+//   This function will read group and interrupt line number to then return in
+//   R12 a pointer to a user-provided interrupt handler.
+
+  .balign 4
+
+_int0:
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+  // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+  mfsr    r12, AVR32_SR
+  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+  cp.w    r12, 0b110
+  brlo    _int0_normal
+  lddsp   r12, sp[0 * 4]
+  stdsp   sp[6 * 4], r12
+  lddsp   r12, sp[1 * 4]
+  stdsp   sp[7 * 4], r12
+  lddsp   r12, sp[3 * 4]
+  sub     sp, -6 * 4
+  rete
+_int0_normal:
+#endif
+  mov     r12, 0  // Pass the int_lev parameter to the _get_interrupt_handler function.
+  call    _get_interrupt_handler
+  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
+  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+_int1:
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+  // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+  mfsr    r12, AVR32_SR
+  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+  cp.w    r12, 0b110
+  brlo    _int1_normal
+  lddsp   r12, sp[0 * 4]
+  stdsp   sp[6 * 4], r12
+  lddsp   r12, sp[1 * 4]
+  stdsp   sp[7 * 4], r12
+  lddsp   r12, sp[3 * 4]
+  sub     sp, -6 * 4
+  rete
+_int1_normal:
+#endif
+  mov     r12, 1  // Pass the int_lev parameter to the _get_interrupt_handler function.
+  call    _get_interrupt_handler
+  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
+  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+_int2:
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+  // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+  mfsr    r12, AVR32_SR
+  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+  cp.w    r12, 0b110
+  brlo    _int2_normal
+  lddsp   r12, sp[0 * 4]
+  stdsp   sp[6 * 4], r12
+  lddsp   r12, sp[1 * 4]
+  stdsp   sp[7 * 4], r12
+  lddsp   r12, sp[3 * 4]
+  sub     sp, -6 * 4
+  rete
+_int2_normal:
+#endif
+  mov     r12, 2  // Pass the int_lev parameter to the _get_interrupt_handler function.
+  call    _get_interrupt_handler
+  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
+  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+_int3:
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+  // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+  mfsr    r12, AVR32_SR
+  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+  cp.w    r12, 0b110
+  brlo    _int3_normal
+  lddsp   r12, sp[0 * 4]
+  stdsp   sp[6 * 4], r12
+  lddsp   r12, sp[1 * 4]
+  stdsp   sp[7 * 4], r12
+  lddsp   r12, sp[3 * 4]
+  sub     sp, -6 * 4
+  rete
+_int3_normal:
+#endif
+  mov     r12, 3  // Pass the int_lev parameter to the _get_interrupt_handler function.
+  call    _get_interrupt_handler
+  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
+  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+
+// Constant data area.
+
+  .balign 4
+
+  // Values to store in the interrupt priority registers for the various interrupt priority levels.
+  // The interrupt priority registers contain the interrupt priority level and
+  // the EVBA-relative interrupt vector offset.
+  .global ipr_val
+  .type ipr_val, @object
+ipr_val:
+  .word (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int0 - _evba),\
+        (INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int1 - _evba),\
+        (INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int2 - _evba),\
+        (INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int3 - _evba)
+
+
+//! \endverbatim
+//! @}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/AVR32_UC3/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/AVR32_UC3/port.c
new file mode 100644
index 0000000..36a6e26
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/AVR32_UC3/port.c
@@ -0,0 +1,435 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief FreeRTOS port source for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/* Standard includes. */
+#include 
+#include 
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* AVR32 UC3 includes. */
+#include 
+#include "gpio.h"
+#if( configTICK_USE_TC==1 )
+	#include "tc.h"
+#endif
+
+
+/* Constants required to setup the task context. */
+#define portINITIAL_SR            ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
+#define portINSTRUCTION_SIZE      ( ( StackType_t ) 0 )
+
+/* Each task maintains its own critical nesting variable. */
+#define portNO_CRITICAL_NESTING   ( ( uint32_t ) 0 )
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+#if( configTICK_USE_TC==0 )
+	static void prvScheduleNextTick( void );
+#else
+	static void prvClearTcInt( void );
+#endif
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Low-level initialization routine called during startup, before the main
+ * function.
+ * This version comes in replacement to the default one provided by Newlib.
+ * Newlib's _init_startup only calls init_exceptions, but Newlib's exception
+ * vectors are not compatible with the SCALL management in the current FreeRTOS
+ * port. More low-level initializations are besides added here.
+ */
+void _init_startup(void)
+{
+	/* Import the Exception Vector Base Address. */
+	extern void _evba;
+
+	#if configHEAP_INIT
+		extern void __heap_start__;
+		extern void __heap_end__;
+		BaseType_t *pxMem;
+	#endif
+
+	/* Load the Exception Vector Base Address in the corresponding system register. */
+	Set_system_register( AVR32_EVBA, ( int ) &_evba );
+
+	/* Enable exceptions. */
+	ENABLE_ALL_EXCEPTIONS();
+
+	/* Initialize interrupt handling. */
+	INTC_init_interrupts();
+
+	#if configHEAP_INIT
+
+		/* Initialize the heap used by malloc. */
+		for( pxMem = &__heap_start__; pxMem < ( BaseType_t * )&__heap_end__; )
+		{
+			*pxMem++ = 0xA5A5A5A5;
+		}
+
+	#endif
+
+	/* Give the used CPU clock frequency to Newlib, so it can work properly. */
+	set_cpu_hz( configCPU_CLOCK_HZ );
+
+	/* Code section present if and only if the debug trace is activated. */
+	#if configDBG
+	{
+		static const gpio_map_t DBG_USART_GPIO_MAP =
+		{
+			{ configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
+			{ configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
+		};
+
+		/* Initialize the USART used for the debug trace with the configured parameters. */
+		set_usart_base( ( void * ) configDBG_USART );
+		gpio_enable_module( DBG_USART_GPIO_MAP,
+		                    sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );
+		usart_init( configDBG_USART_BAUDRATE );
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * malloc, realloc and free are meant to be called through respectively
+ * pvPortMalloc, pvPortRealloc and vPortFree.
+ * The latter functions call the former ones from within sections where tasks
+ * are suspended, so the latter functions are task-safe. __malloc_lock and
+ * __malloc_unlock use the same mechanism to also keep the former functions
+ * task-safe as they may be called directly from Newlib's functions.
+ * However, all these functions are interrupt-unsafe and SHALL THEREFORE NOT BE
+ * CALLED FROM WITHIN AN INTERRUPT, because __malloc_lock and __malloc_unlock do
+ * not call portENTER_CRITICAL and portEXIT_CRITICAL in order not to disable
+ * interrupts during memory allocation management as this may be a very time-
+ * consuming process.
+ */
+
+/*
+ * Lock routine called by Newlib on malloc / realloc / free entry to guarantee a
+ * safe section as memory allocation management uses global data.
+ * See the aforementioned details.
+ */
+void __malloc_lock(struct _reent *ptr)
+{
+	vTaskSuspendAll();
+}
+
+/*
+ * Unlock routine called by Newlib on malloc / realloc / free exit to guarantee
+ * a safe section as memory allocation management uses global data.
+ * See the aforementioned details.
+ */
+void __malloc_unlock(struct _reent *ptr)
+{
+	xTaskResumeAll();
+}
+/*-----------------------------------------------------------*/
+
+/* Added as there is no such function in FreeRTOS. */
+void *pvPortRealloc( void *pv, size_t xWantedSize )
+{
+void *pvReturn;
+
+	vTaskSuspendAll();
+	{
+		pvReturn = realloc( pv, xWantedSize );
+	}
+	xTaskResumeAll();
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+/* The cooperative scheduler requires a normal IRQ service routine to
+simply increment the system tick. */
+/* The preemptive scheduler is defined as "naked" as the full context is saved
+on entry as part of the context switch. */
+__attribute__((__naked__)) static void vTick( void )
+{
+	/* Save the context of the interrupted task. */
+	portSAVE_CONTEXT_OS_INT();
+
+	#if( configTICK_USE_TC==1 )
+		/* Clear the interrupt flag. */
+		prvClearTcInt();
+	#else
+		/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
+		clock cycles from now. */
+		prvScheduleNextTick();
+	#endif
+
+	/* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
+	calls in a critical section . */
+	portENTER_CRITICAL();
+		xTaskIncrementTick();
+	portEXIT_CRITICAL();
+
+	/* Restore the context of the "elected task". */
+	portRESTORE_CONTEXT_OS_INT();
+}
+/*-----------------------------------------------------------*/
+
+__attribute__((__naked__)) void SCALLYield( void )
+{
+	/* Save the context of the interrupted task. */
+	portSAVE_CONTEXT_SCALL();
+	vTaskSwitchContext();
+	portRESTORE_CONTEXT_SCALL();
+}
+/*-----------------------------------------------------------*/
+
+/* The code generated by the GCC compiler uses the stack in different ways at
+different optimisation levels.  The interrupt flags can therefore not always
+be saved to the stack.  Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
+__attribute__((__noinline__)) void vPortEnterCritical( void )
+{
+	/* Disable interrupts */
+	portDISABLE_INTERRUPTS();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	 directly.  Increment ulCriticalNesting to keep a count of how many times
+	 portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+__attribute__((__noinline__)) void vPortExitCritical( void )
+{
+	if(ulCriticalNesting > portNO_CRITICAL_NESTING)
+	{
+		ulCriticalNesting--;
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Enable all interrupt/exception. */
+			portENABLE_INTERRUPTS();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* When the task starts, it will expect to find the function parameter in R12. */
+	pxTopOfStack--;
+	*pxTopOfStack-- = ( StackType_t ) 0x08080808;					/* R8 */
+	*pxTopOfStack-- = ( StackType_t ) 0x09090909;					/* R9 */
+	*pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A;					/* R10 */
+	*pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B;					/* R11 */
+	*pxTopOfStack-- = ( StackType_t ) pvParameters;					/* R12 */
+	*pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF;					/* R14/LR */
+	*pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
+	*pxTopOfStack-- = ( StackType_t ) portINITIAL_SR;				/* SR */
+	*pxTopOfStack-- = ( StackType_t ) 0xFF0000FF;					/* R0 */
+	*pxTopOfStack-- = ( StackType_t ) 0x01010101;					/* R1 */
+	*pxTopOfStack-- = ( StackType_t ) 0x02020202;					/* R2 */
+	*pxTopOfStack-- = ( StackType_t ) 0x03030303;					/* R3 */
+	*pxTopOfStack-- = ( StackType_t ) 0x04040404;					/* R4 */
+	*pxTopOfStack-- = ( StackType_t ) 0x05050505;					/* R5 */
+	*pxTopOfStack-- = ( StackType_t ) 0x06060606;					/* R6 */
+	*pxTopOfStack-- = ( StackType_t ) 0x07070707;					/* R7 */
+	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING;			/* ulCriticalNesting */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	portRESTORE_CONTEXT();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the AVR32 port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
+clock cycles from now. */
+#if( configTICK_USE_TC==0 )
+	static void prvScheduleFirstTick(void)
+	{
+		uint32_t lCycles;
+
+		lCycles = Get_system_register(AVR32_COUNT);
+		lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+		// If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
+		// generation feature does not get disabled.
+		if(0 == lCycles)
+		{
+			lCycles++;
+		}
+		Set_system_register(AVR32_COMPARE, lCycles);
+	}
+	
+	__attribute__((__noinline__)) static void prvScheduleNextTick(void)
+	{
+		uint32_t lCycles, lCount;
+
+		lCycles = Get_system_register(AVR32_COMPARE);
+		lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+		// If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
+		// generation feature does not get disabled.
+		if(0 == lCycles)
+		{
+			lCycles++;
+		}
+		lCount = Get_system_register(AVR32_COUNT);
+		if( lCycles < lCount )
+		{		// We missed a tick, recover for the next.
+			lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+		}
+		Set_system_register(AVR32_COMPARE, lCycles);
+	}
+#else
+	__attribute__((__noinline__)) static void prvClearTcInt(void)
+	{
+		AVR32_TC.channel[configTICK_TC_CHANNEL].sr;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt(void)
+{
+#if( configTICK_USE_TC==1 )
+
+	volatile avr32_tc_t *tc = &AVR32_TC;
+
+	// Options for waveform genration.
+	tc_waveform_opt_t waveform_opt =
+	{
+	.channel  = configTICK_TC_CHANNEL,             /* Channel selection. */
+
+	.bswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOB. */
+	.beevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOB. */
+	.bcpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOB. */
+	.bcpb     = TC_EVT_EFFECT_NOOP,                /* RB compare effect on TIOB. */
+
+	.aswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOA. */
+	.aeevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOA. */
+	.acpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOA: toggle. */
+	.acpa     = TC_EVT_EFFECT_NOOP,                /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
+
+	.wavsel   = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
+	.enetrg   = FALSE,                             /* External event trigger enable. */
+	.eevt     = 0,                                 /* External event selection. */
+	.eevtedg  = TC_SEL_NO_EDGE,                    /* External event edge selection. */
+	.cpcdis   = FALSE,                             /* Counter disable when RC compare. */
+	.cpcstop  = FALSE,                             /* Counter clock stopped with RC compare. */
+
+	.burst    = FALSE,                             /* Burst signal selection. */
+	.clki     = FALSE,                             /* Clock inversion. */
+	.tcclks   = TC_CLOCK_SOURCE_TC2                /* Internal source clock 2. */
+	};
+
+	tc_interrupt_t tc_interrupt =
+	{
+		.etrgs=0,
+		.ldrbs=0,
+		.ldras=0,
+		.cpcs =1,
+		.cpbs =0,
+		.cpas =0,
+		.lovrs=0,
+		.covfs=0,
+	};
+
+#endif
+
+	/* Disable all interrupt/exception. */
+	portDISABLE_INTERRUPTS();
+
+	/* Register the compare interrupt handler to the interrupt controller and
+	enable the compare interrupt. */
+
+	#if( configTICK_USE_TC==1 )
+	{
+		INTC_register_interrupt(&vTick, configTICK_TC_IRQ, INT0);
+
+		/* Initialize the timer/counter. */
+		tc_init_waveform(tc, &waveform_opt);
+
+		/* Set the compare triggers.
+		Remember TC counter is 16-bits, so counting second is not possible!
+		That's why we configure it to count ms. */
+		tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );
+
+		tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
+
+		/* Start the timer/counter. */
+		tc_start(tc, configTICK_TC_CHANNEL);
+	}
+	#else
+	{
+		INTC_register_interrupt(&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
+		prvScheduleFirstTick();
+	}
+	#endif
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/AVR32_UC3/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/AVR32_UC3/portmacro.h
new file mode 100644
index 0000000..fc51cb2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/AVR32_UC3/portmacro.h
@@ -0,0 +1,667 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief FreeRTOS port source for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+#include 
+#include "intc.h"
+#include "compiler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Type definitions. */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint32_t
+#define portBASE_TYPE   long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#define TASK_DELAY_MS(x)   ( (x)        /portTICK_PERIOD_MS )
+#define TASK_DELAY_S(x)    ( (x)*1000   /portTICK_PERIOD_MS )
+#define TASK_DELAY_MIN(x)  ( (x)*60*1000/portTICK_PERIOD_MS )
+
+#define configTICK_TC_IRQ             ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS      ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    4
+#define portNOP()             {__asm__ __volatile__ ("nop");}
+/*-----------------------------------------------------------*/
+
+
+/*-----------------------------------------------------------*/
+
+/* INTC-specific. */
+#define DISABLE_ALL_EXCEPTIONS()    Disable_global_exception()
+#define ENABLE_ALL_EXCEPTIONS()     Enable_global_exception()
+
+#define DISABLE_ALL_INTERRUPTS()    Disable_global_interrupt()
+#define ENABLE_ALL_INTERRUPTS()     Enable_global_interrupt()
+
+#define DISABLE_INT_LEVEL(int_lev)  Disable_interrupt_level(int_lev)
+#define ENABLE_INT_LEVEL(int_lev)   Enable_interrupt_level(int_lev)
+
+
+/*
+ * Debug trace.
+ * Activated if and only if configDBG is nonzero.
+ * Prints a formatted string to stdout.
+ * The current source file name and line number are output with a colon before
+ * the formatted string.
+ * A carriage return and a linefeed are appended to the output.
+ * stdout is redirected to the USART configured by configDBG_USART.
+ * The parameters are the same as for the standard printf function.
+ * There is no return value.
+ * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
+ * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
+ */
+#if configDBG
+#define portDBG_TRACE(...) \
+{\
+  fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout);\
+  printf(__VA_ARGS__);\
+  fputs("\r\n", stdout);\
+}
+#else
+#define portDBG_TRACE(...)
+#endif
+
+
+/* Critical section management. */
+#define portDISABLE_INTERRUPTS()  DISABLE_ALL_INTERRUPTS()
+#define portENABLE_INTERRUPTS()   ENABLE_ALL_INTERRUPTS()
+
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()      vPortEnterCritical();
+#define portEXIT_CRITICAL()       vPortExitCritical();
+
+
+/* Added as there is no such function in FreeRTOS. */
+extern void *pvPortRealloc( void *pv, size_t xSize );
+/*-----------------------------------------------------------*/
+
+
+/*=============================================================================================*/
+
+/*
+ * Restore Context for cases other than INTi.
+ */
+#define portRESTORE_CONTEXT()															\
+{																						\
+  extern volatile uint32_t ulCriticalNesting;									\
+  extern volatile void *volatile pxCurrentTCB;											\
+																						\
+  __asm__ __volatile__ (																\
+    /* Set SP to point to new stack */													\
+    "mov     r8, LO(%[pxCurrentTCB])													\n\t"\
+    "orh     r8, HI(%[pxCurrentTCB])													\n\t"\
+    "ld.w    r0, r8[0]																	\n\t"\
+    "ld.w    sp, r0[0]																	\n\t"\
+																						\
+    /* Restore ulCriticalNesting variable */											\
+    "ld.w    r0, sp++																	\n\t"\
+    "mov     r8, LO(%[ulCriticalNesting])												\n\t"\
+    "orh     r8, HI(%[ulCriticalNesting])												\n\t"\
+    "st.w    r8[0], r0																	\n\t"\
+																						\
+    /* Restore R0..R7 */																\
+    "ldm     sp++, r0-r7																\n\t"\
+    /* R0-R7 should not be used below this line */										\
+    /* Skip PC and SR (will do it at the end) */										\
+    "sub     sp, -2*4																	\n\t"\
+    /* Restore R8..R12 and LR */														\
+    "ldm     sp++, r8-r12, lr															\n\t"\
+    /* Restore SR */																	\
+    "ld.w    r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */					\
+    "mtsr    %[SR], r0																	\n\t"\
+    /* Restore r0 */																	\
+    "ld.w    r0, sp[-9*4]																\n\t"\
+    /* Restore PC */																	\
+    "ld.w    pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */		\
+    :																					\
+    : [ulCriticalNesting] "i" (&ulCriticalNesting),										\
+      [pxCurrentTCB] "i" (&pxCurrentTCB),												\
+      [SR] "i" (AVR32_SR)																\
+  );																					\
+}
+
+
+/*
+ * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
+ * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
+ *
+ * Had to make different versions because registers saved on the system stack
+ * are not the same between INT0..3 exceptions and the scall exception.
+ */
+
+// Task context stack layout:
+  // R8  (*)
+  // R9  (*)
+  // R10 (*)
+  // R11 (*)
+  // R12 (*)
+  // R14/LR (*)
+  // R15/PC (*)
+  // SR (*)
+  // R0
+  // R1
+  // R2
+  // R3
+  // R4
+  // R5
+  // R6
+  // R7
+  // ulCriticalNesting
+// (*) automatically done for INT0..INT3, but not for SCALL
+
+/*
+ * The ISR used for the scheduler tick depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+#if configUSE_PREEMPTION == 0
+
+/*
+ * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
+ */
+#define portSAVE_CONTEXT_OS_INT()														\
+{																						\
+  /* Save R0..R7 */																		\
+  __asm__ __volatile__ ("stm     --sp, r0-r7");											\
+																						\
+  /* With the cooperative scheduler, as there is no context switch by interrupt, */		\
+  /* there is also no context save. */													\
+}
+
+/*
+ * portRESTORE_CONTEXT_OS_INT() for Tick exception.
+ */
+#define portRESTORE_CONTEXT_OS_INT()													\
+{																						\
+  __asm__ __volatile__ (																\
+    /* Restore R0..R7 */																\
+    "ldm     sp++, r0-r7\n\t"															\
+																						\
+    /* With the cooperative scheduler, as there is no context switch by interrupt, */	\
+    /* there is also no context restore. */												\
+    "rete"																				\
+  );																					\
+}
+
+#else
+
+/*
+ * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
+ */
+#define portSAVE_CONTEXT_OS_INT()																	\
+{																									\
+  extern volatile uint32_t ulCriticalNesting;												\
+  extern volatile void *volatile pxCurrentTCB;														\
+																									\
+  /* When we come here */																			\
+  /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */					\
+																									\
+  __asm__ __volatile__ (																			\
+    /* Save R0..R7 */																				\
+    "stm     --sp, r0-r7																			\n\t"\
+																									\
+    /* Save ulCriticalNesting variable  - R0 is overwritten */										\
+    "mov     r8, LO(%[ulCriticalNesting])\n\t"														\
+    "orh     r8, HI(%[ulCriticalNesting])\n\t"														\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "st.w    --sp, r0																				\n\t"\
+																									\
+    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */	\
+    /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
+    /* level and allow other lower interrupt level to occur). */									\
+    /* In this case we don't want to do a task switch because we don't know what the stack */		\
+    /* currently looks like (we don't know what the interrupted interrupt handler was doing). */	\
+    /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */		\
+    /* will just be restoring the interrupt handler, no way!!! */									\
+    /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */					\
+    "ld.w    r0, sp[9*4]\n\t" /* Read SR in stack */												\
+    "bfextu  r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */									\
+    "cp.w    r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */						\
+    "brhi    LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]													\n\t"\
+																									\
+    /* Store SP in the first member of the structure pointed to by pxCurrentTCB */					\
+    /* NOTE: we don't enter a critical section here because all interrupt handlers */				\
+    /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */							\
+    /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */			\
+    /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */		\
+    "mov     r8, LO(%[pxCurrentTCB])\n\t"															\
+    "orh     r8, HI(%[pxCurrentTCB])\n\t"															\
+    "ld.w    r0, r8[0]\n\t"																			\
+    "st.w    r0[0], sp\n"																			\
+																									\
+    "LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:"															\
+    :																								\
+    : [ulCriticalNesting] "i" (&ulCriticalNesting),													\
+      [pxCurrentTCB] "i" (&pxCurrentTCB),															\
+      [LINE] "i" (__LINE__)																			\
+  );																								\
+}
+
+/*
+ * portRESTORE_CONTEXT_OS_INT() for Tick exception.
+ */
+#define portRESTORE_CONTEXT_OS_INT()																\
+{																									\
+  extern volatile uint32_t ulCriticalNesting;												\
+  extern volatile void *volatile pxCurrentTCB;														\
+																									\
+  /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */		\
+  /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
+  /* level and allow other lower interrupt level to occur). */										\
+  /* In this case we don't want to do a task switch because we don't know what the stack */			\
+  /* currently looks like (we don't know what the interrupted interrupt handler was doing). */		\
+  /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */			\
+  /* will just be restoring the interrupt handler, no way!!! */										\
+  __asm__ __volatile__ (																			\
+    "ld.w    r0, sp[9*4]\n\t" /* Read SR in stack */												\
+    "bfextu  r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */									\
+    "cp.w    r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */						\
+    "brhi    LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]"												\
+    :																								\
+    : [LINE] "i" (__LINE__)																			\
+  );																								\
+																									\
+  /* Else */																						\
+  /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */		\
+  /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
+  portENTER_CRITICAL();																				\
+  vTaskSwitchContext();																				\
+  portEXIT_CRITICAL();																				\
+																									\
+  /* Restore all registers */																		\
+																									\
+  __asm__ __volatile__ (																			\
+    /* Set SP to point to new stack */																\
+    "mov     r8, LO(%[pxCurrentTCB])																\n\t"\
+    "orh     r8, HI(%[pxCurrentTCB])																\n\t"\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "ld.w    sp, r0[0]																				\n"\
+																									\
+    "LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]:														\n\t"\
+																									\
+    /* Restore ulCriticalNesting variable */														\
+    "ld.w    r0, sp++																				\n\t"																			\
+    "mov     r8, LO(%[ulCriticalNesting])															\n\t"\
+    "orh     r8, HI(%[ulCriticalNesting])															\n\t"\
+    "st.w    r8[0], r0																				\n\t"\
+																									\
+    /* Restore R0..R7 */																			\
+    "ldm     sp++, r0-r7																			\n\t"\
+																									\
+    /* Now, the stack should be R8..R12, LR, PC and SR */											\
+    "rete"																							\
+    :																								\
+    : [ulCriticalNesting] "i" (&ulCriticalNesting),													\
+      [pxCurrentTCB] "i" (&pxCurrentTCB),															\
+      [LINE] "i" (__LINE__)																			\
+  );																								\
+}
+
+#endif
+
+
+/*
+ * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
+ *
+ * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
+ *
+ */
+#define portSAVE_CONTEXT_SCALL()															\
+{																							\
+  extern volatile uint32_t ulCriticalNesting;										\
+  extern volatile void *volatile pxCurrentTCB;												\
+																							\
+  /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */		\
+  /* If SR[M2:M0] == 001 */																	\
+  /*    PC and SR are on the stack.  */														\
+  /* Else (other modes) */																	\
+  /*    Nothing on the stack. */															\
+																							\
+  /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */		\
+  /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */		\
+  /* in an interrupt|exception handler. */													\
+																							\
+  __asm__ __volatile__ (																	\
+    /* in order to save R0-R7 */															\
+    "sub     sp, 6*4																		\n\t"\
+    /* Save R0..R7 */																		\
+    "stm     --sp, r0-r7																	\n\t"\
+																							\
+    /* in order to save R8-R12 and LR */													\
+    /* do not use SP if interrupts occurs, SP must be left at bottom of stack */			\
+    "sub     r7, sp,-16*4																	\n\t"\
+    /* Copy PC and SR in other places in the stack. */										\
+    "ld.w    r0, r7[-2*4]																	\n\t" /* Read SR */\
+    "st.w    r7[-8*4], r0																	\n\t" /* Copy SR */\
+    "ld.w    r0, r7[-1*4]																	\n\t" /* Read PC */\
+    "st.w    r7[-7*4], r0																	\n\t" /* Copy PC */\
+																							\
+    /* Save R8..R12 and LR on the stack. */													\
+    "stm     --r7, r8-r12, lr																\n\t"\
+																							\
+    /* Arriving here we have the following stack organizations: */							\
+    /* R8..R12, LR, PC, SR, R0..R7. */														\
+																							\
+    /* Now we can finalize the save. */														\
+																							\
+    /* Save ulCriticalNesting variable  - R0 is overwritten */								\
+    "mov     r8, LO(%[ulCriticalNesting])													\n\t"\
+    "orh     r8, HI(%[ulCriticalNesting])													\n\t"\
+    "ld.w    r0, r8[0]																		\n\t"\
+    "st.w    --sp, r0"																		\
+    :																						\
+    : [ulCriticalNesting] "i" (&ulCriticalNesting)											\
+  );																						\
+																							\
+  /* Disable the its which may cause a context switch (i.e. cause a change of */			\
+  /* pxCurrentTCB). */																		\
+  /* Basically, all accesses to the pxCurrentTCB structure should be put in a */			\
+  /* critical section because it is a global structure. */									\
+  portENTER_CRITICAL();																		\
+																							\
+  /* Store SP in the first member of the structure pointed to by pxCurrentTCB */			\
+  __asm__ __volatile__ (																	\
+    "mov     r8, LO(%[pxCurrentTCB])														\n\t"\
+    "orh     r8, HI(%[pxCurrentTCB])														\n\t"\
+    "ld.w    r0, r8[0]																		\n\t"\
+    "st.w    r0[0], sp"																		\
+    :																						\
+    : [pxCurrentTCB] "i" (&pxCurrentTCB)													\
+  );																						\
+}
+
+/*
+ * portRESTORE_CONTEXT() for SupervisorCALL exception.
+ */
+#define portRESTORE_CONTEXT_SCALL()															\
+{																							\
+  extern volatile uint32_t ulCriticalNesting;										\
+  extern volatile void *volatile pxCurrentTCB;												\
+																							\
+  /* Restore all registers */																\
+																							\
+  /* Set SP to point to new stack */														\
+  __asm__ __volatile__ (																	\
+    "mov     r8, LO(%[pxCurrentTCB])														\n\t"\
+    "orh     r8, HI(%[pxCurrentTCB])														\n\t"\
+    "ld.w    r0, r8[0]																		\n\t"\
+    "ld.w    sp, r0[0]"																		\
+    :																						\
+    : [pxCurrentTCB] "i" (&pxCurrentTCB)													\
+  );																						\
+																							\
+  /* Leave pxCurrentTCB variable access critical section */									\
+  portEXIT_CRITICAL();																		\
+																							\
+  __asm__ __volatile__ (																	\
+    /* Restore ulCriticalNesting variable */												\
+    "ld.w    r0, sp++																		\n\t"\
+    "mov     r8, LO(%[ulCriticalNesting])													\n\t"\
+    "orh     r8, HI(%[ulCriticalNesting])													\n\t"\
+    "st.w    r8[0], r0																		\n\t"\
+																							\
+    /* skip PC and SR */																	\
+    /* do not use SP if interrupts occurs, SP must be left at bottom of stack */			\
+    "sub     r7, sp, -10*4																	\n\t"\
+    /* Restore r8-r12 and LR */																\
+    "ldm     r7++, r8-r12, lr																\n\t"\
+																							\
+    /* RETS will take care of the extra PC and SR restore. */								\
+    /* So, we have to prepare the stack for this. */										\
+    "ld.w    r0, r7[-8*4]																	\n\t" /* Read SR */\
+    "st.w    r7[-2*4], r0																	\n\t" /* Copy SR */\
+    "ld.w    r0, r7[-7*4]																	\n\t" /* Read PC */\
+    "st.w    r7[-1*4], r0																	\n\t" /* Copy PC */\
+																							\
+    /* Restore R0..R7 */																	\
+    "ldm     sp++, r0-r7																	\n\t"\
+																							\
+    "sub     sp, -6*4																		\n\t"\
+																							\
+    "rets"																					\
+    :																						\
+    : [ulCriticalNesting] "i" (&ulCriticalNesting)											\
+  );																						\
+}
+
+
+/*
+ * The ISR used depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+#if configUSE_PREEMPTION == 0
+
+/*
+ * ISR entry and exit macros.  These are only required if a task switch
+ * is required from the ISR.
+ */
+#define portENTER_SWITCHING_ISR()															\
+{																							\
+  /* Save R0..R7 */																			\
+  __asm__ __volatile__ ("stm     --sp, r0-r7");												\
+																							\
+  /* With the cooperative scheduler, as there is no context switch by interrupt, */			\
+  /* there is also no context save. */														\
+}
+
+/*
+ * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
+ */
+#define portEXIT_SWITCHING_ISR()															\
+{																							\
+  __asm__ __volatile__ (																	\
+    /* Restore R0..R7 */																	\
+    "ldm     sp++, r0-r7																	\n\t"\
+																							\
+    /* With the cooperative scheduler, as there is no context switch by interrupt, */		\
+    /* there is also no context restore. */													\
+    "rete"																					\
+  );																						\
+}
+
+#else
+
+/*
+ * ISR entry and exit macros.  These are only required if a task switch
+ * is required from the ISR.
+ */
+#define portENTER_SWITCHING_ISR()															\
+{																							\
+  extern volatile uint32_t ulCriticalNesting;										\
+  extern volatile void *volatile pxCurrentTCB;												\
+																							\
+  /* When we come here */																	\
+  /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */			\
+																							\
+  __asm__ __volatile__ (																	\
+    /* Save R0..R7 */																		\
+    "stm     --sp, r0-r7																	\n\t"\
+																							\
+    /* Save ulCriticalNesting variable  - R0 is overwritten */								\
+    "mov     r8, LO(%[ulCriticalNesting])													\n\t"\
+    "orh     r8, HI(%[ulCriticalNesting])													\n\t"\
+    "ld.w    r0, r8[0]																		\n\t"\
+    "st.w    --sp, r0																		\n\t"\
+																									\
+    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */	\
+    /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
+    /* level and allow other lower interrupt level to occur). */									\
+    /* In this case we don't want to do a task switch because we don't know what the stack */		\
+    /* currently looks like (we don't know what the interrupted interrupt handler was doing). */	\
+    /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */		\
+    /* will just be restoring the interrupt handler, no way!!! */									\
+    /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */					\
+    "ld.w    r0, sp[9*4]																	\n\t" /* Read SR in stack */\
+    "bfextu  r0, r0, 22, 3																	\n\t" /* Extract the mode bits to R0. */\
+    "cp.w    r0, 1																			\n\t" /* Compare the mode bits with supervisor mode(b'001) */\
+    "brhi    LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]											\n\t"\
+																							\
+    /* Store SP in the first member of the structure pointed to by pxCurrentTCB */			\
+    "mov     r8, LO(%[pxCurrentTCB])														\n\t"\
+    "orh     r8, HI(%[pxCurrentTCB])														\n\t"\
+    "ld.w    r0, r8[0]																		\n\t"\
+    "st.w    r0[0], sp																		\n"\
+																							\
+    "LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:"													\
+    :																						\
+    : [ulCriticalNesting] "i" (&ulCriticalNesting),											\
+      [pxCurrentTCB] "i" (&pxCurrentTCB),													\
+      [LINE] "i" (__LINE__)																	\
+  );																						\
+}
+
+/*
+ * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
+ */
+#define portEXIT_SWITCHING_ISR()															\
+{																							\
+  extern volatile uint32_t ulCriticalNesting;										\
+  extern volatile void *volatile pxCurrentTCB;												\
+																							\
+  __asm__ __volatile__ (																	\
+    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */		\
+    /* interrupt handler (which was of a higher priority level but decided to lower its priority */		\
+    /* level and allow other lower interrupt level to occur). */										\
+    /* In this case it's of no use to switch context and restore a new SP because we purposedly */		\
+    /* did not previously save SP in its TCB. */																				\
+    "ld.w    r0, sp[9*4]																	\n\t" /* Read SR in stack */\
+    "bfextu  r0, r0, 22, 3																	\n\t" /* Extract the mode bits to R0. */\
+    "cp.w    r0, 1																			\n\t" /* Compare the mode bits with supervisor mode(b'001) */\
+    "brhi    LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]											\n\t"\
+																							\
+    /* If a switch is required then we just need to call */									\
+    /* vTaskSwitchContext() as the context has already been */								\
+    /* saved. */																			\
+    "cp.w    r12, 1																			\n\t" /* Check if Switch context is required. */\
+    "brne    LABEL_ISR_RESTORE_CONTEXT_%[LINE]"												\
+    :																						\
+    : [LINE] "i" (__LINE__)																	\
+  );																						\
+																							\
+  /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */	\
+  portENTER_CRITICAL();																		\
+  vTaskSwitchContext();																		\
+  portEXIT_CRITICAL();																		\
+																							\
+  __asm__ __volatile__ (																	\
+    "LABEL_ISR_RESTORE_CONTEXT_%[LINE]:														\n\t"\
+    /* Restore the context of which ever task is now the highest */							\
+    /* priority that is ready to run. */													\
+																							\
+    /* Restore all registers */																\
+																							\
+    /* Set SP to point to new stack */														\
+    "mov     r8, LO(%[pxCurrentTCB])														\n\t"\
+    "orh     r8, HI(%[pxCurrentTCB])														\n\t"\
+    "ld.w    r0, r8[0]																		\n\t"\
+    "ld.w    sp, r0[0]																		\n"\
+																							\
+    "LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]:												\n\t"\
+																							\
+    /* Restore ulCriticalNesting variable */												\
+    "ld.w    r0, sp++																		\n\t"\
+    "mov     r8, LO(%[ulCriticalNesting])													\n\t"\
+    "orh     r8, HI(%[ulCriticalNesting])													\n\t"\
+    "st.w    r8[0], r0																		\n\t"\
+																							\
+    /* Restore R0..R7 */																	\
+    "ldm     sp++, r0-r7																	\n\t"\
+																							\
+    /* Now, the stack should be R8..R12, LR, PC and SR  */									\
+    "rete"																					\
+    :																						\
+    : [ulCriticalNesting] "i" (&ulCriticalNesting),											\
+      [pxCurrentTCB] "i" (&pxCurrentTCB),													\
+      [LINE] "i" (__LINE__)																	\
+  );																						\
+}
+
+#endif
+
+
+#define portYIELD()                 {__asm__ __volatile__ ("scall");}
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/CORTUS_APS3/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/CORTUS_APS3/port.c
new file mode 100644
index 0000000..ca6adf1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/CORTUS_APS3/port.c
@@ -0,0 +1,145 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Machine includes */
+#include 
+#include 
+/*-----------------------------------------------------------*/
+
+/* The initial PSR has the Previous Interrupt Enabled (PIEN) flag set. */
+#define portINITIAL_PSR			( 0x00020000 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Perform any hardware configuration necessary to generate the tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Make space on the stack for the context - this leaves a couple of spaces
+	empty.  */
+	pxTopOfStack -= 20;
+
+	/* Fill the registers with known values to assist debugging. */
+	pxTopOfStack[ 16 ] = 0;
+	pxTopOfStack[ 15 ] = portINITIAL_PSR;
+	pxTopOfStack[ 14 ] = ( uint32_t ) pxCode;
+	pxTopOfStack[ 13 ] = 0x00000000UL; /* R15. */
+	pxTopOfStack[ 12 ] = 0x00000000UL; /* R14. */
+	pxTopOfStack[ 11 ] = 0x0d0d0d0dUL;
+	pxTopOfStack[ 10 ] = 0x0c0c0c0cUL;
+	pxTopOfStack[ 9 ] = 0x0b0b0b0bUL;
+	pxTopOfStack[ 8 ] = 0x0a0a0a0aUL;
+	pxTopOfStack[ 7 ] = 0x09090909UL;
+	pxTopOfStack[ 6 ] = 0x08080808UL;
+	pxTopOfStack[ 5 ] = 0x07070707UL;
+	pxTopOfStack[ 4 ] = 0x06060606UL;
+	pxTopOfStack[ 3 ] = 0x05050505UL;
+	pxTopOfStack[ 2 ] = 0x04040404UL;
+	pxTopOfStack[ 1 ] = 0x03030303UL;
+	pxTopOfStack[ 0 ] = ( uint32_t ) pvParameters;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Set-up the timer interrupt. */
+	prvSetupTimerInterrupt();
+
+	/* Integrated Interrupt Controller: Enable all interrupts. */
+	ic->ien = 1;
+
+	/* Restore callee saved registers. */
+	portRESTORE_CONTEXT();
+
+	/* Should not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+	/* Enable timer interrupts */
+	counter1->reload = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1;
+	counter1->value = counter1->reload;
+	counter1->mask = 1;
+
+	/* Set the IRQ Handler priority and enable it. */
+	irq[ IRQ_COUNTER1 ].ien = 1;
+}
+/*-----------------------------------------------------------*/
+
+/* Trap 31 handler. */
+void interrupt31_handler( void ) __attribute__((naked));
+void interrupt31_handler( void )
+{
+	portSAVE_CONTEXT();
+	__asm volatile ( "call vTaskSwitchContext" );
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessTick( void ) __attribute__((noinline));
+static void prvProcessTick( void )
+{
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		vTaskSwitchContext();
+	}
+		
+	/* Clear the Tick Interrupt. */
+	counter1->expired = 0;
+}
+/*-----------------------------------------------------------*/
+
+/* Timer 1 interrupt handler, used for tick interrupt. */
+void interrupt7_handler( void ) __attribute__((naked));
+void interrupt7_handler( void )
+{
+	portSAVE_CONTEXT();
+	prvProcessTick();
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Nothing to do. Unlikely to want to end. */
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/CORTUS_APS3/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/CORTUS_APS3/portmacro.h
new file mode 100644
index 0000000..f641997
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/CORTUS_APS3/portmacro.h
@@ -0,0 +1,152 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH							( -1 )
+#define portTICK_PERIOD_MS							( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT							4
+#define portNOP()									__asm__ volatile ( "mov r0, r0" )
+#define portCRITICAL_NESTING_IN_TCB					1
+#define portIRQ_TRAP_YIELD							31
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+extern void vPortYield( void );
+
+/*---------------------------------------------------------------------------*/
+
+#define portYIELD()		asm __volatile__( " trap #%0 "::"i"(portIRQ_TRAP_YIELD):"memory")
+/*---------------------------------------------------------------------------*/
+
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()		vTaskEnterCritical()
+#define portEXIT_CRITICAL()			vTaskExitCritical()
+/*---------------------------------------------------------------------------*/
+
+/* Critical section management. */
+#define portDISABLE_INTERRUPTS() 	cpu_int_disable()
+#define portENABLE_INTERRUPTS() 	cpu_int_enable()
+
+/*---------------------------------------------------------------------------*/
+
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken != pdFALSE ) vTaskSwitchContext()
+
+/*---------------------------------------------------------------------------*/
+
+#define portSAVE_CONTEXT()				\
+	asm __volatile__																								\
+	(																												\
+		"sub	r1, #68					\n" /* Make space on the stack for the context. */							\
+		"std	r2, [r1] + 	0			\n"																			\
+		"stq	r4, [r1] +	8			\n"																			\
+		"stq	r8, [r1] +	24			\n"																			\
+		"stq	r12, [r1] +	40			\n"																			\
+		"mov	r6, rtt					\n"																			\
+		"mov	r7, psr					\n"																			\
+		"std	r6, [r1] +	56			\n"																			\
+		"movhi	r2, #16384				\n"	/* Set the pointer to the IC. */										\
+		"ldub	r3, [r2] + 2			\n"	/* Load the current interrupt mask. */									\
+		"st		r3, [r1]+ 64			\n"	/* Store the interrupt mask on the stack. */ 							\
+		"ld		r2, [r0]+short(pxCurrentTCB)	\n"	/* Load the pointer to the TCB. */								\
+		"st		r1, [r2]				\n"	/* Save the stack pointer into the TCB. */								\
+		"mov	r14, r1					\n"	/* Compiler expects r14 to be set to the function stack. */				\
+	);
+/*---------------------------------------------------------------------------*/
+
+#define portRESTORE_CONTEXT()																						\
+	asm __volatile__(																								\
+		"ld		r2, [r0]+short(pxCurrentTCB)	\n"	/* Load the TCB to find the stack pointer and context. */		\
+		"ld		r1, [r2]				\n"																			\
+		"movhi	r2, #16384				\n"	/* Set the pointer to the IC. */										\
+		"ld		r3, [r1] + 64			\n"	/* Load the previous interrupt mask. */									\
+		"stb	r3, [r2] + 2  			\n"	/* Set the current interrupt mask to be the previous. */				\
+		"ldd	r6, [r1] + 56			\n"	/* Restore context. */													\
+		"mov	rtt, r6					\n"																			\
+		"mov	psr, r7					\n"																			\
+		"ldd	r2, [r1] + 0			\n"																			\
+		"ldq	r4, [r1] +	8			\n"																			\
+		"ldq	r8, [r1] +	24			\n"																			\
+		"ldq	r12, [r1] +	40			\n"																			\
+		"add	r1, #68					\n"																			\
+		"rti							\n"																			\
+	 );
+
+/*---------------------------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*---------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ColdFire_V2/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ColdFire_V2/port.c
new file mode 100644
index 0000000..995c6d9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ColdFire_V2/port.c
@@ -0,0 +1,134 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#define portINITIAL_FORMAT_VECTOR		( ( StackType_t ) 0x4000 )
+
+/* Supervisor mode set. */
+#define portINITIAL_STATUS_REGISTER		( ( StackType_t ) 0x2000)
+
+/* Used to keep track of the number of nested calls to taskENTER_CRITICAL().  This
+will be set to 0 prior to the first task being started. */
+static uint32_t ulCriticalNesting = 0x9999UL;
+
+/*-----------------------------------------------------------*/
+
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	*pxTopOfStack = ( StackType_t ) pvParameters;
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) 0xDEADBEEF;
+	pxTopOfStack--;
+
+	/* Exception stack frame starts with the return address. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER );
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0x0; /*FP*/
+	pxTopOfStack -= 14; /* A5 to D0. */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+
+	ulCriticalNesting = 0UL;
+
+	/* Configure the interrupts used by this port. */
+	vApplicationSetupInterrupts();
+
+	/* Start the first task executing. */
+	vPortStartFirstTask();
+
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented as there is nothing to return to. */
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	if( ulCriticalNesting == 0UL )
+	{
+		/* Guard against context switches being pended simultaneously with a
+		critical section being entered. */
+		do
+		{
+			portDISABLE_INTERRUPTS();
+			if( MCF_INTC0_INTFRCL == 0UL )
+			{
+				break;
+			}
+
+			portENABLE_INTERRUPTS();
+
+		} while( 1 );
+	}
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	ulCriticalNesting--;
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortYieldHandler( void )
+{
+uint32_t ulSavedInterruptMask;
+
+	ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+		/* Note this will clear all forced interrupts - this is done for speed. */
+		MCF_INTC0_INTFRCL = 0;
+		vTaskSwitchContext();
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
+}
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ColdFire_V2/portasm.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ColdFire_V2/portasm.S
new file mode 100644
index 0000000..a11608f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ColdFire_V2/portasm.S
@@ -0,0 +1,120 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Purpose: Lowest level routines for all ColdFire processors.
+ *
+ * Notes:
+ * 
+ * ulPortSetIPL() and mcf5xxx_wr_cacr() copied with permission from FreeScale
+ * supplied source files.
+ */
+
+    .global ulPortSetIPL
+    .global mcf5xxx_wr_cacr
+    .global __cs3_isr_interrupt_80
+    .global vPortStartFirstTask
+
+    .text
+
+.macro portSAVE_CONTEXT
+
+	lea.l		(-60, %sp), %sp
+	movem.l		%d0-%fp, (%sp)
+	move.l		pxCurrentTCB, %a0
+	move.l		%sp, (%a0)
+
+	.endm
+
+.macro portRESTORE_CONTEXT
+
+	move.l		pxCurrentTCB, %a0
+	move.l		(%a0), %sp
+	movem.l		(%sp), %d0-%fp
+	lea.l		%sp@(60), %sp
+	rte
+
+	.endm
+
+/********************************************************************/
+/*
+ * This routines changes the IPL to the value passed into the routine.
+ * It also returns the old IPL value back.
+ * Calling convention from C:
+ *   old_ipl = asm_set_ipl(new_ipl);
+ * For the Diab Data C compiler, it passes return value thru D0.
+ * Note that only the least significant three bits of the passed
+ * value are used.
+ */
+
+ulPortSetIPL:
+    link    A6,#-8
+    movem.l D6-D7,(SP)
+
+    move.w  SR,D7       /* current sr    */
+
+    move.l  D7,D0       /* prepare return value  */
+    andi.l  #0x0700,D0  /* mask out IPL  */
+    lsr.l   #8,D0       /* IPL   */
+
+    move.l  8(A6),D6    /* get argument  */
+    andi.l  #0x07,D6    /* least significant three bits  */
+    lsl.l   #8,D6       /* move over to make mask    */
+
+    andi.l  #0x0000F8FF,D7  /* zero out current IPL  */
+    or.l    D6,D7           /* place new IPL in sr   */
+    move.w  D7,SR
+
+    movem.l (SP),D6-D7
+    lea     8(SP),SP
+    unlk    A6
+    rts
+/********************************************************************/
+
+mcf5xxx_wr_cacr:
+    move.l  4(sp),d0
+    .long   0x4e7b0002  /* movec d0,cacr   */
+    nop
+    rts
+
+/********************************************************************/
+
+/* Yield interrupt. */
+__cs3_isr_interrupt_80:
+	portSAVE_CONTEXT
+	jsr vPortYieldHandler
+	portRESTORE_CONTEXT
+
+/********************************************************************/
+
+
+vPortStartFirstTask:
+	portRESTORE_CONTEXT
+
+    .end
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ColdFire_V2/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ColdFire_V2/portmacro.h
new file mode 100644
index 0000000..550281f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/ColdFire_V2/portmacro.h
@@ -0,0 +1,114 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			4
+#define portSTACK_GROWTH			-1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+uint32_t ulPortSetIPL( uint32_t );
+#define portDISABLE_INTERRUPTS()	ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portENABLE_INTERRUPTS()		ulPortSetIPL( 0 )
+
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+
+extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
+extern void vPortClearInterruptMaskFromISR( UBaseType_t );
+#define portSET_INTERRUPT_MASK_FROM_ISR()	ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+#define portNOP()	asm volatile ( 	"nop" )
+
+/* Note this will overwrite all other bits in the force register, it is done this way for speed. */
+#define portYIELD()			MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#define portEND_SWITCHING_ISR( xSwitchRequired )	if( xSwitchRequired != pdFALSE )	\
+													{									\
+														portYIELD();					\
+													}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/H8S2329/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/H8S2329/port.c
new file mode 100644
index 0000000..88295f9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/H8S2329/port.c
@@ -0,0 +1,303 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the H8S port.
+ *----------------------------------------------------------*/
+
+
+/*-----------------------------------------------------------*/
+
+/* When the task starts interrupts should be enabled. */
+#define portINITIAL_CCR			( ( StackType_t ) 0x00 )
+
+/* Hardware specific constants used to generate the RTOS tick from the TPU. */
+#define portCLEAR_ON_TGRA_COMPARE_MATCH ( ( uint8_t ) 0x20 )
+#define portCLOCK_DIV_64				( ( uint8_t ) 0x03 )
+#define portCLOCK_DIV					( ( uint32_t ) 64 )
+#define portTGRA_INTERRUPT_ENABLE		( ( uint8_t ) 0x01 )
+#define portTIMER_CHANNEL				( ( uint8_t ) 0x02 )
+#define portMSTP13						( ( uint16_t ) 0x2000 )
+
+/*
+ * Setup TPU channel one for the RTOS tick at the requested frequency.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * The ISR used by portYIELD(). This is installed as a trap handler.
+ */
+void vPortYield( void ) __attribute__ ( ( saveall, interrupt_handler ) );
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint32_t ulValue;
+
+	/* This requires an even address. */
+	ulValue = ( uint32_t ) pxTopOfStack;
+	if( ulValue & 1UL )
+	{
+		pxTopOfStack = pxTopOfStack - 1;
+	}
+
+	/* Place a few bytes of known values on the bottom of the stack. 
+	This is just useful for debugging. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0xaa;
+	pxTopOfStack--;
+	*pxTopOfStack = 0xbb;
+	pxTopOfStack--;
+	*pxTopOfStack = 0xcc;
+	pxTopOfStack--;
+	*pxTopOfStack = 0xdd;
+
+	/* The initial stack mimics an interrupt stack.  First there is the program
+	counter (24 bits). */
+	ulValue = ( uint32_t ) pxCode;
+
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+	pxTopOfStack--;
+	ulValue >>= 8UL;
+	*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+	pxTopOfStack--;
+	ulValue >>= 8UL;
+	*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+
+	/* Followed by the CCR. */	
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_CCR;
+
+	/* Next all the general purpose registers - with the parameters being passed
+	in ER0.  The parameter order must match that used by the compiler when the
+	"saveall" function attribute is used. */
+
+	/* ER6 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x66;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x66;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x66;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x66;
+	
+	/* ER0 */
+	ulValue = ( uint32_t ) pvParameters;
+
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+	pxTopOfStack--;
+	ulValue >>= 8UL;
+	*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+	pxTopOfStack--;
+	ulValue >>= 8UL;
+	*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+	pxTopOfStack--;
+	ulValue >>= 8UL;
+	*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+	
+	/* ER1 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x11;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x11;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x11;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x11;
+
+	/* ER2 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22;
+
+	/* ER3 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33;
+
+	/* ER4 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x44;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x44;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x44;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x44;
+
+	/* ER5 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x55;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x55;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x55;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x55;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void * pxCurrentTCB;
+
+	/* Setup the hardware to generate the tick. */
+	prvSetupTimerInterrupt();
+
+	/* Restore the context of the first task that is going to run.  This
+	mirrors the function epilogue code generated by the compiler when the
+	"saveall" function attribute is used. */
+	asm volatile ( 
+					"MOV.L		@_pxCurrentTCB, ER6			\n\t"
+					"MOV.L		@ER6, ER7					\n\t"
+					"LDM.L     	@SP+, (ER4-ER5)				\n\t"
+					"LDM.L     	@SP+, (ER0-ER3)				\n\t"
+					"MOV.L     	@ER7+, ER6					\n\t"
+					"RTE									\n\t"
+				);
+
+	( void ) pxCurrentTCB;
+
+	/* Should not get here. */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the h8 port will get stopped. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch.  This is a trap handler.  The "saveall" function
+ * attribute is used so the context is saved by the compiler prologue.  All
+ * we have to do is save the stack pointer.
+ */
+void vPortYield( void )
+{
+	portSAVE_STACK_POINTER();
+		vTaskSwitchContext();
+	portRESTORE_STACK_POINTER();
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * The interrupt handler installed for the RTOS tick depends on whether the 
+ * preemptive or cooperative scheduler is being used. 
+ */
+#if( configUSE_PREEMPTION == 1 )
+
+	/* 
+	 * The preemptive scheduler is used so the ISR calls vTaskSwitchContext().
+	 * The function prologue saves the context so all we have to do is save
+	 * the stack pointer.
+	 */
+	void vTickISR( void ) __attribute__ ( ( saveall, interrupt_handler ) );
+	void vTickISR( void )
+	{
+		portSAVE_STACK_POINTER();
+		
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			vTaskSwitchContext();
+		}
+
+		/* Clear the interrupt. */
+		TSR1 &= ~0x01;
+
+		portRESTORE_STACK_POINTER();
+	}
+
+#else
+
+	/*
+	 * The cooperative scheduler is being used so all we have to do is 
+	 * periodically increment the tick.  This can just be a normal ISR and
+	 * the "saveall" attribute is not required.
+	 */
+	void vTickISR( void ) __attribute__ ( ( interrupt_handler ) );
+	void vTickISR( void )
+	{
+		xTaskIncrementTick();
+
+		/* Clear the interrupt. */
+		TSR1 &= ~0x01;
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup timer 1 compare match to generate a tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+const uint32_t ulCompareMatch = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / portCLOCK_DIV;
+
+	/* Turn the module on. */
+	MSTPCR &= ~portMSTP13;
+
+	/* Configure timer 1. */
+	TCR1 = portCLEAR_ON_TGRA_COMPARE_MATCH | portCLOCK_DIV_64;
+
+	/* Configure the compare match value for a tick of configTICK_RATE_HZ. */
+	TGR1A = ulCompareMatch;
+
+	/* Start the timer and enable the interrupt - we can do this here as 
+	interrupts are globally disabled when this function is called. */
+	TIER1 |= portTGRA_INTERRUPT_ENABLE;
+	TSTR |= portTIMER_CHANNEL;
+}
+/*-----------------------------------------------------------*/
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/H8S2329/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/H8S2329/portmacro.h
new file mode 100644
index 0000000..147616c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/H8S2329/portmacro.h
@@ -0,0 +1,138 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint8_t
+#define portBASE_TYPE	char
+
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			2
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portYIELD()					asm volatile( "TRAPA #0" )
+#define portNOP()					asm volatile( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+#define portENABLE_INTERRUPTS()		asm volatile( "ANDC	#0x7F, CCR" );
+#define portDISABLE_INTERRUPTS()	asm volatile( "ORC  #0x80, CCR" );
+
+/* Push the CCR then disable interrupts. */
+#define portENTER_CRITICAL()  		asm volatile( "STC	CCR, @-ER7" ); \
+                               		portDISABLE_INTERRUPTS();
+
+/* Pop the CCR to set the interrupt masking back to its previous state. */
+#define  portEXIT_CRITICAL()    	asm volatile( "LDC  @ER7+, CCR" );
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* Context switch macros.  These macros are very simple as the context
+is saved simply by selecting the saveall attribute of the context switch
+interrupt service routines.  These macros save and restore the stack
+pointer to the TCB. */
+
+#define portSAVE_STACK_POINTER()								\
+extern void* pxCurrentTCB;										\
+																\
+	asm volatile(												\
+					"MOV.L	@_pxCurrentTCB, ER5			\n\t" 	\
+					"MOV.L	ER7, @ER5					\n\t"	\
+				);												\
+	( void ) pxCurrentTCB;
+
+
+#define	portRESTORE_STACK_POINTER()								\
+extern void* pxCurrentTCB;										\
+																\
+	asm volatile(												\
+					"MOV.L	@_pxCurrentTCB, ER5			\n\t"	\
+					"MOV.L	@ER5, ER7					\n\t"	\
+				);												\
+	( void ) pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/* Macros to allow a context switch from within an application ISR. */
+
+#define portENTER_SWITCHING_ISR() portSAVE_STACK_POINTER(); {
+
+#define portEXIT_SWITCHING_ISR( x )							\
+	if( x )													\
+	{														\
+		extern void vTaskSwitchContext( void );				\
+		vTaskSwitchContext();								\
+	}														\
+	} portRESTORE_STACK_POINTER();
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/HCS12/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/HCS12/port.c
new file mode 100644
index 0000000..bc3f60d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/HCS12/port.c
@@ -0,0 +1,237 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* GCC/HCS12 port by Jefferson L Smith, 2005 */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Port includes */
+#include 
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the HCS12 port.
+ *----------------------------------------------------------*/
+
+
+/*
+ * Configure a timer to generate the RTOS tick at the frequency specified 
+ * within FreeRTOSConfig.h.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/* NOTE: Interrupt service routines must be in non-banked memory - as does the
+scheduler startup function. */
+#define ATTR_NEAR	__attribute__((near))
+
+/* Manual context switch function.  This is the SWI ISR. */
+// __attribute__((interrupt))
+void ATTR_NEAR vPortYield( void );
+
+/* Tick context switch function.  This is the timer ISR. */
+// __attribute__((interrupt))
+void ATTR_NEAR vPortTickInterrupt( void );
+
+/* Function in non-banked memory which actually switches to first task. */
+BaseType_t ATTR_NEAR xStartSchedulerNear( void );
+
+/* Calls to portENTER_CRITICAL() can be nested.  When they are nested the 
+critical section should not be left (i.e. interrupts should not be re-enabled)
+until the nesting depth reaches 0.  This variable simply tracks the nesting 
+depth.  Each task maintains it's own critical nesting depth variable so 
+uxCriticalNesting is saved and restored from the task stack during a context
+switch. */
+volatile UBaseType_t uxCriticalNesting = 0x80;  // un-initialized
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+
+
+	/* Setup the initial stack of the task.  The stack is set exactly as 
+	expected by the portRESTORE_CONTEXT() macro.  In this case the stack as
+	expected by the HCS12 RTI instruction. */
+
+
+	/* The address of the task function is placed in the stack byte at a time. */
+	*pxTopOfStack   = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 1 );
+	*--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 0 );
+
+	/* Next are all the registers that form part of the task context. */
+
+	/* Y register */
+	*--pxTopOfStack = ( StackType_t ) 0xff;
+	*--pxTopOfStack = ( StackType_t ) 0xee;
+
+	/* X register */
+	*--pxTopOfStack = ( StackType_t ) 0xdd;
+	*--pxTopOfStack = ( StackType_t ) 0xcc;
+ 
+	/* A register contains parameter high byte. */
+	*--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 0 );
+
+	/* B register contains parameter low byte. */
+	*--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 1 );
+
+	/* CCR: Note that when the task starts interrupts will be enabled since
+	"I" bit of CCR is cleared */
+	*--pxTopOfStack = ( StackType_t ) 0x80;		// keeps Stop disabled (MCU default)
+	
+	/* tmp softregs used by GCC. Values right now don't	matter. */
+	__asm("\n\
+		movw _.frame, 2,-%0							\n\
+		movw _.tmp, 2,-%0							\n\
+		movw _.z, 2,-%0								\n\
+		movw _.xy, 2,-%0							\n\
+		;movw _.d2, 2,-%0							\n\
+		;movw _.d1, 2,-%0							\n\
+	": "=A"(pxTopOfStack) : "0"(pxTopOfStack) );
+
+	#ifdef BANKED_MODEL
+		/* The page of the task. */
+		*--pxTopOfStack = 0x30;      // can only directly start in PPAGE 0x30
+	#endif
+	
+	/* The critical nesting depth is initialised with 0 (meaning not in
+	a critical section). */
+	*--pxTopOfStack = ( StackType_t ) 0x00;
+
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the HCS12 port will get stopped. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+	/* Enable hardware RTI timer */
+	/* Ignores configTICK_RATE_HZ */
+	RTICTL = 0x50;			// 16 MHz xtal: 976.56 Hz, 1024mS 
+	CRGINT |= 0x80;			// RTIE
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* xPortStartScheduler() does not start the scheduler directly because 
+	the header file containing the xPortStartScheduler() prototype is part 
+	of the common kernel code, and therefore cannot use the CODE_SEG pragma. 
+	Instead it simply calls the locally defined xNearStartScheduler() - 
+	which does use the CODE_SEG pragma. */
+
+	int16_t register d;
+	__asm ("jmp  xStartSchedulerNear		; will never return": "=d"(d));
+	return d;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStartSchedulerNear( void )
+{
+	/* Configure the timer that will generate the RTOS tick.  Interrupts are
+	disabled when this function is called. */
+	prvSetupTimerInterrupt();
+
+	/* Restore the context of the first task. */
+	portRESTORE_CONTEXT();
+
+	portISR_TAIL();
+
+	/* Should not get here! */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Context switch functions.  These are interrupt service routines.
+ */
+
+/*
+ * Manual context switch forced by calling portYIELD().  This is the SWI
+ * handler.
+ */
+void vPortYield( void )
+{
+	portISR_HEAD();
+	/* NOTE: This is the trap routine (swi) although not defined as a trap.
+	   It will fill the stack the same way as an ISR in order to mix preemtion
+	   and cooperative yield. */
+
+	portSAVE_CONTEXT();
+	vTaskSwitchContext();
+	portRESTORE_CONTEXT();
+
+	portISR_TAIL();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * RTOS tick interrupt service routine.  If the cooperative scheduler is 
+ * being used then this simply increments the tick count.  If the 
+ * preemptive scheduler is being used a context switch can occur.
+ */
+void vPortTickInterrupt( void )
+{
+	portISR_HEAD();
+
+	/* Clear tick timer flag */
+	CRGFLG = 0x80;
+
+	#if configUSE_PREEMPTION == 1
+	{
+		/* A context switch might happen so save the context. */
+		portSAVE_CONTEXT();
+
+		/* Increment the tick ... */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is necessary. */
+			vTaskSwitchContext();
+		}
+
+		/* Restore the context of a task - which may be a different task
+		to that interrupted. */
+		portRESTORE_CONTEXT();
+	}
+	#else
+	{
+		xTaskIncrementTick();
+	}
+	#endif
+
+	portISR_TAIL();
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/HCS12/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/HCS12/portmacro.h
new file mode 100644
index 0000000..66e9a18
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/HCS12/portmacro.h
@@ -0,0 +1,246 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint8_t
+#define portBASE_TYPE	char
+
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			1
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portYIELD()					__asm( "swi" );
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+#define portENABLE_INTERRUPTS()				__asm( "cli" )
+#define portDISABLE_INTERRUPTS()			__asm( "sei" )
+
+/*
+ * Disable interrupts before incrementing the count of critical section nesting.
+ * The nesting count is maintained so we know when interrupts should be
+ * re-enabled.  Once interrupts are disabled the nesting count can be accessed
+ * directly.  Each task maintains its own nesting count.
+ */
+#define portENTER_CRITICAL()  									\
+{																\
+	extern volatile UBaseType_t uxCriticalNesting;	\
+																\
+	portDISABLE_INTERRUPTS();									\
+	uxCriticalNesting++;										\
+}
+
+/*
+ * Interrupts are disabled so we can access the nesting count directly.  If the
+ * nesting is found to be 0 (no nesting) then we are leaving the critical
+ * section and interrupts can be re-enabled.
+ */
+#define  portEXIT_CRITICAL()									\
+{																\
+	extern volatile UBaseType_t uxCriticalNesting;	\
+																\
+	uxCriticalNesting--;										\
+	if( uxCriticalNesting == 0 )								\
+	{															\
+		portENABLE_INTERRUPTS();								\
+	}															\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/*
+ * These macros are very simple as the processor automatically saves and
+ * restores its registers as interrupts are entered and exited.  In
+ * addition to the (automatically stacked) registers we also stack the
+ * critical nesting count.  Each task maintains its own critical nesting
+ * count as it is legitimate for a task to yield from within a critical
+ * section.  If the banked memory model is being used then the PPAGE
+ * register is also stored as part of the tasks context.
+ */
+
+#ifdef BANKED_MODEL
+	/*
+	 * Load the stack pointer for the task, then pull the critical nesting
+	 * count and PPAGE register from the stack.  The remains of the
+	 * context are restored by the RTI instruction.
+	 */
+	#define portRESTORE_CONTEXT()							\
+	{										\
+		__asm( "								\n\
+		.globl pxCurrentTCB			; void *			\n\
+		.globl uxCriticalNesting		; char				\n\
+											\n\
+		ldx  pxCurrentTCB							\n\
+		lds  0,x				; Stack				\n\
+											\n\
+		movb 1,sp+,uxCriticalNesting						\n\
+		movb 1,sp+,0x30				; PPAGE				\n\
+		" );									\
+	}
+
+	/*
+	 * By the time this macro is called the processor has already stacked the
+	 * registers.  Simply stack the nesting count and PPAGE value, then save
+	 * the task stack pointer.
+	 */
+	#define portSAVE_CONTEXT()							\
+	{										\
+		__asm( "								\n\
+		.globl pxCurrentTCB			; void *			\n\
+		.globl uxCriticalNesting		; char				\n\
+											\n\
+		movb 0x30, 1,-sp			; PPAGE				\n\
+		movb uxCriticalNesting, 1,-sp						\n\
+											\n\
+		ldx  pxCurrentTCB							\n\
+		sts  0,x				; Stack				\n\
+		" );									\
+	}
+#else
+
+	/*
+	 * These macros are as per the BANKED versions above, but without saving
+	 * and restoring the PPAGE register.
+	 */
+
+	#define portRESTORE_CONTEXT()							\
+	{										\
+		__asm( "								\n\
+		.globl pxCurrentTCB			; void *			\n\
+		.globl uxCriticalNesting		; char				\n\
+											\n\
+		ldx  pxCurrentTCB							\n\
+		lds  0,x				; Stack				\n\
+											\n\
+		movb 1,sp+,uxCriticalNesting						\n\
+		" );									\
+	}
+
+	#define portSAVE_CONTEXT()							\
+	{										\
+		__asm( "								\n\
+		.globl pxCurrentTCB			; void *			\n\
+		.globl uxCriticalNesting		; char				\n\
+											\n\
+		movb uxCriticalNesting, 1,-sp						\n\
+											\n\
+		ldx  pxCurrentTCB							\n\
+		sts  0,x				; Stack				\n\
+		" );									\
+	}
+#endif
+
+/*
+ * Utility macros to save/restore correct software registers for GCC. This is
+ * useful when GCC does not generate appropriate ISR head/tail code.
+ */
+#define portISR_HEAD()									\
+{											\
+		__asm("									\n\
+		movw _.frame, 2,-sp							\n\
+		movw _.tmp, 2,-sp							\n\
+		movw _.z, 2,-sp								\n\
+		movw _.xy, 2,-sp							\n\
+		;movw _.d2, 2,-sp							\n\
+		;movw _.d1, 2,-sp							\n\
+		");									\
+}
+
+#define portISR_TAIL()									\
+{											\
+		__asm("									\n\
+		movw 2,sp+, _.xy							\n\
+		movw 2,sp+, _.z								\n\
+		movw 2,sp+, _.tmp							\n\
+		movw 2,sp+, _.frame							\n\
+		;movw 2,sp+, _.d1							\n\
+		;movw 2,sp+, _.d2							\n\
+		rti									\n\
+		");									\
+}
+
+/*
+ * Utility macro to call macros above in correct order in order to perform a
+ * task switch from within a standard ISR.  This macro can only be used if
+ * the ISR does not use any local (stack) variables.  If the ISR uses stack
+ * variables portYIELD() should be used in it's place.
+ */
+
+#define portTASK_SWITCH_FROM_ISR()								\
+	portSAVE_CONTEXT();											\
+	vTaskSwitchContext();										\
+	portRESTORE_CONTEXT();
+
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/IA32_flat/ISR_Support.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/IA32_flat/ISR_Support.h
new file mode 100644
index 0000000..e45c274
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/IA32_flat/ISR_Support.h
@@ -0,0 +1,127 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	.extern ulTopOfSystemStack
+	.extern ulInterruptNesting
+
+/*-----------------------------------------------------------*/
+
+.macro portFREERTOS_INTERRUPT_ENTRY
+
+	/* Save general purpose registers. */
+	pusha
+
+	/* If ulInterruptNesting is zero the rest of the task context will need
+	saving and a stack switch might be required. */
+	movl	ulInterruptNesting, %eax
+	test	%eax, %eax
+	jne		2f
+
+	/* Interrupts are not nested, so save the rest of the task context. */
+	.if configSUPPORT_FPU == 1
+
+		/* If the task has a buffer allocated to save the FPU context then
+		save the FPU context now. */
+		movl	pucPortTaskFPUContextBuffer, %eax
+		test	%eax, %eax
+		je		1f
+		fnsave	( %eax ) /* Save FLOP context into ucTempFPUBuffer array. */
+		fwait
+
+		1:
+		/* Save the address of the FPU context, if any. */
+		push	pucPortTaskFPUContextBuffer
+
+	.endif /* configSUPPORT_FPU */
+
+	/* Find the TCB. */
+	movl 	pxCurrentTCB, %eax
+
+	/* Stack location is first item in the TCB. */
+	movl	%esp, (%eax)
+
+	/* Switch stacks. */
+	movl 	ulTopOfSystemStack, %esp
+	movl	%esp, %ebp
+
+	2:
+	/* Increment nesting count. */
+	add 	$1, ulInterruptNesting
+
+.endm
+/*-----------------------------------------------------------*/
+
+.macro portINTERRUPT_EPILOGUE
+
+	cli
+	sub		$1, ulInterruptNesting
+
+	/* If the nesting has unwound to zero. */
+	movl	ulInterruptNesting, %eax
+	test	%eax, %eax
+	jne		2f
+
+	/* If a yield was requested then select a new TCB now. */
+	movl	ulPortYieldPending, %eax
+	test	%eax, %eax
+	je		1f
+	movl	$0, ulPortYieldPending
+	call	vTaskSwitchContext
+
+	1:
+	/* Stack location is first item in the TCB. */
+	movl 	pxCurrentTCB, %eax
+	movl	(%eax), %esp
+
+	.if configSUPPORT_FPU == 1
+
+		/* Restore address of task's FPU context buffer. */
+		pop 	pucPortTaskFPUContextBuffer
+
+		/* If the task has a buffer allocated in which its FPU context is saved,
+		then restore it now. */
+		movl	pucPortTaskFPUContextBuffer, %eax
+		test	%eax, %eax
+		je		1f
+		frstor	( %eax )
+		1:
+	.endif
+
+	2:
+	popa
+
+.endm
+/*-----------------------------------------------------------*/
+
+.macro portFREERTOS_INTERRUPT_EXIT
+
+	portINTERRUPT_EPILOGUE
+	/* EOI. */
+	movl	$0x00, (0xFEE000B0)
+	iret
+
+.endm
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/IA32_flat/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/IA32_flat/port.c
new file mode 100644
index 0000000..56c0b4c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/IA32_flat/port.c
@@ -0,0 +1,686 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#if( configISR_STACK_SIZE < ( configMINIMAL_STACK_SIZE * 2 ) )
+	#warning configISR_STACK_SIZE is probably too small!
+#endif /* ( configISR_STACK_SIZE < configMINIMAL_STACK_SIZE * 2 ) */
+
+#if( ( configMAX_API_CALL_INTERRUPT_PRIORITY > portMAX_PRIORITY ) || ( configMAX_API_CALL_INTERRUPT_PRIORITY < 2 ) )
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be between 2 and 15
+#endif
+
+#if( ( configSUPPORT_FPU == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )
+	#error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port with an FPU
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+this value. */
+#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
+
+/* Tasks are not created with a floating point context, but can be given a
+floating point context after they have been created.  A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
+
+/* Only the IF bit is set so tasks start with interrupts enabled. */
+#define portINITIAL_EFLAGS				( 0x200UL )
+
+/* Error interrupts are at the highest priority vectors. */
+#define portAPIC_LVT_ERROR_VECTOR 		( 0xfe )
+#define portAPIC_SPURIOUS_INT_VECTOR 	( 0xff )
+
+/* EFLAGS bits. */
+#define portEFLAGS_IF					( 0x200UL )
+
+/* FPU context size if FSAVE is used. */
+#define portFPU_CONTEXT_SIZE_BYTES 		108
+
+/* The expected size of each entry in the IDT.  Used to check structure packing
+ is set correctly. */
+#define portEXPECTED_IDT_ENTRY_SIZE		8
+
+/* Default flags setting for entries in the IDT. */
+#define portIDT_FLAGS					( 0x8E )
+
+/* This is the lowest possible ISR vector available to application code. */
+#define portAPIC_MIN_ALLOWABLE_VECTOR	( 0x20 )
+
+/* If configASSERT() is defined then the system stack is filled with this value
+to allow for a crude stack overflow check. */
+#define portSTACK_WORD					( 0xecececec )
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing.
+ */
+extern void vPortStartFirstTask( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*
+ * Complete one descriptor in the IDT.
+ */
+static void prvSetInterruptGate( uint8_t ucNumber, ISR_Handler_t pxHandlerFunction, uint8_t ucFlags );
+
+/*
+ * The default handler installed in each IDT position.
+ */
+extern void vPortCentralInterruptWrapper( void );
+
+/*
+ * Handler for portYIELD().
+ */
+extern void vPortYieldCall( void );
+
+/*
+ * Configure the APIC to generate the RTOS tick.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * Tick interrupt handler.
+ */
+extern void vPortTimerHandler( void );
+
+/*
+ * Check an interrupt vector is not too high, too low, in use by FreeRTOS, or
+ * already in use by the application.
+ */
+static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting.  This
+variable must be initialised to a non zero value to ensure interrupts don't
+inadvertently become unmasked before the scheduler starts. It is set to zero
+before the first task starts executing. */
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/* A structure used to map the various fields of an IDT entry into separate
+structure members. */
+struct IDTEntry
+{
+	uint16_t usISRLow;				/* Low 16 bits of handler address. */
+	uint16_t usSegmentSelector;		/* Flat model means this is not changed. */
+	uint8_t ucZero;					/* Must be set to zero. */
+	uint8_t ucFlags;				/* Flags for this entry. */
+	uint16_t usISRHigh;				/* High 16 bits of handler address. */
+} __attribute__( ( packed ) );
+typedef struct IDTEntry IDTEntry_t;
+
+
+/* Use to pass the location of the IDT to the CPU. */
+struct IDTPointer
+{
+   uint16_t usTableLimit;
+   uint32_t ulTableBase;                /* The address of the first entry in xInterruptDescriptorTable. */
+} __attribute__( ( __packed__ ) );
+typedef struct IDTPointer IDTPointer_t;
+
+/* The IDT itself. */
+static __attribute__ ( ( aligned( 32 ) ) ) IDTEntry_t xInterruptDescriptorTable[ portNUM_VECTORS ];
+
+#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
+
+	/* A table in which application defined interrupt handlers are stored.  These
+	are called by the central interrupt handler if a common interrupt entry
+	point it used. */
+	static ISR_Handler_t xInterruptHandlerTable[ portNUM_VECTORS ] = { NULL };
+
+#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
+
+#if ( configSUPPORT_FPU == 1 )
+
+	/* Saved as part of the task context.  If pucPortTaskFPUContextBuffer is NULL
+	then the task does not have an FPU context.  If pucPortTaskFPUContextBuffer is
+	not NULL then it points to a buffer into which the FPU context can be saved. */
+	uint8_t *pucPortTaskFPUContextBuffer __attribute__((used)) = pdFALSE;
+
+#endif /* configSUPPORT_FPU */
+
+/* The stack used by interrupt handlers. */
+static uint32_t ulSystemStack[ configISR_STACK_SIZE ] __attribute__((used))  = { 0 };
+
+/* Don't use the very top of the system stack so the return address
+appears as 0 if the debugger tries to unwind the stack. */
+volatile uint32_t ulTopOfSystemStack __attribute__((used)) = ( uint32_t ) &( ulSystemStack[ configISR_STACK_SIZE - 5 ] );
+
+/* If a yield is requested from an interrupt or from a critical section then
+the yield is not performed immediately, and ulPortYieldPending is set to pdTRUE
+instead to indicate the yield should be performed at the end of the interrupt
+when the critical section is exited. */
+volatile uint32_t ulPortYieldPending __attribute__((used)) = pdFALSE;
+
+/* Counts the interrupt nesting depth.  Used to know when to switch to the
+interrupt/system stack and when to save/restore a complete context. */
+volatile uint32_t ulInterruptNesting __attribute__((used)) = 0;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint32_t ulCodeSegment;
+
+	/* Setup the initial stack as expected by the portFREERTOS_INTERRUPT_EXIT macro. */
+
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+
+	/* Parameters first. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;
+	pxTopOfStack--;
+
+	/* There is nothing to return to so assert if attempting to use the return
+	address. */
+	*pxTopOfStack = ( StackType_t ) prvTaskExitError;
+	pxTopOfStack--;
+
+	/* iret used to start the task pops up to here. */
+	*pxTopOfStack = portINITIAL_EFLAGS;
+	pxTopOfStack--;
+
+	/* CS */
+	__asm volatile( "movl %%cs, %0" : "=r" ( ulCodeSegment ) );
+	*pxTopOfStack = ulCodeSegment;
+	pxTopOfStack--;
+
+	/* First instruction in the task. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+
+	/* General purpose registers as expected by a POPA instruction. */
+	*pxTopOfStack = 0xEA;
+	pxTopOfStack--;
+
+	*pxTopOfStack = 0xEC;
+	pxTopOfStack--;
+
+	*pxTopOfStack = 0xED1; /* EDX */
+	pxTopOfStack--;
+
+	*pxTopOfStack = 0xEB1; /* EBX */
+	pxTopOfStack--;
+
+	/* Hole for ESP. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = 0x00; /* EBP */
+	pxTopOfStack--;
+
+	*pxTopOfStack = 0xE5; /* ESI */
+	pxTopOfStack--;
+
+	*pxTopOfStack = 0xeeeeeeee; /* EDI */
+
+	#if ( configSUPPORT_FPU == 1 )
+	{
+		pxTopOfStack--;
+
+		/* Buffer for FPU context, which is initialised to NULL as tasks are not
+		created with an FPU context. */
+		*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+	}
+	#endif /* configSUPPORT_FPU */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetInterruptGate( uint8_t ucNumber, ISR_Handler_t pxHandlerFunction, uint8_t ucFlags )
+{
+uint16_t usCodeSegment;
+uint32_t ulBase = ( uint32_t ) pxHandlerFunction;
+
+	xInterruptDescriptorTable[ ucNumber ].usISRLow = ( uint16_t ) ( ulBase & USHRT_MAX );
+	xInterruptDescriptorTable[ ucNumber ].usISRHigh = ( uint16_t ) ( ( ulBase >> 16UL ) & USHRT_MAX );
+
+	/* When the flat model is used the CS will never change. */
+	__asm volatile( "mov %%cs, %0" : "=r" ( usCodeSegment ) );
+	xInterruptDescriptorTable[ ucNumber ].usSegmentSelector = usCodeSegment;
+	xInterruptDescriptorTable[ ucNumber ].ucZero = 0;
+	xInterruptDescriptorTable[ ucNumber ].ucFlags = ucFlags;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetupIDT( void )
+{
+uint32_t ulNum;
+IDTPointer_t xIDT;
+
+	#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
+	{
+		for( ulNum = 0; ulNum < portNUM_VECTORS; ulNum++ )
+		{
+			/* If a handler has not already been installed on this vector. */
+			if( ( xInterruptDescriptorTable[ ulNum ].usISRLow == 0x00 ) && ( xInterruptDescriptorTable[ ulNum ].usISRHigh == 0x00 ) )
+			{
+				prvSetInterruptGate( ( uint8_t ) ulNum, vPortCentralInterruptWrapper, portIDT_FLAGS );
+			}
+		}
+	}
+	#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
+
+	/* Set IDT address. */
+	xIDT.ulTableBase = ( uint32_t ) xInterruptDescriptorTable;
+	xIDT.usTableLimit = sizeof( xInterruptDescriptorTable ) - 1;
+
+	/* Set IDT in CPU. */
+	__asm volatile( "lidt %0" :: "m" (xIDT) );
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( ulCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+extern void vPortAPICErrorHandlerWrapper( void );
+extern void vPortAPICSpuriousHandler( void );
+
+	/* Initialise LAPIC to a well known state. */
+	portAPIC_LDR = 0xFFFFFFFF;
+	portAPIC_LDR = ( ( portAPIC_LDR & 0x00FFFFFF ) | 0x00000001 );
+	portAPIC_LVT_TIMER = portAPIC_DISABLE;
+	portAPIC_LVT_PERF = portAPIC_NMI;
+	portAPIC_LVT_LINT0 = portAPIC_DISABLE;
+	portAPIC_LVT_LINT1 = portAPIC_DISABLE;
+	portAPIC_TASK_PRIORITY = 0;
+
+	/* Install APIC timer ISR vector. */
+	prvSetInterruptGate( ( uint8_t ) portAPIC_TIMER_INT_VECTOR, vPortTimerHandler, portIDT_FLAGS );
+
+	/* Install API error handler. */
+	prvSetInterruptGate( ( uint8_t ) portAPIC_LVT_ERROR_VECTOR, vPortAPICErrorHandlerWrapper, portIDT_FLAGS );
+
+	/* Install Yield handler. */
+	prvSetInterruptGate( ( uint8_t ) portAPIC_YIELD_INT_VECTOR, vPortYieldCall, portIDT_FLAGS );
+
+	/* Install spurious interrupt vector. */
+	prvSetInterruptGate( ( uint8_t ) portAPIC_SPURIOUS_INT_VECTOR, vPortAPICSpuriousHandler, portIDT_FLAGS );
+
+	/* Enable the APIC, mapping the spurious interrupt at the same time. */
+	portAPIC_SPURIOUS_INT = portAPIC_SPURIOUS_INT_VECTOR | portAPIC_ENABLE_BIT;
+
+	/* Set timer error vector. */
+	portAPIC_LVT_ERROR = portAPIC_LVT_ERROR_VECTOR;
+
+	/* Set the interrupt frequency. */
+	portAPIC_TMRDIV = portAPIC_DIV_16;
+	portAPIC_TIMER_INITIAL_COUNT = ( ( configCPU_CLOCK_HZ >> 4UL ) / configTICK_RATE_HZ ) - 1UL;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+BaseType_t xWord;
+
+	/* Some versions of GCC require the -mno-ms-bitfields command line option
+	for packing to work. */
+	configASSERT( sizeof( struct IDTEntry ) == portEXPECTED_IDT_ENTRY_SIZE );
+
+	/* Fill part of the system stack with a known value to help detect stack
+	overflow.  A few zeros are left so GDB doesn't get confused unwinding
+	the stack. */
+	for( xWord = 0; xWord < configISR_STACK_SIZE - 20; xWord++ )
+	{
+		ulSystemStack[ xWord ] = portSTACK_WORD;
+	}
+
+	/* Initialise Interrupt Descriptor Table (IDT). */
+	vPortSetupIDT();
+
+	/* Initialise LAPIC and install system handlers. */
+	prvSetupTimerInterrupt();
+
+	/* Make sure the stack used by interrupts is aligned. */
+	ulTopOfSystemStack &= ~portBYTE_ALIGNMENT_MASK;
+
+	ulCriticalNesting = 0;
+
+	/* Enable LAPIC Counter.*/
+	portAPIC_LVT_TIMER = portAPIC_TIMER_PERIODIC | portAPIC_TIMER_INT_VECTOR;
+
+	/* Sometimes needed. */
+	portAPIC_TMRDIV = portAPIC_DIV_16;
+
+	/* Should not return from the following function as the scheduler will then
+	be executing the tasks. */
+	vPortStartFirstTask();
+
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	if( ulCriticalNesting == 0 )
+	{
+		#if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
+		{
+			__asm volatile( "cli" );
+		}
+		#else
+		{
+			portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY;
+			configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY );
+		}
+		#endif
+	}
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as the critical section is being
+		exited. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then all interrupt
+		priorities must be re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Critical nesting has reached zero so all interrupt priorities
+			should be unmasked. */
+			#if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
+			{
+				__asm volatile( "sti" );
+			}
+			#else
+			{
+				portAPIC_TASK_PRIORITY = 0;
+			}
+			#endif
+
+			/* If a yield was pended from within the critical section then
+			perform the yield now. */
+			if( ulPortYieldPending != pdFALSE )
+			{
+				ulPortYieldPending = pdFALSE;
+				__asm volatile( portYIELD_INTERRUPT );
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortSetInterruptMask( void )
+{
+volatile uint32_t ulOriginalMask;
+
+	/* Set mask to max syscall priority. */
+	#if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
+	{
+		/* Return whether interrupts were already enabled or not.  Pop adjusts
+		the stack first. */
+		__asm volatile( "pushf		\t\n"
+						"pop %0		\t\n"
+						"cli			"
+						: "=rm" (ulOriginalMask) :: "memory" );
+
+		ulOriginalMask &= portEFLAGS_IF;
+	}
+	#else
+	{
+		/* Return original mask. */
+		ulOriginalMask = portAPIC_TASK_PRIORITY;
+		portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY;
+		configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY );
+	}
+	#endif
+
+	return ulOriginalMask;
+}
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMask( uint32_t ulNewMaskValue )
+{
+	#if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
+	{
+		if( ulNewMaskValue != pdFALSE )
+		{
+			__asm volatile( "sti" );
+		}
+	}
+	#else
+	{
+		portAPIC_TASK_PRIORITY = ulNewMaskValue;
+		configASSERT( portAPIC_TASK_PRIORITY == ulNewMaskValue );
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_FPU == 1 )
+
+	void vPortTaskUsesFPU( void )
+	{
+		/* A task is registering the fact that it needs an FPU context.  Allocate a
+		buffer into which the context can be saved. */
+		pucPortTaskFPUContextBuffer = ( uint8_t * ) pvPortMalloc( portFPU_CONTEXT_SIZE_BYTES );
+		configASSERT( pucPortTaskFPUContextBuffer );
+
+		/* Initialise the floating point registers. */
+		__asm volatile(	"fninit" );
+	}
+
+#endif /* configSUPPORT_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortAPICErrorHandler( void )
+{
+/* Variable to hold the APIC error status for viewing in the debugger. */
+volatile uint32_t ulErrorStatus = 0;
+
+	portAPIC_ERROR_STATUS = 0;
+	ulErrorStatus = portAPIC_ERROR_STATUS;
+	( void ) ulErrorStatus;
+
+	/* Force an assert. */
+	configASSERT( ulCriticalNesting == ~0UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
+
+	void vPortCentralInterruptHandler( uint32_t ulVector )
+	{
+		if( ulVector < portNUM_VECTORS )
+		{
+			if( xInterruptHandlerTable[ ulVector ] != NULL )
+			{
+				( xInterruptHandlerTable[ ulVector ] )();
+			}
+		}
+
+		/* Check for a system stack overflow. */
+		configASSERT( ulSystemStack[ 10 ] == portSTACK_WORD );
+		configASSERT( ulSystemStack[ 12 ] == portSTACK_WORD );
+		configASSERT( ulSystemStack[ 14 ] == portSTACK_WORD );
+	}
+
+#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
+
+	BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber )
+	{
+	BaseType_t xReturn;
+
+		xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber );
+
+		if( xReturn != pdFAIL )
+		{
+			/* Save the handler passed in by the application in the vector number
+			passed in.  The addresses are then called from the central interrupt
+			handler. */
+			xInterruptHandlerTable[ ulVectorNumber ] = pxHandler;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber )
+{
+BaseType_t xReturn;
+
+	xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber );
+
+	if( xReturn != pdFAIL )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Update the IDT to include the application defined handler. */
+			prvSetInterruptGate( ( uint8_t ) ulVectorNumber, ( ISR_Handler_t ) pxHandler, portIDT_FLAGS );
+		}
+		taskEXIT_CRITICAL();
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber )
+{
+BaseType_t xReturn;
+
+	/* Check validity of vector number. */
+	if( ulVectorNumber >= portNUM_VECTORS )
+	{
+		/* Too high. */
+		xReturn = pdFAIL;
+	}
+	else if( ulVectorNumber < portAPIC_MIN_ALLOWABLE_VECTOR )
+	{
+		/* Too low. */
+		xReturn = pdFAIL;
+	}
+	else if( ulVectorNumber == portAPIC_TIMER_INT_VECTOR )
+	{
+		/* In use by FreeRTOS. */
+		xReturn = pdFAIL;
+	}
+	else if( ulVectorNumber == portAPIC_YIELD_INT_VECTOR )
+	{
+		/* In use by FreeRTOS. */
+		xReturn = pdFAIL;
+	}
+	else if( ulVectorNumber == portAPIC_LVT_ERROR_VECTOR )
+	{
+		/* In use by FreeRTOS. */
+		xReturn = pdFAIL;
+	}
+	else if( ulVectorNumber == portAPIC_SPURIOUS_INT_VECTOR )
+	{
+		/* In use by FreeRTOS. */
+		xReturn = pdFAIL;
+	}
+	else if( xInterruptHandlerTable[ ulVectorNumber ] != NULL )
+	{
+		/* Already in use by the application. */
+		xReturn = pdFAIL;
+	}
+	else
+	{
+		xReturn = pdPASS;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vGenerateYieldInterrupt( void )
+{
+	__asm volatile( portYIELD_INTERRUPT );
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/IA32_flat/portASM.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/IA32_flat/portASM.S
new file mode 100644
index 0000000..10394b0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/IA32_flat/portASM.S
@@ -0,0 +1,274 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+.file "portASM.S"
+#include "FreeRTOSConfig.h"
+#include "ISR_Support.h"
+
+	.extern pxCurrentTCB
+	.extern vTaskSwitchContext
+	.extern vPortCentralInterruptHandler
+	.extern xTaskIncrementTick
+	.extern vPortAPICErrorHandler
+	.extern pucPortTaskFPUContextBuffer
+	.extern ulPortYieldPending
+
+	.global vPortStartFirstTask
+	.global vPortCentralInterruptWrapper
+	.global vPortAPICErrorHandlerWrapper
+	.global vPortTimerHandler
+	.global vPortYieldCall
+	.global vPortAPICSpuriousHandler
+
+	.text
+
+/*-----------------------------------------------------------*/
+
+.align 4
+.func vPortYieldCall
+vPortYieldCall:
+	/* Save general purpose registers. */
+	pusha
+
+	.if configSUPPORT_FPU == 1
+
+		/* If the task has a buffer allocated to save the FPU context then save
+		the FPU context now. */
+		movl	pucPortTaskFPUContextBuffer, %eax
+		test	%eax, %eax
+		je		1f
+		fnsave	( %eax )
+		fwait
+
+		1:
+
+		/* Save the address of the FPU context, if any. */
+		push	pucPortTaskFPUContextBuffer
+
+	.endif /* configSUPPORT_FPU */
+
+	/* Find the TCB. */
+	movl 	pxCurrentTCB, %eax
+
+	/* Stack location is first item in the TCB. */
+	movl	%esp, (%eax)
+
+	call vTaskSwitchContext
+
+	/* Find the location of pxCurrentTCB again - a callee saved register could
+	be used in place of eax to prevent this second load, but that then relies
+	on the compiler and other asm code. */
+	movl 	pxCurrentTCB, %eax
+	movl	(%eax), %esp
+
+	.if configSUPPORT_FPU == 1
+
+		/* Restore address of task's FPU context buffer. */
+		pop 	pucPortTaskFPUContextBuffer
+
+		/* If the task has a buffer allocated in which its FPU context is saved,
+		then restore it now. */
+		movl	pucPortTaskFPUContextBuffer, %eax
+		test	%eax, %eax
+		je		1f
+		frstor	( %eax )
+		1:
+	.endif
+
+	popa
+	iret
+
+.endfunc
+/*-----------------------------------------------------------*/
+
+.align 4
+.func vPortStartFirstTask
+vPortStartFirstTask:
+
+	/* Find the TCB. */
+	movl 	pxCurrentTCB, %eax
+
+	/* Stack location is first item in the TCB. */
+	movl	(%eax), %esp
+
+	/* Restore FPU context flag. */
+	.if configSUPPORT_FPU == 1
+
+		pop 	pucPortTaskFPUContextBuffer
+
+	.endif /* configSUPPORT_FPU */
+
+	/* Restore general purpose registers. */
+	popa
+	iret
+.endfunc
+/*-----------------------------------------------------------*/
+
+.align 4
+.func vPortAPICErrorHandlerWrapper
+vPortAPICErrorHandlerWrapper:
+	pusha
+	call	vPortAPICErrorHandler
+	popa
+	/* EOI. */
+	movl	$0x00, (0xFEE000B0)
+	iret
+.endfunc
+/*-----------------------------------------------------------*/
+
+.align 4
+.func vPortTimerHandler
+vPortTimerHandler:
+
+	/* Save general purpose registers. */
+	pusha
+
+	/* Interrupts are not nested, so save the rest of the task context. */
+	.if configSUPPORT_FPU == 1
+
+		/* If the task has a buffer allocated to save the FPU context then save the
+		FPU context now. */
+		movl	pucPortTaskFPUContextBuffer, %eax
+		test	%eax, %eax
+		je		1f
+		fnsave	( %eax ) /* Save FLOP context into ucTempFPUBuffer array. */
+		fwait
+
+		1:
+		/* Save the address of the FPU context, if any. */
+		push	pucPortTaskFPUContextBuffer
+
+	.endif /* configSUPPORT_FPU */
+
+	/* Find the TCB. */
+	movl 	pxCurrentTCB, %eax
+
+	/* Stack location is first item in the TCB. */
+	movl	%esp, (%eax)
+
+	/* Switch stacks. */
+	movl 	ulTopOfSystemStack, %esp
+	movl	%esp, %ebp
+
+	/* Increment nesting count. */
+	add 	$1, ulInterruptNesting
+
+	call 	xTaskIncrementTick
+
+	sti
+
+	/* Is a switch to another task required? */
+	test	%eax, %eax
+	je		_skip_context_switch
+	cli
+	call	vTaskSwitchContext
+
+_skip_context_switch:
+	cli
+
+	/* Decrement the variable used to determine if a switch to a system
+	stack is necessary. */
+	sub		$1, ulInterruptNesting
+
+	/* Stack location is first item in the TCB. */
+	movl 	pxCurrentTCB, %eax
+	movl	(%eax), %esp
+
+	.if configSUPPORT_FPU == 1
+
+		/* Restore address of task's FPU context buffer. */
+		pop 	pucPortTaskFPUContextBuffer
+
+		/* If the task has a buffer allocated in which its FPU context is saved,
+		then restore it now. */
+		movl	pucPortTaskFPUContextBuffer, %eax
+		test	%eax, %eax
+		je		1f
+		frstor	( %eax )
+		1:
+	.endif
+
+	popa
+
+	/* EOI. */
+	movl	$0x00, (0xFEE000B0)
+	iret
+
+.endfunc
+/*-----------------------------------------------------------*/
+
+.if configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1
+
+	.align 4
+	.func vPortCentralInterruptWrapper
+	vPortCentralInterruptWrapper:
+
+		portFREERTOS_INTERRUPT_ENTRY
+
+		movl $0xFEE00170, %eax 			/* Highest In Service Register (ISR) long word. */
+		movl $8, %ecx					/* Loop counter. */
+
+	next_isr_long_word:
+		test %ecx, %ecx					/* Loop counter reached 0? */
+		je wrapper_epilogue				/* Looked at all ISR registers without finding a bit set. */
+		sub $1, %ecx					/* Sub 1 from loop counter. */
+		movl (%eax), %ebx				/* Load next ISR long word. */
+		sub $0x10, %eax					/* Point to next ISR long word in case no bits are set in the current long word. */
+		test %ebx, %ebx					/* Are there any bits set? */
+		je next_isr_long_word			/* Look at next ISR long word if no bits were set. */
+		sti
+		bsr %ebx, %ebx					/* A bit was set, which one? */
+		movl $32, %eax					/* Destination operand for following multiplication. */
+		mul %ecx						/* Calculate base vector for current register, 32 vectors per register. */
+		add %ebx, %eax					/* Add bit offset into register to get final vector number. */
+		push %eax						/* Vector number is function parameter. */
+		call vPortCentralInterruptHandler
+		pop %eax						/* Remove parameter. */
+
+	wrapper_epilogue:
+		portFREERTOS_INTERRUPT_EXIT
+
+	.endfunc
+
+.endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
+/*-----------------------------------------------------------*/
+
+.align 4
+.func vPortAPISpuriousHandler
+vPortAPICSpuriousHandler:
+	iret
+
+.endfunc
+
+.end
+
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/IA32_flat/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/IA32_flat/portmacro.h
new file mode 100644
index 0000000..eabeeee
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/IA32_flat/portmacro.h
@@ -0,0 +1,291 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+	extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+typedef uint32_t TickType_t;
+#define portMAX_DELAY ( ( TickType_t ) 0xffffffffUL )
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			32
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* The interrupt priority (for vectors 16 to 255) is determined using vector/16.
+The quotient is rounded to the nearest integer with 1 being the lowest priority
+and 15 is the highest.  Therefore the following two interrupts are at the lowest
+priority.  *NOTE 1* If the yield vector is changed then it must also be changed
+in the portYIELD_INTERRUPT definition immediately below. */
+#define portAPIC_TIMER_INT_VECTOR 		( 0x21 )
+#define portAPIC_YIELD_INT_VECTOR 		( 0x20 )
+
+/* Build yield interrupt instruction. */
+#define portYIELD_INTERRUPT "int $0x20"
+
+/* APIC register addresses. */
+#define portAPIC_EOI					( *( ( volatile uint32_t * ) 0xFEE000B0UL ) )
+
+/* APIC bit definitions. */
+#define portAPIC_ENABLE_BIT				( 1UL << 8UL )
+#define portAPIC_TIMER_PERIODIC 		( 1UL << 17UL )
+#define portAPIC_DISABLE 				( 1UL << 16UL )
+#define portAPIC_NMI 					( 4 << 8)
+#define portAPIC_DIV_16 				( 0x03 )
+
+/* Define local API register addresses. */
+#define portAPIC_ID_REGISTER			( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x20UL  ) ) )
+#define portAPIC_SPURIOUS_INT			( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xF0UL  ) ) )
+#define portAPIC_LVT_TIMER				( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x320UL ) ) )
+#define portAPIC_TIMER_INITIAL_COUNT	( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x380UL ) ) )
+#define portAPIC_TIMER_CURRENT_COUNT	( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x390UL ) ) )
+#define portAPIC_TASK_PRIORITY			( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x80UL  ) ) )
+#define portAPIC_LVT_ERROR				( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x370UL ) ) )
+#define portAPIC_ERROR_STATUS			( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x280UL ) ) )
+#define portAPIC_LDR	 				( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xD0UL  ) ) )
+#define portAPIC_TMRDIV 				( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x3E0UL ) ) )
+#define portAPIC_LVT_PERF 				( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x340UL ) ) )
+#define portAPIC_LVT_LINT0 				( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x350UL ) ) )
+#define portAPIC_LVT_LINT1 				( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x360UL ) ) )
+
+/* Don't yield if inside a critical section - instead hold the yield pending
+so it is performed when the critical section is exited. */
+#define portYIELD() 								\
+{													\
+extern volatile uint32_t ulCriticalNesting;			\
+extern volatile uint32_t ulPortYieldPending;		\
+	if( ulCriticalNesting != 0 )					\
+	{												\
+		ulPortYieldPending = pdTRUE;				\
+	}												\
+	else											\
+	{												\
+		__asm volatile( portYIELD_INTERRUPT );		\
+	}												\
+}
+
+/* Called at the end of an ISR that can cause a context switch - pend a yield if
+xSwithcRequired is not false. */
+#define portEND_SWITCHING_ISR( xSwitchRequired )	\
+{													\
+extern volatile uint32_t ulPortYieldPending;		\
+	if( xSwitchRequired != pdFALSE )				\
+	{												\
+		ulPortYieldPending = 1; 				 	\
+	}												\
+}
+
+/* Same as portEND_SWITCHING_ISR() - take your pick which name to use. */
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+
+/*-----------------------------------------------------------
+ * Critical section control
+ *----------------------------------------------------------*/
+
+/* Critical sections for use in interrupts. */
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask( x )
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+
+/* These macros do not globally disable/enable interrupts.  They do mask off
+interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+#define portDISABLE_INTERRUPTS()	__asm volatile( "cli" )
+#define portENABLE_INTERRUPTS()		__asm volatile( "sti" )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
+
+/* Architecture specific optimisations. */
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )	\
+		__asm volatile(	"bsr %1, %0\n\t" 									\
+						:"=r"(uxTopPriority) : "rm"(uxReadyPriorities) : "cc" )
+
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#define portNOP() __asm volatile( "NOP" )
+
+/*-----------------------------------------------------------
+ * Misc
+ *----------------------------------------------------------*/
+
+#define portNUM_VECTORS		256
+#define portMAX_PRIORITY	15
+typedef void ( *ISR_Handler_t ) ( void );
+
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+before any floating point instructions are executed. */
+#ifndef configSUPPORT_FPU
+	#define configSUPPORT_FPU 0
+#endif
+
+#if configSUPPORT_FPU == 1
+	void vPortTaskUsesFPU( void );
+	#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+#endif
+
+/* See the comments under the configUSE_COMMON_INTERRUPT_ENTRY_POINT definition
+below. */
+BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber );
+BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber );
+
+#ifndef configAPIC_BASE
+	/* configAPIC_BASE_ADDRESS sets the base address of the local APIC.  It can
+	be overridden in FreeRTOSConfig.h should it not be constant. */
+	#define configAPIC_BASE	0xFEE00000UL
+#endif
+
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	/* The FreeRTOS scheduling algorithm selects the task that will enter the
+	Running state.  configUSE_PORT_OPTIMISED_TASK_SELECTION is used to set how
+	that is done.
+
+	If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 0 then the task to
+	enter the Running state is selected using a portable algorithm written in
+	C.  This is the slowest method, but the algorithm does not restrict the
+	maximum number of unique RTOS task priorities that are available.
+
+	If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 1 then the task to
+	enter the Running state is selected using a single assembly instruction.
+	This is the fastest method, but restricts the maximum number of unique RTOS
+	task priorities to 32 (the same task priority can be assigned to any number
+	of RTOS	tasks). */
+	#warning configUSE_PORT_OPTIMISED_TASK_SELECTION was not defined in FreeRTOSConfig.h and has been defaulted to 1
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#ifndef configUSE_COMMON_INTERRUPT_ENTRY_POINT
+	/* There are two ways of implementing interrupt handlers:
+
+		1) As standard C functions -
+
+		This method can only be used if configUSE_COMMON_INTERRUPT_ENTRY_POINT
+		is set to 1.  The C function is installed using
+		xPortRegisterCInterruptHandler().
+
+		This is the simplest of the two methods but incurs a slightly longer
+		interrupt entry time.
+
+		2) By using an assembly stub that wraps the handler in the FreeRTOS
+		   portFREERTOS_INTERRUPT_ENTRY and portFREERTOS_INTERRUPT_EXIT macros.
+
+		This method can always be used.  It is slightly more complex than
+		method 1 but benefits from a faster interrupt entry time. */
+	#warning configUSE_COMMON_INTERRUPT_ENTRY_POINT was not defined in FreeRTOSConfig.h and has been defaulted to 1.
+	#define configUSE_COMMON_INTERRUPT_ENTRY_POINT	1
+#endif
+
+#ifndef configISR_STACK_SIZE
+	/* Interrupt entry code will switch the stack in use to a dedicated system
+	stack.
+
+	configISR_STACK_SIZE defines the number of 32-bit values that can be stored
+	on the system stack, and must be large enough to hold a potentially nested
+	interrupt stack frame. */
+
+	#error configISR_STACK_SIZE was not defined in FreeRTOSConfig.h.
+#endif
+
+#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
+	/* Interrupt safe FreeRTOS functions (those that end in "FromISR" must not
+	be called from an interrupt that has a priority above that set by
+	configMAX_API_CALL_INTERRUPT_PRIORITY.  */
+	#warning configMAX_API_CALL_INTERRUPT_PRIORITY was not defined in FreeRTOSConfig.h and has been defaulted to 10
+	#define configMAX_API_CALL_INTERRUPT_PRIORITY 10
+#endif
+
+#ifndef configSUPPORT_FPU
+	#warning configSUPPORT_FPU was not defined in FreeRTOSConfig.h and has been defaulted to 0
+	#define configSUPPORT_FPU 0
+#endif
+
+/* The value written to the task priority register to raise the interrupt mask
+to the maximum from which FreeRTOS API calls can be made. */
+#define portAPIC_PRIORITY_SHIFT		( 4UL )
+#define portAPIC_MAX_SUB_PRIORITY	( 0x0fUL )
+#define portMAX_API_CALL_PRIORITY		( ( configMAX_API_CALL_INTERRUPT_PRIORITY << portAPIC_PRIORITY_SHIFT ) | portAPIC_MAX_SUB_PRIORITY )
+
+/* Asserts if interrupt safe FreeRTOS functions are called from a priority
+above the max system call interrupt priority. */
+#define portAPIC_PROCESSOR_PRIORITY	( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xA0UL  ) ) )
+#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( portAPIC_PROCESSOR_PRIORITY ) <= ( portMAX_API_CALL_PRIORITY ) )
+
+#ifdef __cplusplus
+	} /* extern C */
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MCF5235/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MCF5235/port.c
new file mode 100644
index 0000000..092ea51
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MCF5235/port.c
@@ -0,0 +1,285 @@
+/*
+    FreeRTOS V4.1.1 - Copyright (C) 2003-2006 Richard Barry.
+    MCF5235 Port - Copyright (C) 2006 Christian Walter.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License** as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    FreeRTOS is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with FreeRTOS; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+    A special exception to the GPL can be applied should you wish to distribute
+    a combined work that includes FreeRTOS, without being obliged to provide
+    the source code for any proprietary components.  See the licensing section
+    of http://www.FreeRTOS.org for full details of how and when the exception
+    can be applied.
+
+    ***************************************************************************
+    ***************************************************************************
+    *                                                                         *
+    * Get the FreeRTOS eBook!  See http://www.FreeRTOS.org/Documentation      *
+	*                                                                         *
+	* This is a concise, step by step, 'hands on' guide that describes both   *
+	* general multitasking concepts and FreeRTOS specifics. It presents and   *
+	* explains numerous examples that are written using the FreeRTOS API.     *
+	* Full source code for all the examples is provided in an accompanying    *
+	* .zip file.                                                              *
+    *                                                                         *
+    ***************************************************************************
+    ***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the
+	online documentation.
+
+	http://www.FreeRTOS.org - Documentation, latest information, license and 
+	contact details.
+
+	http://www.SafeRTOS.com - A version that is certified for use in safety 
+	critical systems.
+
+	http://www.OpenRTOS.com - Commercial support, development, porting, 
+	licensing and training services.
+*/
+
+#include 
+
+#include "FreeRTOS.h"
+#include "FreeRTOSConfig.h"
+#include "task.h"
+
+/* ------------------------ Types ----------------------------------------- */
+typedef volatile uint32_t vuint32;
+typedef volatile uint16_t vuint16;
+typedef volatile uint8_t vuint8;
+
+/* ------------------------ Defines --------------------------------------- */
+#define portVECTOR_TABLE                __RAMVEC
+#define portVECTOR_SYSCALL              ( 32 + portTRAP_YIELD )
+#define portVECTOR_TIMER                ( 64 + 36 )
+
+#define MCF_PIT_PRESCALER               512UL
+#define MCF_PIT_TIMER_TICKS             ( FSYS_2 / MCF_PIT_PRESCALER )
+#define MCF_PIT_MODULUS_REGISTER(freq)  ( MCF_PIT_TIMER_TICKS / ( freq ) - 1UL)
+
+#define MCF_PIT_PMR0                    ( *( vuint16 * )( void * )( &__IPSBAR[ 0x150002 ] ) )
+#define MCF_PIT_PCSR0                   ( *( vuint16 * )( void * )( &__IPSBAR[ 0x150000 ] ) )
+#define MCF_PIT_PCSR_PRE(x)             ( ( ( x ) & 0x000F ) << 8 )
+#define MCF_PIT_PCSR_EN                 ( 0x0001 )
+#define MCF_PIT_PCSR_RLD                ( 0x0002 )
+#define MCF_PIT_PCSR_PIF                ( 0x0004 )
+#define MCF_PIT_PCSR_PIE                ( 0x0008 )
+#define MCF_PIT_PCSR_OVW                ( 0x0010 )
+#define MCF_INTC0_ICR36                 ( *( vuint8 * )( void * )( &__IPSBAR[ 0x000C64 ] ) )
+#define MCF_INTC0_IMRH                  ( *( vuint32 * )( void * )( &__IPSBAR[ 0x000C08 ] ) )
+#define MCF_INTC0_IMRH_INT_MASK36       ( 0x00000010 )
+#define MCF_INTC0_IMRH_MASKALL          ( 0x00000001 )
+#define MCF_INTC0_ICRn_IP(x)            ( ( ( x ) & 0x07 ) << 0 )
+#define MCF_INTC0_ICRn_IL(x)            ( ( ( x ) & 0x07 ) << 3 )
+
+#define portNO_CRITICAL_NESTING         ( ( uint32_t ) 0 )
+#define portINITIAL_CRITICAL_NESTING    ( ( uint32_t ) 10 )
+
+/* ------------------------ Static variables ------------------------------ */
+volatile uint32_t              ulCriticalNesting = portINITIAL_CRITICAL_NESTING;
+
+/* ------------------------ Static functions ------------------------------ */
+#if configUSE_PREEMPTION == 0
+static void prvPortPreemptiveTick ( void ) __attribute__ ((interrupt_handler));
+#else
+static void prvPortPreemptiveTick ( void );
+#endif
+
+/* ------------------------ Start implementation -------------------------- */
+
+StackType_t *
+pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode,
+                       void *pvParameters )
+{
+    /* Place the parameter on the stack in the expected location. */
+    *pxTopOfStack = ( StackType_t ) pvParameters;
+    pxTopOfStack--;
+
+    /* Place dummy return address on stack. Tasks should never terminate so
+     * we can set this to anything. */
+    *pxTopOfStack = ( StackType_t ) 0;
+    pxTopOfStack--;
+
+    /* Create a Motorola Coldfire exception stack frame. First comes the return
+     * address. */
+    *pxTopOfStack = ( StackType_t ) pxCode;
+    pxTopOfStack--;
+
+    /* Format, fault-status, vector number for exception stack frame. Task
+     * run in supervisor mode. */
+    *pxTopOfStack = 0x40002000UL | ( portVECTOR_SYSCALL + 32 ) << 18;
+    pxTopOfStack--;
+
+    /* Set the initial critical section nesting counter to zero. This value
+     * is used to restore the value of ulCriticalNesting. */
+    *pxTopOfStack = 0;
+    *pxTopOfStack--;
+
+    *pxTopOfStack = ( StackType_t ) 0xA6;    /* A6 / FP */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xA5;    /* A5 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xA4;    /* A4 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xA3;    /* A3 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xA2;    /* A2 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xA1;    /* A1 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xA0;    /* A0 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xD7;    /* D7 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xD6;    /* D6 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xD5;    /* D5 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xD4;    /* D4 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xD3;    /* D3 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xD2;    /* D2 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xD1;    /* D1 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xD0;    /* D0 */
+
+    return pxTopOfStack;
+}
+
+/*
+ * Called by portYIELD() or taskYIELD() to manually force a context switch.
+ */
+static void
+prvPortYield( void )
+{
+    asm volatile ( "move.w  #0x2700, %sr\n\t" );
+#if _GCC_USES_FP == 1
+    asm volatile ( "unlk %fp\n\t" );
+#endif
+     /* Perform the context switch.  First save the context of the current task. */
+    portSAVE_CONTEXT(  );
+
+    /* Find the highest priority task that is ready to run. */
+    vTaskSwitchContext(  );
+
+    /* Restore the context of the new task. */
+    portRESTORE_CONTEXT(  );
+}
+
+#if configUSE_PREEMPTION == 0
+/*
+ * The ISR used for the scheduler tick depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+static void
+prvPortPreemptiveTick ( void )
+{
+    /* The cooperative scheduler requires a normal IRQ service routine to
+     * simply increment the system tick.
+     */
+
+    xTaskIncrementTick();
+    MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF;
+}
+
+#else
+
+static void
+prvPortPreemptiveTick( void )
+{
+    asm volatile ( "move.w  #0x2700, %sr\n\t" );
+#if _GCC_USES_FP == 1
+    asm volatile ( "unlk %fp\n\t" );
+#endif
+    portSAVE_CONTEXT(  );
+    MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF;
+    if( xTaskIncrementTick() != pdFALSE )
+	{
+		vTaskSwitchContext(  );
+	}
+    portRESTORE_CONTEXT(  );
+}
+#endif
+
+void
+vPortEnterCritical()
+{
+    /* FIXME: We should store the old IPL here - How are we supposed to do
+     * this.
+     */
+    ( void )portSET_IPL( portIPL_MAX );
+
+    /* Now interrupts are disabled ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
+    ulCriticalNesting++;
+}
+
+void
+vPortExitCritical()
+{
+    if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+    {
+        /* Decrement the nesting count as we are leaving a critical section. */
+        ulCriticalNesting--;
+
+        /* If the nesting level has reached zero then interrupts should be
+        re-enabled. */
+        if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+        {
+            ( void )portSET_IPL( 0 );
+        }
+    }
+}
+
+BaseType_t
+xPortStartScheduler( void )
+{
+    extern void     ( *portVECTOR_TABLE[  ] ) (  );
+
+    /* Add entry in vector table for yield system call. */
+    portVECTOR_TABLE[ portVECTOR_SYSCALL ] = prvPortYield;
+    /* Add entry in vector table for periodic timer. */
+    portVECTOR_TABLE[ portVECTOR_TIMER ] = prvPortPreemptiveTick;
+
+    /* Configure the timer for the system clock. */
+    if ( configTICK_RATE_HZ > 0)
+    {
+        /* Configure prescaler */
+        MCF_PIT_PCSR0 = MCF_PIT_PCSR_PRE( 0x9 ) | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_OVW;
+        /* Initialize the periodic timer interrupt. */
+        MCF_PIT_PMR0 = MCF_PIT_MODULUS_REGISTER( configTICK_RATE_HZ );
+        /* Configure interrupt priority and level and unmask interrupt. */
+        MCF_INTC0_ICR36 = MCF_INTC0_ICRn_IL( 0x1 ) | MCF_INTC0_ICRn_IP( 0x1 );
+        MCF_INTC0_IMRH &= ~( MCF_INTC0_IMRH_INT_MASK36 | MCF_INTC0_IMRH_MASKALL );
+        /* Enable interrupts */
+        MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_EN | MCF_PIT_PCSR_PIF;
+    }
+
+    /* Restore the context of the first task that is going to run. */
+    portRESTORE_CONTEXT(  );
+
+    /* Should not get here. */
+    return pdTRUE;
+}
+
+void
+vPortEndScheduler( void )
+{
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MCF5235/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MCF5235/portmacro.h
new file mode 100644
index 0000000..ea2598b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MCF5235/portmacro.h
@@ -0,0 +1,182 @@
+/*
+    FreeRTOS V4.1.1 - Copyright (C) 2003-2006 Richard Barry.
+    MCF5235 Port - Copyright (C) 2006 Christian Walter.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License** as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    FreeRTOS is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with FreeRTOS; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+    A special exception to the GPL can be applied should you wish to distribute
+    a combined work that includes FreeRTOS, without being obliged to provide
+    the source code for any proprietary components.  See the licensing section
+    of http://www.FreeRTOS.org for full details of how and when the exception
+    can be applied.
+
+    ***************************************************************************
+    ***************************************************************************
+    *                                                                         *
+    * Get the FreeRTOS eBook!  See http://www.FreeRTOS.org/Documentation      *
+	*                                                                         *
+	* This is a concise, step by step, 'hands on' guide that describes both   *
+	* general multitasking concepts and FreeRTOS specifics. It presents and   *
+	* explains numerous examples that are written using the FreeRTOS API.     *
+	* Full source code for all the examples is provided in an accompanying    *
+	* .zip file.                                                              *
+    *                                                                         *
+    ***************************************************************************
+    ***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the
+	online documentation.
+
+	http://www.FreeRTOS.org - Documentation, latest information, license and
+	contact details.
+
+	http://www.SafeRTOS.com - A version that is certified for use in safety
+	critical systems.
+
+	http://www.OpenRTOS.com - Commercial support, development, porting,
+	licensing and training services.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ------------------------ Data types for Coldfire ----------------------- */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  unsigned int
+#define portBASE_TYPE   int
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+
+/* ------------------------ Architecture specifics ------------------------ */
+#define portSTACK_GROWTH                ( -1 )
+#define portTICK_PERIOD_MS                ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT              4
+
+#define portTRAP_YIELD                  0   /* Trap 0 */
+#define portIPL_MAX                     7   /* Only NMI interrupt 7 allowed. */
+
+/* ------------------------ FreeRTOS macros for port ---------------------- */
+
+/*
+ * This function must be called when the current state of the active task
+ * should be stored. It must be called immediately after exception
+ * processing from the CPU, i.e. there exists a Coldfire exception frame at
+ * the current position in the stack. The function reserves space on
+ * the stack for the CPU registers and other task dependent values (e.g
+ * ulCriticalNesting) and updates the top of the stack in the TCB.
+ */
+#define portSAVE_CONTEXT()                                                   \
+    asm volatile ( /* reserve space for task state. */                       \
+                   "lea.l   (-64, %sp), %sp\n\t"                             \
+                   /* push data register %d0-%d7/%a0-%a6 on stack. */        \
+                   "movem.l %d0-%d7/%a0-%a6, (%sp)\n\t"                      \
+                   /* push ulCriticalNesting counter on stack. */            \
+                   "lea.l  (60, %sp), %a0\n\t"                               \
+                   "move.l  ulCriticalNesting, (%a0)\n\t"                    \
+                   /* set the new top of the stack in the TCB. */            \
+                   "move.l  pxCurrentTCB, %a0\n\t"                           \
+                   "move.l  %sp, (%a0)");
+
+/*.
+ * This function restores the current active and continues its execution.
+ * It loads the current TCB and restores the processor registers, the
+ * task dependent values (e.g ulCriticalNesting). Finally execution
+ * is continued by executing an rte instruction.
+ */
+#define portRESTORE_CONTEXT()                                                \
+    asm volatile ( "move.l  pxCurrentTCB, %sp\n\t"                           \
+                   "move.l  (%sp), %sp\n\t"                                  \
+                   /* stack pointer now points to the saved registers. */    \
+                   "movem.l (%sp), %d0-%d7/%a0-%a6\n\t"                      \
+                   /* restore ulCriticalNesting counter from stack. */       \
+                   "lea.l   (%sp, 60), %sp\n\t"                              \
+                   "move.l  (%sp)+, ulCriticalNesting\n\t"                   \
+                   /* stack pointer now points to exception frame. */        \
+                   "rte\n\t" );
+
+#define portENTER_CRITICAL()                                                 \
+    vPortEnterCritical();
+
+#define portEXIT_CRITICAL()                                                  \
+    vPortExitCritical();
+
+#define portSET_IPL( xIPL )                                                  \
+    asm_set_ipl( xIPL )
+
+#define portDISABLE_INTERRUPTS() \
+    do { ( void )portSET_IPL( portIPL_MAX ); } while( 0 )
+#define portENABLE_INTERRUPTS() \
+    do { ( void )portSET_IPL( 0 ); } while( 0 )
+
+#define portYIELD()                                                          \
+    asm volatile ( " trap   %0\n\t" : : "i"(portTRAP_YIELD) )
+
+#define portNOP()                                                            \
+    asm volatile ( "nop\n\t" )
+
+#define portENTER_SWITCHING_ISR()                                            \
+    asm volatile ( "move.w  #0x2700, %sr" );                                 \
+    /* Save the context of the interrupted task. */                          \
+    portSAVE_CONTEXT(  );                                                    \
+    {
+
+#define portEXIT_SWITCHING_ISR( SwitchRequired )                             \
+        /* If a switch is required we call vTaskSwitchContext(). */          \
+        if( SwitchRequired )                                                 \
+        {                                                                    \
+            vTaskSwitchContext(  );                                          \
+        }                                                                    \
+    }                                                                        \
+    portRESTORE_CONTEXT(  );
+
+/* ------------------------ Function prototypes --------------------------- */
+void vPortEnterCritical( void );
+void vPortExitCritical( void );
+int asm_set_ipl( uint32_t int uiNewIPL );
+
+/* ------------------------ Compiler specifics ---------------------------- */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )                   \
+    void vFunction( void *pvParameters )
+
+#define portTASK_FUNCTION( vFunction, pvParameters )                         \
+    void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MSP430F449/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MSP430F449/port.c
new file mode 100644
index 0000000..d84bf9f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MSP430F449/port.c
@@ -0,0 +1,328 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+	Changes from V2.5.2
+		
+	+ usCriticalNesting now has a volatile qualifier.
+*/
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MSP430 port.
+ *----------------------------------------------------------*/
+
+/* Constants required for hardware setup.  The tick ISR runs off the ACLK, 
+not the MCLK. */
+#define portACLK_FREQUENCY_HZ			( ( TickType_t ) 32768 )
+#define portINITIAL_CRITICAL_NESTING	( ( uint16_t ) 10 )
+#define portFLAGS_INT_ENABLED	( ( StackType_t ) 0x08 )
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/* Most ports implement critical sections by placing the interrupt flags on
+the stack before disabling interrupts.  Exiting the critical section is then
+simply a case of popping the flags from the stack.  As mspgcc does not use
+a frame pointer this cannot be done as modifying the stack will clobber all
+the stack variables.  Instead each task maintains a count of the critical
+section nesting depth.  Each time a critical section is entered the count is
+incremented.  Each time a critical section is left the count is decremented -
+with interrupts only being re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as this will cause problems during the startup
+sequence. */
+volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
+/*-----------------------------------------------------------*/
+
+/* 
+ * Macro to save a task context to the task stack.  This simply pushes all the 
+ * general purpose msp430 registers onto the stack, followed by the 
+ * usCriticalNesting value used by the task.  Finally the resultant stack 
+ * pointer value is saved into the task control block so it can be retrieved 
+ * the next time the task executes.
+ */
+#define portSAVE_CONTEXT()									\
+	asm volatile (	"push	r4						\n\t"	\
+					"push	r5						\n\t"	\
+					"push	r6						\n\t"	\
+					"push	r7						\n\t"	\
+					"push	r8						\n\t"	\
+					"push	r9						\n\t"	\
+					"push	r10						\n\t"	\
+					"push	r11						\n\t"	\
+					"push	r12						\n\t"	\
+					"push	r13						\n\t"	\
+					"push	r14						\n\t"	\
+					"push	r15						\n\t"	\
+					"mov.w	usCriticalNesting, r14	\n\t"	\
+					"push	r14						\n\t"	\
+					"mov.w	pxCurrentTCB, r12		\n\t"	\
+					"mov.w	r1, @r12				\n\t"	\
+				);
+
+/* 
+ * Macro to restore a task context from the task stack.  This is effectively
+ * the reverse of portSAVE_CONTEXT().  First the stack pointer value is
+ * loaded from the task control block.  Next the value for usCriticalNesting
+ * used by the task is retrieved from the stack - followed by the value of all
+ * the general purpose msp430 registers.
+ *
+ * The bic instruction ensures there are no low power bits set in the status
+ * register that is about to be popped from the stack.
+ */
+#define portRESTORE_CONTEXT()								\
+	asm volatile (	"mov.w	pxCurrentTCB, r12		\n\t"	\
+					"mov.w	@r12, r1				\n\t"	\
+					"pop	r15						\n\t"	\
+					"mov.w	r15, usCriticalNesting	\n\t"	\
+					"pop	r15						\n\t"	\
+					"pop	r14						\n\t"	\
+					"pop	r13						\n\t"	\
+					"pop	r12						\n\t"	\
+					"pop	r11						\n\t"	\
+					"pop	r10						\n\t"	\
+					"pop	r9						\n\t"	\
+					"pop	r8						\n\t"	\
+					"pop	r7						\n\t"	\
+					"pop	r6						\n\t"	\
+					"pop	r5						\n\t"	\
+					"pop	r4						\n\t"	\
+					"bic	#(0xf0),0(r1)			\n\t"	\
+					"reti							\n\t"	\
+				);
+/*-----------------------------------------------------------*/
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
+ * could have alternatively used the watchdog timer or timer 1.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been called.
+ * 
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* 
+		Place a few bytes of known values on the bottom of the stack. 
+		This is just useful for debugging and can be included if required.
+
+		*pxTopOfStack = ( StackType_t ) 0x1111;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x2222;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x3333;
+		pxTopOfStack--; 
+	*/
+
+	/* The msp430 automatically pushes the PC then SR onto the stack before 
+	executing an ISR.  We want the stack to look just as if this has happened
+	so place a pointer to the start of the task on the stack first - followed
+	by the flags we want the task to use when it starts up. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+	*pxTopOfStack = portFLAGS_INT_ENABLED;
+	pxTopOfStack--;
+
+	/* Next the general purpose registers. */
+	*pxTopOfStack = ( StackType_t ) 0x4444;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x5555;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x6666;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x7777;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x8888;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x9999;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xaaaa;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xbbbb;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xcccc;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xdddd;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xeeee;
+	pxTopOfStack--;
+
+	/* When the task starts is will expect to find the function parameter in
+	R15. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;
+	pxTopOfStack--;
+
+	/* The code generated by the mspgcc compiler does not maintain separate
+	stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
+	use the stack as per other ports.  Instead a variable is used to keep
+	track of the critical section nesting.  This variable has to be stored
+	as part of the task context and is initially set to zero. */
+	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;	
+
+	/* Return a pointer to the top of the stack we have generated so this can
+	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Setup the hardware to generate the tick.  Interrupts are disabled when
+	this function is called. */
+	prvSetupTimerInterrupt();
+
+	/* Restore the context of the first task that is going to run. */
+	portRESTORE_CONTEXT();
+
+	/* Should not get here as the tasks are now running! */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the MSP430 port will get stopped.  If required simply
+	disable the tick interrupt here. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.  
+ *
+ * The first thing we do is save the registers so we can use a naked attribute.
+ */
+void vPortYield( void ) __attribute__ ( ( naked ) );
+void vPortYield( void )
+{
+	/* We want the stack of the task being saved to look exactly as if the task
+	was saved during a pre-emptive RTOS tick ISR.  Before calling an ISR the 
+	msp430 places the status register onto the stack.  As this is a function 
+	call and not an ISR we have to do this manually. */
+	asm volatile ( "push	r2" );
+	_DINT();
+
+	/* Save the context of the current task. */
+	portSAVE_CONTEXT();
+
+	/* Switch to the highest priority task that is ready to run. */
+	vTaskSwitchContext();
+
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.  This uses timer 0
+ * but could alternatively use the watchdog timer or timer 1. 
+ */
+static void prvSetupTimerInterrupt( void )
+{
+	/* Ensure the timer is stopped. */
+	TACTL = 0;
+
+	/* Run the timer of the ACLK. */
+	TACTL = TASSEL_1;
+
+	/* Clear everything to start with. */
+	TACTL |= TACLR;
+
+	/* Set the compare match value according to the tick rate we want. */
+	TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;
+
+	/* Enable the interrupts. */
+	TACCTL0 = CCIE;
+
+	/* Start up clean. */
+	TACTL |= TACLR;
+
+	/* Up mode. */
+	TACTL |= MC_1;
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * The interrupt service routine used depends on whether the pre-emptive
+ * scheduler is being used or not.
+ */
+
+#if configUSE_PREEMPTION == 1
+
+	/*
+	 * Tick ISR for preemptive scheduler.  We can use a naked attribute as
+	 * the context is saved at the start of vPortYieldFromTick().  The tick
+	 * count is incremented after the context is saved.
+	 */
+	interrupt (TIMERA0_VECTOR) prvTickISR( void ) __attribute__ ( ( naked ) );
+	interrupt (TIMERA0_VECTOR) prvTickISR( void )
+	{
+		/* Save the context of the interrupted task. */
+		portSAVE_CONTEXT();
+
+		/* Increment the tick count then switch to the highest priority task
+		that is ready to run. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			vTaskSwitchContext();
+		}
+
+		/* Restore the context of the new task. */
+		portRESTORE_CONTEXT();
+	}
+
+#else
+
+	/*
+	 * Tick ISR for the cooperative scheduler.  All this does is increment the
+	 * tick count.  We don't need to switch context, this can only be done by
+	 * manual calls to taskYIELD();
+	 */
+	interrupt (TIMERA0_VECTOR) prvTickISR( void );
+	interrupt (TIMERA0_VECTOR) prvTickISR( void )
+	{
+		xTaskIncrementTick();
+	}
+#endif
+
+
+	
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MSP430F449/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MSP430F449/portmacro.h
new file mode 100644
index 0000000..9b5d224
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MSP430F449/portmacro.h
@@ -0,0 +1,127 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	uint16_t
+#define portBASE_TYPE	short
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS()	asm volatile ( "DINT" ); asm volatile ( "NOP" )
+#define portENABLE_INTERRUPTS()		asm volatile ( "EINT" ); asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Critical section control macros. */
+#define portNO_CRITICAL_SECTION_NESTING		( ( uint16_t ) 0 )
+
+#define portENTER_CRITICAL()													\
+{																				\
+extern volatile uint16_t usCriticalNesting;							\
+																				\
+	portDISABLE_INTERRUPTS();													\
+																				\
+	/* Now interrupts are disabled ulCriticalNesting can be accessed */			\
+	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
+	/* times portENTER_CRITICAL() has been called. */							\
+	usCriticalNesting++;														\
+}
+
+#define portEXIT_CRITICAL()														\
+{																				\
+extern volatile uint16_t usCriticalNesting;							\
+																				\
+	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
+	{																			\
+		/* Decrement the nesting count as we are leaving a critical section. */	\
+		usCriticalNesting--;													\
+																				\
+		/* If the nesting level has reached zero then interrupts should be */	\
+		/* re-enabled. */														\
+		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
+		{																		\
+			portENABLE_INTERRUPTS();											\
+		}																		\
+	}																			\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+extern void vPortYield( void ) __attribute__ ( ( naked ) );
+#define portYIELD()			vPortYield()
+#define portNOP()			asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Hardwware specifics. */
+#define portBYTE_ALIGNMENT			2
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlaze/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlaze/port.c
new file mode 100644
index 0000000..632bbd3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlaze/port.c
@@ -0,0 +1,333 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MicroBlaze port.
+ *----------------------------------------------------------*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include 
+
+/* Hardware includes. */
+#include 
+#include 
+#include 
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+	#error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port.
+#endif
+
+/* Tasks are started with interrupts enabled. */
+#define portINITIAL_MSR_STATE		( ( StackType_t ) 0x02 )
+
+/* Tasks are started with a critical section nesting of 0 - however prior
+to the scheduler being commenced we don't want the critical nesting level
+to reach zero, so it is initialised to a high value. */
+#define portINITIAL_NESTING_VALUE	( 0xff )
+
+/* Our hardware setup only uses one counter. */
+#define portCOUNTER_0 				0
+
+/* The stack used by the ISR is filled with a known value to assist in
+debugging. */
+#define portISR_STACK_FILL_VALUE	0x55555555
+
+/* Counts the nesting depth of calls to portENTER_CRITICAL().  Each task
+maintains it's own count, so this variable is saved as part of the task
+context. */
+volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
+
+/* To limit the amount of stack required by each task, this port uses a
+separate stack for interrupts. */
+uint32_t *pulISRStack;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
+ * could have alternatively used the watchdog timer or timer 1.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been made.
+ *
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+extern void *_SDA2_BASE_, *_SDA_BASE_;
+const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
+const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
+
+	/* Place a few bytes of known values on the bottom of the stack.
+	This is essential for the Microblaze port and these lines must
+	not be omitted.  The parameter value will overwrite the
+	0x22222222 value during the function prologue. */
+	*pxTopOfStack = ( StackType_t ) 0x11111111;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x22222222;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x33333333;
+	pxTopOfStack--;
+
+	/* First stack an initial value for the critical section nesting.  This
+	is initialised to zero as tasks are started with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) 0x00;	/* R0. */
+
+	/* Place an initial value for all the general purpose registers. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) ulR2;	/* R2 - small data area. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x03;	/* R3. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x04;	/* R4. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x06;	/* R6. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x07;	/* R7. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x08;	/* R8. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x09;	/* R9. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0a;	/* R10. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0b;	/* R11. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0c;	/* R12. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) ulR13;	/* R13 - small data read write area. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;	/* R14. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0f;	/* R15. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x10;	/* R16. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x11;	/* R17. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12;	/* R18. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x13;	/* R19. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x14;	/* R20. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x15;	/* R21. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x16;	/* R22. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x17;	/* R23. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x18;	/* R24. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x19;	/* R25. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x1a;	/* R26. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x1b;	/* R27. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x1c;	/* R28. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x1d;	/* R29. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x1e;	/* R30. */
+	pxTopOfStack--;
+
+	/* The MSR is stacked between R30 and R31. */
+	*pxTopOfStack = portINITIAL_MSR_STATE;
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0x1f;	/* R31. */
+	pxTopOfStack--;
+
+	/* Return a pointer to the top of the stack we have generated so this can
+	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void ( __FreeRTOS_interrupt_Handler )( void );
+extern void ( vStartFirstTask )( void );
+
+
+	/* Setup the FreeRTOS interrupt handler.  Code copied from crt0.s. */
+	asm volatile ( 	"la	r6, r0, __FreeRTOS_interrupt_handler		\n\t" \
+					"sw	r6, r1, r0									\n\t" \
+					"lhu r7, r1, r0									\n\t" \
+					"shi r7, r0, 0x12								\n\t" \
+					"shi r6, r0, 0x16 " );
+
+	/* Setup the hardware to generate the tick.  Interrupts are disabled when
+	this function is called. */
+	prvSetupTimerInterrupt();
+
+	/* Allocate the stack to be used by the interrupt handler. */
+	pulISRStack = ( uint32_t * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) );
+
+	/* Restore the context of the first task that is going to run. */
+	if( pulISRStack != NULL )
+	{
+		/* Fill the ISR stack with a known value to facilitate debugging. */
+		memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( StackType_t ) );
+		pulISRStack += ( configMINIMAL_STACK_SIZE - 1 );
+
+		/* Kick off the first task. */
+		vStartFirstTask();
+	}
+
+	/* Should not get here as the tasks are now running! */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.
+ */
+void vPortYield( void )
+{
+extern void VPortYieldASM( void );
+
+	/* Perform the context switch in a critical section to assure it is
+	not interrupted by the tick ISR.  It is not a problem to do this as
+	each task maintains it's own interrupt status. */
+	portENTER_CRITICAL();
+		/* Jump directly to the yield function to ensure there is no
+		compiler generated prologue code. */
+		asm volatile (	"bralid r14, VPortYieldASM		\n\t" \
+						"or r0, r0, r0					\n\t" );
+	portEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+XTmrCtr xTimer;
+const uint32_t ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+UBaseType_t uxMask;
+
+	/* The OPB timer1 is used to generate the tick.  Use the provided library
+	functions to enable the timer and set the tick frequency. */
+	XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID );
+	XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
+   	XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue );
+	XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK );
+
+	/* Set the timer interrupt enable bit while maintaining the other bit
+	states. */
+	uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
+	uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK;
+	XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) );
+
+	XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
+	XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_OCCURED_MASK );
+	XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt handler placed in the interrupt vector when the scheduler is
+ * started.  The task context has already been saved when this is called.
+ * This handler determines the interrupt source and calls the relevant
+ * peripheral handler.
+ */
+void vTaskISRHandler( void )
+{
+static uint32_t ulPending;
+
+	/* Which interrupts are pending? */
+	ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) );
+
+	if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS )
+	{
+		static XIntc_VectorTableEntry *pxTablePtr;
+		static XIntc_Config *pxConfig;
+		static uint32_t ulInterruptMask;
+
+		ulInterruptMask = ( uint32_t ) 1 << ulPending;
+
+		/* Get the configuration data using the device ID */
+		pxConfig = &XIntc_ConfigTable[ ( uint32_t ) XPAR_INTC_SINGLE_DEVICE_ID ];
+
+		pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] );
+		if( pxConfig->AckBeforeService & ( ulInterruptMask  ) )
+		{
+			XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
+			pxTablePtr->Handler( pxTablePtr->CallBackRef );
+		}
+		else
+		{
+			pxTablePtr->Handler( pxTablePtr->CallBackRef );
+			XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Handler for the timer interrupt.
+ */
+void vTickISR( void *pvBaseAddress )
+{
+uint32_t ulCSR;
+
+	/* Increment the RTOS tick - this might cause a task to unblock. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		vTaskSwitchContext();
+	}
+
+	/* Clear the timer interrupt */
+	ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0);
+	XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR );
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlaze/portasm.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlaze/portasm.s
new file mode 100644
index 0000000..67cf22c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlaze/portasm.s
@@ -0,0 +1,197 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+	.extern pxCurrentTCB
+	.extern vTaskISRHandler
+	.extern vTaskSwitchContext
+	.extern uxCriticalNesting
+	.extern pulISRStack
+
+	.global __FreeRTOS_interrupt_handler
+	.global VPortYieldASM
+	.global vStartFirstTask
+
+
+.macro portSAVE_CONTEXT
+	/* Make room for the context on the stack. */
+	addik r1, r1, -132
+	/* Save r31 so it can then be used. */
+	swi r31, r1, 4
+	/* Copy the msr into r31 - this is stacked later. */
+	mfs r31, rmsr
+	/* Stack general registers. */
+	swi r30, r1, 12
+	swi r29, r1, 16
+	swi r28, r1, 20
+	swi r27, r1, 24
+	swi r26, r1, 28
+	swi r25, r1, 32
+	swi r24, r1, 36
+	swi r23, r1, 40
+	swi r22, r1, 44
+	swi r21, r1, 48
+	swi r20, r1, 52
+	swi r19, r1, 56
+	swi r18, r1, 60
+	swi r17, r1, 64
+	swi r16, r1, 68
+	swi r15, r1, 72
+	swi r13, r1, 80
+	swi r12, r1, 84
+	swi r11, r1, 88
+	swi r10, r1, 92
+	swi r9, r1, 96
+	swi r8, r1, 100
+	swi r7, r1, 104
+	swi r6, r1, 108
+	swi r5, r1, 112
+	swi r4, r1, 116
+	swi r3, r1, 120
+	swi r2, r1, 124
+	/* Stack the critical section nesting value. */
+	lwi r3, r0, uxCriticalNesting
+	swi r3, r1, 128
+	/* Save the top of stack value to the TCB. */
+	lwi r3, r0, pxCurrentTCB
+	sw	r1, r0, r3
+	
+	.endm
+
+.macro portRESTORE_CONTEXT
+	/* Load the top of stack value from the TCB. */
+	lwi r3, r0, pxCurrentTCB
+	lw	r1, r0, r3	
+	/* Restore the general registers. */
+	lwi r31, r1, 4		
+	lwi r30, r1, 12		
+	lwi r29, r1, 16	
+	lwi r28, r1, 20	
+	lwi r27, r1, 24	
+	lwi r26, r1, 28	
+	lwi r25, r1, 32	
+	lwi r24, r1, 36	
+	lwi r23, r1, 40	
+	lwi r22, r1, 44	
+	lwi r21, r1, 48	
+	lwi r20, r1, 52	
+	lwi r19, r1, 56	
+	lwi r18, r1, 60	
+	lwi r17, r1, 64	
+	lwi r16, r1, 68	
+	lwi r15, r1, 72	
+	lwi r14, r1, 76	
+	lwi r13, r1, 80	
+	lwi r12, r1, 84	
+	lwi r11, r1, 88	
+	lwi r10, r1, 92	
+	lwi r9, r1, 96	
+	lwi r8, r1, 100	
+	lwi r7, r1, 104
+	lwi r6, r1, 108
+	lwi r5, r1, 112
+	lwi r4, r1, 116
+	lwi r2, r1, 124
+
+	/* Load the critical nesting value. */
+	lwi r3, r1, 128
+	swi r3, r0, uxCriticalNesting
+
+	/* Obtain the MSR value from the stack. */
+	lwi r3, r1, 8
+
+	/* Are interrupts enabled in the MSR?  If so return using an return from 
+	interrupt instruction to ensure interrupts are enabled only once the task
+	is running again. */
+	andi r3, r3, 2
+	beqid r3, 36
+	or r0, r0, r0
+
+	/* Reload the rmsr from the stack, clear the enable interrupt bit in the
+	value before saving back to rmsr register, then return enabling interrupts
+	as we return. */
+	lwi r3, r1, 8
+	andi r3, r3, ~2
+	mts rmsr, r3
+	lwi r3, r1, 120
+	addik r1, r1, 132
+	rtid r14, 0
+	or r0, r0, r0
+
+	/* Reload the rmsr from the stack, place it in the rmsr register, and
+	return without enabling interrupts. */
+	lwi r3, r1, 8
+	mts rmsr, r3
+	lwi r3, r1, 120
+	addik r1, r1, 132
+	rtsd r14, 0
+	or r0, r0, r0
+
+	.endm
+
+	.text
+	.align  2
+
+
+__FreeRTOS_interrupt_handler:
+	portSAVE_CONTEXT
+	/* Entered via an interrupt so interrupts must be enabled in msr. */
+	ori r31, r31, 2
+	/* Stack msr. */
+	swi r31, r1, 8
+	/* Stack the return address.  As we entered via an interrupt we do
+	not need to modify the return address prior to stacking. */
+	swi r14, r1, 76
+	/* Now switch to use the ISR stack. */
+	lwi r3, r0, pulISRStack
+	add r1, r3, r0
+	bralid r15, vTaskISRHandler
+	or r0, r0, r0
+	portRESTORE_CONTEXT
+
+
+VPortYieldASM:
+	portSAVE_CONTEXT
+	/* Stack msr. */
+	swi r31, r1, 8
+	/* Modify the return address so we return to the instruction after the
+	exception. */
+	addi r14, r14, 8
+	swi r14, r1, 76
+	/* Now switch to use the ISR stack. */
+	lwi r3, r0, pulISRStack
+	add r1, r3, r0
+	bralid r15, vTaskSwitchContext
+	or r0, r0, r0
+	portRESTORE_CONTEXT
+
+vStartFirstTask:
+	portRESTORE_CONTEXT
+	
+	
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlaze/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlaze/portmacro.h
new file mode 100644
index 0000000..d6af7a4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlaze/portmacro.h
@@ -0,0 +1,126 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+void microblaze_disable_interrupts( void );
+void microblaze_enable_interrupts( void );
+#define portDISABLE_INTERRUPTS()	microblaze_disable_interrupts()
+#define portENABLE_INTERRUPTS()		microblaze_enable_interrupts()
+/*-----------------------------------------------------------*/
+
+/* Critical section macros. */
+void vPortEnterCritical( void );
+void vPortExitCritical( void );
+#define portENTER_CRITICAL()		{														\
+										extern UBaseType_t uxCriticalNesting;	\
+										microblaze_disable_interrupts();					\
+										uxCriticalNesting++;								\
+									}
+
+#define portEXIT_CRITICAL()			{														\
+										extern UBaseType_t uxCriticalNesting;	\
+										/* Interrupts are disabled, so we can */			\
+										/* access the variable directly. */					\
+										uxCriticalNesting--;								\
+										if( uxCriticalNesting == 0 )			\
+										{													\
+											/* The nesting has unwound and we 				\
+											can enable interrupts again. */					\
+											portENABLE_INTERRUPTS();						\
+										}													\
+									}
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+void vPortYield( void );
+#define portYIELD() vPortYield()
+
+void vTaskSwitchContext();
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			4
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV8/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV8/port.c
new file mode 100644
index 0000000..ec35a43
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV8/port.c
@@ -0,0 +1,452 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MicroBlaze port.
+ *----------------------------------------------------------*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include 
+
+/* Hardware includes. */
+#include 
+#include 
+#include 
+
+/* Tasks are started with a critical section nesting of 0 - however, prior to
+the scheduler being commenced interrupts should not be enabled, so the critical
+nesting variable is initialised to a non-zero value. */
+#define portINITIAL_NESTING_VALUE	( 0xff )
+
+/* The bit within the MSR register that enabled/disables interrupts and 
+exceptions respectively. */
+#define portMSR_IE					( 0x02U )
+#define portMSR_EE					( 0x100U )
+
+/* If the floating point unit is included in the MicroBlaze build, then the
+FSR register is saved as part of the task context.  portINITIAL_FSR is the value
+given to the FSR register when the initial context is set up for a task being
+created. */
+#define portINITIAL_FSR				( 0U )
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the interrupt controller instance.
+ */
+static int32_t prvInitialiseInterruptController( void );
+
+/* Ensure the interrupt controller instance variable is initialised before it is
+ * used, and that the initialisation only happens once.
+ */
+static int32_t prvEnsureInterruptControllerIsInitialised( void );
+
+/*-----------------------------------------------------------*/
+
+/* Counts the nesting depth of calls to portENTER_CRITICAL().  Each task
+maintains its own count, so this variable is saved as part of the task
+context. */
+volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
+
+/* This port uses a separate stack for interrupts.  This prevents the stack of
+every task needing to be large enough to hold an entire interrupt stack on top
+of the task stack. */
+uint32_t *pulISRStack;
+
+/* If an interrupt requests a context switch, then ulTaskSwitchRequested will
+get set to 1.  ulTaskSwitchRequested is inspected just before the main interrupt
+handler exits.  If, at that time, ulTaskSwitchRequested is set to 1, the kernel
+will call vTaskSwitchContext() to ensure the task that runs immediately after
+the interrupt exists is the highest priority task that is able to run.  This is
+an unusual mechanism, but is used for this port because a single interrupt can
+cause the servicing of multiple peripherals - and it is inefficient to call
+vTaskSwitchContext() multiple times as each peripheral is serviced. */
+volatile uint32_t ulTaskSwitchRequested = 0UL;
+
+/* The instance of the interrupt controller used by this port.  This is required
+by the Xilinx library API functions. */
+static XIntc xInterruptControllerInstance;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been made.
+ *
+ * See the portable.h header file.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+extern void *_SDA2_BASE_, *_SDA_BASE_;
+const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
+const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
+
+	/* Place a few bytes of known values on the bottom of the stack.
+	This is essential for the Microblaze port and these lines must
+	not be omitted. */
+	*pxTopOfStack = ( StackType_t ) 0x00000000;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00000000;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00000000;
+	pxTopOfStack--;
+
+	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+		/* The FSR value placed in the initial task context is just 0. */
+		*pxTopOfStack = portINITIAL_FSR;
+		pxTopOfStack--;
+	#endif
+
+	/* The MSR value placed in the initial task context should have interrupts
+	disabled.  Each task will enable interrupts automatically when it enters
+	the running state for the first time. */
+	*pxTopOfStack = mfmsr() & ~portMSR_IE;
+	
+	#if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
+	{
+		/* Ensure exceptions are enabled for the task. */
+		*pxTopOfStack |= portMSR_EE;
+	}
+	#endif
+
+	pxTopOfStack--;
+
+	/* First stack an initial value for the critical section nesting.  This
+	is initialised to zero. */
+	*pxTopOfStack = ( StackType_t ) 0x00;
+
+	/* R0 is always zero. */
+	/* R1 is the SP. */
+
+	/* Place an initial value for all the general purpose registers. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) ulR2;	/* R2 - read only small data area. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x03;	/* R3 - return values and temporaries. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x04;	/* R4 - return values and temporaries. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
+
+	#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06;	/* R6 - other parameters and temporaries.  Used as the return address from vPortTaskEntryPoint. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07;	/* R7 - other parameters and temporaries. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x08;	/* R8 - other parameters and temporaries. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09;	/* R9 - other parameters and temporaries. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x0a;	/* R10 - other parameters and temporaries. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x0b;	/* R11 - temporaries. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x0c;	/* R12 - temporaries. */
+		pxTopOfStack--;
+	#else
+		pxTopOfStack-= 8;
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) ulR13;	/* R13 - read/write small data area. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;	/* R14 - return address for interrupt. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) NULL;	/* R15 - return address for subroutine. */
+
+	#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10;	/* R16 - return address for trap (debugger). */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11;	/* R17 - return address for exceptions, if configured. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x12;	/* R18 - reserved for assembler and compiler temporaries. */
+		pxTopOfStack--;
+	#else
+		pxTopOfStack -= 4;
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) 0x00;	/* R19 - must be saved across function calls. Callee-save.  Seems to be interpreted as the frame pointer. */
+
+	#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x14;	/* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save.  Not used by FreeRTOS. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x15;	/* R21 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x16;	/* R22 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x17;	/* R23 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x18;	/* R24 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x19;	/* R25 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1a;	/* R26 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1b;	/* R27 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1c;	/* R28 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1d;	/* R29 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1e;	/* R30 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1f;	/* R31 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+	#else
+		pxTopOfStack -= 13;
+	#endif
+
+	/* Return a pointer to the top of the stack that has been generated so this
+	can	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void ( vPortStartFirstTask )( void );
+extern uint32_t _stack[];
+
+	/* Setup the hardware to generate the tick.  Interrupts are disabled when
+	this function is called.
+
+	This port uses an application defined callback function to install the tick
+	interrupt handler because the kernel will run on lots of different
+	MicroBlaze and FPGA configurations - not all of	which will have the same
+	timer peripherals defined or available.  An example definition of
+	vApplicationSetupTimerInterrupt() is provided in the official demo
+	application that accompanies this port. */
+	vApplicationSetupTimerInterrupt();
+
+	/* Reuse the stack from main() as the stack for the interrupts/exceptions. */
+	pulISRStack = ( uint32_t * ) _stack;
+
+	/* Ensure there is enough space for the functions called from the interrupt
+	service routines to write back into the stack frame of the caller. */
+	pulISRStack -= 2;
+
+	/* Restore the context of the first task that is going to run.  From here
+	on, the created tasks will be executing. */
+	vPortStartFirstTask();
+
+	/* Should not get here as the tasks are now running! */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.
+ */
+void vPortYield( void )
+{
+extern void VPortYieldASM( void );
+
+	/* Perform the context switch in a critical section to assure it is
+	not interrupted by the tick ISR.  It is not a problem to do this as
+	each task maintains its own interrupt status. */
+	portENTER_CRITICAL();
+	{
+		/* Jump directly to the yield function to ensure there is no
+		compiler generated prologue code. */
+		asm volatile (	"bralid r14, VPortYieldASM		\n\t" \
+						"or r0, r0, r0					\n\t" );
+	}
+	portEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnableInterrupt( uint8_t ucInterruptID )
+{
+int32_t lReturn;
+
+	/* An API function is provided to enable an interrupt in the interrupt
+	controller because the interrupt controller instance variable is private
+	to this file. */
+	lReturn = prvEnsureInterruptControllerIsInitialised();
+	if( lReturn == pdPASS )
+	{
+		XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
+	}
+
+	configASSERT( lReturn );
+}
+/*-----------------------------------------------------------*/
+
+void vPortDisableInterrupt( uint8_t ucInterruptID )
+{
+int32_t lReturn;
+
+	/* An API function is provided to disable an interrupt in the interrupt
+	controller because the interrupt controller instance variable is private
+	to this file. */
+	lReturn = prvEnsureInterruptControllerIsInitialised();
+
+	if( lReturn == pdPASS )
+	{
+		XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );
+	}
+
+	configASSERT( lReturn );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
+{
+int32_t lReturn;
+
+	/* An API function is provided to install an interrupt handler because the
+	interrupt controller instance variable is private to this file. */
+
+	lReturn = prvEnsureInterruptControllerIsInitialised();
+
+	if( lReturn == pdPASS )
+	{
+		lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );
+	}
+
+	if( lReturn == XST_SUCCESS )
+	{
+		lReturn = pdPASS;
+	}
+
+	configASSERT( lReturn == pdPASS );
+
+	return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+static int32_t prvEnsureInterruptControllerIsInitialised( void )
+{
+static int32_t lInterruptControllerInitialised = pdFALSE;
+int32_t lReturn;
+
+	/* Ensure the interrupt controller instance variable is initialised before
+	it is used, and that the initialisation only happens once. */
+	if( lInterruptControllerInitialised != pdTRUE )
+	{
+		lReturn = prvInitialiseInterruptController();
+
+		if( lReturn == pdPASS )
+		{
+			lInterruptControllerInitialised = pdTRUE;
+		}
+	}
+	else
+	{
+		lReturn = pdPASS;
+	}
+
+	return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Handler for the timer interrupt.  This is the handler that the application
+ * defined callback function vApplicationSetupTimerInterrupt() should install.
+ */
+void vPortTickISR( void *pvUnused )
+{
+extern void vApplicationClearTimerInterrupt( void );
+
+	/* Ensure the unused parameter does not generate a compiler warning. */
+	( void ) pvUnused;
+
+	/* This port uses an application defined callback function to clear the tick
+	interrupt because the kernel will run on lots of different MicroBlaze and
+	FPGA configurations - not all of which will have the same timer peripherals
+	defined or available.  An example definition of
+	vApplicationClearTimerInterrupt() is provided in the official demo
+	application that accompanies this port. */
+	vApplicationClearTimerInterrupt();
+
+	/* Increment the RTOS tick - this might cause a task to unblock. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		/* Force vTaskSwitchContext() to be called as the interrupt exits. */
+		ulTaskSwitchRequested = 1;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static int32_t prvInitialiseInterruptController( void )
+{
+int32_t lStatus;
+
+	lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
+
+	if( lStatus == XST_SUCCESS )
+	{
+		/* Initialise the exception table. */
+		Xil_ExceptionInit();
+
+	    /* Service all pending interrupts each time the handler is entered. */
+	    XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
+
+	    /* Install exception handlers if the MicroBlaze is configured to handle
+	    exceptions, and the application defined constant
+	    configINSTALL_EXCEPTION_HANDLERS is set to 1. */
+		#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
+	    {
+	    	vPortExceptionsInstallHandlers();
+	    }
+		#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
+
+		/* Start the interrupt controller.  Interrupts are enabled when the
+		scheduler starts. */
+		lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
+
+		if( lStatus == XST_SUCCESS )
+		{
+			lStatus = pdPASS;
+		}
+		else
+		{
+			lStatus = pdFAIL;
+		}
+	}
+
+	configASSERT( lStatus == pdPASS );
+
+	return lStatus;
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV8/port_exceptions.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV8/port_exceptions.c
new file mode 100644
index 0000000..33380c7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV8/port_exceptions.c
@@ -0,0 +1,282 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Hardware includes. */
+#include 
+#include 
+
+/* The Xilinx library defined exception entry point stacks a number of
+registers.  These definitions are offsets from the stack pointer to the various
+stacked register values. */
+#define portexR3_STACK_OFFSET	4
+#define portexR4_STACK_OFFSET	5
+#define portexR5_STACK_OFFSET	6
+#define portexR6_STACK_OFFSET	7
+#define portexR7_STACK_OFFSET	8
+#define portexR8_STACK_OFFSET	9
+#define portexR9_STACK_OFFSET	10
+#define portexR10_STACK_OFFSET	11
+#define portexR11_STACK_OFFSET	12
+#define portexR12_STACK_OFFSET	13
+#define portexR15_STACK_OFFSET	16
+#define portexR18_STACK_OFFSET  19
+#define portexMSR_STACK_OFFSET	20
+#define portexR19_STACK_OFFSET  -1
+
+/* This is defined to equal the size, in bytes, of the stack frame generated by
+the Xilinx standard library exception entry point.  It is required to determine
+the stack pointer value prior to the exception being entered. */
+#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL
+
+/* The number of bytes a MicroBlaze instruction consumes. */
+#define portexINSTRUCTION_SIZE	4
+
+/* Exclude this entire file if the MicroBlaze is not configured to handle
+exceptions, or the application defined configuration constant
+configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
+#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
+
+/* This variable is set in the exception entry code, before
+vPortExceptionHandler is called. */
+uint32_t *pulStackPointerOnFunctionEntry = NULL;
+
+/* This is the structure that is filled with the MicroBlaze context as it
+existed immediately prior to the exception occurrence.  A pointer to this
+structure is passed into the vApplicationExceptionRegisterDump() callback
+function, if one is defined. */
+static xPortRegisterDump xRegisterDump;
+
+/* This is the FreeRTOS exception handler that is installed for all exception
+types.  It is called from vPortExceptionHanlderEntry() - which is itself defined
+in portasm.S. */
+void vPortExceptionHandler( void *pvExceptionID );
+extern void vPortExceptionHandlerEntry( void *pvExceptionID );
+
+/*-----------------------------------------------------------*/
+
+/* vApplicationExceptionRegisterDump() is a callback function that the
+application can optionally define to receive a populated xPortRegisterDump
+structure.  If the application chooses not to define a version of
+vApplicationExceptionRegisterDump() then this weekly defined default
+implementation will be called instead. */
+extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak));
+void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )
+{
+	( void ) xRegisterDump;
+
+	for( ;; )
+	{
+		portNOP();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExceptionHandler( void *pvExceptionID )
+{
+extern void *pxCurrentTCB;
+
+	/* Fill an xPortRegisterDump structure with the MicroBlaze context as it
+	was immediately before the exception occurrence. */
+
+	/* First fill in the name and handle of the task that was in the Running
+	state when the exception occurred. */
+	xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
+	xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
+
+	configASSERT( pulStackPointerOnFunctionEntry );
+
+	/* Obtain the values of registers that were stacked prior to this function
+	being called, and may have changed since they were stacked. */
+	xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
+	xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
+	xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
+	xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
+	xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
+	xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
+	xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
+	xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
+	xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
+	xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
+	xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
+	xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
+	xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
+	xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
+
+	/* Obtain the value of all other registers. */
+	xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
+	xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
+	xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
+	xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
+	xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
+	xRegisterDump.ulR20 = mfgpr( R20 );
+	xRegisterDump.ulR21 = mfgpr( R21 );
+	xRegisterDump.ulR22 = mfgpr( R22 );
+	xRegisterDump.ulR23 = mfgpr( R23 );
+	xRegisterDump.ulR24 = mfgpr( R24 );
+	xRegisterDump.ulR25 = mfgpr( R25 );
+	xRegisterDump.ulR26 = mfgpr( R26 );
+	xRegisterDump.ulR27 = mfgpr( R27 );
+	xRegisterDump.ulR28 = mfgpr( R28 );
+	xRegisterDump.ulR29 = mfgpr( R29 );
+	xRegisterDump.ulR30 = mfgpr( R30 );
+	xRegisterDump.ulR31 = mfgpr( R31 );
+	xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
+	xRegisterDump.ulEAR = mfear();
+	xRegisterDump.ulESR = mfesr();
+	xRegisterDump.ulEDR = mfedr();
+
+	/* Move the saved program counter back to the instruction that was executed
+	when the exception occurred.  This is only valid for certain types of
+	exception. */
+	xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
+
+	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+	{
+		xRegisterDump.ulFSR = mffsr();
+	}
+	#else
+	{
+		xRegisterDump.ulFSR = 0UL;
+	}
+	#endif
+
+	/* Also fill in a string that describes what type of exception this is.
+	The string uses the same ID names as defined in the MicroBlaze standard
+	library exception header files. */
+	switch( ( uint32_t ) pvExceptionID )
+	{
+		case XEXC_ID_FSL :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
+				break;
+
+		case XEXC_ID_UNALIGNED_ACCESS :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
+				break;
+
+		case XEXC_ID_ILLEGAL_OPCODE :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
+				break;
+
+		case XEXC_ID_M_AXI_I_EXCEPTION :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
+				break;
+
+		case XEXC_ID_M_AXI_D_EXCEPTION :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
+				break;
+
+		case XEXC_ID_DIV_BY_ZERO :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
+				break;
+
+		case XEXC_ID_STACK_VIOLATION :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
+				break;
+
+		#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+
+			case XEXC_ID_FPU :
+						xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
+						break;
+
+		#endif /* XPAR_MICROBLAZE_USE_FPU */
+	}
+
+	/* vApplicationExceptionRegisterDump() is a callback function that the
+	application can optionally define to receive the populated xPortRegisterDump
+	structure.  If the application chooses not to define a version of
+	vApplicationExceptionRegisterDump() then the weekly defined default
+	implementation within this file will be called instead. */
+	vApplicationExceptionRegisterDump( &xRegisterDump );
+
+	/* Must not attempt to leave this function! */
+	for( ;; )
+	{
+		portNOP();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExceptionsInstallHandlers( void )
+{
+static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
+
+	if( ulHandlersAlreadyInstalled == pdFALSE )
+	{
+		ulHandlersAlreadyInstalled = pdTRUE;
+
+		#if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
+			microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
+		#endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
+
+		#if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
+		#endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
+		#endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
+		#endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
+		#endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
+		#endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
+		#endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
+		#endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
+		#endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
+
+		microblaze_enable_exceptions();
+	}
+}
+
+/* Exclude the entire file if the MicroBlaze is not configured to handle
+exceptions, or the application defined configuration item
+configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
+#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV8/portasm.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV8/portasm.S
new file mode 100644
index 0000000..5d6b4b8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV8/portasm.S
@@ -0,0 +1,328 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/* Xilinx library includes. */
+#include "microblaze_exceptions_g.h"
+#include "xparameters.h"
+
+/* The context is oversized to allow functions called from the ISR to write
+back into the caller stack. */
+#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+	#define portCONTEXT_SIZE 136
+	#define portMINUS_CONTEXT_SIZE -136
+#else
+	#define portCONTEXT_SIZE 132
+	#define portMINUS_CONTEXT_SIZE -132
+#endif
+
+/* Offsets from the stack pointer at which saved registers are placed. */
+#define portR31_OFFSET	4
+#define portR30_OFFSET	8
+#define portR29_OFFSET	12
+#define portR28_OFFSET	16
+#define portR27_OFFSET	20
+#define portR26_OFFSET	24
+#define portR25_OFFSET	28
+#define portR24_OFFSET	32
+#define portR23_OFFSET	36
+#define portR22_OFFSET	40
+#define portR21_OFFSET	44
+#define portR20_OFFSET	48
+#define portR19_OFFSET	52
+#define portR18_OFFSET	56
+#define portR17_OFFSET	60
+#define portR16_OFFSET	64
+#define portR15_OFFSET	68
+#define portR14_OFFSET	72
+#define portR13_OFFSET	76
+#define portR12_OFFSET	80
+#define portR11_OFFSET	84
+#define portR10_OFFSET	88
+#define portR9_OFFSET	92
+#define portR8_OFFSET	96
+#define portR7_OFFSET	100
+#define portR6_OFFSET	104
+#define portR5_OFFSET	108
+#define portR4_OFFSET	112
+#define portR3_OFFSET	116
+#define portR2_OFFSET	120
+#define portCRITICAL_NESTING_OFFSET 124
+#define portMSR_OFFSET 128
+#define portFSR_OFFSET 132
+
+	.extern pxCurrentTCB
+	.extern XIntc_DeviceInterruptHandler
+	.extern vTaskSwitchContext
+	.extern uxCriticalNesting
+	.extern pulISRStack
+	.extern ulTaskSwitchRequested
+	.extern vPortExceptionHandler
+	.extern pulStackPointerOnFunctionEntry
+
+	.global _interrupt_handler
+	.global VPortYieldASM
+	.global vPortStartFirstTask
+	.global vPortExceptionHandlerEntry
+
+
+.macro portSAVE_CONTEXT
+
+	/* Make room for the context on the stack. */
+	addik r1, r1, portMINUS_CONTEXT_SIZE
+
+	/* Stack general registers. */
+	swi r31, r1, portR31_OFFSET
+	swi r30, r1, portR30_OFFSET
+	swi r29, r1, portR29_OFFSET
+	swi r28, r1, portR28_OFFSET
+	swi r27, r1, portR27_OFFSET
+	swi r26, r1, portR26_OFFSET
+	swi r25, r1, portR25_OFFSET
+	swi r24, r1, portR24_OFFSET
+	swi r23, r1, portR23_OFFSET
+	swi r22, r1, portR22_OFFSET
+	swi r21, r1, portR21_OFFSET
+	swi r20, r1, portR20_OFFSET
+	swi r19, r1, portR19_OFFSET
+	swi r18, r1, portR18_OFFSET
+	swi r17, r1, portR17_OFFSET
+	swi r16, r1, portR16_OFFSET
+	swi r15, r1, portR15_OFFSET
+	/* R14 is saved later as it needs adjustment if a yield is performed. */
+	swi r13, r1, portR13_OFFSET
+	swi r12, r1, portR12_OFFSET
+	swi r11, r1, portR11_OFFSET
+	swi r10, r1, portR10_OFFSET
+	swi r9, r1, portR9_OFFSET
+	swi r8, r1, portR8_OFFSET
+	swi r7, r1, portR7_OFFSET
+	swi r6, r1, portR6_OFFSET
+	swi r5, r1, portR5_OFFSET
+	swi r4, r1, portR4_OFFSET
+	swi r3, r1, portR3_OFFSET
+	swi r2, r1, portR2_OFFSET
+
+	/* Stack the critical section nesting value. */
+	lwi r18, r0, uxCriticalNesting
+	swi r18, r1, portCRITICAL_NESTING_OFFSET
+
+	/* Stack MSR. */
+	mfs r18, rmsr
+	swi r18, r1, portMSR_OFFSET
+
+	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+		/* Stack FSR. */
+		mfs r18, rfsr
+		swi r18, r1, portFSR_OFFSET
+	#endif
+
+	/* Save the top of stack value to the TCB. */
+	lwi r3, r0, pxCurrentTCB
+	sw	r1, r0, r3
+
+	.endm
+
+.macro portRESTORE_CONTEXT
+
+	/* Load the top of stack value from the TCB. */
+	lwi r18, r0, pxCurrentTCB
+	lw	r1, r0, r18
+
+	/* Restore the general registers. */
+	lwi r31, r1, portR31_OFFSET
+	lwi r30, r1, portR30_OFFSET
+	lwi r29, r1, portR29_OFFSET
+	lwi r28, r1, portR28_OFFSET
+	lwi r27, r1, portR27_OFFSET
+	lwi r26, r1, portR26_OFFSET
+	lwi r25, r1, portR25_OFFSET
+	lwi r24, r1, portR24_OFFSET
+	lwi r23, r1, portR23_OFFSET
+	lwi r22, r1, portR22_OFFSET
+	lwi r21, r1, portR21_OFFSET
+	lwi r20, r1, portR20_OFFSET
+	lwi r19, r1, portR19_OFFSET
+	lwi r17, r1, portR17_OFFSET
+	lwi r16, r1, portR16_OFFSET
+	lwi r15, r1, portR15_OFFSET
+	lwi r14, r1, portR14_OFFSET
+	lwi r13, r1, portR13_OFFSET
+	lwi r12, r1, portR12_OFFSET
+	lwi r11, r1, portR11_OFFSET
+	lwi r10, r1, portR10_OFFSET
+	lwi r9, r1, portR9_OFFSET
+	lwi r8, r1, portR8_OFFSET
+	lwi r7, r1, portR7_OFFSET
+	lwi r6, r1, portR6_OFFSET
+	lwi r5, r1, portR5_OFFSET
+	lwi r4, r1, portR4_OFFSET
+	lwi r3, r1, portR3_OFFSET
+	lwi r2, r1, portR2_OFFSET
+
+	/* Reload the rmsr from the stack. */
+	lwi r18, r1, portMSR_OFFSET
+	mts rmsr, r18
+
+	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+		/* Reload the FSR from the stack. */
+		lwi r18, r1, portFSR_OFFSET
+		mts rfsr, r18
+	#endif
+
+	/* Load the critical nesting value. */
+	lwi r18, r1, portCRITICAL_NESTING_OFFSET
+	swi r18, r0, uxCriticalNesting
+
+	/* Test the critical nesting value.  If it is non zero then the task last
+	exited the running state using a yield.  If it is zero, then the task
+	last exited the running state through an interrupt. */
+	xori r18, r18, 0
+	bnei r18, exit_from_yield
+
+	/* r18 was being used as a temporary.  Now restore its true value from the
+	stack. */
+	lwi r18, r1, portR18_OFFSET
+
+	/* Remove the stack frame. */
+	addik r1, r1, portCONTEXT_SIZE
+
+	/* Return using rtid so interrupts are re-enabled as this function is
+	exited. */
+	rtid r14, 0
+	or r0, r0, r0
+
+	.endm
+
+/* This function is used to exit portRESTORE_CONTEXT() if the task being
+returned to last left the Running state by calling taskYIELD() (rather than
+being preempted by an interrupt). */
+	.text
+	.align  4
+exit_from_yield:
+
+	/* r18 was being used as a temporary.  Now restore its true value from the
+	stack. */
+	lwi r18, r1, portR18_OFFSET
+
+	/* Remove the stack frame. */
+	addik r1, r1, portCONTEXT_SIZE
+
+	/* Return to the task. */
+	rtsd r14, 0
+	or r0, r0, r0
+
+
+	.text
+	.align  4
+_interrupt_handler:
+
+	portSAVE_CONTEXT
+
+	/* Stack the return address. */
+	swi r14, r1, portR14_OFFSET
+
+	/* Switch to the ISR stack. */
+	lwi r1, r0, pulISRStack
+
+	/* The parameter to the interrupt handler. */
+	ori r5, r0, configINTERRUPT_CONTROLLER_TO_USE
+
+	/* Execute any pending interrupts. */
+	bralid r15, XIntc_DeviceInterruptHandler
+	or r0, r0, r0
+
+	/* See if a new task should be selected to execute. */
+	lwi r18, r0, ulTaskSwitchRequested
+	or r18, r18, r0
+
+	/* If ulTaskSwitchRequested is already zero, then jump straight to
+	restoring the task that is already in the Running state. */
+	beqi r18, task_switch_not_requested
+
+	/* Set ulTaskSwitchRequested back to zero as a task switch is about to be
+	performed. */
+	swi r0, r0, ulTaskSwitchRequested
+
+	/* ulTaskSwitchRequested was not 0 when tested.  Select the next task to
+	execute. */
+	bralid r15, vTaskSwitchContext
+	or r0, r0, r0
+
+task_switch_not_requested:
+
+	/* Restore the context of the next task scheduled to execute. */
+	portRESTORE_CONTEXT
+
+
+	.text
+	.align  4
+VPortYieldASM:
+
+	portSAVE_CONTEXT
+
+	/* Modify the return address so a return is done to the instruction after
+	the call to VPortYieldASM. */
+	addi r14, r14, 8
+	swi r14, r1, portR14_OFFSET
+
+	/* Switch to use the ISR stack. */
+	lwi r1, r0, pulISRStack
+
+	/* Select the next task to execute. */
+	bralid r15, vTaskSwitchContext
+	or r0, r0, r0
+
+	/* Restore the context of the next task scheduled to execute. */
+	portRESTORE_CONTEXT
+
+	.text
+	.align  4
+vPortStartFirstTask:
+
+	portRESTORE_CONTEXT
+
+
+
+#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
+
+	.text
+	.align 4
+vPortExceptionHandlerEntry:
+
+	/* Take a copy of the stack pointer before vPortExecptionHandler is called,
+	storing its value prior to the function stack frame being created. */
+	swi r1, r0, pulStackPointerOnFunctionEntry
+	bralid r15, vPortExceptionHandler
+	or r0, r0, r0
+
+#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV8/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV8/portmacro.h
new file mode 100644
index 0000000..f0e6dcf
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV8/portmacro.h
@@ -0,0 +1,369 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* BSP includes. */
+#include 
+#include 
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros and functions. */
+void microblaze_disable_interrupts( void );
+void microblaze_enable_interrupts( void );
+#define portDISABLE_INTERRUPTS()	microblaze_disable_interrupts()
+#define portENABLE_INTERRUPTS()		microblaze_enable_interrupts()
+/*-----------------------------------------------------------*/
+
+/* Critical section macros. */
+void vPortEnterCritical( void );
+void vPortExitCritical( void );
+#define portENTER_CRITICAL()		{																\
+										extern volatile UBaseType_t uxCriticalNesting;				\
+										microblaze_disable_interrupts();							\
+										uxCriticalNesting++;										\
+									}
+
+#define portEXIT_CRITICAL()			{																\
+										extern volatile UBaseType_t uxCriticalNesting;				\
+										/* Interrupts are disabled, so we can */					\
+										/* access the variable directly. */							\
+										uxCriticalNesting--;										\
+										if( uxCriticalNesting == 0 )								\
+										{															\
+											/* The nesting has unwound and we 						\
+											can enable interrupts again. */							\
+											portENABLE_INTERRUPTS();								\
+										}															\
+									}
+
+/*-----------------------------------------------------------*/
+
+/* The yield macro maps directly to the vPortYield() function. */
+void vPortYield( void );
+#define portYIELD() vPortYield()
+
+/* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead
+sets a flag to say that a yield has been requested.  The interrupt exit code
+then checks this flag, and calls vTaskSwitchContext() before restoring a task
+context, if the flag is not false.  This is done to prevent multiple calls to
+vTaskSwitchContext() being made from a single interrupt, as a single interrupt
+can result in multiple peripherals being serviced. */
+extern volatile uint32_t ulTaskSwitchRequested;
+#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1
+
+#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+	/* Generic helper function. */
+	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+	{
+	uint8_t ucReturn;
+
+		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
+		return ucReturn;
+	}
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			4
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* The following structure is used by the FreeRTOS exception handler.  It is
+filled with the MicroBlaze context as it was at the time the exception occurred.
+This is done as an aid to debugging exception occurrences. */
+typedef struct PORT_REGISTER_DUMP
+{
+	/* The following structure members hold the values of the MicroBlaze
+	registers at the time the exception was raised. */
+	uint32_t ulR1_SP;
+	uint32_t ulR2_small_data_area;
+	uint32_t ulR3;
+	uint32_t ulR4;
+	uint32_t ulR5;
+	uint32_t ulR6;
+	uint32_t ulR7;
+	uint32_t ulR8;
+	uint32_t ulR9;
+	uint32_t ulR10;
+	uint32_t ulR11;
+	uint32_t ulR12;
+	uint32_t ulR13_read_write_small_data_area;
+	uint32_t ulR14_return_address_from_interrupt;
+	uint32_t ulR15_return_address_from_subroutine;
+	uint32_t ulR16_return_address_from_trap;
+	uint32_t ulR17_return_address_from_exceptions; /* The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. */
+	uint32_t ulR18;
+	uint32_t ulR19;
+	uint32_t ulR20;
+	uint32_t ulR21;
+	uint32_t ulR22;
+	uint32_t ulR23;
+	uint32_t ulR24;
+	uint32_t ulR25;
+	uint32_t ulR26;
+	uint32_t ulR27;
+	uint32_t ulR28;
+	uint32_t ulR29;
+	uint32_t ulR30;
+	uint32_t ulR31;
+	uint32_t ulPC;
+	uint32_t ulESR;
+	uint32_t ulMSR;
+	uint32_t ulEAR;
+	uint32_t ulFSR;
+	uint32_t ulEDR;
+
+	/* A human readable description of the exception cause.  The strings used
+	are the same as the #define constant names found in the
+	microblaze_exceptions_i.h header file */
+	int8_t *pcExceptionCause;
+
+	/* The human readable name of the task that was running at the time the
+	exception occurred.  This is the name that was given to the task when the
+	task was created using the FreeRTOS xTaskCreate() API function. */
+	char *pcCurrentTaskName;
+
+	/* The handle of the task that was running a the time the exception
+	occurred. */
+	void * xCurrentTaskHandle;
+
+} xPortRegisterDump;
+
+
+/*
+ * Installs pxHandler as the interrupt handler for the peripheral specified by
+ * the ucInterruptID parameter.
+ *
+ * ucInterruptID:
+ *
+ * The ID of the peripheral that will have pxHandler assigned as its interrupt
+ * handler.  Peripheral IDs are defined in the xparameters.h header file, which
+ * is itself part of the BSP project.  For example, in the official demo
+ * application for this port, xparameters.h defines the following IDs for the
+ * four possible interrupt sources:
+ *
+ * XPAR_INTC_0_UARTLITE_1_VEC_ID  -  for the UARTlite peripheral.
+ * XPAR_INTC_0_TMRCTR_0_VEC_ID    -  for the AXI Timer 0 peripheral.
+ * XPAR_INTC_0_EMACLITE_0_VEC_ID  -  for the Ethernet lite peripheral.
+ * XPAR_INTC_0_GPIO_1_VEC_ID      -  for the button inputs.
+ *
+ *
+ * pxHandler:
+ *
+ * A pointer to the interrupt handler function itself.  This must be a void
+ * function that takes a (void *) parameter.
+ *
+ *
+ * pvCallBackRef:
+ *
+ * The parameter passed into the handler function.  In many cases this will not
+ * be used and can be NULL.  Some times it is used to pass in a reference to
+ * the peripheral instance variable, so it can be accessed from inside the
+ * handler function.
+ *
+ *
+ * pdPASS is returned if the function executes successfully.  Any other value
+ * being returned indicates that the function did not execute correctly.
+ */
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
+
+
+/*
+ * Enables the interrupt, within the interrupt controller, for the peripheral
+ * specified by the ucInterruptID parameter.
+ *
+ * ucInterruptID:
+ *
+ * The ID of the peripheral that will have its interrupt enabled in the
+ * interrupt controller.  Peripheral IDs are defined in the xparameters.h header
+ * file, which is itself part of the BSP project.  For example, in the official
+ * demo application for this port, xparameters.h defines the following IDs for
+ * the four possible interrupt sources:
+ *
+ * XPAR_INTC_0_UARTLITE_1_VEC_ID  -  for the UARTlite peripheral.
+ * XPAR_INTC_0_TMRCTR_0_VEC_ID    -  for the AXI Timer 0 peripheral.
+ * XPAR_INTC_0_EMACLITE_0_VEC_ID  -  for the Ethernet lite peripheral.
+ * XPAR_INTC_0_GPIO_1_VEC_ID      -  for the button inputs.
+ *
+ */
+void vPortEnableInterrupt( uint8_t ucInterruptID );
+
+/*
+ * Disables the interrupt, within the interrupt controller, for the peripheral
+ * specified by the ucInterruptID parameter.
+ *
+ * ucInterruptID:
+ *
+ * The ID of the peripheral that will have its interrupt disabled in the
+ * interrupt controller.  Peripheral IDs are defined in the xparameters.h header
+ * file, which is itself part of the BSP project.  For example, in the official
+ * demo application for this port, xparameters.h defines the following IDs for
+ * the four possible interrupt sources:
+ *
+ * XPAR_INTC_0_UARTLITE_1_VEC_ID  -  for the UARTlite peripheral.
+ * XPAR_INTC_0_TMRCTR_0_VEC_ID    -  for the AXI Timer 0 peripheral.
+ * XPAR_INTC_0_EMACLITE_0_VEC_ID  -  for the Ethernet lite peripheral.
+ * XPAR_INTC_0_GPIO_1_VEC_ID      -  for the button inputs.
+ *
+ */
+void vPortDisableInterrupt( uint8_t ucInterruptID );
+
+/*
+ * This is an application defined callback function used to install the tick
+ * interrupt handler.  It is provided as an application callback because the
+ * kernel will run on lots of different MicroBlaze and FPGA configurations - not
+ * all of which will have the same timer peripherals defined or available.  This
+ * example uses the AXI Timer 0.  If that is available on your hardware platform
+ * then this example callback implementation should not require modification.
+ * The name of the interrupt handler that should be installed is vPortTickISR(),
+ * which the function below declares as an extern.
+ */
+void vApplicationSetupTimerInterrupt( void );
+
+/*
+ * This is an application defined callback function used to clear whichever
+ * interrupt was installed by the the vApplicationSetupTimerInterrupt() callback
+ * function - in this case the interrupt generated by the AXI timer.  It is
+ * provided as an application callback because the kernel will run on lots of
+ * different MicroBlaze and FPGA configurations - not all of which will have the
+ * same timer peripherals defined or available.  This example uses the AXI Timer 0.
+ * If that is available on your hardware platform then this example callback
+ * implementation should not require modification provided the example definition
+ * of vApplicationSetupTimerInterrupt() is also not modified.
+ */
+void vApplicationClearTimerInterrupt( void );
+
+/*
+ * vPortExceptionsInstallHandlers() is only available when the MicroBlaze
+ * is configured to include exception functionality, and
+ * configINSTALL_EXCEPTION_HANDLERS is set to 1 in FreeRTOSConfig.h.
+ *
+ * vPortExceptionsInstallHandlers() installs the FreeRTOS exception handler
+ * for every possible exception cause.
+ *
+ * vPortExceptionsInstallHandlers() can be called explicitly from application
+ * code.  After that is done, the default FreeRTOS exception handler that will
+ * have been installed can be replaced for any specific exception cause by using
+ * the standard Xilinx library function microblaze_register_exception_handler().
+ *
+ * If vPortExceptionsInstallHandlers() is not called explicitly by the
+ * application, it will be called automatically by the kernel the first time
+ * xPortInstallInterruptHandler() is called.  At that time, any exception
+ * handlers that may have already been installed will be replaced.
+ *
+ * See the description of vApplicationExceptionRegisterDump() for information
+ * on the processing performed by the FreeRTOS exception handler.
+ */
+void vPortExceptionsInstallHandlers( void );
+
+/*
+ * The FreeRTOS exception handler fills an xPortRegisterDump structure (defined
+ * in portmacro.h) with the MicroBlaze context, as it was at the time the
+ * exception occurred.  The exception handler then calls
+ * vApplicationExceptionRegisterDump(), passing in the completed
+ * xPortRegisterDump structure as its parameter.
+ *
+ * The FreeRTOS kernel provides its own implementation of
+ * vApplicationExceptionRegisterDump(), but the kernel provided implementation
+ * is declared as being 'weak'.  The weak definition allows the application
+ * writer to provide their own implementation, should they wish to use the
+ * register dump information.  For example, an implementation could be provided
+ * that wrote the register dump data to a display, or a UART port.
+ */
+void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump );
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c
new file mode 100644
index 0000000..62d3bb1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c
@@ -0,0 +1,460 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MicroBlaze port.
+ *----------------------------------------------------------*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include 
+
+/* Hardware includes. */
+#include 
+#include 
+#include 
+
+/* Tasks are started with a critical section nesting of 0 - however, prior to
+the scheduler being commenced interrupts should not be enabled, so the critical
+nesting variable is initialised to a non-zero value. */
+#define portINITIAL_NESTING_VALUE	( 0xff )
+
+/* The bit within the MSR register that enabled/disables interrupts and
+exceptions respectively. */
+#define portMSR_IE					( 0x02U )
+#define portMSR_EE					( 0x100U )
+
+/* If the floating point unit is included in the MicroBlaze build, then the
+FSR register is saved as part of the task context.  portINITIAL_FSR is the value
+given to the FSR register when the initial context is set up for a task being
+created. */
+#define portINITIAL_FSR				( 0U )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the interrupt controller instance.
+ */
+static int32_t prvInitialiseInterruptController( void );
+
+/* Ensure the interrupt controller instance variable is initialised before it is
+ * used, and that the initialisation only happens once.
+ */
+static int32_t prvEnsureInterruptControllerIsInitialised( void );
+
+/*-----------------------------------------------------------*/
+
+/* Counts the nesting depth of calls to portENTER_CRITICAL().  Each task
+maintains its own count, so this variable is saved as part of the task
+context. */
+volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
+
+/* This port uses a separate stack for interrupts.  This prevents the stack of
+every task needing to be large enough to hold an entire interrupt stack on top
+of the task stack. */
+uint32_t *pulISRStack;
+
+/* If an interrupt requests a context switch, then ulTaskSwitchRequested will
+get set to 1.  ulTaskSwitchRequested is inspected just before the main interrupt
+handler exits.  If, at that time, ulTaskSwitchRequested is set to 1, the kernel
+will call vTaskSwitchContext() to ensure the task that runs immediately after
+the interrupt exists is the highest priority task that is able to run.  This is
+an unusual mechanism, but is used for this port because a single interrupt can
+cause the servicing of multiple peripherals - and it is inefficient to call
+vTaskSwitchContext() multiple times as each peripheral is serviced. */
+volatile uint32_t ulTaskSwitchRequested = 0UL;
+
+/* The instance of the interrupt controller used by this port.  This is required
+by the Xilinx library API functions. */
+static XIntc xInterruptControllerInstance;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been made.
+ *
+ * See the portable.h header file.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+extern void *_SDA2_BASE_, *_SDA_BASE_;
+const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
+const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
+extern void _start1( void );
+
+	/* Place a few bytes of known values on the bottom of the stack.
+	This is essential for the Microblaze port and these lines must
+	not be omitted. */
+	*pxTopOfStack = ( StackType_t ) 0x00000000;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00000000;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00000000;
+	pxTopOfStack--;
+
+	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+		/* The FSR value placed in the initial task context is just 0. */
+		*pxTopOfStack = portINITIAL_FSR;
+		pxTopOfStack--;
+	#endif
+
+	/* The MSR value placed in the initial task context should have interrupts
+	disabled.  Each task will enable interrupts automatically when it enters
+	the running state for the first time. */
+	*pxTopOfStack = mfmsr() & ~portMSR_IE;
+
+	#if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
+	{
+		/* Ensure exceptions are enabled for the task. */
+		*pxTopOfStack |= portMSR_EE;
+	}
+	#endif
+
+	pxTopOfStack--;
+
+	/* First stack an initial value for the critical section nesting.  This
+	is initialised to zero. */
+	*pxTopOfStack = ( StackType_t ) 0x00;
+
+	/* R0 is always zero. */
+	/* R1 is the SP. */
+
+	/* Place an initial value for all the general purpose registers. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) ulR2;	/* R2 - read only small data area. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x03;	/* R3 - return values and temporaries. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x04;	/* R4 - return values and temporaries. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
+
+	#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06;	/* R6 - other parameters and temporaries. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07;	/* R7 - other parameters and temporaries. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) NULL;	/* R8 - other parameters and temporaries. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09;	/* R9 - other parameters and temporaries. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x0a;	/* R10 - other parameters and temporaries. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x0b;	/* R11 - temporaries. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x0c;	/* R12 - temporaries. */
+		pxTopOfStack--;
+	#else
+		pxTopOfStack-= 8;
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) ulR13;	/* R13 - read/write small data area. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;	/* R14 - return address for interrupt. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) _start1;	/* R15 - return address for subroutine. */
+
+	#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10;	/* R16 - return address for trap (debugger). */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11;	/* R17 - return address for exceptions, if configured. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x12;	/* R18 - reserved for assembler and compiler temporaries. */
+		pxTopOfStack--;
+	#else
+		pxTopOfStack -= 4;
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) 0x00;	/* R19 - must be saved across function calls. Callee-save.  Seems to be interpreted as the frame pointer. */
+
+	#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x14;	/* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save.  Not used by FreeRTOS. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x15;	/* R21 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x16;	/* R22 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x17;	/* R23 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x18;	/* R24 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x19;	/* R25 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1a;	/* R26 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1b;	/* R27 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1c;	/* R28 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1d;	/* R29 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1e;	/* R30 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1f;	/* R31 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+	#else
+		pxTopOfStack -= 13;
+	#endif
+
+	/* Return a pointer to the top of the stack that has been generated so this
+	can	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void ( vPortStartFirstTask )( void );
+extern uint32_t _stack[];
+
+	/* Setup the hardware to generate the tick.  Interrupts are disabled when
+	this function is called.
+
+	This port uses an application defined callback function to install the tick
+	interrupt handler because the kernel will run on lots of different
+	MicroBlaze and FPGA configurations - not all of	which will have the same
+	timer peripherals defined or available.  An example definition of
+	vApplicationSetupTimerInterrupt() is provided in the official demo
+	application that accompanies this port. */
+	vApplicationSetupTimerInterrupt();
+
+	/* Reuse the stack from main() as the stack for the interrupts/exceptions. */
+	pulISRStack = ( uint32_t * ) _stack;
+
+	/* Ensure there is enough space for the functions called from the interrupt
+	service routines to write back into the stack frame of the caller. */
+	pulISRStack -= 2;
+
+	/* Restore the context of the first task that is going to run.  From here
+	on, the created tasks will be executing. */
+	vPortStartFirstTask();
+
+	/* Should not get here as the tasks are now running! */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.
+ */
+void vPortYield( void )
+{
+extern void VPortYieldASM( void );
+
+	/* Perform the context switch in a critical section to assure it is
+	not interrupted by the tick ISR.  It is not a problem to do this as
+	each task maintains its own interrupt status. */
+	portENTER_CRITICAL();
+	{
+		/* Jump directly to the yield function to ensure there is no
+		compiler generated prologue code. */
+		asm volatile (	"bralid r14, VPortYieldASM		\n\t" \
+						"or r0, r0, r0					\n\t" );
+	}
+	portEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnableInterrupt( uint8_t ucInterruptID )
+{
+int32_t lReturn;
+
+	/* An API function is provided to enable an interrupt in the interrupt
+	controller because the interrupt controller instance variable is private
+	to this file. */
+	lReturn = prvEnsureInterruptControllerIsInitialised();
+	if( lReturn == pdPASS )
+	{
+		/* Critical section protects read/modify/writer operation inside
+		XIntc_Enable(). */
+		portENTER_CRITICAL();
+		{
+			XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
+		}
+		portEXIT_CRITICAL();
+	}
+
+	configASSERT( lReturn );
+}
+/*-----------------------------------------------------------*/
+
+void vPortDisableInterrupt( uint8_t ucInterruptID )
+{
+int32_t lReturn;
+
+	/* An API function is provided to disable an interrupt in the interrupt
+	controller because the interrupt controller instance variable is private
+	to this file. */
+	lReturn = prvEnsureInterruptControllerIsInitialised();
+
+	if( lReturn == pdPASS )
+	{
+		XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );
+	}
+
+	configASSERT( lReturn );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
+{
+int32_t lReturn;
+
+	/* An API function is provided to install an interrupt handler because the
+	interrupt controller instance variable is private to this file. */
+
+	lReturn = prvEnsureInterruptControllerIsInitialised();
+
+	if( lReturn == pdPASS )
+	{
+		lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );
+	}
+
+	if( lReturn == XST_SUCCESS )
+	{
+		lReturn = pdPASS;
+	}
+
+	configASSERT( lReturn == pdPASS );
+
+	return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+static int32_t prvEnsureInterruptControllerIsInitialised( void )
+{
+static int32_t lInterruptControllerInitialised = pdFALSE;
+int32_t lReturn;
+
+	/* Ensure the interrupt controller instance variable is initialised before
+	it is used, and that the initialisation only happens once. */
+	if( lInterruptControllerInitialised != pdTRUE )
+	{
+		lReturn = prvInitialiseInterruptController();
+
+		if( lReturn == pdPASS )
+		{
+			lInterruptControllerInitialised = pdTRUE;
+		}
+	}
+	else
+	{
+		lReturn = pdPASS;
+	}
+
+	return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Handler for the timer interrupt.  This is the handler that the application
+ * defined callback function vApplicationSetupTimerInterrupt() should install.
+ */
+void vPortTickISR( void *pvUnused )
+{
+extern void vApplicationClearTimerInterrupt( void );
+
+	/* Ensure the unused parameter does not generate a compiler warning. */
+	( void ) pvUnused;
+
+	/* This port uses an application defined callback function to clear the tick
+	interrupt because the kernel will run on lots of different MicroBlaze and
+	FPGA configurations - not all of which will have the same timer peripherals
+	defined or available.  An example definition of
+	vApplicationClearTimerInterrupt() is provided in the official demo
+	application that accompanies this port. */
+	vApplicationClearTimerInterrupt();
+
+	/* Increment the RTOS tick - this might cause a task to unblock. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		/* Force vTaskSwitchContext() to be called as the interrupt exits. */
+		ulTaskSwitchRequested = 1;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static int32_t prvInitialiseInterruptController( void )
+{
+int32_t lStatus;
+
+	lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
+
+	if( lStatus == XST_SUCCESS )
+	{
+		/* Initialise the exception table. */
+		Xil_ExceptionInit();
+
+	    /* Service all pending interrupts each time the handler is entered. */
+	    XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
+
+	    /* Install exception handlers if the MicroBlaze is configured to handle
+	    exceptions, and the application defined constant
+	    configINSTALL_EXCEPTION_HANDLERS is set to 1. */
+		#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
+	    {
+	    	vPortExceptionsInstallHandlers();
+	    }
+		#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
+
+		/* Start the interrupt controller.  Interrupts are enabled when the
+		scheduler starts. */
+		lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
+
+		if( lStatus == XST_SUCCESS )
+		{
+			lStatus = pdPASS;
+		}
+		else
+		{
+			lStatus = pdFAIL;
+		}
+	}
+
+	configASSERT( lStatus == pdPASS );
+
+	return lStatus;
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port_exceptions.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port_exceptions.c
new file mode 100644
index 0000000..33380c7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port_exceptions.c
@@ -0,0 +1,282 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Hardware includes. */
+#include 
+#include 
+
+/* The Xilinx library defined exception entry point stacks a number of
+registers.  These definitions are offsets from the stack pointer to the various
+stacked register values. */
+#define portexR3_STACK_OFFSET	4
+#define portexR4_STACK_OFFSET	5
+#define portexR5_STACK_OFFSET	6
+#define portexR6_STACK_OFFSET	7
+#define portexR7_STACK_OFFSET	8
+#define portexR8_STACK_OFFSET	9
+#define portexR9_STACK_OFFSET	10
+#define portexR10_STACK_OFFSET	11
+#define portexR11_STACK_OFFSET	12
+#define portexR12_STACK_OFFSET	13
+#define portexR15_STACK_OFFSET	16
+#define portexR18_STACK_OFFSET  19
+#define portexMSR_STACK_OFFSET	20
+#define portexR19_STACK_OFFSET  -1
+
+/* This is defined to equal the size, in bytes, of the stack frame generated by
+the Xilinx standard library exception entry point.  It is required to determine
+the stack pointer value prior to the exception being entered. */
+#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL
+
+/* The number of bytes a MicroBlaze instruction consumes. */
+#define portexINSTRUCTION_SIZE	4
+
+/* Exclude this entire file if the MicroBlaze is not configured to handle
+exceptions, or the application defined configuration constant
+configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
+#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
+
+/* This variable is set in the exception entry code, before
+vPortExceptionHandler is called. */
+uint32_t *pulStackPointerOnFunctionEntry = NULL;
+
+/* This is the structure that is filled with the MicroBlaze context as it
+existed immediately prior to the exception occurrence.  A pointer to this
+structure is passed into the vApplicationExceptionRegisterDump() callback
+function, if one is defined. */
+static xPortRegisterDump xRegisterDump;
+
+/* This is the FreeRTOS exception handler that is installed for all exception
+types.  It is called from vPortExceptionHanlderEntry() - which is itself defined
+in portasm.S. */
+void vPortExceptionHandler( void *pvExceptionID );
+extern void vPortExceptionHandlerEntry( void *pvExceptionID );
+
+/*-----------------------------------------------------------*/
+
+/* vApplicationExceptionRegisterDump() is a callback function that the
+application can optionally define to receive a populated xPortRegisterDump
+structure.  If the application chooses not to define a version of
+vApplicationExceptionRegisterDump() then this weekly defined default
+implementation will be called instead. */
+extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak));
+void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )
+{
+	( void ) xRegisterDump;
+
+	for( ;; )
+	{
+		portNOP();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExceptionHandler( void *pvExceptionID )
+{
+extern void *pxCurrentTCB;
+
+	/* Fill an xPortRegisterDump structure with the MicroBlaze context as it
+	was immediately before the exception occurrence. */
+
+	/* First fill in the name and handle of the task that was in the Running
+	state when the exception occurred. */
+	xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
+	xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
+
+	configASSERT( pulStackPointerOnFunctionEntry );
+
+	/* Obtain the values of registers that were stacked prior to this function
+	being called, and may have changed since they were stacked. */
+	xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
+	xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
+	xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
+	xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
+	xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
+	xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
+	xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
+	xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
+	xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
+	xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
+	xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
+	xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
+	xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
+	xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
+
+	/* Obtain the value of all other registers. */
+	xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
+	xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
+	xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
+	xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
+	xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
+	xRegisterDump.ulR20 = mfgpr( R20 );
+	xRegisterDump.ulR21 = mfgpr( R21 );
+	xRegisterDump.ulR22 = mfgpr( R22 );
+	xRegisterDump.ulR23 = mfgpr( R23 );
+	xRegisterDump.ulR24 = mfgpr( R24 );
+	xRegisterDump.ulR25 = mfgpr( R25 );
+	xRegisterDump.ulR26 = mfgpr( R26 );
+	xRegisterDump.ulR27 = mfgpr( R27 );
+	xRegisterDump.ulR28 = mfgpr( R28 );
+	xRegisterDump.ulR29 = mfgpr( R29 );
+	xRegisterDump.ulR30 = mfgpr( R30 );
+	xRegisterDump.ulR31 = mfgpr( R31 );
+	xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
+	xRegisterDump.ulEAR = mfear();
+	xRegisterDump.ulESR = mfesr();
+	xRegisterDump.ulEDR = mfedr();
+
+	/* Move the saved program counter back to the instruction that was executed
+	when the exception occurred.  This is only valid for certain types of
+	exception. */
+	xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
+
+	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+	{
+		xRegisterDump.ulFSR = mffsr();
+	}
+	#else
+	{
+		xRegisterDump.ulFSR = 0UL;
+	}
+	#endif
+
+	/* Also fill in a string that describes what type of exception this is.
+	The string uses the same ID names as defined in the MicroBlaze standard
+	library exception header files. */
+	switch( ( uint32_t ) pvExceptionID )
+	{
+		case XEXC_ID_FSL :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
+				break;
+
+		case XEXC_ID_UNALIGNED_ACCESS :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
+				break;
+
+		case XEXC_ID_ILLEGAL_OPCODE :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
+				break;
+
+		case XEXC_ID_M_AXI_I_EXCEPTION :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
+				break;
+
+		case XEXC_ID_M_AXI_D_EXCEPTION :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
+				break;
+
+		case XEXC_ID_DIV_BY_ZERO :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
+				break;
+
+		case XEXC_ID_STACK_VIOLATION :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
+				break;
+
+		#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+
+			case XEXC_ID_FPU :
+						xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
+						break;
+
+		#endif /* XPAR_MICROBLAZE_USE_FPU */
+	}
+
+	/* vApplicationExceptionRegisterDump() is a callback function that the
+	application can optionally define to receive the populated xPortRegisterDump
+	structure.  If the application chooses not to define a version of
+	vApplicationExceptionRegisterDump() then the weekly defined default
+	implementation within this file will be called instead. */
+	vApplicationExceptionRegisterDump( &xRegisterDump );
+
+	/* Must not attempt to leave this function! */
+	for( ;; )
+	{
+		portNOP();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExceptionsInstallHandlers( void )
+{
+static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
+
+	if( ulHandlersAlreadyInstalled == pdFALSE )
+	{
+		ulHandlersAlreadyInstalled = pdTRUE;
+
+		#if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
+			microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
+		#endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
+
+		#if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
+		#endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
+		#endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
+		#endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
+		#endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
+		#endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
+		#endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
+		#endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
+		#endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
+
+		microblaze_enable_exceptions();
+	}
+}
+
+/* Exclude the entire file if the MicroBlaze is not configured to handle
+exceptions, or the application defined configuration item
+configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
+#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV9/portasm.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV9/portasm.S
new file mode 100644
index 0000000..5d6b4b8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV9/portasm.S
@@ -0,0 +1,328 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/* Xilinx library includes. */
+#include "microblaze_exceptions_g.h"
+#include "xparameters.h"
+
+/* The context is oversized to allow functions called from the ISR to write
+back into the caller stack. */
+#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+	#define portCONTEXT_SIZE 136
+	#define portMINUS_CONTEXT_SIZE -136
+#else
+	#define portCONTEXT_SIZE 132
+	#define portMINUS_CONTEXT_SIZE -132
+#endif
+
+/* Offsets from the stack pointer at which saved registers are placed. */
+#define portR31_OFFSET	4
+#define portR30_OFFSET	8
+#define portR29_OFFSET	12
+#define portR28_OFFSET	16
+#define portR27_OFFSET	20
+#define portR26_OFFSET	24
+#define portR25_OFFSET	28
+#define portR24_OFFSET	32
+#define portR23_OFFSET	36
+#define portR22_OFFSET	40
+#define portR21_OFFSET	44
+#define portR20_OFFSET	48
+#define portR19_OFFSET	52
+#define portR18_OFFSET	56
+#define portR17_OFFSET	60
+#define portR16_OFFSET	64
+#define portR15_OFFSET	68
+#define portR14_OFFSET	72
+#define portR13_OFFSET	76
+#define portR12_OFFSET	80
+#define portR11_OFFSET	84
+#define portR10_OFFSET	88
+#define portR9_OFFSET	92
+#define portR8_OFFSET	96
+#define portR7_OFFSET	100
+#define portR6_OFFSET	104
+#define portR5_OFFSET	108
+#define portR4_OFFSET	112
+#define portR3_OFFSET	116
+#define portR2_OFFSET	120
+#define portCRITICAL_NESTING_OFFSET 124
+#define portMSR_OFFSET 128
+#define portFSR_OFFSET 132
+
+	.extern pxCurrentTCB
+	.extern XIntc_DeviceInterruptHandler
+	.extern vTaskSwitchContext
+	.extern uxCriticalNesting
+	.extern pulISRStack
+	.extern ulTaskSwitchRequested
+	.extern vPortExceptionHandler
+	.extern pulStackPointerOnFunctionEntry
+
+	.global _interrupt_handler
+	.global VPortYieldASM
+	.global vPortStartFirstTask
+	.global vPortExceptionHandlerEntry
+
+
+.macro portSAVE_CONTEXT
+
+	/* Make room for the context on the stack. */
+	addik r1, r1, portMINUS_CONTEXT_SIZE
+
+	/* Stack general registers. */
+	swi r31, r1, portR31_OFFSET
+	swi r30, r1, portR30_OFFSET
+	swi r29, r1, portR29_OFFSET
+	swi r28, r1, portR28_OFFSET
+	swi r27, r1, portR27_OFFSET
+	swi r26, r1, portR26_OFFSET
+	swi r25, r1, portR25_OFFSET
+	swi r24, r1, portR24_OFFSET
+	swi r23, r1, portR23_OFFSET
+	swi r22, r1, portR22_OFFSET
+	swi r21, r1, portR21_OFFSET
+	swi r20, r1, portR20_OFFSET
+	swi r19, r1, portR19_OFFSET
+	swi r18, r1, portR18_OFFSET
+	swi r17, r1, portR17_OFFSET
+	swi r16, r1, portR16_OFFSET
+	swi r15, r1, portR15_OFFSET
+	/* R14 is saved later as it needs adjustment if a yield is performed. */
+	swi r13, r1, portR13_OFFSET
+	swi r12, r1, portR12_OFFSET
+	swi r11, r1, portR11_OFFSET
+	swi r10, r1, portR10_OFFSET
+	swi r9, r1, portR9_OFFSET
+	swi r8, r1, portR8_OFFSET
+	swi r7, r1, portR7_OFFSET
+	swi r6, r1, portR6_OFFSET
+	swi r5, r1, portR5_OFFSET
+	swi r4, r1, portR4_OFFSET
+	swi r3, r1, portR3_OFFSET
+	swi r2, r1, portR2_OFFSET
+
+	/* Stack the critical section nesting value. */
+	lwi r18, r0, uxCriticalNesting
+	swi r18, r1, portCRITICAL_NESTING_OFFSET
+
+	/* Stack MSR. */
+	mfs r18, rmsr
+	swi r18, r1, portMSR_OFFSET
+
+	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+		/* Stack FSR. */
+		mfs r18, rfsr
+		swi r18, r1, portFSR_OFFSET
+	#endif
+
+	/* Save the top of stack value to the TCB. */
+	lwi r3, r0, pxCurrentTCB
+	sw	r1, r0, r3
+
+	.endm
+
+.macro portRESTORE_CONTEXT
+
+	/* Load the top of stack value from the TCB. */
+	lwi r18, r0, pxCurrentTCB
+	lw	r1, r0, r18
+
+	/* Restore the general registers. */
+	lwi r31, r1, portR31_OFFSET
+	lwi r30, r1, portR30_OFFSET
+	lwi r29, r1, portR29_OFFSET
+	lwi r28, r1, portR28_OFFSET
+	lwi r27, r1, portR27_OFFSET
+	lwi r26, r1, portR26_OFFSET
+	lwi r25, r1, portR25_OFFSET
+	lwi r24, r1, portR24_OFFSET
+	lwi r23, r1, portR23_OFFSET
+	lwi r22, r1, portR22_OFFSET
+	lwi r21, r1, portR21_OFFSET
+	lwi r20, r1, portR20_OFFSET
+	lwi r19, r1, portR19_OFFSET
+	lwi r17, r1, portR17_OFFSET
+	lwi r16, r1, portR16_OFFSET
+	lwi r15, r1, portR15_OFFSET
+	lwi r14, r1, portR14_OFFSET
+	lwi r13, r1, portR13_OFFSET
+	lwi r12, r1, portR12_OFFSET
+	lwi r11, r1, portR11_OFFSET
+	lwi r10, r1, portR10_OFFSET
+	lwi r9, r1, portR9_OFFSET
+	lwi r8, r1, portR8_OFFSET
+	lwi r7, r1, portR7_OFFSET
+	lwi r6, r1, portR6_OFFSET
+	lwi r5, r1, portR5_OFFSET
+	lwi r4, r1, portR4_OFFSET
+	lwi r3, r1, portR3_OFFSET
+	lwi r2, r1, portR2_OFFSET
+
+	/* Reload the rmsr from the stack. */
+	lwi r18, r1, portMSR_OFFSET
+	mts rmsr, r18
+
+	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+		/* Reload the FSR from the stack. */
+		lwi r18, r1, portFSR_OFFSET
+		mts rfsr, r18
+	#endif
+
+	/* Load the critical nesting value. */
+	lwi r18, r1, portCRITICAL_NESTING_OFFSET
+	swi r18, r0, uxCriticalNesting
+
+	/* Test the critical nesting value.  If it is non zero then the task last
+	exited the running state using a yield.  If it is zero, then the task
+	last exited the running state through an interrupt. */
+	xori r18, r18, 0
+	bnei r18, exit_from_yield
+
+	/* r18 was being used as a temporary.  Now restore its true value from the
+	stack. */
+	lwi r18, r1, portR18_OFFSET
+
+	/* Remove the stack frame. */
+	addik r1, r1, portCONTEXT_SIZE
+
+	/* Return using rtid so interrupts are re-enabled as this function is
+	exited. */
+	rtid r14, 0
+	or r0, r0, r0
+
+	.endm
+
+/* This function is used to exit portRESTORE_CONTEXT() if the task being
+returned to last left the Running state by calling taskYIELD() (rather than
+being preempted by an interrupt). */
+	.text
+	.align  4
+exit_from_yield:
+
+	/* r18 was being used as a temporary.  Now restore its true value from the
+	stack. */
+	lwi r18, r1, portR18_OFFSET
+
+	/* Remove the stack frame. */
+	addik r1, r1, portCONTEXT_SIZE
+
+	/* Return to the task. */
+	rtsd r14, 0
+	or r0, r0, r0
+
+
+	.text
+	.align  4
+_interrupt_handler:
+
+	portSAVE_CONTEXT
+
+	/* Stack the return address. */
+	swi r14, r1, portR14_OFFSET
+
+	/* Switch to the ISR stack. */
+	lwi r1, r0, pulISRStack
+
+	/* The parameter to the interrupt handler. */
+	ori r5, r0, configINTERRUPT_CONTROLLER_TO_USE
+
+	/* Execute any pending interrupts. */
+	bralid r15, XIntc_DeviceInterruptHandler
+	or r0, r0, r0
+
+	/* See if a new task should be selected to execute. */
+	lwi r18, r0, ulTaskSwitchRequested
+	or r18, r18, r0
+
+	/* If ulTaskSwitchRequested is already zero, then jump straight to
+	restoring the task that is already in the Running state. */
+	beqi r18, task_switch_not_requested
+
+	/* Set ulTaskSwitchRequested back to zero as a task switch is about to be
+	performed. */
+	swi r0, r0, ulTaskSwitchRequested
+
+	/* ulTaskSwitchRequested was not 0 when tested.  Select the next task to
+	execute. */
+	bralid r15, vTaskSwitchContext
+	or r0, r0, r0
+
+task_switch_not_requested:
+
+	/* Restore the context of the next task scheduled to execute. */
+	portRESTORE_CONTEXT
+
+
+	.text
+	.align  4
+VPortYieldASM:
+
+	portSAVE_CONTEXT
+
+	/* Modify the return address so a return is done to the instruction after
+	the call to VPortYieldASM. */
+	addi r14, r14, 8
+	swi r14, r1, portR14_OFFSET
+
+	/* Switch to use the ISR stack. */
+	lwi r1, r0, pulISRStack
+
+	/* Select the next task to execute. */
+	bralid r15, vTaskSwitchContext
+	or r0, r0, r0
+
+	/* Restore the context of the next task scheduled to execute. */
+	portRESTORE_CONTEXT
+
+	.text
+	.align  4
+vPortStartFirstTask:
+
+	portRESTORE_CONTEXT
+
+
+
+#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
+
+	.text
+	.align 4
+vPortExceptionHandlerEntry:
+
+	/* Take a copy of the stack pointer before vPortExecptionHandler is called,
+	storing its value prior to the function stack frame being created. */
+	swi r1, r0, pulStackPointerOnFunctionEntry
+	bralid r15, vPortExceptionHandler
+	or r0, r0, r0
+
+#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV9/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV9/portmacro.h
new file mode 100644
index 0000000..f0e6dcf
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/MicroBlazeV9/portmacro.h
@@ -0,0 +1,369 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* BSP includes. */
+#include 
+#include 
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros and functions. */
+void microblaze_disable_interrupts( void );
+void microblaze_enable_interrupts( void );
+#define portDISABLE_INTERRUPTS()	microblaze_disable_interrupts()
+#define portENABLE_INTERRUPTS()		microblaze_enable_interrupts()
+/*-----------------------------------------------------------*/
+
+/* Critical section macros. */
+void vPortEnterCritical( void );
+void vPortExitCritical( void );
+#define portENTER_CRITICAL()		{																\
+										extern volatile UBaseType_t uxCriticalNesting;				\
+										microblaze_disable_interrupts();							\
+										uxCriticalNesting++;										\
+									}
+
+#define portEXIT_CRITICAL()			{																\
+										extern volatile UBaseType_t uxCriticalNesting;				\
+										/* Interrupts are disabled, so we can */					\
+										/* access the variable directly. */							\
+										uxCriticalNesting--;										\
+										if( uxCriticalNesting == 0 )								\
+										{															\
+											/* The nesting has unwound and we 						\
+											can enable interrupts again. */							\
+											portENABLE_INTERRUPTS();								\
+										}															\
+									}
+
+/*-----------------------------------------------------------*/
+
+/* The yield macro maps directly to the vPortYield() function. */
+void vPortYield( void );
+#define portYIELD() vPortYield()
+
+/* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead
+sets a flag to say that a yield has been requested.  The interrupt exit code
+then checks this flag, and calls vTaskSwitchContext() before restoring a task
+context, if the flag is not false.  This is done to prevent multiple calls to
+vTaskSwitchContext() being made from a single interrupt, as a single interrupt
+can result in multiple peripherals being serviced. */
+extern volatile uint32_t ulTaskSwitchRequested;
+#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1
+
+#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+	/* Generic helper function. */
+	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+	{
+	uint8_t ucReturn;
+
+		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
+		return ucReturn;
+	}
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			4
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* The following structure is used by the FreeRTOS exception handler.  It is
+filled with the MicroBlaze context as it was at the time the exception occurred.
+This is done as an aid to debugging exception occurrences. */
+typedef struct PORT_REGISTER_DUMP
+{
+	/* The following structure members hold the values of the MicroBlaze
+	registers at the time the exception was raised. */
+	uint32_t ulR1_SP;
+	uint32_t ulR2_small_data_area;
+	uint32_t ulR3;
+	uint32_t ulR4;
+	uint32_t ulR5;
+	uint32_t ulR6;
+	uint32_t ulR7;
+	uint32_t ulR8;
+	uint32_t ulR9;
+	uint32_t ulR10;
+	uint32_t ulR11;
+	uint32_t ulR12;
+	uint32_t ulR13_read_write_small_data_area;
+	uint32_t ulR14_return_address_from_interrupt;
+	uint32_t ulR15_return_address_from_subroutine;
+	uint32_t ulR16_return_address_from_trap;
+	uint32_t ulR17_return_address_from_exceptions; /* The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. */
+	uint32_t ulR18;
+	uint32_t ulR19;
+	uint32_t ulR20;
+	uint32_t ulR21;
+	uint32_t ulR22;
+	uint32_t ulR23;
+	uint32_t ulR24;
+	uint32_t ulR25;
+	uint32_t ulR26;
+	uint32_t ulR27;
+	uint32_t ulR28;
+	uint32_t ulR29;
+	uint32_t ulR30;
+	uint32_t ulR31;
+	uint32_t ulPC;
+	uint32_t ulESR;
+	uint32_t ulMSR;
+	uint32_t ulEAR;
+	uint32_t ulFSR;
+	uint32_t ulEDR;
+
+	/* A human readable description of the exception cause.  The strings used
+	are the same as the #define constant names found in the
+	microblaze_exceptions_i.h header file */
+	int8_t *pcExceptionCause;
+
+	/* The human readable name of the task that was running at the time the
+	exception occurred.  This is the name that was given to the task when the
+	task was created using the FreeRTOS xTaskCreate() API function. */
+	char *pcCurrentTaskName;
+
+	/* The handle of the task that was running a the time the exception
+	occurred. */
+	void * xCurrentTaskHandle;
+
+} xPortRegisterDump;
+
+
+/*
+ * Installs pxHandler as the interrupt handler for the peripheral specified by
+ * the ucInterruptID parameter.
+ *
+ * ucInterruptID:
+ *
+ * The ID of the peripheral that will have pxHandler assigned as its interrupt
+ * handler.  Peripheral IDs are defined in the xparameters.h header file, which
+ * is itself part of the BSP project.  For example, in the official demo
+ * application for this port, xparameters.h defines the following IDs for the
+ * four possible interrupt sources:
+ *
+ * XPAR_INTC_0_UARTLITE_1_VEC_ID  -  for the UARTlite peripheral.
+ * XPAR_INTC_0_TMRCTR_0_VEC_ID    -  for the AXI Timer 0 peripheral.
+ * XPAR_INTC_0_EMACLITE_0_VEC_ID  -  for the Ethernet lite peripheral.
+ * XPAR_INTC_0_GPIO_1_VEC_ID      -  for the button inputs.
+ *
+ *
+ * pxHandler:
+ *
+ * A pointer to the interrupt handler function itself.  This must be a void
+ * function that takes a (void *) parameter.
+ *
+ *
+ * pvCallBackRef:
+ *
+ * The parameter passed into the handler function.  In many cases this will not
+ * be used and can be NULL.  Some times it is used to pass in a reference to
+ * the peripheral instance variable, so it can be accessed from inside the
+ * handler function.
+ *
+ *
+ * pdPASS is returned if the function executes successfully.  Any other value
+ * being returned indicates that the function did not execute correctly.
+ */
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
+
+
+/*
+ * Enables the interrupt, within the interrupt controller, for the peripheral
+ * specified by the ucInterruptID parameter.
+ *
+ * ucInterruptID:
+ *
+ * The ID of the peripheral that will have its interrupt enabled in the
+ * interrupt controller.  Peripheral IDs are defined in the xparameters.h header
+ * file, which is itself part of the BSP project.  For example, in the official
+ * demo application for this port, xparameters.h defines the following IDs for
+ * the four possible interrupt sources:
+ *
+ * XPAR_INTC_0_UARTLITE_1_VEC_ID  -  for the UARTlite peripheral.
+ * XPAR_INTC_0_TMRCTR_0_VEC_ID    -  for the AXI Timer 0 peripheral.
+ * XPAR_INTC_0_EMACLITE_0_VEC_ID  -  for the Ethernet lite peripheral.
+ * XPAR_INTC_0_GPIO_1_VEC_ID      -  for the button inputs.
+ *
+ */
+void vPortEnableInterrupt( uint8_t ucInterruptID );
+
+/*
+ * Disables the interrupt, within the interrupt controller, for the peripheral
+ * specified by the ucInterruptID parameter.
+ *
+ * ucInterruptID:
+ *
+ * The ID of the peripheral that will have its interrupt disabled in the
+ * interrupt controller.  Peripheral IDs are defined in the xparameters.h header
+ * file, which is itself part of the BSP project.  For example, in the official
+ * demo application for this port, xparameters.h defines the following IDs for
+ * the four possible interrupt sources:
+ *
+ * XPAR_INTC_0_UARTLITE_1_VEC_ID  -  for the UARTlite peripheral.
+ * XPAR_INTC_0_TMRCTR_0_VEC_ID    -  for the AXI Timer 0 peripheral.
+ * XPAR_INTC_0_EMACLITE_0_VEC_ID  -  for the Ethernet lite peripheral.
+ * XPAR_INTC_0_GPIO_1_VEC_ID      -  for the button inputs.
+ *
+ */
+void vPortDisableInterrupt( uint8_t ucInterruptID );
+
+/*
+ * This is an application defined callback function used to install the tick
+ * interrupt handler.  It is provided as an application callback because the
+ * kernel will run on lots of different MicroBlaze and FPGA configurations - not
+ * all of which will have the same timer peripherals defined or available.  This
+ * example uses the AXI Timer 0.  If that is available on your hardware platform
+ * then this example callback implementation should not require modification.
+ * The name of the interrupt handler that should be installed is vPortTickISR(),
+ * which the function below declares as an extern.
+ */
+void vApplicationSetupTimerInterrupt( void );
+
+/*
+ * This is an application defined callback function used to clear whichever
+ * interrupt was installed by the the vApplicationSetupTimerInterrupt() callback
+ * function - in this case the interrupt generated by the AXI timer.  It is
+ * provided as an application callback because the kernel will run on lots of
+ * different MicroBlaze and FPGA configurations - not all of which will have the
+ * same timer peripherals defined or available.  This example uses the AXI Timer 0.
+ * If that is available on your hardware platform then this example callback
+ * implementation should not require modification provided the example definition
+ * of vApplicationSetupTimerInterrupt() is also not modified.
+ */
+void vApplicationClearTimerInterrupt( void );
+
+/*
+ * vPortExceptionsInstallHandlers() is only available when the MicroBlaze
+ * is configured to include exception functionality, and
+ * configINSTALL_EXCEPTION_HANDLERS is set to 1 in FreeRTOSConfig.h.
+ *
+ * vPortExceptionsInstallHandlers() installs the FreeRTOS exception handler
+ * for every possible exception cause.
+ *
+ * vPortExceptionsInstallHandlers() can be called explicitly from application
+ * code.  After that is done, the default FreeRTOS exception handler that will
+ * have been installed can be replaced for any specific exception cause by using
+ * the standard Xilinx library function microblaze_register_exception_handler().
+ *
+ * If vPortExceptionsInstallHandlers() is not called explicitly by the
+ * application, it will be called automatically by the kernel the first time
+ * xPortInstallInterruptHandler() is called.  At that time, any exception
+ * handlers that may have already been installed will be replaced.
+ *
+ * See the description of vApplicationExceptionRegisterDump() for information
+ * on the processing performed by the FreeRTOS exception handler.
+ */
+void vPortExceptionsInstallHandlers( void );
+
+/*
+ * The FreeRTOS exception handler fills an xPortRegisterDump structure (defined
+ * in portmacro.h) with the MicroBlaze context, as it was at the time the
+ * exception occurred.  The exception handler then calls
+ * vApplicationExceptionRegisterDump(), passing in the completed
+ * xPortRegisterDump structure as its parameter.
+ *
+ * The FreeRTOS kernel provides its own implementation of
+ * vApplicationExceptionRegisterDump(), but the kernel provided implementation
+ * is declared as being 'weak'.  The weak definition allows the application
+ * writer to provide their own implementation, should they wish to use the
+ * register dump information.  For example, an implementation could be provided
+ * that wrote the register dump data to a display, or a UART port.
+ */
+void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump );
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/NiosII/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/NiosII/port.c
new file mode 100644
index 0000000..ed6d11a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/NiosII/port.c
@@ -0,0 +1,203 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the NIOS2 port.
+ *----------------------------------------------------------*/
+
+/* Standard Includes. */
+#include 
+#include 
+
+/* Altera includes. */
+#include "sys/alt_irq.h"
+#include "altera_avalon_timer_regs.h"
+#include "priv/alt_irq_table.h"
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Interrupts are enabled. */
+#define portINITIAL_ESTATUS     ( StackType_t ) 0x01 
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * Call back for the alarm function.
+ */
+void vPortSysTickHandler( void * context, alt_u32 id );
+
+/*-----------------------------------------------------------*/
+
+static void prvReadGp( uint32_t *ulValue )
+{
+	asm( "stw gp, (%0)" :: "r"(ulValue) );
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{    
+StackType_t *pxFramePointer = pxTopOfStack - 1;
+StackType_t xGlobalPointer;
+
+    prvReadGp( &xGlobalPointer ); 
+
+    /* End of stack marker. */
+    *pxTopOfStack = 0xdeadbeef;
+    pxTopOfStack--;
+    
+    *pxTopOfStack = ( StackType_t ) pxFramePointer; 
+    pxTopOfStack--;
+    
+    *pxTopOfStack = xGlobalPointer; 
+    
+    /* Space for R23 to R16. */
+    pxTopOfStack -= 9;
+
+    *pxTopOfStack = ( StackType_t ) pxCode; 
+    pxTopOfStack--;
+
+    *pxTopOfStack = portINITIAL_ESTATUS; 
+
+    /* Space for R15 to R5. */    
+    pxTopOfStack -= 12;
+    
+    *pxTopOfStack = ( StackType_t ) pvParameters; 
+
+    /* Space for R3 to R1, muldiv and RA. */
+    pxTopOfStack -= 5;
+    
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+	
+	/* Start the first task. */
+    asm volatile (  " movia r2, restore_sp_from_pxCurrentTCB        \n"
+                    " jmp r2                                          " );
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the NIOS2 port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+void prvSetupTimerInterrupt( void )
+{
+	/* Try to register the interrupt handler. */
+	if ( -EINVAL == alt_irq_register( SYS_CLK_IRQ, 0x0, vPortSysTickHandler ) )
+	{ 
+		/* Failed to install the Interrupt Handler. */
+		asm( "break" );
+	}
+	else
+	{
+		/* Configure SysTick to interrupt at the requested rate. */
+		IOWR_ALTERA_AVALON_TIMER_CONTROL( SYS_CLK_BASE, ALTERA_AVALON_TIMER_CONTROL_STOP_MSK );
+		IOWR_ALTERA_AVALON_TIMER_PERIODL( SYS_CLK_BASE, ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) & 0xFFFF );
+		IOWR_ALTERA_AVALON_TIMER_PERIODH( SYS_CLK_BASE, ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) >> 16 );
+		IOWR_ALTERA_AVALON_TIMER_CONTROL( SYS_CLK_BASE, ALTERA_AVALON_TIMER_CONTROL_CONT_MSK | ALTERA_AVALON_TIMER_CONTROL_START_MSK | ALTERA_AVALON_TIMER_CONTROL_ITO_MSK );	
+	} 
+
+	/* Clear any already pending interrupts generated by the Timer. */
+	IOWR_ALTERA_AVALON_TIMER_STATUS( SYS_CLK_BASE, ~ALTERA_AVALON_TIMER_STATUS_TO_MSK );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSysTickHandler( void * context, alt_u32 id )
+{
+	/* Increment the kernel tick. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+        vTaskSwitchContext();
+	}
+		
+	/* Clear the interrupt. */
+	IOWR_ALTERA_AVALON_TIMER_STATUS( SYS_CLK_BASE, ~ALTERA_AVALON_TIMER_STATUS_TO_MSK );
+}
+/*-----------------------------------------------------------*/
+
+/** This function is a re-implementation of the Altera provided function.
+ * The function is re-implemented to prevent it from enabling an interrupt
+ * when it is registered. Interrupts should only be enabled after the FreeRTOS.org
+ * kernel has its scheduler started so that contexts are saved and switched 
+ * correctly.
+ */
+int alt_irq_register( alt_u32 id, void* context, void (*handler)(void*, alt_u32) )
+{
+	int rc = -EINVAL;  
+	alt_irq_context status;
+
+	if (id < ALT_NIRQ)
+	{
+		/* 
+		 * interrupts are disabled while the handler tables are updated to ensure
+		 * that an interrupt doesn't occur while the tables are in an inconsistent
+		 * state.
+		 */
+	
+		status = alt_irq_disable_all ();
+	
+		alt_irq[id].handler = handler;
+		alt_irq[id].context = context;
+	
+		rc = (handler) ? alt_irq_enable (id): alt_irq_disable (id);
+	
+		/* alt_irq_enable_all(status); This line is removed to prevent the interrupt from being immediately enabled. */
+	}
+    
+	return rc; 
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/NiosII/port_asm.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/NiosII/port_asm.S
new file mode 100644
index 0000000..e8691c5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/NiosII/port_asm.S
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+.extern		vTaskSwitchContext
+	
+.set noat
+
+# Exported to start the first task.
+.globl restore_sp_from_pxCurrentTCB		
+	
+# Entry point for exceptions.
+.section .exceptions.entry, "xa"		
+
+# Save the entire context of a task.
+save_context:
+	addi	ea, ea, -4			# Point to the next instruction.
+	addi	sp,	sp, -116		# Create space on the stack.
+	stw		ra, 0(sp)
+								# Leave a gap for muldiv 0
+	stw		at, 8(sp)		 
+	stw		r2, 12(sp)
+	stw		r3, 16(sp)
+	stw		r4, 20(sp)
+	stw		r5, 24(sp) 
+	stw		r6, 28(sp) 
+	stw		r7, 32(sp) 
+	stw		r8, 36(sp) 
+	stw		r9, 40(sp) 
+	stw		r10, 44(sp)
+	stw		r11, 48(sp)
+	stw		r12, 52(sp)
+	stw		r13, 56(sp)
+	stw		r14, 60(sp)
+	stw		r15, 64(sp)
+	rdctl	r5, estatus 		# Save the eStatus
+	stw		r5, 68(sp)
+	stw		ea, 72(sp)			# Save the PC
+	stw		r16, 76(sp)			# Save the remaining registers
+	stw		r17, 80(sp)
+	stw		r18, 84(sp)
+	stw		r19, 88(sp)
+	stw		r20, 92(sp)
+	stw		r21, 96(sp)
+	stw		r22, 100(sp)
+	stw		r23, 104(sp)
+	stw		gp, 108(sp)
+	stw		fp, 112(sp)
+
+save_sp_to_pxCurrentTCB:
+	movia	et, pxCurrentTCB	# Load the address of the pxCurrentTCB pointer
+	ldw		et, (et)			# Load the value of the pxCurrentTCB pointer
+	stw		sp, (et)			# Store the stack pointer into the top of the TCB
+	
+	.section .exceptions.irqtest, "xa"	
+hw_irq_test:
+	/*
+     * Test to see if the exception was a software exception or caused 
+     * by an external interrupt, and vector accordingly.
+     */
+    rdctl	r4, ipending		# Load the Pending Interrupts indication
+	rdctl	r5, estatus 		# Load the eStatus (enabled interrupts).
+    andi	r2, r5, 1			# Are interrupts enabled globally.
+    beq		r2, zero, soft_exceptions		# Interrupts are not enabled.
+    beq		r4, zero, soft_exceptions		# There are no interrupts triggered.
+
+	.section .exceptions.irqhandler, "xa"
+hw_irq_handler:
+	call	alt_irq_handler					# Call the alt_irq_handler to deliver to the registered interrupt handler.
+
+    .section .exceptions.irqreturn, "xa"
+restore_sp_from_pxCurrentTCB:
+	movia	et, pxCurrentTCB		# Load the address of the pxCurrentTCB pointer
+	ldw		et, (et)				# Load the value of the pxCurrentTCB pointer
+	ldw		sp, (et)				# Load the stack pointer with the top value of the TCB
+
+restore_context:
+	ldw		ra, 0(sp)		# Restore the registers.
+							# Leave a gap for muldiv 0.
+	ldw		at, 8(sp)
+	ldw		r2, 12(sp)
+	ldw		r3, 16(sp)
+	ldw		r4, 20(sp)
+	ldw		r5, 24(sp) 
+	ldw		r6, 28(sp) 
+	ldw		r7, 32(sp) 
+	ldw		r8, 36(sp) 
+	ldw		r9, 40(sp) 
+	ldw		r10, 44(sp)
+	ldw		r11, 48(sp)
+	ldw		r12, 52(sp)
+	ldw		r13, 56(sp)
+	ldw		r14, 60(sp)
+	ldw		r15, 64(sp)
+	ldw		et, 68(sp)		# Load the eStatus
+	wrctl	estatus, et 	# Write the eStatus
+	ldw		ea, 72(sp)		# Load the Program Counter
+	ldw		r16, 76(sp)
+	ldw		r17, 80(sp)
+	ldw		r18, 84(sp)
+	ldw		r19, 88(sp)
+	ldw		r20, 92(sp)
+	ldw		r21, 96(sp)
+	ldw		r22, 100(sp)
+	ldw		r23, 104(sp)
+	ldw		gp, 108(sp)
+	ldw		fp, 112(sp)
+	addi	sp,	sp, 116		# Release stack space
+
+    eret					# Return to address ea, loading eStatus into Status.
+   
+	.section .exceptions.soft, "xa"
+soft_exceptions:
+	ldw		et, 0(ea)				# Load the instruction where the interrupt occured.
+	movhi	at, %hi(0x003B683A)		# Load the registers with the trap instruction code
+	ori		at, at, %lo(0x003B683A)
+   	cmpne	et, et, at				# Compare the trap instruction code to the last excuted instruction
+  	beq		et, r0, call_scheduler	# its a trap so switchcontext
+  	break							# This is an un-implemented instruction or muldiv problem.
+  	br		restore_context			# its something else
+
+call_scheduler:
+	addi	ea, ea, 4						# A trap was called, increment the program counter so it is not called again.
+	stw		ea, 72(sp)						# Save the new program counter to the context.
+	call	vTaskSwitchContext				# Pick the next context.
+	br		restore_sp_from_pxCurrentTCB	# Switch in the task context and restore. 
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/NiosII/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/NiosII/portmacro.h
new file mode 100644
index 0000000..9e988ad
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/NiosII/portmacro.h
@@ -0,0 +1,109 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "sys/alt_irq.h"
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH				( -1 )
+#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT				4
+#define portNOP()                   	asm volatile ( "NOP" )
+#define portCRITICAL_NESTING_IN_TCB		1
+/*-----------------------------------------------------------*/
+
+extern void vTaskSwitchContext( void );
+#define portYIELD()									asm volatile ( "trap" );
+#define portEND_SWITCHING_ISR( xSwitchRequired ) 	if( xSwitchRequired ) 	vTaskSwitchContext()
+
+
+/* Include the port_asm.S file where the Context saving/restoring is defined. */
+__asm__( "\n\t.globl	save_context" );
+
+/*-----------------------------------------------------------*/
+
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()	alt_irq_disable_all()
+#define portENABLE_INTERRUPTS()		alt_irq_enable_all( 0x01 );
+#define portENTER_CRITICAL()        vTaskEnterCritical()
+#define portEXIT_CRITICAL()         vTaskExitCritical()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/FPU_Macros.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/FPU_Macros.h
new file mode 100644
index 0000000..cc99cee
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/FPU_Macros.h
@@ -0,0 +1,45 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* When switching out a task, if the task tag contains a buffer address then
+save the flop context into the buffer. */
+#define traceTASK_SWITCHED_OUT()											\
+	if( pxCurrentTCB->pxTaskTag != NULL )									\
+	{																		\
+		extern void vPortSaveFPURegisters( void * );						\
+		vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) );	\
+	}
+
+/* When switching in a task, if the task tag contains a buffer address then
+load the flop context from the buffer. */
+#define traceTASK_SWITCHED_IN()												\
+	if( pxCurrentTCB->pxTaskTag != NULL )									\
+	{																		\
+		extern void vPortRestoreFPURegisters( void * );						\
+		vPortRestoreFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) );	\
+	}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/port.c
new file mode 100644
index 0000000..dd113ae
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/port.c
@@ -0,0 +1,260 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the PPC405 port.
+ *----------------------------------------------------------*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "xtime_l.h"
+#include "xintc.h"
+#include "xintc_i.h"
+
+/*-----------------------------------------------------------*/
+
+/* Definitions to set the initial MSR of each task. */
+#define portCRITICAL_INTERRUPT_ENABLE	( 1UL << 17UL )
+#define portEXTERNAL_INTERRUPT_ENABLE	( 1UL << 15UL )
+#define portMACHINE_CHECK_ENABLE		( 1UL << 12UL )
+
+#if configUSE_FPU == 1
+	#define portAPU_PRESENT				( 1UL << 25UL )
+	#define portFCM_FPU_PRESENT			( 1UL << 13UL )
+#else
+	#define portAPU_PRESENT				( 0UL )
+	#define portFCM_FPU_PRESENT			( 0UL )
+#endif
+
+#define portINITIAL_MSR		( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
+
+
+extern const unsigned _SDA_BASE_;
+extern const unsigned _SDA2_BASE_;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the system timer to generate the tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * The handler for the tick interrupt - defined in portasm.s.
+ */
+extern void vPortTickISR( void );
+
+/*
+ * The handler for the yield function - defined in portasm.s.
+ */
+extern void vPortYield( void );
+
+/*
+ * Function to start the scheduler running by starting the highest
+ * priority task that has thus far been created.
+ */
+extern void vPortStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/* Structure used to hold the state of the interrupt controller. */
+static XIntc xInterruptController;
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if the task had been
+ * interrupted.
+ * 
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Place a known value at the bottom of the stack for debugging. */
+	*pxTopOfStack = 0xDEADBEEF;
+	pxTopOfStack--;
+
+	/* EABI stack frame. */
+	pxTopOfStack -= 20;	/* Previous backchain and LR, R31 to R4 inclusive. */
+
+	/* Parameters in R13. */
+	*pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */
+	pxTopOfStack -= 10;
+
+	/* Parameters in R3. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;
+	pxTopOfStack--;
+
+	/* Parameters in R2. */
+	*pxTopOfStack = ( StackType_t ) &_SDA2_BASE_;	/* address of the second small data area */
+	pxTopOfStack--;
+
+	/* R1 is the stack pointer so is omitted. */
+
+	*pxTopOfStack = 0x10000001UL;;	/* R0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x00000000UL;	/* USPRG0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x00000000UL;	/* CR. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x00000000UL;	/* XER. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x00000000UL;	/* CTR. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) vPortEndScheduler;	/* LR. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_MSR;/* SRR1. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) vPortEndScheduler;/* Next LR. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x00000000UL;/* Backchain. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	prvSetupTimerInterrupt();
+	XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 );
+	vPortStartFirstTask();
+
+	/* Should not get here as the tasks are now running! */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented. */
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.   
+ */
+static void prvSetupTimerInterrupt( void )
+{
+const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
+
+	XTime_PITClearInterrupt();
+	XTime_FITClearInterrupt();
+	XTime_WDTClearInterrupt();
+	XTime_WDTDisableInterrupt();
+	XTime_FITDisableInterrupt();
+
+	XExc_RegisterHandler( XEXC_ID_PIT_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 );
+
+	XTime_PITEnableAutoReload();
+	XTime_PITSetInterval( ulInterval );
+	XTime_PITEnableInterrupt();
+}
+/*-----------------------------------------------------------*/
+
+void vPortISRHandler( void *pvNullDoNotUse )
+{
+uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
+BaseType_t xInterruptNumber;
+XIntc_Config *pxInterruptController;
+XIntc_VectorTableEntry *pxTable;
+
+	/* Just to remove compiler warning. */
+	( void ) pvNullDoNotUse;	
+
+	/* Get the configuration by using the device ID - in this case it is
+	assumed that only one interrupt controller is being used. */
+	pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
+  
+	/* Which interrupts are pending? */
+	ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
+  
+	for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ )
+	{
+		if( ulInterruptStatus & 0x01UL )
+		{
+			/* Clear the pending interrupt. */
+			XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask );
+
+			/* Call the registered handler. */
+			pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] );
+			pxTable->Handler( pxTable->CallBackRef );
+		}
+        
+		/* Check the next interrupt. */
+		ulInterruptMask <<= 0x01UL;
+		ulInterruptStatus >>= 0x01UL;
+
+		/* Have we serviced all interrupts? */
+		if( ulInterruptStatus == 0UL )
+		{
+			break;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetupInterruptController( void )
+{
+extern void vPortISRWrapper( void );
+
+	/* Perform all library calls necessary to initialise the exception table
+	and interrupt controller.  This assumes only one interrupt controller is in
+	use. */
+	XExc_mDisableExceptions( XEXC_NON_CRITICAL );
+	XExc_Init();
+
+	/* The library functions save the context - we then jump to a wrapper to
+	save the stack into the TCB.  The wrapper then calls the handler defined
+	above. */
+	XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
+	XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
+	XIntc_Start( &xInterruptController, XIN_REAL_MODE );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
+{
+BaseType_t xReturn = pdFAIL;
+
+	/* This function is defined here so the scope of xInterruptController can
+	remain within this file. */
+
+	if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
+	{
+		XIntc_Enable( &xInterruptController, ucInterruptID );
+		xReturn = pdPASS;
+	}
+
+	return xReturn;		
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/portasm.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/portasm.S
new file mode 100644
index 0000000..dd855a1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/portasm.S
@@ -0,0 +1,382 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "FreeRTOSConfig.h"
+
+	.extern pxCurrentTCB
+	.extern vTaskSwitchContext
+	.extern xTaskIncrementTick
+	.extern vPortISRHandler
+
+	.global vPortStartFirstTask
+	.global vPortYield
+	.global vPortTickISR
+	.global vPortISRWrapper
+	.global vPortSaveFPURegisters
+	.global vPortRestoreFPURegisters
+
+.set	BChainField, 0
+.set	NextLRField, BChainField + 4
+.set	MSRField,    NextLRField + 4
+.set	PCField,     MSRField    + 4
+.set	LRField,     PCField     + 4
+.set	CTRField,    LRField     + 4
+.set	XERField,    CTRField    + 4
+.set	CRField,     XERField    + 4
+.set	USPRG0Field, CRField     + 4
+.set	r0Field,     USPRG0Field + 4
+.set	r2Field,     r0Field     + 4
+.set	r3r31Field,  r2Field     + 4
+.set	IFrameSize,  r3r31Field  + ( ( 31 - 3 ) + 1 ) * 4
+
+
+.macro portSAVE_STACK_POINTER_AND_LR
+
+	/* Get the address of the TCB. */
+	xor		R0, R0, R0
+	addis	R2, R0, pxCurrentTCB@ha
+	lwz		R2,	pxCurrentTCB@l( R2 )
+
+	/* Store the stack pointer into the TCB */
+	stw		SP,	0( R2 )
+
+	/* Save the link register */
+	stwu	R1, -24( R1 )
+	mflr	R0
+	stw		R31, 20( R1 )
+	stw		R0, 28( R1 )
+	mr		R31, r1
+
+.endm
+
+.macro portRESTORE_STACK_POINTER_AND_LR
+
+	/* Restore the link register */
+	lwz		R11, 0( R1 )
+	lwz		R0, 4( R11 )
+	mtlr	R0
+	lwz		R31, -4( R11 )
+	mr		R1, R11
+
+	/* Get the address of the TCB. */
+	xor		R0, R0, R0
+	addis   SP, R0, pxCurrentTCB@ha
+	lwz		SP,	pxCurrentTCB@l( R1 )
+
+	/* Get the task stack pointer from the TCB. */
+	lwz		SP, 0( SP )
+
+.endm
+
+
+vPortStartFirstTask:
+
+	/* Get the address of the TCB. */
+	xor		R0, R0, R0
+    addis   SP, R0, pxCurrentTCB@ha
+    lwz		SP,	pxCurrentTCB@l( SP )
+
+	/* Get the task stack pointer from the TCB. */
+	lwz		SP, 0( SP )
+	
+	/* Restore MSR register to SRR1. */
+	lwz		R0, MSRField(R1)
+	mtsrr1	R0
+	
+	/* Restore current PC location to SRR0. */
+	lwz		R0, PCField(R1)
+	mtsrr0	R0
+
+	/* Save  USPRG0 register */
+	lwz		R0, USPRG0Field(R1)
+	mtspr	0x100,R0
+	
+	/* Restore Condition register */
+	lwz		R0, CRField(R1)
+	mtcr	R0
+	
+	/* Restore Fixed Point Exception register */
+	lwz		R0, XERField(R1)
+	mtxer	R0
+	
+	/* Restore Counter register */
+	lwz		R0, CTRField(R1)
+	mtctr	R0
+	
+	/* Restore Link register */
+	lwz		R0, LRField(R1)
+	mtlr	R0
+	
+	/* Restore remaining GPR registers. */
+	lmw	R3,r3r31Field(R1)
+	
+	/* Restore r0 and r2. */
+	lwz		R0, r0Field(R1)
+	lwz		R2, r2Field(R1)
+	
+	/* Remove frame from stack */
+	addi	R1,R1,IFrameSize
+
+	/* Return into the first task */
+	rfi
+
+
+
+vPortYield:
+
+	portSAVE_STACK_POINTER_AND_LR
+	bl vTaskSwitchContext
+	portRESTORE_STACK_POINTER_AND_LR
+	blr
+
+vPortTickISR:
+
+	portSAVE_STACK_POINTER_AND_LR
+	bl xTaskIncrementTick
+	
+	#if configUSE_PREEMPTION == 1
+		bl vTaskSwitchContext
+	#endif
+
+	/* Clear the interrupt */
+	lis		R0, 2048
+	mttsr	R0
+
+	portRESTORE_STACK_POINTER_AND_LR
+	blr
+
+vPortISRWrapper:
+
+	portSAVE_STACK_POINTER_AND_LR
+	bl vPortISRHandler
+	portRESTORE_STACK_POINTER_AND_LR
+	blr
+
+#if configUSE_FPU == 1
+
+vPortSaveFPURegisters:
+
+	/* Enable APU and mark FPU as present. */
+	mfmsr	r0
+	xor		r30, r30, r30
+	oris	r30, r30, 512
+	ori		r30, r30, 8192
+	or		r0, r0, r30
+	mtmsr	r0
+
+#ifdef USE_DP_FPU
+
+	/* Buffer address is in r3.  Save each flop register into an offset from
+	this buffer address. */
+	stfd	f0, 0(r3)
+	stfd	f1, 8(r3)
+	stfd	f2, 16(r3)
+	stfd	f3, 24(r3)
+	stfd	f4, 32(r3)
+	stfd	f5, 40(r3)
+	stfd	f6, 48(r3)
+	stfd	f7, 56(r3)
+	stfd	f8, 64(r3)
+	stfd	f9, 72(r3)
+	stfd	f10, 80(r3)
+	stfd	f11, 88(r3)
+	stfd	f12, 96(r3)
+	stfd	f13, 104(r3)
+	stfd	f14, 112(r3)
+	stfd	f15, 120(r3)
+	stfd	f16, 128(r3)
+	stfd	f17, 136(r3)
+	stfd	f18, 144(r3)
+	stfd	f19, 152(r3)
+	stfd	f20, 160(r3)
+	stfd	f21, 168(r3)
+	stfd	f22, 176(r3)
+	stfd	f23, 184(r3)
+	stfd	f24, 192(r3)
+	stfd	f25, 200(r3)
+	stfd	f26, 208(r3)
+	stfd	f27, 216(r3)
+	stfd	f28, 224(r3)
+	stfd	f29, 232(r3)
+	stfd	f30, 240(r3)
+	stfd	f31, 248(r3)	
+	
+	/* Also save the FPSCR. */
+	mffs	f31
+	stfs	f31, 256(r3)
+
+#else
+
+	/* Buffer address is in r3.  Save each flop register into an offset from
+	this buffer address. */
+	stfs	f0, 0(r3)
+	stfs	f1, 4(r3)
+	stfs	f2, 8(r3)
+	stfs	f3, 12(r3)
+	stfs	f4, 16(r3)
+	stfs	f5, 20(r3)
+	stfs	f6, 24(r3)
+	stfs	f7, 28(r3)
+	stfs	f8, 32(r3)
+	stfs	f9, 36(r3)
+	stfs	f10, 40(r3)
+	stfs	f11, 44(r3)
+	stfs	f12, 48(r3)
+	stfs	f13, 52(r3)
+	stfs	f14, 56(r3)
+	stfs	f15, 60(r3)
+	stfs	f16, 64(r3)
+	stfs	f17, 68(r3)
+	stfs	f18, 72(r3)
+	stfs	f19, 76(r3)
+	stfs	f20, 80(r3)
+	stfs	f21, 84(r3)
+	stfs	f22, 88(r3)
+	stfs	f23, 92(r3)
+	stfs	f24, 96(r3)
+	stfs	f25, 100(r3)
+	stfs	f26, 104(r3)
+	stfs	f27, 108(r3)
+	stfs	f28, 112(r3)
+	stfs	f29, 116(r3)
+	stfs	f30, 120(r3)
+	stfs	f31, 124(r3)
+	
+	/* Also save the FPSCR. */
+	mffs	f31
+	stfs	f31, 128(r3)
+	
+#endif
+
+	blr
+
+#endif /* configUSE_FPU. */
+
+
+#if configUSE_FPU == 1
+
+vPortRestoreFPURegisters:
+
+	/* Enable APU and mark FPU as present. */
+	mfmsr	r0
+	xor		r30, r30, r30
+	oris	r30, r30, 512
+	ori		r30, r30, 8192
+	or		r0, r0, r30
+	mtmsr	r0
+
+#ifdef USE_DP_FPU
+
+	/* Buffer address is in r3.  Restore each flop register from an offset
+	into this buffer. 
+	
+	First the FPSCR. */
+	lfs		f31, 256(r3)
+	mtfsf	f31, 7
+
+	lfd		f0, 0(r3)
+	lfd	    f1, 8(r3)
+	lfd		f2, 16(r3)
+	lfd		f3, 24(r3)
+	lfd		f4, 32(r3)
+	lfd		f5, 40(r3)
+	lfd		f6, 48(r3)
+	lfd		f7, 56(r3)
+	lfd		f8, 64(r3)
+	lfd		f9, 72(r3)
+	lfd		f10, 80(r3)
+	lfd		f11, 88(r3)
+	lfd		f12, 96(r3)
+	lfd		f13, 104(r3)
+	lfd		f14, 112(r3)
+	lfd		f15, 120(r3)
+	lfd		f16, 128(r3)
+	lfd		f17, 136(r3)
+	lfd		f18, 144(r3)
+	lfd		f19, 152(r3)
+	lfd		f20, 160(r3)
+	lfd		f21, 168(r3)
+	lfd		f22, 176(r3)
+	lfd		f23, 184(r3)
+	lfd		f24, 192(r3)
+	lfd		f25, 200(r3)
+	lfd		f26, 208(r3)
+	lfd		f27, 216(r3)
+	lfd		f28, 224(r3)
+	lfd		f29, 232(r3)
+	lfd		f30, 240(r3)
+	lfd		f31, 248(r3)
+
+#else
+
+	/* Buffer address is in r3.  Restore each flop register from an offset
+	into this buffer. 
+	
+	First the FPSCR. */
+	lfs		f31, 128(r3)
+	mtfsf	f31, 7
+
+	lfs		f0, 0(r3)
+	lfs		f1, 4(r3)
+	lfs		f2, 8(r3)
+	lfs		f3, 12(r3)
+	lfs		f4, 16(r3)
+	lfs		f5, 20(r3)
+	lfs		f6, 24(r3)
+	lfs		f7, 28(r3)
+	lfs		f8, 32(r3)
+	lfs		f9, 36(r3)
+	lfs		f10, 40(r3)
+	lfs		f11, 44(r3)
+	lfs		f12, 48(r3)
+	lfs		f13, 52(r3)
+	lfs		f14, 56(r3)
+	lfs		f15, 60(r3)
+	lfs		f16, 64(r3)
+	lfs		f17, 68(r3)
+	lfs		f18, 72(r3)
+	lfs		f19, 76(r3)
+	lfs		f20, 80(r3)
+	lfs		f21, 84(r3)
+	lfs		f22, 88(r3)
+	lfs		f23, 92(r3)
+	lfs		f24, 96(r3)
+	lfs		f25, 100(r3)
+	lfs		f26, 104(r3)
+	lfs		f27, 108(r3)
+	lfs		f28, 112(r3)
+	lfs		f29, 116(r3)
+	lfs		f30, 120(r3)
+	lfs		f31, 124(r3)
+
+#endif
+
+	blr
+
+#endif /* configUSE_FPU. */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/portmacro.h
new file mode 100644
index 0000000..7986f2e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/portmacro.h
@@ -0,0 +1,118 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include "xexception_l.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* This port uses the critical nesting count from the TCB rather than
+maintaining a separate value and then saving this value in the task stack. */
+#define portCRITICAL_NESTING_IN_TCB		1
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS()		XExc_mDisableExceptions( XEXC_NON_CRITICAL );
+#define portENABLE_INTERRUPTS()			XExc_mEnableExceptions( XEXC_NON_CRITICAL );
+
+/*-----------------------------------------------------------*/
+
+/* Critical section macros. */
+void vTaskEnterCritical( void );
+void vTaskExitCritical( void );
+#define portENTER_CRITICAL()			vTaskEnterCritical()
+#define portEXIT_CRITICAL()				vTaskExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+void vPortYield( void );
+#define portYIELD() asm volatile ( "SC \n\t NOP" )
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			8
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					asm volatile ( "NOP" )
+
+/* There are 32 * 32bit floating point regieters, plus the FPSCR to save. */
+#define portNO_FLOP_REGISTERS_TO_SAVE  ( 32 + 1 )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+/* Port specific interrupt handling functions. */
+void vPortSetupInterruptController( void );
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/FPU_Macros.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/FPU_Macros.h
new file mode 100644
index 0000000..cc99cee
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/FPU_Macros.h
@@ -0,0 +1,45 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* When switching out a task, if the task tag contains a buffer address then
+save the flop context into the buffer. */
+#define traceTASK_SWITCHED_OUT()											\
+	if( pxCurrentTCB->pxTaskTag != NULL )									\
+	{																		\
+		extern void vPortSaveFPURegisters( void * );						\
+		vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) );	\
+	}
+
+/* When switching in a task, if the task tag contains a buffer address then
+load the flop context from the buffer. */
+#define traceTASK_SWITCHED_IN()												\
+	if( pxCurrentTCB->pxTaskTag != NULL )									\
+	{																		\
+		extern void vPortRestoreFPURegisters( void * );						\
+		vPortRestoreFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) );	\
+	}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/port.c
new file mode 100644
index 0000000..260ccb9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/port.c
@@ -0,0 +1,260 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the PPC440 port.
+ *----------------------------------------------------------*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "xtime_l.h"
+#include "xintc.h"
+#include "xintc_i.h"
+
+/*-----------------------------------------------------------*/
+
+/* Definitions to set the initial MSR of each task. */
+#define portCRITICAL_INTERRUPT_ENABLE	( 1UL << 17UL )
+#define portEXTERNAL_INTERRUPT_ENABLE	( 1UL << 15UL )
+#define portMACHINE_CHECK_ENABLE		( 1UL << 12UL )
+
+#if configUSE_FPU == 1
+	#define portAPU_PRESENT				( 1UL << 25UL )
+	#define portFCM_FPU_PRESENT			( 1UL << 13UL )
+#else
+	#define portAPU_PRESENT				( 0UL )
+	#define portFCM_FPU_PRESENT			( 0UL )
+#endif
+
+#define portINITIAL_MSR		( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
+
+
+extern const unsigned _SDA_BASE_;
+extern const unsigned _SDA2_BASE_;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the system timer to generate the tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * The handler for the tick interrupt - defined in portasm.s.
+ */
+extern void vPortTickISR( void );
+
+/*
+ * The handler for the yield function - defined in portasm.s.
+ */
+extern void vPortYield( void );
+
+/*
+ * Function to start the scheduler running by starting the highest
+ * priority task that has thus far been created.
+ */
+extern void vPortStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/* Structure used to hold the state of the interrupt controller. */
+static XIntc xInterruptController;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if the task had been
+ * interrupted.
+ *
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Place a known value at the bottom of the stack for debugging. */
+	*pxTopOfStack = 0xDEADBEEF;
+	pxTopOfStack--;
+
+	/* EABI stack frame. */
+	pxTopOfStack -= 20;	/* Previous backchain and LR, R31 to R4 inclusive. */
+
+	/* Parameters in R13. */
+	*pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */
+	pxTopOfStack -= 10;
+
+	/* Parameters in R3. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;
+	pxTopOfStack--;
+
+	/* Parameters in R2. */
+	*pxTopOfStack = ( StackType_t ) &_SDA2_BASE_;	/* address of the second small data area */
+	pxTopOfStack--;
+
+	/* R1 is the stack pointer so is omitted. */
+
+	*pxTopOfStack = 0x10000001UL;;	/* R0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x00000000UL;	/* USPRG0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x00000000UL;	/* CR. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x00000000UL;	/* XER. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x00000000UL;	/* CTR. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) vPortEndScheduler;	/* LR. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_MSR;/* SRR1. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) vPortEndScheduler;/* Next LR. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x00000000UL;/* Backchain. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	prvSetupTimerInterrupt();
+	XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 );
+	vPortStartFirstTask();
+
+	/* Should not get here as the tasks are now running! */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented. */
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
+
+	XTime_DECClearInterrupt();
+	XTime_FITClearInterrupt();
+	XTime_WDTClearInterrupt();
+	XTime_WDTDisableInterrupt();
+	XTime_FITDisableInterrupt();
+
+	XExc_RegisterHandler( XEXC_ID_DEC_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 );
+
+	XTime_DECEnableAutoReload();
+	XTime_DECSetInterval( ulInterval );
+	XTime_DECEnableInterrupt();
+}
+/*-----------------------------------------------------------*/
+
+void vPortISRHandler( void *pvNullDoNotUse )
+{
+uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
+BaseType_t xInterruptNumber;
+XIntc_Config *pxInterruptController;
+XIntc_VectorTableEntry *pxTable;
+
+	/* Just to remove compiler warning. */
+	( void ) pvNullDoNotUse;
+
+	/* Get the configuration by using the device ID - in this case it is
+	assumed that only one interrupt controller is being used. */
+	pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
+
+	/* Which interrupts are pending? */
+	ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
+
+	for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ )
+	{
+		if( ulInterruptStatus & 0x01UL )
+		{
+			/* Clear the pending interrupt. */
+			XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask );
+
+			/* Call the registered handler. */
+			pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] );
+			pxTable->Handler( pxTable->CallBackRef );
+		}
+
+		/* Check the next interrupt. */
+		ulInterruptMask <<= 0x01UL;
+		ulInterruptStatus >>= 0x01UL;
+
+		/* Have we serviced all interrupts? */
+		if( ulInterruptStatus == 0UL )
+		{
+			break;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetupInterruptController( void )
+{
+extern void vPortISRWrapper( void );
+
+	/* Perform all library calls necessary to initialise the exception table
+	and interrupt controller.  This assumes only one interrupt controller is in
+	use. */
+	XExc_mDisableExceptions( XEXC_NON_CRITICAL );
+	XExc_Init();
+
+	/* The library functions save the context - we then jump to a wrapper to
+	save the stack into the TCB.  The wrapper then calls the handler defined
+	above. */
+	XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
+	XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
+	XIntc_Start( &xInterruptController, XIN_REAL_MODE );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
+{
+BaseType_t xReturn = pdFAIL;
+
+	/* This function is defined here so the scope of xInterruptController can
+	remain within this file. */
+
+	if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
+	{
+		XIntc_Enable( &xInterruptController, ucInterruptID );
+		xReturn = pdPASS;
+	}
+
+	return xReturn;
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/portasm.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/portasm.S
new file mode 100644
index 0000000..dd855a1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/portasm.S
@@ -0,0 +1,382 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "FreeRTOSConfig.h"
+
+	.extern pxCurrentTCB
+	.extern vTaskSwitchContext
+	.extern xTaskIncrementTick
+	.extern vPortISRHandler
+
+	.global vPortStartFirstTask
+	.global vPortYield
+	.global vPortTickISR
+	.global vPortISRWrapper
+	.global vPortSaveFPURegisters
+	.global vPortRestoreFPURegisters
+
+.set	BChainField, 0
+.set	NextLRField, BChainField + 4
+.set	MSRField,    NextLRField + 4
+.set	PCField,     MSRField    + 4
+.set	LRField,     PCField     + 4
+.set	CTRField,    LRField     + 4
+.set	XERField,    CTRField    + 4
+.set	CRField,     XERField    + 4
+.set	USPRG0Field, CRField     + 4
+.set	r0Field,     USPRG0Field + 4
+.set	r2Field,     r0Field     + 4
+.set	r3r31Field,  r2Field     + 4
+.set	IFrameSize,  r3r31Field  + ( ( 31 - 3 ) + 1 ) * 4
+
+
+.macro portSAVE_STACK_POINTER_AND_LR
+
+	/* Get the address of the TCB. */
+	xor		R0, R0, R0
+	addis	R2, R0, pxCurrentTCB@ha
+	lwz		R2,	pxCurrentTCB@l( R2 )
+
+	/* Store the stack pointer into the TCB */
+	stw		SP,	0( R2 )
+
+	/* Save the link register */
+	stwu	R1, -24( R1 )
+	mflr	R0
+	stw		R31, 20( R1 )
+	stw		R0, 28( R1 )
+	mr		R31, r1
+
+.endm
+
+.macro portRESTORE_STACK_POINTER_AND_LR
+
+	/* Restore the link register */
+	lwz		R11, 0( R1 )
+	lwz		R0, 4( R11 )
+	mtlr	R0
+	lwz		R31, -4( R11 )
+	mr		R1, R11
+
+	/* Get the address of the TCB. */
+	xor		R0, R0, R0
+	addis   SP, R0, pxCurrentTCB@ha
+	lwz		SP,	pxCurrentTCB@l( R1 )
+
+	/* Get the task stack pointer from the TCB. */
+	lwz		SP, 0( SP )
+
+.endm
+
+
+vPortStartFirstTask:
+
+	/* Get the address of the TCB. */
+	xor		R0, R0, R0
+    addis   SP, R0, pxCurrentTCB@ha
+    lwz		SP,	pxCurrentTCB@l( SP )
+
+	/* Get the task stack pointer from the TCB. */
+	lwz		SP, 0( SP )
+	
+	/* Restore MSR register to SRR1. */
+	lwz		R0, MSRField(R1)
+	mtsrr1	R0
+	
+	/* Restore current PC location to SRR0. */
+	lwz		R0, PCField(R1)
+	mtsrr0	R0
+
+	/* Save  USPRG0 register */
+	lwz		R0, USPRG0Field(R1)
+	mtspr	0x100,R0
+	
+	/* Restore Condition register */
+	lwz		R0, CRField(R1)
+	mtcr	R0
+	
+	/* Restore Fixed Point Exception register */
+	lwz		R0, XERField(R1)
+	mtxer	R0
+	
+	/* Restore Counter register */
+	lwz		R0, CTRField(R1)
+	mtctr	R0
+	
+	/* Restore Link register */
+	lwz		R0, LRField(R1)
+	mtlr	R0
+	
+	/* Restore remaining GPR registers. */
+	lmw	R3,r3r31Field(R1)
+	
+	/* Restore r0 and r2. */
+	lwz		R0, r0Field(R1)
+	lwz		R2, r2Field(R1)
+	
+	/* Remove frame from stack */
+	addi	R1,R1,IFrameSize
+
+	/* Return into the first task */
+	rfi
+
+
+
+vPortYield:
+
+	portSAVE_STACK_POINTER_AND_LR
+	bl vTaskSwitchContext
+	portRESTORE_STACK_POINTER_AND_LR
+	blr
+
+vPortTickISR:
+
+	portSAVE_STACK_POINTER_AND_LR
+	bl xTaskIncrementTick
+	
+	#if configUSE_PREEMPTION == 1
+		bl vTaskSwitchContext
+	#endif
+
+	/* Clear the interrupt */
+	lis		R0, 2048
+	mttsr	R0
+
+	portRESTORE_STACK_POINTER_AND_LR
+	blr
+
+vPortISRWrapper:
+
+	portSAVE_STACK_POINTER_AND_LR
+	bl vPortISRHandler
+	portRESTORE_STACK_POINTER_AND_LR
+	blr
+
+#if configUSE_FPU == 1
+
+vPortSaveFPURegisters:
+
+	/* Enable APU and mark FPU as present. */
+	mfmsr	r0
+	xor		r30, r30, r30
+	oris	r30, r30, 512
+	ori		r30, r30, 8192
+	or		r0, r0, r30
+	mtmsr	r0
+
+#ifdef USE_DP_FPU
+
+	/* Buffer address is in r3.  Save each flop register into an offset from
+	this buffer address. */
+	stfd	f0, 0(r3)
+	stfd	f1, 8(r3)
+	stfd	f2, 16(r3)
+	stfd	f3, 24(r3)
+	stfd	f4, 32(r3)
+	stfd	f5, 40(r3)
+	stfd	f6, 48(r3)
+	stfd	f7, 56(r3)
+	stfd	f8, 64(r3)
+	stfd	f9, 72(r3)
+	stfd	f10, 80(r3)
+	stfd	f11, 88(r3)
+	stfd	f12, 96(r3)
+	stfd	f13, 104(r3)
+	stfd	f14, 112(r3)
+	stfd	f15, 120(r3)
+	stfd	f16, 128(r3)
+	stfd	f17, 136(r3)
+	stfd	f18, 144(r3)
+	stfd	f19, 152(r3)
+	stfd	f20, 160(r3)
+	stfd	f21, 168(r3)
+	stfd	f22, 176(r3)
+	stfd	f23, 184(r3)
+	stfd	f24, 192(r3)
+	stfd	f25, 200(r3)
+	stfd	f26, 208(r3)
+	stfd	f27, 216(r3)
+	stfd	f28, 224(r3)
+	stfd	f29, 232(r3)
+	stfd	f30, 240(r3)
+	stfd	f31, 248(r3)	
+	
+	/* Also save the FPSCR. */
+	mffs	f31
+	stfs	f31, 256(r3)
+
+#else
+
+	/* Buffer address is in r3.  Save each flop register into an offset from
+	this buffer address. */
+	stfs	f0, 0(r3)
+	stfs	f1, 4(r3)
+	stfs	f2, 8(r3)
+	stfs	f3, 12(r3)
+	stfs	f4, 16(r3)
+	stfs	f5, 20(r3)
+	stfs	f6, 24(r3)
+	stfs	f7, 28(r3)
+	stfs	f8, 32(r3)
+	stfs	f9, 36(r3)
+	stfs	f10, 40(r3)
+	stfs	f11, 44(r3)
+	stfs	f12, 48(r3)
+	stfs	f13, 52(r3)
+	stfs	f14, 56(r3)
+	stfs	f15, 60(r3)
+	stfs	f16, 64(r3)
+	stfs	f17, 68(r3)
+	stfs	f18, 72(r3)
+	stfs	f19, 76(r3)
+	stfs	f20, 80(r3)
+	stfs	f21, 84(r3)
+	stfs	f22, 88(r3)
+	stfs	f23, 92(r3)
+	stfs	f24, 96(r3)
+	stfs	f25, 100(r3)
+	stfs	f26, 104(r3)
+	stfs	f27, 108(r3)
+	stfs	f28, 112(r3)
+	stfs	f29, 116(r3)
+	stfs	f30, 120(r3)
+	stfs	f31, 124(r3)
+	
+	/* Also save the FPSCR. */
+	mffs	f31
+	stfs	f31, 128(r3)
+	
+#endif
+
+	blr
+
+#endif /* configUSE_FPU. */
+
+
+#if configUSE_FPU == 1
+
+vPortRestoreFPURegisters:
+
+	/* Enable APU and mark FPU as present. */
+	mfmsr	r0
+	xor		r30, r30, r30
+	oris	r30, r30, 512
+	ori		r30, r30, 8192
+	or		r0, r0, r30
+	mtmsr	r0
+
+#ifdef USE_DP_FPU
+
+	/* Buffer address is in r3.  Restore each flop register from an offset
+	into this buffer. 
+	
+	First the FPSCR. */
+	lfs		f31, 256(r3)
+	mtfsf	f31, 7
+
+	lfd		f0, 0(r3)
+	lfd	    f1, 8(r3)
+	lfd		f2, 16(r3)
+	lfd		f3, 24(r3)
+	lfd		f4, 32(r3)
+	lfd		f5, 40(r3)
+	lfd		f6, 48(r3)
+	lfd		f7, 56(r3)
+	lfd		f8, 64(r3)
+	lfd		f9, 72(r3)
+	lfd		f10, 80(r3)
+	lfd		f11, 88(r3)
+	lfd		f12, 96(r3)
+	lfd		f13, 104(r3)
+	lfd		f14, 112(r3)
+	lfd		f15, 120(r3)
+	lfd		f16, 128(r3)
+	lfd		f17, 136(r3)
+	lfd		f18, 144(r3)
+	lfd		f19, 152(r3)
+	lfd		f20, 160(r3)
+	lfd		f21, 168(r3)
+	lfd		f22, 176(r3)
+	lfd		f23, 184(r3)
+	lfd		f24, 192(r3)
+	lfd		f25, 200(r3)
+	lfd		f26, 208(r3)
+	lfd		f27, 216(r3)
+	lfd		f28, 224(r3)
+	lfd		f29, 232(r3)
+	lfd		f30, 240(r3)
+	lfd		f31, 248(r3)
+
+#else
+
+	/* Buffer address is in r3.  Restore each flop register from an offset
+	into this buffer. 
+	
+	First the FPSCR. */
+	lfs		f31, 128(r3)
+	mtfsf	f31, 7
+
+	lfs		f0, 0(r3)
+	lfs		f1, 4(r3)
+	lfs		f2, 8(r3)
+	lfs		f3, 12(r3)
+	lfs		f4, 16(r3)
+	lfs		f5, 20(r3)
+	lfs		f6, 24(r3)
+	lfs		f7, 28(r3)
+	lfs		f8, 32(r3)
+	lfs		f9, 36(r3)
+	lfs		f10, 40(r3)
+	lfs		f11, 44(r3)
+	lfs		f12, 48(r3)
+	lfs		f13, 52(r3)
+	lfs		f14, 56(r3)
+	lfs		f15, 60(r3)
+	lfs		f16, 64(r3)
+	lfs		f17, 68(r3)
+	lfs		f18, 72(r3)
+	lfs		f19, 76(r3)
+	lfs		f20, 80(r3)
+	lfs		f21, 84(r3)
+	lfs		f22, 88(r3)
+	lfs		f23, 92(r3)
+	lfs		f24, 96(r3)
+	lfs		f25, 100(r3)
+	lfs		f26, 104(r3)
+	lfs		f27, 108(r3)
+	lfs		f28, 112(r3)
+	lfs		f29, 116(r3)
+	lfs		f30, 120(r3)
+	lfs		f31, 124(r3)
+
+#endif
+
+	blr
+
+#endif /* configUSE_FPU. */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/portmacro.h
new file mode 100644
index 0000000..7986f2e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/portmacro.h
@@ -0,0 +1,118 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include "xexception_l.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* This port uses the critical nesting count from the TCB rather than
+maintaining a separate value and then saving this value in the task stack. */
+#define portCRITICAL_NESTING_IN_TCB		1
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS()		XExc_mDisableExceptions( XEXC_NON_CRITICAL );
+#define portENABLE_INTERRUPTS()			XExc_mEnableExceptions( XEXC_NON_CRITICAL );
+
+/*-----------------------------------------------------------*/
+
+/* Critical section macros. */
+void vTaskEnterCritical( void );
+void vTaskExitCritical( void );
+#define portENTER_CRITICAL()			vTaskEnterCritical()
+#define portEXIT_CRITICAL()				vTaskExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+void vPortYield( void );
+#define portYIELD() asm volatile ( "SC \n\t NOP" )
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			8
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					asm volatile ( "NOP" )
+
+/* There are 32 * 32bit floating point regieters, plus the FPSCR to save. */
+#define portNO_FLOP_REGISTERS_TO_SAVE  ( 32 + 1 )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+/* Port specific interrupt handling functions. */
+void vPortSetupInterruptController( void );
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
new file mode 100644
index 0000000..9e58143
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
@@ -0,0 +1,109 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and t
+
+ o permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
+ *
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ *   is common to all currently supported RISC-V chips.  There is only one
+ *   portASM.S file because the same file is built for all RISC-V target chips.
+ *
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
+ *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
+ *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
+ *   as there are multiple RISC-V chip implementations.
+ *
+ * !!!NOTE!!!
+ * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
+ * HEADER FILE FOR THE CHIP IN USE.  This is done using the assembler's (not the
+ * compiler's!) include path.  For example, if the chip in use includes a core
+ * local interrupter (CLINT) and does not include any chip specific register
+ * extensions then add the path below to the assembler's include path:
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ *
+ */
+
+/*
+ * This freertos_risc_v_chip_specific_extensions.h is for use with Pulpino Ri5cy
+ * devices, developed and tested using the Vega board RV32M1RM.
+ */
+
+#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
+#define __FREERTOS_RISC_V_EXTENSIONS_H__
+
+#define portasmHAS_CLINT 0
+
+/* Constants to define the additional registers found on the Pulpino RI5KY. */
+#define lpstart0 	0x7b0
+#define lpend0 		0x7b1
+#define lpcount0 	0x7b2
+#define lpstart1 	0x7b4
+#define lpend1 		0x7b5
+#define lpcount1 	0x7b6
+
+/* Six additional registers to save and restore, as per the #defines above. */
+#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */
+
+/* Save additional registers found on the Pulpino. */
+.macro portasmSAVE_ADDITIONAL_REGISTERS
+	addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */
+	csrr t0, lpstart0							 /* Load additional registers into accessible temporary registers. */
+	csrr t1, lpend0
+	csrr t2, lpcount0
+	csrr t3, lpstart1
+	csrr t4, lpend1
+	csrr t5, lpcount1
+	sw t0, 1 * portWORD_SIZE( sp )
+	sw t1, 2 * portWORD_SIZE( sp )
+	sw t2, 3 * portWORD_SIZE( sp )
+	sw t3, 4 * portWORD_SIZE( sp )
+	sw t4, 5 * portWORD_SIZE( sp )
+	sw t5, 6 * portWORD_SIZE( sp )
+	.endm
+
+/* Restore the additional registers found on the Pulpino. */
+.macro portasmRESTORE_ADDITIONAL_REGISTERS
+	lw t0, 1 * portWORD_SIZE( sp )			/* Load additional registers into accessible temporary registers. */
+	lw t1, 2 * portWORD_SIZE( sp )
+	lw t2, 3 * portWORD_SIZE( sp )
+	lw t3, 4 * portWORD_SIZE( sp )
+	lw t4, 5 * portWORD_SIZE( sp )
+	lw t5, 6 * portWORD_SIZE( sp )
+	csrw lpstart0, t0
+	csrw lpend0, t1
+	csrw lpcount0, t2
+	csrw lpstart1, t3
+	csrw lpend1, t4
+	csrw lpcount1, t5
+	addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */
+	.endm
+
+#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
new file mode 100644
index 0000000..3333a7c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
@@ -0,0 +1,68 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
+ *
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ *   is common to all currently supported RISC-V chips.  There is only one
+ *   portASM.S file because the same file is built for all RISC-V target chips.
+ *
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
+ *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
+ *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
+ *   as there are multiple RISC-V chip implementations.
+ *
+ * !!!NOTE!!!
+ * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
+ * HEADER FILE FOR THE CHIP IN USE.  This is done using the assembler's (not the
+ * compiler's!) include path.  For example, if the chip in use includes a core
+ * local interrupter (CLINT) and does not include any chip specific register
+ * extensions then add the path below to the assembler's include path:
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ *
+ */
+
+
+#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
+#define __FREERTOS_RISC_V_EXTENSIONS_H__
+
+#define portasmHAS_CLINT 1
+#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
+
+.macro portasmSAVE_ADDITIONAL_REGISTERS
+	/* No additional registers to save, so this macro does nothing. */
+	.endm
+
+/* Restore the additional registers found on the Pulpino. */
+.macro portasmRESTORE_ADDITIONAL_REGISTERS
+	/* No additional registers to restore, so this macro does nothing. */
+	.endm
+
+#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/readme.txt b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/readme.txt
new file mode 100644
index 0000000..69d98d9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/readme.txt
@@ -0,0 +1,23 @@
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
+ *
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ *   is common to all currently supported RISC-V chips.  There is only one
+ *   portASM.S file because the same file is built for all RISC-V target chips.
+ *
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
+ *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
+ *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
+ *   as there are multiple RISC-V chip implementations.
+ *
+ * !!!NOTE!!!
+ * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
+ * HEADER FILE FOR THE CHIP IN USE.  This is done using the assembler's (not the
+ * compiler's!) include path.  For example, if the chip in use includes a core
+ * local interrupter (CLINT) and does not include any chip specific register
+ * extensions then add the path below to the assembler's include path:
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ *
+ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RISC-V/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RISC-V/port.c
new file mode 100644
index 0000000..10350a9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RISC-V/port.c
@@ -0,0 +1,189 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the RISC-V RV32 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "portmacro.h"
+
+#ifndef configCLINT_BASE_ADDRESS
+	#warning configCLINT_BASE_ADDRESS must be defined in FreeRTOSConfig.h.  If the target chip includes a Core Local Interrupter (CLINT) then set configCLINT_BASE_ADDRESS to the CLINT base address.  Otherwise set configCLINT_BASE_ADDRESS to 0.
+#endif
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/* The stack used by interrupt service routines.  Set configISR_STACK_SIZE_WORDS
+to use a statically allocated array as the interrupt stack.  Alternative leave
+configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
+linker variable names __freertos_irq_stack_top has the same value as the top
+of the stack used by main.  Using the linker script method will repurpose the
+stack that was used by main before the scheduler was started for use as the
+interrupt stack after the scheduler has started. */
+#ifdef configISR_STACK_SIZE_WORDS
+	static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };
+	const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ ( configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ) - 1 ] );
+#else
+	extern const uint32_t __freertos_irq_stack_top[];
+	const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top;
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void ) __attribute__(( weak ));
+
+/*-----------------------------------------------------------*/
+
+/* Used to program the machine timer compare register. */
+uint64_t ullNextTime = 0ULL;
+const uint64_t *pullNextTime = &ullNextTime;
+const size_t uxTimerIncrementsForOneTick = ( size_t ) ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); /* Assumes increment won't go over 32-bits. */
+volatile uint64_t * const pullMachineTimerCompareRegister = ( volatile uint64_t * const ) ( configCLINT_BASE_ADDRESS + 0x4000 );
+
+/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
+stack checking.  A problem in the ISR stack will trigger an assert, not call the
+stack overflow hook function (because the stack overflow hook is specific to a
+task stack, not the ISR stack). */
+#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
+	#warning This path not tested, or even compiled yet.
+	/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
+	the task stacks, and so will legitimately appear in many positions within
+	the ISR stack. */
+	#define portISR_STACK_FILL_BYTE	0xee
+
+	static const uint8_t ucExpectedStackBytes[] = {
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE };	\
+
+	#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else
+	/* Define the function away. */
+	#define portCHECK_ISR_STACK()
+#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
+
+/*-----------------------------------------------------------*/
+
+#if( configCLINT_BASE_ADDRESS != 0 )
+
+	void vPortSetupTimerInterrupt( void )
+	{
+	uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
+	volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( configCLINT_BASE_ADDRESS + 0xBFFC );
+	volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configCLINT_BASE_ADDRESS + 0xBFF8 );
+
+		do
+		{
+			ulCurrentTimeHigh = *pulTimeHigh;
+			ulCurrentTimeLow = *pulTimeLow;
+		} while( ulCurrentTimeHigh != *pulTimeHigh );
+
+		ullNextTime = ( uint64_t ) ulCurrentTimeHigh;
+		ullNextTime <<= 32ULL;
+		ullNextTime |= ( uint64_t ) ulCurrentTimeLow;
+		ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
+		*pullMachineTimerCompareRegister = ullNextTime;
+
+		/* Prepare the time to use after the next tick interrupt. */
+		ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
+	}
+
+#endif /* ( configCLINT_BASE_ADDRESS != 0 ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void xPortStartFirstTask( void );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t mtvec = 0;
+
+		/* Check the least significant two bits of mtvec are 00 - indicating
+		single vector mode. */
+		__asm volatile( "csrr %0, mtvec" : "=r"( mtvec ) );
+		configASSERT( ( mtvec & 0x03UL ) == 0 );
+
+		/* Check alignment of the interrupt stack - which is the same as the
+		stack that was being used by main() prior to the scheduler being
+		started. */
+		configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );
+	}
+	#endif /* configASSERT_DEFINED */
+
+	/* If there is a CLINT then it is ok to use the default implementation
+	in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
+	configure whichever clock is to be used to generate the tick interrupt. */
+	vPortSetupTimerInterrupt();
+
+	#if( configCLINT_BASE_ADDRESS != 0 )
+	{
+		/* Enable mtime and external interrupts.  1<<7 for timer interrupt, 1<<11
+		for external interrupt.  _RB_ What happens here when mtime is not present as
+		with pulpino? */
+		__asm volatile( "csrs mie, %0" :: "r"(0x880) );
+	}
+	#else
+	{
+		/* Enable external interrupts. */
+		__asm volatile( "csrs mie, %0" :: "r"(0x800) );
+	}
+	#endif /* configCLINT_BASE_ADDRESS */
+
+	xPortStartFirstTask();
+
+	/* Should not get here as after calling xPortStartFirstTask() only tasks
+	should be executing. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented. */
+	for( ;; );
+}
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S
new file mode 100644
index 0000000..df6495f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S
@@ -0,0 +1,420 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
+ *
+ * + The code that is common to all RISC-V chips is implemented in
+ *   FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S.  There is only one
+ *   portASM.S file because the same file is used no matter which RISC-V chip is
+ *   in use.
+ *
+ * + The code that tailors the kernel's RISC-V port to a specific RISC-V
+ *   chip is implemented in freertos_risc_v_chip_specific_extensions.h.  There
+ *   is one freertos_risc_v_chip_specific_extensions.h that can be used with any
+ *   RISC-V chip that both includes a standard CLINT and does not add to the
+ *   base set of RISC-V registers.  There are additional
+ *   freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
+ *   that do not include a standard CLINT or do add to the base set of RISC-V
+ *   registers.
+ *
+ * CARE MUST BE TAKEN TO INCLDUE THE CORRECT
+ * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
+ * IN USE.  To include the correct freertos_risc_v_chip_specific_extensions.h
+ * header file ensure the path to the correct header file is in the assembler's
+ * include path.
+ *
+ * This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
+ * that include a standard CLINT and do not add to the base set of RISC-V
+ * registers.
+ *
+ */
+#if __riscv_xlen == 64
+	#define portWORD_SIZE 8
+	#define store_x sd
+	#define load_x ld
+#elif __riscv_xlen == 32
+	#define store_x sw
+	#define load_x lw
+	#define portWORD_SIZE 4
+#else
+	#error Assembler did not define __riscv_xlen
+#endif
+
+#include "freertos_risc_v_chip_specific_extensions.h"
+
+/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line
+definitions. */
+#ifndef portasmHAS_CLINT
+	#error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_CLINT to either 1 (CLINT present) or 0 (clint not present).
+#endif
+
+#ifndef portasmHANDLE_INTERRUPT
+	#error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts.  portasmHANDLE_INTERRUPT can be defined on the assmbler command line or in the appropriate freertos_risc_v_chip_specific_extensions.h header file.
+#endif
+
+/* Only the standard core registers are stored by default.  Any additional
+registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and
+portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
+specific version of freertos_risc_v_chip_specific_extensions.h.  See the notes
+at the top of this file. */
+#define portCONTEXT_SIZE ( 30 * portWORD_SIZE )
+
+.global xPortStartFirstTask
+.global freertos_risc_v_trap_handler
+.global pxPortInitialiseStack
+.extern pxCurrentTCB
+.extern ulPortTrapHandler
+.extern vTaskSwitchContext
+.extern Timer_IRQHandler
+.extern pullMachineTimerCompareRegister
+.extern pullNextTime
+.extern uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */
+.extern xISRStackTop
+
+/*-----------------------------------------------------------*/
+
+.align 8
+.func
+freertos_risc_v_trap_handler:
+	addi sp, sp, -portCONTEXT_SIZE
+	store_x x1, 1 * portWORD_SIZE( sp )
+	store_x x5, 2 * portWORD_SIZE( sp )
+	store_x x6, 3 * portWORD_SIZE( sp )
+	store_x x7, 4 * portWORD_SIZE( sp )
+	store_x x8, 5 * portWORD_SIZE( sp )
+	store_x x9, 6 * portWORD_SIZE( sp )
+	store_x x10, 7 * portWORD_SIZE( sp )
+	store_x x11, 8 * portWORD_SIZE( sp )
+	store_x x12, 9 * portWORD_SIZE( sp )
+	store_x x13, 10 * portWORD_SIZE( sp )
+	store_x x14, 11 * portWORD_SIZE( sp )
+	store_x x15, 12 * portWORD_SIZE( sp )
+	store_x x16, 13 * portWORD_SIZE( sp )
+	store_x x17, 14 * portWORD_SIZE( sp )
+	store_x x18, 15 * portWORD_SIZE( sp )
+	store_x x19, 16 * portWORD_SIZE( sp )
+	store_x x20, 17 * portWORD_SIZE( sp )
+	store_x x21, 18 * portWORD_SIZE( sp )
+	store_x x22, 19 * portWORD_SIZE( sp )
+	store_x x23, 20 * portWORD_SIZE( sp )
+	store_x x24, 21 * portWORD_SIZE( sp )
+	store_x x25, 22 * portWORD_SIZE( sp )
+	store_x x26, 23 * portWORD_SIZE( sp )
+	store_x x27, 24 * portWORD_SIZE( sp )
+	store_x x28, 25 * portWORD_SIZE( sp )
+	store_x x29, 26 * portWORD_SIZE( sp )
+	store_x x30, 27 * portWORD_SIZE( sp )
+	store_x x31, 28 * portWORD_SIZE( sp )
+
+	csrr t0, mstatus					/* Required for MPIE bit. */
+	store_x t0, 29 * portWORD_SIZE( sp )
+
+	portasmSAVE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
+
+	load_x  t0, pxCurrentTCB			/* Load pxCurrentTCB. */
+	store_x  sp, 0( t0 )				/* Write sp to first TCB member. */
+
+	csrr a0, mcause
+	csrr a1, mepc
+
+test_if_asynchronous:
+	srli a2, a0, __riscv_xlen - 1		/* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */
+	beq a2, x0, handle_synchronous		/* Branch past interrupt handing if not asynchronous. */
+	store_x a1, 0( sp )					/* Asynch so save unmodified exception return address. */
+
+handle_asynchronous:
+
+#if( portasmHAS_CLINT != 0 )
+
+	test_if_mtimer:						/* If there is a CLINT then the mtimer is used to generate the tick interrupt. */
+
+		addi t0, x0, 1
+
+		slli t0, t0, __riscv_xlen - 1   /* LSB is already set, shift into MSB.  Shift 31 on 32-bit or 63 on 64-bit cores. */
+		addi t1, t0, 7					/* 0x8000[]0007 == machine timer interrupt. */
+		bne a0, t1, test_if_external_interrupt
+
+		load_x t0, pullMachineTimerCompareRegister  /* Load address of compare register into t0. */
+		load_x t1, pullNextTime  		/* Load the address of ullNextTime into t1. */
+
+		#if( __riscv_xlen == 32 )
+
+			/* Update the 64-bit mtimer compare match value in two 32-bit writes. */
+			lw t2, 0(t1)				/* Load the low word of ullNextTime into t2. */
+			lw t3, 4(t1)				/* Load the high word of ullNextTime into t3. */
+			sw t2, 0(t0)				/* Store low word of ullNextTime into compare register. */
+			sw t3, 4(t0)				/* Store high word of ullNextTime into compare register. */
+			lw t0, uxTimerIncrementsForOneTick	/* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
+			add t4, t0, t2				/* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */
+			sltu t5, t4, t2				/* See if the sum of low words overflowed (what about the zero case?). */
+			add t6, t3, t5				/* Add overflow to high word of ullNextTime. */
+			sw t4, 0(t1)				/* Store new low word of ullNextTime. */
+			sw t6, 4(t1)				/* Store new high word of ullNextTime. */
+
+		#endif /* __riscv_xlen == 32 */
+
+		#if( __riscv_xlen == 64 )
+
+			/* Update the 64-bit mtimer compare match value. */
+			ld t2, 0(t1)			 	/* Load ullNextTime into t2. */
+			sd t2, 0(t0)				/* Store ullNextTime into compare register. */
+			ld t0, uxTimerIncrementsForOneTick  /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
+			add t4, t0, t2				/* Add ullNextTime to the timer increments for one tick. */
+			sd t4, 0(t1)				/* Store ullNextTime. */
+
+		#endif /* __riscv_xlen == 64 */
+
+		load_x sp, xISRStackTop			/* Switch to ISR stack before function call. */
+		jal xTaskIncrementTick
+		beqz a0, processed_source		/* Don't switch context if incrementing tick didn't unblock a task. */
+		jal vTaskSwitchContext
+		j processed_source
+
+	test_if_external_interrupt:			/* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */
+		addi t1, t1, 4					/* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */
+		bne a0, t1, as_yet_unhandled	/* Something as yet unhandled. */
+
+#endif /* portasmHAS_CLINT */
+
+	load_x sp, xISRStackTop				/* Switch to ISR stack before function call. */
+	jal portasmHANDLE_INTERRUPT			/* Jump to the interrupt handler if there is no CLINT or if there is a CLINT and it has been determined that an external interrupt is pending. */
+	j processed_source
+
+handle_synchronous:
+	addi a1, a1, 4						/* Synchronous so updated exception return address to the instruction after the instruction that generated the exeption. */
+	store_x a1, 0( sp )					/* Save updated exception return address. */
+
+test_if_environment_call:
+	li t0, 11 							/* 11 == environment call. */
+	bne a0, t0, is_exception			/* Not an M environment call, so some other exception. */
+	load_x sp, xISRStackTop				/* Switch to ISR stack before function call. */
+	jal vTaskSwitchContext
+	j processed_source
+
+is_exception:
+	ebreak
+	j is_exception
+
+as_yet_unhandled:
+	ebreak
+	j as_yet_unhandled
+
+processed_source:
+	load_x  t1, pxCurrentTCB			/* Load pxCurrentTCB. */
+	load_x  sp, 0( t1 )				 	/* Read sp from first TCB member. */
+
+	/* Load mret with the address of the next instruction in the task to run next. */
+	load_x t0, 0( sp )
+	csrw mepc, t0
+
+	portasmRESTORE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
+
+	/* Load mstatus with the interrupt enable bits used by the task. */
+	load_x  t0, 29 * portWORD_SIZE( sp )
+	csrw mstatus, t0						/* Required for MPIE bit. */
+
+	load_x  x1, 1 * portWORD_SIZE( sp )
+	load_x  x5, 2 * portWORD_SIZE( sp )		/* t0 */
+	load_x  x6, 3 * portWORD_SIZE( sp )		/* t1 */
+	load_x  x7, 4 * portWORD_SIZE( sp )		/* t2 */
+	load_x  x8, 5 * portWORD_SIZE( sp )		/* s0/fp */
+	load_x  x9, 6 * portWORD_SIZE( sp )		/* s1 */
+	load_x  x10, 7 * portWORD_SIZE( sp )	/* a0 */
+	load_x  x11, 8 * portWORD_SIZE( sp )	/* a1 */
+	load_x  x12, 9 * portWORD_SIZE( sp )	/* a2 */
+	load_x  x13, 10 * portWORD_SIZE( sp )	/* a3 */
+	load_x  x14, 11 * portWORD_SIZE( sp )	/* a4 */
+	load_x  x15, 12 * portWORD_SIZE( sp )	/* a5 */
+	load_x  x16, 13 * portWORD_SIZE( sp )	/* a6 */
+	load_x  x17, 14 * portWORD_SIZE( sp )	/* a7 */
+	load_x  x18, 15 * portWORD_SIZE( sp )	/* s2 */
+	load_x  x19, 16 * portWORD_SIZE( sp )	/* s3 */
+	load_x  x20, 17 * portWORD_SIZE( sp )	/* s4 */
+	load_x  x21, 18 * portWORD_SIZE( sp )	/* s5 */
+	load_x  x22, 19 * portWORD_SIZE( sp )	/* s6 */
+	load_x  x23, 20 * portWORD_SIZE( sp )	/* s7 */
+	load_x  x24, 21 * portWORD_SIZE( sp )	/* s8 */
+	load_x  x25, 22 * portWORD_SIZE( sp )	/* s9 */
+	load_x  x26, 23 * portWORD_SIZE( sp )	/* s10 */
+	load_x  x27, 24 * portWORD_SIZE( sp )	/* s11 */
+	load_x  x28, 25 * portWORD_SIZE( sp )	/* t3 */
+	load_x  x29, 26 * portWORD_SIZE( sp )	/* t4 */
+	load_x  x30, 27 * portWORD_SIZE( sp )	/* t5 */
+	load_x  x31, 28 * portWORD_SIZE( sp )	/* t6 */
+	addi sp, sp, portCONTEXT_SIZE
+
+	mret
+	.endfunc
+/*-----------------------------------------------------------*/
+
+.align 8
+.func
+xPortStartFirstTask:
+
+#if( portasmHAS_CLINT != 0 )
+	/* If there is a clint then interrupts can branch directly to the FreeRTOS
+	trap handler.  Otherwise the interrupt controller will need to be configured
+	outside of this file. */
+	la t0, freertos_risc_v_trap_handler
+	csrw mtvec, t0
+#endif /* portasmHAS_CLILNT */
+
+	load_x  sp, pxCurrentTCB			/* Load pxCurrentTCB. */
+	load_x  sp, 0( sp )				 	/* Read sp from first TCB member. */
+
+	load_x  x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
+
+	portasmRESTORE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
+
+	load_x  t0, 29 * portWORD_SIZE( sp )	/* mstatus */
+	csrrw  x0, mstatus, t0					/* Interrupts enabled from here! */
+
+	load_x  x5, 2 * portWORD_SIZE( sp )		/* t0 */
+	load_x  x6, 3 * portWORD_SIZE( sp )		/* t1 */
+	load_x  x7, 4 * portWORD_SIZE( sp )		/* t2 */
+	load_x  x8, 5 * portWORD_SIZE( sp )		/* s0/fp */
+	load_x  x9, 6 * portWORD_SIZE( sp )		/* s1 */
+	load_x  x10, 7 * portWORD_SIZE( sp )	/* a0 */
+	load_x  x11, 8 * portWORD_SIZE( sp )	/* a1 */
+	load_x  x12, 9 * portWORD_SIZE( sp )	/* a2 */
+	load_x  x13, 10 * portWORD_SIZE( sp )	/* a3 */
+	load_x  x14, 11 * portWORD_SIZE( sp )	/* a4 */
+	load_x  x15, 12 * portWORD_SIZE( sp )	/* a5 */
+	load_x  x16, 13 * portWORD_SIZE( sp )	/* a6 */
+	load_x  x17, 14 * portWORD_SIZE( sp )	/* a7 */
+	load_x  x18, 15 * portWORD_SIZE( sp )	/* s2 */
+	load_x  x19, 16 * portWORD_SIZE( sp )	/* s3 */
+	load_x  x20, 17 * portWORD_SIZE( sp )	/* s4 */
+	load_x  x21, 18 * portWORD_SIZE( sp )	/* s5 */
+	load_x  x22, 19 * portWORD_SIZE( sp )	/* s6 */
+	load_x  x23, 20 * portWORD_SIZE( sp )	/* s7 */
+	load_x  x24, 21 * portWORD_SIZE( sp )	/* s8 */
+	load_x  x25, 22 * portWORD_SIZE( sp )	/* s9 */
+	load_x  x26, 23 * portWORD_SIZE( sp )	/* s10 */
+	load_x  x27, 24 * portWORD_SIZE( sp )	/* s11 */
+	load_x  x28, 25 * portWORD_SIZE( sp )	/* t3 */
+	load_x  x29, 26 * portWORD_SIZE( sp )	/* t4 */
+	load_x  x30, 27 * portWORD_SIZE( sp )	/* t5 */
+	load_x  x31, 28 * portWORD_SIZE( sp )	/* t6 */
+	addi	sp, sp, portCONTEXT_SIZE
+	ret
+	.endfunc
+/*-----------------------------------------------------------*/
+
+/*
+ * Unlike other ports pxPortInitialiseStack() is written in assembly code as it
+ * needs access to the portasmADDITIONAL_CONTEXT_SIZE constant.  The prototype
+ * for the function is as per the other ports:
+ * StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );
+ *
+ * As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in
+ * a1, and pvParameters in a2.  The new top of stack is passed out in a0.
+ *
+ * RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
+ * for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
+ *
+ * Register		ABI Name	Description						Saver
+ * x0			zero		Hard-wired zero					-
+ * x1			ra			Return address					Caller
+ * x2			sp			Stack pointer					Callee
+ * x3			gp			Global pointer					-
+ * x4			tp			Thread pointer					-
+ * x5-7			t0-2		Temporaries						Caller
+ * x8			s0/fp		Saved register/Frame pointer	Callee
+ * x9			s1			Saved register					Callee
+ * x10-11		a0-1		Function Arguments/return values Caller
+ * x12-17		a2-7		Function arguments				Caller
+ * x18-27		s2-11		Saved registers					Callee
+ * x28-31		t3-6		Temporaries						Caller
+ *
+ * The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
+ * where the global and thread pointers are currently assumed to be constant so
+ * are not saved:
+ *
+ * mstatus
+ * x31
+ * x30
+ * x29
+ * x28
+ * x27
+ * x26
+ * x25
+ * x24
+ * x23
+ * x22
+ * x21
+ * x20
+ * x19
+ * x18
+ * x17
+ * x16
+ * x15
+ * x14
+ * x13
+ * x12
+ * x11
+ * pvParameters
+ * x9
+ * x8
+ * x7
+ * x6
+ * x5
+ * portTASK_RETURN_ADDRESS
+ * [chip specific registers go here]
+ * pxCode
+ */
+.align 8
+.func
+pxPortInitialiseStack:
+
+	csrr t0, mstatus					/* Obtain current mstatus value. */
+	addi t1, x0, 0x188					/* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
+	slli t1, t1, 4
+	or t0, t0, t1						/* Set MPIE and MPP bits in mstatus value. */
+
+	addi a0, a0, -portWORD_SIZE
+	store_x t0, 0(a0)					/* mstatus onto the stack. */
+	addi a0, a0, -(22 * portWORD_SIZE)	/* Space for registers x11-x31. */
+	store_x a2, 0(a0)					/* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
+	addi a0, a0, -(6 * portWORD_SIZE)	/* Space for registers x5-x9. */
+	store_x x0, 0(a0)					/* Return address onto the stack, could be portTASK_RETURN_ADDRESS */
+	addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
+chip_specific_stack_frame:				/* First add any chip specific registers to the stack frame being created. */
+	beq t0, x0, 1f						/* No more chip specific registers to save. */
+	addi a0, a0, -portWORD_SIZE			/* Make space for chip specific register. */
+	store_x x0, 0(a0)					/* Give the chip specific register an initial value of zero. */
+	addi t0, t0, -1						/* Decrement the count of chip specific registers remaining. */
+	j chip_specific_stack_frame			/* Until no more chip specific registers. */
+1:
+	addi a0, a0, -portWORD_SIZE
+	store_x a1, 0(a0)					/* mret value (pxCode parameter) onto the stack. */
+	ret
+	.endfunc
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RISC-V/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RISC-V/portmacro.h
new file mode 100644
index 0000000..fac3c89
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RISC-V/portmacro.h
@@ -0,0 +1,155 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#if __riscv_xlen == 64
+	#define portSTACK_TYPE			uint64_t
+	#define portBASE_TYPE			int64_t
+	#define portUBASE_TYPE			uint64_t
+	#define portMAX_DELAY 			( TickType_t ) 0xffffffffffffffffUL
+	#define portPOINTER_SIZE_TYPE 	uint64_t
+#elif __riscv_xlen == 32
+	#define portSTACK_TYPE	uint32_t
+	#define portBASE_TYPE	int32_t
+	#define portUBASE_TYPE	uint32_t
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#else
+	#error Assembler did not define __riscv_xlen
+#endif
+
+
+typedef portSTACK_TYPE StackType_t;
+typedef portBASE_TYPE BaseType_t;
+typedef portUBASE_TYPE UBaseType_t;
+typedef portUBASE_TYPE TickType_t;
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#ifdef __riscv64
+	#error This is the RV32 port that has not yet been adapted for 64.
+	#define portBYTE_ALIGNMENT			16
+#else
+	#define portBYTE_ALIGNMENT 8
+#endif
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+extern void vTaskSwitchContext( void );
+#define portYIELD() __asm volatile( "ecall" );
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vTaskSwitchContext()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+#define portCRITICAL_NESTING_IN_TCB					1
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+
+#define portSET_INTERRUPT_MASK_FROM_ISR() 0
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
+#define portDISABLE_INTERRUPTS()	__asm volatile( "csrc mstatus, 8" )
+#define portENABLE_INTERRUPTS()		__asm volatile( "csrs mstatus, 8" )
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - __builtin_clz( uxReadyPriorities ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+/*-----------------------------------------------------------*/
+
+#define portNOP() __asm volatile 	( " nop " )
+
+#define portINLINE	__inline
+
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE inline __attribute__(( always_inline))
+#endif
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RISC-V/readme.txt b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RISC-V/readme.txt
new file mode 100644
index 0000000..69d98d9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RISC-V/readme.txt
@@ -0,0 +1,23 @@
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
+ *
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ *   is common to all currently supported RISC-V chips.  There is only one
+ *   portASM.S file because the same file is built for all RISC-V target chips.
+ *
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
+ *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
+ *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
+ *   as there are multiple RISC-V chip implementations.
+ *
+ * !!!NOTE!!!
+ * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
+ * HEADER FILE FOR THE CHIP IN USE.  This is done using the assembler's (not the
+ * compiler's!) include path.  For example, if the chip in use includes a core
+ * local interrupter (CLINT) and does not include any chip specific register
+ * extensions then add the path below to the assembler's include path:
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ *
+ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RL78/isr_support.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RL78/isr_support.h
new file mode 100644
index 0000000..3265b18
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RL78/isr_support.h
@@ -0,0 +1,126 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Variables used by scheduler */
+	.extern    _pxCurrentTCB
+	.extern    _usCriticalNesting
+
+/*
+ * portSAVE_CONTEXT MACRO
+ * Saves the context of the general purpose registers, CS and ES (only in far
+ * memory mode) registers the usCriticalNesting Value and the Stack Pointer
+ * of the active Task onto the task stack
+ */
+	.macro portSAVE_CONTEXT
+
+	SEL 	RB0
+
+	/* Save AX Register to stack. */
+	PUSH	AX
+	PUSH	HL
+	/* Save CS register. */
+	MOV 	A, CS
+	XCH		A, X
+	/* Save ES register. */
+	MOV		A, ES
+	PUSH	AX
+	/* Save the remaining general purpose registers from bank 0. */
+	PUSH	DE
+	PUSH	BC
+	/* Save the other register banks - only necessary in the GCC port. */
+	SEL		RB1
+	PUSH	AX
+	PUSH	BC
+	PUSH	DE
+	PUSH	HL
+	SEL		RB2
+	PUSH	AX
+	PUSH	BC
+	PUSH	DE
+	PUSH	HL
+	/* Registers in bank 3 are for ISR use only so don't need saving. */
+	SEL		RB0
+	/* Save the usCriticalNesting value. */
+	MOVW	AX, !_usCriticalNesting
+	PUSH	AX
+	/* Save the Stack pointer. */
+	MOVW	AX, !_pxCurrentTCB
+	MOVW	HL, AX
+	MOVW	AX, SP
+	MOVW	[HL], AX
+	/* Switch stack pointers. */
+	movw sp,#_stack /* Set stack pointer */
+
+	.endm
+
+
+/*
+ * portRESTORE_CONTEXT MACRO
+ * Restores the task Stack Pointer then use this to restore usCriticalNesting,
+ * general purpose registers and the CS and ES (only in far memory mode)
+ * of the selected task from the task stack
+ */
+.macro portRESTORE_CONTEXT MACRO
+	SEL		RB0
+	/* Restore the Stack pointer. */
+	MOVW	AX, !_pxCurrentTCB
+	MOVW	HL, AX
+	MOVW	AX, [HL]
+	MOVW	SP, AX
+	/* Restore usCriticalNesting value. */
+	POP		AX
+	MOVW	!_usCriticalNesting, AX
+	/* Restore the alternative register banks - only necessary in the GCC
+	port.  Register bank 3 is dedicated for interrupts use so is not saved or
+	restored. */
+	SEL		RB2
+	POP		HL
+	POP		DE
+	POP		BC
+	POP		AX
+	SEL		RB1
+	POP		HL
+	POP		DE
+	POP		BC
+	POP		AX
+	SEL		RB0
+	/* Restore the necessary general purpose registers. */
+	POP		BC
+	POP		DE
+	/* Restore the ES register. */
+	POP		AX
+	MOV		ES, A
+	/* Restore the CS register. */
+	XCH		A, X
+	MOV		CS, A
+	/* Restore general purpose register HL. */
+	POP		HL
+	/* Restore AX. */
+	POP		AX
+
+	.endm
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RL78/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RL78/port.c
new file mode 100644
index 0000000..3fb8d12
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RL78/port.c
@@ -0,0 +1,211 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* The critical nesting value is initialised to a non zero value to ensure
+interrupts don't accidentally become enabled before the scheduler is started. */
+#define portINITIAL_CRITICAL_NESTING  ( ( uint16_t ) 10 )
+
+/* Initial PSW value allocated to a newly created task.
+ *   11000110
+ *   ||||||||-------------- Fill byte
+ *   |||||||--------------- Carry Flag cleared
+ *   |||||----------------- In-service priority Flags set to low level
+ *   ||||------------------ Register bank Select 0 Flag cleared
+ *   |||------------------- Auxiliary Carry Flag cleared
+ *   ||-------------------- Register bank Select 1 Flag cleared
+ *   |--------------------- Zero Flag set
+ *   ---------------------- Global Interrupt Flag set (enabled)
+ */
+#define portPSW		  ( 0xc6UL )
+
+/* Each task maintains a count of the critical section nesting depth.  Each time
+a critical section is entered the count is incremented.  Each time a critical
+section is exited the count is decremented - with interrupts only being
+re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as that could cause problems during the startup
+sequence. */
+volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.
+ */
+__attribute__((weak)) void vApplicationSetupTimerInterrupt( void );
+
+/*
+ * Starts the scheduler by loading the context of the first task to run.
+ * (defined in portasm.S).
+ */
+extern void vPortStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint32_t *pulLocal;
+
+	/* Stack type and pointers to the stack type are both 2 bytes. */
+
+	/* Parameters are passed in on the stack, and written using a 32bit value
+	hence a space is left for the second two bytes. */
+	pxTopOfStack--;
+
+	/* Write in the parameter value. */
+	pulLocal =  ( uint32_t * ) pxTopOfStack;
+	*pulLocal = ( StackType_t ) pvParameters;
+	pxTopOfStack--;
+
+	/* The return address, leaving space for the first two bytes of	the
+	32-bit value. */
+	pxTopOfStack--;
+	pulLocal = ( uint32_t * ) pxTopOfStack;
+	*pulLocal = ( uint32_t ) 0;
+	pxTopOfStack--;
+
+	/* The start address / PSW value is also written in as a 32bit value,
+	so leave a space for the second two bytes. */
+	pxTopOfStack--;
+
+	/* Task function start address combined with the PSW. */
+	pulLocal = ( uint32_t * ) pxTopOfStack;
+	*pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
+	pxTopOfStack--;
+
+	/* An initial value for the AX register. */
+	*pxTopOfStack = ( StackType_t ) 0x1111;
+	pxTopOfStack--;
+
+	/* An initial value for the HL register. */
+	*pxTopOfStack = ( StackType_t ) 0x2222;
+	pxTopOfStack--;
+
+	/* CS and ES registers. */
+	*pxTopOfStack = ( StackType_t ) 0x0F00;
+	pxTopOfStack--;
+
+	/* The remaining general purpose registers bank 0 (DE and BC) and the other
+	two register banks...register bank 3 is dedicated for use by interrupts so
+	is not saved as part of the task context. */
+	pxTopOfStack -= 10;
+
+	/* Finally the critical section nesting count is set to zero when the task
+	first starts. */
+	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
+
+	/* Return a pointer to the top of the stack that has beene generated so it
+	can	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xPortStartScheduler( void )
+{
+	/* Setup the hardware to generate the tick.  Interrupts are disabled when
+	this function is called. */
+	vApplicationSetupTimerInterrupt();
+
+	/* Restore the context of the first task that is going to run. */
+	vPortStartFirstTask();
+
+	/* Execution should not reach here as the tasks are now running! */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the RL78 port will get stopped. */
+}
+/*-----------------------------------------------------------*/
+
+__attribute__((weak)) void vApplicationSetupTimerInterrupt( void )
+{
+const uint16_t usClockHz = 15000UL; /* Internal clock. */
+const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL;
+
+	/* Use the internal 15K clock. */
+	OSMC = ( unsigned char ) 0x16;
+
+	#ifdef RTCEN
+	{
+		/* Supply the interval timer clock. */
+		RTCEN = ( unsigned char ) 1U;
+
+		/* Disable INTIT interrupt. */
+		ITMK = ( unsigned char ) 1;
+
+		/* Disable ITMC operation. */
+		ITMC = ( unsigned char ) 0x0000;
+
+		/* Clear INIT interrupt. */
+		ITIF = ( unsigned char ) 0;
+
+		/* Set interval and enable interrupt operation. */
+		ITMC = usCompareMatch | 0x8000U;
+
+		/* Enable INTIT interrupt. */
+		ITMK = ( unsigned char ) 0;
+	}
+	#endif
+
+	#ifdef TMKAEN
+	{
+		/* Supply the interval timer clock. */
+		TMKAEN = ( unsigned char ) 1U;
+
+		/* Disable INTIT interrupt. */
+		TMKAMK = ( unsigned char ) 1;
+
+		/* Disable ITMC operation. */
+		ITMC = ( unsigned char ) 0x0000;
+
+		/* Clear INIT interrupt. */
+		TMKAIF = ( unsigned char ) 0;
+
+		/* Set interval and enable interrupt operation. */
+		ITMC = usCompareMatch | 0x8000U;
+
+		/* Enable INTIT interrupt. */
+		TMKAMK = ( unsigned char ) 0;
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RL78/portasm.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RL78/portasm.S
new file mode 100644
index 0000000..275f6b9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RL78/portasm.S
@@ -0,0 +1,80 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "FreeRTOSConfig.h"
+#include "ISR_Support.h"
+
+	.global    _vPortYield
+	.global    _vPortStartFirstTask
+	.global    _vPortTickISR
+
+	.extern    _vTaskSwitchContext
+	.extern    _xTaskIncrementTick
+
+	.text
+	.align 2
+
+/* FreeRTOS yield handler.  This is installed as the BRK software interrupt
+handler. */
+_vPortYield:
+	/* Save the context of the current task. */
+	portSAVE_CONTEXT
+	/* Call the scheduler to select the next task. */
+	call      !!_vTaskSwitchContext
+	/* Restore the context of the next task to run. */
+	portRESTORE_CONTEXT
+	retb
+
+
+/* Starts the scheduler by restoring the context of the task that will execute
+first. */
+	.align 2
+_vPortStartFirstTask:
+	/* Restore the context of whichever task will execute first. */
+	portRESTORE_CONTEXT
+	/* An interrupt stack frame is used so the task is started using RETI. */
+	reti
+
+/* FreeRTOS tick handler.  This is installed as the interval timer interrupt
+handler. */
+	.align 2
+_vPortTickISR:
+
+	/* Save the context of the currently executing task. */
+	portSAVE_CONTEXT
+	/* Call the RTOS tick function. */
+	call      !!_xTaskIncrementTick
+#if configUSE_PREEMPTION == 1
+	/* Select the next task to run. */
+	call      !!_vTaskSwitchContext
+#endif
+	/* Retore the context of whichever task will run next. */
+	portRESTORE_CONTEXT
+	reti
+
+	.end
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RL78/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RL78/portmacro.h
new file mode 100644
index 0000000..d2231ef
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RL78/portmacro.h
@@ -0,0 +1,121 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE	uint16_t
+#define portBASE_TYPE   short
+#define portPOINTER_SIZE_TYPE uint16_t
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS() __asm volatile ( "DI" )
+#define portENABLE_INTERRUPTS()	 __asm volatile ( "EI" )
+/*-----------------------------------------------------------*/
+
+/* Critical section control macros. */
+#define portNO_CRITICAL_SECTION_NESTING		( ( unsigned short ) 0 )
+
+#define portENTER_CRITICAL()													\
+{																				\
+extern volatile uint16_t usCriticalNesting;										\
+																				\
+	portDISABLE_INTERRUPTS();													\
+																				\
+	/* Now interrupts are disabled ulCriticalNesting can be accessed */			\
+	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
+	/* times portENTER_CRITICAL() has been called. */							\
+	usCriticalNesting++;														\
+}
+
+#define portEXIT_CRITICAL()														\
+{																				\
+extern volatile uint16_t usCriticalNesting;										\
+																				\
+	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
+	{																			\
+		/* Decrement the nesting count as we are leaving a critical section. */	\
+		usCriticalNesting--;													\
+																				\
+		/* If the nesting level has reached zero then interrupts should be */	\
+		/* re-enabled. */														\
+		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
+		{																		\
+			portENABLE_INTERRUPTS();											\
+		}																		\
+	}																			\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+#define portYIELD() 	__asm volatile ( "BRK" )
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext()
+#define portNOP()	__asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Hardwware specifics. */
+#define portBYTE_ALIGNMENT	2
+#define portSTACK_GROWTH	( -1 )
+#define portTICK_PERIOD_MS	( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RX100/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RX100/port.c
new file mode 100644
index 0000000..63adc01
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RX100/port.c
@@ -0,0 +1,674 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
+
+/* Standard C includes. */
+#include "limits.h"
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#include "iodefine.h"
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
+
+/* The peripheral clock is divided by this value before being supplying the
+CMT. */
+#if ( configUSE_TICKLESS_IDLE == 0 )
+	/* If tickless idle is not used then the divisor can be fixed. */
+	#define portCLOCK_DIVISOR	8UL
+#elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
+	#define portCLOCK_DIVISOR	512UL
+#elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
+	#define portCLOCK_DIVISOR	128UL
+#elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
+	#define portCLOCK_DIVISOR	32UL
+#else
+	#define portCLOCK_DIVISOR	8UL
+#endif
+
+/* These macros allow a critical section to be added around the call to
+xTaskIncrementTick(), which is only ever called from interrupts at the kernel
+priority - ie a known priority.  Therefore these local macros are a slight
+optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
+which would require the old IPL to be read first and stored in a local variable. */
+#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() 	__asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() 	__asm volatile ( "MVTIPL	%0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
+
+/* Keys required to lock and unlock access to certain system registers
+respectively. */
+#define portUNLOCK_KEY		0xA50B
+#define portLOCK_KEY		0xA500
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+static void prvStartFirstTask( void ) __attribute__((naked));
+
+/*
+ * Software interrupt handler.  Performs the actual context switch (saving and
+ * restoring of registers).  Written in asm code as direct register access is
+ * required.
+ */
+void vPortSoftwareInterruptISR( void ) __attribute__((naked));
+
+/*
+ * The tick interrupt handler.
+ */
+void vPortTickISR( void ) __attribute__((interrupt));
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick using the CMT.
+ * The application writer can define configSETUP_TICK_INTERRUPT() (in
+ * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
+ * in place of prvSetupTimerInterrupt().
+ */
+static void prvSetupTimerInterrupt( void );
+#ifndef configSETUP_TICK_INTERRUPT
+	/* The user has not provided their own tick interrupt configuration so use
+    the definition in this file (which uses the interval timer). */
+	#define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
+#endif /* configSETUP_TICK_INTERRUPT */
+
+/*
+ * Called after the sleep mode registers have been configured, prvSleep()
+ * executes the pre and post sleep macros, and actually calls the wait
+ * instruction.
+ */
+#if configUSE_TICKLESS_IDLE == 1
+	static void prvSleep( TickType_t xExpectedIdleTime );
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*-----------------------------------------------------------*/
+
+/* Used in the context save and restore code. */
+extern void *pxCurrentTCB;
+
+/* Calculate how many clock increments make up a single tick period. */
+static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
+
+#if configUSE_TICKLESS_IDLE == 1
+
+	/* Holds the maximum number of ticks that can be suppressed - which is
+	basically how far into the future an interrupt can be generated. Set
+	during initialisation.  This is the maximum possible value that the
+	compare match register can hold divided by ulMatchValueForOneTick. */
+	static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
+
+	/* Flag set from the tick interrupt to allow the sleep processing to know if
+	sleep mode was exited because of a tick interrupt, or an interrupt
+	generated by something else. */
+	static volatile uint32_t ulTickFlag = pdFALSE;
+
+	/* The CMT counter is stopped temporarily each time it is re-programmed.
+	The following constant offsets the CMT counter match value by the number of
+	CMT	counts that would typically be missed while the counter was stopped to
+	compensate for the lost time.  The large difference between the divided CMT
+	clock and the CPU clock means it is likely ulStoppedTimerCompensation will
+	equal zero - and be optimised away. */
+	static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Offset to end up on 8 byte boundary. */
+	pxTopOfStack--;
+
+	/* R0 is not included as it is the stack pointer. */
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+    *pxTopOfStack = 0x00;
+	pxTopOfStack--;
+ 	*pxTopOfStack = portINITIAL_PSW;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;
+
+	/* When debugging it can be useful if every register is set to a known
+	value.  Otherwise code space can be saved by just setting the registers
+	that need to be set. */
+	#ifdef USE_FULL_REGISTER_INITIALISATION
+	{
+		pxTopOfStack--;
+		*pxTopOfStack = 0x12345678;	/* r15. */
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaabbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xdddddddd;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xcccccccc;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xbbbbbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaaaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x99999999;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x88888888;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x77777777;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x66666666;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x55555555;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x44444444;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x33333333;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x22222222;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		/* Leave space for the registers that will get popped from the stack
+		when the task first starts executing. */
+		pxTopOfStack -= 15;
+	}
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x12345678; /* Accumulator. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x87654321; /* Accumulator. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Use pxCurrentTCB just so it does not get optimised away. */
+	if( pxCurrentTCB != NULL )
+	{
+		/* Call an application function to set up the timer that will generate
+		the tick interrupt.  This way the application can decide which
+		peripheral to use.  If tickless mode is used then the default
+		implementation defined in this file (which uses CMT0) should not be
+		overridden. */
+		configSETUP_TICK_INTERRUPT();
+
+		/* Enable the software interrupt. */
+		_IEN( _ICU_SWINT ) = 1;
+
+		/* Ensure the software interrupt is clear. */
+		_IR( _ICU_SWINT ) = 0;
+
+		/* Ensure the software interrupt is set to the kernel priority. */
+		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+		/* Start the first task. */
+		prvStartFirstTask();
+	}
+
+	/* Execution should not reach here as the tasks are now running!
+	prvSetupTimerInterrupt() is called here to prevent the compiler outputting
+	a warning about a statically declared function not being referenced in the
+	case that the application writer has provided their own tick interrupt
+	configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
+	their own routine will be called in place of prvSetupTimerInterrupt()). */
+	prvSetupTimerInterrupt();
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( pxCurrentTCB == NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvStartFirstTask( void )
+{
+	__asm volatile
+	(
+		/* When starting the scheduler there is nothing that needs moving to the
+		interrupt stack because the function is not called from an interrupt.
+		Just ensure the current stack is the user stack. */
+		"SETPSW		U						\n" \
+
+		/* Obtain the location of the stack associated with which ever task
+		pxCurrentTCB is currently pointing to. */
+		"MOV.L		#_pxCurrentTCB, R15		\n" \
+		"MOV.L		[R15], R15				\n" \
+		"MOV.L		[R15], R0				\n" \
+
+		/* Restore the registers from the stack of the task pointed to by
+		pxCurrentTCB. */
+	    "POP		R15						\n" \
+
+		/* Accumulator low 32 bits. */
+	    "MVTACLO	R15 					\n" \
+	    "POP		R15						\n" \
+
+		/* Accumulator high 32 bits. */
+	    "MVTACHI	R15 					\n" \
+
+		/* R1 to R15 - R0 is not included as it is the SP. */
+	    "POPM		R1-R15 					\n" \
+
+		/* This pops the remaining registers. */
+	    "RTE								\n" \
+	    "NOP								\n" \
+	    "NOP								\n"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vPortSoftwareInterruptISR( void )
+{
+	__asm volatile
+	(
+		/* Re-enable interrupts. */
+		"SETPSW		I							\n" \
+
+		/* Move the data that was automatically pushed onto the interrupt stack when
+		the interrupt occurred from the interrupt stack to the user stack.
+
+		R15 is saved before it is clobbered. */
+		"PUSH.L		R15							\n" \
+
+		/* Read the user stack pointer. */
+		"MVFC		USP, R15					\n" \
+
+		/* Move the address down to the data being moved. */
+		"SUB		#12, R15					\n" \
+		"MVTC		R15, USP					\n" \
+
+		/* Copy the data across, R15, then PC, then PSW. */
+		"MOV.L		[ R0 ], [ R15 ]				\n" \
+		"MOV.L 		4[ R0 ], 4[ R15 ]			\n" \
+		"MOV.L		8[ R0 ], 8[ R15 ]			\n" \
+
+		/* Move the interrupt stack pointer to its new correct position. */
+		"ADD		#12, R0						\n" \
+
+		/* All the rest of the registers are saved directly to the user stack. */
+		"SETPSW		U							\n" \
+
+		/* Save the rest of the general registers (R15 has been saved already). */
+		"PUSHM		R1-R14						\n" \
+
+		/* Save the accumulator. */
+		"MVFACHI 	R15							\n" \
+		"PUSH.L		R15							\n" \
+
+		/* Middle word. */
+		"MVFACMI	R15							\n" \
+
+		/* Shifted left as it is restored to the low order word. */
+		"SHLL		#16, R15					\n" \
+		"PUSH.L		R15							\n" \
+
+		/* Save the stack pointer to the TCB. */
+		"MOV.L		#_pxCurrentTCB, R15			\n" \
+		"MOV.L		[ R15 ], R15				\n" \
+		"MOV.L		R0, [ R15 ]					\n" \
+
+		/* Ensure the interrupt mask is set to the syscall priority while the kernel
+		structures are being accessed. */
+		"MVTIPL		%0 							\n" \
+
+		/* Select the next task to run. */
+		"BSR.A		_vTaskSwitchContext			\n" \
+
+		/* Reset the interrupt mask as no more data structure access is required. */
+		"MVTIPL		%1							\n" \
+
+		/* Load the stack pointer of the task that is now selected as the Running
+		state task from its TCB. */
+		"MOV.L		#_pxCurrentTCB,R15			\n" \
+		"MOV.L		[ R15 ], R15				\n" \
+		"MOV.L		[ R15 ], R0					\n" \
+
+		/* Restore the context of the new task.  The PSW (Program Status Word) and
+		PC will be popped by the RTE instruction. */
+		"POP		R15							\n" \
+		"MVTACLO 	R15							\n" \
+		"POP		R15							\n" \
+		"MVTACHI 	R15							\n" \
+		"POPM		R1-R15						\n" \
+		"RTE									\n" \
+		"NOP									\n" \
+		"NOP									  "
+		:: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vPortTickISR( void )
+{
+	/* Re-enabled interrupts. */
+	__asm volatile( "SETPSW	I" );
+
+	/* Increment the tick, and perform any processing the new tick value
+	necessitates.  Ensure IPL is at the max syscall value first. */
+	portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			taskYIELD();
+		}
+	}
+	portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
+
+	#if configUSE_TICKLESS_IDLE == 1
+	{
+		/* The CPU woke because of a tick. */
+		ulTickFlag = pdTRUE;
+
+		/* If this is the first tick since exiting tickless mode then the CMT
+		compare match value needs resetting. */
+		CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortGetIPL( void )
+{
+	__asm volatile
+	(
+		"MVFC	PSW, R1			\n"	\
+		"SHLR	#24, R1			\n"	\
+		"RTS					  "
+	);
+
+	/* This will never get executed, but keeps the compiler from complaining. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetIPL( uint32_t ulNewIPL )
+{
+	__asm volatile
+	(
+		"PUSH	R5				\n" \
+		"MVFC	PSW, R5			\n"	\
+		"SHLL	#24, R1			\n" \
+		"AND	#-0F000001H, R5 \n" \
+		"OR		R1, R5			\n" \
+		"MVTC	R5, PSW			\n" \
+		"POP	R5				\n" \
+		"RTS					  "
+	 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+	/* Unlock. */
+	SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+
+	/* Enable CMT0. */
+	MSTP( CMT0 ) = 0;
+
+	/* Lock again. */
+	SYSTEM.PRCR.WORD = portLOCK_KEY;
+
+	/* Interrupt on compare match. */
+	CMT0.CMCR.BIT.CMIE = 1;
+
+	/* Set the compare match value. */
+	CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
+
+	/* Divide the PCLK. */
+	#if portCLOCK_DIVISOR == 512
+	{
+		CMT0.CMCR.BIT.CKS = 3;
+	}
+	#elif portCLOCK_DIVISOR == 128
+	{
+		CMT0.CMCR.BIT.CKS = 2;
+	}
+	#elif portCLOCK_DIVISOR == 32
+	{
+		CMT0.CMCR.BIT.CKS = 1;
+	}
+	#elif portCLOCK_DIVISOR == 8
+	{
+		CMT0.CMCR.BIT.CKS = 0;
+	}
+	#else
+	{
+		#error Invalid portCLOCK_DIVISOR setting
+	}
+	#endif
+
+	/* Enable the interrupt... */
+	_IEN( _CMT0_CMI0 ) = 1;
+
+	/* ...and set its priority to the application defined kernel priority. */
+	_IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
+
+	/* Start the timer. */
+	CMT.CMSTR0.BIT.STR0 = 1;
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_TICKLESS_IDLE == 1
+
+	static void prvSleep( TickType_t xExpectedIdleTime )
+	{
+		/* Allow the application to define some pre-sleep processing. */
+		configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
+
+		/* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
+		means the application defined code has already executed the WAIT
+		instruction. */
+		if( xExpectedIdleTime > 0 )
+		{
+			__asm volatile( "WAIT" );
+		}
+
+		/* Allow the application to define some post sleep processing. */
+		configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if configUSE_TICKLESS_IDLE == 1
+
+	void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
+	eSleepModeStatus eSleepAction;
+
+		/* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
+
+		/* Make sure the CMT reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Calculate the reload value required to wait xExpectedIdleTime tick
+		periods. */
+		ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
+		if( ulMatchValue > ulStoppedTimerCompensation )
+		{
+			/* Compensate for the fact that the CMT is going to be stopped
+			momentarily. */
+			ulMatchValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Stop the CMT momentarily.  The time the CMT is stopped for is
+		accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		CMT.CMSTR0.BIT.STR0 = 0;
+		while( CMT.CMSTR0.BIT.STR0 == 1 )
+		{
+			/* Nothing to do here. */
+		}
+
+		/* Critical section using the global interrupt bit as the i bit is
+		automatically reset by the WAIT instruction. */
+		__asm volatile( "CLRPSW i" );
+
+		/* The tick flag is set to false before sleeping.  If it is true when
+		sleep mode is exited then sleep mode was probably exited because the
+		tick was suppressed for the entire xExpectedIdleTime period. */
+		ulTickFlag = pdFALSE;
+
+		/* If a context switch is pending then abandon the low power entry as
+		the context switch might have been pended by an external interrupt that
+		requires processing. */
+		eSleepAction = eTaskConfirmSleepModeStatus();
+		if( eSleepAction == eAbortSleep )
+		{
+			/* Restart tick. */
+			CMT.CMSTR0.BIT.STR0 = 1;
+			__asm volatile( "SETPSW i" );
+		}
+		else if( eSleepAction == eNoTasksWaitingTimeout )
+		{
+		    /* Protection off. */
+		    SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+
+		    /* Ready for software standby with all clocks stopped. */
+			SYSTEM.SBYCR.BIT.SSBY = 1;
+
+		    /* Protection on. */
+		    SYSTEM.PRCR.WORD = portLOCK_KEY;
+
+			/* Sleep until something happens.  Calling prvSleep() will
+			automatically reset the i bit in the PSW. */
+			prvSleep( xExpectedIdleTime );
+
+			/* Restart the CMT. */
+			CMT.CMSTR0.BIT.STR0 = 1;
+		}
+		else
+		{
+		    /* Protection off. */
+		    SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+
+		    /* Ready for deep sleep mode. */
+			SYSTEM.MSTPCRC.BIT.DSLPE = 1;
+			SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
+			SYSTEM.SBYCR.BIT.SSBY = 0;
+
+		    /* Protection on. */
+		    SYSTEM.PRCR.WORD = portLOCK_KEY;
+
+		    /* Adjust the match value to take into account that the current
+			time slice is already partially complete. */
+			ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
+			CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+
+			/* Restart the CMT to count up to the new match value. */
+			CMT0.CMCNT = 0;
+			CMT.CMSTR0.BIT.STR0 = 1;
+
+			/* Sleep until something happens.  Calling prvSleep() will
+			automatically reset the i bit in the PSW. */
+			prvSleep( xExpectedIdleTime );
+
+			/* Stop CMT.  Again, the time the SysTick is stopped for is
+			accounted for as best it can be, but using the tickless mode will
+			inevitably result in some tiny drift of the time maintained by the
+			kernel with	respect to calendar time. */
+			CMT.CMSTR0.BIT.STR0 = 0;
+			while( CMT.CMSTR0.BIT.STR0 == 1 )
+			{
+				/* Nothing to do here. */
+			}
+
+			ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
+
+			if( ulTickFlag != pdFALSE )
+			{
+				/* The tick interrupt has already executed, although because
+				this function is called with the scheduler suspended the actual
+				tick processing will not occur until after this function has
+				exited.  Reset the match value with whatever remains of this
+				tick period. */
+				ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
+				CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+
+				/* The tick interrupt handler will already have pended the tick
+				processing in the kernel.  As the pending tick will be
+				processed as soon as this function exits, the tick value
+				maintained by the tick is stepped forward by one less than the
+				time spent sleeping.  The actual stepping of the tick appears
+				later in this function. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				How	many complete tick periods passed while the processor was
+				sleeping? */
+				ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
+
+				/* The match value is set to whatever fraction of a single tick
+				period remains. */
+				ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
+				CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+			}
+
+			/* Restart the CMT so it runs up to the match value.  The match value
+			will get set to the value required to generate exactly one tick period
+			the next time the CMT interrupt executes. */
+			CMT0.CMCNT = 0;
+			CMT.CMSTR0.BIT.STR0 = 1;
+
+			/* Wind the tick forward by the number of tick periods that the CPU
+			remained in a low power state. */
+			vTaskStepTick( ulCompleteTickPeriods );
+		}
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RX100/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RX100/portmacro.h
new file mode 100644
index 0000000..97bed4a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RX100/portmacro.h
@@ -0,0 +1,144 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			8	/* Could make four, according to manual. */
+#define portSTACK_GROWTH			-1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					__asm volatile( "NOP" )
+
+/* Save clobbered register, set ITU SWINR (at address 0x872E0), read the value
+back to ensure it is set before continuing, then restore the clobbered
+register. */
+#define portYIELD()							\
+	__asm volatile							\
+	(										\
+		"MOV.L #0x872E0, r5			\n\t"	\
+		"MOV.B #1, [r5]				\n\t"	\
+		"MOV.L [r5], r5				\n\t"	\
+		::: "r5"							\
+	)
+
+#define portYIELD_FROM_ISR( x )	if( x != pdFALSE ) { portYIELD(); }
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() 	__asm volatile ( "MVTIPL	#0" )
+#ifdef configASSERT
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+	#define portDISABLE_INTERRUPTS() 	if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#else
+	#define portDISABLE_INTERRUPTS() 	__asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+uint32_t ulPortGetIPL( void ) __attribute__((naked));
+void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
+
+/* Tickless idle/low power functionality. */
+#if configUSE_TICKLESS_IDLE == 1
+	#ifndef portSUPPRESS_TICKS_AND_SLEEP
+		extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+		#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+	#endif
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RX600/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RX600/port.c
new file mode 100644
index 0000000..bafb47f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RX600/port.c
@@ -0,0 +1,358 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#include "iodefine.h"
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
+
+/* These macros allow a critical section to be added around the call to
+xTaskIncrementTick(), which is only ever called from interrupts at the kernel
+priority - ie a known priority.  Therefore these local macros are a slight
+optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
+which would require the old IPL to be read first and stored in a local variable. */
+#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() 	__asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() 	__asm volatile ( "MVTIPL	%0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+static void prvStartFirstTask( void ) __attribute__((naked));
+
+/*
+ * Software interrupt handler.  Performs the actual context switch (saving and
+ * restoring of registers).  Written in asm code as direct register access is
+ * required.
+ */
+void vSoftwareInterruptISR( void ) __attribute__((naked));
+
+/*
+ * The tick interrupt handler.
+ */
+void vTickISR( void ) __attribute__((interrupt));
+
+/*-----------------------------------------------------------*/
+
+extern void *pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* R0 is not included as it is the stack pointer. */
+
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+ 	*pxTopOfStack = portINITIAL_PSW;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;
+
+	/* When debugging it can be useful if every register is set to a known
+	value.  Otherwise code space can be saved by just setting the registers
+	that need to be set. */
+	#ifdef USE_FULL_REGISTER_INITIALISATION
+	{
+		pxTopOfStack--;
+		*pxTopOfStack = 0xffffffff;	/* r15. */
+		pxTopOfStack--;
+		*pxTopOfStack = 0xeeeeeeee;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xdddddddd;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xcccccccc;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xbbbbbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaaaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x99999999;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x88888888;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x77777777;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x66666666;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x55555555;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x44444444;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x33333333;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x22222222;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		pxTopOfStack -= 15;
+	}
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_FPSW;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x12345678; /* Accumulator. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x87654321; /* Accumulator. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vApplicationSetupTimerInterrupt( void );
+
+	/* Use pxCurrentTCB just so it does not get optimised away. */
+	if( pxCurrentTCB != NULL )
+	{
+		/* Call an application function to set up the timer that will generate the
+		tick interrupt.  This way the application can decide which peripheral to
+		use.  A demo application is provided to show a suitable example. */
+		vApplicationSetupTimerInterrupt();
+
+		/* Enable the software interrupt. */
+		_IEN( _ICU_SWINT ) = 1;
+
+		/* Ensure the software interrupt is clear. */
+		_IR( _ICU_SWINT ) = 0;
+
+		/* Ensure the software interrupt is set to the kernel priority. */
+		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+		/* Start the first task. */
+		prvStartFirstTask();
+	}
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( pxCurrentTCB == NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvStartFirstTask( void )
+{
+	__asm volatile
+	(
+		/* When starting the scheduler there is nothing that needs moving to the
+		interrupt stack because the function is not called from an interrupt.
+		Just ensure the current stack is the user stack. */
+		"SETPSW		U						\n" \
+
+		/* Obtain the location of the stack associated with which ever task
+		pxCurrentTCB is currently pointing to. */
+		"MOV.L		#_pxCurrentTCB, R15		\n" \
+		"MOV.L		[R15], R15				\n" \
+		"MOV.L		[R15], R0				\n" \
+
+		/* Restore the registers from the stack of the task pointed to by
+		pxCurrentTCB. */
+	    "POP		R15						\n" \
+
+		/* Accumulator low 32 bits. */
+	    "MVTACLO	R15 					\n" \
+	    "POP		R15						\n" \
+
+		/* Accumulator high 32 bits. */
+	    "MVTACHI	R15 					\n" \
+	    "POP		R15						\n" \
+
+		/* Floating point status word. */
+	    "MVTC		R15, FPSW 				\n" \
+
+		/* R1 to R15 - R0 is not included as it is the SP. */
+	    "POPM		R1-R15 					\n" \
+
+		/* This pops the remaining registers. */
+	    "RTE								\n" \
+	    "NOP								\n" \
+	    "NOP								\n"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vSoftwareInterruptISR( void )
+{
+	__asm volatile
+	(
+		/* Re-enable interrupts. */
+		"SETPSW		I							\n" \
+
+		/* Move the data that was automatically pushed onto the interrupt stack when
+		the interrupt occurred from the interrupt stack to the user stack.
+
+		R15 is saved before it is clobbered. */
+		"PUSH.L		R15							\n" \
+
+		/* Read the user stack pointer. */
+		"MVFC		USP, R15					\n" \
+
+		/* Move the address down to the data being moved. */
+		"SUB		#12, R15					\n" \
+		"MVTC		R15, USP					\n" \
+
+		/* Copy the data across, R15, then PC, then PSW. */
+		"MOV.L		[ R0 ], [ R15 ]				\n" \
+		"MOV.L 		4[ R0 ], 4[ R15 ]			\n" \
+		"MOV.L		8[ R0 ], 8[ R15 ]			\n" \
+
+		/* Move the interrupt stack pointer to its new correct position. */
+		"ADD		#12, R0						\n" \
+
+		/* All the rest of the registers are saved directly to the user stack. */
+		"SETPSW		U							\n" \
+
+		/* Save the rest of the general registers (R15 has been saved already). */
+		"PUSHM		R1-R14						\n" \
+
+		/* Save the FPSW and accumulator. */
+		"MVFC		FPSW, R15					\n" \
+		"PUSH.L		R15							\n" \
+		"MVFACHI 	R15							\n" \
+		"PUSH.L		R15							\n" \
+
+		/* Middle word. */
+		"MVFACMI	R15							\n" \
+
+		/* Shifted left as it is restored to the low order word. */
+		"SHLL		#16, R15					\n" \
+		"PUSH.L		R15							\n" \
+
+		/* Save the stack pointer to the TCB. */
+		"MOV.L		#_pxCurrentTCB, R15			\n" \
+		"MOV.L		[ R15 ], R15				\n" \
+		"MOV.L		R0, [ R15 ]					\n" \
+
+		/* Ensure the interrupt mask is set to the syscall priority while the kernel
+		structures are being accessed. */
+		"MVTIPL		%0 							\n" \
+
+		/* Select the next task to run. */
+		"BSR.A		_vTaskSwitchContext			\n" \
+
+		/* Reset the interrupt mask as no more data structure access is required. */
+		"MVTIPL		%1							\n" \
+
+		/* Load the stack pointer of the task that is now selected as the Running
+		state task from its TCB. */
+		"MOV.L		#_pxCurrentTCB,R15			\n" \
+		"MOV.L		[ R15 ], R15				\n" \
+		"MOV.L		[ R15 ], R0					\n" \
+
+		/* Restore the context of the new task.  The PSW (Program Status Word) and
+		PC will be popped by the RTE instruction. */
+		"POP		R15							\n" \
+		"MVTACLO 	R15							\n" \
+		"POP		R15							\n" \
+		"MVTACHI 	R15							\n" \
+		"POP		R15							\n" \
+		"MVTC		R15, FPSW					\n" \
+		"POPM		R1-R15						\n" \
+		"RTE									\n" \
+		"NOP									\n" \
+		"NOP									  "
+		:: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vTickISR( void )
+{
+	/* Re-enabled interrupts. */
+	__asm volatile( "SETPSW	I" );
+
+	/* Increment the tick, and perform any processing the new tick value
+	necessitates.  Ensure IPL is at the max syscall value first. */
+	portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			taskYIELD();
+		}
+	}
+	portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortGetIPL( void )
+{
+	__asm volatile
+	(
+		"MVFC	PSW, R1			\n"	\
+		"SHLR	#24, R1			\n"	\
+		"RTS					  "
+	);
+
+	/* This will never get executed, but keeps the compiler from complaining. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetIPL( uint32_t ulNewIPL )
+{
+	__asm volatile
+	(
+		"PUSH	R5				\n" \
+		"MVFC	PSW, R5			\n"	\
+		"SHLL	#24, R1			\n" \
+		"AND	#-0F000001H, R5 \n" \
+		"OR		R1, R5			\n" \
+		"MVTC	R5, PSW			\n" \
+		"POP	R5				\n" \
+		"RTS					  "
+	 );
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RX600/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RX600/portmacro.h
new file mode 100644
index 0000000..0bafa1e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RX600/portmacro.h
@@ -0,0 +1,138 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			8	/* Could make four, according to manual. */
+#define portSTACK_GROWTH			-1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					__asm volatile( "NOP" )
+
+/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
+where portITU_SWINTR is the location of the software interrupt register
+(0x000872E0).  Don't rely on the assembler to select a register, so instead
+save and restore clobbered registers manually. */
+#define portYIELD()							\
+	__asm volatile 							\
+	(										\
+		"PUSH.L	R10					\n"		\
+		"MOV.L	#0x872E0, R10		\n"		\
+		"MOV.B	#0x1, [R10]			\n"		\
+		"MOV.L	[R10], R10			\n"		\
+		"POP	R10					\n"		\
+	)
+
+#define portYIELD_FROM_ISR( x )	if( x != pdFALSE ) portYIELD()
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() 	__asm volatile ( "MVTIPL	#0" )
+#ifdef configASSERT
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+	#define portDISABLE_INTERRUPTS() 	if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#else
+	#define portDISABLE_INTERRUPTS() 	__asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+uint32_t ulPortGetIPL( void ) __attribute__((naked));
+void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RX600v2/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RX600v2/port.c
new file mode 100644
index 0000000..809a194
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RX600v2/port.c
@@ -0,0 +1,407 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#include "iodefine.h"
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
+
+/* These macros allow a critical section to be added around the call to
+xTaskIncrementTick(), which is only ever called from interrupts at the kernel
+priority - ie a known priority.  Therefore these local macros are a slight
+optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
+which would require the old IPL to be read first and stored in a local variable. */
+#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() 	__asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() 	__asm volatile ( "MVTIPL	%0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+static void prvStartFirstTask( void ) __attribute__((naked));
+
+/*
+ * Software interrupt handler.  Performs the actual context switch (saving and
+ * restoring of registers).  Written in asm code as direct register access is
+ * required.
+ */
+void vSoftwareInterruptISR( void ) __attribute__((naked));
+
+/*
+ * The tick interrupt handler.
+ */
+void vTickISR( void ) __attribute__((interrupt));
+
+/*-----------------------------------------------------------*/
+
+extern void *pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* R0 is not included as it is the stack pointer. */
+
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+ 	*pxTopOfStack = portINITIAL_PSW;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;
+
+	/* When debugging it can be useful if every register is set to a known
+	value.  Otherwise code space can be saved by just setting the registers
+	that need to be set. */
+	#ifdef USE_FULL_REGISTER_INITIALISATION
+	{
+		pxTopOfStack--;
+		*pxTopOfStack = 0xffffffff;	/* r15. */
+		pxTopOfStack--;
+		*pxTopOfStack = 0xeeeeeeee;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xdddddddd;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xcccccccc;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xbbbbbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaaaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x99999999;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x88888888;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x77777777;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x66666666;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x55555555;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x44444444;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x33333333;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x22222222;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		pxTopOfStack -= 15;
+	}
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_FPSW;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x11111111; /* Accumulator 0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22222222; /* Accumulator 0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33333333; /* Accumulator 0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x44444444; /* Accumulator 1. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x55555555; /* Accumulator 1. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x66666666; /* Accumulator 1. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vApplicationSetupTimerInterrupt( void );
+
+	/* Use pxCurrentTCB just so it does not get optimised away. */
+	if( pxCurrentTCB != NULL )
+	{
+		/* Call an application function to set up the timer that will generate the
+		tick interrupt.  This way the application can decide which peripheral to
+		use.  A demo application is provided to show a suitable example. */
+		vApplicationSetupTimerInterrupt();
+
+		/* Enable the software interrupt. */
+		_IEN( _ICU_SWINT ) = 1;
+
+		/* Ensure the software interrupt is clear. */
+		_IR( _ICU_SWINT ) = 0;
+
+		/* Ensure the software interrupt is set to the kernel priority. */
+		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+		/* Start the first task. */
+		prvStartFirstTask();
+	}
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( pxCurrentTCB == NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvStartFirstTask( void )
+{
+	__asm volatile
+	(
+		/* When starting the scheduler there is nothing that needs moving to the
+		interrupt stack because the function is not called from an interrupt.
+		Just ensure the current stack is the user stack. */
+		"SETPSW		U						\n" \
+
+		/* Obtain the location of the stack associated with which ever task
+		pxCurrentTCB is currently pointing to. */
+		"MOV.L		#_pxCurrentTCB, R15		\n" \
+		"MOV.L		[R15], R15				\n" \
+		"MOV.L		[R15], R0				\n" \
+
+		/* Restore the registers from the stack of the task pointed to by
+		pxCurrentTCB. */
+	    "POP		R15						\n" \
+
+		/* Accumulator low 32 bits. */
+	    "MVTACLO	R15, A0					\n" \
+	    "POP		R15						\n" \
+
+	    /* Accumulator high 32 bits. */
+	    "MVTACHI	R15, A0					\n" \
+	    "POP		R15						\n" \
+
+	    /* Accumulator guard. */
+	    "MVTACGU	R15, A0					\n" \
+	    "POP		R15						\n" \
+
+	    /* Accumulator low 32 bits. */
+	    "MVTACLO	R15, A1					\n" \
+	    "POP		R15						\n" \
+
+	    /* Accumulator high 32 bits. */
+	    "MVTACHI	R15, A1					\n" \
+	    "POP		R15						\n" \
+
+	    /* Accumulator guard. */
+	    "MVTACGU	R15, A1					\n" \
+	    "POP		R15						\n" \
+
+		/* Floating point status word. */
+	    "MVTC		R15, FPSW 				\n" \
+
+		/* R1 to R15 - R0 is not included as it is the SP. */
+	    "POPM		R1-R15 					\n" \
+
+		/* This pops the remaining registers. */
+	    "RTE								\n" \
+	    "NOP								\n" \
+	    "NOP								\n"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vSoftwareInterruptISR( void )
+{
+	__asm volatile
+	(
+		/* Re-enable interrupts. */
+		"SETPSW		I							\n" \
+
+		/* Move the data that was automatically pushed onto the interrupt stack when
+		the interrupt occurred from the interrupt stack to the user stack.
+
+		R15 is saved before it is clobbered. */
+		"PUSH.L		R15							\n" \
+
+		/* Read the user stack pointer. */
+		"MVFC		USP, R15					\n" \
+
+		/* Move the address down to the data being moved. */
+		"SUB		#12, R15					\n" \
+		"MVTC		R15, USP					\n" \
+
+		/* Copy the data across, R15, then PC, then PSW. */
+		"MOV.L		[ R0 ], [ R15 ]				\n" \
+		"MOV.L 		4[ R0 ], 4[ R15 ]			\n" \
+		"MOV.L		8[ R0 ], 8[ R15 ]			\n" \
+
+		/* Move the interrupt stack pointer to its new correct position. */
+		"ADD		#12, R0						\n" \
+
+		/* All the rest of the registers are saved directly to the user stack. */
+		"SETPSW		U							\n" \
+
+		/* Save the rest of the general registers (R15 has been saved already). */
+		"PUSHM		R1-R14						\n" \
+
+		/* Save the FPSW and accumulator. */
+		"MVFC		FPSW, R15					\n" \
+		"PUSH.L		R15							\n" \
+		"MVFACGU	#0, A1, R15					\n" \
+		"PUSH.L		R15							\n" \
+		"MVFACHI	#0, A1, R15					\n" \
+		"PUSH.L		R15							\n" \
+		/* Low order word. */
+		"MVFACLO	#0, A1, R15					\n" \
+		"PUSH.L		R15							\n" \
+		"MVFACGU	#0, A0, R15					\n" \
+		"PUSH.L		R15							\n" \
+		"MVFACHI	#0, A0, R15					\n" \
+		"PUSH.L		R15							\n" \
+		/* Low order word. */
+		"MVFACLO	#0, A0, R15					\n" \
+		"PUSH.L		R15							\n" \
+
+		/* Save the stack pointer to the TCB. */
+		"MOV.L		#_pxCurrentTCB, R15			\n" \
+		"MOV.L		[ R15 ], R15				\n" \
+		"MOV.L		R0, [ R15 ]					\n" \
+
+		/* Ensure the interrupt mask is set to the syscall priority while the kernel
+		structures are being accessed. */
+		"MVTIPL		%0 							\n" \
+
+		/* Select the next task to run. */
+		"BSR.A		_vTaskSwitchContext			\n" \
+
+		/* Reset the interrupt mask as no more data structure access is required. */
+		"MVTIPL		%1							\n" \
+
+		/* Load the stack pointer of the task that is now selected as the Running
+		state task from its TCB. */
+		"MOV.L		#_pxCurrentTCB,R15			\n" \
+		"MOV.L		[ R15 ], R15				\n" \
+		"MOV.L		[ R15 ], R0					\n" \
+
+		/* Restore the context of the new task.  The PSW (Program Status Word) and
+		PC will be popped by the RTE instruction. */
+	    "POP		R15							\n" \
+
+	    /* Accumulator low 32 bits. */
+	    "MVTACLO	R15, A0						\n" \
+	    "POP		R15							\n" \
+
+	    /* Accumulator high 32 bits. */
+	    "MVTACHI	R15, A0						\n" \
+	    "POP		R15							\n" \
+
+	    /* Accumulator guard. */
+	    "MVTACGU	R15, A0						\n" \
+	    "POP		R15							\n" \
+
+	    /* Accumulator low 32 bits. */
+	    "MVTACLO	R15, A1						\n" \
+	    "POP		R15							\n" \
+
+	    /* Accumulator high 32 bits. */
+	    "MVTACHI	R15, A1						\n" \
+	    "POP		R15							\n" \
+
+	    /* Accumulator guard. */
+	    "MVTACGU	R15, A1						\n" \
+		"POP		R15							\n" \
+		"MVTC		R15, FPSW					\n" \
+		"POPM		R1-R15						\n" \
+		"RTE									\n" \
+		"NOP									\n" \
+		"NOP									  "
+		:: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vTickISR( void )
+{
+	/* Re-enabled interrupts. */
+	__asm volatile( "SETPSW	I" );
+
+	/* Increment the tick, and perform any processing the new tick value
+	necessitates.  Ensure IPL is at the max syscall value first. */
+	portMASK_INTERRUPTS_FROM_KERNEL_ISR();
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			taskYIELD();
+		}
+	}
+	portUNMASK_INTERRUPTS_FROM_KERNEL_ISR();
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortGetIPL( void )
+{
+	__asm volatile
+	(
+		"MVFC	PSW, R1			\n"	\
+		"SHLR	#24, R1			\n"	\
+		"RTS					  "
+	);
+
+	/* This will never get executed, but keeps the compiler from complaining. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetIPL( uint32_t ulNewIPL )
+{
+	__asm volatile
+	(
+		"PUSH	R5				\n" \
+		"MVFC	PSW, R5			\n"	\
+		"SHLL	#24, R1			\n" \
+		"AND	#-0F000001H, R5 \n" \
+		"OR		R1, R5			\n" \
+		"MVTC	R5, PSW			\n" \
+		"POP	R5				\n" \
+		"RTS					  "
+	 );
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RX600v2/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RX600v2/portmacro.h
new file mode 100644
index 0000000..0bafa1e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/RX600v2/portmacro.h
@@ -0,0 +1,138 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			8	/* Could make four, according to manual. */
+#define portSTACK_GROWTH			-1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					__asm volatile( "NOP" )
+
+/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
+where portITU_SWINTR is the location of the software interrupt register
+(0x000872E0).  Don't rely on the assembler to select a register, so instead
+save and restore clobbered registers manually. */
+#define portYIELD()							\
+	__asm volatile 							\
+	(										\
+		"PUSH.L	R10					\n"		\
+		"MOV.L	#0x872E0, R10		\n"		\
+		"MOV.B	#0x1, [R10]			\n"		\
+		"MOV.L	[R10], R10			\n"		\
+		"POP	R10					\n"		\
+	)
+
+#define portYIELD_FROM_ISR( x )	if( x != pdFALSE ) portYIELD()
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() 	__asm volatile ( "MVTIPL	#0" )
+#ifdef configASSERT
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+	#define portDISABLE_INTERRUPTS() 	if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#else
+	#define portDISABLE_INTERRUPTS() 	__asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+uint32_t ulPortGetIPL( void ) __attribute__((naked));
+void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/STR75x/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/STR75x/port.c
new file mode 100644
index 0000000..175f359
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/STR75x/port.c
@@ -0,0 +1,197 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ST STR75x ARM7
+ * port.
+ *----------------------------------------------------------*/
+
+/* Library includes. */
+#include "75x_tb.h"
+#include "75x_eic.h"
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup the initial stack. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
+
+/* Prescale used on the timer clock when calculating the tick period. */
+#define portPRESCALE 20
+
+
+/*-----------------------------------------------------------*/
+
+/* Setup the TB to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* To ensure asserts in tasks.c don't fail, although in this case the assert
+	is not really required. */
+	pxTopOfStack--;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The status register is set for system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	#ifdef THUMB_INTERWORK
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+	#endif
+
+	pxTopOfStack--;
+
+	/* Interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+
+	return pxTopOfStack;	
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortISRStartFirstTask( void );
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortISRStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+EIC_IRQInitTypeDef  EIC_IRQInitStructure;	
+TB_InitTypeDef      TB_InitStructure;
+
+	/* Setup the EIC for the TB. */
+	EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE;
+	EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel;
+	EIC_IRQInitStructure.EIC_IRQChannelPriority = 1;
+	EIC_IRQInit(&EIC_IRQInitStructure);
+	
+	/* Setup the TB for the generation of the tick interrupt. */
+	TB_InitStructure.TB_Mode = TB_Mode_Timing;
+	TB_InitStructure.TB_CounterMode = TB_CounterMode_Down;
+	TB_InitStructure.TB_Prescaler = portPRESCALE - 1;
+	TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ );
+	TB_Init(&TB_InitStructure);
+	
+	/* Enable TB Update interrupt */
+	TB_ITConfig(TB_IT_Update, ENABLE);
+
+	/* Clear TB Update interrupt pending bit */
+	TB_ClearITPendingBit(TB_IT_Update);
+
+	/* Enable TB */
+	TB_Cmd(ENABLE);
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/STR75x/portISR.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/STR75x/portISR.c
new file mode 100644
index 0000000..7488307
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/STR75x/portISR.c
@@ -0,0 +1,182 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*-----------------------------------------------------------
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c  The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
+
+/*
+*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING		( ( uint32_t ) 0 )
+
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * The scheduler can only be started from ARM mode, hence the inclusion of this
+ * function here.
+ */
+void vPortISRStartFirstTask( void );
+/*-----------------------------------------------------------*/
+
+void vPortISRStartFirstTask( void )
+{
+	/* Simply start the scheduler.  This is included here as it can only be
+	called from ARM mode. */
+	asm volatile (														\
+	"LDR		R0, =pxCurrentTCB								\n\t"	\
+	"LDR		R0, [R0]										\n\t"	\
+	"LDR		LR, [R0]										\n\t"	\
+																		\
+	/* The critical nesting depth is the first item on the stack. */	\
+	/* Load it into the ulCriticalNesting variable. */					\
+	"LDR		R0, =ulCriticalNesting							\n\t"	\
+	"LDMFD	LR!, {R1}											\n\t"	\
+	"STR		R1, [R0]										\n\t"	\
+																		\
+	/* Get the SPSR from the stack. */									\
+	"LDMFD	LR!, {R0}											\n\t"	\
+	"MSR		SPSR, R0										\n\t"	\
+																		\
+	/* Restore all system mode registers for the task. */				\
+	"LDMFD	LR, {R0-R14}^										\n\t"	\
+	"NOP														\n\t"	\
+																		\
+	/* Restore the return address. */									\
+	"LDR		LR, [LR, #+60]									\n\t"	\
+																		\
+	/* And return - correcting the offset in the LR to obtain the */	\
+	/* correct address. */												\
+	"SUBS PC, LR, #4											\n\t"	\
+	);																	
+}
+/*-----------------------------------------------------------*/
+
+void vPortTickISR( void )
+{
+	/* Increment the RTOS tick count, then look for the highest priority 
+	task that is ready to run. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{	
+		vTaskSwitchContext();
+	}
+			
+	/* Ready for the next interrupt. */
+	TB_ClearITPendingBit( TB_IT_Update );	
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to
+ * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then
+ * the utilities are defined as macros in portmacro.h - as per other ports.
+ */
+#ifdef THUMB_INTERWORK
+
+	void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	void vPortDisableInterruptsFromThumb( void )
+	{
+		asm volatile ( 
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.						*/
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+			
+	void vPortEnableInterruptsFromThumb( void )
+	{
+		asm volatile ( 
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/	
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/	
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.							*/	
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/	
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+
+#endif /* THUMB_INTERWORK */
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 							*/
+	asm volatile ( 
+		"STMDB	SP!, {R0}			\n\t"	/* Push R0.								*/
+		"MRS	R0, CPSR			\n\t"	/* Get CPSR.							*/
+		"ORR	R0, R0, #0xC0		\n\t"	/* Disable IRQ, FIQ.					*/
+		"MSR	CPSR, R0			\n\t"	/* Write back modified value.			*/
+		"LDMIA	SP!, {R0}" );				/* Pop R0.								*/
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed 
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Enable interrupts as per portEXIT_CRITICAL().					*/
+			asm volatile ( 
+				"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	
+				"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	
+				"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	
+				"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	
+				"LDMIA	SP!, {R0}" );			/* Pop R0.						*/
+		}
+	}
+}
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/STR75x/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/STR75x/portmacro.h
new file mode 100644
index 0000000..219aac9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/STR75x/portmacro.h
@@ -0,0 +1,141 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+#define portYIELD()					asm volatile ( "SWI 0" )
+#define portNOP()					asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions in
+ * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not
+ * defined then the utilities are defined as macros here - as per other ports.
+ */
+
+#ifdef THUMB_INTERWORK
+
+	extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	#define portDISABLE_INTERRUPTS()	vPortDisableInterruptsFromThumb()
+	#define portENABLE_INTERRUPTS()		vPortEnableInterruptsFromThumb()
+
+#else
+
+	#define portDISABLE_INTERRUPTS()											\
+		asm volatile (															\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.			*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+	#define portENABLE_INTERRUPTS()												\
+		asm volatile (															\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+#endif /* THUMB_INTERWORK */
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+#define portEND_SWITCHING_ISR( xSwitchRequired ) 	\
+{													\
+extern void vTaskSwitchContext( void );				\
+													\
+	if( xSwitchRequired ) 							\
+	{												\
+		vTaskSwitchContext();						\
+	}												\
+}
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/TriCore_1782/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/TriCore_1782/port.c
new file mode 100644
index 0000000..686129a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/TriCore_1782/port.c
@@ -0,0 +1,541 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* TriCore specific includes. */
+#include 
+#include 
+#include 
+#include 
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "list.h"
+
+#if configCHECK_FOR_STACK_OVERFLOW > 0
+	#error "Stack checking cannot be used with this port, as, unlike most ports, the pxTopOfStack member of the TCB is consumed CSA.  CSA starvation, loosely equivalent to stack overflow, will result in a trap exception."
+	/* The stack pointer is accessible using portCSA_TO_ADDRESS( portCSA_TO_ADDRESS( pxCurrentTCB->pxTopOfStack )[ 0 ] )[ 2 ]; */
+#endif /* configCHECK_FOR_STACK_OVERFLOW */
+
+
+/*-----------------------------------------------------------*/
+
+/* System register Definitions. */
+#define portSYSTEM_PROGRAM_STATUS_WORD					( 0x000008FFUL ) /* Supervisor Mode, MPU Register Set 0 and Call Depth Counting disabled. */
+#define portINITIAL_PRIVILEGED_PROGRAM_STATUS_WORD		( 0x000014FFUL ) /* IO Level 1, MPU Register Set 1 and Call Depth Counting disabled. */
+#define portINITIAL_UNPRIVILEGED_PROGRAM_STATUS_WORD	( 0x000010FFUL ) /* IO Level 0, MPU Register Set 1 and Call Depth Counting disabled. */
+#define portINITIAL_PCXI_UPPER_CONTEXT_WORD				( 0x00C00000UL ) /* The lower 20 bits identify the CSA address. */
+#define portINITIAL_SYSCON								( 0x00000000UL ) /* MPU Disable. */
+
+/* CSA manipulation macros. */
+#define portCSA_FCX_MASK					( 0x000FFFFFUL )
+
+/* OS Interrupt and Trap mechanisms. */
+#define portRESTORE_PSW_MASK				( ~( 0x000000FFUL ) )
+#define portSYSCALL_TRAP					( 6 )
+
+/* Each CSA contains 16 words of data. */
+#define portNUM_WORDS_IN_CSA				( 16 )
+
+/* The interrupt enable bit in the PCP_SRC register. */
+#define portENABLE_CPU_INTERRUPT 			( 1U << 12U )
+/*-----------------------------------------------------------*/
+
+/*
+ * Perform any hardware configuration necessary to generate the tick interrupt.
+ */
+static void prvSystemTickHandler( int ) __attribute__((longcall));
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * Trap handler for yields.
+ */
+static void prvTrapYield( int iTrapIdentification );
+
+/*
+ * Priority 1 interrupt handler for yields pended from an interrupt.
+ */
+static void prvInterruptYield( int iTrapIdentification );
+
+/*-----------------------------------------------------------*/
+
+/* This reference is required by the save/restore context macros. */
+extern volatile uint32_t *pxCurrentTCB;
+
+/* Precalculate the compare match value at compile time. */
+static const uint32_t ulCompareMatchValue = ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ );
+
+/*-----------------------------------------------------------*/
+
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint32_t *pulUpperCSA = NULL;
+uint32_t *pulLowerCSA = NULL;
+
+	/* 16 Address Registers (4 Address registers are global), 16 Data
+	Registers, and 3 System Registers.
+
+	There are 3 registers that track the CSAs.
+		FCX points to the head of globally free set of CSAs.
+		PCX for the task needs to point to Lower->Upper->NULL arrangement.
+		LCX points to the last free CSA so that corrective action can be taken.
+
+	Need two CSAs to store the context of a task.
+		The upper context contains D8-D15, A10-A15, PSW and PCXI->NULL.
+		The lower context contains D0-D7, A2-A7, A11 and PCXI->UpperContext.
+		The pxCurrentTCB->pxTopOfStack points to the Lower Context RSLCX matching the initial BISR.
+		The Lower Context points to the Upper Context ready for the return from the interrupt handler.
+
+	 The Real stack pointer for the task is stored in the A10 which is restored
+	 with the upper context. */
+
+	/* Have to disable interrupts here because the CSAs are going to be
+	manipulated. */
+	portENTER_CRITICAL();
+	{
+		/* DSync to ensure that buffering is not a problem. */
+		_dsync();
+
+		/* Consume two free CSAs. */
+		pulLowerCSA = portCSA_TO_ADDRESS( __MFCR( $FCX ) );
+		if( NULL != pulLowerCSA )
+		{
+			/* The Lower Links to the Upper. */
+			pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[ 0 ] );
+		}
+
+		/* Check that we have successfully reserved two CSAs. */
+		if( ( NULL != pulLowerCSA ) && ( NULL != pulUpperCSA ) )
+		{
+			/* Remove the two consumed CSAs from the free CSA list. */
+			_disable();
+			_dsync();
+			_mtcr( $FCX, pulUpperCSA[ 0 ] );
+			_isync();
+			_enable();
+		}
+		else
+		{
+			/* Simply trigger a context list depletion trap. */
+			_svlcx();
+		}
+	}
+	portEXIT_CRITICAL();
+
+	/* Clear the upper CSA. */
+	memset( pulUpperCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
+
+	/* Upper Context. */
+	pulUpperCSA[ 2 ] = ( uint32_t )pxTopOfStack;		/* A10;	Stack Return aka Stack Pointer */
+	pulUpperCSA[ 1 ] = portSYSTEM_PROGRAM_STATUS_WORD;		/* PSW	*/
+
+	/* Clear the lower CSA. */
+	memset( pulLowerCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
+
+	/* Lower Context. */
+	pulLowerCSA[ 8 ] = ( uint32_t ) pvParameters;		/* A4;	Address Type Parameter Register	*/
+	pulLowerCSA[ 1 ] = ( uint32_t ) pxCode;			/* A11;	Return Address aka RA */
+
+	/* PCXI pointing to the Upper context. */
+	pulLowerCSA[ 0 ] = ( portINITIAL_PCXI_UPPER_CONTEXT_WORD | ( uint32_t ) portADDRESS_TO_CSA( pulUpperCSA ) );
+
+	/* Save the link to the CSA in the top of stack. */
+	pxTopOfStack = (uint32_t * ) portADDRESS_TO_CSA( pulLowerCSA );
+
+	/* DSync to ensure that buffering is not a problem. */
+	_dsync();
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+int32_t xPortStartScheduler( void )
+{
+extern void vTrapInstallHandlers( void );
+uint32_t ulMFCR = 0UL;
+uint32_t *pulUpperCSA = NULL;
+uint32_t *pulLowerCSA = NULL;
+
+	/* Interrupts at or below configMAX_SYSCALL_INTERRUPT_PRIORITY are disable
+	when this function is called. */
+
+	/* Set-up the timer interrupt. */
+	prvSetupTimerInterrupt();
+
+	/* Install the Trap Handlers. */
+	vTrapInstallHandlers();
+
+	/* Install the Syscall Handler for yield calls. */
+	if( 0 == _install_trap_handler( portSYSCALL_TRAP, prvTrapYield ) )
+	{
+		/* Failed to install the yield handler, force an assert. */
+		configASSERT( ( ( volatile void * ) NULL ) );
+	}
+
+	/* Enable then install the priority 1 interrupt for pending context
+	switches from an ISR.  See mod_SRC in the TriCore manual. */
+	CPU_SRC0.reg = 	( portENABLE_CPU_INTERRUPT ) | ( configKERNEL_YIELD_PRIORITY );
+	if( 0 == _install_int_handler( configKERNEL_YIELD_PRIORITY, prvInterruptYield, 0 ) )
+	{
+		/* Failed to install the yield handler, force an assert. */
+		configASSERT( ( ( volatile void * ) NULL ) );
+	}
+
+	_disable();
+
+	/* Load the initial SYSCON. */
+	_mtcr( $SYSCON, portINITIAL_SYSCON );
+	_isync();
+
+	/* ENDINIT has already been applied in the 'cstart.c' code. */
+
+	/* Clear the PSW.CDC to enable the use of an RFE without it generating an
+	exception because this code is not genuinely in an exception. */
+	ulMFCR = __MFCR( $PSW );
+	ulMFCR &= portRESTORE_PSW_MASK;
+	_dsync();
+	_mtcr( $PSW, ulMFCR );
+	_isync();
+
+	/* Finally, perform the equivalent of a portRESTORE_CONTEXT() */
+	pulLowerCSA = portCSA_TO_ADDRESS( ( *pxCurrentTCB ) );
+	pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[0] );
+	_dsync();
+	_mtcr( $PCXI, *pxCurrentTCB );
+	_isync();
+	_nop();
+	_rslcx();
+	_nop();
+
+	/* Return to the first task selected to execute. */
+	__asm volatile( "rfe" );
+
+	/* Will not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+	/* Set-up the clock divider. */
+	unlock_wdtcon();
+	{
+		/* Wait until access to Endint protected register is enabled. */
+		while( 0 != ( WDT_CON0.reg & 0x1UL ) );
+
+		/* RMC == 1 so STM Clock == FPI */
+		STM_CLC.reg = ( 1UL << 8 );
+	}
+	lock_wdtcon();
+
+    /* Determine how many bits are used without changing other bits in the CMCON register. */
+	STM_CMCON.reg &= ~( 0x1fUL );
+	STM_CMCON.reg |= ( 0x1fUL - __CLZ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) );
+
+	/* Take into account the current time so a tick doesn't happen immediately. */
+	STM_CMP0.reg = ulCompareMatchValue + STM_TIM0.reg;
+
+	if( 0 != _install_int_handler( configKERNEL_INTERRUPT_PRIORITY, prvSystemTickHandler, 0 ) )
+	{
+		/* Set-up the interrupt. */
+		STM_SRC0.reg = ( configKERNEL_INTERRUPT_PRIORITY | 0x00005000UL );
+
+		/* Enable the Interrupt. */
+		STM_ISRR.reg &= ~( 0x03UL );
+		STM_ISRR.reg |= 0x1UL;
+		STM_ISRR.reg &= ~( 0x07UL );
+		STM_ICR.reg |= 0x1UL;
+	}
+	else
+	{
+		/* Failed to install the Tick Interrupt. */
+		configASSERT( ( ( volatile void * ) NULL ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSystemTickHandler( int iArg )
+{
+uint32_t ulSavedInterruptMask;
+uint32_t *pxUpperCSA = NULL;
+uint32_t xUpperCSA = 0UL;
+extern volatile uint32_t *pxCurrentTCB;
+int32_t lYieldRequired;
+
+	/* Just to avoid compiler warnings about unused parameters. */
+	( void ) iArg;
+
+	/* Clear the interrupt source. */
+	STM_ISRR.reg = 1UL;
+
+	/* Reload the Compare Match register for X ticks into the future.
+
+	If critical section or interrupt nesting budgets are exceeded, then
+	it is possible that the calculated next compare match value is in the
+	past.  If this occurs (unlikely), it is possible that the resulting
+	time slippage will exceed a single tick period.  Any adverse effect of
+	this is time bounded by the fact that only the first n bits of the 56 bit
+	STM timer are being used for a compare match, so another compare match
+	will occur after an overflow in just those n bits (not the entire 56 bits).
+	As an example, if the peripheral clock is 75MHz, and the tick rate is 1KHz,
+	a missed tick could result in the next tick interrupt occurring within a
+	time that is 1.7 times the desired period.  The fact that this is greater
+	than a single tick period is an effect of using a timer that cannot be
+	automatically reset, in hardware, by the occurrence of a tick interrupt.
+	Changing the tick source to a timer that has an automatic reset on compare
+	match (such as a GPTA timer) will reduce the maximum possible additional
+	period to exactly 1 times the desired period. */
+	STM_CMP0.reg += ulCompareMatchValue;
+
+	/* Kernel API calls require Critical Sections. */
+	ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the Tick. */
+		lYieldRequired = xTaskIncrementTick();
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
+
+	if( lYieldRequired != pdFALSE )
+	{
+		/* Save the context of a task.
+		The upper context is automatically saved when entering a trap or interrupt.
+		Need to save the lower context as well and copy the PCXI CSA ID into
+		pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
+		TCB of a task.
+
+		Call vTaskSwitchContext to select the next task, note that this changes the
+		value of pxCurrentTCB so that it needs to be reloaded.
+
+		Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
+		that has just been switched in.
+
+		Load the context of the task.
+		Need to restore the lower context by loading the CSA from
+		pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
+		In the Interrupt handler post-amble, RSLCX will restore the lower context
+		of the task. RFE will restore the upper context of the task, jump to the
+		return address and restore the previous state of interrupts being
+		enabled/disabled. */
+		_disable();
+		_dsync();
+		xUpperCSA = __MFCR( $PCXI );
+		pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
+		*pxCurrentTCB = pxUpperCSA[ 0 ];
+		vTaskSwitchContext();
+		pxUpperCSA[ 0 ] = *pxCurrentTCB;
+		CPU_SRC0.bits.SETR = 0;
+		_isync();
+	}
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * When a task is deleted, it is yielded permanently until the IDLE task
+ * has an opportunity to reclaim the memory that that task was using.
+ * Typically, the memory used by a task is the TCB and Stack but in the
+ * TriCore this includes the CSAs that were consumed as part of the Call
+ * Stack. These CSAs can only be returned to the Globally Free Pool when
+ * they are not part of the current Call Stack, hence, delaying the
+ * reclamation until the IDLE task is freeing the task's other resources.
+ * This function uses the head of the linked list of CSAs (from when the
+ * task yielded for the last time) and finds the tail (the very bottom of
+ * the call stack) and inserts this list at the head of the Free list,
+ * attaching the existing Free List to the tail of the reclaimed call stack.
+ *
+ * NOTE: the IDLE task needs processing time to complete this function
+ * and in heavily loaded systems, the Free CSAs may be consumed faster
+ * than they can be freed assuming that tasks are being spawned and
+ * deleted frequently.
+ */
+void vPortReclaimCSA( uint32_t *pxTCB )
+{
+uint32_t pxHeadCSA, pxTailCSA, pxFreeCSA;
+uint32_t *pulNextCSA;
+
+	/* A pointer to the first CSA in the list of CSAs consumed by the task is
+	stored in the first element of the tasks TCB structure (where the stack
+	pointer would be on a traditional stack based architecture). */
+	pxHeadCSA = ( *pxTCB ) & portCSA_FCX_MASK;
+
+	/* Mask off everything in the CSA link field other than the address.  If
+	the	address is NULL, then the CSA is not linking anywhere and there is
+	nothing	to do. */
+	pxTailCSA = pxHeadCSA;
+
+	/* Convert the link value to contain just a raw address and store this
+	in a local variable. */
+	pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
+
+	/* Iterate over the CSAs that were consumed as part of the task.  The
+	first field in the CSA is the pointer to then next CSA.  Mask off
+	everything in the pointer to the next CSA, other than the link address.
+	If this is NULL, then the CSA currently being pointed to is the last in
+	the chain. */
+	while( 0UL != ( pulNextCSA[ 0 ] & portCSA_FCX_MASK ) )
+	{
+		/* Clear all bits of the pointer to the next in the chain, other
+		than the address bits themselves. */
+		pulNextCSA[ 0 ] = pulNextCSA[ 0 ] & portCSA_FCX_MASK;
+
+		/* Move the pointer to point to the next CSA in the list. */
+		pxTailCSA = pulNextCSA[ 0 ];
+
+		/* Update the local pointer to the CSA. */
+		pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
+	}
+
+	_disable();
+	{
+		/* Look up the current free CSA head. */
+		_dsync();
+		pxFreeCSA = __MFCR( $FCX );
+
+		/* Join the current Free onto the Tail of what is being reclaimed. */
+		portCSA_TO_ADDRESS( pxTailCSA )[ 0 ] = pxFreeCSA;
+
+		/* Move the head of the reclaimed into the Free. */
+		_dsync();
+		_mtcr( $FCX, pxHeadCSA );
+		_isync();
+	}
+	_enable();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Nothing to do. Unlikely to want to end. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvTrapYield( int iTrapIdentification )
+{
+uint32_t *pxUpperCSA = NULL;
+uint32_t xUpperCSA = 0UL;
+extern volatile uint32_t *pxCurrentTCB;
+
+	switch( iTrapIdentification )
+	{
+		case portSYSCALL_TASK_YIELD:
+			/* Save the context of a task.
+			The upper context is automatically saved when entering a trap or interrupt.
+			Need to save the lower context as well and copy the PCXI CSA ID into
+			pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
+			TCB of a task.
+
+			Call vTaskSwitchContext to select the next task, note that this changes the
+			value of pxCurrentTCB so that it needs to be reloaded.
+
+			Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
+			that has just been switched in.
+
+			Load the context of the task.
+			Need to restore the lower context by loading the CSA from
+			pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
+			In the Interrupt handler post-amble, RSLCX will restore the lower context
+			of the task. RFE will restore the upper context of the task, jump to the
+			return address and restore the previous state of interrupts being
+			enabled/disabled. */
+			_disable();
+			_dsync();
+			xUpperCSA = __MFCR( $PCXI );
+			pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
+			*pxCurrentTCB = pxUpperCSA[ 0 ];
+			vTaskSwitchContext();
+			pxUpperCSA[ 0 ] = *pxCurrentTCB;
+			CPU_SRC0.bits.SETR = 0;
+			_isync();
+			break;
+
+		default:
+			/* Unimplemented trap called. */
+			configASSERT( ( ( volatile void * ) NULL ) );
+			break;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvInterruptYield( int iId )
+{
+uint32_t *pxUpperCSA = NULL;
+uint32_t xUpperCSA = 0UL;
+extern volatile uint32_t *pxCurrentTCB;
+
+	/* Just to remove compiler warnings. */
+	( void ) iId;
+
+	/* Save the context of a task.
+	The upper context is automatically saved when entering a trap or interrupt.
+	Need to save the lower context as well and copy the PCXI CSA ID into
+	pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
+	TCB of a task.
+
+	Call vTaskSwitchContext to select the next task, note that this changes the
+	value of pxCurrentTCB so that it needs to be reloaded.
+
+	Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
+	that has just been switched in.
+
+	Load the context of the task.
+	Need to restore the lower context by loading the CSA from
+	pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
+	In the Interrupt handler post-amble, RSLCX will restore the lower context
+	of the task. RFE will restore the upper context of the task, jump to the
+	return address and restore the previous state of interrupts being
+	enabled/disabled. */
+	_disable();
+	_dsync();
+	xUpperCSA = __MFCR( $PCXI );
+	pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
+	*pxCurrentTCB = pxUpperCSA[ 0 ];
+	vTaskSwitchContext();
+	pxUpperCSA[ 0 ] = *pxCurrentTCB;
+	CPU_SRC0.bits.SETR = 0;
+	_isync();
+}
+/*-----------------------------------------------------------*/
+
+uint32_t uxPortSetInterruptMaskFromISR( void )
+{
+uint32_t uxReturn = 0UL;
+
+	_disable();
+	uxReturn = __MFCR( $ICR );
+	_mtcr( $ICR, ( ( uxReturn & ~portCCPN_MASK ) | configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
+	_isync();
+	_enable();
+
+	/* Return just the interrupt mask bits. */
+	return ( uxReturn & portCCPN_MASK );
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/TriCore_1782/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/TriCore_1782/portmacro.h
new file mode 100644
index 0000000..f47e84e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/TriCore_1782/portmacro.h
@@ -0,0 +1,173 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* System Includes. */
+#include 
+#include 
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*---------------------------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH							( -1 )
+#define portTICK_PERIOD_MS							( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT							4
+#define portNOP()									__asm volatile( " nop " )
+#define portCRITICAL_NESTING_IN_TCB					1
+#define portRESTORE_FIRST_TASK_PRIORITY_LEVEL		1
+
+
+/*---------------------------------------------------------------------------*/
+
+typedef struct MPU_SETTINGS { uint32_t ulNotUsed; } xMPU_SETTINGS;
+
+/* Define away the instruction from the Restore Context Macro. */
+#define portPRIVILEGE_BIT							0x0UL
+
+#define portCCPN_MASK						( 0x000000FFUL )
+
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()			vTaskEnterCritical()
+#define portEXIT_CRITICAL()				vTaskExitCritical()
+/*---------------------------------------------------------------------------*/
+
+/* CSA Manipulation. */
+#define portCSA_TO_ADDRESS( pCSA )			( ( uint32_t * )( ( ( ( pCSA ) & 0x000F0000 ) << 12 ) | ( ( ( pCSA ) & 0x0000FFFF ) << 6 ) ) )
+#define portADDRESS_TO_CSA( pAddress )		( ( uint32_t )( ( ( ( (uint32_t)( pAddress ) ) & 0xF0000000 ) >> 12 ) | ( ( ( uint32_t )( pAddress ) & 0x003FFFC0 ) >> 6 ) ) )
+/*---------------------------------------------------------------------------*/
+
+#define portYIELD()								_syscall( 0 )
+/* Port Restore is implicit in the platform when the function is returned from the original PSW is automatically replaced. */
+#define portSYSCALL_TASK_YIELD					0
+#define portSYSCALL_RAISE_PRIORITY				1
+/*---------------------------------------------------------------------------*/
+
+/* Critical section management. */
+
+/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+#define portDISABLE_INTERRUPTS()	{																									\
+										uint32_t ulICR;																			\
+										_disable();																						\
+										ulICR = __MFCR( $ICR ); 		/* Get current ICR value. */										\
+										ulICR &= ~portCCPN_MASK;	/* Clear down mask bits. */											\
+										ulICR |= configMAX_SYSCALL_INTERRUPT_PRIORITY; /* Set mask bits to required priority mask. */	\
+										_mtcr( $ICR, ulICR );		/* Write back updated ICR. */										\
+										_isync();																						\
+										_enable();																						\
+									}
+
+/* Clear ICR.CCPN to allow all interrupt priorities. */
+#define portENABLE_INTERRUPTS()		{																	\
+										uint32_t ulICR;											\
+										_disable();														\
+										ulICR = __MFCR( $ICR );		/* Get current ICR value. */		\
+										ulICR &= ~portCCPN_MASK;	/* Clear down mask bits. */			\
+										_mtcr( $ICR, ulICR );		/* Write back updated ICR. */		\
+										_isync();														\
+										_enable();														\
+									}
+
+/* Set ICR.CCPN to uxSavedMaskValue. */
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedMaskValue ) 	{																						\
+																	uint32_t ulICR;																\
+																	_disable();																			\
+																	ulICR = __MFCR( $ICR );		/* Get current ICR value. */							\
+																	ulICR &= ~portCCPN_MASK;	/* Clear down mask bits. */								\
+																	ulICR |= uxSavedMaskValue;	/* Set mask bits to previously saved mask value. */		\
+																	_mtcr( $ICR, ulICR );		/* Write back updated ICR. */							\
+																	_isync();																			\
+																	_enable();																			\
+																}
+
+
+/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY */
+extern uint32_t uxPortSetInterruptMaskFromISR( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR() 	uxPortSetInterruptMaskFromISR()
+
+/* Pend a priority 1 interrupt, which will take care of the context switch. */
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) 		if( xHigherPriorityTaskWoken != pdFALSE ) {	CPU_SRC0.bits.SETR = 1; _isync(); }
+
+/*---------------------------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*---------------------------------------------------------------------------*/
+
+/*
+ * Port specific clean up macro required to free the CSAs that were consumed by
+ * a task that has since been deleted.
+ */
+void vPortReclaimCSA( uint32_t *pxTCB );
+#define portCLEAN_UP_TCB( pxTCB )		vPortReclaimCSA( ( uint32_t * ) ( pxTCB ) )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/TriCore_1782/porttrap.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/TriCore_1782/porttrap.c
new file mode 100644
index 0000000..672edc0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/GCC/TriCore_1782/porttrap.c
@@ -0,0 +1,281 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+
+/* Machine includes */
+#include 
+#include 
+#include 
+/*---------------------------------------------------------------------------*/
+
+/*
+ * This reference is required by the Save/Restore Context Macros.
+ */
+extern volatile uint32_t *pxCurrentTCB;
+/*-----------------------------------------------------------*/
+
+/*
+ * This file contains base definitions for all of the possible traps in the system.
+ * It is suggested to provide implementations for all of the traps but for
+ * the time being they simply trigger a DEBUG instruction so that it is easy
+ * to see what caused a particular trap.
+ *
+ * Trap Class 6, the SYSCALL, is used exclusively by the operating system.
+ */
+
+/* The Trap Classes. */
+#define portMMU_TRAP										0
+#define portIPT_TRAP										1
+#define portIE_TRAP											2
+#define portCM_TRAP											3
+#define portSBP_TRAP										4
+#define portASSERT_TRAP										5
+#define portNMI_TRAP										7
+
+/* MMU Trap Identifications. */
+#define portTIN_MMU_VIRTUAL_ADDRESS_FILL					0
+#define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION				1
+
+/* Internal Protection Trap Identifications. */
+#define portTIN_IPT_PRIVILIGED_INSTRUCTION					1
+#define portTIN_IPT_MEMORY_PROTECTION_READ					2
+#define portTIN_IPT_MEMORY_PROTECTION_WRITE					3
+#define portTIN_IPT_MEMORY_PROTECTION_EXECUTION				4
+#define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS		5
+#define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS			6
+#define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION	7
+
+/* Instruction Error Trap Identifications. */
+#define portTIN_IE_ILLEGAL_OPCODE							1
+#define portTIN_IE_UNIMPLEMENTED_OPCODE						2
+#define portTIN_IE_INVALID_OPERAND							3
+#define portTIN_IE_DATA_ADDRESS_ALIGNMENT					4
+#define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS				5
+
+/* Context Management Trap Identifications. */
+#define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION				1
+#define portTIN_CM_CALL_DEPTH_OVERFLOW						2
+#define portTIN_CM_CALL_DEPTH_UNDEFLOW						3
+#define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW				4
+#define portTIN_CM_CALL_STACK_UNDERFLOW						5
+#define portTIN_CM_CONTEXT_TYPE								6
+#define portTIN_CM_NESTING_ERROR							7
+
+/* System Bus and Peripherals Trap Identifications. */
+#define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR			1
+#define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR			2
+#define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR			3
+#define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR		4
+#define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR			5
+#define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR				6
+
+/* Assertion Trap Identifications. */
+#define portTIN_ASSERT_ARITHMETIC_OVERFLOW					1
+#define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW			2
+
+/* Non-maskable Interrupt Trap Identifications. */
+#define portTIN_NMI_NON_MASKABLE_INTERRUPT					0
+/*---------------------------------------------------------------------------*/
+
+void vMMUTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vInternalProtectionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vInstructionErrorTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vContextManagementTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vSystemBusAndPeripheralsTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vAssertionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vNonMaskableInterruptTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+/*---------------------------------------------------------------------------*/
+
+void vTrapInstallHandlers( void )
+{
+	if( 0 == _install_trap_handler ( portMMU_TRAP, vMMUTrap ) )
+	{
+		_debug();
+	}
+
+	if( 0 == _install_trap_handler ( portIPT_TRAP, vInternalProtectionTrap ) )
+	{
+		_debug();
+	}
+
+	if( 0 == _install_trap_handler ( portIE_TRAP, vInstructionErrorTrap ) )
+	{
+		_debug();
+	}
+
+	if( 0 == _install_trap_handler ( portCM_TRAP, vContextManagementTrap ) )
+	{
+		_debug();
+	}
+
+	if( 0 == _install_trap_handler ( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )
+	{
+		_debug();
+	}
+
+	if( 0 == _install_trap_handler ( portASSERT_TRAP, vAssertionTrap ) )
+	{
+		_debug();
+	}
+
+	if( 0 == _install_trap_handler ( portNMI_TRAP, vNonMaskableInterruptTrap ) )
+	{
+		_debug();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vMMUTrap( int iTrapIdentification )
+{
+	switch( iTrapIdentification )
+	{
+	case portTIN_MMU_VIRTUAL_ADDRESS_FILL:
+	case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:
+	default:
+		_debug();
+		break;
+	}
+}
+/*---------------------------------------------------------------------------*/
+
+void vInternalProtectionTrap( int iTrapIdentification )
+{
+	/* Deliberate fall through to default. */
+	switch( iTrapIdentification )
+	{
+		case portTIN_IPT_PRIVILIGED_INSTRUCTION:
+			/* Instruction is not allowed at current execution level, eg DISABLE at User-0. */
+
+		case portTIN_IPT_MEMORY_PROTECTION_READ:
+			/* Load word using invalid address. */
+			
+		case portTIN_IPT_MEMORY_PROTECTION_WRITE:
+			/* Store Word using invalid address. */
+			
+		case portTIN_IPT_MEMORY_PROTECTION_EXECUTION:
+			/* PC jumped to an address outside of the valid range. */
+			
+		case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS:
+			/* Access to a peripheral denied at current execution level. */
+			
+		case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS:
+			/* NULL Pointer. */
+			
+		case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION:
+			/* Tried to modify a global address pointer register. */
+			
+		default:
+		
+			pxCurrentTCB[ 0 ] = __MFCR( $PCXI );
+			_debug();
+			break;
+	}
+}
+/*---------------------------------------------------------------------------*/
+
+void vInstructionErrorTrap( int iTrapIdentification )
+{
+	/* Deliberate fall through to default. */
+	switch( iTrapIdentification )
+	{
+		case portTIN_IE_ILLEGAL_OPCODE:
+		case portTIN_IE_UNIMPLEMENTED_OPCODE:
+		case portTIN_IE_INVALID_OPERAND:
+		case portTIN_IE_DATA_ADDRESS_ALIGNMENT:
+		case portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS:
+		default:
+			_debug();
+			break;
+	}
+}
+/*---------------------------------------------------------------------------*/
+
+void vContextManagementTrap( int iTrapIdentification )
+{
+	/* Deliberate fall through to default. */
+	switch( iTrapIdentification )
+	{
+		case portTIN_CM_FREE_CONTEXT_LIST_DEPLETION:
+		case portTIN_CM_CALL_DEPTH_OVERFLOW:
+		case portTIN_CM_CALL_DEPTH_UNDEFLOW:
+		case portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW:
+		case portTIN_CM_CALL_STACK_UNDERFLOW:
+		case portTIN_CM_CONTEXT_TYPE:
+		case portTIN_CM_NESTING_ERROR:
+		default:
+			_debug();
+			break;
+	}
+}
+/*---------------------------------------------------------------------------*/
+
+void vSystemBusAndPeripheralsTrap( int iTrapIdentification )
+{
+	/* Deliberate fall through to default. */
+	switch( iTrapIdentification )
+	{
+		case portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR:
+		case portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR:
+		case portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR:
+		case portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR:
+		case portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR:
+		case portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR:
+		default:
+			_debug();
+			break;
+	}
+}
+/*---------------------------------------------------------------------------*/
+
+void vAssertionTrap( int iTrapIdentification )
+{
+	/* Deliberate fall through to default. */
+	switch( iTrapIdentification )
+	{
+		case portTIN_ASSERT_ARITHMETIC_OVERFLOW:
+		case portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW:
+		default:
+			_debug();
+			break;
+	}
+}
+/*---------------------------------------------------------------------------*/
+
+void vNonMaskableInterruptTrap( int iTrapIdentification )
+{
+	/* Deliberate fall through to default. */
+	switch( iTrapIdentification )
+	{
+		case portTIN_NMI_NON_MASKABLE_INTERRUPT:
+		default:
+			_debug();
+			break;
+	}
+}
+/*---------------------------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/78K0R/ISR_Support.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/78K0R/ISR_Support.h
new file mode 100644
index 0000000..4d322f3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/78K0R/ISR_Support.h
@@ -0,0 +1,82 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+#include "FreeRTOSConfig.h"
+
+; Variables used by scheduler
+;------------------------------------------------------------------------------
+	EXTERN    pxCurrentTCB
+	EXTERN    usCriticalNesting
+
+;------------------------------------------------------------------------------
+;   portSAVE_CONTEXT MACRO
+;   Saves the context of the general purpose registers, CS and ES (only in far
+;	memory mode) registers the usCriticalNesting Value and the Stack Pointer
+;   of the active Task onto the task stack
+;------------------------------------------------------------------------------
+portSAVE_CONTEXT MACRO
+
+	PUSH      AX                    ; Save AX Register to stack.
+	PUSH      HL
+	MOV       A, CS                 ; Save CS register.
+	XCH       A, X
+	MOV       A, ES                 ; Save ES register.
+	PUSH      AX
+	PUSH      DE                    ; Save the remaining general purpose registers.
+	PUSH      BC
+	MOVW      AX, usCriticalNesting ; Save the usCriticalNesting value.
+	PUSH      AX
+	MOVW      AX, pxCurrentTCB 	    ; Save the Stack pointer.
+	MOVW      HL, AX
+	MOVW      AX, SP
+	MOVW      [HL], AX
+	ENDM
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   portRESTORE_CONTEXT MACRO
+;   Restores the task Stack Pointer then use this to restore usCriticalNesting,
+;   general purpose registers and the CS and ES (only in far memory mode)
+;   of the selected task from the task stack
+;------------------------------------------------------------------------------
+portRESTORE_CONTEXT MACRO
+	MOVW      AX, pxCurrentTCB	    ; Restore the Stack pointer.
+	MOVW      HL, AX
+	MOVW      AX, [HL]
+	MOVW      SP, AX
+	POP	      AX	                ; Restore usCriticalNesting value.
+	MOVW      usCriticalNesting, AX
+	POP	      BC                    ; Restore the necessary general purpose registers.
+	POP	      DE
+	POP       AX                    ; Restore the ES register.
+	MOV       ES, A
+	XCH       A, X                  ; Restore the CS register.
+	MOV       CS, A
+	POP       HL                    ; Restore general purpose register HL.
+	POP       AX                    ; Restore AX.
+	ENDM
+;------------------------------------------------------------------------------
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/78K0R/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/78K0R/port.c
new file mode 100644
index 0000000..18fc494
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/78K0R/port.c
@@ -0,0 +1,225 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* The critical nesting value is initialised to a non zero value to ensure
+interrupts don't accidentally become enabled before the scheduler is started. */
+#define portINITIAL_CRITICAL_NESTING  (( uint16_t ) 10)
+
+/* Initial PSW value allocated to a newly created task.
+ *   1100011000000000
+ *   ||||||||-------------- Fill byte
+ *   |||||||--------------- Carry Flag cleared
+ *   |||||----------------- In-service priority Flags set to low level
+ *   ||||------------------ Register bank Select 0 Flag cleared
+ *   |||------------------- Auxiliary Carry Flag cleared
+ *   ||-------------------- Register bank Select 1 Flag cleared
+ *   |--------------------- Zero Flag set
+ *   ---------------------- Global Interrupt Flag set (enabled)
+ */
+#define portPSW		  (0xc6UL)
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/* Most ports implement critical sections by placing the interrupt flags on
+the stack before disabling interrupts.  Exiting the critical section is then
+simply a case of popping the flags from the stack.  As 78K0 IAR does not use
+a frame pointer this cannot be done as modifying the stack will clobber all
+the stack variables.  Instead each task maintains a count of the critical
+section nesting depth.  Each time a critical section is entered the count is
+incremented.  Each time a critical section is left the count is decremented -
+with interrupts only being re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as this will cause problems during the startup
+sequence. */
+volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
+/*-----------------------------------------------------------*/
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint32_t *pulLocal;
+
+	#if configMEMORY_MODE == 1
+	{
+		/* Parameters are passed in on the stack, and written using a 32bit value
+		hence a space is left for the second two bytes. */
+		pxTopOfStack--;
+
+		/* Write in the parameter value. */
+		pulLocal =  ( uint32_t * ) pxTopOfStack;
+		*pulLocal = ( uint32_t ) pvParameters;
+		pxTopOfStack--;
+
+		/* These values are just spacers.  The return address of the function
+		would normally be written here. */
+		*pxTopOfStack = ( StackType_t ) 0xcdcd;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0xcdcd;
+		pxTopOfStack--;
+
+		/* The start address / PSW value is also written in as a 32bit value,
+		so leave a space for the second two bytes. */
+		pxTopOfStack--;
+	
+		/* Task function start address combined with the PSW. */
+		pulLocal = ( uint32_t * ) pxTopOfStack;
+		*pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
+		pxTopOfStack--;
+
+		/* An initial value for the AX register. */
+		*pxTopOfStack = ( StackType_t ) 0x1111;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		/* Task function address is written to the stack first.  As it is
+		written as a 32bit value a space is left on the stack for the second
+		two bytes. */
+		pxTopOfStack--;
+
+		/* Task function start address combined with the PSW. */
+		pulLocal = ( uint32_t * ) pxTopOfStack;
+		*pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
+		pxTopOfStack--;
+
+		/* The parameter is passed in AX. */
+		*pxTopOfStack = ( StackType_t ) pvParameters;
+		pxTopOfStack--;
+	}
+	#endif
+
+	/* An initial value for the HL register. */
+	*pxTopOfStack = ( StackType_t ) 0x2222;
+	pxTopOfStack--;
+
+	/* CS and ES registers. */
+	*pxTopOfStack = ( StackType_t ) 0x0F00;
+	pxTopOfStack--;
+
+	/* Finally the remaining general purpose registers DE and BC */
+	*pxTopOfStack = ( StackType_t ) 0xDEDE;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xBCBC;
+	pxTopOfStack--;
+
+	/* Finally the critical section nesting count is set to zero when the task
+	first starts. */
+	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;	
+
+	/* Return a pointer to the top of the stack we have generated so this can
+	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Setup the hardware to generate the tick.  Interrupts are disabled when
+	this function is called. */
+	prvSetupTimerInterrupt();
+
+	/* Restore the context of the first task that is going to run. */
+	vPortStart();
+
+	/* Should not get here as the tasks are now running! */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the 78K0R port will get stopped.  If required simply
+	disable the tick interrupt here. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+	/* Setup channel 5 of the TAU to generate the tick interrupt. */
+
+	/* First the Timer Array Unit has to be enabled. */
+	TAU0EN = 1;
+
+	/* To configure the Timer Array Unit all Channels have to first be stopped. */
+	TT0 = 0xff;
+
+	/* Interrupt of Timer Array Unit Channel 5 is disabled to set the interrupt
+	priority. */
+	TMMK05 = 1;
+
+	/* Clear Timer Array Unit Channel 5 interrupt flag. */	
+	TMIF05 = 0;
+
+	/* Set Timer Array Unit Channel 5 interrupt priority */
+	TMPR005 = 0;
+	TMPR105 = 0;
+
+	/* Set Timer Array Unit Channel 5 Mode as interval timer. */
+	TMR05 = 0x0000;
+
+	/* Set the compare match value according to the tick rate we want. */
+	TDR05 = ( TickType_t ) ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
+
+	/* Set Timer Array Unit Channel 5 output mode */
+	TOM0 &= ~0x0020;
+
+	/* Set Timer Array Unit Channel 5 output level */	
+	TOL0 &= ~0x0020;
+
+	/* Set Timer Array Unit Channel 5 output enable */	
+	TOE0 &= ~0x0020;
+
+	/* Interrupt of Timer Array Unit Channel 5 enabled */
+	TMMK05 = 0;
+
+	/* Start Timer Array Unit Channel 5.*/
+	TS0 |= 0x0020;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/78K0R/portasm.s26 b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/78K0R/portasm.s26
new file mode 100644
index 0000000..aa49f1a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/78K0R/portasm.s26
@@ -0,0 +1,138 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+#include "ISR_Support.h"
+;------------------------------------------------------------------------------
+
+#if __CORE__ != __78K0R__
+	#error "This file is only for 78K0R Devices"
+#endif
+
+#define CS                    0xFFFFC
+#define ES                    0xFFFFD
+
+; Functions implemented in this file
+;------------------------------------------------------------------------------
+	PUBLIC    vPortYield
+	PUBLIC    vPortStart
+
+; Functions used by scheduler
+;------------------------------------------------------------------------------
+	EXTERN    vTaskSwitchContext
+	EXTERN    xTaskIncrementTick
+
+; Tick ISR Prototype
+;------------------------------------------------------------------------------
+;	EXTERN    ?CL78K0R_V2_L00
+
+	PUBWEAK   `??MD_INTTM05??INTVEC 68`
+	PUBLIC    MD_INTTM05
+
+MD_INTTM05    SYMBOL "MD_INTTM05"
+`??MD_INTTM05??INTVEC 68` SYMBOL "??INTVEC 68", MD_INTTM05
+
+
+
+;------------------------------------------------------------------------------
+;   Yield to another task.  Implemented as a software interrupt.  The return
+;   address and PSW will have been saved to the stack automatically before
+;   this code runs.
+;
+;   Input:  NONE
+;
+;   Call:   CALL    vPortYield
+;
+;   Output: NONE
+;
+;------------------------------------------------------------------------------
+    RSEG CODE:CODE
+vPortYield:
+	portSAVE_CONTEXT		        ; Save the context of the current task.
+	call      vTaskSwitchContext    ; Call the scheduler to select the next task.
+	portRESTORE_CONTEXT		        ; Restore the context of the next task to run.
+	retb
+
+
+;------------------------------------------------------------------------------
+;   Restore the context of the first task that is going to run.
+;
+;   Input:  NONE
+;
+;   Call:   CALL    vPortStart
+;
+;   Output: NONE
+;
+;------------------------------------------------------------------------------
+    RSEG CODE:CODE
+vPortStart:
+	portRESTORE_CONTEXT	            ; Restore the context of whichever task the ...
+	reti					        ; An interrupt stack frame is used so the task
+                                    ; is started using a RETI instruction.
+
+;------------------------------------------------------------------------------
+;   Perform the necessary steps of the Tick Count Increment and Task Switch
+;   depending on the chosen kernel configuration
+;
+;   Input:  NONE
+;
+;   Call:   ISR
+;
+;   Output: NONE
+;
+;------------------------------------------------------------------------------
+
+MD_INTTM05:
+
+	portSAVE_CONTEXT		        ; Save the context of the current task.
+	call      xTaskIncrementTick    ; Call the timer tick function.
+#if configUSE_PREEMPTION == 1
+	call      vTaskSwitchContext    ; Call the scheduler to select the next task.
+#endif
+	portRESTORE_CONTEXT		        ; Restore the context of the next task to run.
+	reti
+
+
+
+;	REQUIRE ?CL78K0R_V2_L00
+	COMMON INTVEC:CODE:ROOT(1)      ; Set ISR location to the Interrupt vector table.
+	ORG 68
+`??MD_INTTM05??INTVEC 68`:
+	DW MD_INTTM05
+
+	COMMON INTVEC:CODE:ROOT(1)      ; Set ISR location to the Interrupt vector table.
+	ORG 126
+`??vPortYield??INTVEC 126`:
+	DW vPortYield
+
+									; Set value for the usCriticalNesting.
+	RSEG NEAR_ID:CONST:SORT:NOROOT(1)
+`?`:
+	DW 10
+
+;#endif
+
+      END
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/78K0R/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/78K0R/portmacro.h
new file mode 100644
index 0000000..4267246
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/78K0R/portmacro.h
@@ -0,0 +1,145 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint16_t
+#define portBASE_TYPE   short
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+#if (configUSE_16_BIT_TICKS==1)
+	typedef unsigned int TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS() __asm ( "DI" )
+#define portENABLE_INTERRUPTS()	 __asm ( "EI" )
+/*-----------------------------------------------------------*/
+
+/* Critical section control macros. */
+#define portNO_CRITICAL_SECTION_NESTING		( ( uint16_t ) 0 )
+
+#define portENTER_CRITICAL()													\
+{																				\
+extern volatile uint16_t usCriticalNesting;							\
+																				\
+	portDISABLE_INTERRUPTS();													\
+																				\
+	/* Now interrupts are disabled ulCriticalNesting can be accessed */			\
+	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
+	/* times portENTER_CRITICAL() has been called. */							\
+	usCriticalNesting++;														\
+}
+
+#define portEXIT_CRITICAL()														\
+{																				\
+extern volatile uint16_t usCriticalNesting;							\
+																				\
+	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
+	{																			\
+		/* Decrement the nesting count as we are leaving a critical section. */	\
+		usCriticalNesting--;													\
+																				\
+		/* If the nesting level has reached zero then interrupts should be */	\
+		/* re-enabled. */														\
+		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
+		{																		\
+			portENABLE_INTERRUPTS();											\
+		}																		\
+	}																			\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+extern void vPortStart( void );
+#define portYIELD()	__asm( "BRK" )
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext()
+#define portNOP()	__asm( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Hardwware specifics. */
+#define portBYTE_ALIGNMENT	2
+#define portSTACK_GROWTH	( -1 )
+#define portTICK_PERIOD_MS	( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+
+static __interrupt void P0_isr   (void);
+
+/* --------------------------------------------------------------------------*/
+/* Option-bytes and security ID                                              */
+/* --------------------------------------------------------------------------*/
+#define OPT_BYTES_SIZE     4
+#define SECU_ID_SIZE       10
+#define WATCHDOG_DISABLED  0x00
+#define LVI_ENABLED        0xFE
+#define LVI_DISABLED       0xFF
+#define RESERVED_FF        0xFF
+#define OCD_DISABLED       0x04
+#define OCD_ENABLED        0x81
+#define OCD_ENABLED_ERASE  0x80
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c
new file mode 100644
index 0000000..1171f8a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c
@@ -0,0 +1,300 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* IAR includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#ifndef configSETUP_TICK_INTERRUPT
+	#error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt.  A default that uses the PIT is provided in the official demo application.
+#endif
+
+#ifndef configCLEAR_TICK_INTERRUPT
+	#error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt.  A default that uses the PIT is provided in the official demo application.
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+this value. */
+#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
+
+/* Tasks are not created with a floating point context, but can be given a
+floating point context after they have been created.  A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
+
+/* Constants required to setup the initial task context. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS			( 0x01UL )
+
+/* Masks all bits in the APSR other than the mode bits. */
+#define portAPSR_MODE_BITS_MASK			( 0x1F )
+
+/* The value of the mode bits in the APSR when the CPU is executing in user
+mode. */
+#define portAPSR_USER_MODE				( 0x10 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing.  This function is necessarily written in
+ * assembly code so is implemented in portASM.s.
+ */
+extern void vPortRestoreTaskContext( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting.  This
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts.  As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero
+then a floating point context must be saved and restored for the task. */
+uint32_t ulPortTaskHasFPUContext = pdFALSE;
+
+/* Set to 1 to pend a context switch from an ISR. */
+uint32_t ulPortYieldRequired = pdFALSE;
+
+/* Counts the interrupt nesting depth.  A context switch is only performed if
+if the nesting depth is 0. */
+uint32_t ulPortInterruptNesting = 0UL;
+
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro.
+
+	The fist real value on the stack is the status register, which is set for
+	system mode, with interrupts enabled.  A few NULLs are added first to ensure
+	GDB does not try decoding a non-existent return address. */
+	*pxTopOfStack = NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+	{
+		/* The task will start in THUMB mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+
+	pxTopOfStack--;
+
+	/* Next the return address, which in this case is the start of the task. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+
+	/* Next all the registers other than the stack pointer. */
+	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The task will start with a critical nesting count of 0 as interrupts are
+	enabled. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+	pxTopOfStack--;
+
+	/* The task will start without a floating point context.  A task that uses
+	the floating point hardware must call vPortTaskUsesFPU() before executing
+	any floating point instructions. */
+	*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( ulPortInterruptNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+uint32_t ulAPSR;
+
+	/* Only continue if the CPU is not in User mode.  The CPU must be in a
+	Privileged mode for the scheduler to start. */
+	__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
+	ulAPSR &= portAPSR_MODE_BITS_MASK;
+	configASSERT( ulAPSR != portAPSR_USER_MODE );
+
+	if( ulAPSR != portAPSR_USER_MODE )
+	{
+		/* Start the timer that generates the tick ISR. */
+		configSETUP_TICK_INTERRUPT();
+		vPortRestoreTaskContext();
+	}
+
+	/* Will only get here if vTaskStartScheduler() was called with the CPU in
+	a non-privileged mode or the binary point register was not set to its lowest
+	possible value. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( ulCriticalNesting == 1 )
+	{
+		configASSERT( ulPortInterruptNesting == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as the critical section is being
+		exited. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then all interrupt
+		priorities must be re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Critical nesting has reached zero so all interrupt priorities
+			should be unmasked. */
+			portENABLE_INTERRUPTS();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void FreeRTOS_Tick_Handler( void )
+{
+	portDISABLE_INTERRUPTS();
+
+	/* Increment the RTOS tick. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		ulPortYieldRequired = pdTRUE;
+	}
+
+	portENABLE_INTERRUPTS();
+	configCLEAR_TICK_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortTaskUsesFPU( void )
+{
+uint32_t ulInitialFPSCR = 0;
+
+	/* A task is registering the fact that it needs an FPU context.  Set the
+	FPU flag (which is saved as part of the task context). */
+	ulPortTaskHasFPUContext = pdTRUE;
+
+	/* Initialise the floating point status register. */
+	__asm( "FMXR 	FPSCR, %0" :: "r" (ulInitialFPSCR) );
+}
+/*-----------------------------------------------------------*/
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h
new file mode 100644
index 0000000..d079fc0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h
@@ -0,0 +1,113 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	EXTERN	vTaskSwitchContext
+	EXTERN  ulCriticalNesting
+	EXTERN	pxCurrentTCB
+	EXTERN	ulPortTaskHasFPUContext
+	EXTERN  ulAsmAPIPriorityMask
+
+portSAVE_CONTEXT macro
+
+	; Save the LR and SPSR onto the system mode stack before switching to
+	; system mode to save the remaining system mode registers
+	SRSDB	sp!, #SYS_MODE
+	CPS		#SYS_MODE
+	PUSH	{R0-R12, R14}
+
+	; Push the critical nesting count
+	LDR		R2, =ulCriticalNesting
+	LDR		R1, [R2]
+	PUSH	{R1}
+
+	; Does the task have a floating point context that needs saving?  If
+	; ulPortTaskHasFPUContext is 0 then no.
+	LDR		R2, =ulPortTaskHasFPUContext
+	LDR		R3, [R2]
+	CMP		R3, #0
+
+	; Save the floating point context, if any
+	FMRXNE  R1,  FPSCR
+	VPUSHNE {D0-D15}
+#if configFPU_D32 == 1
+	VPUSHNE	{D16-D31}
+#endif ; configFPU_D32
+	PUSHNE	{R1}
+
+	; Save ulPortTaskHasFPUContext itself
+	PUSH	{R3}
+
+	; Save the stack pointer in the TCB
+	LDR		R0, =pxCurrentTCB
+	LDR		R1, [R0]
+	STR		SP, [R1]
+
+	endm
+
+; /**********************************************************************/
+
+portRESTORE_CONTEXT macro
+
+	; Set the SP to point to the stack of the task being restored.
+	LDR		R0, =pxCurrentTCB
+	LDR		R1, [R0]
+	LDR		SP, [R1]
+
+	; Is there a floating point context to restore?  If the restored
+	; ulPortTaskHasFPUContext is zero then no.
+	LDR		R0, =ulPortTaskHasFPUContext
+	POP		{R1}
+	STR		R1, [R0]
+	CMP		R1, #0
+
+	; Restore the floating point context, if any
+	POPNE 	{R0}
+#if configFPU_D32 == 1
+	VPOPNE	{D16-D31}
+#endif ; configFPU_D32
+	VPOPNE	{D0-D15}
+	VMSRNE  FPSCR, R0
+
+	; Restore the critical section nesting depth
+	LDR		R0, =ulCriticalNesting
+	POP		{R1}
+	STR		R1, [R0]
+
+	; Restore all system mode registers other than the SP (which is already
+	; being used)
+	POP		{R0-R12, R14}
+
+	; Return to the task code, loading CPSR on the way.  CPSR has the interrupt
+	; enable bit set appropriately for the task about to execute.
+	RFEIA	sp!
+
+	endm
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s
new file mode 100644
index 0000000..674049c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s
@@ -0,0 +1,176 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	INCLUDE FreeRTOSConfig.h
+	INCLUDE portmacro.h
+
+	EXTERN	vTaskSwitchContext
+	EXTERN	ulPortYieldRequired
+	EXTERN	ulPortInterruptNesting
+	EXTERN	vApplicationIRQHandler
+
+	PUBLIC	FreeRTOS_SWI_Handler
+	PUBLIC  FreeRTOS_IRQ_Handler
+	PUBLIC 	vPortRestoreTaskContext
+
+SYS_MODE			EQU		0x1f
+SVC_MODE			EQU		0x13
+IRQ_MODE			EQU		0x12
+
+	SECTION .text:CODE:ROOT(2)
+	ARM
+
+	INCLUDE portASM.h
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; SVC handler is used to yield a task.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+FreeRTOS_SWI_Handler
+
+	PRESERVE8
+
+	; Save the context of the current task and select a new task to run.
+	portSAVE_CONTEXT
+	LDR R0, =vTaskSwitchContext
+	BLX	R0
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; vPortRestoreTaskContext is used to start the scheduler.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortRestoreTaskContext
+
+	PRESERVE8
+
+	; Switch to system mode
+	CPS		#SYS_MODE
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; IRQ interrupt handler used when individual priorities cannot be masked
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+FreeRTOS_IRQ_Handler
+
+	PRESERVE8
+
+	; Return to the interrupted instruction.
+	SUB		lr, lr, #4
+
+	; Push the return address and SPSR
+	PUSH	{lr}
+	MRS		lr, SPSR
+	PUSH	{lr}
+
+	; Change to supervisor mode to allow reentry.
+	CPS		#SVC_MODE
+
+	; Push used registers.
+	PUSH	{r0-r4, r12}
+
+	; Increment nesting count.  r3 holds the address of ulPortInterruptNesting
+	; for future use.  r1 holds the original ulPortInterruptNesting value for
+	; future use.
+	LDR		r3, =ulPortInterruptNesting
+	LDR		r1, [r3]
+	ADD		r4, r1, #1
+	STR		r4, [r3]
+
+	; Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
+	; future use.
+	MOV		r2, sp
+	AND		r2, r2, #4
+	SUB		sp, sp, r2
+
+	PUSH	{r0-r4, lr}
+
+	; Call the port part specific handler.
+	LDR		r0, =vApplicationIRQHandler
+	BLX		r0
+	POP		{r0-r4, lr}
+	ADD		sp, sp, r2
+
+	CPSID	i
+
+	; Write to the EOI register.
+	LDR 	r4, =configEOI_ADDRESS
+	STR		r0, [r4]
+
+	; Restore the old nesting count
+	STR		r1, [r3]
+
+	; A context switch is never performed if the nesting count is not 0.
+	CMP		r1, #0
+	BNE		exit_without_switch
+
+	; Did the interrupt request a context switch?  r1 holds the address of
+	; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
+	; use.
+	LDR		r1, =ulPortYieldRequired
+	LDR		r0, [r1]
+	CMP		r0, #0
+	BNE		switch_before_exit
+
+exit_without_switch
+	; No context switch.  Restore used registers, LR_irq and SPSR before
+	; returning.
+	POP		{r0-r4, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	MOVS	PC, LR
+
+switch_before_exit
+	; A context switch is to be performed.  Clear the context switch pending
+	; flag.
+	MOV		r0, #0
+	STR		r0, [r1]
+
+	; Restore used registers, LR-irq and SPSR before saving the context
+	; to the task stack.
+	POP		{r0-r4, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	portSAVE_CONTEXT
+
+	; Call the function that selects the new task to execute.
+	; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
+	; instructions, or 8 byte aligned stack allocated data.  LR does not need
+	; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway.
+	LDR		r0, =vTaskSwitchContext
+	BLX		r0
+
+	; Restore the context of, and branch to, the task selected to execute next.
+	portRESTORE_CONTEXT
+
+	END
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h
new file mode 100644
index 0000000..f5ae853
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h
@@ -0,0 +1,162 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* IAR includes. */
+#ifdef __ICCARM__
+
+	#include 
+
+	#ifdef __cplusplus
+		extern "C" {
+	#endif
+
+	/*-----------------------------------------------------------
+	 * Port specific definitions.
+	 *
+	 * The settings in this file configure FreeRTOS correctly for the given hardware
+	 * and compiler.
+	 *
+	 * These settings should not be altered.
+	 *-----------------------------------------------------------
+	 */
+
+	/* Type definitions. */
+	#define portCHAR		char
+	#define portFLOAT		float
+	#define portDOUBLE		double
+	#define portLONG		long
+	#define portSHORT		short
+	#define portSTACK_TYPE	uint32_t
+	#define portBASE_TYPE	long
+
+	typedef portSTACK_TYPE StackType_t;
+	typedef long BaseType_t;
+	typedef unsigned long UBaseType_t;
+
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+
+	/*-----------------------------------------------------------*/
+
+	/* Hardware specifics. */
+	#define portSTACK_GROWTH			( -1 )
+	#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+	#define portBYTE_ALIGNMENT			8
+
+	/*-----------------------------------------------------------*/
+
+	/* Task utilities. */
+
+	/* Called at the end of an ISR that can cause a context switch. */
+	#define portEND_SWITCHING_ISR( xSwitchRequired )\
+	{												\
+	extern uint32_t ulPortYieldRequired;			\
+													\
+		if( xSwitchRequired != pdFALSE )			\
+		{											\
+			ulPortYieldRequired = pdTRUE;			\
+		}											\
+	}
+
+	#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+	#define portYIELD() __asm volatile ( "SWI 0" ); __ISB()
+
+
+	/*-----------------------------------------------------------
+	 * Critical section control
+	 *----------------------------------------------------------*/
+
+	extern void vPortEnterCritical( void );
+	extern void vPortExitCritical( void );
+	extern uint32_t ulPortSetInterruptMask( void );
+	extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+
+	#define portENTER_CRITICAL()		vPortEnterCritical();
+	#define portEXIT_CRITICAL()			vPortExitCritical();
+	#define portDISABLE_INTERRUPTS()	__disable_irq(); __DSB(); __ISB() /* No priority mask register so global disable is used. */
+	#define portENABLE_INTERRUPTS()		__enable_irq()
+	#define portSET_INTERRUPT_MASK_FROM_ISR()		__get_interrupt_state(); __disable_irq() /* No priority mask register so global disable is used. */
+	#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	__set_interrupt_state(x)
+
+	/*-----------------------------------------------------------*/
+
+	/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+	not required for this port but included in case common demo code that uses these
+	macros is used. */
+	#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+	#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
+
+	/* Prototype of the FreeRTOS tick handler.  This must be installed as the
+	handler for whichever peripheral is used to generate the RTOS tick. */
+	void FreeRTOS_Tick_Handler( void );
+
+	/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+	before any floating point instructions are executed. */
+	void vPortTaskUsesFPU( void );
+	#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+
+	/* Architecture specific optimisations. */
+	#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+		#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+	#endif
+
+	#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+		/* Store/clear the ready priorities in a bit map. */
+		#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+		#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+		/*-----------------------------------------------------------*/
+
+		#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) )
+
+	#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+	#define portNOP() __asm volatile( "NOP" )
+
+
+	#ifdef __cplusplus
+		} /* extern C */
+	#endif
+
+	/* Suppress warnings that are generated by the IAR tools, but cannot be
+	fixed in the source code because to do so would cause other compilers to
+	generate warnings. */
+	#pragma diag_suppress=Pe191
+	#pragma diag_suppress=Pa082
+
+#endif /* __ICCARM__ */
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA9/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA9/port.c
new file mode 100644
index 0000000..69d8723
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA9/port.c
@@ -0,0 +1,439 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* IAR includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
+	#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
+	#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configUNIQUE_INTERRUPT_PRIORITIES
+	#error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configSETUP_TICK_INTERRUPT
+	#error configSETUP_TICK_INTERRUPT() must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif /* configSETUP_TICK_INTERRUPT */
+
+#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/* In case security extensions are implemented. */
+#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+#endif
+
+#ifndef configCLEAR_TICK_INTERRUPT
+	#define configCLEAR_TICK_INTERRUPT()
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+this value. */
+#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
+
+/* In all GICs 255 can be written to the priority mask register to unmask all
+(but the lowest) interrupt priority. */
+#define portUNMASK_VALUE				( 0xFFUL )
+
+/* Tasks are not created with a floating point context, but can be given a
+floating point context after they have been created.  A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
+
+/* Constants required to setup the initial task context. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS			( 0x01UL )
+
+/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
+point is zero. */
+#define portBINARY_POINT_BITS			( ( uint8_t ) 0x03 )
+
+/* Masks all bits in the APSR other than the mode bits. */
+#define portAPSR_MODE_BITS_MASK			( 0x1F )
+
+/* The value of the mode bits in the APSR when the CPU is executing in user
+mode. */
+#define portAPSR_USER_MODE				( 0x10 )
+
+/* Macro to unmask all interrupt priorities. */
+#define portCLEAR_INTERRUPT_MASK()											\
+{																			\
+	__disable_irq();														\
+	portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;					\
+	__asm(	"DSB		\n"													\
+			"ISB		\n" );												\
+	__enable_irq();															\
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing.  This function is necessarily written in
+ * assembly code so is implemented in portASM.s.
+ */
+extern void vPortRestoreTaskContext( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting.  This
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts.  As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero
+then a floating point context must be saved and restored for the task. */
+uint32_t ulPortTaskHasFPUContext = pdFALSE;
+
+/* Set to 1 to pend a context switch from an ISR. */
+uint32_t ulPortYieldRequired = pdFALSE;
+
+/* Counts the interrupt nesting depth.  A context switch is only performed if
+if the nesting depth is 0. */
+uint32_t ulPortInterruptNesting = 0UL;
+
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro.
+
+	The fist real value on the stack is the status register, which is set for
+	system mode, with interrupts enabled.  A few NULLs are added first to ensure
+	GDB does not try decoding a non-existent return address. */
+	*pxTopOfStack = NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+	{
+		/* The task will start in THUMB mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+
+	pxTopOfStack--;
+
+	/* Next the return address, which in this case is the start of the task. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+
+	/* Next all the registers other than the stack pointer. */
+	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The task will start with a critical nesting count of 0 as interrupts are
+	enabled. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+	pxTopOfStack--;
+
+	/* The task will start without a floating point context.  A task that uses
+	the floating point hardware must call vPortTaskUsesFPU() before executing
+	any floating point instructions. */
+	*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( ulPortInterruptNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+uint32_t ulAPSR;
+
+	/* Only continue if the CPU is not in User mode.  The CPU must be in a
+	Privileged mode for the scheduler to start. */
+	__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
+	ulAPSR &= portAPSR_MODE_BITS_MASK;
+	configASSERT( ulAPSR != portAPSR_USER_MODE );
+
+	if( ulAPSR != portAPSR_USER_MODE )
+	{
+		/* Only continue if the binary point value is set to its lowest possible
+		setting.  See the comments in vPortValidateInterruptPriority() below for
+		more information. */
+		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+
+		if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
+		{
+			/* Start the timer that generates the tick ISR. */
+			configSETUP_TICK_INTERRUPT();
+
+			__enable_irq();
+			vPortRestoreTaskContext();
+		}
+	}
+
+	/* Will only get here if vTaskStartScheduler() was called with the CPU in
+	a non-privileged mode or the binary point register was not set to its lowest
+	possible value. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 	*/
+	ulPortSetInterruptMask();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+	
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API 
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( ulCriticalNesting == 1 )
+	{
+		configASSERT( ulPortInterruptNesting == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as the critical section is being
+		exited. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then all interrupt
+		priorities must be re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Critical nesting has reached zero so all interrupt priorities
+			should be unmasked. */
+			portCLEAR_INTERRUPT_MASK();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void FreeRTOS_Tick_Handler( void )
+{
+	/* Set interrupt mask before altering scheduler structures.   The tick
+	handler runs at the lowest priority, so interrupts cannot already be masked,
+	so there is no need to save and restore the current mask value. */
+	__disable_irq();
+	portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+	__asm(	"DSB		\n"
+			"ISB		\n" );
+	__enable_irq();
+
+	/* Increment the RTOS tick. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		ulPortYieldRequired = pdTRUE;
+	}
+
+	/* Ensure all interrupt priorities are active again. */
+	portCLEAR_INTERRUPT_MASK();
+	configCLEAR_TICK_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortTaskUsesFPU( void )
+{
+uint32_t ulInitialFPSCR = 0;
+
+	/* A task is registering the fact that it needs an FPU context.  Set the
+	FPU flag (which is saved as part of the task context). */
+	ulPortTaskHasFPUContext = pdTRUE;
+
+	/* Initialise the floating point status register. */
+	__asm( "FMXR 	FPSCR, %0" :: "r" (ulInitialFPSCR) );
+}
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMask( uint32_t ulNewMaskValue )
+{
+	if( ulNewMaskValue == pdFALSE )
+	{
+		portCLEAR_INTERRUPT_MASK();
+	}
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortSetInterruptMask( void )
+{
+uint32_t ulReturn;
+
+	__disable_irq();
+	if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
+	{
+		/* Interrupts were already masked. */
+		ulReturn = pdTRUE;
+	}
+	else
+	{
+		ulReturn = pdFALSE;
+		portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+		__asm(	"DSB		\n"
+				"ISB		\n" );
+	}
+	__enable_irq();
+
+	return ulReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+		/* The following assertion will fail if a service routine (ISR) for
+		an interrupt that has been assigned a priority above
+		configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+		function.  ISR safe FreeRTOS API functions must *only* be called
+		from interrupts that have been assigned a priority at or below
+		configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+		Numerically low interrupt priority numbers represent logically high
+		interrupt priorities, therefore the priority of the interrupt must
+		be set to a value equal to or numerically *higher* than
+		configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+		FreeRTOS maintains separate thread and ISR API functions to ensure
+		interrupt entry is as fast and simple as possible.
+
+		The following links provide detailed information:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html
+		http://www.freertos.org/FAQHelp.html */
+		configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+
+		/* Priority grouping:  The interrupt controller (GIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		The priority grouping is configured by the GIC's binary point register
+		(ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
+		possible value (which may be above 0). */
+		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.h
new file mode 100644
index 0000000..7c15091
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.h
@@ -0,0 +1,115 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	EXTERN	vTaskSwitchContext
+	EXTERN  ulCriticalNesting
+	EXTERN	pxCurrentTCB
+	EXTERN	ulPortTaskHasFPUContext
+	EXTERN  ulAsmAPIPriorityMask
+
+portSAVE_CONTEXT macro
+
+	; Save the LR and SPSR onto the system mode stack before switching to
+	; system mode to save the remaining system mode registers
+	SRSDB	sp!, #SYS_MODE
+	CPS		#SYS_MODE
+	PUSH	{R0-R12, R14}
+
+	; Push the critical nesting count
+	LDR		R2, =ulCriticalNesting
+	LDR		R1, [R2]
+	PUSH	{R1}
+
+	; Does the task have a floating point context that needs saving?  If
+	; ulPortTaskHasFPUContext is 0 then no.
+	LDR		R2, =ulPortTaskHasFPUContext
+	LDR		R3, [R2]
+	CMP		R3, #0
+
+	; Save the floating point context, if any
+	FMRXNE  R1,  FPSCR
+	VPUSHNE {D0-D15}
+	VPUSHNE	{D16-D31}
+	PUSHNE	{R1}
+
+	; Save ulPortTaskHasFPUContext itself
+	PUSH	{R3}
+
+	; Save the stack pointer in the TCB
+	LDR		R0, =pxCurrentTCB
+	LDR		R1, [R0]
+	STR		SP, [R1]
+
+	endm
+
+; /**********************************************************************/
+
+portRESTORE_CONTEXT macro
+
+	; Set the SP to point to the stack of the task being restored.
+	LDR		R0, =pxCurrentTCB
+	LDR		R1, [R0]
+	LDR		SP, [R1]
+
+	; Is there a floating point context to restore?  If the restored
+	; ulPortTaskHasFPUContext is zero then no.
+	LDR		R0, =ulPortTaskHasFPUContext
+	POP		{R1}
+	STR		R1, [R0]
+	CMP		R1, #0
+
+	; Restore the floating point context, if any
+	POPNE 	{R0}
+	VPOPNE	{D16-D31}
+	VPOPNE	{D0-D15}
+	VMSRNE  FPSCR, R0
+
+	; Restore the critical section nesting depth
+	LDR		R0, =ulCriticalNesting
+	POP		{R1}
+	STR		R1, [R0]
+
+	; Ensure the priority mask is correct for the critical nesting depth
+	LDR		R2, =portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS
+	CMP		R1, #0
+	MOVEQ	R4, #255
+	LDRNE	R4, =( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT )
+	STR		R4, [r2]
+
+	; Restore all system mode registers other than the SP (which is already
+	; being used)
+	POP		{R0-R12, R14}
+
+	; Return to the task code, loading CPSR on the way.
+	RFEIA	sp!
+
+	endm
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.s
new file mode 100644
index 0000000..d50e561
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.s
@@ -0,0 +1,177 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	INCLUDE FreeRTOSConfig.h
+	INCLUDE portmacro.h
+
+	EXTERN	vApplicationIRQHandler
+	EXTERN	vTaskSwitchContext
+	EXTERN	ulPortYieldRequired
+	EXTERN	ulPortInterruptNesting
+
+	PUBLIC	FreeRTOS_SWI_Handler
+	PUBLIC  FreeRTOS_IRQ_Handler
+	PUBLIC 	vPortRestoreTaskContext
+
+SYS_MODE			EQU		0x1f
+SVC_MODE			EQU		0x13
+IRQ_MODE			EQU		0x12
+
+
+	SECTION .text:CODE:ROOT(2)
+	ARM
+
+	INCLUDE portASM.h
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; SVC handler is used to yield a task.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+FreeRTOS_SWI_Handler
+
+	PRESERVE8
+
+	; Save the context of the current task and select a new task to run.
+	portSAVE_CONTEXT
+	LDR R0, =vTaskSwitchContext
+	BLX	R0
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; vPortRestoreTaskContext is used to start the scheduler.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortRestoreTaskContext
+	; Switch to system mode
+	CPS		#SYS_MODE
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; PL390 GIC interrupt handler
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+FreeRTOS_IRQ_Handler
+
+	; Return to the interrupted instruction.
+	SUB		lr, lr, #4
+
+	; Push the return address and SPSR
+	PUSH	{lr}
+	MRS		lr, SPSR
+	PUSH	{lr}
+
+	; Change to supervisor mode to allow reentry.
+	CPS		#SVC_MODE
+
+	; Push used registers.
+	PUSH	{r0-r4, r12}
+
+	; Increment nesting count.  r3 holds the address of ulPortInterruptNesting
+	; for future use.  r1 holds the original ulPortInterruptNesting value for
+	; future use.
+	LDR		r3, =ulPortInterruptNesting
+	LDR		r1, [r3]
+	ADD		r4, r1, #1
+	STR		r4, [r3]
+
+	; Read value from the interrupt acknowledge register, which is stored in r0
+	; for future parameter and interrupt clearing use.
+	LDR 	r2, =portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS
+	LDR		r0, [r2]
+
+	; Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
+	; future use.  _RB_ Is this ever necessary if start of stack is 8-byte aligned?
+	MOV		r2, sp
+	AND		r2, r2, #4
+	SUB		sp, sp, r2
+
+	; Call the interrupt handler.  r4 is pushed to maintain alignment.
+	PUSH	{r0-r4, lr}
+	LDR		r1, =vApplicationIRQHandler
+	BLX		r1
+	POP		{r0-r4, lr}
+	ADD		sp, sp, r2
+
+	CPSID	i
+
+	; Write the value read from ICCIAR to ICCEOIR
+	LDR 	r4, =portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS
+	STR		r0, [r4]
+
+	; Restore the old nesting count
+	STR		r1, [r3]
+
+	; A context switch is never performed if the nesting count is not 0
+	CMP		r1, #0
+	BNE		exit_without_switch
+
+	; Did the interrupt request a context switch?  r1 holds the address of
+	; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
+	; use.
+	LDR		r1, =ulPortYieldRequired
+	LDR		r0, [r1]
+	CMP		r0, #0
+	BNE		switch_before_exit
+
+exit_without_switch
+	; No context switch.  Restore used registers, LR_irq and SPSR before
+	; returning.
+	POP		{r0-r4, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	MOVS	PC, LR
+
+switch_before_exit
+	; A context switch is to be performed.  Clear the context switch pending
+	; flag.
+	MOV		r0, #0
+	STR		r0, [r1]
+
+	; Restore used registers, LR-irq and SPSR before saving the context
+	; to the task stack.
+	POP		{r0-r4, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	portSAVE_CONTEXT
+
+	; Call the function that selects the new task to execute.
+	; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
+	; instructions, or 8 byte aligned stack allocated data.  LR does not need
+	; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway.
+	LDR		r0, =vTaskSwitchContext
+	BLX		r0
+
+	; Restore the context of, and branch to, the task selected to execute next.
+	portRESTORE_CONTEXT
+
+
+	END
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA9/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA9/portmacro.h
new file mode 100644
index 0000000..4f6c303
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CA9/portmacro.h
@@ -0,0 +1,209 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* IAR includes. */
+#ifdef __ICCARM__
+
+	#include 
+
+	#ifdef __cplusplus
+		extern "C" {
+	#endif
+
+	/*-----------------------------------------------------------
+	 * Port specific definitions.
+	 *
+	 * The settings in this file configure FreeRTOS correctly for the given hardware
+	 * and compiler.
+	 *
+	 * These settings should not be altered.
+	 *-----------------------------------------------------------
+	 */
+
+	/* Type definitions. */
+	#define portCHAR		char
+	#define portFLOAT		float
+	#define portDOUBLE		double
+	#define portLONG		long
+	#define portSHORT		short
+	#define portSTACK_TYPE	uint32_t
+	#define portBASE_TYPE	long
+
+	typedef portSTACK_TYPE StackType_t;
+	typedef long BaseType_t;
+	typedef unsigned long UBaseType_t;
+
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+
+	/*-----------------------------------------------------------*/
+
+	/* Hardware specifics. */
+	#define portSTACK_GROWTH			( -1 )
+	#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+	#define portBYTE_ALIGNMENT			8
+
+	/*-----------------------------------------------------------*/
+
+	/* Task utilities. */
+
+	/* Called at the end of an ISR that can cause a context switch. */
+	#define portEND_SWITCHING_ISR( xSwitchRequired )\
+	{												\
+	extern uint32_t ulPortYieldRequired;			\
+													\
+		if( xSwitchRequired != pdFALSE )			\
+		{											\
+			ulPortYieldRequired = pdTRUE;			\
+		}											\
+	}
+
+	#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+	#define portYIELD() __asm( "SWI 0" );
+
+
+	/*-----------------------------------------------------------
+	 * Critical section control
+	 *----------------------------------------------------------*/
+
+	extern void vPortEnterCritical( void );
+	extern void vPortExitCritical( void );
+	extern uint32_t ulPortSetInterruptMask( void );
+	extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+
+	/* These macros do not globally disable/enable interrupts.  They do mask off
+	interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+	#define portENTER_CRITICAL()		vPortEnterCritical();
+	#define portEXIT_CRITICAL()			vPortExitCritical();
+	#define portDISABLE_INTERRUPTS()	ulPortSetInterruptMask()
+	#define portENABLE_INTERRUPTS()		vPortClearInterruptMask( 0 )
+	#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortSetInterruptMask()
+	#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask(x)
+
+	/*-----------------------------------------------------------*/
+
+	/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+	not required for this port but included in case common demo code that uses these
+	macros is used. */
+	#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+	#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
+
+	/* Prototype of the FreeRTOS tick handler.  This must be installed as the
+	handler for whichever peripheral is used to generate the RTOS tick. */
+	void FreeRTOS_Tick_Handler( void );
+
+	/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+	before any floating point instructions are executed. */
+	void vPortTaskUsesFPU( void );
+	#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+
+	#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+	#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+
+	/* Architecture specific optimisations. */
+	#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+		#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+	#endif
+
+	#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+		/* Store/clear the ready priorities in a bit map. */
+		#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+		#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+		/*-----------------------------------------------------------*/
+
+		#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) )
+
+	#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+	#ifdef configASSERT
+		void vPortValidateInterruptPriority( void );
+		#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+	#endif /* configASSERT */
+
+	#define portNOP() __asm volatile( "NOP" )
+
+
+	#ifdef __cplusplus
+		} /* extern C */
+	#endif
+
+	/* Suppress warnings that are generated by the IAR tools, but cannot be
+	fixed in the source code because to do so would cause other compilers to
+	generate warnings. */
+	#pragma diag_suppress=Pe191
+	#pragma diag_suppress=Pa082
+
+#endif /* __ICCARM__ */
+
+
+/* The number of bits to shift for an interrupt priority is dependent on the
+number of bits implemented by the interrupt controller. */
+#if configUNIQUE_INTERRUPT_PRIORITIES == 16
+	#define portPRIORITY_SHIFT 4
+	#define portMAX_BINARY_POINT_VALUE	3
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
+	#define portPRIORITY_SHIFT 3
+	#define portMAX_BINARY_POINT_VALUE	2
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
+	#define portPRIORITY_SHIFT 2
+	#define portMAX_BINARY_POINT_VALUE	1
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
+	#define portPRIORITY_SHIFT 1
+	#define portMAX_BINARY_POINT_VALUE	0
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
+	#define portPRIORITY_SHIFT 0
+	#define portMAX_BINARY_POINT_VALUE	0
+#else
+	#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
+#endif
+
+/* Interrupt controller access addresses. */
+#define portICCPMR_PRIORITY_MASK_OFFSET  						( 0x04 )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET 				( 0x0C )
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET 					( 0x10 )
+#define portICCBPR_BINARY_POINT_OFFSET							( 0x08 )
+#define portICCRPR_RUNNING_PRIORITY_OFFSET						( 0x14 )
+
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS 		( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER 					( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS 	( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS 		( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS 			( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+#define portICCBPR_BINARY_POINT_REGISTER 					( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+#define portICCRPR_RUNNING_PRIORITY_REGISTER 				( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM0/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM0/port.c
new file mode 100644
index 0000000..41b7d43
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM0/port.c
@@ -0,0 +1,218 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM0 port.
+ *----------------------------------------------------------*/
+
+/* IAR includes. */
+#include "intrinsics.h"
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to manipulate the NVIC. */
+#define portNVIC_SYSTICK_CTRL			( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD			( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE	( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_SYSPRI2			( ( volatile uint32_t *) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK		0x00000004
+#define portNVIC_SYSTICK_INT		0x00000002
+#define portNVIC_SYSTICK_ENABLE		0x00000001
+#define portMIN_INTERRUPT_PRIORITY	( 255UL )
+#define portNVIC_PENDSV_PRI			( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI		( portMIN_INTERRUPT_PRIORITY << 24UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR			( 0x01000000 )
+
+/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
+defined.  The value 255 should also ensure backward compatibility.
+FreeRTOS.org versions prior to V4.3.0 did not include this definition. */
+#ifndef configKERNEL_INTERRUPT_PRIORITY
+	#define configKERNEL_INTERRUPT_PRIORITY 0
+#endif
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortSysTickHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+extern void vPortStartFirstTask( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* LR */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+	pxTopOfStack -= 8; /* R11..R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	*(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
+	*(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Start the first task. */
+	vPortStartFirstTask();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortYield( void )
+{
+	/* Set a PendSV to request a context switch. */
+	*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
+
+	/* Barriers are normally not required but do ensure the code is completely
+	within the specified behaviour for the architecture. */
+	__DSB();
+	__ISB();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+	__DSB();
+	__ISB();
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+uint32_t ulPreviousMask;
+
+	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+	/* Stop and reset the SysTick. */
+	*(portNVIC_SYSTICK_CTRL) = 0UL;
+	*(portNVIC_SYSTICK_CURRENT_VALUE) = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	*(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	*(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM0/portasm.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM0/portasm.s
new file mode 100644
index 0000000..76f48c4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM0/portasm.s
@@ -0,0 +1,131 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include 
+
+	RSEG    CODE:CODE(2)
+	thumb
+
+	EXTERN vPortYieldFromISR
+	EXTERN pxCurrentTCB
+	EXTERN vTaskSwitchContext
+
+	PUBLIC vSetMSP
+	PUBLIC xPortPendSVHandler
+	PUBLIC vPortSVCHandler
+	PUBLIC vPortStartFirstTask
+	PUBLIC ulSetInterruptMaskFromISR
+	PUBLIC vClearInterruptMaskFromISR
+
+/*-----------------------------------------------------------*/
+
+vSetMSP
+	msr msp, r0
+	bx lr
+
+/*-----------------------------------------------------------*/
+
+xPortPendSVHandler:
+	mrs r0, psp
+
+	ldr	r3, =pxCurrentTCB	/* Get the location of the current TCB. */
+	ldr	r2, [r3]
+
+	subs r0, r0, #32		/* Make space for the remaining low registers. */
+	str r0, [r2]			/* Save the new top of stack. */
+	stmia r0!, {r4-r7}		/* Store the low registers that are not saved automatically. */
+	mov r4, r8				/* Store the high registers. */
+	mov r5, r9
+	mov r6, r10
+	mov r7, r11
+	stmia r0!, {r4-r7}
+
+	push {r3, r14}
+	cpsid i
+	bl vTaskSwitchContext
+	cpsie i
+	pop {r2, r3}			/* lr goes in r3. r2 now holds tcb pointer. */
+
+	ldr r1, [r2]
+	ldr r0, [r1]			/* The first item in pxCurrentTCB is the task top of stack. */
+	adds r0, r0, #16		/* Move to the high registers. */
+	ldmia r0!, {r4-r7}		/* Pop the high registers. */
+	mov r8, r4
+	mov r9, r5
+	mov r10, r6
+	mov r11, r7
+
+	msr psp, r0				/* Remember the new top of stack for the task. */
+
+	subs r0, r0, #32		/* Go back for the low registers that are not automatically restored. */
+	ldmia r0!, {r4-r7}		/* Pop low registers.  */
+
+	bx r3
+
+/*-----------------------------------------------------------*/
+
+vPortSVCHandler;
+	/* This function is no longer used, but retained for backward
+	compatibility. */
+	bx lr
+
+/*-----------------------------------------------------------*/
+
+vPortStartFirstTask
+	/* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
+	table offset register that can be used to locate the initial stack value.
+	Not all M0 parts have the application vector table at address 0. */
+
+	ldr	r3, =pxCurrentTCB	/* Obtain location of pxCurrentTCB. */
+	ldr r1, [r3]
+	ldr r0, [r1]			/* The first item in pxCurrentTCB is the task top of stack. */
+	adds r0, #32			/* Discard everything up to r0. */
+	msr psp, r0				/* This is now the new top of stack to use in the task. */
+	movs r0, #2				/* Switch to the psp stack. */
+	msr CONTROL, r0
+	isb
+	pop {r0-r5}				/* Pop the registers that are saved automatically. */
+	mov lr, r5				/* lr is now in r5. */
+	pop {r3}				/* The return address is now in r3. */
+	pop {r2}				/* Pop and discard the XPSR. */
+	cpsie i					/* The first task has its context and interrupts can be enabled. */
+	bx r3					/* Jump to the user defined task code. */
+
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMaskFromISR
+	mrs r0, PRIMASK
+	cpsid i
+	bx lr
+
+/*-----------------------------------------------------------*/
+
+vClearInterruptMaskFromISR
+	msr PRIMASK, r0
+	bx lr
+
+	END
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM0/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM0/portmacro.h
new file mode 100644
index 0000000..11f362c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM0/portmacro.h
@@ -0,0 +1,122 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+extern void vPortYield( void );
+#define portNVIC_INT_CTRL			( ( volatile uint32_t *) 0xe000ed04 )
+#define portNVIC_PENDSVSET			0x10000000
+#define portYIELD()					vPortYield()
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) 	*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulSetInterruptMaskFromISR( void );
+extern void vClearInterruptMaskFromISR( uint32_t ulMask );
+
+#define portDISABLE_INTERRUPTS()				__asm volatile( "cpsid i" )
+#define portENABLE_INTERRUPTS()					__asm volatile( "cpsie i" )
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vClearInterruptMaskFromISR( x )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#define portNOP()
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+the source code because to do so would cause other compilers to generate
+warnings. */
+#pragma diag_suppress=Pa082
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/port.c
new file mode 100644
index 0000000..b0394fb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/* Secure components includes. */
+	#include "secure_context.h"
+	#include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK				( 0x00000004 )
+#define portNVIC_SYSTICK_INT				( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
+#define portNVIC_PENDSVSET					( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY			( 255UL )
+#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE				( 3UL )
+#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS					( 20UL )
+#define portCPACR_CP11_POS					( 22UL )
+
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS					( 31UL )
+#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS					( 30UL )
+#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS				( 0UL )
+#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS				( 8UL )
+#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS				( 16UL )
+#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS				( 24UL )
+#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS				( 0UL )
+#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS				( 8UL )
+#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS				( 16UL )
+#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS				( 24UL )
+#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE			( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE						( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR					( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         FD
+	 * 1111 1111  1111 1111  1111 1111  1111 1101
+	 *
+	 * Bit[6] - 1 --> The exception was taken from the Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 1 --> The exception was taken to the Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
+#else
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         BC
+	 * 1111 1111  1111 1111  1111 1111  1011 1100
+	 *
+	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS			prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS				1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT				0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Setup the Memory Protection Unit (MPU).
+	 */
+	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+	/**
+	 * @brief Setup the Floating Point Unit (FPU).
+	 */
+	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Saved as part of the task context to indicate which context the
+	 * task is using on the secure side.
+	 */
+	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Stop and reset the SysTick. */
+	*( portNVIC_SYSTICK_CTRL ) = 0UL;
+	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+	/* A function that implements a task must not exit or attempt to return to
+	 * its caller as there is nothing to return to. If a task wants to exit it
+	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
+	 * to be triggered if configASSERT() is defined, then stop here so
+	 * application writers can catch the error. */
+	configASSERT( ulCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		 * started to remove a compiler warning about the function being
+		 * defined but never called.  ulDummy is used purely to quieten other
+		 * warnings about code appearing after this function is called - making
+		 * ulDummy volatile makes the compiler think the function could return
+		 * and therefore not output an 'unreachable code' warning for code that
+		 * appears after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __privileged_functions_start__;
+		extern uint32_t * __privileged_functions_end__;
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+		extern uint32_t * __unprivileged_flash_start__;
+		extern uint32_t * __unprivileged_flash_end__;
+		extern uint32_t * __privileged_sram_start__;
+		extern uint32_t * __privileged_sram_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __privileged_functions_start__[];
+		extern uint32_t __privileged_functions_end__[];
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+		extern uint32_t __unprivileged_flash_start__[];
+		extern uint32_t __unprivileged_flash_end__[];
+		extern uint32_t __privileged_sram_start__[];
+		extern uint32_t __privileged_sram_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+
+		/* Check that the MPU is present. */
+		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+		{
+			/* MAIR0 - Index 0. */
+			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+			/* MAIR0 - Index 1. */
+			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+			/* Setup privileged flash as Read Only so that privileged tasks can
+			 * read it but not modify. */
+			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged flash as Read Only by both privileged and
+			 * unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged syscalls flash as Read Only by both privileged
+			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup RAM containing kernel data for privileged access only. */
+			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+								( portMPU_REGION_EXECUTE_NEVER );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Enable mem fault. */
+			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+			/* Enable MPU with privileged background access i.e. unmapped
+			 * regions have privileged access. */
+			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			/* Enable non-secure access to the FPU. */
+			SecureInit_EnableNSFPUAccess();
+		}
+		#endif /* configENABLE_TRUSTZONE */
+
+		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+		 * unprivileged code should be able to access FPU. CP11 should be
+		 * programmed to the same value as CP10. */
+		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+							);
+
+		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
+		 * context on exception entry and restore on exception return.
+		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
+		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+	}
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Set a PendSV to request a context switch. */
+	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	portDISABLE_INTERRUPTS();
+	ulCriticalNesting++;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	configASSERT( ulCriticalNesting );
+	ulCriticalNesting--;
+
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	uint32_t ulR0;
+	#if( configENABLE_MPU == 1 )
+		uint32_t ulControl, ulIsTaskPrivileged;
+	#endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
+	 * R12, LR, PC, xPSR. */
+	ulPC = pulCallerStackAddress[ 6 ];
+	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+	switch( ucSVCNumber )
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+			case portSVC_ALLOCATE_SECURE_CONTEXT:
+			{
+				/* R0 contains the stack size passed as parameter to the
+				 * vPortAllocateSecureContext function. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Read the CONTROL register value. */
+					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+					/* The task that raised the SVC is privileged if Bit[0]
+					 * in the CONTROL register is 0. */
+					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+				}
+				#else
+				{
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0 );
+				}
+				#endif /* configENABLE_MPU */
+
+				configASSERT( xSecureContext != NULL );
+				SecureContext_LoadContext( xSecureContext );
+			}
+			break;
+
+			case portSVC_FREE_SECURE_CONTEXT:
+			{
+				/* R0 contains the secure context handle to be freed. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				/* Free the secure context. */
+				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+			}
+			break;
+		#endif /* configENABLE_TRUSTZONE */
+
+		case portSVC_START_SCHEDULER:
+		{
+			#if( configENABLE_TRUSTZONE == 1 )
+			{
+				/* De-prioritize the non-secure exceptions so that the
+				 * non-secure pendSV runs at the lowest priority. */
+				SecureInit_DePrioritizeNSExceptions();
+
+				/* Initialize the secure context management system. */
+				SecureContext_Init();
+			}
+			#endif /* configENABLE_TRUSTZONE */
+
+			#if( configENABLE_FPU == 1 )
+			{
+				/* Setup the Floating Point Unit (FPU). */
+				prvSetupFPU();
+			}
+			#endif /* configENABLE_FPU */
+
+			/* Setup the context of the first task so that the first task starts
+			 * executing. */
+			vRestoreContextOfFirstTask();
+		}
+		break;
+
+		#if( configENABLE_MPU == 1 )
+			case portSVC_RAISE_PRIVILEGE:
+			{
+				/* Only raise the privilege, if the svc was raised from any of
+				 * the system calls. */
+				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+				{
+					vRaisePrivilege();
+				}
+			}
+			break;
+		#endif /* configENABLE_MPU */
+
+		default:
+		{
+			/* Incorrect SVC call. */
+			configASSERT( pdFALSE );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	 * interrupt. */
+	#if( portPRELOAD_REGISTERS == 0 )
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
+		*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#else /* portPRELOAD_REGISTERS */
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
+		pxTopOfStack--;
+		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#endif /* portPRELOAD_REGISTERS */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+	#if( configENABLE_MPU == 1 )
+	{
+		/* Setup the Memory Protection Unit (MPU). */
+		prvSetupMPU();
+	}
+	#endif /* configENABLE_MPU */
+
+	/* Start the timer that generates the tick ISR. Interrupts are disabled
+	 * here already. */
+	prvSetupTimerInterrupt();
+
+	/* Initialize the critical nesting count ready for the first task. */
+	ulCriticalNesting = 0;
+
+	/* Start the first task. */
+	vStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing. Call the task
+	 * exit error function to prevent compiler warnings about a static function
+	 * not being called in the case that the application writer overrides this
+	 * functionality by defining configTASK_RETURN_ADDRESS. Call
+	 * vTaskSwitchContext() so link time optimization does not remove the
+	 * symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Not implemented in ports where there is nothing to return to.
+	 * Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+	{
+	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+	int32_t lIndex = 0;
+
+		/* Setup MAIR0. */
+		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+		/* This function is called automatically when the task is created - in
+		 * which case the stack region parameters will be valid.  At all other
+		 * times the stack parameters will not be valid and it is assumed that
+		 * the stack region has already been configured. */
+		if( ulStackDepth > 0 )
+		{
+			/* Define the region that allows access to the stack. */
+			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
+															( portMPU_REGION_NON_SHAREABLE ) |
+															( portMPU_REGION_READ_WRITE ) |
+															( portMPU_REGION_EXECUTE_NEVER );
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
+															( portMPU_RLAR_ATTR_INDEX0 ) |
+															( portMPU_RLAR_REGION_ENABLE );
+		}
+
+		/* User supplied configurable regions. */
+		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+		{
+			/* If xRegions is NULL i.e. the task has not specified any MPU
+			 * region, the else part ensures that all the configurable MPU
+			 * regions are invalidated. */
+			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+			{
+				/* Translate the generic region definition contained in xRegions
+				 * into the ARMv8 specific MPU settings that are then stored in
+				 * xMPUSettings. */
+				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+				/* Start address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
+																			( portMPU_REGION_NON_SHAREABLE );
+
+				/* RO/RW. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+				}
+				else
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+				}
+
+				/* XN. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+				}
+
+				/* End Address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
+																			( portMPU_RLAR_REGION_ENABLE );
+
+				/* Normal memory/ Device memory. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+				{
+					/* Attr1 in MAIR0 is configured as device memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+				}
+				else
+				{
+					/* Attr1 in MAIR0 is configured as normal memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+				}
+			}
+			else
+			{
+				/* Invalidate the region. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+			}
+
+			lIndex++;
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.h
new file mode 100644
index 0000000..6314e96
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.s
new file mode 100644
index 0000000..36872fa
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.s
@@ -0,0 +1,377 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	EXTERN pxCurrentTCB
+	EXTERN xSecureContext
+	EXTERN vTaskSwitchContext
+	EXTERN vPortSVCHandler_C
+	EXTERN SecureContext_SaveContext
+	EXTERN SecureContext_LoadContext
+
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
+	PUBLIC vPortAllocateSecureContext
+	PUBLIC vRestoreContextOfFirstTask
+	PUBLIC vRaisePrivilege
+	PUBLIC vStartFirstTask
+	PUBLIC ulSetInterruptMaskFromISR
+	PUBLIC vClearInterruptMaskFromISR
+	PUBLIC PendSV_Handler
+	PUBLIC SVC_Handler
+	PUBLIC vPortFreeSecureContext
+
+#if ( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+	mrs r0, control							/* r0 = CONTROL. */
+	movs r1, #1								/* r1 = 1. */
+	tst r0, r1								/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+	beq running_privileged					/* If the result of previous AND operation was 0, branch. */
+	movs r0, #0								/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	bx lr									/* Return. */
+	running_privileged:
+		movs r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+		bx lr								/* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+	mrs r0, control							/* r0 = CONTROL. */
+	movs r1, #1								/* r1 = 1. */
+	orrs r0, r1								/* r0 = r0 | r1. */
+	msr control, r0							/* CONTROL = r0. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vPortAllocateSecureContext:
+	svc 0									/* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION privileged_functions:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr  r3, [r2]							/* Read pxCurrentTCB. */
+	ldr  r0, [r3]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	movs r5, #1								/* r5 = 1. */
+	bics r4, r5								/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+	str r4, [r2]							/* Disable MPU. */
+
+	adds r3, #4								/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+	ldr  r4, [r3]							/* r4 = *r3 i.e. r4 = MAIR0. */
+	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str  r4, [r2]							/* Program MAIR0. */
+	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+	adds r3, #4								/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+	movs r5, #4								/* r5 = 4. */
+	str  r5, [r2]							/* Program RNR = 4. */
+	ldmia r3!, {r6,r7}						/* Read first set of RBAR/RLAR from TCB. */
+	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
+	stmia r4!, {r6,r7}						/* Write first set of RBAR/RLAR registers. */
+	movs r5, #5								/* r5 = 5. */
+	str  r5, [r2]							/* Program RNR = 5. */
+	ldmia r3!, {r6,r7}						/* Read second set of RBAR/RLAR from TCB. */
+	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
+	stmia r4!, {r6,r7}						/* Write second set of RBAR/RLAR registers. */
+	movs r5, #6								/* r5 = 6. */
+	str  r5, [r2]							/* Program RNR = 6. */
+	ldmia r3!, {r6,r7}						/* Read third set of RBAR/RLAR from TCB. */
+	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
+	stmia r4!, {r6,r7}						/* Write third set of RBAR/RLAR registers. */
+	movs r5, #7								/* r5 = 7. */
+	str  r5, [r2]							/* Program RNR = 7. */
+	ldmia r3!, {r6,r7}						/* Read fourth set of RBAR/RLAR from TCB. */
+	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
+	stmia r4!, {r6,r7}						/* Write fourth set of RBAR/RLAR registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	movs r5, #1								/* r5 = 1. */
+	orrs r4, r5								/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+	str r4, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldm  r0!, {r1-r4}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+	ldr  r5, =xSecureContext
+	str  r1, [r5]							/* Set xSecureContext to this task's value for the same. */
+	msr  psplim, r2							/* Set this task's PSPLIM value. */
+	msr  control, r3						/* Set this task's CONTROL value. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r4									/* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+	ldm  r0!, {r1-r3}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+	ldr  r4, =xSecureContext
+	str  r1, [r4]							/* Set xSecureContext to this task's value for the same. */
+	msr  psplim, r2							/* Set this task's PSPLIM value. */
+	movs r1, #2								/* r1 = 2. */
+	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r3									/* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+	mrs r0, control							/* Read the CONTROL register. */
+	movs r1, #1								/* r1 = 1. */
+	bics r0, r1								/* Clear the bit 0. */
+	msr control, r0							/* Write back the new CONTROL value. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
+	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
+	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
+	msr msp, r0								/* Set the MSP back to the start of the stack. */
+	cpsie i									/* Globally enable interrupts. */
+	dsb
+	isb
+	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMaskFromISR:
+	mrs r0, PRIMASK
+	cpsid i
+	bx lr
+/*-----------------------------------------------------------*/
+
+vClearInterruptMaskFromISR:
+	msr PRIMASK, r0
+	bx lr
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+	mrs r1, psp								/* Read PSP in r1. */
+	ldr r2, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	ldr r0, [r2]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+
+	cbz r0, save_ns_context					/* No secure context to save. */
+	push {r0-r2, r14}
+	bl SecureContext_SaveContext
+	pop {r0-r3}								/* LR is now in r3. */
+	mov lr, r3								/* LR = r3. */
+	lsls r2, r3, #25						/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	bpl save_ns_context						/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r2, [r3]							/* Read pxCurrentTCB. */
+#if ( configENABLE_MPU == 1 )
+	subs r1, r1, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	str r1, [r2]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mrs r3, control							/* r3 = CONTROL. */
+	mov r4, lr								/* r4 = LR/EXC_RETURN. */
+	stmia r1!, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+#else /* configENABLE_MPU */
+	subs r1, r1, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+	str r1, [r2]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmia r1!, {r0, r2-r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
+#endif /* configENABLE_MPU */
+	b select_next_task
+
+	save_ns_context:
+		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r2, [r3]						/* Read pxCurrentTCB. */
+	#if ( configENABLE_MPU == 1 )
+		subs r1, r1, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+		str r1, [r2]						/* Save the new top of stack in TCB. */
+		adds r1, r1, #16					/* r1 = r1 + 16. */
+		stmia r1!, {r4-r7}					/* Store the low registers that are not saved automatically. */
+		mov r4, r8							/* r4 = r8. */
+		mov r5, r9							/* r5 = r9. */
+		mov r6, r10							/* r6 = r10. */
+		mov r7, r11							/* r7 = r11. */
+		stmia r1!, {r4-r7}					/* Store the high registers that are not saved automatically. */
+		mrs r2, psplim						/* r2 = PSPLIM. */
+		mrs r3, control						/* r3 = CONTROL. */
+		mov r4, lr							/* r4 = LR/EXC_RETURN. */
+		subs r1, r1, #48					/* r1 = r1 - 48. */
+		stmia r1!, {r0, r2-r4}				/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	#else /* configENABLE_MPU */
+		subs r1, r1, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+		str r1, [r2]						/* Save the new top of stack in TCB. */
+		mrs r2, psplim						/* r2 = PSPLIM. */
+		mov r3, lr							/* r3 = LR/EXC_RETURN. */
+		stmia r1!, {r0, r2-r7}				/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
+		mov r4, r8							/* r4 = r8. */
+		mov r5, r9							/* r5 = r9. */
+		mov r6, r10							/* r6 = r10. */
+		mov r7, r11							/* r7 = r11. */
+		stmia r1!, {r4-r7}					/* Store the high registers that are not saved automatically. */
+	#endif /* configENABLE_MPU */
+
+	select_next_task:
+		cpsid i
+		bl vTaskSwitchContext
+		cpsie i
+
+		ldr r2, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r3, [r2]						/* Read pxCurrentTCB. */
+		ldr r1, [r3]						/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+
+	#if ( configENABLE_MPU == 1 )
+		dmb									/* Complete outstanding transfers before disabling MPU. */
+		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		movs r5, #1							/* r5 = 1. */
+		bics r4, r5							/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+		str r4, [r2]						/* Disable MPU. */
+
+		adds r3, #4							/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+		ldr r4, [r3]						/* r4 = *r3 i.e. r4 = MAIR0. */
+		ldr r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+		str r4, [r2]						/* Program MAIR0. */
+		ldr r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+		adds r3, #4							/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+		movs r5, #4							/* r5 = 4. */
+		str  r5, [r2]						/* Program RNR = 4. */
+		ldmia r3!, {r6,r7}					/* Read first set of RBAR/RLAR from TCB. */
+		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		stmia r4!, {r6,r7}					/* Write first set of RBAR/RLAR registers. */
+		movs r5, #5							/* r5 = 5. */
+		str  r5, [r2]						/* Program RNR = 5. */
+		ldmia r3!, {r6,r7}					/* Read second set of RBAR/RLAR from TCB. */
+		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		stmia r4!, {r6,r7}					/* Write second set of RBAR/RLAR registers. */
+		movs r5, #6							/* r5 = 6. */
+		str  r5, [r2]						/* Program RNR = 6. */
+		ldmia r3!, {r6,r7}					/* Read third set of RBAR/RLAR from TCB. */
+		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		stmia r4!, {r6,r7}					/* Write third set of RBAR/RLAR registers. */
+		movs r5, #7							/* r5 = 7. */
+		str  r5, [r2]						/* Program RNR = 7. */
+		ldmia r3!, {r6,r7}					/* Read fourth set of RBAR/RLAR from TCB. */
+		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		stmia r4!, {r6,r7}					/* Write fourth set of RBAR/RLAR registers. */
+
+		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		movs r5, #1							/* r5 = 1. */
+		orrs r4, r5							/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+		str r4, [r2]						/* Enable MPU. */
+		dsb									/* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+
+	#if ( configENABLE_MPU == 1 )
+		ldmia r1!, {r0, r2-r4}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		msr control, r3						/* Restore the CONTROL register value for the task. */
+		mov lr, r4							/* LR = r4. */
+		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r2]						/* Restore the task's xSecureContext. */
+		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
+		push {r1,r4}
+		bl SecureContext_LoadContext		/* Restore the secure context. */
+		pop {r1,r4}
+		mov lr, r4							/* LR = r4. */
+		lsls r2, r4, #25					/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+	#else /* configENABLE_MPU */
+		ldmia r1!, {r0, r2-r3}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		mov lr, r3							/* LR = r3. */
+		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r2]						/* Restore the task's xSecureContext. */
+		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
+		push {r1,r3}
+		bl SecureContext_LoadContext		/* Restore the secure context. */
+		pop {r1,r3}
+		mov lr, r3							/* LR = r3. */
+		lsls r2, r3, #25					/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+	#endif /* configENABLE_MPU */
+
+	restore_ns_context:
+		adds r1, r1, #16					/* Move to the high registers. */
+		ldmia r1!, {r4-r7}					/* Restore the high registers that are not automatically restored. */
+		mov r8, r4							/* r8 = r4. */
+		mov r9, r5							/* r9 = r5. */
+		mov r10, r6							/* r10 = r6. */
+		mov r11, r7							/* r11 = r7. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		subs r1, r1, #32					/* Go back to the low registers. */
+		ldmia r1!, {r4-r7}					/* Restore the low registers that are not automatically restored. */
+		bx lr
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+	movs r0, #4
+	mov r1, lr
+	tst r0, r1
+	beq stacking_used_msp
+	mrs r0, psp
+	b vPortSVCHandler_C
+	stacking_used_msp:
+		mrs r0, msp
+		b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+vPortFreeSecureContext:
+	ldr r1, [r0]							/* The first item in the TCB is the top of the stack. */
+	ldr r0, [r1]							/* The first item on the stack is the task's xSecureContext. */
+	cmp r0, #0								/* Raise svc if task's xSecureContext is not NULL. */
+	beq free_secure_context
+	bx lr									/* There is no secure context (xSecureContext is NULL). */
+	free_secure_context:
+		svc 1								/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
+		bx lr								/* Return. */
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h
new file mode 100644
index 0000000..969c563
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M23"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.c
new file mode 100644
index 0000000..8a42230
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.c
@@ -0,0 +1,204 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED		0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED		0x03
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first addess of the allocated memory.
+ */
+typedef struct SecureContext
+{
+	uint8_t *pucCurrentStackPointer;	/**< Current value of stack pointer (PSP). */
+	uint8_t *pucStackLimit;				/**< Last location of the stack memory (PSPLIM). */
+	uint8_t *pucStackStart;				/**< First location of the stack memory. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+	uint32_t ulIPSR;
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* No stack for thread mode until a task's context is loaded. */
+		secureportSET_PSPLIM( securecontextNO_STACK );
+		secureportSET_PSP( securecontextNO_STACK );
+
+		#if( configENABLE_MPU == 1 )
+		{
+			/* Configure thread mode to use PSP and to be unprivileged. */
+			secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+		}
+		#else /* configENABLE_MPU */
+		{
+			/* Configure thread mode to use PSP and to be privileged.. */
+			secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+		}
+		#endif /* configENABLE_MPU */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
+#else /* configENABLE_MPU */
+	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
+#endif /* configENABLE_MPU */
+{
+	uint8_t *pucStackMemory = NULL;
+	uint32_t ulIPSR;
+	SecureContextHandle_t xSecureContextHandle = NULL;
+	#if( configENABLE_MPU == 1 )
+		uint32_t *pulCurrentStackPointer = NULL;
+	#endif /* configENABLE_MPU */
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* Allocate the context structure. */
+		xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
+
+		if( xSecureContextHandle != NULL )
+		{
+			/* Allocate the stack space. */
+			pucStackMemory = pvPortMalloc( ulSecureStackSize );
+
+			if( pucStackMemory != NULL )
+			{
+				/* Since stack grows down, the starting point will be the last
+				 * location. Note that this location is next to the last
+				 * allocated byte because the hardware decrements the stack
+				 * pointer before writing i.e. if stack pointer is 0x2, a push
+				 * operation will decrement the stack pointer to 0x1 and then
+				 * write at 0x1. */
+				xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
+
+				/* The stack cannot go beyond this location. This value is
+				 * programmed in the PSPLIM register on context switch.*/
+				xSecureContextHandle->pucStackLimit = pucStackMemory;
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Store the correct CONTROL value for the task on the stack.
+					 * This value is programmed in the CONTROL register on
+					 * context switch. */
+					pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
+					pulCurrentStackPointer--;
+					if( ulIsTaskPrivileged )
+					{
+						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+					}
+					else
+					{
+						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+					}
+
+					/* Store the current stack pointer. This value is programmed in
+					 * the PSP register on context switch. */
+					xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+				}
+				#else /* configENABLE_MPU */
+				{
+					/* Current SP is set to the starting of the stack. This
+					 * value programmed in the PSP register on context switch. */
+					xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
+
+				}
+				#endif /* configENABLE_MPU */
+			}
+			else
+			{
+				/* Free the context to avoid memory leak and make sure to return
+				 * NULL to indicate failure. */
+				vPortFree( xSecureContextHandle );
+				xSecureContextHandle = NULL;
+			}
+		}
+	}
+
+	return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
+{
+	uint32_t ulIPSR;
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* Ensure that valid parameters are passed. */
+		secureportASSERT( xSecureContextHandle != NULL );
+
+		/* Free the stack space. */
+		vPortFree( xSecureContextHandle->pucStackLimit );
+
+		/* Free the context itself. */
+		vPortFree( xSecureContextHandle );
+	}
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.h
new file mode 100644
index 0000000..a98a7d0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.h
@@ -0,0 +1,111 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include 
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no task's context is loaded.
+ */
+#define securecontextNO_STACK	0x0
+
+/**
+ * @brief Opaque handle.
+ */
+struct SecureContext;
+typedef struct SecureContext*	SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if( configENABLE_MPU == 1 )
+	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
+#else /* configENABLE_MPU */
+	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port.c
new file mode 100644
index 0000000..6df620d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port.c
@@ -0,0 +1,48 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/* Functions implemented in assembler file. */
+extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );
+extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+	SecureContext_LoadContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+	SecureContext_SaveContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s
new file mode 100644
index 0000000..947e70a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s
@@ -0,0 +1,76 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+
+	PUBLIC SecureContext_LoadContextAsm
+	PUBLIC SecureContext_SaveContextAsm
+
+#if ( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+/*-----------------------------------------------------------*/
+
+SecureContext_LoadContextAsm:
+	/* xSecureContextHandle value is in r0. */
+	mrs r1, ipsr							/* r1 = IPSR. */
+	cbz r1, load_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
+	ldmia r0!, {r1, r2}						/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+#if ( configENABLE_MPU == 1 )
+	ldmia r1!, {r3}							/* Read CONTROL register value from task's stack. r3 = CONTROL. */
+	msr control, r3							/* CONTROL = r3. */
+#endif /* configENABLE_MPU */
+	msr psplim, r2							/* PSPLIM = r2. */
+	msr psp, r1								/* PSP = r1. */
+
+	load_ctx_therad_mode:
+		bx lr
+/*-----------------------------------------------------------*/
+
+SecureContext_SaveContextAsm:
+	/* xSecureContextHandle value is in r0. */
+	mrs r1, ipsr							/* r1 = IPSR. */
+	cbz r1, save_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
+	mrs r1, psp								/* r1 = PSP. */
+#if ( configENABLE_MPU == 1 )
+	mrs r2, control							/* r2 = CONTROL. */
+	subs r1, r1, #4							/* Make space for the CONTROL value on the stack. */
+	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+	stmia r1!, {r2}							/* Store CONTROL value on the stack. */
+#else /* configENABLE_MPU */
+	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+#endif /* configENABLE_MPU */
+	movs r1, #0								/* r1 = securecontextNO_STACK. */
+	msr psplim, r1							/* PSPLIM = securecontextNO_STACK. */
+	msr psp, r1								/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+
+	save_ctx_therad_mode:
+		bx lr
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.c
new file mode 100644
index 0000000..c4f613f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.c
@@ -0,0 +1,450 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#define secureconfigTOTAL_HEAP_SIZE		( ( ( size_t ) ( 10 * 1024 ) ) )
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+	#define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+	#define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+	#define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE			( ( size_t ) 8 )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+	/* The application writer has already defined the array used for the RTOS
+	 * heap - probably so it can be placed in a special segment or address. */
+	extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+	static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/**< The next free block in the list. */
+	size_t xBlockSize;						/**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/**
+ * @brief Gets set to the top bit of an size_t type.
+ *
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set
+ * then the block belongs to the application. When the bit is free the block is
+ * still part of the free heap space.
+ */
+static size_t xBlockAllocatedBit = 0;
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	uxAddress = ( size_t ) ucHeap;
+
+	if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+	{
+		uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+		uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+	}
+
+	pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	 * blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+	xStart.xBlockSize = ( size_t ) 0;
+
+	/* pxEnd is used to mark the end of the list of free blocks and is inserted
+	 * at the end of the heap space. */
+	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+	uxAddress -= xHeapStructSize;
+	uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+	pxEnd = ( void * ) uxAddress;
+	pxEnd->xBlockSize = 0;
+	pxEnd->pxNextFreeBlock = NULL;
+
+	/* To start with there is a single free block that is sized to take up the
+	 * entire heap space, minus the space taken by pxEnd. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+	/* Only one block exists - and it covers the entire usable heap space. */
+	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	 * than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+	{
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	 * make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+		pxBlockToInsert = pxIterator;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	 * make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+	}
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	 * before and the block after, then it's pxNextFreeBlock pointer will have
+	 * already been set, and should not be set here as that would make it point
+	 * to itself. */
+	if( pxIterator != pxBlockToInsert )
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+	/* If this is the first call to malloc then the heap will require
+	 * initialisation to setup the list of free blocks. */
+	if( pxEnd == NULL )
+	{
+		prvHeapInit();
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Check the requested block size is not so large that the top bit is set.
+	 * The top bit of the block size member of the BlockLink_t structure is used
+	 * to determine who owns the block - the application or the kernel, so it
+	 * must be free. */
+	if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+	{
+		/* The wanted size is increased so it can contain a BlockLink_t
+		 * structure in addition to the requested amount of bytes. */
+		if( xWantedSize > 0 )
+		{
+			xWantedSize += xHeapStructSize;
+
+			/* Ensure that blocks are always aligned to the required number of
+			 * bytes. */
+			if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+			{
+				/* Byte alignment required. */
+				xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+				secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+		{
+			/* Traverse the list from the start (lowest address) block until
+			 * one of adequate size is found. */
+			pxPreviousBlock = &xStart;
+			pxBlock = xStart.pxNextFreeBlock;
+			while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+			{
+				pxPreviousBlock = pxBlock;
+				pxBlock = pxBlock->pxNextFreeBlock;
+			}
+
+			/* If the end marker was reached then a block of adequate size was
+			 * not found. */
+			if( pxBlock != pxEnd )
+			{
+				/* Return the memory space pointed to - jumping over the
+				 * BlockLink_t structure at its start. */
+				pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+				/* This block is being returned for use so must be taken out
+				 * of the list of free blocks. */
+				pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+				/* If the block is larger than required it can be split into
+				 * two. */
+				if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+				{
+					/* This block is to be split into two.  Create a new
+					 * block following the number of bytes requested. The void
+					 * cast is used to prevent byte alignment warnings from the
+					 * compiler. */
+					pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+					secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+					/* Calculate the sizes of two blocks split from the single
+					 * block. */
+					pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+					pxBlock->xBlockSize = xWantedSize;
+
+					/* Insert the new block into the list of free blocks. */
+					prvInsertBlockIntoFreeList( pxNewBlockLink );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+				if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+				{
+					xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* The block is being returned - it is allocated and owned by
+				 * the application and has no "next" block. */
+				pxBlock->xBlockSize |= xBlockAllocatedBit;
+				pxBlock->pxNextFreeBlock = NULL;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceMALLOC( pvReturn, xWantedSize );
+
+	#if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		 * before it. */
+		puc -= xHeapStructSize;
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+
+		/* Check the block is actually allocated. */
+		secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+		secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+			{
+				/* The block is being returned to the heap - it is no longer
+				 * allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+				secureportDISABLE_NON_SECURE_INTERRUPTS();
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+				}
+				secureportENABLE_NON_SECURE_INTERRUPTS();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+	return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.h
new file mode 100644
index 0000000..aae5cfc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.h
@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include 
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void *pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void *pv );
+
+#endif /* __SECURE_HEAP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.c
new file mode 100644
index 0000000..60ef1e8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.c
@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR					( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS		( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK	( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS		( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK		( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR						( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS			( 29UL )
+#define secureinitFPCCR_LSPENS_MASK			( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS				( 26UL )
+#define secureinitFPCCR_TS_MASK				( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR						( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS			( 10UL )
+#define secureinitNSACR_CP10_MASK			( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS			( 11UL )
+#define secureinitNSACR_CP11_MASK			( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+	uint32_t ulIPSR;
+
+	 /* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		*( secureinitSCB_AIRCR ) =	( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+									( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+									( ( 0x1UL	<< secureinitSCB_AIRCR_PRIS_POS )	& secureinitSCB_AIRCR_PRIS_MASK );
+	}
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+	uint32_t ulIPSR;
+
+	 /* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+		 * permitted. CP11 should be programmed to the same value as CP10. */
+		*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+		/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+		 * that we can enable/disable lazy stacking in port.c file. */
+		*( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
+
+		/* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+		 * registers (S16-S31) are also pushed to stack on exception entry and
+		 * restored on exception return. */
+		*( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+	}
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.h
new file mode 100644
index 0000000..3954e13
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.h
@@ -0,0 +1,53 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h
new file mode 100644
index 0000000..f392537
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT					8
+#define secureportBYTE_ALIGNMENT_MASK				( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+	#define secureportNON_SECURE_CALLABLE			__cmse_nonsecure_entry __root
+#else
+	#define secureportNON_SECURE_CALLABLE			__attribute__((cmse_nonsecure_entry)) __attribute__((used))
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+	__asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+	__asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+	__asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+	__asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+	__asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+	__asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+	__asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+	__asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL		0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL	1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS()		secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x )						\
+	if( ( x ) == 0 )								\
+	{												\
+		secureportDISABLE_SECURE_INTERRUPTS();		\
+		secureportDISABLE_NON_SECURE_INTERRUPTS();	\
+		for( ;; );									\
+	}
+
+#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
new file mode 100644
index 0000000..b0394fb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/* Secure components includes. */
+	#include "secure_context.h"
+	#include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK				( 0x00000004 )
+#define portNVIC_SYSTICK_INT				( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
+#define portNVIC_PENDSVSET					( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY			( 255UL )
+#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE				( 3UL )
+#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS					( 20UL )
+#define portCPACR_CP11_POS					( 22UL )
+
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS					( 31UL )
+#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS					( 30UL )
+#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS				( 0UL )
+#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS				( 8UL )
+#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS				( 16UL )
+#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS				( 24UL )
+#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS				( 0UL )
+#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS				( 8UL )
+#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS				( 16UL )
+#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS				( 24UL )
+#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE			( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE						( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR					( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         FD
+	 * 1111 1111  1111 1111  1111 1111  1111 1101
+	 *
+	 * Bit[6] - 1 --> The exception was taken from the Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 1 --> The exception was taken to the Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
+#else
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         BC
+	 * 1111 1111  1111 1111  1111 1111  1011 1100
+	 *
+	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS			prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS				1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT				0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Setup the Memory Protection Unit (MPU).
+	 */
+	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+	/**
+	 * @brief Setup the Floating Point Unit (FPU).
+	 */
+	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Saved as part of the task context to indicate which context the
+	 * task is using on the secure side.
+	 */
+	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Stop and reset the SysTick. */
+	*( portNVIC_SYSTICK_CTRL ) = 0UL;
+	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+	/* A function that implements a task must not exit or attempt to return to
+	 * its caller as there is nothing to return to. If a task wants to exit it
+	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
+	 * to be triggered if configASSERT() is defined, then stop here so
+	 * application writers can catch the error. */
+	configASSERT( ulCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		 * started to remove a compiler warning about the function being
+		 * defined but never called.  ulDummy is used purely to quieten other
+		 * warnings about code appearing after this function is called - making
+		 * ulDummy volatile makes the compiler think the function could return
+		 * and therefore not output an 'unreachable code' warning for code that
+		 * appears after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __privileged_functions_start__;
+		extern uint32_t * __privileged_functions_end__;
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+		extern uint32_t * __unprivileged_flash_start__;
+		extern uint32_t * __unprivileged_flash_end__;
+		extern uint32_t * __privileged_sram_start__;
+		extern uint32_t * __privileged_sram_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __privileged_functions_start__[];
+		extern uint32_t __privileged_functions_end__[];
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+		extern uint32_t __unprivileged_flash_start__[];
+		extern uint32_t __unprivileged_flash_end__[];
+		extern uint32_t __privileged_sram_start__[];
+		extern uint32_t __privileged_sram_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+
+		/* Check that the MPU is present. */
+		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+		{
+			/* MAIR0 - Index 0. */
+			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+			/* MAIR0 - Index 1. */
+			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+			/* Setup privileged flash as Read Only so that privileged tasks can
+			 * read it but not modify. */
+			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged flash as Read Only by both privileged and
+			 * unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged syscalls flash as Read Only by both privileged
+			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup RAM containing kernel data for privileged access only. */
+			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+								( portMPU_REGION_EXECUTE_NEVER );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Enable mem fault. */
+			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+			/* Enable MPU with privileged background access i.e. unmapped
+			 * regions have privileged access. */
+			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			/* Enable non-secure access to the FPU. */
+			SecureInit_EnableNSFPUAccess();
+		}
+		#endif /* configENABLE_TRUSTZONE */
+
+		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+		 * unprivileged code should be able to access FPU. CP11 should be
+		 * programmed to the same value as CP10. */
+		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+							);
+
+		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
+		 * context on exception entry and restore on exception return.
+		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
+		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+	}
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Set a PendSV to request a context switch. */
+	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	portDISABLE_INTERRUPTS();
+	ulCriticalNesting++;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	configASSERT( ulCriticalNesting );
+	ulCriticalNesting--;
+
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	uint32_t ulR0;
+	#if( configENABLE_MPU == 1 )
+		uint32_t ulControl, ulIsTaskPrivileged;
+	#endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
+	 * R12, LR, PC, xPSR. */
+	ulPC = pulCallerStackAddress[ 6 ];
+	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+	switch( ucSVCNumber )
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+			case portSVC_ALLOCATE_SECURE_CONTEXT:
+			{
+				/* R0 contains the stack size passed as parameter to the
+				 * vPortAllocateSecureContext function. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Read the CONTROL register value. */
+					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+					/* The task that raised the SVC is privileged if Bit[0]
+					 * in the CONTROL register is 0. */
+					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+				}
+				#else
+				{
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0 );
+				}
+				#endif /* configENABLE_MPU */
+
+				configASSERT( xSecureContext != NULL );
+				SecureContext_LoadContext( xSecureContext );
+			}
+			break;
+
+			case portSVC_FREE_SECURE_CONTEXT:
+			{
+				/* R0 contains the secure context handle to be freed. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				/* Free the secure context. */
+				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+			}
+			break;
+		#endif /* configENABLE_TRUSTZONE */
+
+		case portSVC_START_SCHEDULER:
+		{
+			#if( configENABLE_TRUSTZONE == 1 )
+			{
+				/* De-prioritize the non-secure exceptions so that the
+				 * non-secure pendSV runs at the lowest priority. */
+				SecureInit_DePrioritizeNSExceptions();
+
+				/* Initialize the secure context management system. */
+				SecureContext_Init();
+			}
+			#endif /* configENABLE_TRUSTZONE */
+
+			#if( configENABLE_FPU == 1 )
+			{
+				/* Setup the Floating Point Unit (FPU). */
+				prvSetupFPU();
+			}
+			#endif /* configENABLE_FPU */
+
+			/* Setup the context of the first task so that the first task starts
+			 * executing. */
+			vRestoreContextOfFirstTask();
+		}
+		break;
+
+		#if( configENABLE_MPU == 1 )
+			case portSVC_RAISE_PRIVILEGE:
+			{
+				/* Only raise the privilege, if the svc was raised from any of
+				 * the system calls. */
+				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+				{
+					vRaisePrivilege();
+				}
+			}
+			break;
+		#endif /* configENABLE_MPU */
+
+		default:
+		{
+			/* Incorrect SVC call. */
+			configASSERT( pdFALSE );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	 * interrupt. */
+	#if( portPRELOAD_REGISTERS == 0 )
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
+		*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#else /* portPRELOAD_REGISTERS */
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
+		pxTopOfStack--;
+		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#endif /* portPRELOAD_REGISTERS */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+	#if( configENABLE_MPU == 1 )
+	{
+		/* Setup the Memory Protection Unit (MPU). */
+		prvSetupMPU();
+	}
+	#endif /* configENABLE_MPU */
+
+	/* Start the timer that generates the tick ISR. Interrupts are disabled
+	 * here already. */
+	prvSetupTimerInterrupt();
+
+	/* Initialize the critical nesting count ready for the first task. */
+	ulCriticalNesting = 0;
+
+	/* Start the first task. */
+	vStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing. Call the task
+	 * exit error function to prevent compiler warnings about a static function
+	 * not being called in the case that the application writer overrides this
+	 * functionality by defining configTASK_RETURN_ADDRESS. Call
+	 * vTaskSwitchContext() so link time optimization does not remove the
+	 * symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Not implemented in ports where there is nothing to return to.
+	 * Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+	{
+	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+	int32_t lIndex = 0;
+
+		/* Setup MAIR0. */
+		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+		/* This function is called automatically when the task is created - in
+		 * which case the stack region parameters will be valid.  At all other
+		 * times the stack parameters will not be valid and it is assumed that
+		 * the stack region has already been configured. */
+		if( ulStackDepth > 0 )
+		{
+			/* Define the region that allows access to the stack. */
+			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
+															( portMPU_REGION_NON_SHAREABLE ) |
+															( portMPU_REGION_READ_WRITE ) |
+															( portMPU_REGION_EXECUTE_NEVER );
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
+															( portMPU_RLAR_ATTR_INDEX0 ) |
+															( portMPU_RLAR_REGION_ENABLE );
+		}
+
+		/* User supplied configurable regions. */
+		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+		{
+			/* If xRegions is NULL i.e. the task has not specified any MPU
+			 * region, the else part ensures that all the configurable MPU
+			 * regions are invalidated. */
+			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+			{
+				/* Translate the generic region definition contained in xRegions
+				 * into the ARMv8 specific MPU settings that are then stored in
+				 * xMPUSettings. */
+				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+				/* Start address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
+																			( portMPU_REGION_NON_SHAREABLE );
+
+				/* RO/RW. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+				}
+				else
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+				}
+
+				/* XN. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+				}
+
+				/* End Address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
+																			( portMPU_RLAR_REGION_ENABLE );
+
+				/* Normal memory/ Device memory. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+				{
+					/* Attr1 in MAIR0 is configured as device memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+				}
+				else
+				{
+					/* Attr1 in MAIR0 is configured as normal memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+				}
+			}
+			else
+			{
+				/* Invalidate the region. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+			}
+
+			lIndex++;
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
new file mode 100644
index 0000000..6314e96
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
new file mode 100644
index 0000000..b84c356
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
@@ -0,0 +1,303 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	EXTERN pxCurrentTCB
+	EXTERN vTaskSwitchContext
+	EXTERN vPortSVCHandler_C
+
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
+	PUBLIC vRestoreContextOfFirstTask
+	PUBLIC vRaisePrivilege
+	PUBLIC vStartFirstTask
+	PUBLIC ulSetInterruptMaskFromISR
+	PUBLIC vClearInterruptMaskFromISR
+	PUBLIC PendSV_Handler
+	PUBLIC SVC_Handler
+
+#if ( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+	mrs r0, control							/* r0 = CONTROL. */
+	movs r1, #1								/* r1 = 1. */
+	tst r0, r1								/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+	beq running_privileged					/* If the result of previous AND operation was 0, branch. */
+	movs r0, #0								/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	bx lr									/* Return. */
+	running_privileged:
+		movs r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+		bx lr								/* Return. */
+
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+	mrs r0, control							/* r0 = CONTROL. */
+	movs r1, #1								/* r1 = 1. */
+	orrs r0, r1								/* r0 = r0 | r1. */
+	msr control, r0							/* CONTROL = r0. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION privileged_functions:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr  r1, [r2]							/* Read pxCurrentTCB. */
+	ldr  r0, [r1]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
+	movs r4, #1								/* r4 = 1. */
+	bics r3, r4								/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+	str r3, [r2]							/* Disable MPU. */
+
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	ldr  r4, [r1]							/* r4 = *r1 i.e. r4 = MAIR0. */
+	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str  r4, [r2]							/* Program MAIR0. */
+	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	movs r4, #4								/* r4 = 4. */
+	str  r4, [r2]							/* Program RNR = 4. */
+	ldmia r1!, {r5,r6}						/* Read first set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write first set of RBAR/RLAR registers. */
+	movs r4, #5								/* r4 = 5. */
+	str  r4, [r2]							/* Program RNR = 5. */
+	ldmia r1!, {r5,r6}						/* Read second set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write second set of RBAR/RLAR registers. */
+	movs r4, #6								/* r4 = 6. */
+	str  r4, [r2]							/* Program RNR = 6. */
+	ldmia r1!, {r5,r6}						/* Read third set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write third set of RBAR/RLAR registers. */
+	movs r4, #7								/* r4 = 7. */
+	str  r4, [r2]							/* Program RNR = 7. */
+	ldmia r1!, {r5,r6}						/* Read fourth set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write fourth set of RBAR/RLAR registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
+	movs r4, #1								/* r4 = 1. */
+	orrs r3, r4								/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+	str r3, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldm  r0!, {r1-r3}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+	msr  psplim, r1							/* Set this task's PSPLIM value. */
+	msr  control, r2						/* Set this task's CONTROL value. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r3									/* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+	ldm  r0!, {r1-r2}						/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+	msr  psplim, r1							/* Set this task's PSPLIM value. */
+	movs r1, #2								/* r1 = 2. */
+	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r2									/* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+	mrs  r0, control						/* Read the CONTROL register. */
+	movs r1, #1								/* r1 = 1. */
+	bics r0, r1								/* Clear the bit 0. */
+	msr  control, r0						/* Write back the new CONTROL value. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
+	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
+	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
+	msr msp, r0								/* Set the MSP back to the start of the stack. */
+	cpsie i									/* Globally enable interrupts. */
+	dsb
+	isb
+	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+	nop
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMaskFromISR:
+	mrs r0, PRIMASK
+	cpsid i
+	bx lr
+/*-----------------------------------------------------------*/
+
+vClearInterruptMaskFromISR:
+	msr PRIMASK, r0
+	bx lr
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+	mrs r0, psp								/* Read PSP in r0. */
+	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r1, [r2]							/* Read pxCurrentTCB. */
+#if ( configENABLE_MPU == 1 )
+	subs r0, r0, #44						/* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+	str r0, [r1]							/* Save the new top of stack in TCB. */
+	mrs r1, psplim							/* r1 = PSPLIM. */
+	mrs r2, control							/* r2 = CONTROL. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmia r0!, {r1-r7}						/* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */
+	mov r4, r8								/* r4 = r8. */
+	mov r5, r9								/* r5 = r9. */
+	mov r6, r10								/* r6 = r10. */
+	mov r7, r11								/* r7 = r11. */
+	stmia r0!, {r4-r7}						/* Store the high registers that are not saved automatically. */
+#else /* configENABLE_MPU */
+	subs r0, r0, #40						/* Make space for PSPLIM, LR and the remaining registers on the stack. */
+	str r0, [r1]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmia r0!, {r2-r7}						/* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
+	mov r4, r8								/* r4 = r8. */
+	mov r5, r9								/* r5 = r9. */
+	mov r6, r10								/* r6 = r10. */
+	mov r7, r11								/* r7 = r11. */
+	stmia r0!, {r4-r7}						/* Store the high registers that are not saved automatically. */
+#endif /* configENABLE_MPU */
+
+	cpsid i
+	bl vTaskSwitchContext
+	cpsie i
+
+	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r1, [r2]							/* Read pxCurrentTCB. */
+	ldr r0, [r1]							/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
+	movs r4, #1								/* r4 = 1. */
+	bics r3, r4								/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+	str r3, [r2]							/* Disable MPU. */
+
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	ldr  r4, [r1]							/* r4 = *r1 i.e. r4 = MAIR0. */
+	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str  r4, [r2]							/* Program MAIR0. */
+	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	movs r4, #4								/* r4 = 4. */
+	str  r4, [r2]							/* Program RNR = 4. */
+	ldmia r1!, {r5,r6}						/* Read first set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write first set of RBAR/RLAR registers. */
+	movs r4, #5								/* r4 = 5. */
+	str  r4, [r2]							/* Program RNR = 5. */
+	ldmia r1!, {r5,r6}						/* Read second set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write second set of RBAR/RLAR registers. */
+	movs r4, #6								/* r4 = 6. */
+	str  r4, [r2]							/* Program RNR = 6. */
+	ldmia r1!, {r5,r6}						/* Read third set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write third set of RBAR/RLAR registers. */
+	movs r4, #7								/* r4 = 7. */
+	str  r4, [r2]							/* Program RNR = 7. */
+	ldmia r1!, {r5,r6}						/* Read fourth set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write fourth set of RBAR/RLAR registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
+	movs r4, #1								/* r4 = 1. */
+	orrs r3, r4								/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+	str r3, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	adds r0, r0, #28						/* Move to the high registers. */
+	ldmia r0!, {r4-r7}						/* Restore the high registers that are not automatically restored. */
+	mov r8, r4								/* r8 = r4. */
+	mov r9, r5								/* r9 = r5. */
+	mov r10, r6								/* r10 = r6. */
+	mov r11, r7								/* r11 = r7. */
+	msr psp, r0								/* Remember the new top of stack for the task. */
+	subs r0, r0, #44						/* Move to the starting of the saved context. */
+	ldmia r0!, {r1-r7}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */
+	msr psplim, r1							/* Restore the PSPLIM register value for the task. */
+	msr control, r2							/* Restore the CONTROL register value for the task. */
+	bx r3
+#else /* configENABLE_MPU */
+	adds r0, r0, #24						/* Move to the high registers. */
+	ldmia r0!, {r4-r7}						/* Restore the high registers that are not automatically restored. */
+	mov r8, r4								/* r8 = r4. */
+	mov r9, r5								/* r9 = r5. */
+	mov r10, r6								/* r10 = r6. */
+	mov r11, r7								/* r11 = r7. */
+	msr psp, r0								/* Remember the new top of stack for the task. */
+	subs r0, r0, #40						/* Move to the starting of the saved context. */
+	ldmia r0!, {r2-r7}						/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
+	msr psplim, r2							/* Restore the PSPLIM register value for the task. */
+	bx r3
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+	movs r0, #4
+	mov r1, lr
+	tst r0, r1
+	beq stacking_used_msp
+	mrs r0, psp
+	b vPortSVCHandler_C
+	stacking_used_msp:
+		mrs r0, msp
+		b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
new file mode 100644
index 0000000..969c563
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M23"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM3/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM3/port.c
new file mode 100644
index 0000000..33303c3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM3/port.c
@@ -0,0 +1,619 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM3 port.
+ *----------------------------------------------------------*/
+
+/* IAR includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
+	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK					( 0xFFUL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR					( 0x01000000 )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR			( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
+
+/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
+defined.  The value 255 should also ensure backward compatibility.
+FreeRTOS.org versions prior to V4.3.0 did not include this definition. */
+#ifndef configKERNEL_INTERRUPT_PRIORITY
+	#define configKERNEL_INTERRUPT_PRIORITY 255
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortSysTickHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+extern void vPortStartFirstTask( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* LR */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Start the first task. */
+	vPortStartFirstTask();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
+	executes all interrupts must be unmasked.  There is therefore no need to
+	save and then restore the interrupt mask value as its value is already
+	known. */
+	portDISABLE_INTERRUPTS();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE == 1 )
+
+	__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+	TickType_t xModifiableIdleTime;
+
+		/* Make sure the SysTick reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
+		is accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+		/* Calculate the reload value required to wait xExpectedIdleTime
+		tick periods.  -1 is used because this code will execute part way
+		through one of the tick periods. */
+		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+		if( ulReloadValue > ulStoppedTimerCompensation )
+		{
+			ulReloadValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Enter a critical section but don't use the taskENTER_CRITICAL()
+		method as that will mask interrupts that should exit sleep mode. */
+		__disable_interrupt();
+		__DSB();
+		__ISB();
+
+		/* If a context switch is pending or a task is waiting for the scheduler
+		to be unsuspended then abandon the low power entry. */
+		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+		{
+			/* Restart from whatever is left in the count register to complete
+			this tick period. */
+			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Reset the reload register to the value required for normal tick
+			periods. */
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Re-enable interrupts - see comments above __disable_interrupt()
+			call above. */
+			__enable_interrupt();
+		}
+		else
+		{
+			/* Set the new reload value. */
+			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+			/* Clear the SysTick count flag and set the count value back to
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+			set its parameter to 0 to indicate that its implementation contains
+			its own wait for interrupt or wait for event instruction, and so wfi
+			should not be executed again.  However, the original expected idle
+			time variable must remain unmodified, so a copy is taken. */
+			xModifiableIdleTime = xExpectedIdleTime;
+			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+			if( xModifiableIdleTime > 0 )
+			{
+				__DSB();
+				__WFI();
+				__ISB();
+			}
+			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+			/* Re-enable interrupts to allow the interrupt that brought the MCU
+			out of sleep mode to execute immediately.  see comments above
+			__disable_interrupt() call above. */
+			__enable_interrupt();
+			__DSB();
+			__ISB();
+
+			/* Disable interrupts again because the clock is about to be stopped
+			and interrupts that execute while the clock is stopped will increase
+			any slippage between the time maintained by the RTOS and calendar
+			time. */
+			__disable_interrupt();
+			__DSB();
+			__ISB();
+			
+			/* Disable the SysTick clock without reading the 
+			portNVIC_SYSTICK_CTRL_REG register to ensure the
+			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again, 
+			the time the SysTick is stopped for is accounted for as best it can 
+			be, but using the tickless mode will inevitably result in some tiny 
+			drift of the time maintained by the kernel with respect to calendar 
+			time*/
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+			/* Determine if the SysTick clock has already counted to zero and
+			been set back to the current reload value (the reload back being
+			correct for the entire expected idle time) or if the SysTick is yet
+			to count to zero (in which case an interrupt other than the SysTick
+			must have brought the system out of sleep mode). */
+			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			{
+				uint32_t ulCalculatedLoadValue;
+
+				/* The tick interrupt is already pending, and the SysTick count
+				reloaded with ulReloadValue.  Reset the
+				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+				period. */
+				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+				/* Don't allow a tiny value, or values that have somehow
+				underflowed because the post sleep hook did something
+				that took too long. */
+				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+				{
+					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+				}
+
+				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+				/* As the pending tick will be processed as soon as this
+				function exits, the tick value maintained by the tick is stepped
+				forward by one less than the time spent waiting. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				Work out how long the sleep lasted rounded to complete tick
+				periods (not the ulReload value which accounted for part
+				ticks). */
+				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+				/* How many complete tick periods passed while the processor
+				was waiting? */
+				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+				/* The reload value is set to whatever fraction of a single tick
+				period remains. */
+				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+			}
+
+			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+			value. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+			vTaskStepTick( ulCompleteTickPeriods );
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Exit with interrpts enabled. */
+			__enable_interrupt();
+		}
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__weak void vPortSetupTimerInterrupt( void )
+{
+	/* Calculate the constants required to configure the tick interrupt. */
+	#if( configUSE_TICKLESS_IDLE == 1 )
+	{
+		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+	}
+	#endif /* configUSE_TICKLESS_IDLE */
+
+	/* Stop and clear the SysTick. */
+	portNVIC_SYSTICK_CTRL_REG = 0UL;
+	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredictable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM3/portasm.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM3/portasm.s
new file mode 100644
index 0000000..f91e1a6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM3/portasm.s
@@ -0,0 +1,103 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include 
+
+	RSEG    CODE:CODE(2)
+	thumb
+
+	EXTERN pxCurrentTCB
+	EXTERN vTaskSwitchContext
+
+	PUBLIC xPortPendSVHandler
+	PUBLIC vPortSVCHandler
+	PUBLIC vPortStartFirstTask
+
+
+
+/*-----------------------------------------------------------*/
+
+xPortPendSVHandler:
+	mrs r0, psp
+	isb
+	ldr	r3, =pxCurrentTCB			/* Get the location of the current TCB. */
+	ldr	r2, [r3]
+
+	stmdb r0!, {r4-r11}				/* Save the remaining registers. */
+	str r0, [r2]					/* Save the new top of stack into the first member of the TCB. */
+
+	stmdb sp!, {r3, r14}
+	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+	msr basepri, r0
+	dsb
+	isb
+	bl vTaskSwitchContext
+	mov r0, #0
+	msr basepri, r0
+	ldmia sp!, {r3, r14}
+
+	ldr r1, [r3]
+	ldr r0, [r1]					/* The first item in pxCurrentTCB is the task top of stack. */
+	ldmia r0!, {r4-r11}				/* Pop the registers. */
+	msr psp, r0
+	isb
+	bx r14
+
+
+/*-----------------------------------------------------------*/
+
+vPortSVCHandler:
+	/* Get the location of the current TCB. */
+	ldr	r3, =pxCurrentTCB
+	ldr r1, [r3]
+	ldr r0, [r1]
+	/* Pop the core registers. */
+	ldmia r0!, {r4-r11}
+	msr psp, r0
+	isb
+	mov r0, #0
+	msr	basepri, r0
+	orr r14, r14, #13
+	bx r14
+
+/*-----------------------------------------------------------*/
+
+vPortStartFirstTask
+	/* Use the NVIC offset register to locate the stack. */
+	ldr r0, =0xE000ED08
+	ldr r0, [r0]
+	ldr r0, [r0]
+	/* Set the msp back to the start of the stack. */
+	msr msp, r0
+	/* Call SVC to start the first task, ensuring interrupts are enabled. */
+	cpsie i
+	cpsie f
+	dsb
+	isb
+	svc 0
+
+	END
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h
new file mode 100644
index 0000000..e508089
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h
@@ -0,0 +1,180 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* IAR includes. */
+#include 
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+/* Compiler directives. */
+#define portWEAK_SYMBOL				__attribute__( ( weak ) )
+
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+#define portYIELD()											\
+{															\
+	/* Set a PendSV to request a context switch. */			\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;			\
+	__DSB();												\
+	__ISB();												\
+}
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()							\
+{															\
+	__set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY );	\
+	__DSB();												\
+	__ISB();												\
+}
+
+#define portENABLE_INTERRUPTS()					__set_BASEPRI( 0 )
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()		__get_BASEPRI(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	__set_BASEPRI( x )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+the source code because to do so would cause other compilers to generate
+warnings. */
+#pragma diag_suppress=Pe191
+#pragma diag_suppress=Pa082
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/port.c
new file mode 100644
index 0000000..b0394fb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/* Secure components includes. */
+	#include "secure_context.h"
+	#include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK				( 0x00000004 )
+#define portNVIC_SYSTICK_INT				( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
+#define portNVIC_PENDSVSET					( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY			( 255UL )
+#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE				( 3UL )
+#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS					( 20UL )
+#define portCPACR_CP11_POS					( 22UL )
+
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS					( 31UL )
+#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS					( 30UL )
+#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS				( 0UL )
+#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS				( 8UL )
+#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS				( 16UL )
+#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS				( 24UL )
+#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS				( 0UL )
+#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS				( 8UL )
+#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS				( 16UL )
+#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS				( 24UL )
+#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE			( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE						( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR					( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         FD
+	 * 1111 1111  1111 1111  1111 1111  1111 1101
+	 *
+	 * Bit[6] - 1 --> The exception was taken from the Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 1 --> The exception was taken to the Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
+#else
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         BC
+	 * 1111 1111  1111 1111  1111 1111  1011 1100
+	 *
+	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS			prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS				1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT				0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Setup the Memory Protection Unit (MPU).
+	 */
+	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+	/**
+	 * @brief Setup the Floating Point Unit (FPU).
+	 */
+	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Saved as part of the task context to indicate which context the
+	 * task is using on the secure side.
+	 */
+	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Stop and reset the SysTick. */
+	*( portNVIC_SYSTICK_CTRL ) = 0UL;
+	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+	/* A function that implements a task must not exit or attempt to return to
+	 * its caller as there is nothing to return to. If a task wants to exit it
+	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
+	 * to be triggered if configASSERT() is defined, then stop here so
+	 * application writers can catch the error. */
+	configASSERT( ulCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		 * started to remove a compiler warning about the function being
+		 * defined but never called.  ulDummy is used purely to quieten other
+		 * warnings about code appearing after this function is called - making
+		 * ulDummy volatile makes the compiler think the function could return
+		 * and therefore not output an 'unreachable code' warning for code that
+		 * appears after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __privileged_functions_start__;
+		extern uint32_t * __privileged_functions_end__;
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+		extern uint32_t * __unprivileged_flash_start__;
+		extern uint32_t * __unprivileged_flash_end__;
+		extern uint32_t * __privileged_sram_start__;
+		extern uint32_t * __privileged_sram_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __privileged_functions_start__[];
+		extern uint32_t __privileged_functions_end__[];
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+		extern uint32_t __unprivileged_flash_start__[];
+		extern uint32_t __unprivileged_flash_end__[];
+		extern uint32_t __privileged_sram_start__[];
+		extern uint32_t __privileged_sram_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+
+		/* Check that the MPU is present. */
+		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+		{
+			/* MAIR0 - Index 0. */
+			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+			/* MAIR0 - Index 1. */
+			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+			/* Setup privileged flash as Read Only so that privileged tasks can
+			 * read it but not modify. */
+			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged flash as Read Only by both privileged and
+			 * unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged syscalls flash as Read Only by both privileged
+			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup RAM containing kernel data for privileged access only. */
+			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+								( portMPU_REGION_EXECUTE_NEVER );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Enable mem fault. */
+			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+			/* Enable MPU with privileged background access i.e. unmapped
+			 * regions have privileged access. */
+			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			/* Enable non-secure access to the FPU. */
+			SecureInit_EnableNSFPUAccess();
+		}
+		#endif /* configENABLE_TRUSTZONE */
+
+		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+		 * unprivileged code should be able to access FPU. CP11 should be
+		 * programmed to the same value as CP10. */
+		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+							);
+
+		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
+		 * context on exception entry and restore on exception return.
+		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
+		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+	}
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Set a PendSV to request a context switch. */
+	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	portDISABLE_INTERRUPTS();
+	ulCriticalNesting++;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	configASSERT( ulCriticalNesting );
+	ulCriticalNesting--;
+
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	uint32_t ulR0;
+	#if( configENABLE_MPU == 1 )
+		uint32_t ulControl, ulIsTaskPrivileged;
+	#endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
+	 * R12, LR, PC, xPSR. */
+	ulPC = pulCallerStackAddress[ 6 ];
+	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+	switch( ucSVCNumber )
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+			case portSVC_ALLOCATE_SECURE_CONTEXT:
+			{
+				/* R0 contains the stack size passed as parameter to the
+				 * vPortAllocateSecureContext function. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Read the CONTROL register value. */
+					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+					/* The task that raised the SVC is privileged if Bit[0]
+					 * in the CONTROL register is 0. */
+					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+				}
+				#else
+				{
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0 );
+				}
+				#endif /* configENABLE_MPU */
+
+				configASSERT( xSecureContext != NULL );
+				SecureContext_LoadContext( xSecureContext );
+			}
+			break;
+
+			case portSVC_FREE_SECURE_CONTEXT:
+			{
+				/* R0 contains the secure context handle to be freed. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				/* Free the secure context. */
+				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+			}
+			break;
+		#endif /* configENABLE_TRUSTZONE */
+
+		case portSVC_START_SCHEDULER:
+		{
+			#if( configENABLE_TRUSTZONE == 1 )
+			{
+				/* De-prioritize the non-secure exceptions so that the
+				 * non-secure pendSV runs at the lowest priority. */
+				SecureInit_DePrioritizeNSExceptions();
+
+				/* Initialize the secure context management system. */
+				SecureContext_Init();
+			}
+			#endif /* configENABLE_TRUSTZONE */
+
+			#if( configENABLE_FPU == 1 )
+			{
+				/* Setup the Floating Point Unit (FPU). */
+				prvSetupFPU();
+			}
+			#endif /* configENABLE_FPU */
+
+			/* Setup the context of the first task so that the first task starts
+			 * executing. */
+			vRestoreContextOfFirstTask();
+		}
+		break;
+
+		#if( configENABLE_MPU == 1 )
+			case portSVC_RAISE_PRIVILEGE:
+			{
+				/* Only raise the privilege, if the svc was raised from any of
+				 * the system calls. */
+				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+				{
+					vRaisePrivilege();
+				}
+			}
+			break;
+		#endif /* configENABLE_MPU */
+
+		default:
+		{
+			/* Incorrect SVC call. */
+			configASSERT( pdFALSE );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	 * interrupt. */
+	#if( portPRELOAD_REGISTERS == 0 )
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
+		*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#else /* portPRELOAD_REGISTERS */
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
+		pxTopOfStack--;
+		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#endif /* portPRELOAD_REGISTERS */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+	#if( configENABLE_MPU == 1 )
+	{
+		/* Setup the Memory Protection Unit (MPU). */
+		prvSetupMPU();
+	}
+	#endif /* configENABLE_MPU */
+
+	/* Start the timer that generates the tick ISR. Interrupts are disabled
+	 * here already. */
+	prvSetupTimerInterrupt();
+
+	/* Initialize the critical nesting count ready for the first task. */
+	ulCriticalNesting = 0;
+
+	/* Start the first task. */
+	vStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing. Call the task
+	 * exit error function to prevent compiler warnings about a static function
+	 * not being called in the case that the application writer overrides this
+	 * functionality by defining configTASK_RETURN_ADDRESS. Call
+	 * vTaskSwitchContext() so link time optimization does not remove the
+	 * symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Not implemented in ports where there is nothing to return to.
+	 * Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+	{
+	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+	int32_t lIndex = 0;
+
+		/* Setup MAIR0. */
+		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+		/* This function is called automatically when the task is created - in
+		 * which case the stack region parameters will be valid.  At all other
+		 * times the stack parameters will not be valid and it is assumed that
+		 * the stack region has already been configured. */
+		if( ulStackDepth > 0 )
+		{
+			/* Define the region that allows access to the stack. */
+			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
+															( portMPU_REGION_NON_SHAREABLE ) |
+															( portMPU_REGION_READ_WRITE ) |
+															( portMPU_REGION_EXECUTE_NEVER );
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
+															( portMPU_RLAR_ATTR_INDEX0 ) |
+															( portMPU_RLAR_REGION_ENABLE );
+		}
+
+		/* User supplied configurable regions. */
+		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+		{
+			/* If xRegions is NULL i.e. the task has not specified any MPU
+			 * region, the else part ensures that all the configurable MPU
+			 * regions are invalidated. */
+			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+			{
+				/* Translate the generic region definition contained in xRegions
+				 * into the ARMv8 specific MPU settings that are then stored in
+				 * xMPUSettings. */
+				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+				/* Start address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
+																			( portMPU_REGION_NON_SHAREABLE );
+
+				/* RO/RW. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+				}
+				else
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+				}
+
+				/* XN. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+				}
+
+				/* End Address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
+																			( portMPU_RLAR_REGION_ENABLE );
+
+				/* Normal memory/ Device memory. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+				{
+					/* Attr1 in MAIR0 is configured as device memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+				}
+				else
+				{
+					/* Attr1 in MAIR0 is configured as normal memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+				}
+			}
+			else
+			{
+				/* Invalidate the region. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+			}
+
+			lIndex++;
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.h
new file mode 100644
index 0000000..6314e96
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.s
new file mode 100644
index 0000000..8d9bcc9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.s
@@ -0,0 +1,326 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	EXTERN pxCurrentTCB
+	EXTERN xSecureContext
+	EXTERN vTaskSwitchContext
+	EXTERN vPortSVCHandler_C
+	EXTERN SecureContext_SaveContext
+	EXTERN SecureContext_LoadContext
+
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
+	PUBLIC vPortAllocateSecureContext
+	PUBLIC vRestoreContextOfFirstTask
+	PUBLIC vRaisePrivilege
+	PUBLIC vStartFirstTask
+	PUBLIC ulSetInterruptMaskFromISR
+	PUBLIC vClearInterruptMaskFromISR
+	PUBLIC PendSV_Handler
+	PUBLIC SVC_Handler
+	PUBLIC vPortFreeSecureContext
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+	mrs r0, control							/* r0 = CONTROL. */
+	tst r0, #1								/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	ite ne
+	movne r0, #0							/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	moveq r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+	mrs r0, control							/* r0 = CONTROL. */
+	orr r0, r0, #1							/* r0 = r0 | 1. */
+	msr control, r0							/* CONTROL = r0. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vPortAllocateSecureContext:
+	svc 0									/* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION privileged_functions:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr  r3, [r2]							/* Read pxCurrentTCB. */
+	ldr  r0, [r3]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	str r4, [r2]							/* Disable MPU. */
+
+	adds r3, #4								/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+	ldr  r4, [r3]							/* r4 = *r3 i.e. r4 = MAIR0. */
+	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str  r4, [r2]							/* Program MAIR0. */
+	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+	movs r4, #4								/* r4 = 4. */
+	str  r4, [r2]							/* Program RNR = 4. */
+	adds r3, #4								/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+	ldr  r2, =0xe000ed9c					/* r2 = 0xe000ed9c [Location of RBAR]. */
+	ldmia r3!, {r4-r11}						/* Read 4 set of RBAR/RLAR registers from TCB. */
+	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	str r4, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldm  r0!, {r1-r4}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+	ldr  r5, =xSecureContext
+	str  r1, [r5]							/* Set xSecureContext to this task's value for the same. */
+	msr  psplim, r2							/* Set this task's PSPLIM value. */
+	msr  control, r3						/* Set this task's CONTROL value. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r4									/* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+	ldm  r0!, {r1-r3}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+	ldr  r4, =xSecureContext
+	str  r1, [r4]							/* Set xSecureContext to this task's value for the same. */
+	msr  psplim, r2							/* Set this task's PSPLIM value. */
+	movs r1, #2								/* r1 = 2. */
+	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r3									/* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+	mrs  r0, control						/* Read the CONTROL register. */
+	bic r0, r0, #1							/* Clear the bit 0. */
+	msr  control, r0						/* Write back the new CONTROL value. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
+	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
+	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
+	msr msp, r0								/* Set the MSP back to the start of the stack. */
+	cpsie i									/* Globally enable interrupts. */
+	cpsie f
+	dsb
+	isb
+	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMaskFromISR:
+	mrs r0, PRIMASK
+	cpsid i
+	bx lr
+/*-----------------------------------------------------------*/
+
+vClearInterruptMaskFromISR:
+	msr PRIMASK, r0
+	bx lr
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+	mrs r1, psp								/* Read PSP in r1. */
+	ldr r2, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	ldr r0, [r2]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+
+	cbz r0, save_ns_context					/* No secure context to save. */
+	push {r0-r2, r14}
+	bl SecureContext_SaveContext
+	pop {r0-r3}								/* LR is now in r3. */
+	mov lr, r3								/* LR = r3. */
+	lsls r2, r3, #25						/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	bpl save_ns_context						/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r2, [r3]							/* Read pxCurrentTCB. */
+#if ( configENABLE_MPU == 1 )
+	subs r1, r1, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	str r1, [r2]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mrs r3, control							/* r3 = CONTROL. */
+	mov r4, lr								/* r4 = LR/EXC_RETURN. */
+	stmia r1!, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+#else /* configENABLE_MPU */
+	subs r1, r1, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+	str r1, [r2]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmia r1!, {r0, r2-r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
+#endif /* configENABLE_MPU */
+	b select_next_task
+
+	save_ns_context:
+		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r2, [r3]						/* Read pxCurrentTCB. */
+	#if ( configENABLE_FPU == 1 )
+		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+		it eq
+		vstmdbeq r1!, {s16-s31}				/* Store the FPU registers which are not saved automatically. */
+	#endif /* configENABLE_FPU */
+	#if ( configENABLE_MPU == 1 )
+		subs r1, r1, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+		str r1, [r2]						/* Save the new top of stack in TCB. */
+		adds r1, r1, #16					/* r1 = r1 + 16. */
+		stm r1, {r4-r11}					/* Store the registers that are not saved automatically. */
+		mrs r2, psplim						/* r2 = PSPLIM. */
+		mrs r3, control						/* r3 = CONTROL. */
+		mov r4, lr							/* r4 = LR/EXC_RETURN. */
+		subs r1, r1, #16					/* r1 = r1 - 16. */
+		stm r1, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	#else /* configENABLE_MPU */
+		subs r1, r1, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+		str r1, [r2]						/* Save the new top of stack in TCB. */
+		adds r1, r1, #12					/* r1 = r1 + 12. */
+		stm r1, {r4-r11}					/* Store the registers that are not saved automatically. */
+		mrs r2, psplim						/* r2 = PSPLIM. */
+		mov r3, lr							/* r3 = LR/EXC_RETURN. */
+		subs r1, r1, #12					/* r1 = r1 - 12. */
+		stmia r1!, {r0, r2-r3}				/* Store xSecureContext, PSPLIM and LR on the stack. */
+	#endif /* configENABLE_MPU */
+
+	select_next_task:
+		cpsid i
+		bl vTaskSwitchContext
+		cpsie i
+
+		ldr r2, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r3, [r2]						/* Read pxCurrentTCB. */
+		ldr r1, [r3]						/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+
+	#if ( configENABLE_MPU == 1 )
+		dmb									/* Complete outstanding transfers before disabling MPU. */
+		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		bic r4, r4, #1						/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+		str r4, [r2]						/* Disable MPU. */
+
+		adds r3, #4							/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+		ldr r4, [r3]						/* r4 = *r3 i.e. r4 = MAIR0. */
+		ldr r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+		str r4, [r2]						/* Program MAIR0. */
+		ldr r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+		movs r4, #4							/* r4 = 4. */
+		str r4, [r2]						/* Program RNR = 4. */
+		adds r3, #4							/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+		ldr  r2, =0xe000ed9c				/* r2 = 0xe000ed9c [Location of RBAR]. */
+		ldmia r3!, {r4-r11}					/* Read 4 sets of RBAR/RLAR registers from TCB. */
+		stmia r2!, {r4-r11}					/* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		orr r4, r4, #1						/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+		str r4, [r2]						/* Enable MPU. */
+		dsb									/* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+
+	#if ( configENABLE_MPU == 1 )
+		ldmia r1!, {r0, r2-r4}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		msr control, r3						/* Restore the CONTROL register value for the task. */
+		mov lr, r4							/* LR = r4. */
+		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r2]						/* Restore the task's xSecureContext. */
+		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
+		push {r1,r4}
+		bl SecureContext_LoadContext		/* Restore the secure context. */
+		pop {r1,r4}
+		mov lr, r4							/* LR = r4. */
+		lsls r2, r4, #25					/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+	#else /* configENABLE_MPU */
+		ldmia r1!, {r0, r2-r3}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		mov lr, r3							/* LR = r3. */
+		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r2]						/* Restore the task's xSecureContext. */
+		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
+		push {r1,r3}
+		bl SecureContext_LoadContext		/* Restore the secure context. */
+		pop {r1,r3}
+		mov lr, r3							/* LR = r3. */
+		lsls r2, r3, #25					/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+	#endif /* configENABLE_MPU */
+
+	restore_ns_context:
+		ldmia r1!, {r4-r11}					/* Restore the registers that are not automatically restored. */
+	#if ( configENABLE_FPU == 1 )
+		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+		it eq
+		vldmiaeq r1!, {s16-s31}				/* Restore the FPU registers which are not restored automatically. */
+	#endif /* configENABLE_FPU */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+	tst lr, #4
+	ite eq
+	mrseq r0, msp
+	mrsne r0, psp
+	b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+vPortFreeSecureContext:
+	/* r0 = uint32_t *pulTCB. */
+	ldr r1, [r0]							/* The first item in the TCB is the top of the stack. */
+	ldr r0, [r1]							/* The first item on the stack is the task's xSecureContext. */
+	cmp r0, #0								/* Raise svc if task's xSecureContext is not NULL. */
+	it ne
+	svcne 1									/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h
new file mode 100644
index 0000000..c09b3ce
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M33"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.c
new file mode 100644
index 0000000..8a42230
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.c
@@ -0,0 +1,204 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED		0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED		0x03
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first addess of the allocated memory.
+ */
+typedef struct SecureContext
+{
+	uint8_t *pucCurrentStackPointer;	/**< Current value of stack pointer (PSP). */
+	uint8_t *pucStackLimit;				/**< Last location of the stack memory (PSPLIM). */
+	uint8_t *pucStackStart;				/**< First location of the stack memory. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+	uint32_t ulIPSR;
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* No stack for thread mode until a task's context is loaded. */
+		secureportSET_PSPLIM( securecontextNO_STACK );
+		secureportSET_PSP( securecontextNO_STACK );
+
+		#if( configENABLE_MPU == 1 )
+		{
+			/* Configure thread mode to use PSP and to be unprivileged. */
+			secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+		}
+		#else /* configENABLE_MPU */
+		{
+			/* Configure thread mode to use PSP and to be privileged.. */
+			secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+		}
+		#endif /* configENABLE_MPU */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
+#else /* configENABLE_MPU */
+	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
+#endif /* configENABLE_MPU */
+{
+	uint8_t *pucStackMemory = NULL;
+	uint32_t ulIPSR;
+	SecureContextHandle_t xSecureContextHandle = NULL;
+	#if( configENABLE_MPU == 1 )
+		uint32_t *pulCurrentStackPointer = NULL;
+	#endif /* configENABLE_MPU */
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* Allocate the context structure. */
+		xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
+
+		if( xSecureContextHandle != NULL )
+		{
+			/* Allocate the stack space. */
+			pucStackMemory = pvPortMalloc( ulSecureStackSize );
+
+			if( pucStackMemory != NULL )
+			{
+				/* Since stack grows down, the starting point will be the last
+				 * location. Note that this location is next to the last
+				 * allocated byte because the hardware decrements the stack
+				 * pointer before writing i.e. if stack pointer is 0x2, a push
+				 * operation will decrement the stack pointer to 0x1 and then
+				 * write at 0x1. */
+				xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
+
+				/* The stack cannot go beyond this location. This value is
+				 * programmed in the PSPLIM register on context switch.*/
+				xSecureContextHandle->pucStackLimit = pucStackMemory;
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Store the correct CONTROL value for the task on the stack.
+					 * This value is programmed in the CONTROL register on
+					 * context switch. */
+					pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
+					pulCurrentStackPointer--;
+					if( ulIsTaskPrivileged )
+					{
+						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+					}
+					else
+					{
+						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+					}
+
+					/* Store the current stack pointer. This value is programmed in
+					 * the PSP register on context switch. */
+					xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+				}
+				#else /* configENABLE_MPU */
+				{
+					/* Current SP is set to the starting of the stack. This
+					 * value programmed in the PSP register on context switch. */
+					xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
+
+				}
+				#endif /* configENABLE_MPU */
+			}
+			else
+			{
+				/* Free the context to avoid memory leak and make sure to return
+				 * NULL to indicate failure. */
+				vPortFree( xSecureContextHandle );
+				xSecureContextHandle = NULL;
+			}
+		}
+	}
+
+	return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
+{
+	uint32_t ulIPSR;
+
+	/* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* Ensure that valid parameters are passed. */
+		secureportASSERT( xSecureContextHandle != NULL );
+
+		/* Free the stack space. */
+		vPortFree( xSecureContextHandle->pucStackLimit );
+
+		/* Free the context itself. */
+		vPortFree( xSecureContextHandle );
+	}
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.h
new file mode 100644
index 0000000..a98a7d0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.h
@@ -0,0 +1,111 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include 
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no task's context is loaded.
+ */
+#define securecontextNO_STACK	0x0
+
+/**
+ * @brief Opaque handle.
+ */
+struct SecureContext;
+typedef struct SecureContext*	SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if( configENABLE_MPU == 1 )
+	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
+#else /* configENABLE_MPU */
+	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port.c
new file mode 100644
index 0000000..6df620d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port.c
@@ -0,0 +1,48 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/* Functions implemented in assembler file. */
+extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );
+extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+	SecureContext_LoadContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+	SecureContext_SaveContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s
new file mode 100644
index 0000000..759a21f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s
@@ -0,0 +1,73 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+
+	PUBLIC SecureContext_LoadContextAsm
+	PUBLIC SecureContext_SaveContextAsm
+/*-----------------------------------------------------------*/
+
+SecureContext_LoadContextAsm:
+	/* xSecureContextHandle value is in r0. */
+	mrs r1, ipsr							/* r1 = IPSR. */
+	cbz r1, load_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
+	ldmia r0!, {r1, r2}						/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+#if ( configENABLE_MPU == 1 )
+	ldmia r1!, {r3}							/* Read CONTROL register value from task's stack. r3 = CONTROL. */
+	msr control, r3							/* CONTROL = r3. */
+#endif /* configENABLE_MPU */
+	msr psplim, r2							/* PSPLIM = r2. */
+	msr psp, r1								/* PSP = r1. */
+
+	load_ctx_therad_mode:
+		bx lr
+/*-----------------------------------------------------------*/
+
+SecureContext_SaveContextAsm:
+	/* xSecureContextHandle value is in r0. */
+	mrs r1, ipsr							/* r1 = IPSR. */
+	cbz r1, save_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
+	mrs r1, psp								/* r1 = PSP. */
+#if ( configENABLE_FPU == 1 )
+	vstmdb r1!, {s0}						/* Trigger the defferred stacking of FPU registers. */
+	vldmia r1!, {s0}						/* Nullify the effect of the pervious statement. */
+#endif /* configENABLE_FPU */
+#if ( configENABLE_MPU == 1 )
+	mrs r2, control							/* r2 = CONTROL. */
+	stmdb r1!, {r2}							/* Store CONTROL value on the stack. */
+#endif /* configENABLE_MPU */
+	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+	movs r1, #0								/* r1 = securecontextNO_STACK. */
+	msr psplim, r1							/* PSPLIM = securecontextNO_STACK. */
+	msr psp, r1								/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+
+	save_ctx_therad_mode:
+		bx lr
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.c
new file mode 100644
index 0000000..c4f613f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.c
@@ -0,0 +1,450 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#define secureconfigTOTAL_HEAP_SIZE		( ( ( size_t ) ( 10 * 1024 ) ) )
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+	#define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+	#define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+	#define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE			( ( size_t ) 8 )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+	/* The application writer has already defined the array used for the RTOS
+	 * heap - probably so it can be placed in a special segment or address. */
+	extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+	static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/**< The next free block in the list. */
+	size_t xBlockSize;						/**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/**
+ * @brief Gets set to the top bit of an size_t type.
+ *
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set
+ * then the block belongs to the application. When the bit is free the block is
+ * still part of the free heap space.
+ */
+static size_t xBlockAllocatedBit = 0;
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	uxAddress = ( size_t ) ucHeap;
+
+	if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+	{
+		uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+		uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+	}
+
+	pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	 * blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+	xStart.xBlockSize = ( size_t ) 0;
+
+	/* pxEnd is used to mark the end of the list of free blocks and is inserted
+	 * at the end of the heap space. */
+	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+	uxAddress -= xHeapStructSize;
+	uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+	pxEnd = ( void * ) uxAddress;
+	pxEnd->xBlockSize = 0;
+	pxEnd->pxNextFreeBlock = NULL;
+
+	/* To start with there is a single free block that is sized to take up the
+	 * entire heap space, minus the space taken by pxEnd. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+	/* Only one block exists - and it covers the entire usable heap space. */
+	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	 * than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+	{
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	 * make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+		pxBlockToInsert = pxIterator;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	 * make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+	}
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	 * before and the block after, then it's pxNextFreeBlock pointer will have
+	 * already been set, and should not be set here as that would make it point
+	 * to itself. */
+	if( pxIterator != pxBlockToInsert )
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+	/* If this is the first call to malloc then the heap will require
+	 * initialisation to setup the list of free blocks. */
+	if( pxEnd == NULL )
+	{
+		prvHeapInit();
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Check the requested block size is not so large that the top bit is set.
+	 * The top bit of the block size member of the BlockLink_t structure is used
+	 * to determine who owns the block - the application or the kernel, so it
+	 * must be free. */
+	if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+	{
+		/* The wanted size is increased so it can contain a BlockLink_t
+		 * structure in addition to the requested amount of bytes. */
+		if( xWantedSize > 0 )
+		{
+			xWantedSize += xHeapStructSize;
+
+			/* Ensure that blocks are always aligned to the required number of
+			 * bytes. */
+			if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+			{
+				/* Byte alignment required. */
+				xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+				secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+		{
+			/* Traverse the list from the start (lowest address) block until
+			 * one of adequate size is found. */
+			pxPreviousBlock = &xStart;
+			pxBlock = xStart.pxNextFreeBlock;
+			while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+			{
+				pxPreviousBlock = pxBlock;
+				pxBlock = pxBlock->pxNextFreeBlock;
+			}
+
+			/* If the end marker was reached then a block of adequate size was
+			 * not found. */
+			if( pxBlock != pxEnd )
+			{
+				/* Return the memory space pointed to - jumping over the
+				 * BlockLink_t structure at its start. */
+				pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+				/* This block is being returned for use so must be taken out
+				 * of the list of free blocks. */
+				pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+				/* If the block is larger than required it can be split into
+				 * two. */
+				if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+				{
+					/* This block is to be split into two.  Create a new
+					 * block following the number of bytes requested. The void
+					 * cast is used to prevent byte alignment warnings from the
+					 * compiler. */
+					pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+					secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+					/* Calculate the sizes of two blocks split from the single
+					 * block. */
+					pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+					pxBlock->xBlockSize = xWantedSize;
+
+					/* Insert the new block into the list of free blocks. */
+					prvInsertBlockIntoFreeList( pxNewBlockLink );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+				if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+				{
+					xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* The block is being returned - it is allocated and owned by
+				 * the application and has no "next" block. */
+				pxBlock->xBlockSize |= xBlockAllocatedBit;
+				pxBlock->pxNextFreeBlock = NULL;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceMALLOC( pvReturn, xWantedSize );
+
+	#if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		 * before it. */
+		puc -= xHeapStructSize;
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+
+		/* Check the block is actually allocated. */
+		secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+		secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+			{
+				/* The block is being returned to the heap - it is no longer
+				 * allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+				secureportDISABLE_NON_SECURE_INTERRUPTS();
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+				}
+				secureportENABLE_NON_SECURE_INTERRUPTS();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+	return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.h
new file mode 100644
index 0000000..aae5cfc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.h
@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include 
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void *pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void *pv );
+
+#endif /* __SECURE_HEAP_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.c
new file mode 100644
index 0000000..60ef1e8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.c
@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR					( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS		( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK	( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS		( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK		( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR						( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS			( 29UL )
+#define secureinitFPCCR_LSPENS_MASK			( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS				( 26UL )
+#define secureinitFPCCR_TS_MASK				( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR						( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS			( 10UL )
+#define secureinitNSACR_CP10_MASK			( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS			( 11UL )
+#define secureinitNSACR_CP11_MASK			( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+	uint32_t ulIPSR;
+
+	 /* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		*( secureinitSCB_AIRCR ) =	( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+									( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+									( ( 0x1UL	<< secureinitSCB_AIRCR_PRIS_POS )	& secureinitSCB_AIRCR_PRIS_MASK );
+	}
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+	uint32_t ulIPSR;
+
+	 /* Read the Interrupt Program Status Register (IPSR) value. */
+	secureportREAD_IPSR( ulIPSR );
+
+	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+	 * when the processor is running in the Thread Mode. */
+	if( ulIPSR != 0 )
+	{
+		/* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+		 * permitted. CP11 should be programmed to the same value as CP10. */
+		*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+		/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+		 * that we can enable/disable lazy stacking in port.c file. */
+		*( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
+
+		/* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+		 * registers (S16-S31) are also pushed to stack on exception entry and
+		 * restored on exception return. */
+		*( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+	}
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.h
new file mode 100644
index 0000000..3954e13
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.h
@@ -0,0 +1,53 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h
new file mode 100644
index 0000000..f392537
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT					8
+#define secureportBYTE_ALIGNMENT_MASK				( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+	#define secureportNON_SECURE_CALLABLE			__cmse_nonsecure_entry __root
+#else
+	#define secureportNON_SECURE_CALLABLE			__attribute__((cmse_nonsecure_entry)) __attribute__((used))
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+	__asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+	__asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+	__asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+	__asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+	__asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+	__asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+	__asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+	__asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL		0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL	1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS()		secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x )						\
+	if( ( x ) == 0 )								\
+	{												\
+		secureportDISABLE_SECURE_INTERRUPTS();		\
+		secureportDISABLE_NON_SECURE_INTERRUPTS();	\
+		for( ;; );									\
+	}
+
+#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
new file mode 100644
index 0000000..b0394fb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/* Secure components includes. */
+	#include "secure_context.h"
+	#include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK				( 0x00000004 )
+#define portNVIC_SYSTICK_INT				( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
+#define portNVIC_PENDSVSET					( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY			( 255UL )
+#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE				( 3UL )
+#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS					( 20UL )
+#define portCPACR_CP11_POS					( 22UL )
+
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS					( 31UL )
+#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS					( 30UL )
+#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS				( 0UL )
+#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS				( 8UL )
+#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS				( 16UL )
+#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS				( 24UL )
+#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS				( 0UL )
+#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS				( 8UL )
+#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS				( 16UL )
+#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS				( 24UL )
+#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE			( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE						( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR					( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         FD
+	 * 1111 1111  1111 1111  1111 1111  1111 1101
+	 *
+	 * Bit[6] - 1 --> The exception was taken from the Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 1 --> The exception was taken to the Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
+#else
+	/**
+	 * @brief Initial EXC_RETURN value.
+	 *
+	 *     FF         FF         FF         BC
+	 * 1111 1111  1111 1111  1111 1111  1011 1100
+	 *
+	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
+	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+	 * Bit[3] - 1 --> Return to the Thread mode.
+	 * Bit[2] - 1 --> Restore registers from the process stack.
+	 * Bit[1] - 0 --> Reserved, 0.
+	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+	 */
+	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS			prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS				1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT				0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Setup the Memory Protection Unit (MPU).
+	 */
+	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+	/**
+	 * @brief Setup the Floating Point Unit (FPU).
+	 */
+	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Saved as part of the task context to indicate which context the
+	 * task is using on the secure side.
+	 */
+	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Stop and reset the SysTick. */
+	*( portNVIC_SYSTICK_CTRL ) = 0UL;
+	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+	/* A function that implements a task must not exit or attempt to return to
+	 * its caller as there is nothing to return to. If a task wants to exit it
+	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
+	 * to be triggered if configASSERT() is defined, then stop here so
+	 * application writers can catch the error. */
+	configASSERT( ulCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		 * started to remove a compiler warning about the function being
+		 * defined but never called.  ulDummy is used purely to quieten other
+		 * warnings about code appearing after this function is called - making
+		 * ulDummy volatile makes the compiler think the function could return
+		 * and therefore not output an 'unreachable code' warning for code that
+		 * appears after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __privileged_functions_start__;
+		extern uint32_t * __privileged_functions_end__;
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+		extern uint32_t * __unprivileged_flash_start__;
+		extern uint32_t * __unprivileged_flash_end__;
+		extern uint32_t * __privileged_sram_start__;
+		extern uint32_t * __privileged_sram_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __privileged_functions_start__[];
+		extern uint32_t __privileged_functions_end__[];
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+		extern uint32_t __unprivileged_flash_start__[];
+		extern uint32_t __unprivileged_flash_end__[];
+		extern uint32_t __privileged_sram_start__[];
+		extern uint32_t __privileged_sram_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+
+		/* Check that the MPU is present. */
+		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+		{
+			/* MAIR0 - Index 0. */
+			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+			/* MAIR0 - Index 1. */
+			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+			/* Setup privileged flash as Read Only so that privileged tasks can
+			 * read it but not modify. */
+			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged flash as Read Only by both privileged and
+			 * unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup unprivileged syscalls flash as Read Only by both privileged
+			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
+			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_READ_ONLY );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Setup RAM containing kernel data for privileged access only. */
+			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+								( portMPU_REGION_NON_SHAREABLE ) |
+								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+								( portMPU_REGION_EXECUTE_NEVER );
+			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+								( portMPU_RLAR_ATTR_INDEX0 ) |
+								( portMPU_RLAR_REGION_ENABLE );
+
+			/* Enable mem fault. */
+			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+			/* Enable MPU with privileged background access i.e. unmapped
+			 * regions have privileged access. */
+			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			/* Enable non-secure access to the FPU. */
+			SecureInit_EnableNSFPUAccess();
+		}
+		#endif /* configENABLE_TRUSTZONE */
+
+		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+		 * unprivileged code should be able to access FPU. CP11 should be
+		 * programmed to the same value as CP10. */
+		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+							);
+
+		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
+		 * context on exception entry and restore on exception return.
+		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
+		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+	}
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Set a PendSV to request a context switch. */
+	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	portDISABLE_INTERRUPTS();
+	ulCriticalNesting++;
+
+	/* Barriers are normally not required but do ensure the code is
+	 * completely within the specified behaviour for the architecture. */
+	__asm volatile( "dsb" ::: "memory" );
+	__asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+	configASSERT( ulCriticalNesting );
+	ulCriticalNesting--;
+
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+	#if defined( __ARMCC_VERSION )
+		/* Declaration when these variable are defined in code instead of being
+		 * exported from linker scripts. */
+		extern uint32_t * __syscalls_flash_start__;
+		extern uint32_t * __syscalls_flash_end__;
+	#else
+		/* Declaration when these variable are exported from linker scripts. */
+		extern uint32_t __syscalls_flash_start__[];
+		extern uint32_t __syscalls_flash_end__[];
+	#endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	uint32_t ulR0;
+	#if( configENABLE_MPU == 1 )
+		uint32_t ulControl, ulIsTaskPrivileged;
+	#endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
+	 * R12, LR, PC, xPSR. */
+	ulPC = pulCallerStackAddress[ 6 ];
+	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+	switch( ucSVCNumber )
+	{
+		#if( configENABLE_TRUSTZONE == 1 )
+			case portSVC_ALLOCATE_SECURE_CONTEXT:
+			{
+				/* R0 contains the stack size passed as parameter to the
+				 * vPortAllocateSecureContext function. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				#if( configENABLE_MPU == 1 )
+				{
+					/* Read the CONTROL register value. */
+					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+					/* The task that raised the SVC is privileged if Bit[0]
+					 * in the CONTROL register is 0. */
+					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+				}
+				#else
+				{
+					/* Allocate and load a context for the secure task. */
+					xSecureContext = SecureContext_AllocateContext( ulR0 );
+				}
+				#endif /* configENABLE_MPU */
+
+				configASSERT( xSecureContext != NULL );
+				SecureContext_LoadContext( xSecureContext );
+			}
+			break;
+
+			case portSVC_FREE_SECURE_CONTEXT:
+			{
+				/* R0 contains the secure context handle to be freed. */
+				ulR0 = pulCallerStackAddress[ 0 ];
+
+				/* Free the secure context. */
+				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+			}
+			break;
+		#endif /* configENABLE_TRUSTZONE */
+
+		case portSVC_START_SCHEDULER:
+		{
+			#if( configENABLE_TRUSTZONE == 1 )
+			{
+				/* De-prioritize the non-secure exceptions so that the
+				 * non-secure pendSV runs at the lowest priority. */
+				SecureInit_DePrioritizeNSExceptions();
+
+				/* Initialize the secure context management system. */
+				SecureContext_Init();
+			}
+			#endif /* configENABLE_TRUSTZONE */
+
+			#if( configENABLE_FPU == 1 )
+			{
+				/* Setup the Floating Point Unit (FPU). */
+				prvSetupFPU();
+			}
+			#endif /* configENABLE_FPU */
+
+			/* Setup the context of the first task so that the first task starts
+			 * executing. */
+			vRestoreContextOfFirstTask();
+		}
+		break;
+
+		#if( configENABLE_MPU == 1 )
+			case portSVC_RAISE_PRIVILEGE:
+			{
+				/* Only raise the privilege, if the svc was raised from any of
+				 * the system calls. */
+				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+				{
+					vRaisePrivilege();
+				}
+			}
+			break;
+		#endif /* configENABLE_MPU */
+
+		default:
+		{
+			/* Incorrect SVC call. */
+			configASSERT( pdFALSE );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	 * interrupt. */
+	#if( portPRELOAD_REGISTERS == 0 )
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
+		*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#else /* portPRELOAD_REGISTERS */
+	{
+		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
+		pxTopOfStack--;
+		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
+
+		#if( configENABLE_MPU == 1 )
+		{
+			pxTopOfStack--;
+			if( xRunPrivileged == pdTRUE )
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
+			}
+			else
+			{
+				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
+			}
+		}
+		#endif /* configENABLE_MPU */
+
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
+
+		#if( configENABLE_TRUSTZONE == 1 )
+		{
+			pxTopOfStack--;
+			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
+		}
+		#endif /* configENABLE_TRUSTZONE */
+	}
+	#endif /* portPRELOAD_REGISTERS */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+	#if( configENABLE_MPU == 1 )
+	{
+		/* Setup the Memory Protection Unit (MPU). */
+		prvSetupMPU();
+	}
+	#endif /* configENABLE_MPU */
+
+	/* Start the timer that generates the tick ISR. Interrupts are disabled
+	 * here already. */
+	prvSetupTimerInterrupt();
+
+	/* Initialize the critical nesting count ready for the first task. */
+	ulCriticalNesting = 0;
+
+	/* Start the first task. */
+	vStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing. Call the task
+	 * exit error function to prevent compiler warnings about a static function
+	 * not being called in the case that the application writer overrides this
+	 * functionality by defining configTASK_RETURN_ADDRESS. Call
+	 * vTaskSwitchContext() so link time optimization does not remove the
+	 * symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+	/* Not implemented in ports where there is nothing to return to.
+	 * Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+	{
+	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+	int32_t lIndex = 0;
+
+		/* Setup MAIR0. */
+		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+		/* This function is called automatically when the task is created - in
+		 * which case the stack region parameters will be valid.  At all other
+		 * times the stack parameters will not be valid and it is assumed that
+		 * the stack region has already been configured. */
+		if( ulStackDepth > 0 )
+		{
+			/* Define the region that allows access to the stack. */
+			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
+															( portMPU_REGION_NON_SHAREABLE ) |
+															( portMPU_REGION_READ_WRITE ) |
+															( portMPU_REGION_EXECUTE_NEVER );
+
+			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
+															( portMPU_RLAR_ATTR_INDEX0 ) |
+															( portMPU_RLAR_REGION_ENABLE );
+		}
+
+		/* User supplied configurable regions. */
+		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+		{
+			/* If xRegions is NULL i.e. the task has not specified any MPU
+			 * region, the else part ensures that all the configurable MPU
+			 * regions are invalidated. */
+			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+			{
+				/* Translate the generic region definition contained in xRegions
+				 * into the ARMv8 specific MPU settings that are then stored in
+				 * xMPUSettings. */
+				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+				/* Start address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
+																			( portMPU_REGION_NON_SHAREABLE );
+
+				/* RO/RW. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+				}
+				else
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+				}
+
+				/* XN. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+				{
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+				}
+
+				/* End Address. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
+																			( portMPU_RLAR_REGION_ENABLE );
+
+				/* Normal memory/ Device memory. */
+				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+				{
+					/* Attr1 in MAIR0 is configured as device memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+				}
+				else
+				{
+					/* Attr1 in MAIR0 is configured as normal memory. */
+					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+				}
+			}
+			else
+			{
+				/* Invalidate the region. */
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+			}
+
+			lIndex++;
+		}
+	}
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
new file mode 100644
index 0000000..6314e96
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
new file mode 100644
index 0000000..31623f2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
@@ -0,0 +1,242 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	EXTERN pxCurrentTCB
+	EXTERN vTaskSwitchContext
+	EXTERN vPortSVCHandler_C
+
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
+	PUBLIC vRestoreContextOfFirstTask
+	PUBLIC vRaisePrivilege
+	PUBLIC vStartFirstTask
+	PUBLIC ulSetInterruptMaskFromISR
+	PUBLIC vClearInterruptMaskFromISR
+	PUBLIC PendSV_Handler
+	PUBLIC SVC_Handler
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+	mrs r0, control							/* r0 = CONTROL. */
+	tst r0, #1								/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	ite ne
+	movne r0, #0							/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	moveq r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+	mrs r0, control							/* r0 = CONTROL. */
+	orr r0, r0, #1							/* r0 = r0 | 1. */
+	msr control, r0							/* CONTROL = r0. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION privileged_functions:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr  r1, [r2]							/* Read pxCurrentTCB. */
+	ldr  r0, [r1]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	str r4, [r2]							/* Disable MPU. */
+
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	ldr r3, [r1]							/* r3 = *r1 i.e. r3 = MAIR0. */
+	ldr r2, =0xe000edc0						/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str r3, [r2]							/* Program MAIR0. */
+	ldr r2, =0xe000ed98						/* r2 = 0xe000ed98 [Location of RNR]. */
+	movs r3, #4								/* r3 = 4. */
+	str r3, [r2]							/* Program RNR = 4. */
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	ldr r2, =0xe000ed9c						/* r2 = 0xe000ed9c [Location of RBAR]. */
+	ldmia r1!, {r4-r11}						/* Read 4 sets of RBAR/RLAR registers from TCB. */
+	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	str r4, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldm  r0!, {r1-r3}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+	msr  psplim, r1							/* Set this task's PSPLIM value. */
+	msr  control, r2						/* Set this task's CONTROL value. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r3									/* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+	ldm  r0!, {r1-r2}						/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+	msr  psplim, r1							/* Set this task's PSPLIM value. */
+	movs r1, #2								/* r1 = 2. */
+	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r2									/* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+	mrs  r0, control						/* Read the CONTROL register. */
+	bic r0, r0, #1							/* Clear the bit 0. */
+	msr  control, r0						/* Write back the new CONTROL value. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
+	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
+	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
+	msr msp, r0								/* Set the MSP back to the start of the stack. */
+	cpsie i									/* Globally enable interrupts. */
+	cpsie f
+	dsb
+	isb
+	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMaskFromISR:
+	mrs r0, PRIMASK
+	cpsid i
+	bx lr
+/*-----------------------------------------------------------*/
+
+vClearInterruptMaskFromISR:
+	msr PRIMASK, r0
+	bx lr
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+	mrs r0, psp								/* Read PSP in r0. */
+#if ( configENABLE_FPU == 1 )
+	tst lr, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+	it eq
+	vstmdbeq r0!, {s16-s31}					/* Store the FPU registers which are not saved automatically. */
+#endif /* configENABLE_FPU */
+#if ( configENABLE_MPU == 1 )
+	mrs r1, psplim							/* r1 = PSPLIM. */
+	mrs r2, control							/* r2 = CONTROL. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmdb r0!, {r1-r11}						/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
+#else /* configENABLE_MPU */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmdb r0!, {r2-r11}						/* Store on the stack - PSPLIM, LR and registers that are not automatically. */
+#endif /* configENABLE_MPU */
+
+	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r1, [r2]							/* Read pxCurrentTCB. */
+	str r0, [r1]							/* Save the new top of stack in TCB. */
+
+	cpsid i
+	bl vTaskSwitchContext
+	cpsie i
+
+	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r1, [r2]							/* Read pxCurrentTCB. */
+	ldr r0, [r1]							/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	str r4, [r2]							/* Disable MPU. */
+
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	ldr r3, [r1]							/* r3 = *r1 i.e. r3 = MAIR0. */
+	ldr r2, =0xe000edc0						/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str r3, [r2]							/* Program MAIR0. */
+	ldr r2, =0xe000ed98						/* r2 = 0xe000ed98 [Location of RNR]. */
+	movs r3, #4								/* r3 = 4. */
+	str r3, [r2]							/* Program RNR = 4. */
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	ldr r2, =0xe000ed9c						/* r2 = 0xe000ed9c [Location of RBAR]. */
+	ldmia r1!, {r4-r11}						/* Read 4 sets of RBAR/RLAR registers from TCB. */
+	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	str r4, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldmia r0!, {r1-r11}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
+#else /* configENABLE_MPU */
+	ldmia r0!, {r2-r11}						/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_FPU == 1 )
+	tst r3, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+	it eq
+	vldmiaeq r0!, {s16-s31}					/* Restore the FPU registers which are not restored automatically. */
+#endif /* configENABLE_FPU */
+
+ #if ( configENABLE_MPU == 1 )
+	msr psplim, r1							/* Restore the PSPLIM register value for the task. */
+	msr control, r2							/* Restore the CONTROL register value for the task. */
+#else /* configENABLE_MPU */
+	msr psplim, r2							/* Restore the PSPLIM register value for the task. */
+#endif /* configENABLE_MPU */
+	msr psp, r0								/* Remember the new top of stack for the task. */
+	bx r3
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+	tst lr, #4
+	ite eq
+	mrseq r0, msp
+	mrsne r0, psp
+	b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
new file mode 100644
index 0000000..c09b3ce
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR											char
+#define portFLOAT											float
+#define portDOUBLE											double
+#define portLONG											long
+#define portSHORT											short
+#define portSTACK_TYPE										uint32_t
+#define portBASE_TYPE										long
+
+typedef portSTACK_TYPE										StackType_t;
+typedef long												BaseType_t;
+typedef unsigned long										UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	 * not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC							1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME										"Cortex-M33"
+#define portSTACK_GROWTH									( -1 )
+#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT									8
+#define portNOP()
+#define portINLINE											__inline
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING						1
+#define portDONT_DISCARD									__root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+	#define portUSING_MPU_WRAPPERS							1
+	#define portPRIVILEGE_BIT								( 0x80000000UL )
+#else
+	#define portPRIVILEGE_BIT								( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION							( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
+#define portPRIVILEGED_RAM_REGION							( 3UL )
+#define portSTACK_REGION									( 4UL )
+#define portFIRST_CONFIGURABLE_REGION						( 5UL )
+#define portLAST_CONFIGURABLE_REGION						( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+	uint32_t ulRBAR;	/**< RBAR for the region. */
+	uint32_t ulRLAR;	/**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT						0
+#define portSVC_FREE_SECURE_CONTEXT							1
+#define portSVC_START_SCHEDULER								2
+#define portSVC_RAISE_PRIVILEGE								3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()											vPortYield()
+#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()								vPortEnterCritical()
+#define portEXIT_CRITICAL()									vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+	/**
+	 * @brief Allocate a secure context for the task.
+	 *
+	 * Tasks are not created with a secure context. Any task that is going to call
+	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+	 * secure context before it calls any secure function.
+	 *
+	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+	 */
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
+
+	/**
+	 * @brief Called when a task is deleted to delete the task's secure context,
+	 * if it has one.
+	 *
+	 * @param[in] pxTCB The TCB of the task being deleted.
+	 */
+	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+	#define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+	/**
+	 * @brief Checks whether or not the processor is privileged.
+	 *
+	 * @return 1 if the processor is already privileged, 0 otherwise.
+	 */
+	#define portIS_PRIVILEGED()									xIsPrivileged()
+
+	/**
+	 * @brief Raise an SVC request to raise privilege.
+	 *
+	 * The SVC handler checks that the SVC was raised from a system call and only
+	 * then it raises the privilege. If this is called from any other place,
+	 * the privilege is not raised.
+	 */
+	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+	/**
+	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+	 * register.
+	 */
+	#define portRESET_PRIVILEGE()								vResetPrivilege()
+#else
+	#define portIS_PRIVILEGED()
+	#define portRAISE_PRIVILEGE()
+	#define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM4F/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM4F/port.c
new file mode 100644
index 0000000..cf89048
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM4F/port.c
@@ -0,0 +1,656 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM4F port.
+ *----------------------------------------------------------*/
+
+/* IAR includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __ARMVFP__
+	#error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
+	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
+r0p1 port. */
+#define portCPUID							( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
+#define portCORTEX_M7_r0p1_ID				( 0x410FC271UL )
+#define portCORTEX_M7_r0p0_ID				( 0x410FC270UL )
+
+#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK					( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS			( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR					( 0x01000000 )
+#define portINITIAL_EXC_RETURN				( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR			( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortSysTickHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+extern void vPortStartFirstTask( void );
+
+/*
+ * Turn the VFP on.
+ */
+extern void vPortEnableVFP( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+
+	/* Offset added to account for the way the MCU uses the stack on entry/exit
+	of interrupts, and to ensure alignment. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* LR */
+
+	/* Save code space by skipping register initialisation. */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+
+	/* A save method is being used that requires each task to maintain its
+	own exec return value. */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+	/* This port can be used on all revisions of the Cortex-M7 core other than
+	the r0p1 parts.  r0p1 parts should use the port from the
+	/source/portable/GCC/ARM_CM7/r0p1 directory. */
+	configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
+	configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Ensure the VFP is enabled - it should be anyway. */
+	vPortEnableVFP();
+
+	/* Lazy save always. */
+	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+	/* Start the first task. */
+	vPortStartFirstTask();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
+	executes all interrupts must be unmasked.  There is therefore no need to
+	save and then restore the interrupt mask value as its value is already
+	known. */
+	portDISABLE_INTERRUPTS();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE == 1 )
+
+	__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+	TickType_t xModifiableIdleTime;
+
+		/* Make sure the SysTick reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
+		is accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+		/* Calculate the reload value required to wait xExpectedIdleTime
+		tick periods.  -1 is used because this code will execute part way
+		through one of the tick periods. */
+		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+		if( ulReloadValue > ulStoppedTimerCompensation )
+		{
+			ulReloadValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Enter a critical section but don't use the taskENTER_CRITICAL()
+		method as that will mask interrupts that should exit sleep mode. */
+		__disable_interrupt();
+		__DSB();
+		__ISB();
+
+		/* If a context switch is pending or a task is waiting for the scheduler
+		to be unsuspended then abandon the low power entry. */
+		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+		{
+			/* Restart from whatever is left in the count register to complete
+			this tick period. */
+			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Reset the reload register to the value required for normal tick
+			periods. */
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Re-enable interrupts - see comments above __disable_interrupt()
+			call above. */
+			__enable_interrupt();
+		}
+		else
+		{
+			/* Set the new reload value. */
+			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+			/* Clear the SysTick count flag and set the count value back to
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+			set its parameter to 0 to indicate that its implementation contains
+			its own wait for interrupt or wait for event instruction, and so wfi
+			should not be executed again.  However, the original expected idle
+			time variable must remain unmodified, so a copy is taken. */
+			xModifiableIdleTime = xExpectedIdleTime;
+			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+			if( xModifiableIdleTime > 0 )
+			{
+				__DSB();
+				__WFI();
+				__ISB();
+			}
+			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+			/* Re-enable interrupts to allow the interrupt that brought the MCU
+			out of sleep mode to execute immediately.  see comments above
+			__disable_interrupt() call above. */
+			__enable_interrupt();
+			__DSB();
+			__ISB();
+
+			/* Disable interrupts again because the clock is about to be stopped
+			and interrupts that execute while the clock is stopped will increase
+			any slippage between the time maintained by the RTOS and calendar
+			time. */
+			__disable_interrupt();
+			__DSB();
+			__ISB();
+			
+			/* Disable the SysTick clock without reading the 
+			portNVIC_SYSTICK_CTRL_REG register to ensure the
+			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again, 
+			the time the SysTick is stopped for is accounted for as best it can 
+			be, but using the tickless mode will inevitably result in some tiny 
+			drift of the time maintained by the kernel with respect to calendar 
+			time*/
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+			/* Determine if the SysTick clock has already counted to zero and
+			been set back to the current reload value (the reload back being
+			correct for the entire expected idle time) or if the SysTick is yet
+			to count to zero (in which case an interrupt other than the SysTick
+			must have brought the system out of sleep mode). */
+			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			{
+				uint32_t ulCalculatedLoadValue;
+
+				/* The tick interrupt is already pending, and the SysTick count
+				reloaded with ulReloadValue.  Reset the
+				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+				period. */
+				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+				/* Don't allow a tiny value, or values that have somehow
+				underflowed because the post sleep hook did something
+				that took too long. */
+				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+				{
+					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+				}
+
+				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+				/* As the pending tick will be processed as soon as this
+				function exits, the tick value maintained by the tick is stepped
+				forward by one less than the time spent waiting. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				Work out how long the sleep lasted rounded to complete tick
+				periods (not the ulReload value which accounted for part
+				ticks). */
+				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+				/* How many complete tick periods passed while the processor
+				was waiting? */
+				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+				/* The reload value is set to whatever fraction of a single tick
+				period remains. */
+				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+			}
+
+			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+			value. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+			vTaskStepTick( ulCompleteTickPeriods );
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Exit with interrpts enabled. */
+			__enable_interrupt();
+		}
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__weak void vPortSetupTimerInterrupt( void )
+{
+	/* Calculate the constants required to configure the tick interrupt. */
+	#if( configUSE_TICKLESS_IDLE == 1 )
+	{
+		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+	}
+	#endif /* configUSE_TICKLESS_IDLE */
+
+	/* Stop and clear the SysTick. */
+	portNVIC_SYSTICK_CTRL_REG = 0UL;
+	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredictable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s
new file mode 100644
index 0000000..8f37baa
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include 
+
+	RSEG    CODE:CODE(2)
+	thumb
+
+	EXTERN pxCurrentTCB
+	EXTERN vTaskSwitchContext
+
+	PUBLIC xPortPendSVHandler
+	PUBLIC vPortSVCHandler
+	PUBLIC vPortStartFirstTask
+	PUBLIC vPortEnableVFP
+
+
+/*-----------------------------------------------------------*/
+
+xPortPendSVHandler:
+	mrs r0, psp
+	isb
+	/* Get the location of the current TCB. */
+	ldr	r3, =pxCurrentTCB
+	ldr	r2, [r3]
+
+	/* Is the task using the FPU context?  If so, push high vfp registers. */
+	tst r14, #0x10
+	it eq
+	vstmdbeq r0!, {s16-s31}
+
+	/* Save the core registers. */
+	stmdb r0!, {r4-r11, r14}
+
+	/* Save the new top of stack into the first member of the TCB. */
+	str r0, [r2]
+
+	stmdb sp!, {r0, r3}
+	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+	msr basepri, r0
+	dsb
+	isb
+	bl vTaskSwitchContext
+	mov r0, #0
+	msr basepri, r0
+	ldmia sp!, {r0, r3}
+
+	/* The first item in pxCurrentTCB is the task top of stack. */
+	ldr r1, [r3]
+	ldr r0, [r1]
+
+	/* Pop the core registers. */
+	ldmia r0!, {r4-r11, r14}
+
+	/* Is the task using the FPU context?  If so, pop the high vfp registers
+	too. */
+	tst r14, #0x10
+	it eq
+	vldmiaeq r0!, {s16-s31}
+
+	msr psp, r0
+	isb
+	#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
+		#if WORKAROUND_PMU_CM001 == 1
+			push { r14 }
+			pop { pc }
+		#endif
+	#endif
+
+	bx r14
+
+
+/*-----------------------------------------------------------*/
+
+vPortSVCHandler:
+	/* Get the location of the current TCB. */
+	ldr	r3, =pxCurrentTCB
+	ldr r1, [r3]
+	ldr r0, [r1]
+	/* Pop the core registers. */
+	ldmia r0!, {r4-r11, r14}
+	msr psp, r0
+	isb
+	mov r0, #0
+	msr	basepri, r0
+	bx r14
+
+/*-----------------------------------------------------------*/
+
+vPortStartFirstTask
+	/* Use the NVIC offset register to locate the stack. */
+	ldr r0, =0xE000ED08
+	ldr r0, [r0]
+	ldr r0, [r0]
+	/* Set the msp back to the start of the stack. */
+	msr msp, r0
+	/* Clear the bit that indicates the FPU is in use in case the FPU was used
+	before the scheduler was started - which would otherwise result in the
+	unnecessary leaving of space in the SVC stack for lazy saving of FPU
+	registers. */
+	mov r0, #0
+	msr control, r0
+	/* Call SVC to start the first task. */
+	cpsie i
+	cpsie f
+	dsb
+	isb
+	svc 0
+
+/*-----------------------------------------------------------*/
+
+vPortEnableVFP:
+	/* The FPU enable bits are in the CPACR. */
+	ldr.w r0, =0xE000ED88
+	ldr	r1, [r0]
+
+	/* Enable CP10 and CP11 coprocessors, then save back. */
+	orr	r1, r1, #( 0xf << 20 )
+	str r1, [r0]
+	bx	r14
+
+
+
+	END
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM4F/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM4F/portmacro.h
new file mode 100644
index 0000000..445a2dd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM4F/portmacro.h
@@ -0,0 +1,173 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* IAR includes. */
+#include 
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD()											\
+{															\
+	/* Set a PendSV to request a context switch. */			\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;			\
+	__DSB();												\
+	__ISB();												\
+}
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()							\
+{															\
+	__set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY );	\
+	__DSB();												\
+	__ISB();												\
+}
+
+#define portENABLE_INTERRUPTS()					__set_BASEPRI( 0 )
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()		__get_BASEPRI(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	__set_BASEPRI( x )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+the source code because to do so would cause other compilers to generate
+warnings. */
+#pragma diag_suppress=Pe191
+#pragma diag_suppress=Pa082
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/port.c
new file mode 100644
index 0000000..6fb38e8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/port.c
@@ -0,0 +1,747 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM4F port.
+ *----------------------------------------------------------*/
+
+/* IAR includes. */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#warning This is not yet a documented port as it has not been fully tested, so no demo projects that use this port are provided.
+
+#ifndef __ARMVFP__
+	#error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
+	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG				( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG				( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG		( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG					( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSPRI1_REG					( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
+#define portNVIC_SYS_CTRL_STATE_REG				( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
+#define portNVIC_MEM_FAULT_ENABLE				( 1UL << 16UL )
+
+/* Constants required to access and manipulate the MPU. */
+#define portMPU_TYPE_REG						( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_REGION_BASE_ADDRESS_REG			( * ( ( volatile uint32_t * ) 0xe000ed9C ) )
+#define portMPU_REGION_ATTRIBUTE_REG			( * ( ( volatile uint32_t * ) 0xe000edA0 ) )
+#define portMPU_CTRL_REG						( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portEXPECTED_MPU_TYPE_VALUE				( 8UL << 8UL ) /* 8 regions, unified. */
+#define portMPU_ENABLE							( 0x01UL )
+#define portMPU_BACKGROUND_ENABLE				( 1UL << 2UL )
+#define portPRIVILEGED_EXECUTION_START_ADDRESS	( 0UL )
+#define portMPU_REGION_VALID					( 0x10UL )
+#define portMPU_REGION_ENABLE					( 0x01UL )
+#define portPERIPHERALS_START_ADDRESS			0x40000000UL
+#define portPERIPHERALS_END_ADDRESS				0x5FFFFFFFUL
+
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
+r0p1 port. */
+#define portCPUID							( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
+#define portCORTEX_M7_r0p1_ID				( 0x410FC271UL )
+#define portCORTEX_M7_r0p0_ID				( 0x410FC270UL )
+
+#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portNVIC_SVC_PRI					( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK					( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS			( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR					( 0x01000000 )
+#define portINITIAL_EXC_RETURN				( 0xfffffffd )
+#define portINITIAL_CONTROL_IF_UNPRIVILEGED	( 0x03 )
+#define portINITIAL_CONTROL_IF_PRIVILEGED	( 0x02 )
+
+/* Offsets in the stack to the parameters when inside the SVC handler. */
+#define portOFFSET_TO_PC						( 6 )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR			( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
+
+/*
+ * Configure a number of standard MPU regions that are used by all tasks.
+ */
+static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the smallest MPU region size that a given number of bytes will fit
+ * into.  The region size is returned as the value that should be programmed
+ * into the region attribute register for that region.
+ */
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+extern void vPortStartFirstTask( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Turn the VFP on.
+ */
+extern void vPortEnableVFP( void );
+
+/*
+ * The C portion of the SVC handler.
+ */
+void vPortSVCHandler_C( uint32_t *pulParam );
+
+/*
+ * Called from the SVC handler used to start the scheduler.
+ */
+extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+
+	/* Offset added to account for the way the MCU uses the stack on entry/exit
+	of interrupts, and to ensure alignment. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0;	/* LR */
+
+	/* Save code space by skipping register initialisation. */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+
+	/* A save method is being used that requires each task to maintain its
+	own exec return value. */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+	pxTopOfStack -= 9;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	if( xRunPrivileged == pdTRUE )
+	{
+		*pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
+	}
+	else
+	{
+		*pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
+	}
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulParam )
+{
+uint8_t ucSVCNumber;
+
+	/* The stack contains: r0, r1, r2, r3, r12, r14, the return address and
+	xPSR.  The first argument (r0) is pulParam[ 0 ]. */
+	ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];
+	switch( ucSVCNumber )
+	{
+		case portSVC_START_SCHEDULER	:	portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
+											vPortRestoreContextOfFirstTask();
+											break;
+
+		case portSVC_YIELD				:	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+											/* Barriers are normally not required
+											but do ensure the code is completely
+											within the specified behaviour for the
+											architecture. */
+											__asm volatile( "dsb" ::: "memory" );
+											__asm volatile( "isb" );
+
+											break;
+
+		case portSVC_RAISE_PRIVILEGE	:	__asm volatile
+											(
+												"	mrs r1, control		\n" /* Obtain current control value. */
+												"	bic r1, r1, #1		\n" /* Set privilege bit. */
+												"	msr control, r1		\n" /* Write back new control value. */
+												::: "r1", "memory"
+											);
+											break;
+
+		default							:	/* Unknown SVC call. */
+											break;
+	}
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+	/* This port can be used on all revisions of the Cortex-M7 core other than
+	the r0p1 parts.  r0p1 parts should use the port from the
+	/source/portable/GCC/ARM_CM7/r0p1 directory. */
+	configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
+	configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Configure the regions in the MPU that are common to all tasks. */
+	prvSetupMPU();
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Ensure the VFP is enabled - it should be anyway. */
+	vPortEnableVFP();
+
+	/* Lazy save always. */
+	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+	/* Start the first task. */
+	vPortStartFirstTask();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	vPortResetPrivilege( xRunningPrivileged );
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	configASSERT( uxCriticalNesting );
+
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+
+	vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
+	executes all interrupts must be unmasked.  There is therefore no need to
+	save and then restore the interrupt mask value as its value is already
+	known. */
+	portDISABLE_INTERRUPTS();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__weak void vPortSetupTimerInterrupt( void )
+{
+	/* Stop and clear the SysTick. */
+	portNVIC_SYSTICK_CTRL_REG = 0UL;
+	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupMPU( void )
+{
+extern uint32_t __privileged_functions_end__[];
+extern uint32_t __FLASH_segment_start__[];
+extern uint32_t __FLASH_segment_end__[];
+extern uint32_t __privileged_data_start__[];
+extern uint32_t __privileged_data_end__[];
+
+	/* Check the expected MPU is present. */
+	if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+	{
+		/* First setup the entire flash for unprivileged read only access. */
+		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
+											( portMPU_REGION_VALID ) |
+											( portUNPRIVILEGED_FLASH_REGION );
+
+		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_READ_ONLY ) |
+										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+										( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
+										( portMPU_REGION_ENABLE );
+
+		/* Setup the first 16K for privileged only access (even though less
+		than 10K is actually being used).  This is where the kernel code is
+		placed. */
+		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
+											( portMPU_REGION_VALID ) |
+											( portPRIVILEGED_FLASH_REGION );
+
+		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
+										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+										( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
+										( portMPU_REGION_ENABLE );
+
+		/* Setup the privileged data RAM region.  This is where the kernel data
+		is placed. */
+		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
+											( portMPU_REGION_VALID ) |
+											( portPRIVILEGED_RAM_REGION );
+
+		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+										prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
+										( portMPU_REGION_ENABLE );
+
+		/* By default allow everything to access the general peripherals.  The
+		system peripherals and registers are protected. */
+		portMPU_REGION_BASE_ADDRESS_REG =	( portPERIPHERALS_START_ADDRESS ) |
+											( portMPU_REGION_VALID ) |
+											( portGENERAL_PERIPHERALS_REGION );
+
+		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
+										( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
+										( portMPU_REGION_ENABLE );
+
+		/* Enable the memory fault exception. */
+		portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
+
+		/* Enable the MPU with the background region configured. */
+		portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
+{
+uint32_t ulRegionSize, ulReturnValue = 4;
+
+	/* 32 is the smallest region size, 31 is the largest valid value for
+	ulReturnValue. */
+	for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
+	{
+		if( ulActualSizeInBytes <= ulRegionSize )
+		{
+			break;
+		}
+		else
+		{
+			ulReturnValue++;
+		}
+	}
+
+	/* Shift the code by one before returning so it can be written directly
+	into the the correct bit position of the attribute register. */
+	return ( ulReturnValue << 1UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+{
+extern uint32_t __SRAM_segment_start__[];
+extern uint32_t __SRAM_segment_end__[];
+extern uint32_t __privileged_data_start__[];
+extern uint32_t __privileged_data_end__[];
+int32_t lIndex;
+uint32_t ul;
+
+	if( xRegions == NULL )
+	{
+		/* No MPU regions are specified so allow access to all RAM. */
+		xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
+				( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
+				( portMPU_REGION_VALID ) |
+				( portSTACK_REGION );
+
+		xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
+				( portMPU_REGION_READ_WRITE ) |
+				( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+				( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
+				( portMPU_REGION_ENABLE );
+
+		/* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
+		just removed the privileged only parameters. */
+		xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
+				( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
+				( portMPU_REGION_VALID ) |
+				( portSTACK_REGION + 1 );
+
+		xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
+				( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+				( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+				prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
+				( portMPU_REGION_ENABLE );
+
+		/* Invalidate all other regions. */
+		for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+		{
+			xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+			xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
+		}
+	}
+	else
+	{
+		/* This function is called automatically when the task is created - in
+		which case the stack region parameters will be valid.  At all other
+		times the stack parameters will not be valid and it is assumed that the
+		stack region has already been configured. */
+		if( ulStackDepth > 0 )
+		{
+			/* Define the region that allows access to the stack. */
+			xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
+					( ( uint32_t ) pxBottomOfStack ) |
+					( portMPU_REGION_VALID ) |
+					( portSTACK_REGION ); /* Region number. */
+
+			xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
+					( portMPU_REGION_READ_WRITE ) | /* Read and write. */
+					( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
+					( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+					( portMPU_REGION_ENABLE );
+		}
+
+		lIndex = 0;
+
+		for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+		{
+			if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
+			{
+				/* Translate the generic region definition contained in
+				xRegions into the CM3 specific MPU settings that are then
+				stored in xMPUSettings. */
+				xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
+						( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
+						( portMPU_REGION_VALID ) |
+						( portSTACK_REGION + ul ); /* Region number. */
+
+				xMPUSettings->xRegion[ ul ].ulRegionAttribute =
+						( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
+						( xRegions[ lIndex ].ulParameters ) |
+						( portMPU_REGION_ENABLE );
+			}
+			else
+			{
+				/* Invalidate the region. */
+				xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+				xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
+			}
+
+			lIndex++;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredictable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portasm.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portasm.s
new file mode 100644
index 0000000..60a5e57
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portasm.s
@@ -0,0 +1,199 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include 
+
+	RSEG    CODE:CODE(2)
+	thumb
+
+	EXTERN pxCurrentTCB
+	EXTERN vTaskSwitchContext
+	EXTERN vPortSVCHandler_C
+
+	PUBLIC xPortPendSVHandler
+	PUBLIC vPortSVCHandler
+	PUBLIC vPortStartFirstTask
+	PUBLIC vPortEnableVFP
+	PUBLIC vPortRestoreContextOfFirstTask
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
+
+/*-----------------------------------------------------------*/
+
+xPortPendSVHandler:
+	mrs r0, psp
+	isb
+	/* Get the location of the current TCB. */
+	ldr	r3, =pxCurrentTCB
+	ldr	r2, [r3]
+
+	/* Is the task using the FPU context?  If so, push high vfp registers. */
+	tst r14, #0x10
+	it eq
+	vstmdbeq r0!, {s16-s31}
+
+	/* Save the core registers. */
+	mrs r1, control
+	stmdb r0!, {r1, r4-r11, r14}
+
+	/* Save the new top of stack into the first member of the TCB. */
+	str r0, [r2]
+
+	stmdb sp!, {r0, r3}
+	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+	msr basepri, r0
+	dsb
+	isb
+	bl vTaskSwitchContext
+	mov r0, #0
+	msr basepri, r0
+	ldmia sp!, {r0, r3}
+
+	/* The first item in pxCurrentTCB is the task top of stack. */
+	ldr r1, [r3]
+	ldr r0, [r1]
+	/* Move onto the second item in the TCB... */
+	add r1, r1, #4
+	/* Region Base Address register. */
+	ldr r2, =0xe000ed9c
+	/* Read 4 sets of MPU registers. */
+	ldmia r1!, {r4-r11}
+	/* Write 4 sets of MPU registers. */
+	stmia r2!, {r4-r11}
+	/* Pop the registers that are not automatically saved on exception entry. */
+	ldmia r0!, {r3-r11, r14}
+	msr control, r3
+
+	/* Is the task using the FPU context?  If so, pop the high vfp registers
+	too. */
+	tst r14, #0x10
+	it eq
+	vldmiaeq r0!, {s16-s31}
+
+	msr psp, r0
+	isb
+
+	bx r14
+
+
+/*-----------------------------------------------------------*/
+
+vPortSVCHandler:
+	#ifndef USE_PROCESS_STACK	/* Code should not be required if a main() is using the process stack. */
+		tst lr, #4
+		ite eq
+		mrseq r0, msp
+		mrsne r0, psp
+	#else
+		mrs r0, psp
+	#endif
+		b vPortSVCHandler_C
+
+/*-----------------------------------------------------------*/
+
+vPortStartFirstTask:
+	/* Use the NVIC offset register to locate the stack. */
+	ldr r0, =0xE000ED08
+	ldr r0, [r0]
+	ldr r0, [r0]
+	/* Set the msp back to the start of the stack. */
+	msr msp, r0
+	/* Clear the bit that indicates the FPU is in use in case the FPU was used
+	before the scheduler was started - which would otherwise result in the
+	unnecessary leaving of space in the SVC stack for lazy saving of FPU
+	registers. */
+	mov r0, #0
+	msr control, r0
+	/* Call SVC to start the first task. */
+	cpsie i
+	cpsie f
+	dsb
+	isb
+	svc 0
+
+/*-----------------------------------------------------------*/
+
+vPortRestoreContextOfFirstTask:
+	/* Use the NVIC offset register to locate the stack. */
+	ldr r0, =0xE000ED08
+	ldr r0, [r0]
+	ldr r0, [r0]
+	/* Set the msp back to the start of the stack. */
+	msr msp, r0
+	/* Restore the context. */
+	ldr	r3, =pxCurrentTCB
+	ldr r1, [r3]
+	/* The first item in the TCB is the task top of stack. */
+	ldr r0, [r1]
+	/* Move onto the second item in the TCB... */
+	add r1, r1, #4
+	/* Region Base Address register. */
+	ldr r2, =0xe000ed9c
+	/* Read 4 sets of MPU registers. */
+	ldmia r1!, {r4-r11}
+	/* Write 4 sets of MPU registers. */
+	stmia r2!, {r4-r11}
+	/* Pop the registers that are not automatically saved on exception entry. */
+	ldmia r0!, {r3-r11, r14}
+	msr control, r3
+	/* Restore the task stack pointer. */
+	msr psp, r0
+	mov r0, #0
+	msr	basepri, r0
+	bx r14
+
+/*-----------------------------------------------------------*/
+
+vPortEnableVFP:
+	/* The FPU enable bits are in the CPACR. */
+	ldr.w r0, =0xE000ED88
+	ldr	r1, [r0]
+
+	/* Enable CP10 and CP11 coprocessors, then save back. */
+	orr	r1, r1, #( 0xf << 20 )
+	str r1, [r0]
+	bx	r14
+
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+	mrs r0, control		/* r0 = CONTROL. */
+	tst r0, #1			/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	ite ne
+	movne r0, #0		/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	moveq r0, #1		/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	bx lr				/* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+	mrs r0, control		/* r0 = CONTROL. */
+	orr r0, r0, #1		/* r0 = r0 | 1. */
+	msr control, r0		/* CONTROL = r0. */
+	bx lr				/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portmacro.h
new file mode 100644
index 0000000..493066a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portmacro.h
@@ -0,0 +1,228 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* IAR includes. */
+#include 
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* MPU specific constants. */
+#define portUSING_MPU_WRAPPERS		1
+#define portPRIVILEGE_BIT			( 0x80000000UL )
+
+#define portMPU_REGION_READ_WRITE				( 0x03UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY		( 0x05UL << 24UL )
+#define portMPU_REGION_READ_ONLY				( 0x06UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE	( 0x01UL << 24UL )
+#define portMPU_REGION_CACHEABLE_BUFFERABLE		( 0x07UL << 16UL )
+#define portMPU_REGION_EXECUTE_NEVER			( 0x01UL << 28UL )
+
+#define portUNPRIVILEGED_FLASH_REGION			( 0UL )
+#define portPRIVILEGED_FLASH_REGION				( 1UL )
+#define portPRIVILEGED_RAM_REGION				( 2UL )
+#define portGENERAL_PERIPHERALS_REGION			( 3UL )
+#define portSTACK_REGION						( 4UL )
+#define portFIRST_CONFIGURABLE_REGION			( 5UL )
+#define portLAST_CONFIGURABLE_REGION			( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS			( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS					( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, r0, #1 \n msr control, r0 " ::: "r0", "memory" )
+
+typedef struct MPU_REGION_REGISTERS
+{
+	uint32_t ulRegionBaseAddress;
+	uint32_t ulRegionAttribute;
+} xMPU_REGION_REGISTERS;
+
+/* Plus 1 to create space for the stack region. */
+typedef struct MPU_SETTINGS
+{
+	xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
+} xMPU_SETTINGS;
+
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+/* SVC numbers for various services. */
+#define portSVC_START_SCHEDULER				0
+#define portSVC_YIELD						1
+#define portSVC_RAISE_PRIVILEGE				2
+
+/* Scheduler utilities. */
+#define portYIELD()				__asm volatile ( "	SVC	%0	\n" :: "i" (portSVC_YIELD) : "memory" )
+#define portYIELD_WITHIN_API()								\
+{															\
+	/* Set a PendSV to request a context switch. */			\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;			\
+	__DSB();												\
+	__ISB();												\
+}
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD_WITHIN_API()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()							\
+{															\
+	__set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY );	\
+	__DSB();												\
+	__ISB();												\
+}
+
+#define portENABLE_INTERRUPTS()					__set_BASEPRI( 0 )
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()		__get_BASEPRI(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	__set_BASEPRI( x )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+/*-----------------------------------------------------------*/
+
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED()			xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+*/
+#define portRAISE_PRIVILEGE()		__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE()		vResetPrivilege()
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+the source code because to do so would cause other compilers to generate
+warnings. */
+#pragma diag_suppress=Pe191
+#pragma diag_suppress=Pa082
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM7/ReadMe.txt b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM7/ReadMe.txt
new file mode 100644
index 0000000..2116456
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM7/ReadMe.txt
@@ -0,0 +1,18 @@
+There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers.
+The best option depends on the revision of the ARM Cortex-M7 core in use.  The
+revision is specified by an 'r' number, and a 'p' number, so will look something
+like 'r0p1'.  Check the documentation for the microcontroller in use to find the 
+revision of the Cortex-M7 core used in that microcontroller.  If in doubt, use 
+the FreeRTOS port provided specifically for r0p1 revisions, as that can be used
+with all core revisions.
+
+The first option is to use the ARM Cortex-M4F port, and the second option is to
+use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround.
+
+If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be
+used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in 
+the /FreeRTOS/Source/portable/IAR/ARM_CM4F directory.
+
+If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM
+Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1
+directory.
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/port.c
new file mode 100644
index 0000000..4b3e628
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/port.c
@@ -0,0 +1,644 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM4F port.
+ *----------------------------------------------------------*/
+
+/* IAR includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __ARMVFP__
+	#error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
+	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK					( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS			( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR					( 0x01000000 )
+#define portINITIAL_EXC_RETURN				( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR			( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortSysTickHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+extern void vPortStartFirstTask( void );
+
+/*
+ * Turn the VFP on.
+ */
+extern void vPortEnableVFP( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+
+	/* Offset added to account for the way the MCU uses the stack on entry/exit
+	of interrupts, and to ensure alignment. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* LR */
+
+	/* Save code space by skipping register initialisation. */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+
+	/* A save method is being used that requires each task to maintain its
+	own exec return value. */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Ensure the VFP is enabled - it should be anyway. */
+	vPortEnableVFP();
+
+	/* Lazy save always. */
+	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+	/* Start the first task. */
+	vPortStartFirstTask();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
+	executes all interrupts must be unmasked.  There is therefore no need to
+	save and then restore the interrupt mask value as its value is already
+	known. */
+	portDISABLE_INTERRUPTS();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE == 1 )
+
+	__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+	TickType_t xModifiableIdleTime;
+
+		/* Make sure the SysTick reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
+		is accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+		/* Calculate the reload value required to wait xExpectedIdleTime
+		tick periods.  -1 is used because this code will execute part way
+		through one of the tick periods. */
+		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+		if( ulReloadValue > ulStoppedTimerCompensation )
+		{
+			ulReloadValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Enter a critical section but don't use the taskENTER_CRITICAL()
+		method as that will mask interrupts that should exit sleep mode. */
+		__disable_interrupt();
+		__DSB();
+		__ISB();
+
+		/* If a context switch is pending or a task is waiting for the scheduler
+		to be unsuspended then abandon the low power entry. */
+		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+		{
+			/* Restart from whatever is left in the count register to complete
+			this tick period. */
+			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Reset the reload register to the value required for normal tick
+			periods. */
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Re-enable interrupts - see comments above __disable_interrupt()
+			call above. */
+			__enable_interrupt();
+		}
+		else
+		{
+			/* Set the new reload value. */
+			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+			/* Clear the SysTick count flag and set the count value back to
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+			set its parameter to 0 to indicate that its implementation contains
+			its own wait for interrupt or wait for event instruction, and so wfi
+			should not be executed again.  However, the original expected idle
+			time variable must remain unmodified, so a copy is taken. */
+			xModifiableIdleTime = xExpectedIdleTime;
+			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+			if( xModifiableIdleTime > 0 )
+			{
+				__DSB();
+				__WFI();
+				__ISB();
+			}
+			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+			/* Re-enable interrupts to allow the interrupt that brought the MCU
+			out of sleep mode to execute immediately.  see comments above
+			__disable_interrupt() call above. */
+			__enable_interrupt();
+			__DSB();
+			__ISB();
+
+			/* Disable interrupts again because the clock is about to be stopped
+			and interrupts that execute while the clock is stopped will increase
+			any slippage between the time maintained by the RTOS and calendar
+			time. */
+			__disable_interrupt();
+			__DSB();
+			__ISB();
+			
+			/* Disable the SysTick clock without reading the 
+			portNVIC_SYSTICK_CTRL_REG register to ensure the
+			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again, 
+			the time the SysTick is stopped for is accounted for as best it can 
+			be, but using the tickless mode will inevitably result in some tiny 
+			drift of the time maintained by the kernel with respect to calendar 
+			time*/
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+			/* Determine if the SysTick clock has already counted to zero and
+			been set back to the current reload value (the reload back being
+			correct for the entire expected idle time) or if the SysTick is yet
+			to count to zero (in which case an interrupt other than the SysTick
+			must have brought the system out of sleep mode). */
+			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			{
+				uint32_t ulCalculatedLoadValue;
+
+				/* The tick interrupt is already pending, and the SysTick count
+				reloaded with ulReloadValue.  Reset the
+				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+				period. */
+				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+				/* Don't allow a tiny value, or values that have somehow
+				underflowed because the post sleep hook did something
+				that took too long. */
+				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+				{
+					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+				}
+
+				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+				/* As the pending tick will be processed as soon as this
+				function exits, the tick value maintained by the tick is stepped
+				forward by one less than the time spent waiting. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				Work out how long the sleep lasted rounded to complete tick
+				periods (not the ulReload value which accounted for part
+				ticks). */
+				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+				/* How many complete tick periods passed while the processor
+				was waiting? */
+				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+				/* The reload value is set to whatever fraction of a single tick
+				period remains. */
+				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+			}
+
+			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+			value. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+			vTaskStepTick( ulCompleteTickPeriods );
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Exit with interrpts enabled. */
+			__enable_interrupt();
+		}
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__weak void vPortSetupTimerInterrupt( void )
+{
+	/* Calculate the constants required to configure the tick interrupt. */
+	#if( configUSE_TICKLESS_IDLE == 1 )
+	{
+		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+	}
+	#endif /* configUSE_TICKLESS_IDLE */
+
+	/* Stop and clear the SysTick. */
+	portNVIC_SYSTICK_CTRL_REG = 0UL;
+	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredictable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portasm.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portasm.s
new file mode 100644
index 0000000..37ac1a7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portasm.s
@@ -0,0 +1,151 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include 
+
+	RSEG    CODE:CODE(2)
+	thumb
+
+	EXTERN pxCurrentTCB
+	EXTERN vTaskSwitchContext
+
+	PUBLIC xPortPendSVHandler
+	PUBLIC vPortSVCHandler
+	PUBLIC vPortStartFirstTask
+	PUBLIC vPortEnableVFP
+
+
+/*-----------------------------------------------------------*/
+
+xPortPendSVHandler:
+	mrs r0, psp
+	isb
+	/* Get the location of the current TCB. */
+	ldr	r3, =pxCurrentTCB
+	ldr	r2, [r3]
+
+	/* Is the task using the FPU context?  If so, push high vfp registers. */
+	tst r14, #0x10
+	it eq
+	vstmdbeq r0!, {s16-s31}
+
+	/* Save the core registers. */
+	stmdb r0!, {r4-r11, r14}
+
+	/* Save the new top of stack into the first member of the TCB. */
+	str r0, [r2]
+
+	stmdb sp!, {r0, r3}
+	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+	cpsid i
+	msr basepri, r0
+	dsb
+	isb
+	cpsie i
+	bl vTaskSwitchContext
+	mov r0, #0
+	msr basepri, r0
+	ldmia sp!, {r0, r3}
+
+	/* The first item in pxCurrentTCB is the task top of stack. */
+	ldr r1, [r3]
+	ldr r0, [r1]
+
+	/* Pop the core registers. */
+	ldmia r0!, {r4-r11, r14}
+
+	/* Is the task using the FPU context?  If so, pop the high vfp registers
+	too. */
+	tst r14, #0x10
+	it eq
+	vldmiaeq r0!, {s16-s31}
+
+	msr psp, r0
+	isb
+	#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
+		#if WORKAROUND_PMU_CM001 == 1
+			push { r14 }
+			pop { pc }
+		#endif
+	#endif
+
+	bx r14
+
+
+/*-----------------------------------------------------------*/
+
+vPortSVCHandler:
+	/* Get the location of the current TCB. */
+	ldr	r3, =pxCurrentTCB
+	ldr r1, [r3]
+	ldr r0, [r1]
+	/* Pop the core registers. */
+	ldmia r0!, {r4-r11, r14}
+	msr psp, r0
+	isb
+	mov r0, #0
+	msr	basepri, r0
+	bx r14
+
+/*-----------------------------------------------------------*/
+
+vPortStartFirstTask
+	/* Use the NVIC offset register to locate the stack. */
+	ldr r0, =0xE000ED08
+	ldr r0, [r0]
+	ldr r0, [r0]
+	/* Set the msp back to the start of the stack. */
+	msr msp, r0
+	/* Clear the bit that indicates the FPU is in use in case the FPU was used
+	before the scheduler was started - which would otherwise result in the
+	unnecessary leaving of space in the SVC stack for lazy saving of FPU
+	registers. */
+	mov r0, #0
+	msr control, r0
+	/* Call SVC to start the first task. */
+	cpsie i
+	cpsie f
+	dsb
+	isb
+	svc 0
+
+/*-----------------------------------------------------------*/
+
+vPortEnableVFP:
+	/* The FPU enable bits are in the CPACR. */
+	ldr.w r0, =0xE000ED88
+	ldr	r1, [r0]
+
+	/* Enable CP10 and CP11 coprocessors, then save back. */
+	orr	r1, r1, #( 0xf << 20 )
+	str r1, [r0]
+	bx	r14
+
+
+
+	END
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h
new file mode 100644
index 0000000..cce737e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h
@@ -0,0 +1,176 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* IAR includes. */
+#include 
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD()											\
+{															\
+	/* Set a PendSV to request a context switch. */			\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;			\
+	__DSB();												\
+	__ISB();												\
+}
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()							\
+{															\
+	 /* Errata work around. */								\
+	__disable_interrupt();									\
+	__set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY );	\
+	__DSB();												\
+	__ISB();												\
+	__enable_interrupt();									\
+}
+
+#define portENABLE_INTERRUPTS()					__set_BASEPRI( 0 )
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()		__get_BASEPRI(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	__set_BASEPRI( x )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+the source code because to do so would cause other compilers to generate
+warnings. */
+#pragma diag_suppress=Pe191
+#pragma diag_suppress=Pa082
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/port.c
new file mode 100644
index 0000000..85ce365
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/port.c
@@ -0,0 +1,316 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#ifndef configSETUP_TICK_INTERRUPT
+	#error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt.
+#endif
+
+#ifndef configCLEAR_TICK_INTERRUPT
+	#error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt.
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+this value. */
+#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
+
+/* Tasks are not created with a floating point context, but can be given a
+floating point context after they have been created.  A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
+
+/* Constants required to setup the initial task context. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS			( 0x01UL )
+
+/* Masks all bits in the APSR other than the mode bits. */
+#define portAPSR_MODE_BITS_MASK			( 0x1F )
+
+/* The value of the mode bits in the APSR when the CPU is executing in user
+mode. */
+#define portAPSR_USER_MODE				( 0x10 )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing.  This function is necessarily written in
+ * assembly code so is implemented in portASM.s.
+ */
+extern void vPortRestoreTaskContext( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting.  This
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts.  As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then
+a floating point context must be saved and restored for the task. */
+volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
+
+/* Set to 1 to pend a context switch from an ISR. */
+volatile uint32_t ulPortYieldRequired = pdFALSE;
+
+/* Counts the interrupt nesting depth.  A context switch is only performed if
+if the nesting depth is 0. */
+volatile uint32_t ulPortInterruptNesting = 0UL;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro.
+
+	The fist real value on the stack is the status register, which is set for
+	system mode, with interrupts enabled.  A few NULLs are added first to ensure
+	GDB does not try decoding a non-existent return address. */
+	*pxTopOfStack = ( StackType_t ) NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+	{
+		/* The task will start in THUMB mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+
+	pxTopOfStack--;
+
+	/* Next the return address, which in this case is the start of the task. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+
+	/* Next all the registers other than the stack pointer. */
+	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The task will start with a critical nesting count of 0 as interrupts are
+	enabled. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+	pxTopOfStack--;
+
+	/* The task will start without a floating point context.  A task that uses
+	the floating point hardware must call vPortTaskUsesFPU() before executing
+	any floating point instructions. */
+	*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( ulPortInterruptNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+uint32_t ulAPSR;
+
+	/* Only continue if the CPU is not in User mode.  The CPU must be in a
+	Privileged mode for the scheduler to start. */
+	__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
+	ulAPSR &= portAPSR_MODE_BITS_MASK;
+	configASSERT( ulAPSR != portAPSR_USER_MODE );
+
+	if( ulAPSR != portAPSR_USER_MODE )
+	{
+		/* Start the timer that generates the tick ISR. */
+		portDISABLE_INTERRUPTS();
+		configSETUP_TICK_INTERRUPT();
+
+		/* Start the first task executing. */
+		vPortRestoreTaskContext();
+	}
+
+	/* Will only get here if vTaskStartScheduler() was called with the CPU in
+	a non-privileged mode or the binary point register was not set to its lowest
+	possible value.  prvTaskExitError() is referenced to prevent a compiler
+	warning about it being defined but not referenced in the case that the user
+	defines their own exit address. */
+	( void ) prvTaskExitError;
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( ulCriticalNesting == 1 )
+	{
+		configASSERT( ulPortInterruptNesting == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as the critical section is being
+		exited. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then all interrupt
+		priorities must be re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Critical nesting has reached zero so all interrupt priorities
+			should be unmasked. */
+			portENABLE_INTERRUPTS();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void FreeRTOS_Tick_Handler( void )
+{
+uint32_t ulInterruptStatus;
+
+	ulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+
+	/* Increment the RTOS tick. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		ulPortYieldRequired = pdTRUE;
+	}
+
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulInterruptStatus );
+
+	configCLEAR_TICK_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortTaskUsesFPU( void )
+{
+uint32_t ulInitialFPSCR = 0;
+
+	/* A task is registering the fact that it needs an FPU context.  Set the
+	FPU flag (which is saved as part of the task context). */
+	ulPortTaskHasFPUContext = pdTRUE;
+
+	/* Initialise the floating point status register. */
+	__asm volatile ( "FMXR 	FPSCR, %0" :: "r" (ulInitialFPSCR) );
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portASM.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portASM.s
new file mode 100644
index 0000000..5c9add7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portASM.s
@@ -0,0 +1,247 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+#include "FreeRTOSConfig.h"
+
+	SECTION .text:CODE:ROOT(2)
+	arm
+
+	/* Variables and functions. */
+	EXTERN pxCurrentTCB
+	EXTERN vTaskSwitchContext
+	EXTERN vApplicationIRQHandler
+	EXTERN ulPortInterruptNesting
+	EXTERN ulPortTaskHasFPUContext
+	EXTERN ulPortYieldRequired
+	EXTERN ulCriticalNesting
+
+	PUBLIC FreeRTOS_IRQ_Handler
+	PUBLIC FreeRTOS_SVC_Handler
+	PUBLIC vPortRestoreTaskContext
+
+SYS_MODE			EQU		0x1f
+SVC_MODE			EQU		0x13
+IRQ_MODE			EQU		0x12
+
+portSAVE_CONTEXT MACRO
+
+	/* Save the LR and SPSR onto the system mode stack before switching to
+	system mode to save the remaining system mode registers. */
+	SRSDB	sp!, #SYS_MODE
+	CPS		#SYS_MODE
+	PUSH	{R0-R12, R14}
+
+	/* Push the critical nesting count. */
+	LDR		R2, =ulCriticalNesting
+	LDR		R1, [R2]
+	PUSH	{R1}
+
+	/* Does the task have a floating point context that needs saving?  If
+	ulPortTaskHasFPUContext is 0 then no. */
+	LDR		R2, =ulPortTaskHasFPUContext
+	LDR		R3, [R2]
+	CMP		R3, #0
+
+	/* Save the floating point context, if any. */
+	FMRXNE  R1,  FPSCR
+	VPUSHNE {D0-D15}
+#if configFPU_D32 == 1
+	VPUSHNE	{D16-D31}
+#endif /* configFPU_D32 */
+	PUSHNE	{R1}
+
+	/* Save ulPortTaskHasFPUContext itself. */
+	PUSH	{R3}
+
+	/* Save the stack pointer in the TCB. */
+	LDR		R0, =pxCurrentTCB
+	LDR		R1, [R0]
+	STR		SP, [R1]
+
+	ENDM
+
+; /**********************************************************************/
+
+portRESTORE_CONTEXT MACRO
+
+	/* Set the SP to point to the stack of the task being restored. */
+	LDR		R0, =pxCurrentTCB
+	LDR		R1, [R0]
+	LDR		SP, [R1]
+
+	/* Is there a floating point context to restore?  If the restored
+	ulPortTaskHasFPUContext is zero then no. */
+	LDR		R0, =ulPortTaskHasFPUContext
+	POP		{R1}
+	STR		R1, [R0]
+	CMP		R1, #0
+
+	/* Restore the floating point context, if any. */
+	POPNE 	{R0}
+#if configFPU_D32 == 1
+	VPOPNE	{D16-D31}
+#endif /* configFPU_D32 */
+	VPOPNE	{D0-D15}
+	VMSRNE  FPSCR, R0
+
+	/* Restore the critical section nesting depth. */
+	LDR		R0, =ulCriticalNesting
+	POP		{R1}
+	STR		R1, [R0]
+
+	/* Restore all system mode registers other than the SP (which is already
+	being used). */
+	POP		{R0-R12, R14}
+
+	/* Return to the task code, loading CPSR on the way. */
+	RFEIA	sp!
+
+	ENDM
+
+
+
+
+/******************************************************************************
+ * SVC handler is used to yield.
+ *****************************************************************************/
+FreeRTOS_SVC_Handler:
+	/* Save the context of the current task and select a new task to run. */
+	portSAVE_CONTEXT
+	LDR R0, =vTaskSwitchContext
+	BLX	R0
+	portRESTORE_CONTEXT
+
+
+/******************************************************************************
+ * vPortRestoreTaskContext is used to start the scheduler.
+ *****************************************************************************/
+vPortRestoreTaskContext:
+	/* Switch to system mode. */
+	CPS		#SYS_MODE
+	portRESTORE_CONTEXT
+
+FreeRTOS_IRQ_Handler:
+	/* Return to the interrupted instruction. */
+	SUB		lr, lr, #4
+
+	/* Push the return address and SPSR. */
+	PUSH	{lr}
+	MRS		lr, SPSR
+	PUSH	{lr}
+
+	/* Change to supervisor mode to allow reentry. */
+	CPS		#SVC_MODE
+
+	/* Push used registers. */
+	PUSH	{r0-r3, r12}
+
+	/* Increment nesting count.  r3 holds the address of ulPortInterruptNesting
+	for future use.  r1 holds the original ulPortInterruptNesting value for
+	future use. */
+	LDR		r3, =ulPortInterruptNesting
+	LDR		r1, [r3]
+	ADD		r0, r1, #1
+	STR		r0, [r3]
+
+	/* Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
+	future use. */
+	MOV		r0, sp
+	AND		r2, r0, #4
+	SUB		sp, sp, r2
+
+	/* Call the interrupt handler. */
+	PUSH	{r0-r3, lr}
+	LDR		r1, =vApplicationIRQHandler
+	BLX		r1
+	POP		{r0-r3, lr}
+	ADD		sp, sp, r2
+
+	CPSID	i
+	DSB
+	ISB
+
+	/* Write to the EOI register. */
+	LDR 	r2, =configEOI_ADDRESS
+	STR		r0, [r2]
+
+	/* Restore the old nesting count. */
+	STR		r1, [r3]
+
+	/* A context switch is never performed if the nesting count is not 0. */
+	CMP		r1, #0
+	BNE		exit_without_switch
+
+	/* Did the interrupt request a context switch?  r1 holds the address of
+	ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
+	use. */
+	LDR		r1, =ulPortYieldRequired
+	LDR		r0, [r1]
+	CMP		r0, #0
+	BNE		switch_before_exit
+
+exit_without_switch:
+	/* No context switch.  Restore used registers, LR_irq and SPSR before
+	returning. */
+	POP		{r0-r3, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	MOVS	PC, LR
+
+switch_before_exit:
+	/* A context swtich is to be performed.  Clear the context switch pending
+	flag. */
+	MOV		r0, #0
+	STR		r0, [r1]
+
+	/* Restore used registers, LR-irq and SPSR before saving the context
+	to the task stack. */
+	POP		{r0-r3, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	portSAVE_CONTEXT
+
+	/* Call the function that selects the new task to execute.
+	vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
+	instructions, or 8 byte aligned stack allocated data.  LR does not need
+	saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
+	LDR		R0, =vTaskSwitchContext
+	BLX		R0
+
+	/* Restore the context of, and branch to, the task selected to execute
+	next. */
+	portRESTORE_CONTEXT
+
+	END
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portmacro.h
new file mode 100644
index 0000000..b6c075c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portmacro.h
@@ -0,0 +1,181 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include 
+
+#ifdef __cplusplus
+	extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+typedef uint32_t TickType_t;
+#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* Called at the end of an ISR that can cause a context switch. */
+#define portEND_SWITCHING_ISR( xSwitchRequired )\
+{												\
+extern volatile uint32_t ulPortYieldRequired;	\
+												\
+	if( xSwitchRequired != pdFALSE )			\
+	{											\
+		ulPortYieldRequired = pdTRUE;			\
+	}											\
+}
+
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() __asm volatile ( "SWI 0		\n"				\
+									 "ISB		  " );
+
+
+/*-----------------------------------------------------------
+ * Critical section control
+ *----------------------------------------------------------*/
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+extern void vPortInstallFreeRTOSVectorTable( void );
+
+/* The I bit within the CPSR. */
+#define portINTERRUPT_ENABLE_BIT	( 1 << 7 )
+
+/* In the absence of a priority mask register, these functions and macros
+globally enable and disable interrupts. */
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+#define portENABLE_INTERRUPTS()		__asm volatile ( "CPSIE i 	\n"	);
+#define portDISABLE_INTERRUPTS()	__asm volatile ( "CPSID i 	\n"		\
+													 "DSB		\n"		\
+													 "ISB		  " );
+#pragma inline
+static inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void )
+{
+volatile uint32_t ulCPSR;
+
+	__asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) );
+	ulCPSR &= portINTERRUPT_ENABLE_BIT;
+	portDISABLE_INTERRUPTS();
+	return ulCPSR;
+}
+
+#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	if( x == 0 ) portENABLE_INTERRUPTS()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
+
+/* Prototype of the FreeRTOS tick handler.  This must be installed as the
+handler for whichever peripheral is used to generate the RTOS tick. */
+void FreeRTOS_Tick_Handler( void );
+
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+before any floating point instructions are executed. */
+void vPortTaskUsesFPU( void );
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __CLZ( uxReadyPriorities ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#define portNOP() __asm volatile( "NOP" )
+#define portINLINE inline
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+the source code because to do so would cause other compilers to generate
+warnings. */
+#pragma diag_suppress=Pe191
+#pragma diag_suppress=Pa082
+
+#ifdef __cplusplus
+	} /* extern C */
+#endif
+
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ATMega323/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ATMega323/port.c
new file mode 100644
index 0000000..0914f40
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ATMega323/port.c
@@ -0,0 +1,339 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include 
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the AVR/IAR port.
+ *----------------------------------------------------------*/
+
+/* Start tasks with interrupts enables. */
+#define portFLAGS_INT_ENABLED					( ( StackType_t ) 0x80 )
+
+/* Hardware constants for timer 1. */
+#define portCLEAR_COUNTER_ON_MATCH				( ( uint8_t ) 0x08 )
+#define portPRESCALE_64							( ( uint8_t ) 0x03 )
+#define portCLOCK_PRESCALER						( ( uint32_t ) 64 )
+#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE	( ( uint8_t ) 0x10 )
+
+/* The number of bytes used on the hardware stack by the task start address. */
+#define portBYTES_USED_BY_RETURN_ADDRESS		( 2 )
+/*-----------------------------------------------------------*/
+
+/* Stores the critical section nesting.  This must not be initialised to 0.
+It will be initialised when a task starts. */
+#define portNO_CRITICAL_NESTING					( ( UBaseType_t ) 0 )
+UBaseType_t uxCriticalNesting = 0x50;
+
+
+/*
+ * Perform hardware setup to enable ticks from timer 1, compare match A.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * The IAR compiler does not have full support for inline assembler, so
+ * these are defined in the portmacro assembler file.
+ */
+extern void vPortYieldFromTick( void );
+extern void vPortStart( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint16_t usAddress;
+StackType_t *pxTopOfHardwareStack;
+
+	/* Place a few bytes of known values on the bottom of the stack.
+	This is just useful for debugging. */
+
+	*pxTopOfStack = 0x11;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33;
+	pxTopOfStack--;
+
+	/* Remember where the top of the hardware stack is - this is required
+	below. */
+	pxTopOfHardwareStack = pxTopOfStack;
+
+
+	/* Simulate how the stack would look after a call to vPortYield(). */
+
+	/*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
+
+
+
+	/* The IAR compiler requires two stacks per task.  First there is the
+	hardware call stack which uses the AVR stack pointer.  Second there is the
+	software stack (local variables, parameter passing, etc.) which uses the
+	AVR Y register.
+
+	This function places both stacks within the memory block passed in as the
+	first parameter.  The hardware stack is placed at the bottom of the memory
+	block.  A gap is then left for the hardware stack to grow.  Next the software
+	stack is placed.  The amount of space between the software and hardware
+	stacks is defined by configCALL_STACK_SIZE.
+
+
+
+	The first part of the stack is the hardware stack.  Place the start
+	address of the task on the hardware stack. */
+	usAddress = ( uint16_t ) pxCode;
+	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+	pxTopOfStack--;
+
+	usAddress >>= 8;
+	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+	pxTopOfStack--;
+
+
+	/* Leave enough space for the hardware stack before starting the software
+	stack.  The '- 2' is because we have already used two spaces for the
+	address of the start of the task. */
+	pxTopOfStack -= ( configCALL_STACK_SIZE - 2 );
+
+
+
+	/* Next simulate the stack as if after a call to portSAVE_CONTEXT().
+	portSAVE_CONTEXT places the flags on the stack immediately after r0
+	to ensure the interrupts get disabled as soon as possible, and so ensuring
+	the stack use is minimal should a context switch interrupt occur. */
+	*pxTopOfStack = ( StackType_t ) 0x00;	/* R0 */
+	pxTopOfStack--;
+	*pxTopOfStack = portFLAGS_INT_ENABLED;
+	pxTopOfStack--;
+
+	/* Next place the address of the hardware stack.  This is required so
+	the AVR stack pointer can be restored to point to the hardware stack. */
+	pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS;
+	usAddress = ( uint16_t ) pxTopOfHardwareStack;
+
+	/* SPL */
+	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+	pxTopOfStack--;
+
+	/* SPH */
+	usAddress >>= 8;
+	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+	pxTopOfStack--;
+
+
+
+
+	/* Now the remaining registers. */
+	*pxTopOfStack = ( StackType_t ) 0x01;	/* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x02;	/* R2 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x03;	/* R3 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x04;	/* R4 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x05;	/* R5 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x06;	/* R6 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x07;	/* R7 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x08;	/* R8 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x09;	/* R9 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x10;	/* R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x11;	/* R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12;	/* R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x13;	/* R13 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x14;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x15;	/* R15 */
+	pxTopOfStack--;
+
+	/* Place the parameter on the stack in the expected location. */
+	usAddress = ( uint16_t ) pvParameters;
+	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+	pxTopOfStack--;
+
+	usAddress >>= 8;
+	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0x18;	/* R18 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x19;	/* R19 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x20;	/* R20 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x21;	/* R21 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x22;	/* R22 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x23;	/* R23 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x24;	/* R24 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x25;	/* R25 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x26;	/* R26 X */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x27;	/* R27 */
+	pxTopOfStack--;
+
+	/* The Y register is not stored as it is used as the software stack and
+	gets saved into the task control block. */
+
+	*pxTopOfStack = ( StackType_t ) 0x30;	/* R30 Z */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x031;	/* R31 */
+
+	pxTopOfStack--;
+	*pxTopOfStack = portNO_CRITICAL_NESTING;	/* Critical nesting is zero when the task starts. */
+
+	/*lint +e950 +e611 +e923 */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Setup the hardware to generate the tick. */
+	prvSetupTimerInterrupt();
+
+	/* Restore the context of the first task that is going to run.
+	Normally we would just call portRESTORE_CONTEXT() here, but as the IAR
+	compiler does not fully support inline assembler we have to make a call.*/
+	vPortStart();
+
+	/* Should not get here! */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the AVR port will get stopped.  If required simply
+	disable the tick interrupt here. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup timer 1 compare match A to generate a tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+uint32_t ulCompareMatch;
+uint8_t ucHighByte, ucLowByte;
+
+	/* Using 16bit timer 1 to generate the tick.  Correct fuses must be
+	selected for the configCPU_CLOCK_HZ clock. */
+
+	ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+	/* We only have 16 bits so have to scale to get our required tick rate. */
+	ulCompareMatch /= portCLOCK_PRESCALER;
+
+	/* Adjust for correct value. */
+	ulCompareMatch -= ( uint32_t ) 1;
+
+	/* Setup compare match value for compare match A.  Interrupts are disabled
+	before this is called so we need not worry here. */
+	ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
+	ulCompareMatch >>= 8;
+	ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
+	OCR1AH = ucHighByte;
+	OCR1AL = ucLowByte;
+
+	/* Setup clock source and compare match behaviour. */
+	ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64;
+	TCCR1B = ucLowByte;
+
+	/* Enable the interrupt - this is okay as interrupt are currently globally
+	disabled. */
+	TIMSK |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 1
+
+	/*
+	 * Tick ISR for preemptive scheduler.  We can use a __task attribute as
+	 * the context is saved at the start of vPortYieldFromTick().  The tick
+	 * count is incremented after the context is saved.
+	 */
+	__task void SIG_OUTPUT_COMPARE1A( void )
+	{
+		vPortYieldFromTick();
+		asm( "reti" );
+	}
+
+#else
+
+	/*
+	 * Tick ISR for the cooperative scheduler.  All this does is increment the
+	 * tick count.  We don't need to switch context, this can only be done by
+	 * manual calls to taskYIELD();
+	 *
+	 * THE INTERRUPT VECTOR IS POPULATED IN portmacro.s90.  DO NOT INSTALL
+	 * IT HERE USING THE USUAL PRAGMA.
+	 */
+	__interrupt void SIG_OUTPUT_COMPARE1A( void )
+	{
+		xTaskIncrementTick();
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	uxCriticalNesting--;
+	if( uxCriticalNesting == portNO_CRITICAL_NESTING )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.h
new file mode 100644
index 0000000..20acd2c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.h
@@ -0,0 +1,112 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V1.2.3
+
+	+ portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it
+	  base 16.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	uint8_t
+#define portBASE_TYPE	char
+#define portPOINTER_SIZE_TYPE uint16_t
+
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portENTER_CRITICAL()	vPortEnterCritical()
+#define portEXIT_CRITICAL()		vPortExitCritical()
+
+#define portDISABLE_INTERRUPTS()	asm( "cli" )
+#define portENABLE_INTERRUPTS()		asm( "sei" )
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			1
+#define portNOP()					asm( "nop" )
+/*-----------------------------------------------------------*/
+
+/* Kernel utilities. */
+void vPortYield( void );
+#define portYIELD()	vPortYield()
+
+#ifdef IAR_MEGA_AVR
+	#define outb( PORT, VALUE ) PORT = VALUE
+#endif
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.s90 b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.s90
new file mode 100644
index 0000000..6e33f48
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.s90
@@ -0,0 +1,245 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+#include 
+
+; Declare all extern symbols here - including any ISRs that are referenced in
+; the vector table.
+
+; ISR functions
+; -------------
+EXTERN SIG_OUTPUT_COMPARE1A
+EXTERN SIG_UART_RECV
+EXTERN SIG_UART_DATA
+
+
+; Functions used by scheduler
+; ---------------------------
+EXTERN vTaskSwitchContext
+EXTERN pxCurrentTCB
+EXTERN xTaskIncrementTick
+EXTERN uxCriticalNesting
+
+; Functions implemented in this file
+; ----------------------------------
+PUBLIC vPortYield
+PUBLIC vPortYieldFromTick
+PUBLIC vPortStart
+
+
+; Interrupt vector table.
+; -----------------------
+;
+; For simplicity the RTOS tick interrupt routine uses the __task keyword.
+; As the IAR compiler does not permit a function to be declared using both
+; __task and __interrupt, the use of __task necessitates that the interrupt
+; vector table be setup manually.
+;
+; To write an ISR, implement the ISR function using the __interrupt keyword
+; but do not install the interrupt using the "#pragma vector=ABC" method.
+; Instead manually place the name of the ISR in the vector table using an
+; ORG and jmp instruction as demonstrated below.
+; You will also have to add an EXTERN statement at the top of the file.
+
+	ASEG
+
+
+	ORG TIMER1_COMPA_vect				; Vector address
+		jmp SIG_OUTPUT_COMPARE1A		; ISR
+
+	ORG USART_RXC_vect					; Vector address
+		jmp SIG_UART_RECV				; ISR
+
+	ORG USART_UDRE_vect					; Vector address
+		jmp SIG_UART_DATA				; ISR
+
+
+	RSEG CODE
+
+
+
+; Saving and Restoring a Task Context and Task Switching
+; ------------------------------------------------------
+;
+; The IAR compiler does not fully support inline assembler, so saving and
+; restoring a task context has to be written in an asm file.
+;
+; vPortYield() and vPortYieldFromTick() are usually written in C.  Doing
+; so in this case would required calls to be made to portSAVE_CONTEXT() and
+; portRESTORE_CONTEXT().  This is dis-advantageous as the context switch
+; function would require two extra jump and return instructions over the
+; WinAVR equivalent.
+;
+; To avoid this I have opted to implement both vPortYield() and
+; vPortYieldFromTick() in this assembly file.  For convenience
+; portSAVE_CONTEXT and portRESTORE_CONTEXT are implemented as macros.
+
+portSAVE_CONTEXT MACRO
+	st	-y, r0			; First save the r0 register - we need to use this.
+	in	r0, SREG		; Obtain the SREG value so we can disable interrupts...
+	cli					; ... as soon as possible.
+	st	-y, r0			; Store the SREG as it was before we disabled interrupts.
+
+	in	r0, SPL			; Next store the hardware stack pointer.  The IAR...
+	st	-y, r0			; ... compiler uses the hardware stack as a call stack ...
+	in	r0, SPH			; ...  only.
+	st	-y, r0
+
+	st	-y, r1			; Now store the rest of the registers.  Dont store the ...
+	st	-y, r2			; ... the Y register here as it is used as the software
+	st	-y, r3			; stack pointer and will get saved into the TCB.
+	st	-y, r4
+	st	-y, r5
+	st	-y, r6
+	st	-y, r7
+	st	-y, r8
+	st	-y, r9
+	st	-y, r10
+	st	-y, r11
+	st	-y, r12
+	st	-y, r13
+	st	-y, r14
+	st	-y, r15
+	st	-y, r16
+	st	-y, r17
+	st	-y, r18
+	st	-y, r19
+	st	-y, r20
+	st	-y, r21
+	st	-y, r22
+	st	-y, r23
+	st	-y, r24
+	st	-y, r25
+	st	-y, r26
+	st	-y, r27
+	st	-y, r30
+	st	-y, r31
+	lds r0, uxCriticalNesting
+	st	-y, r0					; Store the critical nesting counter.
+
+	lds	r26, pxCurrentTCB		; Finally save the software stack pointer (Y ...
+	lds	r27, pxCurrentTCB + 1	; ... register) into the TCB.
+	st	x+, r28
+	st	x+, r29
+
+	ENDM
+
+
+portRESTORE_CONTEXT MACRO
+	lds	r26, pxCurrentTCB
+	lds	r27, pxCurrentTCB + 1	; Restore the software stack pointer from ...
+	ld	r28, x+					; the TCB into the software stack pointer (...
+	ld	r29, x+					; ... the Y register).
+
+	ld	r0, y+
+	sts	uxCriticalNesting, r0
+	ld	r31, y+					; Restore the registers down to R0.  The Y
+	ld	r30, y+					; register is missing from this list as it
+	ld	r27, y+					; has already been restored.
+	ld	r26, y+
+	ld	r25, y+
+	ld	r24, y+
+	ld	r23, y+
+	ld	r22, y+
+	ld	r21, y+
+	ld	r20, y+
+	ld	r19, y+
+	ld	r18, y+
+	ld	r17, y+
+	ld	r16, y+
+	ld	r15, y+
+	ld	r14, y+
+	ld	r13, y+
+	ld	r12, y+
+	ld	r11, y+
+	ld	r10, y+
+	ld	r9, y+
+	ld	r8, y+
+	ld	r7, y+
+	ld	r6, y+
+	ld	r5, y+
+	ld	r4, y+
+	ld	r3, y+
+	ld	r2, y+
+	ld	r1, y+
+
+	ld	r0, y+					; The next thing on the stack is the ...
+	out	SPH, r0					; ... hardware stack pointer.
+	ld	r0, y+
+	out	SPL, r0
+
+	ld	r0, y+					; Next there is the SREG register.
+	out SREG, r0
+
+	ld	r0, y+					; Finally we have finished with r0, so restore r0.
+
+	ENDM
+
+
+
+; vPortYield() and vPortYieldFromTick()
+; -------------------------------------
+;
+; Manual and preemptive context switch functions respectively.
+; The IAR compiler does not fully support inline assembler,
+; so these are implemented here rather than the more usually
+; place of within port.c.
+
+vPortYield:
+	portSAVE_CONTEXT			; Save the context of the current task.
+	call vTaskSwitchContext		; Call the scheduler.
+	portRESTORE_CONTEXT			; Restore the context of whichever task the ...
+	ret							; ... scheduler decided should run.
+
+vPortYieldFromTick:
+	portSAVE_CONTEXT			; Save the context of the current task.
+	call xTaskIncrementTick		; Call the timer tick function.
+	tst r16
+	breq SkipTaskSwitch
+	call vTaskSwitchContext		; Call the scheduler.
+SkipTaskSwitch:
+	portRESTORE_CONTEXT			; Restore the context of whichever task the ...
+	ret							; ... scheduler decided should run.
+
+; vPortStart()
+; ------------
+;
+; Again due to the lack of inline assembler, this is required
+; to get access to the portRESTORE_CONTEXT macro.
+
+vPortStart:
+	portRESTORE_CONTEXT
+	ret
+
+
+; Just a filler for unused interrupt vectors.
+vNoISR:
+	reti
+
+
+	END
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AVR32_UC3/exception.s82 b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AVR32_UC3/exception.s82
new file mode 100644
index 0000000..2df712c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AVR32_UC3/exception.s82
@@ -0,0 +1,310 @@
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Exception and interrupt vectors.
+ *
+ * This file maps all events supported by an AVR32UC.
+ *
+ * - Compiler:           IAR EWAVR32
+ * - Supported devices:  All AVR32UC devices with an INTC module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include 
+#include "intc.h"
+
+
+//! @{
+//! \verbatim
+
+
+// Start of Exception Vector Table.
+
+  // EVBA must be aligned with a power of two strictly greater than the EVBA-
+  // relative offset of the last vector.
+  COMMON  EVTAB:CODE:ROOT(9)
+
+
+  // Force EVBA initialization.
+  EXTERN  ??init_EVBA
+  REQUIRE ??init_EVBA
+
+  // Export symbol.
+  PUBLIC  ??EVBA
+  PUBLIC  _evba
+??EVBA:
+_evba:
+
+        ORG 0x000
+        // Unrecoverable Exception.
+_handle_Unrecoverable_Exception:
+        rjmp $
+
+        ORG 0x004
+        // TLB Multiple Hit: UNUSED IN AVR32UC.
+_handle_TLB_Multiple_Hit:
+        rjmp $
+
+        ORG 0x008
+        // Bus Error Data Fetch.
+_handle_Bus_Error_Data_Fetch:
+        rjmp $
+
+        ORG 0x00C
+         // Bus Error Instruction Fetch.
+_handle_Bus_Error_Instruction_Fetch:
+        rjmp $
+
+        ORG 0x010
+        // NMI.
+_handle_NMI:
+        rjmp $
+
+        ORG 0x014
+        // Instruction Address.
+_handle_Instruction_Address:
+        rjmp $
+
+        ORG 0x018
+        // ITLB Protection.
+_handle_ITLB_Protection:
+        rjmp $
+
+        ORG 0x01C
+        // Breakpoint.
+_handle_Breakpoint:
+        rjmp $
+
+        ORG 0x020
+        // Illegal Opcode.
+_handle_Illegal_Opcode:
+        rjmp $
+
+        ORG 0x024
+        // Unimplemented Instruction.
+_handle_Unimplemented_Instruction:
+        rjmp $
+
+        ORG 0x028
+        // Privilege Violation.
+_handle_Privilege_Violation:
+        rjmp $
+
+        ORG 0x02C
+        // Floating-Point: UNUSED IN AVR32UC.
+_handle_Floating_Point:
+        rjmp $
+
+        ORG 0x030
+        // Coprocessor Absent: UNUSED IN AVR32UC.
+_handle_Coprocessor_Absent:
+        rjmp $
+
+        ORG 0x034
+        // Data Address (Read).
+_handle_Data_Address_Read:
+        rjmp $
+
+        ORG 0x038
+        // Data Address (Write).
+_handle_Data_Address_Write:
+        rjmp $
+
+        ORG 0x03C
+        // DTLB Protection (Read).
+_handle_DTLB_Protection_Read:
+        rjmp $
+
+        ORG 0x040
+        // DTLB Protection (Write).
+_handle_DTLB_Protection_Write:
+        rjmp $
+
+        ORG 0x044
+        // DTLB Modified: UNUSED IN AVR32UC.
+_handle_DTLB_Modified:
+        rjmp $
+
+        ORG 0x050
+        // ITLB Miss: UNUSED IN AVR32UC.
+_handle_ITLB_Miss:
+        rjmp $
+
+        ORG 0x060
+        // DTLB Miss (Read): UNUSED IN AVR32UC.
+_handle_DTLB_Miss_Read:
+        rjmp $
+
+        ORG 0x070
+        // DTLB Miss (Write): UNUSED IN AVR32UC.
+_handle_DTLB_Miss_Write:
+        rjmp $
+
+        ORG 0x100
+        // Supervisor Call.
+_handle_Supervisor_Call:
+        lddpc   pc, __SCALLYield
+
+
+// Interrupt support.
+// The interrupt controller must provide the offset address relative to EVBA.
+// Important note:
+//   All interrupts call a C function named _get_interrupt_handler.
+//   This function will read group and interrupt line number to then return in
+//   R12 a pointer to a user-provided interrupt handler.
+
+  ALIGN 2
+
+_int0:
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+  // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+  mfsr    r12, AVR32_SR
+  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+  cp.w    r12, 110b
+  brlo    _int0_normal
+  lddsp   r12, sp[0 * 4]
+  stdsp   sp[6 * 4], r12
+  lddsp   r12, sp[1 * 4]
+  stdsp   sp[7 * 4], r12
+  lddsp   r12, sp[3 * 4]
+  sub     sp, -6 * 4
+  rete
+_int0_normal:
+#endif
+  mov     r12, 0  // Pass the int_lev parameter to the _get_interrupt_handler function.
+  mcall   __get_interrupt_handler
+  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
+  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+_int1:
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+  // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+  mfsr    r12, AVR32_SR
+  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+  cp.w    r12, 110b
+  brlo    _int1_normal
+  lddsp   r12, sp[0 * 4]
+  stdsp   sp[6 * 4], r12
+  lddsp   r12, sp[1 * 4]
+  stdsp   sp[7 * 4], r12
+  lddsp   r12, sp[3 * 4]
+  sub     sp, -6 * 4
+  rete
+_int1_normal:
+#endif
+  mov     r12, 1  // Pass the int_lev parameter to the _get_interrupt_handler function.
+  mcall   __get_interrupt_handler
+  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
+  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+_int2:
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+  // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+  mfsr    r12, AVR32_SR
+  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+  cp.w    r12, 110b
+  brlo    _int2_normal
+  lddsp   r12, sp[0 * 4]
+  stdsp   sp[6 * 4], r12
+  lddsp   r12, sp[1 * 4]
+  stdsp   sp[7 * 4], r12
+  lddsp   r12, sp[3 * 4]
+  sub     sp, -6 * 4
+  rete
+_int2_normal:
+#endif
+  mov     r12, 2  // Pass the int_lev parameter to the _get_interrupt_handler function.
+  mcall   __get_interrupt_handler
+  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
+  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+_int3:
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+  // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+  mfsr    r12, AVR32_SR
+  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+  cp.w    r12, 110b
+  brlo    _int3_normal
+  lddsp   r12, sp[0 * 4]
+  stdsp   sp[6 * 4], r12
+  lddsp   r12, sp[1 * 4]
+  stdsp   sp[7 * 4], r12
+  lddsp   r12, sp[3 * 4]
+  sub     sp, -6 * 4
+  rete
+_int3_normal:
+#endif
+  mov     r12, 3  // Pass the int_lev parameter to the _get_interrupt_handler function.
+  mcall   __get_interrupt_handler
+  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
+  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+
+// Constant data area.
+
+  ALIGN 2
+
+  // Import symbols.
+  EXTERN  SCALLYield
+  EXTERN  _get_interrupt_handler
+__SCALLYield:
+  DC32  SCALLYield
+__get_interrupt_handler:
+  DC32  _get_interrupt_handler
+
+  // Values to store in the interrupt priority registers for the various interrupt priority levels.
+  // The interrupt priority registers contain the interrupt priority level and
+  // the EVBA-relative interrupt vector offset.
+  PUBLIC  ipr_val
+ipr_val:
+  DC32  (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int0 - _evba),\
+        (INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int1 - _evba),\
+        (INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int2 - _evba),\
+        (INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int3 - _evba)
+
+
+  END
+
+
+//! \endverbatim
+//! @}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AVR32_UC3/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AVR32_UC3/port.c
new file mode 100644
index 0000000..61f941e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AVR32_UC3/port.c
@@ -0,0 +1,406 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief FreeRTOS port source for AVR32 UC3.
+ *
+ * - Compiler:           IAR EWAVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* AVR32 UC3 includes. */
+#include 
+#include 
+#include "gpio.h"
+
+#if configDBG
+	#include "usart.h"
+#endif
+
+#if( configTICK_USE_TC==1 )
+	#include "tc.h"
+#endif
+
+
+/* Constants required to setup the task context. */
+#define portINITIAL_SR            ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
+#define portINSTRUCTION_SIZE      ( ( StackType_t ) 0 )
+
+/* Each task maintains its own critical nesting variable. */
+#define portNO_CRITICAL_NESTING   ( ( uint32_t ) 0 )
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+#if( configTICK_USE_TC==0 )
+	static void prvScheduleNextTick( void );
+#else
+	static void prvClearTcInt( void );
+#endif
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Low-level initialization routine called during startup, before the main
+ * function.
+ */
+int __low_level_init(void)
+{
+	#if configHEAP_INIT
+		#pragma segment = "HEAP"
+		BaseType_t *pxMem;
+	#endif
+
+	/* Enable exceptions. */
+	ENABLE_ALL_EXCEPTIONS();
+
+	/* Initialize interrupt handling. */
+	INTC_init_interrupts();
+
+	#if configHEAP_INIT
+	{
+		/* Initialize the heap used by malloc. */
+		for( pxMem = __segment_begin( "HEAP" ); pxMem < ( BaseType_t * ) __segment_end( "HEAP" ); )
+		{
+			*pxMem++ = 0xA5A5A5A5;
+		}
+	}
+	#endif
+
+	/* Code section present if and only if the debug trace is activated. */
+	#if configDBG
+	{
+		static const gpio_map_t DBG_USART_GPIO_MAP =
+		{
+			{ configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
+			{ configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
+		};
+
+		static const usart_options_t DBG_USART_OPTIONS =
+		{
+			.baudrate = configDBG_USART_BAUDRATE,
+			.charlength = 8,
+			.paritytype = USART_NO_PARITY,
+			.stopbits = USART_1_STOPBIT,
+			.channelmode = USART_NORMAL_CHMODE
+		};
+
+		/* Initialize the USART used for the debug trace with the configured parameters. */
+		extern volatile avr32_usart_t *volatile stdio_usart_base;
+		stdio_usart_base = configDBG_USART;
+		gpio_enable_module( DBG_USART_GPIO_MAP,
+		                    sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );
+		usart_init_rs232(configDBG_USART, &DBG_USART_OPTIONS, configCPU_CLOCK_HZ);
+	}
+	#endif
+
+	/* Request initialization of data segments. */
+	return 1;
+}
+/*-----------------------------------------------------------*/
+
+/* Added as there is no such function in FreeRTOS. */
+void *pvPortRealloc( void *pv, size_t xWantedSize )
+{
+void *pvReturn;
+
+	vTaskSuspendAll();
+	{
+		pvReturn = realloc( pv, xWantedSize );
+	}
+	xTaskResumeAll();
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+/* The cooperative scheduler requires a normal IRQ service routine to
+simply increment the system tick. */
+/* The preemptive scheduler is defined as "naked" as the full context is saved
+on entry as part of the context switch. */
+#pragma shadow_registers = full   // Naked.
+static void vTick( void )
+{
+	/* Save the context of the interrupted task. */
+	portSAVE_CONTEXT_OS_INT();
+
+	#if( configTICK_USE_TC==1 )
+		/* Clear the interrupt flag. */
+		prvClearTcInt();
+	#else
+		/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
+		clock cycles from now. */
+		prvScheduleNextTick();
+	#endif
+
+	/* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
+	calls in a critical section . */
+	portENTER_CRITICAL();
+		xTaskIncrementTick();
+	portEXIT_CRITICAL();
+
+	/* Restore the context of the "elected task". */
+	portRESTORE_CONTEXT_OS_INT();
+}
+/*-----------------------------------------------------------*/
+
+#pragma shadow_registers = full   // Naked.
+void SCALLYield( void )
+{
+	/* Save the context of the interrupted task. */
+	portSAVE_CONTEXT_SCALL();
+	vTaskSwitchContext();
+	portRESTORE_CONTEXT_SCALL();
+}
+/*-----------------------------------------------------------*/
+
+/* The code generated by the GCC compiler uses the stack in different ways at
+different optimisation levels.  The interrupt flags can therefore not always
+be saved to the stack.  Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
+#pragma optimize = no_inline
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts */
+	portDISABLE_INTERRUPTS();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	 directly.  Increment ulCriticalNesting to keep a count of how many times
+	 portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+#pragma optimize = no_inline
+void vPortExitCritical( void )
+{
+	if(ulCriticalNesting > portNO_CRITICAL_NESTING)
+	{
+		ulCriticalNesting--;
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Enable all interrupt/exception. */
+			portENABLE_INTERRUPTS();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* When the task starts, it will expect to find the function parameter in R12. */
+	pxTopOfStack--;
+	*pxTopOfStack-- = ( StackType_t ) 0x08080808;					/* R8 */
+	*pxTopOfStack-- = ( StackType_t ) 0x09090909;					/* R9 */
+	*pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A;					/* R10 */
+	*pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B;					/* R11 */
+	*pxTopOfStack-- = ( StackType_t ) pvParameters;					/* R12 */
+	*pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF;					/* R14/LR */
+	*pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
+	*pxTopOfStack-- = ( StackType_t ) portINITIAL_SR;				/* SR */
+	*pxTopOfStack-- = ( StackType_t ) 0xFF0000FF;					/* R0 */
+	*pxTopOfStack-- = ( StackType_t ) 0x01010101;					/* R1 */
+	*pxTopOfStack-- = ( StackType_t ) 0x02020202;					/* R2 */
+	*pxTopOfStack-- = ( StackType_t ) 0x03030303;					/* R3 */
+	*pxTopOfStack-- = ( StackType_t ) 0x04040404;					/* R4 */
+	*pxTopOfStack-- = ( StackType_t ) 0x05050505;					/* R5 */
+	*pxTopOfStack-- = ( StackType_t ) 0x06060606;					/* R6 */
+	*pxTopOfStack-- = ( StackType_t ) 0x07070707;					/* R7 */
+	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING;			/* ulCriticalNesting */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	portRESTORE_CONTEXT();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the AVR32 port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
+clock cycles from now. */
+#if( configTICK_USE_TC==0 )
+	static void prvScheduleFirstTick(void)
+	{
+		uint32_t lCycles;
+
+		lCycles = Get_system_register(AVR32_COUNT);
+		lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+		// If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
+		// generation feature does not get disabled.
+		if(0 == lCycles)
+		{
+			lCycles++;
+		}
+		Set_system_register(AVR32_COMPARE, lCycles);
+	}
+	
+	#pragma optimize = no_inline
+	static void prvScheduleNextTick(void)
+	{
+		uint32_t lCycles, lCount;
+
+		lCycles = Get_system_register(AVR32_COMPARE);
+		lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+		// If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
+		// generation feature does not get disabled.
+		if(0 == lCycles)
+		{
+			lCycles++;
+		}
+		lCount = Get_system_register(AVR32_COUNT);
+		if( lCycles < lCount )
+		{		// We missed a tick, recover for the next.
+			lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+		}
+		Set_system_register(AVR32_COMPARE, lCycles);
+	}
+#else
+	#pragma optimize = no_inline
+	static void prvClearTcInt(void)
+	{
+		AVR32_TC.channel[configTICK_TC_CHANNEL].sr;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt(void)
+{
+	#if( configTICK_USE_TC==1 )
+
+		volatile avr32_tc_t *tc = &AVR32_TC;
+
+		// Options for waveform genration.
+		tc_waveform_opt_t waveform_opt =
+		{
+		.channel  = configTICK_TC_CHANNEL,             /* Channel selection. */
+
+		.bswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOB. */
+		.beevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOB. */
+		.bcpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOB. */
+		.bcpb     = TC_EVT_EFFECT_NOOP,                /* RB compare effect on TIOB. */
+
+		.aswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOA. */
+		.aeevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOA. */
+		.acpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOA: toggle. */
+		.acpa     = TC_EVT_EFFECT_NOOP,                /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
+
+		.wavsel   = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
+		.enetrg   = FALSE,                             /* External event trigger enable. */
+		.eevt     = 0,                                 /* External event selection. */
+		.eevtedg  = TC_SEL_NO_EDGE,                    /* External event edge selection. */
+		.cpcdis   = FALSE,                             /* Counter disable when RC compare. */
+		.cpcstop  = FALSE,                             /* Counter clock stopped with RC compare. */
+
+		.burst    = FALSE,                             /* Burst signal selection. */
+		.clki     = FALSE,                             /* Clock inversion. */
+		.tcclks   = TC_CLOCK_SOURCE_TC2                /* Internal source clock 2. */
+		};
+
+		tc_interrupt_t tc_interrupt =
+		{
+			.etrgs=0,
+			.ldrbs=0,
+			.ldras=0,
+			.cpcs =1,
+			.cpbs =0,
+			.cpas =0,
+			.lovrs=0,
+			.covfs=0,
+		};
+
+	#endif
+
+	/* Disable all interrupt/exception. */
+	portDISABLE_INTERRUPTS();
+
+	/* Register the compare interrupt handler to the interrupt controller and
+	enable the compare interrupt. */
+
+	#if( configTICK_USE_TC==1 )
+	{
+		INTC_register_interrupt((__int_handler)&vTick, configTICK_TC_IRQ, INT0);
+
+		/* Initialize the timer/counter. */
+		tc_init_waveform(tc, &waveform_opt);
+
+		/* Set the compare triggers.
+		Remember TC counter is 16-bits, so counting second is not possible!
+		That's why we configure it to count ms. */
+		tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );
+
+		tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
+
+		/* Start the timer/counter. */
+		tc_start(tc, configTICK_TC_CHANNEL);
+	}
+	#else
+	{
+		INTC_register_interrupt((__int_handler)&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
+		prvScheduleFirstTick();
+	}
+	#endif
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AVR32_UC3/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AVR32_UC3/portmacro.h
new file mode 100644
index 0000000..de74a38
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AVR32_UC3/portmacro.h
@@ -0,0 +1,654 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief FreeRTOS port header for AVR32 UC3.
+ *
+ * - Compiler:           IAR EWAVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+#include 
+#include "intc.h"
+#include "compiler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Type definitions. */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint32_t
+#define portBASE_TYPE   long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#define TASK_DELAY_MS(x)   ( (x)        /portTICK_PERIOD_MS )
+#define TASK_DELAY_S(x)    ( (x)*1000   /portTICK_PERIOD_MS )
+#define TASK_DELAY_MIN(x)  ( (x)*60*1000/portTICK_PERIOD_MS )
+
+#define configTICK_TC_IRQ             ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
+
+#if( configUSE_16_BIT_TICKS == 1 )
+  typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+  typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS      ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT       4
+#define portNOP()             {__asm__ __volatile__ ("nop");}
+/*-----------------------------------------------------------*/
+
+
+/*-----------------------------------------------------------*/
+
+/* INTC-specific. */
+#define DISABLE_ALL_EXCEPTIONS()    Disable_global_exception()
+#define ENABLE_ALL_EXCEPTIONS()     Enable_global_exception()
+
+#define DISABLE_ALL_INTERRUPTS()    Disable_global_interrupt()
+#define ENABLE_ALL_INTERRUPTS()     Enable_global_interrupt()
+
+#define DISABLE_INT_LEVEL(int_lev)  Disable_interrupt_level(int_lev)
+#define ENABLE_INT_LEVEL(int_lev)   Enable_interrupt_level(int_lev)
+
+
+/*
+ * Debug trace.
+ * Activated if and only if configDBG is nonzero.
+ * Prints a formatted string to stdout.
+ * The current source file name and line number are output with a colon before
+ * the formatted string.
+ * A carriage return and a linefeed are appended to the output.
+ * stdout is redirected to the USART configured by configDBG_USART.
+ * The parameters are the same as for the standard printf function.
+ * There is no return value.
+ * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
+ * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
+ */
+#if configDBG
+	#define portDBG_TRACE(...)												\
+	{																		\
+	  fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout);					\
+	  printf(__VA_ARGS__);													\
+	  fputs("\r\n", stdout);												\
+	}
+#else
+	#define portDBG_TRACE(...)
+#endif
+
+
+/* Critical section management. */
+#define portDISABLE_INTERRUPTS()  DISABLE_ALL_INTERRUPTS()
+#define portENABLE_INTERRUPTS()   ENABLE_ALL_INTERRUPTS()
+
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()      vPortEnterCritical();
+#define portEXIT_CRITICAL()       vPortExitCritical();
+
+
+/* Added as there is no such function in FreeRTOS. */
+extern void *pvPortRealloc( void *pv, size_t xSize );
+/*-----------------------------------------------------------*/
+
+
+/*=============================================================================================*/
+
+/*
+ * Restore Context for cases other than INTi.
+ */
+#define portRESTORE_CONTEXT()																\
+{																							\
+  extern volatile uint32_t ulCriticalNesting;										\
+  extern volatile void *volatile pxCurrentTCB;												\
+																							\
+  __asm__ __volatile__ (																	\
+    /* Set SP to point to new stack */														\
+    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")												\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")												\n\t"\
+    "ld.w    r0, r8[0]																		\n\t"\
+    "ld.w    sp, r0[0]																		\n\t"\
+																							\
+    /* Restore ulCriticalNesting variable */												\
+    "ld.w    r0, sp++																		\n\t"\
+    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")										\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")										\n\t"\
+    "st.w    r8[0], r0																		\n\t"\
+																							\
+    /* Restore R0..R7 */																	\
+    "ldm     sp++, r0-r7																	\n\t"\
+    /* R0-R7 should not be used below this line */											\
+    /* Skip PC and SR (will do it at the end) */											\
+    "sub     sp, -2*4																		\n\t"\
+    /* Restore R8..R12 and LR */															\
+    "ldm     sp++, r8-r12, lr																\n\t"\
+    /* Restore SR */																		\
+    "ld.w    r0, sp[-8*4]																	\n\t" /* R0 is modified, is restored later. */\
+    "mtsr    "ASTRINGZ(AVR32_SR)", r0														\n\t"\
+    /* Restore r0 */																		\
+    "ld.w    r0, sp[-9*4]																	\n\t"\
+    /* Restore PC */																		\
+    "ld.w    pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */			\
+  );																						\
+																							\
+  /* Force import of global symbols from assembly */										\
+  ulCriticalNesting;																		\
+  pxCurrentTCB;																				\
+}
+
+
+/*
+ * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
+ * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
+ *
+ * Had to make different versions because registers saved on the system stack
+ * are not the same between INT0..3 exceptions and the scall exception.
+ */
+
+// Task context stack layout:
+  // R8  (*)
+  // R9  (*)
+  // R10 (*)
+  // R11 (*)
+  // R12 (*)
+  // R14/LR (*)
+  // R15/PC (*)
+  // SR (*)
+  // R0
+  // R1
+  // R2
+  // R3
+  // R4
+  // R5
+  // R6
+  // R7
+  // ulCriticalNesting
+// (*) automatically done for INT0..INT3, but not for SCALL
+
+/*
+ * The ISR used for the scheduler tick depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+#if configUSE_PREEMPTION == 0
+
+/*
+ * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
+ */
+#define portSAVE_CONTEXT_OS_INT()															\
+{																							\
+  /* Save R0..R7 */																			\
+  __asm__ __volatile__ ("stm     --sp, r0-r7");												\
+																							\
+  /* With the cooperative scheduler, as there is no context switch by interrupt, */			\
+  /* there is also no context save. */														\
+}
+
+/*
+ * portRESTORE_CONTEXT_OS_INT() for Tick exception.
+ */
+#define portRESTORE_CONTEXT_OS_INT()														\
+{																							\
+  __asm__ __volatile__ (																	\
+    /* Restore R0..R7 */																	\
+    "ldm     sp++, r0-r7																	\n\t"\
+																							\
+    /* With the cooperative scheduler, as there is no context switch by interrupt, */		\
+    /* there is also no context restore. */													\
+    "rete"																					\
+  );																						\
+}
+
+#else
+
+/*
+ * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
+ */
+#define portSAVE_CONTEXT_OS_INT()																	\
+{																									\
+  extern volatile uint32_t ulCriticalNesting;												\
+  extern volatile void *volatile pxCurrentTCB;														\
+																									\
+  /* When we come here */																			\
+  /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */					\
+																									\
+  __asm__ __volatile__ (																			\
+    /* Save R0..R7 */																				\
+    "stm     --sp, r0-r7																			\n\t"\
+																									\
+    /* Save ulCriticalNesting variable  - R0 is overwritten */										\
+    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "st.w    --sp, r0																				\n\t"\
+																									\
+    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */	\
+    /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
+    /* level and allow other lower interrupt level to occur). */									\
+    /* In this case we don't want to do a task switch because we don't know what the stack */		\
+    /* currently looks like (we don't know what the interrupted interrupt handler was doing). */	\
+    /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */		\
+    /* will just be restoring the interrupt handler, no way!!! */									\
+    /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */					\
+    "ld.w    r0, sp[9*4]																			\n\t" /* Read SR in stack */\
+    "bfextu  r0, r0, 22, 3																			\n\t" /* Extract the mode bits to R0. */\
+    "cp.w    r0, 1																					\n\t" /* Compare the mode bits with supervisor mode(b'001) */\
+    "brhi    LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)"										\n\t"\
+																									\
+    /* Store SP in the first member of the structure pointed to by pxCurrentTCB */					\
+    /* NOTE: we don't enter a critical section here because all interrupt handlers */				\
+    /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */							\
+    /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */			\
+    /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */		\
+    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "st.w    r0[0], sp																				\n"\
+																									\
+    "LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":"												\
+  );																								\
+}
+
+/*
+ * portRESTORE_CONTEXT_OS_INT() for Tick exception.
+ */
+#define portRESTORE_CONTEXT_OS_INT()																\
+{																									\
+  extern volatile uint32_t ulCriticalNesting;												\
+  extern volatile void *volatile pxCurrentTCB;														\
+																									\
+  /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */		\
+  /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
+  /* level and allow other lower interrupt level to occur). */										\
+  /* In this case we don't want to do a task switch because we don't know what the stack */			\
+  /* currently looks like (we don't know what the interrupted interrupt handler was doing). */		\
+  /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */			\
+  /* will just be restoring the interrupt handler, no way!!! */										\
+  __asm__ __volatile__ (																			\
+    "ld.w    r0, sp[9*4]																			\n\t" /* Read SR in stack */\
+    "bfextu  r0, r0, 22, 3																			\n\t" /* Extract the mode bits to R0. */\
+    "cp.w    r0, 1																					\n\t" /* Compare the mode bits with supervisor mode(b'001) */\
+    "brhi    LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)										\
+  );																								\
+																									\
+  /* Else */																						\
+  /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */		\
+  /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
+  portENTER_CRITICAL();																				\
+  vTaskSwitchContext();																				\
+  portEXIT_CRITICAL();																				\
+																									\
+  /* Restore all registers */																		\
+																									\
+  __asm__ __volatile__ (																			\
+    /* Set SP to point to new stack */																\
+    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "ld.w    sp, r0[0]																				\n"\
+																									\
+    "LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":											\n\t"\
+																									\
+    /* Restore ulCriticalNesting variable */														\
+    "ld.w    r0, sp++																				\n\t"\
+    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "st.w    r8[0], r0																				\n\t"\
+																									\
+    /* Restore R0..R7 */																			\
+    "ldm     sp++, r0-r7																			\n\t"\
+																									\
+    /* Now, the stack should be R8..R12, LR, PC and SR */											\
+    "rete"																							\
+  );																								\
+																									\
+  /* Force import of global symbols from assembly */												\
+  ulCriticalNesting;																				\
+  pxCurrentTCB;																						\
+}
+
+#endif
+
+
+/*
+ * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
+ *
+ * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
+ *
+ */
+#define portSAVE_CONTEXT_SCALL()																	\
+{																									\
+  extern volatile uint32_t ulCriticalNesting;												\
+  extern volatile void *volatile pxCurrentTCB;														\
+																									\
+  /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */				\
+  /* If SR[M2:M0] == 001 */																			\
+  /*    PC and SR are on the stack.  */																\
+  /* Else (other modes) */																			\
+  /*    Nothing on the stack. */																	\
+																									\
+  /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */				\
+  /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */				\
+  /* in an interrupt|exception handler. */															\
+																									\
+  __asm__ __volatile__ (																			\
+    /* in order to save R0-R7 */																	\
+    "sub     sp, 6*4																				\n\t"\
+    /* Save R0..R7 */																				\
+    "stm     --sp, r0-r7																			\n\t"\
+																									\
+    /* in order to save R8-R12 and LR */															\
+    /* do not use SP if interrupts occurs, SP must be left at bottom of stack */					\
+    "sub     r7, sp,-16*4																			\n\t"\
+    /* Copy PC and SR in other places in the stack. */												\
+    "ld.w    r0, r7[-2*4]																			\n\t" /* Read SR */\
+    "st.w    r7[-8*4], r0																			\n\t" /* Copy SR */\
+    "ld.w    r0, r7[-1*4]																			\n\t" /* Read PC */\
+    "st.w    r7[-7*4], r0																			\n\t" /* Copy PC */\
+																									\
+    /* Save R8..R12 and LR on the stack. */															\
+    "stm     --r7, r8-r12, lr																		\n\t"\
+																									\
+    /* Arriving here we have the following stack organizations: */									\
+    /* R8..R12, LR, PC, SR, R0..R7. */																\
+																									\
+    /* Now we can finalize the save. */																\
+																									\
+    /* Save ulCriticalNesting variable  - R0 is overwritten */										\
+    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "st.w    --sp, r0"																				\
+  );																								\
+																									\
+  /* Disable the its which may cause a context switch (i.e. cause a change of */					\
+  /* pxCurrentTCB). */																				\
+  /* Basically, all accesses to the pxCurrentTCB structure should be put in a */					\
+  /* critical section because it is a global structure. */											\
+  portENTER_CRITICAL();																				\
+																									\
+  /* Store SP in the first member of the structure pointed to by pxCurrentTCB */					\
+  __asm__ __volatile__ (																			\
+    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "st.w    r0[0], sp"																				\
+  );																								\
+}
+
+/*
+ * portRESTORE_CONTEXT() for SupervisorCALL exception.
+ */
+#define portRESTORE_CONTEXT_SCALL()																	\
+{																									\
+  extern volatile uint32_t ulCriticalNesting;												\
+  extern volatile void *volatile pxCurrentTCB;														\
+																									\
+  /* Restore all registers */																		\
+																									\
+  /* Set SP to point to new stack */																\
+  __asm__ __volatile__ (																			\
+    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "ld.w    sp, r0[0]"																				\
+  );																								\
+																									\
+  /* Leave pxCurrentTCB variable access critical section */											\
+  portEXIT_CRITICAL();																				\
+																									\
+  __asm__ __volatile__ (																			\
+    /* Restore ulCriticalNesting variable */														\
+    "ld.w    r0, sp++																				\n\t"\
+    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "st.w    r8[0], r0																				\n\t"\
+																									\
+    /* skip PC and SR */																			\
+    /* do not use SP if interrupts occurs, SP must be left at bottom of stack */					\
+    "sub     r7, sp, -10*4																			\n\t"\
+    /* Restore r8-r12 and LR */																		\
+    "ldm     r7++, r8-r12, lr																		\n\t"\
+																									\
+    /* RETS will take care of the extra PC and SR restore. */										\
+    /* So, we have to prepare the stack for this. */												\
+    "ld.w    r0, r7[-8*4]																			\n\t" /* Read SR */\
+    "st.w    r7[-2*4], r0																			\n\t" /* Copy SR */\
+    "ld.w    r0, r7[-7*4]																			\n\t" /* Read PC */\
+    "st.w    r7[-1*4], r0																			\n\t" /* Copy PC */\
+																									\
+    /* Restore R0..R7 */																			\
+    "ldm     sp++, r0-r7																			\n\t"\
+																									\
+    "sub     sp, -6*4																				\n\t"\
+																									\
+    "rets"																							\
+  );																								\
+																									\
+  /* Force import of global symbols from assembly */												\
+  ulCriticalNesting;																				\
+  pxCurrentTCB;																						\
+}
+
+
+/*
+ * The ISR used depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+#if configUSE_PREEMPTION == 0
+
+/*
+ * ISR entry and exit macros.  These are only required if a task switch
+ * is required from the ISR.
+ */
+#define portENTER_SWITCHING_ISR()																	\
+{																									\
+  /* Save R0..R7 */																					\
+  __asm__ __volatile__ ("stm     --sp, r0-r7");														\
+																									\
+  /* With the cooperative scheduler, as there is no context switch by interrupt, */					\
+  /* there is also no context save. */																\
+}
+
+/*
+ * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
+ */
+#define portEXIT_SWITCHING_ISR()																	\
+{																									\
+  __asm__ __volatile__ (																			\
+    /* Restore R0..R7 */																			\
+    "ldm     sp++, r0-r7																			\n\t"\
+																									\
+    /* With the cooperative scheduler, as there is no context switch by interrupt, */				\
+    /* there is also no context restore. */															\
+    "rete"																							\
+  );																								\
+}
+
+#else
+
+/*
+ * ISR entry and exit macros.  These are only required if a task switch
+ * is required from the ISR.
+ */
+#define portENTER_SWITCHING_ISR()																	\
+{																									\
+  extern volatile uint32_t ulCriticalNesting;												\
+  extern volatile void *volatile pxCurrentTCB;														\
+																									\
+  /* When we come here */																			\
+  /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */					\
+																									\
+  __asm__ __volatile__ (																			\
+    /* Save R0..R7 */																				\
+    "stm     --sp, r0-r7																			\n\t"\
+																									\
+    /* Save ulCriticalNesting variable  - R0 is overwritten */										\
+    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "st.w    --sp, r0																				\n\t"\
+																									\
+    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */	\
+    /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
+    /* level and allow other lower interrupt level to occur). */									\
+    /* In this case we don't want to do a task switch because we don't know what the stack */		\
+    /* currently looks like (we don't know what the interrupted interrupt handler was doing). */	\
+    /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */		\
+    /* will just be restoring the interrupt handler, no way!!! */									\
+    /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */					\
+    "ld.w    r0, sp[9*4]																			\n\t" /* Read SR in stack */\
+    "bfextu  r0, r0, 22, 3																			\n\t" /* Extract the mode bits to R0. */\
+    "cp.w    r0, 1																					\n\t" /* Compare the mode bits with supervisor mode(b'001) */\
+    "brhi    LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)"										\n\t"\
+																									\
+    /* Store SP in the first member of the structure pointed to by pxCurrentTCB */					\
+    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "st.w    r0[0], sp																				\n"\
+																									\
+    "LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":"												\
+  );																								\
+}
+
+
+/*
+ * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
+ */
+#define portEXIT_SWITCHING_ISR()																	\
+{																									\
+  extern volatile uint32_t ulCriticalNesting;												\
+  extern volatile void *volatile pxCurrentTCB;														\
+																									\
+  __asm__ __volatile__ (																			\
+    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */	\
+    /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
+    /* level and allow other lower interrupt level to occur). */									\
+    /* In this case it's of no use to switch context and restore a new SP because we purposedly */	\
+    /* did not previously save SP in its TCB. */													\
+    "ld.w    r0, sp[9*4]																			\n\t" /* Read SR in stack */\
+    "bfextu  r0, r0, 22, 3																			\n\t" /* Extract the mode bits to R0. */\
+    "cp.w    r0, 1																					\n\t" /* Compare the mode bits with supervisor mode(b'001) */\
+    "brhi    LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)"									\n\t"\
+																									\
+    /* If a switch is required then we just need to call */											\
+    /* vTaskSwitchContext() as the context has already been */										\
+    /* saved. */																					\
+    "cp.w    r12, 1																					\n\t" /* Check if Switch context is required. */\
+    "brne    LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":C"										\
+  );																								\
+																									\
+  /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
+  portENTER_CRITICAL();																				\
+  vTaskSwitchContext();																				\
+  portEXIT_CRITICAL();																				\
+																									\
+  __asm__ __volatile__ (																			\
+    "LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":												\n\t"\
+    /* Restore the context of which ever task is now the highest */									\
+    /* priority that is ready to run. */															\
+																									\
+    /* Restore all registers */																		\
+																									\
+    /* Set SP to point to new stack */																\
+    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "ld.w    sp, r0[0]																				\n"\
+																									\
+    "LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":											\n\t"\
+																									\
+    /* Restore ulCriticalNesting variable */														\
+    "ld.w    r0, sp++																				\n\t"\
+    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "st.w    r8[0], r0																				\n\t"\
+																									\
+    /* Restore R0..R7 */																			\
+    "ldm     sp++, r0-r7																			\n\t"\
+																									\
+    /* Now, the stack should be R8..R12, LR, PC and SR  */											\
+    "rete"																							\
+  );																								\
+																									\
+  /* Force import of global symbols from assembly */												\
+  ulCriticalNesting;																				\
+  pxCurrentTCB;																						\
+}
+
+#endif
+
+
+#define portYIELD()                 {__asm__ __volatile__ ("scall");}
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AVR32_UC3/read.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AVR32_UC3/read.c
new file mode 100644
index 0000000..30b5ee8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AVR32_UC3/read.c
@@ -0,0 +1,93 @@
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief System-specific implementation of the \ref __read function used by
+          the standard library.
+ *
+ * - Compiler:           IAR EWAVR32
+ * - Supported devices:  All AVR32 devices with a USART module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include 
+#include 
+#include "usart.h"
+
+
+_STD_BEGIN
+
+
+#pragma module_name = "?__read"
+
+
+extern volatile avr32_usart_t *volatile stdio_usart_base;
+
+
+/*! \brief Reads a number of bytes, at most \a size, into the memory area
+ *         pointed to by \a buffer.
+ *
+ * \param handle File handle to read from.
+ * \param buffer Pointer to buffer to write read bytes to.
+ * \param size Number of bytes to read.
+ *
+ * \return The number of bytes read, \c 0 at the end of the file, or
+ *         \c _LLIO_ERROR on failure.
+ */
+size_t __read(int handle, uint8_t *buffer, size_t size)
+{
+  int nChars = 0;
+
+  // This implementation only reads from stdin.
+  // For all other file handles, it returns failure.
+  if (handle != _LLIO_STDIN)
+  {
+    return _LLIO_ERROR;
+  }
+
+  for (; size > 0; --size)
+  {
+    int c = usart_getchar(stdio_usart_base);
+    if (c < 0)
+      break;
+
+    *buffer++ = c;
+    ++nChars;
+  }
+
+  return nChars;
+}
+
+
+_STD_END
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AVR32_UC3/write.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AVR32_UC3/write.c
new file mode 100644
index 0000000..859487e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AVR32_UC3/write.c
@@ -0,0 +1,103 @@
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief System-specific implementation of the \ref __write function used by
+          the standard library.
+ *
+ * - Compiler:           IAR EWAVR32
+ * - Supported devices:  All AVR32 devices with a USART module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include 
+#include 
+#include "usart.h"
+
+
+_STD_BEGIN
+
+
+#pragma module_name = "?__write"
+
+
+//! Pointer to the base of the USART module instance to use for stdio.
+__no_init volatile avr32_usart_t *volatile stdio_usart_base;
+
+
+/*! \brief Writes a number of bytes, at most \a size, from the memory area
+ *         pointed to by \a buffer.
+ *
+ * If \a buffer is zero then \ref __write performs flushing of internal buffers,
+ * if any. In this case, \a handle can be \c -1 to indicate that all handles
+ * should be flushed.
+ *
+ * \param handle File handle to write to.
+ * \param buffer Pointer to buffer to read bytes to write from.
+ * \param size Number of bytes to write.
+ *
+ * \return The number of bytes written, or \c _LLIO_ERROR on failure.
+ */
+size_t __write(int handle, const uint8_t *buffer, size_t size)
+{
+  size_t nChars = 0;
+
+  if (buffer == 0)
+  {
+    // This means that we should flush internal buffers.
+    return 0;
+  }
+
+  // This implementation only writes to stdout and stderr.
+  // For all other file handles, it returns failure.
+  if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR)
+  {
+    return _LLIO_ERROR;
+  }
+
+  for (; size != 0; --size)
+  {
+    if (usart_putchar(stdio_usart_base, *buffer++) < 0)
+    {
+      return _LLIO_ERROR;
+    }
+
+    ++nChars;
+  }
+
+  return nChars;
+}
+
+
+_STD_END
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h
new file mode 100644
index 0000000..8f9ddb4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h
@@ -0,0 +1,1914 @@
+// ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ----------------------------------------------------------------------------
+//  The software is delivered "AS IS" without warranty or condition of any
+//  kind, either express, implied or statutory. This includes without
+//  limitation any warranty or condition with respect to merchantability or
+//  fitness for any particular purpose, or against the infringements of
+//  intellectual property rights of others.
+// ----------------------------------------------------------------------------
+// File Name           : AT91SAM7S64.h
+// Object              : AT91SAM7S64 definitions
+// Generated           : AT91 SW Application Group  07/16/2004 (07:43:08)
+// 
+// CVS Reference       : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004//
+// CVS Reference       : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004//
+// CVS Reference       : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004//
+// CVS Reference       : /UDP_1765B.pl/1.3/Fri Aug  2 14:45:38 2002//
+// CVS Reference       : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
+// CVS Reference       : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//
+// CVS Reference       : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
+// CVS Reference       : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//
+// CVS Reference       : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004//
+// CVS Reference       : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003//
+// CVS Reference       : /SSC_1762A.pl/1.2/Fri Nov  8 13:26:40 2002//
+// CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+// CVS Reference       : /TWI_1761B.pl/1.4/Fri Feb  7 10:30:08 2003//
+// CVS Reference       : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002//
+// CVS Reference       : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003//
+// CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+// ----------------------------------------------------------------------------
+
+#ifndef AT91SAM7S64_H
+#define AT91SAM7S64_H
+
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYSC {
+	AT91_REG	 SYSC_AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 SYSC_AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 SYSC_AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 SYSC_AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 SYSC_AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 SYSC_AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 SYSC_AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 SYSC_AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 SYSC_AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 SYSC_AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 SYSC_AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 SYSC_AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 SYSC_AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 SYSC_AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 SYSC_AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 SYSC_AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 SYSC_AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 SYSC_AIC_FFSR; 	// Fast Forcing Status Register
+	AT91_REG	 Reserved2[45]; 	// 
+	AT91_REG	 SYSC_DBGU_CR; 	// Control Register
+	AT91_REG	 SYSC_DBGU_MR; 	// Mode Register
+	AT91_REG	 SYSC_DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 SYSC_DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SYSC_DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 SYSC_DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 SYSC_DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 SYSC_DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 SYSC_DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved3[7]; 	// 
+	AT91_REG	 SYSC_DBGU_C1R; 	// Chip ID1 Register
+	AT91_REG	 SYSC_DBGU_C2R; 	// Chip ID2 Register
+	AT91_REG	 SYSC_DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved4[45]; 	// 
+	AT91_REG	 SYSC_DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 SYSC_DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 SYSC_DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SYSC_DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 SYSC_DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SYSC_DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SYSC_DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SYSC_DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SYSC_DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SYSC_DBGU_PTSR; 	// PDC Transfer Status Register
+	AT91_REG	 Reserved5[54]; 	// 
+	AT91_REG	 SYSC_PIOA_PER; 	// PIO Enable Register
+	AT91_REG	 SYSC_PIOA_PDR; 	// PIO Disable Register
+	AT91_REG	 SYSC_PIOA_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved6[1]; 	// 
+	AT91_REG	 SYSC_PIOA_OER; 	// Output Enable Register
+	AT91_REG	 SYSC_PIOA_ODR; 	// Output Disable Registerr
+	AT91_REG	 SYSC_PIOA_OSR; 	// Output Status Register
+	AT91_REG	 Reserved7[1]; 	// 
+	AT91_REG	 SYSC_PIOA_IFER; 	// Input Filter Enable Register
+	AT91_REG	 SYSC_PIOA_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 SYSC_PIOA_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved8[1]; 	// 
+	AT91_REG	 SYSC_PIOA_SODR; 	// Set Output Data Register
+	AT91_REG	 SYSC_PIOA_CODR; 	// Clear Output Data Register
+	AT91_REG	 SYSC_PIOA_ODSR; 	// Output Data Status Register
+	AT91_REG	 SYSC_PIOA_PDSR; 	// Pin Data Status Register
+	AT91_REG	 SYSC_PIOA_IER; 	// Interrupt Enable Register
+	AT91_REG	 SYSC_PIOA_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SYSC_PIOA_IMR; 	// Interrupt Mask Register
+	AT91_REG	 SYSC_PIOA_ISR; 	// Interrupt Status Register
+	AT91_REG	 SYSC_PIOA_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 SYSC_PIOA_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 SYSC_PIOA_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved9[1]; 	// 
+	AT91_REG	 SYSC_PIOA_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 SYSC_PIOA_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 SYSC_PIOA_PPUSR; 	// Pad Pull-up Status Register
+	AT91_REG	 Reserved10[1]; 	// 
+	AT91_REG	 SYSC_PIOA_ASR; 	// Select A Register
+	AT91_REG	 SYSC_PIOA_BSR; 	// Select B Register
+	AT91_REG	 SYSC_PIOA_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved11[9]; 	// 
+	AT91_REG	 SYSC_PIOA_OWER; 	// Output Write Enable Register
+	AT91_REG	 SYSC_PIOA_OWDR; 	// Output Write Disable Register
+	AT91_REG	 SYSC_PIOA_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved12[469]; 	// 
+	AT91_REG	 SYSC_PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 SYSC_PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 SYSC_PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved13[1]; 	// 
+	AT91_REG	 SYSC_PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 SYSC_PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 SYSC_PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved14[1]; 	// 
+	AT91_REG	 SYSC_PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 SYSC_PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved15[1]; 	// 
+	AT91_REG	 SYSC_PMC_PLLR; 	// PLL Register
+	AT91_REG	 SYSC_PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved16[3]; 	// 
+	AT91_REG	 SYSC_PMC_PCKR[8]; 	// Programmable Clock Register
+	AT91_REG	 SYSC_PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 SYSC_PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SYSC_PMC_SR; 	// Status Register
+	AT91_REG	 SYSC_PMC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved17[36]; 	// 
+	AT91_REG	 SYSC_RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 SYSC_RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 SYSC_RSTC_RMR; 	// Reset Mode Register
+	AT91_REG	 Reserved18[5]; 	// 
+	AT91_REG	 SYSC_RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 SYSC_RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 SYSC_RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 SYSC_RTTC_RTSR; 	// Real-time Status Register
+	AT91_REG	 SYSC_PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 SYSC_PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 SYSC_PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 SYSC_PITC_PIIR; 	// Period Interval Image Register
+	AT91_REG	 SYSC_WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 SYSC_WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 SYSC_WDTC_WDSR; 	// Watchdog Status Register
+	AT91_REG	 Reserved19[5]; 	// 
+	AT91_REG	 SYSC_SYSC_VRPM; 	// Voltage Regulator Power Mode Register
+} AT91S_SYSC, *AT91PS_SYSC;
+
+// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- 
+#define AT91C_SYSC_PSTDBY     ((unsigned int) 0x1 <<  0) // (SYSC) Voltage Regulator Power Mode
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       ((unsigned int) 0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    ((unsigned int) 0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved0[7]; 	// 
+	AT91_REG	 DBGU_C1R; 	// Chip ID1 Register
+	AT91_REG	 DBGU_C2R; 	// Chip ID2 Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved1[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral Data Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
+	AT91_REG	 PDC_RCR; 	// Receive Counter Register
+	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
+	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+	AT91_REG	 PIO_PER; 	// PIO Enable Register
+	AT91_REG	 PIO_PDR; 	// PIO Disable Register
+	AT91_REG	 PIO_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PIO_OER; 	// Output Enable Register
+	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIO_OSR; 	// Output Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PIO_SODR; 	// Set Output Data Register
+	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved3[1]; 	// 
+	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIO_PPUSR; 	// Pad Pull-up Status Register
+	AT91_REG	 Reserved4[1]; 	// 
+	AT91_REG	 PIO_ASR; 	// Select A Register
+	AT91_REG	 PIO_BSR; 	// Select B Register
+	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved5[9]; 	// 
+	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
+	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 CKGR_PLLR; 	// PLL Register
+} AT91S_CKGR, *AT91PS_CKGR;
+
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
+#define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
+#define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
+#define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved3[3]; 	// 
+	AT91_REG	 PMC_PCKR[8]; 	// Programmable Clock Register
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RSTC {
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
+
+// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_SYSC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_SYSC_ICERST     ((unsigned int) 0x1 <<  1) // (RSTC) ICE Interface Reset
+#define AT91C_SYSC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_SYSC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
+#define AT91C_SYSC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
+// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_SYSC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_SYSC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brown-out Detection Status
+#define AT91C_SYSC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_SYSC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define 	AT91C_SYSC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_SYSC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_SYSC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define 	AT91C_SYSC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brown-out Reset.
+#define AT91C_SYSC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_SYSC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_SYSC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_SYSC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_SYSC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
+#define AT91C_SYSC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RTTC {
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+
+// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_SYSC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_SYSC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_SYSC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_SYSC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_SYSC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
+// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_SYSC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_SYSC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_SYSC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PITC {
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+
+// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_SYSC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_SYSC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_SYSC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_SYSC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_SYSC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_SYSC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_WDTC {
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+
+// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_SYSC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
+// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_SYSC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_SYSC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_SYSC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_SYSC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_SYSC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_SYSC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_SYSC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_SYSC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_SYSC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_SYSC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+	AT91_REG	 MC_RCR; 	// MC Remap Control Register
+	AT91_REG	 MC_ASR; 	// MC Abort Status Register
+	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
+	AT91_REG	 Reserved0[21]; 	// 
+	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
+	AT91_REG	 MC_FCR; 	// MC Flash Command Register
+	AT91_REG	 MC_FSR; 	// MC Flash Status Register
+} AT91S_MC, *AT91PS_MC;
+
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
+#define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
+#define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
+#define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
+#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
+#define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
+#define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
+#define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
+#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
+#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
+#define 	AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
+#define 	AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
+#define 	AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
+#define 	AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
+#define 	AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define 	AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define 	AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define 	AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
+#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+	AT91_REG	 SPI_CR; 	// Control Register
+	AT91_REG	 SPI_MR; 	// Mode Register
+	AT91_REG	 SPI_RDR; 	// Receive Data Register
+	AT91_REG	 SPI_TDR; 	// Transmit Data Register
+	AT91_REG	 SPI_SR; 	// Status Register
+	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
+	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
+	AT91_REG	 Reserved1[48]; 	// 
+	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
+	AT91_REG	 SPI_RCR; 	// Receive Counter Register
+	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
+	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// *****************************************************************************
+typedef struct _AT91S_ADC {
+	AT91_REG	 ADC_CR; 	// ADC Control Register
+	AT91_REG	 ADC_MR; 	// ADC Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
+	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
+	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
+	AT91_REG	 ADC_SR; 	// ADC Status Register
+	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
+	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
+	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
+	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
+	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
+	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
+	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
+	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
+	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
+	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
+	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
+	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
+	AT91_REG	 Reserved1[44]; 	// 
+	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
+	AT91_REG	 ADC_RCR; 	// Receive Counter Register
+	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
+	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
+
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
+#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
+#define 	AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define 	AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
+#define 	AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
+#define 	AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
+#define 	AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
+#define 	AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
+#define 	AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
+#define 	AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
+#define 	AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
+#define 	AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
+#define 	AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define 	AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
+#define 	AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
+// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
+#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
+#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
+#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
+#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
+#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
+#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
+#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
+// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+	AT91_REG	 SSC_CR; 	// Control Register
+	AT91_REG	 SSC_CMR; 	// Clock Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
+	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
+	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
+	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
+	AT91_REG	 SSC_RHR; 	// Receive Holding Register
+	AT91_REG	 SSC_THR; 	// Transmit Holding Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
+	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
+	AT91_REG	 SSC_RC0R; 	// Receive Compare 0 Register
+	AT91_REG	 SSC_RC1R; 	// Receive Compare 1 Register
+	AT91_REG	 SSC_SR; 	// Status Register
+	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
+	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved2[44]; 	// 
+	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
+	AT91_REG	 SSC_RCR; 	// Receive Counter Register
+	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
+	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_CKG         ((unsigned int) 0x3 <<  6) // (SSC) Receive/Transmit Clock Gating Selection
+#define 	AT91C_SSC_CKG_NONE                 ((unsigned int) 0x0 <<  6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
+#define 	AT91C_SSC_CKG_LOW                  ((unsigned int) 0x1 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF Low
+#define 	AT91C_SSC_CKG_HIGH                 ((unsigned int) 0x2 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF High
+#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STOP        ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection
+#define AT91C_SSC_STTOUT      ((unsigned int) 0x1 << 15) // (SSC) Receive/Transmit Start Output Selection
+#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_CP0         ((unsigned int) 0x1 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_CP1         ((unsigned int) 0x1 <<  9) // (SSC) Compare 1
+#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+	AT91_REG	 US_CR; 	// Control Register
+	AT91_REG	 US_MR; 	// Mode Register
+	AT91_REG	 US_IER; 	// Interrupt Enable Register
+	AT91_REG	 US_IDR; 	// Interrupt Disable Register
+	AT91_REG	 US_IMR; 	// Interrupt Mask Register
+	AT91_REG	 US_CSR; 	// Channel Status Register
+	AT91_REG	 US_RHR; 	// Receiver Holding Register
+	AT91_REG	 US_THR; 	// Transmitter Holding Register
+	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
+	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
+	AT91_REG	 Reserved0[5]; 	// 
+	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
+	AT91_REG	 US_NER; 	// Nb Errors Register
+	AT91_REG	 US_XXR; 	// XON_XOFF Register
+	AT91_REG	 US_IF; 	// IRDA_FILTER Register
+	AT91_REG	 Reserved1[44]; 	// 
+	AT91_REG	 US_RPR; 	// Receive Pointer Register
+	AT91_REG	 US_RCR; 	// Receive Counter Register
+	AT91_REG	 US_TPR; 	// Transmit Pointer Register
+	AT91_REG	 US_TCR; 	// Transmit Counter Register
+	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (USART) Reset Status Bits
+#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+	AT91_REG	 TWI_CR; 	// Control Register
+	AT91_REG	 TWI_MMR; 	// Master Mode Register
+	AT91_REG	 TWI_SMR; 	// Slave Mode Register
+	AT91_REG	 TWI_IADR; 	// Internal Address Register
+	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
+	AT91_REG	 Reserved0[3]; 	// 
+	AT91_REG	 TWI_SR; 	// Status Register
+	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
+	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TWI_RHR; 	// Receive Holding Register
+	AT91_REG	 TWI_THR; 	// Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
+
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SVEN        ((unsigned int) 0x1 <<  4) // (TWI) TWI Slave Transfer Enabled
+#define AT91C_TWI_SVDIS       ((unsigned int) 0x1 <<  5) // (TWI) TWI Slave Transfer Disabled
+#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
+// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- 
+#define AT91C_TWI_SADR        ((unsigned int) 0x7F << 16) // (TWI) Slave Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_SVREAD      ((unsigned int) 0x1 <<  3) // (TWI) Slave Read
+#define AT91C_TWI_SVACC       ((unsigned int) 0x1 <<  4) // (TWI) Slave Access
+#define AT91C_TWI_GCACC       ((unsigned int) 0x1 <<  5) // (TWI) General Call Access
+#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
+#define AT91C_TWI_ARBLST      ((unsigned int) 0x1 <<  9) // (TWI) Arbitration Lost
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+	AT91_REG	 TC_CCR; 	// Channel Control Register
+	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TC_CV; 	// Counter Value
+	AT91_REG	 TC_RA; 	// Register A
+	AT91_REG	 TC_RB; 	// Register B
+	AT91_REG	 TC_RC; 	// Register C
+	AT91_REG	 TC_SR; 	// Status Register
+	AT91_REG	 TC_IER; 	// Interrupt Enable Register
+	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_NONE                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_RISING               ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_FALLING              ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_BOTH                 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) 
+#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRCS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_ETRGS        ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+	AT91S_TC	 TCB_TC0; 	// TC Channel 0
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91S_TC	 TCB_TC1; 	// TC Channel 1
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91S_TC	 TCB_TC2; 	// TC Channel 2
+	AT91_REG	 Reserved2[4]; 	// 
+	AT91_REG	 TCB_BCR; 	// TC Block Control Register
+	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x1 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x1 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x1 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA2                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC_CH {
+	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
+	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
+	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
+	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
+	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
+	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
+
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define 	AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH) 
+#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC {
+	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
+	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
+	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
+	AT91_REG	 PWMC_SR; 	// PWMC Status Register
+	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
+	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
+	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
+	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
+	AT91_REG	 Reserved0[55]; 	// 
+	AT91_REG	 PWMC_VR; 	// PWMC Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_PWMC_CH	 PWMC_CH[32]; 	// PWMC Channel 0
+} AT91S_PWMC, *AT91PS_PWMC;
+
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
+#define 	AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC) 
+#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define 	AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC) 
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
+#define AT91C_PWMC_CHID4      ((unsigned int) 0x1 <<  4) // (PWMC) Channel ID 4
+#define AT91C_PWMC_CHID5      ((unsigned int) 0x1 <<  5) // (PWMC) Channel ID 5
+#define AT91C_PWMC_CHID6      ((unsigned int) 0x1 <<  6) // (PWMC) Channel ID 6
+#define AT91C_PWMC_CHID7      ((unsigned int) 0x1 <<  7) // (PWMC) Channel ID 7
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+	AT91_REG	 UDP_NUM; 	// Frame Number Register
+	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
+	AT91_REG	 UDP_FADDR; 	// Function Address Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
+	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
+	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
+	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
+	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 UDP_CSR[8]; 	// Endpoint Control and Status Register
+	AT91_REG	 UDP_FDR[8]; 	// Endpoint FIFO Data Register
+} AT91S_UDP, *AT91PS_UDP;
+
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  2) // (UDP) Remote Wake Up Enable
+#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_EPINT6      ((unsigned int) 0x1 <<  6) // (UDP) Endpoint 6 Interrupt
+#define AT91C_UDP_EPINT7      ((unsigned int) 0x1 <<  7) // (UDP) Endpoint 7 Interrupt
+#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
+#define AT91C_UDP_EP6         ((unsigned int) 0x1 <<  6) // (UDP) Reset Endpoint 6
+#define AT91C_UDP_EP7         ((unsigned int) 0x1 <<  7) // (UDP) Reset Endpoint 7
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM7S64
+// *****************************************************************************
+// ========== Register definition for SYSC peripheral ========== 
+#define AT91C_SYSC_SYSC_VRPM ((AT91_REG *) 	0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_ICCR  ((AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_IECR  ((AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_SMR   ((AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_ISCR  ((AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_EOICR ((AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_DCR   ((AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_FFER  ((AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_SVR   ((AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_SPU   ((AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
+#define AT91C_AIC_FFDR  ((AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_FVR   ((AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_FFSR  ((AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_IMR   ((AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_ISR   ((AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IVR   ((AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_IDCR  ((AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_CISR  ((AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IPR   ((AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_C2R  ((AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID2 Register
+#define AT91C_DBGU_THR  ((AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_CSR  ((AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_IDR  ((AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_MR   ((AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_C1R  ((AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID1 Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_RHR  ((AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IMR  ((AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_IER  ((AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
+#define AT91C_DBGU_CR   ((AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_TNCR ((AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_RCR  ((AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_TCR  ((AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RPR  ((AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_TPR  ((AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_IMR  ((AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_IER  ((AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_ISR  ((AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PER  ((AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_PSR  ((AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
+#define AT91C_PIOA_OER  ((AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_BSR  ((AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_ODR  ((AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_IFDR ((AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_ASR  ((AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 	0xFFFFF468) // (PIOA) Pad Pull-up Status Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_SODR ((AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_OSR  ((AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_IDR  ((AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_PLLR ((AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+#define AT91C_CKGR_MOR  ((AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_SCSR  ((AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_SCER  ((AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR   ((AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IDR   ((AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_PCDR  ((AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCDR  ((AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_SR    ((AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
+#define AT91C_PMC_IER   ((AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PCER  ((AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCSR  ((AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_MCFR  ((AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_PCKR  ((AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RSR  ((AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
+#define AT91C_RSTC_RMR  ((AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RCR  ((AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR ((AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTAR ((AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
+#define AT91C_RTTC_RTVR ((AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTMR ((AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIIR ((AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PISR ((AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIVR ((AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PIMR ((AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDMR ((AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
+#define AT91C_WDTC_WDSR ((AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDCR ((AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
+// ========== Register definition for MC peripheral ========== 
+#define AT91C_MC_FCR    ((AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_ASR    ((AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_FSR    ((AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR    ((AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
+#define AT91C_MC_AASR   ((AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_RCR    ((AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
+// ========== Register definition for PDC_SPI peripheral ========== 
+#define AT91C_SPI_PTCR  ((AT91_REG *) 	0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
+#define AT91C_SPI_TNPR  ((AT91_REG *) 	0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
+#define AT91C_SPI_RNPR  ((AT91_REG *) 	0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
+#define AT91C_SPI_TPR   ((AT91_REG *) 	0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
+#define AT91C_SPI_RPR   ((AT91_REG *) 	0xFFFE0100) // (PDC_SPI) Receive Pointer Register
+#define AT91C_SPI_PTSR  ((AT91_REG *) 	0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
+#define AT91C_SPI_TNCR  ((AT91_REG *) 	0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
+#define AT91C_SPI_RNCR  ((AT91_REG *) 	0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
+#define AT91C_SPI_TCR   ((AT91_REG *) 	0xFFFE010C) // (PDC_SPI) Transmit Counter Register
+#define AT91C_SPI_RCR   ((AT91_REG *) 	0xFFFE0104) // (PDC_SPI) Receive Counter Register
+// ========== Register definition for SPI peripheral ========== 
+#define AT91C_SPI_CSR   ((AT91_REG *) 	0xFFFE0030) // (SPI) Chip Select Register
+#define AT91C_SPI_IDR   ((AT91_REG *) 	0xFFFE0018) // (SPI) Interrupt Disable Register
+#define AT91C_SPI_SR    ((AT91_REG *) 	0xFFFE0010) // (SPI) Status Register
+#define AT91C_SPI_RDR   ((AT91_REG *) 	0xFFFE0008) // (SPI) Receive Data Register
+#define AT91C_SPI_CR    ((AT91_REG *) 	0xFFFE0000) // (SPI) Control Register
+#define AT91C_SPI_IMR   ((AT91_REG *) 	0xFFFE001C) // (SPI) Interrupt Mask Register
+#define AT91C_SPI_IER   ((AT91_REG *) 	0xFFFE0014) // (SPI) Interrupt Enable Register
+#define AT91C_SPI_TDR   ((AT91_REG *) 	0xFFFE000C) // (SPI) Transmit Data Register
+#define AT91C_SPI_MR    ((AT91_REG *) 	0xFFFE0004) // (SPI) Mode Register
+// ========== Register definition for PDC_ADC peripheral ========== 
+#define AT91C_ADC_PTCR  ((AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR  ((AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_RNPR  ((AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_TPR   ((AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RPR   ((AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_PTSR  ((AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_TNCR  ((AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNCR  ((AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_TCR   ((AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_RCR   ((AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ========== 
+#define AT91C_ADC_IMR   ((AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+#define AT91C_ADC_CDR4  ((AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR2  ((AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR0  ((AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR7  ((AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR1  ((AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_CDR3  ((AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR5  ((AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_MR    ((AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_CDR6  ((AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_CR    ((AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CHER  ((AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR  ((AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_IER   ((AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_SR    ((AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CHDR  ((AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_IDR   ((AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_LCDR  ((AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
+// ========== Register definition for PDC_SSC peripheral ========== 
+#define AT91C_SSC_PTCR  ((AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TNPR  ((AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_RNPR  ((AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TPR   ((AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_RPR   ((AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_PTSR  ((AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+#define AT91C_SSC_TNCR  ((AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RNCR  ((AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TCR   ((AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR   ((AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
+// ========== Register definition for SSC peripheral ========== 
+#define AT91C_SSC_RFMR  ((AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
+#define AT91C_SSC_CMR   ((AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_IDR   ((AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_SR    ((AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_RC0R  ((AT91_REG *) 	0xFFFD4038) // (SSC) Receive Compare 0 Register
+#define AT91C_SSC_RSHR  ((AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_RHR   ((AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_TCMR  ((AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_RCMR  ((AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_CR    ((AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR   ((AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_IER   ((AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_RC1R  ((AT91_REG *) 	0xFFFD403C) // (SSC) Receive Compare 1 Register
+#define AT91C_SSC_TSHR  ((AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_THR   ((AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_TFMR  ((AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_PTSR  ((AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNCR  ((AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_RNCR  ((AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_PTCR  ((AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TNPR  ((AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RNPR  ((AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_XXR   ((AT91_REG *) 	0xFFFC4048) // (US1) XON_XOFF Register
+#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_FIDI  ((AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_IF    ((AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER   ((AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_PTCR  ((AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_TNPR  ((AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR  ((AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_PTSR  ((AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR  ((AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_RNCR  ((AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_NER   ((AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_XXR   ((AT91_REG *) 	0xFFFC0048) // (US0) XON_XOFF Register
+#define AT91C_US0_FIDI  ((AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
+#define AT91C_US0_IF    ((AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
+// ========== Register definition for TWI peripheral ========== 
+#define AT91C_TWI_RHR   ((AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
+#define AT91C_TWI_IDR   ((AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_SR    ((AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_CWGR  ((AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_SMR   ((AT91_REG *) 	0xFFFB8008) // (TWI) Slave Mode Register
+#define AT91C_TWI_CR    ((AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_THR   ((AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IMR   ((AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_IER   ((AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_IADR  ((AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR   ((AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_IER   ((AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_RC    ((AT91_REG *) 	0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_RA    ((AT91_REG *) 	0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
+#define AT91C_TC2_RB    ((AT91_REG *) 	0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_CV    ((AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_RB    ((AT91_REG *) 	0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CV    ((AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
+#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
+#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
+// ========== Register definition for TCB peripheral ========== 
+#define AT91C_TCB_BMR   ((AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR   ((AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for PWMC_CH3 peripheral ========== 
+#define AT91C_CH3_CUPDR ((AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_CH3_CPRDR ((AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_CH3_CMR   ((AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+#define AT91C_CH3_Reserved ((AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_CH3_CCNTR ((AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_CH3_CDTYR ((AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH2 peripheral ========== 
+#define AT91C_CH2_CUPDR ((AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_CH2_CPRDR ((AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_CH2_CMR   ((AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_CH2_Reserved ((AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_CH2_CCNTR ((AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_CH2_CDTYR ((AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ========== 
+#define AT91C_CH1_CUPDR ((AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_CH1_CPRDR ((AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_CH1_CMR   ((AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+#define AT91C_CH1_Reserved ((AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_CH1_CCNTR ((AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_CH1_CDTYR ((AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH0 peripheral ========== 
+#define AT91C_CH0_CUPDR ((AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_CH0_CPRDR ((AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_CH0_CMR   ((AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_CH0_Reserved ((AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_CH0_CCNTR ((AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+#define AT91C_CH0_CDTYR ((AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+// ========== Register definition for PWMC peripheral ========== 
+#define AT91C_PWMC_VR   ((AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR  ((AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_IDR  ((AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_SR   ((AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_ENA  ((AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
+#define AT91C_PWMC_IMR  ((AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR   ((AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_DIS  ((AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER  ((AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+// ========== Register definition for UDP peripheral ========== 
+#define AT91C_UDP_ISR   ((AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_IDR   ((AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_FDR   ((AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_CSR   ((AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_ICR   ((AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_IMR   ((AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_IER   ((AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM   ((AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_PWM0     ((unsigned int) AT91C_PIO_PA0) //  PWM Channel 0
+#define AT91C_PA0_TIOA0    ((unsigned int) AT91C_PIO_PA0) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_PWM1     ((unsigned int) AT91C_PIO_PA1) //  PWM Channel 1
+#define AT91C_PA1_TIOB0    ((unsigned int) AT91C_PIO_PA1) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_DTXD     ((unsigned int) AT91C_PIO_PA10) //  DBGU Debug Transmit Data
+#define AT91C_PA10_NPCS2    ((unsigned int) AT91C_PIO_PA10) //  SPI Peripheral Chip Select 2
+#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_NPCS0    ((unsigned int) AT91C_PIO_PA11) //  SPI Peripheral Chip Select 0
+#define AT91C_PA11_PWM0     ((unsigned int) AT91C_PIO_PA11) //  PWM Channel 0
+#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_MISO     ((unsigned int) AT91C_PIO_PA12) //  SPI Master In Slave
+#define AT91C_PA12_PWM1     ((unsigned int) AT91C_PIO_PA12) //  PWM Channel 1
+#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_MOSI     ((unsigned int) AT91C_PIO_PA13) //  SPI Master Out Slave
+#define AT91C_PA13_PWM2     ((unsigned int) AT91C_PIO_PA13) //  PWM Channel 2
+#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_SPCK     ((unsigned int) AT91C_PIO_PA14) //  SPI Serial Clock
+#define AT91C_PA14_PWM3     ((unsigned int) AT91C_PIO_PA14) //  PWM Channel 3
+#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_TF       ((unsigned int) AT91C_PIO_PA15) //  SSC Transmit Frame Sync
+#define AT91C_PA15_TIOA1    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_TK       ((unsigned int) AT91C_PIO_PA16) //  SSC Transmit Clock
+#define AT91C_PA16_TIOB1    ((unsigned int) AT91C_PIO_PA16) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_TD       ((unsigned int) AT91C_PIO_PA17) //  SSC Transmit data
+#define AT91C_PA17_PCK1     ((unsigned int) AT91C_PIO_PA17) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_RD       ((unsigned int) AT91C_PIO_PA18) //  SSC Receive Data
+#define AT91C_PA18_PCK2     ((unsigned int) AT91C_PIO_PA18) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_RK       ((unsigned int) AT91C_PIO_PA19) //  SSC Receive Clock
+#define AT91C_PA19_FIQ      ((unsigned int) AT91C_PIO_PA19) //  AIC Fast Interrupt Input
+#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_PWM2     ((unsigned int) AT91C_PIO_PA2) //  PWM Channel 2
+#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
+#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_RF       ((unsigned int) AT91C_PIO_PA20) //  SSC Receive Frame Sync
+#define AT91C_PA20_IRQ0     ((unsigned int) AT91C_PIO_PA20) //  External Interrupt 0
+#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_RXD1     ((unsigned int) AT91C_PIO_PA21) //  USART 1 Receive Data
+#define AT91C_PA21_PCK1     ((unsigned int) AT91C_PIO_PA21) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TXD1     ((unsigned int) AT91C_PIO_PA22) //  USART 1 Transmit Data
+#define AT91C_PA22_NPCS3    ((unsigned int) AT91C_PIO_PA22) //  SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_SCK1     ((unsigned int) AT91C_PIO_PA23) //  USART 1 Serial Clock
+#define AT91C_PA23_PWM0     ((unsigned int) AT91C_PIO_PA23) //  PWM Channel 0
+#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RTS1     ((unsigned int) AT91C_PIO_PA24) //  USART 1 Ready To Send
+#define AT91C_PA24_PWM1     ((unsigned int) AT91C_PIO_PA24) //  PWM Channel 1
+#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_CTS1     ((unsigned int) AT91C_PIO_PA25) //  USART 1 Clear To Send
+#define AT91C_PA25_PWM2     ((unsigned int) AT91C_PIO_PA25) //  PWM Channel 2
+#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_DCD1     ((unsigned int) AT91C_PIO_PA26) //  USART 1 Data Carrier Detect
+#define AT91C_PA26_TIOA2    ((unsigned int) AT91C_PIO_PA26) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DTR1     ((unsigned int) AT91C_PIO_PA27) //  USART 1 Data Terminal ready
+#define AT91C_PA27_TIOB2    ((unsigned int) AT91C_PIO_PA27) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DSR1     ((unsigned int) AT91C_PIO_PA28) //  USART 1 Data Set ready
+#define AT91C_PA28_TCLK1    ((unsigned int) AT91C_PIO_PA28) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_RI1      ((unsigned int) AT91C_PIO_PA29) //  USART 1 Ring Indicator
+#define AT91C_PA29_TCLK2    ((unsigned int) AT91C_PIO_PA29) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_TWD      ((unsigned int) AT91C_PIO_PA3) //  TWI Two-wire Serial Data
+#define AT91C_PA3_NPCS3    ((unsigned int) AT91C_PIO_PA3) //  SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ1     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 1
+#define AT91C_PA30_NPCS2    ((unsigned int) AT91C_PIO_PA30) //  SPI Peripheral Chip Select 2
+#define AT91C_PIO_PA31       ((unsigned int) 1 << 31) // Pin Controlled by PA31
+#define AT91C_PA31_NPCS1    ((unsigned int) AT91C_PIO_PA31) //  SPI Peripheral Chip Select 1
+#define AT91C_PA31_PCK2     ((unsigned int) AT91C_PIO_PA31) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_TWCK     ((unsigned int) AT91C_PIO_PA4) //  TWI Two-wire Serial Clock
+#define AT91C_PA4_TCLK0    ((unsigned int) AT91C_PIO_PA4) //  Timer Counter 0 external clock input
+#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD0     ((unsigned int) AT91C_PIO_PA5) //  USART 0 Receive Data
+#define AT91C_PA5_NPCS3    ((unsigned int) AT91C_PIO_PA5) //  SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD0     ((unsigned int) AT91C_PIO_PA6) //  USART 0 Transmit Data
+#define AT91C_PA6_PCK0     ((unsigned int) AT91C_PIO_PA6) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_RTS0     ((unsigned int) AT91C_PIO_PA7) //  USART 0 Ready To Send
+#define AT91C_PA7_PWM3     ((unsigned int) AT91C_PIO_PA7) //  PWM Channel 3
+#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_CTS0     ((unsigned int) AT91C_PIO_PA8) //  USART 0 Clear To Send
+#define AT91C_PA8_ADTRG    ((unsigned int) AT91C_PIO_PA8) //  ADC External Trigger
+#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_DRXD     ((unsigned int) AT91C_PIO_PA9) //  DBGU Debug Receive Data
+#define AT91C_PA9_NPCS1    ((unsigned int) AT91C_PIO_PA9) //  SPI Peripheral Chip Select 1
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
+#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller
+#define AT91C_ID_3_Reserved ((unsigned int)  3) // Reserved
+#define AT91C_ID_ADC    ((unsigned int)  4) // Analog-to-Digital Converter
+#define AT91C_ID_SPI    ((unsigned int)  5) // Serial Peripheral Interface
+#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
+#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
+#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
+#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
+#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
+#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
+#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
+#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
+#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
+#define AT91C_ID_15_Reserved ((unsigned int) 15) // Reserved
+#define AT91C_ID_16_Reserved ((unsigned int) 16) // Reserved
+#define AT91C_ID_17_Reserved ((unsigned int) 17) // Reserved
+#define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved
+#define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
+#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_BASE_SYSC      ((AT91PS_SYSC) 	0xFFFFF000) // (SYSC) Base Address
+#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_DBGU      ((AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_CKGR      ((AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC       ((AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC      ((AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC      ((AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC      ((AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC      ((AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_MC        ((AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI   ((AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI) Base Address
+#define AT91C_BASE_SPI       ((AT91PS_SPI) 	0xFFFE0000) // (SPI) Base Address
+#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC       ((AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC       ((AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_TWI       ((AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TCB       ((AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC      ((AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP       ((AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_ISRAM	 ((char *) 	0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE	 ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbyte)
+#define AT91C_IFLASH	 ((char *) 	0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE	 ((unsigned int) 0x00010000) // Internal ROM size in byte (64 Kbyte)
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h
new file mode 100644
index 0000000..7d2657a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h
@@ -0,0 +1,1812 @@
+// ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ----------------------------------------------------------------------------
+//  The software is delivered "AS IS" without warranty or condition of any
+//  kind, either express, implied or statutory. This includes without
+//  limitation any warranty or condition with respect to merchantability or
+//  fitness for any particular purpose, or against the infringements of
+//  intellectual property rights of others.
+// ----------------------------------------------------------------------------
+// File Name           : AT91SAM7S64.h
+// Object              : AT91SAM7S64 definitions
+// Generated           : AT91 SW Application Group  07/16/2004 (07:43:09)
+// 
+// CVS Reference       : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004//
+// CVS Reference       : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004//
+// CVS Reference       : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004//
+// CVS Reference       : /UDP_1765B.pl/1.3/Fri Aug  2 14:45:38 2002//
+// CVS Reference       : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
+// CVS Reference       : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//
+// CVS Reference       : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
+// CVS Reference       : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//
+// CVS Reference       : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004//
+// CVS Reference       : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003//
+// CVS Reference       : /SSC_1762A.pl/1.2/Fri Nov  8 13:26:40 2002//
+// CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+// CVS Reference       : /TWI_1761B.pl/1.4/Fri Feb  7 10:30:08 2003//
+// CVS Reference       : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002//
+// CVS Reference       : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003//
+// CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+// ----------------------------------------------------------------------------
+
+// Hardware register definition
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+// *** Register offset in AT91S_SYSC structure ***
+#define SYSC_AIC_SMR    ( 0) // Source Mode Register
+#define SYSC_AIC_SVR    (128) // Source Vector Register
+#define SYSC_AIC_IVR    (256) // IRQ Vector Register
+#define SYSC_AIC_FVR    (260) // FIQ Vector Register
+#define SYSC_AIC_ISR    (264) // Interrupt Status Register
+#define SYSC_AIC_IPR    (268) // Interrupt Pending Register
+#define SYSC_AIC_IMR    (272) // Interrupt Mask Register
+#define SYSC_AIC_CISR   (276) // Core Interrupt Status Register
+#define SYSC_AIC_IECR   (288) // Interrupt Enable Command Register
+#define SYSC_AIC_IDCR   (292) // Interrupt Disable Command Register
+#define SYSC_AIC_ICCR   (296) // Interrupt Clear Command Register
+#define SYSC_AIC_ISCR   (300) // Interrupt Set Command Register
+#define SYSC_AIC_EOICR  (304) // End of Interrupt Command Register
+#define SYSC_AIC_SPU    (308) // Spurious Vector Register
+#define SYSC_AIC_DCR    (312) // Debug Control Register (Protect)
+#define SYSC_AIC_FFER   (320) // Fast Forcing Enable Register
+#define SYSC_AIC_FFDR   (324) // Fast Forcing Disable Register
+#define SYSC_AIC_FFSR   (328) // Fast Forcing Status Register
+#define SYSC_DBGU_CR    (512) // Control Register
+#define SYSC_DBGU_MR    (516) // Mode Register
+#define SYSC_DBGU_IER   (520) // Interrupt Enable Register
+#define SYSC_DBGU_IDR   (524) // Interrupt Disable Register
+#define SYSC_DBGU_IMR   (528) // Interrupt Mask Register
+#define SYSC_DBGU_CSR   (532) // Channel Status Register
+#define SYSC_DBGU_RHR   (536) // Receiver Holding Register
+#define SYSC_DBGU_THR   (540) // Transmitter Holding Register
+#define SYSC_DBGU_BRGR  (544) // Baud Rate Generator Register
+#define SYSC_DBGU_C1R   (576) // Chip ID1 Register
+#define SYSC_DBGU_C2R   (580) // Chip ID2 Register
+#define SYSC_DBGU_FNTR  (584) // Force NTRST Register
+#define SYSC_DBGU_RPR   (768) // Receive Pointer Register
+#define SYSC_DBGU_RCR   (772) // Receive Counter Register
+#define SYSC_DBGU_TPR   (776) // Transmit Pointer Register
+#define SYSC_DBGU_TCR   (780) // Transmit Counter Register
+#define SYSC_DBGU_RNPR  (784) // Receive Next Pointer Register
+#define SYSC_DBGU_RNCR  (788) // Receive Next Counter Register
+#define SYSC_DBGU_TNPR  (792) // Transmit Next Pointer Register
+#define SYSC_DBGU_TNCR  (796) // Transmit Next Counter Register
+#define SYSC_DBGU_PTCR  (800) // PDC Transfer Control Register
+#define SYSC_DBGU_PTSR  (804) // PDC Transfer Status Register
+#define SYSC_PIOA_PER   (1024) // PIO Enable Register
+#define SYSC_PIOA_PDR   (1028) // PIO Disable Register
+#define SYSC_PIOA_PSR   (1032) // PIO Status Register
+#define SYSC_PIOA_OER   (1040) // Output Enable Register
+#define SYSC_PIOA_ODR   (1044) // Output Disable Registerr
+#define SYSC_PIOA_OSR   (1048) // Output Status Register
+#define SYSC_PIOA_IFER  (1056) // Input Filter Enable Register
+#define SYSC_PIOA_IFDR  (1060) // Input Filter Disable Register
+#define SYSC_PIOA_IFSR  (1064) // Input Filter Status Register
+#define SYSC_PIOA_SODR  (1072) // Set Output Data Register
+#define SYSC_PIOA_CODR  (1076) // Clear Output Data Register
+#define SYSC_PIOA_ODSR  (1080) // Output Data Status Register
+#define SYSC_PIOA_PDSR  (1084) // Pin Data Status Register
+#define SYSC_PIOA_IER   (1088) // Interrupt Enable Register
+#define SYSC_PIOA_IDR   (1092) // Interrupt Disable Register
+#define SYSC_PIOA_IMR   (1096) // Interrupt Mask Register
+#define SYSC_PIOA_ISR   (1100) // Interrupt Status Register
+#define SYSC_PIOA_MDER  (1104) // Multi-driver Enable Register
+#define SYSC_PIOA_MDDR  (1108) // Multi-driver Disable Register
+#define SYSC_PIOA_MDSR  (1112) // Multi-driver Status Register
+#define SYSC_PIOA_PPUDR (1120) // Pull-up Disable Register
+#define SYSC_PIOA_PPUER (1124) // Pull-up Enable Register
+#define SYSC_PIOA_PPUSR (1128) // Pad Pull-up Status Register
+#define SYSC_PIOA_ASR   (1136) // Select A Register
+#define SYSC_PIOA_BSR   (1140) // Select B Register
+#define SYSC_PIOA_ABSR  (1144) // AB Select Status Register
+#define SYSC_PIOA_OWER  (1184) // Output Write Enable Register
+#define SYSC_PIOA_OWDR  (1188) // Output Write Disable Register
+#define SYSC_PIOA_OWSR  (1192) // Output Write Status Register
+#define SYSC_PMC_SCER   (3072) // System Clock Enable Register
+#define SYSC_PMC_SCDR   (3076) // System Clock Disable Register
+#define SYSC_PMC_SCSR   (3080) // System Clock Status Register
+#define SYSC_PMC_PCER   (3088) // Peripheral Clock Enable Register
+#define SYSC_PMC_PCDR   (3092) // Peripheral Clock Disable Register
+#define SYSC_PMC_PCSR   (3096) // Peripheral Clock Status Register
+#define SYSC_PMC_MOR    (3104) // Main Oscillator Register
+#define SYSC_PMC_MCFR   (3108) // Main Clock  Frequency Register
+#define SYSC_PMC_PLLR   (3116) // PLL Register
+#define SYSC_PMC_MCKR   (3120) // Master Clock Register
+#define SYSC_PMC_PCKR   (3136) // Programmable Clock Register
+#define SYSC_PMC_IER    (3168) // Interrupt Enable Register
+#define SYSC_PMC_IDR    (3172) // Interrupt Disable Register
+#define SYSC_PMC_SR     (3176) // Status Register
+#define SYSC_PMC_IMR    (3180) // Interrupt Mask Register
+#define SYSC_RSTC_RCR   (3328) // Reset Control Register
+#define SYSC_RSTC_RSR   (3332) // Reset Status Register
+#define SYSC_RSTC_RMR   (3336) // Reset Mode Register
+#define SYSC_RTTC_RTMR  (3360) // Real-time Mode Register
+#define SYSC_RTTC_RTAR  (3364) // Real-time Alarm Register
+#define SYSC_RTTC_RTVR  (3368) // Real-time Value Register
+#define SYSC_RTTC_RTSR  (3372) // Real-time Status Register
+#define SYSC_PITC_PIMR  (3376) // Period Interval Mode Register
+#define SYSC_PITC_PISR  (3380) // Period Interval Status Register
+#define SYSC_PITC_PIVR  (3384) // Period Interval Value Register
+#define SYSC_PITC_PIIR  (3388) // Period Interval Image Register
+#define SYSC_WDTC_WDCR  (3392) // Watchdog Control Register
+#define SYSC_WDTC_WDMR  (3396) // Watchdog Mode Register
+#define SYSC_WDTC_WDSR  (3400) // Watchdog Status Register
+#define SYSC_SYSC_VRPM  (3424) // Voltage Regulator Power Mode Register
+// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- 
+#define AT91C_SYSC_PSTDBY         (0x1 <<  0) // (SYSC) Voltage Regulator Power Mode
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+// *** Register offset in AT91S_AIC structure ***
+#define AIC_SMR         ( 0) // Source Mode Register
+#define AIC_SVR         (128) // Source Vector Register
+#define AIC_IVR         (256) // IRQ Vector Register
+#define AIC_FVR         (260) // FIQ Vector Register
+#define AIC_ISR         (264) // Interrupt Status Register
+#define AIC_IPR         (268) // Interrupt Pending Register
+#define AIC_IMR         (272) // Interrupt Mask Register
+#define AIC_CISR        (276) // Core Interrupt Status Register
+#define AIC_IECR        (288) // Interrupt Enable Command Register
+#define AIC_IDCR        (292) // Interrupt Disable Command Register
+#define AIC_ICCR        (296) // Interrupt Clear Command Register
+#define AIC_ISCR        (300) // Interrupt Set Command Register
+#define AIC_EOICR       (304) // End of Interrupt Command Register
+#define AIC_SPU         (308) // Spurious Vector Register
+#define AIC_DCR         (312) // Debug Control Register (Protect)
+#define AIC_FFER        (320) // Fast Forcing Enable Register
+#define AIC_FFDR        (324) // Fast Forcing Disable Register
+#define AIC_FFSR        (328) // Fast Forcing Status Register
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR           (0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE         (0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  (0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   (0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       (0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    (0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ            (0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ            (0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT        (0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK        (0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+// *** Register offset in AT91S_DBGU structure ***
+#define DBGU_CR         ( 0) // Control Register
+#define DBGU_MR         ( 4) // Mode Register
+#define DBGU_IER        ( 8) // Interrupt Enable Register
+#define DBGU_IDR        (12) // Interrupt Disable Register
+#define DBGU_IMR        (16) // Interrupt Mask Register
+#define DBGU_CSR        (20) // Channel Status Register
+#define DBGU_RHR        (24) // Receiver Holding Register
+#define DBGU_THR        (28) // Transmitter Holding Register
+#define DBGU_BRGR       (32) // Baud Rate Generator Register
+#define DBGU_C1R        (64) // Chip ID1 Register
+#define DBGU_C2R        (68) // Chip ID2 Register
+#define DBGU_FNTR       (72) // Force NTRST Register
+#define DBGU_RPR        (256) // Receive Pointer Register
+#define DBGU_RCR        (260) // Receive Counter Register
+#define DBGU_TPR        (264) // Transmit Pointer Register
+#define DBGU_TCR        (268) // Transmit Counter Register
+#define DBGU_RNPR       (272) // Receive Next Pointer Register
+#define DBGU_RNCR       (276) // Receive Next Counter Register
+#define DBGU_TNPR       (280) // Transmit Next Pointer Register
+#define DBGU_TNCR       (284) // Transmit Next Counter Register
+#define DBGU_PTCR       (288) // PDC Transfer Control Register
+#define DBGU_PTSR       (292) // PDC Transfer Status Register
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX            (0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX            (0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN             (0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS            (0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN             (0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS            (0x1 <<  7) // (DBGU) Transmitter Disable
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR              (0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE           (0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY            (0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY            (0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX            (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX            (0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE             (0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME            (0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE             (0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY          (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE           (0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF           (0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX          (0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX          (0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST      (0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral Data Controller
+// *****************************************************************************
+// *** Register offset in AT91S_PDC structure ***
+#define PDC_RPR         ( 0) // Receive Pointer Register
+#define PDC_RCR         ( 4) // Receive Counter Register
+#define PDC_TPR         ( 8) // Transmit Pointer Register
+#define PDC_TCR         (12) // Transmit Counter Register
+#define PDC_RNPR        (16) // Receive Next Pointer Register
+#define PDC_RNCR        (20) // Receive Next Counter Register
+#define PDC_TNPR        (24) // Transmit Next Pointer Register
+#define PDC_TNCR        (28) // Transmit Next Counter Register
+#define PDC_PTCR        (32) // PDC Transfer Control Register
+#define PDC_PTSR        (36) // PDC Transfer Status Register
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN           (0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS          (0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN           (0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS          (0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+// *** Register offset in AT91S_PIO structure ***
+#define PIO_PER         ( 0) // PIO Enable Register
+#define PIO_PDR         ( 4) // PIO Disable Register
+#define PIO_PSR         ( 8) // PIO Status Register
+#define PIO_OER         (16) // Output Enable Register
+#define PIO_ODR         (20) // Output Disable Registerr
+#define PIO_OSR         (24) // Output Status Register
+#define PIO_IFER        (32) // Input Filter Enable Register
+#define PIO_IFDR        (36) // Input Filter Disable Register
+#define PIO_IFSR        (40) // Input Filter Status Register
+#define PIO_SODR        (48) // Set Output Data Register
+#define PIO_CODR        (52) // Clear Output Data Register
+#define PIO_ODSR        (56) // Output Data Status Register
+#define PIO_PDSR        (60) // Pin Data Status Register
+#define PIO_IER         (64) // Interrupt Enable Register
+#define PIO_IDR         (68) // Interrupt Disable Register
+#define PIO_IMR         (72) // Interrupt Mask Register
+#define PIO_ISR         (76) // Interrupt Status Register
+#define PIO_MDER        (80) // Multi-driver Enable Register
+#define PIO_MDDR        (84) // Multi-driver Disable Register
+#define PIO_MDSR        (88) // Multi-driver Status Register
+#define PIO_PPUDR       (96) // Pull-up Disable Register
+#define PIO_PPUER       (100) // Pull-up Enable Register
+#define PIO_PPUSR       (104) // Pad Pull-up Status Register
+#define PIO_ASR         (112) // Select A Register
+#define PIO_BSR         (116) // Select B Register
+#define PIO_ABSR        (120) // AB Select Status Register
+#define PIO_OWER        (160) // Output Write Enable Register
+#define PIO_OWDR        (164) // Output Write Disable Register
+#define PIO_OWSR        (168) // Output Write Status Register
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+// *** Register offset in AT91S_CKGR structure ***
+#define CKGR_MOR        ( 0) // Main Oscillator Register
+#define CKGR_MCFR       ( 4) // Main Clock  Frequency Register
+#define CKGR_PLLR       (12) // PLL Register
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN         (0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS      (0x1 <<  1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT        (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF          (0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY        (0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+#define AT91C_CKGR_DIV            (0xFF <<  0) // (CKGR) Divider Selected
+#define 	AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0
+#define 	AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT       (0x3F <<  8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT            (0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define 	AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL            (0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV         (0x3 << 28) // (CKGR) Divider for USB Clocks
+#define 	AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define 	AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define 	AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+// *** Register offset in AT91S_PMC structure ***
+#define PMC_SCER        ( 0) // System Clock Enable Register
+#define PMC_SCDR        ( 4) // System Clock Disable Register
+#define PMC_SCSR        ( 8) // System Clock Status Register
+#define PMC_PCER        (16) // Peripheral Clock Enable Register
+#define PMC_PCDR        (20) // Peripheral Clock Disable Register
+#define PMC_PCSR        (24) // Peripheral Clock Status Register
+#define PMC_MOR         (32) // Main Oscillator Register
+#define PMC_MCFR        (36) // Main Clock  Frequency Register
+#define PMC_PLLR        (44) // PLL Register
+#define PMC_MCKR        (48) // Master Clock Register
+#define PMC_PCKR        (64) // Programmable Clock Register
+#define PMC_IER         (96) // Interrupt Enable Register
+#define PMC_IDR         (100) // Interrupt Disable Register
+#define PMC_SR          (104) // Status Register
+#define PMC_IMR         (108) // Interrupt Mask Register
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_PCK             (0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP             (0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0            (0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1            (0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2            (0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3            (0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS             (0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLL_CLK              (0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES            (0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS           (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK            (0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY          (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY         (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY         (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY         (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY         (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_RSTC structure ***
+#define RSTC_RCR        ( 0) // Reset Control Register
+#define RSTC_RSR        ( 4) // Reset Status Register
+#define RSTC_RMR        ( 8) // Reset Mode Register
+// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_SYSC_PROCRST        (0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_SYSC_ICERST         (0x1 <<  1) // (RSTC) ICE Interface Reset
+#define AT91C_SYSC_PERRST         (0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_SYSC_EXTRST         (0x1 <<  3) // (RSTC) External Reset
+#define AT91C_SYSC_KEY            (0xFF << 24) // (RSTC) Password
+// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_SYSC_URSTS          (0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_SYSC_BODSTS         (0x1 <<  1) // (RSTC) Brown-out Detection Status
+#define AT91C_SYSC_RSTTYP         (0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_SYSC_RSTTYP_POWERUP              (0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define 	AT91C_SYSC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_SYSC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_SYSC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define 	AT91C_SYSC_RSTTYP_BROWNOUT             (0x5 <<  8) // (RSTC) Brown-out Reset.
+#define AT91C_SYSC_NRSTL          (0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_SYSC_SRCMP          (0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_SYSC_URSTEN         (0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_SYSC_URSTIEN        (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_SYSC_ERSTL          (0xF <<  8) // (RSTC) User Reset Enable
+#define AT91C_SYSC_BODIEN         (0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_RTTC structure ***
+#define RTTC_RTMR       ( 0) // Real-time Mode Register
+#define RTTC_RTAR       ( 4) // Real-time Alarm Register
+#define RTTC_RTVR       ( 8) // Real-time Value Register
+#define RTTC_RTSR       (12) // Real-time Status Register
+// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_SYSC_RTPRES         (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_SYSC_ALMIEN         (0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_SYSC_RTTINCIEN      (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_SYSC_RTTRST         (0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_SYSC_ALMV           (0x0 <<  0) // (RTTC) Alarm Value
+// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_SYSC_CRTV           (0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_SYSC_ALMS           (0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_SYSC_RTTINC         (0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PITC structure ***
+#define PITC_PIMR       ( 0) // Period Interval Mode Register
+#define PITC_PISR       ( 4) // Period Interval Status Register
+#define PITC_PIVR       ( 8) // Period Interval Value Register
+#define PITC_PIIR       (12) // Period Interval Image Register
+// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_SYSC_PIV            (0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_SYSC_PITEN          (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_SYSC_PITIEN         (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_SYSC_PITS           (0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_SYSC_CPIV           (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_SYSC_PICNT          (0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_WDTC structure ***
+#define WDTC_WDCR       ( 0) // Watchdog Control Register
+#define WDTC_WDMR       ( 4) // Watchdog Mode Register
+#define WDTC_WDSR       ( 8) // Watchdog Status Register
+// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_SYSC_WDRSTT         (0x1 <<  0) // (WDTC) Watchdog Restart
+// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_SYSC_WDV            (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_SYSC_WDFIEN         (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_SYSC_WDRSTEN        (0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_SYSC_WDRPROC        (0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_SYSC_WDDIS          (0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_SYSC_WDD            (0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_SYSC_WDDBGHLT       (0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_SYSC_WDIDLEHLT      (0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_SYSC_WDUNF          (0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_SYSC_WDERR          (0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_MC structure ***
+#define MC_RCR          ( 0) // MC Remap Control Register
+#define MC_ASR          ( 4) // MC Abort Status Register
+#define MC_AASR         ( 8) // MC Abort Address Status Register
+#define MC_FMR          (96) // MC Flash Mode Register
+#define MC_FCR          (100) // MC Flash Command Register
+#define MC_FSR          (104) // MC Flash Status Register
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+#define AT91C_MC_RCB              (0x1 <<  0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+#define AT91C_MC_UNDADD           (0x1 <<  0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD           (0x1 <<  1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ            (0x3 <<  8) // (MC) Abort Size Status
+#define 	AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
+#define 	AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
+#define 	AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
+#define AT91C_MC_ABTTYP           (0x3 << 10) // (MC) Abort Type Status
+#define 	AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
+#define 	AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
+#define 	AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0             (0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1             (0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0           (0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1           (0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+#define AT91C_MC_FRDY             (0x1 <<  0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE            (0x1 <<  2) // (MC) Lock Error
+#define AT91C_MC_PROGE            (0x1 <<  3) // (MC) Programming Error
+#define AT91C_MC_NEBP             (0x1 <<  7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS              (0x3 <<  8) // (MC) Flash Wait State
+#define 	AT91C_MC_FWS_0FWS                 (0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
+#define 	AT91C_MC_FWS_1FWS                 (0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
+#define 	AT91C_MC_FWS_2FWS                 (0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
+#define 	AT91C_MC_FWS_3FWS                 (0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN             (0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+#define AT91C_MC_FCMD             (0xF <<  0) // (MC) Flash Command
+#define 	AT91C_MC_FCMD_START_PROG           (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define 	AT91C_MC_FCMD_LOCK                 (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_PROG_AND_LOCK        (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define 	AT91C_MC_FCMD_UNLOCK               (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_ERASE_ALL            (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define 	AT91C_MC_FCMD_SET_GP_NVM           (0xB) // (MC) Set General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_CLR_GP_NVM           (0xD) // (MC) Clear General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_SET_SECURITY         (0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN            (0x3FF <<  8) // (MC) Page Number
+#define AT91C_MC_KEY              (0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+#define AT91C_MC_SECURITY         (0x1 <<  4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0           (0x1 <<  8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1           (0x1 <<  9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2           (0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3           (0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4           (0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5           (0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6           (0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7           (0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0           (0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1           (0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2           (0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3           (0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4           (0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5           (0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6           (0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7           (0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8           (0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9           (0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10          (0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11          (0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12          (0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13          (0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14          (0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15          (0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_SPI structure ***
+#define SPI_CR          ( 0) // Control Register
+#define SPI_MR          ( 4) // Mode Register
+#define SPI_RDR         ( 8) // Receive Data Register
+#define SPI_TDR         (12) // Transmit Data Register
+#define SPI_SR          (16) // Status Register
+#define SPI_IER         (20) // Interrupt Enable Register
+#define SPI_IDR         (24) // Interrupt Disable Register
+#define SPI_IMR         (28) // Interrupt Mask Register
+#define SPI_CSR         (48) // Chip Select Register
+#define SPI_RPR         (256) // Receive Pointer Register
+#define SPI_RCR         (260) // Receive Counter Register
+#define SPI_TPR         (264) // Transmit Pointer Register
+#define SPI_TCR         (268) // Transmit Counter Register
+#define SPI_RNPR        (272) // Receive Next Pointer Register
+#define SPI_RNCR        (276) // Receive Next Counter Register
+#define SPI_TNPR        (280) // Transmit Next Pointer Register
+#define SPI_TNCR        (284) // Transmit Next Counter Register
+#define SPI_PTCR        (288) // PDC Transfer Control Register
+#define SPI_PTSR        (292) // PDC Transfer Status Register
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN           (0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS          (0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST           (0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER        (0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR            (0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS              (0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC          (0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV            (0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS         (0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB             (0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS             (0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS          (0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD              (0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD              (0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF            (0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE            (0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF            (0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES           (0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX           (0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX           (0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF          (0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE          (0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR            (0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY         (0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS          (0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL            (0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA           (0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT           (0x1 <<  2) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS            (0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR            (0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS           (0xFF << 16) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBCT          (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// *****************************************************************************
+// *** Register offset in AT91S_ADC structure ***
+#define ADC_CR          ( 0) // ADC Control Register
+#define ADC_MR          ( 4) // ADC Mode Register
+#define ADC_CHER        (16) // ADC Channel Enable Register
+#define ADC_CHDR        (20) // ADC Channel Disable Register
+#define ADC_CHSR        (24) // ADC Channel Status Register
+#define ADC_SR          (28) // ADC Status Register
+#define ADC_LCDR        (32) // ADC Last Converted Data Register
+#define ADC_IER         (36) // ADC Interrupt Enable Register
+#define ADC_IDR         (40) // ADC Interrupt Disable Register
+#define ADC_IMR         (44) // ADC Interrupt Mask Register
+#define ADC_CDR0        (48) // ADC Channel Data Register 0
+#define ADC_CDR1        (52) // ADC Channel Data Register 1
+#define ADC_CDR2        (56) // ADC Channel Data Register 2
+#define ADC_CDR3        (60) // ADC Channel Data Register 3
+#define ADC_CDR4        (64) // ADC Channel Data Register 4
+#define ADC_CDR5        (68) // ADC Channel Data Register 5
+#define ADC_CDR6        (72) // ADC Channel Data Register 6
+#define ADC_CDR7        (76) // ADC Channel Data Register 7
+#define ADC_RPR         (256) // Receive Pointer Register
+#define ADC_RCR         (260) // Receive Counter Register
+#define ADC_TPR         (264) // Transmit Pointer Register
+#define ADC_TCR         (268) // Transmit Counter Register
+#define ADC_RNPR        (272) // Receive Next Pointer Register
+#define ADC_RNCR        (276) // Receive Next Counter Register
+#define ADC_TNPR        (280) // Transmit Next Pointer Register
+#define ADC_TNCR        (284) // Transmit Next Counter Register
+#define ADC_PTCR        (288) // PDC Transfer Control Register
+#define ADC_PTSR        (292) // PDC Transfer Status Register
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+#define AT91C_ADC_SWRST           (0x1 <<  0) // (ADC) Software Reset
+#define AT91C_ADC_START           (0x1 <<  1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+#define AT91C_ADC_TRGEN           (0x1 <<  0) // (ADC) Trigger Enable
+#define 	AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define 	AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL          (0x7 <<  1) // (ADC) Trigger Selection
+#define 	AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
+#define 	AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
+#define 	AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
+#define 	AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
+#define 	AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
+#define 	AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
+#define 	AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES          (0x1 <<  4) // (ADC) Resolution.
+#define 	AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
+#define 	AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP           (0x1 <<  5) // (ADC) Sleep Mode
+#define 	AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
+#define 	AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL         (0x3F <<  8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP         (0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM           (0xF << 24) // (ADC) Sample & Hold Time
+// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+#define AT91C_ADC_CH0             (0x1 <<  0) // (ADC) Channel 0
+#define AT91C_ADC_CH1             (0x1 <<  1) // (ADC) Channel 1
+#define AT91C_ADC_CH2             (0x1 <<  2) // (ADC) Channel 2
+#define AT91C_ADC_CH3             (0x1 <<  3) // (ADC) Channel 3
+#define AT91C_ADC_CH4             (0x1 <<  4) // (ADC) Channel 4
+#define AT91C_ADC_CH5             (0x1 <<  5) // (ADC) Channel 5
+#define AT91C_ADC_CH6             (0x1 <<  6) // (ADC) Channel 6
+#define AT91C_ADC_CH7             (0x1 <<  7) // (ADC) Channel 7
+// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+#define AT91C_ADC_EOC0            (0x1 <<  0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1            (0x1 <<  1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2            (0x1 <<  2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3            (0x1 <<  3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4            (0x1 <<  4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5            (0x1 <<  5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6            (0x1 <<  6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7            (0x1 <<  7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0           (0x1 <<  8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1           (0x1 <<  9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2           (0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3           (0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4           (0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5           (0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6           (0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7           (0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY            (0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE           (0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX           (0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF          (0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+#define AT91C_ADC_LDATA           (0x3FF <<  0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+#define AT91C_ADC_DATA            (0x3FF <<  0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_SSC structure ***
+#define SSC_CR          ( 0) // Control Register
+#define SSC_CMR         ( 4) // Clock Mode Register
+#define SSC_RCMR        (16) // Receive Clock ModeRegister
+#define SSC_RFMR        (20) // Receive Frame Mode Register
+#define SSC_TCMR        (24) // Transmit Clock Mode Register
+#define SSC_TFMR        (28) // Transmit Frame Mode Register
+#define SSC_RHR         (32) // Receive Holding Register
+#define SSC_THR         (36) // Transmit Holding Register
+#define SSC_RSHR        (48) // Receive Sync Holding Register
+#define SSC_TSHR        (52) // Transmit Sync Holding Register
+#define SSC_RC0R        (56) // Receive Compare 0 Register
+#define SSC_RC1R        (60) // Receive Compare 1 Register
+#define SSC_SR          (64) // Status Register
+#define SSC_IER         (68) // Interrupt Enable Register
+#define SSC_IDR         (72) // Interrupt Disable Register
+#define SSC_IMR         (76) // Interrupt Mask Register
+#define SSC_RPR         (256) // Receive Pointer Register
+#define SSC_RCR         (260) // Receive Counter Register
+#define SSC_TPR         (264) // Transmit Pointer Register
+#define SSC_TCR         (268) // Transmit Counter Register
+#define SSC_RNPR        (272) // Receive Next Pointer Register
+#define SSC_RNCR        (276) // Receive Next Counter Register
+#define SSC_TNPR        (280) // Transmit Next Pointer Register
+#define SSC_TNCR        (284) // Transmit Next Counter Register
+#define SSC_PTCR        (288) // PDC Transfer Control Register
+#define SSC_PTSR        (292) // PDC Transfer Status Register
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN            (0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS           (0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN            (0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS           (0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST           (0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS             (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO             (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI             (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_CKG             (0x3 <<  6) // (SSC) Receive/Transmit Clock Gating Selection
+#define 	AT91C_SSC_CKG_NONE                 (0x0 <<  6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
+#define 	AT91C_SSC_CKG_LOW                  (0x1 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF Low
+#define 	AT91C_SSC_CKG_HIGH                 (0x2 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF High
+#define AT91C_SSC_START           (0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STOP            (0x1 << 12) // (SSC) Receive Stop Selection
+#define AT91C_SSC_STTOUT          (0x1 << 15) // (SSC) Receive/Transmit Start Output Selection
+#define AT91C_SSC_STTDLY          (0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD          (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN          (0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP            (0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF            (0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB           (0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN           (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS            (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE          (0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF          (0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN           (0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY           (0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY         (0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX           (0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE          (0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY           (0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN           (0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX           (0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF          (0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_CP0             (0x1 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_CP1             (0x1 <<  9) // (SSC) Compare 1
+#define AT91C_SSC_TXSYN           (0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN           (0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA           (0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA           (0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+// *** Register offset in AT91S_USART structure ***
+#define US_CR           ( 0) // Control Register
+#define US_MR           ( 4) // Mode Register
+#define US_IER          ( 8) // Interrupt Enable Register
+#define US_IDR          (12) // Interrupt Disable Register
+#define US_IMR          (16) // Interrupt Mask Register
+#define US_CSR          (20) // Channel Status Register
+#define US_RHR          (24) // Receiver Holding Register
+#define US_THR          (28) // Transmitter Holding Register
+#define US_BRGR         (32) // Baud Rate Generator Register
+#define US_RTOR         (36) // Receiver Time-out Register
+#define US_TTGR         (40) // Transmitter Time-guard Register
+#define US_FIDI         (64) // FI_DI_Ratio Register
+#define US_NER          (68) // Nb Errors Register
+#define US_XXR          (72) // XON_XOFF Register
+#define US_IF           (76) // IRDA_FILTER Register
+#define US_RPR          (256) // Receive Pointer Register
+#define US_RCR          (260) // Receive Counter Register
+#define US_TPR          (264) // Transmit Pointer Register
+#define US_TCR          (268) // Transmit Counter Register
+#define US_RNPR         (272) // Receive Next Pointer Register
+#define US_RNCR         (276) // Receive Next Counter Register
+#define US_TNPR         (280) // Transmit Next Pointer Register
+#define US_TNCR         (284) // Transmit Next Counter Register
+#define US_PTCR         (288) // PDC Transfer Control Register
+#define US_PTSR         (292) // PDC Transfer Status Register
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTSTA           (0x1 <<  8) // (USART) Reset Status Bits
+#define AT91C_US_STTBRK           (0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK           (0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO            (0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA            (0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT            (0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK          (0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO            (0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN            (0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS           (0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN            (0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS           (0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_USMODE           (0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS             (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL             (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC             (0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP           (0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF             (0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9            (0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO             (0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER             (0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK            (0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK           (0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER         (0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER           (0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK            (0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT          (0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION        (0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK             (0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC             (0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC            (0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC            (0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC            (0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+#define AT91C_US_RI               (0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR              (0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD              (0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS              (0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TWI structure ***
+#define TWI_CR          ( 0) // Control Register
+#define TWI_MMR         ( 4) // Master Mode Register
+#define TWI_SMR         ( 8) // Slave Mode Register
+#define TWI_IADR        (12) // Internal Address Register
+#define TWI_CWGR        (16) // Clock Waveform Generator Register
+#define TWI_SR          (32) // Status Register
+#define TWI_IER         (36) // Interrupt Enable Register
+#define TWI_IDR         (40) // Interrupt Disable Register
+#define TWI_IMR         (44) // Interrupt Mask Register
+#define TWI_RHR         (48) // Receive Holding Register
+#define TWI_THR         (52) // Transmit Holding Register
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START           (0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP            (0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN            (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS           (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SVEN            (0x1 <<  4) // (TWI) TWI Slave Transfer Enabled
+#define AT91C_TWI_SVDIS           (0x1 <<  5) // (TWI) TWI Slave Transfer Disabled
+#define AT91C_TWI_SWRST           (0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ          (0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD           (0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR            (0x7F << 16) // (TWI) Device Address
+// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- 
+#define AT91C_TWI_SADR            (0x7F << 16) // (TWI) Slave Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV           (0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV           (0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV           (0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP          (0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY           (0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY           (0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_SVREAD          (0x1 <<  3) // (TWI) Slave Read
+#define AT91C_TWI_SVACC           (0x1 <<  4) // (TWI) Slave Access
+#define AT91C_TWI_GCACC           (0x1 <<  5) // (TWI) General Call Access
+#define AT91C_TWI_OVRE            (0x1 <<  6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE            (0x1 <<  7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK            (0x1 <<  8) // (TWI) Not Acknowledged
+#define AT91C_TWI_ARBLST          (0x1 <<  9) // (TWI) Arbitration Lost
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TC structure ***
+#define TC_CCR          ( 0) // Channel Control Register
+#define TC_CMR          ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
+#define TC_CV           (16) // Counter Value
+#define TC_RA           (20) // Register A
+#define TC_RB           (24) // Register B
+#define TC_RC           (28) // Register C
+#define TC_SR           (32) // Status Register
+#define TC_IER          (36) // Interrupt Enable Register
+#define TC_IDR          (40) // Interrupt Disable Register
+#define TC_IMR          (44) // Interrupt Mask Register
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN            (0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS           (0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG            (0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS             (0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI             (0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST            (0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_LDBDIS           (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_CPCDIS           (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_ETRGEDG          (0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG          (0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_ABETRG           (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_EEVT             (0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_NONE                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_RISING               (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_FALLING              (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_BOTH                 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ENETRG           (0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL          (0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG           (0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE             (0x1 << 15) // (TC) 
+#define AT91C_TC_LDRA             (0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPA             (0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRB             (0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC             (0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_AEEVT            (0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG           (0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB             (0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC             (0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT            (0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG           (0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS            (0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS            (0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS             (0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS             (0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS             (0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS            (0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS            (0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRCS            (0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_ETRGS            (0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA            (0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB            (0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TCB structure ***
+#define TCB_TC0         ( 0) // TC Channel 0
+#define TCB_TC1         (64) // TC Channel 1
+#define TCB_TC2         (128) // TC Channel 2
+#define TCB_BCR         (192) // TC Block Control Register
+#define TCB_BMR         (196) // TC Block Mode Register
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC            (0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S         (0x1 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S         (0x1 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S         (0x1 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA2                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PWMC_CH structure ***
+#define PWMC_CMR        ( 0) // Channel Mode Register
+#define PWMC_CDTYR      ( 4) // Channel Duty Cycle Register
+#define PWMC_CPRDR      ( 8) // Channel Period Register
+#define PWMC_CCNTR      (12) // Channel Counter Register
+#define PWMC_CUPDR      (16) // Channel Update Register
+#define PWMC_Reserved   (20) // Reserved
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+#define AT91C_PWMC_CPRE           (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define 	AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH) 
+#define AT91C_PWMC_CALG           (0x1 <<  8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL           (0x1 <<  9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD            (0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+#define AT91C_PWMC_CDTY           (0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+#define AT91C_PWMC_CPRD           (0x0 <<  0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+#define AT91C_PWMC_CCNT           (0x0 <<  0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+#define AT91C_PWMC_CUPD           (0x0 <<  0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PWMC structure ***
+#define PWMC_MR         ( 0) // PWMC Mode Register
+#define PWMC_ENA        ( 4) // PWMC Enable Register
+#define PWMC_DIS        ( 8) // PWMC Disable Register
+#define PWMC_SR         (12) // PWMC Status Register
+#define PWMC_IER        (16) // PWMC Interrupt Enable Register
+#define PWMC_IDR        (20) // PWMC Interrupt Disable Register
+#define PWMC_IMR        (24) // PWMC Interrupt Mask Register
+#define PWMC_ISR        (28) // PWMC Interrupt Status Register
+#define PWMC_VR         (252) // PWMC Version Register
+#define PWMC_CH         (512) // PWMC Channel 0
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+#define AT91C_PWMC_DIVA           (0xFF <<  0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA           (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
+#define 	AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC) 
+#define AT91C_PWMC_DIVB           (0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB           (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define 	AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC) 
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+#define AT91C_PWMC_CHID0          (0x1 <<  0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1          (0x1 <<  1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2          (0x1 <<  2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3          (0x1 <<  3) // (PWMC) Channel ID 3
+#define AT91C_PWMC_CHID4          (0x1 <<  4) // (PWMC) Channel ID 4
+#define AT91C_PWMC_CHID5          (0x1 <<  5) // (PWMC) Channel ID 5
+#define AT91C_PWMC_CHID6          (0x1 <<  6) // (PWMC) Channel ID 6
+#define AT91C_PWMC_CHID7          (0x1 <<  7) // (PWMC) Channel ID 7
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+// *** Register offset in AT91S_UDP structure ***
+#define UDP_NUM         ( 0) // Frame Number Register
+#define UDP_GLBSTATE    ( 4) // Global State Register
+#define UDP_FADDR       ( 8) // Function Address Register
+#define UDP_IER         (16) // Interrupt Enable Register
+#define UDP_IDR         (20) // Interrupt Disable Register
+#define UDP_IMR         (24) // Interrupt Mask Register
+#define UDP_ISR         (28) // Interrupt Status Register
+#define UDP_ICR         (32) // Interrupt Clear Register
+#define UDP_RSTEP       (40) // Reset Endpoint Register
+#define UDP_CSR         (48) // Endpoint Control and Status Register
+#define UDP_FDR         (80) // Endpoint FIFO Data Register
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+#define AT91C_UDP_FRM_NUM         (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR         (0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK          (0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+#define AT91C_UDP_FADDEN          (0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG           (0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_RMWUPE          (0x1 <<  2) // (UDP) Remote Wake Up Enable
+#define AT91C_UDP_RSMINPR         (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+#define AT91C_UDP_FADD            (0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN             (0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+#define AT91C_UDP_EPINT0          (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1          (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2          (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3          (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4          (0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5          (0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_EPINT6          (0x1 <<  6) // (UDP) Endpoint 6 Interrupt
+#define AT91C_UDP_EPINT7          (0x1 <<  7) // (UDP) Endpoint 7 Interrupt
+#define AT91C_UDP_RXSUSP          (0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM           (0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM          (0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT          (0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP          (0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+#define AT91C_UDP_ENDBUSRES       (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+#define AT91C_UDP_EP0             (0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1             (0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2             (0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3             (0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4             (0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5             (0x1 <<  5) // (UDP) Reset Endpoint 5
+#define AT91C_UDP_EP6             (0x1 <<  6) // (UDP) Reset Endpoint 6
+#define AT91C_UDP_EP7             (0x1 <<  7) // (UDP) Reset Endpoint 7
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+#define AT91C_UDP_TXCOMP          (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0     (0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP         (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR        (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY        (0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL      (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1     (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR             (0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE          (0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE           (0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS           (0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT       (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM7S64
+// *****************************************************************************
+// ========== Register definition for SYSC peripheral ========== 
+#define AT91C_SYSC_SYSC_VRPM      (0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_ICCR            (0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_IECR            (0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_SMR             (0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_ISCR            (0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_EOICR           (0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_DCR             (0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_FFER            (0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_SVR             (0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_SPU             (0xFFFFF134) // (AIC) Spurious Vector Register
+#define AT91C_AIC_FFDR            (0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_FVR             (0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_FFSR            (0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_IMR             (0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_ISR             (0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IVR             (0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_IDCR            (0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_CISR            (0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IPR             (0xFFFFF10C) // (AIC) Interrupt Pending Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_C2R            (0xFFFFF244) // (DBGU) Chip ID2 Register
+#define AT91C_DBGU_THR            (0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_CSR            (0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_IDR            (0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_MR             (0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_FNTR           (0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_C1R            (0xFFFFF240) // (DBGU) Chip ID1 Register
+#define AT91C_DBGU_BRGR           (0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_RHR            (0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IMR            (0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_IER            (0xFFFFF208) // (DBGU) Interrupt Enable Register
+#define AT91C_DBGU_CR             (0xFFFFF200) // (DBGU) Control Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_TNCR           (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+#define AT91C_DBGU_RNCR           (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR           (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR           (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_RCR            (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_TCR            (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RPR            (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_TPR            (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RNPR           (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR           (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_IMR            (0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_IER            (0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_OWDR           (0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_ISR            (0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_PPUDR          (0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_MDSR           (0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_MDER           (0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PER            (0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_PSR            (0xFFFFF408) // (PIOA) PIO Status Register
+#define AT91C_PIOA_OER            (0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_BSR            (0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_PPUER          (0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_MDDR           (0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_PDR            (0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_ODR            (0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_IFDR           (0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_ABSR           (0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_ASR            (0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_PPUSR          (0xFFFFF468) // (PIOA) Pad Pull-up Status Register
+#define AT91C_PIOA_ODSR           (0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_SODR           (0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_IFSR           (0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_IFER           (0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_OSR            (0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_IDR            (0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_PDSR           (0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_CODR           (0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_OWSR           (0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_OWER           (0xFFFFF4A0) // (PIOA) Output Write Enable Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_PLLR           (0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR           (0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+#define AT91C_CKGR_MOR            (0xFFFFFC20) // (CKGR) Main Oscillator Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_SCSR            (0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_SCER            (0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR             (0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IDR             (0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_PCDR            (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCDR            (0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_SR              (0xFFFFFC68) // (PMC) Status Register
+#define AT91C_PMC_IER             (0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_MCKR            (0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_MOR             (0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PCER            (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCSR            (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_PLLR            (0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_MCFR            (0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_PCKR            (0xFFFFFC40) // (PMC) Programmable Clock Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RSR            (0xFFFFFD04) // (RSTC) Reset Status Register
+#define AT91C_RSTC_RMR            (0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RCR            (0xFFFFFD00) // (RSTC) Reset Control Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR           (0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTAR           (0xFFFFFD24) // (RTTC) Real-time Alarm Register
+#define AT91C_RTTC_RTVR           (0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTMR           (0xFFFFFD20) // (RTTC) Real-time Mode Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIIR           (0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PISR           (0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIVR           (0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PIMR           (0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDMR           (0xFFFFFD44) // (WDTC) Watchdog Mode Register
+#define AT91C_WDTC_WDSR           (0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDCR           (0xFFFFFD40) // (WDTC) Watchdog Control Register
+// ========== Register definition for MC peripheral ========== 
+#define AT91C_MC_FCR              (0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_ASR              (0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_FSR              (0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR              (0xFFFFFF60) // (MC) MC Flash Mode Register
+#define AT91C_MC_AASR             (0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_RCR              (0xFFFFFF00) // (MC) MC Remap Control Register
+// ========== Register definition for PDC_SPI peripheral ========== 
+#define AT91C_SPI_PTCR            (0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
+#define AT91C_SPI_TNPR            (0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
+#define AT91C_SPI_RNPR            (0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
+#define AT91C_SPI_TPR             (0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
+#define AT91C_SPI_RPR             (0xFFFE0100) // (PDC_SPI) Receive Pointer Register
+#define AT91C_SPI_PTSR            (0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
+#define AT91C_SPI_TNCR            (0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
+#define AT91C_SPI_RNCR            (0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
+#define AT91C_SPI_TCR             (0xFFFE010C) // (PDC_SPI) Transmit Counter Register
+#define AT91C_SPI_RCR             (0xFFFE0104) // (PDC_SPI) Receive Counter Register
+// ========== Register definition for SPI peripheral ========== 
+#define AT91C_SPI_CSR             (0xFFFE0030) // (SPI) Chip Select Register
+#define AT91C_SPI_IDR             (0xFFFE0018) // (SPI) Interrupt Disable Register
+#define AT91C_SPI_SR              (0xFFFE0010) // (SPI) Status Register
+#define AT91C_SPI_RDR             (0xFFFE0008) // (SPI) Receive Data Register
+#define AT91C_SPI_CR              (0xFFFE0000) // (SPI) Control Register
+#define AT91C_SPI_IMR             (0xFFFE001C) // (SPI) Interrupt Mask Register
+#define AT91C_SPI_IER             (0xFFFE0014) // (SPI) Interrupt Enable Register
+#define AT91C_SPI_TDR             (0xFFFE000C) // (SPI) Transmit Data Register
+#define AT91C_SPI_MR              (0xFFFE0004) // (SPI) Mode Register
+// ========== Register definition for PDC_ADC peripheral ========== 
+#define AT91C_ADC_PTCR            (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR            (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_RNPR            (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_TPR             (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RPR             (0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_PTSR            (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_TNCR            (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNCR            (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_TCR             (0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_RCR             (0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ========== 
+#define AT91C_ADC_IMR             (0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+#define AT91C_ADC_CDR4            (0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR2            (0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR0            (0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR7            (0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR1            (0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_CDR3            (0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR5            (0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_MR              (0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_CDR6            (0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_CR              (0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CHER            (0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR            (0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_IER             (0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_SR              (0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CHDR            (0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_IDR             (0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_LCDR            (0xFFFD8020) // (ADC) ADC Last Converted Data Register
+// ========== Register definition for PDC_SSC peripheral ========== 
+#define AT91C_SSC_PTCR            (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TNPR            (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_RNPR            (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TPR             (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_RPR             (0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_PTSR            (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+#define AT91C_SSC_TNCR            (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RNCR            (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TCR             (0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR             (0xFFFD4104) // (PDC_SSC) Receive Counter Register
+// ========== Register definition for SSC peripheral ========== 
+#define AT91C_SSC_RFMR            (0xFFFD4014) // (SSC) Receive Frame Mode Register
+#define AT91C_SSC_CMR             (0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_IDR             (0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_SR              (0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_RC0R            (0xFFFD4038) // (SSC) Receive Compare 0 Register
+#define AT91C_SSC_RSHR            (0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_RHR             (0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_TCMR            (0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_RCMR            (0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_CR              (0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR             (0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_IER             (0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_RC1R            (0xFFFD403C) // (SSC) Receive Compare 1 Register
+#define AT91C_SSC_TSHR            (0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_THR             (0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_TFMR            (0xFFFD401C) // (SSC) Transmit Frame Mode Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_PTSR            (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNCR            (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_RNCR            (0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_TCR             (0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_RCR             (0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_PTCR            (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TNPR            (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RNPR            (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_TPR             (0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+#define AT91C_US1_RPR             (0xFFFC4100) // (PDC_US1) Receive Pointer Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_XXR             (0xFFFC4048) // (US1) XON_XOFF Register
+#define AT91C_US1_RHR             (0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_IMR             (0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_IER             (0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_CR              (0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_RTOR            (0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_THR             (0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_CSR             (0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR             (0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_FIDI            (0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_BRGR            (0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_TTGR            (0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_IF              (0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER             (0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_MR              (0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_PTCR            (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_TNPR            (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR            (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TPR             (0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RPR             (0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_PTSR            (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR            (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_RNCR            (0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+#define AT91C_US0_TCR             (0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_RCR             (0xFFFC0104) // (PDC_US0) Receive Counter Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_TTGR            (0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_BRGR            (0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_RHR             (0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IMR             (0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_NER             (0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_RTOR            (0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_XXR             (0xFFFC0048) // (US0) XON_XOFF Register
+#define AT91C_US0_FIDI            (0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_CR              (0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IER             (0xFFFC0008) // (US0) Interrupt Enable Register
+#define AT91C_US0_IF              (0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_MR              (0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_IDR             (0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_CSR             (0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_THR             (0xFFFC001C) // (US0) Transmitter Holding Register
+// ========== Register definition for TWI peripheral ========== 
+#define AT91C_TWI_RHR             (0xFFFB8030) // (TWI) Receive Holding Register
+#define AT91C_TWI_IDR             (0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_SR              (0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_CWGR            (0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_SMR             (0xFFFB8008) // (TWI) Slave Mode Register
+#define AT91C_TWI_CR              (0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_THR             (0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IMR             (0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_IER             (0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_IADR            (0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR             (0xFFFB8004) // (TWI) Master Mode Register
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_IMR             (0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_IER             (0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_RC              (0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_RA              (0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_CMR             (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_IDR             (0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_SR              (0xFFFA00A0) // (TC2) Status Register
+#define AT91C_TC2_RB              (0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_CV              (0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_CCR             (0xFFFA0080) // (TC2) Channel Control Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_IMR             (0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_IER             (0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_RC              (0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_RA              (0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_CMR             (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_IDR             (0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR              (0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_RB              (0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CV              (0xFFFA0050) // (TC1) Counter Value
+#define AT91C_TC1_CCR             (0xFFFA0040) // (TC1) Channel Control Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_IMR             (0xFFFA002C) // (TC0) Interrupt Mask Register
+#define AT91C_TC0_IER             (0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RC              (0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RA              (0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_CMR             (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IDR             (0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_SR              (0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RB              (0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CV              (0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_CCR             (0xFFFA0000) // (TC0) Channel Control Register
+// ========== Register definition for TCB peripheral ========== 
+#define AT91C_TCB_BMR             (0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR             (0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for PWMC_CH3 peripheral ========== 
+#define AT91C_CH3_CUPDR           (0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_CH3_CPRDR           (0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_CH3_CMR             (0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+#define AT91C_CH3_Reserved        (0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_CH3_CCNTR           (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_CH3_CDTYR           (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH2 peripheral ========== 
+#define AT91C_CH2_CUPDR           (0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_CH2_CPRDR           (0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_CH2_CMR             (0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_CH2_Reserved        (0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_CH2_CCNTR           (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_CH2_CDTYR           (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ========== 
+#define AT91C_CH1_CUPDR           (0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_CH1_CPRDR           (0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_CH1_CMR             (0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+#define AT91C_CH1_Reserved        (0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_CH1_CCNTR           (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_CH1_CDTYR           (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH0 peripheral ========== 
+#define AT91C_CH0_CUPDR           (0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_CH0_CPRDR           (0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_CH0_CMR             (0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_CH0_Reserved        (0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_CH0_CCNTR           (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+#define AT91C_CH0_CDTYR           (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+// ========== Register definition for PWMC peripheral ========== 
+#define AT91C_PWMC_VR             (0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR            (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_IDR            (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_SR             (0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_ENA            (0xFFFCC004) // (PWMC) PWMC Enable Register
+#define AT91C_PWMC_IMR            (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR             (0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_DIS            (0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER            (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+// ========== Register definition for UDP peripheral ========== 
+#define AT91C_UDP_ISR             (0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_IDR             (0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_GLBSTATE        (0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_FDR             (0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_CSR             (0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_RSTEP           (0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_ICR             (0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_IMR             (0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_IER             (0xFFFB0010) // (UDP) Interrupt Enable Register
+#define AT91C_UDP_FADDR           (0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM             (0xFFFB0000) // (UDP) Frame Number Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_PIO_PA0             (1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_PWM0            (AT91C_PIO_PA0) //  PWM Channel 0
+#define AT91C_PA0_TIOA0           (AT91C_PIO_PA0) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA1             (1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_PWM1            (AT91C_PIO_PA1) //  PWM Channel 1
+#define AT91C_PA1_TIOB0           (AT91C_PIO_PA1) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA10            (1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_DTXD           (AT91C_PIO_PA10) //  DBGU Debug Transmit Data
+#define AT91C_PA10_NPCS2          (AT91C_PIO_PA10) //  SPI Peripheral Chip Select 2
+#define AT91C_PIO_PA11            (1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_NPCS0          (AT91C_PIO_PA11) //  SPI Peripheral Chip Select 0
+#define AT91C_PA11_PWM0           (AT91C_PIO_PA11) //  PWM Channel 0
+#define AT91C_PIO_PA12            (1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_MISO           (AT91C_PIO_PA12) //  SPI Master In Slave
+#define AT91C_PA12_PWM1           (AT91C_PIO_PA12) //  PWM Channel 1
+#define AT91C_PIO_PA13            (1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_MOSI           (AT91C_PIO_PA13) //  SPI Master Out Slave
+#define AT91C_PA13_PWM2           (AT91C_PIO_PA13) //  PWM Channel 2
+#define AT91C_PIO_PA14            (1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_SPCK           (AT91C_PIO_PA14) //  SPI Serial Clock
+#define AT91C_PA14_PWM3           (AT91C_PIO_PA14) //  PWM Channel 3
+#define AT91C_PIO_PA15            (1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_TF             (AT91C_PIO_PA15) //  SSC Transmit Frame Sync
+#define AT91C_PA15_TIOA1          (AT91C_PIO_PA15) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA16            (1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_TK             (AT91C_PIO_PA16) //  SSC Transmit Clock
+#define AT91C_PA16_TIOB1          (AT91C_PIO_PA16) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA17            (1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_TD             (AT91C_PIO_PA17) //  SSC Transmit data
+#define AT91C_PA17_PCK1           (AT91C_PIO_PA17) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA18            (1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_RD             (AT91C_PIO_PA18) //  SSC Receive Data
+#define AT91C_PA18_PCK2           (AT91C_PIO_PA18) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA19            (1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_RK             (AT91C_PIO_PA19) //  SSC Receive Clock
+#define AT91C_PA19_FIQ            (AT91C_PIO_PA19) //  AIC Fast Interrupt Input
+#define AT91C_PIO_PA2             (1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_PWM2            (AT91C_PIO_PA2) //  PWM Channel 2
+#define AT91C_PA2_SCK0            (AT91C_PIO_PA2) //  USART 0 Serial Clock
+#define AT91C_PIO_PA20            (1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_RF             (AT91C_PIO_PA20) //  SSC Receive Frame Sync
+#define AT91C_PA20_IRQ0           (AT91C_PIO_PA20) //  External Interrupt 0
+#define AT91C_PIO_PA21            (1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_RXD1           (AT91C_PIO_PA21) //  USART 1 Receive Data
+#define AT91C_PA21_PCK1           (AT91C_PIO_PA21) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA22            (1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TXD1           (AT91C_PIO_PA22) //  USART 1 Transmit Data
+#define AT91C_PA22_NPCS3          (AT91C_PIO_PA22) //  SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA23            (1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_SCK1           (AT91C_PIO_PA23) //  USART 1 Serial Clock
+#define AT91C_PA23_PWM0           (AT91C_PIO_PA23) //  PWM Channel 0
+#define AT91C_PIO_PA24            (1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RTS1           (AT91C_PIO_PA24) //  USART 1 Ready To Send
+#define AT91C_PA24_PWM1           (AT91C_PIO_PA24) //  PWM Channel 1
+#define AT91C_PIO_PA25            (1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_CTS1           (AT91C_PIO_PA25) //  USART 1 Clear To Send
+#define AT91C_PA25_PWM2           (AT91C_PIO_PA25) //  PWM Channel 2
+#define AT91C_PIO_PA26            (1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_DCD1           (AT91C_PIO_PA26) //  USART 1 Data Carrier Detect
+#define AT91C_PA26_TIOA2          (AT91C_PIO_PA26) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA27            (1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DTR1           (AT91C_PIO_PA27) //  USART 1 Data Terminal ready
+#define AT91C_PA27_TIOB2          (AT91C_PIO_PA27) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA28            (1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DSR1           (AT91C_PIO_PA28) //  USART 1 Data Set ready
+#define AT91C_PA28_TCLK1          (AT91C_PIO_PA28) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PA29            (1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_RI1            (AT91C_PIO_PA29) //  USART 1 Ring Indicator
+#define AT91C_PA29_TCLK2          (AT91C_PIO_PA29) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PA3             (1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_TWD             (AT91C_PIO_PA3) //  TWI Two-wire Serial Data
+#define AT91C_PA3_NPCS3           (AT91C_PIO_PA3) //  SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA30            (1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ1           (AT91C_PIO_PA30) //  External Interrupt 1
+#define AT91C_PA30_NPCS2          (AT91C_PIO_PA30) //  SPI Peripheral Chip Select 2
+#define AT91C_PIO_PA31            (1 << 31) // Pin Controlled by PA31
+#define AT91C_PA31_NPCS1          (AT91C_PIO_PA31) //  SPI Peripheral Chip Select 1
+#define AT91C_PA31_PCK2           (AT91C_PIO_PA31) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4             (1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_TWCK            (AT91C_PIO_PA4) //  TWI Two-wire Serial Clock
+#define AT91C_PA4_TCLK0           (AT91C_PIO_PA4) //  Timer Counter 0 external clock input
+#define AT91C_PIO_PA5             (1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD0            (AT91C_PIO_PA5) //  USART 0 Receive Data
+#define AT91C_PA5_NPCS3           (AT91C_PIO_PA5) //  SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA6             (1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD0            (AT91C_PIO_PA6) //  USART 0 Transmit Data
+#define AT91C_PA6_PCK0            (AT91C_PIO_PA6) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PA7             (1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_RTS0            (AT91C_PIO_PA7) //  USART 0 Ready To Send
+#define AT91C_PA7_PWM3            (AT91C_PIO_PA7) //  PWM Channel 3
+#define AT91C_PIO_PA8             (1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_CTS0            (AT91C_PIO_PA8) //  USART 0 Clear To Send
+#define AT91C_PA8_ADTRG           (AT91C_PIO_PA8) //  ADC External Trigger
+#define AT91C_PIO_PA9             (1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_DRXD            (AT91C_PIO_PA9) //  DBGU Debug Receive Data
+#define AT91C_PA9_NPCS1           (AT91C_PIO_PA9) //  SPI Peripheral Chip Select 1
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_ID_FIQ              ( 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS              ( 1) // System Peripheral
+#define AT91C_ID_PIOA             ( 2) // Parallel IO Controller
+#define AT91C_ID_3_Reserved       ( 3) // Reserved
+#define AT91C_ID_ADC              ( 4) // Analog-to-Digital Converter
+#define AT91C_ID_SPI              ( 5) // Serial Peripheral Interface
+#define AT91C_ID_US0              ( 6) // USART 0
+#define AT91C_ID_US1              ( 7) // USART 1
+#define AT91C_ID_SSC              ( 8) // Serial Synchronous Controller
+#define AT91C_ID_TWI              ( 9) // Two-Wire Interface
+#define AT91C_ID_PWMC             (10) // PWM Controller
+#define AT91C_ID_UDP              (11) // USB Device Port
+#define AT91C_ID_TC0              (12) // Timer Counter 0
+#define AT91C_ID_TC1              (13) // Timer Counter 1
+#define AT91C_ID_TC2              (14) // Timer Counter 2
+#define AT91C_ID_15_Reserved      (15) // Reserved
+#define AT91C_ID_16_Reserved      (16) // Reserved
+#define AT91C_ID_17_Reserved      (17) // Reserved
+#define AT91C_ID_18_Reserved      (18) // Reserved
+#define AT91C_ID_19_Reserved      (19) // Reserved
+#define AT91C_ID_20_Reserved      (20) // Reserved
+#define AT91C_ID_21_Reserved      (21) // Reserved
+#define AT91C_ID_22_Reserved      (22) // Reserved
+#define AT91C_ID_23_Reserved      (23) // Reserved
+#define AT91C_ID_24_Reserved      (24) // Reserved
+#define AT91C_ID_25_Reserved      (25) // Reserved
+#define AT91C_ID_26_Reserved      (26) // Reserved
+#define AT91C_ID_27_Reserved      (27) // Reserved
+#define AT91C_ID_28_Reserved      (28) // Reserved
+#define AT91C_ID_29_Reserved      (29) // Reserved
+#define AT91C_ID_IRQ0             (30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1             (31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_BASE_SYSC           (0xFFFFF000) // (SYSC) Base Address
+#define AT91C_BASE_AIC            (0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_DBGU           (0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PDC_DBGU       (0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_PIOA           (0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_CKGR           (0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC            (0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC           (0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC           (0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC           (0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC           (0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_MC             (0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI        (0xFFFE0100) // (PDC_SPI) Base Address
+#define AT91C_BASE_SPI            (0xFFFE0000) // (SPI) Base Address
+#define AT91C_BASE_PDC_ADC        (0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC            (0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_SSC        (0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC            (0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_PDC_US1        (0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1            (0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0        (0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0            (0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_TWI            (0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_TC2            (0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TC1            (0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC0            (0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TCB            (0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_PWMC_CH3       (0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2       (0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1       (0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0       (0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC           (0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP            (0xFFFB0000) // (UDP) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_ISRAM	              (0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE	         (0x00004000) // Internal SRAM size in byte (16 Kbyte)
+#define AT91C_IFLASH	             (0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE	        (0x00010000) // Internal ROM size in byte (64 Kbyte)
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h
new file mode 100644
index 0000000..ae4f35f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h
@@ -0,0 +1,2715 @@
+//  ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+//  ----------------------------------------------------------------------------
+//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  ----------------------------------------------------------------------------
+// File Name           : AT91SAM7X128.h
+// Object              : AT91SAM7X128 definitions
+// Generated           : AT91 SW Application Group  05/20/2005 (16:22:23)
+// 
+// CVS Reference       : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005//
+// CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
+// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
+// CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
+// CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
+// CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
+// CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
+// CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
+// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
+// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
+// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
+// CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
+// CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
+// CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+//  ----------------------------------------------------------------------------
+
+#ifndef AT91SAM7X128_H
+#define AT91SAM7X128_H
+
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYS {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+	AT91_REG	 Reserved2[45]; 	// 
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved3[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved4[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+	AT91_REG	 Reserved5[54]; 	// 
+	AT91_REG	 PIOA_PER; 	// PIO Enable Register
+	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOA_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved6[1]; 	// 
+	AT91_REG	 PIOA_OER; 	// Output Enable Register
+	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOA_OSR; 	// Output Status Register
+	AT91_REG	 Reserved7[1]; 	// 
+	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved8[1]; 	// 
+	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved9[1]; 	// 
+	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved10[1]; 	// 
+	AT91_REG	 PIOA_ASR; 	// Select A Register
+	AT91_REG	 PIOA_BSR; 	// Select B Register
+	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved11[9]; 	// 
+	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved12[85]; 	// 
+	AT91_REG	 PIOB_PER; 	// PIO Enable Register
+	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOB_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved13[1]; 	// 
+	AT91_REG	 PIOB_OER; 	// Output Enable Register
+	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOB_OSR; 	// Output Status Register
+	AT91_REG	 Reserved14[1]; 	// 
+	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved15[1]; 	// 
+	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved16[1]; 	// 
+	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved17[1]; 	// 
+	AT91_REG	 PIOB_ASR; 	// Select A Register
+	AT91_REG	 PIOB_BSR; 	// Select B Register
+	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved18[9]; 	// 
+	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved19[341]; 	// 
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved20[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved21[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved22[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved23[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved24[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved25[36]; 	// 
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+	AT91_REG	 Reserved26[5]; 	// 
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+	AT91_REG	 Reserved27[5]; 	// 
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_SYS, *AT91PS_SYS;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
+#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
+	AT91_REG	 PDC_RCR; 	// Receive Counter Register
+	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
+	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved0[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved1[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+	AT91_REG	 PIO_PER; 	// PIO Enable Register
+	AT91_REG	 PIO_PDR; 	// PIO Disable Register
+	AT91_REG	 PIO_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PIO_OER; 	// Output Enable Register
+	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIO_OSR; 	// Output Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PIO_SODR; 	// Set Output Data Register
+	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved3[1]; 	// 
+	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved4[1]; 	// 
+	AT91_REG	 PIO_ASR; 	// Select A Register
+	AT91_REG	 PIO_BSR; 	// Select B Register
+	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved5[9]; 	// 
+	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
+	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 CKGR_PLLR; 	// PLL Register
+} AT91S_CKGR, *AT91PS_CKGR;
+
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
+#define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
+#define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
+#define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved3[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved4[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RSTC {
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
+
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define 	AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RTTC {
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PITC {
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_WDTC {
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_VREG {
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_VREG, *AT91PS_VREG;
+
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
+#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+	AT91_REG	 MC_RCR; 	// MC Remap Control Register
+	AT91_REG	 MC_ASR; 	// MC Abort Status Register
+	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
+	AT91_REG	 Reserved0[21]; 	// 
+	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
+	AT91_REG	 MC_FCR; 	// MC Flash Command Register
+	AT91_REG	 MC_FSR; 	// MC Flash Status Register
+} AT91S_MC, *AT91PS_MC;
+
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
+#define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
+#define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
+#define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
+#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
+#define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
+#define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
+#define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
+#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
+#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
+#define 	AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
+#define 	AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
+#define 	AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
+#define 	AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
+#define 	AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define 	AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define 	AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define 	AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
+#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+	AT91_REG	 SPI_CR; 	// Control Register
+	AT91_REG	 SPI_MR; 	// Mode Register
+	AT91_REG	 SPI_RDR; 	// Receive Data Register
+	AT91_REG	 SPI_TDR; 	// Transmit Data Register
+	AT91_REG	 SPI_SR; 	// Status Register
+	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
+	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
+	AT91_REG	 Reserved1[48]; 	// 
+	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
+	AT91_REG	 SPI_RCR; 	// Receive Counter Register
+	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
+	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+	AT91_REG	 US_CR; 	// Control Register
+	AT91_REG	 US_MR; 	// Mode Register
+	AT91_REG	 US_IER; 	// Interrupt Enable Register
+	AT91_REG	 US_IDR; 	// Interrupt Disable Register
+	AT91_REG	 US_IMR; 	// Interrupt Mask Register
+	AT91_REG	 US_CSR; 	// Channel Status Register
+	AT91_REG	 US_RHR; 	// Receiver Holding Register
+	AT91_REG	 US_THR; 	// Transmitter Holding Register
+	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
+	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
+	AT91_REG	 Reserved0[5]; 	// 
+	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
+	AT91_REG	 US_NER; 	// Nb Errors Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 US_IF; 	// IRDA_FILTER Register
+	AT91_REG	 Reserved2[44]; 	// 
+	AT91_REG	 US_RPR; 	// Receive Pointer Register
+	AT91_REG	 US_RCR; 	// Receive Counter Register
+	AT91_REG	 US_TPR; 	// Transmit Pointer Register
+	AT91_REG	 US_TCR; 	// Transmit Counter Register
+	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+	AT91_REG	 SSC_CR; 	// Control Register
+	AT91_REG	 SSC_CMR; 	// Clock Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
+	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
+	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
+	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
+	AT91_REG	 SSC_RHR; 	// Receive Holding Register
+	AT91_REG	 SSC_THR; 	// Transmit Holding Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
+	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 SSC_SR; 	// Status Register
+	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
+	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved3[44]; 	// 
+	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
+	AT91_REG	 SSC_RCR; 	// Receive Counter Register
+	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
+	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+	AT91_REG	 TWI_CR; 	// Control Register
+	AT91_REG	 TWI_MMR; 	// Master Mode Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 TWI_IADR; 	// Internal Address Register
+	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
+	AT91_REG	 Reserved1[3]; 	// 
+	AT91_REG	 TWI_SR; 	// Status Register
+	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
+	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TWI_RHR; 	// Receive Holding Register
+	AT91_REG	 TWI_THR; 	// Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
+
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC_CH {
+	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
+	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
+	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
+	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
+	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
+	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
+
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define 	AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH) 
+#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC {
+	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
+	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
+	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
+	AT91_REG	 PWMC_SR; 	// PWMC Status Register
+	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
+	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
+	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
+	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
+	AT91_REG	 Reserved0[55]; 	// 
+	AT91_REG	 PWMC_VR; 	// PWMC Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
+} AT91S_PWMC, *AT91PS_PWMC;
+
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
+#define 	AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC) 
+#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define 	AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC) 
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+	AT91_REG	 UDP_NUM; 	// Frame Number Register
+	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
+	AT91_REG	 UDP_FADDR; 	// Function Address Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
+	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
+	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
+	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
+	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
+	AT91_REG	 Reserved4[3]; 	// 
+	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
+
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_ESR         ((unsigned int) 0x1 <<  2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+#define AT91C_UDP_TXVDIS      ((unsigned int) 0x1 <<  8) // (UDP) 
+#define AT91C_UDP_PUON        ((unsigned int) 0x1 <<  9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+	AT91_REG	 TC_CCR; 	// Channel Control Register
+	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TC_CV; 	// Counter Value
+	AT91_REG	 TC_RA; 	// Register A
+	AT91_REG	 TC_RB; 	// Register B
+	AT91_REG	 TC_RC; 	// Register C
+	AT91_REG	 TC_SR; 	// Status Register
+	AT91_REG	 TC_IER; 	// Interrupt Enable Register
+	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_TIOB                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_XC0                  ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC1                  ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC2                  ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) 
+#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRGS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA       ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+	AT91S_TC	 TCB_TC0; 	// TC Channel 0
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91S_TC	 TCB_TC1; 	// TC Channel 1
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91S_TC	 TCB_TC2; 	// TC Channel 2
+	AT91_REG	 Reserved2[4]; 	// 
+	AT91_REG	 TCB_BCR; 	// TC Block Control Register
+	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x3 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x3 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x3 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA1                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN_MB {
+	AT91_REG	 CAN_MB_MMR; 	// MailBox Mode Register
+	AT91_REG	 CAN_MB_MAM; 	// MailBox Acceptance Mask Register
+	AT91_REG	 CAN_MB_MID; 	// MailBox ID Register
+	AT91_REG	 CAN_MB_MFID; 	// MailBox Family ID Register
+	AT91_REG	 CAN_MB_MSR; 	// MailBox Status Register
+	AT91_REG	 CAN_MB_MDL; 	// MailBox Data Low Register
+	AT91_REG	 CAN_MB_MDH; 	// MailBox Data High Register
+	AT91_REG	 CAN_MB_MCR; 	// MailBox Control Register
+} AT91S_CAN_MB, *AT91PS_CAN_MB;
+
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
+#define AT91C_CAN_MTIMEMARK   ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR       ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT         ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define 	AT91C_CAN_MOT_DIS                  ((unsigned int) 0x0 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RX                   ((unsigned int) 0x1 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RXOVERWRITE          ((unsigned int) 0x2 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_TX                   ((unsigned int) 0x3 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_CONSUMER             ((unsigned int) 0x4 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_PRODUCER             ((unsigned int) 0x5 << 24) // (CAN_MB) 
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
+#define AT91C_CAN_MIDvB       ((unsigned int) 0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA       ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE        ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
+#define AT91C_CAN_MTIMESTAMP  ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC        ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR        ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT        ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI         ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
+#define AT91C_CAN_MACR        ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN {
+	AT91_REG	 CAN_MR; 	// Mode Register
+	AT91_REG	 CAN_IER; 	// Interrupt Enable Register
+	AT91_REG	 CAN_IDR; 	// Interrupt Disable Register
+	AT91_REG	 CAN_IMR; 	// Interrupt Mask Register
+	AT91_REG	 CAN_SR; 	// Status Register
+	AT91_REG	 CAN_BR; 	// Baudrate Register
+	AT91_REG	 CAN_TIM; 	// Timer Register
+	AT91_REG	 CAN_TIMESTP; 	// Time Stamp Register
+	AT91_REG	 CAN_ECR; 	// Error Counter Register
+	AT91_REG	 CAN_TCR; 	// Transfer Command Register
+	AT91_REG	 CAN_ACR; 	// Abort Command Register
+	AT91_REG	 Reserved0[52]; 	// 
+	AT91_REG	 CAN_VR; 	// Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_CAN_MB	 CAN_MB0; 	// CAN Mailbox 0
+	AT91S_CAN_MB	 CAN_MB1; 	// CAN Mailbox 1
+	AT91S_CAN_MB	 CAN_MB2; 	// CAN Mailbox 2
+	AT91S_CAN_MB	 CAN_MB3; 	// CAN Mailbox 3
+	AT91S_CAN_MB	 CAN_MB4; 	// CAN Mailbox 4
+	AT91S_CAN_MB	 CAN_MB5; 	// CAN Mailbox 5
+	AT91S_CAN_MB	 CAN_MB6; 	// CAN Mailbox 6
+	AT91S_CAN_MB	 CAN_MB7; 	// CAN Mailbox 7
+	AT91S_CAN_MB	 CAN_MB8; 	// CAN Mailbox 8
+	AT91S_CAN_MB	 CAN_MB9; 	// CAN Mailbox 9
+	AT91S_CAN_MB	 CAN_MB10; 	// CAN Mailbox 10
+	AT91S_CAN_MB	 CAN_MB11; 	// CAN Mailbox 11
+	AT91S_CAN_MB	 CAN_MB12; 	// CAN Mailbox 12
+	AT91S_CAN_MB	 CAN_MB13; 	// CAN Mailbox 13
+	AT91S_CAN_MB	 CAN_MB14; 	// CAN Mailbox 14
+	AT91S_CAN_MB	 CAN_MB15; 	// CAN Mailbox 15
+} AT91S_CAN, *AT91PS_CAN;
+
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
+#define AT91C_CAN_CANEN       ((unsigned int) 0x1 <<  0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM         ((unsigned int) 0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM         ((unsigned int) 0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL         ((unsigned int) 0x1 <<  3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF        ((unsigned int) 0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM         ((unsigned int) 0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ      ((unsigned int) 0x1 <<  6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT        ((unsigned int) 0x1 <<  7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
+#define AT91C_CAN_MB0         ((unsigned int) 0x1 <<  0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1         ((unsigned int) 0x1 <<  1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2         ((unsigned int) 0x1 <<  2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3         ((unsigned int) 0x1 <<  3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4         ((unsigned int) 0x1 <<  4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5         ((unsigned int) 0x1 <<  5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6         ((unsigned int) 0x1 <<  6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7         ((unsigned int) 0x1 <<  7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8         ((unsigned int) 0x1 <<  8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9         ((unsigned int) 0x1 <<  9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10        ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11        ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12        ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13        ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14        ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15        ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA        ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN        ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP        ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF        ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP       ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP      ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF        ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP        ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR        ((unsigned int) 0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR        ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR        ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR        ((unsigned int) 0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR        ((unsigned int) 0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
+#define AT91C_CAN_RBSY        ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY        ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY        ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
+#define AT91C_CAN_PHASE2      ((unsigned int) 0x7 <<  0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1      ((unsigned int) 0x7 <<  4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG      ((unsigned int) 0x7 <<  8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC        ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP         ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP         ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
+#define AT91C_CAN_TIMER       ((unsigned int) 0xFFFF <<  0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
+#define AT91C_CAN_REC         ((unsigned int) 0xFF <<  0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC         ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
+#define AT91C_CAN_TIMRST      ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// *****************************************************************************
+typedef struct _AT91S_EMAC {
+	AT91_REG	 EMAC_NCR; 	// Network Control Register
+	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
+	AT91_REG	 EMAC_NSR; 	// Network Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
+	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
+	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
+	AT91_REG	 EMAC_RSR; 	// Receive Status Register
+	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
+	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
+	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
+	AT91_REG	 EMAC_PTR; 	// Pause Time Register
+	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
+	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
+	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
+	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
+	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
+	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
+	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
+	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
+	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
+	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
+	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
+	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
+	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
+	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
+	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
+	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
+	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
+	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
+	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
+	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
+	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
+	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
+	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
+	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
+	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
+	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
+	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
+	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
+	AT91_REG	 Reserved1[13]; 	// 
+	AT91_REG	 EMAC_REV; 	// Revision Register
+} AT91S_EMAC, *AT91PS_EMAC;
+
+// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local. 
+#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable. 
+#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable. 
+#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable. 
+#define AT91C_EMAC_CLRSTAT    ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers. 
+#define AT91C_EMAC_INCSTAT    ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers. 
+#define AT91C_EMAC_WESTAT     ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers. 
+#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure. 
+#define AT91C_EMAC_TSTART     ((unsigned int) 0x1 <<  9) // (EMAC) Start Transmission. 
+#define AT91C_EMAC_THALT      ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. 
+#define AT91C_EMAC_TPFR       ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame 
+#define AT91C_EMAC_TZQ        ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed. 
+#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex. 
+#define AT91C_EMAC_JFRAME     ((unsigned int) 0x1 <<  3) // (EMAC) Jumbo Frames. 
+#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames. 
+#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast. 
+#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable. 
+#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes. 
+#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable. 
+#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC) 
+#define 	AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
+#define 	AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
+#define 	AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
+#define 	AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PAE        ((unsigned int) 0x1 << 13) // (EMAC) 
+#define AT91C_EMAC_RBOF       ((unsigned int) 0x3 << 14) // (EMAC) 
+#define 	AT91C_EMAC_RBOF_OFFSET_0             ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_1             ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_2             ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_3             ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE       ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS      ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD      ((unsigned int) 0x1 << 18) // (EMAC) 
+#define AT91C_EMAC_IRXFCS     ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+#define AT91C_EMAC_LINKR      ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+#define AT91C_EMAC_UBR        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RLES       ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TGO        ((unsigned int) 0x1 <<  3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX        ((unsigned int) 0x1 <<  4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC) 
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+#define AT91C_EMAC_MFD        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_RCOMP      ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RXUBR      ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TXUBR      ((unsigned int) 0x1 <<  3) // (EMAC) 
+#define AT91C_EMAC_TUNDR      ((unsigned int) 0x1 <<  4) // (EMAC) 
+#define AT91C_EMAC_RLEX       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_TXERR      ((unsigned int) 0x1 <<  6) // (EMAC) 
+#define AT91C_EMAC_TCOMP      ((unsigned int) 0x1 <<  7) // (EMAC) 
+#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC) 
+#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC) 
+#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC) 
+#define AT91C_EMAC_PFRE       ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PTZ        ((unsigned int) 0x1 << 13) // (EMAC) 
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC) 
+#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC) 
+#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC) 
+#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC) 
+#define AT91C_EMAC_SOF        ((unsigned int) 0x3 << 30) // (EMAC) 
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+#define AT91C_EMAC_RMII       ((unsigned int) 0x1 <<  0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+#define AT91C_EMAC_IP         ((unsigned int) 0xFFFF <<  0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG        ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP        ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1        ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+#define AT91C_EMAC_REVREF     ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_PARTREF    ((unsigned int) 0xFFFF << 16) // (EMAC) 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// *****************************************************************************
+typedef struct _AT91S_ADC {
+	AT91_REG	 ADC_CR; 	// ADC Control Register
+	AT91_REG	 ADC_MR; 	// ADC Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
+	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
+	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
+	AT91_REG	 ADC_SR; 	// ADC Status Register
+	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
+	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
+	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
+	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
+	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
+	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
+	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
+	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
+	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
+	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
+	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
+	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
+	AT91_REG	 Reserved1[44]; 	// 
+	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
+	AT91_REG	 ADC_RCR; 	// Receive Counter Register
+	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
+	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
+
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
+#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
+#define 	AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define 	AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
+#define 	AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
+#define 	AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
+#define 	AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
+#define 	AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
+#define 	AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
+#define 	AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
+#define 	AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
+#define 	AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
+#define 	AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define 	AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
+#define 	AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
+// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
+#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
+#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
+#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
+#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
+#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
+#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
+#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
+// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_AES {
+	AT91_REG	 AES_CR; 	// Control Register
+	AT91_REG	 AES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AES_IER; 	// Interrupt Enable Register
+	AT91_REG	 AES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 AES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AES_ISR; 	// Interrupt Status Register
+	AT91_REG	 AES_KEYWxR[4]; 	// Key Word x Register
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91_REG	 AES_IDATAxR[4]; 	// Input Data x Register
+	AT91_REG	 AES_ODATAxR[4]; 	// Output Data x Register
+	AT91_REG	 AES_IVxR[4]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved2[35]; 	// 
+	AT91_REG	 AES_VR; 	// AES Version Register
+	AT91_REG	 AES_RPR; 	// Receive Pointer Register
+	AT91_REG	 AES_RCR; 	// Receive Counter Register
+	AT91_REG	 AES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 AES_TCR; 	// Transmit Counter Register
+	AT91_REG	 AES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 AES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 AES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 AES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 AES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 AES_PTSR; 	// PDC Transfer Status Register
+} AT91S_AES, *AT91PS_AES;
+
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
+#define AT91C_AES_START       ((unsigned int) 0x1 <<  0) // (AES) Starts Processing
+#define AT91C_AES_SWRST       ((unsigned int) 0x1 <<  8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED    ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
+#define AT91C_AES_CIPHER      ((unsigned int) 0x1 <<  0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY     ((unsigned int) 0xF <<  4) // (AES) Processing Delay
+#define AT91C_AES_SMOD        ((unsigned int) 0x3 <<  8) // (AES) Start Mode
+#define 	AT91C_AES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define 	AT91C_AES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define 	AT91C_AES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD       ((unsigned int) 0x7 << 12) // (AES) Operation Mode
+#define 	AT91C_AES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define 	AT91C_AES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define 	AT91C_AES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
+#define 	AT91C_AES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define 	AT91C_AES_OPMOD_CTR                  ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD         ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS        ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
+#define 	AT91C_AES_CFBS_128_BIT              ((unsigned int) 0x0 << 16) // (AES) 128-bit.
+#define 	AT91C_AES_CFBS_64_BIT               ((unsigned int) 0x1 << 16) // (AES) 64-bit.
+#define 	AT91C_AES_CFBS_32_BIT               ((unsigned int) 0x2 << 16) // (AES) 32-bit.
+#define 	AT91C_AES_CFBS_16_BIT               ((unsigned int) 0x3 << 16) // (AES) 16-bit.
+#define 	AT91C_AES_CFBS_8_BIT                ((unsigned int) 0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY        ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE       ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
+#define 	AT91C_AES_CTYPE_TYPE1_EN             ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE2_EN             ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE3_EN             ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE4_EN             ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE5_EN             ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_AES_DATRDY      ((unsigned int) 0x1 <<  0) // (AES) DATRDY
+#define AT91C_AES_ENDRX       ((unsigned int) 0x1 <<  1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX       ((unsigned int) 0x1 <<  2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF      ((unsigned int) 0x1 <<  3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE      ((unsigned int) 0x1 <<  4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD        ((unsigned int) 0x1 <<  8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_AES_URAT        ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define 	AT91C_AES_URAT_WO_REG_READ          ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_TDES {
+	AT91_REG	 TDES_CR; 	// Control Register
+	AT91_REG	 TDES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TDES_IER; 	// Interrupt Enable Register
+	AT91_REG	 TDES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TDES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TDES_ISR; 	// Interrupt Status Register
+	AT91_REG	 TDES_KEY1WxR[2]; 	// Key 1 Word x Register
+	AT91_REG	 TDES_KEY2WxR[2]; 	// Key 2 Word x Register
+	AT91_REG	 TDES_KEY3WxR[2]; 	// Key 3 Word x Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 TDES_IDATAxR[2]; 	// Input Data x Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 TDES_ODATAxR[2]; 	// Output Data x Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 TDES_IVxR[2]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved4[37]; 	// 
+	AT91_REG	 TDES_VR; 	// TDES Version Register
+	AT91_REG	 TDES_RPR; 	// Receive Pointer Register
+	AT91_REG	 TDES_RCR; 	// Receive Counter Register
+	AT91_REG	 TDES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 TDES_TCR; 	// Transmit Counter Register
+	AT91_REG	 TDES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 TDES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 TDES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 TDES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 TDES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 TDES_PTSR; 	// PDC Transfer Status Register
+} AT91S_TDES, *AT91PS_TDES;
+
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
+#define AT91C_TDES_START      ((unsigned int) 0x1 <<  0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST      ((unsigned int) 0x1 <<  8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
+#define AT91C_TDES_CIPHER     ((unsigned int) 0x1 <<  0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD    ((unsigned int) 0x1 <<  1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD     ((unsigned int) 0x1 <<  4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD       ((unsigned int) 0x3 <<  8) // (TDES) Start Mode
+#define 	AT91C_TDES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define 	AT91C_TDES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define 	AT91C_TDES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD      ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
+#define 	AT91C_TDES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define 	AT91C_TDES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define 	AT91C_TDES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define 	AT91C_TDES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD        ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS       ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define 	AT91C_TDES_CFBS_64_BIT               ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
+#define 	AT91C_TDES_CFBS_32_BIT               ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
+#define 	AT91C_TDES_CFBS_16_BIT               ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
+#define 	AT91C_TDES_CFBS_8_BIT                ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_TDES_DATRDY     ((unsigned int) 0x1 <<  0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX      ((unsigned int) 0x1 <<  1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX      ((unsigned int) 0x1 <<  2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF     ((unsigned int) 0x1 <<  3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE     ((unsigned int) 0x1 <<  4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD       ((unsigned int) 0x1 <<  8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_TDES_URAT       ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
+#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
+#define 	AT91C_TDES_URAT_WO_REG_READ          ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X128
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ========== 
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_IVR   ((AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR   ((AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR   ((AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR   ((AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR ((AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR   ((AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR  ((AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR  ((AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR   ((AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR   ((AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR   ((AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER  ((AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR  ((AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR  ((AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR  ((AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR  ((AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR  ((AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU   ((AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_TCR  ((AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR  ((AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR  ((AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR  ((AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR ((AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_EXID ((AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR  ((AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR  ((AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR ((AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR   ((AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR  ((AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR   ((AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR  ((AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR  ((AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER  ((AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_ODR  ((AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR ((AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR  ((AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER  ((AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR  ((AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER  ((AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR ((AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR  ((AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR  ((AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR  ((AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR  ((AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER  ((AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR  ((AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ========== 
+#define AT91C_PIOB_OWDR ((AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER ((AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR  ((AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR  ((AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR  ((AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER  ((AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR ((AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER ((AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR ((AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR ((AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR ((AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR  ((AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR ((AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR  ((AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR  ((AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR ((AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER ((AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR ((AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR  ((AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR ((AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR  ((AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR ((AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER ((AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR  ((AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR ((AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER  ((AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER  ((AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_MOR  ((AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR ((AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_IDR   ((AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER  ((AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR  ((AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR  ((AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR  ((AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR  ((AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR  ((AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR  ((AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_SCER  ((AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR   ((AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER   ((AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR    ((AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RCR  ((AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR  ((AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR  ((AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR ((AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR ((AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR ((AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR ((AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIVR ((AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR ((AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR ((AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR ((AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDCR ((AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR ((AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR ((AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ========== 
+#define AT91C_VREG_MR   ((AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ========== 
+#define AT91C_MC_ASR    ((AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR    ((AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR    ((AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR   ((AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR    ((AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR    ((AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ========== 
+#define AT91C_SPI1_PTCR ((AT91_REG *) 	0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR  ((AT91_REG *) 	0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR ((AT91_REG *) 	0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR  ((AT91_REG *) 	0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR ((AT91_REG *) 	0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR  ((AT91_REG *) 	0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR  ((AT91_REG *) 	0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR ((AT91_REG *) 	0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR ((AT91_REG *) 	0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR ((AT91_REG *) 	0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ========== 
+#define AT91C_SPI1_IMR  ((AT91_REG *) 	0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER  ((AT91_REG *) 	0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR   ((AT91_REG *) 	0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR  ((AT91_REG *) 	0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR  ((AT91_REG *) 	0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR   ((AT91_REG *) 	0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR  ((AT91_REG *) 	0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR   ((AT91_REG *) 	0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR  ((AT91_REG *) 	0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ========== 
+#define AT91C_SPI0_PTCR ((AT91_REG *) 	0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR  ((AT91_REG *) 	0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR  ((AT91_REG *) 	0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR  ((AT91_REG *) 	0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR ((AT91_REG *) 	0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR ((AT91_REG *) 	0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR  ((AT91_REG *) 	0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR ((AT91_REG *) 	0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR ((AT91_REG *) 	0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR ((AT91_REG *) 	0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ========== 
+#define AT91C_SPI0_IER  ((AT91_REG *) 	0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR   ((AT91_REG *) 	0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR  ((AT91_REG *) 	0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR   ((AT91_REG *) 	0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR   ((AT91_REG *) 	0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR  ((AT91_REG *) 	0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR  ((AT91_REG *) 	0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR  ((AT91_REG *) 	0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR  ((AT91_REG *) 	0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_RNCR  ((AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR  ((AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR  ((AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR  ((AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR  ((AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR  ((AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_IF    ((AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER   ((AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI  ((AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_TNPR  ((AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR  ((AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR  ((AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR  ((AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR  ((AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR  ((AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER   ((AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI  ((AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF    ((AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ========== 
+#define AT91C_SSC_TNCR  ((AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR   ((AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR  ((AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR   ((AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR  ((AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR   ((AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR   ((AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR  ((AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR  ((AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR  ((AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ========== 
+#define AT91C_SSC_RHR   ((AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR  ((AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR  ((AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR   ((AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR   ((AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR  ((AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER   ((AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR  ((AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR    ((AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR   ((AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR  ((AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR    ((AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR   ((AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR  ((AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ========== 
+#define AT91C_TWI_IER   ((AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR    ((AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR    ((AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR   ((AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR   ((AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR   ((AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR  ((AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR   ((AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR  ((AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR   ((AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ========== 
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ========== 
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ========== 
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ========== 
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ========== 
+#define AT91C_PWMC_IDR  ((AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS  ((AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER  ((AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR   ((AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR  ((AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR   ((AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR  ((AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR   ((AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA  ((AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ========== 
+#define AT91C_UDP_IMR   ((AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM   ((AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR   ((AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR   ((AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR   ((AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR   ((AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR   ((AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC  ((AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER   ((AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_RB    ((AT91_REG *) 	0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV    ((AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV    ((AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA    ((AT91_REG *) 	0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB    ((AT91_REG *) 	0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC    ((AT91_REG *) 	0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER   ((AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ========== 
+#define AT91C_TCB_BMR   ((AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR   ((AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ========== 
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 	0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 	0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 	0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 	0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 	0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 	0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 	0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 	0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ========== 
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 	0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 	0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 	0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 	0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 	0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 	0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 	0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 	0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ========== 
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 	0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 	0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 	0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 	0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 	0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 	0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 	0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 	0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ========== 
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 	0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 	0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 	0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 	0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 	0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 	0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 	0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 	0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ========== 
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 	0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 	0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 	0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 	0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 	0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 	0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 	0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 	0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ========== 
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 	0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 	0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 	0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 	0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 	0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 	0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 	0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 	0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ========== 
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 	0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 	0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 	0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 	0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 	0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 	0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 	0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 	0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ========== 
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 	0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 	0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 	0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 	0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 	0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 	0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 	0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 	0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ========== 
+#define AT91C_CAN_TCR   ((AT91_REG *) 	0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR   ((AT91_REG *) 	0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER   ((AT91_REG *) 	0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR   ((AT91_REG *) 	0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 	0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR    ((AT91_REG *) 	0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR   ((AT91_REG *) 	0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR   ((AT91_REG *) 	0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM   ((AT91_REG *) 	0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR    ((AT91_REG *) 	0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR    ((AT91_REG *) 	0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR    ((AT91_REG *) 	0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ========== 
+#define AT91C_EMAC_ISR  ((AT91_REG *) 	0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H ((AT91_REG *) 	0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L ((AT91_REG *) 	0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE  ((AT91_REG *) 	0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL ((AT91_REG *) 	0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE  ((AT91_REG *) 	0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL  ((AT91_REG *) 	0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF  ((AT91_REG *) 	0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND ((AT91_REG *) 	0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR  ((AT91_REG *) 	0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L ((AT91_REG *) 	0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR  ((AT91_REG *) 	0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L ((AT91_REG *) 	0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR  ((AT91_REG *) 	0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR  ((AT91_REG *) 	0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE  ((AT91_REG *) 	0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL ((AT91_REG *) 	0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID  ((AT91_REG *) 	0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB  ((AT91_REG *) 	0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP ((AT91_REG *) 	0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO ((AT91_REG *) 	0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR  ((AT91_REG *) 	0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H ((AT91_REG *) 	0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV  ((AT91_REG *) 	0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE  ((AT91_REG *) 	0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA  ((AT91_REG *) 	0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP ((AT91_REG *) 	0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF  ((AT91_REG *) 	0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 	0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT  ((AT91_REG *) 	0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF  ((AT91_REG *) 	0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE ((AT91_REG *) 	0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ  ((AT91_REG *) 	0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN  ((AT91_REG *) 	0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO  ((AT91_REG *) 	0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV  ((AT91_REG *) 	0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR  ((AT91_REG *) 	0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF  ((AT91_REG *) 	0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR  ((AT91_REG *) 	0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF  ((AT91_REG *) 	0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR  ((AT91_REG *) 	0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L ((AT91_REG *) 	0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO  ((AT91_REG *) 	0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER  ((AT91_REG *) 	0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H ((AT91_REG *) 	0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE  ((AT91_REG *) 	0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H ((AT91_REG *) 	0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE  ((AT91_REG *) 	0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE  ((AT91_REG *) 	0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ========== 
+#define AT91C_ADC_PTSR  ((AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR  ((AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR  ((AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR  ((AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR  ((AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR  ((AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR   ((AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR   ((AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR   ((AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR   ((AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ========== 
+#define AT91C_ADC_CDR2  ((AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3  ((AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0  ((AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5  ((AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR  ((AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR    ((AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4  ((AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1  ((AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR  ((AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR   ((AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR    ((AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7  ((AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6  ((AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER   ((AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER  ((AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR  ((AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR    ((AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR   ((AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ========== 
+#define AT91C_AES_TPR   ((AT91_REG *) 	0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR  ((AT91_REG *) 	0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR  ((AT91_REG *) 	0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR  ((AT91_REG *) 	0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR   ((AT91_REG *) 	0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR   ((AT91_REG *) 	0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR  ((AT91_REG *) 	0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR  ((AT91_REG *) 	0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR   ((AT91_REG *) 	0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR  ((AT91_REG *) 	0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ========== 
+#define AT91C_AES_IVxR  ((AT91_REG *) 	0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR    ((AT91_REG *) 	0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR    ((AT91_REG *) 	0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR ((AT91_REG *) 	0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR ((AT91_REG *) 	0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR    ((AT91_REG *) 	0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR   ((AT91_REG *) 	0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR   ((AT91_REG *) 	0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER   ((AT91_REG *) 	0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR ((AT91_REG *) 	0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR   ((AT91_REG *) 	0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ========== 
+#define AT91C_TDES_RNCR ((AT91_REG *) 	0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR  ((AT91_REG *) 	0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR  ((AT91_REG *) 	0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR ((AT91_REG *) 	0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR ((AT91_REG *) 	0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR  ((AT91_REG *) 	0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR ((AT91_REG *) 	0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR  ((AT91_REG *) 	0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR ((AT91_REG *) 	0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR ((AT91_REG *) 	0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ========== 
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 	0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 	0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR  ((AT91_REG *) 	0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR   ((AT91_REG *) 	0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR ((AT91_REG *) 	0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 	0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR  ((AT91_REG *) 	0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR   ((AT91_REG *) 	0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR   ((AT91_REG *) 	0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER  ((AT91_REG *) 	0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR  ((AT91_REG *) 	0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 	0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 	0xFFFA8020) // (TDES) Key 1 Word x Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0     ((unsigned int) AT91C_PIO_PA0) //  USART 0 Receive Data
+#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0     ((unsigned int) AT91C_PIO_PA1) //  USART 0 Transmit Data
+#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD      ((unsigned int) AT91C_PIO_PA10) //  TWI Two-wire Serial Data
+#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK     ((unsigned int) AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00   ((unsigned int) AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01   ((unsigned int) AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1     ((unsigned int) AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02   ((unsigned int) AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1     ((unsigned int) AT91C_PIO_PA14) //  External Interrupt 1
+#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03   ((unsigned int) AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0    ((unsigned int) AT91C_PIO_PA16) //  SPI 0 Master In Slave
+#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0    ((unsigned int) AT91C_PIO_PA17) //  SPI 0 Master Out Slave
+#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0    ((unsigned int) AT91C_PIO_PA18) //  SPI 0 Serial Clock
+#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX    ((unsigned int) AT91C_PIO_PA19) //  CAN Receive
+#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
+#define AT91C_PA2_NPCS11   ((unsigned int) AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX    ((unsigned int) AT91C_PIO_PA20) //  CAN Transmit
+#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF       ((unsigned int) AT91C_PIO_PA21) //  SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10   ((unsigned int) AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK       ((unsigned int) AT91C_PIO_PA22) //  SSC Transmit Clock
+#define AT91C_PA22_SPCK1    ((unsigned int) AT91C_PIO_PA22) //  SPI 1 Serial Clock
+#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD       ((unsigned int) AT91C_PIO_PA23) //  SSC Transmit data
+#define AT91C_PA23_MOSI1    ((unsigned int) AT91C_PIO_PA23) //  SPI 1 Master Out Slave
+#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD       ((unsigned int) AT91C_PIO_PA24) //  SSC Receive Data
+#define AT91C_PA24_MISO1    ((unsigned int) AT91C_PIO_PA24) //  SPI 1 Master In Slave
+#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK       ((unsigned int) AT91C_PIO_PA25) //  SSC Receive Clock
+#define AT91C_PA25_NPCS11   ((unsigned int) AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF       ((unsigned int) AT91C_PIO_PA26) //  SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12   ((unsigned int) AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD     ((unsigned int) AT91C_PIO_PA27) //  DBGU Debug Receive Data
+#define AT91C_PA27_PCK3     ((unsigned int) AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD     ((unsigned int) AT91C_PIO_PA28) //  DBGU Debug Transmit Data
+#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ      ((unsigned int) AT91C_PIO_PA29) //  AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13   ((unsigned int) AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0     ((unsigned int) AT91C_PIO_PA3) //  USART 0 Ready To Send
+#define AT91C_PA3_NPCS12   ((unsigned int) AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 0
+#define AT91C_PA30_PCK2     ((unsigned int) AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0     ((unsigned int) AT91C_PIO_PA4) //  USART 0 Clear To Send
+#define AT91C_PA4_NPCS13   ((unsigned int) AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1     ((unsigned int) AT91C_PIO_PA5) //  USART 1 Receive Data
+#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1     ((unsigned int) AT91C_PIO_PA6) //  USART 1 Transmit Data
+#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1     ((unsigned int) AT91C_PIO_PA7) //  USART 1 Serial Clock
+#define AT91C_PA7_NPCS01   ((unsigned int) AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1     ((unsigned int) AT91C_PIO_PA8) //  USART 1 Ready To Send
+#define AT91C_PA8_NPCS02   ((unsigned int) AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1     ((unsigned int) AT91C_PIO_PA9) //  USART 1 Clear To Send
+#define AT91C_PA9_NPCS03   ((unsigned int) AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0     ((unsigned int) AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN    ((unsigned int) AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2     ((unsigned int) AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11   ((unsigned int) AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3     ((unsigned int) AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12   ((unsigned int) AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER    ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0    ((unsigned int) AT91C_PIO_PB12) //  Timer Counter 0 external clock input
+#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01   ((unsigned int) AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3     ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02   ((unsigned int) AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV    ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13   ((unsigned int) AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03   ((unsigned int) AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100    ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG    ((unsigned int) AT91C_PIO_PB18) //  ADC External Trigger
+#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0     ((unsigned int) AT91C_PIO_PB19) //  PWM Channel 0
+#define AT91C_PB19_TCLK1    ((unsigned int) AT91C_PIO_PB19) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0     ((unsigned int) AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1     ((unsigned int) AT91C_PIO_PB20) //  PWM Channel 1
+#define AT91C_PB20_PCK0     ((unsigned int) AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2     ((unsigned int) AT91C_PIO_PB21) //  PWM Channel 2
+#define AT91C_PB21_PCK1     ((unsigned int) AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3     ((unsigned int) AT91C_PIO_PB22) //  PWM Channel 3
+#define AT91C_PB22_PCK2     ((unsigned int) AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0    ((unsigned int) AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0    ((unsigned int) AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Data Set ready
+#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1    ((unsigned int) AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Terminal ready
+#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1    ((unsigned int) AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1      ((unsigned int) AT91C_PIO_PB26) //  USART 1 Ring Indicator
+#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2    ((unsigned int) AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0     ((unsigned int) AT91C_PIO_PB27) //  PWM Channel 0
+#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2    ((unsigned int) AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1     ((unsigned int) AT91C_PIO_PB28) //  PWM Channel 1
+#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1     ((unsigned int) AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2     ((unsigned int) AT91C_PIO_PB29) //  PWM Channel 2
+#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1     ((unsigned int) AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30       ((unsigned int) 1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2     ((unsigned int) AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3     ((unsigned int) AT91C_PIO_PB30) //  PWM Channel 3
+#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0     ((unsigned int) AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1     ((unsigned int) AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER    ((unsigned int) AT91C_PIO_PB7) //  Ethernet MAC Receive Error
+#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC     ((unsigned int) AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO    ((unsigned int) AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
+#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A
+#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
+#define AT91C_ID_SPI0   ((unsigned int)  4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1   ((unsigned int)  5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
+#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
+#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
+#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
+#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
+#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
+#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
+#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
+#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
+#define AT91C_ID_CAN    ((unsigned int) 15) // Control Area Network Controller
+#define AT91C_ID_EMAC   ((unsigned int) 16) // Ethernet MAC
+#define AT91C_ID_ADC    ((unsigned int) 17) // Analog-to-Digital Converter
+#define AT91C_ID_AES    ((unsigned int) 18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES   ((unsigned int) 19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
+#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_BASE_SYS       ((AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU      ((AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB      ((AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR      ((AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC       ((AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC      ((AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC      ((AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC      ((AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC      ((AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG      ((AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC        ((AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1  ((AT91PS_PDC) 	0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1      ((AT91PS_SPI) 	0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0  ((AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0      ((AT91PS_SPI) 	0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC       ((AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI       ((AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC      ((AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP       ((AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB       ((AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0   ((AT91PS_CAN_MB) 	0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1   ((AT91PS_CAN_MB) 	0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2   ((AT91PS_CAN_MB) 	0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3   ((AT91PS_CAN_MB) 	0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4   ((AT91PS_CAN_MB) 	0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5   ((AT91PS_CAN_MB) 	0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6   ((AT91PS_CAN_MB) 	0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7   ((AT91PS_CAN_MB) 	0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN       ((AT91PS_CAN) 	0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC      ((AT91PS_EMAC) 	0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC       ((AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES   ((AT91PS_PDC) 	0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES       ((AT91PS_AES) 	0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES  ((AT91PS_PDC) 	0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES      ((AT91PS_TDES) 	0xFFFA8000) // (TDES) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_ISRAM	 ((char *) 	0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE	 ((unsigned int) 0x00008000) // Internal SRAM size in byte (32 Kbyte)
+#define AT91C_IFLASH	 ((char *) 	0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE	 ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte)
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h
new file mode 100644
index 0000000..96b680a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h
@@ -0,0 +1,2446 @@
+//  ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+//  ----------------------------------------------------------------------------
+//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  ----------------------------------------------------------------------------
+// File Name           : AT91SAM7X128.h
+// Object              : AT91SAM7X128 definitions
+// Generated           : AT91 SW Application Group  05/20/2005 (16:22:23)
+// 
+// CVS Reference       : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005//
+// CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
+// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
+// CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
+// CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
+// CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
+// CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
+// CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
+// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
+// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
+// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
+// CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
+// CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
+// CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+//  ----------------------------------------------------------------------------
+
+// Hardware register definition
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+// *** Register offset in AT91S_AIC structure ***
+#define AIC_SMR         ( 0) // Source Mode Register
+#define AIC_SVR         (128) // Source Vector Register
+#define AIC_IVR         (256) // IRQ Vector Register
+#define AIC_FVR         (260) // FIQ Vector Register
+#define AIC_ISR         (264) // Interrupt Status Register
+#define AIC_IPR         (268) // Interrupt Pending Register
+#define AIC_IMR         (272) // Interrupt Mask Register
+#define AIC_CISR        (276) // Core Interrupt Status Register
+#define AIC_IECR        (288) // Interrupt Enable Command Register
+#define AIC_IDCR        (292) // Interrupt Disable Command Register
+#define AIC_ICCR        (296) // Interrupt Clear Command Register
+#define AIC_ISCR        (300) // Interrupt Set Command Register
+#define AIC_EOICR       (304) // End of Interrupt Command Register
+#define AIC_SPU         (308) // Spurious Vector Register
+#define AIC_DCR         (312) // Debug Control Register (Protect)
+#define AIC_FFER        (320) // Fast Forcing Enable Register
+#define AIC_FFDR        (324) // Fast Forcing Disable Register
+#define AIC_FFSR        (328) // Fast Forcing Status Register
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR           (0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE         (0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       (0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        (0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    (0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    (0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
+#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           (0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        (0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ            (0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ            (0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT        (0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK        (0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// *****************************************************************************
+// *** Register offset in AT91S_PDC structure ***
+#define PDC_RPR         ( 0) // Receive Pointer Register
+#define PDC_RCR         ( 4) // Receive Counter Register
+#define PDC_TPR         ( 8) // Transmit Pointer Register
+#define PDC_TCR         (12) // Transmit Counter Register
+#define PDC_RNPR        (16) // Receive Next Pointer Register
+#define PDC_RNCR        (20) // Receive Next Counter Register
+#define PDC_TNPR        (24) // Transmit Next Pointer Register
+#define PDC_TNCR        (28) // Transmit Next Counter Register
+#define PDC_PTCR        (32) // PDC Transfer Control Register
+#define PDC_PTSR        (36) // PDC Transfer Status Register
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN           (0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS          (0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN           (0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS          (0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+// *** Register offset in AT91S_DBGU structure ***
+#define DBGU_CR         ( 0) // Control Register
+#define DBGU_MR         ( 4) // Mode Register
+#define DBGU_IER        ( 8) // Interrupt Enable Register
+#define DBGU_IDR        (12) // Interrupt Disable Register
+#define DBGU_IMR        (16) // Interrupt Mask Register
+#define DBGU_CSR        (20) // Channel Status Register
+#define DBGU_RHR        (24) // Receiver Holding Register
+#define DBGU_THR        (28) // Transmitter Holding Register
+#define DBGU_BRGR       (32) // Baud Rate Generator Register
+#define DBGU_CIDR       (64) // Chip ID Register
+#define DBGU_EXID       (68) // Chip ID Extension Register
+#define DBGU_FNTR       (72) // Force NTRST Register
+#define DBGU_RPR        (256) // Receive Pointer Register
+#define DBGU_RCR        (260) // Receive Counter Register
+#define DBGU_TPR        (264) // Transmit Pointer Register
+#define DBGU_TCR        (268) // Transmit Counter Register
+#define DBGU_RNPR       (272) // Receive Next Pointer Register
+#define DBGU_RNCR       (276) // Receive Next Counter Register
+#define DBGU_TNPR       (280) // Transmit Next Pointer Register
+#define DBGU_TNCR       (284) // Transmit Next Counter Register
+#define DBGU_PTCR       (288) // PDC Transfer Control Register
+#define DBGU_PTSR       (292) // PDC Transfer Status Register
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX            (0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX            (0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN             (0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS            (0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN             (0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS            (0x1 <<  7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA           (0x1 <<  8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR              (0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE           (0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY            (0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY            (0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX            (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX            (0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE             (0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME            (0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE             (0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY          (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE           (0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF           (0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX          (0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX          (0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST      (0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+// *** Register offset in AT91S_PIO structure ***
+#define PIO_PER         ( 0) // PIO Enable Register
+#define PIO_PDR         ( 4) // PIO Disable Register
+#define PIO_PSR         ( 8) // PIO Status Register
+#define PIO_OER         (16) // Output Enable Register
+#define PIO_ODR         (20) // Output Disable Registerr
+#define PIO_OSR         (24) // Output Status Register
+#define PIO_IFER        (32) // Input Filter Enable Register
+#define PIO_IFDR        (36) // Input Filter Disable Register
+#define PIO_IFSR        (40) // Input Filter Status Register
+#define PIO_SODR        (48) // Set Output Data Register
+#define PIO_CODR        (52) // Clear Output Data Register
+#define PIO_ODSR        (56) // Output Data Status Register
+#define PIO_PDSR        (60) // Pin Data Status Register
+#define PIO_IER         (64) // Interrupt Enable Register
+#define PIO_IDR         (68) // Interrupt Disable Register
+#define PIO_IMR         (72) // Interrupt Mask Register
+#define PIO_ISR         (76) // Interrupt Status Register
+#define PIO_MDER        (80) // Multi-driver Enable Register
+#define PIO_MDDR        (84) // Multi-driver Disable Register
+#define PIO_MDSR        (88) // Multi-driver Status Register
+#define PIO_PPUDR       (96) // Pull-up Disable Register
+#define PIO_PPUER       (100) // Pull-up Enable Register
+#define PIO_PPUSR       (104) // Pull-up Status Register
+#define PIO_ASR         (112) // Select A Register
+#define PIO_BSR         (116) // Select B Register
+#define PIO_ABSR        (120) // AB Select Status Register
+#define PIO_OWER        (160) // Output Write Enable Register
+#define PIO_OWDR        (164) // Output Write Disable Register
+#define PIO_OWSR        (168) // Output Write Status Register
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+// *** Register offset in AT91S_CKGR structure ***
+#define CKGR_MOR        ( 0) // Main Oscillator Register
+#define CKGR_MCFR       ( 4) // Main Clock  Frequency Register
+#define CKGR_PLLR       (12) // PLL Register
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN         (0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS      (0x1 <<  1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT        (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF          (0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY        (0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+#define AT91C_CKGR_DIV            (0xFF <<  0) // (CKGR) Divider Selected
+#define 	AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0
+#define 	AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT       (0x3F <<  8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT            (0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define 	AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL            (0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV         (0x3 << 28) // (CKGR) Divider for USB Clocks
+#define 	AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define 	AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define 	AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+// *** Register offset in AT91S_PMC structure ***
+#define PMC_SCER        ( 0) // System Clock Enable Register
+#define PMC_SCDR        ( 4) // System Clock Disable Register
+#define PMC_SCSR        ( 8) // System Clock Status Register
+#define PMC_PCER        (16) // Peripheral Clock Enable Register
+#define PMC_PCDR        (20) // Peripheral Clock Disable Register
+#define PMC_PCSR        (24) // Peripheral Clock Status Register
+#define PMC_MOR         (32) // Main Oscillator Register
+#define PMC_MCFR        (36) // Main Clock  Frequency Register
+#define PMC_PLLR        (44) // PLL Register
+#define PMC_MCKR        (48) // Master Clock Register
+#define PMC_PCKR        (64) // Programmable Clock Register
+#define PMC_IER         (96) // Interrupt Enable Register
+#define PMC_IDR         (100) // Interrupt Disable Register
+#define PMC_SR          (104) // Status Register
+#define PMC_IMR         (108) // Interrupt Mask Register
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_PCK             (0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP             (0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0            (0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1            (0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2            (0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3            (0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS             (0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLL_CLK              (0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES            (0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS           (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK            (0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY          (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY         (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY         (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY         (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY         (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_RSTC structure ***
+#define RSTC_RCR        ( 0) // Reset Control Register
+#define RSTC_RSR        ( 4) // Reset Status Register
+#define RSTC_RMR        ( 8) // Reset Mode Register
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_RSTC_PROCRST        (0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST         (0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST         (0x1 <<  3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY            (0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_RSTC_URSTS          (0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS         (0x1 <<  1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP         (0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_RSTC_RSTTYP_POWERUP              (0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define 	AT91C_RSTC_RSTTYP_BROWNOUT             (0x5 <<  8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL          (0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP          (0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_RSTC_URSTEN         (0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN        (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL          (0xF <<  8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN         (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_RTTC structure ***
+#define RTTC_RTMR       ( 0) // Real-time Mode Register
+#define RTTC_RTAR       ( 4) // Real-time Alarm Register
+#define RTTC_RTVR       ( 8) // Real-time Value Register
+#define RTTC_RTSR       (12) // Real-time Status Register
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_RTTC_RTPRES         (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN         (0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN      (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST         (0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_RTTC_ALMV           (0x0 <<  0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_RTTC_CRTV           (0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_RTTC_ALMS           (0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC         (0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PITC structure ***
+#define PITC_PIMR       ( 0) // Period Interval Mode Register
+#define PITC_PISR       ( 4) // Period Interval Status Register
+#define PITC_PIVR       ( 8) // Period Interval Value Register
+#define PITC_PIIR       (12) // Period Interval Image Register
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_PITC_PIV            (0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN          (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN         (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_PITC_PITS           (0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_PITC_CPIV           (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT          (0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_WDTC structure ***
+#define WDTC_WDCR       ( 0) // Watchdog Control Register
+#define WDTC_WDMR       ( 4) // Watchdog Mode Register
+#define WDTC_WDSR       ( 8) // Watchdog Status Register
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_WDTC_WDRSTT         (0x1 <<  0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY            (0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_WDTC_WDV            (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN         (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN        (0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC        (0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS          (0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD            (0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT       (0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT      (0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_WDTC_WDUNF          (0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR          (0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_VREG structure ***
+#define VREG_MR         ( 0) // Voltage Regulator Mode Register
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
+#define AT91C_VREG_PSTDBY         (0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_MC structure ***
+#define MC_RCR          ( 0) // MC Remap Control Register
+#define MC_ASR          ( 4) // MC Abort Status Register
+#define MC_AASR         ( 8) // MC Abort Address Status Register
+#define MC_FMR          (96) // MC Flash Mode Register
+#define MC_FCR          (100) // MC Flash Command Register
+#define MC_FSR          (104) // MC Flash Status Register
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+#define AT91C_MC_RCB              (0x1 <<  0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+#define AT91C_MC_UNDADD           (0x1 <<  0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD           (0x1 <<  1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ            (0x3 <<  8) // (MC) Abort Size Status
+#define 	AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
+#define 	AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
+#define 	AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
+#define AT91C_MC_ABTTYP           (0x3 << 10) // (MC) Abort Type Status
+#define 	AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
+#define 	AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
+#define 	AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0             (0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1             (0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0           (0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1           (0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+#define AT91C_MC_FRDY             (0x1 <<  0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE            (0x1 <<  2) // (MC) Lock Error
+#define AT91C_MC_PROGE            (0x1 <<  3) // (MC) Programming Error
+#define AT91C_MC_NEBP             (0x1 <<  7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS              (0x3 <<  8) // (MC) Flash Wait State
+#define 	AT91C_MC_FWS_0FWS                 (0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
+#define 	AT91C_MC_FWS_1FWS                 (0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
+#define 	AT91C_MC_FWS_2FWS                 (0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
+#define 	AT91C_MC_FWS_3FWS                 (0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN             (0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+#define AT91C_MC_FCMD             (0xF <<  0) // (MC) Flash Command
+#define 	AT91C_MC_FCMD_START_PROG           (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define 	AT91C_MC_FCMD_LOCK                 (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_PROG_AND_LOCK        (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define 	AT91C_MC_FCMD_UNLOCK               (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_ERASE_ALL            (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define 	AT91C_MC_FCMD_SET_GP_NVM           (0xB) // (MC) Set General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_CLR_GP_NVM           (0xD) // (MC) Clear General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_SET_SECURITY         (0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN            (0x3FF <<  8) // (MC) Page Number
+#define AT91C_MC_KEY              (0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+#define AT91C_MC_SECURITY         (0x1 <<  4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0           (0x1 <<  8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1           (0x1 <<  9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2           (0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3           (0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4           (0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5           (0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6           (0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7           (0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0           (0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1           (0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2           (0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3           (0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4           (0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5           (0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6           (0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7           (0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8           (0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9           (0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10          (0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11          (0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12          (0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13          (0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14          (0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15          (0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_SPI structure ***
+#define SPI_CR          ( 0) // Control Register
+#define SPI_MR          ( 4) // Mode Register
+#define SPI_RDR         ( 8) // Receive Data Register
+#define SPI_TDR         (12) // Transmit Data Register
+#define SPI_SR          (16) // Status Register
+#define SPI_IER         (20) // Interrupt Enable Register
+#define SPI_IDR         (24) // Interrupt Disable Register
+#define SPI_IMR         (28) // Interrupt Mask Register
+#define SPI_CSR         (48) // Chip Select Register
+#define SPI_RPR         (256) // Receive Pointer Register
+#define SPI_RCR         (260) // Receive Counter Register
+#define SPI_TPR         (264) // Transmit Pointer Register
+#define SPI_TCR         (268) // Transmit Counter Register
+#define SPI_RNPR        (272) // Receive Next Pointer Register
+#define SPI_RNCR        (276) // Receive Next Counter Register
+#define SPI_TNPR        (280) // Transmit Next Pointer Register
+#define SPI_TNCR        (284) // Transmit Next Counter Register
+#define SPI_PTCR        (288) // PDC Transfer Control Register
+#define SPI_PTSR        (292) // PDC Transfer Status Register
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN           (0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS          (0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST           (0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER        (0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR            (0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS              (0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC          (0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV            (0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS         (0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB             (0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS             (0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS          (0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD              (0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD              (0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF            (0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE            (0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF            (0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES           (0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX           (0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX           (0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF          (0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE          (0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR            (0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY         (0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS          (0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL            (0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA           (0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT           (0x1 <<  3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS            (0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR            (0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS           (0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT          (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+// *** Register offset in AT91S_USART structure ***
+#define US_CR           ( 0) // Control Register
+#define US_MR           ( 4) // Mode Register
+#define US_IER          ( 8) // Interrupt Enable Register
+#define US_IDR          (12) // Interrupt Disable Register
+#define US_IMR          (16) // Interrupt Mask Register
+#define US_CSR          (20) // Channel Status Register
+#define US_RHR          (24) // Receiver Holding Register
+#define US_THR          (28) // Transmitter Holding Register
+#define US_BRGR         (32) // Baud Rate Generator Register
+#define US_RTOR         (36) // Receiver Time-out Register
+#define US_TTGR         (40) // Transmitter Time-guard Register
+#define US_FIDI         (64) // FI_DI_Ratio Register
+#define US_NER          (68) // Nb Errors Register
+#define US_IF           (76) // IRDA_FILTER Register
+#define US_RPR          (256) // Receive Pointer Register
+#define US_RCR          (260) // Receive Counter Register
+#define US_TPR          (264) // Transmit Pointer Register
+#define US_TCR          (268) // Transmit Counter Register
+#define US_RNPR         (272) // Receive Next Pointer Register
+#define US_RNCR         (276) // Receive Next Counter Register
+#define US_TNPR         (280) // Transmit Next Pointer Register
+#define US_TNCR         (284) // Transmit Next Counter Register
+#define US_PTCR         (288) // PDC Transfer Control Register
+#define US_PTSR         (292) // PDC Transfer Status Register
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_STTBRK           (0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK           (0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO            (0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA            (0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT            (0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK          (0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO            (0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN            (0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS           (0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN            (0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS           (0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_USMODE           (0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS             (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL             (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC             (0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP           (0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF             (0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9            (0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO             (0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER             (0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK            (0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK           (0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER         (0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER           (0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK            (0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT          (0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION        (0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK             (0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC             (0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC            (0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC            (0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC            (0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+#define AT91C_US_RI               (0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR              (0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD              (0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS              (0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_SSC structure ***
+#define SSC_CR          ( 0) // Control Register
+#define SSC_CMR         ( 4) // Clock Mode Register
+#define SSC_RCMR        (16) // Receive Clock ModeRegister
+#define SSC_RFMR        (20) // Receive Frame Mode Register
+#define SSC_TCMR        (24) // Transmit Clock Mode Register
+#define SSC_TFMR        (28) // Transmit Frame Mode Register
+#define SSC_RHR         (32) // Receive Holding Register
+#define SSC_THR         (36) // Transmit Holding Register
+#define SSC_RSHR        (48) // Receive Sync Holding Register
+#define SSC_TSHR        (52) // Transmit Sync Holding Register
+#define SSC_SR          (64) // Status Register
+#define SSC_IER         (68) // Interrupt Enable Register
+#define SSC_IDR         (72) // Interrupt Disable Register
+#define SSC_IMR         (76) // Interrupt Mask Register
+#define SSC_RPR         (256) // Receive Pointer Register
+#define SSC_RCR         (260) // Receive Counter Register
+#define SSC_TPR         (264) // Transmit Pointer Register
+#define SSC_TCR         (268) // Transmit Counter Register
+#define SSC_RNPR        (272) // Receive Next Pointer Register
+#define SSC_RNCR        (276) // Receive Next Counter Register
+#define SSC_TNPR        (280) // Transmit Next Pointer Register
+#define SSC_TNCR        (284) // Transmit Next Counter Register
+#define SSC_PTCR        (288) // PDC Transfer Control Register
+#define SSC_PTSR        (292) // PDC Transfer Status Register
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN            (0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS           (0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN            (0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS           (0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST           (0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS             (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO             (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI             (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START           (0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY          (0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD          (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN          (0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP            (0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF            (0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB           (0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN           (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS            (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE          (0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF          (0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN           (0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY           (0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY         (0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX           (0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE          (0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY           (0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN           (0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX           (0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF          (0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN           (0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN           (0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA           (0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA           (0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TWI structure ***
+#define TWI_CR          ( 0) // Control Register
+#define TWI_MMR         ( 4) // Master Mode Register
+#define TWI_IADR        (12) // Internal Address Register
+#define TWI_CWGR        (16) // Clock Waveform Generator Register
+#define TWI_SR          (32) // Status Register
+#define TWI_IER         (36) // Interrupt Enable Register
+#define TWI_IDR         (40) // Interrupt Disable Register
+#define TWI_IMR         (44) // Interrupt Mask Register
+#define TWI_RHR         (48) // Receive Holding Register
+#define TWI_THR         (52) // Transmit Holding Register
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START           (0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP            (0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN            (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS           (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST           (0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ          (0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD           (0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR            (0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV           (0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV           (0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV           (0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP          (0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY           (0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY           (0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE            (0x1 <<  6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE            (0x1 <<  7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK            (0x1 <<  8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PWMC_CH structure ***
+#define PWMC_CMR        ( 0) // Channel Mode Register
+#define PWMC_CDTYR      ( 4) // Channel Duty Cycle Register
+#define PWMC_CPRDR      ( 8) // Channel Period Register
+#define PWMC_CCNTR      (12) // Channel Counter Register
+#define PWMC_CUPDR      (16) // Channel Update Register
+#define PWMC_Reserved   (20) // Reserved
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+#define AT91C_PWMC_CPRE           (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define 	AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH) 
+#define AT91C_PWMC_CALG           (0x1 <<  8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL           (0x1 <<  9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD            (0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+#define AT91C_PWMC_CDTY           (0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+#define AT91C_PWMC_CPRD           (0x0 <<  0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+#define AT91C_PWMC_CCNT           (0x0 <<  0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+#define AT91C_PWMC_CUPD           (0x0 <<  0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PWMC structure ***
+#define PWMC_MR         ( 0) // PWMC Mode Register
+#define PWMC_ENA        ( 4) // PWMC Enable Register
+#define PWMC_DIS        ( 8) // PWMC Disable Register
+#define PWMC_SR         (12) // PWMC Status Register
+#define PWMC_IER        (16) // PWMC Interrupt Enable Register
+#define PWMC_IDR        (20) // PWMC Interrupt Disable Register
+#define PWMC_IMR        (24) // PWMC Interrupt Mask Register
+#define PWMC_ISR        (28) // PWMC Interrupt Status Register
+#define PWMC_VR         (252) // PWMC Version Register
+#define PWMC_CH         (512) // PWMC Channel
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+#define AT91C_PWMC_DIVA           (0xFF <<  0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA           (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
+#define 	AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC) 
+#define AT91C_PWMC_DIVB           (0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB           (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define 	AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC) 
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+#define AT91C_PWMC_CHID0          (0x1 <<  0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1          (0x1 <<  1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2          (0x1 <<  2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3          (0x1 <<  3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+// *** Register offset in AT91S_UDP structure ***
+#define UDP_NUM         ( 0) // Frame Number Register
+#define UDP_GLBSTATE    ( 4) // Global State Register
+#define UDP_FADDR       ( 8) // Function Address Register
+#define UDP_IER         (16) // Interrupt Enable Register
+#define UDP_IDR         (20) // Interrupt Disable Register
+#define UDP_IMR         (24) // Interrupt Mask Register
+#define UDP_ISR         (28) // Interrupt Status Register
+#define UDP_ICR         (32) // Interrupt Clear Register
+#define UDP_RSTEP       (40) // Reset Endpoint Register
+#define UDP_CSR         (48) // Endpoint Control and Status Register
+#define UDP_FDR         (80) // Endpoint FIFO Data Register
+#define UDP_TXVC        (116) // Transceiver Control Register
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+#define AT91C_UDP_FRM_NUM         (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR         (0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK          (0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+#define AT91C_UDP_FADDEN          (0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG           (0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_ESR             (0x1 <<  2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR         (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE          (0x1 <<  4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+#define AT91C_UDP_FADD            (0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN             (0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+#define AT91C_UDP_EPINT0          (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1          (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2          (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3          (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4          (0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5          (0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP          (0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM           (0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM          (0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT          (0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP          (0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+#define AT91C_UDP_ENDBUSRES       (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+#define AT91C_UDP_EP0             (0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1             (0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2             (0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3             (0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4             (0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5             (0x1 <<  5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+#define AT91C_UDP_TXCOMP          (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0     (0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP         (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR        (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY        (0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL      (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1     (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR             (0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE          (0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE           (0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS           (0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT       (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+#define AT91C_UDP_TXVDIS          (0x1 <<  8) // (UDP) 
+#define AT91C_UDP_PUON            (0x1 <<  9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TC structure ***
+#define TC_CCR          ( 0) // Channel Control Register
+#define TC_CMR          ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
+#define TC_CV           (16) // Counter Value
+#define TC_RA           (20) // Register A
+#define TC_RB           (24) // Register B
+#define TC_RC           (28) // Register C
+#define TC_SR           (32) // Status Register
+#define TC_IER          (36) // Interrupt Enable Register
+#define TC_IDR          (40) // Interrupt Disable Register
+#define TC_IMR          (44) // Interrupt Mask Register
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN            (0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS           (0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG            (0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS             (0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI             (0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST            (0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS           (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS           (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG          (0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG          (0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT             (0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG           (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG           (0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL          (0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG           (0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE             (0x1 << 15) // (TC) 
+#define AT91C_TC_ACPA             (0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA             (0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC             (0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB             (0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT            (0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG           (0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB             (0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC             (0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT            (0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG           (0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS            (0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS            (0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS             (0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS             (0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS             (0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS            (0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS            (0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRGS            (0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA           (0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA            (0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB            (0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TCB structure ***
+#define TCB_TC0         ( 0) // TC Channel 0
+#define TCB_TC1         (64) // TC Channel 1
+#define TCB_TC2         (128) // TC Channel 2
+#define TCB_BCR         (192) // TC Block Control Register
+#define TCB_BMR         (196) // TC Block Mode Register
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC            (0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S         (0x3 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S         (0x3 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S         (0x3 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
+// *****************************************************************************
+// *** Register offset in AT91S_CAN_MB structure ***
+#define CAN_MB_MMR      ( 0) // MailBox Mode Register
+#define CAN_MB_MAM      ( 4) // MailBox Acceptance Mask Register
+#define CAN_MB_MID      ( 8) // MailBox ID Register
+#define CAN_MB_MFID     (12) // MailBox Family ID Register
+#define CAN_MB_MSR      (16) // MailBox Status Register
+#define CAN_MB_MDL      (20) // MailBox Data Low Register
+#define CAN_MB_MDH      (24) // MailBox Data High Register
+#define CAN_MB_MCR      (28) // MailBox Control Register
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
+#define AT91C_CAN_MTIMEMARK       (0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR           (0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT             (0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define 	AT91C_CAN_MOT_DIS                  (0x0 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RX                   (0x1 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RXOVERWRITE          (0x2 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_TX                   (0x3 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_CONSUMER             (0x4 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_PRODUCER             (0x5 << 24) // (CAN_MB) 
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
+#define AT91C_CAN_MIDvB           (0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA           (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE            (0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
+#define AT91C_CAN_MTIMESTAMP      (0xFFFF <<  0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC            (0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR            (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT            (0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY            (0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI             (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
+#define AT91C_CAN_MACR            (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR            (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
+// *****************************************************************************
+// *** Register offset in AT91S_CAN structure ***
+#define CAN_MR          ( 0) // Mode Register
+#define CAN_IER         ( 4) // Interrupt Enable Register
+#define CAN_IDR         ( 8) // Interrupt Disable Register
+#define CAN_IMR         (12) // Interrupt Mask Register
+#define CAN_SR          (16) // Status Register
+#define CAN_BR          (20) // Baudrate Register
+#define CAN_TIM         (24) // Timer Register
+#define CAN_TIMESTP     (28) // Time Stamp Register
+#define CAN_ECR         (32) // Error Counter Register
+#define CAN_TCR         (36) // Transfer Command Register
+#define CAN_ACR         (40) // Abort Command Register
+#define CAN_VR          (252) // Version Register
+#define CAN_MB0         (512) // CAN Mailbox 0
+#define CAN_MB1         (544) // CAN Mailbox 1
+#define CAN_MB2         (576) // CAN Mailbox 2
+#define CAN_MB3         (608) // CAN Mailbox 3
+#define CAN_MB4         (640) // CAN Mailbox 4
+#define CAN_MB5         (672) // CAN Mailbox 5
+#define CAN_MB6         (704) // CAN Mailbox 6
+#define CAN_MB7         (736) // CAN Mailbox 7
+#define CAN_MB8         (768) // CAN Mailbox 8
+#define CAN_MB9         (800) // CAN Mailbox 9
+#define CAN_MB10        (832) // CAN Mailbox 10
+#define CAN_MB11        (864) // CAN Mailbox 11
+#define CAN_MB12        (896) // CAN Mailbox 12
+#define CAN_MB13        (928) // CAN Mailbox 13
+#define CAN_MB14        (960) // CAN Mailbox 14
+#define CAN_MB15        (992) // CAN Mailbox 15
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
+#define AT91C_CAN_CANEN           (0x1 <<  0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM             (0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM             (0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL             (0x1 <<  3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF            (0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM             (0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ          (0x1 <<  6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT            (0x1 <<  7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
+#define AT91C_CAN_MB0             (0x1 <<  0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1             (0x1 <<  1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2             (0x1 <<  2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3             (0x1 <<  3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4             (0x1 <<  4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5             (0x1 <<  5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6             (0x1 <<  6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7             (0x1 <<  7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8             (0x1 <<  8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9             (0x1 <<  9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10            (0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11            (0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12            (0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13            (0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14            (0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15            (0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA            (0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN            (0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP            (0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF            (0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP           (0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP          (0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF            (0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP            (0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR            (0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR            (0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR            (0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR            (0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR            (0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
+#define AT91C_CAN_RBSY            (0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY            (0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY            (0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
+#define AT91C_CAN_PHASE2          (0x7 <<  0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1          (0x7 <<  4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG          (0x7 <<  8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC            (0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP             (0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP             (0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
+#define AT91C_CAN_TIMER           (0xFFFF <<  0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
+#define AT91C_CAN_REC             (0xFF <<  0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC             (0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
+#define AT91C_CAN_TIMRST          (0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// *****************************************************************************
+// *** Register offset in AT91S_EMAC structure ***
+#define EMAC_NCR        ( 0) // Network Control Register
+#define EMAC_NCFGR      ( 4) // Network Configuration Register
+#define EMAC_NSR        ( 8) // Network Status Register
+#define EMAC_TSR        (20) // Transmit Status Register
+#define EMAC_RBQP       (24) // Receive Buffer Queue Pointer
+#define EMAC_TBQP       (28) // Transmit Buffer Queue Pointer
+#define EMAC_RSR        (32) // Receive Status Register
+#define EMAC_ISR        (36) // Interrupt Status Register
+#define EMAC_IER        (40) // Interrupt Enable Register
+#define EMAC_IDR        (44) // Interrupt Disable Register
+#define EMAC_IMR        (48) // Interrupt Mask Register
+#define EMAC_MAN        (52) // PHY Maintenance Register
+#define EMAC_PTR        (56) // Pause Time Register
+#define EMAC_PFR        (60) // Pause Frames received Register
+#define EMAC_FTO        (64) // Frames Transmitted OK Register
+#define EMAC_SCF        (68) // Single Collision Frame Register
+#define EMAC_MCF        (72) // Multiple Collision Frame Register
+#define EMAC_FRO        (76) // Frames Received OK Register
+#define EMAC_FCSE       (80) // Frame Check Sequence Error Register
+#define EMAC_ALE        (84) // Alignment Error Register
+#define EMAC_DTF        (88) // Deferred Transmission Frame Register
+#define EMAC_LCOL       (92) // Late Collision Register
+#define EMAC_ECOL       (96) // Excessive Collision Register
+#define EMAC_TUND       (100) // Transmit Underrun Error Register
+#define EMAC_CSE        (104) // Carrier Sense Error Register
+#define EMAC_RRE        (108) // Receive Ressource Error Register
+#define EMAC_ROV        (112) // Receive Overrun Errors Register
+#define EMAC_RSE        (116) // Receive Symbol Errors Register
+#define EMAC_ELE        (120) // Excessive Length Errors Register
+#define EMAC_RJA        (124) // Receive Jabbers Register
+#define EMAC_USF        (128) // Undersize Frames Register
+#define EMAC_STE        (132) // SQE Test Error Register
+#define EMAC_RLE        (136) // Receive Length Field Mismatch Register
+#define EMAC_TPF        (140) // Transmitted Pause Frames Register
+#define EMAC_HRB        (144) // Hash Address Bottom[31:0]
+#define EMAC_HRT        (148) // Hash Address Top[63:32]
+#define EMAC_SA1L       (152) // Specific Address 1 Bottom, First 4 bytes
+#define EMAC_SA1H       (156) // Specific Address 1 Top, Last 2 bytes
+#define EMAC_SA2L       (160) // Specific Address 2 Bottom, First 4 bytes
+#define EMAC_SA2H       (164) // Specific Address 2 Top, Last 2 bytes
+#define EMAC_SA3L       (168) // Specific Address 3 Bottom, First 4 bytes
+#define EMAC_SA3H       (172) // Specific Address 3 Top, Last 2 bytes
+#define EMAC_SA4L       (176) // Specific Address 4 Bottom, First 4 bytes
+#define EMAC_SA4H       (180) // Specific Address 4 Top, Last 2 bytes
+#define EMAC_TID        (184) // Type ID Checking Register
+#define EMAC_TPQ        (188) // Transmit Pause Quantum Register
+#define EMAC_USRIO      (192) // USER Input/Output Register
+#define EMAC_WOL        (196) // Wake On LAN Register
+#define EMAC_REV        (252) // Revision Register
+// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+#define AT91C_EMAC_LB             (0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB            (0x1 <<  1) // (EMAC) Loopback local. 
+#define AT91C_EMAC_RE             (0x1 <<  2) // (EMAC) Receive enable. 
+#define AT91C_EMAC_TE             (0x1 <<  3) // (EMAC) Transmit enable. 
+#define AT91C_EMAC_MPE            (0x1 <<  4) // (EMAC) Management port enable. 
+#define AT91C_EMAC_CLRSTAT        (0x1 <<  5) // (EMAC) Clear statistics registers. 
+#define AT91C_EMAC_INCSTAT        (0x1 <<  6) // (EMAC) Increment statistics registers. 
+#define AT91C_EMAC_WESTAT         (0x1 <<  7) // (EMAC) Write enable for statistics registers. 
+#define AT91C_EMAC_BP             (0x1 <<  8) // (EMAC) Back pressure. 
+#define AT91C_EMAC_TSTART         (0x1 <<  9) // (EMAC) Start Transmission. 
+#define AT91C_EMAC_THALT          (0x1 << 10) // (EMAC) Transmission Halt. 
+#define AT91C_EMAC_TPFR           (0x1 << 11) // (EMAC) Transmit pause frame 
+#define AT91C_EMAC_TZQ            (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+#define AT91C_EMAC_SPD            (0x1 <<  0) // (EMAC) Speed. 
+#define AT91C_EMAC_FD             (0x1 <<  1) // (EMAC) Full duplex. 
+#define AT91C_EMAC_JFRAME         (0x1 <<  3) // (EMAC) Jumbo Frames. 
+#define AT91C_EMAC_CAF            (0x1 <<  4) // (EMAC) Copy all frames. 
+#define AT91C_EMAC_NBC            (0x1 <<  5) // (EMAC) No broadcast. 
+#define AT91C_EMAC_MTI            (0x1 <<  6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI            (0x1 <<  7) // (EMAC) Unicast hash enable. 
+#define AT91C_EMAC_BIG            (0x1 <<  8) // (EMAC) Receive 1522 bytes. 
+#define AT91C_EMAC_EAE            (0x1 <<  9) // (EMAC) External address match enable. 
+#define AT91C_EMAC_CLK            (0x3 << 10) // (EMAC) 
+#define 	AT91C_EMAC_CLK_HCLK_8               (0x0 << 10) // (EMAC) HCLK divided by 8
+#define 	AT91C_EMAC_CLK_HCLK_16              (0x1 << 10) // (EMAC) HCLK divided by 16
+#define 	AT91C_EMAC_CLK_HCLK_32              (0x2 << 10) // (EMAC) HCLK divided by 32
+#define 	AT91C_EMAC_CLK_HCLK_64              (0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY            (0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PAE            (0x1 << 13) // (EMAC) 
+#define AT91C_EMAC_RBOF           (0x3 << 14) // (EMAC) 
+#define 	AT91C_EMAC_RBOF_OFFSET_0             (0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_1             (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_2             (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_3             (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE           (0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS          (0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD          (0x1 << 18) // (EMAC) 
+#define AT91C_EMAC_IRXFCS         (0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+#define AT91C_EMAC_LINKR          (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_MDIO           (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_IDLE           (0x1 <<  2) // (EMAC) 
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+#define AT91C_EMAC_UBR            (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_COL            (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RLES           (0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TGO            (0x1 <<  3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX            (0x1 <<  4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP           (0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_UND            (0x1 <<  6) // (EMAC) 
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+#define AT91C_EMAC_BNA            (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_REC            (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_OVR            (0x1 <<  2) // (EMAC) 
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+#define AT91C_EMAC_MFD            (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_RCOMP          (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RXUBR          (0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TXUBR          (0x1 <<  3) // (EMAC) 
+#define AT91C_EMAC_TUNDR          (0x1 <<  4) // (EMAC) 
+#define AT91C_EMAC_RLEX           (0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_TXERR          (0x1 <<  6) // (EMAC) 
+#define AT91C_EMAC_TCOMP          (0x1 <<  7) // (EMAC) 
+#define AT91C_EMAC_LINK           (0x1 <<  9) // (EMAC) 
+#define AT91C_EMAC_ROVR           (0x1 << 10) // (EMAC) 
+#define AT91C_EMAC_HRESP          (0x1 << 11) // (EMAC) 
+#define AT91C_EMAC_PFRE           (0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PTZ            (0x1 << 13) // (EMAC) 
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+#define AT91C_EMAC_DATA           (0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_CODE           (0x3 << 16) // (EMAC) 
+#define AT91C_EMAC_REGA           (0x1F << 18) // (EMAC) 
+#define AT91C_EMAC_PHYA           (0x1F << 23) // (EMAC) 
+#define AT91C_EMAC_RW             (0x3 << 28) // (EMAC) 
+#define AT91C_EMAC_SOF            (0x3 << 30) // (EMAC) 
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+#define AT91C_EMAC_RMII           (0x1 <<  0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+#define AT91C_EMAC_IP             (0xFFFF <<  0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG            (0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP            (0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1            (0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+#define AT91C_EMAC_REVREF         (0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_PARTREF        (0xFFFF << 16) // (EMAC) 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// *****************************************************************************
+// *** Register offset in AT91S_ADC structure ***
+#define ADC_CR          ( 0) // ADC Control Register
+#define ADC_MR          ( 4) // ADC Mode Register
+#define ADC_CHER        (16) // ADC Channel Enable Register
+#define ADC_CHDR        (20) // ADC Channel Disable Register
+#define ADC_CHSR        (24) // ADC Channel Status Register
+#define ADC_SR          (28) // ADC Status Register
+#define ADC_LCDR        (32) // ADC Last Converted Data Register
+#define ADC_IER         (36) // ADC Interrupt Enable Register
+#define ADC_IDR         (40) // ADC Interrupt Disable Register
+#define ADC_IMR         (44) // ADC Interrupt Mask Register
+#define ADC_CDR0        (48) // ADC Channel Data Register 0
+#define ADC_CDR1        (52) // ADC Channel Data Register 1
+#define ADC_CDR2        (56) // ADC Channel Data Register 2
+#define ADC_CDR3        (60) // ADC Channel Data Register 3
+#define ADC_CDR4        (64) // ADC Channel Data Register 4
+#define ADC_CDR5        (68) // ADC Channel Data Register 5
+#define ADC_CDR6        (72) // ADC Channel Data Register 6
+#define ADC_CDR7        (76) // ADC Channel Data Register 7
+#define ADC_RPR         (256) // Receive Pointer Register
+#define ADC_RCR         (260) // Receive Counter Register
+#define ADC_TPR         (264) // Transmit Pointer Register
+#define ADC_TCR         (268) // Transmit Counter Register
+#define ADC_RNPR        (272) // Receive Next Pointer Register
+#define ADC_RNCR        (276) // Receive Next Counter Register
+#define ADC_TNPR        (280) // Transmit Next Pointer Register
+#define ADC_TNCR        (284) // Transmit Next Counter Register
+#define ADC_PTCR        (288) // PDC Transfer Control Register
+#define ADC_PTSR        (292) // PDC Transfer Status Register
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+#define AT91C_ADC_SWRST           (0x1 <<  0) // (ADC) Software Reset
+#define AT91C_ADC_START           (0x1 <<  1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+#define AT91C_ADC_TRGEN           (0x1 <<  0) // (ADC) Trigger Enable
+#define 	AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define 	AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL          (0x7 <<  1) // (ADC) Trigger Selection
+#define 	AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
+#define 	AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
+#define 	AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
+#define 	AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
+#define 	AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
+#define 	AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
+#define 	AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES          (0x1 <<  4) // (ADC) Resolution.
+#define 	AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
+#define 	AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP           (0x1 <<  5) // (ADC) Sleep Mode
+#define 	AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
+#define 	AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL         (0x3F <<  8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP         (0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM           (0xF << 24) // (ADC) Sample & Hold Time
+// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+#define AT91C_ADC_CH0             (0x1 <<  0) // (ADC) Channel 0
+#define AT91C_ADC_CH1             (0x1 <<  1) // (ADC) Channel 1
+#define AT91C_ADC_CH2             (0x1 <<  2) // (ADC) Channel 2
+#define AT91C_ADC_CH3             (0x1 <<  3) // (ADC) Channel 3
+#define AT91C_ADC_CH4             (0x1 <<  4) // (ADC) Channel 4
+#define AT91C_ADC_CH5             (0x1 <<  5) // (ADC) Channel 5
+#define AT91C_ADC_CH6             (0x1 <<  6) // (ADC) Channel 6
+#define AT91C_ADC_CH7             (0x1 <<  7) // (ADC) Channel 7
+// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+#define AT91C_ADC_EOC0            (0x1 <<  0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1            (0x1 <<  1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2            (0x1 <<  2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3            (0x1 <<  3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4            (0x1 <<  4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5            (0x1 <<  5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6            (0x1 <<  6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7            (0x1 <<  7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0           (0x1 <<  8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1           (0x1 <<  9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2           (0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3           (0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4           (0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5           (0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6           (0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7           (0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY            (0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE           (0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX           (0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF          (0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+#define AT91C_ADC_LDATA           (0x3FF <<  0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+#define AT91C_ADC_DATA            (0x3FF <<  0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
+// *****************************************************************************
+// *** Register offset in AT91S_AES structure ***
+#define AES_CR          ( 0) // Control Register
+#define AES_MR          ( 4) // Mode Register
+#define AES_IER         (16) // Interrupt Enable Register
+#define AES_IDR         (20) // Interrupt Disable Register
+#define AES_IMR         (24) // Interrupt Mask Register
+#define AES_ISR         (28) // Interrupt Status Register
+#define AES_KEYWxR      (32) // Key Word x Register
+#define AES_IDATAxR     (64) // Input Data x Register
+#define AES_ODATAxR     (80) // Output Data x Register
+#define AES_IVxR        (96) // Initialization Vector x Register
+#define AES_VR          (252) // AES Version Register
+#define AES_RPR         (256) // Receive Pointer Register
+#define AES_RCR         (260) // Receive Counter Register
+#define AES_TPR         (264) // Transmit Pointer Register
+#define AES_TCR         (268) // Transmit Counter Register
+#define AES_RNPR        (272) // Receive Next Pointer Register
+#define AES_RNCR        (276) // Receive Next Counter Register
+#define AES_TNPR        (280) // Transmit Next Pointer Register
+#define AES_TNCR        (284) // Transmit Next Counter Register
+#define AES_PTCR        (288) // PDC Transfer Control Register
+#define AES_PTSR        (292) // PDC Transfer Status Register
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
+#define AT91C_AES_START           (0x1 <<  0) // (AES) Starts Processing
+#define AT91C_AES_SWRST           (0x1 <<  8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED        (0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
+#define AT91C_AES_CIPHER          (0x1 <<  0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY         (0xF <<  4) // (AES) Processing Delay
+#define AT91C_AES_SMOD            (0x3 <<  8) // (AES) Start Mode
+#define 	AT91C_AES_SMOD_MANUAL               (0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define 	AT91C_AES_SMOD_AUTO                 (0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define 	AT91C_AES_SMOD_PDC                  (0x2 <<  8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD           (0x7 << 12) // (AES) Operation Mode
+#define 	AT91C_AES_OPMOD_ECB                  (0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define 	AT91C_AES_OPMOD_CBC                  (0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define 	AT91C_AES_OPMOD_OFB                  (0x2 << 12) // (AES) OFB Output Feedback mode.
+#define 	AT91C_AES_OPMOD_CFB                  (0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define 	AT91C_AES_OPMOD_CTR                  (0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD             (0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS            (0x7 << 16) // (AES) Cipher Feedback Data Size
+#define 	AT91C_AES_CFBS_128_BIT              (0x0 << 16) // (AES) 128-bit.
+#define 	AT91C_AES_CFBS_64_BIT               (0x1 << 16) // (AES) 64-bit.
+#define 	AT91C_AES_CFBS_32_BIT               (0x2 << 16) // (AES) 32-bit.
+#define 	AT91C_AES_CFBS_16_BIT               (0x3 << 16) // (AES) 16-bit.
+#define 	AT91C_AES_CFBS_8_BIT                (0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY            (0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE           (0x1F << 24) // (AES) Countermeasure Type
+#define 	AT91C_AES_CTYPE_TYPE1_EN             (0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE2_EN             (0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE3_EN             (0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE4_EN             (0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE5_EN             (0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_AES_DATRDY          (0x1 <<  0) // (AES) DATRDY
+#define AT91C_AES_ENDRX           (0x1 <<  1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX           (0x1 <<  2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF          (0x1 <<  3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE          (0x1 <<  4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD            (0x1 <<  8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_AES_URAT            (0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  (0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define 	AT91C_AES_URAT_WO_REG_READ          (0x5 << 12) // (AES) Write-only register read access.
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
+// *****************************************************************************
+// *** Register offset in AT91S_TDES structure ***
+#define TDES_CR         ( 0) // Control Register
+#define TDES_MR         ( 4) // Mode Register
+#define TDES_IER        (16) // Interrupt Enable Register
+#define TDES_IDR        (20) // Interrupt Disable Register
+#define TDES_IMR        (24) // Interrupt Mask Register
+#define TDES_ISR        (28) // Interrupt Status Register
+#define TDES_KEY1WxR    (32) // Key 1 Word x Register
+#define TDES_KEY2WxR    (40) // Key 2 Word x Register
+#define TDES_KEY3WxR    (48) // Key 3 Word x Register
+#define TDES_IDATAxR    (64) // Input Data x Register
+#define TDES_ODATAxR    (80) // Output Data x Register
+#define TDES_IVxR       (96) // Initialization Vector x Register
+#define TDES_VR         (252) // TDES Version Register
+#define TDES_RPR        (256) // Receive Pointer Register
+#define TDES_RCR        (260) // Receive Counter Register
+#define TDES_TPR        (264) // Transmit Pointer Register
+#define TDES_TCR        (268) // Transmit Counter Register
+#define TDES_RNPR       (272) // Receive Next Pointer Register
+#define TDES_RNCR       (276) // Receive Next Counter Register
+#define TDES_TNPR       (280) // Transmit Next Pointer Register
+#define TDES_TNCR       (284) // Transmit Next Counter Register
+#define TDES_PTCR       (288) // PDC Transfer Control Register
+#define TDES_PTSR       (292) // PDC Transfer Status Register
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
+#define AT91C_TDES_START          (0x1 <<  0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST          (0x1 <<  8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
+#define AT91C_TDES_CIPHER         (0x1 <<  0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD        (0x1 <<  1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD         (0x1 <<  4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD           (0x3 <<  8) // (TDES) Start Mode
+#define 	AT91C_TDES_SMOD_MANUAL               (0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define 	AT91C_TDES_SMOD_AUTO                 (0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define 	AT91C_TDES_SMOD_PDC                  (0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD          (0x3 << 12) // (TDES) Operation Mode
+#define 	AT91C_TDES_OPMOD_ECB                  (0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define 	AT91C_TDES_OPMOD_CBC                  (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define 	AT91C_TDES_OPMOD_OFB                  (0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define 	AT91C_TDES_OPMOD_CFB                  (0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD            (0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS           (0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define 	AT91C_TDES_CFBS_64_BIT               (0x0 << 16) // (TDES) 64-bit.
+#define 	AT91C_TDES_CFBS_32_BIT               (0x1 << 16) // (TDES) 32-bit.
+#define 	AT91C_TDES_CFBS_16_BIT               (0x2 << 16) // (TDES) 16-bit.
+#define 	AT91C_TDES_CFBS_8_BIT                (0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_TDES_DATRDY         (0x1 <<  0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX          (0x1 <<  1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX          (0x1 <<  2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF         (0x1 <<  3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE         (0x1 <<  4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD           (0x1 <<  8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_TDES_URAT           (0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing.
+#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing.
+#define 	AT91C_TDES_URAT_WO_REG_READ          (0x3 << 12) // (TDES) Write-only register read access.
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X128
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ========== 
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_IVR             (0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR             (0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR             (0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR             (0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR           (0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR             (0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR            (0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR            (0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR             (0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR             (0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR             (0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER            (0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR            (0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR            (0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR            (0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR            (0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR            (0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU             (0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_TCR            (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR           (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR           (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR            (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR            (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR            (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR           (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR           (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR           (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR           (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_EXID           (0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR           (0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR            (0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR            (0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR           (0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR             (0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR            (0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR             (0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR           (0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR            (0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR            (0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER            (0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_ODR            (0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR           (0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR            (0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR           (0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER            (0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR          (0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR            (0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER            (0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR           (0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR           (0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR           (0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR            (0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR           (0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR          (0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR           (0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR            (0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER           (0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER           (0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR           (0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER          (0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR            (0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR            (0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR           (0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR           (0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER           (0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR            (0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR           (0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER            (0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR            (0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ========== 
+#define AT91C_PIOB_OWDR           (0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER           (0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR          (0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR            (0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR            (0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR          (0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR            (0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER            (0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR           (0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER           (0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR           (0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR           (0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR           (0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR            (0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR           (0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR            (0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR            (0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR           (0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER          (0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR           (0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR            (0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR           (0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR            (0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR           (0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER           (0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR            (0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR           (0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER            (0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER            (0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_MOR            (0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR           (0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR           (0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_IDR             (0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR             (0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR            (0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER            (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR            (0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR            (0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR            (0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR            (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR            (0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR            (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR            (0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_SCER            (0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR             (0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER             (0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR              (0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RCR            (0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR            (0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR            (0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR           (0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR           (0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR           (0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR           (0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIVR           (0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR           (0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR           (0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR           (0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDCR           (0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR           (0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR           (0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ========== 
+#define AT91C_VREG_MR             (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ========== 
+#define AT91C_MC_ASR              (0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR              (0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR              (0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR             (0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR              (0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR              (0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ========== 
+#define AT91C_SPI1_PTCR           (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR            (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR           (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR            (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR           (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR            (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR            (0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR           (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR           (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR           (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ========== 
+#define AT91C_SPI1_IMR            (0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER            (0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR             (0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR            (0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR            (0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR             (0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR            (0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR             (0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR            (0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ========== 
+#define AT91C_SPI0_PTCR           (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR            (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR            (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR            (0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR           (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR           (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR            (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR           (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR           (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR           (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ========== 
+#define AT91C_SPI0_IER            (0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR             (0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR            (0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR             (0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR             (0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR            (0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR            (0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR            (0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR            (0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_RNCR            (0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR            (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR             (0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR            (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR            (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR             (0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR            (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR             (0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR            (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR             (0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_IF              (0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER             (0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR            (0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR             (0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR             (0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER             (0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR             (0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR            (0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR             (0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR            (0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR             (0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI            (0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR              (0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR              (0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_TNPR            (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR            (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR             (0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR            (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR            (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR            (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR             (0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR             (0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR             (0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR            (0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_BRGR            (0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER             (0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR              (0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR             (0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI            (0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR            (0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR              (0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR            (0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR             (0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR             (0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR             (0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR             (0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF              (0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER             (0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ========== 
+#define AT91C_SSC_TNCR            (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR             (0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR            (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR             (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR            (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR             (0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR             (0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR            (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR            (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR            (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ========== 
+#define AT91C_SSC_RHR             (0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR            (0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR            (0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR             (0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR             (0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR            (0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER             (0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR            (0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR              (0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR             (0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR            (0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR              (0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR             (0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR            (0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ========== 
+#define AT91C_TWI_IER             (0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR              (0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR              (0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR             (0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR             (0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR             (0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR            (0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR             (0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR            (0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR             (0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ========== 
+#define AT91C_PWMC_CH3_CUPDR      (0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved   (0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR      (0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR      (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR      (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR        (0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ========== 
+#define AT91C_PWMC_CH2_Reserved   (0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR        (0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR      (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR      (0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR      (0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR      (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ========== 
+#define AT91C_PWMC_CH1_Reserved   (0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR      (0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR      (0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR      (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR      (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR        (0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ========== 
+#define AT91C_PWMC_CH0_Reserved   (0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR      (0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR      (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR        (0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR      (0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR      (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ========== 
+#define AT91C_PWMC_IDR            (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS            (0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER            (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR             (0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR            (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR             (0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR            (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR             (0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA            (0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ========== 
+#define AT91C_UDP_IMR             (0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR           (0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM             (0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR             (0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR             (0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR             (0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR             (0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR             (0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP           (0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC            (0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE        (0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER             (0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_SR              (0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC              (0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB              (0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR             (0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR             (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER             (0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA              (0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR             (0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV              (0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR             (0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_RB              (0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR             (0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER             (0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR             (0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR              (0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR             (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA              (0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC              (0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR             (0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV              (0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_CMR             (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR             (0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV              (0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA              (0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB              (0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR             (0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR             (0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC              (0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER             (0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR              (0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ========== 
+#define AT91C_TCB_BMR             (0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR             (0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ========== 
+#define AT91C_CAN_MB0_MDL         (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM         (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR         (0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID         (0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR         (0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID        (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH         (0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR         (0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ========== 
+#define AT91C_CAN_MB1_MDL         (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID         (0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR         (0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR         (0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM         (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH         (0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR         (0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID        (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ========== 
+#define AT91C_CAN_MB2_MCR         (0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH         (0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID         (0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL         (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR         (0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM         (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID        (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR         (0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ========== 
+#define AT91C_CAN_MB3_MFID        (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM         (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID         (0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR         (0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR         (0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR         (0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL         (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH         (0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ========== 
+#define AT91C_CAN_MB4_MID         (0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR         (0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH         (0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID        (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR         (0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR         (0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL         (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM         (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ========== 
+#define AT91C_CAN_MB5_MSR         (0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR         (0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID        (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH         (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID         (0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR         (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL         (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM         (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ========== 
+#define AT91C_CAN_MB6_MFID        (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID         (0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM         (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR         (0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL         (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR         (0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH         (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR         (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ========== 
+#define AT91C_CAN_MB7_MCR         (0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH         (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID        (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL         (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID         (0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR         (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM         (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR         (0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ========== 
+#define AT91C_CAN_TCR             (0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR             (0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER             (0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR             (0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP         (0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR              (0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR             (0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR             (0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM             (0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR              (0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR              (0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR              (0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ========== 
+#define AT91C_EMAC_ISR            (0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H           (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L           (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE            (0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL           (0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE            (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL            (0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF            (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND           (0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR            (0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L           (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR            (0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L           (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR            (0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR            (0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE            (0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL           (0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID            (0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB            (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP           (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO          (0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR            (0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H           (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV            (0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE            (0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA            (0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP           (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF            (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR          (0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT            (0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF            (0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE           (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ            (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN            (0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO            (0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV            (0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR            (0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF            (0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR            (0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF            (0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR            (0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L           (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO            (0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER            (0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H           (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE            (0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H           (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE            (0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE            (0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ========== 
+#define AT91C_ADC_PTSR            (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR            (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR            (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR            (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR            (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR            (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR             (0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR             (0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR             (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR             (0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ========== 
+#define AT91C_ADC_CDR2            (0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3            (0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0            (0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5            (0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR            (0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR              (0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4            (0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1            (0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR            (0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR             (0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR              (0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7            (0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6            (0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER             (0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER            (0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR            (0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR              (0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR             (0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ========== 
+#define AT91C_AES_TPR             (0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR            (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR            (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR            (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR             (0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR             (0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR            (0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR            (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR             (0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR            (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ========== 
+#define AT91C_AES_IVxR            (0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR              (0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR              (0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR         (0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR         (0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR              (0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR             (0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR             (0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER             (0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR          (0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR             (0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ========== 
+#define AT91C_TDES_RNCR           (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR            (0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR            (0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR           (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR           (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR            (0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR           (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR            (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR           (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR           (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ========== 
+#define AT91C_TDES_KEY2WxR        (0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR        (0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR            (0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR             (0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR           (0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR        (0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR            (0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR             (0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR             (0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER            (0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR            (0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR        (0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR        (0xFFFA8020) // (TDES) Key 1 Word x Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_PIO_PA0             (1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0            (AT91C_PIO_PA0) //  USART 0 Receive Data
+#define AT91C_PIO_PA1             (1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0            (AT91C_PIO_PA1) //  USART 0 Transmit Data
+#define AT91C_PIO_PA10            (1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD            (AT91C_PIO_PA10) //  TWI Two-wire Serial Data
+#define AT91C_PIO_PA11            (1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK           (AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12            (1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00         (AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13            (1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01         (AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1           (AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14            (1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02         (AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1           (AT91C_PIO_PA14) //  External Interrupt 1
+#define AT91C_PIO_PA15            (1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03         (AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2          (AT91C_PIO_PA15) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PA16            (1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0          (AT91C_PIO_PA16) //  SPI 0 Master In Slave
+#define AT91C_PIO_PA17            (1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0          (AT91C_PIO_PA17) //  SPI 0 Master Out Slave
+#define AT91C_PIO_PA18            (1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0          (AT91C_PIO_PA18) //  SPI 0 Serial Clock
+#define AT91C_PIO_PA19            (1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX          (AT91C_PIO_PA19) //  CAN Receive
+#define AT91C_PIO_PA2             (1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0            (AT91C_PIO_PA2) //  USART 0 Serial Clock
+#define AT91C_PA2_NPCS11          (AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20            (1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX          (AT91C_PIO_PA20) //  CAN Transmit
+#define AT91C_PIO_PA21            (1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF             (AT91C_PIO_PA21) //  SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10         (AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22            (1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK             (AT91C_PIO_PA22) //  SSC Transmit Clock
+#define AT91C_PA22_SPCK1          (AT91C_PIO_PA22) //  SPI 1 Serial Clock
+#define AT91C_PIO_PA23            (1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD             (AT91C_PIO_PA23) //  SSC Transmit data
+#define AT91C_PA23_MOSI1          (AT91C_PIO_PA23) //  SPI 1 Master Out Slave
+#define AT91C_PIO_PA24            (1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD             (AT91C_PIO_PA24) //  SSC Receive Data
+#define AT91C_PA24_MISO1          (AT91C_PIO_PA24) //  SPI 1 Master In Slave
+#define AT91C_PIO_PA25            (1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK             (AT91C_PIO_PA25) //  SSC Receive Clock
+#define AT91C_PA25_NPCS11         (AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26            (1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF             (AT91C_PIO_PA26) //  SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12         (AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27            (1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD           (AT91C_PIO_PA27) //  DBGU Debug Receive Data
+#define AT91C_PA27_PCK3           (AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28            (1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD           (AT91C_PIO_PA28) //  DBGU Debug Transmit Data
+#define AT91C_PIO_PA29            (1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ            (AT91C_PIO_PA29) //  AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13         (AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3             (1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0            (AT91C_PIO_PA3) //  USART 0 Ready To Send
+#define AT91C_PA3_NPCS12          (AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30            (1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0           (AT91C_PIO_PA30) //  External Interrupt 0
+#define AT91C_PA30_PCK2           (AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4             (1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0            (AT91C_PIO_PA4) //  USART 0 Clear To Send
+#define AT91C_PA4_NPCS13          (AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5             (1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1            (AT91C_PIO_PA5) //  USART 1 Receive Data
+#define AT91C_PIO_PA6             (1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1            (AT91C_PIO_PA6) //  USART 1 Transmit Data
+#define AT91C_PIO_PA7             (1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1            (AT91C_PIO_PA7) //  USART 1 Serial Clock
+#define AT91C_PA7_NPCS01          (AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8             (1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1            (AT91C_PIO_PA8) //  USART 1 Ready To Send
+#define AT91C_PA8_NPCS02          (AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9             (1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1            (AT91C_PIO_PA9) //  USART 1 Clear To Send
+#define AT91C_PA9_NPCS03          (AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0             (1 <<  0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK    (AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0            (AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1             (1 <<  1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN           (AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10            (1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2           (AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11         (AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11            (1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3           (AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12         (AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12            (1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER          (AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0          (AT91C_PIO_PB12) //  Timer Counter 0 external clock input
+#define AT91C_PIO_PB13            (1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2           (AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01         (AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14            (1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3           (AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02         (AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15            (1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV          (AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16            (1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL           (AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13         (AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17            (1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK          (AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03         (AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18            (1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100          (AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG          (AT91C_PIO_PB18) //  ADC External Trigger
+#define AT91C_PIO_PB19            (1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0           (AT91C_PIO_PB19) //  PWM Channel 0
+#define AT91C_PB19_TCLK1          (AT91C_PIO_PB19) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PB2             (1 <<  2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0            (AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20            (1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1           (AT91C_PIO_PB20) //  PWM Channel 1
+#define AT91C_PB20_PCK0           (AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21            (1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2           (AT91C_PIO_PB21) //  PWM Channel 2
+#define AT91C_PB21_PCK1           (AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22            (1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3           (AT91C_PIO_PB22) //  PWM Channel 3
+#define AT91C_PB22_PCK2           (AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23            (1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0          (AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1           (AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24            (1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0          (AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1           (AT91C_PIO_PB24) //  USART 1 Data Set ready
+#define AT91C_PIO_PB25            (1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1          (AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1           (AT91C_PIO_PB25) //  USART 1 Data Terminal ready
+#define AT91C_PIO_PB26            (1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1          (AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1            (AT91C_PIO_PB26) //  USART 1 Ring Indicator
+#define AT91C_PIO_PB27            (1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2          (AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0           (AT91C_PIO_PB27) //  PWM Channel 0
+#define AT91C_PIO_PB28            (1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2          (AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1           (AT91C_PIO_PB28) //  PWM Channel 1
+#define AT91C_PIO_PB29            (1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1           (AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2           (AT91C_PIO_PB29) //  PWM Channel 2
+#define AT91C_PIO_PB3             (1 <<  3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1            (AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30            (1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2           (AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3           (AT91C_PIO_PB30) //  PWM Channel 3
+#define AT91C_PIO_PB4             (1 <<  4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV     (AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5             (1 <<  5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0            (AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6             (1 <<  6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1            (AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7             (1 <<  7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER           (AT91C_PIO_PB7) //  Ethernet MAC Receive Error
+#define AT91C_PIO_PB8             (1 <<  8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC            (AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9             (1 <<  9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO           (AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_ID_FIQ              ( 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS              ( 1) // System Peripheral
+#define AT91C_ID_PIOA             ( 2) // Parallel IO Controller A
+#define AT91C_ID_PIOB             ( 3) // Parallel IO Controller B
+#define AT91C_ID_SPI0             ( 4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1             ( 5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0              ( 6) // USART 0
+#define AT91C_ID_US1              ( 7) // USART 1
+#define AT91C_ID_SSC              ( 8) // Serial Synchronous Controller
+#define AT91C_ID_TWI              ( 9) // Two-Wire Interface
+#define AT91C_ID_PWMC             (10) // PWM Controller
+#define AT91C_ID_UDP              (11) // USB Device Port
+#define AT91C_ID_TC0              (12) // Timer Counter 0
+#define AT91C_ID_TC1              (13) // Timer Counter 1
+#define AT91C_ID_TC2              (14) // Timer Counter 2
+#define AT91C_ID_CAN              (15) // Control Area Network Controller
+#define AT91C_ID_EMAC             (16) // Ethernet MAC
+#define AT91C_ID_ADC              (17) // Analog-to-Digital Converter
+#define AT91C_ID_AES              (18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES             (19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved      (20) // Reserved
+#define AT91C_ID_21_Reserved      (21) // Reserved
+#define AT91C_ID_22_Reserved      (22) // Reserved
+#define AT91C_ID_23_Reserved      (23) // Reserved
+#define AT91C_ID_24_Reserved      (24) // Reserved
+#define AT91C_ID_25_Reserved      (25) // Reserved
+#define AT91C_ID_26_Reserved      (26) // Reserved
+#define AT91C_ID_27_Reserved      (27) // Reserved
+#define AT91C_ID_28_Reserved      (28) // Reserved
+#define AT91C_ID_29_Reserved      (29) // Reserved
+#define AT91C_ID_IRQ0             (30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1             (31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_BASE_SYS            (0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC            (0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU       (0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU           (0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA           (0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB           (0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR           (0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC            (0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC           (0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC           (0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC           (0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC           (0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG           (0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC             (0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1       (0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1           (0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0       (0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0           (0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1        (0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1            (0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0        (0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0            (0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC        (0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC            (0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI            (0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3       (0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2       (0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1       (0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0       (0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC           (0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP            (0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0            (0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1            (0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2            (0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB            (0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0        (0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1        (0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2        (0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3        (0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4        (0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5        (0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6        (0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7        (0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN            (0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC           (0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC        (0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC            (0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES        (0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES            (0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES       (0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES           (0xFFFA8000) // (TDES) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_ISRAM	              (0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE	         (0x00008000) // Internal SRAM size in byte (32 Kbyte)
+#define AT91C_IFLASH	             (0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE	        (0x00020000) // Internal ROM size in byte (128 Kbyte)
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h
new file mode 100644
index 0000000..6b73f8a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h
@@ -0,0 +1,2715 @@
+//  ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+//  ----------------------------------------------------------------------------
+//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  ----------------------------------------------------------------------------
+// File Name           : AT91SAM7X256.h
+// Object              : AT91SAM7X256 definitions
+// Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
+// 
+// CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
+// CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
+// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
+// CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
+// CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
+// CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
+// CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
+// CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
+// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
+// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
+// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
+// CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
+// CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
+// CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+//  ----------------------------------------------------------------------------
+
+#ifndef AT91SAM7X256_H
+#define AT91SAM7X256_H
+
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYS {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+	AT91_REG	 Reserved2[45]; 	// 
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved3[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved4[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+	AT91_REG	 Reserved5[54]; 	// 
+	AT91_REG	 PIOA_PER; 	// PIO Enable Register
+	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOA_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved6[1]; 	// 
+	AT91_REG	 PIOA_OER; 	// Output Enable Register
+	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOA_OSR; 	// Output Status Register
+	AT91_REG	 Reserved7[1]; 	// 
+	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved8[1]; 	// 
+	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved9[1]; 	// 
+	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved10[1]; 	// 
+	AT91_REG	 PIOA_ASR; 	// Select A Register
+	AT91_REG	 PIOA_BSR; 	// Select B Register
+	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved11[9]; 	// 
+	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved12[85]; 	// 
+	AT91_REG	 PIOB_PER; 	// PIO Enable Register
+	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOB_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved13[1]; 	// 
+	AT91_REG	 PIOB_OER; 	// Output Enable Register
+	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOB_OSR; 	// Output Status Register
+	AT91_REG	 Reserved14[1]; 	// 
+	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved15[1]; 	// 
+	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved16[1]; 	// 
+	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved17[1]; 	// 
+	AT91_REG	 PIOB_ASR; 	// Select A Register
+	AT91_REG	 PIOB_BSR; 	// Select B Register
+	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved18[9]; 	// 
+	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved19[341]; 	// 
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved20[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved21[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved22[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved23[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved24[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved25[36]; 	// 
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+	AT91_REG	 Reserved26[5]; 	// 
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+	AT91_REG	 Reserved27[5]; 	// 
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_SYS, *AT91PS_SYS;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
+#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
+	AT91_REG	 PDC_RCR; 	// Receive Counter Register
+	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
+	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved0[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved1[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+	AT91_REG	 PIO_PER; 	// PIO Enable Register
+	AT91_REG	 PIO_PDR; 	// PIO Disable Register
+	AT91_REG	 PIO_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PIO_OER; 	// Output Enable Register
+	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIO_OSR; 	// Output Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PIO_SODR; 	// Set Output Data Register
+	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved3[1]; 	// 
+	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved4[1]; 	// 
+	AT91_REG	 PIO_ASR; 	// Select A Register
+	AT91_REG	 PIO_BSR; 	// Select B Register
+	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved5[9]; 	// 
+	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
+	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 CKGR_PLLR; 	// PLL Register
+} AT91S_CKGR, *AT91PS_CKGR;
+
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
+#define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
+#define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
+#define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved3[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved4[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RSTC {
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
+
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define 	AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RTTC {
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PITC {
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_WDTC {
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_VREG {
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_VREG, *AT91PS_VREG;
+
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
+#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+	AT91_REG	 MC_RCR; 	// MC Remap Control Register
+	AT91_REG	 MC_ASR; 	// MC Abort Status Register
+	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
+	AT91_REG	 Reserved0[21]; 	// 
+	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
+	AT91_REG	 MC_FCR; 	// MC Flash Command Register
+	AT91_REG	 MC_FSR; 	// MC Flash Status Register
+} AT91S_MC, *AT91PS_MC;
+
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
+#define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
+#define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
+#define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
+#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
+#define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
+#define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
+#define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
+#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
+#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
+#define 	AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
+#define 	AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
+#define 	AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
+#define 	AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
+#define 	AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define 	AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define 	AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define 	AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
+#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+	AT91_REG	 SPI_CR; 	// Control Register
+	AT91_REG	 SPI_MR; 	// Mode Register
+	AT91_REG	 SPI_RDR; 	// Receive Data Register
+	AT91_REG	 SPI_TDR; 	// Transmit Data Register
+	AT91_REG	 SPI_SR; 	// Status Register
+	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
+	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
+	AT91_REG	 Reserved1[48]; 	// 
+	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
+	AT91_REG	 SPI_RCR; 	// Receive Counter Register
+	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
+	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+	AT91_REG	 US_CR; 	// Control Register
+	AT91_REG	 US_MR; 	// Mode Register
+	AT91_REG	 US_IER; 	// Interrupt Enable Register
+	AT91_REG	 US_IDR; 	// Interrupt Disable Register
+	AT91_REG	 US_IMR; 	// Interrupt Mask Register
+	AT91_REG	 US_CSR; 	// Channel Status Register
+	AT91_REG	 US_RHR; 	// Receiver Holding Register
+	AT91_REG	 US_THR; 	// Transmitter Holding Register
+	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
+	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
+	AT91_REG	 Reserved0[5]; 	// 
+	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
+	AT91_REG	 US_NER; 	// Nb Errors Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 US_IF; 	// IRDA_FILTER Register
+	AT91_REG	 Reserved2[44]; 	// 
+	AT91_REG	 US_RPR; 	// Receive Pointer Register
+	AT91_REG	 US_RCR; 	// Receive Counter Register
+	AT91_REG	 US_TPR; 	// Transmit Pointer Register
+	AT91_REG	 US_TCR; 	// Transmit Counter Register
+	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+	AT91_REG	 SSC_CR; 	// Control Register
+	AT91_REG	 SSC_CMR; 	// Clock Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
+	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
+	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
+	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
+	AT91_REG	 SSC_RHR; 	// Receive Holding Register
+	AT91_REG	 SSC_THR; 	// Transmit Holding Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
+	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 SSC_SR; 	// Status Register
+	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
+	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved3[44]; 	// 
+	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
+	AT91_REG	 SSC_RCR; 	// Receive Counter Register
+	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
+	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+	AT91_REG	 TWI_CR; 	// Control Register
+	AT91_REG	 TWI_MMR; 	// Master Mode Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 TWI_IADR; 	// Internal Address Register
+	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
+	AT91_REG	 Reserved1[3]; 	// 
+	AT91_REG	 TWI_SR; 	// Status Register
+	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
+	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TWI_RHR; 	// Receive Holding Register
+	AT91_REG	 TWI_THR; 	// Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
+
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC_CH {
+	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
+	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
+	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
+	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
+	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
+	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
+
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define 	AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH) 
+#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC {
+	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
+	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
+	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
+	AT91_REG	 PWMC_SR; 	// PWMC Status Register
+	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
+	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
+	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
+	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
+	AT91_REG	 Reserved0[55]; 	// 
+	AT91_REG	 PWMC_VR; 	// PWMC Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
+} AT91S_PWMC, *AT91PS_PWMC;
+
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
+#define 	AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC) 
+#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define 	AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC) 
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+	AT91_REG	 UDP_NUM; 	// Frame Number Register
+	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
+	AT91_REG	 UDP_FADDR; 	// Function Address Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
+	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
+	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
+	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
+	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
+	AT91_REG	 Reserved4[3]; 	// 
+	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
+
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_ESR         ((unsigned int) 0x1 <<  2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+#define AT91C_UDP_TXVDIS      ((unsigned int) 0x1 <<  8) // (UDP) 
+#define AT91C_UDP_PUON        ((unsigned int) 0x1 <<  9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+	AT91_REG	 TC_CCR; 	// Channel Control Register
+	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TC_CV; 	// Counter Value
+	AT91_REG	 TC_RA; 	// Register A
+	AT91_REG	 TC_RB; 	// Register B
+	AT91_REG	 TC_RC; 	// Register C
+	AT91_REG	 TC_SR; 	// Status Register
+	AT91_REG	 TC_IER; 	// Interrupt Enable Register
+	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_TIOB                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_XC0                  ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC1                  ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC2                  ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) 
+#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRGS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA       ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+	AT91S_TC	 TCB_TC0; 	// TC Channel 0
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91S_TC	 TCB_TC1; 	// TC Channel 1
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91S_TC	 TCB_TC2; 	// TC Channel 2
+	AT91_REG	 Reserved2[4]; 	// 
+	AT91_REG	 TCB_BCR; 	// TC Block Control Register
+	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x3 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x3 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x3 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA1                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN_MB {
+	AT91_REG	 CAN_MB_MMR; 	// MailBox Mode Register
+	AT91_REG	 CAN_MB_MAM; 	// MailBox Acceptance Mask Register
+	AT91_REG	 CAN_MB_MID; 	// MailBox ID Register
+	AT91_REG	 CAN_MB_MFID; 	// MailBox Family ID Register
+	AT91_REG	 CAN_MB_MSR; 	// MailBox Status Register
+	AT91_REG	 CAN_MB_MDL; 	// MailBox Data Low Register
+	AT91_REG	 CAN_MB_MDH; 	// MailBox Data High Register
+	AT91_REG	 CAN_MB_MCR; 	// MailBox Control Register
+} AT91S_CAN_MB, *AT91PS_CAN_MB;
+
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
+#define AT91C_CAN_MTIMEMARK   ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR       ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT         ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define 	AT91C_CAN_MOT_DIS                  ((unsigned int) 0x0 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RX                   ((unsigned int) 0x1 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RXOVERWRITE          ((unsigned int) 0x2 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_TX                   ((unsigned int) 0x3 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_CONSUMER             ((unsigned int) 0x4 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_PRODUCER             ((unsigned int) 0x5 << 24) // (CAN_MB) 
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
+#define AT91C_CAN_MIDvB       ((unsigned int) 0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA       ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE        ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
+#define AT91C_CAN_MTIMESTAMP  ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC        ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR        ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT        ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI         ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
+#define AT91C_CAN_MACR        ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN {
+	AT91_REG	 CAN_MR; 	// Mode Register
+	AT91_REG	 CAN_IER; 	// Interrupt Enable Register
+	AT91_REG	 CAN_IDR; 	// Interrupt Disable Register
+	AT91_REG	 CAN_IMR; 	// Interrupt Mask Register
+	AT91_REG	 CAN_SR; 	// Status Register
+	AT91_REG	 CAN_BR; 	// Baudrate Register
+	AT91_REG	 CAN_TIM; 	// Timer Register
+	AT91_REG	 CAN_TIMESTP; 	// Time Stamp Register
+	AT91_REG	 CAN_ECR; 	// Error Counter Register
+	AT91_REG	 CAN_TCR; 	// Transfer Command Register
+	AT91_REG	 CAN_ACR; 	// Abort Command Register
+	AT91_REG	 Reserved0[52]; 	// 
+	AT91_REG	 CAN_VR; 	// Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_CAN_MB	 CAN_MB0; 	// CAN Mailbox 0
+	AT91S_CAN_MB	 CAN_MB1; 	// CAN Mailbox 1
+	AT91S_CAN_MB	 CAN_MB2; 	// CAN Mailbox 2
+	AT91S_CAN_MB	 CAN_MB3; 	// CAN Mailbox 3
+	AT91S_CAN_MB	 CAN_MB4; 	// CAN Mailbox 4
+	AT91S_CAN_MB	 CAN_MB5; 	// CAN Mailbox 5
+	AT91S_CAN_MB	 CAN_MB6; 	// CAN Mailbox 6
+	AT91S_CAN_MB	 CAN_MB7; 	// CAN Mailbox 7
+	AT91S_CAN_MB	 CAN_MB8; 	// CAN Mailbox 8
+	AT91S_CAN_MB	 CAN_MB9; 	// CAN Mailbox 9
+	AT91S_CAN_MB	 CAN_MB10; 	// CAN Mailbox 10
+	AT91S_CAN_MB	 CAN_MB11; 	// CAN Mailbox 11
+	AT91S_CAN_MB	 CAN_MB12; 	// CAN Mailbox 12
+	AT91S_CAN_MB	 CAN_MB13; 	// CAN Mailbox 13
+	AT91S_CAN_MB	 CAN_MB14; 	// CAN Mailbox 14
+	AT91S_CAN_MB	 CAN_MB15; 	// CAN Mailbox 15
+} AT91S_CAN, *AT91PS_CAN;
+
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
+#define AT91C_CAN_CANEN       ((unsigned int) 0x1 <<  0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM         ((unsigned int) 0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM         ((unsigned int) 0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL         ((unsigned int) 0x1 <<  3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF        ((unsigned int) 0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM         ((unsigned int) 0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ      ((unsigned int) 0x1 <<  6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT        ((unsigned int) 0x1 <<  7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
+#define AT91C_CAN_MB0         ((unsigned int) 0x1 <<  0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1         ((unsigned int) 0x1 <<  1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2         ((unsigned int) 0x1 <<  2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3         ((unsigned int) 0x1 <<  3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4         ((unsigned int) 0x1 <<  4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5         ((unsigned int) 0x1 <<  5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6         ((unsigned int) 0x1 <<  6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7         ((unsigned int) 0x1 <<  7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8         ((unsigned int) 0x1 <<  8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9         ((unsigned int) 0x1 <<  9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10        ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11        ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12        ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13        ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14        ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15        ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA        ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN        ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP        ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF        ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP       ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP      ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF        ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP        ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR        ((unsigned int) 0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR        ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR        ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR        ((unsigned int) 0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR        ((unsigned int) 0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
+#define AT91C_CAN_RBSY        ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY        ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY        ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
+#define AT91C_CAN_PHASE2      ((unsigned int) 0x7 <<  0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1      ((unsigned int) 0x7 <<  4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG      ((unsigned int) 0x7 <<  8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC        ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP         ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP         ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
+#define AT91C_CAN_TIMER       ((unsigned int) 0xFFFF <<  0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
+#define AT91C_CAN_REC         ((unsigned int) 0xFF <<  0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC         ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
+#define AT91C_CAN_TIMRST      ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// *****************************************************************************
+typedef struct _AT91S_EMAC {
+	AT91_REG	 EMAC_NCR; 	// Network Control Register
+	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
+	AT91_REG	 EMAC_NSR; 	// Network Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
+	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
+	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
+	AT91_REG	 EMAC_RSR; 	// Receive Status Register
+	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
+	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
+	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
+	AT91_REG	 EMAC_PTR; 	// Pause Time Register
+	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
+	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
+	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
+	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
+	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
+	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
+	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
+	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
+	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
+	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
+	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
+	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
+	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
+	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
+	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
+	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
+	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
+	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
+	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
+	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
+	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
+	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
+	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
+	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
+	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
+	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
+	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
+	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
+	AT91_REG	 Reserved1[13]; 	// 
+	AT91_REG	 EMAC_REV; 	// Revision Register
+} AT91S_EMAC, *AT91PS_EMAC;
+
+// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local. 
+#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable. 
+#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable. 
+#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable. 
+#define AT91C_EMAC_CLRSTAT    ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers. 
+#define AT91C_EMAC_INCSTAT    ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers. 
+#define AT91C_EMAC_WESTAT     ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers. 
+#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure. 
+#define AT91C_EMAC_TSTART     ((unsigned int) 0x1 <<  9) // (EMAC) Start Transmission. 
+#define AT91C_EMAC_THALT      ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. 
+#define AT91C_EMAC_TPFR       ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame 
+#define AT91C_EMAC_TZQ        ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed. 
+#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex. 
+#define AT91C_EMAC_JFRAME     ((unsigned int) 0x1 <<  3) // (EMAC) Jumbo Frames. 
+#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames. 
+#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast. 
+#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable. 
+#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes. 
+#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable. 
+#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC) 
+#define 	AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
+#define 	AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
+#define 	AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
+#define 	AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PAE        ((unsigned int) 0x1 << 13) // (EMAC) 
+#define AT91C_EMAC_RBOF       ((unsigned int) 0x3 << 14) // (EMAC) 
+#define 	AT91C_EMAC_RBOF_OFFSET_0             ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_1             ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_2             ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_3             ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE       ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS      ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD      ((unsigned int) 0x1 << 18) // (EMAC) 
+#define AT91C_EMAC_IRXFCS     ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+#define AT91C_EMAC_LINKR      ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+#define AT91C_EMAC_UBR        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RLES       ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TGO        ((unsigned int) 0x1 <<  3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX        ((unsigned int) 0x1 <<  4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC) 
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+#define AT91C_EMAC_MFD        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_RCOMP      ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RXUBR      ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TXUBR      ((unsigned int) 0x1 <<  3) // (EMAC) 
+#define AT91C_EMAC_TUNDR      ((unsigned int) 0x1 <<  4) // (EMAC) 
+#define AT91C_EMAC_RLEX       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_TXERR      ((unsigned int) 0x1 <<  6) // (EMAC) 
+#define AT91C_EMAC_TCOMP      ((unsigned int) 0x1 <<  7) // (EMAC) 
+#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC) 
+#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC) 
+#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC) 
+#define AT91C_EMAC_PFRE       ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PTZ        ((unsigned int) 0x1 << 13) // (EMAC) 
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC) 
+#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC) 
+#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC) 
+#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC) 
+#define AT91C_EMAC_SOF        ((unsigned int) 0x3 << 30) // (EMAC) 
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+#define AT91C_EMAC_RMII       ((unsigned int) 0x1 <<  0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+#define AT91C_EMAC_IP         ((unsigned int) 0xFFFF <<  0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG        ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP        ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1        ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+#define AT91C_EMAC_REVREF     ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_PARTREF    ((unsigned int) 0xFFFF << 16) // (EMAC) 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// *****************************************************************************
+typedef struct _AT91S_ADC {
+	AT91_REG	 ADC_CR; 	// ADC Control Register
+	AT91_REG	 ADC_MR; 	// ADC Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
+	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
+	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
+	AT91_REG	 ADC_SR; 	// ADC Status Register
+	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
+	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
+	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
+	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
+	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
+	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
+	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
+	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
+	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
+	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
+	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
+	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
+	AT91_REG	 Reserved1[44]; 	// 
+	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
+	AT91_REG	 ADC_RCR; 	// Receive Counter Register
+	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
+	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
+
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
+#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
+#define 	AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define 	AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
+#define 	AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
+#define 	AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
+#define 	AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
+#define 	AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
+#define 	AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
+#define 	AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
+#define 	AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
+#define 	AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
+#define 	AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define 	AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
+#define 	AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
+// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
+#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
+#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
+#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
+#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
+#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
+#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
+#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
+// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_AES {
+	AT91_REG	 AES_CR; 	// Control Register
+	AT91_REG	 AES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AES_IER; 	// Interrupt Enable Register
+	AT91_REG	 AES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 AES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AES_ISR; 	// Interrupt Status Register
+	AT91_REG	 AES_KEYWxR[4]; 	// Key Word x Register
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91_REG	 AES_IDATAxR[4]; 	// Input Data x Register
+	AT91_REG	 AES_ODATAxR[4]; 	// Output Data x Register
+	AT91_REG	 AES_IVxR[4]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved2[35]; 	// 
+	AT91_REG	 AES_VR; 	// AES Version Register
+	AT91_REG	 AES_RPR; 	// Receive Pointer Register
+	AT91_REG	 AES_RCR; 	// Receive Counter Register
+	AT91_REG	 AES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 AES_TCR; 	// Transmit Counter Register
+	AT91_REG	 AES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 AES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 AES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 AES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 AES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 AES_PTSR; 	// PDC Transfer Status Register
+} AT91S_AES, *AT91PS_AES;
+
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
+#define AT91C_AES_START       ((unsigned int) 0x1 <<  0) // (AES) Starts Processing
+#define AT91C_AES_SWRST       ((unsigned int) 0x1 <<  8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED    ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
+#define AT91C_AES_CIPHER      ((unsigned int) 0x1 <<  0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY     ((unsigned int) 0xF <<  4) // (AES) Processing Delay
+#define AT91C_AES_SMOD        ((unsigned int) 0x3 <<  8) // (AES) Start Mode
+#define 	AT91C_AES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define 	AT91C_AES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define 	AT91C_AES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD       ((unsigned int) 0x7 << 12) // (AES) Operation Mode
+#define 	AT91C_AES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define 	AT91C_AES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define 	AT91C_AES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
+#define 	AT91C_AES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define 	AT91C_AES_OPMOD_CTR                  ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD         ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS        ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
+#define 	AT91C_AES_CFBS_128_BIT              ((unsigned int) 0x0 << 16) // (AES) 128-bit.
+#define 	AT91C_AES_CFBS_64_BIT               ((unsigned int) 0x1 << 16) // (AES) 64-bit.
+#define 	AT91C_AES_CFBS_32_BIT               ((unsigned int) 0x2 << 16) // (AES) 32-bit.
+#define 	AT91C_AES_CFBS_16_BIT               ((unsigned int) 0x3 << 16) // (AES) 16-bit.
+#define 	AT91C_AES_CFBS_8_BIT                ((unsigned int) 0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY        ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE       ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
+#define 	AT91C_AES_CTYPE_TYPE1_EN             ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE2_EN             ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE3_EN             ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE4_EN             ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE5_EN             ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_AES_DATRDY      ((unsigned int) 0x1 <<  0) // (AES) DATRDY
+#define AT91C_AES_ENDRX       ((unsigned int) 0x1 <<  1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX       ((unsigned int) 0x1 <<  2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF      ((unsigned int) 0x1 <<  3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE      ((unsigned int) 0x1 <<  4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD        ((unsigned int) 0x1 <<  8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_AES_URAT        ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define 	AT91C_AES_URAT_WO_REG_READ          ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_TDES {
+	AT91_REG	 TDES_CR; 	// Control Register
+	AT91_REG	 TDES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TDES_IER; 	// Interrupt Enable Register
+	AT91_REG	 TDES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TDES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TDES_ISR; 	// Interrupt Status Register
+	AT91_REG	 TDES_KEY1WxR[2]; 	// Key 1 Word x Register
+	AT91_REG	 TDES_KEY2WxR[2]; 	// Key 2 Word x Register
+	AT91_REG	 TDES_KEY3WxR[2]; 	// Key 3 Word x Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 TDES_IDATAxR[2]; 	// Input Data x Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 TDES_ODATAxR[2]; 	// Output Data x Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 TDES_IVxR[2]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved4[37]; 	// 
+	AT91_REG	 TDES_VR; 	// TDES Version Register
+	AT91_REG	 TDES_RPR; 	// Receive Pointer Register
+	AT91_REG	 TDES_RCR; 	// Receive Counter Register
+	AT91_REG	 TDES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 TDES_TCR; 	// Transmit Counter Register
+	AT91_REG	 TDES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 TDES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 TDES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 TDES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 TDES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 TDES_PTSR; 	// PDC Transfer Status Register
+} AT91S_TDES, *AT91PS_TDES;
+
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
+#define AT91C_TDES_START      ((unsigned int) 0x1 <<  0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST      ((unsigned int) 0x1 <<  8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
+#define AT91C_TDES_CIPHER     ((unsigned int) 0x1 <<  0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD    ((unsigned int) 0x1 <<  1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD     ((unsigned int) 0x1 <<  4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD       ((unsigned int) 0x3 <<  8) // (TDES) Start Mode
+#define 	AT91C_TDES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define 	AT91C_TDES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define 	AT91C_TDES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD      ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
+#define 	AT91C_TDES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define 	AT91C_TDES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define 	AT91C_TDES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define 	AT91C_TDES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD        ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS       ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define 	AT91C_TDES_CFBS_64_BIT               ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
+#define 	AT91C_TDES_CFBS_32_BIT               ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
+#define 	AT91C_TDES_CFBS_16_BIT               ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
+#define 	AT91C_TDES_CFBS_8_BIT                ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_TDES_DATRDY     ((unsigned int) 0x1 <<  0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX      ((unsigned int) 0x1 <<  1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX      ((unsigned int) 0x1 <<  2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF     ((unsigned int) 0x1 <<  3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE     ((unsigned int) 0x1 <<  4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD       ((unsigned int) 0x1 <<  8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_TDES_URAT       ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
+#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
+#define 	AT91C_TDES_URAT_WO_REG_READ          ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ========== 
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_IVR   ((AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR   ((AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR   ((AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR   ((AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR ((AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR   ((AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR  ((AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR  ((AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR   ((AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR   ((AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR   ((AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER  ((AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR  ((AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR  ((AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR  ((AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR  ((AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR  ((AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU   ((AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_TCR  ((AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR  ((AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR  ((AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR  ((AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR ((AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_EXID ((AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR  ((AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR  ((AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR ((AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR   ((AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR  ((AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR   ((AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR  ((AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR  ((AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER  ((AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_ODR  ((AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR ((AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR  ((AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER  ((AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR  ((AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER  ((AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR ((AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR  ((AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR  ((AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR  ((AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR  ((AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER  ((AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR  ((AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ========== 
+#define AT91C_PIOB_OWDR ((AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER ((AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR  ((AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR  ((AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR  ((AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER  ((AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR ((AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER ((AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR ((AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR ((AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR ((AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR  ((AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR ((AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR  ((AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR  ((AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR ((AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER ((AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR ((AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR  ((AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR ((AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR  ((AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR ((AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER ((AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR  ((AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR ((AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER  ((AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER  ((AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_MOR  ((AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR ((AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_IDR   ((AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER  ((AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR  ((AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR  ((AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR  ((AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR  ((AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR  ((AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR  ((AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_SCER  ((AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR   ((AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER   ((AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR    ((AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RCR  ((AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR  ((AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR  ((AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR ((AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR ((AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR ((AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR ((AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIVR ((AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR ((AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR ((AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR ((AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDCR ((AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR ((AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR ((AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ========== 
+#define AT91C_VREG_MR   ((AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ========== 
+#define AT91C_MC_ASR    ((AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR    ((AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR    ((AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR   ((AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR    ((AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR    ((AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ========== 
+#define AT91C_SPI1_PTCR ((AT91_REG *) 	0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR  ((AT91_REG *) 	0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR ((AT91_REG *) 	0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR  ((AT91_REG *) 	0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR ((AT91_REG *) 	0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR  ((AT91_REG *) 	0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR  ((AT91_REG *) 	0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR ((AT91_REG *) 	0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR ((AT91_REG *) 	0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR ((AT91_REG *) 	0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ========== 
+#define AT91C_SPI1_IMR  ((AT91_REG *) 	0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER  ((AT91_REG *) 	0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR   ((AT91_REG *) 	0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR  ((AT91_REG *) 	0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR  ((AT91_REG *) 	0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR   ((AT91_REG *) 	0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR  ((AT91_REG *) 	0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR   ((AT91_REG *) 	0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR  ((AT91_REG *) 	0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ========== 
+#define AT91C_SPI0_PTCR ((AT91_REG *) 	0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR  ((AT91_REG *) 	0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR  ((AT91_REG *) 	0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR  ((AT91_REG *) 	0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR ((AT91_REG *) 	0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR ((AT91_REG *) 	0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR  ((AT91_REG *) 	0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR ((AT91_REG *) 	0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR ((AT91_REG *) 	0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR ((AT91_REG *) 	0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ========== 
+#define AT91C_SPI0_IER  ((AT91_REG *) 	0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR   ((AT91_REG *) 	0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR  ((AT91_REG *) 	0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR   ((AT91_REG *) 	0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR   ((AT91_REG *) 	0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR  ((AT91_REG *) 	0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR  ((AT91_REG *) 	0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR  ((AT91_REG *) 	0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR  ((AT91_REG *) 	0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_RNCR  ((AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR  ((AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR  ((AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR  ((AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR  ((AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR  ((AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_IF    ((AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER   ((AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI  ((AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_TNPR  ((AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR  ((AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR  ((AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR  ((AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR  ((AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR  ((AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER   ((AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI  ((AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF    ((AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ========== 
+#define AT91C_SSC_TNCR  ((AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR   ((AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR  ((AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR   ((AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR  ((AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR   ((AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR   ((AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR  ((AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR  ((AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR  ((AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ========== 
+#define AT91C_SSC_RHR   ((AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR  ((AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR  ((AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR   ((AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR   ((AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR  ((AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER   ((AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR  ((AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR    ((AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR   ((AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR  ((AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR    ((AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR   ((AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR  ((AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ========== 
+#define AT91C_TWI_IER   ((AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR    ((AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR    ((AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR   ((AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR   ((AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR   ((AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR  ((AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR   ((AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR  ((AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR   ((AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ========== 
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ========== 
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ========== 
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ========== 
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ========== 
+#define AT91C_PWMC_IDR  ((AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS  ((AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER  ((AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR   ((AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR  ((AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR   ((AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR  ((AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR   ((AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA  ((AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ========== 
+#define AT91C_UDP_IMR   ((AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM   ((AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR   ((AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR   ((AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR   ((AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR   ((AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR   ((AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC  ((AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER   ((AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_RB    ((AT91_REG *) 	0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV    ((AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV    ((AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA    ((AT91_REG *) 	0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB    ((AT91_REG *) 	0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC    ((AT91_REG *) 	0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER   ((AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ========== 
+#define AT91C_TCB_BMR   ((AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR   ((AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ========== 
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 	0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 	0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 	0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 	0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 	0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 	0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 	0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 	0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ========== 
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 	0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 	0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 	0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 	0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 	0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 	0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 	0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 	0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ========== 
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 	0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 	0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 	0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 	0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 	0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 	0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 	0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 	0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ========== 
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 	0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 	0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 	0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 	0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 	0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 	0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 	0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 	0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ========== 
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 	0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 	0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 	0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 	0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 	0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 	0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 	0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 	0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ========== 
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 	0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 	0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 	0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 	0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 	0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 	0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 	0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 	0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ========== 
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 	0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 	0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 	0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 	0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 	0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 	0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 	0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 	0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ========== 
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 	0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 	0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 	0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 	0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 	0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 	0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 	0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 	0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ========== 
+#define AT91C_CAN_TCR   ((AT91_REG *) 	0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR   ((AT91_REG *) 	0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER   ((AT91_REG *) 	0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR   ((AT91_REG *) 	0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 	0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR    ((AT91_REG *) 	0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR   ((AT91_REG *) 	0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR   ((AT91_REG *) 	0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM   ((AT91_REG *) 	0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR    ((AT91_REG *) 	0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR    ((AT91_REG *) 	0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR    ((AT91_REG *) 	0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ========== 
+#define AT91C_EMAC_ISR  ((AT91_REG *) 	0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H ((AT91_REG *) 	0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L ((AT91_REG *) 	0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE  ((AT91_REG *) 	0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL ((AT91_REG *) 	0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE  ((AT91_REG *) 	0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL  ((AT91_REG *) 	0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF  ((AT91_REG *) 	0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND ((AT91_REG *) 	0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR  ((AT91_REG *) 	0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L ((AT91_REG *) 	0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR  ((AT91_REG *) 	0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L ((AT91_REG *) 	0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR  ((AT91_REG *) 	0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR  ((AT91_REG *) 	0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE  ((AT91_REG *) 	0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL ((AT91_REG *) 	0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID  ((AT91_REG *) 	0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB  ((AT91_REG *) 	0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP ((AT91_REG *) 	0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO ((AT91_REG *) 	0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR  ((AT91_REG *) 	0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H ((AT91_REG *) 	0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV  ((AT91_REG *) 	0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE  ((AT91_REG *) 	0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA  ((AT91_REG *) 	0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP ((AT91_REG *) 	0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF  ((AT91_REG *) 	0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 	0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT  ((AT91_REG *) 	0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF  ((AT91_REG *) 	0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE ((AT91_REG *) 	0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ  ((AT91_REG *) 	0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN  ((AT91_REG *) 	0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO  ((AT91_REG *) 	0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV  ((AT91_REG *) 	0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR  ((AT91_REG *) 	0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF  ((AT91_REG *) 	0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR  ((AT91_REG *) 	0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF  ((AT91_REG *) 	0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR  ((AT91_REG *) 	0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L ((AT91_REG *) 	0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO  ((AT91_REG *) 	0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER  ((AT91_REG *) 	0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H ((AT91_REG *) 	0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE  ((AT91_REG *) 	0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H ((AT91_REG *) 	0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE  ((AT91_REG *) 	0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE  ((AT91_REG *) 	0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ========== 
+#define AT91C_ADC_PTSR  ((AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR  ((AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR  ((AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR  ((AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR  ((AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR  ((AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR   ((AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR   ((AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR   ((AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR   ((AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ========== 
+#define AT91C_ADC_CDR2  ((AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3  ((AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0  ((AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5  ((AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR  ((AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR    ((AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4  ((AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1  ((AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR  ((AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR   ((AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR    ((AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7  ((AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6  ((AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER   ((AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER  ((AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR  ((AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR    ((AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR   ((AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ========== 
+#define AT91C_AES_TPR   ((AT91_REG *) 	0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR  ((AT91_REG *) 	0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR  ((AT91_REG *) 	0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR  ((AT91_REG *) 	0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR   ((AT91_REG *) 	0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR   ((AT91_REG *) 	0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR  ((AT91_REG *) 	0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR  ((AT91_REG *) 	0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR   ((AT91_REG *) 	0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR  ((AT91_REG *) 	0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ========== 
+#define AT91C_AES_IVxR  ((AT91_REG *) 	0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR    ((AT91_REG *) 	0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR    ((AT91_REG *) 	0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR ((AT91_REG *) 	0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR ((AT91_REG *) 	0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR    ((AT91_REG *) 	0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR   ((AT91_REG *) 	0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR   ((AT91_REG *) 	0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER   ((AT91_REG *) 	0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR ((AT91_REG *) 	0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR   ((AT91_REG *) 	0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ========== 
+#define AT91C_TDES_RNCR ((AT91_REG *) 	0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR  ((AT91_REG *) 	0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR  ((AT91_REG *) 	0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR ((AT91_REG *) 	0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR ((AT91_REG *) 	0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR  ((AT91_REG *) 	0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR ((AT91_REG *) 	0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR  ((AT91_REG *) 	0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR ((AT91_REG *) 	0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR ((AT91_REG *) 	0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ========== 
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 	0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 	0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR  ((AT91_REG *) 	0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR   ((AT91_REG *) 	0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR ((AT91_REG *) 	0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 	0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR  ((AT91_REG *) 	0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR   ((AT91_REG *) 	0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR   ((AT91_REG *) 	0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER  ((AT91_REG *) 	0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR  ((AT91_REG *) 	0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 	0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 	0xFFFA8020) // (TDES) Key 1 Word x Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0     ((unsigned int) AT91C_PIO_PA0) //  USART 0 Receive Data
+#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0     ((unsigned int) AT91C_PIO_PA1) //  USART 0 Transmit Data
+#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD      ((unsigned int) AT91C_PIO_PA10) //  TWI Two-wire Serial Data
+#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK     ((unsigned int) AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00   ((unsigned int) AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01   ((unsigned int) AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1     ((unsigned int) AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02   ((unsigned int) AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1     ((unsigned int) AT91C_PIO_PA14) //  External Interrupt 1
+#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03   ((unsigned int) AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0    ((unsigned int) AT91C_PIO_PA16) //  SPI 0 Master In Slave
+#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0    ((unsigned int) AT91C_PIO_PA17) //  SPI 0 Master Out Slave
+#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0    ((unsigned int) AT91C_PIO_PA18) //  SPI 0 Serial Clock
+#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX    ((unsigned int) AT91C_PIO_PA19) //  CAN Receive
+#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
+#define AT91C_PA2_NPCS11   ((unsigned int) AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX    ((unsigned int) AT91C_PIO_PA20) //  CAN Transmit
+#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF       ((unsigned int) AT91C_PIO_PA21) //  SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10   ((unsigned int) AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK       ((unsigned int) AT91C_PIO_PA22) //  SSC Transmit Clock
+#define AT91C_PA22_SPCK1    ((unsigned int) AT91C_PIO_PA22) //  SPI 1 Serial Clock
+#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD       ((unsigned int) AT91C_PIO_PA23) //  SSC Transmit data
+#define AT91C_PA23_MOSI1    ((unsigned int) AT91C_PIO_PA23) //  SPI 1 Master Out Slave
+#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD       ((unsigned int) AT91C_PIO_PA24) //  SSC Receive Data
+#define AT91C_PA24_MISO1    ((unsigned int) AT91C_PIO_PA24) //  SPI 1 Master In Slave
+#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK       ((unsigned int) AT91C_PIO_PA25) //  SSC Receive Clock
+#define AT91C_PA25_NPCS11   ((unsigned int) AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF       ((unsigned int) AT91C_PIO_PA26) //  SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12   ((unsigned int) AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD     ((unsigned int) AT91C_PIO_PA27) //  DBGU Debug Receive Data
+#define AT91C_PA27_PCK3     ((unsigned int) AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD     ((unsigned int) AT91C_PIO_PA28) //  DBGU Debug Transmit Data
+#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ      ((unsigned int) AT91C_PIO_PA29) //  AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13   ((unsigned int) AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0     ((unsigned int) AT91C_PIO_PA3) //  USART 0 Ready To Send
+#define AT91C_PA3_NPCS12   ((unsigned int) AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 0
+#define AT91C_PA30_PCK2     ((unsigned int) AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0     ((unsigned int) AT91C_PIO_PA4) //  USART 0 Clear To Send
+#define AT91C_PA4_NPCS13   ((unsigned int) AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1     ((unsigned int) AT91C_PIO_PA5) //  USART 1 Receive Data
+#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1     ((unsigned int) AT91C_PIO_PA6) //  USART 1 Transmit Data
+#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1     ((unsigned int) AT91C_PIO_PA7) //  USART 1 Serial Clock
+#define AT91C_PA7_NPCS01   ((unsigned int) AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1     ((unsigned int) AT91C_PIO_PA8) //  USART 1 Ready To Send
+#define AT91C_PA8_NPCS02   ((unsigned int) AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1     ((unsigned int) AT91C_PIO_PA9) //  USART 1 Clear To Send
+#define AT91C_PA9_NPCS03   ((unsigned int) AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0     ((unsigned int) AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN    ((unsigned int) AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2     ((unsigned int) AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11   ((unsigned int) AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3     ((unsigned int) AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12   ((unsigned int) AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER    ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0    ((unsigned int) AT91C_PIO_PB12) //  Timer Counter 0 external clock input
+#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01   ((unsigned int) AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3     ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02   ((unsigned int) AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV    ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13   ((unsigned int) AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03   ((unsigned int) AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100    ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG    ((unsigned int) AT91C_PIO_PB18) //  ADC External Trigger
+#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0     ((unsigned int) AT91C_PIO_PB19) //  PWM Channel 0
+#define AT91C_PB19_TCLK1    ((unsigned int) AT91C_PIO_PB19) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0     ((unsigned int) AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1     ((unsigned int) AT91C_PIO_PB20) //  PWM Channel 1
+#define AT91C_PB20_PCK0     ((unsigned int) AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2     ((unsigned int) AT91C_PIO_PB21) //  PWM Channel 2
+#define AT91C_PB21_PCK1     ((unsigned int) AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3     ((unsigned int) AT91C_PIO_PB22) //  PWM Channel 3
+#define AT91C_PB22_PCK2     ((unsigned int) AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0    ((unsigned int) AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0    ((unsigned int) AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Data Set ready
+#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1    ((unsigned int) AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Terminal ready
+#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1    ((unsigned int) AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1      ((unsigned int) AT91C_PIO_PB26) //  USART 1 Ring Indicator
+#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2    ((unsigned int) AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0     ((unsigned int) AT91C_PIO_PB27) //  PWM Channel 0
+#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2    ((unsigned int) AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1     ((unsigned int) AT91C_PIO_PB28) //  PWM Channel 1
+#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1     ((unsigned int) AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2     ((unsigned int) AT91C_PIO_PB29) //  PWM Channel 2
+#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1     ((unsigned int) AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30       ((unsigned int) 1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2     ((unsigned int) AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3     ((unsigned int) AT91C_PIO_PB30) //  PWM Channel 3
+#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0     ((unsigned int) AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1     ((unsigned int) AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER    ((unsigned int) AT91C_PIO_PB7) //  Ethernet MAC Receive Error
+#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC     ((unsigned int) AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO    ((unsigned int) AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
+#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A
+#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
+#define AT91C_ID_SPI0   ((unsigned int)  4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1   ((unsigned int)  5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
+#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
+#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
+#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
+#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
+#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
+#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
+#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
+#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
+#define AT91C_ID_CAN    ((unsigned int) 15) // Control Area Network Controller
+#define AT91C_ID_EMAC   ((unsigned int) 16) // Ethernet MAC
+#define AT91C_ID_ADC    ((unsigned int) 17) // Analog-to-Digital Converter
+#define AT91C_ID_AES    ((unsigned int) 18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES   ((unsigned int) 19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
+#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_BASE_SYS       ((AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU      ((AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB      ((AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR      ((AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC       ((AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC      ((AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC      ((AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC      ((AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC      ((AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG      ((AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC        ((AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1  ((AT91PS_PDC) 	0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1      ((AT91PS_SPI) 	0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0  ((AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0      ((AT91PS_SPI) 	0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC       ((AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI       ((AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC      ((AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP       ((AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB       ((AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0   ((AT91PS_CAN_MB) 	0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1   ((AT91PS_CAN_MB) 	0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2   ((AT91PS_CAN_MB) 	0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3   ((AT91PS_CAN_MB) 	0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4   ((AT91PS_CAN_MB) 	0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5   ((AT91PS_CAN_MB) 	0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6   ((AT91PS_CAN_MB) 	0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7   ((AT91PS_CAN_MB) 	0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN       ((AT91PS_CAN) 	0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC      ((AT91PS_EMAC) 	0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC       ((AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES   ((AT91PS_PDC) 	0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES       ((AT91PS_AES) 	0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES  ((AT91PS_PDC) 	0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES      ((AT91PS_TDES) 	0xFFFA8000) // (TDES) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ISRAM	 ((char *) 	0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE	 ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)
+#define AT91C_IFLASH	 ((char *) 	0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE	 ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h
new file mode 100644
index 0000000..5b8dfe8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h
@@ -0,0 +1,2446 @@
+//  ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+//  ----------------------------------------------------------------------------
+//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  ----------------------------------------------------------------------------
+// File Name           : AT91SAM7X256.h
+// Object              : AT91SAM7X256 definitions
+// Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
+// 
+// CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
+// CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
+// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
+// CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
+// CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
+// CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
+// CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
+// CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
+// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
+// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
+// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
+// CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
+// CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
+// CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+//  ----------------------------------------------------------------------------
+
+// Hardware register definition
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+// *** Register offset in AT91S_AIC structure ***
+#define AIC_SMR         ( 0) // Source Mode Register
+#define AIC_SVR         (128) // Source Vector Register
+#define AIC_IVR         (256) // IRQ Vector Register
+#define AIC_FVR         (260) // FIQ Vector Register
+#define AIC_ISR         (264) // Interrupt Status Register
+#define AIC_IPR         (268) // Interrupt Pending Register
+#define AIC_IMR         (272) // Interrupt Mask Register
+#define AIC_CISR        (276) // Core Interrupt Status Register
+#define AIC_IECR        (288) // Interrupt Enable Command Register
+#define AIC_IDCR        (292) // Interrupt Disable Command Register
+#define AIC_ICCR        (296) // Interrupt Clear Command Register
+#define AIC_ISCR        (300) // Interrupt Set Command Register
+#define AIC_EOICR       (304) // End of Interrupt Command Register
+#define AIC_SPU         (308) // Spurious Vector Register
+#define AIC_DCR         (312) // Debug Control Register (Protect)
+#define AIC_FFER        (320) // Fast Forcing Enable Register
+#define AIC_FFDR        (324) // Fast Forcing Disable Register
+#define AIC_FFSR        (328) // Fast Forcing Status Register
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR           (0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE         (0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       (0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        (0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    (0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    (0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
+#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           (0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        (0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ            (0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ            (0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT        (0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK        (0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// *****************************************************************************
+// *** Register offset in AT91S_PDC structure ***
+#define PDC_RPR         ( 0) // Receive Pointer Register
+#define PDC_RCR         ( 4) // Receive Counter Register
+#define PDC_TPR         ( 8) // Transmit Pointer Register
+#define PDC_TCR         (12) // Transmit Counter Register
+#define PDC_RNPR        (16) // Receive Next Pointer Register
+#define PDC_RNCR        (20) // Receive Next Counter Register
+#define PDC_TNPR        (24) // Transmit Next Pointer Register
+#define PDC_TNCR        (28) // Transmit Next Counter Register
+#define PDC_PTCR        (32) // PDC Transfer Control Register
+#define PDC_PTSR        (36) // PDC Transfer Status Register
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN           (0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS          (0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN           (0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS          (0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+// *** Register offset in AT91S_DBGU structure ***
+#define DBGU_CR         ( 0) // Control Register
+#define DBGU_MR         ( 4) // Mode Register
+#define DBGU_IER        ( 8) // Interrupt Enable Register
+#define DBGU_IDR        (12) // Interrupt Disable Register
+#define DBGU_IMR        (16) // Interrupt Mask Register
+#define DBGU_CSR        (20) // Channel Status Register
+#define DBGU_RHR        (24) // Receiver Holding Register
+#define DBGU_THR        (28) // Transmitter Holding Register
+#define DBGU_BRGR       (32) // Baud Rate Generator Register
+#define DBGU_CIDR       (64) // Chip ID Register
+#define DBGU_EXID       (68) // Chip ID Extension Register
+#define DBGU_FNTR       (72) // Force NTRST Register
+#define DBGU_RPR        (256) // Receive Pointer Register
+#define DBGU_RCR        (260) // Receive Counter Register
+#define DBGU_TPR        (264) // Transmit Pointer Register
+#define DBGU_TCR        (268) // Transmit Counter Register
+#define DBGU_RNPR       (272) // Receive Next Pointer Register
+#define DBGU_RNCR       (276) // Receive Next Counter Register
+#define DBGU_TNPR       (280) // Transmit Next Pointer Register
+#define DBGU_TNCR       (284) // Transmit Next Counter Register
+#define DBGU_PTCR       (288) // PDC Transfer Control Register
+#define DBGU_PTSR       (292) // PDC Transfer Status Register
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX            (0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX            (0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN             (0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS            (0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN             (0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS            (0x1 <<  7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA           (0x1 <<  8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR              (0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE           (0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY            (0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY            (0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX            (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX            (0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE             (0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME            (0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE             (0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY          (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE           (0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF           (0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX          (0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX          (0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST      (0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+// *** Register offset in AT91S_PIO structure ***
+#define PIO_PER         ( 0) // PIO Enable Register
+#define PIO_PDR         ( 4) // PIO Disable Register
+#define PIO_PSR         ( 8) // PIO Status Register
+#define PIO_OER         (16) // Output Enable Register
+#define PIO_ODR         (20) // Output Disable Registerr
+#define PIO_OSR         (24) // Output Status Register
+#define PIO_IFER        (32) // Input Filter Enable Register
+#define PIO_IFDR        (36) // Input Filter Disable Register
+#define PIO_IFSR        (40) // Input Filter Status Register
+#define PIO_SODR        (48) // Set Output Data Register
+#define PIO_CODR        (52) // Clear Output Data Register
+#define PIO_ODSR        (56) // Output Data Status Register
+#define PIO_PDSR        (60) // Pin Data Status Register
+#define PIO_IER         (64) // Interrupt Enable Register
+#define PIO_IDR         (68) // Interrupt Disable Register
+#define PIO_IMR         (72) // Interrupt Mask Register
+#define PIO_ISR         (76) // Interrupt Status Register
+#define PIO_MDER        (80) // Multi-driver Enable Register
+#define PIO_MDDR        (84) // Multi-driver Disable Register
+#define PIO_MDSR        (88) // Multi-driver Status Register
+#define PIO_PPUDR       (96) // Pull-up Disable Register
+#define PIO_PPUER       (100) // Pull-up Enable Register
+#define PIO_PPUSR       (104) // Pull-up Status Register
+#define PIO_ASR         (112) // Select A Register
+#define PIO_BSR         (116) // Select B Register
+#define PIO_ABSR        (120) // AB Select Status Register
+#define PIO_OWER        (160) // Output Write Enable Register
+#define PIO_OWDR        (164) // Output Write Disable Register
+#define PIO_OWSR        (168) // Output Write Status Register
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+// *** Register offset in AT91S_CKGR structure ***
+#define CKGR_MOR        ( 0) // Main Oscillator Register
+#define CKGR_MCFR       ( 4) // Main Clock  Frequency Register
+#define CKGR_PLLR       (12) // PLL Register
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN         (0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS      (0x1 <<  1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT        (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF          (0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY        (0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+#define AT91C_CKGR_DIV            (0xFF <<  0) // (CKGR) Divider Selected
+#define 	AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0
+#define 	AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT       (0x3F <<  8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT            (0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define 	AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL            (0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV         (0x3 << 28) // (CKGR) Divider for USB Clocks
+#define 	AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define 	AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define 	AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+// *** Register offset in AT91S_PMC structure ***
+#define PMC_SCER        ( 0) // System Clock Enable Register
+#define PMC_SCDR        ( 4) // System Clock Disable Register
+#define PMC_SCSR        ( 8) // System Clock Status Register
+#define PMC_PCER        (16) // Peripheral Clock Enable Register
+#define PMC_PCDR        (20) // Peripheral Clock Disable Register
+#define PMC_PCSR        (24) // Peripheral Clock Status Register
+#define PMC_MOR         (32) // Main Oscillator Register
+#define PMC_MCFR        (36) // Main Clock  Frequency Register
+#define PMC_PLLR        (44) // PLL Register
+#define PMC_MCKR        (48) // Master Clock Register
+#define PMC_PCKR        (64) // Programmable Clock Register
+#define PMC_IER         (96) // Interrupt Enable Register
+#define PMC_IDR         (100) // Interrupt Disable Register
+#define PMC_SR          (104) // Status Register
+#define PMC_IMR         (108) // Interrupt Mask Register
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_PCK             (0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP             (0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0            (0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1            (0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2            (0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3            (0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS             (0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLL_CLK              (0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES            (0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS           (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK            (0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY          (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY         (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY         (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY         (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY         (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_RSTC structure ***
+#define RSTC_RCR        ( 0) // Reset Control Register
+#define RSTC_RSR        ( 4) // Reset Status Register
+#define RSTC_RMR        ( 8) // Reset Mode Register
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_RSTC_PROCRST        (0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST         (0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST         (0x1 <<  3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY            (0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_RSTC_URSTS          (0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS         (0x1 <<  1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP         (0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_RSTC_RSTTYP_POWERUP              (0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define 	AT91C_RSTC_RSTTYP_BROWNOUT             (0x5 <<  8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL          (0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP          (0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_RSTC_URSTEN         (0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN        (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL          (0xF <<  8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN         (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_RTTC structure ***
+#define RTTC_RTMR       ( 0) // Real-time Mode Register
+#define RTTC_RTAR       ( 4) // Real-time Alarm Register
+#define RTTC_RTVR       ( 8) // Real-time Value Register
+#define RTTC_RTSR       (12) // Real-time Status Register
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_RTTC_RTPRES         (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN         (0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN      (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST         (0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_RTTC_ALMV           (0x0 <<  0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_RTTC_CRTV           (0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_RTTC_ALMS           (0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC         (0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PITC structure ***
+#define PITC_PIMR       ( 0) // Period Interval Mode Register
+#define PITC_PISR       ( 4) // Period Interval Status Register
+#define PITC_PIVR       ( 8) // Period Interval Value Register
+#define PITC_PIIR       (12) // Period Interval Image Register
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_PITC_PIV            (0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN          (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN         (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_PITC_PITS           (0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_PITC_CPIV           (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT          (0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_WDTC structure ***
+#define WDTC_WDCR       ( 0) // Watchdog Control Register
+#define WDTC_WDMR       ( 4) // Watchdog Mode Register
+#define WDTC_WDSR       ( 8) // Watchdog Status Register
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_WDTC_WDRSTT         (0x1 <<  0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY            (0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_WDTC_WDV            (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN         (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN        (0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC        (0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS          (0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD            (0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT       (0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT      (0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_WDTC_WDUNF          (0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR          (0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_VREG structure ***
+#define VREG_MR         ( 0) // Voltage Regulator Mode Register
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
+#define AT91C_VREG_PSTDBY         (0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_MC structure ***
+#define MC_RCR          ( 0) // MC Remap Control Register
+#define MC_ASR          ( 4) // MC Abort Status Register
+#define MC_AASR         ( 8) // MC Abort Address Status Register
+#define MC_FMR          (96) // MC Flash Mode Register
+#define MC_FCR          (100) // MC Flash Command Register
+#define MC_FSR          (104) // MC Flash Status Register
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+#define AT91C_MC_RCB              (0x1 <<  0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+#define AT91C_MC_UNDADD           (0x1 <<  0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD           (0x1 <<  1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ            (0x3 <<  8) // (MC) Abort Size Status
+#define 	AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
+#define 	AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
+#define 	AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
+#define AT91C_MC_ABTTYP           (0x3 << 10) // (MC) Abort Type Status
+#define 	AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
+#define 	AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
+#define 	AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0             (0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1             (0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0           (0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1           (0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+#define AT91C_MC_FRDY             (0x1 <<  0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE            (0x1 <<  2) // (MC) Lock Error
+#define AT91C_MC_PROGE            (0x1 <<  3) // (MC) Programming Error
+#define AT91C_MC_NEBP             (0x1 <<  7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS              (0x3 <<  8) // (MC) Flash Wait State
+#define 	AT91C_MC_FWS_0FWS                 (0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
+#define 	AT91C_MC_FWS_1FWS                 (0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
+#define 	AT91C_MC_FWS_2FWS                 (0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
+#define 	AT91C_MC_FWS_3FWS                 (0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN             (0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+#define AT91C_MC_FCMD             (0xF <<  0) // (MC) Flash Command
+#define 	AT91C_MC_FCMD_START_PROG           (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define 	AT91C_MC_FCMD_LOCK                 (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_PROG_AND_LOCK        (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define 	AT91C_MC_FCMD_UNLOCK               (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_ERASE_ALL            (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define 	AT91C_MC_FCMD_SET_GP_NVM           (0xB) // (MC) Set General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_CLR_GP_NVM           (0xD) // (MC) Clear General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_SET_SECURITY         (0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN            (0x3FF <<  8) // (MC) Page Number
+#define AT91C_MC_KEY              (0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+#define AT91C_MC_SECURITY         (0x1 <<  4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0           (0x1 <<  8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1           (0x1 <<  9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2           (0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3           (0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4           (0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5           (0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6           (0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7           (0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0           (0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1           (0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2           (0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3           (0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4           (0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5           (0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6           (0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7           (0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8           (0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9           (0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10          (0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11          (0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12          (0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13          (0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14          (0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15          (0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_SPI structure ***
+#define SPI_CR          ( 0) // Control Register
+#define SPI_MR          ( 4) // Mode Register
+#define SPI_RDR         ( 8) // Receive Data Register
+#define SPI_TDR         (12) // Transmit Data Register
+#define SPI_SR          (16) // Status Register
+#define SPI_IER         (20) // Interrupt Enable Register
+#define SPI_IDR         (24) // Interrupt Disable Register
+#define SPI_IMR         (28) // Interrupt Mask Register
+#define SPI_CSR         (48) // Chip Select Register
+#define SPI_RPR         (256) // Receive Pointer Register
+#define SPI_RCR         (260) // Receive Counter Register
+#define SPI_TPR         (264) // Transmit Pointer Register
+#define SPI_TCR         (268) // Transmit Counter Register
+#define SPI_RNPR        (272) // Receive Next Pointer Register
+#define SPI_RNCR        (276) // Receive Next Counter Register
+#define SPI_TNPR        (280) // Transmit Next Pointer Register
+#define SPI_TNCR        (284) // Transmit Next Counter Register
+#define SPI_PTCR        (288) // PDC Transfer Control Register
+#define SPI_PTSR        (292) // PDC Transfer Status Register
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN           (0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS          (0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST           (0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER        (0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR            (0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS              (0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC          (0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV            (0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS         (0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB             (0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS             (0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS          (0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD              (0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD              (0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF            (0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE            (0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF            (0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES           (0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX           (0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX           (0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF          (0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE          (0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR            (0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY         (0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS          (0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL            (0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA           (0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT           (0x1 <<  3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS            (0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR            (0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS           (0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT          (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+// *** Register offset in AT91S_USART structure ***
+#define US_CR           ( 0) // Control Register
+#define US_MR           ( 4) // Mode Register
+#define US_IER          ( 8) // Interrupt Enable Register
+#define US_IDR          (12) // Interrupt Disable Register
+#define US_IMR          (16) // Interrupt Mask Register
+#define US_CSR          (20) // Channel Status Register
+#define US_RHR          (24) // Receiver Holding Register
+#define US_THR          (28) // Transmitter Holding Register
+#define US_BRGR         (32) // Baud Rate Generator Register
+#define US_RTOR         (36) // Receiver Time-out Register
+#define US_TTGR         (40) // Transmitter Time-guard Register
+#define US_FIDI         (64) // FI_DI_Ratio Register
+#define US_NER          (68) // Nb Errors Register
+#define US_IF           (76) // IRDA_FILTER Register
+#define US_RPR          (256) // Receive Pointer Register
+#define US_RCR          (260) // Receive Counter Register
+#define US_TPR          (264) // Transmit Pointer Register
+#define US_TCR          (268) // Transmit Counter Register
+#define US_RNPR         (272) // Receive Next Pointer Register
+#define US_RNCR         (276) // Receive Next Counter Register
+#define US_TNPR         (280) // Transmit Next Pointer Register
+#define US_TNCR         (284) // Transmit Next Counter Register
+#define US_PTCR         (288) // PDC Transfer Control Register
+#define US_PTSR         (292) // PDC Transfer Status Register
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_STTBRK           (0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK           (0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO            (0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA            (0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT            (0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK          (0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO            (0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN            (0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS           (0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN            (0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS           (0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_USMODE           (0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS             (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL             (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC             (0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP           (0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF             (0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9            (0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO             (0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER             (0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK            (0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK           (0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER         (0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER           (0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK            (0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT          (0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION        (0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK             (0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC             (0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC            (0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC            (0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC            (0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+#define AT91C_US_RI               (0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR              (0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD              (0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS              (0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_SSC structure ***
+#define SSC_CR          ( 0) // Control Register
+#define SSC_CMR         ( 4) // Clock Mode Register
+#define SSC_RCMR        (16) // Receive Clock ModeRegister
+#define SSC_RFMR        (20) // Receive Frame Mode Register
+#define SSC_TCMR        (24) // Transmit Clock Mode Register
+#define SSC_TFMR        (28) // Transmit Frame Mode Register
+#define SSC_RHR         (32) // Receive Holding Register
+#define SSC_THR         (36) // Transmit Holding Register
+#define SSC_RSHR        (48) // Receive Sync Holding Register
+#define SSC_TSHR        (52) // Transmit Sync Holding Register
+#define SSC_SR          (64) // Status Register
+#define SSC_IER         (68) // Interrupt Enable Register
+#define SSC_IDR         (72) // Interrupt Disable Register
+#define SSC_IMR         (76) // Interrupt Mask Register
+#define SSC_RPR         (256) // Receive Pointer Register
+#define SSC_RCR         (260) // Receive Counter Register
+#define SSC_TPR         (264) // Transmit Pointer Register
+#define SSC_TCR         (268) // Transmit Counter Register
+#define SSC_RNPR        (272) // Receive Next Pointer Register
+#define SSC_RNCR        (276) // Receive Next Counter Register
+#define SSC_TNPR        (280) // Transmit Next Pointer Register
+#define SSC_TNCR        (284) // Transmit Next Counter Register
+#define SSC_PTCR        (288) // PDC Transfer Control Register
+#define SSC_PTSR        (292) // PDC Transfer Status Register
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN            (0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS           (0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN            (0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS           (0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST           (0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS             (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO             (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI             (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START           (0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY          (0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD          (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN          (0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP            (0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF            (0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB           (0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN           (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS            (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE          (0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF          (0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN           (0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY           (0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY         (0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX           (0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE          (0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY           (0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN           (0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX           (0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF          (0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN           (0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN           (0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA           (0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA           (0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TWI structure ***
+#define TWI_CR          ( 0) // Control Register
+#define TWI_MMR         ( 4) // Master Mode Register
+#define TWI_IADR        (12) // Internal Address Register
+#define TWI_CWGR        (16) // Clock Waveform Generator Register
+#define TWI_SR          (32) // Status Register
+#define TWI_IER         (36) // Interrupt Enable Register
+#define TWI_IDR         (40) // Interrupt Disable Register
+#define TWI_IMR         (44) // Interrupt Mask Register
+#define TWI_RHR         (48) // Receive Holding Register
+#define TWI_THR         (52) // Transmit Holding Register
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START           (0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP            (0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN            (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS           (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST           (0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ          (0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD           (0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR            (0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV           (0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV           (0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV           (0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP          (0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY           (0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY           (0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE            (0x1 <<  6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE            (0x1 <<  7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK            (0x1 <<  8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PWMC_CH structure ***
+#define PWMC_CMR        ( 0) // Channel Mode Register
+#define PWMC_CDTYR      ( 4) // Channel Duty Cycle Register
+#define PWMC_CPRDR      ( 8) // Channel Period Register
+#define PWMC_CCNTR      (12) // Channel Counter Register
+#define PWMC_CUPDR      (16) // Channel Update Register
+#define PWMC_Reserved   (20) // Reserved
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+#define AT91C_PWMC_CPRE           (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define 	AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH) 
+#define AT91C_PWMC_CALG           (0x1 <<  8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL           (0x1 <<  9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD            (0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+#define AT91C_PWMC_CDTY           (0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+#define AT91C_PWMC_CPRD           (0x0 <<  0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+#define AT91C_PWMC_CCNT           (0x0 <<  0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+#define AT91C_PWMC_CUPD           (0x0 <<  0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PWMC structure ***
+#define PWMC_MR         ( 0) // PWMC Mode Register
+#define PWMC_ENA        ( 4) // PWMC Enable Register
+#define PWMC_DIS        ( 8) // PWMC Disable Register
+#define PWMC_SR         (12) // PWMC Status Register
+#define PWMC_IER        (16) // PWMC Interrupt Enable Register
+#define PWMC_IDR        (20) // PWMC Interrupt Disable Register
+#define PWMC_IMR        (24) // PWMC Interrupt Mask Register
+#define PWMC_ISR        (28) // PWMC Interrupt Status Register
+#define PWMC_VR         (252) // PWMC Version Register
+#define PWMC_CH         (512) // PWMC Channel
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+#define AT91C_PWMC_DIVA           (0xFF <<  0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA           (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
+#define 	AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC) 
+#define AT91C_PWMC_DIVB           (0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB           (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define 	AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC) 
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+#define AT91C_PWMC_CHID0          (0x1 <<  0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1          (0x1 <<  1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2          (0x1 <<  2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3          (0x1 <<  3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+// *** Register offset in AT91S_UDP structure ***
+#define UDP_NUM         ( 0) // Frame Number Register
+#define UDP_GLBSTATE    ( 4) // Global State Register
+#define UDP_FADDR       ( 8) // Function Address Register
+#define UDP_IER         (16) // Interrupt Enable Register
+#define UDP_IDR         (20) // Interrupt Disable Register
+#define UDP_IMR         (24) // Interrupt Mask Register
+#define UDP_ISR         (28) // Interrupt Status Register
+#define UDP_ICR         (32) // Interrupt Clear Register
+#define UDP_RSTEP       (40) // Reset Endpoint Register
+#define UDP_CSR         (48) // Endpoint Control and Status Register
+#define UDP_FDR         (80) // Endpoint FIFO Data Register
+#define UDP_TXVC        (116) // Transceiver Control Register
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+#define AT91C_UDP_FRM_NUM         (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR         (0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK          (0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+#define AT91C_UDP_FADDEN          (0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG           (0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_ESR             (0x1 <<  2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR         (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE          (0x1 <<  4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+#define AT91C_UDP_FADD            (0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN             (0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+#define AT91C_UDP_EPINT0          (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1          (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2          (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3          (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4          (0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5          (0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP          (0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM           (0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM          (0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT          (0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP          (0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+#define AT91C_UDP_ENDBUSRES       (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+#define AT91C_UDP_EP0             (0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1             (0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2             (0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3             (0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4             (0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5             (0x1 <<  5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+#define AT91C_UDP_TXCOMP          (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0     (0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP         (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR        (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY        (0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL      (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1     (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR             (0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE          (0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE           (0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS           (0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT       (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+#define AT91C_UDP_TXVDIS          (0x1 <<  8) // (UDP) 
+#define AT91C_UDP_PUON            (0x1 <<  9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TC structure ***
+#define TC_CCR          ( 0) // Channel Control Register
+#define TC_CMR          ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
+#define TC_CV           (16) // Counter Value
+#define TC_RA           (20) // Register A
+#define TC_RB           (24) // Register B
+#define TC_RC           (28) // Register C
+#define TC_SR           (32) // Status Register
+#define TC_IER          (36) // Interrupt Enable Register
+#define TC_IDR          (40) // Interrupt Disable Register
+#define TC_IMR          (44) // Interrupt Mask Register
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN            (0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS           (0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG            (0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS             (0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI             (0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST            (0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS           (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS           (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG          (0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG          (0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT             (0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG           (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG           (0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL          (0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG           (0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE             (0x1 << 15) // (TC) 
+#define AT91C_TC_ACPA             (0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA             (0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC             (0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB             (0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT            (0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG           (0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB             (0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC             (0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT            (0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG           (0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS            (0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS            (0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS             (0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS             (0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS             (0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS            (0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS            (0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRGS            (0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA           (0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA            (0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB            (0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TCB structure ***
+#define TCB_TC0         ( 0) // TC Channel 0
+#define TCB_TC1         (64) // TC Channel 1
+#define TCB_TC2         (128) // TC Channel 2
+#define TCB_BCR         (192) // TC Block Control Register
+#define TCB_BMR         (196) // TC Block Mode Register
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC            (0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S         (0x3 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S         (0x3 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S         (0x3 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
+// *****************************************************************************
+// *** Register offset in AT91S_CAN_MB structure ***
+#define CAN_MB_MMR      ( 0) // MailBox Mode Register
+#define CAN_MB_MAM      ( 4) // MailBox Acceptance Mask Register
+#define CAN_MB_MID      ( 8) // MailBox ID Register
+#define CAN_MB_MFID     (12) // MailBox Family ID Register
+#define CAN_MB_MSR      (16) // MailBox Status Register
+#define CAN_MB_MDL      (20) // MailBox Data Low Register
+#define CAN_MB_MDH      (24) // MailBox Data High Register
+#define CAN_MB_MCR      (28) // MailBox Control Register
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
+#define AT91C_CAN_MTIMEMARK       (0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR           (0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT             (0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define 	AT91C_CAN_MOT_DIS                  (0x0 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RX                   (0x1 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RXOVERWRITE          (0x2 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_TX                   (0x3 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_CONSUMER             (0x4 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_PRODUCER             (0x5 << 24) // (CAN_MB) 
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
+#define AT91C_CAN_MIDvB           (0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA           (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE            (0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
+#define AT91C_CAN_MTIMESTAMP      (0xFFFF <<  0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC            (0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR            (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT            (0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY            (0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI             (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
+#define AT91C_CAN_MACR            (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR            (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
+// *****************************************************************************
+// *** Register offset in AT91S_CAN structure ***
+#define CAN_MR          ( 0) // Mode Register
+#define CAN_IER         ( 4) // Interrupt Enable Register
+#define CAN_IDR         ( 8) // Interrupt Disable Register
+#define CAN_IMR         (12) // Interrupt Mask Register
+#define CAN_SR          (16) // Status Register
+#define CAN_BR          (20) // Baudrate Register
+#define CAN_TIM         (24) // Timer Register
+#define CAN_TIMESTP     (28) // Time Stamp Register
+#define CAN_ECR         (32) // Error Counter Register
+#define CAN_TCR         (36) // Transfer Command Register
+#define CAN_ACR         (40) // Abort Command Register
+#define CAN_VR          (252) // Version Register
+#define CAN_MB0         (512) // CAN Mailbox 0
+#define CAN_MB1         (544) // CAN Mailbox 1
+#define CAN_MB2         (576) // CAN Mailbox 2
+#define CAN_MB3         (608) // CAN Mailbox 3
+#define CAN_MB4         (640) // CAN Mailbox 4
+#define CAN_MB5         (672) // CAN Mailbox 5
+#define CAN_MB6         (704) // CAN Mailbox 6
+#define CAN_MB7         (736) // CAN Mailbox 7
+#define CAN_MB8         (768) // CAN Mailbox 8
+#define CAN_MB9         (800) // CAN Mailbox 9
+#define CAN_MB10        (832) // CAN Mailbox 10
+#define CAN_MB11        (864) // CAN Mailbox 11
+#define CAN_MB12        (896) // CAN Mailbox 12
+#define CAN_MB13        (928) // CAN Mailbox 13
+#define CAN_MB14        (960) // CAN Mailbox 14
+#define CAN_MB15        (992) // CAN Mailbox 15
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
+#define AT91C_CAN_CANEN           (0x1 <<  0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM             (0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM             (0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL             (0x1 <<  3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF            (0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM             (0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ          (0x1 <<  6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT            (0x1 <<  7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
+#define AT91C_CAN_MB0             (0x1 <<  0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1             (0x1 <<  1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2             (0x1 <<  2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3             (0x1 <<  3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4             (0x1 <<  4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5             (0x1 <<  5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6             (0x1 <<  6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7             (0x1 <<  7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8             (0x1 <<  8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9             (0x1 <<  9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10            (0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11            (0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12            (0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13            (0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14            (0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15            (0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA            (0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN            (0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP            (0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF            (0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP           (0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP          (0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF            (0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP            (0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR            (0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR            (0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR            (0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR            (0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR            (0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
+#define AT91C_CAN_RBSY            (0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY            (0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY            (0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
+#define AT91C_CAN_PHASE2          (0x7 <<  0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1          (0x7 <<  4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG          (0x7 <<  8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC            (0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP             (0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP             (0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
+#define AT91C_CAN_TIMER           (0xFFFF <<  0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
+#define AT91C_CAN_REC             (0xFF <<  0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC             (0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
+#define AT91C_CAN_TIMRST          (0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// *****************************************************************************
+// *** Register offset in AT91S_EMAC structure ***
+#define EMAC_NCR        ( 0) // Network Control Register
+#define EMAC_NCFGR      ( 4) // Network Configuration Register
+#define EMAC_NSR        ( 8) // Network Status Register
+#define EMAC_TSR        (20) // Transmit Status Register
+#define EMAC_RBQP       (24) // Receive Buffer Queue Pointer
+#define EMAC_TBQP       (28) // Transmit Buffer Queue Pointer
+#define EMAC_RSR        (32) // Receive Status Register
+#define EMAC_ISR        (36) // Interrupt Status Register
+#define EMAC_IER        (40) // Interrupt Enable Register
+#define EMAC_IDR        (44) // Interrupt Disable Register
+#define EMAC_IMR        (48) // Interrupt Mask Register
+#define EMAC_MAN        (52) // PHY Maintenance Register
+#define EMAC_PTR        (56) // Pause Time Register
+#define EMAC_PFR        (60) // Pause Frames received Register
+#define EMAC_FTO        (64) // Frames Transmitted OK Register
+#define EMAC_SCF        (68) // Single Collision Frame Register
+#define EMAC_MCF        (72) // Multiple Collision Frame Register
+#define EMAC_FRO        (76) // Frames Received OK Register
+#define EMAC_FCSE       (80) // Frame Check Sequence Error Register
+#define EMAC_ALE        (84) // Alignment Error Register
+#define EMAC_DTF        (88) // Deferred Transmission Frame Register
+#define EMAC_LCOL       (92) // Late Collision Register
+#define EMAC_ECOL       (96) // Excessive Collision Register
+#define EMAC_TUND       (100) // Transmit Underrun Error Register
+#define EMAC_CSE        (104) // Carrier Sense Error Register
+#define EMAC_RRE        (108) // Receive Ressource Error Register
+#define EMAC_ROV        (112) // Receive Overrun Errors Register
+#define EMAC_RSE        (116) // Receive Symbol Errors Register
+#define EMAC_ELE        (120) // Excessive Length Errors Register
+#define EMAC_RJA        (124) // Receive Jabbers Register
+#define EMAC_USF        (128) // Undersize Frames Register
+#define EMAC_STE        (132) // SQE Test Error Register
+#define EMAC_RLE        (136) // Receive Length Field Mismatch Register
+#define EMAC_TPF        (140) // Transmitted Pause Frames Register
+#define EMAC_HRB        (144) // Hash Address Bottom[31:0]
+#define EMAC_HRT        (148) // Hash Address Top[63:32]
+#define EMAC_SA1L       (152) // Specific Address 1 Bottom, First 4 bytes
+#define EMAC_SA1H       (156) // Specific Address 1 Top, Last 2 bytes
+#define EMAC_SA2L       (160) // Specific Address 2 Bottom, First 4 bytes
+#define EMAC_SA2H       (164) // Specific Address 2 Top, Last 2 bytes
+#define EMAC_SA3L       (168) // Specific Address 3 Bottom, First 4 bytes
+#define EMAC_SA3H       (172) // Specific Address 3 Top, Last 2 bytes
+#define EMAC_SA4L       (176) // Specific Address 4 Bottom, First 4 bytes
+#define EMAC_SA4H       (180) // Specific Address 4 Top, Last 2 bytes
+#define EMAC_TID        (184) // Type ID Checking Register
+#define EMAC_TPQ        (188) // Transmit Pause Quantum Register
+#define EMAC_USRIO      (192) // USER Input/Output Register
+#define EMAC_WOL        (196) // Wake On LAN Register
+#define EMAC_REV        (252) // Revision Register
+// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+#define AT91C_EMAC_LB             (0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB            (0x1 <<  1) // (EMAC) Loopback local. 
+#define AT91C_EMAC_RE             (0x1 <<  2) // (EMAC) Receive enable. 
+#define AT91C_EMAC_TE             (0x1 <<  3) // (EMAC) Transmit enable. 
+#define AT91C_EMAC_MPE            (0x1 <<  4) // (EMAC) Management port enable. 
+#define AT91C_EMAC_CLRSTAT        (0x1 <<  5) // (EMAC) Clear statistics registers. 
+#define AT91C_EMAC_INCSTAT        (0x1 <<  6) // (EMAC) Increment statistics registers. 
+#define AT91C_EMAC_WESTAT         (0x1 <<  7) // (EMAC) Write enable for statistics registers. 
+#define AT91C_EMAC_BP             (0x1 <<  8) // (EMAC) Back pressure. 
+#define AT91C_EMAC_TSTART         (0x1 <<  9) // (EMAC) Start Transmission. 
+#define AT91C_EMAC_THALT          (0x1 << 10) // (EMAC) Transmission Halt. 
+#define AT91C_EMAC_TPFR           (0x1 << 11) // (EMAC) Transmit pause frame 
+#define AT91C_EMAC_TZQ            (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+#define AT91C_EMAC_SPD            (0x1 <<  0) // (EMAC) Speed. 
+#define AT91C_EMAC_FD             (0x1 <<  1) // (EMAC) Full duplex. 
+#define AT91C_EMAC_JFRAME         (0x1 <<  3) // (EMAC) Jumbo Frames. 
+#define AT91C_EMAC_CAF            (0x1 <<  4) // (EMAC) Copy all frames. 
+#define AT91C_EMAC_NBC            (0x1 <<  5) // (EMAC) No broadcast. 
+#define AT91C_EMAC_MTI            (0x1 <<  6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI            (0x1 <<  7) // (EMAC) Unicast hash enable. 
+#define AT91C_EMAC_BIG            (0x1 <<  8) // (EMAC) Receive 1522 bytes. 
+#define AT91C_EMAC_EAE            (0x1 <<  9) // (EMAC) External address match enable. 
+#define AT91C_EMAC_CLK            (0x3 << 10) // (EMAC) 
+#define 	AT91C_EMAC_CLK_HCLK_8               (0x0 << 10) // (EMAC) HCLK divided by 8
+#define 	AT91C_EMAC_CLK_HCLK_16              (0x1 << 10) // (EMAC) HCLK divided by 16
+#define 	AT91C_EMAC_CLK_HCLK_32              (0x2 << 10) // (EMAC) HCLK divided by 32
+#define 	AT91C_EMAC_CLK_HCLK_64              (0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY            (0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PAE            (0x1 << 13) // (EMAC) 
+#define AT91C_EMAC_RBOF           (0x3 << 14) // (EMAC) 
+#define 	AT91C_EMAC_RBOF_OFFSET_0             (0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_1             (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_2             (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_3             (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE           (0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS          (0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD          (0x1 << 18) // (EMAC) 
+#define AT91C_EMAC_IRXFCS         (0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+#define AT91C_EMAC_LINKR          (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_MDIO           (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_IDLE           (0x1 <<  2) // (EMAC) 
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+#define AT91C_EMAC_UBR            (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_COL            (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RLES           (0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TGO            (0x1 <<  3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX            (0x1 <<  4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP           (0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_UND            (0x1 <<  6) // (EMAC) 
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+#define AT91C_EMAC_BNA            (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_REC            (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_OVR            (0x1 <<  2) // (EMAC) 
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+#define AT91C_EMAC_MFD            (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_RCOMP          (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RXUBR          (0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TXUBR          (0x1 <<  3) // (EMAC) 
+#define AT91C_EMAC_TUNDR          (0x1 <<  4) // (EMAC) 
+#define AT91C_EMAC_RLEX           (0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_TXERR          (0x1 <<  6) // (EMAC) 
+#define AT91C_EMAC_TCOMP          (0x1 <<  7) // (EMAC) 
+#define AT91C_EMAC_LINK           (0x1 <<  9) // (EMAC) 
+#define AT91C_EMAC_ROVR           (0x1 << 10) // (EMAC) 
+#define AT91C_EMAC_HRESP          (0x1 << 11) // (EMAC) 
+#define AT91C_EMAC_PFRE           (0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PTZ            (0x1 << 13) // (EMAC) 
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+#define AT91C_EMAC_DATA           (0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_CODE           (0x3 << 16) // (EMAC) 
+#define AT91C_EMAC_REGA           (0x1F << 18) // (EMAC) 
+#define AT91C_EMAC_PHYA           (0x1F << 23) // (EMAC) 
+#define AT91C_EMAC_RW             (0x3 << 28) // (EMAC) 
+#define AT91C_EMAC_SOF            (0x3 << 30) // (EMAC) 
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+#define AT91C_EMAC_RMII           (0x1 <<  0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+#define AT91C_EMAC_IP             (0xFFFF <<  0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG            (0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP            (0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1            (0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+#define AT91C_EMAC_REVREF         (0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_PARTREF        (0xFFFF << 16) // (EMAC) 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// *****************************************************************************
+// *** Register offset in AT91S_ADC structure ***
+#define ADC_CR          ( 0) // ADC Control Register
+#define ADC_MR          ( 4) // ADC Mode Register
+#define ADC_CHER        (16) // ADC Channel Enable Register
+#define ADC_CHDR        (20) // ADC Channel Disable Register
+#define ADC_CHSR        (24) // ADC Channel Status Register
+#define ADC_SR          (28) // ADC Status Register
+#define ADC_LCDR        (32) // ADC Last Converted Data Register
+#define ADC_IER         (36) // ADC Interrupt Enable Register
+#define ADC_IDR         (40) // ADC Interrupt Disable Register
+#define ADC_IMR         (44) // ADC Interrupt Mask Register
+#define ADC_CDR0        (48) // ADC Channel Data Register 0
+#define ADC_CDR1        (52) // ADC Channel Data Register 1
+#define ADC_CDR2        (56) // ADC Channel Data Register 2
+#define ADC_CDR3        (60) // ADC Channel Data Register 3
+#define ADC_CDR4        (64) // ADC Channel Data Register 4
+#define ADC_CDR5        (68) // ADC Channel Data Register 5
+#define ADC_CDR6        (72) // ADC Channel Data Register 6
+#define ADC_CDR7        (76) // ADC Channel Data Register 7
+#define ADC_RPR         (256) // Receive Pointer Register
+#define ADC_RCR         (260) // Receive Counter Register
+#define ADC_TPR         (264) // Transmit Pointer Register
+#define ADC_TCR         (268) // Transmit Counter Register
+#define ADC_RNPR        (272) // Receive Next Pointer Register
+#define ADC_RNCR        (276) // Receive Next Counter Register
+#define ADC_TNPR        (280) // Transmit Next Pointer Register
+#define ADC_TNCR        (284) // Transmit Next Counter Register
+#define ADC_PTCR        (288) // PDC Transfer Control Register
+#define ADC_PTSR        (292) // PDC Transfer Status Register
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+#define AT91C_ADC_SWRST           (0x1 <<  0) // (ADC) Software Reset
+#define AT91C_ADC_START           (0x1 <<  1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+#define AT91C_ADC_TRGEN           (0x1 <<  0) // (ADC) Trigger Enable
+#define 	AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define 	AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL          (0x7 <<  1) // (ADC) Trigger Selection
+#define 	AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
+#define 	AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
+#define 	AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
+#define 	AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
+#define 	AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
+#define 	AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
+#define 	AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES          (0x1 <<  4) // (ADC) Resolution.
+#define 	AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
+#define 	AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP           (0x1 <<  5) // (ADC) Sleep Mode
+#define 	AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
+#define 	AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL         (0x3F <<  8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP         (0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM           (0xF << 24) // (ADC) Sample & Hold Time
+// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+#define AT91C_ADC_CH0             (0x1 <<  0) // (ADC) Channel 0
+#define AT91C_ADC_CH1             (0x1 <<  1) // (ADC) Channel 1
+#define AT91C_ADC_CH2             (0x1 <<  2) // (ADC) Channel 2
+#define AT91C_ADC_CH3             (0x1 <<  3) // (ADC) Channel 3
+#define AT91C_ADC_CH4             (0x1 <<  4) // (ADC) Channel 4
+#define AT91C_ADC_CH5             (0x1 <<  5) // (ADC) Channel 5
+#define AT91C_ADC_CH6             (0x1 <<  6) // (ADC) Channel 6
+#define AT91C_ADC_CH7             (0x1 <<  7) // (ADC) Channel 7
+// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+#define AT91C_ADC_EOC0            (0x1 <<  0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1            (0x1 <<  1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2            (0x1 <<  2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3            (0x1 <<  3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4            (0x1 <<  4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5            (0x1 <<  5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6            (0x1 <<  6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7            (0x1 <<  7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0           (0x1 <<  8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1           (0x1 <<  9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2           (0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3           (0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4           (0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5           (0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6           (0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7           (0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY            (0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE           (0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX           (0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF          (0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+#define AT91C_ADC_LDATA           (0x3FF <<  0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+#define AT91C_ADC_DATA            (0x3FF <<  0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
+// *****************************************************************************
+// *** Register offset in AT91S_AES structure ***
+#define AES_CR          ( 0) // Control Register
+#define AES_MR          ( 4) // Mode Register
+#define AES_IER         (16) // Interrupt Enable Register
+#define AES_IDR         (20) // Interrupt Disable Register
+#define AES_IMR         (24) // Interrupt Mask Register
+#define AES_ISR         (28) // Interrupt Status Register
+#define AES_KEYWxR      (32) // Key Word x Register
+#define AES_IDATAxR     (64) // Input Data x Register
+#define AES_ODATAxR     (80) // Output Data x Register
+#define AES_IVxR        (96) // Initialization Vector x Register
+#define AES_VR          (252) // AES Version Register
+#define AES_RPR         (256) // Receive Pointer Register
+#define AES_RCR         (260) // Receive Counter Register
+#define AES_TPR         (264) // Transmit Pointer Register
+#define AES_TCR         (268) // Transmit Counter Register
+#define AES_RNPR        (272) // Receive Next Pointer Register
+#define AES_RNCR        (276) // Receive Next Counter Register
+#define AES_TNPR        (280) // Transmit Next Pointer Register
+#define AES_TNCR        (284) // Transmit Next Counter Register
+#define AES_PTCR        (288) // PDC Transfer Control Register
+#define AES_PTSR        (292) // PDC Transfer Status Register
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
+#define AT91C_AES_START           (0x1 <<  0) // (AES) Starts Processing
+#define AT91C_AES_SWRST           (0x1 <<  8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED        (0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
+#define AT91C_AES_CIPHER          (0x1 <<  0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY         (0xF <<  4) // (AES) Processing Delay
+#define AT91C_AES_SMOD            (0x3 <<  8) // (AES) Start Mode
+#define 	AT91C_AES_SMOD_MANUAL               (0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define 	AT91C_AES_SMOD_AUTO                 (0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define 	AT91C_AES_SMOD_PDC                  (0x2 <<  8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD           (0x7 << 12) // (AES) Operation Mode
+#define 	AT91C_AES_OPMOD_ECB                  (0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define 	AT91C_AES_OPMOD_CBC                  (0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define 	AT91C_AES_OPMOD_OFB                  (0x2 << 12) // (AES) OFB Output Feedback mode.
+#define 	AT91C_AES_OPMOD_CFB                  (0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define 	AT91C_AES_OPMOD_CTR                  (0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD             (0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS            (0x7 << 16) // (AES) Cipher Feedback Data Size
+#define 	AT91C_AES_CFBS_128_BIT              (0x0 << 16) // (AES) 128-bit.
+#define 	AT91C_AES_CFBS_64_BIT               (0x1 << 16) // (AES) 64-bit.
+#define 	AT91C_AES_CFBS_32_BIT               (0x2 << 16) // (AES) 32-bit.
+#define 	AT91C_AES_CFBS_16_BIT               (0x3 << 16) // (AES) 16-bit.
+#define 	AT91C_AES_CFBS_8_BIT                (0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY            (0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE           (0x1F << 24) // (AES) Countermeasure Type
+#define 	AT91C_AES_CTYPE_TYPE1_EN             (0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE2_EN             (0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE3_EN             (0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE4_EN             (0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE5_EN             (0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_AES_DATRDY          (0x1 <<  0) // (AES) DATRDY
+#define AT91C_AES_ENDRX           (0x1 <<  1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX           (0x1 <<  2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF          (0x1 <<  3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE          (0x1 <<  4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD            (0x1 <<  8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_AES_URAT            (0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  (0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define 	AT91C_AES_URAT_WO_REG_READ          (0x5 << 12) // (AES) Write-only register read access.
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
+// *****************************************************************************
+// *** Register offset in AT91S_TDES structure ***
+#define TDES_CR         ( 0) // Control Register
+#define TDES_MR         ( 4) // Mode Register
+#define TDES_IER        (16) // Interrupt Enable Register
+#define TDES_IDR        (20) // Interrupt Disable Register
+#define TDES_IMR        (24) // Interrupt Mask Register
+#define TDES_ISR        (28) // Interrupt Status Register
+#define TDES_KEY1WxR    (32) // Key 1 Word x Register
+#define TDES_KEY2WxR    (40) // Key 2 Word x Register
+#define TDES_KEY3WxR    (48) // Key 3 Word x Register
+#define TDES_IDATAxR    (64) // Input Data x Register
+#define TDES_ODATAxR    (80) // Output Data x Register
+#define TDES_IVxR       (96) // Initialization Vector x Register
+#define TDES_VR         (252) // TDES Version Register
+#define TDES_RPR        (256) // Receive Pointer Register
+#define TDES_RCR        (260) // Receive Counter Register
+#define TDES_TPR        (264) // Transmit Pointer Register
+#define TDES_TCR        (268) // Transmit Counter Register
+#define TDES_RNPR       (272) // Receive Next Pointer Register
+#define TDES_RNCR       (276) // Receive Next Counter Register
+#define TDES_TNPR       (280) // Transmit Next Pointer Register
+#define TDES_TNCR       (284) // Transmit Next Counter Register
+#define TDES_PTCR       (288) // PDC Transfer Control Register
+#define TDES_PTSR       (292) // PDC Transfer Status Register
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
+#define AT91C_TDES_START          (0x1 <<  0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST          (0x1 <<  8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
+#define AT91C_TDES_CIPHER         (0x1 <<  0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD        (0x1 <<  1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD         (0x1 <<  4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD           (0x3 <<  8) // (TDES) Start Mode
+#define 	AT91C_TDES_SMOD_MANUAL               (0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define 	AT91C_TDES_SMOD_AUTO                 (0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define 	AT91C_TDES_SMOD_PDC                  (0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD          (0x3 << 12) // (TDES) Operation Mode
+#define 	AT91C_TDES_OPMOD_ECB                  (0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define 	AT91C_TDES_OPMOD_CBC                  (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define 	AT91C_TDES_OPMOD_OFB                  (0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define 	AT91C_TDES_OPMOD_CFB                  (0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD            (0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS           (0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define 	AT91C_TDES_CFBS_64_BIT               (0x0 << 16) // (TDES) 64-bit.
+#define 	AT91C_TDES_CFBS_32_BIT               (0x1 << 16) // (TDES) 32-bit.
+#define 	AT91C_TDES_CFBS_16_BIT               (0x2 << 16) // (TDES) 16-bit.
+#define 	AT91C_TDES_CFBS_8_BIT                (0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_TDES_DATRDY         (0x1 <<  0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX          (0x1 <<  1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX          (0x1 <<  2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF         (0x1 <<  3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE         (0x1 <<  4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD           (0x1 <<  8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_TDES_URAT           (0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing.
+#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing.
+#define 	AT91C_TDES_URAT_WO_REG_READ          (0x3 << 12) // (TDES) Write-only register read access.
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ========== 
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_IVR             (0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR             (0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR             (0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR             (0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR           (0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR             (0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR            (0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR            (0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR             (0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR             (0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR             (0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER            (0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR            (0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR            (0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR            (0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR            (0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR            (0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU             (0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_TCR            (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR           (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR           (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR            (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR            (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR            (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR           (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR           (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR           (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR           (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_EXID           (0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR           (0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR            (0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR            (0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR           (0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR             (0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR            (0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR             (0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR           (0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR            (0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR            (0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER            (0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_ODR            (0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR           (0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR            (0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR           (0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER            (0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR          (0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR            (0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER            (0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR           (0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR           (0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR           (0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR            (0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR           (0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR          (0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR           (0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR            (0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER           (0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER           (0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR           (0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER          (0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR            (0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR            (0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR           (0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR           (0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER           (0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR            (0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR           (0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER            (0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR            (0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ========== 
+#define AT91C_PIOB_OWDR           (0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER           (0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR          (0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR            (0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR            (0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR          (0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR            (0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER            (0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR           (0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER           (0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR           (0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR           (0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR           (0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR            (0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR           (0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR            (0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR            (0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR           (0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER          (0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR           (0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR            (0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR           (0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR            (0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR           (0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER           (0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR            (0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR           (0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER            (0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER            (0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_MOR            (0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR           (0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR           (0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_IDR             (0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR             (0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR            (0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER            (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR            (0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR            (0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR            (0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR            (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR            (0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR            (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR            (0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_SCER            (0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR             (0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER             (0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR              (0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RCR            (0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR            (0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR            (0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR           (0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR           (0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR           (0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR           (0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIVR           (0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR           (0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR           (0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR           (0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDCR           (0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR           (0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR           (0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ========== 
+#define AT91C_VREG_MR             (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ========== 
+#define AT91C_MC_ASR              (0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR              (0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR              (0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR             (0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR              (0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR              (0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ========== 
+#define AT91C_SPI1_PTCR           (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR            (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR           (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR            (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR           (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR            (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR            (0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR           (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR           (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR           (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ========== 
+#define AT91C_SPI1_IMR            (0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER            (0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR             (0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR            (0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR            (0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR             (0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR            (0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR             (0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR            (0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ========== 
+#define AT91C_SPI0_PTCR           (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR            (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR            (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR            (0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR           (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR           (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR            (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR           (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR           (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR           (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ========== 
+#define AT91C_SPI0_IER            (0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR             (0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR            (0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR             (0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR             (0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR            (0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR            (0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR            (0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR            (0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_RNCR            (0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR            (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR             (0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR            (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR            (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR             (0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR            (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR             (0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR            (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR             (0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_IF              (0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER             (0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR            (0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR             (0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR             (0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER             (0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR             (0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR            (0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR             (0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR            (0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR             (0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI            (0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR              (0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR              (0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_TNPR            (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR            (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR             (0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR            (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR            (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR            (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR             (0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR             (0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR             (0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR            (0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_BRGR            (0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER             (0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR              (0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR             (0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI            (0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR            (0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR              (0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR            (0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR             (0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR             (0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR             (0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR             (0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF              (0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER             (0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ========== 
+#define AT91C_SSC_TNCR            (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR             (0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR            (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR             (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR            (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR             (0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR             (0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR            (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR            (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR            (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ========== 
+#define AT91C_SSC_RHR             (0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR            (0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR            (0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR             (0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR             (0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR            (0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER             (0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR            (0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR              (0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR             (0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR            (0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR              (0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR             (0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR            (0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ========== 
+#define AT91C_TWI_IER             (0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR              (0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR              (0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR             (0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR             (0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR             (0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR            (0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR             (0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR            (0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR             (0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ========== 
+#define AT91C_PWMC_CH3_CUPDR      (0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved   (0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR      (0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR      (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR      (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR        (0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ========== 
+#define AT91C_PWMC_CH2_Reserved   (0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR        (0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR      (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR      (0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR      (0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR      (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ========== 
+#define AT91C_PWMC_CH1_Reserved   (0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR      (0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR      (0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR      (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR      (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR        (0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ========== 
+#define AT91C_PWMC_CH0_Reserved   (0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR      (0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR      (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR        (0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR      (0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR      (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ========== 
+#define AT91C_PWMC_IDR            (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS            (0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER            (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR             (0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR            (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR             (0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR            (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR             (0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA            (0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ========== 
+#define AT91C_UDP_IMR             (0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR           (0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM             (0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR             (0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR             (0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR             (0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR             (0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR             (0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP           (0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC            (0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE        (0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER             (0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_SR              (0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC              (0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB              (0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR             (0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR             (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER             (0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA              (0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR             (0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV              (0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR             (0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_RB              (0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR             (0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER             (0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR             (0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR              (0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR             (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA              (0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC              (0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR             (0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV              (0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_CMR             (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR             (0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV              (0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA              (0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB              (0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR             (0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR             (0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC              (0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER             (0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR              (0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ========== 
+#define AT91C_TCB_BMR             (0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR             (0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ========== 
+#define AT91C_CAN_MB0_MDL         (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM         (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR         (0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID         (0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR         (0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID        (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH         (0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR         (0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ========== 
+#define AT91C_CAN_MB1_MDL         (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID         (0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR         (0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR         (0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM         (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH         (0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR         (0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID        (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ========== 
+#define AT91C_CAN_MB2_MCR         (0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH         (0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID         (0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL         (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR         (0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM         (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID        (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR         (0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ========== 
+#define AT91C_CAN_MB3_MFID        (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM         (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID         (0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR         (0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR         (0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR         (0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL         (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH         (0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ========== 
+#define AT91C_CAN_MB4_MID         (0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR         (0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH         (0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID        (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR         (0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR         (0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL         (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM         (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ========== 
+#define AT91C_CAN_MB5_MSR         (0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR         (0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID        (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH         (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID         (0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR         (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL         (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM         (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ========== 
+#define AT91C_CAN_MB6_MFID        (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID         (0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM         (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR         (0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL         (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR         (0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH         (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR         (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ========== 
+#define AT91C_CAN_MB7_MCR         (0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH         (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID        (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL         (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID         (0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR         (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM         (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR         (0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ========== 
+#define AT91C_CAN_TCR             (0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR             (0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER             (0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR             (0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP         (0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR              (0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR             (0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR             (0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM             (0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR              (0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR              (0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR              (0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ========== 
+#define AT91C_EMAC_ISR            (0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H           (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L           (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE            (0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL           (0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE            (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL            (0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF            (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND           (0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR            (0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L           (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR            (0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L           (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR            (0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR            (0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE            (0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL           (0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID            (0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB            (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP           (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO          (0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR            (0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H           (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV            (0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE            (0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA            (0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP           (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF            (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR          (0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT            (0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF            (0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE           (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ            (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN            (0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO            (0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV            (0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR            (0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF            (0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR            (0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF            (0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR            (0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L           (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO            (0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER            (0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H           (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE            (0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H           (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE            (0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE            (0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ========== 
+#define AT91C_ADC_PTSR            (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR            (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR            (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR            (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR            (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR            (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR             (0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR             (0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR             (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR             (0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ========== 
+#define AT91C_ADC_CDR2            (0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3            (0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0            (0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5            (0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR            (0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR              (0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4            (0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1            (0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR            (0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR             (0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR              (0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7            (0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6            (0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER             (0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER            (0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR            (0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR              (0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR             (0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ========== 
+#define AT91C_AES_TPR             (0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR            (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR            (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR            (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR             (0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR             (0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR            (0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR            (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR             (0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR            (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ========== 
+#define AT91C_AES_IVxR            (0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR              (0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR              (0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR         (0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR         (0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR              (0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR             (0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR             (0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER             (0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR          (0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR             (0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ========== 
+#define AT91C_TDES_RNCR           (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR            (0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR            (0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR           (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR           (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR            (0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR           (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR            (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR           (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR           (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ========== 
+#define AT91C_TDES_KEY2WxR        (0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR        (0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR            (0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR             (0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR           (0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR        (0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR            (0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR             (0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR             (0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER            (0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR            (0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR        (0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR        (0xFFFA8020) // (TDES) Key 1 Word x Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_PIO_PA0             (1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0            (AT91C_PIO_PA0) //  USART 0 Receive Data
+#define AT91C_PIO_PA1             (1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0            (AT91C_PIO_PA1) //  USART 0 Transmit Data
+#define AT91C_PIO_PA10            (1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD            (AT91C_PIO_PA10) //  TWI Two-wire Serial Data
+#define AT91C_PIO_PA11            (1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK           (AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12            (1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00         (AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13            (1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01         (AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1           (AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14            (1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02         (AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1           (AT91C_PIO_PA14) //  External Interrupt 1
+#define AT91C_PIO_PA15            (1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03         (AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2          (AT91C_PIO_PA15) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PA16            (1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0          (AT91C_PIO_PA16) //  SPI 0 Master In Slave
+#define AT91C_PIO_PA17            (1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0          (AT91C_PIO_PA17) //  SPI 0 Master Out Slave
+#define AT91C_PIO_PA18            (1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0          (AT91C_PIO_PA18) //  SPI 0 Serial Clock
+#define AT91C_PIO_PA19            (1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX          (AT91C_PIO_PA19) //  CAN Receive
+#define AT91C_PIO_PA2             (1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0            (AT91C_PIO_PA2) //  USART 0 Serial Clock
+#define AT91C_PA2_NPCS11          (AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20            (1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX          (AT91C_PIO_PA20) //  CAN Transmit
+#define AT91C_PIO_PA21            (1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF             (AT91C_PIO_PA21) //  SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10         (AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22            (1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK             (AT91C_PIO_PA22) //  SSC Transmit Clock
+#define AT91C_PA22_SPCK1          (AT91C_PIO_PA22) //  SPI 1 Serial Clock
+#define AT91C_PIO_PA23            (1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD             (AT91C_PIO_PA23) //  SSC Transmit data
+#define AT91C_PA23_MOSI1          (AT91C_PIO_PA23) //  SPI 1 Master Out Slave
+#define AT91C_PIO_PA24            (1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD             (AT91C_PIO_PA24) //  SSC Receive Data
+#define AT91C_PA24_MISO1          (AT91C_PIO_PA24) //  SPI 1 Master In Slave
+#define AT91C_PIO_PA25            (1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK             (AT91C_PIO_PA25) //  SSC Receive Clock
+#define AT91C_PA25_NPCS11         (AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26            (1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF             (AT91C_PIO_PA26) //  SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12         (AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27            (1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD           (AT91C_PIO_PA27) //  DBGU Debug Receive Data
+#define AT91C_PA27_PCK3           (AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28            (1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD           (AT91C_PIO_PA28) //  DBGU Debug Transmit Data
+#define AT91C_PIO_PA29            (1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ            (AT91C_PIO_PA29) //  AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13         (AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3             (1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0            (AT91C_PIO_PA3) //  USART 0 Ready To Send
+#define AT91C_PA3_NPCS12          (AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30            (1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0           (AT91C_PIO_PA30) //  External Interrupt 0
+#define AT91C_PA30_PCK2           (AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4             (1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0            (AT91C_PIO_PA4) //  USART 0 Clear To Send
+#define AT91C_PA4_NPCS13          (AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5             (1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1            (AT91C_PIO_PA5) //  USART 1 Receive Data
+#define AT91C_PIO_PA6             (1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1            (AT91C_PIO_PA6) //  USART 1 Transmit Data
+#define AT91C_PIO_PA7             (1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1            (AT91C_PIO_PA7) //  USART 1 Serial Clock
+#define AT91C_PA7_NPCS01          (AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8             (1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1            (AT91C_PIO_PA8) //  USART 1 Ready To Send
+#define AT91C_PA8_NPCS02          (AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9             (1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1            (AT91C_PIO_PA9) //  USART 1 Clear To Send
+#define AT91C_PA9_NPCS03          (AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0             (1 <<  0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK    (AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0            (AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1             (1 <<  1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN           (AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10            (1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2           (AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11         (AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11            (1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3           (AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12         (AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12            (1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER          (AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0          (AT91C_PIO_PB12) //  Timer Counter 0 external clock input
+#define AT91C_PIO_PB13            (1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2           (AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01         (AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14            (1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3           (AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02         (AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15            (1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV          (AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16            (1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL           (AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13         (AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17            (1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK          (AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03         (AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18            (1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100          (AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG          (AT91C_PIO_PB18) //  ADC External Trigger
+#define AT91C_PIO_PB19            (1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0           (AT91C_PIO_PB19) //  PWM Channel 0
+#define AT91C_PB19_TCLK1          (AT91C_PIO_PB19) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PB2             (1 <<  2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0            (AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20            (1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1           (AT91C_PIO_PB20) //  PWM Channel 1
+#define AT91C_PB20_PCK0           (AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21            (1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2           (AT91C_PIO_PB21) //  PWM Channel 2
+#define AT91C_PB21_PCK1           (AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22            (1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3           (AT91C_PIO_PB22) //  PWM Channel 3
+#define AT91C_PB22_PCK2           (AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23            (1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0          (AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1           (AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24            (1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0          (AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1           (AT91C_PIO_PB24) //  USART 1 Data Set ready
+#define AT91C_PIO_PB25            (1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1          (AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1           (AT91C_PIO_PB25) //  USART 1 Data Terminal ready
+#define AT91C_PIO_PB26            (1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1          (AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1            (AT91C_PIO_PB26) //  USART 1 Ring Indicator
+#define AT91C_PIO_PB27            (1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2          (AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0           (AT91C_PIO_PB27) //  PWM Channel 0
+#define AT91C_PIO_PB28            (1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2          (AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1           (AT91C_PIO_PB28) //  PWM Channel 1
+#define AT91C_PIO_PB29            (1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1           (AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2           (AT91C_PIO_PB29) //  PWM Channel 2
+#define AT91C_PIO_PB3             (1 <<  3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1            (AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30            (1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2           (AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3           (AT91C_PIO_PB30) //  PWM Channel 3
+#define AT91C_PIO_PB4             (1 <<  4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV     (AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5             (1 <<  5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0            (AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6             (1 <<  6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1            (AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7             (1 <<  7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER           (AT91C_PIO_PB7) //  Ethernet MAC Receive Error
+#define AT91C_PIO_PB8             (1 <<  8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC            (AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9             (1 <<  9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO           (AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ID_FIQ              ( 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS              ( 1) // System Peripheral
+#define AT91C_ID_PIOA             ( 2) // Parallel IO Controller A
+#define AT91C_ID_PIOB             ( 3) // Parallel IO Controller B
+#define AT91C_ID_SPI0             ( 4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1             ( 5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0              ( 6) // USART 0
+#define AT91C_ID_US1              ( 7) // USART 1
+#define AT91C_ID_SSC              ( 8) // Serial Synchronous Controller
+#define AT91C_ID_TWI              ( 9) // Two-Wire Interface
+#define AT91C_ID_PWMC             (10) // PWM Controller
+#define AT91C_ID_UDP              (11) // USB Device Port
+#define AT91C_ID_TC0              (12) // Timer Counter 0
+#define AT91C_ID_TC1              (13) // Timer Counter 1
+#define AT91C_ID_TC2              (14) // Timer Counter 2
+#define AT91C_ID_CAN              (15) // Control Area Network Controller
+#define AT91C_ID_EMAC             (16) // Ethernet MAC
+#define AT91C_ID_ADC              (17) // Analog-to-Digital Converter
+#define AT91C_ID_AES              (18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES             (19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved      (20) // Reserved
+#define AT91C_ID_21_Reserved      (21) // Reserved
+#define AT91C_ID_22_Reserved      (22) // Reserved
+#define AT91C_ID_23_Reserved      (23) // Reserved
+#define AT91C_ID_24_Reserved      (24) // Reserved
+#define AT91C_ID_25_Reserved      (25) // Reserved
+#define AT91C_ID_26_Reserved      (26) // Reserved
+#define AT91C_ID_27_Reserved      (27) // Reserved
+#define AT91C_ID_28_Reserved      (28) // Reserved
+#define AT91C_ID_29_Reserved      (29) // Reserved
+#define AT91C_ID_IRQ0             (30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1             (31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_BASE_SYS            (0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC            (0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU       (0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU           (0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA           (0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB           (0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR           (0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC            (0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC           (0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC           (0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC           (0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC           (0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG           (0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC             (0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1       (0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1           (0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0       (0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0           (0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1        (0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1            (0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0        (0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0            (0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC        (0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC            (0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI            (0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3       (0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2       (0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1       (0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0       (0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC           (0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP            (0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0            (0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1            (0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2            (0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB            (0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0        (0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1        (0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2        (0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3        (0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4        (0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5        (0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6        (0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7        (0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN            (0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC           (0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC        (0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC            (0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES        (0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES            (0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES       (0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES           (0xFFFA8000) // (TDES) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ISRAM	              (0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE	         (0x00010000) // Internal SRAM size in byte (64 Kbyte)
+#define AT91C_IFLASH	             (0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE	        (0x00040000) // Internal ROM size in byte (256 Kbyte)
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h
new file mode 100644
index 0000000..18e0b3b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h
@@ -0,0 +1,105 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	EXTERN pxCurrentTCB
+	EXTERN ulCriticalNesting
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Context save and restore macro definitions
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+portSAVE_CONTEXT MACRO
+
+	; Push R0 as we are going to use the register.
+	STMDB	SP!, {R0}
+
+	; Set R0 to point to the task stack pointer.
+	STMDB	SP, {SP}^
+	NOP
+	SUB		SP, SP, #4
+	LDMIA	SP!, {R0}
+
+	; Push the return address onto the stack.
+	STMDB	R0!, {LR}
+
+	; Now we have saved LR we can use it instead of R0.
+	MOV		LR, R0
+
+	; Pop R0 so we can save it onto the system mode stack.
+	LDMIA	SP!, {R0}
+
+	; Push all the system mode registers onto the task stack.
+	STMDB	LR, {R0-LR}^
+	NOP
+	SUB		LR, LR, #60
+
+	; Push the SPSR onto the task stack.
+	MRS		R0, SPSR
+	STMDB	LR!, {R0}
+
+	LDR		R0, =ulCriticalNesting
+	LDR		R0, [R0]
+	STMDB	LR!, {R0}
+
+	; Store the new top of stack for the task.
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	STR		LR, [R0]
+
+	ENDM
+
+
+portRESTORE_CONTEXT MACRO
+
+	; Set the LR to the task stack.
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	LDR		LR, [R0]
+
+	; The critical nesting depth is the first item on the stack.
+	; Load it into the ulCriticalNesting variable.
+	LDR		R0, =ulCriticalNesting
+	LDMFD	LR!, {R1}
+	STR		R1, [R0]
+
+	; Get the SPSR from the stack.
+	LDMFD	LR!, {R0}
+	MSR		SPSR_cxsf, R0
+
+	; Restore all system mode registers for the task.
+	LDMFD	LR, {R0-R14}^
+	NOP
+
+	; Restore the return address.
+	LDR		LR, [LR, #+60]
+
+	; And return - correcting the offset in the LR to obtain the
+	; correct address.
+	SUBS	PC, LR, #4
+
+	ENDM
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h
new file mode 100644
index 0000000..9d012c4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h
@@ -0,0 +1,3265 @@
+//*----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name           : lib_AT91SAM7S64.h
+//* Object              : AT91SAM7S64 inlined functions
+//* Generated           : AT91 SW Application Group  07/16/2004 (07:43:09)
+//*
+//* CVS Reference       : /lib_MC_SAM.h/1.3/Thu Mar 25 15:19:14 2004//
+//* CVS Reference       : /lib_pdc_1363d.h/1.2/Wed Feb 19 09:25:22 2003//
+//* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
+//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
+//* CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 13:23:52 2003//
+//* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+//* CVS Reference       : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//
+//* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 08:12:38 2003//
+//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
+//* CVS Reference       : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003//
+//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
+//* CVS Reference       : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003//
+//* CVS Reference       : /lib_aic.h/1.3/Fri Jul 12 07:46:12 2002//
+//*----------------------------------------------------------------------------
+
+#ifndef lib_AT91SAM7S64_H
+#define lib_AT91SAM7S64_H
+
+/* *****************************************************************************
+                SOFTWARE API FOR MC
+   ***************************************************************************** */
+
+#define AT91C_MC_CORRECT_KEY  ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_Remap
+//* \brief Make Remap
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_Remap (void)     //  
+{
+    AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
+    
+    pMC->MC_RCR = AT91C_MC_RCB;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_CfgModeReg
+//* \brief Configure the EFC Mode Register of the MC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_CfgModeReg (
+	AT91PS_MC pMC, // pointer to a MC controller
+	unsigned int mode)        // mode register 
+{
+	// Write to the FMR register
+	pMC->MC_FMR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_GetModeReg
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetModeReg(
+	AT91PS_MC pMC) // pointer to a MC controller
+{
+	return pMC->MC_FMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_ComputeFMCN
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_ComputeFMCN(
+	int master_clock) // master clock in Hz
+{
+	return (master_clock/1000000 +2);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_PerformCmd
+//* \brief Perform EFC Command
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_PerformCmd (
+	AT91PS_MC pMC, // pointer to a MC controller
+    unsigned int transfer_cmd)
+{
+	pMC->MC_FCR = transfer_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_GetStatus
+//* \brief Return MC EFC Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetStatus(
+	AT91PS_MC pMC) // pointer to a MC controller
+{
+	return pMC->MC_FSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_IsInterruptMasked
+//* \brief Test if EFC MC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
+        AT91PS_MC pMC,   // \arg  pointer to a MC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_IsInterruptSet
+//* \brief Test if EFC MC Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptSet(
+        AT91PS_MC pMC,   // \arg  pointer to a MC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_MC_EFC_GetStatus(pMC) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PDC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetNextRx
+//* \brief Set the next receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextRx (
+	AT91PS_PDC pPDC,     // \arg pointer to a PDC controller
+	char *address,       // \arg address to the next bloc to be received
+	unsigned int bytes)  // \arg number of bytes to be received
+{
+	pPDC->PDC_RNPR = (unsigned int) address;
+	pPDC->PDC_RNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetNextTx
+//* \brief Set the next transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextTx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be transmitted
+	unsigned int bytes)    // \arg number of bytes to be transmitted
+{
+	pPDC->PDC_TNPR = (unsigned int) address;
+	pPDC->PDC_TNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetRx
+//* \brief Set the receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetRx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be received
+	unsigned int bytes)    // \arg number of bytes to be received
+{
+	pPDC->PDC_RPR = (unsigned int) address;
+	pPDC->PDC_RCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetTx
+//* \brief Set the transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetTx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be transmitted
+	unsigned int bytes)    // \arg number of bytes to be transmitted
+{
+	pPDC->PDC_TPR = (unsigned int) address;
+	pPDC->PDC_TCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_EnableTx
+//* \brief Enable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableTx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_EnableRx
+//* \brief Enable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableRx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_DisableTx
+//* \brief Disable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableTx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_DisableRx
+//* \brief Disable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableRx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsTxEmpty
+//* \brief Test if the current transfer descriptor has been sent
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_TCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsNextTxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_TNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsRxEmpty
+//* \brief Test if the current transfer descriptor has been filled
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_RCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsNextRxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_RNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_Open
+//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Open (
+	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
+{
+    //* Disable the RX and TX PDC transfer requests
+	AT91F_PDC_DisableRx(pPDC);
+	AT91F_PDC_DisableTx(pPDC);
+
+	//* Reset all Counter register Next buffer first
+	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+    //* Enable the RX and TX PDC transfer requests
+	AT91F_PDC_EnableRx(pPDC);
+	AT91F_PDC_EnableTx(pPDC);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_Close
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Close (
+	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
+{
+    //* Disable the RX and TX PDC transfer requests
+	AT91F_PDC_DisableRx(pPDC);
+	AT91F_PDC_DisableTx(pPDC);
+
+	//* Reset all Counter register Next buffer first
+	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SendFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_SendFrame(
+	AT91PS_PDC pPDC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	if (AT91F_PDC_IsTxEmpty(pPDC)) {
+		//* Buffer and next buffer can be initialized
+		AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
+		AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
+		return 2;
+	}
+	else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
+		//* Only one buffer can be initialized
+		AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
+		return 1;
+	}
+	else {
+		//* All buffer are in use...
+		return 0;
+	}
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_ReceiveFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_ReceiveFrame (
+	AT91PS_PDC pPDC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	if (AT91F_PDC_IsRxEmpty(pPDC)) {
+		//* Buffer and next buffer can be initialized
+		AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
+		AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
+		return 2;
+	}
+	else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
+		//* Only one buffer can be initialized
+		AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
+		return 1;
+	}
+	else {
+		//* All buffer are in use...
+		return 0;
+	}
+}
+/* *****************************************************************************
+                SOFTWARE API FOR DBGU
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_InterruptEnable
+//* \brief Enable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptEnable(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  dbgu interrupt to be enabled
+{
+        pDbgu->DBGU_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_InterruptDisable
+//* \brief Disable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptDisable(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  dbgu interrupt to be disabled
+{
+        pDbgu->DBGU_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_GetInterruptMaskStatus
+//* \brief Return DBGU Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
+        AT91PS_DBGU pDbgu) // \arg  pointer to a DBGU controller
+{
+        return pDbgu->DBGU_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_IsInterruptMasked
+//* \brief Test if DBGU Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_DBGU_IsInterruptMasked(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR SSC
+   ***************************************************************************** */
+//* Define the standard I2S mode configuration
+
+//* Configuration to set in the SSC Transmit Clock Mode Register
+//* Parameters :  nb_bit_by_slot : 8, 16 or 32 bits
+//* 			  nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+									   AT91C_SSC_CKS_DIV   +\
+                            		   AT91C_SSC_CKO_CONTINOUS      +\
+                            		   AT91C_SSC_CKG_NONE    +\
+                                       AT91C_SSC_START_FALL_RF +\
+                           			   AT91C_SSC_STTOUT  +\
+                            		   ((1<<16) & AT91C_SSC_STTDLY) +\
+                            		   ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
+
+
+//* Configuration to set in the SSC Transmit Frame Mode Register
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
+//* 			 nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+									(nb_bit_by_slot-1)  +\
+                            		AT91C_SSC_MSBF   +\
+                            		(((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB)  +\
+                            		(((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
+                            		AT91C_SSC_FSOS_NEGATIVE)
+
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_SetBaudrate (
+        AT91PS_SSC pSSC,        // \arg pointer to a SSC controller
+        unsigned int mainClock, // \arg peripheral clock
+        unsigned int speed)     // \arg SSC baudrate
+{
+        unsigned int baud_value;
+        //* Define the baud rate divisor register
+        if (speed == 0)
+           baud_value = 0;
+        else
+        {
+           baud_value = (unsigned int) (mainClock * 10)/(2*speed);
+           if ((baud_value % 10) >= 5)
+                  baud_value = (baud_value / 10) + 1;
+           else
+                  baud_value /= 10;
+        }
+
+        pSSC->SSC_CMR = baud_value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_Configure
+//* \brief Configure SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_Configure (
+             AT91PS_SSC pSSC,          // \arg pointer to a SSC controller
+             unsigned int syst_clock,  // \arg System Clock Frequency
+             unsigned int baud_rate,   // \arg Expected Baud Rate Frequency
+             unsigned int clock_rx,    // \arg Receiver Clock Parameters
+             unsigned int mode_rx,     // \arg mode Register to be programmed
+             unsigned int clock_tx,    // \arg Transmitter Clock Parameters
+             unsigned int mode_tx)     // \arg mode Register to be programmed
+{
+    //* Disable interrupts
+	pSSC->SSC_IDR = (unsigned int) -1;
+
+    //* Reset receiver and transmitter
+	pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
+
+    //* Define the Clock Mode Register
+	AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
+
+     //* Write the Receive Clock Mode Register
+	pSSC->SSC_RCMR =  clock_rx;
+
+     //* Write the Transmit Clock Mode Register
+	pSSC->SSC_TCMR =  clock_tx;
+
+     //* Write the Receive Frame Mode Register
+	pSSC->SSC_RFMR =  mode_rx;
+
+     //* Write the Transmit Frame Mode Register
+	pSSC->SSC_TFMR =  mode_tx;
+
+    //* Clear Transmit and Receive Counters
+	AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
+
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableRx
+//* \brief Enable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableRx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Enable receiver
+    pSSC->SSC_CR = AT91C_SSC_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableRx
+//* \brief Disable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableRx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Disable receiver
+    pSSC->SSC_CR = AT91C_SSC_RXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableTx
+//* \brief Enable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableTx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Enable  transmitter
+    pSSC->SSC_CR = AT91C_SSC_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableTx
+//* \brief Disable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableTx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Disable  transmitter
+    pSSC->SSC_CR = AT91C_SSC_TXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableIt
+//* \brief Enable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableIt (
+	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pSSC->SSC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableIt
+//* \brief Disable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableIt (
+	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pSSC->SSC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_ReceiveFrame (
+	AT91PS_SSC pSSC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pSSC->SSC_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_SendFrame(
+	AT91PS_SSC pSSC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pSSC->SSC_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_GetInterruptMaskStatus
+//* \brief Return SSC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
+        AT91PS_SSC pSsc) // \arg  pointer to a SSC controller
+{
+        return pSsc->SSC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_IsInterruptMasked
+//* \brief Test if SSC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_SSC_IsInterruptMasked(
+        AT91PS_SSC pSsc,   // \arg  pointer to a SSC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR SPI
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Open
+//* \brief Open a SPI Port
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_Open (
+        const unsigned int null)  // \arg
+{
+        /* NOT DEFINED AT THIS MOMENT */
+        return ( 0 );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgCs
+//* \brief Configure SPI chip select register
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgCs (
+	AT91PS_SPI pSPI,     // pointer to a SPI controller
+	int cs,     // SPI cs number (0 to 3)
+ 	int val)   //  chip select register
+{
+	//* Write to the CSR register
+	*(pSPI->SPI_CSR + cs) = val;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_EnableIt
+//* \brief Enable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_EnableIt (
+	AT91PS_SPI pSPI,     // pointer to a SPI controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pSPI->SPI_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_DisableIt
+//* \brief Disable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_DisableIt (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pSPI->SPI_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Reset
+//* \brief Reset the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Reset (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SWRST;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Enable
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Enable (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SPIEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Disable
+//* \brief Disable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Disable (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SPIDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgMode
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgMode (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	int mode)        // mode register 
+{
+	//* Write to the MR register
+	pSPI->SPI_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgPCS
+//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgPCS (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	char PCS_Device) // PCS of the Device
+{	
+ 	//* Write to the MR register
+	pSPI->SPI_MR &= 0xFFF0FFFF;
+	pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_ReceiveFrame (
+	AT91PS_SPI pSPI,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pSPI->SPI_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_SendFrame(
+	AT91PS_SPI pSPI,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pSPI->SPI_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Close
+//* \brief Close SPI: disable IT disable transfert, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Close (
+	AT91PS_SPI pSPI)     // \arg pointer to a SPI controller
+{
+    //* Reset all the Chip Select register
+    pSPI->SPI_CSR[0] = 0 ;
+    pSPI->SPI_CSR[1] = 0 ;
+    pSPI->SPI_CSR[2] = 0 ;
+    pSPI->SPI_CSR[3] = 0 ;
+
+    //* Reset the SPI mode
+    pSPI->SPI_MR = 0  ;
+
+    //* Disable all interrupts
+    pSPI->SPI_IDR = 0xFFFFFFFF ;
+
+    //* Abort the Peripheral Data Transfers
+    AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
+
+    //* Disable receiver and transmitter and stop any activity immediately
+    pSPI->SPI_CR = AT91C_SPI_SPIDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_PutChar (
+	AT91PS_SPI pSPI,
+	unsigned int character,
+             unsigned int cs_number )
+{
+    unsigned int value_for_cs;
+    value_for_cs = (~(1 << cs_number)) & 0xF;  //Place a zero among a 4 ONEs number
+    pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_GetChar (
+	const AT91PS_SPI pSPI)
+{
+    return((pSPI->SPI_RDR) & 0xFFFF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_GetInterruptMaskStatus
+//* \brief Return SPI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
+        AT91PS_SPI pSpi) // \arg  pointer to a SPI controller
+{
+        return pSpi->SPI_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_IsInterruptMasked
+//* \brief Test if SPI Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_IsInterruptMasked(
+        AT91PS_SPI pSpi,   // \arg  pointer to a SPI controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PWMC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_GetStatus
+//* \brief Return PWM Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
+	AT91PS_PWMC pPWM) // pointer to a PWM controller
+{
+	return pPWM->PWMC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_InterruptEnable
+//* \brief Enable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptEnable(
+        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  PWM interrupt to be enabled
+{
+        pPwm->PWMC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_InterruptDisable
+//* \brief Disable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptDisable(
+        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  PWM interrupt to be disabled
+{
+        pPwm->PWMC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_GetInterruptMaskStatus
+//* \brief Return PWM Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
+        AT91PS_PWMC pPwm) // \arg  pointer to a PWM controller
+{
+        return pPwm->PWMC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_IsInterruptMasked
+//* \brief Test if PWM Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsInterruptMasked(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_IsStatusSet
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsStatusSet(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PWMC_GetStatus(pPWM) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_CfgChannel
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int channelId, // \arg PWM channel ID
+        unsigned int mode, // \arg  PWM mode
+        unsigned int period, // \arg PWM period
+        unsigned int duty) // \arg PWM duty cycle
+{
+	pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
+	pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
+	pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_StartChannel
+//* \brief Enable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StartChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_ENA = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_StopChannel
+//* \brief Disable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StopChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_DIS = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_UpdateChannel
+//* \brief Update Period or Duty Cycle
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_UpdateChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int channelId, // \arg PWM channel ID
+        unsigned int update) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR TC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_InterruptEnable
+//* \brief Enable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptEnable(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  TC interrupt to be enabled
+{
+        pTc->TC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_InterruptDisable
+//* \brief Disable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptDisable(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  TC interrupt to be disabled
+{
+        pTc->TC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_GetInterruptMaskStatus
+//* \brief Return TC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
+        AT91PS_TC pTc) // \arg  pointer to a TC controller
+{
+        return pTc->TC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_IsInterruptMasked
+//* \brief Test if TC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_TC_IsInterruptMasked(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PMC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgSysClkEnableReg
+//* \brief Configure the System Clock Enable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkEnableReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	//* Write to the SCER register
+	pPMC->PMC_SCER = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgSysClkDisableReg
+//* \brief Configure the System Clock Disable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkDisableReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	//* Write to the SCDR register
+	pPMC->PMC_SCDR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetSysClkStatusReg
+//* \brief Return the System Clock Status Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
+	AT91PS_PMC pPMC // pointer to a CAN controller
+	)
+{
+	return pPMC->PMC_SCSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnablePeriphClock
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePeriphClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int periphIds)  // \arg IDs of peripherals to enable
+{
+	pPMC->PMC_PCER = periphIds;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisablePeriphClock
+//* \brief Disable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePeriphClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int periphIds)  // \arg IDs of peripherals to enable
+{
+	pPMC->PMC_PCDR = periphIds;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetPeriphClock
+//* \brief Get peripheral clock status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetPeriphClock (
+	AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+	return pPMC->PMC_PCSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_CfgMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscillatorReg (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int mode)
+{
+	pCKGR->CKGR_MOR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	return pCKGR->CKGR_MOR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_EnableMainOscillator
+//* \brief Enable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_EnableMainOscillator(
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_DisableMainOscillator
+//* \brief Disable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_DisableMainOscillator (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_CfgMainOscStartUpTime
+//* \brief Cfg MOR Register according to the main osc startup time
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscStartUpTime (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int startup_time,  // \arg main osc startup time in microsecond (us)
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
+	pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainClockFreqReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	return pCKGR->CKGR_MCFR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainClock
+//* \brief Return Main clock in Hz
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClock (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	return ((pCKGR->CKGR_MCFR  & AT91C_CKGR_MAINF) * slowClock) >> 4;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgMCKReg
+//* \brief Cfg Master Clock Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgMCKReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	pPMC->PMC_MCKR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetMCKReg
+//* \brief Return Master Clock Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMCKReg(
+	AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+	return pPMC->PMC_MCKR;
+}
+
+//*------------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetMasterClock
+//* \brief Return master clock in Hz which correponds to processor clock for ARM7
+//*------------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMasterClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	unsigned int reg = pPMC->PMC_MCKR;
+	unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
+	unsigned int pllDivider, pllMultiplier;
+
+	switch (reg & AT91C_PMC_CSS) {
+		case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
+			return slowClock / prescaler;
+		case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
+			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
+		case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
+			reg = pCKGR->CKGR_PLLR;
+			pllDivider    = (reg  & AT91C_CKGR_DIV);
+			pllMultiplier = ((reg  & AT91C_CKGR_MUL) >> 16) + 1;
+			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
+	}
+	return 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePCK (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int pck,  // \arg Peripheral clock identifier 0 .. 7
+	unsigned int mode)
+{
+	pPMC->PMC_PCKR[pck] = mode;
+	pPMC->PMC_SCER = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePCK (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int pck)  // \arg Peripheral clock identifier 0 .. 7
+{
+	pPMC->PMC_SCDR = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnableIt
+//* \brief Enable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnableIt (
+	AT91PS_PMC pPMC,     // pointer to a PMC controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pPMC->PMC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisableIt
+//* \brief Disable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisableIt (
+	AT91PS_PMC pPMC, // pointer to a PMC controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pPMC->PMC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetStatus
+//* \brief Return PMC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
+	AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+	return pPMC->PMC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetInterruptMaskStatus
+//* \brief Return PMC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
+	AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+	return pPMC->PMC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_IsInterruptMasked
+//* \brief Test if PMC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsInterruptMasked(
+        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_IsStatusSet
+//* \brief Test if PMC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsStatusSet(
+        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PMC_GetStatus(pPMC) & flag);
+}/* *****************************************************************************
+                SOFTWARE API FOR ADC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_EnableIt
+//* \brief Enable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableIt (
+	AT91PS_ADC pADC,     // pointer to a ADC controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pADC->ADC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_DisableIt
+//* \brief Disable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableIt (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pADC->ADC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetStatus
+//* \brief Return ADC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
+	AT91PS_ADC pADC) // pointer to a ADC controller
+{
+	return pADC->ADC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetInterruptMaskStatus
+//* \brief Return ADC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
+	AT91PS_ADC pADC) // pointer to a ADC controller
+{
+	return pADC->ADC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_IsInterruptMasked
+//* \brief Test if ADC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsInterruptMasked(
+        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_IsStatusSet
+//* \brief Test if ADC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsStatusSet(
+        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_ADC_GetStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgModeReg
+//* \brief Configure the Mode Register of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgModeReg (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int mode)        // mode register 
+{
+	//* Write to the MR register
+	pADC->ADC_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetModeReg
+//* \brief Return the Mode Register of the ADC controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetModeReg (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgTimings
+//* \brief Configure the different necessary timings of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgTimings (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int mck_clock, // in MHz 
+	unsigned int adc_clock, // in MHz 
+	unsigned int startup_time, // in us 
+	unsigned int sample_and_hold_time)	// in ns  
+{
+	unsigned int prescal,startup,shtim;
+	
+	prescal = mck_clock/(2*adc_clock) - 1;
+	startup = adc_clock*startup_time/8 - 1;
+	shtim = adc_clock*sample_and_hold_time/1000 - 1;
+	
+	//* Write to the MR register
+	pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_EnableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableChannel (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int channel)        // mode register 
+{
+	//* Write to the CHER register
+	pADC->ADC_CHER = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_DisableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableChannel (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int channel)        // mode register 
+{
+	//* Write to the CHDR register
+	pADC->ADC_CHDR = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetChannelStatus
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetChannelStatus (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CHSR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_StartConversion
+//* \brief Software request for a analog to digital conversion 
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_StartConversion (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	pADC->ADC_CR = AT91C_ADC_START;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_SoftReset
+//* \brief Software reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_SoftReset (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	pADC->ADC_CR = AT91C_ADC_SWRST;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetLastConvertedData
+//* \brief Return the Last Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetLastConvertedData (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_LCDR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH0
+//* \brief Return the Channel 0 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR0;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH1
+//* \brief Return the Channel 1 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR1;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH2
+//* \brief Return the Channel 2 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR2;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH3
+//* \brief Return the Channel 3 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR3;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH4
+//* \brief Return the Channel 4 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR4;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH5
+//* \brief Return the Channel 5 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR5;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH6
+//* \brief Return the Channel 6 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR6;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH7
+//* \brief Return the Channel 7 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR7;	
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PIO
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgPeriph
+//* \brief Enable pins to be drived by peripheral
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPeriph(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int periphAEnable,  // \arg PERIPH A to enable
+	unsigned int periphBEnable)  // \arg PERIPH B to enable
+
+{
+	pPio->PIO_ASR = periphAEnable;
+	pPio->PIO_BSR = periphBEnable;
+	pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgOutput
+//* \brief Enable PIO in output mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOutput(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int pioEnable)      // \arg PIO to be enabled
+{
+	pPio->PIO_PER = pioEnable; // Set in PIO mode
+	pPio->PIO_OER = pioEnable; // Configure in Output
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgInput
+//* \brief Enable PIO in input mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInput(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int inputEnable)      // \arg PIO to be enabled
+{
+	// Disable output
+	pPio->PIO_ODR  = inputEnable;
+	pPio->PIO_PER  = inputEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgOpendrain
+//* \brief Configure PIO in open drain
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOpendrain(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int multiDrvEnable) // \arg pio to be configured in open drain
+{
+	// Configure the multi-drive option
+	pPio->PIO_MDDR = ~multiDrvEnable;
+	pPio->PIO_MDER = multiDrvEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgPullup
+//* \brief Enable pullup on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPullup(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int pullupEnable)   // \arg enable pullup on PIO
+{
+		// Connect or not Pullup
+	pPio->PIO_PPUDR = ~pullupEnable;
+	pPio->PIO_PPUER = pullupEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgDirectDrive
+//* \brief Enable direct drive on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgDirectDrive(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int directDrive)    // \arg PIO to be configured with direct drive
+
+{
+	// Configure the Direct Drive
+	pPio->PIO_OWDR  = ~directDrive;
+	pPio->PIO_OWER  = directDrive;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgInputFilter
+//* \brief Enable input filter on input PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInputFilter(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int inputFilter)    // \arg PIO to be configured with input filter
+
+{
+	// Configure the Direct Drive
+	pPio->PIO_IFDR  = ~inputFilter;
+	pPio->PIO_IFER  = inputFilter;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInput
+//* \brief Return PIO input value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
+	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+	return pPio->PIO_PDSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInputSet
+//* \brief Test if PIO is input flag is active
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputSet(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PIO_GetInput(pPio) & flag);
+}
+
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_SetOutput
+//* \brief Set to 1 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_SetOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be set
+{
+	pPio->PIO_SODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_ClearOutput
+//* \brief Set to 0 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ClearOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be cleared
+{
+	pPio->PIO_CODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_ForceOutput
+//* \brief Force output when Direct drive option is enabled
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ForceOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be forced
+{
+	pPio->PIO_ODSR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Enable
+//* \brief Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Enable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be enabled 
+{
+        pPio->PIO_PER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Disable
+//* \brief Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Disable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be disabled 
+{
+        pPio->PIO_PDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetStatus
+//* \brief Return PIO Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_PSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsSet
+//* \brief Test if PIO is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputEnable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output to be enabled
+{
+        pPio->PIO_OER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputDisable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output to be disabled
+{
+        pPio->PIO_ODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputStatus
+//* \brief Return PIO Output Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_OSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOuputSet
+//* \brief Test if PIO Output is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InputFilterEnable
+//* \brief Input Filter Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio input filter to be enabled
+{
+        pPio->PIO_IFER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InputFilterDisable
+//* \brief Input Filter Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio input filter to be disabled
+{
+        pPio->PIO_IFDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInputFilterStatus
+//* \brief Return PIO Input Filter Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_IFSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInputFilterSet
+//* \brief Test if PIO Input filter is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputFilterSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputDataStatus
+//* \brief Return PIO Output Data Status 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status 
+	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ODSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InterruptEnable
+//* \brief Enable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio interrupt to be enabled
+{
+        pPio->PIO_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InterruptDisable
+//* \brief Disable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio interrupt to be disabled
+{
+        pPio->PIO_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInterruptMaskStatus
+//* \brief Return PIO Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInterruptStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInterruptMasked
+//* \brief Test if PIO Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptMasked(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInterruptSet
+//* \brief Test if PIO Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_MultiDriverEnable
+//* \brief Multi Driver Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be enabled
+{
+        pPio->PIO_MDER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_MultiDriverDisable
+//* \brief Multi Driver Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be disabled
+{
+        pPio->PIO_MDDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetMultiDriverStatus
+//* \brief Return PIO Multi Driver Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_MDSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsMultiDriverSet
+//* \brief Test if PIO MultiDriver is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsMultiDriverSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_A_RegisterSelection
+//* \brief PIO A Register Selection 
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_A_RegisterSelection(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio A register selection
+{
+        pPio->PIO_ASR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_B_RegisterSelection
+//* \brief PIO B Register Selection 
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_B_RegisterSelection(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio B register selection 
+{
+        pPio->PIO_BSR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Get_AB_RegisterStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ABSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsAB_RegisterSet
+//* \brief Test if PIO AB Register is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsAB_RegisterSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputWriteEnable
+//* \brief Output Write Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output write to be enabled
+{
+        pPio->PIO_OWER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputWriteDisable
+//* \brief Output Write Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output write to be disabled
+{
+        pPio->PIO_OWDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputWriteStatus
+//* \brief Return PIO Output Write Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_OWSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOutputWriteSet
+//* \brief Test if PIO OutputWrite is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputWriteSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetCfgPullup
+//* \brief Return PIO Configuration Pullup
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup 
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_PPUSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOutputDataStatusSet
+//* \brief Test if PIO Output Data Status is Set 
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputDataStatusSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsCfgPullupStatusSet
+//* \brief Test if PIO Configuration Pullup Status is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsCfgPullupStatusSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR TWI
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_EnableIt
+//* \brief Enable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_EnableIt (
+	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pTWI->TWI_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_DisableIt
+//* \brief Disable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_DisableIt (
+	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pTWI->TWI_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_Configure
+//* \brief Configure TWI in master mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI )          // \arg pointer to a TWI controller
+{
+    //* Disable interrupts
+	pTWI->TWI_IDR = (unsigned int) -1;
+
+    //* Reset peripheral
+	pTWI->TWI_CR = AT91C_TWI_SWRST;
+
+	//* Set Master mode
+	pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS;
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_GetInterruptMaskStatus
+//* \brief Return TWI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
+        AT91PS_TWI pTwi) // \arg  pointer to a TWI controller
+{
+        return pTwi->TWI_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_IsInterruptMasked
+//* \brief Test if TWI Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_TWI_IsInterruptMasked(
+        AT91PS_TWI pTwi,   // \arg  pointer to a TWI controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR USART
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Baudrate
+//* \brief Calculate the baudrate
+//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
+                        AT91C_US_NBSTOP_1_BIT + \
+                        AT91C_US_PAR_NONE + \
+                        AT91C_US_CHRL_8_BITS + \
+                        AT91C_US_CLKS_CLOCK )
+
+//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
+                            AT91C_US_NBSTOP_1_BIT + \
+                            AT91C_US_PAR_NONE + \
+                            AT91C_US_CHRL_8_BITS + \
+                            AT91C_US_CLKS_EXT )
+
+//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
+                       AT91C_US_USMODE_NORMAL + \
+                       AT91C_US_NBSTOP_1_BIT + \
+                       AT91C_US_PAR_NONE + \
+                       AT91C_US_CHRL_8_BITS + \
+                       AT91C_US_CLKS_CLOCK )
+
+//* SCK used Label
+#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
+
+//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
+#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
+					   		 AT91C_US_CLKS_CLOCK +\
+                       		 AT91C_US_NBSTOP_1_BIT + \
+                       		 AT91C_US_PAR_EVEN + \
+                       		 AT91C_US_CHRL_8_BITS + \
+                       		 AT91C_US_CKLO +\
+                       		 AT91C_US_OVER)
+
+//* Standard IRDA mode
+#define AT91C_US_ASYNC_IRDA_MODE (  AT91C_US_USMODE_IRDA + \
+                            AT91C_US_NBSTOP_1_BIT + \
+                            AT91C_US_PAR_NONE + \
+                            AT91C_US_CHRL_8_BITS + \
+                            AT91C_US_CLKS_CLOCK )
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Baudrate
+//* \brief Caluculate baud_value according to the main clock and the baud rate
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Baudrate (
+	const unsigned int main_clock, // \arg peripheral clock
+	const unsigned int baud_rate)  // \arg UART baudrate
+{
+	unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
+	if ((baud_value % 10) >= 5)
+		baud_value = (baud_value / 10) + 1;
+	else
+		baud_value /= 10;
+	return baud_value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetBaudrate (
+	AT91PS_USART pUSART,    // \arg pointer to a USART controller
+	unsigned int mainClock, // \arg peripheral clock
+	unsigned int speed)     // \arg UART baudrate
+{
+	//* Define the baud rate divisor register
+	pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetTimeguard
+//* \brief Set USART timeguard
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetTimeguard (
+	AT91PS_USART pUSART,    // \arg pointer to a USART controller
+	unsigned int timeguard) // \arg timeguard value
+{
+	//* Write the Timeguard Register
+	pUSART->US_TTGR = timeguard ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableIt
+//* \brief Enable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableIt (
+	AT91PS_USART pUSART, // \arg pointer to a USART controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pUSART->US_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableIt
+//* \brief Disable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableIt (
+	AT91PS_USART pUSART, // \arg pointer to a USART controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IER register
+	pUSART->US_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Configure
+//* \brief Configure USART
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Configure (
+	AT91PS_USART pUSART,     // \arg pointer to a USART controller
+	unsigned int mainClock,  // \arg peripheral clock
+	unsigned int mode ,      // \arg mode Register to be programmed
+	unsigned int baudRate ,  // \arg baudrate to be programmed
+	unsigned int timeguard ) // \arg timeguard to be programmed
+{
+    //* Disable interrupts
+    pUSART->US_IDR = (unsigned int) -1;
+
+    //* Reset receiver and transmitter
+    pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
+
+	//* Define the baud rate divisor register
+	AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
+
+	//* Write the Timeguard Register
+	AT91F_US_SetTimeguard(pUSART, timeguard);
+
+    //* Clear Transmit and Receive Counters
+    AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
+
+    //* Define the USART mode
+    pUSART->US_MR = mode  ;
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableRx
+//* \brief Enable receiving characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Enable receiver
+    pUSART->US_CR = AT91C_US_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableTx
+//* \brief Enable sending characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Enable  transmitter
+    pUSART->US_CR = AT91C_US_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ResetRx
+//* \brief Reset Receiver and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+	//* Reset receiver
+	pUSART->US_CR = AT91C_US_RSTRX;
+    //* Re-Enable receiver
+    pUSART->US_CR = AT91C_US_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ResetTx
+//* \brief Reset Transmitter and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+	//* Reset transmitter
+	pUSART->US_CR = AT91C_US_RSTTX;
+    //* Enable transmitter
+    pUSART->US_CR = AT91C_US_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableRx
+//* \brief Disable Receiver
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Disable receiver
+    pUSART->US_CR = AT91C_US_RXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableTx
+//* \brief Disable Transmitter
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Disable transmitter
+    pUSART->US_CR = AT91C_US_TXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Close
+//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Close (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Reset the baud rate divisor register
+    pUSART->US_BRGR = 0 ;
+
+    //* Reset the USART mode
+    pUSART->US_MR = 0  ;
+
+    //* Reset the Timeguard Register
+    pUSART->US_TTGR = 0;
+
+    //* Disable all interrupts
+    pUSART->US_IDR = 0xFFFFFFFF ;
+
+    //* Abort the Peripheral Data Transfers
+    AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
+
+    //* Disable receiver and transmitter and stop any activity immediately
+    pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_TxReady
+//* \brief Return 1 if a character can be written in US_THR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_TxReady (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR & AT91C_US_TXRDY);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_RxReady
+//* \brief Return 1 if a character can be read in US_RHR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_RxReady (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR & AT91C_US_RXRDY);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Error
+//* \brief Return the error flag
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Error (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR &
+    	(AT91C_US_OVRE |  // Overrun error
+    	 AT91C_US_FRAME | // Framing error
+    	 AT91C_US_PARE));  // Parity error
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_PutChar (
+	AT91PS_USART pUSART,
+	int character )
+{
+    pUSART->US_THR = (character & 0x1FF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_US_GetChar (
+	const AT91PS_USART pUSART)
+{
+    return((pUSART->US_RHR) & 0x1FF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_SendFrame(
+	AT91PS_USART pUSART,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pUSART->US_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_ReceiveFrame (
+	AT91PS_USART pUSART,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pUSART->US_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetIrdaFilter
+//* \brief Set the value of IrDa filter tregister
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetIrdaFilter (
+	AT91PS_USART pUSART,
+	unsigned char value
+)
+{
+	pUSART->US_IF = value;
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR UDP
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EnableIt
+//* \brief Enable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableIt (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pUDP->UDP_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_DisableIt
+//* \brief Disable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableIt (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pUDP->UDP_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_SetAddress
+//* \brief Set UDP functional address
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetAddress (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char address)   // \arg new UDP address
+{
+	pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EnableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableEp (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg endpoints to be enabled
+{
+	pUDP->UDP_GLBSTATE  |= flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_DisableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableEp (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg endpoints to be enabled
+{
+	pUDP->UDP_GLBSTATE  &= ~(flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_SetState
+//* \brief Set UDP Device state
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetState (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg new UDP address
+{
+	pUDP->UDP_GLBSTATE  &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
+	pUDP->UDP_GLBSTATE  |= flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_GetState
+//* \brief return UDP Device state
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
+	AT91PS_UDP pUDP)     // \arg pointer to a UDP controller
+{
+	return (pUDP->UDP_GLBSTATE  & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_ResetEp
+//* \brief Reset UDP endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_ResetEp ( // \return the UDP device state
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg Endpoints to be reset
+{
+	pUDP->UDP_RSTEP = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpStall
+//* \brief Endpoint will STALL requests
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpStall(
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char endpoint)   // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpWrite
+//* \brief Write value in the DPR
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpWrite(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned char value)     // \arg value to be written in the DPR
+{
+	pUDP->UDP_FDR[endpoint] = value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpRead
+//* \brief Return value from the DPR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpRead(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	return pUDP->UDP_FDR[endpoint];
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpEndOfWr
+//* \brief Notify the UDP that values in DPR are ready to be sent
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpEndOfWr(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpClear
+//* \brief Clear flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpClear(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned int flag)       // \arg flag to be cleared
+{
+	pUDP->UDP_CSR[endpoint] &= ~(flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpSet
+//* \brief Set flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpSet(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned int flag)       // \arg flag to be cleared
+{
+	pUDP->UDP_CSR[endpoint] |= flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpStatus
+//* \brief Return the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpStatus(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	return pUDP->UDP_CSR[endpoint];
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_GetInterruptMaskStatus
+//* \brief Return UDP Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status
+        AT91PS_UDP pUdp) // \arg  pointer to a UDP controller
+{
+        return pUdp->UDP_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_IsInterruptMasked
+//* \brief Test if UDP Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_UDP_IsInterruptMasked(
+        AT91PS_UDP pUdp,   // \arg  pointer to a UDP controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR AIC
+   ***************************************************************************** */
+#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_ConfigureIt
+//* \brief Interrupt Handler Initialization
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_ConfigureIt (
+	AT91PS_AIC pAic,  // \arg pointer to the AIC registers
+	unsigned int irq_id,     // \arg interrupt number to initialize
+	unsigned int priority,   // \arg priority to give to the interrupt
+	unsigned int src_type,   // \arg activation and sense of activation
+	void (*newHandler) (void) ) // \arg address of the interrupt handler
+{
+	unsigned int oldHandler;
+    unsigned int mask ;
+
+    oldHandler = pAic->AIC_SVR[irq_id];
+
+    mask = 0x1 << irq_id ;
+    //* Disable the interrupt on the interrupt controller
+    pAic->AIC_IDCR = mask ;
+    //* Save the interrupt handler routine pointer and the interrupt priority
+    pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
+    //* Store the Source Mode Register
+    pAic->AIC_SMR[irq_id] = src_type | priority  ;
+    //* Clear the interrupt on the interrupt controller
+    pAic->AIC_ICCR = mask ;
+
+	return oldHandler;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_EnableIt
+//* \brief Enable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_EnableIt (
+	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
+	unsigned int irq_id ) // \arg interrupt number to initialize
+{
+    //* Enable the interrupt on the interrupt controller
+    pAic->AIC_IECR = 0x1 << irq_id ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_DisableIt
+//* \brief Disable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_DisableIt (
+	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
+	unsigned int irq_id ) // \arg interrupt number to initialize
+{
+    unsigned int mask = 0x1 << irq_id;
+    //* Disable the interrupt on the interrupt controller
+    pAic->AIC_IDCR = mask ;
+    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+    pAic->AIC_ICCR = mask ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_ClearIt
+//* \brief Clear corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_ClearIt (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg interrupt number to initialize
+{
+    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+    pAic->AIC_ICCR = (0x1 << irq_id);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_AcknowledgeIt
+//* \brief Acknowledge corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_AcknowledgeIt (
+	AT91PS_AIC pAic)     // \arg pointer to the AIC registers
+{
+    pAic->AIC_EOICR = pAic->AIC_EOICR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_SetExceptionVector
+//* \brief Configure vector handler
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_SetExceptionVector (
+	unsigned int *pVector, // \arg pointer to the AIC registers
+	void (*Handler) () )   // \arg Interrupt Handler
+{
+	unsigned int oldVector = *pVector;
+
+	if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
+		*pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
+	else
+		*pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
+
+	return oldVector;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_Trig
+//* \brief Trig an IT
+//*----------------------------------------------------------------------------
+__inline void  AT91F_AIC_Trig (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg interrupt number
+{
+	pAic->AIC_ISCR = (0x1 << irq_id) ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_IsActive
+//* \brief Test if an IT is active
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_IsActive (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg Interrupt Number
+{
+	return (pAic->AIC_ISR & (0x1 << irq_id));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_IsPending
+//* \brief Test if an IT is pending
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_IsPending (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg Interrupt Number
+{
+	return (pAic->AIC_IPR & (0x1 << irq_id));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_Open
+//* \brief Set exception vectors and AIC registers to default values
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_Open(
+	AT91PS_AIC pAic,        // \arg pointer to the AIC registers
+	void (*IrqHandler) (),  // \arg Default IRQ vector exception
+	void (*FiqHandler) (),  // \arg Default FIQ vector exception
+	void (*DefaultHandler)  (), // \arg Default Handler set in ISR
+	void (*SpuriousHandler) (), // \arg Default Spurious Handler
+	unsigned int protectMode)   // \arg Debug Control Register
+{
+	int i;
+
+	// Disable all interrupts and set IVR to the default handler
+	for (i = 0; i < 32; ++i) {
+		AT91F_AIC_DisableIt(pAic, i);
+		AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler);
+	}
+
+	// Set the IRQ exception vector
+	AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
+	// Set the Fast Interrupt exception vector
+	AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
+
+	pAic->AIC_SPU = (unsigned int) SpuriousHandler;
+	pAic->AIC_DCR = protectMode;
+}
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  MC
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  DBGU
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_CfgPIO
+//* \brief Configure PIO controllers to drive DBGU signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA10_DTXD    ) |
+		((unsigned int) AT91C_PA9_DRXD    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH3_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH3 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH3_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA14_PWM3    ) |
+		((unsigned int) AT91C_PA7_PWM3    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH2_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH2_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA2_PWM2    ), // Peripheral A
+		((unsigned int) AT91C_PA25_PWM2    ) |
+		((unsigned int) AT91C_PA13_PWM2    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH1_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA1_PWM1    ), // Peripheral A
+		((unsigned int) AT91C_PA24_PWM1    ) |
+		((unsigned int) AT91C_PA12_PWM1    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH0_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA0_PWM0    ), // Peripheral A
+		((unsigned int) AT91C_PA23_PWM0    ) |
+		((unsigned int) AT91C_PA11_PWM0    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SSC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_CfgPIO
+//* \brief Configure PIO controllers to drive SSC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA17_TD      ) |
+		((unsigned int) AT91C_PA15_TF      ) |
+		((unsigned int) AT91C_PA19_RK      ) |
+		((unsigned int) AT91C_PA18_RD      ) |
+		((unsigned int) AT91C_PA20_RF      ) |
+		((unsigned int) AT91C_PA16_TK      ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  SPI
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SPI));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgPIO
+//* \brief Configure PIO controllers to drive SPI signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA11_NPCS0   ) |
+		((unsigned int) AT91C_PA13_MOSI    ) |
+		((unsigned int) AT91C_PA31_NPCS1   ) |
+		((unsigned int) AT91C_PA12_MISO    ) |
+		((unsigned int) AT91C_PA14_SPCK    ), // Peripheral A
+		((unsigned int) AT91C_PA9_NPCS1   ) |
+		((unsigned int) AT91C_PA30_NPCS2   ) |
+		((unsigned int) AT91C_PA10_NPCS2   ) |
+		((unsigned int) AT91C_PA22_NPCS3   ) |
+		((unsigned int) AT91C_PA3_NPCS3   ) |
+		((unsigned int) AT91C_PA5_NPCS3   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PWMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_PWMC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC2_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC2
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC2));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC2_CfgPIO
+//* \brief Configure PIO controllers to drive TC2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA26_TIOA2   ) |
+		((unsigned int) AT91C_PA27_TIOB2   ) |
+		((unsigned int) AT91C_PA29_TCLK2   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC1
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC1_CfgPIO
+//* \brief Configure PIO controllers to drive TC1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA15_TIOA1   ) |
+		((unsigned int) AT91C_PA16_TIOB1   ) |
+		((unsigned int) AT91C_PA28_TCLK1   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC0
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC0_CfgPIO
+//* \brief Configure PIO controllers to drive TC0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA0_TIOA0   ) |
+		((unsigned int) AT91C_PA1_TIOB0   ) |
+		((unsigned int) AT91C_PA4_TCLK0   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgPIO
+//* \brief Configure PIO controllers to drive PMC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA17_PCK1    ) |
+		((unsigned int) AT91C_PA21_PCK1    ) |
+		((unsigned int) AT91C_PA31_PCK2    ) |
+		((unsigned int) AT91C_PA18_PCK2    ) |
+		((unsigned int) AT91C_PA6_PCK0    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  ADC
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_ADC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgPIO
+//* \brief Configure PIO controllers to drive ADC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA8_ADTRG   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIOA_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PIOA
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIOA_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_PIOA));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TWI
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TWI));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_CfgPIO
+//* \brief Configure PIO controllers to drive TWI signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA3_TWD     ) |
+		((unsigned int) AT91C_PA4_TWCK    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  US1
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_US1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US1_CfgPIO
+//* \brief Configure PIO controllers to drive US1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA21_RXD1    ) |
+		((unsigned int) AT91C_PA27_DTR1    ) |
+		((unsigned int) AT91C_PA26_DCD1    ) |
+		((unsigned int) AT91C_PA22_TXD1    ) |
+		((unsigned int) AT91C_PA24_RTS1    ) |
+		((unsigned int) AT91C_PA23_SCK1    ) |
+		((unsigned int) AT91C_PA28_DSR1    ) |
+		((unsigned int) AT91C_PA29_RI1     ) |
+		((unsigned int) AT91C_PA25_CTS1    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  US0
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_US0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US0_CfgPIO
+//* \brief Configure PIO controllers to drive US0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA5_RXD0    ) |
+		((unsigned int) AT91C_PA6_TXD0    ) |
+		((unsigned int) AT91C_PA7_RTS0    ) |
+		((unsigned int) AT91C_PA8_CTS0    ), // Peripheral A
+		((unsigned int) AT91C_PA2_SCK0    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  UDP
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_UDP));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  AIC
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_IRQ0) |
+		((unsigned int) 1 << AT91C_ID_FIQ) |
+		((unsigned int) 1 << AT91C_ID_IRQ1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_CfgPIO
+//* \brief Configure PIO controllers to drive AIC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA30_IRQ1    ), // Peripheral A
+		((unsigned int) AT91C_PA20_IRQ0    ) |
+		((unsigned int) AT91C_PA19_FIQ     )); // Peripheral B
+}
+
+#endif // lib_AT91SAM7S64_H
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h
new file mode 100644
index 0000000..805a2bc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h
@@ -0,0 +1,4558 @@
+//* ----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//* ----------------------------------------------------------------------------
+//* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//* ----------------------------------------------------------------------------
+//* File Name           : lib_AT91SAM7X128.h
+//* Object              : AT91SAM7X128 inlined functions
+//* Generated           : AT91 SW Application Group  05/20/2005 (16:22:23)
+//*
+//* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
+//* CVS Reference       : /lib_pmc_SAM7X.h/1.1/Tue Feb  1 08:32:10 2005//
+//* CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005//
+//* CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004//
+//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
+//* CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004//
+//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
+//* CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
+//* CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004//
+//* CVS Reference       : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
+//* CVS Reference       : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
+//* CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
+//* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
+//* CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004//
+//* CVS Reference       : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
+//* CVS Reference       : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
+//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+//* CVS Reference       : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
+//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
+//* CVS Reference       : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
+//* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+//* CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002//
+//* ----------------------------------------------------------------------------
+
+#ifndef lib_AT91SAM7X128_H
+#define lib_AT91SAM7X128_H
+
+/* *****************************************************************************
+                SOFTWARE API FOR AIC
+   ***************************************************************************** */
+#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_ConfigureIt
+//* \brief Interrupt Handler Initialization
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_ConfigureIt (
+	AT91PS_AIC pAic,  // \arg pointer to the AIC registers
+	unsigned int irq_id,     // \arg interrupt number to initialize
+	unsigned int priority,   // \arg priority to give to the interrupt
+	unsigned int src_type,   // \arg activation and sense of activation
+	void (*newHandler) (void) ) // \arg address of the interrupt handler
+{
+	unsigned int oldHandler;
+    unsigned int mask ;
+
+    oldHandler = pAic->AIC_SVR[irq_id];
+
+    mask = 0x1 << irq_id ;
+    //* Disable the interrupt on the interrupt controller
+    pAic->AIC_IDCR = mask ;
+    //* Save the interrupt handler routine pointer and the interrupt priority
+    pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
+    //* Store the Source Mode Register
+    pAic->AIC_SMR[irq_id] = src_type | priority  ;
+    //* Clear the interrupt on the interrupt controller
+    pAic->AIC_ICCR = mask ;
+
+	return oldHandler;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_EnableIt
+//* \brief Enable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_EnableIt (
+	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
+	unsigned int irq_id ) // \arg interrupt number to initialize
+{
+    //* Enable the interrupt on the interrupt controller
+    pAic->AIC_IECR = 0x1 << irq_id ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_DisableIt
+//* \brief Disable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_DisableIt (
+	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
+	unsigned int irq_id ) // \arg interrupt number to initialize
+{
+    unsigned int mask = 0x1 << irq_id;
+    //* Disable the interrupt on the interrupt controller
+    pAic->AIC_IDCR = mask ;
+    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+    pAic->AIC_ICCR = mask ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_ClearIt
+//* \brief Clear corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_ClearIt (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg interrupt number to initialize
+{
+    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+    pAic->AIC_ICCR = (0x1 << irq_id);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_AcknowledgeIt
+//* \brief Acknowledge corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_AcknowledgeIt (
+	AT91PS_AIC pAic)     // \arg pointer to the AIC registers
+{
+    pAic->AIC_EOICR = pAic->AIC_EOICR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_SetExceptionVector
+//* \brief Configure vector handler
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_SetExceptionVector (
+	unsigned int *pVector, // \arg pointer to the AIC registers
+	void (*Handler) () )   // \arg Interrupt Handler
+{
+	unsigned int oldVector = *pVector;
+
+	if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
+		*pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
+	else
+		*pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
+
+	return oldVector;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_Trig
+//* \brief Trig an IT
+//*----------------------------------------------------------------------------
+__inline void  AT91F_AIC_Trig (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg interrupt number
+{
+	pAic->AIC_ISCR = (0x1 << irq_id) ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_IsActive
+//* \brief Test if an IT is active
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_IsActive (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg Interrupt Number
+{
+	return (pAic->AIC_ISR & (0x1 << irq_id));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_IsPending
+//* \brief Test if an IT is pending
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_IsPending (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg Interrupt Number
+{
+	return (pAic->AIC_IPR & (0x1 << irq_id));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_Open
+//* \brief Set exception vectors and AIC registers to default values
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_Open(
+	AT91PS_AIC pAic,        // \arg pointer to the AIC registers
+	void (*IrqHandler) (),  // \arg Default IRQ vector exception
+	void (*FiqHandler) (),  // \arg Default FIQ vector exception
+	void (*DefaultHandler)  (), // \arg Default Handler set in ISR
+	void (*SpuriousHandler) (), // \arg Default Spurious Handler
+	unsigned int protectMode)   // \arg Debug Control Register
+{
+	int i;
+
+	// Disable all interrupts and set IVR to the default handler
+	for (i = 0; i < 32; ++i) {
+		AT91F_AIC_DisableIt(pAic, i);
+		AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);
+	}
+
+	// Set the IRQ exception vector
+	AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
+	// Set the Fast Interrupt exception vector
+	AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
+
+	pAic->AIC_SPU = (unsigned int) SpuriousHandler;
+	pAic->AIC_DCR = protectMode;
+}
+/* *****************************************************************************
+                SOFTWARE API FOR PDC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetNextRx
+//* \brief Set the next receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextRx (
+	AT91PS_PDC pPDC,     // \arg pointer to a PDC controller
+	char *address,       // \arg address to the next bloc to be received
+	unsigned int bytes)  // \arg number of bytes to be received
+{
+	pPDC->PDC_RNPR = (unsigned int) address;
+	pPDC->PDC_RNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetNextTx
+//* \brief Set the next transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextTx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be transmitted
+	unsigned int bytes)    // \arg number of bytes to be transmitted
+{
+	pPDC->PDC_TNPR = (unsigned int) address;
+	pPDC->PDC_TNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetRx
+//* \brief Set the receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetRx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be received
+	unsigned int bytes)    // \arg number of bytes to be received
+{
+	pPDC->PDC_RPR = (unsigned int) address;
+	pPDC->PDC_RCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetTx
+//* \brief Set the transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetTx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be transmitted
+	unsigned int bytes)    // \arg number of bytes to be transmitted
+{
+	pPDC->PDC_TPR = (unsigned int) address;
+	pPDC->PDC_TCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_EnableTx
+//* \brief Enable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableTx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_EnableRx
+//* \brief Enable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableRx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_DisableTx
+//* \brief Disable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableTx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_DisableRx
+//* \brief Disable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableRx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsTxEmpty
+//* \brief Test if the current transfer descriptor has been sent
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_TCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsNextTxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_TNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsRxEmpty
+//* \brief Test if the current transfer descriptor has been filled
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_RCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsNextRxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_RNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_Open
+//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Open (
+	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
+{
+    //* Disable the RX and TX PDC transfer requests
+	AT91F_PDC_DisableRx(pPDC);
+	AT91F_PDC_DisableTx(pPDC);
+
+	//* Reset all Counter register Next buffer first
+	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+    //* Enable the RX and TX PDC transfer requests
+	AT91F_PDC_EnableRx(pPDC);
+	AT91F_PDC_EnableTx(pPDC);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_Close
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Close (
+	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
+{
+    //* Disable the RX and TX PDC transfer requests
+	AT91F_PDC_DisableRx(pPDC);
+	AT91F_PDC_DisableTx(pPDC);
+
+	//* Reset all Counter register Next buffer first
+	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SendFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_SendFrame(
+	AT91PS_PDC pPDC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	if (AT91F_PDC_IsTxEmpty(pPDC)) {
+		//* Buffer and next buffer can be initialized
+		AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
+		AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
+		return 2;
+	}
+	else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
+		//* Only one buffer can be initialized
+		AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
+		return 1;
+	}
+	else {
+		//* All buffer are in use...
+		return 0;
+	}
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_ReceiveFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_ReceiveFrame (
+	AT91PS_PDC pPDC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	if (AT91F_PDC_IsRxEmpty(pPDC)) {
+		//* Buffer and next buffer can be initialized
+		AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
+		AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
+		return 2;
+	}
+	else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
+		//* Only one buffer can be initialized
+		AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
+		return 1;
+	}
+	else {
+		//* All buffer are in use...
+		return 0;
+	}
+}
+/* *****************************************************************************
+                SOFTWARE API FOR DBGU
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_InterruptEnable
+//* \brief Enable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptEnable(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  dbgu interrupt to be enabled
+{
+        pDbgu->DBGU_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_InterruptDisable
+//* \brief Disable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptDisable(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  dbgu interrupt to be disabled
+{
+        pDbgu->DBGU_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_GetInterruptMaskStatus
+//* \brief Return DBGU Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
+        AT91PS_DBGU pDbgu) // \arg  pointer to a DBGU controller
+{
+        return pDbgu->DBGU_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_IsInterruptMasked
+//* \brief Test if DBGU Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_DBGU_IsInterruptMasked(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PIO
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgPeriph
+//* \brief Enable pins to be drived by peripheral
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPeriph(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int periphAEnable,  // \arg PERIPH A to enable
+	unsigned int periphBEnable)  // \arg PERIPH B to enable
+
+{
+	pPio->PIO_ASR = periphAEnable;
+	pPio->PIO_BSR = periphBEnable;
+	pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgOutput
+//* \brief Enable PIO in output mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOutput(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int pioEnable)      // \arg PIO to be enabled
+{
+	pPio->PIO_PER = pioEnable; // Set in PIO mode
+	pPio->PIO_OER = pioEnable; // Configure in Output
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgInput
+//* \brief Enable PIO in input mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInput(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int inputEnable)      // \arg PIO to be enabled
+{
+	// Disable output
+	pPio->PIO_ODR  = inputEnable;
+	pPio->PIO_PER  = inputEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgOpendrain
+//* \brief Configure PIO in open drain
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOpendrain(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int multiDrvEnable) // \arg pio to be configured in open drain
+{
+	// Configure the multi-drive option
+	pPio->PIO_MDDR = ~multiDrvEnable;
+	pPio->PIO_MDER = multiDrvEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgPullup
+//* \brief Enable pullup on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPullup(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int pullupEnable)   // \arg enable pullup on PIO
+{
+		// Connect or not Pullup
+	pPio->PIO_PPUDR = ~pullupEnable;
+	pPio->PIO_PPUER = pullupEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgDirectDrive
+//* \brief Enable direct drive on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgDirectDrive(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int directDrive)    // \arg PIO to be configured with direct drive
+
+{
+	// Configure the Direct Drive
+	pPio->PIO_OWDR  = ~directDrive;
+	pPio->PIO_OWER  = directDrive;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgInputFilter
+//* \brief Enable input filter on input PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInputFilter(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int inputFilter)    // \arg PIO to be configured with input filter
+
+{
+	// Configure the Direct Drive
+	pPio->PIO_IFDR  = ~inputFilter;
+	pPio->PIO_IFER  = inputFilter;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInput
+//* \brief Return PIO input value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
+	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+	return pPio->PIO_PDSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInputSet
+//* \brief Test if PIO is input flag is active
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputSet(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PIO_GetInput(pPio) & flag);
+}
+
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_SetOutput
+//* \brief Set to 1 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_SetOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be set
+{
+	pPio->PIO_SODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_ClearOutput
+//* \brief Set to 0 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ClearOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be cleared
+{
+	pPio->PIO_CODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_ForceOutput
+//* \brief Force output when Direct drive option is enabled
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ForceOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be forced
+{
+	pPio->PIO_ODSR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Enable
+//* \brief Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Enable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be enabled 
+{
+        pPio->PIO_PER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Disable
+//* \brief Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Disable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be disabled 
+{
+        pPio->PIO_PDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetStatus
+//* \brief Return PIO Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_PSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsSet
+//* \brief Test if PIO is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputEnable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output to be enabled
+{
+        pPio->PIO_OER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputDisable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output to be disabled
+{
+        pPio->PIO_ODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputStatus
+//* \brief Return PIO Output Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_OSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOuputSet
+//* \brief Test if PIO Output is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InputFilterEnable
+//* \brief Input Filter Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio input filter to be enabled
+{
+        pPio->PIO_IFER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InputFilterDisable
+//* \brief Input Filter Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio input filter to be disabled
+{
+        pPio->PIO_IFDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInputFilterStatus
+//* \brief Return PIO Input Filter Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_IFSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInputFilterSet
+//* \brief Test if PIO Input filter is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputFilterSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputDataStatus
+//* \brief Return PIO Output Data Status 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status 
+	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ODSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InterruptEnable
+//* \brief Enable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio interrupt to be enabled
+{
+        pPio->PIO_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InterruptDisable
+//* \brief Disable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio interrupt to be disabled
+{
+        pPio->PIO_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInterruptMaskStatus
+//* \brief Return PIO Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInterruptStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInterruptMasked
+//* \brief Test if PIO Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptMasked(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInterruptSet
+//* \brief Test if PIO Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_MultiDriverEnable
+//* \brief Multi Driver Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be enabled
+{
+        pPio->PIO_MDER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_MultiDriverDisable
+//* \brief Multi Driver Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be disabled
+{
+        pPio->PIO_MDDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetMultiDriverStatus
+//* \brief Return PIO Multi Driver Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_MDSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsMultiDriverSet
+//* \brief Test if PIO MultiDriver is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsMultiDriverSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_A_RegisterSelection
+//* \brief PIO A Register Selection 
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_A_RegisterSelection(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio A register selection
+{
+        pPio->PIO_ASR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_B_RegisterSelection
+//* \brief PIO B Register Selection 
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_B_RegisterSelection(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio B register selection 
+{
+        pPio->PIO_BSR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Get_AB_RegisterStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ABSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsAB_RegisterSet
+//* \brief Test if PIO AB Register is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsAB_RegisterSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputWriteEnable
+//* \brief Output Write Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output write to be enabled
+{
+        pPio->PIO_OWER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputWriteDisable
+//* \brief Output Write Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output write to be disabled
+{
+        pPio->PIO_OWDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputWriteStatus
+//* \brief Return PIO Output Write Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_OWSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOutputWriteSet
+//* \brief Test if PIO OutputWrite is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputWriteSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetCfgPullup
+//* \brief Return PIO Configuration Pullup
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup 
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_PPUSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOutputDataStatusSet
+//* \brief Test if PIO Output Data Status is Set 
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputDataStatusSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsCfgPullupStatusSet
+//* \brief Test if PIO Configuration Pullup Status is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsCfgPullupStatusSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PMC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgSysClkEnableReg
+//* \brief Configure the System Clock Enable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkEnableReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	//* Write to the SCER register
+	pPMC->PMC_SCER = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgSysClkDisableReg
+//* \brief Configure the System Clock Disable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkDisableReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	//* Write to the SCDR register
+	pPMC->PMC_SCDR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetSysClkStatusReg
+//* \brief Return the System Clock Status Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
+	AT91PS_PMC pPMC // pointer to a CAN controller
+	)
+{
+	return pPMC->PMC_SCSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnablePeriphClock
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePeriphClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int periphIds)  // \arg IDs of peripherals to enable
+{
+	pPMC->PMC_PCER = periphIds;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisablePeriphClock
+//* \brief Disable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePeriphClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int periphIds)  // \arg IDs of peripherals to enable
+{
+	pPMC->PMC_PCDR = periphIds;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetPeriphClock
+//* \brief Get peripheral clock status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetPeriphClock (
+	AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+	return pPMC->PMC_PCSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_CfgMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscillatorReg (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int mode)
+{
+	pCKGR->CKGR_MOR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	return pCKGR->CKGR_MOR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_EnableMainOscillator
+//* \brief Enable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_EnableMainOscillator(
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_DisableMainOscillator
+//* \brief Disable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_DisableMainOscillator (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_CfgMainOscStartUpTime
+//* \brief Cfg MOR Register according to the main osc startup time
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscStartUpTime (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int startup_time,  // \arg main osc startup time in microsecond (us)
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
+	pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainClockFreqReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	return pCKGR->CKGR_MCFR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainClock
+//* \brief Return Main clock in Hz
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClock (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	return ((pCKGR->CKGR_MCFR  & AT91C_CKGR_MAINF) * slowClock) >> 4;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgMCKReg
+//* \brief Cfg Master Clock Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgMCKReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	pPMC->PMC_MCKR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetMCKReg
+//* \brief Return Master Clock Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMCKReg(
+	AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+	return pPMC->PMC_MCKR;
+}
+
+//*------------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetMasterClock
+//* \brief Return master clock in Hz which correponds to processor clock for ARM7
+//*------------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMasterClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	unsigned int reg = pPMC->PMC_MCKR;
+	unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
+	unsigned int pllDivider, pllMultiplier;
+
+	switch (reg & AT91C_PMC_CSS) {
+		case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
+			return slowClock / prescaler;
+		case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
+			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
+		case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
+			reg = pCKGR->CKGR_PLLR;
+			pllDivider    = (reg  & AT91C_CKGR_DIV);
+			pllMultiplier = ((reg  & AT91C_CKGR_MUL) >> 16) + 1;
+			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
+	}
+	return 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePCK (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int pck,  // \arg Peripheral clock identifier 0 .. 7
+	unsigned int mode)
+{
+	pPMC->PMC_PCKR[pck] = mode;
+	pPMC->PMC_SCER = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePCK (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int pck)  // \arg Peripheral clock identifier 0 .. 7
+{
+	pPMC->PMC_SCDR = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnableIt
+//* \brief Enable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnableIt (
+	AT91PS_PMC pPMC,     // pointer to a PMC controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pPMC->PMC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisableIt
+//* \brief Disable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisableIt (
+	AT91PS_PMC pPMC, // pointer to a PMC controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pPMC->PMC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetStatus
+//* \brief Return PMC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
+	AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+	return pPMC->PMC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetInterruptMaskStatus
+//* \brief Return PMC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
+	AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+	return pPMC->PMC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_IsInterruptMasked
+//* \brief Test if PMC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsInterruptMasked(
+        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_IsStatusSet
+//* \brief Test if PMC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsStatusSet(
+        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PMC_GetStatus(pPMC) & flag);
+}/* *****************************************************************************
+                SOFTWARE API FOR RSTC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTSoftReset
+//* \brief Start Software Reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTSoftReset(
+        AT91PS_RSTC pRSTC,
+        unsigned int reset)
+{
+	pRSTC->RSTC_RCR = (0xA5000000 | reset);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTSetMode
+//* \brief Set Reset Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTSetMode(
+        AT91PS_RSTC pRSTC,
+        unsigned int mode)
+{
+	pRSTC->RSTC_RMR = (0xA5000000 | mode);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTGetMode
+//* \brief Get Reset Mode
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTGetMode(
+        AT91PS_RSTC pRSTC)
+{
+	return (pRSTC->RSTC_RMR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTGetStatus
+//* \brief Get Reset Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTGetStatus(
+        AT91PS_RSTC pRSTC)
+{
+	return (pRSTC->RSTC_RSR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTIsSoftRstActive
+//* \brief Return !=0 if software reset is still not completed
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTIsSoftRstActive(
+        AT91PS_RSTC pRSTC)
+{
+	return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR RTTC
+   ***************************************************************************** */
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_SetRTT_TimeBase()
+//* \brief  Set the RTT prescaler according to the TimeBase in ms
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTSetTimeBase(
+        AT91PS_RTTC pRTTC, 
+        unsigned int ms)
+{
+	if (ms > 2000)
+		return 1;   // AT91C_TIME_OUT_OF_RANGE
+	pRTTC->RTTC_RTMR &= ~0xFFFF;	
+	pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF);	
+	return 0;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTTSetPrescaler()
+//* \brief  Set the new prescaler value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTSetPrescaler(
+        AT91PS_RTTC pRTTC, 
+        unsigned int rtpres)
+{
+	pRTTC->RTTC_RTMR &= ~0xFFFF;	
+	pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF);	
+	return (pRTTC->RTTC_RTMR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTTRestart()
+//* \brief  Restart the RTT prescaler
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTRestart(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;	
+}
+
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_SetAlarmINT()
+//* \brief  Enable RTT Alarm Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetAlarmINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_ClearAlarmINT()
+//* \brief  Disable RTT Alarm Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTClearAlarmINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_SetRttIncINT()
+//* \brief  Enable RTT INC Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetRttIncINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_ClearRttIncINT()
+//* \brief  Disable RTT INC Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTClearRttIncINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_SetAlarmValue()
+//* \brief  Set RTT Alarm Value
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetAlarmValue(
+        AT91PS_RTTC pRTTC, unsigned int alarm)
+{
+	pRTTC->RTTC_RTAR = alarm;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_GetAlarmValue()
+//* \brief  Get RTT Alarm Value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTGetAlarmValue(
+        AT91PS_RTTC pRTTC)
+{
+	return(pRTTC->RTTC_RTAR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTTGetStatus()
+//* \brief  Read the RTT status
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTGetStatus(
+        AT91PS_RTTC pRTTC)
+{
+	return(pRTTC->RTTC_RTSR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_ReadValue()
+//* \brief  Read the RTT value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTReadValue(
+        AT91PS_RTTC pRTTC)
+{
+        register volatile unsigned int val1,val2;
+	do
+	{
+		val1 = pRTTC->RTTC_RTVR;
+		val2 = pRTTC->RTTC_RTVR;
+	}	
+	while(val1 != val2);
+	return(val1);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR PITC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITInit
+//* \brief System timer init : period in µsecond, system clock freq in MHz
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITInit(
+        AT91PS_PITC pPITC,
+        unsigned int period,
+        unsigned int pit_frequency)
+{
+	pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10
+	pPITC->PITC_PIMR |= AT91C_PITC_PITEN;	 
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITSetPIV
+//* \brief Set the PIT Periodic Interval Value 
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITSetPIV(
+        AT91PS_PITC pPITC,
+        unsigned int piv)
+{
+	pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITEnableInt
+//* \brief Enable PIT periodic interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITEnableInt(
+        AT91PS_PITC pPITC)
+{
+	pPITC->PITC_PIMR |= AT91C_PITC_PITIEN;	 
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITDisableInt
+//* \brief Disable PIT periodic interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITDisableInt(
+        AT91PS_PITC pPITC)
+{
+	pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;	 
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetMode
+//* \brief Read PIT mode register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetMode(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PIMR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetStatus
+//* \brief Read PIT status register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetStatus(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PISR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetPIIR
+//* \brief Read PIT CPIV and PICNT without ressetting the counters
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetPIIR(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PIIR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetPIVR
+//* \brief Read System timer CPIV and PICNT without ressetting the counters
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetPIVR(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PIVR);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR WDTC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTSetMode
+//* \brief Set Watchdog Mode Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTSetMode(
+        AT91PS_WDTC pWDTC,
+        unsigned int Mode)
+{
+	pWDTC->WDTC_WDMR = Mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTRestart
+//* \brief Restart Watchdog
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTRestart(
+        AT91PS_WDTC pWDTC)
+{
+	pWDTC->WDTC_WDCR = 0xA5000001;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTSGettatus
+//* \brief Get Watchdog Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_WDTSGettatus(
+        AT91PS_WDTC pWDTC)
+{
+	return(pWDTC->WDTC_WDSR & 0x3);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTGetPeriod
+//* \brief Translate ms into Watchdog Compatible value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms)
+{
+	if ((ms < 4) || (ms > 16000))
+		return 0;
+	return((ms << 8) / 1000);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR VREG
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_VREG_Enable_LowPowerMode
+//* \brief Enable VREG Low Power Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_Enable_LowPowerMode(
+        AT91PS_VREG pVREG)
+{
+	pVREG->VREG_MR |= AT91C_VREG_PSTDBY;	 
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_VREG_Disable_LowPowerMode
+//* \brief Disable VREG Low Power Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_Disable_LowPowerMode(
+        AT91PS_VREG pVREG)
+{
+	pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY;	 
+}/* *****************************************************************************
+                SOFTWARE API FOR MC
+   ***************************************************************************** */
+
+#define AT91C_MC_CORRECT_KEY  ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_Remap
+//* \brief Make Remap
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_Remap (void)     //  
+{
+    AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
+    
+    pMC->MC_RCR = AT91C_MC_RCB;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_CfgModeReg
+//* \brief Configure the EFC Mode Register of the MC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_CfgModeReg (
+	AT91PS_MC pMC, // pointer to a MC controller
+	unsigned int mode)        // mode register 
+{
+	// Write to the FMR register
+	pMC->MC_FMR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_GetModeReg
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetModeReg(
+	AT91PS_MC pMC) // pointer to a MC controller
+{
+	return pMC->MC_FMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_ComputeFMCN
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_ComputeFMCN(
+	int master_clock) // master clock in Hz
+{
+	return (master_clock/1000000 +2);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_PerformCmd
+//* \brief Perform EFC Command
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_PerformCmd (
+	AT91PS_MC pMC, // pointer to a MC controller
+    unsigned int transfer_cmd)
+{
+	pMC->MC_FCR = transfer_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_GetStatus
+//* \brief Return MC EFC Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetStatus(
+	AT91PS_MC pMC) // pointer to a MC controller
+{
+	return pMC->MC_FSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_IsInterruptMasked
+//* \brief Test if EFC MC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
+        AT91PS_MC pMC,   // \arg  pointer to a MC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_IsInterruptSet
+//* \brief Test if EFC MC Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptSet(
+        AT91PS_MC pMC,   // \arg  pointer to a MC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_MC_EFC_GetStatus(pMC) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR SPI
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Open
+//* \brief Open a SPI Port
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_Open (
+        const unsigned int null)  // \arg
+{
+        /* NOT DEFINED AT THIS MOMENT */
+        return ( 0 );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgCs
+//* \brief Configure SPI chip select register
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgCs (
+	AT91PS_SPI pSPI,     // pointer to a SPI controller
+	int cs,     // SPI cs number (0 to 3)
+ 	int val)   //  chip select register
+{
+	//* Write to the CSR register
+	*(pSPI->SPI_CSR + cs) = val;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_EnableIt
+//* \brief Enable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_EnableIt (
+	AT91PS_SPI pSPI,     // pointer to a SPI controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pSPI->SPI_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_DisableIt
+//* \brief Disable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_DisableIt (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pSPI->SPI_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Reset
+//* \brief Reset the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Reset (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SWRST;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Enable
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Enable (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SPIEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Disable
+//* \brief Disable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Disable (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SPIDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgMode
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgMode (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	int mode)        // mode register 
+{
+	//* Write to the MR register
+	pSPI->SPI_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgPCS
+//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgPCS (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	char PCS_Device) // PCS of the Device
+{	
+ 	//* Write to the MR register
+	pSPI->SPI_MR &= 0xFFF0FFFF;
+	pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_ReceiveFrame (
+	AT91PS_SPI pSPI,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pSPI->SPI_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_SendFrame(
+	AT91PS_SPI pSPI,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pSPI->SPI_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Close
+//* \brief Close SPI: disable IT disable transfert, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Close (
+	AT91PS_SPI pSPI)     // \arg pointer to a SPI controller
+{
+    //* Reset all the Chip Select register
+    pSPI->SPI_CSR[0] = 0 ;
+    pSPI->SPI_CSR[1] = 0 ;
+    pSPI->SPI_CSR[2] = 0 ;
+    pSPI->SPI_CSR[3] = 0 ;
+
+    //* Reset the SPI mode
+    pSPI->SPI_MR = 0  ;
+
+    //* Disable all interrupts
+    pSPI->SPI_IDR = 0xFFFFFFFF ;
+
+    //* Abort the Peripheral Data Transfers
+    AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
+
+    //* Disable receiver and transmitter and stop any activity immediately
+    pSPI->SPI_CR = AT91C_SPI_SPIDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_PutChar (
+	AT91PS_SPI pSPI,
+	unsigned int character,
+             unsigned int cs_number )
+{
+    unsigned int value_for_cs;
+    value_for_cs = (~(1 << cs_number)) & 0xF;  //Place a zero among a 4 ONEs number
+    pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_GetChar (
+	const AT91PS_SPI pSPI)
+{
+    return((pSPI->SPI_RDR) & 0xFFFF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_GetInterruptMaskStatus
+//* \brief Return SPI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
+        AT91PS_SPI pSpi) // \arg  pointer to a SPI controller
+{
+        return pSpi->SPI_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_IsInterruptMasked
+//* \brief Test if SPI Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_IsInterruptMasked(
+        AT91PS_SPI pSpi,   // \arg  pointer to a SPI controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR USART
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Baudrate
+//* \brief Calculate the baudrate
+//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
+                        AT91C_US_NBSTOP_1_BIT + \
+                        AT91C_US_PAR_NONE + \
+                        AT91C_US_CHRL_8_BITS + \
+                        AT91C_US_CLKS_CLOCK )
+
+//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
+                            AT91C_US_NBSTOP_1_BIT + \
+                            AT91C_US_PAR_NONE + \
+                            AT91C_US_CHRL_8_BITS + \
+                            AT91C_US_CLKS_EXT )
+
+//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
+                       AT91C_US_USMODE_NORMAL + \
+                       AT91C_US_NBSTOP_1_BIT + \
+                       AT91C_US_PAR_NONE + \
+                       AT91C_US_CHRL_8_BITS + \
+                       AT91C_US_CLKS_CLOCK )
+
+//* SCK used Label
+#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
+
+//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
+#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
+					   		 AT91C_US_CLKS_CLOCK +\
+                       		 AT91C_US_NBSTOP_1_BIT + \
+                       		 AT91C_US_PAR_EVEN + \
+                       		 AT91C_US_CHRL_8_BITS + \
+                       		 AT91C_US_CKLO +\
+                       		 AT91C_US_OVER)
+
+//* Standard IRDA mode
+#define AT91C_US_ASYNC_IRDA_MODE (  AT91C_US_USMODE_IRDA + \
+                            AT91C_US_NBSTOP_1_BIT + \
+                            AT91C_US_PAR_NONE + \
+                            AT91C_US_CHRL_8_BITS + \
+                            AT91C_US_CLKS_CLOCK )
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Baudrate
+//* \brief Caluculate baud_value according to the main clock and the baud rate
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Baudrate (
+	const unsigned int main_clock, // \arg peripheral clock
+	const unsigned int baud_rate)  // \arg UART baudrate
+{
+	unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
+	if ((baud_value % 10) >= 5)
+		baud_value = (baud_value / 10) + 1;
+	else
+		baud_value /= 10;
+	return baud_value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetBaudrate (
+	AT91PS_USART pUSART,    // \arg pointer to a USART controller
+	unsigned int mainClock, // \arg peripheral clock
+	unsigned int speed)     // \arg UART baudrate
+{
+	//* Define the baud rate divisor register
+	pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetTimeguard
+//* \brief Set USART timeguard
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetTimeguard (
+	AT91PS_USART pUSART,    // \arg pointer to a USART controller
+	unsigned int timeguard) // \arg timeguard value
+{
+	//* Write the Timeguard Register
+	pUSART->US_TTGR = timeguard ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableIt
+//* \brief Enable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableIt (
+	AT91PS_USART pUSART, // \arg pointer to a USART controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pUSART->US_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableIt
+//* \brief Disable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableIt (
+	AT91PS_USART pUSART, // \arg pointer to a USART controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IER register
+	pUSART->US_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Configure
+//* \brief Configure USART
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Configure (
+	AT91PS_USART pUSART,     // \arg pointer to a USART controller
+	unsigned int mainClock,  // \arg peripheral clock
+	unsigned int mode ,      // \arg mode Register to be programmed
+	unsigned int baudRate ,  // \arg baudrate to be programmed
+	unsigned int timeguard ) // \arg timeguard to be programmed
+{
+    //* Disable interrupts
+    pUSART->US_IDR = (unsigned int) -1;
+
+    //* Reset receiver and transmitter
+    pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
+
+	//* Define the baud rate divisor register
+	AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
+
+	//* Write the Timeguard Register
+	AT91F_US_SetTimeguard(pUSART, timeguard);
+
+    //* Clear Transmit and Receive Counters
+    AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
+
+    //* Define the USART mode
+    pUSART->US_MR = mode  ;
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableRx
+//* \brief Enable receiving characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Enable receiver
+    pUSART->US_CR = AT91C_US_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableTx
+//* \brief Enable sending characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Enable  transmitter
+    pUSART->US_CR = AT91C_US_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ResetRx
+//* \brief Reset Receiver and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+	//* Reset receiver
+	pUSART->US_CR = AT91C_US_RSTRX;
+    //* Re-Enable receiver
+    pUSART->US_CR = AT91C_US_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ResetTx
+//* \brief Reset Transmitter and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+	//* Reset transmitter
+	pUSART->US_CR = AT91C_US_RSTTX;
+    //* Enable transmitter
+    pUSART->US_CR = AT91C_US_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableRx
+//* \brief Disable Receiver
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Disable receiver
+    pUSART->US_CR = AT91C_US_RXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableTx
+//* \brief Disable Transmitter
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Disable transmitter
+    pUSART->US_CR = AT91C_US_TXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Close
+//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Close (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Reset the baud rate divisor register
+    pUSART->US_BRGR = 0 ;
+
+    //* Reset the USART mode
+    pUSART->US_MR = 0  ;
+
+    //* Reset the Timeguard Register
+    pUSART->US_TTGR = 0;
+
+    //* Disable all interrupts
+    pUSART->US_IDR = 0xFFFFFFFF ;
+
+    //* Abort the Peripheral Data Transfers
+    AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
+
+    //* Disable receiver and transmitter and stop any activity immediately
+    pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_TxReady
+//* \brief Return 1 if a character can be written in US_THR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_TxReady (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR & AT91C_US_TXRDY);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_RxReady
+//* \brief Return 1 if a character can be read in US_RHR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_RxReady (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR & AT91C_US_RXRDY);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Error
+//* \brief Return the error flag
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Error (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR &
+    	(AT91C_US_OVRE |  // Overrun error
+    	 AT91C_US_FRAME | // Framing error
+    	 AT91C_US_PARE));  // Parity error
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_PutChar (
+	AT91PS_USART pUSART,
+	int character )
+{
+    pUSART->US_THR = (character & 0x1FF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_US_GetChar (
+	const AT91PS_USART pUSART)
+{
+    return((pUSART->US_RHR) & 0x1FF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_SendFrame(
+	AT91PS_USART pUSART,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pUSART->US_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_ReceiveFrame (
+	AT91PS_USART pUSART,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pUSART->US_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetIrdaFilter
+//* \brief Set the value of IrDa filter tregister
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetIrdaFilter (
+	AT91PS_USART pUSART,
+	unsigned char value
+)
+{
+	pUSART->US_IF = value;
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR SSC
+   ***************************************************************************** */
+//* Define the standard I2S mode configuration
+
+//* Configuration to set in the SSC Transmit Clock Mode Register
+//* Parameters :  nb_bit_by_slot : 8, 16 or 32 bits
+//* 			  nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+									   AT91C_SSC_CKS_DIV   +\
+                            		   AT91C_SSC_CKO_CONTINOUS      +\
+                            		   AT91C_SSC_CKG_NONE    +\
+                                       AT91C_SSC_START_FALL_RF +\
+                           			   AT91C_SSC_STTOUT  +\
+                            		   ((1<<16) & AT91C_SSC_STTDLY) +\
+                            		   ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
+
+
+//* Configuration to set in the SSC Transmit Frame Mode Register
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
+//* 			 nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+									(nb_bit_by_slot-1)  +\
+                            		AT91C_SSC_MSBF   +\
+                            		(((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB)  +\
+                            		(((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
+                            		AT91C_SSC_FSOS_NEGATIVE)
+
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_SetBaudrate (
+        AT91PS_SSC pSSC,        // \arg pointer to a SSC controller
+        unsigned int mainClock, // \arg peripheral clock
+        unsigned int speed)     // \arg SSC baudrate
+{
+        unsigned int baud_value;
+        //* Define the baud rate divisor register
+        if (speed == 0)
+           baud_value = 0;
+        else
+        {
+           baud_value = (unsigned int) (mainClock * 10)/(2*speed);
+           if ((baud_value % 10) >= 5)
+                  baud_value = (baud_value / 10) + 1;
+           else
+                  baud_value /= 10;
+        }
+
+        pSSC->SSC_CMR = baud_value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_Configure
+//* \brief Configure SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_Configure (
+             AT91PS_SSC pSSC,          // \arg pointer to a SSC controller
+             unsigned int syst_clock,  // \arg System Clock Frequency
+             unsigned int baud_rate,   // \arg Expected Baud Rate Frequency
+             unsigned int clock_rx,    // \arg Receiver Clock Parameters
+             unsigned int mode_rx,     // \arg mode Register to be programmed
+             unsigned int clock_tx,    // \arg Transmitter Clock Parameters
+             unsigned int mode_tx)     // \arg mode Register to be programmed
+{
+    //* Disable interrupts
+	pSSC->SSC_IDR = (unsigned int) -1;
+
+    //* Reset receiver and transmitter
+	pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
+
+    //* Define the Clock Mode Register
+	AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
+
+     //* Write the Receive Clock Mode Register
+	pSSC->SSC_RCMR =  clock_rx;
+
+     //* Write the Transmit Clock Mode Register
+	pSSC->SSC_TCMR =  clock_tx;
+
+     //* Write the Receive Frame Mode Register
+	pSSC->SSC_RFMR =  mode_rx;
+
+     //* Write the Transmit Frame Mode Register
+	pSSC->SSC_TFMR =  mode_tx;
+
+    //* Clear Transmit and Receive Counters
+	AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
+
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableRx
+//* \brief Enable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableRx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Enable receiver
+    pSSC->SSC_CR = AT91C_SSC_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableRx
+//* \brief Disable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableRx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Disable receiver
+    pSSC->SSC_CR = AT91C_SSC_RXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableTx
+//* \brief Enable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableTx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Enable  transmitter
+    pSSC->SSC_CR = AT91C_SSC_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableTx
+//* \brief Disable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableTx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Disable  transmitter
+    pSSC->SSC_CR = AT91C_SSC_TXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableIt
+//* \brief Enable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableIt (
+	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pSSC->SSC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableIt
+//* \brief Disable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableIt (
+	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pSSC->SSC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_ReceiveFrame (
+	AT91PS_SSC pSSC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pSSC->SSC_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_SendFrame(
+	AT91PS_SSC pSSC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pSSC->SSC_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_GetInterruptMaskStatus
+//* \brief Return SSC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
+        AT91PS_SSC pSsc) // \arg  pointer to a SSC controller
+{
+        return pSsc->SSC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_IsInterruptMasked
+//* \brief Test if SSC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_SSC_IsInterruptMasked(
+        AT91PS_SSC pSsc,   // \arg  pointer to a SSC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR TWI
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_EnableIt
+//* \brief Enable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_EnableIt (
+	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pTWI->TWI_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_DisableIt
+//* \brief Disable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_DisableIt (
+	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pTWI->TWI_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_Configure
+//* \brief Configure TWI in master mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI )          // \arg pointer to a TWI controller
+{
+    //* Disable interrupts
+	pTWI->TWI_IDR = (unsigned int) -1;
+
+    //* Reset peripheral
+	pTWI->TWI_CR = AT91C_TWI_SWRST;
+
+	//* Set Master mode
+	pTWI->TWI_CR = AT91C_TWI_MSEN;
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_GetInterruptMaskStatus
+//* \brief Return TWI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
+        AT91PS_TWI pTwi) // \arg  pointer to a TWI controller
+{
+        return pTwi->TWI_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_IsInterruptMasked
+//* \brief Test if TWI Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_TWI_IsInterruptMasked(
+        AT91PS_TWI pTwi,   // \arg  pointer to a TWI controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PWMC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_GetStatus
+//* \brief Return PWM Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
+	AT91PS_PWMC pPWM) // pointer to a PWM controller
+{
+	return pPWM->PWMC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_InterruptEnable
+//* \brief Enable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptEnable(
+        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  PWM interrupt to be enabled
+{
+        pPwm->PWMC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_InterruptDisable
+//* \brief Disable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptDisable(
+        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  PWM interrupt to be disabled
+{
+        pPwm->PWMC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_GetInterruptMaskStatus
+//* \brief Return PWM Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
+        AT91PS_PWMC pPwm) // \arg  pointer to a PWM controller
+{
+        return pPwm->PWMC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_IsInterruptMasked
+//* \brief Test if PWM Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsInterruptMasked(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_IsStatusSet
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsStatusSet(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PWMC_GetStatus(pPWM) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_CfgChannel
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int channelId, // \arg PWM channel ID
+        unsigned int mode, // \arg  PWM mode
+        unsigned int period, // \arg PWM period
+        unsigned int duty) // \arg PWM duty cycle
+{
+	pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
+	pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
+	pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_StartChannel
+//* \brief Enable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StartChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_ENA = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_StopChannel
+//* \brief Disable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StopChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_DIS = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_UpdateChannel
+//* \brief Update Period or Duty Cycle
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_UpdateChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int channelId, // \arg PWM channel ID
+        unsigned int update) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR UDP
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EnableIt
+//* \brief Enable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableIt (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pUDP->UDP_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_DisableIt
+//* \brief Disable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableIt (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pUDP->UDP_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_SetAddress
+//* \brief Set UDP functional address
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetAddress (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char address)   // \arg new UDP address
+{
+	pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EnableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableEp (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char endpoint)   // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_DisableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableEp (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char endpoint)   // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_SetState
+//* \brief Set UDP Device state
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetState (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg new UDP address
+{
+	pUDP->UDP_GLBSTATE  &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
+	pUDP->UDP_GLBSTATE  |= flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_GetState
+//* \brief return UDP Device state
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
+	AT91PS_UDP pUDP)     // \arg pointer to a UDP controller
+{
+	return (pUDP->UDP_GLBSTATE  & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_ResetEp
+//* \brief Reset UDP endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_ResetEp ( // \return the UDP device state
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg Endpoints to be reset
+{
+	pUDP->UDP_RSTEP = flag;
+	pUDP->UDP_RSTEP = 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpStall
+//* \brief Endpoint will STALL requests
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpStall(
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char endpoint)   // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpWrite
+//* \brief Write value in the DPR
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpWrite(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned char value)     // \arg value to be written in the DPR
+{
+	pUDP->UDP_FDR[endpoint] = value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpRead
+//* \brief Return value from the DPR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpRead(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	return pUDP->UDP_FDR[endpoint];
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpEndOfWr
+//* \brief Notify the UDP that values in DPR are ready to be sent
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpEndOfWr(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpClear
+//* \brief Clear flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpClear(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned int flag)       // \arg flag to be cleared
+{
+	pUDP->UDP_CSR[endpoint] &= ~(flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpSet
+//* \brief Set flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpSet(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned int flag)       // \arg flag to be cleared
+{
+	pUDP->UDP_CSR[endpoint] |= flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpStatus
+//* \brief Return the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpStatus(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	return pUDP->UDP_CSR[endpoint];
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_GetInterruptMaskStatus
+//* \brief Return UDP Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status
+        AT91PS_UDP pUdp) // \arg  pointer to a UDP controller
+{
+        return pUdp->UDP_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_IsInterruptMasked
+//* \brief Test if UDP Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_UDP_IsInterruptMasked(
+        AT91PS_UDP pUdp,   // \arg  pointer to a UDP controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR TC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_InterruptEnable
+//* \brief Enable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptEnable(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  TC interrupt to be enabled
+{
+        pTc->TC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_InterruptDisable
+//* \brief Disable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptDisable(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  TC interrupt to be disabled
+{
+        pTc->TC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_GetInterruptMaskStatus
+//* \brief Return TC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
+        AT91PS_TC pTc) // \arg  pointer to a TC controller
+{
+        return pTc->TC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_IsInterruptMasked
+//* \brief Test if TC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_TC_IsInterruptMasked(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR CAN
+   ***************************************************************************** */
+#define	STANDARD_FORMAT 0
+#define	EXTENDED_FORMAT 1
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_InitMailboxRegisters()
+//* \brief Configure the corresponding mailbox
+//*----------------------------------------------------------------------------
+__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB	CAN_Mailbox,
+								int  			mode_reg,
+								int 			acceptance_mask_reg,
+								int  			id_reg,
+								int  			data_low_reg,
+								int  			data_high_reg,
+								int  			control_reg)
+{
+	CAN_Mailbox->CAN_MB_MCR 	= 0x0;
+	CAN_Mailbox->CAN_MB_MMR 	= mode_reg;
+	CAN_Mailbox->CAN_MB_MAM 	= acceptance_mask_reg;
+	CAN_Mailbox->CAN_MB_MID 	= id_reg;
+	CAN_Mailbox->CAN_MB_MDL 	= data_low_reg; 		
+	CAN_Mailbox->CAN_MB_MDH 	= data_high_reg;
+	CAN_Mailbox->CAN_MB_MCR 	= control_reg;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_EnableCAN()
+//* \brief 
+//*----------------------------------------------------------------------------
+__inline void AT91F_EnableCAN(
+	AT91PS_CAN pCAN)     // pointer to a CAN controller
+{
+	pCAN->CAN_MR |= AT91C_CAN_CANEN;
+
+	// Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver
+	while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DisableCAN()
+//* \brief 
+//*----------------------------------------------------------------------------
+__inline void AT91F_DisableCAN(
+	AT91PS_CAN pCAN)     // pointer to a CAN controller
+{
+	pCAN->CAN_MR &= ~AT91C_CAN_CANEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_EnableIt
+//* \brief Enable CAN interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_EnableIt (
+	AT91PS_CAN pCAN,     // pointer to a CAN controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pCAN->CAN_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_DisableIt
+//* \brief Disable CAN interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_DisableIt (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pCAN->CAN_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetStatus
+//* \brief Return CAN Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status
+	AT91PS_CAN pCAN) // pointer to a CAN controller
+{
+	return pCAN->CAN_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetInterruptMaskStatus
+//* \brief Return CAN Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status
+	AT91PS_CAN pCAN) // pointer to a CAN controller
+{
+	return pCAN->CAN_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_IsInterruptMasked
+//* \brief Test if CAN Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_IsInterruptMasked(
+        AT91PS_CAN pCAN,   // \arg  pointer to a CAN controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_IsStatusSet
+//* \brief Test if CAN Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_IsStatusSet(
+        AT91PS_CAN pCAN,   // \arg  pointer to a CAN controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_CAN_GetStatus(pCAN) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgModeReg
+//* \brief Configure the Mode Register of the CAN controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgModeReg (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+	unsigned int mode)        // mode register 
+{
+	//* Write to the MR register
+	pCAN->CAN_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetModeReg
+//* \brief Return the Mode Register of the CAN controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetModeReg (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgBaudrateReg
+//* \brief Configure the Baudrate of the CAN controller for the network
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgBaudrateReg (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+	unsigned int baudrate_cfg)
+{
+	//* Write to the BR register
+	pCAN->CAN_BR = baudrate_cfg;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetBaudrate
+//* \brief Return the Baudrate of the CAN controller for the network value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetBaudrate (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_BR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetInternalCounter
+//* \brief Return CAN Timer Regsiter Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetInternalCounter (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_TIM;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetTimestamp
+//* \brief Return CAN Timestamp Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetTimestamp (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_TIMESTP;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetErrorCounter
+//* \brief Return CAN Error Counter Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetErrorCounter (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_ECR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_InitTransferRequest
+//* \brief Request for a transfer on the corresponding mailboxes
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_InitTransferRequest (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+    unsigned int transfer_cmd)
+{
+	pCAN->CAN_TCR = transfer_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_InitAbortRequest
+//* \brief Abort the corresponding mailboxes
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_InitAbortRequest (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+    unsigned int abort_cmd)
+{
+	pCAN->CAN_ACR = abort_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageModeReg
+//* \brief Program the Message Mode Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageModeReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int mode)
+{
+	CAN_Mailbox->CAN_MB_MMR = mode;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageModeReg
+//* \brief Return the Message Mode Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageModeReg (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MMR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageIDReg
+//* \brief Program the Message ID Register
+//* \brief Version == 0 for Standard messsage, Version == 1 for Extended  
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageIDReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int id,
+    unsigned char version)
+{
+	if(version==0)	// IDvA Standard Format
+		CAN_Mailbox->CAN_MB_MID = id<<18;
+	else	// IDvB Extended Format
+		CAN_Mailbox->CAN_MB_MID = id | (1<<29);	// set MIDE bit
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageIDReg
+//* \brief Return the Message ID Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageIDReg (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MID;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageAcceptanceMaskReg
+//* \brief Program the Message Acceptance Mask Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int mask)
+{
+	CAN_Mailbox->CAN_MB_MAM = mask;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageAcceptanceMaskReg
+//* \brief Return the Message Acceptance Mask Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MAM;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetFamilyID
+//* \brief Return the Message ID Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetFamilyID (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MFID;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageCtrl
+//* \brief Request and config for a transfer on the corresponding mailbox
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageCtrlReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int message_ctrl_cmd)
+{
+	CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageStatus
+//* \brief Return CAN Mailbox Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageStatus (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MSR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageDataLow
+//* \brief Program data low value
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageDataLow (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int data)
+{
+	CAN_Mailbox->CAN_MB_MDL = data;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageDataLow
+//* \brief Return data low value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageDataLow (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MDL;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageDataHigh
+//* \brief Program data high value
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageDataHigh (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int data)
+{
+	CAN_Mailbox->CAN_MB_MDH = data;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageDataHigh
+//* \brief Return data high value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageDataHigh (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MDH;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_Open
+//* \brief Open a CAN Port
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_Open (
+        const unsigned int null)  // \arg
+{
+        /* NOT DEFINED AT THIS MOMENT */
+        return ( 0 );
+}
+/* *****************************************************************************
+                SOFTWARE API FOR ADC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_EnableIt
+//* \brief Enable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableIt (
+	AT91PS_ADC pADC,     // pointer to a ADC controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pADC->ADC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_DisableIt
+//* \brief Disable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableIt (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pADC->ADC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetStatus
+//* \brief Return ADC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
+	AT91PS_ADC pADC) // pointer to a ADC controller
+{
+	return pADC->ADC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetInterruptMaskStatus
+//* \brief Return ADC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
+	AT91PS_ADC pADC) // pointer to a ADC controller
+{
+	return pADC->ADC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_IsInterruptMasked
+//* \brief Test if ADC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsInterruptMasked(
+        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_IsStatusSet
+//* \brief Test if ADC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsStatusSet(
+        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_ADC_GetStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgModeReg
+//* \brief Configure the Mode Register of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgModeReg (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int mode)        // mode register 
+{
+	//* Write to the MR register
+	pADC->ADC_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetModeReg
+//* \brief Return the Mode Register of the ADC controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetModeReg (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgTimings
+//* \brief Configure the different necessary timings of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgTimings (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int mck_clock, // in MHz 
+	unsigned int adc_clock, // in MHz 
+	unsigned int startup_time, // in us 
+	unsigned int sample_and_hold_time)	// in ns  
+{
+	unsigned int prescal,startup,shtim;
+	
+	prescal = mck_clock/(2*adc_clock) - 1;
+	startup = adc_clock*startup_time/8 - 1;
+	shtim = adc_clock*sample_and_hold_time/1000 - 1;
+	
+	//* Write to the MR register
+	pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_EnableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableChannel (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int channel)        // mode register 
+{
+	//* Write to the CHER register
+	pADC->ADC_CHER = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_DisableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableChannel (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int channel)        // mode register 
+{
+	//* Write to the CHDR register
+	pADC->ADC_CHDR = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetChannelStatus
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetChannelStatus (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CHSR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_StartConversion
+//* \brief Software request for a analog to digital conversion 
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_StartConversion (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	pADC->ADC_CR = AT91C_ADC_START;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_SoftReset
+//* \brief Software reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_SoftReset (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	pADC->ADC_CR = AT91C_ADC_SWRST;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetLastConvertedData
+//* \brief Return the Last Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetLastConvertedData (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_LCDR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH0
+//* \brief Return the Channel 0 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR0;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH1
+//* \brief Return the Channel 1 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR1;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH2
+//* \brief Return the Channel 2 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR2;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH3
+//* \brief Return the Channel 3 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR3;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH4
+//* \brief Return the Channel 4 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR4;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH5
+//* \brief Return the Channel 5 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR5;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH6
+//* \brief Return the Channel 6 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR6;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH7
+//* \brief Return the Channel 7 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR7;	
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR AES
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_EnableIt
+//* \brief Enable AES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_EnableIt (
+	AT91PS_AES pAES,     // pointer to a AES controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pAES->AES_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_DisableIt
+//* \brief Disable AES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_DisableIt (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pAES->AES_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetStatus
+//* \brief Return AES Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status
+	AT91PS_AES pAES) // pointer to a AES controller
+{
+	return pAES->AES_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetInterruptMaskStatus
+//* \brief Return AES Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status
+	AT91PS_AES pAES) // pointer to a AES controller
+{
+	return pAES->AES_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_IsInterruptMasked
+//* \brief Test if AES Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_IsInterruptMasked(
+        AT91PS_AES pAES,   // \arg  pointer to a AES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_IsStatusSet
+//* \brief Test if AES Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_IsStatusSet(
+        AT91PS_AES pAES,   // \arg  pointer to a AES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_AES_GetStatus(pAES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_CfgModeReg
+//* \brief Configure the Mode Register of the AES controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_CfgModeReg (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned int mode)        // mode register 
+{
+	//* Write to the MR register
+	pAES->AES_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetModeReg
+//* \brief Return the Mode Register of the AES controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetModeReg (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	return pAES->AES_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_StartProcessing
+//* \brief Start Encryption or Decryption
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_StartProcessing (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	pAES->AES_CR = AT91C_AES_START;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_SoftReset
+//* \brief Reset AES
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SoftReset (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	pAES->AES_CR = AT91C_AES_SWRST;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_LoadNewSeed
+//* \brief Load New Seed in the random number generator
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_LoadNewSeed (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	pAES->AES_CR = AT91C_AES_LOADSEED;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_SetCryptoKey
+//* \brief Set Cryptographic Key x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SetCryptoKey (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pAES->AES_KEYWxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_InputData
+//* \brief Set Input Data x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_InputData (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index,
+	unsigned int indata
+	)
+{
+	pAES->AES_IDATAxR[index] = indata;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetOutputData
+//* \brief Get Output Data x
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetOutputData (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index
+	)
+{
+	return pAES->AES_ODATAxR[index];	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_SetInitializationVector
+//* \brief Set Initialization Vector (or Counter) x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SetInitializationVector (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index,
+	unsigned int initvector
+	)
+{
+	pAES->AES_IVxR[index] = initvector;	
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR TDES
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_EnableIt
+//* \brief Enable TDES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_EnableIt (
+	AT91PS_TDES pTDES,     // pointer to a TDES controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pTDES->TDES_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_DisableIt
+//* \brief Disable TDES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_DisableIt (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pTDES->TDES_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetStatus
+//* \brief Return TDES Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status
+	AT91PS_TDES pTDES) // pointer to a TDES controller
+{
+	return pTDES->TDES_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetInterruptMaskStatus
+//* \brief Return TDES Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status
+	AT91PS_TDES pTDES) // pointer to a TDES controller
+{
+	return pTDES->TDES_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_IsInterruptMasked
+//* \brief Test if TDES Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_IsInterruptMasked(
+        AT91PS_TDES pTDES,   // \arg  pointer to a TDES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_IsStatusSet
+//* \brief Test if TDES Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_IsStatusSet(
+        AT91PS_TDES pTDES,   // \arg  pointer to a TDES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_TDES_GetStatus(pTDES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_CfgModeReg
+//* \brief Configure the Mode Register of the TDES controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_CfgModeReg (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned int mode)        // mode register 
+{
+	//* Write to the MR register
+	pTDES->TDES_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetModeReg
+//* \brief Return the Mode Register of the TDES controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetModeReg (
+	AT91PS_TDES pTDES // pointer to a TDES controller
+	)
+{
+	return pTDES->TDES_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_StartProcessing
+//* \brief Start Encryption or Decryption
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_StartProcessing (
+	AT91PS_TDES pTDES // pointer to a TDES controller
+	)
+{
+	pTDES->TDES_CR = AT91C_TDES_START;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SoftReset
+//* \brief Reset TDES
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SoftReset (
+	AT91PS_TDES pTDES // pointer to a TDES controller
+	)
+{
+	pTDES->TDES_CR = AT91C_TDES_SWRST;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetCryptoKey1
+//* \brief Set Cryptographic Key 1 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey1 (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pTDES->TDES_KEY1WxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetCryptoKey2
+//* \brief Set Cryptographic Key 2 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey2 (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pTDES->TDES_KEY2WxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetCryptoKey3
+//* \brief Set Cryptographic Key 3 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey3 (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pTDES->TDES_KEY3WxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_InputData
+//* \brief Set Input Data x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_InputData (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int indata
+	)
+{
+	pTDES->TDES_IDATAxR[index] = indata;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetOutputData
+//* \brief Get Output Data x
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetOutputData (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index
+	)
+{
+	return pTDES->TDES_ODATAxR[index];	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetInitializationVector
+//* \brief Set Initialization Vector x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetInitializationVector (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int initvector
+	)
+{
+	pTDES->TDES_IVxR[index] = initvector;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  DBGU
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_CfgPIO
+//* \brief Configure PIO controllers to drive DBGU signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA27_DRXD    ) |
+		((unsigned int) AT91C_PA28_DTXD    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgPIO
+//* \brief Configure PIO controllers to drive PMC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB30_PCK2    ) |
+		((unsigned int) AT91C_PB29_PCK1    ), // Peripheral A
+		((unsigned int) AT91C_PB20_PCK0    ) |
+		((unsigned int) AT91C_PB0_PCK0    ) |
+		((unsigned int) AT91C_PB22_PCK2    ) |
+		((unsigned int) AT91C_PB21_PCK1    )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA30_PCK2    ) |
+		((unsigned int) AT91C_PA13_PCK1    ) |
+		((unsigned int) AT91C_PA27_PCK3    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_VREG_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  VREG
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  RSTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SSC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_CfgPIO
+//* \brief Configure PIO controllers to drive SSC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA25_RK      ) |
+		((unsigned int) AT91C_PA22_TK      ) |
+		((unsigned int) AT91C_PA21_TF      ) |
+		((unsigned int) AT91C_PA24_RD      ) |
+		((unsigned int) AT91C_PA26_RF      ) |
+		((unsigned int) AT91C_PA23_TD      ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  WDTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  US1
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_US1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US1_CfgPIO
+//* \brief Configure PIO controllers to drive US1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB26_RI1     ) |
+		((unsigned int) AT91C_PB24_DSR1    ) |
+		((unsigned int) AT91C_PB23_DCD1    ) |
+		((unsigned int) AT91C_PB25_DTR1    )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA7_SCK1    ) |
+		((unsigned int) AT91C_PA8_RTS1    ) |
+		((unsigned int) AT91C_PA6_TXD1    ) |
+		((unsigned int) AT91C_PA5_RXD1    ) |
+		((unsigned int) AT91C_PA9_CTS1    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  US0
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_US0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US0_CfgPIO
+//* \brief Configure PIO controllers to drive US0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA0_RXD0    ) |
+		((unsigned int) AT91C_PA4_CTS0    ) |
+		((unsigned int) AT91C_PA3_RTS0    ) |
+		((unsigned int) AT91C_PA2_SCK0    ) |
+		((unsigned int) AT91C_PA1_TXD0    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  SPI1
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI1_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SPI1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI1_CfgPIO
+//* \brief Configure PIO controllers to drive SPI1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB16_NPCS13  ) |
+		((unsigned int) AT91C_PB10_NPCS11  ) |
+		((unsigned int) AT91C_PB11_NPCS12  )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA4_NPCS13  ) |
+		((unsigned int) AT91C_PA29_NPCS13  ) |
+		((unsigned int) AT91C_PA21_NPCS10  ) |
+		((unsigned int) AT91C_PA22_SPCK1   ) |
+		((unsigned int) AT91C_PA25_NPCS11  ) |
+		((unsigned int) AT91C_PA2_NPCS11  ) |
+		((unsigned int) AT91C_PA24_MISO1   ) |
+		((unsigned int) AT91C_PA3_NPCS12  ) |
+		((unsigned int) AT91C_PA26_NPCS12  ) |
+		((unsigned int) AT91C_PA23_MOSI1   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  SPI0
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI0_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SPI0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI0_CfgPIO
+//* \brief Configure PIO controllers to drive SPI0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB13_NPCS01  ) |
+		((unsigned int) AT91C_PB17_NPCS03  ) |
+		((unsigned int) AT91C_PB14_NPCS02  )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA16_MISO0   ) |
+		((unsigned int) AT91C_PA13_NPCS01  ) |
+		((unsigned int) AT91C_PA15_NPCS03  ) |
+		((unsigned int) AT91C_PA17_MOSI0   ) |
+		((unsigned int) AT91C_PA18_SPCK0   ) |
+		((unsigned int) AT91C_PA14_NPCS02  ) |
+		((unsigned int) AT91C_PA12_NPCS00  ), // Peripheral A
+		((unsigned int) AT91C_PA7_NPCS01  ) |
+		((unsigned int) AT91C_PA9_NPCS03  ) |
+		((unsigned int) AT91C_PA8_NPCS02  )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PITC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  AIC
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_FIQ) |
+		((unsigned int) 1 << AT91C_ID_IRQ0) |
+		((unsigned int) 1 << AT91C_ID_IRQ1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_CfgPIO
+//* \brief Configure PIO controllers to drive AIC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA30_IRQ0    ) |
+		((unsigned int) AT91C_PA29_FIQ     ), // Peripheral A
+		((unsigned int) AT91C_PA14_IRQ1    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  AES
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_AES));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TWI
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TWI));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_CfgPIO
+//* \brief Configure PIO controllers to drive TWI signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA11_TWCK    ) |
+		((unsigned int) AT91C_PA10_TWD     ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  ADC
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_ADC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgPIO
+//* \brief Configure PIO controllers to drive ADC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB18_ADTRG   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH3_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH3 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH3_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB22_PWM3    ), // Peripheral A
+		((unsigned int) AT91C_PB30_PWM3    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH2_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH2_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB21_PWM2    ), // Peripheral A
+		((unsigned int) AT91C_PB29_PWM2    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH1_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB20_PWM1    ), // Peripheral A
+		((unsigned int) AT91C_PB28_PWM1    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH0_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB19_PWM0    ), // Peripheral A
+		((unsigned int) AT91C_PB27_PWM0    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RTTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  RTTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_RTTC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  UDP
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_UDP));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TDES
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TDES));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_EMAC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  EMAC
+//*----------------------------------------------------------------------------
+__inline void AT91F_EMAC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_EMAC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_EMAC_CfgPIO
+//* \brief Configure PIO controllers to drive EMAC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_EMAC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB2_ETX0    ) |
+		((unsigned int) AT91C_PB12_ETXER   ) |
+		((unsigned int) AT91C_PB16_ECOL    ) |
+		((unsigned int) AT91C_PB11_ETX3    ) |
+		((unsigned int) AT91C_PB6_ERX1    ) |
+		((unsigned int) AT91C_PB15_ERXDV   ) |
+		((unsigned int) AT91C_PB13_ERX2    ) |
+		((unsigned int) AT91C_PB3_ETX1    ) |
+		((unsigned int) AT91C_PB8_EMDC    ) |
+		((unsigned int) AT91C_PB5_ERX0    ) |
+		//((unsigned int) AT91C_PB18_EF100   ) |
+		((unsigned int) AT91C_PB14_ERX3    ) |
+		((unsigned int) AT91C_PB4_ECRS_ECRSDV) |
+		((unsigned int) AT91C_PB1_ETXEN   ) |
+		((unsigned int) AT91C_PB10_ETX2    ) |
+		((unsigned int) AT91C_PB0_ETXCK_EREFCK) |
+		((unsigned int) AT91C_PB9_EMDIO   ) |
+		((unsigned int) AT91C_PB7_ERXER   ) |
+		((unsigned int) AT91C_PB17_ERXCK   ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC0
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC0_CfgPIO
+//* \brief Configure PIO controllers to drive TC0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB23_TIOA0   ) |
+		((unsigned int) AT91C_PB24_TIOB0   ), // Peripheral A
+		((unsigned int) AT91C_PB12_TCLK0   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC1
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC1_CfgPIO
+//* \brief Configure PIO controllers to drive TC1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB25_TIOA1   ) |
+		((unsigned int) AT91C_PB26_TIOB1   ), // Peripheral A
+		((unsigned int) AT91C_PB19_TCLK1   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC2_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC2
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC2));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC2_CfgPIO
+//* \brief Configure PIO controllers to drive TC2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB28_TIOB2   ) |
+		((unsigned int) AT91C_PB27_TIOA2   ), // Peripheral A
+		0); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA15_TCLK2   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  MC
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIOA_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PIOA
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIOA_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_PIOA));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIOB_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PIOB
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIOB_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_PIOB));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  CAN
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_CAN));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgPIO
+//* \brief Configure PIO controllers to drive CAN signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA20_CANTX   ) |
+		((unsigned int) AT91C_PA19_CANRX   ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PWMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_PWMC));
+}
+
+#endif // lib_AT91SAM7X128_H
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h
new file mode 100644
index 0000000..02ee900
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h
@@ -0,0 +1,4558 @@
+//* ----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//* ----------------------------------------------------------------------------
+//* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//* ----------------------------------------------------------------------------
+//* File Name           : lib_AT91SAM7X256.h
+//* Object              : AT91SAM7X256 inlined functions
+//* Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
+//*
+//* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
+//* CVS Reference       : /lib_pmc_SAM7X.h/1.1/Tue Feb  1 08:32:10 2005//
+//* CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005//
+//* CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004//
+//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
+//* CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004//
+//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
+//* CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
+//* CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004//
+//* CVS Reference       : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
+//* CVS Reference       : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
+//* CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
+//* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
+//* CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004//
+//* CVS Reference       : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
+//* CVS Reference       : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
+//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+//* CVS Reference       : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
+//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
+//* CVS Reference       : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
+//* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+//* CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002//
+//* ----------------------------------------------------------------------------
+
+#ifndef lib_AT91SAM7X256_H
+#define lib_AT91SAM7X256_H
+
+/* *****************************************************************************
+                SOFTWARE API FOR AIC
+   ***************************************************************************** */
+#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_ConfigureIt
+//* \brief Interrupt Handler Initialization
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_ConfigureIt (
+	AT91PS_AIC pAic,  // \arg pointer to the AIC registers
+	unsigned int irq_id,     // \arg interrupt number to initialize
+	unsigned int priority,   // \arg priority to give to the interrupt
+	unsigned int src_type,   // \arg activation and sense of activation
+	void (*newHandler) (void) ) // \arg address of the interrupt handler
+{
+	unsigned int oldHandler;
+    unsigned int mask ;
+
+    oldHandler = pAic->AIC_SVR[irq_id];
+
+    mask = 0x1 << irq_id ;
+    //* Disable the interrupt on the interrupt controller
+    pAic->AIC_IDCR = mask ;
+    //* Save the interrupt handler routine pointer and the interrupt priority
+    pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
+    //* Store the Source Mode Register
+    pAic->AIC_SMR[irq_id] = src_type | priority  ;
+    //* Clear the interrupt on the interrupt controller
+    pAic->AIC_ICCR = mask ;
+
+	return oldHandler;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_EnableIt
+//* \brief Enable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_EnableIt (
+	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
+	unsigned int irq_id ) // \arg interrupt number to initialize
+{
+    //* Enable the interrupt on the interrupt controller
+    pAic->AIC_IECR = 0x1 << irq_id ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_DisableIt
+//* \brief Disable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_DisableIt (
+	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
+	unsigned int irq_id ) // \arg interrupt number to initialize
+{
+    unsigned int mask = 0x1 << irq_id;
+    //* Disable the interrupt on the interrupt controller
+    pAic->AIC_IDCR = mask ;
+    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+    pAic->AIC_ICCR = mask ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_ClearIt
+//* \brief Clear corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_ClearIt (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg interrupt number to initialize
+{
+    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+    pAic->AIC_ICCR = (0x1 << irq_id);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_AcknowledgeIt
+//* \brief Acknowledge corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_AcknowledgeIt (
+	AT91PS_AIC pAic)     // \arg pointer to the AIC registers
+{
+    pAic->AIC_EOICR = pAic->AIC_EOICR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_SetExceptionVector
+//* \brief Configure vector handler
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_SetExceptionVector (
+	unsigned int *pVector, // \arg pointer to the AIC registers
+	void (*Handler) () )   // \arg Interrupt Handler
+{
+	unsigned int oldVector = *pVector;
+
+	if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
+		*pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
+	else
+		*pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
+
+	return oldVector;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_Trig
+//* \brief Trig an IT
+//*----------------------------------------------------------------------------
+__inline void  AT91F_AIC_Trig (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg interrupt number
+{
+	pAic->AIC_ISCR = (0x1 << irq_id) ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_IsActive
+//* \brief Test if an IT is active
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_IsActive (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg Interrupt Number
+{
+	return (pAic->AIC_ISR & (0x1 << irq_id));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_IsPending
+//* \brief Test if an IT is pending
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_IsPending (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg Interrupt Number
+{
+	return (pAic->AIC_IPR & (0x1 << irq_id));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_Open
+//* \brief Set exception vectors and AIC registers to default values
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_Open(
+	AT91PS_AIC pAic,        // \arg pointer to the AIC registers
+	void (*IrqHandler) (),  // \arg Default IRQ vector exception
+	void (*FiqHandler) (),  // \arg Default FIQ vector exception
+	void (*DefaultHandler)  (), // \arg Default Handler set in ISR
+	void (*SpuriousHandler) (), // \arg Default Spurious Handler
+	unsigned int protectMode)   // \arg Debug Control Register
+{
+	int i;
+
+	// Disable all interrupts and set IVR to the default handler
+	for (i = 0; i < 32; ++i) {
+		AT91F_AIC_DisableIt(pAic, i);
+		AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);
+	}
+
+	// Set the IRQ exception vector
+	AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
+	// Set the Fast Interrupt exception vector
+	AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
+
+	pAic->AIC_SPU = (unsigned int) SpuriousHandler;
+	pAic->AIC_DCR = protectMode;
+}
+/* *****************************************************************************
+                SOFTWARE API FOR PDC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetNextRx
+//* \brief Set the next receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextRx (
+	AT91PS_PDC pPDC,     // \arg pointer to a PDC controller
+	char *address,       // \arg address to the next bloc to be received
+	unsigned int bytes)  // \arg number of bytes to be received
+{
+	pPDC->PDC_RNPR = (unsigned int) address;
+	pPDC->PDC_RNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetNextTx
+//* \brief Set the next transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextTx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be transmitted
+	unsigned int bytes)    // \arg number of bytes to be transmitted
+{
+	pPDC->PDC_TNPR = (unsigned int) address;
+	pPDC->PDC_TNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetRx
+//* \brief Set the receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetRx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be received
+	unsigned int bytes)    // \arg number of bytes to be received
+{
+	pPDC->PDC_RPR = (unsigned int) address;
+	pPDC->PDC_RCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetTx
+//* \brief Set the transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetTx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be transmitted
+	unsigned int bytes)    // \arg number of bytes to be transmitted
+{
+	pPDC->PDC_TPR = (unsigned int) address;
+	pPDC->PDC_TCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_EnableTx
+//* \brief Enable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableTx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_EnableRx
+//* \brief Enable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableRx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_DisableTx
+//* \brief Disable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableTx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_DisableRx
+//* \brief Disable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableRx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsTxEmpty
+//* \brief Test if the current transfer descriptor has been sent
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_TCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsNextTxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_TNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsRxEmpty
+//* \brief Test if the current transfer descriptor has been filled
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_RCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsNextRxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_RNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_Open
+//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Open (
+	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
+{
+    //* Disable the RX and TX PDC transfer requests
+	AT91F_PDC_DisableRx(pPDC);
+	AT91F_PDC_DisableTx(pPDC);
+
+	//* Reset all Counter register Next buffer first
+	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+    //* Enable the RX and TX PDC transfer requests
+	AT91F_PDC_EnableRx(pPDC);
+	AT91F_PDC_EnableTx(pPDC);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_Close
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Close (
+	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
+{
+    //* Disable the RX and TX PDC transfer requests
+	AT91F_PDC_DisableRx(pPDC);
+	AT91F_PDC_DisableTx(pPDC);
+
+	//* Reset all Counter register Next buffer first
+	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SendFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_SendFrame(
+	AT91PS_PDC pPDC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	if (AT91F_PDC_IsTxEmpty(pPDC)) {
+		//* Buffer and next buffer can be initialized
+		AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
+		AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
+		return 2;
+	}
+	else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
+		//* Only one buffer can be initialized
+		AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
+		return 1;
+	}
+	else {
+		//* All buffer are in use...
+		return 0;
+	}
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_ReceiveFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_ReceiveFrame (
+	AT91PS_PDC pPDC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	if (AT91F_PDC_IsRxEmpty(pPDC)) {
+		//* Buffer and next buffer can be initialized
+		AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
+		AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
+		return 2;
+	}
+	else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
+		//* Only one buffer can be initialized
+		AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
+		return 1;
+	}
+	else {
+		//* All buffer are in use...
+		return 0;
+	}
+}
+/* *****************************************************************************
+                SOFTWARE API FOR DBGU
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_InterruptEnable
+//* \brief Enable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptEnable(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  dbgu interrupt to be enabled
+{
+        pDbgu->DBGU_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_InterruptDisable
+//* \brief Disable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptDisable(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  dbgu interrupt to be disabled
+{
+        pDbgu->DBGU_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_GetInterruptMaskStatus
+//* \brief Return DBGU Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
+        AT91PS_DBGU pDbgu) // \arg  pointer to a DBGU controller
+{
+        return pDbgu->DBGU_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_IsInterruptMasked
+//* \brief Test if DBGU Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_DBGU_IsInterruptMasked(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PIO
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgPeriph
+//* \brief Enable pins to be drived by peripheral
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPeriph(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int periphAEnable,  // \arg PERIPH A to enable
+	unsigned int periphBEnable)  // \arg PERIPH B to enable
+
+{
+	pPio->PIO_ASR = periphAEnable;
+	pPio->PIO_BSR = periphBEnable;
+	pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgOutput
+//* \brief Enable PIO in output mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOutput(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int pioEnable)      // \arg PIO to be enabled
+{
+	pPio->PIO_PER = pioEnable; // Set in PIO mode
+	pPio->PIO_OER = pioEnable; // Configure in Output
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgInput
+//* \brief Enable PIO in input mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInput(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int inputEnable)      // \arg PIO to be enabled
+{
+	// Disable output
+	pPio->PIO_ODR  = inputEnable;
+	pPio->PIO_PER  = inputEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgOpendrain
+//* \brief Configure PIO in open drain
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOpendrain(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int multiDrvEnable) // \arg pio to be configured in open drain
+{
+	// Configure the multi-drive option
+	pPio->PIO_MDDR = ~multiDrvEnable;
+	pPio->PIO_MDER = multiDrvEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgPullup
+//* \brief Enable pullup on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPullup(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int pullupEnable)   // \arg enable pullup on PIO
+{
+		// Connect or not Pullup
+	pPio->PIO_PPUDR = ~pullupEnable;
+	pPio->PIO_PPUER = pullupEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgDirectDrive
+//* \brief Enable direct drive on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgDirectDrive(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int directDrive)    // \arg PIO to be configured with direct drive
+
+{
+	// Configure the Direct Drive
+	pPio->PIO_OWDR  = ~directDrive;
+	pPio->PIO_OWER  = directDrive;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgInputFilter
+//* \brief Enable input filter on input PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInputFilter(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int inputFilter)    // \arg PIO to be configured with input filter
+
+{
+	// Configure the Direct Drive
+	pPio->PIO_IFDR  = ~inputFilter;
+	pPio->PIO_IFER  = inputFilter;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInput
+//* \brief Return PIO input value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
+	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+	return pPio->PIO_PDSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInputSet
+//* \brief Test if PIO is input flag is active
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputSet(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PIO_GetInput(pPio) & flag);
+}
+
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_SetOutput
+//* \brief Set to 1 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_SetOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be set
+{
+	pPio->PIO_SODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_ClearOutput
+//* \brief Set to 0 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ClearOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be cleared
+{
+	pPio->PIO_CODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_ForceOutput
+//* \brief Force output when Direct drive option is enabled
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ForceOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be forced
+{
+	pPio->PIO_ODSR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Enable
+//* \brief Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Enable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be enabled
+{
+        pPio->PIO_PER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Disable
+//* \brief Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Disable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be disabled
+{
+        pPio->PIO_PDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetStatus
+//* \brief Return PIO Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_PSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsSet
+//* \brief Test if PIO is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputEnable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output to be enabled
+{
+        pPio->PIO_OER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputDisable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output to be disabled
+{
+        pPio->PIO_ODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputStatus
+//* \brief Return PIO Output Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_OSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOuputSet
+//* \brief Test if PIO Output is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InputFilterEnable
+//* \brief Input Filter Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio input filter to be enabled
+{
+        pPio->PIO_IFER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InputFilterDisable
+//* \brief Input Filter Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio input filter to be disabled
+{
+        pPio->PIO_IFDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInputFilterStatus
+//* \brief Return PIO Input Filter Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_IFSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInputFilterSet
+//* \brief Test if PIO Input filter is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputFilterSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputDataStatus
+//* \brief Return PIO Output Data Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status
+	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ODSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InterruptEnable
+//* \brief Enable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio interrupt to be enabled
+{
+        pPio->PIO_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InterruptDisable
+//* \brief Disable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio interrupt to be disabled
+{
+        pPio->PIO_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInterruptMaskStatus
+//* \brief Return PIO Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInterruptStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInterruptMasked
+//* \brief Test if PIO Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptMasked(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInterruptSet
+//* \brief Test if PIO Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_MultiDriverEnable
+//* \brief Multi Driver Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be enabled
+{
+        pPio->PIO_MDER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_MultiDriverDisable
+//* \brief Multi Driver Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be disabled
+{
+        pPio->PIO_MDDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetMultiDriverStatus
+//* \brief Return PIO Multi Driver Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_MDSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsMultiDriverSet
+//* \brief Test if PIO MultiDriver is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsMultiDriverSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_A_RegisterSelection
+//* \brief PIO A Register Selection
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_A_RegisterSelection(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio A register selection
+{
+        pPio->PIO_ASR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_B_RegisterSelection
+//* \brief PIO B Register Selection
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_B_RegisterSelection(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio B register selection
+{
+        pPio->PIO_BSR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Get_AB_RegisterStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ABSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsAB_RegisterSet
+//* \brief Test if PIO AB Register is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsAB_RegisterSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputWriteEnable
+//* \brief Output Write Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output write to be enabled
+{
+        pPio->PIO_OWER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputWriteDisable
+//* \brief Output Write Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output write to be disabled
+{
+        pPio->PIO_OWDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputWriteStatus
+//* \brief Return PIO Output Write Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_OWSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOutputWriteSet
+//* \brief Test if PIO OutputWrite is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputWriteSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetCfgPullup
+//* \brief Return PIO Configuration Pullup
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_PPUSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOutputDataStatusSet
+//* \brief Test if PIO Output Data Status is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputDataStatusSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsCfgPullupStatusSet
+//* \brief Test if PIO Configuration Pullup Status is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsCfgPullupStatusSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PMC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgSysClkEnableReg
+//* \brief Configure the System Clock Enable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkEnableReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	//* Write to the SCER register
+	pPMC->PMC_SCER = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgSysClkDisableReg
+//* \brief Configure the System Clock Disable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkDisableReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	//* Write to the SCDR register
+	pPMC->PMC_SCDR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetSysClkStatusReg
+//* \brief Return the System Clock Status Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
+	AT91PS_PMC pPMC // pointer to a CAN controller
+	)
+{
+	return pPMC->PMC_SCSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnablePeriphClock
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePeriphClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int periphIds)  // \arg IDs of peripherals to enable
+{
+	pPMC->PMC_PCER = periphIds;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisablePeriphClock
+//* \brief Disable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePeriphClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int periphIds)  // \arg IDs of peripherals to enable
+{
+	pPMC->PMC_PCDR = periphIds;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetPeriphClock
+//* \brief Get peripheral clock status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetPeriphClock (
+	AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+	return pPMC->PMC_PCSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_CfgMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscillatorReg (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int mode)
+{
+	pCKGR->CKGR_MOR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	return pCKGR->CKGR_MOR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_EnableMainOscillator
+//* \brief Enable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_EnableMainOscillator(
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_DisableMainOscillator
+//* \brief Disable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_DisableMainOscillator (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_CfgMainOscStartUpTime
+//* \brief Cfg MOR Register according to the main osc startup time
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscStartUpTime (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int startup_time,  // \arg main osc startup time in microsecond (us)
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
+	pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainClockFreqReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	return pCKGR->CKGR_MCFR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainClock
+//* \brief Return Main clock in Hz
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClock (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	return ((pCKGR->CKGR_MCFR  & AT91C_CKGR_MAINF) * slowClock) >> 4;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgMCKReg
+//* \brief Cfg Master Clock Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgMCKReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	pPMC->PMC_MCKR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetMCKReg
+//* \brief Return Master Clock Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMCKReg(
+	AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+	return pPMC->PMC_MCKR;
+}
+
+//*------------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetMasterClock
+//* \brief Return master clock in Hz which correponds to processor clock for ARM7
+//*------------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMasterClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	unsigned int reg = pPMC->PMC_MCKR;
+	unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
+	unsigned int pllDivider, pllMultiplier;
+
+	switch (reg & AT91C_PMC_CSS) {
+		case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
+			return slowClock / prescaler;
+		case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
+			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
+		case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
+			reg = pCKGR->CKGR_PLLR;
+			pllDivider    = (reg  & AT91C_CKGR_DIV);
+			pllMultiplier = ((reg  & AT91C_CKGR_MUL) >> 16) + 1;
+			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
+	}
+	return 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePCK (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int pck,  // \arg Peripheral clock identifier 0 .. 7
+	unsigned int mode)
+{
+	pPMC->PMC_PCKR[pck] = mode;
+	pPMC->PMC_SCER = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePCK (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int pck)  // \arg Peripheral clock identifier 0 .. 7
+{
+	pPMC->PMC_SCDR = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnableIt
+//* \brief Enable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnableIt (
+	AT91PS_PMC pPMC,     // pointer to a PMC controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pPMC->PMC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisableIt
+//* \brief Disable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisableIt (
+	AT91PS_PMC pPMC, // pointer to a PMC controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pPMC->PMC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetStatus
+//* \brief Return PMC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
+	AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+	return pPMC->PMC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetInterruptMaskStatus
+//* \brief Return PMC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
+	AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+	return pPMC->PMC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_IsInterruptMasked
+//* \brief Test if PMC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsInterruptMasked(
+        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_IsStatusSet
+//* \brief Test if PMC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsStatusSet(
+        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PMC_GetStatus(pPMC) & flag);
+}/* *****************************************************************************
+                SOFTWARE API FOR RSTC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTSoftReset
+//* \brief Start Software Reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTSoftReset(
+        AT91PS_RSTC pRSTC,
+        unsigned int reset)
+{
+	pRSTC->RSTC_RCR = (0xA5000000 | reset);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTSetMode
+//* \brief Set Reset Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTSetMode(
+        AT91PS_RSTC pRSTC,
+        unsigned int mode)
+{
+	pRSTC->RSTC_RMR = (0xA5000000 | mode);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTGetMode
+//* \brief Get Reset Mode
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTGetMode(
+        AT91PS_RSTC pRSTC)
+{
+	return (pRSTC->RSTC_RMR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTGetStatus
+//* \brief Get Reset Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTGetStatus(
+        AT91PS_RSTC pRSTC)
+{
+	return (pRSTC->RSTC_RSR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTIsSoftRstActive
+//* \brief Return !=0 if software reset is still not completed
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTIsSoftRstActive(
+        AT91PS_RSTC pRSTC)
+{
+	return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR RTTC
+   ***************************************************************************** */
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_SetRTT_TimeBase()
+//* \brief  Set the RTT prescaler according to the TimeBase in ms
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTSetTimeBase(
+        AT91PS_RTTC pRTTC,
+        unsigned int ms)
+{
+	if (ms > 2000)
+		return 1;   // AT91C_TIME_OUT_OF_RANGE
+	pRTTC->RTTC_RTMR &= ~0xFFFF;	
+	pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF);	
+	return 0;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTTSetPrescaler()
+//* \brief  Set the new prescaler value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTSetPrescaler(
+        AT91PS_RTTC pRTTC,
+        unsigned int rtpres)
+{
+	pRTTC->RTTC_RTMR &= ~0xFFFF;	
+	pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF);	
+	return (pRTTC->RTTC_RTMR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTTRestart()
+//* \brief  Restart the RTT prescaler
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTRestart(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;	
+}
+
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_SetAlarmINT()
+//* \brief  Enable RTT Alarm Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetAlarmINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_ClearAlarmINT()
+//* \brief  Disable RTT Alarm Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTClearAlarmINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_SetRttIncINT()
+//* \brief  Enable RTT INC Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetRttIncINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_ClearRttIncINT()
+//* \brief  Disable RTT INC Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTClearRttIncINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_SetAlarmValue()
+//* \brief  Set RTT Alarm Value
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetAlarmValue(
+        AT91PS_RTTC pRTTC, unsigned int alarm)
+{
+	pRTTC->RTTC_RTAR = alarm;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_GetAlarmValue()
+//* \brief  Get RTT Alarm Value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTGetAlarmValue(
+        AT91PS_RTTC pRTTC)
+{
+	return(pRTTC->RTTC_RTAR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTTGetStatus()
+//* \brief  Read the RTT status
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTGetStatus(
+        AT91PS_RTTC pRTTC)
+{
+	return(pRTTC->RTTC_RTSR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_ReadValue()
+//* \brief  Read the RTT value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTReadValue(
+        AT91PS_RTTC pRTTC)
+{
+        register volatile unsigned int val1,val2;
+	do
+	{
+		val1 = pRTTC->RTTC_RTVR;
+		val2 = pRTTC->RTTC_RTVR;
+	}	
+	while(val1 != val2);
+	return(val1);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR PITC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITInit
+//* \brief System timer init : period in µsecond, system clock freq in MHz
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITInit(
+        AT91PS_PITC pPITC,
+        unsigned int period,
+        unsigned int pit_frequency)
+{
+	pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10
+	pPITC->PITC_PIMR |= AT91C_PITC_PITEN;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITSetPIV
+//* \brief Set the PIT Periodic Interval Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITSetPIV(
+        AT91PS_PITC pPITC,
+        unsigned int piv)
+{
+	pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITEnableInt
+//* \brief Enable PIT periodic interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITEnableInt(
+        AT91PS_PITC pPITC)
+{
+	pPITC->PITC_PIMR |= AT91C_PITC_PITIEN;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITDisableInt
+//* \brief Disable PIT periodic interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITDisableInt(
+        AT91PS_PITC pPITC)
+{
+	pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetMode
+//* \brief Read PIT mode register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetMode(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PIMR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetStatus
+//* \brief Read PIT status register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetStatus(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PISR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetPIIR
+//* \brief Read PIT CPIV and PICNT without ressetting the counters
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetPIIR(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PIIR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetPIVR
+//* \brief Read System timer CPIV and PICNT without ressetting the counters
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetPIVR(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PIVR);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR WDTC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTSetMode
+//* \brief Set Watchdog Mode Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTSetMode(
+        AT91PS_WDTC pWDTC,
+        unsigned int Mode)
+{
+	pWDTC->WDTC_WDMR = Mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTRestart
+//* \brief Restart Watchdog
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTRestart(
+        AT91PS_WDTC pWDTC)
+{
+	pWDTC->WDTC_WDCR = 0xA5000001;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTSGettatus
+//* \brief Get Watchdog Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_WDTSGettatus(
+        AT91PS_WDTC pWDTC)
+{
+	return(pWDTC->WDTC_WDSR & 0x3);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTGetPeriod
+//* \brief Translate ms into Watchdog Compatible value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms)
+{
+	if ((ms < 4) || (ms > 16000))
+		return 0;
+	return((ms << 8) / 1000);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR VREG
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_VREG_Enable_LowPowerMode
+//* \brief Enable VREG Low Power Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_Enable_LowPowerMode(
+        AT91PS_VREG pVREG)
+{
+	pVREG->VREG_MR |= AT91C_VREG_PSTDBY;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_VREG_Disable_LowPowerMode
+//* \brief Disable VREG Low Power Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_Disable_LowPowerMode(
+        AT91PS_VREG pVREG)
+{
+	pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY;	
+}/* *****************************************************************************
+                SOFTWARE API FOR MC
+   ***************************************************************************** */
+
+#define AT91C_MC_CORRECT_KEY  ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_Remap
+//* \brief Make Remap
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_Remap (void)     //
+{
+    AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
+
+    pMC->MC_RCR = AT91C_MC_RCB;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_CfgModeReg
+//* \brief Configure the EFC Mode Register of the MC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_CfgModeReg (
+	AT91PS_MC pMC, // pointer to a MC controller
+	unsigned int mode)        // mode register
+{
+	// Write to the FMR register
+	pMC->MC_FMR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_GetModeReg
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetModeReg(
+	AT91PS_MC pMC) // pointer to a MC controller
+{
+	return pMC->MC_FMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_ComputeFMCN
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_ComputeFMCN(
+	int master_clock) // master clock in Hz
+{
+	return (master_clock/1000000 +2);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_PerformCmd
+//* \brief Perform EFC Command
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_PerformCmd (
+	AT91PS_MC pMC, // pointer to a MC controller
+    unsigned int transfer_cmd)
+{
+	pMC->MC_FCR = transfer_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_GetStatus
+//* \brief Return MC EFC Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetStatus(
+	AT91PS_MC pMC) // pointer to a MC controller
+{
+	return pMC->MC_FSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_IsInterruptMasked
+//* \brief Test if EFC MC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
+        AT91PS_MC pMC,   // \arg  pointer to a MC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_IsInterruptSet
+//* \brief Test if EFC MC Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptSet(
+        AT91PS_MC pMC,   // \arg  pointer to a MC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_MC_EFC_GetStatus(pMC) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR SPI
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Open
+//* \brief Open a SPI Port
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_Open (
+        const unsigned int null)  // \arg
+{
+        /* NOT DEFINED AT THIS MOMENT */
+        return ( 0 );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgCs
+//* \brief Configure SPI chip select register
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgCs (
+	AT91PS_SPI pSPI,     // pointer to a SPI controller
+	int cs,     // SPI cs number (0 to 3)
+ 	int val)   //  chip select register
+{
+	//* Write to the CSR register
+	*(pSPI->SPI_CSR + cs) = val;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_EnableIt
+//* \brief Enable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_EnableIt (
+	AT91PS_SPI pSPI,     // pointer to a SPI controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pSPI->SPI_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_DisableIt
+//* \brief Disable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_DisableIt (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pSPI->SPI_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Reset
+//* \brief Reset the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Reset (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SWRST;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Enable
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Enable (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SPIEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Disable
+//* \brief Disable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Disable (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SPIDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgMode
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgMode (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	int mode)        // mode register
+{
+	//* Write to the MR register
+	pSPI->SPI_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgPCS
+//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgPCS (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	char PCS_Device) // PCS of the Device
+{	
+ 	//* Write to the MR register
+	pSPI->SPI_MR &= 0xFFF0FFFF;
+	pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_ReceiveFrame (
+	AT91PS_SPI pSPI,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pSPI->SPI_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_SendFrame(
+	AT91PS_SPI pSPI,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pSPI->SPI_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Close
+//* \brief Close SPI: disable IT disable transfert, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Close (
+	AT91PS_SPI pSPI)     // \arg pointer to a SPI controller
+{
+    //* Reset all the Chip Select register
+    pSPI->SPI_CSR[0] = 0 ;
+    pSPI->SPI_CSR[1] = 0 ;
+    pSPI->SPI_CSR[2] = 0 ;
+    pSPI->SPI_CSR[3] = 0 ;
+
+    //* Reset the SPI mode
+    pSPI->SPI_MR = 0  ;
+
+    //* Disable all interrupts
+    pSPI->SPI_IDR = 0xFFFFFFFF ;
+
+    //* Abort the Peripheral Data Transfers
+    AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
+
+    //* Disable receiver and transmitter and stop any activity immediately
+    pSPI->SPI_CR = AT91C_SPI_SPIDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_PutChar (
+	AT91PS_SPI pSPI,
+	unsigned int character,
+             unsigned int cs_number )
+{
+    unsigned int value_for_cs;
+    value_for_cs = (~(1 << cs_number)) & 0xF;  //Place a zero among a 4 ONEs number
+    pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_GetChar (
+	const AT91PS_SPI pSPI)
+{
+    return((pSPI->SPI_RDR) & 0xFFFF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_GetInterruptMaskStatus
+//* \brief Return SPI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
+        AT91PS_SPI pSpi) // \arg  pointer to a SPI controller
+{
+        return pSpi->SPI_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_IsInterruptMasked
+//* \brief Test if SPI Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_IsInterruptMasked(
+        AT91PS_SPI pSpi,   // \arg  pointer to a SPI controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR USART
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Baudrate
+//* \brief Calculate the baudrate
+//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
+                        AT91C_US_NBSTOP_1_BIT + \
+                        AT91C_US_PAR_NONE + \
+                        AT91C_US_CHRL_8_BITS + \
+                        AT91C_US_CLKS_CLOCK )
+
+//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
+                            AT91C_US_NBSTOP_1_BIT + \
+                            AT91C_US_PAR_NONE + \
+                            AT91C_US_CHRL_8_BITS + \
+                            AT91C_US_CLKS_EXT )
+
+//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
+                       AT91C_US_USMODE_NORMAL + \
+                       AT91C_US_NBSTOP_1_BIT + \
+                       AT91C_US_PAR_NONE + \
+                       AT91C_US_CHRL_8_BITS + \
+                       AT91C_US_CLKS_CLOCK )
+
+//* SCK used Label
+#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
+
+//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
+#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
+					   		 AT91C_US_CLKS_CLOCK +\
+                       		 AT91C_US_NBSTOP_1_BIT + \
+                       		 AT91C_US_PAR_EVEN + \
+                       		 AT91C_US_CHRL_8_BITS + \
+                       		 AT91C_US_CKLO +\
+                       		 AT91C_US_OVER)
+
+//* Standard IRDA mode
+#define AT91C_US_ASYNC_IRDA_MODE (  AT91C_US_USMODE_IRDA + \
+                            AT91C_US_NBSTOP_1_BIT + \
+                            AT91C_US_PAR_NONE + \
+                            AT91C_US_CHRL_8_BITS + \
+                            AT91C_US_CLKS_CLOCK )
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Baudrate
+//* \brief Caluculate baud_value according to the main clock and the baud rate
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Baudrate (
+	const unsigned int main_clock, // \arg peripheral clock
+	const unsigned int baud_rate)  // \arg UART baudrate
+{
+	unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
+	if ((baud_value % 10) >= 5)
+		baud_value = (baud_value / 10) + 1;
+	else
+		baud_value /= 10;
+	return baud_value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetBaudrate (
+	AT91PS_USART pUSART,    // \arg pointer to a USART controller
+	unsigned int mainClock, // \arg peripheral clock
+	unsigned int speed)     // \arg UART baudrate
+{
+	//* Define the baud rate divisor register
+	pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetTimeguard
+//* \brief Set USART timeguard
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetTimeguard (
+	AT91PS_USART pUSART,    // \arg pointer to a USART controller
+	unsigned int timeguard) // \arg timeguard value
+{
+	//* Write the Timeguard Register
+	pUSART->US_TTGR = timeguard ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableIt
+//* \brief Enable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableIt (
+	AT91PS_USART pUSART, // \arg pointer to a USART controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pUSART->US_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableIt
+//* \brief Disable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableIt (
+	AT91PS_USART pUSART, // \arg pointer to a USART controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IER register
+	pUSART->US_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Configure
+//* \brief Configure USART
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Configure (
+	AT91PS_USART pUSART,     // \arg pointer to a USART controller
+	unsigned int mainClock,  // \arg peripheral clock
+	unsigned int mode ,      // \arg mode Register to be programmed
+	unsigned int baudRate ,  // \arg baudrate to be programmed
+	unsigned int timeguard ) // \arg timeguard to be programmed
+{
+    //* Disable interrupts
+    pUSART->US_IDR = (unsigned int) -1;
+
+    //* Reset receiver and transmitter
+    pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
+
+	//* Define the baud rate divisor register
+	AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
+
+	//* Write the Timeguard Register
+	AT91F_US_SetTimeguard(pUSART, timeguard);
+
+    //* Clear Transmit and Receive Counters
+    AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
+
+    //* Define the USART mode
+    pUSART->US_MR = mode  ;
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableRx
+//* \brief Enable receiving characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Enable receiver
+    pUSART->US_CR = AT91C_US_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableTx
+//* \brief Enable sending characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Enable  transmitter
+    pUSART->US_CR = AT91C_US_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ResetRx
+//* \brief Reset Receiver and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+	//* Reset receiver
+	pUSART->US_CR = AT91C_US_RSTRX;
+    //* Re-Enable receiver
+    pUSART->US_CR = AT91C_US_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ResetTx
+//* \brief Reset Transmitter and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+	//* Reset transmitter
+	pUSART->US_CR = AT91C_US_RSTTX;
+    //* Enable transmitter
+    pUSART->US_CR = AT91C_US_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableRx
+//* \brief Disable Receiver
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Disable receiver
+    pUSART->US_CR = AT91C_US_RXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableTx
+//* \brief Disable Transmitter
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Disable transmitter
+    pUSART->US_CR = AT91C_US_TXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Close
+//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Close (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Reset the baud rate divisor register
+    pUSART->US_BRGR = 0 ;
+
+    //* Reset the USART mode
+    pUSART->US_MR = 0  ;
+
+    //* Reset the Timeguard Register
+    pUSART->US_TTGR = 0;
+
+    //* Disable all interrupts
+    pUSART->US_IDR = 0xFFFFFFFF ;
+
+    //* Abort the Peripheral Data Transfers
+    AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
+
+    //* Disable receiver and transmitter and stop any activity immediately
+    pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_TxReady
+//* \brief Return 1 if a character can be written in US_THR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_TxReady (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR & AT91C_US_TXRDY);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_RxReady
+//* \brief Return 1 if a character can be read in US_RHR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_RxReady (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR & AT91C_US_RXRDY);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Error
+//* \brief Return the error flag
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Error (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR &
+    	(AT91C_US_OVRE |  // Overrun error
+    	 AT91C_US_FRAME | // Framing error
+    	 AT91C_US_PARE));  // Parity error
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_PutChar (
+	AT91PS_USART pUSART,
+	int character )
+{
+    pUSART->US_THR = (character & 0x1FF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_US_GetChar (
+	const AT91PS_USART pUSART)
+{
+    return((pUSART->US_RHR) & 0x1FF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_SendFrame(
+	AT91PS_USART pUSART,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pUSART->US_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_ReceiveFrame (
+	AT91PS_USART pUSART,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pUSART->US_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetIrdaFilter
+//* \brief Set the value of IrDa filter tregister
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetIrdaFilter (
+	AT91PS_USART pUSART,
+	unsigned char value
+)
+{
+	pUSART->US_IF = value;
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR SSC
+   ***************************************************************************** */
+//* Define the standard I2S mode configuration
+
+//* Configuration to set in the SSC Transmit Clock Mode Register
+//* Parameters :  nb_bit_by_slot : 8, 16 or 32 bits
+//* 			  nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+									   AT91C_SSC_CKS_DIV   +\
+                            		   AT91C_SSC_CKO_CONTINOUS      +\
+                            		   AT91C_SSC_CKG_NONE    +\
+                                       AT91C_SSC_START_FALL_RF +\
+                           			   AT91C_SSC_STTOUT  +\
+                            		   ((1<<16) & AT91C_SSC_STTDLY) +\
+                            		   ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
+
+
+//* Configuration to set in the SSC Transmit Frame Mode Register
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
+//* 			 nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+									(nb_bit_by_slot-1)  +\
+                            		AT91C_SSC_MSBF   +\
+                            		(((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB)  +\
+                            		(((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
+                            		AT91C_SSC_FSOS_NEGATIVE)
+
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_SetBaudrate (
+        AT91PS_SSC pSSC,        // \arg pointer to a SSC controller
+        unsigned int mainClock, // \arg peripheral clock
+        unsigned int speed)     // \arg SSC baudrate
+{
+        unsigned int baud_value;
+        //* Define the baud rate divisor register
+        if (speed == 0)
+           baud_value = 0;
+        else
+        {
+           baud_value = (unsigned int) (mainClock * 10)/(2*speed);
+           if ((baud_value % 10) >= 5)
+                  baud_value = (baud_value / 10) + 1;
+           else
+                  baud_value /= 10;
+        }
+
+        pSSC->SSC_CMR = baud_value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_Configure
+//* \brief Configure SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_Configure (
+             AT91PS_SSC pSSC,          // \arg pointer to a SSC controller
+             unsigned int syst_clock,  // \arg System Clock Frequency
+             unsigned int baud_rate,   // \arg Expected Baud Rate Frequency
+             unsigned int clock_rx,    // \arg Receiver Clock Parameters
+             unsigned int mode_rx,     // \arg mode Register to be programmed
+             unsigned int clock_tx,    // \arg Transmitter Clock Parameters
+             unsigned int mode_tx)     // \arg mode Register to be programmed
+{
+    //* Disable interrupts
+	pSSC->SSC_IDR = (unsigned int) -1;
+
+    //* Reset receiver and transmitter
+	pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
+
+    //* Define the Clock Mode Register
+	AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
+
+     //* Write the Receive Clock Mode Register
+	pSSC->SSC_RCMR =  clock_rx;
+
+     //* Write the Transmit Clock Mode Register
+	pSSC->SSC_TCMR =  clock_tx;
+
+     //* Write the Receive Frame Mode Register
+	pSSC->SSC_RFMR =  mode_rx;
+
+     //* Write the Transmit Frame Mode Register
+	pSSC->SSC_TFMR =  mode_tx;
+
+    //* Clear Transmit and Receive Counters
+	AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
+
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableRx
+//* \brief Enable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableRx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Enable receiver
+    pSSC->SSC_CR = AT91C_SSC_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableRx
+//* \brief Disable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableRx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Disable receiver
+    pSSC->SSC_CR = AT91C_SSC_RXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableTx
+//* \brief Enable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableTx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Enable  transmitter
+    pSSC->SSC_CR = AT91C_SSC_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableTx
+//* \brief Disable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableTx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Disable  transmitter
+    pSSC->SSC_CR = AT91C_SSC_TXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableIt
+//* \brief Enable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableIt (
+	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pSSC->SSC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableIt
+//* \brief Disable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableIt (
+	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pSSC->SSC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_ReceiveFrame (
+	AT91PS_SSC pSSC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pSSC->SSC_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_SendFrame(
+	AT91PS_SSC pSSC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pSSC->SSC_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_GetInterruptMaskStatus
+//* \brief Return SSC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
+        AT91PS_SSC pSsc) // \arg  pointer to a SSC controller
+{
+        return pSsc->SSC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_IsInterruptMasked
+//* \brief Test if SSC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_SSC_IsInterruptMasked(
+        AT91PS_SSC pSsc,   // \arg  pointer to a SSC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR TWI
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_EnableIt
+//* \brief Enable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_EnableIt (
+	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pTWI->TWI_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_DisableIt
+//* \brief Disable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_DisableIt (
+	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pTWI->TWI_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_Configure
+//* \brief Configure TWI in master mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI )          // \arg pointer to a TWI controller
+{
+    //* Disable interrupts
+	pTWI->TWI_IDR = (unsigned int) -1;
+
+    //* Reset peripheral
+	pTWI->TWI_CR = AT91C_TWI_SWRST;
+
+	//* Set Master mode
+	pTWI->TWI_CR = AT91C_TWI_MSEN;
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_GetInterruptMaskStatus
+//* \brief Return TWI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
+        AT91PS_TWI pTwi) // \arg  pointer to a TWI controller
+{
+        return pTwi->TWI_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_IsInterruptMasked
+//* \brief Test if TWI Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_TWI_IsInterruptMasked(
+        AT91PS_TWI pTwi,   // \arg  pointer to a TWI controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PWMC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_GetStatus
+//* \brief Return PWM Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
+	AT91PS_PWMC pPWM) // pointer to a PWM controller
+{
+	return pPWM->PWMC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_InterruptEnable
+//* \brief Enable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptEnable(
+        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  PWM interrupt to be enabled
+{
+        pPwm->PWMC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_InterruptDisable
+//* \brief Disable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptDisable(
+        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  PWM interrupt to be disabled
+{
+        pPwm->PWMC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_GetInterruptMaskStatus
+//* \brief Return PWM Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
+        AT91PS_PWMC pPwm) // \arg  pointer to a PWM controller
+{
+        return pPwm->PWMC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_IsInterruptMasked
+//* \brief Test if PWM Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsInterruptMasked(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_IsStatusSet
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsStatusSet(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PWMC_GetStatus(pPWM) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_CfgChannel
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int channelId, // \arg PWM channel ID
+        unsigned int mode, // \arg  PWM mode
+        unsigned int period, // \arg PWM period
+        unsigned int duty) // \arg PWM duty cycle
+{
+	pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
+	pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
+	pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_StartChannel
+//* \brief Enable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StartChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_ENA = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_StopChannel
+//* \brief Disable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StopChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_DIS = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_UpdateChannel
+//* \brief Update Period or Duty Cycle
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_UpdateChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int channelId, // \arg PWM channel ID
+        unsigned int update) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR UDP
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EnableIt
+//* \brief Enable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableIt (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pUDP->UDP_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_DisableIt
+//* \brief Disable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableIt (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pUDP->UDP_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_SetAddress
+//* \brief Set UDP functional address
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetAddress (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char address)   // \arg new UDP address
+{
+	pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EnableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableEp (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char endpoint)   // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_DisableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableEp (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char endpoint)   // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_SetState
+//* \brief Set UDP Device state
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetState (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg new UDP address
+{
+	pUDP->UDP_GLBSTATE  &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
+	pUDP->UDP_GLBSTATE  |= flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_GetState
+//* \brief return UDP Device state
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
+	AT91PS_UDP pUDP)     // \arg pointer to a UDP controller
+{
+	return (pUDP->UDP_GLBSTATE  & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_ResetEp
+//* \brief Reset UDP endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_ResetEp ( // \return the UDP device state
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg Endpoints to be reset
+{
+	pUDP->UDP_RSTEP = flag;
+	pUDP->UDP_RSTEP = 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpStall
+//* \brief Endpoint will STALL requests
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpStall(
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char endpoint)   // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpWrite
+//* \brief Write value in the DPR
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpWrite(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned char value)     // \arg value to be written in the DPR
+{
+	pUDP->UDP_FDR[endpoint] = value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpRead
+//* \brief Return value from the DPR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpRead(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	return pUDP->UDP_FDR[endpoint];
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpEndOfWr
+//* \brief Notify the UDP that values in DPR are ready to be sent
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpEndOfWr(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpClear
+//* \brief Clear flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpClear(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned int flag)       // \arg flag to be cleared
+{
+	pUDP->UDP_CSR[endpoint] &= ~(flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpSet
+//* \brief Set flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpSet(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned int flag)       // \arg flag to be cleared
+{
+	pUDP->UDP_CSR[endpoint] |= flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpStatus
+//* \brief Return the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpStatus(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	return pUDP->UDP_CSR[endpoint];
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_GetInterruptMaskStatus
+//* \brief Return UDP Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status
+        AT91PS_UDP pUdp) // \arg  pointer to a UDP controller
+{
+        return pUdp->UDP_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_IsInterruptMasked
+//* \brief Test if UDP Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_UDP_IsInterruptMasked(
+        AT91PS_UDP pUdp,   // \arg  pointer to a UDP controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR TC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_InterruptEnable
+//* \brief Enable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptEnable(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  TC interrupt to be enabled
+{
+        pTc->TC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_InterruptDisable
+//* \brief Disable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptDisable(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  TC interrupt to be disabled
+{
+        pTc->TC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_GetInterruptMaskStatus
+//* \brief Return TC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
+        AT91PS_TC pTc) // \arg  pointer to a TC controller
+{
+        return pTc->TC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_IsInterruptMasked
+//* \brief Test if TC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_TC_IsInterruptMasked(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR CAN
+   ***************************************************************************** */
+#define	STANDARD_FORMAT 0
+#define	EXTENDED_FORMAT 1
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_InitMailboxRegisters()
+//* \brief Configure the corresponding mailbox
+//*----------------------------------------------------------------------------
+__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB	CAN_Mailbox,
+								int  			mode_reg,
+								int 			acceptance_mask_reg,
+								int  			id_reg,
+								int  			data_low_reg,
+								int  			data_high_reg,
+								int  			control_reg)
+{
+	CAN_Mailbox->CAN_MB_MCR 	= 0x0;
+	CAN_Mailbox->CAN_MB_MMR 	= mode_reg;
+	CAN_Mailbox->CAN_MB_MAM 	= acceptance_mask_reg;
+	CAN_Mailbox->CAN_MB_MID 	= id_reg;
+	CAN_Mailbox->CAN_MB_MDL 	= data_low_reg; 		
+	CAN_Mailbox->CAN_MB_MDH 	= data_high_reg;
+	CAN_Mailbox->CAN_MB_MCR 	= control_reg;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_EnableCAN()
+//* \brief
+//*----------------------------------------------------------------------------
+__inline void AT91F_EnableCAN(
+	AT91PS_CAN pCAN)     // pointer to a CAN controller
+{
+	pCAN->CAN_MR |= AT91C_CAN_CANEN;
+
+	// Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver
+	while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DisableCAN()
+//* \brief
+//*----------------------------------------------------------------------------
+__inline void AT91F_DisableCAN(
+	AT91PS_CAN pCAN)     // pointer to a CAN controller
+{
+	pCAN->CAN_MR &= ~AT91C_CAN_CANEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_EnableIt
+//* \brief Enable CAN interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_EnableIt (
+	AT91PS_CAN pCAN,     // pointer to a CAN controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pCAN->CAN_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_DisableIt
+//* \brief Disable CAN interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_DisableIt (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pCAN->CAN_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetStatus
+//* \brief Return CAN Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status
+	AT91PS_CAN pCAN) // pointer to a CAN controller
+{
+	return pCAN->CAN_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetInterruptMaskStatus
+//* \brief Return CAN Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status
+	AT91PS_CAN pCAN) // pointer to a CAN controller
+{
+	return pCAN->CAN_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_IsInterruptMasked
+//* \brief Test if CAN Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_IsInterruptMasked(
+        AT91PS_CAN pCAN,   // \arg  pointer to a CAN controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_IsStatusSet
+//* \brief Test if CAN Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_IsStatusSet(
+        AT91PS_CAN pCAN,   // \arg  pointer to a CAN controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_CAN_GetStatus(pCAN) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgModeReg
+//* \brief Configure the Mode Register of the CAN controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgModeReg (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+	unsigned int mode)        // mode register
+{
+	//* Write to the MR register
+	pCAN->CAN_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetModeReg
+//* \brief Return the Mode Register of the CAN controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetModeReg (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgBaudrateReg
+//* \brief Configure the Baudrate of the CAN controller for the network
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgBaudrateReg (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+	unsigned int baudrate_cfg)
+{
+	//* Write to the BR register
+	pCAN->CAN_BR = baudrate_cfg;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetBaudrate
+//* \brief Return the Baudrate of the CAN controller for the network value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetBaudrate (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_BR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetInternalCounter
+//* \brief Return CAN Timer Regsiter Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetInternalCounter (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_TIM;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetTimestamp
+//* \brief Return CAN Timestamp Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetTimestamp (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_TIMESTP;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetErrorCounter
+//* \brief Return CAN Error Counter Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetErrorCounter (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_ECR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_InitTransferRequest
+//* \brief Request for a transfer on the corresponding mailboxes
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_InitTransferRequest (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+    unsigned int transfer_cmd)
+{
+	pCAN->CAN_TCR = transfer_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_InitAbortRequest
+//* \brief Abort the corresponding mailboxes
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_InitAbortRequest (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+    unsigned int abort_cmd)
+{
+	pCAN->CAN_ACR = abort_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageModeReg
+//* \brief Program the Message Mode Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageModeReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int mode)
+{
+	CAN_Mailbox->CAN_MB_MMR = mode;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageModeReg
+//* \brief Return the Message Mode Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageModeReg (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MMR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageIDReg
+//* \brief Program the Message ID Register
+//* \brief Version == 0 for Standard messsage, Version == 1 for Extended
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageIDReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int id,
+    unsigned char version)
+{
+	if(version==0)	// IDvA Standard Format
+		CAN_Mailbox->CAN_MB_MID = id<<18;
+	else	// IDvB Extended Format
+		CAN_Mailbox->CAN_MB_MID = id | (1<<29);	// set MIDE bit
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageIDReg
+//* \brief Return the Message ID Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageIDReg (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MID;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageAcceptanceMaskReg
+//* \brief Program the Message Acceptance Mask Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int mask)
+{
+	CAN_Mailbox->CAN_MB_MAM = mask;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageAcceptanceMaskReg
+//* \brief Return the Message Acceptance Mask Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MAM;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetFamilyID
+//* \brief Return the Message ID Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetFamilyID (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MFID;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageCtrl
+//* \brief Request and config for a transfer on the corresponding mailbox
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageCtrlReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int message_ctrl_cmd)
+{
+	CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageStatus
+//* \brief Return CAN Mailbox Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageStatus (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MSR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageDataLow
+//* \brief Program data low value
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageDataLow (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int data)
+{
+	CAN_Mailbox->CAN_MB_MDL = data;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageDataLow
+//* \brief Return data low value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageDataLow (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MDL;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageDataHigh
+//* \brief Program data high value
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageDataHigh (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int data)
+{
+	CAN_Mailbox->CAN_MB_MDH = data;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageDataHigh
+//* \brief Return data high value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageDataHigh (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MDH;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_Open
+//* \brief Open a CAN Port
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_Open (
+        const unsigned int null)  // \arg
+{
+        /* NOT DEFINED AT THIS MOMENT */
+        return ( 0 );
+}
+/* *****************************************************************************
+                SOFTWARE API FOR ADC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_EnableIt
+//* \brief Enable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableIt (
+	AT91PS_ADC pADC,     // pointer to a ADC controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pADC->ADC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_DisableIt
+//* \brief Disable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableIt (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pADC->ADC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetStatus
+//* \brief Return ADC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
+	AT91PS_ADC pADC) // pointer to a ADC controller
+{
+	return pADC->ADC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetInterruptMaskStatus
+//* \brief Return ADC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
+	AT91PS_ADC pADC) // pointer to a ADC controller
+{
+	return pADC->ADC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_IsInterruptMasked
+//* \brief Test if ADC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsInterruptMasked(
+        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_IsStatusSet
+//* \brief Test if ADC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsStatusSet(
+        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_ADC_GetStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgModeReg
+//* \brief Configure the Mode Register of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgModeReg (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int mode)        // mode register
+{
+	//* Write to the MR register
+	pADC->ADC_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetModeReg
+//* \brief Return the Mode Register of the ADC controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetModeReg (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgTimings
+//* \brief Configure the different necessary timings of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgTimings (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int mck_clock, // in MHz
+	unsigned int adc_clock, // in MHz
+	unsigned int startup_time, // in us
+	unsigned int sample_and_hold_time)	// in ns
+{
+	unsigned int prescal,startup,shtim;
+	
+	prescal = mck_clock/(2*adc_clock) - 1;
+	startup = adc_clock*startup_time/8 - 1;
+	shtim = adc_clock*sample_and_hold_time/1000 - 1;
+	
+	//* Write to the MR register
+	pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_EnableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableChannel (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int channel)        // mode register
+{
+	//* Write to the CHER register
+	pADC->ADC_CHER = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_DisableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableChannel (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int channel)        // mode register
+{
+	//* Write to the CHDR register
+	pADC->ADC_CHDR = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetChannelStatus
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetChannelStatus (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CHSR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_StartConversion
+//* \brief Software request for a analog to digital conversion
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_StartConversion (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	pADC->ADC_CR = AT91C_ADC_START;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_SoftReset
+//* \brief Software reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_SoftReset (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	pADC->ADC_CR = AT91C_ADC_SWRST;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetLastConvertedData
+//* \brief Return the Last Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetLastConvertedData (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_LCDR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH0
+//* \brief Return the Channel 0 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR0;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH1
+//* \brief Return the Channel 1 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR1;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH2
+//* \brief Return the Channel 2 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR2;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH3
+//* \brief Return the Channel 3 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR3;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH4
+//* \brief Return the Channel 4 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR4;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH5
+//* \brief Return the Channel 5 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR5;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH6
+//* \brief Return the Channel 6 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR6;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH7
+//* \brief Return the Channel 7 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR7;	
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR AES
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_EnableIt
+//* \brief Enable AES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_EnableIt (
+	AT91PS_AES pAES,     // pointer to a AES controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pAES->AES_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_DisableIt
+//* \brief Disable AES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_DisableIt (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pAES->AES_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetStatus
+//* \brief Return AES Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status
+	AT91PS_AES pAES) // pointer to a AES controller
+{
+	return pAES->AES_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetInterruptMaskStatus
+//* \brief Return AES Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status
+	AT91PS_AES pAES) // pointer to a AES controller
+{
+	return pAES->AES_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_IsInterruptMasked
+//* \brief Test if AES Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_IsInterruptMasked(
+        AT91PS_AES pAES,   // \arg  pointer to a AES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_IsStatusSet
+//* \brief Test if AES Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_IsStatusSet(
+        AT91PS_AES pAES,   // \arg  pointer to a AES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_AES_GetStatus(pAES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_CfgModeReg
+//* \brief Configure the Mode Register of the AES controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_CfgModeReg (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned int mode)        // mode register
+{
+	//* Write to the MR register
+	pAES->AES_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetModeReg
+//* \brief Return the Mode Register of the AES controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetModeReg (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	return pAES->AES_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_StartProcessing
+//* \brief Start Encryption or Decryption
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_StartProcessing (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	pAES->AES_CR = AT91C_AES_START;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_SoftReset
+//* \brief Reset AES
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SoftReset (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	pAES->AES_CR = AT91C_AES_SWRST;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_LoadNewSeed
+//* \brief Load New Seed in the random number generator
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_LoadNewSeed (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	pAES->AES_CR = AT91C_AES_LOADSEED;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_SetCryptoKey
+//* \brief Set Cryptographic Key x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SetCryptoKey (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pAES->AES_KEYWxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_InputData
+//* \brief Set Input Data x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_InputData (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index,
+	unsigned int indata
+	)
+{
+	pAES->AES_IDATAxR[index] = indata;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetOutputData
+//* \brief Get Output Data x
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetOutputData (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index
+	)
+{
+	return pAES->AES_ODATAxR[index];	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_SetInitializationVector
+//* \brief Set Initialization Vector (or Counter) x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SetInitializationVector (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index,
+	unsigned int initvector
+	)
+{
+	pAES->AES_IVxR[index] = initvector;	
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR TDES
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_EnableIt
+//* \brief Enable TDES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_EnableIt (
+	AT91PS_TDES pTDES,     // pointer to a TDES controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pTDES->TDES_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_DisableIt
+//* \brief Disable TDES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_DisableIt (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pTDES->TDES_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetStatus
+//* \brief Return TDES Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status
+	AT91PS_TDES pTDES) // pointer to a TDES controller
+{
+	return pTDES->TDES_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetInterruptMaskStatus
+//* \brief Return TDES Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status
+	AT91PS_TDES pTDES) // pointer to a TDES controller
+{
+	return pTDES->TDES_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_IsInterruptMasked
+//* \brief Test if TDES Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_IsInterruptMasked(
+        AT91PS_TDES pTDES,   // \arg  pointer to a TDES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_IsStatusSet
+//* \brief Test if TDES Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_IsStatusSet(
+        AT91PS_TDES pTDES,   // \arg  pointer to a TDES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_TDES_GetStatus(pTDES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_CfgModeReg
+//* \brief Configure the Mode Register of the TDES controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_CfgModeReg (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned int mode)        // mode register
+{
+	//* Write to the MR register
+	pTDES->TDES_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetModeReg
+//* \brief Return the Mode Register of the TDES controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetModeReg (
+	AT91PS_TDES pTDES // pointer to a TDES controller
+	)
+{
+	return pTDES->TDES_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_StartProcessing
+//* \brief Start Encryption or Decryption
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_StartProcessing (
+	AT91PS_TDES pTDES // pointer to a TDES controller
+	)
+{
+	pTDES->TDES_CR = AT91C_TDES_START;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SoftReset
+//* \brief Reset TDES
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SoftReset (
+	AT91PS_TDES pTDES // pointer to a TDES controller
+	)
+{
+	pTDES->TDES_CR = AT91C_TDES_SWRST;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetCryptoKey1
+//* \brief Set Cryptographic Key 1 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey1 (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pTDES->TDES_KEY1WxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetCryptoKey2
+//* \brief Set Cryptographic Key 2 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey2 (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pTDES->TDES_KEY2WxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetCryptoKey3
+//* \brief Set Cryptographic Key 3 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey3 (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pTDES->TDES_KEY3WxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_InputData
+//* \brief Set Input Data x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_InputData (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int indata
+	)
+{
+	pTDES->TDES_IDATAxR[index] = indata;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetOutputData
+//* \brief Get Output Data x
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetOutputData (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index
+	)
+{
+	return pTDES->TDES_ODATAxR[index];	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetInitializationVector
+//* \brief Set Initialization Vector x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetInitializationVector (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int initvector
+	)
+{
+	pTDES->TDES_IVxR[index] = initvector;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  DBGU
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_CfgPIO
+//* \brief Configure PIO controllers to drive DBGU signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA27_DRXD    ) |
+		((unsigned int) AT91C_PA28_DTXD    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgPIO
+//* \brief Configure PIO controllers to drive PMC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB30_PCK2    ) |
+		((unsigned int) AT91C_PB29_PCK1    ), // Peripheral A
+		((unsigned int) AT91C_PB20_PCK0    ) |
+		((unsigned int) AT91C_PB0_PCK0    ) |
+		((unsigned int) AT91C_PB22_PCK2    ) |
+		((unsigned int) AT91C_PB21_PCK1    )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA30_PCK2    ) |
+		((unsigned int) AT91C_PA13_PCK1    ) |
+		((unsigned int) AT91C_PA27_PCK3    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_VREG_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  VREG
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  RSTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SSC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_CfgPIO
+//* \brief Configure PIO controllers to drive SSC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA25_RK      ) |
+		((unsigned int) AT91C_PA22_TK      ) |
+		((unsigned int) AT91C_PA21_TF      ) |
+		((unsigned int) AT91C_PA24_RD      ) |
+		((unsigned int) AT91C_PA26_RF      ) |
+		((unsigned int) AT91C_PA23_TD      ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  WDTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  US1
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_US1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US1_CfgPIO
+//* \brief Configure PIO controllers to drive US1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB26_RI1     ) |
+		((unsigned int) AT91C_PB24_DSR1    ) |
+		((unsigned int) AT91C_PB23_DCD1    ) |
+		((unsigned int) AT91C_PB25_DTR1    )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA7_SCK1    ) |
+		((unsigned int) AT91C_PA8_RTS1    ) |
+		((unsigned int) AT91C_PA6_TXD1    ) |
+		((unsigned int) AT91C_PA5_RXD1    ) |
+		((unsigned int) AT91C_PA9_CTS1    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  US0
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_US0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US0_CfgPIO
+//* \brief Configure PIO controllers to drive US0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA0_RXD0    ) |
+		((unsigned int) AT91C_PA4_CTS0    ) |
+		((unsigned int) AT91C_PA3_RTS0    ) |
+		((unsigned int) AT91C_PA2_SCK0    ) |
+		((unsigned int) AT91C_PA1_TXD0    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  SPI1
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI1_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SPI1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI1_CfgPIO
+//* \brief Configure PIO controllers to drive SPI1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB16_NPCS13  ) |
+		((unsigned int) AT91C_PB10_NPCS11  ) |
+		((unsigned int) AT91C_PB11_NPCS12  )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA4_NPCS13  ) |
+		((unsigned int) AT91C_PA29_NPCS13  ) |
+		((unsigned int) AT91C_PA21_NPCS10  ) |
+		((unsigned int) AT91C_PA22_SPCK1   ) |
+		((unsigned int) AT91C_PA25_NPCS11  ) |
+		((unsigned int) AT91C_PA2_NPCS11  ) |
+		((unsigned int) AT91C_PA24_MISO1   ) |
+		((unsigned int) AT91C_PA3_NPCS12  ) |
+		((unsigned int) AT91C_PA26_NPCS12  ) |
+		((unsigned int) AT91C_PA23_MOSI1   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  SPI0
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI0_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SPI0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI0_CfgPIO
+//* \brief Configure PIO controllers to drive SPI0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB13_NPCS01  ) |
+		((unsigned int) AT91C_PB17_NPCS03  ) |
+		((unsigned int) AT91C_PB14_NPCS02  )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA16_MISO0   ) |
+		((unsigned int) AT91C_PA13_NPCS01  ) |
+		((unsigned int) AT91C_PA15_NPCS03  ) |
+		((unsigned int) AT91C_PA17_MOSI0   ) |
+		((unsigned int) AT91C_PA18_SPCK0   ) |
+		((unsigned int) AT91C_PA14_NPCS02  ) |
+		((unsigned int) AT91C_PA12_NPCS00  ), // Peripheral A
+		((unsigned int) AT91C_PA7_NPCS01  ) |
+		((unsigned int) AT91C_PA9_NPCS03  ) |
+		((unsigned int) AT91C_PA8_NPCS02  )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PITC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  AIC
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_FIQ) |
+		((unsigned int) 1 << AT91C_ID_IRQ0) |
+		((unsigned int) 1 << AT91C_ID_IRQ1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_CfgPIO
+//* \brief Configure PIO controllers to drive AIC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA30_IRQ0    ) |
+		((unsigned int) AT91C_PA29_FIQ     ), // Peripheral A
+		((unsigned int) AT91C_PA14_IRQ1    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  AES
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_AES));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TWI
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TWI));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_CfgPIO
+//* \brief Configure PIO controllers to drive TWI signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA11_TWCK    ) |
+		((unsigned int) AT91C_PA10_TWD     ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  ADC
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_ADC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgPIO
+//* \brief Configure PIO controllers to drive ADC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB18_ADTRG   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH3_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH3 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH3_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB22_PWM3    ), // Peripheral A
+		((unsigned int) AT91C_PB30_PWM3    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH2_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH2_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB21_PWM2    ), // Peripheral A
+		((unsigned int) AT91C_PB29_PWM2    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH1_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB20_PWM1    ), // Peripheral A
+		((unsigned int) AT91C_PB28_PWM1    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH0_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB19_PWM0    ), // Peripheral A
+		((unsigned int) AT91C_PB27_PWM0    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RTTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  RTTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_RTTC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  UDP
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_UDP));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TDES
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TDES));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_EMAC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  EMAC
+//*----------------------------------------------------------------------------
+__inline void AT91F_EMAC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_EMAC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_EMAC_CfgPIO
+//* \brief Configure PIO controllers to drive EMAC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_EMAC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB2_ETX0    ) |
+		((unsigned int) AT91C_PB12_ETXER   ) |
+		((unsigned int) AT91C_PB16_ECOL    ) |
+		((unsigned int) AT91C_PB11_ETX3    ) |
+		((unsigned int) AT91C_PB6_ERX1    ) |
+		((unsigned int) AT91C_PB15_ERXDV   ) |
+		((unsigned int) AT91C_PB13_ERX2    ) |
+		((unsigned int) AT91C_PB3_ETX1    ) |
+		((unsigned int) AT91C_PB8_EMDC    ) |
+		((unsigned int) AT91C_PB5_ERX0    ) |
+		//((unsigned int) AT91C_PB18_EF100   ) |
+		((unsigned int) AT91C_PB14_ERX3    ) |
+		((unsigned int) AT91C_PB4_ECRS_ECRSDV) |
+		((unsigned int) AT91C_PB1_ETXEN   ) |
+		((unsigned int) AT91C_PB10_ETX2    ) |
+		((unsigned int) AT91C_PB0_ETXCK_EREFCK) |
+		((unsigned int) AT91C_PB9_EMDIO   ) |
+		((unsigned int) AT91C_PB7_ERXER   ) |
+		((unsigned int) AT91C_PB17_ERXCK   ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC0
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC0_CfgPIO
+//* \brief Configure PIO controllers to drive TC0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB23_TIOA0   ) |
+		((unsigned int) AT91C_PB24_TIOB0   ), // Peripheral A
+		((unsigned int) AT91C_PB12_TCLK0   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC1
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC1_CfgPIO
+//* \brief Configure PIO controllers to drive TC1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB25_TIOA1   ) |
+		((unsigned int) AT91C_PB26_TIOB1   ), // Peripheral A
+		((unsigned int) AT91C_PB19_TCLK1   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC2_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC2
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC2));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC2_CfgPIO
+//* \brief Configure PIO controllers to drive TC2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB28_TIOB2   ) |
+		((unsigned int) AT91C_PB27_TIOA2   ), // Peripheral A
+		0); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA15_TCLK2   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  MC
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIOA_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PIOA
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIOA_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_PIOA));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIOB_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PIOB
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIOB_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_PIOB));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  CAN
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_CAN));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgPIO
+//* \brief Configure PIO controllers to drive CAN signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA20_CANTX   ) |
+		((unsigned int) AT91C_PA19_CANRX   ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PWMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_PWMC));
+}
+
+#endif // lib_AT91SAM7X256_H
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/port.c
new file mode 100644
index 0000000..56842e4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/port.c
@@ -0,0 +1,259 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the Atmel ARM7 port.
+ *----------------------------------------------------------*/
+
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup the initial stack. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+
+/* Constants required to setup the PIT. */
+#define portPIT_CLOCK_DIVISOR			( ( uint32_t ) 16 )
+#define portPIT_COUNTER_VALUE			( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
+
+
+#define portINT_LEVEL_SENSITIVE  0
+#define portPIT_ENABLE      	( ( uint16_t ) 0x1 << 24 )
+#define portPIT_INT_ENABLE     	( ( uint16_t ) 0x1 << 25 )
+/*-----------------------------------------------------------*/
+
+/* Setup the PIT to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* ulCriticalNesting will get set to zero when the first task starts.  It
+cannot be initialised to 0 as this will cause interrupts to be enabled
+during the kernel initialisation process. */
+uint32_t ulCriticalNesting = ( uint32_t ) 9999;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* To ensure asserts in tasks.c don't fail, although in this case the assert
+	is not really required. */
+	pxTopOfStack--;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The status register is set for system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+	
+	if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}	
+	
+	pxTopOfStack--;
+
+	/* Interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+
+	return pxTopOfStack;	
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 0
+
+	/* The cooperative scheduler requires a normal IRQ service routine to
+	simply increment the system tick. */
+	static __arm __irq void vPortNonPreemptiveTick( void );
+	static __arm __irq void vPortNonPreemptiveTick( void )
+	{
+		uint32_t ulDummy;
+		
+		/* Increment the tick count - which may wake some tasks but as the
+		preemptive scheduler is not being used any woken task is not given
+		processor time no matter what its priority. */
+		xTaskIncrementTick();
+		
+		/* Clear the PIT interrupt. */
+		ulDummy = AT91C_BASE_PITC->PITC_PIVR;
+		
+		/* End the interrupt in the AIC. */
+		AT91C_BASE_AIC->AIC_EOICR = ulDummy;
+	}
+
+#else
+
+	/* Currently the IAR port requires the preemptive tick function to be
+	defined in an asm file. */
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+AT91PS_PITC pxPIT = AT91C_BASE_PITC;
+
+	/* Setup the AIC for PIT interrupts.  The interrupt routine chosen depends
+	on whether the preemptive or cooperative scheduler is being used. */
+	#if configUSE_PREEMPTION == 0
+
+		AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortNonPreemptiveTick );
+
+	#else
+		
+		extern void ( vPortPreemptiveTick )( void );
+		AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortPreemptiveTick );
+
+	#endif
+
+	/* Configure the PIT period. */
+	pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
+
+	/* Enable the interrupt.  Global interrupts are disables at this point so
+	this is safe. */
+	AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_SYS );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts first! */
+	__disable_interrupt();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			__enable_interrupt();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portasm.s79 b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portasm.s79
new file mode 100644
index 0000000..9af364f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portasm.s79
@@ -0,0 +1,88 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+		RSEG ICODE:CODE
+		CODE32
+
+	EXTERN vTaskSwitchContext
+	EXTERN xTaskIncrementTick
+
+	PUBLIC vPortYieldProcessor
+	PUBLIC vPortPreemptiveTick
+	PUBLIC vPortStartFirstTask
+
+#include "AT91SAM7S64_inc.h"
+#include "ISR_Support.h"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Starting the first task is just a matter of restoring the context that
+; was created by pxPortInitialiseStack().
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortStartFirstTask:
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Manual context switch function.  This is the SWI hander.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortYieldProcessor:
+	ADD		LR, LR, #4			; Add 4 to the LR to make the LR appear exactly
+								; as if the context was saved during and IRQ
+								; handler.
+
+	portSAVE_CONTEXT			; Save the context of the current task...
+	LDR R0, =vTaskSwitchContext	; before selecting the next task to execute.
+	mov     lr, pc
+	BX R0
+	portRESTORE_CONTEXT			; Restore the context of the selected task.
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Preemptive context switch function.  This will only ever get installed if
+; portUSE_PREEMPTION is set to 1 in portmacro.h.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortPreemptiveTick:
+	portSAVE_CONTEXT			; Save the context of the current task.
+
+	LDR R0, =xTaskIncrementTick ; Increment the tick count - this may wake a task.
+	mov lr, pc
+	BX R0
+
+	CMP R0, #0
+	BEQ SkipContextSwitch
+	LDR R0, =vTaskSwitchContext ; Select the next task to execute.
+	mov lr, pc
+	BX R0
+SkipContextSwitch
+	LDR	R14, =AT91C_BASE_PITC	; Clear the PIT interrupt
+	LDR	R0, [R14, #PITC_PIVR ]
+
+	LDR R14, =AT91C_BASE_AIC	; Mark the End of Interrupt on the AIC
+    STR	R14, [R14, #AIC_EOICR]
+
+	portRESTORE_CONTEXT			; Restore the context of the selected task.
+
+
+	END
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portmacro.h
new file mode 100644
index 0000000..5fdf4f2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portmacro.h
@@ -0,0 +1,111 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+#define portYIELD()					asm ( "SWI 0" )
+#define portNOP()					asm ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+__arm __interwork void vPortDisableInterruptsFromThumb( void );
+__arm __interwork void vPortEnableInterruptsFromThumb( void );
+__arm __interwork void vPortEnterCritical( void );
+__arm __interwork void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()	__disable_interrupt()
+#define portENABLE_INTERRUPTS()		__enable_interrupt()
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+#define portEND_SWITCHING_ISR( xSwitchRequired ) 	\
+{													\
+extern void vTaskSwitchContext( void );				\
+													\
+	if( xSwitchRequired ) 							\
+	{												\
+		vTaskSwitchContext();						\
+	}												\
+}
+/*-----------------------------------------------------------*/
+
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/ISR_Support.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/ISR_Support.h
new file mode 100644
index 0000000..4a32f39
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/ISR_Support.h
@@ -0,0 +1,78 @@
+	EXTERN pxCurrentTCB
+	EXTERN ulCriticalNesting
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Context save and restore macro definitions
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+portSAVE_CONTEXT MACRO
+
+	; Push R0 as we are going to use the register. 					
+	STMDB	SP!, {R0}
+
+	; Set R0 to point to the task stack pointer. 					
+	STMDB	SP, {SP}^
+	NOP
+	SUB		SP, SP, #4
+	LDMIA	SP!, {R0}
+
+	; Push the return address onto the stack. 						
+	STMDB	R0!, {LR}
+
+	; Now we have saved LR we can use it instead of R0. 				
+	MOV		LR, R0
+
+	; Pop R0 so we can save it onto the system mode stack. 			
+	LDMIA	SP!, {R0}
+
+	; Push all the system mode registers onto the task stack. 		
+	STMDB	LR, {R0-LR}^
+	NOP
+	SUB		LR, LR, #60
+
+	; Push the SPSR onto the task stack. 							
+	MRS		R0, SPSR
+	STMDB	LR!, {R0}
+
+	LDR		R0, =ulCriticalNesting 
+	LDR		R0, [R0]
+	STMDB	LR!, {R0}
+
+	; Store the new top of stack for the task. 						
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	STR		LR, [R0]
+
+	ENDM
+
+
+portRESTORE_CONTEXT MACRO
+
+	; Set the LR to the task stack. 									
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	LDR		LR, [R0]
+
+	; The critical nesting depth is the first item on the stack. 	
+	; Load it into the ulCriticalNesting variable. 					
+	LDR		R0, =ulCriticalNesting
+	LDMFD	LR!, {R1}
+	STR		R1, [R0]
+
+	; Get the SPSR from the stack. 									
+	LDMFD	LR!, {R0}
+	MSR		SPSR_cxsf, R0
+
+	; Restore all system mode registers for the task. 				
+	LDMFD	LR, {R0-R14}^
+	NOP
+
+	; Restore the return address. 									
+	LDR		LR, [LR, #+60]
+
+	; And return - correcting the offset in the LR to obtain the 	
+	; correct address. 												
+	SUBS	PC, LR, #4
+
+	ENDM
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/port.c
new file mode 100644
index 0000000..54361b9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/port.c
@@ -0,0 +1,256 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the Atmel ARM7 port.
+ *----------------------------------------------------------*/
+
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Hardware includes. */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/*-----------------------------------------------------------*/
+
+/* Constants required to setup the initial stack. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+
+/* Constants required to setup the PIT. */
+#define port1MHz_IN_Hz 					( 1000000ul )
+#define port1SECOND_IN_uS				( 1000000.0 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
+
+
+#define portINT_LEVEL_SENSITIVE  0
+#define portPIT_ENABLE      	( ( uint16_t ) 0x1 << 24 )
+#define portPIT_INT_ENABLE     	( ( uint16_t ) 0x1 << 25 )
+/*-----------------------------------------------------------*/
+
+/* Setup the PIT to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* The PIT interrupt handler - the RTOS tick. */
+static void vPortTickISR( void );
+
+/* ulCriticalNesting will get set to zero when the first task starts.  It
+cannot be initialised to 0 as this will cause interrupts to be enabled
+during the kernel initialisation process. */
+uint32_t ulCriticalNesting = ( uint32_t ) 9999;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* To ensure asserts in tasks.c don't fail, although in this case the assert
+	is not really required. */
+	pxTopOfStack--;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The status register is set for system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+	
+	#ifdef THUMB_INTERWORK
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+	#endif
+	
+	pxTopOfStack--;
+
+	/* Interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+
+	return pxTopOfStack;	
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+static __arm void vPortTickISR( void )
+{
+volatile uint32_t ulDummy;
+	
+	/* Increment the tick count - which may wake some tasks but as the
+	preemptive scheduler is not being used any woken task is not given
+	processor time no matter what its priority. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		vTaskSwitchContext();
+	}
+		
+	/* Clear the PIT interrupt. */
+	ulDummy = AT91C_BASE_PITC->PITC_PIVR;
+	
+	/* To remove compiler warning. */
+	( void ) ulDummy;
+	
+	/* The AIC is cleared in the asm wrapper, outside of this function. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+const uint32_t ulPeriodIn_uS = ( 1.0 / ( double ) configTICK_RATE_HZ ) * port1SECOND_IN_uS;
+
+	/* Setup the PIT for the required frequency. */
+	PIT_Init( ulPeriodIn_uS, BOARD_MCK / port1MHz_IN_Hz );
+	
+	/* Setup the PIT interrupt. */
+	AIC_DisableIT( AT91C_ID_SYS );
+	AIC_ConfigureIT( AT91C_ID_SYS, AT91C_AIC_PRIOR_LOWEST, vPortTickISR );
+	AIC_EnableIT( AT91C_ID_SYS );
+	PIT_EnableIT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts first! */
+	__disable_irq();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			__enable_irq();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portasm.s79 b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portasm.s79
new file mode 100644
index 0000000..d5ac7eb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portasm.s79
@@ -0,0 +1,34 @@
+		RSEG ICODE:CODE
+		CODE32
+
+	EXTERN vTaskSwitchContext
+
+	PUBLIC vPortYieldProcessor
+	PUBLIC vPortStartFirstTask
+
+#include "ISR_Support.h"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Starting the first task is just a matter of restoring the context that
+; was created by pxPortInitialiseStack().
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortStartFirstTask:
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Manual context switch function.  This is the SWI hander.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortYieldProcessor:
+	ADD		LR, LR, #4			; Add 4 to the LR to make the LR appear exactly
+								; as if the context was saved during and IRQ
+								; handler.
+								
+	portSAVE_CONTEXT			; Save the context of the current task...
+	LDR R0, =vTaskSwitchContext	; before selecting the next task to execute.
+	mov     lr, pc
+	BX R0
+	portRESTORE_CONTEXT			; Restore the context of the selected task.
+
+
+	END
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portmacro.h
new file mode 100644
index 0000000..7fe236d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portmacro.h
@@ -0,0 +1,114 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+#define portYIELD()					asm ( "SWI 0" )
+#define portNOP()					asm ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+__arm __interwork void vPortDisableInterruptsFromThumb( void );
+__arm __interwork void vPortEnableInterruptsFromThumb( void );
+__arm __interwork void vPortEnterCritical( void );
+__arm __interwork void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()	__disable_irq()
+#define portENABLE_INTERRUPTS()		__enable_irq()
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+#define portEND_SWITCHING_ISR( xSwitchRequired ) 	\
+{													\
+extern void vTaskSwitchContext( void );				\
+													\
+	if( xSwitchRequired ) 							\
+	{												\
+		vTaskSwitchContext();						\
+	}												\
+}
+/*-----------------------------------------------------------*/
+
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/LPC2000/ISR_Support.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/LPC2000/ISR_Support.h
new file mode 100644
index 0000000..18e0b3b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/LPC2000/ISR_Support.h
@@ -0,0 +1,105 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	EXTERN pxCurrentTCB
+	EXTERN ulCriticalNesting
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Context save and restore macro definitions
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+portSAVE_CONTEXT MACRO
+
+	; Push R0 as we are going to use the register.
+	STMDB	SP!, {R0}
+
+	; Set R0 to point to the task stack pointer.
+	STMDB	SP, {SP}^
+	NOP
+	SUB		SP, SP, #4
+	LDMIA	SP!, {R0}
+
+	; Push the return address onto the stack.
+	STMDB	R0!, {LR}
+
+	; Now we have saved LR we can use it instead of R0.
+	MOV		LR, R0
+
+	; Pop R0 so we can save it onto the system mode stack.
+	LDMIA	SP!, {R0}
+
+	; Push all the system mode registers onto the task stack.
+	STMDB	LR, {R0-LR}^
+	NOP
+	SUB		LR, LR, #60
+
+	; Push the SPSR onto the task stack.
+	MRS		R0, SPSR
+	STMDB	LR!, {R0}
+
+	LDR		R0, =ulCriticalNesting
+	LDR		R0, [R0]
+	STMDB	LR!, {R0}
+
+	; Store the new top of stack for the task.
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	STR		LR, [R0]
+
+	ENDM
+
+
+portRESTORE_CONTEXT MACRO
+
+	; Set the LR to the task stack.
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	LDR		LR, [R0]
+
+	; The critical nesting depth is the first item on the stack.
+	; Load it into the ulCriticalNesting variable.
+	LDR		R0, =ulCriticalNesting
+	LDMFD	LR!, {R1}
+	STR		R1, [R0]
+
+	; Get the SPSR from the stack.
+	LDMFD	LR!, {R0}
+	MSR		SPSR_cxsf, R0
+
+	; Restore all system mode registers for the task.
+	LDMFD	LR, {R0-R14}^
+	NOP
+
+	; Restore the return address.
+	LDR		LR, [LR, #+60]
+
+	; And return - correcting the offset in the LR to obtain the
+	; correct address.
+	SUBS	PC, LR, #4
+
+	ENDM
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/LPC2000/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/LPC2000/port.c
new file mode 100644
index 0000000..371a74a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/LPC2000/port.c
@@ -0,0 +1,317 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the Philips ARM7 port.
+ *----------------------------------------------------------*/
+
+/*
+	Changes from V3.2.2
+
+	+ Bug fix - The prescale value for the timer setup is now written to T0PR
+	  instead of T0PC.  This bug would have had no effect unless a prescale
+	  value was actually used.
+*/
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup the tick ISR. */
+#define portENABLE_TIMER			( ( uint8_t ) 0x01 )
+#define portPRESCALE_VALUE			0x00
+#define portINTERRUPT_ON_MATCH		( ( uint32_t ) 0x01 )
+#define portRESET_COUNT_ON_MATCH	( ( uint32_t ) 0x02 )
+
+/* Constants required to setup the initial stack. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+
+/* Constants required to setup the PIT. */
+#define portPIT_CLOCK_DIVISOR			( ( uint32_t ) 16 )
+#define portPIT_COUNTER_VALUE			( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
+
+/* Constants required to handle interrupts. */
+#define portTIMER_MATCH_ISR_BIT		( ( uint8_t ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT		( ( uint32_t ) 0 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
+
+
+#define portINT_LEVEL_SENSITIVE  0
+#define portPIT_ENABLE      	( ( uint16_t ) 0x1 << 24 )
+#define portPIT_INT_ENABLE     	( ( uint16_t ) 0x1 << 25 )
+
+/* Constants required to setup the VIC for the tick ISR. */
+#define portTIMER_VIC_CHANNEL		( ( uint32_t ) 0x0004 )
+#define portTIMER_VIC_CHANNEL_BIT	( ( uint32_t ) 0x0010 )
+#define portTIMER_VIC_ENABLE		( ( uint32_t ) 0x0020 )
+
+/*-----------------------------------------------------------*/
+
+/* Setup the PIT to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* ulCriticalNesting will get set to zero when the first task starts.  It
+cannot be initialised to 0 as this will cause interrupts to be enabled
+during the kernel initialisation process. */
+uint32_t ulCriticalNesting = ( uint32_t ) 9999;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The status register is set for system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+	
+	if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+	
+	pxTopOfStack--;
+
+	/* Interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+
+	return pxTopOfStack;	
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 0
+
+	/* The cooperative scheduler requires a normal IRQ service routine to
+	simply increment the system tick. */
+	static __arm __irq void vPortNonPreemptiveTick( void );
+	static __arm __irq void vPortNonPreemptiveTick( void )
+	{
+		/* Increment the tick count - which may wake some tasks but as the
+		preemptive scheduler is not being used any woken task is not given
+		processor time no matter what its priority. */
+		xTaskIncrementTick();
+		
+		/* Ready for the next interrupt. */
+		T0IR = portTIMER_MATCH_ISR_BIT;
+		VICVectAddr = portCLEAR_VIC_INTERRUPT;
+	}
+
+#else
+
+	/* This function is called from an asm wrapper, so does not require the __irq
+	keyword. */
+	void vPortPreemptiveTick( void );
+	void vPortPreemptiveTick( void )
+	{
+		/* Increment the tick counter. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{	
+			/* The new tick value might unblock a task.  Ensure the highest task that
+			is ready to execute is the task that will execute when the tick ISR
+			exits. */
+			vTaskSwitchContext();
+		}
+	
+		/* Ready for the next interrupt. */
+		T0IR = portTIMER_MATCH_ISR_BIT;
+		VICVectAddr = portCLEAR_VIC_INTERRUPT;
+	}
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+uint32_t ulCompareMatch;
+
+	/* A 1ms tick does not require the use of the timer prescale.  This is
+	defaulted to zero but can be used if necessary. */
+	T0PR = portPRESCALE_VALUE;
+
+	/* Calculate the match value required for our wanted tick rate. */
+	ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+	/* Protect against divide by zero.  Using an if() statement still results
+	in a warning - hence the #if. */
+	#if portPRESCALE_VALUE != 0
+	{
+		ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
+	}
+	#endif
+
+	T0MR0 = ulCompareMatch;
+
+	/* Generate tick with timer 0 compare match. */
+	T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
+
+	/* Setup the VIC for the timer. */
+	VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
+	VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
+	
+	/* The ISR installed depends on whether the preemptive or cooperative
+	scheduler is being used. */
+	#if configUSE_PREEMPTION == 1
+	{	
+		extern void ( vPortPreemptiveTickEntry )( void );
+
+		VICVectAddr0 = ( uint32_t ) vPortPreemptiveTickEntry;
+	}
+	#else
+	{
+		extern void ( vNonPreemptiveTick )( void );
+
+		VICVectAddr0 = ( int32_t ) vPortNonPreemptiveTick;
+	}
+	#endif
+
+	VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
+
+	/* Start the timer - interrupts are disabled when this function is called
+	so it is okay to do this here. */
+	T0TCR = portENABLE_TIMER;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts first! */
+	__disable_interrupt();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			__enable_interrupt();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/LPC2000/portasm.s79 b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/LPC2000/portasm.s79
new file mode 100644
index 0000000..6036e3e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/LPC2000/portasm.s79
@@ -0,0 +1,76 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+		RSEG ICODE:CODE
+		CODE32
+
+	EXTERN vTaskSwitchContext
+	EXTERN vPortPreemptiveTick
+
+	PUBLIC vPortPreemptiveTickEntry
+	PUBLIC vPortYieldProcessor
+	PUBLIC vPortStartFirstTask
+
+#include "FreeRTOSConfig.h"
+#include "ISR_Support.h"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Starting the first task is just a matter of restoring the context that
+; was created by pxPortInitialiseStack().
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortStartFirstTask:
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Manual context switch function.  This is the SWI hander.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortYieldProcessor:
+	ADD		LR, LR, #4			; Add 4 to the LR to make the LR appear exactly
+								; as if the context was saved during and IRQ
+								; handler.
+
+	portSAVE_CONTEXT			; Save the context of the current task...
+	LDR R0, =vTaskSwitchContext	; before selecting the next task to execute.
+	mov     lr, pc
+	BX R0
+	portRESTORE_CONTEXT			; Restore the context of the selected task.
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Preemptive context switch function.  This will only ever get installed if
+; portUSE_PREEMPTION is set to 1 in portmacro.h.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortPreemptiveTickEntry:
+#if configUSE_PREEMPTION == 1
+	portSAVE_CONTEXT			; Save the context of the current task...
+	LDR R0, =vPortPreemptiveTick; before selecting the next task to execute.
+	mov     lr, pc
+	BX R0
+	portRESTORE_CONTEXT			; Restore the context of the selected task.
+#endif
+
+	END
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/LPC2000/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/LPC2000/portmacro.h
new file mode 100644
index 0000000..7ebcbe8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/LPC2000/portmacro.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+#define portYIELD()					asm ( "SWI 0" )
+#define portNOP()					asm ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+__arm __interwork void vPortDisableInterruptsFromThumb( void );
+__arm __interwork void vPortEnableInterruptsFromThumb( void );
+__arm __interwork void vPortEnterCritical( void );
+__arm __interwork void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()	__disable_interrupt()
+#define portENABLE_INTERRUPTS()		__enable_interrupt()
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+#define portEND_SWITCHING_ISR( xSwitchRequired ) 	\
+{													\
+extern void vTaskSwitchContext( void );				\
+													\
+	if( xSwitchRequired ) 							\
+	{												\
+		vTaskSwitchContext();						\
+	}												\
+}
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430/port.c
new file mode 100644
index 0000000..605c7c7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430/port.c
@@ -0,0 +1,173 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MSP430 port.
+ *----------------------------------------------------------*/
+
+/* Constants required for hardware setup.  The tick ISR runs off the ACLK,
+not the MCLK. */
+#define portACLK_FREQUENCY_HZ			( ( TickType_t ) 32768 )
+#define portINITIAL_CRITICAL_NESTING	( ( uint16_t ) 10 )
+#define portFLAGS_INT_ENABLED			( ( StackType_t ) 0x08 )
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/* Each task maintains a count of the critical section nesting depth.  Each
+time a critical section is entered the count is incremented.  Each time a
+critical section is exited the count is decremented - with interrupts only
+being re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as this will cause problems during the startup
+sequence. */
+volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
+/*-----------------------------------------------------------*/
+
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
+ * could have alternatively used the watchdog timer or timer 1.
+ */
+void vPortSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/*
+		Place a few bytes of known values on the bottom of the stack.
+		This is just useful for debugging and can be included if required.
+
+		*pxTopOfStack = ( StackType_t ) 0x1111;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x2222;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x3333;
+		pxTopOfStack--;
+	*/
+
+	/* The msp430 automatically pushes the PC then SR onto the stack before
+	executing an ISR.  We want the stack to look just as if this has happened
+	so place a pointer to the start of the task on the stack first - followed
+	by the flags we want the task to use when it starts up. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+	*pxTopOfStack = portFLAGS_INT_ENABLED;
+	pxTopOfStack--;
+
+	/* Next the general purpose registers. */
+	*pxTopOfStack = ( StackType_t ) 0x4444;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x5555;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x6666;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x7777;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x8888;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x9999;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xaaaa;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xbbbb;
+	pxTopOfStack--;	
+	
+	/* When the task starts is will expect to find the function parameter in
+	R15. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;
+	pxTopOfStack--;
+	
+	*pxTopOfStack = ( StackType_t ) 0xdddd;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xeeee;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xffff;
+	pxTopOfStack--;
+
+	/* A variable is used to keep track of the critical section nesting.
+	This variable has to be stored as part of the task context and is
+	initially set to zero. */
+	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;	
+
+	/* Return a pointer to the top of the stack we have generated so this can
+	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the MSP430 port will get stopped.  If required simply
+	disable the tick interrupt here. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.  This uses timer 0
+ * but could alternatively use the watchdog timer or timer 1.
+ */
+void vPortSetupTimerInterrupt( void )
+{
+	/* Ensure the timer is stopped. */
+	TACTL = 0;
+
+	/* Run the timer of the ACLK. */
+	TACTL = TASSEL_1;
+
+	/* Clear everything to start with. */
+	TACTL |= TACLR;
+
+	/* Set the compare match value according to the tick rate we want. */
+	TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;
+
+	/* Enable the interrupts. */
+	TACCTL0 = CCIE;
+
+	/* Start up clean. */
+	TACTL |= TACLR;
+
+	/* Up mode. */
+	TACTL |= MC_1;
+}
+/*-----------------------------------------------------------*/
+
+
+	
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430/portasm.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430/portasm.h
new file mode 100644
index 0000000..bb5da67
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430/portasm.h
@@ -0,0 +1,84 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTASM_H
+#define PORTASM_H
+
+portSAVE_CONTEXT macro
+
+		IMPORT pxCurrentTCB
+		IMPORT usCriticalNesting
+
+		/* Save the remaining registers. */
+		push	r4
+		push	r5
+		push	r6
+		push	r7
+		push	r8
+		push	r9
+		push	r10
+		push	r11
+		push	r12
+		push	r13
+		push	r14
+		push	r15
+		mov.w	&usCriticalNesting, r14
+		push	r14
+		mov.w	&pxCurrentTCB, r12
+		mov.w	r1, 0(r12)
+		endm
+/*-----------------------------------------------------------*/
+		
+portRESTORE_CONTEXT macro
+		mov.w	&pxCurrentTCB, r12
+		mov.w	@r12, r1
+		pop		r15
+		mov.w	r15, &usCriticalNesting
+		pop		r15
+		pop		r14
+		pop		r13
+		pop		r12
+		pop		r11
+		pop		r10
+		pop		r9
+		pop		r8
+		pop		r7
+		pop		r6
+		pop		r5
+		pop		r4
+
+		/* The last thing on the stack will be the status register.
+        Ensure the power down bits are clear ready for the next
+        time this power down register is popped from the stack. */
+		bic.w   #0xf0,0(SP)
+
+		reti
+		endm
+/*-----------------------------------------------------------*/
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430/portext.s43 b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430/portext.s43
new file mode 100644
index 0000000..ace7e5c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430/portext.s43
@@ -0,0 +1,106 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+#include "FreeRTOSConfig.h"
+#include "portasm.h"
+
+	IMPORT xTaskIncrementTick
+	IMPORT vTaskSwitchContext
+	IMPORT vPortSetupTimerInterrupt
+
+	EXPORT vTickISR
+	EXPORT vPortYield
+	EXPORT xPortStartScheduler
+
+	RSEG CODE
+
+/*
+ * The RTOS tick ISR.
+ *
+ * If the cooperative scheduler is in use this simply increments the tick
+ * count.
+ *
+ * If the preemptive scheduler is in use a context switch can also occur.
+ */
+vTickISR:
+	portSAVE_CONTEXT
+
+	call	#xTaskIncrementTick
+	cmp.w	#0x0, R12
+    jeq		SkipContextSwitch
+	call	#vTaskSwitchContext
+SkipContextSwitch:
+
+	portRESTORE_CONTEXT
+/*-----------------------------------------------------------*/
+
+
+/*
+ * Manual context switch called by the portYIELD() macro.
+ */
+vPortYield:
+
+	/* Mimic an interrupt by pushing the SR. */
+	push	SR
+
+	/* Now the SR is stacked we can disable interrupts. */
+	dint
+
+	/* Save the context of the current task. */
+	portSAVE_CONTEXT
+
+	/* Switch to the highest priority task that is ready to run. */
+	call	#vTaskSwitchContext
+
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT
+/*-----------------------------------------------------------*/
+
+
+/*
+ * Start off the scheduler by initialising the RTOS tick timer, then restoring
+ * the context of the first task.
+ */
+xPortStartScheduler:
+
+	/* Setup the hardware to generate the tick.  Interrupts are disabled
+	when this function is called. */
+	call	#vPortSetupTimerInterrupt
+
+	/* Restore the context of the first task that is going to run. */
+	portRESTORE_CONTEXT
+/*-----------------------------------------------------------*/
+
+
+	/* Install vTickISR as the timer A0 interrupt. */
+	ASEG
+	ORG 0xFFE0 + TIMERA0_VECTOR
+
+	_vTickISR_: DC16 vTickISR
+
+
+	END
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430/portmacro.h
new file mode 100644
index 0000000..728c17d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430/portmacro.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	uint16_t
+#define portBASE_TYPE	short
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS()	_DINT(); _NOP()
+#define portENABLE_INTERRUPTS()		_EINT(); _NOP()
+/*-----------------------------------------------------------*/
+
+/* Critical section control macros. */
+#define portNO_CRITICAL_SECTION_NESTING		( ( uint16_t ) 0 )
+
+#define portENTER_CRITICAL()													\
+{																				\
+extern volatile uint16_t usCriticalNesting;							\
+																				\
+	portDISABLE_INTERRUPTS();													\
+																				\
+	/* Now interrupts are disabled usCriticalNesting can be accessed */			\
+	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
+	/* times portENTER_CRITICAL() has been called. */							\
+	usCriticalNesting++;														\
+}
+
+#define portEXIT_CRITICAL()														\
+{																				\
+extern volatile uint16_t usCriticalNesting;							\
+																				\
+	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
+	{																			\
+		/* Decrement the nesting count as we are leaving a critical section. */	\
+		usCriticalNesting--;													\
+																				\
+		/* If the nesting level has reached zero then interrupts should be */	\
+		/* re-enabled. */														\
+		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
+		{																		\
+			portENABLE_INTERRUPTS();											\
+		}																		\
+	}																			\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.
+ */
+extern void vPortYield( void );
+#define portYIELD() vPortYield()
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			2
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()
+#define portPOINTER_SIZE_TYPE		uint16_t
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#if configINTERRUPT_EXAMPLE_METHOD == 2
+
+extern void vTaskSwitchContext( void );
+#define portYIELD_FROM_ISR( x ) if( x ) vTaskSwitchContext()
+
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430X/data_model.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430X/data_model.h
new file mode 100644
index 0000000..e03a16b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430X/data_model.h
@@ -0,0 +1,63 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef DATA_MODEL_H
+#define DATA_MODEL_H
+
+#if __DATA_MODEL__ == __DATA_MODEL_SMALL__
+	#define pushm_x pushm.w
+	#define popm_x popm.w
+	#define push_x push.w
+	#define pop_x pop.w
+	#define mov_x mov.w
+	#define cmp_x cmp.w
+#endif
+
+#if __DATA_MODEL__ == __DATA_MODEL_MEDIUM__
+	#define pushm_x pushm.a
+	#define popm_x popm.a
+	#define push_x pushx.a
+	#define pop_x popx.a
+	#define mov_x mov.w
+	#define cmp_x cmp.w
+#endif
+
+#if __DATA_MODEL__ == __DATA_MODEL_LARGE__
+	#define pushm_x pushm.a
+	#define popm_x popm.a
+	#define push_x pushx.a
+	#define pop_x popx.a
+	#define mov_x movx.a
+	#define cmp_x cmpx.a
+#endif
+
+#ifndef pushm_x
+	#error The assembler options must define one of the following symbols: __DATA_MODEL_SMALL__, __DATA_MODEL_MEDIUM__, or __DATA_MODEL_LARGE__
+#endif
+
+#endif /* DATA_MODEL_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430X/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430X/port.c
new file mode 100644
index 0000000..c8d63da
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430X/port.c
@@ -0,0 +1,182 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MSP430X port.
+ *----------------------------------------------------------*/
+
+/* Constants required for hardware setup.  The tick ISR runs off the ACLK,
+not the MCLK. */
+#define portACLK_FREQUENCY_HZ			( ( TickType_t ) 32768 )
+#define portINITIAL_CRITICAL_NESTING	( ( uint16_t ) 10 )
+#define portFLAGS_INT_ENABLED			( ( StackType_t ) 0x08 )
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/* Each task maintains a count of the critical section nesting depth.  Each
+time a critical section is entered the count is incremented.  Each time a
+critical section is exited the count is decremented - with interrupts only
+being re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as this will cause problems during the startup
+sequence. */
+volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
+/*-----------------------------------------------------------*/
+
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
+ * could have alternatively used the watchdog timer or timer 1.
+ */
+void vPortSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint16_t *pusTopOfStack;
+uint32_t *pulTopOfStack;
+
+	/*
+		Place a few bytes of known values on the bottom of the stack.
+		This is just useful for debugging and can be included if required.
+	
+		*pxTopOfStack = ( StackType_t ) 0x1111;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x2222;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x3333;
+	*/
+
+	/* StackType_t is either 16 bits or 32 bits depending on the data model.
+	Some stacked items do not change size depending on the data model so have
+	to be explicitly cast to the correct size so this function will work
+	whichever data model is being used. */
+	if( sizeof( StackType_t ) == sizeof( uint16_t ) )
+	{
+		/* Make room for a 20 bit value stored as a 32 bit value. */
+		pusTopOfStack = ( uint16_t * ) pxTopOfStack;
+		pusTopOfStack--;
+		pulTopOfStack = ( uint32_t * ) pusTopOfStack;
+	}
+	else
+	{
+		pulTopOfStack = ( uint32_t * ) pxTopOfStack;
+	}
+	*pulTopOfStack = ( uint32_t ) pxCode;
+	
+	pusTopOfStack = ( uint16_t * ) pulTopOfStack;
+	pusTopOfStack--;
+	*pusTopOfStack = portFLAGS_INT_ENABLED;
+	pusTopOfStack -= ( sizeof( StackType_t ) / 2 );
+	
+	/* From here on the size of stacked items depends on the memory model. */
+	pxTopOfStack = ( StackType_t * ) pusTopOfStack;
+
+	/* Next the general purpose registers. */
+	#ifdef PRELOAD_REGISTER_VALUES
+		*pxTopOfStack = ( StackType_t ) 0xffff;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0xeeee;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0xdddd;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pvParameters;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0xbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0xaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x9999;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x8888;
+		pxTopOfStack--;	
+		*pxTopOfStack = ( StackType_t ) 0x5555;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x6666;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x5555;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x4444;
+		pxTopOfStack--;
+	#else
+		pxTopOfStack -= 3;
+		*pxTopOfStack = ( StackType_t ) pvParameters;
+		pxTopOfStack -= 9;
+	#endif
+
+
+	/* A variable is used to keep track of the critical section nesting.
+	This variable has to be stored as part of the task context and is
+	initially set to zero. */
+	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;	
+
+	/* Return a pointer to the top of the stack we have generated so this can
+	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the MSP430 port will get stopped.  If required simply
+	disable the tick interrupt here. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.
+ */
+void vPortSetupTimerInterrupt( void )
+{
+	vApplicationSetupTimerInterrupt();
+}
+/*-----------------------------------------------------------*/
+
+#pragma vector=configTICK_VECTOR
+__interrupt __raw void vTickISREntry( void )
+{
+extern void vPortTickISR( void );
+
+	__bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF );
+	vPortTickISR();
+}
+
+	
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430X/portext.s43 b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430X/portext.s43
new file mode 100644
index 0000000..eef4454
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430X/portext.s43
@@ -0,0 +1,138 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+#include "msp430.h"
+#include "FreeRTOSConfig.h"
+#include "data_model.h"
+
+	IMPORT xTaskIncrementTick
+	IMPORT vTaskSwitchContext
+	IMPORT vPortSetupTimerInterrupt
+	IMPORT pxCurrentTCB
+	IMPORT usCriticalNesting
+
+	EXPORT vPortTickISR
+	EXPORT vPortYield
+	EXPORT xPortStartScheduler
+
+portSAVE_CONTEXT macro
+
+	/* Save the remaining registers. */
+	pushm_x	#12, r15
+	mov.w	&usCriticalNesting, r14
+	push_x r14
+	mov_x	&pxCurrentTCB, r12
+	mov_x	sp, 0( r12 )
+	endm
+/*-----------------------------------------------------------*/
+
+portRESTORE_CONTEXT macro
+
+	mov_x	&pxCurrentTCB, r12
+	mov_x	@r12, sp
+	pop_x	r15
+	mov.w	r15, &usCriticalNesting
+	popm_x	#12, r15
+	nop
+	pop.w	sr
+	nop
+	reta
+	endm
+/*-----------------------------------------------------------*/
+
+
+/*
+ * The RTOS tick ISR.
+ *
+ * If the cooperative scheduler is in use this simply increments the tick
+ * count.
+ *
+ * If the preemptive scheduler is in use a context switch can also occur.
+ */
+
+	RSEG CODE
+	EVEN
+
+vPortTickISR:
+
+	/* The sr is not saved in portSAVE_CONTEXT() because vPortYield() needs
+	to save it manually before it gets modified (interrupts get disabled).
+	Entering through this interrupt means the SR is already on the stack, but
+	this keeps the stack frames identical. */
+	push.w sr
+	portSAVE_CONTEXT
+
+	calla	#xTaskIncrementTick
+	cmp.w   #0x0, R12
+    jeq     SkipContextSwitch
+    calla   #vTaskSwitchContext
+SkipContextSwitch:
+	portRESTORE_CONTEXT
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch called by the portYIELD() macro.
+ */
+ 	EVEN
+
+vPortYield:
+
+	/* The sr needs saving before it is modified. */
+	push.w	sr
+
+	/* Now the SR is stacked interrupts can be disabled. */
+	dint
+	nop
+
+	/* Save the context of the current task. */
+	portSAVE_CONTEXT
+
+	/* Select the next task to run. */
+	calla	#vTaskSwitchContext
+
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT
+/*-----------------------------------------------------------*/
+
+
+/*
+ * Start off the scheduler by initialising the RTOS tick timer, then restoring
+ * the context of the first task.
+ */
+ 	EVEN
+
+xPortStartScheduler:
+
+	/* Setup the hardware to generate the tick.  Interrupts are disabled
+	when this function is called. */
+	calla	#vPortSetupTimerInterrupt
+
+	/* Restore the context of the first task that is going to run. */
+	portRESTORE_CONTEXT
+/*-----------------------------------------------------------*/
+
+	END
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430X/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430X/portmacro.h
new file mode 100644
index 0000000..d5719fe
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/MSP430X/portmacro.h
@@ -0,0 +1,142 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Hardware includes. */
+#include "msp430.h"
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		int
+#define portBASE_TYPE	short
+
+/* The stack type changes depending on the data model. */
+#if( __DATA_MODEL__ == __DATA_MODEL_SMALL__ )
+	#define portSTACK_TYPE uint16_t
+	#define portPOINTER_SIZE_TYPE uint16_t
+#else
+	#define portSTACK_TYPE uint32_t
+#endif
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS()	_DINT(); _NOP()
+#define portENABLE_INTERRUPTS()		_EINT(); _NOP()
+/*-----------------------------------------------------------*/
+
+/* Critical section control macros. */
+#define portNO_CRITICAL_SECTION_NESTING		( ( uint16_t ) 0 )
+
+#define portENTER_CRITICAL()													\
+{																				\
+extern volatile uint16_t usCriticalNesting;										\
+																				\
+	portDISABLE_INTERRUPTS();													\
+																				\
+	/* Now interrupts are disabled usCriticalNesting can be accessed */			\
+	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
+	/* times portENTER_CRITICAL() has been called. */							\
+	usCriticalNesting++;														\
+}
+
+#define portEXIT_CRITICAL()														\
+{																				\
+extern volatile uint16_t usCriticalNesting;										\
+																				\
+	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
+	{																			\
+		/* Decrement the nesting count as we are leaving a critical section. */	\
+		usCriticalNesting--;													\
+																				\
+		/* If the nesting level has reached zero then interrupts should be */	\
+		/* re-enabled. */														\
+		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
+		{																		\
+			portENABLE_INTERRUPTS();											\
+		}																		\
+	}																			\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.
+ */
+extern void vPortYield( void );
+#define portYIELD() vPortYield()
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			2
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					__no_operation()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#define portYIELD_FROM_ISR( x ) if( x ) vPortYield()
+
+void vApplicationSetupTimerInterrupt( void );
+
+/* sizeof( int ) != sizeof( long ) so a full printf() library is required if
+run time stats information is to be displayed. */
+#define portLU_PRINTF_SPECIFIER_REQUIRED
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RL78/ISR_Support.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RL78/ISR_Support.h
new file mode 100644
index 0000000..d9aeb95
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RL78/ISR_Support.h
@@ -0,0 +1,83 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+
+#include "FreeRTOSConfig.h"
+
+; Variables used by scheduler
+;------------------------------------------------------------------------------
+	EXTERN    pxCurrentTCB
+	EXTERN    usCriticalNesting
+
+;------------------------------------------------------------------------------
+;   portSAVE_CONTEXT MACRO
+;   Saves the context of the general purpose registers, CS and ES (only in far
+;	memory mode) registers the usCriticalNesting Value and the Stack Pointer
+;   of the active Task onto the task stack
+;------------------------------------------------------------------------------
+portSAVE_CONTEXT MACRO
+
+	PUSH      AX                    ; Save AX Register to stack.
+	PUSH      HL
+	MOV       A, CS                 ; Save CS register.
+	XCH       A, X
+	MOV       A, ES                 ; Save ES register.
+	PUSH      AX
+	PUSH      DE                    ; Save the remaining general purpose registers.
+	PUSH      BC
+	MOVW      AX, usCriticalNesting ; Save the usCriticalNesting value.
+	PUSH      AX
+	MOVW      AX, pxCurrentTCB 	    ; Save the Stack pointer.
+	MOVW      HL, AX
+	MOVW      AX, SP
+	MOVW      [HL], AX
+	ENDM
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   portRESTORE_CONTEXT MACRO
+;   Restores the task Stack Pointer then use this to restore usCriticalNesting,
+;   general purpose registers and the CS and ES (only in far memory mode)
+;   of the selected task from the task stack
+;------------------------------------------------------------------------------
+portRESTORE_CONTEXT MACRO
+	MOVW      AX, pxCurrentTCB	    ; Restore the Stack pointer.
+	MOVW      HL, AX
+	MOVW      AX, [HL]
+	MOVW      SP, AX
+	POP	      AX	                ; Restore usCriticalNesting value.
+	MOVW      usCriticalNesting, AX
+	POP	      BC                    ; Restore the necessary general purpose registers.
+	POP	      DE
+	POP       AX                    ; Restore the ES register.
+	MOV       ES, A
+	XCH       A, X                  ; Restore the CS register.
+	MOV       CS, A
+	POP       HL                    ; Restore general purpose register HL.
+	POP       AX                    ; Restore AX.
+	ENDM
+;------------------------------------------------------------------------------
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RL78/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RL78/port.c
new file mode 100644
index 0000000..84bfabd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RL78/port.c
@@ -0,0 +1,280 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* The critical nesting value is initialised to a non zero value to ensure
+interrupts don't accidentally become enabled before the scheduler is started. */
+#define portINITIAL_CRITICAL_NESTING  ( ( uint16_t ) 10 )
+
+/* Initial PSW value allocated to a newly created task.
+ *   1100011000000000
+ *   ||||||||-------------- Fill byte
+ *   |||||||--------------- Carry Flag cleared
+ *   |||||----------------- In-service priority Flags set to low level
+ *   ||||------------------ Register bank Select 0 Flag cleared
+ *   |||------------------- Auxiliary Carry Flag cleared
+ *   ||-------------------- Register bank Select 1 Flag cleared
+ *   |--------------------- Zero Flag set
+ *   ---------------------- Global Interrupt Flag set (enabled)
+ */
+#define portPSW		  ( 0xc6UL )
+
+/* The address of the pxCurrentTCB variable, but don't know or need to know its
+type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/* Each task maintains a count of the critical section nesting depth.  Each time
+a critical section is entered the count is incremented.  Each time a critical
+section is exited the count is decremented - with interrupts only being
+re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as that could cause problems during the startup
+sequence. */
+volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick using the interval timer.
+ * The application writer can define configSETUP_TICK_INTERRUPT() (in
+ * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
+ * in place of prvSetupTimerInterrupt().
+ */
+static void prvSetupTimerInterrupt( void );
+#ifndef configSETUP_TICK_INTERRUPT
+	/* The user has not provided their own tick interrupt configuration so use
+    the definition in this file (which uses the interval timer). */
+	#define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
+#endif /* configSETUP_TICK_INTERRUPT */
+
+/*
+ * Defined in portasm.s87, this function starts the scheduler by loading the
+ * context of the first task to run.
+ */
+extern void vPortStartFirstTask( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint32_t *pulLocal;
+
+	/* With large code and large data sizeof( StackType_t ) == 2, and
+	sizeof( StackType_t * ) == 4.  With small code and small data
+	sizeof( StackType_t ) == 2 and sizeof( StackType_t * ) == 2. */
+
+	#if __DATA_MODEL__ == __DATA_MODEL_FAR__
+	{
+		/* Parameters are passed in on the stack, and written using a 32-bit value
+		hence a space is left for the second two bytes. */
+		pxTopOfStack--;
+
+		/* Write in the parameter value. */
+		pulLocal =  ( uint32_t * ) pxTopOfStack;
+		*pulLocal = ( uint32_t ) pvParameters;
+		pxTopOfStack--;
+
+		/* The return address, leaving space for the first two bytes of	the
+		32-bit value.  See the comments above the prvTaskExitError() prototype
+		at the top of this file. */
+		pxTopOfStack--;
+		pulLocal = ( uint32_t * ) pxTopOfStack;
+		*pulLocal = ( uint32_t ) prvTaskExitError;
+		pxTopOfStack--;
+
+		/* The start address / PSW value is also written in as a 32-bit value,
+		so leave a space for the second two bytes. */
+		pxTopOfStack--;
+
+		/* Task function start address combined with the PSW. */
+		pulLocal = ( uint32_t * ) pxTopOfStack;
+		*pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
+		pxTopOfStack--;
+
+		/* An initial value for the AX register. */
+		*pxTopOfStack = ( StackType_t ) 0x1111;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		/* The return address, leaving space for the first two bytes of	the
+		32-bit value.  See the comments above the prvTaskExitError() prototype
+		at the top of this file. */
+		pxTopOfStack--;
+		pulLocal = ( uint32_t * ) pxTopOfStack;
+		*pulLocal = ( uint32_t ) prvTaskExitError;
+		pxTopOfStack--;
+
+		/* Task function.  Again as it is written as a 32-bit value a space is
+		left on the stack for the second two bytes. */
+		pxTopOfStack--;
+
+		/* Task function start address combined with the PSW. */
+		pulLocal = ( uint32_t * ) pxTopOfStack;
+		*pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
+		pxTopOfStack--;
+
+		/* The parameter is passed in AX. */
+		*pxTopOfStack = ( StackType_t ) pvParameters;
+		pxTopOfStack--;
+	}
+	#endif
+
+	/* An initial value for the HL register. */
+	*pxTopOfStack = ( StackType_t ) 0x2222;
+	pxTopOfStack--;
+
+	/* CS and ES registers. */
+	*pxTopOfStack = ( StackType_t ) 0x0F00;
+	pxTopOfStack--;
+
+	/* The remaining general purpose registers DE and BC */
+	*pxTopOfStack = ( StackType_t ) 0xDEDE;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xBCBC;
+	pxTopOfStack--;
+
+	/* Finally the critical section nesting count is set to zero when the task
+	first starts. */
+	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
+
+	/* Return a pointer to the top of the stack that has been generated so it
+	can	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( usCriticalNesting == ~0U );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Setup the hardware to generate the tick.  Interrupts are disabled when
+	this function is called. */
+	configSETUP_TICK_INTERRUPT();
+
+	/* Restore the context of the first task that is going to run. */
+	vPortStartFirstTask();
+
+	/* Execution should not reach here as the tasks are now running!
+	prvSetupTimerInterrupt() is called here to prevent the compiler outputting
+	a warning about a statically declared function not being referenced in the
+	case that the application writer has provided their own tick interrupt
+	configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
+	their own routine will be called in place of prvSetupTimerInterrupt()). */
+	prvSetupTimerInterrupt();
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the RL78 port will get stopped. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+const uint16_t usClockHz = 15000UL; /* Internal clock. */
+const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL;
+
+	/* Use the internal 15K clock. */
+	OSMC = ( uint8_t ) 0x16;
+
+	#ifdef RTCEN
+	{
+		/* Supply the interval timer clock. */
+		RTCEN = ( uint8_t ) 1U;
+
+		/* Disable INTIT interrupt. */
+		ITMK = ( uint8_t ) 1;
+
+		/* Disable ITMC operation. */
+		ITMC = ( uint8_t ) 0x0000;
+
+		/* Clear INIT interrupt. */
+		ITIF = ( uint8_t ) 0;
+
+		/* Set interval and enable interrupt operation. */
+		ITMC = usCompareMatch | 0x8000U;
+
+		/* Enable INTIT interrupt. */
+		ITMK = ( uint8_t ) 0;
+	}
+	#endif
+
+	#ifdef TMKAEN
+	{
+		/* Supply the interval timer clock. */
+		TMKAEN = ( uint8_t ) 1U;
+
+		/* Disable INTIT interrupt. */
+		TMKAMK = ( uint8_t ) 1;
+
+		/* Disable ITMC operation. */
+		ITMC = ( uint8_t ) 0x0000;
+
+		/* Clear INIT interrupt. */
+		TMKAIF = ( uint8_t ) 0;
+
+		/* Set interval and enable interrupt operation. */
+		ITMC = usCompareMatch | 0x8000U;
+
+		/* Enable INTIT interrupt. */
+		TMKAMK = ( uint8_t ) 0;
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RL78/portasm.s87 b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RL78/portasm.s87
new file mode 100644
index 0000000..8e30f01
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RL78/portasm.s87
@@ -0,0 +1,83 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+#include "ISR_Support.h"
+
+#define CS                    0xFFFFC
+#define ES                    0xFFFFD
+
+	PUBLIC    vPortYield
+	PUBLIC    vPortStartFirstTask
+	PUBLIC    vPortTickISR
+
+	EXTERN    vTaskSwitchContext
+	EXTERN    xTaskIncrementTick
+
+; FreeRTOS yield handler.  This is installed as the BRK software interrupt
+; handler.
+    RSEG CODE:CODE
+vPortYield:
+	portSAVE_CONTEXT		        ; Save the context of the current task.
+	call      vTaskSwitchContext    ; Call the scheduler to select the next task.
+	portRESTORE_CONTEXT		        ; Restore the context of the next task to run.
+	retb
+
+
+; Starts the scheduler by restoring the context of the task that will execute
+; first.
+    RSEG CODE:CODE
+vPortStartFirstTask:
+	portRESTORE_CONTEXT	            ; Restore the context of whichever task the ...
+	reti					        ; An interrupt stack frame is used so the task
+                                    ; is started using a RETI instruction.
+
+; FreeRTOS tick handler.  This is installed as the interval timer interrupt
+; handler.
+	 RSEG CODE:CODE
+vPortTickISR:
+
+	portSAVE_CONTEXT		       ; Save the context of the current task.
+	call	xTaskIncrementTick     ; Call the timer tick function.
+	cmpw	ax, #0x00
+	skz
+	call	vTaskSwitchContext     ; Call the scheduler to select the next task.
+	portRESTORE_CONTEXT		       ; Restore the context of the next task to run.
+	reti
+
+
+; Install the interrupt handlers
+
+	COMMON INTVEC:CODE:ROOT(1)
+	ORG configTICK_VECTOR
+	DW vPortTickISR
+
+	COMMON INTVEC:CODE:ROOT(1)
+	ORG 126
+	DW vPortYield
+
+
+      END
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RL78/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RL78/portmacro.h
new file mode 100644
index 0000000..9261bad
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RL78/portmacro.h
@@ -0,0 +1,144 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+#if __DATA_MODEL__ == __DATA_MODEL_FAR__ && __CODE_MODEL__ == __CODE_MODEL_NEAR__
+	#warning This port has not been tested with your selected memory model combination. If a far data model is required it is recommended to also use a far code model.
+#endif
+
+#if __DATA_MODEL__ == __DATA_MODEL_NEAR__ && __CODE_MODEL__ == __CODE_MODEL_FAR__
+	#warning This port has not been tested with your selected memory model combination. If a far code model is required it is recommended to also use a far data model.
+#endif
+
+/* Type definitions. */
+
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint16_t
+#define portBASE_TYPE   short
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+
+#if __DATA_MODEL__ == __DATA_MODEL_FAR__
+	#define portPOINTER_SIZE_TYPE uint32_t
+#else
+	#define portPOINTER_SIZE_TYPE uint16_t
+#endif
+
+
+#if ( configUSE_16_BIT_TICKS == 1 )
+	typedef unsigned int TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS() __asm ( "DI" )
+#define portENABLE_INTERRUPTS()	 __asm ( "EI" )
+/*-----------------------------------------------------------*/
+
+/* Critical section control macros. */
+#define portNO_CRITICAL_SECTION_NESTING		( ( uint16_t ) 0 )
+
+#define portENTER_CRITICAL()													\
+{																				\
+extern volatile uint16_t usCriticalNesting;										\
+																				\
+	portDISABLE_INTERRUPTS();													\
+																				\
+	/* Now interrupts are disabled ulCriticalNesting can be accessed */			\
+	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
+	/* times portENTER_CRITICAL() has been called. */							\
+	usCriticalNesting++;														\
+}
+
+#define portEXIT_CRITICAL()														\
+{																				\
+extern volatile uint16_t usCriticalNesting;										\
+																				\
+	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
+	{																			\
+		/* Decrement the nesting count as we are leaving a critical section. */	\
+		usCriticalNesting--;													\
+																				\
+		/* If the nesting level has reached zero then interrupts should be */	\
+		/* re-enabled. */														\
+		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
+		{																		\
+			portENABLE_INTERRUPTS();											\
+		}																		\
+	}																			\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+#define portYIELD()	__asm( "BRK" )
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext()
+#define portNOP()	__asm( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Hardwware specifics. */
+#define portBYTE_ALIGNMENT	2
+#define portSTACK_GROWTH	( -1 )
+#define portTICK_PERIOD_MS	( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RX100/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RX100/port.c
new file mode 100644
index 0000000..f9e9dbc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RX100/port.c
@@ -0,0 +1,516 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
+
+/* Standard C includes. */
+#include "limits.h"
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#include "machine.h"
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
+
+/* The peripheral clock is divided by this value before being supplying the
+CMT. */
+#if ( configUSE_TICKLESS_IDLE == 0 )
+	/* If tickless idle is not used then the divisor can be fixed. */
+	#define portCLOCK_DIVISOR	8UL
+#elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
+	#define portCLOCK_DIVISOR	512UL
+#elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
+	#define portCLOCK_DIVISOR	128UL
+#elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
+	#define portCLOCK_DIVISOR	32UL
+#else
+	#define portCLOCK_DIVISOR	8UL
+#endif
+
+
+/* Keys required to lock and unlock access to certain system registers
+respectively. */
+#define portUNLOCK_KEY		0xA50B
+#define portLOCK_KEY		0xA500
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+extern void prvStartFirstTask( void );
+
+/*
+ * The tick ISR handler.  The peripheral used is configured by the application
+ * via a hook/callback function.
+ */
+__interrupt static void prvTickISR( void );
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick using the CMT.
+ * The application writer can define configSETUP_TICK_INTERRUPT() (in
+ * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
+ * in place of prvSetupTimerInterrupt().
+ */
+static void prvSetupTimerInterrupt( void );
+#ifndef configSETUP_TICK_INTERRUPT
+	/* The user has not provided their own tick interrupt configuration so use
+    the definition in this file (which uses the interval timer). */
+	#define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
+#endif /* configSETUP_TICK_INTERRUPT */
+
+/*
+ * Called after the sleep mode registers have been configured, prvSleep()
+ * executes the pre and post sleep macros, and actually calls the wait
+ * instruction.
+ */
+#if configUSE_TICKLESS_IDLE == 1
+	static void prvSleep( TickType_t xExpectedIdleTime );
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*-----------------------------------------------------------*/
+
+extern void *pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/* Calculate how many clock increments make up a single tick period. */
+static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
+
+#if configUSE_TICKLESS_IDLE == 1
+
+	/* Holds the maximum number of ticks that can be suppressed - which is
+	basically how far into the future an interrupt can be generated. Set
+	during initialisation.  This is the maximum possible value that the
+	compare match register can hold divided by ulMatchValueForOneTick. */
+	static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
+
+	/* Flag set from the tick interrupt to allow the sleep processing to know if
+	sleep mode was exited because of a tick interrupt, or an interrupt
+	generated by something else. */
+	static volatile uint32_t ulTickFlag = pdFALSE;
+
+	/* The CMT counter is stopped temporarily each time it is re-programmed.
+	The following constant offsets the CMT counter match value by the number of
+	CMT	counts that would typically be missed while the counter was stopped to
+	compensate for the lost time.  The large difference between the divided CMT
+	clock and the CPU clock means it is likely ulStoppedTimerCompensation will
+	equal zero - and be optimised away. */
+	static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Offset to end up on 8 byte boundary. */
+	pxTopOfStack--;
+
+	/* R0 is not included as it is the stack pointer. */
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+    *pxTopOfStack = 0x00;
+	pxTopOfStack--;
+ 	*pxTopOfStack = portINITIAL_PSW;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;
+
+	/* When debugging it can be useful if every register is set to a known
+	value.  Otherwise code space can be saved by just setting the registers
+	that need to be set. */
+	#ifdef USE_FULL_REGISTER_INITIALISATION
+	{
+		pxTopOfStack--;
+		*pxTopOfStack = 0x12345678;	/* r15. */
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaabbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xdddddddd;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xcccccccc;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xbbbbbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaaaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x99999999;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x88888888;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x77777777;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x66666666;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x55555555;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x44444444;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x33333333;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x22222222;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		/* Leave space for the registers that will get popped from the stack
+		when the task first starts executing. */
+		pxTopOfStack -= 15;
+	}
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x12345678; /* Accumulator. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x87654321; /* Accumulator. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Use pxCurrentTCB just so it does not get optimised away. */
+	if( pxCurrentTCB != NULL )
+	{
+		/* Call an application function to set up the timer that will generate
+		the tick interrupt.  This way the application can decide which
+		peripheral to use.  If tickless mode is used then the default
+		implementation defined in this file (which uses CMT0) should not be
+		overridden. */
+		configSETUP_TICK_INTERRUPT();
+
+		/* Enable the software interrupt. */
+		_IEN( _ICU_SWINT ) = 1;
+
+		/* Ensure the software interrupt is clear. */
+		_IR( _ICU_SWINT ) = 0;
+
+		/* Ensure the software interrupt is set to the kernel priority. */
+		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+		/* Start the first task. */
+		prvStartFirstTask();
+	}
+
+	/* Execution should not reach here as the tasks are now running!
+	prvSetupTimerInterrupt() is called here to prevent the compiler outputting
+	a warning about a statically declared function not being referenced in the
+	case that the application writer has provided their own tick interrupt
+	configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
+	their own routine will be called in place of prvSetupTimerInterrupt()). */
+	prvSetupTimerInterrupt();
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+#pragma vector = configTICK_VECTOR
+__interrupt static void prvTickISR( void )
+{
+	/* Re-enable interrupts. */
+	__enable_interrupt();
+
+	/* Increment the tick, and perform any processing the new tick value
+	necessitates. */
+	__set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			taskYIELD();
+		}
+	}
+	__set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY );
+
+	#if configUSE_TICKLESS_IDLE == 1
+	{
+		/* The CPU woke because of a tick. */
+		ulTickFlag = pdTRUE;
+
+		/* If this is the first tick since exiting tickless mode then the CMT
+		compare match value needs resetting. */
+		CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( pxCurrentTCB == NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+	/* Unlock. */
+	SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+
+	/* Enable CMT0. */
+	MSTP( CMT0 ) = 0;
+
+	/* Lock again. */
+	SYSTEM.PRCR.WORD = portLOCK_KEY;
+
+	/* Interrupt on compare match. */
+	CMT0.CMCR.BIT.CMIE = 1;
+
+	/* Set the compare match value. */
+	CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
+
+	/* Divide the PCLK. */
+	#if portCLOCK_DIVISOR == 512
+	{
+		CMT0.CMCR.BIT.CKS = 3;
+	}
+	#elif portCLOCK_DIVISOR == 128
+	{
+		CMT0.CMCR.BIT.CKS = 2;
+	}
+	#elif portCLOCK_DIVISOR == 32
+	{
+		CMT0.CMCR.BIT.CKS = 1;
+	}
+	#elif portCLOCK_DIVISOR == 8
+	{
+		CMT0.CMCR.BIT.CKS = 0;
+	}
+	#else
+	{
+		#error Invalid portCLOCK_DIVISOR setting
+	}
+	#endif
+
+
+	/* Enable the interrupt... */
+	_IEN( _CMT0_CMI0 ) = 1;
+
+	/* ...and set its priority to the application defined kernel priority. */
+	_IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
+
+	/* Start the timer. */
+	CMT.CMSTR0.BIT.STR0 = 1;
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_TICKLESS_IDLE == 1
+
+	static void prvSleep( TickType_t xExpectedIdleTime )
+	{
+		/* Allow the application to define some pre-sleep processing. */
+		configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
+
+		/* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
+		means the application defined code has already executed the WAIT
+		instruction. */
+		if( xExpectedIdleTime > 0 )
+		{
+			__wait_for_interrupt();
+		}
+
+		/* Allow the application to define some post sleep processing. */
+		configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if configUSE_TICKLESS_IDLE == 1
+
+	void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
+	eSleepModeStatus eSleepAction;
+
+		/* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
+
+		/* Make sure the CMT reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Calculate the reload value required to wait xExpectedIdleTime tick
+		periods. */
+		ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
+		if( ulMatchValue > ulStoppedTimerCompensation )
+		{
+			/* Compensate for the fact that the CMT is going to be stopped
+			momentarily. */
+			ulMatchValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Stop the CMT momentarily.  The time the CMT is stopped for is
+		accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		CMT.CMSTR0.BIT.STR0 = 0;
+		while( CMT.CMSTR0.BIT.STR0 == 1 )
+		{
+			/* Nothing to do here. */
+		}
+
+		/* Critical section using the global interrupt bit as the i bit is
+		automatically reset by the WAIT instruction. */
+		__disable_interrupt();
+
+		/* The tick flag is set to false before sleeping.  If it is true when
+		sleep mode is exited then sleep mode was probably exited because the
+		tick was suppressed for the entire xExpectedIdleTime period. */
+		ulTickFlag = pdFALSE;
+
+		/* If a context switch is pending then abandon the low power entry as
+		the context switch might have been pended by an external interrupt that
+		requires processing. */
+		eSleepAction = eTaskConfirmSleepModeStatus();
+		if( eSleepAction == eAbortSleep )
+		{
+			/* Restart tick. */
+			CMT.CMSTR0.BIT.STR0 = 1;
+			__enable_interrupt();
+		}
+		else if( eSleepAction == eNoTasksWaitingTimeout )
+		{
+		    /* Protection off. */
+		    SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+
+		    /* Ready for software standby with all clocks stopped. */
+			SYSTEM.SBYCR.BIT.SSBY = 1;
+
+		    /* Protection on. */
+		    SYSTEM.PRCR.WORD = portLOCK_KEY;
+
+			/* Sleep until something happens.  Calling prvSleep() will
+			automatically reset the i bit in the PSW. */
+			prvSleep( xExpectedIdleTime );
+
+			/* Restart the CMT. */
+			CMT.CMSTR0.BIT.STR0 = 1;
+		}
+		else
+		{
+		    /* Protection off. */
+		    SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+
+		    /* Ready for deep sleep mode. */
+			SYSTEM.MSTPCRC.BIT.DSLPE = 1;
+			SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
+			SYSTEM.SBYCR.BIT.SSBY = 0;
+
+		    /* Protection on. */
+		    SYSTEM.PRCR.WORD = portLOCK_KEY;
+
+		    /* Adjust the match value to take into account that the current
+			time slice is already partially complete. */
+			ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
+			CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+
+			/* Restart the CMT to count up to the new match value. */
+			CMT0.CMCNT = 0;
+			CMT.CMSTR0.BIT.STR0 = 1;
+
+			/* Sleep until something happens.  Calling prvSleep() will
+			automatically reset the i bit in the PSW. */
+			prvSleep( xExpectedIdleTime );
+
+			/* Stop CMT.  Again, the time the SysTick is stopped for is
+			accounted for as best it can be, but using the tickless mode will
+			inevitably result in some tiny drift of the time maintained by the
+			kernel with	respect to calendar time. */
+			CMT.CMSTR0.BIT.STR0 = 0;
+			while( CMT.CMSTR0.BIT.STR0 == 1 )
+			{
+				/* Nothing to do here. */
+			}
+
+			ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
+
+			if( ulTickFlag != pdFALSE )
+			{
+				/* The tick interrupt has already executed, although because
+				this function is called with the scheduler suspended the actual
+				tick processing will not occur until after this function has
+				exited.  Reset the match value with whatever remains of this
+				tick period. */
+				ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
+				CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+
+				/* The tick interrupt handler will already have pended the tick
+				processing in the kernel.  As the pending tick will be
+				processed as soon as this function exits, the tick value
+				maintained by the tick is stepped forward by one less than the
+				time spent sleeping.  The actual stepping of the tick appears
+				later in this function. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				How	many complete tick periods passed while the processor was
+				sleeping? */
+				ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
+
+				/* The match value is set to whatever fraction of a single tick
+				period remains. */
+				ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
+				CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+			}
+
+			/* Restart the CMT so it runs up to the match value.  The match value
+			will get set to the value required to generate exactly one tick period
+			the next time the CMT interrupt executes. */
+			CMT0.CMCNT = 0;
+			CMT.CMSTR0.BIT.STR0 = 1;
+
+			/* Wind the tick forward by the number of tick periods that the CPU
+			remained in a low power state. */
+			vTaskStepTick( ulCompleteTickPeriods );
+		}
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RX100/port_asm.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RX100/port_asm.s
new file mode 100644
index 0000000..69d3178
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RX100/port_asm.s
@@ -0,0 +1,151 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "PriorityDefinitions.h"
+
+	PUBLIC _prvStartFirstTask
+	PUBLIC ___interrupt_27
+
+	EXTERN _pxCurrentTCB
+	EXTERN _vTaskSwitchContext
+
+	RSEG CODE:CODE(4)
+
+_prvStartFirstTask:
+
+		/* When starting the scheduler there is nothing that needs moving to the
+		interrupt stack because the function is not called from an interrupt.
+		Just ensure the current stack is the user stack. */
+		SETPSW		U
+
+		/* Obtain the location of the stack associated with which ever task
+		pxCurrentTCB is currently pointing to. */
+		MOV.L		#_pxCurrentTCB, R15
+		MOV.L		[R15], R15
+		MOV.L		[R15], R0
+
+		/* Restore the registers from the stack of the task pointed to by
+		pxCurrentTCB. */
+		POP			R15
+
+		/* Accumulator low 32 bits. */
+		MVTACLO		R15
+		POP			R15
+
+		/* Accumulator high 32 bits. */
+		MVTACHI		R15
+
+		/* R1 to R15 - R0 is not included as it is the SP. */
+		POPM		R1-R15
+
+		/* This pops the remaining registers. */
+		RTE
+		NOP
+		NOP
+
+/*-----------------------------------------------------------*/
+
+/* The software interrupt - overwrite the default 'weak' definition. */
+___interrupt_27:
+
+		/* Re-enable interrupts. */
+		SETPSW		I
+
+		/* Move the data that was automatically pushed onto the interrupt stack when
+		the interrupt occurred from the interrupt stack to the user stack.
+
+		R15 is saved before it is clobbered. */
+		PUSH.L		R15
+
+		/* Read the user stack pointer. */
+		MVFC		USP, R15
+
+		/* Move the address down to the data being moved. */
+		SUB			#12, R15
+		MVTC		R15, USP
+
+		/* Copy the data across, R15, then PC, then PSW. */
+		MOV.L		[ R0 ], [ R15 ]
+		MOV.L 		4[ R0 ], 4[ R15 ]
+		MOV.L		8[ R0 ], 8[ R15 ]
+
+		/* Move the interrupt stack pointer to its new correct position. */
+		ADD		#12, R0
+
+		/* All the rest of the registers are saved directly to the user stack. */
+		SETPSW		U
+
+		/* Save the rest of the general registers (R15 has been saved already). */
+		PUSHM		R1-R14
+
+		/* Save the accumulator. */
+		MVFACHI 	R15
+		PUSH.L		R15
+
+		/* Middle word. */
+		MVFACMI	R15
+
+		/* Shifted left as it is restored to the low order word. */
+		SHLL		#16, R15
+		PUSH.L		R15
+
+		/* Save the stack pointer to the TCB. */
+		MOV.L		#_pxCurrentTCB, R15
+		MOV.L		[ R15 ], R15
+		MOV.L		R0, [ R15 ]
+
+		/* Ensure the interrupt mask is set to the syscall priority while the kernel
+		structures are being accessed. */
+		MVTIPL		#configMAX_SYSCALL_INTERRUPT_PRIORITY
+
+		/* Select the next task to run. */
+		BSR.A		_vTaskSwitchContext
+
+		/* Reset the interrupt mask as no more data structure access is required. */
+		MVTIPL		#configKERNEL_INTERRUPT_PRIORITY
+
+		/* Load the stack pointer of the task that is now selected as the Running
+		state task from its TCB. */
+		MOV.L		#_pxCurrentTCB,R15
+		MOV.L		[ R15 ], R15
+		MOV.L		[ R15 ], R0
+
+		/* Restore the context of the new task.  The PSW (Program Status Word) and
+		PC will be popped by the RTE instruction. */
+		POP			R15
+		MVTACLO 	R15
+		POP			R15
+		MVTACHI 	R15
+		POPM		R1-R15
+		RTE
+		NOP
+		NOP
+
+/*-----------------------------------------------------------*/
+
+		END
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RX100/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RX100/portmacro.h
new file mode 100644
index 0000000..324e988
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RX100/portmacro.h
@@ -0,0 +1,150 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Hardware specifics. */
+#include "machine.h"
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			8	/* Could make four, according to manual. */
+#define portSTACK_GROWTH			-1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					__no_operation()
+
+#define portYIELD()						\
+	__asm volatile						\
+	(									\
+		"MOV.L #0x872E0, R15		\n"	\
+		"MOV.B #1, [R15]			\n"	\
+		"MOV.L [R15], R15			\n"	\
+		::: "R15"						\
+	)
+
+#define portYIELD_FROM_ISR( x )	if( ( x ) != pdFALSE ) { portYIELD(); }
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() 	__set_interrupt_level( ( uint8_t ) 0 )
+#ifdef configASSERT
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+	#define portDISABLE_INTERRUPTS() 	if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#else
+	#define portDISABLE_INTERRUPTS() 	__set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
+
+/* Tickless idle/low power functionality. */
+#if configUSE_TICKLESS_IDLE == 1
+	#ifndef portSUPPRESS_TICKS_AND_SLEEP
+		extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+		#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+	#endif
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+/* Prevent warnings of undefined behaviour: the order of volatile accesses is
+undefined - all warnings have been manually checked and are not an issue, and
+the warnings cannot be prevent by code changes without undesirable effects. */
+#pragma diag_suppress=Pa082
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RX600/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RX600/port.c
new file mode 100644
index 0000000..7f8f4cc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RX600/port.c
@@ -0,0 +1,193 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#include 
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW	 ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW	( ( StackType_t ) 0x00000100 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+extern void prvStartFirstTask( void );
+
+/*
+ * The tick ISR handler.  The peripheral used is configured by the application
+ * via a hook/callback function.
+ */
+__interrupt void vTickISR( void );
+
+/*-----------------------------------------------------------*/
+
+extern void *pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* R0 is not included as it is the stack pointer. */
+
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+ 	*pxTopOfStack = portINITIAL_PSW;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;
+
+	/* When debugging it can be useful if every register is set to a known
+	value.  Otherwise code space can be saved by just setting the registers
+	that need to be set. */
+	#ifdef USE_FULL_REGISTER_INITIALISATION
+	{
+		pxTopOfStack--;
+		*pxTopOfStack = 0xffffffff;	/* r15. */
+		pxTopOfStack--;
+		*pxTopOfStack = 0xeeeeeeee;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xdddddddd;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xcccccccc;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xbbbbbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaaaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x99999999;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x88888888;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x77777777;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x66666666;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x55555555;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x44444444;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x33333333;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x22222222;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		pxTopOfStack -= 15;
+	}
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_FPSW;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x12345678; /* Accumulator. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x87654321; /* Accumulator. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vApplicationSetupTimerInterrupt( void );
+
+	/* Use pxCurrentTCB just so it does not get optimised away. */
+	if( pxCurrentTCB != NULL )
+	{
+		/* Call an application function to set up the timer that will generate the
+		tick interrupt.  This way the application can decide which peripheral to
+		use.  A demo application is provided to show a suitable example. */
+		vApplicationSetupTimerInterrupt();
+
+		/* Enable the software interrupt. */
+		_IEN( _ICU_SWINT ) = 1;
+
+		/* Ensure the software interrupt is clear. */
+		_IR( _ICU_SWINT ) = 0;
+
+		/* Ensure the software interrupt is set to the kernel priority. */
+		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+		/* Start the first task. */
+		prvStartFirstTask();
+	}
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+#pragma vector = configTICK_VECTOR
+__interrupt void vTickISR( void )
+{
+	/* Re-enable interrupts. */
+	__enable_interrupt();
+
+	/* Increment the tick, and perform any processing the new tick value
+	necessitates. */
+	__set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			taskYIELD();
+		}
+	}
+	__set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( pxCurrentTCB == NULL );
+}
+/*-----------------------------------------------------------*/
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RX600/port_asm.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RX600/port_asm.s
new file mode 100644
index 0000000..c66e99e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RX600/port_asm.s
@@ -0,0 +1,159 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "PriorityDefinitions.h"
+
+	PUBLIC _prvStartFirstTask
+	PUBLIC ___interrupt_27
+
+	EXTERN _pxCurrentTCB
+	EXTERN _vTaskSwitchContext
+
+	RSEG CODE:CODE(4)
+
+_prvStartFirstTask:
+
+		/* When starting the scheduler there is nothing that needs moving to the
+		interrupt stack because the function is not called from an interrupt.
+		Just ensure the current stack is the user stack. */
+		SETPSW		U
+
+		/* Obtain the location of the stack associated with which ever task
+		pxCurrentTCB is currently pointing to. */
+		MOV.L		#_pxCurrentTCB, R15
+		MOV.L		[R15], R15
+		MOV.L		[R15], R0
+
+		/* Restore the registers from the stack of the task pointed to by
+		pxCurrentTCB. */
+		POP			R15
+
+		/* Accumulator low 32 bits. */
+		MVTACLO		R15
+		POP			R15
+
+		/* Accumulator high 32 bits. */
+		MVTACHI		R15
+		POP			R15
+
+		/* Floating point status word. */
+		MVTC		R15, FPSW
+
+		/* R1 to R15 - R0 is not included as it is the SP. */
+		POPM		R1-R15
+
+		/* This pops the remaining registers. */
+		RTE
+		NOP
+		NOP
+
+/*-----------------------------------------------------------*/
+
+/* The software interrupt - overwrite the default 'weak' definition. */
+___interrupt_27:
+
+		/* Re-enable interrupts. */
+		SETPSW		I
+
+		/* Move the data that was automatically pushed onto the interrupt stack when
+		the interrupt occurred from the interrupt stack to the user stack.
+
+		R15 is saved before it is clobbered. */
+		PUSH.L		R15
+
+		/* Read the user stack pointer. */
+		MVFC		USP, R15
+
+		/* Move the address down to the data being moved. */
+		SUB			#12, R15
+		MVTC		R15, USP
+
+		/* Copy the data across, R15, then PC, then PSW. */
+		MOV.L		[ R0 ], [ R15 ]
+		MOV.L 		4[ R0 ], 4[ R15 ]
+		MOV.L		8[ R0 ], 8[ R15 ]
+
+		/* Move the interrupt stack pointer to its new correct position. */
+		ADD		#12, R0
+
+		/* All the rest of the registers are saved directly to the user stack. */
+		SETPSW		U
+
+		/* Save the rest of the general registers (R15 has been saved already). */
+		PUSHM		R1-R14
+
+		/* Save the FPSW and accumulator. */
+		MVFC		FPSW, R15
+		PUSH.L		R15
+		MVFACHI 	R15
+		PUSH.L		R15
+
+		/* Middle word. */
+		MVFACMI	R15
+
+		/* Shifted left as it is restored to the low order word. */
+		SHLL		#16, R15
+		PUSH.L		R15
+
+		/* Save the stack pointer to the TCB. */
+		MOV.L		#_pxCurrentTCB, R15
+		MOV.L		[ R15 ], R15
+		MOV.L		R0, [ R15 ]
+
+		/* Ensure the interrupt mask is set to the syscall priority while the kernel
+		structures are being accessed. */
+		MVTIPL		#configMAX_SYSCALL_INTERRUPT_PRIORITY
+
+		/* Select the next task to run. */
+		BSR.A		_vTaskSwitchContext
+
+		/* Reset the interrupt mask as no more data structure access is required. */
+		MVTIPL		#configKERNEL_INTERRUPT_PRIORITY
+
+		/* Load the stack pointer of the task that is now selected as the Running
+		state task from its TCB. */
+		MOV.L		#_pxCurrentTCB,R15
+		MOV.L		[ R15 ], R15
+		MOV.L		[ R15 ], R0
+
+		/* Restore the context of the new task.  The PSW (Program Status Word) and
+		PC will be popped by the RTE instruction. */
+		POP			R15
+		MVTACLO 	R15
+		POP			R15
+		MVTACHI 	R15
+		POP			R15
+		MVTC		R15, FPSW
+		POPM		R1-R15
+		RTE
+		NOP
+		NOP
+
+/*-----------------------------------------------------------*/
+
+		END
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RX600/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RX600/portmacro.h
new file mode 100644
index 0000000..e869600
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RX600/portmacro.h
@@ -0,0 +1,139 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			8	/* Could make four, according to manual. */
+#define portSTACK_GROWTH			-1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					__no_operation()
+
+/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
+where portITU_SWINTR is the location of the software interrupt register
+(0x000872E0).  Don't rely on the assembler to select a register, so instead
+save and restore clobbered registers manually. */
+#define portYIELD()							\
+	__asm volatile 							\
+	(										\
+		"PUSH.L	R10					\n"		\
+		"MOV.L	#0x872E0, R10		\n"		\
+		"MOV.B	#0x1, [R10]			\n"		\
+		"MOV.L	[R10], R10			\n"		\
+		"POP	R10					\n"		\
+	)
+
+#define portYIELD_FROM_ISR( x )	if( ( x ) != pdFALSE ) portYIELD()
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() 	__set_interrupt_level( ( uint8_t ) 0 )
+#ifdef configASSERT
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+	#define portDISABLE_INTERRUPTS() 	if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#else
+	#define portDISABLE_INTERRUPTS() 	__set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RXv2/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RXv2/port.c
new file mode 100644
index 0000000..484d71a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RXv2/port.c
@@ -0,0 +1,201 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#include 
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW	 ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW	( ( StackType_t ) 0x00000100 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+extern void prvStartFirstTask( void );
+
+/*
+ * The tick ISR handler.  The peripheral used is configured by the application
+ * via a hook/callback function.
+ */
+__interrupt void vTickISR( void );
+
+/*-----------------------------------------------------------*/
+
+extern void *pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* R0 is not included as it is the stack pointer. */
+
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+ 	*pxTopOfStack = portINITIAL_PSW;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;
+
+	/* When debugging it can be useful if every register is set to a known
+	value.  Otherwise code space can be saved by just setting the registers
+	that need to be set. */
+	#ifdef USE_FULL_REGISTER_INITIALISATION
+	{
+		pxTopOfStack--;
+		*pxTopOfStack = 0xffffffff;	/* r15. */
+		pxTopOfStack--;
+		*pxTopOfStack = 0xeeeeeeee;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xdddddddd;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xcccccccc;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xbbbbbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaaaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x99999999;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x88888888;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x77777777;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x66666666;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x55555555;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x44444444;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x33333333;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x22222222;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		pxTopOfStack -= 15;
+	}
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_FPSW;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x11111111; /* Accumulator 0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22222222; /* Accumulator 0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33333333; /* Accumulator 0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x44444444; /* Accumulator 1. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x55555555; /* Accumulator 1. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x66666666; /* Accumulator 1. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vApplicationSetupTimerInterrupt( void );
+
+	/* Use pxCurrentTCB just so it does not get optimised away. */
+	if( pxCurrentTCB != NULL )
+	{
+		/* Call an application function to set up the timer that will generate the
+		tick interrupt.  This way the application can decide which peripheral to
+		use.  A demo application is provided to show a suitable example. */
+		vApplicationSetupTimerInterrupt();
+
+		/* Enable the software interrupt. */
+		_IEN( _ICU_SWINT ) = 1;
+
+		/* Ensure the software interrupt is clear. */
+		_IR( _ICU_SWINT ) = 0;
+
+		/* Ensure the software interrupt is set to the kernel priority. */
+		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+		/* Start the first task. */
+		prvStartFirstTask();
+	}
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+#pragma vector = configTICK_VECTOR
+__interrupt void vTickISR( void )
+{
+	/* Re-enable interrupts. */
+	__enable_interrupt();
+
+	/* Increment the tick, and perform any processing the new tick value
+	necessitates. */
+	__set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			taskYIELD();
+		}
+	}
+	__set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( pxCurrentTCB == NULL );
+}
+/*-----------------------------------------------------------*/
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RXv2/port_asm.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RXv2/port_asm.s
new file mode 100644
index 0000000..3c4ef17
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RXv2/port_asm.s
@@ -0,0 +1,200 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "PriorityDefinitions.h"
+
+	PUBLIC _prvStartFirstTask
+	PUBLIC ___interrupt_27
+
+	EXTERN _pxCurrentTCB
+	EXTERN _vTaskSwitchContext
+
+	RSEG CODE:CODE(4)
+
+_prvStartFirstTask:
+
+		/* When starting the scheduler there is nothing that needs moving to the
+		interrupt stack because the function is not called from an interrupt.
+		Just ensure the current stack is the user stack. */
+		SETPSW		U
+
+		/* Obtain the location of the stack associated with which ever task
+		pxCurrentTCB is currently pointing to. */
+		MOV.L		#_pxCurrentTCB, R15
+		MOV.L		[R15], R15
+		MOV.L		[R15], R0
+
+		/* Restore the registers from the stack of the task pointed to by
+		pxCurrentTCB. */
+		POP			R15
+
+		/* Accumulator low 32 bits. */
+		MVTACLO		R15, A0
+		POP			R15
+
+		/* Accumulator high 32 bits. */
+		MVTACHI		R15, A0
+		POP			R15
+
+		/* Accumulator guard. */
+		MVTACGU		R15, A0
+		POP			R15
+
+		/* Accumulator low 32 bits. */
+		MVTACLO		R15, A1
+		POP			R15
+
+		/* Accumulator high 32 bits. */
+		MVTACHI		R15, A1
+		POP			R15
+
+		/* Accumulator guard. */
+		MVTACGU		R15, A1
+		POP			R15
+
+		/* Floating point status word. */
+		MVTC		R15, FPSW
+
+		/* R1 to R15 - R0 is not included as it is the SP. */
+		POPM		R1-R15
+
+		/* This pops the remaining registers. */
+		RTE
+		NOP
+		NOP
+
+/*-----------------------------------------------------------*/
+
+/* The software interrupt - overwrite the default 'weak' definition. */
+___interrupt_27:
+
+		/* Re-enable interrupts. */
+		SETPSW		I
+
+		/* Move the data that was automatically pushed onto the interrupt stack when
+		the interrupt occurred from the interrupt stack to the user stack.
+
+		R15 is saved before it is clobbered. */
+		PUSH.L		R15
+
+		/* Read the user stack pointer. */
+		MVFC		USP, R15
+
+		/* Move the address down to the data being moved. */
+		SUB		#12, R15
+		MVTC		R15, USP
+
+		/* Copy the data across, R15, then PC, then PSW. */
+		MOV.L		[ R0 ], [ R15 ]
+		MOV.L 		4[ R0 ], 4[ R15 ]
+		MOV.L		8[ R0 ], 8[ R15 ]
+
+		/* Move the interrupt stack pointer to its new correct position. */
+		ADD		#12, R0
+
+		/* All the rest of the registers are saved directly to the user stack. */
+		SETPSW		U
+
+		/* Save the rest of the general registers (R15 has been saved already). */
+		PUSHM		R1-R14
+
+		/* Save the FPSW and accumulator. */
+		MVFC		FPSW, R15
+		PUSH.L		R15
+		MVFACGU		#0, A1, R15
+		PUSH.L		R15
+		MVFACHI		#0, A1, R15
+		PUSH.L		R15
+		/* Low order word. */
+		MVFACLO		#0, A1, R15
+		PUSH.L		R15
+		MVFACGU		#0, A0, R15
+		PUSH.L		R15
+		MVFACHI		#0, A0, R15
+		PUSH.L		R15
+		/* Low order word. */
+		MVFACLO		#0, A0, R15
+		PUSH.L		R15
+
+		/* Save the stack pointer to the TCB. */
+		MOV.L		#_pxCurrentTCB, R15
+		MOV.L		[ R15 ], R15
+		MOV.L		R0, [ R15 ]
+
+		/* Ensure the interrupt mask is set to the syscall priority while the kernel
+		structures are being accessed. */
+		MVTIPL		#configMAX_SYSCALL_INTERRUPT_PRIORITY
+
+		/* Select the next task to run. */
+		BSR.A		_vTaskSwitchContext
+
+		/* Reset the interrupt mask as no more data structure access is required. */
+		MVTIPL		#configKERNEL_INTERRUPT_PRIORITY
+
+		/* Load the stack pointer of the task that is now selected as the Running
+		state task from its TCB. */
+		MOV.L		#_pxCurrentTCB,R15
+		MOV.L		[ R15 ], R15
+		MOV.L		[ R15 ], R0
+
+		/* Restore the context of the new task.  The PSW (Program Status Word) and
+		PC will be popped by the RTE instruction. */
+		POP		R15
+
+		/* Accumulator low 32 bits. */
+		MVTACLO	R15, A0
+		POP		R15
+
+		/* Accumulator high 32 bits. */
+		MVTACHI	R15, A0
+		POP		R15
+
+		/* Accumulator guard. */
+		MVTACGU	R15, A0
+		POP		R15
+
+		/* Accumulator low 32 bits. */
+		MVTACLO	R15, A1
+		POP		R15
+
+		/* Accumulator high 32 bits. */
+		MVTACHI	R15, A1
+		POP		R15
+
+		/* Accumulator guard. */
+		MVTACGU	R15, A1
+		POP		R15
+		MVTC		R15, FPSW
+		POPM		R1-R15
+		RTE
+		NOP
+		NOP
+
+/*-----------------------------------------------------------*/
+
+		END
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RXv2/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RXv2/portmacro.h
new file mode 100644
index 0000000..f260ab4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/RXv2/portmacro.h
@@ -0,0 +1,144 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			8	/* Could make four, according to manual. */
+#define portSTACK_GROWTH			-1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					__no_operation()
+
+/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
+where portITU_SWINTR is the location of the software interrupt register
+(0x000872E0).  Don't rely on the assembler to select a register, so instead
+save and restore clobbered registers manually. */
+#define portYIELD()							\
+	__asm volatile 							\
+	(										\
+		"PUSH.L	R10					\n"		\
+		"MOV.L	#0x872E0, R10		\n"		\
+		"MOV.B	#0x1, [R10]			\n"		\
+		"MOV.L	[R10], R10			\n"		\
+		"POP	R10					\n"		\
+	)
+
+#define portYIELD_FROM_ISR( x )	if( ( x ) != pdFALSE ) portYIELD()
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() 	__set_interrupt_level( ( uint8_t ) 0 )
+#ifdef configASSERT
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+	#define portDISABLE_INTERRUPTS() 	if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#else
+	#define portDISABLE_INTERRUPTS() 	__set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+/* Prevent warnings of undefined behaviour: the order of volatile accesses is
+undefined - all warnings have been manually checked and are not an issue, and
+the warnings cannot be prevent by code changes without undesirable effects. */
+#pragma diag_suppress=Pa082
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR71x/ISR_Support.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR71x/ISR_Support.h
new file mode 100644
index 0000000..18e0b3b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR71x/ISR_Support.h
@@ -0,0 +1,105 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	EXTERN pxCurrentTCB
+	EXTERN ulCriticalNesting
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Context save and restore macro definitions
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+portSAVE_CONTEXT MACRO
+
+	; Push R0 as we are going to use the register.
+	STMDB	SP!, {R0}
+
+	; Set R0 to point to the task stack pointer.
+	STMDB	SP, {SP}^
+	NOP
+	SUB		SP, SP, #4
+	LDMIA	SP!, {R0}
+
+	; Push the return address onto the stack.
+	STMDB	R0!, {LR}
+
+	; Now we have saved LR we can use it instead of R0.
+	MOV		LR, R0
+
+	; Pop R0 so we can save it onto the system mode stack.
+	LDMIA	SP!, {R0}
+
+	; Push all the system mode registers onto the task stack.
+	STMDB	LR, {R0-LR}^
+	NOP
+	SUB		LR, LR, #60
+
+	; Push the SPSR onto the task stack.
+	MRS		R0, SPSR
+	STMDB	LR!, {R0}
+
+	LDR		R0, =ulCriticalNesting
+	LDR		R0, [R0]
+	STMDB	LR!, {R0}
+
+	; Store the new top of stack for the task.
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	STR		LR, [R0]
+
+	ENDM
+
+
+portRESTORE_CONTEXT MACRO
+
+	; Set the LR to the task stack.
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	LDR		LR, [R0]
+
+	; The critical nesting depth is the first item on the stack.
+	; Load it into the ulCriticalNesting variable.
+	LDR		R0, =ulCriticalNesting
+	LDMFD	LR!, {R1}
+	STR		R1, [R0]
+
+	; Get the SPSR from the stack.
+	LDMFD	LR!, {R0}
+	MSR		SPSR_cxsf, R0
+
+	; Restore all system mode registers for the task.
+	LDMFD	LR, {R0-R14}^
+	NOP
+
+	; Restore the return address.
+	LDR		LR, [LR, #+60]
+
+	; And return - correcting the offset in the LR to obtain the
+	; correct address.
+	SUBS	PC, LR, #4
+
+	ENDM
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR71x/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR71x/port.c
new file mode 100644
index 0000000..ed06217
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR71x/port.c
@@ -0,0 +1,258 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ST STR71x ARM7
+ * port.
+ *----------------------------------------------------------*/
+
+/* Library includes. */
+#include "wdg.h"
+#include "eic.h"
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup the initial stack. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
+
+#define portMICROS_PER_SECOND 1000000
+
+/*-----------------------------------------------------------*/
+
+/* Setup the watchdog to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* ulCriticalNesting will get set to zero when the first task starts.  It
+cannot be initialised to 0 as this will cause interrupts to be enabled
+during the kernel initialisation process. */
+uint32_t ulCriticalNesting = ( uint32_t ) 9999;
+
+/* Tick interrupt routines for cooperative and preemptive operation
+respectively.  The preemptive version is not defined as __irq as it is called
+from an asm wrapper function. */
+__arm __irq void vPortNonPreemptiveTick( void );
+void vPortPreemptiveTick( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* To ensure asserts in tasks.c don't fail, although in this case the assert
+	is not really required. */
+	pxTopOfStack--;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The status register is set for system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+	
+	if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}		
+	
+	pxTopOfStack--;
+
+	/* Interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+
+	return pxTopOfStack;	
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+/* The cooperative scheduler requires a normal IRQ service routine to
+simply increment the system tick. */
+__arm __irq void vPortNonPreemptiveTick( void )
+{
+	/* Increment the tick count - which may wake some tasks but as the
+	preemptive scheduler is not being used any woken task is not given
+	processor time no matter what its priority. */
+	xTaskIncrementTick();
+
+	/* Clear the interrupt in the watchdog and EIC. */
+	WDG->SR = 0x0000;
+	portCLEAR_EIC();		
+}
+/*-----------------------------------------------------------*/
+
+/* This function is called from an asm wrapper, so does not require the __irq
+keyword. */
+void vPortPreemptiveTick( void )
+{
+	/* Increment the tick counter. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		/* Select a new task to execute. */
+		vTaskSwitchContext();
+	}
+
+	/* Clear the interrupt in the watchdog and EIC. */
+	WDG->SR = 0x0000;
+	portCLEAR_EIC();			
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+	/* Set the watchdog up to generate a periodic tick. */
+	WDG_ECITConfig( DISABLE );
+	WDG_CntOnOffConfig( DISABLE );
+	WDG_PeriodValueConfig( portMICROS_PER_SECOND / configTICK_RATE_HZ );
+
+	/* Setup the tick interrupt in the EIC. */
+	EIC_IRQChannelPriorityConfig( WDG_IRQChannel, 1 );
+	EIC_IRQChannelConfig( WDG_IRQChannel, ENABLE );
+	EIC_IRQConfig( ENABLE );
+	WDG_ECITConfig( ENABLE );
+
+	/* Start the timer - interrupts are actually disabled at this point so
+	it is safe to do this here. */
+	WDG_CntOnOffConfig( ENABLE );
+}
+/*-----------------------------------------------------------*/
+
+__arm __interwork void vPortEnterCritical( void )
+{
+	/* Disable interrupts first! */
+	__disable_interrupt();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+__arm __interwork void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			__enable_interrupt();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR71x/portasm.s79 b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR71x/portasm.s79
new file mode 100644
index 0000000..59afb02
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR71x/portasm.s79
@@ -0,0 +1,76 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+		RSEG ICODE:CODE
+		CODE32
+
+	EXTERN vPortPreemptiveTick
+	EXTERN vTaskSwitchContext
+
+	PUBLIC vPortYieldProcessor
+	PUBLIC vPortStartFirstTask
+	PUBLIC vPortPreemptiveTickISR
+
+#include "ISR_Support.h"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Starting the first task is just a matter of restoring the context that
+; was created by pxPortInitialiseStack().
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortStartFirstTask:
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Manual context switch function.  This is the SWI hander.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortYieldProcessor:
+	ADD		LR, LR, #4			; Add 4 to the LR to make the LR appear exactly
+								; as if the context was saved during and IRQ
+								; handler.
+
+	portSAVE_CONTEXT			; Save the context of the current task...
+	LDR R0, =vTaskSwitchContext	; before selecting the next task to execute.
+	mov     lr, pc
+	BX R0
+	portRESTORE_CONTEXT			; Restore the context of the selected task.
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Preemptive context switch function.  This will only ever get used if
+; portUSE_PREEMPTION is set to 1 in portmacro.h.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortPreemptiveTickISR:
+	portSAVE_CONTEXT			; Save the context of the current task.
+
+	LDR R0, =vPortPreemptiveTick ; Increment the tick count - this may wake a task.
+	MOV lr, pc
+	BX R0
+
+	portRESTORE_CONTEXT			; Restore the context of the selected task.
+
+
+	END
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR71x/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR71x/portmacro.h
new file mode 100644
index 0000000..2cf720f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR71x/portmacro.h
@@ -0,0 +1,121 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+#define portYIELD()					asm ( "SWI 0" )
+#define portNOP()					asm ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+__arm __interwork void vPortDisableInterruptsFromThumb( void );
+__arm __interwork void vPortEnableInterruptsFromThumb( void );
+__arm __interwork void vPortEnterCritical( void );
+__arm __interwork void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()	__disable_interrupt()
+#define portENABLE_INTERRUPTS()		__enable_interrupt()
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+#define portEND_SWITCHING_ISR( xSwitchRequired ) 	\
+{													\
+extern void vTaskSwitchContext( void );				\
+													\
+	if( xSwitchRequired ) 							\
+	{												\
+		vTaskSwitchContext();						\
+	}												\
+}
+/*-----------------------------------------------------------*/
+
+/* EIC utilities. */
+#define portEIC_CICR_ADDR		*( ( uint32_t * ) 0xFFFFF804 )
+#define portEIC_IPR_ADDR		*( ( uint32_t * ) 0xFFFFF840 )
+#define portCLEAR_EIC()			portEIC_IPR_ADDR = 0x01 << portEIC_CICR_ADDR
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR75x/ISR_Support.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR75x/ISR_Support.h
new file mode 100644
index 0000000..18e0b3b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR75x/ISR_Support.h
@@ -0,0 +1,105 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	EXTERN pxCurrentTCB
+	EXTERN ulCriticalNesting
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Context save and restore macro definitions
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+portSAVE_CONTEXT MACRO
+
+	; Push R0 as we are going to use the register.
+	STMDB	SP!, {R0}
+
+	; Set R0 to point to the task stack pointer.
+	STMDB	SP, {SP}^
+	NOP
+	SUB		SP, SP, #4
+	LDMIA	SP!, {R0}
+
+	; Push the return address onto the stack.
+	STMDB	R0!, {LR}
+
+	; Now we have saved LR we can use it instead of R0.
+	MOV		LR, R0
+
+	; Pop R0 so we can save it onto the system mode stack.
+	LDMIA	SP!, {R0}
+
+	; Push all the system mode registers onto the task stack.
+	STMDB	LR, {R0-LR}^
+	NOP
+	SUB		LR, LR, #60
+
+	; Push the SPSR onto the task stack.
+	MRS		R0, SPSR
+	STMDB	LR!, {R0}
+
+	LDR		R0, =ulCriticalNesting
+	LDR		R0, [R0]
+	STMDB	LR!, {R0}
+
+	; Store the new top of stack for the task.
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	STR		LR, [R0]
+
+	ENDM
+
+
+portRESTORE_CONTEXT MACRO
+
+	; Set the LR to the task stack.
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	LDR		LR, [R0]
+
+	; The critical nesting depth is the first item on the stack.
+	; Load it into the ulCriticalNesting variable.
+	LDR		R0, =ulCriticalNesting
+	LDMFD	LR!, {R1}
+	STR		R1, [R0]
+
+	; Get the SPSR from the stack.
+	LDMFD	LR!, {R0}
+	MSR		SPSR_cxsf, R0
+
+	; Restore all system mode registers for the task.
+	LDMFD	LR, {R0-R14}^
+	NOP
+
+	; Restore the return address.
+	LDR		LR, [LR, #+60]
+
+	; And return - correcting the offset in the LR to obtain the
+	; correct address.
+	SUBS	PC, LR, #4
+
+	ENDM
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR75x/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR75x/port.c
new file mode 100644
index 0000000..0d68bcc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR75x/port.c
@@ -0,0 +1,237 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ST STR75x ARM7
+ * port.
+ *----------------------------------------------------------*/
+
+/* Library includes. */
+#include "75x_tb.h"
+#include "75x_eic.h"
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup the initial stack. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
+
+/* Prescale used on the timer clock when calculating the tick period. */
+#define portPRESCALE 20
+
+
+/*-----------------------------------------------------------*/
+
+/* Setup the TB to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* ulCriticalNesting will get set to zero when the first task starts.  It
+cannot be initialised to 0 as this will cause interrupts to be enabled
+during the kernel initialisation process. */
+uint32_t ulCriticalNesting = ( uint32_t ) 9999;
+
+/* Tick interrupt routines for preemptive operation. */
+__arm void vPortPreemptiveTick( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* To ensure asserts in tasks.c don't fail, although in this case the assert
+	is not really required. */
+	pxTopOfStack--;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The status register is set for system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+	pxTopOfStack--;
+
+	/* Interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+
+	return pxTopOfStack;	
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+__arm void vPortPreemptiveTick( void )
+{
+	/* Increment the tick counter. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		/* Select a new task to execute. */
+		vTaskSwitchContext();
+	}
+		
+	TB_ClearITPendingBit( TB_IT_Update );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+EIC_IRQInitTypeDef  EIC_IRQInitStructure;	
+TB_InitTypeDef      TB_InitStructure;
+
+	/* Setup the EIC for the TB. */
+	EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE;
+	EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel;
+	EIC_IRQInitStructure.EIC_IRQChannelPriority = 1;
+	EIC_IRQInit(&EIC_IRQInitStructure);
+	
+	/* Setup the TB for the generation of the tick interrupt. */
+	TB_InitStructure.TB_Mode = TB_Mode_Timing;
+	TB_InitStructure.TB_CounterMode = TB_CounterMode_Down;
+	TB_InitStructure.TB_Prescaler = portPRESCALE - 1;
+	TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ );
+	TB_Init(&TB_InitStructure);
+	
+	/* Enable TB Update interrupt */
+	TB_ITConfig(TB_IT_Update, ENABLE);
+
+	/* Clear TB Update interrupt pending bit */
+	TB_ClearITPendingBit(TB_IT_Update);
+
+	/* Enable TB */
+	TB_Cmd(ENABLE);
+}
+/*-----------------------------------------------------------*/
+
+__arm __interwork void vPortEnterCritical( void )
+{
+	/* Disable interrupts first! */
+	__disable_interrupt();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+__arm __interwork void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			__enable_interrupt();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR75x/portasm.s79 b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR75x/portasm.s79
new file mode 100644
index 0000000..eac9c4b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR75x/portasm.s79
@@ -0,0 +1,63 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	RSEG ICODE:CODE
+	CODE32
+
+	EXTERN vPortPreemptiveTick
+	EXTERN vTaskSwitchContext
+
+	PUBLIC vPortYieldProcessor
+	PUBLIC vPortStartFirstTask
+
+#include "ISR_Support.h"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Starting the first task is just a matter of restoring the context that
+; was created by pxPortInitialiseStack().
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortStartFirstTask:
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Manual context switch function.  This is the SWI hander.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortYieldProcessor:
+	ADD		LR, LR, #4			; Add 4 to the LR to make the LR appear exactly
+								; as if the context was saved during and IRQ
+								; handler.
+
+	portSAVE_CONTEXT			; Save the context of the current task...
+	LDR R0, =vTaskSwitchContext	; before selecting the next task to execute.
+	mov     lr, pc
+	BX R0
+	portRESTORE_CONTEXT			; Restore the context of the selected task.
+
+
+
+	END
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR75x/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR75x/portmacro.h
new file mode 100644
index 0000000..4a20cf1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR75x/portmacro.h
@@ -0,0 +1,112 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+#define portYIELD()					asm ( "SWI 0" )
+#define portNOP()					asm ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+__arm __interwork void vPortEnterCritical( void );
+__arm __interwork void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()	__disable_interrupt()
+#define portENABLE_INTERRUPTS()		__enable_interrupt()
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+#define portEND_SWITCHING_ISR( xSwitchRequired ) 	\
+{													\
+extern void vTaskSwitchContext( void );				\
+													\
+	if( xSwitchRequired ) 							\
+	{												\
+		vTaskSwitchContext();						\
+	}												\
+}
+/*-----------------------------------------------------------*/
+
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR91x/ISR_Support.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR91x/ISR_Support.h
new file mode 100644
index 0000000..f9a6466
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR91x/ISR_Support.h
@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	EXTERN pxCurrentTCB
+	EXTERN ulCriticalNesting
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Context save and restore macro definitions
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+portSAVE_CONTEXT MACRO
+
+	; Push R0 as we are going to use the register. 					
+	STMDB	SP!, {R0}
+
+	; Set R0 to point to the task stack pointer. 					
+	STMDB	SP, {SP}^
+	NOP
+	SUB		SP, SP, #4
+	LDMIA	SP!, {R0}
+
+	; Push the return address onto the stack. 						
+	STMDB	R0!, {LR}
+
+	; Now we have saved LR we can use it instead of R0. 				
+	MOV		LR, R0
+
+	; Pop R0 so we can save it onto the system mode stack. 			
+	LDMIA	SP!, {R0}
+
+	; Push all the system mode registers onto the task stack. 		
+	STMDB	LR, {R0-LR}^
+	NOP
+	SUB		LR, LR, #60
+
+	; Push the SPSR onto the task stack. 							
+	MRS		R0, SPSR
+	STMDB	LR!, {R0}
+
+	LDR		R0, =ulCriticalNesting 
+	LDR		R0, [R0]
+	STMDB	LR!, {R0}
+
+	; Store the new top of stack for the task. 						
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	STR		LR, [R0]
+
+	ENDM
+
+
+portRESTORE_CONTEXT MACRO
+
+	; Set the LR to the task stack. 									
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	LDR		LR, [R0]
+
+	; The critical nesting depth is the first item on the stack. 	
+	; Load it into the ulCriticalNesting variable. 					
+	LDR		R0, =ulCriticalNesting
+	LDMFD	LR!, {R1}
+	STR		R1, [R0]
+
+	; Get the SPSR from the stack. 									
+	LDMFD	LR!, {R0}
+	MSR		SPSR_cxsf, R0
+
+	; Restore all system mode registers for the task. 				
+	LDMFD	LR, {R0-R14}^
+	NOP
+
+	; Restore the return address. 									
+	LDR		LR, [LR, #+60]
+
+	; And return - correcting the offset in the LR to obtain the 	
+	; correct address. 												
+	SUBS	PC, LR, #4
+
+	ENDM
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR91x/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR91x/port.c
new file mode 100644
index 0000000..2a4c44e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR91x/port.c
@@ -0,0 +1,421 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ST STR91x ARM9
+ * port.
+ *----------------------------------------------------------*/
+
+/* Library includes. */
+#include "91x_lib.h"
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef configUSE_WATCHDOG_TICK
+	#error configUSE_WATCHDOG_TICK must be set to either 1 or 0 in FreeRTOSConfig.h to use either the Watchdog or timer 2 to generate the tick interrupt respectively.
+#endif
+
+/* Constants required to setup the initial stack. */
+#ifndef _RUN_TASK_IN_ARM_MODE_
+	#define portINITIAL_SPSR			( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */
+#else
+	#define portINITIAL_SPSR 			( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#endif
+
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
+
+#ifndef abs
+	#define abs(x) ((x)>0 ? (x) : -(x))
+#endif
+
+/**
+ * Toggle a led using the following algorithm:
+ * if ( GPIO_ReadBit(GPIO9, GPIO_Pin_2) )
+ * {
+ *   GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET );
+ * }
+ * else
+ * {
+ *   GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET );
+ * }
+ *
+ */
+#define TOGGLE_LED(port,pin) 									\
+	if ( ((((port)->DR[(pin)<<2])) & (pin)) != Bit_RESET ) 		\
+	{															\
+    	(port)->DR[(pin) <<2] = 0x00;							\
+  	}															\
+  	else														\
+	{															\
+    	(port)->DR[(pin) <<2] = (pin);							\
+  	}
+
+
+/*-----------------------------------------------------------*/
+
+/* Setup the watchdog to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* ulCriticalNesting will get set to zero when the first task starts.  It
+cannot be initialised to 0 as this will cause interrupts to be enabled
+during the kernel initialisation process. */
+uint32_t ulCriticalNesting = ( uint32_t ) 9999;
+
+/* Tick interrupt routines for cooperative and preemptive operation
+respectively.  The preemptive version is not defined as __irq as it is called
+from an asm wrapper function. */
+void WDG_IRQHandler( void );
+
+/* VIC interrupt default handler. */
+static void prvDefaultHandler( void );
+
+#if configUSE_WATCHDOG_TICK == 0
+	/* Used to update the OCR timer register */
+	static u16 s_nPulseLength;
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* To ensure asserts in tasks.c don't fail, although in this case the assert
+	is not really required. */
+	pxTopOfStack--;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The status register is set for system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+	pxTopOfStack--;
+
+	/* Interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+
+	return pxTopOfStack;	
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+/* This function is called from an asm wrapper, so does not require the __irq
+keyword. */
+#if configUSE_WATCHDOG_TICK == 1
+
+	static void prvFindFactors(u32 n, u16 *a, u32 *b)
+	{
+		/* This function is copied from the ST STR7 library and is
+		copyright STMicroelectronics.  Reproduced with permission. */
+	
+		u32 b0;
+		u16 a0;
+		int32_t err, err_min=n;
+	
+		*a = a0 = ((n-1)/65536ul) + 1;
+		*b = b0 = n / *a;
+	
+		for (; *a <= 256; (*a)++)
+		{
+			*b = n / *a;
+			err = (int32_t)*a * (int32_t)*b - (int32_t)n;
+			if (abs(err) > (*a / 2))
+			{
+				(*b)++;
+				err = (int32_t)*a * (int32_t)*b - (int32_t)n;
+			}
+			if (abs(err) < abs(err_min))
+			{
+				err_min = err;
+				a0 = *a;
+				b0 = *b;
+				if (err == 0) break;
+			}
+		}
+	
+		*a = a0;
+		*b = b0;
+	}
+	/*-----------------------------------------------------------*/
+
+	static void prvSetupTimerInterrupt( void )
+	{
+	WDG_InitTypeDef xWdg;
+	uint16_t a;
+	uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ, b;
+	
+		/* Configure the watchdog as a free running timer that generates a
+		periodic interrupt. */
+	
+		SCU_APBPeriphClockConfig( __WDG, ENABLE );
+		WDG_DeInit();
+		WDG_StructInit(&xWdg);
+		prvFindFactors( n, &a, &b );
+		xWdg.WDG_Prescaler = a - 1;
+		xWdg.WDG_Preload = b - 1;
+		WDG_Init( &xWdg );
+		WDG_ITConfig(ENABLE);
+		
+		/* Configure the VIC for the WDG interrupt. */
+		VIC_Config( WDG_ITLine, VIC_IRQ, 10 );
+		VIC_ITCmd( WDG_ITLine, ENABLE );
+		
+		/* Install the default handlers for both VIC's. */
+		VIC0->DVAR = ( uint32_t ) prvDefaultHandler;
+		VIC1->DVAR = ( uint32_t ) prvDefaultHandler;
+		
+		WDG_Cmd(ENABLE);
+	}
+	/*-----------------------------------------------------------*/
+
+	void WDG_IRQHandler( void )
+	{
+		{
+			/* Increment the tick counter. */
+			if( xTaskIncrementTick() != pdFALSE )
+			{		
+				/* Select a new task to execute. */
+				vTaskSwitchContext();
+			}
+		
+			/* Clear the interrupt in the watchdog. */
+			WDG->SR &= ~0x0001;
+		}
+	}
+
+#else
+
+	static void prvFindFactors(u32 n, u8 *a, u16 *b)
+	{
+		/* This function is copied from the ST STR7 library and is
+		copyright STMicroelectronics.  Reproduced with permission. */
+	
+		u16 b0;
+		u8 a0;
+		int32_t err, err_min=n;
+	
+	
+		*a = a0 = ((n-1)/256) + 1;
+		*b = b0 = n / *a;
+	
+		for (; *a <= 256; (*a)++)
+		{
+			*b = n / *a;
+			err = (int32_t)*a * (int32_t)*b - (int32_t)n;
+			if (abs(err) > (*a / 2))
+			{
+				(*b)++;
+				err = (int32_t)*a * (int32_t)*b - (int32_t)n;
+			}
+			if (abs(err) < abs(err_min))
+			{
+				err_min = err;
+				a0 = *a;
+				b0 = *b;
+				if (err == 0) break;
+			}
+		}
+	
+		*a = a0;
+		*b = b0;
+	}
+	/*-----------------------------------------------------------*/
+
+	static void prvSetupTimerInterrupt( void )
+	{
+		uint8_t a;
+		uint16_t b;
+		uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ;
+		
+		TIM_InitTypeDef timer;
+		
+		SCU_APBPeriphClockConfig( __TIM23, ENABLE );
+		TIM_DeInit(TIM2);
+		TIM_StructInit(&timer);
+		prvFindFactors( n, &a, &b );
+		
+		timer.TIM_Mode           = TIM_OCM_CHANNEL_1;
+		timer.TIM_OC1_Modes      = TIM_TIMING;
+		timer.TIM_Clock_Source   = TIM_CLK_APB;
+		timer.TIM_Clock_Edge     = TIM_CLK_EDGE_RISING;
+		timer.TIM_Prescaler      = a-1;
+		timer.TIM_Pulse_Level_1  = TIM_HIGH;
+		timer.TIM_Pulse_Length_1 = s_nPulseLength  = b-1;
+		
+		TIM_Init (TIM2, &timer);
+		TIM_ITConfig(TIM2, TIM_IT_OC1, ENABLE);
+		/* Configure the VIC for the WDG interrupt. */
+		VIC_Config( TIM2_ITLine, VIC_IRQ, 10 );
+		VIC_ITCmd( TIM2_ITLine, ENABLE );
+		
+		/* Install the default handlers for both VIC's. */
+		VIC0->DVAR = ( uint32_t ) prvDefaultHandler;
+		VIC1->DVAR = ( uint32_t ) prvDefaultHandler;
+		
+		TIM_CounterCmd(TIM2, TIM_CLEAR);
+		TIM_CounterCmd(TIM2, TIM_START);
+	}
+	/*-----------------------------------------------------------*/
+
+	void TIM2_IRQHandler( void )
+	{
+		/* Reset the timer counter to avioid overflow. */
+		TIM2->OC1R += s_nPulseLength;
+		
+		/* Increment the tick counter. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Select a new task to run. */
+			vTaskSwitchContext();
+		}
+		
+		/* Clear the interrupt in the watchdog. */
+		TIM2->SR &= ~TIM_FLAG_OC1;
+	}
+
+#endif /* USE_WATCHDOG_TICK */
+
+/*-----------------------------------------------------------*/
+
+__arm __interwork void vPortEnterCritical( void )
+{
+	/* Disable interrupts first! */
+	portDISABLE_INTERRUPTS();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+__arm __interwork void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			portENABLE_INTERRUPTS();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvDefaultHandler( void )
+{
+}
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR91x/portasm.s79 b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR91x/portasm.s79
new file mode 100644
index 0000000..8ee30f7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR91x/portasm.s79
@@ -0,0 +1,60 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+		RSEG ICODE:CODE
+		CODE32
+
+	EXTERN vTaskSwitchContext
+
+	PUBLIC vPortYieldProcessor
+	PUBLIC vPortStartFirstTask
+
+#include "ISR_Support.h"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Starting the first task is just a matter of restoring the context that
+; was created by pxPortInitialiseStack().
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortStartFirstTask:
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Manual context switch function.  This is the SWI hander.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortYieldProcessor:
+	ADD		LR, LR, #4			; Add 4 to the LR to make the LR appear exactly
+								; as if the context was saved during and IRQ
+								; handler.
+								
+	portSAVE_CONTEXT			; Save the context of the current task...
+	LDR R0, =vTaskSwitchContext	; before selecting the next task to execute.
+	MOV     lr, pc
+	BX R0
+	portRESTORE_CONTEXT			; Restore the context of the selected task.
+
+	END
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR91x/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR91x/portmacro.h
new file mode 100644
index 0000000..ba63916
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/STR91x/portmacro.h
@@ -0,0 +1,114 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Type definitions. */
+#define portCHAR			char
+#define portFLOAT			float
+#define portDOUBLE			double
+#define portLONG			long
+#define portSHORT			short
+#define portSTACK_TYPE		uint32_t
+#define portBASE_TYPE		long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+#define portYIELD()					asm ( "SWI 0" )
+#define portNOP()					asm ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+__arm __interwork void vPortEnterCritical( void );
+__arm __interwork void vPortExitCritical( void );
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+
+#define portDISABLE_INTERRUPTS()	__disable_interrupt()
+#define portENABLE_INTERRUPTS()		__enable_interrupt()
+
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+#define portEND_SWITCHING_ISR( xSwitchRequired ) 	\
+{													\
+extern void vTaskSwitchContext( void );				\
+													\
+	if( xSwitchRequired ) 							\
+	{												\
+		vTaskSwitchContext();						\
+	}												\
+}
+/*-----------------------------------------------------------*/
+
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/V850ES/ISR_Support.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/V850ES/ISR_Support.h
new file mode 100644
index 0000000..8ee843a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/V850ES/ISR_Support.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	EXTERN pxCurrentTCB
+	EXTERN usCriticalNesting
+
+#include "FreeRTOSConfig.h"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Context save and restore macro definitions
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+portSAVE_CONTEXT MACRO
+
+    add     -0x0C,sp			; prepare stack to save necessary values
+    st.w    lp,8[sp]			; store LP to stack
+    stsr    0,r31
+    st.w    lp,4[sp]			; store EIPC to stack
+    stsr    1,lp
+    st.w    lp,0[sp]			; store EIPSW to stack
+#if configDATA_MODE == 1                                        ; Using the Tiny data model
+    prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers
+    sst.w   r19,72[ep]
+    sst.w   r18,68[ep]
+    sst.w   r17,64[ep]
+    sst.w   r16,60[ep]
+    sst.w   r15,56[ep]
+    sst.w   r14,52[ep]
+    sst.w   r13,48[ep]
+    sst.w   r12,44[ep]
+    sst.w   r11,40[ep]
+    sst.w   r10,36[ep]
+    sst.w   r9,32[ep]
+    sst.w   r8,28[ep]
+    sst.w   r7,24[ep]
+    sst.w   r6,20[ep]
+    sst.w   r5,16[ep]
+    sst.w   r4,12[ep]
+#else                                                           ; Using the Small/Large data model
+    prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp     ; save general purpose registers
+    sst.w   r19,68[ep]
+    sst.w   r18,64[ep]
+    sst.w   r17,60[ep]
+    sst.w   r16,56[ep]
+    sst.w   r15,52[ep]
+    sst.w   r14,48[ep]
+    sst.w   r13,44[ep]
+    sst.w   r12,40[ep]
+    sst.w   r11,36[ep]
+    sst.w   r10,32[ep]
+    sst.w   r9,28[ep]
+    sst.w   r8,24[ep]
+    sst.w   r7,20[ep]
+    sst.w   r6,16[ep]
+    sst.w   r5,12[ep]
+#endif /* configDATA_MODE */
+    sst.w   r2,8[ep]
+    sst.w   r1,4[ep]
+    MOVHI   hi1(usCriticalNesting),r0,r1	; save usCriticalNesting value to stack
+    ld.w    lw1(usCriticalNesting)[r1],r2
+    sst.w   r2,0[ep]
+    MOVHI   hi1(pxCurrentTCB),r0,r1			; save SP to top of current TCB
+    ld.w    lw1(pxCurrentTCB)[r1],r2
+    st.w    sp,0[r2]
+    ENDM
+
+
+portRESTORE_CONTEXT MACRO
+
+    MOVHI   hi1(pxCurrentTCB),r0,r1			; get Stackpointer address
+    ld.w    lw1(pxCurrentTCB)[r1],sp
+    MOV     sp,r1
+    ld.w    0[r1],sp						; load stackpointer
+    MOV     sp,ep							; set stack pointer to element pointer
+    sld.w   0[ep],r1						; load usCriticalNesting value from stack
+    MOVHI   hi1(usCriticalNesting),r0,r2
+    st.w    r1,lw1(usCriticalNesting)[r2]
+    sld.w   4[ep],r1						; restore general purpose registers
+    sld.w   8[ep],r2
+#if configDATA_MODE == 1					; Using Tiny data model
+    sld.w   12[ep],r4
+    sld.w   16[ep],r5
+    sld.w   20[ep],r6
+    sld.w   24[ep],r7
+    sld.w   28[ep],r8
+    sld.w   32[ep],r9
+    sld.w   36[ep],r10
+    sld.w   40[ep],r11
+    sld.w   44[ep],r12
+    sld.w   48[ep],r13
+    sld.w   52[ep],r14
+    sld.w   56[ep],r15
+    sld.w   60[ep],r16
+    sld.w   64[ep],r17
+    sld.w   68[ep],r18
+    sld.w   72[ep],r19
+    dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30}
+#else										; Using Small/Large data model
+    sld.w   12[ep],r5
+    sld.w   16[ep],r6
+    sld.w   20[ep],r7
+    sld.w   24[ep],r8
+    sld.w   28[ep],r9
+    sld.w   32[ep],r10
+    sld.w   36[ep],r11
+    sld.w   40[ep],r12
+    sld.w   44[ep],r13
+    sld.w   48[ep],r14
+    sld.w   52[ep],r15
+    sld.w   56[ep],r16
+    sld.w   60[ep],r17
+    sld.w   64[ep],r18
+    sld.w   68[ep],r19
+    dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30}
+#endif /* configDATA_MODE */
+    ld.w    0[sp],lp						; restore EIPSW from stack
+    ldsr    lp,1
+    ld.w    4[sp],lp						; restore EIPC from stack
+    ldsr    lp,0
+    ld.w    8[sp],lp						; restore LP from stack
+    add     0x0C,sp							; set SP to right position
+
+    RETI
+
+    ENDM
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/V850ES/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/V850ES/port.c
new file mode 100644
index 0000000..b6e7580
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/V850ES/port.c
@@ -0,0 +1,183 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Critical nesting should be initialised to a non zero value so interrupts don't
+accidentally get enabled before the scheduler is started. */
+#define portINITIAL_CRITICAL_NESTING  (( StackType_t ) 10)
+
+/* The PSW value assigned to tasks when they start to run for the first time. */
+#define portPSW		  (( StackType_t ) 0x00000000)
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/* Keeps track of the nesting level of critical sections. */
+volatile StackType_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
+/*-----------------------------------------------------------*/
+
+/* Sets up the timer to generate the tick interrupt. */
+static void prvSetupTimerInterrupt( void );
+
+/*-----------------------------------------------------------*/
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	*pxTopOfStack = ( StackType_t ) pxCode;          /* Task function start address */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;          /* Task function start address */
+	pxTopOfStack--;
+	*pxTopOfStack = portPSW;                            /* Initial PSW value */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x20202020;      /* Initial Value of R20 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x21212121;      /* Initial Value of R21 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x22222222;      /* Initial Value of R22 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x23232323;      /* Initial Value of R23 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x24242424;      /* Initial Value of R24 */
+	pxTopOfStack--;
+#if (__DATA_MODEL__ == 0) || (__DATA_MODEL__ == 1)
+	*pxTopOfStack = ( StackType_t ) 0x25252525;      /* Initial Value of R25 */
+	pxTopOfStack--;
+#endif /* configDATA_MODE */
+	*pxTopOfStack = ( StackType_t ) 0x26262626;      /* Initial Value of R26 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x27272727;      /* Initial Value of R27 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x28282828;      /* Initial Value of R28 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x29292929;      /* Initial Value of R29 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x30303030;      /* Initial Value of R30 */
+	pxTopOfStack--; 	
+	*pxTopOfStack = ( StackType_t ) 0x19191919;      /* Initial Value of R19 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x18181818;      /* Initial Value of R18 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x17171717;      /* Initial Value of R17 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x16161616;      /* Initial Value of R16 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x15151515;      /* Initial Value of R15 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x14141414;      /* Initial Value of R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x13131313;      /* Initial Value of R13 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;      /* Initial Value of R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x11111111;      /* Initial Value of R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x10101010;      /* Initial Value of R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x99999999;      /* Initial Value of R09 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x88888888;      /* Initial Value of R08 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x77777777;      /* Initial Value of R07 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x66666666;      /* Initial Value of R06 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x55555555;      /* Initial Value of R05 */
+	pxTopOfStack--;
+#if __DATA_MODEL__ == 0 || __DATA_MODEL__ == 1
+	*pxTopOfStack = ( StackType_t ) 0x44444444;      /* Initial Value of R04 */
+	pxTopOfStack--;
+#endif /* configDATA_MODE */
+	*pxTopOfStack = ( StackType_t ) 0x22222222;      /* Initial Value of R02 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pvParameters;    /* R1 is expected to hold the function parameter*/
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;	
+
+	/*
+	 * Return a pointer to the top of the stack we have generated so this can
+	 * be stored in the task control block for the task.
+	 */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Setup the hardware to generate the tick.  Interrupts are disabled when
+	this function is called. */
+	prvSetupTimerInterrupt();
+
+	/* Restore the context of the first task that is going to run. */
+	vPortStart();
+
+	/* Should not get here as the tasks are now running! */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the V850ES/Fx3 port will get stopped.  If required simply
+	disable the tick interrupt here. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.  This uses
+ */
+static void prvSetupTimerInterrupt( void )
+{
+	TM0CE     = 0;	/* TMM0 operation disable */
+	TM0EQMK0  = 1;	/* INTTM0EQ0 interrupt disable */
+	TM0EQIF0  = 0;	/* clear INTTM0EQ0 interrupt flag */
+
+	#ifdef __IAR_V850ES_Fx3__
+	{
+		TM0CMP0   = (((configCPU_CLOCK_HZ / configTICK_RATE_HZ) / 2)-1);    /* divided by 2 because peripherals only run at CPU_CLOCK/2 */
+	}
+	#else
+	{
+		TM0CMP0   = (configCPU_CLOCK_HZ / configTICK_RATE_HZ);	
+	}
+	#endif
+
+	TM0EQIC0 &= 0xF8;
+	TM0CTL0   = 0x00;
+	TM0EQIF0 =  0;	/* clear INTTM0EQ0 interrupt flag */
+	TM0EQMK0 =  0;	/* INTTM0EQ0 interrupt enable */
+	TM0CE =     1;	/* TMM0 operation enable */
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/V850ES/portasm.s85 b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/V850ES/portasm.s85
new file mode 100644
index 0000000..f1393b3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/V850ES/portasm.s85
@@ -0,0 +1,315 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+; Note: Select the correct include files for the device used by the application.
+#include "FreeRTOSConfig.h"
+;------------------------------------------------------------------------------
+
+; Functions used by scheduler
+;------------------------------------------------------------------------------
+    EXTERN    vTaskSwitchContext
+    EXTERN    xTaskIncrementTick
+
+; Variables used by scheduler
+;------------------------------------------------------------------------------
+    EXTERN    pxCurrentTCB
+    EXTERN    usCriticalNesting
+
+; Functions implemented in this file
+;------------------------------------------------------------------------------
+    PUBLIC    vPortYield
+    PUBLIC    vPortStart
+
+; Security ID definition
+;------------------------------------------------------------------------------
+#define	CG_SECURITY0	0FFH
+#define	CG_SECURITY1	0FFH
+#define	CG_SECURITY2	0FFH
+#define	CG_SECURITY3	0FFH
+#define	CG_SECURITY4	0FFH
+#define	CG_SECURITY5	0FFH
+#define	CG_SECURITY6	0FFH
+#define	CG_SECURITY7	0FFH
+#define	CG_SECURITY8	0FFH
+#define	CG_SECURITY9	0FFH
+
+; Tick ISR Prototype
+;------------------------------------------------------------------------------
+        PUBWEAK `??MD_INTTM0EQ0??INTVEC 640`
+        PUBLIC MD_INTTM0EQ0
+
+MD_INTTM0EQ0        SYMBOL "MD_INTTM0EQ0"
+`??MD_INTTM0EQ0??INTVEC 640` SYMBOL "??INTVEC 640", MD_INTTM0EQ0
+
+;------------------------------------------------------------------------------
+;   portSAVE_CONTEXT MACRO
+;   Saves the context of the remaining general purpose registers
+;   and the usCriticalNesting Value of the active Task onto the task stack
+;   saves stack pointer to the TCB
+;------------------------------------------------------------------------------
+portSAVE_CONTEXT MACRO
+#if configDATA_MODE == 1                                        ; Using the Tiny data model
+    prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers
+    sst.w   r19,72[ep]
+    sst.w   r18,68[ep]
+    sst.w   r17,64[ep]
+    sst.w   r16,60[ep]
+    sst.w   r15,56[ep]
+    sst.w   r14,52[ep]
+    sst.w   r13,48[ep]
+    sst.w   r12,44[ep]
+    sst.w   r11,40[ep]
+    sst.w   r10,36[ep]
+    sst.w   r9,32[ep]
+    sst.w   r8,28[ep]
+    sst.w   r7,24[ep]
+    sst.w   r6,20[ep]
+    sst.w   r5,16[ep]
+    sst.w   r4,12[ep]
+#else                                                           ; Using the Small/Large data model
+    prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp     ; save general purpose registers
+    sst.w   r19,68[ep]
+    sst.w   r18,64[ep]
+    sst.w   r17,60[ep]
+    sst.w   r16,56[ep]
+    sst.w   r15,52[ep]
+    sst.w   r14,48[ep]
+    sst.w   r13,44[ep]
+    sst.w   r12,40[ep]
+    sst.w   r11,36[ep]
+    sst.w   r10,32[ep]
+    sst.w   r9,28[ep]
+    sst.w   r8,24[ep]
+    sst.w   r7,20[ep]
+    sst.w   r6,16[ep]
+    sst.w   r5,12[ep]
+#endif /* configDATA_MODE */
+    sst.w   r2,8[ep]
+    sst.w   r1,4[ep]
+    MOVHI   hi1(usCriticalNesting),r0,r1                        ; save usCriticalNesting value to stack
+    ld.w    lw1(usCriticalNesting)[r1],r2
+    sst.w   r2,0[ep]
+    MOVHI   hi1(pxCurrentTCB),r0,r1                             ; save SP to top of current TCB
+    ld.w    lw1(pxCurrentTCB)[r1],r2
+    st.w    sp,0[r2]
+    ENDM
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   portRESTORE_CONTEXT MACRO
+;   Gets stack pointer from the current TCB
+;   Restores the context of the usCriticalNesting value and general purpose
+;   registers of the selected task from the task stack
+;------------------------------------------------------------------------------
+portRESTORE_CONTEXT MACRO
+    MOVHI   hi1(pxCurrentTCB),r0,r1         ; get Stackpointer address
+    ld.w    lw1(pxCurrentTCB)[r1],sp
+    MOV     sp,r1
+    ld.w    0[r1],sp                        ; load stackpointer
+    MOV     sp,ep                           ; set stack pointer to element pointer
+    sld.w   0[ep],r1                        ; load usCriticalNesting value from stack
+    MOVHI   hi1(usCriticalNesting),r0,r2
+    st.w    r1,lw1(usCriticalNesting)[r2]
+    sld.w   4[ep],r1                        ; restore general purpose registers
+    sld.w   8[ep],r2
+#if configDATA_MODE == 1                    ; Using Tiny data model
+    sld.w   12[ep],r4
+    sld.w   16[ep],r5
+    sld.w   20[ep],r6
+    sld.w   24[ep],r7
+    sld.w   28[ep],r8
+    sld.w   32[ep],r9
+    sld.w   36[ep],r10
+    sld.w   40[ep],r11
+    sld.w   44[ep],r12
+    sld.w   48[ep],r13
+    sld.w   52[ep],r14
+    sld.w   56[ep],r15
+    sld.w   60[ep],r16
+    sld.w   64[ep],r17
+    sld.w   68[ep],r18
+    sld.w   72[ep],r19
+    dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30}
+#else                                       ; Using Small/Large data model
+    sld.w   12[ep],r5
+    sld.w   16[ep],r6
+    sld.w   20[ep],r7
+    sld.w   24[ep],r8
+    sld.w   28[ep],r9
+    sld.w   32[ep],r10
+    sld.w   36[ep],r11
+    sld.w   40[ep],r12
+    sld.w   44[ep],r13
+    sld.w   48[ep],r14
+    sld.w   52[ep],r15
+    sld.w   56[ep],r16
+    sld.w   60[ep],r17
+    sld.w   64[ep],r18
+    sld.w   68[ep],r19
+    dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30}
+#endif /* configDATA_MODE */
+    ENDM
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   Restore the context of the first task that is going to run.
+;
+;   Input:  NONE
+;
+;   Call:   CALL    vPortStart
+;
+;   Output: NONE
+;------------------------------------------------------------------------------
+    RSEG CODE:CODE
+vPortStart:
+    portRESTORE_CONTEXT	                    ; Restore the context of whichever task the ...
+    ld.w    0[sp],lp
+    ldsr    lp,5                            ; restore PSW
+    DI
+    ld.w    4[sp],lp                        ; restore LP
+    ld.w    8[sp],lp                        ; restore LP
+    ADD     0x0C,sp                         ; set SP to right position
+    EI
+    jmp     [lp]
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   Port Yield function to check for a Task switch in the cooperative and
+;   preemptive mode
+;
+;   Input:  NONE
+;
+;   Call:   CALL    vPortYield
+;
+;   Output: NONE
+;------------------------------------------------------------------------------
+
+	RSEG CODE:CODE
+vPortYield:
+
+    add     -0x0C,sp                          ; prepare stack to save necessary values
+    st.w    lp,8[sp]                        ; store LP to stack
+    stsr    0,r31
+    st.w    lp,4[sp]                        ; store EIPC to stack
+    stsr    1,lp
+    st.w    lp,0[sp]                        ; store EIPSW to stack
+    portSAVE_CONTEXT		            ; Save the context of the current task.
+    jarl    vTaskSwitchContext,lp           ; Call the scheduler.
+    portRESTORE_CONTEXT		            ; Restore the context of whichever task the ...
+                		            ; ... scheduler decided should run.
+	ld.w    0[sp],lp                        ; restore EIPSW from stack
+    ldsr    lp,1
+    ld.w    4[sp],lp                        ; restore EIPC from stack
+    ldsr    lp,0
+    ld.w    8[sp],lp                        ; restore LP from stack
+    add     0x0C,sp                         ; set SP to right position
+
+    RETI
+
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   Perform the necessary steps of the Tick Count Increment and Task Switch
+;   depending on the chosen kernel configuration
+;
+;   Input:  NONE
+;
+;   Call:   ISR
+;
+;   Output: NONE
+;------------------------------------------------------------------------------
+#if configUSE_PREEMPTION == 1               ; use preemptive kernel mode
+
+MD_INTTM0EQ0:
+
+    add     -0x0C,sp                          ; prepare stack to save necessary values
+    st.w    lp,8[sp]                        ; store LP to stack
+    stsr    0,r31
+    st.w    lp,4[sp]                        ; store EIPC to stack
+    stsr    1,lp
+    st.w    lp,0[sp]                        ; store EIPSW to stack
+    portSAVE_CONTEXT		            ; Save the context of the current task.
+    jarl    xTaskIncrementTick,lp           ; Call the timer tick function.
+    jarl    vTaskSwitchContext,lp           ; Call the scheduler.
+    portRESTORE_CONTEXT		            ; Restore the context of whichever task the ...
+                		            ; ... scheduler decided should run.
+    ld.w    0[sp],lp                        ; restore EIPSW from stack
+    ldsr    lp,1
+    ld.w    4[sp],lp                        ; restore EIPC from stack
+    ldsr    lp,0
+    ld.w    8[sp],lp                        ; restore LP from stack
+    add     0x0C,sp                         ; set SP to right position
+
+    RETI
+;------------------------------------------------------------------------------
+#else                                       ; use cooperative kernel mode
+
+MD_INTTM0EQ0:
+    prepare {lp,ep},8,sp
+    sst.w   r1,4[ep]
+    sst.w   r5,0[ep]
+    jarl    xTaskIncrementTick,lp           ; Call the timer tick function.
+    sld.w   0[ep],r5
+    sld.w   4[ep],r1
+    dispose 8,{lp,ep}
+    RETI
+#endif /* configUSE_PREEMPTION */
+
+;------------------------------------------------------------------------------
+        COMMON INTVEC:CODE:ROOT(2)
+        ORG 640
+`??MD_INTTM0EQ0??INTVEC 640`:
+        JR MD_INTTM0EQ0
+
+        RSEG NEAR_ID:CONST:SORT:NOROOT(2)
+`?`:
+        DW 10
+
+      COMMON INTVEC:CODE:ROOT(2)
+      ORG 40H
+`??vPortYield??INTVEC 40`:
+        JR vPortYield
+
+;------------------------------------------------------------------------------
+; set microcontroller security ID
+
+      COMMON INTVEC:CODE:ROOT(2)
+      ORG 70H
+`SECUID`:
+      DB CG_SECURITY0
+      DB CG_SECURITY1
+      DB CG_SECURITY2
+      DB CG_SECURITY3
+      DB CG_SECURITY4
+      DB CG_SECURITY5
+      DB CG_SECURITY6
+      DB CG_SECURITY7
+      DB CG_SECURITY8
+      DB CG_SECURITY9
+
+
+      END
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/V850ES/portasm_Fx3.s85 b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/V850ES/portasm_Fx3.s85
new file mode 100644
index 0000000..62cf09f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/V850ES/portasm_Fx3.s85
@@ -0,0 +1,335 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+; Note: Select the correct include files for the device used by the application.
+#include "FreeRTOSConfig.h"
+;------------------------------------------------------------------------------
+
+; Functions used by scheduler
+;------------------------------------------------------------------------------
+    EXTERN    vTaskSwitchContext
+    EXTERN    xTaskIncrementTick
+
+; Variables used by scheduler
+;------------------------------------------------------------------------------
+    EXTERN    pxCurrentTCB
+    EXTERN    usCriticalNesting
+
+; Functions implemented in this file
+;------------------------------------------------------------------------------
+    PUBLIC    vPortYield
+    PUBLIC    vPortStart
+
+; Security ID definition
+;------------------------------------------------------------------------------
+#define	CG_SECURITY0	0FFH
+#define	CG_SECURITY1	0FFH
+#define	CG_SECURITY2	0FFH
+#define	CG_SECURITY3	0FFH
+#define	CG_SECURITY4	0FFH
+#define	CG_SECURITY5	0FFH
+#define	CG_SECURITY6	0FFH
+#define	CG_SECURITY7	0FFH
+#define	CG_SECURITY8	0FFH
+#define	CG_SECURITY9	0FFH
+
+; Option Byte definitions
+;------------------------------------------------------------------------------
+#define	CG_OPTION7A	0x00
+#define	CG_OPTION7B	0x04
+#define	OPT7C		0x00
+#define	OPT7D		0x00
+#define	OPT7E		0x00
+#define	OPT7F		0x00
+
+; Tick ISR Prototype
+;------------------------------------------------------------------------------
+        PUBWEAK `??MD_INTTM0EQ0??INTVEC 608`
+        PUBLIC MD_INTTM0EQ0
+
+MD_INTTM0EQ0        SYMBOL "MD_INTTM0EQ0"
+`??MD_INTTM0EQ0??INTVEC 608` SYMBOL "??INTVEC 608", MD_INTTM0EQ0
+
+;------------------------------------------------------------------------------
+;   portSAVE_CONTEXT MACRO
+;   Saves the context of the remaining general purpose registers
+;   and the usCriticalNesting Value of the active Task onto the task stack
+;   saves stack pointer to the TCB
+;------------------------------------------------------------------------------
+portSAVE_CONTEXT MACRO
+#if configDATA_MODE == 1                                        ; Using the Tiny data model
+    prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers
+    sst.w   r19,72[ep]
+    sst.w   r18,68[ep]
+    sst.w   r17,64[ep]
+    sst.w   r16,60[ep]
+    sst.w   r15,56[ep]
+    sst.w   r14,52[ep]
+    sst.w   r13,48[ep]
+    sst.w   r12,44[ep]
+    sst.w   r11,40[ep]
+    sst.w   r10,36[ep]
+    sst.w   r9,32[ep]
+    sst.w   r8,28[ep]
+    sst.w   r7,24[ep]
+    sst.w   r6,20[ep]
+    sst.w   r5,16[ep]
+    sst.w   r4,12[ep]
+#else                                                           ; Using the Small/Large data model
+    prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp     ; save general purpose registers
+    sst.w   r19,68[ep]
+    sst.w   r18,64[ep]
+    sst.w   r17,60[ep]
+    sst.w   r16,56[ep]
+    sst.w   r15,52[ep]
+    sst.w   r14,48[ep]
+    sst.w   r13,44[ep]
+    sst.w   r12,40[ep]
+    sst.w   r11,36[ep]
+    sst.w   r10,32[ep]
+    sst.w   r9,28[ep]
+    sst.w   r8,24[ep]
+    sst.w   r7,20[ep]
+    sst.w   r6,16[ep]
+    sst.w   r5,12[ep]
+#endif /* configDATA_MODE */
+    sst.w   r2,8[ep]
+    sst.w   r1,4[ep]
+    MOVHI   hi1(usCriticalNesting),r0,r1                        ; save usCriticalNesting value to stack
+    ld.w    lw1(usCriticalNesting)[r1],r2
+    sst.w   r2,0[ep]
+    MOVHI   hi1(pxCurrentTCB),r0,r1                             ; save SP to top of current TCB
+    ld.w    lw1(pxCurrentTCB)[r1],r2
+    st.w    sp,0[r2]
+    ENDM
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   portRESTORE_CONTEXT MACRO
+;   Gets stack pointer from the current TCB
+;   Restores the context of the usCriticalNesting value and general purpose
+;   registers of the selected task from the task stack
+;------------------------------------------------------------------------------
+portRESTORE_CONTEXT MACRO
+    MOVHI   hi1(pxCurrentTCB),r0,r1         ; get Stackpointer address
+    ld.w    lw1(pxCurrentTCB)[r1],sp
+    MOV     sp,r1
+    ld.w    0[r1],sp                        ; load stackpointer
+    MOV     sp,ep                           ; set stack pointer to element pointer
+    sld.w   0[ep],r1                        ; load usCriticalNesting value from stack
+    MOVHI   hi1(usCriticalNesting),r0,r2
+    st.w    r1,lw1(usCriticalNesting)[r2]
+    sld.w   4[ep],r1                        ; restore general purpose registers
+    sld.w   8[ep],r2
+#if configDATA_MODE == 1                    ; Using Tiny data model
+    sld.w   12[ep],r4
+    sld.w   16[ep],r5
+    sld.w   20[ep],r6
+    sld.w   24[ep],r7
+    sld.w   28[ep],r8
+    sld.w   32[ep],r9
+    sld.w   36[ep],r10
+    sld.w   40[ep],r11
+    sld.w   44[ep],r12
+    sld.w   48[ep],r13
+    sld.w   52[ep],r14
+    sld.w   56[ep],r15
+    sld.w   60[ep],r16
+    sld.w   64[ep],r17
+    sld.w   68[ep],r18
+    sld.w   72[ep],r19
+    dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30}
+#else                                       ; Using Small/Large data model
+    sld.w   12[ep],r5
+    sld.w   16[ep],r6
+    sld.w   20[ep],r7
+    sld.w   24[ep],r8
+    sld.w   28[ep],r9
+    sld.w   32[ep],r10
+    sld.w   36[ep],r11
+    sld.w   40[ep],r12
+    sld.w   44[ep],r13
+    sld.w   48[ep],r14
+    sld.w   52[ep],r15
+    sld.w   56[ep],r16
+    sld.w   60[ep],r17
+    sld.w   64[ep],r18
+    sld.w   68[ep],r19
+    dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30}
+#endif /* configDATA_MODE */
+    ENDM
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   Restore the context of the first task that is going to run.
+;
+;   Input:  NONE
+;
+;   Call:   CALL    vPortStart
+;
+;   Output: NONE
+;------------------------------------------------------------------------------
+    RSEG CODE:CODE
+vPortStart:
+    portRESTORE_CONTEXT	                    ; Restore the context of whichever task the ...
+    ld.w    0[sp],lp
+    ldsr    lp,5                            ; restore PSW
+    DI
+    ld.w    4[sp],lp                        ; restore LP
+    ld.w    8[sp],lp                        ; restore LP
+    ADD     0x0C,sp                         ; set SP to right position
+    EI
+    jmp     [lp]
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   Port Yield function to check for a Task switch in the cooperative and
+;   preemptive mode
+;
+;   Input:  NONE
+;
+;   Call:   CALL    vPortYield
+;
+;   Output: NONE
+;------------------------------------------------------------------------------
+
+	RSEG CODE:CODE
+vPortYield:
+
+    add     -0x0C,sp                          ; prepare stack to save necessary values
+    st.w    lp,8[sp]                        ; store LP to stack
+    stsr    0,r31
+    st.w    lp,4[sp]                        ; store EIPC to stack
+    stsr    1,lp
+    st.w    lp,0[sp]                        ; store EIPSW to stack
+    portSAVE_CONTEXT		            ; Save the context of the current task.
+    jarl    vTaskSwitchContext,lp           ; Call the scheduler.
+    portRESTORE_CONTEXT		            ; Restore the context of whichever task the ...
+                		            ; ... scheduler decided should run.
+	ld.w    0[sp],lp                        ; restore EIPSW from stack
+    ldsr    lp,1
+    ld.w    4[sp],lp                        ; restore EIPC from stack
+    ldsr    lp,0
+    ld.w    8[sp],lp                        ; restore LP from stack
+    add     0x0C,sp                         ; set SP to right position
+
+    RETI
+
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   Perform the necessary steps of the Tick Count Increment and Task Switch
+;   depending on the chosen kernel configuration
+;
+;   Input:  NONE
+;
+;   Call:   ISR
+;
+;   Output: NONE
+;------------------------------------------------------------------------------
+#if configUSE_PREEMPTION == 1               ; use preemptive kernel mode
+
+MD_INTTM0EQ0:
+
+    add     -0x0C,sp                          ; prepare stack to save necessary values
+    st.w    lp,8[sp]                        ; store LP to stack
+    stsr    0,r31
+    st.w    lp,4[sp]                        ; store EIPC to stack
+    stsr    1,lp
+    st.w    lp,0[sp]                        ; store EIPSW to stack
+    portSAVE_CONTEXT		            ; Save the context of the current task.
+    jarl    xTaskIncrementTick,lp           ; Call the timer tick function.
+    jarl    vTaskSwitchContext,lp           ; Call the scheduler.
+    portRESTORE_CONTEXT		            ; Restore the context of whichever task the ...
+                		            ; ... scheduler decided should run.
+    ld.w    0[sp],lp                        ; restore EIPSW from stack
+    ldsr    lp,1
+    ld.w    4[sp],lp                        ; restore EIPC from stack
+    ldsr    lp,0
+    ld.w    8[sp],lp                        ; restore LP from stack
+    add     0x0C,sp                         ; set SP to right position
+
+    RETI
+;------------------------------------------------------------------------------
+#else                                       ; use cooperative kernel mode
+
+MD_INTTM0EQ0:
+    prepare {lp,ep},8,sp
+    sst.w   r1,4[ep]
+    sst.w   r5,0[ep]
+    jarl    xTaskIncrementTick,lp           ; Call the timer tick function.
+    sld.w   0[ep],r5
+    sld.w   4[ep],r1
+    dispose 8,{lp,ep}
+    RETI
+#endif /* configUSE_PREEMPTION */
+
+;------------------------------------------------------------------------------
+        COMMON INTVEC:CODE:ROOT(2)
+        ORG 608
+`??MD_INTTM0EQ0??INTVEC 608`:
+        JR MD_INTTM0EQ0
+
+        RSEG NEAR_ID:CONST:SORT:NOROOT(2)
+`?`:
+        DW 10
+
+      COMMON INTVEC:CODE:ROOT(2)
+      ORG 40H
+`??vPortYield??INTVEC 40`:
+        JR vPortYield
+
+;------------------------------------------------------------------------------
+; set microcontroller security ID
+
+      COMMON INTVEC:CODE:ROOT(2)
+      ORG 70H
+`SECUID`:
+      DB CG_SECURITY0
+      DB CG_SECURITY1
+      DB CG_SECURITY2
+      DB CG_SECURITY3
+      DB CG_SECURITY4
+      DB CG_SECURITY5
+      DB CG_SECURITY6
+      DB CG_SECURITY7
+      DB CG_SECURITY8
+      DB CG_SECURITY9
+
+;------------------------------------------------------------------------------
+; set microcontroller option bytes
+
+      COMMON INTVEC:CODE:ROOT(2)
+      ORG 7AH
+`OPTBYTES`:
+      DB CG_OPTION7A
+      DB CG_OPTION7B
+      DB OPT7C
+      DB OPT7D
+      DB OPT7E
+      DB OPT7F
+
+      END
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/V850ES/portasm_Hx2.s85 b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/V850ES/portasm_Hx2.s85
new file mode 100644
index 0000000..4be6fb3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/V850ES/portasm_Hx2.s85
@@ -0,0 +1,350 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+; Note: Select the correct include files for the device used by the application.
+#include "FreeRTOSConfig.h"
+;------------------------------------------------------------------------------
+
+; Functions used by scheduler
+;------------------------------------------------------------------------------
+    EXTERN    vTaskSwitchContext
+    EXTERN    xTaskIncrementTick
+
+; Variables used by scheduler
+;------------------------------------------------------------------------------
+    EXTERN    pxCurrentTCB
+    EXTERN    usCriticalNesting
+
+; Functions implemented in this file
+;------------------------------------------------------------------------------
+    PUBLIC    vPortYield
+    PUBLIC    vPortStart
+
+; Security ID definition
+;------------------------------------------------------------------------------
+#define	CG_SECURITY0	0FFH
+#define	CG_SECURITY1	0FFH
+#define	CG_SECURITY2	0FFH
+#define	CG_SECURITY3	0FFH
+#define	CG_SECURITY4	0FFH
+#define	CG_SECURITY5	0FFH
+#define	CG_SECURITY6	0FFH
+#define	CG_SECURITY7	0FFH
+#define	CG_SECURITY8	0FFH
+#define	CG_SECURITY9	0FFH
+
+; Tick ISR Prototype
+;------------------------------------------------------------------------------
+        PUBWEAK `??MD_INTTM0EQ0??INTVEC 544`
+        PUBLIC MD_INTTM0EQ0
+
+MD_INTTM0EQ0        SYMBOL "MD_INTTM0EQ0"
+`??MD_INTTM0EQ0??INTVEC 544` SYMBOL "??INTVEC 544", MD_INTTM0EQ0
+
+;------------------------------------------------------------------------------
+;   portSAVE_CONTEXT MACRO
+;   Saves the context of the remaining general purpose registers
+;   and the usCriticalNesting Value of the active Task onto the task stack
+;   saves stack pointer to the TCB
+;------------------------------------------------------------------------------
+portSAVE_CONTEXT MACRO
+#if configDATA_MODE == 1                                        ; Using the Tiny data model
+    prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers
+    sst.w   r19,72[ep]
+    sst.w   r18,68[ep]
+    sst.w   r17,64[ep]
+    sst.w   r16,60[ep]
+    sst.w   r15,56[ep]
+    sst.w   r14,52[ep]
+    sst.w   r13,48[ep]
+    sst.w   r12,44[ep]
+    sst.w   r11,40[ep]
+    sst.w   r10,36[ep]
+    sst.w   r9,32[ep]
+    sst.w   r8,28[ep]
+    sst.w   r7,24[ep]
+    sst.w   r6,20[ep]
+    sst.w   r5,16[ep]
+    sst.w   r4,12[ep]
+#else                                                           ; Using the Small/Large data model
+    prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp     ; save general purpose registers
+    sst.w   r19,68[ep]
+    sst.w   r18,64[ep]
+    sst.w   r17,60[ep]
+    sst.w   r16,56[ep]
+    sst.w   r15,52[ep]
+    sst.w   r14,48[ep]
+    sst.w   r13,44[ep]
+    sst.w   r12,40[ep]
+    sst.w   r11,36[ep]
+    sst.w   r10,32[ep]
+    sst.w   r9,28[ep]
+    sst.w   r8,24[ep]
+    sst.w   r7,20[ep]
+    sst.w   r6,16[ep]
+    sst.w   r5,12[ep]
+#endif /* configDATA_MODE */
+    sst.w   r2,8[ep]
+    sst.w   r1,4[ep]
+    MOVHI   hi1(usCriticalNesting),r0,r1                        ; save usCriticalNesting value to stack
+    ld.w    lw1(usCriticalNesting)[r1],r2
+    sst.w   r2,0[ep]
+    MOVHI   hi1(pxCurrentTCB),r0,r1                             ; save SP to top of current TCB
+    ld.w    lw1(pxCurrentTCB)[r1],r2
+    st.w    sp,0[r2]
+    ENDM
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   portRESTORE_CONTEXT MACRO
+;   Gets stack pointer from the current TCB
+;   Restores the context of the usCriticalNesting value and general purpose
+;   registers of the selected task from the task stack
+;------------------------------------------------------------------------------
+portRESTORE_CONTEXT MACRO
+    MOVHI   hi1(pxCurrentTCB),r0,r1         ; get Stackpointer address
+    ld.w    lw1(pxCurrentTCB)[r1],sp
+    MOV     sp,r1
+    ld.w    0[r1],sp                        ; load stackpointer
+    MOV     sp,ep                           ; set stack pointer to element pointer
+    sld.w   0[ep],r1                        ; load usCriticalNesting value from stack
+    MOVHI   hi1(usCriticalNesting),r0,r2
+    st.w    r1,lw1(usCriticalNesting)[r2]
+    sld.w   4[ep],r1                        ; restore general purpose registers
+    sld.w   8[ep],r2
+#if configDATA_MODE == 1                    ; Using Tiny data model
+    sld.w   12[ep],r4
+    sld.w   16[ep],r5
+    sld.w   20[ep],r6
+    sld.w   24[ep],r7
+    sld.w   28[ep],r8
+    sld.w   32[ep],r9
+    sld.w   36[ep],r10
+    sld.w   40[ep],r11
+    sld.w   44[ep],r12
+    sld.w   48[ep],r13
+    sld.w   52[ep],r14
+    sld.w   56[ep],r15
+    sld.w   60[ep],r16
+    sld.w   64[ep],r17
+    sld.w   68[ep],r18
+    sld.w   72[ep],r19
+    dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30}
+#else                                       ; Using Small/Large data model
+    sld.w   12[ep],r5
+    sld.w   16[ep],r6
+    sld.w   20[ep],r7
+    sld.w   24[ep],r8
+    sld.w   28[ep],r9
+    sld.w   32[ep],r10
+    sld.w   36[ep],r11
+    sld.w   40[ep],r12
+    sld.w   44[ep],r13
+    sld.w   48[ep],r14
+    sld.w   52[ep],r15
+    sld.w   56[ep],r16
+    sld.w   60[ep],r17
+    sld.w   64[ep],r18
+    sld.w   68[ep],r19
+    dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30}
+#endif /* configDATA_MODE */
+    ENDM
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   Restore the context of the first task that is going to run.
+;
+;   Input:  NONE
+;
+;   Call:   CALL    vPortStart
+;
+;   Output: NONE
+;------------------------------------------------------------------------------
+    RSEG CODE:CODE
+vPortStart:
+    portRESTORE_CONTEXT	                    ; Restore the context of whichever task the ...
+    ld.w    0[sp],lp
+    ldsr    lp,5                            ; restore PSW
+    DI
+    ld.w    4[sp],lp                        ; restore LP
+    ld.w    8[sp],lp                        ; restore LP
+    ADD     0x0C,sp                         ; set SP to right position
+    EI
+    jmp     [lp]
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   Port Yield function to check for a Task switch in the cooperative and
+;   preemptive mode
+;
+;   Input:  NONE
+;
+;   Call:   CALL    vPortYield
+;
+;   Output: NONE
+;------------------------------------------------------------------------------
+
+	RSEG CODE:CODE
+vPortYield:
+
+    add     -0x0C,sp                          ; prepare stack to save necessary values
+    st.w    lp,8[sp]                        ; store LP to stack
+    stsr    0,r31
+    st.w    lp,4[sp]                        ; store EIPC to stack
+    stsr    1,lp
+    st.w    lp,0[sp]                        ; store EIPSW to stack
+    portSAVE_CONTEXT		            ; Save the context of the current task.
+    jarl    vTaskSwitchContext,lp           ; Call the scheduler.
+    portRESTORE_CONTEXT		            ; Restore the context of whichever task the ...
+                		            ; ... scheduler decided should run.
+	ld.w    0[sp],lp                        ; restore EIPSW from stack
+    ldsr    lp,1
+    ld.w    4[sp],lp                        ; restore EIPC from stack
+    ldsr    lp,0
+    ld.w    8[sp],lp                        ; restore LP from stack
+    add     0x0C,sp                         ; set SP to right position
+
+    RETI
+
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   Perform the necessary steps of the Tick Count Increment and Task Switch
+;   depending on the chosen kernel configuration
+;
+;   Input:  NONE
+;
+;   Call:   ISR
+;
+;   Output: NONE
+;------------------------------------------------------------------------------
+#if configUSE_PREEMPTION == 1               ; use preemptive kernel mode
+
+MD_INTTM0EQ0:
+
+    add     -0x0C,sp                          ; prepare stack to save necessary values
+    st.w    lp,8[sp]                        ; store LP to stack
+    stsr    0,r31
+    st.w    lp,4[sp]                        ; store EIPC to stack
+    stsr    1,lp
+    st.w    lp,0[sp]                        ; store EIPSW to stack
+    portSAVE_CONTEXT		            ; Save the context of the current task.
+    jarl    xTaskIncrementTick,lp           ; Call the timer tick function.
+    jarl    vTaskSwitchContext,lp           ; Call the scheduler.
+    portRESTORE_CONTEXT		            ; Restore the context of whichever task the ...
+                		            ; ... scheduler decided should run.
+    ld.w    0[sp],lp                        ; restore EIPSW from stack
+    ldsr    lp,1
+    ld.w    4[sp],lp                        ; restore EIPC from stack
+    ldsr    lp,0
+    ld.w    8[sp],lp                        ; restore LP from stack
+    add     0x0C,sp                         ; set SP to right position
+
+    RETI
+;------------------------------------------------------------------------------
+#else                                       ; use cooperative kernel mode
+
+MD_INTTM0EQ0:
+    prepare {lp,ep},8,sp
+    sst.w   r1,4[ep]
+    sst.w   r5,0[ep]
+    jarl    xTaskIncrementTick,lp           ; Call the timer tick function.
+    sld.w   0[ep],r5
+    sld.w   4[ep],r1
+    dispose 8,{lp,ep}
+    RETI
+#endif /* configUSE_PREEMPTION */
+
+;------------------------------------------------------------------------------
+        COMMON INTVEC:CODE:ROOT(2)
+        ORG 544
+`??MD_INTTM0EQ0??INTVEC 544`:
+        JR MD_INTTM0EQ0
+
+        RSEG NEAR_ID:CONST:SORT:NOROOT(2)
+`?`:
+        DW 10
+
+      COMMON INTVEC:CODE:ROOT(2)
+      ORG 40H
+`??vPortYield??INTVEC 40`:
+        JR vPortYield
+
+;------------------------------------------------------------------------------
+; set microcontroller security ID
+
+      COMMON INTVEC:CODE:ROOT(2)
+      ORG 70H
+`SECUID`:
+      DB CG_SECURITY0
+      DB CG_SECURITY1
+      DB CG_SECURITY2
+      DB CG_SECURITY3
+      DB CG_SECURITY4
+      DB CG_SECURITY5
+      DB CG_SECURITY6
+      DB CG_SECURITY7
+      DB CG_SECURITY8
+      DB CG_SECURITY9
+
+
+; set microcontroller Option bytes
+
+      COMMON INTVEC:CODE:ROOT(2)
+      ORG 122
+`OPTBYTES`:
+      DB 0xFD
+      DB 0xFF
+      DB 0xFF
+      DB 0xFF
+      DB 0xFF
+      DB 0xFF
+
+#if configOCD_USAGE == 1
+
+      COMMON   INTVEC:CODE:ROOT(4)
+      ORG      0x230
+      PUBLIC ROM_INT2
+ROM_INT2:
+      DB 0xff, 0xff, 0xff, 0xff
+      DB 0xff, 0xff, 0xff, 0xff
+      DB 0xff, 0xff, 0xff, 0xff
+      DB 0xff, 0xff, 0xff, 0xff
+
+
+      COMMON   INTVEC:CODE:ROOT(4)
+      ORG      0x60
+      PUBLIC   ROM_INT
+ROM_INT:
+      DB 0xff, 0xff, 0xff, 0xff
+      DB 0xff, 0xff, 0xff, 0xff
+      DB 0xff, 0xff, 0xff, 0xff
+      DB 0xff, 0xff, 0xff, 0xff
+
+#endif /* configOCD_USAGE */
+
+      END
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/V850ES/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/V850ES/portmacro.h
new file mode 100644
index 0000000..5a97624
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/IAR/V850ES/portmacro.h
@@ -0,0 +1,135 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  unsigned int
+#define portBASE_TYPE   int
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if (configUSE_16_BIT_TICKS==1)
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS() __asm ( "DI" )
+#define portENABLE_INTERRUPTS()	 __asm ( "EI" )
+/*-----------------------------------------------------------*/
+
+/* Critical section control macros. */
+#define portNO_CRITICAL_SECTION_NESTING		( ( UBaseType_t ) 0 )
+
+#define portENTER_CRITICAL()														\
+{																					\
+extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting;						\
+																					\
+	portDISABLE_INTERRUPTS();														\
+																					\
+	/* Now interrupts are disabled ulCriticalNesting can be accessed */				\
+	/* directly.  Increment ulCriticalNesting to keep a count of how many */		\
+	/* times portENTER_CRITICAL() has been called. */								\
+	usCriticalNesting++;															\
+}
+
+#define portEXIT_CRITICAL()															\
+{																					\
+extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting;						\
+																					\
+	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )						\
+	{																				\
+		/* Decrement the nesting count as we are leaving a critical section. */		\
+		usCriticalNesting--;														\
+																					\
+		/* If the nesting level has reached zero then interrupts should be */		\
+		/* re-enabled. */															\
+		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )					\
+		{																			\
+			portENABLE_INTERRUPTS();												\
+		}																			\
+	}																				\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+extern void vPortYield( void );
+extern void vPortStart( void );
+extern void portSAVE_CONTEXT( void );
+extern void portRESTORE_CONTEXT( void );
+#define portYIELD()	__asm ( "trap 0" )
+#define portNOP()	__asm ( "NOP" )
+extern void vTaskSwitchContext( void );
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext()
+
+/*-----------------------------------------------------------*/
+
+/* Hardwware specifics. */
+#define portBYTE_ALIGNMENT	4
+#define portSTACK_GROWTH	( -1 )
+#define portTICK_PERIOD_MS	( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Keil/See-also-the-RVDS-directory.txt b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Keil/See-also-the-RVDS-directory.txt
new file mode 100644
index 0000000..bd7fab7
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Keil/See-also-the-RVDS-directory.txt
@@ -0,0 +1 @@
+Nothing to see here.
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC18F/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC18F/port.c
new file mode 100644
index 0000000..8a2919d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC18F/port.c
@@ -0,0 +1,615 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* 
+Changes between V1.2.4 and V1.2.5
+
+	+ Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global 
+	  interrupt flag setting.  Using the two bits defined within
+	  portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
+	  before the test was performed.
+
+Changes from V1.2.5
+
+	+ Set the interrupt vector address to 0x08.  Previously it was at the
+	  incorrect address for compatibility mode of 0x18.
+
+Changes from V2.1.1
+
+	+ PCLATU and PCLATH are now saved as part of the context.  This allows
+	  function pointers to be used within tasks.  Thanks to Javier Espeche
+	  for the enhancement. 
+
+Changes from V2.3.1
+
+	+ TABLAT is now saved as part of the task context.
+	
+Changes from V3.2.0
+
+	+ TBLPTRU is now initialised to zero as the MPLAB compiler expects this
+	  value and does not write to the register.
+*/
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPLAB library include file. */
+#include "timers.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the PIC port.
+ *----------------------------------------------------------*/
+
+/* Hardware setup for tick. */
+#define portTIMER_FOSC_SCALE			( ( uint32_t ) 4 )
+
+/* Initial interrupt enable state for newly created tasks.  This value is
+copied into INTCON when a task switches in for the first time. */
+#define portINITAL_INTERRUPT_STATE			0xc0
+
+/* Just the bit within INTCON for the global interrupt flag. */
+#define portGLOBAL_INTERRUPT_FLAG			0x80
+
+/* Constant used for context switch macro when we require the interrupt 
+enable state to be unchanged when the interrupted task is switched back in. */
+#define portINTERRUPTS_UNCHANGED			0x00
+
+/* Some memory areas get saved as part of the task context.  These memory
+area's get used by the compiler for temporary storage, especially when 
+performing mathematical operations, or when using 32bit data types.  This
+constant defines the size of memory area which must be saved. */
+#define portCOMPILER_MANAGED_MEMORY_SIZE	( ( uint8_t ) 0x13 )
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/* IO port constants. */
+#define portBIT_SET		( ( uint8_t ) 1 )
+#define portBIT_CLEAR	( ( uint8_t ) 0 )
+
+/*
+ * The serial port ISR's are defined in serial.c, but are called from portable
+ * as they use the same vector as the tick ISR.
+ */
+void vSerialTxISR( void );
+void vSerialRxISR( void );
+
+/*
+ * Perform hardware setup to enable ticks.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/* 
+ * ISR to maintain the tick, and perform tick context switches if the
+ * preemptive scheduler is being used.
+ */
+static void prvTickISR( void );
+
+/*
+ * ISR placed on the low priority vector.  This calls the appropriate ISR for
+ * the actual interrupt.
+ */
+static void prvLowInterrupt( void );
+
+/* 
+ * Macro that pushes all the registers that make up the context of a task onto
+ * the stack, then saves the new top of stack into the TCB.
+ * 
+ * If this is called from an ISR then the interrupt enable bits must have been 
+ * set for the ISR to ever get called.  Therefore we want to save the INTCON
+ * register with the enable bits forced to be set - and ucForcedInterruptFlags 
+ * must contain these bit settings.  This means the interrupts will again be
+ * enabled when the interrupted task is switched back in.
+ *
+ * If this is called from a manual context switch (i.e. from a call to yield),
+ * then we want to save the INTCON so it is restored with its current state,
+ * and ucForcedInterruptFlags must be 0.  This allows a yield from within
+ * a critical section.
+ *
+ * The compiler uses some locations at the bottom of the memory for temporary
+ * storage during math and other computations.  This is especially true if
+ * 32bit data types are utilised (as they are by the scheduler).  The .tmpdata
+ * and MATH_DATA sections have to be stored in there entirety as part of a task
+ * context.  This macro stores from data address 0x00 to 
+ * portCOMPILER_MANAGED_MEMORY_SIZE.  This is sufficient for the demo 
+ * applications but you should check the map file for your project to ensure 
+ * this is sufficient for your needs.  It is not clear whether this size is 
+ * fixed for all compilations or has the potential to be program specific.
+ */
+#define	portSAVE_CONTEXT( ucForcedInterruptFlags )								\
+{																				\
+	_asm																		\
+		/* Save the status and WREG registers first, as these will get modified	\
+		by the operations below. */												\
+		MOVFF	WREG, PREINC1													\
+		MOVFF   STATUS, PREINC1													\
+		/* Save the INTCON register with the appropriate bits forced if			\
+		necessary - as described above. */										\
+		MOVFF	INTCON, WREG													\
+		IORLW	ucForcedInterruptFlags											\
+		MOVFF	WREG, PREINC1													\
+	_endasm																		\
+																				\
+	portDISABLE_INTERRUPTS();													\
+																				\
+	_asm																		\
+		/* Store the necessary registers to the stack. */						\
+		MOVFF	BSR, PREINC1													\
+		MOVFF	FSR2L, PREINC1													\
+		MOVFF	FSR2H, PREINC1													\
+		MOVFF	FSR0L, PREINC1													\
+		MOVFF	FSR0H, PREINC1													\
+		MOVFF	TABLAT, PREINC1													\
+		MOVFF	TBLPTRU, PREINC1												\
+		MOVFF	TBLPTRH, PREINC1												\
+		MOVFF	TBLPTRL, PREINC1												\
+		MOVFF	PRODH, PREINC1													\
+		MOVFF	PRODL, PREINC1													\
+		MOVFF	PCLATU, PREINC1													\
+		MOVFF	PCLATH, PREINC1													\
+		/* Store the .tempdata and MATH_DATA areas as described above. */		\
+		CLRF	FSR0L, 0														\
+		CLRF	FSR0H, 0														\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	INDF0, PREINC1													\
+		MOVFF	FSR0L, PREINC1													\
+		MOVFF	FSR0H, PREINC1													\
+		/* Store the hardware stack pointer in a temp register before we		\
+		modify it. */															\
+		MOVFF	STKPTR, FSR0L													\
+	_endasm																		\
+																				\
+		/* Store each address from the hardware stack. */						\
+		while( STKPTR > ( uint8_t ) 0 )								\
+		{																		\
+			_asm																\
+				MOVFF	TOSL, PREINC1											\
+				MOVFF	TOSH, PREINC1											\
+				MOVFF	TOSU, PREINC1											\
+				POP																\
+			_endasm																\
+		}																		\
+																				\
+	_asm																		\
+		/* Store the number of addresses on the hardware stack (from the		\
+		temporary register). */													\
+		MOVFF	FSR0L, PREINC1													\
+		MOVF	PREINC1, 1, 0													\
+	_endasm																		\
+																				\
+	/* Save the new top of the software stack in the TCB. */					\
+	_asm																		\
+		MOVFF	pxCurrentTCB, FSR0L												\
+		MOVFF	pxCurrentTCB + 1, FSR0H											\
+		MOVFF	FSR1L, POSTINC0													\
+		MOVFF	FSR1H, POSTINC0													\
+	_endasm																		\
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * This is the reverse of portSAVE_CONTEXT.  See portSAVE_CONTEXT for more
+ * details.
+ */
+#define portRESTORE_CONTEXT()													\
+{																				\
+	_asm																		\
+		/* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */					\
+		MOVFF	pxCurrentTCB, FSR0L												\
+		MOVFF	pxCurrentTCB + 1, FSR0H											\
+																				\
+		/* De-reference FSR0 to set the address it holds into FSR1.				\
+		(i.e. *( pxCurrentTCB->pxTopOfStack ) ). */								\
+		MOVFF	POSTINC0, FSR1L													\
+		MOVFF	POSTINC0, FSR1H													\
+																				\
+		/* How many return addresses are there on the hardware stack?  Discard	\
+		the first byte as we are pointing to the next free space. */			\
+		MOVFF	POSTDEC1, FSR0L													\
+		MOVFF	POSTDEC1, FSR0L													\
+	_endasm																		\
+																				\
+	/* Fill the hardware stack from our software stack. */						\
+	STKPTR = 0;																	\
+																				\
+	while( STKPTR < FSR0L )														\
+	{																			\
+		_asm																	\
+			PUSH																\
+			MOVF	POSTDEC1, 0, 0												\
+			MOVWF	TOSU, 0														\
+			MOVF	POSTDEC1, 0, 0												\
+			MOVWF	TOSH, 0														\
+			MOVF	POSTDEC1, 0, 0												\
+			MOVWF	TOSL, 0														\
+		_endasm																	\
+	}																			\
+																				\
+	_asm																		\
+		/* Restore the .tmpdata and MATH_DATA memory. */						\
+		MOVFF	POSTDEC1, FSR0H													\
+		MOVFF	POSTDEC1, FSR0L													\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, INDF0													\
+		/* Restore the other registers forming the tasks context. */			\
+		MOVFF	POSTDEC1, PCLATH												\
+		MOVFF	POSTDEC1, PCLATU												\
+		MOVFF	POSTDEC1, PRODL													\
+		MOVFF	POSTDEC1, PRODH													\
+		MOVFF	POSTDEC1, TBLPTRL												\
+		MOVFF	POSTDEC1, TBLPTRH												\
+		MOVFF	POSTDEC1, TBLPTRU												\
+		MOVFF	POSTDEC1, TABLAT												\
+		MOVFF	POSTDEC1, FSR0H													\
+		MOVFF	POSTDEC1, FSR0L													\
+		MOVFF	POSTDEC1, FSR2H													\
+		MOVFF	POSTDEC1, FSR2L													\
+		MOVFF	POSTDEC1, BSR													\
+		/* The next byte is the INTCON register.  Read this into WREG as some	\
+		manipulation is required. */											\
+		MOVFF	POSTDEC1, WREG													\
+	_endasm																		\
+																				\
+	/* From the INTCON register, only the interrupt enable bits form part		\
+	of the tasks context.  It is perfectly legitimate for another task to		\
+	have modified any other bits.  We therefore only restore the top two bits.	\
+	*/																			\
+	if( WREG & portGLOBAL_INTERRUPT_FLAG )										\
+	{																			\
+		_asm 																	\
+			MOVFF	POSTDEC1, STATUS											\
+			MOVFF	POSTDEC1, WREG												\
+			/* Return enabling interrupts. */									\
+			RETFIE	0															\
+		_endasm																	\
+	}																			\
+	else																		\
+	{																			\
+		_asm 																	\
+			MOVFF	POSTDEC1, STATUS											\
+			MOVFF	POSTDEC1, WREG												\
+			/* Return without effecting interrupts.  The context may have		\
+			been saved from a critical region. */								\
+			RETURN	0															\
+		_endasm																	\
+	}																			\
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint32_t ulAddress;
+uint8_t ucBlock;
+
+	/* Place a few bytes of known values on the bottom of the stack. 
+	This is just useful for debugging. */
+
+	*pxTopOfStack = 0x11;
+	pxTopOfStack++;
+	*pxTopOfStack = 0x22;
+	pxTopOfStack++;
+	*pxTopOfStack = 0x33;
+	pxTopOfStack++;
+
+
+	/* Simulate how the stack would look after a call to vPortYield() generated
+	by the compiler. 
+
+	First store the function parameters.  This is where the task will expect to
+	find them when it starts running. */
+	ulAddress = ( uint32_t ) pvParameters;
+	*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
+	pxTopOfStack++;
+
+	ulAddress >>= 8;
+	*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
+	pxTopOfStack++;
+
+	/* Next we just leave a space.  When a context is saved the stack pointer
+	is incremented before it is used so as not to corrupt whatever the stack
+	pointer is actually pointing to.  This is especially necessary during 
+	function epilogue code generated by the compiler. */
+	*pxTopOfStack = 0x44;
+	pxTopOfStack++;
+
+	/* Next are all the registers that form part of the task context. */
+	
+	*pxTopOfStack = ( StackType_t ) 0x66; /* WREG. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0xcc; /* Status. */
+	pxTopOfStack++;
+
+	/* INTCON is saved with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITAL_INTERRUPT_STATE; /* INTCON */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x11; /* BSR. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x22; /* FSR2L. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x33; /* FSR2H. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x44; /* FSR0L. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x55; /* FSR0H. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x66; /* TABLAT. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x00; /* TBLPTRU. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x88; /* TBLPTRUH. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x99; /* TBLPTRUL. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0xaa; /* PRODH. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0xbb; /* PRODL. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x00; /* PCLATU. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x00; /* PCLATH. */
+	pxTopOfStack++;
+
+	/* Next the .tmpdata and MATH_DATA sections. */
+	for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ )
+	{
+		*pxTopOfStack = ( StackType_t ) ucBlock;
+		*pxTopOfStack++;
+	}
+
+	/* Store the top of the global data section. */
+	*pxTopOfStack = ( StackType_t ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x00; /* High. */
+	pxTopOfStack++;
+
+	/* The only function return address so far is the address of the 
+	task. */
+	ulAddress = ( uint32_t ) pxCode;
+
+	/* TOS low. */
+	*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
+	pxTopOfStack++;
+	ulAddress >>= 8;
+
+	/* TOS high. */
+	*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
+	pxTopOfStack++;
+	ulAddress >>= 8;
+
+	/* TOS even higher. */
+	*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
+	pxTopOfStack++;
+
+	/* Store the number of return addresses on the hardware stack - so far only
+	the address of the task entry point. */
+	*pxTopOfStack = ( StackType_t ) 1;
+	pxTopOfStack++;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Setup a timer for the tick ISR is using the preemptive scheduler. */
+	prvSetupTimerInterrupt(); 
+
+	/* Restore the context of the first task to run. */
+	portRESTORE_CONTEXT();
+
+	/* Should not get here.  Use the function name to stop compiler warnings. */
+	( void ) prvLowInterrupt;
+	( void ) prvTickISR;
+
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the scheduler for the PIC port will get stopped
+	once running.  If required disable the tick interrupt here, then return 
+	to xPortStartScheduler(). */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch.  This is similar to the tick context switch,
+ * but does not increment the tick count.  It must be identical to the
+ * tick context switch in how it stores the stack of a task.
+ */
+void vPortYield( void )
+{
+	/* This can get called with interrupts either enabled or disabled.  We
+	will save the INTCON register with the interrupt enable bits unmodified. */
+	portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
+
+	/* Switch to the highest priority task that is ready to run. */
+	vTaskSwitchContext();
+
+	/* Start executing the task we have just switched to. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Vector for ISR.  Nothing here must alter any registers!
+ */
+#pragma code high_vector=0x08
+static void prvLowInterrupt( void )
+{
+	/* Was the interrupt the tick? */
+	if( PIR1bits.CCP1IF )
+	{		
+		_asm
+			goto prvTickISR
+		_endasm
+	}
+
+	/* Was the interrupt a byte being received? */
+	if( PIR1bits.RCIF )
+	{
+		_asm
+			goto vSerialRxISR
+		_endasm
+	}
+
+	/* Was the interrupt the Tx register becoming empty? */
+	if( PIR1bits.TXIF )
+	{
+		if( PIE1bits.TXIE )
+		{
+			_asm
+				goto vSerialTxISR
+			_endasm
+		}
+	}
+}
+#pragma code
+
+/*-----------------------------------------------------------*/
+
+/*
+ * ISR for the tick.
+ * This increments the tick count and, if using the preemptive scheduler, 
+ * performs a context switch.  This must be identical to the manual 
+ * context switch in how it stores the context of a task. 
+ */
+static void prvTickISR( void )
+{
+	/* Interrupts must have been enabled for the ISR to fire, so we have to 
+	save the context with interrupts enabled. */
+	portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );
+	PIR1bits.CCP1IF = 0;
+
+	/* Maintain the tick count. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		/* Switch to the highest priority task that is ready to run. */
+		vTaskSwitchContext();
+	}
+
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup a timer for a regular tick.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+const uint32_t ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
+uint32_t ulCompareValue;
+uint8_t ucByte;
+
+	/* Interrupts are disabled when this function is called.
+
+	Setup CCP1 to provide the tick interrupt using a compare match on timer
+	1.
+
+	Clear the time count then setup timer. */
+	TMR1H = ( uint8_t ) 0x00;
+	TMR1L = ( uint8_t ) 0x00;
+
+	/* Set the compare match value. */
+	ulCompareValue = ulConstCompareValue;
+	CCPR1L = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
+	ulCompareValue >>= ( uint32_t ) 8;
+	CCPR1H = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );	
+
+	CCP1CONbits.CCP1M0 = portBIT_SET;	/*< Compare match mode. */
+	CCP1CONbits.CCP1M1 = portBIT_SET;	/*< Compare match mode. */
+	CCP1CONbits.CCP1M2 = portBIT_CLEAR;	/*< Compare match mode. */
+	CCP1CONbits.CCP1M3 = portBIT_SET;	/*< Compare match mode. */
+	PIE1bits.CCP1IE = portBIT_SET;		/*< Interrupt enable. */
+
+	/* We are only going to use the global interrupt bit, so set the peripheral
+	bit to true. */
+	INTCONbits.GIEL = portBIT_SET;
+
+	/* Provided library function for setting up the timer that will produce the
+	tick. */
+	OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC18F/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC18F/portmacro.h
new file mode 100644
index 0000000..e238b8f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC18F/portmacro.h
@@ -0,0 +1,112 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	uint8_t
+#define portBASE_TYPE	char
+
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			1
+#define portGLOBAL_INT_ENABLE_BIT	0x80
+#define portSTACK_GROWTH			1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#define portDISABLE_INTERRUPTS()	INTCONbits.GIEH = 0;
+#define portENABLE_INTERRUPTS()		INTCONbits.GIEH = 1;
+
+/* Push the INTCON register onto the stack, then disable interrupts. */
+#define portENTER_CRITICAL()		POSTINC1 = INTCON;				\
+									INTCONbits.GIEH = 0;
+
+/* Retrieve the INTCON register from the stack, and enable interrupts
+if they were saved as being enabled.  Don't modify any other bits
+within the INTCON register as these may have lagitimately have been
+modified within the critical region. */
+#define portEXIT_CRITICAL()			_asm									\
+										MOVF	POSTDEC1, 1, 0				\
+									_endasm									\
+									if( INDF1 & portGLOBAL_INT_ENABLE_BIT )	\
+									{										\
+										portENABLE_INTERRUPTS();			\
+									}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+extern void vPortYield( void );
+#define portYIELD()				vPortYield()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Required by the kernel aware debugger. */
+#ifdef __DEBUG
+	#define portREMOVE_STATIC_QUALIFIER
+#endif
+
+
+#define portNOP()				_asm	\
+									NOP \
+								_endasm
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC18F/stdio.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC18F/stdio.h
new file mode 100644
index 0000000..e69de29
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/port.c
new file mode 100644
index 0000000..3861975
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/port.c
@@ -0,0 +1,333 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+	Changes from V4.2.1
+
+	+ Introduced the configKERNEL_INTERRUPT_PRIORITY definition.
+*/
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the PIC24 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Hardware specifics. */
+#define portBIT_SET 1
+#define portTIMER_PRESCALE 8
+#define portINITIAL_SR	0
+
+/* Defined for backward compatability with project created prior to
+FreeRTOS.org V4.3.0. */
+#ifndef configKERNEL_INTERRUPT_PRIORITY
+	#define configKERNEL_INTERRUPT_PRIORITY 1
+#endif
+
+/* Use _T1Interrupt as the interrupt handler name if the application writer has
+not provided their own. */
+#ifndef configTICK_INTERRUPT_HANDLER
+	#define configTICK_INTERRUPT_HANDLER _T1Interrupt
+#endif /* configTICK_INTERRUPT_HANDLER */
+
+/* The program counter is only 23 bits. */
+#define portUNUSED_PR_BITS	0x7f
+
+/* Records the nesting depth of calls to portENTER_CRITICAL(). */
+UBaseType_t uxCriticalNesting = 0xef;
+
+#if configKERNEL_INTERRUPT_PRIORITY != 1
+	#error If configKERNEL_INTERRUPT_PRIORITY is not 1 then the #32 in the following macros needs changing to equal the portINTERRUPT_BITS value, which is ( configKERNEL_INTERRUPT_PRIORITY << 5 )
+#endif
+
+#if defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ )
+
+    #ifdef __HAS_EDS__
+		#define portRESTORE_CONTEXT()																						\
+					asm volatile(	"MOV	_pxCurrentTCB, W0		\n"	/* Restore the stack pointer for the task. */		\
+							"MOV	[W0], W15				\n"																\
+							"POP	W0						\n"	/* Restore the critical nesting counter for the task. */	\
+							"MOV	W0, _uxCriticalNesting	\n"																\
+							"POP	DSWPAG					\n"																\
+							"POP    DSRPAG					\n"																\
+							"POP	CORCON					\n"																\
+							"POP	TBLPAG					\n"																\
+							"POP	RCOUNT					\n"	/* Restore the registers from the stack. */					\
+							"POP	W14						\n"																\
+							"POP.D	W12						\n"																\
+							"POP.D	W10						\n"																\
+							"POP.D	W8						\n"																\
+							"POP.D	W6						\n"																\
+							"POP.D	W4						\n"																\
+							"POP.D	W2						\n"																\
+							"POP.D	W0						\n"																\
+							"POP	SR						  " );
+	#else /* __HAS_EDS__ */
+		#define portRESTORE_CONTEXT()																						\
+			asm volatile(	"MOV	_pxCurrentTCB, W0		\n"	/* Restore the stack pointer for the task. */				\
+							"MOV	[W0], W15				\n"																\
+							"POP	W0						\n"	/* Restore the critical nesting counter for the task. */	\
+							"MOV	W0, _uxCriticalNesting	\n"																\
+							"POP	PSVPAG					\n"																\
+							"POP	CORCON					\n"																\
+							"POP	TBLPAG					\n"																\
+							"POP	RCOUNT					\n"	/* Restore the registers from the stack. */					\
+							"POP	W14						\n"																\
+							"POP.D	W12						\n"																\
+							"POP.D	W10						\n"																\
+							"POP.D	W8						\n"																\
+							"POP.D	W6						\n"																\
+							"POP.D	W4						\n"																\
+							"POP.D	W2						\n"																\
+							"POP.D	W0						\n"																\
+							"POP	SR						  " );
+		#endif /* __HAS_EDS__ */
+#endif /* MPLAB_PIC24_PORT */
+
+#if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ )
+
+	#define portRESTORE_CONTEXT()																						\
+		asm volatile(	"MOV	_pxCurrentTCB, W0		\n"	/* Restore the stack pointer for the task. */				\
+						"MOV	[W0], W15				\n"																\
+						"POP	W0						\n"	/* Restore the critical nesting counter for the task. */	\
+						"MOV	W0, _uxCriticalNesting	\n"																\
+						"POP	PSVPAG					\n"																\
+						"POP	CORCON					\n"																\
+						"POP	DOENDH					\n"																\
+						"POP	DOENDL					\n"																\
+						"POP	DOSTARTH				\n"																\
+						"POP	DOSTARTL				\n"																\
+						"POP	DCOUNT					\n"																\
+						"POP	ACCBU					\n"																\
+						"POP	ACCBH					\n"																\
+						"POP	ACCBL					\n"																\
+						"POP	ACCAU					\n"																\
+						"POP	ACCAH					\n"																\
+						"POP	ACCAL					\n"																\
+						"POP	TBLPAG					\n"																\
+						"POP	RCOUNT					\n"	/* Restore the registers from the stack. */					\
+						"POP	W14						\n"																\
+						"POP.D	W12						\n"																\
+						"POP.D	W10						\n"																\
+						"POP.D	W8						\n"																\
+						"POP.D	W6						\n"																\
+						"POP.D	W4						\n"																\
+						"POP.D	W2						\n"																\
+						"POP.D	W0						\n"																\
+						"POP	SR						  " );
+
+#endif /* MPLAB_DSPIC_PORT */
+
+#ifndef portRESTORE_CONTEXT
+	#error Unrecognised device selected
+
+	/* Note:  dsPIC parts with EDS are not supported as there is no easy way to
+	recover the hardware stacked copies for DOCOUNT, DOHIGH, DOLOW. */
+#endif
+
+/*
+ * Setup the timer used to generate the tick interrupt.
+ */
+void vApplicationSetupTickTimerInterrupt( void );
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint16_t usCode;
+UBaseType_t i;
+
+const StackType_t xInitialStack[] =
+{
+	0x1111,	/* W1 */
+	0x2222, /* W2 */
+	0x3333, /* W3 */
+	0x4444, /* W4 */
+	0x5555, /* W5 */
+	0x6666, /* W6 */
+	0x7777, /* W7 */
+	0x8888, /* W8 */
+	0x9999, /* W9 */
+	0xaaaa, /* W10 */
+	0xbbbb, /* W11 */
+	0xcccc, /* W12 */
+	0xdddd, /* W13 */
+	0xeeee, /* W14 */
+	0xcdce, /* RCOUNT */
+	0xabac, /* TBLPAG */
+
+	/* dsPIC specific registers. */
+	#ifdef MPLAB_DSPIC_PORT
+		0x0202, /* ACCAL */
+		0x0303, /* ACCAH */
+		0x0404, /* ACCAU */
+		0x0505, /* ACCBL */
+		0x0606, /* ACCBH */
+		0x0707, /* ACCBU */
+		0x0808, /* DCOUNT */
+		0x090a, /* DOSTARTL */
+		0x1010, /* DOSTARTH */
+		0x1110, /* DOENDL */
+		0x1212, /* DOENDH */
+	#endif
+};
+
+	/* Setup the stack as if a yield had occurred.
+
+	Save the low bytes of the program counter. */
+	usCode = ( uint16_t ) pxCode;
+	*pxTopOfStack = ( StackType_t ) usCode;
+	pxTopOfStack++;
+
+	/* Save the high byte of the program counter.  This will always be zero
+	here as it is passed in a 16bit pointer.  If the address is greater than
+	16 bits then the pointer will point to a jump table. */
+	*pxTopOfStack = ( StackType_t ) 0;
+	pxTopOfStack++;
+
+	/* Status register with interrupts enabled. */
+	*pxTopOfStack = portINITIAL_SR;
+	pxTopOfStack++;
+
+	/* Parameters are passed in W0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;
+	pxTopOfStack++;
+
+	for( i = 0; i < ( sizeof( xInitialStack ) / sizeof( StackType_t ) ); i++ )
+	{
+		*pxTopOfStack = xInitialStack[ i ];
+		pxTopOfStack++;
+	}
+
+	*pxTopOfStack = CORCON;
+	pxTopOfStack++;
+
+	#if defined(__HAS_EDS__)
+		*pxTopOfStack = DSRPAG;
+		pxTopOfStack++;
+		*pxTopOfStack = DSWPAG;
+		pxTopOfStack++;
+	#else /* __HAS_EDS__ */
+		*pxTopOfStack = PSVPAG;
+		pxTopOfStack++;
+	#endif /* __HAS_EDS__ */
+
+	/* Finally the critical nesting depth. */
+	*pxTopOfStack = 0x00;
+	pxTopOfStack++;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Setup a timer for the tick ISR. */
+	vApplicationSetupTickTimerInterrupt();
+
+	/* Restore the context of the first task to run. */
+	portRESTORE_CONTEXT();
+
+	/* Simulate the end of the yield function. */
+	asm volatile ( "return" );
+
+	/* Should not reach here. */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup a timer for a regular tick.
+ */
+__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
+{
+const uint32_t ulCompareMatch = ( ( configCPU_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1;
+
+	/* Prescale of 8. */
+	T1CON = 0;
+	TMR1 = 0;
+
+	PR1 = ( uint16_t ) ulCompareMatch;
+
+	/* Setup timer 1 interrupt priority. */
+	IPC0bits.T1IP = configKERNEL_INTERRUPT_PRIORITY;
+
+	/* Clear the interrupt as a starting condition. */
+	IFS0bits.T1IF = 0;
+
+	/* Enable the interrupt. */
+	IEC0bits.T1IE = 1;
+
+	/* Setup the prescale value. */
+	T1CONbits.TCKPS0 = 1;
+	T1CONbits.TCKPS1 = 0;
+
+	/* Start the timer. */
+	T1CONbits.TON = 1;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void __attribute__((__interrupt__, auto_psv)) configTICK_INTERRUPT_HANDLER( void )
+{
+	/* Clear the timer interrupt. */
+	IFS0bits.T1IF = 0;
+
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		portYIELD();
+	}
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S
new file mode 100644
index 0000000..83b5803
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S
@@ -0,0 +1,92 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#if defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ )
+
+        .global _vPortYield
+		.extern _vTaskSwitchContext
+		.extern uxCriticalNesting
+
+_vPortYield:
+
+		PUSH	SR						/* Save the SR used by the task.... */
+		PUSH	W0						/* ....then disable interrupts. */
+		MOV		#32, W0
+		MOV		W0, SR
+		PUSH	W1						/* Save registers to the stack. */
+		PUSH.D	W2
+		PUSH.D	W4
+		PUSH.D	W6
+		PUSH.D 	W8
+		PUSH.D 	W10
+		PUSH.D	W12
+		PUSH	W14
+		PUSH	RCOUNT
+		PUSH	TBLPAG
+
+		PUSH	CORCON
+		#ifdef __HAS_EDS__
+			PUSH	DSRPAG
+			PUSH	DSWPAG
+		#else
+			PUSH	PSVPAG
+		#endif /* __HAS_EDS__ */
+		MOV		_uxCriticalNesting, W0		/* Save the critical nesting counter for the task. */
+		PUSH	W0
+		MOV		_pxCurrentTCB, W0			/* Save the new top of stack into the TCB. */
+		MOV		W15, [W0]
+
+		call 	_vTaskSwitchContext
+
+		MOV		_pxCurrentTCB, W0			/* Restore the stack pointer for the task. */
+		MOV		[W0], W15
+		POP		W0							/* Restore the critical nesting counter for the task. */
+		MOV		W0, _uxCriticalNesting
+		#ifdef __HAS_EDS__
+			POP		DSWPAG
+			POP		DSRPAG
+		#else
+			POP		PSVPAG
+		#endif /* __HAS_EDS__ */
+		POP		CORCON
+		POP		TBLPAG
+		POP		RCOUNT						/* Restore the registers from the stack. */
+		POP		W14
+		POP.D	W12
+		POP.D	W10
+		POP.D	W8
+		POP.D	W6
+		POP.D	W4
+		POP.D	W2
+		POP.D	W0
+		POP		SR
+
+        return
+
+        .end
+		
+#endif /* defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ ) */
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S
new file mode 100644
index 0000000..e1fc2ed
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S
@@ -0,0 +1,106 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ )
+
+        .global _vPortYield
+		.extern _vTaskSwitchContext
+		.extern uxCriticalNesting
+
+_vPortYield:
+
+		PUSH	SR						/* Save the SR used by the task.... */
+		PUSH	W0						/* ....then disable interrupts. */
+		MOV		#32, W0
+		MOV		W0, SR
+		PUSH	W1						/* Save registers to the stack. */
+		PUSH.D	W2
+		PUSH.D	W4
+		PUSH.D	W6
+		PUSH.D 	W8
+		PUSH.D 	W10
+		PUSH.D	W12
+		PUSH	W14
+		PUSH	RCOUNT
+		PUSH	TBLPAG
+		PUSH	ACCAL
+		PUSH	ACCAH
+		PUSH	ACCAU
+		PUSH	ACCBL
+		PUSH	ACCBH
+		PUSH	ACCBU
+		PUSH	DCOUNT
+		PUSH	DOSTARTL
+		PUSH	DOSTARTH
+		PUSH	DOENDL
+		PUSH	DOENDH
+
+
+		PUSH	CORCON
+		PUSH	PSVPAG
+		MOV		_uxCriticalNesting, W0		/* Save the critical nesting counter for the task. */
+		PUSH	W0
+		MOV		_pxCurrentTCB, W0			/* Save the new top of stack into the TCB. */
+		MOV		W15, [W0]
+
+		call 	_vTaskSwitchContext
+
+		MOV		_pxCurrentTCB, W0			/* Restore the stack pointer for the task. */
+		MOV		[W0], W15
+		POP		W0							/* Restore the critical nesting counter for the task. */
+		MOV		W0, _uxCriticalNesting
+		POP		PSVPAG
+		POP		CORCON
+		POP		DOENDH
+		POP		DOENDL
+		POP		DOSTARTH
+		POP		DOSTARTL
+		POP		DCOUNT
+		POP		ACCBU
+		POP		ACCBH
+		POP		ACCBL
+		POP		ACCAU
+		POP		ACCAH
+		POP		ACCAL
+		POP		TBLPAG
+		POP		RCOUNT						/* Restore the registers from the stack. */
+		POP		W14
+		POP.D	W12
+		POP.D	W10
+		POP.D	W8
+		POP.D	W6
+		POP.D	W4
+		POP.D	W2
+		POP.D	W0
+		POP		SR
+
+        return
+
+        .end
+
+#endif /* defined( __dsPIC30F__ ) || defined( __dsPIC33F__ ) */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portmacro.h
new file mode 100644
index 0000000..7605e1b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portmacro.h
@@ -0,0 +1,108 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint16_t
+#define portBASE_TYPE	short
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			2
+#define portSTACK_GROWTH			1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#define portDISABLE_INTERRUPTS()	SET_CPU_IPL( configKERNEL_INTERRUPT_PRIORITY ); __asm volatile ( "NOP" )
+#define portENABLE_INTERRUPTS()		SET_CPU_IPL( 0 )
+
+/* Note that exiting a critical sectino will set the IPL bits to 0, nomatter
+what their value was prior to entering the critical section. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+extern void vPortYield( void );
+#define portYIELD()				asm volatile ( "CALL _vPortYield			\n"		\
+												"NOP					  " );
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Required by the kernel aware debugger. */
+#ifdef __DEBUG
+	#define portREMOVE_STATIC_QUALIFIER
+#endif
+
+#define portNOP()				asm volatile ( "NOP" )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/ISR_Support.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/ISR_Support.h
new file mode 100644
index 0000000..8b69cb6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/ISR_Support.h
@@ -0,0 +1,214 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "FreeRTOSConfig.h"
+
+#define portCONTEXT_SIZE 132
+#define portEPC_STACK_LOCATION 124
+#define portSTATUS_STACK_LOCATION 128
+
+#ifdef __LANGUAGE_ASSEMBLY__
+
+/******************************************************************/
+.macro	portSAVE_CONTEXT
+
+	/* Make room for the context. First save the current status so it can be
+	manipulated, and the cause and EPC registers so their original values are
+	captured. */
+	mfc0	k0, _CP0_CAUSE
+	addiu	sp, sp, -portCONTEXT_SIZE
+	mfc0	k1, _CP0_STATUS
+
+	/* Also save s6 and s5 so they can be used.  Any nesting interrupts should
+	maintain the values of these registers across the ISR. */
+	sw		s6, 44(sp)
+	sw		s5, 40(sp)
+	sw		k1, portSTATUS_STACK_LOCATION(sp)
+
+	/* Prepare to enable interrupts above the current priority.
+	k0 = k0 >> 10. Moves RIPL[17:10] to [7:0] */
+	srl		k0, k0, 0xa
+
+	/* Insert bit field. 7 bits k0[6:0] to k1[16:10] */
+	ins		k1, k0, 10, 7
+
+	/* Sets CP0.Status.IPL = CP0.Cause.RIPL
+	Copy the MSB of the IPL, but it would be an error if it was set anyway. */
+	srl		k0, k0, 0x7
+
+	/* MSB of IPL is bit[18] of CP0.Status */
+	ins		k1, k0, 18, 1
+
+	/* CP0.Status[5:1] = 0 b[5]=Rsvd, b[4]=UM,
+	   b[3]=Rsvd, b[2]=ERL, b[1]=EXL
+	   Setting EXL=0 allows higher priority interrupts
+	   to preempt this handler */
+	ins		k1, zero, 1, 4
+
+
+	/* s5 is used as the frame pointer. */
+	add		s5, zero, sp
+
+	/* Check the nesting count value. */
+	la		k0, uxInterruptNesting
+	lw		s6, (k0)
+
+	/* If the nesting count is 0 then swap to the the system stack, otherwise
+	the system stack is already being used. */
+	bne		s6, zero, 1f
+	nop
+
+	/* Swap to the system stack. */
+	la		sp, xISRStackTop
+	lw		sp, (sp)
+
+	/* Increment and save the nesting count. */
+1:  addiu   s6, s6, 1
+	sw		s6, 0(k0)
+
+	/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
+	mfc0	s6, _CP0_EPC
+
+	/* Re-enable interrupts. */
+	mtc0	k1, _CP0_STATUS
+
+	/* Save the context into the space just created.  s6 is saved again
+	here as it now contains the EPC value.  No other s registers need be
+	saved. */
+	sw		ra, 120(s5) /* Return address (RA=R31) */
+	sw		s8, 116(s5) /* Frame Pointer (FP=R30) */
+	sw		t9, 112(s5)
+	sw		t8, 108(s5)
+	sw		t7, 104(s5)
+	sw		t6, 100(s5)
+	sw		t5, 96(s5)
+	sw		t4, 92(s5)
+	sw		t3, 88(s5)
+	sw		t2, 84(s5)
+	sw		t1, 80(s5)
+	sw		t0, 76(s5)
+	sw		a3, 72(s5)
+	sw		a2, 68(s5)
+	sw		a1, 64(s5)
+	sw		a0, 60(s5)
+	sw		v1, 56(s5)
+	sw		v0, 52(s5)
+	sw		s6, portEPC_STACK_LOCATION(s5)
+	sw		$1, 16(s5)
+
+	/* MEC14xx does not have DSP, removed 7 words */
+	mfhi	s6
+	sw		s6, 12(s5)
+	mflo	s6
+	sw		s6, 8(s5)
+
+	/* Update the task stack pointer value if nesting is zero. */
+	la		s6, uxInterruptNesting
+	lw		s6, (s6)
+	addiu	s6, s6, -1
+	bne		s6, zero, 1f
+	nop
+
+	/* Save the stack pointer. */
+	la		s6, uxSavedTaskStackPointer
+	sw		s5, (s6)
+1:
+	.endm
+
+/******************************************************************/
+.macro	portRESTORE_CONTEXT
+
+	/* Restore the stack pointer from the TCB.  This is only done if the
+	nesting count is 1. */
+	la		s6, uxInterruptNesting
+	lw		s6, (s6)
+	addiu   s6, s6, -1
+	bne		s6, zero, 1f
+	nop
+	la		s6, uxSavedTaskStackPointer
+	lw		s5, (s6)
+
+	/* Restore the context.
+	MCHP MEC14xx does not include DSP */
+1:
+	lw		s6, 8(s5)
+	mtlo	s6
+	lw		s6, 12(s5)
+	mthi	s6
+	lw		$1, 16(s5)
+
+	/* s6 is loaded as it was used as a scratch register and therefore saved
+	as part of the interrupt context. */
+	lw		s6, 44(s5)
+	lw		v0, 52(s5)
+	lw		v1, 56(s5)
+	lw		a0, 60(s5)
+	lw		a1, 64(s5)
+	lw		a2, 68(s5)
+	lw		a3, 72(s5)
+	lw		t0, 76(s5)
+	lw		t1, 80(s5)
+	lw		t2, 84(s5)
+	lw		t3, 88(s5)
+	lw		t4, 92(s5)
+	lw		t5, 96(s5)
+	lw		t6, 100(s5)
+	lw		t7, 104(s5)
+	lw		t8, 108(s5)
+	lw		t9, 112(s5)
+	lw		s8, 116(s5)
+	lw		ra, 120(s5)
+
+	/* Protect access to the k registers, and others. */
+	di
+	ehb
+
+	/* Decrement the nesting count. */
+	la		k0, uxInterruptNesting
+	lw		k1, (k0)
+	addiu	k1, k1, -1
+	sw		k1, 0(k0)
+
+	lw		k0, portSTATUS_STACK_LOCATION(s5)
+	lw		k1, portEPC_STACK_LOCATION(s5)
+
+	/* Leave the stack in its original state.  First load sp from s5, then
+	restore s5 from the stack. */
+	add		sp, zero, s5
+	lw		s5, 40(sp)
+	addiu   sp, sp, portCONTEXT_SIZE
+
+	mtc0	k0, _CP0_STATUS
+	mtc0	k1, _CP0_EPC
+	ehb
+	eret
+	nop
+
+	.endm
+
+#endif /* #ifdef __LANGUAGE_ASSEMBLY__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port.c
new file mode 100644
index 0000000..261fb69
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port.c
@@ -0,0 +1,345 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the PIC32MEC14xx  port.
+ *----------------------------------------------------------*/
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Microchip includes. */
+#include 
+#include 
+
+#if !defined(__MEC__)
+	#error This port is designed to work with XC32 on MEC14xx.  Please update your C compiler version or settings.
+#endif
+
+#if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
+	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
+#endif
+
+/* Bits within various registers. */
+#define portIE_BIT					( 0x00000001 )
+#define portEXL_BIT					( 0x00000002 )
+
+/* The EXL bit is set to ensure interrupts do not occur while the context of
+the first task is being restored.  MEC14xx does not have DSP HW. */
+#define portINITIAL_SR				( portIE_BIT | portEXL_BIT )
+
+/* MEC14xx RTOS Timer MMCR's. */
+#define portMMCR_RTMR_PRELOAD	*((volatile uint32_t *)(0xA0007404ul))
+#define portMMCR_RTMR_CONTROL	*((volatile uint32_t *)(0xA0007408ul))
+
+/* MEC14xx JTVIC external interrupt controller is mapped to M14K closely-coupled
+peripheral space. */
+#define portGIRQ23_RTOS_TIMER_BITPOS	( 4 )
+#define portGIRQ23_RTOS_TIMER_MASK		( 1ul << ( portGIRQ23_RTOS_TIMER_BITPOS ) )
+#define portMMCR_JTVIC_GIRQ23_SRC		*((volatile uint32_t *)(0xBFFFC0F0ul))
+#define portMMCR_JTVIC_GIRQ23_SETEN		*((volatile uint32_t *)(0xBFFFC0F4ul))
+#define portMMCR_JTVIC_GIRQ23_PRIA		*((volatile uint32_t *)(0xBFFFC3F0ul))
+
+/* MIPS Software Interrupts are routed through JTVIC GIRQ24 */
+#define portGIRQ24_M14K_SOFTIRQ0_BITPOS	( 1 )
+#define portGIRQ24_M14K_SOFTIRQ0_MASK	( 1ul << ( portGIRQ24_M14K_SOFTIRQ0_BITPOS ) )
+#define portMMCR_JTVIC_GIRQ24_SRC		*((volatile uint32_t *)(0xBFFFC100ul))
+#define portMMCR_JTVIC_GIRQ24_SETEN		*((volatile uint32_t *)(0xBFFFC104ul))
+#define portMMCR_JTVIC_GIRQ24_PRIA		*((volatile uint32_t *)(0xBFFFC400ul))
+
+/*
+By default port.c generates its tick interrupt from the RTOS timer.  The user
+can override this behaviour by:
+	1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
+	   which is the function that configures the timer.  The function is defined
+	   as a weak symbol in this file so if the same function name is used in the
+	   application code then the version in the application code will be linked
+	   into the application in preference to the version defined in this file.
+	2: Provide a vector implementation in port_asm.S that overrides the default
+	   behaviour for the specified interrupt vector.
+	3: Specify the correct bit to clear the interrupt during the timer interrupt
+	   handler.
+*/
+#ifndef configTICK_INTERRUPT_VECTOR
+	#define configTICK_INTERRUPT_VECTOR girq23_b4
+	#define configCLEAR_TICK_TIMER_INTERRUPT() portMMCR_JTVIC_GIRQ23_SRC = portGIRQ23_RTOS_TIMER_MASK
+#else
+	#ifndef configCLEAR_TICK_TIMER_INTERRUPT
+		#error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
+	#endif
+#endif
+
+/* Let the user override the pre-loading of the initial RA with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the debugger -
+in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
+stack checking.  A problem in the ISR stack will trigger an assert, not call the
+stack overflow hook function (because the stack overflow hook is specific to a
+task stack, not the ISR stack). */
+#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
+
+	/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
+	the task stacks, and so will legitimately appear in many positions within
+	the ISR stack. */
+    #define portISR_STACK_FILL_BYTE	0xee
+
+	static const uint8_t ucExpectedStackBytes[] = {
+							portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+							portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+							portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+							portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+							portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE };	\
+
+	#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else
+	/* Define the function away. */
+	#define portCHECK_ISR_STACK()
+#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
+
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Records the interrupt nesting depth.  This is initialised to one as it is
+decremented to 0 when the first task starts. */
+volatile UBaseType_t uxInterruptNesting = 0x01;
+
+/* Stores the task stack pointer when a switch is made to use the system stack. */
+UBaseType_t uxSavedTaskStackPointer = 0;
+
+/* The stack used by interrupt service routines that cause a context switch. */
+StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
+
+/* The top of stack value ensures there is enough space to store 6 registers on
+the callers stack, as some functions seem to want to do this. */
+const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7 ] );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Ensure byte alignment is maintained when leaving this function. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) 0xDEADBEEF;
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) 0x12345678;	/* Word to which the stack pointer will be left pointing after context restore. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) ulPortGetCP0Cause();
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) portINITIAL_SR;	/* CP0_STATUS */
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) pxCode; 		/* CP0_EPC */
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS;	/* ra */
+	pxTopOfStack -= 15;
+
+	*pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
+	pxTopOfStack -= 15;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static __inline uint32_t prvDisableInterrupt( void )
+{
+uint32_t prev_state;
+
+	__asm volatile( "di %0; ehb" : "=r" ( prev_state ) :: "memory" );
+	return prev_state;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxSavedTaskStackPointer == 0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup a timer for a regular tick.  This function uses the RTOS timer.
+ * The function is declared weak so an application writer can use a different
+ * timer by redefining this implementation.  If a different timer is used then
+ * configTICK_INTERRUPT_VECTOR must also be defined in FreeRTOSConfig.h to
+ * ensure the RTOS provided tick interrupt handler is installed on the correct
+ * vector number.
+ */
+__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
+{
+/* MEC14xx RTOS Timer whose input clock is 32KHz. */
+const uint32_t ulPreload = ( 32768ul / ( configTICK_RATE_HZ ) );
+
+	configASSERT( ulPreload != 0UL );
+
+	/* Configure the RTOS timer. */
+	portMMCR_RTMR_CONTROL = 0ul;
+	portMMCR_RTMR_PRELOAD = ulPreload;
+
+	/* Configure interrupts from the RTOS timer. */
+	portMMCR_JTVIC_GIRQ23_SRC = ( portGIRQ23_RTOS_TIMER_MASK );
+	portMMCR_JTVIC_GIRQ23_PRIA &= ~( 0x0Ful << 16 );
+	portMMCR_JTVIC_GIRQ23_PRIA |= ( ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) ) << 16 );
+	portMMCR_JTVIC_GIRQ23_SETEN = ( portGIRQ23_RTOS_TIMER_MASK );
+
+	/* Enable the RTOS timer. */
+	portMMCR_RTMR_CONTROL = 0x0Fu;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler(void)
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxInterruptNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+extern void *pxCurrentTCB;
+
+	#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
+	{
+		/* Fill the ISR stack to make it easy to asses how much is being used. */
+		memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
+	}
+	#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
+
+	/* Clear the software interrupt flag. */
+	portMMCR_JTVIC_GIRQ24_SRC = (portGIRQ24_M14K_SOFTIRQ0_MASK);
+
+	/* Set software timer priority.  Each GIRQn has one nibble containing its
+	priority */
+	portMMCR_JTVIC_GIRQ24_PRIA &= ~(0xF0ul);
+	portMMCR_JTVIC_GIRQ24_PRIA |= ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) << 4 );
+
+	/* Enable software interrupt. */
+	portMMCR_JTVIC_GIRQ24_SETEN = ( portGIRQ24_M14K_SOFTIRQ0_MASK );
+
+	/* Setup the timer to generate the tick.  Interrupts will have been disabled
+	by the time we get here. */
+	vApplicationSetupTickTimerInterrupt();
+
+	/* Start the highest priority task that has been created so far.  Its stack
+	location is loaded into uxSavedTaskStackPointer. */
+	uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
+	vPortStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing!  Call the task
+	exit error function to prevent compiler warnings about a static function
+	not being called in the case that the application writer overrides this
+	functionality by defining configTASK_RETURN_ADDRESS. */
+	prvTaskExitError();
+
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortIncrementTick( void )
+{
+UBaseType_t uxSavedStatus;
+uint32_t ulCause;
+
+	uxSavedStatus = uxPortSetInterruptMaskFromISR();
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			ulCause = ulPortGetCP0Cause();
+			ulCause |= ( 1ul << 8UL );
+			vPortSetCP0Cause( ulCause );
+		}
+	}
+	vPortClearInterruptMaskFromISR( uxSavedStatus );
+
+	/* Look for the ISR stack getting near or past its limit. */
+	portCHECK_ISR_STACK();
+
+	/* Clear timer interrupt. */
+	configCLEAR_TICK_TIMER_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxPortSetInterruptMaskFromISR( void )
+{
+UBaseType_t uxSavedStatusRegister;
+
+	prvDisableInterrupt();
+	uxSavedStatusRegister = ulPortGetCP0Status() | 0x01;
+
+	/* This clears the IPL bits, then sets them to
+	configMAX_SYSCALL_INTERRUPT_PRIORITY.  This function should not be called
+	from an interrupt that has a priority above
+	configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
+	can only result in the IPL being unchanged or raised, and therefore never
+	lowered. */
+	vPortSetCP0Status( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
+
+	return uxSavedStatusRegister;
+}
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
+{
+	vPortSetCP0Status( uxSavedStatusRegister );
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port_asm.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port_asm.S
new file mode 100644
index 0000000..15c55f4
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port_asm.S
@@ -0,0 +1,348 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+#include "ISR_Support.h"
+
+/* Microchip includes. */
+#include 
+#include 
+
+	.extern pxCurrentTCB
+	.extern vTaskSwitchContext
+	.extern vPortIncrementTick
+	.extern xISRStackTop
+
+	PORT_CPP_JTVIC_BASE = 0xBFFFC000
+	PORT_CCP_JTVIC_GIRQ24_SRC = 0xBFFFC100
+
+	.global vPortStartFirstTask .text
+	.global vPortYieldISR .text
+	.global vPortTickInterruptHandler .text
+
+
+/******************************************************************/
+
+
+/***************************************************************
+*  The following is needed to locate the
+*  vPortTickInterruptHandler function into the correct vector
+*  MEC14xx - This ISR will only be used if HW timers' interrupts
+*  in GIRQ23 are disaggregated.
+*
+***************************************************************/
+
+	.set  noreorder
+	.set  noat
+	.set  micromips
+
+	.section .text, code
+	.ent    vPortTickInterruptHandler
+
+#if configTIMERS_DISAGGREGATED_ISRS == 0
+
+	.globl girq23_isr
+
+girq23_isr:
+vPortTickInterruptHandler:
+
+	portSAVE_CONTEXT
+
+	jal		girq23_handler
+	nop
+
+	portRESTORE_CONTEXT
+
+.end vPortTickInterruptHandler
+
+#else
+
+	.globl girq23_b4
+
+girq23_b4:
+vPortTickInterruptHandler:
+
+	portSAVE_CONTEXT
+
+	jal		vPortIncrementTick
+	nop
+
+	portRESTORE_CONTEXT
+
+.end vPortTickInterruptHandler
+
+#endif /* #if configTIMERS_DISAGGREGATED_ISRS == 0 */
+
+/******************************************************************/
+
+	.set	micromips
+	.set	noreorder
+	.set	noat
+
+	.section .text, code
+	.ent	vPortStartFirstTask
+
+vPortStartFirstTask:
+
+	/* Simply restore the context of the highest priority task that has
+	been created so far. */
+	portRESTORE_CONTEXT
+
+.end vPortStartFirstTask
+
+
+
+/*******************************************************************/
+
+/***************************************************************
+*  The following is needed to locate the vPortYieldISR function into the correct
+* vector.
+***************************************************************/
+
+	.set micromips
+	.set noreorder
+	.set noat
+
+	.section .text, code
+
+	.global vPortYieldISR
+
+
+#if configCPU_DISAGGREGATED_ISRS == 0
+	.global girq24_isr
+	.ent girq24_isr
+girq24_isr:
+	la		k0, PORT_CPP_JTVIC_BASE
+	lw		k0, 0x10C(k0)
+	andi	k1, k0, 0x2
+	bgtz	k1, vPortYieldISR
+	nop
+
+	portSAVE_CONTEXT
+
+	jal		girq24_b_0_2
+
+	portRESTORE_CONTEXT
+
+	.end girq24_isr
+
+#else
+	.global girq24_b1
+girq24_b1:
+#endif
+		.ent  vPortYieldISR
+vPortYieldISR:
+
+	/* Make room for the context. First save the current status so it can be
+	manipulated, and the cause and EPC registers so thier original values
+	are captured. */
+	addiu	sp, sp, -portCONTEXT_SIZE
+	mfc0	k1, _CP0_STATUS
+
+	/* Also save s6 and s5 so they can be used.  Any nesting interrupts should
+	maintain the values of these registers across the ISR. */
+	sw		s6, 44(sp)
+	sw		s5, 40(sp)
+	sw		k1, portSTATUS_STACK_LOCATION(sp)
+
+	/* Prepare to re-enable interrupts above the kernel priority. */
+	ins		k1, zero, 10, 7		 /* Clear IPL bits 0:6. */
+	ins		k1, zero, 18, 1		 /* Clear IPL bit 7  */
+	ori		k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
+	ins		k1, zero, 1, 4		  /* Clear EXL, ERL and UM. */
+
+	/* s5 is used as the frame pointer. */
+	add		s5, zero, sp
+
+	/* Swap to the system stack.  This is not conditional on the nesting
+	count as this interrupt is always the lowest priority and therefore
+	the nesting is always 0. */
+	la		sp, xISRStackTop
+	lw		sp, (sp)
+
+	/* Set the nesting count. */
+	la		k0, uxInterruptNesting
+	addiu   s6, zero, 1
+	sw		s6, 0(k0)
+
+	/* s6 holds the EPC value, this is saved with the rest of the context
+	after interrupts are enabled. */
+	mfc0	s6, _CP0_EPC
+
+	/* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+	mtc0	k1, _CP0_STATUS
+
+	/* Save the context into the space just created.  s6 is saved again
+	here as it now contains the EPC value. */
+	sw		ra, 120(s5)
+	sw		s8, 116(s5)
+	sw		t9, 112(s5)
+	sw		t8, 108(s5)
+	sw		t7, 104(s5)
+	sw		t6, 100(s5)
+	sw		t5, 96(s5)
+	sw		t4, 92(s5)
+	sw		t3, 88(s5)
+	sw		t2, 84(s5)
+	sw		t1, 80(s5)
+	sw		t0, 76(s5)
+	sw		a3, 72(s5)
+	sw		a2, 68(s5)
+	sw		a1, 64(s5)
+	sw		a0, 60(s5)
+	sw		v1, 56(s5)
+	sw		v0, 52(s5)
+	sw		s7, 48(s5)
+	sw		s6, portEPC_STACK_LOCATION(s5)
+	/* s5 and s6 has already been saved. */
+	sw		s4, 36(s5)
+	sw		s3, 32(s5)
+	sw		s2, 28(s5)
+	sw		s1, 24(s5)
+	sw		s0, 20(s5)
+	sw		$1, 16(s5)
+
+	/* s7 is used as a scratch register as this should always be saved acro ss
+	nesting interrupts. */
+	mfhi	s7
+	sw		s7, 12(s5)
+	mflo	s7
+	sw		s7, 8(s5)
+
+	/* Save the stack pointer to the task. */
+	la		s7, pxCurrentTCB
+	lw		s7, (s7)
+	sw		s5, (s7)
+
+	/* Set the interrupt mask to the max priority that can use the API.
+	The yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY
+	which is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only
+	ever raise the IPL value and never lower it. */
+	di
+	ehb
+	mfc0	s7, _CP0_STATUS
+	ins		s7, zero, 10, 7
+	ins		s7, zero, 18, 1
+	ori		s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
+
+	/* This mtc0 re-enables interrupts, but only above
+	configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+	mtc0	s6, _CP0_STATUS
+	ehb
+
+	/* Clear the software interrupt in the core. */
+	mfc0	s6, _CP0_CAUSE
+	ins		s6, zero, 8, 1
+	mtc0	s6, _CP0_CAUSE
+	ehb
+
+	/* Clear the interrupt in the interrupt controller.
+	MEC14xx GIRQ24 Source bit[1] = 1 to clear */
+	la		s6, PORT_CCP_JTVIC_GIRQ24_SRC
+	addiu	s4, zero, 2
+	sw		s4, (s6)
+	jal		vTaskSwitchContext
+	nop
+
+	/* Clear the interrupt mask again. The saved status value is still in s7 */
+	mtc0	s7, _CP0_STATUS
+	ehb
+
+	/* Restore the stack pointer from the TCB. */
+	la		s0, pxCurrentTCB
+	lw		s0, (s0)
+	lw		s5, (s0)
+
+	/* Restore the rest of the context. */
+	lw		s0, 8(s5)
+	mtlo	s0
+	lw		s0, 12(s5)
+	mthi	s0
+
+	lw		$1, 16(s5)
+	lw		s0, 20(s5)
+	lw		s1, 24(s5)
+	lw		s2, 28(s5)
+	lw		s3, 32(s5)
+	lw		s4, 36(s5)
+
+	/* s5 is loaded later. */
+	lw		s6, 44(s5)
+	lw		s7, 48(s5)
+	lw		v0, 52(s5)
+	lw		v1, 56(s5)
+	lw		a0, 60(s5)
+	lw		a1, 64(s5)
+	lw		a2, 68(s5)
+	lw		a3, 72(s5)
+	lw		t0, 76(s5)
+	lw		t1, 80(s5)
+	lw		t2, 84(s5)
+	lw		t3, 88(s5)
+	lw		t4, 92(s5)
+	lw		t5, 96(s5)
+	lw		t6, 100(s5)
+	lw		t7, 104(s5)
+	lw		t8, 108(s5)
+	lw		t9, 112(s5)
+	lw		s8, 116(s5)
+	lw		ra, 120(s5)
+
+	/* Protect access to the k registers, and others. */
+	di
+	ehb
+
+	/* Set nesting back to zero.  As the lowest priority interrupt this
+	interrupt cannot have nested. */
+	la		k0, uxInterruptNesting
+	sw		zero, 0(k0)
+
+	/* Switch back to use the real stack pointer. */
+	add		sp, zero, s5
+
+	/* Restore the real s5 value. */
+	lw		s5, 40(sp)
+
+	/* Pop the status and epc values. */
+	lw		k1, portSTATUS_STACK_LOCATION(sp)
+	lw		k0, portEPC_STACK_LOCATION(sp)
+
+	/* Remove stack frame. */
+	addiu	sp, sp, portCONTEXT_SIZE
+
+	mtc0	k1, _CP0_STATUS
+	mtc0	k0, _CP0_EPC
+	ehb
+	eret
+	nop
+
+.end	vPortYieldISR
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/portmacro.h
new file mode 100644
index 0000000..179165b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/portmacro.h
@@ -0,0 +1,252 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint32_t
+#define portBASE_TYPE   long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT  8
+#define portSTACK_GROWTH    -1
+#define portTICK_PERIOD_MS  ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#define portIPL_SHIFT       ( 10UL )
+/* Don't straddle the CEE bit.  Interrupts calling FreeRTOS functions should
+never have higher IPL bits set anyway. */
+#define portALL_IPL_BITS    ( 0x7FUL << portIPL_SHIFT )
+#define portSW0_BIT         ( 0x01 << 8 )
+
+/* Interrupt priority conversion */
+#define portIPL_TO_CODE( iplNumber )    ( ( iplNumber >> 1 ) & 0x03ul )
+#define portCODE_TO_IPL( iplCode )      ( ( iplCode << 1 ) | 0x01ul )
+
+/*-----------------------------------------------------------*/
+
+static inline uint32_t ulPortGetCP0Status( void )
+{
+uint32_t rv;
+
+	__asm volatile(
+			"\n\t"
+			"mfc0 %0,$12,0      \n\t"
+			: "=r" ( rv ) :: );
+
+	return rv;
+}
+/*-----------------------------------------------------------*/
+
+static inline void vPortSetCP0Status( uint32_t new_status)
+{
+	( void ) new_status;
+
+	__asm__ __volatile__(
+			"\n\t"
+			"mtc0 %0,$12,0      \n\t"
+			"ehb                \n\t"
+			:
+			:"r" ( new_status ) : );
+}
+/*-----------------------------------------------------------*/
+
+static inline uint32_t ulPortGetCP0Cause( void )
+{
+uint32_t rv;
+
+	__asm volatile(
+			"\n\t"
+			"mfc0 %0,$13,0      \n\t"
+			: "=r" ( rv ) :: );
+
+    return rv;
+}
+/*-----------------------------------------------------------*/
+
+static inline void vPortSetCP0Cause( uint32_t new_cause )
+{
+	( void ) new_cause;
+
+	__asm__ __volatile__(
+			"\n\t"
+			"mtc0 %0,$13,0      \n\t"
+			"ehb                \n\t"
+			:
+			:"r" ( new_cause ) : );
+}
+/*-----------------------------------------------------------*/
+
+/* This clears the IPL bits, then sets them to
+configMAX_SYSCALL_INTERRUPT_PRIORITY.  An extra check is performed if
+configASSERT() is defined to ensure an assertion handler does not inadvertently
+attempt to lower the IPL when the call to assert was triggered because the IPL
+value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
+safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
+those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
+ensure API function and interrupt entry is as fast and as simple as possible. */
+#ifdef configASSERT
+    #define portDISABLE_INTERRUPTS() 																			\
+	{ 																											\
+	uint32_t ulStatus; 																							\
+		/* Mask interrupts at and below the kernel interrupt priority. */  										\
+		ulStatus = ulPortGetCP0Status(); 																		\
+		/* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ 									\
+		if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) 		\
+		{ 																										\
+			ulStatus &= ~portALL_IPL_BITS;  																	\
+			vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); 		\
+		} 																										\
+    }
+#else /* configASSERT */
+	#define portDISABLE_INTERRUPTS() 																			\
+	{ 																											\
+	uint32_t ulStatus;  																						\
+		/* Mask interrupts at and below the kernel interrupt priority. */ 										\
+		ulStatus = ulPortGetCP0Status(); 																		\
+		ulStatus &= ~portALL_IPL_BITS; 																			\
+		vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); 			\
+	}
+#endif /* configASSERT */
+
+#define portENABLE_INTERRUPTS() 			\
+{ 											\
+uint32_t ulStatus; 							\
+	/* Unmask all interrupts. */ 			\
+	ulStatus = ulPortGetCP0Status(); 		\
+	ulStatus &= ~portALL_IPL_BITS; 			\
+	vPortSetCP0Status( ulStatus ); 			\
+}
+
+
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portCRITICAL_NESTING_IN_TCB	1
+#define portENTER_CRITICAL()		vTaskEnterCritical()
+#define portEXIT_CRITICAL()			vTaskExitCritical()
+
+extern UBaseType_t uxPortSetInterruptMaskFromISR();
+extern void vPortClearInterruptMaskFromISR( UBaseType_t );
+#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
+
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - _clz( ( uxReadyPriorities ) ) )
+
+#endif /* taskRECORD_READY_PRIORITY */
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+#define portYIELD() 						\
+{ 											\
+uint32_t ulCause; 							\
+	/* Trigger software interrupt. */ 		\
+	ulCause = ulPortGetCP0Cause(); 			\
+	ulCause |= portSW0_BIT; 				\
+	vPortSetCP0Cause( ulCause ); 			\
+}
+
+extern volatile UBaseType_t uxInterruptNesting;
+#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
+
+#define portNOP() __asm volatile ( "nop" )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#define portEND_SWITCHING_ISR( xSwitchRequired ) 	if( xSwitchRequired )	\
+													{ 						\
+														portYIELD();		\
+													}
+
+/* Required by the kernel aware debugger. */
+#ifdef __DEBUG
+    #define portREMOVE_STATIC_QUALIFIER
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MX/ISR_Support.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MX/ISR_Support.h
new file mode 100644
index 0000000..043a6fc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MX/ISR_Support.h
@@ -0,0 +1,191 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "FreeRTOSConfig.h"
+
+#define portCONTEXT_SIZE 132
+#define portEPC_STACK_LOCATION	124
+#define portSTATUS_STACK_LOCATION 128
+
+/******************************************************************/
+.macro	portSAVE_CONTEXT
+
+	/* Make room for the context. First save the current status so it can be
+	manipulated, and the cause and EPC registers so their original values are
+	captured. */
+	mfc0		k0, _CP0_CAUSE
+	addiu		sp,	sp, -portCONTEXT_SIZE
+	mfc0		k1, _CP0_STATUS
+
+	/* Also save s6 and s5 so they can be used.  Any nesting interrupts should
+	maintain the values of these registers across the ISR. */
+	sw			s6, 44(sp)
+	sw			s5, 40(sp)
+	sw			k1, portSTATUS_STACK_LOCATION(sp)
+
+	/* Prepare to enable interrupts above the current priority. */
+	srl			k0, k0, 0xa
+	ins 		k1, k0, 10, 6
+	ins			k1, zero, 1, 4
+
+	/* s5 is used as the frame pointer. */
+	add			s5, zero, sp
+
+	/* Check the nesting count value. */
+	la			k0, uxInterruptNesting
+	lw			s6, (k0)
+
+	/* If the nesting count is 0 then swap to the the system stack, otherwise
+	the system stack is already being used. */
+	bne			s6, zero, 1f
+	nop
+
+	/* Swap to the system stack. */
+	la			sp, xISRStackTop
+	lw			sp, (sp)
+
+	/* Increment and save the nesting count. */
+1:	addiu		s6, s6, 1
+	sw			s6, 0(k0)
+
+	/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
+	mfc0 		s6, _CP0_EPC
+
+	/* Re-enable interrupts. */
+	mtc0		k1, _CP0_STATUS
+
+	/* Save the context into the space just created.  s6 is saved again
+	here as it now contains the EPC value.  No other s registers need be
+	saved. */
+	sw			ra, 120(s5)
+	sw			s8, 116(s5)
+	sw			t9, 112(s5)
+	sw			t8, 108(s5)
+	sw			t7, 104(s5)
+	sw			t6, 100(s5)
+	sw			t5, 96(s5)
+	sw			t4, 92(s5)
+	sw			t3, 88(s5)
+	sw			t2, 84(s5)
+	sw			t1, 80(s5)
+	sw			t0, 76(s5)
+	sw			a3, 72(s5)
+	sw			a2, 68(s5)
+	sw			a1, 64(s5)
+	sw			a0, 60(s5)
+	sw			v1, 56(s5)
+	sw			v0, 52(s5)
+	sw			s6, portEPC_STACK_LOCATION(s5)
+	sw			$1, 16(s5)
+
+	/* s6 is used as a scratch register. */
+	mfhi		s6
+	sw			s6, 12(s5)
+	mflo		s6
+	sw			s6, 8(s5)
+
+	/* Update the task stack pointer value if nesting is zero. */
+	la			s6, uxInterruptNesting
+	lw			s6, (s6)
+	addiu		s6, s6, -1
+	bne			s6, zero, 1f
+	nop
+
+	/* Save the stack pointer. */
+	la			s6, uxSavedTaskStackPointer
+	sw			s5, (s6)
+1:
+	.endm
+
+/******************************************************************/
+.macro	portRESTORE_CONTEXT
+
+	/* Restore the stack pointer from the TCB.  This is only done if the
+	nesting count is 1. */
+	la			s6, uxInterruptNesting
+	lw			s6, (s6)
+	addiu		s6, s6, -1
+	bne			s6, zero, 1f
+	nop
+	la			s6, uxSavedTaskStackPointer
+	lw			s5, (s6)
+
+	/* Restore the context. */
+1:	lw			s6, 8(s5)
+	mtlo		s6
+	lw			s6, 12(s5)
+	mthi		s6
+	lw			$1, 16(s5)
+	/* s6 is loaded as it was used as a scratch register and therefore saved
+	as part of the interrupt context. */
+	lw			s6, 44(s5)
+	lw			v0, 52(s5)
+	lw			v1, 56(s5)
+	lw			a0, 60(s5)
+	lw			a1, 64(s5)
+	lw			a2, 68(s5)
+	lw			a3, 72(s5)
+	lw			t0, 76(s5)
+	lw			t1, 80(s5)
+	lw			t2, 84(s5)
+	lw			t3, 88(s5)
+	lw			t4, 92(s5)
+	lw			t5, 96(s5)
+	lw			t6, 100(s5)
+	lw			t7, 104(s5)
+	lw			t8, 108(s5)
+	lw			t9, 112(s5)
+	lw			s8, 116(s5)
+	lw			ra, 120(s5)
+
+	/* Protect access to the k registers, and others. */
+	di
+	ehb
+
+	/* Decrement the nesting count. */
+	la			k0, uxInterruptNesting
+	lw			k1, (k0)
+	addiu		k1, k1, -1
+	sw			k1, 0(k0)
+
+	lw			k0, portSTATUS_STACK_LOCATION(s5)
+	lw			k1, portEPC_STACK_LOCATION(s5)
+
+	/* Leave the stack in its original state.  First load sp from s5, then
+	restore s5 from the stack. */
+	add			sp, zero, s5
+	lw			s5, 40(sp)
+	addiu		sp, sp,	portCONTEXT_SIZE
+
+	mtc0		k0, _CP0_STATUS
+	mtc0 		k1, _CP0_EPC
+	ehb
+	eret
+	nop
+
+	.endm
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MX/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MX/port.c
new file mode 100644
index 0000000..75e1a12
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MX/port.c
@@ -0,0 +1,332 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the PIC32MX port.
+  *----------------------------------------------------------*/
+
+#ifndef __XC
+    #error This port is designed to work with XC32.  Please update your C compiler version.
+#endif
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Hardware specifics. */
+#define portTIMER_PRESCALE	8
+#define portPRESCALE_BITS	1
+
+/* Bits within various registers. */
+#define portIE_BIT						( 0x00000001 )
+#define portEXL_BIT						( 0x00000002 )
+
+/* Bits within the CAUSE register. */
+#define portCORE_SW_0					( 0x00000100 )
+#define portCORE_SW_1					( 0x00000200 )
+
+/* The EXL bit is set to ensure interrupts do not occur while the context of
+the first task is being restored. */
+#define portINITIAL_SR					( portIE_BIT | portEXL_BIT )
+
+/*
+By default port.c generates its tick interrupt from TIMER1.  The user can
+override this behaviour by:
+	1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
+	   which is the function that configures the timer.  The function is defined
+	   as a weak symbol in this file so if the same function name is used in the
+	   application code then the version in the application code will be linked
+	   into the application in preference to the version defined in this file.
+	2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
+	   to generate the tick interrupt.  For example, when timer 1 is used then
+	   configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
+	   configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
+	3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
+	   timer used to generate the tick interrupt.  For example, when timer 1 is
+	   used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
+	   IFS0CLR = _IFS0_T1IF_MASK.
+*/
+#ifndef configTICK_INTERRUPT_VECTOR
+	#define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR
+	#define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK
+#else
+	#ifndef configCLEAR_TICK_TIMER_INTERRUPT
+		#error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
+	#endif
+#endif
+
+/* Let the user override the pre-loading of the initial RA with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
+stack checking.  A problem in the ISR stack will trigger an assert, not call the
+stack overflow hook function (because the stack overflow hook is specific to a
+task stack, not the ISR stack). */
+#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
+
+	/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
+	the task stacks, and so will legitimately appear in many positions within
+	the ISR stack. */
+	#define portISR_STACK_FILL_BYTE	0xee
+
+	static const uint8_t ucExpectedStackBytes[] = {
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE };	\
+
+	#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else
+	/* Define the function away. */
+	#define portCHECK_ISR_STACK()
+#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
+
+/*-----------------------------------------------------------*/
+
+
+/*
+ * Place the prototype here to ensure the interrupt vector is correctly installed.
+ * Note that because the interrupt is written in assembly, the IPL setting in the
+ * following line of code has no effect.  The interrupt priority is set by the
+ * call to ConfigIntTimer1() in vApplicationSetupTickTimerInterrupt().
+ */
+extern void __attribute__( (interrupt(IPL1AUTO), vector( configTICK_INTERRUPT_VECTOR ))) vPortTickInterruptHandler( void );
+
+/*
+ * The software interrupt handler that performs the yield.  Note that, because
+ * the interrupt is written in assembly, the IPL setting in the following line of
+ * code has no effect.  The interrupt priority is set by the call to
+ * mConfigIntCoreSW0() in xPortStartScheduler().
+ */
+void __attribute__( (interrupt(IPL1AUTO), vector(_CORE_SOFTWARE_0_VECTOR))) vPortYieldISR( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Records the interrupt nesting depth.  This is initialised to one as it is
+decremented to 0 when the first task starts. */
+volatile UBaseType_t uxInterruptNesting = 0x01;
+
+/* Stores the task stack pointer when a switch is made to use the system stack. */
+UBaseType_t uxSavedTaskStackPointer = 0;
+
+/* The stack used by interrupt service routines that cause a context switch. */
+__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
+
+/* The top of stack value ensures there is enough space to store 6 registers on
+the callers stack, as some functions seem to want to do this. */
+const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Ensure byte alignment is maintained when leaving this function. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) 0xDEADBEEF;
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) 0x12345678;	/* Word to which the stack pointer will be left pointing after context restore. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) _CP0_GET_CAUSE();
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) portINITIAL_SR;/* CP0_STATUS */
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) pxCode; 		/* CP0_EPC */
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS;	/* ra */
+	pxTopOfStack -= 15;
+
+	*pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
+	pxTopOfStack -= 15;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxSavedTaskStackPointer == 0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup a timer for a regular tick.  This function uses peripheral timer 1.
+ * The function is declared weak so an application writer can use a different
+ * timer by redefining this implementation.  If a different timer is used then
+ * configTICK_INTERRUPT_VECTOR must also be defined in FreeRTOSConfig.h to
+ * ensure the RTOS provided tick interrupt handler is installed on the correct
+ * vector number.  When Timer 1 is used the vector number is defined as
+ * _TIMER_1_VECTOR.
+ */
+__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
+{
+const uint32_t ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE) / configTICK_RATE_HZ ) - 1;
+
+	T1CON = 0x0000;
+	T1CONbits.TCKPS = portPRESCALE_BITS;
+	PR1 = ulCompareMatch;
+	IPC1bits.T1IP = configKERNEL_INTERRUPT_PRIORITY;
+
+	/* Clear the interrupt as a starting condition. */
+	IFS0bits.T1IF = 0;
+
+	/* Enable the interrupt. */
+	IEC0bits.T1IE = 1;
+
+	/* Start the timer. */
+	T1CONbits.TON = 1;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler(void)
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxInterruptNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+extern void *pxCurrentTCB;
+
+	#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
+	{
+		/* Fill the ISR stack to make it easy to asses how much is being used. */
+		memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
+	}
+	#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
+
+	/* Clear the software interrupt flag. */
+	IFS0CLR = _IFS0_CS0IF_MASK;
+
+	/* Set software timer priority. */
+	IPC0CLR = _IPC0_CS0IP_MASK;
+	IPC0SET = ( configKERNEL_INTERRUPT_PRIORITY << _IPC0_CS0IP_POSITION );
+
+	/* Enable software interrupt. */
+	IEC0CLR = _IEC0_CS0IE_MASK;
+	IEC0SET = 1 << _IEC0_CS0IE_POSITION;
+
+	/* Setup the timer to generate the tick.  Interrupts will have been
+	disabled by the time we get here. */
+	vApplicationSetupTickTimerInterrupt();
+
+	/* Kick off the highest priority task that has been created so far.
+	Its stack location is loaded into uxSavedTaskStackPointer. */
+	uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
+	vPortStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing!  Call the task
+	exit error function to prevent compiler warnings about a static function
+	not being called in the case that the application writer overrides this
+	functionality by defining configTASK_RETURN_ADDRESS. */
+	prvTaskExitError();
+
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortIncrementTick( void )
+{
+UBaseType_t uxSavedStatus;
+
+	uxSavedStatus = uxPortSetInterruptMaskFromISR();
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			_CP0_BIS_CAUSE( portCORE_SW_0 );
+		}
+	}
+	vPortClearInterruptMaskFromISR( uxSavedStatus );
+
+	/* Look for the ISR stack getting near or past its limit. */
+	portCHECK_ISR_STACK();
+
+	/* Clear timer interrupt. */
+	configCLEAR_TICK_TIMER_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxPortSetInterruptMaskFromISR( void )
+{
+UBaseType_t uxSavedStatusRegister;
+
+	__builtin_disable_interrupts();
+	uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
+	/* This clears the IPL bits, then sets them to
+	configMAX_SYSCALL_INTERRUPT_PRIORITY.  This function should not be called
+	from an interrupt that has a priority above
+	configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
+	can only result in the IPL being unchanged or raised, and therefore never
+	lowered. */
+	_CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
+
+	return uxSavedStatusRegister;
+}
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
+{
+	_CP0_SET_STATUS( uxSavedStatusRegister );
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MX/port_asm.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MX/port_asm.S
new file mode 100644
index 0000000..f47b1b2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MX/port_asm.S
@@ -0,0 +1,268 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include 
+#include 
+#include "ISR_Support.h"
+
+
+	.set	nomips16
+ 	.set 	noreorder
+
+ 	.extern pxCurrentTCB
+ 	.extern vTaskSwitchContext
+ 	.extern vPortIncrementTick
+	.extern xISRStackTop
+
+ 	.global vPortStartFirstTask
+	.global vPortYieldISR
+	.global vPortTickInterruptHandler
+
+
+/******************************************************************/
+
+ 	.set		noreorder
+	.set 		noat
+ 	.ent		vPortTickInterruptHandler
+
+vPortTickInterruptHandler:
+
+	portSAVE_CONTEXT
+
+	jal 		vPortIncrementTick
+	nop
+
+	portRESTORE_CONTEXT
+
+	.end vPortTickInterruptHandler
+
+/******************************************************************/
+
+ 	.set		noreorder
+	.set 		noat
+ 	.ent		vPortStartFirstTask
+
+vPortStartFirstTask:
+
+	/* Simply restore the context of the highest priority task that has been
+	created so far. */
+	portRESTORE_CONTEXT
+
+	.end vPortStartFirstTask
+
+
+
+/*******************************************************************/
+
+	.set		noreorder
+	.set 		noat
+	.ent		vPortYieldISR
+
+vPortYieldISR:
+
+	/* Make room for the context. First save the current status so it can be
+	manipulated. */
+	addiu		sp, sp, -portCONTEXT_SIZE
+	mfc0		k1, _CP0_STATUS
+
+	/* Also save s6 and s5 so they can be used.  Any nesting interrupts should
+	maintain the values of these registers across the ISR. */
+	sw			s6, 44(sp)
+	sw			s5, 40(sp)
+	sw			k1, portSTATUS_STACK_LOCATION(sp)
+
+	/* Prepare to re-enabled interrupt above the kernel priority. */
+	ins 		k1, zero, 10, 6
+	ori			k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
+	ins			k1, zero, 1, 4
+
+	/* s5 is used as the frame pointer. */
+	add			s5, zero, sp
+
+	/* Swap to the system stack.  This is not conditional on the nesting
+	count as this interrupt is always the lowest priority and therefore
+	the nesting is always 0. */
+	la			sp, xISRStackTop
+	lw			sp, (sp)
+
+	/* Set the nesting count. */
+	la			k0, uxInterruptNesting
+	addiu		s6, zero, 1
+	sw			s6, 0(k0)
+
+	/* s6 holds the EPC value, this is saved with the rest of the context
+	after interrupts are enabled. */
+	mfc0 		s6, _CP0_EPC
+
+	/* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+	mtc0		k1, _CP0_STATUS
+
+	/* Save the context into the space just created.  s6 is saved again
+	here as it now contains the EPC value. */
+	sw			ra, 120(s5)
+	sw			s8, 116(s5)
+	sw			t9, 112(s5)
+	sw			t8, 108(s5)
+	sw			t7, 104(s5)
+	sw			t6, 100(s5)
+	sw			t5, 96(s5)
+	sw			t4, 92(s5)
+	sw			t3, 88(s5)
+	sw			t2, 84(s5)
+	sw			t1, 80(s5)
+	sw			t0, 76(s5)
+	sw			a3, 72(s5)
+	sw			a2, 68(s5)
+	sw			a1, 64(s5)
+	sw			a0, 60(s5)
+	sw			v1, 56(s5)
+	sw			v0, 52(s5)
+	sw			s7, 48(s5)
+	sw			s6, portEPC_STACK_LOCATION(s5)
+	/* s5 and s6 has already been saved. */
+	sw			s4, 36(s5)
+	sw			s3, 32(s5)
+	sw			s2, 28(s5)
+	sw			s1, 24(s5)
+	sw			s0, 20(s5)
+	sw			$1, 16(s5)
+
+	/* s7 is used as a scratch register as this should always be saved across
+	nesting interrupts. */
+	mfhi		s7
+	sw			s7, 12(s5)
+	mflo		s7
+	sw			s7, 8(s5)
+
+	/* Save the stack pointer to the task. */
+	la			s7, pxCurrentTCB
+	lw			s7, (s7)
+	sw			s5, (s7)
+
+	/* Set the interrupt mask to the max priority that can use the API.  The
+	yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which
+	is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever
+	raise the IPL value and never lower it. */
+	di
+	ehb
+	mfc0		s7, _CP0_STATUS
+	ins 		s7, zero, 10, 6
+	ori			s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
+
+	/* This mtc0 re-enables interrupts, but only above
+	configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+	mtc0		s6, _CP0_STATUS
+	ehb
+
+	/* Clear the software interrupt in the core. */
+	mfc0		s6, _CP0_CAUSE
+	ins			s6, zero, 8, 1
+	mtc0		s6, _CP0_CAUSE
+	ehb
+
+	/* Clear the interrupt in the interrupt controller. */
+	la			s6, IFS0CLR
+	addiu		s4, zero, 2
+	sw			s4, (s6)
+
+	jal			vTaskSwitchContext
+	nop
+
+	/* Clear the interrupt mask again.  The saved status value is still in s7. */
+	mtc0		s7, _CP0_STATUS
+	ehb
+
+	/* Restore the stack pointer from the TCB. */
+	la			s0, pxCurrentTCB
+	lw			s0, (s0)
+	lw			s5, (s0)
+
+	/* Restore the rest of the context. */
+	lw			s0, 8(s5)
+	mtlo		s0
+	lw			s0, 12(s5)
+	mthi		s0
+	lw			$1, 16(s5)
+	lw			s0, 20(s5)
+	lw			s1, 24(s5)
+	lw			s2, 28(s5)
+	lw			s3, 32(s5)
+	lw			s4, 36(s5)
+	/* s5 is loaded later. */
+	lw			s6, 44(s5)
+	lw			s7, 48(s5)
+	lw			v0, 52(s5)
+	lw			v1, 56(s5)
+	lw			a0, 60(s5)
+	lw			a1, 64(s5)
+	lw			a2, 68(s5)
+	lw			a3, 72(s5)
+	lw			t0, 76(s5)
+	lw			t1, 80(s5)
+	lw			t2, 84(s5)
+	lw			t3, 88(s5)
+	lw			t4, 92(s5)
+	lw			t5, 96(s5)
+	lw			t6, 100(s5)
+	lw			t7, 104(s5)
+	lw			t8, 108(s5)
+	lw			t9, 112(s5)
+	lw			s8, 116(s5)
+	lw			ra, 120(s5)
+
+	/* Protect access to the k registers, and others. */
+	di
+	ehb
+
+	/* Set nesting back to zero.  As the lowest priority interrupt this
+	interrupt cannot have nested. */
+	la			k0, uxInterruptNesting
+	sw			zero, 0(k0)
+
+	/* Switch back to use the real stack pointer. */
+	add			sp, zero, s5
+
+	/* Restore the real s5 value. */
+	lw			s5, 40(sp)
+
+	/* Pop the status and epc values. */
+	lw			k1, portSTATUS_STACK_LOCATION(sp)
+	lw			k0, portEPC_STACK_LOCATION(sp)
+
+	/* Remove stack frame. */
+	addiu		sp, sp, portCONTEXT_SIZE
+
+	mtc0		k1, _CP0_STATUS
+	mtc0 		k0, _CP0_EPC
+	ehb
+	eret
+	nop
+
+	.end		vPortYieldISR
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MX/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MX/portmacro.h
new file mode 100644
index 0000000..b53fd64
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MX/portmacro.h
@@ -0,0 +1,204 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* System include files */
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			8
+#define portSTACK_GROWTH			-1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#define portIPL_SHIFT				( 10UL )
+#define portALL_IPL_BITS			( 0x3fUL << portIPL_SHIFT )
+#define portSW0_BIT					( 0x01 << 8 )
+
+/* This clears the IPL bits, then sets them to
+configMAX_SYSCALL_INTERRUPT_PRIORITY.  An extra check is performed if
+configASSERT() is defined to ensure an assertion handler does not inadvertently
+attempt to lower the IPL when the call to assert was triggered because the IPL
+value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
+safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
+those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
+ensure API function and interrupt entry is as fast and as simple as possible. */
+#ifdef configASSERT
+	#define portDISABLE_INTERRUPTS()											\
+	{																			\
+	uint32_t ulStatus;														\
+																				\
+		/* Mask interrupts at and below the kernel interrupt priority. */		\
+		ulStatus = _CP0_GET_STATUS();											\
+																				\
+		/* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */	\
+		if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
+		{																		\
+			ulStatus &= ~portALL_IPL_BITS;										\
+			_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
+		}																		\
+	}
+#else /* configASSERT */
+	#define portDISABLE_INTERRUPTS()										\
+	{																		\
+	uint32_t ulStatus;													\
+																			\
+		/* Mask interrupts at and below the kernel interrupt priority. */	\
+		ulStatus = _CP0_GET_STATUS();										\
+		ulStatus &= ~portALL_IPL_BITS;										\
+		_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
+	}
+#endif /* configASSERT */
+
+#define portENABLE_INTERRUPTS()											\
+{																		\
+uint32_t ulStatus;													\
+																		\
+	/* Unmask all interrupts. */										\
+	ulStatus = _CP0_GET_STATUS();										\
+	ulStatus &= ~portALL_IPL_BITS;										\
+	_CP0_SET_STATUS( ulStatus );										\
+}
+
+
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portCRITICAL_NESTING_IN_TCB	1
+#define portENTER_CRITICAL()		vTaskEnterCritical()
+#define portEXIT_CRITICAL()			vTaskExitCritical()
+
+extern UBaseType_t uxPortSetInterruptMaskFromISR();
+extern void vPortClearInterruptMaskFromISR( UBaseType_t );
+#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
+
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
+
+#endif /* taskRECORD_READY_PRIORITY */
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+#define portYIELD()								\
+{												\
+uint32_t ulCause;							\
+												\
+	/* Trigger software interrupt. */			\
+	ulCause = _CP0_GET_CAUSE();					\
+	ulCause |= portSW0_BIT;						\
+	_CP0_SET_CAUSE( ulCause );					\
+}
+
+extern volatile UBaseType_t uxInterruptNesting;
+#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
+
+#define portNOP()	__asm volatile ( "nop" )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#define portEND_SWITCHING_ISR( xSwitchRequired )	if( xSwitchRequired )	\
+													{						\
+														portYIELD();		\
+													}
+
+/* Required by the kernel aware debugger. */
+#ifdef __DEBUG
+	#define portREMOVE_STATIC_QUALIFIER
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MZ/ISR_Support.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MZ/ISR_Support.h
new file mode 100644
index 0000000..9a570bb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MZ/ISR_Support.h
@@ -0,0 +1,432 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "FreeRTOSConfig.h"
+
+#define portCONTEXT_SIZE                160
+#define portEPC_STACK_LOCATION          152
+#define portSTATUS_STACK_LOCATION       156
+#define portFPCSR_STACK_LOCATION        0
+#define portTASK_HAS_FPU_STACK_LOCATION     0
+#define portFPU_CONTEXT_SIZE            264
+
+/******************************************************************/
+.macro  portSAVE_FPU_REGS    offset, base
+    /* Macro to assist with saving just the FPU registers to the
+     * specified address and base offset,
+     * offset is a constant, base is the base pointer register  */
+
+	sdc1		$f31, \offset + 248(\base)
+	sdc1		$f30, \offset + 240(\base)
+	sdc1		$f29, \offset + 232(\base)
+	sdc1		$f28, \offset + 224(\base)
+	sdc1		$f27, \offset + 216(\base)
+	sdc1		$f26, \offset + 208(\base)
+	sdc1		$f25, \offset + 200(\base)
+	sdc1		$f24, \offset + 192(\base)
+	sdc1		$f23, \offset + 184(\base)
+	sdc1		$f22, \offset + 176(\base)
+	sdc1		$f21, \offset + 168(\base)
+	sdc1		$f20, \offset + 160(\base)
+	sdc1		$f19, \offset + 152(\base)
+	sdc1		$f18, \offset + 144(\base)
+	sdc1		$f17, \offset + 136(\base)
+	sdc1		$f16, \offset + 128(\base)
+	sdc1		$f15, \offset + 120(\base)
+	sdc1		$f14, \offset + 112(\base)
+	sdc1		$f13, \offset + 104(\base)
+	sdc1		$f12, \offset + 96(\base)
+	sdc1		$f11, \offset + 88(\base)
+	sdc1		$f10, \offset + 80(\base)
+	sdc1		$f9, \offset + 72(\base)
+	sdc1		$f8, \offset + 64(\base)
+	sdc1		$f7, \offset + 56(\base)
+	sdc1		$f6, \offset + 48(\base)
+	sdc1		$f5, \offset + 40(\base)
+	sdc1		$f4, \offset + 32(\base)
+	sdc1		$f3, \offset + 24(\base)
+	sdc1		$f2, \offset + 16(\base)
+	sdc1		$f1, \offset + 8(\base)
+	sdc1		$f0, \offset + 0(\base)
+
+    .endm
+
+/******************************************************************/
+.macro  portLOAD_FPU_REGS    offset, base
+    /* Macro to assist with loading just the FPU registers from the
+     * specified address and base offset, offset is a constant,
+     * base is the base pointer register  */
+
+	ldc1		$f0, \offset + 0(\base)
+	ldc1		$f1, \offset + 8(\base)
+	ldc1		$f2, \offset + 16(\base)
+	ldc1		$f3, \offset + 24(\base)
+	ldc1		$f4, \offset + 32(\base)
+	ldc1		$f5, \offset + 40(\base)
+	ldc1		$f6, \offset + 48(\base)
+	ldc1		$f7, \offset + 56(\base)
+	ldc1		$f8, \offset + 64(\base)
+	ldc1		$f9, \offset + 72(\base)
+	ldc1		$f10, \offset + 80(\base)
+	ldc1		$f11, \offset + 88(\base)
+	ldc1		$f12, \offset + 96(\base)
+	ldc1		$f13, \offset + 104(\base)
+	ldc1		$f14, \offset + 112(\base)
+	ldc1		$f15, \offset + 120(\base)
+	ldc1		$f16, \offset + 128(\base)
+	ldc1		$f17, \offset + 136(\base)
+	ldc1		$f18, \offset + 144(\base)
+	ldc1		$f19, \offset + 152(\base)
+	ldc1		$f20, \offset + 160(\base)
+	ldc1		$f21, \offset + 168(\base)
+	ldc1		$f22, \offset + 176(\base)
+	ldc1		$f23, \offset + 184(\base)
+	ldc1		$f24, \offset + 192(\base)
+	ldc1		$f25, \offset + 200(\base)
+	ldc1		$f26, \offset + 208(\base)
+	ldc1		$f27, \offset + 216(\base)
+	ldc1		$f28, \offset + 224(\base)
+	ldc1		$f29, \offset + 232(\base)
+	ldc1		$f30, \offset + 240(\base)
+	ldc1		$f31, \offset + 248(\base)
+
+    .endm
+
+/******************************************************************/
+.macro	portSAVE_CONTEXT
+
+	/* Make room for the context. First save the current status so it can be
+	manipulated, and the cause and EPC registers so their original values are
+	captured. */
+	mfc0		k0, _CP0_CAUSE
+	addiu		sp, sp, -portCONTEXT_SIZE
+
+	#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+		/* Test if we are already using the system stack. Only tasks may use the
+		FPU so if we are already in a nested interrupt then the FPU context does
+		not require saving. */
+		la			k1, uxInterruptNesting
+		lw			k1, 0(k1)
+		bne			k1, zero, 2f
+		nop
+
+		/* Test if the current task needs the FPU context saving. */
+		la			k1, ulTaskHasFPUContext
+		lw			k1, 0(k1)
+		beq			k1, zero, 1f
+		nop
+
+		/* Adjust the stack to account for the additional FPU context.*/
+		addiu		sp, sp, -portFPU_CONTEXT_SIZE
+
+	1:
+		/* Save the ulTaskHasFPUContext flag. */
+		sw			k1, portTASK_HAS_FPU_STACK_LOCATION(sp)
+
+	2:
+	#endif
+
+	mfc0		k1, _CP0_STATUS
+
+	/* Also save s7, s6 and s5 so they can be used.  Any nesting interrupts
+	should maintain the values of these registers across the ISR. */
+	sw			s7, 48(sp)
+	sw			s6, 44(sp)
+	sw			s5, 40(sp)
+	sw			k1, portSTATUS_STACK_LOCATION(sp)
+
+	/* Prepare to enable interrupts above the current priority. */
+	srl			k0, k0, 0xa
+	ins 		k1, k0, 10, 7
+	srl			k0, k0, 0x7 /* This copies the MSB of the IPL, but it would be an error if it was set anyway. */
+	ins 		k1, k0, 18, 1
+	ins			k1, zero, 1, 4
+
+	/* s5 is used as the frame pointer. */
+	add			s5, zero, sp
+
+	/* Check the nesting count value. */
+	la			k0, uxInterruptNesting
+	lw			s6, (k0)
+
+	/* If the nesting count is 0 then swap to the the system stack, otherwise
+	the system stack is already being used. */
+	bne			s6, zero, 1f
+	nop
+
+	/* Swap to the system stack. */
+	la			sp, xISRStackTop
+	lw			sp, (sp)
+
+	/* Increment and save the nesting count. */
+1:	addiu		s6, s6, 1
+	sw			s6, 0(k0)
+
+	/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
+	mfc0 		s6, _CP0_EPC
+
+	/* Re-enable interrupts. */
+	mtc0		k1, _CP0_STATUS
+
+	/* Save the context into the space just created.  s6 is saved again
+	here as it now contains the EPC value.  No other s registers need be
+	saved. */
+	sw			ra, 120(s5)
+	sw			s8, 116(s5)
+	sw			t9, 112(s5)
+	sw			t8, 108(s5)
+	sw			t7, 104(s5)
+	sw			t6, 100(s5)
+	sw			t5, 96(s5)
+	sw			t4, 92(s5)
+	sw			t3, 88(s5)
+	sw			t2, 84(s5)
+	sw			t1, 80(s5)
+	sw			t0, 76(s5)
+	sw			a3, 72(s5)
+	sw			a2, 68(s5)
+	sw			a1, 64(s5)
+	sw			a0, 60(s5)
+	sw			v1, 56(s5)
+	sw			v0, 52(s5)
+	sw			s6, portEPC_STACK_LOCATION(s5)
+	sw			$1, 16(s5)
+
+	/* Save the AC0, AC1, AC2, AC3 registers from the DSP.  s6 is used as a
+	scratch register. */
+	mfhi		s6, $ac1
+	sw			s6, 128(s5)
+	mflo		s6, $ac1
+	sw			s6, 124(s5)
+
+	mfhi		s6, $ac2
+	sw			s6, 136(s5)
+	mflo		s6, $ac2
+	sw			s6, 132(s5)
+
+	mfhi		s6, $ac3
+	sw			s6, 144(s5)
+	mflo		s6, $ac3
+	sw			s6, 140(s5)
+
+	/* Save the DSP Control register */
+	rddsp		s6
+	sw			s6, 148(s5)
+
+	/* ac0 is done separately to match the MX port. */
+	mfhi		s6, $ac0
+	sw			s6, 12(s5)
+	mflo		s6, $ac0
+	sw			s6, 8(s5)
+
+	/* Save the FPU context if the nesting count was zero. */
+	#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+		la			s6, uxInterruptNesting
+		lw			s6, 0(s6)
+		addiu		s6, s6, -1
+		bne			s6, zero, 1f
+		nop
+
+		/* Test if the current task needs the FPU context saving. */
+		lw			s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
+		beq			s6, zero, 1f
+		nop
+
+		/* Save the FPU registers. */
+		portSAVE_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
+
+		/* Save the FPU status register */
+		cfc1		s6, $f31
+		sw			s6, (portCONTEXT_SIZE + portFPCSR_STACK_LOCATION)(s5)
+
+		1:
+	#endif
+
+	/* Update the task stack pointer value if nesting is zero. */
+	la			s6, uxInterruptNesting
+	lw			s6, (s6)
+	addiu		s6, s6, -1
+	bne			s6, zero, 1f
+	nop
+
+	/* Save the stack pointer. */
+	la			s6, uxSavedTaskStackPointer
+	sw			s5, (s6)
+1:
+	.endm
+
+/******************************************************************/
+.macro	portRESTORE_CONTEXT
+
+	/* Restore the stack pointer from the TCB.  This is only done if the
+	nesting count is 1. */
+	la			s6, uxInterruptNesting
+	lw			s6, (s6)
+	addiu		s6, s6, -1
+	bne			s6, zero, 1f
+	nop
+	la			s6, uxSavedTaskStackPointer
+	lw			s5, (s6)
+
+    #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+		/* Restore the FPU context if required. */
+		lw			s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
+		beq			s6, zero, 1f
+		nop
+
+		/* Restore the FPU registers. */
+		portLOAD_FPU_REGS   ( portCONTEXT_SIZE + 8 ), s5
+
+		/* Restore the FPU status register. */
+		lw			s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
+		ctc1		s6, $f31
+   	#endif
+
+1:
+
+	/* Restore the context. */
+	lw			s6, 128(s5)
+	mthi		s6, $ac1
+	lw			s6, 124(s5)
+	mtlo		s6, $ac1
+
+	lw			s6, 136(s5)
+	mthi		s6, $ac2
+	lw			s6, 132(s5)
+	mtlo		s6, $ac2
+
+	lw			s6, 144(s5)
+	mthi		s6, $ac3
+	lw			s6, 140(s5)
+	mtlo		s6, $ac3
+
+	/* Restore DSPControl. */
+	lw			s6, 148(s5)
+	wrdsp		s6
+
+	lw			s6, 8(s5)
+	mtlo		s6, $ac0
+	lw			s6, 12(s5)
+	mthi		s6, $ac0
+	lw			$1, 16(s5)
+
+	/* s6 is loaded as it was used as a scratch register and therefore saved
+	as part of the interrupt context. */
+	lw			s7, 48(s5)
+	lw			s6, 44(s5)
+	lw			v0, 52(s5)
+	lw			v1, 56(s5)
+	lw			a0, 60(s5)
+	lw			a1, 64(s5)
+	lw			a2, 68(s5)
+	lw			a3, 72(s5)
+	lw			t0, 76(s5)
+	lw			t1, 80(s5)
+	lw			t2, 84(s5)
+	lw			t3, 88(s5)
+	lw			t4, 92(s5)
+	lw			t5, 96(s5)
+	lw			t6, 100(s5)
+	lw			t7, 104(s5)
+	lw			t8, 108(s5)
+	lw			t9, 112(s5)
+	lw			s8, 116(s5)
+	lw			ra, 120(s5)
+
+	/* Protect access to the k registers, and others. */
+	di
+	ehb
+
+	/* Decrement the nesting count. */
+	la			k0, uxInterruptNesting
+	lw			k1, (k0)
+	addiu		k1, k1, -1
+	sw			k1, 0(k0)
+
+	#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+		/* If the nesting count is now zero then the FPU context may be restored. */
+		bne			k1, zero, 1f
+		nop
+
+		/* Restore the value of ulTaskHasFPUContext */
+		la			k0, ulTaskHasFPUContext
+		lw			k1, 0(s5)
+		sw			k1, 0(k0)
+
+		/* If the task does not have an FPU context then adjust the stack normally. */
+		beq			k1, zero, 1f
+		nop
+
+		/* Restore the STATUS and EPC registers */
+		lw			k0, portSTATUS_STACK_LOCATION(s5)
+		lw			k1, portEPC_STACK_LOCATION(s5)
+
+		/* Leave the stack in its original state.  First load sp from s5, then
+		restore s5 from the stack. */
+		add			sp, zero, s5
+		lw			s5, 40(sp)
+
+		/* Adjust the stack pointer to remove the FPU context */
+		addiu		sp, sp,	portFPU_CONTEXT_SIZE
+		beq			zero, zero, 2f
+		nop
+
+		1:  /* Restore the STATUS and EPC registers */
+		lw			k0, portSTATUS_STACK_LOCATION(s5)
+		lw			k1, portEPC_STACK_LOCATION(s5)
+
+		/* Leave the stack in its original state.  First load sp from s5, then
+		restore s5 from the stack. */
+		add			sp, zero, s5
+		lw			s5, 40(sp)
+
+		2:  /* Adjust the stack pointer */
+		addiu		sp, sp, portCONTEXT_SIZE
+
+	#else
+
+		/* Restore the frame when there is no hardware FP support. */
+		lw			k0, portSTATUS_STACK_LOCATION(s5)
+		lw			k1, portEPC_STACK_LOCATION(s5)
+
+		/* Leave the stack in its original state.  First load sp from s5, then
+		restore s5 from the stack. */
+		add			sp, zero, s5
+		lw			s5, 40(sp)
+
+		addiu		sp, sp,	portCONTEXT_SIZE
+
+	#endif // ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+
+	mtc0		k0, _CP0_STATUS
+	mtc0 		k1, _CP0_EPC
+	ehb
+	eret
+	nop
+
+	.endm
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port.c
new file mode 100644
index 0000000..3e1f655
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port.c
@@ -0,0 +1,372 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the PIC32MZ port.
+  *----------------------------------------------------------*/
+
+/* Microchip specific headers. */
+#include 
+
+/* Standard headers. */
+#include 
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#if !defined(__PIC32MZ__)
+    #error This port is designed to work with XC32 on PIC32MZ MCUs.  Please update your C compiler version or settings.
+#endif
+
+#if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
+	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
+#endif
+
+/* Hardware specifics. */
+#define portTIMER_PRESCALE	8
+#define portPRESCALE_BITS	1
+
+/* Bits within various registers. */
+#define portIE_BIT					( 0x00000001 )
+#define portEXL_BIT					( 0x00000002 )
+#define portMX_BIT					( 0x01000000 ) /* Allow access to DSP instructions. */
+#define portCU1_BIT					( 0x20000000 ) /* enable CP1 for parts with hardware. */
+#define portFR_BIT					( 0x04000000 ) /* Enable 64 bit floating point registers. */
+
+/* Bits within the CAUSE register. */
+#define portCORE_SW_0				( 0x00000100 )
+#define portCORE_SW_1				( 0x00000200 )
+
+/* The EXL bit is set to ensure interrupts do not occur while the context of
+the first task is being restored. */
+#if ( __mips_hard_float == 1 )
+    #define portINITIAL_SR			( portIE_BIT | portEXL_BIT | portMX_BIT | portFR_BIT | portCU1_BIT )
+#else
+    #define portINITIAL_SR			( portIE_BIT | portEXL_BIT | portMX_BIT )
+#endif
+
+/* The initial value to store into the FPU status and control register. This is
+ only used on parts that support a hardware FPU. */
+#define portINITIAL_FPSCR			(0x1000000) /* High perf on denormal ops */
+
+
+/*
+By default port.c generates its tick interrupt from TIMER1.  The user can
+override this behaviour by:
+	1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
+	   which is the function that configures the timer.  The function is defined
+	   as a weak symbol in this file so if the same function name is used in the
+	   application code then the version in the application code will be linked
+	   into the application in preference to the version defined in this file.
+	2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
+	   to generate the tick interrupt.  For example, when timer 1 is used then
+	   configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
+	   configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
+	3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
+	   timer used to generate the tick interrupt.  For example, when timer 1 is
+	   used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
+	   IFS0CLR = _IFS0_T1IF_MASK.
+*/
+#ifndef configTICK_INTERRUPT_VECTOR
+	#define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR
+	#define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK
+#else
+	#ifndef configCLEAR_TICK_TIMER_INTERRUPT
+		#error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
+	#endif
+#endif
+
+/* Let the user override the pre-loading of the initial RA with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
+stack checking.  A problem in the ISR stack will trigger an assert, not call the
+stack overflow hook function (because the stack overflow hook is specific to a
+task stack, not the ISR stack). */
+#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
+
+	/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
+	the task stacks, and so will legitimately appear in many positions within
+	the ISR stack. */
+	#define portISR_STACK_FILL_BYTE	0xee
+
+	static const uint8_t ucExpectedStackBytes[] = {
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE };	\
+
+	#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else
+	/* Define the function away. */
+	#define portCHECK_ISR_STACK()
+#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Records the interrupt nesting depth.  This is initialised to one as it is
+decremented to 0 when the first task starts. */
+volatile UBaseType_t uxInterruptNesting = 0x01;
+
+/* Stores the task stack pointer when a switch is made to use the system stack. */
+UBaseType_t uxSavedTaskStackPointer = 0;
+
+/* The stack used by interrupt service routines that cause a context switch. */
+__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
+
+/* The top of stack value ensures there is enough space to store 6 registers on
+the callers stack, as some functions seem to want to do this.  8 byte alignment
+is required to allow double word floating point stack pushes generated by the
+compiler. */
+const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] );
+
+/* Saved as part of the task context. Set to pdFALSE if the task does not
+ require an FPU context. */
+#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+	uint32_t ulTaskHasFPUContext = 0;
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Ensure 8 byte alignment is maintained when leaving this function. */
+	pxTopOfStack--;
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) 0xDEADBEEF;
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) 0x12345678;	/* Word to which the stack pointer will be left pointing after context restore. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) _CP0_GET_CAUSE();
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) portINITIAL_SR;/* CP0_STATUS */
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) pxCode; 		/* CP0_EPC */
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) 0x00000000;	/* DSPControl */
+	pxTopOfStack -= 7;  						/* Includes space for AC1 - AC3. */
+
+	*pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS;	/* ra */
+	pxTopOfStack -= 15;
+
+	*pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
+	pxTopOfStack -= 15;
+
+	*pxTopOfStack = (StackType_t) pdFALSE; /*by default disable FPU context save on parts with FPU */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxSavedTaskStackPointer == 0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup a timer for a regular tick.  This function uses peripheral timer 1.
+ * The function is declared weak so an application writer can use a different
+ * timer by redefining this implementation.  If a different timer is used then
+ * configTICK_INTERRUPT_VECTOR must also be defined in FreeRTOSConfig.h to
+ * ensure the RTOS provided tick interrupt handler is installed on the correct
+ * vector number.  When Timer 1 is used the vector number is defined as
+ * _TIMER_1_VECTOR.
+ */
+__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
+{
+const uint32_t ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE) / configTICK_RATE_HZ ) - 1UL;
+
+	T1CON = 0x0000;
+	T1CONbits.TCKPS = portPRESCALE_BITS;
+	PR1 = ulCompareMatch;
+	IPC1bits.T1IP = configKERNEL_INTERRUPT_PRIORITY;
+
+	/* Clear the interrupt as a starting condition. */
+	IFS0bits.T1IF = 0;
+
+	/* Enable the interrupt. */
+	IEC0bits.T1IE = 1;
+
+	/* Start the timer. */
+	T1CONbits.TON = 1;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler(void)
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxInterruptNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+extern void *pxCurrentTCB;
+
+	#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
+	{
+		/* Fill the ISR stack to make it easy to asses how much is being used. */
+		memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
+	}
+	#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
+
+	/* Clear the software interrupt flag. */
+	IFS0CLR = _IFS0_CS0IF_MASK;
+
+	/* Set software timer priority. */
+	IPC0CLR = _IPC0_CS0IP_MASK;
+	IPC0SET = ( configKERNEL_INTERRUPT_PRIORITY << _IPC0_CS0IP_POSITION );
+
+	/* Enable software interrupt. */
+	IEC0CLR = _IEC0_CS0IE_MASK;
+	IEC0SET = 1 << _IEC0_CS0IE_POSITION;
+
+	/* Setup the timer to generate the tick.  Interrupts will have been
+	disabled by the time we get here. */
+	vApplicationSetupTickTimerInterrupt();
+
+	/* Kick off the highest priority task that has been created so far.
+	Its stack location is loaded into uxSavedTaskStackPointer. */
+	uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
+	vPortStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing!  Call the task
+	exit error function to prevent compiler warnings about a static function
+	not being called in the case that the application writer overrides this
+	functionality by defining configTASK_RETURN_ADDRESS. */
+	prvTaskExitError();
+
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortIncrementTick( void )
+{
+UBaseType_t uxSavedStatus;
+
+	uxSavedStatus = uxPortSetInterruptMaskFromISR();
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			_CP0_BIS_CAUSE( portCORE_SW_0 );
+		}
+	}
+	vPortClearInterruptMaskFromISR( uxSavedStatus );
+
+	/* Look for the ISR stack getting near or past its limit. */
+	portCHECK_ISR_STACK();
+
+	/* Clear timer interrupt. */
+	configCLEAR_TICK_TIMER_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxPortSetInterruptMaskFromISR( void )
+{
+UBaseType_t uxSavedStatusRegister;
+
+	__builtin_disable_interrupts();
+	uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
+	/* This clears the IPL bits, then sets them to
+	configMAX_SYSCALL_INTERRUPT_PRIORITY.  This function should not be called
+	from an interrupt that has a priority above
+	configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
+	can only result in the IPL being unchanged or raised, and therefore never
+	lowered. */
+	_CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
+
+	return uxSavedStatusRegister;
+}
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
+{
+	_CP0_SET_STATUS( uxSavedStatusRegister );
+}
+/*-----------------------------------------------------------*/
+
+#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+
+	void vPortTaskUsesFPU(void)
+	{
+	extern void vPortInitialiseFPSCR( uint32_t uxFPSCRInit );
+
+		portENTER_CRITICAL();
+
+		/* Initialise the floating point status register. */
+		vPortInitialiseFPSCR(portINITIAL_FPSCR);
+
+		/* A task is registering the fact that it needs a FPU context. Set the
+		FPU flag (saved as part of the task context). */
+		ulTaskHasFPUContext = pdTRUE;
+
+		portEXIT_CRITICAL();
+	}
+
+#endif /* __mips_hard_float == 1 */
+
+/*-----------------------------------------------------------*/
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port_asm.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port_asm.S
new file mode 100644
index 0000000..58d8e40
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port_asm.S
@@ -0,0 +1,768 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include 
+#include 
+#include "FreeRTOSConfig.h"
+#include "ISR_Support.h"
+
+	.extern pxCurrentTCB
+	.extern vTaskSwitchContext
+	.extern vPortIncrementTick
+	.extern xISRStackTop
+	.extern ulTaskHasFPUContext
+
+	.global vPortStartFirstTask
+	.global vPortYieldISR
+	.global vPortTickInterruptHandler
+	.global vPortInitialiseFPSCR
+
+
+/******************************************************************/
+
+	.set  nomips16
+	.set  nomicromips
+	.set  noreorder
+	.set  noat
+
+	/***************************************************************
+	*  The following is needed to locate the
+	*  vPortTickInterruptHandler function into the correct vector
+	***************************************************************/
+	#ifdef configTICK_INTERRUPT_VECTOR
+		#if (configTICK_INTERRUPT_VECTOR == _CORE_TIMER_VECTOR)
+			.equ     __vector_dispatch_0, vPortTickInterruptHandler
+			.global  __vector_dispatch_0
+			.section .vector_0, code, keep
+		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_1_VECTOR)
+			.equ     __vector_dispatch_4, vPortTickInterruptHandler
+			.global  __vector_dispatch_4
+			.section .vector_4, code, keep
+		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_2_VECTOR)
+			.equ     __vector_dispatch_9, vPortTickInterruptHandler
+			.global  __vector_dispatch_9
+			.section .vector_9, code, keep
+		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_3_VECTOR)
+			.equ     __vector_dispatch_14, vPortTickInterruptHandler
+			.global  __vector_dispatch_14
+			.section .vector_14, code, keep
+		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_4_VECTOR)
+			.equ     __vector_dispatch_19, vPortTickInterruptHandler
+			.global  __vector_dispatch_19
+			.section .vector_19, code, keep
+		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_5_VECTOR)
+			.equ     __vector_dispatch_24, vPortTickInterruptHandler
+			.global  __vector_dispatch_24
+			.section .vector_24, code, keep
+		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_6_VECTOR)
+			.equ     __vector_dispatch_28, vPortTickInterruptHandler
+			.global  __vector_dispatch_28
+			.section .vector_28, code, keep
+		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_7_VECTOR)
+			.equ     __vector_dispatch_32, vPortTickInterruptHandler
+			.global  __vector_dispatch_32
+			.section .vector_32, code, keep
+		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_8_VECTOR)
+			.equ     __vector_dispatch_36, vPortTickInterruptHandler
+			.global  __vector_dispatch_36
+			.section .vector_36, code, keep
+		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_9_VECTOR)
+			.equ     __vector_dispatch_40, vPortTickInterruptHandler
+			.global  __vector_dispatch_40
+			.section .vector_40, code, keep
+		#endif
+	#else
+		.equ     __vector_dispatch_4, vPortTickInterruptHandler
+		.global  __vector_dispatch_4
+		.section .vector_4, code, keep
+	#endif
+
+	.ent		vPortTickInterruptHandler
+
+vPortTickInterruptHandler:
+
+	portSAVE_CONTEXT
+
+	jal 		vPortIncrementTick
+	nop
+
+	portRESTORE_CONTEXT
+
+	.end vPortTickInterruptHandler
+
+/******************************************************************/
+
+	.set		noreorder
+	.set 		noat
+	.section .text, code
+	.ent		vPortStartFirstTask
+
+vPortStartFirstTask:
+
+	/* Simply restore the context of the highest priority task that has been
+	created so far. */
+	portRESTORE_CONTEXT
+
+	.end vPortStartFirstTask
+
+
+
+/*******************************************************************/
+
+	.set  nomips16
+	.set  nomicromips
+	.set  noreorder
+	.set  noat
+	/***************************************************************
+	*  The following is needed to locate the vPortYieldISR function
+	*  into the correct vector
+	***************************************************************/
+	.equ     __vector_dispatch_1, vPortYieldISR
+	.global  __vector_dispatch_1
+	.section .vector_1, code
+
+	.ent  vPortYieldISR
+vPortYieldISR:
+
+	#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+		/* Code sequence for FPU support, the context save requires advance
+		knowledge of the stack frame size and if the current task actually uses the 
+		FPU. */
+
+		/* Make room for the context. First save the current status so it can be
+		manipulated, and the cause and EPC registers so their original values are
+		captured. */
+		la		k0, ulTaskHasFPUContext
+		lw		k0, 0(k0)
+		beq		k0, zero, 1f
+		addiu	sp, sp, -portCONTEXT_SIZE	/* always reserve space for the context. */
+		addiu	sp, sp, -portFPU_CONTEXT_SIZE	/* reserve additional space for the FPU context. */
+	1:
+		mfc0	k1, _CP0_STATUS
+
+		/* Also save s6 and s5 so they can be used.  Any nesting interrupts should
+		maintain the values of these registers across the ISR. */
+		sw		s6, 44(sp)
+		sw		s5, 40(sp)
+		sw		k1, portSTATUS_STACK_LOCATION(sp)
+		sw		k0, portTASK_HAS_FPU_STACK_LOCATION(sp)
+
+		/* Prepare to re-enabled interrupts above the kernel priority. */
+		ins 	k1, zero, 10, 7         /* Clear IPL bits 0:6. */
+		ins 	k1, zero, 18, 1         /* Clear IPL bit 7.  It would be an error here if this bit were set anyway. */
+		ori		k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
+		ins		k1, zero, 1, 4          /* Clear EXL, ERL and UM. */
+
+		/* s5 is used as the frame pointer. */
+		add		s5, zero, sp
+
+		/* Swap to the system stack.  This is not conditional on the nesting
+		count as this interrupt is always the lowest priority and therefore
+		the nesting is always 0. */
+		la		sp, xISRStackTop
+		lw		sp, (sp)
+
+		/* Set the nesting count. */
+		la		k0, uxInterruptNesting
+		addiu	s6, zero, 1
+		sw		s6, 0(k0)
+
+		/* s6 holds the EPC value, this is saved with the rest of the context
+		after interrupts are enabled. */
+		mfc0 	s6, _CP0_EPC
+
+		/* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+		mtc0	k1, _CP0_STATUS
+
+		/* Save the context into the space just created.  s6 is saved again
+		here as it now contains the EPC value. */
+		sw		ra, 120(s5)
+		sw		s8, 116(s5)
+		sw		t9, 112(s5)
+		sw		t8, 108(s5)
+		sw		t7, 104(s5)
+		sw		t6, 100(s5)
+		sw		t5, 96(s5)
+		sw		t4, 92(s5)
+		sw		t3, 88(s5)
+		sw		t2, 84(s5)
+		sw		t1, 80(s5)
+		sw		t0, 76(s5)
+		sw		a3, 72(s5)
+		sw		a2, 68(s5)
+		sw		a1, 64(s5)
+		sw		a0, 60(s5)
+		sw		v1, 56(s5)
+		sw		v0, 52(s5)
+		sw		s7, 48(s5)
+		sw		s6, portEPC_STACK_LOCATION(s5)
+		/* s5 and s6 has already been saved. */
+		sw		s4, 36(s5)
+		sw		s3, 32(s5)
+		sw		s2, 28(s5)
+		sw		s1, 24(s5)
+		sw		s0, 20(s5)
+		sw		$1, 16(s5)
+
+		/* s7 is used as a scratch register as this should always be saved across
+		nesting interrupts. */
+
+		/* Save the AC0, AC1, AC2 and AC3. */
+		mfhi	s7, $ac1
+		sw		s7, 128(s5)
+		mflo	s7, $ac1
+		sw		s7, 124(s5)
+
+		mfhi	s7, $ac2
+		sw		s7, 136(s5)
+		mflo	s7, $ac2
+		sw		s7, 132(s5)
+
+		mfhi	s7, $ac3
+		sw		s7, 144(s5)
+		mflo	s7, $ac3
+		sw		s7, 140(s5)
+
+		rddsp	s7
+		sw		s7, 148(s5)
+
+		mfhi	s7, $ac0
+		sw		s7, 12(s5)
+		mflo	s7, $ac0
+		sw		s7, 8(s5)
+
+		/* Test if FPU context save is required. */
+		lw		s7, portTASK_HAS_FPU_STACK_LOCATION(s5)
+		beq		s7, zero, 1f
+		nop
+
+		/* Save the FPU registers above the normal context. */
+		portSAVE_FPU_REGS   (portCONTEXT_SIZE + 8), s5
+
+		/* Save the FPU status register */
+		cfc1	s7, $f31
+		sw		s7, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
+
+	1:
+		/* Save the stack pointer to the task. */
+		la		s7, pxCurrentTCB
+		lw		s7, (s7)
+		sw		s5, (s7)
+
+		/* Set the interrupt mask to the max priority that can use the API.  The
+		yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which
+		is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever
+		raise the IPL value and never lower it. */
+		di
+		ehb
+		mfc0	s7, _CP0_STATUS
+		ins 	s7, zero, 10, 7
+		ins 	s7, zero, 18, 1
+		ori		s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
+
+		/* This mtc0 re-enables interrupts, but only above
+		configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+		mtc0	s6, _CP0_STATUS
+		ehb
+
+		/* Clear the software interrupt in the core. */
+		mfc0	s6, _CP0_CAUSE
+		ins		s6, zero, 8, 1
+		mtc0	s6, _CP0_CAUSE
+		ehb
+
+		/* Clear the interrupt in the interrupt controller. */
+		la		s6, IFS0CLR
+		addiu	s4, zero, 2
+		sw		s4, (s6)
+
+		jal		vTaskSwitchContext
+		nop
+
+		/* Clear the interrupt mask again.  The saved status value is still in s7. */
+		mtc0	s7, _CP0_STATUS
+		ehb
+
+		/* Restore the stack pointer from the TCB. */
+		la		s0, pxCurrentTCB
+		lw		s0, (s0)
+		lw		s5, (s0)
+
+		/* Test if the FPU context needs restoring. */
+		lw		s0, portTASK_HAS_FPU_STACK_LOCATION(s5)
+		beq		s0, zero, 1f
+		nop
+
+		/* Restore the FPU status register. */
+		lw		s0, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
+		ctc1	s0, $f31
+
+		/* Restore the FPU registers. */
+		portLOAD_FPU_REGS   ( portCONTEXT_SIZE + 8 ), s5
+
+	1:
+		/* Restore the rest of the context. */
+		lw		s0, 128(s5)
+		mthi	s0, $ac1
+		lw		s0, 124(s5)
+		mtlo		s0, $ac1
+
+		lw		s0, 136(s5)
+		mthi	s0, $ac2
+		lw		s0, 132(s5)
+		mtlo	s0, $ac2
+
+		lw		s0, 144(s5)
+		mthi	s0, $ac3
+		lw		s0, 140(s5)
+		mtlo	s0, $ac3
+
+		lw		s0, 148(s5)
+		wrdsp	s0
+
+		lw		s0, 8(s5)
+		mtlo	s0, $ac0
+		lw		s0, 12(s5)
+		mthi	s0, $ac0
+
+		lw		$1, 16(s5)
+		lw		s0, 20(s5)
+		lw		s1, 24(s5)
+		lw		s2, 28(s5)
+		lw		s3, 32(s5)
+		lw		s4, 36(s5)
+
+		/* s5 is loaded later. */
+		lw		s6, 44(s5)
+		lw		s7, 48(s5)
+		lw		v0, 52(s5)
+		lw		v1, 56(s5)
+		lw		a0, 60(s5)
+		lw		a1, 64(s5)
+		lw		a2, 68(s5)
+		lw		a3, 72(s5)
+		lw		t0, 76(s5)
+		lw		t1, 80(s5)
+		lw		t2, 84(s5)
+		lw		t3, 88(s5)
+		lw		t4, 92(s5)
+		lw		t5, 96(s5)
+		lw		t6, 100(s5)
+		lw		t7, 104(s5)
+		lw		t8, 108(s5)
+		lw		t9, 112(s5)
+		lw		s8, 116(s5)
+		lw		ra, 120(s5)
+
+		/* Protect access to the k registers, and others. */
+		di
+		ehb
+
+		/* Set nesting back to zero.  As the lowest priority interrupt this
+		interrupt cannot have nested. */
+		la		k0, uxInterruptNesting
+		sw		zero, 0(k0)
+
+		/* Switch back to use the real stack pointer. */
+		add		sp, zero, s5
+
+		/* Restore the real s5 value. */
+		lw		s5, 40(sp)
+
+		/* Pop the FPU context value from the stack */
+		lw		k0, portTASK_HAS_FPU_STACK_LOCATION(sp)
+		la		k1, ulTaskHasFPUContext
+		sw		k0, 0(k1)
+		beq		k0, zero, 1f
+		nop
+
+		/* task has FPU context so adjust the stack frame after popping the
+		status and epc values. */
+		lw		k1, portSTATUS_STACK_LOCATION(sp)
+		lw		k0, portEPC_STACK_LOCATION(sp)
+		addiu	sp, sp, portFPU_CONTEXT_SIZE
+		beq		zero, zero, 2f
+		nop
+
+	1:
+		/* Pop the status and epc values. */
+		lw		k1, portSTATUS_STACK_LOCATION(sp)
+		lw		k0, portEPC_STACK_LOCATION(sp)
+
+	2:
+		/* Remove stack frame. */
+		addiu	sp, sp, portCONTEXT_SIZE
+
+	#else
+		/* Code sequence for no FPU support, the context save requires advance
+		knowledge of the stack frame size when no FPU is being used */
+
+		/* Make room for the context. First save the current status so it can be
+		manipulated, and the cause and EPC registers so thier original values are
+		captured. */
+		addiu	sp, sp, -portCONTEXT_SIZE
+		mfc0	k1, _CP0_STATUS
+
+		/* Also save s6 and s5 so they can be used.  Any nesting interrupts should
+		maintain the values of these registers across the ISR. */
+		sw		s6, 44(sp)
+		sw		s5, 40(sp)
+		sw		k1, portSTATUS_STACK_LOCATION(sp)
+
+		/* Prepare to re-enabled interrupts above the kernel priority. */
+		ins 	k1, zero, 10, 7         /* Clear IPL bits 0:6. */
+		ins 	k1, zero, 18, 1         /* Clear IPL bit 7.  It would be an error here if this bit were set anyway. */
+		ori		k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
+		ins		k1, zero, 1, 4          /* Clear EXL, ERL and UM. */
+
+		/* s5 is used as the frame pointer. */
+		add		s5, zero, sp
+
+		/* Swap to the system stack.  This is not conditional on the nesting
+		count as this interrupt is always the lowest priority and therefore
+		the nesting is always 0. */
+		la		sp, xISRStackTop
+		lw		sp, (sp)
+
+		/* Set the nesting count. */
+		la		k0, uxInterruptNesting
+		addiu	s6, zero, 1
+		sw		s6, 0(k0)
+
+		/* s6 holds the EPC value, this is saved with the rest of the context
+		after interrupts are enabled. */
+		mfc0 	s6, _CP0_EPC
+
+		/* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+		mtc0	k1, _CP0_STATUS
+
+		/* Save the context into the space just created.  s6 is saved again
+		here as it now contains the EPC value. */
+		sw		ra, 120(s5)
+		sw		s8, 116(s5)
+		sw		t9, 112(s5)
+		sw		t8, 108(s5)
+		sw		t7, 104(s5)
+		sw		t6, 100(s5)
+		sw		t5, 96(s5)
+		sw		t4, 92(s5)
+		sw		t3, 88(s5)
+		sw		t2, 84(s5)
+		sw		t1, 80(s5)
+		sw		t0, 76(s5)
+		sw		a3, 72(s5)
+		sw		a2, 68(s5)
+		sw		a1, 64(s5)
+		sw		a0, 60(s5)
+		sw		v1, 56(s5)
+		sw		v0, 52(s5)
+		sw		s7, 48(s5)
+		sw		s6, portEPC_STACK_LOCATION(s5)
+		/* s5 and s6 has already been saved. */
+		sw		s4, 36(s5)
+		sw		s3, 32(s5)
+		sw		s2, 28(s5)
+		sw		s1, 24(s5)
+		sw		s0, 20(s5)
+		sw		$1, 16(s5)
+
+		/* s7 is used as a scratch register as this should always be saved across
+		nesting interrupts. */
+
+		/* Save the AC0, AC1, AC2 and AC3. */
+		mfhi	s7, $ac1
+		sw		s7, 128(s5)
+		mflo	s7, $ac1
+		sw		s7, 124(s5)
+
+		mfhi	s7, $ac2
+		sw		s7, 136(s5)
+		mflo	s7, $ac2
+		sw		s7, 132(s5)
+
+		mfhi	s7, $ac3
+		sw		s7, 144(s5)
+		mflo	s7, $ac3
+		sw		s7, 140(s5)
+
+		rddsp	s7
+		sw		s7, 148(s5)
+
+		mfhi	s7, $ac0
+		sw		s7, 12(s5)
+		mflo	s7, $ac0
+		sw		s7, 8(s5)
+
+		/* Save the stack pointer to the task. */
+		la		s7, pxCurrentTCB
+		lw		s7, (s7)
+		sw		s5, (s7)
+
+		/* Set the interrupt mask to the max priority that can use the API.  The
+		yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which
+		is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever
+		raise the IPL value and never lower it. */
+		di
+		ehb
+		mfc0	s7, _CP0_STATUS
+		ins 	s7, zero, 10, 7
+		ins 	s7, zero, 18, 1
+		ori		s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
+
+		/* This mtc0 re-enables interrupts, but only above
+		configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+		mtc0	s6, _CP0_STATUS
+		ehb
+
+		/* Clear the software interrupt in the core. */
+		mfc0	s6, _CP0_CAUSE
+		ins		s6, zero, 8, 1
+		mtc0	s6, _CP0_CAUSE
+		ehb
+
+		/* Clear the interrupt in the interrupt controller. */
+		la		s6, IFS0CLR
+		addiu	s4, zero, 2
+		sw		s4, (s6)
+
+		jal		vTaskSwitchContext
+		nop
+
+		/* Clear the interrupt mask again.  The saved status value is still in s7. */
+		mtc0	s7, _CP0_STATUS
+		ehb
+
+		/* Restore the stack pointer from the TCB. */
+		la		s0, pxCurrentTCB
+		lw		s0, (s0)
+		lw		s5, (s0)
+
+		/* Restore the rest of the context. */
+		lw		s0, 128(s5)
+		mthi	s0, $ac1
+		lw		s0, 124(s5)
+		mtlo	s0, $ac1
+
+		lw		s0, 136(s5)
+		mthi	s0, $ac2
+		lw		s0, 132(s5)
+		mtlo	s0, $ac2
+
+		lw		s0, 144(s5)
+		mthi	s0, $ac3
+		lw		s0, 140(s5)
+		mtlo	s0, $ac3
+
+		lw		s0, 148(s5)
+		wrdsp	s0
+
+		lw		s0, 8(s5)
+		mtlo	s0, $ac0
+		lw		s0, 12(s5)
+		mthi	s0, $ac0
+
+		lw		$1, 16(s5)
+		lw		s0, 20(s5)
+		lw		s1, 24(s5)
+		lw		s2, 28(s5)
+		lw		s3, 32(s5)
+		lw		s4, 36(s5)
+
+		/* s5 is loaded later. */
+		lw		s6, 44(s5)
+		lw		s7, 48(s5)
+		lw		v0, 52(s5)
+		lw		v1, 56(s5)
+		lw		a0, 60(s5)
+		lw		a1, 64(s5)
+		lw		a2, 68(s5)
+		lw		a3, 72(s5)
+		lw		t0, 76(s5)
+		lw		t1, 80(s5)
+		lw		t2, 84(s5)
+		lw		t3, 88(s5)
+		lw		t4, 92(s5)
+		lw		t5, 96(s5)
+		lw		t6, 100(s5)
+		lw		t7, 104(s5)
+		lw		t8, 108(s5)
+		lw		t9, 112(s5)
+		lw		s8, 116(s5)
+		lw		ra, 120(s5)
+
+		/* Protect access to the k registers, and others. */
+		di
+		ehb
+
+		/* Set nesting back to zero.  As the lowest priority interrupt this
+		interrupt cannot have nested. */
+		la		k0, uxInterruptNesting
+		sw		zero, 0(k0)
+
+		/* Switch back to use the real stack pointer. */
+		add		sp, zero, s5
+
+		/* Restore the real s5 value. */
+		lw		s5, 40(sp)
+
+		/* Pop the status and epc values. */
+		lw		k1, portSTATUS_STACK_LOCATION(sp)
+		lw		k0, portEPC_STACK_LOCATION(sp)
+
+		/* Remove stack frame. */
+		addiu	sp, sp, portCONTEXT_SIZE
+
+	#endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
+
+	/* Restore the status and EPC registers and return */
+	mtc0	k1, _CP0_STATUS
+	mtc0 	k0, _CP0_EPC
+	ehb
+	eret
+	nop
+
+	.end	vPortYieldISR
+
+/******************************************************************/
+
+#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+
+	.macro portFPUSetAndInc reg, dest
+	mtc1	\reg, \dest
+	cvt.d.w	\dest, \dest
+	addiu	\reg, \reg, 1
+	.endm
+
+	.set	noreorder
+	.set 	noat
+	.section .text, code
+	.ent	vPortInitialiseFPSCR
+
+vPortInitialiseFPSCR:
+
+	/* Initialize the floating point status register in CP1. The initial
+	value is passed in a0. */
+	ctc1		a0, $f31
+
+	/* Clear the FPU registers */
+	addiu			a0, zero, 0x0000
+	portFPUSetAndInc	a0, $f0
+	portFPUSetAndInc	a0, $f1
+	portFPUSetAndInc	a0, $f2
+	portFPUSetAndInc	a0, $f3
+	portFPUSetAndInc	a0, $f4
+	portFPUSetAndInc	a0, $f5
+	portFPUSetAndInc	a0, $f6
+	portFPUSetAndInc	a0, $f7
+	portFPUSetAndInc	a0, $f8
+	portFPUSetAndInc	a0, $f9
+	portFPUSetAndInc	a0, $f10
+	portFPUSetAndInc	a0, $f11
+	portFPUSetAndInc	a0, $f12
+	portFPUSetAndInc	a0, $f13
+	portFPUSetAndInc	a0, $f14
+	portFPUSetAndInc	a0, $f15
+	portFPUSetAndInc	a0, $f16
+	portFPUSetAndInc	a0, $f17
+	portFPUSetAndInc	a0, $f18
+	portFPUSetAndInc	a0, $f19
+	portFPUSetAndInc	a0, $f20
+	portFPUSetAndInc	a0, $f21
+	portFPUSetAndInc	a0, $f22
+	portFPUSetAndInc	a0, $f23
+	portFPUSetAndInc	a0, $f24
+	portFPUSetAndInc	a0, $f25
+	portFPUSetAndInc	a0, $f26
+	portFPUSetAndInc	a0, $f27
+	portFPUSetAndInc	a0, $f28
+	portFPUSetAndInc	a0, $f29
+	portFPUSetAndInc	a0, $f30
+	portFPUSetAndInc	a0, $f31
+
+	jr		ra
+	nop
+
+	.end vPortInitialiseFPSCR
+
+#endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
+	
+#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+
+	/**********************************************************************/
+	/* Test read back								*/
+	/* a0 = address to store registers				*/
+
+	.set		noreorder
+	.set 		noat
+	.section	.text, code
+	.ent		vPortFPUReadback
+	.global		vPortFPUReadback
+
+vPortFPUReadback:
+	sdc1		$f0, 0(a0)
+	sdc1		$f1, 8(a0)
+	sdc1		$f2, 16(a0)
+	sdc1		$f3, 24(a0)
+	sdc1		$f4, 32(a0)
+	sdc1		$f5, 40(a0)
+	sdc1		$f6, 48(a0)
+	sdc1		$f7, 56(a0)
+	sdc1		$f8, 64(a0)
+	sdc1		$f9, 72(a0)
+	sdc1		$f10, 80(a0)
+	sdc1		$f11, 88(a0)
+	sdc1		$f12, 96(a0)
+	sdc1		$f13, 104(a0)
+	sdc1		$f14, 112(a0)
+	sdc1		$f15, 120(a0)
+	sdc1		$f16, 128(a0)
+	sdc1		$f17, 136(a0)
+	sdc1		$f18, 144(a0)
+	sdc1		$f19, 152(a0)
+	sdc1		$f20, 160(a0)
+	sdc1		$f21, 168(a0)
+	sdc1		$f22, 176(a0)
+	sdc1		$f23, 184(a0)
+	sdc1		$f24, 192(a0)
+	sdc1		$f25, 200(a0)
+	sdc1		$f26, 208(a0)
+	sdc1		$f27, 216(a0)
+	sdc1		$f28, 224(a0)
+	sdc1		$f29, 232(a0)
+	sdc1		$f30, 240(a0)
+	sdc1		$f31, 248(a0)
+
+	jr		ra
+	nop
+
+	.end vPortFPUReadback
+
+#endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MZ/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MZ/portmacro.h
new file mode 100644
index 0000000..061b901
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MPLAB/PIC32MZ/portmacro.h
@@ -0,0 +1,215 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* System include files */
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			8
+#define portSTACK_GROWTH			-1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#define portIPL_SHIFT				( 10UL )
+/* Don't straddle the CEE bit.  Interrupts calling FreeRTOS functions should
+never have higher IPL bits set anyway. */
+#define portALL_IPL_BITS			( 0x7FUL << portIPL_SHIFT )
+#define portSW0_BIT					( 0x01 << 8 )
+
+/* This clears the IPL bits, then sets them to
+configMAX_SYSCALL_INTERRUPT_PRIORITY.  An extra check is performed if
+configASSERT() is defined to ensure an assertion handler does not inadvertently
+attempt to lower the IPL when the call to assert was triggered because the IPL
+value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
+safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
+those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
+ensure API function and interrupt entry is as fast and as simple as possible. */
+#ifdef configASSERT
+	#define portDISABLE_INTERRUPTS()											\
+	{																			\
+	uint32_t ulStatus;															\
+																				\
+		/* Mask interrupts at and below the kernel interrupt priority. */		\
+		ulStatus = _CP0_GET_STATUS();											\
+																				\
+		/* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */	\
+		if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
+		{																		\
+			ulStatus &= ~portALL_IPL_BITS;										\
+			_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
+		}																		\
+	}
+#else /* configASSERT */
+	#define portDISABLE_INTERRUPTS()										\
+	{																		\
+	uint32_t ulStatus;														\
+																			\
+		/* Mask interrupts at and below the kernel interrupt priority. */	\
+		ulStatus = _CP0_GET_STATUS();										\
+		ulStatus &= ~portALL_IPL_BITS;										\
+		_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
+	}
+#endif /* configASSERT */
+
+#define portENABLE_INTERRUPTS()											\
+{																		\
+uint32_t ulStatus;														\
+																		\
+	/* Unmask all interrupts. */										\
+	ulStatus = _CP0_GET_STATUS();										\
+	ulStatus &= ~portALL_IPL_BITS;										\
+	_CP0_SET_STATUS( ulStatus );										\
+}
+
+
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portCRITICAL_NESTING_IN_TCB	1
+#define portENTER_CRITICAL()		vTaskEnterCritical()
+#define portEXIT_CRITICAL()			vTaskExitCritical()
+
+extern UBaseType_t uxPortSetInterruptMaskFromISR();
+extern void vPortClearInterruptMaskFromISR( UBaseType_t );
+#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
+
+#if ( __mips_hard_float == 0 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+    #error configUSE_TASK_FPU_SUPPORT can only be set to 1 when the part supports a hardware FPU module.
+#endif
+
+#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+    void vPortTaskUsesFPU( void );
+	#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+#endif
+
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
+
+#endif /* taskRECORD_READY_PRIORITY */
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+#define portYIELD()								\
+{												\
+uint32_t ulCause;								\
+												\
+	/* Trigger software interrupt. */			\
+	ulCause = _CP0_GET_CAUSE();					\
+	ulCause |= portSW0_BIT;						\
+	_CP0_SET_CAUSE( ulCause );					\
+}
+
+extern volatile UBaseType_t uxInterruptNesting;
+#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
+
+#define portNOP()	__asm volatile ( "nop" )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#define portEND_SWITCHING_ISR( xSwitchRequired )	if( xSwitchRequired )	\
+													{						\
+														portYIELD();		\
+													}
+
+/* Required by the kernel aware debugger. */
+#ifdef __DEBUG
+	#define portREMOVE_STATIC_QUALIFIER
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MSVC-MingW/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MSVC-MingW/port.c
new file mode 100644
index 0000000..4b7758f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MSVC-MingW/port.c
@@ -0,0 +1,620 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifdef __GNUC__
+	#include "mmsystem.h"
+#else
+	#pragma comment(lib, "winmm.lib")
+#endif
+
+#define portMAX_INTERRUPTS				( ( uint32_t ) sizeof( uint32_t ) * 8UL ) /* The number of bits in an uint32_t. */
+#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
+
+/* The priorities at which the various components of the simulation execute. */
+#define portDELETE_SELF_THREAD_PRIORITY			 THREAD_PRIORITY_TIME_CRITICAL /* Must be highest. */
+#define portSIMULATED_INTERRUPTS_THREAD_PRIORITY THREAD_PRIORITY_TIME_CRITICAL
+#define portSIMULATED_TIMER_THREAD_PRIORITY		 THREAD_PRIORITY_HIGHEST
+#define portTASK_THREAD_PRIORITY				 THREAD_PRIORITY_ABOVE_NORMAL
+
+/*
+ * Created as a high priority thread, this function uses a timer to simulate
+ * a tick interrupt being generated on an embedded target.  In this Windows
+ * environment the timer does not achieve anything approaching real time
+ * performance though.
+ */
+static DWORD WINAPI prvSimulatedPeripheralTimer( LPVOID lpParameter );
+
+/*
+ * Process all the simulated interrupts - each represented by a bit in
+ * ulPendingInterrupts variable.
+ */
+static void prvProcessSimulatedInterrupts( void );
+
+/*
+ * Interrupt handlers used by the kernel itself.  These are executed from the
+ * simulated interrupt handler thread.
+ */
+static uint32_t prvProcessYieldInterrupt( void );
+static uint32_t prvProcessTickInterrupt( void );
+
+/*
+ * Called when the process exits to let Windows know the high timer resolution
+ * is no longer required.
+ */
+static BOOL WINAPI prvEndProcess( DWORD dwCtrlType );
+
+/*-----------------------------------------------------------*/
+
+/* The WIN32 simulator runs each task in a thread.  The context switching is
+managed by the threads, so the task stack does not have to be managed directly,
+although the task stack is still used to hold an xThreadState structure this is
+the only thing it will ever hold.  The structure indirectly maps the task handle
+to a thread handle. */
+typedef struct
+{
+	/* Handle of the thread that executes the task. */
+	void *pvThread;
+
+} xThreadState;
+
+/* Simulated interrupts waiting to be processed.  This is a bit mask where each
+bit represents one interrupt, so a maximum of 32 interrupts can be simulated. */
+static volatile uint32_t ulPendingInterrupts = 0UL;
+
+/* An event used to inform the simulated interrupt processing thread (a high
+priority thread that simulated interrupt processing) that an interrupt is
+pending. */
+static void *pvInterruptEvent = NULL;
+
+/* Mutex used to protect all the simulated interrupt variables that are accessed
+by multiple threads. */
+static void *pvInterruptEventMutex = NULL;
+
+/* The critical nesting count for the currently executing task.  This is
+initialised to a non-zero value so interrupts do not become enabled during
+the initialisation phase.  As each task has its own critical nesting value
+ulCriticalNesting will get set to zero when the first task runs.  This
+initialisation is probably not critical in this simulated environment as the
+simulated interrupt handlers do not get created until the FreeRTOS scheduler is
+started anyway. */
+static uint32_t ulCriticalNesting = 9999UL;
+
+/* Handlers for all the simulated software interrupts.  The first two positions
+are used for the Yield and Tick interrupts so are handled slightly differently,
+all the other interrupts can be user defined. */
+static uint32_t (*ulIsrHandler[ portMAX_INTERRUPTS ])( void ) = { 0 };
+
+/* Pointer to the TCB of the currently executing task. */
+extern void *pxCurrentTCB;
+
+/* Used to ensure nothing is processed during the startup sequence. */
+static BaseType_t xPortRunning = pdFALSE;
+
+/*-----------------------------------------------------------*/
+
+static DWORD WINAPI prvSimulatedPeripheralTimer( LPVOID lpParameter )
+{
+TickType_t xMinimumWindowsBlockTime;
+TIMECAPS xTimeCaps;
+
+	/* Set the timer resolution to the maximum possible. */
+	if( timeGetDevCaps( &xTimeCaps, sizeof( xTimeCaps ) ) == MMSYSERR_NOERROR )
+	{
+		xMinimumWindowsBlockTime = ( TickType_t ) xTimeCaps.wPeriodMin;
+		timeBeginPeriod( xTimeCaps.wPeriodMin );
+
+		/* Register an exit handler so the timeBeginPeriod() function can be
+		matched with a timeEndPeriod() when the application exits. */
+		SetConsoleCtrlHandler( prvEndProcess, TRUE );
+	}
+	else
+	{
+		xMinimumWindowsBlockTime = ( TickType_t ) 20;
+	}
+
+	/* Just to prevent compiler warnings. */
+	( void ) lpParameter;
+
+	for( ;; )
+	{
+		/* Wait until the timer expires and we can access the simulated interrupt
+		variables.  *NOTE* this is not a 'real time' way of generating tick
+		events as the next wake time should be relative to the previous wake
+		time, not the time that Sleep() is called.  It is done this way to
+		prevent overruns in this very non real time simulated/emulated
+		environment. */
+		if( portTICK_PERIOD_MS < xMinimumWindowsBlockTime )
+		{
+			Sleep( xMinimumWindowsBlockTime );
+		}
+		else
+		{
+			Sleep( portTICK_PERIOD_MS );
+		}
+
+		configASSERT( xPortRunning );
+
+		WaitForSingleObject( pvInterruptEventMutex, INFINITE );
+
+		/* The timer has expired, generate the simulated tick event. */
+		ulPendingInterrupts |= ( 1 << portINTERRUPT_TICK );
+
+		/* The interrupt is now pending - notify the simulated interrupt
+		handler thread. */
+		if( ulCriticalNesting == 0 )
+		{
+			SetEvent( pvInterruptEvent );
+		}
+
+		/* Give back the mutex so the simulated interrupt handler unblocks
+		and can	access the interrupt handler variables. */
+		ReleaseMutex( pvInterruptEventMutex );
+	}
+
+	#ifdef __GNUC__
+		/* Should never reach here - MingW complains if you leave this line out,
+		MSVC complains if you put it in. */
+		return 0;
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+static BOOL WINAPI prvEndProcess( DWORD dwCtrlType )
+{
+TIMECAPS xTimeCaps;
+
+	( void ) dwCtrlType;
+
+	if( timeGetDevCaps( &xTimeCaps, sizeof( xTimeCaps ) ) == MMSYSERR_NOERROR )
+	{
+		/* Match the call to timeBeginPeriod( xTimeCaps.wPeriodMin ) made when
+		the process started with a timeEndPeriod() as the process exits. */
+		timeEndPeriod( xTimeCaps.wPeriodMin );
+	}
+
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+xThreadState *pxThreadState = NULL;
+int8_t *pcTopOfStack = ( int8_t * ) pxTopOfStack;
+const SIZE_T xStackSize = 1024; /* Set the size to a small number which will get rounded up to the minimum possible. */
+
+	/* In this simulated case a stack is not initialised, but instead a thread
+	is created that will execute the task being created.  The thread handles
+	the context switching itself.  The xThreadState object is placed onto
+	the stack that was created for the task - so the stack buffer is still
+	used, just not in the conventional way.  It will not be used for anything
+	other than holding this structure. */
+	pxThreadState = ( xThreadState * ) ( pcTopOfStack - sizeof( xThreadState ) );
+
+	/* Create the thread itself. */
+	pxThreadState->pvThread = CreateThread( NULL, xStackSize, ( LPTHREAD_START_ROUTINE ) pxCode, pvParameters, CREATE_SUSPENDED | STACK_SIZE_PARAM_IS_A_RESERVATION, NULL );
+	configASSERT( pxThreadState->pvThread ); /* See comment where TerminateThread() is called. */
+	SetThreadAffinityMask( pxThreadState->pvThread, 0x01 );
+	SetThreadPriorityBoost( pxThreadState->pvThread, TRUE );
+	SetThreadPriority( pxThreadState->pvThread, portTASK_THREAD_PRIORITY );
+
+	return ( StackType_t * ) pxThreadState;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+void *pvHandle = NULL;
+int32_t lSuccess;
+xThreadState *pxThreadState = NULL;
+SYSTEM_INFO xSystemInfo;
+
+	/* This port runs windows threads with extremely high priority.  All the
+	threads execute on the same core - to prevent locking up the host only start
+	if the host has multiple cores. */
+	GetSystemInfo( &xSystemInfo );
+	if( xSystemInfo.dwNumberOfProcessors <= 1 )
+	{
+		printf( "This version of the FreeRTOS Windows port can only be used on multi-core hosts.\r\n" );
+		lSuccess = pdFAIL;
+	}
+	else
+	{
+		lSuccess = pdPASS;
+
+		/* The highest priority class is used to [try to] prevent other Windows
+		activity interfering with FreeRTOS timing too much. */
+		if( SetPriorityClass( GetCurrentProcess(), REALTIME_PRIORITY_CLASS ) == 0 )
+		{
+			printf( "SetPriorityClass() failed\r\n" );
+		}
+
+		/* Install the interrupt handlers used by the scheduler itself. */
+		vPortSetInterruptHandler( portINTERRUPT_YIELD, prvProcessYieldInterrupt );
+		vPortSetInterruptHandler( portINTERRUPT_TICK, prvProcessTickInterrupt );
+
+		/* Create the events and mutexes that are used to synchronise all the
+		threads. */
+		pvInterruptEventMutex = CreateMutex( NULL, FALSE, NULL );
+		pvInterruptEvent = CreateEvent( NULL, FALSE, FALSE, NULL );
+
+		if( ( pvInterruptEventMutex == NULL ) || ( pvInterruptEvent == NULL ) )
+		{
+			lSuccess = pdFAIL;
+		}
+
+		/* Set the priority of this thread such that it is above the priority of
+		the threads that run tasks.  This higher priority is required to ensure
+		simulated interrupts take priority over tasks. */
+		pvHandle = GetCurrentThread();
+		if( pvHandle == NULL )
+		{
+			lSuccess = pdFAIL;
+		}
+	}
+
+	if( lSuccess == pdPASS )
+	{
+		if( SetThreadPriority( pvHandle, portSIMULATED_INTERRUPTS_THREAD_PRIORITY ) == 0 )
+		{
+			lSuccess = pdFAIL;
+		}
+		SetThreadPriorityBoost( pvHandle, TRUE );
+		SetThreadAffinityMask( pvHandle, 0x01 );
+	}
+
+	if( lSuccess == pdPASS )
+	{
+		/* Start the thread that simulates the timer peripheral to generate
+		tick interrupts.  The priority is set below that of the simulated
+		interrupt handler so the interrupt event mutex is used for the
+		handshake / overrun protection. */
+		pvHandle = CreateThread( NULL, 0, prvSimulatedPeripheralTimer, NULL, CREATE_SUSPENDED, NULL );
+		if( pvHandle != NULL )
+		{
+			SetThreadPriority( pvHandle, portSIMULATED_TIMER_THREAD_PRIORITY );
+			SetThreadPriorityBoost( pvHandle, TRUE );
+			SetThreadAffinityMask( pvHandle, 0x01 );
+			ResumeThread( pvHandle );
+		}
+
+		/* Start the highest priority task by obtaining its associated thread
+		state structure, in which is stored the thread handle. */
+		pxThreadState = ( xThreadState * ) *( ( size_t * ) pxCurrentTCB );
+		ulCriticalNesting = portNO_CRITICAL_NESTING;
+
+		/* Bump up the priority of the thread that is going to run, in the
+		hope that this will assist in getting the Windows thread scheduler to
+		behave as an embedded engineer might expect. */
+		ResumeThread( pxThreadState->pvThread );
+
+		/* Handle all simulated interrupts - including yield requests and
+		simulated ticks. */
+		prvProcessSimulatedInterrupts();
+	}
+
+	/* Would not expect to return from prvProcessSimulatedInterrupts(), so should
+	not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+static uint32_t prvProcessYieldInterrupt( void )
+{
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+static uint32_t prvProcessTickInterrupt( void )
+{
+uint32_t ulSwitchRequired;
+
+	/* Process the tick itself. */
+	configASSERT( xPortRunning );
+	ulSwitchRequired = ( uint32_t ) xTaskIncrementTick();
+
+	return ulSwitchRequired;
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessSimulatedInterrupts( void )
+{
+uint32_t ulSwitchRequired, i;
+xThreadState *pxThreadState;
+void *pvObjectList[ 2 ];
+CONTEXT xContext;
+
+	/* Going to block on the mutex that ensured exclusive access to the simulated
+	interrupt objects, and the event that signals that a simulated interrupt
+	should be processed. */
+	pvObjectList[ 0 ] = pvInterruptEventMutex;
+	pvObjectList[ 1 ] = pvInterruptEvent;
+
+	/* Create a pending tick to ensure the first task is started as soon as
+	this thread pends. */
+	ulPendingInterrupts |= ( 1 << portINTERRUPT_TICK );
+	SetEvent( pvInterruptEvent );
+
+	xPortRunning = pdTRUE;
+
+	for(;;)
+	{
+		WaitForMultipleObjects( sizeof( pvObjectList ) / sizeof( void * ), pvObjectList, TRUE, INFINITE );
+
+		/* Used to indicate whether the simulated interrupt processing has
+		necessitated a context switch to another task/thread. */
+		ulSwitchRequired = pdFALSE;
+
+		/* For each interrupt we are interested in processing, each of which is
+		represented by a bit in the 32bit ulPendingInterrupts variable. */
+		for( i = 0; i < portMAX_INTERRUPTS; i++ )
+		{
+			/* Is the simulated interrupt pending? */
+			if( ulPendingInterrupts & ( 1UL << i ) )
+			{
+				/* Is a handler installed? */
+				if( ulIsrHandler[ i ] != NULL )
+				{
+					/* Run the actual handler. */
+					if( ulIsrHandler[ i ]() != pdFALSE )
+					{
+						ulSwitchRequired |= ( 1 << i );
+					}
+				}
+
+				/* Clear the interrupt pending bit. */
+				ulPendingInterrupts &= ~( 1UL << i );
+			}
+		}
+
+		if( ulSwitchRequired != pdFALSE )
+		{
+			void *pvOldCurrentTCB;
+
+			pvOldCurrentTCB = pxCurrentTCB;
+
+			/* Select the next task to run. */
+			vTaskSwitchContext();
+
+			/* If the task selected to enter the running state is not the task
+			that is already in the running state. */
+			if( pvOldCurrentTCB != pxCurrentTCB )
+			{
+				/* Suspend the old thread. */
+				pxThreadState = ( xThreadState *) *( ( size_t * ) pvOldCurrentTCB );
+				SuspendThread( pxThreadState->pvThread );
+
+				/* Ensure the thread is actually suspended by performing a
+				synchronous operation that can only complete when the thread is
+				actually suspended.  The below code asks for dummy register
+				data. */
+				xContext.ContextFlags = CONTEXT_INTEGER;
+				( void ) GetThreadContext( pxThreadState->pvThread, &xContext );
+
+				/* Obtain the state of the task now selected to enter the
+				Running state. */
+				pxThreadState = ( xThreadState * ) ( *( size_t *) pxCurrentTCB );
+				ResumeThread( pxThreadState->pvThread );
+			}
+		}
+
+		ReleaseMutex( pvInterruptEventMutex );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortDeleteThread( void *pvTaskToDelete )
+{
+xThreadState *pxThreadState;
+uint32_t ulErrorCode;
+
+	/* Remove compiler warnings if configASSERT() is not defined. */
+	( void ) ulErrorCode;
+
+	/* Find the handle of the thread being deleted. */
+	pxThreadState = ( xThreadState * ) ( *( size_t *) pvTaskToDelete );
+
+	/* Check that the thread is still valid, it might have been closed by
+	vPortCloseRunningThread() - which will be the case if the task associated
+	with the thread originally deleted itself rather than being deleted by a
+	different task. */
+	if( pxThreadState->pvThread != NULL )
+	{
+		WaitForSingleObject( pvInterruptEventMutex, INFINITE );
+
+		/* !!! This is not a nice way to terminate a thread, and will eventually
+		result in resources being depleted if tasks frequently delete other
+		tasks (rather than deleting themselves) as the task stacks will not be
+		freed. */
+		ulErrorCode = TerminateThread( pxThreadState->pvThread, 0 );
+		configASSERT( ulErrorCode );
+
+		ulErrorCode = CloseHandle( pxThreadState->pvThread );
+		configASSERT( ulErrorCode );
+
+		ReleaseMutex( pvInterruptEventMutex );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortCloseRunningThread( void *pvTaskToDelete, volatile BaseType_t *pxPendYield )
+{
+xThreadState *pxThreadState;
+void *pvThread;
+uint32_t ulErrorCode;
+
+	/* Remove compiler warnings if configASSERT() is not defined. */
+	( void ) ulErrorCode;
+
+	/* Find the handle of the thread being deleted. */
+	pxThreadState = ( xThreadState * ) ( *( size_t *) pvTaskToDelete );
+	pvThread = pxThreadState->pvThread;
+
+	/* Raise the Windows priority of the thread to ensure the FreeRTOS scheduler
+	does not run and swap it out before it is closed.  If that were to happen
+	the thread would never run again and effectively be a thread handle and
+	memory leak. */
+	SetThreadPriority( pvThread, portDELETE_SELF_THREAD_PRIORITY );
+
+	/* This function will not return, therefore a yield is set as pending to
+	ensure a context switch occurs away from this thread on the next tick. */
+	*pxPendYield = pdTRUE;
+
+	/* Mark the thread associated with this task as invalid so
+	vPortDeleteThread() does not try to terminate it. */
+	pxThreadState->pvThread = NULL;
+
+	/* Close the thread. */
+	ulErrorCode = CloseHandle( pvThread );
+	configASSERT( ulErrorCode );
+
+	/* This is called from a critical section, which must be exited before the
+	thread stops. */
+	taskEXIT_CRITICAL();
+
+	ExitThread( 0 );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	exit( 0 );
+}
+/*-----------------------------------------------------------*/
+
+void vPortGenerateSimulatedInterrupt( uint32_t ulInterruptNumber )
+{
+	configASSERT( xPortRunning );
+
+	if( ( ulInterruptNumber < portMAX_INTERRUPTS ) && ( pvInterruptEventMutex != NULL ) )
+	{
+		/* Yield interrupts are processed even when critical nesting is
+		non-zero. */
+		WaitForSingleObject( pvInterruptEventMutex, INFINITE );
+		ulPendingInterrupts |= ( 1 << ulInterruptNumber );
+
+		/* The simulated interrupt is now held pending, but don't actually
+		process it yet if this call is within a critical section.  It is
+		possible for this to be in a critical section as calls to wait for
+		mutexes are accumulative. */
+		if( ulCriticalNesting == 0 )
+		{
+			SetEvent( pvInterruptEvent );
+		}
+
+		ReleaseMutex( pvInterruptEventMutex );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetInterruptHandler( uint32_t ulInterruptNumber, uint32_t (*pvHandler)( void ) )
+{
+	if( ulInterruptNumber < portMAX_INTERRUPTS )
+	{
+		if( pvInterruptEventMutex != NULL )
+		{
+			WaitForSingleObject( pvInterruptEventMutex, INFINITE );
+			ulIsrHandler[ ulInterruptNumber ] = pvHandler;
+			ReleaseMutex( pvInterruptEventMutex );
+		}
+		else
+		{
+			ulIsrHandler[ ulInterruptNumber ] = pvHandler;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	if( xPortRunning == pdTRUE )
+	{
+		/* The interrupt event mutex is held for the entire critical section,
+		effectively disabling (simulated) interrupts. */
+		WaitForSingleObject( pvInterruptEventMutex, INFINITE );
+		ulCriticalNesting++;
+	}
+	else
+	{
+		ulCriticalNesting++;
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+int32_t lMutexNeedsReleasing;
+
+	/* The interrupt event mutex should already be held by this thread as it was
+	obtained on entry to the critical section. */
+
+	lMutexNeedsReleasing = pdTRUE;
+
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		if( ulCriticalNesting == ( portNO_CRITICAL_NESTING + 1 ) )
+		{
+			ulCriticalNesting--;
+
+			/* Were any interrupts set to pending while interrupts were
+			(simulated) disabled? */
+			if( ulPendingInterrupts != 0UL )
+			{
+				configASSERT( xPortRunning );
+				SetEvent( pvInterruptEvent );
+
+				/* Mutex will be released now, so does not require releasing
+				on function exit. */
+				lMutexNeedsReleasing = pdFALSE;
+				ReleaseMutex( pvInterruptEventMutex );
+			}
+		}
+		else
+		{
+			/* Tick interrupts will still not be processed as the critical
+			nesting depth will not be zero. */
+			ulCriticalNesting--;
+		}
+	}
+
+	if( pvInterruptEventMutex != NULL )
+	{
+		if( lMutexNeedsReleasing == pdTRUE )
+		{
+			configASSERT( xPortRunning );
+			ReleaseMutex( pvInterruptEventMutex );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MSVC-MingW/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MSVC-MingW/portmacro.h
new file mode 100644
index 0000000..5f54128
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MSVC-MingW/portmacro.h
@@ -0,0 +1,157 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include 
+#include 
+
+/******************************************************************************
+	Defines
+******************************************************************************/
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	size_t
+#define portBASE_TYPE	long
+#define portPOINTER_SIZE_TYPE size_t
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32/64-bit tick type on a 32/64-bit architecture, so reads of the tick
+	count do not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portINLINE __inline
+
+#if defined( __x86_64__) || defined( _M_X64 )
+	#define portBYTE_ALIGNMENT		8
+#else
+	#define portBYTE_ALIGNMENT		4
+#endif
+
+#define portYIELD()					vPortGenerateSimulatedInterrupt( portINTERRUPT_YIELD )
+
+/* Simulated interrupts return pdFALSE if no context switch should be performed,
+or a non-zero number if a context switch should be performed. */
+#define portYIELD_FROM_ISR( x ) ( void ) x
+#define portEND_SWITCHING_ISR( x ) portYIELD_FROM_ISR( ( x ) )
+
+void vPortCloseRunningThread( void *pvTaskToDelete, volatile BaseType_t *pxPendYield );
+void vPortDeleteThread( void *pvThreadToDelete );
+#define portCLEAN_UP_TCB( pxTCB )	vPortDeleteThread( pxTCB )
+#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxPendYield ) vPortCloseRunningThread( ( pvTaskToDelete ), ( pxPendYield ) )
+#define portDISABLE_INTERRUPTS() vPortEnterCritical()
+#define portENABLE_INTERRUPTS() vPortExitCritical()
+
+/* Critical section handling. */
+void vPortEnterCritical( void );
+void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+
+	/*-----------------------------------------------------------*/
+
+	#ifdef __GNUC__
+		#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )	\
+			__asm volatile(	"bsr %1, %0\n\t" 									\
+							:"=r"(uxTopPriority) : "rm"(uxReadyPriorities) : "cc" )
+	#else
+		/* BitScanReverse returns the bit position of the most significant '1'
+		in the word. */
+		#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) _BitScanReverse( ( DWORD * ) &( uxTopPriority ), ( uxReadyPriorities ) )
+	#endif /* __GNUC__ */
+
+#endif /* taskRECORD_READY_PRIORITY */
+
+#ifndef __GNUC__
+	__pragma( warning( disable:4211 ) ) /* Nonstandard extension used, as extern is only nonstandard to MSVC. */
+#endif
+
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+
+#define portINTERRUPT_YIELD				( 0UL )
+#define portINTERRUPT_TICK				( 1UL )
+
+/*
+ * Raise a simulated interrupt represented by the bit mask in ulInterruptMask.
+ * Each bit can be used to represent an individual interrupt - with the first
+ * two bits being used for the Yield and Tick interrupts respectively.
+*/
+void vPortGenerateSimulatedInterrupt( uint32_t ulInterruptNumber );
+
+/*
+ * Install an interrupt handler to be called by the simulated interrupt handler
+ * thread.  The interrupt number must be above any used by the kernel itself
+ * (at the time of writing the kernel was using interrupt numbers 0, 1, and 2
+ * as defined above).  The number must also be lower than 32.
+ *
+ * Interrupt handler functions must return a non-zero value if executing the
+ * handler resulted in a task switch being required.
+ */
+void vPortSetInterruptHandler( uint32_t ulInterruptNumber, uint32_t (*pvHandler)( void ) );
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MemMang/ReadMe.url b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MemMang/ReadMe.url
new file mode 100644
index 0000000..b04bfe3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MemMang/ReadMe.url
@@ -0,0 +1,5 @@
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,2
+[InternetShortcut]
+URL=http://www.freertos.org/a00111.html
+IDList=
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MemMang/heap_1.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MemMang/heap_1.c
new file mode 100644
index 0000000..137733a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MemMang/heap_1.c
@@ -0,0 +1,146 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*
+ * The simplest possible implementation of pvPortMalloc().  Note that this
+ * implementation does NOT allow allocated memory to be freed again.
+ *
+ * See heap_2.c, heap_3.c and heap_4.c for alternative implementations, and the
+ * memory management pages of http://www.FreeRTOS.org for more information.
+ */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+/* A few bytes might be lost to byte aligning the heap start address. */
+#define configADJUSTED_HEAP_SIZE	( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+	/* The application writer has already defined the array used for the RTOS
+	heap - probably so it can be placed in a special segment or address. */
+	extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#else
+	static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/* Index into the ucHeap array. */
+static size_t xNextFreeByte = ( size_t ) 0;
+
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+void *pvReturn = NULL;
+static uint8_t *pucAlignedHeap = NULL;
+
+	/* Ensure that blocks are always aligned to the required number of bytes. */
+	#if( portBYTE_ALIGNMENT != 1 )
+	{
+		if( xWantedSize & portBYTE_ALIGNMENT_MASK )
+		{
+			/* Byte alignment required. */
+			xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+		}
+	}
+	#endif
+
+	vTaskSuspendAll();
+	{
+		if( pucAlignedHeap == NULL )
+		{
+			/* Ensure the heap starts on a correctly aligned boundary. */
+			pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) &ucHeap[ portBYTE_ALIGNMENT ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
+		}
+
+		/* Check there is enough room left for the allocation. */
+		if( ( ( xNextFreeByte + xWantedSize ) < configADJUSTED_HEAP_SIZE ) &&
+			( ( xNextFreeByte + xWantedSize ) > xNextFreeByte )	)/* Check for overflow. */
+		{
+			/* Return the next free byte then increment the index past this
+			block. */
+			pvReturn = pucAlignedHeap + xNextFreeByte;
+			xNextFreeByte += xWantedSize;
+		}
+
+		traceMALLOC( pvReturn, xWantedSize );
+	}
+	( void ) xTaskResumeAll();
+
+	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+	}
+	#endif
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+	/* Memory cannot be freed using this scheme.  See heap_2.c, heap_3.c and
+	heap_4.c for alternative implementations, and the memory management pages of
+	http://www.FreeRTOS.org for more information. */
+	( void ) pv;
+
+	/* Force an assert as it is invalid to call this function. */
+	configASSERT( pv == NULL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* Only required when static memory is not cleared. */
+	xNextFreeByte = ( size_t ) 0;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return ( configADJUSTED_HEAP_SIZE - xNextFreeByte );
+}
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MemMang/heap_2.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MemMang/heap_2.c
new file mode 100644
index 0000000..2c5ceb8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MemMang/heap_2.c
@@ -0,0 +1,272 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * A sample implementation of pvPortMalloc() and vPortFree() that permits
+ * allocated blocks to be freed, but does not combine adjacent free blocks
+ * into a single larger block (and so will fragment memory).  See heap_4.c for
+ * an equivalent that does combine adjacent blocks into single larger blocks.
+ *
+ * See heap_1.c, heap_3.c and heap_4.c for alternative implementations, and the
+ * memory management pages of http://www.FreeRTOS.org for more information.
+ */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+/* A few bytes might be lost to byte aligning the heap start address. */
+#define configADJUSTED_HEAP_SIZE	( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
+
+/*
+ * Initialises the heap structures before their first use.
+ */
+static void prvHeapInit( void );
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+	/* The application writer has already defined the array used for the RTOS
+	heap - probably so it can be placed in a special segment or address. */
+	extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#else
+	static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+
+/* Define the linked list structure.  This is used to link free blocks in order
+of their size. */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/*<< The next free block in the list. */
+	size_t xBlockSize;						/*<< The size of the free block. */
+} BlockLink_t;
+
+
+static const uint16_t heapSTRUCT_SIZE	= ( ( sizeof ( BlockLink_t ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~portBYTE_ALIGNMENT_MASK );
+#define heapMINIMUM_BLOCK_SIZE	( ( size_t ) ( heapSTRUCT_SIZE * 2 ) )
+
+/* Create a couple of list links to mark the start and end of the list. */
+static BlockLink_t xStart, xEnd;
+
+/* Keeps track of the number of free bytes remaining, but says nothing about
+fragmentation. */
+static size_t xFreeBytesRemaining = configADJUSTED_HEAP_SIZE;
+
+/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */
+
+/*
+ * Insert a block into the list of free blocks - which is ordered by size of
+ * the block.  Small blocks at the start of the list and large blocks at the end
+ * of the list.
+ */
+#define prvInsertBlockIntoFreeList( pxBlockToInsert )								\
+{																					\
+BlockLink_t *pxIterator;															\
+size_t xBlockSize;																	\
+																					\
+	xBlockSize = pxBlockToInsert->xBlockSize;										\
+																					\
+	/* Iterate through the list until a block is found that has a larger size */	\
+	/* than the block we are inserting. */											\
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock )	\
+	{																				\
+		/* There is nothing to do here - just iterate to the correct position. */	\
+	}																				\
+																					\
+	/* Update the list to include the block being inserted in the correct */		\
+	/* position. */																	\
+	pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;					\
+	pxIterator->pxNextFreeBlock = pxBlockToInsert;									\
+}
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+static BaseType_t xHeapHasBeenInitialised = pdFALSE;
+void *pvReturn = NULL;
+
+	vTaskSuspendAll();
+	{
+		/* If this is the first call to malloc then the heap will require
+		initialisation to setup the list of free blocks. */
+		if( xHeapHasBeenInitialised == pdFALSE )
+		{
+			prvHeapInit();
+			xHeapHasBeenInitialised = pdTRUE;
+		}
+
+		/* The wanted size is increased so it can contain a BlockLink_t
+		structure in addition to the requested amount of bytes. */
+		if( xWantedSize > 0 )
+		{
+			xWantedSize += heapSTRUCT_SIZE;
+
+			/* Ensure that blocks are always aligned to the required number of bytes. */
+			if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0 )
+			{
+				/* Byte alignment required. */
+				xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+			}
+		}
+
+		if( ( xWantedSize > 0 ) && ( xWantedSize < configADJUSTED_HEAP_SIZE ) )
+		{
+			/* Blocks are stored in byte order - traverse the list from the start
+			(smallest) block until one of adequate size is found. */
+			pxPreviousBlock = &xStart;
+			pxBlock = xStart.pxNextFreeBlock;
+			while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+			{
+				pxPreviousBlock = pxBlock;
+				pxBlock = pxBlock->pxNextFreeBlock;
+			}
+
+			/* If we found the end marker then a block of adequate size was not found. */
+			if( pxBlock != &xEnd )
+			{
+				/* Return the memory space - jumping over the BlockLink_t structure
+				at its start. */
+				pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE );
+
+				/* This block is being returned for use so must be taken out of the
+				list of free blocks. */
+				pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+				/* If the block is larger than required it can be split into two. */
+				if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+				{
+					/* This block is to be split into two.  Create a new block
+					following the number of bytes requested. The void cast is
+					used to prevent byte alignment warnings from the compiler. */
+					pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+
+					/* Calculate the sizes of two blocks split from the single
+					block. */
+					pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+					pxBlock->xBlockSize = xWantedSize;
+
+					/* Insert the new block into the list of free blocks. */
+					prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
+				}
+
+				xFreeBytesRemaining -= pxBlock->xBlockSize;
+			}
+		}
+
+		traceMALLOC( pvReturn, xWantedSize );
+	}
+	( void ) xTaskResumeAll();
+
+	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+	}
+	#endif
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		before it. */
+		puc -= heapSTRUCT_SIZE;
+
+		/* This unexpected casting is to keep some compilers from issuing
+		byte alignment warnings. */
+		pxLink = ( void * ) puc;
+
+		vTaskSuspendAll();
+		{
+			/* Add this block to the list of free blocks. */
+			prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+			xFreeBytesRemaining += pxLink->xBlockSize;
+			traceFREE( pv, pxLink->xBlockSize );
+		}
+		( void ) xTaskResumeAll();
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) &ucHeap[ portBYTE_ALIGNMENT ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+	xStart.xBlockSize = ( size_t ) 0;
+
+	/* xEnd is used to mark the end of the list of free blocks. */
+	xEnd.xBlockSize = configADJUSTED_HEAP_SIZE;
+	xEnd.pxNextFreeBlock = NULL;
+
+	/* To start with there is a single free block that is sized to take up the
+	entire heap space. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+	pxFirstFreeBlock->xBlockSize = configADJUSTED_HEAP_SIZE;
+	pxFirstFreeBlock->pxNextFreeBlock = &xEnd;
+}
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MemMang/heap_3.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MemMang/heap_3.c
new file mode 100644
index 0000000..c391d46
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MemMang/heap_3.c
@@ -0,0 +1,97 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*
+ * Implementation of pvPortMalloc() and vPortFree() that relies on the
+ * compilers own malloc() and free() implementations.
+ *
+ * This file can only be used if the linker is configured to to generate
+ * a heap memory area.
+ *
+ * See heap_1.c, heap_2.c and heap_4.c for alternative implementations, and the
+ * memory management pages of http://www.FreeRTOS.org for more information.
+ */
+
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+void *pvReturn;
+
+	vTaskSuspendAll();
+	{
+		pvReturn = malloc( xWantedSize );
+		traceMALLOC( pvReturn, xWantedSize );
+	}
+	( void ) xTaskResumeAll();
+
+	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+	}
+	#endif
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+	if( pv )
+	{
+		vTaskSuspendAll();
+		{
+			free( pv );
+			traceFREE( pv, 0 );
+		}
+		( void ) xTaskResumeAll();
+	}
+}
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MemMang/heap_4.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MemMang/heap_4.c
new file mode 100644
index 0000000..23714eb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MemMang/heap_4.c
@@ -0,0 +1,436 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * A sample implementation of pvPortMalloc() and vPortFree() that combines
+ * (coalescences) adjacent memory blocks as they are freed, and in so doing
+ * limits memory fragmentation.
+ *
+ * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the
+ * memory management pages of http://www.FreeRTOS.org for more information.
+ */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+/* Block sizes must not get too small. */
+#define heapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define heapBITS_PER_BYTE		( ( size_t ) 8 )
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+	/* The application writer has already defined the array used for the RTOS
+	heap - probably so it can be placed in a special segment or address. */
+	extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#else
+	static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/* Define the linked list structure.  This is used to link free blocks in order
+of their memory address. */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/*<< The next free block in the list. */
+	size_t xBlockSize;						/*<< The size of the free block. */
+} BlockLink_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Inserts a block of memory that is being freed into the correct position in
+ * the list of free memory blocks.  The block being freed will be merged with
+ * the block in front it and/or the block behind it if the memory blocks are
+ * adjacent to each other.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+
+/*
+ * Called automatically to setup the required heap structures the first time
+ * pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/*-----------------------------------------------------------*/
+
+/* The size of the structure placed at the beginning of each allocated memory
+block must by correctly byte aligned. */
+static const size_t xHeapStructSize	= ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+
+/* Create a couple of list links to mark the start and end of the list. */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/* Keeps track of the number of free bytes remaining, but says nothing about
+fragmentation. */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize
+member of an BlockLink_t structure is set then the block belongs to the
+application.  When the bit is free the block is still part of the free heap
+space. */
+static size_t xBlockAllocatedBit = 0;
+
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+	vTaskSuspendAll();
+	{
+		/* If this is the first call to malloc then the heap will require
+		initialisation to setup the list of free blocks. */
+		if( pxEnd == NULL )
+		{
+			prvHeapInit();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Check the requested block size is not so large that the top bit is
+		set.  The top bit of the block size member of the BlockLink_t structure
+		is used to determine who owns the block - the application or the
+		kernel, so it must be free. */
+		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+		{
+			/* The wanted size is increased so it can contain a BlockLink_t
+			structure in addition to the requested amount of bytes. */
+			if( xWantedSize > 0 )
+			{
+				xWantedSize += xHeapStructSize;
+
+				/* Ensure that blocks are always aligned to the required number
+				of bytes. */
+				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+				{
+					/* Byte alignment required. */
+					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+					configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+			{
+				/* Traverse the list from the start	(lowest address) block until
+				one	of adequate size is found. */
+				pxPreviousBlock = &xStart;
+				pxBlock = xStart.pxNextFreeBlock;
+				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+				{
+					pxPreviousBlock = pxBlock;
+					pxBlock = pxBlock->pxNextFreeBlock;
+				}
+
+				/* If the end marker was reached then a block of adequate size
+				was	not found. */
+				if( pxBlock != pxEnd )
+				{
+					/* Return the memory space pointed to - jumping over the
+					BlockLink_t structure at its start. */
+					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+					/* This block is being returned for use so must be taken out
+					of the list of free blocks. */
+					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+					/* If the block is larger than required it can be split into
+					two. */
+					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+					{
+						/* This block is to be split into two.  Create a new
+						block following the number of bytes requested. The void
+						cast is used to prevent byte alignment warnings from the
+						compiler. */
+						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+						configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
+
+						/* Calculate the sizes of two blocks split from the
+						single block. */
+						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+						pxBlock->xBlockSize = xWantedSize;
+
+						/* Insert the new block into the list of free blocks. */
+						prvInsertBlockIntoFreeList( pxNewBlockLink );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+					{
+						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The block is being returned - it is allocated and owned
+					by the application and has no "next" block. */
+					pxBlock->xBlockSize |= xBlockAllocatedBit;
+					pxBlock->pxNextFreeBlock = NULL;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		traceMALLOC( pvReturn, xWantedSize );
+	}
+	( void ) xTaskResumeAll();
+
+	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		before it. */
+		puc -= xHeapStructSize;
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+
+		/* Check the block is actually allocated. */
+		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+		configASSERT( pxLink->pxNextFreeBlock == NULL );
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+			{
+				/* The block is being returned to the heap - it is no longer
+				allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+				vTaskSuspendAll();
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+	return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	uxAddress = ( size_t ) ucHeap;
+
+	if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
+	{
+		uxAddress += ( portBYTE_ALIGNMENT - 1 );
+		uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+	}
+
+	pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+	xStart.xBlockSize = ( size_t ) 0;
+
+	/* pxEnd is used to mark the end of the list of free blocks and is inserted
+	at the end of the heap space. */
+	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+	uxAddress -= xHeapStructSize;
+	uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+	pxEnd = ( void * ) uxAddress;
+	pxEnd->xBlockSize = 0;
+	pxEnd->pxNextFreeBlock = NULL;
+
+	/* To start with there is a single free block that is sized to take up the
+	entire heap space, minus the space taken by pxEnd. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+	/* Only one block exists - and it covers the entire usable heap space. */
+	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+	{
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+		pxBlockToInsert = pxIterator;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+	}
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	before and the block after, then it's pxNextFreeBlock pointer will have
+	already been set, and should not be set here as that would make it point
+	to itself. */
+	if( pxIterator != pxBlockToInsert )
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MemMang/heap_5.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MemMang/heap_5.c
new file mode 100644
index 0000000..8e50762
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MemMang/heap_5.c
@@ -0,0 +1,485 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * A sample implementation of pvPortMalloc() that allows the heap to be defined
+ * across multiple non-contigous blocks and combines (coalescences) adjacent
+ * memory blocks as they are freed.
+ *
+ * See heap_1.c, heap_2.c, heap_3.c and heap_4.c for alternative
+ * implementations, and the memory management pages of http://www.FreeRTOS.org
+ * for more information.
+ *
+ * Usage notes:
+ *
+ * vPortDefineHeapRegions() ***must*** be called before pvPortMalloc().
+ * pvPortMalloc() will be called if any task objects (tasks, queues, event
+ * groups, etc.) are created, therefore vPortDefineHeapRegions() ***must*** be
+ * called before any other objects are defined.
+ *
+ * vPortDefineHeapRegions() takes a single parameter.  The parameter is an array
+ * of HeapRegion_t structures.  HeapRegion_t is defined in portable.h as
+ *
+ * typedef struct HeapRegion
+ * {
+ *	uint8_t *pucStartAddress; << Start address of a block of memory that will be part of the heap.
+ *	size_t xSizeInBytes;	  << Size of the block of memory.
+ * } HeapRegion_t;
+ *
+ * The array is terminated using a NULL zero sized region definition, and the
+ * memory regions defined in the array ***must*** appear in address order from
+ * low address to high address.  So the following is a valid example of how
+ * to use the function.
+ *
+ * HeapRegion_t xHeapRegions[] =
+ * {
+ * 	{ ( uint8_t * ) 0x80000000UL, 0x10000 }, << Defines a block of 0x10000 bytes starting at address 0x80000000
+ * 	{ ( uint8_t * ) 0x90000000UL, 0xa0000 }, << Defines a block of 0xa0000 bytes starting at address of 0x90000000
+ * 	{ NULL, 0 }                << Terminates the array.
+ * };
+ *
+ * vPortDefineHeapRegions( xHeapRegions ); << Pass the array into vPortDefineHeapRegions().
+ *
+ * Note 0x80000000 is the lower address so appears in the array first.
+ *
+ */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+/* Block sizes must not get too small. */
+#define heapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define heapBITS_PER_BYTE		( ( size_t ) 8 )
+
+/* Define the linked list structure.  This is used to link free blocks in order
+of their memory address. */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/*<< The next free block in the list. */
+	size_t xBlockSize;						/*<< The size of the free block. */
+} BlockLink_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Inserts a block of memory that is being freed into the correct position in
+ * the list of free memory blocks.  The block being freed will be merged with
+ * the block in front it and/or the block behind it if the memory blocks are
+ * adjacent to each other.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+
+/*-----------------------------------------------------------*/
+
+/* The size of the structure placed at the beginning of each allocated memory
+block must by correctly byte aligned. */
+static const size_t xHeapStructSize	= ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+
+/* Create a couple of list links to mark the start and end of the list. */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/* Keeps track of the number of free bytes remaining, but says nothing about
+fragmentation. */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize
+member of an BlockLink_t structure is set then the block belongs to the
+application.  When the bit is free the block is still part of the free heap
+space. */
+static size_t xBlockAllocatedBit = 0;
+
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+	/* The heap must be initialised before the first call to
+	prvPortMalloc(). */
+	configASSERT( pxEnd );
+
+	vTaskSuspendAll();
+	{
+		/* Check the requested block size is not so large that the top bit is
+		set.  The top bit of the block size member of the BlockLink_t structure
+		is used to determine who owns the block - the application or the
+		kernel, so it must be free. */
+		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+		{
+			/* The wanted size is increased so it can contain a BlockLink_t
+			structure in addition to the requested amount of bytes. */
+			if( xWantedSize > 0 )
+			{
+				xWantedSize += xHeapStructSize;
+
+				/* Ensure that blocks are always aligned to the required number
+				of bytes. */
+				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+				{
+					/* Byte alignment required. */
+					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+			{
+				/* Traverse the list from the start	(lowest address) block until
+				one	of adequate size is found. */
+				pxPreviousBlock = &xStart;
+				pxBlock = xStart.pxNextFreeBlock;
+				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+				{
+					pxPreviousBlock = pxBlock;
+					pxBlock = pxBlock->pxNextFreeBlock;
+				}
+
+				/* If the end marker was reached then a block of adequate size
+				was	not found. */
+				if( pxBlock != pxEnd )
+				{
+					/* Return the memory space pointed to - jumping over the
+					BlockLink_t structure at its start. */
+					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+					/* This block is being returned for use so must be taken out
+					of the list of free blocks. */
+					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+					/* If the block is larger than required it can be split into
+					two. */
+					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+					{
+						/* This block is to be split into two.  Create a new
+						block following the number of bytes requested. The void
+						cast is used to prevent byte alignment warnings from the
+						compiler. */
+						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+
+						/* Calculate the sizes of two blocks split from the
+						single block. */
+						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+						pxBlock->xBlockSize = xWantedSize;
+
+						/* Insert the new block into the list of free blocks. */
+						prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+					{
+						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The block is being returned - it is allocated and owned
+					by the application and has no "next" block. */
+					pxBlock->xBlockSize |= xBlockAllocatedBit;
+					pxBlock->pxNextFreeBlock = NULL;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		traceMALLOC( pvReturn, xWantedSize );
+	}
+	( void ) xTaskResumeAll();
+
+	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		before it. */
+		puc -= xHeapStructSize;
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+
+		/* Check the block is actually allocated. */
+		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+		configASSERT( pxLink->pxNextFreeBlock == NULL );
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+			{
+				/* The block is being returned to the heap - it is no longer
+				allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+				vTaskSuspendAll();
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+	return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+	{
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+		pxBlockToInsert = pxIterator;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+	}
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	before and the block after, then it's pxNextFreeBlock pointer will have
+	already been set, and should not be set here as that would make it point
+	to itself. */
+	if( pxIterator != pxBlockToInsert )
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions )
+{
+BlockLink_t *pxFirstFreeBlockInRegion = NULL, *pxPreviousFreeBlock;
+size_t xAlignedHeap;
+size_t xTotalRegionSize, xTotalHeapSize = 0;
+BaseType_t xDefinedRegions = 0;
+size_t xAddress;
+const HeapRegion_t *pxHeapRegion;
+
+	/* Can only call once! */
+	configASSERT( pxEnd == NULL );
+
+	pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );
+
+	while( pxHeapRegion->xSizeInBytes > 0 )
+	{
+		xTotalRegionSize = pxHeapRegion->xSizeInBytes;
+
+		/* Ensure the heap region starts on a correctly aligned boundary. */
+		xAddress = ( size_t ) pxHeapRegion->pucStartAddress;
+		if( ( xAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
+		{
+			xAddress += ( portBYTE_ALIGNMENT - 1 );
+			xAddress &= ~portBYTE_ALIGNMENT_MASK;
+
+			/* Adjust the size for the bytes lost to alignment. */
+			xTotalRegionSize -= xAddress - ( size_t ) pxHeapRegion->pucStartAddress;
+		}
+
+		xAlignedHeap = xAddress;
+
+		/* Set xStart if it has not already been set. */
+		if( xDefinedRegions == 0 )
+		{
+			/* xStart is used to hold a pointer to the first item in the list of
+			free blocks.  The void cast is used to prevent compiler warnings. */
+			xStart.pxNextFreeBlock = ( BlockLink_t * ) xAlignedHeap;
+			xStart.xBlockSize = ( size_t ) 0;
+		}
+		else
+		{
+			/* Should only get here if one region has already been added to the
+			heap. */
+			configASSERT( pxEnd != NULL );
+
+			/* Check blocks are passed in with increasing start addresses. */
+			configASSERT( xAddress > ( size_t ) pxEnd );
+		}
+
+		/* Remember the location of the end marker in the previous region, if
+		any. */
+		pxPreviousFreeBlock = pxEnd;
+
+		/* pxEnd is used to mark the end of the list of free blocks and is
+		inserted at the end of the region space. */
+		xAddress = xAlignedHeap + xTotalRegionSize;
+		xAddress -= xHeapStructSize;
+		xAddress &= ~portBYTE_ALIGNMENT_MASK;
+		pxEnd = ( BlockLink_t * ) xAddress;
+		pxEnd->xBlockSize = 0;
+		pxEnd->pxNextFreeBlock = NULL;
+
+		/* To start with there is a single free block in this region that is
+		sized to take up the entire heap region minus the space taken by the
+		free block structure. */
+		pxFirstFreeBlockInRegion = ( BlockLink_t * ) xAlignedHeap;
+		pxFirstFreeBlockInRegion->xBlockSize = xAddress - ( size_t ) pxFirstFreeBlockInRegion;
+		pxFirstFreeBlockInRegion->pxNextFreeBlock = pxEnd;
+
+		/* If this is not the first region that makes up the entire heap space
+		then link the previous region to this region. */
+		if( pxPreviousFreeBlock != NULL )
+		{
+			pxPreviousFreeBlock->pxNextFreeBlock = pxFirstFreeBlockInRegion;
+		}
+
+		xTotalHeapSize += pxFirstFreeBlockInRegion->xBlockSize;
+
+		/* Move onto the next HeapRegion_t structure. */
+		xDefinedRegions++;
+		pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );
+	}
+
+	xMinimumEverFreeBytesRemaining = xTotalHeapSize;
+	xFreeBytesRemaining = xTotalHeapSize;
+
+	/* Check something was actually defined before it is accessed. */
+	configASSERT( xTotalHeapSize );
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MikroC/ARM_CM4F/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MikroC/ARM_CM4F/port.c
new file mode 100644
index 0000000..8b38a72
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MikroC/ARM_CM4F/port.c
@@ -0,0 +1,788 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM4F port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT			 ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16	 ( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK					( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS			( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR					( 0x01000000 )
+#define portINITIAL_EXC_RETURN				( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR			( 45UL )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/* Cannot find a weak linkage attribute, so the
+configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if the
+application writer wants to provide their own implementation of
+vPortSetupTimerInterrupt().  Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION
+is defined. */
+#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
+		#define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
+#endif
+
+/* Manual definition of missing asm names. */
+#define psp 	9
+#define basepri	17
+#define msp		8
+#define ipsr	5
+#define control	20
+
+/* From port.c. */
+extern void *pxCurrentTCB;
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void );
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask( void );
+
+/*
+ * Function to enable the VFP.
+ */
+ static void vPortEnableVFP( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+
+	/* Offset added to account for the way the MCU uses the stack on entry/exit
+	of interrupts, and to ensure alignment. */
+	pxTopOfStack--;
+
+	/* Sometimes the parameters are loaded from the stack. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;
+	pxTopOfStack--;
+
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+
+	/* Save code space by skipping register initialisation. */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+
+	/* A save method is being used that requires each task to maintain its
+	own exec return value. */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void ) iv IVT_INT_SVCall ics ICS_OFF
+{
+	__asm {
+			ldr r3, =_pxCurrentTCB  /* Restore the context. */
+			ldr r1, [r3]			/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+			ldr r0, [r1]			/* The first item in pxCurrentTCB is the task top of stack. */
+			ldm r0!, (r4-r11, r14)/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+			msr psp, r0				/* Restore the task stack pointer. */
+			isb
+			mov r0, #0
+			msr basepri, r0
+			bx r14
+	};
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortStartFirstTask( void )
+{
+	__asm {
+				ldr r0, =0xE000ED08	 /* Use the NVIC offset register to locate the stack. */
+				ldr r0, [r0]
+				ldr r0, [r0]
+				msr msp, r0			 /* Set the msp back to the start of the stack. */
+				/* Clear the bit that indicates the FPU is in use in case the FPU was used
+				before the scheduler was started - which would otherwise result in the
+				unnecessary leaving of space in the SVC stack for lazy saving of FPU
+				registers. */
+				mov r0, #0
+				msr control, r0
+				cpsie i				 /* Globally enable interrupts. */
+				cpsie f
+				dsb
+				isb
+				svc #0					/* System call to start first task. */
+				nop
+			};
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* The kernel interrupt priority should be set to the lowest
+		priority. */
+		configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Ensure the VFP is enabled - it should be anyway. */
+	vPortEnableVFP();
+
+	/* Lazy save always. */
+	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+	/* Start the first task. */
+	prvPortStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing!  Call the task
+	exit error function to prevent compiler warnings about a static function
+	not being called in the case that the application writer overrides this
+	functionality by defining configTASK_RETURN_ADDRESS. */
+	prvTaskExitError();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+const uint8_t ucMaxSyscallInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+void xPortPendSVHandler( void ) iv IVT_INT_PendSV ics ICS_OFF
+{
+	__asm {
+#ifdef HW_DEBUG
+				/* The function is not truly naked, so add back the 4 bytes subtracted
+				from the stack pointer by the function prologue. */
+		add sp, sp, #4
+#endif
+	mrs r0, psp
+	isb
+
+	ldr	r3, =_pxCurrentTCB		 /* Get the location of the current TCB. */
+	ldr	r2, [r3]
+
+	tst r14, #0x10			 /* Is the task using the FPU context?  If so, push high vfp registers. */
+	it eq
+	vstmdbeq r0!, (s16-s31)
+
+	stmdb r0!, (r4-r11, r14)		 /* Save the core registers. */
+
+	str r0, [r2]			 /* Save the new top of stack into the first member of the TCB. */
+
+	stmdb sp!, (r0, r3)
+	ldr r0, =_ucMaxSyscallInterruptPriority
+	ldr r1, [r0]
+	msr basepri, r1
+	dsb
+	isb
+	bl _vTaskSwitchContext
+	mov r0, #0
+	msr basepri, r0
+	ldm sp!, (r0, r3)
+
+	ldr r1, [r3]			 /* The first item in pxCurrentTCB is the task top of stack. */
+	ldr r0, [r1]
+
+	ldm r0!, (r4-r11, r14)		 /* Pop the core registers. */
+
+	tst r14, #0x10			 /* Is the task using the FPU context?  If so, pop the high vfp registers too. */
+	it eq
+	vldmiaeq r0!, (s16-s31)
+
+	msr psp, r0
+	isb
+	bx r14
+	}
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void ) iv IVT_INT_SysTick ics ICS_AUTO
+{
+	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
+	executes all interrupts must be unmasked.  There is therefore no need to
+	save and then restore the interrupt mask value as its value is already
+	known - therefore the slightly faster portDISABLE_INTERRUPTS() function is
+	used in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
+	portDISABLE_INTERRUPTS();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_TICKLESS_IDLE == 1 ) && ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 ) )
+
+	void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+	TickType_t xModifiableIdleTime;
+
+		/* Make sure the SysTick reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
+		is accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+		/* Calculate the reload value required to wait xExpectedIdleTime
+		tick periods.  -1 is used because this code will execute part way
+		through one of the tick periods. */
+		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+		if( ulReloadValue > ulStoppedTimerCompensation )
+		{
+			ulReloadValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Enter a critical section but don't use the taskENTER_CRITICAL()
+		method as that will mask interrupts that should exit sleep mode. */
+		__asm { "cpsid i" };
+		__asm { "dsb" };
+		__asm { "isb" };
+
+		/* If a context switch is pending or a task is waiting for the scheduler
+		to be unsuspended then abandon the low power entry. */
+		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+		{
+			/* Restart from whatever is left in the count register to complete
+			this tick period. */
+			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Reset the reload register to the value required for normal tick
+			periods. */
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Re-enable interrupts - see comments above the cpsid instruction()
+			above. */
+			__asm { "cpsie i" };
+		}
+		else
+		{
+			/* Set the new reload value. */
+			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+			/* Clear the SysTick count flag and set the count value back to
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+			set its parameter to 0 to indicate that its implementation contains
+			its own wait for interrupt or wait for event instruction, and so wfi
+			should not be executed again.  However, the original expected idle
+			time variable must remain unmodified, so a copy is taken. */
+			xModifiableIdleTime = xExpectedIdleTime;
+			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+			if( xModifiableIdleTime > 0 )
+			{
+				__asm { "dsb" };
+				__asm { "wfi" };
+				__asm { "isb" };
+			}
+			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+			/* Re-enable interrupts to allow the interrupt that brought the MCU
+			out of sleep mode to execute immediately.  see comments above
+			__disable_interrupt() call above. */
+			__asm { "cpsie i" };
+			__asm { "dsb" };
+			__asm { "isb" };
+
+			/* Disable interrupts again because the clock is about to be stopped
+			and interrupts that execute while the clock is stopped will increase
+			any slippage between the time maintained by the RTOS and calendar
+			time. */
+			__asm { "cpsid i" };
+			__asm { "dsb" };
+			__asm { "isb" };
+
+			/* Disable the SysTick clock without reading the
+			portNVIC_SYSTICK_CTRL_REG register to ensure the
+			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+			the time the SysTick is stopped for is accounted for as best it can
+			be, but using the tickless mode will inevitably result in some tiny
+			drift of the time maintained by the kernel with respect to calendar
+			time*/
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+			/* Determine if the SysTick clock has already counted to zero and
+			been set back to the current reload value (the reload back being
+			correct for the entire expected idle time) or if the SysTick is yet
+			to count to zero (in which case an interrupt other than the SysTick
+			must have brought the system out of sleep mode). */
+			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			{
+				uint32_t ulCalculatedLoadValue;
+
+				/* The tick interrupt is already pending, and the SysTick count
+				reloaded with ulReloadValue.  Reset the
+				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+				period. */
+				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+				/* Don't allow a tiny value, or values that have somehow
+				underflowed because the post sleep hook did something
+				that took too long. */
+				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+				{
+					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+				}
+
+				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+				/* As the pending tick will be processed as soon as this
+				function exits, the tick value maintained by the tick is stepped
+				forward by one less than the time spent waiting. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				Work out how long the sleep lasted rounded to complete tick
+				periods (not the ulReload value which accounted for part
+				ticks). */
+				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+				/* How many complete tick periods passed while the processor
+				was waiting? */
+				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+				/* The reload value is set to whatever fraction of a single tick
+				period remains. */
+				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+			}
+
+			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+			value. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+			vTaskStepTick( ulCompleteTickPeriods );
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Exit with interrpts enabled. */
+			__asm { "cpsie i" };
+		}
+	}
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+#if( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
+
+	void vPortSetupTimerInterrupt( void )
+	{
+			/* Calculate the constants required to configure the tick interrupt. */
+			#if( configUSE_TICKLESS_IDLE == 1 )
+			{
+					ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+					xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+					ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+			}
+			#endif /* configUSE_TICKLESS_IDLE */
+
+			/* Reset SysTick. */
+			portNVIC_SYSTICK_CTRL_REG = 0UL;
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+			/* Configure SysTick to interrupt at the requested rate. */
+			portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+	}
+
+#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
+/*-----------------------------------------------------------*/
+
+/* This is a naked function. */
+static void vPortEnableVFP( void )
+{
+	__asm {
+			ldr r0, =0xE000ED88			 /* The FPU enable bits are in the CPACR. */
+			ldr r1, [r0]
+
+			orr r1, r1, #0xF00000		 /* Enable CP10 and CP11 coprocessors, then save back. */
+			str r1, [r0]
+			bx r14
+	};
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortIsInsideInterrupt( void )
+{
+BaseType_t xReturn;
+
+	/* Obtain the number of the currently executing interrupt. */
+	if( CPU_REG_GET( CPU_IPSR ) == 0 )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	/* Limitations in the MikroC inline asm means ulCurrentInterrupt has to be
+	global - which makes vPortValidateInterruptPriority() non re-entrant.
+	However that should not matter as an interrupt can only itself be
+	interrupted by a higher priority interrupt.  That means if
+	ulCurrentInterrupt, so ulCurrentInterrupt getting corrupted cannot lead to
+	an invalid interrupt priority being missed. */
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+	void vPortValidateInterruptPriority( void )
+	{
+		/* Obtain the number of the currently executing interrupt. */
+		__asm { push (r0, r1)
+				mrs r0, ipsr
+				ldr r1, =_ulCurrentInterrupt
+				str r0, [r1]
+				pop (r0, r1)
+		};
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = *( ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + ulCurrentInterrupt ) );
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredictable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MikroC/ARM_CM4F/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MikroC/ARM_CM4F/portmacro.h
new file mode 100644
index 0000000..2931cbc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/MikroC/ARM_CM4F/portmacro.h
@@ -0,0 +1,188 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* The compiler needs to be told functions that are only referenced by pointer
+are to be included in the build.  NOTE:  Omitting these lines will result in a
+run-time crash, not a linker error! */
+#pragma funcall vTaskStartScheduler prvIdleTask
+#pragma funcall xTimerCreateTimerTask prvTimerTask
+
+/* Type definitions. */
+#define portCHAR        char
+#define portFLOAT        float
+#define portDOUBLE        double
+#define portLONG        long
+#define portSHORT        short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE    long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+    not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH            ( -1 )
+#define portTICK_PERIOD_MS            ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT            8
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD()                                                             \
+{                                                                                \
+    /* Set a PendSV to request a context switch. */                                \
+    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;                                \
+                                                                                \
+    /* Barriers are normally not required but do ensure the code is completely    \
+    within the specified behaviour for the architecture. */                        \
+  __asm{ dsb  };                       \
+  __asm{ isb };                      \
+}
+
+#define portNVIC_INT_CTRL_REG        ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT        ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portDISABLE_INTERRUPTS()                CPU_REG_SET( CPU_BASEPRI, configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm{ dsb }; __asm{ isb }
+#define portENABLE_INTERRUPTS()                    CPU_REG_SET( CPU_BASEPRI, 0 );
+#define portENTER_CRITICAL()                    vPortEnterCritical()
+#define portEXIT_CRITICAL()                        vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()        ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)    CPU_REG_SET( CPU_BASEPRI, x ); /* Barrier instructions not used as this is only used to lower the basepri. */
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+    extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+    /* Generic helper function. */
+    __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+    uint8_t ucReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
+        return ucReturn;
+    }
+
+    /* Check the configuration. */
+    #if( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #endif
+
+    /* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /*-----------------------------------------------------------*/
+
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+    void vPortValidateInterruptPriority( void );
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()     vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+BaseType_t xPortIsInsideInterrupt( void );
+
+/*-----------------------------------------------------------*/
+
+static inline uint32_t ulPortRaiseBASEPRI( void )
+{
+uint32_t ulOriginalBASEPRI;
+
+	ulOriginalBASEPRI = CPU_REG_GET( CPU_BASEPRI );
+	CPU_REG_SET( CPU_BASEPRI, configMAX_SYSCALL_INTERRUPT_PRIORITY );
+	__asm{ dsb };
+	__asm{ isb };
+	return ulOriginalBASEPRI;
+}
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/port.c
new file mode 100644
index 0000000..442af33
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/port.c
@@ -0,0 +1,239 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the Tern EE 186
+ * port.
+ *----------------------------------------------------------*/
+
+/* Library includes. */
+#include 
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "portasm.h"
+
+/* The timer increments every four clocks, hence the divide by 4. */
+#define portTIMER_COMPARE ( uint16_t ) ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / ( uint32_t ) 4 )
+
+/* From the RDC data sheet. */
+#define portENABLE_TIMER_AND_INTERRUPT ( uint16_t ) 0xe001
+
+/* Interrupt control. */
+#define portEIO_REGISTER 0xff22
+#define portCLEAR_INTERRUPT 0x0008
+
+/* Setup the hardware to generate the required tick frequency. */
+static void prvSetupTimerInterrupt( void );
+
+/* The ISR used depends on whether the preemptive or cooperative scheduler
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
+	/* Tick service routine used by the scheduler when preemptive scheduling is
+	being used. */
+	static void __interrupt __far prvPreemptiveTick( void );
+#else
+	/* Tick service routine used by the scheduler when cooperative scheduling is
+	being used. */
+	static void __interrupt __far prvNonPreemptiveTick( void );
+#endif
+
+/* Trap routine used by taskYIELD() to manually cause a context switch. */
+static void __interrupt __far prvYieldProcessor( void );
+
+/* The timer initialisation functions leave interrupts enabled,
+which is not what we want.  This ISR is installed temporarily in case
+the timer fires before we get a change to disable interrupts again. */
+static void __interrupt __far prvDummyISR( void );
+
+/*-----------------------------------------------------------*/
+/* See header file for description. */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t DS_Reg = 0;
+
+	/* Place a few bytes of known values on the bottom of the stack.
+	This is just useful for debugging. */
+
+	*pxTopOfStack = 0x1111;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2222;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x3333;
+	pxTopOfStack--;
+
+	/* We are going to start the scheduler using a return from interrupt
+	instruction to load the program counter, so first there would be the
+	function call with parameters preamble. */
+	
+	*pxTopOfStack = FP_SEG( pvParameters );
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pvParameters );
+	pxTopOfStack--;
+	*pxTopOfStack = FP_SEG( pxCode );
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pxCode );
+	pxTopOfStack--;
+
+	/* Next the status register and interrupt return address. */
+	*pxTopOfStack = portINITIAL_SW;
+	pxTopOfStack--;
+	*pxTopOfStack = FP_SEG( pxCode );
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pxCode );
+	pxTopOfStack--;
+
+	/* The remaining registers would be pushed on the stack by our context
+	switch function.  These are loaded with values simply to make debugging
+	easier. */
+	*pxTopOfStack = ( StackType_t ) 0xAAAA;	/* AX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xCCCC;	/* CX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xDDDD;	/* DX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xEEEE;	/* ES */
+	pxTopOfStack--;
+
+	/* We need the true data segment. */
+	__asm{	MOV DS_Reg, DS };
+
+	*pxTopOfStack = DS_Reg;						/* DS */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0123;	/* SI */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xDDDD;	/* DI */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BP */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* This is called with interrupts already disabled. */
+
+	/* Put our manual switch (yield) function on a known
+	vector. */
+	setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
+
+	/* Setup the tick interrupt. */
+	prvSetupTimerInterrupt();
+
+	/* Kick off the scheduler by setting up the context of the first task. */
+	portFIRST_CONTEXT();
+
+	/* Should not get here! */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static void __interrupt __far prvDummyISR( void )
+{
+	/* The timer initialisation functions leave interrupts enabled,
+	which is not what we want.  This ISR is installed temporarily in case
+	the timer fires before we get a change to disable interrupts again. */
+	outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
+}
+/*-----------------------------------------------------------*/
+
+/* The ISR used depends on whether the preemptive or cooperative scheduler
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
+	static void __interrupt __far prvPreemptiveTick( void )
+	{
+		/* Get the scheduler to update the task states following the tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Switch in the context of the next task to be run. */
+			portSWITCH_CONTEXT();
+		}
+
+		/* Reset interrupt. */
+		outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
+	}
+#else
+	static void __interrupt __far prvNonPreemptiveTick( void )
+	{
+		/* Same as preemptive tick, but the cooperative scheduler is being used
+		so we don't have to switch in the context of the next task. */
+		xTaskIncrementTick();
+		
+		/* Reset interrupt. */
+		outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+static void __interrupt __far prvYieldProcessor( void )
+{
+	/* Switch in the context of the next task to be run. */
+	portSWITCH_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+const uint16_t usTimerACompare = portTIMER_COMPARE, usTimerAMode = portENABLE_TIMER_AND_INTERRUPT;
+const uint16_t usT2_IRQ = 0x13;
+
+	/* Configure the timer, the dummy handler is used here as the init
+	function leaves interrupts enabled. */
+	t2_init( usTimerAMode, usTimerACompare, prvDummyISR );
+
+	/* Disable interrupts again before installing the real handlers. */
+	portDISABLE_INTERRUPTS();
+
+	#if( configUSE_PREEMPTION == 1 )
+		/* Tick service routine used by the scheduler when preemptive scheduling is
+		being used. */
+		setvect( usT2_IRQ, prvPreemptiveTick );
+	#else
+		/* Tick service routine used by the scheduler when cooperative scheduling is
+		being used. */
+		setvect( usT2_IRQ, prvNonPreemptiveTick );
+	#endif
+}
+
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h
new file mode 100644
index 0000000..e19fc83
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h
@@ -0,0 +1,76 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+extern void vTaskSwitchContext( void );
+
+/*
+ * Saves the stack pointer for one task into its TCB, calls
+ * vTaskSwitchContext() to update the TCB being used, then restores the stack
+ * from the new TCB read to run the task.
+ */
+void portSWITCH_CONTEXT( void );
+
+/*
+ * Load the stack pointer from the TCB of the task which is going to be first
+ * to execute.  Then force an IRET so the registers and IP are popped off the
+ * stack.
+ */
+void portFIRST_CONTEXT( void );
+
+#define portSWITCH_CONTEXT()										 \
+						asm { mov	ax, seg pxCurrentTCB		} \
+							asm { mov	ds, ax						}  \
+							asm { les	bx, pxCurrentTCB			}	/* Save the stack pointer into the TCB. */    \
+							asm { mov	es:0x2[ bx ], ss			}   \
+							asm { mov	es:[ bx ], sp				}   \
+							asm { call  far ptr vTaskSwitchContext	}	/* Perform the switch. */   \
+							asm { mov	ax, seg pxCurrentTCB		}	/* Restore the stack pointer from the TCB. */  \
+							asm { mov	ds, ax						}   \
+							asm { les	bx, dword ptr pxCurrentTCB	}   \
+							asm { mov	ss, es:[ bx + 2 ]			}      \
+							asm { mov	sp, es:[ bx ]				}
+
+#define portFIRST_CONTEXT()												\
+							asm { mov	ax, seg pxCurrentTCB		}	\
+							asm { mov	ds, ax						}	\
+							asm { les	bx, dword ptr pxCurrentTCB	}	\
+							asm { mov	ss, es:[ bx + 2 ]			}	\
+							asm { mov	sp, es:[ bx ]				}	\
+							asm { pop	bp							}	\
+							asm { pop	di							}	\
+							asm { pop	si							}	\
+							asm { pop	ds							}	\
+							asm { pop	es							}	\
+							asm { pop	dx							}	\
+							asm { pop	cx							}	\
+							asm { pop	bx							}	\
+							asm { pop	ax							}	\
+							asm { iret								}
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h
new file mode 100644
index 0000000..4b0f367
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h
@@ -0,0 +1,106 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		long
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	uint16_t
+#define portBASE_TYPE	short
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+#define portENTER_CRITICAL()			__asm{ pushf }  \
+										__asm{ cli 	 }	\
+
+#define portEXIT_CRITICAL()				__asm{ popf }
+
+#define portDISABLE_INTERRUPTS()		__asm{ cli }
+
+#define portENABLE_INTERRUPTS()			__asm{ sti }
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portNOP()						__asm{ nop }
+#define portSTACK_GROWTH				( -1 )
+#define portSWITCH_INT_NUMBER 			0x80
+#define portYIELD()						__asm{ int portSWITCH_INT_NUMBER }
+#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT				2
+#define portINITIAL_SW					( ( portSTACK_TYPE ) 0x0202 )	/* Start the tasks with interrupts enabled. */
+/*-----------------------------------------------------------*/
+
+/* Compiler specifics. */
+#define portINPUT_BYTE( xAddr )				inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )	outp( xAddr, ucValue )
+#define portINPUT_WORD( xAddr )				inpw( xAddr )
+#define portOUTPUT_WORD( xAddr, usValue )	outpw( xAddr, usValue )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/port.c
new file mode 100644
index 0000000..e28b3ca
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/port.c
@@ -0,0 +1,219 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the Tern EE 186
+ * port.
+ *----------------------------------------------------------*/
+
+/* Library includes. */
+#include 
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "portasm.h"
+
+/* The timer increments every four clocks, hence the divide by 4. */
+#define portPRESCALE_VALUE ( 16 )
+#define portTIMER_COMPARE ( configCPU_CLOCK_HZ  / ( configTICK_RATE_HZ * 4UL ) )
+
+/* From the RDC data sheet. */
+#define portENABLE_TIMER_AND_INTERRUPT 	( uint16_t ) 0xe00b
+#define portENABLE_TIMER				( uint16_t ) 0xC001
+
+/* Interrupt control. */
+#define portEIO_REGISTER 0xff22
+#define portCLEAR_INTERRUPT 0x0008
+
+/* Setup the hardware to generate the required tick frequency. */
+static void prvSetupTimerInterrupt( void );
+
+/* The ISR used depends on whether the preemptive or cooperative scheduler
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
+	/* Tick service routine used by the scheduler when preemptive scheduling is
+	being used. */
+	static void __interrupt __far prvPreemptiveTick( void );
+#else
+	/* Tick service routine used by the scheduler when cooperative scheduling is
+	being used. */
+	static void __interrupt __far prvNonPreemptiveTick( void );
+#endif
+
+/* Trap routine used by taskYIELD() to manually cause a context switch. */
+static void __interrupt __far prvYieldProcessor( void );
+
+/*-----------------------------------------------------------*/
+/* See header file for description. */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t DS_Reg = 0;
+
+	/* We need the true data segment. */
+	__asm{	MOV DS_Reg, DS };
+
+	/* Place a few bytes of known values on the bottom of the stack.
+	This is just useful for debugging. */
+
+	*pxTopOfStack = 0x1111;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2222;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x3333;
+	pxTopOfStack--;
+
+	/* We are going to start the scheduler using a return from interrupt
+	instruction to load the program counter, so first there would be the
+	function call with parameters preamble. */
+	
+	*pxTopOfStack = FP_OFF( pvParameters );
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pxCode );
+	pxTopOfStack--;
+
+	/* Next the status register and interrupt return address. */
+	*pxTopOfStack = portINITIAL_SW;
+	pxTopOfStack--;
+	*pxTopOfStack = FP_SEG( pxCode );
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pxCode );
+	pxTopOfStack--;
+
+	/* The remaining registers would be pushed on the stack by our context
+	switch function.  These are loaded with values simply to make debugging
+	easier. */
+	*pxTopOfStack = ( StackType_t ) 0xAAAA;	/* AX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xCCCC;	/* CX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xDDDD;	/* DX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xEEEE;	/* ES */
+	pxTopOfStack--;
+
+	*pxTopOfStack = DS_Reg;						/* DS */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0123;	/* SI */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xDDDD;	/* DI */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BP */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* This is called with interrupts already disabled. */
+
+	/* Put our manual switch (yield) function on a known
+	vector. */
+	setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
+
+	/* Setup the tick interrupt. */
+	prvSetupTimerInterrupt();
+
+	/* Kick off the scheduler by setting up the context of the first task. */
+	portFIRST_CONTEXT();
+
+	/* Should not get here! */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+/* The ISR used depends on whether the preemptive or cooperative scheduler
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
+	static void __interrupt __far prvPreemptiveTick( void )
+	{
+		/* Get the scheduler to update the task states following the tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Switch in the context of the next task to be run. */
+			portEND_SWITCHING_ISR();
+		}
+
+		/* Reset interrupt. */
+		outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
+	}
+#else
+	static void __interrupt __far prvNonPreemptiveTick( void )
+	{
+		/* Same as preemptive tick, but the cooperative scheduler is being used
+		so we don't have to switch in the context of the next task. */
+		xTaskIncrementTick();
+		
+		/* Reset interrupt. */
+		outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+static void __interrupt __far prvYieldProcessor( void )
+{
+	/* Switch in the context of the next task to be run. */
+	portEND_SWITCHING_ISR();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+const uint32_t ulCompareValue = portTIMER_COMPARE;
+uint16_t usTimerCompare;
+
+	usTimerCompare = ( uint16_t ) ( ulCompareValue >> 4 );
+    t2_init( portENABLE_TIMER, portPRESCALE_VALUE, NULL );
+
+	#if( configUSE_PREEMPTION == 1 )
+		/* Tick service routine used by the scheduler when preemptive scheduling is
+		being used. */
+		t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvPreemptiveTick );
+	#else
+		/* Tick service routine used by the scheduler when cooperative scheduling is
+		being used. */
+		t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvNonPreemptiveTick );
+	#endif
+}
+
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/portasm.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/portasm.h
new file mode 100644
index 0000000..723cc21
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/portasm.h
@@ -0,0 +1,72 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORT_ASM_H
+#define PORT_ASM_H
+
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+extern void vTaskSwitchContext( void );
+
+/*
+ * Saves the stack pointer for one task into its TCB, calls
+ * vTaskSwitchContext() to update the TCB being used, then restores the stack
+ * from the new TCB read to run the task.
+ */
+void portEND_SWITCHING_ISR( void );
+
+/*
+ * Load the stack pointer from the TCB of the task which is going to be first
+ * to execute.  Then force an IRET so the registers and IP are popped off the
+ * stack.
+ */
+void portFIRST_CONTEXT( void );
+
+#define portEND_SWITCHING_ISR()											\
+							asm { mov	bx, [pxCurrentTCB]			}   \
+                            asm { mov	word ptr [bx], sp			}	\
+							asm { call  far ptr vTaskSwitchContext	}	\
+							asm { mov	bx, [pxCurrentTCB]			}	\
+							asm { mov	sp, [bx]					}
+
+#define portFIRST_CONTEXT()											\
+							asm { mov	bx, [pxCurrentTCB]			}	\
+							asm { mov	sp, [bx]					}	\
+							asm { pop	bp							}	\
+							asm { pop	di							}	\
+							asm { pop	si							}	\
+   							asm { pop	ds							}	\
+   							asm { pop	es							}	\
+							asm { pop	dx							}	\
+							asm { pop	cx							}	\
+							asm { pop	bx							}	\
+							asm { pop	ax							}	\
+							asm { iret								}
+
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/portmacro.h
new file mode 100644
index 0000000..79231c0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/portmacro.h
@@ -0,0 +1,107 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		long
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	uint16_t
+#define portBASE_TYPE	short
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+
+typedef void ( __interrupt __far *pxISR )();
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+#define portENTER_CRITICAL()			__asm{ pushf }  \
+										__asm{ cli 	 }	\
+
+#define portEXIT_CRITICAL()				__asm{ popf }
+
+#define portDISABLE_INTERRUPTS()		__asm{ cli }
+
+#define portENABLE_INTERRUPTS()			__asm{ sti }
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portNOP()						__asm{ nop }
+#define portSTACK_GROWTH				( -1 )
+#define portSWITCH_INT_NUMBER 			0x80
+#define portYIELD()						__asm{ int portSWITCH_INT_NUMBER }
+#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT				2
+#define portINITIAL_SW					( ( portSTACK_TYPE ) 0x0202 )	/* Start the tasks with interrupts enabled. */
+/*-----------------------------------------------------------*/
+
+/* Compiler specifics. */
+#define portINPUT_BYTE( xAddr )				inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )	outp( xAddr, ucValue )
+#define portINPUT_WORD( xAddr )				inpw( xAddr )
+#define portOUTPUT_WORD( xAddr, usValue )	outpw( xAddr, usValue )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/port.c
new file mode 100644
index 0000000..4705771
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/port.c
@@ -0,0 +1,291 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup the initial task context. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING	( ( StackType_t ) 0 )
+
+/* Constants required to setup the tick ISR. */
+#define portENABLE_TIMER			( ( uint8_t ) 0x01 )
+#define portPRESCALE_VALUE			0x00
+#define portINTERRUPT_ON_MATCH		( ( uint32_t ) 0x01 )
+#define portRESET_COUNT_ON_MATCH	( ( uint32_t ) 0x02 )
+
+/* Constants required to setup the VIC for the tick ISR. */
+#define portTIMER_VIC_CHANNEL		( ( uint32_t ) 0x0004 )
+#define portTIMER_VIC_CHANNEL_BIT	( ( uint32_t ) 0x0010 )
+#define portTIMER_VIC_ENABLE		( ( uint32_t ) 0x0020 )
+
+/* Constants required to handle interrupts. */
+#define portTIMER_MATCH_ISR_BIT		( ( uint8_t ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT		( ( uint32_t ) 0 )
+
+/*-----------------------------------------------------------*/
+
+/* The code generated by the Keil compiler does not maintain separate
+stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
+use the stack as per other ports.  Instead a variable is used to keep
+track of the critical section nesting.  This variable has to be stored
+as part of the task context and must be initialised to a non zero value. */
+
+#define portNO_CRITICAL_NESTING		( ( uint32_t ) 0 )
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* 
+ * The scheduler can only be started from ARM mode, so 
+ * vPortStartFirstSTask() is defined in portISR.c. 
+ */
+extern __asm void vPortStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as 
+	expected by the portRESTORE_CONTEXT() macro.
+
+	Remember where the top of the (simulated) stack is before we place 
+	anything on it. */
+	pxOriginalTOS = pxTopOfStack;
+	
+	/* To ensure asserts in tasks.c don't fail, although in this case the assert
+	is not really required. */
+	pxTopOfStack--;
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The last thing onto the stack is the status register, which is set for
+	system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+
+	pxTopOfStack--;
+
+	/* The code generated by the Keil compiler does not maintain separate
+	stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
+	use the stack as per other ports.  Instead a variable is used to keep
+	track of the critical section nesting.  This variable has to be stored
+	as part of the task context and is initially set to zero. */
+	*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Start the timer that generates the tick ISR. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task.  This is done from portISR.c as ARM mode must be
+	used. */
+	vPortStartFirstTask();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  If this is required - stop the tick ISR then
+	return back to main. */
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 0
+
+	/* 
+	 * The cooperative scheduler requires a normal IRQ service routine to 
+	 * simply increment the system tick. 
+	 */
+	void vNonPreemptiveTick( void ) __irq;
+	void vNonPreemptiveTick( void ) __irq
+	{
+		/* Increment the tick count - this may make a delaying task ready
+		to run - but a context switch is not performed. */		
+		xTaskIncrementTick();
+
+		T0IR = portTIMER_MATCH_ISR_BIT;				/* Clear the timer event */
+		VICVectAddr = portCLEAR_VIC_INTERRUPT;		/* Acknowledge the Interrupt */
+	}
+
+ #else
+
+	/*
+	 **************************************************************************
+	 * The preemptive scheduler ISR is written in assembler and can be found   
+	 * in the portASM.s file. This will only get used if portUSE_PREEMPTION
+	 * is set to 1 in portmacro.h
+	 ************************************************************************** 
+	 */
+
+	  void vPreemptiveTick( void );
+
+#endif
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+uint32_t ulCompareMatch;
+
+	/* A 1ms tick does not require the use of the timer prescale.  This is
+	defaulted to zero but can be used if necessary. */
+	T0PR = portPRESCALE_VALUE;
+
+	/* Calculate the match value required for our wanted tick rate. */
+	ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+	/* Protect against divide by zero.  Using an if() statement still results
+	in a warning - hence the #if. */
+	#if portPRESCALE_VALUE != 0
+	{
+		ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
+	}
+	#endif
+
+	T0MR0 = ulCompareMatch;
+
+	/* Generate tick with timer 0 compare match. */
+	T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
+
+	/* Setup the VIC for the timer. */
+	VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
+	VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
+	
+	/* The ISR installed depends on whether the preemptive or cooperative
+	scheduler is being used. */
+	#if configUSE_PREEMPTION == 1
+	{	
+		VICVectAddr0 = ( uint32_t ) vPreemptiveTick;
+	}
+	#else
+	{
+		VICVectAddr0 = ( uint32_t ) vNonPreemptiveTick;
+	}
+	#endif
+
+	VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
+
+	/* Start the timer - interrupts are disabled when this function is called
+	so it is okay to do this here. */
+	T0TCR = portENABLE_TIMER;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 							*/
+	__disable_irq();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed 
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Enable interrupts as per portEXIT_CRITICAL(). */
+			__enable_irq();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portASM.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portASM.s
new file mode 100644
index 0000000..dadcafa
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portASM.s
@@ -0,0 +1,124 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	INCLUDE portmacro.inc
+
+	IMPORT	vTaskSwitchContext
+	IMPORT	xTaskIncrementTick
+
+	EXPORT	vPortYieldProcessor
+	EXPORT	vPortStartFirstTask
+	EXPORT	vPreemptiveTick
+	EXPORT	vPortYield
+
+
+VICVECTADDR	EQU	0xFFFFF030
+T0IR		EQU	0xE0004000
+T0MATCHBIT	EQU	0x00000001
+
+	ARM
+	AREA	PORT_ASM, CODE, READONLY
+
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Starting the first task is done by just restoring the context
+; setup by pxPortInitialiseStack
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortStartFirstTask
+
+	PRESERVE8
+
+	portRESTORE_CONTEXT
+
+vPortYield
+
+	PRESERVE8
+
+	SVC 0
+	bx lr
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Interrupt service routine for the SWI interrupt.  The vector table is
+; configured in the startup.s file.
+;
+; vPortYieldProcessor() is used to manually force a context switch.  The
+; SWI interrupt is generated by a call to taskYIELD() or portYIELD().
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+vPortYieldProcessor
+
+	PRESERVE8
+
+	; Within an IRQ ISR the link register has an offset from the true return
+	; address, but an SWI ISR does not.  Add the offset manually so the same
+	; ISR return code can be used in both cases.
+	ADD	LR, LR, #4
+
+	; Perform the context switch.
+	portSAVE_CONTEXT					; Save current task context
+	LDR R0, =vTaskSwitchContext			; Get the address of the context switch function
+	MOV LR, PC							; Store the return address
+	BX	R0								; Call the contedxt switch function
+	portRESTORE_CONTEXT					; restore the context of the selected task
+
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Interrupt service routine for preemptive scheduler tick timer
+; Only used if portUSE_PREEMPTION is set to 1 in portmacro.h
+;
+; Uses timer 0 of LPC21XX Family
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+vPreemptiveTick
+
+	PRESERVE8
+
+	portSAVE_CONTEXT					; Save the context of the current task.
+
+	LDR R0, =xTaskIncrementTick			; Increment the tick count.
+	MOV LR, PC							; This may make a delayed task ready
+	BX R0								; to run.
+
+	CMP R0, #0
+	BEQ SkipContextSwitch
+	LDR R0, =vTaskSwitchContext			; Find the highest priority task that
+	MOV LR, PC							; is ready to run.
+	BX R0
+SkipContextSwitch
+	MOV R0, #T0MATCHBIT					; Clear the timer event
+	LDR R1, =T0IR
+	STR R0, [R1]
+
+	LDR	R0, =VICVECTADDR				; Acknowledge the interrupt
+	STR	R0,[R0]
+
+	portRESTORE_CONTEXT					; Restore the context of the highest
+										; priority task that is ready to run.
+	END
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portmacro.h
new file mode 100644
index 0000000..44bb601
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portmacro.h
@@ -0,0 +1,146 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/*-----------------------------------------------------------
+ * ISR entry and exit macros.  These are only required if a task switch
+ * is required from an ISR.
+ *----------------------------------------------------------*/
+
+/* If a switch is required then we just need to call */
+/* vTaskSwitchContext() as the context has already been */
+/* saved. */
+
+#define portEXIT_SWITCHING_ISR(SwitchRequired)				 \
+{															 \
+extern void vTaskSwitchContext(void);						 \
+															 \
+		if(SwitchRequired)									 \
+		{													 \
+			vTaskSwitchContext();							 \
+		}													 \
+}															 \
+
+extern void vPortYield( void );
+#define portYIELD() vPortYield()
+
+
+/* Critical section management. */
+
+/*
+ ******************************************************************
+ * We don't need to worry about whether we're in ARM or
+ * THUMB mode with the Keil Real View compiler when enabling
+ * or disabling interrupts as the compiler's intrinsic functions
+ * take care of that for us.
+ *******************************************************************
+ */
+#define portDISABLE_INTERRUPTS()	__disable_irq()
+#define portENABLE_INTERRUPTS()		__enable_irq()
+
+
+/*-----------------------------------------------------------
+ * Critical section control
+ *
+ * The code generated by the Keil compiler does not maintain separate
+ * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
+ * use the stack as per other ports.  Instead a variable is used to keep
+ * track of the critical section nesting.  This necessitates the use of a
+ * function in place of the macro.
+ *----------------------------------------------------------*/
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+/*-----------------------------------------------------------*/
+
+/* Compiler specifics. */
+#define inline
+#define register
+#define portNOP()	__asm{ NOP }
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portmacro.inc b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portmacro.inc
new file mode 100644
index 0000000..268a024
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portmacro.inc
@@ -0,0 +1,91 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	IMPORT  ulCriticalNesting		;
+	IMPORT	pxCurrentTCB			;
+
+
+	MACRO
+	portRESTORE_CONTEXT
+
+
+	LDR		R0, =pxCurrentTCB		; Set the LR to the task stack.  The location was...
+	LDR		R0, [R0]				; ... stored in pxCurrentTCB
+	LDR		LR, [R0]
+
+	LDR		R0, =ulCriticalNesting	; The critical nesting depth is the first item on...
+	LDMFD	LR!, {R1}				; ...the stack.  Load it into the ulCriticalNesting var.
+	STR		R1, [R0]				;
+
+	LDMFD	LR!, {R0}				; Get the SPSR from the stack.
+	MSR		SPSR_cxsf, R0			;
+
+	LDMFD	LR, {R0-R14}^			; Restore all system mode registers for the task.
+	NOP								;
+
+	LDR		LR, [LR, #+60]			; Restore the return address
+
+									; And return - correcting the offset in the LR to obtain ...
+	SUBS	PC, LR, #4				; ...the correct address.
+
+	MEND
+
+; /**********************************************************************/
+
+	MACRO
+	portSAVE_CONTEXT
+
+
+	STMDB 	SP!, {R0}				; Store R0 first as we need to use it.
+
+	STMDB	SP,{SP}^				; Set R0 to point to the task stack pointer.
+	NOP								;
+	SUB		SP, SP, #4				;
+	LDMIA	SP!,{R0}				;
+
+	STMDB	R0!, {LR}				; Push the return address onto the stack.
+	MOV		LR, R0					; Now we have saved LR we can use it instead of R0.
+	LDMIA	SP!, {R0}				; Pop R0 so we can save it onto the system mode stack.
+
+	STMDB	LR,{R0-LR}^				; Push all the system mode registers onto the task stack.
+	NOP								;
+	SUB		LR, LR, #60				;
+
+	MRS		R0, SPSR				; Push the SPSR onto the task stack.
+	STMDB	LR!, {R0}				;
+
+	LDR		R0, =ulCriticalNesting	;
+	LDR		R0, [R0]				;
+	STMDB	LR!, {R0}				;
+
+	LDR		R0, =pxCurrentTCB		; Store the new top of stack for the task.
+	LDR		R1, [R0]				;
+	STR		LR, [R1]				;
+
+	MEND
+
+	END
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CA9/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CA9/port.c
new file mode 100644
index 0000000..c68d4bd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CA9/port.c
@@ -0,0 +1,480 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
+	#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
+	#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configUNIQUE_INTERRUPT_PRIORITIES
+	#error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configSETUP_TICK_INTERRUPT
+	#error configSETUP_TICK_INTERRUPT() must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif /* configSETUP_TICK_INTERRUPT */
+
+#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/* In case security extensions are implemented. */
+#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+#endif
+
+#ifndef configCLEAR_TICK_INTERRUPT
+	#define configCLEAR_TICK_INTERRUPT()
+#endif
+
+/* The number of bits to shift for an interrupt priority is dependent on the
+number of bits implemented by the interrupt controller. */
+#if configUNIQUE_INTERRUPT_PRIORITIES == 16
+	#define portPRIORITY_SHIFT 4
+	#define portMAX_BINARY_POINT_VALUE	3
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
+	#define portPRIORITY_SHIFT 3
+	#define portMAX_BINARY_POINT_VALUE	2
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
+	#define portPRIORITY_SHIFT 2
+	#define portMAX_BINARY_POINT_VALUE	1
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
+	#define portPRIORITY_SHIFT 1
+	#define portMAX_BINARY_POINT_VALUE	0
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
+	#define portPRIORITY_SHIFT 0
+	#define portMAX_BINARY_POINT_VALUE	0
+#else
+	#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+this value. */
+#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
+
+/* In all GICs 255 can be written to the priority mask register to unmask all
+(but the lowest) interrupt priority. */
+#define portUNMASK_VALUE				( 0xFFUL )
+
+/* Tasks are not created with a floating point context, but can be given a
+floating point context after they have been created.  A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
+
+/* Interrupt controller access addresses. */
+#define portICCPMR_PRIORITY_MASK_OFFSET  		( 0x04 )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET 	( 0x10 )
+#define portICCBPR_BINARY_POINT_OFFSET			( 0x08 )
+#define portICCRPR_RUNNING_PRIORITY_OFFSET		( 0x14 )
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS 		( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER 					( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS 	( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS 		( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS 			( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+#define portICCBPR_BINARY_POINT_REGISTER 					( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+#define portICCRPR_RUNNING_PRIORITY_REGISTER 				( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+
+/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
+point is zero. */
+#define portBINARY_POINT_BITS			( ( uint8_t ) 0x03 )
+
+/* Constants required to setup the initial task context. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS			( 0x01UL )
+
+/* Masks all bits in the APSR other than the mode bits. */
+#define portAPSR_MODE_BITS_MASK			( 0x1F )
+
+/* The value of the mode bits in the APSR when the CPU is executing in user
+mode. */
+#define portAPSR_USER_MODE				( 0x10 )
+
+/* Macro to unmask all interrupt priorities. */
+#define portCLEAR_INTERRUPT_MASK()											\
+{																			\
+	__disable_irq();														\
+	portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;					\
+	__asm(	"DSB		\n"													\
+			"ISB		\n" );												\
+	__enable_irq();															\
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing.  This function is necessarily written in
+ * assembly code so is implemented in portASM.s.
+ */
+extern void vPortRestoreTaskContext( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting.  This
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts.  As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/* Used to pass constants into the ASM code.  The address at which variables are
+placed is the constant value so indirect loads in the asm code are not
+required. */
+uint32_t ulICCIAR __attribute__( ( at( portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ) ) );
+uint32_t ulICCEOIR __attribute__( ( at( portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ) ) );
+uint32_t ulICCPMR __attribute__( ( at( portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ) ) );
+uint32_t ulAsmAPIPriorityMask __attribute__( ( at( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) );
+
+/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then
+a floating point context must be saved and restored for the task. */
+uint32_t ulPortTaskHasFPUContext = pdFALSE;
+
+/* Set to 1 to pend a context switch from an ISR. */
+uint32_t ulPortYieldRequired = pdFALSE;
+
+/* Counts the interrupt nesting depth.  A context switch is only performed if
+if the nesting depth is 0. */
+uint32_t ulPortInterruptNesting = 0UL;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro.
+
+	The fist real value on the stack is the status register, which is set for
+	system mode, with interrupts enabled.  A few NULLs are added first to ensure
+	GDB does not try decoding a non-existent return address. */
+	*pxTopOfStack = NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+	{
+		/* The task will start in THUMB mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+
+	pxTopOfStack--;
+
+	/* Next the return address, which in this case is the start of the task. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+
+	/* Next all the registers other than the stack pointer. */
+	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The task will start with a critical nesting count of 0 as interrupts are
+	enabled. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+	pxTopOfStack--;
+
+	/* The task will start without a floating point context.  A task that uses
+	the floating point hardware must call vPortTaskUsesFPU() before executing
+	any floating point instructions. */
+	*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( ulPortInterruptNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+uint32_t ulAPSR;
+
+	/* Only continue if the CPU is not in User mode.  The CPU must be in a
+	Privileged mode for the scheduler to start. */
+	__asm( "MRS ulAPSR, APSR" );
+	ulAPSR &= portAPSR_MODE_BITS_MASK;
+	configASSERT( ulAPSR != portAPSR_USER_MODE );
+
+	if( ulAPSR != portAPSR_USER_MODE )
+	{
+		/* Only continue if the binary point value is set to its lowest possible
+		setting.  See the comments in vPortValidateInterruptPriority() below for
+		more information. */
+		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+
+		if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
+		{
+			/* Start the timer that generates the tick ISR. */
+			configSETUP_TICK_INTERRUPT();
+
+			__enable_irq();
+			vPortRestoreTaskContext();
+		}
+	}
+
+	/* Will only get here if vTaskStartScheduler() was called with the CPU in
+	a non-privileged mode or the binary point register was not set to its lowest
+	possible value. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 	*/
+	ulPortSetInterruptMask();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( ulCriticalNesting == 1 )
+	{
+		configASSERT( ulPortInterruptNesting == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as the critical section is being
+		exited. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then all interrupt
+		priorities must be re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Critical nesting has reached zero so all interrupt priorities
+			should be unmasked. */
+			portCLEAR_INTERRUPT_MASK();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void FreeRTOS_Tick_Handler( void )
+{
+	/* Set interrupt mask before altering scheduler structures.   The tick
+	handler runs at the lowest priority, so interrupts cannot already be masked,
+	so there is no need to save and restore the current mask value. */
+	__disable_irq();
+	portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+	__asm(	"DSB		\n"
+			"ISB		\n" );
+	__enable_irq();
+
+	/* Increment the RTOS tick. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		ulPortYieldRequired = pdTRUE;
+	}
+
+	/* Ensure all interrupt priorities are active again. */
+	portCLEAR_INTERRUPT_MASK();
+	configCLEAR_TICK_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortTaskUsesFPU( void )
+{
+uint32_t ulInitialFPSCR = 0;
+
+	/* A task is registering the fact that it needs an FPU context.  Set the
+	FPU flag (which is saved as part of the task context). */
+	ulPortTaskHasFPUContext = pdTRUE;
+
+	/* Initialise the floating point status register. */
+	__asm( "FMXR 	FPSCR, ulInitialFPSCR" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMask( uint32_t ulNewMaskValue )
+{
+	if( ulNewMaskValue == pdFALSE )
+	{
+		portCLEAR_INTERRUPT_MASK();
+	}
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortSetInterruptMask( void )
+{
+uint32_t ulReturn;
+
+	__disable_irq();
+	if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
+	{
+		/* Interrupts were already masked. */
+		ulReturn = pdTRUE;
+	}
+	else
+	{
+		ulReturn = pdFALSE;
+		portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+		__asm(	"DSB		\n"
+				"ISB		\n" );
+	}
+	__enable_irq();
+
+	return ulReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+		/* The following assertion will fail if a service routine (ISR) for
+		an interrupt that has been assigned a priority above
+		configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+		function.  ISR safe FreeRTOS API functions must *only* be called
+		from interrupts that have been assigned a priority at or below
+		configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+		Numerically low interrupt priority numbers represent logically high
+		interrupt priorities, therefore the priority of the interrupt must
+		be set to a value equal to or numerically *higher* than
+		configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+		FreeRTOS maintains separate thread and ISR API functions to ensure
+		interrupt entry is as fast and simple as possible.
+
+		The following links provide detailed information:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html
+		http://www.freertos.org/FAQHelp.html */
+		configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+
+		/* Priority grouping:  The interrupt controller (GIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		The priority grouping is configured by the GIC's binary point register
+		(ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
+		possible value (which may be above 0). */
+		configASSERT( portICCBPR_BINARY_POINT_REGISTER <= portMAX_BINARY_POINT_VALUE );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CA9/portASM.s b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CA9/portASM.s
new file mode 100644
index 0000000..84ff0d6
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CA9/portASM.s
@@ -0,0 +1,174 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	INCLUDE portmacro.inc
+
+	IMPORT	vApplicationIRQHandler
+	IMPORT	vTaskSwitchContext
+	IMPORT	ulPortYieldRequired
+	IMPORT	ulPortInterruptNesting
+	IMPORT	vTaskSwitchContext
+	IMPORT	ulICCIAR
+	IMPORT	ulICCEOIR
+
+	EXPORT	FreeRTOS_SWI_Handler
+	EXPORT  FreeRTOS_IRQ_Handler
+	EXPORT 	vPortRestoreTaskContext
+
+	ARM
+	AREA	PORT_ASM, CODE, READONLY
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; SVC handler is used to yield a task.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+FreeRTOS_SWI_Handler
+
+	PRESERVE8
+
+	; Save the context of the current task and select a new task to run.
+	portSAVE_CONTEXT
+	LDR R0, =vTaskSwitchContext
+	BLX	R0
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; vPortRestoreTaskContext is used to start the scheduler.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortRestoreTaskContext
+	; Switch to system mode
+	CPS		#SYS_MODE
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; PL390 GIC interrupt handler
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+FreeRTOS_IRQ_Handler
+
+	; Return to the interrupted instruction.
+	SUB		lr, lr, #4
+
+	; Push the return address and SPSR
+	PUSH	{lr}
+	MRS		lr, SPSR
+	PUSH	{lr}
+
+	; Change to supervisor mode to allow reentry.
+	CPS		#SVC_MODE
+
+	; Push used registers.
+	PUSH	{r0-r4, r12}
+
+	; Increment nesting count.  r3 holds the address of ulPortInterruptNesting
+	; for future use.  r1 holds the original ulPortInterruptNesting value for
+	; future use.
+	LDR		r3, =ulPortInterruptNesting
+	LDR		r1, [r3]
+	ADD		r4, r1, #1
+	STR		r4, [r3]
+
+	; Read value from the interrupt acknowledge register, which is stored in r0
+	; for future parameter and interrupt clearing use.
+	LDR 	r2, =ulICCIAR
+	LDR		r0, [r2]
+
+	; Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
+	; future use.  _RB_ Does this ever actually need to be done provided the
+	; start of the stack is 8-byte aligned?
+	MOV		r2, sp
+	AND		r2, r2, #4
+	SUB		sp, sp, r2
+
+	; Call the interrupt handler.  r4 is pushed to maintain alignment.
+	PUSH	{r0-r4, lr}
+	LDR		r1, =vApplicationIRQHandler
+	BLX		r1
+	POP		{r0-r4, lr}
+	ADD		sp, sp, r2
+
+	CPSID 	i
+
+	; Write the value read from ICCIAR to ICCEOIR
+	LDR 	r4, =ulICCEOIR
+	STR		r0, [r4]
+
+	; Restore the old nesting count
+	STR		r1, [r3]
+
+	; A context switch is never performed if the nesting count is not 0
+	CMP		r1, #0
+	BNE		exit_without_switch
+
+	; Did the interrupt request a context switch?  r1 holds the address of
+	; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
+	; use.
+	LDR		r1, =ulPortYieldRequired
+	LDR		r0, [r1]
+	CMP		r0, #0
+	BNE		switch_before_exit
+
+exit_without_switch
+	; No context switch.  Restore used registers, LR_irq and SPSR before
+	; returning.
+	POP		{r0-r4, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	MOVS	PC, LR
+
+switch_before_exit
+	; A context swtich is to be performed.  Clear the context switch pending
+	; flag.
+	MOV		r0, #0
+	STR		r0, [r1]
+
+	; Restore used registers, LR-irq and SPSR before saving the context
+	; to the task stack.
+	POP		{r0-r4, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	portSAVE_CONTEXT
+
+	; Call the function that selects the new task to execute.
+	; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
+	; instructions, or 8 byte aligned stack allocated data.  LR does not need
+	; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway.
+	LDR		r0, =vTaskSwitchContext
+	BLX		r0
+
+	; Restore the context of, and branch to, the task selected to execute next.
+	portRESTORE_CONTEXT
+
+
+	END
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CA9/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CA9/portmacro.h
new file mode 100644
index 0000000..cf75bdc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CA9/portmacro.h
@@ -0,0 +1,163 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* Called at the end of an ISR that can cause a context switch. */
+#define portEND_SWITCHING_ISR( xSwitchRequired )\
+{												\
+extern uint32_t ulPortYieldRequired;			\
+												\
+	if( xSwitchRequired != pdFALSE )			\
+	{											\
+		ulPortYieldRequired = pdTRUE;			\
+	}											\
+}
+
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() __asm( "SWI 0" );
+
+
+/*-----------------------------------------------------------
+ * Critical section control
+ *----------------------------------------------------------*/
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+
+/* These macros do not globally disable/enable interrupts.  They do mask off
+interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+#define portDISABLE_INTERRUPTS()	ulPortSetInterruptMask()
+#define portENABLE_INTERRUPTS()		vPortClearInterruptMask( 0 )
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask(x)
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
+
+/* Prototype of the FreeRTOS tick handler.  This must be installed as the
+handler for whichever peripheral is used to generate the RTOS tick. */
+void FreeRTOS_Tick_Handler( void );
+
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+before any floating point instructions are executed. */
+void vPortTaskUsesFPU( void );
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( uxReadyPriorities ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+#define portNOP() __nop()
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CA9/portmacro.inc b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CA9/portmacro.inc
new file mode 100644
index 0000000..eb78401
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CA9/portmacro.inc
@@ -0,0 +1,120 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+SYS_MODE			EQU		0x1f
+SVC_MODE			EQU		0x13
+IRQ_MODE			EQU		0x12
+
+	IMPORT  ulCriticalNesting
+	IMPORT	pxCurrentTCB
+	IMPORT	ulPortTaskHasFPUContext
+	IMPORT  ulAsmAPIPriorityMask
+	IMPORT	ulICCPMR
+
+
+	MACRO
+	portSAVE_CONTEXT
+
+	; Save the LR and SPSR onto the system mode stack before switching to
+	; system mode to save the remaining system mode registers
+	SRSDB	sp!, #SYS_MODE
+	CPS		#SYS_MODE
+	PUSH	{R0-R12, R14}
+
+	; Push the critical nesting count
+	LDR		R2, =ulCriticalNesting
+	LDR		R1, [R2]
+	PUSH	{R1}
+
+	; Does the task have a floating point context that needs saving?  If
+	; ulPortTaskHasFPUContext is 0 then no.
+	LDR		R2, =ulPortTaskHasFPUContext
+	LDR		R3, [R2]
+	CMP		R3, #0
+
+	; Save the floating point context, if any
+	FMRXNE  R1,  FPSCR
+	VPUSHNE {D0-D15}
+	VPUSHNE	{D16-D31}
+	PUSHNE	{R1}
+
+	; Save ulPortTaskHasFPUContext itself
+	PUSH	{R3}
+
+	; Save the stack pointer in the TCB
+	LDR		R0, =pxCurrentTCB
+	LDR		R1, [R0]
+	STR		SP, [R1]
+
+	MEND
+
+; /**********************************************************************/
+
+	MACRO
+	portRESTORE_CONTEXT
+
+	; Set the SP to point to the stack of the task being restored.
+	LDR		R0, =pxCurrentTCB
+	LDR		R1, [R0]
+	LDR		SP, [R1]
+
+	; Is there a floating point context to restore?  If the restored
+	; ulPortTaskHasFPUContext is zero then no.
+	LDR		R0, =ulPortTaskHasFPUContext
+	POP		{R1}
+	STR		R1, [R0]
+	CMP		R1, #0
+
+	; Restore the floating point context, if any
+	POPNE	{R0}
+	VPOPNE	{D16-D31}
+	VPOPNE	{D0-D15}
+	VMSRNE  FPSCR, R0
+
+	; Restore the critical section nesting depth
+	LDR		R0, =ulCriticalNesting
+	POP		{R1}
+	STR		R1, [R0]
+
+	; Ensure the priority mask is correct for the critical nesting depth
+	LDR		R2, =ulICCPMR
+	CMP		R1, #0
+	MOVEQ	R4, #255
+	LDRNE	R4, =ulAsmAPIPriorityMask
+	STR		R4, [r2]
+
+	; Restore all system mode registers other than the SP (which is already
+	; being used)
+	POP		{R0-R12, R14}
+
+	; Return to the task code, loading CPSR on the way.
+	RFEIA	sp!
+
+	MEND
+
+	END
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM0/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM0/port.c
new file mode 100644
index 0000000..646dd8e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM0/port.c
@@ -0,0 +1,312 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM0 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to manipulate the NVIC. */
+#define portNVIC_SYSTICK_CTRL			( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD			( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE	( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL			( ( volatile uint32_t *) 0xe000ed04 )
+#define portNVIC_SYSPRI2			( ( volatile uint32_t *) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK		0x00000004
+#define portNVIC_SYSTICK_INT		0x00000002
+#define portNVIC_SYSTICK_ENABLE		0x00000001
+#define portNVIC_PENDSVSET			0x10000000
+#define portMIN_INTERRUPT_PRIORITY	( 255UL )
+#define portNVIC_PENDSV_PRI			( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI		( portMIN_INTERRUPT_PRIORITY << 24UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR			( 0x01000000 )
+
+/* Constants used with memory barrier intrinsics. */
+#define portSY_FULL_READ_WRITE		( 15 )
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void );
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* LR */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+	pxTopOfStack -= 8; /* R11..R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+	/* This function is no longer used, but retained for backward
+	compatibility. */
+}
+/*-----------------------------------------------------------*/
+
+__asm void prvPortStartFirstTask( void )
+{
+	extern pxCurrentTCB;
+
+	PRESERVE8
+
+	/* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
+	table offset register that can be used to locate the initial stack value.
+	Not all M0 parts have the application vector table at address 0. */
+
+	ldr	r3, =pxCurrentTCB	/* Obtain location of pxCurrentTCB. */
+	ldr r1, [r3]
+	ldr r0, [r1]			/* The first item in pxCurrentTCB is the task top of stack. */
+	adds r0, #32			/* Discard everything up to r0. */
+	msr psp, r0				/* This is now the new top of stack to use in the task. */
+	movs r0, #2				/* Switch to the psp stack. */
+	msr CONTROL, r0
+	isb
+	pop {r0-r5}				/* Pop the registers that are saved automatically. */
+	mov lr, r5				/* lr is now in r5. */
+	pop {r3}				/* The return address is now in r3. */
+	pop {r2}				/* Pop and discard the XPSR. */
+	cpsie i					/* The first task has its context and interrupts can be enabled. */
+	bx r3					/* Finally, jump to the user defined task code. */
+
+	ALIGN
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+	*(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
+	*(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Start the first task. */
+	prvPortStartFirstTask();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortYield( void )
+{
+	/* Set a PendSV to request a context switch. */
+	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+	/* Barriers are normally not required but do ensure the code is completely
+	within the specified behaviour for the architecture. */
+	__dsb( portSY_FULL_READ_WRITE );
+	__isb( portSY_FULL_READ_WRITE );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+	__dsb( portSY_FULL_READ_WRITE );
+	__isb( portSY_FULL_READ_WRITE );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+    uxCriticalNesting--;
+    if( uxCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+__asm uint32_t ulSetInterruptMaskFromISR( void )
+{
+	mrs r0, PRIMASK
+	cpsid i
+	bx lr
+}
+/*-----------------------------------------------------------*/
+
+__asm void vClearInterruptMaskFromISR( uint32_t ulMask )
+{
+	msr PRIMASK, r0
+	bx lr
+}
+/*-----------------------------------------------------------*/
+
+__asm void xPortPendSVHandler( void )
+{
+	extern vTaskSwitchContext
+	extern pxCurrentTCB
+
+	PRESERVE8
+
+	mrs r0, psp
+
+	ldr	r3, =pxCurrentTCB 	/* Get the location of the current TCB. */
+	ldr	r2, [r3]
+
+	subs r0, #32			/* Make space for the remaining low registers. */
+	str r0, [r2]			/* Save the new top of stack. */
+	stmia r0!, {r4-r7}		/* Store the low registers that are not saved automatically. */
+	mov r4, r8				/* Store the high registers. */
+	mov r5, r9
+	mov r6, r10
+	mov r7, r11
+	stmia r0!, {r4-r7}
+
+	push {r3, r14}
+	cpsid i
+	bl vTaskSwitchContext
+	cpsie i
+	pop {r2, r3}			/* lr goes in r3. r2 now holds tcb pointer. */
+
+	ldr r1, [r2]
+	ldr r0, [r1]			/* The first item in pxCurrentTCB is the task top of stack. */
+	adds r0, #16			/* Move to the high registers. */
+	ldmia r0!, {r4-r7}		/* Pop the high registers. */
+	mov r8, r4
+	mov r9, r5
+	mov r10, r6
+	mov r11, r7
+
+	msr psp, r0				/* Remember the new top of stack for the task. */
+
+	subs r0, #32			/* Go back for the low registers that are not automatically restored. */
+	ldmia r0!, {r4-r7}      /* Pop low registers.  */
+
+	bx r3
+	ALIGN
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+uint32_t ulPreviousMask;
+
+	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+void prvSetupTimerInterrupt( void )
+{
+	/* Stop and reset the SysTick. */
+	*(portNVIC_SYSTICK_CTRL) = 0UL;
+	*(portNVIC_SYSTICK_CURRENT_VALUE) = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	*(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	*(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM0/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM0/portmacro.h
new file mode 100644
index 0000000..44e7567
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM0/portmacro.h
@@ -0,0 +1,114 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+extern void vPortYield( void );
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portYIELD()					vPortYield()
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulSetInterruptMaskFromISR( void );
+extern void vClearInterruptMaskFromISR( uint32_t ulMask );
+
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()				__disable_irq()
+#define portENABLE_INTERRUPTS()					__enable_irq()
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#define portNOP()
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c
new file mode 100644
index 0000000..4a6fc12
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c
@@ -0,0 +1,698 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM3 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef configKERNEL_INTERRUPT_PRIORITY
+	#define configKERNEL_INTERRUPT_PRIORITY 255
+#endif
+
+#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
+	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+/* The __weak attribute does not work as you might expect with the Keil tools
+so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if
+the application writer wants to provide their own implementation of
+vPortSetupTimerInterrupt().  Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION
+is defined. */
+#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
+	#define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK					( 0xFFUL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR			( 0x01000000 )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR			( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void );
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvStartFirstTask( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* LR */
+
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+__asm void vPortSVCHandler( void )
+{
+	PRESERVE8
+
+	ldr	r3, =pxCurrentTCB	/* Restore the context. */
+	ldr r1, [r3]			/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+	ldr r0, [r1]			/* The first item in pxCurrentTCB is the task top of stack. */
+	ldmia r0!, {r4-r11}		/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+	msr psp, r0				/* Restore the task stack pointer. */
+	isb
+	mov r0, #0
+	msr	basepri, r0
+	orr r14, #0xd
+	bx r14
+}
+/*-----------------------------------------------------------*/
+
+__asm void prvStartFirstTask( void )
+{
+	PRESERVE8
+
+	/* Use the NVIC offset register to locate the stack. */
+	ldr r0, =0xE000ED08
+	ldr r0, [r0]
+	ldr r0, [r0]
+
+	/* Set the msp back to the start of the stack. */
+	msr msp, r0
+	/* Globally enable interrupts. */
+	cpsie i
+	cpsie f
+	dsb
+	isb
+	/* Call SVC to start the first task. */
+	svc 0
+	nop
+	nop
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* The kernel interrupt priority should be set to the lowest
+		priority. */
+		configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Start the first task. */
+	prvStartFirstTask();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+__asm void xPortPendSVHandler( void )
+{
+	extern uxCriticalNesting;
+	extern pxCurrentTCB;
+	extern vTaskSwitchContext;
+
+	PRESERVE8
+
+	mrs r0, psp
+	isb
+
+	ldr	r3, =pxCurrentTCB		/* Get the location of the current TCB. */
+	ldr	r2, [r3]
+
+	stmdb r0!, {r4-r11}			/* Save the remaining registers. */
+	str r0, [r2]				/* Save the new top of stack into the first member of the TCB. */
+
+	stmdb sp!, {r3, r14}
+	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+	msr basepri, r0
+	dsb
+	isb
+	bl vTaskSwitchContext
+	mov r0, #0
+	msr basepri, r0
+	ldmia sp!, {r3, r14}
+
+	ldr r1, [r3]
+	ldr r0, [r1]				/* The first item in pxCurrentTCB is the task top of stack. */
+	ldmia r0!, {r4-r11}			/* Pop the registers and the critical nesting count. */
+	msr psp, r0
+	isb
+	bx r14
+	nop
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
+	executes all interrupts must be unmasked.  There is therefore no need to
+	save and then restore the interrupt mask value as its value is already
+	known - therefore the slightly faster vPortRaiseBASEPRI() function is used
+	in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
+	vPortRaiseBASEPRI();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	vPortClearBASEPRIFromISR();
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE == 1 )
+
+	__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+	TickType_t xModifiableIdleTime;
+
+		/* Make sure the SysTick reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
+		is accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+		/* Calculate the reload value required to wait xExpectedIdleTime
+		tick periods.  -1 is used because this code will execute part way
+		through one of the tick periods. */
+		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+		if( ulReloadValue > ulStoppedTimerCompensation )
+		{
+			ulReloadValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Enter a critical section but don't use the taskENTER_CRITICAL()
+		method as that will mask interrupts that should exit sleep mode. */
+		__disable_irq();
+		__dsb( portSY_FULL_READ_WRITE );
+		__isb( portSY_FULL_READ_WRITE );
+
+		/* If a context switch is pending or a task is waiting for the scheduler
+		to be unsuspended then abandon the low power entry. */
+		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+		{
+			/* Restart from whatever is left in the count register to complete
+			this tick period. */
+			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Reset the reload register to the value required for normal tick
+			periods. */
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Re-enable interrupts - see comments above __disable_irq() call
+			above. */
+			__enable_irq();
+		}
+		else
+		{
+			/* Set the new reload value. */
+			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+			/* Clear the SysTick count flag and set the count value back to
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+			set its parameter to 0 to indicate that its implementation contains
+			its own wait for interrupt or wait for event instruction, and so wfi
+			should not be executed again.  However, the original expected idle
+			time variable must remain unmodified, so a copy is taken. */
+			xModifiableIdleTime = xExpectedIdleTime;
+			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+			if( xModifiableIdleTime > 0 )
+			{
+				__dsb( portSY_FULL_READ_WRITE );
+				__wfi();
+				__isb( portSY_FULL_READ_WRITE );
+			}
+			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+			/* Re-enable interrupts to allow the interrupt that brought the MCU
+			out of sleep mode to execute immediately.  see comments above
+			__disable_interrupt() call above. */
+			__enable_irq();
+			__dsb( portSY_FULL_READ_WRITE );
+			__isb( portSY_FULL_READ_WRITE );
+
+			/* Disable interrupts again because the clock is about to be stopped
+			and interrupts that execute while the clock is stopped will increase
+			any slippage between the time maintained by the RTOS and calendar
+			time. */
+			__disable_irq();
+			__dsb( portSY_FULL_READ_WRITE );
+			__isb( portSY_FULL_READ_WRITE );
+			
+			/* Disable the SysTick clock without reading the 
+			portNVIC_SYSTICK_CTRL_REG register to ensure the
+			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again, 
+			the time the SysTick is stopped for is accounted for as best it can 
+			be, but using the tickless mode will inevitably result in some tiny 
+			drift of the time maintained by the kernel with respect to calendar 
+			time*/
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+			/* Determine if the SysTick clock has already counted to zero and
+			been set back to the current reload value (the reload back being
+			correct for the entire expected idle time) or if the SysTick is yet
+			to count to zero (in which case an interrupt other than the SysTick
+			must have brought the system out of sleep mode). */
+			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			{
+				uint32_t ulCalculatedLoadValue;
+
+				/* The tick interrupt is already pending, and the SysTick count
+				reloaded with ulReloadValue.  Reset the
+				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+				period. */
+				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+				/* Don't allow a tiny value, or values that have somehow
+				underflowed because the post sleep hook did something
+				that took too long. */
+				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+				{
+					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+				}
+
+				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+				/* As the pending tick will be processed as soon as this
+				function exits, the tick value maintained by the tick is stepped
+				forward by one less than the time spent waiting. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				Work out how long the sleep lasted rounded to complete tick
+				periods (not the ulReload value which accounted for part
+				ticks). */
+				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+				/* How many complete tick periods passed while the processor
+				was waiting? */
+				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+				/* The reload value is set to whatever fraction of a single tick
+				period remains. */
+				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+			}
+
+			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+			value. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+			vTaskStepTick( ulCompleteTickPeriods );
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Exit with interrpts enabled. */
+			__enable_irq();
+		}
+	}
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the SysTick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+#if( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
+
+	void vPortSetupTimerInterrupt( void )
+	{
+		/* Calculate the constants required to configure the tick interrupt. */
+		#if( configUSE_TICKLESS_IDLE == 1 )
+		{
+			ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+			xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+			ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+		}
+		#endif /* configUSE_TICKLESS_IDLE */
+
+		/* Stop and clear the SysTick. */
+		portNVIC_SYSTICK_CTRL_REG = 0UL;
+		portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+		/* Configure SysTick to interrupt at the requested rate. */
+		portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+		portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+	}
+
+#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
+/*-----------------------------------------------------------*/
+
+__asm uint32_t vPortGetIPSR( void )
+{
+	PRESERVE8
+
+	mrs r0, ipsr
+	bx r14
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		ulCurrentInterrupt = vPortGetIPSR();
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredictable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h
new file mode 100644
index 0000000..90173ee
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h
@@ -0,0 +1,252 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+
+/* Constants used with memory barrier intrinsics. */
+#define portSY_FULL_READ_WRITE		( 15 )
+
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD()																\
+{																				\
+	/* Set a PendSV to request a context switch. */								\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
+																				\
+	/* Barriers are normally not required but do ensure the code is completely	\
+	within the specified behaviour for the architecture. */						\
+	__dsb( portSY_FULL_READ_WRITE );											\
+	__isb( portSY_FULL_READ_WRITE );											\
+}
+/*-----------------------------------------------------------*/
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()					vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
+
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/* Port specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
+
+#endif /* taskRECORD_READY_PRIORITY */
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE __inline
+
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE __forceinline
+#endif
+
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+{
+	__asm
+	{
+		/* Barrier instructions are not used as this function is only used to
+		lower the BASEPRI value. */
+		msr basepri, ulBASEPRI
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE void vPortRaiseBASEPRI( void )
+{
+uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+	__asm
+	{
+		/* Set BASEPRI to the max syscall priority to effect a critical
+		section. */
+		msr basepri, ulNewBASEPRI
+		dsb
+		isb
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+{
+	__asm
+	{
+		/* Set BASEPRI to 0 so no interrupts are masked.  This function is only
+		used to lower the mask in an interrupt, so memory barriers are not 
+		used. */
+		msr basepri, #0
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
+{
+uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+	__asm
+	{
+		/* Set BASEPRI to the max syscall priority to effect a critical
+		section. */
+		mrs ulReturn, basepri
+		msr basepri, ulNewBASEPRI
+		dsb
+		isb
+	}
+
+	return ulReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
+{
+uint32_t ulCurrentInterrupt;
+BaseType_t xReturn;
+
+	/* Obtain the number of the currently executing interrupt. */
+	__asm
+	{
+		mrs ulCurrentInterrupt, ipsr
+	}
+
+	if( ulCurrentInterrupt == 0 )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	return xReturn;
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
new file mode 100644
index 0000000..c5e47a5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
@@ -0,0 +1,788 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM4F port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __TARGET_FPU_VFP
+	#error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
+	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+/* The __weak attribute does not work as you might expect with the Keil tools
+so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if
+the application writer wants to provide their own implementation of
+vPortSetupTimerInterrupt().  Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION
+is defined. */
+#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
+	#define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
+r0p1 port. */
+#define portCPUID							( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
+#define portCORTEX_M7_r0p1_ID				( 0x410FC271UL )
+#define portCORTEX_M7_r0p0_ID				( 0x410FC270UL )
+
+#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK					( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR					( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS	( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR			( 0x01000000 )
+#define portINITIAL_EXC_RETURN		( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER		( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR	( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK		( ( StackType_t ) 0xfffffffeUL )
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void );
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvStartFirstTask( void );
+
+/*
+ * Functions defined in portasm.s to enable the VFP.
+ */
+static void prvEnableVFP( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+
+	/* Offset added to account for the way the MCU uses the stack on entry/exit
+	of interrupts, and to ensure alignment. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* LR */
+
+	/* Save code space by skipping register initialisation. */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+
+	/* A save method is being used that requires each task to maintain its
+	own exec return value. */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+__asm void vPortSVCHandler( void )
+{
+	PRESERVE8
+
+	/* Get the location of the current TCB. */
+	ldr	r3, =pxCurrentTCB
+	ldr r1, [r3]
+	ldr r0, [r1]
+	/* Pop the core registers. */
+	ldmia r0!, {r4-r11, r14}
+	msr psp, r0
+	isb
+	mov r0, #0
+	msr	basepri, r0
+	bx r14
+}
+/*-----------------------------------------------------------*/
+
+__asm void prvStartFirstTask( void )
+{
+	PRESERVE8
+
+	/* Use the NVIC offset register to locate the stack. */
+	ldr r0, =0xE000ED08
+	ldr r0, [r0]
+	ldr r0, [r0]
+	/* Set the msp back to the start of the stack. */
+	msr msp, r0
+	/* Clear the bit that indicates the FPU is in use in case the FPU was used
+	before the scheduler was started - which would otherwise result in the
+	unnecessary leaving of space in the SVC stack for lazy saving of FPU
+	registers. */
+	mov r0, #0
+	msr control, r0
+	/* Globally enable interrupts. */
+	cpsie i
+	cpsie f
+	dsb
+	isb
+	/* Call SVC to start the first task. */
+	svc 0
+	nop
+	nop
+}
+/*-----------------------------------------------------------*/
+
+__asm void prvEnableVFP( void )
+{
+	PRESERVE8
+
+	/* The FPU enable bits are in the CPACR. */
+	ldr.w r0, =0xE000ED88
+	ldr	r1, [r0]
+
+	/* Enable CP10 and CP11 coprocessors, then save back. */
+	orr	r1, r1, #( 0xf << 20 )
+	str r1, [r0]
+	bx	r14
+	nop
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+	/* This port can be used on all revisions of the Cortex-M7 core other than
+	the r0p1 parts.  r0p1 parts should use the port from the
+	/source/portable/GCC/ARM_CM7/r0p1 directory. */
+	configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
+	configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* The kernel interrupt priority should be set to the lowest
+		priority. */
+		configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Ensure the VFP is enabled - it should be anyway. */
+	prvEnableVFP();
+
+	/* Lazy save always. */
+	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+	/* Start the first task. */
+	prvStartFirstTask();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+__asm void xPortPendSVHandler( void )
+{
+	extern uxCriticalNesting;
+	extern pxCurrentTCB;
+	extern vTaskSwitchContext;
+
+	PRESERVE8
+
+	mrs r0, psp
+	isb
+	/* Get the location of the current TCB. */
+	ldr	r3, =pxCurrentTCB
+	ldr	r2, [r3]
+
+	/* Is the task using the FPU context?  If so, push high vfp registers. */
+	tst r14, #0x10
+	it eq
+	vstmdbeq r0!, {s16-s31}
+
+	/* Save the core registers. */
+	stmdb r0!, {r4-r11, r14}
+
+	/* Save the new top of stack into the first member of the TCB. */
+	str r0, [r2]
+
+	stmdb sp!, {r0, r3}
+	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+	msr basepri, r0
+	dsb
+	isb
+	bl vTaskSwitchContext
+	mov r0, #0
+	msr basepri, r0
+	ldmia sp!, {r0, r3}
+
+	/* The first item in pxCurrentTCB is the task top of stack. */
+	ldr r1, [r3]
+	ldr r0, [r1]
+
+	/* Pop the core registers. */
+	ldmia r0!, {r4-r11, r14}
+
+	/* Is the task using the FPU context?  If so, pop the high vfp registers
+	too. */
+	tst r14, #0x10
+	it eq
+	vldmiaeq r0!, {s16-s31}
+
+	msr psp, r0
+	isb
+	#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
+		#if WORKAROUND_PMU_CM001 == 1
+			push { r14 }
+			pop { pc }
+			nop
+		#endif
+	#endif
+
+	bx r14
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
+	executes all interrupts must be unmasked.  There is therefore no need to
+	save and then restore the interrupt mask value as its value is already
+	known - therefore the slightly faster vPortRaiseBASEPRI() function is used
+	in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
+	vPortRaiseBASEPRI();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	vPortClearBASEPRIFromISR();
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE == 1 )
+
+	__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+	TickType_t xModifiableIdleTime;
+
+		/* Make sure the SysTick reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
+		is accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+		/* Calculate the reload value required to wait xExpectedIdleTime
+		tick periods.  -1 is used because this code will execute part way
+		through one of the tick periods. */
+		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+		if( ulReloadValue > ulStoppedTimerCompensation )
+		{
+			ulReloadValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Enter a critical section but don't use the taskENTER_CRITICAL()
+		method as that will mask interrupts that should exit sleep mode. */
+		__disable_irq();
+		__dsb( portSY_FULL_READ_WRITE );
+		__isb( portSY_FULL_READ_WRITE );
+
+		/* If a context switch is pending or a task is waiting for the scheduler
+		to be unsuspended then abandon the low power entry. */
+		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+		{
+			/* Restart from whatever is left in the count register to complete
+			this tick period. */
+			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Reset the reload register to the value required for normal tick
+			periods. */
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Re-enable interrupts - see comments above __disable_irq() call
+			above. */
+			__enable_irq();
+		}
+		else
+		{
+			/* Set the new reload value. */
+			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+			/* Clear the SysTick count flag and set the count value back to
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+			set its parameter to 0 to indicate that its implementation contains
+			its own wait for interrupt or wait for event instruction, and so wfi
+			should not be executed again.  However, the original expected idle
+			time variable must remain unmodified, so a copy is taken. */
+			xModifiableIdleTime = xExpectedIdleTime;
+			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+			if( xModifiableIdleTime > 0 )
+			{
+				__dsb( portSY_FULL_READ_WRITE );
+				__wfi();
+				__isb( portSY_FULL_READ_WRITE );
+			}
+			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+			/* Re-enable interrupts to allow the interrupt that brought the MCU
+			out of sleep mode to execute immediately.  see comments above
+			__disable_interrupt() call above. */
+			__enable_irq();
+			__dsb( portSY_FULL_READ_WRITE );
+			__isb( portSY_FULL_READ_WRITE );
+
+			/* Disable interrupts again because the clock is about to be stopped
+			and interrupts that execute while the clock is stopped will increase
+			any slippage between the time maintained by the RTOS and calendar
+			time. */
+			__disable_irq();
+			__dsb( portSY_FULL_READ_WRITE );
+			__isb( portSY_FULL_READ_WRITE );
+
+			/* Disable the SysTick clock without reading the
+			portNVIC_SYSTICK_CTRL_REG register to ensure the
+			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+			the time the SysTick is stopped for is accounted for as best it can
+			be, but using the tickless mode will inevitably result in some tiny
+			drift of the time maintained by the kernel with respect to calendar
+			time*/
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+			/* Determine if the SysTick clock has already counted to zero and
+			been set back to the current reload value (the reload back being
+			correct for the entire expected idle time) or if the SysTick is yet
+			to count to zero (in which case an interrupt other than the SysTick
+			must have brought the system out of sleep mode). */
+			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			{
+				uint32_t ulCalculatedLoadValue;
+
+				/* The tick interrupt is already pending, and the SysTick count
+				reloaded with ulReloadValue.  Reset the
+				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+				period. */
+				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+				/* Don't allow a tiny value, or values that have somehow
+				underflowed because the post sleep hook did something
+				that took too long. */
+				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+				{
+					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+				}
+
+				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+				/* As the pending tick will be processed as soon as this
+				function exits, the tick value maintained by the tick is stepped
+				forward by one less than the time spent waiting. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				Work out how long the sleep lasted rounded to complete tick
+				periods (not the ulReload value which accounted for part
+				ticks). */
+				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+				/* How many complete tick periods passed while the processor
+				was waiting? */
+				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+				/* The reload value is set to whatever fraction of a single tick
+				period remains. */
+				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+			}
+
+			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+			value. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+			vTaskStepTick( ulCompleteTickPeriods );
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Exit with interrpts enabled. */
+			__enable_irq();
+		}
+	}
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the SysTick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+#if( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
+
+	void vPortSetupTimerInterrupt( void )
+	{
+		/* Calculate the constants required to configure the tick interrupt. */
+		#if( configUSE_TICKLESS_IDLE == 1 )
+		{
+			ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+			xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+			ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+		}
+		#endif /* configUSE_TICKLESS_IDLE */
+
+		/* Stop and clear the SysTick. */
+		portNVIC_SYSTICK_CTRL_REG = 0UL;
+		portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+		/* Configure SysTick to interrupt at the requested rate. */
+		portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+		portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+	}
+
+#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
+/*-----------------------------------------------------------*/
+
+__asm uint32_t vPortGetIPSR( void )
+{
+	PRESERVE8
+
+	mrs r0, ipsr
+	bx r14
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		ulCurrentInterrupt = vPortGetIPSR();
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredictable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h
new file mode 100644
index 0000000..90173ee
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h
@@ -0,0 +1,252 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+
+/* Constants used with memory barrier intrinsics. */
+#define portSY_FULL_READ_WRITE		( 15 )
+
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD()																\
+{																				\
+	/* Set a PendSV to request a context switch. */								\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
+																				\
+	/* Barriers are normally not required but do ensure the code is completely	\
+	within the specified behaviour for the architecture. */						\
+	__dsb( portSY_FULL_READ_WRITE );											\
+	__isb( portSY_FULL_READ_WRITE );											\
+}
+/*-----------------------------------------------------------*/
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()					vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
+
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/* Port specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
+
+#endif /* taskRECORD_READY_PRIORITY */
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE __inline
+
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE __forceinline
+#endif
+
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+{
+	__asm
+	{
+		/* Barrier instructions are not used as this function is only used to
+		lower the BASEPRI value. */
+		msr basepri, ulBASEPRI
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE void vPortRaiseBASEPRI( void )
+{
+uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+	__asm
+	{
+		/* Set BASEPRI to the max syscall priority to effect a critical
+		section. */
+		msr basepri, ulNewBASEPRI
+		dsb
+		isb
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+{
+	__asm
+	{
+		/* Set BASEPRI to 0 so no interrupts are masked.  This function is only
+		used to lower the mask in an interrupt, so memory barriers are not 
+		used. */
+		msr basepri, #0
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
+{
+uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+	__asm
+	{
+		/* Set BASEPRI to the max syscall priority to effect a critical
+		section. */
+		mrs ulReturn, basepri
+		msr basepri, ulNewBASEPRI
+		dsb
+		isb
+	}
+
+	return ulReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
+{
+uint32_t ulCurrentInterrupt;
+BaseType_t xReturn;
+
+	/* Obtain the number of the currently executing interrupt. */
+	__asm
+	{
+		mrs ulCurrentInterrupt, ipsr
+	}
+
+	if( ulCurrentInterrupt == 0 )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	return xReturn;
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/port.c
new file mode 100644
index 0000000..3f299f1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/port.c
@@ -0,0 +1,867 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM3 port.
+ *----------------------------------------------------------*/
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __TARGET_FPU_VFP
+	#error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Constants required to access and manipulate the NVIC. */
+#define portNVIC_SYSTICK_CTRL_REG				( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG				( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG		( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG					( *	( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSPRI1_REG					( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
+#define portNVIC_SYS_CTRL_STATE_REG				( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
+#define portNVIC_MEM_FAULT_ENABLE				( 1UL << 16UL )
+
+/* Constants required to access and manipulate the MPU. */
+#define portMPU_TYPE_REG						( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_REGION_BASE_ADDRESS_REG			( * ( ( volatile uint32_t * ) 0xe000ed9C ) )
+#define portMPU_REGION_ATTRIBUTE_REG			( * ( ( volatile uint32_t * ) 0xe000edA0 ) )
+#define portMPU_CTRL_REG						( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portEXPECTED_MPU_TYPE_VALUE				( 8UL << 8UL ) /* 8 regions, unified. */
+#define portMPU_ENABLE							( 0x01UL )
+#define portMPU_BACKGROUND_ENABLE				( 1UL << 2UL )
+#define portPRIVILEGED_EXECUTION_START_ADDRESS	( 0UL )
+#define portMPU_REGION_VALID					( 0x10UL )
+#define portMPU_REGION_ENABLE					( 0x01UL )
+#define portPERIPHERALS_START_ADDRESS			0x40000000UL
+#define portPERIPHERALS_END_ADDRESS				0x5FFFFFFFUL
+
+/* Constants required to access and manipulate the SysTick. */
+#define portNVIC_SYSTICK_CLK					( 0x00000004UL )
+#define portNVIC_SYSTICK_INT					( 0x00000002UL )
+#define portNVIC_SYSTICK_ENABLE					( 0x00000001UL )
+#define portNVIC_PENDSV_PRI						( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portNVIC_SVC_PRI						( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR								( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS				( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR						( 0x01000000UL )
+#define portINITIAL_EXC_RETURN					( 0xfffffffdUL )
+#define portINITIAL_CONTROL_IF_UNPRIVILEGED		( 0x03 )
+#define portINITIAL_CONTROL_IF_PRIVILEGED		( 0x02 )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Offsets in the stack to the parameters when inside the SVC handler. */
+#define portOFFSET_TO_PC						( 6 )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable.  Note this is not saved as part of the task context as context
+switches can only occur when uxCriticalNesting is zero. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Configure a number of standard MPU regions that are used by all tasks.
+ */
+static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvStartFirstTask( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the smallest MPU region size that a given number of bytes will fit
+ * into.  The region size is returned as the value that should be programmed
+ * into the region attribute register for that region.
+ */
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
+
+/*
+ * Standard FreeRTOS exception handlers.
+ */
+void xPortPendSVHandler( void ) PRIVILEGED_FUNCTION;
+void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
+void vPortSVCHandler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Starts the scheduler by restoring the context of the first task to run.
+ */
+static void prvRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * C portion of the SVC handler.  The SVC handler is split between an asm entry
+ * and a C wrapper for simplicity of coding and maintenance.
+ */
+void prvSVCHandler( uint32_t *pulRegisters ) __attribute__((used)) PRIVILEGED_FUNCTION;
+
+/*
+ * Function to enable the VFP.
+ */
+static void vPortEnableVFP( void );
+
+/*
+ * Utility function.
+ */
+static uint32_t prvPortGetIPSR( void );
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void );
+
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = 0;	/* LR */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+
+	/* A save method is being used that requires each task to maintain its
+	own exec return value. */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+	pxTopOfStack -= 9;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	if( xRunPrivileged == pdTRUE )
+	{
+		*pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
+	}
+	else
+	{
+		*pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
+	}
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void prvSVCHandler( uint32_t *pulParam )
+{
+uint8_t ucSVCNumber;
+uint32_t ulReg;
+
+	/* The stack contains: r0, r1, r2, r3, r12, r14, the return address and
+	xPSR.  The first argument (r0) is pulParam[ 0 ]. */
+	ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];
+	switch( ucSVCNumber )
+	{
+		case portSVC_START_SCHEDULER	:	portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
+											prvRestoreContextOfFirstTask();
+											break;
+
+		case portSVC_YIELD				:	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+											/* Barriers are normally not required
+											but do ensure the code is completely
+											within the specified behaviour for the
+											architecture. */
+											__asm volatile( "dsb" );
+											__asm volatile( "isb" );
+
+											break;
+
+		case portSVC_RAISE_PRIVILEGE	:	__asm
+											{
+												mrs ulReg, control	/* Obtain current control value. */
+												bic ulReg, #1		/* Set privilege bit. */
+												msr control, ulReg	/* Write back new control value. */
+											}
+											break;
+
+		default							:	/* Unknown SVC call. */
+											break;
+	}
+}
+/*-----------------------------------------------------------*/
+
+__asm void vPortSVCHandler( void )
+{
+	extern prvSVCHandler
+
+	PRESERVE8
+
+	/* Assumes psp was in use. */
+	#ifndef USE_PROCESS_STACK	/* Code should not be required if a main() is using the process stack. */
+		tst lr, #4
+		ite eq
+		mrseq r0, msp
+		mrsne r0, psp
+	#else
+		mrs r0, psp
+	#endif
+		b prvSVCHandler
+}
+/*-----------------------------------------------------------*/
+
+__asm void prvRestoreContextOfFirstTask( void )
+{
+	PRESERVE8
+
+	ldr r0, =0xE000ED08				/* Use the NVIC offset register to locate the stack. */
+	ldr r0, [r0]
+	ldr r0, [r0]
+	msr msp, r0						/* Set the msp back to the start of the stack. */
+	ldr	r3, =pxCurrentTCB			/* Restore the context. */
+	ldr r1, [r3]
+	ldr r0, [r1]					/* The first item in the TCB is the task top of stack. */
+	add r1, r1, #4					/* Move onto the second item in the TCB... */
+	ldr r2, =0xe000ed9c				/* Region Base Address register. */
+	ldmia r1!, {r4-r11}				/* Read 4 sets of MPU registers. */
+	stmia r2!, {r4-r11}				/* Write 4 sets of MPU registers. */
+	ldmia r0!, {r3-r11, r14}	/* Pop the registers that are not automatically saved on exception entry. */
+	msr control, r3
+	msr psp, r0						/* Restore the task stack pointer. */
+	mov r0, #0
+	msr	basepri, r0
+	bx r14
+	nop
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See
+	http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+	configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the same priority as the kernel, and the SVC
+	handler higher priority so it can be used to exit a critical section (where
+	lower priorities are masked). */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Configure the regions in the MPU that are common to all tasks. */
+	prvSetupMPU();
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Ensure the VFP is enabled - it should be anyway. */
+	vPortEnableVFP();
+
+	/* Lazy save always. */
+	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+	/* Start the first task. */
+	prvStartFirstTask();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+__asm void prvStartFirstTask( void )
+{
+	PRESERVE8
+
+	/* Use the NVIC offset register to locate the stack. */
+	ldr r0, =0xE000ED08
+	ldr r0, [r0]
+	ldr r0, [r0]
+	/* Set the msp back to the start of the stack. */
+	msr msp, r0
+	/* Clear the bit that indicates the FPU is in use in case the FPU was used
+	before the scheduler was started - which would otherwise result in the
+	unnecessary leaving of space in the SVC stack for lazy saving of FPU
+	registers. */
+	mov r0, #0
+	msr control, r0
+	/* Globally enable interrupts. */
+	cpsie i
+	cpsie f
+	dsb
+	isb
+	svc portSVC_START_SCHEDULER	/* System call to start first task. */
+	nop
+	nop
+}
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+	vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+__asm void xPortPendSVHandler( void )
+{
+	extern uxCriticalNesting;
+	extern pxCurrentTCB;
+	extern vTaskSwitchContext;
+
+	PRESERVE8
+
+	mrs r0, psp
+
+	ldr r3, =pxCurrentTCB			/* Get the location of the current TCB. */
+	ldr r2, [r3]
+
+	tst r14, #0x10					/* Is the task using the FPU context?  If so, push high vfp registers. */
+	it eq
+	vstmdbeq r0!, {s16-s31}
+
+	mrs r1, control
+	stmdb r0!, {r1, r4-r11, r14}	/* Save the remaining registers. */
+	str r0, [r2]					/* Save the new top of stack into the first member of the TCB. */
+
+	stmdb sp!, {r0, r3}
+	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+	msr basepri, r0
+	dsb
+	isb
+	bl vTaskSwitchContext
+	mov r0, #0
+	msr basepri, r0
+	ldmia sp!, {r0, r3}
+									/* Restore the context. */
+	ldr r1, [r3]
+	ldr r0, [r1]					/* The first item in the TCB is the task top of stack. */
+	add r1, r1, #4					/* Move onto the second item in the TCB... */
+	ldr r2, =0xe000ed9c				/* Region Base Address register. */
+	ldmia r1!, {r4-r11}				/* Read 4 sets of MPU registers. */
+	stmia r2!, {r4-r11}				/* Write 4 sets of MPU registers. */
+	ldmia r0!, {r3-r11, r14}		/* Pop the registers that are not automatically saved on exception entry. */
+	msr control, r3
+
+	tst r14, #0x10					/* Is the task using the FPU context?  If so, pop the high vfp registers too. */
+	it eq
+	vldmiaeq r0!, {s16-s31}
+
+	msr psp, r0
+	bx r14
+	nop
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+uint32_t ulDummy;
+
+	ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+	/* Reset the SysTick. */
+	portNVIC_SYSTICK_CTRL_REG = 0UL;
+	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+__asm void vPortSwitchToUserMode( void )
+{
+	PRESERVE8
+
+	mrs r0, control
+	orr r0, #1
+	msr control, r0
+	bx r14
+}
+/*-----------------------------------------------------------*/
+
+__asm void vPortEnableVFP( void )
+{
+	PRESERVE8
+
+	ldr.w r0, =0xE000ED88		/* The FPU enable bits are in the CPACR. */
+	ldr r1, [r0]
+
+	orr r1, r1, #( 0xf << 20 )	/* Enable CP10 and CP11 coprocessors, then save back. */
+	str r1, [r0]
+	bx r14
+	nop
+	nop
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupMPU( void )
+{
+extern uint32_t __privileged_functions_end__;
+extern uint32_t __FLASH_segment_start__;
+extern uint32_t __FLASH_segment_end__;
+extern uint32_t __privileged_data_start__;
+extern uint32_t __privileged_data_end__;
+
+	/* Check the expected MPU is present. */
+	if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+	{
+		/* First setup the entire flash for unprivileged read only access. */
+		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
+											( portMPU_REGION_VALID ) |
+											( portUNPRIVILEGED_FLASH_REGION );
+
+		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_READ_ONLY ) |
+										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+										( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
+										( portMPU_REGION_ENABLE );
+
+		/* Setup the first 16K for privileged only access (even though less
+		than 10K is actually being used).  This is where the kernel code is
+		placed. */
+		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
+											( portMPU_REGION_VALID ) |
+											( portPRIVILEGED_FLASH_REGION );
+
+		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
+										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+										( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
+										( portMPU_REGION_ENABLE );
+
+		/* Setup the privileged data RAM region.  This is where the kernel data
+		is placed. */
+		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
+											( portMPU_REGION_VALID ) |
+											( portPRIVILEGED_RAM_REGION );
+
+		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+										prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
+										( portMPU_REGION_ENABLE );
+
+		/* By default allow everything to access the general peripherals.  The
+		system peripherals and registers are protected. */
+		portMPU_REGION_BASE_ADDRESS_REG =	( portPERIPHERALS_START_ADDRESS ) |
+											( portMPU_REGION_VALID ) |
+											( portGENERAL_PERIPHERALS_REGION );
+
+		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
+										( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
+										( portMPU_REGION_ENABLE );
+
+		/* Enable the memory fault exception. */
+		portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
+
+		/* Enable the MPU with the background region configured. */
+		portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
+{
+uint32_t ulRegionSize, ulReturnValue = 4;
+
+	/* 32 is the smallest region size, 31 is the largest valid value for
+	ulReturnValue. */
+	for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
+	{
+		if( ulActualSizeInBytes <= ulRegionSize )
+		{
+			break;
+		}
+		else
+		{
+			ulReturnValue++;
+		}
+	}
+
+	/* Shift the code by one before returning so it can be written directly
+	into the the correct bit position of the attribute register. */
+	return ( ulReturnValue << 1UL );
+}
+/*-----------------------------------------------------------*/
+
+__asm BaseType_t xIsPrivileged( void )
+{
+	PRESERVE8
+
+	mrs r0, control		/* r0 = CONTROL. */
+	tst r0, #1			/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	ite ne
+	movne r0, #0		/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	moveq r0, #1		/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	bx lr				/* Return. */
+}
+/*-----------------------------------------------------------*/
+
+__asm void vResetPrivilege( void )
+{
+	PRESERVE8
+
+	mrs r0, control		/* r0 = CONTROL. */
+	orrs r0, #1			/* r0 = r0 | 1. */
+	msr control, r0		/* CONTROL = r0. */
+	bx lr				/* Return. */
+}
+/*-----------------------------------------------------------*/
+
+void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+{
+extern uint32_t __SRAM_segment_start__;
+extern uint32_t __SRAM_segment_end__;
+extern uint32_t __privileged_data_start__;
+extern uint32_t __privileged_data_end__;
+
+
+int32_t lIndex;
+uint32_t ul;
+
+	if( xRegions == NULL )
+	{
+		/* No MPU regions are specified so allow access to all RAM. */
+		xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
+				( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
+				( portMPU_REGION_VALID ) |
+				( portSTACK_REGION );
+
+		xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
+				( portMPU_REGION_READ_WRITE ) |
+				( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+				( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
+				( portMPU_REGION_ENABLE );
+
+		/* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
+		just removed the privileged only parameters. */
+		xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
+				( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
+				( portMPU_REGION_VALID ) |
+				( portSTACK_REGION + 1 );
+
+		xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
+				( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+				( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+				prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
+				( portMPU_REGION_ENABLE );
+
+		/* Invalidate all other regions. */
+		for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+		{
+			xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+			xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
+		}
+	}
+	else
+	{
+		/* This function is called automatically when the task is created - in
+		which case the stack region parameters will be valid.  At all other
+		times the stack parameters will not be valid and it is assumed that the
+		stack region has already been configured. */
+		if( ulStackDepth > 0 )
+		{
+			/* Define the region that allows access to the stack. */
+			xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
+					( ( uint32_t ) pxBottomOfStack ) |
+					( portMPU_REGION_VALID ) |
+					( portSTACK_REGION ); /* Region number. */
+
+			xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
+					( portMPU_REGION_READ_WRITE ) | /* Read and write. */
+					( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
+					( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+					( portMPU_REGION_ENABLE );
+		}
+
+		lIndex = 0;
+
+		for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+		{
+			if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
+			{
+				/* Translate the generic region definition contained in
+				xRegions into the CM3 specific MPU settings that are then
+				stored in xMPUSettings. */
+				xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
+						( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
+						( portMPU_REGION_VALID ) |
+						( portSTACK_REGION + ul ); /* Region number. */
+
+				xMPUSettings->xRegion[ ul ].ulRegionAttribute =
+						( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
+						( xRegions[ lIndex ].ulParameters ) |
+						( portMPU_REGION_ENABLE );
+			}
+			else
+			{
+				/* Invalidate the region. */
+				xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+				xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
+			}
+
+			lIndex++;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+__asm uint32_t prvPortGetIPSR( void )
+{
+	PRESERVE8
+
+	mrs r0, ipsr
+	bx r14
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		ulCurrentInterrupt = prvPortGetIPSR();
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredicable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h
new file mode 100644
index 0000000..3ec3c1f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h
@@ -0,0 +1,309 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* MPU specific constants. */
+#define portUSING_MPU_WRAPPERS		1
+#define portPRIVILEGE_BIT			( 0x80000000UL )
+
+#define portMPU_REGION_READ_WRITE				( 0x03UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY		( 0x05UL << 24UL )
+#define portMPU_REGION_READ_ONLY				( 0x06UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE	( 0x01UL << 24UL )
+#define portMPU_REGION_CACHEABLE_BUFFERABLE		( 0x07UL << 16UL )
+#define portMPU_REGION_EXECUTE_NEVER			( 0x01UL << 28UL )
+
+#define portUNPRIVILEGED_FLASH_REGION		( 0UL )
+#define portPRIVILEGED_FLASH_REGION			( 1UL )
+#define portPRIVILEGED_RAM_REGION			( 2UL )
+#define portGENERAL_PERIPHERALS_REGION		( 3UL )
+#define portSTACK_REGION					( 4UL )
+#define portFIRST_CONFIGURABLE_REGION		( 5UL )
+#define portLAST_CONFIGURABLE_REGION		( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS		( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS				( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+void vPortSwitchToUserMode( void );
+#define portSWITCH_TO_USER_MODE()	vPortSwitchToUserMode()
+
+typedef struct MPU_REGION_REGISTERS
+{
+	uint32_t ulRegionBaseAddress;
+	uint32_t ulRegionAttribute;
+} xMPU_REGION_REGISTERS;
+
+/* Plus 1 to create space for the stack region. */
+typedef struct MPU_SETTINGS
+{
+	xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
+} xMPU_SETTINGS;
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+
+/* Constants used with memory barrier intrinsics. */
+#define portSY_FULL_READ_WRITE		( 15 )
+
+/*-----------------------------------------------------------*/
+
+/* SVC numbers for various services. */
+#define portSVC_START_SCHEDULER				0
+#define portSVC_YIELD						1
+#define portSVC_RAISE_PRIVILEGE				2
+
+/* Scheduler utilities. */
+
+#define portYIELD()				__asm{ SVC portSVC_YIELD }
+#define portYIELD_WITHIN_API() 													\
+{																				\
+	/* Set a PendSV to request a context switch. */								\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
+																				\
+	/* Barriers are normally not required but do ensure the code is completely	\
+	within the specified behaviour for the architecture. */						\
+	__dsb( portSY_FULL_READ_WRITE );											\
+	__isb( portSY_FULL_READ_WRITE );											\
+}
+/*-----------------------------------------------------------*/
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()					vPortSetBASEPRI(0)
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE __inline
+
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE __forceinline
+#endif
+/*-----------------------------------------------------------*/
+
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED()			xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ */
+#define portRAISE_PRIVILEGE()		__asm { svc portSVC_RAISE_PRIVILEGE }
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE()		vResetPrivilege()
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+{
+	__asm
+	{
+		/* Barrier instructions are not used as this function is only used to
+		lower the BASEPRI value. */
+		msr basepri, ulBASEPRI
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE void vPortRaiseBASEPRI( void )
+{
+uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+	__asm
+	{
+		/* Set BASEPRI to the max syscall priority to effect a critical
+		section. */
+		msr basepri, ulNewBASEPRI
+		dsb
+		isb
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+{
+	__asm
+	{
+		/* Set BASEPRI to 0 so no interrupts are masked.  This function is only
+		used to lower the mask in an interrupt, so memory barriers are not
+		used. */
+		msr basepri, #0
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
+{
+uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+	__asm
+	{
+		/* Set BASEPRI to the max syscall priority to effect a critical
+		section. */
+		mrs ulReturn, basepri
+		msr basepri, ulNewBASEPRI
+		dsb
+		isb
+	}
+
+	return ulReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
+{
+uint32_t ulCurrentInterrupt;
+BaseType_t xReturn;
+
+	/* Obtain the number of the currently executing interrupt. */
+	__asm
+	{
+		mrs ulCurrentInterrupt, ipsr
+	}
+
+	if( ulCurrentInterrupt == 0 )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM7/ReadMe.txt b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM7/ReadMe.txt
new file mode 100644
index 0000000..b3950da
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM7/ReadMe.txt
@@ -0,0 +1,18 @@
+There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers.
+The best option depends on the revision of the ARM Cortex-M7 core in use.  The
+revision is specified by an 'r' number, and a 'p' number, so will look something
+like 'r0p1'.  Check the documentation for the microcontroller in use to find the 
+revision of the Cortex-M7 core used in that microcontroller.  If in doubt, use 
+the FreeRTOS port provided specifically for r0p1 revisions, as that can be used
+with all core revisions.
+
+The first option is to use the ARM Cortex-M4F port, and the second option is to
+use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround.
+
+If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be
+used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in 
+the /FreeRTOS/Source/portable/RVDS/ARM_CM4F directory.
+
+If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM
+Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1
+directory.
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/port.c
new file mode 100644
index 0000000..2c00cf5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/port.c
@@ -0,0 +1,774 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM4F port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __TARGET_FPU_VFP
+	#error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
+	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+/* The __weak attribute does not work as you might expect with the Keil tools
+so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if
+the application writer wants to provide their own implementation of
+vPortSetupTimerInterrupt().  Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION
+is defined. */
+#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
+	#define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK					( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR					( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS	( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR			( 0x01000000 )
+#define portINITIAL_EXC_RETURN		( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER		( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR	( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK		( ( StackType_t ) 0xfffffffeUL )
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void );
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvStartFirstTask( void );
+
+/*
+ * Functions defined in portasm.s to enable the VFP.
+ */
+static void prvEnableVFP( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+
+	/* Offset added to account for the way the MCU uses the stack on entry/exit
+	of interrupts, and to ensure alignment. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* LR */
+
+	/* Save code space by skipping register initialisation. */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+
+	/* A save method is being used that requires each task to maintain its
+	own exec return value. */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+__asm void vPortSVCHandler( void )
+{
+	PRESERVE8
+
+	/* Get the location of the current TCB. */
+	ldr	r3, =pxCurrentTCB
+	ldr r1, [r3]
+	ldr r0, [r1]
+	/* Pop the core registers. */
+	ldmia r0!, {r4-r11, r14}
+	msr psp, r0
+	isb
+	mov r0, #0
+	msr	basepri, r0
+	bx r14
+}
+/*-----------------------------------------------------------*/
+
+__asm void prvStartFirstTask( void )
+{
+	PRESERVE8
+
+	/* Use the NVIC offset register to locate the stack. */
+	ldr r0, =0xE000ED08
+	ldr r0, [r0]
+	ldr r0, [r0]
+	/* Set the msp back to the start of the stack. */
+	msr msp, r0
+	/* Clear the bit that indicates the FPU is in use in case the FPU was used
+	before the scheduler was started - which would otherwise result in the
+	unnecessary leaving of space in the SVC stack for lazy saving of FPU
+	registers. */
+	mov r0, #0
+	msr control, r0
+	/* Globally enable interrupts. */
+	cpsie i
+	cpsie f
+	dsb
+	isb
+	/* Call SVC to start the first task. */
+	svc 0
+	nop
+	nop
+}
+/*-----------------------------------------------------------*/
+
+__asm void prvEnableVFP( void )
+{
+	PRESERVE8
+
+	/* The FPU enable bits are in the CPACR. */
+	ldr.w r0, =0xE000ED88
+	ldr	r1, [r0]
+
+	/* Enable CP10 and CP11 coprocessors, then save back. */
+	orr	r1, r1, #( 0xf << 20 )
+	str r1, [r0]
+	bx	r14
+	nop
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* The kernel interrupt priority should be set to the lowest
+		priority. */
+		configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Ensure the VFP is enabled - it should be anyway. */
+	prvEnableVFP();
+
+	/* Lazy save always. */
+	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+	/* Start the first task. */
+	prvStartFirstTask();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+__asm void xPortPendSVHandler( void )
+{
+	extern uxCriticalNesting;
+	extern pxCurrentTCB;
+	extern vTaskSwitchContext;
+
+	PRESERVE8
+
+	mrs r0, psp
+	isb
+	/* Get the location of the current TCB. */
+	ldr	r3, =pxCurrentTCB
+	ldr	r2, [r3]
+
+	/* Is the task using the FPU context?  If so, push high vfp registers. */
+	tst r14, #0x10
+	it eq
+	vstmdbeq r0!, {s16-s31}
+
+	/* Save the core registers. */
+	stmdb r0!, {r4-r11, r14}
+
+	/* Save the new top of stack into the first member of the TCB. */
+	str r0, [r2]
+
+	stmdb sp!, {r0, r3}
+	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+	cpsid i
+	msr basepri, r0
+	dsb
+	isb
+	cpsie i
+	bl vTaskSwitchContext
+	mov r0, #0
+	msr basepri, r0
+	ldmia sp!, {r0, r3}
+
+	/* The first item in pxCurrentTCB is the task top of stack. */
+	ldr r1, [r3]
+	ldr r0, [r1]
+
+	/* Pop the core registers. */
+	ldmia r0!, {r4-r11, r14}
+
+	/* Is the task using the FPU context?  If so, pop the high vfp registers
+	too. */
+	tst r14, #0x10
+	it eq
+	vldmiaeq r0!, {s16-s31}
+
+	msr psp, r0
+	isb
+	#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
+		#if WORKAROUND_PMU_CM001 == 1
+			push { r14 }
+			pop { pc }
+			nop
+		#endif
+	#endif
+
+	bx r14
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
+	executes all interrupts must be unmasked.  There is therefore no need to
+	save and then restore the interrupt mask value as its value is already
+	known - therefore the slightly faster vPortRaiseBASEPRI() function is used
+	in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
+	vPortRaiseBASEPRI();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	vPortClearBASEPRIFromISR();
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE == 1 )
+
+	__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+	TickType_t xModifiableIdleTime;
+
+		/* Make sure the SysTick reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
+		is accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+		/* Calculate the reload value required to wait xExpectedIdleTime
+		tick periods.  -1 is used because this code will execute part way
+		through one of the tick periods. */
+		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+		if( ulReloadValue > ulStoppedTimerCompensation )
+		{
+			ulReloadValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Enter a critical section but don't use the taskENTER_CRITICAL()
+		method as that will mask interrupts that should exit sleep mode. */
+		__disable_irq();
+		__dsb( portSY_FULL_READ_WRITE );
+		__isb( portSY_FULL_READ_WRITE );
+
+		/* If a context switch is pending or a task is waiting for the scheduler
+		to be unsuspended then abandon the low power entry. */
+		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+		{
+			/* Restart from whatever is left in the count register to complete
+			this tick period. */
+			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Reset the reload register to the value required for normal tick
+			periods. */
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Re-enable interrupts - see comments above __disable_irq() call
+			above. */
+			__enable_irq();
+		}
+		else
+		{
+			/* Set the new reload value. */
+			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+			/* Clear the SysTick count flag and set the count value back to
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+			set its parameter to 0 to indicate that its implementation contains
+			its own wait for interrupt or wait for event instruction, and so wfi
+			should not be executed again.  However, the original expected idle
+			time variable must remain unmodified, so a copy is taken. */
+			xModifiableIdleTime = xExpectedIdleTime;
+			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+			if( xModifiableIdleTime > 0 )
+			{
+				__dsb( portSY_FULL_READ_WRITE );
+				__wfi();
+				__isb( portSY_FULL_READ_WRITE );
+			}
+			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+			/* Re-enable interrupts to allow the interrupt that brought the MCU
+			out of sleep mode to execute immediately.  see comments above
+			__disable_interrupt() call above. */
+			__enable_irq();
+			__dsb( portSY_FULL_READ_WRITE );
+			__isb( portSY_FULL_READ_WRITE );
+
+			/* Disable interrupts again because the clock is about to be stopped
+			and interrupts that execute while the clock is stopped will increase
+			any slippage between the time maintained by the RTOS and calendar
+			time. */
+			__disable_irq();
+			__dsb( portSY_FULL_READ_WRITE );
+			__isb( portSY_FULL_READ_WRITE );
+
+			/* Disable the SysTick clock without reading the
+			portNVIC_SYSTICK_CTRL_REG register to ensure the
+			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+			the time the SysTick is stopped for is accounted for as best it can
+			be, but using the tickless mode will inevitably result in some tiny
+			drift of the time maintained by the kernel with respect to calendar
+			time*/
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+			/* Determine if the SysTick clock has already counted to zero and
+			been set back to the current reload value (the reload back being
+			correct for the entire expected idle time) or if the SysTick is yet
+			to count to zero (in which case an interrupt other than the SysTick
+			must have brought the system out of sleep mode). */
+			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			{
+				uint32_t ulCalculatedLoadValue;
+
+				/* The tick interrupt is already pending, and the SysTick count
+				reloaded with ulReloadValue.  Reset the
+				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+				period. */
+				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+				/* Don't allow a tiny value, or values that have somehow
+				underflowed because the post sleep hook did something
+				that took too long. */
+				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+				{
+					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+				}
+
+				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+				/* As the pending tick will be processed as soon as this
+				function exits, the tick value maintained by the tick is stepped
+				forward by one less than the time spent waiting. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				Work out how long the sleep lasted rounded to complete tick
+				periods (not the ulReload value which accounted for part
+				ticks). */
+				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+				/* How many complete tick periods passed while the processor
+				was waiting? */
+				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+				/* The reload value is set to whatever fraction of a single tick
+				period remains. */
+				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+			}
+
+			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+			value. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+			vTaskStepTick( ulCompleteTickPeriods );
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Exit with interrpts enabled. */
+			__enable_irq();
+		}
+	}
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the SysTick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+#if( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
+
+	void vPortSetupTimerInterrupt( void )
+	{
+		/* Calculate the constants required to configure the tick interrupt. */
+		#if( configUSE_TICKLESS_IDLE == 1 )
+		{
+			ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+			xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+			ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+		}
+		#endif /* configUSE_TICKLESS_IDLE */
+
+		/* Stop and clear the SysTick. */
+		portNVIC_SYSTICK_CTRL_REG = 0UL;
+		portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+		/* Configure SysTick to interrupt at the requested rate. */
+		portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+		portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+	}
+
+#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
+/*-----------------------------------------------------------*/
+
+__asm uint32_t vPortGetIPSR( void )
+{
+	PRESERVE8
+
+	mrs r0, ipsr
+	bx r14
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		ulCurrentInterrupt = vPortGetIPSR();
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredictable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h
new file mode 100644
index 0000000..30ef19f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h
@@ -0,0 +1,256 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+
+/* Constants used with memory barrier intrinsics. */
+#define portSY_FULL_READ_WRITE		( 15 )
+
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD()																\
+{																				\
+	/* Set a PendSV to request a context switch. */								\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
+																				\
+	/* Barriers are normally not required but do ensure the code is completely	\
+	within the specified behaviour for the architecture. */						\
+	__dsb( portSY_FULL_READ_WRITE );											\
+	__isb( portSY_FULL_READ_WRITE );											\
+}
+/*-----------------------------------------------------------*/
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()					vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )	vPortSetBASEPRI( x )
+
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/* Port specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
+
+#endif /* taskRECORD_READY_PRIORITY */
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE __inline
+
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE __forceinline
+#endif
+
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+{
+	__asm
+	{
+		/* Barrier instructions are not used as this function is only used to
+		lower the BASEPRI value. */
+		msr basepri, ulBASEPRI
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE void vPortRaiseBASEPRI( void )
+{
+uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+	__asm
+	{
+		/* Set BASEPRI to the max syscall priority to effect a critical
+		section. */
+		cpsid i
+		msr basepri, ulNewBASEPRI
+		dsb
+		isb
+		cpsie i
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+{
+	__asm
+	{
+		/* Set BASEPRI to 0 so no interrupts are masked.  This function is only
+		used to lower the mask in an interrupt, so memory barriers are not 
+		used. */
+		msr basepri, #0
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
+{
+uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+	__asm
+	{
+		/* Set BASEPRI to the max syscall priority to effect a critical
+		section. */
+		mrs ulReturn, basepri
+		cpsid i
+		msr basepri, ulNewBASEPRI
+		dsb
+		isb
+		cpsie i
+	}
+
+	return ulReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
+{
+uint32_t ulCurrentInterrupt;
+BaseType_t xReturn;
+
+	/* Obtain the number of the currently executing interrupt. */
+	__asm
+	{
+		mrs ulCurrentInterrupt, ipsr
+	}
+
+	if( ulCurrentInterrupt == 0 )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	return xReturn;
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX100/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX100/port.c
new file mode 100644
index 0000000..88291a8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX100/port.c
@@ -0,0 +1,646 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the RX100 port.
+ *----------------------------------------------------------*/
+
+/* Standard C includes. */
+#include "limits.h"
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#include "iodefine.h"
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
+
+/* The peripheral clock is divided by this value before being supplying the
+CMT. */
+#if ( configUSE_TICKLESS_IDLE == 0 )
+	/* If tickless idle is not used then the divisor can be fixed. */
+	#define portCLOCK_DIVISOR	8UL
+#elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
+	#define portCLOCK_DIVISOR	512UL
+#elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
+	#define portCLOCK_DIVISOR	128UL
+#elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
+	#define portCLOCK_DIVISOR	32UL
+#else
+	#define portCLOCK_DIVISOR	8UL
+#endif
+
+
+/* Keys required to lock and unlock access to certain system registers
+respectively. */
+#define portUNLOCK_KEY		0xA50B
+#define portLOCK_KEY		0xA500
+
+/*-----------------------------------------------------------*/
+
+/* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
+ and therefore installed in the vector table, when the FreeRTOS code is built
+as a library. */
+extern BaseType_t vSoftwareInterruptEntry;
+const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+static void prvStartFirstTask( void );
+
+/*
+ * Software interrupt handler.  Performs the actual context switch (saving and
+ * restoring of registers).  Written in asm code as direct register access is
+ * required.
+ */
+static void prvYieldHandler( void );
+
+/*
+ * The entry point for the software interrupt handler.  This is the function
+ * that calls the inline asm function prvYieldHandler().  It is installed in
+ * the vector table, but the code that installs it is in prvYieldHandler rather
+ * than using a #pragma.
+ */
+void vSoftwareInterruptISR( void );
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick using the CMT.
+ * The application writer can define configSETUP_TICK_INTERRUPT() (in
+ * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
+ * in place of prvSetupTimerInterrupt().
+ */
+static void prvSetupTimerInterrupt( void );
+#ifndef configSETUP_TICK_INTERRUPT
+	/* The user has not provided their own tick interrupt configuration so use
+    the definition in this file (which uses the interval timer). */
+	#define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
+#endif /* configSETUP_TICK_INTERRUPT */
+
+/*
+ * Called after the sleep mode registers have been configured, prvSleep()
+ * executes the pre and post sleep macros, and actually calls the wait
+ * instruction.
+ */
+#if configUSE_TICKLESS_IDLE == 1
+	static void prvSleep( TickType_t xExpectedIdleTime );
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*-----------------------------------------------------------*/
+
+/* These is accessed by the inline assembler functions. */
+extern void *pxCurrentTCB;
+extern void vTaskSwitchContext( void );
+
+/*-----------------------------------------------------------*/
+
+/* Calculate how many clock increments make up a single tick period. */
+static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
+
+#if configUSE_TICKLESS_IDLE == 1
+
+	/* Holds the maximum number of ticks that can be suppressed - which is
+	basically how far into the future an interrupt can be generated. Set
+	during initialisation.  This is the maximum possible value that the
+	compare match register can hold divided by ulMatchValueForOneTick. */
+	static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
+
+	/* Flag set from the tick interrupt to allow the sleep processing to know if
+	sleep mode was exited because of a tick interrupt, or an interrupt
+	generated by something else. */
+	static volatile uint32_t ulTickFlag = pdFALSE;
+
+	/* The CMT counter is stopped temporarily each time it is re-programmed.
+	The following constant offsets the CMT counter match value by the number of
+	CMT	counts that would typically be missed while the counter was stopped to
+	compensate for the lost time.  The large difference between the divided CMT
+	clock and the CPU clock means it is likely ulStoppedTimerCompensation will
+	equal zero - and be optimised away. */
+	static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Offset to end up on 8 byte boundary. */
+	pxTopOfStack--;
+
+	/* R0 is not included as it is the stack pointer. */
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+    *pxTopOfStack = 0x00;
+	pxTopOfStack--;
+ 	*pxTopOfStack = portINITIAL_PSW;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;
+
+	/* When debugging it can be useful if every register is set to a known
+	value.  Otherwise code space can be saved by just setting the registers
+	that need to be set. */
+	#ifdef USE_FULL_REGISTER_INITIALISATION
+	{
+		pxTopOfStack--;
+		*pxTopOfStack = 0x12345678;	/* r15. */
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaabbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xdddddddd;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xcccccccc;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xbbbbbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaaaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x99999999;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x88888888;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x77777777;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x66666666;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x55555555;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x44444444;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x33333333;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x22222222;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		/* Leave space for the registers that will get popped from the stack
+		when the task first starts executing. */
+		pxTopOfStack -= 15;
+	}
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x12345678; /* Accumulator. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x87654321; /* Accumulator. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Use pxCurrentTCB just so it does not get optimised away. */
+	if( pxCurrentTCB != NULL )
+	{
+		/* Call an application function to set up the timer that will generate
+		the tick interrupt.  This way the application can decide which
+		peripheral to use.  If tickless mode is used then the default
+		implementation defined in this file (which uses CMT0) should not be
+		overridden. */
+		configSETUP_TICK_INTERRUPT();
+
+		/* Enable the software interrupt. */
+		_IEN( _ICU_SWINT ) = 1;
+
+		/* Ensure the software interrupt is clear. */
+		_IR( _ICU_SWINT ) = 0;
+
+		/* Ensure the software interrupt is set to the kernel priority. */
+		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+		/* Start the first task. */
+		prvStartFirstTask();
+	}
+
+	/* Execution should not reach here as the tasks are now running!
+	prvSetupTimerInterrupt() is called here to prevent the compiler outputting
+	a warning about a statically declared function not being referenced in the
+	case that the application writer has provided their own tick interrupt
+	configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
+	their own routine will be called in place of prvSetupTimerInterrupt()). */
+	prvSetupTimerInterrupt();
+
+	/* Just to make sure the function is not optimised away. */
+	( void ) vSoftwareInterruptISR();
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+#pragma inline_asm prvStartFirstTask
+static void prvStartFirstTask( void )
+{
+	/* When starting the scheduler there is nothing that needs moving to the
+	interrupt stack because the function is not called from an interrupt.
+	Just ensure the current stack is the user stack. */
+	SETPSW	U
+
+	/* Obtain the location of the stack associated with which ever task
+	pxCurrentTCB is currently pointing to. */
+	MOV.L	#_pxCurrentTCB, R15
+	MOV.L	[R15], R15
+	MOV.L	[R15], R0
+
+	/* Restore the registers from the stack of the task pointed to by
+	pxCurrentTCB. */
+    POP		R15
+    MVTACLO	R15 		/* Accumulator low 32 bits. */
+    POP		R15
+    MVTACHI	R15 		/* Accumulator high 32 bits. */
+    POPM	R1-R15 		/* R1 to R15 - R0 is not included as it is the SP. */
+    RTE					/* This pops the remaining registers. */
+    NOP
+    NOP
+}
+/*-----------------------------------------------------------*/
+
+#pragma interrupt ( prvTickISR( vect = configTICK_VECTOR, enable ) )
+void prvTickISR( void )
+{
+	/* Increment the tick, and perform any processing the new tick value
+	necessitates. */
+	set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			taskYIELD();
+		}
+	}
+	set_ipl( configKERNEL_INTERRUPT_PRIORITY );
+
+	#if configUSE_TICKLESS_IDLE == 1
+	{
+		/* The CPU woke because of a tick. */
+		ulTickFlag = pdTRUE;
+
+		/* If this is the first tick since exiting tickless mode then the CMT
+		compare match value needs resetting. */
+		CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+void vSoftwareInterruptISR( void )
+{
+	prvYieldHandler();
+}
+/*-----------------------------------------------------------*/
+
+#pragma inline_asm prvYieldHandler
+static void prvYieldHandler( void )
+{
+	/* Re-enable interrupts. */
+	SETPSW	I
+
+	/* Move the data that was automatically pushed onto the interrupt stack
+	when the interrupt occurred from the interrupt stack to the user stack.
+
+	R15 is saved before it is clobbered. */
+	PUSH.L	R15
+
+	/* Read the user stack pointer. */
+	MVFC	USP, R15
+
+	/* Move the address down to the data being moved. */
+	SUB		#12, R15
+	MVTC	R15, USP
+
+	/* Copy the data across. */
+	MOV.L	[ R0 ], [ R15 ] ; R15
+	MOV.L 	4[ R0 ], 4[ R15 ]  ; PC
+	MOV.L	8[ R0 ], 8[ R15 ]  ; PSW
+
+	/* Move the interrupt stack pointer to its new correct position. */
+	ADD	#12, R0
+
+	/* All the rest of the registers are saved directly to the user stack. */
+	SETPSW	U
+
+	/* Save the rest of the general registers (R15 has been saved already). */
+	PUSHM	R1-R14
+
+	/* Save the accumulator. */
+	MVFACHI	R15
+	PUSH.L	R15
+	MVFACMI	R15	; Middle order word.
+	SHLL	#16, R15 ; Shifted left as it is restored to the low order word.
+	PUSH.L	R15
+
+	/* Save the stack pointer to the TCB. */
+	MOV.L	#_pxCurrentTCB, R15
+	MOV.L	[ R15 ], R15
+	MOV.L	R0, [ R15 ]
+
+	/* Ensure the interrupt mask is set to the syscall priority while the
+	kernel structures are being accessed. */
+	MVTIPL	#configMAX_SYSCALL_INTERRUPT_PRIORITY
+
+	/* Select the next task to run. */
+	BSR.A	_vTaskSwitchContext
+
+	/* Reset the interrupt mask as no more data structure access is
+	required. */
+	MVTIPL	#configKERNEL_INTERRUPT_PRIORITY
+
+	/* Load the stack pointer of the task that is now selected as the Running
+	state task from its TCB. */
+	MOV.L	#_pxCurrentTCB,R15
+	MOV.L	[ R15 ], R15
+	MOV.L	[ R15 ], R0
+
+	/* Restore the context of the new task.  The PSW (Program Status Word) and
+	PC will be popped by the RTE instruction. */
+	POP		R15
+	MVTACLO	R15
+	POP		R15
+	MVTACHI	R15
+	POPM	R1-R15
+	RTE
+	NOP
+	NOP
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( pxCurrentTCB == NULL );
+
+	/* The following line is just to prevent the symbol getting optimised away. */
+	( void ) vTaskSwitchContext();
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+	/* Unlock. */
+	SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+
+	/* Enable CMT0. */
+	MSTP( CMT0 ) = 0;
+
+	/* Lock again. */
+	SYSTEM.PRCR.WORD = portLOCK_KEY;
+
+	/* Interrupt on compare match. */
+	CMT0.CMCR.BIT.CMIE = 1;
+
+	/* Set the compare match value. */
+	CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
+
+	/* Divide the PCLK. */
+	#if portCLOCK_DIVISOR == 512
+	{
+		CMT0.CMCR.BIT.CKS = 3;
+	}
+	#elif portCLOCK_DIVISOR == 128
+	{
+		CMT0.CMCR.BIT.CKS = 2;
+	}
+	#elif portCLOCK_DIVISOR == 32
+	{
+		CMT0.CMCR.BIT.CKS = 1;
+	}
+	#elif portCLOCK_DIVISOR == 8
+	{
+		CMT0.CMCR.BIT.CKS = 0;
+	}
+	#else
+	{
+		#error Invalid portCLOCK_DIVISOR setting
+	}
+	#endif
+
+
+	/* Enable the interrupt... */
+	_IEN( _CMT0_CMI0 ) = 1;
+
+	/* ...and set its priority to the application defined kernel priority. */
+	_IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
+
+	/* Start the timer. */
+	CMT.CMSTR0.BIT.STR0 = 1;
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_TICKLESS_IDLE == 1
+
+	static void prvSleep( TickType_t xExpectedIdleTime )
+	{
+		/* Allow the application to define some pre-sleep processing. */
+		configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
+
+		/* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
+		means the application defined code has already executed the WAIT
+		instruction. */
+		if( xExpectedIdleTime > 0 )
+		{
+			wait();
+		}
+
+		/* Allow the application to define some post sleep processing. */
+		configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if configUSE_TICKLESS_IDLE == 1
+
+	void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
+	eSleepModeStatus eSleepAction;
+
+		/* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
+
+		/* Make sure the CMT reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Calculate the reload value required to wait xExpectedIdleTime tick
+		periods. */
+		ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
+		if( ulMatchValue > ulStoppedTimerCompensation )
+		{
+			/* Compensate for the fact that the CMT is going to be stopped
+			momentarily. */
+			ulMatchValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Stop the CMT momentarily.  The time the CMT is stopped for is
+		accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		CMT.CMSTR0.BIT.STR0 = 0;
+		while( CMT.CMSTR0.BIT.STR0 == 1 )
+		{
+			/* Nothing to do here. */
+		}
+
+		/* Critical section using the global interrupt bit as the i bit is
+		automatically reset by the WAIT instruction. */
+		clrpsw_i();
+
+		/* The tick flag is set to false before sleeping.  If it is true when
+		sleep mode is exited then sleep mode was probably exited because the
+		tick was suppressed for the entire xExpectedIdleTime period. */
+		ulTickFlag = pdFALSE;
+
+		/* If a context switch is pending then abandon the low power entry as
+		the context switch might have been pended by an external interrupt that
+		requires processing. */
+		eSleepAction = eTaskConfirmSleepModeStatus();
+		if( eSleepAction == eAbortSleep )
+		{
+			/* Restart tick. */
+			CMT.CMSTR0.BIT.STR0 = 1;
+			setpsw_i();
+		}
+		else if( eSleepAction == eNoTasksWaitingTimeout )
+		{
+		    /* Protection off. */
+		    SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+
+		    /* Ready for software standby with all clocks stopped. */
+			SYSTEM.SBYCR.BIT.SSBY = 1;
+
+		    /* Protection on. */
+		    SYSTEM.PRCR.WORD = portLOCK_KEY;
+
+			/* Sleep until something happens.  Calling prvSleep() will
+			automatically reset the i bit in the PSW. */
+			prvSleep( xExpectedIdleTime );
+
+			/* Restart the CMT. */
+			CMT.CMSTR0.BIT.STR0 = 1;
+		}
+		else
+		{
+		    /* Protection off. */
+		    SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+
+		    /* Ready for deep sleep mode. */
+			SYSTEM.MSTPCRC.BIT.DSLPE = 1;
+			SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
+			SYSTEM.SBYCR.BIT.SSBY = 0;
+
+		    /* Protection on. */
+		    SYSTEM.PRCR.WORD = portLOCK_KEY;
+
+		    /* Adjust the match value to take into account that the current
+			time slice is already partially complete. */
+			ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
+			CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+
+			/* Restart the CMT to count up to the new match value. */
+			CMT0.CMCNT = 0;
+			CMT.CMSTR0.BIT.STR0 = 1;
+
+			/* Sleep until something happens.  Calling prvSleep() will
+			automatically reset the i bit in the PSW. */
+			prvSleep( xExpectedIdleTime );
+
+			/* Stop CMT.  Again, the time the SysTick is stopped for is
+			accounted for as best it can be, but using the tickless mode will
+			inevitably result in some tiny drift of the time maintained by the
+			kernel with	respect to calendar time. */
+			CMT.CMSTR0.BIT.STR0 = 0;
+			while( CMT.CMSTR0.BIT.STR0 == 1 )
+			{
+				/* Nothing to do here. */
+			}
+
+			ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
+
+			if( ulTickFlag != pdFALSE )
+			{
+				/* The tick interrupt has already executed, although because
+				this function is called with the scheduler suspended the actual
+				tick processing will not occur until after this function has
+				exited.  Reset the match value with whatever remains of this
+				tick period. */
+				ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
+				CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+
+				/* The tick interrupt handler will already have pended the tick
+				processing in the kernel.  As the pending tick will be
+				processed as soon as this function exits, the tick value
+				maintained by the tick is stepped forward by one less than the
+				time spent sleeping.  The actual stepping of the tick appears
+				later in this function. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				How	many complete tick periods passed while the processor was
+				sleeping? */
+				ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
+
+				/* The match value is set to whatever fraction of a single tick
+				period remains. */
+				ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
+				CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+			}
+
+			/* Restart the CMT so it runs up to the match value.  The match value
+			will get set to the value required to generate exactly one tick period
+			the next time the CMT interrupt executes. */
+			CMT0.CMCNT = 0;
+			CMT.CMSTR0.BIT.STR0 = 1;
+
+			/* Wind the tick forward by the number of tick periods that the CPU
+			remained in a low power state. */
+			vTaskStepTick( ulCompleteTickPeriods );
+		}
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX100/port_asm.src b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX100/port_asm.src
new file mode 100644
index 0000000..6a154ea
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX100/port_asm.src
@@ -0,0 +1,41 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+		.GLB	_vSoftwareInterruptISR
+                .GLB    _vSoftwareInterruptEntry
+
+		.SECTION   P,CODE
+
+_vSoftwareInterruptEntry:
+
+	BRA	_vSoftwareInterruptISR
+
+		.RVECTOR	27, _vSoftwareInterruptEntry
+
+		.END
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX100/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX100/portmacro.h
new file mode 100644
index 0000000..fd0f197
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX100/portmacro.h
@@ -0,0 +1,151 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Hardware specifics. */
+#include "machine.h"
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions - these are a bit legacy and not really used now, other
+than portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT				8	/* Could make four, according to manual. */
+#define portSTACK_GROWTH				-1
+#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()						nop()
+
+#pragma inline_asm vPortYield
+static void vPortYield( void )
+{
+	/* Save clobbered register - may not actually be necessary if inline asm
+	functions are considered to use the same rules as function calls by the
+	compiler. */
+	PUSH.L R5
+	/* Set ITU SWINTR. */
+	MOV.L #872E0H, R5
+	MOV.B #1, [R5]
+	/* Read back to ensure the value is taken before proceeding. */
+	MOV.L [R5], R5
+	/* Restore clobbered register to its previous value. */
+	POP R5
+}
+#define portYIELD()	vPortYield()
+#define portYIELD_FROM_ISR( x )	if( x != pdFALSE ) { portYIELD(); }
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() 	set_ipl( ( long ) 0 )
+#ifdef configASSERT
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+	#define portDISABLE_INTERRUPTS() 	if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#else
+	#define portDISABLE_INTERRUPTS() 	set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+#define portSET_INTERRUPT_MASK_FROM_ISR() ( UBaseType_t ) get_ipl(); set_ipl( ( signed long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( signed long ) uxSavedInterruptStatus )
+
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#if configUSE_TICKLESS_IDLE == 1
+	#ifndef portSUPPRESS_TICKS_AND_SLEEP
+		extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+		#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+	#endif
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX200/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX200/port.c
new file mode 100644
index 0000000..e3f24bd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX200/port.c
@@ -0,0 +1,324 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the RX200 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#include "iodefine.h"
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
+
+/*-----------------------------------------------------------*/
+
+/* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
+ and therefore installed in the vector table, when the FreeRTOS code is built
+as a library. */
+extern BaseType_t vSoftwareInterruptEntry;
+const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+static void prvStartFirstTask( void );
+
+/*
+ * Software interrupt handler.  Performs the actual context switch (saving and
+ * restoring of registers).  Written in asm code as direct register access is
+ * required.
+ */
+static void prvYieldHandler( void );
+
+/*
+ * The entry point for the software interrupt handler.  This is the function
+ * that calls the inline asm function prvYieldHandler().  It is installed in
+ * the vector table, but the code that installs it is in prvYieldHandler rather
+ * than using a #pragma.
+ */
+void vSoftwareInterruptISR( void );
+
+/*-----------------------------------------------------------*/
+
+/* This is accessed by the inline assembler functions so is file scope for
+convenience. */
+extern void *pxCurrentTCB;
+extern void vTaskSwitchContext( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Offset to end up on 8 byte boundary. */
+	pxTopOfStack--;
+
+	/* R0 is not included as it is the stack pointer. */
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+    *pxTopOfStack = 0x00;
+	pxTopOfStack--;
+ 	*pxTopOfStack = portINITIAL_PSW;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;
+
+	/* When debugging it can be useful if every register is set to a known
+	value.  Otherwise code space can be saved by just setting the registers
+	that need to be set. */
+	#ifdef USE_FULL_REGISTER_INITIALISATION
+	{
+		pxTopOfStack--;
+		*pxTopOfStack = 0x12345678;	/* r15. */
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaabbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xdddddddd;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xcccccccc;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xbbbbbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaaaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x99999999;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x88888888;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x77777777;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x66666666;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x55555555;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x44444444;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x33333333;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x22222222;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		pxTopOfStack -= 15;
+	}
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x12345678; /* Accumulator. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x87654321; /* Accumulator. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vApplicationSetupTimerInterrupt( void );
+
+	/* Use pxCurrentTCB just so it does not get optimised away. */
+	if( pxCurrentTCB != NULL )
+	{
+		/* Call an application function to set up the timer that will generate the
+		tick interrupt.  This way the application can decide which peripheral to
+		use.  A demo application is provided to show a suitable example. */
+		vApplicationSetupTimerInterrupt();
+
+		/* Enable the software interrupt. */
+		_IEN( _ICU_SWINT ) = 1;
+
+		/* Ensure the software interrupt is clear. */
+		_IR( _ICU_SWINT ) = 0;
+
+		/* Ensure the software interrupt is set to the kernel priority. */
+		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+		/* Start the first task. */
+		prvStartFirstTask();
+	}
+
+	/* Just to make sure the function is not optimised away. */
+	( void ) vSoftwareInterruptISR();
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+#pragma inline_asm prvStartFirstTask
+static void prvStartFirstTask( void )
+{
+	/* When starting the scheduler there is nothing that needs moving to the
+	interrupt stack because the function is not called from an interrupt.
+	Just ensure the current stack is the user stack. */
+	SETPSW	U
+
+	/* Obtain the location of the stack associated with which ever task
+	pxCurrentTCB is currently pointing to. */
+	MOV.L	#_pxCurrentTCB, R15
+	MOV.L	[R15], R15
+	MOV.L	[R15], R0
+
+	/* Restore the registers from the stack of the task pointed to by
+	pxCurrentTCB. */
+    POP		R15
+    MVTACLO	R15 		/* Accumulator low 32 bits. */
+    POP		R15
+    MVTACHI	R15 		/* Accumulator high 32 bits. */
+    POPM	R1-R15 		/* R1 to R15 - R0 is not included as it is the SP. */
+    RTE					/* This pops the remaining registers. */
+    NOP
+    NOP
+}
+/*-----------------------------------------------------------*/
+
+#pragma interrupt ( vTickISR( vect = _VECT( configTICK_VECTOR ), enable ) )
+void vTickISR( void )
+{
+	/* Increment the tick, and perform any processing the new tick value
+	necessitates. */
+	set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			taskYIELD();
+		}
+	}
+	set_ipl( configKERNEL_INTERRUPT_PRIORITY );
+}
+/*-----------------------------------------------------------*/
+
+void vSoftwareInterruptISR( void )
+{
+	prvYieldHandler();
+}
+/*-----------------------------------------------------------*/
+
+#pragma inline_asm prvYieldHandler
+static void prvYieldHandler( void )
+{
+	/* Re-enable interrupts. */
+	SETPSW	I
+
+	/* Move the data that was automatically pushed onto the interrupt stack when
+	the interrupt occurred from the interrupt stack to the user stack.
+
+	R15 is saved before it is clobbered. */
+	PUSH.L	R15
+
+	/* Read the user stack pointer. */
+	MVFC	USP, R15
+
+	/* Move the address down to the data being moved. */
+	SUB		#12, R15
+	MVTC	R15, USP
+
+	/* Copy the data across. */
+	MOV.L	[ R0 ], [ R15 ] ; R15
+	MOV.L 	4[ R0 ], 4[ R15 ]  ; PC
+	MOV.L	8[ R0 ], 8[ R15 ]  ; PSW
+
+	/* Move the interrupt stack pointer to its new correct position. */
+	ADD	#12, R0
+
+	/* All the rest of the registers are saved directly to the user stack. */
+	SETPSW	U
+
+	/* Save the rest of the general registers (R15 has been saved already). */
+	PUSHM	R1-R14
+
+	/* Save the accumulator. */
+	MVFACHI	R15
+	PUSH.L	R15
+	MVFACMI	R15	; Middle order word.
+	SHLL	#16, R15 ; Shifted left as it is restored to the low order word.
+	PUSH.L	R15
+
+	/* Save the stack pointer to the TCB. */
+	MOV.L	#_pxCurrentTCB, R15
+	MOV.L	[ R15 ], R15
+	MOV.L	R0, [ R15 ]
+
+	/* Ensure the interrupt mask is set to the syscall priority while the kernel
+	structures are being accessed. */
+	MVTIPL	#configMAX_SYSCALL_INTERRUPT_PRIORITY
+
+	/* Select the next task to run. */
+	BSR.A	_vTaskSwitchContext
+
+	/* Reset the interrupt mask as no more data structure access is required. */
+	MVTIPL	#configKERNEL_INTERRUPT_PRIORITY
+
+	/* Load the stack pointer of the task that is now selected as the Running
+	state task from its TCB. */
+	MOV.L	#_pxCurrentTCB,R15
+	MOV.L	[ R15 ], R15
+	MOV.L	[ R15 ], R0
+
+	/* Restore the context of the new task.  The PSW (Program Status Word) and
+	PC will be popped by the RTE instruction. */
+	POP		R15
+	MVTACLO	R15
+	POP		R15
+	MVTACHI	R15
+	POPM	R1-R15
+	RTE
+	NOP
+	NOP
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( pxCurrentTCB == NULL );
+
+	/* The following line is just to prevent the symbol getting optimised away. */
+	( void ) vTaskSwitchContext();
+}
+/*-----------------------------------------------------------*/
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX200/port_asm.src b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX200/port_asm.src
new file mode 100644
index 0000000..6a154ea
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX200/port_asm.src
@@ -0,0 +1,41 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+		.GLB	_vSoftwareInterruptISR
+                .GLB    _vSoftwareInterruptEntry
+
+		.SECTION   P,CODE
+
+_vSoftwareInterruptEntry:
+
+	BRA	_vSoftwareInterruptISR
+
+		.RVECTOR	27, _vSoftwareInterruptEntry
+
+		.END
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX200/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX200/portmacro.h
new file mode 100644
index 0000000..84ab8c3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX200/portmacro.h
@@ -0,0 +1,141 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Hardware specifics. */
+#include "machine.h"
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT				8	/* Could make four, according to manual. */
+#define portSTACK_GROWTH				-1
+#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()						nop()
+
+#pragma inline_asm vPortYield
+static void vPortYield( void )
+{
+	/* Save clobbered register - may not actually be necessary if inline asm
+	functions are considered to use the same rules as function calls by the
+	compiler. */
+	PUSH.L R5
+	/* Set ITU SWINTR. */
+	MOV.L #553696, R5
+	MOV.B #1, [R5]
+	/* Read back to ensure the value is taken before proceeding. */
+	MOV.L [R5], R5
+	/* Restore clobbered register to its previous value. */
+	POP R5
+}
+#define portYIELD()	vPortYield()
+#define portYIELD_FROM_ISR( x )	if( x != pdFALSE ) portYIELD()
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() 	set_ipl( ( long ) 0 )
+#ifdef configASSERT
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+	#define portDISABLE_INTERRUPTS() 	if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#else
+	#define portDISABLE_INTERRUPTS() 	set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+#define portSET_INTERRUPT_MASK_FROM_ISR() get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX600/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX600/port.c
new file mode 100644
index 0000000..1ffdd2d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX600/port.c
@@ -0,0 +1,329 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the RX600 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#include "iodefine.h"
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
+
+/*-----------------------------------------------------------*/
+
+/* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
+ and therefore installed in the vector table, when the FreeRTOS code is built
+as a library. */
+extern BaseType_t vSoftwareInterruptEntry;
+const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+static void prvStartFirstTask( void );
+
+/*
+ * Software interrupt handler.  Performs the actual context switch (saving and
+ * restoring of registers).  Written in asm code as direct register access is
+ * required.
+ */
+static void prvYieldHandler( void );
+
+/*
+ * The entry point for the software interrupt handler.  This is the function
+ * that calls the inline asm function prvYieldHandler().  It is installed in
+ * the vector table, but the code that installs it is in prvYieldHandler rather
+ * than using a #pragma.
+ */
+void vSoftwareInterruptISR( void );
+
+/*-----------------------------------------------------------*/
+
+/* This is accessed by the inline assembler functions so is file scope for
+convenience. */
+extern void *pxCurrentTCB;
+extern void vTaskSwitchContext( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* R0 is not included as it is the stack pointer. */
+
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+ 	*pxTopOfStack = portINITIAL_PSW;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;
+
+	/* When debugging it can be useful if every register is set to a known
+	value.  Otherwise code space can be saved by just setting the registers
+	that need to be set. */
+	#ifdef USE_FULL_REGISTER_INITIALISATION
+	{
+		pxTopOfStack--;
+		*pxTopOfStack = 0xffffffff;	/* r15. */
+		pxTopOfStack--;
+		*pxTopOfStack = 0xeeeeeeee;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xdddddddd;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xcccccccc;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xbbbbbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaaaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x99999999;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x88888888;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x77777777;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x66666666;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x55555555;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x44444444;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x33333333;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x22222222;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		pxTopOfStack -= 15;
+	}
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_FPSW;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x12345678; /* Accumulator. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x87654321; /* Accumulator. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vApplicationSetupTimerInterrupt( void );
+
+	/* Use pxCurrentTCB just so it does not get optimised away. */
+	if( pxCurrentTCB != NULL )
+	{
+		/* Call an application function to set up the timer that will generate the
+		tick interrupt.  This way the application can decide which peripheral to
+		use.  A demo application is provided to show a suitable example. */
+		vApplicationSetupTimerInterrupt();
+
+		/* Enable the software interrupt. */
+		_IEN( _ICU_SWINT ) = 1;
+
+		/* Ensure the software interrupt is clear. */
+		_IR( _ICU_SWINT ) = 0;
+
+		/* Ensure the software interrupt is set to the kernel priority. */
+		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+		/* Start the first task. */
+		prvStartFirstTask();
+	}
+
+	/* Just to make sure the function is not optimised away. */
+	( void ) vSoftwareInterruptISR();
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+#pragma inline_asm prvStartFirstTask
+static void prvStartFirstTask( void )
+{
+	/* When starting the scheduler there is nothing that needs moving to the
+	interrupt stack because the function is not called from an interrupt.
+	Just ensure the current stack is the user stack. */
+	SETPSW	U
+
+	/* Obtain the location of the stack associated with which ever task
+	pxCurrentTCB is currently pointing to. */
+	MOV.L	#_pxCurrentTCB, R15
+	MOV.L	[R15], R15
+	MOV.L	[R15], R0
+
+	/* Restore the registers from the stack of the task pointed to by
+	pxCurrentTCB. */
+    POP		R15
+    MVTACLO	R15 		/* Accumulator low 32 bits. */
+    POP		R15
+    MVTACHI	R15 		/* Accumulator high 32 bits. */
+    POP		R15
+    MVTC	R15,FPSW 	/* Floating point status word. */
+    POPM	R1-R15 		/* R1 to R15 - R0 is not included as it is the SP. */
+    RTE					/* This pops the remaining registers. */
+    NOP
+    NOP
+}
+/*-----------------------------------------------------------*/
+
+#pragma interrupt ( vTickISR( vect = _VECT( configTICK_VECTOR ), enable ) )
+void vTickISR( void )
+{
+	/* Increment the tick, and perform any processing the new tick value
+	necessitates. */
+	set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			taskYIELD();
+		}
+	}
+	set_ipl( configKERNEL_INTERRUPT_PRIORITY );
+}
+/*-----------------------------------------------------------*/
+
+void vSoftwareInterruptISR( void )
+{
+	prvYieldHandler();
+}
+/*-----------------------------------------------------------*/
+
+#pragma inline_asm prvYieldHandler
+static void prvYieldHandler( void )
+{
+	/* Re-enable interrupts. */
+	SETPSW	I
+
+	/* Move the data that was automatically pushed onto the interrupt stack when
+	the interrupt occurred from the interrupt stack to the user stack.
+
+	R15 is saved before it is clobbered. */
+	PUSH.L	R15
+
+	/* Read the user stack pointer. */
+	MVFC	USP, R15
+
+	/* Move the address down to the data being moved. */
+	SUB		#12, R15
+	MVTC	R15, USP
+
+	/* Copy the data across. */
+	MOV.L	[ R0 ], [ R15 ] ; R15
+	MOV.L 	4[ R0 ], 4[ R15 ]  ; PC
+	MOV.L	8[ R0 ], 8[ R15 ]  ; PSW
+
+	/* Move the interrupt stack pointer to its new correct position. */
+	ADD	#12, R0
+
+	/* All the rest of the registers are saved directly to the user stack. */
+	SETPSW	U
+
+	/* Save the rest of the general registers (R15 has been saved already). */
+	PUSHM	R1-R14
+
+	/* Save the FPSW and accumulator. */
+	MVFC	FPSW, R15
+	PUSH.L	R15
+	MVFACHI	R15
+	PUSH.L	R15
+	MVFACMI	R15	; Middle order word.
+	SHLL	#16, R15 ; Shifted left as it is restored to the low order word.
+	PUSH.L	R15
+
+	/* Save the stack pointer to the TCB. */
+	MOV.L	#_pxCurrentTCB, R15
+	MOV.L	[ R15 ], R15
+	MOV.L	R0, [ R15 ]
+
+	/* Ensure the interrupt mask is set to the syscall priority while the kernel
+	structures are being accessed. */
+	MVTIPL	#configMAX_SYSCALL_INTERRUPT_PRIORITY
+
+	/* Select the next task to run. */
+	BSR.A	_vTaskSwitchContext
+
+	/* Reset the interrupt mask as no more data structure access is required. */
+	MVTIPL	#configKERNEL_INTERRUPT_PRIORITY
+
+	/* Load the stack pointer of the task that is now selected as the Running
+	state task from its TCB. */
+	MOV.L	#_pxCurrentTCB,R15
+	MOV.L	[ R15 ], R15
+	MOV.L	[ R15 ], R0
+
+	/* Restore the context of the new task.  The PSW (Program Status Word) and
+	PC will be popped by the RTE instruction. */
+	POP		R15
+	MVTACLO	R15
+	POP		R15
+	MVTACHI	R15
+	POP		R15
+	MVTC	R15,FPSW
+	POPM	R1-R15
+	RTE
+	NOP
+	NOP
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( pxCurrentTCB == NULL );
+
+	/* The following line is just to prevent the symbol getting optimised away. */
+	( void ) vTaskSwitchContext();
+}
+/*-----------------------------------------------------------*/
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX600/port_asm.src b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX600/port_asm.src
new file mode 100644
index 0000000..6a154ea
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX600/port_asm.src
@@ -0,0 +1,41 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+		.GLB	_vSoftwareInterruptISR
+                .GLB    _vSoftwareInterruptEntry
+
+		.SECTION   P,CODE
+
+_vSoftwareInterruptEntry:
+
+	BRA	_vSoftwareInterruptISR
+
+		.RVECTOR	27, _vSoftwareInterruptEntry
+
+		.END
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX600/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX600/portmacro.h
new file mode 100644
index 0000000..1d6414b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX600/portmacro.h
@@ -0,0 +1,142 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Hardware specifics. */
+#include "machine.h"
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT				8	/* Could make four, according to manual. */
+#define portSTACK_GROWTH				-1
+#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()						nop()
+
+
+#pragma inline_asm vPortYield
+static void vPortYield( void )
+{
+	/* Save clobbered register - may not actually be necessary if inline asm
+	functions are considered to use the same rules as function calls by the
+	compiler. */
+	PUSH.L R5
+	/* Set ITU SWINTR. */
+	MOV.L #553696, R5
+	MOV.B #1, [R5]
+	/* Read back to ensure the value is taken before proceeding. */
+	MOV.L [R5], R5
+	/* Restore clobbered register to its previous value. */
+	POP R5
+}
+#define portYIELD()	vPortYield()
+#define portYIELD_FROM_ISR( x )	if( x != pdFALSE ) portYIELD()
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() 	set_ipl( ( long ) 0 )
+#ifdef configASSERT
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+	#define portDISABLE_INTERRUPTS() 	if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#else
+	#define portDISABLE_INTERRUPTS() 	set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+#define portSET_INTERRUPT_MASK_FROM_ISR() get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX600v2/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX600v2/port.c
new file mode 100644
index 0000000..64fbf83
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX600v2/port.c
@@ -0,0 +1,364 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the RX600 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#if defined( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H ) && ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+	#include "platform.h"
+#else
+	#include "iodefine.h"
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
+
+/*-----------------------------------------------------------*/
+
+/* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
+ and therefore installed in the vector table, when the FreeRTOS code is built
+as a library. */
+extern BaseType_t vSoftwareInterruptEntry;
+const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+static void prvStartFirstTask( void );
+
+/*
+ * Software interrupt handler.  Performs the actual context switch (saving and
+ * restoring of registers).  Written in asm code as direct register access is
+ * required.
+ */
+static void prvYieldHandler( void );
+
+/*
+ * The entry point for the software interrupt handler.  This is the function
+ * that calls the inline asm function prvYieldHandler().  It is installed in
+ * the vector table, but the code that installs it is in prvYieldHandler rather
+ * than using a #pragma.
+ */
+void vSoftwareInterruptISR( void );
+
+/*-----------------------------------------------------------*/
+
+/* This is accessed by the inline assembler functions so is file scope for
+convenience. */
+extern void *pxCurrentTCB;
+extern void vTaskSwitchContext( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* R0 is not included as it is the stack pointer. */
+
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+ 	*pxTopOfStack = portINITIAL_PSW;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;
+
+	/* When debugging it can be useful if every register is set to a known
+	value.  Otherwise code space can be saved by just setting the registers
+	that need to be set. */
+	#ifdef USE_FULL_REGISTER_INITIALISATION
+	{
+		pxTopOfStack--;
+		*pxTopOfStack = 0xffffffff;	/* r15. */
+		pxTopOfStack--;
+		*pxTopOfStack = 0xeeeeeeee;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xdddddddd;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xcccccccc;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xbbbbbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaaaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x99999999;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x88888888;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x77777777;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x66666666;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x55555555;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x44444444;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x33333333;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x22222222;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		pxTopOfStack -= 15;
+	}
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_FPSW;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x11111111; /* Accumulator 0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22222222; /* Accumulator 0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33333333; /* Accumulator 0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x44444444; /* Accumulator 1. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x55555555; /* Accumulator 1. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x66666666; /* Accumulator 1. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vApplicationSetupTimerInterrupt( void );
+
+	/* Use pxCurrentTCB just so it does not get optimised away. */
+	if( pxCurrentTCB != NULL )
+	{
+		/* Call an application function to set up the timer that will generate the
+		tick interrupt.  This way the application can decide which peripheral to
+		use.  A demo application is provided to show a suitable example. */
+		vApplicationSetupTimerInterrupt();
+
+		/* Enable the software interrupt. */
+		_IEN( _ICU_SWINT ) = 1;
+
+		/* Ensure the software interrupt is clear. */
+		_IR( _ICU_SWINT ) = 0;
+
+		/* Ensure the software interrupt is set to the kernel priority. */
+		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+		/* Start the first task. */
+		prvStartFirstTask();
+	}
+
+	/* Just to make sure the function is not optimised away. */
+	( void ) vSoftwareInterruptISR();
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+#pragma inline_asm prvStartFirstTask
+static void prvStartFirstTask( void )
+{
+	/* When starting the scheduler there is nothing that needs moving to the
+	interrupt stack because the function is not called from an interrupt.
+	Just ensure the current stack is the user stack. */
+	SETPSW	U
+
+	/* Obtain the location of the stack associated with which ever task
+	pxCurrentTCB is currently pointing to. */
+	MOV.L	#_pxCurrentTCB, R15
+	MOV.L	[R15], R15
+	MOV.L	[R15], R0
+
+	/* Restore the registers from the stack of the task pointed to by
+	pxCurrentTCB. */
+    POP		R15
+    MVTACLO	R15, A0		/* Accumulator low 32 bits. */
+    POP		R15
+    MVTACHI	R15, A0		/* Accumulator high 32 bits. */
+    POP		R15
+    MVTACGU	R15, A0		/* Accumulator guard. */
+    POP		R15
+    MVTACLO	R15, A1		/* Accumulator low 32 bits. */
+    POP		R15
+    MVTACHI	R15, A1		/* Accumulator high 32 bits. */
+    POP		R15
+    MVTACGU	R15, A1		/* Accumulator guard. */
+    POP		R15
+    MVTC	R15,FPSW 	/* Floating point status word. */
+    POPM	R1-R15 		/* R1 to R15 - R0 is not included as it is the SP. */
+    RTE					/* This pops the remaining registers. */
+    NOP
+    NOP
+}
+/*-----------------------------------------------------------*/
+
+#pragma interrupt ( vTickISR( vect = _VECT( configTICK_VECTOR ), enable ) )
+void vTickISR( void )
+{
+	/* Increment the tick, and perform any processing the new tick value
+	necessitates. */
+	set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			taskYIELD();
+		}
+	}
+	set_ipl( configKERNEL_INTERRUPT_PRIORITY );
+}
+/*-----------------------------------------------------------*/
+
+void vSoftwareInterruptISR( void )
+{
+	prvYieldHandler();
+}
+/*-----------------------------------------------------------*/
+
+#pragma inline_asm prvYieldHandler
+static void prvYieldHandler( void )
+{
+	/* Re-enable interrupts. */
+	SETPSW	I
+
+	/* Move the data that was automatically pushed onto the interrupt stack when
+	the interrupt occurred from the interrupt stack to the user stack.
+
+	R15 is saved before it is clobbered. */
+	PUSH.L	R15
+
+	/* Read the user stack pointer. */
+	MVFC	USP, R15
+
+	/* Move the address down to the data being moved. */
+	SUB		#12, R15
+	MVTC	R15, USP
+
+	/* Copy the data across. */
+	MOV.L	[ R0 ], [ R15 ] ; R15
+	MOV.L 	4[ R0 ], 4[ R15 ]  ; PC
+	MOV.L	8[ R0 ], 8[ R15 ]  ; PSW
+
+	/* Move the interrupt stack pointer to its new correct position. */
+	ADD	#12, R0
+
+	/* All the rest of the registers are saved directly to the user stack. */
+	SETPSW	U
+
+	/* Save the rest of the general registers (R15 has been saved already). */
+	PUSHM	R1-R14
+
+	/* Save the FPSW and accumulators. */
+	MVFC	FPSW, R15
+	PUSH.L	R15
+	MVFACGU	#0, A1, R15
+	PUSH.L	R15
+	MVFACHI	#0, A1, R15
+	PUSH.L	R15
+	MVFACLO	#0, A1, R15	; Low order word.
+	PUSH.L	R15
+	MVFACGU	#0, A0, R15
+	PUSH.L	R15
+	MVFACHI	#0, A0, R15
+	PUSH.L	R15
+	MVFACLO	#0, A0, R15	; Low order word.
+	PUSH.L	R15
+
+	/* Save the stack pointer to the TCB. */
+	MOV.L	#_pxCurrentTCB, R15
+	MOV.L	[ R15 ], R15
+	MOV.L	R0, [ R15 ]
+
+	/* Ensure the interrupt mask is set to the syscall priority while the kernel
+	structures are being accessed. */
+	MVTIPL	#configMAX_SYSCALL_INTERRUPT_PRIORITY
+
+	/* Select the next task to run. */
+	BSR.A	_vTaskSwitchContext
+
+	/* Reset the interrupt mask as no more data structure access is required. */
+	MVTIPL	#configKERNEL_INTERRUPT_PRIORITY
+
+	/* Load the stack pointer of the task that is now selected as the Running
+	state task from its TCB. */
+	MOV.L	#_pxCurrentTCB,R15
+	MOV.L	[ R15 ], R15
+	MOV.L	[ R15 ], R0
+
+	/* Restore the context of the new task.  The PSW (Program Status Word) and
+	PC will be popped by the RTE instruction. */
+    POP		R15
+    MVTACLO	R15, A0		/* Accumulator low 32 bits. */
+    POP		R15
+    MVTACHI	R15, A0		/* Accumulator high 32 bits. */
+    POP		R15
+    MVTACGU	R15, A0		/* Accumulator guard. */
+    POP		R15
+    MVTACLO	R15, A1		/* Accumulator low 32 bits. */
+    POP		R15
+    MVTACHI	R15, A1		/* Accumulator high 32 bits. */
+    POP		R15
+    MVTACGU	R15, A1		/* Accumulator guard. */
+	POP		R15
+	MVTC	R15,FPSW
+	POPM	R1-R15
+	RTE
+	NOP
+	NOP
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( pxCurrentTCB == NULL );
+
+	/* The following line is just to prevent the symbol getting optimised away. */
+	( void ) vTaskSwitchContext();
+}
+/*-----------------------------------------------------------*/
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX600v2/port_asm.src b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX600v2/port_asm.src
new file mode 100644
index 0000000..c0bc9e2
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX600v2/port_asm.src
@@ -0,0 +1,41 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+		.GLB	_vSoftwareInterruptISR
+		.GLB    _vSoftwareInterruptEntry
+
+		.SECTION   P,CODE
+
+_vSoftwareInterruptEntry:
+
+	BRA	_vSoftwareInterruptISR
+
+		.RVECTOR	27, _vSoftwareInterruptEntry
+
+		.END
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX600v2/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX600v2/portmacro.h
new file mode 100644
index 0000000..6d14314
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/RX600v2/portmacro.h
@@ -0,0 +1,142 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Hardware specifics. */
+#include "machine.h"
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT				8	/* Could make four, according to manual. */
+#define portSTACK_GROWTH				-1
+#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()						nop()
+
+
+#pragma inline_asm vPortYield
+static void vPortYield( void )
+{
+	/* Save clobbered register - may not actually be necessary if inline asm
+	functions are considered to use the same rules as function calls by the
+	compiler. */
+	PUSH.L R5
+	/* Set ITU SWINTR. */
+	MOV.L #553696, R5
+	MOV.B #1, [R5]
+	/* Read back to ensure the value is taken before proceeding. */
+	MOV.L [R5], R5
+	/* Restore clobbered register to its previous value. */
+	POP R5
+}
+#define portYIELD()	vPortYield()
+#define portYIELD_FROM_ISR( x )	if( x != pdFALSE ) portYIELD()
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() 	set_ipl( ( long ) 0 )
+#ifdef configASSERT
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+	#define portDISABLE_INTERRUPTS() 	if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#else
+	#define portDISABLE_INTERRUPTS() 	set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+#define portSET_INTERRUPT_MASK_FROM_ISR() ( UBaseType_t ) get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/SH2A_FPU/ISR_Support.inc b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/SH2A_FPU/ISR_Support.inc
new file mode 100644
index 0000000..e0a5996
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/SH2A_FPU/ISR_Support.inc
@@ -0,0 +1,74 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+	.macro portSAVE_CONTEXT
+
+	; Save r0 to r14 and pr.
+	movml.l r15, @-r15
+
+	; Save mac1, mach and gbr
+	sts.l	macl, @-r15
+	sts.l	mach, @-r15
+	stc.l	gbr, @-r15
+
+	; Get the address of pxCurrentTCB
+	mov.l	#_pxCurrentTCB, r0
+
+	; Get the address of pxTopOfStack from the TCB.
+	mov.l	@r0, r0
+
+	; Save the stack pointer in pxTopOfStack.
+	mov.l	r15, @r0
+
+	.endm
+
+;-----------------------------------------------------------
+
+	.macro portRESTORE_CONTEXT
+
+	; Get the address of the pxCurrentTCB variable.
+	mov.l	#_pxCurrentTCB, r0
+
+	; Get the address of the task stack from pxCurrentTCB.
+	mov.l	@r0, r0
+
+	; Get the task stack itself into the stack pointer.
+	mov.l	@r0, r15
+
+	; Restore system registers.
+	ldc.l	@r15+, gbr
+	lds.l	@r15+, mach
+	lds.l	@r15+, macl
+
+	; Restore r0 to r14 and PR
+	movml.l	@r15+, r15
+
+	; Pop the SR and PC to jump to the start of the task.
+	rte
+	nop
+
+	.endm
+;-----------------------------------------------------------
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/SH2A_FPU/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/SH2A_FPU/port.c
new file mode 100644
index 0000000..8c4d50a
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/SH2A_FPU/port.c
@@ -0,0 +1,271 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/*-----------------------------------------------------------*/
+
+/* The SR assigned to a newly created task.  The only important thing in this
+value is for all interrupts to be enabled. */
+#define portINITIAL_SR				( 0UL )
+
+/* Dimensions the array into which the floating point context is saved.
+Allocate enough space for FPR0 to FPR15, FPUL and FPSCR, each of which is 4
+bytes big.  If this number is changed then the 72 in portasm.src also needs
+changing. */
+#define portFLOP_REGISTERS_TO_STORE	( 18 )
+#define portFLOP_STORAGE_SIZE 		( portFLOP_REGISTERS_TO_STORE * 4 )
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+	#error configSUPPORT_DYNAMIC_ALLOCATION must be 1 to use this port.
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The TRAPA handler used to force a context switch.
+ */
+void vPortYield( void );
+
+/*
+ * Function to start the first task executing - defined in portasm.src.
+ */
+extern void vPortStartFirstTask( void );
+
+/*
+ * Obtains the current GBR value - defined in portasm.src.
+ */
+extern uint32_t ulPortGetGBR( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Mark the end of the stack - used for debugging only and can be removed. */
+	*pxTopOfStack = 0x11111111UL;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22222222UL;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33333333UL;
+	pxTopOfStack--;
+
+	/* SR. */
+	*pxTopOfStack = portINITIAL_SR;
+	pxTopOfStack--;
+
+	/* PC. */
+	*pxTopOfStack = ( uint32_t ) pxCode;
+	pxTopOfStack--;
+
+	/* PR. */
+	*pxTopOfStack = 15;
+	pxTopOfStack--;
+
+	/* 14. */
+	*pxTopOfStack = 14;
+	pxTopOfStack--;
+
+	/* R13. */
+	*pxTopOfStack = 13;
+	pxTopOfStack--;
+
+	/* R12. */
+	*pxTopOfStack = 12;
+	pxTopOfStack--;
+
+	/* R11. */
+	*pxTopOfStack = 11;
+	pxTopOfStack--;
+
+	/* R10. */
+	*pxTopOfStack = 10;
+	pxTopOfStack--;
+
+	/* R9. */
+	*pxTopOfStack = 9;
+	pxTopOfStack--;
+
+	/* R8. */
+	*pxTopOfStack = 8;
+	pxTopOfStack--;
+
+	/* R7. */
+	*pxTopOfStack = 7;
+	pxTopOfStack--;
+
+	/* R6. */
+	*pxTopOfStack = 6;
+	pxTopOfStack--;
+
+	/* R5. */
+	*pxTopOfStack = 5;
+	pxTopOfStack--;
+
+	/* R4. */
+	*pxTopOfStack = ( uint32_t ) pvParameters;
+	pxTopOfStack--;
+
+	/* R3. */
+	*pxTopOfStack = 3;
+	pxTopOfStack--;
+
+	/* R2. */
+	*pxTopOfStack = 2;
+	pxTopOfStack--;
+
+	/* R1. */
+	*pxTopOfStack = 1;
+	pxTopOfStack--;
+
+	/* R0 */
+	*pxTopOfStack = 0;
+	pxTopOfStack--;
+
+	/* MACL. */
+	*pxTopOfStack = 16;
+	pxTopOfStack--;
+
+	/* MACH. */
+	*pxTopOfStack = 17;
+	pxTopOfStack--;
+
+	/* GBR. */
+	*pxTopOfStack = ulPortGetGBR();
+
+	/* GBR = global base register.
+	   VBR = vector base register.
+	   TBR = jump table base register.
+	   R15 is the stack pointer. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vApplicationSetupTimerInterrupt( void );
+
+	/* Call an application function to set up the timer that will generate the
+	tick interrupt.  This way the application can decide which peripheral to
+	use.  A demo application is provided to show a suitable example. */
+	vApplicationSetupTimerInterrupt();
+
+	/* Start the first task.  This will only restore the standard registers and
+	not the flop registers.  This does not really matter though because the only
+	flop register that is initialised to a particular value is fpscr, and it is
+	only initialised to the current value, which will still be the current value
+	when the first task starts executing. */
+	trapa( portSTART_SCHEDULER_TRAP_NO );
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented as there is nothing to return to. */
+}
+/*-----------------------------------------------------------*/
+
+void vPortYield( void )
+{
+int32_t lInterruptMask;
+
+	/* Ensure the yield trap runs at the same priority as the other interrupts
+	that can cause a context switch. */
+	lInterruptMask = get_imask();
+
+	/* taskYIELD() can only be called from a task, not an interrupt, so the
+	current interrupt mask can only be 0 or portKERNEL_INTERRUPT_PRIORITY and
+	the mask can be set without risk of accidentally lowering the mask value. */
+	set_imask( portKERNEL_INTERRUPT_PRIORITY );
+
+	trapa( portYIELD_TRAP_NO );
+
+	/* Restore the interrupt mask to whatever it was previously (when the
+	function was entered). */
+	set_imask( ( int ) lInterruptMask );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortUsesFloatingPoint( TaskHandle_t xTask )
+{
+uint32_t *pulFlopBuffer;
+BaseType_t xReturn;
+extern void * volatile pxCurrentTCB;
+
+	/* This function tells the kernel that the task referenced by xTask is
+	going to use the floating point registers and therefore requires the
+	floating point registers saved as part of its context. */
+
+	/* Passing NULL as xTask is used to indicate that the calling task is the
+	subject task - so pxCurrentTCB is the task handle. */
+	if( xTask == NULL )
+	{
+		xTask = ( TaskHandle_t ) pxCurrentTCB;
+	}
+
+	/* Allocate a buffer large enough to hold all the flop registers. */
+	pulFlopBuffer = ( uint32_t * ) pvPortMalloc( portFLOP_STORAGE_SIZE );
+
+	if( pulFlopBuffer != NULL )
+	{
+		/* Start with the registers in a benign state. */
+		memset( ( void * ) pulFlopBuffer, 0x00, portFLOP_STORAGE_SIZE );
+
+		/* The first thing to get saved in the buffer is the FPSCR value -
+		initialise this to the current FPSCR value. */
+		*pulFlopBuffer = get_fpscr();
+
+		/* Use the task tag to point to the flop buffer.  Pass pointer to just
+		above the buffer because the flop save routine uses a pre-decrement. */
+		vTaskSetApplicationTaskTag( xTask, ( void * ) ( pulFlopBuffer + portFLOP_REGISTERS_TO_STORE ) );
+		xReturn = pdPASS;
+	}
+	else
+	{
+		xReturn = pdFAIL;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/SH2A_FPU/portasm.src b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/SH2A_FPU/portasm.src
new file mode 100644
index 0000000..3bcdb5f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/SH2A_FPU/portasm.src
@@ -0,0 +1,150 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	.import _pxCurrentTCB
+	.import _vTaskSwitchContext
+	.import _xTaskIncrementTick
+
+	.export _vPortStartFirstTask
+	.export _ulPortGetGBR
+	.export _vPortYieldHandler
+	.export _vPortPreemptiveTick
+	.export _vPortCooperativeTick
+	.export _vPortSaveFlopRegisters
+	.export _vPortRestoreFlopRegisters
+
+    .section    P
+
+	.INCLUDE "ISR_Support.inc"
+
+_vPortStartFirstTask:
+
+	portRESTORE_CONTEXT
+
+;-----------------------------------------------------------
+
+_vPortYieldHandler:
+
+	portSAVE_CONTEXT
+
+	mov.l	#_vTaskSwitchContext, r0
+	jsr		@r0
+	nop
+
+	portRESTORE_CONTEXT
+
+;-----------------------------------------------------------
+
+_vPortPreemptiveTick
+
+	portSAVE_CONTEXT
+
+	mov.l	#_xTaskIncrementTick, r0
+	jsr		@r0
+	nop
+
+	mov.l	#_vTaskSwitchContext, r0
+	jsr		@r0
+	nop
+
+	portRESTORE_CONTEXT
+
+;-----------------------------------------------------------
+
+_vPortCooperativeTick
+
+	portSAVE_CONTEXT
+
+	mov.l	#_xTaskIncrementTick, r0
+	jsr		@r0
+	nop
+
+	portRESTORE_CONTEXT
+
+;-----------------------------------------------------------
+
+_ulPortGetGBR:
+
+	stc.l	gbr, r0
+	rts
+	nop
+
+;-----------------------------------------------------------
+
+_vPortSaveFlopRegisters:
+
+	fmov.s	fr0, @-r4
+	fmov.s	fr1, @-r4
+	fmov.s	fr2, @-r4
+	fmov.s	fr3, @-r4
+	fmov.s	fr4, @-r4
+	fmov.s	fr5, @-r4
+	fmov.s	fr6, @-r4
+	fmov.s	fr7, @-r4
+	fmov.s	fr8, @-r4
+	fmov.s	fr9, @-r4
+	fmov.s	fr10, @-r4
+	fmov.s	fr11, @-r4
+	fmov.s	fr12, @-r4
+	fmov.s	fr13, @-r4
+	fmov.s	fr14, @-r4
+	fmov.s	fr15, @-r4
+	sts.l   fpul, @-r4
+	sts.l   fpscr, @-r4
+
+	rts
+	nop
+
+;-----------------------------------------------------------
+
+_vPortRestoreFlopRegisters:
+
+	add.l  #-72, r4
+	lds.l  @r4+, fpscr
+	lds.l  @r4+, fpul
+	fmov.s @r4+, fr15
+	fmov.s @r4+, fr14
+	fmov.s @r4+, fr13
+	fmov.s @r4+, fr12
+	fmov.s @r4+, fr11
+	fmov.s @r4+, fr10
+	fmov.s @r4+, fr9
+	fmov.s @r4+, fr8
+	fmov.s @r4+, fr7
+	fmov.s @r4+, fr6
+	fmov.s @r4+, fr5
+	fmov.s @r4+, fr4
+	fmov.s @r4+, fr3
+	fmov.s @r4+, fr2
+	fmov.s @r4+, fr1
+	fmov.s @r4+, fr0
+
+	rts
+	nop
+
+	.end
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/SH2A_FPU/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/SH2A_FPU/portmacro.h
new file mode 100644
index 0000000..009f2b0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Renesas/SH2A_FPU/portmacro.h
@@ -0,0 +1,139 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT				8
+#define portSTACK_GROWTH				-1
+#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()						nop()
+#define portSTART_SCHEDULER_TRAP_NO		( 32 )
+#define portYIELD_TRAP_NO				( 33 )
+#define portKERNEL_INTERRUPT_PRIORITY	( 1 )
+
+void vPortYield( void );
+#define portYIELD()						vPortYield()
+
+extern void vTaskSwitchContext( void );
+#define portYIELD_FROM_ISR( x )			if( x != pdFALSE ) vTaskSwitchContext()
+
+/*
+ * This function tells the kernel that the task referenced by xTask is going to
+ * use the floating point registers and therefore requires the floating point
+ * registers saved as part of its context.
+ */
+BaseType_t xPortUsesFloatingPoint( void* xTask );
+
+/*
+ * The flop save and restore functions are defined in portasm.src and called by
+ * the trace "task switched in" and "trace task switched out" macros.
+ */
+void vPortSaveFlopRegisters( void *pulBuffer );
+void vPortRestoreFlopRegisters( void *pulBuffer );
+
+/*
+ * pxTaskTag is used to point to the buffer into which the floating point
+ * context should be saved.  If pxTaskTag is NULL then the task does not use
+ * a floating point context.
+ */
+#define traceTASK_SWITCHED_OUT() if( pxCurrentTCB->pxTaskTag != NULL ) vPortSaveFlopRegisters( pxCurrentTCB->pxTaskTag )
+#define traceTASK_SWITCHED_IN() if( pxCurrentTCB->pxTaskTag != NULL ) vPortRestoreFlopRegisters( pxCurrentTCB->pxTaskTag )
+
+/*
+ * These macros should be called directly, but through the taskENTER_CRITICAL()
+ * and taskEXIT_CRITICAL() macros.
+ */
+#define portENABLE_INTERRUPTS() 	set_imask( 0x00 )
+#define portDISABLE_INTERRUPTS() 	set_imask( portKERNEL_INTERRUPT_PRIORITY )
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()	vTaskEnterCritical();
+#define portEXIT_CRITICAL()		vTaskExitCritical();
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Rowley/ARM7/readme.txt b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Rowley/ARM7/readme.txt
new file mode 100644
index 0000000..8d3e87f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Rowley/ARM7/readme.txt
@@ -0,0 +1 @@
+The Rowley ARM7 demo uses the GCC ARM7 port files.
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Rowley/MSP430F449/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Rowley/MSP430F449/port.c
new file mode 100644
index 0000000..6c0fddd
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Rowley/MSP430F449/port.c
@@ -0,0 +1,172 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MSP430 port.
+ *----------------------------------------------------------*/
+
+/* Constants required for hardware setup.  The tick ISR runs off the ACLK, 
+not the MCLK. */
+#define portACLK_FREQUENCY_HZ			( ( TickType_t ) 32768 )
+#define portINITIAL_CRITICAL_NESTING	( ( uint16_t ) 10 )
+#define portFLAGS_INT_ENABLED			( ( StackType_t ) 0x08 )
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/* Each task maintains a count of the critical section nesting depth.  Each 
+time a critical section is entered the count is incremented.  Each time a 
+critical section is exited the count is decremented - with interrupts only 
+being re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as this will cause problems during the startup
+sequence. */
+volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
+/*-----------------------------------------------------------*/
+
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
+ * could have alternatively used the watchdog timer or timer 1.
+ */
+void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been called.
+ * 
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* 
+		Place a few bytes of known values on the bottom of the stack. 
+		This is just useful for debugging and can be included if required.
+
+		*pxTopOfStack = ( StackType_t ) 0x1111;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x2222;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x3333;
+		pxTopOfStack--; 
+	*/
+
+	/* The msp430 automatically pushes the PC then SR onto the stack before 
+	executing an ISR.  We want the stack to look just as if this has happened
+	so place a pointer to the start of the task on the stack first - followed
+	by the flags we want the task to use when it starts up. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+	*pxTopOfStack = portFLAGS_INT_ENABLED;
+	pxTopOfStack--;
+
+	/* Next the general purpose registers. */
+	*pxTopOfStack = ( StackType_t ) 0x4444;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x5555;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x6666;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x7777;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x8888;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x9999;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xaaaa;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xbbbb;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xcccc;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xdddd;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xeeee;
+	pxTopOfStack--;
+
+	/* When the task starts is will expect to find the function parameter in
+	R15. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;
+	pxTopOfStack--;
+
+	/* A variable is used to keep track of the critical section nesting.  
+	This variable has to be stored as part of the task context and is 
+	initially set to zero. */
+	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;	
+
+	/* Return a pointer to the top of the stack we have generated so this can
+	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the MSP430 port will get stopped.  If required simply
+	disable the tick interrupt here. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.  This uses timer 0
+ * but could alternatively use the watchdog timer or timer 1. 
+ */
+void prvSetupTimerInterrupt( void )
+{
+	/* Ensure the timer is stopped. */
+	TACTL = 0;
+
+	/* Run the timer of the ACLK. */
+	TACTL = TASSEL_1;
+
+	/* Clear everything to start with. */
+	TACTL |= TACLR;
+
+	/* Set the compare match value according to the tick rate we want. */
+	TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;
+
+	/* Enable the interrupts. */
+	TACCTL0 = CCIE;
+
+	/* Start up clean. */
+	TACTL |= TACLR;
+
+	/* Up mode. */
+	TACTL |= MC_1;
+}
+/*-----------------------------------------------------------*/
+
+
+	
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Rowley/MSP430F449/portasm.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Rowley/MSP430F449/portasm.h
new file mode 100644
index 0000000..129847b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Rowley/MSP430F449/portasm.h
@@ -0,0 +1,80 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORT_ASM_H
+#define PORT_ASM_H
+
+portSAVE_CONTEXT macro
+                /* Save the remaining registers. */
+		push	r4
+		push	r5
+		push	r6
+		push	r7
+		push	r8
+		push	r9
+		push	r10
+		push	r11
+		push	r12
+		push	r13
+		push	r14
+		push	r15
+		mov.w	&_usCriticalNesting, r14
+		push	r14
+		mov.w	&_pxCurrentTCB, r12
+		mov.w	r1, @r12
+		endm
+/*-----------------------------------------------------------*/
+		
+portRESTORE_CONTEXT macro
+		mov.w	&_pxCurrentTCB, r12
+		mov.w	@r12, r1
+		pop		r15
+		mov.w	r15, &_usCriticalNesting
+		pop		r15
+		pop		r14
+		pop		r13
+		pop		r12
+		pop		r11
+		pop		r10
+		pop		r9
+		pop		r8
+		pop		r7
+		pop		r6
+		pop		r5
+		pop		r4
+
+		/* The last thing on the stack will be the status register.
+                Ensure the power down bits are clear ready for the next
+                time this power down register is popped from the stack. */
+		bic.w   #0xf0,0(SP)
+
+		reti
+		endm
+/*-----------------------------------------------------------*/
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Rowley/MSP430F449/portext.asm b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Rowley/MSP430F449/portext.asm
new file mode 100644
index 0000000..b4792d1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Rowley/MSP430F449/portext.asm
@@ -0,0 +1,102 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "FreeRTOSConfig.h"
+#include "portasm.h"
+
+
+.CODE
+
+/*
+ * The RTOS tick ISR.
+ *
+ * If the cooperative scheduler is in use this simply increments the tick 
+ * count.
+ *
+ * If the preemptive scheduler is in use a context switch can also occur.
+ */
+_vTickISR:
+		portSAVE_CONTEXT
+				
+		call	#_xTaskIncrementTick
+		cmp.w   #0x00, r15
+                jeq     _SkipContextSwitch
+		call	#_vTaskSwitchContext
+_SkipContextSwitch:		
+		portRESTORE_CONTEXT
+/*-----------------------------------------------------------*/
+
+
+/*
+ * Manual context switch called by the portYIELD() macro.
+ */                
+_vPortYield::
+
+		/* Mimic an interrupt by pushing the SR. */
+		push	SR			
+
+		/* Now the SR is stacked we can disable interrupts. */
+		dint			
+				
+		/* Save the context of the current task. */
+		portSAVE_CONTEXT			
+
+		/* Switch to the highest priority task that is ready to run. */
+		call	#_vTaskSwitchContext		
+
+		/* Restore the context of the new task. */
+		portRESTORE_CONTEXT
+/*-----------------------------------------------------------*/
+
+
+/*
+ * Start off the scheduler by initialising the RTOS tick timer, then restoring
+ * the context of the first task.
+ */
+_xPortStartScheduler::
+
+		/* Setup the hardware to generate the tick.  Interrupts are disabled 
+		when this function is called. */
+		call	#_prvSetupTimerInterrupt
+
+		/* Restore the context of the first task that is going to run. */
+		portRESTORE_CONTEXT
+/*-----------------------------------------------------------*/          
+      		
+
+		/* Place the tick ISR in the correct vector. */
+		.VECTORS
+		
+		.KEEP
+		
+		ORG		TIMERA0_VECTOR
+		DW		_vTickISR
+		
+
+
+		END
+		
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Rowley/MSP430F449/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Rowley/MSP430F449/portmacro.h
new file mode 100644
index 0000000..52eebf9
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Rowley/MSP430F449/portmacro.h
@@ -0,0 +1,132 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	uint16_t
+#define portBASE_TYPE	short
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS()	_DINT(); _NOP()
+#define portENABLE_INTERRUPTS()		_EINT();
+/*-----------------------------------------------------------*/
+
+/* Critical section control macros. */
+#define portNO_CRITICAL_SECTION_NESTING		( ( uint16_t ) 0 )
+
+#define portENTER_CRITICAL()													\
+{																				\
+extern volatile uint16_t usCriticalNesting;							\
+																				\
+	portDISABLE_INTERRUPTS();													\
+																				\
+	/* Now interrupts are disabled usCriticalNesting can be accessed */			\
+	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
+	/* times portENTER_CRITICAL() has been called. */							\
+	usCriticalNesting++;														\
+}
+
+#define portEXIT_CRITICAL()														\
+{																				\
+extern volatile uint16_t usCriticalNesting;							\
+																				\
+	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
+	{																			\
+		/* Decrement the nesting count as we are leaving a critical section. */	\
+		usCriticalNesting--;													\
+																				\
+		/* If the nesting level has reached zero then interrupts should be */	\
+		/* re-enabled. */														\
+		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
+		{																		\
+			portENABLE_INTERRUPTS();											\
+		}																		\
+	}																			\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.
+ */
+extern void vPortYield( void );
+#define portYIELD() vPortYield()
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			2
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) __toplevel
+
+#if configINTERRUPT_EXAMPLE_METHOD == 2
+
+extern void vTaskSwitchContext( void );
+#define portYIELD_FROM_ISR( x ) if( x ) vTaskSwitchContext()
+
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/SDCC/Cygnal/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/SDCC/Cygnal/port.c
new file mode 100644
index 0000000..eb1a08e
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/SDCC/Cygnal/port.c
@@ -0,0 +1,424 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the Cygnal port.
+ *----------------------------------------------------------*/
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup timer 2 to produce the RTOS tick. */
+#define portCLOCK_DIVISOR				( ( uint32_t ) 12 )
+#define portMAX_TIMER_VALUE				( ( uint32_t ) 0xffff )
+#define portENABLE_TIMER				( ( uint8_t ) 0x04 )
+#define portTIMER_2_INTERRUPT_ENABLE	( ( uint8_t ) 0x20 )
+
+/* The value used in the IE register when a task first starts. */
+#define portGLOBAL_INTERRUPT_BIT	( ( StackType_t ) 0x80 )
+
+/* The value used in the PSW register when a task first starts. */
+#define portINITIAL_PSW				( ( StackType_t ) 0x00 )
+
+/* Macro to clear the timer 2 interrupt flag. */
+#define portCLEAR_INTERRUPT_FLAG()	TMR2CN &= ~0x80;
+
+/* Used during a context switch to store the size of the stack being copied
+to or from XRAM. */
+data static uint8_t ucStackBytes;
+
+/* Used during a context switch to point to the next byte in XRAM from/to which
+a RAM byte is to be copied. */
+xdata static StackType_t * data pxXRAMStack;
+
+/* Used during a context switch to point to the next byte in RAM from/to which
+an XRAM byte is to be copied. */
+data static StackType_t * data pxRAMStack;
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/*
+ * Setup the hardware to generate an interrupt off timer 2 at the required 
+ * frequency.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*-----------------------------------------------------------*/
+/*
+ * Macro that copies the current stack from internal RAM to XRAM.  This is 
+ * required as the 8051 only contains enough internal RAM for a single stack, 
+ * but we have a stack for every task.
+ */
+#define portCOPY_STACK_TO_XRAM()																\
+{																								\
+	/* pxCurrentTCB points to a TCB which itself points to the location into					\
+	which the first	stack byte should be copied.  Set pxXRAMStack to point						\
+	to the location into which the first stack byte is to be copied. */							\
+	pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB );		\
+																								\
+	/* Set pxRAMStack to point to the first byte to be coped from the stack. */					\
+	pxRAMStack = ( data StackType_t * data ) configSTACK_START;								\
+																								\
+	/* Calculate the size of the stack we are about to copy from the current					\
+	stack pointer value. */																		\
+	ucStackBytes = SP - ( configSTACK_START - 1 );												\
+																								\
+	/* Before starting to copy the stack, store the calculated stack size so					\
+	the stack can be restored when the task is resumed. */										\
+	*pxXRAMStack = ucStackBytes;																\
+																								\
+	/* Copy each stack byte in turn.  pxXRAMStack is incremented first as we					\
+	have already stored the stack size into XRAM. */											\
+	while( ucStackBytes )																		\
+	{																							\
+		pxXRAMStack++;																			\
+		*pxXRAMStack = *pxRAMStack;																\
+		pxRAMStack++;																			\
+		ucStackBytes--;																			\
+	}																							\
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro that copies the stack of the task being resumed from XRAM into 
+ * internal RAM.
+ */
+#define portCOPY_XRAM_TO_STACK()																\
+{																								\
+	/* Setup the pointers as per portCOPY_STACK_TO_XRAM(), but this time to						\
+	copy the data back out of XRAM and into the stack. */										\
+	pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB );		\
+	pxRAMStack = ( data StackType_t * data ) ( configSTACK_START - 1 );						\
+																								\
+	/* The first value stored in XRAM was the size of the stack - i.e. the						\
+	number of bytes we need to copy back. */													\
+	ucStackBytes = pxXRAMStack[ 0 ];															\
+																								\
+	/* Copy the required number of bytes back into the stack. */								\
+	do																							\
+	{																							\
+		pxXRAMStack++;																			\
+		pxRAMStack++;																			\
+		*pxRAMStack = *pxXRAMStack;																\
+		ucStackBytes--;																			\
+	} while( ucStackBytes );																	\
+																								\
+	/* Restore the stack pointer ready to use the restored stack. */							\
+	SP = ( uint8_t ) pxRAMStack;														\
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to push the current execution context onto the stack, before the stack 
+ * is moved to XRAM. 
+ */
+#define portSAVE_CONTEXT()																		\
+{																								\
+	_asm																						\
+		/* Push ACC first, as when restoring the context it must be restored					\
+		last (it is used to set the IE register). */											\
+		push	ACC																				\
+		/* Store the IE register then disable interrupts. */									\
+		push	IE																				\
+		clr		_EA																				\
+		push	DPL																				\
+		push	DPH																				\
+		push	b																				\
+		push	ar2																				\
+		push	ar3																				\
+		push	ar4																				\
+		push	ar5																				\
+		push	ar6																				\
+		push	ar7																				\
+		push	ar0																				\
+		push	ar1																				\
+		push	PSW																				\
+	_endasm;																					\
+		PSW = 0;																				\
+	_asm																						\
+		push	_bp																				\
+	_endasm;																					\
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro that restores the execution context from the stack.  The execution 
+ * context was saved into the stack before the stack was copied into XRAM.
+ */
+#define portRESTORE_CONTEXT()																	\
+{																								\
+	_asm																						\
+		pop		_bp																				\
+		pop		PSW																				\
+		pop		ar1																				\
+		pop		ar0																				\
+		pop		ar7																				\
+		pop		ar6																				\
+		pop		ar5																				\
+		pop		ar4																				\
+		pop		ar3																				\
+		pop		ar2																				\
+		pop		b																				\
+		pop		DPH																				\
+		pop		DPL																				\
+		/* The next byte of the stack is the IE register.  Only the global						\
+		enable bit forms part of the task context.  Pop off the IE then set						\
+		the global enable bit to match that of the stored IE register. */						\
+		pop		ACC																				\
+		JB		ACC.7,0098$																		\
+		CLR		IE.7																			\
+		LJMP	0099$																			\
+	0098$:																						\
+		SETB	IE.7																			\
+	0099$:																						\
+		/* Finally pop off the ACC, which was the first register saved. */						\
+		pop		ACC																				\
+		reti																					\
+	_endasm;																					\
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint32_t ulAddress;
+StackType_t *pxStartOfStack;
+
+	/* Leave space to write the size of the stack as the first byte. */
+	pxStartOfStack = pxTopOfStack;
+	pxTopOfStack++;
+
+	/* Place a few bytes of known values on the bottom of the stack. 
+	This is just useful for debugging and can be uncommented if required.
+	*pxTopOfStack = 0x11;
+	pxTopOfStack++;
+	*pxTopOfStack = 0x22;
+	pxTopOfStack++;
+	*pxTopOfStack = 0x33;
+	pxTopOfStack++;
+	*/
+
+	/* Simulate how the stack would look after a call to the scheduler tick 
+	ISR. 
+
+	The return address that would have been pushed by the MCU. */
+	ulAddress = ( uint32_t ) pxCode;
+	*pxTopOfStack = ( StackType_t ) ulAddress;
+	ulAddress >>= 8;
+	pxTopOfStack++;
+	*pxTopOfStack = ( StackType_t ) ( ulAddress );
+	pxTopOfStack++;
+
+	/* Next all the registers will have been pushed by portSAVE_CONTEXT(). */
+	*pxTopOfStack = 0xaa;	/* acc */
+	pxTopOfStack++;	
+
+	/* We want tasks to start with interrupts enabled. */
+	*pxTopOfStack = portGLOBAL_INTERRUPT_BIT;
+	pxTopOfStack++;
+
+	/* The function parameters will be passed in the DPTR and B register as
+	a three byte generic pointer is used. */
+	ulAddress = ( uint32_t ) pvParameters;
+	*pxTopOfStack = ( StackType_t ) ulAddress;	/* DPL */
+	ulAddress >>= 8;
+	*pxTopOfStack++;
+	*pxTopOfStack = ( StackType_t ) ulAddress;	/* DPH */
+	ulAddress >>= 8;
+	pxTopOfStack++;
+	*pxTopOfStack = ( StackType_t ) ulAddress;	/* b */
+	pxTopOfStack++;
+
+	/* The remaining registers are straight forward. */
+	*pxTopOfStack = 0x02;	/* R2 */
+	pxTopOfStack++;
+	*pxTopOfStack = 0x03;	/* R3 */
+	pxTopOfStack++;
+	*pxTopOfStack = 0x04;	/* R4 */
+	pxTopOfStack++;
+	*pxTopOfStack = 0x05;	/* R5 */
+	pxTopOfStack++;
+	*pxTopOfStack = 0x06;	/* R6 */
+	pxTopOfStack++;
+	*pxTopOfStack = 0x07;	/* R7 */
+	pxTopOfStack++;
+	*pxTopOfStack = 0x00;	/* R0 */
+	pxTopOfStack++;
+	*pxTopOfStack = 0x01;	/* R1 */
+	pxTopOfStack++;
+	*pxTopOfStack = 0x00;	/* PSW */
+	pxTopOfStack++;
+	*pxTopOfStack = 0xbb;	/* BP */
+
+	/* Dont increment the stack size here as we don't want to include
+	the stack size byte as part of the stack size count.
+
+	Finally we place the stack size at the beginning. */
+	*pxStartOfStack = ( StackType_t ) ( pxTopOfStack - pxStartOfStack );
+
+	/* Unlike most ports, we return the start of the stack as this is where the
+	size of the stack is stored. */
+	return pxStartOfStack;
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* Setup timer 2 to generate the RTOS tick. */
+	prvSetupTimerInterrupt();	
+
+	/* Make sure we start with the expected SFR page.  This line should not
+	really be required. */
+	SFRPAGE = 0;
+
+	/* Copy the stack for the first task to execute from XRAM into the stack,
+	restore the task context from the new stack, then start running the task. */
+	portCOPY_XRAM_TO_STACK();
+	portRESTORE_CONTEXT();
+
+	/* Should never get here! */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented for this port. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch.  The first thing we do is save the registers so we
+ * can use a naked attribute.
+ */
+void vPortYield( void ) _naked
+{
+	/* Save the execution context onto the stack, then copy the entire stack
+	to XRAM.  This is necessary as the internal RAM is only large enough to
+	hold one stack, and we want one per task. 
+	
+	PERFORMANCE COULD BE IMPROVED BY ONLY COPYING TO XRAM IF A TASK SWITCH
+	IS REQUIRED. */
+	portSAVE_CONTEXT();
+	portCOPY_STACK_TO_XRAM();
+
+	/* Call the standard scheduler context switch function. */
+	vTaskSwitchContext();
+
+	/* Copy the stack of the task about to execute from XRAM into RAM and
+	restore it's context ready to run on exiting. */
+	portCOPY_XRAM_TO_STACK();
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 1
+	void vTimer2ISR( void ) interrupt 5 _naked
+	{
+		/* Preemptive context switch function triggered by the timer 2 ISR.
+		This does the same as vPortYield() (see above) with the addition
+		of incrementing the RTOS tick count. */
+
+		portSAVE_CONTEXT();
+		portCOPY_STACK_TO_XRAM();
+
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			vTaskSwitchContext();
+		}
+		
+		portCLEAR_INTERRUPT_FLAG();
+		portCOPY_XRAM_TO_STACK();
+		portRESTORE_CONTEXT();
+	}
+#else
+	void vTimer2ISR( void ) interrupt 5
+	{
+		/* When using the cooperative scheduler the timer 2 ISR is only 
+		required to increment the RTOS tick count. */
+
+		xTaskIncrementTick();
+		portCLEAR_INTERRUPT_FLAG();
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+uint8_t ucOriginalSFRPage;
+
+/* Constants calculated to give the required timer capture values. */
+const uint32_t ulTicksPerSecond = configCPU_CLOCK_HZ / portCLOCK_DIVISOR;
+const uint32_t ulCaptureTime = ulTicksPerSecond / configTICK_RATE_HZ;
+const uint32_t ulCaptureValue = portMAX_TIMER_VALUE - ulCaptureTime;
+const uint8_t ucLowCaptureByte = ( uint8_t ) ( ulCaptureValue & ( uint32_t ) 0xff );
+const uint8_t ucHighCaptureByte = ( uint8_t ) ( ulCaptureValue >> ( uint32_t ) 8 );
+
+	/* NOTE:  This uses a timer only present on 8052 architecture. */
+
+	/* Remember the current SFR page so we can restore it at the end of the
+	function. */
+	ucOriginalSFRPage = SFRPAGE;
+	SFRPAGE = 0;
+
+	/* TMR2CF can be left in its default state. */	
+	TMR2CF = ( uint8_t ) 0;
+
+	/* Setup the overflow reload value. */
+	RCAP2L = ucLowCaptureByte;
+	RCAP2H = ucHighCaptureByte;
+
+	/* The initial load is performed manually. */
+	TMR2L = ucLowCaptureByte;
+	TMR2H = ucHighCaptureByte;
+
+	/* Enable the timer 2 interrupts. */
+	IE |= portTIMER_2_INTERRUPT_ENABLE;
+
+	/* Interrupts are disabled when this is called so the timer can be started
+	here. */
+	TMR2CN = portENABLE_TIMER;
+
+	/* Restore the original SFR page. */
+	SFRPAGE = ucOriginalSFRPage;
+}
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/SDCC/Cygnal/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/SDCC/Cygnal/portmacro.h
new file mode 100644
index 0000000..45197f8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/SDCC/Cygnal/portmacro.h
@@ -0,0 +1,115 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#if configUSE_PREEMPTION == 0
+	void vTimer2ISR( void ) interrupt 5;
+#else
+	void vTimer2ISR( void ) interrupt 5 _naked;
+#endif
+
+void vSerialISR( void ) interrupt 4;
+
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		float
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint8_t
+#define portBASE_TYPE	char
+
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#define portENTER_CRITICAL()		_asm		\
+									push	ACC	\
+									push	IE	\
+									_endasm;	\
+									EA = 0;
+
+#define portEXIT_CRITICAL()			_asm			\
+									pop		ACC		\
+									_endasm;		\
+									ACC &= 0x80;	\
+									IE |= ACC;		\
+									_asm			\
+									pop		ACC		\
+									_endasm;
+
+#define portDISABLE_INTERRUPTS()	EA = 0;
+#define portENABLE_INTERRUPTS()		EA = 1;
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			1
+#define portSTACK_GROWTH			( 1 )
+#define portTICK_PERIOD_MS			( ( uint32_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+void vPortYield( void ) _naked;
+#define portYIELD()	vPortYield();
+/*-----------------------------------------------------------*/
+
+#define portNOP()				_asm	\
+									nop \
+								_endasm;
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#endif /* PORTMACRO_H */
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Softune/MB91460/__STD_LIB_sbrk.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Softune/MB91460/__STD_LIB_sbrk.c
new file mode 100644
index 0000000..fe70d48
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Softune/MB91460/__STD_LIB_sbrk.c
@@ -0,0 +1,23 @@
+#include "FreeRTOSConfig.h"
+#include 
+
+	static  long         brk_siz  =  0;
+//	#if  configTOTAL_HEAP_SIZE != 0
+	typedef int          _heep_t;
+	#define ROUNDUP(s)   (((s)+sizeof(_heep_t)-1)&~(sizeof(_heep_t)-1))
+	static  _heep_t      _heep[ROUNDUP(configTOTAL_HEAP_SIZE)/sizeof(_heep_t)];
+	#define              _heep_size      ROUNDUP(configTOTAL_HEAP_SIZE)
+/*	#else
+	extern  char        *_heep;
+	extern  long        _heep_size;
+	#endif
+*/	
+	extern  char  *sbrk(int  size)
+	{
+	   if  (brk_siz  +  size  >  _heep_size  ||  brk_siz  +  size  <  0)
+
+          return((char*)-1);
+	   brk_siz  +=  size;
+	   return(  (char*)_heep  +  brk_siz  -  size);
+	}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Softune/MB91460/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Softune/MB91460/port.c
new file mode 100644
index 0000000..4246106
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Softune/MB91460/port.c
@@ -0,0 +1,321 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "mb91467d.h"
+
+/*-----------------------------------------------------------*/
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+ 
+#pragma asm
+#macro  SaveContext
+	 ORCCR #0x20								;Switch to user stack
+	 ST RP,@-R15								;Store RP
+	 STM0 (R7,R6,R5,R4,R3,R2,R1,R0)				;Store R7-R0
+	 STM1 (R14,R13,R12,R11,R10,R9,R8)			;Store R14-R8
+	 ST MDH, @-R15								;Store MDH
+	 ST MDL, @-R15								;Store MDL
+	 
+	 ANDCCR #0xDF								;Switch back to system stack
+	 LD @R15+,R0								;Store PC to R0 
+	 ORCCR #0x20								;Switch to user stack
+	 ST R0,@-R15								;Store PC to User stack
+	 
+	 ANDCCR #0xDF								;Switch back to system stack
+	 LD @R15+,R0								;Store PS to R0
+	 ORCCR #0x20								;Switch to user stack
+	 ST R0,@-R15								;Store PS to User stack
+	 
+	 LDI #_pxCurrentTCB, R0						;Get pxCurrentTCB address
+	 LD @R0, R0									;Get the pxCurrentTCB->pxTopOfStack address
+	 ST R15,@R0									;Store USP to pxCurrentTCB->pxTopOfStack
+	 
+	 ANDCCR #0xDF								;Switch back to system stack for the rest of tick ISR
+#endm
+
+#macro RestoreContext
+	 LDI #_pxCurrentTCB, R0						;Get pxCurrentTCB address
+	 LD @R0, R0									;Get the pxCurrentTCB->pxTopOfStack address
+	 ORCCR #0x20								;Switch to user stack
+	 LD @R0, R15								;Restore USP from pxCurrentTCB->pxTopOfStack
+
+	 LD @R15+,R0								;Store PS to R0
+	 ANDCCR #0xDF								;Switch to system stack
+	 ST R0,@-R15								;Store PS to system stack
+
+	 ORCCR #0x20								;Switch to user stack
+	 LD @R15+,R0								;Store PC to R0
+	 ANDCCR #0xDF								;Switch to system stack
+	 ST R0,@-R15								;Store PC to system stack
+
+	 ORCCR #0x20								;Switch back to retrieve the remaining context
+
+	 LD @R15+, MDL								;Restore MDL
+	 LD @R15+, MDH								;Restore MDH
+	 LDM1 (R14,R13,R12,R11,R10,R9,R8)			;Restore R14-R8
+	 LDM0 (R7,R6,R5,R4,R3,R2,R1,R0)				;Restore R7-R0
+	 LD @R15+, RP								;Restore RP
+	 
+	 ANDCCR #0xDF								;Switch back to system stack for the rest of tick ISR
+#endm
+#pragma endasm
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Perform hardware setup to enable ticks from timer 1,
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been called.
+ * 
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Place a few bytes of known values on the bottom of the stack. 
+	This is just useful for debugging. */
+
+	*pxTopOfStack = 0x11111111;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22222222;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33333333;
+	pxTopOfStack--;
+
+	/* This is a redundant push to the stack, it may be required if 
+	in some implementations of the compiler the parameter to the task 
+	is passed on to the stack rather than in R4 register. */
+	*pxTopOfStack = (StackType_t)(pvParameters);
+	pxTopOfStack--;                  
+    
+	*pxTopOfStack = ( StackType_t ) 0x00000000;	/* RP */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00007777;	/* R7 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00006666;	/* R6 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00005555;	/* R5 */
+	pxTopOfStack--;
+	
+	/* In the current implementation of the compiler the first 
+	parameter to the task (or function) is passed via R4 parameter 
+	to the task, hence the pvParameters pointer is copied into the R4 
+	register. See compiler manual section 4.6.2 for more information. */
+	*pxTopOfStack = ( StackType_t ) (pvParameters);	/* R4 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00003333;	/* R3 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00002222;	/* R2 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00001111;	/* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00000001;	/* R0 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x0000EEEE;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0000DDDD;	/* R13 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0000CCCC;	/* R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0000BBBB;	/* R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0000AAAA;	/* R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00009999;	/* R9 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00008888;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11110000;	/* MDH */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x22220000;	/* MDL */
+	pxTopOfStack--;
+
+	/* The start of the task code. */
+	*pxTopOfStack = ( StackType_t ) pxCode;	/* PC */
+	pxTopOfStack--;
+	 
+    /* PS - User Mode, USP, ILM=31, Interrupts enabled */
+	*pxTopOfStack = ( StackType_t ) 0x001F0030;	/* PS */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Setup the hardware to generate the tick. */
+	prvSetupTimerInterrupt();
+
+	/* Restore the context of the first task that is going to run. */
+	#pragma asm
+		RestoreContext
+	#pragma endasm
+
+	/* Simulate a function call end as generated by the compiler.  We will now
+	jump to the start of the task the context of which we have just restored. */	
+	__asm(" reti ");
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented - unlikely to ever be required as there is nothing to
+	return to. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+/* The peripheral clock divided by 32 is used by the timer. */
+const uint16_t usReloadValue = ( uint16_t ) ( ( ( configPER_CLOCK_HZ / configTICK_RATE_HZ ) / 32UL ) - 1UL );
+
+	/* Setup RLT0 to generate a tick interrupt. */
+
+	TMCSR0_CNTE = 0;		/* Count Disable */
+    TMCSR0_CSL = 0x2;		/* CLKP/32 */
+    TMCSR0_MOD = 0;			/* Software trigger */
+    TMCSR0_RELD = 1;		/* Reload */
+    
+    TMCSR0_UF = 0;			/* Clear underflow flag */
+	TMRLR0 = usReloadValue;
+	TMCSR0_INTE = 1;		/* Interrupt Enable */
+	TMCSR0_CNTE = 1;		/* Count Enable */
+	TMCSR0_TRG = 1;			/* Trigger */
+	
+    PORTEN = 0x3;			/* Port Enable */
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 1
+
+	/* 
+	 * Tick ISR for preemptive scheduler. The tick count is incremented 
+	 * after the context is saved. Then the context is switched if required,
+	 * and last the context of the task which is to be resumed is restored.
+	 */
+
+	#pragma asm
+
+	.global _ReloadTimer0_IRQHandler
+	_ReloadTimer0_IRQHandler:
+
+	ANDCCR #0xEF							;Disable Interrupts
+	SaveContext								;Save context
+	ORCCR #0x10								;Re-enable Interrupts
+
+	LDI #0xFFFB,R1
+	LDI #_tmcsr0, R0
+	AND R1,@R0								;Clear RLT0 interrupt flag
+
+	CALL32	 _xTaskIncrementTick,R12		;Increment Tick
+	CALL32	 _vTaskSwitchContext,R12		;Switch context if required
+
+	ANDCCR #0xEF							;Disable Interrupts
+	RestoreContext							;Restore context
+	ORCCR #0x10								;Re-enable Interrupts
+
+	RETI
+
+	#pragma endasm
+	
+#else
+	
+	/* 
+	 * Tick ISR for the cooperative scheduler.  All this does is increment the
+	 * tick count.  We don't need to switch context, this can only be done by
+	 * manual calls to taskYIELD();
+	 */
+	__interrupt void ReloadTimer0_IRQHandler( void )
+	{
+		/* Clear RLT0 interrupt flag */
+		TMCSR0_UF = 0; 
+		xTaskIncrementTick();
+	}
+
+#endif
+
+/*
+ * Manual context switch. We can use a __nosavereg attribute  as the context 
+ * would be saved by PortSAVE_CONTEXT().  The context is switched and then 
+ * the context of the new task is restored saved. 
+ */
+#pragma asm
+
+	.global _vPortYieldDelayed
+	_vPortYieldDelayed:
+
+	ANDCCR #0xEF							;Disable Interrupts
+	SaveContext								;Save context
+	ORCCR #0x10								;Re-enable Interrupts
+
+	LDI #_dicr, R0
+	BANDL #0x0E, @R0						;Clear Delayed interrupt flag
+
+	CALL32	 _vTaskSwitchContext,R12		;Switch context if required
+
+	ANDCCR #0xEF							;Disable Interrupts
+	RestoreContext							;Restore context
+	ORCCR #0x10								;Re-enable Interrupts
+
+	RETI
+
+#pragma endasm
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch. We can use a __nosavereg attribute  as the context 
+ * would be saved by PortSAVE_CONTEXT().  The context is switched and then 
+ * the context of the new task is restored saved. 
+ */ 	 
+#pragma asm
+
+	.global _vPortYield
+	_vPortYield:
+
+	SaveContext								;Save context
+	CALL32	 _vTaskSwitchContext,R12		;Switch context if required
+	RestoreContext							;Restore context
+	
+	RETI
+
+#pragma endasm
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Softune/MB91460/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Softune/MB91460/portmacro.h
new file mode 100644
index 0000000..ed2ac67
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Softune/MB91460/portmacro.h
@@ -0,0 +1,109 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* Hardware specific includes. */
+#include "mb91467d.h"
+
+/* Standard includes. */
+#include 
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#if configKERNEL_INTERRUPT_PRIORITY != 30
+	#error configKERNEL_INTERRUPT_PRIORITY (set in FreeRTOSConfig.h) must match the ILM value set in the following line - 30 (1Eh) being the default.
+#endif
+#define portDISABLE_INTERRUPTS() __asm(" STILM #1Eh ")
+#define portENABLE_INTERRUPTS() __asm(" STILM #1Fh ")
+
+#define portENTER_CRITICAL()	\
+	__asm(" ST PS,@-R15 ");		\
+	__asm(" ANDCCR #0xef ");	\
+
+
+#define portEXIT_CRITICAL()		\
+	__asm(" LD @R15+,PS ");		\
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			4
+#define portNOP()					__asm( " nop " );
+/*-----------------------------------------------------------*/
+
+/* portYIELD() uses a SW interrupt */
+#define portYIELD()					__asm( " INT #40H " );
+
+/* portYIELD_FROM_ISR() uses delayed interrupt */
+#define portYIELD_FROM_ISR()			DICR_DLYI = 1
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#define portMINIMAL_STACK_SIZE configMINIMAL_STACK_SIZE
+
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Softune/MB96340/__STD_LIB_sbrk.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Softune/MB96340/__STD_LIB_sbrk.c
new file mode 100644
index 0000000..a520aff
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Softune/MB96340/__STD_LIB_sbrk.c
@@ -0,0 +1,28 @@
+/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
+/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
+/* ELIGIBILITY FOR ANY PURPOSES.                                             */
+/*                 (C) Fujitsu Microelectronics Europe GmbH                  */
+/*---------------------------------------------------------------------------
+  __STD_LIB_sbrk.C
+  - Used by heap_3.c for memory accocation and deletion.
+
+/*---------------------------------------------------------------------------*/
+
+#include "FreeRTOSConfig.h"
+#include 
+
+	static  long         brk_siz  =  0;
+	typedef int          _heep_t;
+	#define ROUNDUP(s)   (((s)+sizeof(_heep_t)-1)&~(sizeof(_heep_t)-1))
+	static  _heep_t      _heep[ROUNDUP(configTOTAL_HEAP_SIZE)/sizeof(_heep_t)];
+	#define              _heep_size      ROUNDUP(configTOTAL_HEAP_SIZE)
+
+	extern  char  *sbrk(int  size)
+	{
+	   if  (brk_siz  +  size  >  _heep_size  ||  brk_siz  +  size  <  0)
+
+          return((char*)-1);
+	   brk_siz  +=  size;
+	   return(  (char*)_heep  +  brk_siz  -  size);
+	}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Softune/MB96340/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Softune/MB96340/port.c
new file mode 100644
index 0000000..8ceabc5
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Softune/MB96340/port.c
@@ -0,0 +1,509 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the 16FX port.
+ *----------------------------------------------------------*/
+
+/* 
+ * Get current value of DPR and ADB registers 
+ */
+StackType_t xGet_DPR_ADB_bank( void ); 
+
+/* 
+ * Get current value of DTB and PCB registers 
+ */
+StackType_t xGet_DTB_PCB_bank( void );
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.  This uses RLT0, but
+ * can be done using any given RLT.
+ */
+static void prvSetupRLT0Interrupt( void );
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * We require the address of the pxCurrentTCB variable, but don't want to know
+ * any details of its type. 
+ */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * Macro to save a task context to the task stack. This macro  copies the 
+ * saved context (AH:AL, DPR:ADB, DTB:PCB , PC and PS) from  the   system 
+ * stack to task stack pointed by user stack pointer ( USP  for SMALL and 
+ * MEDIUM memory model amd USB:USP for COMPACT  and LARGE memory model ),
+ * then  it pushes the general purpose registers RW0-RW7  on  to the task 
+ * stack. Finally the  resultant  stack  pointer  value is saved into the 
+ * task  control  block  so  it  can  be retrieved the next time the task 
+ * executes.
+ */ 
+#if( ( configMEMMODEL == portSMALL ) || ( configMEMMODEL == portMEDIUM ) )
+
+	#define portSAVE_CONTEXT()											\
+			{	__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" OR   CCR,#H'20 ");								\
+	    		__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) ");		\
+				__asm(" MOVW A, _pxCurrentTCB ");						\
+				__asm(" MOVW A, SP ");									\
+  				__asm(" SWAPW ");										\
+				__asm(" MOVW @AL, AH ");								\
+				__asm(" OR   CCR,#H'20 ");								\
+			}
+
+/* 
+ * Macro to restore a task context from the task stack.  This is effecti-
+ * vely the reverse of SAVE_CONTEXT(). First the stack pointer  value
+ * (USP for SMALL and MEDIUM memory model amd  USB:USP  for  COMPACT  and 
+ * LARGE memory model ) is loaded from the task  control block.  Next the 
+ * value of all the general purpose registers RW0-RW7 is retrieved. Fina-
+ * lly it copies of the context ( AH:AL,  DPR:ADB, DTB:PCB, PC and PS) of 
+ * the task to be executed upon RETI from user stack to system stack.  
+ */
+ 
+	#define portRESTORE_CONTEXT()										\
+			{	__asm(" MOVW A, _pxCurrentTCB ");						\
+				__asm(" MOVW A, @A ");									\
+  				__asm(" AND  CCR,#H'DF ");  							\
+  				__asm(" MOVW SP, A ");									\
+				__asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) ");		\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+			}
+		
+#elif( ( configMEMMODEL == portCOMPACT ) || ( configMEMMODEL == portLARGE ) )
+
+	#define portSAVE_CONTEXT()											\
+			{	__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" OR   CCR,#H'20 ");								\
+	    		__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) ");		\
+				__asm(" MOVL A, _pxCurrentTCB ");						\
+				__asm(" MOVL RL2, A ");									\
+				__asm(" MOVW A, SP ");									\
+				__asm(" MOVW @RL2+0, A ");								\
+				__asm(" MOV A, USB ");									\
+				__asm(" MOV @RL2+2, A ");								\
+			}	
+            
+	#define portRESTORE_CONTEXT()										\
+			{	__asm(" MOVL A, _pxCurrentTCB ");						\
+				__asm(" MOVL RL2, A ");									\
+				__asm(" MOVW A, @RL2+0 ");								\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" MOVW SP, A ");									\
+				__asm(" MOV A, @RL2+2 ");								\
+				__asm(" MOV USB, A ");									\
+				__asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) ");		\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+			}
+#endif
+
+/*-----------------------------------------------------------*/	
+
+/* 
+ * Functions for obtaining the current value  of  DPR:ADB, DTB:PCB bank registers
+ */
+ 
+#pragma asm
+
+        .GLOBAL    _xGet_DPR_ADB_bank
+        .GLOBAL    _xGet_DTB_PCB_bank
+        .SECTION   CODE, CODE, ALIGN=1
+
+_xGet_DPR_ADB_bank:
+
+    MOV A, DPR
+    SWAP
+    MOV A, ADB
+    ORW A
+	#if configMEMMODEL == portMEDIUM || configMEMMODEL == portLARGE
+		RETP
+	#elif configMEMMODEL == portSMALL || configMEMMODEL == portCOMPACT   
+		RET
+	#endif 
+
+
+_xGet_DTB_PCB_bank:
+
+    MOV A, DTB
+    SWAP
+    MOV A, PCB
+    ORW A
+	#if configMEMMODEL == portMEDIUM || configMEMMODEL == portLARGE
+		RETP
+	#elif configMEMMODEL == portSMALL || configMEMMODEL == portCOMPACT   
+		RET
+	#endif 
+
+#pragma endasm
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been called.
+ * 
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Place a few bytes of known values on the bottom of the stack. 
+	This is just useful for debugging. */
+	*pxTopOfStack = 0x1111;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2222;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x3333;
+	pxTopOfStack--;
+
+	/* Once the task is called the task  would  push  the  pointer to the
+	parameter onto the stack. Hence here the pointer would be copied to the stack
+	first.  When using the COMPACT or LARGE memory model the pointer would be 24 
+	bits, and when using the SMALL or MEDIUM memory model the pointer would be 16 
+	bits. */ 
+	#if( ( configMEMMODEL == portCOMPACT ) || ( configMEMMODEL == portLARGE ) )
+	{
+		*pxTopOfStack = ( StackType_t ) ( ( uint32_t ) ( pvParameters ) >> 16 );
+		pxTopOfStack--;         
+	}
+	#endif
+
+    *pxTopOfStack = ( StackType_t ) ( pvParameters );
+    pxTopOfStack--;                  
+    
+    /* This is redundant push to the stack. This is required in order to introduce 
+    an offset so that the task accesses a parameter correctly that is passed on to 
+    the task stack. */
+	#if( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) )
+	{
+		*pxTopOfStack = ( xGet_DTB_PCB_bank() & 0xff00 ) | ( ( ( int32_t ) ( pxCode ) >> 16 ) & 0xff );      
+		pxTopOfStack--;       
+	}
+	#endif
+
+    /* This is redundant push to the stack. This is required in order to introduce 
+    an offset so the task correctly accesses the parameter passed on the task stack. */
+    *pxTopOfStack = ( StackType_t ) ( pxCode );
+    pxTopOfStack--;       
+
+    /* PS - User Mode, ILM=7, RB=0, Interrupts enabled,USP */
+    *pxTopOfStack = 0xE0C0;							
+	pxTopOfStack--; 
+
+	/* PC */
+	*pxTopOfStack = ( StackType_t ) ( pxCode );     
+    pxTopOfStack--;      
+    
+    /* DTB | PCB */
+	#if configMEMMODEL == portSMALL || configMEMMODEL == portCOMPACT
+	{
+		*pxTopOfStack = xGet_DTB_PCB_bank();         	
+		pxTopOfStack--;
+	}
+	#endif
+
+	/* DTB | PCB, in case of MEDIUM and LARGE memory models, PCB would be used
+	along with PC to indicate the start address of the function. */
+	#if( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) )
+	{
+		*pxTopOfStack = ( xGet_DTB_PCB_bank() & 0xff00 ) | ( ( ( int32_t ) ( pxCode ) >> 16 ) & 0xff );
+		pxTopOfStack--;       
+	}
+	#endif
+
+	/* DPR | ADB  */
+	*pxTopOfStack = xGet_DPR_ADB_bank();				
+	pxTopOfStack--;
+    
+	/* AL */
+	*pxTopOfStack = ( StackType_t ) 0x9999;		
+	pxTopOfStack--;
+
+	/* AH */
+	*pxTopOfStack = ( StackType_t ) 0xAAAA;		
+	pxTopOfStack--;
+	
+	/* Next the general purpose registers. */
+	*pxTopOfStack = ( StackType_t ) 0x7777;	/* RW7 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x6666;	/* RW6 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x5555;	/* RW5 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x4444;	/* RW4 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x3333;	/* RW3 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x2222;	/* RW2 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x1111;	/* RW1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x8888;	/* RW0 */
+		
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupRLT0Interrupt( void )
+{
+/* The peripheral clock divided by 16 is used by the timer. */
+const uint16_t usReloadValue = ( uint16_t ) ( ( ( configCLKP1_CLOCK_HZ / configTICK_RATE_HZ ) / 16UL ) - 1UL );
+
+	/* set reload value = 34999+1, TICK Interrupt after 10 ms @ 56MHz of CLKP1 */
+	TMRLR0 = usReloadValue;    
+    
+    /* prescaler 1:16, reload, interrupt enable, count enable, trigger */
+    TMCSR0 = 0x041B;    
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Setup the hardware to generate the tick. */
+	prvSetupRLT0Interrupt();
+	
+	/* Restore the context of the first task that is going to run. */
+	portRESTORE_CONTEXT();
+
+	/* Simulate a function call end as generated by the compiler.  We will now
+	jump to the start of the task the context of which we have just restored. */	
+	__asm(" reti ");
+
+
+	/* Should not get here. */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented - unlikely to ever be required as there is nothing to
+	return to. */
+}
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * The interrupt service routine used depends on whether the pre-emptive
+ * scheduler is being used or not.
+ */
+
+#if configUSE_PREEMPTION == 1
+
+	/* 
+	 * Tick ISR for preemptive scheduler.  We can use a __nosavereg attribute
+	 * as the context is to be saved by the portSAVE_CONTEXT() macro, not the
+	 * compiler generated code.  The tick count is incremented after the context 
+	 * is saved. 
+	 */
+	__nosavereg __interrupt void prvRLT0_TICKISR( void )
+	{
+		/* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */
+		__DI();
+		
+		/* Save the context of the interrupted task. */
+		portSAVE_CONTEXT();
+		
+		/* Enable interrupts */
+		__EI();
+		
+		/* Clear RLT0 interrupt flag */
+		TMCSR0_UF = 0;      
+		
+		/* Increment the tick count then switch to the highest priority task
+		that is ready to run. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			vTaskSwitchContext();
+		}
+
+		/* Disable interrupts so that portRESTORE_CONTEXT() is not interrupted */
+		__DI();
+		
+		/* Restore the context of the new task. */
+		portRESTORE_CONTEXT();
+		
+		/* Enable interrupts */
+		__EI();
+	}
+
+#else
+
+	/*
+	 * Tick ISR for the cooperative scheduler.  All this does is increment the
+	 * tick count.  We don't need to switch context, this can only be done by
+	 * manual calls to taskYIELD();
+	 */
+	__interrupt void prvRLT0_TICKISR( void )
+	{
+		/* Clear RLT0 interrupt flag */
+		TMCSR0_UF = 0;  
+		
+		xTaskIncrementTick();
+	}
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch. We can use a __nosavereg attribute  as the context 
+ * is to be saved by the portSAVE_CONTEXT() macro, not the compiler generated 
+ * code.
+ */
+__nosavereg __interrupt void vPortYield( void )
+{
+	/* Save the context of the interrupted task. */
+	portSAVE_CONTEXT();
+	
+	/* Switch to the highest priority task that is ready to run. */
+	vTaskSwitchContext();
+	
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+__nosavereg __interrupt void vPortYieldDelayed( void )
+{    
+    /* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */      
+	__DI();
+	
+	/* Save the context of the interrupted task. */
+	portSAVE_CONTEXT();
+	
+	/* Enable interrupts */
+	__EI();
+				
+	/* Clear delayed interrupt flag */
+    __asm (" CLRB  03A4H:0 ");
+	
+	/* Switch to the highest priority task that is ready to run. */
+	vTaskSwitchContext();
+	
+	/* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */   
+	__DI();
+	
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT();
+
+	/* Enable interrupts */
+	__EI();
+}	
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Softune/MB96340/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Softune/MB96340/portmacro.h
new file mode 100644
index 0000000..2e14db8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Softune/MB96340/portmacro.h
@@ -0,0 +1,116 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* Standard includes. */
+#include 
+
+/* Constants denoting the available memory models.  These are used within
+FreeRTOSConfig.h to set the configMEMMODEL value. */
+#define portSMALL     0
+#define portMEDIUM    1
+#define portCOMPACT   2
+#define portLARGE     3
+
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint16_t
+#define portBASE_TYPE	short
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+#if configKERNEL_INTERRUPT_PRIORITY != 6
+	#error configKERNEL_INTERRUPT_PRIORITY (set in FreeRTOSConfig.h) must match the ILM value set in the following line - #06H being the default.
+#endif
+#define portDISABLE_INTERRUPTS()	__asm(" MOV ILM, #06h ")
+#define portENABLE_INTERRUPTS()		__asm(" MOV ILM, #07h ")
+
+#define portENTER_CRITICAL()								\
+		{	__asm(" PUSHW PS ");							\
+			portDISABLE_INTERRUPTS();						\
+		}
+
+#define portEXIT_CRITICAL()									\
+		{	__asm(" POPW PS ");								\
+		}
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			2
+#define portNOP()					__asm( " NOP " );
+/*-----------------------------------------------------------*/
+
+/* portYIELD() uses SW interrupt */
+#define portYIELD()					__asm( " INT #122 " );
+
+/* portYIELD_FROM_ISR() uses delayed interrupt */
+#define portYIELD_FROM_ISR()		 __asm( " SETB  03A4H:0 " );
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#define portMINIMAL_STACK_SIZE configMINIMAL_STACK_SIZE
+
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port.c
new file mode 100644
index 0000000..a141d33
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port.c
@@ -0,0 +1,263 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM4F port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to manipulate the NVIC. */
+#define portNVIC_SYSTICK_CTRL		( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD		( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSPRI2			( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK		0x00000004
+#define portNVIC_SYSTICK_INT		0x00000002
+#define portNVIC_SYSTICK_ENABLE		0x00000001
+#define portNVIC_PENDSV_PRI			( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )
+#define portNVIC_SYSTICK_PRI		( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK			( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR					( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS	( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR			( 0x01000000 )
+#define portINITIAL_EXC_RETURN		( 0xfffffffd )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
+
+/* The priority used by the kernel is assigned to a variable to make access
+from inline assembler easier. */
+const uint32_t ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY;
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+/*
+ * Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void SysTick_Handler( void );
+
+/*
+ * Functions defined in port_asm.asm.
+ */
+extern void vPortEnableVFP( void );
+extern void vPortStartFirstTask( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/* This exists purely to allow the const to be used from within the
+port_asm.asm assembly file. */
+const uint32_t ulMaxSyscallInterruptPriorityConst = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+
+	/* Offset added to account for the way the MCU uses the stack on entry/exit
+	of interrupts, and to ensure alignment. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+
+	/* Save code space by skipping register initialisation. */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+
+	/* A save method is being used that requires each task to maintain its
+	own exec return value. */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( ulCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+	configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	*(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
+	*(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	ulCriticalNesting = 0;
+
+	/* Ensure the VFP is enabled - it should be anyway. */
+	vPortEnableVFP();
+
+	/* Lazy save always. */
+	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+	/* Start the first task. */
+	vPortStartFirstTask();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortYield( void )
+{
+	/* Set a PendSV to request a context switch. */
+	*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
+
+	/* Barriers are normally not required but do ensure the code is completely
+	within the specified behaviour for the architecture. */
+	__DSB();
+	__ISB();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	ulCriticalNesting++;
+	__DSB();
+	__ISB();
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( ulCriticalNesting == 1 )
+	{
+		configASSERT( ( ( *(portNVIC_INT_CTRL) ) & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( ulCriticalNesting );
+	ulCriticalNesting--;
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void )
+{
+uint32_t ulDummy;
+
+	ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+void prvSetupTimerInterrupt( void )
+{
+	/* Configure SysTick to interrupt at the requested rate. */
+	*(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	*(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port_asm.asm b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port_asm.asm
new file mode 100644
index 0000000..c8204b8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port_asm.asm
@@ -0,0 +1,236 @@
+;/*
+; * FreeRTOS Kernel V10.2.1
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * http://www.FreeRTOS.org
+; * http://aws.amazon.com/freertos
+; *
+; * 1 tab == 4 spaces!
+; */
+
+
+	.extern pxCurrentTCB
+	.extern vTaskSwitchContext
+	.extern ulMaxSyscallInterruptPriorityConst
+
+	.global _vector_14
+	.global _lc_ref__vector_pp_14
+	.global SVC_Handler
+	.global vPortStartFirstTask
+	.global vPortEnableVFP
+	.global ulPortSetInterruptMask
+	.global vPortClearInterruptMask
+
+;-----------------------------------------------------------
+
+	.section .text
+	.thumb
+	.align 4
+_vector_14: .type func
+
+	mrs r0, psp
+	isb
+
+	;Get the location of the current TCB.
+	ldr.w	r3, =pxCurrentTCB
+	ldr	r2, [r3]
+
+	;Is the task using the FPU context?  If so, push high vfp registers.
+	tst r14, #0x10
+	it eq
+	vstmdbeq r0!, {s16-s31}
+
+	;Save the core registers.
+	stmdb r0!, {r4-r11, r14}
+
+	;Save the new top of stack into the first member of the TCB.
+	str r0, [r2]
+
+	stmdb sp!, {r0, r3}
+	ldr.w r0, =ulMaxSyscallInterruptPriorityConst
+	ldr r0, [r0]
+	msr basepri, r0
+	bl vTaskSwitchContext
+	mov r0, #0
+	msr basepri, r0
+	ldmia sp!, {r0, r3}
+
+	;The first item in pxCurrentTCB is the task top of stack.
+	ldr r1, [r3]
+	ldr r0, [r1]
+
+	;Pop the core registers.
+	ldmia r0!, {r4-r11, r14}
+
+	;Is the task using the FPU context?  If so, pop the high vfp registers too.
+	tst r14, #0x10
+	it eq
+	vldmiaeq r0!, {s16-s31}
+
+	msr psp, r0
+	isb
+	bx r14
+
+	.size	_vector_14, $-_vector_14
+	.endsec
+
+;-----------------------------------------------------------
+
+; This function is an XMC4000 silicon errata workaround.  It will get used when
+; the SILICON_BUG_PMC_CM_001 linker macro is defined.
+	.section .text
+	.thumb
+	.align 4
+_lc_ref__vector_pp_14: .type func
+
+	mrs r0, psp
+	isb
+
+	;Get the location of the current TCB.
+	ldr.w	r3, =pxCurrentTCB
+	ldr	r2, [r3]
+
+	;Is the task using the FPU context?  If so, push high vfp registers.
+	tst r14, #0x10
+	it eq
+	vstmdbeq r0!, {s16-s31}
+
+	;Save the core registers.
+	stmdb r0!, {r4-r11, r14}
+
+	;Save the new top of stack into the first member of the TCB.
+	str r0, [r2]
+
+	stmdb sp!, {r3}
+	ldr.w r0, =ulMaxSyscallInterruptPriorityConst
+	ldr r0, [r0]
+	msr basepri, r0
+	bl vTaskSwitchContext
+	mov r0, #0
+	msr basepri, r0
+	ldmia sp!, {r3}
+
+	;The first item in pxCurrentTCB is the task top of stack.
+	ldr r1, [r3]
+	ldr r0, [r1]
+
+	;Pop the core registers.
+	ldmia r0!, {r4-r11, r14}
+
+	;Is the task using the FPU context?  If so, pop the high vfp registers too.
+	tst r14, #0x10
+	it eq
+	vldmiaeq r0!, {s16-s31}
+
+	msr psp, r0
+	isb
+	push { lr }
+	pop { pc } ; XMC4000 specific errata workaround.  Do not used "bx lr" here.
+
+	.size	_lc_ref__vector_pp_14, $-_lc_ref__vector_pp_14
+	.endsec
+
+;-----------------------------------------------------------
+
+	.section .text
+	.thumb
+	.align 4
+SVC_Handler: .type func
+	;Get the location of the current TCB.
+	ldr.w	r3, =pxCurrentTCB
+	ldr r1, [r3]
+	ldr r0, [r1]
+	;Pop the core registers.
+	ldmia r0!, {r4-r11, r14}
+	msr psp, r0
+	isb
+	mov r0, #0
+	msr	basepri, r0
+	bx r14
+	.size	SVC_Handler, $-SVC_Handler
+	.endsec
+
+;-----------------------------------------------------------
+
+	.section .text
+	.thumb
+	.align 4
+vPortStartFirstTask .type func
+	;Use the NVIC offset register to locate the stack.
+	ldr.w r0, =0xE000ED08
+	ldr r0, [r0]
+	ldr r0, [r0]
+	;Set the msp back to the start of the stack.
+	msr msp, r0
+	;Call SVC to start the first task.
+	cpsie i
+	cpsie f
+	dsb
+	isb
+	svc 0
+	.size	vPortStartFirstTask, $-vPortStartFirstTask
+	.endsec
+
+;-----------------------------------------------------------
+
+	.section .text
+	.thumb
+	.align 4
+vPortEnableVFP .type func
+	;The FPU enable bits are in the CPACR.
+	ldr.w r0, =0xE000ED88
+	ldr	r1, [r0]
+
+	;Enable CP10 and CP11 coprocessors, then save back.
+	orr	r1, r1, #( 0xf << 20 )
+	str r1, [r0]
+	bx	r14
+	.size	vPortEnableVFP, $-vPortEnableVFP
+	.endsec
+
+;-----------------------------------------------------------
+
+	.section .text
+	.thumb
+	.align 4
+ulPortSetInterruptMask:
+	mrs r0, basepri
+	ldr.w r1, =ulMaxSyscallInterruptPriorityConst
+	ldr r1, [r1]
+	msr basepri, r1
+	bx r14
+	.size	ulPortSetInterruptMask, $-ulPortSetInterruptMask
+	.endsec
+
+;-----------------------------------------------------------
+
+	.section .text
+	.thumb
+	.align 4
+vPortClearInterruptMask:
+	msr basepri, r0
+	bx r14
+	.size	vPortClearInterruptMask, $-vPortClearInterruptMask
+	.endsec
+
+;-----------------------------------------------------------
+
+	.end
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h
new file mode 100644
index 0000000..a2d421c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+extern void vPortYield( void );
+#define portNVIC_INT_CTRL			( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_PENDSVSET			0x10000000
+#define portYIELD()					vPortYield()
+
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+
+/*
+ * Set basepri to portMAX_SYSCALL_INTERRUPT_PRIORITY without effecting other
+ * registers.  r0 is clobbered.
+ */
+#define portSET_INTERRUPT_MASK() __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+
+/*
+ * Set basepri back to 0 without effective other registers.
+ * r0 is clobbered.  FAQ:  Setting BASEPRI to 0 is not a bug.  Please see
+ * http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing.
+ */
+#define portCLEAR_INTERRUPT_MASK() __set_BASEPRI( 0 )
+
+extern uint32_t ulPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( uint32_t ulNewMask );
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask( x )
+
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()	portSET_INTERRUPT_MASK()
+#define portENABLE_INTERRUPTS()		portCLEAR_INTERRUPT_MASK()
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#define portNOP()
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/GCC/RISC-V/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/GCC/RISC-V/port.c
new file mode 100644
index 0000000..3d96ce8
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/GCC/RISC-V/port.c
@@ -0,0 +1,385 @@
+/*
+    FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution and was contributed
+    to the project by Technolution B.V. (www.technolution.nl,
+    freertos-riscv@technolution.eu) under the terms of the FreeRTOS
+    contributors license.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the RISC-V port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "portmacro.h"
+
+#include "riscv_hal.h"
+
+#ifdef __riscv64
+# define STORE    sd
+# define LOAD     ld
+# define REGBYTES 8
+#else
+# define STORE    sw
+# define LOAD     lw
+# define REGBYTES 4
+#endif
+/* A variable is used to keep track of the critical section nesting.  This
+variable has to be stored as part of the task context and must be initialized to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts.  As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/* Contains context when starting scheduler, save all 31 registers */
+#ifdef __gracefulExit
+BaseType_t xStartContext[31] = {0};
+#endif
+
+
+typedef struct
+{
+	uint32_t val_low;
+	uint32_t val_high;
+}riscv_machine_timer_t;
+
+static volatile riscv_machine_timer_t *mtime = (riscv_machine_timer_t *)0x4400BFF8;
+
+static volatile riscv_machine_timer_t *mtimecmp = (riscv_machine_timer_t *)0x44004000;
+
+/*
+ * Setup the timer to generate the tick interrupts.
+ */
+void vPortSetupTimer( void );
+
+/*
+ * Set the next interval for the timer
+ */
+static void prvSetNextTimerInterrupt( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* Sets the next timer interrupt
+ * Reads previous timer compare register, and adds tickrate */
+static void prvSetNextTimerInterrupt(void)
+{
+	uint64_t time;
+
+	time = mtime->val_low;
+	time |= ((uint64_t)mtime->val_high << 32);
+
+	time += (configCPU_CLOCK_HZ / configTICK_RATE_HZ);
+
+	mtimecmp->val_low = (uint32_t)(time & 0xFFFFFFFF);
+	mtimecmp->val_high = (uint32_t)((time >> 32) & 0xFFFFFFFF);
+
+	/* Enable timer interrupt */
+	__asm volatile("csrs mie,%0"::"r"(0x80));
+}
+/*-----------------------------------------------------------*/
+
+/* Sets and enable the timer interrupt */
+void vPortSetupTimer(void)
+{
+	uint64_t time;
+
+	time = mtime->val_low;
+	time |= ((uint64_t)mtime->val_high << 32);
+
+	time += (configCPU_CLOCK_HZ / configTICK_RATE_HZ);
+
+	mtimecmp->val_low = (uint32_t)(time & 0xFFFFFFFF);
+	mtimecmp->val_high = (uint32_t)((time >> 32) & 0xFFFFFFFF);
+
+
+	/* Enable timer interrupt */
+	__asm volatile("csrs mie,%0"::"r"(0x80));
+}
+/*-----------------------------------------------------------*/
+
+void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+/* Clear current interrupt mask and set given mask */
+void vPortClearInterruptMask(int mask)
+{
+	__asm volatile("csrw mie, %0"::"r"(mask));
+}
+/*-----------------------------------------------------------*/
+
+/* Set interrupt mask and return current interrupt enable register */
+int vPortSetInterruptMask(void)
+{
+	int ret;
+	__asm volatile("csrr %0,mie":"=r"(ret));
+	__asm volatile("csrc mie,%0"::"i"(7));
+	return ret;
+}
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+	register int *tp asm("x3");
+	pxTopOfStack--;
+	*pxTopOfStack = (portSTACK_TYPE)pxCode;			/* Start address */
+	pxTopOfStack -= 22;
+	*pxTopOfStack = (portSTACK_TYPE)pvParameters;	/* Register a0 */
+	pxTopOfStack -= 6;
+	*pxTopOfStack = (portSTACK_TYPE)tp; /* Register thread pointer */
+	pxTopOfStack -= 3;
+	*pxTopOfStack = (portSTACK_TYPE)prvTaskExitError; /* Register ra */
+	
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSysTickHandler( void )
+{
+	/*Save Context*/
+	{
+		__asm volatile("lw	t0, pxCurrentTCB");
+		__asm volatile("sw	a2, 0x0(t0)");
+	}
+
+	/* Increment the RTOS tick. */
+	prvSetNextTimerInterrupt();
+
+	/*Switch task */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		vTaskSwitchContext();
+	}
+
+	/*Restore Context*/
+	{
+		__asm volatile("lw	sp, pxCurrentTCB");
+		__asm volatile("lw	sp, 0x0(sp)");
+
+		__asm volatile("lw	t0, 31 * 4(sp)");
+		__asm volatile("csrw	mepc, t0");
+
+		__asm volatile("lw	x1, 0x0(sp)");
+		__asm volatile("lw   x4, 3 * 4(sp)");
+		__asm volatile("lw   x5, 4 * 4(sp)");
+		__asm volatile("lw   x6, 5 * 4(sp)");
+		__asm volatile("lw   x7, 6 * 4(sp)");
+		__asm volatile("lw   x8, 7 * 4(sp)");
+		__asm volatile("lw   x9, 8 * 4(sp)");
+		__asm volatile("lw   x10, 9 * 4(sp)");
+		__asm volatile("lw   x11, 10 * 4(sp)");
+		__asm volatile("lw   x12, 11 * 4(sp)");
+		__asm volatile("lw   x13, 12 * 4(sp)");
+		__asm volatile("lw   x14, 13 * 4(sp)");
+		__asm volatile("lw   x15, 14 * 4(sp)");
+		__asm volatile("lw   x16, 15 * 4(sp)");
+		__asm volatile("lw   x17, 16 * 4(sp)");
+		__asm volatile("lw   x18, 17 * 4(sp)");
+		__asm volatile("lw   x19, 18 * 4(sp)");
+		__asm volatile("lw   x20, 19 * 4(sp)");
+		__asm volatile("lw   x21, 20 * 4(sp)");
+		__asm volatile("lw   x22, 21 * 4(sp)");
+		__asm volatile("lw   x23, 22 * 4(sp)");
+		__asm volatile("lw   x24, 23 * 4(sp)");
+		__asm volatile("lw   x25, 24 * 4(sp)");
+		__asm volatile("lw   x26, 25 * 4(sp)");
+		__asm volatile("lw   x27, 26 * 4(sp)");
+		__asm volatile("lw   x28, 27 * 4(sp)");
+		__asm volatile("lw   x29, 28 * 4(sp)");
+		__asm volatile("lw   x30, 29 * 4(sp)");
+		__asm volatile("lw   x31, 30 * 4(sp)");
+
+		__asm volatile("addi	sp, sp, 4 * 32");
+
+		__asm volatile("mret");
+	}
+}
+uint32_t g_startscheduler = 0;
+BaseType_t xPortStartScheduler( void )
+{
+	vPortSetupTimer();
+	uxCriticalNesting = 0;
+	g_startscheduler = 1;
+	__enable_irq();
+
+	raise_soft_interrupt();
+
+	/*Should not get here*/
+	return pdFALSE;
+}
+
+void Software_IRQHandler(void)
+{
+	if(1 == g_startscheduler)
+	{
+		g_startscheduler = 2; //skip the save n switch context first time when scheduler is starting.
+	}
+	else
+	{
+		/*Save Context*/
+		{
+			__asm volatile("lw	t0, pxCurrentTCB");
+			__asm volatile("sw	a2, 0x0(t0)");
+		}
+
+		vTaskSwitchContext();
+	}
+
+	/*Restore Context*/
+	{
+		__asm volatile("lw	sp, pxCurrentTCB");
+		__asm volatile("lw	sp, 0x0(sp)");
+
+		__asm volatile("lw	t0, 31 * 4(sp)");
+		__asm volatile("csrw	mepc, t0");
+
+		__asm volatile("lw	x1, 0x0(sp)");
+		__asm volatile("lw   x4, 3 * 4(sp)");
+		__asm volatile("lw   x5, 4 * 4(sp)");
+		__asm volatile("lw   x6, 5 * 4(sp)");
+		__asm volatile("lw   x7, 6 * 4(sp)");
+		__asm volatile("lw   x8, 7 * 4(sp)");
+		__asm volatile("lw   x9, 8 * 4(sp)");
+		__asm volatile("lw   x10, 9 * 4(sp)");
+		__asm volatile("lw   x11, 10 * 4(sp)");
+		__asm volatile("lw   x12, 11 * 4(sp)");
+		__asm volatile("lw   x13, 12 * 4(sp)");
+		__asm volatile("lw   x14, 13 * 4(sp)");
+		__asm volatile("lw   x15, 14 * 4(sp)");
+		__asm volatile("lw   x16, 15 * 4(sp)");
+		__asm volatile("lw   x17, 16 * 4(sp)");
+		__asm volatile("lw   x18, 17 * 4(sp)");
+		__asm volatile("lw   x19, 18 * 4(sp)");
+		__asm volatile("lw   x20, 19 * 4(sp)");
+		__asm volatile("lw   x21, 20 * 4(sp)");
+		__asm volatile("lw   x22, 21 * 4(sp)");
+		__asm volatile("lw   x23, 22 * 4(sp)");
+		__asm volatile("lw   x24, 23 * 4(sp)");
+		__asm volatile("lw   x25, 24 * 4(sp)");
+		__asm volatile("lw   x26, 25 * 4(sp)");
+		__asm volatile("lw   x27, 26 * 4(sp)");
+		__asm volatile("lw   x28, 27 * 4(sp)");
+		__asm volatile("lw   x29, 28 * 4(sp)");
+		__asm volatile("lw   x30, 29 * 4(sp)");
+		__asm volatile("lw   x31, 30 * 4(sp)");
+
+		__asm volatile("addi	sp, sp, 4 * 32");
+
+		//PRCI->MSIP[0] = 0x00;
+
+		__asm volatile("addi sp, sp, -1*4");
+		__asm volatile("sw t0, 0(sp)");
+		__asm volatile("li t0, 0x44000000");	// address of PRCI->MSIP[0]
+		__asm volatile("sw zero,0(t0)");
+		__asm volatile("lw t0, 0(sp)");
+		__asm volatile("addi sp, sp, 1*4");
+
+		__asm volatile("mret");
+	}
+}
+
+void vPortYield( void )
+{
+	raise_soft_interrupt();
+}
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/GCC/RISC-V/portasm.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/GCC/RISC-V/portasm.S
new file mode 100644
index 0000000..78b2265
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/GCC/RISC-V/portasm.S
@@ -0,0 +1,282 @@
+/*
+    FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution and was contributed
+    to the project by Technolution B.V. (www.technolution.nl,
+    freertos-riscv@technolution.eu) under the terms of the FreeRTOS
+    contributors license.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry''s de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+
+#ifdef __riscv64
+# define STORE    sd
+# define LOAD     ld
+# define REGBYTES 8
+#else
+# define STORE    sw
+# define LOAD     lw
+# define REGBYTES 4
+#endif
+
+#define MSTATUS_PRV1 0x1800
+
+.global portSAVE_CONTEXT
+.global portRESTORE_CONTEXT
+
+//.global xPortStartScheduler
+.global vPortYield
+.global vTaskIncrementTick
+.global vPortEndScheduler
+.global xExitStack
+
+
+/* Macro for saving task context */
+.macro portSAVE_CONTEXT
+	.global	pxCurrentTCB
+	/* make room in stack */
+	addi	sp, sp, -REGBYTES * 32
+
+	/* Save Context */
+	STORE	x1, 0x0(sp)
+	STORE	x2, 1 * REGBYTES(sp)
+	STORE	x3, 2 * REGBYTES(sp)
+	STORE	x4, 3 * REGBYTES(sp)
+	STORE	x5, 4 * REGBYTES(sp)
+	STORE	x6, 5 * REGBYTES(sp)
+	STORE	x7, 6 * REGBYTES(sp)
+	STORE	x8, 7 * REGBYTES(sp)
+	STORE	x9, 8 * REGBYTES(sp)
+	STORE	x10, 9 * REGBYTES(sp)
+	STORE	x11, 10 * REGBYTES(sp)
+	STORE	x12, 11 * REGBYTES(sp)
+	STORE	x13, 12 * REGBYTES(sp)
+	STORE	x14, 13 * REGBYTES(sp)
+	STORE	x15, 14 * REGBYTES(sp)
+	STORE	x16, 15 * REGBYTES(sp)
+	STORE	x17, 16 * REGBYTES(sp)
+	STORE	x18, 17 * REGBYTES(sp)
+	STORE	x19, 18 * REGBYTES(sp)
+	STORE	x20, 19 * REGBYTES(sp)
+	STORE	x21, 20 * REGBYTES(sp)
+	STORE	x22, 21 * REGBYTES(sp)
+	STORE	x23, 22 * REGBYTES(sp)
+	STORE	x24, 23 * REGBYTES(sp)
+	STORE	x25, 24 * REGBYTES(sp)
+	STORE	x26, 25 * REGBYTES(sp)
+	STORE	x27, 26 * REGBYTES(sp)
+	STORE	x28, 27 * REGBYTES(sp)
+	STORE	x29, 28 * REGBYTES(sp)
+	STORE	x30, 29 * REGBYTES(sp)
+	STORE	x31, 30 * REGBYTES(sp)
+
+	/* Store current stackpointer in task control block (TCB) */
+	LOAD	t0, pxCurrentTCB	//pointer
+	STORE	sp, 0x0(t0)
+	.endm
+
+/* Saves current error program counter (EPC) as task program counter */
+.macro portSAVE_EPC
+  	csrr	t0, mepc
+	STORE	t0, 31 * REGBYTES(sp)
+	.endm
+
+/* Saves current return adress (RA) as task program counter */
+.macro portSAVE_RA
+	STORE	ra, 31 * REGBYTES(sp)
+	.endm
+
+/* Macro for restoring task context */
+.macro portRESTORE_CONTEXT
+
+	.global	pxCurrentTCB
+	/* Load stack pointer from the current TCB */
+	LOAD	sp, pxCurrentTCB
+	LOAD	sp, 0x0(sp)
+
+	/* Load task program counter */
+	LOAD	t0, 31 * REGBYTES(sp)
+  	csrw	mepc, t0
+
+	/* Restore registers,
+	   Skip global pointer because that does not change */
+	LOAD	x1, 0x0(sp)
+	LOAD	x4, 3 * REGBYTES(sp)
+	LOAD	x5, 4 * REGBYTES(sp)
+	LOAD	x6, 5 * REGBYTES(sp)
+	LOAD	x7, 6 * REGBYTES(sp)
+	LOAD	x8, 7 * REGBYTES(sp)
+	LOAD	x9, 8 * REGBYTES(sp)
+	LOAD	x10, 9 * REGBYTES(sp)
+	LOAD	x11, 10 * REGBYTES(sp)
+	LOAD	x12, 11 * REGBYTES(sp)
+	LOAD	x13, 12 * REGBYTES(sp)
+	LOAD	x14, 13 * REGBYTES(sp)
+	LOAD	x15, 14 * REGBYTES(sp)
+	LOAD	x16, 15 * REGBYTES(sp)
+	LOAD	x17, 16 * REGBYTES(sp)
+	LOAD	x18, 17 * REGBYTES(sp)
+	LOAD	x19, 18 * REGBYTES(sp)
+	LOAD	x20, 19 * REGBYTES(sp)
+	LOAD	x21, 20 * REGBYTES(sp)
+	LOAD	x22, 21 * REGBYTES(sp)
+	LOAD	x23, 22 * REGBYTES(sp)
+	LOAD	x24, 23 * REGBYTES(sp)
+	LOAD	x25, 24 * REGBYTES(sp)
+	LOAD	x26, 25 * REGBYTES(sp)
+	LOAD	x27, 26 * REGBYTES(sp)
+	LOAD	x28, 27 * REGBYTES(sp)
+	LOAD	x29, 28 * REGBYTES(sp)
+	LOAD	x30, 29 * REGBYTES(sp)
+	LOAD	x31, 30 * REGBYTES(sp)
+
+	addi	sp, sp, REGBYTES * 32
+
+	/* Enable global interupt */
+    csrs mstatus,8
+
+	ret
+	.endm
+
+
+/*
+xPortStartScheduler:
+#ifdef __gracefulExit
+
+	la		t0, xStartContext
+	STORE	x1, 0x0(t0)
+	STORE	x2, 1 * REGBYTES(t0)
+	STORE	x3, 2 * REGBYTES(t0)
+	STORE	x4, 3 * REGBYTES(t0)
+	STORE	x5, 4 * REGBYTES(t0)
+	STORE	x6, 5 * REGBYTES(t0)
+	STORE	x7, 6 * REGBYTES(t0)
+	STORE	x8, 7 * REGBYTES(t0)
+	STORE	x9, 8 * REGBYTES(t0)
+	STORE	x10, 9 * REGBYTES(t0)
+	STORE	x11, 10 * REGBYTES(t0)
+	STORE	x12, 11 * REGBYTES(t0)
+	STORE	x13, 12 * REGBYTES(t0)
+	STORE	x14, 13 * REGBYTES(t0)
+	STORE	x15, 14 * REGBYTES(t0)
+	STORE	x16, 15 * REGBYTES(t0)
+	STORE	x17, 16 * REGBYTES(t0)
+	STORE	x18, 17 * REGBYTES(t0)
+	STORE	x19, 18 * REGBYTES(t0)
+	STORE	x20, 19 * REGBYTES(t0)
+	STORE	x21, 20 * REGBYTES(t0)
+	STORE	x22, 21 * REGBYTES(t0)
+	STORE	x23, 22 * REGBYTES(t0)
+	STORE	x24, 23 * REGBYTES(t0)
+	STORE	x25, 24 * REGBYTES(t0)
+	STORE	x26, 25 * REGBYTES(t0)
+	STORE	x27, 26 * REGBYTES(t0)
+	STORE	x28, 27 * REGBYTES(t0)
+	STORE	x29, 28 * REGBYTES(t0)
+	STORE	x30, 29 * REGBYTES(t0)
+	STORE	x31, 30 * REGBYTES(t0)
+#endif
+	jal		vPortSetupTimer
+	portRESTORE_CONTEXT
+*/
+
+vPortEndScheduler:
+#ifdef __gracefulExit
+	/* Load current context from xStartContext */
+	la		t0, xStartContext
+	LOAD	x1, 0x0(t0)
+	LOAD	x2, 1 * REGBYTES(t0)
+	LOAD	x3, 2 * REGBYTES(t0)
+	LOAD	x4, 3 * REGBYTES(t0)
+	LOAD	x5, 4 * REGBYTES(t0)
+	LOAD	x6, 5 * REGBYTES(t0)
+	LOAD	x7, 6 * REGBYTES(t0)
+	LOAD	x8, 7 * REGBYTES(t0)
+	LOAD	x9, 8 * REGBYTES(t0)
+	LOAD	x10, 9 * REGBYTES(t0)
+	LOAD	x11, 10 * REGBYTES(t0)
+	LOAD	x12, 11 * REGBYTES(t0)
+	LOAD	x13, 12 * REGBYTES(t0)
+	LOAD	x14, 13 * REGBYTES(t0)
+	LOAD	x15, 14 * REGBYTES(t0)
+	LOAD	x16, 15 * REGBYTES(t0)
+	LOAD	x17, 16 * REGBYTES(t0)
+	LOAD	x18, 17 * REGBYTES(t0)
+	LOAD	x19, 18 * REGBYTES(t0)
+	LOAD	x20, 19 * REGBYTES(t0)
+	LOAD	x21, 20 * REGBYTES(t0)
+	LOAD	x22, 21 * REGBYTES(t0)
+	LOAD	x23, 22 * REGBYTES(t0)
+	LOAD	x24, 23 * REGBYTES(t0)
+	LOAD	x25, 24 * REGBYTES(t0)
+	LOAD	x26, 25 * REGBYTES(t0)
+	LOAD	x27, 26 * REGBYTES(t0)
+	LOAD	x28, 27 * REGBYTES(t0)
+	LOAD	x29, 28 * REGBYTES(t0)
+	LOAD	x30, 39 * REGBYTES(t0)
+	LOAD	x31, 30 * REGBYTES(t0)
+#endif
+	ret
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/GCC/RISC-V/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/GCC/RISC-V/portmacro.h
new file mode 100644
index 0000000..e8240ba
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/GCC/RISC-V/portmacro.h
@@ -0,0 +1,169 @@
+/*
+    FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution and was contributed
+    to the project by Technolution B.V. (www.technolution.nl,
+    freertos-riscv@technolution.eu) under the terms of the FreeRTOS
+    contributors license.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portBASE_TYPE	long
+
+#ifdef __riscv64
+	#define portSTACK_TYPE	uint64_t
+	#define portPOINTER_SIZE_TYPE	uint64_t
+#else
+	#define portSTACK_TYPE	uint32_t
+	#define portPOINTER_SIZE_TYPE	uint32_t
+#endif
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) (1000 / configTICK_RATE_HZ) )
+#ifdef __riscv64
+	#define portBYTE_ALIGNMENT	8
+#else
+	#define portBYTE_ALIGNMENT	4
+#endif
+#define portCRITICAL_NESTING_IN_TCB					1
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+extern void vPortYield( void );
+#define portYIELD()					vPortYield()
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+extern int vPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( int );
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()				__asm volatile 	( "csrc mstatus,8" )
+#define portENABLE_INTERRUPTS()					__asm volatile 	( "csrs mstatus,8" )
+
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+
+#define portSET_INTERRUPT_MASK_FROM_ISR()       vPortSetInterruptMask()
+
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue )       vPortClearInterruptMask( uxSavedStatusValue )
+
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYield()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#define portNOP() __asm volatile 	( " nop " )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/Makefile b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/Makefile
new file mode 100644
index 0000000..6a0d3b0
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/Makefile
@@ -0,0 +1,98 @@
+### Makefile to build the FreeRTOS library ###
+
+# Build target (options: sim, board)
+
+TARGET      = sim
+SMALL       =
+
+# Tools
+
+CC          = xt-xcc
+AS          = xt-xcc
+AR          = xt-ar
+XT_CORE     = $(patsubst %-params,%,$(notdir $(shell xt-xcc --show-config=core)))
+CONFIGDIR   = $(shell xt-xcc --show-config=config)
+
+# For platform-specific commands
+
+include $(CONFIGDIR)/misc/hostenv.mk
+
+# Source code and build locations
+
+SRCROOT     = $(subst /,$(S),$(CURDIR))
+TSTROOT     = $(abspath $(SRCROOT)$(S)..$(S)..$(S)..$(S)..$(S)..$(S)demos$(S)cadence$(S)sim$(SMALL))
+BLDROOT     = $(TSTROOT)$(S)build
+BLDDIR      = $(BLDROOT)$(S)$(XT_CORE)
+
+FR_SRCDIR   = $(abspath $(SRCROOT)$(S)..$(S)..$(S)..)
+FR_SRCDIR2  = $(FR_SRCDIR)$(S)portable$(S)MemMang
+XT_SRCDIR   = $(SRCROOT)
+
+vpath %.c $(FR_SRCDIR) $(FR_SRCDIR2) $(XT_SRCDIR)
+vpath %.S $(XT_SRCDIR)
+
+# File lists
+
+FR_C_FILES  = $(notdir $(wildcard $(FR_SRCDIR)/*.c)) $(notdir $(wildcard $(FR_SRCDIR2)/*.c))
+XT_C_FILES  = $(notdir $(wildcard $(XT_SRCDIR)/*.c))
+XT_S_FILES  = $(notdir $(wildcard $(XT_SRCDIR)/*.S))
+
+# List of all .o files that will go into the library
+
+LIB_C_O     = $(patsubst %.c,%.o,$(XT_C_FILES) $(FR_C_FILES))
+LIB_S_O     = $(patsubst %.S,%.o,$(XT_S_FILES))
+LIB_O_LIST  = $(addprefix $(BLDDIR)/,$(LIB_C_O) $(LIB_S_O))
+
+# Output files
+
+OSLIB       = $(BLDDIR)$(S)libfreertos.a
+
+# Build options
+
+ifeq ($(TARGET),sim)
+DFLAGS      = -DXT_SIMULATOR
+endif
+ifeq ($(TARGET),board)
+DFLAGS      = -DXT_BOARD
+endif
+
+IFLAGS      = \
+  -I$(FR_SRCDIR)$(S)..$(S)include -I$(FR_SRCDIR)$(S)..$(S)include$(S)private \
+  -I$(XT_SRCDIR) -I$(TSTROOT)$(S)common$(S)config_files -I$(BLDDIR)
+
+CFLAGS      = -O2 -g
+CCFLAGS     = $(CFLAGS) -Wall -mno-coproc -mlongcalls -ffunction-sections -mno-l32r-flix $(DFLAGS)
+ASFLAGS     = $(CCFLAGS)
+
+# Include dependency rules (generated using -MD)
+
+-include $(wildcard $(BLDDIR)/*.d)
+
+# Targets
+
+all : mkdir $(OSLIB)
+
+mkdir : $(BLDDIR)/.mkdir
+
+$(BLDDIR)/.mkdir :
+	@$(MKPATH) $(BLDDIR)
+	@echo "" > $@
+	-$(CP) $(CONFIGDIR)/xtensa-elf/include/sys/reent.h $(BLDDIR)/reent.h
+
+$(OSLIB) : $(LIB_O_LIST)
+	$(AR) -rs $@ $^
+
+$(BLDDIR)/%.o : %.c
+	$(CC) $(CCFLAGS) $(IFLAGS) -MD -MF $(subst .o,.d,$@) -c -o $@ $<
+
+$(BLDDIR)/%.o : %.S
+	$(CC) $(ASFLAGS) $(IFLAGS) -MD -MF $(subst .o,.d,$@) -c -o $@ $<
+
+clean :
+	$(RM_R) $(BLDDIR)
+
+clean_all :
+	$(RM_R) $(BLDROOT)
+
+.PHONY : all mkdir clean clean_all
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/port.c
new file mode 100644
index 0000000..c16dfed
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/port.c
@@ -0,0 +1,222 @@
+
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+
+#include "xtensa_rtos.h"
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+
+/* Defined in portasm.h */
+extern void _frxt_tick_timer_init(void);
+
+/* Defined in xtensa_context.S */
+extern void _xt_coproc_init(void);
+
+
+/*-----------------------------------------------------------*/
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+unsigned port_xSchedulerRunning = 0; // Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting
+unsigned port_interruptNesting = 0;  // Interrupt nesting level
+
+/*-----------------------------------------------------------*/
+
+// User exception dispatcher when exiting
+void _xt_user_exit(void);
+
+/* 
+ * Stack initialization
+ */
+#if portUSING_MPU_WRAPPERS
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
+#else
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+#endif
+{
+	StackType_t *sp, *tp;
+	XtExcFrame  *frame;
+	#if XCHAL_CP_NUM > 0
+	uint32_t *p;
+	#endif
+
+	/* Create interrupt stack frame aligned to 16 byte boundary */
+	sp = (StackType_t *) (((UBaseType_t)(pxTopOfStack + 1) - XT_CP_SIZE - XT_STK_FRMSZ) & ~0xf);
+
+	/* Clear the entire frame (do not use memset() because we don't depend on C library) */
+	for (tp = sp; tp <= pxTopOfStack; ++tp)
+		*tp = 0;
+
+	frame = (XtExcFrame *) sp;
+
+	/* Explicitly initialize certain saved registers */
+	frame->pc   = (UBaseType_t) pxCode;             /* task entrypoint                */
+	frame->a0   = 0;                                /* to terminate GDB backtrace     */
+	frame->a1   = (UBaseType_t) sp + XT_STK_FRMSZ;  /* physical top of stack frame    */
+	frame->exit = (UBaseType_t) _xt_user_exit;      /* user exception exit dispatcher */
+
+	/* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. */
+	/* Also set entry point argument parameter. */
+	#ifdef __XTENSA_CALL0_ABI__
+	frame->a2 = (UBaseType_t) pvParameters;
+	frame->ps = PS_UM | PS_EXCM;
+	#else
+	/* + for windowed ABI also set WOE and CALLINC (pretend task was 'call4'd). */
+	frame->a6 = (UBaseType_t) pvParameters;
+	frame->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1);
+	#endif
+
+	#ifdef XT_USE_SWPRI
+	/* Set the initial virtual priority mask value to all 1's. */
+	frame->vpri = 0xFFFFFFFF;
+	#endif
+
+	#if XCHAL_CP_NUM > 0
+	/* Init the coprocessor save area (see xtensa_context.h) */
+	/* No access to TCB here, so derive indirectly. Stack growth is top to bottom.
+         * //p = (uint32_t *) xMPUSettings->coproc_area;
+	 */
+	p = (uint32_t *)(((uint32_t) pxTopOfStack - XT_CP_SIZE) & ~0xf);
+	p[0] = 0;
+	p[1] = 0;
+	p[2] = (((uint32_t) p) + 12 + XCHAL_TOTAL_SA_ALIGN - 1) & -XCHAL_TOTAL_SA_ALIGN;
+	#endif
+
+	return sp;
+}
+
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the Xtensa port will get stopped.  If required simply
+	disable the tick interrupt here. */
+}
+
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	// Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored
+
+	#if XCHAL_CP_NUM > 0
+	/* Initialize co-processor management for tasks. Leave CPENABLE alone. */
+	_xt_coproc_init();
+	#endif
+
+	/* Init the tick divisor value */
+	_xt_tick_divisor_init();
+
+	/* Setup the hardware to generate the tick. */
+	_frxt_tick_timer_init();
+
+	#if XT_USE_THREAD_SAFE_CLIB
+	// Init C library
+	vPortClibInit();
+	#endif
+
+	port_xSchedulerRunning = 1;
+
+	// Cannot be directly called from C; never returns
+	__asm__ volatile ("call0    _frxt_dispatch\n");
+
+	/* Should not get here. */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortSysTickHandler( void )
+{
+	BaseType_t ret;
+	uint32_t interruptMask;
+
+	portbenchmarkIntLatency();
+
+	/* Interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY must be
+	 * disabled before calling xTaskIncrementTick as it access the
+	 * kernel lists. */
+	interruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		ret = xTaskIncrementTick();
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( interruptMask );
+
+	portYIELD_FROM_ISR( ret );
+
+	return ret;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Used to set coprocessor area in stack. Current hack is to reuse MPU pointer for coprocessor area.
+ */
+#if portUSING_MPU_WRAPPERS
+void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+{
+	#if XCHAL_CP_NUM > 0
+	xMPUSettings->coproc_area = (StackType_t*)((((uint32_t)(pxBottomOfStack + ulStackDepth - 1)) - XT_CP_SIZE ) & ~0xf);
+
+
+	/* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to
+         * clear the stack area after we return. This is done in pxPortInitialiseStack().
+	 */
+	#endif
+}
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portasm.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portasm.S
new file mode 100644
index 0000000..11017f3
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portasm.S
@@ -0,0 +1,596 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "xtensa_rtos.h"
+
+#define TOPOFSTACK_OFFS                 0x00    /* StackType_t *pxTopOfStack */
+#define CP_TOPOFSTACK_OFFS              0x04    /* xMPU_SETTINGS.coproc_area */
+
+.extern pxCurrentTCB
+
+
+/*
+*******************************************************************************
+* Interrupt stack. The size of the interrupt stack is determined by the config
+* parameter "configISR_STACK_SIZE" in FreeRTOSConfig.h
+*******************************************************************************
+*/
+    .data
+    .align      16
+    .global     port_IntStack
+port_IntStack:
+    .space      configISR_STACK_SIZE
+port_IntStackTop:
+    .word       0
+port_switch_flag:
+    .word       0
+
+    .text
+/*
+*******************************************************************************
+* _frxt_setup_switch
+* void _frxt_setup_switch(void);
+* 
+* Sets an internal flag indicating that a task switch is required on return
+* from interrupt handling.
+* 
+*******************************************************************************
+*/
+    .global     _frxt_setup_switch
+    .type       _frxt_setup_switch,@function
+    .align      4
+_frxt_setup_switch:
+
+    ENTRY(16)
+
+    movi    a2, port_switch_flag
+    movi    a3, 1
+    s32i    a3, a2, 0
+
+    RET(16)
+
+/*
+*******************************************************************************
+*                                            _frxt_int_enter
+*                                       void _frxt_int_enter(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_ENTER function for
+* freeRTOS. Saves the rest of the interrupt context (not already saved).
+* May only be called from assembly code by the 'call0' instruction, with
+* interrupts disabled.
+* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+*******************************************************************************
+*/
+    .globl  _frxt_int_enter
+    .type   _frxt_int_enter,@function
+    .align  4
+_frxt_int_enter:
+
+    /* Save a12-13 in the stack frame as required by _xt_context_save. */
+    s32i    a12, a1, XT_STK_A12
+    s32i    a13, a1, XT_STK_A13
+
+    /* Save return address in a safe place (free a0). */
+    mov     a12, a0
+
+    /* Save the rest of the interrupted context (preserves A12-13). */
+    call0   _xt_context_save
+
+    /*
+    Save interrupted task's SP in TCB only if not nesting.
+    Manage nesting directly rather than call the generic IntEnter()
+    (in windowed ABI we can't call a C function here anyway because PS.EXCM is still set).
+    */
+    movi    a2,  port_xSchedulerRunning
+    movi    a3,  port_interruptNesting
+    l32i    a2,  a2, 0                  /* a2 = port_xSchedulerRunning     */
+    beqz    a2,  1f                     /* scheduler not running, no tasks */
+    l32i    a2,  a3, 0                  /* a2 = port_interruptNesting      */
+    addi    a2,  a2, 1                  /* increment nesting count         */
+    s32i    a2,  a3, 0                  /* save nesting count              */
+    bnei    a2,  1, .Lnested            /* !=0 before incr, so nested      */
+
+    movi    a2,  pxCurrentTCB
+    l32i    a2,  a2, 0                  /* a2 = current TCB                */
+    beqz    a2,  1f
+    s32i    a1,  a2, TOPOFSTACK_OFFS    /* pxCurrentTCB->pxTopOfStack = SP */
+    movi    a1,  port_IntStackTop       /* a1 = top of intr stack          */
+
+.Lnested:
+1:
+    mov     a0,  a12                    /* restore return addr and return  */
+    ret
+
+/*
+*******************************************************************************
+*                                            _frxt_int_exit
+*                                       void _frxt_int_exit(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_EXIT function for
+* FreeRTOS. If required, calls vPortYieldFromInt() to perform task context
+* switching, restore the (possibly) new task's context, and return to the
+* exit dispatcher saved in the task's stack frame at XT_STK_EXIT.
+* May only be called from assembly code by the 'call0' instruction. Does not
+* return to caller.
+* See the description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+*******************************************************************************
+*/
+    .globl  _frxt_int_exit
+    .type   _frxt_int_exit,@function
+    .align  4
+_frxt_int_exit:
+
+    movi    a2,  port_xSchedulerRunning
+    movi    a3,  port_interruptNesting
+    rsil    a0,  XCHAL_EXCM_LEVEL       /* lock out interrupts             */
+    l32i    a2,  a2, 0                  /* a2 = port_xSchedulerRunning     */
+    beqz    a2,  .Lnoswitch             /* scheduler not running, no tasks */
+    l32i    a2,  a3, 0                  /* a2 = port_interruptNesting      */
+    addi    a2,  a2, -1                 /* decrement nesting count         */
+    s32i    a2,  a3, 0                  /* save nesting count              */
+    bnez    a2,  .Lnesting              /* !=0 after decr so still nested  */
+
+    movi    a2,  pxCurrentTCB
+    l32i    a2,  a2, 0                  /* a2 = current TCB                */
+    beqz    a2,  1f                     /* no task ? go to dispatcher      */
+    l32i    a1,  a2, TOPOFSTACK_OFFS    /* SP = pxCurrentTCB->pxTopOfStack */
+
+    movi    a2,  port_switch_flag       /* address of switch flag          */
+    l32i    a3,  a2, 0                  /* a3 = port_switch_flag           */
+    beqz    a3,  .Lnoswitch             /* flag = 0 means no switch reqd   */
+    movi    a3,  0
+    s32i    a3,  a2, 0                  /* zero out the flag for next time */
+
+1:
+    /*
+    Call0 ABI callee-saved regs a12-15 need to be saved before possible preemption.
+    However a12-13 were already saved by _frxt_int_enter().
+    */
+    #ifdef __XTENSA_CALL0_ABI__
+    s32i    a14, a1, XT_STK_A14
+    s32i    a15, a1, XT_STK_A15
+    #endif
+
+    #ifdef __XTENSA_CALL0_ABI__
+    call0   vPortYieldFromInt       /* call dispatch inside the function; never returns */
+    #else
+    call4   vPortYieldFromInt       /* this one returns */
+    call0   _frxt_dispatch          /* tail-call dispatcher */
+    /* Never returns here. */
+    #endif
+
+.Lnoswitch:
+    /*
+    If we came here then about to resume the interrupted task.
+    */
+
+.Lnesting:
+    /*
+    We come here only if there was no context switch, that is if this
+    is a nested interrupt, or the interrupted task was not preempted.
+    In either case there's no need to load the SP.
+    */
+
+    /* Restore full context from interrupt stack frame */
+    call0   _xt_context_restore
+
+    /*
+    Must return via the exit dispatcher corresponding to the entrypoint from which
+    this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
+    stack frame is deallocated in the exit dispatcher.
+    */
+    l32i    a0,  a1, XT_STK_EXIT
+    ret
+
+
+/*
+**********************************************************************************************************
+*                                           _frxt_timer_int
+*                                      void _frxt_timer_int(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_TIMER_INT function for FreeRTOS.
+* Called every timer interrupt.
+* Manages the tick timer and calls xPortSysTickHandler() every tick.
+* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+* Callable from C (obeys ABI conventions). Implemented in assmebly code for performance.
+*
+**********************************************************************************************************
+*/
+    .globl  _frxt_timer_int
+    .type   _frxt_timer_int,@function
+    .align  4
+_frxt_timer_int:
+
+    /*
+    Xtensa timers work by comparing a cycle counter with a preset value.  Once the match occurs
+    an interrupt is generated, and the handler has to set a new cycle count into the comparator.
+    To avoid clock drift due to interrupt latency, the new cycle count is computed from the old,
+    not the time the interrupt was serviced. However if a timer interrupt is ever serviced more
+    than one tick late, it is necessary to process multiple ticks until the new cycle count is
+    in the future, otherwise the next timer interrupt would not occur until after the cycle
+    counter had wrapped (2^32 cycles later).
+
+    do {
+        ticks++;
+        old_ccompare = read_ccompare_i();
+        write_ccompare_i( old_ccompare + divisor );
+        service one tick;
+        diff = read_ccount() - old_ccompare;
+    } while ( diff > divisor );
+    */
+
+    ENTRY(16)
+
+.L_xt_timer_int_catchup:
+
+    /* Update the timer comparator for the next tick. */
+    #ifdef XT_CLOCK_FREQ
+    movi    a2, XT_TICK_DIVISOR         /* a2 = comparator increment          */
+    #else
+    movi    a3, _xt_tick_divisor
+    l32i    a2, a3, 0                   /* a2 = comparator increment          */
+    #endif
+    rsr     a3, XT_CCOMPARE             /* a3 = old comparator value          */
+    add     a4, a3, a2                  /* a4 = new comparator value          */
+    wsr     a4, XT_CCOMPARE             /* update comp. and clear interrupt   */
+    esync
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /* Preserve a2 and a3 across C calls. */
+    s32i    a2, sp, 4
+    s32i    a3, sp, 8
+    #endif
+
+    /* Call the FreeRTOS tick handler (see port.c). */
+    #ifdef __XTENSA_CALL0_ABI__
+    call0   xPortSysTickHandler
+    #else
+    call4   xPortSysTickHandler
+    #endif
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /* Restore a2 and a3. */
+    l32i    a2, sp, 4
+    l32i    a3, sp, 8
+    #endif
+
+    /* Check if we need to process more ticks to catch up. */
+    esync                               /* ensure comparator update complete  */
+    rsr     a4, CCOUNT                  /* a4 = cycle count                   */
+    sub     a4, a4, a3                  /* diff = ccount - old comparator     */
+    blt     a2, a4, .L_xt_timer_int_catchup  /* repeat while diff > divisor */
+
+    RET(16)
+
+    /*
+**********************************************************************************************************
+*                                           _frxt_tick_timer_init
+*                                      void _frxt_tick_timer_init(void)
+*
+* Initialize timer and timer interrrupt handler (_xt_tick_divisor_init() has already been been called).
+* Callable from C (obeys ABI conventions on entry).
+*
+**********************************************************************************************************
+*/
+    .globl  _frxt_tick_timer_init
+    .type   _frxt_tick_timer_init,@function
+    .align  4
+_frxt_tick_timer_init:
+
+    ENTRY(16)
+
+    /* Set up the periodic tick timer (assume enough time to complete init). */
+    #ifdef XT_CLOCK_FREQ
+    movi    a3, XT_TICK_DIVISOR
+    #else
+    movi    a2, _xt_tick_divisor
+    l32i    a3, a2, 0
+    #endif
+    rsr     a2, CCOUNT              /* current cycle count */
+    add     a2, a2, a3              /* time of first timer interrupt */
+    wsr     a2, XT_CCOMPARE         /* set the comparator */
+
+    /*
+    Enable the timer interrupt at the device level. Don't write directly
+    to the INTENABLE register because it may be virtualized.
+    */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a2, XT_TIMER_INTEN
+    call0   xt_ints_on
+    #else
+    movi    a6, XT_TIMER_INTEN
+    call4   xt_ints_on
+    #endif
+
+    RET(16)
+
+/*
+**********************************************************************************************************
+*                                    DISPATCH THE HIGH READY TASK
+*                                     void _frxt_dispatch(void)
+*
+* Switch context to the highest priority ready task, restore its state and dispatch control to it.
+*
+* This is a common dispatcher that acts as a shared exit path for all the context switch functions
+* including vPortYield() and vPortYieldFromInt(), all of which tail-call this dispatcher
+* (for windowed ABI vPortYieldFromInt() calls it indirectly via _frxt_int_exit() ).
+*
+* The Xtensa port uses different stack frames for solicited and unsolicited task suspension (see
+* comments on stack frames in xtensa_context.h). This function restores the state accordingly.
+* If restoring a task that solicited entry, restores the minimal state and leaves CPENABLE clear.
+* If restoring a task that was preempted, restores all state including the task's CPENABLE.
+*
+* Entry:
+*   pxCurrentTCB  points to the TCB of the task to suspend,
+*   Because it is tail-called without a true function entrypoint, it needs no 'entry' instruction.
+*
+* Exit:
+*   If incoming task called vPortYield() (solicited), this function returns as if from vPortYield().
+*   If incoming task was preempted by an interrupt, this function jumps to exit dispatcher.
+*
+**********************************************************************************************************
+*/
+    .globl  _frxt_dispatch
+    .type   _frxt_dispatch,@function
+    .align  4
+_frxt_dispatch:
+
+    #ifdef __XTENSA_CALL0_ABI__
+    call0   vTaskSwitchContext  // Get next TCB to resume
+    movi    a2, pxCurrentTCB
+    #else
+    movi    a2, pxCurrentTCB
+    call4   vTaskSwitchContext  // Get next TCB to resume
+    #endif
+    l32i    a3,  a2, 0
+    l32i    sp,  a3, TOPOFSTACK_OFFS     /* SP = next_TCB->pxTopOfStack;  */
+    s32i    a3,  a2, 0
+
+    /* Determine the type of stack frame. */
+    l32i    a2,  sp, XT_STK_EXIT        /* exit dispatcher or solicited flag */
+    bnez    a2,  .L_frxt_dispatch_stk
+
+.L_frxt_dispatch_sol:
+
+    /* Solicited stack frame. Restore minimal context and return from vPortYield(). */
+    l32i    a3,  sp, XT_SOL_PS
+    #ifdef __XTENSA_CALL0_ABI__
+    l32i    a12, sp, XT_SOL_A12
+    l32i    a13, sp, XT_SOL_A13
+    l32i    a14, sp, XT_SOL_A14
+    l32i    a15, sp, XT_SOL_A15
+    #endif
+    l32i    a0,  sp, XT_SOL_PC
+    #if XCHAL_CP_NUM > 0
+    /* Ensure wsr.CPENABLE is complete (should be, it was cleared on entry). */
+    rsync
+    #endif
+    /* As soons as PS is restored, interrupts can happen. No need to sync PS. */
+    wsr     a3,  PS
+    #ifdef __XTENSA_CALL0_ABI__
+    addi    sp,  sp, XT_SOL_FRMSZ
+    ret
+    #else
+    retw
+    #endif
+
+.L_frxt_dispatch_stk:
+
+    #if XCHAL_CP_NUM > 0
+    /* Restore CPENABLE from task's co-processor save area. */
+    movi    a3, pxCurrentTCB            /* cp_state =                       */
+    l32i    a3, a3, 0
+    l32i    a2, a3, CP_TOPOFSTACK_OFFS     /* StackType_t                       *pxStack; */
+    l16ui    a3, a2, XT_CPENABLE         /* CPENABLE = cp_state->cpenable;   */
+    wsr     a3, CPENABLE
+    #endif
+
+    /* Interrupt stack frame. Restore full context and return to exit dispatcher. */
+    call0   _xt_context_restore
+
+    /* In Call0 ABI, restore callee-saved regs (A12, A13 already restored). */
+    #ifdef __XTENSA_CALL0_ABI__
+    l32i    a14, sp, XT_STK_A14
+    l32i    a15, sp, XT_STK_A15
+    #endif
+
+    #if XCHAL_CP_NUM > 0
+    /* Ensure wsr.CPENABLE has completed. */
+    rsync
+    #endif
+
+    /*
+    Must return via the exit dispatcher corresponding to the entrypoint from which
+    this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
+    stack frame is deallocated in the exit dispatcher.
+    */
+    l32i    a0, sp, XT_STK_EXIT
+    ret
+
+
+/*
+**********************************************************************************************************
+*                            PERFORM A SOLICTED CONTEXT SWITCH (from a task)
+*                                        void vPortYield(void)
+*
+* This function saves the minimal state needed for a solicited task suspension, clears CPENABLE,
+* then tail-calls the dispatcher _frxt_dispatch() to perform the actual context switch
+*
+* At Entry:
+*   pxCurrentTCB  points to the TCB of the task to suspend
+*   Callable from C (obeys ABI conventions on entry).
+*
+* Does not return to caller.
+*
+**********************************************************************************************************
+*/
+    .globl  vPortYield
+    .type   vPortYield,@function
+    .align  4
+vPortYield:
+
+    #ifdef __XTENSA_CALL0_ABI__
+    addi    sp,  sp, -XT_SOL_FRMSZ
+    #else
+    entry   sp,  XT_SOL_FRMSZ
+    #endif
+
+    rsr     a2,  PS
+    s32i    a0,  sp, XT_SOL_PC
+    s32i    a2,  sp, XT_SOL_PS
+    #ifdef __XTENSA_CALL0_ABI__
+    s32i    a12, sp, XT_SOL_A12         /* save callee-saved registers      */
+    s32i    a13, sp, XT_SOL_A13
+    s32i    a14, sp, XT_SOL_A14
+    s32i    a15, sp, XT_SOL_A15
+    #else
+    /* Spill register windows. Calling xthal_window_spill() causes extra    */
+    /* spills and reloads, so we will set things up to call the _nw version */
+    /* instead to save cycles.                                              */
+    movi    a6,  ~(PS_WOE_MASK|PS_INTLEVEL_MASK)  /* spills a4-a7 if needed */
+    and     a2,  a2, a6                           /* clear WOE, INTLEVEL    */
+    addi    a2,  a2, XCHAL_EXCM_LEVEL             /* set INTLEVEL           */
+    wsr     a2,  PS
+    rsync
+    call0   xthal_window_spill_nw
+    l32i    a2,  sp, XT_SOL_PS                    /* restore PS             */
+    wsr     a2,  PS
+    #endif
+
+    rsil    a2,  XCHAL_EXCM_LEVEL       /* disable low/med interrupts       */
+
+    #if XCHAL_CP_NUM > 0
+    /* Save coprocessor callee-saved state (if any). At this point CPENABLE */
+    /* should still reflect which CPs were in use (enabled).                */
+    call0   _xt_coproc_savecs
+    #endif
+
+    movi    a2,  pxCurrentTCB
+    movi    a3,  0
+    l32i    a2,  a2, 0                  /* a2 = pxCurrentTCB                */
+    s32i    a3,  sp, XT_SOL_EXIT        /* 0 to flag as solicited frame     */
+    s32i    sp,  a2, TOPOFSTACK_OFFS    /* pxCurrentTCB->pxTopOfStack = SP  */
+
+    #if XCHAL_CP_NUM > 0
+    /* Clear CPENABLE, also in task's co-processor state save area. */
+    l32i    a2,  a2, CP_TOPOFSTACK_OFFS /* a2 = pxCurrentTCB->cp_state      */
+    movi    a3,  0
+    wsr     a3,  CPENABLE
+    beqz    a2,  1f
+    s16i     a3,  a2, XT_CPENABLE        /* clear saved cpenable             */
+1:
+    #endif
+
+    /* Tail-call dispatcher. */
+    call0   _frxt_dispatch
+    /* Never reaches here. */
+
+
+/*
+**********************************************************************************************************
+*                         PERFORM AN UNSOLICITED CONTEXT SWITCH (from an interrupt)
+*                                        void vPortYieldFromInt(void)
+*
+* This calls the context switch hook (removed), saves and clears CPENABLE, then tail-calls the dispatcher
+* _frxt_dispatch() to perform the actual context switch.
+*
+* At Entry:
+*   Interrupted task context has been saved in an interrupt stack frame at pxCurrentTCB->pxTopOfStack.
+*   pxCurrentTCB  points to the TCB of the task to suspend,
+*   Callable from C (obeys ABI conventions on entry).
+*
+* At Exit:
+*   Windowed ABI defers the actual context switch until the stack is unwound to interrupt entry.
+*   Call0 ABI tail-calls the dispatcher directly (no need to unwind) so does not return to caller.
+*
+**********************************************************************************************************
+*/
+    .globl  vPortYieldFromInt
+    .type   vPortYieldFromInt,@function
+    .align  4
+vPortYieldFromInt:
+
+    ENTRY(16)
+
+    #if XCHAL_CP_NUM > 0
+    /* Save CPENABLE in task's co-processor save area, and clear CPENABLE.  */
+    movi    a3, pxCurrentTCB            /* cp_state =                       */
+    l32i    a3, a3, 0
+    l32i    a2, a3, CP_TOPOFSTACK_OFFS
+
+    rsr     a3, CPENABLE
+    s16i     a3, a2, XT_CPENABLE         /* cp_state->cpenable = CPENABLE;   */
+    movi    a3, 0
+    wsr     a3, CPENABLE                /* disable all co-processors        */
+    #endif
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /* Tail-call dispatcher. */
+    call0   _frxt_dispatch
+    /* Never reaches here. */
+    #else
+    RET(16)
+    #endif
+
+/*
+**********************************************************************************************************
+*                                        _frxt_task_coproc_state
+*                                   void _frxt_task_coproc_state(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_CP_STATE function for FreeRTOS.
+*
+* May only be called when a task is running, not within an interrupt handler (returns 0 in that case).
+* May only be called from assembly code by the 'call0' instruction. Does NOT obey ABI conventions.
+* Returns in A15 a pointer to the base of the co-processor state save area for the current task.
+* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+**********************************************************************************************************
+*/
+#if XCHAL_CP_NUM > 0
+
+    .globl  _frxt_task_coproc_state
+    .type   _frxt_task_coproc_state,@function
+    .align  4
+_frxt_task_coproc_state:
+
+    movi    a15, port_xSchedulerRunning /* if (port_xSchedulerRunning              */
+    l32i    a15, a15, 0
+    beqz    a15, 1f
+    movi    a15, port_interruptNesting  /* && port_interruptNesting == 0           */
+    l32i    a15, a15, 0
+    bnez    a15, 1f
+    movi    a15, pxCurrentTCB
+    l32i    a15, a15, 0                 /* && pxCurrentTCB != 0) {                 */
+    beqz    a15, 2f
+    l32i    a15, a15, CP_TOPOFSTACK_OFFS
+    ret
+
+1:  movi    a15, 0
+2:  ret
+
+#endif /* XCHAL_CP_NUM > 0 */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portbenchmark.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portbenchmark.h
new file mode 100644
index 0000000..3df6103
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portbenchmark.h
@@ -0,0 +1,46 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * This utility helps benchmarking interrupt latency and context switches.
+ * In order to enable it, set configBENCHMARK to 1 in FreeRTOSConfig.h.
+ * You will also need to download the FreeRTOS_trace patch that contains
+ * portbenchmark.c and the complete version of portbenchmark.h
+ */
+
+#ifndef PORTBENCHMARK_H
+#define PORTBENCHMARK_H
+
+#if configBENCHMARK
+    #error "You need to download the FreeRTOS_trace patch that overwrites this file"
+#endif
+
+#define portbenchmarkINTERRUPT_DISABLE()
+#define portbenchmarkINTERRUPT_RESTORE(newstate)
+#define portbenchmarkIntLatency()
+#define portbenchmarkIntWait()
+#define portbenchmarkReset()
+#define portbenchmarkPrint()
+
+#endif /* PORTBENCHMARK */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portclib.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portclib.c
new file mode 100644
index 0000000..7268923
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portclib.c
@@ -0,0 +1,225 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "FreeRTOS.h"
+
+#if XT_USE_THREAD_SAFE_CLIB
+
+#if XSHAL_CLIB == XTHAL_CLIB_XCLIB
+
+#include 
+#include 
+
+#include "semphr.h"
+
+typedef SemaphoreHandle_t       _Rmtx;
+
+//-----------------------------------------------------------------------------
+//  Override this and set to nonzero to enable locking.
+//-----------------------------------------------------------------------------
+int32_t _xclib_use_mt = 1;
+
+
+//-----------------------------------------------------------------------------
+//  Init lock.
+//-----------------------------------------------------------------------------
+void
+_Mtxinit(_Rmtx * mtx)
+{
+    *mtx = xSemaphoreCreateRecursiveMutex();
+}
+
+//-----------------------------------------------------------------------------
+//  Destroy lock.
+//-----------------------------------------------------------------------------
+void
+_Mtxdst(_Rmtx * mtx)
+{
+    if ((mtx != NULL) && (*mtx != NULL)) {
+        vSemaphoreDelete(*mtx);
+    }
+}
+
+//-----------------------------------------------------------------------------
+//  Lock.
+//-----------------------------------------------------------------------------
+void
+_Mtxlock(_Rmtx * mtx)
+{
+    if ((mtx != NULL) && (*mtx != NULL)) {
+        xSemaphoreTakeRecursive(*mtx, portMAX_DELAY);
+    }
+}
+
+//-----------------------------------------------------------------------------
+//  Unlock.
+//-----------------------------------------------------------------------------
+void
+_Mtxunlock(_Rmtx * mtx)
+{
+    if ((mtx != NULL) && (*mtx != NULL)) {
+        xSemaphoreGiveRecursive(*mtx);
+    }
+}
+
+//-----------------------------------------------------------------------------
+//  Called by malloc() to allocate blocks of memory from the heap.
+//-----------------------------------------------------------------------------
+void *
+_sbrk_r (struct _reent * reent, int32_t incr)
+{
+    extern char _end;
+    extern char _heap_sentry;
+    static char * _heap_sentry_ptr = &_heap_sentry;
+    static char * heap_ptr;
+    char * base;
+
+    if (!heap_ptr)
+        heap_ptr = (char *) &_end;
+
+    base = heap_ptr;
+    if (heap_ptr + incr >= _heap_sentry_ptr) {
+        reent->_errno = ENOMEM;
+        return (char *) -1;
+    }
+
+    heap_ptr += incr;
+    return base;
+}
+
+//-----------------------------------------------------------------------------
+//  Global initialization for C library.
+//-----------------------------------------------------------------------------
+void
+vPortClibInit(void)
+{
+}
+
+//-----------------------------------------------------------------------------
+//  Per-thread cleanup stub provided for linking, does nothing.
+//-----------------------------------------------------------------------------
+void
+_reclaim_reent(void * ptr)
+{
+}
+
+#endif /* XSHAL_CLIB == XTHAL_CLIB_XCLIB */
+
+#if XSHAL_CLIB == XTHAL_CLIB_NEWLIB
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "semphr.h"
+
+static SemaphoreHandle_t xClibMutex;
+static uint32_t  ulClibInitDone = 0;
+
+//-----------------------------------------------------------------------------
+//  Get C library lock.
+//-----------------------------------------------------------------------------
+void
+__malloc_lock(struct _reent * ptr)
+{
+    if (!ulClibInitDone)
+        return;
+
+    xSemaphoreTakeRecursive(xClibMutex, portMAX_DELAY);
+}
+
+//-----------------------------------------------------------------------------
+//  Release C library lock.
+//-----------------------------------------------------------------------------
+void
+__malloc_unlock(struct _reent * ptr)
+{
+    if (!ulClibInitDone)
+        return;
+
+    xSemaphoreGiveRecursive(xClibMutex);
+}
+
+//-----------------------------------------------------------------------------
+//  Lock for environment. Since we have only one global lock we can just call
+//  the malloc() lock function.
+//-----------------------------------------------------------------------------
+void
+__env_lock(struct _reent * ptr)
+{
+    __malloc_lock(ptr);
+}
+
+
+//-----------------------------------------------------------------------------
+//  Unlock environment.
+//-----------------------------------------------------------------------------
+void
+__env_unlock(struct _reent * ptr)
+{
+    __malloc_unlock(ptr);
+}
+
+//-----------------------------------------------------------------------------
+//  Called by malloc() to allocate blocks of memory from the heap.
+//-----------------------------------------------------------------------------
+void *
+_sbrk_r (struct _reent * reent, int32_t incr)
+{
+    extern char _end;
+    extern char _heap_sentry;
+    static char * _heap_sentry_ptr = &_heap_sentry;
+    static char * heap_ptr;
+    char * base;
+
+    if (!heap_ptr)
+        heap_ptr = (char *) &_end;
+
+    base = heap_ptr;
+    if (heap_ptr + incr >= _heap_sentry_ptr) {
+        reent->_errno = ENOMEM;
+        return (char *) -1;
+    }
+
+    heap_ptr += incr;
+    return base;
+}
+
+//-----------------------------------------------------------------------------
+//  Global initialization for C library.
+//-----------------------------------------------------------------------------
+void
+vPortClibInit(void)
+{
+    configASSERT(!ulClibInitDone);
+
+    xClibMutex = xSemaphoreCreateRecursiveMutex();
+    ulClibInitDone  = 1;
+}
+
+#endif /* XSHAL_CLIB == XTHAL_CLIB_NEWLIB */
+
+#endif /* XT_USE_THREAD_SAFE_CLIB */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portmacro.h
new file mode 100644
index 0000000..edf48aa
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portmacro.h
@@ -0,0 +1,236 @@
+
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include 
+
+#include 
+#include 
+#include 
+#include 	/* required for XSHAL_CLIB */
+#include 
+
+//#include "xtensa_context.h"
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+
+#define portCHAR		int8_t
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		int32_t
+#define portSHORT		int16_t
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	int
+
+typedef portSTACK_TYPE			StackType_t;
+typedef portBASE_TYPE			BaseType_t;
+typedef unsigned portBASE_TYPE	UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+// portbenchmark
+#include "portbenchmark.h"
+
+/* Critical section management. NW-TODO: replace XTOS_SET_INTLEVEL with more efficient version, if any? */
+// These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level.
+#define portDISABLE_INTERRUPTS()      do { XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); } while (0)
+#define portENABLE_INTERRUPTS()       do { portbenchmarkINTERRUPT_RESTORE(0); XTOS_SET_INTLEVEL(0); } while (0)
+
+// These can be nested
+#define portCRITICAL_NESTING_IN_TCB 1  // For now, let FreeRTOS' (tasks.c) manage critical nesting
+void vTaskEnterCritical(void);
+void vTaskExitCritical(void);
+#define portENTER_CRITICAL()        vTaskEnterCritical()
+#define portEXIT_CRITICAL()         vTaskExitCritical()
+
+// Cleaner and preferred solution allows nested interrupts disabling and restoring via local registers or stack.
+// They can be called from interrupts too.
+static inline unsigned portENTER_CRITICAL_NESTED() { unsigned state = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); return state; }
+#define portEXIT_CRITICAL_NESTED(state)   do { portbenchmarkINTERRUPT_RESTORE(state); XTOS_RESTORE_JUST_INTLEVEL(state); } while (0)
+
+// These FreeRTOS versions are similar to the nested versions above
+#define portSET_INTERRUPT_MASK_FROM_ISR()            portENTER_CRITICAL_NESTED()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(state)     portEXIT_CRITICAL_NESTED(state)
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			4
+#define portNOP()					XT_NOP()
+/*-----------------------------------------------------------*/
+
+/* Fine resolution time */
+#define portGET_RUN_TIME_COUNTER_VALUE()  xthal_get_ccount()
+
+/* Kernel utilities. */
+void vPortYield( void );
+void _frxt_setup_switch( void );
+#define portYIELD()       vPortYield()
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken )	\
+	if ( ( xHigherPriorityTaskWoken ) != 0 ) {	\
+		_frxt_setup_switch();			\
+	}
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+// When coprocessors are defined, we to maintain a pointer to coprocessors area.
+// We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold:
+// MPU wrappers, coprocessor area pointer, trace code structure, and more if needed.
+// The field is normally used for memory protection. FreeRTOS should create another general purpose field.
+typedef struct {
+	#if XCHAL_CP_NUM > 0
+	volatile StackType_t* coproc_area; // Pointer to coprocessor save area; MUST BE FIRST
+	#endif
+
+	#if portUSING_MPU_WRAPPERS
+	// Define here mpu_settings, which is port dependent
+	int mpu_setting; // Just a dummy example here; MPU not ported to Xtensa yet
+	#endif
+
+	#if configUSE_TRACE_FACILITY_2
+	struct {
+		// Cf. porttraceStamp()
+		int taskstamp;        /* Stamp from inside task to see where we are */
+		int taskstampcount;   /* A counter usually incremented when we restart the task's loop */
+	} porttrace;
+	#endif
+} xMPU_SETTINGS;
+
+// Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS)
+#if (XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2) && !portUSING_MPU_WRAPPERS   // If MPU wrappers not used, we still need to allocate coproc area
+	#undef portUSING_MPU_WRAPPERS
+	#define portUSING_MPU_WRAPPERS 1   // Enable it to allocate coproc area
+	#define MPU_WRAPPERS_H             // Override mpu_wrapper.h to disable unwanted code
+	#define PRIVILEGED_FUNCTION
+	#define PRIVILEGED_DATA
+#endif
+
+// porttrace
+#if configUSE_TRACE_FACILITY_2
+#include "porttrace.h"
+#endif
+
+// configASSERT_2 if requested
+#if configASSERT_2
+#include 
+void exit(int);
+#define configASSERT( x )   if (!(x)) { porttracePrint(-1); printf("\nAssertion failed in %s:%d\n", __FILE__, __LINE__); exit(-1); }
+#endif
+
+
+/* C library support -- only XCLIB and NEWLIB are supported. */
+
+/* To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must be
+   defined to be > 0 somewhere above or on the command line. */
+
+#if (XT_USE_THREAD_SAFE_CLIB > 0u) && (XSHAL_CLIB == XTHAL_CLIB_XCLIB)
+extern void vPortClibInit(void);
+
+// No cleanup necessary at this time.
+#define portCLEAN_UP_TCB(pxTCB)
+#endif // XCLIB support
+
+#if (XT_USE_THREAD_SAFE_CLIB > 0u) && (XSHAL_CLIB == XTHAL_CLIB_NEWLIB)
+extern void vPortClibInit(void);
+
+// This C library cleanup is not currently done by FreeRTOS when deleting a task
+#include 
+#define portCLEAN_UP_TCB(pxTCB)   vPortCleanUpTcbClib(&((pxTCB)->xNewLib_reent))
+static inline void vPortCleanUpTcbClib(struct _reent *ptr)
+{
+    FILE * fp = &(ptr->__sf[0]);
+    int i;
+    for (i = 0; i < 3; ++i, ++fp) {
+        fp->_close = NULL;
+    }
+}
+#endif // NEWLIB support
+
+#endif // __ASSEMBLER__
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/porttrace.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/porttrace.h
new file mode 100644
index 0000000..498444b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/porttrace.h
@@ -0,0 +1,44 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * This utility helps tracing the entering and exiting from tasks.
+ * It maintains a circular buffer of tasks in the order they execute,
+ * and their execution time. To enable it, set configUSE_TRACE_FACILITY_2
+ * to 1 in FreeRTOSConfig.h. You will also need to download the 
+ * FreeRTOS_trace patch that contains porttrace.c and the complete version
+ * of porttrace.h.
+ */
+
+#ifndef PORTTRACE_H
+#define PORTTRACE_H
+
+#if configUSE_TRACE_FACILITY_2
+    #error "You need to download the FreeRTOS_trace patch that overwrites this file"
+#endif
+
+#define porttracePrint(nelements)
+#define porttraceStamp(stamp, count_incr)
+
+#endif /* PORTTRACE_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/readme_xtensa.txt b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/readme_xtensa.txt
new file mode 100644
index 0000000..247d731
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/readme_xtensa.txt
@@ -0,0 +1,764 @@
+    FreeRTOS Port for Xtensa Configurable and Diamond Processors
+    ============================================================
+
+                FreeRTOS Kernel Version 10.0.0
+
+
+Introduction
+------------
+
+This document describes the Xtensa port for FreeRTOS multitasking RTOS.
+For an introduction to FreeRTOS itself, please refer to FreeRTOS
+documentation.
+
+This port currently works with FreeRTOS kernel version 10.0.0.
+
+
+Xtensa Configuration Requirements and Restrictions
+--------------------------------------------------
+
+The Xtensa configurable architecture supports a vast space of processor
+features. This port supports all of them, including custom processor
+extensions defined in the TIE language, with certain minimum
+requirements. You must use Xtensa Tools to compile and link FreeRTOS and
+your application for your Xtensa configuration. The port uses the Xtensa
+Hardware Abstraction Layer (HAL) to adapt to your Xtensa configuration.
+NOTE: It may be possible to build and run this with the open-source 
+xtensa-linux tools provided you have the correct overlay for your Xtensa
+configuration. However, this has not been tested and is currently not
+supported by Cadence.
+
+This port includes optional reentrancy support for the 'newlib' and
+'xclib' C runtime libraries distributed with Xtensa Tools, providing
+thread-safety on a per task basis (for use in tasks only, not interrupt
+handlers).
+
+NOTE: At this time only 'newlib' and 'xclib' C libraries are supported
+for thread safety. The 'uclibc' library is not reentrant and does not
+provide thread safety at this time. However, if you are not concerned
+with reentrancy then you can use any of these libraries.
+
+This port also includes a simple example application that may run on
+a supported board or the Xtensa instruction set simulator (ISS). There
+are also a couple of test programs used in maintaining the port, which
+serve as additional examples.
+
+FreeRTOS for Xtensa configurable processors requires the following minimum 
+processor configuration options:
+- Timer interrupt option with at least one interruptible timer.
+- Interrupt option (implied by the timer interrupt option).
+- Exception Architecture 2 (XEA2). Please note that XEA1 is NOT supported.
+  All 'Diamond', 'Xtensa 6', 'Xtensa LX' and 'Xtensa LX2' processors and
+  most 'Xtensa T1050' processors are configured with XEA2.
+All Diamond processor cores meet these requirements and are supported.
+
+Minimal support for certain evaluation boards is provided via a board
+independent XTBSP API implemented by a board specific library distributed
+with the Xtensa Tools. This provides the board clock frequency and basic
+polled drivers for the display and console device. Note that XTBSP
+is not a tradtional RTOS "board support package" with RTOS specific
+interrupt-driven drivers - it is not specific to any RTOS. Note that
+FreeRTOS can run on any Xtensa or Diamond board without this board support
+(a "raw" platform), but you will have to provide the clock frequency
+and drivers for any on-board devices you want to use.
+
+
+Installation
+------------
+
+The Xtensa port of FreeRTOS is available at this location:
+
+    https://github.com/foss-xtensa/amazon-freertos
+
+This download includes the core FreeRTOS source and include files needed
+to build the port. You can also download the official release of FreeRTOS
+version 1.0.0 or later from this location:
+
+    https://github.com/aws/amazon-freertos
+
+The Xtensa port files are currently not included in the official package.
+
+All source is provided along with a Makefile that works for any host
+platform supported by Xtensa Tools (Windows, Linux). These instructions
+are written for Windows users, but can easily be understood and adapted
+to other host platforms.
+
+First install the FreeRTOS common package in a directory of your choosing.
+The structure of that package will look like this:
+
+
+|-- demos
+|   `-- cadence
+|       `-- sim
+|           |-- common
+|           |   |-- application_code
+|           |   |   `-- cadence_code
+|           |   `-- config_files
+|           `-- xplorer
+`-- lib
+    |-- FreeRTOS
+    |   `-- portable
+    |       |-- Common
+    |       |-- MemMang
+    |       `-- XCC
+    |           `-- Xtensa
+    `-- include
+        `-- private
+
+The Xtensa Tools are available from Cadence as part of a processor
+license. Be sure you have installed the Xtensa Tools and your processor
+configuration.
+
+
+Building FreeRTOS for Xtensa
+----------------------------
+
+To build the FreeRTOS library and the example programs, go into the
+directory 'demos/cadence/sim' and use the makefile in that directory.
+"make all" will build all the examples. There is another makefile in
+the 'lib/FreeRTOS/portable/XCC/Xtensa' directory that builds just the
+FreeRTOS library.
+
+By default, you will build for the Xtensa instruction set simulator. If
+you have a supported emulation board, you can build to run on that. You
+can also build to run on a raw Xtensa core with no board support, a
+good starting point for supporting your own target platform. Cadence
+recommends doing functional development on the simulator because it
+is easier to debug with, then move to a board if/when you need to test
+hardware drivers or real-time performance.
+
+The provided makefile simplifies building FreeRTOS and the example
+for your Xtensa configuration and platform (ISS, board, etc.). There
+are detailed instructions in the comments at the top of the makefile.
+
+The makefiles work on Windows and Linux and support incremental builds.
+The build for each Xtensa configuration and target platform is placed in
+a subdirectory so several core and platform builds can co-exist even with
+incremental rebuilds. You may specify the root of the build area (if tou
+want it to be elsewhere than under the source tree) by defining BLDROOT
+either in the make command or your shell environment.
+
+
+Building the FreeRTOS Library
+-----------------------------
+
+First, be sure you have installed Xtensa Tools and your processor
+configuration, and be sure that Xtensa Tools are in your search path.
+You can use xt-make, which comes with the Xtensa Tools, to run the
+makefiles.
+
+Change directories to the Xtensa port directory:
+
+> cd lib/FreeRTOS/portable/XCC/Xtensa
+
+Now build the FreeRTOS RTOS as a library (libfreertos.a) as follows:
+
+> xt-make
+
+which by default builds for the simulator (TARGET=sim), or:
+
+> xt-make TARGET=board
+
+which builds for a supported board. Note that the board type does not
+need to be specified when building the FreeRTOS library.
+
+If you are building for an Xtensa processor configuration that is not the
+default you selected when you installed Xtensa Tools, you need to define the 
+environment variable XTENSA_CORE. If your configuration is not in the 
+default registry you selected when you installed Xtensa Tools, you also
+need to define the environment variable XTENSA_SYSTEM. See tools manuals.
+You can avoid defining these in your environment if you pass the variables 
+you need to redefine into xt-make as follows:
+
+> xt-make XTENSA_CORE= XTENSA_SYSTEM= ...
+
+There are more details about build options in the comment in the Makefile.
+
+After the library has been built, you must link your application with this
+library in order to use FreeRTOS.
+
+
+Building the FreeRTOS Examples
+------------------------------
+
+The provided examples are designed to run on the Xtensa instruction set
+simulator (ISS) or a supported evaluation board programmed with your
+Xtensa processor configuration.
+
+To build the examples for the default platform (simulator):
+
+> cd demos/cadence/sim
+
+> xt-make all
+
+which is the same as
+
+> xt-make all TARGET=sim
+
+The boards currently supported are the Xilinx ML605 and KC705 FPGA
+development boards. To target these boards, type
+
+> xt-make all TARGET=ml605
+
+or
+
+> xt-make all TARGET=kc705
+
+To build in a location other than the default, specify the new location
+using the BLDROOT variable. Note that this makefile will invoke the 
+FreeRTOS library build makefile automatically, passing on the relevant
+parameters based on what you specified.
+
+You can override the default compilation options by specifying the new
+options via CFLAGS. For example:
+
+> xt-make all TARGET=sim CFLAGS="-O2 -Os -g"
+
+This compiles the examples and links them with the FreeRTOS library
+libfreertos.a and the appropriate linker-support package (LSP) for your
+target platform (you can override the LSP by adding LSP= to the
+xt-make command line). The resulting ELF files can be downloaded and
+executed on the target. The example binaries appear in the platform
+specific subdirectory described earlier.
+
+To build your application with thread-safe C library support, you
+need to make certain modifications to the application to plug in and
+invoke the reentrancy support. This allows each task to use the library
+without interference with other tasks (it is not safe for interrupt
+handlers to call the C library).
+
+First, you must define
+
+    XT_USE_THREAD_SAFE_CLIB
+
+to a nonzero value either in xtensa_config.h or on the compiler's command
+line. Note that the default xtensa_config.h provided with this port does
+define this to 1 if either newlib or xclib is detected.
+
+Then, you must also make sure to allocate extra space on the stack for
+each task that will use the C library reentrant functions. This extra
+space is to be allocated over and above the actual stack space required
+by the task itself. The define
+
+    XT_STACK_EXTRA_CLIB
+
+specifies the amount of extra space to be added on to the stack to allow
+saving the context for the C library as well as the coprocessors if any.
+E.g. if your task requires 2000 bytes of stack space, you must allocate
+(2000 + XT_STACK_EXTRA_CLIB) bytes for the stack.
+
+
+IMPORTANT NOTE
+--------------
+
+The header file FreeRTOS.h, which is a part of the core FreeRTOS sources,
+includes  if thread safety for the C libraries is enabled. For
+xclib, this file exists in  and so is reported as missing.
+To work around this, the makefiles supplied with this port will copy the
+reent.h header into the build directory during the build process. If you
+use a different build process, then you must make sure to copy this file
+to a location that is included in the list of include paths. This can be
+the build directory or the directory that contains the Xtensa port source
+files.
+
+
+Running or Debugging an Application
+-----------------------------------
+
+To execute the example application on the simulator:
+
+> xt-run [--turbo] example.exe
+
+The option --turbo provides much faster, but non-cycle-accurate simulation
+(the --turbo option is only available with Xtensa Tools version 7 or later).
+
+
+To execute on the simulator using the Xplorer GUI based debugger:
+
+> xplorer --debug example.exe
+
+
+To execute on a supported evaluation board, download example.exe per
+instructions in the tools manuals. Be sure the board has been programmed
+with the correct configuration and is set up to boot from RAM and debug
+a downloaded program!  Optionally you may connect a terminal or terminal
+emulator to the serial port on the board with settings as described in
+the board user manual, and see the output of printf on the terminal.
+
+To obtain I/O on a "raw" platform such as an unsupported board, you need
+to provide low level I/O drivers (eg. inbyte() and outbyte() for character
+I/O if you want to use printf etc.).  You can run "raw" executables on
+any Xtensa platform, including simulator and any board, but you will not
+see any behavior specific to the platform (eg. display, printed output,
+stopping simulation at end of program). You can, while debugging, use a
+debugger mechanism called GDBIO to obtain basic I/O. To use GDBIO, link
+with the gdbio LSP. Refer to Xtensa tools documentation for details.
+
+
+Task Stack Sizes
+----------------
+
+The application must ensure that every task has enough space for its
+stack. Each task needs enough space for its own use, its own interrupt
+stack frame (defined in xtensa_context.h) and space to save coprocessor
+state, if any. Several factors influence the size of the stack required,
+including the compiler optimization level and the use of the C library.
+Calls to standard output functions such as printf() can use up a lot of
+stack space. The tool xt-stack-usage is helpful in determining safe stack
+sizes for your application.
+
+Some macros are provided in xtensa_config.h to help determine the stack
+size for tasks that do and do not use the C library. Use these as the
+basis for each task's stack size. They are minimum requirements taking
+into account your configuration and use of the C library. In particular,
+the define
+
+    XT_STACK_MIN_SIZE
+
+defines the minimum stack size for any task. Be very careful if you try
+to use a stack size smaller than this minimum. Stack overruns can cause
+all kinds of hard-to-debug errors. It is recommended that you enable the
+FreeRTOS stack checking features during development.
+
+WARNING: The newlib printf() function uses a lot of stack space. Be very
+careful in using it. Optionally you can use the 'libxtutil' library for
+output - it implements a subset of printf() that has smaller code size
+and uses far less stack space. More information about this library is in
+the Xtensa Tools documentation.
+
+
+Interrupt Stack
+---------------
+
+Beginning with port version 1.2, the port uses a separate interrupt stack
+for handling interrupts. Thus, it is no longer necessary for each task to
+reserve space on its stack to handle interrupts. The size of the interrupt
+stack is controlled by the parameter "configISR_STACK_SIZE" defined in
+FreeRTOSConfig.h. Define this carefully to match your system requirements.
+
+
+Assembler / Compiler Switches
+-----------------------------
+
+The following are compiler switches are used by the provided
+Makefile in building the FreeRTOS library and example application.
+These can be modified by editing the Makefile or by overriding the
+CFLAGS variable in the make command line, for example:
+
+> xt-make CFLAGS="-O2 -DXT_USE_THREAD_SAFE_CLIB"
+
+    -g                      Specifies debug information.
+    -c                      Specifies object code generation.
+    -On                     Sets compiler optimization level n (default -O0).
+    -mlongcalls             Allows assembler and linker to convert call 
+                            instructions to longer indirect call sequences 
+                            when target is out of range.
+    -x assembler-with-cpp   Passes .s and .S files through C preprocessor.
+    -Dmacro                 Define a preprocessor macro with no value.
+    -Dmacro=value           Define a preprocessor macro with a value.
+
+See the compiler / linker documentation for a full list of switches and
+their use.
+
+Many definitions can be provided at compile-time via the -D option 
+without editing the source code. Here are some of the more useful ones:
+
+    XT_USE_THREAD_SAFE_CLIB Enable support for the reentrancy to provide
+                            thread-safety for the newlib and xclib libraries
+                            supplied with Xtensa Tools. Default ON.
+
+    Note, the follwing defines are unique to the Xtensa port so have names
+    beginning with "XT_".
+
+    XT_SIMULATOR            Set this if building to run on the simulator.
+                            Takes advantage of certain simulator control
+                            and reporting facilities, and adjusts timing 
+                            of periodic tick to provide a more acceptable
+                            performance in simulation (see XT_CLOCK_FREQ).
+                            Set by default unless PLATFORM is overridden.
+
+    XT_BOARD                Set this if building for a supported board.
+                            Be sure to specify the correct LSP for the
+                            board. See the example makefile for usage.
+
+    XT_CLOCK_FREQ=freq      Specifies the target processor's clock 
+                            frequency in Hz. Used primarily to set the 
+                            timer that generates the periodic interrupt.
+                            Defaults are provided and may be edited in
+                            xtensa_timer.h (see comments there also).
+                            Default for simulator provides more acceptable
+                            performance, but cannot provide real-time
+                            performance due to variation in simulation
+                            speed per host platform and insufficient 
+                            cycles between interrupts to process them.
+                            Supported board platforms by default leave 
+                            this undefined and compute the clock frequency 
+                            at initialization unless this is explicitly 
+                            defined.
+
+    XT_TICK_PER_SEC=n       Specifies the frequency of the periodic tick.
+
+    XT_TIMER_INDEX=n        Specifies which timer to use for periodic tick.
+                            Set this if your Xtensa processor configuration 
+                            provides more than one suitable timer and you 
+                            want to override the default. See xtensa_timer.h .
+
+    XT_INTEXC_HOOKS         Enables hooks in interrupt vector handlers
+                            to support dynamic installation of exception
+                            and interrupt handlers. Disabled by default.
+
+    XT_USE_OVLY             Enable code overlay support. It uses a mutex,
+                            hence configUSE_MUTEX must be enabled. This
+                            option is currently unsupported.
+
+    XT_USE_SWPRI            Enable software prioritization of interrupts.
+                            Enabling this will prioritize interrupts with
+                            higher bit numbers over those with lower bit
+                            numbers at the same level. This works only for
+                            low and medium priority interrupts that can be
+                            dispatched to C handlers.
+
+
+Register Usage and Stack Frames
+-------------------------------
+
+The Xtensa architecture specifies two ABIs that determine how the general
+purpose registers a0-a15 are used: the standard windowed ABI use with
+the Xtensa windowed register file architecture, and the optional and
+more conventional Call0 ABI (required for Xtensa configurations without
+a windowed register file).
+
+Xtensa processors may have other special registers (including co-processor
+registers and other TIE "states") that are independent of this choice
+of ABI. See Xtensa documentation for more details.
+
+In the windowed ABI the registers of the current window are used as follows:
+    a0      = return address
+    a1      = stack pointer (alias sp)
+    a2      = first argument and result of call (in simple cases)
+    a3-7    = second through sixth arguments of call (in simple cases).
+              Note that complex or large arguments are passed on the
+              stack. Details are in the Xtensa Tools manuals.
+    a8-a15  = available for use as temporaries.
+There are no callee-save registers. The windowed hardware automatically
+saves registers a0-a3 on a call4, a0-a8 on a call8, a0-a12 on a call12,
+by rotating the register window. Hardware triggers window overflow and
+underflow exceptions as necessary when registers outside the current 
+window need to be spilled to preallocated space in the stack frame, or
+restored. Complete details are in the Xtensa manuals. The entire windowed
+register file is saved and restored on interrupt or task context switch.
+
+The Call0 ABI does not make use of register windows, relying instead
+on a fixed set of 16 registers without window rotation.
+The Call0 ABI is more conventional and uses registers as follows:
+    a0      = return address
+    a1      = stack pointer (alias sp)
+    a2      = first argument and result of call (in simple cases)
+    a3-7    = second through sixth arguments of call (in simple cases).
+              Note that complex or large arguments are passed on the
+              stack. Details are in the Xtensa Tools manuals.
+    a8-a11  = scratch.
+    a12-a15 = callee-save (a function must preserve these for its caller).
+On a FreeRTOS API call, callee-save registers are saved only when a task
+context switch occurs, and other registers are not saved at all (the caller
+does not expect them to be preserved). On an interrupt, callee-saved
+registers might only be saved and restored when a task context-switch
+occurs, but all other registers are always saved and restored.
+
+An Xtensa processor has other special registers independent of the ABI,
+depending on the configuration (including co-processor registers and other
+TIE state) that are part of the task context. FreeRTOS preserves all such
+registers over an unsolicited context-switch triggered by an interrupt.
+However it does NOT preserve these over a solicited context-switch during
+a FreeRTOS API call. This bears some explanation. These special registers
+are either ignored by the compiler or treated as caller-saved, meaning
+that if kept "live" over a function call (ie. need to be preserved)
+they must be saved and restored by the caller. Since solicited entry to
+FreeRTOS is always made by a function call, FreeRTOS assumes the caller
+has saved any of these registers that are "live". FreeRTOS avoids a lot
+of overhead by not having to save and restore every special register
+(there can be many) on every solicited context switch.
+
+As a consequence, the application developer should NOT assume that special
+registers are preserved over a FreeRTOS API call such as vTaskDelay().
+If multiple tasks use a register, the caller must save and restore it.
+
+The saved context stack frames for context switches that occur as
+a result of interrupt handling (interrupt frame) or from task-level
+API calls (solicited frame) are described in human readable form in
+xtensa_context.h .  All suspended tasks have one of these two types
+of stack frames. The top of the suspended task's stack is pointed to
+by pxCurrentTCB->pxTopOfStack. A special location common to both stack
+frames differentiates solicited and interrupt stack frames.
+
+
+Improving Performance, Footprint, or Ease of Debugging
+------------------------------------------------------
+
+By default FreeRTOS for Xtensa is built with debug (-g) and without
+compiler optimizations (-O0). This makes debugging easier. Of course,
+-O0 costs performance and usually also increases stack usage. To make
+FreeRTOS run faster you can change the Makefile to enable the desired
+optimizations or set a predefined optimization level (-O) .
+
+Maximum performance is achieved with -O3 -ipa, but that might increase 
+the footprint substantially. A good compromise is -O2. See the compiler
+manual for details.
+
+Minimal footprint is achieved by optimizing for space with -Os, at the
+cost of some performance. See the compiler manual for details.
+
+The Xtensa architecture port-specific assembly files are coded with no
+file-scope labels inside functions (all labels inside functions begin with
+".L"). This allows a profiler to accurately associate an address with a
+function, and also allows the debugger's stack trace to show the correct
+function wherever the program counter is within that function. However
+there are some tradeoffs in debugging. Local (".L") labels are not
+visible to the debugger, so the following limitations may be observed
+during debugging:
+- You cannot set a breakpoint on a local label inside a function.
+- Disassembly will show the entire function, but will get out of sync and
+  show incorrect opcodes if it crosses any padding before an aligned local
+  branch target (".L" label, not ".Ln"). Restart disassembly specifying an
+  address range explicitly between points where there is padding.
+Since FreeRTOS is provided in source form, it is not difficult to remove
+the ".L" and ".Ln" prefixes from local labels if you want them visible.
+They can also be made visible by passing the '-L' option to the assembler
+and linker (see the assembler and linker manuals for details).
+
+
+Interrupt and Exception Handling
+--------------------------------
+
+FreeRTOS provides a complete set of efficient exception and first-level
+interrupt handlers installed at the appropriate exception and interrupt
+vector locations. The Xtensa architecture supports several different
+classes of exceptions and interrupts. Being a configurable architecture,
+many of these are optional, and the vector locations are determined by
+your processor configuration. (Note that Diamond cores are pre-configured
+with specific vector locations.) The handlers provided use conditional
+compilation to adapt to your processor configuration and include only 
+the code that is needed.
+
+Xtensa vector locations may reside almost anywhere, including in ROM.
+The amount of code space available at each of these locations is
+often very small (e.g. due to following vectors). A small stub of
+code installed at the vector jumps to the corresponding handler,
+usually in RAM. The exception and interrupt handlers are defined in
+xtensa_vectors.S. They are not specific to FreeRTOS, but call into
+FreeRTOS where appropriate via macros defined in xtensa_rtos.h .
+
+The handlers provided for low and medium priority interrupts are just
+dispatchers that save relevant state and call user-definable handlers.
+See the files xtensa_vectors.S and xtensa_api.h for more details of how
+to create and install application-specific user interrupt handlers.
+Similarly, user-defined handlers can be installed for exceptions (other
+than a few which are always handled by the OS).
+
+The high priority interrupt handlers provided may be considered templates
+into which the application adds code to service specific interrupts.
+The places where application handlers should be inserted are tagged with
+the comment "USER_EDIT" in xtensa_vectors.S.
+
+This FreeRTOS port supports strict priority-based nesting of interrupts.
+An interrupt may only nest on top of one of strictly lower priority.
+Equal priority interrupts concurrently pending are handled in an
+application-defined sequence before any lower priority interrupts
+are handled. During interrupt and exception handling, the processor's
+interrupt level (PS.INTLEVEL) is used to control the interrupt priority
+level that can be accepted; interrupt sources are not controlled
+individually by FreeRTOS (the application is free to access the INTENABLE
+register directly to enable/disable individual interrupts, eg. using
+Xtensa HAL services). This approach provides the most deterministic
+bounds on interrupt latency (for a given priority) and stack depth.
+
+Software prioritization of interrupts at the same priority is controlled
+by the definition of XT_USE_SWPRI. See above for a description of this
+parameter.
+
+The following subsections describe the handling of each class of exception
+and interrupt in more detail. Many have nothing to do with FreeRTOS but
+are mentioned because there is code to handle them in xtensa_vectors.S.
+
+User Exception and Interrupt Handler (Low/Medium Priority):
+
+    All Xtensa 'general exceptions' come to the user, kernel, or double
+    exception vector.  The exception type is identified by the EXCCAUSE
+    special register (level 1 interrupts are one particular cause of a
+    general exception). This port sets up PS to direct all such exceptions
+    to the user vector. Exceptions taken at the other two vectors usually
+    indicate a kernel or application bug.
+
+    Level 1 interrupts are identified at the beginning of the handler
+    and are dispatched to a dedicated handler. Then, syscall and alloca
+    exceptions are identified and dispatched to special handlers described
+    below. After this, coprocessor exceptions are identified and dispatched
+    to the coprocessor handler.
+
+    Any remaining exceptions are processed as follows:
+
+    Having allocated the exception stack frame, the user exception handler
+    saves the current task state and sets up a C environment and enables
+    the high-priority class of interrupts (which do not interact with
+    FreeRTOS), then reads EXCCAUSE and uses the cause (number) to index
+    into a table of user-specified handlers. The correct handler is then
+    called. If the handler returns, the context is restored and control is
+    returned to the code that caused the exception. The user-defined handler
+    may alter the saved context, or any other system state, that allows the
+    faulting instruction to be retried.
+
+    If the cause is a level 1 (low-priority) or medium-priority interrupt,
+    the handler enables all interrupts above that priority level after
+    saving the task context. It then sets up the environment for C code
+    and then calls the handler (found in the handler table) for the
+    interrupt number. If the user has not specified a handler, then the
+    default handler will be called, which will terminate the program.
+
+    If the interrupt is for the system timer, it calls a special interrupt
+    handler for the system timer tick, which calls _frxt_timer_int then
+    clears its bit from the mask. This interrupt cannot be hooked by the
+    user-defined handler.
+
+    Finally, the handler calls _frxt_int_exit to allow FreeRTOS to perform
+    any scheduling necessary and return either to the interrupted task
+    or another.
+
+    If software prioritization is enabled, the handler will re-enable all
+    interrupts at the same level that are numerically higher than the current
+    one, before calling the user handler. This allows a higher priority
+    interrupt to pre-empt the lower priority handler.
+
+Medium Priority Interrupt Handlers:
+
+    Medium priority interrupts are those at levels 2 up to XCHAL_EXCM_LEVEL,
+    a configuration-specific maximum interrupt level affected by the global
+    'exception mode' bit in the processor status word (PS.EXCM).
+    Interrupt levels above XCHAL_EXCM_LEVEL are of the high-priority class.
+    The Xtensa hardware documentation considers medium priority interrupts
+    to be a special case of high-priority interrupts, but from a software
+    perspective they are very different.
+
+    Dispatch of medium-priority interrupts is discussed in the section
+    above.
+
+High Priority Interrupt Handlers:
+
+    High priority interrupts are those strictly above XCHAL_EXCM_LEVEL, 
+    a configuration-specific maximum interrupt level affected by the 
+    global 'exception mode' bit in the processor status word (PS.EXCM).
+    High priority handlers may not directly interact with FreeRTOS at all,
+    and are described here only for the sake of completeness. They must
+    be coded in assembler (may not be coded in C) and are intended to be 
+    used for handling extremely high frequency hardware events that need
+    to be handled in only a few cycles. A high priority interrupt handler
+    may trigger a software interrupt at a medium or low priority level to
+    occasionally signal FreeRTOS. Please see Xtensa documentation.
+
+    There is a separate vector and a few special registers for each high
+    priority interrupt, providing for fast dispatch and efficient nesting
+    on top of lower priority interrupts. Handlers are templates included
+    only for the vectors that exist in your Xtensa processor configuration.
+    These templates are written for only one interrupt per high priority 
+    level to minimize latency servicing very fast time-critical interrupts.
+    The vector code jumps to the corresponding first-level interrupt handler,
+    which then executes application-provided assembler code before returning
+    quickly to the interrupted task or lower priority handler.
+
+Kernel Exception Handler:
+
+    Kernel mode is not used in this port of FreeRTOS, and therefore kernel
+    exceptions should not happen. A stub is provided for the vector that
+    triggers the debugger (if connected) or calls _xt_panic to freeze the 
+    processor should a kernel exception occur.
+
+Alloca Exception Handler:
+
+    Alloca exceptions are generated by the 'movsp' instruction, which
+    is used only in the windowed ABI. Its purpose is to allocate some
+    space on top of the stack. Because the window hardware may have
+    spilled some registers to the 16 byte "base save" area below the
+    stack pointer, it is necessary to protect those values. The alloca
+    handler accomplishes this quickly without setting up an interrupt
+    frame or entering FreeRTOS, by emulating a register underflow and
+    re-executing 'movsp'.
+
+Syscall Exception Handler:
+
+    Syscall exceptions are generated by a 'syscall' instruction.
+    The windowed ABI specifies that executing this instruction with
+    a value of zero in register a2 must spill any unsaved registers
+    in the windowed register file to their pre-determined locations
+    on the caller's stack. The handler does exactly that, and skips
+    over the 'syscall' instruction before returning to the caller.
+    If a2 is non-zero, the handler returns a2 == -1 to the caller.
+
+Co-Processor Exception Handler:
+
+    A co-processor exception is generated when a task accesses a
+    co-processor that it does not "own". Ownership represents which
+    task's state is currently in the co-processor. Co-processors are
+    context-switched "lazily" (on demand) only when a non-owning task
+    uses a co-processor instruction, otherwise a task retains ownership
+    even when it is preempted from the main processor. The co-processor
+    exception handler performs the context-switch and manages ownership.
+
+    Co-processors may not be used by any code outside the context of a
+    task. A co-processor exception triggered by code that is not part
+    of a running task is a fatal error and FreeRTOS for Xtensa will panic.
+    This restriction is intended to reduce the overhead of saving and 
+    restoring co-processor state (which can be quite large) and in 
+    particular remove that overhead from interrupt handlers.
+
+Debug Exception Handler:
+
+    A debug exception is caused as a result of running code, such as by
+    a 'break' instruction or hardware breakpoints and watchpoints, or
+    as a result of an external debug interrupt, such as from an OCD based
+    debugger or multiprocessor debug events ("breakin/breakout"). If the
+    processor is running in OCD mode under control of an OCD-based debugger,
+    the trigger event immediately halts the processor and gives control to
+    the OCD debugger. Otherwise control is transferred to the debug vector.
+    The debug vector handler calls the simulator if running on the ISS,
+    which then takes control and interacts with any attached debugger.
+    If running on hardware and not in OCD mode, debug exceptions are not
+    expected, so the debug handler calls _xt_panic to freeze the processor.
+
+Double Exception Handler:
+
+    A double exception is a general exception that happens while the
+    processor is in exception mode (PS.EXCM set), and thus indicates a
+    bug in kernel code. The double exception vector handler triggers
+    the debugger (if connected) or calls _xt_panic to freeze the 
+    processor.
+
+Window Overflow and Underflow Exception Handlers:
+
+    Window overflow and underflow handlers are required for use of the
+    windowed ABI. Each has its own dedicated vector and highly optimized
+    code that is independent of OS. See Xtensa documentation for details.
+
+Hooks for Dynamic Installation of Handlers:
+
+    Optional hooks are provided in the user exception and low level
+    interrupt handler and all medium and high priority interrupt handlers,
+    to dynamically install a handler function (which may be coded in C,
+    unless in a high-priority interrupt handler). These hooks are enabled
+    and used by automatic regression tests, they are not part of a normal
+    FreeRTOS build. However an application is free to take advantage of
+    them. The interrupt/exception hooks are described in xtensa_rtos.h .
+
+    It is recommended that the application not make use of these hooks, but
+    rather use xt_set_interrupt_handler() and xt_set_exception_handler()
+    to install application-specific handlers. This method is more convenient
+    and allows arguments to be passed to the handlers. Software prioritization
+    of interrupts works only with this method. See xtensa_api.h for details.
+
+Overlay Support
+
+    Code overlays are currently not supported for FreeRTOS. This will be
+    supported in a future release. Make sure that the option XT_USE_OVLY is
+    never defined when building.
+
+
+-End-
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_api.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_api.h
new file mode 100644
index 0000000..1be2905
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_api.h
@@ -0,0 +1,123 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Xtensa-specific API for RTOS ports.
+ */
+
+#ifndef __XTENSA_API_H__
+#define __XTENSA_API_H__
+
+#include 
+
+#include "xtensa_context.h"
+
+
+/* Typedef for C-callable interrupt handler function */
+typedef void (*xt_handler)(void *);
+
+/* Typedef for C-callable exception handler function */
+typedef void (*xt_exc_handler)(XtExcFrame *);
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to set a handler for the specified exception.
+
+    n        - Exception number (type)
+    f        - Handler function address, NULL to uninstall handler.
+
+  The handler will be passed a pointer to the exception frame, which is created
+  on the stack of the thread that caused the exception.
+
+  If the handler returns, the thread context will be restored and the faulting
+  instruction will be retried. Any values in the exception frame that are
+  modified by the handler will be restored as part of the context. For details
+  of the exception frame structure see xtensa_context.h.
+-------------------------------------------------------------------------------
+*/
+extern xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f);
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to set a handler for the specified interrupt.
+ 
+    n        - Interrupt number.
+    f        - Handler function address, NULL to uninstall handler.
+    arg      - Argument to be passed to handler.
+-------------------------------------------------------------------------------
+*/
+extern xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg);
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to enable the specified interrupts.
+
+    mask     - Bit mask of interrupts to be enabled.
+
+  Returns the previous state of the interrupt enables.
+-------------------------------------------------------------------------------
+*/
+extern unsigned int xt_ints_on(unsigned int mask);
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to disable the specified interrupts.
+
+    mask     - Bit mask of interrupts to be disabled.
+
+  Returns the previous state of the interrupt enables.
+-------------------------------------------------------------------------------
+*/
+extern unsigned int xt_ints_off(unsigned int mask);
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to set the specified (s/w) interrupt.
+-------------------------------------------------------------------------------
+*/
+static inline void xt_set_intset(unsigned int arg)
+{
+    xthal_set_intset(arg);
+}
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to clear the specified (s/w or edge-triggered)
+  interrupt.
+-------------------------------------------------------------------------------
+*/
+static inline void xt_set_intclear(unsigned int arg)
+{
+    xthal_set_intclear(arg);
+}
+
+
+#endif /* __XTENSA_API_H__ */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_config.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_config.h
new file mode 100644
index 0000000..308361f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_config.h
@@ -0,0 +1,183 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Configuration-specific information for Xtensa build. This file must be
+ * included in FreeRTOSConfig.h to properly set up the config-dependent
+ * parameters correctly.
+ *
+ * NOTE: To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must
+ * be defined to be > 0 somewhere above or on the command line.
+ */
+
+#ifndef XTENSA_CONFIG_H
+#define XTENSA_CONFIG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+#include 
+#include 	/* required for XSHAL_CLIB */
+
+#include "xtensa_context.h"
+
+
+/*-----------------------------------------------------------------------------
+*                                 STACK REQUIREMENTS
+*
+* This section defines the minimum stack size, and the extra space required to
+* be allocated for saving coprocessor state and/or C library state information
+* (if thread safety is enabled for the C library). The sizes are in bytes.
+*
+* Stack sizes for individual tasks should be derived from these minima based on
+* the maximum call depth of the task and the maximum level of interrupt nesting.
+* A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based
+* on the requirement for a task that calls nothing else but can be interrupted.
+* This assumes that interrupt handlers do not call more than a few levels deep.
+* If this is not true, i.e. one or more interrupt handlers make deep calls then
+* the minimum must be increased.
+*
+* If the Xtensa processor configuration includes coprocessors, then space is 
+* allocated to save the coprocessor state on the stack.
+*
+* If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
+* is defined) then space is allocated to save the C library context in the TCB.
+* 
+* Allocating insufficient stack space is a common source of hard-to-find errors.
+* During development, it is best to enable the FreeRTOS stack checking features.
+*
+* Usage:
+* 
+* XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe
+*                            use of the C library. This will require extra stack
+*                            space to be allocated for tasks that use the C library
+*                            reentrant functions. See below for more information.
+* 
+* NOTE: The Xtensa toolchain supports multiple C libraries and not all of them
+* support thread safety. Check your core configuration to see which C library
+* was chosen for your system.
+* 
+* XT_STACK_MIN_SIZE       -- The minimum stack size for any task. It is recommended
+*                            that you do not use a stack smaller than this for any
+*                            task. In case you want to use stacks smaller than this
+*                            size, you must verify that the smaller size(s) will work
+*                            under all operating conditions.
+*
+* XT_STACK_EXTRA          -- The amount of extra stack space to allocate for a task
+*                            that does not make C library reentrant calls. Add this
+*                            to the amount of stack space required by the task itself.
+*
+* XT_STACK_EXTRA_CLIB     -- The amount of space to allocate for C library state.
+*
+-----------------------------------------------------------------------------*/
+
+/* Extra space required for interrupt/exception hooks. */
+#ifdef XT_INTEXC_HOOKS
+  #ifdef __XTENSA_CALL0_ABI__
+    #define STK_INTEXC_EXTRA        0x200
+  #else
+    #define STK_INTEXC_EXTRA        0x180
+  #endif
+#else
+  #define STK_INTEXC_EXTRA          0
+#endif
+
+/* Check C library thread safety support and compute size of C library save area.
+   For the supported libraries, we enable thread safety by default, and this can
+   be overridden from the compiler/make command line. */
+#if (XSHAL_CLIB == XTHAL_CLIB_NEWLIB) || (XSHAL_CLIB == XTHAL_CLIB_XCLIB)
+  #ifndef XT_USE_THREAD_SAFE_CLIB
+    #define XT_USE_THREAD_SAFE_CLIB         1
+  #endif
+#else
+  #define XT_USE_THREAD_SAFE_CLIB           0
+#endif
+
+#if XT_USE_THREAD_SAFE_CLIB > 0u
+  #if XSHAL_CLIB == XTHAL_CLIB_XCLIB
+    #define XT_HAVE_THREAD_SAFE_CLIB        1
+    #if !defined __ASSEMBLER__
+      #include 
+      #define XT_CLIB_CONTEXT_AREA_SIZE     ((sizeof(struct _reent) + 15) + (-16))
+      #define XT_CLIB_GLOBAL_PTR            _reent_ptr
+      #define _REENT_INIT_PTR               _init_reent
+      #define _impure_ptr                   _reent_ptr
+
+      void _reclaim_reent(void * ptr);
+    #endif
+  #elif XSHAL_CLIB == XTHAL_CLIB_NEWLIB
+    #define XT_HAVE_THREAD_SAFE_CLIB        1
+    #if !defined __ASSEMBLER__
+      #include 
+      #define XT_CLIB_CONTEXT_AREA_SIZE     ((sizeof(struct _reent) + 15) + (-16))
+      #define XT_CLIB_GLOBAL_PTR            _impure_ptr
+    #endif
+  #else
+    #define XT_HAVE_THREAD_SAFE_CLIB        0
+    #error The selected C runtime library is not thread safe.
+  #endif
+#else
+  #define XT_CLIB_CONTEXT_AREA_SIZE         0
+#endif
+
+/*------------------------------------------------------------------------------
+  Extra size -- interrupt frame plus coprocessor save area plus hook space.
+  NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
+------------------------------------------------------------------------------*/
+#ifdef __XTENSA_CALL0_ABI__
+  #define XT_XTRA_SIZE            (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE)
+#else
+  #define XT_XTRA_SIZE            (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE)
+#endif
+
+/*------------------------------------------------------------------------------
+  Space allocated for user code -- function calls and local variables.
+  NOTE: This number can be adjusted to suit your needs. You must verify that the
+  amount of space you reserve is adequate for the worst-case conditions in your
+  application.
+  NOTE: The windowed ABI requires more stack, since space has to be reserved
+  for spilling register windows.
+------------------------------------------------------------------------------*/
+#ifdef __XTENSA_CALL0_ABI__
+  #define XT_USER_SIZE            0x200
+#else
+  #define XT_USER_SIZE            0x400
+#endif
+
+/* Minimum recommended stack size. */
+#define XT_STACK_MIN_SIZE         ((XT_XTRA_SIZE + XT_USER_SIZE) / sizeof(unsigned char))
+
+/* OS overhead with and without C library thread context. */
+#define XT_STACK_EXTRA              (XT_XTRA_SIZE)
+#define XT_STACK_EXTRA_CLIB         (XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XTENSA_CONFIG_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.S
new file mode 100644
index 0000000..7e10b13
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.S
@@ -0,0 +1,625 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * XTENSA CONTEXT SAVE AND RESTORE ROUTINES
+ *
+ * Low-level Call0 functions for handling generic context save and restore of
+ * registers not specifically addressed by the interrupt vectors and handlers.
+ * Those registers (not handled by these functions) are PC, PS, A0, A1 (SP).
+ * Except for the calls to RTOS functions, this code is generic to Xtensa.
+ *
+ * Note that in Call0 ABI, interrupt handlers are expected to preserve the callee-
+ * save regs (A12-A15), which is always the case if the handlers are coded in C.
+ * However A12, A13 are made available as scratch registers for interrupt dispatch
+ * code, so are presumed saved anyway, and are always restored even in Call0 ABI.
+ * Only A14, A15 are truly handled as callee-save regs.
+ *
+ * Because Xtensa is a configurable architecture, this port supports all user
+ * generated configurations (except restrictions stated in the release notes).
+ * This is accomplished by conditional compilation using macros and functions
+ * defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
+ * Only the processor state included in your configuration is saved and restored,
+ * including any processor state added by user configuration options or TIE.
+ */
+
+/*  Warn nicely if this file gets named with a lowercase .s instead of .S:  */
+#define NOERROR #
+NOERROR: .error "C preprocessor needed for this file: make sure its filename\
+ ends in uppercase .S, or use xt-xcc's -x assembler-with-cpp option."
+
+
+#include "xtensa_rtos.h"
+
+#ifdef XT_USE_OVLY
+#include 
+#endif
+
+    .text
+
+/*******************************************************************************
+
+_xt_context_save
+
+    !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
+
+Saves all Xtensa processor state except PC, PS, A0, A1 (SP), A12, A13, in the
+interrupt stack frame defined in xtensa_rtos.h.
+Its counterpart is _xt_context_restore (which also restores A12, A13).
+
+Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the frame.
+This function preserves A12 & A13 in order to provide the caller with 2 scratch 
+regs that need not be saved over the call to this function. The choice of which
+2 regs to provide is governed by xthal_window_spill_nw and xthal_save_extra_nw,
+to avoid moving data more than necessary. Caller can assign regs accordingly.
+
+Entry Conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+    Original A12, A13 have already been saved in the interrupt stack frame.
+    Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the 
+    point of interruption.
+    If windowed ABI, PS.EXCM = 1 (exceptions disabled).
+
+Exit conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+    A12, A13 as at entry (preserved).
+    If windowed ABI, PS.EXCM = 1 (exceptions disabled).
+
+*******************************************************************************/
+
+    .global _xt_context_save
+    .type   _xt_context_save,@function
+    .align  4
+_xt_context_save:
+
+    s32i    a2,  sp, XT_STK_A2
+    s32i    a3,  sp, XT_STK_A3
+    s32i    a4,  sp, XT_STK_A4
+    s32i    a5,  sp, XT_STK_A5
+    s32i    a6,  sp, XT_STK_A6
+    s32i    a7,  sp, XT_STK_A7
+    s32i    a8,  sp, XT_STK_A8
+    s32i    a9,  sp, XT_STK_A9
+    s32i    a10, sp, XT_STK_A10
+    s32i    a11, sp, XT_STK_A11
+
+    /*
+    Call0 ABI callee-saved regs a12-15 do not need to be saved here.
+    a12-13 are the caller's responsibility so it can use them as scratch.
+    So only need to save a14-a15 here for Windowed ABI (not Call0).
+    */
+    #ifndef __XTENSA_CALL0_ABI__
+    s32i    a14, sp, XT_STK_A14
+    s32i    a15, sp, XT_STK_A15
+    #endif
+
+    rsr     a3,  SAR
+    s32i    a3,  sp, XT_STK_SAR
+
+    #if XCHAL_HAVE_LOOPS
+    rsr     a3,  LBEG
+    s32i    a3,  sp, XT_STK_LBEG
+    rsr     a3,  LEND
+    s32i    a3,  sp, XT_STK_LEND
+    rsr     a3,  LCOUNT
+    s32i    a3,  sp, XT_STK_LCOUNT
+    #endif
+
+    #if XT_USE_SWPRI
+    /* Save virtual priority mask */
+    movi    a3,  _xt_vpri_mask
+    l32i    a3,  a3, 0
+    s32i    a3,  sp, XT_STK_VPRI
+    #endif
+
+    #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
+    mov     a9,  a0                     /* preserve ret addr */
+    #endif
+
+    #ifndef __XTENSA_CALL0_ABI__
+    /*
+    To spill the reg windows, temp. need pre-interrupt stack ptr and a4-15.
+    Need to save a9,12,13 temporarily (in frame temps) and recover originals.
+    Interrupts need to be disabled below XCHAL_EXCM_LEVEL and window overflow
+    and underflow exceptions disabled (assured by PS.EXCM == 1).
+    */
+    s32i    a12, sp, XT_STK_TMP0        /* temp. save stuff in stack frame */
+    s32i    a13, sp, XT_STK_TMP1    
+    s32i    a9,  sp, XT_STK_TMP2    
+
+    /*
+    Save the overlay state if we are supporting overlays. Since we just saved
+    three registers, we can conveniently use them here. Note that as of now,
+    overlays only work for windowed calling ABI.
+    */
+    #ifdef XT_USE_OVLY
+    l32i    a9,  sp, XT_STK_PC          /* recover saved PC */
+    _xt_overlay_get_state    a9, a12, a13
+    s32i    a9,  sp, XT_STK_OVLY        /* save overlay state */
+    #endif
+
+    l32i    a12, sp, XT_STK_A12         /* recover original a9,12,13 */
+    l32i    a13, sp, XT_STK_A13
+    l32i    a9,  sp, XT_STK_A9
+    addi    sp,  sp, XT_STK_FRMSZ       /* restore the interruptee's SP */
+    call0   xthal_window_spill_nw       /* preserves only a4,5,8,9,12,13 */
+    addi    sp,  sp, -XT_STK_FRMSZ
+    l32i    a12, sp, XT_STK_TMP0        /* recover stuff from stack frame */
+    l32i    a13, sp, XT_STK_TMP1    
+    l32i    a9,  sp, XT_STK_TMP2    
+    #endif
+
+    #if XCHAL_EXTRA_SA_SIZE > 0
+    /*  
+    NOTE: Normally the xthal_save_extra_nw macro only affects address
+    registers a2-a5. It is theoretically possible for Xtensa processor
+    designers to write TIE that causes more address registers to be
+    affected, but it is generally unlikely. If that ever happens,
+    more registers need to be saved/restored around this macro invocation.
+    Here we assume a9,12,13 are preserved.
+    Future Xtensa tools releases might limit the regs that can be affected.
+    */
+    addi    a2,  sp, XT_STK_EXTRA       /* where to save it */
+    # if XCHAL_EXTRA_SA_ALIGN > 16
+    movi    a3, -XCHAL_EXTRA_SA_ALIGN
+    and     a2, a2, a3                  /* align dynamically >16 bytes */
+    # endif
+    call0   xthal_save_extra_nw         /* destroys a0,2,3,4,5 */
+    #endif
+
+    #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
+    mov     a0, a9                      /* retrieve ret addr */
+    #endif
+
+    ret
+
+/*******************************************************************************
+
+_xt_context_restore
+
+    !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
+
+Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in Call0
+ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt 
+stack frame defined in xtensa_rtos.h .
+Its counterpart is _xt_context_save (whose caller saved A12, A13).
+
+Caller is responsible to restore PC, PS, A0, A1 (SP).
+
+Entry Conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+
+Exit conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+    Other processor state except PC, PS, A0, A1 (SP), is as at the point 
+    of interruption.
+
+*******************************************************************************/
+
+    .global _xt_context_restore
+    .type   _xt_context_restore,@function
+    .align  4
+_xt_context_restore:
+
+    #if XCHAL_EXTRA_SA_SIZE > 0
+    /*  
+    NOTE: Normally the xthal_restore_extra_nw macro only affects address
+    registers a2-a5. It is theoretically possible for Xtensa processor
+    designers to write TIE that causes more address registers to be
+    affected, but it is generally unlikely. If that ever happens,
+    more registers need to be saved/restored around this macro invocation.
+    Here we only assume a13 is preserved.
+    Future Xtensa tools releases might limit the regs that can be affected.
+    */
+    mov     a13, a0                     /* preserve ret addr */
+    addi    a2,  sp, XT_STK_EXTRA       /* where to find it */
+    # if XCHAL_EXTRA_SA_ALIGN > 16
+    movi    a3, -XCHAL_EXTRA_SA_ALIGN
+    and     a2, a2, a3                  /* align dynamically >16 bytes */
+    # endif
+    call0   xthal_restore_extra_nw      /* destroys a0,2,3,4,5 */
+    mov     a0,  a13                    /* retrieve ret addr */
+    #endif
+
+    #if XCHAL_HAVE_LOOPS
+    l32i    a2,  sp, XT_STK_LBEG
+    l32i    a3,  sp, XT_STK_LEND
+    wsr     a2,  LBEG
+    l32i    a2,  sp, XT_STK_LCOUNT
+    wsr     a3,  LEND
+    wsr     a2,  LCOUNT
+    #endif
+
+    #ifdef XT_USE_OVLY
+    /*
+    If we are using overlays, this is a good spot to check if we need
+    to restore an overlay for the incoming task. Here we have a bunch
+    of registers to spare. Note that this step is going to use a few
+    bytes of storage below SP (SP-20 to SP-32) if an overlay is going
+    to be restored.
+    */
+    l32i    a2,  sp, XT_STK_PC          /* retrieve PC */
+    l32i    a3,  sp, XT_STK_PS          /* retrieve PS */
+    l32i    a4,  sp, XT_STK_OVLY        /* retrieve overlay state */
+    l32i    a5,  sp, XT_STK_A1          /* retrieve stack ptr */
+    _xt_overlay_check_map    a2, a3, a4, a5, a6
+    s32i    a2,  sp, XT_STK_PC          /* save updated PC */
+    s32i    a3,  sp, XT_STK_PS          /* save updated PS */
+    #endif
+
+    #ifdef XT_USE_SWPRI
+    /* Restore virtual interrupt priority and interrupt enable */
+    movi    a3,  _xt_intdata
+    l32i    a4,  a3, 0                  /* a4 = _xt_intenable */
+    l32i    a5,  sp, XT_STK_VPRI        /* a5 = saved _xt_vpri_mask */
+    and     a4,  a4, a5
+    wsr     a4,  INTENABLE              /* update INTENABLE */
+    s32i    a5,  a3, 4                  /* restore _xt_vpri_mask */
+    #endif
+
+    l32i    a3,  sp, XT_STK_SAR
+    l32i    a2,  sp, XT_STK_A2
+    wsr     a3,  SAR
+    l32i    a3,  sp, XT_STK_A3
+    l32i    a4,  sp, XT_STK_A4
+    l32i    a5,  sp, XT_STK_A5
+    l32i    a6,  sp, XT_STK_A6
+    l32i    a7,  sp, XT_STK_A7
+    l32i    a8,  sp, XT_STK_A8
+    l32i    a9,  sp, XT_STK_A9
+    l32i    a10, sp, XT_STK_A10
+    l32i    a11, sp, XT_STK_A11
+
+    /*
+    Call0 ABI callee-saved regs a12-15 do not need to be restored here.
+    However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(), 
+    so need to be restored anyway, despite being callee-saved in Call0.
+    */
+    l32i    a12, sp, XT_STK_A12
+    l32i    a13, sp, XT_STK_A13
+    #ifndef __XTENSA_CALL0_ABI__
+    l32i    a14, sp, XT_STK_A14
+    l32i    a15, sp, XT_STK_A15
+    #endif
+
+    ret
+
+
+/*******************************************************************************
+
+_xt_coproc_init
+
+Initializes global co-processor management data, setting all co-processors
+to "unowned". Leaves CPENABLE as it found it (does NOT clear it).
+
+Called during initialization of the RTOS, before any threads run.
+
+This may be called from normal Xtensa single-threaded application code which
+might use co-processors. The Xtensa run-time initialization enables all 
+co-processors. They must remain enabled here, else a co-processor exception
+might occur outside of a thread, which the exception handler doesn't expect.
+
+Entry Conditions:
+    Xtensa single-threaded run-time environment is in effect.
+    No thread is yet running.
+
+Exit conditions:
+    None.
+
+Obeys ABI conventions per prototype:
+    void _xt_coproc_init(void)
+
+*******************************************************************************/
+
+#if XCHAL_CP_NUM > 0
+
+    .global _xt_coproc_init
+    .type   _xt_coproc_init,@function
+    .align  4
+_xt_coproc_init:
+    ENTRY0
+
+    /* Initialize thread co-processor ownerships to 0 (unowned). */
+    movi    a2, _xt_coproc_owner_sa         /* a2 = base of owner array */
+    addi    a3, a2, XCHAL_CP_MAX << 2       /* a3 = top+1 of owner array */
+    movi    a4, 0                           /* a4 = 0 (unowned) */
+1:  s32i    a4, a2, 0
+    addi    a2, a2, 4
+    bltu    a2, a3, 1b
+
+    RET0
+
+#endif
+
+
+/*******************************************************************************
+
+_xt_coproc_release
+
+Releases any and all co-processors owned by a given thread. The thread is 
+identified by it's co-processor state save area defined in xtensa_context.h .
+
+Must be called before a thread's co-proc save area is deleted to avoid
+memory corruption when the exception handler tries to save the state.
+May be called when a thread terminates or completes but does not delete
+the co-proc save area, to avoid the exception handler having to save the 
+thread's co-proc state before another thread can use it (optimization).
+
+Entry Conditions:
+    A2  = Pointer to base of co-processor state save area.
+
+Exit conditions:
+    None.
+
+Obeys ABI conventions per prototype:
+    void _xt_coproc_release(void * coproc_sa_base)
+
+*******************************************************************************/
+
+#if XCHAL_CP_NUM > 0
+
+    .global _xt_coproc_release
+    .type   _xt_coproc_release,@function
+    .align  4
+_xt_coproc_release:
+    ENTRY0                                  /* a2 = base of save area */
+
+    movi    a3, _xt_coproc_owner_sa         /* a3 = base of owner array */
+    addi    a4, a3, XCHAL_CP_MAX << 2       /* a4 = top+1 of owner array */
+    movi    a5, 0                           /* a5 = 0 (unowned) */
+
+    rsil    a6, XCHAL_EXCM_LEVEL            /* lock interrupts */
+
+1:  l32i    a7, a3, 0                       /* a7 = owner at a3 */
+    bne     a2, a7, 2f                      /* if (coproc_sa_base == owner) */
+    s32i    a5, a3, 0                       /*   owner = unowned */
+2:  addi    a3, a3, 1<<2                    /* a3 = next entry in owner array */
+    bltu    a3, a4, 1b                      /* repeat until end of array */
+
+3:  wsr     a6, PS                          /* restore interrupts */
+
+    RET0
+
+#endif
+
+
+/*******************************************************************************
+_xt_coproc_savecs
+
+If there is a current thread and it has a coprocessor state save area, then
+save all callee-saved state into this area. This function is called from the
+solicited context switch handler. It calls a system-specific function to get
+the coprocessor save area base address.
+
+Entry conditions:
+    - The thread being switched out is still the current thread.
+    - CPENABLE state reflects which coprocessors are active.
+    - Registers have been saved/spilled already.
+
+Exit conditions:
+    - All necessary CP callee-saved state has been saved.
+    - Registers a2-a7, a13-a15 have been trashed.
+
+Must be called from assembly code only, using CALL0.
+*******************************************************************************/
+#if XCHAL_CP_NUM > 0
+
+    .extern     _xt_coproc_sa_offset   /* external reference */
+
+    .global     _xt_coproc_savecs
+    .type       _xt_coproc_savecs,@function
+    .align      4
+_xt_coproc_savecs:
+
+    /* At entry, CPENABLE should be showing which CPs are enabled. */
+
+    rsr     a2, CPENABLE                /* a2 = which CPs are enabled      */
+    beqz    a2, .Ldone                  /* quick exit if none              */
+    mov     a14, a0                     /* save return address             */
+    call0   XT_RTOS_CP_STATE            /* get address of CP save area     */
+    mov     a0, a14                     /* restore return address          */
+    beqz    a15, .Ldone                 /* if none then nothing to do      */
+    s16i    a2, a15, XT_CP_CS_ST        /* save mask of CPs being stored   */
+    movi    a13, _xt_coproc_sa_offset   /* array of CP save offsets        */
+    l32i    a15, a15, XT_CP_ASA         /* a15 = base of aligned save area */
+
+#if XCHAL_CP0_SA_SIZE
+    bbci.l  a2, 0, 2f                   /* CP 0 not enabled                */
+    l32i    a14, a13, 0                 /* a14 = _xt_coproc_sa_offset[0]   */
+    add     a3, a14, a15                /* a3 = save area for CP 0         */
+    xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP1_SA_SIZE
+    bbci.l  a2, 1, 2f                   /* CP 1 not enabled                */
+    l32i    a14, a13, 4                 /* a14 = _xt_coproc_sa_offset[1]   */
+    add     a3, a14, a15                /* a3 = save area for CP 1         */
+    xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP2_SA_SIZE
+    bbci.l  a2, 2, 2f
+    l32i    a14, a13, 8
+    add     a3, a14, a15
+    xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP3_SA_SIZE
+    bbci.l  a2, 3, 2f
+    l32i    a14, a13, 12
+    add     a3, a14, a15
+    xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP4_SA_SIZE
+    bbci.l  a2, 4, 2f
+    l32i    a14, a13, 16
+    add     a3, a14, a15
+    xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP5_SA_SIZE
+    bbci.l  a2, 5, 2f
+    l32i    a14, a13, 20
+    add     a3, a14, a15
+    xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP6_SA_SIZE
+    bbci.l  a2, 6, 2f
+    l32i    a14, a13, 24
+    add     a3, a14, a15
+    xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP7_SA_SIZE
+    bbci.l  a2, 7, 2f
+    l32i    a14, a13, 28
+    add     a3, a14, a15
+    xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+.Ldone:
+    ret
+#endif
+
+
+/*******************************************************************************
+_xt_coproc_restorecs
+
+Restore any callee-saved coprocessor state for the incoming thread.
+This function is called from coprocessor exception handling, when giving
+ownership to a thread that solicited a context switch earlier. It calls a
+system-specific function to get the coprocessor save area base address.
+
+Entry conditions:
+    - The incoming thread is set as the current thread.
+    - CPENABLE is set up correctly for all required coprocessors.
+    - a2 = mask of coprocessors to be restored.
+
+Exit conditions:
+    - All necessary CP callee-saved state has been restored.
+    - CPENABLE - unchanged.
+    - Registers a2-a7, a13-a15 have been trashed.
+
+Must be called from assembly code only, using CALL0.
+*******************************************************************************/
+#if XCHAL_CP_NUM > 0
+
+    .global     _xt_coproc_restorecs
+    .type       _xt_coproc_restorecs,@function
+    .align      4
+_xt_coproc_restorecs:
+
+    mov     a14, a0                     /* save return address             */
+    call0   XT_RTOS_CP_STATE            /* get address of CP save area     */
+    mov     a0, a14                     /* restore return address          */
+    beqz    a15, .Ldone2                /* if none then nothing to do      */
+    l16ui   a3, a15, XT_CP_CS_ST        /* a3 = which CPs have been saved  */
+    xor     a3, a3, a2                  /* clear the ones being restored   */
+    s32i    a3, a15, XT_CP_CS_ST        /* update saved CP mask            */
+    movi    a13, _xt_coproc_sa_offset   /* array of CP save offsets        */
+    l32i    a15, a15, XT_CP_ASA         /* a15 = base of aligned save area */
+    
+#if XCHAL_CP0_SA_SIZE
+    bbci.l  a2, 0, 2f                   /* CP 0 not enabled                */
+    l32i    a14, a13, 0                 /* a14 = _xt_coproc_sa_offset[0]   */
+    add     a3, a14, a15                /* a3 = save area for CP 0         */
+    xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:  
+#endif
+
+#if XCHAL_CP1_SA_SIZE
+    bbci.l  a2, 1, 2f                   /* CP 1 not enabled                */
+    l32i    a14, a13, 4                 /* a14 = _xt_coproc_sa_offset[1]   */
+    add     a3, a14, a15                /* a3 = save area for CP 1         */
+    xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP2_SA_SIZE
+    bbci.l  a2, 2, 2f
+    l32i    a14, a13, 8
+    add     a3, a14, a15
+    xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP3_SA_SIZE
+    bbci.l  a2, 3, 2f
+    l32i    a14, a13, 12
+    add     a3, a14, a15
+    xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP4_SA_SIZE
+    bbci.l  a2, 4, 2f
+    l32i    a14, a13, 16
+    add     a3, a14, a15
+    xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP5_SA_SIZE
+    bbci.l  a2, 5, 2f
+    l32i    a14, a13, 20
+    add     a3, a14, a15
+    xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP6_SA_SIZE
+    bbci.l  a2, 6, 2f
+    l32i    a14, a13, 24
+    add     a3, a14, a15
+    xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP7_SA_SIZE
+    bbci.l  a2, 7, 2f
+    l32i    a14, a13, 28
+    add     a3, a14, a15
+    xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+.Ldone2:
+    ret
+
+#endif
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
new file mode 100644
index 0000000..122d236
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
@@ -0,0 +1,351 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES
+ *
+ * This header contains definitions and macros for use primarily by Xtensa
+ * RTOS assembly coded source files. It includes and uses the Xtensa hardware
+ * abstraction layer (HAL) to deal with config specifics. It may also be
+ * included in C source files.
+ *
+ * !! Supports only Xtensa Exception Architecture 2 (XEA2). XEA1 not supported. !!
+ *
+ * NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes.
+ */
+
+#ifndef XTENSA_CONTEXT_H
+#define XTENSA_CONTEXT_H
+
+#ifdef __ASSEMBLER__
+#include    
+#endif
+
+#include    
+#include    
+#include    
+
+
+/* Align a value up to nearest n-byte boundary, where n is a power of 2. */
+#define ALIGNUP(n, val) (((val) + (n)-1) & -(n))
+
+
+/*
+-------------------------------------------------------------------------------
+  Macros that help define structures for both C and assembler.
+-------------------------------------------------------------------------------
+*/
+#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
+
+#define STRUCT_BEGIN            .pushsection .text; .struct 0
+#define STRUCT_FIELD(ctype,size,asname,name)    asname: .space  size
+#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space  (size)*(n)
+#define STRUCT_END(sname)       sname##Size:; .popsection
+
+#else
+
+#define STRUCT_BEGIN            typedef struct {
+#define STRUCT_FIELD(ctype,size,asname,name)    ctype   name;
+#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype   name[n];
+#define STRUCT_END(sname)       } sname;
+
+#endif //_ASMLANGUAGE || __ASSEMBLER__
+
+
+/*
+-------------------------------------------------------------------------------
+  INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
+
+  A stack frame of this structure is allocated for any interrupt or exception.
+  It goes on the current stack. If the RTOS has a system stack for handling 
+  interrupts, every thread stack must allow space for just one interrupt stack 
+  frame, then nested interrupt stack frames go on the system stack.
+
+  The frame includes basic registers (explicit) and "extra" registers introduced 
+  by user TIE or the use of the MAC16 option in the user's Xtensa config.
+  The frame size is minimized by omitting regs not applicable to user's config.
+
+  For Windowed ABI, this stack frame includes the interruptee's base save area,
+  another base save area to manage gcc nested functions, and a little temporary 
+  space to help manage the spilling of the register windows.
+-------------------------------------------------------------------------------
+*/
+
+STRUCT_BEGIN
+STRUCT_FIELD (long, 4, XT_STK_EXIT,     exit) /* exit point for dispatch */
+STRUCT_FIELD (long, 4, XT_STK_PC,       pc)   /* return PC */
+STRUCT_FIELD (long, 4, XT_STK_PS,       ps)   /* return PS */
+STRUCT_FIELD (long, 4, XT_STK_A0,       a0)
+STRUCT_FIELD (long, 4, XT_STK_A1,       a1)   /* stack pointer before interrupt */
+STRUCT_FIELD (long, 4, XT_STK_A2,       a2)
+STRUCT_FIELD (long, 4, XT_STK_A3,       a3)
+STRUCT_FIELD (long, 4, XT_STK_A4,       a4)
+STRUCT_FIELD (long, 4, XT_STK_A5,       a5)
+STRUCT_FIELD (long, 4, XT_STK_A6,       a6)
+STRUCT_FIELD (long, 4, XT_STK_A7,       a7)
+STRUCT_FIELD (long, 4, XT_STK_A8,       a8)
+STRUCT_FIELD (long, 4, XT_STK_A9,       a9)
+STRUCT_FIELD (long, 4, XT_STK_A10,      a10)
+STRUCT_FIELD (long, 4, XT_STK_A11,      a11)
+STRUCT_FIELD (long, 4, XT_STK_A12,      a12)
+STRUCT_FIELD (long, 4, XT_STK_A13,      a13)
+STRUCT_FIELD (long, 4, XT_STK_A14,      a14)
+STRUCT_FIELD (long, 4, XT_STK_A15,      a15)
+STRUCT_FIELD (long, 4, XT_STK_SAR,      sar)
+STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause)
+STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr)
+#if XCHAL_HAVE_LOOPS
+STRUCT_FIELD (long, 4, XT_STK_LBEG,   lbeg)
+STRUCT_FIELD (long, 4, XT_STK_LEND,   lend)
+STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount)
+#endif
+#ifndef __XTENSA_CALL0_ABI__
+/* Temporary space for saving stuff during window spill */
+STRUCT_FIELD (long, 4, XT_STK_TMP0,   tmp0)
+STRUCT_FIELD (long, 4, XT_STK_TMP1,   tmp1)
+STRUCT_FIELD (long, 4, XT_STK_TMP2,   tmp2)
+#endif
+#ifdef XT_USE_SWPRI
+/* Storage for virtual priority mask */
+STRUCT_FIELD (long, 4, XT_STK_VPRI,   vpri)
+#endif
+#ifdef XT_USE_OVLY
+/* Storage for overlay state */
+STRUCT_FIELD (long, 4, XT_STK_OVLY,   ovly)
+#endif
+STRUCT_END(XtExcFrame)
+
+#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
+#define XT_STK_NEXT1      XtExcFrameSize
+#else
+#define XT_STK_NEXT1      sizeof(XtExcFrame)
+#endif
+
+/* Allocate extra storage if needed */
+#if XCHAL_EXTRA_SA_SIZE != 0
+
+#if XCHAL_EXTRA_SA_ALIGN <= 16
+#define XT_STK_EXTRA            ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1)
+#else
+/* If need more alignment than stack, add space for dynamic alignment */
+#define XT_STK_EXTRA            (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN)
+#endif
+#define XT_STK_NEXT2            (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE)
+
+#else
+
+#define XT_STK_NEXT2            XT_STK_NEXT1   
+
+#endif
+
+/*
+-------------------------------------------------------------------------------
+  This is the frame size. Add space for 4 registers (interruptee's base save
+  area) and some space for gcc nested functions if any.
+-------------------------------------------------------------------------------
+*/
+#define XT_STK_FRMSZ            (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20)
+
+
+/*
+-------------------------------------------------------------------------------
+  SOLICITED STACK FRAME FOR A THREAD
+
+  A stack frame of this structure is allocated whenever a thread enters the 
+  RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
+  It goes on the current thread's stack.
+
+  The solicited frame only includes registers that are required to be preserved
+  by the callee according to the compiler's ABI conventions, some space to save 
+  the return address for returning to the caller, and the caller's PS register.
+
+  For Windowed ABI, this stack frame includes the caller's base save area.
+
+  Note on XT_SOL_EXIT field:
+      It is necessary to distinguish a solicited from an interrupt stack frame.
+      This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
+      always at the same offset (0). It can be written with a code (usually 0) 
+      to distinguish a solicted frame from an interrupt frame. An RTOS port may
+      opt to ignore this field if it has another way of distinguishing frames.
+-------------------------------------------------------------------------------
+*/
+
+STRUCT_BEGIN
+#ifdef __XTENSA_CALL0_ABI__
+STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
+STRUCT_FIELD (long, 4, XT_SOL_PC,   pc)
+STRUCT_FIELD (long, 4, XT_SOL_PS,   ps)
+STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
+STRUCT_FIELD (long, 4, XT_SOL_A12,  a12)    /* should be on 16-byte alignment */
+STRUCT_FIELD (long, 4, XT_SOL_A13,  a13)
+STRUCT_FIELD (long, 4, XT_SOL_A14,  a14)
+STRUCT_FIELD (long, 4, XT_SOL_A15,  a15)
+#else
+STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
+STRUCT_FIELD (long, 4, XT_SOL_PC,   pc)
+STRUCT_FIELD (long, 4, XT_SOL_PS,   ps)
+STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
+STRUCT_FIELD (long, 4, XT_SOL_A0,   a0)    /* should be on 16-byte alignment */
+STRUCT_FIELD (long, 4, XT_SOL_A1,   a1)
+STRUCT_FIELD (long, 4, XT_SOL_A2,   a2)
+STRUCT_FIELD (long, 4, XT_SOL_A3,   a3)
+#endif
+STRUCT_END(XtSolFrame)
+
+/* Size of solicited stack frame */
+#define XT_SOL_FRMSZ            ALIGNUP(0x10, XtSolFrameSize)
+
+
+/*
+-------------------------------------------------------------------------------
+  CO-PROCESSOR STATE SAVE AREA FOR A THREAD
+
+  The RTOS must provide an area per thread to save the state of co-processors
+  when that thread does not have control. Co-processors are context-switched
+  lazily (on demand) only when a new thread uses a co-processor instruction,
+  otherwise a thread retains ownership of the co-processor even when it loses
+  control of the processor. An Xtensa co-processor exception is triggered when
+  any co-processor instruction is executed by a thread that is not the owner,
+  and the context switch of that co-processor is then peformed by the handler.
+  Ownership represents which thread's state is currently in the co-processor.
+
+  Co-processors may not be used by interrupt or exception handlers. If an 
+  co-processor instruction is executed by an interrupt or exception handler,
+  the co-processor exception handler will trigger a kernel panic and freeze.
+  This restriction is introduced to reduce the overhead of saving and restoring
+  co-processor state (which can be quite large) and in particular remove that
+  overhead from interrupt handlers.
+
+  The co-processor state save area may be in any convenient per-thread location
+  such as in the thread control block or above the thread stack area. It need
+  not be in the interrupt stack frame since interrupts don't use co-processors.
+
+  Along with the save area for each co-processor, two bitmasks with flags per 
+  co-processor (laid out as in the CPENABLE reg) help manage context-switching
+  co-processors as efficiently as possible:
+
+  XT_CPENABLE
+    The contents of a non-running thread's CPENABLE register.
+    It represents the co-processors owned (and whose state is still needed)
+    by the thread. When a thread is preempted, its CPENABLE is saved here.
+    When a thread solicits a context-swtich, its CPENABLE is cleared - the
+    compiler has saved the (caller-saved) co-proc state if it needs to.
+    When a non-running thread loses ownership of a CP, its bit is cleared.
+    When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
+    Avoids co-processor exceptions when no change of ownership is needed.
+
+  XT_CPSTORED
+    A bitmask with the same layout as CPENABLE, a bit per co-processor.
+    Indicates whether the state of each co-processor is saved in the state 
+    save area. When a thread enters the kernel, only the state of co-procs
+    still enabled in CPENABLE is saved. When the co-processor exception 
+    handler assigns ownership of a co-processor to a thread, it restores 
+    the saved state only if this bit is set, and clears this bit.
+
+  XT_CP_CS_ST
+    A bitmask with the same layout as CPENABLE, a bit per co-processor.
+    Indicates whether callee-saved state is saved in the state save area.
+    Callee-saved state is saved by itself on a solicited context switch,
+    and restored when needed by the coprocessor exception handler.
+    Unsolicited switches will cause the entire coprocessor to be saved
+    when necessary.
+
+  XT_CP_ASA
+    Pointer to the aligned save area.  Allows it to be aligned more than
+    the overall save area (which might only be stack-aligned or TCB-aligned).
+    Especially relevant for Xtensa cores configured with a very large data
+    path that requires alignment greater than 16 bytes (ABI stack alignment).
+-------------------------------------------------------------------------------
+*/
+
+#if XCHAL_CP_NUM > 0
+
+/*  Offsets of each coprocessor save area within the 'aligned save area':  */
+#define XT_CP0_SA   0
+#define XT_CP1_SA   ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE)
+#define XT_CP2_SA   ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE)
+#define XT_CP3_SA   ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE)
+#define XT_CP4_SA   ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE)
+#define XT_CP5_SA   ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE)
+#define XT_CP6_SA   ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE)
+#define XT_CP7_SA   ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE)
+#define XT_CP_SA_SIZE   ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE)
+
+/*  Offsets within the overall save area:  */
+#define XT_CPENABLE 0   /* (2 bytes) coprocessors active for this thread */
+#define XT_CPSTORED 2   /* (2 bytes) coprocessors saved for this thread */
+#define XT_CP_CS_ST 4   /* (2 bytes) coprocessor callee-saved regs stored for this thread */
+#define XT_CP_ASA   8   /* (4 bytes) ptr to aligned save area */
+/*  Overall size allows for dynamic alignment:  */
+#define XT_CP_SIZE  (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN)
+#else
+#define XT_CP_SIZE  0
+#endif
+
+
+/*
+-------------------------------------------------------------------------------
+  MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
+
+  Convenient where the frame size requirements are the same for both ABIs.
+    ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
+    ENTRY0,    RET0    are for frameless functions (no locals, no calls).
+
+  where size = size of stack frame in bytes (must be >0 and aligned to 16).
+  For framed functions the frame is created and the return address saved at
+  base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
+  For frameless functions, there is no frame and return address remains in a0.
+  Note: Because CPP macros expand to a single line, macros requiring multi-line 
+  expansions are implemented as assembler macros.
+-------------------------------------------------------------------------------
+*/
+
+#ifdef __ASSEMBLER__
+#ifdef __XTENSA_CALL0_ABI__
+  /* Call0 */
+  #define ENTRY(sz)     entry1  sz
+    .macro  entry1 size=0x10
+    addi    sp, sp, -\size
+    s32i    a0, sp, 0
+    .endm
+  #define ENTRY0      
+  #define RET(sz)       ret1    sz
+    .macro  ret1 size=0x10
+    l32i    a0, sp, 0
+    addi    sp, sp, \size
+    ret
+    .endm
+  #define RET0          ret
+#else
+  /* Windowed */
+  #define ENTRY(sz)     entry   sp, sz
+  #define ENTRY0        entry   sp, 0x10
+  #define RET(sz)       retw
+  #define RET0          retw
+#endif
+#endif
+
+
+#endif /* XTENSA_CONTEXT_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_init.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_init.c
new file mode 100644
index 0000000..da8bf2d
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_init.c
@@ -0,0 +1,66 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * XTENSA INITIALIZATION ROUTINES CODED IN C
+ *
+ * This file contains miscellaneous Xtensa RTOS-generic initialization functions
+ * that are implemented in C.
+ */
+
+
+#ifdef XT_BOARD
+#include    
+#endif
+
+#include    "xtensa_rtos.h"
+
+#ifdef XT_RTOS_TIMER_INT
+
+unsigned _xt_tick_divisor = 0;  /* cached number of cycles per tick */
+
+/*
+Compute and initialize at run-time the tick divisor (the number of 
+processor clock cycles in an RTOS tick, used to set the tick timer).
+Called when the processor clock frequency is not known at compile-time.
+*/
+void _xt_tick_divisor_init(void)
+{
+#ifdef XT_CLOCK_FREQ
+
+    _xt_tick_divisor = (XT_CLOCK_FREQ / XT_TICK_PER_SEC);
+
+#else
+
+    #ifdef XT_BOARD
+    _xt_tick_divisor = xtbsp_clock_freq_hz() / XT_TICK_PER_SEC;
+    #else
+    #error "No way to obtain processor clock frequency"
+    #endif  /* XT_BOARD */
+
+#endif /* XT_CLOCK_FREQ */
+}
+
+#endif /* XT_RTOS_TIMER_INT */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c
new file mode 100644
index 0000000..846aafb
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c
@@ -0,0 +1,133 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Xtensa-specific interrupt and exception functions for RTOS ports.
+ * Also see xtensa_intr_asm.S.
+ */
+
+#include 
+
+#include 
+
+#include "xtensa_api.h"
+
+
+#if XCHAL_HAVE_EXCEPTIONS
+
+/* Handler table is in xtensa_intr_asm.S */
+
+extern xt_exc_handler _xt_exception_table[XCHAL_EXCCAUSE_NUM];
+
+
+/*
+  Default handler for unhandled exceptions.
+*/
+void xt_unhandled_exception(XtExcFrame *frame)
+{
+    exit(-1);
+}
+
+
+/*
+  This function registers a handler for the specified exception.
+  The function returns the address of the previous handler.
+  On error, it returns 0.
+*/
+xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f)
+{
+    xt_exc_handler old;
+
+    if( n < 0 || n >= XCHAL_EXCCAUSE_NUM )
+        return 0;       /* invalid exception number */
+
+    old = _xt_exception_table[n];
+
+    if (f) {
+        _xt_exception_table[n] = f;
+    }
+    else {
+        _xt_exception_table[n] = &xt_unhandled_exception;
+    }
+
+    return ((old == &xt_unhandled_exception) ? 0 : old);
+}
+
+#endif
+
+#if XCHAL_HAVE_INTERRUPTS
+
+/* Handler table is in xtensa_intr_asm.S */
+
+typedef struct xt_handler_table_entry {
+    void * handler;
+    void * arg;
+} xt_handler_table_entry;
+
+extern xt_handler_table_entry _xt_interrupt_table[XCHAL_NUM_INTERRUPTS];
+
+
+/*
+  Default handler for unhandled interrupts.
+*/
+void xt_unhandled_interrupt(void * arg)
+{
+    exit(-1);
+}
+
+
+/*
+  This function registers a handler for the specified interrupt. The "arg"
+  parameter specifies the argument to be passed to the handler when it is
+  invoked. The function returns the address of the previous handler.
+  On error, it returns 0.
+*/
+xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg)
+{
+    xt_handler_table_entry * entry;
+    xt_handler               old;
+
+    if( n < 0 || n >= XCHAL_NUM_INTERRUPTS )
+        return 0;       /* invalid interrupt number */
+    if( Xthal_intlevel[n] > XCHAL_EXCM_LEVEL )
+        return 0;       /* priority level too high to safely handle in C */
+
+    entry = _xt_interrupt_table + n;
+    old   = entry->handler;
+
+    if (f) {
+        entry->handler = f;
+        entry->arg     = arg;
+    }
+    else {
+        entry->handler = &xt_unhandled_interrupt;
+        entry->arg     = (void*)n;
+    }
+
+    return ((old == &xt_unhandled_interrupt) ? 0 : old);
+}
+
+
+#endif /* XCHAL_HAVE_INTERRUPTS */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S
new file mode 100644
index 0000000..45060f1
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S
@@ -0,0 +1,180 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Xtensa interrupt handling data and assembly routines.
+ * Also see xtensa_intr.c and xtensa_vectors.S.
+ */
+
+#include 
+#include 
+
+#include "xtensa_context.h"
+
+#if XCHAL_HAVE_INTERRUPTS
+
+/*
+-------------------------------------------------------------------------------
+  INTENABLE virtualization information.
+-------------------------------------------------------------------------------
+*/
+
+    .data
+    .global _xt_intdata
+    .align  8
+_xt_intdata:
+    .global _xt_intenable
+    .type   _xt_intenable,@object
+    .size   _xt_intenable,4
+    .global _xt_vpri_mask
+    .type   _xt_vpri_mask,@object
+    .size   _xt_vpri_mask,4
+
+_xt_intenable:     .word   0             /* Virtual INTENABLE     */
+_xt_vpri_mask:     .word   0xFFFFFFFF    /* Virtual priority mask */
+
+
+/*
+-------------------------------------------------------------------------------
+  Table of C-callable interrupt handlers for each interrupt. Note that not all
+  slots can be filled, because interrupts at level > EXCM_LEVEL will not be
+  dispatched to a C handler by default.
+-------------------------------------------------------------------------------
+*/
+
+    .data
+    .global _xt_interrupt_table
+    .align  8
+
+_xt_interrupt_table:
+
+    .set    i, 0
+    .rept   XCHAL_NUM_INTERRUPTS
+    .word   xt_unhandled_interrupt      /* handler address               */
+    .word   i                           /* handler arg (default: intnum) */
+    .set    i, i+1
+    .endr
+
+#endif /* XCHAL_HAVE_INTERRUPTS */
+
+
+#if XCHAL_HAVE_EXCEPTIONS
+
+/*
+-------------------------------------------------------------------------------
+  Table of C-callable exception handlers for each exception. Note that not all
+  slots will be active, because some exceptions (e.g. coprocessor exceptions)
+  are always handled by the OS and cannot be hooked by user handlers.
+-------------------------------------------------------------------------------
+*/
+
+    .data
+    .global _xt_exception_table
+    .align  4
+
+_xt_exception_table:
+    .rept   XCHAL_EXCCAUSE_NUM
+    .word   xt_unhandled_exception    /* handler address */
+    .endr
+
+#endif
+
+
+/*
+-------------------------------------------------------------------------------
+  unsigned int xt_ints_on ( unsigned int mask )
+
+  Enables a set of interrupts. Does not simply set INTENABLE directly, but
+  computes it as a function of the current virtual priority.
+  Can be called from interrupt handlers.
+-------------------------------------------------------------------------------
+*/
+
+    .text
+    .align  4
+    .global xt_ints_on
+    .type   xt_ints_on,@function
+
+xt_ints_on:
+
+    ENTRY0
+#if XCHAL_HAVE_INTERRUPTS
+    movi    a3, 0
+    movi    a4, _xt_intdata
+    xsr     a3, INTENABLE        /* Disables all interrupts   */
+    rsync
+    l32i    a3, a4, 0            /* a3 = _xt_intenable        */
+    l32i    a6, a4, 4            /* a6 = _xt_vpri_mask        */
+    or      a5, a3, a2           /* a5 = _xt_intenable | mask */
+    s32i    a5, a4, 0            /* _xt_intenable |= mask     */
+    and     a5, a5, a6           /* a5 = _xt_intenable & _xt_vpri_mask */
+    wsr     a5, INTENABLE        /* Reenable interrupts       */
+    mov     a2, a3               /* Previous mask             */
+#else
+    movi    a2, 0                /* Return zero */
+#endif
+    RET0
+
+    .size   xt_ints_on, . - xt_ints_on
+
+
+/*
+-------------------------------------------------------------------------------
+  unsigned int xt_ints_off ( unsigned int mask )
+
+  Disables a set of interrupts. Does not simply set INTENABLE directly,
+  but computes it as a function of the current virtual priority.
+  Can be called from interrupt handlers.
+-------------------------------------------------------------------------------
+*/
+
+    .text
+    .align  4
+    .global xt_ints_off
+    .type   xt_ints_off,@function
+
+xt_ints_off:
+
+    ENTRY0
+#if XCHAL_HAVE_INTERRUPTS
+    movi    a3, 0
+    movi    a4, _xt_intdata
+    xsr     a3, INTENABLE        /* Disables all interrupts    */
+    rsync
+    l32i    a3, a4, 0            /* a3 = _xt_intenable         */
+    l32i    a6, a4, 4            /* a6 = _xt_vpri_mask         */
+    or      a5, a3, a2           /* a5 = _xt_intenable | mask  */
+    xor     a5, a5, a2           /* a5 = _xt_intenable & ~mask */
+    s32i    a5, a4, 0            /* _xt_intenable &= ~mask     */
+    and     a5, a5, a6           /* a5 = _xt_intenable & _xt_vpri_mask */
+    wsr     a5, INTENABLE        /* Reenable interrupts        */
+    mov     a2, a3               /* Previous mask              */
+#else
+    movi    a2, 0                /* return zero */
+#endif
+    RET0
+
+    .size   xt_ints_off, . - xt_ints_off
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c
new file mode 100644
index 0000000..050b495
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c
@@ -0,0 +1,71 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * xtensa_overlay_os_hook.c -- Overlay manager OS hooks for FreeRTOS.
+ */
+
+#include "FreeRTOS.h"
+#include "semphr.h"
+
+#if configUSE_MUTEX
+
+/* Mutex object that controls access to the overlay. Currently only one
+ * overlay region is supported so one mutex suffices.
+ */
+static SemaphoreHandle_t xt_overlay_mutex;
+
+
+/* This function should be overridden to provide OS specific init such
+ * as the creation of a mutex lock that can be used for overlay locking.
+ * Typically this mutex would be set up with priority inheritance. See
+ * overlay manager documentation for more details.
+ */
+void xt_overlay_init_os(void)
+{
+    /* Create the mutex for overlay access. Priority inheritance is
+     * required.
+     */
+    xt_overlay_mutex = xSemaphoreCreateMutex();
+}
+
+
+/* This function locks access to shared overlay resources, typically
+ * by acquiring a mutex.
+ */
+void xt_overlay_lock(void)
+{
+    xSemaphoreTake(xt_overlay_mutex, 0);
+}
+
+
+/* This function releases access to shared overlay resources, typically
+ * by unlocking a mutex.
+ */
+void xt_overlay_unlock(void)
+{
+    xSemaphoreGive(xt_overlay_mutex);
+}
+
+#endif
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h
new file mode 100644
index 0000000..207a76c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h
@@ -0,0 +1,234 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES
+ *                       (FreeRTOS Port)
+ *
+ * This header is the primary glue between generic Xtensa RTOS support
+ * sources and a specific RTOS port for Xtensa.  It contains definitions
+ * and macros for use primarily by Xtensa assembly coded source files.
+ *
+ * Macros in this header map callouts from generic Xtensa files to specific
+ * RTOS functions. It may also be included in C source files.
+ *
+ * Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa 
+ * architecture, using the Xtensa hardware abstraction layer (HAL) to deal 
+ * with configuration specifics.
+ * 
+ * Should be included by all Xtensa generic and RTOS port-specific sources.
+ */
+
+#ifndef XTENSA_RTOS_H
+#define XTENSA_RTOS_H
+
+#ifdef __ASSEMBLER__
+#include    
+#else
+#include    
+#endif
+
+#include    
+#include    
+#include    
+
+/*
+Include any RTOS specific definitions that are needed by this header.
+*/
+#include    
+
+/*
+Convert FreeRTOSConfig definitions to XTENSA definitions.
+However these can still be overridden from the command line.
+*/
+
+#ifndef XT_SIMULATOR
+  #if configXT_SIMULATOR
+    #define XT_SIMULATOR             1  /* Simulator mode */
+  #endif
+#endif
+
+#ifndef XT_BOARD
+  #if configXT_BOARD
+    #define XT_BOARD                 1  /* Board mode */
+  #endif
+#endif
+
+#ifndef XT_TIMER_INDEX
+  #if defined configXT_TIMER_INDEX
+    #define XT_TIMER_INDEX           configXT_TIMER_INDEX  /* Index of hardware timer to be used */
+  #endif
+#endif
+
+#ifndef XT_INTEXC_HOOKS
+  #if configXT_INTEXC_HOOKS
+    #define XT_INTEXC_HOOKS          1  /* Enables exception hooks */
+  #endif
+#endif
+
+#if (!XT_SIMULATOR) && (!XT_BOARD)
+  #error Either XT_SIMULATOR or XT_BOARD must be defined.
+#endif
+
+
+/*
+Name of RTOS (for messages).
+*/
+#define XT_RTOS_NAME    FreeRTOS
+
+/*
+Check some Xtensa configuration requirements and report error if not met.
+Error messages can be customize to the RTOS port.
+*/
+
+#if !XCHAL_HAVE_XEA2
+#error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)."
+#endif
+
+
+/*******************************************************************************
+
+RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.
+
+Define callout macros used in generic Xtensa code to interact with the RTOS.
+The macros are simply the function names for use in calls from assembler code.
+Some of these functions may call back to generic functions in xtensa_context.h .
+
+*******************************************************************************/
+
+/*
+Inform RTOS of entry into an interrupt handler that will affect it. 
+Allows RTOS to manage switch to any system stack and count nesting level.
+Called after minimal context has been saved, with interrupts disabled.
+RTOS port can call0 _xt_context_save to save the rest of the context.
+May only be called from assembly code by the 'call0' instruction.
+*/
+// void XT_RTOS_INT_ENTER(void)
+#define XT_RTOS_INT_ENTER   _frxt_int_enter
+
+/*
+Inform RTOS of completion of an interrupt handler, and give control to
+RTOS to perform thread/task scheduling, switch back from any system stack
+and restore the context, and return to the exit dispatcher saved in the
+stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore
+to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,
+leaving only a minimal part of the context to be restored by the exit
+dispatcher. This function does not return to the place it was called from.
+May only be called from assembly code by the 'call0' instruction.
+*/
+// void XT_RTOS_INT_EXIT(void)
+#define XT_RTOS_INT_EXIT    _frxt_int_exit
+
+/*
+Inform RTOS of the occurrence of a tick timer interrupt.
+If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
+May be coded in or called from C or assembly, per ABI conventions.
+RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro).
+*/
+// void XT_RTOS_TIMER_INT(void)
+#define XT_RTOS_TIMER_INT   _frxt_timer_int
+#define XT_TICK_PER_SEC     configTICK_RATE_HZ
+
+/*
+Return in a15 the base address of the co-processor state save area for the 
+thread that triggered a co-processor exception, or 0 if no thread was running.
+The state save area is structured as defined in xtensa_context.h and has size 
+XT_CP_SIZE. Co-processor instructions should only be used in thread code, never
+in interrupt handlers or the RTOS kernel. May only be called from assembly code
+and by the 'call0' instruction. A result of 0 indicates an unrecoverable error. 
+The implementation may use only a2-4, a15 (all other regs must be preserved).
+*/
+// void* XT_RTOS_CP_STATE(void)
+#define XT_RTOS_CP_STATE    _frxt_task_coproc_state
+
+
+/*******************************************************************************
+
+HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
+
+This Xtensa RTOS port provides hooks for dynamically installing exception
+and interrupt handlers to facilitate automated testing where each test
+case can install its own handler for user exceptions and each interrupt
+priority (level). This consists of an array of function pointers indexed
+by interrupt priority, with index 0 being the user exception handler hook.
+Each entry in the array is initially 0, and may be replaced by a function 
+pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.
+
+The handler for low and medium priority obeys ABI conventions so may be coded
+in C. For the exception handler, the cause is the contents of the EXCCAUSE
+reg, and the result is -1 if handled, else the cause (still needs handling).
+For interrupt handlers, the cause is a mask of pending enabled interrupts at
+that level, and the result is the same mask with the bits for the handled
+interrupts cleared (those not cleared still need handling). This allows a test
+case to either pre-handle or override the default handling for the exception
+or interrupt level (see xtensa_vectors.S).
+
+High priority handlers (including NMI) must be coded in assembly, are always
+called by 'call0' regardless of ABI, must preserve all registers except a0,
+and must not use or modify the interrupted stack. The hook argument 'cause'
+is not passed and the result is ignored, so as not to burden the caller with
+saving and restoring a2 (it assumes only one interrupt per level - see the
+discussion in high priority interrupts in xtensa_vectors.S). The handler
+therefore should be coded to prototype 'void h(void)' even though it plugs
+into an array of handlers of prototype 'unsigned h(unsigned)'.
+
+To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'.
+
+*******************************************************************************/
+
+#define XT_INTEXC_HOOK_NUM  (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI)
+
+#ifndef __ASSEMBLER__
+typedef unsigned (*XT_INTEXC_HOOK)(unsigned cause);
+extern  volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM];
+#endif
+
+
+/*******************************************************************************
+
+CONVENIENCE INCLUSIONS.
+
+Ensures RTOS specific files need only include this one Xtensa-generic header.
+These headers are included last so they can use the RTOS definitions above.
+
+*******************************************************************************/
+
+#include    "xtensa_context.h"
+
+#ifdef XT_RTOS_TIMER_INT
+#include    "xtensa_timer.h"
+#endif
+
+
+/*******************************************************************************
+
+Xtensa Port Version.
+
+*******************************************************************************/
+
+#define XTENSA_PORT_VERSION             1.7
+#define XTENSA_PORT_VERSION_STRING      "1.7"
+
+#endif /* XTENSA_RTOS_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h
new file mode 100644
index 0000000..7d7acaa
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h
@@ -0,0 +1,160 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY
+ *
+ * This header contains definitions and macros for use primarily by Xtensa
+ * RTOS assembly coded source files. It includes and uses the Xtensa hardware
+ * abstraction layer (HAL) to deal with config specifics. It may also be
+ * included in C source files.
+ *
+ * Edit this file to modify timer selection and to specify clock frequency and
+ * tick duration to match timer interrupt to the real-time tick duration.
+ *
+ * If the RTOS has no timer interrupt, then there is no tick timer and the
+ * clock frequency is irrelevant, so all of these macros are left undefined
+ * and the Xtensa core configuration need not have a timer.
+ */
+
+#ifndef XTENSA_TIMER_H
+#define XTENSA_TIMER_H
+
+#ifdef __ASSEMBLER__
+#include    
+#endif
+
+#include    
+#include    
+
+#include    "xtensa_rtos.h"     /* in case this wasn't included directly */
+
+#include    
+
+/*
+Select timer to use for periodic tick, and determine its interrupt number 
+and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
+in which case its validity is checked (it must exist in this core and must 
+not be on a high priority interrupt - an error will be reported in invalid).
+Otherwise select the first low or medium priority interrupt timer available.
+*/
+#if XCHAL_NUM_TIMERS == 0
+
+  #error "This Xtensa configuration is unsupported, it has no timers."
+
+#else
+
+#ifndef XT_TIMER_INDEX
+  #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+    #if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL
+      #undef  XT_TIMER_INDEX
+      #define XT_TIMER_INDEX    3
+    #endif
+  #endif
+  #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+    #if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
+      #undef  XT_TIMER_INDEX
+      #define XT_TIMER_INDEX    2
+    #endif
+  #endif
+  #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+    #if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
+      #undef  XT_TIMER_INDEX
+      #define XT_TIMER_INDEX    1
+    #endif
+  #endif
+  #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+    #if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
+      #undef  XT_TIMER_INDEX
+      #define XT_TIMER_INDEX    0
+    #endif
+  #endif
+#endif
+#ifndef XT_TIMER_INDEX
+  #error "There is no suitable timer in this Xtensa configuration."
+#endif
+
+#define XT_CCOMPARE             (CCOMPARE + XT_TIMER_INDEX)
+#define XT_TIMER_INTNUM         XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX)
+#define XT_TIMER_INTPRI         XCHAL_INT_LEVEL(XT_TIMER_INTNUM)
+#define XT_TIMER_INTEN          (1 << XT_TIMER_INTNUM)
+
+#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
+  #error "The timer selected by XT_TIMER_INDEX does not exist in this core."
+#elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL
+  #error "The timer interrupt cannot be high priority (use medium or low)."
+#endif
+
+#endif /* XCHAL_NUM_TIMERS */
+
+/*
+Set processor clock frequency, used to determine clock divisor for timer tick.
+User should BE SURE TO ADJUST THIS for the Xtensa platform being used.
+If using a supported board via the board-independent API defined in xtbsp.h,
+this may be left undefined and frequency and tick divisor will be computed 
+and cached during run-time initialization.
+
+NOTE ON SIMULATOR:
+Under the Xtensa instruction set simulator, the frequency can only be estimated 
+because it depends on the speed of the host and the version of the simulator.
+Also because it runs much slower than hardware, it is not possible to achieve
+real-time performance for most applications under the simulator. A frequency
+too low does not allow enough time between timer interrupts, starving threads.
+To obtain a more convenient but non-real-time tick duration on the simulator, 
+compile with xt-xcc option "-DXT_SIMULATOR".
+Adjust this frequency to taste (it's not real-time anyway!).
+*/
+#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ)
+#define XT_CLOCK_FREQ       configCPU_CLOCK_HZ
+#endif
+
+#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD)
+  #error "XT_CLOCK_FREQ must be defined for the target platform."
+#endif
+
+/*
+Default number of timer "ticks" per second (default 100 for 10ms tick).
+RTOS may define this in its own way (if applicable) in xtensa_rtos.h.
+User may redefine this to an optimal value for the application, either by
+editing this here or in xtensa_rtos.h, or compiling with xt-xcc option
+"-DXT_TICK_PER_SEC=" where  is a suitable number.
+*/
+#ifndef XT_TICK_PER_SEC
+#define XT_TICK_PER_SEC    configTICK_RATE_HZ        /* 10 ms tick = 100 ticks per second */
+#endif
+
+/*
+Derivation of clock divisor for timer tick and interrupt (one per tick).
+*/
+#ifdef XT_CLOCK_FREQ
+#define XT_TICK_DIVISOR     (XT_CLOCK_FREQ / XT_TICK_PER_SEC)
+#endif
+
+#ifndef __ASSEMBLER__
+extern unsigned _xt_tick_divisor;
+extern void     _xt_tick_divisor_init(void);
+#endif
+
+#endif  /* XTENSA_TIMER_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S
new file mode 100644
index 0000000..224ac87
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S
@@ -0,0 +1,1905 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+        XTENSA VECTORS AND LOW LEVEL HANDLERS FOR AN RTOS
+
+  Xtensa low level exception and interrupt vectors and handlers for an RTOS.
+
+  Interrupt handlers and user exception handlers support interaction with
+  the RTOS by calling XT_RTOS_INT_ENTER and XT_RTOS_INT_EXIT before and
+  after user's specific interrupt handlers. These macros are defined in
+  xtensa_.h to call suitable functions in a specific RTOS.
+
+  Users can install application-specific interrupt handlers for low and
+  medium level interrupts, by calling xt_set_interrupt_handler(). These
+  handlers can be written in C, and must obey C calling convention. The
+  handler table is indexed by the interrupt number. Each handler may be
+  provided with an argument. 
+
+  Note that the system timer interrupt is handled specially, and is
+  dispatched to the RTOS-specific handler. This timer cannot be hooked
+  by application code.
+
+  Optional hooks are also provided to install a handler per level at 
+  run-time, made available by compiling this source file with 
+  '-DXT_INTEXC_HOOKS' (useful for automated testing).
+
+!!  This file is a template that usually needs to be modified to handle       !!
+!!  application specific interrupts. Search USER_EDIT for helpful comments    !!
+!!  on where to insert handlers and how to write them.                        !!
+
+  Users can also install application-specific exception handlers in the
+  same way, by calling xt_set_exception_handler(). One handler slot is
+  provided for each exception type. Note that some exceptions are handled
+  by the porting layer itself, and cannot be taken over by application
+  code in this manner. These are the alloca, syscall, and coprocessor
+  exceptions.
+
+  The exception handlers can be written in C, and must follow C calling
+  convention. Each handler is passed a pointer to an exception frame as
+  its single argument. The exception frame is created on the stack, and
+  holds the saved context of the thread that took the exception. If the
+  handler returns, the context will be restored and the instruction that
+  caused the exception will be retried. If the handler makes any changes
+  to the saved state in the exception frame, the changes will be applied
+  when restoring the context.
+
+  Because Xtensa is a configurable architecture, this port supports all user
+  generated configurations (except restrictions stated in the release notes).
+  This is accomplished by conditional compilation using macros and functions
+  defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
+  Only the relevant parts of this file will be included in your RTOS build.
+  For example, this file provides interrupt vector templates for all types and
+  all priority levels, but only the ones in your configuration are built.
+
+  NOTES on the use of 'call0' for long jumps instead of 'j':
+   1. This file should be assembled with the -mlongcalls option to xt-xcc.
+   2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to
+      a sequence 'l32r a0, dest' 'callx0 a0' which works regardless of the
+      distance from the call to the destination. The linker then relaxes
+      it back to 'call0 dest' if it determines that dest is within range.
+      This allows more flexibility in locating code without the performance
+      overhead of the 'l32r' literal data load in cases where the destination
+      is in range of 'call0'. There is an additional benefit in that 'call0'
+      has a longer range than 'j' due to the target being word-aligned, so 
+      the 'l32r' sequence is less likely needed.
+   3. The use of 'call0' with -mlongcalls requires that register a0 not be 
+      live at the time of the call, which is always the case for a function 
+      call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'.
+   4. This use of 'call0' is independent of the C function call ABI.
+
+ */
+
+#include "xtensa_rtos.h"
+
+
+/* Enable stack backtrace across exception/interrupt - see below */
+#define XT_DEBUG_BACKTRACE    1
+
+
+/*
+--------------------------------------------------------------------------------
+  Defines used to access _xtos_interrupt_table.
+--------------------------------------------------------------------------------
+*/
+#define XIE_HANDLER     0
+#define XIE_ARG         4
+#define XIE_SIZE        8
+
+/*
+--------------------------------------------------------------------------------
+  Macro extract_msb - return the input with only the highest bit set.
+
+  Input  : "ain"  - Input value, clobbered.
+  Output : "aout" - Output value, has only one bit set, MSB of "ain".
+  The two arguments must be different AR registers.
+--------------------------------------------------------------------------------
+*/
+
+    .macro  extract_msb     aout ain
+1:
+    addi    \aout, \ain, -1         /* aout = ain - 1        */
+    and     \ain, \ain, \aout       /* ain  = ain & aout     */
+    bnez    \ain, 1b                /* repeat until ain == 0 */
+    addi    \aout, \aout, 1         /* return aout + 1       */
+    .endm
+
+/*
+--------------------------------------------------------------------------------
+  Macro dispatch_c_isr - dispatch interrupts to user ISRs.
+  This will dispatch to user handlers (if any) that are registered in the
+  XTOS dispatch table (_xtos_interrupt_table). These handlers would have
+  been registered by calling _xtos_set_interrupt_handler(). There is one
+  exception - the timer interrupt used by the OS will not be dispatched
+  to a user handler - this must be handled by the caller of this macro.
+
+  Level triggered and software interrupts are automatically deasserted by
+  this code.
+
+  ASSUMPTIONS:
+    -- PS.INTLEVEL is set to "level" at entry
+    -- PS.EXCM = 0, C calling enabled
+
+  NOTE: For CALL0 ABI, a12-a15 have not yet been saved.
+
+  NOTE: This macro will use registers a0 and a2-a6. The arguments are:
+    level -- interrupt level
+    mask  -- interrupt bitmask for this level
+--------------------------------------------------------------------------------
+*/
+
+    .macro  dispatch_c_isr    level  mask
+
+    /* Get mask of pending, enabled interrupts at this level into a2. */
+
+.L_xt_user_int_&level&:
+    rsr     a2, INTENABLE
+    rsr     a3, INTERRUPT
+    movi    a4, \mask
+    and     a2, a2, a3
+    and     a2, a2, a4
+    beqz    a2, 9f                          /* nothing to do */
+
+    /* This bit of code provides a nice debug backtrace in the debugger.
+       It does take a few more instructions, so undef XT_DEBUG_BACKTRACE
+       if you want to save the cycles.
+    */
+    #if XT_DEBUG_BACKTRACE
+    #ifndef __XTENSA_CALL0_ABI__
+    rsr     a0, EPC_1 + \level - 1          /* return address */
+    movi    a4, 0xC0000000                  /* constant with top 2 bits set (call size) */
+    or      a0, a0, a4                      /* set top 2 bits */
+    addx2   a0, a4, a0                      /* clear top bit -- simulating call4 size   */
+    #endif
+    #endif
+
+    #ifdef XT_INTEXC_HOOKS
+    /* Call interrupt hook if present to (pre)handle interrupts. */
+    movi    a4, _xt_intexc_hooks
+    l32i    a4, a4, \level << 2
+    beqz    a4, 2f
+    #ifdef __XTENSA_CALL0_ABI__
+    callx0  a4
+    beqz    a2, 9f
+    #else
+    mov     a6, a2
+    callx4  a4
+    beqz    a6, 9f
+    mov     a2, a6
+    #endif
+2:
+    #endif
+
+    /* Now look up in the dispatch table and call user ISR if any. */
+    /* If multiple bits are set then MSB has highest priority.     */
+
+    extract_msb  a4, a2                     /* a4 = MSB of a2, a2 trashed */
+
+    #ifdef XT_USE_SWPRI
+    /* Enable all interrupts at this level that are numerically higher
+       than the one we just selected, since they are treated as higher
+       priority.
+    */
+    movi    a3, \mask                       /* a3 = all interrupts at this level */
+    add     a2, a4, a4                      /* a2 = a4 << 1 */
+    addi    a2, a2, -1                      /* a2 = mask of 1's <= a4 bit */
+    and     a2, a2, a3                      /* a2 = mask of all bits <= a4 at this level */
+    movi    a3, _xt_intdata
+    l32i    a6, a3, 4                       /* a6 = _xt_vpri_mask */
+    neg     a2, a2
+    addi    a2, a2, -1                      /* a2 = mask to apply */
+    and     a5, a6, a2                      /* mask off all bits <= a4 bit */
+    s32i    a5, a3, 4                       /* update _xt_vpri_mask */
+    rsr     a3, INTENABLE
+    and     a3, a3, a2                      /* mask off all bits <= a4 bit */
+    wsr     a3, INTENABLE
+    rsil    a3, \level - 1                  /* lower interrupt level by 1 */
+    #endif
+
+    movi    a3, XT_TIMER_INTEN              /* a3 = timer interrupt bit */
+    wsr     a4, INTCLEAR                    /* clear sw or edge-triggered interrupt */
+    beq     a3, a4, 7f                      /* if timer interrupt then skip table */
+
+    find_ms_setbit a3, a4, a3, 0            /* a3 = interrupt number */
+
+    movi    a4, _xt_interrupt_table
+    addx8   a3, a3, a4                      /* a3 = address of interrupt table entry */
+    l32i    a4, a3, XIE_HANDLER             /* a4 = handler address */
+    #ifdef __XTENSA_CALL0_ABI__
+    mov     a12, a6                         /* save in callee-saved reg */
+    l32i    a2, a3, XIE_ARG                 /* a2 = handler arg */
+    callx0  a4                              /* call handler */
+    mov     a2, a12
+    #else
+    mov     a2, a6                          /* save in windowed reg */
+    l32i    a6, a3, XIE_ARG                 /* a6 = handler arg */
+    callx4  a4                              /* call handler */
+    #endif
+
+    #ifdef XT_USE_SWPRI
+    j       8f
+    #else
+    j       .L_xt_user_int_&level&          /* check for more interrupts */
+    #endif
+
+7:
+
+    .ifeq XT_TIMER_INTPRI - \level
+.L_xt_user_int_timer_&level&:
+    /*
+    Interrupt handler for the RTOS tick timer if at this level.
+    We'll be reading the interrupt state again after this call
+    so no need to preserve any registers except a6 (vpri_mask).
+    */
+
+    #ifdef __XTENSA_CALL0_ABI__
+    mov     a12, a6
+    call0   XT_RTOS_TIMER_INT
+    mov     a2, a12
+    #else
+    mov     a2, a6
+    call4   XT_RTOS_TIMER_INT
+    #endif
+    .endif
+
+    #ifdef XT_USE_SWPRI
+    j       8f
+    #else
+    j       .L_xt_user_int_&level&          /* check for more interrupts */
+    #endif
+
+    #ifdef XT_USE_SWPRI
+8:
+    /* Restore old value of _xt_vpri_mask from a2. Also update INTENABLE from
+       virtual _xt_intenable which _could_ have changed during interrupt
+       processing. */
+
+    movi    a3, _xt_intdata
+    l32i    a4, a3, 0                       /* a4 = _xt_intenable    */
+    s32i    a2, a3, 4                       /* update _xt_vpri_mask  */
+    and     a4, a4, a2                      /* a4 = masked intenable */
+    wsr     a4, INTENABLE                   /* update INTENABLE      */
+    #endif
+
+9:
+    /* done */
+
+    .endm
+
+
+/*
+--------------------------------------------------------------------------------
+  Panic handler.
+  Should be reached by call0 (preferable) or jump only. If call0, a0 says where 
+  from. If on simulator, display panic message and abort, else loop indefinitely.
+--------------------------------------------------------------------------------
+*/
+
+    .text
+    .global     _xt_panic
+    .type       _xt_panic,@function
+    .align      4
+
+_xt_panic:
+    #ifdef XT_SIMULATOR
+    addi    a4, a0, -3                      /* point to call0 */
+    movi    a3, _xt_panic_message
+    movi    a2, SYS_log_msg
+    simcall
+    movi    a2, SYS_gdb_abort
+    simcall
+    #else
+    rsil    a2, XCHAL_EXCM_LEVEL            /* disable all low & med ints */
+1:  j       1b                              /* loop infinitely */
+    #endif
+
+    .section    .rodata, "a"
+    .align      4
+
+_xt_panic_message:
+    .string "\n*** _xt_panic() was called from 0x%08x or jumped to. ***\n"
+
+
+/*
+--------------------------------------------------------------------------------
+    Hooks to dynamically install handlers for exceptions and interrupts.
+    Allows automated regression frameworks to install handlers per test.
+    Consists of an array of function pointers indexed by interrupt level, 
+    with index 0 containing the entry for user exceptions.
+    Initialized with all 0s, meaning no handler is installed at each level.
+    See comment in xtensa_rtos.h for more details.
+--------------------------------------------------------------------------------
+*/
+
+    #ifdef XT_INTEXC_HOOKS
+    .data
+    .global     _xt_intexc_hooks
+    .type       _xt_intexc_hooks,@object
+    .align      4
+
+_xt_intexc_hooks:
+    .fill       XT_INTEXC_HOOK_NUM, 4, 0
+    #endif
+
+
+/*
+--------------------------------------------------------------------------------
+  EXCEPTION AND LEVEL 1 INTERRUPT VECTORS AND LOW LEVEL HANDLERS
+  (except window exception vectors).
+
+  Each vector goes at a predetermined location according to the Xtensa
+  hardware configuration, which is ensured by its placement in a special
+  section known to the Xtensa linker support package (LSP). It performs
+  the minimum necessary before jumping to the handler in the .text section.
+
+  The corresponding handler goes in the normal .text section. It sets up
+  the appropriate stack frame, saves a few vector-specific registers and
+  calls XT_RTOS_INT_ENTER to save the rest of the interrupted context
+  and enter the RTOS, then sets up a C environment. It then calls the
+  user's interrupt handler code (which may be coded in C) and finally 
+  calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
+
+  While XT_RTOS_INT_EXIT does not return directly to the interruptee,
+  eventually the RTOS scheduler will want to dispatch the interrupted
+  task or handler. The scheduler will return to the exit point that was
+  saved in the interrupt stack frame at XT_STK_EXIT.
+--------------------------------------------------------------------------------
+*/
+
+
+/*
+--------------------------------------------------------------------------------
+Debug Exception.
+--------------------------------------------------------------------------------
+*/
+
+#if XCHAL_HAVE_DEBUG
+
+    .begin      literal_prefix .DebugExceptionVector
+    .section    .DebugExceptionVector.text, "ax"
+    .global     _DebugExceptionVector
+    .align      4
+
+_DebugExceptionVector:
+
+    #ifdef XT_SIMULATOR
+    /*
+    In the simulator, let the debugger (if any) handle the debug exception,
+    or simply stop the simulation:
+    */
+    wsr     a2, EXCSAVE+XCHAL_DEBUGLEVEL    /* save a2 where sim expects it */
+    movi    a2, SYS_gdb_enter_sktloop
+    simcall                                 /* have ISS handle debug exc. */
+    #elif 0 /* change condition to 1 to use the HAL minimal debug handler */
+    wsr     a3, EXCSAVE+XCHAL_DEBUGLEVEL
+    movi    a3, xthal_debugexc_defhndlr_nw  /* use default debug handler */
+    jx      a3
+    #else
+    wsr     a0, EXCSAVE+XCHAL_DEBUGLEVEL    /* save original a0 somewhere */
+    call0   _xt_panic                       /* does not return */
+    rfi     XCHAL_DEBUGLEVEL                /* make a0 point here not later */
+    #endif
+
+    .end        literal_prefix
+
+#endif
+
+/*
+--------------------------------------------------------------------------------
+Double Exception.
+Double exceptions are not a normal occurrence. They indicate a bug of some kind.
+--------------------------------------------------------------------------------
+*/
+
+#ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
+
+    .begin      literal_prefix .DoubleExceptionVector
+    .section    .DoubleExceptionVector.text, "ax"
+    .global     _DoubleExceptionVector
+    .align      4
+
+_DoubleExceptionVector:
+
+    #if XCHAL_HAVE_DEBUG
+    break   1, 4                            /* unhandled double exception */
+    #endif
+    call0   _xt_panic                       /* does not return */
+    rfde                                    /* make a0 point here not later */
+
+    .end        literal_prefix
+
+#endif /* XCHAL_DOUBLEEXC_VECTOR_VADDR */
+
+/*
+--------------------------------------------------------------------------------
+Kernel Exception (including Level 1 Interrupt from kernel mode).
+--------------------------------------------------------------------------------
+*/
+
+    .begin      literal_prefix .KernelExceptionVector
+    .section    .KernelExceptionVector.text, "ax"
+    .global     _KernelExceptionVector
+    .align      4
+
+_KernelExceptionVector:
+
+    wsr     a0, EXCSAVE_1                   /* preserve a0 */
+    call0   _xt_kernel_exc                  /* kernel exception handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .align      4
+
+_xt_kernel_exc:
+    #if XCHAL_HAVE_DEBUG
+    break   1, 0                            /* unhandled kernel exception */
+    #endif
+    call0   _xt_panic                       /* does not return */
+    rfe                                     /* make a0 point here not there */
+
+
+/*
+--------------------------------------------------------------------------------
+User Exception (including Level 1 Interrupt from user mode).
+--------------------------------------------------------------------------------
+*/
+
+    .begin      literal_prefix .UserExceptionVector
+    .section    .UserExceptionVector.text, "ax"
+    .global     _UserExceptionVector
+    .type       _UserExceptionVector,@function
+    .align      4
+
+_UserExceptionVector:
+
+    wsr     a0, EXCSAVE_1                   /* preserve a0 */
+    call0   _xt_user_exc                    /* user exception handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+/*
+--------------------------------------------------------------------------------
+  Insert some waypoints for jumping beyond the signed 8-bit range of
+  conditional branch instructions, so the conditional branchces to specific
+  exception handlers are not taken in the mainline. Saves some cycles in the
+  mainline.
+--------------------------------------------------------------------------------
+*/
+
+    .text
+
+    #if XCHAL_HAVE_WINDOWED
+    .align      4
+_xt_to_alloca_exc:
+    call0   _xt_alloca_exc                  /* in window vectors section */
+    /* never returns here - call0 is used as a jump (see note at top) */
+    #endif
+
+    .align      4
+_xt_to_syscall_exc:
+    call0   _xt_syscall_exc
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    #if XCHAL_CP_NUM > 0
+    .align      4
+_xt_to_coproc_exc:
+    call0   _xt_coproc_exc
+    /* never returns here - call0 is used as a jump (see note at top) */
+    #endif
+
+
+/*
+--------------------------------------------------------------------------------
+  User exception handler.
+--------------------------------------------------------------------------------
+*/
+
+    .type       _xt_user_exc,@function
+    .align      4
+
+_xt_user_exc:
+
+    /* If level 1 interrupt then jump to the dispatcher */
+    rsr     a0, EXCCAUSE
+    beqi    a0, EXCCAUSE_LEVEL1INTERRUPT, _xt_lowint1
+
+    /* Handle any coprocessor exceptions. Rely on the fact that exception
+       numbers above EXCCAUSE_CP0_DISABLED all relate to the coprocessors.
+    */
+    #if XCHAL_CP_NUM > 0
+    bgeui   a0, EXCCAUSE_CP0_DISABLED, _xt_to_coproc_exc
+    #endif
+
+    /* Handle alloca and syscall exceptions */
+    #if XCHAL_HAVE_WINDOWED
+    beqi    a0, EXCCAUSE_ALLOCA,  _xt_to_alloca_exc
+    #endif
+    beqi    a0, EXCCAUSE_SYSCALL, _xt_to_syscall_exc
+
+    /* Handle all other exceptions. All can have user-defined handlers. */
+    /* NOTE: we'll stay on the user stack for exception handling.       */
+
+    /* Allocate exception frame and save minimal context. */
+    mov     a0, sp
+    addi    sp, sp, -XT_STK_FRMSZ
+    s32i    a0, sp, XT_STK_A1
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -12                     /* for debug backtrace */
+    #endif
+    rsr     a0, PS                          /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_1                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_1                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -16                     /* for debug backtrace */
+    #endif
+    s32i    a12, sp, XT_STK_A12             /* _xt_context_save requires A12- */
+    s32i    a13, sp, XT_STK_A13             /* A13 to have already been saved */
+    call0   _xt_context_save
+
+    /* Save exc cause and vaddr into exception frame */
+    rsr     a0, EXCCAUSE
+    s32i    a0, sp, XT_STK_EXCCAUSE
+    rsr     a0, EXCVADDR
+    s32i    a0, sp, XT_STK_EXCVADDR
+
+    /* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+
+    #ifdef XT_DEBUG_BACKTRACE
+    #ifndef __XTENSA_CALL0_ABI__
+    rsr     a0, EPC_1                       /* return address for debug backtrace */
+    movi    a5, 0xC0000000                  /* constant with top 2 bits set (call size) */
+    rsync                                   /* wait for WSR.PS to complete */
+    or      a0, a0, a5                      /* set top 2 bits */
+    addx2   a0, a5, a0                      /* clear top bit -- thus simulating call4 size */
+    #else
+    rsync                                   /* wait for WSR.PS to complete */
+    #endif
+    #endif
+
+    rsr     a2, EXCCAUSE                    /* recover exc cause */
+
+    #ifdef XT_INTEXC_HOOKS
+    /*
+    Call exception hook to pre-handle exceptions (if installed).
+    Pass EXCCAUSE in a2, and check result in a2 (if -1, skip default handling).
+    */
+    movi    a4, _xt_intexc_hooks
+    l32i    a4, a4, 0                       /* user exception hook index 0 */
+    beqz    a4, 1f
+.Ln_xt_user_exc_call_hook:
+    #ifdef __XTENSA_CALL0_ABI__
+    callx0  a4
+    beqi    a2, -1, .L_xt_user_done
+    #else
+    mov     a6, a2
+    callx4  a4
+    beqi    a6, -1, .L_xt_user_done
+    mov     a2, a6
+    #endif
+1:
+    #endif
+
+    rsr     a2, EXCCAUSE                    /* recover exc cause */
+    movi    a3, _xt_exception_table
+    addx4   a4, a2, a3                      /* a4 = address of exception table entry */
+    l32i    a4, a4, 0                       /* a4 = handler address */
+    #ifdef __XTENSA_CALL0_ABI__
+    mov     a2, sp                          /* a2 = pointer to exc frame */
+    callx0  a4                              /* call handler */
+    #else
+    mov     a6, sp                          /* a6 = pointer to exc frame */
+    callx4  a4                              /* call handler */
+    #endif
+
+.L_xt_user_done:
+
+    /* Restore context and return */
+    call0   _xt_context_restore
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, PS
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_1
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove exception frame */
+    rsync                                   /* ensure PS and EPC written */
+    rfe                                     /* PS.EXCM is cleared */
+
+
+/*
+--------------------------------------------------------------------------------
+  Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+  on entry and used to return to a thread or interrupted interrupt handler.
+--------------------------------------------------------------------------------
+*/
+
+    .global     _xt_user_exit
+    .type       _xt_user_exit,@function
+    .align      4
+_xt_user_exit:
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, PS
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_1
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure PS and EPC written */
+    rfe                                     /* PS.EXCM is cleared */
+
+
+/*
+--------------------------------------------------------------------------------
+Syscall Exception Handler (jumped to from User Exception Handler).
+Syscall 0 is required to spill the register windows (no-op in Call 0 ABI).
+Only syscall 0 is handled here. Other syscalls return -1 to caller in a2.
+--------------------------------------------------------------------------------
+*/
+
+    .text
+    .type       _xt_syscall_exc,@function
+    .align      4
+_xt_syscall_exc:
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /*
+    Save minimal regs for scratch. Syscall 0 does nothing in Call0 ABI.
+    Use a minimal stack frame (16B) to save A2 & A3 for scratch.
+    PS.EXCM could be cleared here, but unlikely to improve worst-case latency.
+    rsr     a0, PS
+    addi    a0, a0, -PS_EXCM_MASK
+    wsr     a0, PS
+    */
+    addi    sp, sp, -16
+    s32i    a2, sp, 8
+    s32i    a3, sp, 12
+    #else   /* Windowed ABI */
+    /*
+    Save necessary context and spill the register windows.
+    PS.EXCM is still set and must remain set until after the spill.
+    Reuse context save function though it saves more than necessary.
+    For this reason, a full interrupt stack frame is allocated.
+    */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a12, sp, XT_STK_A12             /* _xt_context_save requires A12- */
+    s32i    a13, sp, XT_STK_A13             /* A13 to have already been saved */
+    call0   _xt_context_save
+    #endif
+
+    /*
+    Grab the interruptee's PC and skip over the 'syscall' instruction.
+    If it's at the end of a zero-overhead loop and it's not on the last
+    iteration, decrement loop counter and skip to beginning of loop.
+    */
+    rsr     a2, EPC_1                       /* a2 = PC of 'syscall' */
+    addi    a3, a2, 3                       /* ++PC                 */
+    #if XCHAL_HAVE_LOOPS
+    rsr     a0, LEND                        /* if (PC == LEND       */
+    bne     a3, a0, 1f
+    rsr     a0, LCOUNT                      /*     && LCOUNT != 0)  */
+    beqz    a0, 1f                          /* {                    */
+    addi    a0, a0, -1                      /*   --LCOUNT           */
+    rsr     a3, LBEG                        /*   PC = LBEG          */
+    wsr     a0, LCOUNT                      /* }                    */
+    #endif
+1:  wsr     a3, EPC_1                       /* update PC            */
+
+    /* Restore interruptee's context and return from exception. */
+    #ifdef __XTENSA_CALL0_ABI__
+    l32i    a2, sp, 8
+    l32i    a3, sp, 12
+    addi    sp, sp, 16
+    #else
+    call0   _xt_context_restore
+    addi    sp, sp, XT_STK_FRMSZ
+    #endif
+    movi    a0, -1
+    movnez  a2, a0, a2                      /* return -1 if not syscall 0 */
+    rsr     a0, EXCSAVE_1
+    rfe
+
+/*
+--------------------------------------------------------------------------------
+Co-Processor Exception Handler (jumped to from User Exception Handler).
+These exceptions are generated by co-processor instructions, which are only
+allowed in thread code (not in interrupts or kernel code). This restriction is 
+deliberately imposed to reduce the burden of state-save/restore in interrupts.
+--------------------------------------------------------------------------------
+*/
+#if XCHAL_CP_NUM > 0
+
+    .section .rodata, "a"
+
+/* Offset to CP n save area in thread's CP save area. */
+    .global _xt_coproc_sa_offset
+    .type   _xt_coproc_sa_offset,@object
+    .align  16                      /* minimize crossing cache boundaries */
+_xt_coproc_sa_offset:
+    .word   XT_CP0_SA, XT_CP1_SA, XT_CP2_SA, XT_CP3_SA
+    .word   XT_CP4_SA, XT_CP5_SA, XT_CP6_SA, XT_CP7_SA
+
+/* Bitmask for CP n's CPENABLE bit. */
+    .type   _xt_coproc_mask,@object
+    .align  16,,8                   /* try to keep it all in one cache line */
+    .set    i, 0
+_xt_coproc_mask:
+    .rept   XCHAL_CP_MAX
+    .long   (i<<16) | (1<= 2
+
+    .begin      literal_prefix .Level2InterruptVector
+    .section    .Level2InterruptVector.text, "ax"
+    .global     _Level2Vector
+    .type       _Level2Vector,@function
+    .align      4
+_Level2Vector:
+    wsr     a0, EXCSAVE_2                   /* preserve a0 */
+    call0   _xt_medint2                     /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_medint2,@function
+    .align      4
+_xt_medint2:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_2                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_2                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_2                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint2_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(2) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(2) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint2_exit
+    .type       _xt_medint2_exit,@function
+    .align      4
+_xt_medint2_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_2
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_2
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     2
+
+#endif  /* Level 2 */
+
+#if XCHAL_EXCM_LEVEL >= 3
+
+    .begin      literal_prefix .Level3InterruptVector
+    .section    .Level3InterruptVector.text, "ax"
+    .global     _Level3Vector
+    .type       _Level3Vector,@function
+    .align      4
+_Level3Vector:
+    wsr     a0, EXCSAVE_3                   /* preserve a0 */
+    call0   _xt_medint3                     /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_medint3,@function
+    .align      4
+_xt_medint3:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_3                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_3                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_3                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint3_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(3) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(3) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint3_exit
+    .type       _xt_medint3_exit,@function
+    .align      4
+_xt_medint3_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_3
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_3
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     3
+
+#endif  /* Level 3 */
+
+#if XCHAL_EXCM_LEVEL >= 4
+
+    .begin      literal_prefix .Level4InterruptVector
+    .section    .Level4InterruptVector.text, "ax"
+    .global     _Level4Vector
+    .type       _Level4Vector,@function
+    .align      4
+_Level4Vector:
+    wsr     a0, EXCSAVE_4                   /* preserve a0 */
+    call0   _xt_medint4                     /* load interrupt handler */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_medint4,@function
+    .align      4
+_xt_medint4:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_4                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_4                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_4                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint4_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(4) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(4) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint4_exit
+    .type       _xt_medint4_exit,@function
+    .align      4
+_xt_medint4_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_4
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_4
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     4
+
+#endif  /* Level 4 */
+
+#if XCHAL_EXCM_LEVEL >= 5
+
+    .begin      literal_prefix .Level5InterruptVector
+    .section    .Level5InterruptVector.text, "ax"
+    .global     _Level5Vector
+    .type       _Level5Vector,@function
+    .align      4
+_Level5Vector:
+    wsr     a0, EXCSAVE_5                   /* preserve a0 */
+    call0   _xt_medint5                     /* load interrupt handler */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_medint5,@function
+    .align      4
+_xt_medint5:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_5                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_5                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_5                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint5_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(5) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint5_exit
+    .type       _xt_medint5_exit,@function
+    .align      4
+_xt_medint5_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_5
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_5
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     5
+
+#endif  /* Level 5 */
+
+#if XCHAL_EXCM_LEVEL >= 6
+
+    .begin      literal_prefix .Level6InterruptVector
+    .section    .Level6InterruptVector.text, "ax"
+    .global     _Level6Vector
+    .type       _Level6Vector,@function
+    .align      4
+_Level6Vector:
+    wsr     a0, EXCSAVE_6                   /* preserve a0 */
+    call0   _xt_medint6                     /* load interrupt handler */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_medint6,@function
+    .align      4
+_xt_medint6:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_6                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_6                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_6                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint6_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(6) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(6) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint6_exit
+    .type       _xt_medint6_exit,@function
+    .align      4
+_xt_medint6_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_6
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_6
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     6
+
+#endif  /* Level 6 */
+
+
+/*******************************************************************************
+
+HIGH PRIORITY (LEVEL > XCHAL_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS
+
+High priority interrupts are by definition those with priorities greater
+than XCHAL_EXCM_LEVEL. This includes non-maskable (NMI). High priority
+interrupts cannot interact with the RTOS, that is they must save all regs
+they use and not call any RTOS function.
+
+A further restriction imposed by the Xtensa windowed architecture is that
+high priority interrupts must not modify the stack area even logically
+"above" the top of the interrupted stack (they need to provide their
+own stack or static save area).
+
+Cadence Design Systems recommends high priority interrupt handlers be coded in assembly
+and used for purposes requiring very short service times.
+
+Here are templates for high priority (level 2+) interrupt vectors.
+They assume only one interrupt per level to avoid the burden of identifying
+which interrupts at this level are pending and enabled. This allows for 
+minimum latency and avoids having to save/restore a2 in addition to a0.
+If more than one interrupt per high priority level is configured, this burden
+is on the handler which in any case must provide a way to save and restore
+registers it uses without touching the interrupted stack.
+
+Each vector goes at a predetermined location according to the Xtensa
+hardware configuration, which is ensured by its placement in a special
+section known to the Xtensa linker support package (LSP). It performs
+the minimum necessary before jumping to the handler in the .text section.
+
+*******************************************************************************/
+
+/*
+Currently only shells for high priority interrupt handlers are provided
+here. However a template and example can be found in the Cadence Design Systems tools
+documentation: "Microprocessor Programmer's Guide".
+*/
+
+#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2
+
+    .begin      literal_prefix .Level2InterruptVector
+    .section    .Level2InterruptVector.text, "ax"
+    .global     _Level2Vector
+    .type       _Level2Vector,@function
+    .align      4
+_Level2Vector:
+    wsr     a0, EXCSAVE_2                   /* preserve a0 */
+    call0   _xt_highint2                    /* load interrupt handler */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_highint2,@function
+    .align      4
+_xt_highint2:
+
+    #ifdef XT_INTEXC_HOOKS
+    /* Call interrupt hook if present to (pre)handle interrupts. */
+    movi    a0, _xt_intexc_hooks
+    l32i    a0, a0, 2<<2
+    beqz    a0, 1f
+.Ln_xt_highint2_call_hook:
+    callx0  a0                              /* must NOT disturb stack! */
+1:
+    #endif
+
+    /* USER_EDIT:
+    ADD HIGH PRIORITY LEVEL 2 INTERRUPT HANDLER CODE HERE.
+    */
+
+    .align  4
+.L_xt_highint2_exit:
+    rsr     a0, EXCSAVE_2                   /* restore a0 */
+    rfi     2
+
+#endif  /* Level 2 */
+
+#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3
+
+    .begin      literal_prefix .Level3InterruptVector
+    .section    .Level3InterruptVector.text, "ax"
+    .global     _Level3Vector
+    .type       _Level3Vector,@function
+    .align      4
+_Level3Vector:
+    wsr     a0, EXCSAVE_3                   /* preserve a0 */
+    call0   _xt_highint3                    /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_highint3,@function
+    .align      4
+_xt_highint3:
+
+    #ifdef XT_INTEXC_HOOKS
+    /* Call interrupt hook if present to (pre)handle interrupts. */
+    movi    a0, _xt_intexc_hooks
+    l32i    a0, a0, 3<<2
+    beqz    a0, 1f
+.Ln_xt_highint3_call_hook:
+    callx0  a0                              /* must NOT disturb stack! */
+1:
+    #endif
+
+    /* USER_EDIT:
+    ADD HIGH PRIORITY LEVEL 3 INTERRUPT HANDLER CODE HERE.
+    */
+
+    .align  4
+.L_xt_highint3_exit:
+    rsr     a0, EXCSAVE_3                   /* restore a0 */
+    rfi     3
+
+#endif  /* Level 3 */
+
+#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4
+
+    .begin      literal_prefix .Level4InterruptVector
+    .section    .Level4InterruptVector.text, "ax"
+    .global     _Level4Vector
+    .type       _Level4Vector,@function
+    .align      4
+_Level4Vector:
+    wsr     a0, EXCSAVE_4                   /* preserve a0 */
+    call0   _xt_highint4                    /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_highint4,@function
+    .align      4
+_xt_highint4:
+
+    #ifdef XT_INTEXC_HOOKS
+    /* Call interrupt hook if present to (pre)handle interrupts. */
+    movi    a0, _xt_intexc_hooks
+    l32i    a0, a0, 4<<2
+    beqz    a0, 1f
+.Ln_xt_highint4_call_hook:
+    callx0  a0                              /* must NOT disturb stack! */
+1:
+    #endif
+
+    /* USER_EDIT:
+    ADD HIGH PRIORITY LEVEL 4 INTERRUPT HANDLER CODE HERE.
+    */
+
+    .align  4
+.L_xt_highint4_exit:
+    rsr     a0, EXCSAVE_4                   /* restore a0 */
+    rfi     4
+
+#endif  /* Level 4 */
+
+#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5
+
+    .begin      literal_prefix .Level5InterruptVector
+    .section    .Level5InterruptVector.text, "ax"
+    .global     _Level5Vector
+    .type       _Level5Vector,@function
+    .align      4
+_Level5Vector:
+    wsr     a0, EXCSAVE_5                   /* preserve a0 */
+    call0   _xt_highint5                    /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_highint5,@function
+    .align      4
+_xt_highint5:
+
+    #ifdef XT_INTEXC_HOOKS
+    /* Call interrupt hook if present to (pre)handle interrupts. */
+    movi    a0, _xt_intexc_hooks
+    l32i    a0, a0, 5<<2
+    beqz    a0, 1f
+.Ln_xt_highint5_call_hook:
+    callx0  a0                              /* must NOT disturb stack! */
+1:
+    #endif
+
+    /* USER_EDIT:
+    ADD HIGH PRIORITY LEVEL 5 INTERRUPT HANDLER CODE HERE.
+    */
+
+    .align  4
+.L_xt_highint5_exit:
+    rsr     a0, EXCSAVE_5                   /* restore a0 */
+    rfi     5
+
+#endif  /* Level 5 */
+
+#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6
+
+    .begin      literal_prefix .Level6InterruptVector
+    .section    .Level6InterruptVector.text, "ax"
+    .global     _Level6Vector
+    .type       _Level6Vector,@function
+    .align      4
+_Level6Vector:
+    wsr     a0, EXCSAVE_6                   /* preserve a0 */
+    call0   _xt_highint6                    /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_highint6,@function
+    .align      4
+_xt_highint6:
+
+    #ifdef XT_INTEXC_HOOKS
+    /* Call interrupt hook if present to (pre)handle interrupts. */
+    movi    a0, _xt_intexc_hooks
+    l32i    a0, a0, 6<<2
+    beqz    a0, 1f
+.Ln_xt_highint6_call_hook:
+    callx0  a0                              /* must NOT disturb stack! */
+1:
+    #endif
+
+    /* USER_EDIT:
+    ADD HIGH PRIORITY LEVEL 6 INTERRUPT HANDLER CODE HERE.
+    */
+
+    .align  4
+.L_xt_highint6_exit:
+    rsr     a0, EXCSAVE_6                   /* restore a0 */
+    rfi     6
+
+#endif  /* Level 6 */
+
+#if XCHAL_HAVE_NMI
+
+    .begin      literal_prefix .NMIExceptionVector
+    .section    .NMIExceptionVector.text, "ax"
+    .global     _NMIExceptionVector
+    .type       _NMIExceptionVector,@function
+    .align      4
+_NMIExceptionVector:
+    wsr     a0, EXCSAVE + XCHAL_NMILEVEL  _ /* preserve a0 */
+    call0   _xt_nmi                         /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_nmi,@function
+    .align      4
+_xt_nmi:
+
+    #ifdef XT_INTEXC_HOOKS
+    /* Call interrupt hook if present to (pre)handle interrupts. */
+    movi    a0, _xt_intexc_hooks
+    l32i    a0, a0, XCHAL_NMILEVEL<<2
+    beqz    a0, 1f
+.Ln_xt_nmi_call_hook:
+    callx0  a0                              /* must NOT disturb stack! */
+1:
+    #endif
+
+    /* USER_EDIT:
+    ADD HIGH PRIORITY NON-MASKABLE INTERRUPT (NMI) HANDLER CODE HERE.
+    */
+
+    .align  4
+.L_xt_nmi_exit:
+    rsr     a0, EXCSAVE + XCHAL_NMILEVEL    /* restore a0 */
+    rfi     XCHAL_NMILEVEL
+
+#endif  /* NMI */
+
+
+/*******************************************************************************
+
+WINDOW OVERFLOW AND UNDERFLOW EXCEPTION VECTORS AND ALLOCA EXCEPTION HANDLER
+
+Here is the code for each window overflow/underflow exception vector and 
+(interspersed) efficient code for handling the alloca exception cause.
+Window exceptions are handled entirely in the vector area and are very
+tight for performance. The alloca exception is also handled entirely in 
+the window vector area so comes at essentially no cost in code size.
+Users should never need to modify them and Cadence Design Systems recommends 
+they do not.
+
+Window handlers go at predetermined vector locations according to the
+Xtensa hardware configuration, which is ensured by their placement in a
+special section known to the Xtensa linker support package (LSP). Since
+their offsets in that section are always the same, the LSPs do not define
+a section per vector.
+
+These things are coded for XEA2 only (XEA1 is not supported).
+
+Note on Underflow Handlers:
+The underflow handler for returning from call[i+1] to call[i]
+must preserve all the registers from call[i+1]'s window.
+In particular, a0 and a1 must be preserved because the RETW instruction
+will be reexecuted (and may even underflow if an intervening exception
+has flushed call[i]'s registers).
+Registers a2 and up may contain return values.
+
+*******************************************************************************/
+
+#if XCHAL_HAVE_WINDOWED
+
+    .section .WindowVectors.text, "ax"
+
+/*
+--------------------------------------------------------------------------------
+Window Overflow Exception for Call4.
+
+Invoked if a call[i] referenced a register (a4-a15)
+that contains data from ancestor call[j];
+call[j] had done a call4 to call[j+1].
+On entry here:
+    window rotated to call[j] start point;
+        a0-a3 are registers to be saved;
+        a4-a15 must be preserved;
+        a5 is call[j+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0x0
+    .global _WindowOverflow4
+_WindowOverflow4:
+
+    s32e    a0, a5, -16     /* save a0 to call[j+1]'s stack frame */
+    s32e    a1, a5, -12     /* save a1 to call[j+1]'s stack frame */
+    s32e    a2, a5,  -8     /* save a2 to call[j+1]'s stack frame */
+    s32e    a3, a5,  -4     /* save a3 to call[j+1]'s stack frame */
+    rfwo                    /* rotates back to call[i] position */
+
+/*
+--------------------------------------------------------------------------------
+Window Underflow Exception for Call4
+
+Invoked by RETW returning from call[i+1] to call[i]
+where call[i]'s registers must be reloaded (not live in ARs);
+where call[i] had done a call4 to call[i+1].
+On entry here:
+        window rotated to call[i] start point;
+        a0-a3 are undefined, must be reloaded with call[i].reg[0..3];
+        a4-a15 must be preserved (they are call[i+1].reg[0..11]);
+        a5 is call[i+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0x40
+    .global _WindowUnderflow4
+_WindowUnderflow4:
+
+    l32e    a0, a5, -16     /* restore a0 from call[i+1]'s stack frame */
+    l32e    a1, a5, -12     /* restore a1 from call[i+1]'s stack frame */
+    l32e    a2, a5,  -8     /* restore a2 from call[i+1]'s stack frame */
+    l32e    a3, a5,  -4     /* restore a3 from call[i+1]'s stack frame */
+    rfwu
+
+/*
+--------------------------------------------------------------------------------
+Handle alloca exception generated by interruptee executing 'movsp'.
+This uses space between the window vectors, so is essentially "free".
+All interruptee's regs are intact except a0 which is saved in EXCSAVE_1,
+and PS.EXCM has been set by the exception hardware (can't be interrupted).
+The fact the alloca exception was taken means the registers associated with
+the base-save area have been spilled and will be restored by the underflow
+handler, so those 4 registers are available for scratch.
+The code is optimized to avoid unaligned branches and minimize cache misses.
+--------------------------------------------------------------------------------
+*/
+
+    .align  4
+    .global _xt_alloca_exc
+_xt_alloca_exc:
+
+    rsr     a0, WINDOWBASE  /* grab WINDOWBASE before rotw changes it */
+    rotw    -1              /* WINDOWBASE goes to a4, new a0-a3 are scratch */
+    rsr     a2, PS
+    extui   a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS
+    xor     a3, a3, a4      /* bits changed from old to current windowbase */
+    rsr     a4, EXCSAVE_1   /* restore original a0 (now in a4) */
+    slli    a3, a3, XCHAL_PS_OWB_SHIFT
+    xor     a2, a2, a3      /* flip changed bits in old window base */
+    wsr     a2, PS          /* update PS.OWB to new window base */
+    rsync
+
+    _bbci.l a4, 31, _WindowUnderflow4
+    rotw    -1              /* original a0 goes to a8 */
+    _bbci.l a8, 30, _WindowUnderflow8
+    rotw    -1
+    j               _WindowUnderflow12
+
+/*
+--------------------------------------------------------------------------------
+Window Overflow Exception for Call8
+
+Invoked if a call[i] referenced a register (a4-a15)
+that contains data from ancestor call[j];
+call[j] had done a call8 to call[j+1].
+On entry here:
+    window rotated to call[j] start point;
+        a0-a7 are registers to be saved;
+        a8-a15 must be preserved;
+        a9 is call[j+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0x80
+    .global _WindowOverflow8
+_WindowOverflow8:
+
+    s32e    a0, a9, -16     /* save a0 to call[j+1]'s stack frame */
+    l32e    a0, a1, -12     /* a0 <- call[j-1]'s sp
+                               (used to find end of call[j]'s frame) */
+    s32e    a1, a9, -12     /* save a1 to call[j+1]'s stack frame */
+    s32e    a2, a9,  -8     /* save a2 to call[j+1]'s stack frame */
+    s32e    a3, a9,  -4     /* save a3 to call[j+1]'s stack frame */
+    s32e    a4, a0, -32     /* save a4 to call[j]'s stack frame */
+    s32e    a5, a0, -28     /* save a5 to call[j]'s stack frame */
+    s32e    a6, a0, -24     /* save a6 to call[j]'s stack frame */
+    s32e    a7, a0, -20     /* save a7 to call[j]'s stack frame */
+    rfwo                    /* rotates back to call[i] position */
+
+/*
+--------------------------------------------------------------------------------
+Window Underflow Exception for Call8
+
+Invoked by RETW returning from call[i+1] to call[i]
+where call[i]'s registers must be reloaded (not live in ARs);
+where call[i] had done a call8 to call[i+1].
+On entry here:
+        window rotated to call[i] start point;
+        a0-a7 are undefined, must be reloaded with call[i].reg[0..7];
+        a8-a15 must be preserved (they are call[i+1].reg[0..7]);
+        a9 is call[i+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0xC0
+    .global _WindowUnderflow8
+_WindowUnderflow8:
+
+    l32e    a0, a9, -16     /* restore a0 from call[i+1]'s stack frame */
+    l32e    a1, a9, -12     /* restore a1 from call[i+1]'s stack frame */
+    l32e    a2, a9,  -8     /* restore a2 from call[i+1]'s stack frame */
+    l32e    a7, a1, -12     /* a7 <- call[i-1]'s sp
+                               (used to find end of call[i]'s frame) */
+    l32e    a3, a9,  -4     /* restore a3 from call[i+1]'s stack frame */
+    l32e    a4, a7, -32     /* restore a4 from call[i]'s stack frame */
+    l32e    a5, a7, -28     /* restore a5 from call[i]'s stack frame */
+    l32e    a6, a7, -24     /* restore a6 from call[i]'s stack frame */
+    l32e    a7, a7, -20     /* restore a7 from call[i]'s stack frame */
+    rfwu
+
+/*
+--------------------------------------------------------------------------------
+Window Overflow Exception for Call12
+
+Invoked if a call[i] referenced a register (a4-a15)
+that contains data from ancestor call[j];
+call[j] had done a call12 to call[j+1].
+On entry here:
+    window rotated to call[j] start point;
+        a0-a11 are registers to be saved;
+        a12-a15 must be preserved;
+        a13 is call[j+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0x100
+    .global _WindowOverflow12
+_WindowOverflow12:
+
+    s32e    a0,  a13, -16   /* save a0 to call[j+1]'s stack frame */
+    l32e    a0,  a1,  -12   /* a0 <- call[j-1]'s sp
+                               (used to find end of call[j]'s frame) */
+    s32e    a1,  a13, -12   /* save a1 to call[j+1]'s stack frame */
+    s32e    a2,  a13,  -8   /* save a2 to call[j+1]'s stack frame */
+    s32e    a3,  a13,  -4   /* save a3 to call[j+1]'s stack frame */
+    s32e    a4,  a0,  -48   /* save a4 to end of call[j]'s stack frame */
+    s32e    a5,  a0,  -44   /* save a5 to end of call[j]'s stack frame */
+    s32e    a6,  a0,  -40   /* save a6 to end of call[j]'s stack frame */
+    s32e    a7,  a0,  -36   /* save a7 to end of call[j]'s stack frame */
+    s32e    a8,  a0,  -32   /* save a8 to end of call[j]'s stack frame */
+    s32e    a9,  a0,  -28   /* save a9 to end of call[j]'s stack frame */
+    s32e    a10, a0,  -24   /* save a10 to end of call[j]'s stack frame */
+    s32e    a11, a0,  -20   /* save a11 to end of call[j]'s stack frame */
+    rfwo                    /* rotates back to call[i] position */
+
+/*
+--------------------------------------------------------------------------------
+Window Underflow Exception for Call12
+
+Invoked by RETW returning from call[i+1] to call[i]
+where call[i]'s registers must be reloaded (not live in ARs);
+where call[i] had done a call12 to call[i+1].
+On entry here:
+        window rotated to call[i] start point;
+        a0-a11 are undefined, must be reloaded with call[i].reg[0..11];
+        a12-a15 must be preserved (they are call[i+1].reg[0..3]);
+        a13 is call[i+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org 0x140
+    .global _WindowUnderflow12
+_WindowUnderflow12:
+
+    l32e    a0,  a13, -16   /* restore a0 from call[i+1]'s stack frame */
+    l32e    a1,  a13, -12   /* restore a1 from call[i+1]'s stack frame */
+    l32e    a2,  a13,  -8   /* restore a2 from call[i+1]'s stack frame */
+    l32e    a11, a1,  -12   /* a11 <- call[i-1]'s sp
+                               (used to find end of call[i]'s frame) */
+    l32e    a3,  a13,  -4   /* restore a3 from call[i+1]'s stack frame */
+    l32e    a4,  a11, -48   /* restore a4 from end of call[i]'s stack frame */
+    l32e    a5,  a11, -44   /* restore a5 from end of call[i]'s stack frame */
+    l32e    a6,  a11, -40   /* restore a6 from end of call[i]'s stack frame */
+    l32e    a7,  a11, -36   /* restore a7 from end of call[i]'s stack frame */
+    l32e    a8,  a11, -32   /* restore a8 from end of call[i]'s stack frame */
+    l32e    a9,  a11, -28   /* restore a9 from end of call[i]'s stack frame */
+    l32e    a10, a11, -24   /* restore a10 from end of call[i]'s stack frame */
+    l32e    a11, a11, -20   /* restore a11 from end of call[i]'s stack frame */
+    rfwu
+
+#endif /* XCHAL_HAVE_WINDOWED */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c
new file mode 100644
index 0000000..a7e937b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c
@@ -0,0 +1,138 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* 
+Changes from V3.0.0
+	+ ISRcode is pulled inline and portTICKisr() is therefore
+	  deleted from this file.
+
+	+ Prescaler logic for Timer1 added to allow for a wider
+	  range of TickRates.
+
+Changes from V3.0.1
+*/
+
+#include 
+#include 
+
+/* IO port constants. */
+#define portBIT_SET		(1)
+#define portBIT_CLEAR	(0)
+
+/* 
+ * Hardware setup for the tick.
+ * We use a compare match on timer1. Depending on MPU-frequency
+ * and requested tickrate, a prescaled value with a matching
+ * prescaler are determined.
+ */
+#define	portTIMER_COMPARE_BASE			((APROCFREQ/4)/configTICK_RATE_HZ)
+
+#if portTIMER_COMPARE_BASE   < 0x10000
+	#define	portTIMER_COMPARE_VALUE		(portTIMER_COMPARE_BASE)
+	#define portTIMER_COMPARE_PS1		(portBIT_CLEAR)
+	#define portTIMER_COMPARE_PS0		(portBIT_CLEAR)
+#elif portTIMER_COMPARE_BASE < 0x20000
+	#define	portTIMER_COMPARE_VALUE		(portTIMER_COMPARE_BASE / 2)
+	#define portTIMER_COMPARE_PS1		(portBIT_CLEAR)
+	#define portTIMER_COMPARE_PS0		(portBIT_SET)
+#elif portTIMER_COMPARE_BASE < 0x40000
+	#define	portTIMER_COMPARE_VALUE		(portTIMER_COMPARE_BASE / 4)
+	#define portTIMER_COMPARE_PS1		(portBIT_SET)
+	#define portTIMER_COMPARE_PS0		(portBIT_CLEAR)
+#elif portTIMER_COMPARE_BASE < 0x80000
+	#define	portTIMER_COMPARE_VALUE		(portTIMER_COMPARE_BASE / 8)
+	#define portTIMER_COMPARE_PS1		(portBIT_SET)
+	#define portTIMER_COMPARE_PS0		(portBIT_SET)
+#else
+	#error "TickRate out of range"
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup a timer for a regular tick.
+ */
+void portSetupTick( void )
+{
+	/*
+	 * Interrupts are disabled when this function is called.
+	 */
+
+	/*
+	 * Setup CCP1
+	 * Provide the tick interrupt using a compare match on timer1.
+	 */
+
+	/*
+	 * Set the compare match value.
+	 */
+	CCPR1H = ( uint8_t ) ( ( portTIMER_COMPARE_VALUE >> 8 ) & 0xff );
+	CCPR1L = ( uint8_t )   ( portTIMER_COMPARE_VALUE & 0xff );
+
+	/*
+	 * Set Compare Special Event Trigger Mode
+	 */
+	bCCP1M3 	= portBIT_SET;
+	bCCP1M2 	= portBIT_CLEAR;
+	bCCP1M1 	= portBIT_SET;
+	bCCP1M0		= portBIT_SET;
+
+	/*
+	 * Enable CCP1 interrupt
+	 */
+	bCCP1IE 	= portBIT_SET;
+
+	/*
+	 * We are only going to use the global interrupt bit, so disable
+	 * interruptpriorities and enable peripheral interrupts.
+	 */
+	bIPEN		= portBIT_CLEAR;
+	bPEIE		= portBIT_SET;
+
+	/*
+	 * Set up timer1
+	 * It will produce the system tick.
+	 */
+
+	/*
+	 * Clear the time count
+	 */
+	TMR1H = ( uint8_t ) 0x00;
+	TMR1L = ( uint8_t ) 0x00;
+
+	/*
+	 * Setup the timer
+	 */
+	bRD16		= portBIT_SET;				// 16-bit
+	bT1CKPS1	= portTIMER_COMPARE_PS1;	// prescaler
+	bT1CKPS0	= portTIMER_COMPARE_PS0;	// prescaler
+	bT1OSCEN	= portBIT_SET;				// Oscillator enable
+	bT1SYNC		= portBIT_SET;				// No external clock sync
+	bTMR1CS		= portBIT_CLEAR;			// Internal clock
+	
+	bTMR1ON		= portBIT_SET;				// Start timer1
+}
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c
new file mode 100644
index 0000000..29b7d04
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c
@@ -0,0 +1,78 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* 
+Changes from V3.0.0
+	+ ISRcode pulled inline to reduce stack-usage.
+
+	+ Added functionality to only call vTaskSwitchContext() once
+	  when handling multiple interruptsources in a single interruptcall.
+
+	+ Filename changed to a .c extension to allow stepping through code
+	  using F7.
+
+Changes from V3.0.1
+*/
+
+/*
+ * ISR for the tick.
+ * This increments the tick count and, if using the preemptive scheduler, 
+ * performs a context switch.  This must be identical to the manual 
+ * context switch in how it stores the context of a task. 
+ */
+
+#ifndef _FREERTOS_DRIVERS_TICK_ISRTICK_C
+#define _FREERTOS_DRIVERS_TICK_ISRTICK_C
+
+{
+	/*
+	 * Was the interrupt the SystemClock?
+	 */
+	if( bCCP1IF && bCCP1IE )
+	{
+		/*
+		 * Reset the interrupt flag
+		 */
+		bCCP1IF = 0;
+	
+		/*
+	 	 * Maintain the tick count.
+	 	 */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/*
+		 	 * Ask for a switch to the highest priority task
+		 	 * that is ready to run.
+		 	 */
+			uxSwitchRequested = pdTRUE;
+		}
+	}
+}
+
+#pragma wizcpp uselib     "$__PATHNAME__/Tick.c"
+
+#endif	/* _FREERTOS_DRIVERS_TICK_ISRTICK_C */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/WizC/PIC18/Install.bat b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/WizC/PIC18/Install.bat
new file mode 100644
index 0000000..780ec21
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/WizC/PIC18/Install.bat
@@ -0,0 +1,172 @@
+
+@echo off
+cls
+
+SET PACKAGENAME=the FreeRTOS port for fedC and wizC
+
+echo.
+echo Hello, I'm the installationscript for %PACKAGENAME%.
+echo.
+
+:CHECKFEDC
+  set FED=C:\Program Files\FED\PIC_C
+  echo.
+  echo I'm checking your system for fedC
+  if not exist "%FED%" goto NOFEDC
+  echo YES, I found a fedC-installation!
+  goto FOUNDFED
+:NOFEDC
+  echo I could not find a fedC-installation.
+
+
+:CHECKWIZC
+  set FED=C:\Program Files\FED\PIXIE
+  echo.
+  echo I'm checking your system for wizC
+  if not exist "%FED%" goto NOWIZC
+  echo YES, I found a wizC-installation!
+  goto FOUNDFED
+:noWIZC
+  echo I could not find a wizC-installation.
+
+
+:ERROR
+  echo.
+  echo.
+  echo I could not find a FED C-compiler installation on your system.
+  echo.
+  echo Perhaps I got confused because you installed fedC or wizC in a non-default directory.
+  echo If this is the case, please change the path at the top of this install-script.
+  echo After that rerun the script and I will be happy to try again.
+  echo.
+  goto ENDIT
+
+
+:FOUNDFED
+  echo.
+  echo.
+
+  set FEDLIBS=%FED%\Libs
+  set FEDLIBSUSER=%FEDLIBS%\LibsUser
+
+  if exist "%FEDLIBS%" goto INSTALL
+  echo The FED installationdirectory "%FED%"
+  echo contains no Libs subdirectory. This is weird!
+  echo.
+  echo Installation is aborted, sorry...
+  goto ENDIT
+
+
+:INSTALL
+  echo I am about to install %PACKAGENAME%
+  echo into directory %FEDLIBSUSER%
+  echo.
+  echo   Press 'enter'  to let me do my thing
+  echo   Press 'ctrl-c' to stop me
+  pause >nul
+  echo.
+  echo Installing...
+
+
+:RESET_READONLY
+  echo.
+  echo   Removing ReadOnly attributes
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Croutine.c"     >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c"         >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c"         >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c"        >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c"        >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c"    >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h"    >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Croutine.h"     >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\List.h"         >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h"     >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h"     >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h"        >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h"       >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h"         >nul
+  attrib -R "%FEDLIBSUSER%\FreeRTOS.h"                         >nul
+  echo   Done
+
+:CREATE_DIRECTORIES
+  echo.
+  echo   Creating directories (if necessary)...
+  if not exist "%FEDLIBSUSER%"                          mkdir "%FEDLIBSUSER%"
+  if not exist "%FEDLIBSUSER%\libFreeRTOS"              mkdir "%FEDLIBSUSER%\libFreeRTOS"
+  if not exist "%FEDLIBSUSER%\libFreeRTOS\Drivers"      mkdir "%FEDLIBSUSER%\libFreeRTOS\Drivers"
+  if not exist "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick" mkdir "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick"
+  if not exist "%FEDLIBSUSER%\libFreeRTOS\Include"      mkdir "%FEDLIBSUSER%\libFreeRTOS\Include"
+  if not exist "%FEDLIBSUSER%\libFreeRTOS\Modules"      mkdir "%FEDLIBSUSER%\libFreeRTOS\Modules"
+  echo   Done
+
+
+  echo.
+  echo   Copying Files...
+:COPY_MODULES
+  echo     Modules...
+  copy /V /Y "Port.c"                      "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c"         >nul
+  copy /V /Y "..\..\..\Croutine.c"         "%FEDLIBSUSER%\libFreeRTOS\Modules\Croutine.c"     >nul
+  copy /V /Y "..\..\..\List.c"             "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c"         >nul
+  copy /V /Y "..\..\..\Queue.c"            "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c"        >nul
+  copy /V /Y "..\..\..\Tasks.c"            "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c"        >nul
+
+:COPY_DRIVERS
+  echo     Drivers...
+  copy /V /Y "Drivers\Tick\Tick.c"         "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c"    >nul
+  copy /V /Y "Drivers\Tick\isrTick.c"      "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul
+
+:COPY_HEADERS
+  echo     Headers...
+  copy /V /Y "portmacro.h"                 "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h"    >nul
+  copy /V /Y "..\..\..\include\Croutine.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Croutine.h"     >nul
+  copy /V /Y "..\..\..\include\List.h"     "%FEDLIBSUSER%\libFreeRTOS\Include\List.h"         >nul
+  copy /V /Y "..\..\..\include\Portable.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h"     >nul
+  copy /V /Y "..\..\..\include\Projdefs.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h"     >nul
+  copy /V /Y "..\..\..\include\Queue.h"    "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h"        >nul
+  copy /V /Y "..\..\..\include\Semphr.h"   "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h"       >nul
+  copy /V /Y "..\..\..\include\Task.h"     "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h"         >nul
+  copy /V /Y "addFreeRTOS.h" + "..\..\..\include\FreeRTOS.h" "%FEDLIBSUSER%\FreeRTOS.h"       >nul
+
+
+  echo   Done
+
+
+:SET_READONLY
+  echo.
+  echo   Setting files to ReadOnly
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c"         >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Croutine.c"     >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c"         >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c"        >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c"        >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c"    >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h"    >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Croutine.h"     >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\List.h"         >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h"     >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h"     >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h"        >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h"       >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h"         >nul
+  attrib +R "%FEDLIBSUSER%\FreeRTOS.h"                         >nul
+  echo   Done
+
+
+:FINISHED
+  echo.
+  echo The installation of %PACKAGENAME% is completed.
+  echo.
+  echo Please review the installation instructions as additional libraries
+  echo  and fedC/wizC configuration settings may be needed for FreeRTOS
+  echo  to function correctly.
+
+  goto ENDIT
+
+
+:ENDIT
+  echo.
+  echo.
+  echo Press 'enter' to close this window
+  pause >nul
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/WizC/PIC18/addFreeRTOS.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/WizC/PIC18/addFreeRTOS.h
new file mode 100644
index 0000000..02729db
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/WizC/PIC18/addFreeRTOS.h
@@ -0,0 +1,53 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V3.0.0
+
+Changes from V3.0.1
+
+Changes from V4.0.1
+    Uselib pragma added for Croutine.c
+*/
+
+/*
+ * The installation script will automatically prepend this file to the default FreeRTOS.h.
+ */
+
+#ifndef WIZC_FREERTOS_H
+#define WIZC_FREERTOS_H
+
+#pragma	noheap
+#pragma wizcpp expandnl   on
+#pragma wizcpp searchpath "$__PATHNAME__/libFreeRTOS/Include/"
+#pragma wizcpp uselib     "$__PATHNAME__/libFreeRTOS/Modules/Croutine.c"
+#pragma wizcpp uselib     "$__PATHNAME__/libFreeRTOS/Modules/Tasks.c"
+#pragma wizcpp uselib     "$__PATHNAME__/libFreeRTOS/Modules/Queue.c"
+#pragma wizcpp uselib     "$__PATHNAME__/libFreeRTOS/Modules/List.c"
+#pragma wizcpp uselib     "$__PATHNAME__/libFreeRTOS/Modules/Port.c"
+
+#endif	/* WIZC_FREERTOS_H */
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/WizC/PIC18/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/WizC/PIC18/port.c
new file mode 100644
index 0000000..c999f87
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/WizC/PIC18/port.c
@@ -0,0 +1,317 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V3.2.1
+	+ CallReturn Depth increased from 8 to 10 levels to accomodate wizC/fedC V12.
+
+Changes from V3.2.0
+	+ TBLPTRU is now initialised to zero during the initial stack creation of a new task. This solves
+	an error on devices with more than 64kB ROM.
+
+Changes from V3.0.0
+	+ ucCriticalNesting is now initialised to 0x7F to prevent interrupts from being
+          handled before the scheduler is started.
+
+Changes from V3.0.1
+*/
+
+/* Scheduler include files. */
+#include 
+#include 
+
+#include 
+
+/*---------------------------------------------------------------------------
+ * Implementation of functions defined in portable.h for the WizC PIC18 port.
+ *---------------------------------------------------------------------------*/
+
+/*
+ * We require the address of the pxCurrentTCB variable, but don't want to
+ * know any details of its type.
+ */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/*
+ * Define minimal-stack constants
+ * -----
+ * FSR's:
+ *		STATUS, WREG, BSR, PRODH, PRODL, FSR0H, FSR0L,
+ *		FSR1H, FSR1L,TABLAT, (TBLPTRU), TBLPTRH, TBLPTRL,
+ *		(PCLATU), PCLATH
+ *		sfr's within parenthesis only on devices > 64kB
+ * -----
+ * Call/Return stack:
+ *		 2 bytes per entry on devices <= 64kB
+ *		 3 bytes per entry on devices >  64kB
+ * -----
+ * Other bytes:
+ *		 2 bytes: FunctionParameter for initial taskcode
+ *		 1 byte : Number of entries on call/return stack
+ *		 1 byte : ucCriticalNesting
+ *		16 bytes: Free space on stack
+ */
+#if _ROMSIZE > 0x8000
+	#define portSTACK_FSR_BYTES				( 15 )
+	#define portSTACK_CALLRETURN_ENTRY_SIZE	(  3 )
+#else
+	#define portSTACK_FSR_BYTES				( 13 )
+	#define portSTACK_CALLRETURN_ENTRY_SIZE	(  2 )
+#endif
+
+#define portSTACK_MINIMAL_CALLRETURN_DEPTH	( 10 )
+#define portSTACK_OTHER_BYTES				( 20 )
+
+uint16_t usCalcMinStackSize		= 0;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * We initialise ucCriticalNesting to the middle value an
+ * uint8_t can contain. This way portENTER_CRITICAL()
+ * and portEXIT_CRITICAL() can be called without interrupts
+ * being enabled before the scheduler starts.
+ */
+register uint8_t ucCriticalNesting = 0x7F;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a new task.
+ * See portSAVE_CONTEXT macro for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint8_t ucScratch;
+	/*
+	 * Get the size of the RAMarea in page 0 used by the compiler
+	 * We do this here already to avoid W-register conflicts.
+	 */
+	_Pragma("asm")
+		movlw	OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE
+		movwf	PRODL,ACCESS		; PRODL is used as temp register
+	_Pragma("asmend")
+	ucScratch = PRODL;
+
+	/*
+	 * Place a few bytes of known values on the bottom of the stack.
+	 * This is just useful for debugging.
+	 */
+//	*pxTopOfStack--	= 0x11;
+//	*pxTopOfStack-- = 0x22;
+//	*pxTopOfStack-- = 0x33;
+
+	/*
+	 * Simulate how the stack would look after a call to vPortYield()
+	 * generated by the compiler.
+	 */
+
+	/*
+	 * First store the function parameters.  This is where the task expects
+	 * to find them when it starts running.
+	 */
+	*pxTopOfStack-- = ( StackType_t ) ( (( uint16_t ) pvParameters >> 8) & 0x00ff );
+	*pxTopOfStack-- = ( StackType_t ) (  ( uint16_t ) pvParameters       & 0x00ff );
+
+	/*
+	 * Next are all the registers that form part of the task context.
+	 */
+	*pxTopOfStack-- = ( StackType_t ) 0x11; /* STATUS. */
+	*pxTopOfStack-- = ( StackType_t ) 0x22; /* WREG. */
+	*pxTopOfStack-- = ( StackType_t ) 0x33; /* BSR. */
+	*pxTopOfStack-- = ( StackType_t ) 0x44; /* PRODH. */
+	*pxTopOfStack-- = ( StackType_t ) 0x55; /* PRODL. */
+	*pxTopOfStack-- = ( StackType_t ) 0x66; /* FSR0H. */
+	*pxTopOfStack-- = ( StackType_t ) 0x77; /* FSR0L. */
+	*pxTopOfStack-- = ( StackType_t ) 0x88; /* FSR1H. */
+	*pxTopOfStack-- = ( StackType_t ) 0x99; /* FSR1L. */
+	*pxTopOfStack-- = ( StackType_t ) 0xAA; /* TABLAT. */
+#if _ROMSIZE > 0x8000
+	*pxTopOfStack-- = ( StackType_t ) 0x00; /* TBLPTRU. */
+#endif
+	*pxTopOfStack-- = ( StackType_t ) 0xCC; /* TBLPTRH. */
+	*pxTopOfStack-- = ( StackType_t ) 0xDD; /* TBLPTRL. */
+#if _ROMSIZE > 0x8000
+	*pxTopOfStack-- = ( StackType_t ) 0xEE; /* PCLATU. */
+#endif
+	*pxTopOfStack-- = ( StackType_t ) 0xFF; /* PCLATH. */
+
+	/*
+	 * Next the compiler's scratchspace.
+	 */
+	while(ucScratch-- > 0)
+	{
+		*pxTopOfStack-- = ( StackType_t ) 0;
+	}
+
+	/*
+	 * The only function return address so far is the address of the task entry.
+	 * The order is TOSU/TOSH/TOSL. For devices > 64kB, TOSU is put on the
+	 * stack, too. TOSU is always written as zero here because wizC does not allow
+	 * functionpointers to point above 64kB in ROM.
+	 */
+#if _ROMSIZE > 0x8000
+	*pxTopOfStack-- = ( StackType_t ) 0;
+#endif
+	*pxTopOfStack-- = ( StackType_t ) ( ( ( uint16_t ) pxCode >> 8 ) & 0x00ff );
+	*pxTopOfStack-- = ( StackType_t ) ( (   uint16_t ) pxCode        & 0x00ff );
+
+	/*
+	 * Store the number of return addresses on the hardware stack.
+	 * So far only the address of the task entry point.
+	 */
+	*pxTopOfStack-- = ( StackType_t ) 1;
+
+	/*
+	 * The code generated by wizC does not maintain separate
+	 * stack and frame pointers. Therefore the portENTER_CRITICAL macro cannot
+	 * use the stack as per other ports.  Instead a variable is used to keep
+	 * track of the critical section nesting.  This variable has to be stored
+	 * as part of the task context and is initially set to zero.
+	 */
+	*pxTopOfStack-- = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+uint16_t usPortCALCULATE_MINIMAL_STACK_SIZE( void )
+{
+	/*
+	 * Fetch the size of compiler's scratchspace.
+	 */
+	_Pragma("asm")
+		movlw	OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE
+		movlb	usCalcMinStackSize>>8
+		movwf	usCalcMinStackSize,BANKED
+	_Pragma("asmend")
+
+	/*
+	 * Add minimum needed stackspace
+	 */
+	usCalcMinStackSize	+=	( portSTACK_FSR_BYTES )
+		+	( portSTACK_MINIMAL_CALLRETURN_DEPTH * portSTACK_CALLRETURN_ENTRY_SIZE )
+		+	( portSTACK_OTHER_BYTES );
+
+	return(usCalcMinStackSize);
+}
+
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	extern void portSetupTick( void );
+
+	/*
+	 * Setup a timer for the tick ISR for the preemptive scheduler.
+	 */
+	portSetupTick();
+
+	/*
+	 * Restore the context of the first task to run.
+	 */
+	portRESTORE_CONTEXT();
+
+	/*
+	 * This point should never be reached during execution.
+	 */
+	return pdTRUE;
+}
+
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/*
+	 * It is unlikely that the scheduler for the PIC port will get stopped
+	 * once running. When called a reset is done which is probably the
+	 * most valid action.
+	 */
+	_Pragma(asmline reset);
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch.  This is similar to the tick context switch,
+ * but does not increment the tick count.  It must be identical to the
+ * tick context switch in how it stores the stack of a task.
+ */
+void vPortYield( void )
+{
+	/*
+	 * Save the context of the current task.
+	 */
+	portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
+
+	/*
+	 * Switch to the highest priority task that is ready to run.
+	 */
+	vTaskSwitchContext();
+
+	/*
+	 * Start executing the task we have just switched to.
+	 */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	void *pvPortMalloc( uint16_t usWantedSize )
+	{
+	void *pvReturn;
+
+		vTaskSuspendAll();
+		{
+			pvReturn = malloc( ( malloc_t ) usWantedSize );
+		}
+		xTaskResumeAll();
+
+		return pvReturn;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	void vPortFree( void *pv )
+	{
+		if( pv )
+		{
+			vTaskSuspendAll();
+			{
+				free( pv );
+			}
+			xTaskResumeAll();
+		}
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/WizC/PIC18/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/WizC/PIC18/portmacro.h
new file mode 100644
index 0000000..da73925
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/WizC/PIC18/portmacro.h
@@ -0,0 +1,423 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V3.0.0
+
+Changes from V3.0.1
+*/
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#if !defined(_SERIES) || _SERIES != 18
+	#error "WizC supports FreeRTOS on the Microchip PIC18-series only"
+#endif
+
+#if !defined(QUICKCALL) || QUICKCALL != 1
+	#error "QuickCall must be enabled (see ProjectOptions/Optimisations)"
+#endif
+
+#include 
+#include 
+
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		portFLOAT
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint8_t
+#define portBASE_TYPE	char
+
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )	( 0xFFFF )
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )	( 0xFFFFFFFF )
+#endif
+
+#define portBYTE_ALIGNMENT			1
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Constant used for context switch macro when we require the interrupt
+ * enable state to be forced when the interrupted task is switched back in.
+ */
+#define portINTERRUPTS_FORCED				(0x01)
+
+/*
+ * Constant used for context switch macro when we require the interrupt
+ * enable state to be unchanged when the interrupted task is switched back in.
+ */
+#define portINTERRUPTS_UNCHANGED			(0x00)
+
+/* Initial interrupt enable state for newly created tasks.  This value is
+ * used when a task switches in for the first time.
+ */
+#define portINTERRUPTS_INITIAL_STATE		(portINTERRUPTS_FORCED)
+
+/*
+ * Macros to modify the global interrupt enable bit in INTCON.
+ */
+#define portDISABLE_INTERRUPTS()	\
+	do								\
+	{								\
+		bGIE=0;						\
+	} while(bGIE)	// MicroChip recommends this check!
+
+#define portENABLE_INTERRUPTS()		\
+	do								\
+	{								\
+		bGIE=1;						\
+	} while(0)
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Critical section macros.
+ */
+extern uint8_t ucCriticalNesting;
+
+#define portNO_CRITICAL_SECTION_NESTING		( ( uint8_t ) 0 )
+
+#define portENTER_CRITICAL()										\
+	do																\
+	{																\
+		portDISABLE_INTERRUPTS();									\
+																	\
+		/*															\
+		 * Now interrupts are disabled ucCriticalNesting			\
+		 * can be accessed directly. Increment						\
+		 * ucCriticalNesting to keep a count of how					\
+		 * many times portENTER_CRITICAL() has been called. 		\
+		 */															\
+		ucCriticalNesting++;										\
+	} while(0)
+
+#define portEXIT_CRITICAL()											\
+	do																\
+	{																\
+		if(ucCriticalNesting > portNO_CRITICAL_SECTION_NESTING)		\
+		{															\
+			/*														\
+			 * Decrement the nesting count as we are leaving a		\
+			 * critical section.									\
+			 */														\
+			ucCriticalNesting--;									\
+		}															\
+																	\
+		/*															\
+		 * If the nesting level has reached zero then				\
+		 * interrupts should be re-enabled.							\
+		 */															\
+		if( ucCriticalNesting == portNO_CRITICAL_SECTION_NESTING )	\
+		{															\
+			portENABLE_INTERRUPTS();								\
+		}															\
+	} while(0)
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The minimal stacksize is calculated on the first reference of
+ * portMINIMAL_STACK_SIZE. Some input to this calculation is
+ * compiletime determined, other input is port-defined (see port.c)
+ */
+extern uint16_t usPortCALCULATE_MINIMAL_STACK_SIZE( void );
+extern uint16_t usCalcMinStackSize;
+
+#define portMINIMAL_STACK_SIZE					\
+	((usCalcMinStackSize == 0)					\
+		? usPortCALCULATE_MINIMAL_STACK_SIZE()	\
+		: usCalcMinStackSize )
+
+/*
+ * WizC uses a downgrowing stack
+ */
+#define portSTACK_GROWTH			( -1 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro's that pushes all the registers that make up the context of a task onto
+ * the stack, then saves the new top of stack into the TCB. TOSU and TBLPTRU
+ * are only saved/restored on devices with more than 64kB (32k Words) ROM.
+ *
+ * The stackpointer is helt by WizC in FSR2 and points to the first free byte.
+ * WizC uses a "downgrowing" stack. There is no framepointer.
+ *
+ * We keep track of the interruptstatus using ucCriticalNesting. When this
+ * value equals zero, interrupts have to be enabled upon exit from the
+ * portRESTORE_CONTEXT macro.
+ *
+ * If this is called from an ISR then the interrupt enable bits must have been
+ * set for the ISR to ever get called.  Therefore we want to save
+ * ucCriticalNesting with value zero. This means the interrupts will again be
+ * re-enabled when the interrupted task is switched back in.
+ *
+ * If this is called from a manual context switch (i.e. from a call to yield),
+ * then we want to keep the current value of ucCritialNesting so it is restored
+ * with its current value. This allows a yield from within a critical section.
+ *
+ * The compiler uses some locations at the bottom of RAM for temporary
+ * storage. The compiler may also have been instructed to optimize
+ * function-parameters and local variables to global storage. The compiler
+ * uses an area called LocOpt for this wizC feature.
+ * The total overheadstorage has to be saved in it's entirety as part of
+ * a task context. These macro's store/restore from data address 0x0000 to
+ * (OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE - 1).
+ * OVERHEADPAGE0, LOCOPTSIZE and MAXLOCOPTSIZE are compiler-generated
+ * assembler definitions.
+ */
+
+#define	portSAVE_CONTEXT( ucInterruptForced )						\
+	do																\
+	{																\
+		portDISABLE_INTERRUPTS();									\
+																	\
+		_Pragma("asm")												\
+			;														\
+			; Push the relevant SFR's onto the task's stack			\
+			;														\
+			movff   STATUS,POSTDEC2									\
+			movff	WREG,POSTDEC2									\
+			movff	BSR,POSTDEC2									\
+			movff	PRODH,POSTDEC2									\
+			movff	PRODL,POSTDEC2									\
+			movff	FSR0H,POSTDEC2									\
+			movff	FSR0L,POSTDEC2									\
+			movff	FSR1H,POSTDEC2									\
+			movff	FSR1L,POSTDEC2									\
+			movff	TABLAT,POSTDEC2									\
+			if __ROMSIZE > 0x8000									\
+				movff	TBLPTRU,POSTDEC2							\
+			endif													\
+			movff	TBLPTRH,POSTDEC2								\
+			movff	TBLPTRL,POSTDEC2								\
+			if __ROMSIZE > 0x8000									\
+				movff	PCLATU,POSTDEC2								\
+			endif													\
+			movff	PCLATH,POSTDEC2									\
+			;														\
+			; Store the compiler-scratch-area as described above.	\
+			;														\
+			movlw	OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE			\
+			clrf	FSR0L,ACCESS									\
+			clrf	FSR0H,ACCESS									\
+		_rtos_S1:													\
+			movff	POSTINC0,POSTDEC2								\
+			decfsz	WREG,W,ACCESS									\
+			SMARTJUMP _rtos_S1										\
+			;														\
+			; Save the pic call/return-stack belonging to the		\
+			; current task by copying it to the task's software-	\
+			; stack. We save the hardware stack pointer (which		\
+			; is the number of addresses on the stack) in the		\
+			; W-register first because we need it later and it		\
+			; is modified in the save-loop by executing pop's.		\
+			; After the loop the W-register is stored on the		\
+			; stack, too.											\
+			;														\
+			movf	STKPTR,W,ACCESS									\
+			bz		_rtos_s3										\
+		_rtos_S2:													\
+			if __ROMSIZE > 0x8000									\
+				movff	TOSU,POSTDEC2								\
+			endif													\
+			movff	TOSH,POSTDEC2									\
+			movff	TOSL,POSTDEC2									\
+			pop														\
+			tstfsz	STKPTR,ACCESS									\
+			SMARTJUMP _rtos_S2										\
+		_rtos_s3:													\
+			movwf	POSTDEC2,ACCESS									\
+			;														\
+			; Next the value for ucCriticalNesting used by the		\
+			; task is stored on the stack. When						\
+			; (ucInterruptForced == portINTERRUPTS_FORCED), we save	\
+			; it as 0 (portNO_CRITICAL_SECTION_NESTING).			\
+			;														\
+			if ucInterruptForced == portINTERRUPTS_FORCED			\
+				clrf POSTDEC2,ACCESS								\
+			else													\
+				movff	ucCriticalNesting,POSTDEC2					\
+			endif													\
+			;														\
+			; Save the new top of the software stack in the TCB.	\
+			;														\
+			movff	pxCurrentTCB,FSR0L								\
+			movff	pxCurrentTCB+1,FSR0H							\
+			movff	FSR2L,POSTINC0									\
+			movff	FSR2H,POSTINC0									\
+		_Pragma("asmend")											\
+	} while(0)
+
+/************************************************************/
+
+/*
+ * This is the reverse of portSAVE_CONTEXT.
+ */
+#define portRESTORE_CONTEXT()										\
+	do																\
+	{																\
+		_Pragma("asm")												\
+			;														\
+			; Set FSR0 to point to pxCurrentTCB->pxTopOfStack.		\
+			;														\
+			movff	pxCurrentTCB,FSR0L								\
+			movff	pxCurrentTCB+1,FSR0H							\
+			;														\
+			; De-reference FSR0 to set the address it holds into	\
+			; FSR2 (i.e. *( pxCurrentTCB->pxTopOfStack ) ). FSR2	\
+			; is used by wizC as stackpointer.						\
+			;														\
+			movff	POSTINC0,FSR2L									\
+			movff	POSTINC0,FSR2H									\
+			;														\
+			; Next, the value for ucCriticalNesting used by the		\
+			; task is retrieved from the stack.						\
+			;														\
+			movff	PREINC2,ucCriticalNesting						\
+			;														\
+			; Rebuild the pic call/return-stack. The number of		\
+			; return addresses is the next item on the task stack.	\
+			; Save this number in PRODL. Then fetch the addresses	\
+			; and store them on the hardwarestack.					\
+			; The datasheets say we can't use movff here...			\
+			;														\
+			movff	PREINC2,PRODL	// Use PRODL as tempregister	\
+			clrf	STKPTR,ACCESS									\
+		_rtos_R1:													\
+			push													\
+			movf	PREINC2,W,ACCESS								\
+			movwf	TOSL,ACCESS										\
+			movf	PREINC2,W,ACCESS								\
+			movwf	TOSH,ACCESS										\
+			if __ROMSIZE > 0x8000									\
+				movf	PREINC2,W,ACCESS							\
+				movwf	TOSU,ACCESS									\
+			else													\
+				clrf	TOSU,ACCESS									\
+			endif													\
+			decfsz	PRODL,F,ACCESS									\
+			SMARTJUMP _rtos_R1										\
+			;														\
+			; Restore the compiler's working storage area to page 0	\
+			;														\
+			movlw	OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE			\
+			movwf	FSR0L,ACCESS									\
+			clrf	FSR0H,ACCESS									\
+		_rtos_R2:													\
+			decf	FSR0L,F,ACCESS									\
+			movff	PREINC2,INDF0									\
+			tstfsz	FSR0L,ACCESS									\
+			SMARTJUMP _rtos_R2										\
+			;														\
+			; Restore the sfr's forming the tasks context.			\
+			; We cannot yet restore bsr, w and status because		\
+			; we need these	registers for a final test.				\
+			;														\
+			movff	PREINC2,PCLATH									\
+			if __ROMSIZE > 0x8000									\
+				movff	PREINC2,PCLATU								\
+			else													\
+				clrf	PCLATU,ACCESS								\
+			endif													\
+			movff	PREINC2,TBLPTRL									\
+			movff	PREINC2,TBLPTRH									\
+			if __ROMSIZE > 0x8000									\
+				movff	PREINC2,TBLPTRU								\
+			else													\
+				clrf	TBLPTRU,ACCESS								\
+			endif													\
+			movff	PREINC2,TABLAT									\
+			movff	PREINC2,FSR1L									\
+			movff	PREINC2,FSR1H									\
+			movff	PREINC2,FSR0L									\
+			movff	PREINC2,FSR0H									\
+			movff	PREINC2,PRODL									\
+			movff	PREINC2,PRODH									\
+			;														\
+			; The return from portRESTORE_CONTEXT() depends on		\
+			; the value of ucCriticalNesting. When it is zero,		\
+			; interrupts need to be enabled. This is done via a		\
+			; retfie instruction because we need the				\
+			; interrupt-enabling and the return to the restored		\
+			; task to be uninterruptable.							\
+	 		; Because bsr, status and W are affected by the test	\
+	 		; they are restored after the test.						\
+			;														\
+			movlb	ucCriticalNesting>>8							\
+			tstfsz	ucCriticalNesting,BANKED						\
+			SMARTJUMP _rtos_R4										\
+		_rtos_R3:													\
+			movff	PREINC2,BSR										\
+			movff	PREINC2,WREG									\
+			movff	PREINC2,STATUS									\
+			retfie	0		; Return enabling interrupts			\
+		_rtos_R4:													\
+			movff	PREINC2,BSR										\
+			movff	PREINC2,WREG									\
+			movff	PREINC2,STATUS									\
+			return	0		; Return without affecting interrupts	\
+		_Pragma("asmend")											\
+	} while(0)
+
+/*-----------------------------------------------------------*/
+
+#define portTICK_PERIOD_MS	( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+
+/*-----------------------------------------------------------*/
+
+extern void vPortYield( void );
+#define portYIELD()				vPortYield()
+
+#define portNOP()	_Pragma("asm")									\
+						nop											\
+					_Pragma("asmend")
+
+/*-----------------------------------------------------------*/
+
+#define portTASK_FUNCTION( xFunction, pvParameters )	 	\
+	void pointed xFunction( void *pvParameters )		\
+	_Pragma(asmfunc xFunction)
+
+#define portTASK_FUNCTION_PROTO		portTASK_FUNCTION
+/*-----------------------------------------------------------*/
+
+
+#define volatile
+#define register
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/oWatcom/16BitDOS/Flsh186/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/oWatcom/16BitDOS/Flsh186/port.c
new file mode 100644
index 0000000..18e88bc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/oWatcom/16BitDOS/Flsh186/port.c
@@ -0,0 +1,246 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V1.00:
+	
+	+ Call to taskYIELD() from within tick ISR has been replaced by the more
+	  efficient portSWITCH_CONTEXT().
+	+ ISR function definitions renamed to include the prv prefix.
+
+Changes from V1.2.0:
+
+	+ portRESET_PIC() is now called last thing before the end of the preemptive
+	  tick routine.
+
+Changes from V2.6.1
+
+	+ Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
+	  macro to be consistent with the later ports.
+*/
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the Flashlite 186
+ * port.
+ *----------------------------------------------------------*/
+
+#include 
+#include 
+#include 
+#include 
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "portasm.h"
+
+/*lint -e950 Non ANSI reserved words okay in this file only. */
+
+#define portTIMER_EOI_TYPE		( 8 )
+#define portRESET_PIC()			portOUTPUT_WORD( ( uint16_t ) 0xff22, portTIMER_EOI_TYPE )
+#define portTIMER_INT_NUMBER	0x12
+
+#define portTIMER_1_CONTROL_REGISTER	( ( uint16_t ) 0xff5e )
+#define portTIMER_0_CONTROL_REGISTER	( ( uint16_t ) 0xff56 )
+#define portTIMER_INTERRUPT_ENABLE		( ( uint16_t ) 0x2000 )
+
+/* Setup the hardware to generate the required tick frequency. */
+static void prvSetTickFrequency( uint32_t ulTickRateHz );
+
+/* Set the hardware back to the state as per before the scheduler started. */
+static void prvExitFunction( void );
+
+#if configUSE_PREEMPTION == 1
+	/* Tick service routine used by the scheduler when preemptive scheduling is
+	being used. */
+	static void __interrupt __far prvPreemptiveTick( void );
+#else
+	/* Tick service routine used by the scheduler when cooperative scheduling is 
+	being used. */
+	static void __interrupt __far prvNonPreemptiveTick( void );
+#endif
+
+/* Trap routine used by taskYIELD() to manually cause a context switch. */
+static void __interrupt __far prvYieldProcessor( void );
+
+/*lint -e956 File scopes necessary here. */
+
+/* Set true when the vectors are set so the scheduler will service the tick. */
+static int16_t sSchedulerRunning = pdFALSE;
+
+/* Points to the original routine installed on the vector we use for manual context switches.  This is then used to restore the original routine during prvExitFunction(). */
+static void ( __interrupt __far *pxOldSwitchISR )();
+
+/* Used to restore the original DOS context when the scheduler is ended. */
+static jmp_buf xJumpBuf;
+
+/*lint +e956 */
+
+/*-----------------------------------------------------------*/
+BaseType_t xPortStartScheduler( void )
+{
+	/* This is called with interrupts already disabled. */
+
+	/* Remember what was on the interrupts we are going to use
+	so we can put them back later if required. */
+	pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
+
+	/* Put our manual switch (yield) function on a known
+	vector. */
+	_dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
+
+	#if configUSE_PREEMPTION == 1
+	{		
+		/* Put our tick switch function on the timer interrupt. */
+		_dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
+	}
+	#else
+	{
+		/* We want the timer interrupt to just increment the tick count. */
+		_dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );
+	}
+	#endif
+
+	prvSetTickFrequency( configTICK_RATE_HZ );
+
+	/* Clean up function if we want to return to DOS. */
+	if( setjmp( xJumpBuf ) != 0 )
+	{
+		prvExitFunction();
+		sSchedulerRunning = pdFALSE;
+	}
+	else
+	{
+		sSchedulerRunning = pdTRUE;
+
+		/* Kick off the scheduler by setting up the context of the first task. */
+		portFIRST_CONTEXT();
+	}
+
+	return sSchedulerRunning;
+}
+/*-----------------------------------------------------------*/
+
+/* The tick ISR used depend on whether or not the preemptive or cooperative
+kernel is being used. */
+#if configUSE_PREEMPTION == 1
+	static void __interrupt __far prvPreemptiveTick( void )
+	{
+		/* Get the scheduler to update the task states following the tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Switch in the context of the next task to be run. */
+			portSWITCH_CONTEXT();
+		}
+
+		/* Reset the PIC ready for the next time. */
+		portRESET_PIC();
+	}
+#else
+	static void __interrupt __far prvNonPreemptiveTick( void )
+	{
+		/* Same as preemptive tick, but the cooperative scheduler is being used
+		so we don't have to switch in the context of the next task. */
+		xTaskIncrementTick();
+		portRESET_PIC();
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+static void __interrupt __far prvYieldProcessor( void )
+{
+	/* Switch in the context of the next task to be run. */
+	portSWITCH_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Jump back to the processor state prior to starting the
+	scheduler.  This means we are not going to be using a
+	task stack frame so the task can be deleted. */
+	longjmp( xJumpBuf, 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvExitFunction( void )
+{
+const uint16_t usTimerDisable = 0x0000;
+uint16_t usTimer0Control;
+
+	/* Interrupts should be disabled here anyway - but no 
+	harm in making sure. */
+	portDISABLE_INTERRUPTS();
+	if( sSchedulerRunning == pdTRUE )
+	{
+		/* Put back the switch interrupt routines that was in place
+		before the scheduler started. */
+		_dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
+	}
+
+	/* Disable the timer used for the tick to ensure the scheduler is
+	not called before restoring interrupts.  There was previously nothing
+	on this timer so there is no old ISR to restore. */
+	portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable );
+
+	/* Restart the DOS tick. */
+	usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );
+	usTimer0Control |= portTIMER_INTERRUPT_ENABLE;
+	portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );
+
+
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetTickFrequency( uint32_t ulTickRateHz )
+{
+const uint16_t usMaxCountRegister = 0xff5a;
+const uint16_t usTimerPriorityRegister = 0xff32;
+const uint16_t usTimerEnable = 0xC000;
+const uint16_t usRetrigger = 0x0001;
+const uint16_t usTimerHighPriority = 0x0000;
+uint16_t usTimer0Control;
+
+/* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */
+
+const uint32_t ulClockFrequency = 0x7f31a0;
+
+uint32_t ulTimerCount = ulClockFrequency / ulTickRateHz;
+
+	portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger );
+	portOUTPUT_WORD( usMaxCountRegister, ( uint16_t ) ulTimerCount );
+	portOUTPUT_WORD( usTimerPriorityRegister, usTimerHighPriority );
+
+	/* Stop the DOS tick - don't do this if you want to maintain a TOD clock. */
+	usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );
+	usTimer0Control &= ~portTIMER_INTERRUPT_ENABLE;
+	portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );
+}
+
+
+/*lint +e950 */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h
new file mode 100644
index 0000000..59a36cc
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h
@@ -0,0 +1,110 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+
+/* Type definitions. */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      long
+#define portLONG        long
+#define portSHORT       int
+#define portSTACK_TYPE  uint16_t
+#define portBASE_TYPE	short
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t TickType_t;
+        #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+        typedef uint32_t TickType_t;
+        #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+void portENTER_CRITICAL( void );
+#pragma aux portENTER_CRITICAL = "pushf" \
+                                 "cli";
+
+void portEXIT_CRITICAL( void );
+#pragma aux portEXIT_CRITICAL   = "popf";
+
+void portDISABLE_INTERRUPTS( void );
+#pragma aux portDISABLE_INTERRUPTS = "cli";
+
+void portENABLE_INTERRUPTS( void );
+#pragma aux portENABLE_INTERRUPTS = "sti";
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH        ( -1 )
+#define portSWITCH_INT_NUMBER   0x80
+#define portYIELD()             __asm{ int portSWITCH_INT_NUMBER }
+#define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT      2
+#define portINITIAL_SW          ( ( portSTACK_TYPE ) 0x0202 )   /* Start the tasks with interrupts enabled. */
+#define portNOP()				__asm{ nop }
+/*-----------------------------------------------------------*/
+
+/* Compiler specifics. */
+#define portINPUT_BYTE( xAddr )                 inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )       outp( xAddr, ucValue )
+#define portINPUT_WORD( xAddr )                 inpw( xAddr )
+#define portOUTPUT_WORD( xAddr, usValue )       outpw( xAddr, usValue )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/oWatcom/16BitDOS/PC/port.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/oWatcom/16BitDOS/PC/port.c
new file mode 100644
index 0000000..4f9410f
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/oWatcom/16BitDOS/PC/port.c
@@ -0,0 +1,302 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V1.00:
+	
+	+ Call to taskYIELD() from within tick ISR has been replaced by the more
+	  efficient portSWITCH_CONTEXT().
+	+ ISR function definitions renamed to include the prv prefix.
+
+Changes from V1.2.0:
+
+	+ prvPortResetPIC() is now called last thing before the end of the 
+	  preemptive tick routine.
+
+Changes from V2.6.1
+
+	+ Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
+	  macro to be consistent with the later ports.
+
+Changes from V4.0.1
+	
+	+ Add function prvSetTickFrequencyDefault() to set the DOS tick back to
+	  its proper value when the scheduler exits. 
+*/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "portasm.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the industrial
+ * PC port.
+ *----------------------------------------------------------*/
+
+/*lint -e950 Non ANSI reserved words okay in this file only. */
+
+#define portTIMER_INT_NUMBER	0x08
+
+/* Setup hardware for required tick interrupt rate. */
+static void prvSetTickFrequency( uint32_t ulTickRateHz );
+
+/* Restore hardware to as it was prior to starting the scheduler. */
+static void prvExitFunction( void );
+
+/* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC
+directly.  We chain to the DOS tick as close as possible to the standard DOS
+tick rate. */
+static void prvPortResetPIC( void );
+
+/* The tick ISR used depends on whether the preemptive or cooperative scheduler
+is being used. */
+#if configUSE_PREEMPTION == 1
+	/* Tick service routine used by the scheduler when preemptive scheduling is
+	being used. */
+	static void __interrupt __far prvPreemptiveTick( void );
+#else
+	/* Tick service routine used by the scheduler when cooperative scheduling is 
+	being used. */
+	static void __interrupt __far prvNonPreemptiveTick( void );
+#endif
+/* Trap routine used by taskYIELD() to manually cause a context switch. */
+static void __interrupt __far prvYieldProcessor( void );
+
+/* Set the tick frequency back so the floppy drive works correctly when the
+scheduler exits. */
+static void prvSetTickFrequencyDefault( void );
+
+/*lint -e956 File scopes necessary here. */
+
+/* Used to signal when to chain to the DOS tick, and when to just clear the PIC ourselves. */
+static int16_t sDOSTickCounter;							
+
+/* Set true when the vectors are set so the scheduler will service the tick. */
+static int16_t sSchedulerRunning = pdFALSE;				
+
+/* Points to the original routine installed on the vector we use for manual context switches.  This is then used to restore the original routine during prvExitFunction(). */
+static void ( __interrupt __far *pxOldSwitchISR )();		
+
+/* Points to the original routine installed on the vector we use to chain to the DOS tick.  This is then used to restore the original routine during prvExitFunction(). */
+static void ( __interrupt __far *pxOldSwitchISRPlus1 )();	
+
+/* Used to restore the original DOS context when the scheduler is ended. */
+static jmp_buf xJumpBuf;
+
+/*lint +e956 */
+
+/*-----------------------------------------------------------*/
+BaseType_t xPortStartScheduler( void )
+{
+pxISR pxOriginalTickISR;
+	
+	/* This is called with interrupts already disabled. */
+
+	/* Remember what was on the interrupts we are going to use
+	so we can put them back later if required. */
+	pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
+	pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER );
+	pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
+
+	prvSetTickFrequency( configTICK_RATE_HZ );
+
+	/* Put our manual switch (yield) function on a known
+	vector. */
+	_dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
+
+	/* Put the old tick on a different interrupt number so we can
+	call it when we want. */
+	_dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR );
+
+	#if configUSE_PREEMPTION == 1
+	{		
+		/* Put our tick switch function on the timer interrupt. */
+		_dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
+	}
+	#else
+	{
+		/* We want the timer interrupt to just increment the tick count. */
+		_dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );
+	}
+	#endif
+
+	/* Setup a counter that is used to call the DOS interrupt as close
+	to it's original frequency as can be achieved given our chosen tick
+	frequency. */
+	sDOSTickCounter = portTICKS_PER_DOS_TICK;
+
+	/* Clean up function if we want to return to DOS. */
+	if( setjmp( xJumpBuf ) != 0 )
+	{
+		prvExitFunction();
+		sSchedulerRunning = pdFALSE;
+	}
+	else
+	{
+		sSchedulerRunning = pdTRUE;
+
+		/* Kick off the scheduler by setting up the context of the first task. */
+		portFIRST_CONTEXT();
+	}
+
+	return sSchedulerRunning;
+}
+/*-----------------------------------------------------------*/
+
+/* The tick ISR used depends on whether the preemptive or cooperative scheduler
+is being used. */
+#if configUSE_PREEMPTION == 1
+	/* Tick service routine used by the scheduler when preemptive scheduling is
+	being used. */
+	static void __interrupt __far prvPreemptiveTick( void )
+	{
+		/* Get the scheduler to update the task states following the tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Switch in the context of the next task to be run. */
+			portSWITCH_CONTEXT();
+		}
+
+		/* Reset the PIC ready for the next time. */
+		prvPortResetPIC();
+	}
+#else
+	static void __interrupt __far prvNonPreemptiveTick( void )
+	{
+		/* Same as preemptive tick, but the cooperative scheduler is being used
+		so we don't have to switch in the context of the next task. */
+		xTaskIncrementTick();
+		prvPortResetPIC();
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+
+static void __interrupt __far prvYieldProcessor( void )
+{
+	/* Switch in the context of the next task to be run. */
+	portSWITCH_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortResetPIC( void )
+{
+	/* We are going to call the DOS tick interrupt at as close a
+	frequency to the normal DOS tick as possible. */
+
+	/* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */
+	--sDOSTickCounter;
+	if( sDOSTickCounter <= 0 )
+	{
+		sDOSTickCounter = ( int16_t ) portTICKS_PER_DOS_TICK;
+		__asm{ int	portSWITCH_INT_NUMBER + 1 };		 
+	}
+	else
+	{
+		/* Reset the PIC as the DOS tick is not being called to
+		do it. */
+		__asm
+		{
+			mov	al, 20H
+			out 20H, al
+		};
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Jump back to the processor state prior to starting the
+	scheduler.  This means we are not going to be using a
+	task stack frame so the task can be deleted. */
+	longjmp( xJumpBuf, 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvExitFunction( void )
+{
+void ( __interrupt __far *pxOriginalTickISR )();
+
+	/* Interrupts should be disabled here anyway - but no 
+	harm in making sure. */
+	portDISABLE_INTERRUPTS();
+	if( sSchedulerRunning == pdTRUE )
+	{
+		/* Set the DOS tick back onto the timer ticker. */
+		pxOriginalTickISR = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
+		_dos_setvect( portTIMER_INT_NUMBER, pxOriginalTickISR );
+		prvSetTickFrequencyDefault();
+
+		/* Put back the switch interrupt routines that was in place
+		before the scheduler started. */
+		_dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
+		_dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 );
+	}
+	/* The tick timer is back how DOS wants it.  We can re-enable
+	interrupts without the scheduler being called. */
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetTickFrequency( uint32_t ulTickRateHz )
+{
+const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
+const uint16_t usPIT0 = ( uint16_t ) 0x40;
+const uint32_t ulPIT_CONST = ( uint32_t ) 1193180;
+const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
+uint32_t ulOutput;
+
+	/* Setup the 8245 to tick at the wanted frequency. */
+	portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
+	ulOutput = ulPIT_CONST / ulTickRateHz;
+   
+	portOUTPUT_BYTE( usPIT0, ( uint16_t )( ulOutput & ( uint32_t ) 0xff ) );
+	ulOutput >>= 8;
+	portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetTickFrequencyDefault( void )
+{
+const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
+const uint16_t usPIT0 = ( uint16_t ) 0x40;
+const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
+
+	portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
+	portOUTPUT_BYTE( usPIT0,0 );
+	portOUTPUT_BYTE( usPIT0,0 );
+}
+
+
+/*lint +e950 */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/oWatcom/16BitDOS/PC/portmacro.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/oWatcom/16BitDOS/PC/portmacro.h
new file mode 100644
index 0000000..5e3af2c
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/oWatcom/16BitDOS/PC/portmacro.h
@@ -0,0 +1,112 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	uint16_t
+#define portBASE_TYPE	short
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section definitions.  portENTER_CRITICAL() must be defined as a
+macro for portable.h to work properly. */
+void portLOCAL_ENTER_CRITICAL( void );
+#pragma aux portLOCAL_ENTER_CRITICAL = 	"pushf" \
+										"cli";
+#define portENTER_CRITICAL() portLOCAL_ENTER_CRITICAL()
+
+void portEXIT_CRITICAL( void );
+#pragma aux portEXIT_CRITICAL	=		"popf";
+
+void portDISABLE_INTERRUPTS( void );
+#pragma aux portDISABLE_INTERRUPTS =	"cli";
+
+void portENABLE_INTERRUPTS( void );
+#pragma aux portENABLE_INTERRUPTS =		"sti";
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH		( -1 )
+#define portSWITCH_INT_NUMBER 	0x80
+#define portYIELD()				__asm{ int portSWITCH_INT_NUMBER }
+#define portDOS_TICK_RATE		( 18.20648 )
+#define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portTICKS_PER_DOS_TICK	( ( uint16_t ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) )
+#define portINITIAL_SW			( ( portSTACK_TYPE ) 0x0202 )	/* Start the tasks with interrupts enabled. */
+#define portBYTE_ALIGNMENT		( 2 )
+/*-----------------------------------------------------------*/
+
+/* Compiler specifics. */
+#define portINPUT_BYTE( xAddr )				inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )	outp( xAddr, ucValue )
+#define portNOP() __asm{ nop }
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* PORTMACRO_H */
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/oWatcom/16BitDOS/common/portasm.h b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/oWatcom/16BitDOS/common/portasm.h
new file mode 100644
index 0000000..864f910
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/oWatcom/16BitDOS/common/portasm.h
@@ -0,0 +1,110 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+extern void vTaskSwitchContext( void );
+
+/* 
+ * Saves the stack pointer for one task into its TCB, calls 
+ * vTaskSwitchContext() to update the TCB being used, then restores the stack 
+ * from the new TCB read to run the task. 
+ */
+void portSWITCH_CONTEXT( void );
+
+/*
+ * Load the stack pointer from the TCB of the task which is going to be first
+ * to execute.  Then force an IRET so the registers and IP are popped off the
+ * stack.
+ */
+void portFIRST_CONTEXT( void );
+
+/* There are slightly different versions depending on whether you are building
+to include debugger information.  If debugger information is used then there
+are a couple of extra bytes left of the ISR stack (presumably for use by the
+debugger).  The true stack pointer is then stored in the bp register.  We add
+2 to the stack pointer to remove the extra bytes before we restore our context. */
+
+#ifdef DEBUG_BUILD
+
+	#pragma aux portSWITCH_CONTEXT =	"mov	ax, seg pxCurrentTCB"														\
+										"mov	ds, ax"																		\
+										"les	bx, pxCurrentTCB"			/* Save the stack pointer into the TCB. */		\
+										"mov	es:0x2[ bx ], ss"															\
+										"mov	es:[ bx ], sp"																\
+										"call	vTaskSwitchContext"			/* Perform the switch. */						\
+										"mov	ax, seg pxCurrentTCB"		/* Restore the stack pointer from the TCB. */	\
+										"mov	ds, ax"																		\
+										"les	bx, dword ptr pxCurrentTCB"													\
+										"mov	ss, es:[ bx + 2 ]"															\
+										"mov	sp, es:[ bx ]"																\
+										"mov	bp, sp"						/* Prepair the bp register for the restoration of the SP in the compiler generated portion of the ISR */	\
+										"add	bp, 0x0002"
+
+										
+
+	#pragma aux portFIRST_CONTEXT =		"mov	ax, seg pxCurrentTCB"			\
+										"mov	ds, ax"							\
+										"les	bx, dword ptr pxCurrentTCB"		\
+										"mov	ss, es:[ bx + 2 ]"				\
+										"mov	sp, es:[ bx ]"					\
+										"add	sp, 0x0002"						/* Remove the extra bytes that exist in debug builds before restoring the context. */ \
+										"pop	ax"								\
+										"pop	ax"								\
+										"pop	es"								\
+										"pop	ds"								\
+										"popa"									\
+										"iret"									
+#else
+
+	#pragma aux portSWITCH_CONTEXT =	"mov	ax, seg pxCurrentTCB"														\
+										"mov	ds, ax"																		\
+										"les	bx, pxCurrentTCB"			/* Save the stack pointer into the TCB. */		\
+										"mov	es:0x2[ bx ], ss"															\
+										"mov	es:[ bx ], sp"																\
+										"call	vTaskSwitchContext"			/* Perform the switch. */						\
+										"mov	ax, seg pxCurrentTCB"		/* Restore the stack pointer from the TCB. */	\
+										"mov	ds, ax"																		\
+										"les	bx, dword ptr pxCurrentTCB"													\
+										"mov	ss, es:[ bx + 2 ]"															\
+										"mov	sp, es:[ bx ]"
+										
+
+	#pragma aux portFIRST_CONTEXT =		"mov	ax, seg pxCurrentTCB"			\
+										"mov	ds, ax"							\
+										"les	bx, dword ptr pxCurrentTCB"		\
+										"mov	ss, es:[ bx + 2 ]"				\
+										"mov	sp, es:[ bx ]"					\
+										"pop	ax"								\
+										"pop	ax"								\
+										"pop	es"								\
+										"pop	ds"								\
+										"popa"									\
+										"iret"									
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/oWatcom/16BitDOS/common/portcomn.c b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/oWatcom/16BitDOS/common/portcomn.c
new file mode 100644
index 0000000..81f8108
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/oWatcom/16BitDOS/common/portcomn.c
@@ -0,0 +1,141 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V1.00:
+	
+	+ pxPortInitialiseStack() now initialises the stack of new tasks to the 
+	  same format used by the compiler.  This allows the compiler generated
+	  interrupt mechanism to be used for context switches.
+
+Changes from V2.4.2:
+
+	+ pvPortMalloc and vPortFree have been removed.  The projects now use
+	  the definitions from the source/portable/MemMang directory.
+
+Changes from V2.6.1:
+
+	+ usPortCheckFreeStackSpace() has been moved to tasks.c.
+*/
+
+	
+
+#include 
+#include "FreeRTOS.h"
+
+/*-----------------------------------------------------------*/
+
+/* See header file for description. */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t DS_Reg = 0, *pxOriginalSP;
+
+	/* Place a few bytes of known values on the bottom of the stack. 
+	This is just useful for debugging. */
+
+	*pxTopOfStack = 0x1111;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2222;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x3333;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x4444;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x5555;
+	pxTopOfStack--;
+
+
+	/*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
+
+	/* We are going to start the scheduler using a return from interrupt
+	instruction to load the program counter, so first there would be the
+	status register and interrupt return address.  We make this the start 
+	of the task. */
+	*pxTopOfStack = portINITIAL_SW; 
+	pxTopOfStack--;
+	*pxTopOfStack = FP_SEG( pxCode );
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pxCode );
+	pxTopOfStack--;
+
+	/* We are going to setup the stack for the new task to look like
+	the stack frame was setup by a compiler generated ISR.  We need to know
+	the address of the existing stack top to place in the SP register within
+	the stack frame.  pxOriginalSP holds SP before (simulated) pusha was 
+	called. */
+	pxOriginalSP = pxTopOfStack;
+
+	/* The remaining registers would be pushed on the stack by our context 
+	switch function.  These are loaded with values simply to make debugging
+	easier. */
+	*pxTopOfStack = FP_OFF( pvParameters );		/* AX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xCCCC;	/* CX */
+	pxTopOfStack--;
+	*pxTopOfStack = FP_SEG( pvParameters );		/* DX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BX */
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pxOriginalSP );		/* SP */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BP */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0123;	/* SI */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xDDDD;	/* DI */
+
+	/* We need the true data segment. */
+	__asm{	MOV DS_Reg, DS };
+
+	pxTopOfStack--;
+	*pxTopOfStack = DS_Reg;	/* DS */
+
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xEEEE;	/* ES */
+
+	/* The AX register is pushed again twice - don't know why. */
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pvParameters );		/* AX */
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pvParameters );		/* AX */
+
+
+	#ifdef DEBUG_BUILD
+		/* The compiler adds space to each ISR stack if building to
+		include debug information.  Presumably this is used by the
+		debugger - we don't need to initialise it to anything just
+		make sure it is there. */
+		pxTopOfStack--;
+	#endif
+
+	/*lint +e950 +e611 +e923 */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/portable/readme.txt b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/readme.txt
new file mode 100644
index 0000000..b22b36b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/portable/readme.txt
@@ -0,0 +1,20 @@
+Each real time kernel port consists of three files that contain the core kernel
+components and are common to every port, and one or more files that are
+specific to a particular microcontroller and/or compiler.
+
+
++ The FreeRTOS/Source/Portable/MemMang directory contains the five sample
+memory allocators as described on the http://www.FreeRTOS.org WEB site.
+
++ The other directories each contain files specific to a particular
+microcontroller or compiler, where the directory name denotes the compiler
+specific files the directory contains.
+
+
+
+For example, if you are interested in the [compiler] port for the [architecture]
+microcontroller, then the port specific files are contained in
+FreeRTOS/Source/Portable/[compiler]/[architecture] directory.  If this is the
+only port you are interested in then all the other directories can be
+ignored.
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/queue.c b/FreeRTOSv10.2.1/FreeRTOS/Source/queue.c
new file mode 100644
index 0000000..6f79c92
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/queue.c
@@ -0,0 +1,2941 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+#if ( configUSE_CO_ROUTINES == 1 )
+	#include "croutine.h"
+#endif
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+
+/* Constants used with the cRxLock and cTxLock structure members. */
+#define queueUNLOCKED					( ( int8_t ) -1 )
+#define queueLOCKED_UNMODIFIED			( ( int8_t ) 0 )
+
+/* When the Queue_t structure is used to represent a base queue its pcHead and
+pcTail members are used as pointers into the queue storage area.  When the
+Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
+not necessary, and the pcHead pointer is set to NULL to indicate that the
+structure instead holds a pointer to the mutex holder (if any).  Map alternative
+names to the pcHead and structure member to ensure the readability of the code
+is maintained.  The QueuePointers_t and SemaphoreData_t types are used to form
+a union as their usage is mutually exclusive dependent on what the queue is
+being used for. */
+#define uxQueueType						pcHead
+#define queueQUEUE_IS_MUTEX				NULL
+
+typedef struct QueuePointers
+{
+	int8_t *pcTail;					/*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
+	int8_t *pcReadFrom;				/*< Points to the last place that a queued item was read from when the structure is used as a queue. */
+} QueuePointers_t;
+
+typedef struct SemaphoreData
+{
+	TaskHandle_t xMutexHolder;		 /*< The handle of the task that holds the mutex. */
+	UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
+} SemaphoreData_t;
+
+/* Semaphores do not actually store or copy data, so have an item size of
+zero. */
+#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )
+#define queueMUTEX_GIVE_BLOCK_TIME		 ( ( TickType_t ) 0U )
+
+#if( configUSE_PREEMPTION == 0 )
+	/* If the cooperative scheduler is being used then a yield should not be
+	performed just because a higher priority task has been woken. */
+	#define queueYIELD_IF_USING_PREEMPTION()
+#else
+	#define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/*
+ * Definition of the queue used by the scheduler.
+ * Items are queued by copy, not reference.  See the following link for the
+ * rationale: https://www.freertos.org/Embedded-RTOS-Queues.html
+ */
+typedef struct QueueDefinition 		/* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	int8_t *pcHead;					/*< Points to the beginning of the queue storage area. */
+	int8_t *pcWriteTo;				/*< Points to the free next place in the storage area. */
+
+	union
+	{
+		QueuePointers_t xQueue;		/*< Data required exclusively when this structure is used as a queue. */
+		SemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */
+	} u;
+
+	List_t xTasksWaitingToSend;		/*< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */
+	List_t xTasksWaitingToReceive;	/*< List of tasks that are blocked waiting to read from this queue.  Stored in priority order. */
+
+	volatile UBaseType_t uxMessagesWaiting;/*< The number of items currently in the queue. */
+	UBaseType_t uxLength;			/*< The length of the queue defined as the number of items it will hold, not the number of bytes. */
+	UBaseType_t uxItemSize;			/*< The size of each items that the queue will hold. */
+
+	volatile int8_t cRxLock;		/*< Stores the number of items received from the queue (removed from the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+	volatile int8_t cTxLock;		/*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t ucStaticallyAllocated;	/*< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+
+	#if ( configUSE_QUEUE_SETS == 1 )
+		struct QueueDefinition *pxQueueSetContainer;
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxQueueNumber;
+		uint8_t ucQueueType;
+	#endif
+
+} xQUEUE;
+
+/* The old xQUEUE name is maintained above then typedefed to the new Queue_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xQUEUE Queue_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The queue registry is just a means for kernel aware debuggers to locate
+ * queue structures.  It has no other purpose so is an optional component.
+ */
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	/* The type stored within the queue registry array.  This allows a name
+	to be assigned to each queue making kernel aware debugging a little
+	more user friendly. */
+	typedef struct QUEUE_REGISTRY_ITEM
+	{
+		const char *pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+		QueueHandle_t xHandle;
+	} xQueueRegistryItem;
+
+	/* The old xQueueRegistryItem name is maintained above then typedefed to the
+	new xQueueRegistryItem name below to enable the use of older kernel aware
+	debuggers. */
+	typedef xQueueRegistryItem QueueRegistryItem_t;
+
+	/* The queue registry is simply an array of QueueRegistryItem_t structures.
+	The pcQueueName member of a structure being NULL is indicative of the
+	array position being vacant. */
+	PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+
+/*
+ * Unlocks a queue locked by a call to prvLockQueue.  Locking a queue does not
+ * prevent an ISR from adding or removing items to the queue, but does prevent
+ * an ISR from removing tasks from the queue event lists.  If an ISR finds a
+ * queue is locked it will instead increment the appropriate queue lock count
+ * to indicate that a task may require unblocking.  When the queue in unlocked
+ * these lock counts are inspected, and the appropriate action taken.
+ */
+static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any data in a queue.
+ *
+ * @return pdTRUE if the queue contains no items, otherwise pdFALSE.
+ */
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any space in a queue.
+ *
+ * @return pdTRUE if there is no space, otherwise pdFALSE;
+ */
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item into the queue, either at the front of the queue or the
+ * back of the queue.
+ */
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item out of a queue.
+ */
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_QUEUE_SETS == 1 )
+	/*
+	 * Checks to see if a queue is a member of a queue set, and if so, notifies
+	 * the queue set that the queue contains data.
+	 */
+	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Called after a Queue_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Mutexes are a special type of queue.  When a mutex is created, first the
+ * queue is created, then prvInitialiseMutex() is called to configure the queue
+ * as a mutex.
+ */
+#if( configUSE_MUTEXES == 1 )
+	static void prvInitialiseMutex( Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+#if( configUSE_MUTEXES == 1 )
+	/*
+	 * If a task waiting for a mutex causes the mutex holder to inherit a
+	 * priority, but the waiting task times out, then the holder should
+	 * disinherit the priority - but only down to the highest priority of any
+	 * other tasks that are waiting for the same mutex.  This function returns
+	 * that priority.
+	 */
+	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to mark a queue as locked.  Locking a queue prevents an ISR from
+ * accessing the queue event lists.
+ */
+#define prvLockQueue( pxQueue )								\
+	taskENTER_CRITICAL();									\
+	{														\
+		if( ( pxQueue )->cRxLock == queueUNLOCKED )			\
+		{													\
+			( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED;	\
+		}													\
+		if( ( pxQueue )->cTxLock == queueUNLOCKED )			\
+		{													\
+			( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED;	\
+		}													\
+	}														\
+	taskEXIT_CRITICAL()
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
+{
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+
+	taskENTER_CRITICAL();
+	{
+		pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+		pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
+		pxQueue->pcWriteTo = pxQueue->pcHead;
+		pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+		pxQueue->cRxLock = queueUNLOCKED;
+		pxQueue->cTxLock = queueUNLOCKED;
+
+		if( xNewQueue == pdFALSE )
+		{
+			/* If there are tasks blocked waiting to read from the queue, then
+			the tasks will remain blocked as after this function exits the queue
+			will still be empty.  If there are tasks blocked waiting to write to
+			the queue, then one should be unblocked as after this function exits
+			it will be possible to write to it. */
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+				{
+					queueYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			/* Ensure the event queues start in the correct state. */
+			vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
+			vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	/* A value is returned for calling semantic consistency with previous
+	versions. */
+	return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+		/* The StaticQueue_t structure and the queue storage area must be
+		supplied. */
+		configASSERT( pxStaticQueue != NULL );
+
+		/* A queue storage area should be provided if the item size is not 0, and
+		should not be provided if the item size is 0. */
+		configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
+		configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticQueue_t or StaticSemaphore_t equals the size of
+			the real queue and semaphore structures. */
+			volatile size_t xSize = sizeof( StaticQueue_t );
+			configASSERT( xSize == sizeof( Queue_t ) );
+			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+		/* The address of a statically allocated queue was passed in, use it.
+		The address of a statically allocated storage area was also passed in
+		but is already set. */
+		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+
+		if( pxNewQueue != NULL )
+		{
+			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+			{
+				/* Queues can be allocated wither statically or dynamically, so
+				note this queue was allocated statically in case the queue is
+				later deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdTRUE;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+		}
+		else
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxNewQueue;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+	size_t xQueueSizeInBytes;
+	uint8_t *pucQueueStorage;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+		if( uxItemSize == ( UBaseType_t ) 0 )
+		{
+			/* There is not going to be a queue storage area. */
+			xQueueSizeInBytes = ( size_t ) 0;
+		}
+		else
+		{
+			/* Allocate enough space to hold the maximum number of items that
+			can be in the queue at any time. */
+			xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+		}
+
+		/* Allocate the queue and storage area.  Justification for MISRA
+		deviation as follows:  pvPortMalloc() always ensures returned memory
+		blocks are aligned per the requirements of the MCU stack.  In this case
+		pvPortMalloc() must return a pointer that is guaranteed to meet the
+		alignment requirements of the Queue_t structure - which in this case
+		is an int8_t *.  Therefore, whenever the stack alignment requirements
+		are greater than or equal to the pointer to char requirements the cast
+		is safe.  In other cases alignment requirements are not strict (one or
+		two bytes). */
+		pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
+
+		if( pxNewQueue != NULL )
+		{
+			/* Jump past the queue structure to find the location of the queue
+			storage area. */
+			pucQueueStorage = ( uint8_t * ) pxNewQueue;
+			pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* Queues can be created either statically or dynamically, so
+				note this task was created dynamically in case it is later
+				deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdFALSE;
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+		}
+		else
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxNewQueue;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
+{
+	/* Remove compiler warnings about unused parameters should
+	configUSE_TRACE_FACILITY not be set to 1. */
+	( void ) ucQueueType;
+
+	if( uxItemSize == ( UBaseType_t ) 0 )
+	{
+		/* No RAM was allocated for the queue storage area, but PC head cannot
+		be set to NULL because NULL is used as a key to say the queue is used as
+		a mutex.  Therefore just set pcHead to point to the queue as a benign
+		value that is known to be within the memory map. */
+		pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
+	}
+	else
+	{
+		/* Set the head to the start of the queue storage area. */
+		pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
+	}
+
+	/* Initialise the queue members as described where the queue type is
+	defined. */
+	pxNewQueue->uxLength = uxQueueLength;
+	pxNewQueue->uxItemSize = uxItemSize;
+	( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+	{
+		pxNewQueue->ucQueueType = ucQueueType;
+	}
+	#endif /* configUSE_TRACE_FACILITY */
+
+	#if( configUSE_QUEUE_SETS == 1 )
+	{
+		pxNewQueue->pxQueueSetContainer = NULL;
+	}
+	#endif /* configUSE_QUEUE_SETS */
+
+	traceQUEUE_CREATE( pxNewQueue );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+	static void prvInitialiseMutex( Queue_t *pxNewQueue )
+	{
+		if( pxNewQueue != NULL )
+		{
+			/* The queue create function will set all the queue structure members
+			correctly for a generic queue, but this function is creating a
+			mutex.  Overwrite those members that need to be set differently -
+			in particular the information required for priority inheritance. */
+			pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
+			pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
+
+			/* In case this is a recursive mutex. */
+			pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
+
+			traceCREATE_MUTEX( pxNewQueue );
+
+			/* Start with the semaphore in the expected state. */
+			( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
+		}
+		else
+		{
+			traceCREATE_MUTEX_FAILED();
+		}
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
+	{
+	QueueHandle_t xNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+		xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
+		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+
+		return xNewQueue;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
+	{
+	QueueHandle_t xNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+		/* Prevent compiler warnings about unused parameters if
+		configUSE_TRACE_FACILITY does not equal 1. */
+		( void ) ucQueueType;
+
+		xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
+		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+
+		return xNewQueue;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+	TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore )
+	{
+	TaskHandle_t pxReturn;
+	Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore;
+
+		/* This function is called by xSemaphoreGetMutexHolder(), and should not
+		be called directly.  Note:  This is a good way of determining if the
+		calling task is the mutex holder, but not a good way of determining the
+		identity of the mutex holder, as the holder may change between the
+		following critical section exiting and the function returning. */
+		taskENTER_CRITICAL();
+		{
+			if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX )
+			{
+				pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder;
+			}
+			else
+			{
+				pxReturn = NULL;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return pxReturn;
+	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+	TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )
+	{
+	TaskHandle_t pxReturn;
+
+		configASSERT( xSemaphore );
+
+		/* Mutexes cannot be used in interrupt service routines, so the mutex
+		holder should not change in an ISR, and therefore a critical section is
+		not required here. */
+		if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
+		{
+			pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder;
+		}
+		else
+		{
+			pxReturn = NULL;
+		}
+
+		return pxReturn;
+	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+	BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+		configASSERT( pxMutex );
+
+		/* If this is the task that holds the mutex then xMutexHolder will not
+		change outside of this task.  If this task does not hold the mutex then
+		pxMutexHolder can never coincidentally equal the tasks handle, and as
+		this is the only condition we are interested in it does not matter if
+		pxMutexHolder is accessed simultaneously by another task.  Therefore no
+		mutual exclusion is required to test the pxMutexHolder variable. */
+		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
+		{
+			traceGIVE_MUTEX_RECURSIVE( pxMutex );
+
+			/* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to
+			the task handle, therefore no underflow check is required.  Also,
+			uxRecursiveCallCount is only modified by the mutex holder, and as
+			there can only be one, no mutual exclusion is required to modify the
+			uxRecursiveCallCount member. */
+			( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;
+
+			/* Has the recursive call count unwound to 0? */
+			if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )
+			{
+				/* Return the mutex.  This will automatically unblock any other
+				task that might be waiting to access the mutex. */
+				( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			/* The mutex cannot be given because the calling task is not the
+			holder. */
+			xReturn = pdFAIL;
+
+			traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+	BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+		configASSERT( pxMutex );
+
+		/* Comments regarding mutual exclusion as per those within
+		xQueueGiveMutexRecursive(). */
+
+		traceTAKE_MUTEX_RECURSIVE( pxMutex );
+
+		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
+		{
+			( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );
+
+			/* pdPASS will only be returned if the mutex was successfully
+			obtained.  The calling task may have entered the Blocked state
+			before reaching here. */
+			if( xReturn != pdFAIL )
+			{
+				( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+			}
+			else
+			{
+				traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue )
+	{
+	QueueHandle_t xHandle;
+
+		configASSERT( uxMaxCount != 0 );
+		configASSERT( uxInitialCount <= uxMaxCount );
+
+		xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+		if( xHandle != NULL )
+		{
+			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+			traceCREATE_COUNTING_SEMAPHORE();
+		}
+		else
+		{
+			traceCREATE_COUNTING_SEMAPHORE_FAILED();
+		}
+
+		return xHandle;
+	}
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )
+	{
+	QueueHandle_t xHandle;
+
+		configASSERT( uxMaxCount != 0 );
+		configASSERT( uxInitialCount <= uxMaxCount );
+
+		xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+		if( xHandle != NULL )
+		{
+			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+			traceCREATE_COUNTING_SEMAPHORE();
+		}
+		else
+		{
+			traceCREATE_COUNTING_SEMAPHORE_FAILED();
+		}
+
+		return xHandle;
+	}
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
+{
+BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904 This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Is there room on the queue now?  The running task must be the
+			highest priority task wanting to access the queue.  If the head item
+			in the queue is to be overwritten then it does not matter if the
+			queue is full. */
+			if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+			{
+				traceQUEUE_SEND( pxQueue );
+
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+				UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
+						{
+							/* Do not notify the queue set as an existing item
+							was overwritten in the queue so the number of items
+							in the queue has not changed. */
+							mtCOVERAGE_TEST_MARKER();
+						}
+						else if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )
+						{
+							/* The queue is a member of a queue set, and posting
+							to the queue set caused a higher priority task to
+							unblock. A context switch is required. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						/* If there was a task waiting for data to arrive on the
+						queue then unblock it now. */
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The unblocked task has a priority higher than
+								our own so yield immediately.  Yes it is ok to
+								do this from within the critical section - the
+								kernel takes care of that. */
+								queueYIELD_IF_USING_PREEMPTION();
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else if( xYieldRequired != pdFALSE )
+						{
+							/* This path is a special case that will only get
+							executed if the task was holding multiple mutexes
+							and the mutexes were given back in an order that is
+							different to that in which they were taken. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+					/* If there was a task waiting for data to arrive on the
+					queue then unblock it now. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The unblocked task has a priority higher than
+							our own so yield immediately.  Yes it is ok to do
+							this from within the critical section - the kernel
+							takes care of that. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else if( xYieldRequired != pdFALSE )
+					{
+						/* This path is a special case that will only get
+						executed if the task was holding multiple mutexes and
+						the mutexes were given back in an order that is
+						different to that in which they were taken. */
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was full and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+
+					/* Return to the original privilege level before exiting
+					the function. */
+					traceQUEUE_SEND_FAILED( pxQueue );
+					return errQUEUE_FULL;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was full and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_SEND( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
+
+				/* Unlocking the queue means queue events can effect the
+				event list.  It is possible that interrupts occurring now
+				remove this task from the event list again - but as the
+				scheduler is suspended the task will go onto the pending
+				ready last instead of the actual ready list. */
+				prvUnlockQueue( pxQueue );
+
+				/* Resuming the scheduler will move tasks from the pending
+				ready list into the ready list - so it is feasible that this
+				task is already in a ready list before it yields - in which
+				case the yield will not cause a context switch unless there
+				is also a higher priority task in the pending ready list. */
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+			}
+			else
+			{
+				/* Try again. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* The timeout has expired. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			traceQUEUE_SEND_FAILED( pxQueue );
+			return errQUEUE_FULL;
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	/* Similar to xQueueGenericSend, except without blocking if there is no room
+	in the queue.  Also don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+
+			traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+			/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
+			semaphore or mutex.  That means prvCopyDataToQueue() cannot result
+			in a task disinheriting a priority and prvCopyDataToQueue() can be
+			called here even though the disinherit function does not check if
+			the scheduler is suspended before accessing the ready lists. */
+			( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+			{
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )
+						{
+							/* The queue is a member of a queue set, and posting
+							to the queue set caused a higher priority task to
+							unblock.  A context switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The task waiting has a higher priority so
+								record that a context switch is required. */
+								if( pxHigherPriorityTaskWoken != NULL )
+								{
+									*pxHigherPriorityTaskWoken = pdTRUE;
+								}
+								else
+								{
+									mtCOVERAGE_TEST_MARKER();
+								}
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	/* Similar to xQueueGenericSendFromISR() but used with semaphores where the
+	item size is 0.  Don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+
+	configASSERT( pxQueue );
+
+	/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
+	if the item size is not 0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+
+	/* Normally a mutex would not be given from an interrupt, especially if
+	there is a mutex holder, as priority inheritance makes no sense for an
+	interrupts, only tasks. */
+	configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+		/* When the queue is used to implement a semaphore no data is ever
+		moved through the queue but it is still valid to see if the queue 'has
+		space'. */
+		if( uxMessagesWaiting < pxQueue->uxLength )
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+
+			traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+			/* A task can only have an inherited priority if it is a mutex
+			holder - and if there is a mutex holder then the mutex cannot be
+			given from an ISR.  As this is the ISR version of the function it
+			can be assumed there is no mutex holder and no need to determine if
+			priority disinheritance is needed.  Simply increase the count of
+			messages (semaphores) available. */
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+			{
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) != pdFALSE )
+						{
+							/* The semaphore is a member of a queue set, and
+							posting	to the queue set caused a higher priority
+							task to	unblock.  A context switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The task waiting has a higher priority so
+								record that a context switch is required. */
+								if( pxHigherPriorityTaskWoken != NULL )
+								{
+									*pxHigherPriorityTaskWoken = pdTRUE;
+								}
+								else
+								{
+									mtCOVERAGE_TEST_MARKER();
+								}
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904  This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Data available, remove one item. */
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+				traceQUEUE_RECEIVE( pxQueue );
+				pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+				/* There is now space in the queue, were any tasks waiting to
+				post to the queue?  If so, unblock the highest priority waiting
+				task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* The timeout has not expired.  If the queue is still empty place
+			the task on the list of tasks waiting to receive from the queue. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* The queue contains data again.  Loop back to try and read the
+				data. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* Timed out.  If there is no data in the queue exit, otherwise loop
+			back and attempt to read the data. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+#if( configUSE_MUTEXES == 1 )
+	BaseType_t xInheritanceOccurred = pdFALSE;
+#endif
+
+	/* Check the queue pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* Check this really is a semaphore, in which case the item size will be
+	0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
+	statements within the function itself.  This is done in the interest
+	of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Semaphores are queues with an item size of 0, and where the
+			number of messages in the queue is the semaphore's count value. */
+			const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxSemaphoreCount > ( UBaseType_t ) 0 )
+			{
+				traceQUEUE_RECEIVE( pxQueue );
+
+				/* Semaphores are queues with a data size of zero and where the
+				messages waiting is the semaphore's count.  Reduce the count. */
+				pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+					{
+						/* Record the information required to implement
+						priority inheritance should it become necessary. */
+						pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_MUTEXES */
+
+				/* Check to see if other tasks are blocked waiting to give the
+				semaphore, and if so, unblock the highest priority such task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* For inheritance to have occurred there must have been an
+					initial timeout, and an adjusted timeout cannot become 0, as
+					if it were 0 the function would have exited. */
+					#if( configUSE_MUTEXES == 1 )
+					{
+						configASSERT( xInheritanceOccurred == pdFALSE );
+					}
+					#endif /* configUSE_MUTEXES */
+
+					/* The semaphore count was 0 and no block time is specified
+					(or the block time has expired) so exit now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The semaphore count was 0 and a block time was specified
+					so configure the timeout structure ready to block. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can give to and take from the semaphore
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* A block time is specified and not expired.  If the semaphore
+			count is 0 then enter the Blocked state to wait for a semaphore to
+			become available.  As semaphores are implemented with queues the
+			queue being empty is equivalent to the semaphore count being 0. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+					{
+						taskENTER_CRITICAL();
+						{
+							xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
+						}
+						taskEXIT_CRITICAL();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif
+
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* There was no timeout and the semaphore count was not 0, so
+				attempt to take the semaphore again. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* Timed out. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			/* If the semaphore count is 0 exit now as the timeout has
+			expired.  Otherwise return to attempt to take the semaphore that is
+			known to be available.  As semaphores are implemented by queues the
+			queue being empty is equivalent to the semaphore count being 0. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					/* xInheritanceOccurred could only have be set if
+					pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
+					test the mutex type again to check it is actually a mutex. */
+					if( xInheritanceOccurred != pdFALSE )
+					{
+						taskENTER_CRITICAL();
+						{
+							UBaseType_t uxHighestWaitingPriority;
+
+							/* This task blocking on the mutex caused another
+							task to inherit this task's priority.  Now this task
+							has timed out the priority should be disinherited
+							again, but only as low as the next highest priority
+							task that is waiting for the same mutex. */
+							uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
+							vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
+						}
+						taskEXIT_CRITICAL();
+					}
+				}
+				#endif /* configUSE_MUTEXES */
+
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = xQueue;
+
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904  This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Remember the read position so it can be reset after the data
+				is read from the queue as this function is only peeking the
+				data, not removing it. */
+				pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
+
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+				traceQUEUE_PEEK( pxQueue );
+
+				/* The data is not being removed, so reset the read pointer. */
+				pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
+
+				/* The data is being left in the queue, so see if there are
+				any other tasks waiting for the data. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority than this task. */
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_PEEK_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure ready to enter the blocked
+					state. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* Timeout has not expired yet, check to see if there is data in the
+			queue now, and if not enter the Blocked state to wait for data. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_PEEK( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* There is data in the queue now, so don't enter the blocked
+				state, instead return to try and obtain the data. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* The timeout has expired.  If there is still no data in the queue
+			exit, otherwise go back and try to read the data again. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceQUEUE_PEEK_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+		/* Cannot block in an ISR, so check there is data available. */
+		if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			const int8_t cRxLock = pxQueue->cRxLock;
+
+			traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
+
+			prvCopyDataFromQueue( pxQueue, pvBuffer );
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+			/* If the queue is locked the event list will not be modified.
+			Instead update the lock count so the task that unlocks the queue
+			will know that an ISR has removed data while the queue was
+			locked. */
+			if( cRxLock == queueUNLOCKED )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority than us so
+						force a context switch. */
+						if( pxHigherPriorityTaskWoken != NULL )
+						{
+							*pxHigherPriorityTaskWoken = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was removed while it was locked. */
+				pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,  void * const pvBuffer )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Cannot block in an ISR, so check there is data available. */
+		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			traceQUEUE_PEEK_FROM_ISR( pxQueue );
+
+			/* Remember the read position so it can be reset as nothing is
+			actually being removed from the queue. */
+			pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
+			prvCopyDataFromQueue( pxQueue, pvBuffer );
+			pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+
+	configASSERT( xQueue );
+
+	taskENTER_CRITICAL();
+	{
+		uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+
+	taskENTER_CRITICAL();
+	{
+		uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	uxReturn = pxQueue->uxMessagesWaiting;
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+void vQueueDelete( QueueHandle_t xQueue )
+{
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	traceQUEUE_DELETE( pxQueue );
+
+	#if ( configQUEUE_REGISTRY_SIZE > 0 )
+	{
+		vQueueUnregisterQueue( pxQueue );
+	}
+	#endif
+
+	#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+	{
+		/* The queue can only have been allocated dynamically - free it
+		again. */
+		vPortFree( pxQueue );
+	}
+	#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	{
+		/* The queue could have been allocated statically or dynamically, so
+		check before attempting to free the memory. */
+		if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+		{
+			vPortFree( pxQueue );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#else
+	{
+		/* The queue must have been statically allocated, so is not going to be
+		deleted.  Avoid compiler warnings about the unused parameter. */
+		( void ) pxQueue;
+	}
+	#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )
+	{
+		return ( ( Queue_t * ) xQueue )->uxQueueNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber )
+	{
+		( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )
+	{
+		return ( ( Queue_t * ) xQueue )->ucQueueType;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
+	{
+	UBaseType_t uxHighestPriorityOfWaitingTasks;
+
+		/* If a task waiting for a mutex causes the mutex holder to inherit a
+		priority, but the waiting task times out, then the holder should
+		disinherit the priority - but only down to the highest priority of any
+		other tasks that are waiting for the same mutex.  For this purpose,
+		return the priority of the highest priority task that is waiting for the
+		mutex. */
+		if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
+		{
+			uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
+		}
+		else
+		{
+			uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
+		}
+
+		return uxHighestPriorityOfWaitingTasks;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
+{
+BaseType_t xReturn = pdFALSE;
+UBaseType_t uxMessagesWaiting;
+
+	/* This function is called from a critical section. */
+
+	uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+	if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
+	{
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+			{
+				/* The mutex is no longer being held. */
+				xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
+				pxQueue->u.xSemaphore.xMutexHolder = NULL;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_MUTEXES */
+	}
+	else if( xPosition == queueSEND_TO_BACK )
+	{
+		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+		pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+		if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		{
+			pxQueue->pcWriteTo = pxQueue->pcHead;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */
+		pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
+		if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		{
+			pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( xPosition == queueOVERWRITE )
+		{
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* An item is not being added but overwritten, so subtract
+				one from the recorded number of items in the queue so when
+				one is added again below the number of recorded items remains
+				correct. */
+				--uxMessagesWaiting;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
+{
+	if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
+	{
+		pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+		if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
+		{
+			pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvUnlockQueue( Queue_t * const pxQueue )
+{
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */
+
+	/* The lock counts contains the number of extra data items placed or
+	removed from the queue while the queue was locked.  When a queue is
+	locked items can be added or removed, but the event lists cannot be
+	updated. */
+	taskENTER_CRITICAL();
+	{
+		int8_t cTxLock = pxQueue->cTxLock;
+
+		/* See if data was added to the queue while it was locked. */
+		while( cTxLock > queueLOCKED_UNMODIFIED )
+		{
+			/* Data was posted while the queue was locked.  Are any tasks
+			blocked waiting for data to become available? */
+			#if ( configUSE_QUEUE_SETS == 1 )
+			{
+				if( pxQueue->pxQueueSetContainer != NULL )
+				{
+					if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) != pdFALSE )
+					{
+						/* The queue is a member of a queue set, and posting to
+						the queue set caused a higher priority task to unblock.
+						A context switch is required. */
+						vTaskMissedYield();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					/* Tasks that are removed from the event list will get
+					added to the pending ready list as the scheduler is still
+					suspended. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							vTaskMissedYield();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						break;
+					}
+				}
+			}
+			#else /* configUSE_QUEUE_SETS */
+			{
+				/* Tasks that are removed from the event list will get added to
+				the pending ready list as the scheduler is still suspended. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority so record that
+						a context switch is required. */
+						vTaskMissedYield();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					break;
+				}
+			}
+			#endif /* configUSE_QUEUE_SETS */
+
+			--cTxLock;
+		}
+
+		pxQueue->cTxLock = queueUNLOCKED;
+	}
+	taskEXIT_CRITICAL();
+
+	/* Do the same for the Rx lock. */
+	taskENTER_CRITICAL();
+	{
+		int8_t cRxLock = pxQueue->cRxLock;
+
+		while( cRxLock > queueLOCKED_UNMODIFIED )
+		{
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+				{
+					vTaskMissedYield();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				--cRxLock;
+			}
+			else
+			{
+				break;
+			}
+		}
+
+		pxQueue->cRxLock = queueUNLOCKED;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+	{
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )
+		{
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+	{
+		if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+		{
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* If the queue is already full we may have to block.  A critical section
+		is required to prevent an interrupt removing something from the queue
+		between the check to see if the queue is full and blocking on the queue. */
+		portDISABLE_INTERRUPTS();
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+			{
+				/* The queue is full - do we want to block or just leave without
+				posting? */
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					/* As this is called from a coroutine we cannot block directly, but
+					return indicating that we need to block. */
+					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );
+					portENABLE_INTERRUPTS();
+					return errQUEUE_BLOCKED;
+				}
+				else
+				{
+					portENABLE_INTERRUPTS();
+					return errQUEUE_FULL;
+				}
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+			{
+				/* There is room in the queue, copy the data into the queue. */
+				prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+				xReturn = pdPASS;
+
+				/* Were any co-routines waiting for data to become available? */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					/* In this instance the co-routine could be placed directly
+					into the ready list as we are within a critical section.
+					Instead the same pending ready list mechanism is used as if
+					the event were caused from within an interrupt. */
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The co-routine waiting has a higher priority so record
+						that a yield might be appropriate. */
+						xReturn = errQUEUE_YIELD;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				xReturn = errQUEUE_FULL;
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* If the queue is already empty we may have to block.  A critical section
+		is required to prevent an interrupt adding something to the queue
+		between the check to see if the queue is empty and blocking on the queue. */
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+			{
+				/* There are no messages in the queue, do we want to block or just
+				leave with nothing? */
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					/* As this is a co-routine we cannot block directly, but return
+					indicating that we need to block. */
+					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );
+					portENABLE_INTERRUPTS();
+					return errQUEUE_BLOCKED;
+				}
+				else
+				{
+					portENABLE_INTERRUPTS();
+					return errQUEUE_FULL;
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Data is available from the queue. */
+				pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+				if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
+				{
+					pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+				--( pxQueue->uxMessagesWaiting );
+				( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+				xReturn = pdPASS;
+
+				/* Were any co-routines waiting for space to become available? */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					/* In this instance the co-routine could be placed directly
+					into the ready list as we are within a critical section.
+					Instead the same pending ready list mechanism is used as if
+					the event were caused from within an interrupt. */
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						xReturn = errQUEUE_YIELD;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )
+	{
+	Queue_t * const pxQueue = xQueue;
+
+		/* Cannot block within an ISR so if there is no space on the queue then
+		exit without doing anything. */
+		if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+		{
+			prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+
+			/* We only want to wake one co-routine per ISR, so check that a
+			co-routine has not already been woken. */
+			if( xCoRoutinePreviouslyWoken == pdFALSE )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						return pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xCoRoutinePreviouslyWoken;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* We cannot block from an ISR, so check there is data available. If
+		not then just leave without doing anything. */
+		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			/* Copy the data from the queue. */
+			pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+			if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
+			{
+				pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+			--( pxQueue->uxMessagesWaiting );
+			( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+			if( ( *pxCoRoutineWoken ) == pdFALSE )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						*pxCoRoutineWoken = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t ux;
+
+		/* See if there is an empty space in the registry.  A NULL name denotes
+		a free slot. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].pcQueueName == NULL )
+			{
+				/* Store the information on this queue. */
+				xQueueRegistry[ ux ].pcQueueName = pcQueueName;
+				xQueueRegistry[ ux ].xHandle = xQueue;
+
+				traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	const char *pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t ux;
+	const char *pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+		/* Note there is nothing here to protect against another task adding or
+		removing entries from the registry while it is being searched. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].xHandle == xQueue )
+			{
+				pcReturn = xQueueRegistry[ ux ].pcQueueName;
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		return pcReturn;
+	} /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueUnregisterQueue( QueueHandle_t xQueue )
+	{
+	UBaseType_t ux;
+
+		/* See if the handle of the queue being unregistered in actually in the
+		registry. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].xHandle == xQueue )
+			{
+				/* Set the name to NULL to show that this slot if free again. */
+				xQueueRegistry[ ux ].pcQueueName = NULL;
+
+				/* Set the handle to NULL to ensure the same queue handle cannot
+				appear in the registry twice if it is added, removed, then
+				added again. */
+				xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+	} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+	void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+	Queue_t * const pxQueue = xQueue;
+
+		/* This function should not be called by application code hence the
+		'Restricted' in its name.  It is not part of the public API.  It is
+		designed for use by kernel code, and has special calling requirements.
+		It can result in vListInsert() being called on a list that can only
+		possibly ever have one item in it, so the list will be fast, but even
+		so it should be called with the scheduler locked and not from a critical
+		section. */
+
+		/* Only do anything if there are no messages in the queue.  This function
+		will not actually cause the task to block, just place it on a blocked
+		list.  It will not block until the scheduler is unlocked - at which
+		time a yield will be performed.  If an item is added to the queue while
+		the queue is locked, and the calling task blocks on the queue, then the
+		calling task will be immediately unblocked when the queue is unlocked. */
+		prvLockQueue( pxQueue );
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
+		{
+			/* There is nothing in the queue, block for the specified period. */
+			vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		prvUnlockQueue( pxQueue );
+	}
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )
+	{
+	QueueSetHandle_t pxQueue;
+
+		pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET );
+
+		return pxQueue;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	{
+	BaseType_t xReturn;
+
+		taskENTER_CRITICAL();
+		{
+			if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )
+			{
+				/* Cannot add a queue/semaphore to more than one queue set. */
+				xReturn = pdFAIL;
+			}
+			else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )
+			{
+				/* Cannot add a queue/semaphore to a queue set if there are already
+				items in the queue/semaphore. */
+				xReturn = pdFAIL;
+			}
+			else
+			{
+				( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;
+				xReturn = pdPASS;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;
+
+		if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )
+		{
+			/* The queue was not a member of the set. */
+			xReturn = pdFAIL;
+		}
+		else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )
+		{
+			/* It is dangerous to remove a queue from a set when the queue is
+			not empty because the queue set will still hold pending events for
+			the queue. */
+			xReturn = pdFAIL;
+		}
+		else
+		{
+			taskENTER_CRITICAL();
+			{
+				/* The queue is no longer contained in the set. */
+				pxQueueOrSemaphore->pxQueueSetContainer = NULL;
+			}
+			taskEXIT_CRITICAL();
+			xReturn = pdPASS;
+		}
+
+		return xReturn;
+	} /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t const xTicksToWait )
+	{
+	QueueSetMemberHandle_t xReturn = NULL;
+
+		( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )
+	{
+	QueueSetMemberHandle_t xReturn = NULL;
+
+		( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition )
+	{
+	Queue_t *pxQueueSetContainer = pxQueue->pxQueueSetContainer;
+	BaseType_t xReturn = pdFALSE;
+
+		/* This function must be called form a critical section. */
+
+		configASSERT( pxQueueSetContainer );
+		configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );
+
+		if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )
+		{
+			const int8_t cTxLock = pxQueueSetContainer->cTxLock;
+
+			traceQUEUE_SEND( pxQueueSetContainer );
+
+			/* The data copied is the handle of the queue that contains data. */
+			xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, xCopyPosition );
+
+			if( cTxLock == queueUNLOCKED )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority. */
+						xReturn = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				pxQueueSetContainer->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/readme.txt b/FreeRTOSv10.2.1/FreeRTOS/Source/readme.txt
new file mode 100644
index 0000000..81518ec
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/readme.txt
@@ -0,0 +1,17 @@
+Each real time kernel port consists of three files that contain the core kernel
+components and are common to every port, and one or more files that are 
+specific to a particular microcontroller and or compiler.
+
++ The FreeRTOS/Source directory contains the three files that are common to 
+every port - list.c, queue.c and tasks.c.  The kernel is contained within these 
+three files.  croutine.c implements the optional co-routine functionality - which
+is normally only used on very memory limited systems.
+
++ The FreeRTOS/Source/Portable directory contains the files that are specific to 
+a particular microcontroller and or compiler.
+
++ The FreeRTOS/Source/include directory contains the real time kernel header 
+files.
+
+See the readme file in the FreeRTOS/Source/Portable directory for more 
+information.
\ No newline at end of file
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/stream_buffer.c b/FreeRTOSv10.2.1/FreeRTOS/Source/stream_buffer.c
new file mode 100644
index 0000000..8cda238
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/stream_buffer.c
@@ -0,0 +1,1263 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "stream_buffer.h"
+
+#if( configUSE_TASK_NOTIFICATIONS != 1 )
+	#error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
+#endif
+
+/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+/* If the user has not provided application specific Rx notification macros,
+or #defined the notification macros away, them provide default implementations
+that uses task notifications. */
+/*lint -save -e9026 Function like macros allowed and needed here so they can be overidden. */
+#ifndef sbRECEIVE_COMPLETED
+	#define sbRECEIVE_COMPLETED( pxStreamBuffer )										\
+		vTaskSuspendAll();																\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
+			{																			\
+				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend,			\
+									  ( uint32_t ) 0,									\
+									  eNoAction );										\
+				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
+			}																			\
+		}																				\
+		( void ) xTaskResumeAll();
+#endif /* sbRECEIVE_COMPLETED */
+
+#ifndef sbRECEIVE_COMPLETED_FROM_ISR
+	#define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,								\
+										  pxHigherPriorityTaskWoken )					\
+	{																					\
+	UBaseType_t uxSavedInterruptStatus;													\
+																						\
+		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
+			{																			\
+				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,	\
+											 ( uint32_t ) 0,							\
+											 eNoAction,									\
+											 pxHigherPriorityTaskWoken );				\
+				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
+			}																			\
+		}																				\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
+	}
+#endif /* sbRECEIVE_COMPLETED_FROM_ISR */
+
+/* If the user has not provided an application specific Tx notification macro,
+or #defined the notification macro away, them provide a default implementation
+that uses task notifications. */
+#ifndef sbSEND_COMPLETED
+	#define sbSEND_COMPLETED( pxStreamBuffer )											\
+		vTaskSuspendAll();																\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
+			{																			\
+				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive,		\
+									  ( uint32_t ) 0,									\
+									  eNoAction );										\
+				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
+			}																			\
+		}																				\
+		( void ) xTaskResumeAll();
+#endif /* sbSEND_COMPLETED */
+
+#ifndef sbSEND_COMPLETE_FROM_ISR
+	#define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )		\
+	{																					\
+	UBaseType_t uxSavedInterruptStatus;													\
+																						\
+		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
+			{																			\
+				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,	\
+											 ( uint32_t ) 0,							\
+											 eNoAction,									\
+											 pxHigherPriorityTaskWoken );				\
+				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
+			}																			\
+		}																				\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
+	}
+#endif /* sbSEND_COMPLETE_FROM_ISR */
+/*lint -restore (9026) */
+
+/* The number of bytes used to hold the length of a message in the buffer. */
+#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
+
+/* Bits stored in the ucFlags field of the stream buffer. */
+#define sbFLAGS_IS_MESSAGE_BUFFER		( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
+#define sbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */
+
+/*-----------------------------------------------------------*/
+
+/* Structure that hold state information on the buffer. */
+typedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */
+{
+	volatile size_t xTail;				/* Index to the next item to read within the buffer. */
+	volatile size_t xHead;				/* Index to the next item to write within the buffer. */
+	size_t xLength;						/* The length of the buffer pointed to by pucBuffer. */
+	size_t xTriggerLevelBytes;			/* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */
+	volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */
+	volatile TaskHandle_t xTaskWaitingToSend;	/* Holds the handle of a task waiting to send data to a message buffer that is full. */
+	uint8_t *pucBuffer;					/* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */
+	uint8_t ucFlags;
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxStreamBufferNumber;		/* Used for tracing purposes. */
+	#endif
+} StreamBuffer_t;
+
+/*
+ * The number of bytes available to be read from the buffer.
+ */
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Add xCount bytes from pucData into the pxStreamBuffer message buffer.
+ * Returns the number of bytes written, which will either equal xCount in the
+ * success case, or 0 if there was not enough space in the buffer (in which case
+ * no data is written into the buffer).
+ */
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then reads an entire
+ * message out of the buffer.  If the stream buffer is being used as a stream
+ * buffer then read as many bytes as possible from the buffer.
+ * prvReadBytesFromBuffer() is called to actually extract the bytes from the
+ * buffer's data storage area.
+ */
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+										void *pvRxData,
+										size_t xBufferLengthBytes,
+										size_t xBytesAvailable,
+										size_t xBytesToStoreMessageLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then writes an entire
+ * message to the buffer.  If the stream buffer is being used as a stream
+ * buffer then write as many bytes as possible to the buffer.
+ * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's
+ * data storage area.
+ */
+static size_t prvWriteMessageToBuffer(  StreamBuffer_t * const pxStreamBuffer,
+										const void * pvTxData,
+										size_t xDataLengthBytes,
+										size_t xSpace,
+										size_t xRequiredSpace ) PRIVILEGED_FUNCTION;
+
+/*
+ * Read xMaxCount bytes from the pxStreamBuffer message buffer and write them
+ * to pucData.
+ */
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer,
+									  uint8_t *pucData,
+									  size_t xMaxCount,
+									  size_t xBytesAvailable ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to
+ * initialise the members of the newly created stream buffer structure.
+ */
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+										  uint8_t * const pucBuffer,
+										  size_t xBufferSizeBytes,
+										  size_t xTriggerLevelBytes,
+										  uint8_t ucFlags ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer )
+	{
+	uint8_t *pucAllocatedMemory;
+	uint8_t ucFlags;
+
+		/* In case the stream buffer is going to be used as a message buffer
+		(that is, it will hold discrete messages with a little meta data that
+		says how big the next message is) check the buffer will be large enough
+		to hold at least one message. */
+		if( xIsMessageBuffer == pdTRUE )
+		{
+			/* Is a message buffer but not statically allocated. */
+			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER;
+			configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+		}
+		else
+		{
+			/* Not a message buffer and not statically allocated. */
+			ucFlags = 0;
+			configASSERT( xBufferSizeBytes > 0 );
+		}
+		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+		/* A trigger level of 0 would cause a waiting task to unblock even when
+		the buffer was empty. */
+		if( xTriggerLevelBytes == ( size_t ) 0 )
+		{
+			xTriggerLevelBytes = ( size_t ) 1;
+		}
+
+		/* A stream buffer requires a StreamBuffer_t structure and a buffer.
+		Both are allocated in a single call to pvPortMalloc().  The
+		StreamBuffer_t structure is placed at the start of the allocated memory
+		and the buffer follows immediately after.  The requested size is
+		incremented so the free space is returned as the user would expect -
+		this is a quirk of the implementation that means otherwise the free
+		space would be reported as one byte smaller than would be logically
+		expected. */
+		xBufferSizeBytes++;
+		pucAllocatedMemory = ( uint8_t * ) pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); /*lint !e9079 malloc() only returns void*. */
+
+		if( pucAllocatedMemory != NULL )
+		{
+			prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pucAllocatedMemory, /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */
+										   pucAllocatedMemory + sizeof( StreamBuffer_t ),  /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */
+										   xBufferSizeBytes,
+										   xTriggerLevelBytes,
+										   ucFlags );
+
+			traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer );
+		}
+		else
+		{
+			traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
+		}
+
+		return ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+														   size_t xTriggerLevelBytes,
+														   BaseType_t xIsMessageBuffer,
+														   uint8_t * const pucStreamBufferStorageArea,
+														   StaticStreamBuffer_t * const pxStaticStreamBuffer )
+	{
+	StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */
+	StreamBufferHandle_t xReturn;
+	uint8_t ucFlags;
+
+		configASSERT( pucStreamBufferStorageArea );
+		configASSERT( pxStaticStreamBuffer );
+		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+		/* A trigger level of 0 would cause a waiting task to unblock even when
+		the buffer was empty. */
+		if( xTriggerLevelBytes == ( size_t ) 0 )
+		{
+			xTriggerLevelBytes = ( size_t ) 1;
+		}
+
+		if( xIsMessageBuffer != pdFALSE )
+		{
+			/* Statically allocated message buffer. */
+			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
+		}
+		else
+		{
+			/* Statically allocated stream buffer. */
+			ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED;
+		}
+
+		/* In case the stream buffer is going to be used as a message buffer
+		(that is, it will hold discrete messages with a little meta data that
+		says how big the next message is) check the buffer will be large enough
+		to hold at least one message. */
+		configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticStreamBuffer_t equals the size of the real
+			message buffer structure. */
+			volatile size_t xSize = sizeof( StaticStreamBuffer_t );
+			configASSERT( xSize == sizeof( StreamBuffer_t ) );
+		} /*lint !e529 xSize is referenced is configASSERT() is defined. */
+		#endif /* configASSERT_DEFINED */
+
+		if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )
+		{
+			prvInitialiseNewStreamBuffer( pxStreamBuffer,
+										  pucStreamBufferStorageArea,
+										  xBufferSizeBytes,
+										  xTriggerLevelBytes,
+										  ucFlags );
+
+			/* Remember this was statically allocated in case it is ever deleted
+			again. */
+			pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED;
+
+			traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer );
+
+			xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */
+		}
+		else
+		{
+			xReturn = NULL;
+			traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * pxStreamBuffer = xStreamBuffer;
+
+	configASSERT( pxStreamBuffer );
+
+	traceSTREAM_BUFFER_DELETE( xStreamBuffer );
+
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE )
+	{
+		#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+		{
+			/* Both the structure and the buffer were allocated using a single call
+			to pvPortMalloc(), hence only one call to vPortFree() is required. */
+			vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */
+		}
+		#else
+		{
+			/* Should not be possible to get here, ucFlags must be corrupt.
+			Force an assert. */
+			configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 );
+		}
+		#endif
+	}
+	else
+	{
+		/* The structure and buffer were not allocated dynamically and cannot be
+		freed - just scrub the structure so future use will assert. */
+		( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn = pdFAIL;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	UBaseType_t uxStreamBufferNumber;
+#endif
+
+	configASSERT( pxStreamBuffer );
+
+	#if( configUSE_TRACE_FACILITY == 1 )
+	{
+		/* Store the stream buffer number so it can be restored after the
+		reset. */
+		uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;
+	}
+	#endif
+
+	/* Can only reset a message buffer if there are no tasks blocked on it. */
+	taskENTER_CRITICAL();
+	{
+		if( pxStreamBuffer->xTaskWaitingToReceive == NULL )
+		{
+			if( pxStreamBuffer->xTaskWaitingToSend == NULL )
+			{
+				prvInitialiseNewStreamBuffer( pxStreamBuffer,
+											  pxStreamBuffer->pucBuffer,
+											  pxStreamBuffer->xLength,
+											  pxStreamBuffer->xTriggerLevelBytes,
+											  pxStreamBuffer->ucFlags );
+				xReturn = pdPASS;
+
+				#if( configUSE_TRACE_FACILITY == 1 )
+				{
+					pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+				}
+				#endif
+
+				traceSTREAM_BUFFER_RESET( xStreamBuffer );
+			}
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	/* It is not valid for the trigger level to be 0. */
+	if( xTriggerLevel == ( size_t ) 0 )
+	{
+		xTriggerLevel = ( size_t ) 1;
+	}
+
+	/* The trigger level is the number of bytes that must be in the stream
+	buffer before a task that is waiting for data is unblocked. */
+	if( xTriggerLevel <= pxStreamBuffer->xLength )
+	{
+		pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel;
+		xReturn = pdPASS;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xSpace;
+
+	configASSERT( pxStreamBuffer );
+
+	xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
+	xSpace -= pxStreamBuffer->xHead;
+	xSpace -= ( size_t ) 1;
+
+	if( xSpace >= pxStreamBuffer->xLength )
+	{
+		xSpace -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xSpace;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	xReturn = prvBytesInBuffer( pxStreamBuffer );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+						  const void *pvTxData,
+						  size_t xDataLengthBytes,
+						  TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xSpace = 0;
+size_t xRequiredSpace = xDataLengthBytes;
+TimeOut_t xTimeOut;
+
+	configASSERT( pvTxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This send function is used to write to both message buffers and stream
+	buffers.  If this is a message buffer then the space needed must be
+	increased by the amount of bytes needed to store the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+
+		/* Overflow? */
+		configASSERT( xRequiredSpace > xDataLengthBytes );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		vTaskSetTimeOutState( &xTimeOut );
+
+		do
+		{
+			/* Wait until the required number of bytes are free in the message
+			buffer. */
+			taskENTER_CRITICAL();
+			{
+				xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+
+				if( xSpace < xRequiredSpace )
+				{
+					/* Clear notification state as going to wait for space. */
+					( void ) xTaskNotifyStateClear( NULL );
+
+					/* Should only be one writer. */
+					configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
+					pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();
+				}
+				else
+				{
+					taskEXIT_CRITICAL();
+					break;
+				}
+			}
+			taskEXIT_CRITICAL();
+
+			traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+			pxStreamBuffer->xTaskWaitingToSend = NULL;
+
+		} while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	if( xSpace == ( size_t ) 0 )
+	{
+		xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+	if( xReturn > ( size_t ) 0 )
+	{
+		traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn );
+
+		/* Was a task waiting for the data? */
+		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+		{
+			sbSEND_COMPLETED( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+		traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+								 const void *pvTxData,
+								 size_t xDataLengthBytes,
+								 BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xSpace;
+size_t xRequiredSpace = xDataLengthBytes;
+
+	configASSERT( pvTxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This send function is used to write to both message buffers and stream
+	buffers.  If this is a message buffer then the space needed must be
+	increased by the amount of bytes needed to store the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+	if( xReturn > ( size_t ) 0 )
+	{
+		/* Was a task waiting for the data? */
+		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+		{
+			sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
+									   const void * pvTxData,
+									   size_t xDataLengthBytes,
+									   size_t xSpace,
+									   size_t xRequiredSpace )
+{
+	BaseType_t xShouldWrite;
+	size_t xReturn;
+
+	if( xSpace == ( size_t ) 0 )
+	{
+		/* Doesn't matter if this is a stream buffer or a message buffer, there
+		is no space to write. */
+		xShouldWrite = pdFALSE;
+	}
+	else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 )
+	{
+		/* This is a stream buffer, as opposed to a message buffer, so writing a
+		stream of bytes rather than discrete messages.  Write as many bytes as
+		possible. */
+		xShouldWrite = pdTRUE;
+		xDataLengthBytes = configMIN( xDataLengthBytes, xSpace );
+	}
+	else if( xSpace >= xRequiredSpace )
+	{
+		/* This is a message buffer, as opposed to a stream buffer, and there
+		is enough space to write both the message length and the message itself
+		into the buffer.  Start by writing the length of the data, the data
+		itself will be written later in this function. */
+		xShouldWrite = pdTRUE;
+		( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH );
+	}
+	else
+	{
+		/* There is space available, but not enough space. */
+		xShouldWrite = pdFALSE;
+	}
+
+	if( xShouldWrite != pdFALSE )
+	{
+		/* Writes the data itself. */
+		xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */
+	}
+	else
+	{
+		xReturn = 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+							 void *pvRxData,
+							 size_t xBufferLengthBytes,
+							 TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+	configASSERT( pvRxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This receive function is used by both message buffers, which store
+	discrete messages, and stream buffers, which store a continuous stream of
+	bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		/* Checking if there is data and clearing the notification state must be
+		performed atomically. */
+		taskENTER_CRITICAL();
+		{
+			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+			/* If this function was invoked by a message buffer read then
+			xBytesToStoreMessageLength holds the number of bytes used to hold
+			the length of the next discrete message.  If this function was
+			invoked by a stream buffer read then xBytesToStoreMessageLength will
+			be 0. */
+			if( xBytesAvailable <= xBytesToStoreMessageLength )
+			{
+				/* Clear notification state as going to wait for data. */
+				( void ) xTaskNotifyStateClear( NULL );
+
+				/* Should only be one reader. */
+				configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
+				pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		if( xBytesAvailable <= xBytesToStoreMessageLength )
+		{
+			/* Wait for data to be available. */
+			traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+			pxStreamBuffer->xTaskWaitingToReceive = NULL;
+
+			/* Recheck the data available after blocking. */
+			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+	}
+
+	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
+	holds the number of bytes used to store the message length) or a stream of
+	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+	available must be greater than xBytesToStoreMessageLength to be able to
+	read bytes from the buffer. */
+	if( xBytesAvailable > xBytesToStoreMessageLength )
+	{
+		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+		/* Was a task waiting for space in the buffer? */
+		if( xReceivedLength != ( size_t ) 0 )
+		{
+			traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength );
+			sbRECEIVE_COMPLETED( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer );
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xBytesAvailable, xOriginalTail;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	/* Ensure the stream buffer is being used as a message buffer. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+		if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH )
+		{
+			/* The number of bytes available is greater than the number of bytes
+			required to hold the length of the next message, so another message
+			is available.  Return its length without removing the length bytes
+			from the buffer.  A copy of the tail is stored so the buffer can be
+			returned to its prior state as the message is not actually being
+			removed from the buffer. */
+			xOriginalTail = pxStreamBuffer->xTail;
+			( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, xBytesAvailable );
+			xReturn = ( size_t ) xTempReturn;
+			pxStreamBuffer->xTail = xOriginalTail;
+		}
+		else
+		{
+			/* The minimum amount of bytes in a message buffer is
+			( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is
+			less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid
+			value is 0. */
+			configASSERT( xBytesAvailable == 0 );
+			xReturn = 0;
+		}
+	}
+	else
+	{
+		xReturn = 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+									void *pvRxData,
+									size_t xBufferLengthBytes,
+									BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+	configASSERT( pvRxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This receive function is used by both message buffers, which store
+	discrete messages, and stream buffers, which store a continuous stream of
+	bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
+	holds the number of bytes used to store the message length) or a stream of
+	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+	available must be greater than xBytesToStoreMessageLength to be able to
+	read bytes from the buffer. */
+	if( xBytesAvailable > xBytesToStoreMessageLength )
+	{
+		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+		/* Was a task waiting for space in the buffer? */
+		if( xReceivedLength != ( size_t ) 0 )
+		{
+			sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength );
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+										void *pvRxData,
+										size_t xBufferLengthBytes,
+										size_t xBytesAvailable,
+										size_t xBytesToStoreMessageLength )
+{
+size_t xOriginalTail, xReceivedLength, xNextMessageLength;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength;
+
+	if( xBytesToStoreMessageLength != ( size_t ) 0 )
+	{
+		/* A discrete message is being received.  First receive the length
+		of the message.  A copy of the tail is stored so the buffer can be
+		returned to its prior state if the length of the message is too
+		large for the provided buffer. */
+		xOriginalTail = pxStreamBuffer->xTail;
+		( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable );
+		xNextMessageLength = ( size_t ) xTempNextMessageLength;
+
+		/* Reduce the number of bytes available by the number of bytes just
+		read out. */
+		xBytesAvailable -= xBytesToStoreMessageLength;
+
+		/* Check there is enough space in the buffer provided by the
+		user. */
+		if( xNextMessageLength > xBufferLengthBytes )
+		{
+			/* The user has provided insufficient space to read the message
+			so return the buffer to its previous state (so the length of
+			the message is in the buffer again). */
+			pxStreamBuffer->xTail = xOriginalTail;
+			xNextMessageLength = 0;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		/* A stream of bytes is being received (as opposed to a discrete
+		message), so read as many bytes as possible. */
+		xNextMessageLength = xBufferLengthBytes;
+	}
+
+	/* Read the actual data. */
+	xReceivedLength = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xNextMessageLength, xBytesAvailable ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+size_t xTail;
+
+	configASSERT( pxStreamBuffer );
+
+	/* True if no bytes are available. */
+	xTail = pxStreamBuffer->xTail;
+	if( pxStreamBuffer->xHead == xTail )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )
+{
+BaseType_t xReturn;
+size_t xBytesToStoreMessageLength;
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+
+	configASSERT( pxStreamBuffer );
+
+	/* This generic version of the receive function is used by both message
+	buffers, which store discrete messages, and stream buffers, which store a
+	continuous stream of bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	/* True if the available space equals zero. */
+	if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	configASSERT( pxStreamBuffer );
+
+	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
+		{
+			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,
+										 ( uint32_t ) 0,
+										 eNoAction,
+										 pxHigherPriorityTaskWoken );
+			( pxStreamBuffer )->xTaskWaitingToReceive = NULL;
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	configASSERT( pxStreamBuffer );
+
+	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
+		{
+			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,
+										 ( uint32_t ) 0,
+										 eNoAction,
+										 pxHigherPriorityTaskWoken );
+			( pxStreamBuffer )->xTaskWaitingToSend = NULL;
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount )
+{
+size_t xNextHead, xFirstLength;
+
+	configASSERT( xCount > ( size_t ) 0 );
+
+	xNextHead = pxStreamBuffer->xHead;
+
+	/* Calculate the number of bytes that can be added in the first write -
+	which may be less than the total number of bytes that need to be added if
+	the buffer will wrap back to the beginning. */
+	xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount );
+
+	/* Write as many bytes as can be written in the first write. */
+	configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength );
+	( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+	/* If the number of bytes written was less than the number that could be
+	written in the first write... */
+	if( xCount > xFirstLength )
+	{
+		/* ...then write the remaining bytes to the start of the buffer. */
+		configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
+		( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xNextHead += xCount;
+	if( xNextHead >= pxStreamBuffer->xLength )
+	{
+		xNextHead -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxStreamBuffer->xHead = xNextHead;
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer, uint8_t *pucData, size_t xMaxCount, size_t xBytesAvailable )
+{
+size_t xCount, xFirstLength, xNextTail;
+
+	/* Use the minimum of the wanted bytes and the available bytes. */
+	xCount = configMIN( xBytesAvailable, xMaxCount );
+
+	if( xCount > ( size_t ) 0 )
+	{
+		xNextTail = pxStreamBuffer->xTail;
+
+		/* Calculate the number of bytes that can be read - which may be
+		less than the number wanted if the data wraps around to the start of
+		the buffer. */
+		xFirstLength = configMIN( pxStreamBuffer->xLength - xNextTail, xCount );
+
+		/* Obtain the number of bytes it is possible to obtain in the first
+		read.  Asserts check bounds of read and write. */
+		configASSERT( xFirstLength <= xMaxCount );
+		configASSERT( ( xNextTail + xFirstLength ) <= pxStreamBuffer->xLength );
+		( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+		/* If the total number of wanted bytes is greater than the number
+		that could be read in the first read... */
+		if( xCount > xFirstLength )
+		{
+			/*...then read the remaining bytes from the start of the buffer. */
+			configASSERT( xCount <= xMaxCount );
+			( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Move the tail pointer to effectively remove the data read from
+		the buffer. */
+		xNextTail += xCount;
+
+		if( xNextTail >= pxStreamBuffer->xLength )
+		{
+			xNextTail -= pxStreamBuffer->xLength;
+		}
+
+		pxStreamBuffer->xTail = xNextTail;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )
+{
+/* Returns the distance between xTail and xHead. */
+size_t xCount;
+
+	xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
+	xCount -= pxStreamBuffer->xTail;
+	if ( xCount >= pxStreamBuffer->xLength )
+	{
+		xCount -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+										  uint8_t * const pucBuffer,
+										  size_t xBufferSizeBytes,
+										  size_t xTriggerLevelBytes,
+										  uint8_t ucFlags )
+{
+	/* Assert here is deliberately writing to the entire buffer to ensure it can
+	be written to without generating exceptions, and is setting the buffer to a
+	known value to assist in development/debugging. */
+	#if( configASSERT_DEFINED == 1 )
+	{
+		/* The value written just has to be identifiable when looking at the
+		memory.  Don't use 0xA5 as that is the stack fill value and could
+		result in confusion as to what is actually being observed. */
+		const BaseType_t xWriteValue = 0x55;
+		configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );
+	} /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */
+	#endif
+
+	( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */
+	pxStreamBuffer->pucBuffer = pucBuffer;
+	pxStreamBuffer->xLength = xBufferSizeBytes;
+	pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
+	pxStreamBuffer->ucFlags = ucFlags;
+}
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )
+	{
+		return xStreamBuffer->uxStreamBufferNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber )
+	{
+		xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
+	{
+		return ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER );
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/tasks.c b/FreeRTOSv10.2.1/FreeRTOS/Source/tasks.c
new file mode 100644
index 0000000..3274e83
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/tasks.c
@@ -0,0 +1,5214 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "stack_macros.h"
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
+functions but without including stdio.h here. */
+#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )
+	/* At the bottom of this file are two optional functions that can be used
+	to generate human readable text from the raw data generated by the
+	uxTaskGetSystemState() function.  Note the formatting functions are provided
+	for convenience only, and are NOT considered part of the kernel. */
+	#include 
+#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */
+
+#if( configUSE_PREEMPTION == 0 )
+	/* If the cooperative scheduler is being used then a yield should not be
+	performed just because a higher priority task has been woken. */
+	#define taskYIELD_IF_USING_PREEMPTION()
+#else
+	#define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/* Values that can be assigned to the ucNotifyState member of the TCB. */
+#define taskNOT_WAITING_NOTIFICATION	( ( uint8_t ) 0 )
+#define taskWAITING_NOTIFICATION		( ( uint8_t ) 1 )
+#define taskNOTIFICATION_RECEIVED		( ( uint8_t ) 2 )
+
+/*
+ * The value used to fill the stack of a task when the task is created.  This
+ * is used purely for checking the high water mark for tasks.
+ */
+#define tskSTACK_FILL_BYTE	( 0xa5U )
+
+/* Bits used to recored how a task's stack and TCB were allocated. */
+#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB 		( ( uint8_t ) 0 )
+#define tskSTATICALLY_ALLOCATED_STACK_ONLY 			( ( uint8_t ) 1 )
+#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB		( ( uint8_t ) 2 )
+
+/* If any of the following are set then task stacks are filled with a known
+value so the high water mark can be determined.  If none of the following are
+set then don't fill the stack so there is no unnecessary dependency on memset. */
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	1
+#else
+	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	0
+#endif
+
+/*
+ * Macros used by vListTask to indicate which state a task is in.
+ */
+#define tskRUNNING_CHAR		( 'X' )
+#define tskBLOCKED_CHAR		( 'B' )
+#define tskREADY_CHAR		( 'R' )
+#define tskDELETED_CHAR		( 'D' )
+#define tskSUSPENDED_CHAR	( 'S' )
+
+/*
+ * Some kernel aware debuggers require the data the debugger needs access to be
+ * global, rather than file scope.
+ */
+#ifdef portREMOVE_STATIC_QUALIFIER
+	#define static
+#endif
+
+/* The name allocated to the Idle task.  This can be overridden by defining
+configIDLE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configIDLE_TASK_NAME
+	#define configIDLE_TASK_NAME "IDLE"
+#endif
+
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+
+	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is
+	performed in a generic way that is not optimised to any particular
+	microcontroller architecture. */
+
+	/* uxTopReadyPriority holds the priority of the highest priority ready
+	state task. */
+	#define taskRECORD_READY_PRIORITY( uxPriority )														\
+	{																									\
+		if( ( uxPriority ) > uxTopReadyPriority )														\
+		{																								\
+			uxTopReadyPriority = ( uxPriority );														\
+		}																								\
+	} /* taskRECORD_READY_PRIORITY */
+
+	/*-----------------------------------------------------------*/
+
+	#define taskSELECT_HIGHEST_PRIORITY_TASK()															\
+	{																									\
+	UBaseType_t uxTopPriority = uxTopReadyPriority;														\
+																										\
+		/* Find the highest priority queue that contains ready tasks. */								\
+		while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) )							\
+		{																								\
+			configASSERT( uxTopPriority );																\
+			--uxTopPriority;																			\
+		}																								\
+																										\
+		/* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of						\
+		the	same priority get an equal share of the processor time. */									\
+		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );			\
+		uxTopReadyPriority = uxTopPriority;																\
+	} /* taskSELECT_HIGHEST_PRIORITY_TASK */
+
+	/*-----------------------------------------------------------*/
+
+	/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as
+	they are only required when a port optimised method of task selection is
+	being used. */
+	#define taskRESET_READY_PRIORITY( uxPriority )
+	#define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is
+	performed in a way that is tailored to the particular microcontroller
+	architecture being used. */
+
+	/* A port optimised version is provided.  Call the port defined macros. */
+	#define taskRECORD_READY_PRIORITY( uxPriority )	portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+	/*-----------------------------------------------------------*/
+
+	#define taskSELECT_HIGHEST_PRIORITY_TASK()														\
+	{																								\
+	UBaseType_t uxTopPriority;																		\
+																									\
+		/* Find the highest priority list that contains ready tasks. */								\
+		portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority );								\
+		configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 );		\
+		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );		\
+	} /* taskSELECT_HIGHEST_PRIORITY_TASK() */
+
+	/*-----------------------------------------------------------*/
+
+	/* A port optimised version is provided, call it only if the TCB being reset
+	is being referenced from a ready list.  If it is referenced from a delayed
+	or suspended list then it won't be in a ready list. */
+	#define taskRESET_READY_PRIORITY( uxPriority )														\
+	{																									\
+		if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 )	\
+		{																								\
+			portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) );							\
+		}																								\
+	}
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick
+count overflows. */
+#define taskSWITCH_DELAYED_LISTS()																	\
+{																									\
+	List_t *pxTemp;																					\
+																									\
+	/* The delayed tasks list should be empty when the lists are switched. */						\
+	configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );										\
+																									\
+	pxTemp = pxDelayedTaskList;																		\
+	pxDelayedTaskList = pxOverflowDelayedTaskList;													\
+	pxOverflowDelayedTaskList = pxTemp;																\
+	xNumOfOverflows++;																				\
+	prvResetNextTaskUnblockTime();																	\
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Place the task represented by pxTCB into the appropriate ready list for
+ * the task.  It is inserted at the end of the list.
+ */
+#define prvAddTaskToReadyList( pxTCB )																\
+	traceMOVED_TASK_TO_READY_STATE( pxTCB );														\
+	taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority );												\
+	vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \
+	tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
+/*-----------------------------------------------------------*/
+
+/*
+ * Several functions take an TaskHandle_t parameter that can optionally be NULL,
+ * where NULL is used to indicate that the handle of the currently executing
+ * task should be used in place of the parameter.  This macro simply checks to
+ * see if the parameter is NULL and returns a pointer to the appropriate TCB.
+ */
+#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) )
+
+/* The item value of the event list item is normally used to hold the priority
+of the task to which it belongs (coded to allow it to be held in reverse
+priority order).  However, it is occasionally borrowed for other purposes.  It
+is important its value is not updated due to a task priority change while it is
+being used for another purpose.  The following bit definition is used to inform
+the scheduler that the value should not be changed - in which case it is the
+responsibility of whichever module is using the value to ensure it gets set back
+to its original value when it is released. */
+#if( configUSE_16_BIT_TICKS == 1 )
+	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x8000U
+#else
+	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x80000000UL
+#endif
+
+/*
+ * Task control block.  A task control block (TCB) is allocated for each task,
+ * and stores task state information, including a pointer to the task's context
+ * (the task's run time environment, including register values)
+ */
+typedef struct tskTaskControlBlock 			/* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	volatile StackType_t	*pxTopOfStack;	/*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
+
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+		xMPU_SETTINGS	xMPUSettings;		/*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
+	#endif
+
+	ListItem_t			xStateListItem;	/*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
+	ListItem_t			xEventListItem;		/*< Used to reference a task from an event list. */
+	UBaseType_t			uxPriority;			/*< The priority of the task.  0 is the lowest priority. */
+	StackType_t			*pxStack;			/*< Points to the start of the stack. */
+	char				pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+	#if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+		StackType_t		*pxEndOfStack;		/*< Points to the highest valid address for the stack. */
+	#endif
+
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+		UBaseType_t		uxCriticalNesting;	/*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t		uxTCBNumber;		/*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
+		UBaseType_t		uxTaskNumber;		/*< Stores a number specifically for use by third party trace code. */
+	#endif
+
+	#if ( configUSE_MUTEXES == 1 )
+		UBaseType_t		uxBasePriority;		/*< The priority last assigned to the task - used by the priority inheritance mechanism. */
+		UBaseType_t		uxMutexesHeld;
+	#endif
+
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+		TaskHookFunction_t pxTaskTag;
+	#endif
+
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+		void			*pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+	#endif
+
+	#if( configGENERATE_RUN_TIME_STATS == 1 )
+		uint32_t		ulRunTimeCounter;	/*< Stores the amount of time the task has spent in the Running state. */
+	#endif
+
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		/* Allocate a Newlib reent structure that is specific to this task.
+		Note Newlib support has been included by popular demand, but is not
+		used by the FreeRTOS maintainers themselves.  FreeRTOS is not
+		responsible for resulting newlib operation.  User must be familiar with
+		newlib and must provide system-wide implementations of the necessary
+		stubs. Be warned that (at the time of writing) the current newlib design
+		implements a system-wide malloc() that must be provided with locks. */
+		struct	_reent xNewLib_reent;
+	#endif
+
+	#if( configUSE_TASK_NOTIFICATIONS == 1 )
+		volatile uint32_t ulNotifiedValue;
+		volatile uint8_t ucNotifyState;
+	#endif
+
+	/* See the comments in FreeRTOS.h with the definition of
+	tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
+	#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+		uint8_t	ucStaticallyAllocated; 		/*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+		uint8_t ucDelayAborted;
+	#endif
+
+	#if( configUSE_POSIX_ERRNO == 1 )
+		int iTaskErrno;
+	#endif
+
+} tskTCB;
+
+/* The old tskTCB name is maintained above then typedefed to the new TCB_t name
+below to enable the use of older kernel aware debuggers. */
+typedef tskTCB TCB_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
+PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
+
+/* Lists for ready and blocked tasks. --------------------
+xDelayedTaskList1 and xDelayedTaskList2 could be move to function scople but
+doing so breaks some kernel aware debuggers and debuggers that rely on removing
+the static qualifier. */
+PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ];/*< Prioritised ready tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList1;						/*< Delayed tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList2;						/*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList;				/*< Points to the delayed task list currently being used. */
+PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList;		/*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t xPendingReadyList;						/*< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */
+
+#if( INCLUDE_vTaskDelete == 1 )
+
+	PRIVILEGED_DATA static List_t xTasksWaitingTermination;				/*< Tasks that have been deleted - but their memory not yet freed. */
+	PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;
+
+#endif
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	PRIVILEGED_DATA static List_t xSuspendedTaskList;					/*< Tasks that are currently suspended. */
+
+#endif
+
+/* Global POSIX errno. Its value is changed upon context switching to match
+the errno of the currently running task. */
+#if ( configUSE_POSIX_ERRNO == 1 )
+	int FreeRTOS_errno = 0;
+#endif
+
+/* Other file private variables. --------------------------------*/
+PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks 	= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xTickCount 				= ( TickType_t ) configINITIAL_TICK_COUNT;
+PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority 		= tskIDLE_PRIORITY;
+PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning 		= pdFALSE;
+PRIVILEGED_DATA static volatile UBaseType_t uxPendedTicks 			= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile BaseType_t xYieldPending 			= pdFALSE;
+PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows 			= ( BaseType_t ) 0;
+PRIVILEGED_DATA static UBaseType_t uxTaskNumber 					= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime		= ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */
+PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle					= NULL;			/*< Holds the handle of the idle task.  The idle task is created automatically when the scheduler is started. */
+
+/* Context switches are held pending while the scheduler is suspended.  Also,
+interrupts must not manipulate the xStateListItem of a TCB, or any of the
+lists the xStateListItem can be referenced from, if the scheduler is suspended.
+If an interrupt needs to unblock a task while the scheduler is suspended then it
+moves the task's event list item into the xPendingReadyList, ready for the
+kernel to move the task from the pending ready list into the real ready list
+when the scheduler is unsuspended.  The pending ready list itself can only be
+accessed from a critical section. */
+PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended	= ( UBaseType_t ) pdFALSE;
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+	/* Do not move these variables to function scope as doing so prevents the
+	code working with debuggers that need to remove the static qualifier. */
+	PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL;	/*< Holds the value of a timer/counter the last time a task was switched in. */
+	PRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL;		/*< Holds the total amount of execution time as defined by the run time counter clock. */
+
+#endif
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+/* Callback function prototypes. --------------------------*/
+#if(  configCHECK_FOR_STACK_OVERFLOW > 0 )
+
+	extern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );
+
+#endif
+
+#if( configUSE_TICK_HOOK > 0 )
+
+	extern void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
+
+#endif
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	extern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */
+
+#endif
+
+/* File private functions. --------------------------------*/
+
+/**
+ * Utility task that simply returns pdTRUE if the task referenced by xTask is
+ * currently in the Suspended state, or pdFALSE if the task referenced by xTask
+ * is in any other state.
+ */
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*
+ * Utility to ready all the lists used by the scheduler.  This is called
+ * automatically upon the creation of the first task.
+ */
+static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The idle task, which as all tasks is implemented as a never ending loop.
+ * The idle task is automatically created and added to the ready lists upon
+ * creation of the first user task.
+ *
+ * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );
+
+/*
+ * Utility to free all memory allocated by the scheduler to hold a TCB,
+ * including the stack pointed to by the TCB.
+ *
+ * This does not free memory allocated by the task itself (i.e. memory
+ * allocated by calls to pvPortMalloc from within the tasks application code).
+ */
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Used only by the idle task.  This checks to see if anything has been placed
+ * in the list of tasks waiting to be deleted.  If so the task is cleaned up
+ * and its TCB deleted.
+ */
+static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The currently executing task is entering the Blocked state.  Add the task to
+ * either the current or the overflow delayed task list.
+ */
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * Fills an TaskStatus_t structure with information on each task that is
+ * referenced from the pxList list (which may be a ready list, a delayed list,
+ * a suspended list, etc.).
+ *
+ * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM
+ * NORMAL APPLICATION CODE.
+ */
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Searches pxList for a task with name pcNameToQuery - returning a handle to
+ * the task if it is found, or NULL if the task is not found.
+ */
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * When a task is created, the stack of the task is filled with a known value.
+ * This function determines the 'high water mark' of the task stack by
+ * determining how much of the stack remains at the original preset value.
+ */
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+
+	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Return the amount of time, in ticks, that will pass before the kernel will
+ * next move a task from the Blocked state to the Running state.
+ *
+ * This conditional compilation should use inequality to 0, not equality to 1.
+ * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user
+ * defined low power mode implementations require configUSE_TICKLESS_IDLE to be
+ * set to a value other than 1.
+ */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Set xNextTaskUnblockTime to the time at which the next Blocked state task
+ * will exit the Blocked state.
+ */
+static void prvResetNextTaskUnblockTime( void );
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	/*
+	 * Helper function used to pad task names with spaces when printing out
+	 * human readable tables of task information.
+	 */
+	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Called after a Task_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
+									const char * const pcName, 		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a new task has been created and initialised to place the task
+ * under the control of the scheduler.
+ */
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
+
+/*
+ * freertos_tasks_c_additions_init() should only be called if the user definable
+ * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro
+ * called by the function.
+ */
+#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+
+	static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
+									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer )
+	{
+	TCB_t *pxNewTCB;
+	TaskHandle_t xReturn;
+
+		configASSERT( puxStackBuffer != NULL );
+		configASSERT( pxTaskBuffer != NULL );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTask_t equals the size of the real task
+			structure. */
+			volatile size_t xSize = sizeof( StaticTask_t );
+			configASSERT( xSize == sizeof( TCB_t ) );
+			( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+
+		if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
+		{
+			/* The memory used for the task's TCB and stack are passed into this
+			function - use them. */
+			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+			pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
+			prvAddNewTaskToReadyList( pxNewTCB );
+		}
+		else
+		{
+			xReturn = NULL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* SUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+		configASSERT( pxTaskDefinition->puxStackBuffer != NULL );
+		configASSERT( pxTaskDefinition->pxTaskBuffer != NULL );
+
+		if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends
+			on the implementation of the port malloc function and whether or
+			not static allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;
+
+			/* Store the stack location in the TCB. */
+			pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
+									pxTaskDefinition->pcName,
+									( uint32_t ) pxTaskDefinition->usStackDepth,
+									pxTaskDefinition->pvParameters,
+									pxTaskDefinition->uxPriority,
+									pxCreatedTask, pxNewTCB,
+									pxTaskDefinition->xRegions );
+
+			prvAddNewTaskToReadyList( pxNewTCB );
+			xReturn = pdPASS;
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+		configASSERT( pxTaskDefinition->puxStackBuffer );
+
+		if( pxTaskDefinition->puxStackBuffer != NULL )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends
+			on the implementation of the port malloc function and whether or
+			not static allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+			if( pxNewTCB != NULL )
+			{
+				/* Store the stack location in the TCB. */
+				pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+				#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+				{
+					/* Tasks can be created statically or dynamically, so note
+					this task had a statically allocated stack in case it is
+					later deleted.  The TCB was allocated dynamically. */
+					pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
+				}
+				#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+				prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
+										pxTaskDefinition->pcName,
+										( uint32_t ) pxTaskDefinition->usStackDepth,
+										pxTaskDefinition->pvParameters,
+										pxTaskDefinition->uxPriority,
+										pxCreatedTask, pxNewTCB,
+										pxTaskDefinition->xRegions );
+
+				prvAddNewTaskToReadyList( pxNewTCB );
+				xReturn = pdPASS;
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
+							const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn;
+
+		/* If the stack grows down then allocate the stack then the TCB so the stack
+		does not grow into the TCB.  Likewise if the stack grows up then allocate
+		the TCB then the stack. */
+		#if( portSTACK_GROWTH > 0 )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends on
+			the implementation of the port malloc function and whether or not static
+			allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+			if( pxNewTCB != NULL )
+			{
+				/* Allocate space for the stack used by the task being created.
+				The base of the stack memory stored in the TCB so the task can
+				be deleted later if required. */
+				pxNewTCB->pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+				if( pxNewTCB->pxStack == NULL )
+				{
+					/* Could not allocate the stack.  Delete the allocated TCB. */
+					vPortFree( pxNewTCB );
+					pxNewTCB = NULL;
+				}
+			}
+		}
+		#else /* portSTACK_GROWTH */
+		{
+		StackType_t *pxStack;
+
+			/* Allocate space for the stack used by the task being created. */
+			pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
+
+			if( pxStack != NULL )
+			{
+				/* Allocate space for the TCB. */
+				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
+
+				if( pxNewTCB != NULL )
+				{
+					/* Store the stack location in the TCB. */
+					pxNewTCB->pxStack = pxStack;
+				}
+				else
+				{
+					/* The stack cannot be used as the TCB was not created.  Free
+					it again. */
+					vPortFree( pxStack );
+				}
+			}
+			else
+			{
+				pxNewTCB = NULL;
+			}
+		}
+		#endif /* portSTACK_GROWTH */
+
+		if( pxNewTCB != NULL )
+		{
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created dynamically in case it is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+			prvAddNewTaskToReadyList( pxNewTCB );
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
+									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions )
+{
+StackType_t *pxTopOfStack;
+UBaseType_t x;
+
+	#if( portUSING_MPU_WRAPPERS == 1 )
+		/* Should the task be created in privileged mode? */
+		BaseType_t xRunPrivileged;
+		if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )
+		{
+			xRunPrivileged = pdTRUE;
+		}
+		else
+		{
+			xRunPrivileged = pdFALSE;
+		}
+		uxPriority &= ~portPRIVILEGE_BIT;
+	#endif /* portUSING_MPU_WRAPPERS == 1 */
+
+	/* Avoid dependency on memset() if it is not required. */
+	#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
+	{
+		/* Fill the stack with a known value to assist debugging. */
+		( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
+	}
+	#endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */
+
+	/* Calculate the top of stack address.  This depends on whether the stack
+	grows from high memory to low (as per the 80x86) or vice versa.
+	portSTACK_GROWTH is used to make the result positive or negative as required
+	by the port. */
+	#if( portSTACK_GROWTH < 0 )
+	{
+		pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
+		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
+
+		/* Check the alignment of the calculated top of stack is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+		#if( configRECORD_STACK_HIGH_ADDRESS == 1 )
+		{
+			/* Also record the stack's high address, which may assist
+			debugging. */
+			pxNewTCB->pxEndOfStack = pxTopOfStack;
+		}
+		#endif /* configRECORD_STACK_HIGH_ADDRESS */
+	}
+	#else /* portSTACK_GROWTH */
+	{
+		pxTopOfStack = pxNewTCB->pxStack;
+
+		/* Check the alignment of the stack buffer is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+		/* The other extreme of the stack space is required if stack checking is
+		performed. */
+		pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
+	}
+	#endif /* portSTACK_GROWTH */
+
+	/* Store the task name in the TCB. */
+	if( pcName != NULL )
+	{
+		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+		{
+			pxNewTCB->pcTaskName[ x ] = pcName[ x ];
+
+			/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
+			configMAX_TASK_NAME_LEN characters just in case the memory after the
+			string is not accessible (extremely unlikely). */
+			if( pcName[ x ] == ( char ) 0x00 )
+			{
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		/* Ensure the name string is terminated in the case that the string length
+		was greater or equal to configMAX_TASK_NAME_LEN. */
+		pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
+	}
+	else
+	{
+		/* The task has not been given a name, so just ensure there is a NULL
+		terminator when it is read out. */
+		pxNewTCB->pcTaskName[ 0 ] = 0x00;
+	}
+
+	/* This is used as an array index so must ensure it's not too large.  First
+	remove the privilege bit if one is present. */
+	if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+	{
+		uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxNewTCB->uxPriority = uxPriority;
+	#if ( configUSE_MUTEXES == 1 )
+	{
+		pxNewTCB->uxBasePriority = uxPriority;
+		pxNewTCB->uxMutexesHeld = 0;
+	}
+	#endif /* configUSE_MUTEXES */
+
+	vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
+	vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
+
+	/* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
+	back to	the containing TCB from a generic item in a list. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
+
+	/* Event lists are always in priority order. */
+	listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
+
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+	{
+		pxNewTCB->uxCriticalNesting = ( UBaseType_t ) 0U;
+	}
+	#endif /* portCRITICAL_NESTING_IN_TCB */
+
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+	{
+		pxNewTCB->pxTaskTag = NULL;
+	}
+	#endif /* configUSE_APPLICATION_TASK_TAG */
+
+	#if ( configGENERATE_RUN_TIME_STATS == 1 )
+	{
+		pxNewTCB->ulRunTimeCounter = 0UL;
+	}
+	#endif /* configGENERATE_RUN_TIME_STATS */
+
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+	{
+		vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );
+	}
+	#else
+	{
+		/* Avoid compiler warning about unreferenced parameter. */
+		( void ) xRegions;
+	}
+	#endif
+
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+	{
+		for( x = 0; x < ( UBaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS; x++ )
+		{
+			pxNewTCB->pvThreadLocalStoragePointers[ x ] = NULL;
+		}
+	}
+	#endif
+
+	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+	{
+		pxNewTCB->ulNotifiedValue = 0;
+		pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+	}
+	#endif
+
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+	{
+		/* Initialise this task's Newlib reent structure. */
+		_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
+	}
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		pxNewTCB->ucDelayAborted = pdFALSE;
+	}
+	#endif
+
+	/* Initialize the TCB stack to look as if the task was already running,
+	but had been interrupted by the scheduler.  The return address is set
+	to the start of the task function. Once the stack has been initialised
+	the top of stack variable is updated. */
+	#if( portUSING_MPU_WRAPPERS == 1 )
+	{
+		/* If the port has capability to detect stack overflow,
+		pass the stack end address to the stack initialization
+		function as well. */
+		#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		{
+			#if( portSTACK_GROWTH < 0 )
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged );
+			}
+			#else /* portSTACK_GROWTH */
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+			}
+			#endif /* portSTACK_GROWTH */
+		}
+		#else /* portHAS_STACK_OVERFLOW_CHECKING */
+		{
+			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+		}
+		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
+	}
+	#else /* portUSING_MPU_WRAPPERS */
+	{
+		/* If the port has capability to detect stack overflow,
+		pass the stack end address to the stack initialization
+		function as well. */
+		#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		{
+			#if( portSTACK_GROWTH < 0 )
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters );
+			}
+			#else /* portSTACK_GROWTH */
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters );
+			}
+			#endif /* portSTACK_GROWTH */
+		}
+		#else /* portHAS_STACK_OVERFLOW_CHECKING */
+		{
+			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
+		}
+		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
+	}
+	#endif /* portUSING_MPU_WRAPPERS */
+
+	if( pxCreatedTask != NULL )
+	{
+		/* Pass the handle out in an anonymous way.  The handle can be used to
+		change the created task's priority, delete the created task, etc.*/
+		*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
+{
+	/* Ensure interrupts don't access the task lists while the lists are being
+	updated. */
+	taskENTER_CRITICAL();
+	{
+		uxCurrentNumberOfTasks++;
+		if( pxCurrentTCB == NULL )
+		{
+			/* There are no other tasks, or all the other tasks are in
+			the suspended state - make this the current task. */
+			pxCurrentTCB = pxNewTCB;
+
+			if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
+			{
+				/* This is the first task to be created so do the preliminary
+				initialisation required.  We will not recover if this call
+				fails, but we will report the failure. */
+				prvInitialiseTaskLists();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			/* If the scheduler is not already running, make this task the
+			current task if it is the highest priority task to be created
+			so far. */
+			if( xSchedulerRunning == pdFALSE )
+			{
+				if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
+				{
+					pxCurrentTCB = pxNewTCB;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		uxTaskNumber++;
+
+		#if ( configUSE_TRACE_FACILITY == 1 )
+		{
+			/* Add a counter into the TCB for tracing only. */
+			pxNewTCB->uxTCBNumber = uxTaskNumber;
+		}
+		#endif /* configUSE_TRACE_FACILITY */
+		traceTASK_CREATE( pxNewTCB );
+
+		prvAddTaskToReadyList( pxNewTCB );
+
+		portSETUP_TCB( pxNewTCB );
+	}
+	taskEXIT_CRITICAL();
+
+	if( xSchedulerRunning != pdFALSE )
+	{
+		/* If the created task is of a higher priority than the current task
+		then it should run now. */
+		if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
+		{
+			taskYIELD_IF_USING_PREEMPTION();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	void vTaskDelete( TaskHandle_t xTaskToDelete )
+	{
+	TCB_t *pxTCB;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the calling task that is
+			being deleted. */
+			pxTCB = prvGetTCBFromHandle( xTaskToDelete );
+
+			/* Remove task from the ready list. */
+			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+			{
+				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Is the task waiting on an event also? */
+			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+			{
+				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Increment the uxTaskNumber also so kernel aware debuggers can
+			detect that the task lists need re-generating.  This is done before
+			portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will
+			not return. */
+			uxTaskNumber++;
+
+			if( pxTCB == pxCurrentTCB )
+			{
+				/* A task is deleting itself.  This cannot complete within the
+				task itself, as a context switch to another task is required.
+				Place the task in the termination list.  The idle task will
+				check the termination list and free up any memory allocated by
+				the scheduler for the TCB and stack of the deleted task. */
+				vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );
+
+				/* Increment the ucTasksDeleted variable so the idle task knows
+				there is a task that has been deleted and that it should therefore
+				check the xTasksWaitingTermination list. */
+				++uxDeletedTasksWaitingCleanUp;
+
+				/* The pre-delete hook is primarily for the Windows simulator,
+				in which Windows specific clean up operations are performed,
+				after which it is not possible to yield away from this task -
+				hence xYieldPending is used to latch that a context switch is
+				required. */
+				portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
+			}
+			else
+			{
+				--uxCurrentNumberOfTasks;
+				prvDeleteTCB( pxTCB );
+
+				/* Reset the next expected unblock time in case it referred to
+				the task that has just been deleted. */
+				prvResetNextTaskUnblockTime();
+			}
+
+			traceTASK_DELETE( pxTCB );
+		}
+		taskEXIT_CRITICAL();
+
+		/* Force a reschedule if it is the currently running task that has just
+		been deleted. */
+		if( xSchedulerRunning != pdFALSE )
+		{
+			if( pxTCB == pxCurrentTCB )
+			{
+				configASSERT( uxSchedulerSuspended == 0 );
+				portYIELD_WITHIN_API();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelayUntil == 1 )
+
+	void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )
+	{
+	TickType_t xTimeToWake;
+	BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
+
+		configASSERT( pxPreviousWakeTime );
+		configASSERT( ( xTimeIncrement > 0U ) );
+		configASSERT( uxSchedulerSuspended == 0 );
+
+		vTaskSuspendAll();
+		{
+			/* Minor optimisation.  The tick count cannot change in this
+			block. */
+			const TickType_t xConstTickCount = xTickCount;
+
+			/* Generate the tick time at which the task wants to wake. */
+			xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
+
+			if( xConstTickCount < *pxPreviousWakeTime )
+			{
+				/* The tick count has overflowed since this function was
+				lasted called.  In this case the only time we should ever
+				actually delay is if the wake time has also	overflowed,
+				and the wake time is greater than the tick time.  When this
+				is the case it is as if neither time had overflowed. */
+				if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
+				{
+					xShouldDelay = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* The tick time has not overflowed.  In this case we will
+				delay if either the wake time has overflowed, and/or the
+				tick time is less than the wake time. */
+				if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
+				{
+					xShouldDelay = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+
+			/* Update the wake time ready for the next call. */
+			*pxPreviousWakeTime = xTimeToWake;
+
+			if( xShouldDelay != pdFALSE )
+			{
+				traceTASK_DELAY_UNTIL( xTimeToWake );
+
+				/* prvAddCurrentTaskToDelayedList() needs the block time, not
+				the time to wake, so subtract the current tick count. */
+				prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		xAlreadyYielded = xTaskResumeAll();
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelayUntil */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelay == 1 )
+
+	void vTaskDelay( const TickType_t xTicksToDelay )
+	{
+	BaseType_t xAlreadyYielded = pdFALSE;
+
+		/* A delay time of zero just forces a reschedule. */
+		if( xTicksToDelay > ( TickType_t ) 0U )
+		{
+			configASSERT( uxSchedulerSuspended == 0 );
+			vTaskSuspendAll();
+			{
+				traceTASK_DELAY();
+
+				/* A task that is removed from the event list while the
+				scheduler is suspended will not get placed in the ready
+				list or removed from the blocked list until the scheduler
+				is resumed.
+
+				This task cannot be in an event list as it is the currently
+				executing task. */
+				prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
+			}
+			xAlreadyYielded = xTaskResumeAll();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelay */
+/*-----------------------------------------------------------*/
+
+#if( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )
+
+	eTaskState eTaskGetState( TaskHandle_t xTask )
+	{
+	eTaskState eReturn;
+	List_t const * pxStateList, *pxDelayedList, *pxOverflowedDelayedList;
+	const TCB_t * const pxTCB = xTask;
+
+		configASSERT( pxTCB );
+
+		if( pxTCB == pxCurrentTCB )
+		{
+			/* The task calling this function is querying its own state. */
+			eReturn = eRunning;
+		}
+		else
+		{
+			taskENTER_CRITICAL();
+			{
+				pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
+				pxDelayedList = pxDelayedTaskList;
+				pxOverflowedDelayedList = pxOverflowDelayedTaskList;
+			}
+			taskEXIT_CRITICAL();
+
+			if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) )
+			{
+				/* The task being queried is referenced from one of the Blocked
+				lists. */
+				eReturn = eBlocked;
+			}
+
+			#if ( INCLUDE_vTaskSuspend == 1 )
+				else if( pxStateList == &xSuspendedTaskList )
+				{
+					/* The task being queried is referenced from the suspended
+					list.  Is it genuinely suspended or is it blocked
+					indefinitely? */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
+					{
+						#if( configUSE_TASK_NOTIFICATIONS == 1 )
+						{
+							/* The task does not appear on the event list item of
+							and of the RTOS objects, but could still be in the
+							blocked state if it is waiting on its notification
+							rather than waiting on an object. */
+							if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+							{
+								eReturn = eBlocked;
+							}
+							else
+							{
+								eReturn = eSuspended;
+							}
+						}
+						#else
+						{
+							eReturn = eSuspended;
+						}
+						#endif
+					}
+					else
+					{
+						eReturn = eBlocked;
+					}
+				}
+			#endif
+
+			#if ( INCLUDE_vTaskDelete == 1 )
+				else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) )
+				{
+					/* The task being queried is referenced from the deleted
+					tasks list, or it is not referenced from any lists at
+					all. */
+					eReturn = eDeleted;
+				}
+			#endif
+
+			else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */
+			{
+				/* If the task is not in any other state, it must be in the
+				Ready (including pending ready) state. */
+				eReturn = eReady;
+			}
+		}
+
+		return eReturn;
+	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_eTaskGetState */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+	UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask )
+	{
+	TCB_t const *pxTCB;
+	UBaseType_t uxReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the priority of the task
+			that called uxTaskPriorityGet() that is being queried. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+			uxReturn = pxTCB->uxPriority;
+		}
+		taskEXIT_CRITICAL();
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+	UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask )
+	{
+	TCB_t const *pxTCB;
+	UBaseType_t uxReturn, uxSavedInterruptState;
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			/* If null is passed in here then it is the priority of the calling
+			task that is being queried. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+			uxReturn = pxTCB->uxPriority;
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskPrioritySet == 1 )
+
+	void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority )
+	{
+	TCB_t *pxTCB;
+	UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
+	BaseType_t xYieldRequired = pdFALSE;
+
+		configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );
+
+		/* Ensure the new priority is valid. */
+		if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+		{
+			uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the priority of the calling
+			task that is being changed. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+
+			traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );
+
+			#if ( configUSE_MUTEXES == 1 )
+			{
+				uxCurrentBasePriority = pxTCB->uxBasePriority;
+			}
+			#else
+			{
+				uxCurrentBasePriority = pxTCB->uxPriority;
+			}
+			#endif
+
+			if( uxCurrentBasePriority != uxNewPriority )
+			{
+				/* The priority change may have readied a task of higher
+				priority than the calling task. */
+				if( uxNewPriority > uxCurrentBasePriority )
+				{
+					if( pxTCB != pxCurrentTCB )
+					{
+						/* The priority of a task other than the currently
+						running task is being raised.  Is the priority being
+						raised above that of the running task? */
+						if( uxNewPriority >= pxCurrentTCB->uxPriority )
+						{
+							xYieldRequired = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						/* The priority of the running task is being raised,
+						but the running task must already be the highest
+						priority task able to run so no yield is required. */
+					}
+				}
+				else if( pxTCB == pxCurrentTCB )
+				{
+					/* Setting the priority of the running task down means
+					there may now be another task of higher priority that
+					is ready to execute. */
+					xYieldRequired = pdTRUE;
+				}
+				else
+				{
+					/* Setting the priority of any other task down does not
+					require a yield as the running task must be above the
+					new priority of the task being modified. */
+				}
+
+				/* Remember the ready list the task might be referenced from
+				before its uxPriority member is changed so the
+				taskRESET_READY_PRIORITY() macro can function correctly. */
+				uxPriorityUsedOnEntry = pxTCB->uxPriority;
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					/* Only change the priority being used if the task is not
+					currently using an inherited priority. */
+					if( pxTCB->uxBasePriority == pxTCB->uxPriority )
+					{
+						pxTCB->uxPriority = uxNewPriority;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The base priority gets set whatever. */
+					pxTCB->uxBasePriority = uxNewPriority;
+				}
+				#else
+				{
+					pxTCB->uxPriority = uxNewPriority;
+				}
+				#endif
+
+				/* Only reset the event list item value if the value is not
+				being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+				{
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* If the task is in the blocked or suspended list we need do
+				nothing more than change its priority variable. However, if
+				the task is in a ready list it needs to be removed and placed
+				in the list appropriate to its new priority. */
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+				{
+					/* The task is currently in its ready list - remove before
+					adding it to it's new ready list.  As we are in a critical
+					section we can do this even if the scheduler is suspended. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						/* It is known that the task is in its ready list so
+						there is no need to check again and the port level
+						reset macro can be called directly. */
+						portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				if( xYieldRequired != pdFALSE )
+				{
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* Remove compiler warning about unused variables when the port
+				optimised task selection is not being used. */
+				( void ) uxPriorityUsedOnEntry;
+			}
+		}
+		taskEXIT_CRITICAL();
+	}
+
+#endif /* INCLUDE_vTaskPrioritySet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	void vTaskSuspend( TaskHandle_t xTaskToSuspend )
+	{
+	TCB_t *pxTCB;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the running task that is
+			being suspended. */
+			pxTCB = prvGetTCBFromHandle( xTaskToSuspend );
+
+			traceTASK_SUSPEND( pxTCB );
+
+			/* Remove task from the ready/delayed list and place in the
+			suspended list. */
+			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+			{
+				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Is the task waiting on an event also? */
+			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+			{
+				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) );
+
+			#if( configUSE_TASK_NOTIFICATIONS == 1 )
+			{
+				if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+				{
+					/* The task was blocked to wait for a notification, but is
+					now suspended, so no notification was received. */
+					pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+				}
+			}
+			#endif
+		}
+		taskEXIT_CRITICAL();
+
+		if( xSchedulerRunning != pdFALSE )
+		{
+			/* Reset the next expected unblock time in case it referred to the
+			task that is now in the Suspended state. */
+			taskENTER_CRITICAL();
+			{
+				prvResetNextTaskUnblockTime();
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( pxTCB == pxCurrentTCB )
+		{
+			if( xSchedulerRunning != pdFALSE )
+			{
+				/* The current task has just been suspended. */
+				configASSERT( uxSchedulerSuspended == 0 );
+				portYIELD_WITHIN_API();
+			}
+			else
+			{
+				/* The scheduler is not running, but the task that was pointed
+				to by pxCurrentTCB has just been suspended and pxCurrentTCB
+				must be adjusted to point to a different task. */
+				if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */
+				{
+					/* No other tasks are ready, so set pxCurrentTCB back to
+					NULL so when the next task is created pxCurrentTCB will
+					be set to point to it no matter what its relative priority
+					is. */
+					pxCurrentTCB = NULL;
+				}
+				else
+				{
+					vTaskSwitchContext();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
+	{
+	BaseType_t xReturn = pdFALSE;
+	const TCB_t * const pxTCB = xTask;
+
+		/* Accesses xPendingReadyList so must be called from a critical
+		section. */
+
+		/* It does not make sense to check if the calling task is suspended. */
+		configASSERT( xTask );
+
+		/* Is the task being resumed actually in the suspended list? */
+		if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE )
+		{
+			/* Has the task already been resumed from within an ISR? */
+			if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )
+			{
+				/* Is it in the suspended list because it is in the	Suspended
+				state, or because is is blocked with no timeout? */
+				if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961.  The cast is only redundant when NULL is used. */
+				{
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	void vTaskResume( TaskHandle_t xTaskToResume )
+	{
+	TCB_t * const pxTCB = xTaskToResume;
+
+		/* It does not make sense to resume the calling task. */
+		configASSERT( xTaskToResume );
+
+		/* The parameter cannot be NULL as it is impossible to resume the
+		currently executing task. */
+		if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )
+		{
+			taskENTER_CRITICAL();
+			{
+				if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+				{
+					traceTASK_RESUME( pxTCB );
+
+					/* The ready list can be accessed even if the scheduler is
+					suspended because this is inside a critical section. */
+					( void ) uxListRemove(  &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+
+					/* A higher priority task may have just been resumed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						/* This yield may not cause the task just resumed to run,
+						but will leave the lists in the correct state for the
+						next yield. */
+						taskYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
+
+	BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )
+	{
+	BaseType_t xYieldRequired = pdFALSE;
+	TCB_t * const pxTCB = xTaskToResume;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToResume );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+			{
+				traceTASK_RESUME_FROM_ISR( pxTCB );
+
+				/* Check the ready lists can be accessed. */
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					/* Ready lists can be accessed so move the task from the
+					suspended list to the ready list directly. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						xYieldRequired = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed or ready lists cannot be accessed so the task
+					is held in the pending ready list until the scheduler is
+					unsuspended. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xYieldRequired;
+	}
+
+#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+void vTaskStartScheduler( void )
+{
+BaseType_t xReturn;
+
+	/* Add the idle task at the lowest priority. */
+	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	{
+		StaticTask_t *pxIdleTaskTCBBuffer = NULL;
+		StackType_t *pxIdleTaskStackBuffer = NULL;
+		uint32_t ulIdleTaskStackSize;
+
+		/* The Idle task is created using user provided RAM - obtain the
+		address of the RAM then create the idle task. */
+		vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+		xIdleTaskHandle = xTaskCreateStatic(	prvIdleTask,
+												configIDLE_TASK_NAME,
+												ulIdleTaskStackSize,
+												( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */
+												portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+												pxIdleTaskStackBuffer,
+												pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+
+		if( xIdleTaskHandle != NULL )
+		{
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+	}
+	#else
+	{
+		/* The Idle task is being created using dynamically allocated RAM. */
+		xReturn = xTaskCreate(	prvIdleTask,
+								configIDLE_TASK_NAME,
+								configMINIMAL_STACK_SIZE,
+								( void * ) NULL,
+								portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+								&xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+	}
+	#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+	#if ( configUSE_TIMERS == 1 )
+	{
+		if( xReturn == pdPASS )
+		{
+			xReturn = xTimerCreateTimerTask();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif /* configUSE_TIMERS */
+
+	if( xReturn == pdPASS )
+	{
+		/* freertos_tasks_c_additions_init() should only be called if the user
+		definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is
+		the only macro called by the function. */
+		#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+		{
+			freertos_tasks_c_additions_init();
+		}
+		#endif
+
+		/* Interrupts are turned off here, to ensure a tick does not occur
+		before or during the call to xPortStartScheduler().  The stacks of
+		the created tasks contain a status word with interrupts switched on
+		so interrupts will automatically get re-enabled when the first task
+		starts to run. */
+		portDISABLE_INTERRUPTS();
+
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			/* Switch Newlib's _impure_ptr variable to point to the _reent
+			structure specific to the task that will run first. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		xNextTaskUnblockTime = portMAX_DELAY;
+		xSchedulerRunning = pdTRUE;
+		xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
+
+		/* If configGENERATE_RUN_TIME_STATS is defined then the following
+		macro must be defined to configure the timer/counter used to generate
+		the run time counter time base.   NOTE:  If configGENERATE_RUN_TIME_STATS
+		is set to 0 and the following line fails to build then ensure you do not
+		have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your
+		FreeRTOSConfig.h file. */
+		portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
+
+		traceTASK_SWITCHED_IN();
+
+		/* Setting up the timer tick is hardware specific and thus in the
+		portable interface. */
+		if( xPortStartScheduler() != pdFALSE )
+		{
+			/* Should not reach here as if the scheduler is running the
+			function will not return. */
+		}
+		else
+		{
+			/* Should only reach here if a task calls xTaskEndScheduler(). */
+		}
+	}
+	else
+	{
+		/* This line will only be reached if the kernel could not be started,
+		because there was not enough FreeRTOS heap to create the idle task
+		or the timer task. */
+		configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
+	}
+
+	/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
+	meaning xIdleTaskHandle is not used anywhere else. */
+	( void ) xIdleTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskEndScheduler( void )
+{
+	/* Stop the scheduler interrupts and call the portable scheduler end
+	routine so the original ISRs can be restored if necessary.  The port
+	layer must ensure interrupts enable	bit is left in the correct state. */
+	portDISABLE_INTERRUPTS();
+	xSchedulerRunning = pdFALSE;
+	vPortEndScheduler();
+}
+/*----------------------------------------------------------*/
+
+void vTaskSuspendAll( void )
+{
+	/* A critical section is not required as the variable is of type
+	BaseType_t.  Please read Richard Barry's reply in the following link to a
+	post in the FreeRTOS support forum before reporting this as a bug! -
+	http://goo.gl/wu4acr */
+	++uxSchedulerSuspended;
+	portMEMORY_BARRIER();
+}
+/*----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	static TickType_t prvGetExpectedIdleTime( void )
+	{
+	TickType_t xReturn;
+	UBaseType_t uxHigherPriorityReadyTasks = pdFALSE;
+
+		/* uxHigherPriorityReadyTasks takes care of the case where
+		configUSE_PREEMPTION is 0, so there may be tasks above the idle priority
+		task that are in the Ready state, even though the idle task is
+		running. */
+		#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+		{
+			if( uxTopReadyPriority > tskIDLE_PRIORITY )
+			{
+				uxHigherPriorityReadyTasks = pdTRUE;
+			}
+		}
+		#else
+		{
+			const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01;
+
+			/* When port optimised task selection is used the uxTopReadyPriority
+			variable is used as a bit map.  If bits other than the least
+			significant bit are set then there are tasks that have a priority
+			above the idle priority that are in the Ready state.  This takes
+			care of the case where the co-operative scheduler is in use. */
+			if( uxTopReadyPriority > uxLeastSignificantBit )
+			{
+				uxHigherPriorityReadyTasks = pdTRUE;
+			}
+		}
+		#endif
+
+		if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )
+		{
+			xReturn = 0;
+		}
+		else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )
+		{
+			/* There are other idle priority tasks in the ready state.  If
+			time slicing is used then the very next tick interrupt must be
+			processed. */
+			xReturn = 0;
+		}
+		else if( uxHigherPriorityReadyTasks != pdFALSE )
+		{
+			/* There are tasks in the Ready state that have a priority above the
+			idle priority.  This path can only be reached if
+			configUSE_PREEMPTION is 0. */
+			xReturn = 0;
+		}
+		else
+		{
+			xReturn = xNextTaskUnblockTime - xTickCount;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskResumeAll( void )
+{
+TCB_t *pxTCB = NULL;
+BaseType_t xAlreadyYielded = pdFALSE;
+
+	/* If uxSchedulerSuspended is zero then this function does not match a
+	previous call to vTaskSuspendAll(). */
+	configASSERT( uxSchedulerSuspended );
+
+	/* It is possible that an ISR caused a task to be removed from an event
+	list while the scheduler was suspended.  If this was the case then the
+	removed task will have been added to the xPendingReadyList.  Once the
+	scheduler has been resumed it is safe to move all the pending ready
+	tasks from this list into their appropriate ready list. */
+	taskENTER_CRITICAL();
+	{
+		--uxSchedulerSuspended;
+
+		if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+		{
+			if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
+			{
+				/* Move any readied tasks from the pending list into the
+				appropriate ready list. */
+				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
+				{
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+					( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+
+					/* If the moved task has a priority higher than the current
+					task then a yield must be performed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						xYieldPending = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( pxTCB != NULL )
+				{
+					/* A task was unblocked while the scheduler was suspended,
+					which may have prevented the next unblock time from being
+					re-calculated, in which case re-calculate it now.  Mainly
+					important for low power tickless implementations, where
+					this can prevent an unnecessary exit from low power
+					state. */
+					prvResetNextTaskUnblockTime();
+				}
+
+				/* If any ticks occurred while the scheduler was suspended then
+				they should be processed now.  This ensures the tick count does
+				not	slip, and that any delayed tasks are resumed at the correct
+				time. */
+				{
+					UBaseType_t uxPendedCounts = uxPendedTicks; /* Non-volatile copy. */
+
+					if( uxPendedCounts > ( UBaseType_t ) 0U )
+					{
+						do
+						{
+							if( xTaskIncrementTick() != pdFALSE )
+							{
+								xYieldPending = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+							--uxPendedCounts;
+						} while( uxPendedCounts > ( UBaseType_t ) 0U );
+
+						uxPendedTicks = 0;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( xYieldPending != pdFALSE )
+				{
+					#if( configUSE_PREEMPTION != 0 )
+					{
+						xAlreadyYielded = pdTRUE;
+					}
+					#endif
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xAlreadyYielded;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCount( void )
+{
+TickType_t xTicks;
+
+	/* Critical section required if running on a 16 bit processor. */
+	portTICK_TYPE_ENTER_CRITICAL();
+	{
+		xTicks = xTickCount;
+	}
+	portTICK_TYPE_EXIT_CRITICAL();
+
+	return xTicks;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCountFromISR( void )
+{
+TickType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
+	{
+		xReturn = xTickCount;
+	}
+	portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxTaskGetNumberOfTasks( void )
+{
+	/* A critical section is not required because the variables are of type
+	BaseType_t. */
+	return uxCurrentNumberOfTasks;
+}
+/*-----------------------------------------------------------*/
+
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+TCB_t *pxTCB;
+
+	/* If null is passed in here then the name of the calling task is being
+	queried. */
+	pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+	configASSERT( pxTCB );
+	return &( pxTCB->pcTaskName[ 0 ] );
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] )
+	{
+	TCB_t *pxNextTCB, *pxFirstTCB, *pxReturn = NULL;
+	UBaseType_t x;
+	char cNextChar;
+	BaseType_t xBreakLoop;
+
+		/* This function is called with the scheduler suspended. */
+
+		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+		{
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );  /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+			do
+			{
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+				/* Check each character in the name looking for a match or
+				mismatch. */
+				xBreakLoop = pdFALSE;
+				for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+				{
+					cNextChar = pxNextTCB->pcTaskName[ x ];
+
+					if( cNextChar != pcNameToQuery[ x ] )
+					{
+						/* Characters didn't match. */
+						xBreakLoop = pdTRUE;
+					}
+					else if( cNextChar == ( char ) 0x00 )
+					{
+						/* Both strings terminated, a match must have been
+						found. */
+						pxReturn = pxNextTCB;
+						xBreakLoop = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					if( xBreakLoop != pdFALSE )
+					{
+						break;
+					}
+				}
+
+				if( pxReturn != NULL )
+				{
+					/* The handle has been found. */
+					break;
+				}
+
+			} while( pxNextTCB != pxFirstTCB );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxReturn;
+	}
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t uxQueue = configMAX_PRIORITIES;
+	TCB_t* pxTCB;
+
+		/* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */
+		configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN );
+
+		vTaskSuspendAll();
+		{
+			/* Search the ready lists. */
+			do
+			{
+				uxQueue--;
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery );
+
+				if( pxTCB != NULL )
+				{
+					/* Found the handle. */
+					break;
+				}
+
+			} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+			/* Search the delayed lists. */
+			if( pxTCB == NULL )
+			{
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery );
+			}
+
+			if( pxTCB == NULL )
+			{
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery );
+			}
+
+			#if ( INCLUDE_vTaskSuspend == 1 )
+			{
+				if( pxTCB == NULL )
+				{
+					/* Search the suspended list. */
+					pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery );
+				}
+			}
+			#endif
+
+			#if( INCLUDE_vTaskDelete == 1 )
+			{
+				if( pxTCB == NULL )
+				{
+					/* Search the deleted list. */
+					pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery );
+				}
+			}
+			#endif
+		}
+		( void ) xTaskResumeAll();
+
+		return pxTCB;
+	}
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime )
+	{
+	UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;
+
+		vTaskSuspendAll();
+		{
+			/* Is there a space in the array for each task in the system? */
+			if( uxArraySize >= uxCurrentNumberOfTasks )
+			{
+				/* Fill in an TaskStatus_t structure with information on each
+				task in the Ready state. */
+				do
+				{
+					uxQueue--;
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );
+
+				} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+				/* Fill in an TaskStatus_t structure with information on each
+				task in the Blocked state. */
+				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );
+				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );
+
+				#if( INCLUDE_vTaskDelete == 1 )
+				{
+					/* Fill in an TaskStatus_t structure with information on
+					each task that has been deleted but not yet cleaned up. */
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );
+				}
+				#endif
+
+				#if ( INCLUDE_vTaskSuspend == 1 )
+				{
+					/* Fill in an TaskStatus_t structure with information on
+					each task in the Suspended state. */
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );
+				}
+				#endif
+
+				#if ( configGENERATE_RUN_TIME_STATS == 1)
+				{
+					if( pulTotalRunTime != NULL )
+					{
+						#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+							portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );
+						#else
+							*pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+						#endif
+					}
+				}
+				#else
+				{
+					if( pulTotalRunTime != NULL )
+					{
+						*pulTotalRunTime = 0;
+					}
+				}
+				#endif
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		( void ) xTaskResumeAll();
+
+		return uxTask;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+
+	TaskHandle_t xTaskGetIdleTaskHandle( void )
+	{
+		/* If xTaskGetIdleTaskHandle() is called before the scheduler has been
+		started, then xIdleTaskHandle will be NULL. */
+		configASSERT( ( xIdleTaskHandle != NULL ) );
+		return xIdleTaskHandle;
+	}
+
+#endif /* INCLUDE_xTaskGetIdleTaskHandle */
+/*----------------------------------------------------------*/
+
+/* This conditional compilation should use inequality to 0, not equality to 1.
+This is to ensure vTaskStepTick() is available when user defined low power mode
+implementations require configUSE_TICKLESS_IDLE to be set to a value other than
+1. */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	void vTaskStepTick( const TickType_t xTicksToJump )
+	{
+		/* Correct the tick count value after a period during which the tick
+		was suppressed.  Note this does *not* call the tick hook function for
+		each stepped tick. */
+		configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );
+		xTickCount += xTicksToJump;
+		traceINCREASE_TICK_COUNT( xTicksToJump );
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskAbortDelay == 1 )
+
+	BaseType_t xTaskAbortDelay( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB = xTask;
+	BaseType_t xReturn;
+
+		configASSERT( pxTCB );
+
+		vTaskSuspendAll();
+		{
+			/* A task can only be prematurely removed from the Blocked state if
+			it is actually in the Blocked state. */
+			if( eTaskGetState( xTask ) == eBlocked )
+			{
+				xReturn = pdPASS;
+
+				/* Remove the reference to the task from the blocked list.  An
+				interrupt won't touch the xStateListItem because the
+				scheduler is suspended. */
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+				/* Is the task waiting on an event also?  If so remove it from
+				the event list too.  Interrupts can touch the event list item,
+				even though the scheduler is suspended, so a critical section
+				is used. */
+				taskENTER_CRITICAL();
+				{
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+						pxTCB->ucDelayAborted = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				taskEXIT_CRITICAL();
+
+				/* Place the unblocked task into the appropriate ready list. */
+				prvAddTaskToReadyList( pxTCB );
+
+				/* A task being unblocked cannot cause an immediate context
+				switch if preemption is turned off. */
+				#if (  configUSE_PREEMPTION == 1 )
+				{
+					/* Preemption is on, but a context switch should only be
+					performed if the unblocked task has a priority that is
+					equal to or higher than the currently executing task. */
+					if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+					{
+						/* Pend the yield to be performed when the scheduler
+						is unsuspended. */
+						xYieldPending = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_PREEMPTION */
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		( void ) xTaskResumeAll();
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTaskAbortDelay */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskIncrementTick( void )
+{
+TCB_t * pxTCB;
+TickType_t xItemValue;
+BaseType_t xSwitchRequired = pdFALSE;
+
+	/* Called by the portable layer each time a tick interrupt occurs.
+	Increments the tick then checks to see if the new tick value will cause any
+	tasks to be unblocked. */
+	traceTASK_INCREMENT_TICK( xTickCount );
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+	{
+		/* Minor optimisation.  The tick count cannot change in this
+		block. */
+		const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
+
+		/* Increment the RTOS tick, switching the delayed and overflowed
+		delayed lists if it wraps to 0. */
+		xTickCount = xConstTickCount;
+
+		if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
+		{
+			taskSWITCH_DELAYED_LISTS();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* See if this tick has made a timeout expire.  Tasks are stored in
+		the	queue in the order of their wake time - meaning once one task
+		has been found whose block time has not expired there is no need to
+		look any further down the list. */
+		if( xConstTickCount >= xNextTaskUnblockTime )
+		{
+			for( ;; )
+			{
+				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+				{
+					/* The delayed list is empty.  Set xNextTaskUnblockTime
+					to the maximum possible value so it is extremely
+					unlikely that the
+					if( xTickCount >= xNextTaskUnblockTime ) test will pass
+					next time through. */
+					xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					break;
+				}
+				else
+				{
+					/* The delayed list is not empty, get the value of the
+					item at the head of the delayed list.  This is the time
+					at which the task at the head of the delayed list must
+					be removed from the Blocked state. */
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+					xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
+
+					if( xConstTickCount < xItemValue )
+					{
+						/* It is not time to unblock this item yet, but the
+						item value is the time at which the task at the head
+						of the blocked list must be removed from the Blocked
+						state -	so record the item value in
+						xNextTaskUnblockTime. */
+						xNextTaskUnblockTime = xItemValue;
+						break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* It is time to remove the item from the Blocked state. */
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+					/* Is the task waiting on an event also?  If so remove
+					it from the event list. */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Place the unblocked task into the appropriate ready
+					list. */
+					prvAddTaskToReadyList( pxTCB );
+
+					/* A task being unblocked cannot cause an immediate
+					context switch if preemption is turned off. */
+					#if (  configUSE_PREEMPTION == 1 )
+					{
+						/* Preemption is on, but a context switch should
+						only be performed if the unblocked task has a
+						priority that is equal to or higher than the
+						currently executing task. */
+						if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+						{
+							xSwitchRequired = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					#endif /* configUSE_PREEMPTION */
+				}
+			}
+		}
+
+		/* Tasks of equal priority to the currently running task will share
+		processing time (time slice) if preemption is on, and the application
+		writer has not explicitly turned time slicing off. */
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
+		{
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
+			{
+				xSwitchRequired = pdTRUE;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
+
+		#if ( configUSE_TICK_HOOK == 1 )
+		{
+			/* Guard against the tick hook being called when the pended tick
+			count is being unwound (when the scheduler is being unlocked). */
+			if( uxPendedTicks == ( UBaseType_t ) 0U )
+			{
+				vApplicationTickHook();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_TICK_HOOK */
+	}
+	else
+	{
+		++uxPendedTicks;
+
+		/* The tick hook gets called at regular intervals, even if the
+		scheduler is locked. */
+		#if ( configUSE_TICK_HOOK == 1 )
+		{
+			vApplicationTickHook();
+		}
+		#endif
+	}
+
+	#if ( configUSE_PREEMPTION == 1 )
+	{
+		if( xYieldPending != pdFALSE )
+		{
+			xSwitchRequired = pdTRUE;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif /* configUSE_PREEMPTION */
+
+	return xSwitchRequired;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction )
+	{
+	TCB_t *xTCB;
+
+		/* If xTask is NULL then it is the task hook of the calling task that is
+		getting set. */
+		if( xTask == NULL )
+		{
+			xTCB = ( TCB_t * ) pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = xTask;
+		}
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		taskENTER_CRITICAL();
+		{
+			xTCB->pxTaskTag = pxHookFunction;
+		}
+		taskEXIT_CRITICAL();
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	TaskHookFunction_t xReturn;
+
+		/* If xTask is NULL then set the calling task's hook. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		taskENTER_CRITICAL();
+		{
+			xReturn = pxTCB->pxTaskTag;
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	TaskHookFunction_t xReturn;
+	UBaseType_t uxSavedInterruptStatus;
+
+		/* If xTask is NULL then set the calling task's hook. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			xReturn = pxTCB->pxTaskTag;
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )
+	{
+	TCB_t *xTCB;
+	BaseType_t xReturn;
+
+		/* If xTask is NULL then we are calling our own task hook. */
+		if( xTask == NULL )
+		{
+			xTCB = pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = xTask;
+		}
+
+		if( xTCB->pxTaskTag != NULL )
+		{
+			xReturn = xTCB->pxTaskTag( pvParameter );
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+void vTaskSwitchContext( void )
+{
+	if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
+	{
+		/* The scheduler is currently suspended - do not allow a context
+		switch. */
+		xYieldPending = pdTRUE;
+	}
+	else
+	{
+		xYieldPending = pdFALSE;
+		traceTASK_SWITCHED_OUT();
+
+		#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		{
+			#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+				portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
+			#else
+				ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+			#endif
+
+			/* Add the amount of time the task has been running to the
+			accumulated time so far.  The time the task started running was
+			stored in ulTaskSwitchedInTime.  Note that there is no overflow
+			protection here so count values are only valid until the timer
+			overflows.  The guard against negative values is to protect
+			against suspect run time stat counter implementations - which
+			are provided by the application, not the kernel. */
+			if( ulTotalRunTime > ulTaskSwitchedInTime )
+			{
+				pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+			ulTaskSwitchedInTime = ulTotalRunTime;
+		}
+		#endif /* configGENERATE_RUN_TIME_STATS */
+
+		/* Check for stack overflow, if configured. */
+		taskCHECK_FOR_STACK_OVERFLOW();
+
+		/* Before the currently running task is switched out, save its errno. */
+		#if( configUSE_POSIX_ERRNO == 1 )
+		{
+			pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
+		}
+		#endif
+
+		/* Select a new task to run using either the generic C or port
+		optimised asm code. */
+		taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		traceTASK_SWITCHED_IN();
+
+		/* After the new task is switched in, update the global errno. */
+		#if( configUSE_POSIX_ERRNO == 1 )
+		{
+			FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
+		}
+		#endif
+
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			/* Switch Newlib's _impure_ptr variable to point to the _reent
+			structure specific to this task. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
+{
+	configASSERT( pxEventList );
+
+	/* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE
+	SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */
+
+	/* Place the event list item of the TCB in the appropriate event list.
+	This is placed in the list in priority order so the highest priority task
+	is the first to be woken by the event.  The queue that contains the event
+	list is locked, preventing simultaneous access from interrupts. */
+	vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait )
+{
+	configASSERT( pxEventList );
+
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+	the event groups implementation. */
+	configASSERT( uxSchedulerSuspended != 0 );
+
+	/* Store the item value in the event list item.  It is safe to access the
+	event list item here as interrupts won't access the event list item of a
+	task that is not in the Blocked state. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+	/* Place the event list item of the TCB at the end of the appropriate event
+	list.  It is safe to access the event list here because it is part of an
+	event group implementation - and interrupts don't access event groups
+	directly (instead they access them indirectly by pending function calls to
+	the task level). */
+	vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+
+	void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+		configASSERT( pxEventList );
+
+		/* This function should not be called by application code hence the
+		'Restricted' in its name.  It is not part of the public API.  It is
+		designed for use by kernel code, and has special calling requirements -
+		it should be called with the scheduler suspended. */
+
+
+		/* Place the event list item of the TCB in the appropriate event list.
+		In this case it is assume that this is the only task that is going to
+		be waiting on this event list, so the faster vListInsertEnd() function
+		can be used in place of vListInsert. */
+		vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+		/* If the task should block indefinitely then set the block time to a
+		value that will be recognised as an indefinite delay inside the
+		prvAddCurrentTaskToDelayedList() function. */
+		if( xWaitIndefinitely != pdFALSE )
+		{
+			xTicksToWait = portMAX_DELAY;
+		}
+
+		traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
+		prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
+	}
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
+{
+TCB_t *pxUnblockedTCB;
+BaseType_t xReturn;
+
+	/* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION.  It can also be
+	called from a critical section within an ISR. */
+
+	/* The event list is sorted in priority order, so the first in the list can
+	be removed as it is known to be the highest priority.  Remove the TCB from
+	the delayed list, and add it to the ready list.
+
+	If an event is for a queue that is locked then this function will never
+	get called - the lock count on the queue will get modified instead.  This
+	means exclusive access to the event list is guaranteed here.
+
+	This function assumes that a check has already been made to ensure that
+	pxEventList is not empty. */
+	pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+	configASSERT( pxUnblockedTCB );
+	( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
+
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+	{
+		( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+		prvAddTaskToReadyList( pxUnblockedTCB );
+
+		#if( configUSE_TICKLESS_IDLE != 0 )
+		{
+			/* If a task is blocked on a kernel object then xNextTaskUnblockTime
+			might be set to the blocked task's time out time.  If the task is
+			unblocked for a reason other than a timeout xNextTaskUnblockTime is
+			normally left unchanged, because it is automatically reset to a new
+			value when the tick count equals xNextTaskUnblockTime.  However if
+			tickless idling is used it might be more important to enter sleep mode
+			at the earliest possible time - so reset xNextTaskUnblockTime here to
+			ensure it is updated at the earliest possible time. */
+			prvResetNextTaskUnblockTime();
+		}
+		#endif
+	}
+	else
+	{
+		/* The delayed and ready lists cannot be accessed, so hold this task
+		pending until the scheduler is resumed. */
+		vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
+	}
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+	{
+		/* Return true if the task removed from the event list has a higher
+		priority than the calling task.  This allows the calling task to know if
+		it should force a context switch now. */
+		xReturn = pdTRUE;
+
+		/* Mark that a yield is pending in case the user is not using the
+		"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
+		xYieldPending = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )
+{
+TCB_t *pxUnblockedTCB;
+
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+	the event flags implementation. */
+	configASSERT( uxSchedulerSuspended != pdFALSE );
+
+	/* Store the new item value in the event list. */
+	listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+	/* Remove the event list form the event flag.  Interrupts do not access
+	event flags. */
+	pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+	configASSERT( pxUnblockedTCB );
+	( void ) uxListRemove( pxEventListItem );
+
+	/* Remove the task from the delayed list and add it to the ready list.  The
+	scheduler is suspended so interrupts will not be accessing the ready
+	lists. */
+	( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+	prvAddTaskToReadyList( pxUnblockedTCB );
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+	{
+		/* The unblocked task has a priority above that of the calling task, so
+		a context switch is required.  This function is called with the
+		scheduler suspended so xYieldPending is set so the context switch
+		occurs immediately that the scheduler is resumed (unsuspended). */
+		xYieldPending = pdTRUE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+	configASSERT( pxTimeOut );
+	taskENTER_CRITICAL();
+	{
+		pxTimeOut->xOverflowCount = xNumOfOverflows;
+		pxTimeOut->xTimeOnEntering = xTickCount;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+	/* For internal use only as it does not use a critical section. */
+	pxTimeOut->xOverflowCount = xNumOfOverflows;
+	pxTimeOut->xTimeOnEntering = xTickCount;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
+{
+BaseType_t xReturn;
+
+	configASSERT( pxTimeOut );
+	configASSERT( pxTicksToWait );
+
+	taskENTER_CRITICAL();
+	{
+		/* Minor optimisation.  The tick count cannot change in this block. */
+		const TickType_t xConstTickCount = xTickCount;
+		const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
+
+		#if( INCLUDE_xTaskAbortDelay == 1 )
+			if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE )
+			{
+				/* The delay was aborted, which is not the same as a time out,
+				but has the same result. */
+				pxCurrentTCB->ucDelayAborted = pdFALSE;
+				xReturn = pdTRUE;
+			}
+			else
+		#endif
+
+		#if ( INCLUDE_vTaskSuspend == 1 )
+			if( *pxTicksToWait == portMAX_DELAY )
+			{
+				/* If INCLUDE_vTaskSuspend is set to 1 and the block time
+				specified is the maximum block time then the task should block
+				indefinitely, and therefore never time out. */
+				xReturn = pdFALSE;
+			}
+			else
+		#endif
+
+		if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
+		{
+			/* The tick count is greater than the time at which
+			vTaskSetTimeout() was called, but has also overflowed since
+			vTaskSetTimeOut() was called.  It must have wrapped all the way
+			around and gone past again. This passed since vTaskSetTimeout()
+			was called. */
+			xReturn = pdTRUE;
+		}
+		else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
+		{
+			/* Not a genuine timeout. Adjust parameters for time remaining. */
+			*pxTicksToWait -= xElapsedTime;
+			vTaskInternalSetTimeOutState( pxTimeOut );
+			xReturn = pdFALSE;
+		}
+		else
+		{
+			*pxTicksToWait = 0;
+			xReturn = pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskMissedYield( void )
+{
+	xYieldPending = pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )
+	{
+	UBaseType_t uxReturn;
+	TCB_t const *pxTCB;
+
+		if( xTask != NULL )
+		{
+			pxTCB = xTask;
+			uxReturn = pxTCB->uxTaskNumber;
+		}
+		else
+		{
+			uxReturn = 0U;
+		}
+
+		return uxReturn;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )
+	{
+	TCB_t * pxTCB;
+
+		if( xTask != NULL )
+		{
+			pxTCB = xTask;
+			pxTCB->uxTaskNumber = uxHandle;
+		}
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+
+/*
+ * -----------------------------------------------------------
+ * The Idle task.
+ * ----------------------------------------------------------
+ *
+ * The portTASK_FUNCTION() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION( prvIdleTask, pvParameters )
+{
+	/* Stop warnings. */
+	( void ) pvParameters;
+
+	/** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE
+	SCHEDULER IS STARTED. **/
+
+	/* In case a task that has a secure context deletes itself, in which case
+	the idle task is responsible for deleting the task's secure context, if
+	any. */
+	portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
+
+	for( ;; )
+	{
+		/* See if any tasks have deleted themselves - if so then the idle task
+		is responsible for freeing the deleted task's TCB and stack. */
+		prvCheckTasksWaitingTermination();
+
+		#if ( configUSE_PREEMPTION == 0 )
+		{
+			/* If we are not using preemption we keep forcing a task switch to
+			see if any other task has become available.  If we are using
+			preemption we don't need to do this as any task becoming available
+			will automatically get the processor anyway. */
+			taskYIELD();
+		}
+		#endif /* configUSE_PREEMPTION */
+
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
+		{
+			/* When using preemption tasks of equal priority will be
+			timesliced.  If a task that is sharing the idle priority is ready
+			to run then the idle task should yield before the end of the
+			timeslice.
+
+			A critical region is not required here as we are just reading from
+			the list, and an occasional incorrect value will not matter.  If
+			the ready list at the idle priority contains more than one task
+			then a task other than the idle task is ready to execute. */
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
+			{
+				taskYIELD();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
+
+		#if ( configUSE_IDLE_HOOK == 1 )
+		{
+			extern void vApplicationIdleHook( void );
+
+			/* Call the user defined function from within the idle task.  This
+			allows the application designer to add background functionality
+			without the overhead of a separate task.
+			NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
+			CALL A FUNCTION THAT MIGHT BLOCK. */
+			vApplicationIdleHook();
+		}
+		#endif /* configUSE_IDLE_HOOK */
+
+		/* This conditional compilation should use inequality to 0, not equality
+		to 1.  This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when
+		user defined low power mode	implementations require
+		configUSE_TICKLESS_IDLE to be set to a value other than 1. */
+		#if ( configUSE_TICKLESS_IDLE != 0 )
+		{
+		TickType_t xExpectedIdleTime;
+
+			/* It is not desirable to suspend then resume the scheduler on
+			each iteration of the idle task.  Therefore, a preliminary
+			test of the expected idle time is performed without the
+			scheduler suspended.  The result here is not necessarily
+			valid. */
+			xExpectedIdleTime = prvGetExpectedIdleTime();
+
+			if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+			{
+				vTaskSuspendAll();
+				{
+					/* Now the scheduler is suspended, the expected idle
+					time can be sampled again, and this time its value can
+					be used. */
+					configASSERT( xNextTaskUnblockTime >= xTickCount );
+					xExpectedIdleTime = prvGetExpectedIdleTime();
+
+					/* Define the following macro to set xExpectedIdleTime to 0
+					if the application does not want
+					portSUPPRESS_TICKS_AND_SLEEP() to be called. */
+					configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );
+
+					if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+					{
+						traceLOW_POWER_IDLE_BEGIN();
+						portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
+						traceLOW_POWER_IDLE_END();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_TICKLESS_IDLE */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE != 0 )
+
+	eSleepModeStatus eTaskConfirmSleepModeStatus( void )
+	{
+	/* The idle task exists in addition to the application tasks. */
+	const UBaseType_t uxNonApplicationTasks = 1;
+	eSleepModeStatus eReturn = eStandardSleep;
+
+		if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )
+		{
+			/* A task was made ready while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+		}
+		else if( xYieldPending != pdFALSE )
+		{
+			/* A yield was pended while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+		}
+		else
+		{
+			/* If all the tasks are in the suspended list (which might mean they
+			have an infinite block time rather than actually being suspended)
+			then it is safe to turn all clocks off and just wait for external
+			interrupts. */
+			if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )
+			{
+				eReturn = eNoTasksWaitingTimeout;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		return eReturn;
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue )
+	{
+	TCB_t *pxTCB;
+
+		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+		{
+			pxTCB = prvGetTCBFromHandle( xTaskToSet );
+			pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;
+		}
+	}
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex )
+	{
+	void *pvReturn = NULL;
+	TCB_t *pxTCB;
+
+		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+		{
+			pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+			pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];
+		}
+		else
+		{
+			pvReturn = NULL;
+		}
+
+		return pvReturn;
+	}
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( portUSING_MPU_WRAPPERS == 1 )
+
+	void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, const MemoryRegion_t * const xRegions )
+	{
+	TCB_t *pxTCB;
+
+		/* If null is passed in here then we are modifying the MPU settings of
+		the calling task. */
+		pxTCB = prvGetTCBFromHandle( xTaskToModify );
+
+		vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );
+	}
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseTaskLists( void )
+{
+UBaseType_t uxPriority;
+
+	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
+	{
+		vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
+	}
+
+	vListInitialise( &xDelayedTaskList1 );
+	vListInitialise( &xDelayedTaskList2 );
+	vListInitialise( &xPendingReadyList );
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		vListInitialise( &xTasksWaitingTermination );
+	}
+	#endif /* INCLUDE_vTaskDelete */
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		vListInitialise( &xSuspendedTaskList );
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+
+	/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
+	using list2. */
+	pxDelayedTaskList = &xDelayedTaskList1;
+	pxOverflowDelayedTaskList = &xDelayedTaskList2;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTasksWaitingTermination( void )
+{
+
+	/** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		TCB_t *pxTCB;
+
+		/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
+		being called too often in the idle task. */
+		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
+		{
+			taskENTER_CRITICAL();
+			{
+				pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+				--uxCurrentNumberOfTasks;
+				--uxDeletedTasksWaitingCleanUp;
+			}
+			taskEXIT_CRITICAL();
+
+			prvDeleteTCB( pxTCB );
+		}
+	}
+	#endif /* INCLUDE_vTaskDelete */
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TRACE_FACILITY == 1 )
+
+	void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState )
+	{
+	TCB_t *pxTCB;
+
+		/* xTask is NULL then get the state of the calling task. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB;
+		pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName [ 0 ] );
+		pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
+		pxTaskStatus->pxStackBase = pxTCB->pxStack;
+		pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;
+
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
+		}
+		#else
+		{
+			pxTaskStatus->uxBasePriority = 0;
+		}
+		#endif
+
+		#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		{
+			pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;
+		}
+		#else
+		{
+			pxTaskStatus->ulRunTimeCounter = 0;
+		}
+		#endif
+
+		/* Obtaining the task state is a little fiddly, so is only done if the
+		value of eState passed into this function is eInvalid - otherwise the
+		state is just set to whatever is passed in. */
+		if( eState != eInvalid )
+		{
+			if( pxTCB == pxCurrentTCB )
+			{
+				pxTaskStatus->eCurrentState = eRunning;
+			}
+			else
+			{
+				pxTaskStatus->eCurrentState = eState;
+
+				#if ( INCLUDE_vTaskSuspend == 1 )
+				{
+					/* If the task is in the suspended list then there is a
+					chance it is actually just blocked indefinitely - so really
+					it should be reported as being in the Blocked state. */
+					if( eState == eSuspended )
+					{
+						vTaskSuspendAll();
+						{
+							if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+							{
+								pxTaskStatus->eCurrentState = eBlocked;
+							}
+						}
+						( void ) xTaskResumeAll();
+					}
+				}
+				#endif /* INCLUDE_vTaskSuspend */
+			}
+		}
+		else
+		{
+			pxTaskStatus->eCurrentState = eTaskGetState( pxTCB );
+		}
+
+		/* Obtaining the stack space takes some time, so the xGetFreeStackSpace
+		parameter is provided to allow it to be skipped. */
+		if( xGetFreeStackSpace != pdFALSE )
+		{
+			#if ( portSTACK_GROWTH > 0 )
+			{
+				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );
+			}
+			#else
+			{
+				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );
+			}
+			#endif
+		}
+		else
+		{
+			pxTaskStatus->usStackHighWaterMark = 0;
+		}
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )
+	{
+	configLIST_VOLATILE TCB_t *pxNextTCB, *pxFirstTCB;
+	UBaseType_t uxTask = 0;
+
+		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+		{
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+			/* Populate an TaskStatus_t structure within the
+			pxTaskStatusArray array for each task that is referenced from
+			pxList.  See the definition of TaskStatus_t in task.h for the
+			meaning of each TaskStatus_t structure member. */
+			do
+			{
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+				vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
+				uxTask++;
+			} while( pxNextTCB != pxFirstTCB );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return uxTask;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+
+	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
+	{
+	uint32_t ulCount = 0U;
+
+		while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
+		{
+			pucStackByte -= portSTACK_GROWTH;
+			ulCount++;
+		}
+
+		ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
+
+		return ( configSTACK_DEPTH_TYPE ) ulCount;
+	}
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+
+	/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+	same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+	user to determine the return type.  It gets around the problem of the value
+	overflowing on 8-bit types without breaking backward compatibility for
+	applications that expect an 8-bit return type. */
+	configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	uint8_t *pucEndOfStack;
+	configSTACK_DEPTH_TYPE uxReturn;
+
+		/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are
+		the same except for their return type.  Using configSTACK_DEPTH_TYPE
+		allows the user to determine the return type.  It gets around the
+		problem of the value overflowing on 8-bit types without breaking
+		backward compatibility for applications that expect an 8-bit return
+		type. */
+
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		#if portSTACK_GROWTH < 0
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+		}
+		#else
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+		}
+		#endif
+
+		uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+
+	UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	uint8_t *pucEndOfStack;
+	UBaseType_t uxReturn;
+
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		#if portSTACK_GROWTH < 0
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+		}
+		#else
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+		}
+		#endif
+
+		uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB )
+	{
+		/* This call is required specifically for the TriCore port.  It must be
+		above the vPortFree() calls.  The call is also used by ports/demos that
+		want to allocate and clean RAM statically. */
+		portCLEAN_UP_TCB( pxTCB );
+
+		/* Free up the memory allocated by the scheduler for the task.  It is up
+		to the task to free any memory allocated at the application level. */
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			_reclaim_reent( &( pxTCB->xNewLib_reent ) );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
+		{
+			/* The task can only have been allocated dynamically - free both
+			the stack and TCB. */
+			vPortFree( pxTCB->pxStack );
+			vPortFree( pxTCB );
+		}
+		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+		{
+			/* The task could have been allocated statically or dynamically, so
+			check what was statically allocated before trying to free the
+			memory. */
+			if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
+			{
+				/* Both the stack and TCB were allocated dynamically, so both
+				must be freed. */
+				vPortFree( pxTCB->pxStack );
+				vPortFree( pxTCB );
+			}
+			else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
+			{
+				/* Only the stack was statically allocated, so the TCB is the
+				only memory that must be freed. */
+				vPortFree( pxTCB );
+			}
+			else
+			{
+				/* Neither the stack nor the TCB were allocated dynamically, so
+				nothing needs to be freed. */
+				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+	}
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+static void prvResetNextTaskUnblockTime( void )
+{
+TCB_t *pxTCB;
+
+	if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+	{
+		/* The new current delayed list is empty.  Set xNextTaskUnblockTime to
+		the maximum possible value so it is	extremely unlikely that the
+		if( xTickCount >= xNextTaskUnblockTime ) test will pass until
+		there is an item in the delayed list. */
+		xNextTaskUnblockTime = portMAX_DELAY;
+	}
+	else
+	{
+		/* The new current delayed list is not empty, get the value of
+		the item at the head of the delayed list.  This is the time at
+		which the task at the head of the delayed list should be removed
+		from the Blocked state. */
+		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+
+	TaskHandle_t xTaskGetCurrentTaskHandle( void )
+	{
+	TaskHandle_t xReturn;
+
+		/* A critical section is not required as this is not called from
+		an interrupt and the current TCB will always be the same for any
+		individual execution thread. */
+		xReturn = pxCurrentTCB;
+
+		return xReturn;
+	}
+
+#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+
+	BaseType_t xTaskGetSchedulerState( void )
+	{
+	BaseType_t xReturn;
+
+		if( xSchedulerRunning == pdFALSE )
+		{
+			xReturn = taskSCHEDULER_NOT_STARTED;
+		}
+		else
+		{
+			if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+			{
+				xReturn = taskSCHEDULER_RUNNING;
+			}
+			else
+			{
+				xReturn = taskSCHEDULER_SUSPENDED;
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
+	{
+	TCB_t * const pxMutexHolderTCB = pxMutexHolder;
+	BaseType_t xReturn = pdFALSE;
+
+		/* If the mutex was given back by an interrupt while the queue was
+		locked then the mutex holder might now be NULL.  _RB_ Is this still
+		needed as interrupts can no longer use mutexes? */
+		if( pxMutexHolder != NULL )
+		{
+			/* If the holder of the mutex has a priority below the priority of
+			the task attempting to obtain the mutex then it will temporarily
+			inherit the priority of the task attempting to obtain the mutex. */
+			if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
+			{
+				/* Adjust the mutex holder state to account for its new
+				priority.  Only reset the event list item value if the value is
+				not being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+				{
+					listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* If the task being modified is in the ready state it will need
+				to be moved into a new list. */
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
+				{
+					if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						taskRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Inherit the priority before being moved into the new list. */
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+					prvAddTaskToReadyList( pxMutexHolderTCB );
+				}
+				else
+				{
+					/* Just inherit the priority. */
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+				}
+
+				traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
+
+				/* Inheritance occurred. */
+				xReturn = pdTRUE;
+			}
+			else
+			{
+				if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
+				{
+					/* The base priority of the mutex holder is lower than the
+					priority of the task attempting to take the mutex, but the
+					current priority of the mutex holder is not lower than the
+					priority of the task attempting to take the mutex.
+					Therefore the mutex holder must have already inherited a
+					priority, but inheritance would have occurred if that had
+					not been the case. */
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
+	{
+	TCB_t * const pxTCB = pxMutexHolder;
+	BaseType_t xReturn = pdFALSE;
+
+		if( pxMutexHolder != NULL )
+		{
+			/* A task can only have an inherited priority if it holds the mutex.
+			If the mutex is held by a task then it cannot be given from an
+			interrupt, and if a mutex is given by the holding task then it must
+			be the running state task. */
+			configASSERT( pxTCB == pxCurrentTCB );
+			configASSERT( pxTCB->uxMutexesHeld );
+			( pxTCB->uxMutexesHeld )--;
+
+			/* Has the holder of the mutex inherited the priority of another
+			task? */
+			if( pxTCB->uxPriority != pxTCB->uxBasePriority )
+			{
+				/* Only disinherit if no other mutexes are held. */
+				if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
+				{
+					/* A task can only have an inherited priority if it holds
+					the mutex.  If the mutex is held by a task then it cannot be
+					given from an interrupt, and if a mutex is given by the
+					holding task then it must be the running state task.  Remove
+					the holding task from the ready list. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Disinherit the priority before adding the task into the
+					new	ready list. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					pxTCB->uxPriority = pxTCB->uxBasePriority;
+
+					/* Reset the event list item value.  It cannot be in use for
+					any other purpose if this task is running, and it must be
+					running to give back the mutex. */
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					prvAddTaskToReadyList( pxTCB );
+
+					/* Return true to indicate that a context switch is required.
+					This is only actually required in the corner case whereby
+					multiple mutexes were held and the mutexes were given back
+					in an order different to that in which they were taken.
+					If a context switch did not occur when the first mutex was
+					returned, even if a task was waiting on it, then a context
+					switch should occur when the last mutex is returned whether
+					a task is waiting on it or not. */
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
+	{
+	TCB_t * const pxTCB = pxMutexHolder;
+	UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
+	const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
+
+		if( pxMutexHolder != NULL )
+		{
+			/* If pxMutexHolder is not NULL then the holder must hold at least
+			one mutex. */
+			configASSERT( pxTCB->uxMutexesHeld );
+
+			/* Determine the priority to which the priority of the task that
+			holds the mutex should be set.  This will be the greater of the
+			holding task's base priority and the priority of the highest
+			priority task that is waiting to obtain the mutex. */
+			if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
+			{
+				uxPriorityToUse = uxHighestPriorityWaitingTask;
+			}
+			else
+			{
+				uxPriorityToUse = pxTCB->uxBasePriority;
+			}
+
+			/* Does the priority need to change? */
+			if( pxTCB->uxPriority != uxPriorityToUse )
+			{
+				/* Only disinherit if no other mutexes are held.  This is a
+				simplification in the priority inheritance implementation.  If
+				the task that holds the mutex is also holding other mutexes then
+				the other mutexes may have caused the priority inheritance. */
+				if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
+				{
+					/* If a task has timed out because it already holds the
+					mutex it was trying to obtain then it cannot of inherited
+					its own priority. */
+					configASSERT( pxTCB != pxCurrentTCB );
+
+					/* Disinherit the priority, remembering the previous
+					priority to facilitate determining the subject task's
+					state. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					uxPriorityUsedOnEntry = pxTCB->uxPriority;
+					pxTCB->uxPriority = uxPriorityToUse;
+
+					/* Only reset the event list item value if the value is not
+					being used for anything else. */
+					if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+					{
+						listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* If the running task is not the task that holds the mutex
+					then the task that holds the mutex could be in either the
+					Ready, Blocked or Suspended states.  Only remove the task
+					from its current state list if it is in the Ready state as
+					the task's priority is going to change and there is one
+					Ready list per priority. */
+					if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+					{
+						if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+						{
+							taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+
+						prvAddTaskToReadyList( pxTCB );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+	void vTaskEnterCritical( void )
+	{
+		portDISABLE_INTERRUPTS();
+
+		if( xSchedulerRunning != pdFALSE )
+		{
+			( pxCurrentTCB->uxCriticalNesting )++;
+
+			/* This is not the interrupt safe version of the enter critical
+			function so	assert() if it is being called from an interrupt
+			context.  Only API functions that end in "FromISR" can be used in an
+			interrupt.  Only assert if the critical nesting count is 1 to
+			protect against recursive calls if the assert function also uses a
+			critical section. */
+			if( pxCurrentTCB->uxCriticalNesting == 1 )
+			{
+				portASSERT_IF_IN_ISR();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+	void vTaskExitCritical( void )
+	{
+		if( xSchedulerRunning != pdFALSE )
+		{
+			if( pxCurrentTCB->uxCriticalNesting > 0U )
+			{
+				( pxCurrentTCB->uxCriticalNesting )--;
+
+				if( pxCurrentTCB->uxCriticalNesting == 0U )
+				{
+					portENABLE_INTERRUPTS();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName )
+	{
+	size_t x;
+
+		/* Start by copying the entire string. */
+		strcpy( pcBuffer, pcTaskName );
+
+		/* Pad the end of the string with spaces to ensure columns line up when
+		printed out. */
+		for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ )
+		{
+			pcBuffer[ x ] = ' ';
+		}
+
+		/* Terminate. */
+		pcBuffer[ x ] = ( char ) 0x00;
+
+		/* Return the new end of string. */
+		return &( pcBuffer[ x ] );
+	}
+
+#endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	void vTaskList( char * pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	UBaseType_t uxArraySize, x;
+	char cStatus;
+
+		/*
+		 * PLEASE NOTE:
+		 *
+		 * This function is provided for convenience only, and is used by many
+		 * of the demo applications.  Do not consider it to be part of the
+		 * scheduler.
+		 *
+		 * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+		 * uxTaskGetSystemState() output into a human readable table that
+		 * displays task names, states and stack usage.
+		 *
+		 * vTaskList() has a dependency on the sprintf() C library function that
+		 * might bloat the code size, use a lot of stack, and provide different
+		 * results on different platforms.  An alternative, tiny, third party,
+		 * and limited functionality implementation of sprintf() is provided in
+		 * many of the FreeRTOS/Demo sub-directories in a file called
+		 * printf-stdarg.c (note printf-stdarg.c does not provide a full
+		 * snprintf() implementation!).
+		 *
+		 * It is recommended that production systems call uxTaskGetSystemState()
+		 * directly to get access to raw stats data, rather than indirectly
+		 * through a call to vTaskList().
+		 */
+
+
+		/* Make sure the write buffer does not contain a string. */
+		*pcWriteBuffer = ( char ) 0x00;
+
+		/* Take a snapshot of the number of tasks in case it changes while this
+		function is executing. */
+		uxArraySize = uxCurrentNumberOfTasks;
+
+		/* Allocate an array index for each task.  NOTE!  if
+		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+		equate to NULL. */
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+
+		if( pxTaskStatusArray != NULL )
+		{
+			/* Generate the (binary) data. */
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );
+
+			/* Create a human readable table from the binary data. */
+			for( x = 0; x < uxArraySize; x++ )
+			{
+				switch( pxTaskStatusArray[ x ].eCurrentState )
+				{
+					case eRunning:		cStatus = tskRUNNING_CHAR;
+										break;
+
+					case eReady:		cStatus = tskREADY_CHAR;
+										break;
+
+					case eBlocked:		cStatus = tskBLOCKED_CHAR;
+										break;
+
+					case eSuspended:	cStatus = tskSUSPENDED_CHAR;
+										break;
+
+					case eDeleted:		cStatus = tskDELETED_CHAR;
+										break;
+
+					case eInvalid:		/* Fall through. */
+					default:			/* Should not get here, but it is included
+										to prevent static checking errors. */
+										cStatus = ( char ) 0x00;
+										break;
+				}
+
+				/* Write the task name to the string, padding with spaces so it
+				can be printed in tabular form more easily. */
+				pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+				/* Write the rest of the string. */
+				sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+				pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+			}
+
+			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+			is 0 then vPortFree() will be #defined to nothing. */
+			vPortFree( pxTaskStatusArray );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*----------------------------------------------------------*/
+
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	void vTaskGetRunTimeStats( char *pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	UBaseType_t uxArraySize, x;
+	uint32_t ulTotalTime, ulStatsAsPercentage;
+
+		#if( configUSE_TRACE_FACILITY != 1 )
+		{
+			#error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().
+		}
+		#endif
+
+		/*
+		 * PLEASE NOTE:
+		 *
+		 * This function is provided for convenience only, and is used by many
+		 * of the demo applications.  Do not consider it to be part of the
+		 * scheduler.
+		 *
+		 * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part
+		 * of the uxTaskGetSystemState() output into a human readable table that
+		 * displays the amount of time each task has spent in the Running state
+		 * in both absolute and percentage terms.
+		 *
+		 * vTaskGetRunTimeStats() has a dependency on the sprintf() C library
+		 * function that might bloat the code size, use a lot of stack, and
+		 * provide different results on different platforms.  An alternative,
+		 * tiny, third party, and limited functionality implementation of
+		 * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in
+		 * a file called printf-stdarg.c (note printf-stdarg.c does not provide
+		 * a full snprintf() implementation!).
+		 *
+		 * It is recommended that production systems call uxTaskGetSystemState()
+		 * directly to get access to raw stats data, rather than indirectly
+		 * through a call to vTaskGetRunTimeStats().
+		 */
+
+		/* Make sure the write buffer does not contain a string. */
+		*pcWriteBuffer = ( char ) 0x00;
+
+		/* Take a snapshot of the number of tasks in case it changes while this
+		function is executing. */
+		uxArraySize = uxCurrentNumberOfTasks;
+
+		/* Allocate an array index for each task.  NOTE!  If
+		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+		equate to NULL. */
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+
+		if( pxTaskStatusArray != NULL )
+		{
+			/* Generate the (binary) data. */
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );
+
+			/* For percentage calculations. */
+			ulTotalTime /= 100UL;
+
+			/* Avoid divide by zero errors. */
+			if( ulTotalTime > 0UL )
+			{
+				/* Create a human readable table from the binary data. */
+				for( x = 0; x < uxArraySize; x++ )
+				{
+					/* What percentage of the total run time has the task used?
+					This will always be rounded down to the nearest integer.
+					ulTotalRunTimeDiv100 has already been divided by 100. */
+					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;
+
+					/* Write the task name to the string, padding with
+					spaces so it can be printed in tabular form more
+					easily. */
+					pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+					if( ulStatsAsPercentage > 0UL )
+					{
+						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+						{
+							sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+						}
+						#else
+						{
+							/* sizeof( int ) == sizeof( long ) so a smaller
+							printf() library can be used. */
+							sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+						}
+						#endif
+					}
+					else
+					{
+						/* If the percentage is zero here then the task has
+						consumed less than 1% of the total run time. */
+						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+						{
+							sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter );
+						}
+						#else
+						{
+							/* sizeof( int ) == sizeof( long ) so a smaller
+							printf() library can be used. */
+							sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+						}
+						#endif
+					}
+
+					pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+			is 0 then vPortFree() will be #defined to nothing. */
+			vPortFree( pxTaskStatusArray );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+TickType_t uxTaskResetEventItemValue( void )
+{
+TickType_t uxReturn;
+
+	uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );
+
+	/* Reset the event list item to its normal value - so it can be used with
+	queues and semaphores. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	TaskHandle_t pvTaskIncrementMutexHeldCount( void )
+	{
+		/* If xSemaphoreCreateMutex() is called before any tasks have been created
+		then pxCurrentTCB will be NULL. */
+		if( pxCurrentTCB != NULL )
+		{
+			( pxCurrentTCB->uxMutexesHeld )++;
+		}
+
+		return pxCurrentTCB;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )
+	{
+	uint32_t ulReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* Only block if the notification count is not already non-zero. */
+			if( pxCurrentTCB->ulNotifiedValue == 0UL )
+			{
+				/* Mark this task as waiting for a notification. */
+				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+					traceTASK_NOTIFY_TAKE_BLOCK();
+
+					/* All ports are written to allow a yield in a critical
+					section (some will yield immediately, others wait until the
+					critical section exits) - but it is not something that
+					application code should ever do. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		taskENTER_CRITICAL();
+		{
+			traceTASK_NOTIFY_TAKE();
+			ulReturn = pxCurrentTCB->ulNotifiedValue;
+
+			if( ulReturn != 0UL )
+			{
+				if( xClearCountOnExit != pdFALSE )
+				{
+					pxCurrentTCB->ulNotifiedValue = 0UL;
+				}
+				else
+				{
+					pxCurrentTCB->ulNotifiedValue = ulReturn - ( uint32_t ) 1;
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+		}
+		taskEXIT_CRITICAL();
+
+		return ulReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* Only block if a notification is not already pending. */
+			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
+			{
+				/* Clear bits in the task's notification value as bits may get
+				set	by the notifying task or interrupt.  This can be used to
+				clear the value to zero. */
+				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;
+
+				/* Mark this task as waiting for a notification. */
+				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+					traceTASK_NOTIFY_WAIT_BLOCK();
+
+					/* All ports are written to allow a yield in a critical
+					section (some will yield immediately, others wait until the
+					critical section exits) - but it is not something that
+					application code should ever do. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		taskENTER_CRITICAL();
+		{
+			traceTASK_NOTIFY_WAIT();
+
+			if( pulNotificationValue != NULL )
+			{
+				/* Output the current notification value, which may or may not
+				have changed. */
+				*pulNotificationValue = pxCurrentTCB->ulNotifiedValue;
+			}
+
+			/* If ucNotifyValue is set then either the task never entered the
+			blocked state (because a notification was already pending) or the
+			task unblocked because of a notification.  Otherwise the task
+			unblocked because of a timeout. */
+			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
+			{
+				/* A notification was not received. */
+				xReturn = pdFALSE;
+			}
+			else
+			{
+				/* A notification was already pending or a notification was
+				received while the task was waiting. */
+				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;
+				xReturn = pdTRUE;
+			}
+
+			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )
+	{
+	TCB_t * pxTCB;
+	BaseType_t xReturn = pdPASS;
+	uint8_t ucOriginalNotifyState;
+
+		configASSERT( xTaskToNotify );
+		pxTCB = xTaskToNotify;
+
+		taskENTER_CRITICAL();
+		{
+			if( pulPreviousNotificationValue != NULL )
+			{
+				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+			}
+
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			switch( eAction )
+			{
+				case eSetBits	:
+					pxTCB->ulNotifiedValue |= ulValue;
+					break;
+
+				case eIncrement	:
+					( pxTCB->ulNotifiedValue )++;
+					break;
+
+				case eSetValueWithOverwrite	:
+					pxTCB->ulNotifiedValue = ulValue;
+					break;
+
+				case eSetValueWithoutOverwrite :
+					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+					{
+						pxTCB->ulNotifiedValue = ulValue;
+					}
+					else
+					{
+						/* The value could not be written to the task. */
+						xReturn = pdFAIL;
+					}
+					break;
+
+				case eNoAction:
+					/* The task is being notified without its notify value being
+					updated. */
+					break;
+
+				default:
+					/* Should not get here if all enums are handled.
+					Artificially force an assert by testing a value the
+					compiler can't assume is const. */
+					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+
+					break;
+			}
+
+			traceTASK_NOTIFY();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+				prvAddTaskToReadyList( pxTCB );
+
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				#if( configUSE_TICKLESS_IDLE != 0 )
+				{
+					/* If a task is blocked waiting for a notification then
+					xNextTaskUnblockTime might be set to the blocked task's time
+					out time.  If the task is unblocked for a reason other than
+					a timeout xNextTaskUnblockTime is normally left unchanged,
+					because it will automatically get reset to a new value when
+					the tick count equals xNextTaskUnblockTime.  However if
+					tickless idling is used it might be more important to enter
+					sleep mode at the earliest possible time - so reset
+					xNextTaskUnblockTime here to ensure it is updated at the
+					earliest possible time. */
+					prvResetNextTaskUnblockTime();
+				}
+				#endif
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	TCB_t * pxTCB;
+	uint8_t ucOriginalNotifyState;
+	BaseType_t xReturn = pdPASS;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToNotify );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		pxTCB = xTaskToNotify;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			if( pulPreviousNotificationValue != NULL )
+			{
+				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+			}
+
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			switch( eAction )
+			{
+				case eSetBits	:
+					pxTCB->ulNotifiedValue |= ulValue;
+					break;
+
+				case eIncrement	:
+					( pxTCB->ulNotifiedValue )++;
+					break;
+
+				case eSetValueWithOverwrite	:
+					pxTCB->ulNotifiedValue = ulValue;
+					break;
+
+				case eSetValueWithoutOverwrite :
+					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+					{
+						pxTCB->ulNotifiedValue = ulValue;
+					}
+					else
+					{
+						/* The value could not be written to the task. */
+						xReturn = pdFAIL;
+					}
+					break;
+
+				case eNoAction :
+					/* The task is being notified without its notify value being
+					updated. */
+					break;
+
+				default:
+					/* Should not get here if all enums are handled.
+					Artificially force an assert by testing a value the
+					compiler can't assume is const. */
+					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+					break;
+			}
+
+			traceTASK_NOTIFY_FROM_ISR();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed and ready lists cannot be accessed, so hold
+					this task pending until the scheduler is resumed. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					if( pxHigherPriorityTaskWoken != NULL )
+					{
+						*pxHigherPriorityTaskWoken = pdTRUE;
+					}
+
+					/* Mark that a yield is pending in case the user is not
+					using the "xHigherPriorityTaskWoken" parameter to an ISR
+					safe FreeRTOS function. */
+					xYieldPending = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	TCB_t * pxTCB;
+	uint8_t ucOriginalNotifyState;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToNotify );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		pxTCB = xTaskToNotify;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			/* 'Giving' is equivalent to incrementing a count in a counting
+			semaphore. */
+			( pxTCB->ulNotifiedValue )++;
+
+			traceTASK_NOTIFY_GIVE_FROM_ISR();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed and ready lists cannot be accessed, so hold
+					this task pending until the scheduler is resumed. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					if( pxHigherPriorityTaskWoken != NULL )
+					{
+						*pxHigherPriorityTaskWoken = pdTRUE;
+					}
+
+					/* Mark that a yield is pending in case the user is not
+					using the "xHigherPriorityTaskWoken" parameter in an ISR
+					safe FreeRTOS function. */
+					xYieldPending = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	BaseType_t xReturn;
+
+		/* If null is passed in here then it is the calling task that is having
+		its notification state cleared. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		taskENTER_CRITICAL();
+		{
+			if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED )
+			{
+				pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+				xReturn = pdPASS;
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+	TickType_t xTaskGetIdleRunTimeCounter( void )
+	{
+		return xIdleTaskHandle->ulRunTimeCounter;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
+{
+TickType_t xTimeToWake;
+const TickType_t xConstTickCount = xTickCount;
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		/* About to enter a delayed list, so ensure the ucDelayAborted flag is
+		reset to pdFALSE so it can be detected as having been set to pdTRUE
+		when the task leaves the Blocked state. */
+		pxCurrentTCB->ucDelayAborted = pdFALSE;
+	}
+	#endif
+
+	/* Remove the task from the ready list before adding it to the blocked list
+	as the same list item is used for both lists. */
+	if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+	{
+		/* The current task must be in a ready list, so there is no need to
+		check, and the port reset macro can be called directly. */
+		portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task.  pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
+		{
+			/* Add the task to the suspended task list instead of a delayed task
+			list to ensure it is not woken by a timing event.  It will block
+			indefinitely. */
+			vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
+		}
+		else
+		{
+			/* Calculate the time at which the task should be woken if the event
+			does not occur.  This may overflow but this doesn't matter, the
+			kernel will manage it correctly. */
+			xTimeToWake = xConstTickCount + xTicksToWait;
+
+			/* The list item will be inserted in wake time order. */
+			listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+			if( xTimeToWake < xConstTickCount )
+			{
+				/* Wake time has overflowed.  Place this item in the overflow
+				list. */
+				vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+			}
+			else
+			{
+				/* The wake time has not overflowed, so the current block list
+				is used. */
+				vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+				/* If the task entering the blocked state was placed at the
+				head of the list of blocked tasks then xNextTaskUnblockTime
+				needs to be updated too. */
+				if( xTimeToWake < xNextTaskUnblockTime )
+				{
+					xNextTaskUnblockTime = xTimeToWake;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+	}
+	#else /* INCLUDE_vTaskSuspend */
+	{
+		/* Calculate the time at which the task should be woken if the event
+		does not occur.  This may overflow but this doesn't matter, the kernel
+		will manage it correctly. */
+		xTimeToWake = xConstTickCount + xTicksToWait;
+
+		/* The list item will be inserted in wake time order. */
+		listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+		if( xTimeToWake < xConstTickCount )
+		{
+			/* Wake time has overflowed.  Place this item in the overflow list. */
+			vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+		}
+		else
+		{
+			/* The wake time has not overflowed, so the current block list is used. */
+			vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+			/* If the task entering the blocked state was placed at the head of the
+			list of blocked tasks then xNextTaskUnblockTime needs to be updated
+			too. */
+			if( xTimeToWake < xNextTaskUnblockTime )
+			{
+				xNextTaskUnblockTime = xTimeToWake;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
+		( void ) xCanBlockIndefinitely;
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+}
+
+/* Code below here allows additional code to be inserted into this source file,
+especially where access to file scope functions and data is needed (for example
+when performing module tests). */
+
+#ifdef FREERTOS_MODULE_TEST
+	#include "tasks_test_access_functions.h"
+#endif
+
+
+#if( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 )
+
+	#include "freertos_tasks_c_additions.h"
+
+	#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+		static void freertos_tasks_c_additions_init( void )
+		{
+			FREERTOS_TASKS_C_ADDITIONS_INIT();
+		}
+	#endif
+
+#endif
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/Source/timers.c b/FreeRTOSv10.2.1/FreeRTOS/Source/timers.c
new file mode 100644
index 0000000..80c8d9b
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/Source/timers.c
@@ -0,0 +1,1102 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+
+#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )
+	#error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
+#endif
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */
+
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality.  This #if is closed at the very bottom
+of this file.  If you want to include software timer functionality then ensure
+configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#if ( configUSE_TIMERS == 1 )
+
+/* Misc definitions. */
+#define tmrNO_DELAY		( TickType_t ) 0U
+
+/* The name assigned to the timer service task.  This can be overridden by
+defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configTIMER_SERVICE_TASK_NAME
+	#define configTIMER_SERVICE_TASK_NAME "Tmr Svc"
+#endif
+
+/* Bit definitions used in the ucStatus member of a timer structure. */
+#define tmrSTATUS_IS_ACTIVE					( ( uint8_t ) 0x01 )
+#define tmrSTATUS_IS_STATICALLY_ALLOCATED	( ( uint8_t ) 0x02 )
+#define tmrSTATUS_IS_AUTORELOAD				( ( uint8_t ) 0x04 )
+
+/* The definition of the timers themselves. */
+typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	const char				*pcTimerName;		/*<< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	ListItem_t				xTimerListItem;		/*<< Standard linked list item as used by all kernel features for event management. */
+	TickType_t				xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */
+	void 					*pvTimerID;			/*<< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */
+	TimerCallbackFunction_t	pxCallbackFunction;	/*<< The function that will be called when the timer expires. */
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t			uxTimerNumber;		/*<< An ID assigned by trace tools such as FreeRTOS+Trace */
+	#endif
+	uint8_t 				ucStatus;			/*<< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */
+} xTIMER;
+
+/* The old xTIMER name is maintained above then typedefed to the new Timer_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xTIMER Timer_t;
+
+/* The definition of messages that can be sent and received on the timer queue.
+Two types of message can be queued - messages that manipulate a software timer,
+and messages that request the execution of a non-timer related callback.  The
+two message types are defined in two separate structures, xTimerParametersType
+and xCallbackParametersType respectively. */
+typedef struct tmrTimerParameters
+{
+	TickType_t			xMessageValue;		/*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */
+	Timer_t *			pxTimer;			/*<< The timer to which the command will be applied. */
+} TimerParameter_t;
+
+
+typedef struct tmrCallbackParameters
+{
+	PendedFunction_t	pxCallbackFunction;	/* << The callback function to execute. */
+	void *pvParameter1;						/* << The value that will be used as the callback functions first parameter. */
+	uint32_t ulParameter2;					/* << The value that will be used as the callback functions second parameter. */
+} CallbackParameters_t;
+
+/* The structure that contains the two message types, along with an identifier
+that is used to determine which message type is valid. */
+typedef struct tmrTimerQueueMessage
+{
+	BaseType_t			xMessageID;			/*<< The command being sent to the timer service task. */
+	union
+	{
+		TimerParameter_t xTimerParameters;
+
+		/* Don't include xCallbackParameters if it is not going to be used as
+		it makes the structure (and therefore the timer queue) larger. */
+		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+			CallbackParameters_t xCallbackParameters;
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+	} u;
+} DaemonTaskMessage_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
+
+/* The list in which active timers are stored.  Timers are referenced in expire
+time order, with the nearest expiry time at the front of the list.  Only the
+timer service task is allowed to access these lists.
+xActiveTimerList1 and xActiveTimerList2 could be at function scope but that
+breaks some kernel aware debuggers, and debuggers that reply on removing the
+static qualifier. */
+PRIVILEGED_DATA static List_t xActiveTimerList1;
+PRIVILEGED_DATA static List_t xActiveTimerList2;
+PRIVILEGED_DATA static List_t *pxCurrentTimerList;
+PRIVILEGED_DATA static List_t *pxOverflowTimerList;
+
+/* A queue that is used to send commands to the timer service task. */
+PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;
+PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	/* If static allocation is supported then the application must provide the
+	following callback function - which enables the application to optionally
+	provide the memory that will be used by the timer task as the task's stack
+	and TCB. */
+	extern void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize );
+
+#endif
+
+/*
+ * Initialise the infrastructure used by the timer service task if it has not
+ * been initialised already.
+ */
+static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The timer service task (daemon).  Timer functionality is controlled by this
+ * task.  Other tasks communicate with the timer service task using the
+ * xTimerQueue queue.
+ */
+static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by the timer service task to interpret and process a command it
+ * received on the timer queue.
+ */
+static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,
+ * depending on if the expire time causes a timer counter overflow.
+ */
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;
+
+/*
+ * An active timer has reached its expire time.  Reload the timer if it is an
+ * auto reload timer, then call its callback.
+ */
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;
+
+/*
+ * The tick count has overflowed.  Switch the timer lists after ensuring the
+ * current timer list does not still reference some timers.
+ */
+static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE
+ * if a tick count overflow occurred since prvSampleTimeNow() was last called.
+ */
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the timer list contains any active timers then return the expire time of
+ * the timer that will expire first and set *pxListWasEmpty to false.  If the
+ * timer list does not contain any timers then return 0 and set *pxListWasEmpty
+ * to pdTRUE.
+ */
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a timer has expired, process it.  Otherwise, block the timer service task
+ * until either a timer does expire or a command is received.
+ */
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a Timer_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const TickType_t xTimerPeriodInTicks,
+									const UBaseType_t uxAutoReload,
+									void * const pvTimerID,
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerCreateTimerTask( void )
+{
+BaseType_t xReturn = pdFAIL;
+
+	/* This function is called when the scheduler is started if
+	configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
+	timer service task has been created/initialised.  If timers have already
+	been created then the initialisation will already have been performed. */
+	prvCheckForValidListAndQueue();
+
+	if( xTimerQueue != NULL )
+	{
+		#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+		{
+			StaticTask_t *pxTimerTaskTCBBuffer = NULL;
+			StackType_t *pxTimerTaskStackBuffer = NULL;
+			uint32_t ulTimerTaskStackSize;
+
+			vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
+			xTimerTaskHandle = xTaskCreateStatic(	prvTimerTask,
+													configTIMER_SERVICE_TASK_NAME,
+													ulTimerTaskStackSize,
+													NULL,
+													( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+													pxTimerTaskStackBuffer,
+													pxTimerTaskTCBBuffer );
+
+			if( xTimerTaskHandle != NULL )
+			{
+				xReturn = pdPASS;
+			}
+		}
+		#else
+		{
+			xReturn = xTaskCreate(	prvTimerTask,
+									configTIMER_SERVICE_TASK_NAME,
+									configTIMER_TASK_STACK_DEPTH,
+									NULL,
+									( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+									&xTimerTaskHandle );
+		}
+		#endif /* configSUPPORT_STATIC_ALLOCATION */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	configASSERT( xReturn );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+								const TickType_t xTimerPeriodInTicks,
+								const UBaseType_t uxAutoReload,
+								void * const pvTimerID,
+								TimerCallbackFunction_t pxCallbackFunction )
+	{
+	Timer_t *pxNewTimer;
+
+		pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */
+
+		if( pxNewTimer != NULL )
+		{
+			/* Status is thus far zero as the timer is not created statically
+			and has not been started.  The autoreload bit may get set in
+			prvInitialiseNewTimer. */
+			pxNewTimer->ucStatus = 0x00;
+			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+		}
+
+		return pxNewTimer;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+										const TickType_t xTimerPeriodInTicks,
+										const UBaseType_t uxAutoReload,
+										void * const pvTimerID,
+										TimerCallbackFunction_t pxCallbackFunction,
+										StaticTimer_t *pxTimerBuffer )
+	{
+	Timer_t *pxNewTimer;
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTimer_t equals the size of the real timer
+			structure. */
+			volatile size_t xSize = sizeof( StaticTimer_t );
+			configASSERT( xSize == sizeof( Timer_t ) );
+			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+		/* A pointer to a StaticTimer_t structure MUST be provided, use it. */
+		configASSERT( pxTimerBuffer );
+		pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */
+
+		if( pxNewTimer != NULL )
+		{
+			/* Timers can be created statically or dynamically so note this
+			timer was created statically in case it is later deleted.  The
+			autoreload bit may get set in prvInitialiseNewTimer(). */
+			pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED;
+
+			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+		}
+
+		return pxNewTimer;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const TickType_t xTimerPeriodInTicks,
+									const UBaseType_t uxAutoReload,
+									void * const pvTimerID,
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer )
+{
+	/* 0 is not a valid value for xTimerPeriodInTicks. */
+	configASSERT( ( xTimerPeriodInTicks > 0 ) );
+
+	if( pxNewTimer != NULL )
+	{
+		/* Ensure the infrastructure used by the timer service task has been
+		created/initialised. */
+		prvCheckForValidListAndQueue();
+
+		/* Initialise the timer structure members using the function
+		parameters. */
+		pxNewTimer->pcTimerName = pcTimerName;
+		pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
+		pxNewTimer->pvTimerID = pvTimerID;
+		pxNewTimer->pxCallbackFunction = pxCallbackFunction;
+		vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
+		if( uxAutoReload != pdFALSE )
+		{
+			pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+		}
+		traceTIMER_CREATE( pxNewTimer );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
+{
+BaseType_t xReturn = pdFAIL;
+DaemonTaskMessage_t xMessage;
+
+	configASSERT( xTimer );
+
+	/* Send a message to the timer service task to perform a particular action
+	on a particular timer definition. */
+	if( xTimerQueue != NULL )
+	{
+		/* Send a command to the timer service task to start the xTimer timer. */
+		xMessage.xMessageID = xCommandID;
+		xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
+		xMessage.u.xTimerParameters.pxTimer = xTimer;
+
+		if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
+		{
+			if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+			}
+			else
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
+			}
+		}
+		else
+		{
+			xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+		}
+
+		traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
+{
+	/* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been
+	started, then xTimerTaskHandle will be NULL. */
+	configASSERT( ( xTimerTaskHandle != NULL ) );
+	return xTimerTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer )
+{
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+	return pxTimer->xTimerPeriodInTicks;
+}
+/*-----------------------------------------------------------*/
+
+void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload )
+{
+Timer_t * pxTimer =  xTimer;
+
+	configASSERT( xTimer );
+	taskENTER_CRITICAL();
+	{
+		if( uxAutoReload != pdFALSE )
+		{
+			pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+		}
+		else
+		{
+			pxTimer->ucStatus &= ~tmrSTATUS_IS_AUTORELOAD;
+		}
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )
+{
+Timer_t * pxTimer =  xTimer;
+TickType_t xReturn;
+
+	configASSERT( xTimer );
+	xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+	return pxTimer->pcTimerName;
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
+{
+BaseType_t xResult;
+Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+	/* Remove the timer from the list of active timers.  A check has already
+	been performed to ensure the list is not empty. */
+	( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+	traceTIMER_EXPIRED( pxTimer );
+
+	/* If the timer is an auto reload timer then calculate the next
+	expiry time and re-insert the timer in the list of active timers. */
+	if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+	{
+		/* The timer is inserted into a list using a time relative to anything
+		other than the current time.  It will therefore be inserted into the
+		correct list relative to the time this task thinks it is now. */
+		if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
+		{
+			/* The timer expired before it was added to the active timer
+			list.  Reload it now.  */
+			xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+			configASSERT( xResult );
+			( void ) xResult;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Call the timer callback. */
+	pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( prvTimerTask, pvParameters )
+{
+TickType_t xNextExpireTime;
+BaseType_t xListWasEmpty;
+
+	/* Just to avoid compiler warnings. */
+	( void ) pvParameters;
+
+	#if( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 )
+	{
+		extern void vApplicationDaemonTaskStartupHook( void );
+
+		/* Allow the application writer to execute some code in the context of
+		this task at the point the task starts executing.  This is useful if the
+		application includes initialisation code that would benefit from
+		executing after the scheduler has been started. */
+		vApplicationDaemonTaskStartupHook();
+	}
+	#endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */
+
+	for( ;; )
+	{
+		/* Query the timers list to see if it contains any timers, and if so,
+		obtain the time at which the next timer will expire. */
+		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
+
+		/* If a timer has expired, process it.  Otherwise, block this task
+		until either a timer does expire, or a command is received. */
+		prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
+
+		/* Empty the command queue. */
+		prvProcessReceivedCommands();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
+{
+TickType_t xTimeNow;
+BaseType_t xTimerListsWereSwitched;
+
+	vTaskSuspendAll();
+	{
+		/* Obtain the time now to make an assessment as to whether the timer
+		has expired or not.  If obtaining the time causes the lists to switch
+		then don't process this timer as any timers that remained in the list
+		when the lists were switched will have been processed within the
+		prvSampleTimeNow() function. */
+		xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+		if( xTimerListsWereSwitched == pdFALSE )
+		{
+			/* The tick count has not overflowed, has the timer expired? */
+			if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
+			{
+				( void ) xTaskResumeAll();
+				prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
+			}
+			else
+			{
+				/* The tick count has not overflowed, and the next expire
+				time has not been reached yet.  This task should therefore
+				block to wait for the next expire time or a command to be
+				received - whichever comes first.  The following line cannot
+				be reached unless xNextExpireTime > xTimeNow, except in the
+				case when the current timer list is empty. */
+				if( xListWasEmpty != pdFALSE )
+				{
+					/* The current timer list is empty - is the overflow list
+					also empty? */
+					xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
+				}
+
+				vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
+
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					/* Yield to wait for either a command to arrive, or the
+					block time to expire.  If a command arrived between the
+					critical section being exited and this yield then the yield
+					will not cause the task to block. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			( void ) xTaskResumeAll();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
+{
+TickType_t xNextExpireTime;
+
+	/* Timers are listed in expiry time order, with the head of the list
+	referencing the task that will expire first.  Obtain the time at which
+	the timer with the nearest expiry time will expire.  If there are no
+	active timers then just set the next expire time to 0.  That will cause
+	this task to unblock when the tick count overflows, at which point the
+	timer lists will be switched and the next expiry time can be
+	re-assessed.  */
+	*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
+	if( *pxListWasEmpty == pdFALSE )
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+	}
+	else
+	{
+		/* Ensure the task unblocks when the tick count rolls over. */
+		xNextExpireTime = ( TickType_t ) 0U;
+	}
+
+	return xNextExpireTime;
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
+{
+TickType_t xTimeNow;
+PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
+
+	xTimeNow = xTaskGetTickCount();
+
+	if( xTimeNow < xLastTime )
+	{
+		prvSwitchTimerLists();
+		*pxTimerListsWereSwitched = pdTRUE;
+	}
+	else
+	{
+		*pxTimerListsWereSwitched = pdFALSE;
+	}
+
+	xLastTime = xTimeNow;
+
+	return xTimeNow;
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
+{
+BaseType_t xProcessTimerNow = pdFALSE;
+
+	listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
+	listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+
+	if( xNextExpiryTime <= xTimeNow )
+	{
+		/* Has the expiry time elapsed between the command to start/reset a
+		timer was issued, and the time the command was processed? */
+		if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+		{
+			/* The time between a command being issued and the command being
+			processed actually exceeds the timers period.  */
+			xProcessTimerNow = pdTRUE;
+		}
+		else
+		{
+			vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
+		}
+	}
+	else
+	{
+		if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
+		{
+			/* If, since the command was issued, the tick count has overflowed
+			but the expiry time has not, then the timer must have already passed
+			its expiry time and should be processed immediately. */
+			xProcessTimerNow = pdTRUE;
+		}
+		else
+		{
+			vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+		}
+	}
+
+	return xProcessTimerNow;
+}
+/*-----------------------------------------------------------*/
+
+static void	prvProcessReceivedCommands( void )
+{
+DaemonTaskMessage_t xMessage;
+Timer_t *pxTimer;
+BaseType_t xTimerListsWereSwitched, xResult;
+TickType_t xTimeNow;
+
+	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
+	{
+		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+		{
+			/* Negative commands are pended function calls rather than timer
+			commands. */
+			if( xMessage.xMessageID < ( BaseType_t ) 0 )
+			{
+				const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
+
+				/* The timer uses the xCallbackParameters member to request a
+				callback be executed.  Check the callback is not NULL. */
+				configASSERT( pxCallback );
+
+				/* Call the function. */
+				pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+
+		/* Commands that are positive are timer commands rather than pended
+		function calls. */
+		if( xMessage.xMessageID >= ( BaseType_t ) 0 )
+		{
+			/* The messages uses the xTimerParameters member to work on a
+			software timer. */
+			pxTimer = xMessage.u.xTimerParameters.pxTimer;
+
+			if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
+			{
+				/* The timer is in a list, remove it. */
+				( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );
+
+			/* In this case the xTimerListsWereSwitched parameter is not used, but
+			it must be present in the function call.  prvSampleTimeNow() must be
+			called after the message is received from xTimerQueue so there is no
+			possibility of a higher priority task adding a message to the message
+			queue with a time that is ahead of the timer daemon task (because it
+			pre-empted the timer daemon task after the xTimeNow value was set). */
+			xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+
+			switch( xMessage.xMessageID )
+			{
+				case tmrCOMMAND_START :
+				case tmrCOMMAND_START_FROM_ISR :
+				case tmrCOMMAND_RESET :
+				case tmrCOMMAND_RESET_FROM_ISR :
+				case tmrCOMMAND_START_DONT_TRACE :
+					/* Start or restart a timer. */
+					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+					if( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
+					{
+						/* The timer expired before it was added to the active
+						timer list.  Process it now. */
+						pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+						traceTIMER_EXPIRED( pxTimer );
+
+						if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+						{
+							xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
+							configASSERT( xResult );
+							( void ) xResult;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					break;
+
+				case tmrCOMMAND_STOP :
+				case tmrCOMMAND_STOP_FROM_ISR :
+					/* The timer has already been removed from the active list. */
+					pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+					break;
+
+				case tmrCOMMAND_CHANGE_PERIOD :
+				case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
+					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+					pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
+					configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
+
+					/* The new period does not really have a reference, and can
+					be longer or shorter than the old one.  The command time is
+					therefore set to the current time, and as the period cannot
+					be zero the next expiry time can only be in the future,
+					meaning (unlike for the xTimerStart() case above) there is
+					no fail case that needs to be handled here. */
+					( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
+					break;
+
+				case tmrCOMMAND_DELETE :
+					#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+					{
+						/* The timer has already been removed from the active list,
+						just free up the memory if the memory was dynamically
+						allocated. */
+						if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
+						{
+							vPortFree( pxTimer );
+						}
+						else
+						{
+							pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+						}
+					}
+					#else
+					{
+						/* If dynamic allocation is not enabled, the memory
+						could not have been dynamically allocated. So there is
+						no need to free the memory - just mark the timer as
+						"not active". */
+						pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+					}
+					#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+					break;
+
+				default	:
+					/* Don't expect to get here. */
+					break;
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSwitchTimerLists( void )
+{
+TickType_t xNextExpireTime, xReloadTime;
+List_t *pxTemp;
+Timer_t *pxTimer;
+BaseType_t xResult;
+
+	/* The tick count has overflowed.  The timer lists must be switched.
+	If there are any timers still referenced from the current timer list
+	then they must have expired and should be processed before the lists
+	are switched. */
+	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+
+		/* Remove the timer from the list. */
+		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+		traceTIMER_EXPIRED( pxTimer );
+
+		/* Execute its callback, then send a command to restart the timer if
+		it is an auto-reload timer.  It cannot be restarted here as the lists
+		have not yet been switched. */
+		pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+		{
+			/* Calculate the reload value, and if the reload value results in
+			the timer going into the same timer list then it has already expired
+			and the timer should be re-inserted into the current list so it is
+			processed again within this loop.  Otherwise a command should be sent
+			to restart the timer to ensure it is only inserted into a list after
+			the lists have been swapped. */
+			xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
+			if( xReloadTime > xNextExpireTime )
+			{
+				listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
+				listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+				vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+			}
+			else
+			{
+				xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+				configASSERT( xResult );
+				( void ) xResult;
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxTemp = pxCurrentTimerList;
+	pxCurrentTimerList = pxOverflowTimerList;
+	pxOverflowTimerList = pxTemp;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckForValidListAndQueue( void )
+{
+	/* Check that the list from which active timers are referenced, and the
+	queue used to communicate with the timer service, have been
+	initialised. */
+	taskENTER_CRITICAL();
+	{
+		if( xTimerQueue == NULL )
+		{
+			vListInitialise( &xActiveTimerList1 );
+			vListInitialise( &xActiveTimerList2 );
+			pxCurrentTimerList = &xActiveTimerList1;
+			pxOverflowTimerList = &xActiveTimerList2;
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* The timer queue is allocated statically in case
+				configSUPPORT_DYNAMIC_ALLOCATION is 0. */
+				static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+				static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+
+				xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
+			}
+			#else
+			{
+				xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );
+			}
+			#endif
+
+			#if ( configQUEUE_REGISTRY_SIZE > 0 )
+			{
+				if( xTimerQueue != NULL )
+				{
+					vQueueAddToRegistry( xTimerQueue, "TmrQ" );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			#endif /* configQUEUE_REGISTRY_SIZE */
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
+{
+BaseType_t xReturn;
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+
+	/* Is the timer in the list of active timers? */
+	taskENTER_CRITICAL();
+	{
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 )
+		{
+			xReturn = pdFALSE;
+		}
+		else
+		{
+			xReturn = pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+} /*lint !e818 Can't be pointer to const due to the typedef. */
+/*-----------------------------------------------------------*/
+
+void *pvTimerGetTimerID( const TimerHandle_t xTimer )
+{
+Timer_t * const pxTimer = xTimer;
+void *pvReturn;
+
+	configASSERT( xTimer );
+
+	taskENTER_CRITICAL();
+	{
+		pvReturn = pxTimer->pvTimerID;
+	}
+	taskEXIT_CRITICAL();
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )
+{
+Timer_t * const pxTimer = xTimer;
+
+	configASSERT( xTimer );
+
+	taskENTER_CRITICAL();
+	{
+		pxTimer->pvTimerID = pvNewID;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+	BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	DaemonTaskMessage_t xMessage;
+	BaseType_t xReturn;
+
+		/* Complete the message with the function parameters and post it to the
+		daemon task. */
+		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;
+		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+		xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+
+		tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+	BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )
+	{
+	DaemonTaskMessage_t xMessage;
+	BaseType_t xReturn;
+
+		/* This function can only be called after a timer has been created or
+		after the scheduler has been started because, until then, the timer
+		queue does not exist. */
+		configASSERT( xTimerQueue );
+
+		/* Complete the message with the function parameters and post it to the
+		daemon task. */
+		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;
+		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+		xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+
+		tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer )
+	{
+		return ( ( Timer_t * ) xTimer )->uxTimerNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber )
+	{
+		( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality.  If you want to include software timer
+functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#endif /* configUSE_TIMERS == 1 */
+
+
+
diff --git a/FreeRTOSv10.2.1/FreeRTOS/links_to_doc_pages_for_the_demo_projects.url b/FreeRTOSv10.2.1/FreeRTOS/links_to_doc_pages_for_the_demo_projects.url
new file mode 100644
index 0000000..1ae5cac
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/links_to_doc_pages_for_the_demo_projects.url
@@ -0,0 +1,5 @@
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,2
+[InternetShortcut]
+URL=http://www.freertos.org/a00090.html
+IDList=
diff --git a/FreeRTOSv10.2.1/FreeRTOS/readme.txt b/FreeRTOSv10.2.1/FreeRTOS/readme.txt
new file mode 100644
index 0000000..13ddc51
--- /dev/null
+++ b/FreeRTOSv10.2.1/FreeRTOS/readme.txt
@@ -0,0 +1,21 @@
+Directories:
+
++ The FreeRTOS/Source directory contains the FreeRTOS source code, and contains
+  its own readme file.
+
++ The FreeRTOS/Demo directory contains a demo application for every official
+FreeRTOS port, and contains its own readme file.
+
++ See http://www.freertos.org/a00017.html for full details of the directory 
+  structure and information on locating the files you require.
+
+The easiest way to use FreeRTOS is to start with one of the pre-configured demo 
+application projects (found in the FreeRTOS/Demo directory).  That way you will
+have the correct FreeRTOS source files included, and the correct include paths
+configured.  Once a demo application is building and executing you can remove
+the demo application file, and start to add in your own application source
+files.
+
+See also -
+http://www.freertos.org/FreeRTOS-quick-start-guide.html
+http://www.freertos.org/FAQHelp.html
diff --git a/FreeRTOSv10.2.1/readme.txt b/FreeRTOSv10.2.1/readme.txt
new file mode 100644
index 0000000..b35e4fc
--- /dev/null
+++ b/FreeRTOSv10.2.1/readme.txt
@@ -0,0 +1,32 @@
+Directories:
+
++ FreeRTOS/source contains the FreeRTOS real time kernel source code.
+
++ FreeRTOS/demo contains a pre-configured demo project for every official 
+  FreeRTOS port.
+  
++ See http://www.freertos.org/a00017.html for full details of the FreeRTOS
+  directory structure and information on locating the files you require.
+
+  + FreeRTOS-Plus contains additional FreeRTOS components and third party 
+  complementary products.  THESE ARE LICENSED SEPARATELY FROM FreeRTOS although
+  all contain open source options.  See the license files in each respective
+  directory for information.
+  
++ FreeRTOS-Plus/Demo contains pre-configured demo projects for the FreeRTOS-Plus 
+  components.  Most demo projects run in a Windows environment using the 
+  FreeRTOS windows simulator.  These are documented on the FreeRTOS web site 
+  http://www.FreeRTOS.org/plus
+
+Further readme files are contains in sub-directories as appropriate.
+  
+The easiest way to use FreeRTOS is to start with one of the pre-configured demo 
+application projects (found in the FreeRTOS/Demo directory).  That way you will
+have the correct FreeRTOS source files included, and the correct include paths
+configured.  Once a demo application is building and executing you can remove
+the demo application file, and start to add in your own application source
+files.
+
+See also -
+http://www.freertos.org/FreeRTOS-quick-start-guide.html
+http://www.freertos.org/FAQHelp.html
diff --git a/RISC-V-HiFive1_e-FreedomStudio/.cproject b/RISC-V-HiFive1_e-FreedomStudio/.cproject
new file mode 100644
index 0000000..c1f940c
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/.cproject
@@ -0,0 +1,68 @@
+
+
+	
+		
+			
+				
+				
+					
+					
+					
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+	
+		
+			
+		
+	
+	
+	
+		
+		
+			
+		
+		
+			
+		
+	
+	
+
diff --git a/RISC-V-HiFive1_e-FreedomStudio/.project b/RISC-V-HiFive1_e-FreedomStudio/.project
new file mode 100644
index 0000000..31a0fac
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/.project
@@ -0,0 +1,34 @@
+
+
+	FreeRTOS-HiFive1
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		org.eclipse.cdt.core.cnature
+		org.eclipse.cdt.core.ccnature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			Source
+			2
+			/home/eyck/git/FreeRTOS-RISCV/FreeRTOSv10.2.1/FreeRTOS/Source
+		
+	
+
diff --git a/RISC-V-HiFive1_e-FreedomStudio/.settings/language.settings.xml b/RISC-V-HiFive1_e-FreedomStudio/.settings/language.settings.xml
new file mode 100644
index 0000000..0eee743
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/.settings/language.settings.xml
@@ -0,0 +1,15 @@
+
+
+	
+		
+			
+			
+			
+			
+				
+				
+			
+			
+		
+	
+
diff --git a/RISC-V-HiFive1_e-FreedomStudio/BuildEnvironment.mk b/RISC-V-HiFive1_e-FreedomStudio/BuildEnvironment.mk
new file mode 100644
index 0000000..1d01ee3
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/BuildEnvironment.mk
@@ -0,0 +1,53 @@
+#
+# File: BuildEnvironment.mk
+# Copyright (c) 2019, Dornerworks Ltd.
+#
+
+BUILD_DIR = ./build
+CROSS_COMPILE_PREFIX = riscv64-unknown-elf
+
+SDK_DIR = ./freedom-e-sdk
+
+LINKER_SCRIPT = $(SDK_DIR)/env/freedom-e300-hifive1/flash.lds
+#-----------------------------------------------------------
+GCC     = $(CROSS_COMPILE_PREFIX)-gcc
+OBJCOPY = $(CROSS_COMPILE_PREFIX)-objcopy
+OBJDUMP = $(CROSS_COMPILE_PREFIX)-objdump
+AR      = $(CROSS_COMPILE_PREFIX)-ar
+RANLIB  = $(CROSS_COMPILE_PREFIX)-ranlib
+GDB     = $(CROSS_COMPILE_PREFIX)-gdb
+
+# if using the multi-arch (riscv64-unknown-elf-gcc):
+ARCH_FLAGS = -march=rv32imac -mabi=ilp32 -mcmodel=medany
+# Basic CFLAGS:
+CFLAGS  = -Wall -Wextra -O0 -g3 -msmall-data-limit=8 -std=gnu11
+CFLAGS += -ffunction-sections -fdata-sections -fno-builtin-printf
+CFLAGS += -include sys/cdefs.h
+CFLAGS += $(ARCH_FLAGS)
+# These flags are for outputing *.d dependency files for make
+CFLAGS += -MT"$@" -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)"
+
+ASMFLAGS =  -O0 -g3
+ASMFLAGS += $(ARCH_FLAGS)
+ASMFLAGS += -DportasmHANDLE_INTERRUPT=handle_trap -DportasmHAS_CLINT=1
+ASMFLAGS += -msmall-data-limit=8
+ASMFLAGS += -ffunction-sections -fdata-sections
+ASMFLAGS += -x assembler-with-cpp
+ASMFLAGS += -MT"$@" -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)"
+
+# Linker arguments __________________________________________
+LDFLAGS :=  -Xlinker --gc-sections -Xlinker --defsym=__stack_size=1K
+LDFLAGS += -O0 -g3
+LDFLAGS += -ffunction-sections -fdata-sections --specs=nano.specs
+LDFLAGS += -nostartfiles
+LDFLAGS += $(ARCH_FLAGS)
+LDFLAGS += -T $(LINKER_SCRIPT)
+LDFLAGS += -L../
+LDFLAGS += -Wl,--start-group -Wl,--end-group
+LDFLAGS += -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=open -Wl,--wrap=lseek -Wl,--wrap=read -Wl,--wrap=write
+LDFLAGS += -Wl,--wrap=fstat -Wl,--wrap=stat -Wl,--wrap=close -Wl,--wrap=link -Wl,--wrap=unlink -Wl,--wrap=execve
+LDFLAGS += -Wl,--wrap=fork -Wl,--wrap=getpid -Wl,--wrap=kill -Wl,--wrap=wait -Wl,--wrap=isatty -Wl,--wrap=times
+LDFLAGS += -Wl,--wrap=sbrk -Wl,--wrap=_exit -Wl,--wrap=puts -Wl,--wrap=_malloc -Wl,--wrap=_free -Wl,--wrap=_open
+LDFLAGS += -Wl,--wrap=_lseek -Wl,--wrap=_read -Wl,--wrap=_write -Wl,--wrap=_fstat -Wl,--wrap=_stat -Wl,--wrap=_close
+LDFLAGS += -Wl,--wrap=_link -Wl,--wrap=_unlink -Wl,--wrap=_execve -Wl,--wrap=_fork -Wl,--wrap=_getpid -Wl,--wrap=_kill
+LDFLAGS += -Wl,--wrap=_wait -Wl,--wrap=_isatty -Wl,--wrap=_times -Wl,--wrap=_sbrk -Wl,--wrap=__exit -Wl,--wrap=_puts
diff --git a/RISC-V-HiFive1_e-FreedomStudio/FreeRTOS.mk b/RISC-V-HiFive1_e-FreedomStudio/FreeRTOS.mk
new file mode 100644
index 0000000..9c23b51
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/FreeRTOS.mk
@@ -0,0 +1,32 @@
+#
+# File: FreeRTOS.mk
+# Copyright (c) 2019, Dornerworks Ltd.
+#
+
+-include BuildEnvironment.mk
+
+FREERTOS_DIR = ../FreeRTOSv10.2.1/FreeRTOS
+FREERTOS_SOURCE_DIR = $(FREERTOS_DIR)/Source
+
+FREERTOS_SRC = \
+	$(FREERTOS_SOURCE_DIR)/croutine.c \
+	$(FREERTOS_SOURCE_DIR)/list.c \
+	$(FREERTOS_SOURCE_DIR)/queue.c \
+	$(FREERTOS_SOURCE_DIR)/tasks.c \
+	$(FREERTOS_SOURCE_DIR)/timers.c \
+	$(FREERTOS_SOURCE_DIR)/event_groups.c \
+	$(FREERTOS_SOURCE_DIR)/stream_buffer.c \
+	$(FREERTOS_SOURCE_DIR)/portable/MemMang/heap_4.c
+
+FREERTOS_INC = $(FREERTOS_SOURCE_DIR)/include
+
+FREERTOS_INCLUDES := \
+	-I $(FREERTOS_INC)
+
+INTERRUPT_HANDLER = main_blinky
+
+FREERTOS_BUILD_DIR = $(BUILD_DIR)/FreeRTOS
+FREERTOS_OBJS = $(patsubst %.c,$(FREERTOS_BUILD_DIR)/%.o,$(notdir $(FREERTOS_SRC)))
+VPATH += \
+	$(FREERTOS_SOURCE_DIR) \
+	$(FREERTOS_SOURCE_DIR)/portable/MemMang
diff --git a/RISC-V-HiFive1_e-FreedomStudio/FreeRTOSConfig.h b/RISC-V-HiFive1_e-FreedomStudio/FreeRTOSConfig.h
new file mode 100644
index 0000000..b301e13
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+    FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include "platform.h"
+
+/*
+ * For some reason the standard demo timer demo/test tasks fail when executing
+ * in QEMU, although they pass on other RISC-V platforms.  This requires
+ * further investigation, but for now, defining _WINDOWS_ has the effect of
+ * using the wider timer test thresholds that are normally only used when the
+ * tests are used with the FreeRTOS Windows port (which is not deterministic
+ * and therefore requires wider margins).
+ */
+#define _WINDOWS_
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configCLINT_BASE_ADDRESS		CLINT_CTRL_ADDR
+#define configUSE_PREEMPTION			1
+#define configUSE_IDLE_HOOK				0
+#define configUSE_TICK_HOOK				1
+#define configCPU_CLOCK_HZ				( 32768 ) /*lfclk RTC clock with 32768Hz, SystemClock is 224618086*/
+#define configTICK_RATE_HZ				( ( TickType_t ) 1000 )
+#define configMAX_PRIORITIES			( 7 )
+#define configMINIMAL_STACK_SIZE		( ( unsigned short ) 70 )
+#define configTOTAL_HEAP_SIZE			( ( size_t ) 14100 )
+#define configMAX_TASK_NAME_LEN			( 16 )
+#define configUSE_TRACE_FACILITY		0
+#define configUSE_16_BIT_TICKS			0
+#define configIDLE_SHOULD_YIELD			1
+#define configUSE_MUTEXES				1
+#define configQUEUE_REGISTRY_SIZE		8
+#define configCHECK_FOR_STACK_OVERFLOW	2
+#define configUSE_RECURSIVE_MUTEXES		1
+#define configUSE_MALLOC_FAILED_HOOK	1
+#define configUSE_APPLICATION_TASK_TAG	0
+#define configUSE_COUNTING_SEMAPHORES	1
+#define configGENERATE_RUN_TIME_STATS	0
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 			0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Software timer definitions. */
+#define configUSE_TIMERS				1
+#define configTIMER_TASK_PRIORITY		( configMAX_PRIORITIES - 1 )
+#define configTIMER_QUEUE_LENGTH		4
+#define configTIMER_TASK_STACK_DEPTH	( 100 )
+
+/* Task priorities.  Allow these to be overridden. */
+#ifndef uartPRIMARY_PRIORITY
+	#define uartPRIMARY_PRIORITY		( configMAX_PRIORITIES - 3 )
+#endif
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet		1
+#define INCLUDE_uxTaskPriorityGet		1
+#define INCLUDE_vTaskDelete				1
+#define INCLUDE_vTaskCleanUpResources	1
+#define INCLUDE_vTaskSuspend			1
+#define INCLUDE_vTaskDelayUntil			1
+#define INCLUDE_vTaskDelay				1
+#define INCLUDE_eTaskGetState			1
+#define INCLUDE_xTimerPendFunctionCall	1
+
+/* Normal assert() semantics without relying on the provision of an assert.h
+header file. */
+void vAssertCalled( void );
+#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled()
+
+/* Overwrite some of the stack sizes allocated to various test and demo tasks.
+Like all task stack sizes, the value is the number of words, not bytes. */
+#define bktBLOCK_TIME_TASK_STACK_SIZE 100
+#define notifyNOTIFIED_TASK_STACK_SIZE 120
+#define priSUSPENDED_RX_TASK_STACK_SIZE 90
+#define tmrTIMER_TEST_TASK_STACK_SIZE 100
+#define ebRENDESVOUS_TEST_TASK_STACK_SIZE 100
+#define ebEVENT_GROUP_SET_BITS_TEST_TASK_STACK_SIZE 115
+#define genqMUTEX_TEST_TASK_STACK_SIZE 90
+#define genqGENERIC_QUEUE_TEST_TASK_STACK_SIZE 100
+#define recmuRECURSIVE_MUTEX_TEST_TASK_STACK_SIZE 90
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/RISC-V-HiFive1_e-FreedomStudio/Makefile b/RISC-V-HiFive1_e-FreedomStudio/Makefile
new file mode 100644
index 0000000..c43a21c
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/Makefile
@@ -0,0 +1,194 @@
+#
+# File: Makefile
+# Copyright (c) 2019, Dornerworks Ltd.
+#
+
+PROJ_NAME ?= simple
+
+include BuildEnvironment.mk
+include FreeRTOS.mk
+-include $(wildcard $(OUTDIR)/*.d)
+# Platform spcific settings for this application _____________________________________________
+
+ARCH = RISC-V
+ARCH_PORTABLE_INC = $(FREERTOS_SOURCE_DIR)/portable/GCC/$(ARCH)/
+ARCH_PORTABLE_SRC = $(FREERTOS_SOURCE_DIR)/portable/GCC/$(ARCH)/port.c
+ARCH_PORTABLE_ASM = $(FREERTOS_SOURCE_DIR)/portable/GCC/$(ARCH)/portASM.S
+
+SDK_SRC := \
+	$(SDK_DIR)/libwrap/sys/_exit.c \
+	$(SDK_DIR)/libwrap/sys/close.c \
+	$(SDK_DIR)/libwrap/sys/execve.c \
+	$(SDK_DIR)/libwrap/sys/fork.c \
+	$(SDK_DIR)/libwrap/sys/fstat.c \
+	$(SDK_DIR)/libwrap/sys/getpid.c \
+	$(SDK_DIR)/libwrap/sys/isatty.c \
+	$(SDK_DIR)/libwrap/sys/kill.c \
+	$(SDK_DIR)/libwrap/sys/link.c \
+	$(SDK_DIR)/libwrap/sys/lseek.c \
+	$(SDK_DIR)/libwrap/sys/openat.c \
+	$(SDK_DIR)/libwrap/sys/puts.c \
+	$(SDK_DIR)/libwrap/sys/read.c \
+	$(SDK_DIR)/libwrap/sys/sbrk.c \
+	$(SDK_DIR)/libwrap/sys/stat.c \
+	$(SDK_DIR)/libwrap/sys/times.c \
+	$(SDK_DIR)/libwrap/sys/unlink.c \
+	$(SDK_DIR)/libwrap/sys/wait.c \
+	$(SDK_DIR)/libwrap/sys/write.c \
+	$(SDK_DIR)/libwrap/stdlib/malloc.c \
+	$(SDK_DIR)/libwrap/misc/write_hex.c \
+	$(SDK_DIR)/env/freedom-e300-hifive1/init.c \
+	$(SDK_DIR)/drivers/plic/plic_driver.c \
+	$(SDK_DIR)/drivers/fe300prci/fe300prci_driver.c
+
+SDK_ASM := \
+	$(SDK_DIR)/env/entry.S \
+	$(SDK_DIR)/env/start.S
+SDK_OBJS := $(patsubst %.c,$(FREERTOS_BUILD_DIR)/%.o,$(notdir $(SDK_SRC)))
+SDK_OBJS += $(patsubst %.S,$(FREERTOS_BUILD_DIR)/%.o,$(notdir $(SDK_ASM)))
+VPATH += \
+	$(SDK_DIR)/env \
+	$(SDK_DIR)/env/freedom-e300-hifive1 \
+	$(SDK_DIR)/libwrap/sys \
+	$(SDK_DIR)/libwrap/misc \
+	$(SDK_DIR)/libwrap/stdlib \
+	$(SDK_DIR)/drivers/plic \
+	$(SDK_DIR)/drivers/fe300prci
+
+PORT_OBJS := $(patsubst %.c,$(FREERTOS_BUILD_DIR)/%.o,$(notdir $(ARCH_PORTABLE_SRC)))
+PORT_OBJS += $(patsubst %.S,$(FREERTOS_BUILD_DIR)/%.o,$(notdir $(ARCH_PORTABLE_ASM)))
+FREERTOS_OBJS += $(PORT_OBJS) $(SDK_OBJS)
+VPATH += $(FREERTOS_SOURCE_DIR)/portable/GCC/$(ARCH)
+
+
+CFLAGS += -DportasmHANDLE_INTERRUPT=$(INTERRUPT_HANDLER)
+
+# Set up application source, include, and object files for compilation: ______________________
+APP_SRC_DIR = .
+APP_SRC = \
+	$(APP_SRC_DIR)/main.c \
+	$(APP_SRC_DIR)/blinky_demo/main_blinky.c \
+	$(APP_SRC_DIR)/full_demo/main_full.c
+
+APP_ASM = \
+	$(APP_SRC_DIR)/full_demo/RegTest.S
+
+APP_INCLUDES = \
+	-I ./ \
+	-I $(SDK_DIR)/include \
+	-I $(SDK_DIR)/env/freedom-e300-hifive1 \
+	-I $(SDK_DIR)/env \
+	-I $(FREERTOS_INC) \
+	-I $(ARCH_PORTABLE_INC) \
+	-I $(FREERTOS_DIR)/Demo/Common/include
+
+APP_BUILD_DIR = $(BUILD_DIR)/app
+APP_OBJS := $(patsubst %.c,$(APP_BUILD_DIR)/%.o,$(notdir $(APP_SRC)))
+APP_OBJS += $(patsubst %.S,$(APP_BUILD_DIR)/%.o,$(notdir $(APP_ASM)))
+VPATH += \
+	$(APP_SRC_DIR)/blinky_demo \
+	$(APP_SRC_DIR)/full_demo \
+	$(APP_SRC_DIR)
+
+DEMO_COMMON_SRC =  \
+	$(FREERTOS_DIR)/Demo/Common/Minimal/EventGroupsDemo.c \
+	$(FREERTOS_DIR)/Demo/Common/Minimal/TimerDemo.c \
+	$(FREERTOS_DIR)/Demo/Common/Minimal/TaskNotify.c \
+	$(FREERTOS_DIR)/Demo/Common/Minimal/GenQTest.c \
+	$(FREERTOS_DIR)/Demo/Common/Minimal/blocktim.c \
+	$(FREERTOS_DIR)/Demo/Common/Minimal/dynamic.c \
+	$(FREERTOS_DIR)/Demo/Common/Minimal/recmutex.c
+
+DEMO_COMMON_OBJS := $(patsubst %.c,$(APP_BUILD_DIR)/%.o,$(notdir $(DEMO_COMMON_SRC)))
+VPATH += $(FREERTOS_DIR)/Demo/Common/Minimal
+
+OUT_ELF = $(BUILD_DIR)/FreeRTOS-$(PROJ_NAME).elf
+
+# Need to tell FreeRTOS where to find the FreeRTOSConfig.h __________________________________
+FREERTOS_INCLUDES += \
+	-I ./ \
+	-I $(ARCH_PORTABLE_INC) \
+	-I $(SDK_DIR)/include \
+	-I $(SDK_DIR)/env/freedom-e300-hifive1 \
+	-I $(SDK_DIR)/env \
+	-I $(SDK_DIR)/drivers \
+	-I $(FREERTOS_DIR)/Demo/Common/include \
+	-I $(FREERTOS_SOURCE_DIR)/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions
+
+# List of object files to compile for the system:
+OUT_OBJS = \
+	$(APP_OBJS) \
+	$(DEMO_COMMON_OBJS) \
+	$(FREERTOS_OBJS)
+
+BUILD_DIRECTORIES = \
+	$(APP_BUILD_DIR) \
+	$(FREERTOS_BUILD_DIR)
+
+LDFLAGS += -Wl,-Map,"$(BUILD_DIR)/$(PROJ_NAME).map"
+
+.PHONY: debug clean app_compile debug-app frtos_compile print-info out_elf sim-qemu gdb
+all: directories $(OUT_OBJS) $(OUT_ELF)
+directories: $(BUILD_DIRECTORIES)
+app_compile: directories $(APP_OBJS)
+frtos_compile: directories $(FREERTOS_OBJS)
+out_elf: directories $(OUT_ELF)
+
+# Notes
+# Each "Module" needs
+#  - Lists of source files
+#  - Source Directory(ies)
+#  - Include Directory List (with -I prepending each entry)
+#  - Build Directory
+#  - Object list
+#    - OBJS = $(patsubst %.c,$(MODULE_BUILD_DIR)/%.o,$(notdir $(MODULE_SRC)))
+#  - Add source direcories to VPATH
+# In the master make file
+#  - Module build directory must be created
+#  - Object Rules can be done with
+#    - $(MODULE_BUILD_DIR)/%.o : %.c
+
+# Compile Object Files ____________________________________________________________________
+$(APP_BUILD_DIR)/%.o : %.c
+	@echo "[APP Objects] : $@ ______________________________________________________________"
+	@echo "Building: $<"
+	$(GCC) $(CFLAGS) $(APP_INCLUDES) -o $@ -c $<
+	@echo "Finished Building: $<"
+
+$(APP_BUILD_DIR)/%.o : %.S
+	@echo "[APP Objects] : $@ ______________________________________________________________"
+	@echo "Building: $<"
+	$(GCC) $(ASMFLAGS) $(APP_INCLUDES) $(FREERTOS_INCLUDES) -o $@ -c $<
+	@echo "Finished Building: $<"
+
+$(FREERTOS_BUILD_DIR)/%.o : %.c
+	@echo "[FreeRTOS Objects] : $@ __________________________________________________________"
+	@echo "Building: $<"
+	$(GCC) $(CFLAGS) $(FREERTOS_INCLUDES) -o $@ -c $<
+	@echo "Finished Building: $<"
+
+$(FREERTOS_BUILD_DIR)/%.o : %.S
+	@echo "[FreeRTOS Objects] : $@ __________________________________________________________"
+	@echo "Building: $<"
+	$(GCC) $(ASMFLAGS) $(FREERTOS_INCLUDES) -o $@ -c $<
+	@echo "Finished Building: $<"
+
+# Generate ELF ___________________________________________________________________________
+$(OUT_ELF): $(OUT_OBJS)
+	@echo '___________________________________________________________________________________'
+	@echo 'Building target: $@'
+	@echo '_______________________________'
+	$(GCC) $(LDFLAGS) $(LDOPTS) -o $@ $(OUT_OBJS) $(LIB_FLAGS)
+	@echo 'Finished building target: $@'
+	@echo ' '
+
+.PHONY:  build_lib
+
+$(BUILD_DIRECTORIES):
+	mkdir -p $@
+
+clean:
+	rm -rv $(BUILD_DIR)
+
+gdb: $(OUT_ELF)
+	$(GDB) -iex "set mem inaccessible-by-default off" -iex "set arch riscv:rv32" -iex "set riscv use_compressed_breakpoint off"
diff --git a/RISC-V-HiFive1_e-FreedomStudio/blinky_demo/main_blinky.c b/RISC-V-HiFive1_e-FreedomStudio/blinky_demo/main_blinky.c
new file mode 100644
index 0000000..364d1d8
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/blinky_demo/main_blinky.c
@@ -0,0 +1,207 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/******************************************************************************
+ * NOTE 1:  This project provides two demo applications.  A simple blinky
+ * style project, and a more comprehensive test and demo application.  The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
+ * between the two.  See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
+ * in main.c.  This file implements the simply blinky style version.
+ *
+ * NOTE 2:  This file only contains the source code that is specific to the
+ * basic demo.  Generic functions, such FreeRTOS hook functions, and functions
+ * required to configure the hardware are defined in main.c.
+ ******************************************************************************
+ *
+ * main_blinky() creates one queue, and two tasks.  It then starts the
+ * scheduler.
+ *
+ * The Queue Send Task:
+ * The queue send task is implemented by the prvQueueSendTask() function in
+ * this file.  prvQueueSendTask() sits in a loop that causes it to repeatedly
+ * block for 1000 milliseconds, before sending the value 100 to the queue that
+ * was created within main_blinky().  Once the value is sent, the task loops
+ * back around to block for another 1000 milliseconds...and so on.
+ *
+ * The Queue Receive Task:
+ * The queue receive task is implemented by the prvQueueReceiveTask() function
+ * in this file.  prvQueueReceiveTask() sits in a loop where it repeatedly
+ * blocks on attempts to read data from the queue that was created within
+ * main_blinky().  When data is received, the task checks the value of the
+ * data, and if the value equals the expected 100, writes 'Blink' to the UART
+ * (the UART is used in place of the LED to allow easy execution in QEMU).  The
+ * 'block time' parameter passed to the queue receive function specifies that
+ * the task should be held in the Blocked state indefinitely to wait for data to
+ * be available on the queue.  The queue receive task will only leave the
+ * Blocked state when the queue send task writes to the queue.  As the queue
+ * send task writes to the queue every 1000 milliseconds, the queue receive
+ * task leaves the Blocked state every 1000 milliseconds, and therefore toggles
+ * the LED every 200 milliseconds.
+ */
+
+/* Standard includes. */
+#include 
+#include 
+#include 
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+extern void PRCI_use_hfxosc(uint32_t);
+
+/* Priorities used by the tasks. */
+#define mainQUEUE_RECEIVE_TASK_PRIORITY		( tskIDLE_PRIORITY + 2 )
+#define	mainQUEUE_SEND_TASK_PRIORITY		( tskIDLE_PRIORITY + 1 )
+
+/* The rate at which data is sent to the queue.  The 200ms value is converted
+to ticks using the pdMS_TO_TICKS() macro. */
+#define mainQUEUE_SEND_FREQUENCY_MS			pdMS_TO_TICKS( 32 )
+
+/* The maximum number items the queue can hold.  The priority of the receiving
+task is above the priority of the sending task, so the receiving task will
+preempt the sending task and remove the queue items each time the sending task
+writes to the queue.  Therefore the queue will never have more than one item in
+it at any time, and even with a queue length of 1, the sending task will never
+find the queue full. */
+#define mainQUEUE_LENGTH					( 1 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in
+ * main.c.
+ */
+void main_blinky( void );
+
+/*
+ * The tasks as described in the comments at the top of this file.
+ */
+static void prvQueueReceiveTask( void *pvParameters );
+static void prvQueueSendTask( void *pvParameters );
+
+/*-----------------------------------------------------------*/
+
+/* The queue used by both tasks. */
+static QueueHandle_t xQueue = NULL;
+
+/*-----------------------------------------------------------*/
+
+void main_blinky( void )
+{
+    PRCI_use_hfxosc(1);
+
+    /* Create the queue. */
+	xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );
+
+	if( xQueue != NULL )
+	{
+		/* Start the two tasks as described in the comments at the top of this
+		file. */
+		xTaskCreate( prvQueueReceiveTask,				/* The function that implements the task. */
+					"Rx", 								/* The text name assigned to the task - for debug only as it is not used by the kernel. */
+					configMINIMAL_STACK_SIZE * 2U, 			/* The size of the stack to allocate to the task. */
+					NULL, 								/* The parameter passed to the task - not used in this case. */
+					mainQUEUE_RECEIVE_TASK_PRIORITY, 	/* The priority assigned to the task. */
+					NULL );								/* The task handle is not required, so NULL is passed. */
+
+		xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE * 2U, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
+
+		/* Start the tasks and timer running. */
+		vTaskStartScheduler();
+	}
+
+	/* If all is well, the scheduler will now be running, and the following
+	line will never be reached.  If the following line does execute, then
+	there was insufficient FreeRTOS heap memory available for the Idle and/or
+	timer tasks to be created.  See the memory management section on the
+	FreeRTOS web site for more details on the FreeRTOS heap
+	http://www.freertos.org/a00111.html. */
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueSendTask( void *pvParameters )
+{
+TickType_t xNextWakeTime;
+const unsigned long ulValueToSend = 100UL;
+BaseType_t xReturned;
+
+	/* Remove compiler warning about unused parameter. */
+	( void ) pvParameters;
+
+	/* Initialise xNextWakeTime - this only needs to be done once. */
+	xNextWakeTime = xTaskGetTickCount();
+
+	for( ;; )
+	{
+		/* Place this task in the blocked state until it is time to run again. */
+		vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
+
+		/* Send to the queue - causing the queue receive task to unblock and
+		toggle the LED.  0 is used as the block time so the sending operation
+		will not block - it shouldn't need to block as the queue should always
+		be empty at this point in the code. */
+		xReturned = xQueueSend( xQueue, &ulValueToSend, 0U );
+		configASSERT( xReturned == pdPASS );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueReceiveTask( void *pvParameters )
+{
+unsigned long ulReceivedValue;
+const unsigned long ulExpectedValue = 100UL;
+const char * const pcPassMessage = "Blink\r\n";
+const char * const pcFailMessage = "Unexpected value received\r\n";
+
+	/* Remove compiler warning about unused parameter. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		/* Wait until something arrives in the queue - this task will block
+		indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
+		FreeRTOSConfig.h. */
+		xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
+
+		/*  To get here something must have been received from the queue, but
+		is it the expected value?  If it is, toggle the LED. */
+		if( ulReceivedValue == ulExpectedValue )
+		{
+			write( STDOUT_FILENO, pcPassMessage, strlen( pcPassMessage ) );
+			ulReceivedValue = 0U;
+		}
+		else
+		{
+			write( STDOUT_FILENO, pcFailMessage, strlen( pcFailMessage ) );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/LICENSE(Freedom-e-SDK) b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/LICENSE(Freedom-e-SDK)
new file mode 100644
index 0000000..0b0b6c8
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/LICENSE(Freedom-e-SDK)
@@ -0,0 +1,206 @@
+
+This software, except as otherwise noted in subrepositories, 
+is licensed under the Apache 2 license, quoted below.
+
+
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
+
+      "License" shall mean the terms and conditions for use, reproduction,
+      and distribution as defined by Sections 1 through 9 of this document.
+
+      "Licensor" shall mean the copyright owner or entity authorized by
+      the copyright owner that is granting the License.
+
+      "Legal Entity" shall mean the union of the acting entity and all
+      other entities that control, are controlled by, or are under common
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+      direction or management of such entity, whether by contract or
+      otherwise, or (ii) ownership of fifty percent (50%) or more of the
+      outstanding shares, or (iii) beneficial ownership of such entity.
+
+      "You" (or "Your") shall mean an individual or Legal Entity
+      exercising permissions granted by this License.
+
+      "Source" form shall mean the preferred form for making modifications,
+      including but not limited to software source code, documentation
+      source, and configuration files.
+
+      "Object" form shall mean any form resulting from mechanical
+      transformation or translation of a Source form, including but
+      not limited to compiled object code, generated documentation,
+      and conversions to other media types.
+
+      "Work" shall mean the work of authorship, whether in Source or
+      Object form, made available under the License, as indicated by a
+      copyright notice that is included in or attached to the work
+      (an example is provided in the Appendix below).
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+      "Derivative Works" shall mean any work, whether in Source or Object
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+      of this License, Derivative Works shall not include works that remain
+      separable from, or merely link (or bind by name) to the interfaces of,
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+      "Contribution" shall mean any work of authorship, including
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+      "Contributor" shall mean Licensor and any individual or Legal Entity
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+
+   7. Disclaimer of Warranty. Unless required by applicable law or
+      agreed to in writing, Licensor provides the Work (and each
+      Contributor provides its Contributions) on an "AS IS" BASIS,
+      WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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+      PARTICULAR PURPOSE. You are solely responsible for determining the
+      appropriateness of using or redistributing the Work and assume any
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+
+   8. Limitation of Liability. In no event and under no legal theory,
+      whether in tort (including negligence), contract, or otherwise,
+      unless required by applicable law (such as deliberate and grossly
+      negligent acts) or agreed to in writing, shall any Contributor be
+      liable to You for damages, including any direct, indirect, special,
+      incidental, or consequential damages of any character arising as a
+      result of this License or out of the use or inability to use the
+      Work (including but not limited to damages for loss of goodwill,
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+      other commercial damages or losses), even if such Contributor
+      has been advised of the possibility of such damages.
+
+   9. Accepting Warranty or Additional Liability. While redistributing
+      the Work or Derivative Works thereof, You may choose to offer,
+      and charge a fee for, acceptance of support, warranty, indemnity,
+      or other liability obligations and/or rights consistent with this
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+      defend, and hold each Contributor harmless for any liability
+      incurred by, or claims asserted against, such Contributor by reason
+      of your accepting any such warranty or additional liability.
+
+   END OF TERMS AND CONDITIONS
+
+   APPENDIX: How to apply the Apache License to your work.
+
+      To apply the Apache License to your work, attach the following
+      boilerplate notice, with the fields enclosed by brackets "[]"
+      replaced with your own identifying information. (Don't include
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+      file or class name and description of purpose be included on the
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+
+   Copyright 2016 SiFive, Inc.
+
+   Licensed under the Apache License, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   You may obtain a copy of the License at
+
+       http://www.apache.org/licenses/LICENSE-2.0
+
+   Unless required by applicable law or agreed to in writing, software
+   distributed under the License is distributed on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+   See the License for the specific language governing permissions and
+   limitations under the License.
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/drivers/fe300prci/fe300prci_driver.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/drivers/fe300prci/fe300prci_driver.c
new file mode 100644
index 0000000..214b1d5
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/drivers/fe300prci/fe300prci_driver.c
@@ -0,0 +1,252 @@
+// See LICENSE file for license details
+
+#include "platform.h"
+
+#ifdef PRCI_CTRL_ADDR
+#include "fe300prci/fe300prci_driver.h"
+#include 
+
+#define rdmcycle(x)  {				       \
+    uint32_t lo, hi, hi2;			       \
+    __asm__ __volatile__ ("1:\n\t"		       \
+			  "csrr %0, mcycleh\n\t"       \
+			  "csrr %1, mcycle\n\t"	       \
+			  "csrr %2, mcycleh\n\t"		\
+			  "bne  %0, %2, 1b\n\t"			\
+			  : "=r" (hi), "=r" (lo), "=r" (hi2)) ;	\
+    *(x) = lo | ((uint64_t) hi << 32); 				\
+  }
+
+uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq)
+{
+
+  uint32_t start_mtime = CLINT_REG(CLINT_MTIME);
+  uint32_t end_mtime = start_mtime + mtime_ticks + 1;
+
+  // Make sure we won't get rollover.
+  while (end_mtime < start_mtime){
+    start_mtime = CLINT_REG(CLINT_MTIME);
+    end_mtime = start_mtime + mtime_ticks + 1;
+  }
+
+  // Don't start measuring until mtime edge.
+  uint32_t tmp = start_mtime;
+  do {
+    start_mtime = CLINT_REG(CLINT_MTIME);
+  } while (start_mtime == tmp);
+  
+  uint64_t start_mcycle;
+  rdmcycle(&start_mcycle);
+  
+  while (CLINT_REG(CLINT_MTIME) < end_mtime) ;
+  
+  uint64_t end_mcycle;
+  rdmcycle(&end_mcycle);
+  uint32_t difference = (uint32_t) (end_mcycle - start_mcycle);
+
+  uint64_t freq = ((uint64_t) difference * mtime_freq) / mtime_ticks;
+  return (uint32_t) freq & 0xFFFFFFFF;
+  
+}
+ 
+
+void PRCI_use_hfrosc(int div, int trim)
+{
+  // Make sure the HFROSC is running at its default setting
+  // It is OK to change this even if we are running off of it.
+  
+  PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1));
+
+  while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0);
+  
+  PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1);
+}
+
+void PRCI_use_pll(int refsel, int bypass,
+			 int r, int f, int q, int finaldiv,
+			 int hfroscdiv, int hfrosctrim)
+{
+  // Ensure that we aren't running off the PLL before we mess with it.
+  if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {
+    // Make sure the HFROSC is running at its default setting
+    PRCI_use_hfrosc(4, 16);
+  }
+  
+  // Set PLL Source to be HFXOSC if desired.
+  uint32_t config_value = 0;
+
+  config_value |= PLL_REFSEL(refsel);
+  
+  if (bypass) {
+    // Bypass
+    config_value |= PLL_BYPASS(1);
+
+    PRCI_REG(PRCI_PLLCFG) = config_value;
+
+    // If we don't have an HFXTAL, this doesn't really matter.
+    // Set our Final output divide to divide-by-1:
+    PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
+  } else {
+  
+    // To overclock, use the hfrosc
+    if (hfrosctrim >= 0 && hfroscdiv >= 0) {
+      PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
+    }
+    
+    // Set DIV Settings for PLL
+    
+    // (Legal values of f_REF are 6-48MHz)
+
+    // Set DIVR to divide-by-2 to get 8MHz frequency
+    // (legal values of f_R are 6-12 MHz)
+
+    config_value |= PLL_BYPASS(1);
+    config_value |= PLL_R(r);
+
+    // Set DIVF to get 512Mhz frequncy
+    // There is an implied multiply-by-2, 16Mhz.
+    // So need to write 32-1
+    // (legal values of f_F are 384-768 MHz)
+    config_value |= PLL_F(f);
+
+    // Set DIVQ to divide-by-2 to get 256 MHz frequency
+    // (legal values of f_Q are 50-400Mhz)
+    config_value |= PLL_Q(q);
+
+    // Set our Final output divide to divide-by-1:
+    if (finaldiv == 1){
+      PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
+    } else {
+      PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV(finaldiv-1));
+    }
+
+    PRCI_REG(PRCI_PLLCFG) = config_value;
+
+    // Un-Bypass the PLL.
+    PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
+
+    // Wait for PLL Lock
+    // Note that the Lock signal can be glitchy.
+    // Need to wait 100 us
+    // RTC is running at 32kHz.
+    // So wait 4 ticks of RTC.
+    uint32_t now = CLINT_REG(CLINT_MTIME);
+    while (CLINT_REG(CLINT_MTIME) - now < 4) ;
+    
+    // Now it is safe to check for PLL Lock
+    while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0);
+
+  }
+
+  // Switch over to PLL Clock source
+  PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);
+
+  // If we're running off HFXOSC, turn off the HFROSC to
+  // save power.
+  if (refsel) {
+    PRCI_REG(PRCI_HFROSCCFG) &= ~ROSC_EN(1);
+  }
+  
+}
+
+void PRCI_use_default_clocks()
+{
+  // Turn off the LFROSC
+  AON_REG(AON_LFROSC) &= ~ROSC_EN(1);
+
+  // Use HFROSC
+  PRCI_use_hfrosc(4, 16);
+}
+
+void PRCI_use_hfxosc(uint32_t finaldiv)
+{
+  
+  PRCI_use_pll(1, // Use HFXTAL
+	       1, // Bypass = 1
+	       0, // PLL settings don't matter
+	       0, // PLL settings don't matter
+	       0, // PLL settings don't matter
+	       finaldiv,
+	       -1,
+	       -1);
+}
+
+// This is a generic function, which
+// doesn't span the entire range of HFROSC settings.
+// It only adjusts the trim, which can span a hundred MHz or so.
+// This function does not check the legality of the PLL settings
+// at all, and it is quite possible to configure invalid PLL settings
+// this way.
+// It returns the actual measured CPU frequency.
+
+uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target )
+{
+
+  uint32_t hfrosctrim = 0;
+  uint32_t hfroscdiv = 4;
+  uint32_t prev_trim = 0;
+
+  // In this function we use PLL settings which
+  // will give us a 32x multiplier from the output
+  // of the HFROSC source to the output of the
+  // PLL. We first measure our HFROSC to get the
+  // right trim, then finally use it as the PLL source.
+  // We should really check here that the f_cpu
+  // requested is something in the limit of the PLL. For
+  // now that is up to the user.
+
+  // This will undershoot for frequencies not divisible by 16.
+  uint32_t desired_hfrosc_freq = (f_cpu/ 16);
+
+  PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
+  
+  // Ignore the first run (for icache reasons)
+  uint32_t cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
+
+  cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
+  uint32_t prev_freq = cpu_freq;
+  
+  while ((cpu_freq < desired_hfrosc_freq) && (hfrosctrim < 0x1F)){
+    prev_trim = hfrosctrim;
+    prev_freq = cpu_freq;
+    hfrosctrim ++;
+    PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
+    cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
+  } 
+
+  // We couldn't go low enough
+  if (prev_freq > desired_hfrosc_freq){
+    PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
+    cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ);
+    return cpu_freq;
+  }
+  
+  // We couldn't go high enough
+  if (cpu_freq < desired_hfrosc_freq){
+    PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
+    cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ);
+    return cpu_freq;
+  }
+
+  // Check for over/undershoot
+  switch(target) {
+  case(PRCI_FREQ_CLOSEST):
+    if ((desired_hfrosc_freq - prev_freq) < (cpu_freq - desired_hfrosc_freq)) {
+      PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
+    } else {
+      PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim);
+    }
+    break;
+  case(PRCI_FREQ_UNDERSHOOT):
+    PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
+    break;
+  default:
+    PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim);
+  }
+
+  cpu_freq =  PRCI_measure_mcycle_freq(1000, RTC_FREQ);
+  return cpu_freq;
+
+}
+
+#endif
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/drivers/fe300prci/fe300prci_driver.h b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/drivers/fe300prci/fe300prci_driver.h
new file mode 100644
index 0000000..5ad9c0c
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/drivers/fe300prci/fe300prci_driver.h
@@ -0,0 +1,79 @@
+// See LICENSE file for license details
+
+#ifndef _FE300PRCI_DRIVER_H_
+#define _FE300PRCI_DRIVER_H_
+
+__BEGIN_DECLS
+
+#include 
+
+typedef enum prci_freq_target {
+  
+  PRCI_FREQ_OVERSHOOT,
+  PRCI_FREQ_CLOSEST,
+  PRCI_FREQ_UNDERSHOOT
+
+} PRCI_freq_target;
+
+/* Measure and return the approximate frequency of the 
+ * CPU, as given by measuring the mcycle counter against 
+ * the mtime ticks.
+ */
+uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq);
+
+/* Safely switch over to the HFROSC using the given div
+ * and trim settings.
+ */
+void PRCI_use_hfrosc(int div, int trim);
+
+/* Safely switch over to the 16MHz HFXOSC,
+ * applying the finaldiv clock divider (1 is the lowest
+ * legal value).
+ */
+void PRCI_use_hfxosc(uint32_t finaldiv);
+
+/* Safely switch over to the PLL using the given
+ * settings.
+ * 
+ * Note that not all combinations of the inputs are actually
+ * legal, and this function does not check for their
+ * legality ("safely" means that this function won't turn off
+ * or glitch the clock the CPU is actually running off, but
+ * doesn't protect against you making it too fast or slow.)
+ */
+
+void PRCI_use_pll(int refsel, int bypass,
+			 int r, int f, int q, int finaldiv,
+			 int hfroscdiv, int hfrosctrim);
+
+/* Use the default clocks configured at reset.
+ * This is ~16Mhz HFROSC and turns off the LFROSC
+ * (on the current FE310 Dev Platforms, an external LFROSC is 
+ * used as it is more power efficient).
+ */
+void PRCI_use_default_clocks();
+
+/* This routine will adjust the HFROSC trim
+ * while using HFROSC as the clock source, 
+ * measure the resulting frequency, then
+ * use it as the PLL clock source, 
+ * in an attempt to get over, under, or close to the 
+ * requested frequency. It returns the actual measured 
+ * frequency. 
+ *
+ * Note that the requested frequency must be within the 
+ * range supported by the PLL so not all values are 
+ * achievable with this function, and not all 
+ * are guaranteed to actually work. The PLL
+ * is rated higher than the hardware.
+ * 
+ * There is no check on the desired f_cpu frequency, it
+ * is up to the user to specify something reasonable.
+ */
+
+uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target);
+
+__END_DECLS
+
+#endif
+  
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/drivers/plic/plic_driver.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/drivers/plic/plic_driver.c
new file mode 100644
index 0000000..4f0e495
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/drivers/plic/plic_driver.c
@@ -0,0 +1,127 @@
+// See LICENSE for license details.
+
+#include "sifive/devices/plic.h"
+#include "plic/plic_driver.h"
+#include "platform.h"
+#include "encoding.h"
+#include 
+
+
+// Note that there are no assertions or bounds checking on these
+// parameter values.
+
+void volatile_memzero(uint8_t * base, unsigned int size)
+{
+  volatile uint8_t * ptr;
+  for (ptr = base; ptr < (base + size); ptr++){
+    *ptr = 0;
+  }
+}
+
+void PLIC_init (
+                plic_instance_t * this_plic,
+                uintptr_t         base_addr,
+                uint32_t num_sources,
+                uint32_t num_priorities
+                )
+{
+  
+  this_plic->base_addr = base_addr;
+  this_plic->num_sources = num_sources;
+  this_plic->num_priorities = num_priorities;
+  
+  // Disable all interrupts (don't assume that these registers are reset).
+  unsigned long hart_id = read_csr(mhartid);
+  volatile_memzero((uint8_t*) (this_plic->base_addr +
+                               PLIC_ENABLE_OFFSET +
+                               (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET)),
+                   (num_sources + 8) / 8);
+  
+  // Set all priorities to 0 (equal priority -- don't assume that these are reset).
+  volatile_memzero ((uint8_t *)(this_plic->base_addr +
+                                PLIC_PRIORITY_OFFSET),
+                    (num_sources + 1) << PLIC_PRIORITY_SHIFT_PER_SOURCE);
+
+  // Set the threshold to 0.
+  volatile plic_threshold* threshold = (plic_threshold*)
+    (this_plic->base_addr +
+     PLIC_THRESHOLD_OFFSET +
+     (hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET));
+
+  *threshold = 0;
+  
+}
+
+void PLIC_set_threshold (plic_instance_t * this_plic,
+			 plic_threshold threshold){
+
+  unsigned long hart_id = read_csr(mhartid);  
+  volatile plic_threshold* threshold_ptr = (plic_threshold*) (this_plic->base_addr +
+                                                              PLIC_THRESHOLD_OFFSET +
+                                                              (hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET));
+
+  *threshold_ptr = threshold;
+
+}
+  
+
+void PLIC_enable_interrupt (plic_instance_t * this_plic, plic_source source){
+
+  unsigned long hart_id = read_csr(mhartid);
+  volatile uint8_t * current_ptr = (volatile uint8_t *)(this_plic->base_addr +
+                                                        PLIC_ENABLE_OFFSET +
+                                                        (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) +
+                                                        (source >> 3));
+  uint8_t current = *current_ptr;
+  current = current | ( 1 << (source & 0x7));
+  *current_ptr = current;
+
+}
+
+void PLIC_disable_interrupt (plic_instance_t * this_plic, plic_source source){
+  
+  unsigned long hart_id = read_csr(mhartid);
+  volatile uint8_t * current_ptr = (volatile uint8_t *) (this_plic->base_addr +
+                                                         PLIC_ENABLE_OFFSET +
+                                                         (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) +
+                                                         (source >> 3));
+  uint8_t current = *current_ptr;
+  current = current & ~(( 1 << (source & 0x7)));
+  *current_ptr = current;
+  
+}
+
+void PLIC_set_priority (plic_instance_t * this_plic, plic_source source, plic_priority priority){
+
+  if (this_plic->num_priorities > 0) {
+    volatile plic_priority * priority_ptr = (volatile plic_priority *)
+      (this_plic->base_addr +
+       PLIC_PRIORITY_OFFSET +
+       (source << PLIC_PRIORITY_SHIFT_PER_SOURCE));
+    *priority_ptr = priority;
+  }
+}
+
+plic_source PLIC_claim_interrupt(plic_instance_t * this_plic){
+  
+  unsigned long hart_id = read_csr(mhartid);
+
+  volatile plic_source * claim_addr = (volatile plic_source * )
+    (this_plic->base_addr +
+     PLIC_CLAIM_OFFSET +
+     (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET));
+
+  return  *claim_addr;
+  
+}
+
+void PLIC_complete_interrupt(plic_instance_t * this_plic, plic_source source){
+  
+  unsigned long hart_id = read_csr(mhartid);
+  volatile plic_source * claim_addr = (volatile plic_source *) (this_plic->base_addr +
+                                                                PLIC_CLAIM_OFFSET +
+                                                                (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET));
+  *claim_addr = source;
+  
+}
+
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/drivers/plic/plic_driver.h b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/drivers/plic/plic_driver.h
new file mode 100644
index 0000000..8ce8e51
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/drivers/plic/plic_driver.h
@@ -0,0 +1,51 @@
+// See LICENSE file for licence details
+
+#ifndef PLIC_DRIVER_H
+#define PLIC_DRIVER_H
+
+
+__BEGIN_DECLS
+
+#include "platform.h"
+
+typedef struct __plic_instance_t
+{
+  uintptr_t base_addr;
+
+  uint32_t num_sources;
+  uint32_t num_priorities;
+  
+} plic_instance_t;
+
+typedef uint32_t plic_source;
+typedef uint32_t plic_priority;
+typedef uint32_t plic_threshold;
+
+void PLIC_init (
+                plic_instance_t * this_plic,
+                uintptr_t         base_addr,
+                uint32_t num_sources,
+                uint32_t num_priorities
+                );
+
+void PLIC_set_threshold (plic_instance_t * this_plic,
+			 plic_threshold threshold);
+  
+void PLIC_enable_interrupt (plic_instance_t * this_plic,
+			    plic_source source);
+
+void PLIC_disable_interrupt (plic_instance_t * this_plic,
+			     plic_source source);
+  
+void PLIC_set_priority (plic_instance_t * this_plic,
+			plic_source source,
+			plic_priority priority);
+
+plic_source PLIC_claim_interrupt(plic_instance_t * this_plic);
+
+void PLIC_complete_interrupt(plic_instance_t * this_plic,
+			     plic_source source);
+
+__END_DECLS
+
+#endif
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/encoding.h b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/encoding.h
new file mode 100644
index 0000000..417e751
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/encoding.h
@@ -0,0 +1,1313 @@
+// See LICENSE for license details.
+
+#ifndef RISCV_CSR_ENCODING_H
+#define RISCV_CSR_ENCODING_H
+
+#define MSTATUS_UIE         0x00000001
+#define MSTATUS_SIE         0x00000002
+#define MSTATUS_HIE         0x00000004
+#define MSTATUS_MIE         0x00000008
+#define MSTATUS_UPIE        0x00000010
+#define MSTATUS_SPIE        0x00000020
+#define MSTATUS_HPIE        0x00000040
+#define MSTATUS_MPIE        0x00000080
+#define MSTATUS_SPP         0x00000100
+#define MSTATUS_HPP         0x00000600
+#define MSTATUS_MPP         0x00001800
+#define MSTATUS_FS          0x00006000
+#define MSTATUS_XS          0x00018000
+#define MSTATUS_MPRV        0x00020000
+#define MSTATUS_PUM         0x00040000
+#define MSTATUS_MXR         0x00080000
+#define MSTATUS_VM          0x1F000000
+#define MSTATUS32_SD        0x80000000
+#define MSTATUS64_SD        0x8000000000000000
+
+#define SSTATUS_UIE         0x00000001
+#define SSTATUS_SIE         0x00000002
+#define SSTATUS_UPIE        0x00000010
+#define SSTATUS_SPIE        0x00000020
+#define SSTATUS_SPP         0x00000100
+#define SSTATUS_FS          0x00006000
+#define SSTATUS_XS          0x00018000
+#define SSTATUS_PUM         0x00040000
+#define SSTATUS32_SD        0x80000000
+#define SSTATUS64_SD        0x8000000000000000
+
+#define DCSR_XDEBUGVER      (3U<<30)
+#define DCSR_NDRESET        (1<<29)
+#define DCSR_FULLRESET      (1<<28)
+#define DCSR_EBREAKM        (1<<15)
+#define DCSR_EBREAKH        (1<<14)
+#define DCSR_EBREAKS        (1<<13)
+#define DCSR_EBREAKU        (1<<12)
+#define DCSR_STOPCYCLE      (1<<10)
+#define DCSR_STOPTIME       (1<<9)
+#define DCSR_CAUSE          (7<<6)
+#define DCSR_DEBUGINT       (1<<5)
+#define DCSR_HALT           (1<<3)
+#define DCSR_STEP           (1<<2)
+#define DCSR_PRV            (3<<0)
+
+#define DCSR_CAUSE_NONE     0
+#define DCSR_CAUSE_SWBP     1
+#define DCSR_CAUSE_HWBP     2
+#define DCSR_CAUSE_DEBUGINT 3
+#define DCSR_CAUSE_STEP     4
+#define DCSR_CAUSE_HALT     5
+
+#define MCONTROL_TYPE(xlen)    (0xfULL<<((xlen)-4))
+#define MCONTROL_DMODE(xlen)   (1ULL<<((xlen)-5))
+#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
+
+#define MCONTROL_SELECT     (1<<19)
+#define MCONTROL_TIMING     (1<<18)
+#define MCONTROL_ACTION     (0x3f<<12)
+#define MCONTROL_CHAIN      (1<<11)
+#define MCONTROL_MATCH      (0xf<<7)
+#define MCONTROL_M          (1<<6)
+#define MCONTROL_H          (1<<5)
+#define MCONTROL_S          (1<<4)
+#define MCONTROL_U          (1<<3)
+#define MCONTROL_EXECUTE    (1<<2)
+#define MCONTROL_STORE      (1<<1)
+#define MCONTROL_LOAD       (1<<0)
+
+#define MCONTROL_TYPE_NONE      0
+#define MCONTROL_TYPE_MATCH     2
+
+#define MCONTROL_ACTION_DEBUG_EXCEPTION   0
+#define MCONTROL_ACTION_DEBUG_MODE        1
+#define MCONTROL_ACTION_TRACE_START       2
+#define MCONTROL_ACTION_TRACE_STOP        3
+#define MCONTROL_ACTION_TRACE_EMIT        4
+
+#define MCONTROL_MATCH_EQUAL     0
+#define MCONTROL_MATCH_NAPOT     1
+#define MCONTROL_MATCH_GE        2
+#define MCONTROL_MATCH_LT        3
+#define MCONTROL_MATCH_MASK_LOW  4
+#define MCONTROL_MATCH_MASK_HIGH 5
+
+#define MIP_SSIP            (1 << IRQ_S_SOFT)
+#define MIP_HSIP            (1 << IRQ_H_SOFT)
+#define MIP_MSIP            (1 << IRQ_M_SOFT)
+#define MIP_STIP            (1 << IRQ_S_TIMER)
+#define MIP_HTIP            (1 << IRQ_H_TIMER)
+#define MIP_MTIP            (1 << IRQ_M_TIMER)
+#define MIP_SEIP            (1 << IRQ_S_EXT)
+#define MIP_HEIP            (1 << IRQ_H_EXT)
+#define MIP_MEIP            (1 << IRQ_M_EXT)
+
+#define SIP_SSIP MIP_SSIP
+#define SIP_STIP MIP_STIP
+
+#define PRV_U 0
+#define PRV_S 1
+#define PRV_H 2
+#define PRV_M 3
+
+#define VM_MBARE 0
+#define VM_MBB   1
+#define VM_MBBID 2
+#define VM_SV32  8
+#define VM_SV39  9
+#define VM_SV48  10
+
+#define IRQ_S_SOFT   1
+#define IRQ_H_SOFT   2
+#define IRQ_M_SOFT   3
+#define IRQ_S_TIMER  5
+#define IRQ_H_TIMER  6
+#define IRQ_M_TIMER  7
+#define IRQ_S_EXT    9
+#define IRQ_H_EXT    10
+#define IRQ_M_EXT    11
+#define IRQ_COP      12
+#define IRQ_HOST     13
+
+#define DEFAULT_RSTVEC     0x00001000
+#define DEFAULT_NMIVEC     0x00001004
+#define DEFAULT_MTVEC      0x00001010
+#define CONFIG_STRING_ADDR 0x0000100C
+#define EXT_IO_BASE        0x40000000
+#define DRAM_BASE          0x80000000
+
+// page table entry (PTE) fields
+#define PTE_V     0x001 // Valid
+#define PTE_R     0x002 // Read
+#define PTE_W     0x004 // Write
+#define PTE_X     0x008 // Execute
+#define PTE_U     0x010 // User
+#define PTE_G     0x020 // Global
+#define PTE_A     0x040 // Accessed
+#define PTE_D     0x080 // Dirty
+#define PTE_SOFT  0x300 // Reserved for Software
+
+#define PTE_PPN_SHIFT 10
+
+#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
+
+#ifdef __riscv
+
+#ifdef __riscv64
+# define MSTATUS_SD MSTATUS64_SD
+# define SSTATUS_SD SSTATUS64_SD
+# define RISCV_PGLEVEL_BITS 9
+#else
+# define MSTATUS_SD MSTATUS32_SD
+# define SSTATUS_SD SSTATUS32_SD
+# define RISCV_PGLEVEL_BITS 10
+#endif
+#define RISCV_PGSHIFT 12
+#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
+
+#ifndef __ASSEMBLER__
+
+#ifdef __GNUC__
+
+#define read_csr(reg) ({ unsigned long __tmp; \
+  asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+  __tmp; })
+
+#define write_csr(reg, val) ({ \
+  if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+    asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
+  else \
+    asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
+
+#define swap_csr(reg, val) ({ unsigned long __tmp; \
+  if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+    asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
+  else \
+    asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
+  __tmp; })
+
+#define set_csr(reg, bit) ({ unsigned long __tmp; \
+  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+    asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+  else \
+    asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+  __tmp; })
+
+#define clear_csr(reg, bit) ({ unsigned long __tmp; \
+  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+    asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+  else \
+    asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+  __tmp; })
+
+#define rdtime() read_csr(time)
+#define rdcycle() read_csr(cycle)
+#define rdinstret() read_csr(instret)
+
+#endif
+
+#endif
+
+#endif
+
+#endif
+/* Automatically generated by parse-opcodes */
+#ifndef RISCV_ENCODING_H
+#define RISCV_ENCODING_H
+#define MATCH_BEQ 0x63
+#define MASK_BEQ  0x707f
+#define MATCH_BNE 0x1063
+#define MASK_BNE  0x707f
+#define MATCH_BLT 0x4063
+#define MASK_BLT  0x707f
+#define MATCH_BGE 0x5063
+#define MASK_BGE  0x707f
+#define MATCH_BLTU 0x6063
+#define MASK_BLTU  0x707f
+#define MATCH_BGEU 0x7063
+#define MASK_BGEU  0x707f
+#define MATCH_JALR 0x67
+#define MASK_JALR  0x707f
+#define MATCH_JAL 0x6f
+#define MASK_JAL  0x7f
+#define MATCH_LUI 0x37
+#define MASK_LUI  0x7f
+#define MATCH_AUIPC 0x17
+#define MASK_AUIPC  0x7f
+#define MATCH_ADDI 0x13
+#define MASK_ADDI  0x707f
+#define MATCH_SLLI 0x1013
+#define MASK_SLLI  0xfc00707f
+#define MATCH_SLTI 0x2013
+#define MASK_SLTI  0x707f
+#define MATCH_SLTIU 0x3013
+#define MASK_SLTIU  0x707f
+#define MATCH_XORI 0x4013
+#define MASK_XORI  0x707f
+#define MATCH_SRLI 0x5013
+#define MASK_SRLI  0xfc00707f
+#define MATCH_SRAI 0x40005013
+#define MASK_SRAI  0xfc00707f
+#define MATCH_ORI 0x6013
+#define MASK_ORI  0x707f
+#define MATCH_ANDI 0x7013
+#define MASK_ANDI  0x707f
+#define MATCH_ADD 0x33
+#define MASK_ADD  0xfe00707f
+#define MATCH_SUB 0x40000033
+#define MASK_SUB  0xfe00707f
+#define MATCH_SLL 0x1033
+#define MASK_SLL  0xfe00707f
+#define MATCH_SLT 0x2033
+#define MASK_SLT  0xfe00707f
+#define MATCH_SLTU 0x3033
+#define MASK_SLTU  0xfe00707f
+#define MATCH_XOR 0x4033
+#define MASK_XOR  0xfe00707f
+#define MATCH_SRL 0x5033
+#define MASK_SRL  0xfe00707f
+#define MATCH_SRA 0x40005033
+#define MASK_SRA  0xfe00707f
+#define MATCH_OR 0x6033
+#define MASK_OR  0xfe00707f
+#define MATCH_AND 0x7033
+#define MASK_AND  0xfe00707f
+#define MATCH_ADDIW 0x1b
+#define MASK_ADDIW  0x707f
+#define MATCH_SLLIW 0x101b
+#define MASK_SLLIW  0xfe00707f
+#define MATCH_SRLIW 0x501b
+#define MASK_SRLIW  0xfe00707f
+#define MATCH_SRAIW 0x4000501b
+#define MASK_SRAIW  0xfe00707f
+#define MATCH_ADDW 0x3b
+#define MASK_ADDW  0xfe00707f
+#define MATCH_SUBW 0x4000003b
+#define MASK_SUBW  0xfe00707f
+#define MATCH_SLLW 0x103b
+#define MASK_SLLW  0xfe00707f
+#define MATCH_SRLW 0x503b
+#define MASK_SRLW  0xfe00707f
+#define MATCH_SRAW 0x4000503b
+#define MASK_SRAW  0xfe00707f
+#define MATCH_LB 0x3
+#define MASK_LB  0x707f
+#define MATCH_LH 0x1003
+#define MASK_LH  0x707f
+#define MATCH_LW 0x2003
+#define MASK_LW  0x707f
+#define MATCH_LD 0x3003
+#define MASK_LD  0x707f
+#define MATCH_LBU 0x4003
+#define MASK_LBU  0x707f
+#define MATCH_LHU 0x5003
+#define MASK_LHU  0x707f
+#define MATCH_LWU 0x6003
+#define MASK_LWU  0x707f
+#define MATCH_SB 0x23
+#define MASK_SB  0x707f
+#define MATCH_SH 0x1023
+#define MASK_SH  0x707f
+#define MATCH_SW 0x2023
+#define MASK_SW  0x707f
+#define MATCH_SD 0x3023
+#define MASK_SD  0x707f
+#define MATCH_FENCE 0xf
+#define MASK_FENCE  0x707f
+#define MATCH_FENCE_I 0x100f
+#define MASK_FENCE_I  0x707f
+#define MATCH_MUL 0x2000033
+#define MASK_MUL  0xfe00707f
+#define MATCH_MULH 0x2001033
+#define MASK_MULH  0xfe00707f
+#define MATCH_MULHSU 0x2002033
+#define MASK_MULHSU  0xfe00707f
+#define MATCH_MULHU 0x2003033
+#define MASK_MULHU  0xfe00707f
+#define MATCH_DIV 0x2004033
+#define MASK_DIV  0xfe00707f
+#define MATCH_DIVU 0x2005033
+#define MASK_DIVU  0xfe00707f
+#define MATCH_REM 0x2006033
+#define MASK_REM  0xfe00707f
+#define MATCH_REMU 0x2007033
+#define MASK_REMU  0xfe00707f
+#define MATCH_MULW 0x200003b
+#define MASK_MULW  0xfe00707f
+#define MATCH_DIVW 0x200403b
+#define MASK_DIVW  0xfe00707f
+#define MATCH_DIVUW 0x200503b
+#define MASK_DIVUW  0xfe00707f
+#define MATCH_REMW 0x200603b
+#define MASK_REMW  0xfe00707f
+#define MATCH_REMUW 0x200703b
+#define MASK_REMUW  0xfe00707f
+#define MATCH_AMOADD_W 0x202f
+#define MASK_AMOADD_W  0xf800707f
+#define MATCH_AMOXOR_W 0x2000202f
+#define MASK_AMOXOR_W  0xf800707f
+#define MATCH_AMOOR_W 0x4000202f
+#define MASK_AMOOR_W  0xf800707f
+#define MATCH_AMOAND_W 0x6000202f
+#define MASK_AMOAND_W  0xf800707f
+#define MATCH_AMOMIN_W 0x8000202f
+#define MASK_AMOMIN_W  0xf800707f
+#define MATCH_AMOMAX_W 0xa000202f
+#define MASK_AMOMAX_W  0xf800707f
+#define MATCH_AMOMINU_W 0xc000202f
+#define MASK_AMOMINU_W  0xf800707f
+#define MATCH_AMOMAXU_W 0xe000202f
+#define MASK_AMOMAXU_W  0xf800707f
+#define MATCH_AMOSWAP_W 0x800202f
+#define MASK_AMOSWAP_W  0xf800707f
+#define MATCH_LR_W 0x1000202f
+#define MASK_LR_W  0xf9f0707f
+#define MATCH_SC_W 0x1800202f
+#define MASK_SC_W  0xf800707f
+#define MATCH_AMOADD_D 0x302f
+#define MASK_AMOADD_D  0xf800707f
+#define MATCH_AMOXOR_D 0x2000302f
+#define MASK_AMOXOR_D  0xf800707f
+#define MATCH_AMOOR_D 0x4000302f
+#define MASK_AMOOR_D  0xf800707f
+#define MATCH_AMOAND_D 0x6000302f
+#define MASK_AMOAND_D  0xf800707f
+#define MATCH_AMOMIN_D 0x8000302f
+#define MASK_AMOMIN_D  0xf800707f
+#define MATCH_AMOMAX_D 0xa000302f
+#define MASK_AMOMAX_D  0xf800707f
+#define MATCH_AMOMINU_D 0xc000302f
+#define MASK_AMOMINU_D  0xf800707f
+#define MATCH_AMOMAXU_D 0xe000302f
+#define MASK_AMOMAXU_D  0xf800707f
+#define MATCH_AMOSWAP_D 0x800302f
+#define MASK_AMOSWAP_D  0xf800707f
+#define MATCH_LR_D 0x1000302f
+#define MASK_LR_D  0xf9f0707f
+#define MATCH_SC_D 0x1800302f
+#define MASK_SC_D  0xf800707f
+#define MATCH_ECALL 0x73
+#define MASK_ECALL  0xffffffff
+#define MATCH_EBREAK 0x100073
+#define MASK_EBREAK  0xffffffff
+#define MATCH_URET 0x200073
+#define MASK_URET  0xffffffff
+#define MATCH_SRET 0x10200073
+#define MASK_SRET  0xffffffff
+#define MATCH_HRET 0x20200073
+#define MASK_HRET  0xffffffff
+#define MATCH_MRET 0x30200073
+#define MASK_MRET  0xffffffff
+#define MATCH_DRET 0x7b200073
+#define MASK_DRET  0xffffffff
+#define MATCH_SFENCE_VM 0x10400073
+#define MASK_SFENCE_VM  0xfff07fff
+#define MATCH_WFI 0x10500073
+#define MASK_WFI  0xffffffff
+#define MATCH_CSRRW 0x1073
+#define MASK_CSRRW  0x707f
+#define MATCH_CSRRS 0x2073
+#define MASK_CSRRS  0x707f
+#define MATCH_CSRRC 0x3073
+#define MASK_CSRRC  0x707f
+#define MATCH_CSRRWI 0x5073
+#define MASK_CSRRWI  0x707f
+#define MATCH_CSRRSI 0x6073
+#define MASK_CSRRSI  0x707f
+#define MATCH_CSRRCI 0x7073
+#define MASK_CSRRCI  0x707f
+#define MATCH_FADD_S 0x53
+#define MASK_FADD_S  0xfe00007f
+#define MATCH_FSUB_S 0x8000053
+#define MASK_FSUB_S  0xfe00007f
+#define MATCH_FMUL_S 0x10000053
+#define MASK_FMUL_S  0xfe00007f
+#define MATCH_FDIV_S 0x18000053
+#define MASK_FDIV_S  0xfe00007f
+#define MATCH_FSGNJ_S 0x20000053
+#define MASK_FSGNJ_S  0xfe00707f
+#define MATCH_FSGNJN_S 0x20001053
+#define MASK_FSGNJN_S  0xfe00707f
+#define MATCH_FSGNJX_S 0x20002053
+#define MASK_FSGNJX_S  0xfe00707f
+#define MATCH_FMIN_S 0x28000053
+#define MASK_FMIN_S  0xfe00707f
+#define MATCH_FMAX_S 0x28001053
+#define MASK_FMAX_S  0xfe00707f
+#define MATCH_FSQRT_S 0x58000053
+#define MASK_FSQRT_S  0xfff0007f
+#define MATCH_FADD_D 0x2000053
+#define MASK_FADD_D  0xfe00007f
+#define MATCH_FSUB_D 0xa000053
+#define MASK_FSUB_D  0xfe00007f
+#define MATCH_FMUL_D 0x12000053
+#define MASK_FMUL_D  0xfe00007f
+#define MATCH_FDIV_D 0x1a000053
+#define MASK_FDIV_D  0xfe00007f
+#define MATCH_FSGNJ_D 0x22000053
+#define MASK_FSGNJ_D  0xfe00707f
+#define MATCH_FSGNJN_D 0x22001053
+#define MASK_FSGNJN_D  0xfe00707f
+#define MATCH_FSGNJX_D 0x22002053
+#define MASK_FSGNJX_D  0xfe00707f
+#define MATCH_FMIN_D 0x2a000053
+#define MASK_FMIN_D  0xfe00707f
+#define MATCH_FMAX_D 0x2a001053
+#define MASK_FMAX_D  0xfe00707f
+#define MATCH_FCVT_S_D 0x40100053
+#define MASK_FCVT_S_D  0xfff0007f
+#define MATCH_FCVT_D_S 0x42000053
+#define MASK_FCVT_D_S  0xfff0007f
+#define MATCH_FSQRT_D 0x5a000053
+#define MASK_FSQRT_D  0xfff0007f
+#define MATCH_FLE_S 0xa0000053
+#define MASK_FLE_S  0xfe00707f
+#define MATCH_FLT_S 0xa0001053
+#define MASK_FLT_S  0xfe00707f
+#define MATCH_FEQ_S 0xa0002053
+#define MASK_FEQ_S  0xfe00707f
+#define MATCH_FLE_D 0xa2000053
+#define MASK_FLE_D  0xfe00707f
+#define MATCH_FLT_D 0xa2001053
+#define MASK_FLT_D  0xfe00707f
+#define MATCH_FEQ_D 0xa2002053
+#define MASK_FEQ_D  0xfe00707f
+#define MATCH_FCVT_W_S 0xc0000053
+#define MASK_FCVT_W_S  0xfff0007f
+#define MATCH_FCVT_WU_S 0xc0100053
+#define MASK_FCVT_WU_S  0xfff0007f
+#define MATCH_FCVT_L_S 0xc0200053
+#define MASK_FCVT_L_S  0xfff0007f
+#define MATCH_FCVT_LU_S 0xc0300053
+#define MASK_FCVT_LU_S  0xfff0007f
+#define MATCH_FMV_X_S 0xe0000053
+#define MASK_FMV_X_S  0xfff0707f
+#define MATCH_FCLASS_S 0xe0001053
+#define MASK_FCLASS_S  0xfff0707f
+#define MATCH_FCVT_W_D 0xc2000053
+#define MASK_FCVT_W_D  0xfff0007f
+#define MATCH_FCVT_WU_D 0xc2100053
+#define MASK_FCVT_WU_D  0xfff0007f
+#define MATCH_FCVT_L_D 0xc2200053
+#define MASK_FCVT_L_D  0xfff0007f
+#define MATCH_FCVT_LU_D 0xc2300053
+#define MASK_FCVT_LU_D  0xfff0007f
+#define MATCH_FMV_X_D 0xe2000053
+#define MASK_FMV_X_D  0xfff0707f
+#define MATCH_FCLASS_D 0xe2001053
+#define MASK_FCLASS_D  0xfff0707f
+#define MATCH_FCVT_S_W 0xd0000053
+#define MASK_FCVT_S_W  0xfff0007f
+#define MATCH_FCVT_S_WU 0xd0100053
+#define MASK_FCVT_S_WU  0xfff0007f
+#define MATCH_FCVT_S_L 0xd0200053
+#define MASK_FCVT_S_L  0xfff0007f
+#define MATCH_FCVT_S_LU 0xd0300053
+#define MASK_FCVT_S_LU  0xfff0007f
+#define MATCH_FMV_S_X 0xf0000053
+#define MASK_FMV_S_X  0xfff0707f
+#define MATCH_FCVT_D_W 0xd2000053
+#define MASK_FCVT_D_W  0xfff0007f
+#define MATCH_FCVT_D_WU 0xd2100053
+#define MASK_FCVT_D_WU  0xfff0007f
+#define MATCH_FCVT_D_L 0xd2200053
+#define MASK_FCVT_D_L  0xfff0007f
+#define MATCH_FCVT_D_LU 0xd2300053
+#define MASK_FCVT_D_LU  0xfff0007f
+#define MATCH_FMV_D_X 0xf2000053
+#define MASK_FMV_D_X  0xfff0707f
+#define MATCH_FLW 0x2007
+#define MASK_FLW  0x707f
+#define MATCH_FLD 0x3007
+#define MASK_FLD  0x707f
+#define MATCH_FSW 0x2027
+#define MASK_FSW  0x707f
+#define MATCH_FSD 0x3027
+#define MASK_FSD  0x707f
+#define MATCH_FMADD_S 0x43
+#define MASK_FMADD_S  0x600007f
+#define MATCH_FMSUB_S 0x47
+#define MASK_FMSUB_S  0x600007f
+#define MATCH_FNMSUB_S 0x4b
+#define MASK_FNMSUB_S  0x600007f
+#define MATCH_FNMADD_S 0x4f
+#define MASK_FNMADD_S  0x600007f
+#define MATCH_FMADD_D 0x2000043
+#define MASK_FMADD_D  0x600007f
+#define MATCH_FMSUB_D 0x2000047
+#define MASK_FMSUB_D  0x600007f
+#define MATCH_FNMSUB_D 0x200004b
+#define MASK_FNMSUB_D  0x600007f
+#define MATCH_FNMADD_D 0x200004f
+#define MASK_FNMADD_D  0x600007f
+#define MATCH_C_NOP 0x1
+#define MASK_C_NOP  0xffff
+#define MATCH_C_ADDI16SP 0x6101
+#define MASK_C_ADDI16SP  0xef83
+#define MATCH_C_JR 0x8002
+#define MASK_C_JR  0xf07f
+#define MATCH_C_JALR 0x9002
+#define MASK_C_JALR  0xf07f
+#define MATCH_C_EBREAK 0x9002
+#define MASK_C_EBREAK  0xffff
+#define MATCH_C_LD 0x6000
+#define MASK_C_LD  0xe003
+#define MATCH_C_SD 0xe000
+#define MASK_C_SD  0xe003
+#define MATCH_C_ADDIW 0x2001
+#define MASK_C_ADDIW  0xe003
+#define MATCH_C_LDSP 0x6002
+#define MASK_C_LDSP  0xe003
+#define MATCH_C_SDSP 0xe002
+#define MASK_C_SDSP  0xe003
+#define MATCH_C_ADDI4SPN 0x0
+#define MASK_C_ADDI4SPN  0xe003
+#define MATCH_C_FLD 0x2000
+#define MASK_C_FLD  0xe003
+#define MATCH_C_LW 0x4000
+#define MASK_C_LW  0xe003
+#define MATCH_C_FLW 0x6000
+#define MASK_C_FLW  0xe003
+#define MATCH_C_FSD 0xa000
+#define MASK_C_FSD  0xe003
+#define MATCH_C_SW 0xc000
+#define MASK_C_SW  0xe003
+#define MATCH_C_FSW 0xe000
+#define MASK_C_FSW  0xe003
+#define MATCH_C_ADDI 0x1
+#define MASK_C_ADDI  0xe003
+#define MATCH_C_JAL 0x2001
+#define MASK_C_JAL  0xe003
+#define MATCH_C_LI 0x4001
+#define MASK_C_LI  0xe003
+#define MATCH_C_LUI 0x6001
+#define MASK_C_LUI  0xe003
+#define MATCH_C_SRLI 0x8001
+#define MASK_C_SRLI  0xec03
+#define MATCH_C_SRAI 0x8401
+#define MASK_C_SRAI  0xec03
+#define MATCH_C_ANDI 0x8801
+#define MASK_C_ANDI  0xec03
+#define MATCH_C_SUB 0x8c01
+#define MASK_C_SUB  0xfc63
+#define MATCH_C_XOR 0x8c21
+#define MASK_C_XOR  0xfc63
+#define MATCH_C_OR 0x8c41
+#define MASK_C_OR  0xfc63
+#define MATCH_C_AND 0x8c61
+#define MASK_C_AND  0xfc63
+#define MATCH_C_SUBW 0x9c01
+#define MASK_C_SUBW  0xfc63
+#define MATCH_C_ADDW 0x9c21
+#define MASK_C_ADDW  0xfc63
+#define MATCH_C_J 0xa001
+#define MASK_C_J  0xe003
+#define MATCH_C_BEQZ 0xc001
+#define MASK_C_BEQZ  0xe003
+#define MATCH_C_BNEZ 0xe001
+#define MASK_C_BNEZ  0xe003
+#define MATCH_C_SLLI 0x2
+#define MASK_C_SLLI  0xe003
+#define MATCH_C_FLDSP 0x2002
+#define MASK_C_FLDSP  0xe003
+#define MATCH_C_LWSP 0x4002
+#define MASK_C_LWSP  0xe003
+#define MATCH_C_FLWSP 0x6002
+#define MASK_C_FLWSP  0xe003
+#define MATCH_C_MV 0x8002
+#define MASK_C_MV  0xf003
+#define MATCH_C_ADD 0x9002
+#define MASK_C_ADD  0xf003
+#define MATCH_C_FSDSP 0xa002
+#define MASK_C_FSDSP  0xe003
+#define MATCH_C_SWSP 0xc002
+#define MASK_C_SWSP  0xe003
+#define MATCH_C_FSWSP 0xe002
+#define MASK_C_FSWSP  0xe003
+#define MATCH_CUSTOM0 0xb
+#define MASK_CUSTOM0  0x707f
+#define MATCH_CUSTOM0_RS1 0x200b
+#define MASK_CUSTOM0_RS1  0x707f
+#define MATCH_CUSTOM0_RS1_RS2 0x300b
+#define MASK_CUSTOM0_RS1_RS2  0x707f
+#define MATCH_CUSTOM0_RD 0x400b
+#define MASK_CUSTOM0_RD  0x707f
+#define MATCH_CUSTOM0_RD_RS1 0x600b
+#define MASK_CUSTOM0_RD_RS1  0x707f
+#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
+#define MASK_CUSTOM0_RD_RS1_RS2  0x707f
+#define MATCH_CUSTOM1 0x2b
+#define MASK_CUSTOM1  0x707f
+#define MATCH_CUSTOM1_RS1 0x202b
+#define MASK_CUSTOM1_RS1  0x707f
+#define MATCH_CUSTOM1_RS1_RS2 0x302b
+#define MASK_CUSTOM1_RS1_RS2  0x707f
+#define MATCH_CUSTOM1_RD 0x402b
+#define MASK_CUSTOM1_RD  0x707f
+#define MATCH_CUSTOM1_RD_RS1 0x602b
+#define MASK_CUSTOM1_RD_RS1  0x707f
+#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
+#define MASK_CUSTOM1_RD_RS1_RS2  0x707f
+#define MATCH_CUSTOM2 0x5b
+#define MASK_CUSTOM2  0x707f
+#define MATCH_CUSTOM2_RS1 0x205b
+#define MASK_CUSTOM2_RS1  0x707f
+#define MATCH_CUSTOM2_RS1_RS2 0x305b
+#define MASK_CUSTOM2_RS1_RS2  0x707f
+#define MATCH_CUSTOM2_RD 0x405b
+#define MASK_CUSTOM2_RD  0x707f
+#define MATCH_CUSTOM2_RD_RS1 0x605b
+#define MASK_CUSTOM2_RD_RS1  0x707f
+#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
+#define MASK_CUSTOM2_RD_RS1_RS2  0x707f
+#define MATCH_CUSTOM3 0x7b
+#define MASK_CUSTOM3  0x707f
+#define MATCH_CUSTOM3_RS1 0x207b
+#define MASK_CUSTOM3_RS1  0x707f
+#define MATCH_CUSTOM3_RS1_RS2 0x307b
+#define MASK_CUSTOM3_RS1_RS2  0x707f
+#define MATCH_CUSTOM3_RD 0x407b
+#define MASK_CUSTOM3_RD  0x707f
+#define MATCH_CUSTOM3_RD_RS1 0x607b
+#define MASK_CUSTOM3_RD_RS1  0x707f
+#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
+#define MASK_CUSTOM3_RD_RS1_RS2  0x707f
+#define CSR_FFLAGS 0x1
+#define CSR_FRM 0x2
+#define CSR_FCSR 0x3
+#define CSR_CYCLE 0xc00
+#define CSR_TIME 0xc01
+#define CSR_INSTRET 0xc02
+#define CSR_HPMCOUNTER3 0xc03
+#define CSR_HPMCOUNTER4 0xc04
+#define CSR_HPMCOUNTER5 0xc05
+#define CSR_HPMCOUNTER6 0xc06
+#define CSR_HPMCOUNTER7 0xc07
+#define CSR_HPMCOUNTER8 0xc08
+#define CSR_HPMCOUNTER9 0xc09
+#define CSR_HPMCOUNTER10 0xc0a
+#define CSR_HPMCOUNTER11 0xc0b
+#define CSR_HPMCOUNTER12 0xc0c
+#define CSR_HPMCOUNTER13 0xc0d
+#define CSR_HPMCOUNTER14 0xc0e
+#define CSR_HPMCOUNTER15 0xc0f
+#define CSR_HPMCOUNTER16 0xc10
+#define CSR_HPMCOUNTER17 0xc11
+#define CSR_HPMCOUNTER18 0xc12
+#define CSR_HPMCOUNTER19 0xc13
+#define CSR_HPMCOUNTER20 0xc14
+#define CSR_HPMCOUNTER21 0xc15
+#define CSR_HPMCOUNTER22 0xc16
+#define CSR_HPMCOUNTER23 0xc17
+#define CSR_HPMCOUNTER24 0xc18
+#define CSR_HPMCOUNTER25 0xc19
+#define CSR_HPMCOUNTER26 0xc1a
+#define CSR_HPMCOUNTER27 0xc1b
+#define CSR_HPMCOUNTER28 0xc1c
+#define CSR_HPMCOUNTER29 0xc1d
+#define CSR_HPMCOUNTER30 0xc1e
+#define CSR_HPMCOUNTER31 0xc1f
+#define CSR_SSTATUS 0x100
+#define CSR_SIE 0x104
+#define CSR_STVEC 0x105
+#define CSR_SSCRATCH 0x140
+#define CSR_SEPC 0x141
+#define CSR_SCAUSE 0x142
+#define CSR_SBADADDR 0x143
+#define CSR_SIP 0x144
+#define CSR_SPTBR 0x180
+#define CSR_MSTATUS 0x300
+#define CSR_MISA 0x301
+#define CSR_MEDELEG 0x302
+#define CSR_MIDELEG 0x303
+#define CSR_MIE 0x304
+#define CSR_MTVEC 0x305
+#define CSR_MSCRATCH 0x340
+#define CSR_MEPC 0x341
+#define CSR_MCAUSE 0x342
+#define CSR_MBADADDR 0x343
+#define CSR_MIP 0x344
+#define CSR_TSELECT 0x7a0
+#define CSR_TDATA1 0x7a1
+#define CSR_TDATA2 0x7a2
+#define CSR_TDATA3 0x7a3
+#define CSR_DCSR 0x7b0
+#define CSR_DPC 0x7b1
+#define CSR_DSCRATCH 0x7b2
+#define CSR_MCYCLE 0xb00
+#define CSR_MINSTRET 0xb02
+#define CSR_MHPMCOUNTER3 0xb03
+#define CSR_MHPMCOUNTER4 0xb04
+#define CSR_MHPMCOUNTER5 0xb05
+#define CSR_MHPMCOUNTER6 0xb06
+#define CSR_MHPMCOUNTER7 0xb07
+#define CSR_MHPMCOUNTER8 0xb08
+#define CSR_MHPMCOUNTER9 0xb09
+#define CSR_MHPMCOUNTER10 0xb0a
+#define CSR_MHPMCOUNTER11 0xb0b
+#define CSR_MHPMCOUNTER12 0xb0c
+#define CSR_MHPMCOUNTER13 0xb0d
+#define CSR_MHPMCOUNTER14 0xb0e
+#define CSR_MHPMCOUNTER15 0xb0f
+#define CSR_MHPMCOUNTER16 0xb10
+#define CSR_MHPMCOUNTER17 0xb11
+#define CSR_MHPMCOUNTER18 0xb12
+#define CSR_MHPMCOUNTER19 0xb13
+#define CSR_MHPMCOUNTER20 0xb14
+#define CSR_MHPMCOUNTER21 0xb15
+#define CSR_MHPMCOUNTER22 0xb16
+#define CSR_MHPMCOUNTER23 0xb17
+#define CSR_MHPMCOUNTER24 0xb18
+#define CSR_MHPMCOUNTER25 0xb19
+#define CSR_MHPMCOUNTER26 0xb1a
+#define CSR_MHPMCOUNTER27 0xb1b
+#define CSR_MHPMCOUNTER28 0xb1c
+#define CSR_MHPMCOUNTER29 0xb1d
+#define CSR_MHPMCOUNTER30 0xb1e
+#define CSR_MHPMCOUNTER31 0xb1f
+#define CSR_MUCOUNTEREN 0x320
+#define CSR_MSCOUNTEREN 0x321
+#define CSR_MHPMEVENT3 0x323
+#define CSR_MHPMEVENT4 0x324
+#define CSR_MHPMEVENT5 0x325
+#define CSR_MHPMEVENT6 0x326
+#define CSR_MHPMEVENT7 0x327
+#define CSR_MHPMEVENT8 0x328
+#define CSR_MHPMEVENT9 0x329
+#define CSR_MHPMEVENT10 0x32a
+#define CSR_MHPMEVENT11 0x32b
+#define CSR_MHPMEVENT12 0x32c
+#define CSR_MHPMEVENT13 0x32d
+#define CSR_MHPMEVENT14 0x32e
+#define CSR_MHPMEVENT15 0x32f
+#define CSR_MHPMEVENT16 0x330
+#define CSR_MHPMEVENT17 0x331
+#define CSR_MHPMEVENT18 0x332
+#define CSR_MHPMEVENT19 0x333
+#define CSR_MHPMEVENT20 0x334
+#define CSR_MHPMEVENT21 0x335
+#define CSR_MHPMEVENT22 0x336
+#define CSR_MHPMEVENT23 0x337
+#define CSR_MHPMEVENT24 0x338
+#define CSR_MHPMEVENT25 0x339
+#define CSR_MHPMEVENT26 0x33a
+#define CSR_MHPMEVENT27 0x33b
+#define CSR_MHPMEVENT28 0x33c
+#define CSR_MHPMEVENT29 0x33d
+#define CSR_MHPMEVENT30 0x33e
+#define CSR_MHPMEVENT31 0x33f
+#define CSR_MVENDORID 0xf11
+#define CSR_MARCHID 0xf12
+#define CSR_MIMPID 0xf13
+#define CSR_MHARTID 0xf14
+#define CSR_CYCLEH 0xc80
+#define CSR_TIMEH 0xc81
+#define CSR_INSTRETH 0xc82
+#define CSR_HPMCOUNTER3H 0xc83
+#define CSR_HPMCOUNTER4H 0xc84
+#define CSR_HPMCOUNTER5H 0xc85
+#define CSR_HPMCOUNTER6H 0xc86
+#define CSR_HPMCOUNTER7H 0xc87
+#define CSR_HPMCOUNTER8H 0xc88
+#define CSR_HPMCOUNTER9H 0xc89
+#define CSR_HPMCOUNTER10H 0xc8a
+#define CSR_HPMCOUNTER11H 0xc8b
+#define CSR_HPMCOUNTER12H 0xc8c
+#define CSR_HPMCOUNTER13H 0xc8d
+#define CSR_HPMCOUNTER14H 0xc8e
+#define CSR_HPMCOUNTER15H 0xc8f
+#define CSR_HPMCOUNTER16H 0xc90
+#define CSR_HPMCOUNTER17H 0xc91
+#define CSR_HPMCOUNTER18H 0xc92
+#define CSR_HPMCOUNTER19H 0xc93
+#define CSR_HPMCOUNTER20H 0xc94
+#define CSR_HPMCOUNTER21H 0xc95
+#define CSR_HPMCOUNTER22H 0xc96
+#define CSR_HPMCOUNTER23H 0xc97
+#define CSR_HPMCOUNTER24H 0xc98
+#define CSR_HPMCOUNTER25H 0xc99
+#define CSR_HPMCOUNTER26H 0xc9a
+#define CSR_HPMCOUNTER27H 0xc9b
+#define CSR_HPMCOUNTER28H 0xc9c
+#define CSR_HPMCOUNTER29H 0xc9d
+#define CSR_HPMCOUNTER30H 0xc9e
+#define CSR_HPMCOUNTER31H 0xc9f
+#define CSR_MCYCLEH 0xb80
+#define CSR_MINSTRETH 0xb82
+#define CSR_MHPMCOUNTER3H 0xb83
+#define CSR_MHPMCOUNTER4H 0xb84
+#define CSR_MHPMCOUNTER5H 0xb85
+#define CSR_MHPMCOUNTER6H 0xb86
+#define CSR_MHPMCOUNTER7H 0xb87
+#define CSR_MHPMCOUNTER8H 0xb88
+#define CSR_MHPMCOUNTER9H 0xb89
+#define CSR_MHPMCOUNTER10H 0xb8a
+#define CSR_MHPMCOUNTER11H 0xb8b
+#define CSR_MHPMCOUNTER12H 0xb8c
+#define CSR_MHPMCOUNTER13H 0xb8d
+#define CSR_MHPMCOUNTER14H 0xb8e
+#define CSR_MHPMCOUNTER15H 0xb8f
+#define CSR_MHPMCOUNTER16H 0xb90
+#define CSR_MHPMCOUNTER17H 0xb91
+#define CSR_MHPMCOUNTER18H 0xb92
+#define CSR_MHPMCOUNTER19H 0xb93
+#define CSR_MHPMCOUNTER20H 0xb94
+#define CSR_MHPMCOUNTER21H 0xb95
+#define CSR_MHPMCOUNTER22H 0xb96
+#define CSR_MHPMCOUNTER23H 0xb97
+#define CSR_MHPMCOUNTER24H 0xb98
+#define CSR_MHPMCOUNTER25H 0xb99
+#define CSR_MHPMCOUNTER26H 0xb9a
+#define CSR_MHPMCOUNTER27H 0xb9b
+#define CSR_MHPMCOUNTER28H 0xb9c
+#define CSR_MHPMCOUNTER29H 0xb9d
+#define CSR_MHPMCOUNTER30H 0xb9e
+#define CSR_MHPMCOUNTER31H 0xb9f
+#define CAUSE_MISALIGNED_FETCH 0x0
+#define CAUSE_FAULT_FETCH 0x1
+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
+#define CAUSE_BREAKPOINT 0x3
+#define CAUSE_MISALIGNED_LOAD 0x4
+#define CAUSE_FAULT_LOAD 0x5
+#define CAUSE_MISALIGNED_STORE 0x6
+#define CAUSE_FAULT_STORE 0x7
+#define CAUSE_USER_ECALL 0x8
+#define CAUSE_SUPERVISOR_ECALL 0x9
+#define CAUSE_HYPERVISOR_ECALL 0xa
+#define CAUSE_MACHINE_ECALL 0xb
+#endif
+#ifdef DECLARE_INSN
+DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
+DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
+DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
+DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
+DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
+DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
+DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
+DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
+DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
+DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
+DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
+DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
+DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
+DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
+DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
+DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
+DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
+DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
+DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
+DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
+DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
+DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
+DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
+DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
+DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
+DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
+DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
+DECLARE_INSN(or, MATCH_OR, MASK_OR)
+DECLARE_INSN(and, MATCH_AND, MASK_AND)
+DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
+DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
+DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
+DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
+DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
+DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
+DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
+DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
+DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
+DECLARE_INSN(lb, MATCH_LB, MASK_LB)
+DECLARE_INSN(lh, MATCH_LH, MASK_LH)
+DECLARE_INSN(lw, MATCH_LW, MASK_LW)
+DECLARE_INSN(ld, MATCH_LD, MASK_LD)
+DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
+DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
+DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
+DECLARE_INSN(sb, MATCH_SB, MASK_SB)
+DECLARE_INSN(sh, MATCH_SH, MASK_SH)
+DECLARE_INSN(sw, MATCH_SW, MASK_SW)
+DECLARE_INSN(sd, MATCH_SD, MASK_SD)
+DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
+DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
+DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
+DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
+DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
+DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
+DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
+DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
+DECLARE_INSN(rem, MATCH_REM, MASK_REM)
+DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
+DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
+DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
+DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
+DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
+DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
+DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
+DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
+DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
+DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
+DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
+DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
+DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
+DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
+DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
+DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
+DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
+DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
+DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
+DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
+DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
+DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
+DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
+DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
+DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
+DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
+DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
+DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
+DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
+DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
+DECLARE_INSN(uret, MATCH_URET, MASK_URET)
+DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
+DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
+DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
+DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
+DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
+DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
+DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
+DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
+DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
+DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
+DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
+DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
+DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
+DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
+DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
+DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
+DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
+DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
+DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
+DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
+DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
+DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
+DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
+DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
+DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
+DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
+DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
+DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
+DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
+DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
+DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
+DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
+DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
+DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
+DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
+DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
+DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
+DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
+DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
+DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
+DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
+DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
+DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
+DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
+DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
+DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
+DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
+DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
+DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
+DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
+DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
+DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
+DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
+DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
+DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
+DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
+DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
+DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
+DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
+DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
+DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
+DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
+DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
+DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
+DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
+DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
+DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
+DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
+DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
+DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
+DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
+DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
+DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
+DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
+DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
+DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
+DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
+DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
+DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
+DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
+DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
+DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
+DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
+DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
+DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
+DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
+DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
+DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
+DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
+DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
+DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
+DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
+DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
+DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
+DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
+DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
+DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
+DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
+DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
+DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
+DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
+DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
+DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
+DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
+DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
+DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
+DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
+DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
+DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
+DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
+DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
+DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
+DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
+DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
+DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
+DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
+DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
+DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
+DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
+DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
+DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
+DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
+DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
+DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
+DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
+DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
+DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
+DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
+DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
+DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
+DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
+DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
+DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
+DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
+DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
+DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
+DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
+DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
+DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
+#endif
+#ifdef DECLARE_CSR
+DECLARE_CSR(fflags, CSR_FFLAGS)
+DECLARE_CSR(frm, CSR_FRM)
+DECLARE_CSR(fcsr, CSR_FCSR)
+DECLARE_CSR(cycle, CSR_CYCLE)
+DECLARE_CSR(time, CSR_TIME)
+DECLARE_CSR(instret, CSR_INSTRET)
+DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
+DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
+DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
+DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
+DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
+DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
+DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
+DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
+DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
+DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
+DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
+DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
+DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
+DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
+DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
+DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
+DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
+DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
+DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
+DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
+DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
+DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
+DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
+DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
+DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
+DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
+DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
+DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
+DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
+DECLARE_CSR(sstatus, CSR_SSTATUS)
+DECLARE_CSR(sie, CSR_SIE)
+DECLARE_CSR(stvec, CSR_STVEC)
+DECLARE_CSR(sscratch, CSR_SSCRATCH)
+DECLARE_CSR(sepc, CSR_SEPC)
+DECLARE_CSR(scause, CSR_SCAUSE)
+DECLARE_CSR(sbadaddr, CSR_SBADADDR)
+DECLARE_CSR(sip, CSR_SIP)
+DECLARE_CSR(sptbr, CSR_SPTBR)
+DECLARE_CSR(mstatus, CSR_MSTATUS)
+DECLARE_CSR(misa, CSR_MISA)
+DECLARE_CSR(medeleg, CSR_MEDELEG)
+DECLARE_CSR(mideleg, CSR_MIDELEG)
+DECLARE_CSR(mie, CSR_MIE)
+DECLARE_CSR(mtvec, CSR_MTVEC)
+DECLARE_CSR(mscratch, CSR_MSCRATCH)
+DECLARE_CSR(mepc, CSR_MEPC)
+DECLARE_CSR(mcause, CSR_MCAUSE)
+DECLARE_CSR(mbadaddr, CSR_MBADADDR)
+DECLARE_CSR(mip, CSR_MIP)
+DECLARE_CSR(tselect, CSR_TSELECT)
+DECLARE_CSR(tdata1, CSR_TDATA1)
+DECLARE_CSR(tdata2, CSR_TDATA2)
+DECLARE_CSR(tdata3, CSR_TDATA3)
+DECLARE_CSR(dcsr, CSR_DCSR)
+DECLARE_CSR(dpc, CSR_DPC)
+DECLARE_CSR(dscratch, CSR_DSCRATCH)
+DECLARE_CSR(mcycle, CSR_MCYCLE)
+DECLARE_CSR(minstret, CSR_MINSTRET)
+DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
+DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
+DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
+DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
+DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
+DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
+DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
+DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
+DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
+DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
+DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
+DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
+DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
+DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
+DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
+DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
+DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
+DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
+DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
+DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
+DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
+DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
+DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
+DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
+DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
+DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
+DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
+DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
+DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
+DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
+DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
+DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
+DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
+DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
+DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
+DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
+DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
+DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
+DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
+DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
+DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
+DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
+DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
+DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
+DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
+DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
+DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
+DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
+DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
+DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
+DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
+DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
+DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
+DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
+DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
+DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
+DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
+DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
+DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
+DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
+DECLARE_CSR(mvendorid, CSR_MVENDORID)
+DECLARE_CSR(marchid, CSR_MARCHID)
+DECLARE_CSR(mimpid, CSR_MIMPID)
+DECLARE_CSR(mhartid, CSR_MHARTID)
+DECLARE_CSR(cycleh, CSR_CYCLEH)
+DECLARE_CSR(timeh, CSR_TIMEH)
+DECLARE_CSR(instreth, CSR_INSTRETH)
+DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
+DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
+DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
+DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
+DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
+DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
+DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
+DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
+DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
+DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
+DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
+DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
+DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
+DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
+DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
+DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
+DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
+DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
+DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
+DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
+DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
+DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
+DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
+DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
+DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
+DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
+DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
+DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
+DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
+DECLARE_CSR(mcycleh, CSR_MCYCLEH)
+DECLARE_CSR(minstreth, CSR_MINSTRETH)
+DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
+DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
+DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
+DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
+DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
+DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
+DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
+DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
+DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
+DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
+DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
+DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
+DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
+DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
+DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
+DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
+DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
+DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
+DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
+DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
+DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
+DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
+DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
+DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
+DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
+DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
+DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
+DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
+DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
+#endif
+#ifdef DECLARE_CAUSE
+DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
+DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
+DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
+DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
+DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
+DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)
+DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
+DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)
+DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
+DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
+DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
+DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
+#endif
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/entry.S b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/entry.S
new file mode 100644
index 0000000..ce44f48
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/entry.S
@@ -0,0 +1,98 @@
+// See LICENSE for license details
+
+#ifndef ENTRY_S
+#define ENTRY_S
+
+#include "encoding.h"
+#include "sifive/bits.h"
+
+  .section      .text.entry	
+  .align 2
+  .weak trap_entry
+  .global trap_entry
+trap_entry:
+  addi sp, sp, -32*REGBYTES
+
+  STORE x1, 1*REGBYTES(sp)
+  STORE x2, 2*REGBYTES(sp)
+  STORE x3, 3*REGBYTES(sp)
+  STORE x4, 4*REGBYTES(sp)
+  STORE x5, 5*REGBYTES(sp)
+  STORE x6, 6*REGBYTES(sp)
+  STORE x7, 7*REGBYTES(sp)
+  STORE x8, 8*REGBYTES(sp)
+  STORE x9, 9*REGBYTES(sp)
+  STORE x10, 10*REGBYTES(sp)
+  STORE x11, 11*REGBYTES(sp)
+  STORE x12, 12*REGBYTES(sp)
+  STORE x13, 13*REGBYTES(sp)
+  STORE x14, 14*REGBYTES(sp)
+  STORE x15, 15*REGBYTES(sp)
+  STORE x16, 16*REGBYTES(sp)
+  STORE x17, 17*REGBYTES(sp)
+  STORE x18, 18*REGBYTES(sp)
+  STORE x19, 19*REGBYTES(sp)
+  STORE x20, 20*REGBYTES(sp)
+  STORE x21, 21*REGBYTES(sp)
+  STORE x22, 22*REGBYTES(sp)
+  STORE x23, 23*REGBYTES(sp)
+  STORE x24, 24*REGBYTES(sp)
+  STORE x25, 25*REGBYTES(sp)
+  STORE x26, 26*REGBYTES(sp)
+  STORE x27, 27*REGBYTES(sp)
+  STORE x28, 28*REGBYTES(sp)
+  STORE x29, 29*REGBYTES(sp)
+  STORE x30, 30*REGBYTES(sp)
+  STORE x31, 31*REGBYTES(sp)
+
+  csrr a0, mcause
+  csrr a1, mepc
+  mv a2, sp
+  call handle_trap
+  csrw mepc, a0
+
+  # Remain in M-mode after mret
+  li t0, MSTATUS_MPP
+  csrs mstatus, t0
+
+  LOAD x1, 1*REGBYTES(sp)
+  LOAD x2, 2*REGBYTES(sp)
+  LOAD x3, 3*REGBYTES(sp)
+  LOAD x4, 4*REGBYTES(sp)
+  LOAD x5, 5*REGBYTES(sp)
+  LOAD x6, 6*REGBYTES(sp)
+  LOAD x7, 7*REGBYTES(sp)
+  LOAD x8, 8*REGBYTES(sp)
+  LOAD x9, 9*REGBYTES(sp)
+  LOAD x10, 10*REGBYTES(sp)
+  LOAD x11, 11*REGBYTES(sp)
+  LOAD x12, 12*REGBYTES(sp)
+  LOAD x13, 13*REGBYTES(sp)
+  LOAD x14, 14*REGBYTES(sp)
+  LOAD x15, 15*REGBYTES(sp)
+  LOAD x16, 16*REGBYTES(sp)
+  LOAD x17, 17*REGBYTES(sp)
+  LOAD x18, 18*REGBYTES(sp)
+  LOAD x19, 19*REGBYTES(sp)
+  LOAD x20, 20*REGBYTES(sp)
+  LOAD x21, 21*REGBYTES(sp)
+  LOAD x22, 22*REGBYTES(sp)
+  LOAD x23, 23*REGBYTES(sp)
+  LOAD x24, 24*REGBYTES(sp)
+  LOAD x25, 25*REGBYTES(sp)
+  LOAD x26, 26*REGBYTES(sp)
+  LOAD x27, 27*REGBYTES(sp)
+  LOAD x28, 28*REGBYTES(sp)
+  LOAD x29, 29*REGBYTES(sp)
+  LOAD x30, 30*REGBYTES(sp)
+  LOAD x31, 31*REGBYTES(sp)
+
+  addi sp, sp, 32*REGBYTES
+  mret
+
+.weak handle_trap
+handle_trap:
+1:
+  j 1b
+	
+#endif
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/dhrystone.lds b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/dhrystone.lds
new file mode 100644
index 0000000..302bf74
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/dhrystone.lds
@@ -0,0 +1,157 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{
+  flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M
+  ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
+}
+
+PHDRS
+{
+  flash PT_LOAD;
+  ram_init PT_LOAD;
+  ram PT_NULL;
+}
+
+SECTIONS
+{
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
+
+  .init           :
+  {
+    KEEP (*(SORT_NONE(.init)))
+  } >flash AT>flash :flash
+
+  .text           :
+  {
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >flash AT>flash :flash
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >flash AT>flash :flash
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+
+  . = ALIGN(4);
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >flash AT>flash :flash
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >flash AT>flash :flash
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >flash AT>flash :flash
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >flash AT>flash :flash
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >flash AT>flash :flash
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >flash AT>flash :flash
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>flash :ram_init
+
+  .data          :
+  {
+    *(.rdata)
+    *(.rodata .rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+    . = ALIGN(8);
+    PROVIDE( __global_pointer$ = . + 0x800 );
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+    . = ALIGN(8);
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >ram AT>flash :ram_init
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . );
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram :ram
+
+  . = ALIGN(8);
+  PROVIDE( _end = . );
+  PROVIDE( end = . );
+
+  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+  {
+    PROVIDE( _heap_end = . );
+    . = __stack_size;
+    PROVIDE( _sp = . );
+  } >ram AT>ram :ram
+}
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/flash.lds b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/flash.lds
new file mode 100644
index 0000000..0b7e754
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/flash.lds
@@ -0,0 +1,162 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{
+  flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M
+  ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
+}
+
+PHDRS
+{
+  flash PT_LOAD;
+  ram_init PT_LOAD;
+  ram PT_NULL;
+}
+
+SECTIONS
+{
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
+
+  .init           :
+  {
+    KEEP (*(SORT_NONE(.init)))
+  } >flash AT>flash :flash
+
+  .text           :
+  {
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >flash AT>flash :flash
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >flash AT>flash :flash
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+
+  .rodata         :
+  {
+    *(.rdata)
+    *(.rodata .rodata.*)
+    *(.gnu.linkonce.r.*)
+  } >flash AT>flash :flash
+
+  . = ALIGN(4);
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >flash AT>flash :flash
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >flash AT>flash :flash
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >flash AT>flash :flash
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >flash AT>flash :flash
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >flash AT>flash :flash
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >flash AT>flash :flash
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>flash :ram_init
+
+  .data          :
+  {
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+    . = ALIGN(8);
+    PROVIDE( __global_pointer$ = . + 0x800 );
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+    . = ALIGN(8);
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >ram AT>flash :ram_init
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . );
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram :ram
+
+  . = ALIGN(8);
+  PROVIDE( _end = . );
+  PROVIDE( end = . );
+
+  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+  {
+    PROVIDE( _heap_end = . );
+    . = __stack_size;
+    PROVIDE( _sp = . );
+    __freertos_irq_stack_top = .;
+  } >ram AT>ram :ram
+}
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/init.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/init.c
new file mode 100644
index 0000000..a0800e8
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/init.c
@@ -0,0 +1,238 @@
+#include 
+#include 
+#include 
+
+#include "platform.h"
+#include "encoding.h"
+
+extern int main(int argc, char** argv);
+extern void trap_entry();
+
+static unsigned long mtime_lo(void)
+{
+  return *(volatile unsigned long *)(CLINT_CTRL_ADDR + CLINT_MTIME);
+}
+
+#ifdef __riscv32
+
+static uint32_t mtime_hi(void)
+{
+  return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4);
+}
+
+uint64_t get_timer_value()
+{
+  while (1) {
+    uint32_t hi = mtime_hi();
+    uint32_t lo = mtime_lo();
+    if (hi == mtime_hi())
+      return ((uint64_t)hi << 32) | lo;
+  }
+}
+
+#else /* __riscv32 */
+
+uint64_t get_timer_value()
+{
+  return mtime_lo();
+}
+
+#endif
+
+unsigned long get_timer_freq()
+{
+  return 32768;
+}
+
+static void use_hfrosc(int div, int trim)
+{
+  // Make sure the HFROSC is running at its default setting
+  PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1));
+  while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ;
+  PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1);
+}
+
+static void use_pll(int refsel, int bypass, int r, int f, int q)
+{
+  // Ensure that we aren't running off the PLL before we mess with it.
+  if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {
+    // Make sure the HFROSC is running at its default setting
+    use_hfrosc(4, 16);
+  }
+
+  // Set PLL Source to be HFXOSC if available.
+  uint32_t config_value = 0;
+
+  config_value |= PLL_REFSEL(refsel);
+
+  if (bypass) {
+    // Bypass
+    config_value |= PLL_BYPASS(1);
+
+    PRCI_REG(PRCI_PLLCFG) = config_value;
+
+    // If we don't have an HFXTAL, this doesn't really matter.
+    // Set our Final output divide to divide-by-1:
+    PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
+  } else {
+    // In case we are executing from QSPI,
+    // (which is quite likely) we need to
+    // set the QSPI clock divider appropriately
+    // before boosting the clock frequency.
+
+    // Div = f_sck/2
+    SPI0_REG(SPI_REG_SCKDIV) = 8;
+
+    // Set DIV Settings for PLL
+    // Both HFROSC and HFXOSC are modeled as ideal
+    // 16MHz sources (assuming dividers are set properly for
+    // HFROSC).
+    // (Legal values of f_REF are 6-48MHz)
+
+    // Set DIVR to divide-by-2 to get 8MHz frequency
+    // (legal values of f_R are 6-12 MHz)
+
+    config_value |= PLL_BYPASS(1);
+    config_value |= PLL_R(r);
+
+    // Set DIVF to get 512Mhz frequncy
+    // There is an implied multiply-by-2, 16Mhz.
+    // So need to write 32-1
+    // (legal values of f_F are 384-768 MHz)
+    config_value |= PLL_F(f);
+
+    // Set DIVQ to divide-by-2 to get 256 MHz frequency
+    // (legal values of f_Q are 50-400Mhz)
+    config_value |= PLL_Q(q);
+
+    // Set our Final output divide to divide-by-1:
+    PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
+
+    PRCI_REG(PRCI_PLLCFG) = config_value;
+
+    // Un-Bypass the PLL.
+    PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
+
+    // Wait for PLL Lock
+    // Note that the Lock signal can be glitchy.
+    // Need to wait 100 us
+    // RTC is running at 32kHz.
+    // So wait 4 ticks of RTC.
+    uint32_t now = mtime_lo();
+    while (mtime_lo() - now < 4) ;
+
+    // Now it is safe to check for PLL Lock
+    while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ;
+  }
+
+  // Switch over to PLL Clock source
+  PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);
+}
+
+static void use_default_clocks()
+{
+  // Turn off the LFROSC
+  AON_REG(AON_LFROSC) &= ~ROSC_EN(1);
+
+  // Use HFROSC
+  use_hfrosc(4, 16);
+}
+
+static unsigned long __attribute__((noinline)) measure_cpu_freq(size_t n)
+{
+  unsigned long start_mtime, delta_mtime;
+  unsigned long mtime_freq = get_timer_freq();
+
+  // Don't start measuruing until we see an mtime tick
+  unsigned long tmp = mtime_lo();
+  do {
+    start_mtime = mtime_lo();
+  } while (start_mtime == tmp);
+
+  unsigned long start_mcycle = read_csr(mcycle);
+
+  do {
+    delta_mtime = mtime_lo() - start_mtime;
+  } while (delta_mtime < n);
+
+  unsigned long delta_mcycle = read_csr(mcycle) - start_mcycle;
+
+  return (delta_mcycle / delta_mtime) * mtime_freq
+         + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime;
+}
+
+unsigned long get_cpu_freq()
+{
+  static uint32_t cpu_freq;
+
+  if (!cpu_freq) {
+    // warm up I$
+    measure_cpu_freq(1);
+    // measure for real
+    cpu_freq = measure_cpu_freq(10);
+  }
+
+  return cpu_freq;
+}
+
+static void uart_init(size_t baud_rate)
+{
+  GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
+  GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
+  UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1;
+  UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
+}
+
+
+
+#ifdef USE_PLIC
+extern void handle_m_ext_interrupt();
+#endif
+
+#ifdef USE_M_TIME
+extern void handle_m_time_interrupt();
+#endif
+
+uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
+{
+  if (0){
+#ifdef USE_PLIC
+    // External Machine-Level interrupt from PLIC
+  } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
+    handle_m_ext_interrupt();
+#endif
+#ifdef USE_M_TIME
+    // External Machine-Level interrupt from PLIC
+  } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
+    handle_m_time_interrupt();
+#endif
+  }
+  else {
+    write(1, "trap\n", 5);
+    _exit(1 + mcause);
+  }
+  return epc;
+}
+
+void _init()
+{
+  
+  #ifndef NO_INIT
+  use_default_clocks();
+  use_pll(0, 0, 1, 31, 1);
+  uart_init(115200);
+
+  printf("core freq at %d Hz\n", (int)get_cpu_freq());
+
+  write_csr(mtvec, &trap_entry);
+  if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
+    write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
+    write_csr(fcsr, 0); // initialize rounding mode, undefined at reset
+  }
+  #endif
+  
+}
+
+void _fini()
+{
+}
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/openocd.cfg b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/openocd.cfg
new file mode 100644
index 0000000..08b7611
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/openocd.cfg
@@ -0,0 +1,34 @@
+adapter_khz     10000
+
+interface ftdi
+ftdi_device_desc "Dual RS232-HS"
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0008 0x001b
+ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
+
+#Reset Stretcher logic on FE310 is ~1 second long
+#This doesn't apply if you use
+# ftdi_set_signal, but still good to document
+#adapter_nsrst_delay 1500
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
+init
+#reset -- This type of reset is not implemented yet
+if {[ info exists pulse_srst]} {
+  ftdi_set_signal nSRST 0
+  ftdi_set_signal nSRST z
+  #Wait for the reset stretcher
+  #It will work without this, but
+  #will incur lots of delays for later commands.
+  sleep 1500
+}	
+halt
+#flash protect 0 64 last off
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/platform.h b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/platform.h
new file mode 100644
index 0000000..75d31e0
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/freedom-e300-hifive1/platform.h
@@ -0,0 +1,133 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_PLATFORM_H
+#define _SIFIVE_PLATFORM_H
+
+// Some things missing from the official encoding.h
+#define MCAUSE_INT         0x80000000
+#define MCAUSE_CAUSE       0x7FFFFFFF
+
+#include "sifive/const.h"
+#include "sifive/devices/aon.h"
+#include "sifive/devices/clint.h"
+#include "sifive/devices/gpio.h"
+#include "sifive/devices/otp.h"
+#include "sifive/devices/plic.h"
+#include "sifive/devices/prci.h"
+#include "sifive/devices/pwm.h"
+#include "sifive/devices/spi.h"
+#include "sifive/devices/uart.h"
+
+/****************************************************************************
+ * Platform definitions
+ *****************************************************************************/
+
+// Memory map
+#define MASKROM_MEM_ADDR _AC(0x00001000,UL)
+#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
+#define OTP_MEM_ADDR _AC(0x00020000,UL)
+#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
+#define PLIC_CTRL_ADDR _AC(0x0C000000,UL)
+#define AON_CTRL_ADDR _AC(0x10000000,UL)
+#define PRCI_CTRL_ADDR _AC(0x10008000,UL)
+#define OTP_CTRL_ADDR _AC(0x10010000,UL)
+#define GPIO_CTRL_ADDR _AC(0x10012000,UL)
+#define UART0_CTRL_ADDR _AC(0x10013000,UL)
+#define SPI0_CTRL_ADDR _AC(0x10014000,UL)
+#define PWM0_CTRL_ADDR _AC(0x10015000,UL)
+#define UART1_CTRL_ADDR _AC(0x10023000,UL)
+#define SPI1_CTRL_ADDR _AC(0x10024000,UL)
+#define PWM1_CTRL_ADDR _AC(0x10025000,UL)
+#define SPI2_CTRL_ADDR _AC(0x10034000,UL)
+#define PWM2_CTRL_ADDR _AC(0x10035000,UL)
+#define SPI0_MEM_ADDR _AC(0x20000000,UL)
+#define MEM_CTRL_ADDR _AC(0x80000000,UL)
+
+// IOF masks
+#define IOF0_SPI1_MASK          _AC(0x000007FC,UL)
+#define SPI11_NUM_SS     (4)
+#define IOF_SPI1_SS0          (2u)
+#define IOF_SPI1_SS1          (8u)
+#define IOF_SPI1_SS2          (9u)
+#define IOF_SPI1_SS3          (10u)
+#define IOF_SPI1_MOSI         (3u)
+#define IOF_SPI1_MISO         (4u)
+#define IOF_SPI1_SCK          (5u)
+#define IOF_SPI1_DQ0          (3u)
+#define IOF_SPI1_DQ1          (4u)
+#define IOF_SPI1_DQ2          (6u)
+#define IOF_SPI1_DQ3          (7u)
+
+#define IOF0_SPI2_MASK          _AC(0xFC000000,UL)
+#define SPI2_NUM_SS       (1)
+#define IOF_SPI2_SS0          (26u)
+#define IOF_SPI2_MOSI         (27u)
+#define IOF_SPI2_MISO         (28u)
+#define IOF_SPI2_SCK          (29u)
+#define IOF_SPI2_DQ0          (27u)
+#define IOF_SPI2_DQ1          (28u)
+#define IOF_SPI2_DQ2          (30u)
+#define IOF_SPI2_DQ3          (31u)
+
+//#define IOF0_I2C_MASK          _AC(0x00003000,UL)
+
+#define IOF0_UART0_MASK         _AC(0x00030000, UL)
+#define IOF_UART0_RX   (16u)
+#define IOF_UART0_TX   (17u)
+
+#define IOF0_UART1_MASK         _AC(0x03000000, UL)
+#define IOF_UART1_RX (24u)
+#define IOF_UART1_TX (25u)
+
+#define IOF1_PWM0_MASK          _AC(0x0000000F, UL)
+#define IOF1_PWM1_MASK          _AC(0x00780000, UL)
+#define IOF1_PWM2_MASK          _AC(0x00003C00, UL)
+
+// Interrupt numbers
+#define INT_RESERVED 0
+#define INT_WDOGCMP 1
+#define INT_RTCCMP 2
+#define INT_UART0_BASE 3
+#define INT_UART1_BASE 4
+#define INT_SPI0_BASE 5
+#define INT_SPI1_BASE 6
+#define INT_SPI2_BASE 7
+#define INT_GPIO_BASE 8
+#define INT_PWM0_BASE 40
+#define INT_PWM1_BASE 44
+#define INT_PWM2_BASE 48
+
+// Helper functions
+#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
+#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
+#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset)
+#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
+#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
+#define OTP_REG(offset)  _REG32(OTP_CTRL_ADDR, offset)
+#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
+#define PRCI_REG(offset) _REG32(PRCI_CTRL_ADDR, offset)
+#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
+#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset)
+#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset)
+#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
+#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset)
+#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset)
+#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
+#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset)
+
+// Misc
+
+#include 
+
+#define NUM_GPIO 32
+
+#define PLIC_NUM_INTERRUPTS 52
+#define PLIC_NUM_PRIORITIES 7
+
+#include "hifive1.h"
+
+unsigned long get_cpu_freq(void);
+unsigned long get_timer_freq(void);
+uint64_t get_timer_value(void);
+
+#endif /* _SIFIVE_PLATFORM_H */
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/hifive1.h b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/hifive1.h
new file mode 100644
index 0000000..d8fa4c9
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/hifive1.h
@@ -0,0 +1,81 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_HIFIVE1_H
+#define _SIFIVE_HIFIVE1_H
+
+#include 
+
+/****************************************************************************
+ * GPIO Connections
+ *****************************************************************************/
+
+// These are the GPIO bit offsets for the RGB LED on HiFive1 Board.
+// These are also mapped to RGB LEDs on the Freedom E300 Arty
+// FPGA
+// Dev Kit.
+
+#define RED_LED_OFFSET   22
+#define GREEN_LED_OFFSET 19
+#define BLUE_LED_OFFSET  21
+
+// These are the GPIO bit offsets for the differen digital pins
+// on the headers for both the HiFive1 Board and the Freedom E300 Arty FPGA Dev Kit.
+#define PIN_0_OFFSET 16
+#define PIN_1_OFFSET 17
+#define PIN_2_OFFSET 18
+#define PIN_3_OFFSET 19
+#define PIN_4_OFFSET 20
+#define PIN_5_OFFSET 21
+#define PIN_6_OFFSET 22
+#define PIN_7_OFFSET 23
+#define PIN_8_OFFSET 0
+#define PIN_9_OFFSET 1
+#define PIN_10_OFFSET 2
+#define PIN_11_OFFSET 3
+#define PIN_12_OFFSET 4
+#define PIN_13_OFFSET 5
+//#define PIN_14_OFFSET 8 //This pin is not connected on either board.
+#define PIN_15_OFFSET 9
+#define PIN_16_OFFSET 10
+#define PIN_17_OFFSET 11
+#define PIN_18_OFFSET 12
+#define PIN_19_OFFSET 13
+
+// These are *PIN* numbers, not
+// GPIO Offset Numbers.
+#define PIN_SPI1_SCK    (13u)
+#define PIN_SPI1_MISO   (12u)
+#define PIN_SPI1_MOSI   (11u)
+#define PIN_SPI1_SS0    (10u)
+#define PIN_SPI1_SS1    (14u) 
+#define PIN_SPI1_SS2    (15u)
+#define PIN_SPI1_SS3    (16u)
+
+#define SS_PIN_TO_CS_ID(x) \
+  ((x==PIN_SPI1_SS0 ? 0 :		 \
+    (x==PIN_SPI1_SS1 ? 1 :		 \
+     (x==PIN_SPI1_SS2 ? 2 :		 \
+      (x==PIN_SPI1_SS3 ? 3 :		 \
+       -1))))) 
+
+
+// These buttons are present only on the Freedom E300 Arty Dev Kit.
+#ifdef HAS_BOARD_BUTTONS
+#define BUTTON_0_OFFSET 15
+#define BUTTON_1_OFFSET 30
+#define BUTTON_2_OFFSET 31
+
+#define INT_DEVICE_BUTTON_0 (INT_GPIO_BASE + BUTTON_0_OFFSET)
+#define INT_DEVICE_BUTTON_1 (INT_GPIO_BASE + BUTTON_1_OFFSET)
+#define INT_DEVICE_BUTTON_2 (INT_GPIO_BASE + BUTTON_2_OFFSET)
+
+#endif
+
+#define HAS_HFXOSC 1
+#define HAS_LFROSC_BYPASS 1
+
+#define RTC_FREQ 32768
+
+void write_hex(int fd, unsigned long int hex);
+
+#endif /* _SIFIVE_HIFIVE1_H */
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/start.S b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/start.S
new file mode 100644
index 0000000..ac24d51
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/env/start.S
@@ -0,0 +1,110 @@
+// See LICENSE for license details.
+
+/* This is defined in sifive/platform.h, but that can't be included from
+ * assembly. */
+#define CLINT_CTRL_ADDR 0x02000000
+
+	.section .init
+	.globl _start
+	.type _start,@function
+
+_start:
+	.cfi_startproc
+	.cfi_undefined ra
+.option push
+.option norelax
+	la gp, __global_pointer$
+.option pop
+	la sp, _sp
+
+#if defined(ENABLE_SMP)
+	smp_pause(t0, t1)
+#endif
+
+	/* Load data section */
+	la a0, _data_lma
+	la a1, _data
+	la a2, _edata
+	bgeu a1, a2, 2f
+1:
+	lw t0, (a0)
+	sw t0, (a1)
+	addi a0, a0, 4
+	addi a1, a1, 4
+	bltu a1, a2, 1b
+2:
+
+	/* Clear bss section */
+	la a0, __bss_start
+	la a1, _end
+	bgeu a0, a1, 2f
+1:
+	sw zero, (a0)
+	addi a0, a0, 4
+	bltu a0, a1, 1b
+2:
+
+	/* Call global constructors */
+	la a0, __libc_fini_array
+	call atexit
+	call __libc_init_array
+
+#ifndef __riscv_float_abi_soft
+	/* Enable FPU */
+	li t0, MSTATUS_FS
+	csrs mstatus, t0
+	csrr t1, mstatus
+	and t1, t1, t0
+	beqz t1, 1f
+	fssr x0
+1:
+#endif
+
+#if defined(ENABLE_SMP)
+	smp_resume(t0, t1)
+
+	csrr a0, mhartid
+	bnez a0, 2f
+#endif
+
+	auipc ra, 0
+	addi sp, sp, -16
+#if __riscv_xlen == 32
+	sw ra, 8(sp)
+#else
+	sd ra, 8(sp)
+#endif
+
+	/* argc = argv = 0 */
+	li a0, 0
+	li a1, 0
+	call main
+	tail exit
+1:
+	j 1b
+
+#if defined(ENABLE_SMP)
+2:
+	la t0, trap_entry
+	csrw mtvec, t0
+
+	csrr a0, mhartid
+	la t1, _sp
+	slli t0, a0, 10
+	sub sp, t1, t0
+
+	auipc ra, 0
+	addi sp, sp, -16
+#if __riscv_xlen == 32
+	sw ra, 8(sp)
+#else
+	sd ra, 8(sp)
+#endif
+
+	call secondary_main
+	tail exit
+
+1:
+	j 1b
+#endif
+	.cfi_endproc
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/bits.h b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/bits.h
new file mode 100644
index 0000000..54ea8a4
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/bits.h
@@ -0,0 +1,36 @@
+// See LICENSE for license details.
+#ifndef _RISCV_BITS_H
+#define _RISCV_BITS_H
+
+#define likely(x) __builtin_expect((x), 1)
+#define unlikely(x) __builtin_expect((x), 0)
+
+#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b))
+#define ROUNDDOWN(a, b) ((a)/(b)*(b))
+
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
+
+#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
+#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
+
+#define STR(x) XSTR(x)
+#define XSTR(x) #x
+
+#if __riscv_xlen == 64
+# define SLL32    sllw
+# define STORE    sd
+# define LOAD     ld
+# define LWU      lwu
+# define LOG_REGBYTES 3
+#else
+# define SLL32    sll
+# define STORE    sw
+# define LOAD     lw
+# define LWU      lw
+# define LOG_REGBYTES 2
+#endif
+#define REGBYTES (1 << LOG_REGBYTES)
+
+#endif
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/const.h b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/const.h
new file mode 100644
index 0000000..fdd6fca
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/const.h
@@ -0,0 +1,18 @@
+// See LICENSE for license details.
+/* Derived from  */
+
+#ifndef _SIFIVE_CONST_H
+#define _SIFIVE_CONST_H
+
+#ifdef __ASSEMBLER__
+#define _AC(X,Y)        X
+#define _AT(T,X)        X
+#else
+#define _AC(X,Y)        (X##Y)
+#define _AT(T,X)        ((T)(X))
+#endif /* !__ASSEMBLER__*/
+
+#define _BITUL(x)       (_AC(1,UL) << (x))
+#define _BITULL(x)      (_AC(1,ULL) << (x))
+
+#endif /* _SIFIVE_CONST_H */
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/aon.h b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/aon.h
new file mode 100644
index 0000000..7841537
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/aon.h
@@ -0,0 +1,88 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_AON_H
+#define _SIFIVE_AON_H
+
+/* Register offsets */
+
+#define AON_WDOGCFG     0x000
+#define AON_WDOGCOUNT   0x008
+#define AON_WDOGS       0x010
+#define AON_WDOGFEED    0x018
+#define AON_WDOGKEY     0x01C
+#define AON_WDOGCMP     0x020
+
+#define AON_RTCCFG      0x040
+#define AON_RTCLO       0x048
+#define AON_RTCHI       0x04C
+#define AON_RTCS        0x050
+#define AON_RTCCMP      0x060
+
+#define AON_BACKUP0     0x080
+#define AON_BACKUP1     0x084
+#define AON_BACKUP2     0x088
+#define AON_BACKUP3     0x08C
+#define AON_BACKUP4     0x090
+#define AON_BACKUP5     0x094
+#define AON_BACKUP6     0x098
+#define AON_BACKUP7     0x09C
+#define AON_BACKUP8     0x0A0
+#define AON_BACKUP9     0x0A4
+#define AON_BACKUP10    0x0A8
+#define AON_BACKUP11    0x0AC
+#define AON_BACKUP12    0x0B0
+#define AON_BACKUP13    0x0B4
+#define AON_BACKUP14    0x0B8
+#define AON_BACKUP15    0x0BC
+
+#define AON_PMUWAKEUPI0 0x100
+#define AON_PMUWAKEUPI1 0x104
+#define AON_PMUWAKEUPI2 0x108
+#define AON_PMUWAKEUPI3 0x10C
+#define AON_PMUWAKEUPI4 0x110
+#define AON_PMUWAKEUPI5 0x114
+#define AON_PMUWAKEUPI6 0x118
+#define AON_PMUWAKEUPI7 0x11C
+#define AON_PMUSLEEPI0  0x120
+#define AON_PMUSLEEPI1  0x124
+#define AON_PMUSLEEPI2  0x128
+#define AON_PMUSLEEPI3  0x12C
+#define AON_PMUSLEEPI4  0x130
+#define AON_PMUSLEEPI5  0x134
+#define AON_PMUSLEEPI6  0x138
+#define AON_PMUSLEEPI7  0x13C
+#define AON_PMUIE       0x140
+#define AON_PMUCAUSE    0x144
+#define AON_PMUSLEEP    0x148
+#define AON_PMUKEY      0x14C
+
+#define AON_LFROSC      0x070
+/* Constants */
+
+#define AON_WDOGKEY_VALUE  0x51F15E
+#define AON_WDOGFEED_VALUE 0xD09F00D
+
+#define AON_WDOGCFG_SCALE       0x0000000F
+#define AON_WDOGCFG_RSTEN       0x00000100
+#define AON_WDOGCFG_ZEROCMP     0x00000200
+#define AON_WDOGCFG_ENALWAYS    0x00001000
+#define AON_WDOGCFG_ENCOREAWAKE 0x00002000
+#define AON_WDOGCFG_CMPIP       0x10000000
+
+#define AON_RTCCFG_SCALE     0x0000000F
+#define AON_RTCCFG_ENALWAYS  0x00001000
+#define AON_RTCCFG_CMPIP     0x10000000
+
+#define AON_WAKEUPCAUSE_RESET   0x00
+#define AON_WAKEUPCAUSE_RTC     0x01
+#define AON_WAKEUPCAUSE_DWAKEUP 0x02
+#define AON_WAKEUPCAUSE_AWAKEUP 0x03
+
+#define AON_RESETCAUSE_POWERON  0x0000
+#define AON_RESETCAUSE_EXTERNAL 0x0100
+#define AON_RESETCAUSE_WATCHDOG 0x0200
+
+#define AON_PMUCAUSE_WAKEUPCAUSE 0x00FF
+#define AON_PMUCAUSE_RESETCAUSE  0xFF00
+
+#endif /* _SIFIVE_AON_H */
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/clint.h b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/clint.h
new file mode 100644
index 0000000..057ba02
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/clint.h
@@ -0,0 +1,14 @@
+// See LICENSE for license details
+
+#ifndef _SIFIVE_CLINT_H
+#define _SIFIVE_CLINT_H
+
+
+#define CLINT_MSIP 0x0000
+#define CLINT_MSIP_size   0x4
+#define CLINT_MTIMECMP 0x4000
+#define CLINT_MTIMECMP_size 0x8
+#define CLINT_MTIME 0xBFF8
+#define CLINT_MTIME_size 0x8
+
+#endif /* _SIFIVE_CLINT_H */ 
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/gpio.h b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/gpio.h
new file mode 100644
index 0000000..69239de
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/gpio.h
@@ -0,0 +1,24 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_GPIO_H
+#define _SIFIVE_GPIO_H
+
+#define GPIO_INPUT_VAL  (0x00)
+#define GPIO_INPUT_EN   (0x04)
+#define GPIO_OUTPUT_EN  (0x08)
+#define GPIO_OUTPUT_VAL (0x0C)
+#define GPIO_PULLUP_EN  (0x10)
+#define GPIO_DRIVE      (0x14)
+#define GPIO_RISE_IE    (0x18)
+#define GPIO_RISE_IP    (0x1C)
+#define GPIO_FALL_IE    (0x20)
+#define GPIO_FALL_IP    (0x24)
+#define GPIO_HIGH_IE    (0x28)
+#define GPIO_HIGH_IP    (0x2C)
+#define GPIO_LOW_IE     (0x30)
+#define GPIO_LOW_IP     (0x34)
+#define GPIO_IOF_EN     (0x38)
+#define GPIO_IOF_SEL    (0x3C)
+#define GPIO_OUTPUT_XOR    (0x40)
+
+#endif /* _SIFIVE_GPIO_H */
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/otp.h b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/otp.h
new file mode 100644
index 0000000..2482518
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/otp.h
@@ -0,0 +1,23 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_OTP_H
+#define _SIFIVE_OTP_H
+
+/* Register offsets */
+
+#define OTP_LOCK         0x00
+#define OTP_CK           0x04
+#define OTP_OE           0x08
+#define OTP_SEL          0x0C
+#define OTP_WE           0x10
+#define OTP_MR           0x14
+#define OTP_MRR          0x18
+#define OTP_MPP          0x1C
+#define OTP_VRREN        0x20
+#define OTP_VPPEN        0x24
+#define OTP_A            0x28
+#define OTP_D            0x2C
+#define OTP_Q            0x30
+#define OTP_READ_TIMINGS 0x34
+
+#endif
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/plic.h b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/plic.h
new file mode 100644
index 0000000..494e04e
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/plic.h
@@ -0,0 +1,31 @@
+// See LICENSE for license details.
+
+#ifndef PLIC_H
+#define PLIC_H
+
+#include 
+
+// 32 bits per source
+#define PLIC_PRIORITY_OFFSET            _AC(0x0000,UL)
+#define PLIC_PRIORITY_SHIFT_PER_SOURCE  2
+// 1 bit per source (1 address)
+#define PLIC_PENDING_OFFSET             _AC(0x1000,UL)
+#define PLIC_PENDING_SHIFT_PER_SOURCE   0
+
+//0x80 per target
+#define PLIC_ENABLE_OFFSET              _AC(0x2000,UL)
+#define PLIC_ENABLE_SHIFT_PER_TARGET    7
+
+
+#define PLIC_THRESHOLD_OFFSET           _AC(0x200000,UL)
+#define PLIC_CLAIM_OFFSET               _AC(0x200004,UL)
+#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12
+#define PLIC_CLAIM_SHIFT_PER_TARGET     12
+
+#define PLIC_MAX_SOURCE                 1023
+#define PLIC_SOURCE_MASK                0x3FF
+
+#define PLIC_MAX_TARGET                 15871
+#define PLIC_TARGET_MASK                0x3FFF
+
+#endif /* PLIC_H */
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/prci.h b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/prci.h
new file mode 100644
index 0000000..582863c
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/prci.h
@@ -0,0 +1,56 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_PRCI_H
+#define _SIFIVE_PRCI_H
+
+/* Register offsets */
+
+#define PRCI_HFROSCCFG   (0x0000)
+#define PRCI_HFXOSCCFG   (0x0004)
+#define PRCI_PLLCFG      (0x0008)
+#define PRCI_PLLDIV      (0x000C)
+#define PRCI_PROCMONCFG  (0x00F0)
+
+/* Fields */
+#define ROSC_DIV(x)    (((x) & 0x2F) << 0 ) 
+#define ROSC_TRIM(x)   (((x) & 0x1F) << 16)
+#define ROSC_EN(x)     (((x) & 0x1 ) << 30) 
+#define ROSC_RDY(x)    (((x) & 0x1 ) << 31)
+
+#define XOSC_EN(x)     (((x) & 0x1) << 30)
+#define XOSC_RDY(x)    (((x) & 0x1) << 31)
+
+#define PLL_R(x)       (((x) & 0x7)  << 0)
+// single reserved bit for F LSB.
+#define PLL_F(x)       (((x) & 0x3F) << 4)
+#define PLL_Q(x)       (((x) & 0x3)  << 10)
+#define PLL_SEL(x)     (((x) & 0x1)  << 16)
+#define PLL_REFSEL(x)  (((x) & 0x1)  << 17)
+#define PLL_BYPASS(x)  (((x) & 0x1)  << 18)
+#define PLL_LOCK(x)    (((x) & 0x1)  << 31)
+
+#define PLL_R_default 0x1
+#define PLL_F_default 0x1F
+#define PLL_Q_default 0x3
+
+#define PLL_REFSEL_HFROSC 0x0
+#define PLL_REFSEL_HFXOSC 0x1
+
+#define PLL_SEL_HFROSC 0x0
+#define PLL_SEL_PLL    0x1
+
+#define PLL_FINAL_DIV(x)      (((x) & 0x3F) << 0)
+#define PLL_FINAL_DIV_BY_1(x) (((x) & 0x1 ) << 8)
+
+#define PROCMON_DIV(x)   (((x) & 0x1F) << 0)
+#define PROCMON_TRIM(x)  (((x) & 0x1F) << 8)
+#define PROCMON_EN(x)    (((x) & 0x1)  << 16)
+#define PROCMON_SEL(x)   (((x) & 0x3)  << 24)
+#define PROCMON_NT_EN(x) (((x) & 0x1)  << 28)
+
+#define PROCMON_SEL_HFCLK     0
+#define PROCMON_SEL_HFXOSCIN  1
+#define PROCMON_SEL_PLLOUTDIV 2
+#define PROCMON_SEL_PROCMON   3
+
+#endif // _SIFIVE_PRCI_H
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/pwm.h b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/pwm.h
new file mode 100644
index 0000000..3c5f704
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/pwm.h
@@ -0,0 +1,37 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_PWM_H
+#define _SIFIVE_PWM_H
+
+/* Register offsets */
+
+#define PWM_CFG   0x00
+#define PWM_COUNT 0x08
+#define PWM_S     0x10
+#define PWM_CMP0  0x20
+#define PWM_CMP1  0x24
+#define PWM_CMP2  0x28
+#define PWM_CMP3  0x2C
+
+/* Constants */
+
+#define PWM_CFG_SCALE       0x0000000F
+#define PWM_CFG_STICKY      0x00000100
+#define PWM_CFG_ZEROCMP     0x00000200
+#define PWM_CFG_DEGLITCH    0x00000400
+#define PWM_CFG_ENALWAYS    0x00001000
+#define PWM_CFG_ONESHOT     0x00002000
+#define PWM_CFG_CMP0CENTER  0x00010000
+#define PWM_CFG_CMP1CENTER  0x00020000
+#define PWM_CFG_CMP2CENTER  0x00040000
+#define PWM_CFG_CMP3CENTER  0x00080000
+#define PWM_CFG_CMP0GANG    0x01000000
+#define PWM_CFG_CMP1GANG    0x02000000
+#define PWM_CFG_CMP2GANG    0x04000000
+#define PWM_CFG_CMP3GANG    0x08000000
+#define PWM_CFG_CMP0IP      0x10000000
+#define PWM_CFG_CMP1IP      0x20000000
+#define PWM_CFG_CMP2IP      0x40000000
+#define PWM_CFG_CMP3IP      0x80000000
+
+#endif /* _SIFIVE_PWM_H */
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/spi.h b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/spi.h
new file mode 100644
index 0000000..e3c1d35
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/spi.h
@@ -0,0 +1,80 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_SPI_H
+#define _SIFIVE_SPI_H
+
+/* Register offsets */
+
+#define SPI_REG_SCKDIV          0x00
+#define SPI_REG_SCKMODE         0x04
+#define SPI_REG_CSID            0x10
+#define SPI_REG_CSDEF           0x14
+#define SPI_REG_CSMODE          0x18
+
+#define SPI_REG_DCSSCK          0x28
+#define SPI_REG_DSCKCS          0x2a
+#define SPI_REG_DINTERCS        0x2c
+#define SPI_REG_DINTERXFR       0x2e
+
+#define SPI_REG_FMT             0x40
+#define SPI_REG_TXFIFO          0x48
+#define SPI_REG_RXFIFO          0x4c
+#define SPI_REG_TXCTRL          0x50
+#define SPI_REG_RXCTRL          0x54
+
+#define SPI_REG_FCTRL           0x60
+#define SPI_REG_FFMT            0x64
+
+#define SPI_REG_IE              0x70
+#define SPI_REG_IP              0x74
+
+/* Fields */
+
+#define SPI_SCK_PHA             0x1
+#define SPI_SCK_POL             0x2
+
+#define SPI_FMT_PROTO(x)        ((x) & 0x3)
+#define SPI_FMT_ENDIAN(x)       (((x) & 0x1) << 2)
+#define SPI_FMT_DIR(x)          (((x) & 0x1) << 3)
+#define SPI_FMT_LEN(x)          (((x) & 0xf) << 16)
+
+/* TXCTRL register */
+#define SPI_TXWM(x)             ((x) & 0xffff)
+/* RXCTRL register */
+#define SPI_RXWM(x)             ((x) & 0xffff)
+
+#define SPI_IP_TXWM             0x1
+#define SPI_IP_RXWM             0x2
+
+#define SPI_FCTRL_EN            0x1
+
+#define SPI_INSN_CMD_EN         0x1
+#define SPI_INSN_ADDR_LEN(x)    (((x) & 0x7) << 1)
+#define SPI_INSN_PAD_CNT(x)     (((x) & 0xf) << 4)
+#define SPI_INSN_CMD_PROTO(x)   (((x) & 0x3) << 8)
+#define SPI_INSN_ADDR_PROTO(x)  (((x) & 0x3) << 10)
+#define SPI_INSN_DATA_PROTO(x)  (((x) & 0x3) << 12)
+#define SPI_INSN_CMD_CODE(x)    (((x) & 0xff) << 16)
+#define SPI_INSN_PAD_CODE(x)    (((x) & 0xff) << 24)
+
+#define SPI_TXFIFO_FULL  (1 << 31)   
+#define SPI_RXFIFO_EMPTY (1 << 31)   
+
+/* Values */
+
+#define SPI_CSMODE_AUTO         0
+#define SPI_CSMODE_HOLD         2
+#define SPI_CSMODE_OFF          3
+
+#define SPI_DIR_RX              0
+#define SPI_DIR_TX              1
+
+#define SPI_PROTO_S             0
+#define SPI_PROTO_D             1
+#define SPI_PROTO_Q             2
+
+#define SPI_ENDIAN_MSB          0
+#define SPI_ENDIAN_LSB          1
+
+
+#endif /* _SIFIVE_SPI_H */
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/uart.h b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/uart.h
new file mode 100644
index 0000000..ce9fd01
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/devices/uart.h
@@ -0,0 +1,27 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_UART_H
+#define _SIFIVE_UART_H
+
+/* Register offsets */
+#define UART_REG_TXFIFO         0x00
+#define UART_REG_RXFIFO         0x04
+#define UART_REG_TXCTRL         0x08
+#define UART_REG_RXCTRL         0x0c
+#define UART_REG_IE             0x10
+#define UART_REG_IP             0x14
+#define UART_REG_DIV            0x18
+
+/* TXCTRL register */
+#define UART_TXEN               0x1
+#define UART_TXWM(x)            (((x) & 0xffff) << 16)
+
+/* RXCTRL register */
+#define UART_RXEN               0x1
+#define UART_RXWM(x)            (((x) & 0xffff) << 16)
+
+/* IP register */
+#define UART_IP_TXWM            0x1
+#define UART_IP_RXWM            0x2
+
+#endif /* _SIFIVE_UART_H */
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/sections.h b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/sections.h
new file mode 100644
index 0000000..bcbf9f8
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/sections.h
@@ -0,0 +1,17 @@
+// See LICENSE for license details.
+#ifndef _SECTIONS_H
+#define _SECTIONS_H
+
+extern unsigned char _rom[];
+extern unsigned char _rom_end[];
+
+extern unsigned char _ram[];
+extern unsigned char _ram_end[];
+
+extern unsigned char _ftext[];
+extern unsigned char _etext[];
+extern unsigned char _fbss[];
+extern unsigned char _ebss[];
+extern unsigned char _end[];
+
+#endif /* _SECTIONS_H */
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/smp.h b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/smp.h
new file mode 100644
index 0000000..8e7d485
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/include/sifive/smp.h
@@ -0,0 +1,65 @@
+#ifndef SIFIVE_SMP
+#define SIFIVE_SMP
+
+// The maximum number of HARTs this code supports
+#ifndef MAX_HARTS
+#define MAX_HARTS 32
+#endif
+#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4)
+
+// The hart that non-SMP tests should run on
+#ifndef NONSMP_HART
+#define NONSMP_HART 0
+#endif
+
+/* If your test cannot handle multiple-threads, use this: 
+ *   smp_disable(reg1)
+ */
+#define smp_disable(reg1, reg2)			 \
+  csrr reg1, mhartid				;\
+  li   reg2, NONSMP_HART			;\
+  beq  reg1, reg2, hart0_entry			;\
+42:						;\
+  wfi    					;\
+  j 42b						;\
+hart0_entry:
+
+/* If your test needs to temporarily block multiple-threads, do this:
+ *    smp_pause(reg1, reg2)
+ *    ... single-threaded work ...
+ *    smp_resume(reg1, reg2)
+ *    ... multi-threaded work ...
+ */
+
+#define smp_pause(reg1, reg2)	 \
+  li reg2, 0x8			;\
+  csrw mie, reg2		;\
+  csrr reg2, mhartid		;\
+  bnez reg2, 42f
+
+#define smp_resume(reg1, reg2)	 \
+  li reg1, CLINT_CTRL_ADDR	;\
+41:				;\
+  li reg2, 1			;\
+  sw reg2, 0(reg1)		;\
+  addi reg1, reg1, 4		;\
+  li reg2, CLINT_END_HART_IPI	;\
+  blt reg1, reg2, 41b		;\
+42:				;\
+  wfi    			;\
+  csrr reg2, mip		;\
+  andi reg2, reg2, 0x8		;\
+  beqz reg2, 42b		;\
+  li reg1, CLINT_CTRL_ADDR	;\
+  csrr reg2, mhartid		;\
+  slli reg2, reg2, 2		;\
+  add reg2, reg2, reg1		;\
+  sw zero, 0(reg2)		;\
+41:				;\
+  lw reg2, 0(reg1)		;\
+  bnez reg2, 41b		;\
+  addi reg1, reg1, 4		;\
+  li reg2, CLINT_END_HART_IPI	;\
+  blt reg1, reg2, 41b
+
+#endif
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/misc/write_hex.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/misc/write_hex.c
new file mode 100644
index 0000000..4d25241
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/misc/write_hex.c
@@ -0,0 +1,19 @@
+/* See LICENSE of license details. */
+
+#include 
+#include 
+#include "platform.h"
+
+void write_hex(int fd, unsigned long int hex)
+{
+  uint8_t ii;
+  uint8_t jj;
+  char towrite;
+  write(fd , "0x", 2);
+  for (ii = sizeof(unsigned long int) * 2 ; ii > 0; ii--) {
+    jj = ii - 1;
+    uint8_t digit = ((hex & (0xF << (jj*4))) >> (jj*4));
+    towrite = digit < 0xA ? ('0' + digit) : ('A' +  (digit - 0xA));
+    write(fd, &towrite, 1);
+  }
+}
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/stdlib/malloc.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/stdlib/malloc.c
new file mode 100644
index 0000000..871766f
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/stdlib/malloc.c
@@ -0,0 +1,17 @@
+/* See LICENSE for license details. */
+
+/* These functions are intended for embedded RV32 systems and are
+   obviously incorrect in general. */
+
+void* __wrap_malloc(unsigned long sz)
+{
+  extern void* sbrk(long);
+  void* res = sbrk(sz);
+  if ((long)res == -1)
+    return 0;
+  return res;
+}
+
+void __wrap_free(void* ptr)
+{
+}
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/_exit.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/_exit.c
new file mode 100644
index 0000000..89b0b3d
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/_exit.c
@@ -0,0 +1,17 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "platform.h"
+#include "weak_under_alias.h"
+
+void __wrap_exit(int code)
+{
+  const char message[] = "\nProgam has exited with code:";
+
+  write(STDERR_FILENO, message, sizeof(message) - 1);
+  write_hex(STDERR_FILENO, code);
+  write(STDERR_FILENO, "\n", 1);
+
+  for (;;);
+}
+weak_under_alias(exit);
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/close.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/close.c
new file mode 100644
index 0000000..fe2dd77
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/close.c
@@ -0,0 +1,11 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_close(int fd)
+{
+  return _stub(EBADF);
+}
+weak_under_alias(close);
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/execve.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/execve.c
new file mode 100644
index 0000000..508ae21
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/execve.c
@@ -0,0 +1,11 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_execve(const char* name, char* const argv[], char* const env[])
+{
+  return _stub(ENOMEM);
+}
+weak_under_alias(execve);
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/fork.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/fork.c
new file mode 100644
index 0000000..3f05a67
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/fork.c
@@ -0,0 +1,9 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "stub.h"
+
+int fork(void)
+{
+  return _stub(EAGAIN);
+}
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/fstat.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/fstat.c
new file mode 100644
index 0000000..8de6b8c
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/fstat.c
@@ -0,0 +1,18 @@
+/* See LICENSE of license details. */
+
+#include 
+#include 
+#include 
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_fstat(int fd, struct stat* st)
+{
+  if (isatty(fd)) {
+    st->st_mode = S_IFCHR;
+    return 0;
+  }
+
+  return _stub(EBADF);
+}
+weak_under_alias(fstat);
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/getpid.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/getpid.c
new file mode 100644
index 0000000..8b2a7c7
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/getpid.c
@@ -0,0 +1,8 @@
+/* See LICENSE of license details. */
+#include "weak_under_alias.h"
+
+int __wrap_getpid(void)
+{
+  return 1;
+}
+weak_under_alias(getpid);
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/isatty.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/isatty.c
new file mode 100644
index 0000000..d65f932
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/isatty.c
@@ -0,0 +1,13 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "weak_under_alias.h"
+
+int __wrap_isatty(int fd)
+{
+  if (fd == STDOUT_FILENO || fd == STDERR_FILENO)
+    return 1;
+
+  return 0;
+}
+weak_under_alias(isatty);
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/kill.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/kill.c
new file mode 100644
index 0000000..fe1fa62
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/kill.c
@@ -0,0 +1,11 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_kill(int pid, int sig)
+{
+  return _stub(EINVAL);
+}
+weak_under_alias(kill);
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/link.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/link.c
new file mode 100644
index 0000000..eeac5b9
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/link.c
@@ -0,0 +1,11 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_link(const char *old_name, const char *new_name)
+{
+  return _stub(EMLINK);
+}
+weak_under_alias(link);
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/lseek.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/lseek.c
new file mode 100644
index 0000000..81b2b78
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/lseek.c
@@ -0,0 +1,16 @@
+/* See LICENSE of license details. */
+
+#include 
+#include 
+#include 
+#include "stub.h"
+#include "weak_under_alias.h"
+
+off_t __wrap_lseek(int fd, off_t ptr, int dir)
+{
+  if (isatty(fd))
+    return 0;
+
+  return _stub(EBADF);
+}
+weak_under_alias(lseek);
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/open.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/open.c
new file mode 100644
index 0000000..8b74f2a
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/open.c
@@ -0,0 +1,11 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_open(const char* name, int flags, int mode)
+{
+  return _stub(ENOENT);
+}
+weak_under_alias(open);
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/openat.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/openat.c
new file mode 100644
index 0000000..687e0e2
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/openat.c
@@ -0,0 +1,11 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_openat(int dirfd, const char* name, int flags, int mode)
+{
+  return _stub(ENOENT);
+}
+weak_under_alias(openat);
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/puts.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/puts.c
new file mode 100644
index 0000000..45c05c0
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/puts.c
@@ -0,0 +1,28 @@
+/* See LICENSE of license details. */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "platform.h"
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_puts(const char *s)
+{
+  while (*s != '\0') {
+    while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
+    UART0_REG(UART_REG_TXFIFO) = *s;
+
+    if (*s == '\n') {
+      while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
+      UART0_REG(UART_REG_TXFIFO) = '\r';
+    }
+
+    ++s;
+  }
+
+  return 0;
+}
+weak_under_alias(puts);
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/read.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/read.c
new file mode 100644
index 0000000..08d0ab5
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/read.c
@@ -0,0 +1,32 @@
+/* See LICENSE of license details. */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "platform.h"
+#include "stub.h"
+#include "weak_under_alias.h"
+
+ssize_t __wrap_read(int fd, void* ptr, size_t len)
+{
+  uint8_t * current = (uint8_t *)ptr;
+  volatile uint32_t * uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO);
+  volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_CTRL_ADDR + UART_REG_RXCTRL + 2);
+
+  ssize_t result = 0;
+
+  if (isatty(fd)) {
+    for (current = (uint8_t *)ptr;
+        (current < ((uint8_t *)ptr) + len) && (*uart_rx_cnt > 0);
+        current ++) {
+      *current = *uart_rx;
+      result++;
+    }
+    return result;
+  }
+
+  return _stub(EBADF);
+}
+weak_under_alias(read);
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/sbrk.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/sbrk.c
new file mode 100644
index 0000000..451bc27
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/sbrk.c
@@ -0,0 +1,18 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "weak_under_alias.h"
+
+void *__wrap_sbrk(ptrdiff_t incr)
+{
+  extern char _end[];
+  extern char _heap_end[];
+  static char *curbrk = _end;
+
+  if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
+    return NULL - 1;
+
+  curbrk += incr;
+  return curbrk - incr;
+}
+weak_under_alias(sbrk);
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/stat.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/stat.c
new file mode 100644
index 0000000..b950590
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/stat.c
@@ -0,0 +1,12 @@
+/* See LICENSE of license details. */
+
+#include 
+#include 
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_stat(const char* file, struct stat* st)
+{
+  return _stub(EACCES);
+}
+weak_under_alias(stat);
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/stub.h b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/stub.h
new file mode 100644
index 0000000..cebddda
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/stub.h
@@ -0,0 +1,10 @@
+/* See LICENSE of license details. */
+#ifndef _SIFIVE_SYS_STUB_H
+#define _SIFIVE_SYS_STUB_H
+
+static inline int _stub(int err)
+{
+  return -1;
+}
+
+#endif /* _SIFIVE_SYS_STUB_H */
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/times.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/times.c
new file mode 100644
index 0000000..26e1737
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/times.c
@@ -0,0 +1,12 @@
+/* See LICENSE of license details. */
+
+#include 
+#include 
+#include "stub.h"
+#include "weak_under_alias.h"
+
+clock_t __wrap_times(struct tms* buf)
+{
+  return _stub(EACCES);
+}
+weak_under_alias(times);
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/unlink.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/unlink.c
new file mode 100644
index 0000000..8e23464
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/unlink.c
@@ -0,0 +1,11 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "stub.h"
+#include "weak_under_alias.h"
+
+int __wrap_unlink(const char* name)
+{
+  return _stub(ENOENT);
+}
+weak_under_alias(unlink);
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/wait.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/wait.c
new file mode 100644
index 0000000..bb566e6
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/wait.c
@@ -0,0 +1,9 @@
+/* See LICENSE of license details. */
+
+#include 
+#include "stub.h"
+
+int wait(int* status)
+{
+  return _stub(ECHILD);
+}
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/weak_under_alias.h b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/weak_under_alias.h
new file mode 100644
index 0000000..402a223
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/weak_under_alias.h
@@ -0,0 +1,7 @@
+#ifndef _BSP_LIBWRAP_WEAK_UNDER_ALIAS_H
+#define _BSP_LIBWRAP_WEAK_UNDER_ALIAS_H
+
+#define weak_under_alias(name) \
+  extern __typeof (__wrap_##name) __wrap__##name __attribute__ ((weak, alias ("__wrap_"#name)))
+
+#endif
diff --git a/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/write.c b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/write.c
new file mode 100644
index 0000000..c6ec5b4
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/freedom-e-sdk/libwrap/sys/write.c
@@ -0,0 +1,31 @@
+/* See LICENSE of license details. */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "platform.h"
+#include "stub.h"
+#include "weak_under_alias.h"
+
+ssize_t __wrap_write(int fd, const void* ptr, size_t len)
+{
+  const uint8_t * current = (const uint8_t *)ptr;
+
+  if (isatty(fd)) {
+    for (size_t jj = 0; jj < len; jj++) {
+      while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
+      UART0_REG(UART_REG_TXFIFO) = current[jj];
+
+      if (current[jj] == '\n') {
+        while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
+        UART0_REG(UART_REG_TXFIFO) = '\r';
+      }
+    }
+    return len;
+  }
+
+  return _stub(EBADF);
+}
+weak_under_alias(write);
diff --git a/RISC-V-HiFive1_e-FreedomStudio/full_demo/RegTest.S b/RISC-V-HiFive1_e-FreedomStudio/full_demo/RegTest.S
new file mode 100644
index 0000000..0a5e544
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/full_demo/RegTest.S
@@ -0,0 +1,262 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	.extern ulRegTest1LoopCounter
+	.extern ulRegTest2LoopCounter
+
+	.global vRegTest1Implementation
+	.global vRegTest2Implementation
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The register check tasks are described in the comments at the top of
+ * main_full.c.
+ */
+
+vRegTest1Implementation:
+
+	/* Fill the core registers with known values. */
+	li x5, 0x5
+	li x6, 0x6
+	li x7, 0x7
+	li x8, 0x8
+	li x9, 0x9
+	li x10, 0xa
+	li x11, 0xb
+	li x12, 0xc
+	li x13, 0xd
+	li x14, 0xe
+	li x15, 0xf
+	li x16, 0x10
+	li x17, 0x11
+	li x18, 0x12
+	li x19, 0x13
+	li x20, 0x14
+	li x21, 0x15
+	li x22, 0x16
+	li x23, 0x17
+	li x24, 0x18
+	li x25, 0x19
+	li x26, 0x1a
+	li x27, 0x1b
+	li x28, 0x1c
+	li x29, 0x1d
+	li x30, 0x1e
+
+reg1_loop:
+
+	/* Check each register still contains the expected known value.
+	vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation
+	uses x5 as the temporary. */
+	li x31, 0x5
+	bne x31, x5, reg1_error_loop
+	li x31, 0x6
+	bne x31, x6, reg1_error_loop
+	li x31, 0x7
+	bne x31, x7, reg1_error_loop
+	li x31, 0x8
+	bne x31, x8, reg1_error_loop
+	li x31, 0x9
+	bne x31, x9, reg1_error_loop
+	li x31, 0xa
+	bne x31, x10, reg1_error_loop
+	li x31, 0xb
+	bne x31, x11, reg1_error_loop
+	li x31, 0xc
+	bne x31, x12, reg1_error_loop
+	li x31, 0xd
+	bne x31, x13, reg1_error_loop
+	li x31, 0xe
+	bne x31, x14, reg1_error_loop
+	li x31, 0xf
+	bne x31, x15, reg1_error_loop
+	li x31, 0x10
+	bne x31, x16, reg1_error_loop
+	li x31, 0x11
+	bne x31, x17, reg1_error_loop
+	li x31, 0x12
+	bne x31, x18, reg1_error_loop
+	li x31, 0x13
+	bne x31, x19, reg1_error_loop
+	li x31, 0x14
+	bne x31, x20, reg1_error_loop
+	li x31, 0x15
+	bne x31, x21, reg1_error_loop
+	li x31, 0x16
+	bne x31, x22, reg1_error_loop
+	li x31, 0x17
+	bne x31, x23, reg1_error_loop
+	li x31, 0x18
+	bne x31, x24, reg1_error_loop
+	li x31, 0x19
+	bne x31, x25, reg1_error_loop
+	li x31, 0x1a
+	bne x31, x26, reg1_error_loop
+	li x31, 0x1b
+	bne x31, x27, reg1_error_loop
+	li x31, 0x1c
+	bne x31, x28, reg1_error_loop
+	li x31, 0x1d
+	bne x31, x29, reg1_error_loop
+	li x31, 0x1e
+	bne x31, x30, reg1_error_loop
+
+	/* Everything passed, increment the loop counter. */
+	lw x31, ulRegTest1LoopCounterConst
+	lw x30, 0(x31)
+	addi x30, x30, 1
+	sw x30, 0(x31)
+
+	/* Restore clobbered register reading for next loop. */
+	li x30, 0x1e
+
+	/* Yield to increase code coverage. */
+	ecall
+
+	/* Start again. */
+	jal reg1_loop
+
+reg1_error_loop:
+	/* Jump here if a register contains an uxpected value.  This stops the loop
+	counter being incremented so the check task knows an error was found. */
+//	ebreak
+	jal reg1_error_loop
+
+ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter
+
+/*-----------------------------------------------------------*/
+
+vRegTest2Implementation:
+
+	/* Fill the core registers with known values. */
+	li x6, 0x61
+	li x7, 0x71
+	li x8, 0x81
+	li x9, 0x91
+	li x10, 0xa1
+	li x11, 0xb1
+	li x12, 0xc1
+	li x13, 0xd1
+	li x14, 0xe1
+	li x15, 0xf1
+	li x16, 0x20
+	li x17, 0x21
+	li x18, 0x22
+	li x19, 0x23
+	li x20, 0x24
+	li x21, 0x25
+	li x22, 0x26
+	li x23, 0x27
+	li x24, 0x28
+	li x25, 0x29
+	li x26, 0x2a
+	li x27, 0x2b
+	li x28, 0x2c
+	li x29, 0x2d
+	li x30, 0x2e
+	li x31, 0x2f
+
+Reg2_loop:
+
+	/* Check each register still contains the expected known value.
+	vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation
+	uses x31 as the temporary. */
+	li x5, 0x61
+	bne x5, x6, reg2_error_loop
+	li x5, 0x71
+	bne x5, x7, reg2_error_loop
+	li x5, 0x81
+	bne x5, x8, reg2_error_loop
+	li x5, 0x91
+	bne x5, x9, reg2_error_loop
+	li x5, 0xa1
+	bne x5, x10, reg2_error_loop
+	li x5, 0xb1
+	bne x5, x11, reg2_error_loop
+	li x5, 0xc1
+	bne x5, x12, reg2_error_loop
+	li x5, 0xd1
+	bne x5, x13, reg2_error_loop
+	li x5, 0xe1
+	bne x5, x14, reg2_error_loop
+	li x5, 0xf1
+	bne x5, x15, reg2_error_loop
+	li x5, 0x20
+	bne x5, x16, reg2_error_loop
+	li x5, 0x21
+	bne x5, x17, reg2_error_loop
+	li x5, 0x22
+	bne x5, x18, reg2_error_loop
+	li x5, 0x23
+	bne x5, x19, reg2_error_loop
+	li x5, 0x24
+	bne x5, x20, reg2_error_loop
+	li x5, 0x25
+	bne x5, x21, reg2_error_loop
+	li x5, 0x26
+	bne x5, x22, reg2_error_loop
+	li x5, 0x27
+	bne x5, x23, reg2_error_loop
+	li x5, 0x28
+	bne x5, x24, reg2_error_loop
+	li x5, 0x29
+	bne x5, x25, reg2_error_loop
+	li x5, 0x2a
+	bne x5, x26, reg2_error_loop
+	li x5, 0x2b
+	bne x5, x27, reg2_error_loop
+	li x5, 0x2c
+	bne x5, x28, reg2_error_loop
+	li x5, 0x2d
+	bne x5, x29, reg2_error_loop
+	li x5, 0x2e
+	bne x5, x30, reg2_error_loop
+	li x5, 0x2f
+	bne x5, x31, reg2_error_loop
+
+	/* Everything passed, increment the loop counter. */
+	lw x5, ulRegTest2LoopCounterConst
+	lw x6, 0(x5)
+	addi x6, x6, 1
+	sw x6, 0(x5)
+
+	/* Restore clobbered register reading for next loop. */
+	li x6, 0x61
+
+	/* Start again. */
+	jal Reg2_loop
+
+reg2_error_loop:
+	/* Jump here if a register contains an uxpected value.  This stops the loop
+	counter being incremented so the check task knows an error was found. */
+//	ebreak
+	jal reg2_error_loop
+
+ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter
+
+
diff --git a/RISC-V-HiFive1_e-FreedomStudio/full_demo/main_full.c b/RISC-V-HiFive1_e-FreedomStudio/full_demo/main_full.c
new file mode 100644
index 0000000..bd79bcb
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/full_demo/main_full.c
@@ -0,0 +1,320 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/******************************************************************************
+ * NOTE 1:  This project provides two demo applications.  A simple blinky style
+ * project, and a more comprehensive test and demo application.  The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
+ * between the two.  See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
+ * in main.c.  This file implements the comprehensive test and demo version.
+ *
+ * NOTE 2:  This file only contains the source code that is specific to the
+ * full demo.  Generic functions, such FreeRTOS hook functions, and functions
+ * required to configure the hardware, are defined in main.c.
+ *
+ ******************************************************************************
+ *
+ * main_full() creates all the demo application tasks and software timers, then
+ * starts the scheduler.  The web documentation provides more details of the
+ * standard demo application tasks, which provide no particular functionality,
+ * but do provide a good example of how to use the FreeRTOS API.
+ *
+ * In addition to the standard demo tasks, the following tasks and tests are
+ * defined and/or created within this file:
+ *
+ * "Reg test" tasks - These fill both the core registers with known values, then
+ * check that each register maintains its expected value for the lifetime of the
+ * task.  Each task uses a different set of values.  The reg test tasks execute
+ * with a very low priority, so get preempted very frequently.  A register
+ * containing an unexpected value is indicative of an error in the context
+ * switching mechanism.
+ *
+ * "Check" task - The check executes every five seconds.  It checks that all
+ * the standard demo tasks, and the register check tasks, are not only still
+ * executing, but are executing without reporting any errors.  If the check task
+ * discovers that a task has either stalled, or reported an error, then it
+ * prints an error message to the UART, otherwise it prints "Pass" followed
+ * by an additional period (".") after each successful loop of its implementing
+ * function.
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "semphr.h"
+
+/* Standard demo application includes. */
+#include "dynamic.h"
+#include "blocktim.h"
+#include "GenQTest.h"
+#include "recmutex.h"
+#include "TimerDemo.h"
+#include "EventGroupsDemo.h"
+#include "TaskNotify.h"
+
+/* SiFive includes. */
+#include "platform.h"
+#include "encoding.h"
+#include "unistd.h"
+
+/* Priorities for the demo application tasks. */
+#define mainCHECK_TASK_PRIORITY				( configMAX_PRIORITIES - 1 )
+
+/* The period of the check task, in ms, converted to ticks using the
+pdMS_TO_TICKS() macro. */
+#define mainNO_ERROR_CHECK_TASK_PERIOD		pdMS_TO_TICKS( 5000UL )
+
+/* Parameters that are passed into the register check tasks solely for the
+purpose of ensuring parameters are passed into tasks correctl5. */
+#define mainREG_TEST_TASK_1_PARAMETER		( ( void * ) 0x12345678 )
+#define mainREG_TEST_TASK_2_PARAMETER		( ( void * ) 0x87654321 )
+
+/* The base period used by the timer test tasks. */
+#define mainTIMER_TEST_PERIOD				( 50 )
+
+/* The size of the stack allocated to the check task (as described in the
+comments at the top of this file. */
+#define mainCHECK_TASK_STACK_SIZE_WORDS 85
+
+/* Size of the stacks to allocated for the register check tasks. */
+#define mainREG_TEST_STACK_SIZE_WORDS 50
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by main() to run the full demo (as opposed to the blinky demo) when
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
+ */
+void main_full( void );
+
+/*
+ * The check task, as described at the top of this file.
+ */
+static void prvCheckTask( void *pvParameters );
+
+/*
+ * Register check tasks as described at the top of this file.  The nature of
+ * these files necessitates that they are written in an assembly file, but the
+ * entry points are kept in the C file for the convenience of checking the task
+ * parameter.
+ */
+static void prvRegTestTaskEntry1( void *pvParameters );
+extern void vRegTest1Implementation( void );
+static void prvRegTestTaskEntry2( void *pvParameters );
+extern void vRegTest2Implementation( void );
+
+/*
+ * Tick hook used by the full demo, which includes code that interacts with
+ * some of the tests.
+ */
+void vFullDemoTickHook( void );
+
+/*-----------------------------------------------------------*/
+
+/* The following two variables are used to communicate the status of the
+register check tasks to the check task.  If the variables keep incrementing,
+then the register check tasks have not discovered any errors.  If a variable
+stops incrementing, then an error has been found. */
+volatile uint32_t ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
+
+/*-----------------------------------------------------------*/
+
+void main_full( void )
+{
+	/* Create the register check tasks, as described at the top of this	file.
+	Use xTaskCreateStatic() to create a task using only statically allocated
+	memory. */
+	xTaskCreate( prvRegTestTaskEntry1, 			/* The function that implements the task. */
+				 "Reg1", 						/* The name of the task. */
+				 mainREG_TEST_STACK_SIZE_WORDS, /* Size of stack to allocate for the task - in words not bytes!. */
+				 mainREG_TEST_TASK_1_PARAMETER, /* Parameter passed into the task. */
+				 tskIDLE_PRIORITY, 				/* Priority of the task. */
+				 NULL );						/* Can be used to pass out a handle to the created task. */
+	xTaskCreate( prvRegTestTaskEntry2, "Reg2", mainREG_TEST_STACK_SIZE_WORDS, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL );
+
+	/* Start all the other standard demo/test tasks.  They have no particular
+	functionality, but do demonstrate how to use the FreeRTOS API and test the
+	kernel port. */
+	vStartDynamicPriorityTasks();
+	vCreateBlockTimeTasks();
+	vStartGenericQueueTasks( tskIDLE_PRIORITY );
+	vStartRecursiveMutexTasks();
+	vStartTimerDemoTask( mainTIMER_TEST_PERIOD );
+	vStartEventGroupTasks();
+	vStartTaskNotifyTask();
+
+	/* Create the task that performs the 'check' functionality,	as described at
+	the top of this file. */
+	xTaskCreate( prvCheckTask, "Check", mainCHECK_TASK_STACK_SIZE_WORDS, NULL, mainCHECK_TASK_PRIORITY, NULL );
+
+	/* Start the scheduler. */
+	vTaskStartScheduler();
+
+	/* If all is well, the scheduler will now be running, and the following
+	line will never be reached.  If the following line does execute, then
+	there was insufficient FreeRTOS heap memory available for the Idle and/or
+	timer tasks to be created.  See the memory management section on the
+	FreeRTOS web site for more details on the FreeRTOS heap
+	http://www.freertos.org/a00111.html. */
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTask( void *pvParameters )
+{
+const TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;
+TickType_t xLastExecutionTime;
+static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
+const char * const pcPassMessage = "Pass";
+const char * pcStatusMessage = ".";
+
+	/* Just to stop compiler warnings. */
+	( void ) pvParameters;
+
+	write( STDOUT_FILENO, pcPassMessage, strlen( pcPassMessage ) );
+
+	/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
+	works correctly. */
+	xLastExecutionTime = xTaskGetTickCount();
+
+	/* Cycle for ever, delaying then checking all the other tasks are still
+	operating without error.  The onboard LED is toggled on each iteration.
+	If an error is detected then the delay period is decreased from
+	mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD.  This has the
+	effect of increasing the rate at which the onboard LED toggles, and in so
+	doing gives visual feedback of the system status. */
+	for( ;; )
+	{
+		/* Delay until it is time to execute again. */
+		vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );
+
+		/* Check all the demo tasks (other than the flash tasks) to ensure
+		that they are all still running, and that none have detected an error. */
+		if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
+		{
+			pcStatusMessage = "ERROR: Dynamic priority demo/tests.\r\n";
+		}
+
+		if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
+		{
+			pcStatusMessage = "ERROR: Block time demo/tests.\r\n";
+		}
+
+		if ( xAreGenericQueueTasksStillRunning() != pdTRUE )
+		{
+			pcStatusMessage = "ERROR: Generic queue demo/tests.\r\n";
+		}
+
+		if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
+		{
+			pcStatusMessage = "ERROR: Recursive mutex demo/tests.\r\n";
+		}
+
+		if( xAreTimerDemoTasksStillRunning( ( TickType_t ) xDelayPeriod ) != pdPASS )
+		{
+			pcStatusMessage = "ERROR: Timer demo/tests.\r\n";
+		}
+
+		if( xAreEventGroupTasksStillRunning() != pdPASS )
+		{
+			pcStatusMessage = "ERROR: Event group demo/tests.\r\n";
+		}
+
+		if( xAreTaskNotificationTasksStillRunning() != pdPASS )
+		{
+			pcStatusMessage = "ERROR: Task notification demo/tests.\r\n";
+		}
+
+		/* Check that the register test 1 task is still running. */
+		if( ulLastRegTest1Value == ulRegTest1LoopCounter )
+		{
+			pcStatusMessage = "ERROR: Register test 1.\r\n";
+		}
+		ulLastRegTest1Value = ulRegTest1LoopCounter;
+
+		/* Check that the register test 2 task is still running. */
+		if( ulLastRegTest2Value == ulRegTest2LoopCounter )
+		{
+			pcStatusMessage = "ERROR: Register test 2.\r\n";
+		}
+		ulLastRegTest2Value = ulRegTest2LoopCounter;
+
+		/* Write the status message to the UART. */
+		write( STDOUT_FILENO, pcStatusMessage, strlen( pcStatusMessage ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTestTaskEntry1( void *pvParameters )
+{
+	/* Although the regtest task is written in assembler, its entry point is
+	written in C for convenience of checking the task parameter is being passed
+	in correctly. */
+	if( pvParameters == mainREG_TEST_TASK_1_PARAMETER )
+	{
+		/* Start the part of the test that is written in assembler. */
+		vRegTest1Implementation();
+	}
+
+	/* The following line will only execute if the task parameter is found to
+	be incorrect.  The check task will detect that the regtest loop counter is
+	not being incremented and flag an error. */
+	vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvRegTestTaskEntry2( void *pvParameters )
+{
+	/* Although the regtest task is written in assembler, its entry point is
+	written in C for convenience of checking the task parameter is being passed
+	in correctly. */
+	if( pvParameters == mainREG_TEST_TASK_2_PARAMETER )
+	{
+		/* Start the part of the test that is written in assembler. */
+		vRegTest2Implementation();
+	}
+
+	/* The following line will only execute if the task parameter is found to
+	be incorrect.  The check task will detect that the regtest loop counter is
+	not being incremented and flag an error. */
+	vTaskDelete( NULL );
+}
+/*-----------------------------------------------------------*/
+
+void vFullDemoTickHook( void )
+{
+	/* Called from vApplicationTickHook() when the project is configured to
+	build the full demo. */
+	vTimerPeriodicISRTests();
+	vPeriodicEventGroupsProcessing();
+	xNotifyTaskFromISR();
+}
diff --git a/RISC-V-HiFive1_e-FreedomStudio/main.c b/RISC-V-HiFive1_e-FreedomStudio/main.c
new file mode 100644
index 0000000..5c82039
--- /dev/null
+++ b/RISC-V-HiFive1_e-FreedomStudio/main.c
@@ -0,0 +1,178 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* FreeRTOS kernel includes. */
+#include 
+#include 
+
+/******************************************************************************
+ * This project provides two demo applications.  A simple blinky style project,
+ * and a more comprehensive test and demo application.  The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to
+ * select between the two.  The simply blinky demo is implemented and described
+ * in main_blinky.c.  The more comprehensive test and demo application is
+ * implemented and described in main_full.c.
+ *
+ * This file implements the code that is not demo specific, including the
+ * hardware setup and standard FreeRTOS hook functions.
+ *
+ * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON
+ * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO
+ * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!
+ *
+ *
+ * NOTE 1:
+ *
+ * This project has only been tested in the QEMU emulation of the HiFive board
+ * from SiFive.
+ *
+ * Start QEMU using the following command line:
+ *
+ * [your_path_1]\qemu-system-riscv32 -kernel [your_path_2]\FreeRTOS\Demo\RISC-V-Qemu-sifive_e-FreedomStudio\Debug\RTOSDemo.elf -S -s -machine sifive_e
+ *
+ * Where [your_path_1] must be replaced with the correct path to your QEMU
+ * installation and the elf file generated by this project respectively.
+ *
+ *
+ * NOTE 2:
+ *
+ * Start GDB using the following command line (this can be entered in the
+ * Eclipse Debug Launch Configuration dialogue):
+ *
+ * riscv64-unknown-elf-gdb.exe -iex "set mem inaccessible-by-default off" -iex "set arch riscv:rv32" -iex "set riscv use_compressed_breakpoint off"
+ *
+ *
+ * Note 3:
+ *
+ * Status information is sent to the QEMU serial console.
+ */
+
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
+or 0 to run the more comprehensive test and demo application. */
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY	1
+
+/*
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
+ */
+#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1
+	extern void main_blinky( void );
+#else
+	extern void main_full( void );
+#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */
+
+/* Prototypes for the standard FreeRTOS callback/hook functions implemented
+within this file.  See https://www.freertos.org/a00016.html */
+void vApplicationMallocFailedHook( void );
+void vApplicationIdleHook( void );
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );
+void vApplicationTickHook( void );
+
+/*-----------------------------------------------------------*/
+
+int main( void )
+{
+	/* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top
+	of this file. */
+	#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )
+	{
+		main_blinky();
+	}
+	#else
+	{
+		main_full();
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationMallocFailedHook( void )
+{
+	/* vApplicationMallocFailedHook() will only be called if
+	configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h.  It is a hook
+	function that will get called if a call to pvPortMalloc() fails.
+	pvPortMalloc() is called internally by the kernel whenever a task, queue,
+	timer or semaphore is created.  It is also called by various parts of the
+	demo application.  If heap_1.c or heap_2.c are used, then the size of the
+	heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
+	FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
+	to query the size of free heap space that remains (although it does not
+	provide information on how the remaining heap might be fragmented). */
+	taskDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+	/* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
+	to 1 in FreeRTOSConfig.h.  It will be called on each iteration of the idle
+	task.  It is essential that code added to this hook function never attempts
+	to block in any way (for example, call xQueueReceive() with a block time
+	specified, or call vTaskDelay()).  If the application makes use of the
+	vTaskDelete() API function (as this demo application does) then it is also
+	important that vApplicationIdleHook() is permitted to return to its calling
+	function, because it is the responsibility of the idle task to clean up
+	memory allocated by the kernel to any task that has since been deleted. */
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
+{
+	( void ) pcTaskName;
+	( void ) pxTask;
+
+	/* Run time stack overflow checking is performed if
+	configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2.  This hook
+	function is called if a stack overflow is detected. */
+	taskDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationTickHook( void )
+{
+	/* The tests in the full demo expect some interaction with interrupts. */
+	#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 )
+	{
+		extern void vFullDemoTickHook( void );
+		vFullDemoTickHook();
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+void vAssertCalled( void )
+{
+volatile uint32_t ulSetTo1ToExitFunction = 0;
+
+	taskDISABLE_INTERRUPTS();
+	while( ulSetTo1ToExitFunction != 1 )
+	{
+		__asm volatile( "NOP" );
+	}
+}

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